From ben at trinity.fluff.org  Tue Jun  1 00:16:33 2010
From: ben at trinity.fluff.org (Ben Dooks)
Date: Tue, 1 Jun 2010 05:16:33 +0100
Subject: [PATCH v2] ARM: S5PV210: Add Power Management Support
In-Reply-To: <AANLkTinNCTUtXDeRTOBi05Yv7FoatY2ruWmnNtTSmg36@mail.gmail.com>
References: <1275356164-7896-1-git-send-email-kgene.kim@samsung.com>
	<20100601020329.GT4720@trinity.fluff.org>
	<AANLkTinNCTUtXDeRTOBi05Yv7FoatY2ruWmnNtTSmg36@mail.gmail.com>
Message-ID: <20100601041633.GB30276@trinity.fluff.org>

On Tue, Jun 01, 2010 at 12:23:39PM +0900, Kyungmin Park wrote:
> On Tue, Jun 1, 2010 at 11:03 AM, Ben Dooks <ben-linux at fluff.org> wrote:
> >
> > On Tue, Jun 01, 2010 at 10:36:04AM +0900, Kukjin Kim wrote:
> >> From: Jongpill Lee <boyko.lee at samsung.com>
> >>
> >> This patch adds suspend-to-ram support for S5PV210.
> >>
> >> Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
> >> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> >> ---
> >> Changes since v1:
> >>
> >> 1. Fixed comments as per comments from Ben Dooks
> >> 2. Removed redunt #if defined(CONFIG_PM)
> >> 3. Removed redunt including header files
> >> 4. Removed <mach/pm.h> and <plat/pm-s5p.h>
> >> 5. Moved 's5pv210_core_save' into machine directory
> >> 6. Moved sleep.S into machine directory for S5P SoCs compatibility
> >> 7. Added CF retension configuration when wake-up
> >>
> >> This patch is based on Linus' master (2.6.35-rc1)
> >>
> >> ?arch/arm/mach-s5pv210/Kconfig ? ? ? ? ? ? ? ? ? | ? ?6 +
> >> ?arch/arm/mach-s5pv210/Makefile ? ? ? ? ? ? ? ? ?| ? ?1 +
> >> ?arch/arm/mach-s5pv210/include/mach/pm-core.h ? ?| ? 44 ++++++
> >> ?arch/arm/mach-s5pv210/include/mach/regs-clock.h | ? ?5 +-
> >> ?arch/arm/mach-s5pv210/mach-smdkc110.c ? ? ? ? ? | ? ?2 +
> >> ?arch/arm/mach-s5pv210/mach-smdkv210.c ? ? ? ? ? | ? ?3 +
> >> ?arch/arm/mach-s5pv210/pm.c ? ? ? ? ? ? ? ? ? ? ?| ?180 +++++++++++++++++++++++
> >> ?arch/arm/mach-s5pv210/sleep.S ? ? ? ? ? ? ? ? ? | ?166 +++++++++++++++++++++
> >> ?arch/arm/plat-s5p/Makefile ? ? ? ? ? ? ? ? ? ? ?| ? ?2 +
> >> ?arch/arm/plat-s5p/include/plat/irqs.h ? ? ? ? ? | ? ?2 +
> >> ?arch/arm/plat-s5p/irq-pm.c ? ? ? ? ? ? ? ? ? ? ?| ?108 ++++++++++++++
> >> ?arch/arm/plat-s5p/pm.c ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 52 +++++++
> >> ?arch/arm/plat-samsung/pm-gpio.c ? ? ? ? ? ? ? ? | ? ?4 +-
> >> ?13 files changed, 572 insertions(+), 3 deletions(-)
> >> ?create mode 100644 arch/arm/mach-s5pv210/include/mach/pm-core.h
> >> ?create mode 100644 arch/arm/mach-s5pv210/pm.c
> >> ?create mode 100644 arch/arm/mach-s5pv210/sleep.S
> >> ?create mode 100644 arch/arm/plat-s5p/irq-pm.c
> >> ?create mode 100644 arch/arm/plat-s5p/pm.c
> >>
> >> diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
> >> index 0761eac..86cca1b 100644
> >> --- a/arch/arm/mach-s5pv210/Kconfig
> >> +++ b/arch/arm/mach-s5pv210/Kconfig
> >> @@ -14,6 +14,7 @@ config CPU_S5PV210
> >> ? ? ? select PLAT_S5P
> >> ? ? ? select S3C_PL330_DMA
> >> ? ? ? select S5P_EXT_INT
> >> + ? ? select S5PV210_PM if PM
> >> ? ? ? help
> >> ? ? ? ? Enable S5PV210 CPU support
> >>
> >> @@ -88,4 +89,9 @@ config MACH_SMDKC110
> >> ? ? ? ? Machine support for Samsung SMDKC110
> >> ? ? ? ? S5PC110(MCP) is one of package option of S5PV210
> >>
> >> +config S5PV210_PM
> >> + ? ? bool
> >> + ? ? help
> >> + ? ? ? Power Management code common to S5PV210
> >> +
> >> ?endif
> >> diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
> >> index 30be9a6..59382ec 100644
> >> --- a/arch/arm/mach-s5pv210/Makefile
> >> +++ b/arch/arm/mach-s5pv210/Makefile
> >> @@ -14,6 +14,7 @@ obj- ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?:=
> >>
> >> ?obj-$(CONFIG_CPU_S5PV210) ? ?+= cpu.o init.o clock.o dma.o gpiolib.o
> >> ?obj-$(CONFIG_CPU_S5PV210) ? ?+= setup-i2c0.o
> >> +obj-$(CONFIG_S5PV210_PM) ? ? += pm.o sleep.o
> >>
> >> ?# machine support
> >>
> >> diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
> >> new file mode 100644
> >> index 0000000..ca3f827
> >> --- /dev/null
> >> +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
> >> @@ -0,0 +1,44 @@
> >> +/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
> >> + *
> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> >> + * ? ? ? ? ? http://www.samsung.com
> >> + *
> >> + * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
> >> + * Copyright 2008 Simtec Electronics
> >> + * ? ? ?Ben Dooks <ben at simtec.co.uk>
> >> + * ? ? ?http://armlinux.simtec.co.uk/
> >> + *
> >> + * S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License version 2 as
> >> + * published by the Free Software Foundation.
> >> +*/
> >> +
> >> +static inline void s3c_pm_debug_init_uart(void)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> +static inline void s3c_pm_arch_prepare_irqs(void)
> >> +{
> >> + ? ? __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
> >> + ? ? __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
> >> +}
> >> +
> >> +static inline void s3c_pm_arch_stop_clocks(void)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> +static inline void s3c_pm_arch_show_resume_irqs(void)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
> >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct pm_uart_save *save)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
> >> index 2a25ab4..f4a443a 100644
> >> --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
> >> +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
> >> @@ -157,8 +157,11 @@
> >> ?#define S5P_SLEEP_CFG_USBOSC_EN ? ? ? ? ? ? ?(1 << 1)
> >>
> >> ?/* OTHERS Resgister */
> >> +#define S5P_OTHERS_RET_IO ? ? ? ? ? ?(1 << 31)
> >> +#define S5P_OTHERS_RET_CF ? ? ? ? ? ?(1 << 30)
> >> +#define S5P_OTHERS_RET_MMC ? ? ? ? ? (1 << 29)
> >> +#define S5P_OTHERS_RET_UART ? ? ? ? ?(1 << 28)
> >> ?#define S5P_OTHERS_USB_SIG_MASK ? ? ? ? ? ? ?(1 << 16)
> >> -#define S5P_OTHERS_MIPI_DPHY_EN ? ? ? ? ? ? ?(1 << 28)
> >>
> >> ?/* MIPI */
> >> ?#define S5P_MIPI_DPHY_EN ? ? ? ? ? ? (3)
> >> diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
> >> index 4c8903c..ebb4832 100644
> >> --- a/arch/arm/mach-s5pv210/mach-smdkc110.c
> >> +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
> >> @@ -25,6 +25,7 @@
> >> ?#include <plat/s5pv210.h>
> >> ?#include <plat/devs.h>
> >> ?#include <plat/cpu.h>
> >> +#include <plat/pm.h>
> >>
> >> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
> >> ?#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | ? ? ? ?\
> >> @@ -86,6 +87,7 @@ static void __init smdkc110_map_io(void)
> >>
> >> ?static void __init smdkc110_machine_init(void)
> >> ?{
> >> + ? ? s3c_pm_init();
> 
> It's common function. Please add it to platform init instead of each board init.

I know Mark Brown would rather this be the case too, but the original intent
was that each board would declare itself to be capable of PM by calling this
function to ensure that any boards which had not been validated or where
simply incapable of suspend/resume did not end up with this enabled.
 
> >> ? ? ? platform_add_devices(smdkc110_devices, ARRAY_SIZE(smdkc110_devices));
> >> ?}
> >>
> >> diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
> >> index 0d46279..ba30b5d 100644
> >> --- a/arch/arm/mach-s5pv210/mach-smdkv210.c
> >> +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
> >> @@ -27,6 +27,7 @@
> >> ?#include <plat/cpu.h>
> >> ?#include <plat/adc.h>
> >> ?#include <plat/ts.h>
> >> +#include <plat/pm.h>
> >>
> >> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
> >> ?#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | ? ? ? ?\
> >> @@ -96,6 +97,8 @@ static void __init smdkv210_map_io(void)
> >>
> >> ?static void __init smdkv210_machine_init(void)
> >> ?{
> >> + ? ? s3c_pm_init();
> >> +
> ditto.
> >> ? ? ? s3c24xx_ts_set_platdata(&s3c_ts_platform);
> >> ? ? ? platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
> >> ?}
> 
> >> diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
> >> new file mode 100644
> >> index 0000000..0690332
> >> --- /dev/null
> >> +++ b/arch/arm/mach-s5pv210/pm.c
> >> @@ -0,0 +1,180 @@
> >> +/* linux/arch/arm/mach-s5pv210/pm.c
> >> + *
> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> >> + * ? ? ? ? ? http://www.samsung.com
> >> + *
> >> + * S5PV210 - Power Management support
> >> + *
> >> + * Based on arch/arm/mach-s3c2410/pm.c
> >> + * Copyright (c) 2006 Simtec Electronics
> >> + * ? Ben Dooks <ben at simtec.co.uk>
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License version 2 as
> >> + * published by the Free Software Foundation.
> >> +*/
> >> +
> >> +#include <linux/init.h>
> >> +#include <linux/suspend.h>
> >> +#include <linux/io.h>
> >> +
> >> +#include <plat/cpu.h>
> >> +#include <plat/pm.h>
> >> +#include <plat/regs-timer.h>
> >> +
> >> +#include <mach/regs-irq.h>
> >> +#include <mach/regs-clock.h>
> >> +
> >> +static struct sleep_save s5pv210_core_save[] = {
> >> + ? ? /* Clock source */
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC0),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC1),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC2),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC3),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC4),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC5),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC6),
> >> +
> >> + ? ? /* Clock source Mask */
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC_MASK0),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC_MASK1),
> >> +
> >> + ? ? /* Clock Divider */
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV0),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV1),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV2),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV3),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV4),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV5),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV6),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV7),
> >> +
> >> + ? ? /* Clock Main Gate */
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_MAIN0),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_MAIN1),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_MAIN2),
> >> +
> >> + ? ? /* Clock source Peri Gate */
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_PERI0),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_PERI1),
> >> +
> >> + ? ? /* Clock source SCLK Gate */
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_SCLK0),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_SCLK1),
> >> +
> >> + ? ? /* Clock IP Clock gate */
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP0),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP1),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP2),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP3),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP4),
> >> +
> >> + ? ? /* Clock Blcok and Bus gate */
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_BLOCK),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_BUS0),
> >> +
> >> + ? ? /* Clock ETC */
> >> + ? ? SAVE_ITEM(S5P_CLK_OUT),
> >> + ? ? SAVE_ITEM(S5P_MDNIE_SEL),
> >> +
> >> + ? ? /* PWM Register */
> >> + ? ? SAVE_ITEM(S3C2410_TCFG0),
> >> + ? ? SAVE_ITEM(S3C2410_TCFG1),
> >> + ? ? SAVE_ITEM(S3C64XX_TINT_CSTAT),
> >> + ? ? SAVE_ITEM(S3C2410_TCON),
> >> + ? ? SAVE_ITEM(S3C2410_TCNTB(0)),
> >> + ? ? SAVE_ITEM(S3C2410_TCMPB(0)),
> >> + ? ? SAVE_ITEM(S3C2410_TCNTO(0)),
> >> +
> >> + ? ? /* VIC 2 and 3*/
> >> + ? ? SAVE_ITEM(VA_VIC2 + VIC_INT_SELECT),
> >> + ? ? SAVE_ITEM(VA_VIC3 + VIC_INT_SELECT),
> >> + ? ? SAVE_ITEM(VA_VIC2 + VIC_INT_ENABLE),
> >> + ? ? SAVE_ITEM(VA_VIC3 + VIC_INT_ENABLE),
> >> + ? ? SAVE_ITEM(VA_VIC2 + VIC_INT_SOFT),
> >> + ? ? SAVE_ITEM(VA_VIC3 + VIC_INT_SOFT),
> >
> > doesn't the vic driver do this for you? if not, then would be better
> > to change the vic to fix this.
> >
> >> +};
> >> +
> >> +void s5pv210_cpu_suspend(void)
> >> +{
> >> + ? ? unsigned long tmp;
> >> +
> >> + ? ? /* issue the standby signal into the pm unit. Note, we
> >> + ? ? ?* issue a write-buffer drain just in case */
> >> +
> >> + ? ? tmp = 0;
> >> +
> >> + ? ? asm("b 1f\n\t"
> >> + ? ? ? ? ".align 5\n\t"
> >> + ? ? ? ? "1:\n\t"
> >> + ? ? ? ? "mcr p15, 0, %0, c7, c10, 5\n\t"
> >> + ? ? ? ? "mcr p15, 0, %0, c7, c10, 4\n\t"
> >> + ? ? ? ? ".word 0xe320f003" : : "r" (tmp));
> >
> > why .word? if there's a compiler problem then make a comment about
> > what instruction is being synthesised and why.
> >
> >> + ? ? /* we should never get past here */
> >> + ? ? panic("sleep resumed to originator?");
> >> +}
> >> +
> >> +static void s5pv210_pm_prepare(void)
> >> +{
> >> + ? ? unsigned int tmp;
> >> +
> >> + ? ? /* ensure at least INFORM0 has the resume address */
> >> + ? ? __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
> >> +
> >> + ? ? tmp = __raw_readl(S5P_SLEEP_CFG);
> >> + ? ? tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
> >> + ? ? __raw_writel(tmp, S5P_SLEEP_CFG);
> >> +
> >> + ? ? /* WFI for SLEEP mode configuration by SYSCON */
> >> + ? ? tmp = __raw_readl(S5P_PWR_CFG);
> >> + ? ? tmp &= S5P_CFG_WFI_CLEAN;
> 
> CLEAN? just use the MASK and use common mask operation. tmp &=
> ~S5P_CFG_WFI_MASK;
> 
> >> + ? ? tmp |= S5P_CFG_WFI_SLEEP;
> >> + ? ? __raw_writel(tmp, S5P_PWR_CFG);
> >> +
> >> + ? ? /* SYSCON interrupt handling disable */
> >> + ? ? tmp = __raw_readl(S5P_OTHERS);
> >> + ? ? tmp |= S5P_OTHER_SYSC_INTOFF;
> >> + ? ? __raw_writel(tmp, S5P_OTHERS);
> >> +
> >> + ? ? __raw_writel(0xffffffff, (VA_VIC0 + VIC_INT_ENABLE_CLEAR));
> >> + ? ? __raw_writel(0xffffffff, (VA_VIC1 + VIC_INT_ENABLE_CLEAR));
> >> + ? ? __raw_writel(0xffffffff, (VA_VIC2 + VIC_INT_ENABLE_CLEAR));
> >> + ? ? __raw_writel(0xffffffff, (VA_VIC3 + VIC_INT_ENABLE_CLEAR));
> >> +
> >> + ? ? s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
> >> +}
> >> +
> >> +static int s5pv210_pm_add(struct sys_device *sysdev)
> >> +{
> >> + ? ? pm_cpu_prep = s5pv210_pm_prepare;
> >> + ? ? pm_cpu_sleep = s5pv210_cpu_suspend;
> >> +
> >> + ? ? return 0;
> >> +}
> >> +
> >> +static int s5pv210_pm_resume(struct sys_device *dev)
> >> +{
> >> + ? ? u32 tmp;
> >> +
> >> + ? ? tmp = __raw_readl(S5P_OTHERS);
> >> + ? ? tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | \
> >> + ? ? ? ? ? ? S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART);
> >> + ? ? __raw_writel(tmp , S5P_OTHERS);
> >> +
> >> + ? ? s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
> >> +
> >> + ? ? return 0;
> >> +}
> >> +
> >> +static struct sysdev_driver s5pv210_pm_driver = {
> >> + ? ? .add ? ? ? ? ? ?= s5pv210_pm_add,
> >> + ? ? .resume ? ? ? ? = s5pv210_pm_resume,
> >> +};
> >> +
> >> +static __init int s5pv210_pm_drvinit(void)
> >> +{
> >> + ? ? return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver);
> >> +}
> >> +arch_initcall(s5pv210_pm_drvinit);
> >> diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
> >> new file mode 100644
> >> index 0000000..b7f8272
> >> --- /dev/null
> >> +++ b/arch/arm/mach-s5pv210/sleep.S
> >> @@ -0,0 +1,166 @@
> >> +/* linux/arch/arm/mach-s5pv210/sleep.S
> >> + *
> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> >> + * ? ? ? ? ? http://www.samsung.com
> >> + *
> >> + * S5PV210 power Manager (Suspend-To-RAM) support
> >> + *
> >> + * Based on S3C2410 sleep code by:
> >> + * ? Ben Dooks, (c) 2004 Simtec Electronics
> >> + *
> >> + * Based on PXA/SA1100 sleep code by:
> >> + * ? Nicolas Pitre, (c) 2002 Monta Vista Software Inc
> >> + * ? Cliff Brake, (c) 2001
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License as published by
> >> + * the Free Software Foundation; either version 2 of the License, or
> >> + * (at your option) any later version.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> >> + * GNU General Public License for more details.
> >> + *
> >> + * You should have received a copy of the GNU General Public License
> >> + * along with this program; if not, write to the Free Software
> >> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA ?02111-1307 ?USA
> >> +*/
> >> +
> >> +#include <linux/linkage.h>
> >> +#include <asm/assembler.h>
> >> +#include <asm/memory.h>
> >> +
> >> + ? ? .text
> >> +
> >> + ? ? /* s3c_cpu_save
> >> + ? ? ?*
> >> + ? ? ?* entry:
> >> + ? ? ?* ? ? ?r0 = save address (virtual addr of s3c_sleep_save_phys)
> >> + ? ? */
> >> +
> >> +ENTRY(s3c_cpu_save)
> >> +
> >> + ? ? stmfd ? sp!, { r3 - r12, lr }
> >> +
> >> + ? ? mrc ? ? p15, 0, r4, c13, c0, 0 ?@ FCSE/PID
> >> + ? ? mrc ? ? p15, 0, r5, c3, c0, 0 ? @ Domain ID
> >> + ? ? mrc ? ? p15, 0, r6, c2, c0, 0 ? @ Translation Table BASE0
> >> + ? ? mrc ? ? p15, 0, r7, c2, c0, 1 ? @ Translation Table BASE1
> >> + ? ? mrc ? ? p15, 0, r8, c2, c0, 2 ? @ Translation Table Control
> >> + ? ? mrc ? ? p15, 0, r9, c1, c0, 0 ? @ Control register
> >> + ? ? mrc ? ? p15, 0, r10, c1, c0, 1 ?@ Auxiliary control register
> >> + ? ? mrc ? ? p15, 0, r11, c1, c0, 2 ?@ Co-processor access controls
> >> + ? ? mrc ? ? p15, 0, r12, c10, c2, 0 @ Read PRRR
> >> + ? ? mrc ? ? p15, 0, r3, c10, c2, 1 ?@ READ NMRR
> >> +
> >> + ? ? stmia ? r0, { r3 - r13 }
> >> +
> >> + ? ? bl ? ? ?s3c_pm_cb_flushcache
> >> +
> >> + ? ? ldr ? ? r0, =pm_cpu_sleep
> >> + ? ? ldr ? ? r0, [ r0 ]
> >> + ? ? mov ? ? pc, r0
> >> +
> >> +resume_with_mmu:
> >> + ? ? /* delete added mmu table list */
> >
> > hmm, where is this being added?
> > also, a better description on what it is doing would be better.
> >
> >> + ? ? ldr ? ? r9 , =(PAGE_OFFSET - PHYS_OFFSET)
> >> + ? ? add ? ? r4, r4, r9
> >> + ? ? str ? ? r12, [r4]
> >> +
> >> + ? ? ldmfd ? sp!, { r3 - r12, pc }
> >> +
> >> + ? ? .ltorg
> >> +
> >> + ? ? .data
> >> +
> >> + ? ? .global s3c_sleep_save_phys
> >> +s3c_sleep_save_phys:
> >> + ? ? .word ? 0
> >> +
> >> + ? ? /* sleep magic, to allow the bootloader to check for an valid
> >> + ? ? ?* image to resume to. Must be the first word before the
> >> + ? ? ?* s3c_cpu_resume entry.
> >> + ? ? */
> >> +
> >> + ? ? .word ? 0x2bedf00d
> >> +
> >> + ? ? /* s3c_cpu_resume
> >> + ? ? ?*
> >> + ? ? ?* resume code entry for bootloader to call
> >> + ? ? ?*
> >> + ? ? ?* we must put this code here in the data segment as we have no
> >> + ? ? ?* other way of restoring the stack pointer after sleep, and we
> >> + ? ? ?* must not write to the code segment (code is read-only)
> >> + ? ? */
> >> +
> >> +ENTRY(s3c_cpu_resume)
> >> + ? ? mov ? ? r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
> >> + ? ? msr ? ? cpsr_c, r0
> >> +
> >> + ? ? mov ? ? r1, #0
> >> + ? ? mcr ? ? p15, 0, r1, c8, c7, 0 ? ? ? ? ? @@ invalidate TLBs
> >> + ? ? mcr ? ? p15, 0, r1, c7, c5, 0 ? ? ? ? ? @@ invalidate I Cache
> >> +
> >> + ? ? ldr ? ? r0, s3c_sleep_save_phys ? ? ? ? @ address of restore block
> >> + ? ? ldmia ? r0, { r3 - r13 }
> >> +
> >> + ? ? mcr ? ? p15, 0, r4, c13, c0, 0 ? ? ? ? ?@ FCSE/PID
> >> + ? ? mcr ? ? p15, 0, r5, c3, c0, 0 ? ? ? ? ? @ Domain ID
> >> +
> >> + ? ? mcr ? ? p15, 0, r8, c2, c0, 2 ? ? ? ? ? @ Translation Table Control
> >> + ? ? mcr ? ? p15, 0, r7, c2, c0, 1 ? ? ? ? ? @ Translation Table BASE1
> >> + ? ? mcr ? ? p15, 0, r6, c2, c0, 0 ? ? ? ? ? @ Translation Table BASE0
> >> +
> >> + ? ? mcr ? ? p15, 0, r10, c1, c0, 1 ? ? ? ? ?@ Auxiliary control register
> >> +
> >> + ? ? mov ? ? r0, #0
> >> + ? ? mcr ? ? p15, 0, r0, c8, c7, 0 ? ? ? ? ? @ Invalidate I & D TLB
> >> +
> >> + ? ? mov ? ? r0, #0 ? ? ? ? ? ? ? ? ? ? ? ? ?@ restore copro access
> >> + ? ? mcr ? ? p15, 0, r11, c1, c0, 2 ? ? ? ? ?@ Co-processor access
> >> + ? ? mcr ? ? p15, 0, r0, c7, c5, 4
> >> +
> >> + ? ? mcr ? ? p15, 0, r12, c10, c2, 0 ? ? ? ? @ write PRRR
> >> + ? ? mcr ? ? p15, 0, r3, c10, c2, 1 ? ? ? ? ?@ write NMRR
> >> +
> >> + ? ? /* Calculate first section address into r8
> >> + ? ? ?* In Cotex-A8 case, When MMU turn on, MMU is reseted.
> >
> > i'd fix this typo.
> >
> >> + ? ? ?* So, before call resume_with_mmu, backup originally data.
> >> + ? ? */
> >> +
> >> + ? ? mov ? ? r4, r6
> >> + ? ? mov ? ? r4, r4, LSR #14
> >> + ? ? mov ? ? r4, r4, LSL #14
> >> +
> >> + ? ? /* Load TLB Base address from INFORM0 */
> >
> > do you mean mmu page table?
> >
> >> + ? ? ldr ? ? r11, =0xe010f000
> >> + ? ? ldr ? ? r10, [r11, #0]
> >> + ? ? mov ? ? r10, r10, LSR #18
> >> + ? ? bic ? ? r10, r10, #0x3
> >> + ? ? orr ? ? r4, r4, r10
> >> +
> >> + ? ? /* calculate mmu list value into r9 */
> >> + ? ? mov ? ? r10, r10, LSL #18
> >> + ? ? ldr ? ? r5, =0x40e
> >> + ? ? orr ? ? r10, r10, r5
> 
> r10 is correct register? in the above it used the r9 register.
> 
> >> +
> >> + ? ? /* back up originally data */
> >> +
> >> + ? ? ldr ? ? r12, [r4]
> >> +
> >> + ? ? /* Added list about mmu */
> >> + ? ? str ? ? r10, [r4]
> >
> >
> >
> >> + ? ? ldr ? ? r2, =resume_with_mmu
> >> + ? ? mcr ? ? p15, 0, r9, c1, c0, 0 ? ? ? ? ? @ turn on MMU, etc
> >> +
> >> + ? ? nop
> >> + ? ? nop
> >> + ? ? nop
> >> + ? ? nop
> >> + ? ? nop ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ second-to-last before mmu
> >> +
> >> + ? ? mov ? ? pc, r2 ? ? ? ? ? ? ? ? ? ? ? ? ?@ go back to virtual address
> >> +
> >> + ? ? .ltorg
> >> diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
> >> index 39c242b..d04ae49 100644
> >> --- a/arch/arm/plat-s5p/Makefile
> >> +++ b/arch/arm/plat-s5p/Makefile
> >> @@ -18,3 +18,5 @@ obj-y ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += clock.o
> >> ?obj-y ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?+= irq.o
> >> ?obj-$(CONFIG_S5P_EXT_INT) ? ?+= irq-eint.o
> >>
> >> +obj-$(CONFIG_PM) ? ? ? ? ? ? += pm.o
> >> +obj-$(CONFIG_PM) ? ? ? ? ? ? += irq-pm.o
> >> diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
> >> index 3fb3a3a..9ffdd62 100644
> >> --- a/arch/arm/plat-s5p/include/plat/irqs.h
> >> +++ b/arch/arm/plat-s5p/include/plat/irqs.h
> >> @@ -94,4 +94,6 @@
> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ((irq) - S5P_EINT_BASE1) : \
> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ((irq) + 16 - S5P_EINT_BASE2))
> >>
> >> +#define IRQ_EINT_BIT(x) ? ? ? ? ? ? ?EINT_OFFSET(x)
> >> +
> >> ?#endif /* __ASM_PLAT_S5P_IRQS_H */
> >> diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
> >> new file mode 100644
> >> index 0000000..03e83a3
> >> --- /dev/null
> >> +++ b/arch/arm/plat-s5p/irq-pm.c
> >> @@ -0,0 +1,108 @@
> >> +/* linux/arch/arm/plat-s5p/irq-pm.c
> >> + *
> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> >> + * ? ? ? ? ? http://www.samsung.com
> >> + *
> >> + * Based on arch/arm/plat-s3c24xx/irq-pm.c,
> >> + * Copyright (c) 2003,2004 Simtec Electronics
> >> + * ? Ben Dooks <ben at simtec.co.uk>
> >> + * ? http://armlinux.simtec.co.uk/
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License version 2 as
> >> + * published by the Free Software Foundation.
> >> +*/
> >> +
> >> +#include <linux/init.h>
> >> +#include <linux/module.h>
> >> +#include <linux/interrupt.h>
> >> +#include <linux/sysdev.h>
> >> +
> >> +#include <plat/cpu.h>
> >> +#include <plat/irqs.h>
> >> +#include <plat/pm.h>
> >> +#include <mach/map.h>
> >> +
> >> +#include <mach/regs-gpio.h>
> >> +#include <mach/regs-irq.h>
> >> +
> >> +/* state for IRQs over sleep */
> >> +
> >> +/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
> >> + * as wakeup sources
> >> + *
> >> + * set bit to 1 in allow bitfield to enable the wakeup settings on it
> >> +*/
> >> +
> >> +unsigned long s3c_irqwake_intallow ? = 0x00000006L;
> >> +unsigned long s3c_irqwake_eintallow ?= 0xffffffffL;
> >> +
> >> +int s3c_irq_wake(unsigned int irqno, unsigned int state)
> >> +{
> >> + ? ? unsigned long irqbit;
> >> +
> >> + ? ? switch (irqno) {
> >> + ? ? case IRQ_RTC_TIC:
> >> + ? ? case IRQ_RTC_ALARM:
> >> + ? ? ? ? ? ? irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM);
> >> + ? ? ? ? ? ? if (!state)
> >> + ? ? ? ? ? ? ? ? ? ? s3c_irqwake_intmask |= irqbit;
> >> + ? ? ? ? ? ? else
> >> + ? ? ? ? ? ? ? ? ? ? s3c_irqwake_intmask &= ~irqbit;
> >> + ? ? ? ? ? ? break;
> >> + ? ? default:
> >> + ? ? ? ? ? ? return -ENOENT;
> >> + ? ? }
> >> + ? ? return 0;
> >> +}
> >> +
> >> +/* this lot should be really saved by the IRQ code */
> >> +/* VICXADDRESSXX initilaization to be needed */
> >> +static struct sleep_save irq_save[] = {
> >> + ? ? SAVE_ITEM(VA_VIC0 + VIC_INT_SELECT),
> >> + ? ? SAVE_ITEM(VA_VIC1 + VIC_INT_SELECT),
> >> +
> >> + ? ? SAVE_ITEM(VA_VIC0 + VIC_INT_ENABLE),
> >> + ? ? SAVE_ITEM(VA_VIC1 + VIC_INT_ENABLE),
> >> +
> >> + ? ? SAVE_ITEM(VA_VIC0 + VIC_INT_SOFT),
> >> + ? ? SAVE_ITEM(VA_VIC1 + VIC_INT_SOFT),
> >> +};
> >> +
> >> +static struct sleep_save eint_save[] = {
> >> + ? ? SAVE_ITEM(S5P_EINT_CON(0)),
> >> + ? ? SAVE_ITEM(S5P_EINT_CON(1)),
> >> + ? ? SAVE_ITEM(S5P_EINT_CON(2)),
> >> + ? ? SAVE_ITEM(S5P_EINT_CON(3)),
> >> +
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(0)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(1)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(2)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(3)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(4)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(5)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(6)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(7)),
> >> +
> >> + ? ? SAVE_ITEM(S5P_EINT_MASK(0)),
> >> + ? ? SAVE_ITEM(S5P_EINT_MASK(1)),
> >> + ? ? SAVE_ITEM(S5P_EINT_MASK(2)),
> >> + ? ? SAVE_ITEM(S5P_EINT_MASK(3)),
> >> +};
> >> +
> >> +int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
> >> +{
> >> + ? ? s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
> >> + ? ? s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
> >> +
> >> + ? ? return 0;
> >> +}
> >> +
> >> +int s3c24xx_irq_resume(struct sys_device *dev)
> >> +{
> >> + ? ? s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
> >> + ? ? s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
> >> +
> >> + ? ? return 0;
> >> +}
> >> +
> >> diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-s5p/pm.c
> >> new file mode 100644
> >> index 0000000..d592b63
> >> --- /dev/null
> >> +++ b/arch/arm/plat-s5p/pm.c
> >> @@ -0,0 +1,52 @@
> >> +/* linux/arch/arm/plat-s5p/pm.c
> >> + *
> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> >> + * ? ? ? ? ? http://www.samsung.com
> >> + *
> >> + * S5P Power Manager (Suspend-To-RAM) support
> >> + *
> >> + * Based on arch/arm/plat-s3c24xx/pm.c
> >> + * Copyright (c) 2004,2006 Simtec Electronics
> >> + * ? Ben Dooks <ben at simtec.co.uk>
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License version 2 as
> >> + * published by the Free Software Foundation.
> >> +*/
> >> +
> >> +#include <linux/suspend.h>
> >> +#include <plat/pm.h>
> >> +
> >> +#define PFX "s5p pm: "
> >> +
> >> +/* s3c_pm_check_resume_pin
> >> + *
> >> + * check to see if the pin is configured correctly for sleep mode, and
> >> + * make any necessary adjustments if it is not
> >> +*/
> >> +
> >> +static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> +/* s3c_pm_configure_extint
> >> + *
> >> + * configure all external interrupt pins
> >> +*/
> >> +
> >> +void s3c_pm_configure_extint(void)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> +void s3c_pm_restore_core(void)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> +void s3c_pm_save_core(void)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
> >> index 7df03f8..9652820 100644
> >> --- a/arch/arm/plat-samsung/pm-gpio.c
> >> +++ b/arch/arm/plat-samsung/pm-gpio.c
> >> @@ -192,7 +192,7 @@ struct s3c_gpio_pm s3c_gpio_pm_2bit = {
> >> ? ? ? .resume = s3c_gpio_pm_2bit_resume,
> >> ?};
> >>
> >> -#ifdef CONFIG_ARCH_S3C64XX
> >> +#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
> >> ?static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
> >> ?{
> >> ? ? ? chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
> >> @@ -302,7 +302,7 @@ struct s3c_gpio_pm s3c_gpio_pm_4bit = {
> >> ? ? ? .save ? = s3c_gpio_pm_4bit_save,
> >> ? ? ? .resume = s3c_gpio_pm_4bit_resume,
> >> ?};
> >> -#endif /* CONFIG_ARCH_S3C64XX */
> >> +#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
> >>
> >> ?/**
> >> ? * s3c_pm_save_gpio() - save gpio chip data for suspend
> >> --
> >> 1.6.2.5
> >>
> >
> >
> > --
> > --
> > Ben
> >
> > Q: ? ? ?What's a light-year?
> > A: ? ? ?One-third less calories than a regular year.
> >
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at ?http://vger.kernel.org/majordomo-info.html
> >
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From ben at trinity.fluff.org  Tue Jun  1 00:17:13 2010
From: ben at trinity.fluff.org (Ben Dooks)
Date: Tue, 1 Jun 2010 05:17:13 +0100
Subject: [PATCH 2/6] s3c-fb: Correct FRAMESEL1 bitfield defines for
	VIDINTCON0 register
In-Reply-To: <1275296935-2693-3-git-send-email-p.osciak@samsung.com>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
	<1275296935-2693-3-git-send-email-p.osciak@samsung.com>
Message-ID: <20100601041713.GC30276@trinity.fluff.org>

On Mon, May 31, 2010 at 11:08:51AM +0200, Pawel Osciak wrote:
> FRAMESEL1 bitfield starts on 13th bit, not on 14th.

is this true for all variants that have FRAMESEL1?
 
> Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/plat-samsung/include/plat/regs-fb.h |   10 +++++-----
>  1 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
> index f4259e5..ac10013 100644
> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> @@ -292,11 +292,11 @@
>  #define VIDINTCON0_FRAMESEL0_ACTIVE		(0x2 << 15)
>  #define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)
>  
> -#define VIDINTCON0_FRAMESEL1			(1 << 14)
> -#define VIDINTCON0_FRAMESEL1_NONE		(0x0 << 14)
> -#define VIDINTCON0_FRAMESEL1_BACKPORCH		(0x1 << 14)
> -#define VIDINTCON0_FRAMESEL1_VSYNC		(0x2 << 14)
> -#define VIDINTCON0_FRAMESEL1_FRONTPORCH		(0x3 << 14)
> +#define VIDINTCON0_FRAMESEL1			(1 << 13)
> +#define VIDINTCON0_FRAMESEL1_NONE		(0x0 << 13)
> +#define VIDINTCON0_FRAMESEL1_BACKPORCH		(0x1 << 13)
> +#define VIDINTCON0_FRAMESEL1_VSYNC		(0x2 << 13)
> +#define VIDINTCON0_FRAMESEL1_FRONTPORCH		(0x3 << 13)
>  
>  #define VIDINTCON0_INT_FRAME			(1 << 12)
>  #define VIDINTCON0_FIFIOSEL_MASK		(0x7f << 5)
> -- 
> 1.7.0.4
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From kmpark at infradead.org  Tue Jun  1 00:21:26 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Tue, 1 Jun 2010 13:21:26 +0900
Subject: [PATCH v2] ARM: S5PV210: Add Power Management Support
In-Reply-To: <20100601041633.GB30276@trinity.fluff.org>
References: <1275356164-7896-1-git-send-email-kgene.kim@samsung.com>
	<20100601020329.GT4720@trinity.fluff.org>
	<AANLkTinNCTUtXDeRTOBi05Yv7FoatY2ruWmnNtTSmg36@mail.gmail.com>
	<20100601041633.GB30276@trinity.fluff.org>
Message-ID: <AANLkTilCpndcOYjJ4mlMoy45a_FdR6T8kHR3iP-SfuKk@mail.gmail.com>

On Tue, Jun 1, 2010 at 1:16 PM, Ben Dooks <ben at trinity.fluff.org> wrote:
> On Tue, Jun 01, 2010 at 12:23:39PM +0900, Kyungmin Park wrote:
>> On Tue, Jun 1, 2010 at 11:03 AM, Ben Dooks <ben-linux at fluff.org> wrote:
>> >
>> > On Tue, Jun 01, 2010 at 10:36:04AM +0900, Kukjin Kim wrote:
>> >> From: Jongpill Lee <boyko.lee at samsung.com>
>> >>
>> >> This patch adds suspend-to-ram support for S5PV210.
>> >>
>> >> Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
>> >> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
>> >> ---
>> >> Changes since v1:
>> >>
>> >> 1. Fixed comments as per comments from Ben Dooks
>> >> 2. Removed redunt #if defined(CONFIG_PM)
>> >> 3. Removed redunt including header files
>> >> 4. Removed <mach/pm.h> and <plat/pm-s5p.h>
>> >> 5. Moved 's5pv210_core_save' into machine directory
>> >> 6. Moved sleep.S into machine directory for S5P SoCs compatibility
>> >> 7. Added CF retension configuration when wake-up
>> >>
>> >> This patch is based on Linus' master (2.6.35-rc1)
>> >>
>> >> ?arch/arm/mach-s5pv210/Kconfig ? ? ? ? ? ? ? ? ? | ? ?6 +
>> >> ?arch/arm/mach-s5pv210/Makefile ? ? ? ? ? ? ? ? ?| ? ?1 +
>> >> ?arch/arm/mach-s5pv210/include/mach/pm-core.h ? ?| ? 44 ++++++
>> >> ?arch/arm/mach-s5pv210/include/mach/regs-clock.h | ? ?5 +-
>> >> ?arch/arm/mach-s5pv210/mach-smdkc110.c ? ? ? ? ? | ? ?2 +
>> >> ?arch/arm/mach-s5pv210/mach-smdkv210.c ? ? ? ? ? | ? ?3 +
>> >> ?arch/arm/mach-s5pv210/pm.c ? ? ? ? ? ? ? ? ? ? ?| ?180 +++++++++++++++++++++++
>> >> ?arch/arm/mach-s5pv210/sleep.S ? ? ? ? ? ? ? ? ? | ?166 +++++++++++++++++++++
>> >> ?arch/arm/plat-s5p/Makefile ? ? ? ? ? ? ? ? ? ? ?| ? ?2 +
>> >> ?arch/arm/plat-s5p/include/plat/irqs.h ? ? ? ? ? | ? ?2 +
>> >> ?arch/arm/plat-s5p/irq-pm.c ? ? ? ? ? ? ? ? ? ? ?| ?108 ++++++++++++++
>> >> ?arch/arm/plat-s5p/pm.c ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 52 +++++++
>> >> ?arch/arm/plat-samsung/pm-gpio.c ? ? ? ? ? ? ? ? | ? ?4 +-
>> >> ?13 files changed, 572 insertions(+), 3 deletions(-)
>> >> ?create mode 100644 arch/arm/mach-s5pv210/include/mach/pm-core.h
>> >> ?create mode 100644 arch/arm/mach-s5pv210/pm.c
>> >> ?create mode 100644 arch/arm/mach-s5pv210/sleep.S
>> >> ?create mode 100644 arch/arm/plat-s5p/irq-pm.c
>> >> ?create mode 100644 arch/arm/plat-s5p/pm.c
>> >>
>> >> diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
>> >> index 0761eac..86cca1b 100644
>> >> --- a/arch/arm/mach-s5pv210/Kconfig
>> >> +++ b/arch/arm/mach-s5pv210/Kconfig
>> >> @@ -14,6 +14,7 @@ config CPU_S5PV210
>> >> ? ? ? select PLAT_S5P
>> >> ? ? ? select S3C_PL330_DMA
>> >> ? ? ? select S5P_EXT_INT
>> >> + ? ? select S5PV210_PM if PM
>> >> ? ? ? help
>> >> ? ? ? ? Enable S5PV210 CPU support
>> >>
>> >> @@ -88,4 +89,9 @@ config MACH_SMDKC110
>> >> ? ? ? ? Machine support for Samsung SMDKC110
>> >> ? ? ? ? S5PC110(MCP) is one of package option of S5PV210
>> >>
>> >> +config S5PV210_PM
>> >> + ? ? bool
>> >> + ? ? help
>> >> + ? ? ? Power Management code common to S5PV210
>> >> +
>> >> ?endif
>> >> diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
>> >> index 30be9a6..59382ec 100644
>> >> --- a/arch/arm/mach-s5pv210/Makefile
>> >> +++ b/arch/arm/mach-s5pv210/Makefile
>> >> @@ -14,6 +14,7 @@ obj- ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?:=
>> >>
>> >> ?obj-$(CONFIG_CPU_S5PV210) ? ?+= cpu.o init.o clock.o dma.o gpiolib.o
>> >> ?obj-$(CONFIG_CPU_S5PV210) ? ?+= setup-i2c0.o
>> >> +obj-$(CONFIG_S5PV210_PM) ? ? += pm.o sleep.o
>> >>
>> >> ?# machine support
>> >>
>> >> diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
>> >> new file mode 100644
>> >> index 0000000..ca3f827
>> >> --- /dev/null
>> >> +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
>> >> @@ -0,0 +1,44 @@
>> >> +/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
>> >> + *
>> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
>> >> + * ? ? ? ? ? http://www.samsung.com
>> >> + *
>> >> + * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
>> >> + * Copyright 2008 Simtec Electronics
>> >> + * ? ? ?Ben Dooks <ben at simtec.co.uk>
>> >> + * ? ? ?http://armlinux.simtec.co.uk/
>> >> + *
>> >> + * S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or modify
>> >> + * it under the terms of the GNU General Public License version 2 as
>> >> + * published by the Free Software Foundation.
>> >> +*/
>> >> +
>> >> +static inline void s3c_pm_debug_init_uart(void)
>> >> +{
>> >> + ? ? /* nothing here yet */
>> >> +}
>> >> +
>> >> +static inline void s3c_pm_arch_prepare_irqs(void)
>> >> +{
>> >> + ? ? __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
>> >> + ? ? __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
>> >> +}
>> >> +
>> >> +static inline void s3c_pm_arch_stop_clocks(void)
>> >> +{
>> >> + ? ? /* nothing here yet */
>> >> +}
>> >> +
>> >> +static inline void s3c_pm_arch_show_resume_irqs(void)
>> >> +{
>> >> + ? ? /* nothing here yet */
>> >> +}
>> >> +
>> >> +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
>> >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct pm_uart_save *save)
>> >> +{
>> >> + ? ? /* nothing here yet */
>> >> +}
>> >> +
>> >> diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
>> >> index 2a25ab4..f4a443a 100644
>> >> --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
>> >> +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
>> >> @@ -157,8 +157,11 @@
>> >> ?#define S5P_SLEEP_CFG_USBOSC_EN ? ? ? ? ? ? ?(1 << 1)
>> >>
>> >> ?/* OTHERS Resgister */
>> >> +#define S5P_OTHERS_RET_IO ? ? ? ? ? ?(1 << 31)
>> >> +#define S5P_OTHERS_RET_CF ? ? ? ? ? ?(1 << 30)
>> >> +#define S5P_OTHERS_RET_MMC ? ? ? ? ? (1 << 29)
>> >> +#define S5P_OTHERS_RET_UART ? ? ? ? ?(1 << 28)
>> >> ?#define S5P_OTHERS_USB_SIG_MASK ? ? ? ? ? ? ?(1 << 16)
>> >> -#define S5P_OTHERS_MIPI_DPHY_EN ? ? ? ? ? ? ?(1 << 28)
>> >>
>> >> ?/* MIPI */
>> >> ?#define S5P_MIPI_DPHY_EN ? ? ? ? ? ? (3)
>> >> diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
>> >> index 4c8903c..ebb4832 100644
>> >> --- a/arch/arm/mach-s5pv210/mach-smdkc110.c
>> >> +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
>> >> @@ -25,6 +25,7 @@
>> >> ?#include <plat/s5pv210.h>
>> >> ?#include <plat/devs.h>
>> >> ?#include <plat/cpu.h>
>> >> +#include <plat/pm.h>
>> >>
>> >> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
>> >> ?#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | ? ? ? ?\
>> >> @@ -86,6 +87,7 @@ static void __init smdkc110_map_io(void)
>> >>
>> >> ?static void __init smdkc110_machine_init(void)
>> >> ?{
>> >> + ? ? s3c_pm_init();
>>
>> It's common function. Please add it to platform init instead of each board init.
>
> I know Mark Brown would rather this be the case too, but the original intent
> was that each board would declare itself to be capable of PM by calling this
> function to ensure that any boards which had not been validated or where
> simply incapable of suspend/resume did not end up with this enabled.

Just curious!
Which case is possible when enable the PM configuration but don't use
the s3c_pm_init()?

Thank you,
Kyungmin Park

>
>> >> ? ? ? platform_add_devices(smdkc110_devices, ARRAY_SIZE(smdkc110_devices));
>> >> ?}
>> >>
>> >> diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
>> >> index 0d46279..ba30b5d 100644
>> >> --- a/arch/arm/mach-s5pv210/mach-smdkv210.c
>> >> +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
>> >> @@ -27,6 +27,7 @@
>> >> ?#include <plat/cpu.h>
>> >> ?#include <plat/adc.h>
>> >> ?#include <plat/ts.h>
>> >> +#include <plat/pm.h>
>> >>
>> >> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
>> >> ?#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | ? ? ? ?\
>> >> @@ -96,6 +97,8 @@ static void __init smdkv210_map_io(void)
>> >>
>> >> ?static void __init smdkv210_machine_init(void)
>> >> ?{
>> >> + ? ? s3c_pm_init();
>> >> +
>> ditto.
>> >> ? ? ? s3c24xx_ts_set_platdata(&s3c_ts_platform);
>> >> ? ? ? platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
>> >> ?}
>>
>> >> diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
>> >> new file mode 100644
>> >> index 0000000..0690332
>> >> --- /dev/null
>> >> +++ b/arch/arm/mach-s5pv210/pm.c
>> >> @@ -0,0 +1,180 @@
>> >> +/* linux/arch/arm/mach-s5pv210/pm.c
>> >> + *
>> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
>> >> + * ? ? ? ? ? http://www.samsung.com
>> >> + *
>> >> + * S5PV210 - Power Management support
>> >> + *
>> >> + * Based on arch/arm/mach-s3c2410/pm.c
>> >> + * Copyright (c) 2006 Simtec Electronics
>> >> + * ? Ben Dooks <ben at simtec.co.uk>
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or modify
>> >> + * it under the terms of the GNU General Public License version 2 as
>> >> + * published by the Free Software Foundation.
>> >> +*/
>> >> +
>> >> +#include <linux/init.h>
>> >> +#include <linux/suspend.h>
>> >> +#include <linux/io.h>
>> >> +
>> >> +#include <plat/cpu.h>
>> >> +#include <plat/pm.h>
>> >> +#include <plat/regs-timer.h>
>> >> +
>> >> +#include <mach/regs-irq.h>
>> >> +#include <mach/regs-clock.h>
>> >> +
>> >> +static struct sleep_save s5pv210_core_save[] = {
>> >> + ? ? /* Clock source */
>> >> + ? ? SAVE_ITEM(S5P_CLK_SRC0),
>> >> + ? ? SAVE_ITEM(S5P_CLK_SRC1),
>> >> + ? ? SAVE_ITEM(S5P_CLK_SRC2),
>> >> + ? ? SAVE_ITEM(S5P_CLK_SRC3),
>> >> + ? ? SAVE_ITEM(S5P_CLK_SRC4),
>> >> + ? ? SAVE_ITEM(S5P_CLK_SRC5),
>> >> + ? ? SAVE_ITEM(S5P_CLK_SRC6),
>> >> +
>> >> + ? ? /* Clock source Mask */
>> >> + ? ? SAVE_ITEM(S5P_CLK_SRC_MASK0),
>> >> + ? ? SAVE_ITEM(S5P_CLK_SRC_MASK1),
>> >> +
>> >> + ? ? /* Clock Divider */
>> >> + ? ? SAVE_ITEM(S5P_CLK_DIV0),
>> >> + ? ? SAVE_ITEM(S5P_CLK_DIV1),
>> >> + ? ? SAVE_ITEM(S5P_CLK_DIV2),
>> >> + ? ? SAVE_ITEM(S5P_CLK_DIV3),
>> >> + ? ? SAVE_ITEM(S5P_CLK_DIV4),
>> >> + ? ? SAVE_ITEM(S5P_CLK_DIV5),
>> >> + ? ? SAVE_ITEM(S5P_CLK_DIV6),
>> >> + ? ? SAVE_ITEM(S5P_CLK_DIV7),
>> >> +
>> >> + ? ? /* Clock Main Gate */
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_MAIN0),
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_MAIN1),
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_MAIN2),
>> >> +
>> >> + ? ? /* Clock source Peri Gate */
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_PERI0),
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_PERI1),
>> >> +
>> >> + ? ? /* Clock source SCLK Gate */
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_SCLK0),
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_SCLK1),
>> >> +
>> >> + ? ? /* Clock IP Clock gate */
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP0),
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP1),
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP2),
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP3),
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP4),
>> >> +
>> >> + ? ? /* Clock Blcok and Bus gate */
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_BLOCK),
>> >> + ? ? SAVE_ITEM(S5P_CLKGATE_BUS0),
>> >> +
>> >> + ? ? /* Clock ETC */
>> >> + ? ? SAVE_ITEM(S5P_CLK_OUT),
>> >> + ? ? SAVE_ITEM(S5P_MDNIE_SEL),
>> >> +
>> >> + ? ? /* PWM Register */
>> >> + ? ? SAVE_ITEM(S3C2410_TCFG0),
>> >> + ? ? SAVE_ITEM(S3C2410_TCFG1),
>> >> + ? ? SAVE_ITEM(S3C64XX_TINT_CSTAT),
>> >> + ? ? SAVE_ITEM(S3C2410_TCON),
>> >> + ? ? SAVE_ITEM(S3C2410_TCNTB(0)),
>> >> + ? ? SAVE_ITEM(S3C2410_TCMPB(0)),
>> >> + ? ? SAVE_ITEM(S3C2410_TCNTO(0)),
>> >> +
>> >> + ? ? /* VIC 2 and 3*/
>> >> + ? ? SAVE_ITEM(VA_VIC2 + VIC_INT_SELECT),
>> >> + ? ? SAVE_ITEM(VA_VIC3 + VIC_INT_SELECT),
>> >> + ? ? SAVE_ITEM(VA_VIC2 + VIC_INT_ENABLE),
>> >> + ? ? SAVE_ITEM(VA_VIC3 + VIC_INT_ENABLE),
>> >> + ? ? SAVE_ITEM(VA_VIC2 + VIC_INT_SOFT),
>> >> + ? ? SAVE_ITEM(VA_VIC3 + VIC_INT_SOFT),
>> >
>> > doesn't the vic driver do this for you? if not, then would be better
>> > to change the vic to fix this.
>> >
>> >> +};
>> >> +
>> >> +void s5pv210_cpu_suspend(void)
>> >> +{
>> >> + ? ? unsigned long tmp;
>> >> +
>> >> + ? ? /* issue the standby signal into the pm unit. Note, we
>> >> + ? ? ?* issue a write-buffer drain just in case */
>> >> +
>> >> + ? ? tmp = 0;
>> >> +
>> >> + ? ? asm("b 1f\n\t"
>> >> + ? ? ? ? ".align 5\n\t"
>> >> + ? ? ? ? "1:\n\t"
>> >> + ? ? ? ? "mcr p15, 0, %0, c7, c10, 5\n\t"
>> >> + ? ? ? ? "mcr p15, 0, %0, c7, c10, 4\n\t"
>> >> + ? ? ? ? ".word 0xe320f003" : : "r" (tmp));
>> >
>> > why .word? if there's a compiler problem then make a comment about
>> > what instruction is being synthesised and why.
>> >
>> >> + ? ? /* we should never get past here */
>> >> + ? ? panic("sleep resumed to originator?");
>> >> +}
>> >> +
>> >> +static void s5pv210_pm_prepare(void)
>> >> +{
>> >> + ? ? unsigned int tmp;
>> >> +
>> >> + ? ? /* ensure at least INFORM0 has the resume address */
>> >> + ? ? __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
>> >> +
>> >> + ? ? tmp = __raw_readl(S5P_SLEEP_CFG);
>> >> + ? ? tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
>> >> + ? ? __raw_writel(tmp, S5P_SLEEP_CFG);
>> >> +
>> >> + ? ? /* WFI for SLEEP mode configuration by SYSCON */
>> >> + ? ? tmp = __raw_readl(S5P_PWR_CFG);
>> >> + ? ? tmp &= S5P_CFG_WFI_CLEAN;
>>
>> CLEAN? just use the MASK and use common mask operation. tmp &=
>> ~S5P_CFG_WFI_MASK;
>>
>> >> + ? ? tmp |= S5P_CFG_WFI_SLEEP;
>> >> + ? ? __raw_writel(tmp, S5P_PWR_CFG);
>> >> +
>> >> + ? ? /* SYSCON interrupt handling disable */
>> >> + ? ? tmp = __raw_readl(S5P_OTHERS);
>> >> + ? ? tmp |= S5P_OTHER_SYSC_INTOFF;
>> >> + ? ? __raw_writel(tmp, S5P_OTHERS);
>> >> +
>> >> + ? ? __raw_writel(0xffffffff, (VA_VIC0 + VIC_INT_ENABLE_CLEAR));
>> >> + ? ? __raw_writel(0xffffffff, (VA_VIC1 + VIC_INT_ENABLE_CLEAR));
>> >> + ? ? __raw_writel(0xffffffff, (VA_VIC2 + VIC_INT_ENABLE_CLEAR));
>> >> + ? ? __raw_writel(0xffffffff, (VA_VIC3 + VIC_INT_ENABLE_CLEAR));
>> >> +
>> >> + ? ? s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
>> >> +}
>> >> +
>> >> +static int s5pv210_pm_add(struct sys_device *sysdev)
>> >> +{
>> >> + ? ? pm_cpu_prep = s5pv210_pm_prepare;
>> >> + ? ? pm_cpu_sleep = s5pv210_cpu_suspend;
>> >> +
>> >> + ? ? return 0;
>> >> +}
>> >> +
>> >> +static int s5pv210_pm_resume(struct sys_device *dev)
>> >> +{
>> >> + ? ? u32 tmp;
>> >> +
>> >> + ? ? tmp = __raw_readl(S5P_OTHERS);
>> >> + ? ? tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | \
>> >> + ? ? ? ? ? ? S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART);
>> >> + ? ? __raw_writel(tmp , S5P_OTHERS);
>> >> +
>> >> + ? ? s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
>> >> +
>> >> + ? ? return 0;
>> >> +}
>> >> +
>> >> +static struct sysdev_driver s5pv210_pm_driver = {
>> >> + ? ? .add ? ? ? ? ? ?= s5pv210_pm_add,
>> >> + ? ? .resume ? ? ? ? = s5pv210_pm_resume,
>> >> +};
>> >> +
>> >> +static __init int s5pv210_pm_drvinit(void)
>> >> +{
>> >> + ? ? return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver);
>> >> +}
>> >> +arch_initcall(s5pv210_pm_drvinit);
>> >> diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
>> >> new file mode 100644
>> >> index 0000000..b7f8272
>> >> --- /dev/null
>> >> +++ b/arch/arm/mach-s5pv210/sleep.S
>> >> @@ -0,0 +1,166 @@
>> >> +/* linux/arch/arm/mach-s5pv210/sleep.S
>> >> + *
>> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
>> >> + * ? ? ? ? ? http://www.samsung.com
>> >> + *
>> >> + * S5PV210 power Manager (Suspend-To-RAM) support
>> >> + *
>> >> + * Based on S3C2410 sleep code by:
>> >> + * ? Ben Dooks, (c) 2004 Simtec Electronics
>> >> + *
>> >> + * Based on PXA/SA1100 sleep code by:
>> >> + * ? Nicolas Pitre, (c) 2002 Monta Vista Software Inc
>> >> + * ? Cliff Brake, (c) 2001
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or modify
>> >> + * it under the terms of the GNU General Public License as published by
>> >> + * the Free Software Foundation; either version 2 of the License, or
>> >> + * (at your option) any later version.
>> >> + *
>> >> + * This program is distributed in the hope that it will be useful,
>> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
>> >> + * GNU General Public License for more details.
>> >> + *
>> >> + * You should have received a copy of the GNU General Public License
>> >> + * along with this program; if not, write to the Free Software
>> >> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA ?02111-1307 ?USA
>> >> +*/
>> >> +
>> >> +#include <linux/linkage.h>
>> >> +#include <asm/assembler.h>
>> >> +#include <asm/memory.h>
>> >> +
>> >> + ? ? .text
>> >> +
>> >> + ? ? /* s3c_cpu_save
>> >> + ? ? ?*
>> >> + ? ? ?* entry:
>> >> + ? ? ?* ? ? ?r0 = save address (virtual addr of s3c_sleep_save_phys)
>> >> + ? ? */
>> >> +
>> >> +ENTRY(s3c_cpu_save)
>> >> +
>> >> + ? ? stmfd ? sp!, { r3 - r12, lr }
>> >> +
>> >> + ? ? mrc ? ? p15, 0, r4, c13, c0, 0 ?@ FCSE/PID
>> >> + ? ? mrc ? ? p15, 0, r5, c3, c0, 0 ? @ Domain ID
>> >> + ? ? mrc ? ? p15, 0, r6, c2, c0, 0 ? @ Translation Table BASE0
>> >> + ? ? mrc ? ? p15, 0, r7, c2, c0, 1 ? @ Translation Table BASE1
>> >> + ? ? mrc ? ? p15, 0, r8, c2, c0, 2 ? @ Translation Table Control
>> >> + ? ? mrc ? ? p15, 0, r9, c1, c0, 0 ? @ Control register
>> >> + ? ? mrc ? ? p15, 0, r10, c1, c0, 1 ?@ Auxiliary control register
>> >> + ? ? mrc ? ? p15, 0, r11, c1, c0, 2 ?@ Co-processor access controls
>> >> + ? ? mrc ? ? p15, 0, r12, c10, c2, 0 @ Read PRRR
>> >> + ? ? mrc ? ? p15, 0, r3, c10, c2, 1 ?@ READ NMRR
>> >> +
>> >> + ? ? stmia ? r0, { r3 - r13 }
>> >> +
>> >> + ? ? bl ? ? ?s3c_pm_cb_flushcache
>> >> +
>> >> + ? ? ldr ? ? r0, =pm_cpu_sleep
>> >> + ? ? ldr ? ? r0, [ r0 ]
>> >> + ? ? mov ? ? pc, r0
>> >> +
>> >> +resume_with_mmu:
>> >> + ? ? /* delete added mmu table list */
>> >
>> > hmm, where is this being added?
>> > also, a better description on what it is doing would be better.
>> >
>> >> + ? ? ldr ? ? r9 , =(PAGE_OFFSET - PHYS_OFFSET)
>> >> + ? ? add ? ? r4, r4, r9
>> >> + ? ? str ? ? r12, [r4]
>> >> +
>> >> + ? ? ldmfd ? sp!, { r3 - r12, pc }
>> >> +
>> >> + ? ? .ltorg
>> >> +
>> >> + ? ? .data
>> >> +
>> >> + ? ? .global s3c_sleep_save_phys
>> >> +s3c_sleep_save_phys:
>> >> + ? ? .word ? 0
>> >> +
>> >> + ? ? /* sleep magic, to allow the bootloader to check for an valid
>> >> + ? ? ?* image to resume to. Must be the first word before the
>> >> + ? ? ?* s3c_cpu_resume entry.
>> >> + ? ? */
>> >> +
>> >> + ? ? .word ? 0x2bedf00d
>> >> +
>> >> + ? ? /* s3c_cpu_resume
>> >> + ? ? ?*
>> >> + ? ? ?* resume code entry for bootloader to call
>> >> + ? ? ?*
>> >> + ? ? ?* we must put this code here in the data segment as we have no
>> >> + ? ? ?* other way of restoring the stack pointer after sleep, and we
>> >> + ? ? ?* must not write to the code segment (code is read-only)
>> >> + ? ? */
>> >> +
>> >> +ENTRY(s3c_cpu_resume)
>> >> + ? ? mov ? ? r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
>> >> + ? ? msr ? ? cpsr_c, r0
>> >> +
>> >> + ? ? mov ? ? r1, #0
>> >> + ? ? mcr ? ? p15, 0, r1, c8, c7, 0 ? ? ? ? ? @@ invalidate TLBs
>> >> + ? ? mcr ? ? p15, 0, r1, c7, c5, 0 ? ? ? ? ? @@ invalidate I Cache
>> >> +
>> >> + ? ? ldr ? ? r0, s3c_sleep_save_phys ? ? ? ? @ address of restore block
>> >> + ? ? ldmia ? r0, { r3 - r13 }
>> >> +
>> >> + ? ? mcr ? ? p15, 0, r4, c13, c0, 0 ? ? ? ? ?@ FCSE/PID
>> >> + ? ? mcr ? ? p15, 0, r5, c3, c0, 0 ? ? ? ? ? @ Domain ID
>> >> +
>> >> + ? ? mcr ? ? p15, 0, r8, c2, c0, 2 ? ? ? ? ? @ Translation Table Control
>> >> + ? ? mcr ? ? p15, 0, r7, c2, c0, 1 ? ? ? ? ? @ Translation Table BASE1
>> >> + ? ? mcr ? ? p15, 0, r6, c2, c0, 0 ? ? ? ? ? @ Translation Table BASE0
>> >> +
>> >> + ? ? mcr ? ? p15, 0, r10, c1, c0, 1 ? ? ? ? ?@ Auxiliary control register
>> >> +
>> >> + ? ? mov ? ? r0, #0
>> >> + ? ? mcr ? ? p15, 0, r0, c8, c7, 0 ? ? ? ? ? @ Invalidate I & D TLB
>> >> +
>> >> + ? ? mov ? ? r0, #0 ? ? ? ? ? ? ? ? ? ? ? ? ?@ restore copro access
>> >> + ? ? mcr ? ? p15, 0, r11, c1, c0, 2 ? ? ? ? ?@ Co-processor access
>> >> + ? ? mcr ? ? p15, 0, r0, c7, c5, 4
>> >> +
>> >> + ? ? mcr ? ? p15, 0, r12, c10, c2, 0 ? ? ? ? @ write PRRR
>> >> + ? ? mcr ? ? p15, 0, r3, c10, c2, 1 ? ? ? ? ?@ write NMRR
>> >> +
>> >> + ? ? /* Calculate first section address into r8
>> >> + ? ? ?* In Cotex-A8 case, When MMU turn on, MMU is reseted.
>> >
>> > i'd fix this typo.
>> >
>> >> + ? ? ?* So, before call resume_with_mmu, backup originally data.
>> >> + ? ? */
>> >> +
>> >> + ? ? mov ? ? r4, r6
>> >> + ? ? mov ? ? r4, r4, LSR #14
>> >> + ? ? mov ? ? r4, r4, LSL #14
>> >> +
>> >> + ? ? /* Load TLB Base address from INFORM0 */
>> >
>> > do you mean mmu page table?
>> >
>> >> + ? ? ldr ? ? r11, =0xe010f000
>> >> + ? ? ldr ? ? r10, [r11, #0]
>> >> + ? ? mov ? ? r10, r10, LSR #18
>> >> + ? ? bic ? ? r10, r10, #0x3
>> >> + ? ? orr ? ? r4, r4, r10
>> >> +
>> >> + ? ? /* calculate mmu list value into r9 */
>> >> + ? ? mov ? ? r10, r10, LSL #18
>> >> + ? ? ldr ? ? r5, =0x40e
>> >> + ? ? orr ? ? r10, r10, r5
>>
>> r10 is correct register? in the above it used the r9 register.
>>
>> >> +
>> >> + ? ? /* back up originally data */
>> >> +
>> >> + ? ? ldr ? ? r12, [r4]
>> >> +
>> >> + ? ? /* Added list about mmu */
>> >> + ? ? str ? ? r10, [r4]
>> >
>> >
>> >
>> >> + ? ? ldr ? ? r2, =resume_with_mmu
>> >> + ? ? mcr ? ? p15, 0, r9, c1, c0, 0 ? ? ? ? ? @ turn on MMU, etc
>> >> +
>> >> + ? ? nop
>> >> + ? ? nop
>> >> + ? ? nop
>> >> + ? ? nop
>> >> + ? ? nop ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ second-to-last before mmu
>> >> +
>> >> + ? ? mov ? ? pc, r2 ? ? ? ? ? ? ? ? ? ? ? ? ?@ go back to virtual address
>> >> +
>> >> + ? ? .ltorg
>> >> diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
>> >> index 39c242b..d04ae49 100644
>> >> --- a/arch/arm/plat-s5p/Makefile
>> >> +++ b/arch/arm/plat-s5p/Makefile
>> >> @@ -18,3 +18,5 @@ obj-y ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += clock.o
>> >> ?obj-y ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?+= irq.o
>> >> ?obj-$(CONFIG_S5P_EXT_INT) ? ?+= irq-eint.o
>> >>
>> >> +obj-$(CONFIG_PM) ? ? ? ? ? ? += pm.o
>> >> +obj-$(CONFIG_PM) ? ? ? ? ? ? += irq-pm.o
>> >> diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
>> >> index 3fb3a3a..9ffdd62 100644
>> >> --- a/arch/arm/plat-s5p/include/plat/irqs.h
>> >> +++ b/arch/arm/plat-s5p/include/plat/irqs.h
>> >> @@ -94,4 +94,6 @@
>> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ((irq) - S5P_EINT_BASE1) : \
>> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ((irq) + 16 - S5P_EINT_BASE2))
>> >>
>> >> +#define IRQ_EINT_BIT(x) ? ? ? ? ? ? ?EINT_OFFSET(x)
>> >> +
>> >> ?#endif /* __ASM_PLAT_S5P_IRQS_H */
>> >> diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
>> >> new file mode 100644
>> >> index 0000000..03e83a3
>> >> --- /dev/null
>> >> +++ b/arch/arm/plat-s5p/irq-pm.c
>> >> @@ -0,0 +1,108 @@
>> >> +/* linux/arch/arm/plat-s5p/irq-pm.c
>> >> + *
>> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
>> >> + * ? ? ? ? ? http://www.samsung.com
>> >> + *
>> >> + * Based on arch/arm/plat-s3c24xx/irq-pm.c,
>> >> + * Copyright (c) 2003,2004 Simtec Electronics
>> >> + * ? Ben Dooks <ben at simtec.co.uk>
>> >> + * ? http://armlinux.simtec.co.uk/
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or modify
>> >> + * it under the terms of the GNU General Public License version 2 as
>> >> + * published by the Free Software Foundation.
>> >> +*/
>> >> +
>> >> +#include <linux/init.h>
>> >> +#include <linux/module.h>
>> >> +#include <linux/interrupt.h>
>> >> +#include <linux/sysdev.h>
>> >> +
>> >> +#include <plat/cpu.h>
>> >> +#include <plat/irqs.h>
>> >> +#include <plat/pm.h>
>> >> +#include <mach/map.h>
>> >> +
>> >> +#include <mach/regs-gpio.h>
>> >> +#include <mach/regs-irq.h>
>> >> +
>> >> +/* state for IRQs over sleep */
>> >> +
>> >> +/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
>> >> + * as wakeup sources
>> >> + *
>> >> + * set bit to 1 in allow bitfield to enable the wakeup settings on it
>> >> +*/
>> >> +
>> >> +unsigned long s3c_irqwake_intallow ? = 0x00000006L;
>> >> +unsigned long s3c_irqwake_eintallow ?= 0xffffffffL;
>> >> +
>> >> +int s3c_irq_wake(unsigned int irqno, unsigned int state)
>> >> +{
>> >> + ? ? unsigned long irqbit;
>> >> +
>> >> + ? ? switch (irqno) {
>> >> + ? ? case IRQ_RTC_TIC:
>> >> + ? ? case IRQ_RTC_ALARM:
>> >> + ? ? ? ? ? ? irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM);
>> >> + ? ? ? ? ? ? if (!state)
>> >> + ? ? ? ? ? ? ? ? ? ? s3c_irqwake_intmask |= irqbit;
>> >> + ? ? ? ? ? ? else
>> >> + ? ? ? ? ? ? ? ? ? ? s3c_irqwake_intmask &= ~irqbit;
>> >> + ? ? ? ? ? ? break;
>> >> + ? ? default:
>> >> + ? ? ? ? ? ? return -ENOENT;
>> >> + ? ? }
>> >> + ? ? return 0;
>> >> +}
>> >> +
>> >> +/* this lot should be really saved by the IRQ code */
>> >> +/* VICXADDRESSXX initilaization to be needed */
>> >> +static struct sleep_save irq_save[] = {
>> >> + ? ? SAVE_ITEM(VA_VIC0 + VIC_INT_SELECT),
>> >> + ? ? SAVE_ITEM(VA_VIC1 + VIC_INT_SELECT),
>> >> +
>> >> + ? ? SAVE_ITEM(VA_VIC0 + VIC_INT_ENABLE),
>> >> + ? ? SAVE_ITEM(VA_VIC1 + VIC_INT_ENABLE),
>> >> +
>> >> + ? ? SAVE_ITEM(VA_VIC0 + VIC_INT_SOFT),
>> >> + ? ? SAVE_ITEM(VA_VIC1 + VIC_INT_SOFT),
>> >> +};
>> >> +
>> >> +static struct sleep_save eint_save[] = {
>> >> + ? ? SAVE_ITEM(S5P_EINT_CON(0)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_CON(1)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_CON(2)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_CON(3)),
>> >> +
>> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(0)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(1)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(2)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(3)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(4)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(5)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(6)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(7)),
>> >> +
>> >> + ? ? SAVE_ITEM(S5P_EINT_MASK(0)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_MASK(1)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_MASK(2)),
>> >> + ? ? SAVE_ITEM(S5P_EINT_MASK(3)),
>> >> +};
>> >> +
>> >> +int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
>> >> +{
>> >> + ? ? s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
>> >> + ? ? s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
>> >> +
>> >> + ? ? return 0;
>> >> +}
>> >> +
>> >> +int s3c24xx_irq_resume(struct sys_device *dev)
>> >> +{
>> >> + ? ? s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
>> >> + ? ? s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
>> >> +
>> >> + ? ? return 0;
>> >> +}
>> >> +
>> >> diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-s5p/pm.c
>> >> new file mode 100644
>> >> index 0000000..d592b63
>> >> --- /dev/null
>> >> +++ b/arch/arm/plat-s5p/pm.c
>> >> @@ -0,0 +1,52 @@
>> >> +/* linux/arch/arm/plat-s5p/pm.c
>> >> + *
>> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
>> >> + * ? ? ? ? ? http://www.samsung.com
>> >> + *
>> >> + * S5P Power Manager (Suspend-To-RAM) support
>> >> + *
>> >> + * Based on arch/arm/plat-s3c24xx/pm.c
>> >> + * Copyright (c) 2004,2006 Simtec Electronics
>> >> + * ? Ben Dooks <ben at simtec.co.uk>
>> >> + *
>> >> + * This program is free software; you can redistribute it and/or modify
>> >> + * it under the terms of the GNU General Public License version 2 as
>> >> + * published by the Free Software Foundation.
>> >> +*/
>> >> +
>> >> +#include <linux/suspend.h>
>> >> +#include <plat/pm.h>
>> >> +
>> >> +#define PFX "s5p pm: "
>> >> +
>> >> +/* s3c_pm_check_resume_pin
>> >> + *
>> >> + * check to see if the pin is configured correctly for sleep mode, and
>> >> + * make any necessary adjustments if it is not
>> >> +*/
>> >> +
>> >> +static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
>> >> +{
>> >> + ? ? /* nothing here yet */
>> >> +}
>> >> +
>> >> +/* s3c_pm_configure_extint
>> >> + *
>> >> + * configure all external interrupt pins
>> >> +*/
>> >> +
>> >> +void s3c_pm_configure_extint(void)
>> >> +{
>> >> + ? ? /* nothing here yet */
>> >> +}
>> >> +
>> >> +void s3c_pm_restore_core(void)
>> >> +{
>> >> + ? ? /* nothing here yet */
>> >> +}
>> >> +
>> >> +void s3c_pm_save_core(void)
>> >> +{
>> >> + ? ? /* nothing here yet */
>> >> +}
>> >> +
>> >> diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
>> >> index 7df03f8..9652820 100644
>> >> --- a/arch/arm/plat-samsung/pm-gpio.c
>> >> +++ b/arch/arm/plat-samsung/pm-gpio.c
>> >> @@ -192,7 +192,7 @@ struct s3c_gpio_pm s3c_gpio_pm_2bit = {
>> >> ? ? ? .resume = s3c_gpio_pm_2bit_resume,
>> >> ?};
>> >>
>> >> -#ifdef CONFIG_ARCH_S3C64XX
>> >> +#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
>> >> ?static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
>> >> ?{
>> >> ? ? ? chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
>> >> @@ -302,7 +302,7 @@ struct s3c_gpio_pm s3c_gpio_pm_4bit = {
>> >> ? ? ? .save ? = s3c_gpio_pm_4bit_save,
>> >> ? ? ? .resume = s3c_gpio_pm_4bit_resume,
>> >> ?};
>> >> -#endif /* CONFIG_ARCH_S3C64XX */
>> >> +#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
>> >>
>> >> ?/**
>> >> ? * s3c_pm_save_gpio() - save gpio chip data for suspend
>> >> --
>> >> 1.6.2.5
>> >>
>> >
>> >
>> > --
>> > --
>> > Ben
>> >
>> > Q: ? ? ?What's a light-year?
>> > A: ? ? ?One-third less calories than a regular year.
>> >
>> > --
>> > To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> > the body of a message to majordomo at vger.kernel.org
>> > More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>> >
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>
> --
> --
> Ben
>
> Q: ? ? ?What's a light-year?
> A: ? ? ?One-third less calories than a regular year.
>
>


From mcuos.com at gmail.com  Tue Jun  1 01:03:26 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Tue, 1 Jun 2010 13:03:26 +0800
Subject: [PATCH] NUC900/rtc: change the waiting for device ready implement
In-Reply-To: <4BFE1853.5070105@gmail.com>
References: <4BFE1853.5070105@gmail.com>
Message-ID: <AANLkTinNJOFkTUqvXxZjb-pqfjYZPTnxANLjPg9PMdvw@mail.gmail.com>

Hi Andrew,

How about this patch?
Do you think this change is necessary?

? 2010?5?27? ??2:59?Wan ZongShun <mcuos.com at gmail.com> ???
> Dear Andrew,
>
> This patch is only to change the waiting for device ready implement
> for winbond nuc900 platform.
>
> Signed-off-by:Wan ZongShun<mcuos.com at gmail.com>
>
> ---
> ?drivers/rtc/rtc-nuc900.c | ? 15 +++++++--------
> ?1 files changed, 7 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/rtc/rtc-nuc900.c b/drivers/rtc/rtc-nuc900.c
> index a351bd5..21d1330 100644
> --- a/drivers/rtc/rtc-nuc900.c
> +++ b/drivers/rtc/rtc-nuc900.c
> @@ -85,22 +85,21 @@ static irqreturn_t nuc900_rtc_interrupt(int irq, void *_rtc)
>
> ?static int *check_rtc_access_enable(struct nuc900_rtc *nuc900_rtc)
> ?{
> - ? ? ? unsigned int i;
> + ? ? ? unsigned int i, timeout = 0x1000;
> ? ? ? ?__raw_writel(INIRRESET, nuc900_rtc->rtc_reg + REG_RTC_INIR);
>
> ? ? ? ?mdelay(10);
>
> ? ? ? ?__raw_writel(AERPOWERON, nuc900_rtc->rtc_reg + REG_RTC_AER);
>
> - ? ? ? for (i = 0; i < 1000; i++) {
> - ? ? ? ? ? ? ? if (__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB)
> - ? ? ? ? ? ? ? ? ? ? ? return 0;
> - ? ? ? }
> + ? ? ? while (!(__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? && timeout--)
> + ? ? ? ? ? ? ? mdelay(1);
>
> - ? ? ? if ((__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB) == 0x0)
> - ? ? ? ? ? ? ? return ERR_PTR(-ENODEV);
> + ? ? ? if (!timeout)
> + ? ? ? ? ? ? ? return ERR_PTR(-EPERM);
>
> - ? ? ? return ERR_PTR(-EPERM);
> + ? ? ? return 0;
> ?}
>
> ?static void nuc900_rtc_bcd2bin(unsigned int timereg,
> --
> 1.6.3.3
>



-- 
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From myungjoo.ham at gmail.com  Tue Jun  1 01:13:18 2010
From: myungjoo.ham at gmail.com (MyungJoo Ham)
Date: Tue, 1 Jun 2010 14:13:18 +0900
Subject: [PATCH v2] ARM: S5PV210: Add Power Management Support
In-Reply-To: <20100601020329.GT4720@trinity.fluff.org>
References: <1275356164-7896-1-git-send-email-kgene.kim@samsung.com>
	<20100601020329.GT4720@trinity.fluff.org>
Message-ID: <AANLkTikdkOvvdsQvwuqS9QFv6yIM7LQJb24NrTi-RA-s@mail.gmail.com>

On Tue, Jun 1, 2010 at 11:03 AM, Ben Dooks <ben-linux at fluff.org> wrote:
>
> On Tue, Jun 01, 2010 at 10:36:04AM +0900, Kukjin Kim wrote:
>> From: Jongpill Lee <boyko.lee at samsung.com>
>>
>> This patch adds suspend-to-ram support for S5PV210.
>>
>> Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
>> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
>> ---
>> Changes since v1:
>>
>> 1. Fixed comments as per comments from Ben Dooks
>> 2. Removed redunt #if defined(CONFIG_PM)
>> 3. Removed redunt including header files
>> 4. Removed <mach/pm.h> and <plat/pm-s5p.h>
>> 5. Moved 's5pv210_core_save' into machine directory
>> 6. Moved sleep.S into machine directory for S5P SoCs compatibility
>> 7. Added CF retension configuration when wake-up
>>
>> This patch is based on Linus' master (2.6.35-rc1)
>>
>> ?arch/arm/mach-s5pv210/Kconfig ? ? ? ? ? ? ? ? ? | ? ?6 +
>> ?arch/arm/mach-s5pv210/Makefile ? ? ? ? ? ? ? ? ?| ? ?1 +
>> ?arch/arm/mach-s5pv210/include/mach/pm-core.h ? ?| ? 44 ++++++
>> ?arch/arm/mach-s5pv210/include/mach/regs-clock.h | ? ?5 +-
>> ?arch/arm/mach-s5pv210/mach-smdkc110.c ? ? ? ? ? | ? ?2 +
>> ?arch/arm/mach-s5pv210/mach-smdkv210.c ? ? ? ? ? | ? ?3 +
>> ?arch/arm/mach-s5pv210/pm.c ? ? ? ? ? ? ? ? ? ? ?| ?180 +++++++++++++++++++++++
>> ?arch/arm/mach-s5pv210/sleep.S ? ? ? ? ? ? ? ? ? | ?166 +++++++++++++++++++++
>> ?arch/arm/plat-s5p/Makefile ? ? ? ? ? ? ? ? ? ? ?| ? ?2 +
>> ?arch/arm/plat-s5p/include/plat/irqs.h ? ? ? ? ? | ? ?2 +
>> ?arch/arm/plat-s5p/irq-pm.c ? ? ? ? ? ? ? ? ? ? ?| ?108 ++++++++++++++
>> ?arch/arm/plat-s5p/pm.c ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 52 +++++++
>> ?arch/arm/plat-samsung/pm-gpio.c ? ? ? ? ? ? ? ? | ? ?4 +-
>> ?13 files changed, 572 insertions(+), 3 deletions(-)
>> ?create mode 100644 arch/arm/mach-s5pv210/include/mach/pm-core.h
>> ?create mode 100644 arch/arm/mach-s5pv210/pm.c
>> ?create mode 100644 arch/arm/mach-s5pv210/sleep.S
>> ?create mode 100644 arch/arm/plat-s5p/irq-pm.c
>> ?create mode 100644 arch/arm/plat-s5p/pm.c
>>
>> diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
>> index 0761eac..86cca1b 100644
>> --- a/arch/arm/mach-s5pv210/Kconfig
>> +++ b/arch/arm/mach-s5pv210/Kconfig
>> @@ -14,6 +14,7 @@ config CPU_S5PV210
>> ? ? ? select PLAT_S5P
>> ? ? ? select S3C_PL330_DMA
>> ? ? ? select S5P_EXT_INT
>> + ? ? select S5PV210_PM if PM
>> ? ? ? help
>> ? ? ? ? Enable S5PV210 CPU support
>>
>> @@ -88,4 +89,9 @@ config MACH_SMDKC110
>> ? ? ? ? Machine support for Samsung SMDKC110
>> ? ? ? ? S5PC110(MCP) is one of package option of S5PV210
>>
>> +config S5PV210_PM
>> + ? ? bool
>> + ? ? help
>> + ? ? ? Power Management code common to S5PV210
>> +
>> ?endif
>> diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
>> index 30be9a6..59382ec 100644
>> --- a/arch/arm/mach-s5pv210/Makefile
>> +++ b/arch/arm/mach-s5pv210/Makefile
>> @@ -14,6 +14,7 @@ obj- ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?:=
>>
>> ?obj-$(CONFIG_CPU_S5PV210) ? ?+= cpu.o init.o clock.o dma.o gpiolib.o
>> ?obj-$(CONFIG_CPU_S5PV210) ? ?+= setup-i2c0.o
>> +obj-$(CONFIG_S5PV210_PM) ? ? += pm.o sleep.o
>>
>> ?# machine support
>>
>> diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
>> new file mode 100644
>> index 0000000..ca3f827
>> --- /dev/null
>> +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
>> @@ -0,0 +1,44 @@
>> +/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
>> + *
>> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
>> + * ? ? ? ? ? http://www.samsung.com
>> + *
>> + * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
>> + * Copyright 2008 Simtec Electronics
>> + * ? ? ?Ben Dooks <ben at simtec.co.uk>
>> + * ? ? ?http://armlinux.simtec.co.uk/
>> + *
>> + * S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +static inline void s3c_pm_debug_init_uart(void)
>> +{
>> + ? ? /* nothing here yet */
>> +}
>> +
>> +static inline void s3c_pm_arch_prepare_irqs(void)
>> +{
>> + ? ? __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
>> + ? ? __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
>> +}
>> +
>> +static inline void s3c_pm_arch_stop_clocks(void)
>> +{
>> + ? ? /* nothing here yet */
>> +}
>> +
>> +static inline void s3c_pm_arch_show_resume_irqs(void)
>> +{
>> + ? ? /* nothing here yet */
>> +}
>> +
>> +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct pm_uart_save *save)
>> +{
>> + ? ? /* nothing here yet */
>> +}
>> +
>> diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
>> index 2a25ab4..f4a443a 100644
>> --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
>> +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
>> @@ -157,8 +157,11 @@
>> ?#define S5P_SLEEP_CFG_USBOSC_EN ? ? ? ? ? ? ?(1 << 1)
>>
>> ?/* OTHERS Resgister */
>> +#define S5P_OTHERS_RET_IO ? ? ? ? ? ?(1 << 31)
>> +#define S5P_OTHERS_RET_CF ? ? ? ? ? ?(1 << 30)
>> +#define S5P_OTHERS_RET_MMC ? ? ? ? ? (1 << 29)
>> +#define S5P_OTHERS_RET_UART ? ? ? ? ?(1 << 28)
>> ?#define S5P_OTHERS_USB_SIG_MASK ? ? ? ? ? ? ?(1 << 16)
>> -#define S5P_OTHERS_MIPI_DPHY_EN ? ? ? ? ? ? ?(1 << 28)
>>
>> ?/* MIPI */
>> ?#define S5P_MIPI_DPHY_EN ? ? ? ? ? ? (3)
>> diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
>> index 4c8903c..ebb4832 100644
>> --- a/arch/arm/mach-s5pv210/mach-smdkc110.c
>> +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
>> @@ -25,6 +25,7 @@
>> ?#include <plat/s5pv210.h>
>> ?#include <plat/devs.h>
>> ?#include <plat/cpu.h>
>> +#include <plat/pm.h>
>>
>> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
>> ?#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | ? ? ? ?\
>> @@ -86,6 +87,7 @@ static void __init smdkc110_map_io(void)
>>
>> ?static void __init smdkc110_machine_init(void)
>> ?{
>> + ? ? s3c_pm_init();
>> ? ? ? platform_add_devices(smdkc110_devices, ARRAY_SIZE(smdkc110_devices));
>> ?}
>>
>> diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
>> index 0d46279..ba30b5d 100644
>> --- a/arch/arm/mach-s5pv210/mach-smdkv210.c
>> +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
>> @@ -27,6 +27,7 @@
>> ?#include <plat/cpu.h>
>> ?#include <plat/adc.h>
>> ?#include <plat/ts.h>
>> +#include <plat/pm.h>
>>
>> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
>> ?#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | ? ? ? ?\
>> @@ -96,6 +97,8 @@ static void __init smdkv210_map_io(void)
>>
>> ?static void __init smdkv210_machine_init(void)
>> ?{
>> + ? ? s3c_pm_init();
>> +
>> ? ? ? s3c24xx_ts_set_platdata(&s3c_ts_platform);
>> ? ? ? platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
>> ?}
>> diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
>> new file mode 100644
>> index 0000000..0690332
>> --- /dev/null
>> +++ b/arch/arm/mach-s5pv210/pm.c
>> @@ -0,0 +1,180 @@
>> +/* linux/arch/arm/mach-s5pv210/pm.c
>> + *
>> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
>> + * ? ? ? ? ? http://www.samsung.com
>> + *
>> + * S5PV210 - Power Management support
>> + *
>> + * Based on arch/arm/mach-s3c2410/pm.c
>> + * Copyright (c) 2006 Simtec Electronics
>> + * ? Ben Dooks <ben at simtec.co.uk>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +#include <linux/init.h>
>> +#include <linux/suspend.h>
>> +#include <linux/io.h>
>> +
>> +#include <plat/cpu.h>
>> +#include <plat/pm.h>
>> +#include <plat/regs-timer.h>
>> +
>> +#include <mach/regs-irq.h>
>> +#include <mach/regs-clock.h>
>> +
>> +static struct sleep_save s5pv210_core_save[] = {
>> + ? ? /* Clock source */
>> + ? ? SAVE_ITEM(S5P_CLK_SRC0),
>> + ? ? SAVE_ITEM(S5P_CLK_SRC1),
>> + ? ? SAVE_ITEM(S5P_CLK_SRC2),
>> + ? ? SAVE_ITEM(S5P_CLK_SRC3),
>> + ? ? SAVE_ITEM(S5P_CLK_SRC4),
>> + ? ? SAVE_ITEM(S5P_CLK_SRC5),
>> + ? ? SAVE_ITEM(S5P_CLK_SRC6),
>> +
>> + ? ? /* Clock source Mask */
>> + ? ? SAVE_ITEM(S5P_CLK_SRC_MASK0),
>> + ? ? SAVE_ITEM(S5P_CLK_SRC_MASK1),
>> +
>> + ? ? /* Clock Divider */
>> + ? ? SAVE_ITEM(S5P_CLK_DIV0),
>> + ? ? SAVE_ITEM(S5P_CLK_DIV1),
>> + ? ? SAVE_ITEM(S5P_CLK_DIV2),
>> + ? ? SAVE_ITEM(S5P_CLK_DIV3),
>> + ? ? SAVE_ITEM(S5P_CLK_DIV4),
>> + ? ? SAVE_ITEM(S5P_CLK_DIV5),
>> + ? ? SAVE_ITEM(S5P_CLK_DIV6),
>> + ? ? SAVE_ITEM(S5P_CLK_DIV7),
>> +
>> + ? ? /* Clock Main Gate */
>> + ? ? SAVE_ITEM(S5P_CLKGATE_MAIN0),
>> + ? ? SAVE_ITEM(S5P_CLKGATE_MAIN1),
>> + ? ? SAVE_ITEM(S5P_CLKGATE_MAIN2),
>> +
>> + ? ? /* Clock source Peri Gate */
>> + ? ? SAVE_ITEM(S5P_CLKGATE_PERI0),
>> + ? ? SAVE_ITEM(S5P_CLKGATE_PERI1),
>> +
>> + ? ? /* Clock source SCLK Gate */
>> + ? ? SAVE_ITEM(S5P_CLKGATE_SCLK0),
>> + ? ? SAVE_ITEM(S5P_CLKGATE_SCLK1),
>> +
>> + ? ? /* Clock IP Clock gate */
>> + ? ? SAVE_ITEM(S5P_CLKGATE_IP0),
>> + ? ? SAVE_ITEM(S5P_CLKGATE_IP1),
>> + ? ? SAVE_ITEM(S5P_CLKGATE_IP2),
>> + ? ? SAVE_ITEM(S5P_CLKGATE_IP3),
>> + ? ? SAVE_ITEM(S5P_CLKGATE_IP4),
>> +
>> + ? ? /* Clock Blcok and Bus gate */
>> + ? ? SAVE_ITEM(S5P_CLKGATE_BLOCK),
>> + ? ? SAVE_ITEM(S5P_CLKGATE_BUS0),
>> +
>> + ? ? /* Clock ETC */
>> + ? ? SAVE_ITEM(S5P_CLK_OUT),
>> + ? ? SAVE_ITEM(S5P_MDNIE_SEL),
>> +
>> + ? ? /* PWM Register */
>> + ? ? SAVE_ITEM(S3C2410_TCFG0),
>> + ? ? SAVE_ITEM(S3C2410_TCFG1),
>> + ? ? SAVE_ITEM(S3C64XX_TINT_CSTAT),
>> + ? ? SAVE_ITEM(S3C2410_TCON),
>> + ? ? SAVE_ITEM(S3C2410_TCNTB(0)),
>> + ? ? SAVE_ITEM(S3C2410_TCMPB(0)),
>> + ? ? SAVE_ITEM(S3C2410_TCNTO(0)),
>> +
>> + ? ? /* VIC 2 and 3*/
>> + ? ? SAVE_ITEM(VA_VIC2 + VIC_INT_SELECT),
>> + ? ? SAVE_ITEM(VA_VIC3 + VIC_INT_SELECT),
>> + ? ? SAVE_ITEM(VA_VIC2 + VIC_INT_ENABLE),
>> + ? ? SAVE_ITEM(VA_VIC3 + VIC_INT_ENABLE),
>> + ? ? SAVE_ITEM(VA_VIC2 + VIC_INT_SOFT),
>> + ? ? SAVE_ITEM(VA_VIC3 + VIC_INT_SOFT),
>
> doesn't the vic driver do this for you? if not, then would be better
> to change the vic to fix this.

The VIC driver does only for VIC0 and VIC1; thus, moving VIC2/3 from
pm.c to irq-pm.c should be fine.
Probably, a few machines supposed to be supported by this irq-pm
driver has only VIC0 and VIC1.
However, it'd be better if irq-pm supports both machines with VIC0/1 and VIC0-3.

>
>> +};
>> +
>> +void s5pv210_cpu_suspend(void)
>> +{
>> + ? ? unsigned long tmp;
>> +
>> + ? ? /* issue the standby signal into the pm unit. Note, we
>> + ? ? ?* issue a write-buffer drain just in case */
>> +
>> + ? ? tmp = 0;
>> +
>> + ? ? asm("b 1f\n\t"
>> + ? ? ? ? ".align 5\n\t"
>> + ? ? ? ? "1:\n\t"
>> + ? ? ? ? "mcr p15, 0, %0, c7, c10, 5\n\t"
>> + ? ? ? ? "mcr p15, 0, %0, c7, c10, 4\n\t"
>> + ? ? ? ? ".word 0xe320f003" : : "r" (tmp));
>
> why .word? if there's a compiler problem then make a comment about
> what instruction is being synthesised and why.

".word 0xe320f003" may be replaced by "wfi". (wait-for-interrupt)

>
>> + ? ? /* we should never get past here */
>> + ? ? panic("sleep resumed to originator?");
>> +}
>> +
>> +static void s5pv210_pm_prepare(void)
>> +{
>> + ? ? unsigned int tmp;
>> +
>> + ? ? /* ensure at least INFORM0 has the resume address */
>> + ? ? __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
>> +
>> + ? ? tmp = __raw_readl(S5P_SLEEP_CFG);
>> + ? ? tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
>> + ? ? __raw_writel(tmp, S5P_SLEEP_CFG);
>> +
>> + ? ? /* WFI for SLEEP mode configuration by SYSCON */
>> + ? ? tmp = __raw_readl(S5P_PWR_CFG);
>> + ? ? tmp &= S5P_CFG_WFI_CLEAN;
>> + ? ? tmp |= S5P_CFG_WFI_SLEEP;
>> + ? ? __raw_writel(tmp, S5P_PWR_CFG);
>> +
>> + ? ? /* SYSCON interrupt handling disable */
>> + ? ? tmp = __raw_readl(S5P_OTHERS);
>> + ? ? tmp |= S5P_OTHER_SYSC_INTOFF;
>> + ? ? __raw_writel(tmp, S5P_OTHERS);
>> +
>> + ? ? __raw_writel(0xffffffff, (VA_VIC0 + VIC_INT_ENABLE_CLEAR));
>> + ? ? __raw_writel(0xffffffff, (VA_VIC1 + VIC_INT_ENABLE_CLEAR));
>> + ? ? __raw_writel(0xffffffff, (VA_VIC2 + VIC_INT_ENABLE_CLEAR));
>> + ? ? __raw_writel(0xffffffff, (VA_VIC3 + VIC_INT_ENABLE_CLEAR));

It appears to be omitting VIC_INT_SOFT_CLEAR. I'm not sure whether
this is also required as VIC_INT_ENABLE_CLEAR does; however, we've
been doing __raw_writel(0xffffffff, (VA_VICx + VIC_INT_SOFT_CLEAR) as
well.

Clearing pending external interrupt when entering a suspend may be
added here. Sometimes, uncleared pending external interrupts may be
problematic for a sleep; i.e., having waking-up interrupts pending
while entering a sleep may be not too pleasant. "writel(0xff,
S5P_WKUP_INT_PEND**_**);" will do the work. I don't sure whether this
is really "required" for recent S5PV210/S5PC110; however, clearing
pending interrupts improved the stability for the old release of
S5PC110.

>> +
>> + ? ? s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
>> +}
>> +
>> +static int s5pv210_pm_add(struct sys_device *sysdev)
>> +{
>> + ? ? pm_cpu_prep = s5pv210_pm_prepare;
>> + ? ? pm_cpu_sleep = s5pv210_cpu_suspend;
>> +
>> + ? ? return 0;
>> +}
>> +
>> +static int s5pv210_pm_resume(struct sys_device *dev)
>> +{
>> + ? ? u32 tmp;
>> +
>> + ? ? tmp = __raw_readl(S5P_OTHERS);
>> + ? ? tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | \
>> + ? ? ? ? ? ? S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART);
>> + ? ? __raw_writel(tmp , S5P_OTHERS);
>> +
>> + ? ? s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
>> +
>> + ? ? return 0;
>> +}

I don't know how may "printk"s exist after s3c_pm_enter is returned
and before this resume function is called. However, printk's (and
debug messages) between these two often generate broken characters on
UART terminal. It may be better if S5P_OTHERS setting is done much
earlier; e.g., at arch/arm/plat-samsung/pm.c:s3c_pm_enter.

However, this operation may be done at the boot-loader; in such a
case, this doesn't matter at all.

>> +
>> +static struct sysdev_driver s5pv210_pm_driver = {
>> + ? ? .add ? ? ? ? ? ?= s5pv210_pm_add,
>> + ? ? .resume ? ? ? ? = s5pv210_pm_resume,
>> +};
>> +
>> +static __init int s5pv210_pm_drvinit(void)
>> +{
>> + ? ? return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver);
>> +}
>> +arch_initcall(s5pv210_pm_drvinit);
>> diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
>> new file mode 100644
>> index 0000000..b7f8272
>> --- /dev/null
>> +++ b/arch/arm/mach-s5pv210/sleep.S
>> @@ -0,0 +1,166 @@
>> +/* linux/arch/arm/mach-s5pv210/sleep.S
>> + *
>> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
>> + * ? ? ? ? ? http://www.samsung.com
>> + *
>> + * S5PV210 power Manager (Suspend-To-RAM) support
>> + *
>> + * Based on S3C2410 sleep code by:
>> + * ? Ben Dooks, (c) 2004 Simtec Electronics
>> + *
>> + * Based on PXA/SA1100 sleep code by:
>> + * ? Nicolas Pitre, (c) 2002 Monta Vista Software Inc
>> + * ? Cliff Brake, (c) 2001
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
>> + * GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program; if not, write to the Free Software
>> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA ?02111-1307 ?USA
>> +*/
>> +
>> +#include <linux/linkage.h>
>> +#include <asm/assembler.h>
>> +#include <asm/memory.h>
>> +
>> + ? ? .text
>> +
>> + ? ? /* s3c_cpu_save
>> + ? ? ?*
>> + ? ? ?* entry:
>> + ? ? ?* ? ? ?r0 = save address (virtual addr of s3c_sleep_save_phys)
>> + ? ? */
>> +
>> +ENTRY(s3c_cpu_save)
>> +
>> + ? ? stmfd ? sp!, { r3 - r12, lr }
>> +
>> + ? ? mrc ? ? p15, 0, r4, c13, c0, 0 ?@ FCSE/PID
>> + ? ? mrc ? ? p15, 0, r5, c3, c0, 0 ? @ Domain ID
>> + ? ? mrc ? ? p15, 0, r6, c2, c0, 0 ? @ Translation Table BASE0
>> + ? ? mrc ? ? p15, 0, r7, c2, c0, 1 ? @ Translation Table BASE1
>> + ? ? mrc ? ? p15, 0, r8, c2, c0, 2 ? @ Translation Table Control
>> + ? ? mrc ? ? p15, 0, r9, c1, c0, 0 ? @ Control register
>> + ? ? mrc ? ? p15, 0, r10, c1, c0, 1 ?@ Auxiliary control register
>> + ? ? mrc ? ? p15, 0, r11, c1, c0, 2 ?@ Co-processor access controls
>> + ? ? mrc ? ? p15, 0, r12, c10, c2, 0 @ Read PRRR
>> + ? ? mrc ? ? p15, 0, r3, c10, c2, 1 ?@ READ NMRR
>> +
>> + ? ? stmia ? r0, { r3 - r13 }
>> +
>> + ? ? bl ? ? ?s3c_pm_cb_flushcache
>> +
>> + ? ? ldr ? ? r0, =pm_cpu_sleep
>> + ? ? ldr ? ? r0, [ r0 ]
>> + ? ? mov ? ? pc, r0
>> +
>> +resume_with_mmu:
>> + ? ? /* delete added mmu table list */
>
> hmm, where is this being added?
> also, a better description on what it is doing would be better.
>
>> + ? ? ldr ? ? r9 , =(PAGE_OFFSET - PHYS_OFFSET)
>> + ? ? add ? ? r4, r4, r9
>> + ? ? str ? ? r12, [r4]
>> +
>> + ? ? ldmfd ? sp!, { r3 - r12, pc }
>> +
>> + ? ? .ltorg
>> +
>> + ? ? .data
>> +
>> + ? ? .global s3c_sleep_save_phys
>> +s3c_sleep_save_phys:
>> + ? ? .word ? 0
>> +
>> + ? ? /* sleep magic, to allow the bootloader to check for an valid
>> + ? ? ?* image to resume to. Must be the first word before the
>> + ? ? ?* s3c_cpu_resume entry.
>> + ? ? */
>> +
>> + ? ? .word ? 0x2bedf00d
>> +
>> + ? ? /* s3c_cpu_resume
>> + ? ? ?*
>> + ? ? ?* resume code entry for bootloader to call
>> + ? ? ?*
>> + ? ? ?* we must put this code here in the data segment as we have no
>> + ? ? ?* other way of restoring the stack pointer after sleep, and we
>> + ? ? ?* must not write to the code segment (code is read-only)
>> + ? ? */
>> +
>> +ENTRY(s3c_cpu_resume)
>> + ? ? mov ? ? r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
>> + ? ? msr ? ? cpsr_c, r0
>> +
>> + ? ? mov ? ? r1, #0
>> + ? ? mcr ? ? p15, 0, r1, c8, c7, 0 ? ? ? ? ? @@ invalidate TLBs
>> + ? ? mcr ? ? p15, 0, r1, c7, c5, 0 ? ? ? ? ? @@ invalidate I Cache
>> +
>> + ? ? ldr ? ? r0, s3c_sleep_save_phys ? ? ? ? @ address of restore block
>> + ? ? ldmia ? r0, { r3 - r13 }
>> +
>> + ? ? mcr ? ? p15, 0, r4, c13, c0, 0 ? ? ? ? ?@ FCSE/PID
>> + ? ? mcr ? ? p15, 0, r5, c3, c0, 0 ? ? ? ? ? @ Domain ID
>> +
>> + ? ? mcr ? ? p15, 0, r8, c2, c0, 2 ? ? ? ? ? @ Translation Table Control
>> + ? ? mcr ? ? p15, 0, r7, c2, c0, 1 ? ? ? ? ? @ Translation Table BASE1
>> + ? ? mcr ? ? p15, 0, r6, c2, c0, 0 ? ? ? ? ? @ Translation Table BASE0
>> +
>> + ? ? mcr ? ? p15, 0, r10, c1, c0, 1 ? ? ? ? ?@ Auxiliary control register
>> +
>> + ? ? mov ? ? r0, #0
>> + ? ? mcr ? ? p15, 0, r0, c8, c7, 0 ? ? ? ? ? @ Invalidate I & D TLB
>> +
>> + ? ? mov ? ? r0, #0 ? ? ? ? ? ? ? ? ? ? ? ? ?@ restore copro access
>> + ? ? mcr ? ? p15, 0, r11, c1, c0, 2 ? ? ? ? ?@ Co-processor access
>> + ? ? mcr ? ? p15, 0, r0, c7, c5, 4
>> +
>> + ? ? mcr ? ? p15, 0, r12, c10, c2, 0 ? ? ? ? @ write PRRR
>> + ? ? mcr ? ? p15, 0, r3, c10, c2, 1 ? ? ? ? ?@ write NMRR
>> +
>> + ? ? /* Calculate first section address into r8
>> + ? ? ?* In Cotex-A8 case, When MMU turn on, MMU is reseted.
>
> i'd fix this typo.
>
>> + ? ? ?* So, before call resume_with_mmu, backup originally data.
>> + ? ? */
>> +
>> + ? ? mov ? ? r4, r6
>> + ? ? mov ? ? r4, r4, LSR #14
>> + ? ? mov ? ? r4, r4, LSL #14
>> +
>> + ? ? /* Load TLB Base address from INFORM0 */
>
> do you mean mmu page table?
>
>> + ? ? ldr ? ? r11, =0xe010f000
>> + ? ? ldr ? ? r10, [r11, #0]
>> + ? ? mov ? ? r10, r10, LSR #18
>> + ? ? bic ? ? r10, r10, #0x3
>> + ? ? orr ? ? r4, r4, r10
>> +
>> + ? ? /* calculate mmu list value into r9 */
>> + ? ? mov ? ? r10, r10, LSL #18
>> + ? ? ldr ? ? r5, =0x40e
>> + ? ? orr ? ? r10, r10, r5
>> +
>> + ? ? /* back up originally data */
>> +
>> + ? ? ldr ? ? r12, [r4]
>> +
>> + ? ? /* Added list about mmu */
>> + ? ? str ? ? r10, [r4]
>
>
>
>> + ? ? ldr ? ? r2, =resume_with_mmu
>> + ? ? mcr ? ? p15, 0, r9, c1, c0, 0 ? ? ? ? ? @ turn on MMU, etc
>> +
>> + ? ? nop
>> + ? ? nop
>> + ? ? nop
>> + ? ? nop
>> + ? ? nop ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ second-to-last before mmu
>> +
>> + ? ? mov ? ? pc, r2 ? ? ? ? ? ? ? ? ? ? ? ? ?@ go back to virtual address
>> +
>> + ? ? .ltorg
>> diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
>> index 39c242b..d04ae49 100644
>> --- a/arch/arm/plat-s5p/Makefile
>> +++ b/arch/arm/plat-s5p/Makefile
>> @@ -18,3 +18,5 @@ obj-y ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += clock.o
>> ?obj-y ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?+= irq.o
>> ?obj-$(CONFIG_S5P_EXT_INT) ? ?+= irq-eint.o
>>
>> +obj-$(CONFIG_PM) ? ? ? ? ? ? += pm.o
>> +obj-$(CONFIG_PM) ? ? ? ? ? ? += irq-pm.o
>> diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
>> index 3fb3a3a..9ffdd62 100644
>> --- a/arch/arm/plat-s5p/include/plat/irqs.h
>> +++ b/arch/arm/plat-s5p/include/plat/irqs.h
>> @@ -94,4 +94,6 @@
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ((irq) - S5P_EINT_BASE1) : \
>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ((irq) + 16 - S5P_EINT_BASE2))
>>
>> +#define IRQ_EINT_BIT(x) ? ? ? ? ? ? ?EINT_OFFSET(x)
>> +
>> ?#endif /* __ASM_PLAT_S5P_IRQS_H */
>> diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
>> new file mode 100644
>> index 0000000..03e83a3
>> --- /dev/null
>> +++ b/arch/arm/plat-s5p/irq-pm.c
>> @@ -0,0 +1,108 @@
>> +/* linux/arch/arm/plat-s5p/irq-pm.c
>> + *
>> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
>> + * ? ? ? ? ? http://www.samsung.com
>> + *
>> + * Based on arch/arm/plat-s3c24xx/irq-pm.c,
>> + * Copyright (c) 2003,2004 Simtec Electronics
>> + * ? Ben Dooks <ben at simtec.co.uk>
>> + * ? http://armlinux.simtec.co.uk/
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +#include <linux/init.h>
>> +#include <linux/module.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/sysdev.h>
>> +
>> +#include <plat/cpu.h>
>> +#include <plat/irqs.h>
>> +#include <plat/pm.h>
>> +#include <mach/map.h>
>> +
>> +#include <mach/regs-gpio.h>
>> +#include <mach/regs-irq.h>
>> +
>> +/* state for IRQs over sleep */
>> +
>> +/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
>> + * as wakeup sources
>> + *
>> + * set bit to 1 in allow bitfield to enable the wakeup settings on it
>> +*/
>> +
>> +unsigned long s3c_irqwake_intallow ? = 0x00000006L;
>> +unsigned long s3c_irqwake_eintallow ?= 0xffffffffL;
>> +
>> +int s3c_irq_wake(unsigned int irqno, unsigned int state)
>> +{
>> + ? ? unsigned long irqbit;
>> +
>> + ? ? switch (irqno) {
>> + ? ? case IRQ_RTC_TIC:
>> + ? ? case IRQ_RTC_ALARM:
>> + ? ? ? ? ? ? irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM);
>> + ? ? ? ? ? ? if (!state)
>> + ? ? ? ? ? ? ? ? ? ? s3c_irqwake_intmask |= irqbit;
>> + ? ? ? ? ? ? else
>> + ? ? ? ? ? ? ? ? ? ? s3c_irqwake_intmask &= ~irqbit;
>> + ? ? ? ? ? ? break;
>> + ? ? default:
>> + ? ? ? ? ? ? return -ENOENT;
>> + ? ? }
>> + ? ? return 0;
>> +}
>> +
>> +/* this lot should be really saved by the IRQ code */
>> +/* VICXADDRESSXX initilaization to be needed */
>> +static struct sleep_save irq_save[] = {
>> + ? ? SAVE_ITEM(VA_VIC0 + VIC_INT_SELECT),
>> + ? ? SAVE_ITEM(VA_VIC1 + VIC_INT_SELECT),
>> +
>> + ? ? SAVE_ITEM(VA_VIC0 + VIC_INT_ENABLE),
>> + ? ? SAVE_ITEM(VA_VIC1 + VIC_INT_ENABLE),
>> +
>> + ? ? SAVE_ITEM(VA_VIC0 + VIC_INT_SOFT),
>> + ? ? SAVE_ITEM(VA_VIC1 + VIC_INT_SOFT),

S5PV210 has VIC2,3 as well. Maybe those can be moved from pm.c to here.

>> +};
>> +
>> +static struct sleep_save eint_save[] = {
>> + ? ? SAVE_ITEM(S5P_EINT_CON(0)),
>> + ? ? SAVE_ITEM(S5P_EINT_CON(1)),
>> + ? ? SAVE_ITEM(S5P_EINT_CON(2)),
>> + ? ? SAVE_ITEM(S5P_EINT_CON(3)),
>> +
>> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(0)),
>> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(1)),
>> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(2)),
>> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(3)),
>> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(4)),
>> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(5)),
>> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(6)),
>> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(7)),
>> +
>> + ? ? SAVE_ITEM(S5P_EINT_MASK(0)),
>> + ? ? SAVE_ITEM(S5P_EINT_MASK(1)),
>> + ? ? SAVE_ITEM(S5P_EINT_MASK(2)),
>> + ? ? SAVE_ITEM(S5P_EINT_MASK(3)),
>> +};
>> +
>> +int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
>> +{
>> + ? ? s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
>> + ? ? s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
>> +
>> + ? ? return 0;
>> +}
>> +
>> +int s3c24xx_irq_resume(struct sys_device *dev)
>> +{
>> + ? ? s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
>> + ? ? s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
>> +
>> + ? ? return 0;
>> +}
>> +
>> diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-s5p/pm.c
>> new file mode 100644
>> index 0000000..d592b63
>> --- /dev/null
>> +++ b/arch/arm/plat-s5p/pm.c
>> @@ -0,0 +1,52 @@
>> +/* linux/arch/arm/plat-s5p/pm.c
>> + *
>> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
>> + * ? ? ? ? ? http://www.samsung.com
>> + *
>> + * S5P Power Manager (Suspend-To-RAM) support
>> + *
>> + * Based on arch/arm/plat-s3c24xx/pm.c
>> + * Copyright (c) 2004,2006 Simtec Electronics
>> + * ? Ben Dooks <ben at simtec.co.uk>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> +*/
>> +
>> +#include <linux/suspend.h>
>> +#include <plat/pm.h>
>> +
>> +#define PFX "s5p pm: "
>> +
>> +/* s3c_pm_check_resume_pin
>> + *
>> + * check to see if the pin is configured correctly for sleep mode, and
>> + * make any necessary adjustments if it is not
>> +*/
>> +
>> +static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
>> +{
>> + ? ? /* nothing here yet */
>> +}
>> +
>> +/* s3c_pm_configure_extint
>> + *
>> + * configure all external interrupt pins
>> +*/
>> +
>> +void s3c_pm_configure_extint(void)
>> +{
>> + ? ? /* nothing here yet */
>> +}
>> +
>> +void s3c_pm_restore_core(void)
>> +{
>> + ? ? /* nothing here yet */
>> +}
>> +
>> +void s3c_pm_save_core(void)
>> +{
>> + ? ? /* nothing here yet */
>> +}
>> +
>> diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
>> index 7df03f8..9652820 100644
>> --- a/arch/arm/plat-samsung/pm-gpio.c
>> +++ b/arch/arm/plat-samsung/pm-gpio.c
>> @@ -192,7 +192,7 @@ struct s3c_gpio_pm s3c_gpio_pm_2bit = {
>> ? ? ? .resume = s3c_gpio_pm_2bit_resume,
>> ?};
>>
>> -#ifdef CONFIG_ARCH_S3C64XX
>> +#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
>> ?static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
>> ?{
>> ? ? ? chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
>> @@ -302,7 +302,7 @@ struct s3c_gpio_pm s3c_gpio_pm_4bit = {
>> ? ? ? .save ? = s3c_gpio_pm_4bit_save,
>> ? ? ? .resume = s3c_gpio_pm_4bit_resume,
>> ?};
>> -#endif /* CONFIG_ARCH_S3C64XX */
>> +#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
>>
>> ?/**
>> ? * s3c_pm_save_gpio() - save gpio chip data for suspend
>> --
>> 1.6.2.5
>>
>
>
> --
> --
> Ben
>
> Q: ? ? ?What's a light-year?
> A: ? ? ?One-third less calories than a regular year.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
MyungJoo Ham (???), Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858


From Hiroshi.DOYU at nokia.com  Tue Jun  1 01:30:46 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Tue,  1 Jun 2010 08:30:46 +0300
Subject: [PATCH 7/8] omap iommu: move iommu_disable at fault to the above layer
In-Reply-To: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
References: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
Message-ID: <1275370247-15888-7-git-send-email-Hiroshi.DOYU@nokia.com>

The function prefix "omap2_iommu_" indicates that the prefixed
function belongs to "omap2_iommu_ops" to provide iommu basic
functionalities for the above layers. It's better to avoid the
prefixed function called in the same prefixed ones internally, like
nested here. Now "iommu_disable" is called just after fault_isr() in
the above layer. This is a little bit more sensible to keep the
consistency of module layers.

Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/mach-omap2/iommu2.c |    2 +-
 arch/arm/plat-omap/iommu.c   |    2 ++
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index edf7cd4..14ee686 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -172,7 +172,7 @@ static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
 	printk("\n");
 
 	iommu_write_reg(obj, stat, MMU_IRQSTATUS);
-	omap2_iommu_disable(obj);
+
 	return stat;
 }
 
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 688ae66..a202a2c 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -800,6 +800,8 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
 	if (!stat)
 		return IRQ_HANDLED;
 
+	iommu_disable(obj);
+
 	iopgd = iopgd_offset(obj, da);
 
 	if (!iopgd_is_table(*iopgd)) {
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Tue Jun  1 01:30:43 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Tue,  1 Jun 2010 08:30:43 +0300
Subject: [PATCH 4/8] omap iommu: Fix Memory leak
In-Reply-To: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
References: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
Message-ID: <1275370247-15888-4-git-send-email-Hiroshi.DOYU@nokia.com>

From: Satish <x0124230 at ti.com>

The memory allocated for sgt structure is not freed on error
when sg_alloc_table is called in sgtable_alloc().

Signed-off-by: Satish Kumar <x0124230 at ti.com>
Signed-off-by: Manjunatha GK <manjugk at ti.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: vimal singh <vimal.newwork at gmail.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/plat-omap/iovmm.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index e43983b..8ce0de2 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -140,8 +140,10 @@ static struct sg_table *sgtable_alloc(const size_t bytes, u32 flags)
 		return ERR_PTR(-ENOMEM);
 
 	err = sg_alloc_table(sgt, nr_entries, GFP_KERNEL);
-	if (err)
+	if (err) {
+		kfree(sgt);
 		return ERR_PTR(err);
+	}
 
 	pr_debug("%s: sgt:%p(%d entries)\n", __func__, sgt, nr_entries);
 
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Tue Jun  1 01:30:41 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Tue,  1 Jun 2010 08:30:41 +0300
Subject: [PATCH 2/8] omap iommu: Introduce iopgd_is_table MACRO
In-Reply-To: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
References: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
Message-ID: <1275370247-15888-2-git-send-email-Hiroshi.DOYU@nokia.com>

A bit more strict comparison.

Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/plat-omap/iommu.c     |    8 ++++----
 arch/arm/plat-omap/iopgtable.h |    2 ++
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index bc094db..341c481 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -653,7 +653,7 @@ void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd, u32 **ppte)
 	if (!*iopgd)
 		goto out;
 
-	if (*iopgd & IOPGD_TABLE)
+	if (iopgd_is_table(*iopgd))
 		iopte = iopte_offset(iopgd, da);
 out:
 	*ppgd = iopgd;
@@ -670,7 +670,7 @@ static size_t iopgtable_clear_entry_core(struct iommu *obj, u32 da)
 	if (!*iopgd)
 		return 0;
 
-	if (*iopgd & IOPGD_TABLE) {
+	if (iopgd_is_table(*iopgd)) {
 		int i;
 		u32 *iopte = iopte_offset(iopgd, da);
 
@@ -745,7 +745,7 @@ static void iopgtable_clear_entry_all(struct iommu *obj)
 		if (!*iopgd)
 			continue;
 
-		if (*iopgd & IOPGD_TABLE)
+		if (iopgd_is_table(*iopgd))
 			iopte_free(iopte_offset(iopgd, 0));
 
 		*iopgd = 0;
@@ -785,7 +785,7 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
 
 	iopgd = iopgd_offset(obj, da);
 
-	if (!(*iopgd & IOPGD_TABLE)) {
+	if (!iopgd_is_table(*iopgd)) {
 		dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__,
 			da, iopgd, *iopgd);
 		return IRQ_NONE;
diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h
index ab23b6a..f2e6b64 100644
--- a/arch/arm/plat-omap/iopgtable.h
+++ b/arch/arm/plat-omap/iopgtable.h
@@ -63,6 +63,8 @@
 #define IOPGD_SECTION		(2 << 0)
 #define IOPGD_SUPER		(1 << 18 | 2 << 0)
 
+#define iopgd_is_table(x)	(((x) & 3) == IOPGD_TABLE)
+
 #define IOPTE_SMALL		(2 << 0)
 #define IOPTE_LARGE		(1 << 0)
 
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Tue Jun  1 01:30:44 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Tue,  1 Jun 2010 08:30:44 +0300
Subject: [PATCH 5/8] omap iommu: update irq mask to be specific about twl and
	tlb
In-Reply-To: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
References: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
Message-ID: <1275370247-15888-5-git-send-email-Hiroshi.DOYU@nokia.com>

From: Kanigeri, Hari <h-kanigeri2 at ti.com>

Revise the IRQ mask definitions to handle the  MMU faults related
to TWL fault as well as TLB miss fault.

Signed-off-by: Hari Kanigeri <h-kanigeri2 at ti.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/mach-omap2/iommu2.c |   12 ++++++++----
 1 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index e82da68..ebbdae2 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -44,9 +44,13 @@
 #define MMU_IRQ_EMUMISS		(1 << 2)
 #define MMU_IRQ_TRANSLATIONFAULT	(1 << 1)
 #define MMU_IRQ_TLBMISS		(1 << 0)
-#define MMU_IRQ_MASK	\
-	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_EMUMISS | \
-	 MMU_IRQ_TRANSLATIONFAULT)
+
+#define __MMU_IRQ_FAULT		\
+	(MMU_IRQ_MULTIHITFAULT | MMU_IRQ_EMUMISS | MMU_IRQ_TRANSLATIONFAULT)
+#define MMU_IRQ_MASK		\
+	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT | MMU_IRQ_TLBMISS)
+#define MMU_IRQ_TWL_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TABLEWALKFAULT)
+#define MMU_IRQ_TLB_MISS_MASK	(__MMU_IRQ_FAULT | MMU_IRQ_TLBMISS)
 
 /* MMU_CNTL */
 #define MMU_CNTL_SHIFT		1
@@ -96,7 +100,7 @@ static int omap2_iommu_enable(struct iommu *obj)
 	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
 	iommu_write_reg(obj, l, MMU_SYSCONFIG);
 
-	iommu_write_reg(obj, MMU_IRQ_MASK, MMU_IRQENABLE);
+	iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
 	iommu_write_reg(obj, pa, MMU_TTB);
 
 	l = iommu_read_reg(obj, MMU_CNTL);
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Tue Jun  1 01:30:47 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Tue,  1 Jun 2010 08:30:47 +0300
Subject: [PATCH 8/8] omap iommu: Make omap-iommu.o built-in
In-Reply-To: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
References: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
Message-ID: <1275370247-15888-8-git-send-email-Hiroshi.DOYU@nokia.com>

This is a platform device registration.

Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/mach-omap2/Makefile |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ea52b03..6c6d7c6 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -89,7 +89,10 @@ obj-$(CONFIG_OMAP3_EMU)			+= emu.o
 obj-$(CONFIG_OMAP_MBOX_FWK)		+= mailbox_mach.o
 mailbox_mach-objs			:= mailbox.o
 
-obj-$(CONFIG_OMAP_IOMMU)		:= iommu2.o omap-iommu.o
+obj-$(CONFIG_OMAP_IOMMU)		+= iommu2.o
+
+iommu-$(CONFIG_OMAP_IOMMU)		:= omap-iommu.o
+obj-y					+= $(iommu-m) $(iommu-y)
 
 i2c-omap-$(CONFIG_I2C_OMAP)		:= i2c.o
 obj-y					+= $(i2c-omap-m) $(i2c-omap-y)
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Tue Jun  1 01:30:40 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Tue,  1 Jun 2010 08:30:40 +0300
Subject: [PATCH 1/8] omap iommu: update ducati mmu irq define name
In-Reply-To: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
References: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
Message-ID: <1275370247-15888-1-git-send-email-Hiroshi.DOYU@nokia.com>

From: Kanigeri, Hari <h-kanigeri2 at ti.com>

2.6.34-rc6 kernel has the Ducati mmu irq define name changed, which is
resulting in compilation error.

Signed-off-by: Hari Kanigeri <h-kanigeri2 at ti.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/mach-omap2/omap-iommu.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index eb9bee7..f5a1aad 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -59,7 +59,7 @@ static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES];
 static struct iommu_device omap4_devices[] = {
 	{
 		.base = OMAP4_MMU1_BASE,
-		.irq = INT_44XX_DUCATI_MMU_IRQ,
+		.irq = OMAP44XX_IRQ_DUCATI_MMU,
 		.pdata = {
 			.name = "ducati",
 			.nr_tlb_entries = 32,
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Tue Jun  1 01:30:42 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Tue,  1 Jun 2010 08:30:42 +0300
Subject: [PATCH 3/8] omap iommu: Rename iopte_[p, v]addr -> iopte_page_[p,
	v]addr
In-Reply-To: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
References: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
Message-ID: <1275370247-15888-3-git-send-email-Hiroshi.DOYU@nokia.com>

Follow Linux pagetable accessor name convention.

Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/plat-omap/iopgtable.h |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-omap/iopgtable.h b/arch/arm/plat-omap/iopgtable.h
index f2e6b64..c3e93bb 100644
--- a/arch/arm/plat-omap/iopgtable.h
+++ b/arch/arm/plat-omap/iopgtable.h
@@ -72,12 +72,12 @@
 #define iopgd_index(da)		(((da) >> IOPGD_SHIFT) & (PTRS_PER_IOPGD - 1))
 #define iopgd_offset(obj, da)	((obj)->iopgd + iopgd_index(da))
 
-#define iopte_paddr(iopgd)	(*iopgd & ~((1 << 10) - 1))
-#define iopte_vaddr(iopgd)	((u32 *)phys_to_virt(iopte_paddr(iopgd)))
+#define iopgd_page_paddr(iopgd)	(*iopgd & ~((1 << 10) - 1))
+#define iopgd_page_vaddr(iopgd)	((u32 *)phys_to_virt(iopgd_page_paddr(iopgd)))
 
 /* to find an entry in the second-level page table. */
 #define iopte_index(da)		(((da) >> IOPTE_SHIFT) & (PTRS_PER_IOPTE - 1))
-#define iopte_offset(iopgd, da)	(iopte_vaddr(iopgd) + iopte_index(da))
+#define iopte_offset(iopgd, da)	(iopgd_page_vaddr(iopgd) + iopte_index(da))
 
 static inline u32 iotlb_init_entry(struct iotlb_entry *e, u32 da, u32 pa,
 				   u32 flags)
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Tue Jun  1 01:30:45 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Tue,  1 Jun 2010 08:30:45 +0300
Subject: [PATCH 6/8] omap iommu: add functionality to get TLB miss interrupt
In-Reply-To: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
References: <20100531.123637.28796762.Hiroshi.DOYU@nokia.com>
Message-ID: <1275370247-15888-6-git-send-email-Hiroshi.DOYU@nokia.com>

From: Kanigeri, Hari <h-kanigeri2 at ti.com>

In order to enable TLB miss interrupt, the TWL should be
disabled. This patch provides the functionality to get the
MMU fault interrupt for a TLB miss in the cases where the
users are working with the locked TLB entries and with TWL
disabled.
New interface is added to select twl and to enable TLB miss
interrupt.

Signed-off-by: Hari Kanigeri <h-kanigeri2 at ti.com>
Signed-off-by: Ramesh Gupta <grgupta at ti.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/mach-omap2/iommu2.c            |   32 ++++++++++++++++++++++++++----
 arch/arm/plat-omap/include/plat/iommu.h |    2 +
 arch/arm/plat-omap/iommu.c              |   17 ++++++++++++++++
 3 files changed, 46 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index ebbdae2..edf7cd4 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -65,6 +65,26 @@
 	 ((pgsz) == MMU_CAM_PGSZ_64K) ? 0xffff0000 :	\
 	 ((pgsz) == MMU_CAM_PGSZ_4K)  ? 0xfffff000 : 0)
 
+
+static void __iommu_set_twl(struct iommu *obj, bool on)
+{
+	u32 l = iommu_read_reg(obj, MMU_CNTL);
+
+	if (on)
+		iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
+	else
+		iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE);
+
+	l &= ~MMU_CNTL_MASK;
+	if (on)
+		l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
+	else
+		l |= (MMU_CNTL_MMU_EN);
+
+	iommu_write_reg(obj, l, MMU_CNTL);
+}
+
+
 static int omap2_iommu_enable(struct iommu *obj)
 {
 	u32 l, pa;
@@ -100,13 +120,9 @@ static int omap2_iommu_enable(struct iommu *obj)
 	l |= (MMU_SYS_IDLE_SMART | MMU_SYS_AUTOIDLE);
 	iommu_write_reg(obj, l, MMU_SYSCONFIG);
 
-	iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE);
 	iommu_write_reg(obj, pa, MMU_TTB);
 
-	l = iommu_read_reg(obj, MMU_CNTL);
-	l &= ~MMU_CNTL_MASK;
-	l |= (MMU_CNTL_MMU_EN | MMU_CNTL_TWL_EN);
-	iommu_write_reg(obj, l, MMU_CNTL);
+	__iommu_set_twl(obj, true);
 
 	return 0;
 }
@@ -122,6 +138,11 @@ static void omap2_iommu_disable(struct iommu *obj)
 	dev_dbg(obj->dev, "%s is shutting down\n", obj->name);
 }
 
+static void omap2_iommu_set_twl(struct iommu *obj, bool on)
+{
+	__iommu_set_twl(obj, false);
+}
+
 static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
 {
 	int i;
@@ -304,6 +325,7 @@ static const struct iommu_functions omap2_iommu_ops = {
 
 	.enable		= omap2_iommu_enable,
 	.disable	= omap2_iommu_disable,
+	.set_twl	= omap2_iommu_set_twl,
 	.fault_isr	= omap2_iommu_fault_isr,
 
 	.tlb_read_cr	= omap2_tlb_read_cr,
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 0752af9..33c7d41 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -80,6 +80,7 @@ struct iommu_functions {
 
 	int (*enable)(struct iommu *obj);
 	void (*disable)(struct iommu *obj);
+	void (*set_twl)(struct iommu *obj, bool on);
 	u32 (*fault_isr)(struct iommu *obj, u32 *ra);
 
 	void (*tlb_read_cr)(struct iommu *obj, struct cr_regs *cr);
@@ -143,6 +144,7 @@ extern void iotlb_cr_to_e(struct cr_regs *cr, struct iotlb_entry *e);
 extern u32 iotlb_cr_to_virt(struct cr_regs *cr);
 
 extern int load_iotlb_entry(struct iommu *obj, struct iotlb_entry *e);
+extern void iommu_set_twl(struct iommu *obj, bool on);
 extern void flush_iotlb_page(struct iommu *obj, u32 da);
 extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
 extern void flush_iotlb_all(struct iommu *obj);
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index 341c481..688ae66 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -370,6 +370,23 @@ void flush_iotlb_all(struct iommu *obj)
 }
 EXPORT_SYMBOL_GPL(flush_iotlb_all);
 
+/**
+ * iommu_set_twl - enable/disable table walking logic
+ * @obj:	target iommu
+ * @on:		enable/disable
+ *
+ * Function used to enable/disable TWL. If one wants to work
+ * exclusively with locked TLB entries and receive notifications
+ * for TLB miss then call this function to disable TWL.
+ */
+void iommu_set_twl(struct iommu *obj, bool on)
+{
+	clk_enable(obj->clk);
+	arch_iommu->set_twl(obj, on);
+	clk_disable(obj->clk);
+}
+EXPORT_SYMBOL_GPL(iommu_set_twl);
+
 #if defined(CONFIG_OMAP_IOMMU_DEBUG_MODULE)
 
 ssize_t iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t bytes)
-- 
1.7.1.rc1



From ben-linux at fluff.org  Tue Jun  1 01:32:55 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Tue, 1 Jun 2010 06:32:55 +0100
Subject: [PATCH v2] ARM: S5PV210: Add Power Management Support
In-Reply-To: <AANLkTikdkOvvdsQvwuqS9QFv6yIM7LQJb24NrTi-RA-s@mail.gmail.com>
References: <1275356164-7896-1-git-send-email-kgene.kim@samsung.com>
	<20100601020329.GT4720@trinity.fluff.org>
	<AANLkTikdkOvvdsQvwuqS9QFv6yIM7LQJb24NrTi-RA-s@mail.gmail.com>
Message-ID: <20100601053255.GP7248@trinity.fluff.org>

On Tue, Jun 01, 2010 at 02:13:18PM +0900, MyungJoo Ham wrote:
> On Tue, Jun 1, 2010 at 11:03 AM, Ben Dooks <ben-linux at fluff.org> wrote:
> >
> > On Tue, Jun 01, 2010 at 10:36:04AM +0900, Kukjin Kim wrote:
> >> From: Jongpill Lee <boyko.lee at samsung.com>
> >>
> >> This patch adds suspend-to-ram support for S5PV210.
> >>
> >> Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
> >> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> >> ---
> >> Changes since v1:
> >>
> >> 1. Fixed comments as per comments from Ben Dooks
> >> 2. Removed redunt #if defined(CONFIG_PM)
> >> 3. Removed redunt including header files
> >> 4. Removed <mach/pm.h> and <plat/pm-s5p.h>
> >> 5. Moved 's5pv210_core_save' into machine directory
> >> 6. Moved sleep.S into machine directory for S5P SoCs compatibility
> >> 7. Added CF retension configuration when wake-up
> >>
> >> This patch is based on Linus' master (2.6.35-rc1)
> >>
> >> ?arch/arm/mach-s5pv210/Kconfig ? ? ? ? ? ? ? ? ? | ? ?6 +
> >> ?arch/arm/mach-s5pv210/Makefile ? ? ? ? ? ? ? ? ?| ? ?1 +
> >> ?arch/arm/mach-s5pv210/include/mach/pm-core.h ? ?| ? 44 ++++++
> >> ?arch/arm/mach-s5pv210/include/mach/regs-clock.h | ? ?5 +-
> >> ?arch/arm/mach-s5pv210/mach-smdkc110.c ? ? ? ? ? | ? ?2 +
> >> ?arch/arm/mach-s5pv210/mach-smdkv210.c ? ? ? ? ? | ? ?3 +
> >> ?arch/arm/mach-s5pv210/pm.c ? ? ? ? ? ? ? ? ? ? ?| ?180 +++++++++++++++++++++++
> >> ?arch/arm/mach-s5pv210/sleep.S ? ? ? ? ? ? ? ? ? | ?166 +++++++++++++++++++++
> >> ?arch/arm/plat-s5p/Makefile ? ? ? ? ? ? ? ? ? ? ?| ? ?2 +
> >> ?arch/arm/plat-s5p/include/plat/irqs.h ? ? ? ? ? | ? ?2 +
> >> ?arch/arm/plat-s5p/irq-pm.c ? ? ? ? ? ? ? ? ? ? ?| ?108 ++++++++++++++
> >> ?arch/arm/plat-s5p/pm.c ? ? ? ? ? ? ? ? ? ? ? ? ?| ? 52 +++++++
> >> ?arch/arm/plat-samsung/pm-gpio.c ? ? ? ? ? ? ? ? | ? ?4 +-
> >> ?13 files changed, 572 insertions(+), 3 deletions(-)
> >> ?create mode 100644 arch/arm/mach-s5pv210/include/mach/pm-core.h
> >> ?create mode 100644 arch/arm/mach-s5pv210/pm.c
> >> ?create mode 100644 arch/arm/mach-s5pv210/sleep.S
> >> ?create mode 100644 arch/arm/plat-s5p/irq-pm.c
> >> ?create mode 100644 arch/arm/plat-s5p/pm.c
> >>
> >> diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
> >> index 0761eac..86cca1b 100644
> >> --- a/arch/arm/mach-s5pv210/Kconfig
> >> +++ b/arch/arm/mach-s5pv210/Kconfig
> >> @@ -14,6 +14,7 @@ config CPU_S5PV210
> >> ? ? ? select PLAT_S5P
> >> ? ? ? select S3C_PL330_DMA
> >> ? ? ? select S5P_EXT_INT
> >> + ? ? select S5PV210_PM if PM
> >> ? ? ? help
> >> ? ? ? ? Enable S5PV210 CPU support
> >>
> >> @@ -88,4 +89,9 @@ config MACH_SMDKC110
> >> ? ? ? ? Machine support for Samsung SMDKC110
> >> ? ? ? ? S5PC110(MCP) is one of package option of S5PV210
> >>
> >> +config S5PV210_PM
> >> + ? ? bool
> >> + ? ? help
> >> + ? ? ? Power Management code common to S5PV210
> >> +
> >> ?endif
> >> diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
> >> index 30be9a6..59382ec 100644
> >> --- a/arch/arm/mach-s5pv210/Makefile
> >> +++ b/arch/arm/mach-s5pv210/Makefile
> >> @@ -14,6 +14,7 @@ obj- ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?:=
> >>
> >> ?obj-$(CONFIG_CPU_S5PV210) ? ?+= cpu.o init.o clock.o dma.o gpiolib.o
> >> ?obj-$(CONFIG_CPU_S5PV210) ? ?+= setup-i2c0.o
> >> +obj-$(CONFIG_S5PV210_PM) ? ? += pm.o sleep.o
> >>
> >> ?# machine support
> >>
> >> diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
> >> new file mode 100644
> >> index 0000000..ca3f827
> >> --- /dev/null
> >> +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
> >> @@ -0,0 +1,44 @@
> >> +/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
> >> + *
> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> >> + * ? ? ? ? ? http://www.samsung.com
> >> + *
> >> + * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
> >> + * Copyright 2008 Simtec Electronics
> >> + * ? ? ?Ben Dooks <ben at simtec.co.uk>
> >> + * ? ? ?http://armlinux.simtec.co.uk/
> >> + *
> >> + * S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License version 2 as
> >> + * published by the Free Software Foundation.
> >> +*/
> >> +
> >> +static inline void s3c_pm_debug_init_uart(void)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> +static inline void s3c_pm_arch_prepare_irqs(void)
> >> +{
> >> + ? ? __raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
> >> + ? ? __raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
> >> +}
> >> +
> >> +static inline void s3c_pm_arch_stop_clocks(void)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> +static inline void s3c_pm_arch_show_resume_irqs(void)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
> >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct pm_uart_save *save)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
> >> index 2a25ab4..f4a443a 100644
> >> --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
> >> +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
> >> @@ -157,8 +157,11 @@
> >> ?#define S5P_SLEEP_CFG_USBOSC_EN ? ? ? ? ? ? ?(1 << 1)
> >>
> >> ?/* OTHERS Resgister */
> >> +#define S5P_OTHERS_RET_IO ? ? ? ? ? ?(1 << 31)
> >> +#define S5P_OTHERS_RET_CF ? ? ? ? ? ?(1 << 30)
> >> +#define S5P_OTHERS_RET_MMC ? ? ? ? ? (1 << 29)
> >> +#define S5P_OTHERS_RET_UART ? ? ? ? ?(1 << 28)
> >> ?#define S5P_OTHERS_USB_SIG_MASK ? ? ? ? ? ? ?(1 << 16)
> >> -#define S5P_OTHERS_MIPI_DPHY_EN ? ? ? ? ? ? ?(1 << 28)
> >>
> >> ?/* MIPI */
> >> ?#define S5P_MIPI_DPHY_EN ? ? ? ? ? ? (3)
> >> diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
> >> index 4c8903c..ebb4832 100644
> >> --- a/arch/arm/mach-s5pv210/mach-smdkc110.c
> >> +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
> >> @@ -25,6 +25,7 @@
> >> ?#include <plat/s5pv210.h>
> >> ?#include <plat/devs.h>
> >> ?#include <plat/cpu.h>
> >> +#include <plat/pm.h>
> >>
> >> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
> >> ?#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | ? ? ? ?\
> >> @@ -86,6 +87,7 @@ static void __init smdkc110_map_io(void)
> >>
> >> ?static void __init smdkc110_machine_init(void)
> >> ?{
> >> + ? ? s3c_pm_init();
> >> ? ? ? platform_add_devices(smdkc110_devices, ARRAY_SIZE(smdkc110_devices));
> >> ?}
> >>
> >> diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
> >> index 0d46279..ba30b5d 100644
> >> --- a/arch/arm/mach-s5pv210/mach-smdkv210.c
> >> +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
> >> @@ -27,6 +27,7 @@
> >> ?#include <plat/cpu.h>
> >> ?#include <plat/adc.h>
> >> ?#include <plat/ts.h>
> >> +#include <plat/pm.h>
> >>
> >> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
> >> ?#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | ? ? ? ?\
> >> @@ -96,6 +97,8 @@ static void __init smdkv210_map_io(void)
> >>
> >> ?static void __init smdkv210_machine_init(void)
> >> ?{
> >> + ? ? s3c_pm_init();
> >> +
> >> ? ? ? s3c24xx_ts_set_platdata(&s3c_ts_platform);
> >> ? ? ? platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
> >> ?}
> >> diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
> >> new file mode 100644
> >> index 0000000..0690332
> >> --- /dev/null
> >> +++ b/arch/arm/mach-s5pv210/pm.c
> >> @@ -0,0 +1,180 @@
> >> +/* linux/arch/arm/mach-s5pv210/pm.c
> >> + *
> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> >> + * ? ? ? ? ? http://www.samsung.com
> >> + *
> >> + * S5PV210 - Power Management support
> >> + *
> >> + * Based on arch/arm/mach-s3c2410/pm.c
> >> + * Copyright (c) 2006 Simtec Electronics
> >> + * ? Ben Dooks <ben at simtec.co.uk>
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License version 2 as
> >> + * published by the Free Software Foundation.
> >> +*/
> >> +
> >> +#include <linux/init.h>
> >> +#include <linux/suspend.h>
> >> +#include <linux/io.h>
> >> +
> >> +#include <plat/cpu.h>
> >> +#include <plat/pm.h>
> >> +#include <plat/regs-timer.h>
> >> +
> >> +#include <mach/regs-irq.h>
> >> +#include <mach/regs-clock.h>
> >> +
> >> +static struct sleep_save s5pv210_core_save[] = {
> >> + ? ? /* Clock source */
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC0),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC1),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC2),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC3),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC4),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC5),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC6),
> >> +
> >> + ? ? /* Clock source Mask */
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC_MASK0),
> >> + ? ? SAVE_ITEM(S5P_CLK_SRC_MASK1),
> >> +
> >> + ? ? /* Clock Divider */
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV0),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV1),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV2),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV3),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV4),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV5),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV6),
> >> + ? ? SAVE_ITEM(S5P_CLK_DIV7),
> >> +
> >> + ? ? /* Clock Main Gate */
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_MAIN0),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_MAIN1),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_MAIN2),
> >> +
> >> + ? ? /* Clock source Peri Gate */
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_PERI0),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_PERI1),
> >> +
> >> + ? ? /* Clock source SCLK Gate */
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_SCLK0),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_SCLK1),
> >> +
> >> + ? ? /* Clock IP Clock gate */
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP0),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP1),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP2),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP3),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_IP4),
> >> +
> >> + ? ? /* Clock Blcok and Bus gate */
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_BLOCK),
> >> + ? ? SAVE_ITEM(S5P_CLKGATE_BUS0),
> >> +
> >> + ? ? /* Clock ETC */
> >> + ? ? SAVE_ITEM(S5P_CLK_OUT),
> >> + ? ? SAVE_ITEM(S5P_MDNIE_SEL),
> >> +
> >> + ? ? /* PWM Register */
> >> + ? ? SAVE_ITEM(S3C2410_TCFG0),
> >> + ? ? SAVE_ITEM(S3C2410_TCFG1),
> >> + ? ? SAVE_ITEM(S3C64XX_TINT_CSTAT),
> >> + ? ? SAVE_ITEM(S3C2410_TCON),
> >> + ? ? SAVE_ITEM(S3C2410_TCNTB(0)),
> >> + ? ? SAVE_ITEM(S3C2410_TCMPB(0)),
> >> + ? ? SAVE_ITEM(S3C2410_TCNTO(0)),
> >> +
> >> + ? ? /* VIC 2 and 3*/
> >> + ? ? SAVE_ITEM(VA_VIC2 + VIC_INT_SELECT),
> >> + ? ? SAVE_ITEM(VA_VIC3 + VIC_INT_SELECT),
> >> + ? ? SAVE_ITEM(VA_VIC2 + VIC_INT_ENABLE),
> >> + ? ? SAVE_ITEM(VA_VIC3 + VIC_INT_ENABLE),
> >> + ? ? SAVE_ITEM(VA_VIC2 + VIC_INT_SOFT),
> >> + ? ? SAVE_ITEM(VA_VIC3 + VIC_INT_SOFT),
> >
> > doesn't the vic driver do this for you? if not, then would be better
> > to change the vic to fix this.
> 
> The VIC driver does only for VIC0 and VIC1; thus, moving VIC2/3 from
> pm.c to irq-pm.c should be fine.
> Probably, a few machines supposed to be supported by this irq-pm
> driver has only VIC0 and VIC1.
> However, it'd be better if irq-pm supports both machines with VIC0/1 and VIC0-3.

The _correct_ thing to do would be to have defined CONFIG_ARM_VIC_NR to
be bigger than 2, thus the core driver would have been correctly suspending
and resuming all the vics in the system.

Maybe we should change to using the initial memory allocator and getting
rid of the CONFIG_ARM_VIC_NR.

However, how on earth did no-one notice and not do anything about the
hughe KERN_ERR notice about there being two few VICs configured???

looking at arch/arm/common/vic.c:

   193          if (vic_id >= ARRAY_SIZE(vic_devices))
   194                  printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
   195          else {

it isn't as if it fails silently..


> >
> >> +};
> >> +
> >> +void s5pv210_cpu_suspend(void)
> >> +{
> >> + ? ? unsigned long tmp;
> >> +
> >> + ? ? /* issue the standby signal into the pm unit. Note, we
> >> + ? ? ?* issue a write-buffer drain just in case */
> >> +
> >> + ? ? tmp = 0;
> >> +
> >> + ? ? asm("b 1f\n\t"
> >> + ? ? ? ? ".align 5\n\t"
> >> + ? ? ? ? "1:\n\t"
> >> + ? ? ? ? "mcr p15, 0, %0, c7, c10, 5\n\t"
> >> + ? ? ? ? "mcr p15, 0, %0, c7, c10, 4\n\t"
> >> + ? ? ? ? ".word 0xe320f003" : : "r" (tmp));
> >
> > why .word? if there's a compiler problem then make a comment about
> > what instruction is being synthesised and why.
> 
> ".word 0xe320f003" may be replaced by "wfi". (wait-for-interrupt)
> 
> >
> >> + ? ? /* we should never get past here */
> >> + ? ? panic("sleep resumed to originator?");
> >> +}
> >> +
> >> +static void s5pv210_pm_prepare(void)
> >> +{
> >> + ? ? unsigned int tmp;
> >> +
> >> + ? ? /* ensure at least INFORM0 has the resume address */
> >> + ? ? __raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
> >> +
> >> + ? ? tmp = __raw_readl(S5P_SLEEP_CFG);
> >> + ? ? tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
> >> + ? ? __raw_writel(tmp, S5P_SLEEP_CFG);
> >> +
> >> + ? ? /* WFI for SLEEP mode configuration by SYSCON */
> >> + ? ? tmp = __raw_readl(S5P_PWR_CFG);
> >> + ? ? tmp &= S5P_CFG_WFI_CLEAN;
> >> + ? ? tmp |= S5P_CFG_WFI_SLEEP;
> >> + ? ? __raw_writel(tmp, S5P_PWR_CFG);
> >> +
> >> + ? ? /* SYSCON interrupt handling disable */
> >> + ? ? tmp = __raw_readl(S5P_OTHERS);
> >> + ? ? tmp |= S5P_OTHER_SYSC_INTOFF;
> >> + ? ? __raw_writel(tmp, S5P_OTHERS);
> >> +
> >> + ? ? __raw_writel(0xffffffff, (VA_VIC0 + VIC_INT_ENABLE_CLEAR));
> >> + ? ? __raw_writel(0xffffffff, (VA_VIC1 + VIC_INT_ENABLE_CLEAR));
> >> + ? ? __raw_writel(0xffffffff, (VA_VIC2 + VIC_INT_ENABLE_CLEAR));
> >> + ? ? __raw_writel(0xffffffff, (VA_VIC3 + VIC_INT_ENABLE_CLEAR));
> 
> It appears to be omitting VIC_INT_SOFT_CLEAR. I'm not sure whether
> this is also required as VIC_INT_ENABLE_CLEAR does; however, we've
> been doing __raw_writel(0xffffffff, (VA_VICx + VIC_INT_SOFT_CLEAR) as
> well.
> 
> Clearing pending external interrupt when entering a suspend may be
> added here. Sometimes, uncleared pending external interrupts may be
> problematic for a sleep; i.e., having waking-up interrupts pending
> while entering a sleep may be not too pleasant. "writel(0xff,
> S5P_WKUP_INT_PEND**_**);" will do the work. I don't sure whether this
> is really "required" for recent S5PV210/S5PC110; however, clearing
> pending interrupts improved the stability for the old release of
> S5PC110.
> 
> >> +
> >> + ? ? s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
> >> +}
> >> +
> >> +static int s5pv210_pm_add(struct sys_device *sysdev)
> >> +{
> >> + ? ? pm_cpu_prep = s5pv210_pm_prepare;
> >> + ? ? pm_cpu_sleep = s5pv210_cpu_suspend;
> >> +
> >> + ? ? return 0;
> >> +}
> >> +
> >> +static int s5pv210_pm_resume(struct sys_device *dev)
> >> +{
> >> + ? ? u32 tmp;
> >> +
> >> + ? ? tmp = __raw_readl(S5P_OTHERS);
> >> + ? ? tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | \
> >> + ? ? ? ? ? ? S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART);
> >> + ? ? __raw_writel(tmp , S5P_OTHERS);
> >> +
> >> + ? ? s3c_pm_do_restore_core(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
> >> +
> >> + ? ? return 0;
> >> +}
> 
> I don't know how may "printk"s exist after s3c_pm_enter is returned
> and before this resume function is called. However, printk's (and
> debug messages) between these two often generate broken characters on
> UART terminal. It may be better if S5P_OTHERS setting is done much
> earlier; e.g., at arch/arm/plat-samsung/pm.c:s3c_pm_enter.
> 
> However, this operation may be done at the boot-loader; in such a
> case, this doesn't matter at all.
> 
> >> +
> >> +static struct sysdev_driver s5pv210_pm_driver = {
> >> + ? ? .add ? ? ? ? ? ?= s5pv210_pm_add,
> >> + ? ? .resume ? ? ? ? = s5pv210_pm_resume,
> >> +};
> >> +
> >> +static __init int s5pv210_pm_drvinit(void)
> >> +{
> >> + ? ? return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver);
> >> +}
> >> +arch_initcall(s5pv210_pm_drvinit);
> >> diff --git a/arch/arm/mach-s5pv210/sleep.S b/arch/arm/mach-s5pv210/sleep.S
> >> new file mode 100644
> >> index 0000000..b7f8272
> >> --- /dev/null
> >> +++ b/arch/arm/mach-s5pv210/sleep.S
> >> @@ -0,0 +1,166 @@
> >> +/* linux/arch/arm/mach-s5pv210/sleep.S
> >> + *
> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> >> + * ? ? ? ? ? http://www.samsung.com
> >> + *
> >> + * S5PV210 power Manager (Suspend-To-RAM) support
> >> + *
> >> + * Based on S3C2410 sleep code by:
> >> + * ? Ben Dooks, (c) 2004 Simtec Electronics
> >> + *
> >> + * Based on PXA/SA1100 sleep code by:
> >> + * ? Nicolas Pitre, (c) 2002 Monta Vista Software Inc
> >> + * ? Cliff Brake, (c) 2001
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License as published by
> >> + * the Free Software Foundation; either version 2 of the License, or
> >> + * (at your option) any later version.
> >> + *
> >> + * This program is distributed in the hope that it will be useful,
> >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> >> + * GNU General Public License for more details.
> >> + *
> >> + * You should have received a copy of the GNU General Public License
> >> + * along with this program; if not, write to the Free Software
> >> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA ?02111-1307 ?USA
> >> +*/
> >> +
> >> +#include <linux/linkage.h>
> >> +#include <asm/assembler.h>
> >> +#include <asm/memory.h>
> >> +
> >> + ? ? .text
> >> +
> >> + ? ? /* s3c_cpu_save
> >> + ? ? ?*
> >> + ? ? ?* entry:
> >> + ? ? ?* ? ? ?r0 = save address (virtual addr of s3c_sleep_save_phys)
> >> + ? ? */
> >> +
> >> +ENTRY(s3c_cpu_save)
> >> +
> >> + ? ? stmfd ? sp!, { r3 - r12, lr }
> >> +
> >> + ? ? mrc ? ? p15, 0, r4, c13, c0, 0 ?@ FCSE/PID
> >> + ? ? mrc ? ? p15, 0, r5, c3, c0, 0 ? @ Domain ID
> >> + ? ? mrc ? ? p15, 0, r6, c2, c0, 0 ? @ Translation Table BASE0
> >> + ? ? mrc ? ? p15, 0, r7, c2, c0, 1 ? @ Translation Table BASE1
> >> + ? ? mrc ? ? p15, 0, r8, c2, c0, 2 ? @ Translation Table Control
> >> + ? ? mrc ? ? p15, 0, r9, c1, c0, 0 ? @ Control register
> >> + ? ? mrc ? ? p15, 0, r10, c1, c0, 1 ?@ Auxiliary control register
> >> + ? ? mrc ? ? p15, 0, r11, c1, c0, 2 ?@ Co-processor access controls
> >> + ? ? mrc ? ? p15, 0, r12, c10, c2, 0 @ Read PRRR
> >> + ? ? mrc ? ? p15, 0, r3, c10, c2, 1 ?@ READ NMRR
> >> +
> >> + ? ? stmia ? r0, { r3 - r13 }
> >> +
> >> + ? ? bl ? ? ?s3c_pm_cb_flushcache
> >> +
> >> + ? ? ldr ? ? r0, =pm_cpu_sleep
> >> + ? ? ldr ? ? r0, [ r0 ]
> >> + ? ? mov ? ? pc, r0
> >> +
> >> +resume_with_mmu:
> >> + ? ? /* delete added mmu table list */
> >
> > hmm, where is this being added?
> > also, a better description on what it is doing would be better.
> >
> >> + ? ? ldr ? ? r9 , =(PAGE_OFFSET - PHYS_OFFSET)
> >> + ? ? add ? ? r4, r4, r9
> >> + ? ? str ? ? r12, [r4]
> >> +
> >> + ? ? ldmfd ? sp!, { r3 - r12, pc }
> >> +
> >> + ? ? .ltorg
> >> +
> >> + ? ? .data
> >> +
> >> + ? ? .global s3c_sleep_save_phys
> >> +s3c_sleep_save_phys:
> >> + ? ? .word ? 0
> >> +
> >> + ? ? /* sleep magic, to allow the bootloader to check for an valid
> >> + ? ? ?* image to resume to. Must be the first word before the
> >> + ? ? ?* s3c_cpu_resume entry.
> >> + ? ? */
> >> +
> >> + ? ? .word ? 0x2bedf00d
> >> +
> >> + ? ? /* s3c_cpu_resume
> >> + ? ? ?*
> >> + ? ? ?* resume code entry for bootloader to call
> >> + ? ? ?*
> >> + ? ? ?* we must put this code here in the data segment as we have no
> >> + ? ? ?* other way of restoring the stack pointer after sleep, and we
> >> + ? ? ?* must not write to the code segment (code is read-only)
> >> + ? ? */
> >> +
> >> +ENTRY(s3c_cpu_resume)
> >> + ? ? mov ? ? r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
> >> + ? ? msr ? ? cpsr_c, r0
> >> +
> >> + ? ? mov ? ? r1, #0
> >> + ? ? mcr ? ? p15, 0, r1, c8, c7, 0 ? ? ? ? ? @@ invalidate TLBs
> >> + ? ? mcr ? ? p15, 0, r1, c7, c5, 0 ? ? ? ? ? @@ invalidate I Cache
> >> +
> >> + ? ? ldr ? ? r0, s3c_sleep_save_phys ? ? ? ? @ address of restore block
> >> + ? ? ldmia ? r0, { r3 - r13 }
> >> +
> >> + ? ? mcr ? ? p15, 0, r4, c13, c0, 0 ? ? ? ? ?@ FCSE/PID
> >> + ? ? mcr ? ? p15, 0, r5, c3, c0, 0 ? ? ? ? ? @ Domain ID
> >> +
> >> + ? ? mcr ? ? p15, 0, r8, c2, c0, 2 ? ? ? ? ? @ Translation Table Control
> >> + ? ? mcr ? ? p15, 0, r7, c2, c0, 1 ? ? ? ? ? @ Translation Table BASE1
> >> + ? ? mcr ? ? p15, 0, r6, c2, c0, 0 ? ? ? ? ? @ Translation Table BASE0
> >> +
> >> + ? ? mcr ? ? p15, 0, r10, c1, c0, 1 ? ? ? ? ?@ Auxiliary control register
> >> +
> >> + ? ? mov ? ? r0, #0
> >> + ? ? mcr ? ? p15, 0, r0, c8, c7, 0 ? ? ? ? ? @ Invalidate I & D TLB
> >> +
> >> + ? ? mov ? ? r0, #0 ? ? ? ? ? ? ? ? ? ? ? ? ?@ restore copro access
> >> + ? ? mcr ? ? p15, 0, r11, c1, c0, 2 ? ? ? ? ?@ Co-processor access
> >> + ? ? mcr ? ? p15, 0, r0, c7, c5, 4
> >> +
> >> + ? ? mcr ? ? p15, 0, r12, c10, c2, 0 ? ? ? ? @ write PRRR
> >> + ? ? mcr ? ? p15, 0, r3, c10, c2, 1 ? ? ? ? ?@ write NMRR
> >> +
> >> + ? ? /* Calculate first section address into r8
> >> + ? ? ?* In Cotex-A8 case, When MMU turn on, MMU is reseted.
> >
> > i'd fix this typo.
> >
> >> + ? ? ?* So, before call resume_with_mmu, backup originally data.
> >> + ? ? */
> >> +
> >> + ? ? mov ? ? r4, r6
> >> + ? ? mov ? ? r4, r4, LSR #14
> >> + ? ? mov ? ? r4, r4, LSL #14
> >> +
> >> + ? ? /* Load TLB Base address from INFORM0 */
> >
> > do you mean mmu page table?
> >
> >> + ? ? ldr ? ? r11, =0xe010f000
> >> + ? ? ldr ? ? r10, [r11, #0]
> >> + ? ? mov ? ? r10, r10, LSR #18
> >> + ? ? bic ? ? r10, r10, #0x3
> >> + ? ? orr ? ? r4, r4, r10
> >> +
> >> + ? ? /* calculate mmu list value into r9 */
> >> + ? ? mov ? ? r10, r10, LSL #18
> >> + ? ? ldr ? ? r5, =0x40e
> >> + ? ? orr ? ? r10, r10, r5
> >> +
> >> + ? ? /* back up originally data */
> >> +
> >> + ? ? ldr ? ? r12, [r4]
> >> +
> >> + ? ? /* Added list about mmu */
> >> + ? ? str ? ? r10, [r4]
> >
> >
> >
> >> + ? ? ldr ? ? r2, =resume_with_mmu
> >> + ? ? mcr ? ? p15, 0, r9, c1, c0, 0 ? ? ? ? ? @ turn on MMU, etc
> >> +
> >> + ? ? nop
> >> + ? ? nop
> >> + ? ? nop
> >> + ? ? nop
> >> + ? ? nop ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ second-to-last before mmu
> >> +
> >> + ? ? mov ? ? pc, r2 ? ? ? ? ? ? ? ? ? ? ? ? ?@ go back to virtual address
> >> +
> >> + ? ? .ltorg
> >> diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
> >> index 39c242b..d04ae49 100644
> >> --- a/arch/arm/plat-s5p/Makefile
> >> +++ b/arch/arm/plat-s5p/Makefile
> >> @@ -18,3 +18,5 @@ obj-y ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += clock.o
> >> ?obj-y ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?+= irq.o
> >> ?obj-$(CONFIG_S5P_EXT_INT) ? ?+= irq-eint.o
> >>
> >> +obj-$(CONFIG_PM) ? ? ? ? ? ? += pm.o
> >> +obj-$(CONFIG_PM) ? ? ? ? ? ? += irq-pm.o
> >> diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-s5p/include/plat/irqs.h
> >> index 3fb3a3a..9ffdd62 100644
> >> --- a/arch/arm/plat-s5p/include/plat/irqs.h
> >> +++ b/arch/arm/plat-s5p/include/plat/irqs.h
> >> @@ -94,4 +94,6 @@
> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ((irq) - S5P_EINT_BASE1) : \
> >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ((irq) + 16 - S5P_EINT_BASE2))
> >>
> >> +#define IRQ_EINT_BIT(x) ? ? ? ? ? ? ?EINT_OFFSET(x)
> >> +
> >> ?#endif /* __ASM_PLAT_S5P_IRQS_H */
> >> diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
> >> new file mode 100644
> >> index 0000000..03e83a3
> >> --- /dev/null
> >> +++ b/arch/arm/plat-s5p/irq-pm.c
> >> @@ -0,0 +1,108 @@
> >> +/* linux/arch/arm/plat-s5p/irq-pm.c
> >> + *
> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> >> + * ? ? ? ? ? http://www.samsung.com
> >> + *
> >> + * Based on arch/arm/plat-s3c24xx/irq-pm.c,
> >> + * Copyright (c) 2003,2004 Simtec Electronics
> >> + * ? Ben Dooks <ben at simtec.co.uk>
> >> + * ? http://armlinux.simtec.co.uk/
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License version 2 as
> >> + * published by the Free Software Foundation.
> >> +*/
> >> +
> >> +#include <linux/init.h>
> >> +#include <linux/module.h>
> >> +#include <linux/interrupt.h>
> >> +#include <linux/sysdev.h>
> >> +
> >> +#include <plat/cpu.h>
> >> +#include <plat/irqs.h>
> >> +#include <plat/pm.h>
> >> +#include <mach/map.h>
> >> +
> >> +#include <mach/regs-gpio.h>
> >> +#include <mach/regs-irq.h>
> >> +
> >> +/* state for IRQs over sleep */
> >> +
> >> +/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC, IRQ_RTC_ALARM,
> >> + * as wakeup sources
> >> + *
> >> + * set bit to 1 in allow bitfield to enable the wakeup settings on it
> >> +*/
> >> +
> >> +unsigned long s3c_irqwake_intallow ? = 0x00000006L;
> >> +unsigned long s3c_irqwake_eintallow ?= 0xffffffffL;
> >> +
> >> +int s3c_irq_wake(unsigned int irqno, unsigned int state)
> >> +{
> >> + ? ? unsigned long irqbit;
> >> +
> >> + ? ? switch (irqno) {
> >> + ? ? case IRQ_RTC_TIC:
> >> + ? ? case IRQ_RTC_ALARM:
> >> + ? ? ? ? ? ? irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM);
> >> + ? ? ? ? ? ? if (!state)
> >> + ? ? ? ? ? ? ? ? ? ? s3c_irqwake_intmask |= irqbit;
> >> + ? ? ? ? ? ? else
> >> + ? ? ? ? ? ? ? ? ? ? s3c_irqwake_intmask &= ~irqbit;
> >> + ? ? ? ? ? ? break;
> >> + ? ? default:
> >> + ? ? ? ? ? ? return -ENOENT;
> >> + ? ? }
> >> + ? ? return 0;
> >> +}
> >> +
> >> +/* this lot should be really saved by the IRQ code */
> >> +/* VICXADDRESSXX initilaization to be needed */
> >> +static struct sleep_save irq_save[] = {
> >> + ? ? SAVE_ITEM(VA_VIC0 + VIC_INT_SELECT),
> >> + ? ? SAVE_ITEM(VA_VIC1 + VIC_INT_SELECT),
> >> +
> >> + ? ? SAVE_ITEM(VA_VIC0 + VIC_INT_ENABLE),
> >> + ? ? SAVE_ITEM(VA_VIC1 + VIC_INT_ENABLE),
> >> +
> >> + ? ? SAVE_ITEM(VA_VIC0 + VIC_INT_SOFT),
> >> + ? ? SAVE_ITEM(VA_VIC1 + VIC_INT_SOFT),
> 
> S5PV210 has VIC2,3 as well. Maybe those can be moved from pm.c to here.
> 
> >> +};
> >> +
> >> +static struct sleep_save eint_save[] = {
> >> + ? ? SAVE_ITEM(S5P_EINT_CON(0)),
> >> + ? ? SAVE_ITEM(S5P_EINT_CON(1)),
> >> + ? ? SAVE_ITEM(S5P_EINT_CON(2)),
> >> + ? ? SAVE_ITEM(S5P_EINT_CON(3)),
> >> +
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(0)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(1)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(2)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(3)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(4)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(5)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(6)),
> >> + ? ? SAVE_ITEM(S5P_EINT_FLTCON(7)),
> >> +
> >> + ? ? SAVE_ITEM(S5P_EINT_MASK(0)),
> >> + ? ? SAVE_ITEM(S5P_EINT_MASK(1)),
> >> + ? ? SAVE_ITEM(S5P_EINT_MASK(2)),
> >> + ? ? SAVE_ITEM(S5P_EINT_MASK(3)),
> >> +};
> >> +
> >> +int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
> >> +{
> >> + ? ? s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
> >> + ? ? s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
> >> +
> >> + ? ? return 0;
> >> +}
> >> +
> >> +int s3c24xx_irq_resume(struct sys_device *dev)
> >> +{
> >> + ? ? s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
> >> + ? ? s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
> >> +
> >> + ? ? return 0;
> >> +}
> >> +
> >> diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-s5p/pm.c
> >> new file mode 100644
> >> index 0000000..d592b63
> >> --- /dev/null
> >> +++ b/arch/arm/plat-s5p/pm.c
> >> @@ -0,0 +1,52 @@
> >> +/* linux/arch/arm/plat-s5p/pm.c
> >> + *
> >> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> >> + * ? ? ? ? ? http://www.samsung.com
> >> + *
> >> + * S5P Power Manager (Suspend-To-RAM) support
> >> + *
> >> + * Based on arch/arm/plat-s3c24xx/pm.c
> >> + * Copyright (c) 2004,2006 Simtec Electronics
> >> + * ? Ben Dooks <ben at simtec.co.uk>
> >> + *
> >> + * This program is free software; you can redistribute it and/or modify
> >> + * it under the terms of the GNU General Public License version 2 as
> >> + * published by the Free Software Foundation.
> >> +*/
> >> +
> >> +#include <linux/suspend.h>
> >> +#include <plat/pm.h>
> >> +
> >> +#define PFX "s5p pm: "
> >> +
> >> +/* s3c_pm_check_resume_pin
> >> + *
> >> + * check to see if the pin is configured correctly for sleep mode, and
> >> + * make any necessary adjustments if it is not
> >> +*/
> >> +
> >> +static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> +/* s3c_pm_configure_extint
> >> + *
> >> + * configure all external interrupt pins
> >> +*/
> >> +
> >> +void s3c_pm_configure_extint(void)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> +void s3c_pm_restore_core(void)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> +void s3c_pm_save_core(void)
> >> +{
> >> + ? ? /* nothing here yet */
> >> +}
> >> +
> >> diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
> >> index 7df03f8..9652820 100644
> >> --- a/arch/arm/plat-samsung/pm-gpio.c
> >> +++ b/arch/arm/plat-samsung/pm-gpio.c
> >> @@ -192,7 +192,7 @@ struct s3c_gpio_pm s3c_gpio_pm_2bit = {
> >> ? ? ? .resume = s3c_gpio_pm_2bit_resume,
> >> ?};
> >>
> >> -#ifdef CONFIG_ARCH_S3C64XX
> >> +#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
> >> ?static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
> >> ?{
> >> ? ? ? chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
> >> @@ -302,7 +302,7 @@ struct s3c_gpio_pm s3c_gpio_pm_4bit = {
> >> ? ? ? .save ? = s3c_gpio_pm_4bit_save,
> >> ? ? ? .resume = s3c_gpio_pm_4bit_resume,
> >> ?};
> >> -#endif /* CONFIG_ARCH_S3C64XX */
> >> +#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
> >>
> >> ?/**
> >> ? * s3c_pm_save_gpio() - save gpio chip data for suspend
> >> --
> >> 1.6.2.5
> >>
> >
> >
> > --
> > --
> > Ben
> >
> > Q: ? ? ?What's a light-year?
> > A: ? ? ?One-third less calories than a regular year.
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >
> 
> 
> 
> -- 
> MyungJoo Ham (?????????), Ph.D.
> Mobile Software Platform Lab,
> Digital Media and Communications (DMC) Business
> Samsung Electronics
> cell: 82-10-6714-2858
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From eric.y.miao at gmail.com  Tue Jun  1 01:58:55 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 1 Jun 2010 13:58:55 +0800
Subject: [PATCH 1/3] Add battery support into Zipit Z2
In-Reply-To: <1275317512-4239-1-git-send-email-marek.vasut@gmail.com>
References: <1275317512-4239-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTinBW3-PX8wwzgQh9iVeruSvR_uieS-0OSzyIeUk@mail.gmail.com>

On Mon, May 31, 2010 at 10:51 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> This patch adds support for the AER915 battery chip into Zipit Z2
> platform file.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Applied to 'devel'.

> ---
> ?arch/arm/mach-pxa/z2.c | ? 42 +++++++++++++++++++++++++++++++++++++++---
> ?1 files changed, 39 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
> index f5d1ae3..194865e 100644
> --- a/arch/arm/mach-pxa/z2.c
> +++ b/arch/arm/mach-pxa/z2.c
> @@ -16,6 +16,7 @@
> ?#include <linux/mtd/mtd.h>
> ?#include <linux/mtd/partitions.h>
> ?#include <linux/pwm_backlight.h>
> +#include <linux/z2_battery.h>
> ?#include <linux/dma-mapping.h>
> ?#include <linux/spi/spi.h>
> ?#include <linux/spi/libertas_spi.h>
> @@ -458,6 +459,39 @@ static inline void z2_keys_init(void) {}
> ?#endif
>
> ?/******************************************************************************
> + * Battery
> + ******************************************************************************/
> +#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
> +static struct z2_battery_info batt_chip_info = {
> + ? ? ? .batt_I2C_bus ? = 0,
> + ? ? ? .batt_I2C_addr ?= 0x55,
> + ? ? ? .batt_I2C_reg ? = 2,
> + ? ? ? .charge_gpio ? ?= GPIO0_ZIPITZ2_AC_DETECT,
> + ? ? ? .min_voltage ? ?= 2400000,
> + ? ? ? .max_voltage ? ?= 3700000,
> + ? ? ? .batt_div ? ? ? = 69,
> + ? ? ? .batt_mult ? ? ?= 1000000,
> + ? ? ? .batt_tech ? ? ?= POWER_SUPPLY_TECHNOLOGY_LION,
> + ? ? ? .batt_name ? ? ?= "Z2",
> +};
> +
> +static struct i2c_board_info __initdata z2_i2c_board_info[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? I2C_BOARD_INFO("aer915", 0x55),
> + ? ? ? ? ? ? ? .platform_data ?= &batt_chip_info,
> + ? ? ? }
> +};
> +
> +static void __init z2_i2c_init(void)
> +{
> + ? ? ? pxa_set_i2c_info(NULL);
> + ? ? ? i2c_register_board_info(0, ARRAY_AND_SIZE(z2_i2c_board_info));
> +}
> +#else
> +static inline void z2_i2c_init(void) {}
> +#endif
> +
> +/******************************************************************************
> ?* SSP Devices - WiFi and LCD control
> ?******************************************************************************/
> ?#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
> @@ -585,12 +619,14 @@ static void __init z2_init(void)
> ?{
> ? ? ? ?pxa2xx_mfp_config(ARRAY_AND_SIZE(z2_pin_config));
>
> + ? ? ? pxa_set_ffuart_info(NULL);
> + ? ? ? pxa_set_btuart_info(NULL);
> + ? ? ? pxa_set_stuart_info(NULL);
> +
> ? ? ? ?z2_lcd_init();
> ? ? ? ?z2_mmc_init();
> ? ? ? ?z2_mkp_init();
> -
> - ? ? ? pxa_set_i2c_info(NULL);
> -
> + ? ? ? z2_i2c_init();
> ? ? ? ?z2_spi_init();
> ? ? ? ?z2_nor_init();
> ? ? ? ?z2_pwm_init();
> --
> 1.7.0
>
>


From eric.y.miao at gmail.com  Tue Jun  1 02:13:38 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 1 Jun 2010 14:13:38 +0800
Subject: [PATCH 3/3] pxa/z2: Register WM8750
In-Reply-To: <1275317512-4239-3-git-send-email-marek.vasut@gmail.com>
References: <1275317512-4239-1-git-send-email-marek.vasut@gmail.com> 
	<1275317512-4239-3-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTimoMar3sNtZyJ6jXbnxTcpUQ-JSdKJ28wUkql_n@mail.gmail.com>

On Mon, May 31, 2010 at 10:51 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> This patch registers the WM8750 codec on a proper place on the ZipitZ2
> machine after the WM8750 driver was converted to new API.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

This seems to be dependent on the previous z2 battery support patch.
Is this fixing the wm8750 registration bug, otherwise I'll queue this into
the -devel branch. Or you can help make this independent of the battery
support patch so I can merge this into -fix.

> ---
> ?arch/arm/mach-pxa/z2.c | ? ?5 ++++-
> ?1 files changed, 4 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
> index 194865e..4cba5b6 100644
> --- a/arch/arm/mach-pxa/z2.c
> +++ b/arch/arm/mach-pxa/z2.c
> @@ -479,7 +479,10 @@ static struct i2c_board_info __initdata z2_i2c_board_info[] = {
> ? ? ? ?{
> ? ? ? ? ? ? ? ?I2C_BOARD_INFO("aer915", 0x55),
> ? ? ? ? ? ? ? ?.platform_data ?= &batt_chip_info,
> - ? ? ? }
> + ? ? ? }, {
> + ? ? ? ? ? ? ? I2C_BOARD_INFO("wm8750", 0x1b),
> + ? ? ? },
> +
> ?};
>
> ?static void __init z2_i2c_init(void)
> --
> 1.7.0
>
>


From p.osciak at samsung.com  Tue Jun  1 02:49:07 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Tue, 01 Jun 2010 08:49:07 +0200
Subject: [PATCH 2/6] s3c-fb: Correct FRAMESEL1 bitfield defines for
	VIDINTCON0 register
In-Reply-To: <20100601041713.GC30276@trinity.fluff.org>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
	<1275296935-2693-3-git-send-email-p.osciak@samsung.com>
	<20100601041713.GC30276@trinity.fluff.org>
Message-ID: <000e01cb0156$886ed050$994c70f0$%osciak@samsung.com>

>Ben Dooks <ben at trinity.fluff.org> wrote:
>
>On Mon, May 31, 2010 at 11:08:51AM +0200, Pawel Osciak wrote:
>> FRAMESEL1 bitfield starts on 13th bit, not on 14th.
>
>is this true for all variants that have FRAMESEL1?

That's at least the case for all the chips I have docs for:
6400, 6410, S5PC100 and V210...

Best regards
--
Pawel Osciak
Linux Platform Group
Samsung Poland R&D Center




From davem at davemloft.net  Tue Jun  1 03:18:55 2010
From: davem at davemloft.net (David Miller)
Date: Tue, 01 Jun 2010 00:18:55 -0700 (PDT)
Subject: [PATCH] ixp4xx: Support the all multicast flag on the NPE devices.
In-Reply-To: <m3typoyr86.fsf@intrepid.localdomain>
References: <m3pr0c17ue.fsf@intrepid.localdomain>
	<20100531153419.GA17317@riccoc20.at.omicron.at>
	<m3typoyr86.fsf@intrepid.localdomain>
Message-ID: <20100601.001855.71558565.davem@davemloft.net>

From: Krzysztof Halasa <khc at pm.waw.pl>
Date: Mon, 31 May 2010 18:24:09 +0200

> Richard Cochran <richardcochran at gmail.com> writes:
> 
>> This patch adds support for the IFF_ALLMULTI flag. Previously only the
>> IFF_PROMISC flag was supported.
>>
>> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
 ...
> Acked-By: Krzysztof Halasa <khc at pm.waw.pl>

Applied.


From Colin.Tuckley at arm.com  Tue Jun  1 03:46:33 2010
From: Colin.Tuckley at arm.com (Colin Tuckley)
Date: Tue, 1 Jun 2010 08:46:33 +0100
Subject: 2.6.34 hangs during boot on PB11MPCore
In-Reply-To: <1275290414.2843.11.camel@e102109-lin.cambridge.arm.com>
References: <AANLkTin9n6HDdiTnQoQ9mrmuzSR8JhZVq7uPgU86yqgU@mail.gmail.com>
	<20100530073652.GX2695@buzzloop.caiaq.de>
	<AANLkTimUF5iiGnc6RnN5C3sy-R6DAqHZNf6ZEu2o3W9P@mail.gmail.com>
	<AANLkTikdvjg52v-3AKUBukGO2FCp3fENGoYgpZZ2xVtT@mail.gmail.com>
	<AANLkTilMtEpt5hRfF_hszpU_AxZm7H93bkhqUacGWZc9@mail.gmail.com>
	<1275259589.22752.14.camel@e102109-lin.cambridge.arm.com>
	<AANLkTim4e5Sdj9tronOiI-sIMVGaUQdfRIhKHzZ4XfKp@mail.gmail.com>
	<AANLkTim3YdK3QDXC-20otTBPqYF_XX9rGHRX50cycqk6@mail.gmail.com>
	<1275290414.2843.11.camel@e102109-lin.cambridge.arm.com>
Message-ID: <F01D8B85CFF58440B2A13965FBA90CA42DA38528B5@GEORGE.Emea.Arm.com>

> -----Original Message-----
> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-
> kernel-bounces at lists.infradead.org] On Behalf Of Catalin Marinas

> Regarding the SMSC 911x driver synchronisation - I've been asking SMSC
> for more than a year to look into this.

I'm still waiting for them to take up our offer of a PB11MPCore system for testing.

One thing Bjoern hasn't mentioned... is the board firmware up to date? I.e. has the fpga image been updated to the latest release (from the latest CD).

Colin

--
Colin Tuckley - ARM Ltd.
110 Fulbourn Rd
Cambridge, CB1 9NJ
Tel: +44 1223 400536

-- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium.  Thank you.


From raj.khem at gmail.com  Tue Jun  1 04:05:52 2010
From: raj.khem at gmail.com (Mikael Pettersson)
Date: Tue,  1 Jun 2010 01:05:52 -0700
Subject: [PATCH] Augment __naked__ function attribute with __noinline__ and
	__noclone__
Message-ID: <1275379552-23449-1-git-send-email-mikpe@it.uu.se>

The asm() bodies of naked functions often depend on standard calling
conventions, therefore they must be noinline and noclone.  GCC 4.[56]
currently fail to enforce this, see GCC PR44290.  The effect is that
most arch/arm/mm/copypage-*.c modules get miscompiled, resulting in
kernel crashes during bootup.

Part of the fix is to augment the __naked attribute to imply noinline
and noclone.  This patch implements that, and has been verified to fix
the failure to boot a gcc-4.5 compiled 2.6.34 kernel on a Thecus n2100
(XScale-based mach-iop32x).

Signed-off-by: Mikael Pettersson <mikpe at it.uu.se>
Signed-off-by: Khem Raj <raj.khem at gmail.com>
---
 include/linux/compiler-gcc.h  |   11 ++++++++++-
 include/linux/compiler-gcc4.h |    4 ++++
 2 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index 73dcf80..83bd87c 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -58,8 +58,12 @@
  * naked functions because then mcount is called without stack and frame pointer
  * being set up and there is no chance to restore the lr register to the value
  * before mcount was called.
+ *
+ * The asm() bodies of naked functions often depend on standard calling conventions,
+ * therefore they must be noinline and noclone.  GCC 4.[56] currently fail to enforce
+ * this, so we must do so ourselves.  See GCC PR44290.
  */
-#define __naked				__attribute__((naked)) notrace
+#define __naked				__attribute__((naked)) noinline __noclone notrace
 
 #define __noreturn			__attribute__((noreturn))
 
@@ -85,3 +89,8 @@
 #define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h)
 #define gcc_header(x) _gcc_header(x)
 #include gcc_header(__GNUC__)
+
+#if !defined(__noclone)
+#define __noclone	/* not needed */
+#endif
+
diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h
index 94dea3f..fcfa5b9 100644
--- a/include/linux/compiler-gcc4.h
+++ b/include/linux/compiler-gcc4.h
@@ -48,6 +48,10 @@
  * unreleased.  Really, we need to have autoconf for the kernel.
  */
 #define unreachable() __builtin_unreachable()
+
+/* Mark a function definition as prohibited from being cloned. */
+#define __noclone	__attribute__((__noclone__))
+
 #endif
 
 #endif
-- 
1.7.0.4



From raj.khem at gmail.com  Tue Jun  1 04:06:40 2010
From: raj.khem at gmail.com (Khem Raj)
Date: Tue,  1 Jun 2010 01:06:40 -0700
Subject: [PATCH] Add kto and kfrom to input operands list.
Message-ID: <1275379600-23498-1-git-send-email-raj.khem@gmail.com>

When functions incoming parameters are not in input operands list gcc 4.5 does not
load the parameters into registers before calling this function but the
inline assembly assumes valid addresses inside this function. This
breaks the code because r0 and r1 are invalid when execution enters
v4wb_copy_user_page ()

Also the constant needs to be used as third input operand so account for that
as well.

Tested on qemu arm.

Signed-off-by: Khem Raj <raj.khem at gmail.com>
---
 arch/arm/mm/copypage-feroceon.c |    4 ++--
 arch/arm/mm/copypage-v4wb.c     |    4 ++--
 arch/arm/mm/copypage-v4wt.c     |    4 ++--
 arch/arm/mm/copypage-xsc3.c     |    4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mm/copypage-feroceon.c b/arch/arm/mm/copypage-feroceon.c
index 5eb4fd9..ac163de 100644
--- a/arch/arm/mm/copypage-feroceon.c
+++ b/arch/arm/mm/copypage-feroceon.c
@@ -18,7 +18,7 @@ feroceon_copy_user_page(void *kto, const void *kfrom)
 {
 	asm("\
 	stmfd	sp!, {r4-r9, lr}		\n\
-	mov	ip, %0				\n\
+	mov	ip, %2				\n\
 1:	mov	lr, r1				\n\
 	ldmia	r1!, {r2 - r9}			\n\
 	pld	[lr, #32]			\n\
@@ -64,7 +64,7 @@ feroceon_copy_user_page(void *kto, const void *kfrom)
 	mcr	p15, 0, ip, c7, c10, 4		@ drain WB\n\
 	ldmfd	sp!, {r4-r9, pc}"
 	:
-	: "I" (PAGE_SIZE));
+	: "r" (kto), "r" (kfrom), "I" (PAGE_SIZE));
 }
 
 void feroceon_copy_user_highpage(struct page *to, struct page *from,
diff --git a/arch/arm/mm/copypage-v4wb.c b/arch/arm/mm/copypage-v4wb.c
index 7c2eb55..cb589cb 100644
--- a/arch/arm/mm/copypage-v4wb.c
+++ b/arch/arm/mm/copypage-v4wb.c
@@ -27,7 +27,7 @@ v4wb_copy_user_page(void *kto, const void *kfrom)
 {
 	asm("\
 	stmfd	sp!, {r4, lr}			@ 2\n\
-	mov	r2, %0				@ 1\n\
+	mov	r2, %2				@ 1\n\
 	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\
 1:	mcr	p15, 0, r0, c7, c6, 1		@ 1   invalidate D line\n\
 	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\
@@ -44,7 +44,7 @@ v4wb_copy_user_page(void *kto, const void *kfrom)
 	mcr	p15, 0, r1, c7, c10, 4		@ 1   drain WB\n\
 	ldmfd	 sp!, {r4, pc}			@ 3"
 	:
-	: "I" (PAGE_SIZE / 64));
+	: "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64));
 }
 
 void v4wb_copy_user_highpage(struct page *to, struct page *from,
diff --git a/arch/arm/mm/copypage-v4wt.c b/arch/arm/mm/copypage-v4wt.c
index 172e6a5..30c7d04 100644
--- a/arch/arm/mm/copypage-v4wt.c
+++ b/arch/arm/mm/copypage-v4wt.c
@@ -25,7 +25,7 @@ v4wt_copy_user_page(void *kto, const void *kfrom)
 {
 	asm("\
 	stmfd	sp!, {r4, lr}			@ 2\n\
-	mov	r2, %0				@ 1\n\
+	mov	r2, %2				@ 1\n\
 	ldmia	r1!, {r3, r4, ip, lr}		@ 4\n\
 1:	stmia	r0!, {r3, r4, ip, lr}		@ 4\n\
 	ldmia	r1!, {r3, r4, ip, lr}		@ 4+1\n\
@@ -40,7 +40,7 @@ v4wt_copy_user_page(void *kto, const void *kfrom)
 	mcr	p15, 0, r2, c7, c7, 0		@ flush ID cache\n\
 	ldmfd	sp!, {r4, pc}			@ 3"
 	:
-	: "I" (PAGE_SIZE / 64));
+	: "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64));
 }
 
 void v4wt_copy_user_highpage(struct page *to, struct page *from,
diff --git a/arch/arm/mm/copypage-xsc3.c b/arch/arm/mm/copypage-xsc3.c
index 747ad41..f9cde07 100644
--- a/arch/arm/mm/copypage-xsc3.c
+++ b/arch/arm/mm/copypage-xsc3.c
@@ -34,7 +34,7 @@ xsc3_mc_copy_user_page(void *kto, const void *kfrom)
 {
 	asm("\
 	stmfd	sp!, {r4, r5, lr}		\n\
-	mov	lr, %0				\n\
+	mov	lr, %2				\n\
 						\n\
 	pld	[r1, #0]			\n\
 	pld	[r1, #32]			\n\
@@ -67,7 +67,7 @@ xsc3_mc_copy_user_page(void *kto, const void *kfrom)
 						\n\
 	ldmfd	sp!, {r4, r5, pc}"
 	:
-	: "I" (PAGE_SIZE / 64 - 1));
+	: "r" (kto), "r" (kfrom), "I" (PAGE_SIZE / 64 - 1));
 }
 
 void xsc3_mc_copy_user_highpage(struct page *to, struct page *from,
-- 
1.7.0.4



From mkl at pengutronix.de  Tue Jun  1 04:51:16 2010
From: mkl at pengutronix.de (Marc Kleine-Budde)
Date: Tue, 01 Jun 2010 10:51:16 +0200
Subject: [PATCH V2] i2c-imx: do not allow interruptions when waiting for
	I2C to complete
In-Reply-To: <1274962561-17007-1-git-send-email-mkl@pengutronix.de>
References: <1274962561-17007-1-git-send-email-mkl@pengutronix.de>
Message-ID: <4C04CA04.6000207@pengutronix.de>

Marc Kleine-Budde wrote:
> The i2c_imx_trx_complete() function is using
> wait_event_interruptible_timeout() to wait for the I2C controller to
> signal that it has completed an I2C bus operation. If the process that
> causes the I2C operation receives a signal, the wait will be
> interrupted, returning an error. It is better to let the I2C operation
> finished before handling the signal (i.e. returning into userspace).
> 
> It is safe to use wait_event_timeout() instead, because the timeout
> will allow the process to exit if the I2C bus hangs. It's also better
> to allow the I2C operation to finish, because unacknowledged I2C
> operations can cause the I2C bus to hang.

Ping, can someone please comment the patch and/or push upstream.

Marc
> 
> Signed-off-by: Marc Kleine-Budde <mkl at pengutronix.de>
> Reviewed-by: Wolfram Sang <w.sang at pengutronix.de>
> ---
> 
> V2: Remove check for "result < 0" as commented by Wolfram Sang.
> 
>  drivers/i2c/busses/i2c-imx.c |    9 +++------
>  1 files changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c
> index d1ff940..58df809 100644
> --- a/drivers/i2c/busses/i2c-imx.c
> +++ b/drivers/i2c/busses/i2c-imx.c
> @@ -161,13 +161,10 @@ static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
>  {
>  	int result;
>  
> -	result = wait_event_interruptible_timeout(i2c_imx->queue,
> +	result = wait_event_timeout(i2c_imx->queue,
>  		i2c_imx->i2csr & I2SR_IIF, HZ / 10);
>  
> -	if (unlikely(result < 0)) {
> -		dev_dbg(&i2c_imx->adapter.dev, "<%s> result < 0\n", __func__);
> -		return result;
> -	} else if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
> +	if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
>  		dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
>  		return -ETIMEDOUT;
>  	}
> @@ -295,7 +292,7 @@ static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
>  		i2c_imx->i2csr = temp;
>  		temp &= ~I2SR_IIF;
>  		writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
> -		wake_up_interruptible(&i2c_imx->queue);
> +		wake_up(&i2c_imx->queue);
>  		return IRQ_HANDLED;
>  	}
>  


-- 
Pengutronix e.K.                  | Marc Kleine-Budde           |
Industrial Linux Solutions        | Phone: +49-231-2826-924     |
Vertretung West/Dortmund          | Fax:   +49-5121-206917-5555 |
Amtsgericht Hildesheim, HRA 2686  | http://www.pengutronix.de   |

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From marek.vasut at gmail.com  Tue Jun  1 05:42:01 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Tue, 1 Jun 2010 11:42:01 +0200
Subject: [PATCH 3/3] pxa/z2: Register WM8750
In-Reply-To: <AANLkTimoMar3sNtZyJ6jXbnxTcpUQ-JSdKJ28wUkql_n@mail.gmail.com>
References: <1275317512-4239-1-git-send-email-marek.vasut@gmail.com>
	<1275317512-4239-3-git-send-email-marek.vasut@gmail.com>
	<AANLkTimoMar3sNtZyJ6jXbnxTcpUQ-JSdKJ28wUkql_n@mail.gmail.com>
Message-ID: <201006011142.01214.marek.vasut@gmail.com>

Dne ?t 1. ?ervna 2010 08:13:38 Eric Miao napsal(a):
> On Mon, May 31, 2010 at 10:51 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > This patch registers the WM8750 codec on a proper place on the ZipitZ2
> > machine after the WM8750 driver was converted to new API.
> > 
> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> 
> This seems to be dependent on the previous z2 battery support patch.
> Is this fixing the wm8750 registration bug, otherwise I'll queue this into
> the -devel branch. Or you can help make this independent of the battery
> support patch so I can merge this into -fix.

Merge this into -devel please. This patch doesn't fix anything :)

Thanks!
> 
> > ---
> >  arch/arm/mach-pxa/z2.c |    5 ++++-
> >  1 files changed, 4 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
> > index 194865e..4cba5b6 100644
> > --- a/arch/arm/mach-pxa/z2.c
> > +++ b/arch/arm/mach-pxa/z2.c
> > @@ -479,7 +479,10 @@ static struct i2c_board_info __initdata
> > z2_i2c_board_info[] = { {
> >                I2C_BOARD_INFO("aer915", 0x55),
> >                .platform_data  = &batt_chip_info,
> > -       }
> > +       }, {
> > +               I2C_BOARD_INFO("wm8750", 0x1b),
> > +       },
> > +
> >  };
> > 
> >  static void __init z2_i2c_init(void)
> > --
> > 1.7.0


From linus.walleij at stericsson.com  Tue Jun  1 05:47:59 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 1 Jun 2010 11:47:59 +0200
Subject: [PATCH 1/2] ARM: PL011 TX/RX split of LCR for ST-Ericssons derivative
Message-ID: <1275385679-1526-1-git-send-email-linus.walleij@stericsson.com>

From: Marcin Mielczarczyk <marcin.mielczarczyk at tieto.com>

In the ST-Ericsson version of the PL011 the TX and RX have different
control registers.

Cc: Alessandro Rubini <rubini at unipv.it>
Signed-off-by: Marcin Mielczarczyk <marcin.mielczarczyk at tieto.com>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 drivers/serial/amba-pl011.c |   61 +++++++++++++++++++++++++++++++++++--------
 include/linux/amba/serial.h |    2 +
 2 files changed, 52 insertions(+), 11 deletions(-)

diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c
index eb4cb48..7f0c271 100644
--- a/drivers/serial/amba-pl011.c
+++ b/drivers/serial/amba-pl011.c
@@ -69,9 +69,11 @@
 struct uart_amba_port {
 	struct uart_port	port;
 	struct clk		*clk;
-	unsigned int		im;	/* interrupt mask */
+	unsigned int		im;		/* interrupt mask */
 	unsigned int		old_status;
-	unsigned int		ifls;	/* vendor-specific */
+	unsigned int		ifls;		/* vendor-specific */
+	unsigned int            lcrh_tx;        /* vendor-specific */
+	unsigned int            lcrh_rx;        /* vendor-specific */
 	bool			autorts;
 };
 
@@ -79,16 +81,22 @@ struct uart_amba_port {
 struct vendor_data {
 	unsigned int		ifls;
 	unsigned int		fifosize;
+	unsigned int            lcrh_tx;
+	unsigned int            lcrh_rx;
 };
 
 static struct vendor_data vendor_arm = {
 	.ifls			= UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
 	.fifosize		= 16,
+	.lcrh_tx                = UART011_LCRH,
+	.lcrh_rx                = UART011_LCRH,
 };
 
 static struct vendor_data vendor_st = {
 	.ifls			= UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
 	.fifosize		= 64,
+	.lcrh_tx                = ST_UART011_LCRH_TX,
+	.lcrh_rx                = ST_UART011_LCRH_RX,
 };
 
 static void pl011_stop_tx(struct uart_port *port)
@@ -327,12 +335,12 @@ static void pl011_break_ctl(struct uart_port *port, int break_state)
 	unsigned int lcr_h;
 
 	spin_lock_irqsave(&uap->port.lock, flags);
-	lcr_h = readw(uap->port.membase + UART011_LCRH);
+	lcr_h = readw(uap->port.membase + uap->lcrh_tx);
 	if (break_state == -1)
 		lcr_h |= UART01x_LCRH_BRK;
 	else
 		lcr_h &= ~UART01x_LCRH_BRK;
-	writew(lcr_h, uap->port.membase + UART011_LCRH);
+	writew(lcr_h, uap->port.membase + uap->lcrh_tx);
 	spin_unlock_irqrestore(&uap->port.lock, flags);
 }
 
@@ -393,7 +401,17 @@ static int pl011_startup(struct uart_port *port)
 	writew(cr, uap->port.membase + UART011_CR);
 	writew(0, uap->port.membase + UART011_FBRD);
 	writew(1, uap->port.membase + UART011_IBRD);
-	writew(0, uap->port.membase + UART011_LCRH);
+	writew(0, uap->port.membase + uap->lcrh_rx);
+	if (uap->lcrh_tx != uap->lcrh_rx) {
+                int i;
+                /*
+                 * Wait 10 PCLKs before writing LCRH_TX register,
+                 * to get this delay write read only register 10 times
+                 */
+                for (i = 0; i < 10; ++i)
+                        writew(0xff, uap->port.membase + UART011_MIS);
+                writew(0, uap->port.membase + uap->lcrh_tx);
+	}
 	writew(0, uap->port.membase + UART01x_DR);
 	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
 		barrier();
@@ -422,10 +440,19 @@ static int pl011_startup(struct uart_port *port)
 	return retval;
 }
 
+static void pl011_shutdown_channel(struct uart_amba_port *uap,
+					unsigned int lcrh)
+{
+      unsigned long val;
+
+      val = readw(uap->port.membase + lcrh);
+      val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
+      writew(val, uap->port.membase + lcrh);
+}
+
 static void pl011_shutdown(struct uart_port *port)
 {
 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
-	unsigned long val;
 
 	/*
 	 * disable all interrupts
@@ -450,9 +477,9 @@ static void pl011_shutdown(struct uart_port *port)
 	/*
 	 * disable break condition and fifos
 	 */
-	val = readw(uap->port.membase + UART011_LCRH);
-	val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
-	writew(val, uap->port.membase + UART011_LCRH);
+	pl011_shutdown_channel(uap, uap->lcrh_rx);
+	if (uap->lcrh_rx != uap->lcrh_tx)
+		pl011_shutdown_channel(uap, uap->lcrh_tx);
 
 	/*
 	 * Shut down the clock producer
@@ -561,7 +588,17 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
 	 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
 	 * ----------^----------^----------^----------^-----
 	 */
-	writew(lcr_h, port->membase + UART011_LCRH);
+	writew(lcr_h, port->membase + uap->lcrh_rx);
+	if (uap->lcrh_rx != uap->lcrh_tx) {
+                int i;
+                /*
+                 * Wait 10 PCLKs before writing LCRH_TX register,
+                 * to get this delay write read only register 10 times
+                 */
+                for (i = 0; i < 10; ++i)
+                        writew(0xff, uap->port.membase + UART011_MIS);
+		writew(lcr_h, port->membase + uap->lcrh_tx);
+	}
 	writew(old_cr, port->membase + UART011_CR);
 
 	spin_unlock_irqrestore(&port->lock, flags);
@@ -688,7 +725,7 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud,
 	if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
 		unsigned int lcr_h, ibrd, fbrd;
 
-		lcr_h = readw(uap->port.membase + UART011_LCRH);
+		lcr_h = readw(uap->port.membase + uap->lcrh_tx);
 
 		*parity = 'n';
 		if (lcr_h & UART01x_LCRH_PEN) {
@@ -800,6 +837,8 @@ static int pl011_probe(struct amba_device *dev, struct amba_id *id)
 	}
 
 	uap->ifls = vendor->ifls;
+	uap->lcrh_rx = vendor->lcrh_rx;
+	uap->lcrh_tx = vendor->lcrh_tx;
 	uap->port.dev = &dev->dev;
 	uap->port.mapbase = dev->res.start;
 	uap->port.membase = base;
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h
index 5a5a7fd..cf3cb61 100644
--- a/include/linux/amba/serial.h
+++ b/include/linux/amba/serial.h
@@ -38,10 +38,12 @@
 #define UART01x_FR		0x18	/* Flag register (Read only). */
 #define UART010_IIR		0x1C	/* Interrupt indentification register (Read). */
 #define UART010_ICR		0x1C	/* Interrupt clear register (Write). */
+#define ST_UART011_LCRH_RX      0x1C    /* Rx line control register. */
 #define UART01x_ILPR		0x20	/* IrDA low power counter register. */
 #define UART011_IBRD		0x24	/* Integer baud rate divisor register. */
 #define UART011_FBRD		0x28	/* Fractional baud rate divisor register. */
 #define UART011_LCRH		0x2c	/* Line control register. */
+#define ST_UART011_LCRH_TX      0x2c    /* Tx Line control register. */
 #define UART011_CR		0x30	/* Control register. */
 #define UART011_IFLS		0x34	/* Interrupt fifo level select. */
 #define UART011_IMSC		0x38	/* Interrupt mask. */
-- 
1.6.3.3



From linus.walleij at stericsson.com  Tue Jun  1 05:48:18 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 1 Jun 2010 11:48:18 +0200
Subject: [PATCH 2/2] ARM: PL011 baudrate extension for ST-Ericssons derivative
Message-ID: <1275385698-1599-1-git-send-email-linus.walleij@stericsson.com>

From: Marcin Mielczarczyk <marcin.mielczarczyk at tieto.com>

Implementation of the ST-Ericsson baudrate extension in the PL011
block. In this modified variant it is possible to change the
sampling factor from 16 to 8, and thanks to this we can get higher
baudrates while still using the same peripheral clock.

Cc: Alessandro Rubini <rubini at unipv.it>
Signed-off-by: Marcin Mielczarczyk <marcin.mielczarczyk at tieto.com>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 drivers/serial/amba-pl011.c |   27 +++++++++++++++++++++++++--
 include/linux/amba/serial.h |    1 +
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c
index 7f0c271..ed4ab21 100644
--- a/drivers/serial/amba-pl011.c
+++ b/drivers/serial/amba-pl011.c
@@ -74,6 +74,7 @@ struct uart_amba_port {
 	unsigned int		ifls;		/* vendor-specific */
 	unsigned int            lcrh_tx;        /* vendor-specific */
 	unsigned int            lcrh_rx;        /* vendor-specific */
+	bool		        oversampling;   /* vendor-specific */
 	bool			autorts;
 };
 
@@ -83,6 +84,7 @@ struct vendor_data {
 	unsigned int		fifosize;
 	unsigned int            lcrh_tx;
 	unsigned int            lcrh_rx;
+	bool		        oversampling;
 };
 
 static struct vendor_data vendor_arm = {
@@ -90,6 +92,7 @@ static struct vendor_data vendor_arm = {
 	.fifosize		= 16,
 	.lcrh_tx                = UART011_LCRH,
 	.lcrh_rx                = UART011_LCRH,
+        .oversampling	        = false,
 };
 
 static struct vendor_data vendor_st = {
@@ -97,6 +100,7 @@ static struct vendor_data vendor_st = {
 	.fifosize		= 64,
 	.lcrh_tx                = ST_UART011_LCRH_TX,
 	.lcrh_rx                = ST_UART011_LCRH_RX,
+        .oversampling	        = true,
 };
 
 static void pl011_stop_tx(struct uart_port *port)
@@ -499,8 +503,13 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
 	/*
 	 * Ask the core to calculate the divisor for us.
 	 */
-	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
-	quot = port->uartclk * 4 / baud;
+        baud = uart_get_baud_rate(port, termios, old, 0,
+                                  port->uartclk/(uap->oversampling?8:16));
+
+        if (baud > port->uartclk/16)
+                quot = port->uartclk * 8 / baud;
+        else
+                quot = port->uartclk * 4 / baud;
 
 	switch (termios->c_cflag & CSIZE) {
 	case CS5:
@@ -579,6 +588,13 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
 		uap->autorts = false;
 	}
 
+        if (uap->oversampling) {
+                if (baud > port->uartclk/16)
+                        old_cr |= ST_UART011_CR_OVSFACT;
+                else
+                        old_cr &= ~ST_UART011_CR_OVSFACT;
+        }
+
 	/* Set baud rate */
 	writew(quot & 0x3f, port->membase + UART011_FBRD);
 	writew(quot >> 6, port->membase + UART011_IBRD);
@@ -744,6 +760,12 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud,
 		fbrd = readw(uap->port.membase + UART011_FBRD);
 
 		*baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
+
+		if (uap->oversampling) {
+			if (readw(uap->port.membase + UART011_CR)
+				  & ST_UART011_CR_OVSFACT)
+				*baud *= 2;
+		}
 	}
 }
 
@@ -839,6 +861,7 @@ static int pl011_probe(struct amba_device *dev, struct amba_id *id)
 	uap->ifls = vendor->ifls;
 	uap->lcrh_rx = vendor->lcrh_rx;
 	uap->lcrh_tx = vendor->lcrh_tx;
+        uap->oversampling = vendor->oversampling;
 	uap->port.dev = &dev->dev;
 	uap->port.mapbase = dev->res.start;
 	uap->port.membase = base;
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h
index cf3cb61..a87c6a5 100644
--- a/include/linux/amba/serial.h
+++ b/include/linux/amba/serial.h
@@ -86,6 +86,7 @@
 #define UART010_CR_TIE 		0x0020
 #define UART010_CR_RIE 		0x0010
 #define UART010_CR_MSIE		0x0008
+#define ST_UART011_CR_OVSFACT	0x0008	/* Oversampling factor */
 #define UART01x_CR_IIRLP	0x0004	/* SIR low power mode */
 #define UART01x_CR_SIREN	0x0002	/* SIR enable */
 #define UART01x_CR_UARTEN	0x0001	/* UART enable */
-- 
1.6.3.3



From ben-linux at fluff.org  Tue Jun  1 06:36:52 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Tue,  1 Jun 2010 11:36:52 +0100
Subject: VIC dynamic PM
Message-ID: <1275388613-2496-1-git-send-email-ben-linux@fluff.org>

Quick patch that works on s3c6410 to change the vic to use kzalloc()
to allocate devices. I think that other architectures should be able
to use this too, but could other people please check about this?

If it is good for all, then comments on getting it merged for 2.6.36?



From ben-linux at fluff.org  Tue Jun  1 06:36:53 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Tue,  1 Jun 2010 11:36:53 +0100
Subject: [PATCH] ARM: VIC: Allocate VIC PM device from slab
In-Reply-To: <1275388613-2496-1-git-send-email-ben-linux@fluff.org>
References: <1275388613-2496-1-git-send-email-ben-linux@fluff.org>
Message-ID: <1275388613-2496-2-git-send-email-ben-linux@fluff.org>

The original assertion about the inability to allocate the VIC device is
wrong, and that we have the ability to allocate memory when registering
the VIC (tested on s3c6400_defconfig with SMDK6410).

Change to allocating the device at init time, putting it on a list
instead of having a static array of vics.

Note, since this is just for the PM, it does not affect the exisiting
VIC operations.

Signed-off-by: Ben Dooks <ben-linux at fluff.org>
---
 arch/arm/common/vic.c |   35 ++++++++++++++++-------------------
 1 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index ba65f6e..b1f1a9e 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -21,6 +21,7 @@
 
 #include <linux/init.h>
 #include <linux/list.h>
+#include <linux/slab.h>
 #include <linux/io.h>
 #include <linux/sysdev.h>
 #include <linux/device.h>
@@ -44,6 +45,7 @@
  */
 struct vic_device {
 	struct sys_device sysdev;
+	struct list_head list;
 
 	void __iomem	*base;
 	int		irq;
@@ -55,10 +57,7 @@ struct vic_device {
 	u32		protect;
 };
 
-/* we cannot allocate memory when VICs are initially registered */
-static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
-
-static int vic_id;
+static LIST_HEAD(vic_list);
 
 static inline struct vic_device *to_vic(struct sys_device *sys)
 {
@@ -147,11 +146,11 @@ struct sysdev_class vic_class = {
 */
 static int __init vic_pm_init(void)
 {
-	struct vic_device *dev = vic_devices;
+	struct vic_device *dev;
 	int err;
-	int id;
+	int id = 0;
 
-	if (vic_id == 0)
+	if (list_empty(&vic_list))
 		return 0;
 
 	err = sysdev_class_register(&vic_class);
@@ -160,8 +159,8 @@ static int __init vic_pm_init(void)
 		return err;
 	}
 
-	for (id = 0; id < vic_id; id++, dev++) {
-		dev->sysdev.id = id;
+	list_for_each_entry(dev, &vic_list, list) {
+		dev->sysdev.id = id++;
 		dev->sysdev.cls = &vic_class;
 
 		err = sysdev_register(&dev->sysdev);
@@ -190,15 +189,14 @@ static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 res
 {
 	struct vic_device *v;
 
-	if (vic_id >= ARRAY_SIZE(vic_devices))
-		printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
-	else {
-		v = &vic_devices[vic_id];
+	v = kzalloc(sizeof(struct vic_device), GFP_KERNEL);
+	if (v) {
+		list_add_tail(&v->list, &vic_list);
 		v->base = base;
-		v->resume_sources = resume_sources;
 		v->irq = irq;
-		vic_id++;
-	}
+		v->resume_sources = resume_sources;
+	} else
+		printk(KERN_ERR "%s: cannot add vic at %p\n", __func__, base);
 }
 #else
 static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
@@ -230,11 +228,10 @@ static void vic_unmask_irq(unsigned int irq)
 #if defined(CONFIG_PM)
 static struct vic_device *vic_from_irq(unsigned int irq)
 {
-        struct vic_device *v = vic_devices;
 	unsigned int base_irq = irq & ~31;
-	int id;
+	struct vic_device *v;
 
-	for (id = 0; id < vic_id; id++, v++) {
+	list_for_each_entry(v, &vic_list, list) {
 		if (v->irq == base_irq)
 			return v;
 	}
-- 
1.6.3.3



From mikpe at it.uu.se  Tue Jun  1 07:23:39 2010
From: mikpe at it.uu.se (Mikael Pettersson)
Date: Tue, 1 Jun 2010 13:23:39 +0200
Subject: [PATCH 2/2] ARM: move IOP to use common mult/shift calculation
	code
In-Reply-To: <1275068048-17778-1-git-send-email-linus.walleij@stericsson.com>
References: <1275068048-17778-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <19460.60859.675622.130280@pilspetsen.it.uu.se>

Linus Walleij writes:
 > Since the infrastructure for determining shift/mult values from a
 > clock rate and a minimum programmable rate is now in the kernel,
 > lets remove this custom code.
 > 
 > Cc: Mikael Pettersson <mikpe at it.uu.se>
 > Cc: Deepak Saxena <dsaxena at plexity.net>
 > Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
 > ---
 > Mikael: I cannot test this change, but I have compiled it against
 > iop33x_defconfig. You'd have to test it and Acked-by: it before
 > I do anything else with it. Try to think about what a minimum range
 > would be for the generic IOP platform...
 > ---
 >  arch/arm/plat-iop/time.c |   53 +++++++--------------------------------------
 >  1 files changed, 9 insertions(+), 44 deletions(-)

This patch is equivalent to the one I sent on Dec 29
"[PATCH] iop: use generic clock mult/shift compute functions",
which RMK acked and Dan Williams then wrote he would handle via
xscaleiop.git.  Then it ended up in a black hole somewhere.  I was
going to re-send it if it wasn't in .35-rc1, but you beat me to it.

I've been using this since mid-December, so:
Acked-by: Mikael Pettersson <mikpe at it.uu.se>

The value of IOP_MIN_RANGE is a compromise between possibly longer
idle periods and timekeeping accuracy.  The current value of 4s is
known to work and give the same mult/shift values as before the
clocksource/clockevents conversion.  As I can't get even close to 4s
idle intervals, I see little point changing this value right now.

(Plus it seems kernel/time/clocksource.c wants a 5s upper bound on
this anyway.)

/Mikael

 > 
 > diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
 > index 6c8a02a..85d3e55 100644
 > --- a/arch/arm/plat-iop/time.c
 > +++ b/arch/arm/plat-iop/time.c
 > @@ -29,6 +29,11 @@
 >  #include <mach/time.h>
 >  
 >  /*
 > + * Minimum clocksource/clockevent timer range in seconds
 > + */
 > +#define IOP_MIN_RANGE 4
 > +
 > +/*
 >   * IOP clocksource (free-running timer 1).
 >   */
 >  static cycle_t iop_clocksource_read(struct clocksource *unused)
 > @@ -44,27 +49,6 @@ static struct clocksource iop_clocksource = {
 >  	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
 >  };
 >  
 > -static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz)
 > -{
 > -	u64 temp;
 > -	u32 shift;
 > -
 > -	/* Find shift and mult values for hz. */
 > -	shift = 32;
 > -	do {
 > -		temp = (u64) NSEC_PER_SEC << shift;
 > -		do_div(temp, hz);
 > -		if ((temp >> 32) == 0)
 > -			break;
 > -	} while (--shift != 0);
 > -
 > -	cs->shift = shift;
 > -	cs->mult = (u32) temp;
 > -
 > -	printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n",
 > -	       cs->name, cs->shift, cs->mult);
 > -}
 > -
 >  /*
 >   * IOP sched_clock() implementation via its clocksource.
 >   */
 > @@ -130,27 +114,6 @@ static struct clock_event_device iop_clockevent = {
 >  	.set_mode	= iop_set_mode,
 >  };
 >  
 > -static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz)
 > -{
 > -	u64 temp;
 > -	u32 shift;
 > -
 > -	/* Find shift and mult values for hz. */
 > -	shift = 32;
 > -	do {
 > -		temp = (u64) hz << shift;
 > -		do_div(temp, NSEC_PER_SEC);
 > -		if ((temp >> 32) == 0)
 > -			break;
 > -	} while (--shift != 0);
 > -
 > -	ce->shift = shift;
 > -	ce->mult = (u32) temp;
 > -
 > -	printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n",
 > -	       ce->name, ce->shift, ce->mult);
 > -}
 > -
 >  static irqreturn_t
 >  iop_timer_interrupt(int irq, void *dev_id)
 >  {
 > @@ -190,7 +153,8 @@ void __init iop_init_time(unsigned long tick_rate)
 >  	 */
 >  	write_tmr0(timer_ctl & ~IOP_TMR_EN);
 >  	setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
 > -	iop_clockevent_set_hz(&iop_clockevent, tick_rate);
 > +	clockevents_calc_mult_shift(&iop_clockevent,
 > +				    tick_rate, IOP_MIN_RANGE);
 >  	iop_clockevent.max_delta_ns =
 >  		clockevent_delta2ns(0xfffffffe, &iop_clockevent);
 >  	iop_clockevent.min_delta_ns =
 > @@ -207,6 +171,7 @@ void __init iop_init_time(unsigned long tick_rate)
 >  	write_trr1(0xffffffff);
 >  	write_tcr1(0xffffffff);
 >  	write_tmr1(timer_ctl);
 > -	iop_clocksource_set_hz(&iop_clocksource, tick_rate);
 > +	clocksource_calc_mult_shift(&iop_clocksource, tick_rate,
 > +				    IOP_MIN_RANGE);
 >  	clocksource_register(&iop_clocksource);
 >  }
 > -- 
 > 1.6.3.3
 > 


From broonie at opensource.wolfsonmicro.com  Tue Jun  1 08:53:21 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 1 Jun 2010 13:53:21 +0100
Subject: [PATCH v2] ARM: S5PV210: Add Power Management Support
In-Reply-To: <20100601041633.GB30276@trinity.fluff.org>
References: <1275356164-7896-1-git-send-email-kgene.kim@samsung.com>
	<20100601020329.GT4720@trinity.fluff.org>
	<AANLkTinNCTUtXDeRTOBi05Yv7FoatY2ruWmnNtTSmg36@mail.gmail.com>
	<20100601041633.GB30276@trinity.fluff.org>
Message-ID: <20100601125320.GA10031@sirena.org.uk>

On Tue, Jun 01, 2010 at 05:16:33AM +0100, Ben Dooks wrote:
> On Tue, Jun 01, 2010 at 12:23:39PM +0900, Kyungmin Park wrote:

> > It's common function. Please add it to platform init instead of each board init.

> I know Mark Brown would rather this be the case too, but the original intent
> was that each board would declare itself to be capable of PM by calling this
> function to ensure that any boards which had not been validated or where
> simply incapable of suspend/resume did not end up with this enabled.

This does result in rather confusing behaviour, in that the attempts to
suspend end up getting silently ignored which isn't what you expect.
Other ARM platforms deal with this by erroring out of the suspend if
they can tell that it's not going to work and otherwise just trusting
the system integrator to know what they're doing when they turn on
suspend in Kconfig.

It would be more friendly to at least put in a default implementation
which prints an error telling the user what they need to do to actually
get suspend working.


From yegor_sub1 at visionsystems.de  Tue Jun  1 09:39:35 2010
From: yegor_sub1 at visionsystems.de (Yegor Yefremov)
Date: Tue, 01 Jun 2010 15:39:35 +0200
Subject: AC97 audio broken on SAM9263EK?
In-Reply-To: <4B97C086.2080404@atmel.com>
References: <4B85789D.6000704@billgatliff.com>
	<4B864C66.6060209@atmel.com>	<4B867108.2050806@billgatliff.com>
	<4B86AA29.8010806@atmel.com>	<4B89E1BB.6090504@billgatliff.com>
	<4B8B9849.5040203@atmel.com> <4B96571A.3040403@visionsystems.de>
	<4B96668E.6090805@atmel.com> <4B975C9A.3020106@visionsystems.de>
	<4B97602C.6070608@atmel.com> <4B97BD8C.3030502@visionsystems.de>
	<4B97C086.2080404@atmel.com>
Message-ID: <4C050D97.4000404@visionsystems.de>

Hi,

>> When do you think the driver could hit the mainline kernel? Till
>> 2.6.35 open window?
> 
> It has been acked, but I don't know when it will be in the mainline kernel.

have just tested 2.6.35-rc1 with mainline ac97 driver and found this issue. During playback I see following output on the console:

...
atmel_ac97c atmel_ac97c.0: channel A event
atmel_ac97c atmel_ac97c.0: channel A event
atmel_ac97c atmel_ac97c.0: channel A event
...

If I see it right these, lines come from sound/atmel/ac97c.c->atmel_ac97c_interrupt():

dev_info(&chip->pdev->dev, "channel A event%s%s%s%s%s%s\n",
                                casr & AC97C_CSR_OVRUN   ? " OVRUN"   : "",
                                casr & AC97C_CSR_RXRDY   ? " RXRDY"   : "",
                                casr & AC97C_CSR_UNRUN   ? " UNRUN"   : "",
                                casr & AC97C_CSR_TXEMPTY ? " TXEMPTY" : "",
                                casr & AC97C_CSR_TXRDY   ? " TXRDY"   : "",
                                !casr                    ? " NONE"    : "");

 

It is necessary to output this message in normal mode or is it a debug message?

Regards,
Yegor


From saeed at marvell.com  Tue Jun  1 11:09:26 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Tue,  1 Jun 2010 18:09:26 +0300
Subject: [PATCH 1/3] [ARM] Kirkwood: add support for rev A1 of the 88f6192 and
	88f6180 chips.
Message-ID: <1275404968-12258-1-git-send-email-saeed@marvell.com>


Signed-off-by: Saeed Bishara <saeed at marvell.com>
---
 arch/arm/mach-kirkwood/common.c                |    4 ++++
 arch/arm/mach-kirkwood/include/mach/kirkwood.h |    2 ++
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 6072eaa..c780c4a 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -891,11 +891,15 @@ static char * __init kirkwood_id(void)
 			return "MV88F6192-Z0";
 		else if (rev == MV88F6192_REV_A0)
 			return "MV88F6192-A0";
+		else if (rev == MV88F6192_REV_A1)
+			return "MV88F6192-A1";
 		else
 			return "MV88F6192-Rev-Unsupported";
 	} else if (dev == MV88F6180_DEV_ID) {
 		if (rev == MV88F6180_REV_A0)
 			return "MV88F6180-Rev-A0";
+		else if (rev == MV88F6180_REV_A1)
+			return "MV88F6180-Rev-A1";
 		else
 			return "MV88F6180-Rev-Unsupported";
 	} else {
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a15cf0e..d61b9aa 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -107,8 +107,10 @@
 #define MV88F6192_DEV_ID	0x6192
 #define MV88F6192_REV_Z0	0
 #define MV88F6192_REV_A0	2
+#define MV88F6192_REV_A1	3
 
 #define MV88F6180_DEV_ID	0x6180
 #define MV88F6180_REV_A0	2
+#define MV88F6180_REV_A1	3
 
 #endif
-- 
1.6.0.4



From saeed at marvell.com  Tue Jun  1 11:09:27 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Tue,  1 Jun 2010 18:09:27 +0300
Subject: [PATCH 2/3] [ARM] Kirkwood: Add support for 88f6282
In-Reply-To: <1275404968-12258-1-git-send-email-saeed@marvell.com>
References: <1275404968-12258-1-git-send-email-saeed@marvell.com>
Message-ID: <1275404968-12258-2-git-send-email-saeed@marvell.com>

The 6282 SoC is compatible to 6280 and features faster CPU, DDR3, additional
PCIe interface, and LCD controller. More infromation can be found here:
http://www.marvell.com/products/processors/embedded/armada_300/armada_310.pdf

Signed-off-by: Saeed Bishara <saeed at marvell.com>
---
 arch/arm/mach-kirkwood/common.c                |   13 ++++++++++---
 arch/arm/mach-kirkwood/include/mach/kirkwood.h |    2 ++
 arch/arm/mach-kirkwood/mpp.c                   |    3 ++-
 3 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index c780c4a..4ccfdf9 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -402,7 +402,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
 	u32 dev, rev;
 
 	kirkwood_pcie_id(&dev, &rev);
-	if (rev == 0)  /* catch all Kirkwood Z0's */
+	if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
 		mvsdio_data->clock = 100000000;
 	else
 		mvsdio_data->clock = 200000000;
@@ -847,8 +847,10 @@ int __init kirkwood_find_tclk(void)
 	u32 dev, rev;
 
 	kirkwood_pcie_id(&dev, &rev);
-	if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
-					rev == MV88F6281_REV_A1))
+
+	if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
+					rev == MV88F6281_REV_A1)) ||
+	    (dev == MV88F6282_DEV_ID))
 		return 200000000;
 
 	return 166666667;
@@ -902,6 +904,11 @@ static char * __init kirkwood_id(void)
 			return "MV88F6180-Rev-A1";
 		else
 			return "MV88F6180-Rev-Unsupported";
+	} else if (dev == MV88F6282_DEV_ID) {
+		if (rev == MV88F6282_REV_A0)
+			return "MV88F6282-Rev-A0";
+		else
+			return "MV88F6282-Rev-Unsupported";
 	} else {
 		return "Device-Unknown";
 	}
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index d61b9aa..dd7eddb 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -113,4 +113,6 @@
 #define MV88F6180_REV_A0	2
 #define MV88F6180_REV_A1	3
 
+#define MV88F6282_DEV_ID	0x6282
+#define MV88F6282_REV_A0	0
 #endif
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index a5900f6..065187d 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -23,7 +23,8 @@ static unsigned int __init kirkwood_variant(void)
 
 	kirkwood_pcie_id(&dev, &rev);
 
-	if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
+	if ((dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0) ||
+	    (dev == MV88F6282_DEV_ID))
 		return MPP_F6281_MASK;
 	if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
 		return MPP_F6192_MASK;
-- 
1.6.0.4



From saeed at marvell.com  Tue Jun  1 11:09:28 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Tue,  1 Jun 2010 18:09:28 +0300
Subject: [PATCH 3/3] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <1275404968-12258-2-git-send-email-saeed@marvell.com>
References: <1275404968-12258-1-git-send-email-saeed@marvell.com>
	<1275404968-12258-2-git-send-email-saeed@marvell.com>
Message-ID: <1275404968-12258-3-git-send-email-saeed@marvell.com>

This patch extens the kirkwood's PCIe support up to 2 controllers as in the 6282 devices.

Signed-off-by: Saeed Bishara <saeed at marvell.com>
---
 arch/arm/mach-kirkwood/addr-map.c                 |   10 +-
 arch/arm/mach-kirkwood/common.h                   |    2 +-
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c       |   10 +-
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h |    1 +
 arch/arm/mach-kirkwood/include/mach/irqs.h        |    1 +
 arch/arm/mach-kirkwood/include/mach/kirkwood.h    |   10 ++
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c    |    2 +-
 arch/arm/mach-kirkwood/openrd-setup.c             |    2 +-
 arch/arm/mach-kirkwood/pcie.c                     |  153 +++++++++++++++------
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c      |    2 +-
 arch/arm/mach-kirkwood/rd88f6281-setup.c          |    2 +-
 arch/arm/mach-kirkwood/ts219-setup.c              |    6 +-
 arch/arm/mach-kirkwood/ts41x-setup.c              |    2 +-
 13 files changed, 151 insertions(+), 52 deletions(-)

diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168..8d03bce 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
 #define ATTR_DEV_CS0		0x3e
 #define ATTR_PCIE_IO		0xe0
 #define ATTR_PCIE_MEM		0xe8
+#define ATTR_PCIE1_IO		0xd0
+#define ATTR_PCIE1_MEM		0xd8
 #define ATTR_SRAM		0x01
 
 /*
@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
 		      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
 	setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
 		      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
+	setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
+		      TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
+	setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
+		      TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
 
 	/*
 	 * Setup window for NAND controller.
 	 */
-	setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+	setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
 		      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
 
 	/*
 	 * Setup window for SRAM.
 	 */
-	setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+	setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
 		      TARGET_SRAM, ATTR_SRAM, -1);
 
 	/*
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05e8a8a..876f71a 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -34,7 +34,7 @@ void kirkwood_ehci_init(void);
 void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
-void kirkwood_pcie_init(void);
+void kirkwood_pcie_init(int init_port0, int init_port1);
 void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
 void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
 void kirkwood_spi_init(void);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4b..b11b5fe 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -74,9 +74,15 @@ static void __init db88f6281_init(void)
 
 static int __init db88f6281_pci_init(void)
 {
-	if (machine_is_db88f6281_bp())
-		kirkwood_pcie_init();
+	if (machine_is_db88f6281_bp()) {
+		u32 dev, rev;
+		int init_port1 = 0;
 
+		kirkwood_pcie_id(&dev, &rev);
+		if (dev == MV88F6282_DEV_ID)
+			init_port1 = 1;
+		kirkwood_pcie_init(1, init_port1);
+	}
 	return 0;
 }
 subsys_initcall(db88f6281_pci_init);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f501..2026b30 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,6 +59,7 @@
 #define CGC_SATA1		(1 << 15)
 #define CGC_XOR1		(1 << 16)
 #define CGC_CRYPTO		(1 << 17)
+#define CGC_PEX1		(1 << 18)
 #define CGC_GE1			(1 << 19)
 #define CGC_TDM			(1 << 20)
 #define CGC_RESERVED		((1 << 18) | (0x6 << 21))
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index f00a0a4..9da2eb5 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -23,6 +23,7 @@
 #define IRQ_KIRKWOOD_XOR_10	7
 #define IRQ_KIRKWOOD_XOR_11	8
 #define IRQ_KIRKWOOD_PCIE	9
+#define IRQ_KIRKWOOD_PCIE1	10
 #define IRQ_KIRKWOOD_GE00_SUM	11
 #define IRQ_KIRKWOOD_GE01_SUM	15
 #define IRQ_KIRKWOOD_USB	19
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index dd7eddb..058f06b 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -38,6 +38,11 @@
 #define KIRKWOOD_PCIE_IO_BUS_BASE	0x00000000
 #define KIRKWOOD_PCIE_IO_SIZE		SZ_1M
 
+#define KIRKWOOD_PCIE1_IO_PHYS_BASE	0xf5000000
+#define KIRKWOOD_PCIE1_IO_VIRT_BASE	0xfed00000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE	0x00000000
+#define KIRKWOOD_PCIE1_IO_SIZE		SZ_1M
+
 #define KIRKWOOD_REGS_PHYS_BASE		0xf1000000
 #define KIRKWOOD_REGS_VIRT_BASE		0xfee00000
 #define KIRKWOOD_REGS_SIZE		SZ_1M
@@ -46,6 +51,10 @@
 #define KIRKWOOD_PCIE_MEM_BUS_BASE	0xe0000000
 #define KIRKWOOD_PCIE_MEM_SIZE		SZ_128M
 
+#define KIRKWOOD_PCIE1_MEM_PHYS_BASE	0xd8000000
+#define KIRKWOOD_PCIE1_MEM_BUS_BASE	0xd8000000
+#define KIRKWOOD_PCIE1_MEM_SIZE		SZ_128M
+
 /*
  * Register Map
  */
@@ -72,6 +81,7 @@
 #define PCIE_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x40000)
 #define PCIE_LINK_CTRL		(PCIE_VIRT_BASE | 0x70)
 #define PCIE_STATUS		(PCIE_VIRT_BASE | 0x1a04)
+#define PCIE1_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x44000)
 
 #define USB_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x50000)
 
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 5e6f711..6e67f3c 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
 static int __init mv88f6281gtw_ge_pci_init(void)
 {
 	if (machine_is_mv88f6281gtw_ge())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(0, 1);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec..4174f48 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -85,7 +85,7 @@ static void __init openrd_init(void)
 static int __init openrd_pci_init(void)
 {
 	if (machine_is_openrd_base() || machine_is_openrd_client())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(0, 1);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index dee1eff..5c33324 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -21,26 +21,40 @@
 
 #define PCIE_BASE	((void __iomem *)PCIE_VIRT_BASE)
 
+struct pcie_port {
+	u8			index;
+	u8			root_bus_nr;
+	void __iomem		*base;
+	spinlock_t		conf_lock;
+	char			io_space_name[16];
+	char			mem_space_name[16];
+	struct resource		res[2];
+};
+
+static struct pcie_port pcie_port[2];
+static int num_pcie_ports;
+static struct pcie_port *bus_to_port(int bus);
+
 void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
 {
 	*dev = orion_pcie_dev_id(PCIE_BASE);
 	*rev = orion_pcie_rev(PCIE_BASE);
 }
 
-static int pcie_valid_config(int bus, int dev)
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 {
 	/*
 	 * Don't go out when trying to access --
 	 * 1. nonexisting device on local bus
 	 * 2. where there's no device connected (no link)
 	 */
-	if (bus == 0 && dev == 0)
+	if (bus == pp->root_bus_nr && dev == 0)
 		return 1;
 
-	if (!orion_pcie_link_up(PCIE_BASE))
+	if (!orion_pcie_link_up(pp->base))
 		return 0;
 
-	if (bus == 0 && dev != 1)
+	if (bus == pp->root_bus_nr && dev != 1)
 		return 0;
 
 	return 1;
@@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev)
  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  * transactions are atomic.
  */
-static DEFINE_SPINLOCK(kirkwood_pcie_lock);
 
 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 			int size, u32 *val)
 {
+	struct pcie_port *pp = bus_to_port(bus->number);
 	unsigned long flags;
 	int ret;
 
-	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
 		*val = 0xffffffff;
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
 
-	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
-	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+	spin_lock_irqsave(&pp->conf_lock, flags);
+	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+	spin_unlock_irqrestore(&pp->conf_lock, flags);
 
 	return ret;
 }
@@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 			int where, int size, u32 val)
 {
+	struct pcie_port *pp = bus_to_port(bus->number);
 	unsigned long flags;
 	int ret;
 
-	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
-	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
-	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+	spin_lock_irqsave(&pp->conf_lock, flags);
+	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+	spin_unlock_irqrestore(&pp->conf_lock, flags);
 
 	return ret;
 }
@@ -96,51 +111,84 @@ static struct pci_ops pcie_ops = {
 
 static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
 {
-	struct resource *res;
 	extern unsigned int kirkwood_clk_ctrl;
+	struct pcie_port *pp;
+
+	if (nr >= num_pcie_ports)
+		return 0;
+
+	pp = &pcie_port[nr];
+	pp->root_bus_nr = sys->busnr;
 
 	/*
 	 * Generic PCIe unit setup.
 	 */
-	orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
+	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+
+	orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
 
-	/*
-	 * Request resources.
-	 */
-	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-	if (!res)
-		panic("pcie_setup unable to alloc resources");
 
 	/*
 	 * IORESOURCE_IO
 	 */
-	res[0].name = "PCIe I/O Space";
-	res[0].flags = IORESOURCE_IO;
-	res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-	res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
-	if (request_resource(&ioport_resource, &res[0]))
+	snprintf(pp->io_space_name, sizeof(pp->io_space_name),
+		 "PCIe %d I/O", pp->index);
+	pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
+	pp->res[0].name = pp->io_space_name;
+	if (pp->index == 0) {
+		pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+		pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+	} else {
+		pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
+		pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
+	}
+	pp->res[0].flags = IORESOURCE_IO;
+	if (request_resource(&ioport_resource, &pp->res[0]))
 		panic("Request PCIe IO resource failed\n");
-	sys->resource[0] = &res[0];
+	sys->resource[0] = &pp->res[0];
 
 	/*
 	 * IORESOURCE_MEM
 	 */
-	res[1].name = "PCIe Memory Space";
-	res[1].flags = IORESOURCE_MEM;
-	res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
-	res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-	if (request_resource(&iomem_resource, &res[1]))
+	snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
+		 "PCIe %d MEM", pp->index);
+	pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
+	pp->res[1].name = pp->mem_space_name;
+	if (pp->index == 0) {
+		pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+		pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+	} else {
+		pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+		pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+	}
+	pp->res[1].flags = IORESOURCE_MEM;
+	if (request_resource(&iomem_resource, &pp->res[1]))
 		panic("Request PCIe Memory resource failed\n");
-	sys->resource[1] = &res[1];
+	sys->resource[1] = &pp->res[1];
 
 	sys->resource[2] = NULL;
 	sys->io_offset = 0;
 
-	kirkwood_clk_ctrl |= CGC_PEX0;
-
+	if (nr == 0)
+		kirkwood_clk_ctrl |= CGC_PEX0;
+	else
+		kirkwood_clk_ctrl |= CGC_PEX1;
 	return 1;
 }
 
+static struct pcie_port *bus_to_port(int bus)
+{
+	int i;
+
+	for (i = num_pcie_ports - 1; i >= 0; i--) {
+		int rbus = pcie_port[i].root_bus_nr;
+		if (rbus != -1 && rbus <= bus)
+			break;
+	}
+
+	return i >= 0 ? pcie_port + i : NULL;
+}
+
 static void __devinit rc_pci_fixup(struct pci_dev *dev)
 {
 	/*
@@ -163,7 +211,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 {
 	struct pci_bus *bus;
 
-	if (nr == 0) {
+	if (nr < num_pcie_ports) {
 		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
 	} else {
 		bus = NULL;
@@ -175,18 +223,45 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 
 static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-	return IRQ_KIRKWOOD_PCIE;
+	struct pcie_port *pp = bus_to_port(dev->bus->number);
+
+	return pp->index ? IRQ_KIRKWOOD_PCIE1 : IRQ_KIRKWOOD_PCIE;
 }
 
 static struct hw_pci kirkwood_pci __initdata = {
-	.nr_controllers	= 1,
+	.nr_controllers	= 2,
 	.swizzle	= pci_std_swizzle,
 	.setup		= kirkwood_pcie_setup,
 	.scan		= kirkwood_pcie_scan_bus,
 	.map_irq	= kirkwood_pcie_map_irq,
 };
 
-void __init kirkwood_pcie_init(void)
+static void __init add_pcie_port(int index, unsigned long base)
 {
+	printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
+
+	if (orion_pcie_link_up((void __iomem *)base)) {
+		struct pcie_port *pp = &pcie_port[num_pcie_ports++];
+
+		printk(KERN_INFO "link up\n");
+
+		pp->index = index;
+		pp->root_bus_nr = -1;
+		pp->base = (void __iomem *)base;
+		spin_lock_init(&pp->conf_lock);
+		memset(pp->res, 0, sizeof(pp->res));
+	} else {
+		printk(KERN_INFO "link down, ignoring\n");
+	}
+}
+
+void __init kirkwood_pcie_init(int init_port0, int init_port1)
+{
+	if (init_port0)
+		add_pcie_port(0, PCIE_VIRT_BASE);
+
+	if (init_port1)
+		add_pcie_port(1, PCIE1_VIRT_BASE);
+
 	pci_common_init(&kirkwood_pci);
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 3bf6304..e982bb7 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
 static int __init rd88f6192_pci_init(void)
 {
 	if (machine_is_rd88f6192_nas())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(0, 1);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31708dd..5b455b2 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
 static int __init rd88f6281_pci_init(void)
 {
 	if (machine_is_rd88f6281())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(0, 1);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0f..5fe8811 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -110,10 +110,10 @@ static void __init qnap_ts219_init(void)
 
 static int __init ts219_pci_init(void)
 {
-   if (machine_is_ts219())
-           kirkwood_pcie_init();
+	if (machine_is_ts219())
+		kirkwood_pcie_init(1, 0);
 
-   return 0;
+	return 0;
 }
 subsys_initcall(ts219_pci_init);
 
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index de49c2d..8505d30 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -136,7 +136,7 @@ static void __init qnap_ts41x_init(void)
 static int __init ts41x_pci_init(void)
 {
 	if (machine_is_ts41x())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(1, 0);
 
    return 0;
 }
-- 
1.6.0.4



From jason77.wang at gmail.com  Tue Jun  1 11:10:40 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Tue,  1 Jun 2010 23:10:40 +0800
Subject: [PATCH 0/3]Add i.MX51 3-stack board support
Message-ID: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>

These three patches will add a i.MX51 3-stack board support.
Currently, on this board, only 3 devices(serial, ethernet and
keypad) are registered and validated.

[PATCH 1/3] mxc: Add support for the imx51 3-stack board
[PATCH 2/3] mxc/iomux: add GPIO bank offset for iomux v3 platforms
[PATCH 3/3] mx51/clock: add keypad clock definition and registration




From jason77.wang at gmail.com  Tue Jun  1 11:10:41 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Tue,  1 Jun 2010 23:10:41 +0800
Subject: [PATCH 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275405043-18230-2-git-send-email-jason77.wang@gmail.com>

3-stack is a reference board from Freescale for their i.MX51 SoC.

Add board definition, Kconfig and Makefile to enable Freescale 3-stack
board.

Boot tested on a i.MX51 3-stack Rev2.0 board

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx5/Kconfig                       |    5 +
 arch/arm/mach-mx5/Makefile                      |    2 +-
 arch/arm/mach-mx5/board-mx51_3ds.c              |  356 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   73 +++++
 arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h |   43 +++
 5 files changed, 478 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
 create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
 create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 1576d51..6d45f44 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -15,4 +15,9 @@ config MACH_MX51_BABBAGE
 	  u-boot. This includes specific configurations for the board and its
 	  peripherals.
 
+config MACH_MX51_3DS
+	bool "Support MX51PDK (3DS)"
+	help
+	  Include support for MX51PDK (3DS) platform. This includes specific
+	  configurations for the board and its peripherals.
 endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index bf23f86..c757c59 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -6,4 +6,4 @@
 obj-y   := cpu.o mm.o clock-mx51.o devices.o
 
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-
+obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
new file mode 100644
index 0000000..604fb26
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -0,0 +1,356 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/smsc911x.h>
+#include <linux/input/matrix_keypad.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx51-3ds.h>
+#include <mach/board-mx51_3ds.h>
+#include <mach/gpio.h>
+#include <mach/imx-uart.h>
+
+#include "devices.h"
+
+static struct pad_desc mx51_3ds_pads[] = {
+	/* UART1 */
+	MX51_3DS_PAD_UART1_RXD__UART1_RXD,
+	MX51_3DS_PAD_UART1_TXD__UART1_TXD,
+	MX51_3DS_PAD_UART1_RTS__UART1_RTS,
+	MX51_3DS_PAD_UART1_CTS__UART1_CTS,
+
+	/* UART2 */
+	MX51_3DS_PAD_UART2_RXD__UART2_RXD,
+	MX51_3DS_PAD_UART2_TXD__UART2_TXD,
+	MX51_3DS_PAD_EIM_D25__UART2_CTS,
+	MX51_3DS_PAD_EIM_D26__UART2_RTS,
+
+	/* UART3 */
+	MX51_3DS_PAD_GPIO_1_22__UART3_RXD,
+	MX51_3DS_PAD_GPIO_1_23__UART3_TXD,
+	MX51_3DS_PAD_EIM_D24__UART3_CTS,
+	MX51_3DS_PAD_EIM_D27__UART3_RTS,
+
+	/* CPLD PARENT IRQ PIN */
+	MX51_3DS_PAD_GPIO_1_6__GPIO1_6,
+
+	/* KPP */
+	MX51_PAD_KEY_ROW0__KEY_ROW0,
+	MX51_PAD_KEY_ROW1__KEY_ROW1,
+	MX51_PAD_KEY_ROW2__KEY_ROW2,
+	MX51_PAD_KEY_ROW3__KEY_ROW3,
+	MX51_PAD_KEY_COL0__KEY_COL0,
+	MX51_PAD_KEY_COL1__KEY_COL1,
+	MX51_PAD_KEY_COL2__KEY_COL2,
+	MX51_PAD_KEY_COL3__KEY_COL3,
+	MX51_PAD_KEY_COL4__KEY_COL4,
+	MX51_PAD_KEY_COL5__KEY_COL5,
+};
+
+#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
+static int mx51_3ds_board_keymap[] = {
+	KEY(0, 0, KEY_1),
+	KEY(0, 1, KEY_2),
+	KEY(0, 2, KEY_3),
+	KEY(0, 3, KEY_F1),
+	KEY(0, 4, KEY_UP),
+	KEY(0, 5, KEY_F2),
+
+	KEY(1, 0, KEY_4),
+	KEY(1, 1, KEY_5),
+	KEY(1, 2, KEY_6),
+	KEY(1, 3, KEY_LEFT),
+	KEY(1, 4, KEY_SELECT),
+	KEY(1, 5, KEY_RIGHT),
+
+	KEY(2, 0, KEY_7),
+	KEY(2, 1, KEY_8),
+	KEY(2, 2, KEY_9),
+	KEY(2, 3, KEY_F3),
+	KEY(2, 4, KEY_DOWN),
+	KEY(2, 5, KEY_F4),
+
+	KEY(3, 0, KEY_0),
+	KEY(3, 1, KEY_OK),
+	KEY(3, 2, KEY_ESC),
+	KEY(3, 3, KEY_ENTER),
+	KEY(3, 4, KEY_MENU),
+	KEY(3, 5, KEY_BACK)
+};
+
+static struct resource mx51_3ds_kpp_resources[] = {
+	{
+		.start = MX51_MXC_INT_KPP,
+		.end = MX51_MXC_INT_KPP,
+		.flags = IORESOURCE_IRQ,
+	} , {
+		.start = MX51_KPP_BASE_ADDR,
+		.end = MX51_KPP_BASE_ADDR + 0x8 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+static struct matrix_keymap_data mx51_3ds_map_data = {
+	.keymap		= mx51_3ds_board_keymap,
+	.keymap_size	= ARRAY_SIZE(mx51_3ds_board_keymap),
+};
+
+static struct platform_device mx51_3ds_keypad_device = {
+	.name = "imx-keypad",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(mx51_3ds_kpp_resources),
+	.resource = mx51_3ds_kpp_resources,
+	.dev = {
+		.platform_data = &mx51_3ds_map_data,
+	},
+};
+
+static void mxc_init_keypad(void)
+{
+	(void)platform_device_register(&mx51_3ds_keypad_device);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
+
+
+static u32 cpld_base_addr;
+
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+static struct resource smsc911x_resources[] = {
+	{
+		.flags = IORESOURCE_MEM,
+	} , {
+		.start = LAN9217_IRQ,
+		.end = LAN9217_IRQ,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct smsc911x_platform_config smsc911x_config = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+};
+
+static struct platform_device smsc_lan9217_device = {
+	.name = "smsc911x",
+	.id = 0,
+	.dev = {
+		.platform_data = &smsc911x_config,
+	},
+	.num_resources = ARRAY_SIZE(smsc911x_resources),
+	.resource = smsc911x_resources,
+};
+
+static void mxc_init_enet(void)
+{
+	if (cpld_base_addr) {
+		smsc_lan9217_device.resource[0].start =
+		    LAN9217_BASE_ADDR(cpld_base_addr);
+		smsc_lan9217_device.resource[0].end =
+		    LAN9217_BASE_ADDR(cpld_base_addr) + 0x100;
+		(void)platform_device_register(&smsc_lan9217_device);
+	}
+}
+#else
+static inline void mxc_init_enet(void)
+{
+}
+#endif
+
+static u32 brd_io;
+static void expio_ack_irq(u32 irq);
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+	u32 imr_val;
+	u32 int_valid;
+	u32 expio_irq;
+
+	desc->chip->mask(irq);	/* irq = gpio irq number */
+
+	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
+	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
+
+	if (unlikely(!int_valid))
+		goto out;
+
+	expio_irq = MXC_BOARD_IRQ_START;
+	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+		struct irq_desc *d;
+		if ((int_valid & 1) == 0)
+			continue;
+		d = irq_desc + expio_irq;
+		if (unlikely(!(d->handle_irq))) {
+			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
+			BUG();	/* oops */
+		}
+		d->handle_irq(expio_irq, d);
+	}
+
+out:
+	desc->chip->ack(irq);
+	desc->chip->unmask(irq);
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * @param irq		an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+	/* mask the interrupt */
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg |= (1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+/*
+ * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
+ * @param irq		an expanded io virtual irq number
+ */
+static void expio_ack_irq(u32 irq)
+{
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+	/* clear the interrupt status */
+	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	/* mask the interrupt */
+	expio_mask_irq(irq);
+}
+
+/*
+ * Enable a expio pin's interrupt by clearing the bit in the imr.
+ * @param irq		a expio virtual irq number
+ */
+static void expio_unmask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+	/* unmask the interrupt */
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg &= ~(1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+	.ack = expio_ack_irq,
+	.mask = expio_mask_irq,
+	.unmask = expio_unmask_irq,
+};
+
+static int __init mxc_expio_init(void)
+{
+	int i;
+
+	brd_io = (u32) ioremap(BOARD_IO_ADDR(MX51_CS5_BASE_ADDR), SZ_4K);
+	if (brd_io == 0)
+		return -ENOMEM;
+
+	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
+		pr_info("3-Stack Debug board not detected\n");
+		cpld_base_addr = 0;
+		return -ENODEV;
+	} else {
+		cpld_base_addr = MX51_CS5_BASE_ADDR;
+	}
+
+	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
+		readw(brd_io + CPLD_CODE_VER_REG));
+
+	/*
+	 * Configure INT line as GPIO input
+	 */
+	gpio_request(MX51_3DS_CPLD_IRQ_PIN, "gpio1_6");
+	gpio_direction_input(MX51_3DS_CPLD_IRQ_PIN);
+
+	/* disable the interrupt and clear the status */
+	__raw_writew(0, brd_io + INTR_MASK_REG);
+	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
+	for (i = MXC_BOARD_IRQ_START;
+	     i < (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS); i++) {
+		set_irq_chip(i, &expio_irq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+	set_irq_type(EXPIO_PARENT_INT, IRQF_TRIGGER_LOW);
+	set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler);
+
+	return 0;
+}
+
+/* Serial ports */
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static struct imxuart_platform_data uart_pdata = {
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	mxc_register_device(&mxc_uart_device1, &uart_pdata);
+	mxc_register_device(&mxc_uart_device2, &uart_pdata);
+}
+#else /* !SERIAL_IMX */
+static inline void mxc_init_imx_uart(void)
+{
+}
+#endif /* SERIAL_IMX */
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
+					ARRAY_SIZE(mx51_3ds_pads));
+	mxc_init_imx_uart();
+	mxc_expio_init();
+	mxc_init_enet();
+	mxc_init_keypad();
+}
+
+static void __init mx51_3ds_timer_init(void)
+{
+	mx51_clocks_init(32768, 24000000, 22579200, 24576000);
+}
+
+static struct sys_timer mxc_timer = {
+	.init	= mx51_3ds_timer_init,
+};
+
+MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
+	.phys_io = MX51_AIPS1_BASE_ADDR,
+	.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+	.boot_params = PHYS_OFFSET + 0x100,
+	.map_io = mx51_map_io,
+	.init_irq = mx51_init_irq,
+	.init_machine = mxc_board_init,
+	.timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
new file mode 100644
index 0000000..6900a7f
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
+#define __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
+
+/*
+ * @file plat-mxc/include/mach/board-mx51_3ds.h
+ *
+ * @brief This file contains all the board level configuration options.
+ *
+ * It currently hold the options defined for MX51 3Stack Platform.
+ *
+ */
+
+#define MXC_LL_UART_PADDR	UART1_BASE_ADDR
+#define MXC_LL_UART_VADDR	AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
+
+#define DEBUG_BOARD_BASE_ADDRESS(n)	(n)
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n))
+/* External UART */
+#define UARTA_BASE_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n) + 0x8000)
+#define UARTB_BASE_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n) + 0x10000)
+
+#define BOARD_IO_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n) + 0x20000)
+/* LED switchs */
+#define LED_SWITCH_REG		0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG	0x08
+/* status, interrupt */
+#define INTR_STATUS_REG	0x10
+#define INTR_MASK_REG		0x38
+#define INTR_RESET_REG		0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG	0x40
+#define MAGIC_NUMBER2_REG	0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG	0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG	0x58
+/* module reset register*/
+#define MODULE_RESET_REG	0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG	0x68
+
+/* interrupts like external uart , external ethernet etc*/
+#define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
+
+#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
+#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
+#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
+#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
+#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
+
+/* This is System IRQ used by LAN9217 */
+#define LAN9217_IRQ	EXPIO_INT_ENET
+
+/* Define CPLD interrupt pin */
+#define MX51_3DS_CPLD_IRQ_PIN	(GPIO_PORTA + 6)
+
+#endif	/* __ASM_ARCH_MXC_BOARD_MX51_3DS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h b/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h
new file mode 100644
index 0000000..33f1141
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __MACH_IOMUX_MX51_3DS_H__
+#define __MACH_IOMUX_MX51_3DS_H__
+
+#include <mach/iomux-mx51.h>
+
+/* UART1 */
+#define MX51_3DS_PAD_UART1_RXD__UART1_RXD	MX51_PAD_UART1_RXD__UART1_RXD
+#define MX51_3DS_PAD_UART1_TXD__UART1_TXD	MX51_PAD_UART1_TXD__UART1_TXD
+#define MX51_3DS_PAD_UART1_RTS__UART1_RTS	MX51_PAD_UART1_RTS__UART1_RTS
+#define MX51_3DS_PAD_UART1_CTS__UART1_CTS	MX51_PAD_UART1_CTS__UART1_CTS
+
+/* UART2 */
+#define MX51_3DS_PAD_UART2_RXD__UART2_RXD	MX51_PAD_UART2_RXD__UART2_RXD
+#define MX51_3DS_PAD_UART2_TXD__UART2_TXD	MX51_PAD_UART2_TXD__UART2_TXD
+#define MX51_3DS_PAD_EIM_D25__UART2_CTS		IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT4, 0x0, 0, \
+						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
+#define MX51_3DS_PAD_EIM_D26__UART2_RTS		IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT4, 0x9e8, 3, \
+						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
+
+/* UART3 */
+#define MX51_3DS_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, \
+						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
+#define MX51_3DS_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, \
+						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
+#define MX51_3DS_PAD_EIM_D24__UART3_CTS		IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, \
+						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
+#define MX51_3DS_PAD_EIM_D27__UART3_RTS		IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 3, \
+						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
+/* CPLD */
+#define MX51_3DS_PAD_GPIO_1_6__GPIO1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
+
+#endif /* __MACH_IOMUX_MX51_3DS_H__ */
-- 
1.5.6.5



From jason77.wang at gmail.com  Tue Jun  1 11:10:42 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Tue,  1 Jun 2010 23:10:42 +0800
Subject: [PATCH 2/3] mxc/iomux: add GPIO bank offset for iomux v3 platforms
In-Reply-To: <1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275405043-18230-3-git-send-email-jason77.wang@gmail.com>

These GPIO bank offsets are useful when define a gpio number.
E.G. when GPIO PORTC pin 6 is used for irq request pin of external
expanding device, we can define it like:
  #define EXP_PARENT_IRQ_PIN (GPIO_PORTC + 6)

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/include/mach/iomux-v3.h |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index f2f73d3..0880a4a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -89,6 +89,21 @@ struct pad_desc {
 #define PAD_CTL_SRE_FAST		(1 << 0)
 #define PAD_CTL_SRE_SLOW		(0 << 0)
 
+
+#define MX51_NUM_GPIO_PORT	4
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA	(0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB	(1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC	(2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD	(3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE	(4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF	(5 << GPIO_PORT_SHIFT)
+
 /*
  * setups a single pad in the iomuxer
  */
-- 
1.5.6.5



From jason77.wang at gmail.com  Tue Jun  1 11:10:43 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Tue,  1 Jun 2010 23:10:43 +0800
Subject: [PATCH 3/3] mx51/clock: add keypad clock definition and registration
In-Reply-To: <1275405043-18230-3-git-send-email-jason77.wang@gmail.com>
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-3-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275405043-18230-4-git-send-email-jason77.wang@gmail.com>

On i.MX51 platforms, the keypad controller has no gate clock, to
meet the imx keypad driver requirement, we add a empty definition and
register it. Now the keypad driver can work.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx5/clock-mx51.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index d9f612d..e89b93a 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
 	.parent = &ckil_clk,
 };
 
+static struct clk kpp_clk = {
+	.id = 0,
+};
+
 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
 	static struct clk name = {			\
 		.id		= i,			\
@@ -821,6 +825,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
+	_REGISTER_CLOCK(NULL, "kpp", kpp_clk)
 };
 
 static void clk_tree_init(void)
-- 
1.5.6.5



From fabioestevam at yahoo.com  Tue Jun  1 11:35:06 2010
From: fabioestevam at yahoo.com (Fabio Estevam)
Date: Tue, 1 Jun 2010 08:35:06 -0700 (PDT)
Subject: [PATCH 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <82469.38984.qm@web51002.mail.re2.yahoo.com>

Hi Jason,

--- On Tue, 6/1/10, Jason Wang <jason77.wang at gmail.com> wrote:
...
> +static void __init mx51_3ds_timer_init(void)
> +{
> +??? mx51_clocks_init(32768, 24000000, 22579200, 24576000)

This should be:

mx51_clocks_init(32768, 24000000, 22579200, 0)

Regards,

Fabio Estevam


      


From fabioestevam at yahoo.com  Tue Jun  1 11:56:22 2010
From: fabioestevam at yahoo.com (Fabio Estevam)
Date: Tue, 1 Jun 2010 08:56:22 -0700 (PDT)
Subject: [PATCH 3/3] mx51/clock: add keypad clock definition and
	registration
In-Reply-To: <1275405043-18230-4-git-send-email-jason77.wang@gmail.com>
Message-ID: <495250.54370.qm@web51001.mail.re2.yahoo.com>

Jason,

--- On Tue, 6/1/10, Jason Wang <jason77.wang at gmail.com> wrote:

> From: Jason Wang <jason77.wang at gmail.com>
> Subject: [PATCH 3/3] mx51/clock: add keypad clock definition and registration
> To: s.hauer at pengutronix.de, amit.kucheria at canonical.com
> Cc: linux-arm-kernel at lists.infradead.org
> Date: Tuesday, June 1, 2010, 12:10 PM
> On i.MX51 platforms, the keypad
> controller has no gate clock, to
> meet the imx keypad driver requirement, we add a empty
> definition and
> register it. Now the keypad driver can work.

I did not see an entry for the keypad at arch/arm/mach-mx5/devices.c.

Regards,

Fabio Estevam


      


From fachkar.datawind at gmail.com  Tue Jun  1 12:48:36 2010
From: fachkar.datawind at gmail.com (f. achkar)
Date: Tue, 01 Jun 2010 12:48:36 -0400
Subject: incorrect panic("failed to get clock for system timer"); ??
Message-ID: <4C0539E4.9090501@gmail.com>

Hi,
Newbie debugging Linux-2.6.32-9 on S3C2450, the kernel seems to panic at :
s3c2410_timer_init () at arch/arm/plat-s3c/time.c:256

if (IS_ERR(timerclk))
        panic("failed to get clock for system timer");

more precisely  'if (IS_ERR(timerclk))' is non-null !?! although the
'timerclk' seem to be fine:
(gdb) print *timerclk
$27 = {list = {next = 0xc04a933c, prev = 0xc04a93ac}, owner = 0x0,
parent = 0xc04abfd4, name = 0xc042c5a1 "timers", id = -1,
  usage = 0, rate = 0, ctrlbit = 1024, enable = 0xc009631c
<s3c2443_clkcon_enable_p>, set_rate = 0, get_rate = 0,
  round_rate = 0, set_parent = 0}
(gdb) s
257            panic("failed to get clock for system timer");
(gdb) print (unsigned long)(timerclk)
$28 = 3226112884
(gdb)

I'm not sure why 'IS_ERR(timerclk)' is holding true? or is it a bug ?
thanks,
ferar


From cbouatmailru at gmail.com  Tue Jun  1 12:54:09 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 1 Jun 2010 20:54:09 +0400
Subject: [GIT PULL] Some Cavium CNS3xxx updates for 2.6.36
Message-ID: <20100601165409.GA29614@oksana.dev.rtsoft.ru>

Hello Russell,

As Linus' merge window is now officially closed, I believe
we can start requesting pulls for -next?

It's that early because I'd like the already posted patches
separated from any further work to be submitted.

And the following leftovers were posted long ago, but were
waiting for -mm and libata trees:

- cns3xxx: Add support for SDHCI controllers
  http://lists.infradead.org/pipermail/linux-arm-kernel/2010-March/012149.html
- cns3xxx: Add support for AHCI controllers
  http://lists.infradead.org/pipermail/linux-arm-kernel/2010-March/012150.html
- cns3xxx: Add support for PCI Express ports
  http://lists.infradead.org/pipermail/linux-arm-kernel/2010-March/012462.html

For convenience I'm posting the patches again + defconfig update,
and if everything looks reasonable, linux-cns3xxx's master branch
is ready for you to pull.

Thanks!

The following changes since commit 9dda696f0de87a2e5cfabb147e28c76b7d3c6846:
  Linus Torvalds (1):
        Merge branch 'release' of git://git.kernel.org/.../aegl/linux-2.6

are available in the git repository at:

  git://git.infradead.org/users/cbou/linux-cns3xxx.git master

Anton Vorontsov (4):
      ARM: cns3xxx: Add support for PCI Express ports
      ARM: cns3xxx: Add support for SDHCI controllers
      ARM: cns3xxx: Add support for AHCI controllers
      ARM: cns3xxx: Update defconfig to enable AHCI, PCIe and net devices

 arch/arm/Kconfig                     |    3 +-
 arch/arm/configs/cns3420vb_defconfig |  410 ++++++++++++++++++++++++++++++++--
 arch/arm/mach-cns3xxx/Makefile       |    3 +-
 arch/arm/mach-cns3xxx/cns3420vb.c    |    3 +
 arch/arm/mach-cns3xxx/core.c         |   30 +++
 arch/arm/mach-cns3xxx/devices.c      |  206 +++++++++++++++++
 arch/arm/mach-cns3xxx/devices.h      |   20 ++
 arch/arm/mach-cns3xxx/pcie.c         |  352 +++++++++++++++++++++++++++++
 8 files changed, 1008 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/mach-cns3xxx/devices.c
 create mode 100644 arch/arm/mach-cns3xxx/devices.h
 create mode 100644 arch/arm/mach-cns3xxx/pcie.c

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2


From cbouatmailru at gmail.com  Tue Jun  1 12:55:02 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 1 Jun 2010 20:55:02 +0400
Subject: [PATCH 1/4] ARM: cns3xxx: Add support for PCI Express ports
In-Reply-To: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
References: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
Message-ID: <20100601165502.GA7123@oksana.dev.rtsoft.ru>

This patch adds PCIe support for CNS3xxx-based boards. The support
was tested with a directly attached SKY2 NIC, and EHCI USB controller
behind the PLX PEX8112 P2P bridge (to make sure that type1 cfg cycles
work as expected).

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/Kconfig               |    3 +-
 arch/arm/mach-cns3xxx/Makefile |    1 +
 arch/arm/mach-cns3xxx/core.c   |   30 ++++
 arch/arm/mach-cns3xxx/pcie.c   |  352 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 385 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-cns3xxx/pcie.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..fab2ddd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -301,6 +301,7 @@ config ARCH_CNS3XXX
 	select CPU_V6
 	select GENERIC_CLOCKEVENTS
 	select ARM_GIC
+	select PCI_DOMAINS if PCI
 	help
 	  Support for Cavium Networks CNS3XXX platform.
 
@@ -1059,7 +1060,7 @@ config ISA_DMA_API
 	bool
 
 config PCI
-	bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
+	bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
 	help
 	  Find out whether you have a PCI motherboard. PCI is the name of a
 	  bus system, i.e. the way the CPU talks to the other stuff inside
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 427507a..683f117 100644
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o pm.o
+obj-$(CONFIG_PCI)			+= pcie.o
 obj-$(CONFIG_MACH_CNS3420VB)		+= cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 9ca4d58..2850a4b 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -60,6 +60,36 @@ static struct map_desc cns3xxx_io_desc[] __initdata = {
 		.pfn		= __phys_to_pfn(CNS3XXX_PM_BASE),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
+	}, {
+		.virtual	= CNS3XXX_PCIE0_HOST_BASE_VIRT,
+		.pfn		= __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
+		.length		= SZ_16M,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= CNS3XXX_PCIE0_CFG0_BASE_VIRT,
+		.pfn		= __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
+		.length		= SZ_16M,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= CNS3XXX_PCIE0_CFG1_BASE_VIRT,
+		.pfn		= __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
+		.length		= SZ_16M,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= CNS3XXX_PCIE1_HOST_BASE_VIRT,
+		.pfn		= __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
+		.length		= SZ_16M,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= CNS3XXX_PCIE1_CFG0_BASE_VIRT,
+		.pfn		= __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
+		.length		= SZ_16M,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= CNS3XXX_PCIE1_CFG1_BASE_VIRT,
+		.pfn		= __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
+		.length		= SZ_16M,
+		.type		= MT_DEVICE,
 	},
 };
 
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
new file mode 100644
index 0000000..324aa5d
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -0,0 +1,352 @@
+/*
+ * PCI-E support for CNS3xxx
+ *
+ * Copyright 2008 Cavium Networks
+ *		  Richard Liu <richard.liu at caviumnetworks.com>
+ * Copyright 2010 MontaVista Software, LLC.
+ *		  Anton Vorontsov <avorontsov at mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/bug.h>
+#include <linux/pci.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+#include <mach/cns3xxx.h>
+#include "core.h"
+
+enum cns3xxx_access_type {
+	CNS3XXX_HOST_TYPE = 0,
+	CNS3XXX_CFG0_TYPE,
+	CNS3XXX_CFG1_TYPE,
+	CNS3XXX_NUM_ACCESS_TYPES,
+};
+
+struct cns3xxx_pcie {
+	u32 cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
+	unsigned int irqs[2];
+	struct resource res_io;
+	struct resource res_mem;
+	struct hw_pci hw_pci;
+
+	bool linked;
+};
+
+static struct cns3xxx_pcie cns3xxx_pcie[];
+
+static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
+{
+	struct pci_sys_data *root = sysdata;
+
+	return &cns3xxx_pcie[root->domain];
+}
+
+static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev)
+{
+	return sysdata_to_cnspci(dev->sysdata);
+}
+
+static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
+{
+	return sysdata_to_cnspci(bus->sysdata);
+}
+
+static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
+				  unsigned int devfn, int where)
+{
+	struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
+	int busno = bus->number;
+	int slot = PCI_SLOT(devfn);
+	int offset;
+	enum cns3xxx_access_type type;
+	void __iomem *base;
+
+	/* If there is no link, just show the CNS PCI bridge. */
+	if (!cnspci->linked && (busno > 0 || slot > 0))
+		return NULL;
+
+	/*
+	 * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
+	 * we still want to access it. For this to work, we must place
+	 * the first device on the same bus as the CNS PCI bridge.
+	 */
+	if (busno == 0) {
+		if (slot > 1)
+			return NULL;
+		type = slot;
+	} else {
+		type = CNS3XXX_CFG1_TYPE;
+	}
+
+	base = __io(cnspci->cfg_bases[type]);
+	offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
+
+	return base + offset;
+}
+
+static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+				   int where, int size, u32 *val)
+{
+	u32 v;
+	void __iomem *base;
+	u32 mask = (0x1ull << (size * 8)) - 1;
+	int shift = (where % 4) * 8;
+
+	base = cns3xxx_pci_cfg_base(bus, devfn, where);
+	if (!base) {
+		*val = 0xffffffff;
+		return PCIBIOS_SUCCESSFUL;
+	}
+
+	v = (__raw_readl(base) >> shift) & mask;
+
+	if (bus->number == 0 && devfn == 0 && size == 4 && where == 0x8) {
+		/*
+		 * RC's class is 0xb, but Linux PCI driver needs 0x604
+		 * for a PCIe bridge. So we must fixup the class code
+		 * to 0x604 here.
+		 */
+		v &= 0xff;
+		v |= 0x604 << 16;
+	}
+
+	*val = v;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+				    int where, int size, u32 val)
+{
+	u32 v;
+	void __iomem *base;
+	u32 mask = (0x1ull << (size * 8)) - 1;
+	int shift = (where % 4) * 8;
+
+	base = cns3xxx_pci_cfg_base(bus, devfn, where);
+	if (!base)
+		return PCIBIOS_SUCCESSFUL;
+
+	v = __raw_readl(base);
+
+	v &= ~(mask << shift);
+	v |= (val & mask) << shift;
+
+	__raw_writel(v, base);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
+{
+	struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
+	struct resource *res_io = &cnspci->res_io;
+	struct resource *res_mem = &cnspci->res_mem;
+	struct resource **sysres = sys->resource;
+
+	BUG_ON(request_resource(&iomem_resource, res_io) ||
+	       request_resource(&iomem_resource, res_mem));
+
+	sysres[0] = res_io;
+	sysres[1] = res_mem;
+
+	return 1;
+}
+
+static struct pci_ops cns3xxx_pcie_ops = {
+	.read = cns3xxx_pci_read_config,
+	.write = cns3xxx_pci_write_config,
+};
+
+static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
+{
+	return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
+}
+
+static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
+	int irq = cnspci->irqs[slot];
+
+	pr_info("PCIe0 map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
+		pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
+		PCI_FUNC(dev->devfn), slot, pin, irq);
+
+	return irq;
+}
+
+static struct cns3xxx_pcie cns3xxx_pcie[2] = {
+	[0] = {
+		.cfg_bases = {
+			[CNS3XXX_HOST_TYPE] = CNS3XXX_PCIE0_HOST_BASE_VIRT,
+			[CNS3XXX_CFG0_TYPE] = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
+			[CNS3XXX_CFG1_TYPE] = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
+		},
+		.irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
+		.res_io = {
+			.name = "PCIe0 I/O space",
+			.start = CNS3XXX_PCIE0_IO_BASE,
+			.end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1,
+			.flags = IORESOURCE_IO,
+		},
+		.res_mem = {
+			.name = "PCIe0 non-prefetchable",
+			.start = CNS3XXX_PCIE0_MEM_BASE,
+			.end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
+			.flags = IORESOURCE_MEM,
+		},
+		.hw_pci = {
+			.domain = 0,
+			.swizzle = pci_std_swizzle,
+			.nr_controllers = 1,
+			.setup = cns3xxx_pci_setup,
+			.scan = cns3xxx_pci_scan_bus,
+			.map_irq = cns3xxx_pcie_map_irq,
+		},
+	},
+	[1] = {
+		.cfg_bases = {
+			[CNS3XXX_HOST_TYPE] = CNS3XXX_PCIE1_HOST_BASE_VIRT,
+			[CNS3XXX_CFG0_TYPE] = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
+			[CNS3XXX_CFG1_TYPE] = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
+		},
+		.irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
+		.res_io = {
+			.name = "PCIe1 I/O space",
+			.start = CNS3XXX_PCIE1_IO_BASE,
+			.end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1,
+			.flags = IORESOURCE_IO,
+		},
+		.res_mem = {
+			.name = "PCIe1 non-prefetchable",
+			.start = CNS3XXX_PCIE1_MEM_BASE,
+			.end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
+			.flags = IORESOURCE_MEM,
+		},
+		.hw_pci = {
+			.domain = 1,
+			.swizzle = pci_std_swizzle,
+			.nr_controllers = 1,
+			.setup = cns3xxx_pci_setup,
+			.scan = cns3xxx_pci_scan_bus,
+			.map_irq = cns3xxx_pcie_map_irq,
+		},
+	},
+};
+
+static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
+{
+	int port = cnspci->hw_pci.domain;
+	u32 reg;
+	unsigned long time;
+
+	reg = __raw_readl(MISC_PCIE_CTRL(port));
+	/*
+	 * Enable Application Request to 1, it will exit L1 automatically,
+	 * but when chip back, it will use another clock, still can use 0x1.
+	 */
+	reg |= 0x3;
+	__raw_writel(reg, MISC_PCIE_CTRL(port));
+
+	pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
+	pr_info("PCIe: Port[%d] Check data link layer...", port);
+
+	time = jiffies;
+	while (1) {
+		reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
+		if (reg & 0x1) {
+			pr_info("Link up.\n");
+			cnspci->linked = 1;
+			break;
+		} else if (time_after(jiffies, time + 50)) {
+			pr_info("Device not found.\n");
+			break;
+		}
+	}
+}
+
+static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
+{
+	int port = cnspci->hw_pci.domain;
+	struct pci_sys_data sd = {
+		.domain = port,
+	};
+	struct pci_bus bus = {
+		.number = 0,
+		.ops = &cns3xxx_pcie_ops,
+		.sysdata = &sd,
+	};
+	u32 io_base = cnspci->res_io.start >> 16;
+	u32 mem_base = cnspci->res_mem.start >> 16;
+	u32 host_base = (cnspci->cfg_bases[CNS3XXX_HOST_TYPE] - 1) >> 16;
+	u32 cfg0_base = (cnspci->cfg_bases[CNS3XXX_CFG0_TYPE] - 1) >> 16;
+	u32 devfn = 0;
+	u8 tmp8;
+	u16 pos;
+	u16 dc;
+
+	pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
+	pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
+	pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
+
+	pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
+	pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
+	pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
+
+	pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
+	pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base);
+	pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
+	pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base);
+
+	if (!cnspci->linked)
+		return;
+
+	/* Set Device Max_Read_Request_Size to 128 byte */
+	devfn = PCI_DEVFN(1, 0);
+	pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
+	pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+	dc &= ~(0x3 << 12);	/* Clear Device Control Register [14:12] */
+	pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
+	pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+	if (!(dc & (0x3 << 12)))
+		pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n");
+
+	/* Disable PCIe0 Interrupt Mask INTA to INTD */
+	__raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
+}
+
+static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
+				      struct pt_regs *regs)
+{
+	if (fsr & (1 << 10))
+		regs->ARM_pc += 4;
+	return 0;
+}
+
+static int __init cns3xxx_pcie_init(void)
+{
+	int i;
+
+	hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS,
+			"imprecise external abort");
+
+	for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+		cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
+		cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
+		cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+		cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+		pci_common_init(&cns3xxx_pcie[i].hw_pci);
+	}
+
+	pci_assign_unassigned_resources();
+
+	return 0;
+}
+device_initcall(cns3xxx_pcie_init);
-- 
1.7.0.5



From cbouatmailru at gmail.com  Tue Jun  1 12:55:18 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 1 Jun 2010 20:55:18 +0400
Subject: [PATCH 2/4] ARM: cns3xxx: Add support for SDHCI controllers
In-Reply-To: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
References: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
Message-ID: <20100601165518.GB7123@oksana.dev.rtsoft.ru>

CNS3xxx chips have SDHCI-compatible SDIO/SD/MMC controller. This patch
adds the support using generic sdhci-pltfm driver.

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/mach-cns3xxx/Makefile    |    2 +-
 arch/arm/mach-cns3xxx/cns3420vb.c |    2 +
 arch/arm/mach-cns3xxx/devices.c   |  145 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-cns3xxx/devices.h   |   19 +++++
 4 files changed, 167 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-cns3xxx/devices.c
 create mode 100644 arch/arm/mach-cns3xxx/devices.h

diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 683f117..11033f1 100644
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,3 +1,3 @@
-obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o pm.o
+obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o pm.o devices.o
 obj-$(CONFIG_PCI)			+= pcie.o
 obj-$(CONFIG_MACH_CNS3420VB)		+= cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 2e30c82..df9ca5b 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -32,6 +32,7 @@
 #include <mach/cns3xxx.h>
 #include <mach/irqs.h>
 #include "core.h"
+#include "devices.h"
 
 /*
  * NOR Flash
@@ -111,6 +112,7 @@ static void __init cns3420_early_serial_setup(void)
  */
 static struct platform_device *cns3420_pdevs[] __initdata = {
 	&cns3420_nor_pdev,
+	&cns3xxx_sdhci_pdev,
 };
 
 static void __init cns3420_init(void)
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
new file mode 100644
index 0000000..549ad0c
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -0,0 +1,145 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *		  Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *		  Anton Vorontsov <avorontsov at mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+#include <linux/sdhci-pltfm.h>
+#include "../../../drivers/mmc/host/sdhci.h"
+#include "devices.h"
+
+/*
+ * SDHCI
+ */
+static struct resource cns3xxx_sdhci_resources[] = {
+	[0] = {
+		.start = CNS3XXX_SDIO_BASE,
+		.end   = CNS3XXX_SDIO_BASE + SZ_4K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_CNS3XXX_SDIO,
+		.end   = IRQ_CNS3XXX_SDIO,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static int cns3xxx_sdhci_init(struct sdhci_host *host)
+{
+	u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+	u32 gpioa_pins = __raw_readl(gpioa);
+
+	/* MMC/SD pins share with GPIOA */
+	gpioa_pins |= 0x1fff0004;
+	__raw_writel(gpioa_pins, gpioa);
+
+	cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
+	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
+
+	return 0;
+}
+
+static unsigned int cns3xxx_sdhci_get_max_clk(struct sdhci_host *host)
+{
+	return 150000000;
+}
+
+static unsigned int cns3xxx_sdhci_get_timeout_clk(struct sdhci_host *host)
+{
+	return cns3xxx_sdhci_get_max_clk(host) / 100000;
+}
+
+static void cns3xxx_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
+{
+	int div = 1;
+	u16 clk;
+	unsigned long timeout;
+
+	if (clock == host->clock)
+		return;
+
+	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
+
+	if (clock == 0)
+		goto out;
+
+	while (host->max_clk / div > clock) {
+		/*
+		 * On CNS3xxx divider grows linearly up to 4, and then
+		 * exponentially up to 256.
+		 */
+		if (div < 4)
+			div += 1;
+		else if (div < 256)
+			div *= 2;
+		else
+			break;
+	}
+
+	dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n",
+		clock, host->max_clk / div);
+
+	/* Divide by 3 is special. */
+	if (div != 3)
+		div >>= 1;
+
+	clk = div << SDHCI_DIVIDER_SHIFT;
+	clk |= SDHCI_CLOCK_INT_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+	timeout = 10;
+	while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+			& SDHCI_CLOCK_INT_STABLE)) {
+		if (timeout == 0)
+			return;
+		timeout--;
+		mdelay(1);
+	}
+
+	clk |= SDHCI_CLOCK_CARD_EN;
+	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+	host->timeout_clk = cns3xxx_sdhci_get_timeout_clk(host);
+out:
+	host->clock = clock;
+}
+
+static struct sdhci_ops cns3xxx_sdhci_ops = {
+	.get_max_clock		= cns3xxx_sdhci_get_max_clk,
+	.get_timeout_clock	= cns3xxx_sdhci_get_timeout_clk,
+	.set_clock		= cns3xxx_sdhci_set_clock,
+};
+
+static struct sdhci_pltfm_data cns3xxx_sdhci_pdata = {
+	.ops = &cns3xxx_sdhci_ops,
+	.quirks = SDHCI_QUIRK_BROKEN_DMA |
+		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
+		  SDHCI_QUIRK_INVERTED_WRITE_PROTECT |
+		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
+		  SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
+		  SDHCI_QUIRK_NONSTANDARD_CLOCK,
+	.init = cns3xxx_sdhci_init,
+};
+
+struct platform_device cns3xxx_sdhci_pdev = {
+	.name		= "sdhci",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(cns3xxx_sdhci_resources),
+	.resource	= cns3xxx_sdhci_resources,
+	.dev		= {
+		.platform_data	= &cns3xxx_sdhci_pdata,
+	},
+};
diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h
new file mode 100644
index 0000000..c5bf5cf
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.h
@@ -0,0 +1,19 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *		  Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *		  Anton Vorontsov <avorontsov at mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __CNS3XXX_DEVICES_H_
+#define __CNS3XXX_DEVICES_H_
+
+extern struct platform_device cns3xxx_sdhci_pdev;
+
+#endif /* __CNS3XXX_DEVICES_H_ */
-- 
1.7.0.5



From cbouatmailru at gmail.com  Tue Jun  1 12:55:40 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 1 Jun 2010 20:55:40 +0400
Subject: [PATCH 3/4] ARM: cns3xxx: Add support for AHCI controllers
In-Reply-To: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
References: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
Message-ID: <20100601165540.GC7123@oksana.dev.rtsoft.ru>

CNS3xxx chips have AHCI-compatible SATA controller. This patch adds
the support using generic ahci_platform driver.

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/mach-cns3xxx/cns3420vb.c |    1 +
 arch/arm/mach-cns3xxx/devices.c   |   61 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-cns3xxx/devices.h   |    1 +
 3 files changed, 63 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index df9ca5b..1e79ed5 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -112,6 +112,7 @@ static void __init cns3420_early_serial_setup(void)
  */
 static struct platform_device *cns3420_pdevs[] __initdata = {
 	&cns3420_nor_pdev,
+	&cns3xxx_ahci_pdev,
 	&cns3xxx_sdhci_pdev,
 };
 
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
index 549ad0c..bf6044b 100644
--- a/arch/arm/mach-cns3xxx/devices.c
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -14,14 +14,75 @@
 #include <linux/init.h>
 #include <linux/compiler.h>
 #include <linux/delay.h>
+#include <linux/dma-mapping.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
+#include <linux/ahci_platform.h>
 #include <linux/mmc/host.h>
 #include <linux/sdhci-pltfm.h>
 #include "../../../drivers/mmc/host/sdhci.h"
+#include "core.h"
 #include "devices.h"
 
 /*
+ * AHCI
+ */
+static int cns3xxx_ahci_init(struct device *dev)
+{
+	u32 tmp;
+
+	tmp = MISC_SATA_POWER_MODE;
+	tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
+	tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
+	MISC_SATA_POWER_MODE = tmp;
+
+	/* Enable SATA PHY */
+	cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
+	cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
+
+	/* Enable SATA Clock */
+	cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
+
+	/* De-Asscer SATA Reset */
+	tmp = PM_SOFT_RST_REG;
+	tmp |= 0x1 << PM_SOFT_RST_REG_OFFST_SATA;
+	PM_SOFT_RST_REG = tmp;
+
+	return 0;
+}
+
+static struct ahci_platform_data cns3xxx_ahci_pdata = {
+	.init = cns3xxx_ahci_init,
+};
+
+static struct resource cns3xxx_ahci_resource[] = {
+	[0] = {
+		.start	= CNS3XXX_SATA2_BASE,
+		.end	= CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_CNS3XXX_SATA,
+		.end	= IRQ_CNS3XXX_SATA,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device cns3xxx_ahci_pdev = {
+	.name		= "ahci",
+	.id		= 0,
+	.resource	= cns3xxx_ahci_resource,
+	.num_resources	= ARRAY_SIZE(cns3xxx_ahci_resource),
+	.dev		= {
+		.dma_mask		= &cns3xxx_ahci_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &cns3xxx_ahci_pdata,
+	},
+};
+
+/*
  * SDHCI
  */
 static struct resource cns3xxx_sdhci_resources[] = {
diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h
index c5bf5cf..3e6616d 100644
--- a/arch/arm/mach-cns3xxx/devices.h
+++ b/arch/arm/mach-cns3xxx/devices.h
@@ -14,6 +14,7 @@
 #ifndef __CNS3XXX_DEVICES_H_
 #define __CNS3XXX_DEVICES_H_
 
+extern struct platform_device cns3xxx_ahci_pdev;
 extern struct platform_device cns3xxx_sdhci_pdev;
 
 #endif /* __CNS3XXX_DEVICES_H_ */
-- 
1.7.0.5



From cbouatmailru at gmail.com  Tue Jun  1 12:55:56 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 1 Jun 2010 20:55:56 +0400
Subject: [PATCH 4/4] ARM: cns3xxx: Update defconfig to enable AHCI, PCIe
	and net devices
In-Reply-To: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
References: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
Message-ID: <20100601165556.GD7123@oksana.dev.rtsoft.ru>

This patch enables Platform AHCI SATA and PCIe support.

It now makes sense to enable networking and NFS support as we can
use PCIe NICs (SKY2 and E1000E were tested and enabled).

While at it, also disable oprofile, this isn't needed for default
configuration.

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/configs/cns3420vb_defconfig |  410 ++++++++++++++++++++++++++++++++--
 1 files changed, 393 insertions(+), 17 deletions(-)

diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig
index d5c0881..deb50f8 100644
--- a/arch/arm/configs/cns3420vb_defconfig
+++ b/arch/arm/configs/cns3420vb_defconfig
@@ -1,11 +1,12 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.34-rc6
-# Sun May  2 21:58:08 2010
+# Linux kernel version: 2.6.34
+# Fri May 28 13:27:20 2010
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_TIME=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_HAVE_PROC_CPU=y
 CONFIG_GENERIC_HARDIRQS=y
@@ -20,8 +21,6 @@ CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
 CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_OPROFILE_ARMV6=y
-CONFIG_OPROFILE_ARM11_CORE=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
 CONFIG_CONSTRUCTORS=y
@@ -35,6 +34,7 @@ CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 # CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
 CONFIG_HAVE_KERNEL_LZO=y
 CONFIG_KERNEL_GZIP=y
 # CONFIG_KERNEL_BZIP2 is not set
@@ -43,7 +43,10 @@ CONFIG_KERNEL_GZIP=y
 # CONFIG_SWAP is not set
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
 # CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
 
 #
 # RCU Subsystem
@@ -67,6 +70,7 @@ CONFIG_CGROUPS=y
 # CONFIG_CGROUP_CPUACCT is not set
 # CONFIG_RESOURCE_COUNTERS is not set
 # CONFIG_CGROUP_SCHED is not set
+# CONFIG_BLK_CGROUP is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 CONFIG_RELAY=y
@@ -75,6 +79,7 @@ CONFIG_NAMESPACES=y
 # CONFIG_IPC_NS is not set
 # CONFIG_USER_NS is not set
 # CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_INITRAMFS_SOURCE=""
 CONFIG_RD_GZIP=y
@@ -110,12 +115,13 @@ CONFIG_PERF_USE_VMALLOC=y
 # CONFIG_PERF_EVENTS is not set
 # CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
 CONFIG_COMPAT_BRK=y
 CONFIG_SLAB=y
 # CONFIG_SLUB is not set
 # CONFIG_SLOB is not set
 CONFIG_PROFILING=y
-CONFIG_OPROFILE=m
+# CONFIG_OPROFILE is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
@@ -147,8 +153,7 @@ CONFIG_LBDAF=y
 #
 CONFIG_IOSCHED_NOOP=y
 CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=m
-# CONFIG_CFQ_GROUP_IOSCHED is not set
+# CONFIG_IOSCHED_CFQ is not set
 CONFIG_DEFAULT_DEADLINE=y
 # CONFIG_DEFAULT_CFQ is not set
 # CONFIG_DEFAULT_NOOP is not set
@@ -192,6 +197,7 @@ CONFIG_MMU=y
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
 # CONFIG_ARCH_AT91 is not set
 # CONFIG_ARCH_BCMRING is not set
 # CONFIG_ARCH_CLPS711X is not set
@@ -231,7 +237,7 @@ CONFIG_ARCH_CNS3XXX=y
 # CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_S5P6440 is not set
 # CONFIG_ARCH_S5P6442 is not set
-# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PC100 is not set
 # CONFIG_ARCH_S5PV210 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
@@ -240,6 +246,7 @@ CONFIG_ARCH_CNS3XXX=y
 # CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
 
 #
 # CNS3XXX platform type
@@ -270,6 +277,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_DCACHE_DISABLE is not set
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
 CONFIG_CPU_HAS_PMU=y
 # CONFIG_ARM_ERRATA_411920 is not set
 CONFIG_ARM_GIC=y
@@ -277,8 +285,12 @@ CONFIG_ARM_GIC=y
 #
 # Bus support
 #
-# CONFIG_PCI_SYSCALL is not set
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
 # CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
 # CONFIG_PCCARD is not set
 
 #
@@ -322,6 +334,7 @@ CONFIG_ALIGNMENT_TRAP=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_CMDLINE="console=ttyS0,38400 mem=128M root=/dev/mmcblk0p1 ro rootwait"
+# CONFIG_CMDLINE_FORCE is not set
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
 
@@ -355,7 +368,96 @@ CONFIG_HAVE_AOUT=y
 #
 # CONFIG_PM is not set
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_NET is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+
+#
+# Some wireless drivers require a rate control algorithm
+#
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
 
 #
 # Device Drivers
@@ -372,6 +474,7 @@ CONFIG_FW_LOADER=y
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
 # CONFIG_MTD_TESTS is not set
@@ -393,6 +496,7 @@ CONFIG_MTD_BLOCK=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
 # CONFIG_MTD_OOPS is not set
 
 #
@@ -427,11 +531,13 @@ CONFIG_MTD_CFI_UTIL=y
 CONFIG_MTD_PHYSMAP=y
 # CONFIG_MTD_PHYSMAP_COMPAT is not set
 # CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
 # CONFIG_MTD_PLATRAM is not set
 
 #
 # Self-contained MTD device drivers
 #
+# CONFIG_MTD_PMC551 is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
@@ -457,6 +563,10 @@ CONFIG_MTD_PHYSMAP=y
 # CONFIG_MTD_UBI is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -464,11 +574,14 @@ CONFIG_BLK_DEV_LOOP=y
 #
 # DRBD disabled because PROC_FS, INET or CONNECTOR not selected
 #
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=20000
 # CONFIG_BLK_DEV_XIP is not set
 # CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
 # CONFIG_MISC_DEVICES is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
@@ -504,20 +617,160 @@ CONFIG_SCSI_WAIT_SCAN=m
 #
 # CONFIG_SCSI_SPI_ATTRS is not set
 # CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
 # CONFIG_SCSI_SAS_LIBSAS is not set
 # CONFIG_SCSI_SRP_ATTRS is not set
 CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
 # CONFIG_LIBFC is not set
 # CONFIG_LIBFCOE is not set
+# CONFIG_FCOE is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
 # CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_BFA_FC is not set
 # CONFIG_SCSI_DH is not set
 # CONFIG_SCSI_OSD_INITIATOR is not set
 CONFIG_ATA=y
 # CONFIG_ATA_NONSTANDARD is not set
 CONFIG_ATA_VERBOSE_ERROR=y
 # CONFIG_SATA_PMP is not set
+# CONFIG_SATA_AHCI is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+# CONFIG_SATA_SIL24 is not set
+# CONFIG_SATA_INIC162X is not set
 # CONFIG_ATA_SFF is not set
 # CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# The newer stack is recommended.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+CONFIG_E1000E=y
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+CONFIG_SKY2=y
+# CONFIG_SKY2_DEBUG is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+CONFIG_CHELSIO_T3_DEPENDS=y
+# CONFIG_CHELSIO_T3 is not set
+CONFIG_CHELSIO_T4_DEPENDS=y
+# CONFIG_CHELSIO_T4 is not set
+# CONFIG_ENIC is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_VXGE is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
+# CONFIG_MLX4_EN is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
+# CONFIG_QLCNIC is not set
+# CONFIG_QLGE is not set
+# CONFIG_SFC is not set
+# CONFIG_BE2NET is not set
+# CONFIG_TR is not set
+CONFIG_WLAN=y
+# CONFIG_ATMEL is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
 # CONFIG_PHONE is not set
 
 #
@@ -565,12 +818,15 @@ CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
 CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_NOZOMI is not set
 
 #
 # Serial drivers
 #
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
 CONFIG_SERIAL_8250_NR_UARTS=4
 CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 # CONFIG_SERIAL_8250_EXTENDED is not set
@@ -580,7 +836,10 @@ CONFIG_SERIAL_8250_RUNTIME_UARTS=4
 #
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
 # CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
@@ -588,8 +847,11 @@ CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_IPMI_HANDLER is not set
 # CONFIG_HW_RANDOM is not set
 # CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
 # CONFIG_I2C is not set
 # CONFIG_SPI is not set
 
@@ -616,12 +878,16 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_SM501 is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
+# CONFIG_LPC_SCH is not set
 # CONFIG_REGULATOR is not set
 # CONFIG_MEDIA_SUPPORT is not set
 
 #
 # Graphics support
 #
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_DRM is not set
 # CONFIG_VGASTATE is not set
 # CONFIG_VIDEO_OUTPUT_CONTROL is not set
 # CONFIG_FB is not set
@@ -640,6 +906,7 @@ CONFIG_DUMMY_CONSOLE=y
 # CONFIG_SOUND is not set
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
+# CONFIG_UWB is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
@@ -656,19 +923,20 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 # MMC/SD/SDIO Host Controller Drivers
 #
 CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PCI is not set
 CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
 # CONFIG_MEMSTICK is not set
 # CONFIG_NEW_LEDS is not set
 # CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
 CONFIG_RTC_LIB=y
 # CONFIG_RTC_CLASS is not set
 # CONFIG_DMADEVICES is not set
 # CONFIG_AUXDISPLAY is not set
 # CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
 # CONFIG_STAGING is not set
 
 #
@@ -687,6 +955,7 @@ CONFIG_FS_MBCACHE=y
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
 # CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
 # CONFIG_NILFS2_FS is not set
 CONFIG_FILE_LOCKING=y
@@ -753,6 +1022,26 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_FSCACHE is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
 
 #
 # Partition Types
@@ -760,6 +1049,7 @@ CONFIG_MISC_FILESYSTEMS=y
 # CONFIG_PARTITION_ADVANCED is not set
 CONFIG_MSDOS_PARTITION=y
 # CONFIG_NLS is not set
+# CONFIG_DLM is not set
 
 #
 # Kernel hacking
@@ -782,11 +1072,10 @@ CONFIG_FRAME_POINTER=y
 # CONFIG_LATENCYTOP is not set
 # CONFIG_SYSCTL_SYSCALL_CHECK is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_RING_BUFFER=y
-CONFIG_RING_BUFFER_ALLOW_SWAP=y
 CONFIG_TRACING_SUPPORT=y
 # CONFIG_FTRACE is not set
 # CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_ARM_UNWIND is not set
@@ -804,7 +1093,93 @@ CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_DEFAULT_SECURITY_TOMOYO is not set
 CONFIG_DEFAULT_SECURITY_DAC=y
 CONFIG_DEFAULT_SECURITY=""
-# CONFIG_CRYPTO is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
 # CONFIG_BINARY_PRINTF is not set
 
 #
@@ -828,4 +1203,5 @@ CONFIG_DECOMPRESS_LZO=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
 CONFIG_GENERIC_ATOMIC64=y
-- 
1.7.0.5


From linux at arm.linux.org.uk  Tue Jun  1 13:54:03 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 1 Jun 2010 18:54:03 +0100
Subject: incorrect panic("failed to get clock for system timer"); ??
In-Reply-To: <4C0539E4.9090501@gmail.com>
References: <4C0539E4.9090501@gmail.com>
Message-ID: <20100601175403.GA6644@n2100.arm.linux.org.uk>

On Tue, Jun 01, 2010 at 12:48:36PM -0400, f. achkar wrote:
> Hi,
> Newbie debugging Linux-2.6.32-9 on S3C2450, the kernel seems to panic at :
> s3c2410_timer_init () at arch/arm/plat-s3c/time.c:256
> 
> if (IS_ERR(timerclk))
>         panic("failed to get clock for system timer");
> 
> more precisely  'if (IS_ERR(timerclk))' is non-null !?! although the
> 'timerclk' seem to be fine:
> (gdb) print *timerclk
> $27 = {list = {next = 0xc04a933c, prev = 0xc04a93ac}, owner = 0x0,
> parent = 0xc04abfd4, name = 0xc042c5a1 "timers", id = -1,
>   usage = 0, rate = 0, ctrlbit = 1024, enable = 0xc009631c
> <s3c2443_clkcon_enable_p>, set_rate = 0, get_rate = 0,
>   round_rate = 0, set_parent = 0}
> (gdb) s
> 257            panic("failed to get clock for system timer");
> (gdb) print (unsigned long)(timerclk)
> $28 = 3226112884
> (gdb)
> 
> I'm not sure why 'IS_ERR(timerclk)' is holding true? or is it a bug ?
> thanks,

Looks to me like a compiler bug.  Your timerclk is 0xC04A9374, which
certainly isn't a value which IS_ERR() should return true for.


From broonie at opensource.wolfsonmicro.com  Tue Jun  1 14:05:28 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 1 Jun 2010 19:05:28 +0100
Subject: [alsa-devel] [PATCH v2 1/4] imx-ssi.c: add new choices to
	platform configuration
In-Reply-To: <1274950737-26498-1-git-send-email-eric@eukrea.com>
References: <1274950737-26498-1-git-send-email-eric@eukrea.com>
Message-ID: <20100601180527.GC10031@sirena.org.uk>

On Thu, May 27, 2010 at 10:58:54AM +0200, Eric B??nard wrote:
> * introduce 3 new flags to allow a more detailed configuration
> of the SSI link :
> 	IMX_SSI_NET : enable Network Mode
> 	IMX_SSI_SYN : enable Synchronous Mode
> 	IMX_SSI_USE_I2S_SLAVE : enable I2S Slave Mode
> * new platform can use these settings without breaking actual
> platforms.
> 
> Signed-off-by: Eric B??nard <eric at eukrea.com>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>

Sascha, any comments on the first couple of patches here?


From linux at arm.linux.org.uk  Tue Jun  1 14:09:44 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 1 Jun 2010 19:09:44 +0100
Subject: [PATCH 2/2] ARM: PL011 baudrate extension for ST-Ericssons
	derivative
In-Reply-To: <1275385698-1599-1-git-send-email-linus.walleij@stericsson.com>
References: <1275385698-1599-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20100601180944.GC6644@n2100.arm.linux.org.uk>

On Tue, Jun 01, 2010 at 11:48:18AM +0200, Linus Walleij wrote:
> @@ -90,6 +92,7 @@ static struct vendor_data vendor_arm = {
>  	.fifosize		= 16,
>  	.lcrh_tx                = UART011_LCRH,
>  	.lcrh_rx                = UART011_LCRH,
> +        .oversampling	        = false,

I assume these spaces rather than tabs are due to an editor error
rather than an email client problem?


From nico at fluxnic.net  Tue Jun  1 15:55:46 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 01 Jun 2010 15:55:46 -0400 (EDT)
Subject: [PATCH 3/3] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <1275404968-12258-3-git-send-email-saeed@marvell.com>
References: <1275404968-12258-1-git-send-email-saeed@marvell.com>
	<1275404968-12258-2-git-send-email-saeed@marvell.com>
	<1275404968-12258-3-git-send-email-saeed@marvell.com>
Message-ID: <alpine.LFD.2.00.1006011447410.24526@xanadu.home>

On Tue, 1 Jun 2010, Saeed Bishara wrote:

> This patch extens the kirkwood's PCIe support up to 2 controllers as in the 6282 devices.
> 
> Signed-off-by: Saeed Bishara <saeed at marvell.com>

Comments below.

[...]
> diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
> index 5e6f711..6e67f3c 100644
> --- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
> +++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
> @@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
>  static int __init mv88f6281gtw_ge_pci_init(void)
>  {
>  	if (machine_is_mv88f6281gtw_ge())
> -		kirkwood_pcie_init();
> +		kirkwood_pcie_init(0, 1);

This is going to initialize the non existing PCIe1 and disable PCIe0.  
You made the same mistake multiple times.

[...]
> diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
> index dee1eff..5c33324 100644
> --- a/arch/arm/mach-kirkwood/pcie.c
> +++ b/arch/arm/mach-kirkwood/pcie.c
> @@ -21,26 +21,40 @@
>  
>  #define PCIE_BASE	((void __iomem *)PCIE_VIRT_BASE)

Is this PCIE_BASE still used?

> +struct pcie_port {
> +	u8			index;
> +	u8			root_bus_nr;
> +	void __iomem		*base;
> +	spinlock_t		conf_lock;
> +	char			io_space_name[16];
> +	char			mem_space_name[16];
> +	struct resource		res[2];
> +};
> +
> +static struct pcie_port pcie_port[2];
> +static int num_pcie_ports;
> +static struct pcie_port *bus_to_port(int bus);

You should move the actual function here allowing you to get rid of that 
forward declaration.


>  void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
>  {
>  	*dev = orion_pcie_dev_id(PCIE_BASE);
>  	*rev = orion_pcie_rev(PCIE_BASE);
>  }
>  
> -static int pcie_valid_config(int bus, int dev)
> +static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
>  {
>  	/*
>  	 * Don't go out when trying to access --
>  	 * 1. nonexisting device on local bus
>  	 * 2. where there's no device connected (no link)
>  	 */
> -	if (bus == 0 && dev == 0)
> +	if (bus == pp->root_bus_nr && dev == 0)
>  		return 1;
>  
> -	if (!orion_pcie_link_up(PCIE_BASE))
> +	if (!orion_pcie_link_up(pp->base))
>  		return 0;
>  
> -	if (bus == 0 && dev != 1)
> +	if (bus == pp->root_bus_nr && dev != 1)
>  		return 0;
>  
>  	return 1;
> @@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev)
>   * and then reading the PCIE_CONF_DATA register. Need to make sure these
>   * transactions are atomic.
>   */
> -static DEFINE_SPINLOCK(kirkwood_pcie_lock);
>  
>  static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
>  			int size, u32 *val)
>  {
> +	struct pcie_port *pp = bus_to_port(bus->number);
>  	unsigned long flags;
>  	int ret;
>  
> -	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
> +	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
>  		*val = 0xffffffff;
>  		return PCIBIOS_DEVICE_NOT_FOUND;
>  	}
>  
> -	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
> -	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
> -	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
> +	spin_lock_irqsave(&pp->conf_lock, flags);
> +	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
> +	spin_unlock_irqrestore(&pp->conf_lock, flags);
>  
>  	return ret;
>  }
> @@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
>  static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
>  			int where, int size, u32 val)
>  {
> +	struct pcie_port *pp = bus_to_port(bus->number);
>  	unsigned long flags;
>  	int ret;
>  
> -	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
> +	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
>  		return PCIBIOS_DEVICE_NOT_FOUND;
>  
> -	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
> -	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
> -	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
> +	spin_lock_irqsave(&pp->conf_lock, flags);
> +	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
> +	spin_unlock_irqrestore(&pp->conf_lock, flags);
>  
>  	return ret;
>  }
> @@ -96,51 +111,84 @@ static struct pci_ops pcie_ops = {
>  
>  static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
>  {
> -	struct resource *res;
>  	extern unsigned int kirkwood_clk_ctrl;
> +	struct pcie_port *pp;
> +
> +	if (nr >= num_pcie_ports)
> +		return 0;
> +
> +	pp = &pcie_port[nr];
> +	pp->root_bus_nr = sys->busnr;
>  
>  	/*
>  	 * Generic PCIe unit setup.
>  	 */
> -	orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
> +	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
> +
> +	orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
>  
> -	/*
> -	 * Request resources.
> -	 */
> -	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
> -	if (!res)
> -		panic("pcie_setup unable to alloc resources");
>  
>  	/*
>  	 * IORESOURCE_IO
>  	 */
> -	res[0].name = "PCIe I/O Space";
> -	res[0].flags = IORESOURCE_IO;
> -	res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
> -	res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
> -	if (request_resource(&ioport_resource, &res[0]))
> +	snprintf(pp->io_space_name, sizeof(pp->io_space_name),
> +		 "PCIe %d I/O", pp->index);
> +	pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
> +	pp->res[0].name = pp->io_space_name;
> +	if (pp->index == 0) {
> +		pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
> +		pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
> +	} else {
> +		pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
> +		pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
> +	}
> +	pp->res[0].flags = IORESOURCE_IO;
> +	if (request_resource(&ioport_resource, &pp->res[0]))
>  		panic("Request PCIe IO resource failed\n");
> -	sys->resource[0] = &res[0];
> +	sys->resource[0] = &pp->res[0];
>  
>  	/*
>  	 * IORESOURCE_MEM
>  	 */
> -	res[1].name = "PCIe Memory Space";
> -	res[1].flags = IORESOURCE_MEM;
> -	res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
> -	res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
> -	if (request_resource(&iomem_resource, &res[1]))
> +	snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
> +		 "PCIe %d MEM", pp->index);
> +	pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
> +	pp->res[1].name = pp->mem_space_name;
> +	if (pp->index == 0) {
> +		pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
> +		pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
> +	} else {
> +		pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
> +		pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
> +	}
> +	pp->res[1].flags = IORESOURCE_MEM;
> +	if (request_resource(&iomem_resource, &pp->res[1]))
>  		panic("Request PCIe Memory resource failed\n");
> -	sys->resource[1] = &res[1];
> +	sys->resource[1] = &pp->res[1];
>  
>  	sys->resource[2] = NULL;
>  	sys->io_offset = 0;
>  
> -	kirkwood_clk_ctrl |= CGC_PEX0;
> -
> +	if (nr == 0)
> +		kirkwood_clk_ctrl |= CGC_PEX0;
> +	else
> +		kirkwood_clk_ctrl |= CGC_PEX1;
>  	return 1;
>  }
>  
> +static struct pcie_port *bus_to_port(int bus)
> +{
> +	int i;
> +
> +	for (i = num_pcie_ports - 1; i >= 0; i--) {
> +		int rbus = pcie_port[i].root_bus_nr;
> +		if (rbus != -1 && rbus <= bus)
> +			break;
> +	}
> +
> +	return i >= 0 ? pcie_port + i : NULL;
> +}

I think this looks like a bit too much code for what this does.  To 
simplify things, you could:

1) Duplicate kirkwood_pcie_setup() into kirkwood_pcie0_setup() and 
   kirkwood_pcie1_setup() instead.  This will remove a couple
   "if (pp->index == 0)" and the snprintf() which could remain 
   purely static initializations.

2) Remove bus_to_port() entirely, and store the address of the appropriate 
   struct pcie_port instance into the sysdata pointer of the pci_bus 
   structure.  This struct pcie_port could even be kmalloc'd as needed.

>  static void __devinit rc_pci_fixup(struct pci_dev *dev)
>  {
>  	/*
> @@ -163,7 +211,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
>  {
>  	struct pci_bus *bus;
>  
> -	if (nr == 0) {
> +	if (nr < num_pcie_ports) {
>  		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
>  	} else {
>  		bus = NULL;
> @@ -175,18 +223,45 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
>  
>  static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
>  {
> -	return IRQ_KIRKWOOD_PCIE;
> +	struct pcie_port *pp = bus_to_port(dev->bus->number);
> +
> +	return pp->index ? IRQ_KIRKWOOD_PCIE1 : IRQ_KIRKWOOD_PCIE;

Maybe having pp->irq and returning that directly would be better.

>  static struct hw_pci kirkwood_pci __initdata = {
> -	.nr_controllers	= 1,
> +	.nr_controllers	= 2,

I think this should be initialized at run time to 2 only when running on 
a 6282.

>  	.swizzle	= pci_std_swizzle,
>  	.setup		= kirkwood_pcie_setup,
>  	.scan		= kirkwood_pcie_scan_bus,
>  	.map_irq	= kirkwood_pcie_map_irq,
>  };
>  
> -void __init kirkwood_pcie_init(void)
> +static void __init add_pcie_port(int index, unsigned long base)
>  {
> +	printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
> +
> +	if (orion_pcie_link_up((void __iomem *)base)) {
> +		struct pcie_port *pp = &pcie_port[num_pcie_ports++];
> +
> +		printk(KERN_INFO "link up\n");
> +
> +		pp->index = index;
> +		pp->root_bus_nr = -1;
> +		pp->base = (void __iomem *)base;
> +		spin_lock_init(&pp->conf_lock);
> +		memset(pp->res, 0, sizeof(pp->res));
> +	} else {
> +		printk(KERN_INFO "link down, ignoring\n");
> +	}
> +}
> +
> +void __init kirkwood_pcie_init(int init_port0, int init_port1)

And instead of having (int init_port0, int init_port1), this should be 
(int port) which is much less error prone as demonstrated by your own 
kirkwood_pcie_init(0, 1) usage.  Those machines with both PCIe ports 
would simply have to call this twice.


Nicolas


From eric at eukrea.com  Tue Jun  1 15:57:44 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Tue,  1 Jun 2010 21:57:44 +0200
Subject: [PATCH v5] i.MX27: add suspend to RAM support
In-Reply-To: <20100527214642.GG25921@n2100.arm.linux.org.uk>
References: <20100527214642.GG25921@n2100.arm.linux.org.uk>
Message-ID: <1275422264-4040-1-git-send-email-eric@eukrea.com>

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
v5:
	remove const struct
v4:
	fixed include + const struct
v3:
	return -EINVAL instead of -1

 arch/arm/mach-mx2/Makefile   |    2 +-
 arch/arm/mach-mx2/pm-imx27.c |   46 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 47 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-mx2/pm-imx27.c

diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index e3254fa..27d496c 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -8,7 +8,7 @@ obj-y	:=  devices.o serial.o
 
 obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o
 
-obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
+obj-$(CONFIG_MACH_MX27) += cpu_imx27.o pm-imx27.o
 obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o
 
 obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
diff --git a/arch/arm/mach-mx2/pm-imx27.c b/arch/arm/mach-mx2/pm-imx27.c
new file mode 100644
index 0000000..afc17ce
--- /dev/null
+++ b/arch/arm/mach-mx2/pm-imx27.c
@@ -0,0 +1,46 @@
+/*
+ * i.MX27 Power Management Routines
+ *
+ * Based on Freescale's BSP
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License.
+ */
+
+#include <linux/kernel.h>
+#include <linux/suspend.h>
+#include <linux/io.h>
+#include <mach/system.h>
+#include <mach/mx27.h>
+
+static int mx27_suspend_enter(suspend_state_t state)
+{
+	u32 cscr;
+	switch (state) {
+	case PM_SUSPEND_MEM:
+		/* Clear MPEN and SPEN to disable MPLL/SPLL */
+		cscr = __raw_readl(MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
+		cscr &= 0xFFFFFFFC;
+		__raw_writel(cscr, MX27_IO_ADDRESS(MX27_CCM_BASE_ADDR));
+		/* Executes WFI */
+		arch_idle();
+		break;
+
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static struct platform_suspend_ops mx27_suspend_ops = {
+	.enter = mx27_suspend_enter,
+	.valid = suspend_valid_only_mem,
+};
+
+static int __init mx27_pm_init(void)
+{
+	suspend_set_ops(&mx27_suspend_ops);
+	return 0;
+}
+
+device_initcall(mx27_pm_init);
-- 
1.6.3.3



From linux at arm.linux.org.uk  Tue Jun  1 17:10:05 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 1 Jun 2010 22:10:05 +0100
Subject: [GIT PULL] Some Cavium CNS3xxx updates for 2.6.36
In-Reply-To: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
References: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
Message-ID: <20100601211005.GA9111@n2100.arm.linux.org.uk>

On Tue, Jun 01, 2010 at 08:54:09PM +0400, Anton Vorontsov wrote:
> Hello Russell,
> 
> As Linus' merge window is now officially closed, I believe
> we can start requesting pulls for -next?

Yup.

> For convenience I'm posting the patches again + defconfig update,
> and if everything looks reasonable, linux-cns3xxx's master branch
> is ready for you to pull.

Only concern I have is this:

+#include "../../../drivers/mmc/host/sdhci.h"

but short of moving the header file, I don't see any other way.  It
seems a little strange for the sdhci-pltfm.h file to call functions
which take a sdhci_host struct, but not provide a definition for it.

Will pull soon.


From cbouatmailru at gmail.com  Tue Jun  1 17:34:03 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Wed, 2 Jun 2010 01:34:03 +0400
Subject: [GIT PULL] Some Cavium CNS3xxx updates for 2.6.36
In-Reply-To: <20100601211005.GA9111@n2100.arm.linux.org.uk>
References: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
	<20100601211005.GA9111@n2100.arm.linux.org.uk>
Message-ID: <20100601213403.GA7861@oksana.dev.rtsoft.ru>

On Tue, Jun 01, 2010 at 10:10:05PM +0100, Russell King - ARM Linux wrote:
> On Tue, Jun 01, 2010 at 08:54:09PM +0400, Anton Vorontsov wrote:
> > Hello Russell,
> > 
> > As Linus' merge window is now officially closed, I believe
> > we can start requesting pulls for -next?
> 
> Yup.
> 
> > For convenience I'm posting the patches again + defconfig update,
> > and if everything looks reasonable, linux-cns3xxx's master branch
> > is ready for you to pull.
> 
> Only concern I have is this:
> 
> +#include "../../../drivers/mmc/host/sdhci.h"
> 
> but short of moving the header file, I don't see any other way.  It
> seems a little strange for the sdhci-pltfm.h file to call functions
> which take a sdhci_host struct, but not provide a definition for it.

Yeah, there's still some room for cleanups in sdhci land.
It's in my todo list, just didn't want the little cleanups
to interfere with feature additions.

And as sdhci patches normally go via -mm tree, which is based
on -next, there shouldn't be any problem with merging the
sdhci cleanup via -mm.

> Will pull soon.

Thanks!

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2


From fachkar.datawind at gmail.com  Tue Jun  1 17:54:56 2010
From: fachkar.datawind at gmail.com (f. achkar)
Date: Tue, 01 Jun 2010 17:54:56 -0400
Subject: clocks definition ?
Message-ID: <4C0581B0.4080509@gmail.com>

Hi,
Can anyone quickly point to where the variable 'clocks' should be/is
populated for S3C2450, 'clocks' is used in:
/* Clock API calls */
struct clk *clk_get(struct device *dev, const char *id)

thanks,
ferar


From gdavis at mvista.com  Tue Jun  1 17:59:24 2010
From: gdavis at mvista.com (gdavis at mvista.com)
Date: Tue,  1 Jun 2010 17:59:24 -0400
Subject: [RFC PATCH] gcov: Add ARM eABI support
Message-ID: <1275429564-9922-1-git-send-email-gdavis@mvista.com>

From: George G. Davis <gdavis at mvista.com>

Initially based on linux-2.6.30-gcov-arm-eabi.patch [1] and
linux-2.6.30-gcov-arm-hack.patch [2] with fixups to resolve
forward port conflicts.  Improved on [1] by making the
constructors section name a kernel config variable so the
correct section name is automatically selected based on the
build target.

[1] http://ltp.cvs.sourceforge.net/viewvc/*checkout*/ltp/utils/analysis/gcov-kernel/linux-2.6.30-gcov-arm-eabi.patch?revision=1.1
[2] http://ltp.cvs.sourceforge.net/viewvc/*checkout*/ltp/utils/analysis/gcov-kernel/linux-2.6.30-gcov-arm-hack.patch?revision=1.1

Signed-off-by: David Singleton <dsingleton at mvista.com>
Signed-off-by: George G. Davis <gdavis at mvista.com>
---
 arch/arm/boot/bootp/Makefile      |    2 ++
 arch/arm/boot/compressed/Makefile |    2 ++
 arch/arm/include/asm/elf.h        |    1 +
 arch/arm/kernel/module.c          |    1 +
 include/asm-generic/vmlinux.lds.h |    2 +-
 kernel/gcov/Kconfig               |    8 +++++++-
 kernel/module.c                   |    2 +-
 7 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile
index c394e30..5761f00 100644
--- a/arch/arm/boot/bootp/Makefile
+++ b/arch/arm/boot/bootp/Makefile
@@ -5,6 +5,8 @@
 # architecture-specific flags and dependencies.
 #
 
+GCOV_PROFILE	:= n
+
 LDFLAGS_bootp	:=-p --no-undefined -X \
 		 --defsym initrd_phys=$(INITRD_PHYS) \
 		 --defsym params_phys=$(PARAMS_PHYS) -T
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 53faa90..e1aee30 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -8,6 +8,8 @@ HEAD	= head.o
 OBJS	= misc.o decompress.o
 FONTC	= $(srctree)/drivers/video/console/font_acorn_8x8.c
 
+GCOV_PROFILE		:= n
+
 #
 # Architecture dependencies
 #
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 51662fe..6b19f46 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -52,6 +52,7 @@ typedef struct user_fp elf_fpregset_t;
 #define R_ARM_ABS32		2
 #define R_ARM_CALL		28
 #define R_ARM_JUMP24		29
+#define R_ARM_TARGET1		38
 #define R_ARM_V4BX		40
 #define R_ARM_PREL31		42
 #define R_ARM_MOVW_ABS_NC	43
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index c628bdf..2e04a98 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -129,6 +129,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 			break;
 
 		case R_ARM_ABS32:
+		case R_ARM_TARGET1:
 			*(u32 *)loc += sym->st_value;
 			break;
 
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index 48c5299..4dfce1a 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -442,7 +442,7 @@
 #ifdef CONFIG_CONSTRUCTORS
 #define KERNEL_CTORS()	. = ALIGN(8);			   \
 			VMLINUX_SYMBOL(__ctors_start) = .; \
-			*(.ctors)			   \
+			*(CONFIG_GCOV_CTORS)			   \
 			VMLINUX_SYMBOL(__ctors_end) = .;
 #else
 #define KERNEL_CTORS()
diff --git a/kernel/gcov/Kconfig b/kernel/gcov/Kconfig
index 70a298d..8564dc8 100644
--- a/kernel/gcov/Kconfig
+++ b/kernel/gcov/Kconfig
@@ -34,7 +34,7 @@ config GCOV_KERNEL
 config GCOV_PROFILE_ALL
 	bool "Profile entire Kernel"
 	depends on GCOV_KERNEL
-	depends on S390 || X86 || (PPC && EXPERIMENTAL) || MICROBLAZE
+	depends on S390 || X86 || (PPC && EXPERIMENTAL) || MICROBLAZE || ARM
 	default n
 	---help---
 	This options activates profiling for the entire kernel.
@@ -45,4 +45,10 @@ config GCOV_PROFILE_ALL
 	larger and run slower. Also be sure to exclude files from profiling
 	which are not linked to the kernel image to prevent linker errors.
 
+config GCOV_CTORS
+	string
+	depends on GCOV_KERNEL
+	default ".init_array" if ARM && AEABI
+	default ".ctors"
+
 endmenu
diff --git a/kernel/module.c b/kernel/module.c
index 0129769..b4eaed9 100644
--- a/kernel/module.c
+++ b/kernel/module.c
@@ -2296,7 +2296,7 @@ static noinline struct module *load_module(void __user *umod,
 					    "__kcrctab_unused_gpl");
 #endif
 #ifdef CONFIG_CONSTRUCTORS
-	mod->ctors = section_objs(hdr, sechdrs, secstrings, ".ctors",
+	mod->ctors = section_objs(hdr, sechdrs, secstrings, CONFIG_GCOV_CTORS,
 				  sizeof(*mod->ctors), &mod->num_ctors);
 #endif
 
-- 
1.6.3.3.328.ga9ee94



From akpm at linux-foundation.org  Tue Jun  1 18:26:52 2010
From: akpm at linux-foundation.org (Andrew Morton)
Date: Tue, 1 Jun 2010 15:26:52 -0700
Subject: [RFC PATCH] irq: handle private interrupt registration
In-Reply-To: <1274905794-7848-1-git-send-email-adharmap@codeaurora.org>
References: <1274905794-7848-1-git-send-email-adharmap@codeaurora.org>
Message-ID: <20100601152652.9296c5d0.akpm@linux-foundation.org>

On Wed, 26 May 2010 13:29:54 -0700
adharmap at codeaurora.org wrote:

> From: Abhijeet Dharmapurikar <adharmap at codeaurora.org>
> 
> The current code fails to register a handler for the same irq
> without taking in to account that it could be a per cpu interrupt.
> If the IRQF_PERCPU flag is set, enable the interrupt on that cpu
> and return success.
> 
> Change-Id: I748b3aa08d794342ad74cbd0bb900cc599f883a6
> Signed-off-by: Abhijeet Dharmapurikar <adharmap at codeaurora.org>
> ---
> 
> On systems with an interrupt controller that supports
> private interrupts per core, it is not possible to call 
> request_irq/setup_irq from multiple cores for the same irq. This is because
> the second+ invocation of __setup_irq checks if the previous
> hndler had a IRQ_SHARED flag set and errors out if not. 
> 
> The current irq handling code doesnt take in to account what cpu it 
> is executing on.  Usually the local interrupt controller registers are banked 
> per cpu a.k.a. a cpu can enable its local interrupt by writing to its banked 
> registers.
> 
> One way to get around this problem is to call the setup_irq on a single cpu 
> while other cpus simply enable their private interrupts by writing to their 
> banked registers
> 
> For eg. code in arch/arm/time/smp_twd.c
> 	/* Make sure our local interrupt controller has this enabled */
> 	local_irq_save(flags);
> 	get_irq_chip(clk->irq)->unmask(clk->irq);
> 	local_irq_restore(flags);
> 
> This looks like a hacky way to get local interrupts working on 
> multiple cores.
> 
> The patch adds a check for PERCPU flag in __setup_irq - if an handler is 
> present it simply enables that interrupt for that core and returns 0.
> 
> ...
>  
> --- a/kernel/irq/manage.c
> +++ b/kernel/irq/manage.c
> @@ -683,6 +683,37 @@ __setup_irq(unsigned int irq, struct irq_desc *desc, struct irqaction *new)
>  	old_ptr = &desc->action;
>  	old = *old_ptr;
>  	if (old) {
> +#if defined(CONFIG_IRQ_PER_CPU)
> +		/* All handlers must agree on per-cpuness */
> +		if ((old->flags & IRQF_PERCPU) !=
> +			(new->flags & IRQF_PERCPU))
> +			goto mismatch;
> +
> +		if (old->flags & IRQF_PERCPU) {
> +			/* the chip must have been set for this interrupt*/
> +			if (!(desc->status & IRQ_NOAUTOEN)) {
> +				desc->depth = 0;
> +				desc->status &= ~IRQ_DISABLED;
> +				desc->chip->startup(irq);
> +			} else
> +				/* Undo nested disables: */
> +				desc->depth = 1;
> +
> +			spin_unlock_irqrestore(&desc->lock, flags);

The rest of the code uses raw_spin_unlock_irqrestore().

I don't know _why_ is uses this.  There are no code comments, and the
239007b8440abff689632f50cdf0f2b9e895b534 changelog is:

: genirq: Convert irq_desc.lock to raw_spinlock
:    
: Convert locks which cannot be sleeping locks in preempt-rt to
: raw_spinlocks.

which is pathetically useless.

But I suppose we should ignorantly copy it and hope we're not screwing
something up.

> +			if (new->thread)
> +				wake_up_process(new->thread);
> +			return 0;
> +		}
> +#endif
> +
> +		/* they are the same types and same handler
> +		 * perhaps it is a private cpu interrupt
> +		 */
> +		if (old->flags == new->flags
> +			&& old->handler == new->handler)
> +			setup_affinity(irq, desc);
> +			return 0;

And this appears to have forgotten to undo the lock altogether, which
makes one wonder about the testing coverage.

It also embeds a `return' statement deep inside a huge and complex
function, which is invariably bad.

And in so doing it bypasses the register_irq_proc() and
register_handler_proc() calls.  I have no way of knowing whether that
was deliberate or whether it was a bug.  If it was deliberate then some
code and'/or changelog commentary is needed, so that others don't think
that it is a bug too.




From akpm at linux-foundation.org  Tue Jun  1 18:43:24 2010
From: akpm at linux-foundation.org (Andrew Morton)
Date: Tue, 1 Jun 2010 15:43:24 -0700
Subject: [PATCH] NUC900/rtc: change the waiting for device ready implement
In-Reply-To: <4BFE1853.5070105@gmail.com>
References: <4BFE1853.5070105@gmail.com>
Message-ID: <20100601154324.f1273812.akpm@linux-foundation.org>

On Thu, 27 May 2010 14:59:31 +0800
Wan ZongShun <mcuos.com at gmail.com> wrote:

> Dear Andrew,
> 
> This patch is only to change the waiting for device ready implement
> for winbond nuc900 platform.
> 

It's not very helpful to only say "I changed it".  _why_ did you change
it?  What change did you make?  What was wrong with the old code and
what's better about the new code?

> --- a/drivers/rtc/rtc-nuc900.c
> +++ b/drivers/rtc/rtc-nuc900.c
> @@ -85,22 +85,21 @@ static irqreturn_t nuc900_rtc_interrupt(int irq, void *_rtc)
> 
>  static int *check_rtc_access_enable(struct nuc900_rtc *nuc900_rtc)
>  {
> -	unsigned int i;
> +	unsigned int i, timeout = 0x1000;
>  	__raw_writel(INIRRESET, nuc900_rtc->rtc_reg + REG_RTC_INIR);
> 
>  	mdelay(10);
> 
>  	__raw_writel(AERPOWERON, nuc900_rtc->rtc_reg + REG_RTC_AER);
> 
> -	for (i = 0; i < 1000; i++) {
> -		if (__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB)
> -			return 0;
> -	}
> +	while (!(__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB)
> +								&& timeout--)
> +		mdelay(1);
> 
> -	if ((__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB) == 0x0)
> -		return ERR_PTR(-ENODEV);
> +	if (!timeout)
> +		return ERR_PTR(-EPERM);
> 
> -	return ERR_PTR(-EPERM);
> +	return 0;
> }

I can see that the patch makes two changes: it adds an mdelay(1) to the
polling loop and it changes the return value from ENODEV to EPERM if
the loop timed out.

But I don't have the faintest idea _why_ the changes were made!


So.  I merged the patch without a changelog.  Please send a changelog
for this patch which permits others to understand the change.



From bbb.lst at gmail.com  Tue Jun  1 18:53:54 2010
From: bbb.lst at gmail.com (Bjoern Brandenburg)
Date: Tue, 1 Jun 2010 18:53:54 -0400
Subject: 2.6.34 hangs during boot on PB11MPCore
In-Reply-To: <EAF47CD23C76F840A9E7FCE10091EFAB02C5844FB1@dbde02.ent.ti.com>
References: <AANLkTin9n6HDdiTnQoQ9mrmuzSR8JhZVq7uPgU86yqgU@mail.gmail.com>
	<20100530073652.GX2695@buzzloop.caiaq.de>
	<AANLkTimUF5iiGnc6RnN5C3sy-R6DAqHZNf6ZEu2o3W9P@mail.gmail.com>
	<AANLkTikdvjg52v-3AKUBukGO2FCp3fENGoYgpZZ2xVtT@mail.gmail.com>
	<AANLkTilMtEpt5hRfF_hszpU_AxZm7H93bkhqUacGWZc9@mail.gmail.com>
	<1275259589.22752.14.camel@e102109-lin.cambridge.arm.com>
	<AANLkTim4e5Sdj9tronOiI-sIMVGaUQdfRIhKHzZ4XfKp@mail.gmail.com>
	<AANLkTim3YdK3QDXC-20otTBPqYF_XX9rGHRX50cycqk6@mail.gmail.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C5844FB1@dbde02.ent.ti.com>
Message-ID: <AANLkTinEMbV1onbIZtNOvchP-CVsnVZsh_tKKkQUXmpJ@mail.gmail.com>

On Mon, May 31, 2010 at 2:26 AM, Shilimkar, Santosh
<santosh.shilimkar at ti.com> wrote:
>> -----Original Message-----
>> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-kernel-
>> bounces at lists.infradead.org] On Behalf Of Bjoern Brandenburg
>> Sent: Monday, May 31, 2010 6:46 AM
>> To: Catalin Marinas
>> Cc: bastoni at cs.unc.edu; Daniel Mack; linux-arm-kernel at lists.infradead.org; linus.ml.walleij at gmail.com
>> Subject: Re: 2.6.34 hangs during boot on PB11MPCore
>>
>> On Sun, May 30, 2010 at 9:04 PM, Bjoern Brandenburg <bbb.lst at gmail.com> wrote:
>> > On Sun, May 30, 2010 at 6:46 PM, Catalin Marinas
>> > <catalin.marinas at arm.com> wrote:
>> >> On Sun, 2010-05-30 at 22:38 +0100, Bjoern Brandenburg wrote:
>> >>> On Sun, May 30, 2010 at 5:05 PM, Bjoern Brandenburg <bbb.lst at gmail.com> wrote:
>> >>> > On Sun, May 30, 2010 at 3:27 PM, Bjoern Brandenburg <bbb.lst at gmail.com> wrote:
>> >>> >>
>> >>> >> I'll try to see if I can pinpoint what was dropped between 2.6.33-arm1
>> >>> >> and 2.6.34-arm.
>> >>> >
>> >>> > Progress: I can get 2.6.34-arm to boot with all 4 CPUs after
>> >>> > cherry-picking the following commits (which seemed relevant but
>> >>> > absent):
>> >>> >
>> >>> > 60060ca ARM: Handle instruction cache maintenance fault ?properly
>> >>> > 3f64e83 ARM errata: Eviction Buffer not empty after Cache Sync on L220
>> >>> > 3b009b5 ARM: change definition of cpu_relax() for ARM11MPCore
>> >>> >
>> >>> > Let's see which is the critical one...
>> >>>
>> >>> It's 3f64e83 "ARM errata: Eviction Buffer not empty after Cache Sync
>> >>> on L220" [1]. With this commit cherry-picked (on top of the 'rebased'
>> >>> branch in ARM's repository, i.e., 2.6.34-arm), the system boots to X11
>> >>> and runs some simple FS tests; the other ones don't make a difference.
>> >>>
>> >>> Are there plans for getting this and the other patches in the
>> >>> 'rebased' branch into mainline (for .35 or .36)?
>> >>
>> >> Thanks for the investigation. I recall I got something similar in the
>> >> past though I could no longer reproduce it with 2.6.34 (-arm) on the
>> >> PB11MPCore I have. Could you try reverting commit e7c5650f606 (ARM:
>> >> Change the mandatory barriers implementation) on a vanilla 2.6.34
>> >> kernel?
>> >
>> > That doesn't seem to help. v2.6.34 with e7c5650f606 reverted still hangs.
>>
>> Given that 2.6.34-arm contains patches for missing synchronization
>> primitives in the network driver, it is maybe not too surprising that
>> the vanilla kernel won't boot with an NFS root file system.
>>
>> I just tried 2.6.34-arm (i.e., the 'rebased' branch in the ARM repo)
>> with e7c5650f606 reverted (and without cherry-picking 3f64e83) ? and
>> that kernel boots ok!
>>
> We have similar observation on SPI based network driver. By playing with
> buffer alignment, the issue seems to be going away. Do you have link
> to " synchronization primitives in the network driver" ?patches ??

Hi  Santosh,

I was referring to the below patch. Without it, none of the tested
kernels could boot on our box.

- Bjoern

http://linux-arm.org/git?p=linux-2.6.git;a=commit;h=840cb637f8781516b9a4abc8f39508b30a63f1b0
commit 840cb637f8781516b9a4abc8f39508b30a63f1b0
Author: Catalin Marinas <catalin.marinas at arm.com>
Date:   Tue Jun 1 10:05:05 2010 +0100

    smsc911x: Add spinlocks around registers access

    On SMP systems, the SMSC911x registers may be accessed by multiple CPUs
    and this seems to put the chip in an inconsistent state. The patch adds
    spinlocks to the smsc911x_reg_read, smsc911x_reg_write,
    smsc911x_rx_readfifo and smsc911x_tx_writefifo functions.

    Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>


From bbb.lst at gmail.com  Tue Jun  1 18:57:24 2010
From: bbb.lst at gmail.com (Bjoern Brandenburg)
Date: Tue, 1 Jun 2010 18:57:24 -0400
Subject: 2.6.34 hangs during boot on PB11MPCore
In-Reply-To: <F01D8B85CFF58440B2A13965FBA90CA42DA38528B5@GEORGE.Emea.Arm.com>
References: <AANLkTin9n6HDdiTnQoQ9mrmuzSR8JhZVq7uPgU86yqgU@mail.gmail.com>
	<20100530073652.GX2695@buzzloop.caiaq.de>
	<AANLkTimUF5iiGnc6RnN5C3sy-R6DAqHZNf6ZEu2o3W9P@mail.gmail.com>
	<AANLkTikdvjg52v-3AKUBukGO2FCp3fENGoYgpZZ2xVtT@mail.gmail.com>
	<AANLkTilMtEpt5hRfF_hszpU_AxZm7H93bkhqUacGWZc9@mail.gmail.com>
	<1275259589.22752.14.camel@e102109-lin.cambridge.arm.com>
	<AANLkTim4e5Sdj9tronOiI-sIMVGaUQdfRIhKHzZ4XfKp@mail.gmail.com>
	<AANLkTim3YdK3QDXC-20otTBPqYF_XX9rGHRX50cycqk6@mail.gmail.com>
	<1275290414.2843.11.camel@e102109-lin.cambridge.arm.com>
	<F01D8B85CFF58440B2A13965FBA90CA42DA38528B5@GEORGE.Emea.Arm.com>
Message-ID: <AANLkTinvXEs9UKl1hEW8zf2t7JqylO4zhocRfEpak1ho@mail.gmail.com>

On Tue, Jun 1, 2010 at 3:46 AM, Colin Tuckley <Colin.Tuckley at arm.com> wrote:
>> -----Original Message-----
>> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-
>> kernel-bounces at lists.infradead.org] On Behalf Of Catalin Marinas
>
>> Regarding the SMSC 911x driver synchronisation - I've been asking SMSC
>> for more than a year to look into this.
>
> I'm still waiting for them to take up our offer of a PB11MPCore system for testing.
>
> One thing Bjoern hasn't mentioned... is the board firmware up to date? I.e. has the fpga image been updated to the latest release (from the latest CD).
>

Mhhh... Despite much looking through the arm.com site, I couldn't
figure out what the "latest CD" is. We got our box last September and
haven't installed any firmware updates since. Thus it's quite possible
that the firmware is out of date.
Is this the revision ID that you're looking for?

# cat /proc/cpuinfo
Processor	: ARMv6-compatible processor rev 0 (v6l)
processor	: 0
BogoMIPS	: 83.55

processor	: 1
BogoMIPS	: 83.55

processor	: 2
BogoMIPS	: 83.55

processor	: 3
BogoMIPS	: 83.55

Features	: swp half thumb fastmult vfp edsp java
CPU implementer	: 0x41
CPU architecture: 7
CPU variant	: 0x0
CPU part	: 0xb02
CPU revision	: 0

Hardware	: ARM-RealView PB11MPCore
Revision	: 2159f503
Serial		: 0000000000000000

- Bj?rn


From tglx at linutronix.de  Tue Jun  1 19:14:32 2010
From: tglx at linutronix.de (Thomas Gleixner)
Date: Wed, 2 Jun 2010 01:14:32 +0200 (CEST)
Subject: [RFC PATCH] irq: handle private interrupt registration
In-Reply-To: <20100601152652.9296c5d0.akpm@linux-foundation.org>
References: <1274905794-7848-1-git-send-email-adharmap@codeaurora.org>
	<20100601152652.9296c5d0.akpm@linux-foundation.org>
Message-ID: <alpine.LFD.2.00.1006020110090.2933@localhost.localdomain>

On Tue, 1 Jun 2010, Andrew Morton wrote:

> On Wed, 26 May 2010 13:29:54 -0700
> adharmap at codeaurora.org wrote:
> 
> > From: Abhijeet Dharmapurikar <adharmap at codeaurora.org>
> > 
> > The current code fails to register a handler for the same irq
> > without taking in to account that it could be a per cpu interrupt.
> > If the IRQF_PERCPU flag is set, enable the interrupt on that cpu
> > and return success.
> > 
> > Change-Id: I748b3aa08d794342ad74cbd0bb900cc599f883a6
> > Signed-off-by: Abhijeet Dharmapurikar <adharmap at codeaurora.org>
> > ---
> > 
> > On systems with an interrupt controller that supports
> > private interrupts per core, it is not possible to call 
> > request_irq/setup_irq from multiple cores for the same irq. This is because
> > the second+ invocation of __setup_irq checks if the previous
> > hndler had a IRQ_SHARED flag set and errors out if not. 
> > 
> > The current irq handling code doesnt take in to account what cpu it 
> > is executing on.  Usually the local interrupt controller registers are banked 
> > per cpu a.k.a. a cpu can enable its local interrupt by writing to its banked 
> > registers.
> > 
> > One way to get around this problem is to call the setup_irq on a single cpu 
> > while other cpus simply enable their private interrupts by writing to their 
> > banked registers
> > 
> > For eg. code in arch/arm/time/smp_twd.c
> > 	/* Make sure our local interrupt controller has this enabled */
> > 	local_irq_save(flags);
> > 	get_irq_chip(clk->irq)->unmask(clk->irq);
> > 	local_irq_restore(flags);
> > 
> > This looks like a hacky way to get local interrupts working on 
> > multiple cores.

Yes, it is. But it's saner than your aproach to trick the setup_irq()
to handle that case.

There are two sane solutions: 
      
1) Use PER_CPU offsets for the irq numbers. The generic irq code does
   not care whether the interrupt number is matching any physical
   numbering scheme in the hardware, as long as the arch specific chip
   implementation knows how to deal with it, which is not rocket
   science to do.

2) Let the boot CPU setup the interrupt and provide a generic
   enable_per_cpu_irq() / disable_per_cpu_irq() interface, which has
   sanity checking in place. That has a couple of interesting
   implications as well, but they can be dealt with.

Thanks,

	tglx


From ryan at bluewatersys.com  Tue Jun  1 20:55:36 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Wed, 02 Jun 2010 12:55:36 +1200
Subject: [PATCH] at91: Fix uhpck clock rate in upll case
Message-ID: <4C05AC08.9030705@bluewatersys.com>

The uhpck clock should be divided from the utmi clock, not its parent
(main). This change is mostly cosmetic as the uhpck rate value is not
used anywhere except for the debugfs clock output.

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---

diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 7f7da43..57fc6d4 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -657,7 +657,7 @@ static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
 	/* Now set uhpck values */
 	uhpck.parent = &utmi_clk;
 	uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
-	uhpck.rate_hz = utmi_clk.parent->rate_hz;
+	uhpck.rate_hz = utmi_clk.rate_hz;
 	uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 }
 



From kgene.kim at samsung.com  Tue Jun  1 22:31:31 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 02 Jun 2010 11:31:31 +0900
Subject: [PATCH 1/4] ARM: S3C64XX: Add support for Compact Flash driver	on
	SMDK6410
In-Reply-To: <20100527085233.GJ4720@trinity.fluff.org>
References: <1274948524-2970-1-git-send-email-kgene.kim@samsung.com>
	<1274948524-2970-2-git-send-email-kgene.kim@samsung.com>
	<20100527085233.GJ4720@trinity.fluff.org>
Message-ID: <002601cb01fb$b928f7c0$2b7ae740$%kim@samsung.com>

Ben Dooks wrote:
> 
> On Thu, May 27, 2010 at 05:22:01PM +0900, Kukjin Kim wrote:
> > From: Abhilash Kesavan <a.kesavan at samsung.com>
> >
> > Following is added for the CF-ATA driver:
> > 	- Platform data strucure definition and instantiation
> > 	- Platform device definition and enabling code
> > 	- Platform-specific gpio setup code
> > 	- CF controller register definitions
> >
> > Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> > Signed-off-by: Thomas Abraham <thomas.ab at samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> > ---
> >  arch/arm/mach-s3c64xx/Kconfig                   |    7 +++
> >  arch/arm/mach-s3c64xx/Makefile                  |    1 +
> >  arch/arm/mach-s3c64xx/clock.c                   |    6 +++
> >  arch/arm/mach-s3c64xx/include/mach/map.h        |    5 ++-
> >  arch/arm/mach-s3c64xx/include/mach/regs-clock.h |    5 ++
> >  arch/arm/mach-s3c64xx/mach-smdk6410.c           |    9 ++++
> >  arch/arm/mach-s3c64xx/s3c6410.c                 |    1 +
> >  arch/arm/mach-s3c64xx/setup-ide.c               |   55
> ++++++++++++++++++++++
> >  arch/arm/plat-samsung/Kconfig                   |    5 ++
> >  arch/arm/plat-samsung/Makefile                  |    1 +
> >  arch/arm/plat-samsung/dev-ide.c                 |   52
> +++++++++++++++++++++
> >  arch/arm/plat-samsung/include/plat/ata.h        |   38 +++++++++++++++
> >  arch/arm/plat-samsung/include/plat/devs.h       |    1 +
> >  arch/arm/plat-samsung/include/plat/regs-ata.h   |   56
> +++++++++++++++++++++++
> 
> it would have been useful to keep the plat-samsung changes
> seperate.
> 
Ok..will separate the plat-samsung and machine code into different patches.

> >  14 files changed, 241 insertions(+), 1 deletions(-)
> >  create mode 100644 arch/arm/mach-s3c64xx/setup-ide.c
> >  create mode 100644 arch/arm/plat-samsung/dev-ide.c
> >  create mode 100644 arch/arm/plat-samsung/include/plat/ata.h
> >  create mode 100644 arch/arm/plat-samsung/include/plat/regs-ata.h
> >
> > diff --git a/arch/arm/mach-s3c64xx/Kconfig
b/arch/arm/mach-s3c64xx/Kconfig
> > index f5a5972..c00401e 100644
> > --- a/arch/arm/mach-s3c64xx/Kconfig
> > +++ b/arch/arm/mach-s3c64xx/Kconfig
> > @@ -67,6 +67,11 @@ config S3C64XX_SETUP_SDHCI_GPIO
> >  	help
> >  	  Common setup code for S3C64XX SDHCI GPIO configurations
> >
> > +config S3C64XX_SETUP_IDE
> > +	bool
> > +	help
> > +	  Common setup code for S3C64XX IDE.
> > +
> >  # S36400 Macchine support
> >
> >  config MACH_SMDK6400
> > @@ -101,9 +106,11 @@ config MACH_SMDK6410
> >  	select S3C_DEV_USB_HSOTG
> >  	select S3C_DEV_WDT
> >  	select HAVE_S3C2410_WATCHDOG
> > +	select S3C_DEV_IDE
> >  	select S3C64XX_SETUP_SDHCI
> >  	select S3C64XX_SETUP_I2C1
> >  	select S3C64XX_SETUP_FB_24BPP
> > +	select S3C64XX_SETUP_IDE
> >  	help
> >  	  Machine support for the Samsung SMDK6410
> >
> > diff --git a/arch/arm/mach-s3c64xx/Makefile
b/arch/arm/mach-s3c64xx/Makefile
> > index 9d10069..0d52c35 100644
> > --- a/arch/arm/mach-s3c64xx/Makefile
> > +++ b/arch/arm/mach-s3c64xx/Makefile
> > @@ -38,6 +38,7 @@ obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
> >  obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
> >  obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
> >  obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
> > +obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
> >
> >  # PM
> >
> > diff --git a/arch/arm/mach-s3c64xx/clock.c
b/arch/arm/mach-s3c64xx/clock.c
> > index 7a4138b..9dac5c4 100644
> > --- a/arch/arm/mach-s3c64xx/clock.c
> > +++ b/arch/arm/mach-s3c64xx/clock.c
> > @@ -304,6 +304,12 @@ static struct clk init_clocks[] = {
> >  		.id		= -1,
> >  		.parent		= &clk_p,
> >  		.ctrlbit	= S3C_CLKCON_PCLK_AC97,
> > +	}, {
> > +		.name		= "cfcon",
> > +		.id		= -1,
> > +		.parent		= &clk_h,
> > +		.enable		= s3c64xx_hclk_ctrl,
> > +		.ctrlbit	= S3C_CLKCON_HCLK_IHOST,
> >  	}
> >  };
> >
> > diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-
> s3c64xx/include/mach/map.h
> > index e1eab3c..4b1ac79 100644
> > --- a/arch/arm/mach-s3c64xx/include/mach/map.h
> > +++ b/arch/arm/mach-s3c64xx/include/mach/map.h
> > @@ -86,6 +86,9 @@
> >  #define S3C64XX_SZ_GPIO		SZ_4K
> >
> >  #define S3C64XX_PA_SDRAM	(0x50000000)
> > +
> > +#define S3C64XX_PA_CFCON	(0x70300000)
> > +
> >  #define S3C64XX_PA_VIC0		(0x71200000)
> >  #define S3C64XX_PA_VIC1		(0x71300000)
> >
> > @@ -118,7 +121,7 @@
> >  #define S3C_VA_USB_HSPHY	S3C64XX_VA_USB_HSPHY
> >  #define S3C_PA_RTC		S3C64XX_PA_RTC
> >  #define S3C_PA_WDT		S3C64XX_PA_WATCHDOG
> > -
> > +#define SAMSUNG_PA_CFCON	S3C64XX_PA_CFCON
> >  #define SAMSUNG_PA_ADC		S3C64XX_PA_ADC
> >
> >  #endif /* __ASM_ARCH_6400_MAP_H */
> > diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
b/arch/arm/mach-
> s3c64xx/include/mach/regs-clock.h
> > index 0114eb0..05332b9 100644
> > --- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
> > +++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
> > @@ -34,6 +34,7 @@
> >  #define S3C_SCLK_GATE		S3C_CLKREG(0x38)
> >  #define S3C_MEM0_GATE		S3C_CLKREG(0x3C)
> >  #define S3C6410_CLK_SRC2	S3C_CLKREG(0x10C)
> > +#define S3C_MEM_SYS_CFG		S3C_CLKREG(0x120)
> >
> >  /* CLKDIV0 */
> >  #define S3C6400_CLKDIV0_PCLK_MASK	(0xf << 12)
> > @@ -154,4 +155,8 @@
> >  #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT	(2)
> >  #define S3C6400_CLKSRC_MFC		(1 << 4)
> >
> > +/* MEM_SYS_CFG */
> > +#define MEM_SYS_CFG_INDEP_CF		0x4000
> > +#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON	0x30
> > +
> >  #endif /* _PLAT_REGS_CLOCK_H */
> > diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-
> s3c64xx/mach-smdk6410.c
> > index d9a0355..cc1bb0f 100644
> > --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
> > +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
> > @@ -56,6 +56,7 @@
> >  #include <mach/regs-gpio.h>
> >  #include <mach/regs-sys.h>
> >  #include <mach/regs-srom.h>
> > +#include <plat/ata.h>
> >  #include <plat/iic.h>
> >  #include <plat/fb.h>
> >  #include <plat/gpio-cfg.h>
> > @@ -242,6 +243,11 @@ static struct platform_device smdk6410_b_pwr_5v = {
> >  };
> >  #endif
> >
> > +static struct s3c_ide_platdata smdk6410_ide_pdata __initdata = {
> > +	.setup_gpio	= s3c_ide_setup_gpio,
> > +	.cfg_mode	= s3c_ide_cfg_mode,
> 
> 
> These should have been called s3c64xx_ide...
> 
> I'll have a think about what we should be doing with this, it might
> be wroth passing this via the archdata and leaving the platform data
> for the board. If these configs are generally going to be per SoC
> then i'd prefer to see this in the archdata and once per SoC.
> 
Will change it to per SoC.

> > +};
> > +
> >  static struct map_desc smdk6410_iodesc[] = {};
> >
> >  static struct platform_device *smdk6410_devices[] __initdata = {
> > @@ -267,6 +273,7 @@ static struct platform_device *smdk6410_devices[]
> __initdata = {
> >  	&s3c_device_adc,
> >  	&s3c_device_ts,
> >  	&s3c_device_wdt,
> > +	&s3c_device_cfcon,
> >  };
> >
> >  #ifdef CONFIG_REGULATOR
> > @@ -665,6 +672,8 @@ static void __init smdk6410_machine_init(void)
> >  	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
> >  	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
> >
> > +	s3c_ide_set_platdata(&smdk6410_ide_pdata);
> > +
> >  	platform_add_devices(smdk6410_devices,
> ARRAY_SIZE(smdk6410_devices));
> >  }
> >
> > diff --git a/arch/arm/mach-s3c64xx/s3c6410.c
b/arch/arm/mach-s3c64xx/s3c6410.c
> > index 014401c..1d1dce4 100644
> > --- a/arch/arm/mach-s3c64xx/s3c6410.c
> > +++ b/arch/arm/mach-s3c64xx/s3c6410.c
> > @@ -58,6 +58,7 @@ void __init s3c6410_map_io(void)
> >  	s3c_device_nand.name = "s3c6400-nand";
> >  	s3c_onenand_setname("s3c6410-onenand");
> >  	s3c64xx_onenand1_setname("s3c6410-onenand");
> > +	s3c_device_cfcon.name = "s3c6400-pata";
> >  }
> 
> let's get this sorted out and use one method. see Kyungmin Park's prev.
> comments on the subject.
> 
Will create a new file ata-core.h on the lines of iic-core.h/onenand-core.h

> >  void __init s3c6410_init_clocks(int xtal)
> > diff --git a/arch/arm/mach-s3c64xx/setup-ide.c
b/arch/arm/mach-s3c64xx/setup-
> ide.c
> > new file mode 100644
> > index 0000000..0bf4e5e
> > --- /dev/null
> > +++ b/arch/arm/mach-s3c64xx/setup-ide.c
> > @@ -0,0 +1,55 @@
> > +/* linux/arch/arm/mach-s3c64xx/setup-ide.c
> > + *
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com/
> > + *
> > + * S3C64XX setup information for IDE
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > +*/
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/types.h>
> > +#include <linux/io.h>
> > +
> > +#include <mach/map.h>
> > +#include <mach/gpio.h>
> > +#include <mach/regs-clock.h>
> > +#include <plat/gpio-cfg.h>
> > +#include <plat/regs-ata.h>
> > +
> > +void s3c_ide_setup_gpio(void)
> > +{
> > +	u32 reg;
> > +	u32 gpio = 0;
> > +
> > +	reg = __raw_readl(S3C_MEM_SYS_CFG) & (~0x3f);
> > +
> > +	/* Independent CF interface, CF chip select configuration */
> > +	__raw_writel(reg | MEM_SYS_CFG_INDEP_CF |
> > +		MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
> > +
> > +	s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
> > +
> > +	/* Set XhiDATA[15:0] pins as CF Data[15:0] */
> > +	for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++)
> > +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5));
> > +
> > +	/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
> > +	for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++)
> > +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
> > +
> > +	/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
> > +	s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
> > +	for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++)
> > +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
> 
> i'll update this to the cfgrange when merging the cfgrange code.
> 
OK

> > +}
> > +
> > +void s3c_ide_cfg_mode(void __iomem *sfrbase)
> > +{
> > +	/* Select true-ide as the internal operating mode*/
> > +	writel(readl(sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
> > +						sfrbase + S3C_CFATA_MUX);
> > +}
> 
> maybe we just put this in the driver and select on type.
> 
Will move it to the driver file.

> > diff --git a/arch/arm/plat-samsung/Kconfig
b/arch/arm/plat-samsung/Kconfig
> > index 2753fb3..6ec97fe 100644
> > --- a/arch/arm/plat-samsung/Kconfig
> > +++ b/arch/arm/plat-samsung/Kconfig
> > @@ -175,6 +175,11 @@ config S3C_DEV_I2C2
> >  	help
> >  	  Compile in platform device definitions for I2C channel 2
> >
> > +config S3C_DEV_IDE
> > +	bool
> > +	help
> > +	  Compile in platform device definitions for IDE
> > +
> >  config S3C_DEV_FB
> >  	bool
> >  	help
> > diff --git a/arch/arm/plat-samsung/Makefile
b/arch/arm/plat-samsung/Makefile
> > index b1d82cc..252fc76 100644
> > --- a/arch/arm/plat-samsung/Makefile
> > +++ b/arch/arm/plat-samsung/Makefile
> > @@ -48,6 +48,7 @@ obj-$(CONFIG_S3C_DEV_RTC)	+= dev-rtc.o
> >
> >  obj-$(CONFIG_SAMSUNG_DEV_ADC)	+= dev-adc.o
> >  obj-$(CONFIG_SAMSUNG_DEV_TS)	+= dev-ts.o
> > +obj-$(CONFIG_S3C_DEV_IDE)	+= dev-ide.o
> >
> >  # DMA support
> >
> > diff --git a/arch/arm/plat-samsung/dev-ide.c
b/arch/arm/plat-samsung/dev-ide.c
> > new file mode 100644
> > index 0000000..c6b3292
> > --- /dev/null
> > +++ b/arch/arm/plat-samsung/dev-ide.c
> > @@ -0,0 +1,52 @@
> > +/* linux/arch/arm/plat-samsung/dev-ide.c
> > + *
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com
> > + *
> > + * S3C CF-ATA device definition.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > +*/
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/types.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/io.h>
> > +#include <mach/map.h>
> > +#include <plat/ata.h>
> 
> do we need linux/io.h in here?
> 
No..will remove it.

> soem spacing inebtwee nthe include groups would be nice too,.
> 
OK

> > +static struct resource s3c_cfcon_resource[] = {
> > +	[0] = {
> > +		.start	= SAMSUNG_PA_CFCON,
> > +		.end	= SAMSUNG_PA_CFCON + SZ_1M - 1,
> > +		.flags	= IORESOURCE_MEM,
> 
> do we really need to map SZ_1M?

Will change it to SZ_16K.

> > +	},
> > +	[1] = {
> > +		.start	= IRQ_CFCON,
> > +		.end	= IRQ_CFCON,
> > +		.flags	= IORESOURCE_IRQ,
> > +	},
> > +};
> > +
> > +struct platform_device s3c_device_cfcon = {
> > +	.name		= "s3c-pata",
> 
> if the name is going to change, let's simply not bother
> setting one here.
> 
Will remove the name.

> > +	.id		= 0,
> > +	.num_resources	= ARRAY_SIZE(s3c_cfcon_resource),
> > +	.resource	= s3c_cfcon_resource,
> > +};
> 
> > +void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
> > +{
> > +	struct s3c_ide_platdata *pd;
> > +
> > +	pd = (struct s3c_ide_platdata *)kmemdup(pdata,
>   	      ^^^^^ not needed.

Will remove it.

> > +		sizeof(struct s3c_ide_platdata), GFP_KERNEL);
> > +	if (!pd) {
> > +		printk(KERN_ERR "%s: no memory for platform data\n",
> __func__);
> > +		return;
> > +	}
> > +	s3c_device_cfcon.dev.platform_data = pd;
> > +}
> > diff --git a/arch/arm/plat-samsung/include/plat/ata.h b/arch/arm/plat-
> samsung/include/plat/ata.h
> > new file mode 100644
> > index 0000000..aea11dc
> > --- /dev/null
> > +++ b/arch/arm/plat-samsung/include/plat/ata.h
> > @@ -0,0 +1,38 @@
> > +/* arch/arm/plat-samsung/include/plat/ata.h
> > + *
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com
> > + *
> > + * S3C - CF Controller platform_device info
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > +*/
> > +
> > +#ifndef __ASM_PLAT_ATA_H
> > +#define __ASM_PLAT_ATA_H __FILE__
> > +
> > +/**
> > + * struct s3c_ide_platdata - S3C IDE driver platform data.
> > + * @setup_gpio: Setup the external GPIO pins to the right state for data
> > + * transfer in true-ide mode.
> > + * @cfg_mode: Platform specific setup for configuring the CF controller
> > + * in true-ide mode.
> > + */
> > +struct s3c_ide_platdata {
> > +	void (*setup_gpio)(void);
> > +	void (*cfg_mode)(void __iomem *sfrbase);
> > +};
> > +
> > +/*
> > + * s3c_ide_set_platdata() - Setup the platform specifc data for IDE
driver.
> > + * @pdata: Platform data for IDE driver.
> > + */
> > +extern void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata);
> > +
> > +/* architecture-specific IDE configuration */
> > +extern void s3c_ide_setup_gpio(void);
> > +extern void s3c_ide_cfg_mode(void __iomem *sfrbase);
> > +
> > +#endif /*__ASM_PLAT_ATA_H */
> > diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-
> samsung/include/plat/devs.h
> > index e6144e4..e3fcddb 100644
> > --- a/arch/arm/plat-samsung/include/plat/devs.h
> > +++ b/arch/arm/plat-samsung/include/plat/devs.h
> > @@ -75,6 +75,7 @@ extern struct platform_device s5pc110_device_onenand;
> >
> >  extern struct platform_device s3c_device_usbgadget;
> >  extern struct platform_device s3c_device_usb_hsotg;
> > +extern struct platform_device s3c_device_cfcon;
> >
> >  extern struct platform_device s5pv210_device_ac97;
> >  extern struct platform_device s5pv210_device_pcm0;
> > diff --git a/arch/arm/plat-samsung/include/plat/regs-ata.h
b/arch/arm/plat-
> samsung/include/plat/regs-ata.h
> > new file mode 100644
> > index 0000000..f73b267
> > --- /dev/null
> > +++ b/arch/arm/plat-samsung/include/plat/regs-ata.h
> > @@ -0,0 +1,56 @@
> > +/* arch/arm/plat-samsung/include/plat/regs-ata.h
> > + *
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com
> > + *
> > + * S3C CF-ATA register definitions
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > +*/
> > +
> > +#ifndef __ASM_PLAT_REGS_ATA_H
> > +#define __ASM_PLAT_REGS_ATA_H __FILE__
> > +
> > +#define S3C_CFATA_REG(x)	(x)
> > +
> > +#define S3C_CFATA_MUX		S3C_CFATA_REG(0x0)
> > +
> > +#define S3C_ATA_CTRL		S3C_CFATA_REG(0x0)
> > +#define S3C_ATA_STATUS		S3C_CFATA_REG(0x4)
> > +#define S3C_ATA_CMD		S3C_CFATA_REG(0x8)
> > +#define S3C_ATA_SWRST		S3C_CFATA_REG(0xc)
> > +#define S3C_ATA_IRQ		S3C_CFATA_REG(0x10)
> > +#define S3C_ATA_IRQ_MSK		S3C_CFATA_REG(0x14)
> > +#define S3C_ATA_CFG		S3C_CFATA_REG(0x18)
> > +
> > +#define S3C_ATA_MDMA_TIME	S3C_CFATA_REG(0x28)
> > +#define S3C_ATA_PIO_TIME	S3C_CFATA_REG(0x2c)
> > +#define S3C_ATA_UDMA_TIME	S3C_CFATA_REG(0x30)
> > +#define S3C_ATA_XFR_NUM		S3C_CFATA_REG(0x34)
> > +#define S3C_ATA_XFR_CNT		S3C_CFATA_REG(0x38)
> > +#define S3C_ATA_TBUF_START	S3C_CFATA_REG(0x3c)
> > +#define S3C_ATA_TBUF_SIZE	S3C_CFATA_REG(0x40)
> > +#define S3C_ATA_SBUF_START	S3C_CFATA_REG(0x44)
> > +#define S3C_ATA_SBUF_SIZE	S3C_CFATA_REG(0x48)
> > +#define S3C_ATA_CADR_TBUF	S3C_CFATA_REG(0x4c)
> > +#define S3C_ATA_CADR_SBUF	S3C_CFATA_REG(0x50)
> > +#define S3C_ATA_PIO_DTR		S3C_CFATA_REG(0x54)
> > +#define S3C_ATA_PIO_FED		S3C_CFATA_REG(0x58)
> > +#define S3C_ATA_PIO_SCR		S3C_CFATA_REG(0x5c)
> > +#define S3C_ATA_PIO_LLR		S3C_CFATA_REG(0x60)
> > +#define S3C_ATA_PIO_LMR		S3C_CFATA_REG(0x64)
> > +#define S3C_ATA_PIO_LHR		S3C_CFATA_REG(0x68)
> > +#define S3C_ATA_PIO_DVR		S3C_CFATA_REG(0x6c)
> > +#define S3C_ATA_PIO_CSD		S3C_CFATA_REG(0x70)
> > +#define S3C_ATA_PIO_DAD		S3C_CFATA_REG(0x74)
> > +#define S3C_ATA_PIO_READY	S3C_CFATA_REG(0x78)
> > +#define S3C_ATA_PIO_RDATA	S3C_CFATA_REG(0x7c)
> > +
> > +#define S3C_CFATA_MUX_TRUEIDE	0x01
> > +
> > +#define S3C_ATA_CFG_SWAP	0x40
> > +#define S3C_ATA_CFG_IORDYEN	0x02
> > +
> > +#endif /* __ASM_PLAT_REGS_ATA_H */
> > --
> > 1.6.2.5
> >


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Tue Jun  1 22:33:23 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 02 Jun 2010 11:33:23 +0900
Subject: [PATCH 1/4] ARM: S3C64XX: Add support for Compact Flash driver	on
	SMDK6410
In-Reply-To: <20100527194559.GC25921@n2100.arm.linux.org.uk>
References: <1274948524-2970-1-git-send-email-kgene.kim@samsung.com>
	<1274948524-2970-2-git-send-email-kgene.kim@samsung.com>
	<20100527194559.GC25921@n2100.arm.linux.org.uk>
Message-ID: <002701cb01fb$fd5eab10$f81c0130$%kim@samsung.com>

Russell King - ARM Linux wrote:
> 
> On Thu, May 27, 2010 at 05:22:01PM +0900, Kukjin Kim wrote:
> > +#include <mach/map.h>
> > +#include <mach/gpio.h>
> 
> shouldn't this be linux/gpio.h ?

Will change it.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Tue Jun  1 22:34:31 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 02 Jun 2010 11:34:31 +0900
Subject: [PATCH 3/4] ARM: S5PC100: Add support for Compact Flash driver	on
	SMDKC100
In-Reply-To: <20100527194714.GE25921@n2100.arm.linux.org.uk>
References: <1274948524-2970-1-git-send-email-kgene.kim@samsung.com>
	<1274948524-2970-4-git-send-email-kgene.kim@samsung.com>
	<20100527194714.GE25921@n2100.arm.linux.org.uk>
Message-ID: <002801cb01fc$245ad4f0$6d107ed0$%kim@samsung.com>

Russell King - ARM Linux wrote:
> 
> On Thu, May 27, 2010 at 05:22:03PM +0900, Kukjin Kim wrote:
> > +#include <linux/kernel.h>
> > +#include <linux/types.h>
> > +#include <linux/io.h>
> > +
> > +#include <mach/gpio.h>
> 
> linux/gpio.h ?

Will change it :-)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Tue Jun  1 22:37:15 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 02 Jun 2010 11:37:15 +0900
Subject: [PATCH 4/4] pata_samsung: Add Samsung PATA controller driver
In-Reply-To: <20100527084332.GI4720@trinity.fluff.org>
References: <1274948524-2970-1-git-send-email-kgene.kim@samsung.com>
	<1274948524-2970-5-git-send-email-kgene.kim@samsung.com>
	<20100527084332.GI4720@trinity.fluff.org>
Message-ID: <002901cb01fc$85bbb9d0$91332d70$%kim@samsung.com>

Ben Dooks wrote:
> 
> On Thu, May 27, 2010 at 05:22:04PM +0900, Kukjin Kim wrote:
> > From: Abhilash Kesavan <a.kesavan at samsung.com>
> >
> > Adds support for the Samsung PATA controller. This driver is based on the
> > Libata subsystem and references the earlier patches sent for IDE
subsystem.
> >
> > Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> > ---
> >  drivers/ata/Kconfig        |    9 +
> >  drivers/ata/Makefile       |    1 +
> >  drivers/ata/pata_samsung.c |  591
> ++++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 601 insertions(+), 0 deletions(-)
> >  create mode 100644 drivers/ata/pata_samsung.c
> >
> > diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> > index e68541f..ce40f66 100644
> > --- a/drivers/ata/Kconfig
> > +++ b/drivers/ata/Kconfig
> > @@ -640,6 +640,15 @@ config PATA_RZ1000
> >
> >  	  If unsure, say N.
> >
> > +config PATA_SAMSUNG
> > +	tristate "Samsung SoC PATA support"
> > +	depends on S3C_DEV_IDE
> > +	help
> > +	  This option enables basic support for Samsung's S3C/S5P board
> > +	  PATA controllers via the new ATA layer
> > +
> > +	  If unsure, say N.
> > +
> >  config PATA_SC1200
> >  	tristate "SC1200 PATA support"
> >  	depends on PCI
> > diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> > index d0a93c4..0b6d29a 100644
> > --- a/drivers/ata/Makefile
> > +++ b/drivers/ata/Makefile
> > @@ -62,6 +62,7 @@ obj-$(CONFIG_PATA_RADISYS)	+= pata_radisys.o
> >  obj-$(CONFIG_PATA_RB532)	+= pata_rb532_cf.o
> >  obj-$(CONFIG_PATA_RDC)		+= pata_rdc.o
> >  obj-$(CONFIG_PATA_RZ1000)	+= pata_rz1000.o
> > +obj-$(CONFIG_PATA_SAMSUNG)	+= pata_samsung.o
> do you want to call it pata_samsung_soc.o instead, in case samsung make
> otehr types of pata controller?

Will change the name to pata_samsung_cf.

> >  obj-$(CONFIG_PATA_SC1200)	+= pata_sc1200.o
> >  obj-$(CONFIG_PATA_SERVERWORKS)	+= pata_serverworks.o
> >  obj-$(CONFIG_PATA_SIL680)	+= pata_sil680.o
> > diff --git a/drivers/ata/pata_samsung.c b/drivers/ata/pata_samsung.c
> > new file mode 100644
> > index 0000000..14381e4
> > --- /dev/null
> > +++ b/drivers/ata/pata_samsung.c
> > @@ -0,0 +1,591 @@
> > +/* linux/drivers/ata/pata_samsung.c
> > + *
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com
> > + *
> > + * PATA driver for Samsung SoC's.
> SoCs.

OK

> > + * Supports CF Interface in True IDE mode. Currently only PIO mode has
been
> > + * implemented; UDMA support has to be added.
> > + *
> > + * Based on:
> > + *	PATA driver for AT91SAM9260 Static Memory Controller
> > + *	PATA driver for Toshiba SCC controller
> > + *
> > + * This program is free software; you can redistribute it and/or modify
it
> > + * under the terms of the GNU General Public License version 2
> > + * as published by the Free Software Foundation.
> > +*/
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/init.h>
> > +#include <linux/clk.h>
> > +#include <linux/libata.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +
> > +#include <plat/ata.h>
> > +#include <plat/regs-ata.h>
> > +
> > +#define DRV_NAME "pata_samsung"
> > +#define DRV_VERSION "0.1"
> > +
> > +enum s3c_cpu_type {
> > +	TYPE_S3C6400,
> > +	TYPE_S5PC100,
> > +	TYPE_S5PV210,
> > +};
> > +
> > +/*
> > + * struct s3c_ide_info - S3C PATA instance.
> > + * @clk: The clock resource for this controller.
> > + * @ide_addr: The area mapped for the hardware registers.
> > + * @sfr_addr: The area mapped for the special function registers.
> > + * @irq: The IRQ number we are using.
> > + * @cpu_type: The exact type of this controller.
> > + * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
> > + */
> > +struct s3c_ide_info {
> > +	struct clk *clk;
> > +	void __iomem *ide_addr;
> > +	void __iomem *sfr_addr;
> > +	unsigned int irq;
> > +	enum s3c_cpu_type cpu_type;
> > +	unsigned int fifo_status_reg;
> > +};
> > +
> > +static unsigned long piotime[5];
> > +
> > +static void pata_s3c_set_endian(void *s3c_ide_regbase, u8 mode)
> > +{
> > +	u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
> > +	reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg |
> S3C_ATA_CFG_SWAP);
> > +	writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
> > +}
> > +
> > +static void pata_s3c_tune_chipset(struct s3c_ide_info *info, u8
ide_mode)
> > +{
> > +	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
> > +
> > +	/* IORDY is enabled for modes > PIO2 */
> > +	if (XFER_PIO_0 <= ide_mode && ide_mode <= XFER_PIO_4) {
> > +
> > +		switch (ide_mode) {
> > +		case XFER_PIO_0:
> > +		case XFER_PIO_1:
> > +		case XFER_PIO_2:
> > +			ata_cfg &= (~S3C_ATA_CFG_IORDYEN);
> > +			break;
> > +		case XFER_PIO_3:
> > +		case XFER_PIO_4:
> > +			ata_cfg |= S3C_ATA_CFG_IORDYEN;
> > +			break;
> > +		}
> > +
> > +		writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
> > +		writel(piotime[ide_mode - XFER_PIO_0],
> > +			info->ide_addr + S3C_ATA_PIO_TIME);
> > +	} else {
> > +		/* Default to PIO0 */
> > +		ata_cfg &= (~S3C_ATA_CFG_IORDYEN);
> technically no need to ().

OK

> > +		writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
> > +		writel(piotime[0], info->ide_addr + S3C_ATA_PIO_TIME);
> > +	}
> > +}
> > +
> > +static void
> > +pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
> > +{
> > +	struct s3c_ide_info *info = ap->host->private_data;
> > +
> > +	/* Configure IORDY based on PIO mode and also set the timing value */
> > +	pata_s3c_tune_chipset(info, adev->pio_mode);
> > +}
> > +
> > +/*
> > + * Waits until the IDE controller is able to perform next read/write
> > + * operation to the disk. Needed for 64XX series boards only.
> > + */
> > +static int wait_for_host_ready(struct s3c_ide_info *info)
> > +{
> > +	ulong timeout;
> > +
> > +	/* wait for maximum of 20 msec */
> > +	timeout = jiffies + msecs_to_jiffies(20);
> > +	while (time_before(jiffies, timeout)) {
> > +		if ((readl(info->ide_addr + info->fifo_status_reg) >> 28) ==
0)
> > +			return 0;
> > +	}
> > +	return -EBUSY;
> > +}
> > +
> > +/*
> > + * Writes to one of the task file registers.
> > + */
> > +static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
> > +{
> > +	struct s3c_ide_info *info = host->private_data;
> > +
> > +	wait_for_host_ready(info);
> > +	__raw_writeb(addr, reg);
> > +}
> 
> probably want writeb() here. you've used the non __raw versions elsewhere.
> 

OK

> > +/*
> > + * Reads from one of the task file registers.
> > + */
> > +static u8 ata_inb(struct ata_host *host, void __iomem *reg)
> > +{
> > +	struct s3c_ide_info *info = host->private_data;
> > +	u8 temp;
> > +
> > +	wait_for_host_ready(info);
> > +	temp = __raw_readb(reg);
> > +	wait_for_host_ready(info);
> > +	temp = __raw_readb(info->ide_addr + S3C_ATA_PIO_RDATA);
> > +	return temp;
> > +}
> > +
> > +/*
> > + * pata_s3c_tf_load - send taskfile registers to host controller
> > + */
> > +static void pata_s3c_tf_load(struct ata_port *ap,
> > +				const struct ata_taskfile *tf)
> > +{
> > +	struct ata_ioports *ioaddr = &ap->ioaddr;
> > +	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
> > +
> > +	if (tf->ctl != ap->last_ctl) {
> > +		if (ioaddr->ctl_addr)
> > +			ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
> > +		ap->last_ctl = tf->ctl;
> > +		ata_wait_idle(ap);
> > +	}
> > +
> > +	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
> > +		WARN_ON_ONCE(!ioaddr->ctl_addr);
> > +		ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
> > +		ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
> > +		ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
> > +		ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
> > +		ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
> > +	}
> > +
> > +	if (is_addr) {
> > +		ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
> > +		ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
> > +		ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
> > +		ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
> > +		ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
> > +	}
> > +
> > +	if (tf->flags & ATA_TFLAG_DEVICE)
> > +		ata_outb(ap->host, tf->device, ioaddr->device_addr);
> > +
> > +	ata_wait_idle(ap);
> > +}
> > +
> > +/*
> > + * pata_s3c_tf_read - input device's ATA taskfile shadow registers
> > + */
> > +static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile
*tf)
> > +{
> > +	struct ata_ioports *ioaddr = &ap->ioaddr;
> > +
> > +	tf->command = ata_sff_check_status(ap);
> > +	tf->feature = ata_inb(ap->host, ioaddr->error_addr);
> > +	tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
> > +	tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
> > +	tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
> > +	tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
> > +	tf->device = ata_inb(ap->host, ioaddr->device_addr);
> > +
> > +	if (tf->flags & ATA_TFLAG_LBA48) {
> > +		if (likely(ioaddr->ctl_addr)) {
> > +			iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
> > +			tf->hob_feature = ata_inb(ap->host,
ioaddr->error_addr);
> > +			tf->hob_nsect = ata_inb(ap->host,
ioaddr->nsect_addr);
> > +			tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
> > +			tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
> > +			tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
> > +			iowrite8(tf->ctl, ioaddr->ctl_addr);
> > +			ap->last_ctl = tf->ctl;
> > +		} else
> > +			WARN_ON_ONCE(1);
> > +	}
> > +}
> > +
> > +/*
> > + * pata_s3c_exec_command - issue ATA command to host controller
> > + */
> > +static void pata_s3c_exec_command(struct ata_port *ap,
> > +				const struct ata_taskfile *tf)
> > +{
> > +	ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
> > +	ata_sff_pause(ap);
> > +}
> > +
> > +/*
> > + * pata_s3c_check_status - Read device status register
> > + */
> > +static u8 pata_s3c_check_status(struct ata_port *ap)
> > +{
> > +	return ata_inb(ap->host, ap->ioaddr.status_addr);
> > +}
> > +
> > +/*
> > + * pata_s3c_data_xfer - Transfer data by PIO
> > + */
> > +unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char
*buf,
> > +				unsigned int buflen, int rw)
> > +{
> > +	struct ata_port *ap = dev->link->ap;
> > +	struct s3c_ide_info *info = ap->host->private_data;
> > +	void __iomem *data_addr = ap->ioaddr.data_addr;
> > +	unsigned int words = buflen >> 1, i;
> > +	u16 *temp_addr = (u16 *)buf;
> 
> hmm, how about calling it data_ptr instead of temp_addr?
> 

OK

> > +	if (rw == READ) {
> > +		for (i = 0; i < words; i++, temp_addr++) {
> > +			wait_for_host_ready(info);
> > +			*temp_addr = __raw_readw(data_addr);
> > +			wait_for_host_ready(info);
> > +			*temp_addr = __raw_readw(info->ide_addr
> > +					+ S3C_ATA_PIO_RDATA)
> 
> think you want readw() here, please ensure consitency.
> 
> this also look a bit weird, you are writing to *temp_addr twice,
> could you simply dicscard the first read?
> 
> note, you say s3c64xx only needs wait_for_host_ready() but you
> always call it?
> 

wait_for_host_ready is called via pata_s3c_port_ops which is only for 64xx.

> > +		}
> > +	} else {
> > +		for (i = 0; i < words; i++, temp_addr++) {
> > +			wait_for_host_ready(info);
> > +			writel(*temp_addr, data_addr);
> > +		}
> > +	}
> > +
> > +	return words << 1;
> > +}
> > +
> > +static struct scsi_host_template pata_s3c_sht = {
> > +	ATA_PIO_SHT(DRV_NAME),
> > +};
> > +
> > +static struct ata_port_operations pata_s3c_port_ops = {
> > +	.inherits		= &ata_sff_port_ops,
> > +	.sff_check_status	= pata_s3c_check_status,
> > +	.sff_tf_load		= pata_s3c_tf_load,
> > +	.sff_tf_read		= pata_s3c_tf_read,
> > +	.sff_data_xfer		= pata_s3c_data_xfer,
> > +	.sff_exec_command	= pata_s3c_exec_command,
> > +	.qc_prep		= ata_noop_qc_prep,
> > +	.set_piomode		= pata_s3c_set_piomode,
> > +};
> > +
> > +static struct ata_port_operations pata_s5p_port_ops = {
> > +	.inherits		= &ata_sff_port_ops,
> > +	.qc_prep		= ata_noop_qc_prep,
> > +	.set_piomode		= pata_s3c_set_piomode,
> > +};
> > +
> > +static void pata_s3c_enable(void *s3c_ide_regbase, u8 state)
> > +{
> > +	u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
> > +	temp = state ? temp | 1 : temp & ~1;
> you might want ()around the temp |1 and temp & ~1

OK

> > +	writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
> > +}
> > +
> > +static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
> > +{
> > +	struct ata_host *host = dev_instance;
> > +	struct s3c_ide_info *info = host->private_data;
> > +	u32 reg;
> > +
> > +	reg = readl(info->ide_addr + S3C_ATA_IRQ);
> > +	writel(reg, info->ide_addr + S3C_ATA_IRQ);
> > +
> > +	return ata_sff_interrupt(irq, dev_instance);
> > +}
> > +
> > +static void pata_s3c_setup_timing(struct s3c_ide_info *info)
> > +{
> > +	uint t1, t2, teoc, i;
> > +
> > +	uint pio_t1[5] = { 70, 50, 30, 30, 25 };
> > +	uint pio_t2[5] = { 290, 290, 290, 80, 70 };
> > +	uint pio_teoc[5] = { 240, 43, 10, 70, 25 };
> > +
> > +	ulong cycle_time = (uint) (1000000000 / clk_get_rate(info->clk));
> 
> ulong and uinit? surely pick one. you might want to keep UL and cajhnge
> 1000000000 to 1000000000UL
> 

OK

> > +	for (i = 0; i < 5; i++) {
> > +		t1 = (pio_t1[i] / cycle_time) & 0x0f;
> > +		t2 = (pio_t2[i] / cycle_time) & 0xff;
> > +		teoc = (pio_teoc[i] / cycle_time) & 0xff;
> > +		piotime[i] = (teoc << 12) | (t2 << 4) | t1;
> > +	}
> > +}
> > +
> > +static void pata_s3c_hwinit(struct s3c_ide_info *info,
> > +				struct s3c_ide_platdata *pdata)
> > +{
> > +	/* Select true-ide as the internal operating mode*/
> > +	if (pdata && (pdata->cfg_mode))
> > +		pdata->cfg_mode(info->sfr_addr);
> > +
> > +	switch (info->cpu_type) {
> > +	case TYPE_S3C6400:
> > +		/* Configure as big endian and enable the i/f*/
> > +		pata_s3c_set_endian(info->ide_addr, 1);
> > +		pata_s3c_enable(info->ide_addr, 1);
> > +		mdelay(100);
> > +
> > +		/* Remove IRQ Status */
> > +		writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
> > +		writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
> > +	break;
> > +
> > +	case TYPE_S5PV210:
> > +	case TYPE_S5PC100:
> > +		/* Configure as little endian and enable the i/f */
> > +		pata_s3c_set_endian(info->ide_addr, 0);
> > +		pata_s3c_enable(info->ide_addr, 1);
> > +		mdelay(100);
> > +
> > +		/* Remove IRQ Status */
> > +		writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
> > +		writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
> > +	break;
> > +
> > +	default:
> > +		BUG();
> > +	}
> > +}
> > +
> > +static int __devinit pata_s3c_probe(struct platform_device *pdev)
> > +{
> > +	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
> > +	struct device *dev = &pdev->dev;
> > +	struct s3c_ide_info *info;
> > +	struct resource *res;
> > +	struct ata_port *ap;
> > +	struct ata_host *host;
> > +	enum s3c_cpu_type cpu_type;
> > +	int ret;
> > +
> > +	cpu_type = platform_get_device_id(pdev)->driver_data;
> > +
> > +	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
> > +	if (!info) {
> > +		dev_err(dev, "failed to allocate memory for device data\n");
> > +		return -ENOMEM;
> > +	}
> > +
> > +	info->irq = platform_get_irq(pdev, 0);
> > +	if (info->irq < 0) {
> > +		dev_err(dev, "could not obtain irq number\n");
> > +		ret = -ENODEV;
> > +		goto release_device_mem;
> > +	}
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	if (res == NULL) {
> > +		dev_err(dev, "failed to get mem resource\n");
> > +		ret = -ENODEV;
> 
> if i remeber correctly, you don't want to be returning -ENODEV as
> it will be ignored by the uper layers.
> 

Will replace with EINVAL.

> > +		goto release_device_mem;
> > +	}
> > +
> > +	info->ide_addr = devm_ioremap(dev,
> > +				res->start, res->end - res->start + 1);
> 
> resource_size() is your friend here.
> 

OK

> > +	if (!info->ide_addr) {
> > +		dev_err(dev, "failed to map IO base address\n");
> > +		ret = -ENOMEM;
> > +		goto release_mem;
> > +	}
> > +
> > +	info->clk = clk_get(&pdev->dev, "cfcon");
> 
> need to do something about using explicit names here, should be clk_get(,
NULL)
> 

OK

> > +	if (IS_ERR(info->clk)) {
> > +		dev_err(dev, "failed to get access to cf controller
clock\n");
> > +		ret = PTR_ERR(info->clk);
> > +		info->clk = NULL;
> > +		goto unmap;
> > +	}
> > +
> > +	if (clk_enable(info->clk)) {
> > +		dev_err(dev, "failed to enable clock source.\n");
> > +		goto clkerr;
> > +	}
> > +
> > +	/* init ata host */
> > +	host = ata_host_alloc(dev, 1);
> > +	if (!host) {
> > +		dev_err(dev, "failed to allocate ide host\n");
> > +		ret = -ENOMEM;
> > +		goto stop_clk;
> > +	}
> > +
> > +	ap = host->ports[0];
> > +	ap->flags |= ATA_FLAG_MMIO;
> > +	ap->pio_mask = ATA_PIO4;
> > +
> > +	if (cpu_type == TYPE_S3C6400) {
> > +		ap->ops = &pata_s3c_port_ops;
> > +		info->sfr_addr = info->ide_addr + 0x1800;
> > +		info->ide_addr = info->ide_addr + 0x1900;
> > +		info->fifo_status_reg = 0x94;
> > +	} else if (cpu_type == TYPE_S5PC100) {
> > +		ap->ops = &pata_s5p_port_ops;
> > +		info->sfr_addr = info->ide_addr + 0x1800;
> > +		info->ide_addr = info->ide_addr + 0x1900;
> > +		info->fifo_status_reg = 0x84;
> > +	} else {
> > +		ap->ops = &pata_s5p_port_ops;
> > +		info->fifo_status_reg = 0x84;
> > +	}
> > +
> > +	info->cpu_type = cpu_type;
> > +
> > +	if (!(info->irq)) {
> > +		ap->flags |= ATA_FLAG_PIO_POLLING;
> > +		ata_port_desc(ap, "no IRQ, using PIO polling\n");
> > +	}
> > +
> > +	ap->ioaddr.cmd_addr =  info->ide_addr + S3C_ATA_CMD;
> > +	ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
> > +	ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
> > +	ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
> > +	ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
> > +	ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
> > +	ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
> > +	ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
> > +	ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
> > +	ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
> > +	ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
> > +	ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
> > +	ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
> > +
> > +
> > +	ata_port_desc(ap, "mmio cmd 0x%llx ",
> > +			(unsigned long long)res->start);
> > +
> > +	host->private_data = info;
> > +
> > +	/* Calculates timing parameters for PIO mode */
> > +	pata_s3c_setup_timing(info);
> > +
> > +	if (pdata && (pdata->setup_gpio))
> no need for () around the pdata->setup_gpio

OK

> > +		pdata->setup_gpio();
> > +
> > +	/* Set endianness and enable the interface */
> > +	pata_s3c_hwinit(info, pdata);
> > +
> > +	return ata_host_activate(host, info->irq ? info->irq : 0,
> > +			info->irq ? pata_s3c_irq : NULL,
> > +			IRQF_DISABLED, &pata_s3c_sht);
> 
> do you really need to run with IRQs disabled?
> 

No.. will correct it

> > +	dev_set_drvdata(&pdev->dev, host);
> > +
> > +stop_clk:
> > +	clk_disable(info->clk);
> > +clkerr:
> > +	clk_put(info->clk);
> > +unmap:
> > +	devm_iounmap(dev, info->ide_addr);
> > +release_mem:
> > +	release_mem_region(res->start, res->end - res->start + 1);
> > +release_device_mem:
> > +	kfree(info);
> > +return ret;
> > +}
> > +
> > +static int __devexit pata_s3c_remove(struct platform_device *pdev)
> > +{
> > +	struct ata_host *host = dev_get_drvdata(&pdev->dev);
> > +	struct s3c_ide_info *info;
> > +	struct resource *res;
> > +
> > +	if (!host)
> > +		return 0;
> > +	info = host->private_data;
> > +
> > +	ata_host_detach(host);
> > +
> > +	devm_iounmap(&pdev->dev, info->ide_addr);
> > +	clk_disable(info->clk);
> > +	clk_put(info->clk);
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	release_mem_region(res->start, res->end - res->start + 1);
> > +	kfree(info);
> > +
> > +	return 0;
> > +}
> > +
> > +#ifdef CONFIG_PM
> > +static int pata_s3c_suspend(struct platform_device *pdev, pm_message_t
state)
> > +{
> > +	struct ata_host *host = dev_get_drvdata(&pdev->dev);
> > +	if (host)
> > +		return ata_host_suspend(host, state);
> > +	else
> > +		return 0;
> > +}
> > +
> > +static int pata_s3c_resume(struct platform_device *pdev)
> > +{
> > +	struct ata_host *host = dev_get_drvdata(&pdev->dev);
> > +	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
> > +	struct s3c_ide_info *info;
> > +
> > +	info = host->private_data;
> > +
> > +	if (host) {
> > +		pata_s3c_hwinit(info, pdata);
> > +		ata_host_resume(host);
> > +	}
> > +
> > +	return 0;
> > +}
> > +#endif
> > +
> > +/* driver device registration */
> > +static struct platform_device_id pata_s3c_driver_ids[] = {
> > +	{
> > +		.name		= "s3c6400-pata",
> > +		.driver_data	= TYPE_S3C6400,
> > +	}, {
> > +		.name		= "s5pc100-pata",
> > +		.driver_data	= TYPE_S5PC100,
> > +	}, {
> > +		.name		= "s5pv210-pata",
> > +		.driver_data	= TYPE_S5PV210,
> > +	},
> > +	{ }
> > +};
> > +
> > +MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
> > +
> > +static struct platform_driver pata_s3c_driver = {
> > +	.probe		= pata_s3c_probe,
> > +	.remove		= __devexit_p(pata_s3c_remove),
> > +	.id_table	= pata_s3c_driver_ids,
> > +	.driver		= {
> > +		.name		= DRV_NAME,
> > +		.owner		= THIS_MODULE,
> > +	},
> > +#ifdef CONFIG_PM
> > +	.suspend	= pata_s3c_suspend,
> > +	.resume		= pata_s3c_resume,
> > +#endif
> please look at using the new pm_ops.
> 

Will use dev_pm_ops.

> > +};
> > +
> > +static int __init pata_s3c_init(void)
> > +{
> > +	return platform_driver_register(&pata_s3c_driver);
> > +}
> > +
> > +static void __exit pata_s3c_exit(void)
> > +{
> > +	platform_driver_unregister(&pata_s3c_driver);
> > +}
> > +
> > +module_init(pata_s3c_init);
> > +module_exit(pata_s3c_exit);
> > +
> > +MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan at samsung.com>");
> > +MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
> > +MODULE_LICENSE("GPL");
> > +MODULE_VERSION(DRV_VERSION);
> > --
> > 1.6.2.5
> 
> not bad, needs some cleanup.
> 


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Tue Jun  1 22:42:49 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 02 Jun 2010 11:42:49 +0900
Subject: [PATCH 4/4] pata_samsung: Add Samsung PATA controller driver
In-Reply-To: <4BFE46C4.5030007@mvista.com>
References: <1274948524-2970-1-git-send-email-kgene.kim@samsung.com>
	<1274948524-2970-5-git-send-email-kgene.kim@samsung.com>
	<4BFE46C4.5030007@mvista.com>
Message-ID: <002a01cb01fd$4cf10a50$e6d31ef0$%kim@samsung.com>

Sergei Shtylyov wrote:
> 
> Hello.
> 

Hi :-)

> Kukjin Kim wrote:
> 
> > From: Abhilash Kesavan <a.kesavan at samsung.com>
> 
> > Adds support for the Samsung PATA controller. This driver is based on the
> > Libata subsystem and references the earlier patches sent for IDE
subsystem.
> 
> > Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> 
> > diff --git a/drivers/ata/pata_samsung.c b/drivers/ata/pata_samsung.c
> > new file mode 100644
> > index 0000000..14381e4
> > --- /dev/null
> > +++ b/drivers/ata/pata_samsung.c
> > @@ -0,0 +1,591 @@
> [...]
> > +static void pata_s3c_tune_chipset(struct s3c_ide_info *info, u8
ide_mode)
> > +{
> > +	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
> > +
> > +	/* IORDY is enabled for modes > PIO2 */
> > +	if (XFER_PIO_0 <= ide_mode && ide_mode <= XFER_PIO_4) {
> > +
> > +		switch (ide_mode) {
> > +		case XFER_PIO_0:
> > +		case XFER_PIO_1:
> > +		case XFER_PIO_2:
> > +			ata_cfg &= (~S3C_ATA_CFG_IORDYEN);
> 
>     Useless parens.
> 
OK

> > +			break;
> > +		case XFER_PIO_3:
> > +		case XFER_PIO_4:
> > +			ata_cfg |= S3C_ATA_CFG_IORDYEN;
> 
>     IORDY should be controlled by ata_id_pio_need_iordy(),  not by mode
> number. PIO2 also can have IODRY enabled.
> 
Will use ata_id_pio_need_iordy().

> > +			break;
> > +		}
> > +
> > +		writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
> > +		writel(piotime[ide_mode - XFER_PIO_0],
> > +			info->ide_addr + S3C_ATA_PIO_TIME);
> > +	} else {
> > +		/* Default to PIO0 */
> > +		ata_cfg &= (~S3C_ATA_CFG_IORDYEN);
> > +		writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
> > +		writel(piotime[0], info->ide_addr + S3C_ATA_PIO_TIME);
> 
>     If you don't support DMA modes or modes higher than PIO4 (PIO5 and
> PIO6 would have been good for CF though), just do nothing.
> 
OK

> > +	}
> > +}
> > +
> > +static void
> > +pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
> > +{
> > +	struct s3c_ide_info *info = ap->host->private_data;
> > +
> > +	/* Configure IORDY based on PIO mode and also set the timing value */
> > +	pata_s3c_tune_chipset(info, adev->pio_mode);
> 
>     Don't see why you need a separate function for that. Maybe in
> preparation to UDMA support?
> 
That was it..but will remove pata_s3c_set_piomode() and call
pata_s3c_tune_chipset() directly.

> > +/*
> > + * Writes to one of the task file registers.
> > + */
> > +static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
> > +{
> > +	struct s3c_ide_info *info = host->private_data;
> > +
> > +	wait_for_host_ready(info);
> > +	__raw_writeb(addr, reg);
> 
>     You should use write?() or __raw_write?() consistently...
> 
OK

> > +/*
> > + * pata_s3c_tf_load - send taskfile registers to host controller
> > + */
> > +static void pata_s3c_tf_load(struct ata_port *ap,
> > +				const struct ata_taskfile *tf)
> > +{
> > +	struct ata_ioports *ioaddr = &ap->ioaddr;
> > +	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
> > +
> > +	if (tf->ctl != ap->last_ctl) {
> > +		if (ioaddr->ctl_addr)
> 
>     This register does exist and you assign ioaddr->ctl_addr in
> pata_s3c_probe(), hence the check is pointless.
> 
Will remove the check.

> > +			ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
> > +		ap->last_ctl = tf->ctl;
> > +		ata_wait_idle(ap);
> > +	}
> > +
> > +	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
> > +		WARN_ON_ONCE(!ioaddr->ctl_addr);
> 
>     You don't need this either.
> 
OK

> > +/*
> > + * pata_s3c_tf_read - input device's ATA taskfile shadow registers
> > + */
> > +static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile
*tf)
> > +{
> > +	struct ata_ioports *ioaddr = &ap->ioaddr;
> > +
> > +	tf->command = ata_sff_check_status(ap);
> 
>     But you have overriden this method, so ata_sff_check_status()
> shouldn't work!
> 
OK

> > +	tf->feature = ata_inb(ap->host, ioaddr->error_addr);
> > +	tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
> > +	tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
> > +	tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
> > +	tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
> > +	tf->device = ata_inb(ap->host, ioaddr->device_addr);
> > +
> > +	if (tf->flags & ATA_TFLAG_LBA48) {
> > +		if (likely(ioaddr->ctl_addr)) {
> 
>     Not just likely, it's always true. Emilinate the check please.
> 
OK

> > +			iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
> > +			tf->hob_feature = ata_inb(ap->host,
ioaddr->error_addr);
> > +			tf->hob_nsect = ata_inb(ap->host,
ioaddr->nsect_addr);
> > +			tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
> > +			tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
> > +			tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
> > +			iowrite8(tf->ctl, ioaddr->ctl_addr);
> > +			ap->last_ctl = tf->ctl;
> > +		} else
> > +			WARN_ON_ONCE(1);
> 
>     Not needed.
> 
OK

> > +/*
> > + * pata_s3c_data_xfer - Transfer data by PIO
> > + */
> > +unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char
*buf,
> > +				unsigned int buflen, int rw)
> > +{
> > +	struct ata_port *ap = dev->link->ap;
> > +	struct s3c_ide_info *info = ap->host->private_data;
> > +	void __iomem *data_addr = ap->ioaddr.data_addr;
> > +	unsigned int words = buflen >> 1, i;
> > +	u16 *temp_addr = (u16 *)buf;
> > +
> > +	if (rw == READ) {
> 
>     {} not needed.
> 
OK

> > +		for (i = 0; i < words; i++, temp_addr++) {
> > +			wait_for_host_ready(info);
> > +			*temp_addr = __raw_readw(data_addr);
> > +			wait_for_host_ready(info);
> > +			*temp_addr = __raw_readw(info->ide_addr
> > +					+ S3C_ATA_PIO_RDATA);
> > +		}
> > +	} else {
> 
>     {} not needed.
> 
OK

> > +		for (i = 0; i < words; i++, temp_addr++) {
> > +			wait_for_host_ready(info);
> > +			writel(*temp_addr, data_addr);
> > +		}
> > +	}
> 
>     Well, if this is pere CF case, 'buflen' can't be odd, but otherwise
> you should handle that case...
> 
OK

> > +
> > +	return words << 1;
> > +}
> > +
> > +static struct scsi_host_template pata_s3c_sht = {
> > +	ATA_PIO_SHT(DRV_NAME),
> > +};
> > +
> > +static struct ata_port_operations pata_s3c_port_ops = {
> > +	.inherits		= &ata_sff_port_ops,
> > +	.sff_check_status	= pata_s3c_check_status,
> 
>     Since simple iowrite8() isn't enough in your case, you also need to
> override sff_dev_select(), sff_check_altstatus(), and sff_set_devctl()
> methods...
> 
Will add these overrides.

> > +	.sff_tf_load		= pata_s3c_tf_load,
> > +	.sff_tf_read		= pata_s3c_tf_read,
> > +	.sff_data_xfer		= pata_s3c_data_xfer,
> > +	.sff_exec_command	= pata_s3c_exec_command,
> > +	.qc_prep		= ata_noop_qc_prep,
> > +	.set_piomode		= pata_s3c_set_piomode,
> > +};
> > +
> > +static struct ata_port_operations pata_s5p_port_ops = {
> > +	.inherits		= &ata_sff_port_ops,
> > +	.qc_prep		= ata_noop_qc_prep,
> > +	.set_piomode		= pata_s3c_set_piomode,
> > +};
> 
> [...]
> 
> > +static void pata_s3c_setup_timing(struct s3c_ide_info *info)
> > +{
> > +	uint t1, t2, teoc, i;
> > +
> > +	uint pio_t1[5] = { 70, 50, 30, 30, 25 };
> 
>     Could use ata_timing_find_mode() here to get the mode timings,
> intead of duplicating them from libata-ocre.c...
> 
> > +	uint pio_t2[5] = { 290, 290, 290, 80, 70 };
> 
>     Note that those active times are for command cycles, not for data ones.
> 
OK

> > +	uint pio_teoc[5] = { 240, 43, 10, 70, 25 };
> 
>     What timing is this? :-O
> 
Should have been t2i rec.

> > +
> > +	ulong cycle_time = (uint) (1000000000 / clk_get_rate(info->clk));
> > +
> > +	for (i = 0; i < 5; i++) {
> > +		t1 = (pio_t1[i] / cycle_time) & 0x0f;
> > +		t2 = (pio_t2[i] / cycle_time) & 0xff;
> 
>     Could use ata_timing_compute() here.
> 
Will re-use the timing parameters and ata_timing_compute(),
ata_timing_find_mode() from libata-core.c

> > +		teoc = (pio_teoc[i] / cycle_time) & 0xff;
> > +		piotime[i] = (teoc << 12) | (t2 << 4) | t1;
> > +	}
> > +}
> > +
> > +static void pata_s3c_hwinit(struct s3c_ide_info *info,
> > +				struct s3c_ide_platdata *pdata)
> > +{
> > +	/* Select true-ide as the internal operating mode*/
> > +	if (pdata && (pdata->cfg_mode))
> > +		pdata->cfg_mode(info->sfr_addr);
> > +
> > +	switch (info->cpu_type) {
> > +	case TYPE_S3C6400:
> > +		/* Configure as big endian and enable the i/f*/
> 
>     Put space before */, please.
> 
OK

> > +static int __devinit pata_s3c_probe(struct platform_device *pdev)
> > +{
> > +	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
> > +	struct device *dev = &pdev->dev;
> > +	struct s3c_ide_info *info;
> > +	struct resource *res;
> > +	struct ata_port *ap;
> > +	struct ata_host *host;
> > +	enum s3c_cpu_type cpu_type;
> > +	int ret;
> > +
> > +	cpu_type = platform_get_device_id(pdev)->driver_data;
> > +
> > +	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
> > +	if (!info) {
> > +		dev_err(dev, "failed to allocate memory for device data\n");
> > +		return -ENOMEM;
> > +	}
> > +
> > +	info->irq = platform_get_irq(pdev, 0);
> > +	if (info->irq < 0) {
> > +		dev_err(dev, "could not obtain irq number\n");
> > +		ret = -ENODEV;
> > +		goto release_device_mem;
> > +	}
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	if (res == NULL) {
> > +		dev_err(dev, "failed to get mem resource\n");
> > +		ret = -ENODEV;
> > +		goto release_device_mem;
> > +	}
> > +
> > +	info->ide_addr = devm_ioremap(dev,
> > +				res->start, res->end - res->start + 1);
> > +	if (!info->ide_addr) {
> > +		dev_err(dev, "failed to map IO base address\n");
> > +		ret = -ENOMEM;
> > +		goto release_mem;
> > +	}
> > +
> > +	info->clk = clk_get(&pdev->dev, "cfcon");
> > +	if (IS_ERR(info->clk)) {
> > +		dev_err(dev, "failed to get access to cf controller
clock\n");
> > +		ret = PTR_ERR(info->clk);
> > +		info->clk = NULL;
> > +		goto unmap;
> > +	}
> > +
> > +	if (clk_enable(info->clk)) {
> 
>     Can it really fail?
> 
Will remove it.

> > +		dev_err(dev, "failed to enable clock source.\n");
> > +		goto clkerr;
> > +	}
> > +
> > +	/* init ata host */
> > +	host = ata_host_alloc(dev, 1);
> > +	if (!host) {
> > +		dev_err(dev, "failed to allocate ide host\n");
> > +		ret = -ENOMEM;
> > +		goto stop_clk;
> > +	}
> > +
> > +	ap = host->ports[0];
> > +	ap->flags |= ATA_FLAG_MMIO;
> > +	ap->pio_mask = ATA_PIO4;
> > +
> > +	if (cpu_type == TYPE_S3C6400) {
> > +		ap->ops = &pata_s3c_port_ops;
> > +		info->sfr_addr = info->ide_addr + 0x1800;
> > +		info->ide_addr = info->ide_addr + 0x1900;
> > +		info->fifo_status_reg = 0x94;
> > +	} else if (cpu_type == TYPE_S5PC100) {
> > +		ap->ops = &pata_s5p_port_ops;
> > +		info->sfr_addr = info->ide_addr + 0x1800;
> > +		info->ide_addr = info->ide_addr + 0x1900;
> 
>     Does make sense to assign those before *if*.
> 
Offsets not required for S5PV210/S5PC110.

> > +		info->fifo_status_reg = 0x84;
> > +	} else {
> > +		ap->ops = &pata_s5p_port_ops;
> 
>     You don't assign 'info->ide_addr' here but you'll need it in
> pata_s3c_tune_chipset() which will be called thru pata_s5p_port_ops!
> 
The address received at ioremap() is enough for S5PV210/S5PC110..no offset
needed.

> > +		info->fifo_status_reg = 0x84;
> > +	}
> > +
> > +	info->cpu_type = cpu_type;
> > +
> > +	if (!(info->irq)) {
> 
>     Parens not needed around 'info->irq'.
> 
OK

> > +		ap->flags |= ATA_FLAG_PIO_POLLING;
> > +		ata_port_desc(ap, "no IRQ, using PIO polling\n");
> > +	}
> > +
> > +	ap->ioaddr.cmd_addr =  info->ide_addr + S3C_ATA_CMD;
> > +	ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
> > +	ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
> > +	ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
> > +	ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
> > +	ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
> > +	ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
> > +	ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
> > +	ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
> > +	ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
> > +	ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
> > +	ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
> > +	ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
> > +
> > +
> 
>      Extra newline?
> 
Yes..will remove it.

> > +	ata_port_desc(ap, "mmio cmd 0x%llx ",
> > +			(unsigned long long)res->start);
> > +
> > +	host->private_data = info;
> > +
> > +	/* Calculates timing parameters for PIO mode */
> > +	pata_s3c_setup_timing(info);
> 
>     You could do it right in pata_s3c_tune_chipset() -- no need to
> precalculate the timings.
> 
Will move it.

> > +	if (pdata && (pdata->setup_gpio))
> 
>     Prens not needed around 'pdata->setup_gpio'.
> 
OK

> > +		pdata->setup_gpio();
> > +
> > +	/* Set endianness and enable the interface */
> > +	pata_s3c_hwinit(info, pdata);
> > +
> > +	return ata_host_activate(host, info->irq ? info->irq : 0,
> 
>     This ?: doesn't make sense, just pass 'info->irq'.
> 
OK

> > +			info->irq ? pata_s3c_irq : NULL,
> > +			IRQF_DISABLED, &pata_s3c_sht);
> > +
> > +	dev_set_drvdata(&pdev->dev, host);
> 
>     Could use platform_set_drvdata(pdev, host)...
> 
OK

> > +
> > +stop_clk:
> > +	clk_disable(info->clk);
> > +clkerr:
> > +	clk_put(info->clk);
> > +unmap:
> > +	devm_iounmap(dev, info->ide_addr);
> 
>     devm_ioremap() should "look after itself", so no explicait call
> should be needed, if I don't mistake...
> 
OK

> > +release_mem:
> > +	release_mem_region(res->start, res->end - res->start + 1);
> 
>     But you didn't call request_mem_region()!
> 
I didn't..will remove.

> > +release_device_mem:
> > +	kfree(info);
> > +return ret;
> > +}
> > +
> > +static int __devexit pata_s3c_remove(struct platform_device *pdev)
> > +{
> > +	struct ata_host *host = dev_get_drvdata(&pdev->dev);
> 
>     Could use platform_get_drvdata(pdev)...
> 
OK

> > +	struct s3c_ide_info *info;
> > +	struct resource *res;
> > +
> > +	if (!host)
> > +		return 0;
> > +	info = host->private_data;
> > +
> > +	ata_host_detach(host);
> > +
> > +	devm_iounmap(&pdev->dev, info->ide_addr);
> > +	clk_disable(info->clk);
> > +	clk_put(info->clk);
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	release_mem_region(res->start, res->end - res->start + 1);
> 
>     Use resource_size(). Also, you don't call request_mem_region().
> 
OK

> > +	kfree(info);
> > +
> > +	return 0;
> > +}
> > +
> > +#ifdef CONFIG_PM
> > +static int pata_s3c_suspend(struct platform_device *pdev, pm_message_t
state)
> > +{
> > +	struct ata_host *host = dev_get_drvdata(&pdev->dev);
> 
>     Could use platform_get_drvdata(pdev)...
> 
OK

> > +	if (host)
> > +		return ata_host_suspend(host, state);
> > +	else
> > +		return 0;
> > +}
> > +
> > +static int pata_s3c_resume(struct platform_device *pdev)
> > +{
> > +	struct ata_host *host = dev_get_drvdata(&pdev->dev);
> 
>     Could use platform_get_drvdata(pdev)...
> 
OK


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Tue Jun  1 22:46:27 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 02 Jun 2010 11:46:27 +0900
Subject: [PATCH 4/4] pata_samsung: Add Samsung PATA controller driver
In-Reply-To: <4BFEE98B.3090303@kernel.org>
References: <1274948524-2970-1-git-send-email-kgene.kim@samsung.com>
	<1274948524-2970-5-git-send-email-kgene.kim@samsung.com>
	<4BFEE98B.3090303@kernel.org>
Message-ID: <002b01cb01fd$cf1589c0$6d409d40$%kim@samsung.com>

Tejun Heo wrote:
> 
> Hello,
> 
> On 05/27/2010 10:22 AM, Kukjin Kim wrote:
> > From: Abhilash Kesavan <a.kesavan at samsung.com>
> >
> > Adds support for the Samsung PATA controller. This driver is based on the
> > Libata subsystem and references the earlier patches sent for IDE
subsystem.
> 
> Just one small thing.
> 
> > +static struct ata_port_operations pata_s3c_port_ops = {
> > +	.inherits		= &ata_sff_port_ops,
> > +	.sff_check_status	= pata_s3c_check_status,
> > +	.sff_tf_load		= pata_s3c_tf_load,
> > +	.sff_tf_read		= pata_s3c_tf_read,
> > +	.sff_data_xfer		= pata_s3c_data_xfer,
> > +	.sff_exec_command	= pata_s3c_exec_command,
> > +	.qc_prep		= ata_noop_qc_prep,
> > +	.set_piomode		= pata_s3c_set_piomode,
> > +};
> > +
> > +static struct ata_port_operations pata_s5p_port_ops = {
> > +	.inherits		= &ata_sff_port_ops,
> > +	.qc_prep		= ata_noop_qc_prep,
> > +	.set_piomode		= pata_s3c_set_piomode,
> > +};
> 
> You don't need to override .qc_prep to ata_noop_qc_prep() and can you
> please base the patch against the current libata-dev#upstream?
> 
Will remove the override and rebase the new patches against upstream branch.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From felipe.balbi at nokia.com  Wed Jun  2 01:41:04 2010
From: felipe.balbi at nokia.com (Felipe Balbi)
Date: Wed, 2 Jun 2010 08:41:04 +0300
Subject: [RFC PATCH] irq: handle private interrupt registration
In-Reply-To: <alpine.LFD.2.00.1006020110090.2933@localhost.localdomain>
References: <1274905794-7848-1-git-send-email-adharmap@codeaurora.org>
	<20100601152652.9296c5d0.akpm@linux-foundation.org>
	<alpine.LFD.2.00.1006020110090.2933@localhost.localdomain>
Message-ID: <20100602054104.GE6465@nokia.com>

Hi,

On Wed, Jun 02, 2010 at 01:14:32AM +0200, ext Thomas Gleixner wrote:
>1) Use PER_CPU offsets for the irq numbers. The generic irq code does
>   not care whether the interrupt number is matching any physical
>   numbering scheme in the hardware, as long as the arch specific chip
>   implementation knows how to deal with it, which is not rocket
>   science to do.

FWIW, I think (1) is a better approach as the problem will vanish 
altogether and to me it sounds like the simpler approach as well. Archs 
which have more than one IRQ chip (like OMAP with the twl4030 family) 
will already use sequencial numbering anyway, so using the same approach 
for N cpus, to me, sounds like a good deal.

While at that, a question from my side: do we have a generic way of 
fetching the last IRQ number so we can easily use that to calculate the 
physical number of the IRQ line on the chip ?

On OMAP, we have been passing that number down to twl4030 via 
platform_data, but it would be better to ask genirq to tell us which was 
the last irq number "claimed".

-- 
balbi

DefectiveByDesign.org


From linus.ml.walleij at gmail.com  Wed Jun  2 02:19:20 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Wed, 2 Jun 2010 08:19:20 +0200
Subject: Fwd: [RFC, PATCH 1/3] ARM: PL08X: Add PL08x AMBA DMA Controller 
	driver.
In-Reply-To: <AANLkTilXKWWvn6HLjfbcC0XFEn-Z7jSf4f6CKHBuW8Qb@mail.gmail.com>
References: <1227275251-12005-1-git-send-email-protected@arm.com>
	<1227275251-12005-2-git-send-email-protected@arm.com>
	<AANLkTilXKWWvn6HLjfbcC0XFEn-Z7jSf4f6CKHBuW8Qb@mail.gmail.com>
Message-ID: <AANLkTimoZRr5P_k4QH75upXAWRwkBKJjAfrStm5Znn5S@mail.gmail.com>

Oops this was onto the old list address, Peter is busy so does anybody
else know about
address boundaries in the RealViews?

Linus Walleij


---------- Forwarded message ----------
From: Linus Walleij <linus.ml.walleij at gmail.com>
Date: 2010/5/30
Subject: Re: [RFC, PATCH 1/3] ARM: PL08X: Add PL08x AMBA DMA Controller driver.
To: Peter Pearse <peter.pearse at arm.com>
Kopia: linux-arm-kernel <linux-arm-kernel at lists.arm.linux.org.uk>


Hi,

as you know I'm hacking around with this PL08x driver since the Versatile
support is in the way for getting my DMA work merged.

Now this piece I don't quite get:

2008/11/21 Peter Pearse <protected at arm.com>:


> +/*
> + * Return number of bytes to fill to boundary, or len
> + */
> +static int pl08x_pre_boundary(int addr, int len)
> +{
> + ? ? ? int boundary;
> +
> + ? ? ? if (len <= 0)
> + ? ? ? ? ? ? ? printk(KERN_ERR "PL08X::pre_boundary() - zero length\n");
> +
> + ? ? ? boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1) << PL08X_BOUNDARY_SHIFT;
> +
> + ? ? ? if (boundary < addr + len)
> + ? ? ? ? ? ? ? return boundary - addr;
> + ? ? ? else
> + ? ? ? ? ? ? ? return len;
> +}

This PL08X_BOUNDARY_SHIFT is defined to
#define PL08X_BOUNDARY_SHIFT ? ? ? ? ? (10) ? ?/* 1KB 0x400 */
#define PL08X_BOUNDARY_SIZE ? ? ? ? ? ?(1 << PL08X_BOUNDARY_SHIFT)

And then later:

> +/*
> + * Note that we assume we never have to change the burst sizes
> + */
> +int fill_LLIS_for_desc(struct pl08x_txd *local_txd, int pl08x_chan_num)
> +{
> (...)
> + ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ?* Make largest possible LLIs until less than one bus width left
> + ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? while (remainder > (mbus->buswidth - 1)) {
> + ? ? ? ? ? ? ? ? ? ? ? int lli_len, target_len;
> + ? ? ? ? ? ? ? ? ? ? ? int tsize;
> + ? ? ? ? ? ? ? ? ? ? ? int odd_bytes;
> + ? ? ? ? ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ? ? ? ? ?* If enough left try to send max possible,
> + ? ? ? ? ? ? ? ? ? ? ? ?* otherwise try to send the remainder
> + ? ? ? ? ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? ? ? ? ? target_len = remainder;
> + ? ? ? ? ? ? ? ? ? ? ? if (remainder > max_bytes_per_lli)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? target_len = max_bytes_per_lli;
> + ? ? ? ? ? ? ? ? ? ? ? /*
> + ? ? ? ? ? ? ? ? ? ? ? ?* ?Set bus lengths for incrementing busses
> + ? ? ? ? ? ? ? ? ? ? ? ?* ?to number of bytes which fill
> + ? ? ? ? ? ? ? ? ? ? ? ?* ?to next memory boundary
> + ? ? ? ? ? ? ? ? ? ? ? ?*/
> + ? ? ? ? ? ? ? ? ? ? ? if (cctl_parm.bits.si)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? local_txd->srcbus.fill_bytes
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = pl08x_pre_boundary(local_txd->srcbus.addr
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? , remainder);
> + ? ? ? ? ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? local_txd->srcbus.fill_bytes
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = max_bytes_per_lli;

Here the transfer lengths for lli:s crawls up tp a boundary.
Now, the DMAC PL08x cannot move past a 0x400 boundary on the RealViews,
so much is clear. But: is this a thing that will affect:

- All RealView / Versatile equipment
- All implementations of PL08x on all silicon
- All ARM architectures and nothing to do with the PL08x at all, rather
?with some AMBA stuff or so?

Yours,
Linus Walleij


From mcuos.com at gmail.com  Wed Jun  2 03:06:58 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Wed, 2 Jun 2010 15:06:58 +0800
Subject: [PATCH] NUC900/rtc: change the waiting for device ready implement
In-Reply-To: <20100601154324.f1273812.akpm@linux-foundation.org>
References: <4BFE1853.5070105@gmail.com>
	<20100601154324.f1273812.akpm@linux-foundation.org>
Message-ID: <AANLkTikkNZ9DkUUxm6eWTv-UY-Cfl7yT0XZHurMr5vb7@mail.gmail.com>

Hi Andrew ,

The patch makes two changes:
(1) it adds an mdelay(1) to the polling loop

Here I change the 'for' loop to 'while' loop and and add an mdelay(1),
which can make less access to the hardware register.

(2) it changes the return value from ENODEV to EPERM if the loop timed out.

I think the 'Operation not permitted' description is more suitable for
the meaning
of 'check_rtc_access_enable()' function, it just be used to judge rtc
access operation is permitted or not.



2010/6/2 Andrew Morton <akpm at linux-foundation.org>:
> On Thu, 27 May 2010 14:59:31 +0800
> Wan ZongShun <mcuos.com at gmail.com> wrote:
>
>> Dear Andrew,
>>
>> This patch is only to change the waiting for device ready implement
>> for winbond nuc900 platform.
>>
>
> It's not very helpful to only say "I changed it". ?_why_ did you change
> it? ?What change did you make? ?What was wrong with the old code and
> what's better about the new code?
>
>> --- a/drivers/rtc/rtc-nuc900.c
>> +++ b/drivers/rtc/rtc-nuc900.c
>> @@ -85,22 +85,21 @@ static irqreturn_t nuc900_rtc_interrupt(int irq, void *_rtc)
>>
>> ?static int *check_rtc_access_enable(struct nuc900_rtc *nuc900_rtc)
>> ?{
>> - ? ? unsigned int i;
>> + ? ? unsigned int i, timeout = 0x1000;
>> ? ? ? __raw_writel(INIRRESET, nuc900_rtc->rtc_reg + REG_RTC_INIR);
>>
>> ? ? ? mdelay(10);
>>
>> ? ? ? __raw_writel(AERPOWERON, nuc900_rtc->rtc_reg + REG_RTC_AER);
>>
>> - ? ? for (i = 0; i < 1000; i++) {
>> - ? ? ? ? ? ? if (__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB)
>> - ? ? ? ? ? ? ? ? ? ? return 0;
>> - ? ? }
>> + ? ? while (!(__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB)
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? && timeout--)
>> + ? ? ? ? ? ? mdelay(1);
>>
>> - ? ? if ((__raw_readl(nuc900_rtc->rtc_reg + REG_RTC_AER) & AERRWENB) == 0x0)
>> - ? ? ? ? ? ? return ERR_PTR(-ENODEV);
>> + ? ? if (!timeout)
>> + ? ? ? ? ? ? return ERR_PTR(-EPERM);
>>
>> - ? ? return ERR_PTR(-EPERM);
>> + ? ? return 0;
>> }
>
> I can see that the patch makes two changes: it adds an mdelay(1) to the
> polling loop and it changes the return value from ENODEV to EPERM if
> the loop timed out.
>
> But I don't have the faintest idea _why_ the changes were made!
>
>
> So. ?I merged the patch without a changelog. ?Please send a changelog
> for this patch which permits others to understand the change.
>
>



-- 
*linux-arm-kernel mailing list
mail addr:linux-arm-kernel at lists.infradead.org
you can subscribe by:
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

* linux-arm-NUC900 mailing list
mail addr:NUC900 at googlegroups.com
main web: https://groups.google.com/group/NUC900
you can subscribe it by sending me mail:
mcuos.com at gmail.com


From kgene.kim at samsung.com  Wed Jun  2 03:06:08 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed,  2 Jun 2010 16:06:08 +0900
Subject: [PATCH v2] ARM: S5PC100: Add Watchdog support for S5PC100
Message-ID: <1275462368-21621-1-git-send-email-kgene.kim@samsung.com>

From: Banajit Goswami <banajit.g at samsung.com>

This patch adds support for Watchdog timer for Samsung S5PC100.

Signed-off-by: Banajit Goswami <banajit.g at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
Changes since v1:
- Move the dependency of watchdog timer driver from MACH_XXX(board)
  to ARCH_XXX(SoC) as per comments from Ben Dooks

 arch/arm/Kconfig                         |    1 +
 arch/arm/mach-s5pc100/Kconfig            |    1 +
 arch/arm/mach-s5pc100/include/mach/map.h |    3 +++
 arch/arm/mach-s5pc100/mach-smdkc100.c    |    1 +
 4 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 40c90bd..47fb03e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -693,6 +693,7 @@ config ARCH_S5PC100
 	select CPU_V7
 	select ARM_L1_CACHE_SHIFT_6
 	select ARCH_USES_GETTIMEOFFSET
+	select HAVE_S3C2410_WATCHDOG
 	help
 	  Samsung S5PC100 series based systems
 
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b2a11df..56ebd3c 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -12,6 +12,7 @@ config CPU_S5PC100
 	select PLAT_S5P
 	select S5P_EXT_INT
 	select S3C_PL330_DMA
+	select S3C_DEV_WDT
 	help
 	  Enable S5PC100 CPU support
 
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index cadae43..4b3a7b7 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -72,6 +72,8 @@
 
 #define S5PC100_PA_SYSTIMER	(0xEA100000)
 
+#define S5PC100_PA_WATCHDOG	(0xEA200000)
+
 #define S5PC100_PA_UART		(0xEC000000)
 
 #define S5P_PA_UART0		(S5PC100_PA_UART + 0x0)
@@ -131,6 +133,7 @@
 #define S3C_PA_HSMMC2		S5PC100_PA_HSMMC(2)
 #define S3C_PA_KEYPAD		S5PC100_PA_KEYPAD
 #define S3C_PA_TSADC		S5PC100_PA_TSADC
+#define S3C_PA_WDT		S5PC100_PA_WATCHDOG
 #define S3C_PA_ONENAND		S5PC100_PA_ONENAND
 #define S3C_PA_ONENAND_BUF	S5PC100_PA_ONENAND_BUF
 #define S3C_SZ_ONENAND_BUF	S5PC100_SZ_ONENAND_BUF
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index af22f82..49c0270 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -159,6 +159,7 @@ static struct platform_device *smdkc100_devices[] __initdata = {
 	&smdkc100_lcd_powerdev,
 	&s5pc100_device_iis0,
 	&s5pc100_device_ac97,
+	&s3c_device_wdt,
 };
 
 static void __init smdkc100_map_io(void)
-- 
1.6.2.5



From kgene.kim at samsung.com  Wed Jun  2 03:05:37 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed,  2 Jun 2010 16:05:37 +0900
Subject: [PATCH] ARM: SAMSUNG: Reduce virtual memory size for WDT device
Message-ID: <1275462337-21587-1-git-send-email-kgene.kim@samsung.com>

From: Banajit Goswami <banajit.g at samsung.com>

This patch reduces the virtual memory allocated for WDT device from 1M
to 1K.

Signed-off-by: Banajit Goswami <banajit.g at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/plat-samsung/dev-wdt.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-samsung/dev-wdt.c b/arch/arm/plat-samsung/dev-wdt.c
index 5efca87..019b5b8 100644
--- a/arch/arm/plat-samsung/dev-wdt.c
+++ b/arch/arm/plat-samsung/dev-wdt.c
@@ -21,7 +21,7 @@
 static struct resource s3c_wdt_resource[] = {
 	[0] = {
 		.start	= S3C_PA_WDT,
-		.end	= S3C_PA_WDT + SZ_1M - 1,
+		.end	= S3C_PA_WDT + SZ_1K,
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-- 
1.6.2.5



From linus.ml.walleij at gmail.com  Wed Jun  2 03:16:18 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Wed, 2 Jun 2010 09:16:18 +0200
Subject: [PATCH 2/2] ARM: PL011 baudrate extension for ST-Ericssons 
	derivative
In-Reply-To: <20100601180944.GC6644@n2100.arm.linux.org.uk>
References: <1275385698-1599-1-git-send-email-linus.walleij@stericsson.com>
	<20100601180944.GC6644@n2100.arm.linux.org.uk>
Message-ID: <AANLkTikXGuRm_oUYof6DxWadBGQ8LZCD9rZ5TCW_VZxU@mail.gmail.com>

2010/6/1 Russell King - ARM Linux <linux at arm.linux.org.uk>:

> On Tue, Jun 01, 2010 at 11:48:18AM +0200, Linus Walleij wrote:
>> @@ -90,6 +92,7 @@ static struct vendor_data vendor_arm = {
>> ? ? ? .fifosize ? ? ? ? ? ? ? = 16,
>> ? ? ? .lcrh_tx ? ? ? ? ? ? ? ?= UART011_LCRH,
>> ? ? ? .lcrh_rx ? ? ? ? ? ? ? ?= UART011_LCRH,
>> + ? ? ? ?.oversampling ? ? ? ? ? ? ? ?= false,
>
> I assume these spaces rather than tabs are due to an editor error
> rather than an email client problem?

Yeah it was :-/

I've fixed it up and put the fixed versions in the patch tracker.

(Marcin I have some nice extensions to EMACS that check this as
you code, mail me if you want it.)

Yours,
Linus Walleij


From kgene.kim at samsung.com  Wed Jun  2 03:10:11 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed,  2 Jun 2010 16:10:11 +0900
Subject: [PATCH] ARM: SAMSUNG: Make WDT driver dependency SoC specific instead
	of machine specific
Message-ID: <1275462611-21657-1-git-send-email-kgene.kim@samsung.com>

From: Banajit Goswami <banajit.g at samsung.com>

This patch moves the dependency of watchdog timer driver from
MACH_XXX(board) to ARCH_XXX(SoC). This will enable all machines
using Samsung S3C64XX, S5P6440 and S5PV210/S5PC110 SoCs to use
the WDT driver by default.

Signed-off-by: Banajit Goswami <banajit.g at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/Kconfig              |    3 +++
 arch/arm/mach-s3c64xx/Kconfig |    1 -
 arch/arm/mach-s5p6440/Kconfig |    1 -
 arch/arm/mach-s5pv210/Kconfig |    2 --
 4 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..40c90bd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -663,6 +663,7 @@ config ARCH_S3C64XX
 	select S3C_DEV_NAND
 	select USB_ARCH_HAS_OHCI
 	select SAMSUNG_GPIOLIB_4BIT
+	select HAVE_S3C2410_WATCHDOG
 	help
 	  Samsung S3C64XX series based systems
 
@@ -672,6 +673,7 @@ config ARCH_S5P6440
 	select GENERIC_GPIO
 	select HAVE_CLK
 	select ARCH_USES_GETTIMEOFFSET
+	select HAVE_S3C2410_WATCHDOG
 	help
 	  Samsung S5P6440 CPU based systems
 
@@ -701,6 +703,7 @@ config ARCH_S5PV210
 	select HAVE_CLK
 	select ARM_L1_CACHE_SHIFT_6
 	select ARCH_USES_GETTIMEOFFSET
+	select HAVE_S3C2410_WATCHDOG
 	help
 	  Samsung S5PV210/S5PC110 series based systems
 
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index f5a5972..915cb47 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -100,7 +100,6 @@ config MACH_SMDK6410
 	select S3C_DEV_USB_HOST
 	select S3C_DEV_USB_HSOTG
 	select S3C_DEV_WDT
-	select HAVE_S3C2410_WATCHDOG
 	select S3C64XX_SETUP_SDHCI
 	select S3C64XX_SETUP_I2C1
 	select S3C64XX_SETUP_FB_24BPP
diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig
index f066fae..084c0bc 100644
--- a/arch/arm/mach-s5p6440/Kconfig
+++ b/arch/arm/mach-s5p6440/Kconfig
@@ -19,7 +19,6 @@ config MACH_SMDK6440
 	select SAMSUNG_DEV_TS
 	select SAMSUNG_DEV_ADC
 	select S3C_DEV_WDT
-	select HAVE_S3C2410_WATCHDOG
 	help
 	  Machine support for the Samsung SMDK6440
 
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0761eac..2e3ed18 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -74,7 +74,6 @@ config MACH_SMDKV210
 	select SAMSUNG_DEV_ADC
 	select SAMSUNG_DEV_TS
 	select S3C_DEV_WDT
-	select HAVE_S3C2410_WATCHDOG
 	help
 	  Machine support for Samsung SMDKV210
 
@@ -83,7 +82,6 @@ config MACH_SMDKC110
 	select CPU_S5PV210
 	select ARCH_SPARSEMEM_ENABLE
 	select S3C_DEV_WDT
-	select HAVE_S3C2410_WATCHDOG
 	help
 	  Machine support for Samsung SMDKC110
 	  S5PC110(MCP) is one of package option of S5PV210
-- 
1.6.2.5



From ben at trinity.fluff.org  Wed Jun  2 03:27:20 2010
From: ben at trinity.fluff.org (Ben Dooks)
Date: Wed, 2 Jun 2010 08:27:20 +0100
Subject: [PATCH] ARM: SAMSUNG: Reduce virtual memory size for WDT device
In-Reply-To: <1275462337-21587-1-git-send-email-kgene.kim@samsung.com>
References: <1275462337-21587-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <20100602072720.GD30276@trinity.fluff.org>

On Wed, Jun 02, 2010 at 04:05:37PM +0900, Kukjin Kim wrote:
> From: Banajit Goswami <banajit.g at samsung.com>
> 
> This patch reduces the virtual memory allocated for WDT device from 1M
> to 1K.
>
> Signed-off-by: Banajit Goswami <banajit.g at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
Acked-by: Ben Dooks <ben-linux at fluff.org>
> ---
>  arch/arm/plat-samsung/dev-wdt.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/plat-samsung/dev-wdt.c b/arch/arm/plat-samsung/dev-wdt.c
> index 5efca87..019b5b8 100644
> --- a/arch/arm/plat-samsung/dev-wdt.c
> +++ b/arch/arm/plat-samsung/dev-wdt.c
> @@ -21,7 +21,7 @@
>  static struct resource s3c_wdt_resource[] = {
>  	[0] = {
>  		.start	= S3C_PA_WDT,
> -		.end	= S3C_PA_WDT + SZ_1M - 1,
> +		.end	= S3C_PA_WDT + SZ_1K,
>  		.flags	= IORESOURCE_MEM,
>  	},
>  	[1] = {
> -- 
> 1.6.2.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From s.hauer at pengutronix.de  Wed Jun  2 03:36:50 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 2 Jun 2010 09:36:50 +0200
Subject: [PATCH 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <20100602073650.GK26820@pengutronix.de>

Hi Jason,

On Tue, Jun 01, 2010 at 11:10:41PM +0800, Jason Wang wrote:
> 3-stack is a reference board from Freescale for their i.MX51 SoC.
> 
> Add board definition, Kconfig and Makefile to enable Freescale 3-stack
> board.

The debug board code looks the same like in mach-mx31_3ds.c. Does
anybody know how similar the different debug boards for the 3ds boards
are? ATM we only have the mx31_3ds with debug board support in the
kernel. This could be the moment to go for a arch/arm/plat-mxc/3ds-debugboard.c

Several other comments inline.

> 
> Boot tested on a i.MX51 3-stack Rev2.0 board
> 
> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
> ---
>  arch/arm/mach-mx5/Kconfig                       |    5 +
>  arch/arm/mach-mx5/Makefile                      |    2 +-
>  arch/arm/mach-mx5/board-mx51_3ds.c              |  356 +++++++++++++++++++++++
>  arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   73 +++++
>  arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h |   43 +++
>  5 files changed, 478 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
>  create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
>  create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h
> 
> diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
> index 1576d51..6d45f44 100644
> --- a/arch/arm/mach-mx5/Kconfig
> +++ b/arch/arm/mach-mx5/Kconfig
> @@ -15,4 +15,9 @@ config MACH_MX51_BABBAGE
>  	  u-boot. This includes specific configurations for the board and its
>  	  peripherals.
>  
> +config MACH_MX51_3DS
> +	bool "Support MX51PDK (3DS)"
> +	help
> +	  Include support for MX51PDK (3DS) platform. This includes specific
> +	  configurations for the board and its peripherals.
>  endif
> diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
> index bf23f86..c757c59 100644
> --- a/arch/arm/mach-mx5/Makefile
> +++ b/arch/arm/mach-mx5/Makefile
> @@ -6,4 +6,4 @@
>  obj-y   := cpu.o mm.o clock-mx51.o devices.o
>  
>  obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
> -
> +obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
> diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
> new file mode 100644
> index 0000000..604fb26
> --- /dev/null
> +++ b/arch/arm/mach-mx5/board-mx51_3ds.c
> @@ -0,0 +1,356 @@
> +/*
> + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +#include <linux/smsc911x.h>
> +#include <linux/input/matrix_keypad.h>
> +
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/time.h>
> +
> +#include <mach/hardware.h>
> +#include <mach/common.h>
> +#include <mach/iomux-mx51-3ds.h>
> +#include <mach/board-mx51_3ds.h>
> +#include <mach/gpio.h>

linux/gpio.h instead

> +#include <mach/imx-uart.h>
> +
> +#include "devices.h"
> +
> +static struct pad_desc mx51_3ds_pads[] = {
> +	/* UART1 */
> +	MX51_3DS_PAD_UART1_RXD__UART1_RXD,
> +	MX51_3DS_PAD_UART1_TXD__UART1_TXD,
> +	MX51_3DS_PAD_UART1_RTS__UART1_RTS,
> +	MX51_3DS_PAD_UART1_CTS__UART1_CTS,
> +
> +	/* UART2 */
> +	MX51_3DS_PAD_UART2_RXD__UART2_RXD,
> +	MX51_3DS_PAD_UART2_TXD__UART2_TXD,
> +	MX51_3DS_PAD_EIM_D25__UART2_CTS,
> +	MX51_3DS_PAD_EIM_D26__UART2_RTS,
> +
> +	/* UART3 */
> +	MX51_3DS_PAD_GPIO_1_22__UART3_RXD,
> +	MX51_3DS_PAD_GPIO_1_23__UART3_TXD,
> +	MX51_3DS_PAD_EIM_D24__UART3_CTS,
> +	MX51_3DS_PAD_EIM_D27__UART3_RTS,
> +
> +	/* CPLD PARENT IRQ PIN */
> +	MX51_3DS_PAD_GPIO_1_6__GPIO1_6,
> +
> +	/* KPP */
> +	MX51_PAD_KEY_ROW0__KEY_ROW0,
> +	MX51_PAD_KEY_ROW1__KEY_ROW1,
> +	MX51_PAD_KEY_ROW2__KEY_ROW2,
> +	MX51_PAD_KEY_ROW3__KEY_ROW3,
> +	MX51_PAD_KEY_COL0__KEY_COL0,
> +	MX51_PAD_KEY_COL1__KEY_COL1,
> +	MX51_PAD_KEY_COL2__KEY_COL2,
> +	MX51_PAD_KEY_COL3__KEY_COL3,
> +	MX51_PAD_KEY_COL4__KEY_COL4,
> +	MX51_PAD_KEY_COL5__KEY_COL5,
> +};
> +
> +#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
> +static int mx51_3ds_board_keymap[] = {
> +	KEY(0, 0, KEY_1),
> +	KEY(0, 1, KEY_2),
> +	KEY(0, 2, KEY_3),
> +	KEY(0, 3, KEY_F1),
> +	KEY(0, 4, KEY_UP),
> +	KEY(0, 5, KEY_F2),
> +
> +	KEY(1, 0, KEY_4),
> +	KEY(1, 1, KEY_5),
> +	KEY(1, 2, KEY_6),
> +	KEY(1, 3, KEY_LEFT),
> +	KEY(1, 4, KEY_SELECT),
> +	KEY(1, 5, KEY_RIGHT),
> +
> +	KEY(2, 0, KEY_7),
> +	KEY(2, 1, KEY_8),
> +	KEY(2, 2, KEY_9),
> +	KEY(2, 3, KEY_F3),
> +	KEY(2, 4, KEY_DOWN),
> +	KEY(2, 5, KEY_F4),
> +
> +	KEY(3, 0, KEY_0),
> +	KEY(3, 1, KEY_OK),
> +	KEY(3, 2, KEY_ESC),
> +	KEY(3, 3, KEY_ENTER),
> +	KEY(3, 4, KEY_MENU),
> +	KEY(3, 5, KEY_BACK)
> +};
> +
> +static struct resource mx51_3ds_kpp_resources[] = {
> +	{
> +		.start = MX51_MXC_INT_KPP,
> +		.end = MX51_MXC_INT_KPP,
> +		.flags = IORESOURCE_IRQ,
> +	} , {
> +		.start = MX51_KPP_BASE_ADDR,
> +		.end = MX51_KPP_BASE_ADDR + 0x8 - 1,
> +		.flags = IORESOURCE_MEM,
> +	},
> +};
> +
> +static struct matrix_keymap_data mx51_3ds_map_data = {
> +	.keymap		= mx51_3ds_board_keymap,
> +	.keymap_size	= ARRAY_SIZE(mx51_3ds_board_keymap),
> +};
> +
> +static struct platform_device mx51_3ds_keypad_device = {
> +	.name = "imx-keypad",
> +	.id = 0,
> +	.num_resources = ARRAY_SIZE(mx51_3ds_kpp_resources),
> +	.resource = mx51_3ds_kpp_resources,
> +	.dev = {
> +		.platform_data = &mx51_3ds_map_data,
> +	},
> +};

The kpp device and resources should go into devices.[ch]

> +
> +static void mxc_init_keypad(void)
> +{
> +	(void)platform_device_register(&mx51_3ds_keypad_device);

No need for such (void) things.

> +}
> +#else
> +static inline void mxc_init_keypad(void)
> +{
> +}
> +#endif
> +
> +
> +static u32 cpld_base_addr;
> +
> +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
> +static struct resource smsc911x_resources[] = {
> +	{
> +		.flags = IORESOURCE_MEM,
> +	} , {
> +		.start = LAN9217_IRQ,
> +		.end = LAN9217_IRQ,
> +		.flags = IORESOURCE_IRQ,
> +	},
> +};
> +
> +struct smsc911x_platform_config smsc911x_config = {
> +	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
> +	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
> +};
> +
> +static struct platform_device smsc_lan9217_device = {
> +	.name = "smsc911x",
> +	.id = 0,
> +	.dev = {
> +		.platform_data = &smsc911x_config,
> +	},
> +	.num_resources = ARRAY_SIZE(smsc911x_resources),
> +	.resource = smsc911x_resources,
> +};
> +
> +static void mxc_init_enet(void)
> +{
> +	if (cpld_base_addr) {
> +		smsc_lan9217_device.resource[0].start =
> +		    LAN9217_BASE_ADDR(cpld_base_addr);
> +		smsc_lan9217_device.resource[0].end =
> +		    LAN9217_BASE_ADDR(cpld_base_addr) + 0x100;
> +		(void)platform_device_register(&smsc_lan9217_device);
> +	}

This looks overcomplicated. Why don't you declare the resources
statically as usual and call mxc_init_enet() only when the debug board
is detected?

> +}
> +#else
> +static inline void mxc_init_enet(void)
> +{
> +}
> +#endif
> +
> +static u32 brd_io;
> +static void expio_ack_irq(u32 irq);
> +
> +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
> +{
> +	u32 imr_val;
> +	u32 int_valid;
> +	u32 expio_irq;
> +
> +	desc->chip->mask(irq);	/* irq = gpio irq number */
> +
> +	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
> +	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
> +
> +	if (unlikely(!int_valid))
> +		goto out;

This is not needed since handled in the for loop below.

> +
> +	expio_irq = MXC_BOARD_IRQ_START;
> +	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
> +		struct irq_desc *d;
> +		if ((int_valid & 1) == 0)
> +			continue;
> +		d = irq_desc + expio_irq;
> +		if (unlikely(!(d->handle_irq))) {
> +			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
> +			BUG();	/* oops */

No need to crash the board just for an unhandled interrupt. Please
remove the BUG().

> +		}
> +		d->handle_irq(expio_irq, d);
> +	}
> +
> +out:
> +	desc->chip->ack(irq);
> +	desc->chip->unmask(irq);
> +}
> +
> +/*
> + * Disable an expio pin's interrupt by setting the bit in the imr.
> + * @param irq		an expio virtual irq number
> + */
> +static void expio_mask_irq(u32 irq)
> +{
> +	u16 reg;
> +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> +	/* mask the interrupt */

overcommenting. The name of the function already says it and the
function itself has an explanation aswell.

> +	reg = __raw_readw(brd_io + INTR_MASK_REG);
> +	reg |= (1 << expio);
> +	__raw_writew(reg, brd_io + INTR_MASK_REG);
> +}
> +
> +/*
> + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
> + * @param irq		an expanded io virtual irq number
> + */
> +static void expio_ack_irq(u32 irq)
> +{
> +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> +	/* clear the interrupt status */
> +	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
> +	__raw_writew(0, brd_io + INTR_RESET_REG);
> +	/* mask the interrupt */

dito

> +	expio_mask_irq(irq);
> +}
> +
> +/*
> + * Enable a expio pin's interrupt by clearing the bit in the imr.
> + * @param irq		a expio virtual irq number
> + */
> +static void expio_unmask_irq(u32 irq)
> +{
> +	u16 reg;
> +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> +	/* unmask the interrupt */
> +	reg = __raw_readw(brd_io + INTR_MASK_REG);
> +	reg &= ~(1 << expio);
> +	__raw_writew(reg, brd_io + INTR_MASK_REG);
> +}
> +
> +static struct irq_chip expio_irq_chip = {
> +	.ack = expio_ack_irq,
> +	.mask = expio_mask_irq,
> +	.unmask = expio_unmask_irq,
> +};
> +
> +static int __init mxc_expio_init(void)
> +{
> +	int i;
> +
> +	brd_io = (u32) ioremap(BOARD_IO_ADDR(MX51_CS5_BASE_ADDR), SZ_4K);

ioremap returns the correct type for what you need. brd_io should be
of type void __iomem *.

> +	if (brd_io == 0)
> +		return -ENOMEM;
> +
> +	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
> +	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
> +	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
> +		pr_info("3-Stack Debug board not detected\n");
> +		cpld_base_addr = 0;
> +		return -ENODEV;
> +	} else {
> +		cpld_base_addr = MX51_CS5_BASE_ADDR;
> +	}

the 'else' is unnecessary.

> +
> +	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
> +		readw(brd_io + CPLD_CODE_VER_REG));
> +
> +	/*
> +	 * Configure INT line as GPIO input
> +	 */
> +	gpio_request(MX51_3DS_CPLD_IRQ_PIN, "gpio1_6");
> +	gpio_direction_input(MX51_3DS_CPLD_IRQ_PIN);
> +
> +	/* disable the interrupt and clear the status */
> +	__raw_writew(0, brd_io + INTR_MASK_REG);
> +	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
> +	__raw_writew(0, brd_io + INTR_RESET_REG);
> +	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
> +	for (i = MXC_BOARD_IRQ_START;
> +	     i < (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS); i++) {

MXC_BOARD_IRQS is the maximum number of interrupts available for the
board. What you need here instead is the number of interrupts the expio
actually has.

> +		set_irq_chip(i, &expio_irq_chip);
> +		set_irq_handler(i, handle_level_irq);
> +		set_irq_flags(i, IRQF_VALID);
> +	}
> +	set_irq_type(EXPIO_PARENT_INT, IRQF_TRIGGER_LOW);
> +	set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler);
> +
> +	return 0;
> +}
> +
> +/* Serial ports */
> +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
> +static struct imxuart_platform_data uart_pdata = {
> +	.flags = IMXUART_HAVE_RTSCTS,
> +};
> +
> +static inline void mxc_init_imx_uart(void)
> +{
> +	mxc_register_device(&mxc_uart_device0, &uart_pdata);
> +	mxc_register_device(&mxc_uart_device1, &uart_pdata);
> +	mxc_register_device(&mxc_uart_device2, &uart_pdata);
> +}
> +#else /* !SERIAL_IMX */
> +static inline void mxc_init_imx_uart(void)
> +{
> +}
> +#endif /* SERIAL_IMX */
> +
> +/*
> + * Board specific initialization.
> + */
> +static void __init mxc_board_init(void)
> +{
> +	mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
> +					ARRAY_SIZE(mx51_3ds_pads));
> +	mxc_init_imx_uart();
> +	mxc_expio_init();
> +	mxc_init_enet();
> +	mxc_init_keypad();
> +}
> +
> +static void __init mx51_3ds_timer_init(void)
> +{
> +	mx51_clocks_init(32768, 24000000, 22579200, 24576000);
> +}
> +
> +static struct sys_timer mxc_timer = {
> +	.init	= mx51_3ds_timer_init,
> +};
> +
> +MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
> +	.phys_io = MX51_AIPS1_BASE_ADDR,
> +	.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
> +	.boot_params = PHYS_OFFSET + 0x100,
> +	.map_io = mx51_map_io,
> +	.init_irq = mx51_init_irq,
> +	.init_machine = mxc_board_init,
> +	.timer = &mxc_timer,
> +MACHINE_END
> diff --git a/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
> new file mode 100644
> index 0000000..6900a7f
> --- /dev/null
> +++ b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
> @@ -0,0 +1,73 @@
> +/*
> + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#ifndef __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
> +#define __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
> +
> +/*
> + * @file plat-mxc/include/mach/board-mx51_3ds.h
> + *
> + * @brief This file contains all the board level configuration options.
> + *
> + * It currently hold the options defined for MX51 3Stack Platform.
> + *
> + */
> +
> +#define MXC_LL_UART_PADDR	UART1_BASE_ADDR
> +#define MXC_LL_UART_VADDR	AIPS1_IO_ADDRESS(UART1_BASE_ADDR)

These are unused, please remove.

> +
> +#define DEBUG_BOARD_BASE_ADDRESS(n)	(n)

This does not make much sense. If anything then this define should
define the base address.

> +/* LAN9217 ethernet base address */
> +#define LAN9217_BASE_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n))
> +/* External UART */
> +#define UARTA_BASE_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n) + 0x8000)
> +#define UARTB_BASE_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n) + 0x10000)
> +
> +#define BOARD_IO_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n) + 0x20000)
> +/* LED switchs */
> +#define LED_SWITCH_REG		0x00
> +/* buttons */
> +#define SWITCH_BUTTONS_REG	0x08
> +/* status, interrupt */
> +#define INTR_STATUS_REG	0x10
> +#define INTR_MASK_REG		0x38
> +#define INTR_RESET_REG		0x20
> +/* magic word for debug CPLD */
> +#define MAGIC_NUMBER1_REG	0x40
> +#define MAGIC_NUMBER2_REG	0x48
> +/* CPLD code version */
> +#define CPLD_CODE_VER_REG	0x50
> +/* magic word for debug CPLD */
> +#define MAGIC_NUMBER3_REG	0x58
> +/* module reset register*/
> +#define MODULE_RESET_REG	0x60
> +/* CPU ID and Personality ID */
> +#define MCU_BOARD_ID_REG	0x68
> +
> +/* interrupts like external uart , external ethernet etc*/
> +#define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
> +
> +#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
> +
> +#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
> +#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
> +#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
> +#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
> +#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
> +
> +/* This is System IRQ used by LAN9217 */
> +#define LAN9217_IRQ	EXPIO_INT_ENET

Please use EXPIO_INT_ENET directly.

> +
> +/* Define CPLD interrupt pin */
> +#define MX51_3DS_CPLD_IRQ_PIN	(GPIO_PORTA + 6)
> +
> +#endif	/* __ASM_ARCH_MXC_BOARD_MX51_3DS_H__ */
> diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h b/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h
> new file mode 100644
> index 0000000..33f1141
> --- /dev/null
> +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright (C) 2010 Freescale Semiconductor, Inc.
> + * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +#ifndef __MACH_IOMUX_MX51_3DS_H__
> +#define __MACH_IOMUX_MX51_3DS_H__
> +
> +#include <mach/iomux-mx51.h>
> +
> +/* UART1 */
> +#define MX51_3DS_PAD_UART1_RXD__UART1_RXD	MX51_PAD_UART1_RXD__UART1_RXD
> +#define MX51_3DS_PAD_UART1_TXD__UART1_TXD	MX51_PAD_UART1_TXD__UART1_TXD
> +#define MX51_3DS_PAD_UART1_RTS__UART1_RTS	MX51_PAD_UART1_RTS__UART1_RTS
> +#define MX51_3DS_PAD_UART1_CTS__UART1_CTS	MX51_PAD_UART1_CTS__UART1_CTS
> +
> +/* UART2 */
> +#define MX51_3DS_PAD_UART2_RXD__UART2_RXD	MX51_PAD_UART2_RXD__UART2_RXD
> +#define MX51_3DS_PAD_UART2_TXD__UART2_TXD	MX51_PAD_UART2_TXD__UART2_TXD
> +#define MX51_3DS_PAD_EIM_D25__UART2_CTS		IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT4, 0x0, 0, \
> +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> +#define MX51_3DS_PAD_EIM_D26__UART2_RTS		IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT4, 0x9e8, 3, \
> +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> +
> +/* UART3 */
> +#define MX51_3DS_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, \
> +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> +#define MX51_3DS_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, \
> +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> +#define MX51_3DS_PAD_EIM_D24__UART3_CTS		IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, \
> +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> +#define MX51_3DS_PAD_EIM_D27__UART3_RTS		IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 3, \
> +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> +/* CPLD */
> +#define MX51_3DS_PAD_GPIO_1_6__GPIO1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)

Please remove this whole file. Use the MX51_PAD_* defines directly where
appropriate and add the missing entries to iomux-mx51.h.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Jun  2 03:43:58 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 2 Jun 2010 09:43:58 +0200
Subject: [PATCH 3/3] mx51/clock: add keypad clock definition and
	registration
In-Reply-To: <1275405043-18230-4-git-send-email-jason77.wang@gmail.com>
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-3-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-4-git-send-email-jason77.wang@gmail.com>
Message-ID: <20100602074358.GL26820@pengutronix.de>

On Tue, Jun 01, 2010 at 11:10:43PM +0800, Jason Wang wrote:
> On i.MX51 platforms, the keypad controller has no gate clock, to
> meet the imx keypad driver requirement, we add a empty definition and
> register it. Now the keypad driver can work.
> 
> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
> ---
>  arch/arm/mach-mx5/clock-mx51.c |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
> index d9f612d..e89b93a 100644
> --- a/arch/arm/mach-mx5/clock-mx51.c
> +++ b/arch/arm/mach-mx5/clock-mx51.c
> @@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
>  	.parent = &ckil_clk,
>  };
>  
> +static struct clk kpp_clk = {
> +	.id = 0,
> +};
> +
>  #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
>  	static struct clk name = {			\
>  		.id		= i,			\
> @@ -821,6 +825,7 @@ static struct clk_lookup lookups[] = {
>  	_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
>  	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
>  	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
> +	_REGISTER_CLOCK(NULL, "kpp", kpp_clk)

_REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)

(or imx-keypad.0 depending on what id the kpp platform_device has)

SAscha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From grinberg at compulab.co.il  Wed Jun  2 03:40:45 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed,  2 Jun 2010 10:40:45 +0300
Subject: [PATCH 0/5] Enable pxa310 usb otg port host mode.
Message-ID: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>

This patch series extends the existing usb ulpi generic driver
with support for Function and Interface control of the ULPI PHYs,
adds support for SMSC USB3319 ulpi phy,
implement the pxa310 specific ulpi functionality and make pxa specific ohci
implementation aware of pxa310 usb otg port host mode.

Igor Grinberg (5):
  usb/otg/ulpi: extend the generic ulpi driver.
  usb/otg/ulpi: add support for SMSC USB3319 ulpi phy.
  [ARM] pxa: add PXA310 specific ULPI implementation
  [ARM] usb/host/ohci-pxa27x: make PXA310 USB OTG port work in host
    mode.
  [ARM] pxa/cm-x300: enable USB host port 2 on CM-X300 with PXA310 cpu.

 arch/arm/mach-mx2/mach-pca100.c              |   10 +-
 arch/arm/mach-mx3/mach-armadillo5x0.c        |   10 +-
 arch/arm/mach-mx3/mach-mx31lite.c            |    5 +-
 arch/arm/mach-mx3/mach-mx31moboard.c         |    5 +-
 arch/arm/mach-mx3/mach-pcm037.c              |   10 +-
 arch/arm/mach-mx3/mach-pcm043.c              |    5 +-
 arch/arm/mach-pxa/Kconfig                    |    4 +
 arch/arm/mach-pxa/Makefile                   |    1 +
 arch/arm/mach-pxa/cm-x300.c                  |  102 ++++++++++++++
 arch/arm/mach-pxa/include/mach/ohci.h        |    3 +
 arch/arm/mach-pxa/include/mach/pxa310-ulpi.h |   19 +++
 arch/arm/mach-pxa/include/mach/regs-u2d.h    |    2 +
 arch/arm/mach-pxa/pxa310-ulpi.c              |  110 +++++++++++++++
 drivers/usb/host/ohci-pxa27x.c               |  183 ++++++++++++++++++++++++++
 drivers/usb/otg/Kconfig                      |    2 -
 drivers/usb/otg/ulpi.c                       |   65 ++++++++-
 include/linux/usb/ulpi.h                     |   25 ++++-
 17 files changed, 542 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/mach-pxa/include/mach/pxa310-ulpi.h
 create mode 100644 arch/arm/mach-pxa/pxa310-ulpi.c



From grinberg at compulab.co.il  Wed Jun  2 03:40:47 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed,  2 Jun 2010 10:40:47 +0300
Subject: [PATCH 2/5] usb/otg/ulpi: add support for SMSC USB3319 ulpi phy.
In-Reply-To: <1275464450-23003-2-git-send-email-grinberg@compulab.co.il>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-2-git-send-email-grinberg@compulab.co.il>
Message-ID: <1275464450-23003-3-git-send-email-grinberg@compulab.co.il>


Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
Signed-off-by: Mike Rapoport <mike at compulab.co.il>
---
 drivers/usb/otg/ulpi.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/otg/ulpi.c b/drivers/usb/otg/ulpi.c
index 0e7a826..99756ab 100644
--- a/drivers/usb/otg/ulpi.c
+++ b/drivers/usb/otg/ulpi.c
@@ -59,6 +59,7 @@
 /* ULPI hardcoded IDs, used for probing */
 static unsigned int ulpi_ids[] = {
 	ULPI_ID(0x04cc, 0x1504),	/* NXP ISP1504 */
+	ULPI_ID(0x0424, 0x0006),        /* SMSC USB3319 */
 };
 
 static int ulpi_set_otg_flags(struct otg_transceiver *otg)
-- 
1.6.4.4



From grinberg at compulab.co.il  Wed Jun  2 03:40:46 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed,  2 Jun 2010 10:40:46 +0300
Subject: [PATCH 1/5] usb/otg/ulpi: extend the generic ulpi driver.
In-Reply-To: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <1275464450-23003-2-git-send-email-grinberg@compulab.co.il>

This patch extends the generic ulpi driver with support for
Function and Interface control of upli phy.

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
Signed-off-by: Mike Rapoport <mike at compulab.co.il>
---
 arch/arm/mach-mx2/mach-pca100.c       |   10 ++++-
 arch/arm/mach-mx3/mach-armadillo5x0.c |   10 ++++-
 arch/arm/mach-mx3/mach-mx31lite.c     |    5 ++-
 arch/arm/mach-mx3/mach-mx31moboard.c  |    5 ++-
 arch/arm/mach-mx3/mach-pcm037.c       |   10 ++++-
 arch/arm/mach-mx3/mach-pcm043.c       |    5 ++-
 drivers/usb/otg/Kconfig               |    2 -
 drivers/usb/otg/ulpi.c                |   64 +++++++++++++++++++++++++++++----
 include/linux/usb/ulpi.h              |   25 ++++++++++++-
 9 files changed, 117 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c
index 778fff2..0f2ece0 100644
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-mx2/mach-pca100.c
@@ -356,13 +356,19 @@ static void __init pca100_init(void)
 #if defined(CONFIG_USB_ULPI)
 	if (otg_mode_host) {
 		otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+						USB_OTG_DRV_VBUS |
+						USB_OTG_DRV_VBUS_EXT,
+						ULPI_IC_DEFAULT,
+						ULPI_FC_DEFAULT);
 
 		mxc_register_device(&mxc_otg_host, &otg_pdata);
 	}
 
 	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+					  USB_OTG_DRV_VBUS |
+					  USB_OTG_DRV_VBUS_EXT,
+					  ULPI_IC_DEFAULT,
+					  ULPI_FC_DEFAULT);
 
 	mxc_register_device(&mxc_usbh2, &usbh2_pdata);
 #endif
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 5f72ec9..81904d4 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -552,9 +552,15 @@ static void __init armadillo5x0_init(void)
 	/* USB */
 #if defined(CONFIG_USB_ULPI)
 	usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-			USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+					   USB_OTG_DRV_VBUS |
+					   USB_OTG_DRV_VBUS_EXT,
+					   ULPI_IC_DEFAULT,
+					   ULPI_FC_DEFAULT);
 	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-			USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+					  USB_OTG_DRV_VBUS |
+					  USB_OTG_DRV_VBUS_EXT,
+					  ULPI_IC_DEFAULT,
+					  ULPI_FC_DEFAULT);
 
 	mxc_register_device(&mxc_otg_host, &usbotg_pdata);
 	mxc_register_device(&mxc_usbh2, &usbh2_pdata);
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 2b6d114..9413be4 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -261,7 +261,10 @@ static void __init mxc_board_init(void)
 #if defined(CONFIG_USB_ULPI)
 	/* USB */
 	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+					  USB_OTG_DRV_VBUS |
+					  USB_OTG_DRV_VBUS_EXT,
+					  ULPI_IC_DEFAULT,
+					  ULPI_FC_DEFAULT);
 
 	mxc_register_device(&mxc_usbh2, &usbh2_pdata);
 #endif
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index fccb920..620f21a 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -391,7 +391,10 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
 static int __init moboard_usbh2_init(void)
 {
 	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-			USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+					  USB_OTG_DRV_VBUS |
+					  USB_OTG_DRV_VBUS_EXT,
+					  ULPI_IC_DEFAULT,
+					  ULPI_FC_DEFAULT);
 
 	return mxc_register_device(&mxc_usbh2, &usbh2_pdata);
 }
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 2df1ec5..33471c4 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -657,13 +657,19 @@ static void __init mxc_board_init(void)
 #if defined(CONFIG_USB_ULPI)
 	if (otg_mode_host) {
 		otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+						USB_OTG_DRV_VBUS |
+						USB_OTG_DRV_VBUS_EXT,
+						ULPI_IC_DEFAULT,
+						ULPI_FC_DEFAULT);
 
 		mxc_register_device(&mxc_otg_host, &otg_pdata);
 	}
 
 	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+					  USB_OTG_DRV_VBUS |
+					  USB_OTG_DRV_VBUS_EXT,
+					  ULPI_IC_DEFAULT,
+					  ULPI_FC_DEFAULT);
 
 	mxc_register_device(&mxc_usbh2, &usbh2_pdata);
 #endif
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 1bf1ec2..63d8719 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -379,7 +379,10 @@ static void __init mxc_board_init(void)
 #if defined(CONFIG_USB_ULPI)
 	if (otg_mode_host) {
 		otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+						USB_OTG_DRV_VBUS |
+						USB_OTG_DRV_VBUS_EXT,
+						ULPI_IC_DEFAULT,
+						ULPI_FC_DEFAULT);
 
 		mxc_register_device(&mxc_otg_host, &otg_pdata);
 	}
diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
index 3d2d3e5..3b12895 100644
--- a/drivers/usb/otg/Kconfig
+++ b/drivers/usb/otg/Kconfig
@@ -49,8 +49,6 @@ config USB_ULPI
 	  Enable this to support ULPI connected USB OTG transceivers which
 	  are likely found on embedded boards.
 
-	  The only chip currently supported is NXP's ISP1504
-
 config TWL4030_USB
 	tristate "TWL4030 USB Transceiver Driver"
 	depends on TWL4030_CORE && REGULATOR_TWL4030
diff --git a/drivers/usb/otg/ulpi.c b/drivers/usb/otg/ulpi.c
index 9010225..0e7a826 100644
--- a/drivers/usb/otg/ulpi.c
+++ b/drivers/usb/otg/ulpi.c
@@ -34,6 +34,7 @@
 #define ULPI_VID_HIGH        0x01    /* Vendor ID high */
 #define ULPI_PID_LOW         0x02    /* Product ID low */
 #define ULPI_PID_HIGH        0x03    /* Product ID high */
+#define ULPI_FUNCTL          0x04    /* Function Control */
 #define ULPI_ITFCTL          0x07    /* Interface Control */
 #define ULPI_OTGCTL          0x0A    /* OTG Control */
 
@@ -60,25 +61,51 @@ static unsigned int ulpi_ids[] = {
 	ULPI_ID(0x04cc, 0x1504),	/* NXP ISP1504 */
 };
 
-static int ulpi_set_flags(struct otg_transceiver *otg)
+static int ulpi_set_otg_flags(struct otg_transceiver *otg)
 {
+	unsigned int otg_flags = otg->flags & 0xff;
 	unsigned int flags = 0;
 
-	if (otg->flags & USB_OTG_PULLUP_ID)
+	if (otg_flags & USB_OTG_PULLUP_ID)
 		flags |= ID_PULL_UP;
 
-	if (otg->flags & USB_OTG_PULLDOWN_DM)
+	if (otg_flags & USB_OTG_PULLDOWN_DM)
 		flags |= DM_PULL_DOWN;
 
-	if (otg->flags & USB_OTG_PULLDOWN_DP)
+	if (otg_flags & USB_OTG_PULLDOWN_DP)
 		flags |= DP_PULL_DOWN;
 
-	if (otg->flags & USB_OTG_EXT_VBUS_INDICATOR)
+	if (otg_flags & USB_OTG_EXT_VBUS_INDICATOR)
 		flags |= USE_EXT_VBUS_IND;
 
 	return otg_io_write(otg, flags, ULPI_OTGCTL + ULPI_REG_SET);
 }
 
+static int ulpi_set_fc_flags(struct otg_transceiver *otg)
+{
+	unsigned int fc_flags = (otg->flags >> 16) & 0xff;
+
+	/*
+	 * Bit 6 in Function Control Register is SuspendM
+	 * 1 - Powered.
+	 * 0 - Suspend.
+	 */
+	fc_flags |= (1 << 6);
+
+	return otg_io_write(otg, fc_flags, ULPI_FUNCTL + ULPI_REG_SET);
+}
+
+static inline int ulpi_set_flags(struct otg_transceiver *otg)
+{
+	int ret;
+
+	ret = ulpi_set_otg_flags(otg);
+	if (ret)
+		return ret;
+
+	return ulpi_set_fc_flags(otg);
+}
+
 static int ulpi_init(struct otg_transceiver *otg)
 {
 	int i, vid, pid;
@@ -98,6 +125,28 @@ static int ulpi_init(struct otg_transceiver *otg)
 	return -ENODEV;
 }
 
+static int ulpi_set_host(struct otg_transceiver *otg, struct usb_bus *host)
+{
+	unsigned int ic_flags = (otg->flags >> 8) & 0xff;
+	unsigned int ic = ic_flags & ~0x7;
+
+	if (!host) {
+		otg->host = NULL;
+		return 0;
+	}
+
+	otg->host = host;
+
+	if (ic_flags & ULPI_IC_3PIN)
+		ic |= ULPI_IC_3PIN;
+	else if (ic_flags & ULPI_IC_CARKIT)
+		ic |= ULPI_IC_CARKIT;
+	else
+		ic |= ULPI_IC_6PIN;
+
+	return otg_io_write(otg, ic, ULPI_ITFCTL + ULPI_REG_SET);
+}
+
 static int ulpi_set_vbus(struct otg_transceiver *otg, bool on)
 {
 	unsigned int flags = otg_io_read(otg, ULPI_OTGCTL);
@@ -117,7 +166,7 @@ static int ulpi_set_vbus(struct otg_transceiver *otg, bool on)
 
 struct otg_transceiver *
 otg_ulpi_create(struct otg_io_access_ops *ops,
-		unsigned int flags)
+		u8 otg_flags, u8 ic_flags, u8 fc_flags)
 {
 	struct otg_transceiver *otg;
 
@@ -126,9 +175,10 @@ otg_ulpi_create(struct otg_io_access_ops *ops,
 		return NULL;
 
 	otg->label	= "ULPI";
-	otg->flags	= flags;
+	otg->flags	= otg_flags | (ic_flags << 8) | (fc_flags << 16);
 	otg->io_ops	= ops;
 	otg->init	= ulpi_init;
+	otg->set_host	= ulpi_set_host;
 	otg->set_vbus	= ulpi_set_vbus;
 
 	return otg;
diff --git a/include/linux/usb/ulpi.h b/include/linux/usb/ulpi.h
index 20675c6..8318067 100644
--- a/include/linux/usb/ulpi.h
+++ b/include/linux/usb/ulpi.h
@@ -1,7 +1,30 @@
 #ifndef __LINUX_USB_ULPI_H
 #define __LINUX_USB_ULPI_H
 
+/* ULPI Function Control Register bits */
+#define ULPI_FC_HS	0		/* Enable HS tcvr */
+#define ULPI_FC_FS	(0x1 << 0)	/* Enable FS tcvr */
+#define ULPI_FC_LS	(0x2 << 0)	/* Enable LS tcvr */
+#define ULPI_FC_FS_LS	(0x3 << 0)	/* Enable FS tcvr for LS packets */
+#define ULPI_FC_TRM_SEL	(0x1 << 2)	/* Internal pullup and HS termination */
+#define ULPI_FC_NODRV	(0x1 << 3)	/* Non-Driving Operation */
+#define ULPI_FC_NONRZI	(0x1 << 4)	/* Disable bit-stuff and NRZI encode */
+#define ULPI_FC_RESET	(0x1 << 5)	/* Reset the UTMI core */
+#define ULPI_FC_DEFAULT	0x41		/* Function Control Register Default */
+
+
+/* ULPI Interface Register bits */
+#define ULPI_IC_6PIN	(1 << 0)	/* XCVR 6 serial pin mode */
+#define ULPI_IC_3PIN	(1 << 1)	/* XCVR 3 serial pin mode */
+#define ULPI_IC_CARKIT	(1 << 2)	/* Carkit mode */
+#define ULPI_IC_CLKSPND	(1 << 3)	/* Active low clock suspend */
+#define ULPI_IC_AUTORES	(1 << 4)	/* PHY auto transmit resume signal */
+#define ULPI_IC_VBUSINV	(1 << 5)	/* Invert the external VBUS indicator */
+#define ULPI_IC_INDPT	(1 << 6)	/* Indicator Pass Through */
+#define ULPI_IC_DISPRT	(1 << 7)	/* Interface Protect Disable */
+#define ULPI_IC_DEFAULT	0x0		/* Interface Control Register Default */
+
 struct otg_transceiver *otg_ulpi_create(struct otg_io_access_ops *ops,
-					unsigned int flags);
+					u8 fc_flags, u8 ic_flags, u8 otg_flags);
 
 #endif /* __LINUX_USB_ULPI_H */
-- 
1.6.4.4



From grinberg at compulab.co.il  Wed Jun  2 03:40:49 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed,  2 Jun 2010 10:40:49 +0300
Subject: [PATCH 4/5] [ARM] usb/host/ohci-pxa27x: make PXA310 USB OTG port work
	in host mode.
In-Reply-To: <1275464450-23003-4-git-send-email-grinberg@compulab.co.il>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-2-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-3-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-4-git-send-email-grinberg@compulab.co.il>
Message-ID: <1275464450-23003-5-git-send-email-grinberg@compulab.co.il>


Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
Signed-off-by: Mike Rapoport <mike at compulab.co.il>
---
 arch/arm/mach-pxa/include/mach/ohci.h     |    3 +
 arch/arm/mach-pxa/include/mach/regs-u2d.h |    2 +
 drivers/usb/host/ohci-pxa27x.c            |  183 +++++++++++++++++++++++++++++
 3 files changed, 188 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/ohci.h b/arch/arm/mach-pxa/include/mach/ohci.h
index 95b6e2a..a543d0f 100644
--- a/arch/arm/mach-pxa/include/mach/ohci.h
+++ b/arch/arm/mach-pxa/include/mach/ohci.h
@@ -29,6 +29,9 @@ struct pxaohci_platform_data {
 #define PMM_PERPORT_MODE       3
 
 	int power_budget;
+
+	struct otg_transceiver *otg;
+	unsigned long ulpi_mode;
 };
 
 extern void pxa_set_ohci_info(struct pxaohci_platform_data *info);
diff --git a/arch/arm/mach-pxa/include/mach/regs-u2d.h b/arch/arm/mach-pxa/include/mach/regs-u2d.h
index c15c0c5..82597e7 100644
--- a/arch/arm/mach-pxa/include/mach/regs-u2d.h
+++ b/arch/arm/mach-pxa/include/mach/regs-u2d.h
@@ -3,6 +3,8 @@
 
 #include <mach/bitfield.h>
 
+#define U2D_PHYS_BASE   0x54100000
+
 /*
  * USB2 device controller registers and bits definitions
  */
diff --git a/drivers/usb/host/ohci-pxa27x.c b/drivers/usb/host/ohci-pxa27x.c
index a18debd..c4aa239 100644
--- a/drivers/usb/host/ohci-pxa27x.c
+++ b/drivers/usb/host/ohci-pxa27x.c
@@ -24,6 +24,8 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <mach/ohci.h>
+#include <mach/regs-u2d.h>
+#include <mach/pxa310-ulpi.h>
 
 /*
  * UHC: USB Host Controller (OHCI-like) register definitions
@@ -104,10 +106,126 @@ struct pxa27x_ohci {
 	struct device	*dev;
 	struct clk	*clk;
 	void __iomem	*mmio_base;
+
+	struct clk	*u2d_clk;
+	void __iomem	*u2d_mmio_base;
 };
 
 #define to_pxa27x_ohci(hcd)	(struct pxa27x_ohci *)hcd_to_ohci(hcd)
 
+#if defined(CONFIG_PXA310_ULPI)
+static void pxa310_setup_otg_hc(struct pxa27x_ohci *ohci)
+{
+	void __iomem *u2d_mmio_base = ohci->u2d_mmio_base;
+	u32 u2dotgcr;
+
+	u2dotgcr = __raw_readl(u2d_mmio_base + U2DOTGCR);
+	u2dotgcr |= U2DOTGCR_ULAF | U2DOTGCR_UTMID;
+	u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
+	__raw_writel(u2dotgcr, u2d_mmio_base + U2DOTGCR);
+	msleep(5);
+	__raw_writel(u2dotgcr | U2DOTGCR_ULE, u2d_mmio_base + U2DOTGCR);
+	msleep(5);
+	__raw_writel(__raw_readl(u2d_mmio_base + U2DOTGICR) & ~0x37F7F,
+		     u2d_mmio_base + U2DOTGICR);
+}
+
+static void pxa310_otg_transceiver_rtsm(struct pxa27x_ohci *ohci)
+{
+	void __iomem *u2d_mmio_base = ohci->u2d_mmio_base;
+	u32 u2dotgcr;
+
+	/* put PHY to sync mode */
+	u2dotgcr = __raw_readl(u2d_mmio_base + U2DOTGCR);
+	u2dotgcr |=  U2DOTGCR_RTSM | U2DOTGCR_UTMID;
+	__raw_writel(u2dotgcr, u2d_mmio_base + U2DOTGCR);
+	msleep(10);
+	/* setup OTG sync mode */
+	u2dotgcr = __raw_readl(u2d_mmio_base + U2DOTGCR);
+	u2dotgcr |= U2DOTGCR_ULAF;
+	u2dotgcr &= ~(U2DOTGCR_SMAF | U2DOTGCR_CKAF);
+	__raw_writel(u2dotgcr, u2d_mmio_base + U2DOTGCR);
+}
+
+static int start_otg_transceiver(struct pxa27x_ohci *ohci,
+				 struct otg_transceiver *otg)
+{
+	int err;
+
+	err = otg_init(otg);
+	if (err) {
+		pr_err("OTG transceiver init failed");
+		return err;
+	}
+
+	err = otg_set_vbus(otg, 1);
+	if (err) {
+		pr_err("OTG transceiver VBUS set failed");
+		return err;
+	}
+
+	err = otg_set_host(otg, &ohci_to_hcd(&ohci->ohci)->self);
+	if (err)
+		pr_err("OTG transceiver Host mode set failed");
+
+	return err;
+}
+
+static int pxa310_start_otg_hc(struct pxa27x_ohci *ohci,
+			       struct pxaohci_platform_data *inf)
+{
+	void __iomem *u2d_mmio_base = ohci->u2d_mmio_base;
+	u32 u2dotgcr;
+	int err;
+
+	pxa310_otg_transceiver_rtsm(ohci);
+
+	/* disable USB device controller */
+	__raw_writel(__raw_readl(u2d_mmio_base + U2DCR) & ~U2DCR_UDE,
+		     u2d_mmio_base + U2DCR);
+	__raw_writel(__raw_readl(u2d_mmio_base + U2DOTGCR) |
+		     U2DOTGCR_UTMID, u2d_mmio_base + U2DOTGCR);
+	__raw_writel(__raw_readl(u2d_mmio_base + U2DOTGICR) & ~0x37F7F,
+		     u2d_mmio_base + U2DOTGICR);
+
+	err = start_otg_transceiver(ohci, inf->otg);
+	if (err)
+		return err;
+
+	/* set xceiver mode */
+	if (inf->ulpi_mode == ULPI_IC_6PIN)
+		__raw_writel(__raw_readl(u2d_mmio_base + U2DP3CR) &
+			     ~U2DP3CR_P2SS, u2d_mmio_base + U2DP3CR);
+	else if (inf->ulpi_mode == ULPI_IC_3PIN)
+		__raw_writel(__raw_readl(u2d_mmio_base + U2DP3CR) |
+			     U2DP3CR_P2SS, u2d_mmio_base + U2DP3CR);
+
+	/* start OTG host controller */
+	u2dotgcr =__raw_readl(u2d_mmio_base + U2DOTGCR) | U2DOTGCR_SMAF;
+	__raw_writel(u2dotgcr & ~(U2DOTGCR_ULAF | U2DOTGCR_CKAF),
+		     u2d_mmio_base + U2DOTGCR);
+
+	return 0;
+}
+
+static inline bool pxa310_u2d_is_setup(struct pxa27x_ohci *ohci)
+{
+	return cpu_is_pxa310() && !IS_ERR(ohci->u2d_clk) && ohci->u2d_mmio_base;
+}
+#else
+static inline void pxa310_setup_otg_hc(struct pxa27x_ohci *ohci) {}
+static inline void pxa310_otg_transceiver_rtsm(struct pxa27x_ohci *ohci) {}
+static inline int pxa310_start_otg_hc(struct pxa27x_ohci *ohci,
+				      struct pxaohci_platform_data *inf)
+{
+	return 0;
+}
+static inline bool pxa310_u2d_is_setup(struct pxa27x_ohci *ohci)
+{
+	return false;
+}
+#endif /* CONFIG_PXA310_ULPI */
+
 /*
   PMM_NPS_MODE -- PMM Non-power switching mode
       Ports are powered continuously.
@@ -229,12 +347,24 @@ static int pxa27x_start_hc(struct pxa27x_ohci *ohci, struct device *dev)
 
 	pxa27x_setup_hc(ohci, inf);
 
+	if (pxa310_u2d_is_setup(ohci)) {
+		clk_enable(ohci->u2d_clk);
+		pxa310_setup_otg_hc(ohci);
+	}
+
 	if (inf->init)
 		retval = inf->init(dev);
 
 	if (retval < 0)
 		return retval;
 
+	/*
+	 * Platform can have a special init for the ulpi phy,
+	 * therefore the rest of the init must be done after the platform code.
+	 */
+	if (pxa310_u2d_is_setup(ohci))
+		pxa310_start_otg_hc(ohci, inf);
+
 	uhchr = __raw_readl(ohci->mmio_base + UHCHR) & ~UHCHR_SSE;
 	__raw_writel(uhchr, ohci->mmio_base + UHCHR);
 	__raw_writel(UHCHIE_UPRIE | UHCHIE_RWIE, ohci->mmio_base + UHCHIE);
@@ -251,6 +381,11 @@ static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
 
 	inf = dev->platform_data;
 
+	if (pxa310_u2d_is_setup(ohci)) {
+		pxa310_otg_transceiver_rtsm(ohci);
+		clk_disable(ohci->u2d_clk);
+	}
+
 	if (inf->exit)
 		inf->exit(dev);
 
@@ -264,6 +399,38 @@ static void pxa27x_stop_hc(struct pxa27x_ohci *ohci, struct device *dev)
 	clk_disable(ohci->clk);
 }
 
+static int pxa310_init_otg_resources(struct pxa27x_ohci *ohci,
+				     struct pxaohci_platform_data *inf)
+{
+	int retval;
+
+	ohci->u2d_clk = clk_get(NULL, "U2DCLK");
+	if (IS_ERR(ohci->u2d_clk))
+		return PTR_ERR(ohci->u2d_clk);
+
+	inf->otg->io_priv = ioremap(U2D_PHYS_BASE, 0x1300);
+	if (!inf->otg->io_priv) {
+		retval = -ENOMEM;
+		goto err_ioremap;
+	}
+
+	ohci->u2d_mmio_base = inf->otg->io_priv;
+
+	return 0;
+
+err_ioremap:
+	clk_put(ohci->u2d_clk);
+	return retval;
+}
+
+static void pxa310_free_otg_resources(struct pxa27x_ohci *ohci)
+{
+	if (ohci->u2d_mmio_base)
+		iounmap(ohci->u2d_mmio_base);
+
+	if (ohci->u2d_clk)
+		clk_put(ohci->u2d_clk);
+}
 
 /*-------------------------------------------------------------------------*/
 
@@ -337,6 +504,12 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
 	ohci->clk = usb_clk;
 	ohci->mmio_base = (void __iomem *)hcd->regs;
 
+	if (cpu_is_pxa310() && inf->otg) {
+		retval = pxa310_init_otg_resources(ohci, inf);
+		if (retval)
+			goto err3;
+	}
+
 	if ((retval = pxa27x_start_hc(ohci, &pdev->dev)) < 0) {
 		pr_debug("pxa27x_start_hc failed");
 		goto err3;
@@ -357,11 +530,15 @@ int usb_hcd_pxa27x_probe (const struct hc_driver *driver, struct platform_device
 	pxa27x_stop_hc(ohci, &pdev->dev);
  err3:
 	iounmap(hcd->regs);
+
+	if (cpu_is_pxa310() && inf->otg)
+		pxa310_free_otg_resources(ohci);
  err2:
 	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
  err1:
 	usb_put_hcd(hcd);
 	clk_put(usb_clk);
+
 	return retval;
 }
 
@@ -385,6 +562,12 @@ void usb_hcd_pxa27x_remove (struct usb_hcd *hcd, struct platform_device *pdev)
 
 	usb_remove_hcd(hcd);
 	pxa27x_stop_hc(ohci, &pdev->dev);
+
+	if (pxa310_u2d_is_setup(ohci)) {
+		iounmap(ohci->u2d_mmio_base);
+		clk_put(ohci->u2d_clk);
+	}
+
 	iounmap(hcd->regs);
 	release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
 	usb_put_hcd(hcd);
-- 
1.6.4.4



From grinberg at compulab.co.il  Wed Jun  2 03:40:48 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed,  2 Jun 2010 10:40:48 +0300
Subject: [PATCH 3/5] [ARM] pxa: add PXA310 specific ULPI implementation
In-Reply-To: <1275464450-23003-3-git-send-email-grinberg@compulab.co.il>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-2-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-3-git-send-email-grinberg@compulab.co.il>
Message-ID: <1275464450-23003-4-git-send-email-grinberg@compulab.co.il>


Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
Signed-off-by: Mike Rapoport <mike at compulab.co.il>
---
 arch/arm/mach-pxa/Kconfig                    |    4 +
 arch/arm/mach-pxa/Makefile                   |    1 +
 arch/arm/mach-pxa/include/mach/pxa310-ulpi.h |   19 +++++
 arch/arm/mach-pxa/pxa310-ulpi.c              |  110 ++++++++++++++++++++++++++
 4 files changed, 134 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-pxa/include/mach/pxa310-ulpi.h
 create mode 100644 arch/arm/mach-pxa/pxa310-ulpi.c

diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 5b6ee46..3c54cf0 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -616,6 +616,7 @@ config CPU_PXA300
 config CPU_PXA310
 	bool
 	select CPU_PXA300
+	select PXA310_ULPI if USB_ULPI
 	help
 	  PXA310 (codename Monahans-LV)
 
@@ -681,4 +682,7 @@ config PXA_HAVE_BOARD_IRQS
 config PXA_HAVE_ISA_IRQS
 	bool
 
+config PXA310_ULPI
+	bool
+
 endif
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 86bc87b..4ab51dd 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PXA25x)		+= mfp-pxa2xx.o pxa2xx.o pxa25x.o
 obj-$(CONFIG_PXA27x)		+= mfp-pxa2xx.o pxa2xx.o pxa27x.o
 obj-$(CONFIG_PXA3xx)		+= mfp-pxa3xx.o pxa3xx.o smemc.o
 obj-$(CONFIG_CPU_PXA300)	+= pxa300.o
+obj-$(CONFIG_PXA310_ULPI)	+= pxa310-ulpi.o
 obj-$(CONFIG_CPU_PXA320)	+= pxa320.o
 obj-$(CONFIG_CPU_PXA930)	+= pxa930.o
 
diff --git a/arch/arm/mach-pxa/include/mach/pxa310-ulpi.h b/arch/arm/mach-pxa/include/mach/pxa310-ulpi.h
new file mode 100644
index 0000000..b0f2062
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa310-ulpi.h
@@ -0,0 +1,19 @@
+/*
+ * PXA310 ULPI USB host header file.
+ *
+ * Copyright (C) 2010 CompuLab Ltd.
+ *
+ * Igor Grinberg <grinberg at compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __PXA310_ULPI__
+#define __PXA310_ULPI__
+
+#include <linux/usb/ulpi.h>
+
+extern struct otg_io_access_ops pxa310_ulpi_access_ops;
+
+#endif /* __PXA310_ULPI__ */
diff --git a/arch/arm/mach-pxa/pxa310-ulpi.c b/arch/arm/mach-pxa/pxa310-ulpi.c
new file mode 100644
index 0000000..14b6a2e
--- /dev/null
+++ b/arch/arm/mach-pxa/pxa310-ulpi.c
@@ -0,0 +1,110 @@
+/*
+ * linux/arch/arm/mach-pxa/pxa310-ulpi.c
+ *
+ * PXA310 ULPI implementation.
+ *
+ * Copyright (C) 2010 CompuLab Ltd.
+ *
+ * Igor Grinberg <grinberg at compulab.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/usb/otg.h>
+
+#include <mach/regs-u2d.h>
+#include <mach/pxa310-ulpi.h>
+
+#define U2DOTGUCR_ADDR_S	(16)
+#define U2DOTGUCR_WDATA_S	(8)
+
+enum u2d_phy_mode {
+	SYNCH		= 0,
+	CARKIT		= (1 << 0),
+	SER_3PIN	= (1 << 1),
+	SER_6PIN	= (1 << 2),
+	LOWPOWER	= (1 << 3),
+};
+
+static inline u32 u2d_readl(struct otg_transceiver *otg, u32 off)
+{
+	void __iomem *u2d_mmio_base = otg->io_priv;
+
+	return __raw_readl(u2d_mmio_base + off);
+}
+
+static inline void u2d_writel(struct otg_transceiver *otg, u32 off, u32 val)
+{
+	void __iomem *u2d_mmio_base = otg->io_priv;
+
+	__raw_writel(val, u2d_mmio_base + off);
+}
+
+static inline enum u2d_phy_mode ulpi_get_phymode(struct otg_transceiver *otg)
+{
+	return (u2d_readl(otg, U2DOTGUSR) & 0xF0000000) >> 28;
+}
+
+static int ulpi_poll(struct otg_transceiver *otg)
+{
+	int timeout = 50000;
+
+	while (timeout--) {
+		if (!(u2d_readl(otg, U2DOTGUCR) & U2DOTGUCR_RUN))
+			return 0;
+
+		cpu_relax();
+	}
+
+	pr_warning("%s: ULPI access timed out!\n", __func__);
+
+	return -ETIMEDOUT;
+}
+
+static int ulpi_read(struct otg_transceiver *otg, u32 reg)
+{
+	int err;
+
+	if (ulpi_get_phymode(otg)) {
+		pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
+		return -EBUSY;
+	}
+
+	u2d_writel(otg, U2DOTGUCR,
+		   U2DOTGUCR_RUN | U2DOTGUCR_RNW | (reg << U2DOTGUCR_ADDR_S));
+	msleep(5);
+
+	err = ulpi_poll(otg);
+	if (err)
+		return err;
+
+	return u2d_readl(otg, U2DOTGUCR) & U2DOTGUCR_RDATA;
+}
+
+static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
+{
+	if (ulpi_get_phymode(otg)) {
+		pr_warning("%s: PHY is not in SYNCH mode!\n", __func__);
+		return -EBUSY;
+	}
+
+	u2d_writel(otg, U2DOTGUCR, U2DOTGUCR_RUN | (reg << U2DOTGUCR_ADDR_S) |
+		   (val << U2DOTGUCR_WDATA_S));
+	msleep(5);
+
+	return ulpi_poll(otg);
+}
+
+struct otg_io_access_ops pxa310_ulpi_access_ops = {
+	.read	= ulpi_read,
+	.write	= ulpi_write,
+};
+EXPORT_SYMBOL_GPL(pxa310_ulpi_access_ops);
-- 
1.6.4.4



From grinberg at compulab.co.il  Wed Jun  2 03:40:50 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed,  2 Jun 2010 10:40:50 +0300
Subject: [PATCH 5/5] [ARM] pxa/cm-x300: enable USB host port 2 on CM-X300 with
	PXA310 cpu.
In-Reply-To: <1275464450-23003-5-git-send-email-grinberg@compulab.co.il>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-2-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-3-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-4-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-5-git-send-email-grinberg@compulab.co.il>
Message-ID: <1275464450-23003-6-git-send-email-grinberg@compulab.co.il>


Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
Signed-off-by: Mike Rapoport <mike at compulab.co.il>
---
 arch/arm/mach-pxa/cm-x300.c |  102 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 102 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index d37cfa1..87ffb38 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/delay.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 
 #include <linux/gpio.h>
 #include <linux/dm9000.h>
@@ -35,6 +36,9 @@
 #include <linux/spi/spi_gpio.h>
 #include <linux/spi/tdo24m.h>
 
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/setup.h>
@@ -47,6 +51,7 @@
 #include <plat/i2c.h>
 #include <plat/pxa3xx_nand.h>
 #include <mach/audio.h>
+#include <mach/pxa310-ulpi.h>
 
 #include <asm/mach/map.h>
 
@@ -65,6 +70,8 @@
 #define GPIO97_RTC_RD		(97)
 #define GPIO98_RTC_IO		(98)
 
+#define GPIO127_ULPI_PHY_RST	(127)
+
 static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = {
 	/* LCD */
 	GPIO54_LCD_LDD_0,
@@ -470,23 +477,118 @@ static inline void cm_x300_init_mmc(void) {}
 #endif
 
 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+#if defined(CONFIG_PXA310_ULPI)
+static struct clk *pout_clk;
+
+static int cm_x300_ulpi_clk_enable(void)
+{
+	int err;
+
+	/* CLK_POUT is connected to the ULPI PHY */
+	pout_clk = clk_get(NULL, "CLK_POUT");
+	if (IS_ERR(pout_clk)) {
+		err = PTR_ERR(pout_clk);
+		pr_err("%s: failed to get CLK_POUT: %d\n", __func__, err);
+		return err;
+	}
+	clk_enable(pout_clk);
+
+	return 0;
+}
+
+static inline void cm_x300_ulpi_clk_disable(void)
+{
+	if (!IS_ERR(pout_clk)) {
+		clk_disable(pout_clk);
+		clk_put(pout_clk);
+	}
+}
+
+static int cm_x300_ulpi_phy_reset(void)
+{
+	int err;
+
+	/* reset the PHY */
+	err = gpio_request(GPIO127_ULPI_PHY_RST, "ulpi reset");
+	if (err) {
+		pr_err("%s: failed to request ULPI reset GPIO: %d\n",
+		       __func__, err);
+		return err;
+	}
+
+	gpio_direction_output(GPIO127_ULPI_PHY_RST, 0);
+	msleep(10);
+	gpio_set_value(GPIO127_ULPI_PHY_RST, 1);
+	msleep(10);
+
+	gpio_free(GPIO127_ULPI_PHY_RST);
+
+	return 0;
+}
+
+static inline int cm_x300_ulpi_init(void)
+{
+	int err;
+
+	err = cm_x300_ulpi_clk_enable();
+	if (err)
+		return err;
+
+	err = cm_x300_ulpi_phy_reset();
+	if (err)
+		pr_err("%s: ULPI PHY init failed!\n", __func__);
+
+	return err;
+}
+#else
+static inline int cm_x300_ulpi_init(void) { return 0; }
+static inline void cm_x300_ulpi_clk_disable(void) {}
+#endif /* CONFIG_PXA310_ULPI */
+
 static int cm_x300_ohci_init(struct device *dev)
 {
 	if (cpu_is_pxa300())
 		UP2OCR = UP2OCR_HXS
 			| UP2OCR_HXOE | UP2OCR_DMPDE | UP2OCR_DPPDE;
 
+	if (cpu_is_pxa310())
+		cm_x300_ulpi_init();
+
 	return 0;
 }
 
+static void cm_x300_ohci_exit(struct device *dev)
+{
+	if (cpu_is_pxa310())
+		cm_x300_ulpi_clk_disable();
+}
+
 static struct pxaohci_platform_data cm_x300_ohci_platform_data = {
 	.port_mode	= PMM_PERPORT_MODE,
 	.flags		= ENABLE_PORT_ALL | POWER_CONTROL_LOW,
 	.init		= cm_x300_ohci_init,
+	.exit		= cm_x300_ohci_exit,
+
+#if defined(CONFIG_PXA310_ULPI)
+	.ulpi_mode	= ULPI_IC_6PIN,
+#endif
 };
 
 static void __init cm_x300_init_ohci(void)
 {
+	if (cpu_is_pxa310()) {
+#if defined(CONFIG_PXA310_ULPI)
+		cm_x300_ohci_platform_data.otg =
+			otg_ulpi_create(&pxa310_ulpi_access_ops,
+					USB_OTG_PULLDOWN_DM |
+					USB_OTG_PULLDOWN_DP |
+					USB_OTG_DRV_VBUS,
+					ULPI_IC_6PIN,
+					ULPI_FC_DEFAULT |
+					ULPI_FC_TRM_SEL);
+#endif
+	}
+
 	pxa_set_ohci_info(&cm_x300_ohci_platform_data);
 }
 #else
-- 
1.6.4.4



From dbaryshkov at gmail.com  Wed Jun  2 03:46:19 2010
From: dbaryshkov at gmail.com (Dmitry Eremin-Solenikov)
Date: Wed, 2 Jun 2010 11:46:19 +0400
Subject: [PATCH 1/2] at91sam9g20ek: add fixed-value regulator for wm8731
In-Reply-To: <1275059443-10100-1-git-send-email-dbaryshkov@gmail.com>
References: <1275059443-10100-1-git-send-email-dbaryshkov@gmail.com>
Message-ID: <AANLkTimgLRs_MX036cEsoIOYWoGfG9--W86-O6BRWACE@mail.gmail.com>

Any comments on these two patches? Can I submit them to patchsystem?

Without these patches the kernel with CONFIG_REGULATOR enabled is broken
on sam9g20ek boards (sound won't work).



On Fri, May 28, 2010 at 7:10 PM, Dmitry Eremin-Solenikov
<dbaryshkov at gmail.com> wrote:
> If CONFIG_REGULATOR is enabled, wm8731 fails on AT91SAM9G20EK board,
> since codec driver requires several voltage supplies and none are
> provided currently. As requires voltages are hardwired to 3V3, use fixed
> voltage regulator for this chip.
>
> Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>
> ---
> ?arch/arm/mach-at91/board-sam9g20ek.c | ? 45 ++++++++++++++++++++++++++++++++++
> ?1 files changed, 45 insertions(+), 0 deletions(-)

-- 
With best wishes
Dmitry


From linux at arm.linux.org.uk  Wed Jun  2 03:48:00 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 2 Jun 2010 08:48:00 +0100
Subject: [PATCH] Watchdog: Adding support for ARM Primecell SP805 Watchdog
In-Reply-To: <1274344428-28329-1-git-send-email-viresh.kumar@st.com>
References: <1274344428-28329-1-git-send-email-viresh.kumar@st.com>
Message-ID: <20100602074800.GD6644@n2100.arm.linux.org.uk>

On Thu, May 20, 2010 at 02:03:48PM +0530, Viresh KUMAR wrote:
> Technical Reference Manual can be found at:
> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0270b/DDI0270.pdf

Please include Wim Van Sebroeck for watchdog stuff - his address is in
MAINTAINERS.  Please also ensure that in future you're sending your
patches to relevant people - there isn't the capacity to review
every bit of code on this list.

There is a script - scripts/get_maintainer.pl - to help with this.


From dmitry.torokhov at gmail.com  Wed Jun  2 03:52:58 2010
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Wed, 2 Jun 2010 00:52:58 -0700
Subject: [PATCH 1/2] mc13783: add power button support
In-Reply-To: <1275334140-29339-2-git-send-email-philippe.retornaz@epfl.ch>
References: <1275334140-29339-1-git-send-email-philippe.retornaz@epfl.ch>
	<1275334140-29339-2-git-send-email-philippe.retornaz@epfl.ch>
Message-ID: <20100602075257.GJ3713@core.coreip.homeip.net>

Hi Philippe,

On Mon, May 31, 2010 at 09:28:59PM +0200, Philippe R?tornaz wrote:
> This adds support for the power-on buttons of MC13783 PMIC.
> This is done using a misc input device.
> 
> Signed-off-by: Philippe R?tornaz <philippe.retornaz at epfl.ch>
> ---
>  drivers/input/misc/Kconfig             |    7 +
>  drivers/input/misc/Makefile            |    1 +
>  drivers/input/misc/mc13783-pwrbutton.c |  301 ++++++++++++++++++++++++++++++++
>  drivers/mfd/mc13783-core.c             |    4 +
>  include/linux/mfd/mc13783.h            |   19 ++
>  5 files changed, 332 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/input/misc/mc13783-pwrbutton.c
> 
> diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig
> index 23140a3..2d25b16 100644
> --- a/drivers/input/misc/Kconfig
> +++ b/drivers/input/misc/Kconfig
> @@ -340,4 +340,11 @@ config INPUT_PCAP
>  	  To compile this driver as a module, choose M here: the
>  	  module will be called pcap_keys.
>  
> +config INPUT_MC13783_ON
> +	tristate "MC13783 ON buttons"
> +	depends on MFD_MC13783
> +	help
> +	  Support the ON buttons of MC13783 PMIC as an input device
> +	  reporting power button status.
> +

To compile this driver as a module...

>  endif
> diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile
> index 7e95a5d..c96311d 100644
> --- a/drivers/input/misc/Makefile
> +++ b/drivers/input/misc/Makefile
> @@ -32,4 +32,5 @@ obj-$(CONFIG_INPUT_WINBOND_CIR)		+= winbond-cir.o
>  obj-$(CONFIG_INPUT_WISTRON_BTNS)	+= wistron_btns.o
>  obj-$(CONFIG_INPUT_WM831X_ON)		+= wm831x-on.o
>  obj-$(CONFIG_INPUT_YEALINK)		+= yealink.o
> +obj-$(CONFIG_INPUT_MC13783_ON)		+= mc13783-pwrbutton.o

Keep makefile sorted please.

>  
> diff --git a/drivers/input/misc/mc13783-pwrbutton.c b/drivers/input/misc/mc13783-pwrbutton.c
> new file mode 100644
> index 0000000..61cfcce
> --- /dev/null
> +++ b/drivers/input/misc/mc13783-pwrbutton.c
> @@ -0,0 +1,301 @@
> +/**
> + * mc13783-pwrbutton.c - MC13783 Power Button Input Driver
> + *
> + * Copyright (C) 2010 Philippe R?tornaz
> + *
> + * Based on twl4030-pwrbutton driver by:
> + *	Peter De Schrijver <peter.de-schrijver at nokia.com>
> + *	Felipe Balbi <felipe.balbi at nokia.com>
> + *
> + * This file is subject to the terms and conditions of the GNU General
> + * Public License. See the file "COPYING" in the main directory of this
> + * archive for more details.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
> + */
> +
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/errno.h>
> +#include <linux/input.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/mfd/mc13783.h>
> +#include <linux/sched.h>
> +#include <linux/slab.h>
> +
> +struct mc13783_pwrb {
> +	struct input_dev *pwr;
> +	struct mc13783 *mc13783;
> +#define MC13783_PWRB_B1_EMULATE_CAD	(1 << 0)
> +#define MC13783_PWRB_B2_EMULATE_CAD	(1 << 1)
> +#define MC13783_PWRB_B3_EMULATE_CAD	(1 << 2)
> +#define MC13783_PWRB_B1_POL_INVERT	(1 << 3)
> +#define MC13783_PWRB_B2_POL_INVERT	(1 << 4)
> +#define MC13783_PWRB_B3_POL_INVERT	(1 << 5)
> +	int flags;
> +	unsigned int b1on_key;
> +	unsigned int b2on_key;
> +	unsigned int b3on_key;

Make it:

	unsigned short keymap[3];

and then do

	input->keycode = pwrb->keymap;
	input->keycodemax = ARRAY_SIZE(pwrb->keymap);
	input->keycodesize = sizeof(pwrb->keymap[0]);

so that keys can be remapped from userspace.

> +};
> +
> +#define MC13783_REG_INTERRUPT_SENSE_1		5
> +#define MC13783_IRQSENSE1_ONOFD1S		(1 << 3)
> +#define MC13783_IRQSENSE1_ONOFD2S		(1 << 4)
> +#define MC13783_IRQSENSE1_ONOFD3S		(1 << 5)
> +
> +#define MC13783_REG_POWER_CONTROL_2		15
> +#define MC13783_POWER_CONTROL_2_ON1BDBNC	4
> +#define MC13783_POWER_CONTROL_2_ON2BDBNC	6
> +#define MC13783_POWER_CONTROL_2_ON3BDBNC	8
> +#define MC13783_POWER_CONTROL_2_ON1BRSTEN	(1 << 1)
> +#define MC13783_POWER_CONTROL_2_ON2BRSTEN	(1 << 2)
> +#define MC13783_POWER_CONTROL_2_ON3BRSTEN	(1 << 3)
> +
> +static irqreturn_t b1on_irq(int irq, void *_priv)
> +{
> +	struct mc13783_pwrb *priv = _priv;
> +	int val;
> +
> +	mc13783_irq_ack(priv->mc13783, irq);
> +	mc13783_reg_read(priv->mc13783, MC13783_REG_INTERRUPT_SENSE_1, &val);
> +
> +	val = val & MC13783_IRQSENSE1_ONOFD1S ? 1 : 0;
> +
> +	if (priv->flags & MC13783_PWRB_B1_POL_INVERT)
> +		val ^= 1;
> +
> +	if (val && priv->flags & MC13783_PWRB_B1_EMULATE_CAD)
> +		kill_cad_pid(SIGINT, 1);

I do not think that individual input drivers should do this - CAD is
handled by the keyboard driver (drivers/char/keyboard) so it is just a
matter of loading proper keymap for your device.

> +
> +	input_report_key(priv->pwr, priv->b1on_key, val);
> +	input_sync(priv->pwr);
> +	return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t b2on_irq(int irq, void *_priv)
> +{
> +	struct mc13783_pwrb *priv = _priv;
> +	int val;
> +
> +	mc13783_irq_ack(priv->mc13783, irq);
> +	mc13783_reg_read(priv->mc13783, MC13783_REG_INTERRUPT_SENSE_1, &val);
> +
> +	val = val & MC13783_IRQSENSE1_ONOFD2S ? 1 : 0;
> +
> +	if (priv->flags & MC13783_PWRB_B2_POL_INVERT)
> +		val ^= 1;
> +
> +	if (val && priv->flags & MC13783_PWRB_B2_EMULATE_CAD)
> +		kill_cad_pid(SIGINT, 1);
> +
> +	input_report_key(priv->pwr, priv->b2on_key, val);
> +	input_sync(priv->pwr);
> +	return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t b3on_irq(int irq, void *_priv)
> +{
> +	struct mc13783_pwrb *priv = _priv;
> +	int val;
> +
> +	mc13783_irq_ack(priv->mc13783, irq);
> +	mc13783_reg_read(priv->mc13783, MC13783_REG_INTERRUPT_SENSE_1, &val);
> +
> +	val = val & MC13783_IRQSENSE1_ONOFD3S ? 1 : 0;
> +
> +	if (priv->flags & MC13783_PWRB_B3_POL_INVERT)
> +		val ^= 1;
> +
> +	if (val && priv->flags & MC13783_PWRB_B3_EMULATE_CAD)
> +		kill_cad_pid(SIGINT, 1);
> +
> +	input_report_key(priv->pwr, priv->b3on_key, val);
> +	input_sync(priv->pwr);
> +	return IRQ_HANDLED;

I am pretty sure these 3 functions can be combined.

> +}
> +
> +static int __devinit mc13783_pwrbutton_probe(struct platform_device *pdev)
> +{
> +	struct mc13783_buttons_platform_data *pdata;
> +	struct mc13783 *mc13783 = dev_get_drvdata(pdev->dev.parent);
> +	struct input_dev *pwr;
> +	struct mc13783_pwrb *priv;
> +	int err = 0;
> +	int reg = 0;
> +
> +	pdata = dev_get_platdata(&pdev->dev);
> +	if (pdata == NULL) {
> +		dev_err(&pdev->dev, "missing platform data\n");
> +		return -ENODEV;
> +	}
> +
> +	pwr = input_allocate_device();
> +	if (!pwr) {
> +		dev_dbg(&pdev->dev, "Can't allocate power button\n");
> +		return -ENOMEM;
> +	}
> +
> +	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> +
> +	if (!priv) {
> +		dev_dbg(&pdev->dev, "Can't allocate power button\n");
> +		goto free_input_dev;
> +	}
> +
> +	pwr->evbit[0] = BIT_MASK(EV_KEY);
> +
> +	reg |= (pdata->b1on_flags & 0x3) << MC13783_POWER_CONTROL_2_ON1BDBNC;
> +	reg |= (pdata->b2on_flags & 0x3) << MC13783_POWER_CONTROL_2_ON2BDBNC;
> +	reg |= (pdata->b3on_flags & 0x3) << MC13783_POWER_CONTROL_2_ON3BDBNC;
> +
> +	priv->pwr = pwr;
> +	priv->mc13783 = mc13783;
> +
> +	mc13783_lock(mc13783);
> +
> +	if (pdata->b1on_flags & MC13783_BUTTON_ENABLE) {
> +		priv->b1on_key = pdata->b1on_key;
> +		if (pdata->b1on_key != KEY_RESERVED)
> +			pwr->keybit[BIT_WORD(pdata->b1on_key)] |=
> +						BIT_MASK(pdata->b1on_key);

Just use __set_bit().

> +
> +		if (pdata->b1on_flags & MC13783_BUTTON_POL_INVERT)
> +			priv->flags |= MC13783_PWRB_B1_POL_INVERT;
> +		if (pdata->b1on_flags & MC13783_BUTTON_EMUL_CAD)
> +			priv->flags |= MC13783_PWRB_B1_EMULATE_CAD;
> +
> +		if (pdata->b1on_flags & MC13783_BUTTON_RESET_EN)
> +			reg |= MC13783_POWER_CONTROL_2_ON1BRSTEN;
> +
> +		mc13783_irq_request(mc13783, MC13783_IRQ_ONOFD1, b1on_irq,
> +							"b1on", priv);

No error handling here?

> +	}
> +
> +	if (pdata->b2on_flags & MC13783_BUTTON_ENABLE) {
> +		priv->b2on_key = pdata->b2on_key;
> +		if (pdata->b2on_key != KEY_RESERVED)
> +			pwr->keybit[BIT_WORD(pdata->b2on_key)] |=
> +						BIT_MASK(pdata->b2on_key);
> +
> +		if (pdata->b2on_flags & MC13783_BUTTON_POL_INVERT)
> +			priv->flags |= MC13783_PWRB_B2_POL_INVERT;
> +		if (pdata->b2on_flags & MC13783_BUTTON_EMUL_CAD)
> +			priv->flags |= MC13783_PWRB_B2_EMULATE_CAD;
> +
> +		if (pdata->b2on_flags & MC13783_BUTTON_RESET_EN)
> +			reg |= MC13783_POWER_CONTROL_2_ON2BRSTEN;
> +
> +		mc13783_irq_request(mc13783, MC13783_IRQ_ONOFD2, b2on_irq,
> +							"b2on", priv);
> +	}
> +
> +	if (pdata->b3on_flags & MC13783_BUTTON_ENABLE) {
> +		priv->b3on_key = pdata->b3on_key;
> +		if (pdata->b3on_key != KEY_RESERVED)
> +			pwr->keybit[BIT_WORD(pdata->b3on_key)] |=
> +						BIT_MASK(pdata->b3on_key);
> +
> +		if (pdata->b3on_flags & MC13783_BUTTON_POL_INVERT)
> +			priv->flags |= MC13783_PWRB_B3_POL_INVERT;
> +		if (pdata->b3on_flags & MC13783_BUTTON_EMUL_CAD)
> +			priv->flags |= MC13783_PWRB_B3_EMULATE_CAD;
> +
> +		if (pdata->b3on_flags & MC13783_BUTTON_RESET_EN)
> +			reg |= MC13783_POWER_CONTROL_2_ON3BRSTEN;
> +
> +		mc13783_irq_request(mc13783, MC13783_IRQ_ONOFD3, b3on_irq,
> +							"b3on", priv);
> +	}
> +
> +	mc13783_reg_rmw(mc13783, MC13783_REG_POWER_CONTROL_2, 0x3FE, reg);
> +
> +	mc13783_unlock(mc13783);
> +
> +	pwr->name = "mc13783_pwrbutton";
> +	pwr->phys = "mc13783_pwrbutton/input0";
> +	pwr->dev.parent = &pdev->dev;
> +
> +	err = input_register_device(pwr);
> +	if (err) {
> +		dev_dbg(&pdev->dev, "Can't register power button: %d\n", err);
> +		goto free_irq;
> +	}
> +
> +	platform_set_drvdata(pdev, priv);
> +
> +	return 0;
> +
> +free_irq:
> +	mc13783_lock(mc13783);
> +	if (pdata->b3on_flags & MC13783_BUTTON_ENABLE)
> +		mc13783_irq_free(mc13783, MC13783_IRQ_ONOFD3, priv);
> +	if (pdata->b2on_flags & MC13783_BUTTON_ENABLE)
> +		mc13783_irq_free(mc13783, MC13783_IRQ_ONOFD2, priv);
> +	if (pdata->b1on_flags & MC13783_BUTTON_ENABLE)
> +		mc13783_irq_free(mc13783, MC13783_IRQ_ONOFD1, priv);
> +	mc13783_unlock(mc13783);
> +
> +	kfree(priv);
> +
> +free_input_dev:
> +	input_free_device(pwr);
> +	return err;
> +}
> +
> +static int __devexit mc13783_pwrbutton_remove(struct platform_device *pdev)
> +{
> +	struct mc13783_pwrb *priv = platform_get_drvdata(pdev);
> +	struct mc13783_buttons_platform_data *pdata;
> +	pdata = dev_get_platdata(&pdev->dev);
> +
> +	mc13783_lock(priv->mc13783);
> +	if (pdata->b3on_flags & MC13783_BUTTON_ENABLE)
> +		mc13783_irq_free(priv->mc13783, MC13783_IRQ_ONOFD3, priv);
> +	if (pdata->b2on_flags & MC13783_BUTTON_ENABLE)
> +		mc13783_irq_free(priv->mc13783, MC13783_IRQ_ONOFD2, priv);
> +	if (pdata->b1on_flags & MC13783_BUTTON_ENABLE)
> +		mc13783_irq_free(priv->mc13783, MC13783_IRQ_ONOFD1, priv);
> +	mc13783_unlock(priv->mc13783);

Looks like this can be factored into a separate function.

> +
> +	input_unregister_device(priv->pwr);
> +
> +	kfree(priv);
> +
> +	return 0;
> +}
> +
> +struct platform_driver mc13783_pwrbutton_driver = {
> +	.probe		= mc13783_pwrbutton_probe,
> +	.remove		= __devexit_p(mc13783_pwrbutton_remove),
> +	.driver		= {
> +		.name	= "mc13783-pwrbutton",
> +		.owner	= THIS_MODULE,
> +	},
> +};
> +
> +static int __init mc13783_pwrbutton_init(void)
> +{
> +	return platform_driver_register(&mc13783_pwrbutton_driver);
> +}
> +module_init(mc13783_pwrbutton_init);
> +
> +static void __exit mc13783_pwrbutton_exit(void)
> +{
> +	platform_driver_unregister(&mc13783_pwrbutton_driver);
> +}
> +module_exit(mc13783_pwrbutton_exit);
> +
> +MODULE_ALIAS("platform:mc13783-pwrbutton");
> +MODULE_DESCRIPTION("MC13783 Power Button");
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("Philippe Retornaz");
> +
> diff --git a/drivers/mfd/mc13783-core.c b/drivers/mfd/mc13783-core.c
> index fecf38a..fb3e98b 100644
> --- a/drivers/mfd/mc13783-core.c
> +++ b/drivers/mfd/mc13783-core.c
> @@ -683,6 +683,10 @@ err_revision:
>  		mc13783_add_subdevice_pdata(mc13783, "mc13783-led",
>  					pdata->leds, sizeof(*pdata->leds));
>  
> +	if (pdata->flags & MC13783_USE_BUTTON)
> +		mc13783_add_subdevice_pdata(mc13783, "mc13783-pwrbutton",
> +				pdata->buttons, sizeof(*pdata->buttons));
> +
>  	return 0;
>  }
>  
> diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h
> index 4a894f6..66981a5 100644
> --- a/include/linux/mfd/mc13783.h
> +++ b/include/linux/mfd/mc13783.h
> @@ -128,6 +128,23 @@ struct mc13783_leds_platform_data {
>  	char tc3_period;
>  };
>  
> +struct mc13783_buttons_platform_data {
> +#define MC13783_BUTTON_DBNC_0MS		0
> +#define MC13783_BUTTON_DBNC_30MS	1
> +#define MC13783_BUTTON_DBNC_150MS	2
> +#define MC13783_BUTTON_DBNC_750MS	3
> +#define MC13783_BUTTON_ENABLE		(1 << 2)
> +#define MC13783_BUTTON_POL_INVERT	(1 << 3)
> +#define MC13783_BUTTON_RESET_EN		(1 << 4)
> +#define MC13783_BUTTON_EMUL_CAD		(1 << 5)
> +	int b1on_flags;
> +	unsigned int b1on_key;
> +	int b2on_flags;
> +	unsigned int b2on_key;
> +	int b3on_flags;
> +	unsigned int b3on_key;
> +};
> +
>  /* to be cleaned up */
>  struct regulator_init_data;
>  
> @@ -145,6 +162,7 @@ struct mc13783_platform_data {
>  	int num_regulators;
>  	struct mc13783_regulator_init_data *regulators;
>  	struct mc13783_leds_platform_data *leds;
> +	struct mc13783_buttons_platform_data *buttons;
>  
>  #define MC13783_USE_TOUCHSCREEN (1 << 0)
>  #define MC13783_USE_CODEC	(1 << 1)
> @@ -152,6 +170,7 @@ struct mc13783_platform_data {
>  #define MC13783_USE_RTC		(1 << 3)
>  #define MC13783_USE_REGULATOR	(1 << 4)
>  #define MC13783_USE_LED		(1 << 5)
> +#define MC13783_USE_BUTTON	(1 << 6)
>  	unsigned int flags;
>  };
>  
> -- 
> 1.6.3.3
> 

-- 
Dmitry


From viresh.kumar at st.com  Wed Jun  2 03:57:39 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Wed, 02 Jun 2010 13:27:39 +0530
Subject: [PATCH] Watchdog: Adding support for ARM Primecell SP805	Watchdog
In-Reply-To: <20100602074800.GD6644@n2100.arm.linux.org.uk>
References: <1274344428-28329-1-git-send-email-viresh.kumar@st.com>
	<20100602074800.GD6644@n2100.arm.linux.org.uk>
Message-ID: <4C060EF3.1050000@st.com>

On 6/2/2010 1:18 PM, Russell King - ARM Linux wrote:
> On Thu, May 20, 2010 at 02:03:48PM +0530, Viresh KUMAR wrote:
>> Technical Reference Manual can be found at:
>> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0270b/DDI0270.pdf
> 
> Please include Wim Van Sebroeck for watchdog stuff - his address is in
> MAINTAINERS.  Please also ensure that in future you're sending your
> patches to relevant people - there isn't the capacity to review
> every bit of code on this list.
> 

Thanks Russell.

I will send patch to Wim Van.

viresh


From amit.kucheria at canonical.com  Wed Jun  2 04:00:54 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Wed, 2 Jun 2010 11:00:54 +0300
Subject: [PATCH 3/3] mx51/clock: add keypad clock definition and
	registration
In-Reply-To: <1275405043-18230-4-git-send-email-jason77.wang@gmail.com>
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-3-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-4-git-send-email-jason77.wang@gmail.com>
Message-ID: <20100602080054.GL2346@matterhorn.lan>

On 10 Jun 01, Jason Wang wrote:
> On i.MX51 platforms, the keypad controller has no gate clock, to
> meet the imx keypad driver requirement, we add a empty definition and
> register it. Now the keypad driver can work.
> 
> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
> ---
>  arch/arm/mach-mx5/clock-mx51.c |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
> index d9f612d..e89b93a 100644
> --- a/arch/arm/mach-mx5/clock-mx51.c
> +++ b/arch/arm/mach-mx5/clock-mx51.c
> @@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
>  	.parent = &ckil_clk,
>  };
>  
> +static struct clk kpp_clk = {
> +	.id = 0,
> +};
> +
>  #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
>  	static struct clk name = {			\
>  		.id		= i,			\
> @@ -821,6 +825,7 @@ static struct clk_lookup lookups[] = {
>  	_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
>  	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
>  	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
> +	_REGISTER_CLOCK(NULL, "kpp", kpp_clk)

Should be

_REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)

since that is the device id that will be used in your platform device.

-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------


From dmitry.torokhov at gmail.com  Wed Jun  2 04:02:13 2010
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Wed, 2 Jun 2010 01:02:13 -0700
Subject: [PATCH] imx_keypad: add PM support
In-Reply-To: <1275209466-3899-1-git-send-email-eric@eukrea.com>
References: <1275135823.3128.15.camel@realization>
	<1275209466-3899-1-git-send-email-eric@eukrea.com>
Message-ID: <20100602080212.GK3713@core.coreip.homeip.net>

Hi Eric,

On Sun, May 30, 2010 at 10:51:06AM +0200, Eric B?nard wrote:
> * add suspend/resume support
> * use keypad_data to enable wakeup from platform data
> * suspend/resume tested when keypad is not in use and when it's
> is use (in which case we immediatly get the key pressed for
> wakeup)
> 
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> ---
>  drivers/input/keyboard/imx_keypad.c |   56 +++++++++++++++++++++++++++++++++-
>  1 files changed, 54 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/input/keyboard/imx_keypad.c b/drivers/input/keyboard/imx_keypad.c
> index d92c15c..b303cc9 100644
> --- a/drivers/input/keyboard/imx_keypad.c
> +++ b/drivers/input/keyboard/imx_keypad.c
> @@ -364,6 +364,55 @@ static void imx_keypad_inhibit(struct imx_keypad *keypad)
>  	writew(0xff00, keypad->mmio_base + KPCR);
>  }
>  
> +static int mxc_kpp_suspend(struct platform_device *pdev, pm_message_t state)
> +{
> +	struct imx_keypad *keypad = platform_get_drvdata(pdev);
> +	unsigned short reg_val;
> +
> +	clk_disable(keypad->clk);
> +
> +	if (device_may_wakeup(&pdev->dev)) {
> +		reg_val = readw(keypad->mmio_base + KPSR);
> +		if ((reg_val & KBD_STAT_KDIE) == 0) {
> +			/* If no depress interrupt enable the release interrupt */
> +			reg_val |= KBD_STAT_KRIE;
> +			writew(reg_val, keypad->mmio_base + KPSR);
> +		}
> +		enable_irq_wake(keypad->irq);
> +	} else {
> +		keypad->enabled = false;
> +		synchronize_irq(keypad->irq);
> +		disable_irq(keypad->irq);

I'd factor it out as it is used in both suspend and close.

Does everythig (clk_disable, eit) work well in case when device is still
closed when it get ssuspended?

Also, do you really need such an elaborate setup when device is/is not
wakeup source? Do you really loose keypress if you always dosable IRQ in
suspend and enable it in resume?

> +	}
> +
> +	return 0;
> +}
> +
> +/*!
> + * This function brings the Keypad controller back from low-power state.
> + * If Keypad is enabled as a wake source(i.e. it can resume the system
> + * from suspend mode), the Keypad controller doesn't enter low-power state.
> + *
> + * @param   pdev  the device structure used to give information on Keypad
> + *                to resume
> + *
> + * @return  The function always returns 0.
> + */

This is not the standard kerneldoc markup.

> +static int mxc_kpp_resume(struct platform_device *pdev)
> +{
> +	struct imx_keypad *keypad = platform_get_drvdata(pdev);
> +
> +	clk_enable(keypad->clk);
> +	if (device_may_wakeup(&pdev->dev)) {
> +		/* The irq routine already cleared KRIE if it was set */
> +	} else {
> +		keypad->enabled = true;
> +		enable_irq(keypad->irq);
> +	}
> +
> +	return 0;
> +}
> +
>  static void imx_keypad_close(struct input_dev *dev)
>  {
>  	struct imx_keypad *keypad = input_get_drvdata(dev);
> @@ -410,7 +459,8 @@ open_err:
>  
>  static int __devinit imx_keypad_probe(struct platform_device *pdev)
>  {
> -	const struct matrix_keymap_data *keymap_data = pdev->dev.platform_data;
> +	const struct matrix_keypad_platform_data *keypad_data = pdev->dev.platform_data;
> +	const struct matrix_keymap_data *keymap_data = keypad_data->keymap_data;
>  	struct imx_keypad *keypad;
>  	struct input_dev *input_dev;
>  	struct resource *res;
> @@ -525,7 +575,7 @@ static int __devinit imx_keypad_probe(struct platform_device *pdev)
>  	}
>  
>  	platform_set_drvdata(pdev, keypad);
> -	device_init_wakeup(&pdev->dev, 1);
> +	device_init_wakeup(&pdev->dev, keypad_data->wakeup);
>  
>  	return 0;
>  
> @@ -574,6 +624,8 @@ static struct platform_driver imx_keypad_driver = {
>  	},
>  	.probe		= imx_keypad_probe,
>  	.remove		= __devexit_p(imx_keypad_remove),
> +	.suspend = mxc_kpp_suspend,
> +	.resume = mxc_kpp_resume,

Please use pm_ops.

Thanks.

-- 
Dmitry


From viresh.kumar at st.com  Wed Jun  2 04:03:03 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Wed,  2 Jun 2010 13:33:03 +0530
Subject: [PATCH resend] Watchdog: Adding support for ARM Primecell SP805
	Watchdog
Message-ID: <1275465783-14052-1-git-send-email-viresh.kumar@st.com>

Technical Reference Manual can be found at:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0270b/DDI0270.pdf

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/watchdog/Kconfig     |    7 +
 drivers/watchdog/Makefile    |    1 +
 drivers/watchdog/sp805_wdt.c |  386 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 394 insertions(+), 0 deletions(-)
 create mode 100644 drivers/watchdog/sp805_wdt.c

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index b87ba23..2759a91 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -73,6 +73,13 @@ config WM8350_WATCHDOG
 
 # ARM Architecture
 
+config ARM_SP805_WATCHDOG
+	tristate "ARM SP805 Watchdog"
+	depends on ARM_AMBA
+	help
+	  ARM Primecell SP805 Watchdog timer. This will reboot your system when
+	  the timeout is reached.
+
 config AT91RM9200_WATCHDOG
 	tristate "AT91RM9200 watchdog"
 	depends on ARCH_AT91RM9200
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 5e3cb95..28af87a 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -25,6 +25,7 @@ obj-$(CONFIG_USBPCWATCHDOG) += pcwd_usb.o
 # ALPHA Architecture
 
 # ARM Architecture
+obj-$(CONFIG_ARM_SP805_WATCHDOG) += sp805_wdt.o
 obj-$(CONFIG_AT91RM9200_WATCHDOG) += at91rm9200_wdt.o
 obj-$(CONFIG_AT91SAM9X_WATCHDOG) += at91sam9_wdt.o
 obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
diff --git a/drivers/watchdog/sp805_wdt.c b/drivers/watchdog/sp805_wdt.c
new file mode 100644
index 0000000..85d86ac
--- /dev/null
+++ b/drivers/watchdog/sp805_wdt.c
@@ -0,0 +1,386 @@
+/*
+ * drivers/char/watchdog/sp805-wdt.c
+ *
+ * Watchdog driver for ARM SP805 watchdog module
+ *
+ * Copyright (C) 2010 ST Microelectronics
+ * Viresh Kumar<viresh.kumar at st.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2 or later. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/device.h>
+#include <linux/resource.h>
+#include <linux/amba/bus.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/fs.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/kernel.h>
+#include <linux/math64.h>
+#include <linux/miscdevice.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
+#include <linux/watchdog.h>
+
+/* default timeout in seconds */
+#define DEFAULT_TIMEOUT		60
+
+#define MODULE_NAME		"sp805-wdt"
+
+/* watchdog register offsets and masks */
+#define WDTLOAD			0x000
+	#define LOAD_MIN	0x00000001
+	#define LOAD_MAX	0xFFFFFFFF
+#define WDTVALUE		0x004
+#define WDTCONTROL		0x008
+	/* control register masks */
+	#define	INT_ENABLE	(1 << 0)
+	#define	RESET_ENABLE	(1 << 1)
+#define WDTINTCLR		0x00C
+#define WDTRIS			0x010
+#define WDTMIS			0x014
+	#define INT_MASK	(1 << 0)
+#define WDTLOCK			0xC00
+	#define	UNLOCK		0x1ACCE551
+	#define	LOCK		0x00000001
+
+/**
+ * struct sp805_wdt: sp805 wdt device structure
+ *
+ * lock: spin lock protecting dev structure and io access
+ * base: base address of wdt
+ * clk: clock structure of wdt
+ * dev: amba device structure of wdt
+ * status: current status of wdt
+ * load_val: load value to be set for current timeout
+ * timeout: current programmed timeout
+ */
+struct sp805_wdt {
+	spinlock_t			lock;
+	void __iomem			*base;
+	struct clk			*clk;
+	struct amba_device		*adev;
+	unsigned long			status;
+	#define WDT_BUSY		0
+	#define WDT_CAN_BE_CLOSED	1
+	unsigned int			load_val;
+	unsigned int			timeout;
+};
+
+/* local variables */
+static struct sp805_wdt *wdt;
+static int nowayout = WATCHDOG_NOWAYOUT;
+
+/* This routine finds load value that will reset system in required timout */
+static void wdt_setload(unsigned int timeout)
+{
+	u64 load, rate;
+
+	rate = clk_get_rate(wdt->clk);
+
+	/*
+	 * sp805 runs counter with given value twice, after the end of first
+	 * counter it gives an interrupt and then starts counter again. If
+	 * interrupt already occured then it resets the system. This is why
+	 * load is half of what should be required.
+	 */
+	load = div_u64(rate, 2) * timeout - 1;
+
+	load = (load > LOAD_MAX) ? LOAD_MAX : load;
+	load = (load < LOAD_MIN) ? LOAD_MIN : load;
+
+	spin_lock(&wdt->lock);
+	wdt->load_val = load;
+	/* roundup timeout to closest positive integer value */
+	wdt->timeout = div_u64((load + 1) * 2 + (rate / 2), rate);
+	spin_unlock(&wdt->lock);
+}
+
+/* returns number of seconds left for reset to occur */
+static u32 wdt_timeleft(void)
+{
+	u64 load, rate;
+
+	rate = clk_get_rate(wdt->clk);
+
+	spin_lock(&wdt->lock);
+	load = readl(wdt->base + WDTVALUE);
+
+	/*If the interrupt is inactive then time left is WDTValue + WDTLoad. */
+	if (!(readl(wdt->base + WDTRIS) & INT_MASK))
+		load += wdt->load_val + 1;
+	spin_unlock(&wdt->lock);
+
+	return div_u64(load, rate);
+}
+
+/* enables watchdog timers reset */
+static void wdt_enable(void)
+{
+	spin_lock(&wdt->lock);
+
+	writel(UNLOCK, wdt->base + WDTLOCK);
+	writel(wdt->load_val, wdt->base + WDTLOAD);
+	writel(INT_MASK, wdt->base + WDTINTCLR);
+	writel(INT_ENABLE | RESET_ENABLE, wdt->base + WDTCONTROL);
+	writel(LOCK, wdt->base + WDTLOCK);
+
+	spin_unlock(&wdt->lock);
+}
+
+/* disables watchdog timers reset */
+static void wdt_disable(void)
+{
+	spin_lock(&wdt->lock);
+
+	writel(UNLOCK, wdt->base + WDTLOCK);
+	writel(0, wdt->base + WDTCONTROL);
+	writel(0, wdt->base + WDTLOAD);
+	writel(LOCK, wdt->base + WDTLOCK);
+
+	spin_unlock(&wdt->lock);
+}
+
+static ssize_t sp805_wdt_write(struct file *file, const char *data,
+		size_t len, loff_t *ppos)
+{
+	if (len) {
+		if (!nowayout) {
+			size_t i;
+
+			clear_bit(WDT_CAN_BE_CLOSED, &wdt->status);
+
+			for (i = 0; i != len; i++) {
+				char c;
+
+				if (get_user(c, data + i))
+					return -EFAULT;
+				/* Check for Magic Close character */
+				if (c == 'V') {
+					set_bit(WDT_CAN_BE_CLOSED,
+							&wdt->status);
+					break;
+				}
+			}
+		}
+		wdt_enable();
+	}
+	return len;
+}
+
+static const struct watchdog_info ident = {
+	.options = WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
+	.identity = MODULE_NAME,
+};
+
+static long sp805_wdt_ioctl(struct file *file, unsigned int cmd,
+		unsigned long arg)
+{
+	int ret = -ENOTTY;
+	unsigned int timeout;
+
+	switch (cmd) {
+	case WDIOC_GETSUPPORT:
+		ret = copy_to_user((struct watchdog_info *)arg, &ident,
+				sizeof(ident)) ? -EFAULT : 0;
+		break;
+
+	case WDIOC_GETSTATUS:
+		ret = put_user(0, (int *)arg);
+		break;
+
+	case WDIOC_KEEPALIVE:
+		wdt_enable();
+		ret = 0;
+		break;
+
+	case WDIOC_SETTIMEOUT:
+		ret = get_user(timeout, (unsigned int *)arg);
+		if (ret)
+			break;
+
+		wdt_setload(timeout);
+
+		wdt_enable();
+		/* Fall through */
+
+	case WDIOC_GETTIMEOUT:
+		ret = put_user(wdt->timeout, (unsigned int *)arg);
+		break;
+	case WDIOC_GETTIMELEFT:
+		ret = put_user(wdt_timeleft(), (unsigned int *)arg);
+		break;
+	}
+	return ret;
+}
+
+static int sp805_wdt_open(struct inode *inode, struct file *file)
+{
+	int ret = 0;
+
+	if (test_and_set_bit(WDT_BUSY, &wdt->status))
+		return -EBUSY;
+
+	ret = clk_enable(wdt->clk);
+	if (ret) {
+		dev_err(&wdt->adev->dev, "clock enable fail");
+		goto err;
+	}
+
+	wdt_enable();
+
+	/* can not be closed, once enabled */
+	clear_bit(WDT_CAN_BE_CLOSED, &wdt->status);
+	return nonseekable_open(inode, file);
+
+err:
+	clear_bit(WDT_BUSY, &wdt->status);
+	return ret;
+}
+
+static int sp805_wdt_release(struct inode *inode, struct file *file)
+{
+	if (!test_bit(WDT_CAN_BE_CLOSED, &wdt->status)) {
+		clear_bit(WDT_BUSY, &wdt->status);
+		dev_warn(&wdt->adev->dev, "Device closed unexpectedly\n");
+		return 0;
+	}
+
+	wdt_disable();
+	clk_disable(wdt->clk);
+	clear_bit(WDT_BUSY, &wdt->status);
+
+	return 0;
+}
+
+static const struct file_operations sp805_wdt_fops = {
+	.owner = THIS_MODULE,
+	.llseek = no_llseek,
+	.write = sp805_wdt_write,
+	.unlocked_ioctl = sp805_wdt_ioctl,
+	.open = sp805_wdt_open,
+	.release = sp805_wdt_release,
+};
+
+static struct miscdevice sp805_wdt_miscdev = {
+	.minor = WATCHDOG_MINOR,
+	.name = "watchdog",
+	.fops = &sp805_wdt_fops,
+};
+
+static int __devinit
+sp805_wdt_probe(struct amba_device *adev, struct amba_id *id)
+{
+	int ret = 0;
+
+	if (!request_mem_region(adev->res.start, resource_size(&adev->res),
+				"sp805_wdt")) {
+		dev_warn(&adev->dev, "Failed to get memory region resource\n");
+		ret = -ENOENT;
+		goto err;
+	}
+
+	wdt = kzalloc(sizeof(*wdt), GFP_KERNEL);
+	if (!wdt) {
+		dev_warn(&adev->dev, "Kzalloc failed\n");
+		ret = -ENOMEM;
+		goto err_kzalloc;
+	}
+
+	wdt->clk = clk_get(&adev->dev, NULL);
+	if (IS_ERR(wdt->clk)) {
+		dev_warn(&adev->dev, "Clock not found\n");
+		ret = PTR_ERR(wdt->clk);
+		goto err_clk_get;
+	}
+
+	wdt->base = ioremap(adev->res.start, resource_size(&adev->res));
+	if (!wdt->base) {
+		ret = -ENOMEM;
+		dev_warn(&adev->dev, "ioremap fail\n");
+		goto err_ioremap;
+	}
+
+	wdt->adev = adev;
+	spin_lock_init(&wdt->lock);
+	wdt_setload(DEFAULT_TIMEOUT);
+
+	ret = misc_register(&sp805_wdt_miscdev);
+	if (ret < 0) {
+		dev_warn(&adev->dev, "cannot register misc device\n");
+		goto err_misc_register;
+	}
+
+	dev_info(&adev->dev, "registration successful\n");
+	return 0;
+
+err_misc_register:
+	iounmap(wdt->base);
+err_ioremap:
+	clk_put(wdt->clk);
+err_clk_get:
+	kfree(wdt);
+	wdt = NULL;
+err_kzalloc:
+	release_mem_region(adev->res.start, resource_size(&adev->res));
+err:
+	dev_err(&adev->dev, "Probe Failed!!!\n");
+	return ret;
+}
+
+static int __devexit sp805_wdt_remove(struct amba_device *adev)
+{
+	misc_deregister(&sp805_wdt_miscdev);
+	iounmap(wdt->base);
+	clk_put(wdt->clk);
+	kfree(wdt);
+	release_mem_region(adev->res.start, resource_size(&adev->res));
+
+	return 0;
+}
+
+static struct amba_id sp805_wdt_ids[] __initdata = {
+	{
+		.id	= 0x00141805,
+		.mask	= 0x00ffffff,
+	},
+	{ 0, 0 },
+};
+
+static struct amba_driver sp805_wdt_driver = {
+	.drv = {
+		.name	= MODULE_NAME,
+	},
+	.id_table	= sp805_wdt_ids,
+	.probe		= sp805_wdt_probe,
+	.remove = __devexit_p(sp805_wdt_remove),
+};
+
+static int __init sp805_wdt_init(void)
+{
+	return amba_driver_register(&sp805_wdt_driver);
+}
+module_init(sp805_wdt_init);
+
+static void __exit sp805_wdt_exit(void)
+{
+	amba_driver_unregister(&sp805_wdt_driver);
+}
+module_exit(sp805_wdt_exit);
+
+module_param(nowayout, int, 0);
+MODULE_PARM_DESC(nowayout,
+		"Set to 1 to keep watchdog running after device release");
+
+MODULE_AUTHOR("Viresh Kumar <viresh.kumar at st.com>");
+MODULE_DESCRIPTION("ARM SP805 Watchdog Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
-- 
1.6.0.2



From eric.y.miao at gmail.com  Wed Jun  2 04:29:19 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 2 Jun 2010 16:29:19 +0800
Subject: [PATCH 0/5] Enable pxa310 usb otg port host mode.
In-Reply-To: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <AANLkTil7KUMIqP76bXAOOCiAfISzCiixtMzNDAHo7kNo@mail.gmail.com>

On Wed, Jun 2, 2010 at 3:40 PM, Igor Grinberg <grinberg at compulab.co.il> wrote:
> This patch series extends the existing usb ulpi generic driver
> with support for Function and Interface control of the ULPI PHYs,
> adds support for SMSC USB3319 ulpi phy,
> implement the pxa310 specific ulpi functionality and make pxa specific ohci
> implementation aware of pxa310 usb otg port host mode.
>

Looks like a right way to go, include Haojian and Jing for review.

> Igor Grinberg (5):
> ?usb/otg/ulpi: extend the generic ulpi driver.
> ?usb/otg/ulpi: add support for SMSC USB3319 ulpi phy.
> ?[ARM] pxa: add PXA310 specific ULPI implementation
> ?[ARM] usb/host/ohci-pxa27x: make PXA310 USB OTG port work in host
> ? ?mode.
> ?[ARM] pxa/cm-x300: enable USB host port 2 on CM-X300 with PXA310 cpu.
>
> ?arch/arm/mach-mx2/mach-pca100.c ? ? ? ? ? ? ?| ? 10 +-
> ?arch/arm/mach-mx3/mach-armadillo5x0.c ? ? ? ?| ? 10 +-
> ?arch/arm/mach-mx3/mach-mx31lite.c ? ? ? ? ? ?| ? ?5 +-
> ?arch/arm/mach-mx3/mach-mx31moboard.c ? ? ? ? | ? ?5 +-
> ?arch/arm/mach-mx3/mach-pcm037.c ? ? ? ? ? ? ?| ? 10 +-
> ?arch/arm/mach-mx3/mach-pcm043.c ? ? ? ? ? ? ?| ? ?5 +-
> ?arch/arm/mach-pxa/Kconfig ? ? ? ? ? ? ? ? ? ?| ? ?4 +
> ?arch/arm/mach-pxa/Makefile ? ? ? ? ? ? ? ? ? | ? ?1 +
> ?arch/arm/mach-pxa/cm-x300.c ? ? ? ? ? ? ? ? ?| ?102 ++++++++++++++
> ?arch/arm/mach-pxa/include/mach/ohci.h ? ? ? ?| ? ?3 +
> ?arch/arm/mach-pxa/include/mach/pxa310-ulpi.h | ? 19 +++
> ?arch/arm/mach-pxa/include/mach/regs-u2d.h ? ?| ? ?2 +
> ?arch/arm/mach-pxa/pxa310-ulpi.c ? ? ? ? ? ? ?| ?110 +++++++++++++++
> ?drivers/usb/host/ohci-pxa27x.c ? ? ? ? ? ? ? | ?183 ++++++++++++++++++++++++++
> ?drivers/usb/otg/Kconfig ? ? ? ? ? ? ? ? ? ? ?| ? ?2 -
> ?drivers/usb/otg/ulpi.c ? ? ? ? ? ? ? ? ? ? ? | ? 65 ++++++++-
> ?include/linux/usb/ulpi.h ? ? ? ? ? ? ? ? ? ? | ? 25 ++++-
> ?17 files changed, 542 insertions(+), 19 deletions(-)
> ?create mode 100644 arch/arm/mach-pxa/include/mach/pxa310-ulpi.h
> ?create mode 100644 arch/arm/mach-pxa/pxa310-ulpi.c
>
>


From amit.kucheria at canonical.com  Wed Jun  2 04:38:07 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Wed, 2 Jun 2010 11:38:07 +0300
Subject: [PATCH 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <20100602083807.GM2346@matterhorn.lan>

On 10 Jun 01, Jason Wang wrote:
> 3-stack is a reference board from Freescale for their i.MX51 SoC.
> 
> Add board definition, Kconfig and Makefile to enable Freescale 3-stack
> board.
> 
> Boot tested on a i.MX51 3-stack Rev2.0 board
> 
> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
> ---
>  arch/arm/mach-mx5/Kconfig                       |    5 +
>  arch/arm/mach-mx5/Makefile                      |    2 +-
>  arch/arm/mach-mx5/board-mx51_3ds.c              |  356 +++++++++++++++++++++++
>  arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   73 +++++
>  arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h |   43 +++
>  5 files changed, 478 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
>  create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
>  create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h
> 
> diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
> index 1576d51..6d45f44 100644
> --- a/arch/arm/mach-mx5/Kconfig
> +++ b/arch/arm/mach-mx5/Kconfig
> @@ -15,4 +15,9 @@ config MACH_MX51_BABBAGE
>  	  u-boot. This includes specific configurations for the board and its
>  	  peripherals.
>  
> +config MACH_MX51_3DS
> +	bool "Support MX51PDK (3DS)"
> +	help
> +	  Include support for MX51PDK (3DS) platform. This includes specific
> +	  configurations for the board and its peripherals.
>  endif
> diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
> index bf23f86..c757c59 100644
> --- a/arch/arm/mach-mx5/Makefile
> +++ b/arch/arm/mach-mx5/Makefile
> @@ -6,4 +6,4 @@
>  obj-y   := cpu.o mm.o clock-mx51.o devices.o
>  
>  obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
> -
> +obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
> diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
> new file mode 100644
> index 0000000..604fb26
> --- /dev/null
> +++ b/arch/arm/mach-mx5/board-mx51_3ds.c
> @@ -0,0 +1,356 @@
> +/*
> + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +#include <linux/smsc911x.h>
> +#include <linux/input/matrix_keypad.h>
> +
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/time.h>
> +
> +#include <mach/hardware.h>
> +#include <mach/common.h>
> +#include <mach/iomux-mx51-3ds.h>
> +#include <mach/board-mx51_3ds.h>
> +#include <mach/gpio.h>
> +#include <mach/imx-uart.h>
> +
> +#include "devices.h"
> +
> +static struct pad_desc mx51_3ds_pads[] = {
> +	/* UART1 */
> +	MX51_3DS_PAD_UART1_RXD__UART1_RXD,
> +	MX51_3DS_PAD_UART1_TXD__UART1_TXD,
> +	MX51_3DS_PAD_UART1_RTS__UART1_RTS,
> +	MX51_3DS_PAD_UART1_CTS__UART1_CTS,
> +
> +	/* UART2 */
> +	MX51_3DS_PAD_UART2_RXD__UART2_RXD,
> +	MX51_3DS_PAD_UART2_TXD__UART2_TXD,
> +	MX51_3DS_PAD_EIM_D25__UART2_CTS,
> +	MX51_3DS_PAD_EIM_D26__UART2_RTS,
> +
> +	/* UART3 */
> +	MX51_3DS_PAD_GPIO_1_22__UART3_RXD,
> +	MX51_3DS_PAD_GPIO_1_23__UART3_TXD,
> +	MX51_3DS_PAD_EIM_D24__UART3_CTS,
> +	MX51_3DS_PAD_EIM_D27__UART3_RTS,
> +
> +	/* CPLD PARENT IRQ PIN */
> +	MX51_3DS_PAD_GPIO_1_6__GPIO1_6,
> +
> +	/* KPP */
> +	MX51_PAD_KEY_ROW0__KEY_ROW0,
> +	MX51_PAD_KEY_ROW1__KEY_ROW1,
> +	MX51_PAD_KEY_ROW2__KEY_ROW2,
> +	MX51_PAD_KEY_ROW3__KEY_ROW3,
> +	MX51_PAD_KEY_COL0__KEY_COL0,
> +	MX51_PAD_KEY_COL1__KEY_COL1,
> +	MX51_PAD_KEY_COL2__KEY_COL2,
> +	MX51_PAD_KEY_COL3__KEY_COL3,
> +	MX51_PAD_KEY_COL4__KEY_COL4,
> +	MX51_PAD_KEY_COL5__KEY_COL5,
> +};
> +
> +#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
> +static int mx51_3ds_board_keymap[] = {
> +	KEY(0, 0, KEY_1),
> +	KEY(0, 1, KEY_2),
> +	KEY(0, 2, KEY_3),
> +	KEY(0, 3, KEY_F1),
> +	KEY(0, 4, KEY_UP),
> +	KEY(0, 5, KEY_F2),
> +
> +	KEY(1, 0, KEY_4),
> +	KEY(1, 1, KEY_5),
> +	KEY(1, 2, KEY_6),
> +	KEY(1, 3, KEY_LEFT),
> +	KEY(1, 4, KEY_SELECT),
> +	KEY(1, 5, KEY_RIGHT),
> +
> +	KEY(2, 0, KEY_7),
> +	KEY(2, 1, KEY_8),
> +	KEY(2, 2, KEY_9),
> +	KEY(2, 3, KEY_F3),
> +	KEY(2, 4, KEY_DOWN),
> +	KEY(2, 5, KEY_F4),
> +
> +	KEY(3, 0, KEY_0),
> +	KEY(3, 1, KEY_OK),
> +	KEY(3, 2, KEY_ESC),
> +	KEY(3, 3, KEY_ENTER),
> +	KEY(3, 4, KEY_MENU),
> +	KEY(3, 5, KEY_BACK)
> +};
> +
> +static struct resource mx51_3ds_kpp_resources[] = {
> +	{
> +		.start = MX51_MXC_INT_KPP,
> +		.end = MX51_MXC_INT_KPP,
> +		.flags = IORESOURCE_IRQ,
> +	} , {
> +		.start = MX51_KPP_BASE_ADDR,
> +		.end = MX51_KPP_BASE_ADDR + 0x8 - 1,
> +		.flags = IORESOURCE_MEM,
> +	},
> +};
> +
> +static struct matrix_keymap_data mx51_3ds_map_data = {
> +	.keymap		= mx51_3ds_board_keymap,
> +	.keymap_size	= ARRAY_SIZE(mx51_3ds_board_keymap),
> +};
> +
> +static struct platform_device mx51_3ds_keypad_device = {
> +	.name = "imx-keypad",
> +	.id = 0,
> +	.num_resources = ARRAY_SIZE(mx51_3ds_kpp_resources),
> +	.resource = mx51_3ds_kpp_resources,
> +	.dev = {
> +		.platform_data = &mx51_3ds_map_data,
> +	},
> +};

Please move this platform device and the smsc below to devices.c, add the
required devices for the board to an array in the board file and register it
in board_init using

	platform_add_devices(devices, ARRAY_SIZE(devices));

See the babbage board code.

> +static void mxc_init_keypad(void)
> +{
> +	(void)platform_device_register(&mx51_3ds_keypad_device);
> +}
> +#else
> +static inline void mxc_init_keypad(void)
> +{
> +}
> +#endif
> +
> +
> +static u32 cpld_base_addr;
> +
> +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
> +static struct resource smsc911x_resources[] = {
> +	{
> +		.flags = IORESOURCE_MEM,
> +	} , {
> +		.start = LAN9217_IRQ,
> +		.end = LAN9217_IRQ,
> +		.flags = IORESOURCE_IRQ,
> +	},
> +};
> +
> +struct smsc911x_platform_config smsc911x_config = {
> +	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
> +	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
> +};
> +
> +static struct platform_device smsc_lan9217_device = {
> +	.name = "smsc911x",
> +	.id = 0,
> +	.dev = {
> +		.platform_data = &smsc911x_config,
> +	},
> +	.num_resources = ARRAY_SIZE(smsc911x_resources),
> +	.resource = smsc911x_resources,
> +};

Separate out the addition of the smsc device into a separate patch. It isn't
really required for board bringup.

> +static void mxc_init_enet(void)
> +{
> +	if (cpld_base_addr) {
> +		smsc_lan9217_device.resource[0].start =
> +		    LAN9217_BASE_ADDR(cpld_base_addr);
> +		smsc_lan9217_device.resource[0].end =
> +		    LAN9217_BASE_ADDR(cpld_base_addr) + 0x100;
> +		(void)platform_device_register(&smsc_lan9217_device);
> +	}
> +}
> +#else
> +static inline void mxc_init_enet(void)
> +{
> +}
> +#endif
> +
> +static u32 brd_io;
> +static void expio_ack_irq(u32 irq);
> +
> +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
> +{
> +	u32 imr_val;
> +	u32 int_valid;
> +	u32 expio_irq;
> +
> +	desc->chip->mask(irq);	/* irq = gpio irq number */
> +
> +	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
> +	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
> +
> +	if (unlikely(!int_valid))
> +		goto out;
> +
> +	expio_irq = MXC_BOARD_IRQ_START;
> +	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
> +		struct irq_desc *d;
> +		if ((int_valid & 1) == 0)
> +			continue;
> +		d = irq_desc + expio_irq;
> +		if (unlikely(!(d->handle_irq))) {
> +			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
> +			BUG();	/* oops */
> +		}
> +		d->handle_irq(expio_irq, d);
> +	}
> +
> +out:
> +	desc->chip->ack(irq);
> +	desc->chip->unmask(irq);
> +}

Just noticed (half-way through the review) that Sascha has commented on most
of the major problems.

Could you document expio a little better (how debug board works, at the top of
this section)? Also, please move expio to another patch as well, I don't
think a debug board is required for board bringup.

> +/*
> + * Disable an expio pin's interrupt by setting the bit in the imr.
> + * @param irq		an expio virtual irq number
> + */
> +static void expio_mask_irq(u32 irq)
> +{
> +	u16 reg;
> +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> +	/* mask the interrupt */
> +	reg = __raw_readw(brd_io + INTR_MASK_REG);
> +	reg |= (1 << expio);
> +	__raw_writew(reg, brd_io + INTR_MASK_REG);
> +}
> +
> +/*
> + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
> + * @param irq		an expanded io virtual irq number
> + */
> +static void expio_ack_irq(u32 irq)
> +{
> +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> +	/* clear the interrupt status */
> +	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
> +	__raw_writew(0, brd_io + INTR_RESET_REG);
> +	/* mask the interrupt */
> +	expio_mask_irq(irq);
> +}
> +
> +/*
> + * Enable a expio pin's interrupt by clearing the bit in the imr.
> + * @param irq		a expio virtual irq number
> + */
> +static void expio_unmask_irq(u32 irq)
> +{
> +	u16 reg;
> +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> +	/* unmask the interrupt */
> +	reg = __raw_readw(brd_io + INTR_MASK_REG);
> +	reg &= ~(1 << expio);
> +	__raw_writew(reg, brd_io + INTR_MASK_REG);
> +}
> +
> +static struct irq_chip expio_irq_chip = {
> +	.ack = expio_ack_irq,
> +	.mask = expio_mask_irq,
> +	.unmask = expio_unmask_irq,
> +};
> +
> +static int __init mxc_expio_init(void)
> +{
> +	int i;
> +
> +	brd_io = (u32) ioremap(BOARD_IO_ADDR(MX51_CS5_BASE_ADDR), SZ_4K);
> +	if (brd_io == 0)
> +		return -ENOMEM;
> +
> +	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
> +	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
> +	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
> +		pr_info("3-Stack Debug board not detected\n");
> +		cpld_base_addr = 0;
> +		return -ENODEV;
> +	} else {
> +		cpld_base_addr = MX51_CS5_BASE_ADDR;
> +	}
> +
> +	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
> +		readw(brd_io + CPLD_CODE_VER_REG));
> +
> +	/*
> +	 * Configure INT line as GPIO input
> +	 */
> +	gpio_request(MX51_3DS_CPLD_IRQ_PIN, "gpio1_6");
> +	gpio_direction_input(MX51_3DS_CPLD_IRQ_PIN);
> +
> +	/* disable the interrupt and clear the status */
> +	__raw_writew(0, brd_io + INTR_MASK_REG);
> +	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
> +	__raw_writew(0, brd_io + INTR_RESET_REG);
> +	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
> +	for (i = MXC_BOARD_IRQ_START;
> +	     i < (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS); i++) {
> +		set_irq_chip(i, &expio_irq_chip);
> +		set_irq_handler(i, handle_level_irq);
> +		set_irq_flags(i, IRQF_VALID);
> +	}
> +	set_irq_type(EXPIO_PARENT_INT, IRQF_TRIGGER_LOW);
> +	set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler);
> +
> +	return 0;
> +}
> +
> +/* Serial ports */
> +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
> +static struct imxuart_platform_data uart_pdata = {
> +	.flags = IMXUART_HAVE_RTSCTS,
> +};
> +
> +static inline void mxc_init_imx_uart(void)
> +{
> +	mxc_register_device(&mxc_uart_device0, &uart_pdata);
> +	mxc_register_device(&mxc_uart_device1, &uart_pdata);
> +	mxc_register_device(&mxc_uart_device2, &uart_pdata);
> +}
> +#else /* !SERIAL_IMX */
> +static inline void mxc_init_imx_uart(void)
> +{
> +}
> +#endif /* SERIAL_IMX */
> +
> +/*
> + * Board specific initialization.
> + */
> +static void __init mxc_board_init(void)
> +{
> +	mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
> +					ARRAY_SIZE(mx51_3ds_pads));
> +	mxc_init_imx_uart();
> +	mxc_expio_init();
> +	mxc_init_enet();
> +	mxc_init_keypad();
> +}
> +
> +static void __init mx51_3ds_timer_init(void)
> +{
> +	mx51_clocks_init(32768, 24000000, 22579200, 24576000);
> +}
> +
> +static struct sys_timer mxc_timer = {
> +	.init	= mx51_3ds_timer_init,
> +};
> +
> +MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
> +	.phys_io = MX51_AIPS1_BASE_ADDR,
> +	.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
> +	.boot_params = PHYS_OFFSET + 0x100,
> +	.map_io = mx51_map_io,
> +	.init_irq = mx51_init_irq,
> +	.init_machine = mxc_board_init,
> +	.timer = &mxc_timer,
> +MACHINE_END
> diff --git a/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
> new file mode 100644
> index 0000000..6900a7f
> --- /dev/null
> +++ b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
> @@ -0,0 +1,73 @@
> +/*
> + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#ifndef __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
> +#define __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
> +
> +/*
> + * @file plat-mxc/include/mach/board-mx51_3ds.h
> + *
> + * @brief This file contains all the board level configuration options.
> + *
> + * It currently hold the options defined for MX51 3Stack Platform.
> + *
> + */
> +
> +#define MXC_LL_UART_PADDR	UART1_BASE_ADDR
> +#define MXC_LL_UART_VADDR	AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
> +
> +#define DEBUG_BOARD_BASE_ADDRESS(n)	(n)
> +/* LAN9217 ethernet base address */
> +#define LAN9217_BASE_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n))
> +/* External UART */
> +#define UARTA_BASE_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n) + 0x8000)
> +#define UARTB_BASE_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n) + 0x10000)
> +
> +#define BOARD_IO_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n) + 0x20000)
> +/* LED switchs */
> +#define LED_SWITCH_REG		0x00
> +/* buttons */
> +#define SWITCH_BUTTONS_REG	0x08
> +/* status, interrupt */
> +#define INTR_STATUS_REG	0x10
> +#define INTR_MASK_REG		0x38
> +#define INTR_RESET_REG		0x20
> +/* magic word for debug CPLD */
> +#define MAGIC_NUMBER1_REG	0x40
> +#define MAGIC_NUMBER2_REG	0x48
> +/* CPLD code version */
> +#define CPLD_CODE_VER_REG	0x50
> +/* magic word for debug CPLD */
> +#define MAGIC_NUMBER3_REG	0x58
> +/* module reset register*/
> +#define MODULE_RESET_REG	0x60
> +/* CPU ID and Personality ID */
> +#define MCU_BOARD_ID_REG	0x68
> +
> +/* interrupts like external uart , external ethernet etc*/
> +#define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
> +
> +#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
> +
> +#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
> +#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
> +#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
> +#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
> +#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
> +
> +/* This is System IRQ used by LAN9217 */
> +#define LAN9217_IRQ	EXPIO_INT_ENET
> +
> +/* Define CPLD interrupt pin */
> +#define MX51_3DS_CPLD_IRQ_PIN	(GPIO_PORTA + 6)
> +
> +#endif	/* __ASM_ARCH_MXC_BOARD_MX51_3DS_H__ */
> diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h b/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h
> new file mode 100644
> index 0000000..33f1141

Get rid of this file and add what you need to the common iomux-mx51.h

> --- /dev/null
> +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h
> @@ -0,0 +1,43 @@
> +/*
> + * Copyright (C) 2010 Freescale Semiconductor, Inc.
> + * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +#ifndef __MACH_IOMUX_MX51_3DS_H__
> +#define __MACH_IOMUX_MX51_3DS_H__
> +
> +#include <mach/iomux-mx51.h>
> +
> +/* UART1 */
> +#define MX51_3DS_PAD_UART1_RXD__UART1_RXD	MX51_PAD_UART1_RXD__UART1_RXD
> +#define MX51_3DS_PAD_UART1_TXD__UART1_TXD	MX51_PAD_UART1_TXD__UART1_TXD
> +#define MX51_3DS_PAD_UART1_RTS__UART1_RTS	MX51_PAD_UART1_RTS__UART1_RTS
> +#define MX51_3DS_PAD_UART1_CTS__UART1_CTS	MX51_PAD_UART1_CTS__UART1_CTS
> +
> +/* UART2 */
> +#define MX51_3DS_PAD_UART2_RXD__UART2_RXD	MX51_PAD_UART2_RXD__UART2_RXD
> +#define MX51_3DS_PAD_UART2_TXD__UART2_TXD	MX51_PAD_UART2_TXD__UART2_TXD
> +#define MX51_3DS_PAD_EIM_D25__UART2_CTS		IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT4, 0x0, 0, \
> +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> +#define MX51_3DS_PAD_EIM_D26__UART2_RTS		IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT4, 0x9e8, 3, \
> +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> +
> +/* UART3 */
> +#define MX51_3DS_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, \
> +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> +#define MX51_3DS_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, \
> +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> +#define MX51_3DS_PAD_EIM_D24__UART3_CTS		IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, \
> +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> +#define MX51_3DS_PAD_EIM_D27__UART3_RTS		IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 3, \
> +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> +/* CPLD */
> +#define MX51_3DS_PAD_GPIO_1_6__GPIO1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
> +
> +#endif /* __MACH_IOMUX_MX51_3DS_H__ */
> -- 
> 1.5.6.5
> 

-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------


From s.hauer at pengutronix.de  Wed Jun  2 04:52:06 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 2 Jun 2010 10:52:06 +0200
Subject: [PATCH 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <20100602083807.GM2346@matterhorn.lan>
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
	<20100602083807.GM2346@matterhorn.lan>
Message-ID: <20100602085206.GQ26820@pengutronix.de>

On Wed, Jun 02, 2010 at 11:38:07AM +0300, Amit Kucheria wrote:
> > +	.dev = {
> > +		.platform_data = &smsc911x_config,
> > +	},
> > +	.num_resources = ARRAY_SIZE(smsc911x_resources),
> > +	.resource = smsc911x_resources,
> > +};
> 
> Separate out the addition of the smsc device into a separate patch. It isn't
> really required for board bringup.

No need to do this.

> 
> > +static void mxc_init_enet(void)
> > +{
> > +	if (cpld_base_addr) {
> > +		smsc_lan9217_device.resource[0].start =
> > +		    LAN9217_BASE_ADDR(cpld_base_addr);
> > +		smsc_lan9217_device.resource[0].end =
> > +		    LAN9217_BASE_ADDR(cpld_base_addr) + 0x100;
> > +		(void)platform_device_register(&smsc_lan9217_device);
> > +	}
> > +}
> > +#else
> > +static inline void mxc_init_enet(void)
> > +{
> > +}
> > +#endif
> > +
> > +static u32 brd_io;
> > +static void expio_ack_irq(u32 irq);
> > +
> > +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
> > +{
> > +	u32 imr_val;
> > +	u32 int_valid;
> > +	u32 expio_irq;
> > +
> > +	desc->chip->mask(irq);	/* irq = gpio irq number */
> > +
> > +	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
> > +	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
> > +
> > +	if (unlikely(!int_valid))
> > +		goto out;
> > +
> > +	expio_irq = MXC_BOARD_IRQ_START;
> > +	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
> > +		struct irq_desc *d;
> > +		if ((int_valid & 1) == 0)
> > +			continue;
> > +		d = irq_desc + expio_irq;
> > +		if (unlikely(!(d->handle_irq))) {
> > +			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
> > +			BUG();	/* oops */
> > +		}
> > +		d->handle_irq(expio_irq, d);
> > +	}
> > +
> > +out:
> > +	desc->chip->ack(irq);
> > +	desc->chip->unmask(irq);
> > +}
> 
> Just noticed (half-way through the review) that Sascha has commented on most
> of the major problems.
> 
> Could you document expio a little better (how debug board works, at the top of
> this section)? Also, please move expio to another patch as well, I don't
> think a debug board is required for board bringup.

No need to do split this out to another patch, but we should really think about
adding a generic debugboard file common to the 3ds boards. Something like

debugboard_3ds_init(unsigned long base, int irq)

would be nice.

> 
> > +/*
> > + * Disable an expio pin's interrupt by setting the bit in the imr.
> > + * @param irq		an expio virtual irq number
> > + */
> > +static void expio_mask_irq(u32 irq)
> > +{
> > +	u16 reg;
> > +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> > +	/* mask the interrupt */
> > +	reg = __raw_readw(brd_io + INTR_MASK_REG);
> > +	reg |= (1 << expio);
> > +	__raw_writew(reg, brd_io + INTR_MASK_REG);
> > +}
> > +
> > +/*
> > + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
> > + * @param irq		an expanded io virtual irq number
> > + */
> > +static void expio_ack_irq(u32 irq)
> > +{
> > +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> > +	/* clear the interrupt status */
> > +	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
> > +	__raw_writew(0, brd_io + INTR_RESET_REG);
> > +	/* mask the interrupt */
> > +	expio_mask_irq(irq);
> > +}
> > +
> > +/*
> > + * Enable a expio pin's interrupt by clearing the bit in the imr.
> > + * @param irq		a expio virtual irq number
> > + */
> > +static void expio_unmask_irq(u32 irq)
> > +{
> > +	u16 reg;
> > +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> > +	/* unmask the interrupt */
> > +	reg = __raw_readw(brd_io + INTR_MASK_REG);
> > +	reg &= ~(1 << expio);
> > +	__raw_writew(reg, brd_io + INTR_MASK_REG);
> > +}
> > +
> > +static struct irq_chip expio_irq_chip = {
> > +	.ack = expio_ack_irq,
> > +	.mask = expio_mask_irq,
> > +	.unmask = expio_unmask_irq,
> > +};
> > +
> > +static int __init mxc_expio_init(void)
> > +{
> > +	int i;
> > +
> > +	brd_io = (u32) ioremap(BOARD_IO_ADDR(MX51_CS5_BASE_ADDR), SZ_4K);
> > +	if (brd_io == 0)
> > +		return -ENOMEM;
> > +
> > +	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
> > +	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
> > +	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
> > +		pr_info("3-Stack Debug board not detected\n");
> > +		cpld_base_addr = 0;
> > +		return -ENODEV;
> > +	} else {
> > +		cpld_base_addr = MX51_CS5_BASE_ADDR;
> > +	}
> > +
> > +	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
> > +		readw(brd_io + CPLD_CODE_VER_REG));
> > +
> > +	/*
> > +	 * Configure INT line as GPIO input
> > +	 */
> > +	gpio_request(MX51_3DS_CPLD_IRQ_PIN, "gpio1_6");
> > +	gpio_direction_input(MX51_3DS_CPLD_IRQ_PIN);
> > +
> > +	/* disable the interrupt and clear the status */
> > +	__raw_writew(0, brd_io + INTR_MASK_REG);
> > +	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
> > +	__raw_writew(0, brd_io + INTR_RESET_REG);
> > +	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
> > +	for (i = MXC_BOARD_IRQ_START;
> > +	     i < (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS); i++) {
> > +		set_irq_chip(i, &expio_irq_chip);
> > +		set_irq_handler(i, handle_level_irq);
> > +		set_irq_flags(i, IRQF_VALID);
> > +	}
> > +	set_irq_type(EXPIO_PARENT_INT, IRQF_TRIGGER_LOW);
> > +	set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler);
> > +
> > +	return 0;
> > +}
> > +
> > +/* Serial ports */
> > +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
> > +static struct imxuart_platform_data uart_pdata = {
> > +	.flags = IMXUART_HAVE_RTSCTS,
> > +};
> > +
> > +static inline void mxc_init_imx_uart(void)
> > +{
> > +	mxc_register_device(&mxc_uart_device0, &uart_pdata);
> > +	mxc_register_device(&mxc_uart_device1, &uart_pdata);
> > +	mxc_register_device(&mxc_uart_device2, &uart_pdata);
> > +}
> > +#else /* !SERIAL_IMX */
> > +static inline void mxc_init_imx_uart(void)
> > +{
> > +}
> > +#endif /* SERIAL_IMX */
> > +
> > +/*
> > + * Board specific initialization.
> > + */
> > +static void __init mxc_board_init(void)
> > +{
> > +	mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
> > +					ARRAY_SIZE(mx51_3ds_pads));
> > +	mxc_init_imx_uart();
> > +	mxc_expio_init();
> > +	mxc_init_enet();
> > +	mxc_init_keypad();
> > +}
> > +
> > +static void __init mx51_3ds_timer_init(void)
> > +{
> > +	mx51_clocks_init(32768, 24000000, 22579200, 24576000);
> > +}
> > +
> > +static struct sys_timer mxc_timer = {
> > +	.init	= mx51_3ds_timer_init,
> > +};
> > +
> > +MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
> > +	.phys_io = MX51_AIPS1_BASE_ADDR,
> > +	.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
> > +	.boot_params = PHYS_OFFSET + 0x100,
> > +	.map_io = mx51_map_io,
> > +	.init_irq = mx51_init_irq,
> > +	.init_machine = mxc_board_init,
> > +	.timer = &mxc_timer,
> > +MACHINE_END
> > diff --git a/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
> > new file mode 100644
> > index 0000000..6900a7f
> > --- /dev/null
> > +++ b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
> > @@ -0,0 +1,73 @@
> > +/*
> > + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
> > + *
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +#ifndef __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
> > +#define __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
> > +
> > +/*
> > + * @file plat-mxc/include/mach/board-mx51_3ds.h
> > + *
> > + * @brief This file contains all the board level configuration options.
> > + *
> > + * It currently hold the options defined for MX51 3Stack Platform.
> > + *
> > + */
> > +
> > +#define MXC_LL_UART_PADDR	UART1_BASE_ADDR
> > +#define MXC_LL_UART_VADDR	AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
> > +
> > +#define DEBUG_BOARD_BASE_ADDRESS(n)	(n)
> > +/* LAN9217 ethernet base address */
> > +#define LAN9217_BASE_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n))
> > +/* External UART */
> > +#define UARTA_BASE_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n) + 0x8000)
> > +#define UARTB_BASE_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n) + 0x10000)
> > +
> > +#define BOARD_IO_ADDR(n)	(DEBUG_BOARD_BASE_ADDRESS(n) + 0x20000)
> > +/* LED switchs */
> > +#define LED_SWITCH_REG		0x00
> > +/* buttons */
> > +#define SWITCH_BUTTONS_REG	0x08
> > +/* status, interrupt */
> > +#define INTR_STATUS_REG	0x10
> > +#define INTR_MASK_REG		0x38
> > +#define INTR_RESET_REG		0x20
> > +/* magic word for debug CPLD */
> > +#define MAGIC_NUMBER1_REG	0x40
> > +#define MAGIC_NUMBER2_REG	0x48
> > +/* CPLD code version */
> > +#define CPLD_CODE_VER_REG	0x50
> > +/* magic word for debug CPLD */
> > +#define MAGIC_NUMBER3_REG	0x58
> > +/* module reset register*/
> > +#define MODULE_RESET_REG	0x60
> > +/* CPU ID and Personality ID */
> > +#define MCU_BOARD_ID_REG	0x68
> > +
> > +/* interrupts like external uart , external ethernet etc*/
> > +#define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
> > +
> > +#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
> > +
> > +#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
> > +#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
> > +#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
> > +#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
> > +#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
> > +
> > +/* This is System IRQ used by LAN9217 */
> > +#define LAN9217_IRQ	EXPIO_INT_ENET
> > +
> > +/* Define CPLD interrupt pin */
> > +#define MX51_3DS_CPLD_IRQ_PIN	(GPIO_PORTA + 6)
> > +
> > +#endif	/* __ASM_ARCH_MXC_BOARD_MX51_3DS_H__ */
> > diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h b/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h
> > new file mode 100644
> > index 0000000..33f1141
> 
> Get rid of this file and add what you need to the common iomux-mx51.h
> 
> > --- /dev/null
> > +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h
> > @@ -0,0 +1,43 @@
> > +/*
> > + * Copyright (C) 2010 Freescale Semiconductor, Inc.
> > + * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +#ifndef __MACH_IOMUX_MX51_3DS_H__
> > +#define __MACH_IOMUX_MX51_3DS_H__
> > +
> > +#include <mach/iomux-mx51.h>
> > +
> > +/* UART1 */
> > +#define MX51_3DS_PAD_UART1_RXD__UART1_RXD	MX51_PAD_UART1_RXD__UART1_RXD
> > +#define MX51_3DS_PAD_UART1_TXD__UART1_TXD	MX51_PAD_UART1_TXD__UART1_TXD
> > +#define MX51_3DS_PAD_UART1_RTS__UART1_RTS	MX51_PAD_UART1_RTS__UART1_RTS
> > +#define MX51_3DS_PAD_UART1_CTS__UART1_CTS	MX51_PAD_UART1_CTS__UART1_CTS
> > +
> > +/* UART2 */
> > +#define MX51_3DS_PAD_UART2_RXD__UART2_RXD	MX51_PAD_UART2_RXD__UART2_RXD
> > +#define MX51_3DS_PAD_UART2_TXD__UART2_TXD	MX51_PAD_UART2_TXD__UART2_TXD
> > +#define MX51_3DS_PAD_EIM_D25__UART2_CTS		IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT4, 0x0, 0, \
> > +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> > +#define MX51_3DS_PAD_EIM_D26__UART2_RTS		IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT4, 0x9e8, 3, \
> > +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> > +
> > +/* UART3 */
> > +#define MX51_3DS_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, \
> > +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> > +#define MX51_3DS_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, \
> > +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> > +#define MX51_3DS_PAD_EIM_D24__UART3_CTS		IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, \
> > +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> > +#define MX51_3DS_PAD_EIM_D27__UART3_RTS		IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 3, \
> > +						(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST))
> > +/* CPLD */
> > +#define MX51_3DS_PAD_GPIO_1_6__GPIO1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
> > +
> > +#endif /* __MACH_IOMUX_MX51_3DS_H__ */
> > -- 
> > 1.5.6.5
> > 
> 
> -- 
> ----------------------------------------------------------------------
> Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
> ----------------------------------------------------------------------
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From sshtylyov at mvista.com  Wed Jun  2 05:26:48 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Wed, 02 Jun 2010 13:26:48 +0400
Subject: [PATCH 3/4] ARM: cns3xxx: Add support for AHCI controllers
In-Reply-To: <20100601165540.GC7123@oksana.dev.rtsoft.ru>
References: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
	<20100601165540.GC7123@oksana.dev.rtsoft.ru>
Message-ID: <4C0623D8.6030701@ru.mvista.com>

Hello.

Anton Vorontsov wrote:

> CNS3xxx chips have AHCI-compatible SATA controller. This patch adds
> the support using generic ahci_platform driver.

> Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>

[...]

> diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
> index 549ad0c..bf6044b 100644
> --- a/arch/arm/mach-cns3xxx/devices.c
> +++ b/arch/arm/mach-cns3xxx/devices.c
> @@ -14,14 +14,75 @@
>  #include <linux/init.h>
>  #include <linux/compiler.h>
>  #include <linux/delay.h>
> +#include <linux/dma-mapping.h>
>  #include <linux/device.h>
>  #include <linux/platform_device.h>
> +#include <linux/ahci_platform.h>
>  #include <linux/mmc/host.h>
>  #include <linux/sdhci-pltfm.h>
>  #include "../../../drivers/mmc/host/sdhci.h"
> +#include "core.h"
>  #include "devices.h"
>  
>  /*
> + * AHCI
> + */
> +static int cns3xxx_ahci_init(struct device *dev)
> +{
> +	u32 tmp;
> +
> +	tmp = MISC_SATA_POWER_MODE;
> +	tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
> +	tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
> +	MISC_SATA_POWER_MODE = tmp;

    Why aren't you using I/O accessors?

WBR, Sergei


From sshtylyov at mvista.com  Wed Jun  2 05:51:51 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Wed, 02 Jun 2010 13:51:51 +0400
Subject: [PATCH 4/4] pata_samsung: Add Samsung PATA controller driver
In-Reply-To: <002a01cb01fd$4cf10a50$e6d31ef0$%kim@samsung.com>
References: <1274948524-2970-1-git-send-email-kgene.kim@samsung.com>
	<1274948524-2970-5-git-send-email-kgene.kim@samsung.com>
	<4BFE46C4.5030007@mvista.com>
	<002a01cb01fd$4cf10a50$e6d31ef0$%kim@samsung.com>
Message-ID: <4C0629B7.4060300@ru.mvista.com>

Hello.

Kukjin Kim wrote:

>>> From: Abhilash Kesavan <a.kesavan at samsung.com>
>>> Adds support for the Samsung PATA controller. This driver is based on the
>>> Libata subsystem and references the earlier patches sent for IDE subsystem.

    Where I those I wonder? :-)
    It's a pity they didn't get accepted.

>>> Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
>>> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>

[...]

>>> +		for (i = 0; i < words; i++, temp_addr++) {
>>> +			wait_for_host_ready(info);
>>> +			writel(*temp_addr, data_addr);
>>> +		}
>>> +	}

>>     Well, if this is pere CF case, 'buflen' can't be odd, but otherwise

    I meant to type "pure". :-)

>> you should handle that case...

>>> +	uint pio_teoc[5] = { 240, 43, 10, 70, 25 };

>>     What timing is this? :-O

> Should have been t2i rec.

    If it's t2i timing, it is incorrect for the first 3 PIO modes.

>>> +	if (cpu_type == TYPE_S3C6400) {
>>> +		ap->ops = &pata_s3c_port_ops;
>>> +		info->sfr_addr = info->ide_addr + 0x1800;
>>> +		info->ide_addr = info->ide_addr + 0x1900;
>>> +		info->fifo_status_reg = 0x94;
>>> +	} else if (cpu_type == TYPE_S5PC100) {
>>> +		ap->ops = &pata_s5p_port_ops;
>>> +		info->sfr_addr = info->ide_addr + 0x1800;
>>> +		info->ide_addr = info->ide_addr + 0x1900;

>>     Does make sense to assign those before *if*.

> Offsets not required for S5PV210/S5PC110.

    pata_s3c_tune_chipset() certainly requires them.

>>> +		info->fifo_status_reg = 0x84;
>>> +	} else {
>>> +		ap->ops = &pata_s5p_port_ops;

>>     You don't assign 'info->ide_addr' here but you'll need it in
>> pata_s3c_tune_chipset() which will be called thru pata_s5p_port_ops!

> The address received at ioremap() is enough for S5PV210/S5PC110..no offset
> needed.

    I only have to restate that pata_s3c_tune_chipset() does use 
'info->ide_addr'. Maybe you shouldn't install this method for S5PV210/S5PC110? 
Or do you mean thgat offset of 0 will work?

>>> +release_mem:
>>> +	release_mem_region(res->start, res->end - res->start + 1);

>>     But you didn't call request_mem_region()!

> I didn't..will remove.

    But you should call request_mem_region() in one or another form...

MBR, Sergei


From richardcochran at gmail.com  Wed Jun  2 05:55:58 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Wed, 2 Jun 2010 11:55:58 +0200
Subject: [PATCH 0/3] Support for three IXP425 based boards
Message-ID: <cover.1275415521.git.richard.cochran@omicron.at>

This patch series adds support for three IXP425 based boards from
OMICRON electronics GmbH. The code has been adapted from the IXDP425
and the NSLU boards.

Richard Cochran (3):
  ixp4xx: support the OMICRON DEVIXP board
  ixp4xx: support the OMICRON MICCPT board
  ixp4xx: support the OMICRON MIC256 board

 arch/arm/mach-ixp4xx/Kconfig                   |   22 +++
 arch/arm/mach-ixp4xx/Makefile                  |    4 +
 arch/arm/mach-ixp4xx/devixp-setup.c            |  225 ++++++++++++++++++++++++
 arch/arm/mach-ixp4xx/include/mach/uncompress.h |    3 +-
 arch/arm/mach-ixp4xx/mic256-setup.c            |  220 +++++++++++++++++++++++
 arch/arm/mach-ixp4xx/miccpt-pci.c              |   78 ++++++++
 arch/arm/mach-ixp4xx/miccpt-setup.c            |  221 +++++++++++++++++++++++
 7 files changed, 772 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-ixp4xx/devixp-setup.c
 create mode 100644 arch/arm/mach-ixp4xx/mic256-setup.c
 create mode 100644 arch/arm/mach-ixp4xx/miccpt-pci.c
 create mode 100644 arch/arm/mach-ixp4xx/miccpt-setup.c



From richardcochran at gmail.com  Wed Jun  2 05:56:40 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Wed, 2 Jun 2010 11:56:40 +0200
Subject: [PATCH 1/3] ixp4xx: support the OMICRON DEVIXP board
In-Reply-To: <cover.1275415521.git.richard.cochran@omicron.at>
References: <cover.1275415521.git.richard.cochran@omicron.at>
Message-ID: <82c0bd9b2deb7cde837f73b7e366e4889ef47160.1275415521.git.richard.cochran@omicron.at>

This patch adds board support for the DEVIXP, which is an IXP425 based
development board by OMICRON electronics, GmbH.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 arch/arm/mach-ixp4xx/Kconfig                   |    7 +
 arch/arm/mach-ixp4xx/Makefile                  |    1 +
 arch/arm/mach-ixp4xx/devixp-setup.c            |  225 ++++++++++++++++++++++++
 arch/arm/mach-ixp4xx/include/mach/uncompress.h |    3 +-
 4 files changed, 235 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-ixp4xx/devixp-setup.c

diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 9e5070d..18f3609 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -8,6 +8,13 @@ menu "Intel IXP4xx Implementation Options"
 
 comment "IXP4xx Platforms"
 
+config MACH_DEVIXP
+	bool "Omicron DEVIXP"
+	help
+	  Say 'Y' here if you want your kernel to support the DEVIXP
+	  board from OMICRON electronics GmbH. For more information on
+	  this platform, see http://www.omicron.at
+
 config MACH_NSLU2
 	bool
 	prompt "Linksys NSLU2"
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index 47d1f60..44eb184 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -20,6 +20,7 @@ obj-pci-$(CONFIG_MACH_FSG)		+= fsg-pci.o
 obj-y	+= common.o
 
 obj-$(CONFIG_ARCH_IXDP4XX)	+= ixdp425-setup.o
+obj-$(CONFIG_MACH_DEVIXP)	+= devixp-setup.o
 obj-$(CONFIG_MACH_AVILA)	+= avila-setup.o
 obj-$(CONFIG_MACH_IXDPG425)	+= coyote-setup.o
 obj-$(CONFIG_ARCH_ADI_COYOTE)	+= coyote-setup.o
diff --git a/arch/arm/mach-ixp4xx/devixp-setup.c b/arch/arm/mach-ixp4xx/devixp-setup.c
new file mode 100644
index 0000000..3dc686c
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/devixp-setup.c
@@ -0,0 +1,225 @@
+/*
+ * arch/arm/mach-ixp4xx/devixp-setup.c
+ *
+ * devixp board-setup
+ *
+ * based nslu2-setup.c, ixdp425-setup.c:
+ *      Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * Author: Richard Cochran <richard.cochran AT omicron.at>
+ *      Copyright (C) 2009 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#ifdef CONFIG_LEDS_CLASS
+#include <linux/leds.h>
+#endif
+
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+static struct resource devixp_flash_resources[2] = {
+	[0] = {
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct mtd_partition devixp_partitions[] = {
+	{
+		.name =		"Recovery Bootloader",
+		.size =		0x00020000,
+		.offset =	0,
+	}, {
+		.name =		"Calibration Data",
+		.size =		0x00020000,
+		.offset =	0x00020000,
+	}, {
+		.name =		"Recovery FPGA",
+		.size =		0x00020000,
+		.offset =	0x00040000,
+	}, {
+		.name =		"Release Bootloader",
+		.size =		0x00020000,
+		.offset =	0x00060000,
+	}, {
+		.name =		"Release FPGA",
+		.size =		0x00020000,
+		.offset =	0x00080000,
+	}, {
+		.name =		"Kernel",
+		.size =		0x00160000,
+		.offset =	0x000a0000,
+	}, {
+		.name =		"Filesystem",
+		.size =		0x00C00000,
+		.offset =	0x00200000
+	}, {
+		.name =		"Persistent Storage",
+		.size =		0x00200000,
+		.offset =	0x00E00000
+	}
+};
+
+static struct flash_platform_data devixp_flash_data[2] = {
+	{
+		.map_name	= "cfi_probe",
+		.parts		= devixp_partitions,
+		.nr_parts	= ARRAY_SIZE(devixp_partitions),
+	}, {
+		.map_name	= "cfi_probe",
+		.parts		= NULL,
+		.nr_parts	= 0,
+	}
+};
+
+static struct platform_device devixp_flash_device[2] = {
+	{
+		.name		= "IXP4XX-Flash",
+		.id		= 0,
+		.dev = {
+			.platform_data = &devixp_flash_data[0],
+		},
+		.resource = &devixp_flash_resources[0],
+		.num_resources = 1,
+	},
+	{
+		.name		= "IXP4XX-Flash",
+		.id		= 1,
+		.dev = {
+			.platform_data = &devixp_flash_data[1],
+		},
+		.resource = &devixp_flash_resources[1],
+		.num_resources = 1,
+	},
+};
+
+
+/* Swap UART's - DEVIXP board has the console on UART2. The following
+ * configuration is used:
+ *      ttyS0 .. UART2
+ *      ttyS1 .. UART1
+ * This way standard images can be used with the kernel that expect
+ * the console on ttyS0.
+ */
+static struct resource devixp_uart_resources[] = {
+	{
+		.start		= IXP4XX_UART2_BASE_PHYS,
+		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
+		.flags		= IORESOURCE_MEM,
+	},
+	{
+		.start		= IXP4XX_UART1_BASE_PHYS,
+		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
+		.flags		= IORESOURCE_MEM,
+	},
+};
+
+static struct plat_serial8250_port devixp_uart_data[] = {
+	{
+		.mapbase	= IXP4XX_UART2_BASE_PHYS,
+		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+		.irq		= IRQ_IXP4XX_UART2,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= IXP4XX_UART_XTAL,
+	},
+	{
+		.mapbase	= IXP4XX_UART1_BASE_PHYS,
+		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+		.irq		= IRQ_IXP4XX_UART1,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= IXP4XX_UART_XTAL,
+	},
+	{ }
+};
+
+static struct platform_device devixp_uart = {
+	.name			= "serial8250",
+	.id			= PLAT8250_DEV_PLATFORM,
+	.dev.platform_data	= devixp_uart_data,
+	.num_resources		= 2,
+	.resource		= devixp_uart_resources,
+};
+
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info ixdp425_plat_eth[] = {
+	{
+		.phy		= 0,
+		.rxq		= 3,
+		.txreadyq	= 20,
+	}, {
+		.phy		= 1,
+		.rxq		= 4,
+		.txreadyq	= 21,
+	}
+};
+
+static struct platform_device ixdp425_eth[] = {
+	{
+		.name			= "ixp4xx_eth",
+		.id			= IXP4XX_ETH_NPEB,
+		.dev.platform_data	= ixdp425_plat_eth,
+	}, {
+		.name			= "ixp4xx_eth",
+		.id			= IXP4XX_ETH_NPEC,
+		.dev.platform_data	= ixdp425_plat_eth + 1,
+	}
+};
+
+
+static struct platform_device *devixp_devices[] __initdata = {
+	&devixp_flash_device[0],
+	&ixdp425_eth[0],
+	&ixdp425_eth[1],
+};
+
+
+static void __init devixp_init(void)
+{
+	ixp4xx_sys_init();
+
+	/* 16MiB Boot Flash */
+	devixp_flash_resources[0].start = IXP4XX_EXP_BUS_BASE(0);
+	devixp_flash_resources[0].end =
+		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+
+	/* 32 MiB Data Flash */
+	devixp_flash_resources[1].start = IXP4XX_EXP_BUS_BASE(2);
+	devixp_flash_resources[1].end =
+		IXP4XX_EXP_BUS_BASE(2) + 2 * ixp4xx_exp_bus_size - 1;
+
+	/* Have this first in order to see debug messages, and so that
+	 * it does *not* get removed if platform_add_devices fails!
+	 */
+	(void)platform_device_register(&devixp_uart);
+
+	platform_add_devices(devixp_devices, ARRAY_SIZE(devixp_devices));
+}
+
+
+MACHINE_START(DEVIXP, "Omicron DEVIXP")
+	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
+	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
+	.boot_params    = 0x100,
+	.map_io		= ixp4xx_map_io,
+	.init_irq	= ixp4xx_init_irq,
+	.timer          = &ixp4xx_timer,
+	.init_machine	= devixp_init,
+MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index 2db0078..e06eb05 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -41,7 +41,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 	 * Some boards are using UART2 as console
 	 */
 	if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
-			 machine_is_gateway7001() || machine_is_wg302v2())
+	    machine_is_gateway7001() || machine_is_wg302v2() ||
+	    machine_is_devixp())
 		uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
 	else
 		uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
-- 
1.6.3.3



From richardcochran at gmail.com  Wed Jun  2 05:57:12 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Wed, 2 Jun 2010 11:57:12 +0200
Subject: [PATCH 2/3] ixp4xx: support the OMICRON MICCPT board
In-Reply-To: <cover.1275415521.git.richard.cochran@omicron.at>
References: <cover.1275415521.git.richard.cochran@omicron.at>
Message-ID: <3a6e8b8456e4edb8d520f93f028bc476ca65b9f0.1275415521.git.richard.cochran@omicron.at>

This patch adds board support for the MICCPT, which is an IXP425 based
board with PCI support, by OMICRON electronics, GmbH.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 arch/arm/mach-ixp4xx/Kconfig                   |    8 +
 arch/arm/mach-ixp4xx/Makefile                  |    2 +
 arch/arm/mach-ixp4xx/include/mach/uncompress.h |    2 +-
 arch/arm/mach-ixp4xx/miccpt-pci.c              |   78 +++++++++
 arch/arm/mach-ixp4xx/miccpt-setup.c            |  221 ++++++++++++++++++++++++
 5 files changed, 310 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-ixp4xx/miccpt-pci.c
 create mode 100644 arch/arm/mach-ixp4xx/miccpt-setup.c

diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 18f3609..97cb601 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -15,6 +15,14 @@ config MACH_DEVIXP
 	  board from OMICRON electronics GmbH. For more information on
 	  this platform, see http://www.omicron.at
 
+config MACH_MICCPT
+	bool "Omicron MICCPT"
+	select PCI
+	help
+	  Say 'Y' here if you want your kernel to support the MICCPT
+	  board from OMICRON electronics GmbH. For more information on
+	  this platform, see http://www.omicron.at
+
 config MACH_NSLU2
 	bool
 	prompt "Linksys NSLU2"
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index 44eb184..8a7edc8 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -11,6 +11,7 @@ obj-pci-$(CONFIG_MACH_IXDPG425)		+= ixdpg425-pci.o
 obj-pci-$(CONFIG_ARCH_ADI_COYOTE)	+= coyote-pci.o
 obj-pci-$(CONFIG_MACH_GTWX5715)		+= gtwx5715-pci.o
 obj-pci-$(CONFIG_MACH_NSLU2)		+= nslu2-pci.o
+obj-pci-$(CONFIG_MACH_MICCPT)		+= miccpt-pci.o
 obj-pci-$(CONFIG_MACH_NAS100D)		+= nas100d-pci.o
 obj-pci-$(CONFIG_MACH_DSMG600)		+= dsmg600-pci.o
 obj-pci-$(CONFIG_MACH_GATEWAY7001)	+= gateway7001-pci.o
@@ -21,6 +22,7 @@ obj-y	+= common.o
 
 obj-$(CONFIG_ARCH_IXDP4XX)	+= ixdp425-setup.o
 obj-$(CONFIG_MACH_DEVIXP)	+= devixp-setup.o
+obj-$(CONFIG_MACH_MICCPT)	+= miccpt-setup.o
 obj-$(CONFIG_MACH_AVILA)	+= avila-setup.o
 obj-$(CONFIG_MACH_IXDPG425)	+= coyote-setup.o
 obj-$(CONFIG_ARCH_ADI_COYOTE)	+= coyote-setup.o
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index e06eb05..1fa3c48 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -42,7 +42,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 	 */
 	if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
 	    machine_is_gateway7001() || machine_is_wg302v2() ||
-	    machine_is_devixp())
+	    machine_is_devixp() || machine_is_miccpt())
 		uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
 	else
 		uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
diff --git a/arch/arm/mach-ixp4xx/miccpt-pci.c b/arch/arm/mach-ixp4xx/miccpt-pci.c
new file mode 100644
index 0000000..6bd67dd
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/miccpt-pci.c
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/mach-ixp4xx/miccpt-pci.c
+ *
+ * MICCPT board-level PCI initialization
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ * Copyright (C) 2006 OMICRON electronics GmbH
+ *
+ * Author: Michael Jochum <michael.jochum at omicron.at>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <asm/mach/pci.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+
+#define MAX_DEV		4
+#define IRQ_LINES	4
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define INTA		1
+#define INTB		2
+#define INTC		3
+#define INTD		4
+
+
+void __init miccpt_pci_preinit(void)
+{
+	set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+	set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+	set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+	set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
+	ixp4xx_pci_preinit();
+}
+
+static int __init miccpt_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	static int pci_irq_table[IRQ_LINES] = {
+		IXP4XX_GPIO_IRQ(INTA),
+		IXP4XX_GPIO_IRQ(INTB),
+		IXP4XX_GPIO_IRQ(INTC),
+		IXP4XX_GPIO_IRQ(INTD)
+	};
+
+	if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
+		return pci_irq_table[(slot + pin - 2) % 4];
+
+	return -1;
+}
+
+struct hw_pci miccpt_pci __initdata = {
+	.nr_controllers = 1,
+	.preinit	= miccpt_pci_preinit,
+	.swizzle	= pci_std_swizzle,
+	.setup		= ixp4xx_setup,
+	.scan		= ixp4xx_scan_bus,
+	.map_irq	= miccpt_map_irq,
+};
+
+int __init miccpt_pci_init(void)
+{
+	if (machine_is_miccpt())
+		pci_common_init(&miccpt_pci);
+	return 0;
+}
+
+subsys_initcall(miccpt_pci_init);
diff --git a/arch/arm/mach-ixp4xx/miccpt-setup.c b/arch/arm/mach-ixp4xx/miccpt-setup.c
new file mode 100644
index 0000000..07b8bc1
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/miccpt-setup.c
@@ -0,0 +1,221 @@
+/*
+ * arch/arm/mach-ixp4xx/miccpt-setup.c
+ *
+ * miccpt board-setup
+ *
+ * based nslu2-setup.c, ixdp425-setup.c:
+ *      Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * Author: Michael Jochum <michael.jochum AT omicron.at>
+ *      Copyright (C) 2006 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#ifdef CONFIG_LEDS_CLASS
+#include <linux/leds.h>
+#endif
+
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+static struct resource miccpt_flash_resources[] = {
+	[0] = {
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct mtd_partition miccpt_partitions[] = {
+	{
+		.name =		"Recovery Bootloader",
+		.size =		0x00020000,
+		.offset =	0,
+	}, {
+		.name =		"Calibration Data",
+		.size =		0x00020000,
+		.offset =	0x00020000,
+	}, {
+		.name =		"Recovery FPGA",
+		.size =		0x00020000,
+		.offset =	0x00040000,
+	}, {
+		.name =		"Release Bootloader",
+		.size =		0x00020000,
+		.offset =	0x00060000,
+	}, {
+		.name =		"Release FPGA",
+		.size =		0x00020000,
+		.offset =	0x00080000,
+	}, {
+		.name =		"Kernel",
+		.size =		0x00160000,
+		.offset =	0x000a0000,
+	}, {
+		.name =		"Filesystem",
+		.size =		MTDPART_SIZ_FULL,
+		.offset =	0x00200000
+	}
+};
+
+static struct flash_platform_data miccpt_flash_data[2] = {
+	{
+		.map_name	= "cfi_probe",
+		.parts		= miccpt_partitions,
+		.nr_parts	= ARRAY_SIZE(miccpt_partitions),
+	}, {
+		.map_name	= "cfi_probe",
+		.parts		= NULL,
+		.nr_parts	= 0,
+	}
+};
+
+static struct platform_device miccpt_flash_device[2] = {
+	{
+		.name		= "IXP4XX-Flash",
+		.id		= 0,
+		.dev = {
+			.platform_data = &miccpt_flash_data[0],
+		},
+		.resource = &miccpt_flash_resources[0],
+		.num_resources = 1,
+	},
+	{
+		.name		= "IXP4XX-Flash",
+		.id		= 1,
+		.dev = {
+			.platform_data = &miccpt_flash_data[1],
+		},
+		.resource = &miccpt_flash_resources[1],
+		.num_resources = 1,
+	},
+};
+
+
+/* Swap UART's - MICCPT board has the console on UART2. The following
+ * configuration is used:
+ *      ttyS0 .. UART2
+ *      ttyS1 .. UART1
+ * This way standard images can be used with the kernel that expect
+ * the console on ttyS0.
+ */
+static struct resource miccpt_uart_resources[] = {
+	{
+		.start		= IXP4XX_UART2_BASE_PHYS,
+		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
+		.flags		= IORESOURCE_MEM,
+	},
+	{
+		.start		= IXP4XX_UART1_BASE_PHYS,
+		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
+		.flags		= IORESOURCE_MEM,
+	},
+};
+
+static struct plat_serial8250_port miccpt_uart_data[] = {
+	{
+		.mapbase	= IXP4XX_UART2_BASE_PHYS,
+		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+		.irq		= IRQ_IXP4XX_UART2,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= IXP4XX_UART_XTAL,
+	},
+	{
+		.mapbase	= IXP4XX_UART1_BASE_PHYS,
+		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+		.irq		= IRQ_IXP4XX_UART1,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= IXP4XX_UART_XTAL,
+	},
+	{ }
+};
+
+static struct platform_device miccpt_uart = {
+	.name			= "serial8250",
+	.id			= PLAT8250_DEV_PLATFORM,
+	.dev.platform_data	= miccpt_uart_data,
+	.num_resources		= 2,
+	.resource		= miccpt_uart_resources,
+};
+
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info ixdp425_plat_eth[] = {
+	{
+		.phy		= 0,
+		.rxq		= 3,
+		.txreadyq	= 20,
+	}, {
+		.phy		= 1,
+		.rxq		= 4,
+		.txreadyq	= 21,
+	}
+};
+
+static struct platform_device ixdp425_eth[] = {
+	{
+		.name			= "ixp4xx_eth",
+		.id			= IXP4XX_ETH_NPEB,
+		.dev.platform_data	= ixdp425_plat_eth,
+	}, {
+		.name			= "ixp4xx_eth",
+		.id			= IXP4XX_ETH_NPEC,
+		.dev.platform_data	= ixdp425_plat_eth + 1,
+	}
+};
+
+
+static struct platform_device *miccpt_devices[] __initdata = {
+	&miccpt_flash_device[0],
+	&ixdp425_eth[0],
+	&ixdp425_eth[1],
+};
+
+
+static void __init miccpt_init(void)
+{
+	ixp4xx_sys_init();
+
+	/* 16MiB Boot Flash */
+	miccpt_flash_resources[0].start = IXP4XX_EXP_BUS_BASE(0);
+	miccpt_flash_resources[0].end =
+		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+
+	/* 32 MiB Data Flash */
+	miccpt_flash_resources[1].start = IXP4XX_EXP_BUS_BASE(2);
+	miccpt_flash_resources[1].end =
+		IXP4XX_EXP_BUS_BASE(2) + 2 * ixp4xx_exp_bus_size - 1;
+
+	/* Have this first in order to see debug messages, and so that
+	 * it does *not* get removed if platform_add_devices fails!
+	 */
+	(void)platform_device_register(&miccpt_uart);
+
+	platform_add_devices(miccpt_devices, ARRAY_SIZE(miccpt_devices));
+}
+
+
+MACHINE_START(MICCPT, "Omicron MICCPT")
+	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
+	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
+	.boot_params    = 0x100,
+	.map_io		= ixp4xx_map_io,
+	.init_irq	= ixp4xx_init_irq,
+	.timer          = &ixp4xx_timer,
+	.init_machine	= miccpt_init,
+MACHINE_END
-- 
1.6.3.3



From richardcochran at gmail.com  Wed Jun  2 05:57:33 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Wed, 2 Jun 2010 11:57:33 +0200
Subject: [PATCH 3/3] ixp4xx: support the OMICRON MIC256 board
In-Reply-To: <cover.1275415521.git.richard.cochran@omicron.at>
References: <cover.1275415521.git.richard.cochran@omicron.at>
Message-ID: <0bd52b6a4a62ec98c9f4a87a556ed36e7279cd44.1275415521.git.richard.cochran@omicron.at>

This patch adds board support for the MIC256, which is an IXP425 based
board by OMICRON electronics, GmbH.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 arch/arm/mach-ixp4xx/Kconfig                   |    7 +
 arch/arm/mach-ixp4xx/Makefile                  |    1 +
 arch/arm/mach-ixp4xx/include/mach/uncompress.h |    2 +-
 arch/arm/mach-ixp4xx/mic256-setup.c            |  220 ++++++++++++++++++++++++
 4 files changed, 229 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-ixp4xx/mic256-setup.c

diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index 97cb601..a7312d2 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -23,6 +23,13 @@ config MACH_MICCPT
 	  board from OMICRON electronics GmbH. For more information on
 	  this platform, see http://www.omicron.at
 
+config MACH_MIC256
+	bool "Omicron MIC256"
+	help
+	  Say 'Y' here if you want your kernel to support the MIC256
+	  board from OMICRON electronics GmbH. For more information on
+	  this platform, see http://www.omicron.at
+
 config MACH_NSLU2
 	bool
 	prompt "Linksys NSLU2"
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index 8a7edc8..14870cd 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -23,6 +23,7 @@ obj-y	+= common.o
 obj-$(CONFIG_ARCH_IXDP4XX)	+= ixdp425-setup.o
 obj-$(CONFIG_MACH_DEVIXP)	+= devixp-setup.o
 obj-$(CONFIG_MACH_MICCPT)	+= miccpt-setup.o
+obj-$(CONFIG_MACH_MIC256)	+= mic256-setup.o
 obj-$(CONFIG_MACH_AVILA)	+= avila-setup.o
 obj-$(CONFIG_MACH_IXDPG425)	+= coyote-setup.o
 obj-$(CONFIG_ARCH_ADI_COYOTE)	+= coyote-setup.o
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index 1fa3c48..384a361 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -42,7 +42,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 	 */
 	if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
 	    machine_is_gateway7001() || machine_is_wg302v2() ||
-	    machine_is_devixp() || machine_is_miccpt())
+	    machine_is_devixp() || machine_is_miccpt() || machine_is_mic256())
 		uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
 	else
 		uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
diff --git a/arch/arm/mach-ixp4xx/mic256-setup.c b/arch/arm/mach-ixp4xx/mic256-setup.c
new file mode 100644
index 0000000..1e27578
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/mic256-setup.c
@@ -0,0 +1,220 @@
+/*
+ * arch/arm/mach-ixp4xx/mic256-setup.c
+ *
+ * mic256 board-setup
+ *
+ * based nslu2-setup.c, ixdp425-setup.c:
+ *      Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * Author: Richard Cochran <richard.cochran AT omicron.at>
+ *      Copyright (C) 2009 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/serial.h>
+#include <linux/serial_8250.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#ifdef CONFIG_LEDS_CLASS
+#include <linux/leds.h>
+#endif
+
+#include <asm/setup.h>
+#include <asm/memory.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+
+static struct resource mic256_flash_resources[1] = {
+	{
+		.flags	= IORESOURCE_MEM,
+	}
+};
+
+static struct mtd_partition mic256_partitions[] = {
+	{
+		.name =		"Recovery Bootloader",
+		.size =		0x00020000,
+		.offset =	0,
+	}, {
+		.name =		"Calibration Data",
+		.size =		0x00020000,
+		.offset =	0x00020000,
+	}, {
+		.name =		"Recovery FPGA",
+		.size =		0x00020000,
+		.offset =	0x00040000,
+	}, {
+		.name =		"Release Bootloader",
+		.size =		0x00020000,
+		.offset =	0x00060000,
+	}, {
+		.name =		"Release FPGA",
+		.size =		0x00020000,
+		.offset =	0x00080000,
+	}, {
+		.name =		"Kernel",
+		.size =		0x00160000,
+		.offset =	0x000a0000,
+	}, {
+		.name =		"Filesystem",
+		.size =		0x00C00000,
+		.offset =	0x00200000
+	}, {
+		.name =		"Persistent Storage",
+		.size =		0x00200000,
+		.offset =	0x00E00000
+	}
+};
+
+static struct flash_platform_data mic256_flash_data[1] = {
+	{
+		.map_name	= "cfi_probe",
+		.parts		= mic256_partitions,
+		.nr_parts	= ARRAY_SIZE(mic256_partitions),
+	}
+};
+
+static struct platform_device mic256_flash_device[1] = {
+	{
+		.name		= "IXP4XX-Flash",
+		.id		= 0,
+		.dev = {
+			.platform_data = &mic256_flash_data[0],
+		},
+		.resource = &mic256_flash_resources[0],
+		.num_resources = 1,
+	}
+};
+
+/* Swap UART's - MIC256 board has the console on UART2. The following
+ * configuration is used:
+ *      ttyS0 .. UART2
+ *      ttyS1 .. UART1
+ * This way standard images can be used with the kernel that expect
+ * the console on ttyS0.
+ */
+static struct resource mic256_uart_resources[] = {
+	{
+		.start		= IXP4XX_UART2_BASE_PHYS,
+		.end		= IXP4XX_UART2_BASE_PHYS + 0x0fff,
+		.flags		= IORESOURCE_MEM,
+	},
+	{
+		.start		= IXP4XX_UART1_BASE_PHYS,
+		.end		= IXP4XX_UART1_BASE_PHYS + 0x0fff,
+		.flags		= IORESOURCE_MEM,
+	},
+};
+
+static struct plat_serial8250_port mic256_uart_data[] = {
+	{
+		.mapbase	= IXP4XX_UART2_BASE_PHYS,
+		.membase	= (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
+		.irq		= IRQ_IXP4XX_UART2,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= IXP4XX_UART_XTAL,
+	},
+	{
+		.mapbase	= IXP4XX_UART1_BASE_PHYS,
+		.membase	= (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
+		.irq		= IRQ_IXP4XX_UART1,
+		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= IXP4XX_UART_XTAL,
+	},
+	{ }
+};
+
+static struct platform_device mic256_uart = {
+	.name			= "serial8250",
+	.id			= PLAT8250_DEV_PLATFORM,
+	.dev.platform_data	= mic256_uart_data,
+	.num_resources		= 2,
+	.resource		= mic256_uart_resources,
+};
+
+static struct gpio_led mic256_led_pins[] = {
+	{
+		.name		= "LED-A",
+		.gpio		= 7,
+	},
+};
+
+static struct gpio_led_platform_data mic256_led_data = {
+	.num_leds		= ARRAY_SIZE(mic256_led_pins),
+	.leds			= mic256_led_pins,
+};
+
+static struct platform_device mic256_leds = {
+	.name			= "leds-gpio",
+	.id			= -1,
+	.dev.platform_data	= &mic256_led_data,
+};
+
+/* Built-in 10/100 Ethernet MAC interfaces */
+static struct eth_plat_info ixdp425_plat_eth[] = {
+	{
+		.phy		= 0,
+		.rxq		= 3,
+		.txreadyq	= 20,
+	}, {
+		.phy		= 1,
+		.rxq		= 4,
+		.txreadyq	= 21,
+	}
+};
+
+static struct platform_device ixdp425_eth[] = {
+	{
+		.name			= "ixp4xx_eth",
+		.id			= IXP4XX_ETH_NPEB,
+		.dev.platform_data	= ixdp425_plat_eth,
+	}, {
+		.name			= "ixp4xx_eth",
+		.id			= IXP4XX_ETH_NPEC,
+		.dev.platform_data	= ixdp425_plat_eth + 1,
+	}
+};
+
+static struct platform_device *mic256_devices[] __initdata = {
+	&mic256_flash_device[0],
+	&mic256_leds,
+	&ixdp425_eth[0],
+	&ixdp425_eth[1],
+};
+
+static void __init mic256_init(void)
+{
+	ixp4xx_sys_init();
+
+	/* 16MiB Boot Flash */
+	mic256_flash_resources[0].start = IXP4XX_EXP_BUS_BASE(0);
+	mic256_flash_resources[0].end =
+		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
+
+	/* Have this first in order to see debug messages, and so that
+	 * it does *not* get removed if platform_add_devices fails!
+	 */
+	(void)platform_device_register(&mic256_uart);
+
+	platform_add_devices(mic256_devices, ARRAY_SIZE(mic256_devices));
+}
+
+MACHINE_START(MIC256, "Omicron MIC256")
+	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
+	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
+	.boot_params    = 0x100,
+	.map_io		= ixp4xx_map_io,
+	.init_irq	= ixp4xx_init_irq,
+	.timer          = &ixp4xx_timer,
+	.init_machine	= mic256_init,
+MACHINE_END
-- 
1.6.3.3



From saeed.bishara at gmail.com  Wed Jun  2 06:34:18 2010
From: saeed.bishara at gmail.com (saeed bishara)
Date: Wed, 2 Jun 2010 13:34:18 +0300
Subject: [PATCH 3/3] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <alpine.LFD.2.00.1006011447410.24526@xanadu.home>
References: <1275404968-12258-1-git-send-email-saeed@marvell.com>
	<1275404968-12258-2-git-send-email-saeed@marvell.com>
	<1275404968-12258-3-git-send-email-saeed@marvell.com>
	<alpine.LFD.2.00.1006011447410.24526@xanadu.home>
Message-ID: <AANLkTiltiNe5W0bRyEYIFJK0nB-Y4DDxHvBMHZntChdB@mail.gmail.com>

> I think this looks like a bit too much code for what this does. ?To
> simplify things, you could:
>
> 1) Duplicate kirkwood_pcie_setup() into kirkwood_pcie0_setup() and
> ? kirkwood_pcie1_setup() instead. ?This will remove a couple
> ? "if (pp->index == 0)" and the snprintf() which could remain
> ? purely static initializations.
>
> 2) Remove bus_to_port() entirely, and store the address of the appropriate
> ? struct pcie_port instance into the sysdata pointer of the pci_bus
> ? structure. ?This struct pcie_port could even be kmalloc'd as needed.
The sysdata already used by arm to store the pci_sys_data, I think we
will have to add a private pointer to the pci_sys_data structure, that
pointer will hold mach specific data per pci controller. this pointer
is needed for any platform that has multiple pci controller. agree?


From weber at corscience.de  Wed Jun  2 07:37:47 2010
From: weber at corscience.de (Thomas Weber)
Date: Wed,  2 Jun 2010 13:37:47 +0200
Subject: [PATCHv2 07/11] OMAP2: Devkit8000: Remove en-/disable for tv panel
In-Reply-To: <1275478671-24563-1-git-send-email-weber@corscience.de>
References: <1275478671-24563-1-git-send-email-weber@corscience.de>
Message-ID: <1275478671-24563-8-git-send-email-weber@corscience.de>

devkit8000_panel_enable_tv and devkit8000_panel_disable_tv are already
done in DSS2 code. So they are no longer needed in board code.

Signed-off-by: Thomas Weber <weber at corscience.de>
---
 arch/arm/mach-omap2/board-devkit8000.c |   12 ------------
 1 files changed, 0 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 59877b1..095dc7a 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -158,16 +158,6 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
 		gpio_set_value(dssdev->reset_gpio, 0);
 }
 
-static int devkit8000_panel_enable_tv(struct omap_dss_device *dssdev)
-{
-
-	return 0;
-}
-
-static void devkit8000_panel_disable_tv(struct omap_dss_device *dssdev)
-{
-}
-
 static struct regulator_consumer_supply devkit8000_vmmc1_supply = {
 	.supply			= "vmmc",
 };
@@ -201,8 +191,6 @@ static struct omap_dss_device devkit8000_tv_device = {
 	.driver_name            = "venc",
 	.type                   = OMAP_DISPLAY_TYPE_VENC,
 	.phy.venc.type          = OMAP_DSS_VENC_TYPE_SVIDEO,
-	.platform_enable        = devkit8000_panel_enable_tv,
-	.platform_disable       = devkit8000_panel_disable_tv,
 };
 
 
-- 
1.7.1



From weber at corscience.de  Wed Jun  2 07:37:50 2010
From: weber at corscience.de (Thomas Weber)
Date: Wed,  2 Jun 2010 13:37:50 +0200
Subject: [PATCHv2 10/11] OMAP2: Devkit8000: Remove unused omap_board_config
In-Reply-To: <1275478671-24563-1-git-send-email-weber@corscience.de>
References: <1275478671-24563-1-git-send-email-weber@corscience.de>
Message-ID: <1275478671-24563-11-git-send-email-weber@corscience.de>

omap_board_config is no longer used and thats why empty.
This patch removes the empty omap_board_config.

Signed-off-by: Thomas Weber <weber at corscience.de>
---
 arch/arm/mach-omap2/board-devkit8000.c |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index dbd16de..a485d39 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -126,8 +126,6 @@ static struct omap2_hsmmc_info mmc[] = {
 	},
 	{}	/* Terminator */
 };
-static struct omap_board_config_kernel devkit8000_config[] __initdata = {
-};
 
 static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev)
 {
@@ -464,8 +462,6 @@ static struct platform_device keys_gpio = {
 
 static void __init devkit8000_init_irq(void)
 {
-	omap_board_config = devkit8000_config;
-	omap_board_config_size = ARRAY_SIZE(devkit8000_config);
 	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
 			     mt46h32m32lf6_sdrc_params);
 	omap_init_irq();
@@ -797,8 +793,6 @@ static void __init devkit8000_init(void)
 	devkit8000_i2c_init();
 	platform_add_devices(devkit8000_devices,
 			ARRAY_SIZE(devkit8000_devices));
-	omap_board_config = devkit8000_config;
-	omap_board_config_size = ARRAY_SIZE(devkit8000_config);
 
 	spi_register_board_info(devkit8000_spi_board_info,
 	ARRAY_SIZE(devkit8000_spi_board_info));
-- 
1.7.1



From weber at corscience.de  Wed Jun  2 07:37:44 2010
From: weber at corscience.de (Thomas Weber)
Date: Wed,  2 Jun 2010 13:37:44 +0200
Subject: [PATCHv2 04/11] OMAP2: Devkit8000: Setup LCD reset
In-Reply-To: <1275478671-24563-1-git-send-email-weber@corscience.de>
References: <1275478671-24563-1-git-send-email-weber@corscience.de>
Message-ID: <1275478671-24563-5-git-send-email-weber@corscience.de>

From: Kan-Ru Chen <kanru at 0xlab.org>

This patch corrects the LCD reset pin configuration.

Original code from early devkit8000 patch sets the TWL4030 GPIO_1
to EHCI_nOC and TWL4030_GPIO_MAX+1 to ledA. Indeed these two pins
are both LCD_PWREN. Setup the lcd reset_gpio properly so it can be
disabled when other display is turned on.

Signed-off-by: Kan-Ru Chen <kanru at 0xlab.org>
---
 arch/arm/mach-omap2/board-devkit8000.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 17a2517..70552d8 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -134,11 +134,15 @@ static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev)
 	twl_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80, REG_GPIODATADIR1);
 	twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0);
 
+	if (dssdev->reset_gpio != -EINVAL)
+		gpio_set_value(dssdev->reset_gpio, 1);
 	return 0;
 }
 
 static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
+	if (dssdev->reset_gpio != -EINVAL)
+		gpio_set_value(dssdev->reset_gpio, 0);
 }
 
 static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
@@ -183,6 +187,7 @@ static struct omap_dss_device devkit8000_lcd_device = {
 	.driver_name            = "generic_panel",
 	.type                   = OMAP_DISPLAY_TYPE_DPI,
 	.phy.dpi.data_lines     = 24,
+	.reset_gpio             = -EINVAL, /* will be replaced */
 	.platform_enable        = devkit8000_panel_enable_lcd,
 	.platform_disable       = devkit8000_panel_disable_lcd,
 };
@@ -281,6 +286,12 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
 	/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
 	gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
 
+        /* gpio + 1 is "LCD_PWREN" (out, active high) */
+	devkit8000_lcd_device.reset_gpio = gpio + 1;
+	gpio_request(devkit8000_lcd_device.reset_gpio, "LCD_PWREN");
+	/* Disable until needed */
+	gpio_direction_output(devkit8000_lcd_device.reset_gpio, 0);
+
 	/* gpio + 7 is "DVI_PD" (out, active low) */
 	devkit8000_dvi_device.reset_gpio = gpio + 7;
 	gpio_request(devkit8000_dvi_device.reset_gpio, "DVI PowerDown");
-- 
1.7.1



From weber at corscience.de  Wed Jun  2 07:37:43 2010
From: weber at corscience.de (Thomas Weber)
Date: Wed,  2 Jun 2010 13:37:43 +0200
Subject: [PATCHv2 03/11] OMAP2: Devkit8000: Enable DVI-D output
In-Reply-To: <1275478671-24563-1-git-send-email-weber@corscience.de>
References: <1275478671-24563-1-git-send-email-weber@corscience.de>
Message-ID: <1275478671-24563-4-git-send-email-weber@corscience.de>

From: Kan-Ru Chen <kanru at 0xlab.org>

This patch corrects the DVI-D output setup of Devkit8000

Devkit8000 has different DVI reset pin with the BeagleBoard.
On Devkit8000 the TWL4030 GPIO_7 is assigned to do the job.

Signed-off-by: Kan-Ru Chen <kanru at 0xlab.org>
---
 arch/arm/mach-omap2/board-devkit8000.c |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 3bde0e6..17a2517 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -140,13 +140,18 @@ static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev)
 static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
 }
+
 static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
 {
+	if (dssdev->reset_gpio != -EINVAL)
+		gpio_set_value(dssdev->reset_gpio, 1);
 	return 0;
 }
 
 static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
 {
+	if (dssdev->reset_gpio != -EINVAL)
+		gpio_set_value(dssdev->reset_gpio, 0);
 }
 
 static int devkit8000_panel_enable_tv(struct omap_dss_device *dssdev)
@@ -186,6 +191,7 @@ static struct omap_dss_device devkit8000_dvi_device = {
 	.driver_name            = "generic_panel",
 	.type                   = OMAP_DISPLAY_TYPE_DPI,
 	.phy.dpi.data_lines     = 24,
+	.reset_gpio             = -EINVAL, /* will be replaced */
 	.platform_enable        = devkit8000_panel_enable_dvi,
 	.platform_disable       = devkit8000_panel_disable_dvi,
 };
@@ -272,6 +278,15 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
 	devkit8000_vmmc1_supply.dev = mmc[0].dev;
 	devkit8000_vsim_supply.dev = mmc[0].dev;
 
+	/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
+	gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
+
+	/* gpio + 7 is "DVI_PD" (out, active low) */
+	devkit8000_dvi_device.reset_gpio = gpio + 7;
+	gpio_request(devkit8000_dvi_device.reset_gpio, "DVI PowerDown");
+	/* Disable until needed */
+	gpio_direction_output(devkit8000_dvi_device.reset_gpio, 0);
+
 	return 0;
 }
 
-- 
1.7.1



From weber at corscience.de  Wed Jun  2 07:37:45 2010
From: weber at corscience.de (Thomas Weber)
Date: Wed,  2 Jun 2010 13:37:45 +0200
Subject: [PATCHv2 05/11] OMAP2: Devkit8000: Remove unneeded VDVI supply
In-Reply-To: <1275478671-24563-1-git-send-email-weber@corscience.de>
References: <1275478671-24563-1-git-send-email-weber@corscience.de>
Message-ID: <1275478671-24563-6-git-send-email-weber@corscience.de>

The VDVI power supply is no longer needed in
board code with the new DSS2 interface.

Signed-off-by: Thomas Weber <weber at corscience.de>
---
 arch/arm/mach-omap2/board-devkit8000.c |    5 -----
 1 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 70552d8..8cc8c3b 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -314,10 +314,6 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
 
 static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = {
 	{
-	.supply		= "vdvi",
-	.dev		= &devkit8000_lcd_device.dev,
-	},
-	{
 	.supply		= "vdds_dsi",
 	.dev		= &devkit8000_dss_device.dev,
 	}
@@ -370,7 +366,6 @@ static struct regulator_init_data devkit8000_vdac = {
 /* VPLL1 for digital video outputs */
 static struct regulator_init_data devkit8000_vpll1 = {
 	.constraints = {
-		.name			= "VDVI",
 		.min_uV			= 1800000,
 		.max_uV			= 1800000,
 		.valid_modes_mask	= REGULATOR_MODE_NORMAL
-- 
1.7.1



From weber at corscience.de  Wed Jun  2 07:37:42 2010
From: weber at corscience.de (Thomas Weber)
Date: Wed,  2 Jun 2010 13:37:42 +0200
Subject: [PATCHv2 02/11] OMAP2: Devkit8000: change panel to generic panel
In-Reply-To: <1275478671-24563-1-git-send-email-weber@corscience.de>
References: <1275478671-24563-1-git-send-email-weber@corscience.de>
Message-ID: <1275478671-24563-3-git-send-email-weber@corscience.de>

Choose the generic panel for lcd code of Devkit8000.

Signed-off-by: Thomas Weber <weber at corscience.de>
---
 arch/arm/mach-omap2/board-devkit8000.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 08a2a01..3bde0e6 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -175,7 +175,7 @@ static struct regulator_consumer_supply devkit8000_vio_supplies[] = {
 
 static struct omap_dss_device devkit8000_lcd_device = {
 	.name                   = "lcd",
-	.driver_name            = "innolux_at_panel",
+	.driver_name            = "generic_panel",
 	.type                   = OMAP_DISPLAY_TYPE_DPI,
 	.phy.dpi.data_lines     = 24,
 	.platform_enable        = devkit8000_panel_enable_lcd,
-- 
1.7.1



From weber at corscience.de  Wed Jun  2 07:37:41 2010
From: weber at corscience.de (Thomas Weber)
Date: Wed,  2 Jun 2010 13:37:41 +0200
Subject: [PATCHv2 01/11] OMAP2: Devkit8000: Cleanup for power supplies
In-Reply-To: <1275478671-24563-1-git-send-email-weber@corscience.de>
References: <1275478671-24563-1-git-send-email-weber@corscience.de>
Message-ID: <1275478671-24563-2-git-send-email-weber@corscience.de>

Corrected the wrong power supplies in devkit8000 code.

Add supply for ads7846 to support the new regulator framework for
touchscreen.

Signed-off-by: Thomas Weber <weber at corscience.de>
---
 arch/arm/mach-omap2/board-devkit8000.c |   32 ++++++++++++++++++++++++++------
 1 files changed, 26 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 922b746..08a2a01 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -168,6 +168,10 @@ static struct regulator_consumer_supply devkit8000_vsim_supply = {
 	.supply			= "vmmc_aux",
 };
 
+/* ads7846 on SPI */
+static struct regulator_consumer_supply devkit8000_vio_supplies[] = {
+	REGULATOR_SUPPLY("vcc", "spi2.0")
+};
 
 static struct omap_dss_device devkit8000_lcd_device = {
 	.name                   = "lcd",
@@ -282,7 +286,7 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
 	.setup		= devkit8000_twl_gpio_setup,
 };
 
-static struct regulator_consumer_supply devkit8000_vpll2_supplies[] = {
+static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = {
 	{
 	.supply		= "vdvi",
 	.dev		= &devkit8000_lcd_device.dev,
@@ -337,8 +341,8 @@ static struct regulator_init_data devkit8000_vdac = {
 	.consumer_supplies	= &devkit8000_vdda_dac_supply,
 };
 
-/* VPLL2 for digital video outputs */
-static struct regulator_init_data devkit8000_vpll2 = {
+/* VPLL1 for digital video outputs */
+static struct regulator_init_data devkit8000_vpll1 = {
 	.constraints = {
 		.name			= "VDVI",
 		.min_uV			= 1800000,
@@ -348,8 +352,23 @@ static struct regulator_init_data devkit8000_vpll2 = {
 		.valid_ops_mask		= REGULATOR_CHANGE_MODE
 					| REGULATOR_CHANGE_STATUS,
 	},
-	.num_consumer_supplies	= ARRAY_SIZE(devkit8000_vpll2_supplies),
-	.consumer_supplies	= devkit8000_vpll2_supplies,
+	.num_consumer_supplies	= ARRAY_SIZE(devkit8000_vpll1_supplies),
+	.consumer_supplies	= devkit8000_vpll1_supplies,
+};
+
+/* VAUX4 for ads7846 and nubs */
+static struct regulator_init_data devkit8000_vio = {
+	.constraints = {
+		.min_uV                 = 1800000,
+		.max_uV                 = 1800000,
+		.apply_uV               = true,
+		.valid_modes_mask       = REGULATOR_MODE_NORMAL
+			| REGULATOR_MODE_STANDBY,
+		.valid_ops_mask         = REGULATOR_CHANGE_MODE
+			| REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies  = ARRAY_SIZE(devkit8000_vio_supplies),
+	.consumer_supplies      = devkit8000_vio_supplies,
 };
 
 static struct twl4030_usb_data devkit8000_usb_data = {
@@ -376,7 +395,8 @@ static struct twl4030_platform_data devkit8000_twldata = {
 	.vmmc1		= &devkit8000_vmmc1,
 	.vsim		= &devkit8000_vsim,
 	.vdac		= &devkit8000_vdac,
-	.vpll2		= &devkit8000_vpll2,
+	.vpll1		= &devkit8000_vpll1,
+	.vio		= &devkit8000_vio,
 	.keypad		= &devkit8000_kp_data,
 };
 
-- 
1.7.1



From weber at corscience.de  Wed Jun  2 07:37:49 2010
From: weber at corscience.de (Thomas Weber)
Date: Wed,  2 Jun 2010 13:37:49 +0200
Subject: [PATCHv2 09/11] OMAP2: Devkit8000: Using gpio_is_valid macro
In-Reply-To: <1275478671-24563-1-git-send-email-weber@corscience.de>
References: <1275478671-24563-1-git-send-email-weber@corscience.de>
Message-ID: <1275478671-24563-10-git-send-email-weber@corscience.de>

Using the macro gpio_is_valid for check of valid gpio pins.

Signed-off-by: Thomas Weber <weber at corscience.de>
---
 arch/arm/mach-omap2/board-devkit8000.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 3da88c8..dbd16de 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -134,27 +134,27 @@ static int devkit8000_panel_enable_lcd(struct omap_dss_device *dssdev)
 	twl_i2c_write_u8(TWL4030_MODULE_GPIO, 0x80, REG_GPIODATADIR1);
 	twl_i2c_write_u8(TWL4030_MODULE_LED, 0x0, 0x0);
 
-	if (dssdev->reset_gpio != -EINVAL)
+	if (gpio_is_valid(dssdev->reset_gpio))
 		gpio_set_value(dssdev->reset_gpio, 1);
 	return 0;
 }
 
 static void devkit8000_panel_disable_lcd(struct omap_dss_device *dssdev)
 {
-	if (dssdev->reset_gpio != -EINVAL)
+	if (gpio_is_valid(dssdev->reset_gpio))
 		gpio_set_value(dssdev->reset_gpio, 0);
 }
 
 static int devkit8000_panel_enable_dvi(struct omap_dss_device *dssdev)
 {
-	if (dssdev->reset_gpio != -EINVAL)
+	if (gpio_is_valid(dssdev->reset_gpio))
 		gpio_set_value(dssdev->reset_gpio, 1);
 	return 0;
 }
 
 static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
 {
-	if (dssdev->reset_gpio != -EINVAL)
+	if (gpio_is_valid(dssdev->reset_gpio))
 		gpio_set_value(dssdev->reset_gpio, 0);
 }
 
-- 
1.7.1



From weber at corscience.de  Wed Jun  2 07:37:51 2010
From: weber at corscience.de (Thomas Weber)
Date: Wed,  2 Jun 2010 13:37:51 +0200
Subject: [PATCHv2 11/11] OMAP2: Devkit8000: Fix regulator for power supply
In-Reply-To: <1275478671-24563-1-git-send-email-weber@corscience.de>
References: <1275478671-24563-1-git-send-email-weber@corscience.de>
Message-ID: <1275478671-24563-12-git-send-email-weber@corscience.de>

Devkit8000 uses the TPS65930 and not the TWL4030.
The TPS65930 uses only a subset of the power supplies
of the TWL4030.

Signed-off-by: Thomas Weber <weber at corscience.de>
---
 arch/arm/mach-omap2/board-devkit8000.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index a485d39..648b565 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -380,7 +380,7 @@ static struct twl4030_platform_data devkit8000_twldata = {
 
 static struct i2c_board_info __initdata devkit8000_i2c_boardinfo[] = {
 	{
-		I2C_BOARD_INFO("twl4030", 0x48),
+		I2C_BOARD_INFO("tps65930", 0x48),
 		.flags = I2C_CLIENT_WAKE,
 		.irq = INT_34XX_SYS_NIRQ,
 		.platform_data = &devkit8000_twldata,
-- 
1.7.1



From weber at corscience.de  Wed Jun  2 07:37:40 2010
From: weber at corscience.de (Thomas Weber)
Date: Wed,  2 Jun 2010 13:37:40 +0200
Subject: [PATCHv2 00/11] Multiple fixes for Devkit8000
Message-ID: <1275478671-24563-1-git-send-email-weber@corscience.de>

These patches correct errors that were done while using the board code
from beagle board for Devkit8000. 

The Devkit8000 uses the TPS65930, an reduced version of the TWL4030. 
So not all power supplies from the TWL4030 are available.
The DSS2 do not need a VDVI any longer so it is removed. 
The definition of the supplies are changed to use the new REGULATOR_SUPPLY macro.
The pins for lcd and dvi powerdown are corrected.

Changes to v1:
 -remove the patches that only fix comments
 -expand the description of the patches

Kan-Ru Chen (2):
  OMAP2: Devkit8000: Enable DVI-D output
  OMAP2: Devkit8000: Setup LCD reset

Thomas Weber (9):
  OMAP2: Devkit8000: Cleanup for power supplies
  OMAP2: Devkit8000: change panel to generic panel
  OMAP2: Devkit8000: Remove unneeded VDVI supply
  OMAP2: Devkit8000: Remove non existing vsim supply
  OMAP2: Devkit8000: Remove en-/disable for tv panel
  OMAP2: Devkit8000: Using the REGULATOR_SUPPLY macro
  OMAP2: Devkit8000: Using gpio_is_valid macro
  OMAP2: Devkit8000: Remove unused omap_board_config
  OMAP2: Devkit8000: Fix regulator for power supply

 arch/arm/mach-omap2/board-devkit8000.c |  122 +++++++++++++++-----------------
 1 files changed, 58 insertions(+), 64 deletions(-)



From weber at corscience.de  Wed Jun  2 07:37:48 2010
From: weber at corscience.de (Thomas Weber)
Date: Wed,  2 Jun 2010 13:37:48 +0200
Subject: [PATCHv2 08/11] OMAP2: Devkit8000: Using the REGULATOR_SUPPLY macro
In-Reply-To: <1275478671-24563-1-git-send-email-weber@corscience.de>
References: <1275478671-24563-1-git-send-email-weber@corscience.de>
Message-ID: <1275478671-24563-9-git-send-email-weber@corscience.de>

Replacing supplies with the REGULATOR_SUPPLY macro.

Signed-off-by: Thomas Weber <weber at corscience.de>
---
 arch/arm/mach-omap2/board-devkit8000.c |   33 ++++++++++++-------------------
 1 files changed, 13 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 095dc7a..3da88c8 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -158,14 +158,13 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
 		gpio_set_value(dssdev->reset_gpio, 0);
 }
 
-static struct regulator_consumer_supply devkit8000_vmmc1_supply = {
-	.supply			= "vmmc",
-};
+static struct regulator_consumer_supply devkit8000_vmmc1_supply =
+	REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
+
 
 /* ads7846 on SPI */
-static struct regulator_consumer_supply devkit8000_vio_supplies[] = {
-	REGULATOR_SUPPLY("vcc", "spi2.0")
-};
+static struct regulator_consumer_supply devkit8000_vio_supply =
+	REGULATOR_SUPPLY("vcc", "spi2.0");
 
 static struct omap_dss_device devkit8000_lcd_device = {
 	.name                   = "lcd",
@@ -214,10 +213,8 @@ static struct platform_device devkit8000_dss_device = {
 	},
 };
 
-static struct regulator_consumer_supply devkit8000_vdda_dac_supply = {
-	.supply = "vdda_dac",
-	.dev	= &devkit8000_dss_device.dev,
-};
+static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
+	REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
 static int board_keymap[] = {
 	KEY(0, 0, KEY_1),
@@ -294,12 +291,8 @@ static struct twl4030_gpio_platform_data devkit8000_gpio_data = {
 	.setup		= devkit8000_twl_gpio_setup,
 };
 
-static struct regulator_consumer_supply devkit8000_vpll1_supplies[] = {
-	{
-	.supply		= "vdds_dsi",
-	.dev		= &devkit8000_dss_device.dev,
-	}
-};
+static struct regulator_consumer_supply devkit8000_vpll1_supply =
+	REGULATOR_SUPPLY("vdds_dsi", "omapdss");
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
 static struct regulator_init_data devkit8000_vmmc1 = {
@@ -340,8 +333,8 @@ static struct regulator_init_data devkit8000_vpll1 = {
 		.valid_ops_mask		= REGULATOR_CHANGE_MODE
 					| REGULATOR_CHANGE_STATUS,
 	},
-	.num_consumer_supplies	= ARRAY_SIZE(devkit8000_vpll1_supplies),
-	.consumer_supplies	= devkit8000_vpll1_supplies,
+	.num_consumer_supplies	= 1,
+	.consumer_supplies	= &devkit8000_vpll1_supply,
 };
 
 /* VAUX4 for ads7846 and nubs */
@@ -355,8 +348,8 @@ static struct regulator_init_data devkit8000_vio = {
 		.valid_ops_mask         = REGULATOR_CHANGE_MODE
 			| REGULATOR_CHANGE_STATUS,
 	},
-	.num_consumer_supplies  = ARRAY_SIZE(devkit8000_vio_supplies),
-	.consumer_supplies      = devkit8000_vio_supplies,
+	.num_consumer_supplies  = 1,
+	.consumer_supplies      = &devkit8000_vio_supply,
 };
 
 static struct twl4030_usb_data devkit8000_usb_data = {
-- 
1.7.1



From weber at corscience.de  Wed Jun  2 07:37:46 2010
From: weber at corscience.de (Thomas Weber)
Date: Wed,  2 Jun 2010 13:37:46 +0200
Subject: [PATCHv2 06/11] OMAP2: Devkit8000: Remove non existing vsim supply
In-Reply-To: <1275478671-24563-1-git-send-email-weber@corscience.de>
References: <1275478671-24563-1-git-send-email-weber@corscience.de>
Message-ID: <1275478671-24563-7-git-send-email-weber@corscience.de>

The Devkit8000 uses the cost reduced variant tps65930 of the twl4030.
The TPS65930 only has vdd1, vdd2, vpll1, vio, vmmc1, vdac and vaux2.

vaux2 is not used on Devkit8000.

Signed-off-by: Thomas Weber <weber at corscience.de>
---
 arch/arm/mach-omap2/board-devkit8000.c |   22 ----------------------
 1 files changed, 0 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 8cc8c3b..59877b1 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -168,15 +168,10 @@ static void devkit8000_panel_disable_tv(struct omap_dss_device *dssdev)
 {
 }
 
-
 static struct regulator_consumer_supply devkit8000_vmmc1_supply = {
 	.supply			= "vmmc",
 };
 
-static struct regulator_consumer_supply devkit8000_vsim_supply = {
-	.supply			= "vmmc_aux",
-};
-
 /* ads7846 on SPI */
 static struct regulator_consumer_supply devkit8000_vio_supplies[] = {
 	REGULATOR_SUPPLY("vcc", "spi2.0")
@@ -281,7 +276,6 @@ static int devkit8000_twl_gpio_setup(struct device *dev,
 
 	/* link regulators to MMC adapters */
 	devkit8000_vmmc1_supply.dev = mmc[0].dev;
-	devkit8000_vsim_supply.dev = mmc[0].dev;
 
 	/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
 	gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -334,21 +328,6 @@ static struct regulator_init_data devkit8000_vmmc1 = {
 	.consumer_supplies	= &devkit8000_vmmc1_supply,
 };
 
-/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
-static struct regulator_init_data devkit8000_vsim = {
-	.constraints = {
-		.min_uV			= 1800000,
-		.max_uV			= 3000000,
-		.valid_modes_mask	= REGULATOR_MODE_NORMAL
-					| REGULATOR_MODE_STANDBY,
-		.valid_ops_mask		= REGULATOR_CHANGE_VOLTAGE
-					| REGULATOR_CHANGE_MODE
-					| REGULATOR_CHANGE_STATUS,
-	},
-	.num_consumer_supplies	= 1,
-	.consumer_supplies	= &devkit8000_vsim_supply,
-};
-
 /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
 static struct regulator_init_data devkit8000_vdac = {
 	.constraints = {
@@ -414,7 +393,6 @@ static struct twl4030_platform_data devkit8000_twldata = {
 	.gpio		= &devkit8000_gpio_data,
 	.codec		= &devkit8000_codec_data,
 	.vmmc1		= &devkit8000_vmmc1,
-	.vsim		= &devkit8000_vsim,
 	.vdac		= &devkit8000_vdac,
 	.vpll1		= &devkit8000_vpll1,
 	.vio		= &devkit8000_vio,
-- 
1.7.1



From jeremy.kerr at canonical.com  Wed Jun  2 07:56:44 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Wed, 02 Jun 2010 19:56:44 +0800
Subject: [RFC,PATCH 0/2] Common struct clk implementation, v3
Message-ID: <1275479804.137633.565764505843.0.gpush@pororo>

Hi all,

These patches are an attempt to allow platforms to share clock code. At
present, the definitions of 'struct clk' are local to platform code,
which makes allocating and initialising cross-platform clock sources
difficult, and makes it impossible to compile a single image containing
support for two ARM platforms with different struct clks.

The two patches are for the architecture-independent kernel code,
introducing the common clk infrastructure. The changelog for the first
patch includes details about the new clock definitions.

As requested by rmk, I've put together a small series of patches
illustrating the usage of the common struct clock on the ARM imx51
platform. These are available in my git tree:

 git://kernel.ubuntu.com/jk/dt/linux-2.6

in the clk-common-mx51 branch (clk-common..clk-common-mx51).

The approach I've taken with the imx51 port is to temporarly duplicate
the platform-common clock code (ie, for all mxc-based boards) to enable
usage of the common struct clk on one machine (imx51), while leaving the
others as-is. For a proper platform-wide usage of the common struct clk,
we'd be better off doing the whole platform at once. However, mx51 is
the only mxc-based HW I have, hence the duplicated example port.

In the example port, the first change simply converts the mxc's struct
clk to a struct clk_mxc, using the new API.  The subsequent patches move
certain clocks to more specific data structures (eg clk_fixed and
clk_pll) where possible.

Ben Herrenschmidt is looking at using common struct clk code for powerpc
too, hence the kernel-wide approach.

Comments most welcome.

Cheers,


Jeremy

--
v3:
 * do clock usage refcounting in common code
 * provide sample port

v2:
 * no longer ARM-specific
 * use clk_operations

---
Jeremy Kerr (2):
      Add a common struct clk
      clk: Generic support for fixed-rate clocks



From jeremy.kerr at canonical.com  Wed Jun  2 07:56:44 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Wed, 02 Jun 2010 19:56:44 +0800
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <1275479804.137633.565764505843.0.gpush@pororo>
Message-ID: <1275479804.138101.137592675542.1.gpush@pororo>

We currently have 21 definitions of struct clk in the ARM architecture,
each defined on a per-platform basis. This makes it difficult to define
platform- (or architecture-) independent clock sources without making
assumptions about struct clk, and impossible to compile two
platforms with different struct clks into a single image.

This change is an effort to unify struct clk where possible, by defining
a common struct clk, containing a set of clock operations. Different
clock implementations can set their own operations, and have a standard
interface for generic code. The callback interface is exposed to the
kernel proper, while the clock implementations only need to be seen by
the platform internals.

This allows us to share clock code among platforms, and makes it
possible to dynamically create clock devices in platform-independent
code.

Platforms can enable the generic struct clock through
CONFIG_USE_COMMON_STRUCT_CLK. In this case, the clock infrastructure
consists of a common struct clk:

struct clk {
	struct clk_operations *ops;
	atomic_t enable_count;
};

And a set of clock operations (defined per type of clock):

struct clk_operations {
       int             (*enable)(struct clk *);
       void            (*disable)(struct clk *);
       unsigned long   (*get_rate)(struct clk *);
       [...]
};

To define a hardware-specific clock, machine code can "subclass" the
struct clock into a new struct (adding any device-specific data), and
provide a set of operations:

struct clk_foo {
	struct clk	clk;
	void __iomem	*some_register;
};

struct clk_operations clk_foo_ops = {
	.get_rate = clk_foo_get_rate,
};

The common clock definitions are based on a development patch from Ben
Herrenschmidt <benh at kernel.crashing.org>.

Signed-off-by: Jeremy Kerr <jeremy.kerr at canonical.com>

---
 arch/Kconfig        |    3 
 include/linux/clk.h |  148 +++++++++++++++++++++++++++++++++++---------
 2 files changed, 124 insertions(+), 27 deletions(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index acda512..2458b5e 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -151,4 +151,7 @@ config HAVE_MIXED_BREAKPOINTS_REGS
 config HAVE_USER_RETURN_NOTIFIER
 	bool
 
+config USE_COMMON_STRUCT_CLK
+	bool
+
 source "kernel/gcov/Kconfig"
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 1d37f42..f70137a 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -3,6 +3,7 @@
  *
  *  Copyright (C) 2004 ARM Limited.
  *  Written by Deep Blue Solutions Limited.
+ *  Copyright (c) 2010 Jeremy Kerr <jeremy.kerr at canonical.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -11,36 +12,114 @@
 #ifndef __LINUX_CLK_H
 #define __LINUX_CLK_H
 
-struct device;
+#include <linux/err.h>
+#include <asm/atomic.h>
 
-/*
- * The base API.
+#ifdef CONFIG_USE_COMMON_STRUCT_CLK
+
+/* If we're using the common struct clk, we define the base clk object here,
+ * which will be 'subclassed' by device-specific implementations. For example:
+ *
+ *  struct clk_foo {
+ *      struct clk;
+ *      [device specific fields]
+ *  };
+ *
+ * We define the common clock API through a set of static inlines that call the
+ * corresponding clk_operations. The API is exactly the same as that documented
+ * in the !CONFIG_USE_COMMON_STRUCT_CLK case.
  */
 
+struct clk {
+	const struct clk_operations *ops;
+	atomic_t enable_count;
+};
+
+#define DEFINE_CLK(o) \
+	{ .ops = &o, .enable_count = ATOMIC_INIT(0) }
+
+struct clk_operations {
+       int             (*enable)(struct clk *);
+       void            (*disable)(struct clk *);
+       unsigned long   (*get_rate)(struct clk *);
+       void            (*put)(struct clk *);
+       long            (*round_rate)(struct clk *, unsigned long);
+       int             (*set_rate)(struct clk *, unsigned long);
+       int             (*set_parent)(struct clk *, struct clk *);
+       struct clk*     (*get_parent)(struct clk *);
+};
+
+static inline int clk_enable(struct clk *clk)
+{
+	if (!clk->ops->enable)
+		return 0;
+
+	if (atomic_inc_return(&clk->enable_count) != 1)
+		return 0;
+
+	return clk->ops->enable(clk);
+}
+
+static inline void clk_disable(struct clk *clk)
+{
+	if (!clk->ops->disable)
+		return;
+
+	if (atomic_dec_return(&clk->enable_count) != 0)
+		return;
+
+	clk->ops->disable(clk);
+}
+
+static inline unsigned long clk_get_rate(struct clk *clk)
+{
+	if (clk->ops->get_rate)
+		return clk->ops->get_rate(clk);
+	return 0;
+}
+
+static inline void clk_put(struct clk *clk)
+{
+	if (clk->ops->put)
+		clk->ops->put(clk);
+}
+
+static inline long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	if (clk->ops->round_rate)
+		return clk->ops->round_rate(clk, rate);
+	return -ENOSYS;
+}
+
+static inline int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	if (clk->ops->set_rate)
+		return clk->ops->set_rate(clk, rate);
+	return -ENOSYS;
+}
+
+static inline int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	if (clk->ops->set_parent)
+		return clk->ops->set_parent(clk, parent);
+	return -ENOSYS;
+}
+
+static inline struct clk *clk_get_parent(struct clk *clk)
+{
+	if (clk->ops->get_parent)
+		return clk->ops->get_parent(clk);
+	return ERR_PTR(-ENOSYS);
+}
+
+#else /* !CONFIG_USE_COMMON_STRUCT_CLK */
 
 /*
- * struct clk - an machine class defined object / cookie.
+ * Global clock object, actual structure is declared per-machine
  */
 struct clk;
 
 /**
- * clk_get - lookup and obtain a reference to a clock producer.
- * @dev: device for clock "consumer"
- * @id: clock comsumer ID
- *
- * Returns a struct clk corresponding to the clock producer, or
- * valid IS_ERR() condition containing errno.  The implementation
- * uses @dev and @id to determine the clock consumer, and thereby
- * the clock producer.  (IOW, @id may be identical strings, but
- * clk_get may return different clock producers depending on @dev.)
- *
- * Drivers must assume that the clock source is not enabled.
- *
- * clk_get should not be called from within interrupt context.
- */
-struct clk *clk_get(struct device *dev, const char *id);
-
-/**
  * clk_enable - inform the system when the clock source should be running.
  * @clk: clock source
  *
@@ -83,12 +162,6 @@ unsigned long clk_get_rate(struct clk *clk);
  */
 void clk_put(struct clk *clk);
 
-
-/*
- * The remaining APIs are optional for machine class support.
- */
-
-
 /**
  * clk_round_rate - adjust a rate to the exact rate a clock can provide
  * @clk: clock source
@@ -125,6 +198,27 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
  */
 struct clk *clk_get_parent(struct clk *clk);
 
+#endif /* !CONFIG_USE_COMMON_STRUCT_CLK */
+
+struct device;
+
+/**
+ * clk_get - lookup and obtain a reference to a clock producer.
+ * @dev: device for clock "consumer"
+ * @id: clock comsumer ID
+ *
+ * Returns a struct clk corresponding to the clock producer, or
+ * valid IS_ERR() condition containing errno.  The implementation
+ * uses @dev and @id to determine the clock consumer, and thereby
+ * the clock producer.  (IOW, @id may be identical strings, but
+ * clk_get may return different clock producers depending on @dev.)
+ *
+ * Drivers must assume that the clock source is not enabled.
+ *
+ * clk_get should not be called from within interrupt context.
+ */
+struct clk *clk_get(struct device *dev, const char *id);
+
 /**
  * clk_get_sys - get a clock based upon the device name
  * @dev_id: device name


From jeremy.kerr at canonical.com  Wed Jun  2 07:56:44 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Wed, 02 Jun 2010 19:56:44 +0800
Subject: [RFC,PATCH 2/2] clk: Generic support for fixed-rate clocks
In-Reply-To: <1275479804.137633.565764505843.0.gpush@pororo>
Message-ID: <1275479804.138392.188759209099.2.gpush@pororo>

Since most platforms will need a fixed-rate clock, add one. This will
also serve as a basic example of an implementation of struct clk.

Signed-off-by: Jeremy Kerr <jeremy.kerr at canonical.com>

---
 include/linux/clk.h |   13 +++++++++++++
 kernel/Makefile     |    1 +
 kernel/clk.c        |   25 +++++++++++++++++++++++++
 3 files changed, 39 insertions(+)

diff --git a/include/linux/clk.h b/include/linux/clk.h
index f70137a..009ca73 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -112,6 +112,19 @@ static inline struct clk *clk_get_parent(struct clk *clk)
 	return ERR_PTR(-ENOSYS);
 }
 
+/* Simple fixed-rate clock */
+struct clk_fixed {
+	struct clk	clk;
+	unsigned long	rate;
+};
+
+extern struct clk_operations clk_fixed_operations;
+
+#define DEFINE_CLK_FIXED(r) { \
+	.clk = DEFINE_CLK(clk_fixed_operations), \
+	.rate = (r) \
+}
+
 #else /* !CONFIG_USE_COMMON_STRUCT_CLK */
 
 /*
diff --git a/kernel/Makefile b/kernel/Makefile
index 057472f..1ae15aa 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -105,6 +105,7 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o
 obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
 obj-$(CONFIG_USER_RETURN_NOTIFIER) += user-return-notifier.o
 obj-$(CONFIG_PADATA) += padata.o
+obj-$(CONFIG_USE_COMMON_STRUCT_CLK) += clk.o
 
 ifneq ($(CONFIG_SCHED_OMIT_FRAME_POINTER),y)
 # According to Alan Modra <alan at linuxcare.com.au>, the -fno-omit-frame-pointer is
diff --git a/kernel/clk.c b/kernel/clk.c
new file mode 100644
index 0000000..353736c
--- /dev/null
+++ b/kernel/clk.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2010 Canonical Ltd <jeremy.kerr at canonical.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Standard functionality for the common clock API.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+
+#define to_clk_fixed(clk) (container_of(clk, struct clk_fixed, clk))
+
+static unsigned long clk_fixed_get_rate(struct clk *clk)
+{
+	return to_clk_fixed(clk)->rate;
+}
+
+struct clk_operations clk_fixed_operations = {
+	.get_rate = clk_fixed_get_rate,
+};
+
+EXPORT_SYMBOL_GPL(clk_fixed_operations);


From ben-linux at fluff.org  Wed Jun  2 08:03:56 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Wed, 2 Jun 2010 13:03:56 +0100
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <1275479804.138101.137592675542.1.gpush@pororo>
References: <1275479804.137633.565764505843.0.gpush@pororo>
	<1275479804.138101.137592675542.1.gpush@pororo>
Message-ID: <20100602120356.GQ7248@trinity.fluff.org>

On Wed, Jun 02, 2010 at 07:56:44PM +0800, Jeremy Kerr wrote:
> We currently have 21 definitions of struct clk in the ARM architecture,
> each defined on a per-platform basis. This makes it difficult to define
> platform- (or architecture-) independent clock sources without making
> assumptions about struct clk, and impossible to compile two
> platforms with different struct clks into a single image.
> 
> This change is an effort to unify struct clk where possible, by defining
> a common struct clk, containing a set of clock operations. Different
> clock implementations can set their own operations, and have a standard
> interface for generic code. The callback interface is exposed to the
> kernel proper, while the clock implementations only need to be seen by
> the platform internals.
> 
> This allows us to share clock code among platforms, and makes it
> possible to dynamically create clock devices in platform-independent
> code.
> 
> Platforms can enable the generic struct clock through
> CONFIG_USE_COMMON_STRUCT_CLK. In this case, the clock infrastructure
> consists of a common struct clk:
> 
> struct clk {
> 	struct clk_operations *ops;
> 	atomic_t enable_count;
> };
> 
> And a set of clock operations (defined per type of clock):
> 
> struct clk_operations {
>        int             (*enable)(struct clk *);

I'd rather the enable/disable calls where simply a set
and a bool on/off, very rarelyt is the enable and disable
operartions different.

an aside, you might want to just clal these clk_ops to get into the
spirit of the original naming.

>        void            (*disable)(struct clk *);
>        unsigned long   (*get_rate)(struct clk *);
>        [...]
> };
> 
> To define a hardware-specific clock, machine code can "subclass" the
> struct clock into a new struct (adding any device-specific data), and
> provide a set of operations:
> 
> struct clk_foo {
> 	struct clk	clk;
> 	void __iomem	*some_register;
> };
> 
> struct clk_operations clk_foo_ops = {
> 	.get_rate = clk_foo_get_rate,
> };
> 
> The common clock definitions are based on a development patch from Ben
> Herrenschmidt <benh at kernel.crashing.org>.
> 
> Signed-off-by: Jeremy Kerr <jeremy.kerr at canonical.com>
> 
> ---
>  arch/Kconfig        |    3 
>  include/linux/clk.h |  148 +++++++++++++++++++++++++++++++++++---------
>  2 files changed, 124 insertions(+), 27 deletions(-)
> 
> diff --git a/arch/Kconfig b/arch/Kconfig
> index acda512..2458b5e 100644
> --- a/arch/Kconfig
> +++ b/arch/Kconfig
> @@ -151,4 +151,7 @@ config HAVE_MIXED_BREAKPOINTS_REGS
>  config HAVE_USER_RETURN_NOTIFIER
>  	bool
>  
> +config USE_COMMON_STRUCT_CLK
> +	bool
> +
>  source "kernel/gcov/Kconfig"
> diff --git a/include/linux/clk.h b/include/linux/clk.h
> index 1d37f42..f70137a 100644
> --- a/include/linux/clk.h
> +++ b/include/linux/clk.h
> @@ -3,6 +3,7 @@
>   *
>   *  Copyright (C) 2004 ARM Limited.
>   *  Written by Deep Blue Solutions Limited.
> + *  Copyright (c) 2010 Jeremy Kerr <jeremy.kerr at canonical.com>
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
> @@ -11,36 +12,114 @@
>  #ifndef __LINUX_CLK_H
>  #define __LINUX_CLK_H
>  
> -struct device;
> +#include <linux/err.h>
> +#include <asm/atomic.h>
>  
> -/*
> - * The base API.
> +#ifdef CONFIG_USE_COMMON_STRUCT_CLK
> +
> +/* If we're using the common struct clk, we define the base clk object here,
> + * which will be 'subclassed' by device-specific implementations. For example:
> + *
> + *  struct clk_foo {
> + *      struct clk;
> + *      [device specific fields]
> + *  };
> + *
> + * We define the common clock API through a set of static inlines that call the
> + * corresponding clk_operations. The API is exactly the same as that documented
> + * in the !CONFIG_USE_COMMON_STRUCT_CLK case.
>   */
>  
> +struct clk {
> +	const struct clk_operations *ops;
> +	atomic_t enable_count;
> +};
> +
> +#define DEFINE_CLK(o) \
> +	{ .ops = &o, .enable_count = ATOMIC_INIT(0) }
> +
> +struct clk_operations {
> +       int             (*enable)(struct clk *);
> +       void            (*disable)(struct clk *);
> +       unsigned long   (*get_rate)(struct clk *);
> +       void            (*put)(struct clk *);
> +       long            (*round_rate)(struct clk *, unsigned long);
> +       int             (*set_rate)(struct clk *, unsigned long);
> +       int             (*set_parent)(struct clk *, struct clk *);
> +       struct clk*     (*get_parent)(struct clk *);
> +};
> +
> +static inline int clk_enable(struct clk *clk)
> +{
> +	if (!clk->ops->enable)
> +		return 0;
> +
> +	if (atomic_inc_return(&clk->enable_count) != 1)
> +		return 0;
> +
> +	return clk->ops->enable(clk);
> +}
> +
> +static inline void clk_disable(struct clk *clk)
> +{
> +	if (!clk->ops->disable)
> +		return;
> +
> +	if (atomic_dec_return(&clk->enable_count) != 0)
> +		return;
> +
> +	clk->ops->disable(clk);
> +}
> +
> +static inline unsigned long clk_get_rate(struct clk *clk)
> +{
> +	if (clk->ops->get_rate)
> +		return clk->ops->get_rate(clk);
> +	return 0;
> +}
> +
> +static inline void clk_put(struct clk *clk)
> +{
> +	if (clk->ops->put)
> +		clk->ops->put(clk);
> +}
> +
> +static inline long clk_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	if (clk->ops->round_rate)
> +		return clk->ops->round_rate(clk, rate);
> +	return -ENOSYS;
> +}
> +
> +static inline int clk_set_rate(struct clk *clk, unsigned long rate)
> +{
> +	if (clk->ops->set_rate)
> +		return clk->ops->set_rate(clk, rate);
> +	return -ENOSYS;
> +}
> +
> +static inline int clk_set_parent(struct clk *clk, struct clk *parent)
> +{
> +	if (clk->ops->set_parent)
> +		return clk->ops->set_parent(clk, parent);
> +	return -ENOSYS;
> +}
> +
> +static inline struct clk *clk_get_parent(struct clk *clk)
> +{
> +	if (clk->ops->get_parent)
> +		return clk->ops->get_parent(clk);
> +	return ERR_PTR(-ENOSYS);
> +}
> +
> +#else /* !CONFIG_USE_COMMON_STRUCT_CLK */
>  
>  /*
> - * struct clk - an machine class defined object / cookie.
> + * Global clock object, actual structure is declared per-machine
>   */
>  struct clk;
>  
>  /**
> - * clk_get - lookup and obtain a reference to a clock producer.
> - * @dev: device for clock "consumer"
> - * @id: clock comsumer ID
> - *
> - * Returns a struct clk corresponding to the clock producer, or
> - * valid IS_ERR() condition containing errno.  The implementation
> - * uses @dev and @id to determine the clock consumer, and thereby
> - * the clock producer.  (IOW, @id may be identical strings, but
> - * clk_get may return different clock producers depending on @dev.)
> - *
> - * Drivers must assume that the clock source is not enabled.
> - *
> - * clk_get should not be called from within interrupt context.
> - */
> -struct clk *clk_get(struct device *dev, const char *id);
> -
> -/**
>   * clk_enable - inform the system when the clock source should be running.
>   * @clk: clock source
>   *
> @@ -83,12 +162,6 @@ unsigned long clk_get_rate(struct clk *clk);
>   */
>  void clk_put(struct clk *clk);
>  
> -
> -/*
> - * The remaining APIs are optional for machine class support.
> - */
> -
> -
>  /**
>   * clk_round_rate - adjust a rate to the exact rate a clock can provide
>   * @clk: clock source
> @@ -125,6 +198,27 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
>   */
>  struct clk *clk_get_parent(struct clk *clk);
>  
> +#endif /* !CONFIG_USE_COMMON_STRUCT_CLK */
> +
> +struct device;
> +
> +/**
> + * clk_get - lookup and obtain a reference to a clock producer.
> + * @dev: device for clock "consumer"
> + * @id: clock comsumer ID
> + *
> + * Returns a struct clk corresponding to the clock producer, or
> + * valid IS_ERR() condition containing errno.  The implementation
> + * uses @dev and @id to determine the clock consumer, and thereby
> + * the clock producer.  (IOW, @id may be identical strings, but
> + * clk_get may return different clock producers depending on @dev.)
> + *
> + * Drivers must assume that the clock source is not enabled.
> + *
> + * clk_get should not be called from within interrupt context.
> + */
> +struct clk *clk_get(struct device *dev, const char *id);
> +
>  /**
>   * clk_get_sys - get a clock based upon the device name
>   * @dev_id: device name
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From mikpe at it.uu.se  Wed Jun  2 08:08:44 2010
From: mikpe at it.uu.se (Mikael Pettersson)
Date: Wed, 2 Jun 2010 14:08:44 +0200
Subject: [PATCH] Add kto and kfrom to input operands list.
In-Reply-To: <1275379600-23498-1-git-send-email-raj.khem@gmail.com>
References: <1275379600-23498-1-git-send-email-raj.khem@gmail.com>
Message-ID: <19462.18892.533099.360440@pilspetsen.it.uu.se>

Khem Raj writes:
 > When functions incoming parameters are not in input operands list gcc 4.5 does not
 > load the parameters into registers before calling this function but the
 > inline assembly assumes valid addresses inside this function. This
 > breaks the code because r0 and r1 are invalid when execution enters
 > v4wb_copy_user_page ()
 > 
 > Also the constant needs to be used as third input operand so account for that
 > as well.
 > 
 > Tested on qemu arm.
 > 
 > Signed-off-by: Khem Raj <raj.khem at gmail.com>
 > ---
 >  arch/arm/mm/copypage-feroceon.c |    4 ++--

I've tested and verified that this bit enables a gcc-4.5 compiled kernel
to boot on TS-119 (Kirkwood) when combined with my fix for __naked.
With neither or only one of the patches applied, the kernel oopses hard
in copy_user_page() as it tries to start /sbin/init.

So for the copypage-feroceon.c change:
Tested-by: Mikael Pettersson <mikpe at it.uu.se>

To elaborate, the copy_user_page() functions in these copypage-*.c files
break in two ways with gcc-4.5:
- they are static __naked functions, and gcc-4.5 erroneously clones
  them and changes their calling conventions in ways that don't match
  the expectations of their asm() bodies, causing runtime crashes;
  my patch to make __naked imply noinline and noclone fixes that
- the asm() bodies of these __naked functions have inadequate input
  parameter constraints, in particular they fail to declare any
  dependencies on the functions' formal parameters; gcc-4.5 sees this
  and skips the parameter setup before calling these functions, causing
  runtime crashes; Khem's patch (this one) fixes that
  (copypage-xscale.c already had correct asm() constraints so it works
  with only the __naked fix, these other copypage-*.c files need both
  patches to work)

These patches are no-ops for earlier compilers since they merely
formalise the parameter passing behaviour that the kernel has been
expecting all along.

/Mikael


From mikpe at it.uu.se  Wed Jun  2 08:10:56 2010
From: mikpe at it.uu.se (Mikael Pettersson)
Date: Wed, 2 Jun 2010 14:10:56 +0200
Subject: [PATCH] Augment __naked__ function attribute with __noinline__
	and __noclone__
In-Reply-To: <1275379552-23449-1-git-send-email-mikpe@it.uu.se>
References: <1275379552-23449-1-git-send-email-mikpe@it.uu.se>
Message-ID: <19462.19024.560502.149871@pilspetsen.it.uu.se>

Mikael Pettersson writes:
 > The asm() bodies of naked functions often depend on standard calling
 > conventions, therefore they must be noinline and noclone.  GCC 4.[56]
 > currently fail to enforce this, see GCC PR44290.  The effect is that
 > most arch/arm/mm/copypage-*.c modules get miscompiled, resulting in
 > kernel crashes during bootup.
 > 
 > Part of the fix is to augment the __naked attribute to imply noinline
 > and noclone.  This patch implements that, and has been verified to fix
 > the failure to boot a gcc-4.5 compiled 2.6.34 kernel on a Thecus n2100
 > (XScale-based mach-iop32x).

Now also tested with a gcc-4.5 compiled 2.6.35-rc1 kernel on a ds101
(XScale-based mach-ixp4xx).

 >
 > Signed-off-by: Mikael Pettersson <mikpe at it.uu.se>
 > Signed-off-by: Khem Raj <raj.khem at gmail.com>
 > ---
 >  include/linux/compiler-gcc.h  |   11 ++++++++++-
 >  include/linux/compiler-gcc4.h |    4 ++++
 >  2 files changed, 14 insertions(+), 1 deletions(-)
 > 
 > diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
 > index 73dcf80..83bd87c 100644
 > --- a/include/linux/compiler-gcc.h
 > +++ b/include/linux/compiler-gcc.h
 > @@ -58,8 +58,12 @@
 >   * naked functions because then mcount is called without stack and frame pointer
 >   * being set up and there is no chance to restore the lr register to the value
 >   * before mcount was called.
 > + *
 > + * The asm() bodies of naked functions often depend on standard calling conventions,
 > + * therefore they must be noinline and noclone.  GCC 4.[56] currently fail to enforce
 > + * this, so we must do so ourselves.  See GCC PR44290.
 >   */
 > -#define __naked				__attribute__((naked)) notrace
 > +#define __naked				__attribute__((naked)) noinline __noclone notrace
 >  
 >  #define __noreturn			__attribute__((noreturn))
 >  
 > @@ -85,3 +89,8 @@
 >  #define _gcc_header(x) __gcc_header(linux/compiler-gcc##x.h)
 >  #define gcc_header(x) _gcc_header(x)
 >  #include gcc_header(__GNUC__)
 > +
 > +#if !defined(__noclone)
 > +#define __noclone	/* not needed */
 > +#endif
 > +
 > diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h
 > index 94dea3f..fcfa5b9 100644
 > --- a/include/linux/compiler-gcc4.h
 > +++ b/include/linux/compiler-gcc4.h
 > @@ -48,6 +48,10 @@
 >   * unreleased.  Really, we need to have autoconf for the kernel.
 >   */
 >  #define unreachable() __builtin_unreachable()
 > +
 > +/* Mark a function definition as prohibited from being cloned. */
 > +#define __noclone	__attribute__((__noclone__))
 > +
 >  #endif
 >  
 >  #endif
 > -- 
 > 1.7.0.4
 > 


From avorontsov at mvista.com  Wed Jun  2 08:29:44 2010
From: avorontsov at mvista.com (Anton Vorontsov)
Date: Wed, 2 Jun 2010 16:29:44 +0400
Subject: [PATCH 3/4] ARM: cns3xxx: Add support for AHCI controllers
In-Reply-To: <4C0623D8.6030701@ru.mvista.com>
References: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
	<20100601165540.GC7123@oksana.dev.rtsoft.ru>
	<4C0623D8.6030701@ru.mvista.com>
Message-ID: <20100602122944.GA11087@oksana.dev.rtsoft.ru>

On Wed, Jun 02, 2010 at 01:26:48PM +0400, Sergei Shtylyov wrote:
[...]
> >+	tmp = MISC_SATA_POWER_MODE;
> >+	tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
> >+	tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
> >+	MISC_SATA_POWER_MODE = tmp;
> 
>    Why aren't you using I/O accessors?

For CNS3xxx __raw_{read,write} are equivalent to direct accesses,
and originally Cavium used registers directly just because it was
easier (less keystrokes, quite understandable).

Ben Dooks also pointed out this concern, and I agree that using
IO accessors would be a good cleanup.

As I'm going to send other improvements, I think I'll fix this for
all CNS3xxx code base on top of this pull request, if nobody minds.

Thanks!

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2


From sshtylyov at mvista.com  Wed Jun  2 08:49:13 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Wed, 02 Jun 2010 16:49:13 +0400
Subject: [PATCH 3/4] ARM: cns3xxx: Add support for AHCI controllers
In-Reply-To: <20100601165540.GC7123@oksana.dev.rtsoft.ru>
References: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
	<20100601165540.GC7123@oksana.dev.rtsoft.ru>
Message-ID: <4C065349.80005@ru.mvista.com>

Hello.

Anton Vorontsov wrote:

> CNS3xxx chips have AHCI-compatible SATA controller. This patch adds
> the support using generic ahci_platform driver.

> Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>

[...]

> diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
> index 549ad0c..bf6044b 100644
> --- a/arch/arm/mach-cns3xxx/devices.c
> +++ b/arch/arm/mach-cns3xxx/devices.c
> @@ -14,14 +14,75 @@
>  #include <linux/init.h>
>  #include <linux/compiler.h>
>  #include <linux/delay.h>
> +#include <linux/dma-mapping.h>
>  #include <linux/device.h>
>  #include <linux/platform_device.h>
> +#include <linux/ahci_platform.h>
>  #include <linux/mmc/host.h>
>  #include <linux/sdhci-pltfm.h>
>  #include "../../../drivers/mmc/host/sdhci.h"
> +#include "core.h"
>  #include "devices.h"
>  
>  /*
> + * AHCI
> + */
> +static int cns3xxx_ahci_init(struct device *dev)
> +{
> +	u32 tmp;
> +
> +	tmp = MISC_SATA_POWER_MODE;
> +	tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
> +	tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
> +	MISC_SATA_POWER_MODE = tmp;
> +
> +	/* Enable SATA PHY */
> +	cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
> +	cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
> +
> +	/* Enable SATA Clock */
> +	cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
> +
> +	/* De-Asscer SATA Reset */
> +	tmp = PM_SOFT_RST_REG;
> +	tmp |= 0x1 << PM_SOFT_RST_REG_OFFST_SATA;

    You have *REG_OFFSET* everywhere, and *REG_OFFST* here -- a typo?

WBR, Sergei



From cbouatmailru at gmail.com  Wed Jun  2 08:50:27 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Wed, 2 Jun 2010 16:50:27 +0400
Subject: [PATCH] ARM: Small cleanup for 'config PCI'
Message-ID: <20100602125027.GA28977@oksana.dev.rtsoft.ru>

Simply introduce ARCH_HAS_PCI to avoid the very long 'if' condition
for PCI Kconfig symbol.

Suggested-by: Ben Dooks <ben at simtec.co.uk>
Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---

Note that this is on top of the cns3xxx pull request.

 arch/arm/Kconfig                 |   11 ++++++++++-
 arch/arm/mach-integrator/Kconfig |    1 +
 arch/arm/mach-pxa/Kconfig        |    1 +
 arch/arm/mach-versatile/Kconfig  |    1 +
 4 files changed, 13 insertions(+), 1 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fab2ddd..63cb0a2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -301,6 +301,7 @@ config ARCH_CNS3XXX
 	select CPU_V6
 	select GENERIC_CLOCKEVENTS
 	select ARM_GIC
+	select ARCH_HAS_PCI
 	select PCI_DOMAINS if PCI
 	help
 	  Support for Cavium Networks CNS3XXX platform.
@@ -436,6 +437,7 @@ config ARCH_IXP4XX
 	select CPU_XSCALE
 	select GENERIC_GPIO
 	select GENERIC_CLOCKEVENTS
+	select ARCH_HAS_PCI
 	select DMABOUNCE if PCI
 	help
 	  Support for Intel's IXP4XX (XScale) family of processors.
@@ -523,6 +525,7 @@ config ARCH_KS8695
 	select CPU_ARM922T
 	select ARCH_REQUIRE_GPIOLIB
 	select ARCH_USES_GETTIMEOFFSET
+	select ARCH_HAS_PCI
 	help
 	  Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
 	  System-on-Chip devices.
@@ -1059,8 +1062,14 @@ config ISA_DMA
 config ISA_DMA_API
 	bool
 
+config ARCH_HAS_PCI
+	bool
+	help
+	  Architectures should select this option if they want to give
+	  user a choice to enable PCI support.
+
 config PCI
-	bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
+	bool "PCI support" if ARCH_HAS_PCI
 	help
 	  Find out whether you have a PCI motherboard. PCI is the name of a
 	  bus system, i.e. the way the CPU talks to the other stuff inside
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index 27db275..6116308 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -4,6 +4,7 @@ menu "Integrator Options"
 
 config ARCH_INTEGRATOR_AP
 	bool "Support Integrator/AP and Integrator/PP2 platforms"
+	select ARCH_HAS_PCI
 	help
 	  Include support for the ARM(R) Integrator/AP and
 	  Integrator/PP2 platforms.
diff --git a/arch/arm/mach-pxa/Kconfig b/arch/arm/mach-pxa/Kconfig
index 3b51741..67907f0 100644
--- a/arch/arm/mach-pxa/Kconfig
+++ b/arch/arm/mach-pxa/Kconfig
@@ -96,6 +96,7 @@ config MACH_ARMCORE
 	select PXA27x
 	select IWMMXT
 	select PXA25x
+	select ARCH_HAS_PCI
 
 config MACH_EM_X270
 	bool "CompuLab EM-x270 platform"
diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
index c781f30..2dd4c12 100644
--- a/arch/arm/mach-versatile/Kconfig
+++ b/arch/arm/mach-versatile/Kconfig
@@ -4,6 +4,7 @@ menu "Versatile platform type"
 config ARCH_VERSATILE_PB
 	bool "Support Versatile/PB platform"
 	select CPU_ARM926T
+	select ARCH_HAS_PCI
 	default y
 	help
 	  Include support for the ARM(R) Versatile/PB platform.
-- 
1.7.0.5


From avorontsov at mvista.com  Wed Jun  2 08:53:34 2010
From: avorontsov at mvista.com (Anton Vorontsov)
Date: Wed, 2 Jun 2010 16:53:34 +0400
Subject: [PATCH 3/4] ARM: cns3xxx: Add support for AHCI controllers
In-Reply-To: <4C065349.80005@ru.mvista.com>
References: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
	<20100601165540.GC7123@oksana.dev.rtsoft.ru>
	<4C065349.80005@ru.mvista.com>
Message-ID: <20100602125334.GA29292@oksana.dev.rtsoft.ru>

On Wed, Jun 02, 2010 at 04:49:13PM +0400, Sergei Shtylyov wrote:
[..]
> >+	/* De-Asscer SATA Reset */
> >+	tmp = PM_SOFT_RST_REG;
> >+	tmp |= 0x1 << PM_SOFT_RST_REG_OFFST_SATA;
> 
>    You have *REG_OFFSET* everywhere, and *REG_OFFST* here -- a typo?

No, this is how PM_SOFT_RST_REG_OFFST_* bits actually named.

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2


From sshtylyov at mvista.com  Wed Jun  2 08:54:57 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Wed, 02 Jun 2010 16:54:57 +0400
Subject: [PATCH 3/4] ARM: cns3xxx: Add support for AHCI controllers
In-Reply-To: <20100602125334.GA29292@oksana.dev.rtsoft.ru>
References: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
	<20100601165540.GC7123@oksana.dev.rtsoft.ru>
	<4C065349.80005@ru.mvista.com>
	<20100602125334.GA29292@oksana.dev.rtsoft.ru>
Message-ID: <4C0654A1.8060906@mvista.com>

Hello.

Anton Vorontsov wrote:

>>> +	/* De-Asscer SATA Reset */
>>> +	tmp = PM_SOFT_RST_REG;
>>> +	tmp |= 0x1 << PM_SOFT_RST_REG_OFFST_SATA;
>>    You have *REG_OFFSET* everywhere, and *REG_OFFST* here -- a typo?

> No, this is how PM_SOFT_RST_REG_OFFST_* bits actually named.

    Then I guess it's the typo(s) there. ;-)

WBR, Sergei


From avorontsov at mvista.com  Wed Jun  2 09:07:10 2010
From: avorontsov at mvista.com (Anton Vorontsov)
Date: Wed, 2 Jun 2010 17:07:10 +0400
Subject: [PATCH 3/4] ARM: cns3xxx: Add support for AHCI controllers
In-Reply-To: <4C0654A1.8060906@mvista.com>
References: <20100601165409.GA29614@oksana.dev.rtsoft.ru>
	<20100601165540.GC7123@oksana.dev.rtsoft.ru>
	<4C065349.80005@ru.mvista.com>
	<20100602125334.GA29292@oksana.dev.rtsoft.ru>
	<4C0654A1.8060906@mvista.com>
Message-ID: <20100602130710.GB11897@oksana.dev.rtsoft.ru>

On Wed, Jun 02, 2010 at 04:54:57PM +0400, Sergei Shtylyov wrote:
[...]
> >>>+	/* De-Asscer SATA Reset */
> >>>+	tmp = PM_SOFT_RST_REG;
> >>>+	tmp |= 0x1 << PM_SOFT_RST_REG_OFFST_SATA;
> >>   You have *REG_OFFSET* everywhere, and *REG_OFFST* here -- a typo?
> 
> >No, this is how PM_SOFT_RST_REG_OFFST_* bits actually named.
> 
>    Then I guess it's the typo(s) there. ;-)

Or maybe other "OFFSET"s were meant to be "OFFST", e.g. for less
typing, who knows? :-)

But sure, I agree, cns3xxx.h's bit descriptions could be better.
In my todo list now.

Thanks,

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2


From tglx at linutronix.de  Wed Jun  2 09:06:29 2010
From: tglx at linutronix.de (Thomas Gleixner)
Date: Wed, 2 Jun 2010 15:06:29 +0200 (CEST)
Subject: [RFC PATCH] irq: handle private interrupt registration
In-Reply-To: <20100602054104.GE6465@nokia.com>
References: <1274905794-7848-1-git-send-email-adharmap@codeaurora.org>
	<20100601152652.9296c5d0.akpm@linux-foundation.org>
	<alpine.LFD.2.00.1006020110090.2933@localhost.localdomain>
	<20100602054104.GE6465@nokia.com>
Message-ID: <alpine.LFD.2.00.1006021504080.2933@localhost.localdomain>



On Wed, 2 Jun 2010, Felipe Balbi wrote:

> Hi,
> 
> On Wed, Jun 02, 2010 at 01:14:32AM +0200, ext Thomas Gleixner wrote:
> > 1) Use PER_CPU offsets for the irq numbers. The generic irq code does
> >   not care whether the interrupt number is matching any physical
> >   numbering scheme in the hardware, as long as the arch specific chip
> >   implementation knows how to deal with it, which is not rocket
> >   science to do.
> 
> FWIW, I think (1) is a better approach as the problem will vanish altogether
> and to me it sounds like the simpler approach as well. Archs which have more
> than one IRQ chip (like OMAP with the twl4030 family) will already use
> sequencial numbering anyway, so using the same approach for N cpus, to me,
> sounds like a good deal.
> 
> While at that, a question from my side: do we have a generic way of fetching
> the last IRQ number so we can easily use that to calculate the physical number
> of the IRQ line on the chip ?
> 
> On OMAP, we have been passing that number down to twl4030 via platform_data,
> but it would be better to ask genirq to tell us which was the last irq number
> "claimed".

No, we don't, but it might be a good idea to move the virq management
from powerpc into generic code so other archs can use it as
well. Needs some thought.

Thanks

	tglx


      


From ra7055 at freescale.com  Wed Jun  2 09:08:35 2010
From: ra7055 at freescale.com (Rob Herring)
Date: Wed, 02 Jun 2010 08:08:35 -0500
Subject: [PATCH 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <20100602073650.GK26820@pengutronix.de>
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
	<20100602073650.GK26820@pengutronix.de>
Message-ID: <1275484115.6821.10.camel@ra7055-laptop>

On Wed, 2010-06-02 at 09:36 +0200, Sascha Hauer wrote:
> Hi Jason,
> 
> On Tue, Jun 01, 2010 at 11:10:41PM +0800, Jason Wang wrote:
> > 3-stack is a reference board from Freescale for their i.MX51 SoC.
> > 
> > Add board definition, Kconfig and Makefile to enable Freescale 3-stack
> > board.
> 
> The debug board code looks the same like in mach-mx31_3ds.c. Does
> anybody know how similar the different debug boards for the 3ds boards
> are? ATM we only have the mx31_3ds with debug board support in the
> kernel. This could be the moment to go for a arch/arm/plat-mxc/3ds-debugboard.c

All debug boards are the same h/w design. The CPLD program has changed
for muxed addr and data bus support on MX51, but it retains
compatibility with other boards. The interface mode is set automatically
by signals tied off on the personality board, so there are no s/w
differences. 

Rob


From davem at davemloft.net  Wed Jun  2 09:13:44 2010
From: davem at davemloft.net (David Miller)
Date: Wed, 02 Jun 2010 06:13:44 -0700 (PDT)
Subject: [PATCH v2] net/fec: fix pm to survive to suspend/resume
In-Reply-To: <1275163490-13027-1-git-send-email-eric@eukrea.com>
References: <20100529.001534.57459102.davem@davemloft.net>
	<1275163490-13027-1-git-send-email-eric@eukrea.com>
Message-ID: <20100602.061344.129778393.davem@davemloft.net>

From: Eric B?nard <eric at eukrea.com>
Date: Sat, 29 May 2010 22:04:50 +0200

> * in the actual driver, calling fec_stop and fec_enet_init doesn't
> allow to have a working network interface at resume (where a
> ifconfig down and up is required to recover the interface)
> * by using fec_enet_close and fec_enet_open, this patch solves this
> problem and handle the case where the link changed between suspend
> and resume
> * this patch also disable clock at suspend and reenable it at resume
> 
> Signed-off-by: Eric B?nard <eric at eukrea.com>

Applied, thanks.


From jason77.wang at gmail.com  Wed Jun  2 09:53:26 2010
From: jason77.wang at gmail.com (jason wang)
Date: Wed, 2 Jun 2010 21:53:26 +0800
Subject: [PATCH 1/3] mxc: Add support for the imx51 3-stack board
References: <82469.38984.qm@web51002.mail.re2.yahoo.com>
Message-ID: <002101cb025b$0775a0e0$9b00a8c0@wuef10f27ebed8>

>Hi Jason,

>--- On Tue, 6/1/10, Jason Wang <jason77.wang at gmail.com> wrote:
>...
>> +static void __init mx51_3ds_timer_init(void)
>> +{
>> + mx51_clocks_init(32768, 24000000, 22579200, 24576000)

>This should be:

>mx51_clocks_init(32768, 24000000, 22579200, 0)
Hi Fabio,
Thanks for your comments, you are right, i checked schematic, the CKIH2 pin is floating.
I will fix it in V2.

Thanks,
Jason.

>Regards,

>Fabio Estevam



From jason77.wang at gmail.com  Wed Jun  2 09:55:25 2010
From: jason77.wang at gmail.com (jason wang)
Date: Wed, 2 Jun 2010 21:55:25 +0800
Subject: [PATCH 3/3] mx51/clock: add keypad clock definition and
	registration
References: <495250.54370.qm@web51001.mail.re2.yahoo.com>
Message-ID: <002201cb025b$48bc71a0$9b00a8c0@wuef10f27ebed8>


> Jason,
> 
> --- On Tue, 6/1/10, Jason Wang <jason77.wang at gmail.com> wrote:
> 
>> From: Jason Wang <jason77.wang at gmail.com>
>> Subject: [PATCH 3/3] mx51/clock: add keypad clock definition and registration
>> To: s.hauer at pengutronix.de, amit.kucheria at canonical.com
>> Cc: linux-arm-kernel at lists.infradead.org
>> Date: Tuesday, June 1, 2010, 12:10 PM
>> On i.MX51 platforms, the keypad
>> controller has no gate clock, to
>> meet the imx keypad driver requirement, we add a empty
>> definition and
>> register it. Now the keypad driver can work.
> 
> I did not see an entry for the keypad at arch/arm/mach-mx5/devices.c.
> 
I placed the keypad device definition in the board-mx51_3ds.c, i will move it in the devices.c in V2.

Thanks,
Jason.

> Regards,
> 
> Fabio Estevam
> 
> 
>

From jason77.wang at gmail.com  Wed Jun  2 10:27:03 2010
From: jason77.wang at gmail.com (jason wang)
Date: Wed, 2 Jun 2010 22:27:03 +0800
Subject: [PATCH 1/3] mxc: Add support for the imx51 3-stack board
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
	<20100602073650.GK26820@pengutronix.de>
Message-ID: <002e01cb025f$b3daf110$9b00a8c0@wuef10f27ebed8>



> Hi Jason,
> 
> On Tue, Jun 01, 2010 at 11:10:41PM +0800, Jason Wang wrote:
>> 3-stack is a reference board from Freescale for their i.MX51 SoC.
>> 
>> Add board definition, Kconfig and Makefile to enable Freescale 3-stack
>> board.
> 
> The debug board code looks the same like in mach-mx31_3ds.c. Does
> anybody know how similar the different debug boards for the 3ds boards
> are? ATM we only have the mx31_3ds with debug board support in the
> kernel. This could be the moment to go for a arch/arm/plat-mxc/3ds-debugboard.c
> 
Besides mx31_3ds and mx51_3ds, the mx31_ads and mx27_ads also have the similar CPLD expanding device.
They have similar functions but different CPLD image version. That is to say, except base_addr and parent_irq_pin,
the CPLD implemented device controller(like uart and interrupt controller) will be a little bit different.
I think the software for this part could be moved to a common file like plat-mxc/mxc-debugboard.c

Because this is a big action, it will affect some exsiting platforms. How about leave this work to next
action?

Thanks,
Jason.
> Several other comments inline.
> 
Except following 1 comment, all others will be addressed in V2.

<snip>
>> 
>> Boot tested on a i.MX51 3-stack Rev2.0 board
>> + __raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
>> + __raw_writew(0, brd_io + INTR_RESET_REG);
>> + __raw_writew(0x1F, brd_io + INTR_MASK_REG);
>> + for (i = MXC_BOARD_IRQ_START;
>> +      i < (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS); i++) {
> 
> MXC_BOARD_IRQS is the maximum number of interrupts available for the
> board. What you need here instead is the number of interrupts the expio
> actually has.
> 
It seems MXC_BOARD_IRQS is the number of CPLD expanding irq(or debugboard expanding irq).

Thanks,
Jason.
<snip>

From jason77.wang at gmail.com  Wed Jun  2 10:28:37 2010
From: jason77.wang at gmail.com (jason wang)
Date: Wed, 2 Jun 2010 22:28:37 +0800
Subject: [PATCH 3/3] mx51/clock: add keypad clock definition
	andregistration
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-3-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-4-git-send-email-jason77.wang@gmail.com>
	<20100602074358.GL26820@pengutronix.de>
Message-ID: <003601cb025f$ee6cfda0$9b00a8c0@wuef10f27ebed8>

<snip>
>>  _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
>>  _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
>>  _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
>> + _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
> 
> _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
> 
> (or imx-keypad.0 depending on what id the kpp platform_device has)
> 
Accept, will be addressed in V2.

Thanks,
Jason.
> SAscha
> 
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

From jason77.wang at gmail.com  Wed Jun  2 10:29:48 2010
From: jason77.wang at gmail.com (jason wang)
Date: Wed, 2 Jun 2010 22:29:48 +0800
Subject: [PATCH 3/3] mx51/clock: add keypad clock definition and
	registration
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-3-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-4-git-send-email-jason77.wang@gmail.com>
	<20100602080054.GL2346@matterhorn.lan>
Message-ID: <003c01cb0260$162f36a0$9b00a8c0@wuef10f27ebed8>

<snip>

>>  _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
>> + _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
> 
> Should be
> 
> _REGISTER_CLOCK("imx-keypad", NULL, kpp_clk)
> 
> since that is the device id that will be used in your platform device.
>
Accept, will be fixed in V2.

Thanks,
Jason. 
> -- 
> ----------------------------------------------------------------------
> Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
> ----------------------------------------------------------------------

From nobin.mathew at gmail.com  Wed Jun  2 10:34:28 2010
From: nobin.mathew at gmail.com (Nobin Mathew)
Date: Wed, 2 Jun 2010 20:04:28 +0530
Subject: make ARM=arm menuconfig problem in mainline
In-Reply-To: <AANLkTikC61Y9g-WbqwgGDghDSy2XtgraFSRoZYkHRGTG@mail.gmail.com>
References: <AANLkTikC61Y9g-WbqwgGDghDSy2XtgraFSRoZYkHRGTG@mail.gmail.com>
Message-ID: <AANLkTilEYHVHJrj_KgF48OYCSEUcsKLi57Q_Y73d9va-@mail.gmail.com>

adding linux-arm-kernel at lists.infradead.org

Hi,

The following entry creates problem in ARM System type menu. I am
using a Fedora 12 system.

Length of bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
S3C2442, S3C2443, S3C2450" is the problem. How can I fix it.

config ARCH_S3C2410
? ? ? ?bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
S3C2442, S3C2443, S3C2450"
? ? ? ?select GENERIC_GPIO
? ? ? ?select ARCH_HAS_CPUFREQ
? ? ? ?select HAVE_CLK
? ? ? ?select ARCH_USES_GETTIMEOFFSET
? ? ? ?help
? ? ? ? ?Samsung S3C2410X CPU based systems, such as the Simtec Electronics
? ? ? ? ?BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
? ? ? ? ?the Samsung SMDK2410 development board (and derivatives).

? ? ? ? ?Note, the S3C2416 and the S3C2450 are so close that they even share
? ? ? ? ?the same SoC ID code. This means that there is no seperate machine
? ? ? ? ?directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.

Thanks
Nobin


From jason77.wang at gmail.com  Wed Jun  2 10:36:25 2010
From: jason77.wang at gmail.com (jason wang)
Date: Wed, 2 Jun 2010 22:36:25 +0800
Subject: [PATCH 1/3] mxc: Add support for the imx51 3-stack board
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
	<20100602083807.GM2346@matterhorn.lan>
Message-ID: <004001cb0261$04a16380$9b00a8c0@wuef10f27ebed8>

> On 10 Jun 01, Jason Wang wrote:
>> 3-stack is a reference board from Freescale for their i.MX51 SoC.
>> 
>> Add board definition, Kconfig and Makefile to enable Freescale 3-stack
>> board.
>> 
>> Boot tested on a i.MX51 3-stack Rev2.0 board
>> 
>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>> ---
>>  arch/arm/mach-mx5/Kconfig                       |    5 +
>>  arch/arm/mach-mx5/Makefile                      |    2 +-
>>  arch/arm/mach-mx5/board-mx51_3ds.c              |  356 +++++++++++++++++++++++
>>  arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   73 +++++
>>  arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h |   43 +++
>>  5 files changed, 478 insertions(+), 1 deletions(-)
>>  create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
>>  create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
>>  create mode 100644 arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h
<snip>
>> + .resource = mx51_3ds_kpp_resources,
>> + .dev = {
>> + .platform_data = &mx51_3ds_map_data,
>> + },
>> +};
> 
> Please move this platform device and the smsc below to devices.c, add the
> required devices for the board to an array in the board file and register it
> in board_init using
> 
> platform_add_devices(devices, ARRAY_SIZE(devices));
> 
> See the babbage board code.
> 
OK, will be fixed in V2.

Thanks,
Jason.
>> +static void mxc_init_keypad(void)
>> +{
>> + (void)platform_device_register(&mx51_3ds_keypad_device);
>> +}

<snip>
 
> Could you document expio a little better (how debug board works, at the top of
> this section)? Also, please move expio to another patch as well, I don't
> think a debug board is required for board bringup.
> 
If moving CPLD related code to a common file in near future, we can add explanation infos in Kconfig
or in that common file.

>> +/*
>> + * Disable an expio pin's interrupt by setting the bit in the imr.

<snip>

>> +#endif /* __ASM_ARCH_MXC_BOARD_MX51_3DS_H__ */
>> diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h b/arch/arm/plat-mxc/include/mach/iomux-mx51-3ds.h
>> new file mode 100644
>> index 0000000..33f1141
> 
> Get rid of this file and add what you need to the common iomux-mx51.h
> 
OK, will be addressed in V2.

Thanks,
Jason.
<snip>

From randy.dunlap at oracle.com  Wed Jun  2 11:57:48 2010
From: randy.dunlap at oracle.com (Randy Dunlap)
Date: Wed, 2 Jun 2010 08:57:48 -0700
Subject: make ARM=arm menuconfig problem in mainline
In-Reply-To: <AANLkTilEYHVHJrj_KgF48OYCSEUcsKLi57Q_Y73d9va-@mail.gmail.com>
References: <AANLkTikC61Y9g-WbqwgGDghDSy2XtgraFSRoZYkHRGTG@mail.gmail.com>
	<AANLkTilEYHVHJrj_KgF48OYCSEUcsKLi57Q_Y73d9va-@mail.gmail.com>
Message-ID: <20100602085748.6771e025.randy.dunlap@oracle.com>

On Wed, 2 Jun 2010 20:04:28 +0530 Nobin Mathew wrote:

> adding linux-arm-kernel at lists.infradead.org
> 
> Hi,
> 
> The following entry creates problem in ARM System type menu. I am
> using a Fedora 12 system.

What kind of problem does it create?
It seems to work for me (on f11, not f12).
Does it have something to do with F12 specifically?


> Length of bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
> S3C2442, S3C2443, S3C2450" is the problem. How can I fix it.

Describe the problem, please.

> config ARCH_S3C2410
> ? ? ? ?bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
> S3C2442, S3C2443, S3C2450"
> ? ? ? ?select GENERIC_GPIO
> ? ? ? ?select ARCH_HAS_CPUFREQ
> ? ? ? ?select HAVE_CLK
> ? ? ? ?select ARCH_USES_GETTIMEOFFSET
> ? ? ? ?help
> ? ? ? ? ?Samsung S3C2410X CPU based systems, such as the Simtec Electronics
> ? ? ? ? ?BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
> ? ? ? ? ?the Samsung SMDK2410 development board (and derivatives).
> 
> ? ? ? ? ?Note, the S3C2416 and the S3C2450 are so close that they even share
> ? ? ? ? ?the same SoC ID code. This means that there is no seperate machine
> ? ? ? ? ?directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.


---
~Randy
*** Remember to use Documentation/SubmitChecklist when testing your code ***


From linux at arm.linux.org.uk  Wed Jun  2 11:59:47 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 2 Jun 2010 16:59:47 +0100
Subject: [PATCH] Augment __naked__ function attribute with __noinline__
	and __noclone__
In-Reply-To: <19462.19024.560502.149871@pilspetsen.it.uu.se>
References: <1275379552-23449-1-git-send-email-mikpe@it.uu.se>
	<19462.19024.560502.149871@pilspetsen.it.uu.se>
Message-ID: <20100602155947.GA872@n2100.arm.linux.org.uk>

On Wed, Jun 02, 2010 at 02:10:56PM +0200, Mikael Pettersson wrote:
> Mikael Pettersson writes:
>  > The asm() bodies of naked functions often depend on standard calling
>  > conventions, therefore they must be noinline and noclone.  GCC 4.[56]
>  > currently fail to enforce this, see GCC PR44290.  The effect is that
>  > most arch/arm/mm/copypage-*.c modules get miscompiled, resulting in
>  > kernel crashes during bootup.
>  > 
>  > Part of the fix is to augment the __naked attribute to imply noinline
>  > and noclone.  This patch implements that, and has been verified to fix
>  > the failure to boot a gcc-4.5 compiled 2.6.34 kernel on a Thecus n2100
>  > (XScale-based mach-iop32x).
> 
> Now also tested with a gcc-4.5 compiled 2.6.35-rc1 kernel on a ds101
> (XScale-based mach-ixp4xx).

I think this needs to go somewhere near linux-kernel.


From linux at arm.linux.org.uk  Wed Jun  2 12:00:11 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 2 Jun 2010 17:00:11 +0100
Subject: [PATCH] Add kto and kfrom to input operands list.
In-Reply-To: <19462.18892.533099.360440@pilspetsen.it.uu.se>
References: <1275379600-23498-1-git-send-email-raj.khem@gmail.com>
	<19462.18892.533099.360440@pilspetsen.it.uu.se>
Message-ID: <20100602160010.GB872@n2100.arm.linux.org.uk>

On Wed, Jun 02, 2010 at 02:08:44PM +0200, Mikael Pettersson wrote:
> Khem Raj writes:
>  > When functions incoming parameters are not in input operands list gcc 4.5 does not
>  > load the parameters into registers before calling this function but the
>  > inline assembly assumes valid addresses inside this function. This
>  > breaks the code because r0 and r1 are invalid when execution enters
>  > v4wb_copy_user_page ()
>  > 
>  > Also the constant needs to be used as third input operand so account for that
>  > as well.
>  > 
>  > Tested on qemu arm.
>  > 
>  > Signed-off-by: Khem Raj <raj.khem at gmail.com>
>  > ---
>  >  arch/arm/mm/copypage-feroceon.c |    4 ++--
> 
> I've tested and verified that this bit enables a gcc-4.5 compiled kernel
> to boot on TS-119 (Kirkwood) when combined with my fix for __naked.
> With neither or only one of the patches applied, the kernel oopses hard
> in copy_user_page() as it tries to start /sbin/init.
> 
> So for the copypage-feroceon.c change:
> Tested-by: Mikael Pettersson <mikpe at it.uu.se>

Ok.


From nobin.mathew at gmail.com  Wed Jun  2 12:10:23 2010
From: nobin.mathew at gmail.com (Nobin Mathew)
Date: Wed, 2 Jun 2010 21:40:23 +0530
Subject: make ARM=arm menuconfig problem in mainline
In-Reply-To: <20100602085748.6771e025.randy.dunlap@oracle.com>
References: <AANLkTikC61Y9g-WbqwgGDghDSy2XtgraFSRoZYkHRGTG@mail.gmail.com>
	<AANLkTilEYHVHJrj_KgF48OYCSEUcsKLi57Q_Y73d9va-@mail.gmail.com>
	<20100602085748.6771e025.randy.dunlap@oracle.com>
Message-ID: <AANLkTikYYVh0S2l884s_u3efl-b413YhoNttjOJGKsrt@mail.gmail.com>

when I go to select ARM system
type(OMAP, Davinci etc), I am not seeing any entries there in the pop
up window. When I remove  bool "Samsung S3C2410, S3C2412, S3C2413,
S3C2416, S3C2440,
>> S3C2442, S3C2443, S3C2450"  it is working fine. I feel it is something to do with length of that string.

Is it possible to attach screenshots in this list?

Thanks
Nobin

On Wed, Jun 2, 2010 at 9:27 PM, Randy Dunlap <randy.dunlap at oracle.com> wrote:
> On Wed, 2 Jun 2010 20:04:28 +0530 Nobin Mathew wrote:
>
>> adding linux-arm-kernel at lists.infradead.org
>>
>> Hi,
>>
>> The following entry creates problem in ARM System type menu. I am
>> using a Fedora 12 system.
>
> What kind of problem does it create?
> It seems to work for me (on f11, not f12).
> Does it have something to do with F12 specifically?
>
>
>> Length of bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
>> S3C2442, S3C2443, S3C2450" is the problem. How can I fix it.
>
> Describe the problem, please.
>
>> config ARCH_S3C2410
>> ? ? ? ?bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
>> S3C2442, S3C2443, S3C2450"
>> ? ? ? ?select GENERIC_GPIO
>> ? ? ? ?select ARCH_HAS_CPUFREQ
>> ? ? ? ?select HAVE_CLK
>> ? ? ? ?select ARCH_USES_GETTIMEOFFSET
>> ? ? ? ?help
>> ? ? ? ? ?Samsung S3C2410X CPU based systems, such as the Simtec Electronics
>> ? ? ? ? ?BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
>> ? ? ? ? ?the Samsung SMDK2410 development board (and derivatives).
>>
>> ? ? ? ? ?Note, the S3C2416 and the S3C2450 are so close that they even share
>> ? ? ? ? ?the same SoC ID code. This means that there is no seperate machine
>> ? ? ? ? ?directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
>
>
> ---
> ~Randy
> *** Remember to use Documentation/SubmitChecklist when testing your code ***
>


From catalin.marinas at arm.com  Wed Jun  2 12:48:36 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 17:48:36 +0100
Subject: [PATCH v2 0/4] Patches for -next
Message-ID: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>

Hi,

I would like to get these patches in the linux-next tree for this
release cycle and aim to submit them for upstream 2.6.36-rc1 (next
merging window).

Updates from the first version of these patches:

- The domains removal patch was updated to allow FIQ handlers.
- I/D cache synchronisation is done in set_pte_at() for SMP systems
  (rather than in update_mmu_cache() and clearing L_PTE_EXEC in
  set_pte_at). IOW, the last patch was replaced with a new one.

Thanks.


Catalin Marinas (4):
      ARM: Remove the domain switching on ARMv6k/v7 CPUs
      ARM: Use lazy cache flushing on ARMv7 SMP systems
      ARM: Assume new page cache pages have dirty D-cache
      ARM: Synchronise the I and D caches via set_pte_at() on SMP systems


 arch/arm/include/asm/assembler.h  |   13 +++---
 arch/arm/include/asm/cacheflush.h |    6 +--
 arch/arm/include/asm/domain.h     |   31 +++++++++++++-
 arch/arm/include/asm/futex.h      |    9 ++--
 arch/arm/include/asm/pgtable.h    |   25 ++++++++++-
 arch/arm/include/asm/smp_plat.h   |    4 ++
 arch/arm/include/asm/tlbflush.h   |   12 ++++-
 arch/arm/include/asm/traps.h      |    2 +
 arch/arm/include/asm/uaccess.h    |   16 ++++---
 arch/arm/kernel/entry-armv.S      |    4 +-
 arch/arm/kernel/fiq.c             |    5 ++
 arch/arm/kernel/traps.c           |   14 ++++--
 arch/arm/lib/getuser.S            |   13 +++---
 arch/arm/lib/putuser.S            |   29 +++++++------
 arch/arm/lib/uaccess.S            |   83 +++++++++++++++++++------------------
 arch/arm/mm/Kconfig               |    8 ++++
 arch/arm/mm/copypage-v4mc.c       |    2 -
 arch/arm/mm/copypage-v6.c         |    2 -
 arch/arm/mm/copypage-xscale.c     |    2 -
 arch/arm/mm/dma-mapping.c         |    6 +++
 arch/arm/mm/fault-armv.c          |    8 ++--
 arch/arm/mm/flush.c               |   31 +++++++++-----
 arch/arm/mm/mmu.c                 |    6 +--
 arch/arm/mm/proc-macros.S         |    7 +++
 arch/arm/mm/proc-v7.S             |    5 +-
 25 files changed, 226 insertions(+), 117 deletions(-)

-- 
Catalin


From catalin.marinas at arm.com  Wed Jun  2 12:48:41 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 17:48:41 +0100
Subject: [PATCH v2 1/4] ARM: Remove the domain switching on ARMv6k/v7 CPUs
In-Reply-To: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
References: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100602164841.17783.94825.stgit@e102109-lin.cambridge.arm.com>

This patch removes the domain switching functionality via the set_fs and
__switch_to functions on cores that have a TLS register.

Currently, the ioremap and vmalloc areas share the same level 1 page
tables and therefore have the same domain (DOMAIN_KERNEL). When the
kernel domain is modified from Client to Manager (via the __set_fs or in
the __switch_to function), the XN (eXecute Never) bit is overridden and
newer CPUs can speculatively prefetch the ioremap'ed memory.

Linux performs the kernel domain switching to allow user-specific
functions (copy_to/from_user, get/put_user etc.) to access kernel
memory. In order for these functions to work with the kernel domain set
to Client, the patch modifies the LDRT/STRT and related instructions to
the LDR/STR ones.

The user pages access rights are also modified for kernel read-only
access rather than read/write so that the copy-on-write mechanism still
works. CPU_USE_DOMAINS gets disabled only if HAS_TLS_REG is defined
since writing the TLS value to the high vectors page isn't possible.

The user addresses passed to the kernel are checked by the access_ok()
function so that they do not point to the kernel space.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/assembler.h |   13 +++---
 arch/arm/include/asm/domain.h    |   31 +++++++++++++-
 arch/arm/include/asm/futex.h     |    9 ++--
 arch/arm/include/asm/traps.h     |    2 +
 arch/arm/include/asm/uaccess.h   |   16 ++++---
 arch/arm/kernel/entry-armv.S     |    4 +-
 arch/arm/kernel/fiq.c            |    5 ++
 arch/arm/kernel/traps.c          |   14 +++++-
 arch/arm/lib/getuser.S           |   13 +++---
 arch/arm/lib/putuser.S           |   29 +++++++------
 arch/arm/lib/uaccess.S           |   83 +++++++++++++++++++-------------------
 arch/arm/mm/Kconfig              |    8 ++++
 arch/arm/mm/mmu.c                |    6 +--
 arch/arm/mm/proc-macros.S        |    7 +++
 arch/arm/mm/proc-v7.S            |    5 +-
 15 files changed, 153 insertions(+), 92 deletions(-)

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..66db132 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -18,6 +18,7 @@
 #endif
 
 #include <asm/ptrace.h>
+#include <asm/domain.h>
 
 /*
  * Endian independent macros for shifting bytes within registers.
@@ -183,12 +184,12 @@
  */
 #ifdef CONFIG_THUMB2_KERNEL
 
-	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort
+	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T()
 9999:
 	.if	\inc == 1
-	\instr\cond\()bt \reg, [\ptr, #\off]
+	\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
 	.elseif	\inc == 4
-	\instr\cond\()t \reg, [\ptr, #\off]
+	\instr\cond\()\t\().w \reg, [\ptr, #\off]
 	.else
 	.error	"Unsupported inc macro argument"
 	.endif
@@ -223,13 +224,13 @@
 
 #else	/* !CONFIG_THUMB2_KERNEL */
 
-	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort
+	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort, t=T()
 	.rept	\rept
 9999:
 	.if	\inc == 1
-	\instr\cond\()bt \reg, [\ptr], #\inc
+	\instr\cond\()b\()\t \reg, [\ptr], #\inc
 	.elseif	\inc == 4
-	\instr\cond\()t \reg, [\ptr], #\inc
+	\instr\cond\()\t \reg, [\ptr], #\inc
 	.else
 	.error	"Unsupported inc macro argument"
 	.endif
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
index cc7ef40..af18cea 100644
--- a/arch/arm/include/asm/domain.h
+++ b/arch/arm/include/asm/domain.h
@@ -45,13 +45,17 @@
  */
 #define DOMAIN_NOACCESS	0
 #define DOMAIN_CLIENT	1
+#ifdef CONFIG_CPU_USE_DOMAINS
 #define DOMAIN_MANAGER	3
+#else
+#define DOMAIN_MANAGER	1
+#endif
 
 #define domain_val(dom,type)	((type) << (2*(dom)))
 
 #ifndef __ASSEMBLY__
 
-#ifdef CONFIG_MMU
+#ifdef CONFIG_CPU_USE_DOMAINS
 #define set_domain(x)					\
 	do {						\
 	__asm__ __volatile__(				\
@@ -74,5 +78,28 @@
 #define modify_domain(dom,type)	do { } while (0)
 #endif
 
+/*
+ * Generate the T (user) versions of the LDR/STR and related
+ * instructions (inline assembly)
+ */
+#ifdef CONFIG_CPU_USE_DOMAINS
+#define T(instr)	#instr "t"
+#else
+#define T(instr)	#instr
 #endif
-#endif /* !__ASSEMBLY__ */
+
+#else /* __ASSEMBLY__ */
+
+/*
+ * Generate the T (user) versions of the LDR/STR and related
+ * instructions
+ */
+#ifdef CONFIG_CPU_USE_DOMAINS
+#define T(instr)	instr ## t
+#else
+#define T(instr)	instr
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* !__ASM_PROC_DOMAIN_H */
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 540a044..b33fe70 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -13,12 +13,13 @@
 #include <linux/preempt.h>
 #include <linux/uaccess.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)	\
 	__asm__ __volatile__(					\
-	"1:	ldrt	%1, [%2]\n"				\
+	"1:	" T(ldr) "	%1, [%2]\n"			\
 	"	" insn "\n"					\
-	"2:	strt	%0, [%2]\n"				\
+	"2:	" T(str) "	%0, [%2]\n"			\
 	"	mov	%0, #0\n"				\
 	"3:\n"							\
 	"	.pushsection __ex_table,\"a\"\n"		\
@@ -97,10 +98,10 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
 	pagefault_disable();	/* implies preempt_disable() */
 
 	__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
-	"1:	ldrt	%0, [%3]\n"
+	"1:	" T(ldr) "	%0, [%3]\n"
 	"	teq	%0, %1\n"
 	"	it	eq	@ explicit IT needed for the 2b label\n"
-	"2:	streqt	%2, [%3]\n"
+	"2:	" T(streq) "	%2, [%3]\n"
 	"3:\n"
 	"	.pushsection __ex_table,\"a\"\n"
 	"	.align	3\n"
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h
index 491960b..af5d5d1 100644
--- a/arch/arm/include/asm/traps.h
+++ b/arch/arm/include/asm/traps.h
@@ -27,4 +27,6 @@ static inline int in_exception_text(unsigned long ptr)
 extern void __init early_trap_init(void);
 extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame);
 
+extern void *vectors_page;
+
 #endif
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 33e4a48..b293616 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -227,7 +227,7 @@ do {									\
 
 #define __get_user_asm_byte(x,addr,err)				\
 	__asm__ __volatile__(					\
-	"1:	ldrbt	%1,[%2]\n"				\
+	"1:	" T(ldrb) "	%1,[%2],#0\n"			\
 	"2:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
@@ -263,7 +263,7 @@ do {									\
 
 #define __get_user_asm_word(x,addr,err)				\
 	__asm__ __volatile__(					\
-	"1:	ldrt	%1,[%2]\n"				\
+	"1:	" T(ldr) "	%1,[%2],#0\n"			\
 	"2:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
@@ -308,7 +308,7 @@ do {									\
 
 #define __put_user_asm_byte(x,__pu_addr,err)			\
 	__asm__ __volatile__(					\
-	"1:	strbt	%1,[%2]\n"				\
+	"1:	" T(strb) "	%1,[%2],#0\n"			\
 	"2:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
@@ -341,7 +341,7 @@ do {									\
 
 #define __put_user_asm_word(x,__pu_addr,err)			\
 	__asm__ __volatile__(					\
-	"1:	strt	%1,[%2]\n"				\
+	"1:	" T(str) "	%1,[%2],#0\n"			\
 	"2:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
@@ -366,10 +366,10 @@ do {									\
 
 #define __put_user_asm_dword(x,__pu_addr,err)			\
 	__asm__ __volatile__(					\
- ARM(	"1:	strt	" __reg_oper1 ", [%1], #4\n"	)	\
- ARM(	"2:	strt	" __reg_oper0 ", [%1]\n"	)	\
- THUMB(	"1:	strt	" __reg_oper1 ", [%1]\n"	)	\
- THUMB(	"2:	strt	" __reg_oper0 ", [%1, #4]\n"	)	\
+ ARM(	"1:	" T(str) "	" __reg_oper1 ", [%1], #4\n"	)	\
+ ARM(	"2:	" T(str) "	" __reg_oper0 ", [%1]\n"	)	\
+ THUMB(	"1:	" T(str) "	" __reg_oper1 ", [%1]\n"	)	\
+ THUMB(	"2:	" T(str) "	" __reg_oper0 ", [%1, #4]\n"	)	\
 	"3:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 7ee48e7..ba654fa 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -736,7 +736,7 @@ ENTRY(__switch_to)
  THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
  THUMB(	str	sp, [ip], #4		   )
  THUMB(	str	lr, [ip], #4		   )
-#ifdef CONFIG_MMU
+#ifdef CONFIG_CPU_USE_DOMAINS
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
 #if defined(CONFIG_HAS_TLS_REG)
@@ -745,7 +745,7 @@ ENTRY(__switch_to)
 	mov	r4, #0xffff0fff
 	str	r3, [r4, #-15]			@ TLS val at 0xffff0ff0
 #endif
-#ifdef CONFIG_MMU
+#ifdef CONFIG_CPU_USE_DOMAINS
 	mcr	p15, 0, r6, c3, c0, 0		@ Set domain register
 #endif
 	mov	r5, r0
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 6ff7919..d601ef2 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -45,6 +45,7 @@
 #include <asm/fiq.h>
 #include <asm/irq.h>
 #include <asm/system.h>
+#include <asm/traps.h>
 
 static unsigned long no_fiq_insn;
 
@@ -77,7 +78,11 @@ int show_fiq_list(struct seq_file *p, void *v)
 
 void set_fiq_handler(void *start, unsigned int length)
 {
+#if defined(CONFIG_CPU_USE_DOMAINS)
 	memcpy((void *)0xffff001c, start, length);
+#else
+	memcpy(vectors_page + 0x1c, start, length);
+#endif
 	flush_icache_range(0xffff001c, 0xffff001c + length);
 	if (!vectors_high())
 		flush_icache_range(0x1c, 0x1c + length);
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1621e53..6bc57c5 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -36,6 +36,8 @@
 
 static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" };
 
+void *vectors_page;
+
 #ifdef CONFIG_DEBUG_USER
 unsigned int user_debug;
 
@@ -745,7 +747,11 @@ void __init trap_init(void)
 
 void __init early_trap_init(void)
 {
+#if defined(CONFIG_CPU_USE_DOMAINS)
 	unsigned long vectors = CONFIG_VECTORS_BASE;
+#else
+	unsigned long vectors = (unsigned long)vectors_page;
+#endif
 	extern char __stubs_start[], __stubs_end[];
 	extern char __vectors_start[], __vectors_end[];
 	extern char __kuser_helper_start[], __kuser_helper_end[];
@@ -764,10 +770,10 @@ void __init early_trap_init(void)
 	 * Copy signal return handlers into the vector page, and
 	 * set sigreturn to be a pointer to these.
 	 */
-	memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes,
-	       sizeof(sigreturn_codes));
-	memcpy((void *)KERN_RESTART_CODE, syscall_restart_code,
-	       sizeof(syscall_restart_code));
+	memcpy((void *)(vectors + KERN_SIGRETURN_CODE - CONFIG_VECTORS_BASE),
+	       sigreturn_codes, sizeof(sigreturn_codes));
+	memcpy((void *)(vectors + KERN_RESTART_CODE - CONFIG_VECTORS_BASE),
+	       syscall_restart_code, sizeof(syscall_restart_code));
 
 	flush_icache_range(vectors, vectors + PAGE_SIZE);
 	modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index b1631a7..1b049cd 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -28,20 +28,21 @@
  */
 #include <linux/linkage.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 ENTRY(__get_user_1)
-1:	ldrbt	r2, [r0]
+1:	T(ldrb)	r2, [r0]
 	mov	r0, #0
 	mov	pc, lr
 ENDPROC(__get_user_1)
 
 ENTRY(__get_user_2)
 #ifdef CONFIG_THUMB2_KERNEL
-2:	ldrbt	r2, [r0]
-3:	ldrbt	r3, [r0, #1]
+2:	T(ldrb)	r2, [r0]
+3:	T(ldrb)	r3, [r0, #1]
 #else
-2:	ldrbt	r2, [r0], #1
-3:	ldrbt	r3, [r0]
+2:	T(ldrb)	r2, [r0], #1
+3:	T(ldrb)	r3, [r0]
 #endif
 #ifndef __ARMEB__
 	orr	r2, r2, r3, lsl #8
@@ -53,7 +54,7 @@ ENTRY(__get_user_2)
 ENDPROC(__get_user_2)
 
 ENTRY(__get_user_4)
-4:	ldrt	r2, [r0]
+4:	T(ldr)	r2, [r0]
 	mov	r0, #0
 	mov	pc, lr
 ENDPROC(__get_user_4)
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index 5a01a23..c023fc1 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -28,9 +28,10 @@
  */
 #include <linux/linkage.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 ENTRY(__put_user_1)
-1:	strbt	r2, [r0]
+1:	T(strb)	r2, [r0]
 	mov	r0, #0
 	mov	pc, lr
 ENDPROC(__put_user_1)
@@ -39,19 +40,19 @@ ENTRY(__put_user_2)
 	mov	ip, r2, lsr #8
 #ifdef CONFIG_THUMB2_KERNEL
 #ifndef __ARMEB__
-2:	strbt	r2, [r0]
-3:	strbt	ip, [r0, #1]
+2:	T(strb)	r2, [r0]
+3:	T(strb)	ip, [r0, #1]
 #else
-2:	strbt	ip, [r0]
-3:	strbt	r2, [r0, #1]
+2:	T(strb)	ip, [r0]
+3:	T(strb)	r2, [r0, #1]
 #endif
 #else	/* !CONFIG_THUMB2_KERNEL */
 #ifndef __ARMEB__
-2:	strbt	r2, [r0], #1
-3:	strbt	ip, [r0]
+2:	T(strb)	r2, [r0], #1
+3:	T(strb)	ip, [r0]
 #else
-2:	strbt	ip, [r0], #1
-3:	strbt	r2, [r0]
+2:	T(strb)	ip, [r0], #1
+3:	T(strb)	r2, [r0]
 #endif
 #endif	/* CONFIG_THUMB2_KERNEL */
 	mov	r0, #0
@@ -59,18 +60,18 @@ ENTRY(__put_user_2)
 ENDPROC(__put_user_2)
 
 ENTRY(__put_user_4)
-4:	strt	r2, [r0]
+4:	T(str)	r2, [r0]
 	mov	r0, #0
 	mov	pc, lr
 ENDPROC(__put_user_4)
 
 ENTRY(__put_user_8)
 #ifdef CONFIG_THUMB2_KERNEL
-5:	strt	r2, [r0]
-6:	strt	r3, [r0, #4]
+5:	T(str)	r2, [r0]
+6:	T(str)	r3, [r0, #4]
 #else
-5:	strt	r2, [r0], #4
-6:	strt	r3, [r0]
+5:	T(str)	r2, [r0], #4
+6:	T(str)	r3, [r0]
 #endif
 	mov	r0, #0
 	mov	pc, lr
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
index fee9f6f..d0ece2a 100644
--- a/arch/arm/lib/uaccess.S
+++ b/arch/arm/lib/uaccess.S
@@ -14,6 +14,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 		.text
 
@@ -31,11 +32,11 @@
 		rsb	ip, ip, #4
 		cmp	ip, #2
 		ldrb	r3, [r1], #1
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		ldrgeb	r3, [r1], #1
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		ldrgtb	r3, [r1], #1
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		sub	r2, r2, ip
 		b	.Lc2u_dest_aligned
 
@@ -58,7 +59,7 @@ ENTRY(__copy_to_user)
 		addmi	ip, r2, #4
 		bmi	.Lc2u_0nowords
 		ldr	r3, [r1], #4
-USER(		strt	r3, [r0], #4)			@ May fault
+USER(		T(str)	r3, [r0], #4)			@ May fault
 		mov	ip, r0, lsl #32 - PAGE_SHIFT	@ On each page, use a ld/st??t instruction
 		rsb	ip, ip, #0
 		movs	ip, ip, lsr #32 - PAGE_SHIFT
@@ -87,18 +88,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		stmneia	r0!, {r3 - r4}			@ Shouldnt fault
 		tst	ip, #4
 		ldrne	r3, [r1], #4
-		strnet	r3, [r0], #4			@ Shouldnt fault
+		T(strne) r3, [r0], #4			@ Shouldnt fault
 		ands	ip, ip, #3
 		beq	.Lc2u_0fupi
 .Lc2u_0nowords:	teq	ip, #0
 		beq	.Lc2u_finished
 .Lc2u_nowords:	cmp	ip, #2
 		ldrb	r3, [r1], #1
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		ldrgeb	r3, [r1], #1
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		ldrgtb	r3, [r1], #1
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		b	.Lc2u_finished
 
 .Lc2u_not_enough:
@@ -119,7 +120,7 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
 		mov	r3, r7, pull #8
 		ldr	r7, [r1], #4
 		orr	r3, r3, r7, push #24
-USER(		strt	r3, [r0], #4)			@ May fault
+USER(		T(str)	r3, [r0], #4)			@ May fault
 		mov	ip, r0, lsl #32 - PAGE_SHIFT
 		rsb	ip, ip, #0
 		movs	ip, ip, lsr #32 - PAGE_SHIFT
@@ -154,18 +155,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		movne	r3, r7, pull #8
 		ldrne	r7, [r1], #4
 		orrne	r3, r3, r7, push #24
-		strnet	r3, [r0], #4			@ Shouldnt fault
+		T(strne) r3, [r0], #4			@ Shouldnt fault
 		ands	ip, ip, #3
 		beq	.Lc2u_1fupi
 .Lc2u_1nowords:	mov	r3, r7, get_byte_1
 		teq	ip, #0
 		beq	.Lc2u_finished
 		cmp	ip, #2
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		movge	r3, r7, get_byte_2
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		movgt	r3, r7, get_byte_3
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		b	.Lc2u_finished
 
 .Lc2u_2fupi:	subs	r2, r2, #4
@@ -174,7 +175,7 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
 		mov	r3, r7, pull #16
 		ldr	r7, [r1], #4
 		orr	r3, r3, r7, push #16
-USER(		strt	r3, [r0], #4)			@ May fault
+USER(		T(str)	r3, [r0], #4)			@ May fault
 		mov	ip, r0, lsl #32 - PAGE_SHIFT
 		rsb	ip, ip, #0
 		movs	ip, ip, lsr #32 - PAGE_SHIFT
@@ -209,18 +210,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		movne	r3, r7, pull #16
 		ldrne	r7, [r1], #4
 		orrne	r3, r3, r7, push #16
-		strnet	r3, [r0], #4			@ Shouldnt fault
+		T(strne) r3, [r0], #4			@ Shouldnt fault
 		ands	ip, ip, #3
 		beq	.Lc2u_2fupi
 .Lc2u_2nowords:	mov	r3, r7, get_byte_2
 		teq	ip, #0
 		beq	.Lc2u_finished
 		cmp	ip, #2
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		movge	r3, r7, get_byte_3
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		ldrgtb	r3, [r1], #0
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		b	.Lc2u_finished
 
 .Lc2u_3fupi:	subs	r2, r2, #4
@@ -229,7 +230,7 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
 		mov	r3, r7, pull #24
 		ldr	r7, [r1], #4
 		orr	r3, r3, r7, push #8
-USER(		strt	r3, [r0], #4)			@ May fault
+USER(		T(str)	r3, [r0], #4)			@ May fault
 		mov	ip, r0, lsl #32 - PAGE_SHIFT
 		rsb	ip, ip, #0
 		movs	ip, ip, lsr #32 - PAGE_SHIFT
@@ -264,18 +265,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		movne	r3, r7, pull #24
 		ldrne	r7, [r1], #4
 		orrne	r3, r3, r7, push #8
-		strnet	r3, [r0], #4			@ Shouldnt fault
+		T(strne) r3, [r0], #4			@ Shouldnt fault
 		ands	ip, ip, #3
 		beq	.Lc2u_3fupi
 .Lc2u_3nowords:	mov	r3, r7, get_byte_3
 		teq	ip, #0
 		beq	.Lc2u_finished
 		cmp	ip, #2
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		ldrgeb	r3, [r1], #1
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		ldrgtb	r3, [r1], #0
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		b	.Lc2u_finished
 ENDPROC(__copy_to_user)
 
@@ -294,11 +295,11 @@ ENDPROC(__copy_to_user)
 .Lcfu_dest_not_aligned:
 		rsb	ip, ip, #4
 		cmp	ip, #2
-USER(		ldrbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrb)	r3, [r1], #1)			@ May fault
 		strb	r3, [r0], #1
-USER(		ldrgebt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgeb) r3, [r1], #1)			@ May fault
 		strgeb	r3, [r0], #1
-USER(		ldrgtbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgtb) r3, [r1], #1)			@ May fault
 		strgtb	r3, [r0], #1
 		sub	r2, r2, ip
 		b	.Lcfu_dest_aligned
@@ -321,7 +322,7 @@ ENTRY(__copy_from_user)
 .Lcfu_0fupi:	subs	r2, r2, #4
 		addmi	ip, r2, #4
 		bmi	.Lcfu_0nowords
-USER(		ldrt	r3, [r1], #4)
+USER(		T(ldr)	r3, [r1], #4)
 		str	r3, [r0], #4
 		mov	ip, r1, lsl #32 - PAGE_SHIFT	@ On each page, use a ld/st??t instruction
 		rsb	ip, ip, #0
@@ -350,18 +351,18 @@ USER(		ldrt	r3, [r1], #4)
 		ldmneia	r1!, {r3 - r4}			@ Shouldnt fault
 		stmneia	r0!, {r3 - r4}
 		tst	ip, #4
-		ldrnet	r3, [r1], #4			@ Shouldnt fault
+		T(ldrne) r3, [r1], #4			@ Shouldnt fault
 		strne	r3, [r0], #4
 		ands	ip, ip, #3
 		beq	.Lcfu_0fupi
 .Lcfu_0nowords:	teq	ip, #0
 		beq	.Lcfu_finished
 .Lcfu_nowords:	cmp	ip, #2
-USER(		ldrbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrb)	r3, [r1], #1)			@ May fault
 		strb	r3, [r0], #1
-USER(		ldrgebt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgeb) r3, [r1], #1)			@ May fault
 		strgeb	r3, [r0], #1
-USER(		ldrgtbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgtb) r3, [r1], #1)			@ May fault
 		strgtb	r3, [r0], #1
 		b	.Lcfu_finished
 
@@ -374,7 +375,7 @@ USER(		ldrgtbt	r3, [r1], #1)			@ May fault
 
 .Lcfu_src_not_aligned:
 		bic	r1, r1, #3
-USER(		ldrt	r7, [r1], #4)			@ May fault
+USER(		T(ldr)	r7, [r1], #4)			@ May fault
 		cmp	ip, #2
 		bgt	.Lcfu_3fupi
 		beq	.Lcfu_2fupi
@@ -382,7 +383,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		addmi	ip, r2, #4
 		bmi	.Lcfu_1nowords
 		mov	r3, r7, pull #8
-USER(		ldrt	r7, [r1], #4)			@ May fault
+USER(		T(ldr)	r7, [r1], #4)			@ May fault
 		orr	r3, r3, r7, push #24
 		str	r3, [r0], #4
 		mov	ip, r1, lsl #32 - PAGE_SHIFT
@@ -417,7 +418,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		stmneia	r0!, {r3 - r4}
 		tst	ip, #4
 		movne	r3, r7, pull #8
-USER(		ldrnet	r7, [r1], #4)			@ May fault
+USER(		T(ldrne) r7, [r1], #4)			@ May fault
 		orrne	r3, r3, r7, push #24
 		strne	r3, [r0], #4
 		ands	ip, ip, #3
@@ -437,7 +438,7 @@ USER(		ldrnet	r7, [r1], #4)			@ May fault
 		addmi	ip, r2, #4
 		bmi	.Lcfu_2nowords
 		mov	r3, r7, pull #16
-USER(		ldrt	r7, [r1], #4)			@ May fault
+USER(		T(ldr)	r7, [r1], #4)			@ May fault
 		orr	r3, r3, r7, push #16
 		str	r3, [r0], #4
 		mov	ip, r1, lsl #32 - PAGE_SHIFT
@@ -473,7 +474,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		stmneia	r0!, {r3 - r4}
 		tst	ip, #4
 		movne	r3, r7, pull #16
-USER(		ldrnet	r7, [r1], #4)			@ May fault
+USER(		T(ldrne) r7, [r1], #4)			@ May fault
 		orrne	r3, r3, r7, push #16
 		strne	r3, [r0], #4
 		ands	ip, ip, #3
@@ -485,7 +486,7 @@ USER(		ldrnet	r7, [r1], #4)			@ May fault
 		strb	r3, [r0], #1
 		movge	r3, r7, get_byte_3
 		strgeb	r3, [r0], #1
-USER(		ldrgtbt	r3, [r1], #0)			@ May fault
+USER(		T(ldrgtb) r3, [r1], #0)			@ May fault
 		strgtb	r3, [r0], #1
 		b	.Lcfu_finished
 
@@ -493,7 +494,7 @@ USER(		ldrgtbt	r3, [r1], #0)			@ May fault
 		addmi	ip, r2, #4
 		bmi	.Lcfu_3nowords
 		mov	r3, r7, pull #24
-USER(		ldrt	r7, [r1], #4)			@ May fault
+USER(		T(ldr)	r7, [r1], #4)			@ May fault
 		orr	r3, r3, r7, push #8
 		str	r3, [r0], #4
 		mov	ip, r1, lsl #32 - PAGE_SHIFT
@@ -528,7 +529,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		stmneia	r0!, {r3 - r4}
 		tst	ip, #4
 		movne	r3, r7, pull #24
-USER(		ldrnet	r7, [r1], #4)			@ May fault
+USER(		T(ldrne) r7, [r1], #4)			@ May fault
 		orrne	r3, r3, r7, push #8
 		strne	r3, [r0], #4
 		ands	ip, ip, #3
@@ -538,9 +539,9 @@ USER(		ldrnet	r7, [r1], #4)			@ May fault
 		beq	.Lcfu_finished
 		cmp	ip, #2
 		strb	r3, [r0], #1
-USER(		ldrgebt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgeb) r3, [r1], #1)			@ May fault
 		strgeb	r3, [r0], #1
-USER(		ldrgtbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgtb) r3, [r1], #1)			@ May fault
 		strgtb	r3, [r0], #1
 		b	.Lcfu_finished
 ENDPROC(__copy_from_user)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..f33c422 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -599,6 +599,14 @@ config CPU_CP15_MPU
 	help
 	  Processor has the CP15 register, which has MPU related registers.
 
+config CPU_USE_DOMAINS
+	bool
+	depends on MMU
+	default y if !HAS_TLS_REG
+	help
+	  This option enables or disables the use of domain switching
+	  via the set_fs() function.
+
 #
 # CPU supports 36-bit I/O
 #
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 2858941..499e22d 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -25,6 +25,7 @@
 #include <asm/smp_plat.h>
 #include <asm/tlb.h>
 #include <asm/highmem.h>
+#include <asm/traps.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -935,12 +936,11 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 {
 	struct map_desc map;
 	unsigned long addr;
-	void *vectors;
 
 	/*
 	 * Allocate the vector page early.
 	 */
-	vectors = alloc_bootmem_low_pages(PAGE_SIZE);
+	vectors_page = alloc_bootmem_low_pages(PAGE_SIZE);
 
 	for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
 		pmd_clear(pmd_off_k(addr));
@@ -980,7 +980,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 	 * location (0xffff0000).  If we aren't using high-vectors, also
 	 * create a mapping at the low-vectors virtual address.
 	 */
-	map.pfn = __phys_to_pfn(virt_to_phys(vectors));
+	map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
 	map.virtual = 0xffff0000;
 	map.length = PAGE_SIZE;
 	map.type = MT_HIGH_VECTORS;
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 7d63bea..337f102 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -99,6 +99,10 @@
  *  110x   0   1   0	r/w	r/o
  *  11x0   0   1   0	r/w	r/o
  *  1111   0   1   1	r/w	r/w
+ *
+ * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
+ *  110x   1   1   1	r/o	r/o
+ *  11x0   1   1   1	r/o	r/o
  */
 	.macro	armv6_mt_table pfx
 \pfx\()_mt_table:
@@ -138,8 +142,11 @@
 
 	tst	r1, #L_PTE_USER
 	orrne	r3, r3, #PTE_EXT_AP1
+#ifdef CONFIG_CPU_USE_DOMAINS
+	@ allow kernel read/write access to read-only user pages
 	tstne	r3, #PTE_EXT_APX
 	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+#endif
 
 	tst	r1, #L_PTE_EXEC
 	orreq	r3, r3, #PTE_EXT_XN
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a..c1c3fe0 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -152,8 +152,11 @@ ENTRY(cpu_v7_set_pte_ext)
 
 	tst	r1, #L_PTE_USER
 	orrne	r3, r3, #PTE_EXT_AP1
+#ifdef CONFIG_CPU_USE_DOMAINS
+	@ allow kernel read/write access to read-only user pages
 	tstne	r3, #PTE_EXT_APX
 	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+#endif
 
 	tst	r1, #L_PTE_EXEC
 	orreq	r3, r3, #PTE_EXT_XN
@@ -240,8 +243,6 @@ __v7_setup:
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
 	orr	r4, r4, #TTB_FLAGS
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
-	mov	r10, #0x1f			@ domains 0, 1 = manager
-	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
 	/*
 	 * Memory region attributes with SCTLR.TRE=1
 	 *



From catalin.marinas at arm.com  Wed Jun  2 12:48:47 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 17:48:47 +0100
Subject: [PATCH v2 2/4] ARM: Use lazy cache flushing on ARMv7 SMP systems
In-Reply-To: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
References: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100602164847.17783.86056.stgit@e102109-lin.cambridge.arm.com>

ARMv7 processors like Cortex-A9 broadcast the cache maintenance
operations in hardware. This patch allows the
flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
similar to the UP case.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/smp_plat.h |    4 ++++
 arch/arm/mm/fault-armv.c        |    2 --
 arch/arm/mm/flush.c             |   13 ++++---------
 3 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e621530..963a338 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -13,9 +13,13 @@ static inline int tlb_ops_need_broadcast(void)
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
 
+#if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
+#define cache_ops_need_broadcast()	0
+#else
 static inline int cache_ops_need_broadcast(void)
 {
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
+#endif
 
 #endif
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 9b906de..9d77d90 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -168,10 +168,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 		return;
 
 	mapping = page_mapping(page);
-#ifndef CONFIG_SMP
 	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
 		__flush_dcache_page(mapping, page);
-#endif
 	if (mapping) {
 		if (cache_is_vivt())
 			make_coherent(mapping, vma, addr, ptep, pfn);
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index c6844cb..5ad8711 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -17,6 +17,7 @@
 #include <asm/smp_plat.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
+#include <asm/smp_plat.h>
 
 #include "mm.h"
 
@@ -93,12 +94,10 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
 #define flush_pfn_alias(pfn,vaddr)	do { } while (0)
 #endif
 
-#ifdef CONFIG_SMP
 static void flush_ptrace_access_other(void *args)
 {
 	__flush_icache_all();
 }
-#endif
 
 static
 void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
@@ -122,11 +121,9 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 	if (vma->vm_flags & VM_EXEC) {
 		unsigned long addr = (unsigned long)kaddr;
 		__cpuc_coherent_kern_range(addr, addr + len);
-#ifdef CONFIG_SMP
 		if (cache_ops_need_broadcast())
 			smp_call_function(flush_ptrace_access_other,
 					  NULL, 1);
-#endif
 	}
 }
 
@@ -246,12 +243,10 @@ void flush_dcache_page(struct page *page)
 
 	mapping = page_mapping(page);
 
-#ifndef CONFIG_SMP
-	if (!PageHighMem(page) && mapping && !mapping_mapped(mapping))
+	if (!cache_ops_need_broadcast() &&
+	    !PageHighMem(page) && mapping && !mapping_mapped(mapping))
 		set_bit(PG_dcache_dirty, &page->flags);
-	else
-#endif
-	{
+	else {
 		__flush_dcache_page(mapping, page);
 		if (mapping && cache_is_vivt())
 			__flush_dcache_aliases(mapping, page);



From catalin.marinas at arm.com  Wed Jun  2 12:48:52 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 17:48:52 +0100
Subject: [PATCH v2 3/4] ARM: Assume new page cache pages have dirty D-cache
In-Reply-To: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
References: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100602164852.17783.82034.stgit@e102109-lin.cambridge.arm.com>

There are places in Linux where writes to newly allocated page cache
pages happen without a subsequent call to flush_dcache_page() (several
PIO drivers including USB HCD). This patch changes the meaning of
PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly
mapped page in update_mmu_cache().

The patch also sets the PG_arch_1 bit in the DMA cache maintenance
function to avoid additional cache flushing in update_mmu_cache().

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/cacheflush.h |    6 +++---
 arch/arm/include/asm/tlbflush.h   |    2 +-
 arch/arm/mm/copypage-v4mc.c       |    2 +-
 arch/arm/mm/copypage-v6.c         |    2 +-
 arch/arm/mm/copypage-xscale.c     |    2 +-
 arch/arm/mm/dma-mapping.c         |    6 ++++++
 arch/arm/mm/fault-armv.c          |    4 ++--
 arch/arm/mm/flush.c               |    3 ++-
 8 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..d3730f0 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -137,10 +137,10 @@
 #endif
 
 /*
- * This flag is used to indicate that the page pointed to by a pte
- * is dirty and requires cleaning before returning it to the user.
+ * This flag is used to indicate that the page pointed to by a pte is clean
+ * and does not require cleaning before returning it to the user.
  */
-#define PG_dcache_dirty PG_arch_1
+#define PG_dcache_clean PG_arch_1
 
 /*
  *	MM Cache Management
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index bd863d8..40a7092 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -552,7 +552,7 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 #endif
 
 /*
- * if PG_dcache_dirty is set for the page, we need to ensure that any
+ * If PG_dcache_clean is not set for the page, we need to ensure that any
  * cache entries for the kernels virtual memory range are written
  * back to the page.
  */
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 598c51a..b806151 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -73,7 +73,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
 {
 	void *kto = kmap_atomic(to, KM_USER1);
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index f55fa10..bdba6c6 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -79,7 +79,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
 	unsigned int offset = CACHE_COLOUR(vaddr);
 	unsigned long kfrom, kto;
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	/* FIXME: not highmem safe */
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 9920c0a..649bbcd 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -95,7 +95,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
 {
 	void *kto = kmap_atomic(to, KM_USER1);
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 13fa536..bb9b612 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -508,6 +508,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
 		outer_inv_range(paddr, paddr + size);
 
 	dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+
+	/*
+	 * Mark the D-cache clean for this page to avoid extra flushing.
+	 */
+	if (dir != DMA_TO_DEVICE)
+		set_bit(PG_dcache_clean, &page->flags);
 }
 EXPORT_SYMBOL(___dma_page_dev_to_cpu);
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 9d77d90..91a691f 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -141,7 +141,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
  * a page table, or changing an existing PTE.  Basically, there are two
  * things that we need to take care of:
  *
- *  1. If PG_dcache_dirty is set for the page, we need to ensure
+ *  1. If PG_dcache_clean is not set for the page, we need to ensure
  *     that any cache entries for the kernels virtual memory
  *     range are written back to the page.
  *  2. If we have multiple shared mappings of the same space in
@@ -168,7 +168,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 		return;
 
 	mapping = page_mapping(page);
-	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
 		__flush_dcache_page(mapping, page);
 	if (mapping) {
 		if (cache_is_vivt())
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 5ad8711..6f55e36 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -245,13 +245,14 @@ void flush_dcache_page(struct page *page)
 
 	if (!cache_ops_need_broadcast() &&
 	    !PageHighMem(page) && mapping && !mapping_mapped(mapping))
-		set_bit(PG_dcache_dirty, &page->flags);
+		clear_bit(PG_dcache_clean, &page->flags);
 	else {
 		__flush_dcache_page(mapping, page);
 		if (mapping && cache_is_vivt())
 			__flush_dcache_aliases(mapping, page);
 		else if (mapping)
 			__flush_icache_all();
+		set_bit(PG_dcache_clean, &page->flags);
 	}
 }
 EXPORT_SYMBOL(flush_dcache_page);



From catalin.marinas at arm.com  Wed Jun  2 12:48:58 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 17:48:58 +0100
Subject: [PATCH v2 4/4] ARM: Synchronise the I and D caches via set_pte_at()
	on SMP systems
In-Reply-To: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
References: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100602164858.17783.30961.stgit@e102109-lin.cambridge.arm.com>

On SMP systems, there is a small chance of a PTE becoming visible to a
different CPU before the cache maintenance operations in
update_mmu_cache(). This patch follows the IA-64 and PowerPC approach of
synchronising the I and D caches via the set_pte_at() function. In this
case, there is no need for update_mmu_cache() to be implemented since
lazy cache flushing is already handled by the time this function is
called.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/pgtable.h  |   25 ++++++++++++++++++++++---
 arch/arm/include/asm/tlbflush.h |   10 +++++++++-
 arch/arm/mm/fault-armv.c        |    2 ++
 arch/arm/mm/flush.c             |   15 +++++++++++++++
 4 files changed, 48 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index ab68cf1..a3752f5 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -278,9 +278,24 @@ extern struct page *empty_zero_page;
 
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
 
-#define set_pte_at(mm,addr,ptep,pteval) do { \
-	set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \
- } while (0)
+#ifndef CONFIG_SMP
+static inline void __sync_icache_dcache(pte_t pteval)
+{
+}
+#else
+extern void __sync_icache_dcache(pte_t pteval);
+#endif
+
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+			      pte_t *ptep, pte_t pteval)
+{
+	if (addr >= TASK_SIZE)
+		set_pte_ext(ptep, pteval, 0);
+	else {
+		__sync_icache_dcache(pteval);
+		set_pte_ext(ptep, pteval, PTE_EXT_NG);
+	}
+}
 
 /*
  * The following only work if pte_present() is true.
@@ -292,6 +307,10 @@ extern struct page *empty_zero_page;
 #define pte_young(pte)		(pte_val(pte) & L_PTE_YOUNG)
 #define pte_special(pte)	(0)
 
+#define pte_present_exec_user(pte) \
+	((pte_val(pte) & (L_PTE_PRESENT | L_PTE_EXEC | L_PTE_USER)) == \
+	 (L_PTE_PRESENT | L_PTE_EXEC | L_PTE_USER))
+
 #define PTE_BIT_FUNC(fn,op) \
 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
 
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 40a7092..6aabedd 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -554,10 +554,18 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 /*
  * If PG_dcache_clean is not set for the page, we need to ensure that any
  * cache entries for the kernels virtual memory range are written
- * back to the page.
+ * back to the page. On SMP systems, the cache coherency is handled in the
+ * set_pte_at() function.
  */
+#ifndef CONFIG_SMP
 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 	pte_t *ptep);
+#else
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+				    unsigned long addr, pte_t *ptep)
+{
+}
+#endif
 
 #endif
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 91a691f..030f1da 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -28,6 +28,7 @@
 
 static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
 
+#ifndef CONFIG_SMP
 /*
  * We take the easy way out of this problem - we make the
  * PTE uncacheable.  However, we leave the write buffer on.
@@ -177,6 +178,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 			__flush_icache_all();
 	}
 }
+#endif	/* !CONFIG_SMP */
 
 /*
  * Check whether the write buffer has physical address aliasing
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 6f55e36..2d08a5e 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -212,6 +212,21 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p
 	flush_dcache_mmap_unlock(mapping);
 }
 
+#ifdef CONFIG_SMP
+void __sync_icache_dcache(pte_t pteval)
+{
+	unsigned long pfn = pte_pfn(pteval);
+
+	if (pfn_valid(pfn) && pte_present_exec_user(pteval)) {
+		struct page *page = pfn_to_page(pfn);
+
+		if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+			__flush_dcache_page(NULL, page);
+		__flush_icache_all();
+	}
+}
+#endif
+
 /*
  * Ensure cache coherency between kernel mapping and userspace mapping
  * of this page.



From randy.dunlap at oracle.com  Wed Jun  2 12:49:46 2010
From: randy.dunlap at oracle.com (Randy Dunlap)
Date: Wed, 02 Jun 2010 09:49:46 -0700
Subject: [TEMP PATCH] Re: make ARM=arm menuconfig problem in mainline
In-Reply-To: <AANLkTilpzeYVExQfLgpVmS3bPvb_h3kmWaatidekI-0r@mail.gmail.com>
References: <AANLkTikC61Y9g-WbqwgGDghDSy2XtgraFSRoZYkHRGTG@mail.gmail.com>	<AANLkTilEYHVHJrj_KgF48OYCSEUcsKLi57Q_Y73d9va-@mail.gmail.com>	<20100602085748.6771e025.randy.dunlap@oracle.com>
	<AANLkTilpzeYVExQfLgpVmS3bPvb_h3kmWaatidekI-0r@mail.gmail.com>
Message-ID: <4C068BAA.4030004@oracle.com>

On 06/02/10 09:08, Nobin Mathew wrote:
> 
> On Wed, Jun 2, 2010 at 9:27 PM, Randy Dunlap <randy.dunlap at oracle.com> wrote:
>> On Wed, 2 Jun 2010 20:04:28 +0530 Nobin Mathew wrote:
>>
>>> adding linux-arm-kernel at lists.infradead.org
>>>
>>> Hi,
>>>
>>> The following entry creates problem in ARM System type menu. I am
>>> using a Fedora 12 system.
>>
>> What kind of problem does it create?
>> It seems to work for me (on f11, not f12).
>> Does it have something to do with F12 specifically?
>>
>>
>>> Length of bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
>>> S3C2442, S3C2443, S3C2450" is the problem. How can I fix it.
>>
>> Describe the problem, please.

[please don't top-post]

> Sorry if attachments are not allowed, when I go to select ARM system
> type(OMAP, Davinci etc), I am not seeing any entries there in the pop
> up window. When I remove  bool "Samsung S3C2410, S3C2412, S3C2413,
> S3C2416, S3C2440,
>>> S3C2442, S3C2443, S3C2450"  it is working fine. I feel it is something to do with length of that string.
> 
> Thanks
> Nobin


OK, I see that now.  Well, it is some kind of problem.
Adding cc to linux-kbuild mailing list.


The patch below fixes the problem temporarily, but the bool string length does
seem to be a problem.

Thanks for your report.

-- 
From: Randy Dunlap <randy.dunlap at oracle.com>

The bool "long string" causes the choices not to be displayed,
so temporarily change it to a shorter string until a real fix
is found.

Signed-off-by: Randy Dunlap <randy.dunlap at oracle.com>
Reported-by: Nobin Mathew <nobin.mathew at gmail.com>
Cc: Ben Dooks <ben-linux at fluff.org>
---
 arch/arm/Kconfig |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- linux-next-20100602.orig/arch/arm/Kconfig
+++ linux-next-20100602/arch/arm/Kconfig
@@ -629,7 +629,7 @@ config ARCH_SA1100
 	  Support for StrongARM 11x0 based boards.
 
 config ARCH_S3C2410
-	bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
+	bool "Samsung S3C24xx"
 	select GENERIC_GPIO
 	select ARCH_HAS_CPUFREQ
 	select HAVE_CLK


From catalin.marinas at arm.com  Wed Jun  2 12:53:52 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 17:53:52 +0100
Subject: [PATCH v2 0/4] Patches for -next
In-Reply-To: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
References: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <1275497632.23442.27.camel@e102109-lin.cambridge.arm.com>

On Wed, 2010-06-02 at 17:48 +0100, Catalin Marinas wrote:
> Catalin Marinas (4):
>       ARM: Remove the domain switching on ARMv6k/v7 CPUs
>       ARM: Use lazy cache flushing on ARMv7 SMP systems
>       ARM: Assume new page cache pages have dirty D-cache
>       ARM: Synchronise the I and D caches via set_pte_at() on SMP systems

Forgot to mention - for easier testing, these patches are also available
in my "proposed" branch at:

http://git.kernel.org/?p=linux/kernel/git/cmarinas/linux-2.6-cm.git;a=summary

BTW, does anyone know how to get linux-arm-kernel subscribed to
patchwork.kernel.org? I know we have a patch system but that's only for
final merging rather than RFC patches.

-- 
Catalin



From catalin.marinas at arm.com  Wed Jun  2 13:02:11 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 18:02:11 +0100
Subject: [PATCH v2 0/8] Patches for 2.6.35
Message-ID: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>

These are a set of patches I'd like to get merged in 2.6.35 (during the
-rc) period.

The first one was posted some time ago but deferred because of other
conflicting patch (the 16-way PL310).

Some of the other patches are necessary fixes plus a few trivial ones.

Thanks.


Catalin Marinas (8):
      ARM: Improve the L2 cache performance when PL310 is used
      ARM: Align machine_desc.phys_io to a 1MB section
      ARM: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds
      ARM: The v6_dma_inv_range() function must preserve data on SMP
      ARM: Add a config option for the ARM11MPCore DMA cache maintenance workaround
      ARM: Add support for the MOVW/MOVT relocations in Thumb-2
      ARM: Remove dummy loads from the original relocation address
      ARM: Do not compile the Thumb-2 module relocations on an ARM kernel


 arch/arm/include/asm/elf.h |    2 +
 arch/arm/kernel/head.S     |    2 +
 arch/arm/kernel/module.c   |   34 +++++++++++++++++++++++
 arch/arm/mm/Kconfig        |   26 ++++++++++++++++++
 arch/arm/mm/cache-l2x0.c   |   65 ++++++++++++++++++++++++++++++--------------
 arch/arm/mm/cache-v6.S     |   18 +++++++++---
 arch/arm/mm/dma-mapping.c  |    2 +
 7 files changed, 124 insertions(+), 25 deletions(-)

-- 
Catalin


From catalin.marinas at arm.com  Wed Jun  2 13:02:18 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 18:02:18 +0100
Subject: [PATCH v2 1/8] ARM: Improve the L2 cache performance when PL310 is
	used
In-Reply-To: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
References: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100602170216.18569.41768.stgit@e102109-lin.cambridge.arm.com>

With this L2 cache controller, the cache maintenance by PA and sync
operations are atomic and do not require a "wait" loop or spinlocks.
This patch conditionally defines the cache_wait() function and locking
primitives (rather than duplicating the functions or file).

Since L2x0 cache controllers do not work with ARMv7 CPUs, the patch
automatically enables CACHE_PL310 when CPU_V7 is defined.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/mm/Kconfig      |    7 +++++
 arch/arm/mm/cache-l2x0.c |   65 +++++++++++++++++++++++++++++++---------------
 2 files changed, 51 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..521f3cc 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -770,6 +770,13 @@ config CACHE_L2X0
 	help
 	  This option enables the L2x0 PrimeCell.
 
+config CACHE_PL310
+	bool
+	depends on CACHE_L2X0
+	default y if CPU_V7
+	help
+	  This option enables support for the PL310 cache controller.
+
 config CACHE_TAUROS2
 	bool "Enable the Tauros2 L2 cache controller"
 	depends on (ARCH_DOVE || ARCH_MMP)
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 9819869..e4fa95c 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -26,16 +26,39 @@
 #define CACHE_LINE_SIZE		32
 
 static void __iomem *l2x0_base;
-static DEFINE_SPINLOCK(l2x0_lock);
 static uint32_t l2x0_way_mask;	/* Bitmask of active ways */
 
-static inline void cache_wait(void __iomem *reg, unsigned long mask)
+static inline void cache_wait_always(void __iomem *reg, unsigned long mask)
 {
 	/* wait for the operation to complete */
 	while (readl(reg) & mask)
 		;
 }
 
+#ifdef CONFIG_CACHE_PL310
+
+static inline void cache_wait(void __iomem *reg, unsigned long mask)
+{
+	/* cache operations are atomic */
+}
+
+#define _l2x0_lock(lock, flags)		((void)(flags))
+#define _l2x0_unlock(lock, flags)	((void)(flags))
+
+#define block_end(start, end)		(end)
+
+#else	/* !CONFIG_CACHE_PL310 */
+
+#define cache_wait			cache_wait_always
+
+static DEFINE_SPINLOCK(l2x0_lock);
+#define _l2x0_lock(lock, flags)		spin_lock_irqsave(lock, flags)
+#define _l2x0_unlock(lock, flags)	spin_unlock_irqrestore(lock, flags)
+
+#define block_end(start, end)		((start) + min((end) - (start), 4096UL))
+
+#endif	/* CONFIG_CACHE_PL310 */
+
 static inline void cache_sync(void)
 {
 	void __iomem *base = l2x0_base;
@@ -98,9 +121,9 @@ static void l2x0_cache_sync(void)
 {
 	unsigned long flags;
 
-	spin_lock_irqsave(&l2x0_lock, flags);
+	_l2x0_lock(&l2x0_lock, flags);
 	cache_sync();
-	spin_unlock_irqrestore(&l2x0_lock, flags);
+	_l2x0_unlock(&l2x0_lock, flags);
 }
 
 static inline void l2x0_inv_all(void)
@@ -108,11 +131,11 @@ static inline void l2x0_inv_all(void)
 	unsigned long flags;
 
 	/* invalidate all ways */
-	spin_lock_irqsave(&l2x0_lock, flags);
+	_l2x0_lock(&l2x0_lock, flags);
 	writel(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
 	cache_wait(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
 	cache_sync();
-	spin_unlock_irqrestore(&l2x0_lock, flags);
+	_l2x0_unlock(&l2x0_lock, flags);
 }
 
 static void l2x0_inv_range(unsigned long start, unsigned long end)
@@ -120,7 +143,7 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
 	void __iomem *base = l2x0_base;
 	unsigned long flags;
 
-	spin_lock_irqsave(&l2x0_lock, flags);
+	_l2x0_lock(&l2x0_lock, flags);
 	if (start & (CACHE_LINE_SIZE - 1)) {
 		start &= ~(CACHE_LINE_SIZE - 1);
 		debug_writel(0x03);
@@ -137,7 +160,7 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
 	}
 
 	while (start < end) {
-		unsigned long blk_end = start + min(end - start, 4096UL);
+		unsigned long blk_end = block_end(start, end);
 
 		while (start < blk_end) {
 			l2x0_inv_line(start);
@@ -145,13 +168,13 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
 		}
 
 		if (blk_end < end) {
-			spin_unlock_irqrestore(&l2x0_lock, flags);
-			spin_lock_irqsave(&l2x0_lock, flags);
+			_l2x0_unlock(&l2x0_lock, flags);
+			_l2x0_lock(&l2x0_lock, flags);
 		}
 	}
 	cache_wait(base + L2X0_INV_LINE_PA, 1);
 	cache_sync();
-	spin_unlock_irqrestore(&l2x0_lock, flags);
+	_l2x0_unlock(&l2x0_lock, flags);
 }
 
 static void l2x0_clean_range(unsigned long start, unsigned long end)
@@ -159,10 +182,10 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
 	void __iomem *base = l2x0_base;
 	unsigned long flags;
 
-	spin_lock_irqsave(&l2x0_lock, flags);
+	_l2x0_lock(&l2x0_lock, flags);
 	start &= ~(CACHE_LINE_SIZE - 1);
 	while (start < end) {
-		unsigned long blk_end = start + min(end - start, 4096UL);
+		unsigned long blk_end = block_end(start, end);
 
 		while (start < blk_end) {
 			l2x0_clean_line(start);
@@ -170,13 +193,13 @@ static void l2x0_clean_range(unsigned long start, unsigned long end)
 		}
 
 		if (blk_end < end) {
-			spin_unlock_irqrestore(&l2x0_lock, flags);
-			spin_lock_irqsave(&l2x0_lock, flags);
+			_l2x0_unlock(&l2x0_lock, flags);
+			_l2x0_lock(&l2x0_lock, flags);
 		}
 	}
 	cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
 	cache_sync();
-	spin_unlock_irqrestore(&l2x0_lock, flags);
+	_l2x0_unlock(&l2x0_lock, flags);
 }
 
 static void l2x0_flush_range(unsigned long start, unsigned long end)
@@ -184,10 +207,10 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 	void __iomem *base = l2x0_base;
 	unsigned long flags;
 
-	spin_lock_irqsave(&l2x0_lock, flags);
+	_l2x0_lock(&l2x0_lock, flags);
 	start &= ~(CACHE_LINE_SIZE - 1);
 	while (start < end) {
-		unsigned long blk_end = start + min(end - start, 4096UL);
+		unsigned long blk_end = block_end(start, end);
 
 		debug_writel(0x03);
 		while (start < blk_end) {
@@ -197,13 +220,13 @@ static void l2x0_flush_range(unsigned long start, unsigned long end)
 		debug_writel(0x00);
 
 		if (blk_end < end) {
-			spin_unlock_irqrestore(&l2x0_lock, flags);
-			spin_lock_irqsave(&l2x0_lock, flags);
+			_l2x0_unlock(&l2x0_lock, flags);
+			_l2x0_lock(&l2x0_lock, flags);
 		}
 	}
 	cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
 	cache_sync();
-	spin_unlock_irqrestore(&l2x0_lock, flags);
+	_l2x0_unlock(&l2x0_lock, flags);
 }
 
 void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)



From catalin.marinas at arm.com  Wed Jun  2 13:02:23 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 18:02:23 +0100
Subject: [PATCH v2 2/8] ARM: Align machine_desc.phys_io to a 1MB section
In-Reply-To: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
References: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100602170223.18569.70412.stgit@e102109-lin.cambridge.arm.com>

Platforms like RealView don't pass a section-aligned pointer via the
machine_desc structure. This patch aligns the pointer in the
__create_page_tables function. Reported by Tony Thompson.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/kernel/head.S |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..82ea924 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -302,6 +302,8 @@ __create_page_tables:
 	movhi	r3, #0x0800
 	add	r6, r0, r3
 	ldr	r3, [r8, #MACHINFO_PHYSIO]
+	mov	r3, r3, lsr #20			@ 1MB-aligned address
+	mov	r3, r3, lsl #20
 	orr	r3, r3, r7
 1:	str	r3, [r0], #4
 	add	r3, r3, #1 << 20



From catalin.marinas at arm.com  Wed Jun  2 13:02:29 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 18:02:29 +0100
Subject: [PATCH v2 3/8] ARM: Avoid the CONSISTENT_DMA_SIZE warning on noMMU
	builds
In-Reply-To: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
References: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100602170229.18569.22753.stgit@e102109-lin.cambridge.arm.com>

This macro is not defined when !CONFIG_MMU.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/mm/dma-mapping.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 13fa536..c4de90f 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -25,6 +25,7 @@
 #include <asm/sizes.h>
 
 /* Sanity check size */
+#ifdef CONFIG_MMU
 #if (CONSISTENT_DMA_SIZE % SZ_2M)
 #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
 #endif
@@ -32,6 +33,7 @@
 #define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
 #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
 #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
+#endif
 
 static u64 get_coherent_dma_mask(struct device *dev)
 {



From catalin.marinas at arm.com  Wed Jun  2 13:02:34 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 18:02:34 +0100
Subject: [PATCH v2 4/8] ARM: The v6_dma_inv_range() function must preserve
	data on SMP
In-Reply-To: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
References: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100602170234.18569.57694.stgit@e102109-lin.cambridge.arm.com>

A recent patch for DMA cache maintenance on ARM11MPCore added a write
for ownership trick to the v6_dma_inv_range() function. Such operation
destroys data already present in the buffer. However, this function is
used with with dma_sync_single_for_device() which is supposed to
preserve the existing data transfered into the buffer. This patch adds a
combination of read/write for ownership to preserve the original data.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Reported-by: Ronen Shitrit <rshitrit at marvell.com>
---
 arch/arm/mm/cache-v6.S |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index e46ecd8..332b48c 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -212,7 +212,8 @@ v6_dma_inv_range:
 #endif
 1:
 #ifdef CONFIG_SMP
-	str	r0, [r0]			@ write for ownership
+	ldr	r2, [r0]			@ read for ownership
+	str	r2, [r0]			@ write for ownership
 #endif
 #ifdef HARVARD_CACHE
 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D line



From catalin.marinas at arm.com  Wed Jun  2 13:02:40 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 18:02:40 +0100
Subject: [PATCH v2 5/8] ARM: Add a config option for the ARM11MPCore DMA
	cache maintenance workaround
In-Reply-To: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
References: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100602170240.18569.44852.stgit@e102109-lin.cambridge.arm.com>

Commit f4d6477f introduced a workaround for the lack of hardware
broadcasting of the cache maintenance operations on ARM11MPCore.
However, the workaround is only valid on CPUs that do not do speculative
loads into the D-cache.

This patch adds a Kconfig option with the corresponding help to make the
above clear. When the DMA_CACHE_RWFO option is disabled, the kernel
behaviour is that prior to the f4d6477f commit. This also allows ARMv6
UP processors with speculative loads to work correctly.

For other processors, a different workaround may be needed.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Ronen Shitrit <rshitrit at marvell.com>
---
 arch/arm/mm/Kconfig    |   19 +++++++++++++++++++
 arch/arm/mm/cache-v6.S |   15 ++++++++++++---
 2 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 521f3cc..adfc663 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -735,6 +735,25 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
 	  Forget about fast user space cmpxchg support.
 	  It is just not possible.
 
+config DMA_CACHE_RWFO
+	bool "Enable read/write for ownership DMA cache maintenance"
+	depends on CPU_V6 && SMP
+	default y
+	help
+	  The Snoop Control Unit on ARM11MPCore does not detect the
+	  cache maintenance operations and the dma_{map,unmap}_area()
+	  functions may leave stale cache entries on other CPUs. By
+	  enabling this option, Read or Write For Ownership in the ARMv6
+	  DMA cache maintenance functions is performed. These LDR/STR
+	  instructions change the cache line state to shared or modified
+	  so that the cache operation has the desired effect.
+
+	  Note that the workaround is only valid on processors that do
+	  not perform speculative loads into the D-cache. For such
+	  processors, if cache maintenance operations are not broadcast
+	  in hardware, other workarounds are needed (e.g. cache
+	  maintenance broadcasting in software via FIQ).
+
 config OUTER_CACHE
 	bool
 
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 332b48c..86aa689 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -211,7 +211,7 @@ v6_dma_inv_range:
 	mcrne	p15, 0, r1, c7, c15, 1		@ clean & invalidate unified line
 #endif
 1:
-#ifdef CONFIG_SMP
+#ifdef CONFIG_DMA_CACHE_RWFO
 	ldr	r2, [r0]			@ read for ownership
 	str	r2, [r0]			@ write for ownership
 #endif
@@ -235,7 +235,7 @@ v6_dma_inv_range:
 v6_dma_clean_range:
 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
-#ifdef CONFIG_SMP
+#ifdef CONFIG_DMA_CACHE_RWFO
 	ldr	r2, [r0]			@ read for ownership
 #endif
 #ifdef HARVARD_CACHE
@@ -258,7 +258,7 @@ v6_dma_clean_range:
 ENTRY(v6_dma_flush_range)
 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
-#ifdef CONFIG_SMP
+#ifdef CONFIG_DMA_CACHE_RWFO
 	ldr	r2, [r0]			@ read for ownership
 	str	r2, [r0]			@ write for ownership
 #endif
@@ -284,9 +284,13 @@ ENTRY(v6_dma_map_area)
 	add	r1, r1, r0
 	teq	r2, #DMA_FROM_DEVICE
 	beq	v6_dma_inv_range
+#ifndef CONFIG_DMA_CACHE_RWFO
+	b	v6_dma_clean_range
+#else
 	teq	r2, #DMA_TO_DEVICE
 	beq	v6_dma_clean_range
 	b	v6_dma_flush_range
+#endif
 ENDPROC(v6_dma_map_area)
 
 /*
@@ -296,6 +300,11 @@ ENDPROC(v6_dma_map_area)
  *	- dir	- DMA direction
  */
 ENTRY(v6_dma_unmap_area)
+#ifndef CONFIG_DMA_CACHE_RWFO
+	add	r1, r1, r0
+	teq	r2, #DMA_TO_DEVICE
+	bne	v6_dma_inv_range
+#endif
 	mov	pc, lr
 ENDPROC(v6_dma_unmap_area)
 



From catalin.marinas at arm.com  Wed Jun  2 13:02:45 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 18:02:45 +0100
Subject: [PATCH v2 6/8] ARM: Add support for the MOVW/MOVT relocations in
	Thumb-2
In-Reply-To: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
References: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100602170245.18569.26668.stgit@e102109-lin.cambridge.arm.com>

The patch adds handling case for the R_ARM_THM_MOVW_ABS_NC and
R_ARM_THM_MOVT_ABS relocations in arch/arm/kernel/module.c. Such
relocations may appear in Thumb-2 compiled kernel modules.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Reported-by: Kyungmin Park <kmpark at infradead.org>
---
 arch/arm/include/asm/elf.h |    2 ++
 arch/arm/kernel/module.c   |   32 ++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 51662fe..4d0e730 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -59,6 +59,8 @@ typedef struct user_fp elf_fpregset_t;
 
 #define R_ARM_THM_CALL		10
 #define R_ARM_THM_JUMP24	30
+#define R_ARM_THM_MOVW_ABS_NC	47
+#define R_ARM_THM_MOVT_ABS	48
 
 /*
  * These are used to set parameters in the core dumps.
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index c628bdf..ae3c804 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -237,6 +237,38 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 			lower = *(u16 *)(loc + 2);
 			break;
 
+		case R_ARM_THM_MOVW_ABS_NC:
+		case R_ARM_THM_MOVT_ABS:
+			upper = *(u16 *)loc;
+			lower = *(u16 *)(loc + 2);
+
+			/*
+			 * MOVT/MOVW instructions encoding in Thumb-2:
+			 *
+			 * i	= upper[10]
+			 * imm4	= upper[3:0]
+			 * imm3	= lower[14:12]
+			 * imm8	= lower[7:0]
+			 *
+			 * imm16 = imm4:i:imm3:imm8
+			 */
+			offset = ((upper & 0x000f) << 12) |
+				((upper & 0x0400) << 1) |
+				((lower & 0x7000) >> 4) | (lower & 0x00ff);
+			offset = (offset ^ 0x8000) - 0x8000;
+			offset += sym->st_value;
+
+			if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS)
+				offset >>= 16;
+
+			*(u16 *)loc = (u16)((upper & 0xfbf0) |
+					    ((offset & 0xf000) >> 12) |
+					    ((offset & 0x0800) >> 1));
+			*(u16 *)(loc + 2) = (u16)((lower & 0x8f00) |
+						  ((offset & 0x0700) << 4) |
+						  (offset & 0x00ff));
+			break;
+
 		default:
 			printk(KERN_ERR "%s: unknown relocation: %u\n",
 			       module->name, ELF32_R_TYPE(rel->r_info));



From catalin.marinas at arm.com  Wed Jun  2 13:02:51 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 18:02:51 +0100
Subject: [PATCH v2 7/8] ARM: Remove dummy loads from the original relocation
	address
In-Reply-To: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
References: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100602170251.18569.3944.stgit@e102109-lin.cambridge.arm.com>

Reading back the upper and lower values in the R_ARM_THM_CALL and
R_ARM_THM_JUMP24 case was introduced by a previous commit but they are
not needed.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/kernel/module.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index ae3c804..aab7fca 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -233,8 +233,6 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 			*(u16 *)(loc + 2) = (u16)((lower & 0xd000) |
 						  (j1 << 13) | (j2 << 11) |
 						  ((offset >> 1) & 0x07ff));
-			upper = *(u16 *)loc;
-			lower = *(u16 *)(loc + 2);
 			break;
 
 		case R_ARM_THM_MOVW_ABS_NC:



From catalin.marinas at arm.com  Wed Jun  2 13:02:56 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 18:02:56 +0100
Subject: [PATCH v2 8/8] ARM: Do not compile the Thumb-2 module relocations
	on an ARM kernel
In-Reply-To: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
References: <20100602170039.18569.41823.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100602170256.18569.89549.stgit@e102109-lin.cambridge.arm.com>

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/kernel/module.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index aab7fca..6b46058 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -102,7 +102,9 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 		unsigned long loc;
 		Elf32_Sym *sym;
 		s32 offset;
+#ifdef CONFIG_THUMB2_KERNEL
 		u32 upper, lower, sign, j1, j2;
+#endif
 
 		offset = ELF32_R_SYM(rel->r_info);
 		if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) {
@@ -185,6 +187,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 					(offset & 0x0fff);
 			break;
 
+#ifdef CONFIG_THUMB2_KERNEL
 		case R_ARM_THM_CALL:
 		case R_ARM_THM_JUMP24:
 			upper = *(u16 *)loc;
@@ -266,6 +269,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 						  ((offset & 0x0700) << 4) |
 						  (offset & 0x00ff));
 			break;
+#endif
 
 		default:
 			printk(KERN_ERR "%s: unknown relocation: %u\n",



From nobin.mathew at gmail.com  Wed Jun  2 13:11:32 2010
From: nobin.mathew at gmail.com (Nobin Mathew)
Date: Wed, 2 Jun 2010 22:41:32 +0530
Subject: [TEMP PATCH] Re: make ARM=arm menuconfig problem in mainline
In-Reply-To: <4C068BAA.4030004@oracle.com>
References: <AANLkTikC61Y9g-WbqwgGDghDSy2XtgraFSRoZYkHRGTG@mail.gmail.com>
	<AANLkTilEYHVHJrj_KgF48OYCSEUcsKLi57Q_Y73d9va-@mail.gmail.com>
	<20100602085748.6771e025.randy.dunlap@oracle.com>
	<AANLkTilpzeYVExQfLgpVmS3bPvb_h3kmWaatidekI-0r@mail.gmail.com>
	<4C068BAA.4030004@oracle.com>
Message-ID: <AANLkTimGeOsW5Zt5wR7t4uIUoju3wDXSqSFcIiemdsNU@mail.gmail.com>

On Wed, Jun 2, 2010 at 10:19 PM, Randy Dunlap <randy.dunlap at oracle.com> wrote:
> On 06/02/10 09:08, Nobin Mathew wrote:
>>
>> On Wed, Jun 2, 2010 at 9:27 PM, Randy Dunlap <randy.dunlap at oracle.com> wrote:
>>> On Wed, 2 Jun 2010 20:04:28 +0530 Nobin Mathew wrote:
>>>
>>>> adding linux-arm-kernel at lists.infradead.org
>>>>
>>>> Hi,
>>>>
>>>> The following entry creates problem in ARM System type menu. I am
>>>> using a Fedora 12 system.
>>>
>>> What kind of problem does it create?
>>> It seems to work for me (on f11, not f12).
>>> Does it have something to do with F12 specifically?
>>>
>>>
>>>> Length of bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
>>>> S3C2442, S3C2443, S3C2450" is the problem. How can I fix it.
>>>
>>> Describe the problem, please.
>
> [please don't top-post]
Sorry I forgot. I rarely send mails to this list.
>
>> Sorry if attachments are not allowed, when I go to select ARM system
>> type(OMAP, Davinci etc), I am not seeing any entries there in the pop
>> up window. When I remove ?bool "Samsung S3C2410, S3C2412, S3C2413,
>> S3C2416, S3C2440,
>>>> S3C2442, S3C2443, S3C2450" ?it is working fine. I feel it is something to do with length of that string.
>>
>> Thanks
>> Nobin
>
>
> OK, I see that now. ?Well, it is some kind of problem.
> Adding cc to linux-kbuild mailing list.
>
>
> The patch below fixes the problem temporarily, but the bool string length does
> seem to be a problem.
>
> Thanks for your report.
>
> --
> From: Randy Dunlap <randy.dunlap at oracle.com>
>
> The bool "long string" causes the choices not to be displayed,
> so temporarily change it to a shorter string until a real fix
> is found.
>
> Signed-off-by: Randy Dunlap <randy.dunlap at oracle.com>
> Reported-by: Nobin Mathew <nobin.mathew at gmail.com>
> Cc: Ben Dooks <ben-linux at fluff.org>
> ---
> ?arch/arm/Kconfig | ? ?2 +-
> ?1 file changed, 1 insertion(+), 1 deletion(-)
>
> --- linux-next-20100602.orig/arch/arm/Kconfig
> +++ linux-next-20100602/arch/arm/Kconfig
> @@ -629,7 +629,7 @@ config ARCH_SA1100
> ? ? ? ? ?Support for StrongARM 11x0 based boards.
>
> ?config ARCH_S3C2410
> - ? ? ? bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
> + ? ? ? bool "Samsung S3C24xx"
> ? ? ? ?select GENERIC_GPIO
> ? ? ? ?select ARCH_HAS_CPUFREQ
> ? ? ? ?select HAVE_CLK
>


From s.hauer at pengutronix.de  Wed Jun  2 13:23:34 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 2 Jun 2010 19:23:34 +0200
Subject: [PATCH 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <002e01cb025f$b3daf110$9b00a8c0@wuef10f27ebed8>
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
	<20100602073650.GK26820@pengutronix.de>
	<002e01cb025f$b3daf110$9b00a8c0@wuef10f27ebed8>
Message-ID: <20100602172334.GS26820@pengutronix.de>

On Wed, Jun 02, 2010 at 10:27:03PM +0800, jason wang wrote:
> 
> 
> > Hi Jason,
> > 
> > On Tue, Jun 01, 2010 at 11:10:41PM +0800, Jason Wang wrote:
> >> 3-stack is a reference board from Freescale for their i.MX51 SoC.
> >> 
> >> Add board definition, Kconfig and Makefile to enable Freescale 3-stack
> >> board.
> > 
> > The debug board code looks the same like in mach-mx31_3ds.c. Does
> > anybody know how similar the different debug boards for the 3ds boards
> > are? ATM we only have the mx31_3ds with debug board support in the
> > kernel. This could be the moment to go for a arch/arm/plat-mxc/3ds-debugboard.c
> > 
> Besides mx31_3ds and mx51_3ds, the mx31_ads and mx27_ads also have the similar CPLD expanding device.
> They have similar functions but different CPLD image version. That is to say, except base_addr and parent_irq_pin,
> the CPLD implemented device controller(like uart and interrupt controller) will be a little bit different.
> I think the software for this part could be moved to a common file like plat-mxc/mxc-debugboard.c
> 
> Because this is a big action, it will affect some exsiting platforms. How about leave this work to next
> action?
> 
> Thanks,
> Jason.
> > Several other comments inline.
> > 
> Except following 1 comment, all others will be addressed in V2.
> 
> <snip>
> >> 
> >> Boot tested on a i.MX51 3-stack Rev2.0 board
> >> + __raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
> >> + __raw_writew(0, brd_io + INTR_RESET_REG);
> >> + __raw_writew(0x1F, brd_io + INTR_MASK_REG);
> >> + for (i = MXC_BOARD_IRQ_START;
> >> +      i < (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS); i++) {
> > 
> > MXC_BOARD_IRQS is the maximum number of interrupts available for the
> > board. What you need here instead is the number of interrupts the expio
> > actually has.
> > 
> It seems MXC_BOARD_IRQS is the number of CPLD expanding irq(or debugboard expanding irq).

Not exactly. See mach/irqs.h:

/*
 * The next 16 interrupts are for board specific purposes.  Since
 * the kernel can only run on one machine at a time, we can re-use
 * these.  If you need more, increase MXC_BOARD_IRQS, but keep it
 * within sensible limits.
 */
#define MXC_BOARD_IRQ_START     (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)

#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
#define MXC_BOARD_IRQS  80
#else
#define MXC_BOARD_IRQS  16
#endif


Remember that we can compile the kernel for more than one board at a
time. So if MACH_MX31ADS_WM1133_EV1 is compiled in we will have 60 board
irqs. Ok, you will hardly compile a kernel for mx31ads and mx51, but
there could well come a mx51 board with more irqs in which case your
expio handler goes nuts.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From Jacob.Tanenbaum at logicpd.com  Wed Jun  2 13:54:43 2010
From: Jacob.Tanenbaum at logicpd.com (Jacob Tanenbaum)
Date: Wed,  2 Jun 2010 13:54:43 -0400
Subject: [PATCH 1/2] Adding LogicPD OMAP 3530 LV SOM AND OMAP 35X
Message-ID: <1275501284-17160-1-git-send-email-Jacob.Tanenbaum@logicpd.com>

        Adding LogicPD OMAP3 board support

        Adding support for LogicPD's OMAP 3530 LV SOM and
        OMAP 35x Torpedo board.

        Signed-off-by: Jacob Tanenbaum <Jacob.Tanenbaum at logicpd.com>
---
 arch/arm/configs/omap3_logic_defconfig |  990 ++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/Kconfig            |    8 +
 arch/arm/mach-omap2/Makefile           |    4 +
 arch/arm/mach-omap2/board-omap3logic.c |  185 ++++++
 4 files changed, 1187 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/configs/omap3_logic_defconfig
 create mode 100644 arch/arm/mach-omap2/board-omap3logic.c

diff --git a/arch/arm/configs/omap3_logic_defconfig b/arch/arm/configs/omap3_logic_defconfig
new file mode 100644
index 0000000..90f5ecd
--- /dev/null
+++ b/arch/arm/configs/omap3_logic_defconfig
@@ -0,0 +1,990 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32
+# Wed May  5 19:56:47 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_OPROFILE_ARMV7=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_GROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_RT_GROUP_SCHED is not set
+CONFIG_USER_SCHED=y
+# CONFIG_CGROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_TRACEPOINTS=y
+CONFIG_OPROFILE=y
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+CONFIG_ARCH_OMAP=y
+# CONFIG_ARCH_BCMRING is not set
+
+#
+# TI OMAP Implementations
+#
+CONFIG_ARCH_OMAP_OTG=y
+# CONFIG_ARCH_OMAP1 is not set
+# CONFIG_ARCH_OMAP2 is not set
+CONFIG_ARCH_OMAP3=y
+# CONFIG_ARCH_OMAP4 is not set
+
+#
+# OMAP Feature Selections
+#
+# CONFIG_OMAP_DEBUG_POWERDOMAIN is not set
+# CONFIG_OMAP_DEBUG_CLOCKDOMAIN is not set
+CONFIG_OMAP_RESET_CLOCKS=y
+CONFIG_OMAP_MUX=y
+CONFIG_OMAP_MUX_DEBUG=y
+CONFIG_OMAP_MUX_WARNINGS=y
+CONFIG_OMAP_MCBSP=y
+CONFIG_OMAP_MBOX_FWK=m
+# CONFIG_OMAP_MPU_TIMER is not set
+CONFIG_OMAP_32K_TIMER=y
+CONFIG_OMAP_32K_TIMER_HZ=128
+CONFIG_OMAP_DM_TIMER=y
+CONFIG_OMAP_LL_DEBUG_UART1=y
+# CONFIG_OMAP_LL_DEBUG_UART2 is not set
+# CONFIG_OMAP_LL_DEBUG_UART3 is not set
+# CONFIG_OMAP_LL_DEBUG_NONE is not set
+# CONFIG_OMAP_PM_NONE is not set
+CONFIG_OMAP_PM_NOOP=y
+CONFIG_ARCH_OMAP34XX=y
+CONFIG_ARCH_OMAP3430=y
+
+#
+# OMAP Board Type
+#
+# CONFIG_MACH_OMAP3_BEAGLE is not set
+# CONFIG_MACH_OMAP_LDP is not set
+CONFIG_MACH_OMAP3530_LV_SOM=y
+CONFIG_MACH_OMAP3_TORPEDO=y
+# CONFIG_MACH_OVERO is not set
+# CONFIG_MACH_OMAP3EVM is not set
+# CONFIG_MACH_OMAP3517EVM is not set
+# CONFIG_MACH_OMAP3_PANDORA is not set
+# CONFIG_MACH_OMAP_3430SDP is not set
+# CONFIG_MACH_NOKIA_RX51 is not set
+# CONFIG_MACH_OMAP_ZOOM2 is not set
+# CONFIG_MACH_OMAP_ZOOM3 is not set
+# CONFIG_MACH_CM_T35 is not set
+# CONFIG_MACH_IGEP0020 is not set
+# CONFIG_MACH_OMAP_3630SDP is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+CONFIG_ARM_THUMBEE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=128
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_LEDS=y
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=" debug "
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_DEBUG=y
+CONFIG_CPU_FREQ_STAT=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_VERBOSE is not set
+CONFIG_CAN_PM_TRACE=y
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+# CONFIG_PM_TEST_SUSPEND is not set
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_TWL4030_PWRBUTTON=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_OMAP=y
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+CONFIG_GPIO_TWL4030=y
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+CONFIG_TWL4030_CORE=y
+CONFIG_TWL4030_POWER=y
+# CONFIG_TWL4030_CODEC is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+CONFIG_REGULATOR_TWL4030=y
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_OMAP2_DSS is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+CONFIG_RTC_DRV_TWL4030=y
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# CBUS support
+#
+# CONFIG_CBUS is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+CONFIG_PRINT_QUOTA_WARNING=y
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=y
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_NOP_TRACER=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_RING_BUFFER=y
+CONFIG_EVENT_TRACING=y
+CONFIG_CONTEXT_SWITCH_TRACER=y
+CONFIG_RING_BUFFER_ALLOW_SWAP=y
+CONFIG_TRACING=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_RING_BUFFER_BENCHMARK is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+CONFIG_BINARY_PRINTF=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 2455dcc..f670faa 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -69,6 +69,14 @@ config MACH_OMAP_LDP
 	depends on ARCH_OMAP3
 	select OMAP_PACKAGE_CBB
 
+config MACH_OMAP3530_LV_SOM
+        bool "OMAP3 Logic 3530 LV SOM board"
+        depends on ARCH_OMAP3
+
+config MACH_OMAP3_TORPEDO
+        bool "OMAP3 Logic 35x Torpedo board"
+        depends on ARCH_OMAP3
+
 config MACH_OVERO
 	bool "Gumstix Overo board"
 	depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 4b9fc57..77422be 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -109,6 +109,10 @@ obj-$(CONFIG_MACH_DEVKIT8000)     	+= board-devkit8000.o \
                                            hsmmc.o
 obj-$(CONFIG_MACH_OMAP_LDP)		+= board-ldp.o \
 					   hsmmc.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o \
+                                           hsmmc.o
+obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o \
+                                           hsmmc.o
 obj-$(CONFIG_MACH_OVERO)		+= board-overo.o \
 					   hsmmc.o
 obj-$(CONFIG_MACH_OMAP3EVM)		+= board-omap3evm.o \
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
new file mode 100644
index 0000000..fe5db85
--- /dev/null
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -0,0 +1,185 @@
+/*
+ * linux/arch/arm/mach-omap2/board-omap3logic.c
+ *
+ * Copyright (C) 2010 Li-Pro.Net
+ * Stephan Linz <linz at li-pro.net>
+ *
+ * Copyright (C) 2010 Logic Product Development, Inc.
+ * Peter Barada <peter.barada at logicpd.com>
+ *
+ * Modified from Beagle, EVM, and RX51
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <linux/regulator/machine.h>
+
+#include<linux/i2c/twl.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include "mux.h"
+
+#include <plat/mux.h>
+#include <plat/board.h>
+#include <plat/common.h>
+#include <plat/gpmc.h>
+#include <plat/timer-gp.h>
+
+/* Micron MT46H32M32LF-6 */
+/* FIXME: borrowed from sdram-micron-mt46h32m32lf-6.h because on LogicPD
+ * boards we can't use the default values -- why? I suspect the reason
+ * lies in the boot strap code. We correct this part if we have ported
+ * U-Boot and X-Load. */
+#include <plat/sdrc.h>
+static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
+	[0] = {
+		.rate	     = 166000000,
+		.actim_ctrla = 0xaa9db4c6,
+		.actim_ctrlb = 0x00011517,
+		.rfr_ctrl    = 0x0004e201,
+		.mr	     = 0x00000032,
+	},
+	[1] = {
+		.rate	     = 165941176,
+		.actim_ctrla = 0xaa9db4c6,
+		.actim_ctrlb = 0x00011517,
+		.rfr_ctrl    = 0x0004e201,
+		.mr	     = 0x00000032,
+	},
+	[2] = {
+		.rate	     = 83000000,
+		.actim_ctrla = 0x8a99b481,
+		.actim_ctrlb = 0x00011312,
+		.rfr_ctrl    = 0x0003de01,
+		.mr	     = 0x00000032,
+	},
+	[3] = {
+		.rate	     = 82970588,
+		.actim_ctrla = 0x8a99b481,
+		.actim_ctrlb = 0x00011312,
+		.rfr_ctrl    = 0x0003de01,
+		.mr	     = 0x00000032,
+	},
+	[4] = {
+		.rate	     = 0
+	},
+};
+
+static int omap3logic_twl_gpio_setup(struct device *dev,
+				unsigned gpio, unsigned ngpio)
+{
+	return 0;
+}
+
+static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
+	.gpio_base	= OMAP_MAX_GPIO_LINES,
+	.irq_base	= TWL4030_GPIO_IRQ_BASE,
+	.irq_end	= TWL4030_GPIO_IRQ_END,
+	.use_leds	= true,
+	.pullups	= BIT(1),
+	.pulldowns	= BIT(2)  | BIT(6)  | BIT(7)  | BIT(8)
+			| BIT(13) | BIT(15) | BIT(16) | BIT(17),
+	.setup		= omap3logic_twl_gpio_setup,
+};
+
+static struct twl4030_platform_data omap3logic_twldata = {
+	.irq_base	= TWL4030_IRQ_BASE,
+	.irq_end	= TWL4030_IRQ_END,
+
+	/* platform_data for children goes here */
+	.gpio		= &omap3logic_gpio_data,
+};
+
+static struct i2c_board_info __initdata omap3logic_i2c_boardinfo[] = {
+	{
+		I2C_BOARD_INFO("twl4030", 0x48),
+		.flags = I2C_CLIENT_WAKE,
+		.irq = INT_34XX_SYS_NIRQ,
+		.platform_data = &omap3logic_twldata,
+	},
+};
+
+static int __init omap3logic_i2c_init(void)
+{
+	omap_register_i2c_bus(1, 2600, omap3logic_i2c_boardinfo,
+				ARRAY_SIZE(omap3logic_i2c_boardinfo));
+	return 0;
+}
+
+static struct omap_board_config_kernel omap3logic_config[] __initdata = {
+};
+
+static void __init omap3logic_init_irq(void)
+{
+	omap_board_config = omap3logic_config;
+	omap_board_config_size = ARRAY_SIZE(omap3logic_config);
+	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
+				mt46h32m32lf6_sdrc_params);
+	omap_init_irq();
+#ifdef CONFIG_OMAP_32K_TIMER
+	omap2_gp_clockevent_set_gptimer(12);
+#endif
+	omap_gpio_init();
+}
+
+static struct platform_device *omap3logic_devices[] __initdata = {
+};
+
+static void __init omap3logic_init(void)
+{
+	omap3logic_i2c_init();
+	platform_add_devices(omap3logic_devices,
+				ARRAY_SIZE(omap3logic_devices));
+	omap_serial_init();
+
+	/* Ensure SDRC pins are mux'd for self-refresh */
+/*	omap_cfg_reg(H16_34XX_SDRC_CKE0);
+	omap_cfg_reg(H17_34XX_SDRC_CKE1);
+	omap_cfg_reg(SDRC_CKE0);
+	omap_cfg_reg(SDRC_CKE1); */
+	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
+	omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
+}
+
+static void __init omap3logic_map_io(void)
+{
+	omap2_set_globals_343x();
+	omap34xx_map_common_io();
+}
+
+MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
+	/* Maintainer: Peter Barada <peterb at logicpd.com> */
+	.phys_io	= 0x48000000,
+	.io_pg_offst	= ((0xd8000000) >> 18) & 0xfffc,
+	.boot_params	= 0x80000100,
+	.map_io		= omap3logic_map_io,
+	.init_irq	= omap3logic_init_irq,
+	.init_machine	= omap3logic_init,
+	.timer		= &omap_timer,
+MACHINE_END
+
+MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
+	/* Maintainer: Peter Barada <peterb at logicpd.com> */
+	.phys_io	= 0x48000000,
+	.io_pg_offst	= ((0xd8000000) >> 18) & 0xfffc,
+	.boot_params	= 0x80000100,
+	.map_io		= omap3logic_map_io,
+	.init_irq	= omap3logic_init_irq,
+	.init_machine	= omap3logic_init,
+	.timer		= &omap_timer,
+MACHINE_END
-- 
1.6.0.4



From Jacob.Tanenbaum at logicpd.com  Wed Jun  2 13:54:44 2010
From: Jacob.Tanenbaum at logicpd.com (Jacob Tanenbaum)
Date: Wed,  2 Jun 2010 13:54:44 -0400
Subject: [PATCH 2/2] Adding low-level init for hsmmc controller for OMAP
	3540LV SOM and OMAP 35x Torpedo
In-Reply-To: <1275501284-17160-1-git-send-email-Jacob.Tanenbaum@logicpd.com>
References: <1275501284-17160-1-git-send-email-Jacob.Tanenbaum@logicpd.com>
Message-ID: <1275501284-17160-2-git-send-email-Jacob.Tanenbaum@logicpd.com>

                ARM: OMAP3LOGIC: Adding SDMMC support

                Add low-level initialization for hsmmc controller for
                LogicPD's OMAP 3530 LV SOM and OMAP 35x Torpedo board.

                Signed-off-by: Jacob Tanenbaum <Jacob.Tanenbaum at logicpd.com>
---
 arch/arm/mach-omap2/board-omap3logic.c |   69 +++++++++++++++++++++++++++++++-
 1 files changed, 68 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index fe5db85..13e0b16 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -33,13 +33,18 @@
 #include <asm/mach/map.h>
 
 #include "mux.h"
-
+#include "hsmmc.h"
 #include <plat/mux.h>
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/gpmc.h>
 #include <plat/timer-gp.h>
 
+#define OMAP3530_LV_SOM_MMC_GPIO_CD             110
+#define OMAP3530_LV_SOM_MMC_GPIO_WP             126
+#define OMAP3_TORPEDO_MMC_GPIO_CD               127
+#define OMAP3_TORPEDO_MMC_GPIO_WP               (-EINVAL)
+
 /* Micron MT46H32M32LF-6 */
 /* FIXME: borrowed from sdram-micron-mt46h32m32lf-6.h because on LogicPD
  * boards we can't use the default values -- why? I suspect the reason
@@ -80,6 +85,28 @@ static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
 	},
 };
 
+
+static struct regulator_consumer_supply omap3logic_vmmc1_supply = {
+	.supply         = "vmmc",
+};
+
+/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
+static struct regulator_init_data omap3logic_vmmc1 = {
+	.constraints = {
+		.name                   = "VMMC1",
+		.min_uV                 = 1850000,
+		.max_uV                 = 3150000,
+		.valid_modes_mask       = REGULATOR_MODE_NORMAL
+					| REGULATOR_MODE_STANDBY,
+		.valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+					| REGULATOR_CHANGE_MODE
+					| REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies  = 1,
+	.consumer_supplies      = &omap3logic_vmmc1_supply,
+};
+
+
 static int omap3logic_twl_gpio_setup(struct device *dev,
 				unsigned gpio, unsigned ngpio)
 {
@@ -121,6 +148,44 @@ static int __init omap3logic_i2c_init(void)
 	return 0;
 }
 
+
+static struct omap2_hsmmc_info __initdata board_mmc_info[] = {
+	{
+		.name           = "external",
+		.mmc            = 1,
+		.wires          = 4,
+		.gpio_cd        = -EINVAL,
+		.gpio_wp        = -EINVAL,
+	},
+	{}      /* Terminator */
+};
+
+static void __init board_mmc_init(void)
+{
+	/* OMAP3530 LV SOM board */
+	if (machine_is_omap3530_lv_som()) {
+		board_mmc_info[0].gpio_cd = OMAP3530_LV_SOM_MMC_GPIO_CD;
+		board_mmc_info[0].gpio_wp = OMAP3530_LV_SOM_MMC_GPIO_WP;
+		omap_mux_init_signal("gpio_110", OMAP_PIN_OUTPUT);
+		omap_mux_init_signal("gpio_126", OMAP_PIN_OUTPUT);
+
+
+	/* OMAP3 Torpedo board */
+	} else if (machine_is_omap3_torpedo()) {
+		board_mmc_info[0].gpio_cd = OMAP3_TORPEDO_MMC_GPIO_CD;
+		omap_mux_init_signal("gpio_127", OMAP_PIN_OUTPUT);
+	/* unsupported board */
+	} else {
+		printk(KERN_ERR "%s(): unknown machine type\n", __func__);
+	return;
+	}
+
+	omap2_hsmmc_init(board_mmc_info);
+	/* link regulators to MMC adapters */
+	omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev;
+}
+
+
 static struct omap_board_config_kernel omap3logic_config[] __initdata = {
 };
 
@@ -164,6 +229,7 @@ static void __init omap3logic_map_io(void)
 
 MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
 	/* Maintainer: Peter Barada <peterb at logicpd.com> */
+
 	.phys_io	= 0x48000000,
 	.io_pg_offst	= ((0xd8000000) >> 18) & 0xfffc,
 	.boot_params	= 0x80000100,
@@ -175,6 +241,7 @@ MACHINE_END
 
 MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
 	/* Maintainer: Peter Barada <peterb at logicpd.com> */
+
 	.phys_io	= 0x48000000,
 	.io_pg_offst	= ((0xd8000000) >> 18) & 0xfffc,
 	.boot_params	= 0x80000100,
-- 
1.6.0.4



From dkirjanov at hera.kernel.org  Wed Jun  2 15:27:04 2010
From: dkirjanov at hera.kernel.org (Denis Kirjanov)
Date: Wed, 2 Jun 2010 19:27:04 +0000
Subject: [PATCH] fec: convert legacy PM hooks to dem_pm_ops
Message-ID: <20100602192704.GA22726@hera.kernel.org>

This patch compile tested only.

Convert legacy PM hooks to dev_pm_ops
Signed-off-by: Denis Kirjanov <dkirjanov at kernel.org>
---
drivers/net/fec.c |   24 +++++++++++++++++++++---
 1 files changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index 42d9ac9..6990791 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1339,6 +1339,8 @@ fec_drv_remove(struct platform_device *pdev)
 	return 0;
 }
 
+#ifdef CONFIG_PM
+
 static int
 fec_suspend(struct platform_device *dev, pm_message_t state)
 {
@@ -1369,15 +1371,31 @@ fec_resume(struct platform_device *dev)
 	return 0;
 }
 
+static const struct dev_pm_ops fec_pm_ops = {
+	.suspend	= fec_suspend,
+	.resume		= fec_resume,
+	.freeze		= fec_suspend,
+	.thaw		= fec_resume,
+	.poweroff	= fec_suspend,
+	.restore	= fec_resume,
+};
+
+#define FEC_PM_OPS (&fec_pm_ops)
+
+#else /* !CONFIG_PM */
+
+#define FEC_PM_OPS NULL
+
+#endif /* !CONFIG_PM */
+
 static struct platform_driver fec_driver = {
 	.driver	= {
 		.name    = "fec",
 		.owner	 = THIS_MODULE,
+		.pm		 = FEC_PM_OPS,
 	},
 	.probe   = fec_probe,
 	.remove  = __devexit_p(fec_drv_remove),
-	.suspend = fec_suspend,
-	.resume  = fec_resume,
 };
 
 static int __init


From nico at fluxnic.net  Wed Jun  2 15:29:58 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 02 Jun 2010 15:29:58 -0400 (EDT)
Subject: [PATCH 3/3] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <AANLkTiltiNe5W0bRyEYIFJK0nB-Y4DDxHvBMHZntChdB@mail.gmail.com>
References: <1275404968-12258-1-git-send-email-saeed@marvell.com>
	<1275404968-12258-2-git-send-email-saeed@marvell.com>
	<1275404968-12258-3-git-send-email-saeed@marvell.com>
	<alpine.LFD.2.00.1006011447410.24526@xanadu.home>
	<AANLkTiltiNe5W0bRyEYIFJK0nB-Y4DDxHvBMHZntChdB@mail.gmail.com>
Message-ID: <alpine.LFD.2.00.1006021529040.24526@xanadu.home>

On Wed, 2 Jun 2010, saeed bishara wrote:

> > I think this looks like a bit too much code for what this does. ?To
> > simplify things, you could:
> >
> > 1) Duplicate kirkwood_pcie_setup() into kirkwood_pcie0_setup() and
> > ? kirkwood_pcie1_setup() instead. ?This will remove a couple
> > ? "if (pp->index == 0)" and the snprintf() which could remain
> > ? purely static initializations.
> >
> > 2) Remove bus_to_port() entirely, and store the address of the appropriate
> > ? struct pcie_port instance into the sysdata pointer of the pci_bus
> > ? structure. ?This struct pcie_port could even be kmalloc'd as needed.
> The sysdata already used by arm to store the pci_sys_data,

Ah, you're right.

> I think we will have to add a private pointer to the pci_sys_data 
> structure, that pointer will hold mach specific data per pci 
> controller. this pointer is needed for any platform that has multiple 
> pci controller. agree?

Yes.


Nicolas

From linus.walleij at stericsson.com  Wed Jun  2 15:37:13 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 2 Jun 2010 21:37:13 +0200
Subject: [PATCH] ARM: PL011 baudrate extension for ST-Ericssons derivative
Message-ID: <1275507433-32644-1-git-send-email-linus.walleij@stericsson.com>

Implementation of the ST-Ericsson baudrate extension in the PL011
block. In this modified variant it is possible to change the
sampling factor from 16 to 8, and thanks to this we can get higher
baudrates while still using the same peripheral clock.

Also replace the simple division to determine the baud divisor
with DIV_ROUND_CLOSEST() rather than a simple integer division.

Cc: Alessandro Rubini <rubini at unipv.it>
Cc: Jerzy Kasenberg <jerzy.kasenberg at tieto.com>
Signed-off-by: Marcin Mielczarczyk <marcin.mielczarczyk at tieto.com>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
Resending this not purely for the joy of seeing our whitespace
fixes, but for the fact that we also introduced DIV_ROUND_CLOSEST()
to calculate the divisor value.
---
 drivers/serial/amba-pl011.c |   27 +++++++++++++++++++++++++--
 include/linux/amba/serial.h |    1 +
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c
index 5644cf2..f67e09d 100644
--- a/drivers/serial/amba-pl011.c
+++ b/drivers/serial/amba-pl011.c
@@ -74,6 +74,7 @@ struct uart_amba_port {
 	unsigned int		ifls;		/* vendor-specific */
 	unsigned int		lcrh_tx;	/* vendor-specific */
 	unsigned int		lcrh_rx;	/* vendor-specific */
+	bool			oversampling;   /* vendor-specific */
 	bool			autorts;
 };
 
@@ -83,6 +84,7 @@ struct vendor_data {
 	unsigned int		fifosize;
 	unsigned int		lcrh_tx;
 	unsigned int		lcrh_rx;
+	bool			oversampling;
 };
 
 static struct vendor_data vendor_arm = {
@@ -90,6 +92,7 @@ static struct vendor_data vendor_arm = {
 	.fifosize		= 16,
 	.lcrh_tx		= UART011_LCRH,
 	.lcrh_rx		= UART011_LCRH,
+	.oversampling		= false,
 };
 
 static struct vendor_data vendor_st = {
@@ -97,6 +100,7 @@ static struct vendor_data vendor_st = {
 	.fifosize		= 64,
 	.lcrh_tx		= ST_UART011_LCRH_TX,
 	.lcrh_rx		= ST_UART011_LCRH_RX,
+	.oversampling		= true,
 };
 
 static void pl011_stop_tx(struct uart_port *port)
@@ -499,8 +503,13 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
 	/*
 	 * Ask the core to calculate the divisor for us.
 	 */
-	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
-	quot = port->uartclk * 4 / baud;
+	baud = uart_get_baud_rate(port, termios, old, 0,
+				  port->uartclk/(uap->oversampling ? 8 : 16));
+
+	if (baud > port->uartclk/16)
+		quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
+	else
+		quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
 
 	switch (termios->c_cflag & CSIZE) {
 	case CS5:
@@ -579,6 +588,13 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
 		uap->autorts = false;
 	}
 
+	if (uap->oversampling) {
+		if (baud > port->uartclk/16)
+			old_cr |= ST_UART011_CR_OVSFACT;
+		else
+			old_cr &= ~ST_UART011_CR_OVSFACT;
+	}
+
 	/* Set baud rate */
 	writew(quot & 0x3f, port->membase + UART011_FBRD);
 	writew(quot >> 6, port->membase + UART011_IBRD);
@@ -744,6 +760,12 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud,
 		fbrd = readw(uap->port.membase + UART011_FBRD);
 
 		*baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
+
+		if (uap->oversampling) {
+			if (readw(uap->port.membase + UART011_CR)
+				  & ST_UART011_CR_OVSFACT)
+				*baud *= 2;
+		}
 	}
 }
 
@@ -839,6 +861,7 @@ static int pl011_probe(struct amba_device *dev, struct amba_id *id)
 	uap->ifls = vendor->ifls;
 	uap->lcrh_rx = vendor->lcrh_rx;
 	uap->lcrh_tx = vendor->lcrh_tx;
+	uap->oversampling = vendor->oversampling;
 	uap->port.dev = &dev->dev;
 	uap->port.mapbase = dev->res.start;
 	uap->port.membase = base;
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h
index 93c96a6..e1b634b 100644
--- a/include/linux/amba/serial.h
+++ b/include/linux/amba/serial.h
@@ -86,6 +86,7 @@
 #define UART010_CR_TIE 		0x0020
 #define UART010_CR_RIE 		0x0010
 #define UART010_CR_MSIE		0x0008
+#define ST_UART011_CR_OVSFACT	0x0008	/* Oversampling factor */
 #define UART01x_CR_IIRLP	0x0004	/* SIR low power mode */
 #define UART01x_CR_SIREN	0x0002	/* SIR enable */
 #define UART01x_CR_UARTEN	0x0001	/* UART enable */
-- 
1.6.3.3



From robert.jarzmik at free.fr  Wed Jun  2 17:29:50 2010
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Wed,  2 Jun 2010 23:29:50 +0200
Subject: [PATCH] mioa701: fix camera regression
Message-ID: <1275514190-32006-1-git-send-email-robert.jarzmik@free.fr>

Since commit a48c24a696f0d93c49f913b7818e9819612b1f4e, the
camera is not working anymore.

After the v4l2 migration, the mt9m111 camera board
information was not passed to the i2c layer anymore, but
stored for future use of v4l2 (through soc_camera).

Because mioa701_i2c_devices[] was tagged as "__initdata",
and because after the v4l2 migration, the new structure
"iclink" references it, the mt9m111 driver is not probed
anymore, as part of "iclink" is not valid (discarded after
kernel init).

Although there is not compilation error, nor runtime oops,
this patch restores a working camera on the mioa701 board.

Signed-off-by: Robert Jarzmik <robert.jarzmik at free.fr>

--
Eric, could you schedule that into your fix branch please ?
---
 arch/arm/mach-pxa/mioa701.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 7a50ed8..9836921 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -696,7 +696,7 @@ static struct i2c_board_info __initdata mioa701_pi2c_devices[] = {
 };
 
 /* Board I2C devices. */
-static struct i2c_board_info __initdata mioa701_i2c_devices[] = {
+static struct i2c_board_info mioa701_i2c_devices[] = {
 	{
 		I2C_BOARD_INFO("mt9m111", 0x5d),
 	},
-- 
1.7.0.4



From joe at perches.com  Wed Jun  2 18:29:17 2010
From: joe at perches.com (Joe Perches)
Date: Wed, 02 Jun 2010 15:29:17 -0700
Subject: kirkwood: Iomega ix4-200d support?
Message-ID: <1275517757.23599.86.camel@Joe-Laptop.home>

It's also called the IX4-110.

Now that I have one, I'd like to add support for this board
in arch/arm/mach-kirkwood.

File layout has changed since EMC released their kernel 2.6.22.18
with support for this board.

I'm looking for suggestions on where to put the files for
the GPIO driven lcd module.  Should I just drop them into
arch/arm/mach-kirkwood or is there a better generic location?



From linus.ml.walleij at gmail.com  Wed Jun  2 18:33:57 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Thu, 3 Jun 2010 00:33:57 +0200
Subject: PB1176 broken in 2.6.35-rc1, bisected
Message-ID: <AANLkTikoCy2FH_5ICh-iiI_wzGj6D6oszyM-zCXkNC_4@mail.gmail.com>

Hi,

my PB1176 doesn't boot properly in 2.6.35-rc1, it goes to this point
and hangs:

(...)
Switching to clocksource timer3
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.


I bisected until I had this as the first commit causing the trouble:

commit ac1d426e825ab5778995f2f6f053ca2e6b45c622
Merge: fda0e18 a3685f0
Author: Russell King <rmk+kernel at arm.linux.org.uk>
Date:   Mon May 17 17:24:04 2010 +0100

    Merge branch 'devel-stable' into devel

    Conflicts:
        arch/arm/Kconfig
        arch/arm/include/asm/system.h
        arch/arm/mm/Kconfig


This doesn't say much so I suspect it's this latter one causing it:

commit fda0e18c8a7a3e02747c2b045b4fcd2c920410b9
Merge: 98830bc d1e86d6
Author: Russell King <rmk+kernel at arm.linux.org.uk>
Date:   Mon May 17 17:21:23 2010 +0100

    Merge branch 'devel-pmu' into devel


Any hints on how to fix this? Some PMU issue on this board
perhaps?

Yours,
Linus Walleij


From catalin.marinas at arm.com  Wed Jun  2 18:46:23 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 02 Jun 2010 23:46:23 +0100
Subject: PB1176 broken in 2.6.35-rc1, bisected
In-Reply-To: <AANLkTikoCy2FH_5ICh-iiI_wzGj6D6oszyM-zCXkNC_4@mail.gmail.com>
References: <AANLkTikoCy2FH_5ICh-iiI_wzGj6D6oszyM-zCXkNC_4@mail.gmail.com>
Message-ID: <1275518783.27834.2.camel@e102109-lin.cambridge.arm.com>

On Wed, 2010-06-02 at 23:33 +0100, Linus Walleij wrote:
> my PB1176 doesn't boot properly in 2.6.35-rc1, it goes to this point
> and hangs:
> 
> (...)
> Switching to clocksource timer3
> NET: Registered protocol family 2
> IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
> TCP established hash table entries: 4096 (order: 3, 32768 bytes)
> TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
> TCP: Hash tables configured (established 4096 bind 4096)
> TCP reno registered
> UDP hash table entries: 256 (order: 0, 4096 bytes)
> UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
> NET: Registered protocol family 1
> RPC: Registered udp transport module.
> RPC: Registered tcp transport module.
> RPC: Registered tcp NFSv4.1 backchannel transport module.

Have you tried disabling CONFIG_CACHE_L2X0?

-- 
Catalin



From linux at arm.linux.org.uk  Wed Jun  2 18:48:01 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 2 Jun 2010 23:48:01 +0100
Subject: PB1176 broken in 2.6.35-rc1, bisected
In-Reply-To: <AANLkTikoCy2FH_5ICh-iiI_wzGj6D6oszyM-zCXkNC_4@mail.gmail.com>
References: <AANLkTikoCy2FH_5ICh-iiI_wzGj6D6oszyM-zCXkNC_4@mail.gmail.com>
Message-ID: <20100602224801.GA12604@n2100.arm.linux.org.uk>

On Thu, Jun 03, 2010 at 12:33:57AM +0200, Linus Walleij wrote:
> I bisected until I had this as the first commit causing the trouble:
> 
> commit ac1d426e825ab5778995f2f6f053ca2e6b45c622
> Merge: fda0e18 a3685f0
> Author: Russell King <rmk+kernel at arm.linux.org.uk>
> Date:   Mon May 17 17:24:04 2010 +0100
> 
>     Merge branch 'devel-stable' into devel
> 
>     Conflicts:
>         arch/arm/Kconfig
>         arch/arm/include/asm/system.h
>         arch/arm/mm/Kconfig

You should be able to bisect further - did bisect just give up at this
point?

Do you know which half of that merge was also tested?


From linux at arm.linux.org.uk  Wed Jun  2 19:18:05 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 3 Jun 2010 00:18:05 +0100
Subject: [PATCH 1/2] Adding LogicPD OMAP 3530 LV SOM AND OMAP 35X
In-Reply-To: <1275501284-17160-1-git-send-email-Jacob.Tanenbaum@logicpd.com>
References: <1275501284-17160-1-git-send-email-Jacob.Tanenbaum@logicpd.com>
Message-ID: <20100602231805.GB12604@n2100.arm.linux.org.uk>

On Wed, Jun 02, 2010 at 01:54:43PM -0400, Jacob Tanenbaum wrote:
>         Adding LogicPD OMAP3 board support
> 
>         Adding support for LogicPD's OMAP 3530 LV SOM and
>         OMAP 35x Torpedo board.
> 
>         Signed-off-by: Jacob Tanenbaum <Jacob.Tanenbaum at logicpd.com>

I assume no OMAP folk have seen this?  It probably makes sense to
add Cc's for the linux-omap list and Tony Lindgren.

> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 2455dcc..f670faa 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -69,6 +69,14 @@ config MACH_OMAP_LDP
>  	depends on ARCH_OMAP3
>  	select OMAP_PACKAGE_CBB
>  
> +config MACH_OMAP3530_LV_SOM
> +        bool "OMAP3 Logic 3530 LV SOM board"
> +        depends on ARCH_OMAP3

Tabs, not spaces.

> +
> +config MACH_OMAP3_TORPEDO
> +        bool "OMAP3 Logic 35x Torpedo board"
> +        depends on ARCH_OMAP3
> +
>  config MACH_OVERO
>  	bool "Gumstix Overo board"
>  	depends on ARCH_OMAP3
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index 4b9fc57..77422be 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -109,6 +109,10 @@ obj-$(CONFIG_MACH_DEVKIT8000)     	+= board-devkit8000.o \
>                                             hsmmc.o
>  obj-$(CONFIG_MACH_OMAP_LDP)		+= board-ldp.o \
>  					   hsmmc.o
> +obj-$(CONFIG_MACH_OMAP3530_LV_SOM)      += board-omap3logic.o \
> +                                           hsmmc.o
> +obj-$(CONFIG_MACH_OMAP3_TORPEDO)        += board-omap3logic.o \
> +                                           hsmmc.o

Ditto.

>  obj-$(CONFIG_MACH_OVERO)		+= board-overo.o \
>  					   hsmmc.o
>  obj-$(CONFIG_MACH_OMAP3EVM)		+= board-omap3evm.o \
> diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
> new file mode 100644
> index 0000000..fe5db85
> --- /dev/null
> +++ b/arch/arm/mach-omap2/board-omap3logic.c
> @@ -0,0 +1,185 @@
> +/*
> + * linux/arch/arm/mach-omap2/board-omap3logic.c
> + *
> + * Copyright (C) 2010 Li-Pro.Net
> + * Stephan Linz <linz at li-pro.net>
> + *
> + * Copyright (C) 2010 Logic Product Development, Inc.
> + * Peter Barada <peter.barada at logicpd.com>
> + *
> + * Modified from Beagle, EVM, and RX51
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/platform_device.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/gpio.h>
> +
> +#include <linux/regulator/machine.h>
> +
> +#include<linux/i2c/twl.h>

Missing space.

> +
> +#include <mach/hardware.h>
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/map.h>
> +
> +#include "mux.h"
> +
> +#include <plat/mux.h>
> +#include <plat/board.h>
> +#include <plat/common.h>
> +#include <plat/gpmc.h>
> +#include <plat/timer-gp.h>
> +
> +/* Micron MT46H32M32LF-6 */
> +/* FIXME: borrowed from sdram-micron-mt46h32m32lf-6.h because on LogicPD
> + * boards we can't use the default values -- why? I suspect the reason
> + * lies in the boot strap code. We correct this part if we have ported
> + * U-Boot and X-Load. */
> +#include <plat/sdrc.h>

Blank line here please.

> +static struct omap_sdrc_params mt46h32m32lf6_sdrc_params[] = {
> +	[0] = {
> +		.rate	     = 166000000,
> +		.actim_ctrla = 0xaa9db4c6,
> +		.actim_ctrlb = 0x00011517,
> +		.rfr_ctrl    = 0x0004e201,
> +		.mr	     = 0x00000032,
> +	},
> +	[1] = {
> +		.rate	     = 165941176,
> +		.actim_ctrla = 0xaa9db4c6,
> +		.actim_ctrlb = 0x00011517,
> +		.rfr_ctrl    = 0x0004e201,
> +		.mr	     = 0x00000032,
> +	},
> +	[2] = {
> +		.rate	     = 83000000,
> +		.actim_ctrla = 0x8a99b481,
> +		.actim_ctrlb = 0x00011312,
> +		.rfr_ctrl    = 0x0003de01,
> +		.mr	     = 0x00000032,
> +	},
> +	[3] = {
> +		.rate	     = 82970588,
> +		.actim_ctrla = 0x8a99b481,
> +		.actim_ctrlb = 0x00011312,
> +		.rfr_ctrl    = 0x0003de01,
> +		.mr	     = 0x00000032,
> +	},
> +	[4] = {
> +		.rate	     = 0
> +	},
> +};
> +
> +static int omap3logic_twl_gpio_setup(struct device *dev,
> +				unsigned gpio, unsigned ngpio)
> +{
> +	return 0;
> +}
> +
> +static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
> +	.gpio_base	= OMAP_MAX_GPIO_LINES,
> +	.irq_base	= TWL4030_GPIO_IRQ_BASE,
> +	.irq_end	= TWL4030_GPIO_IRQ_END,
> +	.use_leds	= true,
> +	.pullups	= BIT(1),
> +	.pulldowns	= BIT(2)  | BIT(6)  | BIT(7)  | BIT(8)
> +			| BIT(13) | BIT(15) | BIT(16) | BIT(17),
> +	.setup		= omap3logic_twl_gpio_setup,
> +};
> +
> +static struct twl4030_platform_data omap3logic_twldata = {
> +	.irq_base	= TWL4030_IRQ_BASE,
> +	.irq_end	= TWL4030_IRQ_END,
> +
> +	/* platform_data for children goes here */
> +	.gpio		= &omap3logic_gpio_data,
> +};
> +
> +static struct i2c_board_info __initdata omap3logic_i2c_boardinfo[] = {
> +	{
> +		I2C_BOARD_INFO("twl4030", 0x48),
> +		.flags = I2C_CLIENT_WAKE,
> +		.irq = INT_34XX_SYS_NIRQ,
> +		.platform_data = &omap3logic_twldata,
> +	},
> +};
> +
> +static int __init omap3logic_i2c_init(void)
> +{
> +	omap_register_i2c_bus(1, 2600, omap3logic_i2c_boardinfo,
> +				ARRAY_SIZE(omap3logic_i2c_boardinfo));
> +	return 0;
> +}
> +
> +static struct omap_board_config_kernel omap3logic_config[] __initdata = {
> +};
> +
> +static void __init omap3logic_init_irq(void)
> +{
> +	omap_board_config = omap3logic_config;
> +	omap_board_config_size = ARRAY_SIZE(omap3logic_config);
> +	omap2_init_common_hw(mt46h32m32lf6_sdrc_params,
> +				mt46h32m32lf6_sdrc_params);
> +	omap_init_irq();
> +#ifdef CONFIG_OMAP_32K_TIMER
> +	omap2_gp_clockevent_set_gptimer(12);
> +#endif
> +	omap_gpio_init();
> +}
> +
> +static struct platform_device *omap3logic_devices[] __initdata = {
> +};

If there's no platform devices, don't supply this.

> +
> +static void __init omap3logic_init(void)
> +{
> +	omap3logic_i2c_init();
> +	platform_add_devices(omap3logic_devices,
> +				ARRAY_SIZE(omap3logic_devices));
> +	omap_serial_init();
> +
> +	/* Ensure SDRC pins are mux'd for self-refresh */
> +/*	omap_cfg_reg(H16_34XX_SDRC_CKE0);
> +	omap_cfg_reg(H17_34XX_SDRC_CKE1);
> +	omap_cfg_reg(SDRC_CKE0);
> +	omap_cfg_reg(SDRC_CKE1); */
> +	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
> +	omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
> +}
> +
> +static void __init omap3logic_map_io(void)
> +{
> +	omap2_set_globals_343x();
> +	omap34xx_map_common_io();
> +}
> +
> +MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
> +	/* Maintainer: Peter Barada <peterb at logicpd.com> */
> +	.phys_io	= 0x48000000,
> +	.io_pg_offst	= ((0xd8000000) >> 18) & 0xfffc,
> +	.boot_params	= 0x80000100,
> +	.map_io		= omap3logic_map_io,
> +	.init_irq	= omap3logic_init_irq,
> +	.init_machine	= omap3logic_init,
> +	.timer		= &omap_timer,
> +MACHINE_END
> +
> +MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
> +	/* Maintainer: Peter Barada <peterb at logicpd.com> */
> +	.phys_io	= 0x48000000,
> +	.io_pg_offst	= ((0xd8000000) >> 18) & 0xfffc,
> +	.boot_params	= 0x80000100,
> +	.map_io		= omap3logic_map_io,
> +	.init_irq	= omap3logic_init_irq,
> +	.init_machine	= omap3logic_init,
> +	.timer		= &omap_timer,
> +MACHINE_END

So, the kernel will recognise both of these boards at boot time, but
fail if the relevant board is not selected in the configuration
because if (machine_is_xxx()) will be false.

A better thing to do is to wrap these declarations in ifdefs so the
kernel can issue its standard message rather than mysteriously going
wrong.


From mroberto at cetuc.puc-rio.br  Wed Jun  2 19:19:01 2010
From: mroberto at cetuc.puc-rio.br (Marcelo Roberto Jimenez)
Date: Wed, 2 Jun 2010 20:19:01 -0300
Subject: Pull request for nanoengine
Message-ID: <AANLkTilh4NtHS5p3tWbMtIU9MBBC-Md13Aw9_RdL3Ogp@mail.gmail.com>

Hi,

The following is a compilation of all the patches I have done for the
nanoengine. Some of these are also valid for SA11xx based machines
like, e.g, sharp Zaurus.

These are just stable and tested patches, this does not include the
PCI patches. All of them have been previously submitted to LKML and
all critics have been included. The patches should be well commented,
in their changesets, but anyway here goes a quick summary:

1) ARM: mach-sa1100: Put nanoEngine support back in the kernel.
2) ARM: mach-sa1100: Add a defconfig for nanoEngine.
3) ARM: mach-sa1100: Fix for compiler warning of uninitialized variable.
4) ARM: mach-sa1100: Fix checkpatch.pl issues in
arch/arm/mach-sa1100/cpu-sa1100.c.
5) ARM: mach-sa1100: Fix checkpatch.pl issues in
arch/arm/mach-sa1100/cpu-sa1110.c.
6) ARM: mach-sa1100: Fix checkpatch.pl issues in drivers/rtc/rtc-sa1100.c.
7) ARM: mach-sa1100: Print the value of RTSR on /proc/drivers/rtc.
- Self explanatory/trivial patches.

8) ARM: mach-sa1100: Fix for a nasty initialization bug in the RTSR.
- Fixes a bug that could cause the system to hang.

9) ARM: mach-sa1100: Better use of the RTC framework for sa11xx.
- This patch uses the new RTC framework to treat some common ioctl.

10) ARM: pcmcia: Fix for building DEBUG with sa11xx_base.c as a module.
- The symbol soc_pcmcia_debug was not beeing exported.

11) ARM: pcmcia: Fix checkpatch.pl issues in drivers/pcmcia/soc_common.c
- Trivial.

12) ARM: pcmcia: Adds nanoEngine PCMCIA support.
- Adds nanoEngine PCMCIA support for two sockets.

Regards,
Marcelo.

--
The following changes since commit aef4b9aaae1decc775778903922bd0075cce7a88:

  Merge branch 'next' of
git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc (2010-06-01
14:13:14 -0700)

are available in the git repository at:

  git at github.com:mrjimenez/linux-2.6.git nanoengine

Marcelo Roberto Jimenez (12):
      ARM: mach-sa1100: Put nanoEngine support back in the kernel.
      ARM: mach-sa1100: Add a defconfig for nanoEngine.
      ARM: mach-sa1100: Fix for compiler warning of uninitialized variable.
      ARM: mach-sa1100: Fix checkpatch.pl issues in
arch/arm/mach-sa1100/cpu-sa1100.c.
      ARM: mach-sa1100: Fix checkpatch.pl issues in
arch/arm/mach-sa1100/cpu-sa1110.c.
      ARM: mach-sa1100: Fix checkpatch.pl issues in drivers/rtc/rtc-sa1100.c.
      ARM: mach-sa1100: Print the value of RTSR on /proc/drivers/rtc.
      ARM: mach-sa1100: Fix for a nasty initialization bug in the RTSR.
      ARM: mach-sa1100: Better use of the RTC framework for sa11xx.
      ARM: pcmcia: Fix for building DEBUG with sa11xx_base.c as a module.
      ARM: pcmcia: Fix checkpatch.pl issues in drivers/pcmcia/soc_common.c
      ARM: pcmcia: Adds nanoEngine PCMCIA support.

 arch/arm/configs/nanoengine_defconfig          | 1396 ++++++++++++++++++++++++
 arch/arm/mach-sa1100/Kconfig                   |    8 +
 arch/arm/mach-sa1100/Makefile                  |    2 +
 arch/arm/mach-sa1100/cpu-sa1100.c              |   56 +-
 arch/arm/mach-sa1100/cpu-sa1110.c              |   51 +-
 arch/arm/mach-sa1100/include/mach/nanoengine.h |   30 +
 arch/arm/mach-sa1100/nanoengine.c              |  115 ++
 drivers/pcmcia/Makefile                        |    3 +-
 drivers/pcmcia/sa1100_generic.c                |    3 +
 drivers/pcmcia/sa1100_generic.h                |    1 +
 drivers/pcmcia/sa1100_nanoengine.c             |  219 ++++
 drivers/pcmcia/soc_common.c                    |  129 ++-
 drivers/rtc/rtc-sa1100.c                       |  153 ++-
 13 files changed, 2021 insertions(+), 145 deletions(-)
 create mode 100644 arch/arm/configs/nanoengine_defconfig
 create mode 100644 arch/arm/mach-sa1100/include/mach/nanoengine.h
 create mode 100644 arch/arm/mach-sa1100/nanoengine.c
 create mode 100644 drivers/pcmcia/sa1100_nanoengine.c


From akpm at linux-foundation.org  Wed Jun  2 19:38:44 2010
From: akpm at linux-foundation.org (Andrew Morton)
Date: Wed, 2 Jun 2010 16:38:44 -0700
Subject: Pull request for nanoengine
In-Reply-To: <AANLkTilh4NtHS5p3tWbMtIU9MBBC-Md13Aw9_RdL3Ogp@mail.gmail.com>
References: <AANLkTilh4NtHS5p3tWbMtIU9MBBC-Md13Aw9_RdL3Ogp@mail.gmail.com>
Message-ID: <20100602163844.509e9953.akpm@linux-foundation.org>

On Wed, 2 Jun 2010 20:19:01 -0300
Marcelo Roberto Jimenez <mroberto at cetuc.puc-rio.br> wrote:

> The following is a compilation of all the patches I have done for the
> nanoengine. Some of these are also valid for SA11xx based machines
> like, e.g, sharp Zaurus.

Which other kernel developer were you hoping would merge this tree?

>  arch/arm/configs/nanoengine_defconfig          | 1396 ++++++++++++++++++++++++
>  arch/arm/mach-sa1100/Kconfig                   |    8 +
>  arch/arm/mach-sa1100/Makefile                  |    2 +
>  arch/arm/mach-sa1100/cpu-sa1100.c              |   56 +-
>  arch/arm/mach-sa1100/cpu-sa1110.c              |   51 +-
>  arch/arm/mach-sa1100/include/mach/nanoengine.h |   30 +
>  arch/arm/mach-sa1100/nanoengine.c              |  115 ++
>  drivers/pcmcia/Makefile                        |    3 +-
>  drivers/pcmcia/sa1100_generic.c                |    3 +
>  drivers/pcmcia/sa1100_generic.h                |    1 +
>  drivers/pcmcia/sa1100_nanoengine.c             |  219 ++++
>  drivers/pcmcia/soc_common.c                    |  129 ++-
>  drivers/rtc/rtc-sa1100.c                       |  153 ++-

I can only think it must have been Russell.

I've rather lost track of what's happening with ARM subtrees.  I
_think_ it's now the case the relevant maintainers are putting their
trees into linux-next directly and are asking Linus to pull them
directly.  But maybe that's a misconception.

Can someone please explain the current state of play?

Thanks.


From jason77.wang at gmail.com  Wed Jun  2 20:01:33 2010
From: jason77.wang at gmail.com (jason)
Date: Thu, 03 Jun 2010 08:01:33 +0800
Subject: [PATCH 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <20100602172334.GS26820@pengutronix.de>
References: <1275405043-18230-1-git-send-email-jason77.wang@gmail.com>
	<1275405043-18230-2-git-send-email-jason77.wang@gmail.com>
	<20100602073650.GK26820@pengutronix.de>
	<002e01cb025f$b3daf110$9b00a8c0@wuef10f27ebed8>
	<20100602172334.GS26820@pengutronix.de>
Message-ID: <4C06F0DD.4000005@gmail.com>

Sascha Hauer wrote:
> On Wed, Jun 02, 2010 at 10:27:03PM +0800, jason wang wrote:
>   
>>     
>>> Hi Jason,
>>>
>>> On Tue, Jun 01, 2010 at 11:10:41PM +0800, Jason Wang wrote:
>>>       
>>>> 3-stack is a reference board from Freescale for their i.MX51 SoC.
>>>>
>>>> Add board definition, Kconfig and Makefile to enable Freescale 3-stack
>>>> board.
>>>>         
>>> The debug board code looks the same like in mach-mx31_3ds.c. Does
>>> anybody know how similar the different debug boards for the 3ds boards
>>> are? ATM we only have the mx31_3ds with debug board support in the
>>> kernel. This could be the moment to go for a arch/arm/plat-mxc/3ds-debugboard.c
>>>
>>>       
>> Besides mx31_3ds and mx51_3ds, the mx31_ads and mx27_ads also have the similar CPLD expanding device.
>> They have similar functions but different CPLD image version. That is to say, except base_addr and parent_irq_pin,
>> the CPLD implemented device controller(like uart and interrupt controller) will be a little bit different.
>> I think the software for this part could be moved to a common file like plat-mxc/mxc-debugboard.c
>>
>> Because this is a big action, it will affect some exsiting platforms. How about leave this work to next
>> action?
>>
>> Thanks,
>> Jason.
>>     
>>> Several other comments inline.
>>>
>>>       
>> Except following 1 comment, all others will be addressed in V2.
>>
>> <snip>
>>     
>>>> Boot tested on a i.MX51 3-stack Rev2.0 board
>>>> + __raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
>>>> + __raw_writew(0, brd_io + INTR_RESET_REG);
>>>> + __raw_writew(0x1F, brd_io + INTR_MASK_REG);
>>>> + for (i = MXC_BOARD_IRQ_START;
>>>> +      i < (MXC_BOARD_IRQ_START + MXC_BOARD_IRQS); i++) {
>>>>         
>>> MXC_BOARD_IRQS is the maximum number of interrupts available for the
>>> board. What you need here instead is the number of interrupts the expio
>>> actually has.
>>>
>>>       
>> It seems MXC_BOARD_IRQS is the number of CPLD expanding irq(or debugboard expanding irq).
>>     
>
> Not exactly. See mach/irqs.h:
>
> /*
>  * The next 16 interrupts are for board specific purposes.  Since
>  * the kernel can only run on one machine at a time, we can re-use
>  * these.  If you need more, increase MXC_BOARD_IRQS, but keep it
>  * within sensible limits.
>  */
> #define MXC_BOARD_IRQ_START     (MXC_INTERNAL_IRQS + MXC_GPIO_IRQS)
>
> #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
> #define MXC_BOARD_IRQS  80
> #else
> #define MXC_BOARD_IRQS  16
> #endif
>
>
> Remember that we can compile the kernel for more than one board at a
> time. So if MACH_MX31ADS_WM1133_EV1 is compiled in we will have 60 board
> irqs. Ok, you will hardly compile a kernel for mx31ads and mx51, but
> there could well come a mx51 board with more irqs in which case your
> expio handler goes nuts.
>
> Sascha
>
>
>   
OK, clear, thanks for your explanation.

Thanks,
Jason.



From marek.vasut at gmail.com  Wed Jun  2 20:01:13 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 3 Jun 2010 02:01:13 +0200
Subject: [URGENT] Re: bit errors on spitz + voipac
In-Reply-To: <20100308121634.GA14904@atrey.karlin.mff.cuni.cz>
References: <20100305212708.GC21773@elf.ucw.cz>
	<1268048916.6477.9.camel@utx.utx.cz>
	<20100308121634.GA14904@atrey.karlin.mff.cuni.cz>
Message-ID: <201006030201.13341.marek.vasut@gmail.com>

Dne Po 8. b?ezna 2010 13:16:35 Cyril Hrubis napsal(a):
> Hi!
> 
> > - And I see display noise while CF Wi-Fi card is active.
> 
> Forgotten about this one. See for yourself, notice short black vertical
> lines flashing randomly.
> 
> http://atrey.karlin.mff.cuni.cz/~metan/outgoing/zaurus_sickness.mpg

This is not only case of spitz. I've seen LCD image falling apart on pxafb on 
Voipac PXA270 board. The image was like "torn in half and part of it was moved 
to right, the hole between staying white".

This happened exactly when I started doing a DMA transfer from a harddrive 
attached through pata_pxa. It's perfectly replicable. If I disabled DMA and let 
it run only in PIO, the image was fine.

I assume the corruption Pavel was seeing is related. My guess is the problems 
are caused when DMA between the CPU and a companion chip happens. I dunno if the 
DMA controller doesn't have enough power to supply LCD and the companion chip 
with data, but that's one of my guesses.

btw. Adjusting the DMA descriptor length in pata_pxa didn't help.

Guys, we need to investigate this as it seems to cause problems on many places.

Cheers!


From kgene.kim at samsung.com  Wed Jun  2 20:25:24 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 03 Jun 2010 09:25:24 +0900
Subject: [PATCH 4/4] pata_samsung: Add Samsung PATA controller driver
In-Reply-To: <4C0629B7.4060300@ru.mvista.com>
References: <1274948524-2970-1-git-send-email-kgene.kim@samsung.com>
	<1274948524-2970-5-git-send-email-kgene.kim@samsung.com>
	<4BFE46C4.5030007@mvista.com>
	<002a01cb01fd$4cf10a50$e6d31ef0$%kim@samsung.com>
	<4C0629B7.4060300@ru.mvista.com>
Message-ID: <002101cb02b3$44d40be0$ce7c23a0$%kim@samsung.com>

Sergei Shtylyov wrote:
> 
> Hello.

Hi ;-)

> Kukjin Kim wrote:
> 
> >>> From: Abhilash Kesavan <a.kesavan at samsung.com>
> >>> Adds support for the Samsung PATA controller. This driver is based on
the
> >>> Libata subsystem and references the earlier patches sent for IDE
subsystem.
> 
>     Where I those I wonder? :-)
>     It's a pity they didn't get accepted.
> 
Was told that that only new libata based drivers would be accepted.

> >>> Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> >>> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> 
> [...]
> 
> >>> +		for (i = 0; i < words; i++, temp_addr++) {
> >>> +			wait_for_host_ready(info);
> >>> +			writel(*temp_addr, data_addr);
> >>> +		}
> >>> +	}
> 
> >>     Well, if this is pere CF case, 'buflen' can't be odd, but otherwise
> 
>     I meant to type "pure". :-)
> 
considering CF in true-ide mode..should I still add the check?

> >> you should handle that case...
> 
> >>> +	uint pio_teoc[5] = { 240, 43, 10, 70, 25 };
> 
> >>     What timing is this? :-O
> 
> > Should have been t2i rec.
> 
>     If it's t2i timing, it is incorrect for the first 3 PIO modes.
> 
Should have been (240, 93, 40, 70, 25)

> >>> +	if (cpu_type == TYPE_S3C6400) {
> >>> +		ap->ops = &pata_s3c_port_ops;
> >>> +		info->sfr_addr = info->ide_addr + 0x1800;
> >>> +		info->ide_addr = info->ide_addr + 0x1900;
> >>> +		info->fifo_status_reg = 0x94;
> >>> +	} else if (cpu_type == TYPE_S5PC100) {
> >>> +		ap->ops = &pata_s5p_port_ops;
> >>> +		info->sfr_addr = info->ide_addr + 0x1800;
> >>> +		info->ide_addr = info->ide_addr + 0x1900;
> 
> >>     Does make sense to assign those before *if*.
> 
> > Offsets not required for S5PV210/S5PC110.
> 
>     pata_s3c_tune_chipset() certainly requires them.
> 
yes..but for V210/C110 just the ioremapped info->ide_addr with 0 offset is
enough.

> >>> +		info->fifo_status_reg = 0x84;
> >>> +	} else {
> >>> +		ap->ops = &pata_s5p_port_ops;
> 
> >>     You don't assign 'info->ide_addr' here but you'll need it in
> >> pata_s3c_tune_chipset() which will be called thru pata_s5p_port_ops!
> 
> > The address received at ioremap() is enough for S5PV210/S5PC110..no
offset
> > needed.
> 
>     I only have to restate that pata_s3c_tune_chipset() does use
> 'info->ide_addr'. Maybe you shouldn't install this method for
S5PV210/S5PC110?
> Or do you mean thgat offset of 0 will work?
> 
V210/C110 requires 0 offset as compared to 6410 and C100 which require
0x1800.

> >>> +release_mem:
> >>> +	release_mem_region(res->start, res->end - res->start + 1);
> 
> >>     But you didn't call request_mem_region()!
> 
> > I didn't..will remove.
> 
>     But you should call request_mem_region() in one or another form...
> 
OK..will request mem_region() before ioremap()..and then the release_mem's
should be fine.


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From ben-linux at fluff.org  Wed Jun  2 20:25:27 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Thu, 3 Jun 2010 01:25:27 +0100
Subject: [TEMP PATCH] Re: make ARM=arm menuconfig problem in mainline
In-Reply-To: <4C068BAA.4030004@oracle.com>
References: <AANLkTikC61Y9g-WbqwgGDghDSy2XtgraFSRoZYkHRGTG@mail.gmail.com>
	<AANLkTilEYHVHJrj_KgF48OYCSEUcsKLi57Q_Y73d9va-@mail.gmail.com>
	<20100602085748.6771e025.randy.dunlap@oracle.com>
	<AANLkTilpzeYVExQfLgpVmS3bPvb_h3kmWaatidekI-0r@mail.gmail.com>
	<4C068BAA.4030004@oracle.com>
Message-ID: <20100603002526.GV4720@trinity.fluff.org>

On Wed, Jun 02, 2010 at 09:49:46AM -0700, Randy Dunlap wrote:
> On 06/02/10 09:08, Nobin Mathew wrote:
> > 
> > On Wed, Jun 2, 2010 at 9:27 PM, Randy Dunlap <randy.dunlap at oracle.com> wrote:
> >> On Wed, 2 Jun 2010 20:04:28 +0530 Nobin Mathew wrote:
> >>
> >>> adding linux-arm-kernel at lists.infradead.org
> >>>
> >>> Hi,
> >>>
> >>> The following entry creates problem in ARM System type menu. I am
> >>> using a Fedora 12 system.
> >>
> >> What kind of problem does it create?
> >> It seems to work for me (on f11, not f12).
> >> Does it have something to do with F12 specifically?
> >>
> >>
> >>> Length of bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
> >>> S3C2442, S3C2443, S3C2450" is the problem. How can I fix it.
> >>
> >> Describe the problem, please.
> 
> [please don't top-post]


I can think of several solutions, the first being to remove the S3C prefix
friom all these.

S3C24XX is not acceptable, there's S3C series that are either too old to
be bothered with, or don't fit under this architecture.

how about Samsung S3C: 2410,2412/3,2416,2440/2442,2443,2450

 
> > Sorry if attachments are not allowed, when I go to select ARM system
> > type(OMAP, Davinci etc), I am not seeing any entries there in the pop
> > up window. When I remove  bool "Samsung S3C2410, S3C2412, S3C2413,
> > S3C2416, S3C2440,
> >>> S3C2442, S3C2443, S3C2450"  it is working fine. I feel it is something to do with length of that string.
> > 
> > Thanks
> > Nobin
> 
> 
> OK, I see that now.  Well, it is some kind of problem.
> Adding cc to linux-kbuild mailing list.
> 
> 
> The patch below fixes the problem temporarily, but the bool string length does
> seem to be a problem.
> 
> Thanks for your report.
> 
> -- 
> From: Randy Dunlap <randy.dunlap at oracle.com>
> 
> The bool "long string" causes the choices not to be displayed,
> so temporarily change it to a shorter string until a real fix
> is found.
> 
> Signed-off-by: Randy Dunlap <randy.dunlap at oracle.com>
> Reported-by: Nobin Mathew <nobin.mathew at gmail.com>
> Cc: Ben Dooks <ben-linux at fluff.org>
> ---
>  arch/arm/Kconfig |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> --- linux-next-20100602.orig/arch/arm/Kconfig
> +++ linux-next-20100602/arch/arm/Kconfig
> @@ -629,7 +629,7 @@ config ARCH_SA1100
>  	  Support for StrongARM 11x0 based boards.
>  
>  config ARCH_S3C2410
> -	bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
> +	bool "Samsung S3C24xx"
>  	select GENERIC_GPIO
>  	select ARCH_HAS_CPUFREQ
>  	select HAVE_CLK

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From ben-linux at fluff.org  Wed Jun  2 20:49:05 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Thu, 3 Jun 2010 01:49:05 +0100
Subject: [PATCH] ARM: SAMSUNG: Make WDT driver dependency SoC specific
	instead of machine specific
In-Reply-To: <1275462611-21657-1-git-send-email-kgene.kim@samsung.com>
References: <1275462611-21657-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <20100603004905.GE30276@trinity.fluff.org>

On Wed, Jun 02, 2010 at 04:10:11PM +0900, Kukjin Kim wrote:
> From: Banajit Goswami <banajit.g at samsung.com>
> 
> This patch moves the dependency of watchdog timer driver from
> MACH_XXX(board) to ARCH_XXX(SoC). This will enable all machines
> using Samsung S3C64XX, S5P6440 and S5PV210/S5PC110 SoCs to use
> the WDT driver by default.
> 
> Signed-off-by: Banajit Goswami <banajit.g at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
>  arch/arm/Kconfig              |    3 +++

you'll be better off changing the arch/arm/mach-xxx/Kconfig files to avoid
having to change arch/arm/Kconfig and thus make the merge dependant on
Russell.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From ben-linux at fluff.org  Wed Jun  2 21:00:25 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Thu, 3 Jun 2010 02:00:25 +0100
Subject: [PATCH v2 5/5] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <4C01EB2E.4020600@samsung.com>
References: <1275188784-23395-1-git-send-email-jy0922.shim@samsung.com>
	<1275188784-23395-5-git-send-email-jy0922.shim@samsung.com>
	<20100530034250.GK7248@trinity.fluff.org>
	<4C01EB2E.4020600@samsung.com>
Message-ID: <20100603010025.GA14272@trinity.fluff.org>

On Sun, May 30, 2010 at 01:35:58PM +0900, Joonyoung Shim wrote:

> >> +static void samsung_kp_timer(unsigned long data)
> >> +{
> >> +	struct samsung_kp *keypad = (struct samsung_kp *)data;
> >> +
> >> +	schedule_work(&keypad->work);

would schedule_delayed_work() avoid the need for a timer here?


> >> +	keypad = kzalloc(sizeof(*keypad), GFP_KERNEL);
> >> +	keycodes = kzalloc((pdata->rows << row_shift) * sizeof(*keycodes),
> >> +			GFP_KERNEL);
> > 
> > you could allocate this in one go.
> > 
> 
> Hmm, how i do it? Do you mean to allocate keypad and keycodes together?

There's a couple of ways to do this, they may of course be not the nicest
ways.

make the last entry of the first (know size) structure a unsized array.
as so:

   struct a {
   	  ...
	  struct b t[];
   }

then do
     struct a *my_a;
     my_a = kzalloc(sizeof(struct a ) + sizeof(struct b) * nr_b);

or by incrementing the pointer:
	struct a *my_a;
	struct b *my_b;

	my_a = kzalloc(sizeof(struct a ) + sizeof(struct b) * nr_b);
	my_b = (struct b *)(my_a + 1);
     
> >> +	keypad->clk = clk_get(&pdev->dev, "keypad");

I'm going to get rid of this practice, it should be clk_get(&pdev->dev, NULL),
see up-comming clock changes.


> >> +	ret = request_irq(keypad->irq, samsung_kp_interrupt, 0,
> >> +			dev_name(&pdev->dev), keypad);
> >> +
> >> +	if (ret)
NO PRINT HERE?

> >> +		goto err_disable_clk;
> >> +
> >> +	input_dev->name = pdev->name;
> >> +	input_dev->id.bustype = BUS_HOST;
> >> +	input_dev->dev.parent = &pdev->dev;
> >> +
> >> +	input_dev->evbit[0] = BIT_MASK(EV_KEY);
> >> +	if (pdata->rep)
> >> +		input_dev->evbit[0] |= BIT_MASK(EV_REP);
> >> +
> >> +	input_dev->keycode = keycodes;
> >> +	input_dev->keycodesize = sizeof(*keycodes);
> >> +	input_dev->keycodemax = pdata->rows << row_shift;
> >> +
> >> +	matrix_keypad_build_keymap(keymap_data, row_shift,
> >> +			input_dev->keycode, input_dev->keybit);
> >> +
> >> +	ret = input_register_device(keypad->input_dev);
> >> +	if (ret)
> >> +		goto err_free_irq;
> >> +
> >> +	platform_set_drvdata(pdev, keypad);
> >> +	clk_disable(keypad->clk);
> >> +
> >> +	return 0;
> >> +
> >> +err_free_irq:
> >> +	free_irq(keypad->irq, keypad);
> >> +err_disable_clk:
> >> +	clk_disable(keypad->clk);
> >> +	clk_put(keypad->clk);
> >> +err_unmap_base:
> >> +	iounmap(keypad->base);
> >> +err_free_mem:
> >> +	input_free_device(input_dev);
> >> +	kfree(keycodes);
> >> +	kfree(keypad);
> >> +
> >> +	return ret;
> >> +}
> >> +
> >> +static int __devexit samsung_kp_remove(struct platform_device *pdev)
> >> +{
> >> +	struct samsung_kp *keypad = platform_get_drvdata(pdev);
> >> +
> >> +	free_irq(keypad->irq, keypad);
> >> +	cancel_work_sync(&keypad->work);
> >> +	del_timer_sync(&keypad->timer);
> >> +
> >> +	platform_set_drvdata(pdev, NULL);
> >> +	input_unregister_device(keypad->input_dev);
> >> +
> >> +	clk_disable(keypad->clk);
> >> +	clk_put(keypad->clk);
> >> +
> >> +	iounmap(keypad->base);
> >> +	kfree(keypad->keycodes);
> >> +	kfree(keypad);
> >> +
> >> +	return 0;
> >> +}
> >> +
> >> +#ifdef CONFIG_PM
> >> +static int samsung_kp_suspend(struct device *dev)
> >> +{
> >> +	struct platform_device *pdev = to_platform_device(dev);
> >> +	struct samsung_kp *keypad = platform_get_drvdata(pdev);
> >> +
> >> +	disable_irq(keypad->irq);
> >> +
> >> +	return 0;
> >> +}
> >> +
> >> +static int samsung_kp_resume(struct device pdev)
> >> +{
> >> +	struct platform_device *pdev = to_platform_device(dev);
> >> +	struct samsung_kp *keypad = platform_get_drvdata(pdev);
> >> +	unsigned int val;
> >> +
> >> +	clk_enable(keypad->clk);
> >> +
> >> +	/* enable interrupt and wakeup bit */
> >> +	val = SAMSUNG_INT_F_EN | SAMSUNG_INT_R_EN | SAMSUNG_WAKEUPEN;
> >> +	writel(val, keypad->base + SAMSUNG_KEYIFCON);
> >> +
> >> +	/* KEYIFCOL reg clear */
> >> +	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
> >> +
> >> +	enable_irq(keypad->irq);
> >> +	clk_disable(keypad->clk);
> >> +
> >> +	return 0;
> >> +}
> >> +
> >> +static const struct dev_pm_ops samsung_kp_pm_ops = {
> >> +	.suspend	= samsung_kp_suspend,
> >> +	.resume		= samsung_kp_resume,
> >> +};
> >> +#endif
> >> +
> >> +static struct platform_driver samsung_kp_driver = {
> >> +	.probe		= samsung_kp_probe,
> >> +	.remove		= __devexit_p(samsung_kp_remove),
> >> +	.driver		= {
> >> +		.name	= "samsung-keypad",
> >> +		.owner	= THIS_MODULE,
> >> +#ifdef CONFIG_PM
> >> +		.pm	= &samsung_kp_pm_ops,
> >> +#endif
> >> +	},
> >> +};
> >> +
> >> +static int __init samsung_kp_init(void)
> >> +{
> >> +	return platform_driver_register(&samsung_kp_driver);
> >> +}
> >> +
> >> +static void __exit samsung_kp_exit(void)
> >> +{
> >> +	platform_driver_unregister(&samsung_kp_driver);
> >> +}
> >> +
> >> +module_init(samsung_kp_init);
> >> +module_exit(samsung_kp_exit);
> >> +
> >> +MODULE_DESCRIPTION("Samsung keypad driver");
> >> +MODULE_AUTHOR("Joonyoung Shim <jy0922.shim at samsung.com>");
> >> +MODULE_AUTHOR("Donghwa Lee <dh09.lee at samsung.com>");
> >> +MODULE_LICENSE("GPL");

You missed MODULE_ALIAS() for your platform device name

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From randy.dunlap at oracle.com  Wed Jun  2 21:12:26 2010
From: randy.dunlap at oracle.com (Randy Dunlap)
Date: Wed, 02 Jun 2010 18:12:26 -0700
Subject: [TEMP PATCH v2] Re: make ARM=arm menuconfig problem in mainline
In-Reply-To: <20100603002526.GV4720@trinity.fluff.org>
References: <AANLkTikC61Y9g-WbqwgGDghDSy2XtgraFSRoZYkHRGTG@mail.gmail.com>
	<AANLkTilEYHVHJrj_KgF48OYCSEUcsKLi57Q_Y73d9va-@mail.gmail.com>
	<20100602085748.6771e025.randy.dunlap@oracle.com>
	<AANLkTilpzeYVExQfLgpVmS3bPvb_h3kmWaatidekI-0r@mail.gmail.com>
	<4C068BAA.4030004@oracle.com>
	<20100603002526.GV4720@trinity.fluff.org>
Message-ID: <4C07017A.50007@oracle.com>

On 06/02/10 17:25, Ben Dooks wrote:
> On Wed, Jun 02, 2010 at 09:49:46AM -0700, Randy Dunlap wrote:
>> On 06/02/10 09:08, Nobin Mathew wrote:
>>>
>>> On Wed, Jun 2, 2010 at 9:27 PM, Randy Dunlap <randy.dunlap at oracle.com> wrote:
>>>> On Wed, 2 Jun 2010 20:04:28 +0530 Nobin Mathew wrote:
>>>>
>>>>> adding linux-arm-kernel at lists.infradead.org
>>>>>
>>>>> Hi,
>>>>>
>>>>> The following entry creates problem in ARM System type menu. I am
>>>>> using a Fedora 12 system.
>>>>
>>>> What kind of problem does it create?
>>>> It seems to work for me (on f11, not f12).
>>>> Does it have something to do with F12 specifically?
>>>>
>>>>
>>>>> Length of bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
>>>>> S3C2442, S3C2443, S3C2450" is the problem. How can I fix it.
>>>>
>>>> Describe the problem, please.
>>
>> [please don't top-post]
> 
> 
> I can think of several solutions, the first being to remove the S3C prefix
> friom all these.
> 
> S3C24XX is not acceptable, there's S3C series that are either too old to
> be bothered with, or don't fit under this architecture.

and not in the current kernel tree?
I did not find any others in the current tree....

> how about Samsung S3C: 2410,2412/3,2416,2440/2442,2443,2450

OK, that works.

For kbuild/kconfig people:  run:
make ARCH=arm O=test menuconfig

and then select System Type & ARM system type.  The kconfig "choice" menu at this
point looks empty.  It seems to be just a text windowing/display problem.
Pressing the down/up arrow keys will display the choices, although not where they
should be displayed in the rectangle, and they can be selected there.


>>> Sorry if attachments are not allowed, when I go to select ARM system
>>> type(OMAP, Davinci etc), I am not seeing any entries there in the pop
>>> up window. When I remove  bool "Samsung S3C2410, S3C2412, S3C2413,
>>> S3C2416, S3C2440,
>>>>> S3C2442, S3C2443, S3C2450"  it is working fine. I feel it is something to do with length of that string.
>>>
>>> Thanks
>>> Nobin
>>
>>
>> OK, I see that now.  Well, it is some kind of problem.
>> Adding cc to linux-kbuild mailing list.
>>
>>
>> The patch below fixes the problem temporarily, but the bool string length does
>> seem to be a problem.
>>
>> Thanks for your report.


---
From: Randy Dunlap <randy.dunlap at oracle.com>

"bool <long string>" causes kconfig choices not to be displayed
correctly, so temporarily change it to a shorter string until a real
fix is found.

Signed-off-by: Randy Dunlap <randy.dunlap at oracle.com>
Reported-by: Nobin Mathew <nobin.mathew at gmail.com>
Cc: Ben Dooks <ben-linux at fluff.org>
---
 arch/arm/Kconfig |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- linux-next-20100602.orig/arch/arm/Kconfig
+++ linux-next-20100602/arch/arm/Kconfig
@@ -629,7 +629,7 @@ config ARCH_SA1100
 	  Support for StrongARM 11x0 based boards.
 
 config ARCH_S3C2410
-	bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
+	bool "Samsung S3C: 2410,2412/3,2416,2440/2442,2443,2450"
 	select GENERIC_GPIO
 	select ARCH_HAS_CPUFREQ
 	select HAVE_CLK


From randy.dunlap at oracle.com  Wed Jun  2 21:22:01 2010
From: randy.dunlap at oracle.com (Randy Dunlap)
Date: Wed, 2 Jun 2010 18:22:01 -0700
Subject: Pull request for nanoengine
In-Reply-To: <20100602163844.509e9953.akpm@linux-foundation.org>
References: <AANLkTilh4NtHS5p3tWbMtIU9MBBC-Md13Aw9_RdL3Ogp@mail.gmail.com>
	<20100602163844.509e9953.akpm@linux-foundation.org>
Message-ID: <20100602182201.4fcb3417.randy.dunlap@oracle.com>

On Wed, 2 Jun 2010 16:38:44 -0700 Andrew Morton wrote:

> On Wed, 2 Jun 2010 20:19:01 -0300
> Marcelo Roberto Jimenez <mroberto at cetuc.puc-rio.br> wrote:
> 
> > The following is a compilation of all the patches I have done for the
> > nanoengine. Some of these are also valid for SA11xx based machines
> > like, e.g, sharp Zaurus.
> 
> Which other kernel developer were you hoping would merge this tree?
> 
> >  arch/arm/configs/nanoengine_defconfig          | 1396 ++++++++++++++++++++++++
> >  arch/arm/mach-sa1100/Kconfig                   |    8 +
> >  arch/arm/mach-sa1100/Makefile                  |    2 +
> >  arch/arm/mach-sa1100/cpu-sa1100.c              |   56 +-
> >  arch/arm/mach-sa1100/cpu-sa1110.c              |   51 +-
> >  arch/arm/mach-sa1100/include/mach/nanoengine.h |   30 +
> >  arch/arm/mach-sa1100/nanoengine.c              |  115 ++
> >  drivers/pcmcia/Makefile                        |    3 +-
> >  drivers/pcmcia/sa1100_generic.c                |    3 +
> >  drivers/pcmcia/sa1100_generic.h                |    1 +
> >  drivers/pcmcia/sa1100_nanoengine.c             |  219 ++++
> >  drivers/pcmcia/soc_common.c                    |  129 ++-
> >  drivers/rtc/rtc-sa1100.c                       |  153 ++-
> 
> I can only think it must have been Russell.
> 
> I've rather lost track of what's happening with ARM subtrees.  I
> _think_ it's now the case the relevant maintainers are putting their
> trees into linux-next directly and are asking Linus to pull them
> directly.  But maybe that's a misconception.
> 
> Can someone please explain the current state of play?


Check this from about 2 hours before your question:
  http://lkml.org/lkml/2010/6/2/472  (Linus)


---
~Randy
*** Remember to use Documentation/SubmitChecklist when testing your code ***


From marek.vasut at gmail.com  Wed Jun  2 21:44:00 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu,  3 Jun 2010 03:44:00 +0200
Subject: [PATCH] pxa/z2: Fix includes in battery driver
Message-ID: <1275529440-31121-1-git-send-email-marek.vasut@gmail.com>

Remove redundant includes and add slab.h to fix problem with building.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/power/z2_battery.c |   12 +++---------
 1 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/drivers/power/z2_battery.c b/drivers/power/z2_battery.c
index 9cca465..85064a9 100644
--- a/drivers/power/z2_battery.c
+++ b/drivers/power/z2_battery.c
@@ -9,19 +9,13 @@
  *
  */
 
-#include <linux/init.h>
-#include <linux/kernel.h>
 #include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/power_supply.h>
-#include <linux/i2c.h>
-#include <linux/spinlock.h>
-#include <linux/interrupt.h>
 #include <linux/gpio.h>
+#include <linux/i2c.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
-#include <asm/irq.h>
-#include <asm/mach/irq.h>
+#include <linux/power_supply.h>
+#include <linux/slab.h>
 #include <linux/z2_battery.h>
 
 #define	Z2_DEFAULT_NAME	"Z2"
-- 
1.7.0



From marek.vasut at gmail.com  Wed Jun  2 21:50:10 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu,  3 Jun 2010 03:50:10 +0200
Subject: [PATCH] pxa/z2: Fix flash layout to final version
Message-ID: <1275529810-589-1-git-send-email-marek.vasut@gmail.com>

This patch fixes flash layout to it's final version. Also, I fixed the
authorship information of this file as it's been totally reworked since Ken
released his last version.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/z2.c |   26 ++++++++++----------------
 1 files changed, 10 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index 4cba5b6..967e8cb 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -3,8 +3,9 @@
  *
  *  Support for the Zipit Z2 Handheld device.
  *
- *  Author: 	Ken McGuire
- *  Created:	Jan 25, 2009
+ *  Copyright (C) 2009-2010 Marek Vasut <marek.vasut at gmail.com>
+ *
+ *  Based on research and code by: Ken McGuire
  *  Based on mainstone.c as modified for the Zipit Z2.
  *
  *  This program is free software; you can redistribute it and/or modify
@@ -158,21 +159,14 @@ static struct mtd_partition z2_flash_parts[] = {
 	{
 		.name	= "U-Boot Bootloader",
 		.offset	= 0x0,
-		.size	= 0x20000,
-	},
-	{
-		.name	= "Linux Kernel",
-		.offset	= 0x20000,
-		.size	= 0x220000,
-	},
-	{
-		.name	= "Filesystem",
-		.offset	= 0x240000,
-		.size	= 0x5b0000,
-	},
-	{
+		.size	= 0x40000,
+	}, {
 		.name	= "U-Boot Environment",
-		.offset	= 0x7f0000,
+		.offset	= 0x40000,
+		.size	= 0x60000,
+	}, {
+		.name	= "Flash",
+		.offset	= 0x60000,
 		.size	= MTDPART_SIZ_FULL,
 	},
 };
-- 
1.7.0



From eric.y.miao at gmail.com  Wed Jun  2 22:30:06 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Thu, 3 Jun 2010 10:30:06 +0800
Subject: [URGENT] Re: bit errors on spitz + voipac
In-Reply-To: <201006030201.13341.marek.vasut@gmail.com>
References: <20100305212708.GC21773@elf.ucw.cz>
	<1268048916.6477.9.camel@utx.utx.cz> 
	<20100308121634.GA14904@atrey.karlin.mff.cuni.cz>
	<201006030201.13341.marek.vasut@gmail.com>
Message-ID: <AANLkTikSotOdWIKqPpNi100rsVraIxZp6yZplIvaSo9m@mail.gmail.com>

On Thu, Jun 3, 2010 at 8:01 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dne Po 8. b?ezna 2010 13:16:35 Cyril Hrubis napsal(a):
>> Hi!
>>
>> > - And I see display noise while CF Wi-Fi card is active.
>>
>> Forgotten about this one. See for yourself, notice short black vertical
>> lines flashing randomly.
>>
>> http://atrey.karlin.mff.cuni.cz/~metan/outgoing/zaurus_sickness.mpg
>
> This is not only case of spitz. I've seen LCD image falling apart on pxafb on
> Voipac PXA270 board. The image was like "torn in half and part of it was moved
> to right, the hole between staying white".
>
> This happened exactly when I started doing a DMA transfer from a harddrive
> attached through pata_pxa. It's perfectly replicable. If I disabled DMA and let
> it run only in PIO, the image was fine.
>
> I assume the corruption Pavel was seeing is related. My guess is the problems
> are caused when DMA between the CPU and a companion chip happens. I dunno if the
> DMA controller doesn't have enough power to supply LCD and the companion chip
> with data, but that's one of my guesses.
>
> btw. Adjusting the DMA descriptor length in pata_pxa didn't help.
>

If there is a FIFO attached, may need the FIFO status when the error happens.
And a dump of the DMA registers would also be helpful.


From jeremy.kerr at canonical.com  Wed Jun  2 23:21:19 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Thu, 3 Jun 2010 11:21:19 +0800
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100602120356.GQ7248@trinity.fluff.org>
References: <1275479804.137633.565764505843.0.gpush@pororo>
	<1275479804.138101.137592675542.1.gpush@pororo>
	<20100602120356.GQ7248@trinity.fluff.org>
Message-ID: <201006031121.21896.jeremy.kerr@canonical.com>

Hi Ben,

> > And a set of clock operations (defined per type of clock):
> > 
> > struct clk_operations {
> > 
> >        int             (*enable)(struct clk *);
> 
> I'd rather the enable/disable calls where simply a set
> and a bool on/off, very rarelyt is the enable and disable
> operartions different.

I thought about merging these, but decided against it. It does work for the 
simple case where we're setting a bit in a register:

static int clk_foo_set_state(struct clk *_clk, int enable)
{
	struct clk_foo *clk = to_clk_foo(_clk)
	u32 reg;

	reg = raw_readl(foo->some_register);
	if (enable)
		reg |= FOO_ENABLE;
	else
		reg &= ~FOO_ENABLE;
	raw_writel(foo->some_register, reg);

	return 0;
}

However, for anything more complex than this - for example, if there's a 
parent clock - then we start getting pretty messy:

static int clk_foo_set_state(struct clk *_clk, int enable)
{
	struct clk_foo *clk = to_clk_foo(_clk)
	u32 reg;

	if (enable) {
		int ret = clk_enable(clk->parent);
		if (ret)
			return ret;
	}

	reg = raw_readl(foo->some_register);
	if (enable)
		reg |= FOO_ENABLE;
	else
		reg &= ~FOO_ENABLE;

	raw_writel(foo->some_register, reg);

	if (!enable)
		clk_disable(clk->parent);

	return 0;
}

- where most of the function becomes surrounded by "if (enable)" statements. 

I'm aware that we can turn this into a conditional call of clk_foo_enable or 
clk_foo_disable, but then we're back to square 1. I also think that the simple 
case is clearer (if a little more verbose) with separate functions.

Also, enable and disable in the external clock API have different return 
types.

> an aside, you might want to just clal these clk_ops to get into the
> spirit of the original naming.

Either is fine with me - looks like 'ops' is more commonly used:

$ git grep -E '^struct \w*operations\s*\{' include/ | wc -l
30

$ git grep -E '^struct \w*ops\s*{' include/ | wc -l
138

Cheers,


Jeremy


From jy0922.shim at samsung.com  Thu Jun  3 00:47:38 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 03 Jun 2010 13:47:38 +0900
Subject: [PATCH v2 5/5] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <20100603010025.GA14272@trinity.fluff.org>
References: <1275188784-23395-1-git-send-email-jy0922.shim@samsung.com>
	<1275188784-23395-5-git-send-email-jy0922.shim@samsung.com>
	<20100530034250.GK7248@trinity.fluff.org>
	<4C01EB2E.4020600@samsung.com>
	<20100603010025.GA14272@trinity.fluff.org>
Message-ID: <4C0733EA.6040907@samsung.com>

On 6/3/2010 10:00 AM, Ben Dooks wrote:
> On Sun, May 30, 2010 at 01:35:58PM +0900, Joonyoung Shim wrote:
> 
>>>> +static void samsung_kp_timer(unsigned long data)
>>>> +{
>>>> +	struct samsung_kp *keypad = (struct samsung_kp *)data;
>>>> +
>>>> +	schedule_work(&keypad->work);
> 
> would schedule_delayed_work() avoid the need for a timer here?
> 

Right. I will use schedule_delayed_work().

> 
>>>> +	keypad = kzalloc(sizeof(*keypad), GFP_KERNEL);
>>>> +	keycodes = kzalloc((pdata->rows << row_shift) * sizeof(*keycodes),
>>>> +			GFP_KERNEL);
>>> you could allocate this in one go.
>>>
>> Hmm, how i do it? Do you mean to allocate keypad and keycodes together?
> 
> There's a couple of ways to do this, they may of course be not the nicest
> ways.
> 
> make the last entry of the first (know size) structure a unsized array.
> as so:
> 
>    struct a {
>    	  ...
> 	  struct b t[];
>    }
> 
> then do
>      struct a *my_a;
>      my_a = kzalloc(sizeof(struct a ) + sizeof(struct b) * nr_b);
> 
> or by incrementing the pointer:
> 	struct a *my_a;
> 	struct b *my_b;
> 
> 	my_a = kzalloc(sizeof(struct a ) + sizeof(struct b) * nr_b);
> 	my_b = (struct b *)(my_a + 1);
>      

I have modified such as follow:

-	keypad = kzalloc(sizeof(*keypad), GFP_KERNEL);
-	keycodes = kzalloc((pdata->rows << row_shift) * sizeof(*keycodes),
-			GFP_KERNEL);
+	/* alloc with keycodes memory */
+	keypad = kzalloc(sizeof(*keypad) + sizeof(*keycodes) *
+			(pdata->rows << row_shift), GFP_KERNEL);
 	input_dev = input_allocate_device();
-	if (!keypad || !keycodes || !input_dev) {
+	if (!keypad || !input_dev) {
 		ret = -ENOMEM;
 		goto err_free_mem;
 	}
+	keycodes = (unsigned short *)(keypad + 1);

>>>> +	keypad->clk = clk_get(&pdev->dev, "keypad");
> 
> I'm going to get rid of this practice, it should be clk_get(&pdev->dev, NULL),
> see up-comming clock changes.
> 

It is not difficult to modify this if your clock changes are no problem.

> 
>>>> +	ret = request_irq(keypad->irq, samsung_kp_interrupt, 0,
>>>> +			dev_name(&pdev->dev), keypad);
>>>> +
>>>> +	if (ret)
> NO PRINT HERE?
> 

I will add.

>>>> +		goto err_disable_clk;
>>>> +
>>>> +	input_dev->name = pdev->name;
>>>> +	input_dev->id.bustype = BUS_HOST;
>>>> +	input_dev->dev.parent = &pdev->dev;
>>>> +
>>>> +	input_dev->evbit[0] = BIT_MASK(EV_KEY);
>>>> +	if (pdata->rep)
>>>> +		input_dev->evbit[0] |= BIT_MASK(EV_REP);
>>>> +
>>>> +	input_dev->keycode = keycodes;
>>>> +	input_dev->keycodesize = sizeof(*keycodes);
>>>> +	input_dev->keycodemax = pdata->rows << row_shift;
>>>> +
>>>> +	matrix_keypad_build_keymap(keymap_data, row_shift,
>>>> +			input_dev->keycode, input_dev->keybit);
>>>> +
>>>> +	ret = input_register_device(keypad->input_dev);
>>>> +	if (ret)
>>>> +		goto err_free_irq;
>>>> +
>>>> +	platform_set_drvdata(pdev, keypad);
>>>> +	clk_disable(keypad->clk);
>>>> +
>>>> +	return 0;
>>>> +
>>>> +err_free_irq:
>>>> +	free_irq(keypad->irq, keypad);
>>>> +err_disable_clk:
>>>> +	clk_disable(keypad->clk);
>>>> +	clk_put(keypad->clk);
>>>> +err_unmap_base:
>>>> +	iounmap(keypad->base);
>>>> +err_free_mem:
>>>> +	input_free_device(input_dev);
>>>> +	kfree(keycodes);
>>>> +	kfree(keypad);
>>>> +
>>>> +	return ret;
>>>> +}
>>>> +
>>>> +static int __devexit samsung_kp_remove(struct platform_device *pdev)
>>>> +{
>>>> +	struct samsung_kp *keypad = platform_get_drvdata(pdev);
>>>> +
>>>> +	free_irq(keypad->irq, keypad);
>>>> +	cancel_work_sync(&keypad->work);
>>>> +	del_timer_sync(&keypad->timer);
>>>> +
>>>> +	platform_set_drvdata(pdev, NULL);
>>>> +	input_unregister_device(keypad->input_dev);
>>>> +
>>>> +	clk_disable(keypad->clk);
>>>> +	clk_put(keypad->clk);
>>>> +
>>>> +	iounmap(keypad->base);
>>>> +	kfree(keypad->keycodes);
>>>> +	kfree(keypad);
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>>> +#ifdef CONFIG_PM
>>>> +static int samsung_kp_suspend(struct device *dev)
>>>> +{
>>>> +	struct platform_device *pdev = to_platform_device(dev);
>>>> +	struct samsung_kp *keypad = platform_get_drvdata(pdev);
>>>> +
>>>> +	disable_irq(keypad->irq);
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>>> +static int samsung_kp_resume(struct device pdev)
>>>> +{
>>>> +	struct platform_device *pdev = to_platform_device(dev);
>>>> +	struct samsung_kp *keypad = platform_get_drvdata(pdev);
>>>> +	unsigned int val;
>>>> +
>>>> +	clk_enable(keypad->clk);
>>>> +
>>>> +	/* enable interrupt and wakeup bit */
>>>> +	val = SAMSUNG_INT_F_EN | SAMSUNG_INT_R_EN | SAMSUNG_WAKEUPEN;
>>>> +	writel(val, keypad->base + SAMSUNG_KEYIFCON);
>>>> +
>>>> +	/* KEYIFCOL reg clear */
>>>> +	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
>>>> +
>>>> +	enable_irq(keypad->irq);
>>>> +	clk_disable(keypad->clk);
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>>> +static const struct dev_pm_ops samsung_kp_pm_ops = {
>>>> +	.suspend	= samsung_kp_suspend,
>>>> +	.resume		= samsung_kp_resume,
>>>> +};
>>>> +#endif
>>>> +
>>>> +static struct platform_driver samsung_kp_driver = {
>>>> +	.probe		= samsung_kp_probe,
>>>> +	.remove		= __devexit_p(samsung_kp_remove),
>>>> +	.driver		= {
>>>> +		.name	= "samsung-keypad",
>>>> +		.owner	= THIS_MODULE,
>>>> +#ifdef CONFIG_PM
>>>> +		.pm	= &samsung_kp_pm_ops,
>>>> +#endif
>>>> +	},
>>>> +};
>>>> +
>>>> +static int __init samsung_kp_init(void)
>>>> +{
>>>> +	return platform_driver_register(&samsung_kp_driver);
>>>> +}
>>>> +
>>>> +static void __exit samsung_kp_exit(void)
>>>> +{
>>>> +	platform_driver_unregister(&samsung_kp_driver);
>>>> +}
>>>> +
>>>> +module_init(samsung_kp_init);
>>>> +module_exit(samsung_kp_exit);
>>>> +
>>>> +MODULE_DESCRIPTION("Samsung keypad driver");
>>>> +MODULE_AUTHOR("Joonyoung Shim <jy0922.shim at samsung.com>");
>>>> +MODULE_AUTHOR("Donghwa Lee <dh09.lee at samsung.com>");
>>>> +MODULE_LICENSE("GPL");
> 
> You missed MODULE_ALIAS() for your platform device name
> 

I will add.

Thanks.


From jy0922.shim at samsung.com  Thu Jun  3 01:05:27 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 03 Jun 2010 14:05:27 +0900
Subject: [PATCH 0/7] ARM: S5P: Support gpio interrupts and GPIOlib gpio_to_irq
Message-ID: <4C073817.7020000@samsung.com>

This patch set is to support gpio interrupts and GPIOlib gpio_to_irq of
gpio and external interrupts at the samsung s5p cpus.

---
Joonyoung Shim (7):
      ARM: S5PC100: Move external interrupt defines
      ARM: S5P: Add GPIOlib gpio_to_irq for external interrupts
      ARM: S5PV210: Support GPIOlib gpio_to_irq for external interrupts
      ARM: S5PC100: Use S5P GPIOlib gpio_to_irq function for external interrupts
      ARM: S5PV210: Add gpio interrupt support
      ARM: S5PC100: Use S5P gpio interrupts interface
      ARM: S5P: Add GPIOlib gpio_to_irq for gpio interrupts

 arch/arm/mach-s5pc100/Makefile                 |    2 +-
 arch/arm/mach-s5pc100/gpiolib.c                |   65 +-----
 arch/arm/mach-s5pc100/include/mach/gpio.h      |    7 -
 arch/arm/mach-s5pc100/include/mach/irqs.h      |   18 ++-
 arch/arm/mach-s5pc100/include/mach/regs-gpio.h |    7 +
 arch/arm/mach-s5pc100/irq-gpio.c               |  266 ------------------------
 arch/arm/mach-s5pv210/gpiolib.c                |   13 +-
 arch/arm/mach-s5pv210/include/mach/irqs.h      |   16 ++-
 arch/arm/plat-s5p/Makefile                     |    3 +-
 arch/arm/plat-s5p/gpiolib.c                    |   42 ++++
 arch/arm/plat-s5p/irq-gpioint.c                |  208 ++++++++++++++++++
 arch/arm/plat-samsung/include/plat/gpio-core.h |    6 +
 12 files changed, 319 insertions(+), 334 deletions(-)
 delete mode 100644 arch/arm/mach-s5pc100/irq-gpio.c
 create mode 100644 arch/arm/plat-s5p/gpiolib.c
 create mode 100644 arch/arm/plat-s5p/irq-gpioint.c


From jy0922.shim at samsung.com  Thu Jun  3 01:01:33 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 03 Jun 2010 14:01:33 +0900
Subject: [PATCH 1/7] ARM: S5PC100: Move external interrupt defines
Message-ID: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>

This patch moves external interrupt defines from gpio.h to regs-gpio.h
for consistency with s5pv210.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pc100/include/mach/gpio.h      |    7 -------
 arch/arm/mach-s5pc100/include/mach/regs-gpio.h |    7 +++++++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 71ae1f5..29a8a12 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -146,13 +146,6 @@ enum s5p_gpio_number {
 /* define the number of gpios we need to the one after the MP04() range */
 #define ARCH_NR_GPIOS		(S5PC100_GPIO_END + 1)
 
-#define EINT_MODE		S3C_GPIO_SFN(0x2)
-
-#define EINT_GPIO_0(x)		S5PC100_GPH0(x)
-#define EINT_GPIO_1(x)		S5PC100_GPH1(x)
-#define EINT_GPIO_2(x)		S5PC100_GPH2(x)
-#define EINT_GPIO_3(x)		S5PC100_GPH3(x)
-
 #include <asm-generic/gpio.h>
 
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
index dd6295e..6abe481 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
@@ -71,5 +71,12 @@
 #define S5P_EXTINT_RISEEDGE		(0x03)
 #define S5P_EXTINT_BOTHEDGE		(0x04)
 
+#define EINT_MODE		S3C_GPIO_SFN(0x2)
+
+#define EINT_GPIO_0(x)		S5PC100_GPH0(x)
+#define EINT_GPIO_1(x)		S5PC100_GPH1(x)
+#define EINT_GPIO_2(x)		S5PC100_GPH2(x)
+#define EINT_GPIO_3(x)		S5PC100_GPH3(x)
+
 #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
 
-- 
1.7.0.4



From jy0922.shim at samsung.com  Thu Jun  3 01:01:34 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 03 Jun 2010 14:01:34 +0900
Subject: [PATCH 2/7] ARM: S5P: Add GPIOlib gpio_to_irq for external interrupts
In-Reply-To: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
References: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1275541299-25566-2-git-send-email-jy0922.shim@samsung.com>

This patch is to support gpio_to_irq() of GPIOlib for external
interrupts. The gpio_to_irq() calls s5p_gpiolib_eint_to_irq function.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-s5p/Makefile                     |    1 +
 arch/arm/plat-s5p/gpiolib.c                    |   35 ++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/gpio-core.h |    2 +
 3 files changed, 38 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-s5p/gpiolib.c

diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 39c242b..f6e1a13 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -15,6 +15,7 @@ obj-				:=
 obj-y				+= dev-uart.o
 obj-y				+= cpu.o
 obj-y				+= clock.o
+obj-y				+= gpiolib.o
 obj-y				+= irq.o
 obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
 
diff --git a/arch/arm/plat-s5p/gpiolib.c b/arch/arm/plat-s5p/gpiolib.c
new file mode 100644
index 0000000..0c27a9d
--- /dev/null
+++ b/arch/arm/plat-s5p/gpiolib.c
@@ -0,0 +1,35 @@
+/*
+ * linux/arch/arm/plat-s5p/gpiolib.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ * S5P - GPIOlib support
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/gpio.h>
+#include <mach/irqs.h>
+#include <mach/regs-gpio.h>
+
+/* be called from gpio_to_irq() for external interrupts */
+int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+	switch (chip->base) {
+	case EINT_GPIO_0(0):
+		return IRQ_EINT(offset);
+	case EINT_GPIO_1(0):
+		return IRQ_EINT(8 + offset);
+	case EINT_GPIO_2(0):
+		return IRQ_EINT(16 + offset);
+	case EINT_GPIO_3(0):
+		return IRQ_EINT(24 + offset);
+	default:
+		return -EINVAL;
+	}
+}
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index e358c7d..f6c5151 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -121,6 +121,8 @@ extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
 /* exported for core SoC support to change */
 extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
 
+extern int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset);
+
 #ifdef CONFIG_S3C_GPIO_TRACK
 extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
 
-- 
1.7.0.4



From jy0922.shim at samsung.com  Thu Jun  3 01:01:37 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 03 Jun 2010 14:01:37 +0900
Subject: [PATCH 5/7] ARM: S5PV210: Add gpio interrupt support
In-Reply-To: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
References: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1275541299-25566-5-git-send-email-jy0922.shim@samsung.com>

This patch is to support gpio interrupts on s5pv210.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pv210/gpiolib.c                |    8 +-
 arch/arm/mach-s5pv210/include/mach/irqs.h      |   16 ++-
 arch/arm/plat-s5p/Makefile                     |    2 +-
 arch/arm/plat-s5p/irq-gpioint.c                |  208 ++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/gpio-core.h |    2 +
 5 files changed, 233 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/plat-s5p/irq-gpioint.c

diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
index 5b73c3e..166725f 100644
--- a/arch/arm/mach-s5pv210/gpiolib.c
+++ b/arch/arm/mach-s5pv210/gpiolib.c
@@ -150,6 +150,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.label	= "GPG3",
 		},
 	}, {
+		.config	= &gpio_cfg_noint,
 		.chip	= {
 			.base	= S5PV210_GPI(0),
 			.ngpio	= S5PV210_GPIO_I_NR,
@@ -249,11 +250,16 @@ static __init int s5pv210_gpiolib_init(void)
 {
 	struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
 	int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
+	int gpioint_group = 0;
 	int i = 0;
 
 	for (i = 0; i < nr_chips; i++, chip++) {
-		if (chip->config == NULL)
+		if (chip->config == NULL) {
 			chip->config = &gpio_cfg;
+
+			/* gpio interrupts */
+			s5p_gpioint_add(chip, gpioint_group++);
+		}
 		if (chip->base == NULL)
 			chip->base = S5PV210_BANK_BASE(i);
 	}
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 9689537..43baacc 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -121,8 +121,22 @@
 #define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2		(IRQ_VIC_END + 1)
 
+/* GPIO interrupt */
+#define S5P_GPIOINT_GROUP_NR	22
+#define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
+#define S5P_IRQ_GPIOINT(x)	(S5P_GPIOINT_BASE + (x))
+
 /* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + 1)
+
+/*
+ * GPIO groups is 27. Each GPIO group can have max 8 GPIO interrupts.
+ *
+ * We should include gpios of all gpio groups from GPIO_A0 until GPIO_J4 to
+ * NR_IRQS because 22 gpio groups having gpio interrupts aren't in order and
+ * are mixed with no interrupt gpio groups, then it can give simple irq
+ * computation of gpio interrupts.
+ */
+#define NR_IRQS			(S5P_IRQ_GPIOINT(27 * 8) + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index f6e1a13..23c153c 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -16,6 +16,6 @@ obj-y				+= dev-uart.o
 obj-y				+= cpu.o
 obj-y				+= clock.o
 obj-y				+= gpiolib.o
-obj-y				+= irq.o
+obj-y				+= irq.o irq-gpioint.o
 obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
 
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
new file mode 100644
index 0000000..c172e37
--- /dev/null
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -0,0 +1,208 @@
+/*
+ * linux/arch/arm/plat-s5p/irq-gpioint.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Kyungmin Park <kyungmin.park at samsung.com>
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+
+#define S5P_GPIOREG(x)			(S5P_VA_GPIO + (x))
+
+#define GPIOINT_CON_OFFSET		0x700
+#define GPIOINT_MASK_OFFSET		0x900
+#define GPIOINT_PEND_OFFSET		0xA00
+
+#define GPIOINT_LEVEL_LOW		0x0
+#define GPIOINT_LEVEL_HIGH		0x1
+#define GPIOINT_EDGE_FALLING		0x2
+#define GPIOINT_EDGE_RISING		0x3
+#define GPIOINT_EDGE_BOTH		0x4
+
+static struct s3c_gpio_chip *s3c_chips[S5P_GPIOINT_GROUP_NR];
+
+static int s5p_gpioint_get_group(unsigned int irq)
+{
+	struct gpio_chip *chip = get_irq_data(irq);
+	struct s3c_gpio_chip *s3c_chip = container_of(chip,
+			struct s3c_gpio_chip, chip);
+	int group;
+
+	for (group = 0; group < S5P_GPIOINT_GROUP_NR; group++)
+		if (s3c_chip == s3c_chips[group])
+			break;
+
+	return group;
+}
+
+static int s5p_gpioint_get_offset(unsigned int irq)
+{
+	struct gpio_chip *chip = get_irq_data(irq);
+	return irq - S5P_IRQ_GPIOINT(chip->base);
+}
+
+static void s5p_gpioint_ack(unsigned int irq)
+{
+	int group, offset, pend_offset;
+	unsigned int value;
+
+	group = s5p_gpioint_get_group(irq);
+	offset = s5p_gpioint_get_offset(irq);
+	pend_offset = group << 2;
+
+	value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
+	value |= 1 << offset;
+	__raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
+}
+
+static void s5p_gpioint_mask(unsigned int irq)
+{
+	int group, offset, mask_offset;
+	unsigned int value;
+
+	group = s5p_gpioint_get_group(irq);
+	offset = s5p_gpioint_get_offset(irq);
+	mask_offset = group << 2;
+
+	value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+	value |= 1 << offset;
+	__raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+}
+
+static void s5p_gpioint_unmask(unsigned int irq)
+{
+	int group, offset, mask_offset;
+	unsigned int value;
+
+	group = s5p_gpioint_get_group(irq);
+	offset = s5p_gpioint_get_offset(irq);
+	mask_offset = group << 2;
+
+	value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+	value &= ~(1 << offset);
+	__raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+}
+
+static void s5p_gpioint_mask_ack(unsigned int irq)
+{
+	s5p_gpioint_mask(irq);
+	s5p_gpioint_ack(irq);
+}
+
+static int s5p_gpioint_set_type(unsigned int irq, unsigned int type)
+{
+	int group, offset, con_offset;
+	unsigned int value;
+
+	group = s5p_gpioint_get_group(irq);
+	offset = s5p_gpioint_get_offset(irq);
+	con_offset = group << 2;
+
+	switch (type) {
+	case IRQ_TYPE_NONE:
+		printk(KERN_WARNING "No irq type\n");
+		return -EINVAL;
+	case IRQ_TYPE_EDGE_RISING:
+		type = GPIOINT_EDGE_RISING;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		type = GPIOINT_EDGE_FALLING;
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		type = GPIOINT_EDGE_BOTH;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		type = GPIOINT_LEVEL_HIGH;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		type = GPIOINT_LEVEL_LOW;
+		break;
+	default:
+		BUG();
+	}
+
+	value = __raw_readl(S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset);
+	value &= ~(0xf << (offset * 0x4));
+	value |= (type << (offset * 0x4));
+	__raw_writel(value, S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset);
+
+	return 0;
+}
+
+struct irq_chip s5p_gpioint = {
+	.name		= "GPIO",
+	.ack		= s5p_gpioint_ack,
+	.mask		= s5p_gpioint_mask,
+	.mask_ack	= s5p_gpioint_mask_ack,
+	.unmask		= s5p_gpioint_unmask,
+	.set_type	= s5p_gpioint_set_type,
+};
+
+static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
+{
+	int group, offset, pend_offset, mask_offset;
+	int real_irq;
+	unsigned int pend, mask;
+
+	for (group = 0; group < S5P_GPIOINT_GROUP_NR; group++) {
+		pend_offset = group << 2;
+		pend = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) +
+				pend_offset);
+		if (!pend)
+			continue;
+
+		mask_offset = group << 2;
+		mask = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) +
+				mask_offset);
+		pend &= ~mask;
+
+		for (offset = 0; offset < 8; offset++) {
+			if (pend & (1 << offset)) {
+				real_irq = s3c_chips[group]->chip.base +
+					   offset;
+				generic_handle_irq(S5P_IRQ_GPIOINT(real_irq));
+			}
+		}
+	}
+}
+
+void s5p_gpioint_add(struct s3c_gpio_chip *chip, int group)
+{
+	int irq;
+	int i;
+
+	s3c_chips[group] = chip;
+
+	for (i = 0; i < chip->chip.ngpio; i++) {
+		irq = S5P_GPIOINT_BASE + chip->chip.base + i;
+		set_irq_chip(irq, &s5p_gpioint);
+		set_irq_data(irq, &chip->chip);
+		set_irq_handler(irq, handle_level_irq);
+		set_irq_flags(irq, IRQF_VALID);
+	}
+}
+
+int __init s5p_gpioint_init(void)
+{
+	/* register gpio interrupt handler */
+	set_irq_chained_handler(IRQ_GPIOINT, s5p_gpioint_handler);
+
+	return 0;
+}
+
+arch_initcall(s5p_gpioint_init);
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index f6c5151..a6b844c 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -123,6 +123,8 @@ extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
 
 extern int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset);
 
+extern void s5p_gpioint_add(struct s3c_gpio_chip *chip, int group);
+
 #ifdef CONFIG_S3C_GPIO_TRACK
 extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
 
-- 
1.7.0.4



From jy0922.shim at samsung.com  Thu Jun  3 01:01:35 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 03 Jun 2010 14:01:35 +0900
Subject: [PATCH 3/7] ARM: S5PV210: Support GPIOlib gpio_to_irq for external
	interrupts
In-Reply-To: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
References: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1275541299-25566-3-git-send-email-jy0922.shim@samsung.com>

This patch is to support GPIOlib gpio_to_irq for external interrupts to
s5pv210 machine.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pv210/gpiolib.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
index 9ea8972..5b73c3e 100644
--- a/arch/arm/mach-s5pv210/gpiolib.c
+++ b/arch/arm/mach-s5pv210/gpiolib.c
@@ -213,6 +213,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.base	= S5PV210_GPH0(0),
 			.ngpio	= S5PV210_GPIO_H0_NR,
 			.label	= "GPH0",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= (S5P_VA_GPIO + 0xC20),
@@ -221,6 +222,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.base	= S5PV210_GPH1(0),
 			.ngpio	= S5PV210_GPIO_H1_NR,
 			.label	= "GPH1",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= (S5P_VA_GPIO + 0xC40),
@@ -229,6 +231,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.base	= S5PV210_GPH2(0),
 			.ngpio	= S5PV210_GPIO_H2_NR,
 			.label	= "GPH2",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= (S5P_VA_GPIO + 0xC60),
@@ -237,6 +240,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.base	= S5PV210_GPH3(0),
 			.ngpio	= S5PV210_GPIO_H3_NR,
 			.label	= "GPH3",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	},
 };
-- 
1.7.0.4



From jy0922.shim at samsung.com  Thu Jun  3 01:01:38 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 03 Jun 2010 14:01:38 +0900
Subject: [PATCH 6/7] ARM: S5PC100: Use S5P gpio interrupts interface
In-Reply-To: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
References: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1275541299-25566-6-git-send-email-jy0922.shim@samsung.com>

The s5pc100 can use s5p gpio interrupts codes instead of s5pc100
specific gpio interrupts codes.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pc100/Makefile            |    2 +-
 arch/arm/mach-s5pc100/gpiolib.c           |   37 +---
 arch/arm/mach-s5pc100/include/mach/irqs.h |   18 ++-
 arch/arm/mach-s5pc100/irq-gpio.c          |  266 -----------------------------
 4 files changed, 24 insertions(+), 299 deletions(-)
 delete mode 100644 arch/arm/mach-s5pc100/irq-gpio.c

diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 543f3de..e9723f8 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -11,7 +11,7 @@ obj-				:=
 
 # Core support for S5PC100 system
 
-obj-$(CONFIG_CPU_S5PC100)	+= cpu.o init.o clock.o gpiolib.o irq-gpio.o
+obj-$(CONFIG_CPU_S5PC100)	+= cpu.o init.o clock.o gpiolib.o
 obj-$(CONFIG_CPU_S5PC100)	+= setup-i2c0.o
 obj-$(CONFIG_CPU_S5PC100)	+= dma.o
 
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index 60704ef..a34a700 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -63,7 +63,7 @@
 
 static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
 {
-	return S3C_IRQ_GPIO(chip->base + offset);
+	return S5P_IRQ_GPIOINT(chip->base + offset);
 }
 
 static struct s3c_gpio_cfg gpio_cfg = {
@@ -365,45 +365,26 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 	},
 };
 
-/* FIXME move from irq-gpio.c */
-extern struct irq_chip s5pc100_gpioint;
-extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
-
-static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
-{
-	/* Interrupt */
-	if (chip->config == &gpio_cfg) {
-		int i, irq;
-
-		chip->chip.to_irq = s5pc100_gpiolib_to_irq;
-
-		for (i = 0;  i < chip->chip.ngpio; i++) {
-			irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
-			set_irq_chip(irq, &s5pc100_gpioint);
-			set_irq_data(irq, &chip->chip);
-			set_irq_handler(irq, handle_level_irq);
-			set_irq_flags(irq, IRQF_VALID);
-		}
-	}
-}
-
 static __init int s5pc100_gpiolib_init(void)
 {
 	struct s3c_gpio_chip *chip;
 	int nr_chips;
+	int gpioint_group = 0;
 
 	chip = s5pc100_gpio_chips;
 	nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
 
-	for (; nr_chips > 0; nr_chips--, chip++)
-		s5pc100_gpiolib_link(chip);
+	for (; nr_chips > 0; nr_chips--, chip++) {
+		if (chip->config == &gpio_cfg) {
+			/* gpio interrupts */
+			chip->chip.to_irq = s5pc100_gpiolib_to_irq;
+			s5p_gpioint_add(chip, gpioint_group++);
+		}
+	}
 
 	samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
 				       ARRAY_SIZE(s5pc100_gpio_chips));
 
-	/* Interrupt */
-	set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
-
 	return 0;
 }
 core_initcall(s5pc100_gpiolib_init);
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 28aa551..8f725bd 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -100,11 +100,21 @@
 #define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2		(IRQ_VIC_END + 1)
 
-#define S3C_IRQ_GPIO_BASE	(IRQ_EINT(31) + 1)
-#define S3C_IRQ_GPIO(x)		(S3C_IRQ_GPIO_BASE + (x))
+#define S5P_GPIOINT_GROUP_NR	21
+#define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
+#define S5P_IRQ_GPIOINT(x)	(S5P_GPIOINT_BASE + (x))
 
-/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
-#define NR_IRQS		(S3C_IRQ_GPIO(320) + 1)
+/* Set the default NR_IRQS */
+
+/*
+ * GPIO groups is 25. Each GPIO group can have max 8 GPIO interrupts.
+ *
+ * We should include gpios of all gpio groups from GPIO_A0 until GPIO_J4 to
+ * NR_IRQS because 21 gpio groups having gpio interrupts aren't in order and
+ * are mixed with no interrupt gpio groups, then it can give simple irq
+ * computation of gpio interrupts.
+ */
+#define NR_IRQS			(S5P_IRQ_GPIOINT(25 * 8) + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0
diff --git a/arch/arm/mach-s5pc100/irq-gpio.c b/arch/arm/mach-s5pc100/irq-gpio.c
deleted file mode 100644
index 2bf86c1..0000000
--- a/arch/arm/mach-s5pc100/irq-gpio.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * arch/arm/mach-s5pc100/irq-gpio.c
- *
- * Copyright (C) 2009 Samsung Electronics
- *
- * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <mach/map.h>
-#include <plat/gpio-cfg.h>
-
-#define S5P_GPIOREG(x)		(S5P_VA_GPIO + (x))
-
-#define CON_OFFSET			0x700
-#define MASK_OFFSET			0x900
-#define PEND_OFFSET			0xA00
-#define CON_OFFSET_2			0xE00
-#define MASK_OFFSET_2			0xF00
-#define PEND_OFFSET_2			0xF40
-
-#define GPIOINT_LEVEL_LOW		0x0
-#define GPIOINT_LEVEL_HIGH		0x1
-#define GPIOINT_EDGE_FALLING		0x2
-#define GPIOINT_EDGE_RISING		0x3
-#define GPIOINT_EDGE_BOTH		0x4
-
-static int group_to_con_offset(int group)
-{
-	return group << 2;
-}
-
-static int group_to_mask_offset(int group)
-{
-	return group << 2;
-}
-
-static int group_to_pend_offset(int group)
-{
-	return group << 2;
-}
-
-static int s5pc100_get_start(unsigned int group)
-{
-	switch (group) {
-	case 0: return S5PC100_GPIO_A0_START;
-	case 1: return S5PC100_GPIO_A1_START;
-	case 2: return S5PC100_GPIO_B_START;
-	case 3: return S5PC100_GPIO_C_START;
-	case 4: return S5PC100_GPIO_D_START;
-	case 5: return S5PC100_GPIO_E0_START;
-	case 6: return S5PC100_GPIO_E1_START;
-	case 7: return S5PC100_GPIO_F0_START;
-	case 8: return S5PC100_GPIO_F1_START;
-	case 9: return S5PC100_GPIO_F2_START;
-	case 10: return S5PC100_GPIO_F3_START;
-	case 11: return S5PC100_GPIO_G0_START;
-	case 12: return S5PC100_GPIO_G1_START;
-	case 13: return S5PC100_GPIO_G2_START;
-	case 14: return S5PC100_GPIO_G3_START;
-	case 15: return S5PC100_GPIO_I_START;
-	case 16: return S5PC100_GPIO_J0_START;
-	case 17: return S5PC100_GPIO_J1_START;
-	case 18: return S5PC100_GPIO_J2_START;
-	case 19: return S5PC100_GPIO_J3_START;
-	case 20: return S5PC100_GPIO_J4_START;
-	default:
-		BUG();
-	}
-
-	return -EINVAL;
-}
-
-static int s5pc100_get_group(unsigned int irq)
-{
-	irq -= S3C_IRQ_GPIO(0);
-
-	switch (irq) {
-	case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
-		return 0;
-	case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
-		return 1;
-	case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
-		return 2;
-	case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
-		return 3;
-	case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
-		return 4;
-	case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
-		return 5;
-	case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
-		return 6;
-	case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
-		return 7;
-	case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
-		return 8;
-	case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
-		return 9;
-	case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
-		return 10;
-	case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
-		return 11;
-	case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
-		return 12;
-	case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
-		return 13;
-	case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
-		return 14;
-	case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
-		return 15;
-	case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
-		return 16;
-	case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
-		return 17;
-	case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
-		return 18;
-	case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
-		return 19;
-	case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
-		return 20;
-	default:
-		BUG();
-	}
-
-	return -EINVAL;
-}
-
-static int s5pc100_get_offset(unsigned int irq)
-{
-	struct gpio_chip *chip = get_irq_data(irq);
-	return irq - S3C_IRQ_GPIO(chip->base);
-}
-
-static void s5pc100_gpioint_ack(unsigned int irq)
-{
-	int group, offset, pend_offset;
-	unsigned int value;
-
-	group = s5pc100_get_group(irq);
-	offset = s5pc100_get_offset(irq);
-	pend_offset = group_to_pend_offset(group);
-
-	value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
-	value |= 1 << offset;
-	__raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset);
-}
-
-static void s5pc100_gpioint_mask(unsigned int irq)
-{
-	int group, offset, mask_offset;
-	unsigned int value;
-
-	group = s5pc100_get_group(irq);
-	offset = s5pc100_get_offset(irq);
-	mask_offset = group_to_mask_offset(group);
-
-	value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-	value |= 1 << offset;
-	__raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-}
-
-static void s5pc100_gpioint_unmask(unsigned int irq)
-{
-	int group, offset, mask_offset;
-	unsigned int value;
-
-	group = s5pc100_get_group(irq);
-	offset = s5pc100_get_offset(irq);
-	mask_offset = group_to_mask_offset(group);
-
-	value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-	value &= ~(1 << offset);
-	__raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-}
-
-static void s5pc100_gpioint_mask_ack(unsigned int irq)
-{
-	s5pc100_gpioint_mask(irq);
-	s5pc100_gpioint_ack(irq);
-}
-
-static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type)
-{
-	int group, offset, con_offset;
-	unsigned int value;
-
-	group = s5pc100_get_group(irq);
-	offset = s5pc100_get_offset(irq);
-	con_offset = group_to_con_offset(group);
-
-	switch (type) {
-	case IRQ_TYPE_NONE:
-		printk(KERN_WARNING "No irq type\n");
-		return -EINVAL;
-	case IRQ_TYPE_EDGE_RISING:
-		type = GPIOINT_EDGE_RISING;
-		break;
-	case IRQ_TYPE_EDGE_FALLING:
-		type = GPIOINT_EDGE_FALLING;
-		break;
-	case IRQ_TYPE_EDGE_BOTH:
-		type = GPIOINT_EDGE_BOTH;
-		break;
-	case IRQ_TYPE_LEVEL_HIGH:
-		type = GPIOINT_LEVEL_HIGH;
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		type = GPIOINT_LEVEL_LOW;
-		break;
-	default:
-		BUG();
-	}
-
-
-	value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset);
-	value &= ~(0xf << (offset * 0x4));
-	value |= (type << (offset * 0x4));
-	__raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset);
-
-	return 0;
-}
-
-struct irq_chip s5pc100_gpioint = {
-	.name		= "GPIO",
-	.ack		= s5pc100_gpioint_ack,
-	.mask		= s5pc100_gpioint_mask,
-	.mask_ack	= s5pc100_gpioint_mask_ack,
-	.unmask		= s5pc100_gpioint_unmask,
-	.set_type	= s5pc100_gpioint_set_type,
-};
-
-void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
-{
-	int group, offset, pend_offset, mask_offset;
-	int real_irq, group_end;
-	unsigned int pend, mask;
-
-	group_end = 21;
-
-	for (group = 0; group < group_end; group++) {
-		pend_offset = group_to_pend_offset(group);
-		pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
-		if (!pend)
-			continue;
-
-		mask_offset = group_to_mask_offset(group);
-		mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-		pend &= ~mask;
-
-		for (offset = 0; offset < 8; offset++) {
-			if (pend & (1 << offset)) {
-				real_irq = s5pc100_get_start(group) + offset;
-				generic_handle_irq(S3C_IRQ_GPIO(real_irq));
-			}
-		}
-	}
-}
-- 
1.7.0.4



From jy0922.shim at samsung.com  Thu Jun  3 01:01:36 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 03 Jun 2010 14:01:36 +0900
Subject: [PATCH 4/7] ARM: S5PC100: Use S5P GPIOlib gpio_to_irq function for
	external interrupts
In-Reply-To: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
References: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1275541299-25566-4-git-send-email-jy0922.shim@samsung.com>

This changes from s5pc100 machine specific gpio_to_irq function to
S5P GPIOlib gpio_to_irq function for external interrupts.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pc100/gpiolib.c |   25 ++++---------------------
 1 files changed, 4 insertions(+), 21 deletions(-)

diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index 0fab7f2..60704ef 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -66,25 +66,6 @@ static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
 	return S3C_IRQ_GPIO(chip->base + offset);
 }
 
-static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
-{
-	int base;
-
-	base = chip->base - S5PC100_GPH0(0);
-	if (base == 0)
-		return IRQ_EINT(offset);
-	base = chip->base - S5PC100_GPH1(0);
-	if (base == 0)
-		return IRQ_EINT(8 + offset);
-	base = chip->base - S5PC100_GPH2(0);
-	if (base == 0)
-		return IRQ_EINT(16 + offset);
-	base = chip->base - S5PC100_GPH3(0);
-	if (base == 0)
-		return IRQ_EINT(24 + offset);
-	return -EINVAL;
-}
-
 static struct s3c_gpio_cfg gpio_cfg = {
 	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
 	.set_pull	= s3c_gpio_setpull_updown,
@@ -232,6 +213,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 			.base	= S5PC100_GPH0(0),
 			.ngpio	= S5PC100_GPIO_H0_NR,
 			.label	= "GPH0",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPH1_BASE,
@@ -240,6 +222,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 			.base	= S5PC100_GPH1(0),
 			.ngpio	= S5PC100_GPIO_H1_NR,
 			.label	= "GPH1",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPH2_BASE,
@@ -248,6 +231,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 			.base	= S5PC100_GPH2(0),
 			.ngpio	= S5PC100_GPIO_H2_NR,
 			.label	= "GPH2",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPH3_BASE,
@@ -256,6 +240,7 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 			.base	= S5PC100_GPH3(0),
 			.ngpio	= S5PC100_GPIO_H3_NR,
 			.label	= "GPH3",
+			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPI_BASE,
@@ -399,8 +384,6 @@ static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
 			set_irq_handler(irq, handle_level_irq);
 			set_irq_flags(irq, IRQF_VALID);
 		}
-	} else if (chip->config == &gpio_cfg_eint) {
-		chip->chip.to_irq = s5pc100_gpiolib_to_eint;
 	}
 }
 
-- 
1.7.0.4



From jy0922.shim at samsung.com  Thu Jun  3 01:01:39 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 03 Jun 2010 14:01:39 +0900
Subject: [PATCH 7/7] ARM: S5P: Add GPIOlib gpio_to_irq for gpio interrupts
In-Reply-To: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
References: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1275541299-25566-7-git-send-email-jy0922.shim@samsung.com>

This patch is to support gpio_to_irq() of GPIOlib for gpio interrupts on
s5p cpus. The gpio_to_irq() calls s5p_gpiolib_gpioint_to_irq function.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pc100/gpiolib.c                |    7 +------
 arch/arm/mach-s5pv210/gpiolib.c                |    1 +
 arch/arm/plat-s5p/gpiolib.c                    |    7 +++++++
 arch/arm/plat-samsung/include/plat/gpio-core.h |    2 ++
 4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index a34a700..2dcb501 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -61,11 +61,6 @@
  * L3	8	4Bit	None
  */
 
-static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
-{
-	return S5P_IRQ_GPIOINT(chip->base + offset);
-}
-
 static struct s3c_gpio_cfg gpio_cfg = {
 	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
 	.set_pull	= s3c_gpio_setpull_updown,
@@ -377,7 +372,7 @@ static __init int s5pc100_gpiolib_init(void)
 	for (; nr_chips > 0; nr_chips--, chip++) {
 		if (chip->config == &gpio_cfg) {
 			/* gpio interrupts */
-			chip->chip.to_irq = s5pc100_gpiolib_to_irq;
+			chip->chip.to_irq = s5p_gpiolib_gpioint_to_irq;
 			s5p_gpioint_add(chip, gpioint_group++);
 		}
 	}
diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
index 166725f..f4ac81f 100644
--- a/arch/arm/mach-s5pv210/gpiolib.c
+++ b/arch/arm/mach-s5pv210/gpiolib.c
@@ -258,6 +258,7 @@ static __init int s5pv210_gpiolib_init(void)
 			chip->config = &gpio_cfg;
 
 			/* gpio interrupts */
+			chip->chip.to_irq = s5p_gpiolib_gpioint_to_irq;
 			s5p_gpioint_add(chip, gpioint_group++);
 		}
 		if (chip->base == NULL)
diff --git a/arch/arm/plat-s5p/gpiolib.c b/arch/arm/plat-s5p/gpiolib.c
index 0c27a9d..dcd1ee4 100644
--- a/arch/arm/plat-s5p/gpiolib.c
+++ b/arch/arm/plat-s5p/gpiolib.c
@@ -33,3 +33,10 @@ int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset)
 		return -EINVAL;
 	}
 }
+
+/* be called from gpio_to_irq() for gpio interrupts */
+int s5p_gpiolib_gpioint_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+	return S5P_IRQ_GPIOINT(chip->base + offset);
+}
+
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index a6b844c..d484aaf 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -122,6 +122,8 @@ extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
 extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
 
 extern int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset);
+extern int s5p_gpiolib_gpioint_to_irq(struct gpio_chip *chip,
+		unsigned int offset);
 
 extern void s5p_gpioint_add(struct s3c_gpio_chip *chip, int group);
 
-- 
1.7.0.4



From bill_carson at 126.com  Thu Jun  3 01:39:04 2010
From: bill_carson at 126.com (rocky)
Date: Thu, 3 Jun 2010 13:39:04 +0800 (CST)
Subject: Query about arch/arm/boot/compressed/Makefile.debug
Message-ID: <198ace.57aa.128fc51e27e.Coremail.bill_carson@126.com>

Hi, all
I'm porting Linux to a ARM1176 based SOC, sometimes after running make zImage, 
I got CRC error when uncompressing the kernel all the time.

no idea why this should happened, i want to use misc.c with STANDALONE_DEBUG mode, 
so how should i use this debug mode?


thanks 
BR
rocky




From ben-linux at fluff.org  Thu Jun  3 01:43:23 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Thu, 3 Jun 2010 06:43:23 +0100
Subject: [PATCH 2/7] ARM: S5P: Add GPIOlib gpio_to_irq for external
	interrupts
In-Reply-To: <1275541299-25566-2-git-send-email-jy0922.shim@samsung.com>
References: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
	<1275541299-25566-2-git-send-email-jy0922.shim@samsung.com>
Message-ID: <20100603054323.GZ4720@trinity.fluff.org>

On Thu, Jun 03, 2010 at 02:01:34PM +0900, Joonyoung Shim wrote:
> This patch is to support gpio_to_irq() of GPIOlib for external
> interrupts. The gpio_to_irq() calls s5p_gpiolib_eint_to_irq function.

How about each s3c_gpio_chip have a irq base in it?
 
> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/plat-s5p/Makefile                     |    1 +
>  arch/arm/plat-s5p/gpiolib.c                    |   35 ++++++++++++++++++++++++
>  arch/arm/plat-samsung/include/plat/gpio-core.h |    2 +
>  3 files changed, 38 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/plat-s5p/gpiolib.c
> 
> diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
> index 39c242b..f6e1a13 100644
> --- a/arch/arm/plat-s5p/Makefile
> +++ b/arch/arm/plat-s5p/Makefile
> @@ -15,6 +15,7 @@ obj-				:=
>  obj-y				+= dev-uart.o
>  obj-y				+= cpu.o
>  obj-y				+= clock.o
> +obj-y				+= gpiolib.o
>  obj-y				+= irq.o
>  obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
>  
> diff --git a/arch/arm/plat-s5p/gpiolib.c b/arch/arm/plat-s5p/gpiolib.c
> new file mode 100644
> index 0000000..0c27a9d
> --- /dev/null
> +++ b/arch/arm/plat-s5p/gpiolib.c
> @@ -0,0 +1,35 @@
> +/*
> + * linux/arch/arm/plat-s5p/gpiolib.c
> + *
> + * Copyright (C) 2010 Samsung Electronics Co.Ltd
> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
> + *
> + * S5P - GPIOlib support
> + *
> + *  This program is free software; you can redistribute  it and/or modify it
> + *  under  the terms of  the GNU General  Public License as published by the
> + *  Free Software Foundation;  either version 2 of the  License, or (at your
> + *  option) any later version.
> + *
> + */
> +
> +#include <linux/gpio.h>
> +#include <mach/irqs.h>
> +#include <mach/regs-gpio.h>
> +
> +/* be called from gpio_to_irq() for external interrupts */
> +int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset)
> +{
> +	switch (chip->base) {
> +	case EINT_GPIO_0(0):
> +		return IRQ_EINT(offset);
> +	case EINT_GPIO_1(0):
> +		return IRQ_EINT(8 + offset);
> +	case EINT_GPIO_2(0):
> +		return IRQ_EINT(16 + offset);
> +	case EINT_GPIO_3(0):
> +		return IRQ_EINT(24 + offset);
> +	default:
> +		return -EINVAL;
> +	}
> +}
> diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
> index e358c7d..f6c5151 100644
> --- a/arch/arm/plat-samsung/include/plat/gpio-core.h
> +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
> @@ -121,6 +121,8 @@ extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
>  /* exported for core SoC support to change */
>  extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
>  
> +extern int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset);
> +
>  #ifdef CONFIG_S3C_GPIO_TRACK
>  extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
>  
> -- 
> 1.7.0.4
> 

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From eric.y.miao at gmail.com  Thu Jun  3 01:47:00 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Thu, 3 Jun 2010 13:47:00 +0800
Subject: Query about arch/arm/boot/compressed/Makefile.debug
In-Reply-To: <198ace.57aa.128fc51e27e.Coremail.bill_carson@126.com>
References: <198ace.57aa.128fc51e27e.Coremail.bill_carson@126.com>
Message-ID: <AANLkTinEA_7sFG9WqzETirCY76XIIeicKe3Cw9eQvYwx@mail.gmail.com>

On Thu, Jun 3, 2010 at 1:39 PM, rocky <bill_carson at 126.com> wrote:
> Hi, all
> I'm porting Linux to a ARM1176 based SOC, sometimes after running make zImage,
> I got CRC error when uncompressing the kernel all the time.

Conduct a strict memory checking and check the cache enabling code, normally
that's where the problem is. The decompressor itself, should be less problematic
since it's working elsewhere on most other platforms.

>
> no idea why this should happened, i want to use misc.c with STANDALONE_DEBUG mode,
> so how should i use this debug mode?
>
>
> thanks
> BR
> rocky
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From bill_carson at 126.com  Thu Jun  3 01:55:42 2010
From: bill_carson at 126.com (rocky)
Date: Thu, 3 Jun 2010 13:55:42 +0800 (CST)
Subject: Query about arch/arm/boot/compressed/Makefile.debug
In-Reply-To: <AANLkTinEA_7sFG9WqzETirCY76XIIeicKe3Cw9eQvYwx@mail.gmail.com>
References: <AANLkTinEA_7sFG9WqzETirCY76XIIeicKe3Cw9eQvYwx@mail.gmail.com>
	<198ace.57aa.128fc51e27e.Coremail.bill_carson@126.com>
Message-ID: <13ff02f.5b3c.128fc611d48.Coremail.bill_carson@126.com>

Hi, Eric

>Conduct?a?strict?memory?checking?and?check?the?cache?enabling?code,?normally
>that's?where?the?problem?is.?The?decompressor?itself,?should?be?less?problematic
>since?it's?working?elsewhere?on?most?other?platforms.

All ARM1176 based SoC share the same cache enable/disable API which defined in arch/arm/boot/compressed/head.S, ARM1176 falls into ARMv7 .

Actually, our DDR run at 800MHz, I'm trying to tune it a little bit lower at 533MHz to see what happened.

thanks for your kind tips.

rocky










?2010-06-03?13:47:00?"Eric?Miao"?<eric.y.miao at gmail.com>????>On?Thu,?Jun?3,?2010?at?1:39?PM,?rocky?<bill_carson at 126.com>?wrote:>>?Hi,?all>>?I'm?porting?Linux?to?a?ARM1176?based?SOC,?sometimes?after?running?make?zImage,>>?I?got?CRC?error?when?uncompressing?the?kernel?all?the?time.>>Conduct?a?strict?memory?checking?and?check?the?cache?enabling?code,?normally>that's?where?the?problem?is.?The?decompressor?itself,?should?be?less?problematic>since?it's?working?elsewhere?on?most?other?platforms.>>>>>?no?idea?why?this?should?happened,?i?want?to?use?misc.c?with?STANDALONE_DEBUG?mode,>>?so?how?should?i?use?this?debug?mode?>>>>>>?thanks>>?BR>>?rocky>>>>>>>>?_______________________________________________>>?linux-arm-kernel?mailing?list>>?linux-arm-kernel at lists.infradead.org>>?http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>>


From jy0922.shim at samsung.com  Thu Jun  3 01:57:03 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 03 Jun 2010 14:57:03 +0900
Subject: [PATCH] i2c: Enable i2c-s3c2410 for S5P cpus
Message-ID: <1275544623-5425-1-git-send-email-jy0922.shim@samsung.com>

This i2c controller driver can be used on the S5P series processors too,
so enable the driver in Konfig for those platforms.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/i2c/busses/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 87ab056..4765d62 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -503,7 +503,7 @@ config I2C_PXA_SLAVE
 
 config I2C_S3C2410
 	tristate "S3C2410 I2C Driver"
-	depends on ARCH_S3C2410 || ARCH_S3C64XX
+	depends on ARCH_S3C2410 || ARCH_S3C64XX || PLAT_S5P
 	help
 	  Say Y here to include support for I2C controller in the
 	  Samsung S3C2410 based System-on-Chip devices.
-- 
1.7.0.4



From jy0922.shim at samsung.com  Thu Jun  3 02:14:53 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 03 Jun 2010 15:14:53 +0900
Subject: [PATCH 2/7] ARM: S5P: Add GPIOlib gpio_to_irq for external
	interrupts
In-Reply-To: <20100603054323.GZ4720@trinity.fluff.org>
References: <1275541299-25566-1-git-send-email-jy0922.shim@samsung.com>
	<1275541299-25566-2-git-send-email-jy0922.shim@samsung.com>
	<20100603054323.GZ4720@trinity.fluff.org>
Message-ID: <4C07485D.2020808@samsung.com>

On 6/3/2010 2:43 PM, Ben Dooks wrote:
> On Thu, Jun 03, 2010 at 02:01:34PM +0900, Joonyoung Shim wrote:
>> This patch is to support gpio_to_irq() of GPIOlib for external
>> interrupts. The gpio_to_irq() calls s5p_gpiolib_eint_to_irq function.
> 
> How about each s3c_gpio_chip have a irq base in it?
>  

Good, then it can be arch and irq type(gpio, external)independent codes.

>> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>> ---
>>  arch/arm/plat-s5p/Makefile                     |    1 +
>>  arch/arm/plat-s5p/gpiolib.c                    |   35 ++++++++++++++++++++++++
>>  arch/arm/plat-samsung/include/plat/gpio-core.h |    2 +
>>  3 files changed, 38 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/plat-s5p/gpiolib.c
>>
>> diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
>> index 39c242b..f6e1a13 100644
>> --- a/arch/arm/plat-s5p/Makefile
>> +++ b/arch/arm/plat-s5p/Makefile
>> @@ -15,6 +15,7 @@ obj-				:=
>>  obj-y				+= dev-uart.o
>>  obj-y				+= cpu.o
>>  obj-y				+= clock.o
>> +obj-y				+= gpiolib.o
>>  obj-y				+= irq.o
>>  obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
>>  
>> diff --git a/arch/arm/plat-s5p/gpiolib.c b/arch/arm/plat-s5p/gpiolib.c
>> new file mode 100644
>> index 0000000..0c27a9d
>> --- /dev/null
>> +++ b/arch/arm/plat-s5p/gpiolib.c
>> @@ -0,0 +1,35 @@
>> +/*
>> + * linux/arch/arm/plat-s5p/gpiolib.c
>> + *
>> + * Copyright (C) 2010 Samsung Electronics Co.Ltd
>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>> + *
>> + * S5P - GPIOlib support
>> + *
>> + *  This program is free software; you can redistribute  it and/or modify it
>> + *  under  the terms of  the GNU General  Public License as published by the
>> + *  Free Software Foundation;  either version 2 of the  License, or (at your
>> + *  option) any later version.
>> + *
>> + */
>> +
>> +#include <linux/gpio.h>
>> +#include <mach/irqs.h>
>> +#include <mach/regs-gpio.h>
>> +
>> +/* be called from gpio_to_irq() for external interrupts */
>> +int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset)
>> +{
>> +	switch (chip->base) {
>> +	case EINT_GPIO_0(0):
>> +		return IRQ_EINT(offset);
>> +	case EINT_GPIO_1(0):
>> +		return IRQ_EINT(8 + offset);
>> +	case EINT_GPIO_2(0):
>> +		return IRQ_EINT(16 + offset);
>> +	case EINT_GPIO_3(0):
>> +		return IRQ_EINT(24 + offset);
>> +	default:
>> +		return -EINVAL;
>> +	}
>> +}
>> diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
>> index e358c7d..f6c5151 100644
>> --- a/arch/arm/plat-samsung/include/plat/gpio-core.h
>> +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
>> @@ -121,6 +121,8 @@ extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
>>  /* exported for core SoC support to change */
>>  extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
>>  
>> +extern int s5p_gpiolib_eint_to_irq(struct gpio_chip *chip, unsigned int offset);
>> +
>>  #ifdef CONFIG_S3C_GPIO_TRACK
>>  extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
>>  
>> -- 
>> 1.7.0.4
>>
> 



From Hiroshi.DOYU at nokia.com  Thu Jun  3 02:34:18 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu,  3 Jun 2010 09:34:18 +0300
Subject: [PATCH 10/10] omap mailbox: Set a device in logical mbox instance for
	traceability
In-Reply-To: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
Message-ID: <1275546858-29507-11-git-send-email-Hiroshi.DOYU@nokia.com>

From: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>

With this patch, you'll get the following sysfs directories. This
structure implies that a single platform device, "omap2-mailbox" holds
multiple logical mbox instances. This could be the base to add sysfs
files for each logical mboxes. Then userland application can access a
mbox through sysfs entries if necessary(ex: setting kfifo size
dynamically)

  ~# tree -d -L 2 /sys/devices/platform/omap2-mailbox/
  /sys/devices/platform/omap2-mailbox/
  |-- driver -> ../../../bus/platform/drivers/omap2-mailbox
  |-- mbox
  |   |-- dsp      <- they are each instances of logical mailbox.
  |   |-- ducati
  |   |-- iva2
  |   |-- mbox01
  |   |-- mbox02
  |   |-- mbox03
  |   |-- .....
  |   `-- tesla
  |-- power
  `-- subsystem -> ../../../bus/platform

This was wrongly dropped by:
     commit c7c158e57bce6220644f2bcd65d82e1468aa40ec

Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/plat-omap/mailbox.c |   17 ++++++++++++++++-
 1 files changed, 16 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index ec0e159..87e0cde 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -347,6 +347,8 @@ void omap_mbox_put(struct omap_mbox *mbox)
 }
 EXPORT_SYMBOL(omap_mbox_put);
 
+static struct class omap_mbox_class = { .name = "mbox", };
+
 int omap_mbox_register(struct device *parent, struct omap_mbox *mbox)
 {
 	int ret = 0;
@@ -357,6 +359,11 @@ int omap_mbox_register(struct device *parent, struct omap_mbox *mbox)
 	if (mbox->next)
 		return -EBUSY;
 
+	mbox->dev = device_create(&omap_mbox_class,
+				  parent, 0, mbox, "%s", mbox->name);
+	if (IS_ERR(mbox->dev))
+		return PTR_ERR(mbox->dev);
+
 	spin_lock(&mboxes_lock);
 	tmp = find_mboxes(mbox->name);
 	if (*tmp) {
@@ -385,6 +392,7 @@ int omap_mbox_unregister(struct omap_mbox *mbox)
 			*tmp = mbox->next;
 			mbox->next = NULL;
 			spin_unlock(&mboxes_lock);
+			device_unregister(mbox->dev);
 			return 0;
 		}
 		tmp = &(*tmp)->next;
@@ -397,6 +405,12 @@ EXPORT_SYMBOL(omap_mbox_unregister);
 
 static int __init omap_mbox_init(void)
 {
+	int err;
+
+	err = class_register(&omap_mbox_class);
+	if (err)
+		return err;
+
 	mboxd = create_workqueue("mboxd");
 	if (!mboxd)
 		return -ENOMEM;
@@ -407,11 +421,12 @@ static int __init omap_mbox_init(void)
 
 	return 0;
 }
-module_init(omap_mbox_init);
+subsys_initcall(omap_mbox_init);
 
 static void __exit omap_mbox_exit(void)
 {
 	destroy_workqueue(mboxd);
+	class_unregister(&omap_mbox_class);
 }
 module_exit(omap_mbox_exit);
 
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Thu Jun  3 02:34:15 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu,  3 Jun 2010 09:34:15 +0300
Subject: [PATCH 07/10] omap: mailbox cleanup: split MODULE_AUTHOR line
In-Reply-To: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
Message-ID: <1275546858-29507-8-git-send-email-Hiroshi.DOYU@nokia.com>

From: Ohad Ben-Cohen <ohad at wizery.com>

use multiple MODULE_AUTHOR lines for multiple authors

Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/mach-omap2/mailbox.c |    3 ++-
 arch/arm/plat-omap/mailbox.c  |    3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 318f363..763272c 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -486,5 +486,6 @@ module_exit(omap2_mbox_exit);
 
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
-MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU at nokia.com>, Paul Mundt");
+MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU at nokia.com>");
+MODULE_AUTHOR("Paul Mundt");
 MODULE_ALIAS("platform:"DRV_NAME);
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index fafe47b..66c6e87 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -430,4 +430,5 @@ module_exit(omap_mbox_exit);
 
 MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("omap mailbox: interrupt driven messaging");
-MODULE_AUTHOR("Toshihiro Kobayashi and Hiroshi DOYU");
+MODULE_AUTHOR("Toshihiro Kobayashi");
+MODULE_AUTHOR("Hiroshi DOYU");
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Thu Jun  3 02:34:10 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu,  3 Jun 2010 09:34:10 +0300
Subject: [PATCH 02/10] Mailbox: flush pending deferred works before freeing
	blk queue
In-Reply-To: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
Message-ID: <1275546858-29507-3-git-send-email-Hiroshi.DOYU@nokia.com>

From: Fernando Guzman Lugo <x0095840 at ti.com>

flush pending deferred works before freeing blk_queue to prevent
any attempt of access to blk_queue after it was freed

Signed-off-by: Fernando Guzman Lugo <x0095840 at ti.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/plat-omap/mailbox.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 252a586..77c23f5 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -299,6 +299,8 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
 static void omap_mbox_fini(struct omap_mbox *mbox)
 {
 	free_irq(mbox->irq, mbox);
+	tasklet_kill(&mbox->txq->tasklet);
+	flush_work(&mbox->rxq->work);
 	mbox_queue_free(mbox->txq);
 	mbox_queue_free(mbox->rxq);
 
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Thu Jun  3 02:34:11 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu,  3 Jun 2010 09:34:11 +0300
Subject: [PATCH 03/10] Mailbox: Check valid registered callback before calling
In-Reply-To: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
Message-ID: <1275546858-29507-4-git-send-email-Hiroshi.DOYU@nokia.com>

From: Fernando Guzman Lugo <x0095840 at ti.com>

This patch checks if the mailbox user has assinged a valid
callback fuction before calling it.

Signed-off-by: Fernando Guzman Lugo <x0095840 at ti.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/plat-omap/mailbox.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 77c23f5..72efbe5 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -146,7 +146,8 @@ static void mbox_rx_work(struct work_struct *work)
 
 		msg = (mbox_msg_t)rq->special;
 		blk_end_request_all(rq, 0);
-		mbox->rxq->callback((void *)msg);
+		if (mbox->rxq->callback)
+			mbox->rxq->callback((void *)msg);
 	}
 }
 
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Thu Jun  3 02:34:12 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu,  3 Jun 2010 09:34:12 +0300
Subject: [PATCH 04/10] Mailbox: new mutext lock for h/w mailbox configuration
In-Reply-To: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
Message-ID: <1275546858-29507-5-git-send-email-Hiroshi.DOYU@nokia.com>

mailbox startup and shutdown are being executed against
a single H/W module, and a mailbox H/W module is totally
__independent__ of the registration of logical mailboxes.
So, an independent mutext should be used for startup and
shutdown.

Signed-off-by: Fernando Guzman Lugo <x0095840 at ti.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/plat-omap/mailbox.c |   11 ++++++-----
 1 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 72efbe5..986002b 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -34,6 +34,7 @@ static struct omap_mbox *mboxes;
 static DEFINE_RWLOCK(mboxes_lock);
 
 static int mbox_configured;
+static DEFINE_MUTEX(mbox_configured_lock);
 
 /* Mailbox FIFO handle functions */
 static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
@@ -250,16 +251,16 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
 	struct omap_mbox_queue *mq;
 
 	if (likely(mbox->ops->startup)) {
-		write_lock(&mboxes_lock);
+		mutex_lock(&mbox_configured_lock);
 		if (!mbox_configured)
 			ret = mbox->ops->startup(mbox);
 
 		if (unlikely(ret)) {
-			write_unlock(&mboxes_lock);
+			mutex_unlock(&mbox_configured_lock);
 			return ret;
 		}
 		mbox_configured++;
-		write_unlock(&mboxes_lock);
+		mutex_unlock(&mbox_configured_lock);
 	}
 
 	ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
@@ -306,12 +307,12 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
 	mbox_queue_free(mbox->rxq);
 
 	if (unlikely(mbox->ops->shutdown)) {
-		write_lock(&mboxes_lock);
+		mutex_lock(&mbox_configured_lock);
 		if (mbox_configured > 0)
 			mbox_configured--;
 		if (!mbox_configured)
 			mbox->ops->shutdown(mbox);
-		write_unlock(&mboxes_lock);
+		mutex_unlock(&mbox_configured_lock);
 	}
 }
 
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Thu Jun  3 02:34:17 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu,  3 Jun 2010 09:34:17 +0300
Subject: [PATCH 09/10] omap: mailbox: convert block api to kfifo
In-Reply-To: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
Message-ID: <1275546858-29507-10-git-send-email-Hiroshi.DOYU@nokia.com>

From: Ohad Ben-Cohen <ohad at wizery.com>

The underlying buffering implementation of mailbox
is converted from block API to kfifo due to the simplicity
and speed of kfifo.

The default size of the kfifo buffer is set to 256 bytes.
This value is configurable at compile time (via
CONFIG_OMAP_MBOX_KFIFO_SIZE), and can be changed at
runtime (via the mbox_kfifo_size module parameter).

Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
Signed-off-by: Hari Kanigeri <h-kanigeri2 at ti.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/plat-omap/Kconfig                |    9 ++
 arch/arm/plat-omap/include/plat/mailbox.h |    4 +-
 arch/arm/plat-omap/mailbox.c              |  119 +++++++++++++----------------
 3 files changed, 64 insertions(+), 68 deletions(-)

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 78b49a6..111d39a 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -106,6 +106,15 @@ config OMAP_MBOX_FWK
 	  Say Y here if you want to use OMAP Mailbox framework support for
 	  DSP, IVA1.0 and IVA2 in OMAP1/2/3.
 
+config OMAP_MBOX_KFIFO_SIZE
+	int "Mailbox kfifo default buffer size (bytes)"
+	depends on OMAP_MBOX_FWK
+	default 256
+	help
+	  Specify the default size of mailbox's kfifo buffers (bytes).
+	  This can also be changed at runtime (via the mbox_kfifo_size
+	  module parameter).
+
 config OMAP_IOMMU
 	tristate
 
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index 729166b..0c3c4a5 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -5,8 +5,8 @@
 
 #include <linux/wait.h>
 #include <linux/workqueue.h>
-#include <linux/blkdev.h>
 #include <linux/interrupt.h>
+#include <linux/kfifo.h>
 
 typedef u32 mbox_msg_t;
 struct omap_mbox;
@@ -42,7 +42,7 @@ struct omap_mbox_ops {
 
 struct omap_mbox_queue {
 	spinlock_t		lock;
-	struct request_queue	*queue;
+	struct kfifo		fifo;
 	struct work_struct	work;
 	struct tasklet_struct	tasklet;
 	int	(*callback)(void *);
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 81076b5..ec0e159 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -21,11 +21,14 @@
  *
  */
 
+#include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
 #include <linux/device.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
+#include <linux/kfifo.h>
+#include <linux/err.h>
 
 #include <plat/mailbox.h>
 
@@ -37,6 +40,10 @@ static bool rq_full;
 static int mbox_configured;
 static DEFINE_MUTEX(mbox_configured_lock);
 
+static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
+module_param(mbox_kfifo_size, uint, S_IRUGO);
+MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo (bytes)");
+
 /* Mailbox FIFO handle functions */
 static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
 {
@@ -69,7 +76,7 @@ static inline int is_mbox_irq(struct omap_mbox *mbox, omap_mbox_irq_t irq)
 /*
  * message sender
  */
-static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
+static int __mbox_poll_for_space(struct omap_mbox *mbox)
 {
 	int ret = 0, i = 1000;
 
@@ -80,49 +87,50 @@ static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
 			return -1;
 		udelay(1);
 	}
-	mbox_fifo_write(mbox, msg);
 	return ret;
 }
 
-
 int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
 {
+	struct omap_mbox_queue *mq = mbox->txq;
+	int ret = 0, len;
 
-	struct request *rq;
-	struct request_queue *q = mbox->txq->queue;
+	spin_lock(&mq->lock);
 
-	rq = blk_get_request(q, WRITE, GFP_ATOMIC);
-	if (unlikely(!rq))
-		return -ENOMEM;
+	if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
+	WARN_ON(len != sizeof(msg));
 
-	blk_insert_request(q, rq, 0, (void *) msg);
 	tasklet_schedule(&mbox->txq->tasklet);
 
-	return 0;
+out:
+	spin_unlock(&mq->lock);
+	return ret;
 }
 EXPORT_SYMBOL(omap_mbox_msg_send);
 
 static void mbox_tx_tasklet(unsigned long tx_data)
 {
-	int ret;
-	struct request *rq;
 	struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
-	struct request_queue *q = mbox->txq->queue;
-
-	while (1) {
-
-		rq = blk_fetch_request(q);
-
-		if (!rq)
-			break;
+	struct omap_mbox_queue *mq = mbox->txq;
+	mbox_msg_t msg;
+	int ret;
 
-		ret = __mbox_msg_send(mbox, (mbox_msg_t)rq->special);
-		if (ret) {
+	while (kfifo_len(&mq->fifo)) {
+		if (__mbox_poll_for_space(mbox)) {
 			omap_mbox_enable_irq(mbox, IRQ_TX);
-			blk_requeue_request(q, rq);
-			return;
+			break;
 		}
-		blk_end_request_all(rq, 0);
+
+		ret = kfifo_out(&mq->fifo, (unsigned char *)&msg,
+								sizeof(msg));
+		WARN_ON(ret != sizeof(msg));
+
+		mbox_fifo_write(mbox, msg);
 	}
 }
 
@@ -133,41 +141,21 @@ static void mbox_rx_work(struct work_struct *work)
 {
 	struct omap_mbox_queue *mq =
 			container_of(work, struct omap_mbox_queue, work);
-	struct omap_mbox *mbox = mq->queue->queuedata;
-	struct request_queue *q = mbox->rxq->queue;
-	struct request *rq;
 	mbox_msg_t msg;
-	unsigned long flags;
-
-	while (1) {
-		spin_lock_irqsave(q->queue_lock, flags);
-		rq = blk_fetch_request(q);
-		if (rq_full) {
-			omap_mbox_enable_irq(mbox, IRQ_RX);
-			rq_full = false;
-		}
-		spin_unlock_irqrestore(q->queue_lock, flags);
-		if (!rq)
-			break;
+	int len;
+
+	while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
+		len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
+		WARN_ON(len != sizeof(msg));
 
-		msg = (mbox_msg_t)rq->special;
-		blk_end_request_all(rq, 0);
-		if (mbox->rxq->callback)
-			mbox->rxq->callback((void *)msg);
+		if (mq->callback)
+			mq->callback((void *)msg);
 	}
 }
 
 /*
  * Mailbox interrupt handler
  */
-static void mbox_txq_fn(struct request_queue *q)
-{
-}
-
-static void mbox_rxq_fn(struct request_queue *q)
-{
-}
-
 static void __mbox_tx_interrupt(struct omap_mbox *mbox)
 {
 	omap_mbox_disable_irq(mbox, IRQ_TX);
@@ -177,13 +165,12 @@ static void __mbox_tx_interrupt(struct omap_mbox *mbox)
 
 static void __mbox_rx_interrupt(struct omap_mbox *mbox)
 {
-	struct request *rq;
+	struct omap_mbox_queue *mq = mbox->rxq;
 	mbox_msg_t msg;
-	struct request_queue *q = mbox->rxq->queue;
+	int len;
 
 	while (!mbox_fifo_empty(mbox)) {
-		rq = blk_get_request(q, WRITE, GFP_ATOMIC);
-		if (unlikely(!rq)) {
+		if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
 			omap_mbox_disable_irq(mbox, IRQ_RX);
 			rq_full = true;
 			goto nomem;
@@ -191,8 +178,9 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
 
 		msg = mbox_fifo_read(mbox);
 
+		len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
+		WARN_ON(len != sizeof(msg));
 
-		blk_insert_request(q, rq, 0, (void *)msg);
 		if (mbox->ops->type == OMAP_MBOX_TYPE1)
 			break;
 	}
@@ -217,11 +205,9 @@ static irqreturn_t mbox_interrupt(int irq, void *p)
 }
 
 static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
-					request_fn_proc *proc,
 					void (*work) (struct work_struct *),
 					void (*tasklet)(unsigned long))
 {
-	struct request_queue *q;
 	struct omap_mbox_queue *mq;
 
 	mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
@@ -230,11 +216,8 @@ static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
 
 	spin_lock_init(&mq->lock);
 
-	q = blk_init_queue(proc, &mq->lock);
-	if (!q)
+	if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
 		goto error;
-	q->queuedata = mbox;
-	mq->queue = q;
 
 	if (work)
 		INIT_WORK(&mq->work, work);
@@ -249,7 +232,7 @@ error:
 
 static void mbox_queue_free(struct omap_mbox_queue *q)
 {
-	blk_cleanup_queue(q->queue);
+	kfifo_free(&q->fifo);
 	kfree(q);
 }
 
@@ -279,14 +262,14 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
 		goto fail_request_irq;
 	}
 
-	mq = mbox_queue_alloc(mbox, mbox_txq_fn, NULL, mbox_tx_tasklet);
+	mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
 	if (!mq) {
 		ret = -ENOMEM;
 		goto fail_alloc_txq;
 	}
 	mbox->txq = mq;
 
-	mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work, NULL);
+	mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
 	if (!mq) {
 		ret = -ENOMEM;
 		goto fail_alloc_rxq;
@@ -418,6 +401,10 @@ static int __init omap_mbox_init(void)
 	if (!mboxd)
 		return -ENOMEM;
 
+	/* kfifo size sanity check: alignment and minimal size */
+	mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
+	mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size, sizeof(mbox_msg_t));
+
 	return 0;
 }
 module_init(omap_mbox_init);
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Thu Jun  3 02:34:09 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu,  3 Jun 2010 09:34:09 +0300
Subject: [PATCH 01/10] Mailbox: free mailbox interrupt before freeing blk queue
In-Reply-To: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
Message-ID: <1275546858-29507-2-git-send-email-Hiroshi.DOYU@nokia.com>

From: Fernando Guzman Lugo <x0095840 at ti.com>

Free interrupt before freeing blk_queue to avoid
any attempt of access to blk_queue after it was freed.

Signed-off-by: Fernando Guzman Lugo <x0095840 at ti.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/plat-omap/mailbox.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 08a2df7..252a586 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -298,11 +298,10 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
 
 static void omap_mbox_fini(struct omap_mbox *mbox)
 {
+	free_irq(mbox->irq, mbox);
 	mbox_queue_free(mbox->txq);
 	mbox_queue_free(mbox->rxq);
 
-	free_irq(mbox->irq, mbox);
-
 	if (unlikely(mbox->ops->shutdown)) {
 		write_lock(&mboxes_lock);
 		if (mbox_configured > 0)
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Thu Jun  3 02:34:14 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu,  3 Jun 2010 09:34:14 +0300
Subject: [PATCH 06/10] omap: mailbox: convert rwlocks to spinlock
In-Reply-To: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
Message-ID: <1275546858-29507-7-git-send-email-Hiroshi.DOYU@nokia.com>

From: Ohad Ben-Cohen <ohad at wizery.com>

rwlocks are slower and have potential starvation issues
therefore spinlocks are generally preferred.

see also: http://lwn.net/Articles/364583/

Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
Signed-off-by: Kanigeri Hari <h-kanigeri2 at ti.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/plat-omap/mailbox.c |   20 ++++++++++----------
 1 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index c340216..fafe47b 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -31,7 +31,7 @@
 
 static struct workqueue_struct *mboxd;
 static struct omap_mbox *mboxes;
-static DEFINE_RWLOCK(mboxes_lock);
+static DEFINE_SPINLOCK(mboxes_lock);
 static bool rq_full;
 
 static int mbox_configured;
@@ -341,14 +341,14 @@ struct omap_mbox *omap_mbox_get(const char *name)
 	struct omap_mbox *mbox;
 	int ret;
 
-	read_lock(&mboxes_lock);
+	spin_lock(&mboxes_lock);
 	mbox = *(find_mboxes(name));
 	if (mbox == NULL) {
-		read_unlock(&mboxes_lock);
+		spin_unlock(&mboxes_lock);
 		return ERR_PTR(-ENOENT);
 	}
 
-	read_unlock(&mboxes_lock);
+	spin_unlock(&mboxes_lock);
 
 	ret = omap_mbox_startup(mbox);
 	if (ret)
@@ -374,15 +374,15 @@ int omap_mbox_register(struct device *parent, struct omap_mbox *mbox)
 	if (mbox->next)
 		return -EBUSY;
 
-	write_lock(&mboxes_lock);
+	spin_lock(&mboxes_lock);
 	tmp = find_mboxes(mbox->name);
 	if (*tmp) {
 		ret = -EBUSY;
-		write_unlock(&mboxes_lock);
+		spin_unlock(&mboxes_lock);
 		goto err_find;
 	}
 	*tmp = mbox;
-	write_unlock(&mboxes_lock);
+	spin_unlock(&mboxes_lock);
 
 	return 0;
 
@@ -395,18 +395,18 @@ int omap_mbox_unregister(struct omap_mbox *mbox)
 {
 	struct omap_mbox **tmp;
 
-	write_lock(&mboxes_lock);
+	spin_lock(&mboxes_lock);
 	tmp = &mboxes;
 	while (*tmp) {
 		if (mbox == *tmp) {
 			*tmp = mbox->next;
 			mbox->next = NULL;
-			write_unlock(&mboxes_lock);
+			spin_unlock(&mboxes_lock);
 			return 0;
 		}
 		tmp = &(*tmp)->next;
 	}
-	write_unlock(&mboxes_lock);
+	spin_unlock(&mboxes_lock);
 
 	return -EINVAL;
 }
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Thu Jun  3 02:34:16 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu,  3 Jun 2010 09:34:16 +0300
Subject: [PATCH 08/10] omap: mailbox: remove (un)likely macros from cold paths
In-Reply-To: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
Message-ID: <1275546858-29507-9-git-send-email-Hiroshi.DOYU@nokia.com>

From: Ohad Ben-Cohen <ohad at wizery.com>

Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/plat-omap/mailbox.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 66c6e87..81076b5 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -258,12 +258,12 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
 	int ret = 0;
 	struct omap_mbox_queue *mq;
 
-	if (likely(mbox->ops->startup)) {
+	if (mbox->ops->startup) {
 		mutex_lock(&mbox_configured_lock);
 		if (!mbox_configured)
 			ret = mbox->ops->startup(mbox);
 
-		if (unlikely(ret)) {
+		if (ret) {
 			mutex_unlock(&mbox_configured_lock);
 			return ret;
 		}
@@ -273,7 +273,7 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
 
 	ret = request_irq(mbox->irq, mbox_interrupt, IRQF_SHARED,
 				mbox->name, mbox);
-	if (unlikely(ret)) {
+	if (ret) {
 		printk(KERN_ERR
 			"failed to register mailbox interrupt:%d\n", ret);
 		goto fail_request_irq;
@@ -300,7 +300,7 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
  fail_alloc_txq:
 	free_irq(mbox->irq, mbox);
  fail_request_irq:
-	if (unlikely(mbox->ops->shutdown))
+	if (mbox->ops->shutdown)
 		mbox->ops->shutdown(mbox);
 
 	return ret;
@@ -314,7 +314,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
 	mbox_queue_free(mbox->txq);
 	mbox_queue_free(mbox->rxq);
 
-	if (unlikely(mbox->ops->shutdown)) {
+	if (mbox->ops->shutdown) {
 		mutex_lock(&mbox_configured_lock);
 		if (mbox_configured > 0)
 			mbox_configured--;
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Thu Jun  3 02:34:13 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu,  3 Jun 2010 09:34:13 +0300
Subject: [PATCH 05/10] Mailbox: disable mailbox interrupt when request queue
In-Reply-To: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
Message-ID: <1275546858-29507-6-git-send-email-Hiroshi.DOYU@nokia.com>

From: Fernando Guzman Lugo <x0095840 at ti.com>

when blk_get_request fails to get the request it is returning
without read the message from the mailbox fifo, then when it
leaves the isr and interruption is trigger again and again and
the workqueue which get elements from the request queue is never
executed and the kernel is stuck and shows a softlockup message.
Now the mailbox interrupt is disabled when request queue is full
and enabled when it pop a elememt form the request queue.

Signed-off-by: Fernando Guzman Lugo <x0095840 at ti.com>
Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/plat-omap/mailbox.c |   10 +++++++++-
 1 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 986002b..c340216 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -32,6 +32,7 @@
 static struct workqueue_struct *mboxd;
 static struct omap_mbox *mboxes;
 static DEFINE_RWLOCK(mboxes_lock);
+static bool rq_full;
 
 static int mbox_configured;
 static DEFINE_MUTEX(mbox_configured_lock);
@@ -141,6 +142,10 @@ static void mbox_rx_work(struct work_struct *work)
 	while (1) {
 		spin_lock_irqsave(q->queue_lock, flags);
 		rq = blk_fetch_request(q);
+		if (rq_full) {
+			omap_mbox_enable_irq(mbox, IRQ_RX);
+			rq_full = false;
+		}
 		spin_unlock_irqrestore(q->queue_lock, flags);
 		if (!rq)
 			break;
@@ -178,8 +183,11 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
 
 	while (!mbox_fifo_empty(mbox)) {
 		rq = blk_get_request(q, WRITE, GFP_ATOMIC);
-		if (unlikely(!rq))
+		if (unlikely(!rq)) {
+			omap_mbox_disable_irq(mbox, IRQ_RX);
+			rq_full = true;
 			goto nomem;
+		}
 
 		msg = mbox_fifo_read(mbox);
 
-- 
1.7.1.rc1



From Hiroshi.DOYU at nokia.com  Thu Jun  3 02:34:08 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu,  3 Jun 2010 09:34:08 +0300
Subject: [PATCH 00/10] omap mailbox: Paches for -next
Message-ID: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>

Hi,

The following patches are for -next for omap mailbox module.

Fernando Guzman Lugo (4):
  Mailbox: free mailbox interrupt before freeing blk queue
  Mailbox: flush pending deferred works before freeing blk queue
  Mailbox: Check valid registered callback before calling
  Mailbox: disable mailbox interrupt when request queue

Hiroshi DOYU (2):
  Mailbox: new mutext lock for h/w mailbox configuration
  omap mailbox: Set a device in logical mbox instance for traceability

Ohad Ben-Cohen (4):
  omap: mailbox: convert rwlocks to spinlock
  omap: mailbox cleanup: split MODULE_AUTHOR line
  omap: mailbox: remove (un)likely macros from cold paths
  omap: mailbox: convert block api to kfifo

 arch/arm/mach-omap2/mailbox.c             |    3 +-
 arch/arm/plat-omap/Kconfig                |    9 ++
 arch/arm/plat-omap/include/plat/mailbox.h |    4 +-
 arch/arm/plat-omap/mailbox.c              |  182 ++++++++++++++++-------------
 4 files changed, 111 insertions(+), 87 deletions(-)



From Hiroshi.DOYU at nokia.com  Thu Jun  3 02:40:22 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu, 03 Jun 2010 09:40:22 +0300 (EEST)
Subject: [PATCH v3 00/14] omap: mailbox: bunch of cleanups
In-Reply-To: <1274548465-20208-1-git-send-email-felipe.contreras@gmail.com>
References: <1274548465-20208-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <20100603.094022.200375421.Hiroshi.DOYU@nokia.com>

Hi Felipe,

From: ext Felipe Contreras <felipe.contreras at gmail.com>
Subject: [PATCH v3 00/14] omap: mailbox: bunch of cleanups
Date: Sat, 22 May 2010 19:14:11 +0200

> Hi,
> 
> These are hopefully non-functional changes. Just shuffling code around, and
> removing unecessary stuff.
> 
> In v2 I tried to split platform_device and also make mailbox_mach built-in. Not
> any more.
> 
> Comments from Felipe Balbi, Tony Lindgren, Hiroshi DOYU, and Russell King.
> 

Have you had a chance to update them?

> Felipe Contreras (14):
>   omap: mailbox: trivial whitespace cleanups
>   omap: mailbox: trivial cleanups
>   omap: mailbox: reorganize structures
>   omap: mailbox: 2420 should be detected at run-time
>   omap: mailbox: use correct config for omap1
>   omap: mailbox: update omap1 probing
>   omap: mailbox: don't export unecessary symbols
>   omap: mailbox: remove unecessary fields
>   omap: mailbox: add IRQ names
>   omap: mailbox: reorganize registering
>   omap: mailbox: only compile for configured archs
>   omap: mailbox: standarize on 'omap-mailbox'
>   omap: mailbox: simplify omap_mbox_register()
>   omap: mailbox: reorganize headers
> 
>  arch/arm/mach-omap1/devices.c             |   11 +-
>  arch/arm/mach-omap1/mailbox.c             |   52 ++++-----
>  arch/arm/mach-omap2/devices.c             |    6 +-
>  arch/arm/mach-omap2/mailbox.c             |  177 +++++++++++++----------------
>  arch/arm/plat-omap/include/plat/mailbox.h |   16 +--
>  arch/arm/plat-omap/mailbox.c              |  136 +++++++++-------------
>  6 files changed, 168 insertions(+), 230 deletions(-)
> 


From lizf at cn.fujitsu.com  Thu Jun  3 02:53:17 2010
From: lizf at cn.fujitsu.com (Li Zefan)
Date: Thu, 03 Jun 2010 14:53:17 +0800
Subject: [TEMP PATCH v2] Re: make ARM=arm menuconfig problem in mainline
In-Reply-To: <4C07017A.50007@oracle.com>
References: <AANLkTikC61Y9g-WbqwgGDghDSy2XtgraFSRoZYkHRGTG@mail.gmail.com>
	<AANLkTilEYHVHJrj_KgF48OYCSEUcsKLi57Q_Y73d9va-@mail.gmail.com>
	<20100602085748.6771e025.randy.dunlap@oracle.com>
	<AANLkTilpzeYVExQfLgpVmS3bPvb_h3kmWaatidekI-0r@mail.gmail.com>
	<4C068BAA.4030004@oracle.com>
	<20100603002526.GV4720@trinity.fluff.org>
	<4C07017A.50007@oracle.com>
Message-ID: <4C07515D.9030505@cn.fujitsu.com>

Randy Dunlap wrote:
> On 06/02/10 17:25, Ben Dooks wrote:
>> On Wed, Jun 02, 2010 at 09:49:46AM -0700, Randy Dunlap wrote:
>>> On 06/02/10 09:08, Nobin Mathew wrote:
>>>> On Wed, Jun 2, 2010 at 9:27 PM, Randy Dunlap <randy.dunlap at oracle.com> wrote:
>>>>> On Wed, 2 Jun 2010 20:04:28 +0530 Nobin Mathew wrote:
>>>>>
>>>>>> adding linux-arm-kernel at lists.infradead.org
>>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> The following entry creates problem in ARM System type menu. I am
>>>>>> using a Fedora 12 system.
>>>>> What kind of problem does it create?
>>>>> It seems to work for me (on f11, not f12).
>>>>> Does it have something to do with F12 specifically?
>>>>>
>>>>>
>>>>>> Length of bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
>>>>>> S3C2442, S3C2443, S3C2450" is the problem. How can I fix it.
>>>>> Describe the problem, please.
>>> [please don't top-post]
>>
>> I can think of several solutions, the first being to remove the S3C prefix
>> friom all these.
>>
>> S3C24XX is not acceptable, there's S3C series that are either too old to
>> be bothered with, or don't fit under this architecture.
> 
> and not in the current kernel tree?
> I did not find any others in the current tree....
> 
>> how about Samsung S3C: 2410,2412/3,2416,2440/2442,2443,2450
> 
> OK, that works.
> 
> For kbuild/kconfig people:  run:
> make ARCH=arm O=test menuconfig
> 
> and then select System Type & ARM system type.  The kconfig "choice" menu at this
> point looks empty.  It seems to be just a text windowing/display problem.
> Pressing the down/up arrow keys will display the choices, although not where they
> should be displayed in the rectangle, and they can be selected there.
> 

I've found out the cause of this bug, and I'll cook up a patch soon. ;)



From lizf at cn.fujitsu.com  Thu Jun  3 03:24:39 2010
From: lizf at cn.fujitsu.com (Li Zefan)
Date: Thu, 03 Jun 2010 15:24:39 +0800
Subject: [PATCH 1/2] menuconfig: fix to center checklist correctly in a corner
	case
Message-ID: <4C0758B7.5070907@cn.fujitsu.com>

Run:
	make ARCH=arm menuconfig

And then select "System Type" -> "ARM system type". The kconfig
"choice" menu at this point looks empty.

It's because config ARCH_S3C2410 has a long prompt:

config ARCH_S3C2410
        bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
	...

menuconfig centers the checklist according to this prompt without
considering the width of the list, and then things get wrong.

Reported-by: Nobin Mathew <nobin.mathew at gmail.com>
Signed-off-by: Li Zefan <lizf at cn.fujitsu.com>
---

Please queue these 2 patches for 2.6.35.

---
 scripts/kconfig/lxdialog/checklist.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/scripts/kconfig/lxdialog/checklist.c b/scripts/kconfig/lxdialog/checklist.c
index bcc6f19..c92a05a 100644
--- a/scripts/kconfig/lxdialog/checklist.c
+++ b/scripts/kconfig/lxdialog/checklist.c
@@ -175,6 +175,7 @@ do_resize:
 	check_x = 0;
 	item_foreach()
 		check_x = MAX(check_x, strlen(item_str()) + 4);
+	check_x = MIN(check_x, list_width);
 
 	check_x = (list_width - check_x) / 2;
 	item_x = check_x + 4;
-- 
1.6.3



From lizf at cn.fujitsu.com  Thu Jun  3 03:24:57 2010
From: lizf at cn.fujitsu.com (Li Zefan)
Date: Thu, 03 Jun 2010 15:24:57 +0800
Subject: [PATCH 2/2] menuconfig: truncate list items
In-Reply-To: <4C0758B7.5070907@cn.fujitsu.com>
References: <4C0758B7.5070907@cn.fujitsu.com>
Message-ID: <4C0758C9.7080108@cn.fujitsu.com>

Truncate list items to fit in a single line, otherwise those items
which have long prompts will cover some other items.

This follows the behavior of menubox.

Signed-off-by: Li Zefan <lizf at cn.fujitsu.com>
---
 scripts/kconfig/lxdialog/checklist.c |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/scripts/kconfig/lxdialog/checklist.c b/scripts/kconfig/lxdialog/checklist.c
index c92a05a..a2eb80f 100644
--- a/scripts/kconfig/lxdialog/checklist.c
+++ b/scripts/kconfig/lxdialog/checklist.c
@@ -31,6 +31,10 @@ static int list_width, check_x, item_x;
 static void print_item(WINDOW * win, int choice, int selected)
 {
 	int i;
+	char *list_item = malloc(list_width + 1);
+
+	strncpy(list_item, item_str(), list_width - item_x);
+	list_item[list_width - item_x] = '\0';
 
 	/* Clear 'residue' of last item */
 	wattrset(win, dlg.menubox.atr);
@@ -45,13 +49,14 @@ static void print_item(WINDOW * win, int choice, int selected)
 		wprintw(win, "(%c)", item_is_tag('X') ? 'X' : ' ');
 
 	wattrset(win, selected ? dlg.tag_selected.atr : dlg.tag.atr);
-	mvwaddch(win, choice, item_x, item_str()[0]);
+	mvwaddch(win, choice, item_x, list_item[0]);
 	wattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr);
-	waddstr(win, (char *)item_str() + 1);
+	waddstr(win, list_item + 1);
 	if (selected) {
 		wmove(win, choice, check_x + 1);
 		wrefresh(win);
 	}
+	free(list_item);
 }
 
 /*
-- 
1.6.3


From eric.miao at canonical.com  Thu Jun  3 03:36:48 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu,  3 Jun 2010 15:36:48 +0800
Subject: [PATCH 0/5] Makefile.boot cleanup
Message-ID: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>

Several facts:

1. ZRELADDR in most cases can be auto detected by maksing PC with
   0xf000_0000 if the zImage is placed within the first 256MiB from
   the memory start, which is a sane assumption except for:

   - when ARCH_MX1 or ARCH_SHARK is defined
   - when ARCH_U300 is defined (U300 really is strange when defining
     PHYS_OFFSET and ZRELADDR)
   - or when ZBOOT_ROM is defined

2. For the exceptions above or those situations where ZRELADDR still
   needs to be specified, an option CONFIG_ZRELADDR is provided. So
   if there is conflict when mutliple machines are selected (in the
   near future), things can be manually fixed by menuconfig, instead
   of playing tricks with Makefile.

3. INITRD_PHYS and PARAMS_PHYS are really used only for bootpImage,
   and references in arch/arm/boot/compressed can be safely removed

I've listed most of the zreladdr-y found in each Makefile.boot and
made them default value in CONFIG_ZRELADDR, but still there could be
mistakes. Please kindly try and report back, thanks.



From eric.miao at canonical.com  Thu Jun  3 03:36:49 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu,  3 Jun 2010 15:36:49 +0800
Subject: [PATCH 1/5] [ARM] Remove unused PARAMS_PHYS from
	arch/arm/boot/compressed
In-Reply-To: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
Message-ID: <1275550613-9553-2-git-send-email-eric.miao@canonical.com>

From: Eric Miao <eric.y.miao at gmail.com>

The only reference in arch/arm/boot/compressed to PARAMS_PHYS is
params() in head.S, which can be directly converted to the exact
address as specified by arch/arm/mach-rpc/Makefile.boot.

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/boot/compressed/Makefile |    7 ++-----
 arch/arm/boot/compressed/head.S   |    2 +-
 2 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 53faa90..b58a589 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -79,8 +79,8 @@ endif
 EXTRA_CFLAGS  := -fpic -fno-builtin
 EXTRA_AFLAGS  := -Wa,-march=all
 
-# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
-# linker symbols.  We only define initrd_phys and params_phys if the
+# Supply ZRELADDR, INITRD_PHYS to the decompressor via
+# linker symbols.  We only define initrd_phys if the
 # machine class defined the corresponding makefile variable.
 LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
@@ -89,9 +89,6 @@ endif
 ifneq ($(INITRD_PHYS),)
 LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
 endif
-ifneq ($(PARAMS_PHYS),)
-LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS)
-endif
 # ?
 LDFLAGS_vmlinux += -p
 # Report unresolved symbol references
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index c5191b1..0765990 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -321,7 +321,7 @@ LC1:		.word	reloc_end - reloc_start
 
 #ifdef CONFIG_ARCH_RPC
 		.globl	params
-params:		ldr	r0, =params_phys
+params:		ldr	r0, =0x10000100		@ params_phys for RPC
 		mov	pc, lr
 		.ltorg
 		.align
-- 
1.7.0.4



From eric.miao at canonical.com  Thu Jun  3 03:36:50 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu,  3 Jun 2010 15:36:50 +0800
Subject: [PATCH 2/5] [ARM] Remove unused INITRD_PHYS from
	arch/arm/boot/compressed
In-Reply-To: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
Message-ID: <1275550613-9553-3-git-send-email-eric.miao@canonical.com>

From: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

Original patch from Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/boot/compressed/Makefile |    7 +------
 1 files changed, 1 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index b58a589..dbd3fe8 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -79,16 +79,11 @@ endif
 EXTRA_CFLAGS  := -fpic -fno-builtin
 EXTRA_AFLAGS  := -Wa,-march=all
 
-# Supply ZRELADDR, INITRD_PHYS to the decompressor via
-# linker symbols.  We only define initrd_phys if the
-# machine class defined the corresponding makefile variable.
+# Supply ZRELADDR to the decompressor via linker symbols.
 LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
 endif
-ifneq ($(INITRD_PHYS),)
-LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
-endif
 # ?
 LDFLAGS_vmlinux += -p
 # Report unresolved symbol references
-- 
1.7.0.4



From eric.miao at canonical.com  Thu Jun  3 03:36:51 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu,  3 Jun 2010 15:36:51 +0800
Subject: [PATCH 3/5] [ARM] Make TEXT_OFFSET a configurable option
In-Reply-To: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
Message-ID: <1275550613-9553-4-git-send-email-eric.miao@canonical.com>

From: Eric Miao <eric.y.miao at gmail.com>

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/Kconfig         |   13 +++++++++++++
 arch/arm/Makefile        |   13 +------------
 arch/arm/kernel/Makefile |    4 ++--
 3 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..e340193 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1484,6 +1484,19 @@ config ATAGS_PROC
 	  Should the atags used to boot the kernel be exported in an "atags"
 	  file in procfs. Useful with kexec.
 
+config TEXT_OFFSET
+	hex "Offset of the kernel image from the start of RAM"
+	default 0x00008000
+	default 0x00028000 if ARCH_CLPS711X
+	# We don't want the htc bootloader to corrupt kernel during resume
+	default 0x00108000 if PM_H1940
+	# SA1111 DMA bug: we don't want the kernel to live in precious
+	# DMA-able memory
+	default 0x00208000 if (ARCH_SA1100 && SA1111)
+	help
+	  TEXT_OFFSET is the offset of the decompressed kernel image from
+	  memory start. Currently, it is expected the least significant 16
+	  bits to be 0x8000, so to leave space for the initial page table.
 endmenu
 
 menu "CPU Power Management"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 64ba313..df8f73d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -108,14 +108,6 @@ CHECKFLAGS	+= -D__arm__
 
 #Default value
 head-y		:= arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o
-textofs-y	:= 0x00008000
-textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
-# We don't want the htc bootloader to corrupt kernel during resume
-textofs-$(CONFIG_PM_H1940)      := 0x00108000
-# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
-ifeq ($(CONFIG_ARCH_SA1100),y)
-textofs-$(CONFIG_SA1111) := 0x00208000
-endif
 
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
@@ -209,9 +201,6 @@ CFLAGS_3c589_cs.o :=-DISA_SIXTEEN_BIT_PERIPHERAL
 export CFLAGS_3c589_cs.o
 endif
 
-# The byte offset of the kernel image in RAM from the start of RAM.
-TEXT_OFFSET := $(textofs-y)
-
 # The first directory contains additional information for the boot setup code
 ifneq ($(machine-y),)
 MACHINE  := arch/arm/mach-$(word 1,$(machine-y))/
@@ -228,7 +217,7 @@ else
 KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
 endif
 
-export	TEXT_OFFSET GZFLAGS MMUEXT
+export	GZFLAGS MMUEXT
 
 # Do we have FASTFPE?
 FASTFPE		:=arch/arm/fastfpe
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 26d302c..50a0d7e 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -2,8 +2,8 @@
 # Makefile for the linux kernel.
 #
 
-CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET)
-AFLAGS_head.o        := -DTEXT_OFFSET=$(TEXT_OFFSET)
+CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(CONFIG_TEXT_OFFSET)
+AFLAGS_head.o        := -DTEXT_OFFSET=$(CONFIG_TEXT_OFFSET)
 
 ifdef CONFIG_DYNAMIC_FTRACE
 CFLAGS_REMOVE_ftrace.o = -pg
-- 
1.7.0.4



From eric.miao at canonical.com  Thu Jun  3 03:36:52 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu,  3 Jun 2010 15:36:52 +0800
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option for
	exceptions
In-Reply-To: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
Message-ID: <1275550613-9553-5-git-send-email-eric.miao@canonical.com>

From: Eric Miao <eric.y.miao at gmail.com>

Original idea and prototype came from Nicolas Pitre.

As long as the zImage is placed within the 256MB range from the
start of the memory, ZRELADDR (Address where the decompressed
kernel will be placed, usually  == PHYS_OFFSET + TEXT_OFFSET)
can be determined at run-time by masking PC with 0xf000_0000.

Running through all the Makefile.boot, all those zreladdr-y
address == 0x[0-f]000_0000 + TEXT_OFFSET can be determined at
run-time.

Option CONFIG_AUTO_ZRELADDR and CONFIG_ZRELADDR are introduced,
CONFIG_ZRELADDR _must_ be explicitly specified if:

 - ((zreladdr-y - TEXT_OFFSET) & ~0xf0000000) != 0, which means
   a maksing of PC with 0xf000_0000 will result an incorrect
   address.

 - or the assumption of the zImage being loaded by the boot
   loader within 256MB from the start address is simply
   incorrect

 - or when ZBOOT_ROM is used, where the above assumption is
   normally wrong

List of all Makefile.boot:

Hardcoded, and can be auto calculated by masking PC with 0xf000_0000:

arch/arm/mach-cns3xxx/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-dove/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-ebsa110/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-footbridge/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-integrator/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-iop13xx/Makefile.boot:	   zreladdr-y   := 0x00008000
arch/arm/mach-iop33x/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-ixp2000/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-ixp23xx/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-ixp4xx/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-kirkwood/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-ks8695/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-loki/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-mmp/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-mv78xx0/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-nomadik/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-nuc93x/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-ns9xxx/Makefile.boot:	   zreladdr-y	:= 0x8000
arch/arm/mach-orion5x/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-spear3xx/Makefile.boot:      zreladdr-y	:= 0x00008000
arch/arm/mach-spear6xx/Makefile.boot:      zreladdr-y	:= 0x00008000
arch/arm/mach-ux500/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-versatile/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-w90x900/Makefile.boot:	   zreladdr-y	:= 0x00008000
arch/arm/mach-msm/Makefile.boot:	   zreladdr-y	:= 0x10008000
arch/arm/mach-omap1/Makefile.boot:	   zreladdr-y	:= 0x10008000
arch/arm/mach-rpc/Makefile.boot:	   zreladdr-y	:= 0x10008000
arch/arm/mach-s5p6440/Makefile.boot:	   zreladdr-y	:= 0x20008000
arch/arm/mach-s5p6442/Makefile.boot:	   zreladdr-y	:= 0x20008000
arch/arm/mach-s5pc100/Makefile.boot:	   zreladdr-y	:= 0x20008000
arch/arm/mach-s5pv210/Makefile.boot:	   zreladdr-y	:= 0x20008000
arch/arm/mach-s3c2410/Makefile.boot:	   zreladdr-y	:= 0x30008000
arch/arm/mach-s3c2410/Makefile.boot:	   zreladdr-y	:= 0x30108000
arch/arm/mach-stmp378x/Makefile.boot:	   zreladdr-y	:= 0x40008000
arch/arm/mach-stmp37xx/Makefile.boot:	   zreladdr-y	:= 0x40008000
arch/arm/mach-s3c64xx/Makefile.boot:	   zreladdr-y	:= 0x50008000
arch/arm/mach-vexpress/Makefile.boot:	   zreladdr-y	:= 0x60008000
arch/arm/mach-mx25/Makefile.boot:	   zreladdr-y	:= 0x80008000
arch/arm/mach-mx3/Makefile.boot:	   zreladdr-y	:= 0x80008000
arch/arm/mach-netx/Makefile.boot:	   zreladdr-y	:= 0x80008000
arch/arm/mach-omap2/Makefile.boot:	   zreladdr-y	:= 0x80008000
arch/arm/mach-pnx4008/Makefile.boot:	   zreladdr-y	:= 0x80008000
arch/arm/mach-mx5/Makefile.boot:	   zreladdr-y	:= 0x90008000
arch/arm/mach-mxc91231/Makefile.boot:	   zreladdr-y	:= 0x90008000
arch/arm/mach-iop32x/Makefile.boot:	   zreladdr-y	:= 0xa0008000
arch/arm/mach-pxa/Makefile.boot:	   zreladdr-y	:= 0xa0008000
arch/arm/mach-lh7a40x/Makefile.boot:	   zreladdr-y	:= 0xc0008000
arch/arm/mach-clps711x/Makefile.boot:	   zreladdr-y	:= 0xc0028000
arch/arm/mach-aaec2000/Makefile.boot:	   zreladdr-y	:= 0xf0008000
arch/arm/mach-l7200/Makefile.boot:	   zreladdr-y	:= 0xf0008000

Depends on other options/macros, but still can be auto calculated by
masking PC with 0xf000_0000:

arch/arm/mach-bcmring/Makefile.boot:	   zreladdr-y   := $(CONFIG_BCM_ZRELADDR)
* refer to arch/arm/configs/bcmring_defconfig:CONFIG_BCM_ZRELADDR=0x8000
arch/arm/mach-h720x/Makefile.boot:	   zreladdr-$(CONFIG_ARCH_H720X) := 0x40008000
arch/arm/mach-shmobile/Makefile.boot:	   zreladdr-y   := $(__ZRELADDR)
* __ZRELADDR depends on CONFIG_MEMORY_START
arch/arm/configs/ap4evb_defconfig:	CONFIG_MEMORY_START=0x40000000 (SH7372)
arch/arm/configs/g3evm_defconfig:	CONFIG_MEMORY_START=0x50000000 (SH7367)
arch/arm/configs/g4evm_defconfig:	CONFIG_MEMORY_START=0x40000000 (SH7377)

arch/arm/mach-at91/Makefile.boot:	   zreladdr-y	:= 0x70008000 (CONFIG_ARCH_AT91CAP9)
arch/arm/mach-at91/Makefile.boot:	   zreladdr-y	:= 0x70008000 (CONFIG_ARCH_AT91SAM9G45)
arch/arm/mach-at91/Makefile.boot:	   zreladdr-y	:= 0x20008000 (CONFIG_ARCH_AT91)
arch/arm/mach-davinci/Makefile.boot:	   zreladdr-y	:= 0xc0008000 (CONFIG_ARCH_DAVINCI_DA8XX)
arch/arm/mach-davinci/Makefile.boot:	   zreladdr-y	:= 0x80008000 (!CONFIG_ARCH_DAVINCI_DA8XX)
arch/arm/mach-ep93xx/Makefile.boot:	   zreladdr-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET)	:= 0x00008000
arch/arm/mach-ep93xx/Makefile.boot:	   zreladdr-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET)		:= 0xc0008000
arch/arm/mach-ep93xx/Makefile.boot:	   zreladdr-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET)		:= 0xd0008000
arch/arm/mach-ep93xx/Makefile.boot:	   zreladdr-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET)		:= 0xe0008000
arch/arm/mach-ep93xx/Makefile.boot:	   zreladdr-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET)	:= 0xf0008000
arch/arm/mach-gemini/Makefile.boot:	   zreladdr-y	:= 0x00008000 (CONFIG_GEMINI_MEM_SWAP)
arch/arm/mach-gemini/Makefile.boot:	   zreladdr-y	:= 0x10008000 (!CONFIG_GEMINI_MEM_SWAP)
arch/arm/mach-mx2/Makefile.boot:	   zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000
arch/arm/mach-mx2/Makefile.boot:	   zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
arch/arm/mach-realview/Makefile.boot:	   zreladdr-y	:= 0x70008000 (CONFIG_REALVIEW_HIGH_PHYS_OFFSET)
arch/arm/mach-realview/Makefile.boot:	   zreladdr-y	:= 0x00008000 (CONFIG_REALVIEW_HIGH_PHYS_OFFSET)
arch/arm/mach-sa1100/Makefile.boot:	   zreladdr-y	:= 0xc0008000
arch/arm/mach-sa1100/Makefile.boot:	   zreladdr-$(CONFIG_SA1111) := 0xc0208000

Machines where ZRELADDR cannot be auto calcuated:

arch/arm/mach-mx1/Makefile.boot:	   zreladdr-y	:= 0x08008000
arch/arm/mach-shark/Makefile.boot:	   zreladdr-y	:= 0x08008000
arch/arm/mach-u300/Makefile.boot:	   zreladdr-y	:= 0x28E08000
arch/arm/mach-u300/Makefile.boot:	   zreladdr-y	:= 0x48008000

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/Kconfig                  |   63 +++++++++++++++++++++++++++++++++++++
 arch/arm/boot/Makefile            |   10 +++---
 arch/arm/boot/compressed/Makefile |    4 +-
 arch/arm/boot/compressed/head.S   |   12 +++++--
 4 files changed, 79 insertions(+), 10 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e340193..818f731 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1497,6 +1497,69 @@ config TEXT_OFFSET
 	  TEXT_OFFSET is the offset of the decompressed kernel image from
 	  memory start. Currently, it is expected the least significant 16
 	  bits to be 0x8000, so to leave space for the initial page table.
+
+config AUTO_ZRELADDR
+	bool "Auto calculation of the decompressed kernel image address"
+	depends on !ZBOOT_ROM && !(ARCH_MX1 || ARCH_SHARK || ARCH_U300)
+	help
+	  ZRELADDR is the physical address where the decompressed kernel
+	  image will be placed. If AUTO_ZRELADDR is selected, the address
+	  will be determined at run-time by masking the current IP with
+	  0xf000_0000. This assumes the zImage being placed in the 256MB
+	  range from the start of memory.
+
+config ZRELADDR
+	hex "Physical address of the decompressed kernel image"
+	depends on !AUTO_ZRELADDR
+	default 0x00008000 if ARCH_BCMRING || ARCH_CNS3XXX || ARCH_DOVE ||\
+			      ARCH_EBSA110 || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR ||\
+			      ARCH_IOP13XX || ARCH_IOP33X || ARCH_IXP2000 ||\
+			      ARCH_IXP23XX || ARCH_IXP4XX || ARCH_KIRKWOOD ||\
+			      ARCH_KS8695  || ARCH_LOKI || ARCH_MMP || ARCH_MV78XX0 ||\
+			      ARCH_NOMADIK || ARCH_NUC93X || ARCH_NS9XXX ||\
+			      ARCH_ORION5X || ARCH_SPEAR3XX || ARCH_SPEAR6XX ||\
+			      ARCH_UX5XX || ARCH_VERSATILE || ARCH_W90X900
+	default 0x08008000 if ARCH_MX1 || ARCH_SHARK
+	default 0x10008000 if ARCH_MSM || ARCH_OMAP1 || ARCH_RPC
+	default 0x20008000 if ARCH_S5P6440 || ARCH_S5P6442 ||\
+			      ARCH_S5PC100 || ARCH_S5PV210
+	default 0x30008000 if ARCH_S3C2410 || ARCH_S3C2400 || ARCH_S3C2412 ||\
+			      ARCH_S3C2416 || ARCH_S3C2440 || ARCH_S3C2443
+	default 0x40008000 if ARCH_STMP378X || ARCH_STMP37XX || ARCH_SH7372 ||\
+			      ARCH_SH7377
+	default 0x50008000 if ARCH_S3C64XX || ARCH_SH7367
+	default 0x60008000 if ARCH_VEXPRESS
+	default 0x80008000 if ARCH_MX25 || ARCH_MX3 || ARCH_NETX ||\
+			      ARCH_OMAP2 || ARCH_PNX4008
+	default 0x90008000 if ARCH_MX5 || ARCH_MX91231
+	default 0xa0008000 if ARCH_IOP32X || ARCH_PXA || MACH_MX27
+	default 0xc0008000 if ARCH_LH7A40X || MACH_MX21
+	default 0xf0008000 if ARCH_AAEC2000 || ARCH_L7200
+	default 0xc0028000 if ARCH_CLPS711X
+	default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
+	default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
+	default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX
+	default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX
+	default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET
+	default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET
+	default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET
+	default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET
+	default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET
+	default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP
+	default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP
+	default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET
+	default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET
+	default 0xc0208000 if ARCH_SA1100 && SA1111
+	default 0xc0008000 if ARCH_SA1100 && !SA1111
+	default 0x30108000 if ARCH_S3C2410 && PM_H1940
+	default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM
+	default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM
+	help
+	  ZRELADDR is the physical address where the decompressed kernel
+	  image will be placed. ZRELADDR has to be specified when the
+	  assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is
+	  selected.
+
 endmenu
 
 menu "CPU Power Management"
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 4a590f4..8cc4669 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -14,18 +14,16 @@
 MKIMAGE         := $(srctree)/scripts/mkuboot.sh
 
 ifneq ($(MACHINE),)
-include $(srctree)/$(MACHINE)/Makefile.boot
+-include $(srctree)/$(MACHINE)/Makefile.boot
 endif
 
 # Note: the following conditions must always be true:
-#   ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
 #   PARAMS_PHYS must be within 4MB of ZRELADDR
 #   INITRD_PHYS must be in RAM
-ZRELADDR    := $(zreladdr-y)
 PARAMS_PHYS := $(params_phys-y)
 INITRD_PHYS := $(initrd_phys-y)
 
-export ZRELADDR INITRD_PHYS PARAMS_PHYS
+export INITRD_PHYS PARAMS_PHYS
 
 targets := Image zImage xipImage bootpImage uImage
 
@@ -67,7 +65,7 @@ quiet_cmd_uimage = UIMAGE  $@
 ifeq ($(CONFIG_ZBOOT_ROM),y)
 $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
 else
-$(obj)/uImage: LOADADDR=$(ZRELADDR)
+$(obj)/uImage: LOADADDR=$(CONFIG_ZRELADDR)
 endif
 
 ifeq ($(CONFIG_THUMB2_KERNEL),y)
@@ -78,6 +76,8 @@ $(obj)/uImage: STARTADDR=$(LOADADDR)
 endif
 
 $(obj)/uImage:	$(obj)/zImage FORCE
+	@test "$(CONFIG_AUTO_ZRELADDR)" == "y" ||\
+	(echo CONFIG_ZRELADDR must be specified for uImage; exit -1)
 	$(call if_changed,uimage)
 	@echo '  Image $@ is ready'
 
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index dbd3fe8..45b0f48 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -4,6 +4,8 @@
 # create a compressed vmlinuz image from the original vmlinux
 #
 
+AFLAGS_head.o        := -DTEXT_OFFSET=$(CONFIG_TEXT_OFFSET)
+
 HEAD	= head.o
 OBJS	= misc.o decompress.o
 FONTC	= $(srctree)/drivers/video/console/font_acorn_8x8.c
@@ -79,8 +81,6 @@ endif
 EXTRA_CFLAGS  := -fpic -fno-builtin
 EXTRA_AFLAGS  := -Wa,-march=all
 
-# Supply ZRELADDR to the decompressor via linker symbols.
-LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
 endif
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 0765990..17d19dc 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -170,9 +170,16 @@ not_angel:
 
 		.text
 		adr	r0, LC0
- ARM(		ldmia	r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
- THUMB(		ldmia	r0, {r1, r2, r3, r4, r5, r6, r11, ip}	)
+ ARM(		ldmia	r0, {r1, r2, r3, r5, r6, r11, ip, sp})
+ THUMB(		ldmia	r0, {r1, r2, r3, r5, r6, r11, ip}	)
  THUMB(		ldr	sp, [r0, #32]				)
+#ifdef CONFIG_AUTO_ZRELADDR
+		@ determine final kernel image address
+		and	r4, pc, #0xf0000000
+		add	r4, r4, #TEXT_OFFSET
+#else
+		ldr	r4, =CONFIG_ZRELADDR
+#endif
 		subs	r0, r0, r1		@ calculate the delta offset
 
 						@ if delta is zero, we are
@@ -310,7 +317,6 @@ wont_overwrite:	mov	r0, r4
 LC0:		.word	LC0			@ r1
 		.word	__bss_start		@ r2
 		.word	_end			@ r3
-		.word	zreladdr		@ r4
 		.word	_start			@ r5
 		.word	_image_size		@ r6
 		.word	_got_start		@ r11
-- 
1.7.0.4



From eric.miao at canonical.com  Thu Jun  3 03:36:53 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu,  3 Jun 2010 15:36:53 +0800
Subject: [PATCH 5/5] [ARM] Move inclusion of Makefile.boot into
	arch/arm/boot/bootp
In-Reply-To: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
Message-ID: <1275550613-9553-6-git-send-email-eric.miao@canonical.com>

From: Eric Miao <eric.y.miao at gmail.com>

Since zreladdr-y, params_phys-y and initrd_phys-y are no longer
used in arch/arm/boot/compressed, move the inclusion into bootp/.

Now unless you are building for an bootpImage, no per machine
class Makefile.boot needs to be included.

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/boot/Makefile       |   21 +--------------------
 arch/arm/boot/bootp/Makefile |   19 ++++++++++++++++++-
 2 files changed, 19 insertions(+), 21 deletions(-)

diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 8cc4669..5e1b5f4 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -13,18 +13,6 @@
 
 MKIMAGE         := $(srctree)/scripts/mkuboot.sh
 
-ifneq ($(MACHINE),)
--include $(srctree)/$(MACHINE)/Makefile.boot
-endif
-
-# Note: the following conditions must always be true:
-#   PARAMS_PHYS must be within 4MB of ZRELADDR
-#   INITRD_PHYS must be in RAM
-PARAMS_PHYS := $(params_phys-y)
-INITRD_PHYS := $(initrd_phys-y)
-
-export INITRD_PHYS PARAMS_PHYS
-
 targets := Image zImage xipImage bootpImage uImage
 
 ifeq ($(CONFIG_XIP_KERNEL),y)
@@ -81,7 +69,7 @@ $(obj)/uImage:	$(obj)/zImage FORCE
 	$(call if_changed,uimage)
 	@echo '  Image $@ is ready'
 
-$(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
+$(obj)/bootp/bootp: $(obj)/zImage FORCE
 	$(Q)$(MAKE) $(build)=$(obj)/bootp $@
 	@:
 
@@ -89,13 +77,6 @@ $(obj)/bootpImage: $(obj)/bootp/bootp FORCE
 	$(call if_changed,objcopy)
 	@echo '  Kernel: $@ is ready'
 
-PHONY += initrd FORCE
-initrd:
-	@test "$(INITRD_PHYS)" != "" || \
-	(echo This machine does not support INITRD; exit -1)
-	@test "$(INITRD)" != "" || \
-	(echo You must specify INITRD; exit -1)
-
 install: $(obj)/Image
 	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
 	$(obj)/Image System.map "$(INSTALL_PATH)"
diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile
index c394e30..4b32d92 100644
--- a/arch/arm/boot/bootp/Makefile
+++ b/arch/arm/boot/bootp/Makefile
@@ -5,6 +5,16 @@
 # architecture-specific flags and dependencies.
 #
 
+ifneq ($(MACHINE),)
+-include $(srctree)/$(MACHINE)/Makefile.boot
+endif
+
+# Note: the following conditions must always be true:
+#   PARAMS_PHYS must be within 4MB of ZRELADDR
+#   INITRD_PHYS must be in RAM
+PARAMS_PHYS := $(params_phys-y)
+INITRD_PHYS := $(initrd_phys-y)
+
 LDFLAGS_bootp	:=-p --no-undefined -X \
 		 --defsym initrd_phys=$(INITRD_PHYS) \
 		 --defsym params_phys=$(PARAMS_PHYS) -T
@@ -17,11 +27,18 @@ $(obj)/bootp:	$(src)/bootp.lds $(addprefix $(obj)/,init.o kernel.o initrd.o) FOR
 	$(call if_changed,ld)
 	@:
 
+PHONY += initrd FORCE
+initrd:
+	@test "$(INITRD_PHYS)" != "" || \
+	(echo This machine does not support INITRD; exit -1)
+	@test "$(INITRD)" != "" || \
+	(echo You must specify INITRD; exit -1)
+
 # kernel.o and initrd.o includes a binary image using
 # .incbin, a dependency which is not tracked automatically
 
 $(obj)/kernel.o: arch/arm/boot/zImage FORCE
 
-$(obj)/initrd.o: $(INITRD) FORCE
+$(obj)/initrd.o: $(INITRD) initrd FORCE
 
 PHONY += $(INITRD) FORCE
-- 
1.7.0.4



From eric.miao at canonical.com  Thu Jun  3 03:43:30 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 3 Jun 2010 15:43:30 +0800
Subject: [PATCH 0/5] Makefile.boot cleanup
In-Reply-To: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
Message-ID: <AANLkTim-U76fy_N6bfhJ0BFihDrW1YEcJXDyEqtajc8c@mail.gmail.com>

On Thu, Jun 3, 2010 at 3:36 PM, Eric Miao <eric.miao at canonical.com> wrote:
> Several facts:
>
> 1. ZRELADDR in most cases can be auto detected by maksing PC with
> ? 0xf000_0000 if the zImage is placed within the first 256MiB from
> ? the memory start, which is a sane assumption except for:
>
> ? - when ARCH_MX1 or ARCH_SHARK is defined
> ? - when ARCH_U300 is defined (U300 really is strange when defining
> ? ? PHYS_OFFSET and ZRELADDR)
> ? - or when ZBOOT_ROM is defined
>

And maybe we could restrict the assumption to 128MB, so that MX1
and SHARK can be included as well.

> 2. For the exceptions above or those situations where ZRELADDR still
> ? needs to be specified, an option CONFIG_ZRELADDR is provided. So
> ? if there is conflict when mutliple machines are selected (in the
> ? near future), things can be manually fixed by menuconfig, instead
> ? of playing tricks with Makefile.
>
> 3. INITRD_PHYS and PARAMS_PHYS are really used only for bootpImage,
> ? and references in arch/arm/boot/compressed can be safely removed
>
> I've listed most of the zreladdr-y found in each Makefile.boot and
> made them default value in CONFIG_ZRELADDR, but still there could be
> mistakes. Please kindly try and report back, thanks.
>
>


From u.kleine-koenig at pengutronix.de  Thu Jun  3 03:57:04 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 3 Jun 2010 09:57:04 +0200
Subject: [PATCH 0/5] Makefile.boot cleanup
In-Reply-To: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
Message-ID: <20100603075704.GB336@pengutronix.de>

Hello Eric,

On Thu, Jun 03, 2010 at 03:36:48PM +0800, Eric Miao wrote:
> Several facts:
> 
> 1. ZRELADDR in most cases can be auto detected by maksing PC with
>    0xf000_0000 if the zImage is placed within the first 256MiB from
>    the memory start, which is a sane assumption except for:
> 
>    - when ARCH_MX1 or ARCH_SHARK is defined
>    - when ARCH_U300 is defined (U300 really is strange when defining
>      PHYS_OFFSET and ZRELADDR)
>    - or when ZBOOT_ROM is defined
If you guess ZRELADDR based on sp instead of pc it even should work if
ZBOOT_ROM is defined?!

That's how I did it in
http://git.pengutronix.de/?p=ukl/linux-2.6.git;a=commit;h=booting/pu

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From avictor.za at gmail.com  Thu Jun  3 03:57:54 2010
From: avictor.za at gmail.com (avictor.za at gmail.com)
Date: Thu, 3 Jun 2010 09:57:54 +0200
Subject: [PATCH 2/2] at91sam9g20ek: add fixed-value regulator for wm8731
In-Reply-To: <1275059443-10100-2-git-send-email-dbaryshkov@gmail.com>
References: <1275059443-10100-1-git-send-email-dbaryshkov@gmail.com>
	<1275059443-10100-2-git-send-email-dbaryshkov@gmail.com>
Message-ID: <AANLkTil9KtG3QZDXqBtu63SzitW63u_lGDOa3Q8-l9MZ@mail.gmail.com>

hi Dmitry,

> If CONFIG_REGULATOR is enabled, wm8731 fails on AT91SAM9G20EK board,
> since codec driver requires several voltage supplies and none are
> provided currently. As requires voltages are hardwired to 3V3, use fixed
> voltage regulator for this chip.
>
> Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>

Acked-by: Andrew Victor <linux at maxim.org.za>

Please submit to the patch system.


From u.kleine-koenig at pengutronix.de  Thu Jun  3 04:00:43 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 3 Jun 2010 10:00:43 +0200
Subject: [PATCH 0/5] Makefile.boot cleanup
In-Reply-To: <AANLkTim-U76fy_N6bfhJ0BFihDrW1YEcJXDyEqtajc8c@mail.gmail.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<AANLkTim-U76fy_N6bfhJ0BFihDrW1YEcJXDyEqtajc8c@mail.gmail.com>
Message-ID: <20100603080043.GC336@pengutronix.de>

Hi Eric,

On Thu, Jun 03, 2010 at 03:43:30PM +0800, Eric Miao wrote:
> On Thu, Jun 3, 2010 at 3:36 PM, Eric Miao <eric.miao at canonical.com> wrote:
> > Several facts:
> >
> > 1. ZRELADDR in most cases can be auto detected by maksing PC with
> > ? 0xf000_0000 if the zImage is placed within the first 256MiB from
> > ? the memory start, which is a sane assumption except for:
> >
> > ? - when ARCH_MX1 or ARCH_SHARK is defined
> > ? - when ARCH_U300 is defined (U300 really is strange when defining
> > ? ? PHYS_OFFSET and ZRELADDR)
> > ? - or when ZBOOT_ROM is defined
> >
> 
> And maybe we could restrict the assumption to 128MB, so that MX1
> and SHARK can be included as well.
I used 128 MiB, too.  When I did it I found "problems" for s3c2400 and
at91.  For the latter physoffset depended on .config.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From ben-linux at fluff.org  Thu Jun  3 04:13:54 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Thu, 3 Jun 2010 09:13:54 +0100
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <201006031121.21896.jeremy.kerr@canonical.com>
References: <1275479804.137633.565764505843.0.gpush@pororo>
	<1275479804.138101.137592675542.1.gpush@pororo>
	<20100602120356.GQ7248@trinity.fluff.org>
	<201006031121.21896.jeremy.kerr@canonical.com>
Message-ID: <20100603081354.GA4720@trinity.fluff.org>

On Thu, Jun 03, 2010 at 11:21:19AM +0800, Jeremy Kerr wrote:
> Hi Ben,
> 
> > > And a set of clock operations (defined per type of clock):
> > > 
> > > struct clk_operations {
> > > 
> > >        int             (*enable)(struct clk *);
> > 
> > I'd rather the enable/disable calls where simply a set
> > and a bool on/off, very rarelyt is the enable and disable
> > operartions different.
> 
> I thought about merging these, but decided against it. It does work for the 
> simple case where we're setting a bit in a register:
> 
> static int clk_foo_set_state(struct clk *_clk, int enable)
> {
> 	struct clk_foo *clk = to_clk_foo(_clk)
> 	u32 reg;
> 
> 	reg = raw_readl(foo->some_register);
> 	if (enable)
> 		reg |= FOO_ENABLE;
> 	else
> 		reg &= ~FOO_ENABLE;
> 	raw_writel(foo->some_register, reg);
> 
> 	return 0;
> }
> 
> However, for anything more complex than this - for example, if there's a 
> parent clock - then we start getting pretty messy:
> 
> static int clk_foo_set_state(struct clk *_clk, int enable)
> {
> 	struct clk_foo *clk = to_clk_foo(_clk)
> 	u32 reg;

Yuck. I think this should really be handled by the base clk_enable()
and clk_disable() calls. Roughly based on what is currently in the
plat-samsung clock implementation:

clk_enable(struct clk *clk)
{
	if (clk->parent)
		clk_enable(clk->parent)
	...
}

clk_disable(struct clk *clk)
{
	...
	if (clk->parent)
		clk_disable(clk->parent)
}

I think it is a really bad idea for each implementation to have to worry
about this. It sounds like a recipie for people to get wrong, especially
if we have a number of these implementations kicking around.

> 	if (enable) {
> 		int ret = clk_enable(clk->parent);
> 		if (ret)
> 			return ret;
> 	}
> 
> 	reg = raw_readl(foo->some_register);
> 	if (enable)
> 		reg |= FOO_ENABLE;
> 	else
> 		reg &= ~FOO_ENABLE;
> 
> 	raw_writel(foo->some_register, reg);
> 
> 	if (!enable)
> 		clk_disable(clk->parent);
> 
> 	return 0;
> }
> 
> - where most of the function becomes surrounded by "if (enable)" statements. 
> 
> I'm aware that we can turn this into a conditional call of clk_foo_enable or 
> clk_foo_disable, but then we're back to square 1. I also think that the simple 
> case is clearer (if a little more verbose) with separate functions.

If we do decided to move the parent control functionality to the clock
core, then I would prefer to see the change to a single enable/disable
callback. Especially as it fits my current implementations well.

As a note, I also left the enable callback in the 'struct clk' instead
of in the ops, enable/disable is the most used case of these clock
functions, and as such should probably be the easiest to get to.

Also, wheras plat-samsung has very few sets of clk_ops sitting about,
there are more enable/disable calls, and adding more fields to the
clocks to deal with this would add extra space to the kernel.

> Also, enable and disable in the external clock API have different return 
> types.

does that really matter?
 
> > an aside, you might want to just clal these clk_ops to get into the
> > spirit of the original naming.
> 
> Either is fine with me - looks like 'ops' is more commonly used:

My pref. is for less typing.
 
> $ git grep -E '^struct \w*operations\s*\{' include/ | wc -l
> 30
> 
> $ git grep -E '^struct \w*ops\s*{' include/ | wc -l
> 138
> 
> Cheers,
> 
> 
> Jeremy

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From s.hauer at pengutronix.de  Thu Jun  3 04:19:26 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 3 Jun 2010 10:19:26 +0200
Subject: [alsa-devel] [PATCH v2 1/4] imx-ssi.c: add new choices to
	platform configuration
In-Reply-To: <20100601180527.GC10031@sirena.org.uk>
References: <1274950737-26498-1-git-send-email-eric@eukrea.com>
	<20100601180527.GC10031@sirena.org.uk>
Message-ID: <20100603081926.GT26820@pengutronix.de>

On Tue, Jun 01, 2010 at 07:05:28PM +0100, Mark Brown wrote:
> On Thu, May 27, 2010 at 10:58:54AM +0200, Eric B??nard wrote:
> > * introduce 3 new flags to allow a more detailed configuration
> > of the SSI link :
> > 	IMX_SSI_NET : enable Network Mode
> > 	IMX_SSI_SYN : enable Synchronous Mode
> > 	IMX_SSI_USE_I2S_SLAVE : enable I2S Slave Mode
> > * new platform can use these settings without breaking actual
> > platforms.
> > 
> > Signed-off-by: Eric B??nard <eric at eukrea.com>
> > Cc: Sascha Hauer <s.hauer at pengutronix.de>
> 
> Sascha, any comments on the first couple of patches here?

Acked-by: Sascha Hauer <s.hauer at pengutronix.de>



-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From eric.miao at canonical.com  Thu Jun  3 04:27:04 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 3 Jun 2010 16:27:04 +0800
Subject: [PATCH 0/5] Makefile.boot cleanup
In-Reply-To: <20100603080043.GC336@pengutronix.de>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com> 
	<AANLkTim-U76fy_N6bfhJ0BFihDrW1YEcJXDyEqtajc8c@mail.gmail.com> 
	<20100603080043.GC336@pengutronix.de>
Message-ID: <AANLkTik7NEywnBFz6ul7jNKkiDfX5wS-3BP8F1Cyyw5r@mail.gmail.com>

2010/6/3 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> Hi Eric,
>
> On Thu, Jun 03, 2010 at 03:43:30PM +0800, Eric Miao wrote:
>> On Thu, Jun 3, 2010 at 3:36 PM, Eric Miao <eric.miao at canonical.com> wrote:
>> > Several facts:
>> >
>> > 1. ZRELADDR in most cases can be auto detected by maksing PC with
>> > ? 0xf000_0000 if the zImage is placed within the first 256MiB from
>> > ? the memory start, which is a sane assumption except for:
>> >
>> > ? - when ARCH_MX1 or ARCH_SHARK is defined
>> > ? - when ARCH_U300 is defined (U300 really is strange when defining
>> > ? ? PHYS_OFFSET and ZRELADDR)
>> > ? - or when ZBOOT_ROM is defined
>> >
>>
>> And maybe we could restrict the assumption to 128MB, so that MX1
>> and SHARK can be included as well.
> I used 128 MiB, too. ?When I did it I found "problems" for s3c2400 and
> at91. ?For the latter physoffset depended on .config.
>

Yeah, there are some platforms really makes me scratching my head.
For the problem of PHYS_OFFSET actually, not necessarily ZRELADDR.
(I've again reviewed your previous patches, and think maybe we can
possibly work together to bring them to the list again)

1. S3C2400 PHYS_OFFSET == 0x0c00_0000 which is on a 64MB boundary.
I guess we can simply drop support for such platforms. Restricting the
assumption to even smaller is not fair for most other platforms.

2. AT91 is actually much better.

3. The most weird platform must be U300, that PHYS_OFFSET is really
something variable. Depending on a somewhat access processor (I guess
it's a communication processor/MODEM). While for U300, I guess a proper
way for it to do is to declare a high enough TEXT_OFFSET and use .fixup
to reserve a range of memory for the access processor if possible.

Yet we don't have to support those platforms. The complex of the problem
is really: how to support as many platforms as possible yet still leave a
smooth migration path, and a fall-back way for those silicon simply just
cannot do auto detection at run-time, and the different boot method:
ZROM/XIP (and possibly bootp)


From s.hauer at pengutronix.de  Thu Jun  3 04:28:52 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 3 Jun 2010 10:28:52 +0200
Subject: [PATCH v5] i.MX27: add suspend to RAM support
In-Reply-To: <1275422264-4040-1-git-send-email-eric@eukrea.com>
References: <20100527214642.GG25921@n2100.arm.linux.org.uk>
	<1275422264-4040-1-git-send-email-eric@eukrea.com>
Message-ID: <20100603082852.GV26820@pengutronix.de>

On Tue, Jun 01, 2010 at 09:57:44PM +0200, Eric B?nard wrote:
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> ---
> v5:
> 	remove const struct
> v4:
> 	fixed include + const struct
> v3:
> 	return -EINVAL instead of -1
> 
>  arch/arm/mach-mx2/Makefile   |    2 +-
>  arch/arm/mach-mx2/pm-imx27.c |   46 ++++++++++++++++++++++++++++++++++++++++++
>  2 files changed, 47 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/mach-mx2/pm-imx27.c

Ok, applied

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Jun  3 04:31:55 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 3 Jun 2010 10:31:55 +0200
Subject: [PATCH 2/2] mx31moboard: Add MC13783 power button support
In-Reply-To: <1275334140-29339-3-git-send-email-philippe.retornaz@epfl.ch>
References: <1275334140-29339-1-git-send-email-philippe.retornaz@epfl.ch>
	<1275334140-29339-2-git-send-email-philippe.retornaz@epfl.ch>
	<1275334140-29339-3-git-send-email-philippe.retornaz@epfl.ch>
Message-ID: <20100603083155.GW26820@pengutronix.de>

Hi Philippe,

Please ping me once the LED/Power button support is merged. I'll take
care of the platform patches.

Sascha

On Mon, May 31, 2010 at 09:29:00PM +0200, Philippe R?tornaz wrote:
> Add the power-on button on mx31moboard using MC13783 PMIC.
> 
> Signed-off-by: Philippe R?tornaz <philippe.retornaz at epfl.ch>
> ---
>  arch/arm/mach-mx3/mach-mx31moboard.c |   10 +++++++++-
>  1 files changed, 9 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
> index 62b5e40..7a8f078 100644
> --- a/arch/arm/mach-mx3/mach-mx31moboard.c
> +++ b/arch/arm/mach-mx3/mach-mx31moboard.c
> @@ -31,6 +31,7 @@
>  #include <linux/mfd/mc13783.h>
>  #include <linux/spi/spi.h>
>  #include <linux/types.h>
> +#include <linux/input.h>
>  
>  #include <linux/usb/otg.h>
>  #include <linux/usb/ulpi.h>
> @@ -262,12 +263,19 @@ static struct mc13783_leds_platform_data moboard_leds = {
>  	.tc2_period = MC13783_LED_PERIOD_10MS,
>  };
>  
> +static struct mc13783_buttons_platform_data moboard_buttons = {
> +	.b1on_flags = MC13783_BUTTON_DBNC_750MS | MC13783_BUTTON_ENABLE |
> +			MC13783_BUTTON_POL_INVERT | MC13783_BUTTON_EMUL_CAD,
> +	.b1on_key = KEY_POWER,
> +};
> +
>  static struct mc13783_platform_data moboard_pmic = {
>  	.regulators = moboard_regulators,
>  	.num_regulators = ARRAY_SIZE(moboard_regulators),
>  	.leds = &moboard_leds,
> +	.buttons = &moboard_buttons,
>  	.flags = MC13783_USE_REGULATOR | MC13783_USE_RTC |
> -		MC13783_USE_ADC | MC13783_USE_LED,
> +		MC13783_USE_ADC | MC13783_USE_LED | MC13783_USE_BUTTON,
>  };
>  
>  static struct spi_board_info moboard_spi_board_info[] __initdata = {
> -- 
> 1.6.3.3
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Jun  3 04:35:22 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 3 Jun 2010 10:35:22 +0200
Subject: Please pull mxc patches for -rc
Message-ID: <20100603083522.GX26820@pengutronix.de>

Hi Russell,

please pull the following for -rc.

Sascha

The following changes since commit aef4b9aaae1decc775778903922bd0075cce7a88:

  Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc (2010-06-01 14:13:14 -0700)

are available in the git repository at:

  git://git.pengutronix.de/git/imx/linux-2.6.git for-rmk

Amit Kucheria (1):
      arm: mxc: utilise usecount field in clock operations

Baruch Siach (3):
      mxc_nand: add support for platform defined partitions
      mx25: add platform code for imx-keypad
      mx25pdk: add keypad support

Daniel Mack (4):
      ARM: mx3: pcm037: remove unused variable
      ARM: mx3: mx31lilly: fix build error for !CONFIG_USB_ULPI
      ARM: mx3: mx31lilly: pass mc13783 SPI IRQ pin
      ARM: mx3: update mx3_defconfig

Dinh Nguyen (2):
      mx5: Add i2c to Freescale MX51 Babbage HW
      mx5: Register i2c on Freescale MX51 Babbage HW

Eric B?nard (13):
      eukrea_mbimx27-baseboard: fix typo in display name
      eukrea_mbimx27-baseboard: add generic-bl and platform-lcd controls
      eukrea_mbimx27-baseboard: add timings for DVI output
      cpuimx27 and mbimx27: allow fine control of UART4 and SDHC2 usage
      mach-cpuimx27: fix QuadUART's IRQ typo in pins'setup
      eukrea_mbimx27: fix ADS7846 support
      mach-cpuimx27: add USB Host2 and OTG support
      mach-cpuimx27: register wdt and w1_master resources
      mxcmmc: add card detect through DAT3 possibility
      eukrea_mbimx27: use card detect through DAT3 for SDHC1
      MX2X: Add Keypad device definition for MX2X arch
      eukrea_mbimx27: add support for the keyboard
      eukrea_mbimx27: add audio codec

Sascha Hauer (2):
      mxc_nand: Fix OOB handling
      arm: Add a mx25_defconfig file

Wolfram Sang (1):
      pcm037/pcm043/pca100: fix ULPI-related build warnings

 arch/arm/configs/mx25_defconfig              | 1756 ++++++++++++++++++++++++++
 arch/arm/configs/mx3_defconfig               |  695 ++++++++++-
 arch/arm/mach-mx2/Kconfig                    |   10 +-
 arch/arm/mach-mx2/devices.c                  |   18 +
 arch/arm/mach-mx2/devices.h                  |    1 +
 arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c |  181 +++-
 arch/arm/mach-mx2/mach-cpuimx27.c            |   93 ++-
 arch/arm/mach-mx2/mach-pca100.c              |    2 +
 arch/arm/mach-mx25/clock.c                   |    2 +-
 arch/arm/mach-mx25/devices.c                 |   20 +
 arch/arm/mach-mx25/devices.h                 |    1 +
 arch/arm/mach-mx25/mach-mx25pdk.c            |   36 +
 arch/arm/mach-mx3/mach-mx31lilly.c           |   34 +-
 arch/arm/mach-mx3/mach-pcm037.c              |    3 +-
 arch/arm/mach-mx3/mach-pcm043.c              |    2 +
 arch/arm/mach-mx5/board-mx51_babbage.c       |   26 +
 arch/arm/mach-mx5/clock-mx51.c               |   11 +
 arch/arm/mach-mx5/devices.c                  |   58 +
 arch/arm/mach-mx5/devices.h                  |    3 +
 arch/arm/plat-mxc/clock.c                    |   37 +-
 arch/arm/plat-mxc/include/mach/iomux-mx25.h  |   19 +-
 arch/arm/plat-mxc/include/mach/iomux-mx51.h  |   18 +-
 arch/arm/plat-mxc/include/mach/mmc.h         |    3 +
 arch/arm/plat-mxc/include/mach/mx25.h        |    2 +
 arch/arm/plat-mxc/include/mach/mxc_nand.h    |    4 +
 drivers/mmc/host/mxcmmc.c                    |   16 +-
 drivers/mtd/nand/mxc_nand.c                  |   33 +-
 27 files changed, 2949 insertions(+), 135 deletions(-)
 create mode 100644 arch/arm/configs/mx25_defconfig
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From kgene.kim at samsung.com  Thu Jun  3 04:43:42 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 03 Jun 2010 17:43:42 +0900
Subject: [PATCH v2] ARM: S5PV210: Add Power Management Support
In-Reply-To: <20100601020329.GT4720@trinity.fluff.org>
References: <1275356164-7896-1-git-send-email-kgene.kim@samsung.com>
	<20100601020329.GT4720@trinity.fluff.org>
Message-ID: <003801cb02f8$e1d61600$a5824200$%kim@samsung.com>

Ben Dooks wrote:
> 
> On Tue, Jun 01, 2010 at 10:36:04AM +0900, Kukjin Kim wrote:
> > From: Jongpill Lee <boyko.lee at samsung.com>
> >
> > This patch adds suspend-to-ram support for S5PV210.
> >
> > Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> > ---
> > Changes since v1:
> >
> > 1. Fixed comments as per comments from Ben Dooks
> > 2. Removed redunt #if defined(CONFIG_PM)
> > 3. Removed redunt including header files
> > 4. Removed <mach/pm.h> and <plat/pm-s5p.h>
> > 5. Moved 's5pv210_core_save' into machine directory
> > 6. Moved sleep.S into machine directory for S5P SoCs compatibility
> > 7. Added CF retension configuration when wake-up
> >
> > This patch is based on Linus' master (2.6.35-rc1)
> >
> >  arch/arm/mach-s5pv210/Kconfig                   |    6 +
> >  arch/arm/mach-s5pv210/Makefile                  |    1 +
> >  arch/arm/mach-s5pv210/include/mach/pm-core.h    |   44 ++++++
> >  arch/arm/mach-s5pv210/include/mach/regs-clock.h |    5 +-
> >  arch/arm/mach-s5pv210/mach-smdkc110.c           |    2 +
> >  arch/arm/mach-s5pv210/mach-smdkv210.c           |    3 +
> >  arch/arm/mach-s5pv210/pm.c                      |  180
> +++++++++++++++++++++++
> >  arch/arm/mach-s5pv210/sleep.S                   |  166
> +++++++++++++++++++++
> >  arch/arm/plat-s5p/Makefile                      |    2 +
> >  arch/arm/plat-s5p/include/plat/irqs.h           |    2 +
> >  arch/arm/plat-s5p/irq-pm.c                      |  108 ++++++++++++++
> >  arch/arm/plat-s5p/pm.c                          |   52 +++++++
> >  arch/arm/plat-samsung/pm-gpio.c                 |    4 +-
> >  13 files changed, 572 insertions(+), 3 deletions(-)
> >  create mode 100644 arch/arm/mach-s5pv210/include/mach/pm-core.h
> >  create mode 100644 arch/arm/mach-s5pv210/pm.c
> >  create mode 100644 arch/arm/mach-s5pv210/sleep.S
> >  create mode 100644 arch/arm/plat-s5p/irq-pm.c
> >  create mode 100644 arch/arm/plat-s5p/pm.c
> >
> > diff --git a/arch/arm/mach-s5pv210/Kconfig
b/arch/arm/mach-s5pv210/Kconfig
> > index 0761eac..86cca1b 100644
> > --- a/arch/arm/mach-s5pv210/Kconfig
> > +++ b/arch/arm/mach-s5pv210/Kconfig
> > @@ -14,6 +14,7 @@ config CPU_S5PV210
> >  	select PLAT_S5P
> >  	select S3C_PL330_DMA
> >  	select S5P_EXT_INT
> > +	select S5PV210_PM if PM
> >  	help
> >  	  Enable S5PV210 CPU support
> >
> > @@ -88,4 +89,9 @@ config MACH_SMDKC110
> >  	  Machine support for Samsung SMDKC110
> >  	  S5PC110(MCP) is one of package option of S5PV210
> >
> > +config S5PV210_PM
> > +	bool
> > +	help
> > +	  Power Management code common to S5PV210
> > +
> >  endif
> > diff --git a/arch/arm/mach-s5pv210/Makefile
b/arch/arm/mach-s5pv210/Makefile
> > index 30be9a6..59382ec 100644
> > --- a/arch/arm/mach-s5pv210/Makefile
> > +++ b/arch/arm/mach-s5pv210/Makefile
> > @@ -14,6 +14,7 @@ obj-				:=
> >
> >  obj-$(CONFIG_CPU_S5PV210)	+= cpu.o init.o clock.o dma.o gpiolib.o
> >  obj-$(CONFIG_CPU_S5PV210)	+= setup-i2c0.o
> > +obj-$(CONFIG_S5PV210_PM)	+= pm.o sleep.o
> >
> >  # machine support
> >
> > diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h
b/arch/arm/mach-
> s5pv210/include/mach/pm-core.h
> > new file mode 100644
> > index 0000000..ca3f827
> > --- /dev/null
> > +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
> > @@ -0,0 +1,44 @@
> > +/* linux/arch/arm/mach-s5pv210/include/mach/pm-core.h
> > + *
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com
> > + *
> > + * Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
> > + * Copyright 2008 Simtec Electronics
> > + *      Ben Dooks <ben at simtec.co.uk>
> > + *      http://armlinux.simtec.co.uk/
> > + *
> > + * S5PV210 - PM core support for arch/arm/plat-s5p/pm.c
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > +*/
> > +
> > +static inline void s3c_pm_debug_init_uart(void)
> > +{
> > +	/* nothing here yet */
> > +}
> > +
> > +static inline void s3c_pm_arch_prepare_irqs(void)
> > +{
> > +	__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
> > +	__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
> > +}
> > +
> > +static inline void s3c_pm_arch_stop_clocks(void)
> > +{
> > +	/* nothing here yet */
> > +}
> > +
> > +static inline void s3c_pm_arch_show_resume_irqs(void)
> > +{
> > +	/* nothing here yet */
> > +}
> > +
> > +static inline void s3c_pm_arch_update_uart(void __iomem *regs,
> > +					   struct pm_uart_save *save)
> > +{
> > +	/* nothing here yet */
> > +}
> > +
> > diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
b/arch/arm/mach-
> s5pv210/include/mach/regs-clock.h
> > index 2a25ab4..f4a443a 100644
> > --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
> > +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
> > @@ -157,8 +157,11 @@
> >  #define S5P_SLEEP_CFG_USBOSC_EN		(1 << 1)
> >
> >  /* OTHERS Resgister */
> > +#define S5P_OTHERS_RET_IO		(1 << 31)
> > +#define S5P_OTHERS_RET_CF		(1 << 30)
> > +#define S5P_OTHERS_RET_MMC		(1 << 29)
> > +#define S5P_OTHERS_RET_UART		(1 << 28)
> >  #define S5P_OTHERS_USB_SIG_MASK		(1 << 16)
> > -#define S5P_OTHERS_MIPI_DPHY_EN		(1 << 28)
> >
> >  /* MIPI */
> >  #define S5P_MIPI_DPHY_EN		(3)
> > diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-
> s5pv210/mach-smdkc110.c
> > index 4c8903c..ebb4832 100644
> > --- a/arch/arm/mach-s5pv210/mach-smdkc110.c
> > +++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
> > @@ -25,6 +25,7 @@
> >  #include <plat/s5pv210.h>
> >  #include <plat/devs.h>
> >  #include <plat/cpu.h>
> > +#include <plat/pm.h>
> >
> >  /* Following are default values for UCON, ULCON and UFCON UART registers
*/
> >  #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
> > @@ -86,6 +87,7 @@ static void __init smdkc110_map_io(void)
> >
> >  static void __init smdkc110_machine_init(void)
> >  {
> > +	s3c_pm_init();
> >  	platform_add_devices(smdkc110_devices,
> ARRAY_SIZE(smdkc110_devices));
> >  }
> >
> > diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-
> s5pv210/mach-smdkv210.c
> > index 0d46279..ba30b5d 100644
> > --- a/arch/arm/mach-s5pv210/mach-smdkv210.c
> > +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
> > @@ -27,6 +27,7 @@
> >  #include <plat/cpu.h>
> >  #include <plat/adc.h>
> >  #include <plat/ts.h>
> > +#include <plat/pm.h>
> >
> >  /* Following are default values for UCON, ULCON and UFCON UART registers
*/
> >  #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
> > @@ -96,6 +97,8 @@ static void __init smdkv210_map_io(void)
> >
> >  static void __init smdkv210_machine_init(void)
> >  {
> > +	s3c_pm_init();
> > +
> >  	s3c24xx_ts_set_platdata(&s3c_ts_platform);
> >  	platform_add_devices(smdkv210_devices,
> ARRAY_SIZE(smdkv210_devices));
> >  }
> > diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
> > new file mode 100644
> > index 0000000..0690332
> > --- /dev/null
> > +++ b/arch/arm/mach-s5pv210/pm.c
> > @@ -0,0 +1,180 @@
> > +/* linux/arch/arm/mach-s5pv210/pm.c
> > + *
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com
> > + *
> > + * S5PV210 - Power Management support
> > + *
> > + * Based on arch/arm/mach-s3c2410/pm.c
> > + * Copyright (c) 2006 Simtec Electronics
> > + *	Ben Dooks <ben at simtec.co.uk>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > +*/
> > +
> > +#include <linux/init.h>
> > +#include <linux/suspend.h>
> > +#include <linux/io.h>
> > +
> > +#include <plat/cpu.h>
> > +#include <plat/pm.h>
> > +#include <plat/regs-timer.h>
> > +
> > +#include <mach/regs-irq.h>
> > +#include <mach/regs-clock.h>
> > +
> > +static struct sleep_save s5pv210_core_save[] = {
> > +	/* Clock source */
> > +	SAVE_ITEM(S5P_CLK_SRC0),
> > +	SAVE_ITEM(S5P_CLK_SRC1),
> > +	SAVE_ITEM(S5P_CLK_SRC2),
> > +	SAVE_ITEM(S5P_CLK_SRC3),
> > +	SAVE_ITEM(S5P_CLK_SRC4),
> > +	SAVE_ITEM(S5P_CLK_SRC5),
> > +	SAVE_ITEM(S5P_CLK_SRC6),
> > +
> > +	/* Clock source Mask */
> > +	SAVE_ITEM(S5P_CLK_SRC_MASK0),
> > +	SAVE_ITEM(S5P_CLK_SRC_MASK1),
> > +
> > +	/* Clock Divider */
> > +	SAVE_ITEM(S5P_CLK_DIV0),
> > +	SAVE_ITEM(S5P_CLK_DIV1),
> > +	SAVE_ITEM(S5P_CLK_DIV2),
> > +	SAVE_ITEM(S5P_CLK_DIV3),
> > +	SAVE_ITEM(S5P_CLK_DIV4),
> > +	SAVE_ITEM(S5P_CLK_DIV5),
> > +	SAVE_ITEM(S5P_CLK_DIV6),
> > +	SAVE_ITEM(S5P_CLK_DIV7),
> > +
> > +	/* Clock Main Gate */
> > +	SAVE_ITEM(S5P_CLKGATE_MAIN0),
> > +	SAVE_ITEM(S5P_CLKGATE_MAIN1),
> > +	SAVE_ITEM(S5P_CLKGATE_MAIN2),
> > +
> > +	/* Clock source Peri Gate */
> > +	SAVE_ITEM(S5P_CLKGATE_PERI0),
> > +	SAVE_ITEM(S5P_CLKGATE_PERI1),
> > +
> > +	/* Clock source SCLK Gate */
> > +	SAVE_ITEM(S5P_CLKGATE_SCLK0),
> > +	SAVE_ITEM(S5P_CLKGATE_SCLK1),
> > +
> > +	/* Clock IP Clock gate */
> > +	SAVE_ITEM(S5P_CLKGATE_IP0),
> > +	SAVE_ITEM(S5P_CLKGATE_IP1),
> > +	SAVE_ITEM(S5P_CLKGATE_IP2),
> > +	SAVE_ITEM(S5P_CLKGATE_IP3),
> > +	SAVE_ITEM(S5P_CLKGATE_IP4),
> > +
> > +	/* Clock Blcok and Bus gate */
> > +	SAVE_ITEM(S5P_CLKGATE_BLOCK),
> > +	SAVE_ITEM(S5P_CLKGATE_BUS0),
> > +
> > +	/* Clock ETC */
> > +	SAVE_ITEM(S5P_CLK_OUT),
> > +	SAVE_ITEM(S5P_MDNIE_SEL),
> > +
> > +	/* PWM Register */
> > +	SAVE_ITEM(S3C2410_TCFG0),
> > +	SAVE_ITEM(S3C2410_TCFG1),
> > +	SAVE_ITEM(S3C64XX_TINT_CSTAT),
> > +	SAVE_ITEM(S3C2410_TCON),
> > +	SAVE_ITEM(S3C2410_TCNTB(0)),
> > +	SAVE_ITEM(S3C2410_TCMPB(0)),
> > +	SAVE_ITEM(S3C2410_TCNTO(0)),
> > +
> > +	/* VIC 2 and 3*/
> > +	SAVE_ITEM(VA_VIC2 + VIC_INT_SELECT),
> > +	SAVE_ITEM(VA_VIC3 + VIC_INT_SELECT),
> > +	SAVE_ITEM(VA_VIC2 + VIC_INT_ENABLE),
> > +	SAVE_ITEM(VA_VIC3 + VIC_INT_ENABLE),
> > +	SAVE_ITEM(VA_VIC2 + VIC_INT_SOFT),
> > +	SAVE_ITEM(VA_VIC3 + VIC_INT_SOFT),
> 
> doesn't the vic driver do this for you? if not, then would be better
> to change the vic to fix this.
> 
Yes, right..will remove it.

> > +};
> > +
> > +void s5pv210_cpu_suspend(void)
> > +{
> > +	unsigned long tmp;
> > +
> > +	/* issue the standby signal into the pm unit. Note, we
> > +	 * issue a write-buffer drain just in case */
> > +
> > +	tmp = 0;
> > +
> > +	asm("b 1f\n\t"
> > +	    ".align 5\n\t"
> > +	    "1:\n\t"
> > +	    "mcr p15, 0, %0, c7, c10, 5\n\t"
> > +	    "mcr p15, 0, %0, c7, c10, 4\n\t"
> > +	    ".word 0xe320f003" : : "r" (tmp));
> 
> why .word? if there's a compiler problem then make a comment about
> what instruction is being synthesised and why.
> 
OK..will modify it.

> > +	/* we should never get past here */
> > +	panic("sleep resumed to originator?");
> > +}
> > +
> > +static void s5pv210_pm_prepare(void)
> > +{
> > +	unsigned int tmp;
> > +
> > +	/* ensure at least INFORM0 has the resume address */
> > +	__raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
> > +
> > +	tmp = __raw_readl(S5P_SLEEP_CFG);
> > +	tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
> > +	__raw_writel(tmp, S5P_SLEEP_CFG);
> > +
> > +	/* WFI for SLEEP mode configuration by SYSCON */
> > +	tmp = __raw_readl(S5P_PWR_CFG);
> > +	tmp &= S5P_CFG_WFI_CLEAN;
> > +	tmp |= S5P_CFG_WFI_SLEEP;
> > +	__raw_writel(tmp, S5P_PWR_CFG);
> > +
> > +	/* SYSCON interrupt handling disable */
> > +	tmp = __raw_readl(S5P_OTHERS);
> > +	tmp |= S5P_OTHER_SYSC_INTOFF;
> > +	__raw_writel(tmp, S5P_OTHERS);
> > +
> > +	__raw_writel(0xffffffff, (VA_VIC0 + VIC_INT_ENABLE_CLEAR));
> > +	__raw_writel(0xffffffff, (VA_VIC1 + VIC_INT_ENABLE_CLEAR));
> > +	__raw_writel(0xffffffff, (VA_VIC2 + VIC_INT_ENABLE_CLEAR));
> > +	__raw_writel(0xffffffff, (VA_VIC3 + VIC_INT_ENABLE_CLEAR));
> > +
> > +	s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
> > +}
> > +
> > +static int s5pv210_pm_add(struct sys_device *sysdev)
> > +{
> > +	pm_cpu_prep = s5pv210_pm_prepare;
> > +	pm_cpu_sleep = s5pv210_cpu_suspend;
> > +
> > +	return 0;
> > +}
> > +
> > +static int s5pv210_pm_resume(struct sys_device *dev)
> > +{
> > +	u32 tmp;
> > +
> > +	tmp = __raw_readl(S5P_OTHERS);
> > +	tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF |	\
> > +		S5P_OTHERS_RET_MMC | S5P_OTHERS_RET_UART);
> > +	__raw_writel(tmp , S5P_OTHERS);
> > +
> > +	s3c_pm_do_restore_core(s5pv210_core_save,
> ARRAY_SIZE(s5pv210_core_save));
> > +
> > +	return 0;
> > +}
> > +
> > +static struct sysdev_driver s5pv210_pm_driver = {
> > +	.add		= s5pv210_pm_add,
> > +	.resume		= s5pv210_pm_resume,
> > +};
> > +
> > +static __init int s5pv210_pm_drvinit(void)
> > +{
> > +	return sysdev_driver_register(&s5pv210_sysclass, &s5pv210_pm_driver);
> > +}
> > +arch_initcall(s5pv210_pm_drvinit);
> > diff --git a/arch/arm/mach-s5pv210/sleep.S
b/arch/arm/mach-s5pv210/sleep.S
> > new file mode 100644
> > index 0000000..b7f8272
> > --- /dev/null
> > +++ b/arch/arm/mach-s5pv210/sleep.S
> > @@ -0,0 +1,166 @@
> > +/* linux/arch/arm/mach-s5pv210/sleep.S
> > + *
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com
> > + *
> > + * S5PV210 power Manager (Suspend-To-RAM) support
> > + *
> > + * Based on S3C2410 sleep code by:
> > + * 	Ben Dooks, (c) 2004 Simtec Electronics
> > + *
> > + * Based on PXA/SA1100 sleep code by:
> > + *	Nicolas Pitre, (c) 2002 Monta Vista Software Inc
> > + *	Cliff Brake, (c) 2001
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License as published by
> > + * the Free Software Foundation; either version 2 of the License, or
> > + * (at your option) any later version.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > + * GNU General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU General Public License
> > + * along with this program; if not, write to the Free Software
> > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307
USA
> > +*/
> > +
> > +#include <linux/linkage.h>
> > +#include <asm/assembler.h>
> > +#include <asm/memory.h>
> > +
> > +	.text
> > +
> > +	/* s3c_cpu_save
> > +	 *
> > +	 * entry:
> > +	 *	r0 = save address (virtual addr of s3c_sleep_save_phys)
> > +	*/
> > +
> > +ENTRY(s3c_cpu_save)
> > +
> > +	stmfd	sp!, { r3 - r12, lr }
> > +
> > +	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
> > +	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
> > +	mrc	p15, 0, r6, c2, c0, 0	@ Translation Table BASE0
> > +	mrc	p15, 0, r7, c2, c0, 1	@ Translation Table BASE1
> > +	mrc	p15, 0, r8, c2, c0, 2	@ Translation Table Control
> > +	mrc	p15, 0, r9, c1, c0, 0	@ Control register
> > +	mrc	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
> > +	mrc	p15, 0, r11, c1, c0, 2	@ Co-processor access controls
> > +	mrc	p15, 0, r12, c10, c2, 0	@ Read PRRR
> > +	mrc	p15, 0, r3, c10, c2, 1	@ READ NMRR
> > +
> > +	stmia	r0, { r3 - r13 }
> > +
> > +	bl	s3c_pm_cb_flushcache
> > +
> > +	ldr	r0, =pm_cpu_sleep
> > +	ldr	r0, [ r0 ]
> > +	mov	pc, r0
> > +
> > +resume_with_mmu:
> > +	/* delete added mmu table list */
> 
> hmm, where is this being added?
> also, a better description on what it is doing would be better.
> 
OK..will add detail description.

> > +	ldr	r9 , =(PAGE_OFFSET - PHYS_OFFSET)
> > +	add	r4, r4, r9
> > +	str	r12, [r4]
> > +
> > +	ldmfd	sp!, { r3 - r12, pc }
> > +
> > +	.ltorg
> > +
> > +	.data
> > +
> > +	.global	s3c_sleep_save_phys
> > +s3c_sleep_save_phys:
> > +	.word	0
> > +
> > +	/* sleep magic, to allow the bootloader to check for an valid
> > +	 * image to resume to. Must be the first word before the
> > +	 * s3c_cpu_resume entry.
> > +	*/
> > +
> > +	.word	0x2bedf00d
> > +
> > +	/* s3c_cpu_resume
> > +	 *
> > +	 * resume code entry for bootloader to call
> > +	 *
> > +	 * we must put this code here in the data segment as we have no
> > +	 * other way of restoring the stack pointer after sleep, and we
> > +	 * must not write to the code segment (code is read-only)
> > +	*/
> > +
> > +ENTRY(s3c_cpu_resume)
> > +	mov	r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
> > +	msr	cpsr_c, r0
> > +
> > +	mov	r1, #0
> > +	mcr	p15, 0, r1, c8, c7, 0		@@ invalidate TLBs
> > +	mcr	p15, 0, r1, c7, c5, 0		@@ invalidate I Cache
> > +
> > +	ldr	r0, s3c_sleep_save_phys		@ address of restore block
> > +	ldmia	r0, { r3 - r13 }
> > +
> > +	mcr	p15, 0, r4, c13, c0, 0		@ FCSE/PID
> > +	mcr	p15, 0, r5, c3, c0, 0		@ Domain ID
> > +
> > +	mcr	p15, 0, r8, c2, c0, 2		@ Translation Table Control
> > +	mcr	p15, 0, r7, c2, c0, 1		@ Translation Table BASE1
> > +	mcr	p15, 0, r6, c2, c0, 0		@ Translation Table BASE0
> > +
> > +	mcr	p15, 0, r10, c1, c0, 1		@ Auxiliary control register
> > +
> > +	mov	r0, #0
> > +	mcr	p15, 0, r0, c8, c7, 0		@ Invalidate I & D TLB
> > +
> > +	mov	r0, #0				@ restore copro access
> > +	mcr	p15, 0, r11, c1, c0, 2		@ Co-processor access
> > +	mcr 	p15, 0, r0, c7, c5, 4
> > +
> > +	mcr	p15, 0, r12, c10, c2, 0		@ write PRRR
> > +	mcr	p15, 0, r3, c10, c2, 1		@ write NMRR
> > +
> > +	/* Calculate first section address into r8
> > +	 * In Cotex-A8 case, When MMU turn on, MMU is reseted.
> 
> i'd fix this typo.
> 
Yeah, will fix this typo.

> > +	 * So, before call resume_with_mmu, backup originally data.
> > +	*/
> > +
> > +	mov	r4, r6
> > +	mov	r4, r4, LSR #14
> > +	mov	r4, r4, LSL #14
> > +
> > +	/* Load TLB Base address from INFORM0 */
> 
> do you mean mmu page table?
> 
yes..but need to add detailed description.

> > +	ldr	r11, =0xe010f000
> > +	ldr	r10, [r11, #0]
> > +	mov	r10, r10, LSR #18
> > +	bic	r10, r10, #0x3
> > +	orr	r4, r4, r10
> > +
> > +	/* calculate mmu list value into r9 */
> > +	mov 	r10, r10, LSL #18
> > +	ldr	r5, =0x40e
> > +	orr	r10, r10, r5
> > +
> > +	/* back up originally data */
> > +
> > +	ldr	r12, [r4]
> > +
> > +	/* Added list about mmu */
> > +	str	r10, [r4]
> 
> 
> 
> > +	ldr	r2, =resume_with_mmu
> > +	mcr	p15, 0, r9, c1, c0, 0		@ turn on MMU, etc
> > +
> > +	nop
> > +	nop
> > +	nop
> > +	nop
> > +	nop					@ second-to-last before mmu
> > +
> > +	mov	pc, r2				@ go back to virtual address
> > +
> > +	.ltorg
> > diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
> > index 39c242b..d04ae49 100644
> > --- a/arch/arm/plat-s5p/Makefile
> > +++ b/arch/arm/plat-s5p/Makefile
> > @@ -18,3 +18,5 @@ obj-y				+= clock.o
> >  obj-y				+= irq.o
> >  obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
> >
> > +obj-$(CONFIG_PM)		+= pm.o
> > +obj-$(CONFIG_PM)		+= irq-pm.o
> > diff --git a/arch/arm/plat-s5p/include/plat/irqs.h b/arch/arm/plat-
> s5p/include/plat/irqs.h
> > index 3fb3a3a..9ffdd62 100644
> > --- a/arch/arm/plat-s5p/include/plat/irqs.h
> > +++ b/arch/arm/plat-s5p/include/plat/irqs.h
> > @@ -94,4 +94,6 @@
> >  						((irq) - S5P_EINT_BASE1) : \
> >  						((irq) + 16 -
> S5P_EINT_BASE2))
> >
> > +#define IRQ_EINT_BIT(x)		EINT_OFFSET(x)
> > +
> >  #endif /* __ASM_PLAT_S5P_IRQS_H */
> > diff --git a/arch/arm/plat-s5p/irq-pm.c b/arch/arm/plat-s5p/irq-pm.c
> > new file mode 100644
> > index 0000000..03e83a3
> > --- /dev/null
> > +++ b/arch/arm/plat-s5p/irq-pm.c
> > @@ -0,0 +1,108 @@
> > +/* linux/arch/arm/plat-s5p/irq-pm.c
> > + *
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com
> > + *
> > + * Based on arch/arm/plat-s3c24xx/irq-pm.c,
> > + * Copyright (c) 2003,2004 Simtec Electronics
> > + *	Ben Dooks <ben at simtec.co.uk>
> > + *	http://armlinux.simtec.co.uk/
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > +*/
> > +
> > +#include <linux/init.h>
> > +#include <linux/module.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/sysdev.h>
> > +
> > +#include <plat/cpu.h>
> > +#include <plat/irqs.h>
> > +#include <plat/pm.h>
> > +#include <mach/map.h>
> > +
> > +#include <mach/regs-gpio.h>
> > +#include <mach/regs-irq.h>
> > +
> > +/* state for IRQs over sleep */
> > +
> > +/* default is to allow for EINT0..EINT31, and IRQ_RTC_TIC,
IRQ_RTC_ALARM,
> > + * as wakeup sources
> > + *
> > + * set bit to 1 in allow bitfield to enable the wakeup settings on it
> > +*/
> > +
> > +unsigned long s3c_irqwake_intallow	= 0x00000006L;
> > +unsigned long s3c_irqwake_eintallow	= 0xffffffffL;
> > +
> > +int s3c_irq_wake(unsigned int irqno, unsigned int state)
> > +{
> > +	unsigned long irqbit;
> > +
> > +	switch (irqno) {
> > +	case IRQ_RTC_TIC:
> > +	case IRQ_RTC_ALARM:
> > +		irqbit = 1 << (irqno + 1 - IRQ_RTC_ALARM);
> > +		if (!state)
> > +			s3c_irqwake_intmask |= irqbit;
> > +		else
> > +			s3c_irqwake_intmask &= ~irqbit;
> > +		break;
> > +	default:
> > +		return -ENOENT;
> > +	}
> > +	return 0;
> > +}
> > +
> > +/* this lot should be really saved by the IRQ code */
> > +/* VICXADDRESSXX initilaization to be needed */
> > +static struct sleep_save irq_save[] = {
> > +	SAVE_ITEM(VA_VIC0 + VIC_INT_SELECT),
> > +	SAVE_ITEM(VA_VIC1 + VIC_INT_SELECT),
> > +
> > +	SAVE_ITEM(VA_VIC0 + VIC_INT_ENABLE),
> > +	SAVE_ITEM(VA_VIC1 + VIC_INT_ENABLE),
> > +
> > +	SAVE_ITEM(VA_VIC0 + VIC_INT_SOFT),
> > +	SAVE_ITEM(VA_VIC1 + VIC_INT_SOFT),
> > +};
> > +
> > +static struct sleep_save eint_save[] = {
> > +	SAVE_ITEM(S5P_EINT_CON(0)),
> > +	SAVE_ITEM(S5P_EINT_CON(1)),
> > +	SAVE_ITEM(S5P_EINT_CON(2)),
> > +	SAVE_ITEM(S5P_EINT_CON(3)),
> > +
> > +	SAVE_ITEM(S5P_EINT_FLTCON(0)),
> > +	SAVE_ITEM(S5P_EINT_FLTCON(1)),
> > +	SAVE_ITEM(S5P_EINT_FLTCON(2)),
> > +	SAVE_ITEM(S5P_EINT_FLTCON(3)),
> > +	SAVE_ITEM(S5P_EINT_FLTCON(4)),
> > +	SAVE_ITEM(S5P_EINT_FLTCON(5)),
> > +	SAVE_ITEM(S5P_EINT_FLTCON(6)),
> > +	SAVE_ITEM(S5P_EINT_FLTCON(7)),
> > +
> > +	SAVE_ITEM(S5P_EINT_MASK(0)),
> > +	SAVE_ITEM(S5P_EINT_MASK(1)),
> > +	SAVE_ITEM(S5P_EINT_MASK(2)),
> > +	SAVE_ITEM(S5P_EINT_MASK(3)),
> > +};
> > +
> > +int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state)
> > +{
> > +	s3c_pm_do_save(eint_save, ARRAY_SIZE(eint_save));
> > +	s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
> > +
> > +	return 0;
> > +}
> > +
> > +int s3c24xx_irq_resume(struct sys_device *dev)
> > +{
> > +	s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
> > +	s3c_pm_do_restore(eint_save, ARRAY_SIZE(eint_save));
> > +
> > +	return 0;
> > +}
> > +
> > diff --git a/arch/arm/plat-s5p/pm.c b/arch/arm/plat-s5p/pm.c
> > new file mode 100644
> > index 0000000..d592b63
> > --- /dev/null
> > +++ b/arch/arm/plat-s5p/pm.c
> > @@ -0,0 +1,52 @@
> > +/* linux/arch/arm/plat-s5p/pm.c
> > + *
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com
> > + *
> > + * S5P Power Manager (Suspend-To-RAM) support
> > + *
> > + * Based on arch/arm/plat-s3c24xx/pm.c
> > + * Copyright (c) 2004,2006 Simtec Electronics
> > + *	Ben Dooks <ben at simtec.co.uk>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > +*/
> > +
> > +#include <linux/suspend.h>
> > +#include <plat/pm.h>
> > +
> > +#define PFX "s5p pm: "
> > +
> > +/* s3c_pm_check_resume_pin
> > + *
> > + * check to see if the pin is configured correctly for sleep mode, and
> > + * make any necessary adjustments if it is not
> > +*/
> > +
> > +static void s3c_pm_check_resume_pin(unsigned int pin, unsigned int
irqoffs)
> > +{
> > +	/* nothing here yet */
> > +}
> > +
> > +/* s3c_pm_configure_extint
> > + *
> > + * configure all external interrupt pins
> > +*/
> > +
> > +void s3c_pm_configure_extint(void)
> > +{
> > +	/* nothing here yet */
> > +}
> > +
> > +void s3c_pm_restore_core(void)
> > +{
> > +	/* nothing here yet */
> > +}
> > +
> > +void s3c_pm_save_core(void)
> > +{
> > +	/* nothing here yet */
> > +}
> > +
> > diff --git a/arch/arm/plat-samsung/pm-gpio.c
b/arch/arm/plat-samsung/pm-gpio.c
> > index 7df03f8..9652820 100644
> > --- a/arch/arm/plat-samsung/pm-gpio.c
> > +++ b/arch/arm/plat-samsung/pm-gpio.c
> > @@ -192,7 +192,7 @@ struct s3c_gpio_pm s3c_gpio_pm_2bit = {
> >  	.resume = s3c_gpio_pm_2bit_resume,
> >  };
> >
> > -#ifdef CONFIG_ARCH_S3C64XX
> > +#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P)
> >  static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
> >  {
> >  	chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
> > @@ -302,7 +302,7 @@ struct s3c_gpio_pm s3c_gpio_pm_4bit = {
> >  	.save	= s3c_gpio_pm_4bit_save,
> >  	.resume = s3c_gpio_pm_4bit_resume,
> >  };
> > -#endif /* CONFIG_ARCH_S3C64XX */
> > +#endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */
> >
> >  /**
> >   * s3c_pm_save_gpio() - save gpio chip data for suspend
> > --
> > 1.6.2.5
> >

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From ben-linux at fluff.org  Thu Jun  3 04:46:03 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Thu, 3 Jun 2010 09:46:03 +0100
Subject: [PATCH] i2c: Enable i2c-s3c2410 for S5P cpus
In-Reply-To: <1275544623-5425-1-git-send-email-jy0922.shim@samsung.com>
References: <1275544623-5425-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <20100603084603.GB4720@trinity.fluff.org>

On Thu, Jun 03, 2010 at 02:57:03PM +0900, Joonyoung Shim wrote:
> This i2c controller driver can be used on the S5P series processors too,
> so enable the driver in Konfig for those platforms.
> 
> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  drivers/i2c/busses/Kconfig |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index 87ab056..4765d62 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -503,7 +503,7 @@ config I2C_PXA_SLAVE
>  
>  config I2C_S3C2410
>  	tristate "S3C2410 I2C Driver"
> -	depends on ARCH_S3C2410 || ARCH_S3C64XX
> +	depends on ARCH_S3C2410 || ARCH_S3C64XX || PLAT_S5P

It may be worth changing this to PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P
or maybe we should just enable it if PLAT_SAMSUNG

It would be good to get an policy sorted out on these core drivers which
exists across many parts of S3C/S5P supported systems.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From linus.ml.walleij at gmail.com  Thu Jun  3 04:48:42 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Thu, 3 Jun 2010 10:48:42 +0200
Subject: PB1176 broken in 2.6.35-rc1, bisected
In-Reply-To: <1275518783.27834.2.camel@e102109-lin.cambridge.arm.com>
References: <AANLkTikoCy2FH_5ICh-iiI_wzGj6D6oszyM-zCXkNC_4@mail.gmail.com>
	<1275518783.27834.2.camel@e102109-lin.cambridge.arm.com>
Message-ID: <AANLkTimJkaadEM1xvG30WVvEjJPZQXHwx216SeqWFKNp@mail.gmail.com>

2010/6/3 Catalin Marinas <catalin.marinas at arm.com>:
> On Wed, 2010-06-02 at 23:33 +0100, Linus Walleij wrote:
>> my PB1176 doesn't boot properly in 2.6.35-rc1, it goes to this point
>> and hangs:
>>
>> (...)
>> Switching to clocksource timer3
>> NET: Registered protocol family 2
>> IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
>> TCP established hash table entries: 4096 (order: 3, 32768 bytes)
>> TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
>> TCP: Hash tables configured (established 4096 bind 4096)
>> TCP reno registered
>> UDP hash table entries: 256 (order: 0, 4096 bytes)
>> UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
>> NET: Registered protocol family 1
>> RPC: Registered udp transport module.
>> RPC: Registered tcp transport module.
>> RPC: Registered tcp NFSv4.1 backchannel transport module.
>
> Have you tried disabling CONFIG_CACHE_L2X0?

Hey it works! :-)

I suppose your latest patches will hopefully  get the defconfig with
l2x0 working again in -rc2 if they're merged?

Linus Walleij


From philippe.retornaz at epfl.ch  Thu Jun  3 05:23:18 2010
From: philippe.retornaz at epfl.ch (Philippe =?iso-8859-15?q?R=E9tornaz?=)
Date: Thu, 3 Jun 2010 11:23:18 +0200
Subject: [PATCH 2/2] mx31moboard: Add MC13783 power button support
In-Reply-To: <20100603083155.GW26820@pengutronix.de>
References: <1275334140-29339-1-git-send-email-philippe.retornaz@epfl.ch>
	<1275334140-29339-3-git-send-email-philippe.retornaz@epfl.ch>
	<20100603083155.GW26820@pengutronix.de>
Message-ID: <201006031123.18676.philippe.retornaz@epfl.ch>

Le jeudi, 3 juin 2010 10.31:55, Sascha Hauer a ?crit :
> Hi Philippe,
> 
> Please ping me once the LED/Power button support is merged. I'll take
> care of the platform patches.

Thanks, I'll try to produce a new patch ASAP (maybe next week).

Regards,

Philippe


From eric.miao at canonical.com  Thu Jun  3 05:43:33 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu,  3 Jun 2010 17:43:33 +0800
Subject: [PATCH 0/2] Introduce RUNTIME_PHYS_OFFSET
Message-ID: <1275558215-12743-1-git-send-email-eric.miao@canonical.com>

Thanks for the Original great work of Uwe Kleine-K?nig, I'm now
able to boot the resulting kernel without PHYS_OFFSET being
defined on my pxa machines.

Uwe,

I've modified a bit into your patch, hopefully to make it look
a bit cleaner. Please help review.



From eric.miao at canonical.com  Thu Jun  3 05:43:34 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu,  3 Jun 2010 17:43:34 +0800
Subject: [PATCH 1/2] [ARM] Make __create_page_table to accept phys_offset in a
	register
In-Reply-To: <1275558215-12743-1-git-send-email-eric.miao@canonical.com>
References: <1275558215-12743-1-git-send-email-eric.miao@canonical.com>
Message-ID: <1275558215-12743-2-git-send-email-eric.miao@canonical.com>

From: Eric Miao <eric.y.miao at gmail.com>

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/kernel/head.S |   17 ++++++++++-------
 1 files changed, 10 insertions(+), 7 deletions(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..db789fb 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -44,8 +44,12 @@
 	.globl	swapper_pg_dir
 	.equ	swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
 
-	.macro	pgtbl, rd
-	ldr	\rd, =(KERNEL_RAM_PADDR - 0x4000)
+	.macro	pgtbl, rd, phys_offset
+	add	\rd, \phys_offset, #(TEXT_OFFSET - 0x4000)
+	.endm
+
+	.macro	get_phys_offset, rd
+	ldr	\rd, =(PHYS_OFFSET & 0xfff00000)
 	.endm
 
 #ifdef CONFIG_XIP_KERNEL
@@ -86,6 +90,7 @@ ENTRY(stext)
 	movs	r8, r5				@ invalid machine (r5=0)?
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
+	get_phys_offset r5
 	bl	__create_page_tables
 
 	/*
@@ -215,9 +220,10 @@ ENDPROC(__turn_mmu_on)
  * Returns:
  *  r0, r3, r6, r7 corrupted
  *  r4 = physical page table address
+ *  r5 = physical address of memory start
  */
 __create_page_tables:
-	pgtbl	r4				@ page table address
+	pgtbl	r4, r5				@ page table address
 
 	/*
 	 * Clear the 16K level 1 swapper page table
@@ -282,10 +288,7 @@ __create_page_tables:
 	 * Then map first 1MB of ram in case it contains our boot params.
 	 */
 	add	r0, r4, #PAGE_OFFSET >> 18
-	orr	r6, r7, #(PHYS_OFFSET & 0xff000000)
-	.if	(PHYS_OFFSET & 0x00f00000)
-	orr	r6, r6, #(PHYS_OFFSET & 0x00f00000)
-	.endif
+	orr	r6, r5, r7
 	str	r6, [r0]
 
 #ifdef CONFIG_DEBUG_LL
-- 
1.7.0.4



From eric.miao at canonical.com  Thu Jun  3 05:43:35 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu,  3 Jun 2010 17:43:35 +0800
Subject: [PATCH 2/2] [ARM] Allow PHYS_OFFSET to be runtime determined
In-Reply-To: <1275558215-12743-1-git-send-email-eric.miao@canonical.com>
References: <1275558215-12743-1-git-send-email-eric.miao@canonical.com>
Message-ID: <1275558215-12743-3-git-send-email-eric.miao@canonical.com>

From: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

Original patch from: "Uwe Kleine-K?nig" <u.kleine-koenig at pengutronix.de>

Changes to the original patch:

1. simplify the algorithm of getting phys_offset by masking PC with
   0xf000_0000, this works for most platforms, but we can possibly
   loosen this restriction to 0xf800_0000 or 0xfc00_0000 to cover
   more platforms like ARCH_MX1/ARCH_SHARK and ARCH_S3C2400. It is
   a bit more difficult to support the U300 platform though.

2. Assigning 0xdeadbeef to phys_offset might be a bit hackish,
   explicitly specify the section for it.

3. Make RUNTIME_PHYS_OFFSET a toggle-able option in case someone
   want to manually enable or disable it. And make it valid only
   when MMU is enabled and XIP_KERNEL is disabled.

Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Steve Chen <schen at mvista.com>
Cc: Mark A. Greer <mgreer at mvista.com>
Cc: Kevin Hilman <khilman at deeprootsystems.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/Kconfig              |    9 +++++++++
 arch/arm/include/asm/memory.h |    6 ++++++
 arch/arm/kernel/head.S        |   14 +++++++++++++-
 arch/arm/kernel/setup.c       |   10 +++++++++-
 4 files changed, 37 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 818f731..add2c15 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1498,6 +1498,15 @@ config TEXT_OFFSET
 	  memory start. Currently, it is expected the least significant 16
 	  bits to be 0x8000, so to leave space for the initial page table.
 
+config RUNTIME_PHYS_OFFSET
+	bool "Auto calculate the physical address of the memory start"
+	depends on MMU && !XIP_KERNEL
+	help
+	  PHYS_OFFSET can be automatically caculated at run time by
+	  masking the PC with 0xf0000000 if the memory starts at 256MB
+	  boundary (most platforms do). Do not select this option if
+	  it is not a correct assumption on your platform.
+
 config AUTO_ZRELADDR
 	bool "Auto calculation of the decompressed kernel image address"
 	depends on !ZBOOT_ROM && !(ARCH_MX1 || ARCH_SHARK || ARCH_U300)
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 4312ee5..fb18aff 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -147,6 +147,12 @@
 
 #ifndef __ASSEMBLY__
 
+#ifdef CONFIG_RUNTIME_PHYS_OFFSET
+extern unsigned long phys_offset;
+#undef  PHYS_OFFSET
+#define PHYS_OFFSET	phys_offset
+#endif
+
 /*
  * The DMA mask corresponding to the maximum bus address allocatable
  * using GFP_DMA.  The default here places no restriction on DMA
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index db789fb..c77db05 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -22,7 +22,7 @@
 #include <asm/thread_info.h>
 #include <asm/system.h>
 
-#if (PHYS_OFFSET & 0x001fffff)
+#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) && (PHYS_OFFSET & 0x001fffff)
 #error "PHYS_OFFSET must be at an even 2MiB boundary!"
 #endif
 
@@ -48,9 +48,15 @@
 	add	\rd, \phys_offset, #(TEXT_OFFSET - 0x4000)
 	.endm
 
+#ifndef CONFIG_RUNTIME_PHYS_OFFSET
 	.macro	get_phys_offset, rd
 	ldr	\rd, =(PHYS_OFFSET & 0xfff00000)
 	.endm
+#else
+	.macro	get_phys_offset, rd
+	and	\rd, pc, #0xf0000000
+	.endm
+#endif
 
 #ifdef CONFIG_XIP_KERNEL
 #define KERNEL_START	XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
@@ -332,6 +338,12 @@ __create_page_tables:
 	str	r3, [r0]
 #endif
 #endif
+
+#ifdef CONFIG_RUNTIME_PHYS_OFFSET
+	@ save to __phys_to_virt(phys_offset)
+	ldr	r0, =(phys_offset - PAGE_OFFSET)
+	str	r5, [r0, r5]
+#endif
 	mov	pc, lr
 ENDPROC(__create_page_tables)
 	.ltorg
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 122d999..e11fdb7 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -105,6 +105,12 @@ struct cpu_cache_fns cpu_cache;
 struct outer_cache_fns outer_cache;
 EXPORT_SYMBOL(outer_cache);
 #endif
+#ifdef CONFIG_RUNTIME_PHYS_OFFSET
+/* prevent phys_offset from being end up in bss */
+unsigned long phys_offset __attribute__(section(".data"));
+EXPORT_SYMBOL(phys_offset);
+#endif
+
 
 struct stack {
 	u32 irq[3];
@@ -648,7 +654,7 @@ static struct init_tags {
 	{ tag_size(tag_core), ATAG_CORE },
 	{ 1, PAGE_SIZE, 0xff },
 	{ tag_size(tag_mem32), ATAG_MEM },
-	{ MEM_SIZE, PHYS_OFFSET },
+	{ MEM_SIZE, },
 	{ 0, ATAG_NONE }
 };
 
@@ -678,6 +684,8 @@ void __init setup_arch(char **cmdline_p)
 	if (mdesc->soft_reboot)
 		reboot_setup("s");
 
+	init_tags.mem.start = PHYS_OFFSET;
+
 	if (__atags_pointer)
 		tags = phys_to_virt(__atags_pointer);
 	else if (mdesc->boot_params)
-- 
1.7.0.4



From yegor_sub1 at visionsystems.de  Thu Jun  3 05:44:57 2010
From: yegor_sub1 at visionsystems.de (Yegor Yefremov)
Date: Thu, 03 Jun 2010 11:44:57 +0200
Subject: at91sam9g45 real RTC support
Message-ID: <4C077999.4030601@visionsystems.de>

As far as I understand RTC support for at91sam9g45 is realized via RTT and GPBR, where base time offset is stored. But the board has real RTC with common RTC registers as stated in the documentation. Why is it not supported directly? Is hardware broken?

The other issue is this code part

/* --------------------------------------------------------------------
 *  RTC
 * -------------------------------------------------------------------- */

#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
static struct platform_device at91sam9g45_rtc_device = {
	.name		= "at91_rtc",
	.id		= -1,
	.num_resources	= 0,
};

static void __init at91_add_device_rtc(void)
{
	platform_device_register(&at91sam9g45_rtc_device);
}
#else
static void __init at91_add_device_rtc(void) {}
#endif

I've tweaked the driver/rtc/Kconfig and could then select the AT91RM9200 RTC driver. I could successfully compile the kernel and the RTC has completed the quick test: hwclock --systohc, poweroff, poweron hwclock. The time was correct.

So what is advantage of the RTT based solution? And why AT91RM9200 RTC driver is not made selectable?

Best regards,
Yegor


From kmpark at infradead.org  Thu Jun  3 06:09:54 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Thu, 03 Jun 2010 19:09:54 +0900
Subject: [PATCH] S5PV210: Increase the VIC_NR as 4
Message-ID: <20100603100954.GA17434@july>

The S5PV210 SoC have 4 VICs. It requires for suspend and resume.

Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---

diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 0a34c81..0ac3d81 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -6,6 +6,7 @@ config ARM_VIC
 
 config ARM_VIC_NR
 	int
+	default 4 if ARCH_S5PV210
 	default 2
 	depends on ARM_VIC
 	help


From felipe.contreras at gmail.com  Thu Jun  3 06:23:43 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Thu, 3 Jun 2010 13:23:43 +0300
Subject: [PATCH v3 00/14] omap: mailbox: bunch of cleanups
In-Reply-To: <20100603.094022.200375421.Hiroshi.DOYU@nokia.com>
References: <1274548465-20208-1-git-send-email-felipe.contreras@gmail.com>
	<20100603.094022.200375421.Hiroshi.DOYU@nokia.com>
Message-ID: <AANLkTinI-TCT6CnfauzXPnmZFSSxU3LRD030zRbTuxbF@mail.gmail.com>

On Thu, Jun 3, 2010 at 9:40 AM, Hiroshi DOYU <Hiroshi.DOYU at nokia.com> wrote:
> Have you had a chance to update them?

Sorry, no. I've been busy with user-space stuff. Probably this weekend.

There's no merge-window rush or anything, right?

-- 
Felipe Contreras


From jeremy.kerr at canonical.com  Thu Jun  3 06:24:50 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Thu, 3 Jun 2010 18:24:50 +0800
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100603081354.GA4720@trinity.fluff.org>
References: <1275479804.137633.565764505843.0.gpush@pororo>
	<201006031121.21896.jeremy.kerr@canonical.com>
	<20100603081354.GA4720@trinity.fluff.org>
Message-ID: <201006031824.53832.jeremy.kerr@canonical.com>

Hi Ben,

> clk_enable(struct clk *clk)
> {
> 	if (clk->parent)
> 		clk_enable(clk->parent)
> 	...
> }
> 
> clk_disable(struct clk *clk)
> {
> 	...
> 	if (clk->parent)
> 		clk_disable(clk->parent)
> }
> 
> I think it is a really bad idea for each implementation to have to worry
> about this. It sounds like a recipie for people to get wrong, especially
> if we have a number of these implementations kicking around.

OK, this would mean adding parent to struct clk:

struct clk {
	struct clk_operations	*ops;
	atomic_t				enable_count;
	struct clk			*parent;
};

I was originally intending for struct clk to have the absolute minimum of 
fields, only those necessary for every clock in the system. parent didn't make 
the cut, as some clocks don't have a parent.

However, lets explore this a little - handling parents in the infrastructure 
code this may simplify the hardware-specific code somewhat. We'd add the 
parent-handling stuff to the global clk_enable/clk_disable:

static inline int clk_enable(struct clk *clk)
{
	int ret;

	if (atomic_inc(clk->enable_count) != 1))
		return 0;

	if (clk->parent) {
		ret = clk_enable(clk->parent);
		if (ret)
			goto out_dec;
	}

	ret = clk->ops->enable(clk)
	if (!ret)
		return 0;

out_dec:
	atomic_dec(clk->enable_count);
	return ret;
}

The downside here is that the static inline becomes quite bloated, and we can 
no longer avoid the atomic operation if there is no enable op. I guess we 
could add a:

	if (!clk->ops->enable && !clk->parent)
		return 0;

but now were in serious "don't do that as a inline" territory. So we'd be 
better off making this a proper function.

[as an aside, I need to add the atomic_dec to the error path of my current 
code, will respin a new version. But even then, it's small enough to inline]

I think that handling the enable/disable in the hardware-specific op is an 
acceptable solution. It's only one line of code (or two if you want to check 
for the presence of a parent first), and is, after all, a hardware-specific 
property of the clock.

So, we either:

1) keep it as is, with the hw-specific code handling parent enable/disable; or

2) add the parent-handling code to the clock infrastructure and move the core
   API functions out-of-line.

> As a note, I also left the enable callback in the 'struct clk' instead
> of in the ops, enable/disable is the most used case of these clock
> functions, and as such should probably be the easiest to get to.

I strongly disagree on this one. I want all of the ops in one place, not 
scattered around the API.

> Also, wheras plat-samsung has very few sets of clk_ops sitting about,
> there are more enable/disable calls, and adding more fields to the
> clocks to deal with this would add extra space to the kernel.

Sorry, I don't think I understand your point here - you're saying that moving 
the enable/disable callbacks to struct clk will increase the size of the 
kernel (which is correct, as there are more struct clks than there are struct 
clk_operations), so doesn't this provide an argument against doing this?

> > Also, enable and disable in the external clock API have different return
> > types.
> 
> does that really matter?

Only if someone expects a failed disable to be detected by the driver.

> > Either is fine with me - looks like 'ops' is more commonly used:
> My pref. is for less typing.

OK, will do this in the next revision.

Cheers,


Jeremy


From jy0922.shim at samsung.com  Thu Jun  3 06:27:24 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 03 Jun 2010 19:27:24 +0900
Subject: [PATCH] i2c: Enable i2c-s3c2410 for S5P cpus
In-Reply-To: <20100603084603.GB4720@trinity.fluff.org>
References: <1275544623-5425-1-git-send-email-jy0922.shim@samsung.com>
	<20100603084603.GB4720@trinity.fluff.org>
Message-ID: <4C07838C.2060201@samsung.com>

On 6/3/2010 5:46 PM, Ben Dooks wrote:
> On Thu, Jun 03, 2010 at 02:57:03PM +0900, Joonyoung Shim wrote:
>> This i2c controller driver can be used on the S5P series processors too,
>> so enable the driver in Konfig for those platforms.
>>
>> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>> ---
>>  drivers/i2c/busses/Kconfig |    2 +-
>>  1 files changed, 1 insertions(+), 1 deletions(-)
>>
>> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
>> index 87ab056..4765d62 100644
>> --- a/drivers/i2c/busses/Kconfig
>> +++ b/drivers/i2c/busses/Kconfig
>> @@ -503,7 +503,7 @@ config I2C_PXA_SLAVE
>>  
>>  config I2C_S3C2410
>>  	tristate "S3C2410 I2C Driver"
>> -	depends on ARCH_S3C2410 || ARCH_S3C64XX
>> +	depends on ARCH_S3C2410 || ARCH_S3C64XX || PLAT_S5P
> 
> It may be worth changing this to PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P
> or maybe we should just enable it if PLAT_SAMSUNG
> 

I think PLAT_SAMSUNG is more appropriate thing if it is no problem.

> It would be good to get an policy sorted out on these core drivers which
> exists across many parts of S3C/S5P supported systems.
> 



From linux at arm.linux.org.uk  Thu Jun  3 06:31:44 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 3 Jun 2010 11:31:44 +0100
Subject: [PATCH] S5PV210: Increase the VIC_NR as 4
In-Reply-To: <20100603100954.GA17434@july>
References: <20100603100954.GA17434@july>
Message-ID: <20100603103144.GA7127@n2100.arm.linux.org.uk>

On Thu, Jun 03, 2010 at 07:09:54PM +0900, Kyungmin Park wrote:
> The S5PV210 SoC have 4 VICs. It requires for suspend and resume.

Isn't this negated by Ben's "ARM: VIC: Allocate VIC PM device from slab"
patch?

Incidentally, shouldn't Ben's patch remove this configuration option too?

> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
> 
> diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
> index 0a34c81..0ac3d81 100644
> --- a/arch/arm/common/Kconfig
> +++ b/arch/arm/common/Kconfig
> @@ -6,6 +6,7 @@ config ARM_VIC
>  
>  config ARM_VIC_NR
>  	int
> +	default 4 if ARCH_S5PV210
>  	default 2
>  	depends on ARM_VIC
>  	help
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From l.fu at pengutronix.de  Thu Jun  3 06:34:48 2010
From: l.fu at pengutronix.de (Luotao Fu)
Date: Thu,  3 Jun 2010 12:34:48 +0200
Subject: [PATCH] imxfb: add flag to avoid disabling clk multiple times
Message-ID: <1275561288-20661-1-git-send-email-l.fu@pengutronix.de>

while the imxfb driver blanks the screen. The clock supply to the framebuffer
controller is disabled. The same callback to disable the fb is, however, also
used the remove and shutdown hooks of the imxfb platform driver. This means that
the imxfb driver can run into a WARN in clock_disable while unloading or
rebooting, if the screen is blanked previously, since the same clock will be
than eventually disabled multiple times.  This patch adds a flag to make sure
that the clock will only be disabled, if it was not already disabled before.

The remove or shutdown callbacks in the imxfb platform driver call
imxfb_disable_controller to disable the hardware,

Signed-off-by: Luotao Fu <l.fu at pengutronix.de>
---
 drivers/video/imxfb.c |   13 +++++++++++--
 1 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index 17c6b5f..6ef9817 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -35,6 +35,7 @@
 
 #include <mach/imxfb.h>
 #include <mach/hardware.h>
+#include <mach/clock.h>
 
 /*
  * Complain if VAR is out of range.
@@ -176,6 +177,7 @@ struct imxfb_info {
 
 	struct imx_fb_videomode *mode;
 	int			num_modes;
+	bool			fbclk_disabled;
 
 	void (*lcd_power)(int);
 	void (*backlight_power)(int);
@@ -466,6 +468,7 @@ static void imxfb_enable_controller(struct imxfb_info *fbi)
 	writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR);
 
 	clk_enable(fbi->clk);
+	fbi->fbclk_disabled = 0;
 
 	if (fbi->backlight_power)
 		fbi->backlight_power(1);
@@ -482,7 +485,10 @@ static void imxfb_disable_controller(struct imxfb_info *fbi)
 	if (fbi->lcd_power)
 		fbi->lcd_power(0);
 
-	clk_disable(fbi->clk);
+	if (!fbi->fbclk_disabled) {
+		fbi->fbclk_disabled = 1;
+		clk_disable(fbi->clk);
+	}
 
 	writel(0, fbi->regs + LCDC_RMCR);
 }
@@ -863,7 +869,10 @@ static int __devexit imxfb_remove(struct platform_device *pdev)
 
 	iounmap(fbi->regs);
 	release_mem_region(res->start, resource_size(res));
-	clk_disable(fbi->clk);
+
+	if (!fbi->fbclk_disabled)
+		clk_disable(fbi->clk);
+
 	clk_put(fbi->clk);
 
 	platform_set_drvdata(pdev, NULL);
-- 
1.7.1



From peter.pearse at arm.com  Thu Jun  3 06:42:48 2010
From: peter.pearse at arm.com (Peter Pearse)
Date: Thu, 3 Jun 2010 11:42:48 +0100
Subject: [RFC,
	PATCH 1/3] ARM: PL08X: Add PL08x AMBA DMA Controller 	driver.
In-Reply-To: <AANLkTimoZRr5P_k4QH75upXAWRwkBKJjAfrStm5Znn5S@mail.gmail.com>
References: <1227275251-12005-1-git-send-email-protected@arm.com>	<1227275251-12005-2-git-send-email-protected@arm.com>	<AANLkTilXKWWvn6HLjfbcC0XFEn-Z7jSf4f6CKHBuW8Qb@mail.gmail.com>
	<AANLkTimoZRr5P_k4QH75upXAWRwkBKJjAfrStm5Znn5S@mail.gmail.com>
Message-ID: <000301cb0309$827f2230$3744010a@Emea.Arm.com>

 

> -----Original Message-----
> From: linux-arm-kernel-bounces at lists.infradead.org 
> [mailto:linux-arm-kernel-bounces at lists.infradead.org] On 
> Behalf Of Linus Walleij
> Sent: 02 June 2010 07:19
> To: linux-arm-kernel at lists.infradead.org
> Subject: Fwd: [RFC, PATCH 1/3] ARM: PL08X: Add PL08x AMBA DMA 
> Controller driver.
> 
> Oops this was onto the old list address, Peter is busy so 
> does anybody else know about address boundaries in the RealViews?
> 
> Linus Walleij
> 
> 
> ---------- Forwarded message ----------
> From: Linus Walleij <linus.ml.walleij at gmail.com>
> Date: 2010/5/30
> Subject: Re: [RFC, PATCH 1/3] ARM: PL08X: Add PL08x AMBA DMA 
> Controller driver.
> To: Peter Pearse <peter.pearse at arm.com>
> Kopia: linux-arm-kernel <linux-arm-kernel at lists.arm.linux.org.uk>
> 
> 
> Hi,
> 
> as you know I'm hacking around with this PL08x driver since 
> the Versatile support is in the way for getting my DMA work merged.
> 
> Now this piece I don't quite get:
> 
> 2008/11/21 Peter Pearse <protected at arm.com>:
> 
> 
> > +/*
> > + * Return number of bytes to fill to boundary, or len  */ 
> static int 
> > +pl08x_pre_boundary(int addr, int len) {
> > + ? ? ? int boundary;
> > +
> > + ? ? ? if (len <= 0)
> > + ? ? ? ? ? ? ? printk(KERN_ERR "PL08X::pre_boundary() - zero 
> > + length\n");
> > +
> > + ? ? ? boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1) << 
> > + PL08X_BOUNDARY_SHIFT;
> > +
> > + ? ? ? if (boundary < addr + len)
> > + ? ? ? ? ? ? ? return boundary - addr;
> > + ? ? ? else
> > + ? ? ? ? ? ? ? return len;
> > +}
> 
> This PL08X_BOUNDARY_SHIFT is defined to
> #define PL08X_BOUNDARY_SHIFT ? ? ? ? ? (10) ? ?/* 1KB 0x400 
> */ #define PL08X_BOUNDARY_SIZE ? ? ? ? ? ?(1 << PL08X_BOUNDARY_SHIFT)
> 
> And then later:
> 
> > +/*
> > + * Note that we assume we never have to change the burst sizes  */ 
> > +int fill_LLIS_for_desc(struct pl08x_txd *local_txd, int 
> > +pl08x_chan_num) {
> > (...)
> > + ? ? ? ? ? ? ? /*
> > + ? ? ? ? ? ? ? ?* Make largest possible LLIs until less 
> than one bus 
> > + width left
> > + ? ? ? ? ? ? ? ?*/
> > + ? ? ? ? ? ? ? while (remainder > (mbus->buswidth - 1)) {
> > + ? ? ? ? ? ? ? ? ? ? ? int lli_len, target_len;
> > + ? ? ? ? ? ? ? ? ? ? ? int tsize;
> > + ? ? ? ? ? ? ? ? ? ? ? int odd_bytes;
> > + ? ? ? ? ? ? ? ? ? ? ? /*
> > + ? ? ? ? ? ? ? ? ? ? ? ?* If enough left try to send max possible,
> > + ? ? ? ? ? ? ? ? ? ? ? ?* otherwise try to send the remainder
> > + ? ? ? ? ? ? ? ? ? ? ? ?*/
> > + ? ? ? ? ? ? ? ? ? ? ? target_len = remainder;
> > + ? ? ? ? ? ? ? ? ? ? ? if (remainder > max_bytes_per_lli)
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? target_len = max_bytes_per_lli;
> > + ? ? ? ? ? ? ? ? ? ? ? /*
> > + ? ? ? ? ? ? ? ? ? ? ? ?* ?Set bus lengths for incrementing busses
> > + ? ? ? ? ? ? ? ? ? ? ? ?* ?to number of bytes which fill
> > + ? ? ? ? ? ? ? ? ? ? ? ?* ?to next memory boundary
> > + ? ? ? ? ? ? ? ? ? ? ? ?*/
> > + ? ? ? ? ? ? ? ? ? ? ? if (cctl_parm.bits.si)
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? local_txd->srcbus.fill_bytes
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 
> > + pl08x_pre_boundary(local_txd->srcbus.addr
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? , 
> > + remainder);
> > + ? ? ? ? ? ? ? ? ? ? ? else
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? local_txd->srcbus.fill_bytes
> > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = max_bytes_per_lli;
> 
> Here the transfer lengths for lli:s crawls up tp a boundary.
> Now, the DMAC PL08x cannot move past a 0x400 boundary on the 
> RealViews, so much is clear. But: is this a thing that will affect:
> 
> - All RealView / Versatile equipment
> - All implementations of PL08x on all silicon

Both pl08x manuals have
3.5 Address generation
Address generation can be either incrementing or non-incrementing. Address
wrapping
is not supported. Bursts do not cross the 1KB address boundary.


Although our partners may choose to adapt their implementations to cross
boundaries

the driver should play safe......



> - All ARM architectures and nothing to do with the PL08x at 
> all, rather
> ?with some AMBA stuff or so?
> 
> Yours,
> Linus Walleij
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 




From Hiroshi.DOYU at nokia.com  Thu Jun  3 06:59:46 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Thu, 03 Jun 2010 13:59:46 +0300 (EEST)
Subject: [PATCH v3 00/14] omap: mailbox: bunch of cleanups
In-Reply-To: <AANLkTinI-TCT6CnfauzXPnmZFSSxU3LRD030zRbTuxbF@mail.gmail.com>
References: <1274548465-20208-1-git-send-email-felipe.contreras@gmail.com>
	<20100603.094022.200375421.Hiroshi.DOYU@nokia.com>
	<AANLkTinI-TCT6CnfauzXPnmZFSSxU3LRD030zRbTuxbF@mail.gmail.com>
Message-ID: <20100603.135946.233694251.Hiroshi.DOYU@nokia.com>

From: ext Felipe Contreras <felipe.contreras at gmail.com>
Subject: Re: [PATCH v3 00/14] omap: mailbox: bunch of cleanups
Date: Thu, 3 Jun 2010 12:23:43 +0200

> On Thu, Jun 3, 2010 at 9:40 AM, Hiroshi DOYU <Hiroshi.DOYU at nokia.com> wrote:
>> Have you had a chance to update them?
> 
> Sorry, no. I've been busy with user-space stuff. Probably this weekend.
> 
> There's no merge-window rush or anything, right?

No rush. Sorry for just ping.


From linux at arm.linux.org.uk  Thu Jun  3 07:05:33 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 3 Jun 2010 12:05:33 +0100
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <201006031824.53832.jeremy.kerr@canonical.com>
References: <1275479804.137633.565764505843.0.gpush@pororo>
	<201006031121.21896.jeremy.kerr@canonical.com>
	<20100603081354.GA4720@trinity.fluff.org>
	<201006031824.53832.jeremy.kerr@canonical.com>
Message-ID: <20100603110533.GB7127@n2100.arm.linux.org.uk>

On Thu, Jun 03, 2010 at 06:24:50PM +0800, Jeremy Kerr wrote:
> OK, this would mean adding parent to struct clk:
> 
> struct clk {
> 	struct clk_operations	*ops;
> 	atomic_t				enable_count;

I don't think it makes sense for this to be an atomic type.

> static inline int clk_enable(struct clk *clk)
> {
> 	int ret;
> 
> 	if (atomic_inc(clk->enable_count) != 1))
> 		return 0;

Okay, so what if we sleep at this point, and someone else comes along
and calls clk_enable(), which'll merely increment the count and return.

Unfortunately, the clock is still disabled at that point - which is a
violation of what's supposed to happen.

Or to put it another way, the above method results in clk_enable()
sometimes returning with the clock enabled and sometimes with the
clock still disabled.

That's not nice behaviour for drivers which may need the clock enabled
to read/write the device registers.


From saeed.bishara at gmail.com  Thu Jun  3 07:43:56 2010
From: saeed.bishara at gmail.com (saeed bishara)
Date: Thu, 3 Jun 2010 14:43:56 +0300
Subject: [PATCH 3/3] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <alpine.LFD.2.00.1006011447410.24526@xanadu.home>
References: <1275404968-12258-1-git-send-email-saeed@marvell.com>
	<1275404968-12258-2-git-send-email-saeed@marvell.com>
	<1275404968-12258-3-git-send-email-saeed@marvell.com>
	<alpine.LFD.2.00.1006011447410.24526@xanadu.home>
Message-ID: <AANLkTinQ_DdwRrjwtzrTXqtoeQxh87qAjSXDd6O4cPba@mail.gmail.com>

On Tue, Jun 1, 2010 at 10:55 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Tue, 1 Jun 2010, Saeed Bishara wrote:
>
>> This patch extens the kirkwood's PCIe support up to 2 controllers as in the 6282 devices.
>>
>> Signed-off-by: Saeed Bishara <saeed at marvell.com>
>
> Comments below.
>
> [...]
>> diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
>> index 5e6f711..6e67f3c 100644
>> --- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
>> +++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
>> @@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
>> ?static int __init mv88f6281gtw_ge_pci_init(void)
>> ?{
>> ? ? ? if (machine_is_mv88f6281gtw_ge())
>> - ? ? ? ? ? ? kirkwood_pcie_init();
>> + ? ? ? ? ? ? kirkwood_pcie_init(0, 1);
>
> This is going to initialize the non existing PCIe1 and disable PCIe0.
> You made the same mistake multiple times.
right :(
>
> [...]
>> diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
>> index dee1eff..5c33324 100644
>> --- a/arch/arm/mach-kirkwood/pcie.c
>> +++ b/arch/arm/mach-kirkwood/pcie.c
>> @@ -21,26 +21,40 @@
>>
>> ?#define PCIE_BASE ? ?((void __iomem *)PCIE_VIRT_BASE)
>
> Is this PCIE_BASE still used?
yes, but as it only used by kirkwood_pcei_id(), it will be removed
>
>> +struct pcie_port {
>> + ? ? u8 ? ? ? ? ? ? ? ? ? ? ?index;
>> + ? ? u8 ? ? ? ? ? ? ? ? ? ? ?root_bus_nr;
>> + ? ? void __iomem ? ? ? ? ? ?*base;
>> + ? ? spinlock_t ? ? ? ? ? ? ?conf_lock;
>> + ? ? char ? ? ? ? ? ? ? ? ? ?io_space_name[16];
>> + ? ? char ? ? ? ? ? ? ? ? ? ?mem_space_name[16];
>> + ? ? struct resource ? ? ? ? res[2];
>> +};
>> +
>> +static struct pcie_port pcie_port[2];
>> +static int num_pcie_ports;
>> +static struct pcie_port *bus_to_port(int bus);
>
> You should move the actual function here allowing you to get rid of that
> forward declaration.
>
>
>> ?void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
>> ?{
>> ? ? ? *dev = orion_pcie_dev_id(PCIE_BASE);
>> ? ? ? *rev = orion_pcie_rev(PCIE_BASE);
>> ?}
>>
>> -static int pcie_valid_config(int bus, int dev)
>> +static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
>> ?{
>> ? ? ? /*
>> ? ? ? ?* Don't go out when trying to access --
>> ? ? ? ?* 1. nonexisting device on local bus
>> ? ? ? ?* 2. where there's no device connected (no link)
>> ? ? ? ?*/
>> - ? ? if (bus == 0 && dev == 0)
>> + ? ? if (bus == pp->root_bus_nr && dev == 0)
>> ? ? ? ? ? ? ? return 1;
>>
>> - ? ? if (!orion_pcie_link_up(PCIE_BASE))
>> + ? ? if (!orion_pcie_link_up(pp->base))
>> ? ? ? ? ? ? ? return 0;
>>
>> - ? ? if (bus == 0 && dev != 1)
>> + ? ? if (bus == pp->root_bus_nr && dev != 1)
>> ? ? ? ? ? ? ? return 0;
>>
>> ? ? ? return 1;
>> @@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev)
>> ? * and then reading the PCIE_CONF_DATA register. Need to make sure these
>> ? * transactions are atomic.
>> ? */
>> -static DEFINE_SPINLOCK(kirkwood_pcie_lock);
>>
>> ?static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
>> ? ? ? ? ? ? ? ? ? ? ? int size, u32 *val)
>> ?{
>> + ? ? struct pcie_port *pp = bus_to_port(bus->number);
>> ? ? ? unsigned long flags;
>> ? ? ? int ret;
>>
>> - ? ? if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
>> + ? ? if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
>> ? ? ? ? ? ? ? *val = 0xffffffff;
>> ? ? ? ? ? ? ? return PCIBIOS_DEVICE_NOT_FOUND;
>> ? ? ? }
>>
>> - ? ? spin_lock_irqsave(&kirkwood_pcie_lock, flags);
>> - ? ? ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
>> - ? ? spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
>> + ? ? spin_lock_irqsave(&pp->conf_lock, flags);
>> + ? ? ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
>> + ? ? spin_unlock_irqrestore(&pp->conf_lock, flags);
>>
>> ? ? ? return ret;
>> ?}
>> @@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
>> ?static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
>> ? ? ? ? ? ? ? ? ? ? ? int where, int size, u32 val)
>> ?{
>> + ? ? struct pcie_port *pp = bus_to_port(bus->number);
>> ? ? ? unsigned long flags;
>> ? ? ? int ret;
>>
>> - ? ? if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
>> + ? ? if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
>> ? ? ? ? ? ? ? return PCIBIOS_DEVICE_NOT_FOUND;
>>
>> - ? ? spin_lock_irqsave(&kirkwood_pcie_lock, flags);
>> - ? ? ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
>> - ? ? spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
>> + ? ? spin_lock_irqsave(&pp->conf_lock, flags);
>> + ? ? ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
>> + ? ? spin_unlock_irqrestore(&pp->conf_lock, flags);
>>
>> ? ? ? return ret;
>> ?}
>> @@ -96,51 +111,84 @@ static struct pci_ops pcie_ops = {
>>
>> ?static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
>> ?{
>> - ? ? struct resource *res;
>> ? ? ? extern unsigned int kirkwood_clk_ctrl;
>> + ? ? struct pcie_port *pp;
>> +
>> + ? ? if (nr >= num_pcie_ports)
>> + ? ? ? ? ? ? return 0;
>> +
>> + ? ? pp = &pcie_port[nr];
>> + ? ? pp->root_bus_nr = sys->busnr;
>>
>> ? ? ? /*
>> ? ? ? ?* Generic PCIe unit setup.
>> ? ? ? ?*/
>> - ? ? orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
>> + ? ? orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
>> +
>> + ? ? orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
>>
>> - ? ? /*
>> - ? ? ?* Request resources.
>> - ? ? ?*/
>> - ? ? res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
>> - ? ? if (!res)
>> - ? ? ? ? ? ? panic("pcie_setup unable to alloc resources");
>>
>> ? ? ? /*
>> ? ? ? ?* IORESOURCE_IO
>> ? ? ? ?*/
>> - ? ? res[0].name = "PCIe I/O Space";
>> - ? ? res[0].flags = IORESOURCE_IO;
>> - ? ? res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
>> - ? ? res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
>> - ? ? if (request_resource(&ioport_resource, &res[0]))
>> + ? ? snprintf(pp->io_space_name, sizeof(pp->io_space_name),
>> + ? ? ? ? ? ? ?"PCIe %d I/O", pp->index);
>> + ? ? pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
>> + ? ? pp->res[0].name = pp->io_space_name;
>> + ? ? if (pp->index == 0) {
>> + ? ? ? ? ? ? pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
>> + ? ? ? ? ? ? pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
>> + ? ? } else {
>> + ? ? ? ? ? ? pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
>> + ? ? ? ? ? ? pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
>> + ? ? }
>> + ? ? pp->res[0].flags = IORESOURCE_IO;
>> + ? ? if (request_resource(&ioport_resource, &pp->res[0]))
>> ? ? ? ? ? ? ? panic("Request PCIe IO resource failed\n");
>> - ? ? sys->resource[0] = &res[0];
>> + ? ? sys->resource[0] = &pp->res[0];
>>
>> ? ? ? /*
>> ? ? ? ?* IORESOURCE_MEM
>> ? ? ? ?*/
>> - ? ? res[1].name = "PCIe Memory Space";
>> - ? ? res[1].flags = IORESOURCE_MEM;
>> - ? ? res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
>> - ? ? res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
>> - ? ? if (request_resource(&iomem_resource, &res[1]))
>> + ? ? snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
>> + ? ? ? ? ? ? ?"PCIe %d MEM", pp->index);
>> + ? ? pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
>> + ? ? pp->res[1].name = pp->mem_space_name;
>> + ? ? if (pp->index == 0) {
>> + ? ? ? ? ? ? pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
>> + ? ? ? ? ? ? pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
>> + ? ? } else {
>> + ? ? ? ? ? ? pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
>> + ? ? ? ? ? ? pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
>> + ? ? }
>> + ? ? pp->res[1].flags = IORESOURCE_MEM;
>> + ? ? if (request_resource(&iomem_resource, &pp->res[1]))
>> ? ? ? ? ? ? ? panic("Request PCIe Memory resource failed\n");
>> - ? ? sys->resource[1] = &res[1];
>> + ? ? sys->resource[1] = &pp->res[1];
>>
>> ? ? ? sys->resource[2] = NULL;
>> ? ? ? sys->io_offset = 0;
>>
>> - ? ? kirkwood_clk_ctrl |= CGC_PEX0;
>> -
>> + ? ? if (nr == 0)
>> + ? ? ? ? ? ? kirkwood_clk_ctrl |= CGC_PEX0;
>> + ? ? else
>> + ? ? ? ? ? ? kirkwood_clk_ctrl |= CGC_PEX1;
>> ? ? ? return 1;
>> ?}
>>
>> +static struct pcie_port *bus_to_port(int bus)
>> +{
>> + ? ? int i;
>> +
>> + ? ? for (i = num_pcie_ports - 1; i >= 0; i--) {
>> + ? ? ? ? ? ? int rbus = pcie_port[i].root_bus_nr;
>> + ? ? ? ? ? ? if (rbus != -1 && rbus <= bus)
>> + ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? }
>> +
>> + ? ? return i >= 0 ? pcie_port + i : NULL;
>> +}
>
> I think this looks like a bit too much code for what this does. ?To
> simplify things, you could:
>
> 1) Duplicate kirkwood_pcie_setup() into kirkwood_pcie0_setup() and
> ? kirkwood_pcie1_setup() instead. ?This will remove a couple
> ? "if (pp->index == 0)" and the snprintf() which could remain
> ? purely static initializations.
>
> 2) Remove bus_to_port() entirely, and store the address of the appropriate
> ? struct pcie_port instance into the sysdata pointer of the pci_bus
> ? structure. ?This struct pcie_port could even be kmalloc'd as needed.
>
>> ?static void __devinit rc_pci_fixup(struct pci_dev *dev)
>> ?{
>> ? ? ? /*
>> @@ -163,7 +211,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
>> ?{
>> ? ? ? struct pci_bus *bus;
>>
>> - ? ? if (nr == 0) {
>> + ? ? if (nr < num_pcie_ports) {
>> ? ? ? ? ? ? ? bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
>> ? ? ? } else {
>> ? ? ? ? ? ? ? bus = NULL;
>> @@ -175,18 +223,45 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
>>
>> ?static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
>> ?{
>> - ? ? return IRQ_KIRKWOOD_PCIE;
>> + ? ? struct pcie_port *pp = bus_to_port(dev->bus->number);
>> +
>> + ? ? return pp->index ? IRQ_KIRKWOOD_PCIE1 : IRQ_KIRKWOOD_PCIE;
>
> Maybe having pp->irq and returning that directly would be better.
>
>> ?static struct hw_pci kirkwood_pci __initdata = {
>> - ? ? .nr_controllers = 1,
>> + ? ? .nr_controllers = 2,
>
> I think this should be initialized at run time to 2 only when running on
> a 6282.
I will set it to number of requested ports that have a link
>
>> ? ? ? .swizzle ? ? ? ?= pci_std_swizzle,
>> ? ? ? .setup ? ? ? ? ?= kirkwood_pcie_setup,
>> ? ? ? .scan ? ? ? ? ? = kirkwood_pcie_scan_bus,
>> ? ? ? .map_irq ? ? ? ?= kirkwood_pcie_map_irq,
>> ?};
>>
>> -void __init kirkwood_pcie_init(void)
>> +static void __init add_pcie_port(int index, unsigned long base)
>> ?{
>> + ? ? printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
>> +
>> + ? ? if (orion_pcie_link_up((void __iomem *)base)) {
>> + ? ? ? ? ? ? struct pcie_port *pp = &pcie_port[num_pcie_ports++];
>> +
>> + ? ? ? ? ? ? printk(KERN_INFO "link up\n");
>> +
>> + ? ? ? ? ? ? pp->index = index;
>> + ? ? ? ? ? ? pp->root_bus_nr = -1;
>> + ? ? ? ? ? ? pp->base = (void __iomem *)base;
>> + ? ? ? ? ? ? spin_lock_init(&pp->conf_lock);
>> + ? ? ? ? ? ? memset(pp->res, 0, sizeof(pp->res));
>> + ? ? } else {
>> + ? ? ? ? ? ? printk(KERN_INFO "link down, ignoring\n");
>> + ? ? }
>> +}
>> +
>> +void __init kirkwood_pcie_init(int init_port0, int init_port1)
>
> And instead of having (int init_port0, int init_port1), this should be
> (int port) which is much less error prone as demonstrated by your own
> kirkwood_pcie_init(0, 1) usage. ?Those machines with both PCIe ports
> would simply have to call this twice.
nico, this is different from other controller,  we can't have multiple
registrations as the pci_commont_init() can't be called multiple
times.
>
>
> Nicolas
>


From linux at arm.linux.org.uk  Thu Jun  3 07:47:26 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 3 Jun 2010 12:47:26 +0100
Subject: [PATCH v3 00/14] omap: mailbox: bunch of cleanups
In-Reply-To: <20100603.094022.200375421.Hiroshi.DOYU@nokia.com>
References: <1274548465-20208-1-git-send-email-felipe.contreras@gmail.com>
	<20100603.094022.200375421.Hiroshi.DOYU@nokia.com>
Message-ID: <20100603114726.GC7127@n2100.arm.linux.org.uk>

On Thu, Jun 03, 2010 at 09:40:22AM +0300, Hiroshi DOYU wrote:
> > Felipe Contreras (14):
> >   omap: mailbox: trivial whitespace cleanups
> >   omap: mailbox: trivial cleanups

I think folk need to read this:

	http://lkml.org/lkml/2010/6/2/472

and consider what it means for the future, and what can be done to reduce
the amount of "churn".


From felipe.balbi at nokia.com  Thu Jun  3 07:56:18 2010
From: felipe.balbi at nokia.com (Felipe Balbi)
Date: Thu, 3 Jun 2010 14:56:18 +0300
Subject: [PATCH v3 00/14] omap: mailbox: bunch of cleanups
In-Reply-To: <20100603114726.GC7127@n2100.arm.linux.org.uk>
References: <1274548465-20208-1-git-send-email-felipe.contreras@gmail.com>
	<20100603.094022.200375421.Hiroshi.DOYU@nokia.com>
	<20100603114726.GC7127@n2100.arm.linux.org.uk>
Message-ID: <20100603115618.GT11078@nokia.com>

Hi,

On Thu, Jun 03, 2010 at 01:47:26PM +0200, ext Russell King - ARM Linux wrote:
>I think folk need to read this:
>
>	http://lkml.org/lkml/2010/6/2/472
>
>and consider what it means for the future, and what can be done to reduce
>the amount of "churn".

I believe Linus is considering more the amount of files not the amount 
of patches. Personally, I consider trivial cleanup patches the best way 
to start off with a new code (not saying that Felipe C. is new to mbox 
driver) and those patches are as needed as a brand new feature.

One thing to decrease the amount of lines of code in arch/arm is to move 
the drivers to they're proper locations on the tree. Only on omap we 
have 6 platform_drivers that could (should) be moved to proper 
locations after a 'trivial cleanups'.

gpio.c mcbsp.c timer drivers (for clocksource) etc, which alone would 
mean a decrease of 6237 lines out of arch/arm/*omap* only. And I'm not 
even counting the drivers which aren't platform_drivers.

The thing is that ARM is really different than x86 and there's no 
standardization among different SoCs, so other than moving drivers out 
of arch/arm, there isn't much we can do. Or do you have any ideas ?

-- 
balbi

DefectiveByDesign.org


From saeed at marvell.com  Thu Jun  3 07:58:46 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Thu,  3 Jun 2010 14:58:46 +0300
Subject: [PATCH 3/4] [ARM] PCI: add platform private data to pci_sys_data
Message-ID: <1275566327-1764-1-git-send-email-saeed@marvell.com>

Add private_data pointer to the pci_sys_data, this pointer can be
used for holding platform specific data for each pci controller.

Signed-off-by: Saeed Bishara <saeed at marvell.com>
---
 arch/arm/include/asm/mach/pci.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 52f0da1..16330bd 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -46,6 +46,7 @@ struct pci_sys_data {
 					/* IRQ mapping				*/
 	int		(*map_irq)(struct pci_dev *, u8, u8);
 	struct hw_pci	*hw;
+	void		*private_data;	/* platform controller private data	*/
 };
 
 /*
-- 
1.6.0.4



From saeed at marvell.com  Thu Jun  3 07:58:47 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Thu,  3 Jun 2010 14:58:47 +0300
Subject: [PATCH 4/4 v2] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <1275566327-1764-1-git-send-email-saeed@marvell.com>
References: <1275566327-1764-1-git-send-email-saeed@marvell.com>
Message-ID: <1275566327-1764-2-git-send-email-saeed@marvell.com>

This patch extens the kirkwood's PCIe support up to 2 controllers as in the 6282 devices.

Signed-off-by: Saeed Bishara <saeed at marvell.com>
---
 arch/arm/mach-kirkwood/addr-map.c                 |   10 +-
 arch/arm/mach-kirkwood/common.h                   |    2 +-
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c       |   10 +-
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h |    1 +
 arch/arm/mach-kirkwood/include/mach/irqs.h        |    1 +
 arch/arm/mach-kirkwood/include/mach/kirkwood.h    |   10 +
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c    |    2 +-
 arch/arm/mach-kirkwood/openrd-setup.c             |    2 +-
 arch/arm/mach-kirkwood/pcie.c                     |  187 +++++++++++++++-----
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c      |    2 +-
 arch/arm/mach-kirkwood/rd88f6281-setup.c          |    2 +-
 arch/arm/mach-kirkwood/ts219-setup.c              |    6 +-
 arch/arm/mach-kirkwood/ts41x-setup.c              |    2 +-
 13 files changed, 177 insertions(+), 60 deletions(-)

diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168..8d03bce 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
 #define ATTR_DEV_CS0		0x3e
 #define ATTR_PCIE_IO		0xe0
 #define ATTR_PCIE_MEM		0xe8
+#define ATTR_PCIE1_IO		0xd0
+#define ATTR_PCIE1_MEM		0xd8
 #define ATTR_SRAM		0x01
 
 /*
@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
 		      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
 	setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
 		      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
+	setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
+		      TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
+	setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
+		      TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
 
 	/*
 	 * Setup window for NAND controller.
 	 */
-	setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+	setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
 		      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
 
 	/*
 	 * Setup window for SRAM.
 	 */
-	setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+	setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
 		      TARGET_SRAM, ATTR_SRAM, -1);
 
 	/*
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05e8a8a..876f71a 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -34,7 +34,7 @@ void kirkwood_ehci_init(void);
 void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
-void kirkwood_pcie_init(void);
+void kirkwood_pcie_init(int init_port0, int init_port1);
 void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
 void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
 void kirkwood_spi_init(void);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4b..b11b5fe 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -74,9 +74,15 @@ static void __init db88f6281_init(void)
 
 static int __init db88f6281_pci_init(void)
 {
-	if (machine_is_db88f6281_bp())
-		kirkwood_pcie_init();
+	if (machine_is_db88f6281_bp()) {
+		u32 dev, rev;
+		int init_port1 = 0;
 
+		kirkwood_pcie_id(&dev, &rev);
+		if (dev == MV88F6282_DEV_ID)
+			init_port1 = 1;
+		kirkwood_pcie_init(1, init_port1);
+	}
 	return 0;
 }
 subsys_initcall(db88f6281_pci_init);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f501..2026b30 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,6 +59,7 @@
 #define CGC_SATA1		(1 << 15)
 #define CGC_XOR1		(1 << 16)
 #define CGC_CRYPTO		(1 << 17)
+#define CGC_PEX1		(1 << 18)
 #define CGC_GE1			(1 << 19)
 #define CGC_TDM			(1 << 20)
 #define CGC_RESERVED		((1 << 18) | (0x6 << 21))
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index f00a0a4..9da2eb5 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -23,6 +23,7 @@
 #define IRQ_KIRKWOOD_XOR_10	7
 #define IRQ_KIRKWOOD_XOR_11	8
 #define IRQ_KIRKWOOD_PCIE	9
+#define IRQ_KIRKWOOD_PCIE1	10
 #define IRQ_KIRKWOOD_GE00_SUM	11
 #define IRQ_KIRKWOOD_GE01_SUM	15
 #define IRQ_KIRKWOOD_USB	19
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index dd7eddb..058f06b 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -38,6 +38,11 @@
 #define KIRKWOOD_PCIE_IO_BUS_BASE	0x00000000
 #define KIRKWOOD_PCIE_IO_SIZE		SZ_1M
 
+#define KIRKWOOD_PCIE1_IO_PHYS_BASE	0xf5000000
+#define KIRKWOOD_PCIE1_IO_VIRT_BASE	0xfed00000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE	0x00000000
+#define KIRKWOOD_PCIE1_IO_SIZE		SZ_1M
+
 #define KIRKWOOD_REGS_PHYS_BASE		0xf1000000
 #define KIRKWOOD_REGS_VIRT_BASE		0xfee00000
 #define KIRKWOOD_REGS_SIZE		SZ_1M
@@ -46,6 +51,10 @@
 #define KIRKWOOD_PCIE_MEM_BUS_BASE	0xe0000000
 #define KIRKWOOD_PCIE_MEM_SIZE		SZ_128M
 
+#define KIRKWOOD_PCIE1_MEM_PHYS_BASE	0xd8000000
+#define KIRKWOOD_PCIE1_MEM_BUS_BASE	0xd8000000
+#define KIRKWOOD_PCIE1_MEM_SIZE		SZ_128M
+
 /*
  * Register Map
  */
@@ -72,6 +81,7 @@
 #define PCIE_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x40000)
 #define PCIE_LINK_CTRL		(PCIE_VIRT_BASE | 0x70)
 #define PCIE_STATUS		(PCIE_VIRT_BASE | 0x1a04)
+#define PCIE1_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x44000)
 
 #define USB_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x50000)
 
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 5e6f711..079eed9 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
 static int __init mv88f6281gtw_ge_pci_init(void)
 {
 	if (machine_is_mv88f6281gtw_ge())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(1, 0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec..4174f48 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -85,7 +85,7 @@ static void __init openrd_init(void)
 static int __init openrd_pci_init(void)
 {
 	if (machine_is_openrd_base() || machine_is_openrd_client())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(0, 1);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index dee1eff..703e6c8 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,29 +18,43 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
+void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+{
+	*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
+	*rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+}
 
-#define PCIE_BASE	((void __iomem *)PCIE_VIRT_BASE)
+struct pcie_port {
+	u8			root_bus_nr;
+	void __iomem		*base;
+	spinlock_t		conf_lock;
+	int			irq;
+	struct resource		res[2];
+};
 
-void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+static int pcie_port_map[2];
+static int num_pcie_ports;
+
+static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
 {
-	*dev = orion_pcie_dev_id(PCIE_BASE);
-	*rev = orion_pcie_rev(PCIE_BASE);
+	struct pci_sys_data *sys = bus->sysdata;
+	return sys->private_data;
 }
 
-static int pcie_valid_config(int bus, int dev)
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 {
 	/*
 	 * Don't go out when trying to access --
 	 * 1. nonexisting device on local bus
 	 * 2. where there's no device connected (no link)
 	 */
-	if (bus == 0 && dev == 0)
+	if (bus == pp->root_bus_nr && dev == 0)
 		return 1;
 
-	if (!orion_pcie_link_up(PCIE_BASE))
+	if (!orion_pcie_link_up(pp->base))
 		return 0;
 
-	if (bus == 0 && dev != 1)
+	if (bus == pp->root_bus_nr && dev != 1)
 		return 0;
 
 	return 1;
@@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev)
  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  * transactions are atomic.
  */
-static DEFINE_SPINLOCK(kirkwood_pcie_lock);
 
 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 			int size, u32 *val)
 {
+	struct pcie_port *pp = bus_to_port(bus);
 	unsigned long flags;
 	int ret;
 
-	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
 		*val = 0xffffffff;
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
 
-	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
-	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+	spin_lock_irqsave(&pp->conf_lock, flags);
+	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+	spin_unlock_irqrestore(&pp->conf_lock, flags);
 
 	return ret;
 }
@@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 			int where, int size, u32 val)
 {
+	struct pcie_port *pp = bus_to_port(bus);
 	unsigned long flags;
 	int ret;
 
-	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
-	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
-	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+	spin_lock_irqsave(&pp->conf_lock, flags);
+	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+	spin_unlock_irqrestore(&pp->conf_lock, flags);
 
 	return ret;
 }
@@ -93,50 +108,109 @@ static struct pci_ops pcie_ops = {
 	.write = pcie_wr_conf,
 };
 
-
-static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+static int __init pcie0_ioresouces_setup(struct pci_sys_data *sys)
 {
-	struct resource *res;
-	extern unsigned int kirkwood_clk_ctrl;
-
+	struct pcie_port *pp = (struct pcie_port *)sys->private_data;
 	/*
-	 * Generic PCIe unit setup.
+	 * IORESOURCE_IO
 	 */
-	orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
+	pp->res[0].name = "PCIe 0 I/O Space";
+	pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+	pp->res[0].flags = IORESOURCE_IO;
+	if (request_resource(&ioport_resource, &pp->res[0]))
+		panic("Request PCIe 0 IO resource failed\n");
+	sys->resource[0] = &pp->res[0];
 
 	/*
-	 * Request resources.
+	 * IORESOURCE_MEM
 	 */
-	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-	if (!res)
-		panic("pcie_setup unable to alloc resources");
+	pp->res[1].name = "PCIe 0 MEM";
+	pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+	pp->res[1].flags = IORESOURCE_MEM;
+	if (request_resource(&iomem_resource, &pp->res[1]))
+		panic("Request PCIe 0 Memory resource failed\n");
+	sys->resource[1] = &pp->res[1];
+
+	sys->resource[2] = NULL;
+	sys->io_offset = 0;
 
+	return 1;
+}
+
+static int __init pcie1_ioresouces_setup(struct pci_sys_data *sys)
+{
+	struct pcie_port *pp = (struct pcie_port *)sys->private_data;
 	/*
 	 * IORESOURCE_IO
 	 */
-	res[0].name = "PCIe I/O Space";
-	res[0].flags = IORESOURCE_IO;
-	res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-	res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
-	if (request_resource(&ioport_resource, &res[0]))
-		panic("Request PCIe IO resource failed\n");
-	sys->resource[0] = &res[0];
+	pp->res[0].name = "PCIe 1 I/O Space";
+	pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
+	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
+	pp->res[0].flags = IORESOURCE_IO;
+	if (request_resource(&ioport_resource, &pp->res[0]))
+		panic("Request PCIe 1 IO resource failed\n");
+	sys->resource[0] = &pp->res[0];
 
 	/*
 	 * IORESOURCE_MEM
 	 */
-	res[1].name = "PCIe Memory Space";
-	res[1].flags = IORESOURCE_MEM;
-	res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
-	res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-	if (request_resource(&iomem_resource, &res[1]))
-		panic("Request PCIe Memory resource failed\n");
-	sys->resource[1] = &res[1];
+	pp->res[1].name = "PCIe 1 MEM";
+	pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+	pp->res[1].flags = IORESOURCE_MEM;
+	if (request_resource(&iomem_resource, &pp->res[1]))
+		panic("Request PCIe 1 Memory resource failed\n");
+	sys->resource[1] = &pp->res[1];
 
 	sys->resource[2] = NULL;
 	sys->io_offset = 0;
 
-	kirkwood_clk_ctrl |= CGC_PEX0;
+	return 1;
+}
+
+static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+	extern unsigned int kirkwood_clk_ctrl;
+	struct pcie_port *pp;
+	int index;
+	if (nr >= num_pcie_ports)
+		return 0;
+
+	index = pcie_port_map[nr];
+	printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
+
+	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
+	if (!pp)
+		panic("PCIe: failed to allocate pcie_port data");
+	sys->private_data = pp;
+	pp->root_bus_nr = sys->busnr;
+	spin_lock_init(&pp->conf_lock);
+
+	switch (index) {
+	case 0:
+		pp->base = (void __iomem *)PCIE_VIRT_BASE;
+		pp->irq	= IRQ_KIRKWOOD_PCIE;
+		kirkwood_clk_ctrl |= CGC_PEX0;
+		pcie0_ioresouces_setup(sys);
+		break;
+	case 1:
+		pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+		pp->irq	= IRQ_KIRKWOOD_PCIE1;
+		kirkwood_clk_ctrl |= CGC_PEX1;
+		pcie1_ioresouces_setup(sys);
+		break;
+	default:
+		panic("PCIe setup: invalid controller");
+	}
+
+	/*
+	 * Generic PCIe unit setup.
+	 */
+	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+
+	orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
 
 	return 1;
 }
@@ -163,7 +237,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 {
 	struct pci_bus *bus;
 
-	if (nr == 0) {
+	if (nr < num_pcie_ports) {
 		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
 	} else {
 		bus = NULL;
@@ -175,18 +249,37 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 
 static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-	return IRQ_KIRKWOOD_PCIE;
+	struct pcie_port *pp = bus_to_port(dev->bus);
+
+	return pp->irq;
 }
 
 static struct hw_pci kirkwood_pci __initdata = {
-	.nr_controllers	= 1,
 	.swizzle	= pci_std_swizzle,
 	.setup		= kirkwood_pcie_setup,
 	.scan		= kirkwood_pcie_scan_bus,
 	.map_irq	= kirkwood_pcie_map_irq,
 };
 
-void __init kirkwood_pcie_init(void)
+static void __init add_pcie_port(int index, unsigned long base)
+{
+	printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
+
+	if (orion_pcie_link_up((void __iomem *)base)) {
+		printk(KERN_INFO "link up\n");
+		pcie_port_map[num_pcie_ports++] = index;
+	} else
+		printk(KERN_INFO "link down, ignoring\n");
+}
+
+void __init kirkwood_pcie_init(int init_port0, int init_port1)
 {
+	if (init_port0)
+		add_pcie_port(0, PCIE_VIRT_BASE);
+
+	if (init_port1)
+		add_pcie_port(1, PCIE1_VIRT_BASE);
+
+	kirkwood_pci.nr_controllers = num_pcie_ports;
 	pci_common_init(&kirkwood_pci);
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 3bf6304..96b7256 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
 static int __init rd88f6192_pci_init(void)
 {
 	if (machine_is_rd88f6192_nas())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(1, 0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31708dd..87e8fa2 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
 static int __init rd88f6281_pci_init(void)
 {
 	if (machine_is_rd88f6281())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(1, 0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0f..5fe8811 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -110,10 +110,10 @@ static void __init qnap_ts219_init(void)
 
 static int __init ts219_pci_init(void)
 {
-   if (machine_is_ts219())
-           kirkwood_pcie_init();
+	if (machine_is_ts219())
+		kirkwood_pcie_init(1, 0);
 
-   return 0;
+	return 0;
 }
 subsys_initcall(ts219_pci_init);
 
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index de49c2d..8505d30 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -136,7 +136,7 @@ static void __init qnap_ts41x_init(void)
 static int __init ts41x_pci_init(void)
 {
 	if (machine_is_ts41x())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(1, 0);
 
    return 0;
 }
-- 
1.6.0.4



From jason77.wang at gmail.com  Thu Jun  3 08:05:43 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Thu,  3 Jun 2010 20:05:43 +0800
Subject: [V2 0/3]Add i.MX51 3-stack board support
Message-ID: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>

Comparing with V1, several changes are made in V2:

1) drop iomux-mx51-3ds.h and move its contents to iomux-mx51.h
2) move keypad device definition to devices.c
3) fix all remaining comments from Sascha, Amit and Fabio.


[V2 1/3] mxc: Add support for the imx51 3-stack board
[V2 2/3] mxc/iomux: add GPIO bank offset for iomux v3 platforms
[V2 3/3] mx51/keypad: add keypad support for i.MX51 platforms




From baruch at tkos.co.il  Thu Jun  3 08:05:36 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Thu, 3 Jun 2010 15:05:36 +0300
Subject: [PATCH v3 00/14] omap: mailbox: bunch of cleanups
In-Reply-To: <20100603114726.GC7127@n2100.arm.linux.org.uk>
References: <1274548465-20208-1-git-send-email-felipe.contreras@gmail.com>
	<20100603.094022.200375421.Hiroshi.DOYU@nokia.com>
	<20100603114726.GC7127@n2100.arm.linux.org.uk>
Message-ID: <20100603120535.GC32496@jasper.tkos.co.il>

Hi Russell,

On Thu, Jun 03, 2010 at 12:47:26PM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 03, 2010 at 09:40:22AM +0300, Hiroshi DOYU wrote:
> > > Felipe Contreras (14):
> > >   omap: mailbox: trivial whitespace cleanups
> > >   omap: mailbox: trivial cleanups
> 
> I think folk need to read this:
> 
> 	http://lkml.org/lkml/2010/6/2/472
> 
> and consider what it means for the future, and what can be done to reduce
> the amount of "churn".

Can you elaborate a bit? I guess you generally agree with Linus on this. What 
should be done in your opinion for the ARM arch to produce less "churn".

baruch

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From ext-phil.2.carmody at nokia.com  Thu Jun  3 08:17:20 2010
From: ext-phil.2.carmody at nokia.com (Phil Carmody)
Date: Thu,  3 Jun 2010 15:17:20 +0300
Subject: [PATCH 1/3] ARM: module - simplify code with temporaries
In-Reply-To: <1275567442-11370-1-git-send-email-ext-phil.2.carmody@nokia.com>
References: <1275567442-11370-1-git-send-email-ext-phil.2.carmody@nokia.com>
Message-ID: <1275567442-11370-2-git-send-email-ext-phil.2.carmody@nokia.com>

Less to read.

Signed-off-by: Phil Carmody <ext-phil.2.carmody at nokia.com>
---
 arch/arm/kernel/module.c |   14 ++++++++------
 1 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index c628bdf..d531a63 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -71,17 +71,19 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
 	Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
 
 	for (s = sechdrs; s < sechdrs_end; s++) {
-		if (strcmp(".ARM.exidx.init.text", secstrings + s->sh_name) == 0)
+		char const *secname = secstrings + s->sh_name;
+
+		if (strcmp(".ARM.exidx.init.text", secname) == 0)
 			mod->arch.unw_sec_init = s;
-		else if (strcmp(".ARM.exidx.devinit.text", secstrings + s->sh_name) == 0)
+		else if (strcmp(".ARM.exidx.devinit.text", secname) == 0)
 			mod->arch.unw_sec_devinit = s;
-		else if (strcmp(".ARM.exidx", secstrings + s->sh_name) == 0)
+		else if (strcmp(".ARM.exidx", secname) == 0)
 			mod->arch.unw_sec_core = s;
-		else if (strcmp(".init.text", secstrings + s->sh_name) == 0)
+		else if (strcmp(".init.text", secname) == 0)
 			mod->arch.sec_init_text = s;
-		else if (strcmp(".devinit.text", secstrings + s->sh_name) == 0)
+		else if (strcmp(".devinit.text", secname) == 0)
 			mod->arch.sec_devinit_text = s;
-		else if (strcmp(".text", secstrings + s->sh_name) == 0)
+		else if (strcmp(".text", secname) == 0)
 			mod->arch.sec_core_text = s;
 	}
 #endif
-- 
1.6.0.4



From ext-phil.2.carmody at nokia.com  Thu Jun  3 08:17:22 2010
From: ext-phil.2.carmody at nokia.com (Phil Carmody)
Date: Thu,  3 Jun 2010 15:17:22 +0300
Subject: [PATCH 3/3] ARM: module - additional unwind tables for exit/devexit
	sections
In-Reply-To: <1275567442-11370-3-git-send-email-ext-phil.2.carmody@nokia.com>
References: <1275567442-11370-1-git-send-email-ext-phil.2.carmody@nokia.com>
	<1275567442-11370-2-git-send-email-ext-phil.2.carmody@nokia.com>
	<1275567442-11370-3-git-send-email-ext-phil.2.carmody@nokia.com>
Message-ID: <1275567442-11370-4-git-send-email-ext-phil.2.carmody@nokia.com>

Without these, exit functions cannot be stack-traced, so to speak.
This implies that module unloads that perform allocations (don't
laugh) will cause noisy warnings on the console when kmemleak is
enabled, as it presumes that all code's call chains are traceable.
Similarly, BUGs and WARN_ONs will give additional console spam.

Signed-off-by: Phil Carmody <ext-phil.2.carmody at nokia.com>
---
 arch/arm/include/asm/module.h |    2 ++
 arch/arm/kernel/module.c      |    8 ++++++++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index 2164061..fcff0d2 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -17,6 +17,8 @@ enum {
 	ARM_SEC_INIT,
 	ARM_SEC_DEVINIT,
 	ARM_SEC_CORE,
+	ARM_SEC_EXIT,
+	ARM_SEC_DEVEXIT,
 	ARM_SEC_MAX,
 };
 struct mod_arch_specific {
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index bcf928e..8eaff1c 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -80,12 +80,20 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
 			maps[ARM_SEC_DEVINIT].unw_sec = s;
 		else if (strcmp(".ARM.exidx", secname) == 0)
 			maps[ARM_SEC_CORE].unw_sec = s;
+		else if (strcmp(".ARM.exidx.exit.text", secname) == 0)
+			maps[ARM_SEC_EXIT].unw_sec = s;
+		else if (strcmp(".ARM.exidx.devexit.text", secname) == 0)
+			maps[ARM_SEC_DEVEXIT].unw_sec = s;
 		else if (strcmp(".init.text", secname) == 0)
 			maps[ARM_SEC_INIT].sec_text = s;
 		else if (strcmp(".devinit.text", secname) == 0)
 			maps[ARM_SEC_DEVINIT].sec_text = s;
 		else if (strcmp(".text", secname) == 0)
 			maps[ARM_SEC_CORE].sec_text = s;
+		else if (strcmp(".exit.text", secname) == 0)
+			maps[ARM_SEC_EXIT].sec_text = s;
+		else if (strcmp(".devexit.text", secname) == 0)
+			maps[ARM_SEC_DEVEXIT].sec_text = s;
 	}
 #endif
 	return 0;
-- 
1.6.0.4



From ext-phil.2.carmody at nokia.com  Thu Jun  3 08:17:21 2010
From: ext-phil.2.carmody at nokia.com (Phil Carmody)
Date: Thu,  3 Jun 2010 15:17:21 +0300
Subject: [PATCH 2/3] ARM: module - simplify unwind table handling
In-Reply-To: <1275567442-11370-2-git-send-email-ext-phil.2.carmody@nokia.com>
References: <1275567442-11370-1-git-send-email-ext-phil.2.carmody@nokia.com>
	<1275567442-11370-2-git-send-email-ext-phil.2.carmody@nokia.com>
Message-ID: <1275567442-11370-3-git-send-email-ext-phil.2.carmody@nokia.com>

The various sections are all dealt with similarly, so factor out
that common behaviour.

Signed-off-by: Phil Carmody <ext-phil.2.carmody at nokia.com>
---
 arch/arm/include/asm/module.h |   29 +++++++++++++++----------
 arch/arm/kernel/module.c      |   46 +++++++++++++++++------------------------
 2 files changed, 36 insertions(+), 39 deletions(-)

diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index e4dfa69..2164061 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -7,20 +7,25 @@
 
 struct unwind_table;
 
-struct mod_arch_specific
-{
 #ifdef CONFIG_ARM_UNWIND
-	Elf_Shdr *unw_sec_init;
-	Elf_Shdr *unw_sec_devinit;
-	Elf_Shdr *unw_sec_core;
-	Elf_Shdr *sec_init_text;
-	Elf_Shdr *sec_devinit_text;
-	Elf_Shdr *sec_core_text;
-	struct unwind_table *unwind_init;
-	struct unwind_table *unwind_devinit;
-	struct unwind_table *unwind_core;
-#endif
+struct arm_unwind_mapping {
+	Elf_Shdr *unw_sec;
+	Elf_Shdr *sec_text;
+	struct unwind_table *unwind;
+};
+enum {
+	ARM_SEC_INIT,
+	ARM_SEC_DEVINIT,
+	ARM_SEC_CORE,
+	ARM_SEC_MAX,
 };
+struct mod_arch_specific {
+	struct arm_unwind_mapping map[ARM_SEC_MAX];
+};
+#else
+struct mod_arch_specific {
+}
+#endif
 
 /*
  * Include the ARM architecture version.
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index d531a63..bcf928e 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -69,22 +69,23 @@ int module_frob_arch_sections(Elf_Ehdr *hdr,
 {
 #ifdef CONFIG_ARM_UNWIND
 	Elf_Shdr *s, *sechdrs_end = sechdrs + hdr->e_shnum;
+	struct arm_unwind_mapping *maps = mod->arch.map;
 
 	for (s = sechdrs; s < sechdrs_end; s++) {
 		char const *secname = secstrings + s->sh_name;
 
 		if (strcmp(".ARM.exidx.init.text", secname) == 0)
-			mod->arch.unw_sec_init = s;
+			maps[ARM_SEC_INIT].unw_sec = s;
 		else if (strcmp(".ARM.exidx.devinit.text", secname) == 0)
-			mod->arch.unw_sec_devinit = s;
+			maps[ARM_SEC_DEVINIT].unw_sec = s;
 		else if (strcmp(".ARM.exidx", secname) == 0)
-			mod->arch.unw_sec_core = s;
+			maps[ARM_SEC_CORE].unw_sec = s;
 		else if (strcmp(".init.text", secname) == 0)
-			mod->arch.sec_init_text = s;
+			maps[ARM_SEC_INIT].sec_text = s;
 		else if (strcmp(".devinit.text", secname) == 0)
-			mod->arch.sec_devinit_text = s;
+			maps[ARM_SEC_DEVINIT].sec_text = s;
 		else if (strcmp(".text", secname) == 0)
-			mod->arch.sec_core_text = s;
+			maps[ARM_SEC_CORE].sec_text = s;
 	}
 #endif
 	return 0;
@@ -260,31 +261,22 @@ apply_relocate_add(Elf32_Shdr *sechdrs, const char *strtab,
 #ifdef CONFIG_ARM_UNWIND
 static void register_unwind_tables(struct module *mod)
 {
-	if (mod->arch.unw_sec_init && mod->arch.sec_init_text)
-		mod->arch.unwind_init =
-			unwind_table_add(mod->arch.unw_sec_init->sh_addr,
-					 mod->arch.unw_sec_init->sh_size,
-					 mod->arch.sec_init_text->sh_addr,
-					 mod->arch.sec_init_text->sh_size);
-	if (mod->arch.unw_sec_devinit && mod->arch.sec_devinit_text)
-		mod->arch.unwind_devinit =
-			unwind_table_add(mod->arch.unw_sec_devinit->sh_addr,
-					 mod->arch.unw_sec_devinit->sh_size,
-					 mod->arch.sec_devinit_text->sh_addr,
-					 mod->arch.sec_devinit_text->sh_size);
-	if (mod->arch.unw_sec_core && mod->arch.sec_core_text)
-		mod->arch.unwind_core =
-			unwind_table_add(mod->arch.unw_sec_core->sh_addr,
-					 mod->arch.unw_sec_core->sh_size,
-					 mod->arch.sec_core_text->sh_addr,
-					 mod->arch.sec_core_text->sh_size);
+	int i;
+	for (i = 0; i < ARM_SEC_MAX; ++i) {
+		struct arm_unwind_mapping *map = &mod->arch.map[i];
+		if (map->unw_sec && map->sec_text)
+			map->unwind = unwind_table_add(map->unw_sec->sh_addr,
+						       map->unw_sec->sh_size,
+						       map->sec_text->sh_addr,
+						       map->sec_text->sh_size);
+	}
 }
 
 static void unregister_unwind_tables(struct module *mod)
 {
-	unwind_table_del(mod->arch.unwind_init);
-	unwind_table_del(mod->arch.unwind_devinit);
-	unwind_table_del(mod->arch.unwind_core);
+	int i = ARM_SEC_MAX;
+	while (--i >= 0)
+		unwind_table_del(mod->arch.map[i].unwind);
 }
 #else
 static inline void register_unwind_tables(struct module *mod) { }
-- 
1.6.0.4



From ext-phil.2.carmody at nokia.com  Thu Jun  3 08:17:19 2010
From: ext-phil.2.carmody at nokia.com (Phil Carmody)
Date: Thu,  3 Jun 2010 15:17:19 +0300
Subject: [PATCH 0/3] ARM: unwind extension
Message-ID: <1275567442-11370-1-git-send-email-ext-phil.2.carmody@nokia.com>


The first two patches are simply preparation for the third, making it
effectively trivial, even though it's the only one with a concrete 
change in behaviour.

The origins of this patchset are the discovery that unwind and kmemleak
don't always cooperate well with each other - any allocation within 
an exit or devexit function causes kmemleak to look up symbols that 
aren't in any unwind table. This of course means that all WARN_ONs and
BUGs will suffer the same fate.

It could certainly be said that with a typical system the linked list
has grown too large to be practical as a container, and some improvements
could be made in that direction in the future.

Cheers,
Phil


From amit.kucheria at canonical.com  Thu Jun  3 08:39:08 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Thu, 3 Jun 2010 15:39:08 +0300
Subject: [V2 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <20100603123908.GB3527@matterhorn.lan>

Two comments inline.

On 10 Jun 03, Jason Wang wrote:
> 3-stack is a reference board from Freescale for their i.MX51 SoC.
> 
> Add board definition, Kconfig and Makefile to enable Freescale 3-stack
> board.
> 
> Boot tested on a i.MX51 3-stack Rev2.0 board
> 
> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
> ---
>  arch/arm/mach-mx5/Kconfig                       |    5 +
>  arch/arm/mach-mx5/Makefile                      |    2 +-
>  arch/arm/mach-mx5/board-mx51_3ds.c              |  263 +++++++++++++++++++++++
>  arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   70 ++++++
>  arch/arm/plat-mxc/include/mach/iomux-mx51.h     |   10 +-
>  5 files changed, 345 insertions(+), 5 deletions(-)
>  create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
>  create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
> 
> diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
> index 1576d51..6d45f44 100644
> --- a/arch/arm/mach-mx5/Kconfig
> +++ b/arch/arm/mach-mx5/Kconfig
> @@ -15,4 +15,9 @@ config MACH_MX51_BABBAGE
>  	  u-boot. This includes specific configurations for the board and its
>  	  peripherals.
>  
> +config MACH_MX51_3DS
> +	bool "Support MX51PDK (3DS)"
> +	help
> +	  Include support for MX51PDK (3DS) platform. This includes specific
> +	  configurations for the board and its peripherals.
>  endif
> diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
> index bf23f86..c757c59 100644
> --- a/arch/arm/mach-mx5/Makefile
> +++ b/arch/arm/mach-mx5/Makefile
> @@ -6,4 +6,4 @@
>  obj-y   := cpu.o mm.o clock-mx51.o devices.o
>  
>  obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
> -
> +obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
> diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
> new file mode 100644
> index 0000000..5da90e9
> --- /dev/null
> +++ b/arch/arm/mach-mx5/board-mx51_3ds.c
> @@ -0,0 +1,263 @@
> +/*
> + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +#include <linux/gpio.h>
> +#include <linux/smsc911x.h>
> +
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/time.h>
> +
> +#include <mach/hardware.h>
> +#include <mach/common.h>
> +#include <mach/iomux-mx51.h>
> +#include <mach/board-mx51_3ds.h>
> +#include <mach/imx-uart.h>
> +
> +#include "devices.h"
> +
> +static void __iomem *brd_io;
> +
> +static void expio_ack_irq(u32 irq);
> +
> +static struct pad_desc mx51_3ds_pads[] = {
> +	/* UART1 */
> +	MX51_PAD_UART1_RXD__UART1_RXD,
> +	MX51_PAD_UART1_TXD__UART1_TXD,
> +	MX51_PAD_UART1_RTS__UART1_RTS,
> +	MX51_PAD_UART1_CTS__UART1_CTS,
> +
> +	/* UART2 */
> +	MX51_PAD_UART2_RXD__UART2_RXD,
> +	MX51_PAD_UART2_TXD__UART2_TXD,
> +	MX51_PAD_EIM_D25__UART2_CTS,
> +	MX51_PAD_EIM_D26__UART2_RTS,
> +
> +	/* UART3 */
> +	MX51_PAD_GPIO_1_22__UART3_RXD,
> +	MX51_PAD_GPIO_1_23__UART3_TXD,
> +	MX51_PAD_EIM_D24__UART3_CTS,
> +	MX51_PAD_EIM_D27__UART3_RTS,
> +
> +	/* CPLD PARENT IRQ PIN */
> +	MX51_PAD_GPIO_1_6__GPIO1_6,
> +};
> +
> +
> +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
> +static struct resource smsc911x_resources[] = {
> +	{
> +		.start = LAN9217_BASE_ADDR,
> +		.end = LAN9217_BASE_ADDR + 0x100 - 1,
> +		.flags = IORESOURCE_MEM,
> +	} , {
> +		.start = EXPIO_INT_ENET,
> +		.end = EXPIO_INT_ENET,
> +		.flags = IORESOURCE_IRQ,
> +	},
> +};
> +
> +struct smsc911x_platform_config smsc911x_config = {
> +	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
> +	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
> +};
> +
> +static struct platform_device smsc_lan9217_device = {
> +	.name = "smsc911x",
> +	.id = 0,
> +	.dev = {
> +		.platform_data = &smsc911x_config,
> +	},
> +	.num_resources = ARRAY_SIZE(smsc911x_resources),
> +	.resource = smsc911x_resources,
> +};

You forgot to move this platform_device to devices.c

> +static void mxc_init_enet(void)
> +{
> +	if (brd_io != NULL)
> +		platform_device_register(&smsc_lan9217_device);
> +}
> +#else
> +static inline void mxc_init_enet(void)
> +{
> +}
> +#endif
> +
> +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
> +{
> +	u32 imr_val;
> +	u32 int_valid;
> +	u32 expio_irq;
> +
> +	desc->chip->mask(irq);	/* irq = gpio irq number */
> +
> +	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
> +	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
> +
> +	expio_irq = MXC_BOARD_IRQ_START;
> +	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
> +		struct irq_desc *d;
> +		if ((int_valid & 1) == 0)
> +			continue;
> +		d = irq_desc + expio_irq;
> +		if (unlikely(!(d->handle_irq)))
> +			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
> +		else
> +			d->handle_irq(expio_irq, d);
> +	}
> +
> +	desc->chip->ack(irq);
> +	desc->chip->unmask(irq);
> +}
> +
> +/*
> + * Disable an expio pin's interrupt by setting the bit in the imr.
> + * @param irq		an expio virtual irq number
> + */
> +static void expio_mask_irq(u32 irq)
> +{
> +	u16 reg;
> +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> +
> +	reg = __raw_readw(brd_io + INTR_MASK_REG);
> +	reg |= (1 << expio);
> +	__raw_writew(reg, brd_io + INTR_MASK_REG);
> +}
> +
> +/*
> + * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
> + * @param irq		an expanded io virtual irq number
> + */
> +static void expio_ack_irq(u32 irq)
> +{
> +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> +
> +	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
> +	__raw_writew(0, brd_io + INTR_RESET_REG);
> +	expio_mask_irq(irq);
> +}
> +
> +/*
> + * Enable a expio pin's interrupt by clearing the bit in the imr.
> + * @param irq		a expio virtual irq number
> + */
> +static void expio_unmask_irq(u32 irq)
> +{
> +	u16 reg;
> +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> +
> +	reg = __raw_readw(brd_io + INTR_MASK_REG);
> +	reg &= ~(1 << expio);
> +	__raw_writew(reg, brd_io + INTR_MASK_REG);
> +}
> +
> +static struct irq_chip expio_irq_chip = {
> +	.ack = expio_ack_irq,
> +	.mask = expio_mask_irq,
> +	.unmask = expio_unmask_irq,
> +};
> +
> +static int __init mxc_expio_init(void)
> +{
> +	int i;
> +
> +	brd_io = ioremap(BOARD_IO_ADDR, SZ_4K);
> +	if (brd_io == NULL)
> +		return -ENOMEM;
> +
> +	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
> +	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
> +	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
> +		pr_info("3-Stack Debug board not detected\n");
> +		iounmap(brd_io);
> +		brd_io = NULL;
> +		return -ENODEV;
> +	}
> +
> +	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
> +		readw(brd_io + CPLD_CODE_VER_REG));
> +
> +	/*
> +	 * Configure INT line as GPIO input
> +	 */
> +	gpio_request(MX51_3DS_CPLD_IRQ_PIN, "gpio1_6");
> +	gpio_direction_input(MX51_3DS_CPLD_IRQ_PIN);
> +
> +	/* disable the interrupt and clear the status */
> +	__raw_writew(0, brd_io + INTR_MASK_REG);
> +	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
> +	__raw_writew(0, brd_io + INTR_RESET_REG);
> +	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
> +	for (i = MXC_EXP_IO_BASE;
> +	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
> +		set_irq_chip(i, &expio_irq_chip);
> +		set_irq_handler(i, handle_level_irq);
> +		set_irq_flags(i, IRQF_VALID);
> +	}
> +	set_irq_type(EXPIO_PARENT_INT, IRQF_TRIGGER_LOW);
> +	set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler);
> +
> +	return 0;
> +}
> +
> +/* Serial ports */
> +#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
> +static struct imxuart_platform_data uart_pdata = {
> +	.flags = IMXUART_HAVE_RTSCTS,
> +};
> +
> +static inline void mxc_init_imx_uart(void)
> +{
> +	mxc_register_device(&mxc_uart_device0, &uart_pdata);
> +	mxc_register_device(&mxc_uart_device1, &uart_pdata);
> +	mxc_register_device(&mxc_uart_device2, &uart_pdata);
> +}
> +#else /* !SERIAL_IMX */
> +static inline void mxc_init_imx_uart(void)
> +{
> +}
> +#endif /* SERIAL_IMX */
> +
> +/*
> + * Board specific initialization.
> + */
> +static void __init mxc_board_init(void)
> +{
> +	mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
> +					ARRAY_SIZE(mx51_3ds_pads));
> +	mxc_init_imx_uart();
> +	mxc_expio_init();
> +	mxc_init_enet();
> +}
> +
> +static void __init mx51_3ds_timer_init(void)
> +{
> +	mx51_clocks_init(32768, 24000000, 22579200, 0);
> +}
> +
> +static struct sys_timer mxc_timer = {
> +	.init	= mx51_3ds_timer_init,
> +};
> +
> +MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
> +	.phys_io = MX51_AIPS1_BASE_ADDR,
> +	.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
> +	.boot_params = PHYS_OFFSET + 0x100,
> +	.map_io = mx51_map_io,
> +	.init_irq = mx51_init_irq,
> +	.init_machine = mxc_board_init,
> +	.timer = &mxc_timer,
> +MACHINE_END
> diff --git a/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
> new file mode 100644
> index 0000000..035f7bc
> --- /dev/null
> +++ b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
> @@ -0,0 +1,70 @@
> +/*
> + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#ifndef __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
> +#define __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
> +
> +/*
> + * @file plat-mxc/include/mach/board-mx51_3ds.h
> + *
> + * @brief This file contains all the board level configuration options.

Remove this @file, @brief.

> + * It currently hold the options defined for MX51 3Stack Platform.
> + *
> + */
> +
> +#define DEBUG_BOARD_BASE_ADDRESS MX51_CS5_BASE_ADDR
> +/* LAN9217 ethernet base address */
> +#define LAN9217_BASE_ADDR	(DEBUG_BOARD_BASE_ADDRESS + 0x0)
> +/* External UART */
> +#define UARTA_BASE_ADDR		(DEBUG_BOARD_BASE_ADDRESS + 0x8000)
> +#define UARTB_BASE_ADDR		(DEBUG_BOARD_BASE_ADDRESS + 0x10000)
> +
> +#define BOARD_IO_ADDR		(DEBUG_BOARD_BASE_ADDRESS + 0x20000)
> +/* LED switchs */
> +#define LED_SWITCH_REG		0x00
> +/* buttons */
> +#define SWITCH_BUTTONS_REG	0x08
> +/* status, interrupt */
> +#define INTR_STATUS_REG	0x10
> +#define INTR_MASK_REG		0x38
> +#define INTR_RESET_REG		0x20
> +/* magic word for debug CPLD */
> +#define MAGIC_NUMBER1_REG	0x40
> +#define MAGIC_NUMBER2_REG	0x48
> +/* CPLD code version */
> +#define CPLD_CODE_VER_REG	0x50
> +/* magic word for debug CPLD */
> +#define MAGIC_NUMBER3_REG	0x58
> +/* module reset register*/
> +#define MODULE_RESET_REG	0x60
> +/* CPU ID and Personality ID */
> +#define MCU_BOARD_ID_REG	0x68
> +
> +#define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
> +
> +#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
> +
> +#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
> +#define MXC_MAX_EXP_IO_LINES	16
> +
> +/* interrupts like external uart , external ethernet etc*/
> +#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
> +#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
> +#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
> +#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
> +#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
> +
> +/* Define CPLD interrupt pin */
> +#define MX51_3DS_CPLD_IRQ_PIN	(GPIO_PORTA + 6)
> +
> +#endif	/* __ASM_ARCH_MXC_BOARD_MX51_3DS_H__ */
> diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
> index ab0f95d..895c750 100644
> --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
> +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
> @@ -70,8 +70,10 @@ typedef enum iomux_config {
>  /* Babbage UART3 */
>  #define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
>  #define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
> +#define MX51_PAD_EIM_D25__UART2_CTS	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT4, 0x0, 0, MX51_UART2_PAD_CTRL)
>  #define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
> -#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
> +#define MX51_PAD_EIM_D26__UART2_RTS	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
> +#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
>  
>  #define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
>  #define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
> @@ -202,8 +204,8 @@ typedef enum iomux_config {
>  #define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
>  #define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
>  
> -#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_UART3_PAD_CTRL)
>  #define MX51_PAD_GPIO_1_24__OWIRE_LINE	IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
>  #define MX51_PAD_KEY_ROW0__KEY_ROW0	IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
>  #define MX51_PAD_KEY_ROW1__KEY_ROW1	IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
> @@ -306,7 +308,7 @@ typedef enum iomux_config {
>  #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
>  #define MX51_PAD_GPIO_1_4__GPIO1_4	IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
>  #define MX51_PAD_GPIO_1_5__GPIO1_5	IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
>  #define MX51_PAD_GPIO_1_7__GPIO1_7	IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
>  #define MX51_PAD_GPIO_1_8__GPIO1_8	IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
>  						(PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
> -- 
> 1.5.6.5
> 

-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------


From sedji.gaouaou at atmel.com  Thu Jun  3 08:46:26 2010
From: sedji.gaouaou at atmel.com (Sedji Gaouaou)
Date: Thu, 03 Jun 2010 14:46:26 +0200
Subject: AC97 audio broken on SAM9263EK?
In-Reply-To: <4C050D97.4000404@visionsystems.de>
References: <4B85789D.6000704@billgatliff.com>
	<4B864C66.6060209@atmel.com>	<4B867108.2050806@billgatliff.com>
	<4B86AA29.8010806@atmel.com>	<4B89E1BB.6090504@billgatliff.com>
	<4B8B9849.5040203@atmel.com> <4B96571A.3040403@visionsystems.de>
	<4B96668E.6090805@atmel.com> <4B975C9A.3020106@visionsystems.de>
	<4B97602C.6070608@atmel.com> <4B97BD8C.3030502@visionsystems.de>
	<4B97C086.2080404@atmel.com> <4C050D97.4000404@visionsystems.de>
Message-ID: <4C07A422.5070505@atmel.com>

Hi Yegor,

It is an error indeed, it should be a debug message.

Regards,
Sedji

Le 6/1/2010 3:39 PM, Yegor Yefremov a ?crit :
> Hi,
>
>>> When do you think the driver could hit the mainline kernel? Till
>>> 2.6.35 open window?
>>
>> It has been acked, but I don't know when it will be in the mainline kernel.
>
> have just tested 2.6.35-rc1 with mainline ac97 driver and found this issue. During playback I see following output on the console:
>
> ...
> atmel_ac97c atmel_ac97c.0: channel A event
> atmel_ac97c atmel_ac97c.0: channel A event
> atmel_ac97c atmel_ac97c.0: channel A event
> ...
>
> If I see it right these, lines come from sound/atmel/ac97c.c->atmel_ac97c_interrupt():
>
> dev_info(&chip->pdev->dev, "channel A event%s%s%s%s%s%s\n",
>                                  casr&  AC97C_CSR_OVRUN   ? " OVRUN"   : "",
>                                  casr&  AC97C_CSR_RXRDY   ? " RXRDY"   : "",
>                                  casr&  AC97C_CSR_UNRUN   ? " UNRUN"   : "",
>                                  casr&  AC97C_CSR_TXEMPTY ? " TXEMPTY" : "",
>                                  casr&  AC97C_CSR_TXRDY   ? " TXRDY"   : "",
>                                  !casr                    ? " NONE"    : "");
>
>
>
> It is necessary to output this message in normal mode or is it a debug message?
>
> Regards,
> Yegor
>




From vzapolskiy at gmail.com  Thu Jun  3 09:25:50 2010
From: vzapolskiy at gmail.com (Vladimir Zapolskiy)
Date: Thu,  3 Jun 2010 17:25:50 +0400
Subject: [PATCH Resend] PCMCIA: add Cogent CSB726 PCMCIA support
Message-ID: <1275571550-24437-1-git-send-email-vzapolskiy@gmail.com>

This patch adds support for CompactFlash socket found in CSB726 board.

Signed-off-by: Vladimir Zapolskiy <vzapolskiy at gmail.com>
Cc: Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>
Cc: Dominik Brodowski <linux at dominikbrodowski.net>
Acked-by: Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>
Acked-by: Dominik Brodowski<linux at dominikbrodowski.net>
---
 drivers/pcmcia/Kconfig         |    3 +-
 drivers/pcmcia/Makefile        |    1 +
 drivers/pcmcia/pxa2xx_csb726.c |  156 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 159 insertions(+), 1 deletions(-)
 create mode 100644 drivers/pcmcia/pxa2xx_csb726.c

diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
index 9f3adbd..168219b 100644
--- a/drivers/pcmcia/Kconfig
+++ b/drivers/pcmcia/Kconfig
@@ -208,7 +208,8 @@ config PCMCIA_PXA2XX
 	depends on ARM && ARCH_PXA && PCMCIA
 	depends on (ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL \
 		    || MACH_ARMCORE || ARCH_PXA_PALM || TRIZEPS_PCMCIA \
-		    || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2)
+		    || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2 \
+		    || MACH_CSB726)
 	select PCMCIA_SOC_COMMON
 	help
 	  Say Y here to include support for the PXA2xx PCMCIA controller
diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
index 83ff802..efcda3f 100644
--- a/drivers/pcmcia/Makefile
+++ b/drivers/pcmcia/Makefile
@@ -74,5 +74,6 @@ pxa2xx-obj-$(CONFIG_MACH_PALMTC)		+= pxa2xx_palmtc.o
 pxa2xx-obj-$(CONFIG_MACH_PALMLD)		+= pxa2xx_palmld.o
 pxa2xx-obj-$(CONFIG_MACH_E740)			+= pxa2xx_e740.o
 pxa2xx-obj-$(CONFIG_MACH_STARGATE2)		+= pxa2xx_stargate2.o
+pxa2xx-obj-$(CONFIG_MACH_CSB726)		+= pxa2xx_csb726.o
 
 obj-$(CONFIG_PCMCIA_PXA2XX)			+= pxa2xx_base.o $(pxa2xx-obj-y)
diff --git a/drivers/pcmcia/pxa2xx_csb726.c b/drivers/pcmcia/pxa2xx_csb726.c
new file mode 100644
index 0000000..bd86e90
--- /dev/null
+++ b/drivers/pcmcia/pxa2xx_csb726.c
@@ -0,0 +1,156 @@
+/*
+ * linux/drivers/pcmcia/pxa2xx_csb726.c
+ *
+ * Cogent CSB726 Compact Flash specific routines.
+ *
+ * Copyright 2010 Vladimir Zapolskiy <vzapolskiy at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+
+#include <pcmcia/ss.h>
+
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+
+#include "soc_common.h"
+
+#define GPIO_CF_RDY     98
+#define GPIO_CF_CD      99
+#define GPIO_CF_RST     103
+
+static struct pcmcia_irqs irqs[] = {
+	{
+		.sock = 0,
+		.irq  = IRQ_GPIO(GPIO_CF_CD),
+		.str  = "PCMCIA0 CD",
+	},
+};
+
+static int csb726_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
+{
+	int ret;
+
+	ret = gpio_request(GPIO_CF_RST, "CF reset");
+	if (ret)
+		return ret;
+	gpio_direction_output(GPIO_CF_RST, 0);
+
+	skt->socket.pci_irq = IRQ_GPIO(GPIO_CF_RDY);
+	ret = soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
+	if (!ret)
+		gpio_free(GPIO_CF_RST);
+
+	return ret;
+}
+
+static void csb726_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
+{
+	soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs));
+	gpio_free(GPIO_CF_RST);
+}
+
+static void csb726_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
+				       struct pcmcia_state *state)
+{
+	state->detect = !gpio_get_value(GPIO_CF_CD);
+	state->ready  = !!gpio_get_value(GPIO_CF_RDY);
+	state->bvd1   = 0; /* not available - battery detect on card */
+	state->bvd2   = 0; /* not available */
+	state->vs_3v  = 1; /* not available - voltage detect for card */
+	state->vs_Xv  = 0; /* not available */
+	state->wrprot = 0; /* not available - write protect */
+}
+
+static int csb726_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
+					  const socket_state_t *state)
+{
+	switch (skt->nr) {
+	case 0:
+		if (state->flags & SS_RESET) {
+			/* reset */
+			gpio_set_value(GPIO_CF_RST, 1);
+			udelay(10);
+			gpio_set_value(GPIO_CF_RST, 0);
+		}
+		break;
+	}
+
+	return 0;
+}
+
+static void csb726_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
+{
+	soc_pcmcia_enable_irqs(skt, irqs, ARRAY_SIZE(irqs));
+}
+
+static void csb726_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
+{
+	soc_pcmcia_disable_irqs(skt, irqs, ARRAY_SIZE(irqs));
+}
+
+static struct pcmcia_low_level csb726_pcmcia_ops __initdata = {
+	.owner			= THIS_MODULE,
+	.hw_init		= csb726_pcmcia_hw_init,
+	.hw_shutdown		= csb726_pcmcia_hw_shutdown,
+	.socket_state		= csb726_pcmcia_socket_state,
+	.configure_socket	= csb726_pcmcia_configure_socket,
+	.socket_init		= csb726_pcmcia_socket_init,
+	.socket_suspend		= csb726_pcmcia_socket_suspend,
+	.nr			= 1,
+};
+
+static struct platform_device *csb726_pcmcia_device;
+
+static int __init csb726_pcmcia_init(void)
+{
+	int ret;
+
+	if (!machine_is_csb726())
+		return -ENODEV;
+
+	csb726_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
+	if (!csb726_pcmcia_device)
+		return -ENOMEM;
+
+	ret = platform_device_add_data(csb726_pcmcia_device,
+				       &csb726_pcmcia_ops,
+				       sizeof(csb726_pcmcia_ops));
+	if (ret)
+		goto error_put_platform_device;
+
+	ret = platform_device_add(csb726_pcmcia_device);
+	if (ret)
+		goto error_put_platform_device;
+
+	return 0;
+
+error_put_platform_device:
+	platform_device_put(csb726_pcmcia_device);
+
+	return ret;
+}
+
+static void __exit csb726_pcmcia_exit(void)
+{
+	platform_device_unregister(csb726_pcmcia_device);
+}
+
+fs_initcall(csb726_pcmcia_init);
+module_exit(csb726_pcmcia_exit);
+
+MODULE_DESCRIPTION("Cogent CSB726 Compact Flash Driver");
+MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy at gmail.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:pxa2xx-pcmcia");
-- 
1.7.0.4



From ben-linux at fluff.org  Thu Jun  3 09:36:39 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Thu, 3 Jun 2010 14:36:39 +0100
Subject: [PATCH] S5PV210: Increase the VIC_NR as 4
In-Reply-To: <20100603103144.GA7127@n2100.arm.linux.org.uk>
References: <20100603100954.GA17434@july>
	<20100603103144.GA7127@n2100.arm.linux.org.uk>
Message-ID: <20100603133639.GR7248@trinity.fluff.org>

On Thu, Jun 03, 2010 at 11:31:44AM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 03, 2010 at 07:09:54PM +0900, Kyungmin Park wrote:
> > The S5PV210 SoC have 4 VICs. It requires for suspend and resume.
> 
> Isn't this negated by Ben's "ARM: VIC: Allocate VIC PM device from slab"
> patch?

I was awaiting the feedback from other archs which I don't have access
to... 
 
> Incidentally, shouldn't Ben's patch remove this configuration option too?

Yes, you're right, should have removed these.

> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> > 
> > diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
> > index 0a34c81..0ac3d81 100644
> > --- a/arch/arm/common/Kconfig
> > +++ b/arch/arm/common/Kconfig
> > @@ -6,6 +6,7 @@ config ARM_VIC
> >  
> >  config ARM_VIC_NR
> >  	int
> > +	default 4 if ARCH_S5PV210
> >  	default 2
> >  	depends on ARM_VIC
> >  	help
> > 
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From l.fu at pengutronix.de  Thu Jun  3 09:55:47 2010
From: l.fu at pengutronix.de (Luotao Fu)
Date: Thu,  3 Jun 2010 15:55:47 +0200
Subject: [PATCH 1/2] ARM/MX2: add framebuffer device support and TFT to pca100
	board
In-Reply-To: <1275573348-26564-1-git-send-email-l.fu@pengutronix.de>
References: <1275573348-26564-1-git-send-email-l.fu@pengutronix.de>
Message-ID: <1275573348-26564-2-git-send-email-l.fu@pengutronix.de>

this one adds the frambuffer device and a TFT panel to the PhyCard-S
(pca100) board.

Signed-off-by: Luotao Fu <l.fu at pengutronix.de>
---
 arch/arm/mach-mx2/mach-pca100.c |   68 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 68 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c
index 778fff2..cf3d57b 100644
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-mx2/mach-pca100.c
@@ -49,6 +49,7 @@
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
+#include <mach/imxfb.h>
 
 #include "devices.h"
 
@@ -131,6 +132,32 @@ static int pca100_pins[] = {
 	PD23_AF_USBH2_DATA2,
 	PD24_AF_USBH2_DATA1,
 	PD26_AF_USBH2_DATA5,
+	/* display */
+	PA5_PF_LSCLK,
+	PA6_PF_LD0,
+	PA7_PF_LD1,
+	PA8_PF_LD2,
+	PA9_PF_LD3,
+	PA10_PF_LD4,
+	PA11_PF_LD5,
+	PA12_PF_LD6,
+	PA13_PF_LD7,
+	PA14_PF_LD8,
+	PA15_PF_LD9,
+	PA16_PF_LD10,
+	PA17_PF_LD11,
+	PA18_PF_LD12,
+	PA19_PF_LD13,
+	PA20_PF_LD14,
+	PA21_PF_LD15,
+	PA22_PF_LD16,
+	PA23_PF_LD17,
+	PA26_PF_PS,
+	PA28_PF_HSYNC,
+	PA29_PF_VSYNC,
+	PA31_PF_OE_ACD,
+	/* LVDS Transceiver */
+	LVDS_PWR_DWN_GPIO | GPIO_GPIO | GPIO_IN,
 };
 
 static struct imxuart_platform_data uart_pdata = {
@@ -296,6 +323,45 @@ static int __init pca100_otg_mode(char *options)
 }
 __setup("otg_mode=", pca100_otg_mode);
 
+/* framebuffer info */
+static struct imx_fb_videomode pca100_fb_modes[] = {
+	{
+		.mode = {
+			.name		= "EMERGING-ETV570G0DHU",
+			.refresh	= 60,
+			.xres		= 640,
+			.yres		= 480,
+			.pixclock	= 39722, /* in ps (25.175 MHz) */
+			.hsync_len	= 30,
+			.left_margin	= 114,
+			.right_margin	= 16,
+			.vsync_len	= 3,
+			.upper_margin	= 32,
+			.lower_margin	= 0,
+		},
+		/*
+		 * TFT
+		 * Pixel pol active high
+		 * HSYNC active low
+		 * VSYNC active low
+		 * use HSYNC for ACD count
+		 * line clock disable while idle
+		 * always enable line clock even if no data
+		 */
+		.pcr = 0xf0c08080,
+		.bpp = 16,
+	},
+};
+
+static struct imx_fb_platform_data pca100_fb_data = {
+	.mode = pca100_fb_modes,
+	.num_modes = ARRAY_SIZE(pca100_fb_modes),
+
+	.pwmr		= 0x00A903FF,
+	.lscr1		= 0x00120300,
+	.dmacr		= 0x00020010,
+};
+
 static void __init pca100_init(void)
 {
 	int ret;
@@ -371,6 +437,8 @@ static void __init pca100_init(void)
 		mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
 	}
 
+	mxc_register_device(&mxc_fb_device, &pca100_fb_data);
+
 	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
-- 
1.7.1



From l.fu at pengutronix.de  Thu Jun  3 09:55:46 2010
From: l.fu at pengutronix.de (Luotao Fu)
Date: Thu,  3 Jun 2010 15:55:46 +0200
Subject: few patches for PhyCARD-S board(pca100) with mx27 SOC
Message-ID: <1275573348-26564-1-git-send-email-l.fu@pengutronix.de>

Hi,

in following two patches for the phyCARD-S (pca100) board.

cheers
Luotao Fu



From l.fu at pengutronix.de  Thu Jun  3 09:55:48 2010
From: l.fu at pengutronix.de (Luotao Fu)
Date: Thu,  3 Jun 2010 15:55:48 +0200
Subject: [PATCH 2/2] ARM/MX2: clean up GPIO pin multiplexing for pca100 board
In-Reply-To: <1275573348-26564-1-git-send-email-l.fu@pengutronix.de>
References: <1275573348-26564-1-git-send-email-l.fu@pengutronix.de>
Message-ID: <1275573348-26564-3-git-send-email-l.fu@pengutronix.de>

cleaned up some duplicated mxc_gpio_mode calls and move the correpsonding
pin multiplexing either into the initial pin config table or ifdef blocks.

Signed-off-by: Luotao Fu <l.fu at pengutronix.de>
---
 arch/arm/mach-mx2/mach-pca100.c |   23 +++++++++++------------
 1 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c
index cf3d57b..dcd6555 100644
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-mx2/mach-pca100.c
@@ -55,6 +55,9 @@
 
 #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
 #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
+#define SPI1_SS0 (GPIO_PORTD + 28)
+#define SPI1_SS1 (GPIO_PORTD + 27)
+#define SD2_CD (GPIO_PORTC + 29)
 
 static int pca100_pins[] = {
 	/* UART1 */
@@ -69,6 +72,7 @@ static int pca100_pins[] = {
 	PB7_PF_SD2_D3,
 	PB8_PF_SD2_CMD,
 	PB9_PF_SD2_CLK,
+	SD2_CD | GPIO_GPIO | GPIO_IN,
 	/* FEC */
 	PD0_AIN_FEC_TXD0,
 	PD1_AIN_FEC_TXD1,
@@ -158,6 +162,10 @@ static int pca100_pins[] = {
 	PA31_PF_OE_ACD,
 	/* LVDS Transceiver */
 	LVDS_PWR_DWN_GPIO | GPIO_GPIO | GPIO_IN,
+	/* free GPIO */
+	GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */
+	GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */
+	GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */
 };
 
 static struct imxuart_platform_data uart_pdata = {
@@ -215,7 +223,7 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = {
 	},
 };
 
-static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
+static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
 
 static struct spi_imx_master pca100_spi_0_data = {
 	.chipselect	= pca100_spi_cs,
@@ -387,7 +395,6 @@ static void __init pca100_init(void)
 
 	mxc_register_device(&mxc_uart_device0, &uart_pdata);
 
-	mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
 	mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
 
 	mxc_register_device(&imx27_nand_device, &pca100_nand_board_info);
@@ -398,17 +405,9 @@ static void __init pca100_init(void)
 
 	mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
 
-	mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
-	mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
-
-	/* GPIO0_IRQ */
-	mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
-	/* GPIO1_IRQ */
-	mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
-	/* GPIO2_IRQ */
-	mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
-
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+	mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
+	mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
 	spi_register_board_info(pca100_spi_board_info,
 				ARRAY_SIZE(pca100_spi_board_info));
 	mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
-- 
1.7.1



From s.hauer at pengutronix.de  Thu Jun  3 09:57:06 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 3 Jun 2010 15:57:06 +0200
Subject: [V2 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <20100603123908.GB3527@matterhorn.lan>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100603123908.GB3527@matterhorn.lan>
Message-ID: <20100603135705.GA25357@pengutronix.de>

On Thu, Jun 03, 2010 at 03:39:08PM +0300, Amit Kucheria wrote:
> Two comments inline.
> 
> On 10 Jun 03, Jason Wang wrote:
> > 3-stack is a reference board from Freescale for their i.MX51 SoC.
> > 
> > Add board definition, Kconfig and Makefile to enable Freescale 3-stack
> > board.
> > 
> > Boot tested on a i.MX51 3-stack Rev2.0 board
> > 
> > Signed-off-by: Jason Wang <jason77.wang at gmail.com>
> > ---
> >  arch/arm/mach-mx5/Kconfig                       |    5 +
> >  arch/arm/mach-mx5/Makefile                      |    2 +-
> >  arch/arm/mach-mx5/board-mx51_3ds.c              |  263 +++++++++++++++++++++++
> >  arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   70 ++++++
> >  arch/arm/plat-mxc/include/mach/iomux-mx51.h     |   10 +-
> >  5 files changed, 345 insertions(+), 5 deletions(-)
> >  create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
> >  create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
> > 
> > diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
> > index 1576d51..6d45f44 100644
> > --- a/arch/arm/mach-mx5/Kconfig
> > +++ b/arch/arm/mach-mx5/Kconfig
> > @@ -15,4 +15,9 @@ config MACH_MX51_BABBAGE
> >  	  u-boot. This includes specific configurations for the board and its
> >  	  peripherals.
> >  
> > +config MACH_MX51_3DS
> > +	bool "Support MX51PDK (3DS)"
> > +	help
> > +	  Include support for MX51PDK (3DS) platform. This includes specific
> > +	  configurations for the board and its peripherals.
> >  endif
> > diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
> > index bf23f86..c757c59 100644
> > --- a/arch/arm/mach-mx5/Makefile
> > +++ b/arch/arm/mach-mx5/Makefile
> > @@ -6,4 +6,4 @@
> >  obj-y   := cpu.o mm.o clock-mx51.o devices.o
> >  
> >  obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
> > -
> > +obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
> > diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
> > new file mode 100644
> > index 0000000..5da90e9
> > --- /dev/null
> > +++ b/arch/arm/mach-mx5/board-mx51_3ds.c
> > @@ -0,0 +1,263 @@
> > +/*
> > + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
> > + * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
> > + *
> > + * The code contained herein is licensed under the GNU General Public
> > + * License. You may obtain a copy of the GNU General Public License
> > + * Version 2 or later at the following locations:
> > + *
> > + * http://www.opensource.org/licenses/gpl-license.html
> > + * http://www.gnu.org/copyleft/gpl.html
> > + */
> > +
> > +#include <linux/interrupt.h>
> > +#include <linux/irq.h>
> > +#include <linux/io.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/gpio.h>
> > +#include <linux/smsc911x.h>
> > +
> > +#include <asm/mach-types.h>
> > +#include <asm/mach/arch.h>
> > +#include <asm/mach/time.h>
> > +
> > +#include <mach/hardware.h>
> > +#include <mach/common.h>
> > +#include <mach/iomux-mx51.h>
> > +#include <mach/board-mx51_3ds.h>
> > +#include <mach/imx-uart.h>
> > +
> > +#include "devices.h"
> > +
> > +static void __iomem *brd_io;
> > +
> > +static void expio_ack_irq(u32 irq);
> > +
> > +static struct pad_desc mx51_3ds_pads[] = {
> > +	/* UART1 */
> > +	MX51_PAD_UART1_RXD__UART1_RXD,
> > +	MX51_PAD_UART1_TXD__UART1_TXD,
> > +	MX51_PAD_UART1_RTS__UART1_RTS,
> > +	MX51_PAD_UART1_CTS__UART1_CTS,
> > +
> > +	/* UART2 */
> > +	MX51_PAD_UART2_RXD__UART2_RXD,
> > +	MX51_PAD_UART2_TXD__UART2_TXD,
> > +	MX51_PAD_EIM_D25__UART2_CTS,
> > +	MX51_PAD_EIM_D26__UART2_RTS,
> > +
> > +	/* UART3 */
> > +	MX51_PAD_GPIO_1_22__UART3_RXD,
> > +	MX51_PAD_GPIO_1_23__UART3_TXD,
> > +	MX51_PAD_EIM_D24__UART3_CTS,
> > +	MX51_PAD_EIM_D27__UART3_RTS,
> > +
> > +	/* CPLD PARENT IRQ PIN */
> > +	MX51_PAD_GPIO_1_6__GPIO1_6,
> > +};
> > +
> > +
> > +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
> > +static struct resource smsc911x_resources[] = {
> > +	{
> > +		.start = LAN9217_BASE_ADDR,
> > +		.end = LAN9217_BASE_ADDR + 0x100 - 1,
> > +		.flags = IORESOURCE_MEM,
> > +	} , {
> > +		.start = EXPIO_INT_ENET,
> > +		.end = EXPIO_INT_ENET,
> > +		.flags = IORESOURCE_IRQ,
> > +	},
> > +};
> > +
> > +struct smsc911x_platform_config smsc911x_config = {
> > +	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
> > +	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
> > +};
> > +
> > +static struct platform_device smsc_lan9217_device = {
> > +	.name = "smsc911x",
> > +	.id = 0,
> > +	.dev = {
> > +		.platform_data = &smsc911x_config,
> > +	},
> > +	.num_resources = ARRAY_SIZE(smsc911x_resources),
> > +	.resource = smsc911x_resources,
> > +};
> 
> You forgot to move this platform_device to devices.c

No, devices.c is the place for the i.MX51 integrated peripherals, not
for externally conntected peripherals.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From rumjantsev at papillon.ru  Thu Jun  3 09:27:48 2010
From: rumjantsev at papillon.ru (237 Rumjantsev Egor (PROG))
Date: Thu, 03 Jun 2010 19:27:48 +0600
Subject: network device allocation oops
Message-ID: <4C07ADD4.3050706@papillon.ru>

Hello.

We develop custom board on Voipac PXA270 DIMM module. We connected 2 
devices on MMC/SDIO bus of PXA270 (Wifi modem WLRG-DP601 based on 
Marvell 8686 chipset and SD cards slot). Bus switches by analog mux and 
one of GPIOs who selects which of devices is working now.
I add to pxamci some code which forces MMC bus to rescan devices 
connected to bus. I use mmc_suspend_host and mmc_resume_host for it and 
change device select GPIO to proper state.
In many cases this works but some times libertas_sdio fails to load 
modem's firmware and after such error next try to add wifi modem oops.
Is there other way to force to refresh device list on MMC bus?


alloc_etherdev_mq(): size: 8704 count: 1
alloc_netdev_mq(): size: 8704 name: eth%d count: 1
alloc_netdev_mq(): alloc_size: 9631
alloc_netdev_mq(): queue: 1 size: 20
libertas: 00:01:36:1f:23:04, fw 8.73.7p3, cap 0x00000393
libertas: PREP_CMD: command 0x00a3 failed: 2
libertas: PREP_CMD: command 0x00a3 failed: 2
libertas: eth1: Marvell WLAN 802.11 adapter
eth1: no IPv6 routers present
mmc0: card 0001 removed
mmc0: host does not support reading read-only switch. assuming write-enable.
mmc0: new SD card at address b368
mmc0: card b368 removed
mmc0: new SDIO card at address 0001
libertas_sdio mmc0:0001:1: firmware: requesting sd8686_helper.bin
libertas_sdio mmc0:0001:1: firmware: requesting sd8686.bin
lbs_add_card(): size: 8704
alloc_etherdev_mq(): size: 8704 count: 1
alloc_netdev_mq(): size: 8704 name: eth%d count: 1
alloc_netdev_mq(): alloc_size: 9631
alloc_netdev_mq(): queue: 1 size: 20
libertas: 00:01:36:1f:23:04, fw 8.73.7p3, cap 0x00000393
libertas: PREP_CMD: command 0x00a3 failed: 2
libertas: PREP_CMD: command 0x00a3 failed: 2
libertas: eth1: Marvell WLAN 802.11 adapter
eth1: no IPv6 routers present
mmc0: card 0001 removed
mmc0: host does not support reading read-only switch. assuming write-enable.
mmc0: new SD card at address b368
mmcblk0: mmc0:b368 SD01G 958 MiB
  mmcblk0: p1
mmc0: card b368 removed
mmc0: new SDIO card at address 0001
libertas_sdio mmc0:0001:1: firmware: requesting sd8686_helper.bin
libertas_sdio mmc0:0001:1: firmware: requesting sd8686.bin
lbs_add_card(): size: 8704
alloc_etherdev_mq(): size: 8704 count: 1
alloc_netdev_mq(): size: 8704 name: eth%d count: 1
alloc_netdev_mq(): alloc_size: 9631
alloc_netdev_mq(): queue: 1 size: 20
libertas: command 0x0003 timed out
libertas: requeueing command 0x0003 due to timeout (#1)
libertas: command 0x0003 timed out
libertas: requeueing command 0x0003 due to timeout (#2)
libertas: command 0x0003 timed out
libertas: requeueing command 0x0003 due to timeout (#3)
libertas: command 0x0003 timed out
libertas: Excessive timeouts submitting command 0x0003
libertas: PREP_CMD: command 0x0003 failed: -110
libertas_sdio: probe of mmc0:0001:1 failed with error -110
mmc0: card 0001 removed
mmc0: host does not support reading read-only switch. assuming write-enable.
mmc0: new SD card at address b368
mmcblk0: mmc0:b368 SD01G 958 MiB
  mmcblk0: p1
mmc0: card b368 removed
mmc0: new SDIO card at address 0001
libertas_sdio mmc0:0001:1: firmware: requesting sd8686_helper.bin
libertas_sdio mmc0:0001:1: firmware: requesting sd8686.bin
lbs_add_card(): size: 8704
alloc_etherdev_mq(): size: 8704 count: 1
alloc_netdev_mq(): size: 8704 name: eth%d count: 1
alloc_netdev_mq(): alloc_size: 9631
kernel BUG at mm/slab.c:3000!
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = a0004000
[00000000] *pgd=00000000
Internal error: Oops: 817 [#1] PREEMPT
Modules linked in: vfat fat libertas_sdio libertas pxamci pxa_keypad 
pxa_qci ov5620 pxa_reg ac_adapter ucb1400_adc ipv6 power_button 
snd_pxa2xx_ac97 snd_ac97_codec ac97_bus snd_pxa2xx_pcm snd_pxa2xx_lib 
snd_pcm snd_timer snd snd_page_alloc ppp_async crc_ccitt i2c_pxa usbhid 
rtc_pxa [last unloaded: mmc_block]
CPU: 0    Not tainted  (2.6.28.10-vpac3-splash #138)
PC is at __bug+0x20/0x2c
LR is at vprintk+0x320/0x3a0
pc : [<a00325a0>]    lr : [<a00484e0>]    psr: 40000093
sp : c7885cec  ip : c7885c60  fp : c7885cf8
r10: c78004e0  r9 : c7884000  r8 : 00000004
r7 : c7802368  r6 : c7802720  r5 : c7802360  r4 : c7aca300
r3 : 00000000  r2 : c7884000  r1 : c7884000  r0 : 00000021
Flags: nZcv  IRQs off  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 0000397f  Table: a7a6c000  DAC: 00000017
Process kmmcd (pid: 12, stack limit = 0xc7884268)
Stack: (0xc7885cec to 0xc7886000)
5ce0:                            c7885d34 c7885cfc a009156c a003258c 
00000010
5d00: 000000d0 00000000 c7802370 0000259f c78004e0 a0000013 000080d0 
00002200
5d20: a023b414 a03786b4 c7885d54 c7885d38 a0091a68 a0091424 0000259f 
00000001
5d40: c4860000 00000001 c7885d84 c7885d58 a022f6e0 a00919e4 00000001 
00002200
5d60: 00000001 c4860000 c7885de4 c4860000 c7885de4 c49a1e04 c7885d9c 
c7885d88
5d80: a023b400 a022f66c 000003fe a03a0664 c7885dcc c7885da0 9f11c27c 
a023b3d0
5da0: a03a0664 c4860000 000003fe a03a0664 c4860000 c7885de4 c49a1e00 
0000fedc
5dc0: c7885e1c c7885dd0 9f136dc8 9f11c254 00000000 20000013 c5b9c000 
c7bef200
5de0: c7acabc0 00000000 00000000 0000000b 00000000 00000000 9f137f58 
c49a1e00
5e00: 9f1394d8 00000000 00000000 c49a1e6c c7885e3c c7885e20 a02145f8 
9f136234
5e20: 00000000 a018ecec c49a1e04 9f1394d8 c7885e5c c7885e40 a018eb8c 
a0214530
5e40: 00000000 a018ecec c49a1e04 c7885e70 c7885e6c c7885e60 a018ecfc 
a018eac0
5e60: c7885e94 c7885e70 a018e0d0 a018ecf8 c7865be8 c6ba3214 c49a1e04 
c49a1eb0
5e80: 00000001 c49a1e90 c7885eac c7885e98 a018ed84 a018e084 a03b649c 
c49a1e04
5ea0: c7885ec4 c7885eb0 a018def8 a018ed38 c49a1e04 c49a1e04 c7885f08 
c7885ec8
5ec0: a018cb10 a018ded4 c7bef604 00000000 c5b9c000 00000000 00000001 
c7bef600
5ee0: c49a1e04 c49a1e00 00000001 c5b9c000 00000000 00000001 c7bef600 
c7885f20
5f00: c7885f0c a02143e4 a018c7d4 00000000 00000000 c7885f5c c7885f24 
a0213db0
5f20: a02143bc 00000000 c7885f33 90300000 07000000 c7885f60 c5b9c000 
c5b9c180
5f40: c7884000 a021093c 00000000 00000000 c7885f7c c7885f60 a0210a7c 
a02138d8
5f60: 90ff8000 c5b9c184 c786f580 c5b9c180 c7885fa4 c7885f80 a00589b8 
a0210948
5f80: c786f588 c7884000 c786f580 c7885fa8 00000000 00000000 c7885fd8 
c7885fa8
5fa0: a00590d0 a00588e4 00000000 c7871980 a005cff0 c7885fb4 c7885fb4 
c7884000
5fc0: c786f580 a0058fcc 00000000 c7885ff4 c7885fdc a005cd5c a0058fd8 
00000000
5fe0: 00000000 00000000 00000000 c7885ff8 a004ab50 a005cd10 00000000 
00000000
Backtrace:
[<a0032580>] (__bug+0x0/0x2c) from [<a009156c>] 
(cache_alloc_refill+0x154/0x5c0)
[<a0091418>] (cache_alloc_refill+0x0/0x5c0) from [<a0091a68>] 
(__kmalloc+0x90/0xcc)
[<a00919d8>] (__kmalloc+0x0/0xcc) from [<a022f6e0>] 
(alloc_netdev_mq+0x80/0x198)
  r7:00000001 r6:c4860000 r5:00000001 r4:0000259f
[<a022f660>] (alloc_netdev_mq+0x0/0x198) from [<a023b400>] 
(alloc_etherdev_mq+0x3c/0x50)
[<a023b3c4>] (alloc_etherdev_mq+0x0/0x50) from [<9f11c27c>] 
(lbs_add_card+0x34/0x448 [libertas])
  r5:a03a0664 r4:000003fe
[<9f11c248>] (lbs_add_card+0x0/0x448 [libertas]) from [<9f136dc8>] 
(if_sdio_probe+0xba0/0xd90 [libertas_sdio])
[<9f136228>] (if_sdio_probe+0x0/0xd90 [libertas_sdio]) from [<a02145f8>] 
(sdio_bus_probe+0xd4/0xf0)
[<a0214524>] (sdio_bus_probe+0x0/0xf0) from [<a018eb8c>] 
(driver_probe_device+0xd8/0x1ac)
  r7:9f1394d8 r6:c49a1e04 r5:a018ecec r4:00000000
[<a018eab4>] (driver_probe_device+0x0/0x1ac) from [<a018ecfc>] 
(__device_attach+0x10/0x14)
  r7:c7885e70 r6:c49a1e04 r5:a018ecec r4:00000000
[<a018ecec>] (__device_attach+0x0/0x14) from [<a018e0d0>] 
(bus_for_each_drv+0x58/0x98)
[<a018e078>] (bus_for_each_drv+0x0/0x98) from [<a018ed84>] 
(device_attach+0x58/0x70)
  r7:c49a1e90 r6:00000001 r5:c49a1eb0 r4:c49a1e04
[<a018ed2c>] (device_attach+0x0/0x70) from [<a018def8>] 
(bus_attach_device+0x30/0x60)
  r5:c49a1e04 r4:a03b649c
[<a018dec8>] (bus_attach_device+0x0/0x60) from [<a018cb10>] 
(device_add+0x348/0x4e8)
  r5:c49a1e04 r4:c49a1e04
[<a018c7c8>] (device_add+0x0/0x4e8) from [<a02143e4>] 
(sdio_add_func+0x34/0x4c)
[<a02143b0>] (sdio_add_func+0x0/0x4c) from [<a0213db0>] 
(mmc_attach_sdio+0x4e4/0x5b4)
  r5:00000000 r4:00000000
[<a02138cc>] (mmc_attach_sdio+0x0/0x5b4) from [<a0210a7c>] 
(mmc_rescan+0x140/0x274)
[<a021093c>] (mmc_rescan+0x0/0x274) from [<a00589b8>] 
(run_workqueue+0xe0/0x1a4)
  r6:c5b9c180 r5:c786f580 r4:c5b9c184
[<a00588d8>] (run_workqueue+0x0/0x1a4) from [<a00590d0>] 
(worker_thread+0x104/0x118)
[<a0058fcc>] (worker_thread+0x0/0x118) from [<a005cd5c>] (kthread+0x58/0x90)
  r7:00000000 r6:a0058fcc r5:c786f580 r4:c7884000
[<a005cd04>] (kthread+0x0/0x90) from [<a004ab50>] (do_exit+0x0/0x798)
  r6:00000000 r5:00000000 r4:00000000
Code: e1a01000 e59f000c eb0a89ae e3a03000 (e5833000)
---[ end trace 7cccef3b877a8342 ]---
note: kmmcd[12] exited with preempt_count 1

Best Regards
-- 
Rumjantsev Egor


From yegor_sub1 at visionsystems.de  Thu Jun  3 10:02:59 2010
From: yegor_sub1 at visionsystems.de (Yegor Yefremov)
Date: Thu, 03 Jun 2010 16:02:59 +0200
Subject: AC97 audio broken on SAM9263EK?
In-Reply-To: <4C07A422.5070505@atmel.com>
References: <4B85789D.6000704@billgatliff.com>
	<4B864C66.6060209@atmel.com>	<4B867108.2050806@billgatliff.com>
	<4B86AA29.8010806@atmel.com>	<4B89E1BB.6090504@billgatliff.com>
	<4B8B9849.5040203@atmel.com> <4B96571A.3040403@visionsystems.de>
	<4B96668E.6090805@atmel.com> <4B975C9A.3020106@visionsystems.de>
	<4B97602C.6070608@atmel.com> <4B97BD8C.3030502@visionsystems.de>
	<4B97C086.2080404@atmel.com> <4C050D97.4000404@visionsystems.de>
	<4C07A422.5070505@atmel.com>
Message-ID: <4C07B613.2040201@visionsystems.de>

Hi Sedji,

> It is an error indeed, it should be a debug message.

here is a patch:

atmel: set "channel A event" output to debug

Signed-off-by: Yegor Yefremov <yegorslists at googlemail.com>

Index: b/sound/atmel/ac97c.c
===================================================================
--- a/sound/atmel/ac97c.c	2010-06-01 15:28:23.000000000 +0200
+++ b/sound/atmel/ac97c.c	2010-06-03 15:20:43.000000000 +0200
@@ -657,7 +657,7 @@
 	if (sr & AC97C_SR_CAEVT) {
 		struct snd_pcm_runtime *runtime;
 		int offset, next_period, block_size;
-		dev_info(&chip->pdev->dev, "channel A event%s%s%s%s%s%s\n",
+		dev_dbg(&chip->pdev->dev, "channel A event%s%s%s%s%s%s\n",
 				casr & AC97C_CSR_OVRUN   ? " OVRUN"   : "",
 				casr & AC97C_CSR_RXRDY   ? " RXRDY"   : "",
 				casr & AC97C_CSR_UNRUN   ? " UNRUN"   : "",



From amit.kucheria at canonical.com  Thu Jun  3 10:35:34 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Thu, 3 Jun 2010 17:35:34 +0300
Subject: [V2 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <20100603135705.GA25357@pengutronix.de>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100603123908.GB3527@matterhorn.lan>
	<20100603135705.GA25357@pengutronix.de>
Message-ID: <20100603143534.GC3527@matterhorn.lan>

On 10 Jun 03, Sascha Hauer wrote:
> On Thu, Jun 03, 2010 at 03:39:08PM +0300, Amit Kucheria wrote:
> > Two comments inline.
> > 
> > > +static struct platform_device smsc_lan9217_device = {
> > > +	.name = "smsc911x",
> > > +	.id = 0,
> > > +	.dev = {
> > > +		.platform_data = &smsc911x_config,
> > > +	},
> > > +	.num_resources = ARRAY_SIZE(smsc911x_resources),
> > > +	.resource = smsc911x_resources,
> > > +};
> > 
> > You forgot to move this platform_device to devices.c
> 
> No, devices.c is the place for the i.MX51 integrated peripherals, not
> for externally conntected peripherals.

OK. Didn't know this was an externally connected peripheral. Which, BTW, is
also why I had suggested that the smsc and the debug board support were added as
separate patches. But it is a preference thing.

-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------


From jason77.wang at gmail.com  Thu Jun  3 10:36:17 2010
From: jason77.wang at gmail.com (jason)
Date: Thu, 03 Jun 2010 22:36:17 +0800
Subject: [V2 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <20100603135705.GA25357@pengutronix.de>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100603123908.GB3527@matterhorn.lan>
	<20100603135705.GA25357@pengutronix.de>
Message-ID: <4C07BDE1.6020404@gmail.com>

Sascha Hauer wrote:
> On Thu, Jun 03, 2010 at 03:39:08PM +0300, Amit Kucheria wrote:
>   
>> Two comments inline.
>>
>> On 10 Jun 03, Jason Wang wrote:
>>     
>>> 3-stack is a reference board from Freescale for their i.MX51 SoC.
>>>
>>> Add board definition, Kconfig and Makefile to enable Freescale 3-stack
>>> board.
>>>
>>> Boot tested on a i.MX51 3-stack Rev2.0 board
>>>
>>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>>> ---
>>>  arch/arm/mach-mx5/Kconfig                       |    5 +
>>>  arch/arm/mach-mx5/Makefile                      |    2 +-
>>>  arch/arm/mach-mx5/board-mx51_3ds.c              |  263 +++++++++++++++++++++++
>>>  arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   70 ++++++
>>>  arch/arm/plat-mxc/include/mach/iomux-mx51.h     |   10 +-
>>>  5 files changed, 345 insertions(+), 5 deletions(-)
>>>  create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
>>>  create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
>>>
>>> diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
>>> index 1576d51..6d45f44 100644
>>> --- a/arch/arm/mach-mx5/Kconfig
>>> +++ b/arch/arm/mach-mx5/Kconfig
>>> @@ -15,4 +15,9 @@ config MACH_MX51_BABBAGE
>>>  	  u-boot. This includes specific configurations for the board and its
>>>  	  peripherals.
>>>  
>>> +config MACH_MX51_3DS
>>> +	bool "Support MX51PDK (3DS)"
>>> +	help
>>> +	  Include support for MX51PDK (3DS) platform. This includes specific
>>> +	  configurations for the board and its peripherals.
>>>  endif
>>> diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
>>> index bf23f86..c757c59 100644
>>> --- a/arch/arm/mach-mx5/Makefile
>>> +++ b/arch/arm/mach-mx5/Makefile
>>> @@ -6,4 +6,4 @@
>>>  obj-y   := cpu.o mm.o clock-mx51.o devices.o
>>>  
>>>  obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
>>> -
>>> +obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
>>> diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
>>> new file mode 100644
>>> index 0000000..5da90e9
>>> --- /dev/null
>>> +++ b/arch/arm/mach-mx5/board-mx51_3ds.c
>>> @@ -0,0 +1,263 @@
>>> +/*
>>> + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
>>> + * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
>>> + *
>>> + * The code contained herein is licensed under the GNU General Public
>>> + * License. You may obtain a copy of the GNU General Public License
>>> + * Version 2 or later at the following locations:
>>> + *
>>> + * http://www.opensource.org/licenses/gpl-license.html
>>> + * http://www.gnu.org/copyleft/gpl.html
>>> + */
>>> +
>>> +#include <linux/interrupt.h>
>>> +#include <linux/irq.h>
>>> +#include <linux/io.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/gpio.h>
>>> +#include <linux/smsc911x.h>
>>>
>>>       
<snip>
>>> +static struct platform_device smsc_lan9217_device = {
>>> +	.name = "smsc911x",
>>> +	.id = 0,
>>> +	.dev = {
>>> +		.platform_data = &smsc911x_config,
>>> +	},
>>> +	.num_resources = ARRAY_SIZE(smsc911x_resources),
>>> +	.resource = smsc911x_resources,
>>> +};
>>>       
>> You forgot to move this platform_device to devices.c
>>     
>
> No, devices.c is the place for the i.MX51 integrated peripherals, not
> for externally conntected peripherals.
>
> Sascha
>
>   
Yes, this device is board specific, not the one of i.MX51 SOC.
I think it's better to keep it in the board specific file.

Thanks,
Jason.




From jason77.wang at gmail.com  Thu Jun  3 10:39:42 2010
From: jason77.wang at gmail.com (jason)
Date: Thu, 03 Jun 2010 22:39:42 +0800
Subject: [V2 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <20100603123908.GB3527@matterhorn.lan>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100603123908.GB3527@matterhorn.lan>
Message-ID: <4C07BEAE.7020205@gmail.com>

Amit Kucheria wrote:
> Two comments inline.
>
> On 10 Jun 03, Jason Wang wrote:
>   
>> 3-stack is a reference board from Freescale for their i.MX51 SoC.
>>
>> Add board definition, Kconfig and Makefile to enable Freescale 3-stack
>> board.
>>
>> Boot tested on a i.MX51 3-stack Rev2.0 board
>>
>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>> ---
>>  arch/arm/mach-mx5/Kconfig                       |    5 +
>>  arch/arm/mach-mx5/Makefile                      |    2 +-
>>  arch/arm/mach-mx5/board-mx51_3ds.c              |  263 +++++++++++++++++++++++
>>  arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   70 ++++++
>>  arch/arm/plat-mxc/include/mach/iomux-mx51.h     |   10 +-
>>  5 files changed, 345 insertions(+), 5 deletions(-)
>>  create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
>>  create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
>>
>>     
>>     
<snip>
>> diff --git a/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
>> new file mode 100644
>> index 0000000..035f7bc
>> --- /dev/null
>> +++ b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
>> @@ -0,0 +1,70 @@
>> +/*
>> + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
>> + *
>> + *
>> + * The code contained herein is licensed under the GNU General Public
>> + * License. You may obtain a copy of the GNU General Public License
>> + * Version 2 or later at the following locations:
>> + *
>> + * http://www.opensource.org/licenses/gpl-license.html
>> + * http://www.gnu.org/copyleft/gpl.html
>> + */
>> +
>> +#ifndef __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
>> +#define __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
>> +
>> +/*
>> + * @file plat-mxc/include/mach/board-mx51_3ds.h
>> + *
>> + * @brief This file contains all the board level configuration options.
>>     
>
> Remove this @file, @brief.
>
>   
OK, i will fix it in V3.

Thanks,
Jason.
>> + * It currently hold the options defined for MX51 3Stack Platform.
>> + *
>> + */
>> +
>> +#define DEBUG_BOARD_BASE_ADDRESS MX51_CS5_BASE_ADDR
>>     
>
<snip>




From felipe.contreras at gmail.com  Thu Jun  3 10:59:10 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Thu, 3 Jun 2010 17:59:10 +0300
Subject: [PATCH v3 00/14] omap: mailbox: bunch of cleanups
In-Reply-To: <20100603114726.GC7127@n2100.arm.linux.org.uk>
References: <1274548465-20208-1-git-send-email-felipe.contreras@gmail.com>
	<20100603.094022.200375421.Hiroshi.DOYU@nokia.com>
	<20100603114726.GC7127@n2100.arm.linux.org.uk>
Message-ID: <AANLkTinBMdcxzF_pZuiFHc1Eox_bYtD8PXG1OuKo0XWu@mail.gmail.com>

On Thu, Jun 3, 2010 at 2:47 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Thu, Jun 03, 2010 at 09:40:22AM +0300, Hiroshi DOYU wrote:
>> > Felipe Contreras (14):
>> > ? omap: mailbox: trivial whitespace cleanups
>> > ? omap: mailbox: trivial cleanups
>
> I think folk need to read this:
>
> ? ? ? ?http://lkml.org/lkml/2010/6/2/472
>
> and consider what it means for the future, and what can be done to reduce
> the amount of "churn".

If I have to decipher that rant, my best guess is that he is
complaining about the amount of code. If that's the case, this patch
series is only doing good:
6 files changed, 168 insertions(+), 230 deletions(-)

Another part of the rant is the fact that Linus cannot follow the huge
amount of changes. I think "trivial whitespace cleanups" pretty much
says: don't look at me if you want to be productive, while "trivial
cleanups" says, look at me if you feel like looking at easy changes.
If I were to squash these two, I think the patch series would become
harder to follow.

Something that helps in other projects, like git, is that merges are
clearly identified.

Merge branch 'linux-arm'
 Merge branch 'linux-omap'
  Merge branch 'linux-omap-mbox'
   Merge branch 'fc-cleanups'
   Merge branch 'ob-kfifo'

Then it's a bit clearer what each patch series is doing in the mailbox
tree without looking at individual patches.

Cheers.

-- 
Felipe Contreras


From catalin.marinas at arm.com  Thu Jun  3 12:15:09 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 03 Jun 2010 17:15:09 +0100
Subject: PB1176 broken in 2.6.35-rc1, bisected
In-Reply-To: <AANLkTimJkaadEM1xvG30WVvEjJPZQXHwx216SeqWFKNp@mail.gmail.com>
References: <AANLkTikoCy2FH_5ICh-iiI_wzGj6D6oszyM-zCXkNC_4@mail.gmail.com>
	<1275518783.27834.2.camel@e102109-lin.cambridge.arm.com>
	<AANLkTimJkaadEM1xvG30WVvEjJPZQXHwx216SeqWFKNp@mail.gmail.com>
Message-ID: <1275581709.8775.14.camel@e102109-lin.cambridge.arm.com>

On Thu, 2010-06-03 at 09:48 +0100, Linus Walleij wrote:
> 2010/6/3 Catalin Marinas <catalin.marinas at arm.com>:
> > On Wed, 2010-06-02 at 23:33 +0100, Linus Walleij wrote:
> >> my PB1176 doesn't boot properly in 2.6.35-rc1, it goes to this point
> >> and hangs:
> >>
> >> (...)
> >> Switching to clocksource timer3
> >> NET: Registered protocol family 2
> >> IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
> >> TCP established hash table entries: 4096 (order: 3, 32768 bytes)
> >> TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
> >> TCP: Hash tables configured (established 4096 bind 4096)
> >> TCP reno registered
> >> UDP hash table entries: 256 (order: 0, 4096 bytes)
> >> UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
> >> NET: Registered protocol family 1
> >> RPC: Registered udp transport module.
> >> RPC: Registered tcp transport module.
> >> RPC: Registered tcp NFSv4.1 backchannel transport module.
> >
> > Have you tried disabling CONFIG_CACHE_L2X0?
> 
> Hey it works! :-)
> 
> I suppose your latest patches will hopefully  get the defconfig with
> l2x0 working again in -rc2 if they're merged?

I think there is an L2 erratum (and trying to get the right workaround).
It may be triggered by commit e7c5650f6.

I'll get back on the list with a patch.

-- 
Catalin



From nico at fluxnic.net  Thu Jun  3 12:30:05 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 03 Jun 2010 12:30:05 -0400 (EDT)
Subject: [PATCH 3/3] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <AANLkTinQ_DdwRrjwtzrTXqtoeQxh87qAjSXDd6O4cPba@mail.gmail.com>
References: <1275404968-12258-1-git-send-email-saeed@marvell.com>
	<1275404968-12258-2-git-send-email-saeed@marvell.com>
	<1275404968-12258-3-git-send-email-saeed@marvell.com>
	<alpine.LFD.2.00.1006011447410.24526@xanadu.home>
	<AANLkTinQ_DdwRrjwtzrTXqtoeQxh87qAjSXDd6O4cPba@mail.gmail.com>
Message-ID: <alpine.LFD.2.00.1006031224180.24526@xanadu.home>

On Thu, 3 Jun 2010, saeed bishara wrote:

> On Tue, Jun 1, 2010 at 10:55 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> > On Tue, 1 Jun 2010, Saeed Bishara wrote:
> >> +void __init kirkwood_pcie_init(int init_port0, int init_port1)
> >
> > And instead of having (int init_port0, int init_port1), this should be
> > (int port) which is much less error prone as demonstrated by your own
> > kirkwood_pcie_init(0, 1) usage. ?Those machines with both PCIe ports
> > would simply have to call this twice.
> nico, this is different from other controller,  we can't have multiple
> registrations as the pci_commont_init() can't be called multiple
> times.

OK. In that case that would be better to have only one argument and 
define some flag bits for it:

#define KW_PCIE0	(1 << 0)
#define KW_PCIE1	(1 << 1)

void __init kirkwood_pcie_init(int portmask)

And usage would be:

	kirkwood_pcie_init(KW_PCIE0 | KW_PCIE1);

This is much easier to review, and less prone to errors.


Nicolas

From tony at atomide.com  Thu Jun  3 12:15:53 2010
From: tony at atomide.com (Tony Lindgren)
Date: Thu, 3 Jun 2010 19:15:53 +0300
Subject: [PATCH v3 00/14] omap: mailbox: bunch of cleanups
In-Reply-To: <AANLkTinBMdcxzF_pZuiFHc1Eox_bYtD8PXG1OuKo0XWu@mail.gmail.com>
References: <1274548465-20208-1-git-send-email-felipe.contreras@gmail.com>
	<20100603.094022.200375421.Hiroshi.DOYU@nokia.com>
	<20100603114726.GC7127@n2100.arm.linux.org.uk>
	<AANLkTinBMdcxzF_pZuiFHc1Eox_bYtD8PXG1OuKo0XWu@mail.gmail.com>
Message-ID: <20100603161553.GL30622@atomide.com>

* Felipe Contreras <felipe.contreras at gmail.com> [100603 17:53]:
> On Thu, Jun 3, 2010 at 2:47 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> > On Thu, Jun 03, 2010 at 09:40:22AM +0300, Hiroshi DOYU wrote:
> >> > Felipe Contreras (14):
> >> > ? omap: mailbox: trivial whitespace cleanups
> >> > ? omap: mailbox: trivial cleanups
> >
> > I think folk need to read this:
> >
> > ? ? ? ?http://lkml.org/lkml/2010/6/2/472
> >
> > and consider what it means for the future, and what can be done to reduce
> > the amount of "churn".
> 
> If I have to decipher that rant, my best guess is that he is
> complaining about the amount of code. If that's the case, this patch
> series is only doing good:
> 6 files changed, 168 insertions(+), 230 deletions(-)
> 
> Another part of the rant is the fact that Linus cannot follow the huge
> amount of changes. I think "trivial whitespace cleanups" pretty much
> says: don't look at me if you want to be productive, while "trivial
> cleanups" says, look at me if you feel like looking at easy changes.
> If I were to squash these two, I think the patch series would become
> harder to follow.
> 
> Something that helps in other projects, like git, is that merges are
> clearly identified.
> 
> Merge branch 'linux-arm'
>  Merge branch 'linux-omap'
>   Merge branch 'linux-omap-mbox'
>    Merge branch 'fc-cleanups'
>    Merge branch 'ob-kfifo'
> 
> Then it's a bit clearer what each patch series is doing in the mailbox
> tree without looking at individual patches.

Also we need to make sure all the code we merge is really tested
well before the merge window. Too much of the code needs to be
fixed after the merge window. For the upcoming merge window, we
will only merge things that have been sitting in the for-next
for days before the merge window opens.

Tony


From randy.dunlap at oracle.com  Thu Jun  3 12:32:42 2010
From: randy.dunlap at oracle.com (Randy Dunlap)
Date: Thu, 03 Jun 2010 09:32:42 -0700
Subject: [PATCH 1/2] menuconfig: fix to center checklist correctly in
	a corner case
In-Reply-To: <4C0758B7.5070907@cn.fujitsu.com>
References: <4C0758B7.5070907@cn.fujitsu.com>
Message-ID: <4C07D92A.4000806@oracle.com>

On 06/03/10 00:24, Li Zefan wrote:
> Run:
> 	make ARCH=arm menuconfig
> 
> And then select "System Type" -> "ARM system type". The kconfig
> "choice" menu at this point looks empty.
> 
> It's because config ARCH_S3C2410 has a long prompt:
> 
> config ARCH_S3C2410
>         bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
> 	...
> 
> menuconfig centers the checklist according to this prompt without
> considering the width of the list, and then things get wrong.
> 
> Reported-by: Nobin Mathew <nobin.mathew at gmail.com>
> Signed-off-by: Li Zefan <lizf at cn.fujitsu.com>
> ---
> 
> Please queue these 2 patches for 2.6.35.

Tested-by: Randy Dunlap <randy.dunlap at oracle.com>

Thanks.

> ---
>  scripts/kconfig/lxdialog/checklist.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/scripts/kconfig/lxdialog/checklist.c b/scripts/kconfig/lxdialog/checklist.c
> index bcc6f19..c92a05a 100644
> --- a/scripts/kconfig/lxdialog/checklist.c
> +++ b/scripts/kconfig/lxdialog/checklist.c
> @@ -175,6 +175,7 @@ do_resize:
>  	check_x = 0;
>  	item_foreach()
>  		check_x = MAX(check_x, strlen(item_str()) + 4);
> +	check_x = MIN(check_x, list_width);
>  
>  	check_x = (list_width - check_x) / 2;
>  	item_x = check_x + 4;


-- 
~Randy
*** Remember to use Documentation/SubmitChecklist when testing your code ***


From randy.dunlap at oracle.com  Thu Jun  3 12:32:50 2010
From: randy.dunlap at oracle.com (Randy Dunlap)
Date: Thu, 03 Jun 2010 09:32:50 -0700
Subject: [PATCH 2/2] menuconfig: truncate list items
In-Reply-To: <4C0758C9.7080108@cn.fujitsu.com>
References: <4C0758B7.5070907@cn.fujitsu.com> <4C0758C9.7080108@cn.fujitsu.com>
Message-ID: <4C07D932.4040404@oracle.com>

On 06/03/10 00:24, Li Zefan wrote:
> Truncate list items to fit in a single line, otherwise those items
> which have long prompts will cover some other items.
> 
> This follows the behavior of menubox.
> 
> Signed-off-by: Li Zefan <lizf at cn.fujitsu.com>

Thanks :)

Tested-by: Randy Dunlap <randy.dunlap at oracle.com>

Ben, the Samsung S3C24* prompt still gets truncated with this patch (when using
an 80-column wide xterm).  If you care about seeing all of the models,
you might want to shorten the prompt.


> ---
>  scripts/kconfig/lxdialog/checklist.c |    9 +++++++--
>  1 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/scripts/kconfig/lxdialog/checklist.c b/scripts/kconfig/lxdialog/checklist.c
> index c92a05a..a2eb80f 100644
> --- a/scripts/kconfig/lxdialog/checklist.c
> +++ b/scripts/kconfig/lxdialog/checklist.c
> @@ -31,6 +31,10 @@ static int list_width, check_x, item_x;
>  static void print_item(WINDOW * win, int choice, int selected)
>  {
>  	int i;
> +	char *list_item = malloc(list_width + 1);
> +
> +	strncpy(list_item, item_str(), list_width - item_x);
> +	list_item[list_width - item_x] = '\0';
>  
>  	/* Clear 'residue' of last item */
>  	wattrset(win, dlg.menubox.atr);
> @@ -45,13 +49,14 @@ static void print_item(WINDOW * win, int choice, int selected)
>  		wprintw(win, "(%c)", item_is_tag('X') ? 'X' : ' ');
>  
>  	wattrset(win, selected ? dlg.tag_selected.atr : dlg.tag.atr);
> -	mvwaddch(win, choice, item_x, item_str()[0]);
> +	mvwaddch(win, choice, item_x, list_item[0]);
>  	wattrset(win, selected ? dlg.item_selected.atr : dlg.item.atr);
> -	waddstr(win, (char *)item_str() + 1);
> +	waddstr(win, list_item + 1);
>  	if (selected) {
>  		wmove(win, choice, check_x + 1);
>  		wrefresh(win);
>  	}
> +	free(list_item);
>  }
>  
>  /*


-- 
~Randy
*** Remember to use Documentation/SubmitChecklist when testing your code ***


From broonie at opensource.wolfsonmicro.com  Thu Jun  3 12:52:53 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 3 Jun 2010 17:52:53 +0100
Subject: [alsa-devel] [PATCH v2 1/4] imx-ssi.c: add new choices to
	platform configuration
In-Reply-To: <20100603081926.GT26820@pengutronix.de>
References: <1274950737-26498-1-git-send-email-eric@eukrea.com>
	<20100601180527.GC10031@sirena.org.uk>
	<20100603081926.GT26820@pengutronix.de>
Message-ID: <20100603165252.GD2762@rakim.wolfsonmicro.main>

On Thu, Jun 03, 2010 at 10:19:26AM +0200, Sascha Hauer wrote:
> On Tue, Jun 01, 2010 at 07:05:28PM +0100, Mark Brown wrote:

> > Sascha, any comments on the first couple of patches here?

> Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

Applied both, though I had to hand edit the Makefile and Kconfig for the
machine driver - not sure what it was generated against but it didn't
seem terribly mainline.


From g.liakhovetski at gmx.de  Thu Jun  3 14:59:09 2010
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Thu, 3 Jun 2010 20:59:09 +0200 (CEST)
Subject: [PATCH] mioa701: fix camera regression
In-Reply-To: <1275514190-32006-1-git-send-email-robert.jarzmik@free.fr>
References: <1275514190-32006-1-git-send-email-robert.jarzmik@free.fr>
Message-ID: <Pine.LNX.4.64.1006032058380.19573@axis700.grange>

On Wed, 2 Jun 2010, Robert Jarzmik wrote:

> Since commit a48c24a696f0d93c49f913b7818e9819612b1f4e, the
> camera is not working anymore.
> 
> After the v4l2 migration, the mt9m111 camera board
> information was not passed to the i2c layer anymore, but
> stored for future use of v4l2 (through soc_camera).
> 
> Because mioa701_i2c_devices[] was tagged as "__initdata",
> and because after the v4l2 migration, the new structure
> "iclink" references it, the mt9m111 driver is not probed
> anymore, as part of "iclink" is not valid (discarded after
> kernel init).
> 
> Although there is not compilation error, nor runtime oops,
> this patch restores a working camera on the mioa701 board.
> 
> Signed-off-by: Robert Jarzmik <robert.jarzmik at free.fr>

Acked-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>

> 
> --
> Eric, could you schedule that into your fix branch please ?
> ---
>  arch/arm/mach-pxa/mioa701.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
> index 7a50ed8..9836921 100644
> --- a/arch/arm/mach-pxa/mioa701.c
> +++ b/arch/arm/mach-pxa/mioa701.c
> @@ -696,7 +696,7 @@ static struct i2c_board_info __initdata mioa701_pi2c_devices[] = {
>  };
>  
>  /* Board I2C devices. */
> -static struct i2c_board_info __initdata mioa701_i2c_devices[] = {
> +static struct i2c_board_info mioa701_i2c_devices[] = {
>  	{
>  		I2C_BOARD_INFO("mt9m111", 0x5d),
>  	},
> -- 
> 1.7.0.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From linux at arm.linux.org.uk  Thu Jun  3 15:24:59 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 3 Jun 2010 20:24:59 +0100
Subject: Heads up: Linus plans to kill ARM defconfigs
Message-ID: <20100603192459.GA9169@n2100.arm.linux.org.uk>

The subject says everything you need to know.  Randy provided this
link earlier:

  http://lkml.org/lkml/2010/6/2/472

Linus doesn't appear to be listening to reason, so I see now this as
a fait accompli.  It'll apparantly happen at the next merge window.

So, don't send anything which contains a defconfig file or updates to
it.  It's pointless.


From linux at arm.linux.org.uk  Thu Jun  3 15:52:39 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 3 Jun 2010 20:52:39 +0100
Subject: Please pull mxc patches for -rc
In-Reply-To: <20100603083522.GX26820@pengutronix.de>
References: <20100603083522.GX26820@pengutronix.de>
Message-ID: <20100603195239.GB9169@n2100.arm.linux.org.uk>

On Thu, Jun 03, 2010 at 10:35:22AM +0200, Sascha Hauer wrote:
> Hi Russell,
> 
> please pull the following for -rc.

I won't be pulling this for a while; I've no idea at the moment where
ARM as a community goes from where we find ourselves as of this morning
given Linus' complaints about our "pointless churn".

Certainly the defconfigs seem out of the equation.

I'm also off for an extended weekend.  So it's nice timing on major
issues yet again.


From marek.vasut at gmail.com  Thu Jun  3 15:55:19 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 3 Jun 2010 21:55:19 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100603192459.GA9169@n2100.arm.linux.org.uk>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
Message-ID: <201006032155.19349.marek.vasut@gmail.com>

Dne ?t 3. ?ervna 2010 21:24:59 Russell King - ARM Linux napsal(a):
> The subject says everything you need to know.  Randy provided this
> link earlier:
> 
>   http://lkml.org/lkml/2010/6/2/472
> 
> Linus doesn't appear to be listening to reason, so I see now this as
> a fait accompli.  It'll apparantly happen at the next merge window.

The defconfigs age ... there's no point keeping them. They'll be useless crap 
unless someone updates them often anyway.

Maybe adding a Kconfig option that's select all the default stuff the platform 
needs would be a way to go ? (that was already proposed there)

> 
> So, don't send anything which contains a defconfig file or updates to
> it.  It's pointless.
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From nico at fluxnic.net  Thu Jun  3 15:59:03 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 03 Jun 2010 15:59:03 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100603192459.GA9169@n2100.arm.linux.org.uk>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.00.1006031549400.24526@xanadu.home>

On Thu, 3 Jun 2010, Russell King - ARM Linux wrote:

> The subject says everything you need to know.  Randy provided this
> link earlier:
> 
>   http://lkml.org/lkml/2010/6/2/472

Leaving the drama aside...

I agree that there is indeed a growing problem with the growing number 
of ever growing defconfigs.

And the problem is made even worse by the diversity, and shall we say 
"success" of the ARM architecture.

The average defconfig file for a new target is going to be _larger_ than 
the size of the actual source code for that target if the trend 
continues.

Let's acknowledge the problem and try to come up with a solution.


Nicolas


From linux at arm.linux.org.uk  Thu Jun  3 16:01:09 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 3 Jun 2010 21:01:09 +0100
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006032155.19349.marek.vasut@gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<201006032155.19349.marek.vasut@gmail.com>
Message-ID: <20100603200109.GC9169@n2100.arm.linux.org.uk>

On Thu, Jun 03, 2010 at 09:55:19PM +0200, Marek Vasut wrote:
> Dne ?t 3. ?ervna 2010 21:24:59 Russell King - ARM Linux napsal(a):
> > The subject says everything you need to know.  Randy provided this
> > link earlier:
> > 
> >   http://lkml.org/lkml/2010/6/2/472
> > 
> > Linus doesn't appear to be listening to reason, so I see now this as
> > a fait accompli.  It'll apparantly happen at the next merge window.
> 
> The defconfigs age ... there's no point keeping them. They'll be useless crap 
> unless someone updates them often anyway.
> 
> Maybe adding a Kconfig option that's select all the default stuff the platform 
> needs would be a way to go ? (that was already proposed there)

The problem comes (as Daniel pointed out _after_ my suggested solution to
this problem) is if you want to turn off something that's 'selected' in
this way.

Anyway, let's not start a new lengthy thread on the subject here; it won't
have much effect being only on this list.


From linux at arm.linux.org.uk  Thu Jun  3 16:03:57 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 3 Jun 2010 21:03:57 +0100
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <alpine.LFD.2.00.1006031549400.24526@xanadu.home>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006031549400.24526@xanadu.home>
Message-ID: <20100603200357.GD9169@n2100.arm.linux.org.uk>

On Thu, Jun 03, 2010 at 03:59:03PM -0400, Nicolas Pitre wrote:
> On Thu, 3 Jun 2010, Russell King - ARM Linux wrote:
> 
> > The subject says everything you need to know.  Randy provided this
> > link earlier:
> > 
> >   http://lkml.org/lkml/2010/6/2/472
> 
> Leaving the drama aside...

Err, what drama?  Don't you think it would be absolutely stupid of me
_not_ to highlight what's going to happen?  I'm sure there would also
be complaints if I didn't bring people's attention to it.

Damned if I do, and damned if I don't.  So I can't win.

> Let's acknowledge the problem and try to come up with a solution.

I agree with you, but it has already proven pointless to discuss.


From marek.vasut at gmail.com  Thu Jun  3 16:27:56 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 3 Jun 2010 22:27:56 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100603200109.GC9169@n2100.arm.linux.org.uk>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<201006032155.19349.marek.vasut@gmail.com>
	<20100603200109.GC9169@n2100.arm.linux.org.uk>
Message-ID: <201006032227.56429.marek.vasut@gmail.com>

Dne ?t 3. ?ervna 2010 22:01:09 Russell King - ARM Linux napsal(a):
> On Thu, Jun 03, 2010 at 09:55:19PM +0200, Marek Vasut wrote:
> > Dne ?t 3. ?ervna 2010 21:24:59 Russell King - ARM Linux napsal(a):
> > > The subject says everything you need to know.  Randy provided this
> > > 
> > > link earlier:
> > >   http://lkml.org/lkml/2010/6/2/472
> > > 
> > > Linus doesn't appear to be listening to reason, so I see now this as
> > > a fait accompli.  It'll apparantly happen at the next merge window.
> > 
> > The defconfigs age ... there's no point keeping them. They'll be useless
> > crap unless someone updates them often anyway.
> > 
> > Maybe adding a Kconfig option that's select all the default stuff the
> > platform needs would be a way to go ? (that was already proposed there)
> 
> The problem comes (as Daniel pointed out _after_ my suggested solution to
> this problem) is if you want to turn off something that's 'selected' in
> this way.

Yup, I got the point.
> 
> Anyway, let's not start a new lengthy thread on the subject here; it won't
> have much effect being only on this list.

Just as Nicolas pointed out, we need a solution. I guess lenghty thread is 
unavoidable, sorry. If possible, could you CC interested parties ?

btw. Maybe updating the machine registry so it allows pasting/attaching a 
defconfig with information about kernel version the defconfig corresponds with ?


From nico at fluxnic.net  Thu Jun  3 16:36:36 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 03 Jun 2010 16:36:36 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100603200357.GD9169@n2100.arm.linux.org.uk>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006031549400.24526@xanadu.home>
	<20100603200357.GD9169@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.00.1006031634520.24526@xanadu.home>

On Thu, 3 Jun 2010, Russell King - ARM Linux wrote:

> On Thu, Jun 03, 2010 at 03:59:03PM -0400, Nicolas Pitre wrote:
> > On Thu, 3 Jun 2010, Russell King - ARM Linux wrote:
> > 
> > > The subject says everything you need to know.  Randy provided this
> > > link earlier:
> > > 
> > >   http://lkml.org/lkml/2010/6/2/472
> > 
> > Leaving the drama aside...
> 
> Err, what drama?  Don't you think it would be absolutely stupid of me
> _not_ to highlight what's going to happen?

That's part of the drama.  And Linus is also playing a lead role in it.

Let's just try to step back and find a rational solution.

> > Let's acknowledge the problem and try to come up with a solution.
> 
> I agree with you, but it has already proven pointless to discuss.

I won't give up just yet.


Nicolas


From nico at fluxnic.net  Thu Jun  3 16:38:38 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 03 Jun 2010 16:38:38 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006032227.56429.marek.vasut@gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<201006032155.19349.marek.vasut@gmail.com>
	<20100603200109.GC9169@n2100.arm.linux.org.uk>
	<201006032227.56429.marek.vasut@gmail.com>
Message-ID: <alpine.LFD.2.00.1006031637190.24526@xanadu.home>

On Thu, 3 Jun 2010, Marek Vasut wrote:

> > Anyway, let's not start a new lengthy thread on the subject here; it won't
> > have much effect being only on this list.
> 
> Just as Nicolas pointed out, we need a solution. I guess lenghty thread is 
> unavoidable, sorry. If possible, could you CC interested parties ?

The discussion is happening on linux-kernel at vger.kernel.org.  Please 
feel free to contribute to the thread over there.  You don't need to be 
subscribed to post.


Nicolas


From ryan at bluewatersys.com  Thu Jun  3 17:04:57 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Fri, 04 Jun 2010 09:04:57 +1200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100603192459.GA9169@n2100.arm.linux.org.uk>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
Message-ID: <4C0818F9.9070008@bluewatersys.com>

Russell King - ARM Linux wrote:
> The subject says everything you need to know.  Randy provided this
> link earlier:
> 
>   http://lkml.org/lkml/2010/6/2/472
> 
> Linus doesn't appear to be listening to reason, so I see now this as
> a fait accompli.  It'll apparantly happen at the next merge window.
> 
> So, don't send anything which contains a defconfig file or updates to
> it.  It's pointless.

Is it worth being a bit proactive and getting rid of some of them in
advance? Things like spear3[012]0_defconfig are basically identically
except for the board type. Combining all three of those would remove
1500 lines of code.

Basically reduce down to one or two defconfigs for each mach directory
which include as many boards and drivers as possible. People wanting
more tailored configs can do that in their own trees.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From ryan at bluewatersys.com  Thu Jun  3 17:09:29 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Fri, 04 Jun 2010 09:09:29 +1200
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100603081354.GA4720@trinity.fluff.org>
References: <1275479804.137633.565764505843.0.gpush@pororo>	<1275479804.138101.137592675542.1.gpush@pororo>	<20100602120356.GQ7248@trinity.fluff.org>	<201006031121.21896.jeremy.kerr@canonical.com>
	<20100603081354.GA4720@trinity.fluff.org>
Message-ID: <4C081A09.1020706@bluewatersys.com>

Ben Dooks wrote:
> On Thu, Jun 03, 2010 at 11:21:19AM +0800, Jeremy Kerr wrote:
>> Hi Ben,
>>
>>>> And a set of clock operations (defined per type of clock):
>>>>
>>>> struct clk_operations {
>>>>
>>>>        int             (*enable)(struct clk *);
>>> I'd rather the enable/disable calls where simply a set
>>> and a bool on/off, very rarelyt is the enable and disable
>>> operartions different.
>> I thought about merging these, but decided against it. It does work for the 
>> simple case where we're setting a bit in a register:
>>
>> static int clk_foo_set_state(struct clk *_clk, int enable)
>> {
>> 	struct clk_foo *clk = to_clk_foo(_clk)
>> 	u32 reg;
>>
>> 	reg = raw_readl(foo->some_register);
>> 	if (enable)
>> 		reg |= FOO_ENABLE;
>> 	else
>> 		reg &= ~FOO_ENABLE;
>> 	raw_writel(foo->some_register, reg);
>>
>> 	return 0;
>> }
>>
>> However, for anything more complex than this - for example, if there's a 
>> parent clock - then we start getting pretty messy:
>>
>> static int clk_foo_set_state(struct clk *_clk, int enable)
>> {
>> 	struct clk_foo *clk = to_clk_foo(_clk)
>> 	u32 reg;
> 
> Yuck. I think this should really be handled by the base clk_enable()
> and clk_disable() calls. Roughly based on what is currently in the
> plat-samsung clock implementation:

I think its a good idea to do this incrementally. The proposed patches
don't require much code rewrite because the interface is basically the
same. I think the best approach is to get the proposed patches applied,
which basically just makes the common interface from
include/linux/clock.h generic, and _all_ of the mach implementations
(and possibly other archs such as powerpc) converted and tested first.
Then we can go from there to see what other common functionality can be
moved into the generic clock framework.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From grant.likely at secretlab.ca  Thu Jun  3 17:12:17 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 3 Jun 2010 15:12:17 -0600
Subject: Boot interface for device trees on ARM
In-Reply-To: <AANLkTil3vDAN4QIJJImk8MnQklisqFJq_RBc7c9VEZxl@mail.gmail.com>
References: <201005181054.32325.jeremy.kerr@canonical.com> 
	<alpine.LFD.2.00.1005172341200.12758@xanadu.home>
	<AANLkTilJl9_NHiT1LITG7UbA9S7OYsnGMcDAsFEEx5Ob@mail.gmail.com> 
	<alpine.LFD.2.00.1005191055180.12758@xanadu.home>
	<20100519200819.GF1693@shareable.org> 
	<alpine.LFD.2.00.1005191614580.12758@xanadu.home>
	<AANLkTil3vDAN4QIJJImk8MnQklisqFJq_RBc7c9VEZxl@mail.gmail.com>
Message-ID: <AANLkTikgdfC7LL8go8SiXDOll40ZoJeSn4uLjK3na1MO@mail.gmail.com>

On Fri, May 21, 2010 at 10:24 AM, John Rigby <jcrigby at gmail.com> wrote:
> Wow, no responses for almost two days, does that mean consensus has
> been reached?

No, it just means the merge window was open; not to mention the UDS hangover.

g.

>
> On Wed, May 19, 2010 at 2:22 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
>> On Wed, 19 May 2010, Jamie Lokier wrote:
>>
>>> Nicolas Pitre wrote:
>>> > It is not up to the bootloader to "adjust" to the kernel. ?But rather
>>> > for the kernel to cope with the bootloader's provided information. ?If
>>> > the bootloader passes a specific machine ID with the ATAG list then the
>>> > kernel will use that, and if the bootloader passes a DT machine ID with
>>> > a DT blob then the kernel will use that. ?You just have to configure
>>> > your kernel with both "machine types" at the same time.
>>>
>>> Scenario:
>>>
>>> You upgrade your systems to a new DT-capable kernel and DT-capable
>>> bootloader. ?It works great. ?You ship new instances of your device with this.
>>>
>>> Once they're in the field, someone reports a bug that doesn't happen
>>> with the older device instances. ?It's not a bug you can reproduce,
>>> but you suspect the newer of kernel. ?So you remote-update some of the
>>> newly shipped devices with an old, pre-DT kernel binary that's been
>>> stable on the older devices, to see if the bug goes away.
>>>
>>> Problem: The newer shipped devices have a DT-capable bootloader, and
>>> it can't boot old kernels, because they don't understand the DT format.
>>>
>>> You could remote-downgrade the bootloaders, but that's risky. ?You
>>> could try building the old kernel with DT support, but that adds
>>> another variable to your testing.
>>>
>>> Anticipating this well in advance, you of course built your DT-capable
>>> bootloader with the ability to boot old and new style kernels...
>>
>> Exact. ?Quoting myself:
>>
>> |I think that, for the moment, it is best if the bootloader on already
>> |existing subarchitectures where DT is introduced still preserve the
>> |already existing ability to boot using ATAGs. ?This allows for the
>> |testing and validation of the DT concept against the legacy ATAG method
>> |more easily.
>> |
>> |On new subarchitectures, it might make sense to go with DT from the
>> |start instead of creating setup code for every single machine. ?In that
>> |case the bootloader for those machines would only need to care about DT
>> |and forget about ATAGs.
>>
>>
>> Nicolas
>> _______________________________________________
>> devicetree-discuss mailing list
>> devicetree-discuss at lists.ozlabs.org
>> https://lists.ozlabs.org/listinfo/devicetree-discuss
>>
> _______________________________________________
> devicetree-discuss mailing list
> devicetree-discuss at lists.ozlabs.org
> https://lists.ozlabs.org/listinfo/devicetree-discuss
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From nico at fluxnic.net  Thu Jun  3 18:31:56 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 03 Jun 2010 18:31:56 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C0818F9.9070008@bluewatersys.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<4C0818F9.9070008@bluewatersys.com>
Message-ID: <alpine.LFD.2.00.1006031829020.24526@xanadu.home>

On Fri, 4 Jun 2010, Ryan Mallon wrote:

> Is it worth being a bit proactive and getting rid of some of them in
> advance? Things like spear3[012]0_defconfig are basically identically
> except for the board type. Combining all three of those would remove
> 1500 lines of code.

Please go ahead with a patch.

> Basically reduce down to one or two defconfigs for each mach directory
> which include as many boards and drivers as possible. People wanting
> more tailored configs can do that in their own trees.

This actually should have been the plan from the start.  See for example 
orion5x_defconfig which currently already supports 23 machines.


Nicolas


From ryan at bluewatersys.com  Thu Jun  3 19:33:35 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Fri, 04 Jun 2010 11:33:35 +1200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <alpine.LFD.2.00.1006031829020.24526@xanadu.home>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<4C0818F9.9070008@bluewatersys.com>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
Message-ID: <4C083BCF.2060500@bluewatersys.com>

Nicolas Pitre wrote:
> On Fri, 4 Jun 2010, Ryan Mallon wrote:
> 
>> Is it worth being a bit proactive and getting rid of some of them in
>> advance? Things like spear3[012]0_defconfig are basically identically
>> except for the board type. Combining all three of those would remove
>> 1500 lines of code.
> 
> Please go ahead with a patch.

Hmm, not as easy as I thought. The three boards cannot be built into a
single kernel since the arch/arm/mach-spear3xx/spear3[012]0.c files all
extern a bunch of structs which have naming conflicts.

It does look possible to rewrite that code so that all three boards can
be built into a single kernel. I can try and put together a patch, but I
don't have any hardware to test with.

The at91 is actually in a similar state, where only one of the
at91sam9260, at91sam9g45, etc can be selected. Again, it should be
possible to rework the code so that most of the different cpus can be
built into a single kernel. I'm sure other mach's are in a simliar
state. Fixing these where possible would allow us to have single
defconfigs per mach directory and reduce code churn, which is what Linus
is really complaining about.

>> Basically reduce down to one or two defconfigs for each mach directory
>> which include as many boards and drivers as possible. People wanting
>> more tailored configs can do that in their own trees.
> 
> This actually should have been the plan from the start.  See for example 
> orion5x_defconfig which currently already supports 23 machines.

It seems that in a few cases at least the problem is really that all of
the boards for a mach directory cannot be compiled into one kernel.
Fixing that would be a useful goal.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From kmpark at infradead.org  Thu Jun  3 19:45:16 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 4 Jun 2010 08:45:16 +0900
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C083BCF.2060500@bluewatersys.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<4C0818F9.9070008@bluewatersys.com>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
Message-ID: <AANLkTinKoGMzJBUhUkG9O--Q2sWbqaSgdHKTJ6QtrbOd@mail.gmail.com>

On Fri, Jun 4, 2010 at 8:33 AM, Ryan Mallon <ryan at bluewatersys.com> wrote:
> Nicolas Pitre wrote:
>> On Fri, 4 Jun 2010, Ryan Mallon wrote:
>>
>>> Is it worth being a bit proactive and getting rid of some of them in
>>> advance? Things like spear3[012]0_defconfig are basically identically
>>> except for the board type. Combining all three of those would remove
>>> 1500 lines of code.
>>
>> Please go ahead with a patch.
>
> Hmm, not as easy as I thought. The three boards cannot be built into a
> single kernel since the arch/arm/mach-spear3xx/spear3[012]0.c files all
> extern a bunch of structs which have naming conflicts.
>
> It does look possible to rewrite that code so that all three boards can
> be built into a single kernel. I can try and put together a patch, but I
> don't have any hardware to test with.
>
> The at91 is actually in a similar state, where only one of the
> at91sam9260, at91sam9g45, etc can be selected. Again, it should be
> possible to rework the code so that most of the different cpus can be
> built into a single kernel. I'm sure other mach's are in a simliar
> state. Fixing these where possible would allow us to have single
> defconfigs per mach directory and reduce code churn, which is what Linus
> is really complaining about.
>
>>> Basically reduce down to one or two defconfigs for each mach directory
>>> which include as many boards and drivers as possible. People wanting
>>> more tailored configs can do that in their own trees.
>>
>> This actually should have been the plan from the start. ?See for example
>> orion5x_defconfig which currently already supports 23 machines.

If target has several variants with different memory size, different
GPIOs. It's really hard to maintain and support.
To address this issues. we implement the detect routine and give
different system revision at bootloader side and kernel boot with this
information. with this approaches I can support 5 different targets
based on s5pc110.

In previous time, we usually make a kernel for each boards but it's
hard works and takes long time. So single kernel is best approaches
and it's possible at least similar CPUs. e.g. samsung s5p series.

As I know s5pc110 (aka s5pv210) and s5p644x is similar and can
possible to make single kernel.

Thank you,
Kyungmin Park


From ben-linux at fluff.org  Thu Jun  3 19:45:54 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 4 Jun 2010 00:45:54 +0100
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <4C081A09.1020706@bluewatersys.com>
References: <1275479804.137633.565764505843.0.gpush@pororo>
	<1275479804.138101.137592675542.1.gpush@pororo>
	<20100602120356.GQ7248@trinity.fluff.org>
	<201006031121.21896.jeremy.kerr@canonical.com>
	<20100603081354.GA4720@trinity.fluff.org>
	<4C081A09.1020706@bluewatersys.com>
Message-ID: <20100603234554.GE4720@trinity.fluff.org>

On Fri, Jun 04, 2010 at 09:09:29AM +1200, Ryan Mallon wrote:
> Ben Dooks wrote:
> > On Thu, Jun 03, 2010 at 11:21:19AM +0800, Jeremy Kerr wrote:
> >> Hi Ben,
> >>
> >>>> And a set of clock operations (defined per type of clock):
> >>>>
> >>>> struct clk_operations {
> >>>>
> >>>>        int             (*enable)(struct clk *);
> >>> I'd rather the enable/disable calls where simply a set
> >>> and a bool on/off, very rarelyt is the enable and disable
> >>> operartions different.
> >> I thought about merging these, but decided against it. It does work for the 
> >> simple case where we're setting a bit in a register:
> >>
> >> static int clk_foo_set_state(struct clk *_clk, int enable)
> >> {
> >> 	struct clk_foo *clk = to_clk_foo(_clk)
> >> 	u32 reg;
> >>
> >> 	reg = raw_readl(foo->some_register);
> >> 	if (enable)
> >> 		reg |= FOO_ENABLE;
> >> 	else
> >> 		reg &= ~FOO_ENABLE;
> >> 	raw_writel(foo->some_register, reg);
> >>
> >> 	return 0;
> >> }
> >>
> >> However, for anything more complex than this - for example, if there's a 
> >> parent clock - then we start getting pretty messy:
> >>
> >> static int clk_foo_set_state(struct clk *_clk, int enable)
> >> {
> >> 	struct clk_foo *clk = to_clk_foo(_clk)
> >> 	u32 reg;
> > 
> > Yuck. I think this should really be handled by the base clk_enable()
> > and clk_disable() calls. Roughly based on what is currently in the
> > plat-samsung clock implementation:
> 
> I think its a good idea to do this incrementally. The proposed patches
> don't require much code rewrite because the interface is basically the
> same. I think the best approach is to get the proposed patches applied,
> which basically just makes the common interface from

Given the latest comments by Linus on churn, it would be better to
get a well specified <linux/clk.h> decided on before it goes in so
that everyone can move over to it. We're moving to a system where
any change in functionality is going to cause problems with respect
to a wide range of systems.

If the new <linux/clk.h> is not well specified it is just goign to
cause problems down the line of people infering behaviour from other
implementations (a bad idea) and/or causing large tracts of changes.

> include/linux/clock.h generic, and _all_ of the mach implementations
> (and possibly other archs such as powerpc) converted and tested first.
> Then we can go from there to see what other common functionality can be
> moved into the generic clock framework.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From dwalker at codeaurora.org  Thu Jun  3 19:46:37 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Thu, 03 Jun 2010 16:46:37 -0700
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100603200109.GC9169@n2100.arm.linux.org.uk>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<201006032155.19349.marek.vasut@gmail.com>
	<20100603200109.GC9169@n2100.arm.linux.org.uk>
Message-ID: <1275608797.23384.328.camel@c-dwalke-linux.qualcomm.com>

On Thu, 2010-06-03 at 21:01 +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 03, 2010 at 09:55:19PM +0200, Marek Vasut wrote:
> > Dne ?t 3. ?ervna 2010 21:24:59 Russell King - ARM Linux napsal(a):
> > > The subject says everything you need to know.  Randy provided this
> > > link earlier:
> > > 
> > >   http://lkml.org/lkml/2010/6/2/472
> > > 
> > > Linus doesn't appear to be listening to reason, so I see now this as
> > > a fait accompli.  It'll apparantly happen at the next merge window.
> > 
> > The defconfigs age ... there's no point keeping them. They'll be useless crap 
> > unless someone updates them often anyway.
> > 
> > Maybe adding a Kconfig option that's select all the default stuff the platform 
> > needs would be a way to go ? (that was already proposed there)
> 
> The problem comes (as Daniel pointed out _after_ my suggested solution to
> this problem) is if you want to turn off something that's 'selected' in
> this way.
> 
> Anyway, let's not start a new lengthy thread on the subject here; it won't
> have much effect being only on this list.

I think Linus was suggesting that we create Kconfig files that are
strictly used to generate .config files for certain platforms.

So his proposal was to encode everything into Kconfig files, but those
Kconfig options we use don't show up in "make menuconfig" .. so the
whole notion of things not getting unselected doesn't really matter, we
wouldn't end up dealing with it.

You would just generate the .config for whatever sub-architecture you
need, then run "make menuconfig" and select or de-select whatever else
you want.

Daniel



From ben-linux at fluff.org  Thu Jun  3 20:06:05 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 4 Jun 2010 01:06:05 +0100
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100603110533.GB7127@n2100.arm.linux.org.uk>
References: <1275479804.137633.565764505843.0.gpush@pororo>
	<201006031121.21896.jeremy.kerr@canonical.com>
	<20100603081354.GA4720@trinity.fluff.org>
	<201006031824.53832.jeremy.kerr@canonical.com>
	<20100603110533.GB7127@n2100.arm.linux.org.uk>
Message-ID: <20100604000605.GF4720@trinity.fluff.org>

On Thu, Jun 03, 2010 at 12:05:33PM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 03, 2010 at 06:24:50PM +0800, Jeremy Kerr wrote:
> > OK, this would mean adding parent to struct clk:
> > 
> > struct clk {
> > 	struct clk_operations	*ops;
> > 	atomic_t				enable_count;
> 
> I don't think it makes sense for this to be an atomic type.
> 
> > static inline int clk_enable(struct clk *clk)
> > {
> > 	int ret;
> > 
> > 	if (atomic_inc(clk->enable_count) != 1))
> > 		return 0;
> 
> Okay, so what if we sleep at this point, and someone else comes along
> and calls clk_enable(), which'll merely increment the count and return.
> 
> Unfortunately, the clock is still disabled at that point - which is a
> violation of what's supposed to happen.
> 
> Or to put it another way, the above method results in clk_enable()
> sometimes returning with the clock enabled and sometimes with the
> clock still disabled.
> 
> That's not nice behaviour for drivers which may need the clock enabled
> to read/write the device registers.

You're right, especially if the clock takes time to enable.

Either we need some form of locking to deal with this. An overall lock
will cause problems with respect to re-using clk_enable() internally
and per-clock locks are probably a bad idea with respect of trying to
lock the parents (deadlock) depending on the implementation.

I'm not sure if something like a wake queue is required, where any caller
who is calling when the clock is disabled gets placed on the queue
awaiting the original enabler finishing the enable operation.

	 if (atomic_increment(&clk->usage_count) == 1) {
	    /* start enable */
	    atomic_set(&clk->is_enabled, 1);
	    wake_up(&clk->wait_for_enable);   
	 } else if (atomic_read(&clk->is_enabled) == 0) {
	   wait_event(&clk->wait_for_enable);
	 }

Also, what about the behaviour across >1 CPU? There's a pile of
up-comming SoCs with SMP ARM cores. If CPU1 enables the clock, and CPU2
comes along and tries to do that also, we have the same race condition
again.

As an addendum to Russell's comments, we need to specify the behaviour
with resepect to what happens about clock stabilisation as well, if the
clock we enabled takes time to stabilise, then should we wait? This will
be even worse when we realise some of these architectures have clocks
which are source from PLLs that can be turned on/off, and these PLLs
have settling time in 100s of usecs.

Even if the clock is enabled, it requires time to stabilise to avoid
problems when the driver then goes to try and use it.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From nico at fluxnic.net  Thu Jun  3 20:13:32 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 03 Jun 2010 20:13:32 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <AANLkTinKoGMzJBUhUkG9O--Q2sWbqaSgdHKTJ6QtrbOd@mail.gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<4C0818F9.9070008@bluewatersys.com>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
	<AANLkTinKoGMzJBUhUkG9O--Q2sWbqaSgdHKTJ6QtrbOd@mail.gmail.com>
Message-ID: <alpine.LFD.2.00.1006031955510.24526@xanadu.home>

On Fri, 4 Jun 2010, Kyungmin Park wrote:

> If target has several variants with different memory size, different
> GPIOs. It's really hard to maintain and support.
> To address this issues. we implement the detect routine and give
> different system revision at bootloader side and kernel boot with this
> information. with this approaches I can support 5 different targets
> based on s5pc110.

Please have a look at arch/arm/mach-kirkwood/netspace_v2-setup.c for 
example.  This file contains the support for two boards already.  
They're supported by the same source files because they have lot of code 
in common.  but the differences are distinguished by the machine ID 
number passed into r1 by the bootloader used to select which machine 
record is selected.  The proper machine_init method within each of those 
machine records is called on boot, where a different table for GPIO 
initialization (it is called MPP on Kirkwood) is again selected.  All 
this is accomplished at run time.

If you want more complex GPIO config variants, have a look at mach-pxa/* 
where they're called MFP instead.

Memory size should normally be detected and passed along to the kernel 
by the bootloader.

> In previous time, we usually make a kernel for each boards but it's
> hard works and takes long time. So single kernel is best approaches
> and it's possible at least similar CPUs. e.g. samsung s5p series.
> 
> As I know s5pc110 (aka s5pv210) and s5p644x is similar and can
> possible to make single kernel.

Exact.  It is always a good idea to try to compile as many boards as 
possible in a single kernel, and then have the ability to optimize the 
kernel configuration in order to have the support for only one board 
built into the kernel if desired.


Nicolas


From lizf at cn.fujitsu.com  Thu Jun  3 20:57:35 2010
From: lizf at cn.fujitsu.com (Li Zefan)
Date: Fri, 04 Jun 2010 08:57:35 +0800
Subject: [PATCH 2/2] menuconfig: truncate list items
In-Reply-To: <4C07D932.4040404@oracle.com>
References: <4C0758B7.5070907@cn.fujitsu.com>
	<4C0758C9.7080108@cn.fujitsu.com> <4C07D932.4040404@oracle.com>
Message-ID: <4C084F7F.9060802@cn.fujitsu.com>

Randy Dunlap wrote:
> On 06/03/10 00:24, Li Zefan wrote:
>> Truncate list items to fit in a single line, otherwise those items
>> which have long prompts will cover some other items.
>>
>> This follows the behavior of menubox.
>>
>> Signed-off-by: Li Zefan <lizf at cn.fujitsu.com>
> 
> Thanks :)
> 
> Tested-by: Randy Dunlap <randy.dunlap at oracle.com>
> 
> Ben, the Samsung S3C24* prompt still gets truncated with this patch (when using
> an 80-column wide xterm).  If you care about seeing all of the models,
> you might want to shorten the prompt.
> 

An alterative is to print the truncated string and end it with "...":

( ) Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440...





From marek.vasut at gmail.com  Thu Jun  3 21:07:32 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri,  4 Jun 2010 03:07:32 +0200
Subject: [PATCH 1/3] pxa/colibri270: Fix typo in colibri_pxa270_flash
Message-ID: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>

Append colibri_pxa270_flash(_device). This was missing.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/colibri-pxa270.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index 96ce4ae..98673ac 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -99,7 +99,7 @@ static struct platform_device colibri_pxa270_flash_device = {
 
 static void __init colibri_pxa270_nor_init(void)
 {
-	platform_device_register(&colibri_pxa270_flash);
+	platform_device_register(&colibri_pxa270_flash_device);
 }
 #else
 static inline void colibri_pxa270_nor_init(void) {}
-- 
1.7.1



From marek.vasut at gmail.com  Thu Jun  3 21:07:34 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri,  4 Jun 2010 03:07:34 +0200
Subject: [PATCH 3/3] wm97xx_batt: Remove redundant header file
In-Reply-To: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>
References: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1275613654-23918-3-git-send-email-marek.vasut@gmail.com>

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 include/linux/wm97xx_batt.h |   16 ----------------
 1 files changed, 0 insertions(+), 16 deletions(-)
 delete mode 100644 include/linux/wm97xx_batt.h

diff --git a/include/linux/wm97xx_batt.h b/include/linux/wm97xx_batt.h
deleted file mode 100644
index a1d6419..0000000
--- a/include/linux/wm97xx_batt.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef _LINUX_WM97XX_BAT_H
-#define _LINUX_WM97XX_BAT_H
-
-#include <linux/wm97xx.h>
-
-#warning This file will be removed soon, use wm97xx.h instead!
-
-#define wm97xx_batt_info wm97xx_batt_pdata
-
-#ifdef CONFIG_BATTERY_WM97XX
-void wm97xx_bat_set_pdata(struct wm97xx_batt_info *data);
-#else
-static inline void wm97xx_bat_set_pdata(struct wm97xx_batt_info *data) {}
-#endif
-
-#endif
-- 
1.7.1



From marek.vasut at gmail.com  Thu Jun  3 21:07:33 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri,  4 Jun 2010 03:07:33 +0200
Subject: [PATCH 2/3] pxa: Fix all devices using wm97xx_batt.h
In-Reply-To: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>
References: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1275613654-23918-2-git-send-email-marek.vasut@gmail.com>

This file is scheduled for removal, therefore fix all devices that use this
file to use the suggested wm97xx.h and pass platform data properly.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/mioa701.c  |   10 +++++++---
 arch/arm/mach-pxa/palmld.c   |   19 ++++++++++---------
 arch/arm/mach-pxa/palmt5.c   |   19 ++++++++++---------
 arch/arm/mach-pxa/palmte2.c  |   20 ++++++++++++--------
 arch/arm/mach-pxa/palmtreo.c |    1 -
 arch/arm/mach-pxa/palmtx.c   |   19 ++++++++++---------
 arch/arm/mach-pxa/palmz72.c  |   20 ++++++++++++--------
 7 files changed, 61 insertions(+), 47 deletions(-)

diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index d60db87..dbfe4ba 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -34,7 +34,7 @@
 #include <linux/irq.h>
 #include <linux/pda_power.h>
 #include <linux/power_supply.h>
-#include <linux/wm97xx_batt.h>
+#include <linux/wm97xx.h>
 #include <linux/mtd/physmap.h>
 #include <linux/usb/gpio_vbus.h>
 #include <linux/regulator/max1586.h>
@@ -636,7 +636,7 @@ static struct platform_device power_dev = {
 	},
 };
 
-static struct wm97xx_batt_info mioa701_battery_data = {
+static struct wm97xx_batt_pdata mioa701_battery_data = {
 	.batt_aux	= WM97XX_AUX_ID1,
 	.temp_aux	= -1,
 	.charge_gpio	= -1,
@@ -648,6 +648,10 @@ static struct wm97xx_batt_info mioa701_battery_data = {
 	.batt_name	= "mioa701_battery",
 };
 
+static struct wm97xx_pdata mioa701_wm97xx_pdata = {
+	.batt_pdata	= &mioa701_battery_data,
+};
+
 /*
  * Voltage regulation
  */
@@ -716,6 +720,7 @@ struct i2c_pxa_platform_data i2c_pdata = {
 
 static pxa2xx_audio_ops_t mioa701_ac97_info = {
 	.reset_gpio = 95,
+	.codec_pdata = { &mioa701_wm97xx_pdata, },
 };
 
 /*
@@ -794,7 +799,6 @@ static void __init mioa701_machine_init(void)
 	set_pxa_fb_info(&mioa701_pxafb_info);
 	pxa_set_mci_info(&mioa701_mci_info);
 	pxa_set_keypad_info(&mioa701_keypad_info);
-	wm97xx_bat_set_pdata(&mioa701_battery_data);
 	pxa_set_udc_info(&mioa701_udc_info);
 	pxa_set_ac97_info(&mioa701_ac97_info);
 	pm_power_off = mioa701_poweroff;
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 1963819..83a1a55 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -22,7 +22,7 @@
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio.h>
-#include <linux/wm97xx_batt.h>
+#include <linux/wm97xx.h>
 #include <linux/power_supply.h>
 #include <linux/sysdev.h>
 #include <linux/mtd/mtd.h>
@@ -387,9 +387,9 @@ static struct platform_device power_supply = {
 };
 
 /******************************************************************************
- * WM97xx battery
+ * WM97xx audio, battery
  ******************************************************************************/
-static struct wm97xx_batt_info wm97xx_batt_pdata = {
+static struct wm97xx_batt_pdata palmld_batt_pdata = {
 	.batt_aux	= WM97XX_AUX_ID3,
 	.temp_aux	= WM97XX_AUX_ID2,
 	.charge_gpio	= -1,
@@ -403,15 +403,17 @@ static struct wm97xx_batt_info wm97xx_batt_pdata = {
 	.batt_name	= "main-batt",
 };
 
-/******************************************************************************
- * aSoC audio
- ******************************************************************************/
-static struct palm27x_asoc_info palmld_asoc_pdata = {
-	.jack_gpio	= GPIO_NR_PALMLD_EARPHONE_DETECT,
+static struct wm97xx_pdata palmld_wm97xx_pdata = {
+	.batt_pdata	= &palmld_batt_pdata,
 };
 
 static pxa2xx_audio_ops_t palmld_ac97_pdata = {
 	.reset_gpio	= 95,
+	.codec_pdata	= { &palmld_wm97xx_pdata, },
+};
+
+static struct palm27x_asoc_info palmld_asoc_pdata = {
+	.jack_gpio	= GPIO_NR_PALMLD_EARPHONE_DETECT,
 };
 
 static struct platform_device palmld_asoc = {
@@ -521,7 +523,6 @@ static void __init palmld_init(void)
 	pxa_set_ac97_info(&palmld_ac97_pdata);
 	pxa_set_ficp_info(&palmld_ficp_platform_data);
 	pxa_set_keypad_info(&palmld_keypad_platform_data);
-	wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 5305a39..0b36d7d 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -24,7 +24,7 @@
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio.h>
-#include <linux/wm97xx_batt.h>
+#include <linux/wm97xx.h>
 #include <linux/power_supply.h>
 #include <linux/usb/gpio_vbus.h>
 
@@ -298,9 +298,9 @@ static struct platform_device power_supply = {
 };
 
 /******************************************************************************
- * WM97xx battery
+ * WM97xx audio, battery
  ******************************************************************************/
-static struct wm97xx_batt_info wm97xx_batt_pdata = {
+static struct wm97xx_batt_pdata palmt5_batt_pdata = {
 	.batt_aux	= WM97XX_AUX_ID3,
 	.temp_aux	= WM97XX_AUX_ID2,
 	.charge_gpio	= -1,
@@ -314,15 +314,17 @@ static struct wm97xx_batt_info wm97xx_batt_pdata = {
 	.batt_name	= "main-batt",
 };
 
-/******************************************************************************
- * aSoC audio
- ******************************************************************************/
-static struct palm27x_asoc_info palmt5_asoc_pdata = {
-	.jack_gpio	= GPIO_NR_PALMT5_EARPHONE_DETECT,
+static struct wm97xx_pdata palmt5_wm97xx_pdata = {
+	.batt_pdata	= &palmt5_batt_pdata,
 };
 
 static pxa2xx_audio_ops_t palmt5_ac97_pdata = {
 	.reset_gpio	= 95,
+	.codec_pdata	= { &palmt5_wm97xx_pdata, },
+};
+
+static struct palm27x_asoc_info palmt5_asoc_pdata = {
+	.jack_gpio	= GPIO_NR_PALMT5_EARPHONE_DETECT,
 };
 
 static struct platform_device palmt5_asoc = {
@@ -411,7 +413,6 @@ static void __init palmt5_init(void)
 	pxa_set_ac97_info(&palmt5_ac97_pdata);
 	pxa_set_ficp_info(&palmt5_ficp_platform_data);
 	pxa_set_keypad_info(&palmt5_keypad_platform_data);
-	wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 3d284ff..93c11a0 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -23,7 +23,7 @@
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio.h>
-#include <linux/wm97xx_batt.h>
+#include <linux/wm97xx.h>
 #include <linux/power_supply.h>
 #include <linux/usb/gpio_vbus.h>
 
@@ -271,9 +271,9 @@ static struct platform_device power_supply = {
 };
 
 /******************************************************************************
- * WM97xx battery
+ * WM97xx audio, battery
  ******************************************************************************/
-static struct wm97xx_batt_info wm97xx_batt_pdata = {
+static struct wm97xx_batt_pdata palmte2_batt_pdata = {
 	.batt_aux	= WM97XX_AUX_ID3,
 	.temp_aux	= WM97XX_AUX_ID2,
 	.charge_gpio	= -1,
@@ -287,9 +287,14 @@ static struct wm97xx_batt_info wm97xx_batt_pdata = {
 	.batt_name	= "main-batt",
 };
 
-/******************************************************************************
- * aSoC audio
- ******************************************************************************/
+static struct wm97xx_pdata palmte2_wm97xx_pdata = {
+	.batt_pdata	= &palmte2_batt_pdata,
+};
+
+static pxa2xx_audio_ops_t palmte2_ac97_pdata = {
+	.codec_pdata	= { &palmte2_wm97xx_pdata, },
+};
+
 static struct palm27x_asoc_info palmte2_asoc_pdata = {
 	.jack_gpio	= GPIO_NR_PALMTE2_EARPHONE_DETECT,
 };
@@ -361,9 +366,8 @@ static void __init palmte2_init(void)
 	set_pxa_fb_info(&palmte2_lcd_screen);
 	pxa_set_mci_info(&palmte2_mci_platform_data);
 	palmte2_udc_init();
-	pxa_set_ac97_info(NULL);
+	pxa_set_ac97_info(&palmte2_ac97_pdata);
 	pxa_set_ficp_info(&palmte2_ficp_platform_data);
-	wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index d8b4469..4eb0258 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -23,7 +23,6 @@
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio.h>
-#include <linux/wm97xx_batt.h>
 #include <linux/power_supply.h>
 #include <linux/sysdev.h>
 #include <linux/w1-gpio.h>
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index ecc1a40..a5429cd 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -25,7 +25,7 @@
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio.h>
-#include <linux/wm97xx_batt.h>
+#include <linux/wm97xx.h>
 #include <linux/power_supply.h>
 #include <linux/usb/gpio_vbus.h>
 #include <linux/mtd/nand.h>
@@ -359,9 +359,9 @@ static struct platform_device power_supply = {
 };
 
 /******************************************************************************
- * WM97xx battery
+ * WM97xx audio, battery
  ******************************************************************************/
-static struct wm97xx_batt_info wm97xx_batt_pdata = {
+static struct wm97xx_batt_pdata palmtx_batt_pdata = {
 	.batt_aux	= WM97XX_AUX_ID3,
 	.temp_aux	= WM97XX_AUX_ID2,
 	.charge_gpio	= -1,
@@ -375,15 +375,17 @@ static struct wm97xx_batt_info wm97xx_batt_pdata = {
 	.batt_name	= "main-batt",
 };
 
-/******************************************************************************
- * aSoC audio
- ******************************************************************************/
-static struct palm27x_asoc_info palmtx_asoc_pdata = {
-	.jack_gpio	= GPIO_NR_PALMTX_EARPHONE_DETECT,
+static struct wm97xx_pdata palmtx_wm97xx_pdata = {
+	.batt_pdata	= &palmtx_batt_pdata,
 };
 
 static pxa2xx_audio_ops_t palmtx_ac97_pdata = {
 	.reset_gpio	= 95,
+	.codec_pdata	= { &palmtx_wm97xx_pdata, },
+};
+
+static struct palm27x_asoc_info palmtx_asoc_pdata = {
+	.jack_gpio	= GPIO_NR_PALMTX_EARPHONE_DETECT,
 };
 
 static struct platform_device palmtx_asoc = {
@@ -562,7 +564,6 @@ static void __init palmtx_init(void)
 	pxa_set_ac97_info(&palmtx_ac97_pdata);
 	pxa_set_ficp_info(&palmtx_ficp_platform_data);
 	pxa_set_keypad_info(&palmtx_keypad_platform_data);
-	wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 }
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 3a7925c..b78c6b4 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -27,7 +27,7 @@
 #include <linux/pda_power.h>
 #include <linux/pwm_backlight.h>
 #include <linux/gpio.h>
-#include <linux/wm97xx_batt.h>
+#include <linux/wm97xx.h>
 #include <linux/power_supply.h>
 #include <linux/usb/gpio_vbus.h>
 
@@ -325,9 +325,9 @@ static struct platform_device power_supply = {
 };
 
 /******************************************************************************
- * WM97xx battery
+ * WM97xx audio, battery
  ******************************************************************************/
-static struct wm97xx_batt_info wm97xx_batt_pdata = {
+static struct wm97xx_batt_pdata palmz72_batt_pdata = {
 	.batt_aux	= WM97XX_AUX_ID3,
 	.temp_aux	= WM97XX_AUX_ID2,
 	.charge_gpio	= -1,
@@ -341,9 +341,14 @@ static struct wm97xx_batt_info wm97xx_batt_pdata = {
 	.batt_name	= "main-batt",
 };
 
-/******************************************************************************
- * aSoC audio
- ******************************************************************************/
+static struct wm97xx_pdata palmz72_wm97xx_pdata = {
+	.batt_pdata	= &palmz72_batt_pdata,
+};
+
+static pxa2xx_audio_ops_t palmz72_ac97_pdata = {
+	.codec_pdata	= { &palmz72_wm97xx_pdata, },
+};
+
 static struct platform_device palmz72_asoc = {
 	.name = "palm27x-asoc",
 	.id   = -1,
@@ -480,10 +485,9 @@ static void __init palmz72_init(void)
 	set_pxa_fb_info(&palmz72_lcd_screen);
 	pxa_set_mci_info(&palmz72_mci_platform_data);
 	palmz72_udc_init();
-	pxa_set_ac97_info(NULL);
+	pxa_set_ac97_info(&palmz72_ac97_pdata);
 	pxa_set_ficp_info(&palmz72_ficp_platform_data);
 	pxa_set_keypad_info(&palmz72_keypad_platform_data);
-	wm97xx_bat_set_pdata(&wm97xx_batt_pdata);
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 }
-- 
1.7.1



From marek.vasut at gmail.com  Thu Jun  3 21:10:14 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 4 Jun 2010 03:10:14 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C083BCF.2060500@bluewatersys.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
Message-ID: <201006040310.15019.marek.vasut@gmail.com>

Dne P? 4. ?ervna 2010 01:33:35 Ryan Mallon napsal(a):
> Nicolas Pitre wrote:
> > On Fri, 4 Jun 2010, Ryan Mallon wrote:
> >> Is it worth being a bit proactive and getting rid of some of them in
> >> advance? Things like spear3[012]0_defconfig are basically identically
> >> except for the board type. Combining all three of those would remove
> >> 1500 lines of code.
> > 
> > Please go ahead with a patch.
> 
> Hmm, not as easy as I thought. The three boards cannot be built into a
> single kernel since the arch/arm/mach-spear3xx/spear3[012]0.c files all
> extern a bunch of structs which have naming conflicts.
> 
> It does look possible to rewrite that code so that all three boards can
> be built into a single kernel. I can try and put together a patch, but I
> don't have any hardware to test with.
> 
> The at91 is actually in a similar state, where only one of the
> at91sam9260, at91sam9g45, etc can be selected. Again, it should be
> possible to rework the code so that most of the different cpus can be
> built into a single kernel. I'm sure other mach's are in a simliar
> state. Fixing these where possible would allow us to have single
> defconfigs per mach directory and reduce code churn, which is what Linus
> is really complaining about.

I just tested, PXA (mach-pxa) probably can be compiled into single kernel 
supporting all the boards.

> 
> >> Basically reduce down to one or two defconfigs for each mach directory
> >> which include as many boards and drivers as possible. People wanting
> >> more tailored configs can do that in their own trees.
> > 
> > This actually should have been the plan from the start.  See for example
> > orion5x_defconfig which currently already supports 23 machines.
> 
> It seems that in a few cases at least the problem is really that all of
> the boards for a mach directory cannot be compiled into one kernel.
> Fixing that would be a useful goal.
> 
> ~Ryan


From ryan at bluewatersys.com  Thu Jun  3 21:16:17 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Fri, 04 Jun 2010 13:16:17 +1200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006040310.15019.marek.vasut@gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
Message-ID: <4C0853E1.1080005@bluewatersys.com>

Marek Vasut wrote:
> Dne P? 4. ?ervna 2010 01:33:35 Ryan Mallon napsal(a):
>> Nicolas Pitre wrote:
>>> On Fri, 4 Jun 2010, Ryan Mallon wrote:
>>>> Is it worth being a bit proactive and getting rid of some of them in
>>>> advance? Things like spear3[012]0_defconfig are basically identically
>>>> except for the board type. Combining all three of those would remove
>>>> 1500 lines of code.
>>> Please go ahead with a patch.
>> Hmm, not as easy as I thought. The three boards cannot be built into a
>> single kernel since the arch/arm/mach-spear3xx/spear3[012]0.c files all
>> extern a bunch of structs which have naming conflicts.
>>
>> It does look possible to rewrite that code so that all three boards can
>> be built into a single kernel. I can try and put together a patch, but I
>> don't have any hardware to test with.
>>
>> The at91 is actually in a similar state, where only one of the
>> at91sam9260, at91sam9g45, etc can be selected. Again, it should be
>> possible to rework the code so that most of the different cpus can be
>> built into a single kernel. I'm sure other mach's are in a simliar
>> state. Fixing these where possible would allow us to have single
>> defconfigs per mach directory and reduce code churn, which is what Linus
>> is really complaining about.
> 
> I just tested, PXA (mach-pxa) probably can be compiled into single kernel 
> supporting all the boards.

Yes, IIRC Russell and Eric did a huge amount of work to get pxa into
that state.

ryan at okiwi:configs$ grep "ARCH_PXA=y" * | wc -l
25

Can we remove/combine some of those?

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From eric.y.miao at gmail.com  Thu Jun  3 21:35:28 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 4 Jun 2010 09:35:28 +0800
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C0853E1.1080005@bluewatersys.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk> 
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com> 
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
Message-ID: <AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>

On Fri, Jun 4, 2010 at 9:16 AM, Ryan Mallon <ryan at bluewatersys.com> wrote:
> Marek Vasut wrote:
>> Dne P? 4. ?ervna 2010 01:33:35 Ryan Mallon napsal(a):
>>> Nicolas Pitre wrote:
>>>> On Fri, 4 Jun 2010, Ryan Mallon wrote:
>>>>> Is it worth being a bit proactive and getting rid of some of them in
>>>>> advance? Things like spear3[012]0_defconfig are basically identically
>>>>> except for the board type. Combining all three of those would remove
>>>>> 1500 lines of code.
>>>> Please go ahead with a patch.
>>> Hmm, not as easy as I thought. The three boards cannot be built into a
>>> single kernel since the arch/arm/mach-spear3xx/spear3[012]0.c files all
>>> extern a bunch of structs which have naming conflicts.
>>>
>>> It does look possible to rewrite that code so that all three boards can
>>> be built into a single kernel. I can try and put together a patch, but I
>>> don't have any hardware to test with.
>>>
>>> The at91 is actually in a similar state, where only one of the
>>> at91sam9260, at91sam9g45, etc can be selected. Again, it should be
>>> possible to rework the code so that most of the different cpus can be
>>> built into a single kernel. I'm sure other mach's are in a simliar
>>> state. Fixing these where possible would allow us to have single
>>> defconfigs per mach directory and reduce code churn, which is what Linus
>>> is really complaining about.
>>
>> I just tested, PXA (mach-pxa) probably can be compiled into single kernel
>> supporting all the boards.
>
> Yes, IIRC Russell and Eric did a huge amount of work to get pxa into
> that state.
>
> ryan at okiwi:configs$ grep "ARCH_PXA=y" * | wc -l
> 25
>
> Can we remove/combine some of those?
>

Definitely. In the end of the day, I would like to see pxa_defconfig only.
But at the moment, I need every board maintainer to review their defconfig
and combine them as much as possible. E.g.

palmte_defconfig   palmtt_defconfig   palmz71_defconfig  palmz72_defconfig

I'd guess can simply combine into one. (Marek, feel free to do it)

I'd more like a step to step work instead of a brutely removal of all defconfig,
not sure if Linus is going to buy in.

For those sub-arch which cannot simply compile a single kernel for multiple
boards, s5p* as previously mentioned, I suggest not to introduce any new
defconfig until the problem is solved.

Also, we are now working on a single kernel for multiple sub-arch (at least
what Nicolas and I am doing now, and welcome to join us). It's tough (the
way to handle different phys_offset is only the tip of the iceberg) and seems
now more and more necessary. so hopefully by the end of the day, we may
possible end up with only very few defconfig.


From marek.vasut at gmail.com  Thu Jun  3 21:37:10 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 4 Jun 2010 03:37:10 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
Message-ID: <201006040337.10593.marek.vasut@gmail.com>

Dne P? 4. ?ervna 2010 03:35:28 Eric Miao napsal(a):
> On Fri, Jun 4, 2010 at 9:16 AM, Ryan Mallon <ryan at bluewatersys.com> wrote:
> > Marek Vasut wrote:
> >> Dne P? 4. ?ervna 2010 01:33:35 Ryan Mallon napsal(a):
> >>> Nicolas Pitre wrote:
> >>>> On Fri, 4 Jun 2010, Ryan Mallon wrote:
> >>>>> Is it worth being a bit proactive and getting rid of some of them in
> >>>>> advance? Things like spear3[012]0_defconfig are basically identically
> >>>>> except for the board type. Combining all three of those would remove
> >>>>> 1500 lines of code.
> >>>> 
> >>>> Please go ahead with a patch.
> >>> 
> >>> Hmm, not as easy as I thought. The three boards cannot be built into a
> >>> single kernel since the arch/arm/mach-spear3xx/spear3[012]0.c files all
> >>> extern a bunch of structs which have naming conflicts.
> >>> 
> >>> It does look possible to rewrite that code so that all three boards can
> >>> be built into a single kernel. I can try and put together a patch, but
> >>> I don't have any hardware to test with.
> >>> 
> >>> The at91 is actually in a similar state, where only one of the
> >>> at91sam9260, at91sam9g45, etc can be selected. Again, it should be
> >>> possible to rework the code so that most of the different cpus can be
> >>> built into a single kernel. I'm sure other mach's are in a simliar
> >>> state. Fixing these where possible would allow us to have single
> >>> defconfigs per mach directory and reduce code churn, which is what
> >>> Linus is really complaining about.
> >> 
> >> I just tested, PXA (mach-pxa) probably can be compiled into single
> >> kernel supporting all the boards.
> > 
> > Yes, IIRC Russell and Eric did a huge amount of work to get pxa into
> > that state.
> > 
> > ryan at okiwi:configs$ grep "ARCH_PXA=y" * | wc -l
> > 25
> > 
> > Can we remove/combine some of those?
> 
> Definitely. In the end of the day, I would like to see pxa_defconfig only.
> But at the moment, I need every board maintainer to review their defconfig
> and combine them as much as possible. E.g.
> 
> palmte_defconfig   palmtt_defconfig   palmz71_defconfig  palmz72_defconfig

This is OMAP stuff, not PXA. But yeah, these could be combined. I don't have 
these devices available at the moment (and it might be a problem getting them 
into operational state).
> 
> I'd guess can simply combine into one. (Marek, feel free to do it)
> 
> I'd more like a step to step work instead of a brutely removal of all
> defconfig, not sure if Linus is going to buy in.
> 
> For those sub-arch which cannot simply compile a single kernel for multiple
> boards, s5p* as previously mentioned, I suggest not to introduce any new
> defconfig until the problem is solved.
> 
> Also, we are now working on a single kernel for multiple sub-arch (at least
> what Nicolas and I am doing now, and welcome to join us). It's tough (the
> way to handle different phys_offset is only the tip of the iceberg) and
> seems now more and more necessary. so hopefully by the end of the day, we
> may possible end up with only very few defconfig.

How long is your day now ?


From jeremy.kerr at canonical.com  Thu Jun  3 21:40:48 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Fri, 4 Jun 2010 09:40:48 +0800
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100603110533.GB7127@n2100.arm.linux.org.uk>
References: <1275479804.137633.565764505843.0.gpush@pororo>
	<201006031824.53832.jeremy.kerr@canonical.com>
	<20100603110533.GB7127@n2100.arm.linux.org.uk>
Message-ID: <201006040940.51776.jeremy.kerr@canonical.com>

Hi Russell,

> Or to put it another way, the above method results in clk_enable()
> sometimes returning with the clock enabled and sometimes with the
> clock still disabled.
> 
> That's not nice behaviour for drivers which may need the clock enabled
> to read/write the device registers.

OK, I'll rework with proper locking to ensure that the clock is 
enabled/disabled on return from clk_enable.

Cheers,


Jeremy


From jeremy.kerr at canonical.com  Thu Jun  3 21:43:31 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Fri, 4 Jun 2010 09:43:31 +0800
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100604000605.GF4720@trinity.fluff.org>
References: <1275479804.137633.565764505843.0.gpush@pororo>
	<20100603110533.GB7127@n2100.arm.linux.org.uk>
	<20100604000605.GF4720@trinity.fluff.org>
Message-ID: <201006040943.32527.jeremy.kerr@canonical.com>

Hi Ben,

> As an addendum to Russell's comments, we need to specify the behaviour
> with resepect to what happens about clock stabilisation as well, if the
> clock we enabled takes time to stabilise, then should we wait?

Yes. If we're going to the effort of ensuring that the clock is enabled before 
clk_enable returns, we should also guarantee that the clock is fully-
functional.

If that takes some time, then that's just the cost of ensuring correct 
behaviour.

Cheers,


Jeremy


From marek.vasut at gmail.com  Thu Jun  3 21:50:36 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 4 Jun 2010 03:50:36 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006040337.10593.marek.vasut@gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<201006040337.10593.marek.vasut@gmail.com>
Message-ID: <201006040350.36944.marek.vasut@gmail.com>

Dne P? 4. ?ervna 2010 03:37:10 Marek Vasut napsal(a):
> Dne P? 4. ?ervna 2010 03:35:28 Eric Miao napsal(a):
> > On Fri, Jun 4, 2010 at 9:16 AM, Ryan Mallon <ryan at bluewatersys.com> wrote:
> > > Marek Vasut wrote:
> > >> Dne P? 4. ?ervna 2010 01:33:35 Ryan Mallon napsal(a):
> > >>> Nicolas Pitre wrote:
> > >>>> On Fri, 4 Jun 2010, Ryan Mallon wrote:
> > >>>>> Is it worth being a bit proactive and getting rid of some of them
> > >>>>> in advance? Things like spear3[012]0_defconfig are basically
> > >>>>> identically except for the board type. Combining all three of
> > >>>>> those would remove 1500 lines of code.
> > >>>> 
> > >>>> Please go ahead with a patch.
> > >>> 
> > >>> Hmm, not as easy as I thought. The three boards cannot be built into
> > >>> a single kernel since the arch/arm/mach-spear3xx/spear3[012]0.c
> > >>> files all extern a bunch of structs which have naming conflicts.
> > >>> 
> > >>> It does look possible to rewrite that code so that all three boards
> > >>> can be built into a single kernel. I can try and put together a
> > >>> patch, but I don't have any hardware to test with.
> > >>> 
> > >>> The at91 is actually in a similar state, where only one of the
> > >>> at91sam9260, at91sam9g45, etc can be selected. Again, it should be
> > >>> possible to rework the code so that most of the different cpus can be
> > >>> built into a single kernel. I'm sure other mach's are in a simliar
> > >>> state. Fixing these where possible would allow us to have single
> > >>> defconfigs per mach directory and reduce code churn, which is what
> > >>> Linus is really complaining about.
> > >> 
> > >> I just tested, PXA (mach-pxa) probably can be compiled into single
> > >> kernel supporting all the boards.
> > > 
> > > Yes, IIRC Russell and Eric did a huge amount of work to get pxa into
> > > that state.
> > > 
> > > ryan at okiwi:configs$ grep "ARCH_PXA=y" * | wc -l
> > > 25
> > > 
> > > Can we remove/combine some of those?
> > 
> > Definitely. In the end of the day, I would like to see pxa_defconfig
> > only. But at the moment, I need every board maintainer to review their
> > defconfig and combine them as much as possible. E.g.
> > 
> > palmte_defconfig   palmtt_defconfig   palmz71_defconfig 
> > palmz72_defconfig
> 

OMAP: palmte_defconfig, palmtt_defconfig, palmz71_defconfig
PXA: palmz72_defconfig ... the rest of palmxx_defconfig

Sorry about the confusion

> This is OMAP stuff, not PXA. But yeah, these could be combined. I don't
> have these devices available at the moment (and it might be a problem
> getting them into operational state).
> 
> > I'd guess can simply combine into one. (Marek, feel free to do it)
> > 
> > I'd more like a step to step work instead of a brutely removal of all
> > defconfig, not sure if Linus is going to buy in.
> > 
> > For those sub-arch which cannot simply compile a single kernel for
> > multiple boards, s5p* as previously mentioned, I suggest not to
> > introduce any new defconfig until the problem is solved.
> > 
> > Also, we are now working on a single kernel for multiple sub-arch (at
> > least what Nicolas and I am doing now, and welcome to join us). It's
> > tough (the way to handle different phys_offset is only the tip of the
> > iceberg) and seems now more and more necessary. so hopefully by the end
> > of the day, we may possible end up with only very few defconfig.
> 
> How long is your day now ?


From marek.vasut at gmail.com  Thu Jun  3 21:53:35 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 4 Jun 2010 03:53:35 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006040350.36944.marek.vasut@gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<201006040337.10593.marek.vasut@gmail.com>
	<201006040350.36944.marek.vasut@gmail.com>
Message-ID: <201006040353.35816.marek.vasut@gmail.com>

Dne P? 4. ?ervna 2010 03:50:36 Marek Vasut napsal(a):
> Dne P? 4. ?ervna 2010 03:37:10 Marek Vasut napsal(a):
> > Dne P? 4. ?ervna 2010 03:35:28 Eric Miao napsal(a):
> > > On Fri, Jun 4, 2010 at 9:16 AM, Ryan Mallon <ryan at bluewatersys.com> wrote:
> > > > Marek Vasut wrote:
> > > >> Dne P? 4. ?ervna 2010 01:33:35 Ryan Mallon napsal(a):
> > > >>> Nicolas Pitre wrote:
> > > >>>> On Fri, 4 Jun 2010, Ryan Mallon wrote:
> > > >>>>> Is it worth being a bit proactive and getting rid of some of them
> > > >>>>> in advance? Things like spear3[012]0_defconfig are basically
> > > >>>>> identically except for the board type. Combining all three of
> > > >>>>> those would remove 1500 lines of code.
> > > >>>> 
> > > >>>> Please go ahead with a patch.
> > > >>> 
> > > >>> Hmm, not as easy as I thought. The three boards cannot be built
> > > >>> into a single kernel since the
> > > >>> arch/arm/mach-spear3xx/spear3[012]0.c files all extern a bunch of
> > > >>> structs which have naming conflicts.
> > > >>> 
> > > >>> It does look possible to rewrite that code so that all three boards
> > > >>> can be built into a single kernel. I can try and put together a
> > > >>> patch, but I don't have any hardware to test with.
> > > >>> 
> > > >>> The at91 is actually in a similar state, where only one of the
> > > >>> at91sam9260, at91sam9g45, etc can be selected. Again, it should be
> > > >>> possible to rework the code so that most of the different cpus can
> > > >>> be built into a single kernel. I'm sure other mach's are in a
> > > >>> simliar state. Fixing these where possible would allow us to have
> > > >>> single defconfigs per mach directory and reduce code churn, which
> > > >>> is what Linus is really complaining about.
> > > >> 
> > > >> I just tested, PXA (mach-pxa) probably can be compiled into single
> > > >> kernel supporting all the boards.
> > > > 
> > > > Yes, IIRC Russell and Eric did a huge amount of work to get pxa into
> > > > that state.
> > > > 
> > > > ryan at okiwi:configs$ grep "ARCH_PXA=y" * | wc -l
> > > > 25
> > > > 
> > > > Can we remove/combine some of those?
> > > 
> > > Definitely. In the end of the day, I would like to see pxa_defconfig
> > > only. But at the moment, I need every board maintainer to review their
> > > defconfig and combine them as much as possible. E.g.
> > > 
> > > palmte_defconfig   palmtt_defconfig   palmz71_defconfig
> > > palmz72_defconfig
> 
> OMAP: palmte_defconfig, palmtt_defconfig, palmz71_defconfig

Ok, making them into one is compile tested. I'd be for calling it a 
"palmomap_defconfig". Or maybe is there a plan to put whole OMAP1 into a single 
defconfig ?

> PXA: palmz72_defconfig ... the rest of palmxx_defconfig
> 
> Sorry about the confusion
> 
> > This is OMAP stuff, not PXA. But yeah, these could be combined. I don't
> > have these devices available at the moment (and it might be a problem
> > getting them into operational state).
> > 
> > > I'd guess can simply combine into one. (Marek, feel free to do it)
> > > 
> > > I'd more like a step to step work instead of a brutely removal of all
> > > defconfig, not sure if Linus is going to buy in.
> > > 
> > > For those sub-arch which cannot simply compile a single kernel for
> > > multiple boards, s5p* as previously mentioned, I suggest not to
> > > introduce any new defconfig until the problem is solved.
> > > 
> > > Also, we are now working on a single kernel for multiple sub-arch (at
> > > least what Nicolas and I am doing now, and welcome to join us). It's
> > > tough (the way to handle different phys_offset is only the tip of the
> > > iceberg) and seems now more and more necessary. so hopefully by the end
> > > of the day, we may possible end up with only very few defconfig.
> > 
> > How long is your day now ?


From eric.y.miao at gmail.com  Thu Jun  3 21:57:07 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 4 Jun 2010 09:57:07 +0800
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006040337.10593.marek.vasut@gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk> 
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com> 
	<201006040337.10593.marek.vasut@gmail.com>
Message-ID: <AANLkTikn7NY1qwmQX-pbCKLR508AJ4eZ5nyzEA1HD6pe@mail.gmail.com>

On Fri, Jun 4, 2010 at 9:37 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dne P? 4. ?ervna 2010 03:35:28 Eric Miao napsal(a):
>> On Fri, Jun 4, 2010 at 9:16 AM, Ryan Mallon <ryan at bluewatersys.com> wrote:
>> > Marek Vasut wrote:
>> >> Dne P? 4. ?ervna 2010 01:33:35 Ryan Mallon napsal(a):
>> >>> Nicolas Pitre wrote:
>> >>>> On Fri, 4 Jun 2010, Ryan Mallon wrote:
>> >>>>> Is it worth being a bit proactive and getting rid of some of them in
>> >>>>> advance? Things like spear3[012]0_defconfig are basically identically
>> >>>>> except for the board type. Combining all three of those would remove
>> >>>>> 1500 lines of code.
>> >>>>
>> >>>> Please go ahead with a patch.
>> >>>
>> >>> Hmm, not as easy as I thought. The three boards cannot be built into a
>> >>> single kernel since the arch/arm/mach-spear3xx/spear3[012]0.c files all
>> >>> extern a bunch of structs which have naming conflicts.
>> >>>
>> >>> It does look possible to rewrite that code so that all three boards can
>> >>> be built into a single kernel. I can try and put together a patch, but
>> >>> I don't have any hardware to test with.
>> >>>
>> >>> The at91 is actually in a similar state, where only one of the
>> >>> at91sam9260, at91sam9g45, etc can be selected. Again, it should be
>> >>> possible to rework the code so that most of the different cpus can be
>> >>> built into a single kernel. I'm sure other mach's are in a simliar
>> >>> state. Fixing these where possible would allow us to have single
>> >>> defconfigs per mach directory and reduce code churn, which is what
>> >>> Linus is really complaining about.
>> >>
>> >> I just tested, PXA (mach-pxa) probably can be compiled into single
>> >> kernel supporting all the boards.
>> >
>> > Yes, IIRC Russell and Eric did a huge amount of work to get pxa into
>> > that state.
>> >
>> > ryan at okiwi:configs$ grep "ARCH_PXA=y" * | wc -l
>> > 25
>> >
>> > Can we remove/combine some of those?
>>
>> Definitely. In the end of the day, I would like to see pxa_defconfig only.
>> But at the moment, I need every board maintainer to review their defconfig
>> and combine them as much as possible. E.g.
>>
>> palmte_defconfig ? palmtt_defconfig ? palmz71_defconfig ?palmz72_defconfig
>
> This is OMAP stuff, not PXA. But yeah, these could be combined. I don't have
> these devices available at the moment (and it might be a problem getting them
> into operational state).
>>
>> I'd guess can simply combine into one. (Marek, feel free to do it)
>>
>> I'd more like a step to step work instead of a brutely removal of all
>> defconfig, not sure if Linus is going to buy in.
>>
>> For those sub-arch which cannot simply compile a single kernel for multiple
>> boards, s5p* as previously mentioned, I suggest not to introduce any new
>> defconfig until the problem is solved.
>>
>> Also, we are now working on a single kernel for multiple sub-arch (at least
>> what Nicolas and I am doing now, and welcome to join us). It's tough (the
>> way to handle different phys_offset is only the tip of the iceberg) and
>> seems now more and more necessary. so hopefully by the end of the day, we
>> may possible end up with only very few defconfig.
>
> How long is your day now ?
>

In the end of the day, sorry, it's a very long. You know English is not my
tongue ;-)


From ryan at bluewatersys.com  Fri Jun  4 01:11:22 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Fri,  4 Jun 2010 17:11:22 +1200
Subject: [RFC PATCH v3 0/3] ep93xx i2s audio
Message-ID: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>

The following patch series adds support for i2s audio on the ep93xx,
with the Snapper CL15 used as an example implementation.

This version fixes a number of things from the previous round:
 - Removed unused #defines
 - Set symmetric rates for the cpu dai
 - Fixed the sdiv/lrdiv calculation loop
 - Moved the cpu dai registration
 - Removed empty ep93xx_pcm_prepare callback
 - Fixed enable/disable when both capture and playback are running
 
Capture still does not work. The dma is running, but the captured data
is all zeros (tested used arecord and loopback). I have a 2.6.20
kernel with ep93xx i2s audio working an capture works there on the
same hardware. I have spent sometime looking into this, but can't see
the problem. Would appreciate if someone can lend some insight as to
what I have done wrong.

Ryan Mallon (3):
  ep93xx i2s core support
  ep93xx i2s audio driver
  Snapper cl15 audio support

 arch/arm/mach-ep93xx/clock.c                    |   69 ++++-
 arch/arm/mach-ep93xx/core.c                     |   31 ++
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |   10 +
 arch/arm/mach-ep93xx/include/mach/platform.h    |    1 +
 arch/arm/mach-ep93xx/snappercl15.c              |    1 +
 sound/soc/Kconfig                               |    1 +
 sound/soc/Makefile                              |    1 +
 sound/soc/ep93xx/Kconfig                        |   18 +
 sound/soc/ep93xx/Makefile                       |   11 +
 sound/soc/ep93xx/ep93xx-i2s.c                   |  487 +++++++++++++++++++++++
 sound/soc/ep93xx/ep93xx-i2s.h                   |   18 +
 sound/soc/ep93xx/ep93xx-pcm.c                   |  319 +++++++++++++++
 sound/soc/ep93xx/ep93xx-pcm.h                   |   22 +
 sound/soc/ep93xx/snappercl15.c                  |  143 +++++++
 14 files changed, 1131 insertions(+), 1 deletions(-)
 create mode 100644 sound/soc/ep93xx/Kconfig
 create mode 100644 sound/soc/ep93xx/Makefile
 create mode 100644 sound/soc/ep93xx/ep93xx-i2s.c
 create mode 100644 sound/soc/ep93xx/ep93xx-i2s.h
 create mode 100644 sound/soc/ep93xx/ep93xx-pcm.c
 create mode 100644 sound/soc/ep93xx/ep93xx-pcm.h
 create mode 100644 sound/soc/ep93xx/snappercl15.c



From ryan at bluewatersys.com  Fri Jun  4 01:11:23 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Fri,  4 Jun 2010 17:11:23 +1200
Subject: [RFC PATCH v3 1/3] ep93xx i2s core support
In-Reply-To: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
References: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1275628285-12642-2-git-send-email-ryan@bluewatersys.com>

Add ep93xx core support for i2s audio

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-ep93xx/clock.c                    |   69 ++++++++++++++++++++++-
 arch/arm/mach-ep93xx/core.c                     |   31 ++++++++++
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |   10 +++
 arch/arm/mach-ep93xx/include/mach/platform.h    |    1 +
 4 files changed, 110 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 5f80092..503d430 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -43,7 +43,8 @@ static unsigned long get_uart_rate(struct clk *clk);
 
 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
 static int set_div_rate(struct clk *clk, unsigned long rate);
-
+static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
+static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
 
 static struct clk clk_xtali = {
 	.rate		= EP93XX_EXT_CLK_RATE,
@@ -108,6 +109,31 @@ static struct clk clk_video = {
 	.set_rate	= set_div_rate,
 };
 
+static struct clk clk_i2s_mclk = {
+	.sw_locked	= 1,
+	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
+	.enable_mask	= (EP93XX_SYSCON_CLKDIV_ENABLE  |
+			   EP93XX_SYSCON_I2SCLKDIV_SPOL |
+			   EP93XX_SYSCON_I2SCLKDIV_ORIDE),
+	.set_rate	= set_div_rate,
+};
+
+static struct clk clk_i2s_sclk = {
+	.sw_locked	= 1,
+	.parent		= &clk_i2s_mclk,
+	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
+	.enable_mask	= EP93XX_SYSCON_I2SCLKDIV_SENA,
+	.set_rate	= set_i2s_sclk_rate,
+};
+
+static struct clk clk_i2s_lrclk = {
+	.sw_locked	= 1,
+	.parent		= &clk_i2s_sclk,
+	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
+	.enable_mask	= EP93XX_SYSCON_I2SCLKDIV_SENA,
+	.set_rate	= set_i2s_lrclk_rate,
+};
+
 /* DMA Clocks */
 static struct clk clk_m2p0 = {
 	.parent		= &clk_h,
@@ -186,6 +212,9 @@ static struct clk_lookup clocks[] = {
 	INIT_CK("ep93xx-ohci",		NULL,		&clk_usb_host),
 	INIT_CK("ep93xx-keypad",	NULL,		&clk_keypad),
 	INIT_CK("ep93xx-fb",		NULL,		&clk_video),
+	INIT_CK("ep93xx-i2s",		"mclk",		&clk_i2s_mclk),
+	INIT_CK("ep93xx-i2s",		"sclk",		&clk_i2s_sclk),
+	INIT_CK("ep93xx-i2s",		"lrclk",	&clk_i2s_lrclk),
 	INIT_CK(NULL,			"pwm_clk",	&clk_pwm),
 	INIT_CK(NULL,			"m2p0",		&clk_m2p0),
 	INIT_CK(NULL,			"m2p1",		&clk_m2p1),
@@ -396,6 +425,44 @@ static int set_div_rate(struct clk *clk, unsigned long rate)
 	return 0;
 }
 
+static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned val = __raw_readl(clk->enable_reg);
+
+	if (rate == clk_i2s_mclk.rate / 2)
+		ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV, 
+					     clk->enable_reg);
+	else if (rate == clk_i2s_mclk.rate / 4)
+		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV, 
+					     clk->enable_reg);
+	else
+		return -EINVAL;
+
+	clk_i2s_sclk.rate = rate;
+	return 0;
+}
+
+static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned val = __raw_readl(clk->enable_reg) & 
+		~EP93XX_I2SCLKDIV_LRDIV_MASK;
+	
+	if (rate == clk_i2s_sclk.rate / 32)
+		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32,
+					     clk->enable_reg);
+	else if (rate == clk_i2s_sclk.rate / 64)
+		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64,
+					     clk->enable_reg);
+	else if (rate == clk_i2s_sclk.rate / 128)
+		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128,
+					     clk->enable_reg);
+	else
+		return -EINVAL;
+
+	clk_i2s_lrclk.rate = rate;
+	return 0;
+}
+
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
 	if (clk->set_rate)
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 90fb591..c04fd6f 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -617,6 +617,37 @@ void ep93xx_keypad_release_gpio(struct platform_device *pdev)
 }
 EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
 
+/*************************************************************************
+ * EP93xx I2S audio peripheral handling
+ *************************************************************************/
+static struct resource ep93xx_i2s_resource[] = {
+	{
+		.start	= EP93XX_I2S_PHYS_BASE,
+		.end	= EP93XX_I2S_PHYS_BASE + 0x100 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device ep93xx_i2s_device = {
+	.name		= "ep93xx-i2s",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(ep93xx_i2s_resource),
+	.resource	= ep93xx_i2s_resource,
+};
+
+void __init ep93xx_register_i2s(unsigned pins)
+{
+	if (pins != EP93XX_SYSCON_DEVCFG_I2SONSSP &&
+	    pins != EP93XX_SYSCON_DEVCFG_I2SONAC97) {
+		pr_err("Invalid I2S pin configuration - not registering\n");
+		return;
+	}
+
+	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP |
+				 EP93XX_SYSCON_DEVCFG_I2SONAC97);
+	ep93xx_devcfg_set_bits(pins);
+	platform_device_register(&ep93xx_i2s_device);
+}
 
 extern void ep93xx_gpio_init(void);
 
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 93e2ecc..3fbb095 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -93,6 +93,7 @@
 /* APB peripherals */
 #define EP93XX_TIMER_BASE		EP93XX_APB_IOMEM(0x00010000)
 
+#define EP93XX_I2S_PHYS_BASE		EP93XX_APB_PHYS(0x00020000)
 #define EP93XX_I2S_BASE			EP93XX_APB_IOMEM(0x00020000)
 
 #define EP93XX_SECURITY_BASE		EP93XX_APB_IOMEM(0x00030000)
@@ -193,6 +194,15 @@
 #define EP93XX_SYSCON_CLKDIV_ESEL	(1<<14)
 #define EP93XX_SYSCON_CLKDIV_PSEL	(1<<13)
 #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT	8
+#define EP93XX_SYSCON_I2SCLKDIV		EP93XX_SYSCON_REG(0x8c)
+#define EP93XX_SYSCON_I2SCLKDIV_SENA	(1<<31)
+#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
+#define EP93XX_SYSCON_I2SCLKDIV_SPOL	(1<<19)
+#define EP93XX_I2SCLKDIV_SDIV		(1 << 16)
+#define EP93XX_I2SCLKDIV_LRDIV32	(0 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV64	(1 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV128 	(2 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV_MASK 	(3 << 17)
 #define EP93XX_SYSCON_KEYTCHCLKDIV	EP93XX_SYSCON_REG(0x90)
 #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	(1<<31)
 #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	(1<<16)
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index c6dc14d..9252adf 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -43,6 +43,7 @@ void ep93xx_pwm_release_gpio(struct platform_device *pdev);
 void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data);
 int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
 void ep93xx_keypad_release_gpio(struct platform_device *pdev);
+void ep93xx_register_i2s(unsigned pins);
 
 void ep93xx_init_devices(void);
 extern struct sys_timer ep93xx_timer;
-- 
1.5.5.1



From ryan at bluewatersys.com  Fri Jun  4 01:11:24 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Fri,  4 Jun 2010 17:11:24 +1200
Subject: [RFC PATCH v3 2/3] ep93xx i2s audio driver
In-Reply-To: <1275628285-12642-2-git-send-email-ryan@bluewatersys.com>
References: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
	<1275628285-12642-2-git-send-email-ryan@bluewatersys.com>
Message-ID: <1275628285-12642-3-git-send-email-ryan@bluewatersys.com>

Add ep93xx i2s audio driver

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 sound/soc/Kconfig             |    1 +
 sound/soc/Makefile            |    1 +
 sound/soc/ep93xx/Kconfig      |    9 +
 sound/soc/ep93xx/Makefile     |    8 +
 sound/soc/ep93xx/ep93xx-i2s.c |  487 +++++++++++++++++++++++++++++++++++++++++
 sound/soc/ep93xx/ep93xx-i2s.h |   18 ++
 sound/soc/ep93xx/ep93xx-pcm.c |  319 +++++++++++++++++++++++++++
 sound/soc/ep93xx/ep93xx-pcm.h |   22 ++
 8 files changed, 865 insertions(+), 0 deletions(-)
 create mode 100644 sound/soc/ep93xx/Kconfig
 create mode 100644 sound/soc/ep93xx/Makefile
 create mode 100644 sound/soc/ep93xx/ep93xx-i2s.c
 create mode 100644 sound/soc/ep93xx/ep93xx-i2s.h
 create mode 100644 sound/soc/ep93xx/ep93xx-pcm.c
 create mode 100644 sound/soc/ep93xx/ep93xx-pcm.h

diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index b1749bc..f7cb451 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -28,6 +28,7 @@ source "sound/soc/atmel/Kconfig"
 source "sound/soc/au1x/Kconfig"
 source "sound/soc/blackfin/Kconfig"
 source "sound/soc/davinci/Kconfig"
+source "sound/soc/ep93xx/Kconfig"
 source "sound/soc/fsl/Kconfig"
 source "sound/soc/imx/Kconfig"
 source "sound/soc/omap/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 1470141..55b711a 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SND_SOC)	+= atmel/
 obj-$(CONFIG_SND_SOC)	+= au1x/
 obj-$(CONFIG_SND_SOC)	+= blackfin/
 obj-$(CONFIG_SND_SOC)	+= davinci/
+obj-$(CONFIG_SND_SOC)	+= ep93xx/
 obj-$(CONFIG_SND_SOC)	+= fsl/
 obj-$(CONFIG_SND_SOC)   += imx/
 obj-$(CONFIG_SND_SOC)	+= omap/
diff --git a/sound/soc/ep93xx/Kconfig b/sound/soc/ep93xx/Kconfig
new file mode 100644
index 0000000..ba66ac8
--- /dev/null
+++ b/sound/soc/ep93xx/Kconfig
@@ -0,0 +1,9 @@
+config SND_EP93XX_SOC
+	tristate "SoC Audio support for the Cirrus Logic EP93xx series"
+	depends on ARCH_EP93XX && SND_SOC
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the EP93xx I2S interface.
+
+config SND_EP93XX_SOC_I2S
+	tristate
diff --git a/sound/soc/ep93xx/Makefile b/sound/soc/ep93xx/Makefile
new file mode 100644
index 0000000..0239da3
--- /dev/null
+++ b/sound/soc/ep93xx/Makefile
@@ -0,0 +1,8 @@
+# EP93xx Platform Support
+snd-soc-ep93xx-objs				:= ep93xx-pcm.o
+snd-soc-ep93xx-i2s-objs	 			:= ep93xx-i2s.o
+
+obj-$(CONFIG_SND_EP93XX_SOC)			+= snd-soc-ep93xx.o
+obj-$(CONFIG_SND_EP93XX_SOC_I2S)		+= snd-soc-ep93xx-i2s.o
+
+# EP93XX Machine Support
diff --git a/sound/soc/ep93xx/ep93xx-i2s.c b/sound/soc/ep93xx/ep93xx-i2s.c
new file mode 100644
index 0000000..00b9466
--- /dev/null
+++ b/sound/soc/ep93xx/ep93xx-i2s.c
@@ -0,0 +1,487 @@
+/*
+ * linux/sound/soc/ep93xx-i2s.c
+ * EP93xx I2S driver
+ *
+ * Copyright (C) 2010 Ryan Mallon <ryan at bluewatersys.com>
+ *
+ * Based on the original driver by:
+ *   Copyright (C) 2007 Chase Douglas <chasedouglas at gmail>
+ *   Copyright (C) 2006 Lennert Buytenhek <buytenh at wantstofly.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/initval.h>
+#include <sound/soc.h>
+
+#include <mach/hardware.h>
+#include <mach/ep93xx-regs.h>
+#include <mach/dma.h>
+
+#include "ep93xx-pcm.h"
+#include "ep93xx-i2s.h"
+
+#define EP93XX_I2S_TXCLKCFG		0x00
+#define EP93XX_I2S_RXCLKCFG		0x04
+#define EP93XX_I2S_GLCTRL		0x0C
+
+#define EP93XX_I2S_TXLINCTRLDATA	0x28
+#define EP93XX_I2S_TXCTRL		0x2C
+#define EP93XX_I2S_TXWRDLEN		0x30
+#define EP93XX_I2S_TX0EN		0x34
+
+#define EP93XX_I2S_RXLINCTRLDATA	0x58
+#define EP93XX_I2S_RXCTRL		0x5C
+#define EP93XX_I2S_RXWRDLEN		0x60
+#define EP93XX_I2S_RX0EN		0x64
+
+#define EP93XX_I2S_WRDLEN_16		(0 << 0)
+#define EP93XX_I2S_WRDLEN_24		(1 << 0)
+#define EP93XX_I2S_WRDLEN_32		(2 << 0)
+
+#define EP93XX_I2S_LINCTRLDATA_R_JUST	(1 << 2) /* Right justify */
+
+#define EP93XX_I2S_CLKCFG_LRS		(1 << 0) /* lrclk polarity */
+#define EP93XX_I2S_CLKCFG_CKP		(1 << 1) /* Bit clock polarity */
+#define EP93XX_I2S_CLKCFG_REL		(1 << 2) /* First bit transition */
+#define EP93XX_I2S_CLKCFG_MASTER	(1 << 3) /* Master mode */
+#define EP93XX_I2S_CLKCFG_NBCG		(1 << 4) /* Not bit clock gating */
+
+struct ep93xx_i2s_info {
+	struct clk			*mclk;
+	struct clk			*sclk;
+	struct clk			*lrclk;
+	struct ep93xx_pcm_dma_params	*dma_params;
+	struct resource			*mem;
+	void __iomem			*regs;
+};
+
+struct ep93xx_pcm_dma_params ep93xx_i2s_dma_params[] = {
+	[SNDRV_PCM_STREAM_PLAYBACK] = {
+		.name		= "i2s-pcm-out",
+		.dma_port	= EP93XX_DMA_M2P_PORT_I2S1,
+	},
+	[SNDRV_PCM_STREAM_CAPTURE] = {
+		.name		= "i2s-pcm-in",
+		.dma_port	= EP93XX_DMA_M2P_PORT_I2S1,
+	},
+};
+
+static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
+					unsigned reg, unsigned val)
+{
+	__raw_writel(val, info->regs + reg);
+}
+
+static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
+					   unsigned reg)
+{
+	return __raw_readl(info->regs + reg);
+}
+
+static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
+{
+	unsigned base_reg;
+	int i;
+
+	if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
+	    (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
+		/* Enable clocks */
+		clk_enable(info->mclk);
+		clk_enable(info->sclk);
+		clk_enable(info->lrclk);
+
+		/* Enable i2s */
+		ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
+	}
+
+	/* Enable fifos */
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+		base_reg = EP93XX_I2S_TX0EN;
+	else
+		base_reg = EP93XX_I2S_RX0EN;
+	for (i = 0; i < 3; i++)
+		ep93xx_i2s_write_reg(info, base_reg + (i * 4), 1);
+}
+
+static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
+{
+	unsigned base_reg;
+	int i;
+
+	/* Disable fifos */
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+		base_reg = EP93XX_I2S_TX0EN;
+	else
+		base_reg = EP93XX_I2S_RX0EN;
+	for (i = 0; i < 3; i++)
+		ep93xx_i2s_write_reg(info, base_reg + (i * 4), 0);
+
+	if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
+	    (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
+		/* Disable i2s */
+		ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
+
+		/* Disable clocks */
+		clk_disable(info->lrclk);
+		clk_disable(info->sclk);
+		clk_disable(info->mclk);
+	}
+}
+
+static int ep93xx_i2s_startup(struct snd_pcm_substream *substream,
+			      struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct ep93xx_i2s_info *info = rtd->dai->cpu_dai->private_data;
+
+	snd_soc_dai_set_dma_data(cpu_dai, substream,
+				 &info->dma_params[substream->stream]);
+	return 0;
+}
+
+static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
+				struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct ep93xx_i2s_info *info = rtd->dai->cpu_dai->private_data;
+
+	ep93xx_i2s_disable(info, substream->stream);
+}
+
+static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
+				  unsigned int fmt)
+{
+	struct ep93xx_i2s_info *info = cpu_dai->private_data;
+	unsigned int clk_cfg, lin_ctrl;
+
+	clk_cfg  = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
+	lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);
+
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_I2S:
+		clk_cfg |= EP93XX_I2S_CLKCFG_REL;
+		lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
+		break;
+
+	case SND_SOC_DAIFMT_LEFT_J:
+		clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
+		lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
+		break;
+
+	case SND_SOC_DAIFMT_RIGHT_J:
+		clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
+		lin_ctrl |= EP93XX_I2S_LINCTRLDATA_R_JUST;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBS_CFS:
+		/* CPU is master */
+		clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
+		break;
+
+	case SND_SOC_DAIFMT_CBM_CFM:
+		/* Codec is master */
+		clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+	case SND_SOC_DAIFMT_NB_NF:
+		/* Negative bit clock, lrclk low on left word */
+		clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL);
+		break;
+
+	case SND_SOC_DAIFMT_NB_IF:
+		/* Negative bit clock, lrclk low on right word */
+		clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
+		clk_cfg |= EP93XX_I2S_CLKCFG_REL;
+		break;
+
+	case SND_SOC_DAIFMT_IB_NF:
+		/* Positive bit clock, lrclk low on left word */
+		clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
+		clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
+		break;
+
+	case SND_SOC_DAIFMT_IB_IF:
+		/* Positive bit clock, lrclk low on right word */
+		clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL;
+		break;
+	}
+
+	/* Write new register values */
+	ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
+	ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
+	ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl);
+	ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl);
+	return 0;
+}
+
+static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params,
+				struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct ep93xx_i2s_info *info = cpu_dai->private_data;
+	unsigned word_len, div, sdiv, lrdiv;
+	int found = 0, err;
+
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+		word_len = EP93XX_I2S_WRDLEN_16;
+		break;
+
+	case SNDRV_PCM_FORMAT_S24_LE:
+		word_len = EP93XX_I2S_WRDLEN_24;
+		break;
+
+	case SNDRV_PCM_FORMAT_S32_LE:
+		word_len = EP93XX_I2S_WRDLEN_32;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
+	else
+		ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
+
+	/*
+	 * Calculate the sdiv (bit clock) and lrdiv (left/right clock) values.
+	 * If the lrclk is pulse length is larger than the word size, then the
+	 * bit clock will be gated for the unused bits.
+	 */
+	div = (clk_get_rate(info->mclk) / params_rate(params)) *
+		params_channels(params);
+	for (sdiv = 2; sdiv <= 4; sdiv += 2)
+		for (lrdiv = 32; lrdiv <= 128; lrdiv <<= 1)
+			if (sdiv * lrdiv == div) {
+				found = 1;
+				goto out;
+			}
+out:
+	if (!found)
+		return -EINVAL;
+
+	err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
+	if (err)
+		return err;
+
+	err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
+	if (err)
+		return err;
+
+	ep93xx_i2s_enable(info, substream->stream);
+	return 0;
+}
+
+static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
+				 unsigned int freq, int dir)
+{
+	struct ep93xx_i2s_info *info = cpu_dai->private_data;
+
+	if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
+		return -EINVAL;
+
+	return clk_set_rate(info->mclk, freq);
+}
+
+#ifdef CONFIG_PM
+static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
+{
+	struct ep93xx_i2s_info *info = dai->private_data;
+
+	if (!dai->active)
+		return;
+
+	ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
+	ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
+}
+
+static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
+{
+	struct ep93xx_i2s_info *info = dai->private_data;
+
+	if (!dai->active)
+		return;
+
+	ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
+	ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
+}
+#else
+#define ep93xx_i2s_suspend	NULL
+#define ep93xx_i2s_resume	NULL
+#endif
+
+static struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
+	.startup	= ep93xx_i2s_startup,
+	.shutdown	= ep93xx_i2s_shutdown,
+	.hw_params	= ep93xx_i2s_hw_params,
+	.set_sysclk	= ep93xx_i2s_set_sysclk,
+	.set_fmt	= ep93xx_i2s_set_dai_fmt,
+};
+
+#define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+			    SNDRV_PCM_FMTBIT_S24_LE | \
+			    SNDRV_PCM_FMTBIT_S32_LE)
+
+struct snd_soc_dai ep93xx_i2s_dai = {
+	.name		= "ep93xx-i2s",
+	.id		= 0,
+	.symmetric_rates= 1,
+	.suspend	= ep93xx_i2s_suspend,
+	.resume		= ep93xx_i2s_resume,
+	.playback	= {
+		.channels_min	= 2,
+		.channels_max	= 2,
+		.rates		= SNDRV_PCM_RATE_8000_48000,
+		.formats	= EP93XX_I2S_FORMATS,
+	},
+	.capture	= {
+		 .channels_min	= 2,
+		 .channels_max	= 2,
+		 .rates		= SNDRV_PCM_RATE_8000_48000,
+		 .formats	= EP93XX_I2S_FORMATS,
+	},
+	.ops		= &ep93xx_i2s_dai_ops,
+};
+EXPORT_SYMBOL_GPL(ep93xx_i2s_dai);
+
+static int ep93xx_i2s_probe(struct platform_device *pdev)
+{
+	struct ep93xx_i2s_info *info;
+	struct resource *res;
+	int err;
+
+	info = kzalloc(sizeof(struct ep93xx_i2s_info), GFP_KERNEL);
+	if (!info) {
+		err = -ENOMEM;
+		goto fail;
+	}
+
+	ep93xx_i2s_dai.dev = &pdev->dev;
+	ep93xx_i2s_dai.private_data = info;
+	info->dma_params = ep93xx_i2s_dma_params;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		err = -ENODEV;
+		goto fail;
+	}
+
+	info->mem = request_mem_region(res->start, resource_size(res),
+				       pdev->name);
+	if (!info->mem) {
+		err = -EBUSY;
+		goto fail;
+	}
+
+	info->regs = ioremap(info->mem->start, resource_size(info->mem));
+	if (!info->regs) {
+		err = -ENXIO;
+		goto fail_release_mem;
+	}
+
+	info->mclk = clk_get(&pdev->dev, "mclk");
+	if (IS_ERR(info->mclk)) {
+		err = PTR_ERR(info->mclk);
+		goto fail_unmap_mem;
+	}
+
+	info->sclk = clk_get(&pdev->dev, "sclk");
+	if (IS_ERR(info->sclk)) {
+		err = PTR_ERR(info->sclk);
+		goto fail_put_mclk;
+	}
+
+	info->lrclk = clk_get(&pdev->dev, "lrclk");
+	if (IS_ERR(info->lrclk)) {
+		err = PTR_ERR(info->lrclk);
+		goto fail_put_sclk;
+	}
+
+	err = snd_soc_register_dai(&ep93xx_i2s_dai);
+	if (err)
+		goto fail_put_lrclk;
+
+	return 0;
+
+fail_put_lrclk:
+	clk_put(info->lrclk);
+fail_put_sclk:
+	clk_put(info->sclk);
+fail_put_mclk:
+	clk_put(info->mclk);
+fail_unmap_mem:
+	iounmap(info->regs);
+fail_release_mem:
+	release_mem_region(info->mem->start, resource_size(info->mem));
+	kfree(info);
+fail:
+	return err;
+}
+
+static int __devexit ep93xx_i2s_remove(struct platform_device *pdev)
+{
+	struct ep93xx_i2s_info *info = ep93xx_i2s_dai.private_data;
+
+	snd_soc_unregister_dai(&ep93xx_i2s_dai);
+	clk_put(info->lrclk);
+	clk_put(info->sclk);
+	clk_put(info->mclk);
+	iounmap(info->regs);
+	release_mem_region(info->mem->start, resource_size(info->mem));
+	kfree(info);
+	return 0;
+}
+
+static struct platform_driver ep93xx_i2s_driver = {
+	.probe	= ep93xx_i2s_probe,
+	.remove	= __devexit_p(ep93xx_i2s_remove),
+	.driver	= {
+		.name	= "ep93xx-i2s",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init ep93xx_i2s_init(void)
+{
+	return platform_driver_register(&ep93xx_i2s_driver);
+}
+
+static void __exit ep93xx_i2s_exit(void)
+{
+	platform_driver_unregister(&ep93xx_i2s_driver);
+}
+
+module_init(ep93xx_i2s_init);
+module_exit(ep93xx_i2s_exit);
+
+MODULE_ALIAS("platform:ep93xx-i2s");
+MODULE_AUTHOR("Ryan Mallon <ryan at bluewatersys.com>");
+MODULE_DESCRIPTION("EP93XX I2S driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/ep93xx/ep93xx-i2s.h b/sound/soc/ep93xx/ep93xx-i2s.h
new file mode 100644
index 0000000..3bd4ebf
--- /dev/null
+++ b/sound/soc/ep93xx/ep93xx-i2s.h
@@ -0,0 +1,18 @@
+/*
+ * linux/sound/soc/ep93xx-i2s.h
+ * EP93xx I2S driver
+ *
+ * Copyright (C) 2010 Ryan Mallon <ryan at bluewatersys.com>
+ *  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _EP93XX_SND_SOC_I2S_H
+#define _EP93XX_SND_SOC_I2S_H
+
+extern struct snd_soc_dai ep93xx_i2s_dai;
+
+#endif /* _EP93XX_SND_SOC_I2S_H */
diff --git a/sound/soc/ep93xx/ep93xx-pcm.c b/sound/soc/ep93xx/ep93xx-pcm.c
new file mode 100644
index 0000000..4ba9384
--- /dev/null
+++ b/sound/soc/ep93xx/ep93xx-pcm.c
@@ -0,0 +1,319 @@
+/*
+ * linux/sound/arm/ep93xx-pcm.c - EP93xx ALSA PCM interface
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh at wantstofly.org>
+ * Copyright (C) 2006 Applied Data Systems
+ *
+ * Rewritten for the SoC audio subsystem (Based on PXA2xx code):
+ *   Copyright (c) 2008 Ryan Mallon <ryan at bluewatersys.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <mach/dma.h>
+#include <mach/hardware.h>
+#include <mach/ep93xx-regs.h>
+
+#include "ep93xx-pcm.h"
+
+static const struct snd_pcm_hardware ep93xx_pcm_hardware = {
+	.info			= (SNDRV_PCM_INFO_MMAP		|
+				   SNDRV_PCM_INFO_MMAP_VALID	|
+				   SNDRV_PCM_INFO_INTERLEAVED	|
+				   SNDRV_PCM_INFO_BLOCK_TRANSFER),
+				   
+	.rates			= SNDRV_PCM_RATE_8000_48000,
+	.rate_min		= SNDRV_PCM_RATE_8000,
+	.rate_max		= SNDRV_PCM_RATE_48000,
+	
+	.formats		= (SNDRV_PCM_FMTBIT_S16_LE |
+				   SNDRV_PCM_FMTBIT_S24_LE |
+				   SNDRV_PCM_FMTBIT_S32_LE),
+	
+	.buffer_bytes_max	= 131072,
+	.period_bytes_min	= 32,
+	.period_bytes_max	= 32768,
+	.periods_min		= 1,
+	.periods_max		= 32,
+	.fifo_size		= 32,
+};
+
+struct ep93xx_runtime_data
+{
+	struct ep93xx_dma_m2p_client	cl;
+	struct ep93xx_pcm_dma_params	*params;
+	int				pointer_bytes;
+	struct tasklet_struct		period_tasklet;
+	int				periods;
+	struct ep93xx_dma_buffer	buf[32];
+};
+
+static void ep93xx_pcm_period_elapsed(unsigned long data)
+{
+	struct snd_pcm_substream *substream = (struct snd_pcm_substream *)data;
+	snd_pcm_period_elapsed(substream);
+}
+
+static void ep93xx_pcm_buffer_started(void *cookie,
+				      struct ep93xx_dma_buffer *buf)
+{
+}
+
+static void ep93xx_pcm_buffer_finished(void *cookie, 
+				       struct ep93xx_dma_buffer *buf, 
+				       int bytes, int error)
+{
+	struct snd_pcm_substream *substream = cookie;
+	struct ep93xx_runtime_data *rtd = substream->runtime->private_data;
+
+	if (buf == rtd->buf + rtd->periods - 1)
+		rtd->pointer_bytes = 0;
+	else
+		rtd->pointer_bytes += buf->size;
+
+	if (!error) {
+		ep93xx_dma_m2p_submit_recursive(&rtd->cl, buf);
+		tasklet_schedule(&rtd->period_tasklet);
+	} else {
+		snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
+	}
+}
+
+static int ep93xx_pcm_open(struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *soc_rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = soc_rtd->dai->cpu_dai;
+	struct ep93xx_pcm_dma_params *dma_params;
+	struct ep93xx_runtime_data *rtd;    
+	int ret;
+
+	dma_params = snd_soc_dai_get_dma_data(cpu_dai, substream);
+	snd_soc_set_runtime_hwparams(substream, &ep93xx_pcm_hardware);
+
+	rtd = kmalloc(sizeof(*rtd), GFP_KERNEL);
+	if (!rtd) 
+		return -ENOMEM;
+
+	memset(&rtd->period_tasklet, 0, sizeof(rtd->period_tasklet));
+	rtd->period_tasklet.func = ep93xx_pcm_period_elapsed;
+	rtd->period_tasklet.data = (unsigned long)substream;
+
+	rtd->cl.name = dma_params->name;
+	rtd->cl.flags = dma_params->dma_port | EP93XX_DMA_M2P_IGNORE_ERROR |
+		((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+		 EP93XX_DMA_M2P_TX : EP93XX_DMA_M2P_RX);
+	rtd->cl.cookie = substream;
+	rtd->cl.buffer_started = ep93xx_pcm_buffer_started;
+	rtd->cl.buffer_finished = ep93xx_pcm_buffer_finished;
+	ret = ep93xx_dma_m2p_client_register(&rtd->cl);
+	if (ret < 0) {
+		kfree(rtd);
+		return ret;
+	}
+	
+	substream->runtime->private_data = rtd;
+	return 0;
+}
+
+static int ep93xx_pcm_close(struct snd_pcm_substream *substream)
+{
+	struct ep93xx_runtime_data *rtd = substream->runtime->private_data;
+
+	ep93xx_dma_m2p_client_unregister(&rtd->cl);
+	kfree(rtd);
+	return 0;
+}
+
+static int ep93xx_pcm_hw_params(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct ep93xx_runtime_data *rtd = runtime->private_data;
+	size_t totsize = params_buffer_bytes(params);
+	size_t period = params_period_bytes(params);
+	int i;
+
+	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+	runtime->dma_bytes = totsize;
+
+	rtd->periods = (totsize + period - 1) / period;
+	for (i = 0; i < rtd->periods; i++) {
+		rtd->buf[i].bus_addr = runtime->dma_addr + (i * period);
+		rtd->buf[i].size = period;
+		if ((i + 1) * period > totsize)
+			rtd->buf[i].size = totsize - (i * period);
+	}
+
+	return 0;
+}
+
+static int ep93xx_pcm_hw_free(struct snd_pcm_substream *substream)
+{
+	snd_pcm_set_runtime_buffer(substream, NULL);
+	return 0;
+}
+
+static int ep93xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+	struct ep93xx_runtime_data *rtd = substream->runtime->private_data;
+	int ret;
+	int i;
+
+	ret = 0;
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		rtd->pointer_bytes = 0;
+		for (i = 0; i < rtd->periods; i++)
+			ep93xx_dma_m2p_submit(&rtd->cl, rtd->buf + i);
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		ep93xx_dma_m2p_flush(&rtd->cl);
+		break;
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static snd_pcm_uframes_t ep93xx_pcm_pointer(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct ep93xx_runtime_data *rtd = substream->runtime->private_data;
+
+	/* FIXME: implement this with sub-period granularity */
+	return bytes_to_frames(runtime, rtd->pointer_bytes);
+}
+
+static int ep93xx_pcm_mmap(struct snd_pcm_substream *substream,
+			   struct vm_area_struct *vma)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+
+	return dma_mmap_writecombine(substream->pcm->card->dev, vma,
+				     runtime->dma_area,
+				     runtime->dma_addr,
+				     runtime->dma_bytes);
+}
+
+static struct snd_pcm_ops ep93xx_pcm_ops = {
+	.open		= ep93xx_pcm_open,
+	.close		= ep93xx_pcm_close,
+	.ioctl		= snd_pcm_lib_ioctl,
+	.hw_params	= ep93xx_pcm_hw_params,
+	.hw_free	= ep93xx_pcm_hw_free,
+	.trigger	= ep93xx_pcm_trigger,
+	.pointer	= ep93xx_pcm_pointer,
+	.mmap		= ep93xx_pcm_mmap,
+};
+
+static int ep93xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
+{
+	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+	struct snd_dma_buffer *buf = &substream->dma_buffer;
+	size_t size = ep93xx_pcm_hardware.buffer_bytes_max;
+
+	buf->dev.type = SNDRV_DMA_TYPE_DEV;
+	buf->dev.dev = pcm->card->dev;
+	buf->private_data = NULL;
+	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
+					   &buf->addr, GFP_KERNEL);
+	buf->bytes = size;
+
+	return (buf->area == NULL) ? -ENOMEM : 0;
+}
+
+static void ep93xx_pcm_free_dma_buffers(struct snd_pcm *pcm)
+{
+	struct snd_pcm_substream *substream;
+	struct snd_dma_buffer *buf;
+	int stream;
+
+	for (stream = 0; stream < 2; stream++) {		
+		substream = pcm->streams[stream].substream;
+		if (!substream)
+			continue;
+		
+		buf = &substream->dma_buffer;
+		if (!buf->area)
+			continue;
+
+		dma_free_writecombine(pcm->card->dev, buf->bytes, buf->area,
+				      buf->addr);
+		buf->area = NULL;
+	}
+}
+
+static u64 ep93xx_pcm_dmamask = 0xffffffff;
+
+static int ep93xx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
+			  struct snd_pcm *pcm)
+{
+	int ret = 0;
+
+	if (!card->dev->dma_mask)
+		card->dev->dma_mask = &ep93xx_pcm_dmamask;
+	if (!card->dev->coherent_dma_mask)
+		card->dev->coherent_dma_mask = 0xffffffff;
+
+	if (dai->playback.channels_min) {
+		ret = ep93xx_pcm_preallocate_dma_buffer(pcm,
+					SNDRV_PCM_STREAM_PLAYBACK);
+		if (ret)
+			return ret;
+	}
+
+	if (dai->capture.channels_min) {
+		ret = ep93xx_pcm_preallocate_dma_buffer(pcm,
+					SNDRV_PCM_STREAM_CAPTURE);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+struct snd_soc_platform ep93xx_soc_platform = {
+	.name		= "ep93xx-audio",
+	.pcm_ops	= &ep93xx_pcm_ops,
+	.pcm_new	= &ep93xx_pcm_new,
+	.pcm_free	= &ep93xx_pcm_free_dma_buffers,
+};
+EXPORT_SYMBOL_GPL(ep93xx_soc_platform);
+
+static int __init ep93xx_soc_platform_init(void)
+{
+	return snd_soc_register_platform(&ep93xx_soc_platform);
+}
+
+static void __exit ep93xx_soc_platform_exit(void)
+{
+	snd_soc_unregister_platform(&ep93xx_soc_platform);
+}
+
+module_init(ep93xx_soc_platform_init);
+module_exit(ep93xx_soc_platform_exit);
+
+MODULE_AUTHOR("Ryan Mallon <ryan at bluewatersys.com>");
+MODULE_DESCRIPTION("EP93xx ALSA PCM interface");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/ep93xx/ep93xx-pcm.h b/sound/soc/ep93xx/ep93xx-pcm.h
new file mode 100644
index 0000000..4ffdd3f
--- /dev/null
+++ b/sound/soc/ep93xx/ep93xx-pcm.h
@@ -0,0 +1,22 @@
+/*
+ * sound/soc/ep93xx/ep93xx-pcm.h - EP93xx ALSA PCM interface
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh at wantstofly.org>
+ * Copyright (C) 2006 Applied Data Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EP93XX_SND_SOC_PCM_H
+#define _EP93XX_SND_SOC_PCM_H
+
+struct ep93xx_pcm_dma_params {
+	char	*name;
+	int	dma_port;
+};
+
+extern struct snd_soc_platform ep93xx_soc_platform;
+
+#endif /* _EP93XX_SND_SOC_PCM_H */
-- 
1.5.5.1



From ryan at bluewatersys.com  Fri Jun  4 01:11:25 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Fri,  4 Jun 2010 17:11:25 +1200
Subject: [RFC PATCH v3 3/3] Snapper cl15 audio support
In-Reply-To: <1275628285-12642-3-git-send-email-ryan@bluewatersys.com>
References: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
	<1275628285-12642-2-git-send-email-ryan@bluewatersys.com>
	<1275628285-12642-3-git-send-email-ryan@bluewatersys.com>
Message-ID: <1275628285-12642-4-git-send-email-ryan@bluewatersys.com>

Added Snapper CL15 i2s audio support

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-ep93xx/snappercl15.c |    1 +
 sound/soc/ep93xx/Kconfig           |    9 ++
 sound/soc/ep93xx/Makefile          |    3 +
 sound/soc/ep93xx/snappercl15.c     |  143 ++++++++++++++++++++++++++++++++++++
 4 files changed, 156 insertions(+), 0 deletions(-)
 create mode 100644 sound/soc/ep93xx/snappercl15.c

diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index 51134b0..d4ca5cc 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -157,6 +157,7 @@ static void __init snappercl15_init_machine(void)
 	ep93xx_register_i2c(&snappercl15_i2c_gpio_data, snappercl15_i2c_data,
 			    ARRAY_SIZE(snappercl15_i2c_data));
 	ep93xx_register_fb(&snappercl15_fb_info);
+	ep93xx_register_i2s(EP93XX_SYSCON_DEVCFG_I2SONAC97);
 	platform_device_register(&snappercl15_nand_device);
 }
 
diff --git a/sound/soc/ep93xx/Kconfig b/sound/soc/ep93xx/Kconfig
index ba66ac8..f617f56 100644
--- a/sound/soc/ep93xx/Kconfig
+++ b/sound/soc/ep93xx/Kconfig
@@ -7,3 +7,12 @@ config SND_EP93XX_SOC
 
 config SND_EP93XX_SOC_I2S
 	tristate
+
+config SND_EP93XX_SOC_SNAPPERCL15
+        tristate "SoC Audio support for Bluewater Systems Snapper CL15 module"
+        depends on SND_EP93XX_SOC && MACH_SNAPPER_CL15
+        select SND_EP93XX_SOC_I2S
+        select SND_SOC_TLV320AIC23
+        help
+          Say Y or M here if you want to add support for I2S audio on the
+          Bluewater Systems Snapper CL15 module.
diff --git a/sound/soc/ep93xx/Makefile b/sound/soc/ep93xx/Makefile
index 0239da3..272e60f 100644
--- a/sound/soc/ep93xx/Makefile
+++ b/sound/soc/ep93xx/Makefile
@@ -6,3 +6,6 @@ obj-$(CONFIG_SND_EP93XX_SOC)			+= snd-soc-ep93xx.o
 obj-$(CONFIG_SND_EP93XX_SOC_I2S)		+= snd-soc-ep93xx-i2s.o
 
 # EP93XX Machine Support
+snd-soc-snappercl15-objs			:= snappercl15.o
+
+obj-$(CONFIG_SND_EP93XX_SOC_SNAPPERCL15)	+= snd-soc-snappercl15.o
diff --git a/sound/soc/ep93xx/snappercl15.c b/sound/soc/ep93xx/snappercl15.c
new file mode 100644
index 0000000..645a7fb
--- /dev/null
+++ b/sound/soc/ep93xx/snappercl15.c
@@ -0,0 +1,143 @@
+/*
+ * snappercl15.c -- SoC audio for Bluewater Systems Snapper CL15 module
+ *
+ * Copyright (C) 2008 Bluewater Systems Ltd
+ * Author: Ryan Mallon <ryan at bluewatersys.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+#include "../codecs/tlv320aic23.h"
+#include "ep93xx-pcm.h"
+#include "ep93xx-i2s.h"
+
+#define CODEC_CLOCK 5644800
+
+static int snappercl15_hw_params(struct snd_pcm_substream *substream,
+				 struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	int err;
+
+	err = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+				  SND_SOC_DAIFMT_NB_IF |
+				  SND_SOC_DAIFMT_CBS_CFS);
+
+	err = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | 
+				  SND_SOC_DAIFMT_NB_IF |		  
+				  SND_SOC_DAIFMT_CBS_CFS);
+	if (err)
+		return err;
+
+	err = snd_soc_dai_set_sysclk(codec_dai, 0, CODEC_CLOCK, 
+				     SND_SOC_CLOCK_IN);
+	if (err)
+		return err;
+
+	err = snd_soc_dai_set_sysclk(cpu_dai, 0, CODEC_CLOCK, 
+				     SND_SOC_CLOCK_OUT);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static struct snd_soc_ops snappercl15_ops = {
+	.hw_params	= snappercl15_hw_params,
+};
+
+static const struct snd_soc_dapm_widget tlv320aic23_dapm_widgets[] = {
+	SND_SOC_DAPM_HP("Headphone Jack", NULL),
+	SND_SOC_DAPM_LINE("Line In", NULL),
+	SND_SOC_DAPM_MIC("Mic Jack", NULL),
+};
+
+static const struct snd_soc_dapm_route audio_map[] = {
+	{"Headphone Jack", NULL, "LHPOUT"},
+	{"Headphone Jack", NULL, "RHPOUT"},
+
+	{"LLINEIN", NULL, "Line In"},
+	{"RLINEIN", NULL, "Line In"},
+
+	{"MICIN", NULL, "Mic Jack"},
+};
+
+static int snappercl15_tlv320aic23_init(struct snd_soc_codec *codec)
+{
+	snd_soc_dapm_new_controls(codec, tlv320aic23_dapm_widgets,
+				  ARRAY_SIZE(tlv320aic23_dapm_widgets));
+
+	snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+	return 0;
+}
+
+static struct snd_soc_dai_link snappercl15_dai = {
+	.name		= "tlv320aic23",
+	.stream_name	= "AIC23",
+	.cpu_dai	= &ep93xx_i2s_dai,
+	.codec_dai	= &tlv320aic23_dai,
+	.init		= snappercl15_tlv320aic23_init,
+	.ops		= &snappercl15_ops,
+};
+
+static struct snd_soc_card snd_soc_snappercl15 = {
+	.name		= "Snapper CL15",
+	.platform	= &ep93xx_soc_platform,
+	.dai_link	= &snappercl15_dai,
+	.num_links	= 1,
+};
+
+static struct snd_soc_device snappercl15_snd_devdata = {
+	.card		= &snd_soc_snappercl15,
+	.codec_dev	= &soc_codec_dev_tlv320aic23,
+};
+
+static struct platform_device *snappercl15_snd_device;
+
+static int __init snappercl15_init(void)
+{
+	int ret;
+
+	if (!machine_is_snapper_cl15())
+		return -ENODEV;
+
+	snappercl15_snd_device = platform_device_alloc("soc-audio", -1);
+	if (!snappercl15_snd_device)
+		return -ENOMEM;
+	
+	platform_set_drvdata(snappercl15_snd_device, &snappercl15_snd_devdata);
+	snappercl15_snd_devdata.dev = &snappercl15_snd_device->dev;
+	ret = platform_device_add(snappercl15_snd_device);
+	if (ret)
+		platform_device_put(snappercl15_snd_device);
+
+	return ret;
+}
+
+static void __exit snappercl15_exit(void)
+{
+	platform_device_unregister(snappercl15_snd_device);
+}
+
+module_init(snappercl15_init);
+module_exit(snappercl15_exit);
+
+MODULE_AUTHOR("Ryan Mallon <ryan at bluewatersys.com>");
+MODULE_DESCRIPTION("ALSA SoC Snapper CL15");
+MODULE_LICENSE("GPL");
+
-- 
1.5.5.1



From marek.vasut at gmail.com  Fri Jun  4 01:52:27 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri,  4 Jun 2010 07:52:27 +0200
Subject: [PATCH 1/2] backlight: Fix blanking for LMS283GF05 LCD
Message-ID: <1275630748-10722-1-git-send-email-marek.vasut@gmail.com>

The LCD was turned on if the variable power was > 0, but that was incorrect. The
LCD has to be turned on in every case but POWERDOWN.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/video/backlight/lms283gf05.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/video/backlight/lms283gf05.c b/drivers/video/backlight/lms283gf05.c
index abc43a0..6a35602 100644
--- a/drivers/video/backlight/lms283gf05.c
+++ b/drivers/video/backlight/lms283gf05.c
@@ -129,7 +129,7 @@ static int lms283gf05_power_set(struct lcd_device *ld, int power)
 	struct spi_device *spi = st->spi;
 	struct lms283gf05_pdata *pdata = spi->dev.platform_data;
 
-	if (power) {
+	if (power < FB_BLANK_POWERDOWN) {
 		if (pdata)
 			lms283gf05_reset(pdata->reset_gpio,
 					pdata->reset_inverted);
-- 
1.7.1



From marek.vasut at gmail.com  Fri Jun  4 01:52:28 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri,  4 Jun 2010 07:52:28 +0200
Subject: [PATCH 2/2] backlight: Fix blanking for L4F00242T03 LCD
In-Reply-To: <1275630748-10722-1-git-send-email-marek.vasut@gmail.com>
References: <1275630748-10722-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1275630748-10722-2-git-send-email-marek.vasut@gmail.com>

The LCD was turned on if the variable power was > 0, but that was incorrect. The
LCD has to be turned on in every case but POWERDOWN.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/video/backlight/l4f00242t03.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/video/backlight/l4f00242t03.c b/drivers/video/backlight/l4f00242t03.c
index 9093ef0..ac20b2e 100644
--- a/drivers/video/backlight/l4f00242t03.c
+++ b/drivers/video/backlight/l4f00242t03.c
@@ -78,7 +78,7 @@ static int l4f00242t03_lcd_power_set(struct lcd_device *ld, int power)
 	const u16 slpin = 0x10;
 	const u16 disoff = 0x28;
 
-	if (power) {
+	if (power < FB_BLANK_POWERDOWN) {
 		if (priv->lcd_on)
 			return 0;
 
-- 
1.7.1



From tony at atomide.com  Fri Jun  4 02:03:39 2010
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 4 Jun 2010 09:03:39 +0300
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006040353.35816.marek.vasut@gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<201006040337.10593.marek.vasut@gmail.com>
	<201006040350.36944.marek.vasut@gmail.com>
	<201006040353.35816.marek.vasut@gmail.com>
Message-ID: <20100604060338.GH6499@atomide.com>

* Marek Vasut <marek.vasut at gmail.com> [100604 04:54]:
> > 
> > OMAP: palmte_defconfig, palmtt_defconfig, palmz71_defconfig
> 
> Ok, making them into one is compile tested. I'd be for calling it a 
> "palmomap_defconfig". Or maybe is there a plan to put whole OMAP1 into a single 
> defconfig ?

Yeah, we should have just one omap1_defconfig. It should already
mostly work already for 15xx + 16xx. To build in 7xx, the entry-macro.S
needs to be done the same way as for mach-omap2.

Regards,

Tony


From tony at atomide.com  Fri Jun  4 02:10:36 2010
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 4 Jun 2010 09:10:36 +0300
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
Message-ID: <20100604061034.GI6499@atomide.com>

* Eric Miao <eric.y.miao at gmail.com> [100604 04:35]:
> 
> Also, we are now working on a single kernel for multiple sub-arch (at least
> what Nicolas and I am doing now, and welcome to join us). It's tough (the
> way to handle different phys_offset is only the tip of the iceberg) and seems
> now more and more necessary. so hopefully by the end of the day, we may
> possible end up with only very few defconfig.

Great, do you have some git branch for that somewhere?

Parallel to dealing with different phys_offset we can also try combining
some two ARM platforms that have the same phy_offset. That already exposes
tons of conflicting defines that need to be sorted out..

Regards,

Tony


From daniel at caiaq.de  Fri Jun  4 02:27:02 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Fri, 4 Jun 2010 08:27:02 +0200
Subject: [PATCH 1/3] pxa/colibri270: Fix typo in colibri_pxa270_flash
In-Reply-To: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>
References: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <20100604062701.GR2695@buzzloop.caiaq.de>

On Fri, Jun 04, 2010 at 03:07:32AM +0200, Marek Vasut wrote:
> Append colibri_pxa270_flash(_device). This was missing.

Hmm, Eric fixed this typo already when commiting (y)our last patch set.
Did you pull his tree?

Daniel


> 
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> ---
>  arch/arm/mach-pxa/colibri-pxa270.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
> index 96ce4ae..98673ac 100644
> --- a/arch/arm/mach-pxa/colibri-pxa270.c
> +++ b/arch/arm/mach-pxa/colibri-pxa270.c
> @@ -99,7 +99,7 @@ static struct platform_device colibri_pxa270_flash_device = {
>  
>  static void __init colibri_pxa270_nor_init(void)
>  {
> -	platform_device_register(&colibri_pxa270_flash);
> +	platform_device_register(&colibri_pxa270_flash_device);
>  }
>  #else
>  static inline void colibri_pxa270_nor_init(void) {}
> -- 
> 1.7.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From marek.vasut at gmail.com  Fri Jun  4 02:55:00 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 4 Jun 2010 08:55:00 +0200
Subject: [PATCH 1/3] pxa/colibri270: Fix typo in colibri_pxa270_flash
In-Reply-To: <20100604062701.GR2695@buzzloop.caiaq.de>
References: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>
	<20100604062701.GR2695@buzzloop.caiaq.de>
Message-ID: <201006040855.00216.marek.vasut@gmail.com>

Dne P? 4. ?ervna 2010 08:27:02 Daniel Mack napsal(a):
> On Fri, Jun 04, 2010 at 03:07:32AM +0200, Marek Vasut wrote:
> > Append colibri_pxa270_flash(_device). This was missing.
> 
> Hmm, Eric fixed this typo already when commiting (y)our last patch set.
> Did you pull his tree?

I think so ... maybe I forget to pull the recent set of changes, then ignore 
this patch.

Cheers
> 
> Daniel
> 
> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> > ---
> > 
> >  arch/arm/mach-pxa/colibri-pxa270.c |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/arm/mach-pxa/colibri-pxa270.c
> > b/arch/arm/mach-pxa/colibri-pxa270.c index 96ce4ae..98673ac 100644
> > --- a/arch/arm/mach-pxa/colibri-pxa270.c
> > +++ b/arch/arm/mach-pxa/colibri-pxa270.c
> > @@ -99,7 +99,7 @@ static struct platform_device
> > colibri_pxa270_flash_device = {
> > 
> >  static void __init colibri_pxa270_nor_init(void)
> >  {
> > 
> > -	platform_device_register(&colibri_pxa270_flash);
> > +	platform_device_register(&colibri_pxa270_flash_device);
> > 
> >  }
> >  #else
> >  static inline void colibri_pxa270_nor_init(void) {}


From benjamin.zores at alcatel-lucent.com  Fri Jun  4 03:09:27 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Fri, 04 Jun 2010 09:09:27 +0200
Subject: [PATCH 4/4 v2] [ARM] Kirkwood: add support for PCIe1
Message-ID: <4C08A6A7.8010904@alcatel-lucent.com>

Hi,

Sorry not to be able to reply/quote, wasn't subscribed before.
Anyhow, this is a patch review/comment from 
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/017106.html

There are a few things missing for proper PCIe #1 support imho:

diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4b..b11b5fe 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -74,9 +74,15 @@ static void __init db88f6281_init(void)

  static int __init db88f6281_pci_init(void)
  {
-	if (machine_is_db88f6281_bp())
-		kirkwood_pcie_init();
+	if (machine_is_db88f6281_bp()) {
+		u32 dev, rev;
+		int init_port1 = 0;

+		kirkwood_pcie_id(&dev,&rev);
+		if (dev == MV88F6282_DEV_ID)
+			init_port1 = 1;
+		kirkwood_pcie_init(1, init_port1);
+	}
  	return 0;
  }
  subsys_initcall(db88f6281_pci_init);


This is really likely not to be possible, unless the 2 boards 
(db-88f6281-bp and db-88f6282-bp have the same ID given by uboot, which 
I guess is not the case).
Better would be to define a new board.

diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f501..2026b30 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,6 +59,7 @@
  #define CGC_SATA1		(1<<  15)
  #define CGC_XOR1		(1<<  16)
  #define CGC_CRYPTO		(1<<  17)
+#define CGC_PEX1		(1<<  18)
  #define CGC_GE1			(1<<  19)
  #define CGC_TDM			(1<<  20)
  #define CGC_RESERVED		((1<<  18) | (0x6<<  21))


 From datasheet, that's correct but then you need to update the 
CGC_RESERVED define to remove the (1 << 18) now that is being used.

@@ -72,6 +81,7 @@
  #define PCIE_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x40000)
  #define PCIE_LINK_CTRL		(PCIE_VIRT_BASE | 0x70)
  #define PCIE_STATUS		(PCIE_VIRT_BASE | 0x1a04)
+#define PCIE1_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x44000)


Also correct, but then you also need to define the following ones:

+ #define PCIE1_LINK_CTRL        (PCIE1_VIRT_BASE | 0x70)
+ #define PCIE1_STATUS        (PCIE1_VIRT_BASE | 0x1a04)

A few other things also need to be done in 
arch/arm/mach-kirkwood/common.c for 2nd PCIe to be properly initialized.
Sorry for this not to be in patch format but you'll probably get my 
point anyhow.

The I/O Mapping has to be set conditionally. I'd propose the following 
approach:

/* I/O Mapping with 1 PEX controller */
static struct map_desc kirkwood_io_desc_1[] __initdata = {
     {
         .virtual    = KIRKWOOD_PCIE_IO_VIRT_BASE,
         .pfn        = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
         .length        = KIRKWOOD_PCIE_IO_SIZE,
         .type        = MT_DEVICE,
     }, {
         .virtual    = KIRKWOOD_REGS_VIRT_BASE,
         .pfn        = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
         .length        = KIRKWOOD_REGS_SIZE,
         .type        = MT_DEVICE,
     },
};

/* I/O Mapping with 2 PEX controllers */
static struct map_desc kirkwood_io_desc_2[] __initdata = {
     {
         .virtual    = KIRKWOOD_PCIE_IO_VIRT_BASE,
         .pfn        = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
         .length        = KIRKWOOD_PCIE_IO_SIZE,
         .type        = MT_DEVICE,
     }, {
     {
         .virtual    = KIRKWOOD_PCIE1_IO_VIRT_BASE,
         .pfn        = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
         .length        = KIRKWOOD_PCIE1_IO_SIZE,
         .type        = MT_DEVICE,
     }, {
         .virtual    = KIRKWOOD_REGS_VIRT_BASE,
         .pfn        = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
         .length        = KIRKWOOD_REGS_SIZE,
         .type        = MT_DEVICE,
     },
};

void __init kirkwood_map_io(void)
{
     u32 dev, rev;

     kirkwood_pcie_id(&dev, &rev);

     if (dev == MV88F6282_DEV_ID && (rev == MV88F6282_REV_A0))
         iotable_init(kirkwood_io_desc_2,
                  ARRAY_SIZE(kirkwood_io_desc_2));
     else
         iotable_init(kirkwood_io_desc_1,
                  ARRAY_SIZE(kirkwood_io_desc_1));
}


And also in kirkwood_clock_gate():

/* Make sure those units are accessible */
- writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, 
CLOCK_GATING_CTRL);
+ writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);

And 2nd PCIe PHY shutdown at init:

+    /* For PCIe #1: first shutdown the phy */
+   if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
+        writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
+       while (1)
+          if (readl(PCIE1_STATUS) & 0x1)
+             break;
+    writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
+  }

Additionally, not sure it is needed for PCIe support but at least for F6282,
you need to refine the MPP matrix in mpp.h. The 6282 MPP _really_ is 
different from 6281 one.
I can send a patch for this if needed, I already have done the necessary 
changes in my tree.

Ben




From eric.y.miao at gmail.com  Fri Jun  4 03:12:48 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 4 Jun 2010 15:12:48 +0800
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100604061034.GI6499@atomide.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk> 
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com> 
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com> 
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com> 
	<20100604061034.GI6499@atomide.com>
Message-ID: <AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>

On Fri, Jun 4, 2010 at 2:10 PM, Tony Lindgren <tony at atomide.com> wrote:
> * Eric Miao <eric.y.miao at gmail.com> [100604 04:35]:
>>
>> Also, we are now working on a single kernel for multiple sub-arch (at least
>> what Nicolas and I am doing now, and welcome to join us). It's tough (the
>> way to handle different phys_offset is only the tip of the iceberg) and seems
>> now more and more necessary. so hopefully by the end of the day, we may
>> possible end up with only very few defconfig.
>
> Great, do you have some git branch for that somewhere?
>

All the currently done work I've posted to the mailing list:

1. SPARSEIRQ
2. MULTI_IRQ_HANDLER
3. Makefile.boot move to arch/arm/boot/bootp _only_
4. RUNTIME_PHYS_OFFSET (not really my work, but Uwe's)

Nico and I have setup a blueprint and wiki spec for this, I hope more
can join us with the effort.

https://blueprints.launchpad.net/ubuntu/+spec/kernel-maverick-arm-single-zimage
https://wiki.ubuntu.com/Specs/ARMSingleKernel

I'll push what I did to

git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git
unified-kernel

But it's a mess now.

> Parallel to dealing with different phys_offset we can also try combining
> some two ARM platforms that have the same phy_offset. That already exposes
> tons of conflicting defines that need to be sorted out..
>

A first step to take might be looking at all those machine specific header
files that will be included into generic <asm/*.h> and in turn included by
other code. The PHYS_OFFSET is only a small tip of the iceberg I'm afraid.
A very rough grep and analysis as below:

`    $ git grep "#include <mach" arch/arm/include/asm/` <<BR>>
`    arch/arm/include/asm/dma.h:#include <mach/isa-dma.h>` <<BR>>
`    arch/arm/include/asm/floppy.h:#include <mach/floppy.h>` <<BR>>
`    arch/arm/include/asm/gpio.h:#include <mach/gpio.h>` <<BR>>
`    arch/arm/include/asm/hardware/dec21285.h:#include <mach/hardware.h>` <<BR>>
`    arch/arm/include/asm/hardware/iop3xx-adma.h:#include
<mach/hardware.h>` <<BR>>
`    arch/arm/include/asm/hardware/iop3xx-gpio.h:#include
<mach/hardware.h>` <<BR>>
`    arch/arm/include/asm/hardware/sa1111.h:#include <mach/bitfield.h>` <<BR>>
`    arch/arm/include/asm/io.h:#include <mach/io.h>` <<BR>>
`    arch/arm/include/asm/irq.h:#include <mach/irqs.h>` <<BR>>
`    arch/arm/include/asm/mc146818rtc.h:#include <mach/irqs.h>` <<BR>>
`    arch/arm/include/asm/memory.h:#include <mach/memory.h>` <<BR>>
`    arch/arm/include/asm/mmzone.h:#include <mach/memory.h>` <<BR>>
`    arch/arm/include/asm/mtd-xip.h:#include <mach/mtd-xip.h>` <<BR>>
`    arch/arm/include/asm/pci.h:#include <mach/hardware.h> /* for
PCIBIOS_MIN_* */` <<BR>>
`    arch/arm/include/asm/pgtable.h:#include <mach/vmalloc.h>` <<BR>>
`    arch/arm/include/asm/smp.h:#include <mach/smp.h>` <<BR>>
`    arch/arm/include/asm/system.h:#include <mach/barriers.h>` <<BR>>
`    arch/arm/include/asm/timex.h:#include <mach/timex.h>` <<BR>>
`    arch/arm/include/asm/vga.h:#include <mach/hardware.h>` <<BR>>

  * <mach/floppy.h> is no longer necessary

1.  arch/arm/include/asm/memory.h:#include <mach/memory.h>

1.1 PHYS_OFFSET

  * can be ignored if RUNTIME_PHYS_OFFSET is doable
  * should be removed from <mach/memory.h>
  * but we need this somewhere to allow the usage of a hardcoded constant
    [a config option?]

1.2 ISA_DMA_THRESHOLD and DMA_MAX_ADDRESS

  * make them into variables and encode them in machine_desc

1.3 arch_adjust_zones()

  * can be moved into machine_desc
  * this depends on CONFIG_ZONE_DMA
  * what to do with CONFIG_ZONE_DMA?

1.4 NODE_MEM_SIZE_BITS, SECTION_SIZE_BITS, MAX_PHYSMEM_BITS, ...

1.5 CONFIG_SPARSEMEM

  * N/A

2. arch/arm/include/asm/dma.h:#include <mach/isa-dma.h>

  * depends on CONFIG_ISA_DMA_API
  * currently only the machines below:
    * arch/arm/mach-h720x/include/mach/isa-dma.h
    * arch/arm/mach-footbridge/include/mach/isa-dma.h
    * arch/arm/mach-shark/include/mach/isa-dma.h
    * arch/arm/mach-rpc/include/mach/isa-dma.h
  * the most important definition is MAX_DMA_CHANNELS, which can be
    converted to a variable
  * some other machine specific definitions

3. arch/arm/include/asm/gpio.h:#include <mach/gpio.h>

  * gpio_to_irq() and irq_to_gpio(), need to make this generic but
    could hurt performance
  * inlined version of gpio_{get,set}_value(), gpio_direction_*()
    and others will conflict with each other
  * some other definitions like GPIO registers

4. arch/arm/include/asm/hardware/dec21285.h:#include <mach/hardware.h>
   arch/arm/include/asm/hardware/iop3xx-adma.h:#include <mach/hardware.h>
   arch/arm/include/asm/hardware/iop3xx-gpio.h:#include <mach/hardware.h>
   arch/arm/include/asm/vga.h:#include <mach/hardware.h>

  * <mach/hardware.h> is really machine specific and could possibly contain
    anything

5. arch/arm/include/asm/io.h:#include <mach/io.h>

  * IO_SPACE_LIMIT (actually IO_SPACE_LIMIT for _all_ machines are now
    0xffff_ffff), if no exception could just be removed and make it a
    default
  * definitions of __io(), this is defined as __typesafe_io(a) on most
    platforms, on other platforms, it can be abstracted as
`      ((void __iomem *)(BASE + (a)))` <<BR>>
    as long as we can make BASE a variable, this can be removed
  * definitions of __mem_pci(a), defined as (a) on all platforms, can
    be removed and make a default
  * ixp4xx is especially complex, depending on INDIRECT_PCI and PCI
  * how to handle different definitions of {in,out}{b,w,l}()
  * __arch_ioremap() and __arch_iounmap()

6. arch/arm/include/asm/irq.h:#include <mach/irqs.h>

  * what <asm/irq.h> needs is NR_IRQS (can be solved by SPARSEIRQ)
  * <mach/irqs.h> can be made internal to machine specific code _only_

7. arch/arm/include/asm/mtd-xip.h:#include <mach/mtd-xip.h>

  * currently, only omap1, pxa, sa1100 supports this
  * xip_irqpending()
  * xip_currtime()
  * xip_elapsed_since()
  * xip_cpu_idle()

8. arch/arm/include/asm/pci.h:#include <mach/hardware.h> /* for PCIBIOS_MIN_* */

  * need to make PCIBIOS_MIN_* variables

9. arch/arm/include/asm/pgtable.h:#include <mach/vmalloc.h>

  * mainly for VMALLOC_END could be made into a machine specific variable

10. arch/arm/include/asm/smp.h:#include <mach/smp.h>

  * smp_cross_call()
  * hard_smp_processor_id()

11. arch/arm/include/asm/system.h:#include <mach/barriers.h>

  * currently no machine defines barriers.h

12. arch/arm/include/asm/timex.h:#include <mach/timex.h>

  * CLOCK_TICK_RATE, can actually be removed


From olof at lixom.net  Fri Jun  4 03:10:32 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri,  4 Jun 2010 02:10:32 -0500
Subject: [PATCH 0/10] Tegra platform support
In-Reply-To: <3478yvr76gerav>
References: <3478yvr76gerav>
Message-ID: <1275635441-17378-1-git-send-email-olof@lixom.net>


Hi,

This is for the most part a repost of the arch/arm/mach-tegra parts of
Erik Gilling's post of the Tegra series from April 13. I've done some
minor cleanups and picked up a couple of bugfixes from later patches,
but I wanted to keep the original series bite size for easier review.

There is more to come once this is in.

Russell, do you prefer to take the initial series and feed it to Linus, or
should I send a direct pull request with your acked-by (once you give it)?


Thanks,

-Olof


From olof at lixom.net  Fri Jun  4 03:10:34 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri,  4 Jun 2010 02:10:34 -0500
Subject: [PATCH 02/10] [ARM] tegra: Add IRQ support
In-Reply-To: <1275635441-17378-2-git-send-email-olof@lixom.net>
References: <3478yvr76gerav> <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
Message-ID: <1275635441-17378-3-git-send-email-olof@lixom.net>

From: Erik Gilling <konkers at android.com>

v2: fixes from Russell King
	- include linux/io.h instead of asm/io.h and mach/io.h

Fix name of SPI_4 IRQ

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Erik Gilling <konkers at android.com>
Signed-off-by: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-tegra/Makefile            |    1 +
 arch/arm/mach-tegra/include/mach/irqs.h |  173 +++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/irq.c               |   34 ++++++
 3 files changed, 208 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/irqs.h
 create mode 100644 arch/arm/mach-tegra/irq.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 81f003d..a0d2c5b 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,2 +1,3 @@
 obj-y                                   += common.o
 obj-y                                   += io.o
+obj-y                                   += irq.o
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
new file mode 100644
index 0000000..20f640e
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -0,0 +1,173 @@
+/*
+ * arch/arm/mach-tegra/include/mach/irqs.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IRQS_H
+#define __MACH_TEGRA_IRQS_H
+
+#define INT_GIC_BASE			0
+
+#define IRQ_LOCALTIMER                  29
+
+/* Primary Interrupt Controller */
+#define INT_PRI_BASE			(INT_GIC_BASE + 32)
+#define INT_TMR1			(INT_PRI_BASE + 0)
+#define INT_TMR2			(INT_PRI_BASE + 1)
+#define INT_RTC				(INT_PRI_BASE + 2)
+#define INT_I2S2			(INT_PRI_BASE + 3)
+#define INT_SHR_SEM_INBOX_IBF		(INT_PRI_BASE + 4)
+#define INT_SHR_SEM_INBOX_IBE		(INT_PRI_BASE + 5)
+#define INT_SHR_SEM_OUTBOX_IBF		(INT_PRI_BASE + 6)
+#define INT_SHR_SEM_OUTBOX_IBE		(INT_PRI_BASE + 7)
+#define INT_VDE_UCQ_ERROR		(INT_PRI_BASE + 8)
+#define INT_VDE_SYNC_TOKEN		(INT_PRI_BASE + 9)
+#define INT_VDE_BSE_V			(INT_PRI_BASE + 10)
+#define INT_VDE_BSE_A			(INT_PRI_BASE + 11)
+#define INT_VDE_SXE			(INT_PRI_BASE + 12)
+#define INT_I2S1			(INT_PRI_BASE + 13)
+#define INT_SDMMC1			(INT_PRI_BASE + 14)
+#define INT_SDMMC2			(INT_PRI_BASE + 15)
+#define INT_XIO				(INT_PRI_BASE + 16)
+#define INT_VDE				(INT_PRI_BASE + 17)
+#define INT_AVP_UCQ			(INT_PRI_BASE + 18)
+#define INT_SDMMC3			(INT_PRI_BASE + 19)
+#define INT_USB				(INT_PRI_BASE + 20)
+#define INT_USB2			(INT_PRI_BASE + 21)
+#define INT_PRI_RES_22			(INT_PRI_BASE + 22)
+#define INT_EIDE			(INT_PRI_BASE + 23)
+#define INT_NANDFLASH			(INT_PRI_BASE + 24)
+#define INT_VCP				(INT_PRI_BASE + 25)
+#define INT_APB_DMA			(INT_PRI_BASE + 26)
+#define INT_AHB_DMA			(INT_PRI_BASE + 27)
+#define INT_GNT_0			(INT_PRI_BASE + 28)
+#define INT_GNT_1			(INT_PRI_BASE + 29)
+#define INT_OWR				(INT_PRI_BASE + 30)
+#define INT_SDMMC4			(INT_PRI_BASE + 31)
+
+/* Secondary Interrupt Controller */
+#define INT_SEC_BASE			(INT_PRI_BASE + 32)
+#define INT_GPIO1			(INT_SEC_BASE + 0)
+#define INT_GPIO2			(INT_SEC_BASE + 1)
+#define INT_GPIO3			(INT_SEC_BASE + 2)
+#define INT_GPIO4			(INT_SEC_BASE + 3)
+#define INT_UARTA			(INT_SEC_BASE + 4)
+#define INT_UARTB			(INT_SEC_BASE + 5)
+#define INT_I2C				(INT_SEC_BASE + 6)
+#define INT_SPI				(INT_SEC_BASE + 7)
+#define INT_TWC				(INT_SEC_BASE + 8)
+#define INT_TMR3			(INT_SEC_BASE + 9)
+#define INT_TMR4			(INT_SEC_BASE + 10)
+#define INT_FLOW_RSM0			(INT_SEC_BASE + 11)
+#define INT_FLOW_RSM1			(INT_SEC_BASE + 12)
+#define INT_SPDIF			(INT_SEC_BASE + 13)
+#define INT_UARTC			(INT_SEC_BASE + 14)
+#define INT_MIPI			(INT_SEC_BASE + 15)
+#define INT_EVENTA			(INT_SEC_BASE + 16)
+#define INT_EVENTB			(INT_SEC_BASE + 17)
+#define INT_EVENTC			(INT_SEC_BASE + 18)
+#define INT_EVENTD			(INT_SEC_BASE + 19)
+#define INT_VFIR			(INT_SEC_BASE + 20)
+#define INT_DVC				(INT_SEC_BASE + 21)
+#define INT_SYS_STATS_MON		(INT_SEC_BASE + 22)
+#define INT_GPIO5			(INT_SEC_BASE + 23)
+#define INT_CPU0_PMU_INTR		(INT_SEC_BASE + 24)
+#define INT_CPU2_PMU_INTR		(INT_SEC_BASE + 25)
+#define INT_SEC_RES_26			(INT_SEC_BASE + 26)
+#define INT_S_LINK1			(INT_SEC_BASE + 27)
+#define INT_APB_DMA_COP			(INT_SEC_BASE + 28)
+#define INT_AHB_DMA_COP			(INT_SEC_BASE + 29)
+#define INT_DMA_TX			(INT_SEC_BASE + 30)
+#define INT_DMA_RX			(INT_SEC_BASE + 31)
+
+/* Tertiary Interrupt Controller */
+#define INT_TRI_BASE			(INT_SEC_BASE + 32)
+#define INT_HOST1X_COP_SYNCPT		(INT_TRI_BASE + 0)
+#define INT_HOST1X_MPCORE_SYNCPT	(INT_TRI_BASE + 1)
+#define INT_HOST1X_COP_GENERAL		(INT_TRI_BASE + 2)
+#define INT_HOST1X_MPCORE_GENERAL	(INT_TRI_BASE + 3)
+#define INT_MPE_GENERAL			(INT_TRI_BASE + 4)
+#define INT_VI_GENERAL			(INT_TRI_BASE + 5)
+#define INT_EPP_GENERAL			(INT_TRI_BASE + 6)
+#define INT_ISP_GENERAL			(INT_TRI_BASE + 7)
+#define INT_2D_GENERAL			(INT_TRI_BASE + 8)
+#define INT_DISPLAY_GENERAL		(INT_TRI_BASE + 9)
+#define INT_DISPLAY_B_GENERAL		(INT_TRI_BASE + 10)
+#define INT_HDMI			(INT_TRI_BASE + 11)
+#define INT_TVO_GENERAL			(INT_TRI_BASE + 12)
+#define INT_MC_GENERAL			(INT_TRI_BASE + 13)
+#define INT_EMC_GENERAL			(INT_TRI_BASE + 14)
+#define INT_TRI_RES_15			(INT_TRI_BASE + 15)
+#define INT_TRI_RES_16			(INT_TRI_BASE + 16)
+#define INT_AC97			(INT_TRI_BASE + 17)
+#define INT_SPI_2			(INT_TRI_BASE + 18)
+#define INT_SPI_3			(INT_TRI_BASE + 19)
+#define INT_I2C2			(INT_TRI_BASE + 20)
+#define INT_KBC				(INT_TRI_BASE + 21)
+#define INT_EXTERNAL_PMU		(INT_TRI_BASE + 22)
+#define INT_GPIO6			(INT_TRI_BASE + 23)
+#define INT_TVDAC			(INT_TRI_BASE + 24)
+#define INT_GPIO7			(INT_TRI_BASE + 25)
+#define INT_UARTD			(INT_TRI_BASE + 26)
+#define INT_UARTE			(INT_TRI_BASE + 27)
+#define INT_I2C3			(INT_TRI_BASE + 28)
+#define INT_SPI_4			(INT_TRI_BASE + 29)
+#define INT_TRI_RES_30			(INT_TRI_BASE + 30)
+#define INT_SW_RESERVED			(INT_TRI_BASE + 31)
+
+/* Quaternary Interrupt Controller */
+#define INT_QUAD_BASE			(INT_TRI_BASE + 32)
+#define INT_SNOR			(INT_QUAD_BASE + 0)
+#define INT_USB3			(INT_QUAD_BASE + 1)
+#define INT_PCIE_INTR			(INT_QUAD_BASE + 2)
+#define INT_PCIE_MSI			(INT_QUAD_BASE + 3)
+#define INT_QUAD_RES_4			(INT_QUAD_BASE + 4)
+#define INT_QUAD_RES_5			(INT_QUAD_BASE + 5)
+#define INT_QUAD_RES_6			(INT_QUAD_BASE + 6)
+#define INT_QUAD_RES_7			(INT_QUAD_BASE + 7)
+#define INT_APB_DMA_CH0			(INT_QUAD_BASE + 8)
+#define INT_APB_DMA_CH1			(INT_QUAD_BASE + 9)
+#define INT_APB_DMA_CH2			(INT_QUAD_BASE + 10)
+#define INT_APB_DMA_CH3			(INT_QUAD_BASE + 11)
+#define INT_APB_DMA_CH4			(INT_QUAD_BASE + 12)
+#define INT_APB_DMA_CH5			(INT_QUAD_BASE + 13)
+#define INT_APB_DMA_CH6			(INT_QUAD_BASE + 14)
+#define INT_APB_DMA_CH7			(INT_QUAD_BASE + 15)
+#define INT_APB_DMA_CH8			(INT_QUAD_BASE + 16)
+#define INT_APB_DMA_CH9			(INT_QUAD_BASE + 17)
+#define INT_APB_DMA_CH10		(INT_QUAD_BASE + 18)
+#define INT_APB_DMA_CH11		(INT_QUAD_BASE + 19)
+#define INT_APB_DMA_CH12		(INT_QUAD_BASE + 20)
+#define INT_APB_DMA_CH13		(INT_QUAD_BASE + 21)
+#define INT_APB_DMA_CH14		(INT_QUAD_BASE + 22)
+#define INT_APB_DMA_CH15		(INT_QUAD_BASE + 23)
+#define INT_QUAD_RES_24			(INT_QUAD_BASE + 24)
+#define INT_QUAD_RES_25			(INT_QUAD_BASE + 25)
+#define INT_QUAD_RES_26			(INT_QUAD_BASE + 26)
+#define INT_QUAD_RES_27			(INT_QUAD_BASE + 27)
+#define INT_QUAD_RES_28			(INT_QUAD_BASE + 28)
+#define INT_QUAD_RES_29			(INT_QUAD_BASE + 29)
+#define INT_QUAD_RES_30			(INT_QUAD_BASE + 30)
+#define INT_QUAD_RES_31			(INT_QUAD_BASE + 31)
+
+#define INT_GPIO_BASE			(INT_QUAD_BASE + 32)
+#define INT_GPIO_NR			(28 * 8)
+
+#define NR_IRQS				(INT_GPIO_BASE + INT_GPIO_NR)
+
+#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
new file mode 100644
index 0000000..1fdbe70
--- /dev/null
+++ b/arch/arm/mach-tegra/irq.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <asm/hardware/gic.h>
+
+#include <mach/iomap.h>
+
+#include "board.h"
+
+void __init tegra_init_irq(void)
+{
+	gic_dist_init(0, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 29);
+	gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
+}
-- 
1.5.6.5



From olof at lixom.net  Fri Jun  4 03:10:36 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri,  4 Jun 2010 02:10:36 -0500
Subject: [PATCH 04/10] [ARM] tegra: SMP support
In-Reply-To: <1275635441-17378-4-git-send-email-olof@lixom.net>
References: <3478yvr76gerav> <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
	<1275635441-17378-3-git-send-email-olof@lixom.net>
	<1275635441-17378-4-git-send-email-olof@lixom.net>
Message-ID: <1275635441-17378-5-git-send-email-olof@lixom.net>

From: Colin Cross <ccross at android.com>

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Erik Gilling <konkers at android.com>
Signed-off-by: Olof Johansson <olof at lixom.net>
---
 arch/arm/Kconfig                       |   12 ++-
 arch/arm/mach-tegra/Makefile           |    2 +
 arch/arm/mach-tegra/headsmp.S          |   61 +++++++++++++
 arch/arm/mach-tegra/hotplug.c          |  140 ++++++++++++++++++++++++++++
 arch/arm/mach-tegra/include/mach/smp.h |   30 ++++++
 arch/arm/mach-tegra/localtimer.c       |   25 +++++
 arch/arm/mach-tegra/platsmp.c          |  156 ++++++++++++++++++++++++++++++++
 7 files changed, 422 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-tegra/headsmp.S
 create mode 100644 arch/arm/mach-tegra/hotplug.c
 create mode 100644 arch/arm/mach-tegra/include/mach/smp.h
 create mode 100644 arch/arm/mach-tegra/localtimer.c
 create mode 100644 arch/arm/mach-tegra/platsmp.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 92b9572..14453b2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1107,10 +1107,12 @@ source "kernel/time/Kconfig"
 config SMP
 	bool "Symmetric Multi-Processing (EXPERIMENTAL)"
 	depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
-		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
+		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+		 ARCH_U8500 || ARCH_TEGRA)
 	depends on GENERIC_CLOCKEVENTS
 	select USE_GENERIC_SMP_HELPERS
-	select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
+	select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || \
+		 ARCH_TEGRA)
 	help
 	  This enables support for systems with more than one CPU. If you have
 	  a system with only one CPU, like most personal computers, say N. If
@@ -1179,9 +1181,11 @@ config HOTPLUG_CPU
 config LOCAL_TIMERS
 	bool "Use local timer interrupts"
 	depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
-		REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
+		REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+		ARCH_U8500 || ARCH_TEGRA)
 	default y
-	select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
+	select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || \
+		ARCH_TEGRA)
 	help
 	  Enable support for local timers on SMP platforms, rather then the
 	  legacy IPI broadcast method.  Local timers allows the system
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e20546a..f339559 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -3,3 +3,5 @@ obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
+obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
new file mode 100644
index 0000000..b5349b2
--- /dev/null
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -0,0 +1,61 @@
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        .section ".text.head", "ax"
+	__CPUINIT
+
+/*
+ * Tegra specific entry point for secondary CPUs.
+ *   The secondary kernel init calls v7_flush_dcache_all before it enables
+ *   the L1; however, the L1 comes out of reset in an undefined state, so
+ *   the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ *   of cache lines with uninitialized data and uninitialized tags to get
+ *   written out to memory, which does really unpleasant things to the main
+ *   processor.  We fix this by performing an invalidate, rather than a
+ *   clean + invalidate, before jumping into the kernel.
+ */
+ENTRY(v7_invalidate_l1)
+        mov     r0, #0
+        mcr     p15, 2, r0, c0, c0, 0
+        mrc     p15, 1, r0, c0, c0, 0
+
+        ldr     r1, =0x7fff
+        and     r2, r1, r0, lsr #13
+
+        ldr     r1, =0x3ff
+
+        and     r3, r1, r0, lsr #3  @ NumWays - 1
+        add     r2, r2, #1          @ NumSets
+
+        and     r0, r0, #0x7
+        add     r0, r0, #4          @ SetShift
+
+        clz     r1, r3              @ WayShift
+        add     r4, r3, #1          @ NumWays
+1:      sub     r2, r2, #1          @ NumSets--
+        mov     r3, r4              @ Temp = NumWays
+2:      subs    r3, r3, #1          @ Temp--
+        mov     r5, r3, lsl r1
+        mov     r6, r2, lsl r0
+        orr     r5, r5, r6          @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+        mcr     p15, 0, r5, c7, c6, 2
+        bgt     2b
+        cmp     r2, #0
+        bgt     1b
+        dsb
+        isb
+        mov     pc, lr
+ENDPROC(v7_invalidate_l1)
+
+ENTRY(tegra_secondary_startup)
+	msr	cpsr_fsxc, #0xd3
+        bl      v7_invalidate_l1
+	mrc	p15, 0, r0, c0, c0, 5
+        and	r0, r0, #15
+        ldr     r1, =0x6000f100
+        str     r0, [r1]
+1:      ldr     r2, [r1]
+        cmp     r0, r2
+        beq     1b
+        b       secondary_startup
+ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
new file mode 100644
index 0000000..464316c
--- /dev/null
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -0,0 +1,140 @@
+/*
+ *  linux/arch/arm/mach-realview/hotplug.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/completion.h>
+
+#include <asm/cacheflush.h>
+
+static DECLARE_COMPLETION(cpu_killed);
+
+static inline void cpu_enter_lowpower(void)
+{
+	unsigned int v;
+
+	flush_cache_all();
+	asm volatile(
+	"	mcr	p15, 0, %1, c7, c5, 0\n"
+	"	mcr	p15, 0, %1, c7, c10, 4\n"
+	/*
+	 * Turn off coherency
+	 */
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	bic	%0, %0, #0x20\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	"	mrc	p15, 0, %0, c1, c0, 0\n"
+	"	bic	%0, %0, #0x04\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	  : "=&r" (v)
+	  : "r" (0)
+	  : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+	unsigned int v;
+
+	asm volatile(
+	"mrc	p15, 0, %0, c1, c0, 0\n"
+	"	orr	%0, %0, #0x04\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	orr	%0, %0, #0x20\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	  : "=&r" (v)
+	  :
+	  : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu)
+{
+	/*
+	 * there is no power-control hardware on this platform, so all
+	 * we can do is put the core into WFI; this is safe as the calling
+	 * code will have already disabled interrupts
+	 */
+	for (;;) {
+		/*
+		 * here's the WFI
+		 */
+		asm(".word	0xe320f003\n"
+		    :
+		    :
+		    : "memory", "cc");
+
+		/*if (pen_release == cpu) {*/
+			/*
+			 * OK, proper wakeup, we're done
+			 */
+			break;
+		/*}*/
+
+		/*
+		 * getting here, means that we have come out of WFI without
+		 * having been woken up - this shouldn't happen
+		 *
+		 * The trouble is, letting people know about this is not really
+		 * possible, since we are currently running incoherently, and
+		 * therefore cannot safely call printk() or anything else
+		 */
+#ifdef DEBUG
+		printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu);
+#endif
+	}
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+	return wait_for_completion_timeout(&cpu_killed, 5000);
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+#ifdef DEBUG
+	unsigned int this_cpu = hard_smp_processor_id();
+
+	if (cpu != this_cpu) {
+		printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
+			   this_cpu, cpu);
+		BUG();
+	}
+#endif
+
+	printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
+	complete(&cpu_killed);
+
+	/*
+	 * we're ready for shutdown now, so do it
+	 */
+	cpu_enter_lowpower();
+	platform_do_lowpower(cpu);
+
+	/*
+	 * bring this CPU back into the world of cache
+	 * coherency, and then restore interrupts
+	 */
+	cpu_leave_lowpower();
+}
+
+int mach_cpu_disable(unsigned int cpu)
+{
+	/*
+	 * we don't allow CPU 0 to be shutdown (it is still too special
+	 * e.g. clock tick interrupts)
+	 */
+	return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
new file mode 100644
index 0000000..8b42dab
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -0,0 +1,30 @@
+#ifndef ASMARM_ARCH_SMP_H
+#define ASMARM_ARCH_SMP_H
+
+
+#include <asm/hardware/gic.h>
+
+#define hard_smp_processor_id()			\
+	({						\
+		unsigned int cpunum;			\
+		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
+			: "=r" (cpunum));		\
+		cpunum &= 0x0F;				\
+	})
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(const struct cpumask *mask)
+{
+	gic_raise_softirq(mask, 1);
+}
+
+/*
+ * Do nothing on MPcore.
+ */
+static inline void smp_cross_call_done(cpumask_t callmap)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-tegra/localtimer.c b/arch/arm/mach-tegra/localtimer.c
new file mode 100644
index 0000000..f81ca7c
--- /dev/null
+++ b/arch/arm/mach-tegra/localtimer.c
@@ -0,0 +1,25 @@
+/*
+ *  arch/arm/mach-tegra/localtimer.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/irq.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+
+/*
+ * Setup the local clock events for a CPU.
+ */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+	evt->irq = IRQ_LOCALTIMER;
+	twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
new file mode 100644
index 0000000..1c0fd92
--- /dev/null
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -0,0 +1,156 @@
+/*
+ *  linux/arch/arm/mach-tegra/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ *  Copyright (C) 2009 Palm
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/localtimer.h>
+#include <asm/smp_scu.h>
+
+#include <mach/iomap.h>
+
+extern void tegra_secondary_startup(void);
+
+static DEFINE_SPINLOCK(boot_lock);
+static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
+
+#define EVP_CPU_RESET_VECTOR \
+	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
+	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
+	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+	trace_hardirqs_off();
+
+	/*
+	 * if any interrupts are already enabled for the primary
+	 * core (e.g. timer irq), then they will not have been enabled
+	 * for us: do so
+	 */
+	gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100);
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long old_boot_vector;
+	unsigned long boot_vector;
+	unsigned long timeout;
+	u32 reg;
+
+	/*
+	 * set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+
+	/* set the reset vector to point to the secondary_startup routine */
+
+	boot_vector = virt_to_phys(tegra_secondary_startup);
+	old_boot_vector = readl(EVP_CPU_RESET_VECTOR);
+	writel(boot_vector, EVP_CPU_RESET_VECTOR);
+
+	/* enable cpu clock on cpu1 */
+	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+
+	reg = (1<<13) | (1<<9) | (1<<5) | (1<<1);
+	writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+
+	smp_wmb();
+	flush_cache_all();
+
+	/* unhalt the cpu */
+	writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14);
+
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
+			break;
+		udelay(10);
+	}
+
+	/* put the old boot vector back */
+	writel(old_boot_vector, EVP_CPU_RESET_VECTOR);
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+	unsigned int i, ncores = scu_get_core_count(scu_base);
+
+	for (i = 0; i < ncores; i++)
+		cpu_set(i, cpu_possible_map);
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+	unsigned int ncores = scu_get_core_count(scu_base);
+	unsigned int cpu = smp_processor_id();
+	int i;
+
+	smp_store_cpu_info(cpu);
+
+	/*
+	 * are we trying to boot more cores than exist?
+	 */
+	if (max_cpus > ncores)
+		max_cpus = ncores;
+
+	/*
+	 * Initialise the present map, which describes the set of CPUs
+	 * actually populated at the present time.
+	 */
+	for (i = 0; i < max_cpus; i++)
+		set_cpu_present(i, true);
+
+	/*
+	 * Initialise the SCU if there are more than one CPU and let
+	 * them know where to start. Note that, on modern versions of
+	 * MILO, the "poke" doesn't actually do anything until each
+	 * individual core is sent a soft interrupt to get it out of
+	 * WFI
+	 */
+	if (max_cpus > 1) {
+		percpu_timer_setup();
+		scu_enable(scu_base);
+	}
+}
-- 
1.5.6.5



From olof at lixom.net  Fri Jun  4 03:10:35 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri,  4 Jun 2010 02:10:35 -0500
Subject: [PATCH 03/10] [ARM] tegra: Add clock support
In-Reply-To: <1275635441-17378-3-git-send-email-olof@lixom.net>
References: <3478yvr76gerav> <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
	<1275635441-17378-3-git-send-email-olof@lixom.net>
Message-ID: <1275635441-17378-4-git-send-email-olof@lixom.net>

From: Colin Cross <ccross at android.com>

v2: fixes from Russell King:
	- include linux/io.h instead of asm/io.h
	- fix whitespace in Kconfig
	- Use spin_lock_init to initialize lock
	- Return -ENOSYS instead of BUG for unimplemented clock ops
	- Use proper return values in tegra2 clock ops
    additional changes:
	- Rename some clocks to match dev_ids
	- add rate propagation
	- add debugfs entries
	- add support for clock listed in clk_lookup under multiple dev_ids

Merged with separate later patch from Colin:
	Don't reset peripherials on clk_disable
	Correct flags on dvc_i2c
	Remove input clock
	Autodetect state of all clocks on init
	Add cpu, sys, and bus clocks
	Fix clk_set_rate on PLLs
	Replace per-clock locking with global clock lock

Olof:
	Misc formatting cleanups

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Olof Johansson <olof at lixom.net>
---
 arch/arm/Kconfig                          |    1 +
 arch/arm/mach-tegra/Makefile              |    2 +
 arch/arm/mach-tegra/clock.c               |  415 +++++++++
 arch/arm/mach-tegra/clock.h               |  133 +++
 arch/arm/mach-tegra/common.c              |    1 +
 arch/arm/mach-tegra/include/mach/clkdev.h |   32 +
 arch/arm/mach-tegra/tegra2_clocks.c       | 1341 +++++++++++++++++++++++++++++
 arch/arm/tools/mach-types                 |   98 ++-
 8 files changed, 2013 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/mach-tegra/clock.c
 create mode 100644 arch/arm/mach-tegra/clock.h
 create mode 100644 arch/arm/mach-tegra/include/mach/clkdev.h
 create mode 100644 arch/arm/mach-tegra/tegra2_clocks.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 388f371..92b9572 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -581,6 +581,7 @@ config ARCH_TEGRA
 	select GENERIC_CLOCKEVENTS
 	select GENERIC_GPIO
 	select HAVE_CLK
+	select COMMON_CLKDEV
 	select ARCH_HAS_BARRIERS if CACHE_L2X0
 	help
 	  This enables support for NVIDIA Tegra based systems (Tegra APX,
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index a0d2c5b..e20546a 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,3 +1,5 @@
 obj-y                                   += common.o
 obj-y                                   += io.o
 obj-y                                   += irq.o
+obj-y                                   += clock.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
new file mode 100644
index 0000000..bb48242
--- /dev/null
+++ b/arch/arm/mach-tegra/clock.c
@@ -0,0 +1,415 @@
+/*
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/list.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/slab.h>
+#include <linux/seq_file.h>
+#include <asm/clkdev.h>
+
+#include "clock.h"
+
+static LIST_HEAD(clocks);
+
+static DEFINE_SPINLOCK(clock_lock);
+
+struct clk *get_tegra_clock_by_name(const char *name)
+{
+	struct clk *c;
+	struct clk *ret = NULL;
+	unsigned long flags;
+	spin_lock_irqsave(&clock_lock, flags);
+	list_for_each_entry(c, &clocks, node) {
+		if (strcmp(c->name, name) == 0) {
+			ret = c;
+			break;
+		}
+	}
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return ret;
+}
+
+int clk_reparent(struct clk *c, struct clk *parent)
+{
+	pr_debug("%s: %s\n", __func__, c->name);
+	if (c->refcnt && c->parent)
+		clk_disable_locked(c->parent);
+	c->parent = parent;
+	if (c->refcnt && c->parent)
+		clk_enable_locked(c->parent);
+	list_del(&c->sibling);
+	list_add_tail(&c->sibling, &parent->children);
+	return 0;
+}
+
+static void propagate_rate(struct clk *c)
+{
+	struct clk *clkp;
+	pr_debug("%s: %s\n", __func__, c->name);
+	list_for_each_entry(clkp, &c->children, sibling) {
+		pr_debug("   %s\n", clkp->name);
+		if (clkp->ops->recalculate_rate)
+			clkp->ops->recalculate_rate(clkp);
+		propagate_rate(clkp);
+	}
+}
+
+void clk_init(struct clk *c)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&clock_lock, flags);
+
+	INIT_LIST_HEAD(&c->children);
+	INIT_LIST_HEAD(&c->sibling);
+
+	if (c->ops && c->ops->init)
+		c->ops->init(c);
+
+	list_add(&c->node, &clocks);
+
+	if (c->parent)
+		list_add_tail(&c->sibling, &c->parent->children);
+
+	spin_unlock_irqrestore(&clock_lock, flags);
+}
+
+int clk_enable_locked(struct clk *c)
+{
+	int ret;
+	pr_debug("%s: %s\n", __func__, c->name);
+	if (c->refcnt == 0) {
+		if (c->parent) {
+			ret = clk_enable_locked(c->parent);
+			if (ret)
+				return ret;
+		}
+
+		if (c->ops && c->ops->enable) {
+			ret = c->ops->enable(c);
+			if (ret) {
+				if (c->parent)
+					clk_disable_locked(c->parent);
+				return ret;
+			}
+			c->state = ON;
+#ifdef CONFIG_DEBUG_FS
+			c->set = 1;
+#endif
+		}
+	}
+	c->refcnt++;
+
+	return 0;
+}
+
+int clk_enable(struct clk *c)
+{
+	int ret;
+	unsigned long flags;
+	spin_lock_irqsave(&clock_lock, flags);
+	ret = clk_enable_locked(c);
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable_locked(struct clk *c)
+{
+	pr_debug("%s: %s\n", __func__, c->name);
+	if (c->refcnt == 0) {
+		WARN(1, "Attempting to disable clock %s with refcnt 0", c->name);
+		return;
+	}
+	if (c->refcnt == 1) {
+		if (c->ops && c->ops->disable)
+			c->ops->disable(c);
+
+		if (c->parent)
+			clk_disable_locked(c->parent);
+
+		c->state = OFF;
+	}
+	c->refcnt--;
+}
+
+void clk_disable(struct clk *c)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&clock_lock, flags);
+	clk_disable_locked(c);
+	spin_unlock_irqrestore(&clock_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+int clk_set_parent_locked(struct clk *c, struct clk *parent)
+{
+	int ret;
+
+	pr_debug("%s: %s\n", __func__, c->name);
+
+	if (!c->ops || !c->ops->set_parent)
+		return -ENOSYS;
+
+	ret = c->ops->set_parent(c, parent);
+
+	if (ret)
+		return ret;
+
+	propagate_rate(c);
+
+	return 0;
+}
+
+int clk_set_parent(struct clk *c, struct clk *parent)
+{
+	int ret;
+	unsigned long flags;
+	spin_lock_irqsave(&clock_lock, flags);
+	ret = clk_set_parent_locked(c, parent);
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *c)
+{
+	return c->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+int clk_set_rate(struct clk *c, unsigned long rate)
+{
+	int ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clock_lock, flags);
+
+	pr_debug("%s: %s\n", __func__, c->name);
+
+	if (c->ops && c->ops->set_rate)
+		ret = c->ops->set_rate(c, rate);
+	else
+		ret = -ENOSYS;
+
+	propagate_rate(c);
+
+	spin_unlock_irqrestore(&clock_lock, flags);
+
+	return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+unsigned long clk_get_rate(struct clk *c)
+{
+	unsigned long flags;
+	unsigned long ret;
+
+	spin_lock_irqsave(&clock_lock, flags);
+
+	pr_debug("%s: %s\n", __func__, c->name);
+
+	ret = c->rate;
+
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+int __init tegra_init_clock(void)
+{
+	tegra2_init_clocks();
+
+	return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static struct dentry *clk_debugfs_root;
+
+
+static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
+{
+	struct clk *child;
+	struct clk *safe;
+	const char *state = "uninit";
+	char div[5] = {0};
+
+	if (c->state == ON)
+		state = "on";
+	else if (c->state == OFF)
+		state = "off";
+
+	if (c->mul != 0 && c->div != 0) {
+		BUG_ON(c->mul > 2);
+		if (c->mul > c->div)
+			snprintf(div, sizeof(div), "x%d", c->mul / c->div);
+		else
+			snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
+				(c->div % c->mul) ? ".5" : "");
+	}
+
+	seq_printf(s, "%*s%-*s %-6s %-3d %-5s %-10lu\n",
+		level * 3 + 1, c->set ? "" : "*",
+		30 - level * 3, c->name,
+		state, c->refcnt, div, c->rate);
+	list_for_each_entry_safe(child, safe, &c->children, sibling) {
+		clock_tree_show_one(s, child, level + 1);
+	}
+}
+
+static int clock_tree_show(struct seq_file *s, void *data)
+{
+	struct clk *c;
+	unsigned long flags;
+	seq_printf(s, " clock                          state  ref div   rate      \n");
+	seq_printf(s, "-----------------------------------------------------------\n");
+	spin_lock_irqsave(&clock_lock, flags);
+	list_for_each_entry(c, &clocks, node)
+		if (c->parent == NULL)
+			clock_tree_show_one(s, c, 0);
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return 0;
+}
+
+static int clock_tree_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, clock_tree_show, inode->i_private);
+}
+
+static const struct file_operations clock_tree_fops = {
+	.open		= clock_tree_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int possible_parents_show(struct seq_file *s, void *data)
+{
+	struct clk *c = s->private;
+	int i;
+
+	for (i = 0; c->inputs[i].input; i++) {
+		char *first = (i == 0) ? "" : " ";
+		seq_printf(s, "%s%s", first, c->inputs[i].input->name);
+	}
+	seq_printf(s, "\n");
+	return 0;
+}
+
+static int possible_parents_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, possible_parents_show, inode->i_private);
+}
+
+static const struct file_operations possible_parents_fops = {
+	.open		= possible_parents_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int clk_debugfs_register_one(struct clk *c)
+{
+	struct dentry *d, *child, *child_tmp;
+
+	d = debugfs_create_dir(c->name, clk_debugfs_root);
+	if (!d)
+		return -ENOMEM;
+	c->dent = d;
+
+	d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
+	if (!d)
+		goto err_out;
+
+	if (c->inputs) {
+		d = debugfs_create_file("possible_parents", S_IRUGO, c->dent,
+			c, &possible_parents_fops);
+		if (!d)
+			goto err_out;
+	}
+
+	return 0;
+
+err_out:
+	d = c->dent;
+	list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
+		debugfs_remove(child);
+	debugfs_remove(c->dent);
+	return -ENOMEM;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+	int err;
+	struct clk *pa = c->parent;
+
+	if (pa && !pa->dent) {
+		err = clk_debugfs_register(pa);
+		if (err)
+			return err;
+	}
+
+	if (!c->dent) {
+		err = clk_debugfs_register_one(c);
+		if (err)
+			return err;
+	}
+	return 0;
+}
+
+static int __init clk_debugfs_init(void)
+{
+	struct clk *c;
+	struct dentry *d;
+	int err = -ENOMEM;
+
+	d = debugfs_create_dir("clock", NULL);
+	if (!d)
+		return -ENOMEM;
+	clk_debugfs_root = d;
+
+	d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
+		&clock_tree_fops);
+	if (!d)
+		goto err_out;
+
+	list_for_each_entry(c, &clocks, node) {
+		err = clk_debugfs_register(c);
+		if (err)
+			goto err_out;
+	}
+	return 0;
+err_out:
+	debugfs_remove_recursive(clk_debugfs_root);
+	return err;
+}
+
+late_initcall(clk_debugfs_init);
+#endif
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
new file mode 100644
index 0000000..54b21b8
--- /dev/null
+++ b/arch/arm/mach-tegra/clock.h
@@ -0,0 +1,133 @@
+/*
+ * arch/arm/mach-tegra/include/mach/clock.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_CLOCK_H
+#define __MACH_TEGRA_CLOCK_H
+
+#include <asm/clkdev.h>
+
+#define DIV_BUS		0x00000001
+#define DIV_U71		0x00000002
+#define DIV_U71_FIXED	0x00000004
+#define DIV_2		0x00000008
+#define PLL_FIXED	0x00000010
+#define PLL_HAS_CPCON	0x00000020
+#define MUX		0x00000040
+#define PLLD		0x00000080
+#define PERIPH_NO_RESET	0x00000100
+#define PERIPH_NO_ENB	0x00000200
+#define PERIPH_EMC_ENB	0x00000400
+#define ENABLE_ON_INIT	0x10000000
+struct clk;
+
+struct clk_mux_sel {
+	struct clk	*input;
+	u32		value;
+};
+
+struct clk_pll_table {
+	unsigned long	input_rate;
+	unsigned long	output_rate;
+	u16		n;
+	u16		m;
+	u8		p;
+	u8		cpcon;
+};
+
+struct clk_ops {
+	void		(*init)(struct clk *);
+	int		(*enable)(struct clk *);
+	void		(*disable)(struct clk *);
+	void		(*recalc)(struct clk *);
+	int		(*set_parent)(struct clk *, struct clk *);
+	int		(*set_rate)(struct clk *, unsigned long);
+	unsigned long	(*get_rate)(struct clk *);
+	long		(*round_rate)(struct clk *, unsigned long);
+	unsigned long	(*recalculate_rate)(struct clk *);
+};
+
+enum clk_state {
+	UNINITIALIZED = 0,
+	ON,
+	OFF,
+};
+
+struct clk {
+	/* node for master clocks list */
+	struct list_head		node;
+	struct list_head		children;	/* list of children */
+	struct list_head		sibling;	/* node for children */
+#ifdef CONFIG_DEBUG_FS
+	struct dentry			*dent;
+	struct dentry			*parent_dent;
+#endif
+	struct clk_ops			*ops;
+	struct clk			*parent;
+	struct clk_lookup		lookup;
+	unsigned long			rate;
+	u32				flags;
+	u32				refcnt;
+	const char			*name;
+	u32				reg;
+	u32				reg_shift;
+	unsigned int			clk_num;
+	enum clk_state			state;
+#ifdef CONFIG_DEBUG_FS
+	bool				set;
+#endif
+
+	/* PLL */
+	unsigned long			input_min;
+	unsigned long			input_max;
+	unsigned long			cf_min;
+	unsigned long			cf_max;
+	unsigned long			vco_min;
+	unsigned long			vco_max;
+	u32				m;
+	u32				n;
+	u32				p;
+	u32				cpcon;
+	const struct clk_pll_table	*pll_table;
+
+	/* DIV */
+	u32				div;
+	u32				mul;
+
+	/* MUX */
+	const struct clk_mux_sel	*inputs;
+	u32				sel;
+	u32				reg_mask;
+};
+
+
+struct clk_duplicate {
+	const char *name;
+	struct clk_lookup lookup;
+};
+
+void tegra2_init_clocks(void);
+void clk_init(struct clk *clk);
+struct clk *get_tegra_clock_by_name(const char *name);
+unsigned long clk_measure_input_freq(void);
+void clk_disable_locked(struct clk *c);
+int clk_enable_locked(struct clk *c);
+int clk_set_parent_locked(struct clk *c, struct clk *parent);
+int clk_reparent(struct clk *c, struct clk *parent);
+
+#endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 20875ee..838bb5d 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -40,5 +40,6 @@ void __init tegra_init_cache(void)
 
 void __init tegra_common_init(void)
 {
+	tegra_init_clock();
 	tegra_init_cache();
 }
diff --git a/arch/arm/mach-tegra/include/mach/clkdev.h b/arch/arm/mach-tegra/include/mach/clkdev.h
new file mode 100644
index 0000000..412f5c6
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/clkdev.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-tegra/include/mach/clkdev.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+static inline int __clk_get(struct clk *clk)
+{
+	return 1;
+}
+
+static inline void __clk_put(struct clk *clk)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
new file mode 100644
index 0000000..7206653
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -0,0 +1,1341 @@
+/*
+ * arch/arm/mach-tegra/tegra2_clocks.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/iomap.h>
+
+#include "clock.h"
+
+#define RST_DEVICES			0x004
+#define RST_DEVICES_SET			0x300
+#define RST_DEVICES_CLR			0x304
+
+#define CLK_OUT_ENB			0x010
+#define CLK_OUT_ENB_SET			0x320
+#define CLK_OUT_ENB_CLR			0x324
+
+#define OSC_CTRL			0x50
+#define OSC_CTRL_OSC_FREQ_MASK		(3<<30)
+#define OSC_CTRL_OSC_FREQ_13MHZ		(0<<30)
+#define OSC_CTRL_OSC_FREQ_19_2MHZ	(1<<30)
+#define OSC_CTRL_OSC_FREQ_12MHZ		(2<<30)
+#define OSC_CTRL_OSC_FREQ_26MHZ		(3<<30)
+
+#define OSC_FREQ_DET			0x58
+#define OSC_FREQ_DET_TRIG		(1<<31)
+
+#define OSC_FREQ_DET_STATUS		0x5C
+#define OSC_FREQ_DET_BUSY		(1<<31)
+#define OSC_FREQ_DET_CNT_MASK		0xFFFF
+
+#define PERIPH_CLK_SOURCE_MASK		(3<<30)
+#define PERIPH_CLK_SOURCE_SHIFT		30
+#define PERIPH_CLK_SOURCE_ENABLE	(1<<28)
+#define PERIPH_CLK_SOURCE_DIV_MASK	0xFF
+#define PERIPH_CLK_SOURCE_DIV_SHIFT	0
+
+#define PLL_BASE			0x0
+#define PLL_BASE_BYPASS			(1<<31)
+#define PLL_BASE_ENABLE			(1<<30)
+#define PLL_BASE_REF_ENABLE		(1<<29)
+#define PLL_BASE_OVERRIDE		(1<<28)
+#define PLL_BASE_LOCK			(1<<27)
+#define PLL_BASE_DIVP_MASK		(0x7<<20)
+#define PLL_BASE_DIVP_SHIFT		20
+#define PLL_BASE_DIVN_MASK		(0x3FF<<8)
+#define PLL_BASE_DIVN_SHIFT		8
+#define PLL_BASE_DIVM_MASK		(0x1F)
+#define PLL_BASE_DIVM_SHIFT		0
+
+#define PLL_OUT_RATIO_MASK		(0xFF<<8)
+#define PLL_OUT_RATIO_SHIFT		8
+#define PLL_OUT_OVERRIDE		(1<<2)
+#define PLL_OUT_CLKEN			(1<<1)
+#define PLL_OUT_RESET_DISABLE		(1<<0)
+
+#define PLL_MISC			0xc
+#define PLL_MISC_DCCON_SHIFT		20
+#define PLL_MISC_LOCK_ENABLE		(1<<18)
+#define PLL_MISC_CPCON_SHIFT		8
+#define PLL_MISC_CPCON_MASK		(0xF<<PLL_MISC_CPCON_SHIFT)
+#define PLL_MISC_LFCON_SHIFT		4
+#define PLL_MISC_LFCON_MASK		(0xF<<PLL_MISC_LFCON_SHIFT)
+#define PLL_MISC_VCOCON_SHIFT		0
+#define PLL_MISC_VCOCON_MASK		(0xF<<PLL_MISC_VCOCON_SHIFT)
+
+#define PLLD_MISC_CLKENABLE		(1<<30)
+#define PLLD_MISC_DIV_RST		(1<<23)
+#define PLLD_MISC_DCCON_SHIFT		12
+
+#define PERIPH_CLK_TO_ENB_REG(c)	((c->clk_num / 32) * 4)
+#define PERIPH_CLK_TO_ENB_SET_REG(c)	((c->clk_num / 32) * 8)
+#define PERIPH_CLK_TO_ENB_BIT(c)	(1 << (c->clk_num % 32))
+
+#define SUPER_CLK_MUX			0x00
+#define SUPER_STATE_SHIFT		28
+#define SUPER_STATE_MASK		(0xF << SUPER_STATE_SHIFT)
+#define SUPER_STATE_STANDBY		(0x0 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IDLE		(0x1 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_RUN			(0x2 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IRQ			(0x3 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_FIQ			(0x4 << SUPER_STATE_SHIFT)
+#define SUPER_SOURCE_MASK		0xF
+#define	SUPER_FIQ_SOURCE_SHIFT		12
+#define	SUPER_IRQ_SOURCE_SHIFT		8
+#define	SUPER_RUN_SOURCE_SHIFT		4
+#define	SUPER_IDLE_SOURCE_SHIFT		0
+
+#define SUPER_CLK_DIVIDER		0x04
+
+#define BUS_CLK_DISABLE			(1<<3)
+#define BUS_CLK_DIV_MASK		0x3
+
+static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+
+#define clk_writel(value, reg) \
+	__raw_writel(value, (u32)reg_clk_base + (reg))
+#define clk_readl(reg) \
+	__raw_readl((u32)reg_clk_base + (reg))
+
+unsigned long clk_measure_input_freq(void)
+{
+	u32 clock_autodetect;
+
+	clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
+
+	while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY)
+		;
+
+	clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
+
+	if (clock_autodetect >= 732 - 3 &&
+	    clock_autodetect <= 732 + 3) {
+		return 12000000;
+	} else if (clock_autodetect >= 794 - 3 &&
+		   clock_autodetect <= 794 + 3) {
+		return 13000000;
+	} else if (clock_autodetect >= 1172 - 3 &&
+		   clock_autodetect <= 1172 + 3) {
+		return 19200000;
+	} else if (clock_autodetect >= 1587 - 3 &&
+		   clock_autodetect <= 1587 + 3) {
+		return 26000000;
+	} else {
+		pr_err("%s: Unexpected clock autodetect value %d",
+		       __func__, clock_autodetect);
+		BUG();
+		return 0;
+	}
+}
+
+static int clk_div71_possible_rate(struct clk *c, unsigned long rate)
+{
+	unsigned long input_rate = c->rate;
+	int divider_u71;
+
+	divider_u71 = (input_rate*2)/rate;
+	if (rate * divider_u71 == input_rate*2)
+		return divider_u71 - 2;
+	else
+		return -EINVAL;
+}
+
+static unsigned long tegra2_clk_recalculate_rate(struct clk *c)
+{
+	unsigned long rate;
+	rate = c->parent->rate;
+
+	if (c->mul != 0 && c->div != 0)
+		c->rate = rate * c->mul / c->div;
+	else
+		c->rate = rate;
+	return c->rate;
+}
+
+
+/* clk_m functions */
+static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
+{
+	u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
+
+	c->rate = clk_measure_input_freq();
+	switch (c->rate) {
+	case 12000000:
+		auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
+		break;
+	case 13000000:
+		auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
+		break;
+	case 19200000:
+		auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
+		break;
+	case 26000000:
+		auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
+		break;
+	default:
+		pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
+		BUG();
+	}
+	clk_writel(auto_clock_control, OSC_CTRL);
+	return c->rate;
+}
+
+static void tegra2_clk_m_init(struct clk *c)
+{
+	pr_debug("%s on clock %s\n", __func__, c->name);
+	tegra2_clk_m_autodetect_rate(c);
+}
+
+static int tegra2_clk_m_enable(struct clk *c)
+{
+	pr_debug("%s on clock %s\n", __func__, c->name);
+	return 0;
+}
+
+static void tegra2_clk_m_disable(struct clk *c)
+{
+	pr_debug("%s on clock %s\n", __func__, c->name);
+	BUG();
+}
+
+static struct clk_ops tegra_clk_m_ops = {
+	.init     = tegra2_clk_m_init,
+	.enable   = tegra2_clk_m_enable,
+	.disable  = tegra2_clk_m_disable,
+};
+
+/* super clock functions */
+/* "super clocks" on tegra have two-stage muxes and a clock skipping
+ * super divider.  We will ignore the clock skipping divider, since we
+ * can't lower the voltage when using the clock skip, but we can if we
+ * lower the PLL frequency.
+ */
+static void tegra2_super_clk_init(struct clk *c)
+{
+	u32 val;
+	int source;
+	int shift;
+	const struct clk_mux_sel *sel;
+
+	val = clk_readl(c->reg + SUPER_CLK_MUX);
+	c->state = ON;
+	BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+		((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+	shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+		SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+	source = (val >> shift) & SUPER_SOURCE_MASK;
+	pr_info("%s %s %d\n", __func__, c->name, source);
+	for (sel = c->inputs; sel->input != NULL; sel++) {
+		if (sel->value == source)
+			break;
+	}
+	BUG_ON(sel->input == NULL);
+	c->parent = sel->input;
+	tegra2_clk_recalculate_rate(c);
+}
+
+static int tegra2_super_clk_enable(struct clk *c)
+{
+	clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
+	return 0;
+}
+
+static void tegra2_super_clk_disable(struct clk *c)
+{
+	pr_debug("%s on clock %s\n", __func__, c->name);
+
+	/* oops - don't disable the CPU clock! */
+	BUG();
+}
+
+static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
+{
+	u32 val;
+	const struct clk_mux_sel *sel;
+	int shift;
+
+	val = clk_readl(c->reg + SUPER_CLK_MUX);;
+	BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+		((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+	shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+		SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+	for (sel = c->inputs; sel->input != NULL; sel++) {
+		if (sel->input == p) {
+			clk_reparent(c, p);
+			val &= ~(SUPER_SOURCE_MASK << shift);
+			val |= sel->value << shift;
+			clk_writel(val, c->reg);
+			c->rate = c->parent->rate;
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+static struct clk_ops tegra_super_ops = {
+	.init     = tegra2_super_clk_init,
+	.enable   = tegra2_super_clk_enable,
+	.disable  = tegra2_super_clk_disable,
+	.set_parent = tegra2_super_clk_set_parent,
+	.recalculate_rate = tegra2_clk_recalculate_rate,
+};
+
+/* bus clock functions */
+static void tegra2_bus_clk_init(struct clk *c)
+{
+	u32 val = clk_readl(c->reg);
+
+	c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
+	c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
+	c->mul = 1;
+	tegra2_clk_recalculate_rate(c);
+}
+
+static int tegra2_bus_clk_enable(struct clk *c)
+{
+	u32 val = clk_readl(c->reg);
+
+	val &= ~(BUS_CLK_DISABLE << c->reg_shift);
+	clk_writel(val, c->reg);
+	return 0;
+}
+
+static void tegra2_bus_clk_disable(struct clk *c)
+{
+	u32 val = clk_readl(c->reg);
+
+	val |= BUS_CLK_DISABLE << c->reg_shift;
+	clk_writel(val, c->reg);
+}
+
+static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	u32 val = clk_readl(c->reg);
+	unsigned long parent_rate = c->parent->rate;
+	int i;
+
+	for (i = 1; i <= 4; i++) {
+		if (rate == parent_rate / i) {
+			val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
+			val |= (i - 1) << c->reg_shift;
+			clk_writel(val, c->reg);
+			c->div = i;
+			c->mul = 1;
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+static struct clk_ops tegra_bus_ops = {
+	.init     = tegra2_bus_clk_init,
+	.enable   = tegra2_bus_clk_enable,
+	.disable  = tegra2_bus_clk_disable,
+	.set_rate = tegra2_bus_clk_set_rate,
+	.recalculate_rate = tegra2_clk_recalculate_rate,
+};
+
+/* PLL Functions */
+static unsigned long tegra2_pll_clk_recalculate_rate(struct clk *c)
+{
+	u64 rate;
+
+	rate = c->parent->rate;
+	rate *= c->n;
+	do_div(rate, c->m);
+	if (c->p == 2)
+		rate >>= 1;
+	c->rate = rate;
+	return c->rate;
+}
+
+static void tegra2_pll_clk_init(struct clk *c)
+{
+	u32 val = clk_readl(c->reg + PLL_BASE);
+
+	c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+
+	if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+		pr_warning("Clock %s has unknown fixed frequency\n", c->name);
+		c->n = 1;
+		c->m = 0;
+		c->p = 1;
+	} else if (val & PLL_BASE_BYPASS) {
+		c->n = 1;
+		c->m = 1;
+		c->p = 1;
+	} else {
+		c->n = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+		c->m = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+		c->p = (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
+	}
+
+	val = clk_readl(c->reg + PLL_MISC);
+	if (c->flags & PLL_HAS_CPCON)
+		c->cpcon = (val & PLL_MISC_CPCON_MASK) >> PLL_MISC_CPCON_SHIFT;
+
+	tegra2_pll_clk_recalculate_rate(c);
+}
+
+static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	u32 val;
+	unsigned long input_rate;
+	const struct clk_pll_table *sel;
+
+	pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+	/* BUG_ON(c->refcnt != 0); */
+
+	input_rate = c->parent->rate;
+	for (sel = c->pll_table; sel->input_rate != 0; sel++) {
+		if (sel->input_rate == input_rate && sel->output_rate == rate) {
+			c->n = sel->n;
+			c->m = sel->m;
+			c->p = sel->p;
+			c->cpcon = sel->cpcon;
+			val = clk_readl(c->reg + PLL_BASE);
+			if (c->flags & PLL_FIXED)
+				val |= PLL_BASE_OVERRIDE;
+			val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
+				 PLL_BASE_DIVM_MASK);
+			val |= (c->m << PLL_BASE_DIVM_SHIFT) |
+				(c->n << PLL_BASE_DIVN_SHIFT);
+			BUG_ON(c->p > 2);
+			if (c->p == 2)
+				val |= 1 << PLL_BASE_DIVP_SHIFT;
+			clk_writel(val, c->reg + PLL_BASE);
+			c->rate = rate;
+
+			if (c->flags & PLL_HAS_CPCON) {
+				val = c->cpcon << PLL_MISC_CPCON_SHIFT;
+				clk_writel(val, c->reg + PLL_MISC);
+			}
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+static int tegra2_pll_clk_enable(struct clk *c)
+{
+	u32 val;
+
+	pr_debug("%s on clock %s\n", __func__, c->name);
+
+	val = clk_readl(c->reg + PLL_BASE);
+	val &= ~PLL_BASE_BYPASS;
+	val |= PLL_BASE_ENABLE;
+	clk_writel(val, c->reg + PLL_BASE);
+	return 0;
+}
+
+static void tegra2_pll_clk_disable(struct clk *c)
+{
+	u32 val;
+
+	pr_debug("%s on clock %s\n", __func__, c->name);
+
+	val = clk_readl(c->reg);
+	val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+	clk_writel(val, c->reg);
+}
+
+static struct clk_ops tegra_pll_ops = {
+	.init     = tegra2_pll_clk_init,
+	.enable   = tegra2_pll_clk_enable,
+	.disable  = tegra2_pll_clk_disable,
+	.set_rate = tegra2_pll_clk_set_rate,
+	.recalculate_rate = tegra2_pll_clk_recalculate_rate,
+};
+
+/* Clock divider ops */
+static void tegra2_pll_div_clk_init(struct clk *c)
+{
+	u32 val = clk_readl(c->reg);
+	u32 divu71;
+
+	val >>= c->reg_shift;
+	c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
+	if (!(val & PLL_OUT_RESET_DISABLE))
+		c->state = OFF;
+
+	if (c->flags & DIV_U71) {
+		divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+		c->div = (divu71 + 2);
+		c->mul = 2;
+	} else if (c->flags & DIV_2) {
+		c->div = 2;
+		c->mul = 1;
+	} else {
+		c->div = 1;
+		c->mul = 1;
+	}
+
+	tegra2_clk_recalculate_rate(c);
+}
+
+static int tegra2_pll_div_clk_enable(struct clk *c)
+{
+	u32 val;
+	u32 new_val;
+
+	pr_debug("%s: %s\n", __func__, c->name);
+	if (c->flags & DIV_U71) {
+		val = clk_readl(c->reg);
+		new_val = val >> c->reg_shift;
+		new_val &= 0xFFFF;
+
+		new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
+
+		val &= ~(0xFFFF << c->reg_shift);
+		val |= new_val << c->reg_shift;
+		clk_writel(val, c->reg);
+		return 0;
+	} else if (c->flags & DIV_2) {
+		BUG_ON(!(c->flags & PLLD));
+		val = clk_readl(c->reg);
+		val &= ~PLLD_MISC_DIV_RST;
+		clk_writel(val, c->reg);
+		return 0;
+	}
+	return -EINVAL;
+}
+
+static void tegra2_pll_div_clk_disable(struct clk *c)
+{
+	u32 val;
+	u32 new_val;
+
+	pr_debug("%s: %s\n", __func__, c->name);
+	if (c->flags & DIV_U71) {
+		val = clk_readl(c->reg);
+		new_val = val >> c->reg_shift;
+		new_val &= 0xFFFF;
+
+		new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
+
+		val &= ~(0xFFFF << c->reg_shift);
+		val |= new_val << c->reg_shift;
+		clk_writel(val, c->reg);
+	} else if (c->flags & DIV_2) {
+		BUG_ON(!(c->flags & PLLD));
+		val = clk_readl(c->reg);
+		val |= PLLD_MISC_DIV_RST;
+		clk_writel(val, c->reg);
+	}
+}
+
+static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	u32 val;
+	u32 new_val;
+	int divider_u71;
+
+	pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+	if (c->flags & DIV_U71) {
+		divider_u71 = clk_div71_possible_rate(c->parent, rate);
+		if (divider_u71 >= 0) {
+			val = clk_readl(c->reg);
+			new_val = val >> c->reg_shift;
+			new_val &= 0xFFFF;
+			if (c->flags & DIV_U71_FIXED)
+				new_val |= PLL_OUT_OVERRIDE;
+			new_val &= ~PLL_OUT_RATIO_MASK;
+			new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
+
+			val &= ~(0xFFFF << c->reg_shift);
+			val |= new_val << c->reg_shift;
+			clk_writel(val, c->reg);
+			c->rate = rate;
+			return 0;
+		}
+	} else if (c->flags & DIV_2) {
+		if (c->parent->rate == rate * 2) {
+			c->rate = rate;
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+
+static struct clk_ops tegra_pll_div_ops = {
+	.init     = tegra2_pll_div_clk_init,
+	.enable   = tegra2_pll_div_clk_enable,
+	.disable  = tegra2_pll_div_clk_disable,
+	.set_rate = tegra2_pll_div_clk_set_rate,
+	.recalculate_rate = tegra2_clk_recalculate_rate,
+};
+
+/* Periph clk ops */
+
+static void tegra2_periph_clk_init(struct clk *c)
+{
+	u32 val = clk_readl(c->reg);
+	const struct clk_mux_sel *mux = 0;
+	const struct clk_mux_sel *sel;
+
+	if (c->flags & MUX) {
+		for (sel = c->inputs; sel->input != NULL; sel++) {
+			if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
+				mux = sel;
+		}
+		BUG_ON(!mux);
+
+		c->parent = mux->input;
+	} else {
+		c->parent = c->inputs[0].input;
+	}
+
+	if (c->flags & DIV_U71) {
+		u32 divu71 = val & PERIPH_CLK_SOURCE_DIV_MASK;
+		c->div = divu71 + 2;
+		c->mul = 2;
+	} else {
+		c->div = 1;
+		c->mul = 1;
+	}
+
+	c->state = ON;
+	if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+			PERIPH_CLK_TO_ENB_BIT(c)))
+		c->state = OFF;
+	if (!(c->flags & PERIPH_NO_RESET))
+		if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
+				PERIPH_CLK_TO_ENB_BIT(c))
+			c->state = OFF;
+	tegra2_clk_recalculate_rate(c);
+}
+
+static int tegra2_periph_clk_enable(struct clk *c)
+{
+	u32 val;
+
+	pr_debug("%s on clock %s\n", __func__, c->name);
+
+	clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+		CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
+	if (!(c->flags & PERIPH_NO_RESET))
+		clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+			RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+	if (c->flags & PERIPH_EMC_ENB) {
+		/* The EMC peripheral clock has 2 extra enable bits */
+		/* FIXME: Do they need to be disabled? */
+		val = clk_readl(c->reg);
+		val |= 0x3 << 24;
+		clk_writel(val, c->reg);
+	}
+	return 0;
+}
+
+static void tegra2_periph_clk_disable(struct clk *c)
+{
+	pr_debug("%s on clock %s\n", __func__, c->name);
+
+	clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+		CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+}
+
+static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
+{
+	u32 val;
+	const struct clk_mux_sel *sel;
+
+	pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+
+	for (sel = c->inputs; sel->input != NULL; sel++) {
+		if (sel->input == p) {
+			clk_reparent(c, p);
+			val = clk_readl(c->reg);
+			val &= ~PERIPH_CLK_SOURCE_MASK;
+			val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
+			clk_writel(val, c->reg);
+			c->rate = c->parent->rate;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	u32 val;
+	int divider_u71;
+	const struct clk_mux_sel *sel;
+
+	pr_debug("%s: %lu\n", __func__, rate);
+
+	for (sel = c->inputs; sel->input != NULL; sel++) {
+		if (c->flags & DIV_U71) {
+			divider_u71 = clk_div71_possible_rate(sel->input, rate);
+			if (divider_u71 >= 0) {
+				/* FIXME: ensure we don't go through a too-high rate */
+				clk_set_parent_locked(c, sel->input);
+				udelay(1);
+				val = clk_readl(c->reg);
+				val &= ~PERIPH_CLK_SOURCE_DIV_MASK;
+				val |= divider_u71;
+				clk_writel(val, c->reg);
+				c->rate = rate;
+				return 0;
+			}
+		} else {
+			if (sel->input->rate == rate) {
+				clk_set_parent_locked(c, sel->input);
+				return 0;
+			}
+		}
+	}
+	return -EINVAL;
+}
+
+static struct clk_ops tegra_periph_clk_ops = {
+	.init       = &tegra2_periph_clk_init,
+	.enable     = &tegra2_periph_clk_enable,
+	.disable    = &tegra2_periph_clk_disable,
+	.set_parent = &tegra2_periph_clk_set_parent,
+	.set_rate   = &tegra2_periph_clk_set_rate,
+	.recalculate_rate = &tegra2_clk_recalculate_rate,
+};
+
+/* Clock doubler ops */
+static void tegra2_clk_double_init(struct clk *c)
+{
+	c->mul = 2;
+	c->div = 1;
+	c->state = ON;
+	if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+			PERIPH_CLK_TO_ENB_BIT(c)))
+		c->state = OFF;
+	tegra2_clk_recalculate_rate(c);
+};
+
+static struct clk_ops tegra_clk_double_ops = {
+	.init       = &tegra2_clk_double_init,
+	.enable     = &tegra2_periph_clk_enable,
+	.disable    = &tegra2_periph_clk_disable,
+	.recalculate_rate = &tegra2_clk_recalculate_rate,
+};
+
+/* Clock definitions */
+static struct clk tegra_clk_32k = {
+	.name = "tegra_clk_32k",
+	.rate = 32678,
+	.ops  = NULL,
+};
+
+static struct clk_pll_table tegra_pll_s_table[] = {
+	{32768, 12000000, 366, 1, 1, 0},
+	{32768, 13000000, 397, 1, 1, 0},
+	{32768, 19200000, 586, 1, 1, 0},
+	{32768, 26000000, 793, 1, 1, 0},
+	{0, 0, 0, 0, 0, 0},
+};
+
+static struct clk tegra_pll_s = {
+	.name = "tegra_pll_s",
+	.ops = &tegra_pll_ops,
+	.reg       = 0xf0,
+	.input_min = 32768,
+	.input_max = 32768,
+	.parent     = &tegra_clk_32k,
+	.cf_min    = 0, /* FIXME */
+	.cf_max    = 0, /* FIXME */
+	.vco_min   = 12000000,
+	.vco_max   = 26000000,
+	.pll_table = tegra_pll_s_table,
+};
+
+static struct clk_mux_sel tegra_clk_m_sel[] = {
+	{ .input = &tegra_clk_32k, .value = 0},
+	{ .input = &tegra_pll_s,  .value = 1},
+	{ 0, 0},
+};
+static struct clk tegra_clk_m = {
+	.name      = "tegra_clk_m",
+	.flags     = ENABLE_ON_INIT,
+	.ops       = &tegra_clk_m_ops,
+	.inputs    = tegra_clk_m_sel,
+	.reg       = 0x1fc,
+	.reg_mask  = (1<<28),
+	.reg_shift = 28,
+};
+
+static struct clk_pll_table tegra_pll_c_table[] = {
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_c = {
+	.name      = "tegra_pll_c",
+	.flags	   = PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0x80,
+	.input_min = 2000000,
+	.input_max = 31000000,
+	.parent    = &tegra_clk_m,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 20000000,
+	.vco_max   = 1400000000,
+	.pll_table = tegra_pll_c_table,
+};
+
+static struct clk tegra_pll_c_out1 = {
+	.name      = "tegra_pll_c_out1",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = DIV_U71,
+	.parent    = &tegra_pll_c,
+	.reg       = 0x84,
+	.reg_shift = 0,
+};
+
+static struct clk_pll_table tegra_pll_m_table[] = {
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_m = {
+	.name      = "tegra_pll_m",
+	.flags     = PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0x90,
+	.input_min = 2000000,
+	.input_max = 31000000,
+	.parent    = &tegra_clk_m,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 20000000,
+	.vco_max   = 1200000000,
+	.pll_table = tegra_pll_m_table,
+};
+
+static struct clk tegra_pll_m_out1 = {
+	.name      = "tegra_pll_m_out1",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = DIV_U71,
+	.parent    = &tegra_pll_m,
+	.reg       = 0x94,
+	.reg_shift = 0,
+};
+
+static struct clk_pll_table tegra_pll_p_table[] = {
+	{ 12000000, 216000000, 432, 12, 2, 8},
+	{ 13000000, 216000000, 432, 13, 2, 8},
+	{ 19200000, 216000000, 90,   4, 2, 1},
+	{ 26000000, 216000000, 432, 26, 2, 8},
+	{ 12000000, 432000000, 432, 12, 1, 8},
+	{ 13000000, 432000000, 432, 13, 1, 8},
+	{ 19200000, 432000000, 90,   4, 1, 1},
+	{ 26000000, 432000000, 432, 26, 1, 8},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_p = {
+	.name      = "tegra_pll_p",
+	.flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xa0,
+	.input_min = 2000000,
+	.input_max = 31000000,
+	.parent    = &tegra_clk_m,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 20000000,
+	.vco_max   = 1400000000,
+	.pll_table = tegra_pll_p_table,
+};
+
+static struct clk tegra_pll_p_out1 = {
+	.name      = "tegra_pll_p_out1",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa4,
+	.reg_shift = 0,
+};
+
+static struct clk tegra_pll_p_out2 = {
+	.name      = "tegra_pll_p_out2",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa4,
+	.reg_shift = 16,
+};
+
+static struct clk tegra_pll_p_out3 = {
+	.name      = "tegra_pll_p_out3",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa8,
+	.reg_shift = 0,
+};
+
+static struct clk tegra_pll_p_out4 = {
+	.name      = "tegra_pll_p_out4",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa8,
+	.reg_shift = 16,
+};
+
+static struct clk_pll_table tegra_pll_a_table[] = {
+	{ 28800000, 56448000, 49, 25, 1, 1},
+	{ 28800000, 73728000, 64, 25, 1, 1},
+	{ 28800000, 11289600, 49, 25, 1, 1},
+	{ 28800000, 12288000, 64, 25, 1, 1},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_a = {
+	.name      = "tegra_pll_a",
+	.flags     = PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xb0,
+	.input_min = 2000000,
+	.input_max = 31000000,
+	.parent    = &tegra_pll_p_out1,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 20000000,
+	.vco_max   = 1400000000,
+	.pll_table = tegra_pll_a_table,
+};
+
+static struct clk tegra_pll_a_out0 = {
+	.name      = "tegra_pll_a_out0",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = DIV_U71,
+	.parent    = &tegra_pll_a,
+	.reg       = 0xb4,
+	.reg_shift = 0,
+};
+
+static struct clk_pll_table tegra_pll_d_table[] = {
+	{ 12000000, 1000000000, 1000, 12, 1, 12},
+	{ 13000000, 1000000000, 1000, 13, 1, 12},
+	{ 19200000, 1000000000, 625,  12, 1, 8},
+	{ 26000000, 1000000000, 1000, 26, 1, 12},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_d = {
+	.name      = "tegra_pll_d",
+	.flags     = PLL_HAS_CPCON | PLLD,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xd0,
+	.input_min = 2000000,
+	.input_max = 40000000,
+	.parent    = &tegra_clk_m,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 40000000,
+	.vco_max   = 1000000000,
+	.pll_table = tegra_pll_d_table,
+};
+
+static struct clk tegra_pll_d_out0 = {
+	.name      = "tegra_pll_d_out0",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = DIV_2 | PLLD,
+	.parent    = &tegra_pll_d,
+};
+
+static struct clk_pll_table tegra_pll_u_table[] = {
+	{ 12000000, 480000000, 960, 12, 1, 0},
+	{ 13000000, 480000000, 960, 13, 1, 0},
+	{ 19200000, 480000000, 200, 4,  1, 0},
+	{ 26000000, 480000000, 960, 26, 1, 0},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_u = {
+	.name      = "tegra_pll_u",
+	.flags     = 0,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xc0,
+	.input_min = 2000000,
+	.input_max = 40000000,
+	.parent    = &tegra_clk_m,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 480000000,
+	.vco_max   = 960000000,
+	.pll_table = tegra_pll_u_table,
+};
+
+static struct clk_pll_table tegra_pll_x_table[] = {
+	{ 12000000, 1000000000, 1000, 12, 1, 12},
+	{ 13000000, 1000000000, 1000, 13, 1, 12},
+	{ 19200000, 1000000000, 625,  12, 1, 8},
+	{ 26000000, 1000000000, 1000, 26, 1, 12},
+	{ 12000000, 750000000,  750,  12, 1, 12},
+	{ 13000000, 750000000,  750,  13, 1, 12},
+	{ 19200000, 750000000,  625,  16, 1, 8},
+	{ 26000000, 750000000,  750,  26, 1, 12},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_x = {
+	.name      = "tegra_pll_x",
+	.flags     = PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xe0,
+	.input_min = 2000000,
+	.input_max = 31000000,
+	.parent    = &tegra_clk_m,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 20000000,
+	.vco_max   = 1200000000,
+	.pll_table = tegra_pll_x_table,
+};
+
+static struct clk tegra_clk_d = {
+	.name      = "tegra_clk_d",
+	.flags     = PERIPH_NO_RESET,
+	.ops       = &tegra_clk_double_ops,
+	.clk_num   = 90,
+	.reg       = 0x34,
+	.reg_shift = 12,
+	.parent    = &tegra_clk_m,
+};
+
+/* FIXME: need tegra_audio
+static struct clk tegra_clk_audio_2x = {
+	.name      = "tegra_clk_d",
+	.flags     = PERIPH_NO_RESET,
+	.ops       = &tegra_clk_double_ops,
+	.clk_num   = 89,
+	.reg       = 0x34,
+	.reg_shift = 8,
+	.parent    = &tegra_audio,
+}
+*/
+
+static struct clk_mux_sel mux_cclk[] = {
+	{ .input = &tegra_clk_m,	.value = 0},
+	{ .input = &tegra_pll_c,	.value = 1},
+	{ .input = &tegra_clk_32k,	.value = 2},
+	{ .input = &tegra_pll_m,	.value = 3},
+	{ .input = &tegra_pll_p,	.value = 4},
+	{ .input = &tegra_pll_p_out4,	.value = 5},
+	{ .input = &tegra_pll_p_out3,	.value = 6},
+	{ .input = &tegra_clk_d,	.value = 7},
+	{ .input = &tegra_pll_x,	.value = 8},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_sclk[] = {
+	{ .input = &tegra_clk_m,	.value = 0},
+	{ .input = &tegra_pll_c_out1,	.value = 1},
+	{ .input = &tegra_pll_p_out4,	.value = 2},
+	{ .input = &tegra_pll_p_out3,	.value = 3},
+	{ .input = &tegra_pll_p_out2,	.value = 4},
+	{ .input = &tegra_clk_d,	.value = 5},
+	{ .input = &tegra_clk_32k,	.value = 6},
+	{ .input = &tegra_pll_m_out1,	.value = 7},
+	{ 0, 0},
+};
+
+static struct clk tegra_clk_cpu = {
+	.name	= "cpu",
+	.inputs	= mux_cclk,
+	.reg	= 0x20,
+	.ops	= &tegra_super_ops,
+};
+
+static struct clk tegra_clk_sys = {
+	.name	= "sys",
+	.inputs	= mux_sclk,
+	.reg	= 0x28,
+	.ops	= &tegra_super_ops,
+};
+
+static struct clk tegra_clk_hclk = {
+	.name		= "hclk",
+	.flags		= DIV_BUS,
+	.parent		= &tegra_clk_sys,
+	.reg		= 0x30,
+	.reg_shift	= 4,
+	.ops		= &tegra_bus_ops,
+};
+
+static struct clk tegra_clk_pclk = {
+	.name		= "pclk",
+	.flags		= DIV_BUS,
+	.parent		= &tegra_clk_hclk,
+	.reg		= 0x30,
+	.reg_shift	= 0,
+	.ops		= &tegra_bus_ops,
+};
+
+static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
+	{ .input = &tegra_pll_m, .value = 0},
+	{ .input = &tegra_pll_c, .value = 1},
+	{ .input = &tegra_pll_p, .value = 2},
+	{ .input = &tegra_pll_a_out0, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
+	{ .input = &tegra_pll_m, .value = 0},
+	{ .input = &tegra_pll_c, .value = 1},
+	{ .input = &tegra_pll_p, .value = 2},
+	{ .input = &tegra_clk_m, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
+	{ .input = &tegra_pll_p, .value = 0},
+	{ .input = &tegra_pll_c, .value = 1},
+	{ .input = &tegra_pll_m, .value = 2},
+	{ .input = &tegra_clk_m, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_plla_audio_pllp_clkm[] = {
+	{.input = &tegra_pll_a, .value = 0},
+	/* FIXME: no mux defined for tegra_audio
+	{.input = &tegra_audio, .value = 1},*/
+	{.input = &tegra_pll_p, .value = 2},
+	{.input = &tegra_clk_m, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
+	{.input = &tegra_pll_p, .value = 0},
+	{.input = &tegra_pll_d_out0, .value = 1},
+	{.input = &tegra_pll_c, .value = 2},
+	{.input = &tegra_clk_m, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
+	{.input = &tegra_pll_p,     .value = 0},
+	{.input = &tegra_pll_c,     .value = 1},
+	/* FIXME: no mux defined for tegra_audio
+	{.input = &tegra_audio,     .value = 2},*/
+	{.input = &tegra_clk_m,     .value = 3},
+	{.input = &tegra_clk_32k,   .value = 4},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
+	{.input = &tegra_pll_p,     .value = 0},
+	{.input = &tegra_pll_c,     .value = 1},
+	{.input = &tegra_pll_m,     .value = 2},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_clk_m[] = {
+	{ .input = &tegra_clk_m, .value = 0},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_out3[] = {
+	{ .input = &tegra_pll_p_out3, .value = 0},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_clk_32k[] = {
+	{ .input = &tegra_clk_32k, .value = 0},
+	{ 0, 0},
+};
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _inputs, _flags) \
+	{						\
+		.name      = _name,			\
+		.lookup    = {				\
+			.dev_id    = _dev,		\
+			.con_id	   = _con,		\
+		},					\
+		.ops       = &tegra_periph_clk_ops,	\
+		.clk_num   = _clk_num,			\
+		.reg       = _reg,			\
+		.inputs    = _inputs,			\
+		.flags     = _flags,			\
+	}
+
+struct clk tegra_periph_clks[] = {
+	PERIPH_CLK("rtc",       "rtc-tegra",  NULL,   4,  0,     mux_clk_32k,                    PERIPH_NO_RESET),
+	PERIPH_CLK("timer",     "timer",      NULL,   5,  0,     mux_clk_m,                      0),
+	PERIPH_CLK("i2s1",      "i2s.0",      NULL,   11, 0x100, mux_plla_audio_pllp_clkm,       MUX | DIV_U71),
+	PERIPH_CLK("i2s2",      "i2s.1",      NULL,   18, 0x104, mux_plla_audio_pllp_clkm,       MUX | DIV_U71),
+	/* FIXME: spdif has 2 clocks but 1 enable */
+	PERIPH_CLK("spdif_out", "spdif_out",  NULL,   10, 0x108, mux_plla_audio_pllp_clkm,       MUX | DIV_U71),
+	PERIPH_CLK("spdif_in",  "spdif_in",   NULL,   10, 0x10c, mux_pllp_pllc_pllm,             MUX | DIV_U71),
+	PERIPH_CLK("pwm",       "pwm",        NULL,   17, 0x110, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71),
+	PERIPH_CLK("spi",       "spi",        NULL,   43, 0x114, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("xio",       "xio",        NULL,   45, 0x120, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("twc",       "twc",        NULL,   16, 0x12c, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("sbc1",      "spi_tegra.0",NULL,   41, 0x134, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("sbc2",      "spi_tegra.1",NULL,   44, 0x118, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("sbc3",      "spi_tegra.2",NULL,   46, 0x11c, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("sbc4",      "spi_tegra.3",NULL,   68, 0x1b4, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("ide",       "ide",        NULL,   25, 0x144, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("ndflash",   "tegra_nand", NULL,   13, 0x160, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	/* FIXME: vfir shares an enable with uartb */
+	PERIPH_CLK("vfir",      "vfir",       NULL,   7,  0x168, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("sdmmc1",    "sdhci-tegra.0",    NULL,   14, 0x150, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("sdmmc2",    "sdhci-tegra.1",    NULL,   9,  0x154, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("sdmmc3",    "sdhci-tegra.2",    NULL,   69, 0x1bc, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("sdmmc4",    "sdhci-tegra.3",    NULL,   15, 0x160, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("vde",       "vde",        NULL,   61, 0x1c8, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("csite",     "csite",      NULL,   73, 0x1d4, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	/* FIXME: what is la? */
+	PERIPH_CLK("la",        "la",         NULL,   76, 0x1f8, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("owr",       "owr",        NULL,   71, 0x1cc, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("nor",       "nor",        NULL,   42, 0x1d0, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("mipi",      "mipi",       NULL,   50, 0x174, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("i2c1",      "tegra-i2c.0",      NULL,   12, 0x124, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("i2c2",      "tegra-i2c.1",      NULL,   54, 0x198, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("i2c3",      "tegra-i2c.2",      NULL,   67, 0x1b8, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("dvc",       "tegra-i2c.3",      NULL,   47, 0x128, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("i2c1_i2c",  "tegra-i2c.0",      "i2c",  0, 0, mux_pllp_out3,        0),
+	PERIPH_CLK("i2c2_i2c",  "tegra-i2c.1",      "i2c",  0, 0, mux_pllp_out3,        0),
+	PERIPH_CLK("i2c3_i2c",  "tegra-i2c.2",      "i2c",  0, 0, mux_pllp_out3,        0),
+	PERIPH_CLK("dvc_i2c",   "tegra-i2c.3",      "i2c",  0, 0, mux_pllp_out3,        0),
+	PERIPH_CLK("uarta",     "uart.0",     NULL,   6,  0x178, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("uartb",     "uart.1",     NULL,   7,  0x17c, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("uartc",     "uart.2",     NULL,   55, 0x1a0, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("uartd",     "uart.3",     NULL,   65, 0x1c0, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("uarte",     "uart.4",     NULL,   66, 0x1c4, mux_pllp_pllc_pllm_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("3d",        "3d",         NULL,   24, 0x158, mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
+	PERIPH_CLK("2d",        "2d",         NULL,   21, 0x15c, mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
+	/* FIXME: vi and vi_sensor share an enable */
+	PERIPH_CLK("vi",        "vi",         NULL,   20, 0x148, mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
+	PERIPH_CLK("vi_sensor", "vi_sensor",  NULL,   20, 0x1a8, mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
+	PERIPH_CLK("epp",       "epp",        NULL,   19, 0x16c, mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
+	PERIPH_CLK("mpe",       "mpe",        NULL,   60, 0x170, mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
+	PERIPH_CLK("host1x",    "host1x",     NULL,   28, 0x180, mux_pllm_pllc_pllp_plla,        MUX | DIV_U71),
+	/* FIXME: cve and tvo share an enable  */
+	PERIPH_CLK("cve",       "cve",        NULL,   49, 0x140, mux_pllp_plld_pllc_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("tvo",       "tvo",        NULL,   49, 0x188, mux_pllp_plld_pllc_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("hdmi",      "hdmi",       NULL,   51, 0x18c, mux_pllp_plld_pllc_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("tvdac",     "tvdac",      NULL,   53, 0x194, mux_pllp_plld_pllc_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("disp1",     "tegrafb.0",  NULL,   27, 0x138, mux_pllp_plld_pllc_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("disp2",     "tegrafb.1",  NULL,   26, 0x13c, mux_pllp_plld_pllc_clkm,        MUX | DIV_U71),
+	PERIPH_CLK("usbd",      "fsl-tegra-udc",      NULL,   22, 0,     mux_clk_m,                    0),
+	PERIPH_CLK("usb2",      "usb.1",      NULL,   58, 0,     mux_clk_m,                              0),
+	PERIPH_CLK("usb3",      "usb.2",      NULL,   59, 0,     mux_clk_m,                              0),
+	PERIPH_CLK("emc",       "emc",        NULL,   57, 0x19c, mux_pllm_pllc_pllp_clkm,        MUX | DIV_U71 | PERIPH_EMC_ENB),
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con) \
+	{						\
+		.name      = _name,			\
+		.lookup    = {				\
+			.dev_id    = _dev,		\
+			.con_id	   = _con,		\
+		},					\
+	}
+
+/* Some clocks may be used by different drivers depending on the board
+ * configuration.  List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+struct clk_duplicate tegra_clk_duplicates[] = {
+	CLK_DUPLICATE("uarta", "tegra_uart.0", NULL),
+	CLK_DUPLICATE("uartb", "tegra_uart.1", NULL),
+	CLK_DUPLICATE("uartc", "tegra_uart.2", NULL),
+	CLK_DUPLICATE("uartd", "tegra_uart.3", NULL),
+	CLK_DUPLICATE("uarte", "tegra_uart.4", NULL),
+};
+
+#define CLK(dev, con, ck)     \
+	{       \
+		.dev_id = dev,  \
+		.con_id = con,  \
+		.clk = ck,  \
+	}
+
+struct clk_lookup tegra_clk_lookups[] = {
+	/* external root sources */
+	CLK(NULL, "32k_clk", &tegra_clk_32k),
+	CLK(NULL, "pll_s", &tegra_pll_s),
+	CLK(NULL, "clk_m", &tegra_clk_m),
+	CLK(NULL, "pll_m", &tegra_pll_m),
+	CLK(NULL, "pll_m_out1", &tegra_pll_m_out1),
+	CLK(NULL, "pll_c", &tegra_pll_c),
+	CLK(NULL, "pll_c_out1", &tegra_pll_c_out1),
+	CLK(NULL, "pll_p", &tegra_pll_p),
+	CLK(NULL, "pll_p_out1", &tegra_pll_p_out1),
+	CLK(NULL, "pll_p_out2", &tegra_pll_p_out2),
+	CLK(NULL, "pll_p_out3", &tegra_pll_p_out3),
+	CLK(NULL, "pll_p_out4", &tegra_pll_p_out4),
+	CLK(NULL, "pll_a",      &tegra_pll_a),
+	CLK(NULL, "pll_a_out0", &tegra_pll_a_out0),
+	CLK(NULL, "pll_d",      &tegra_pll_d),
+	CLK(NULL, "pll_d_out0", &tegra_pll_d_out0),
+	CLK(NULL, "pll_u",      &tegra_pll_u),
+	CLK(NULL, "pll_x",      &tegra_pll_x),
+	CLK(NULL, "cpu",	&tegra_clk_cpu),
+	CLK(NULL, "sys",	&tegra_clk_sys),
+	CLK(NULL, "hclk",	&tegra_clk_hclk),
+	CLK(NULL, "pclk",	&tegra_clk_pclk),
+	CLK(NULL, "clk_d",	&tegra_clk_d),
+};
+
+void tegra2_init_clocks(void)
+{
+	int i;
+	struct clk_lookup *cl;
+	struct clk *c;
+	struct clk_duplicate *cd;
+
+	for (i = 0; i < ARRAY_SIZE(tegra_clk_lookups); i++) {
+		cl = &tegra_clk_lookups[i];
+		clk_init(cl->clk);
+		clkdev_add(cl);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(tegra_periph_clks); i++) {
+		c = &tegra_periph_clks[i];
+		cl = &c->lookup;
+		cl->clk = c;
+
+		clk_init(cl->clk);
+		clkdev_add(cl);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+		cd = &tegra_clk_duplicates[i];
+		c = get_tegra_clock_by_name(cd->name);
+		if (c) {
+			cl = &cd->lookup;
+			cl->clk = c;
+			clkdev_add(cl);
+		} else {
+			pr_err("%s: Unknown duplicate clock %s\n", __func__,
+				cd->name);
+		}
+	}
+}
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 8f10d24..2f8adca 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Sat May 1 10:36:42 2010
+# Last update: Fri Jun 4 07:10:47 2010
 #
 # machine_is_xxx	CONFIG_xxxx		MACH_TYPE_xxx		number
 #
@@ -1319,7 +1319,7 @@ mistral			MACH_MISTRAL		MISTRAL			1315
 msm			MACH_MSM		MSM			1316
 ct5910			MACH_CT5910		CT5910			1317
 ct5912			MACH_CT5912		CT5912			1318
-hynet_ine		MACH_HYNET_INE		HYNET_INE		1319
+argonst_foundation	MACH_HYNET_INE		HYNET_INE		1319
 hynet_app		MACH_HYNET_APP		HYNET_APP		1320
 msm7200			MACH_MSM7200		MSM7200			1321
 msm7600			MACH_MSM7600		MSM7600			1322
@@ -1777,7 +1777,7 @@ wdg002			MACH_WDG002		WDG002			1785
 sg560adsl		MACH_SG560ADSL		SG560ADSL		1786
 nextio_n2800_ica	MACH_NEXTIO_N2800_ICA	NEXTIO_N2800_ICA	1787
 dove_db			MACH_DOVE_DB		DOVE_DB			1788
-marvell_newdb		MACH_MARVELL_NEWDB	MARVELL_NEWDB		1789
+dove_avng		MACH_MARVELL_NEWDB	MARVELL_NEWDB		1789
 vandihud		MACH_VANDIHUD		VANDIHUD		1790
 magx_e8			MACH_MAGX_E8		MAGX_E8			1791
 magx_z6			MACH_MAGX_Z6		MAGX_Z6			1792
@@ -2308,7 +2308,7 @@ ecac2378		MACH_ECAC2378		ECAC2378		2319
 tazkiosk		MACH_TAZKIOSK		TAZKIOSK		2320
 whiterabbit_mch		MACH_WHITERABBIT_MCH	WHITERABBIT_MCH		2321
 sbox9263		MACH_SBOX9263		SBOX9263		2322
-oreo			MACH_OREO		OREO			2323
+oreo_camera		MACH_OREO		OREO			2323
 smdk6442		MACH_SMDK6442		SMDK6442		2324
 openrd_base		MACH_OPENRD_BASE	OPENRD_BASE		2325
 incredible		MACH_INCREDIBLE		INCREDIBLE		2326
@@ -2374,7 +2374,7 @@ sch_m490		MACH_SCH_M490		SCH_M490		2386
 rbl01			MACH_RBL01		RBL01			2387
 omnifi			MACH_OMNIFI		OMNIFI			2388
 otavalo			MACH_OTAVALO		OTAVALO			2389
-sienna			MACH_SIENNA		SIENNA			2390
+siena			MACH_SIENNA		SIENNA			2390
 htc_excalibur_s620	MACH_HTC_EXCALIBUR_S620	HTC_EXCALIBUR_S620	2391
 htc_opal		MACH_HTC_OPAL		HTC_OPAL		2392
 touchbook		MACH_TOUCHBOOK		TOUCHBOOK		2393
@@ -2498,7 +2498,7 @@ hiram			MACH_HIRAM		HIRAM			2510
 phy3250			MACH_PHY3250		PHY3250			2511
 ea3250			MACH_EA3250		EA3250			2512
 fdi3250			MACH_FDI3250		FDI3250			2513
-whitestone		MACH_WHITESTONE		WHITESTONE		2514
+htcwhitestone		MACH_WHITESTONE		WHITESTONE		2514
 at91sam9263nit		MACH_AT91SAM9263NIT	AT91SAM9263NIT		2515
 ccmx51			MACH_CCMX51		CCMX51			2516
 ccmx51js		MACH_CCMX51JS		CCMX51JS		2517
@@ -2582,7 +2582,7 @@ omap3_bulldog		MACH_OMAP3_BULLDOG	OMAP3_BULLDOG		2594
 pca101			MACH_PCA101		PCA101			2595
 buzzc			MACH_BUZZC		BUZZC			2596
 sasie2			MACH_SASIE2		SASIE2			2597
-davinci_cio		MACH_DAVINCI_CIO	DAVINCI_CIO		2598
+davinci_dm6467_cio	MACH_DAVINCI_CIO	DAVINCI_CIO		2598
 smartmeter_dl		MACH_SMARTMETER_DL	SMARTMETER_DL		2599
 wzl6410			MACH_WZL6410		WZL6410			2600
 wzl6410m		MACH_WZL6410M		WZL6410M		2601
@@ -2750,7 +2750,7 @@ h6053			MACH_H6053		H6053			2762
 smint01			MACH_SMINT01		SMINT01			2763
 prtlvt2			MACH_PRTLVT2		PRTLVT2			2764
 ap420			MACH_AP420		AP420			2765
-htcshift		MACH_HTCSHIFT		HTCSHIFT		2766
+htcclio			MACH_HTCSHIFT		HTCSHIFT		2766
 davinci_dm365_fc	MACH_DAVINCI_DM365_FC	DAVINCI_DM365_FC	2767
 msm8x55_surf		MACH_MSM8X55_SURF	MSM8X55_SURF		2768
 msm8x55_ffa		MACH_MSM8X55_FFA	MSM8X55_FFA		2769
@@ -2761,7 +2761,7 @@ oreo_controller		MACH_OREO_CONTROLLER	OREO_CONTROLLER		2773
 kopin_models		MACH_KOPIN_MODELS	KOPIN_MODELS		2774
 ttc_vision2		MACH_TTC_VISION2	TTC_VISION2		2775
 cns3420vb		MACH_CNS3420VB		CNS3420VB		2776
-lpc2			MACH_LPC2		LPC2			2777
+lpc_evo			MACH_LPC2		LPC2			2777
 olympus			MACH_OLYMPUS		OLYMPUS			2778
 vortex			MACH_VORTEX		VORTEX			2779
 s5pc200			MACH_S5PC200		S5PC200			2780
@@ -2788,7 +2788,7 @@ ti8168evm		MACH_TI8168EVM		TI8168EVM		2800
 neocoreomap		MACH_NEOCOREOMAP	NEOCOREOMAP		2801
 withings_wbp		MACH_WITHINGS_WBP	WITHINGS_WBP		2802
 dbps			MACH_DBPS		DBPS			2803
-sbc9261			MACH_SBC9261		SBC9261			2804
+at91sam9261		MACH_SBC9261		SBC9261			2804
 pcbfp0001		MACH_PCBFP0001		PCBFP0001		2805
 speedy			MACH_SPEEDY		SPEEDY			2806
 chrysaor		MACH_CHRYSAOR		CHRYSAOR		2807
@@ -2804,3 +2804,81 @@ teton_bga		MACH_TETON_BGA		TETON_BGA		2816
 snapper9g45		MACH_SNAPPER9G45	SNAPPER9G45		2817
 tam3517			MACH_TAM3517		TAM3517			2818
 pdc100			MACH_PDC100		PDC100			2819
+eukrea_cpuimx25sd	MACH_EUKREA_CPUIMX25	EUKREA_CPUIMX25		2820
+eukrea_cpuimx35sd	MACH_EUKREA_CPUIMX35	EUKREA_CPUIMX35		2821
+eukrea_cpuimx51sd	MACH_EUKREA_CPUIMX51SD	EUKREA_CPUIMX51SD	2822
+eukrea_cpuimx51		MACH_EUKREA_CPUIMX51	EUKREA_CPUIMX51		2823
+p565			MACH_P565		P565			2824
+acer_a4			MACH_ACER_A4		ACER_A4			2825
+davinci_dm368_bip	MACH_DAVINCI_DM368_BIP	DAVINCI_DM368_BIP	2826
+eshare			MACH_ESHARE		ESHARE			2827
+hw_omapl138_europa	MACH_HW_OMAPL138_EUROPA	HW_OMAPL138_EUROPA	2828
+wlbargn			MACH_WLBARGN		WLBARGN			2829
+bm170			MACH_BM170		BM170			2830
+netspace_mini_v2	MACH_NETSPACE_MINI_V2	NETSPACE_MINI_V2	2831
+netspace_plug_v2	MACH_NETSPACE_PLUG_V2	NETSPACE_PLUG_V2	2832
+siemens_l1		MACH_SIEMENS_L1		SIEMENS_L1		2833
+elv_lcu1		MACH_ELV_LCU1		ELV_LCU1		2834
+mcu1			MACH_MCU1		MCU1			2835
+omap3_tao3530		MACH_OMAP3_TAO3530	OMAP3_TAO3530		2836
+omap3_pcutouch		MACH_OMAP3_PCUTOUCH	OMAP3_PCUTOUCH		2837
+smdkc210		MACH_SMDKC210		SMDKC210		2838
+omap3_braillo		MACH_OMAP3_BRAILLO	OMAP3_BRAILLO		2839
+spyplug			MACH_SPYPLUG		SPYPLUG			2840
+ginger			MACH_GINGER		GINGER			2841
+tny_t3530		MACH_TNY_T3530		TNY_T3530		2842
+pca102			MACH_PCA102		PCA102			2843
+spade			MACH_SPADE		SPADE			2844
+mxc25_topaz		MACH_MXC25_TOPAZ	MXC25_TOPAZ		2845
+t5325			MACH_T5325		T5325			2846
+gw2361			MACH_GW2361		GW2361			2847
+elog			MACH_ELOG		ELOG			2848
+income			MACH_INCOME		INCOME			2849
+bcm589x			MACH_BCM589X		BCM589X			2850
+etna			MACH_ETNA		ETNA			2851
+hawks			MACH_HAWKS		HAWKS			2852
+meson			MACH_MESON		MESON			2853
+xsbase255		MACH_XSBASE255		XSBASE255		2854
+pvm2030			MACH_PVM2030		PVM2030			2855
+mioa502			MACH_MIOA502		MIOA502			2856
+vvbox_sdorig2		MACH_VVBOX_SDORIG2	VVBOX_SDORIG2		2857
+vvbox_sdlite2		MACH_VVBOX_SDLITE2	VVBOX_SDLITE2		2858
+vvbox_sdpro4		MACH_VVBOX_SDPRO4	VVBOX_SDPRO4		2859
+htc_spv_m700		MACH_HTC_SPV_M700	HTC_SPV_M700		2860
+mx257sx			MACH_MX257SX		MX257SX			2861
+goni			MACH_GONI		GONI			2862
+msm8x55_svlte_ffa	MACH_MSM8X55_SVLTE_FFA	MSM8X55_SVLTE_FFA	2863
+msm8x55_svlte_surf	MACH_MSM8X55_SVLTE_SURF	MSM8X55_SVLTE_SURF	2864
+quickstep		MACH_QUICKSTEP		QUICKSTEP		2865
+dmw96			MACH_DMW96		DMW96			2866
+hammerhead		MACH_HAMMERHEAD		HAMMERHEAD		2867
+trident			MACH_TRIDENT		TRIDENT			2868
+lightning		MACH_LIGHTNING		LIGHTNING		2869
+iconnect		MACH_ICONNECT		ICONNECT		2870
+autobot			MACH_AUTOBOT		AUTOBOT			2871
+coconut			MACH_COCONUT		COCONUT			2872
+durian			MACH_DURIAN		DURIAN			2873
+cayenne			MACH_CAYENNE		CAYENNE			2874
+fuji			MACH_FUJI		FUJI			2875
+synology_6282		MACH_SYNOLOGY_6282	SYNOLOGY_6282		2876
+em1sy			MACH_EM1SY		EM1SY			2877
+m502			MACH_M502		M502			2878
+matrix518		MACH_MATRIX518		MATRIX518		2879
+tiny_gurnard		MACH_TINY_GURNARD	TINY_GURNARD		2880
+spear1310		MACH_SPEAR1310		SPEAR1310		2881
+bv07			MACH_BV07		BV07			2882
+mxt_td61		MACH_MXT_TD61		MXT_TD61		2883
+openrd_ultimate		MACH_OPENRD_ULTIMATE	OPENRD_ULTIMATE		2884
+devixp			MACH_DEVIXP		DEVIXP			2885
+miccpt			MACH_MICCPT		MICCPT			2886
+mic256			MACH_MIC256		MIC256			2887
+as1167			MACH_AS1167		AS1167			2888
+omap3_ibiza		MACH_OMAP3_IBIZA	OMAP3_IBIZA		2889
+u5500			MACH_U5500		U5500			2890
+davinci_picto		MACH_DAVINCI_PICTO	DAVINCI_PICTO		2891
+mecha			MACH_MECHA		MECHA			2892
+bubba3			MACH_BUBBA3		BUBBA3			2893
+pupitre			MACH_PUPITRE		PUPITRE			2894
+tegra_harmony		MACH_TEGRA_HARMONY	TEGRA_HARMONY		2895
+tegra_vogue		MACH_TEGRA_VOGUE	TEGRA_VOGUE		2896
+tegra_e1165		MACH_TEGRA_E1165	TEGRA_E1165		2897
-- 
1.5.6.5



From olof at lixom.net  Fri Jun  4 03:10:38 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri,  4 Jun 2010 02:10:38 -0500
Subject: [PATCH 06/10] [ARM] tegra: add GPIO support
In-Reply-To: <1275635441-17378-6-git-send-email-olof@lixom.net>
References: <3478yvr76gerav> <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
	<1275635441-17378-3-git-send-email-olof@lixom.net>
	<1275635441-17378-4-git-send-email-olof@lixom.net>
	<1275635441-17378-5-git-send-email-olof@lixom.net>
	<1275635441-17378-6-git-send-email-olof@lixom.net>
Message-ID: <1275635441-17378-7-git-send-email-olof@lixom.net>

From: Erik Gilling <konkers at android.com>

v2: fixes from Mike Rapoport:
	- move gpio-names.h to arch/arm/mach-tegra
    fixes from Russell King
	- include linux/io.h and linux/gpio.h instead of asm/io.h
	  and asm/gpio.h
    additional changes:
    	- add macros to convert between irq and gpio numbers for platform data
	- change for_each_bit to for_each_set_bit in gpio.c

Olof:
	- Bring in 'mask irq sense type' bugfix

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Erik Gilling <konkers at android.com>
Signed-off-by: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-tegra/Kconfig             |    1 +
 arch/arm/mach-tegra/Makefile            |    1 +
 arch/arm/mach-tegra/gpio-names.h        |  247 ++++++++++++++++++++++
 arch/arm/mach-tegra/gpio.c              |  348 +++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/include/mach/gpio.h |   53 +++++
 5 files changed, 650 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/gpio-names.h
 create mode 100644 arch/arm/mach-tegra/gpio.c
 create mode 100644 arch/arm/mach-tegra/include/mach/gpio.h

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 64ab14f..1ec54d6 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -9,6 +9,7 @@ config ARCH_TEGRA_2x_SOC
 	bool "Tegra 2 family"
 	select CPU_V7
 	select ARM_GIC
+	select ARCH_REQUIRE_GPIOLIB
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 01f47fd..122f7dc 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -3,6 +3,7 @@ obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
+obj-y                                   += gpio.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/gpio-names.h b/arch/arm/mach-tegra/gpio-names.h
new file mode 100644
index 0000000..f28220a
--- /dev/null
+++ b/arch/arm/mach-tegra/gpio-names.h
@@ -0,0 +1,247 @@
+/*
+ * arch/arm/mach-tegra/include/mach/gpio-names.h
+ *
+ * Copyright (c) 2010 Google, Inc
+ *
+ * Author:
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_TEGRA_GPIO_NAMES_H
+#define __MACH_TEGRA_GPIO_NAMES_H
+
+#define TEGRA_GPIO_PA0		0
+#define TEGRA_GPIO_PA1		1
+#define TEGRA_GPIO_PA2		2
+#define TEGRA_GPIO_PA3		3
+#define TEGRA_GPIO_PA4		4
+#define TEGRA_GPIO_PA5		5
+#define TEGRA_GPIO_PA6		6
+#define TEGRA_GPIO_PA7		7
+#define TEGRA_GPIO_PB0		8
+#define TEGRA_GPIO_PB1		9
+#define TEGRA_GPIO_PB2		10
+#define TEGRA_GPIO_PB3		11
+#define TEGRA_GPIO_PB4		12
+#define TEGRA_GPIO_PB5		13
+#define TEGRA_GPIO_PB6		14
+#define TEGRA_GPIO_PB7		15
+#define TEGRA_GPIO_PC0		16
+#define TEGRA_GPIO_PC1		17
+#define TEGRA_GPIO_PC2		18
+#define TEGRA_GPIO_PC3		19
+#define TEGRA_GPIO_PC4		20
+#define TEGRA_GPIO_PC5		21
+#define TEGRA_GPIO_PC6		22
+#define TEGRA_GPIO_PC7		23
+#define TEGRA_GPIO_PD0		24
+#define TEGRA_GPIO_PD1		25
+#define TEGRA_GPIO_PD2		26
+#define TEGRA_GPIO_PD3		27
+#define TEGRA_GPIO_PD4		28
+#define TEGRA_GPIO_PD5		29
+#define TEGRA_GPIO_PD6		30
+#define TEGRA_GPIO_PD7		31
+#define TEGRA_GPIO_PE0		32
+#define TEGRA_GPIO_PE1		33
+#define TEGRA_GPIO_PE2		34
+#define TEGRA_GPIO_PE3		35
+#define TEGRA_GPIO_PE4		36
+#define TEGRA_GPIO_PE5		37
+#define TEGRA_GPIO_PE6		38
+#define TEGRA_GPIO_PE7		39
+#define TEGRA_GPIO_PF0		40
+#define TEGRA_GPIO_PF1		41
+#define TEGRA_GPIO_PF2		42
+#define TEGRA_GPIO_PF3		43
+#define TEGRA_GPIO_PF4		44
+#define TEGRA_GPIO_PF5		45
+#define TEGRA_GPIO_PF6		46
+#define TEGRA_GPIO_PF7		47
+#define TEGRA_GPIO_PG0		48
+#define TEGRA_GPIO_PG1		49
+#define TEGRA_GPIO_PG2		50
+#define TEGRA_GPIO_PG3		51
+#define TEGRA_GPIO_PG4		52
+#define TEGRA_GPIO_PG5		53
+#define TEGRA_GPIO_PG6		54
+#define TEGRA_GPIO_PG7		55
+#define TEGRA_GPIO_PH0		56
+#define TEGRA_GPIO_PH1		57
+#define TEGRA_GPIO_PH2		58
+#define TEGRA_GPIO_PH3		59
+#define TEGRA_GPIO_PH4		60
+#define TEGRA_GPIO_PH5		61
+#define TEGRA_GPIO_PH6		62
+#define TEGRA_GPIO_PH7		63
+#define TEGRA_GPIO_PI0		64
+#define TEGRA_GPIO_PI1		65
+#define TEGRA_GPIO_PI2		66
+#define TEGRA_GPIO_PI3		67
+#define TEGRA_GPIO_PI4		68
+#define TEGRA_GPIO_PI5		69
+#define TEGRA_GPIO_PI6		70
+#define TEGRA_GPIO_PI7		71
+#define TEGRA_GPIO_PJ0		72
+#define TEGRA_GPIO_PJ1		73
+#define TEGRA_GPIO_PJ2		74
+#define TEGRA_GPIO_PJ3		75
+#define TEGRA_GPIO_PJ4		76
+#define TEGRA_GPIO_PJ5		77
+#define TEGRA_GPIO_PJ6		78
+#define TEGRA_GPIO_PJ7		79
+#define TEGRA_GPIO_PK0		80
+#define TEGRA_GPIO_PK1		81
+#define TEGRA_GPIO_PK2		82
+#define TEGRA_GPIO_PK3		83
+#define TEGRA_GPIO_PK4		84
+#define TEGRA_GPIO_PK5		85
+#define TEGRA_GPIO_PK6		86
+#define TEGRA_GPIO_PK7		87
+#define TEGRA_GPIO_PL0		88
+#define TEGRA_GPIO_PL1		89
+#define TEGRA_GPIO_PL2		90
+#define TEGRA_GPIO_PL3		91
+#define TEGRA_GPIO_PL4		92
+#define TEGRA_GPIO_PL5		93
+#define TEGRA_GPIO_PL6		94
+#define TEGRA_GPIO_PL7		95
+#define TEGRA_GPIO_PM0		96
+#define TEGRA_GPIO_PM1		97
+#define TEGRA_GPIO_PM2		98
+#define TEGRA_GPIO_PM3		99
+#define TEGRA_GPIO_PM4		100
+#define TEGRA_GPIO_PM5		101
+#define TEGRA_GPIO_PM6		102
+#define TEGRA_GPIO_PM7		103
+#define TEGRA_GPIO_PN0		104
+#define TEGRA_GPIO_PN1		105
+#define TEGRA_GPIO_PN2		106
+#define TEGRA_GPIO_PN3		107
+#define TEGRA_GPIO_PN4		108
+#define TEGRA_GPIO_PN5		109
+#define TEGRA_GPIO_PN6		110
+#define TEGRA_GPIO_PN7		111
+#define TEGRA_GPIO_PO0		112
+#define TEGRA_GPIO_PO1		113
+#define TEGRA_GPIO_PO2		114
+#define TEGRA_GPIO_PO3		115
+#define TEGRA_GPIO_PO4		116
+#define TEGRA_GPIO_PO5		117
+#define TEGRA_GPIO_PO6		118
+#define TEGRA_GPIO_PO7		119
+#define TEGRA_GPIO_PP0		120
+#define TEGRA_GPIO_PP1		121
+#define TEGRA_GPIO_PP2		122
+#define TEGRA_GPIO_PP3		123
+#define TEGRA_GPIO_PP4		124
+#define TEGRA_GPIO_PP5		125
+#define TEGRA_GPIO_PP6		126
+#define TEGRA_GPIO_PP7		127
+#define TEGRA_GPIO_PQ0		128
+#define TEGRA_GPIO_PQ1		129
+#define TEGRA_GPIO_PQ2		130
+#define TEGRA_GPIO_PQ3		131
+#define TEGRA_GPIO_PQ4		132
+#define TEGRA_GPIO_PQ5		133
+#define TEGRA_GPIO_PQ6		134
+#define TEGRA_GPIO_PQ7		135
+#define TEGRA_GPIO_PR0		136
+#define TEGRA_GPIO_PR1		137
+#define TEGRA_GPIO_PR2		138
+#define TEGRA_GPIO_PR3		139
+#define TEGRA_GPIO_PR4		140
+#define TEGRA_GPIO_PR5		141
+#define TEGRA_GPIO_PR6		142
+#define TEGRA_GPIO_PR7		143
+#define TEGRA_GPIO_PS0		144
+#define TEGRA_GPIO_PS1		145
+#define TEGRA_GPIO_PS2		146
+#define TEGRA_GPIO_PS3		147
+#define TEGRA_GPIO_PS4		148
+#define TEGRA_GPIO_PS5		149
+#define TEGRA_GPIO_PS6		150
+#define TEGRA_GPIO_PS7		151
+#define TEGRA_GPIO_PT0		152
+#define TEGRA_GPIO_PT1		153
+#define TEGRA_GPIO_PT2		154
+#define TEGRA_GPIO_PT3		155
+#define TEGRA_GPIO_PT4		156
+#define TEGRA_GPIO_PT5		157
+#define TEGRA_GPIO_PT6		158
+#define TEGRA_GPIO_PT7		159
+#define TEGRA_GPIO_PU0		160
+#define TEGRA_GPIO_PU1		161
+#define TEGRA_GPIO_PU2		162
+#define TEGRA_GPIO_PU3		163
+#define TEGRA_GPIO_PU4		164
+#define TEGRA_GPIO_PU5		165
+#define TEGRA_GPIO_PU6		166
+#define TEGRA_GPIO_PU7		167
+#define TEGRA_GPIO_PV0		168
+#define TEGRA_GPIO_PV1		169
+#define TEGRA_GPIO_PV2		170
+#define TEGRA_GPIO_PV3		171
+#define TEGRA_GPIO_PV4		172
+#define TEGRA_GPIO_PV5		173
+#define TEGRA_GPIO_PV6		174
+#define TEGRA_GPIO_PV7		175
+#define TEGRA_GPIO_PW0		176
+#define TEGRA_GPIO_PW1		177
+#define TEGRA_GPIO_PW2		178
+#define TEGRA_GPIO_PW3		179
+#define TEGRA_GPIO_PW4		180
+#define TEGRA_GPIO_PW5		181
+#define TEGRA_GPIO_PW6		182
+#define TEGRA_GPIO_PW7		183
+#define TEGRA_GPIO_PX0		184
+#define TEGRA_GPIO_PX1		185
+#define TEGRA_GPIO_PX2		186
+#define TEGRA_GPIO_PX3		187
+#define TEGRA_GPIO_PX4		188
+#define TEGRA_GPIO_PX5		189
+#define TEGRA_GPIO_PX6		190
+#define TEGRA_GPIO_PX7		191
+#define TEGRA_GPIO_PY0		192
+#define TEGRA_GPIO_PY1		193
+#define TEGRA_GPIO_PY2		194
+#define TEGRA_GPIO_PY3		195
+#define TEGRA_GPIO_PY4		196
+#define TEGRA_GPIO_PY5		197
+#define TEGRA_GPIO_PY6		198
+#define TEGRA_GPIO_PY7		199
+#define TEGRA_GPIO_PZ0		200
+#define TEGRA_GPIO_PZ1		201
+#define TEGRA_GPIO_PZ2		202
+#define TEGRA_GPIO_PZ3		203
+#define TEGRA_GPIO_PZ4		204
+#define TEGRA_GPIO_PZ5		205
+#define TEGRA_GPIO_PZ6		206
+#define TEGRA_GPIO_PZ7		207
+#define TEGRA_GPIO_PAA0		208
+#define TEGRA_GPIO_PAA1		209
+#define TEGRA_GPIO_PAA2		210
+#define TEGRA_GPIO_PAA3		211
+#define TEGRA_GPIO_PAA4		212
+#define TEGRA_GPIO_PAA5		213
+#define TEGRA_GPIO_PAA6		214
+#define TEGRA_GPIO_PAA7		215
+#define TEGRA_GPIO_PBB0		216
+#define TEGRA_GPIO_PBB1		217
+#define TEGRA_GPIO_PBB2		218
+#define TEGRA_GPIO_PBB3		219
+#define TEGRA_GPIO_PBB4		220
+#define TEGRA_GPIO_PBB5		221
+#define TEGRA_GPIO_PBB6		222
+#define TEGRA_GPIO_PBB7		223
+
+#endif
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
new file mode 100644
index 0000000..fe78fba
--- /dev/null
+++ b/arch/arm/mach-tegra/gpio.c
@@ -0,0 +1,348 @@
+/*
+ * arch/arm/mach-tegra/gpio.c
+ *
+ * Copyright (c) 2010 Google, Inc
+ *
+ * Author:
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/iomap.h>
+
+#define GPIO_BANK(x)		((x) >> 5)
+#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
+#define GPIO_BIT(x)		((x) & 0x7)
+
+#define GPIO_REG(x)		(IO_TO_VIRT(TEGRA_GPIO_BASE) +	\
+				 GPIO_BANK(x) * 0x80 +		\
+				 GPIO_PORT(x) * 4)
+
+#define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
+#define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
+#define GPIO_OUT(x)		(GPIO_REG(x) + 0X20)
+#define GPIO_IN(x)		(GPIO_REG(x) + 0x30)
+#define GPIO_INT_STA(x)		(GPIO_REG(x) + 0x40)
+#define GPIO_INT_ENB(x)		(GPIO_REG(x) + 0x50)
+#define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
+#define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)
+
+#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + 0x800)
+#define GPIO_MSK_OE(x)		(GPIO_REG(x) + 0x810)
+#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + 0X820)
+#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + 0x840)
+#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + 0x850)
+#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + 0x860)
+
+#define GPIO_INT_LVL_MASK		0x010101
+#define GPIO_INT_LVL_EDGE_RISING	0x000101
+#define GPIO_INT_LVL_EDGE_FALLING	0x000100
+#define GPIO_INT_LVL_EDGE_BOTH		0x010100
+#define GPIO_INT_LVL_LEVEL_HIGH		0x000001
+#define GPIO_INT_LVL_LEVEL_LOW		0x000000
+
+struct tegra_gpio_bank {
+	int bank;
+	int irq;
+	spinlock_t lvl_lock[4];
+};
+
+
+static struct tegra_gpio_bank tegra_gpio_banks[] = {
+	{.bank = 0, .irq = INT_GPIO1},
+	{.bank = 1, .irq = INT_GPIO2},
+	{.bank = 2, .irq = INT_GPIO3},
+	{.bank = 3, .irq = INT_GPIO4},
+	{.bank = 4, .irq = INT_GPIO5},
+	{.bank = 5, .irq = INT_GPIO6},
+	{.bank = 6, .irq = INT_GPIO7},
+};
+
+static int tegra_gpio_compose(int bank, int port, int bit)
+{
+	return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
+}
+
+static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
+{
+	u32 val;
+
+	val = 0x100 << GPIO_BIT(gpio);
+	if (value)
+		val |= 1 << GPIO_BIT(gpio);
+	__raw_writel(val, reg);
+}
+
+void tegra_gpio_enable(int gpio)
+{
+	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
+}
+
+void tegra_gpio_disable(int gpio)
+{
+	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
+}
+
+static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
+}
+
+static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+	return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
+}
+
+static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
+	return 0;
+}
+
+static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+					int value)
+{
+	tegra_gpio_set(chip, offset, value);
+	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
+	return 0;
+}
+
+
+
+static struct gpio_chip tegra_gpio_chip = {
+	.label			= "tegra-gpio",
+	.direction_input	= tegra_gpio_direction_input,
+	.get			= tegra_gpio_get,
+	.direction_output	= tegra_gpio_direction_output,
+	.set			= tegra_gpio_set,
+	.base			= 0,
+	.ngpio			= ARCH_NR_GPIOS,
+};
+
+static void tegra_gpio_irq_ack(unsigned int irq)
+{
+	int gpio = irq - INT_GPIO_BASE;
+
+	__raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
+}
+
+static void tegra_gpio_irq_mask(unsigned int irq)
+{
+	int gpio = irq - INT_GPIO_BASE;
+
+	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
+}
+
+static void tegra_gpio_irq_unmask(unsigned int irq)
+{
+	int gpio = irq - INT_GPIO_BASE;
+
+	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
+}
+
+static int tegra_gpio_irq_set_type(unsigned int irq, unsigned int type)
+{
+	int gpio = irq - INT_GPIO_BASE;
+	struct tegra_gpio_bank *bank = get_irq_chip_data(irq);
+	int port = GPIO_PORT(gpio);
+	int lvl_type;
+	int val;
+	unsigned long flags;
+
+	switch (type & IRQ_TYPE_SENSE_MASK) {
+	case IRQ_TYPE_EDGE_RISING:
+		lvl_type = GPIO_INT_LVL_EDGE_RISING;
+		break;
+
+	case IRQ_TYPE_EDGE_FALLING:
+		lvl_type = GPIO_INT_LVL_EDGE_FALLING;
+		break;
+
+	case IRQ_TYPE_EDGE_BOTH:
+		lvl_type = GPIO_INT_LVL_EDGE_BOTH;
+		break;
+
+	case IRQ_TYPE_LEVEL_HIGH:
+		lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
+		break;
+
+	case IRQ_TYPE_LEVEL_LOW:
+		lvl_type = GPIO_INT_LVL_LEVEL_LOW;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&bank->lvl_lock[port], flags);
+
+	val = __raw_readl(GPIO_INT_LVL(gpio));
+	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
+	val |= lvl_type << GPIO_BIT(gpio);
+	__raw_writel(val, GPIO_INT_LVL(gpio));
+
+	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
+
+	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
+		__set_irq_handler_unlocked(irq, handle_level_irq);
+	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
+		__set_irq_handler_unlocked(irq, handle_edge_irq);
+
+	return 0;
+}
+
+static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct tegra_gpio_bank *bank;
+	int port;
+	int pin;
+	int unmasked = 0;
+
+	desc->chip->ack(irq);
+
+	bank = get_irq_data(irq);
+
+	for (port = 0; port < 4; port++) {
+		int gpio = tegra_gpio_compose(bank->bank, port, 0);
+		unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
+			__raw_readl(GPIO_INT_ENB(gpio));
+		u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));
+
+		for_each_set_bit(pin, &sta, 8) {
+			__raw_writel(1 << pin, GPIO_INT_CLR(gpio));
+
+			/* if gpio is edge triggered, clear condition
+			 * before executing the hander so that we don't
+			 * miss edges
+			 */
+			if (lvl & (0x100 << pin)) {
+				unmasked = 1;
+				desc->chip->unmask(irq);
+			}
+
+			generic_handle_irq(gpio_to_irq(gpio + pin));
+		}
+	}
+
+	if (!unmasked)
+		desc->chip->unmask(irq);
+
+}
+
+
+static struct irq_chip tegra_gpio_irq_chip = {
+	.name		= "GPIO",
+	.ack		= tegra_gpio_irq_ack,
+	.mask		= tegra_gpio_irq_mask,
+	.unmask		= tegra_gpio_irq_unmask,
+	.set_type	= tegra_gpio_irq_set_type,
+};
+
+
+/* This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key gpio_lock_class;
+
+static int __init tegra_gpio_init(void)
+{
+	struct tegra_gpio_bank *bank;
+	int i;
+	int j;
+
+	for (i = 0; i < 7; i++) {
+		for (j = 0; j < 4; j++) {
+			int gpio = tegra_gpio_compose(i, j, 0);
+			__raw_writel(0x00, GPIO_INT_ENB(gpio));
+		}
+	}
+
+	gpiochip_add(&tegra_gpio_chip);
+
+	for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + ARCH_NR_GPIOS); i++) {
+		bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
+
+		lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class);
+		set_irq_chip_data(i, bank);
+		set_irq_chip(i, &tegra_gpio_irq_chip);
+		set_irq_handler(i, handle_simple_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
+		bank = &tegra_gpio_banks[i];
+
+		set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler);
+		set_irq_data(bank->irq, bank);
+
+		for (j = 0; j < 4; j++)
+			spin_lock_init(&bank->lvl_lock[j]);
+	}
+
+	return 0;
+}
+
+postcore_initcall(tegra_gpio_init);
+
+#ifdef	CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static int dbg_gpio_show(struct seq_file *s, void *unused)
+{
+	int i;
+	int j;
+
+	for (i = 0; i < 7; i++) {
+		for (j = 0; j < 4; j++) {
+			int gpio = tegra_gpio_compose(i, j, 0);
+			seq_printf(s, "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
+			       i, j,
+			       __raw_readl(GPIO_CNF(gpio)),
+			       __raw_readl(GPIO_OE(gpio)),
+			       __raw_readl(GPIO_OUT(gpio)),
+			       __raw_readl(GPIO_IN(gpio)),
+			       __raw_readl(GPIO_INT_STA(gpio)),
+			       __raw_readl(GPIO_INT_ENB(gpio)),
+			       __raw_readl(GPIO_INT_LVL(gpio)));
+		}
+	}
+	return 0;
+}
+
+static int dbg_gpio_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, dbg_gpio_show, &inode->i_private);
+}
+
+static const struct file_operations debug_fops = {
+	.open		= dbg_gpio_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int __init tegra_gpio_debuginit(void)
+{
+	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
+					NULL, NULL, &debug_fops);
+	return 0;
+}
+late_initcall(tegra_gpio_debuginit);
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h
new file mode 100644
index 0000000..540e822
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/gpio.h
@@ -0,0 +1,53 @@
+/*
+ * arch/arm/mach-tegra/include/mach/gpio.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_GPIO_H
+#define __MACH_TEGRA_GPIO_H
+
+#include <mach/irqs.h>
+
+#define ARCH_NR_GPIOS		INT_GPIO_NR
+
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value		__gpio_get_value
+#define gpio_set_value		__gpio_set_value
+#define gpio_cansleep		__gpio_cansleep
+
+#define TEGRA_GPIO_TO_IRQ(gpio) (INT_GPIO_BASE + (gpio))
+#define TEGRA_IRQ_TO_GPIO(irq) ((gpio) - INT_GPIO_BASE)
+
+static inline int gpio_to_irq(unsigned int gpio)
+{
+	if (gpio < ARCH_NR_GPIOS)
+		return INT_GPIO_BASE + gpio;
+	return -EINVAL;
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+	if ((irq >= INT_GPIO_BASE) && (irq < INT_GPIO_BASE + INT_GPIO_NR))
+		return irq - INT_GPIO_BASE;
+	return -EINVAL;
+}
+
+void tegra_gpio_enable(int gpio);
+void tegra_gpio_disable(int gpio);
+
+#endif
-- 
1.5.6.5



From olof at lixom.net  Fri Jun  4 03:10:37 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri,  4 Jun 2010 02:10:37 -0500
Subject: [PATCH 05/10] [ARM] tegra: Add timer support
In-Reply-To: <1275635441-17378-5-git-send-email-olof@lixom.net>
References: <3478yvr76gerav> <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
	<1275635441-17378-3-git-send-email-olof@lixom.net>
	<1275635441-17378-4-git-send-email-olof@lixom.net>
	<1275635441-17378-5-git-send-email-olof@lixom.net>
Message-ID: <1275635441-17378-6-git-send-email-olof@lixom.net>

From: Colin Cross <ccross at android.com>

v2: fixes from Russell King:
	- include linux/io.h instead of asm/io.h
    fixes from Gary King:
	- remove extra (and incorrect) irq definitions
	- use timer 3 instead of timer 1 for compatibility with other drivers
	- fix typo that disabled oneshot mode

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-tegra/Makefile |    1 +
 arch/arm/mach-tegra/timer.c  |  183 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 184 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/timer.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index f339559..01f47fd 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -2,6 +2,7 @@ obj-y                                   += common.o
 obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
+obj-y                                   += timer.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
new file mode 100644
index 0000000..71efa7c
--- /dev/null
+++ b/arch/arm/mach-tegra/timer.c
@@ -0,0 +1,183 @@
+/*
+ * arch/arch/mach-tegra/timer.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/mach/time.h>
+#include <asm/mach/time.h>
+#include <asm/localtimer.h>
+
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+
+#include "board.h"
+#include "clock.h"
+
+#define TIMERUS_CNTR_1US 0x10
+#define TIMERUS_USEC_CFG 0x14
+#define TIMERUS_CNTR_FREEZE 0x4c
+
+#define TIMER1_BASE 0x0
+#define TIMER2_BASE 0x8
+#define TIMER3_BASE 0x50
+#define TIMER4_BASE 0x58
+
+#define TIMER_PTV 0x0
+#define TIMER_PCR 0x4
+
+struct tegra_timer;
+
+static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
+
+#define timer_writel(value, reg) \
+	__raw_writel(value, (u32)timer_reg_base + (reg))
+#define timer_readl(reg) \
+	__raw_readl((u32)timer_reg_base + (reg))
+
+static int tegra_timer_set_next_event(unsigned long cycles,
+					 struct clock_event_device *evt)
+{
+	u32 reg;
+
+	reg = 0x80000000 | ((1000000/HZ)*(cycles+1)-1);
+	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
+
+	return 0;
+}
+
+static void tegra_timer_set_mode(enum clock_event_mode mode,
+				    struct clock_event_device *evt)
+{
+	u32 reg;
+
+	timer_writel(0, TIMER3_BASE + TIMER_PTV);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		reg = 0xC0000000 | ((1000000/HZ)-1);
+		timer_writel(reg, TIMER3_BASE + TIMER_PTV);
+		break;
+	case CLOCK_EVT_MODE_ONESHOT:
+		break;
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	case CLOCK_EVT_MODE_RESUME:
+		break;
+	}
+}
+
+static cycle_t tegra_clocksource_read(struct clocksource *cs)
+{
+	return timer_readl(TIMERUS_CNTR_1US);
+}
+
+static struct clock_event_device tegra_clockevent = {
+	.name		= "timer0",
+	.rating         = 300,
+	.features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+	.mult           = 16777,
+	.shift		= 24,
+	.set_next_event	= tegra_timer_set_next_event,
+	.set_mode	= tegra_timer_set_mode,
+};
+
+static struct clocksource tegra_clocksource = {
+	.name	= "timer_us",
+	.rating	= 300,
+	.read	= tegra_clocksource_read,
+	.mask	= 0xFFFFFFFFUL,
+	.mult	= 1000,
+	.shift	= 0,
+	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
+	evt->event_handler(evt);
+	return IRQ_HANDLED;
+}
+
+static struct irqaction tegra_timer_irq = {
+	.name		= "timer0",
+	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
+	.handler	= tegra_timer_interrupt,
+	.dev_id		= &tegra_clockevent,
+	.irq            = INT_TMR3,
+};
+
+static void __init tegra_init_timer(void)
+{
+	unsigned long rate = clk_measure_input_freq();
+	int ret;
+
+#ifdef CONFIG_HAVE_ARM_TWD
+	twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
+#endif
+
+	switch (rate) {
+	case 12000000:
+		timer_writel(0x000b, TIMERUS_USEC_CFG);
+		break;
+	case 13000000:
+		timer_writel(0x000c, TIMERUS_USEC_CFG);
+		break;
+	case 19200000:
+		timer_writel(0x045f, TIMERUS_USEC_CFG);
+		break;
+	case 26000000:
+		timer_writel(0x0019, TIMERUS_USEC_CFG);
+		break;
+	default:
+		WARN(1, "Unknown clock rate");
+	}
+
+	if (clocksource_register(&tegra_clocksource)) {
+		printk(KERN_ERR "Failed to register clocksource\n");
+		BUG();
+	}
+
+	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
+	if (ret) {
+		printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
+		BUG();
+	}
+
+	tegra_clockevent.max_delta_ns =
+		clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
+	tegra_clockevent.max_delta_ns =
+		clockevent_delta2ns(0x1, &tegra_clockevent);
+	tegra_clockevent.cpumask = cpu_all_mask;
+	tegra_clockevent.irq = tegra_timer_irq.irq;
+	clockevents_register_device(&tegra_clockevent);
+
+	return;
+}
+
+struct sys_timer tegra_timer = {
+	.init = tegra_init_timer,
+};
-- 
1.5.6.5



From olof at lixom.net  Fri Jun  4 03:10:41 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri,  4 Jun 2010 02:10:41 -0500
Subject: [PATCH 09/10] [ARM] tegra: Add tegra_defconfig
In-Reply-To: <1275635441-17378-9-git-send-email-olof@lixom.net>
References: <3478yvr76gerav> <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
	<1275635441-17378-3-git-send-email-olof@lixom.net>
	<1275635441-17378-4-git-send-email-olof@lixom.net>
	<1275635441-17378-5-git-send-email-olof@lixom.net>
	<1275635441-17378-6-git-send-email-olof@lixom.net>
	<1275635441-17378-7-git-send-email-olof@lixom.net>
	<1275635441-17378-8-git-send-email-olof@lixom.net>
	<1275635441-17378-9-git-send-email-olof@lixom.net>
Message-ID: <1275635441-17378-10-git-send-email-olof@lixom.net>

We'll keep tegra_defconfig as the SoC-specific superset defconfig
that will contain relevant options for all supported boards, to avoid
proliferation of board-specific defconfigs.

Signed-off-by: Olof Johansson <olof at lixom.net>
---
 arch/arm/configs/tegra_defconfig | 1849 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 1849 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/configs/tegra_defconfig

diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
new file mode 100644
index 0000000..ab3e57b
--- /dev/null
+++ b/arch/arm/configs/tegra_defconfig
@@ -0,0 +1,1849 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.34
+# Fri Jun  4 01:11:30 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_LOCKBREAK=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_SWAP=y
+# CONFIG_SYSVIPC is not set
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+# CONFIG_CGROUP_NS is not set
+CONFIG_CGROUP_FREEZER=y
+# CONFIG_CGROUP_DEVICE is not set
+# CONFIG_CPUSETS is not set
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+# CONFIG_CGROUP_MEM_RES_CTLR is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_LZO is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+CONFIG_ARCH_TEGRA=y
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+
+#
+# NVIDIA Tegra options
+#
+CONFIG_ARCH_TEGRA_2x_SOC=y
+CONFIG_MACH_HARMONY=y
+CONFIG_TEGRA_DEBUG_UART_NONE=y
+# CONFIG_TEGRA_DEBUG_UARTA is not set
+# CONFIG_TEGRA_DEBUG_UARTB is not set
+# CONFIG_TEGRA_DEBUG_UARTC is not set
+# CONFIG_TEGRA_DEBUG_UARTD is not set
+# CONFIG_TEGRA_DEBUG_UARTE is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_CPU_HAS_PMU=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_ARM_GIC=y
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_SMP=y
+CONFIG_HAVE_ARM_SCU=y
+CONFIG_HAVE_ARM_TWD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_NR_CPUS=2
+CONFIG_HOTPLUG_CPU=y
+CONFIG_LOCAL_TIMERS=y
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=448M at 0M console=ttyS0,115200n8 earlyprintk init=/bin/ash"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+# CONFIG_NEON is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP_SMP=y
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+# CONFIG_PM_RUNTIME is not set
+CONFIG_PM_OPS=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+CONFIG_INET_ESP=y
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+# CONFIG_IPV6_ROUTE_INFO is not set
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_INET6_XFRM_TUNNEL=y
+CONFIG_INET6_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+# CONFIG_IPV6_SUBTREES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=y
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
+CONFIG_BT_RFCOMM=y
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=y
+# CONFIG_BT_BNEP_MC_FILTER is not set
+# CONFIG_BT_BNEP_PROTO_FILTER is not set
+CONFIG_BT_HIDP=y
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=y
+CONFIG_BT_HCIUART_H4=y
+# CONFIG_BT_HCIUART_BCSP is not set
+CONFIG_BT_HCIUART_LL=y
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_LIB80211 is not set
+
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=y
+# CONFIG_RFKILL_INPUT is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IWMC3200TOP is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+CONFIG_MD=y
+# CONFIG_BLK_DEV_MD is not set
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_DEBUG=y
+CONFIG_DM_CRYPT=y
+# CONFIG_DM_SNAPSHOT is not set
+# CONFIG_DM_MIRROR is not set
+# CONFIG_DM_ZERO is not set
+# CONFIG_DM_MULTIPATH is not set
+# CONFIG_DM_DELAY is not set
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+CONFIG_ENC28J60=y
+# CONFIG_ENC28J60_WRITEVERIFY is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+CONFIG_KS8851=y
+# CONFIG_KS8851_MLL is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+CONFIG_WLAN=y
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_HOSTAP is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+# CONFIG_USB_NET_CDC_EEM is not set
+# CONFIG_USB_NET_DM9601 is not set
+CONFIG_USB_NET_SMSC75XX=y
+CONFIG_USB_NET_SMSC95XX=y
+# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_NET1080=y
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+# CONFIG_USB_NET_RNDIS_HOST is not set
+CONFIG_USB_NET_CDC_SUBSET=y
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=y
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+CONFIG_PPP_MPPE=y
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+CONFIG_W1=y
+
+#
+# 1-wire Bus Masters
+#
+# CONFIG_W1_MASTER_DS2490 is not set
+CONFIG_W1_MASTER_DS2482=y
+# CONFIG_W1_MASTER_DS1WM is not set
+# CONFIG_W1_MASTER_GPIO is not set
+
+#
+# 1-wire Slaves
+#
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_DS2431 is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+# CONFIG_W1_SLAVE_DS2760 is not set
+# CONFIG_W1_SLAVE_BQ27000 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PDA_POWER=y
+# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_AB4500_CORE is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_DEBUG=y
+# CONFIG_REGULATOR_DUMMY is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+CONFIG_REGULATOR_TPS65023=y
+# CONFIG_REGULATOR_TPS6507X is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+# CONFIG_VIDEO_ALLOW_V4L1 is not set
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+CONFIG_IR_CORE=y
+CONFIG_VIDEO_IR=y
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+# CONFIG_MEDIA_TUNER_CUSTOMISE is not set
+CONFIG_MEDIA_TUNER_SIMPLE=y
+CONFIG_MEDIA_TUNER_TDA8290=y
+CONFIG_MEDIA_TUNER_TDA9887=y
+CONFIG_MEDIA_TUNER_TEA5761=y
+CONFIG_MEDIA_TUNER_TEA5767=y
+CONFIG_MEDIA_TUNER_MT20XX=y
+CONFIG_MEDIA_TUNER_XC2028=y
+CONFIG_MEDIA_TUNER_XC5000=y
+CONFIG_MEDIA_TUNER_MC44S803=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_SOC_CAMERA is not set
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_USB_VIDEO_CLASS is not set
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZC0301 is not set
+CONFIG_USB_PWC_INPUT_EVDEV=y
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_I2C_SI4713 is not set
+# CONFIG_RADIO_SI4713 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_USB_MR800 is not set
+# CONFIG_RADIO_TEA5764 is not set
+# CONFIG_RADIO_SAA7706H is not set
+# CONFIG_RADIO_TEF6862 is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+# CONFIG_FB_CFB_FILLRECT is not set
+# CONFIG_FB_CFB_COPYAREA is not set
+# CONFIG_FB_CFB_IMAGEBLIT is not set
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_LOGO is not set
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_3M_PCT is not set
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MOSART is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_STANTUM is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_ZEROPLUS is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+# CONFIG_MMC_BLOCK_BOUNCE is not set
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+# CONFIG_RTC_INTF_SYSFS is not set
+# CONFIG_RTC_INTF_PROC is not set
+# CONFIG_RTC_INTF_DEV is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+CONFIG_STAGING=y
+# CONFIG_STAGING_EXCLUDE_BUILD is not set
+# CONFIG_USB_IP_COMMON is not set
+# CONFIG_PRISM2_USB is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_TRANZPORT is not set
+
+#
+# Qualcomm MSM Camera And Video
+#
+
+#
+# Camera Sensor Selection
+#
+# CONFIG_INPUT_GPIO is not set
+# CONFIG_POHMELFS is not set
+# CONFIG_VT6656 is not set
+# CONFIG_FB_UDL is not set
+
+#
+# RAR Register Driver
+#
+# CONFIG_RAR_REGISTER is not set
+# CONFIG_IIO is not set
+# CONFIG_RAMZSWAP is not set
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_STRIP is not set
+# CONFIG_FB_SM7XX is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+# CONFIG_DNOTIFY is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+# CONFIG_MSDOS_FS is not set
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+CONFIG_DEBUG_SLAB=y
+# CONFIG_DEBUG_SLAB_LEAK is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+CONFIG_DEBUG_SG=y
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
-- 
1.5.6.5



From olof at lixom.net  Fri Jun  4 03:10:39 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri,  4 Jun 2010 02:10:39 -0500
Subject: [PATCH 07/10] [ARM] tegra: add pinmux support
In-Reply-To: <1275635441-17378-7-git-send-email-olof@lixom.net>
References: <3478yvr76gerav> <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
	<1275635441-17378-3-git-send-email-olof@lixom.net>
	<1275635441-17378-4-git-send-email-olof@lixom.net>
	<1275635441-17378-5-git-send-email-olof@lixom.net>
	<1275635441-17378-6-git-send-email-olof@lixom.net>
	<1275635441-17378-7-git-send-email-olof@lixom.net>
Message-ID: <1275635441-17378-8-git-send-email-olof@lixom.net>

From: Erik Gilling <konkers at android.com>

v2: fixes from Russell King
	- include linux/io.h instead of asm/io.h

Olof:
	- checkpatch cleanups
	- switched from typedefs to regular enums

Signed-off-by: Erik Gilling <konkers at android.com>
Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Olof Johansson <olof at lixom.net>
---
 arch/arm/mach-tegra/Makefile              |    2 +
 arch/arm/mach-tegra/include/mach/pinmux.h |  241 +++++++++++++
 arch/arm/mach-tegra/pinmux.c              |  550 +++++++++++++++++++++++++++++
 3 files changed, 793 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-tegra/pinmux.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 122f7dc..5e47a71 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -4,6 +4,8 @@ obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += gpio.o
+obj-y                                   += pinmux.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
new file mode 100644
index 0000000..b52c35c
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -0,0 +1,241 @@
+/*
+ * linux/arch/arm/mach-tegra/include/mach/pinmux.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_PINMUX_H
+#define __MACH_TEGRA_PINMUX_H
+
+enum tegra_pingroup {
+	TEGRA_PINGROUP_ATA = 0,
+	TEGRA_PINGROUP_ATB,
+	TEGRA_PINGROUP_ATC,
+	TEGRA_PINGROUP_ATD,
+	TEGRA_PINGROUP_ATE,
+	TEGRA_PINGROUP_CDEV1,
+	TEGRA_PINGROUP_CDEV2,
+	TEGRA_PINGROUP_CRTP,
+	TEGRA_PINGROUP_CSUS,
+	TEGRA_PINGROUP_DAP1,
+	TEGRA_PINGROUP_DAP2,
+	TEGRA_PINGROUP_DAP3,
+	TEGRA_PINGROUP_DAP4,
+	TEGRA_PINGROUP_DDC,
+	TEGRA_PINGROUP_DTA,
+	TEGRA_PINGROUP_DTB,
+	TEGRA_PINGROUP_DTC,
+	TEGRA_PINGROUP_DTD,
+	TEGRA_PINGROUP_DTE,
+	TEGRA_PINGROUP_DTF,
+	TEGRA_PINGROUP_GMA,
+	TEGRA_PINGROUP_GMB,
+	TEGRA_PINGROUP_GMC,
+	TEGRA_PINGROUP_GMD,
+	TEGRA_PINGROUP_GME,
+	TEGRA_PINGROUP_GPU,
+	TEGRA_PINGROUP_GPU7,
+	TEGRA_PINGROUP_GPV,
+	TEGRA_PINGROUP_HDINT,
+	TEGRA_PINGROUP_I2CP,
+	TEGRA_PINGROUP_IRRX,
+	TEGRA_PINGROUP_IRTX,
+	TEGRA_PINGROUP_KBCA,
+	TEGRA_PINGROUP_KBCB,
+	TEGRA_PINGROUP_KBCC,
+	TEGRA_PINGROUP_KBCD,
+	TEGRA_PINGROUP_KBCE,
+	TEGRA_PINGROUP_KBCF,
+	TEGRA_PINGROUP_LCSN,
+	TEGRA_PINGROUP_LD0,
+	TEGRA_PINGROUP_LD1,
+	TEGRA_PINGROUP_LD10,
+	TEGRA_PINGROUP_LD11,
+	TEGRA_PINGROUP_LD12,
+	TEGRA_PINGROUP_LD13,
+	TEGRA_PINGROUP_LD14,
+	TEGRA_PINGROUP_LD15,
+	TEGRA_PINGROUP_LD16,
+	TEGRA_PINGROUP_LD17,
+	TEGRA_PINGROUP_LD2,
+	TEGRA_PINGROUP_LD3,
+	TEGRA_PINGROUP_LD4,
+	TEGRA_PINGROUP_LD5,
+	TEGRA_PINGROUP_LD6,
+	TEGRA_PINGROUP_LD7,
+	TEGRA_PINGROUP_LD8,
+	TEGRA_PINGROUP_LD9,
+	TEGRA_PINGROUP_LDC,
+	TEGRA_PINGROUP_LDI,
+	TEGRA_PINGROUP_LHP0,
+	TEGRA_PINGROUP_LHP1,
+	TEGRA_PINGROUP_LHP2,
+	TEGRA_PINGROUP_LHS,
+	TEGRA_PINGROUP_LM0,
+	TEGRA_PINGROUP_LM1,
+	TEGRA_PINGROUP_LPP,
+	TEGRA_PINGROUP_LPW0,
+	TEGRA_PINGROUP_LPW1,
+	TEGRA_PINGROUP_LPW2,
+	TEGRA_PINGROUP_LSC0,
+	TEGRA_PINGROUP_LSC1,
+	TEGRA_PINGROUP_LSCK,
+	TEGRA_PINGROUP_LSDA,
+	TEGRA_PINGROUP_LSDI,
+	TEGRA_PINGROUP_LSPI,
+	TEGRA_PINGROUP_LVP0,
+	TEGRA_PINGROUP_LVP1,
+	TEGRA_PINGROUP_LVS,
+	TEGRA_PINGROUP_OWC,
+	TEGRA_PINGROUP_PMC,
+	TEGRA_PINGROUP_PTA,
+	TEGRA_PINGROUP_RM,
+	TEGRA_PINGROUP_SDB,
+	TEGRA_PINGROUP_SDC,
+	TEGRA_PINGROUP_SDD,
+	TEGRA_PINGROUP_SDIO1,
+	TEGRA_PINGROUP_SLXA,
+	TEGRA_PINGROUP_SLXC,
+	TEGRA_PINGROUP_SLXD,
+	TEGRA_PINGROUP_SLXK,
+	TEGRA_PINGROUP_SPDI,
+	TEGRA_PINGROUP_SPDO,
+	TEGRA_PINGROUP_SPIA,
+	TEGRA_PINGROUP_SPIB,
+	TEGRA_PINGROUP_SPIC,
+	TEGRA_PINGROUP_SPID,
+	TEGRA_PINGROUP_SPIE,
+	TEGRA_PINGROUP_SPIF,
+	TEGRA_PINGROUP_SPIG,
+	TEGRA_PINGROUP_SPIH,
+	TEGRA_PINGROUP_UAA,
+	TEGRA_PINGROUP_UAB,
+	TEGRA_PINGROUP_UAC,
+	TEGRA_PINGROUP_UAD,
+	TEGRA_PINGROUP_UCA,
+	TEGRA_PINGROUP_UCB,
+	TEGRA_PINGROUP_UDA,
+	/* these pin groups only have pullup and pull down control */
+	TEGRA_PINGROUP_CK32,
+	TEGRA_PINGROUP_DDRC,
+	TEGRA_PINGROUP_PMCA,
+	TEGRA_PINGROUP_PMCB,
+	TEGRA_PINGROUP_PMCC,
+	TEGRA_PINGROUP_PMCD,
+	TEGRA_PINGROUP_PMCE,
+	TEGRA_PINGROUP_XM2C,
+	TEGRA_PINGROUP_XM2D,
+	TEGRA_MAX_PINGROUP,
+};
+
+enum tegra_mux_func {
+	TEGRA_MUX_RSVD = 0x8000,
+	TEGRA_MUX_RSVD1 = 0x8000,
+	TEGRA_MUX_RSVD2 = 0x8001,
+	TEGRA_MUX_RSVD3 = 0x8002,
+	TEGRA_MUX_RSVD4 = 0x8003,
+	TEGRA_MUX_NONE = -1,
+	TEGRA_MUX_AHB_CLK,
+	TEGRA_MUX_APB_CLK,
+	TEGRA_MUX_AUDIO_SYNC,
+	TEGRA_MUX_CRT,
+	TEGRA_MUX_DAP1,
+	TEGRA_MUX_DAP2,
+	TEGRA_MUX_DAP3,
+	TEGRA_MUX_DAP4,
+	TEGRA_MUX_DAP5,
+	TEGRA_MUX_DISPLAYA,
+	TEGRA_MUX_DISPLAYB,
+	TEGRA_MUX_EMC_TEST0_DLL,
+	TEGRA_MUX_EMC_TEST1_DLL,
+	TEGRA_MUX_GMI,
+	TEGRA_MUX_GMI_INT,
+	TEGRA_MUX_HDMI,
+	TEGRA_MUX_I2C,
+	TEGRA_MUX_I2C2,
+	TEGRA_MUX_I2C3,
+	TEGRA_MUX_IDE,
+	TEGRA_MUX_IRDA,
+	TEGRA_MUX_KBC,
+	TEGRA_MUX_MIO,
+	TEGRA_MUX_MIPI_HS,
+	TEGRA_MUX_NAND,
+	TEGRA_MUX_OSC,
+	TEGRA_MUX_OWR,
+	TEGRA_MUX_PCIE,
+	TEGRA_MUX_PLLA_OUT,
+	TEGRA_MUX_PLLC_OUT1,
+	TEGRA_MUX_PLLM_OUT1,
+	TEGRA_MUX_PLLP_OUT2,
+	TEGRA_MUX_PLLP_OUT3,
+	TEGRA_MUX_PLLP_OUT4,
+	TEGRA_MUX_PWM,
+	TEGRA_MUX_PWR_INTR,
+	TEGRA_MUX_PWR_ON,
+	TEGRA_MUX_RTCK,
+	TEGRA_MUX_SDIO1,
+	TEGRA_MUX_SDIO2,
+	TEGRA_MUX_SDIO3,
+	TEGRA_MUX_SDIO4,
+	TEGRA_MUX_SFLASH,
+	TEGRA_MUX_SPDIF,
+	TEGRA_MUX_SPI1,
+	TEGRA_MUX_SPI2,
+	TEGRA_MUX_SPI2_ALT,
+	TEGRA_MUX_SPI3,
+	TEGRA_MUX_SPI4,
+	TEGRA_MUX_TRACE,
+	TEGRA_MUX_TWC,
+	TEGRA_MUX_UARTA,
+	TEGRA_MUX_UARTB,
+	TEGRA_MUX_UARTC,
+	TEGRA_MUX_UARTD,
+	TEGRA_MUX_UARTE,
+	TEGRA_MUX_ULPI,
+	TEGRA_MUX_VI,
+	TEGRA_MUX_VI_SENSOR_CLK,
+	TEGRA_MUX_XIO,
+	TEGRA_MAX_MUX,
+};
+
+enum tegra_pullupdown {
+	TEGRA_PUPD_NORMAL = 0,
+	TEGRA_PUPD_PULL_DOWN,
+	TEGRA_PUPD_PULL_UP,
+};
+
+enum tegra_tristate {
+	TEGRA_TRI_NORMAL = 0,
+	TEGRA_TRI_TRISTATE = 1,
+};
+
+struct tegra_pingroup_config {
+	enum tegra_pingroup	pingroup;
+	enum tegra_mux_func	func;
+	enum tegra_pullupdown	pupd;
+	enum tegra_tristate	tristate;
+};
+
+int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func);
+int tegra_pinmux_set_tristate(enum tegra_pingroup pg, enum tegra_tristate tristate);
+int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, enum tegra_pullupdown pupd);
+
+void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup,
+				  enum tegra_mux_func func,
+				  enum tegra_pullupdown pupd,
+				  enum tegra_tristate tristate);
+
+void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len);
+
+#endif
+
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
new file mode 100644
index 0000000..34a403e
--- /dev/null
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -0,0 +1,550 @@
+/*
+ * linux/arch/arm/mach-tegra/pinmux.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+
+#include <mach/iomap.h>
+#include <mach/pinmux.h>
+
+
+#define TEGRA_TRI_STATE(x)	(0x14 + (4 * (x)))
+#define TEGRA_PP_MUX_CTL(x)	(0x80 + (4 * (x)))
+#define TEGRA_PP_PU_PD(x)	(0xa0 + (4 * (x)))
+
+#define REG_A 0
+#define REG_B 1
+#define REG_C 2
+#define REG_D 3
+#define REG_E 4
+#define REG_F 5
+#define REG_G 6
+
+#define REG_N -1
+
+struct tegra_pingroup_desc {
+	const char *name;
+	int funcs[4];
+	s8 tri_reg;	/* offset into the TRISTATE_REG_* register bank */
+	s8 tri_bit;	/* offset into the TRISTATE_REG_* register bit */
+	s8 mux_reg;	/* offset into the PIN_MUX_CTL_* register bank */
+	s8 mux_bit;	/* offset into the PIN_MUX_CTL_* register bit */
+	s8 pupd_reg;	/* offset into the PULL_UPDOWN_REG_* register bank */
+	s8 pupd_bit;	/* offset into the PULL_UPDOWN_REG_* register bit */
+};
+
+#define PINGROUP(pg_name, f0, f1, f2, f3,			\
+		 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b)	\
+	[TEGRA_PINGROUP_ ## pg_name] = {			\
+		.name = #pg_name,				\
+		.funcs = {					\
+			TEGRA_MUX_ ## f0,			\
+			TEGRA_MUX_ ## f1,			\
+			TEGRA_MUX_ ## f2,			\
+			TEGRA_MUX_ ## f3,			\
+		},						\
+		.tri_reg = REG_ ## tri_r,			\
+		.tri_bit = tri_b,				\
+		.mux_reg = REG_ ## mux_r,			\
+		.mux_bit = mux_b,				\
+		.pupd_reg = REG_ ## pupd_r,			\
+		.pupd_bit = pupd_b,				\
+	}
+
+static const struct tegra_pingroup_desc pingroups[TEGRA_MAX_PINGROUP] = {
+	PINGROUP(ATA,   IDE,       NAND,      GMI,       RSVD,          A, 0,  A, 24, A, 0),
+	PINGROUP(ATB,   IDE,       NAND,      GMI,       SDIO4,         A, 1,  A, 16, A, 2),
+	PINGROUP(ATC,   IDE,       NAND,      GMI,       SDIO4,         A, 2,  A, 22, A, 4),
+	PINGROUP(ATD,   IDE,       NAND,      GMI,       SDIO4,         A, 3,  A, 20, A, 6),
+	PINGROUP(ATE,   IDE,       NAND,      GMI,       RSVD,          B, 25, A, 12, A, 8),
+	PINGROUP(CDEV1, OSC,       PLLA_OUT,  PLLM_OUT1, AUDIO_SYNC,    A, 4,  C, 2,  C, 0),
+	PINGROUP(CDEV2, OSC,       AHB_CLK,   APB_CLK,   PLLP_OUT4,     A, 5,  C, 4,  C, 2),
+	PINGROUP(CRTP,  CRT,       RSVD,      RSVD,      RSVD,          D, 14, G, 20, B, 24),
+	PINGROUP(CSUS,  PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, A, 6,  C, 6,  D, 24),
+	PINGROUP(DAP1,  DAP1,      RSVD,      GMI,       SDIO2,         A, 7,  C, 20, A, 10),
+	PINGROUP(DAP2,  DAP2,      TWC,       RSVD,      GMI,           A, 8,  C, 22, A, 12),
+	PINGROUP(DAP3,  DAP3,      RSVD,      RSVD,      RSVD,          A, 9,  C, 24, A, 14),
+	PINGROUP(DAP4,  DAP4,      RSVD,      GMI,       RSVD,          A, 10, C, 26, A, 16),
+	PINGROUP(DDC,   I2C2,      RSVD,      RSVD,      RSVD,          B, 31, C, 0,  E, 28),
+	PINGROUP(DTA,   RSVD,      SDIO2,     VI,        RSVD,          A, 11, B, 20, A, 18),
+	PINGROUP(DTB,   RSVD,      RSVD,      VI,        SPI1,          A, 12, B, 22, A, 20),
+	PINGROUP(DTC,   RSVD,      RSVD,      VI,        RSVD,          A, 13, B, 26, A, 22),
+	PINGROUP(DTD,   RSVD,      SDIO2,     VI,        RSVD,          A, 14, B, 28, A, 24),
+	PINGROUP(DTE,   RSVD,      RSVD,      VI,        SPI1,          A, 15, B, 30, A, 26),
+	PINGROUP(DTF,   I2C3,      RSVD,      VI,        RSVD,          D, 12, G, 30, A, 28),
+	PINGROUP(GMA,   UARTE,     SPI3,      GMI,       SDIO4,         A, 28, B, 0,  E, 20),
+	PINGROUP(GMB,   IDE,       NAND,      GMI,       GMI_INT,       B, 29, C, 28, E, 22),
+	PINGROUP(GMC,   UARTD,     SPI4,      GMI,       SFLASH,        A, 29, B, 2,  E, 24),
+	PINGROUP(GMD,   RSVD,      NAND,      GMI,       SFLASH,        B, 30, C, 30, E, 26),
+	PINGROUP(GME,   RSVD,      DAP5,      GMI,       SDIO4,         B, 0,  D, 0,  C, 24),
+	PINGROUP(GPU,   PWM,       UARTA,     GMI,       RSVD,          A, 16, D, 4,  B, 20),
+	PINGROUP(GPU7,  RTCK,      RSVD,      RSVD,      RSVD,          D, 11, G, 28, B, 6),
+	PINGROUP(GPV,   PCIE,      RSVD,      RSVD,      RSVD,          A, 17, D, 2,  A, 30),
+	PINGROUP(HDINT, HDMI,      RSVD,      RSVD,      RSVD,          C, 23, B, 4,  D, 22),
+	PINGROUP(I2CP,  I2C,       RSVD,      RSVD,      RSVD,          A, 18, C, 8,  B, 2),
+	PINGROUP(IRRX,  UARTA,     UARTB,     GMI,       SPI4,          A, 20, C, 18, C, 22),
+	PINGROUP(IRTX,  UARTA,     UARTB,     GMI,       SPI4,          A, 19, C, 16, C, 20),
+	PINGROUP(KBCA,  KBC,       NAND,      SDIO2,     EMC_TEST0_DLL, A, 22, C, 10, B, 8),
+	PINGROUP(KBCB,  KBC,       NAND,      SDIO2,     MIO,           A, 21, C, 12, B, 10),
+	PINGROUP(KBCC,  KBC,       NAND,      TRACE,     EMC_TEST1_DLL, B, 26, C, 14, B, 12),
+	PINGROUP(KBCD,  KBC,       NAND,      SDIO2,     MIO,           D, 10, G, 26, B, 14),
+	PINGROUP(KBCE,  KBC,       NAND,      OWR,       RSVD,          A, 26, A, 28, E, 2),
+	PINGROUP(KBCF,  KBC,       NAND,      TRACE,     MIO,           A, 27, A, 26, E, 0),
+	PINGROUP(LCSN,  DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          C, 31, E, 12, D, 20),
+	PINGROUP(LD0,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 0,  F, 0,  D, 12),
+	PINGROUP(LD1,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 1,  F, 2,  D, 12),
+	PINGROUP(LD10,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 10, F, 20, D, 12),
+	PINGROUP(LD11,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 11, F, 22, D, 12),
+	PINGROUP(LD12,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 12, F, 24, D, 12),
+	PINGROUP(LD13,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 13, F, 26, D, 12),
+	PINGROUP(LD14,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 14, F, 28, D, 12),
+	PINGROUP(LD15,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 15, F, 30, D, 12),
+	PINGROUP(LD16,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 16, G, 0,  D, 12),
+	PINGROUP(LD17,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 17, G, 2,  D, 12),
+	PINGROUP(LD2,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 2,  F, 4,  D, 12),
+	PINGROUP(LD3,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 3,  F, 6,  D, 12),
+	PINGROUP(LD4,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 4,  F, 8,  D, 12),
+	PINGROUP(LD5,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 5,  F, 10, D, 12),
+	PINGROUP(LD6,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 6,  F, 12, D, 12),
+	PINGROUP(LD7,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 7,  F, 14, D, 12),
+	PINGROUP(LD8,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 8,  F, 16, D, 12),
+	PINGROUP(LD9,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 9,  F, 18, D, 12),
+	PINGROUP(LDC,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 30, E, 14, D, 20),
+	PINGROUP(LDI,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          D, 6,  G, 16, D, 18),
+	PINGROUP(LHP0,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 18, G, 10, D, 16),
+	PINGROUP(LHP1,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 19, G, 4,  D, 14),
+	PINGROUP(LHP2,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 20, G, 6,  D, 14),
+	PINGROUP(LHS,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          D, 7,  E, 22, D, 22),
+	PINGROUP(LM0,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          C, 24, E, 26, D, 22),
+	PINGROUP(LM1,   DISPLAYA,  DISPLAYB,  RSVD,      CRT,           C, 25, E, 28, D, 22),
+	PINGROUP(LPP,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          D, 8,  G, 14, D, 18),
+	PINGROUP(LPW0,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          D, 3,  E, 0,  D, 20),
+	PINGROUP(LPW1,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          D, 4,  E, 2,  D, 20),
+	PINGROUP(LPW2,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          D, 5,  E, 4,  D, 20),
+	PINGROUP(LSC0,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 27, E, 18, D, 22),
+	PINGROUP(LSC1,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          C, 28, E, 20, D, 20),
+	PINGROUP(LSCK,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          C, 29, E, 16, D, 20),
+	PINGROUP(LSDA,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          D, 1,  E, 8,  D, 20),
+	PINGROUP(LSDI,  DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          D, 2,  E, 6,  D, 20),
+	PINGROUP(LSPI,  DISPLAYA,  DISPLAYB,  XIO,       HDMI,          D, 0,  E, 10, D, 22),
+	PINGROUP(LVP0,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 21, E, 30, D, 22),
+	PINGROUP(LVP1,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 22, G, 8,  D, 16),
+	PINGROUP(LVS,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 26, E, 24, D, 22),
+	PINGROUP(OWC,   OWR,       RSVD,      RSVD,      RSVD,          A, 31, B, 8,  E, 30),
+	PINGROUP(PMC,   PWR_ON,    PWR_INTR,  RSVD,      RSVD,          A, 23, G, 18, N, -1),
+	PINGROUP(PTA,   I2C2,      HDMI,      GMI,       RSVD,          A, 24, G, 22, B, 4),
+	PINGROUP(RM,    I2C,       RSVD,      RSVD,      RSVD,          A, 25, A, 14, B, 0),
+	PINGROUP(SDB,   UARTA,     PWM,       SDIO3,     SPI2,          D, 15, D, 10, N, -1),
+	PINGROUP(SDC,   PWM,       TWC,       SDIO3,     SPI3,          B, 1,  D, 12, D, 28),
+	PINGROUP(SDD,   UARTA,     PWM,       SDIO3,     SPI3,          B, 2,  D, 14, D, 30),
+	PINGROUP(SDIO1, SDIO1,     RSVD,      UARTE,     UARTA,         A, 30, A, 30, E, 18),
+	PINGROUP(SLXA,  PCIE,      SPI4,      SDIO3,     SPI2,          B, 3,  B, 6,  B, 22),
+	PINGROUP(SLXC,  SPDIF,     SPI4,      SDIO3,     SPI2,          B, 5,  B, 10, B, 26),
+	PINGROUP(SLXD,  SPDIF,     SPI4,      SDIO3,     SPI2,          B, 6,  B, 12, B, 28),
+	PINGROUP(SLXK,  PCIE,      SPI4,      SDIO3,     SPI2,          B, 7,  B, 14, B, 30),
+	PINGROUP(SPDI,  SPDIF,     RSVD,      I2C,       SDIO2,         B, 8,  D, 8,  B, 16),
+	PINGROUP(SPDO,  SPDIF,     RSVD,      I2C,       SDIO2,         B, 9,  D, 6,  B, 18),
+	PINGROUP(SPIA,  SPI1,      SPI2,      SPI3,      GMI,           B, 10, D, 30, C, 4),
+	PINGROUP(SPIB,  SPI1,      SPI2,      SPI3,      GMI,           B, 11, D, 28, C, 6),
+	PINGROUP(SPIC,  SPI1,      SPI2,      SPI3,      GMI,           B, 12, D, 26, C, 8),
+	PINGROUP(SPID,  SPI2,      SPI1,      SPI2_ALT,  GMI,           B, 13, D, 24, C, 10),
+	PINGROUP(SPIE,  SPI2,      SPI1,      SPI2_ALT,  GMI,           B, 14, D, 22, C, 12),
+	PINGROUP(SPIF,  SPI3,      SPI1,      SPI2,      RSVD,          B, 15, D, 20, C, 14),
+	PINGROUP(SPIG,  SPI3,      SPI2,      SPI2_ALT,  I2C,           B, 16, D, 18, C, 16),
+	PINGROUP(SPIH,  SPI3,      SPI2,      SPI2_ALT,  I2C,           B, 17, D, 16, C, 18),
+	PINGROUP(UAA,   SPI3,      MIPI_HS,   UARTA,     ULPI,          B, 18, A, 0,  D, 0),
+	PINGROUP(UAB,   SPI2,      MIPI_HS,   UARTA,     ULPI,          B, 19, A, 2,  D, 2),
+	PINGROUP(UAC,   OWR,       RSVD,      RSVD,      RSVD,          B, 20, A, 4,  D, 4),
+	PINGROUP(UAD,   IRDA,      SPDIF,     UARTA,     SPI4,          B, 21, A, 6,  D, 6),
+	PINGROUP(UCA,   UARTC,     RSVD,      GMI,       RSVD,          B, 22, B, 16, D, 8),
+	PINGROUP(UCB,   UARTC,     PWM,       GMI,       RSVD,          B, 23, B, 18, D, 10),
+	PINGROUP(UDA,   SPI1,      RSVD,      UARTD,     ULPI,          D, 13, A, 8,  E, 16),
+	/* these pin groups only have pullup and pull down control */
+	PINGROUP(CK32,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 14),
+	PINGROUP(DDRC,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  D, 26),
+	PINGROUP(PMCA,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 4),
+	PINGROUP(PMCB,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 6),
+	PINGROUP(PMCC,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 8),
+	PINGROUP(PMCD,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 10),
+	PINGROUP(PMCE,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 12),
+	PINGROUP(XM2C,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  C, 30),
+	PINGROUP(XM2D,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  C, 28),
+};
+
+static char *tegra_mux_names[TEGRA_MAX_MUX] = {
+	[TEGRA_MUX_AHB_CLK] = "AHB_CLK",
+	[TEGRA_MUX_APB_CLK] = "APB_CLK",
+	[TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
+	[TEGRA_MUX_CRT] = "CRT",
+	[TEGRA_MUX_DAP1] = "DAP1",
+	[TEGRA_MUX_DAP2] = "DAP2",
+	[TEGRA_MUX_DAP3] = "DAP3",
+	[TEGRA_MUX_DAP4] = "DAP4",
+	[TEGRA_MUX_DAP5] = "DAP5",
+	[TEGRA_MUX_DISPLAYA] = "DISPLAYA",
+	[TEGRA_MUX_DISPLAYB] = "DISPLAYB",
+	[TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
+	[TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
+	[TEGRA_MUX_GMI] = "GMI",
+	[TEGRA_MUX_GMI_INT] = "GMI_INT",
+	[TEGRA_MUX_HDMI] = "HDMI",
+	[TEGRA_MUX_I2C] = "I2C",
+	[TEGRA_MUX_I2C2] = "I2C2",
+	[TEGRA_MUX_I2C3] = "I2C3",
+	[TEGRA_MUX_IDE] = "IDE",
+	[TEGRA_MUX_IRDA] = "IRDA",
+	[TEGRA_MUX_KBC] = "KBC",
+	[TEGRA_MUX_MIO] = "MIO",
+	[TEGRA_MUX_MIPI_HS] = "MIPI_HS",
+	[TEGRA_MUX_NAND] = "NAND",
+	[TEGRA_MUX_OSC] = "OSC",
+	[TEGRA_MUX_OWR] = "OWR",
+	[TEGRA_MUX_PCIE] = "PCIE",
+	[TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
+	[TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
+	[TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
+	[TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
+	[TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
+	[TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
+	[TEGRA_MUX_PWM] = "PWM",
+	[TEGRA_MUX_PWR_INTR] = "PWR_INTR",
+	[TEGRA_MUX_PWR_ON] = "PWR_ON",
+	[TEGRA_MUX_RTCK] = "RTCK",
+	[TEGRA_MUX_SDIO1] = "SDIO1",
+	[TEGRA_MUX_SDIO2] = "SDIO2",
+	[TEGRA_MUX_SDIO3] = "SDIO3",
+	[TEGRA_MUX_SDIO4] = "SDIO4",
+	[TEGRA_MUX_SFLASH] = "SFLASH",
+	[TEGRA_MUX_SPDIF] = "SPDIF",
+	[TEGRA_MUX_SPI1] = "SPI1",
+	[TEGRA_MUX_SPI2] = "SPI2",
+	[TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
+	[TEGRA_MUX_SPI3] = "SPI3",
+	[TEGRA_MUX_SPI4] = "SPI4",
+	[TEGRA_MUX_TRACE] = "TRACE",
+	[TEGRA_MUX_TWC] = "TWC",
+	[TEGRA_MUX_UARTA] = "UARTA",
+	[TEGRA_MUX_UARTB] = "UARTB",
+	[TEGRA_MUX_UARTC] = "UARTC",
+	[TEGRA_MUX_UARTD] = "UARTD",
+	[TEGRA_MUX_UARTE] = "UARTE",
+	[TEGRA_MUX_ULPI] = "ULPI",
+	[TEGRA_MUX_VI] = "VI",
+	[TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
+	[TEGRA_MUX_XIO] = "XIO",
+};
+
+static DEFINE_SPINLOCK(mux_lock);
+
+static const char *pingroup_name(enum tegra_pingroup pg)
+{
+	if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+		return "<UNKNOWN>";
+
+	return pingroups[pg].name;
+}
+
+static const char *func_name(enum tegra_mux_func func)
+{
+	if (func == TEGRA_MUX_RSVD1)
+		return "RSVD1";
+
+	if (func == TEGRA_MUX_RSVD2)
+		return "RSVD2";
+
+	if (func == TEGRA_MUX_RSVD3)
+		return "RSVD3";
+
+	if (func == TEGRA_MUX_RSVD4)
+		return "RSVD4";
+
+	if (func == TEGRA_MUX_NONE)
+		return "NONE";
+
+	if (func < 0 || func >=  TEGRA_MAX_MUX)
+		return "<UNKNOWN>";
+
+	return tegra_mux_names[func];
+}
+
+
+static const char *tri_name(unsigned long val)
+{
+	return val ? "TRISTATE" : "NORMAL";
+}
+
+static const char *pupd_name(unsigned long val)
+{
+	switch (val) {
+	case 0:
+		return "NORMAL";
+
+	case 1:
+		return "PULL_DOWN";
+
+	case 2:
+		return "PULL_UP";
+
+	default:
+		return "RSVD";
+	}
+}
+
+
+static inline unsigned long pg_readl(unsigned long offset)
+{
+	return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
+}
+
+static inline void pg_writel(unsigned long value, unsigned long offset)
+{
+	writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
+}
+
+int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func)
+{
+	int mux = -1;
+	int i;
+	unsigned long reg;
+	unsigned long flags;
+
+	if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+		return -ERANGE;
+
+	if (pingroups[pg].mux_reg == REG_N)
+		return -EINVAL;
+
+	if (func < 0)
+		return -ERANGE;
+
+	if (func & TEGRA_MUX_RSVD) {
+		mux = func & 0x3;
+	} else {
+		for (i = 0; i < 4; i++) {
+			if (pingroups[pg].funcs[i] == func) {
+				mux = i;
+				break;
+			}
+		}
+	}
+
+	if (mux < 0)
+		return -EINVAL;
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg));
+	reg &= ~(0x3 << pingroups[pg].mux_bit);
+	reg |= mux << pingroups[pg].mux_bit;
+	pg_writel(reg, TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg));
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
+			      enum tegra_tristate tristate)
+{
+	unsigned long reg;
+	unsigned long flags;
+
+	if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+		return -ERANGE;
+
+	if (pingroups[pg].tri_reg == REG_N)
+		return -EINVAL;
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(TEGRA_TRI_STATE(pingroups[pg].tri_reg));
+	reg &= ~(0x1 << pingroups[pg].tri_bit);
+	if (tristate)
+		reg |= 1 << pingroups[pg].tri_bit;
+	pg_writel(reg, TEGRA_TRI_STATE(pingroups[pg].tri_reg));
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
+				enum tegra_pullupdown pupd)
+{
+	unsigned long reg;
+	unsigned long flags;
+
+	if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+		return -ERANGE;
+
+	if (pingroups[pg].pupd_reg == REG_N)
+		return -EINVAL;
+
+	if (pupd != TEGRA_PUPD_NORMAL &&
+	    pupd != TEGRA_PUPD_PULL_DOWN &&
+	    pupd != TEGRA_PUPD_PULL_UP)
+		return -EINVAL;
+
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(TEGRA_PP_PU_PD(pingroups[pg].pupd_reg));
+	reg &= ~(0x3 << pingroups[pg].pupd_bit);
+	reg |= pupd << pingroups[pg].pupd_bit;
+	pg_writel(reg, TEGRA_PP_PU_PD(pingroups[pg].pupd_reg));
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup,
+				 enum tegra_mux_func func,
+				 enum tegra_pullupdown pupd,
+				 enum tegra_tristate tristate)
+{
+	int err;
+
+	if (pingroups[pingroup].mux_reg != REG_N) {
+		err = tegra_pinmux_set_func(pingroup, func);
+		if (err < 0)
+			pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
+			       pingroup_name(pingroup), func_name(func), err);
+	}
+
+	if (pingroups[pingroup].pupd_reg != REG_N) {
+		err = tegra_pinmux_set_pullupdown(pingroup, pupd);
+		if (err < 0)
+			pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
+			       pingroup_name(pingroup), pupd_name(pupd), err);
+	}
+
+	if (pingroups[pingroup].tri_reg != REG_N) {
+		err = tegra_pinmux_set_tristate(pingroup, tristate);
+		if (err < 0)
+			pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
+			       pingroup_name(pingroup), tri_name(func), err);
+	}
+}
+
+
+
+void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		tegra_pinmux_config_pingroup(config[i].pingroup,
+					     config[i].func,
+					     config[i].pupd,
+					     config[i].tristate);
+}
+
+
+
+
+
+#ifdef	CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static void dbg_pad_field(struct seq_file *s, int len)
+{
+	seq_putc(s, ',');
+
+	while (len-- > -1)
+		seq_putc(s, ' ');
+}
+
+static int dbg_pinmux_show(struct seq_file *s, void *unused)
+{
+	int i;
+	int len;
+
+	for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+		unsigned long tri;
+		unsigned long mux;
+		unsigned long pupd;
+
+		seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
+		len = strlen(pingroups[i].name);
+		dbg_pad_field(s, 5 - len);
+
+		if (pingroups[i].mux_reg == REG_N) {
+			seq_printf(s, "TEGRA_MUX_NONE");
+			len = strlen("NONE");
+		} else {
+			mux = (pg_readl(TEGRA_PP_MUX_CTL(pingroups[i].mux_reg)) >>
+			       pingroups[i].mux_bit) & 0x3;
+			if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
+				seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
+				len = 5;
+			} else {
+				seq_printf(s, "TEGRA_MUX_%s",
+					   tegra_mux_names[pingroups[i].funcs[mux]]);
+				len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
+			}
+		}
+		dbg_pad_field(s, 13-len);
+
+		if (pingroups[i].mux_reg == REG_N) {
+			seq_printf(s, "TEGRA_PUPD_NORMAL");
+			len = strlen("NORMAL");
+		} else {
+			pupd = (pg_readl(TEGRA_PP_PU_PD(pingroups[i].pupd_reg)) >>
+				pingroups[i].pupd_bit) & 0x3;
+			seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
+			len = strlen(pupd_name(pupd));
+		}
+		dbg_pad_field(s, 9 - len);
+
+		if (pingroups[i].tri_reg == REG_N) {
+			seq_printf(s, "TEGRA_TRI_NORMAL");
+		} else {
+			tri = (pg_readl(TEGRA_TRI_STATE(pingroups[i].tri_reg)) >>
+			       pingroups[i].tri_bit) & 0x1;
+
+			seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
+		}
+		seq_printf(s, "},\n");
+	}
+	return 0;
+}
+
+static int dbg_pinmux_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, dbg_pinmux_show, &inode->i_private);
+}
+
+static const struct file_operations debug_fops = {
+	.open		= dbg_pinmux_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int __init tegra_pinmux_debuginit(void)
+{
+	(void) debugfs_create_file("tegra_pinmux", S_IRUGO,
+					NULL, NULL, &debug_fops);
+	return 0;
+}
+late_initcall(tegra_pinmux_debuginit);
+#endif
-- 
1.5.6.5



From olof at lixom.net  Fri Jun  4 03:10:33 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri,  4 Jun 2010 02:10:33 -0500
Subject: [PATCH 01/10] [ARM] tegra: initial tegra support
In-Reply-To: <1275635441-17378-1-git-send-email-olof@lixom.net>
References: <3478yvr76gerav> <1275635441-17378-1-git-send-email-olof@lixom.net>
Message-ID: <1275635441-17378-2-git-send-email-olof@lixom.net>

From: Erik Gilling <konkers at android.com>

v2: Fixes from Mike Rapoport
	- remove unused header files (mach/dma.h and mach/nand.h)
	- remove tegra 1 references from Makefile.boot

v2: fixes from Russell King
	- remove mach/io.h include from mach/iomap.h
	- fix whitespace in Kconfig

v2: from Colin Cross
	- fix invalid immediate in debug-macro.S

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Erik Gilling <konkers at android.com>
Signed-off-by: Olof Johansson <olof at lixom.net>
---
 arch/arm/Kconfig                               |   13 ++
 arch/arm/Makefile                              |    1 +
 arch/arm/mach-tegra/Kconfig                    |   53 ++++++
 arch/arm/mach-tegra/Makefile                   |    2 +
 arch/arm/mach-tegra/Makefile.boot              |    3 +
 arch/arm/mach-tegra/board.h                    |   32 ++++
 arch/arm/mach-tegra/common.c                   |   44 +++++
 arch/arm/mach-tegra/include/mach/barriers.h    |   30 ++++
 arch/arm/mach-tegra/include/mach/debug-macro.S |   46 ++++++
 arch/arm/mach-tegra/include/mach/entry-macro.S |  118 ++++++++++++++
 arch/arm/mach-tegra/include/mach/hardware.h    |   24 +++
 arch/arm/mach-tegra/include/mach/io.h          |   79 +++++++++
 arch/arm/mach-tegra/include/mach/iomap.h       |  203 ++++++++++++++++++++++++
 arch/arm/mach-tegra/include/mach/memory.h      |   28 ++++
 arch/arm/mach-tegra/include/mach/system.h      |   39 +++++
 arch/arm/mach-tegra/include/mach/timex.h       |   26 +++
 arch/arm/mach-tegra/include/mach/uncompress.h  |   78 +++++++++
 arch/arm/mach-tegra/include/mach/vmalloc.h     |   28 ++++
 arch/arm/mach-tegra/io.c                       |   78 +++++++++
 arch/arm/mm/Kconfig                            |    2 +-
 20 files changed, 926 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-tegra/Kconfig
 create mode 100644 arch/arm/mach-tegra/Makefile
 create mode 100644 arch/arm/mach-tegra/Makefile.boot
 create mode 100644 arch/arm/mach-tegra/board.h
 create mode 100644 arch/arm/mach-tegra/common.c
 create mode 100644 arch/arm/mach-tegra/include/mach/barriers.h
 create mode 100644 arch/arm/mach-tegra/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-tegra/include/mach/entry-macro.S
 create mode 100644 arch/arm/mach-tegra/include/mach/hardware.h
 create mode 100644 arch/arm/mach-tegra/include/mach/io.h
 create mode 100644 arch/arm/mach-tegra/include/mach/iomap.h
 create mode 100644 arch/arm/mach-tegra/include/mach/memory.h
 create mode 100644 arch/arm/mach-tegra/include/mach/system.h
 create mode 100644 arch/arm/mach-tegra/include/mach/timex.h
 create mode 100644 arch/arm/mach-tegra/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-tegra/include/mach/vmalloc.h
 create mode 100644 arch/arm/mach-tegra/io.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 92622eb..388f371 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -575,6 +575,17 @@ config ARCH_NUC93X
 	  Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
 	  low-power and high performance MPEG-4/JPEG multimedia controller chip.
 
+config ARCH_TEGRA
+	bool "NVIDIA Tegra"
+	select GENERIC_TIME
+	select GENERIC_CLOCKEVENTS
+	select GENERIC_GPIO
+	select HAVE_CLK
+	select ARCH_HAS_BARRIERS if CACHE_L2X0
+	help
+	  This enables support for NVIDIA Tegra based systems (Tegra APX,
+	  Tegra 6xx and Tegra 2 series).
+
 config ARCH_PNX4008
 	bool "Philips Nexperia PNX4008 Mobile"
 	select CPU_ARM926T
@@ -914,6 +925,8 @@ source "arch/arm/mach-shmobile/Kconfig"
 
 source "arch/arm/plat-stmp3xxx/Kconfig"
 
+source "arch/arm/mach-tegra/Kconfig"
+
 source "arch/arm/mach-u300/Kconfig"
 
 source "arch/arm/mach-ux500/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ed820e7..ddc6cb6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -172,6 +172,7 @@ machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile
 machine-$(CONFIG_ARCH_STMP378X)		:= stmp378x
 machine-$(CONFIG_ARCH_STMP37XX)		:= stmp37xx
+machine-$(CONFIG_ARCH_TEGRA)		:= tegra
 machine-$(CONFIG_ARCH_U300)		:= u300
 machine-$(CONFIG_ARCH_U8500)		:= ux500
 machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
new file mode 100644
index 0000000..64ab14f
--- /dev/null
+++ b/arch/arm/mach-tegra/Kconfig
@@ -0,0 +1,53 @@
+if ARCH_TEGRA
+
+comment "NVIDIA Tegra options"
+
+choice
+	prompt "Select Tegra processor family for target system"
+
+config ARCH_TEGRA_2x_SOC
+	bool "Tegra 2 family"
+	select CPU_V7
+	select ARM_GIC
+	help
+	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
+	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
+
+endchoice
+
+
+choice
+	prompt "Select Tegra-based product"
+
+config MACH_HARMONY
+       bool "Harmony board"
+       help
+         Support for nVidia Harmony development platform
+
+endchoice
+
+choice
+        prompt "Low-level debug console UART"
+        default TEGRA_DEBUG_UART_NONE
+
+config TEGRA_DEBUG_UART_NONE
+        bool "None"
+
+config TEGRA_DEBUG_UARTA
+        bool "UART-A"
+
+config TEGRA_DEBUG_UARTB
+        bool "UART-B"
+
+config TEGRA_DEBUG_UARTC
+        bool "UART-C"
+
+config TEGRA_DEBUG_UARTD
+        bool "UART-D"
+
+config TEGRA_DEBUG_UARTE
+        bool "UART-E"
+
+endchoice
+
+endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
new file mode 100644
index 0000000..81f003d
--- /dev/null
+++ b/arch/arm/mach-tegra/Makefile
@@ -0,0 +1,2 @@
+obj-y                                   += common.o
+obj-y                                   += io.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
new file mode 100644
index 0000000..db52d61
--- /dev/null
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00008000
+params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00000100
+initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00800000
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
new file mode 100644
index 0000000..3d06354
--- /dev/null
+++ b/arch/arm/mach-tegra/board.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-tegra/board.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_BOARD_H
+#define __MACH_TEGRA_BOARD_H
+
+#include <linux/types.h>
+
+void __init tegra_common_init(void);
+void __init tegra_map_common_io(void);
+void __init tegra_init_irq(void);
+void __init tegra_init_clock(void);
+
+extern struct sys_timer tegra_timer;
+#endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
new file mode 100644
index 0000000..20875ee
--- /dev/null
+++ b/arch/arm/mach-tegra/common.c
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/mach-tegra/board-harmony.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/iomap.h>
+
+#include "board.h"
+
+void __init tegra_init_cache(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+	void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
+
+	writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
+	writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
+
+	l2x0_init(p, 0x6C080001, 0x8200c3fe);
+#endif
+}
+
+void __init tegra_common_init(void)
+{
+	tegra_init_cache();
+}
diff --git a/arch/arm/mach-tegra/include/mach/barriers.h b/arch/arm/mach-tegra/include/mach/barriers.h
new file mode 100644
index 0000000..cc11517
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/barriers.h
@@ -0,0 +1,30 @@
+/*
+ * arch/arm/mach-realview/include/mach/barriers.h
+ *
+ * Copyright (C) 2010 ARM Ltd.
+ * Written by Catalin Marinas <catalin.marinas at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __MACH_BARRIERS_H
+#define __MACH_BARRIERS_H
+
+#include <asm/outercache.h>
+
+#define rmb()		dmb()
+#define wmb()		do { dsb(); outer_sync(); } while (0)
+#define mb()		wmb()
+
+#endif	/* __MACH_BARRIERS_H */
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
new file mode 100644
index 0000000..55a3956
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -0,0 +1,46 @@
+/*
+ * arch/arm/mach-tegra/include/mach/debug-macro.S
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <mach/io.h>
+
+	.macro  addruart,rx, tmp
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                 @ MMU enabled?
+        ldreq   \rx, =IO_APB_PHYS       @ physical
+        ldrne   \rx, =IO_APB_VIRT        @ virtual
+#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
+#error "A debug UART must be selected in the kernel config to use DEBUG_LL"
+#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
+        orr     \rx, \rx, #0x6000
+#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
+	ldr	\tmp, =0x6040
+        orr     \rx, \rx, \tmp
+#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
+        orr     \rx, \rx, #0x6200
+#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
+        orr     \rx, \rx, #0x6300
+#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
+        orr     \rx, \rx, #0x6400
+#endif
+	.endm
+
+#define UART_SHIFT	2
+#include <asm/hardware/debug-8250.S>
+
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
new file mode 100644
index 0000000..2ba9e5c
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -0,0 +1,118 @@
+/* arch/arm/mach-tegra/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2009 Palm, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <mach/iomap.h>
+#include <mach/io.h>
+
+#if defined(CONFIG_ARM_GIC)
+
+#include <asm/hardware/gic.h>
+
+	/* Uses the GIC interrupt controller built into the cpu */
+#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
+
+	.macro	disable_fiq
+	.endm
+
+	.macro	get_irqnr_preamble, base, tmp
+	movw \base, #(ICTRL_BASE & 0x0000ffff)
+	movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
+	.endm
+
+	.macro  arch_ret_to_user, tmp1, tmp2
+	.endm
+
+	/*
+	 * The interrupt numbering scheme is defined in the
+	 * interrupt controller spec.  To wit:
+	 *
+	 * Interrupts 0-15 are IPI
+	 * 16-28 are reserved
+	 * 29-31 are local.  We allow 30 to be used for the watchdog.
+	 * 32-1020 are global
+	 * 1021-1022 are reserved
+	 * 1023 is "spurious" (no interrupt)
+	 *
+	 * For now, we ignore all local interrupts so only return an interrupt
+	 * if it's between 30 and 1020.  The test_for_ipi routine below will
+	 * pick up on IPIs.
+	 *
+	 * A simple read from the controller will tell us the number of the
+	 * highest priority enabled interrupt.  We then just need to check
+	 * whether it is in the valid range for an IRQ (30-1020 inclusive).
+	 */
+
+	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+	/* bits 12-10 = src CPU, 9-0 = int # */
+	ldr     \irqstat, [\base, #GIC_CPU_INTACK]
+
+	ldr		\tmp, =1021
+
+	bic     \irqnr, \irqstat, #0x1c00
+
+	cmp     \irqnr, #29
+	cmpcc	\irqnr, \irqnr
+	cmpne	\irqnr, \tmp
+	cmpcs	\irqnr, \irqnr
+
+	.endm
+
+	/* We assume that irqstat (the raw value of the IRQ acknowledge
+	 * register) is preserved from the macro above.
+	 * If there is an IPI, we immediately signal end of interrupt on the
+	 * controller, since this requires the original irqstat value which
+	 * we won't easily be able to recreate later.
+	 */
+
+	.macro test_for_ipi, irqnr, irqstat, base, tmp
+	bic	\irqnr, \irqstat, #0x1c00
+	cmp	\irqnr, #16
+	strcc	\irqstat, [\base, #GIC_CPU_EOI]
+	cmpcs	\irqnr, \irqnr
+	.endm
+
+	/* As above, this assumes that irqstat and base are preserved.. */
+
+	.macro test_for_ltirq, irqnr, irqstat, base, tmp
+	bic	\irqnr, \irqstat, #0x1c00
+	mov 	\tmp, #0
+	cmp	\irqnr, #29
+	moveq	\tmp, #1
+	streq	\irqstat, [\base, #GIC_CPU_EOI]
+	cmp	\tmp, #0
+	.endm
+
+#else
+	/* legacy interrupt controller for AP16 */
+	.macro	disable_fiq
+	.endm
+
+	.macro	get_irqnr_preamble, base, tmp
+	@ enable imprecise aborts
+	cpsie	a
+	@ EVP base at 0xf010f000
+	mov \base, #0xf0000000
+	orr \base, #0x00100000
+	orr \base, #0x0000f000
+	.endm
+
+	.macro	arch_ret_to_user, tmp1, tmp2
+	.endm
+
+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+	ldr \irqnr, [\base, #0x20]	@ EVT_IRQ_STS
+	cmp \irqnr, #0x80
+	.endm
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/hardware.h b/arch/arm/mach-tegra/include/mach/hardware.h
new file mode 100644
index 0000000..6014edf
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/hardware.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-tegra/include/mach/hardware.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_HARDWARE_H
+#define __MACH_TEGRA_HARDWARE_H
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
new file mode 100644
index 0000000..35edfc3
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -0,0 +1,79 @@
+/*
+ * arch/arm/mach-tegra/include/mach/io.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IO_H
+#define __MACH_TEGRA_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/* On TEGRA, many peripherals are very closely packed in
+ * two 256MB io windows (that actually only use about 64KB
+ * at the start of each).
+ *
+ * We will just map the first 1MB of each window (to minimize
+ * pt entries needed) and provide a macro to transform physical
+ * io addresses to an appropriate void __iomem *.
+ *
+ */
+
+#define IO_CPU_PHYS     0x50040000
+#define IO_CPU_VIRT     0xFE000000
+#define IO_CPU_SIZE	SZ_16K
+
+#define IO_PPSB_PHYS	0x60000000
+#define IO_PPSB_VIRT	0xFE200000
+#define IO_PPSB_SIZE	SZ_1M
+
+#define IO_APB_PHYS	0x70000000
+#define IO_APB_VIRT	0xFE300000
+#define IO_APB_SIZE	SZ_1M
+
+#define IO_TO_VIRT_BETWEEN(p, st, sz)	((p) >= (st) && (p) < ((st) + (sz)))
+#define IO_TO_VIRT_XLATE(p, pst, vst)	(((p) - (pst) + (vst)))
+
+#define IO_TO_VIRT(n) ( \
+	IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ?		\
+		IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) :	\
+	IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ?		\
+		IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) :	\
+	IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ?		\
+		IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :	\
+	0)
+
+#ifndef __ASSEMBLER__
+
+#define __arch_ioremap(p, s, t)	tegra_ioremap(p, s, t)
+#define __arch_iounmap(v)	tegra_iounmap(v)
+
+void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
+void tegra_iounmap(volatile void __iomem *addr);
+
+#define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n))
+
+static inline void __iomem *__io(unsigned long addr)
+{
+	return (void __iomem *)addr;
+}
+#define __io(a)         __io(a)
+#define __mem_pci(a)    (a)
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
new file mode 100644
index 0000000..1741f7d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -0,0 +1,203 @@
+/*
+ * arch/arm/mach-tegra/include/mach/iomap.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IOMAP_H
+#define __MACH_TEGRA_IOMAP_H
+
+#include <asm/sizes.h>
+
+#define TEGRA_ARM_PERIF_BASE		0x50040000
+#define TEGRA_ARM_PERIF_SIZE		SZ_8K
+
+#define TEGRA_ARM_INT_DIST_BASE		0x50041000
+#define TEGRA_ARM_INT_DIST_SIZE		SZ_4K
+
+#define TEGRA_DISPLAY_BASE		0x54200000
+#define TEGRA_DISPLAY_SIZE		SZ_256K
+
+#define TEGRA_DISPLAY2_BASE		0x54240000
+#define TEGRA_DISPLAY2_SIZE		SZ_256K
+
+#define TEGRA_PRIMARY_ICTLR_BASE	0x60004000
+#define TEGRA_PRIMARY_ICTLR_SIZE	SZ_64
+
+#define TEGRA_SECONDARY_ICTLR_BASE	0x60004100
+#define TEGRA_SECONDARY_ICTLR_SIZE	SZ_64
+
+#define TEGRA_TERTIARY_ICTLR_BASE	0x60004200
+#define TEGRA_TERTIARY_ICTLR_SIZE	SZ_64
+
+#define TEGRA_QUATERNARY_ICTLR_BASE	0x60004300
+#define TEGRA_QUATERNARY_ICTLR_SIZE	SZ_64
+
+#define TEGRA_TMR1_BASE			0x60005000
+#define TEGRA_TMR1_SIZE			SZ_8
+
+#define TEGRA_TMR2_BASE			0x60005008
+#define TEGRA_TMR2_SIZE			SZ_8
+
+#define TEGRA_TMRUS_BASE		0x60005010
+#define TEGRA_TMRUS_SIZE		SZ_64
+
+#define TEGRA_TMR3_BASE			0x60005050
+#define TEGRA_TMR3_SIZE			SZ_8
+
+#define TEGRA_TMR4_BASE			0x60005058
+#define TEGRA_TMR4_SIZE			SZ_8
+
+#define TEGRA_CLK_RESET_BASE		0x60006000
+#define TEGRA_CLK_RESET_SIZE		SZ_4K
+
+#define TEGRA_FLOW_CTRL_BASE		0x60007000
+#define TEGRA_FLOW_CTRL_SIZE		20
+
+#define TEGRA_STATMON_BASE		0x6000C4000
+#define TEGRA_STATMON_SIZE		SZ_1K
+
+#define TEGRA_GPIO_BASE			0x6000D000
+#define TEGRA_GPIO_SIZE			SZ_4K
+
+#define TEGRA_EXCEPTION_VECTORS_BASE    0x6000F000
+#define TEGRA_EXCEPTION_VECTORS_SIZE    SZ_4K
+
+#define TEGRA_APB_MISC_BASE		0x70000000
+#define TEGRA_APB_MISC_SIZE		SZ_4K
+
+#define TEGRA_AC97_BASE			0x70002000
+#define TEGRA_AC97_SIZE			SZ_512
+
+#define TEGRA_SPDIF_BASE		0x70002400
+#define TEGRA_SPDIF_SIZE		SZ_512
+
+#define TEGRA_I2S1_BASE			0x70002800
+#define TEGRA_I2S1_SIZE			SZ_256
+
+#define TEGRA_I2S2_BASE			0x70002A00
+#define TEGRA_I2S2_SIZE			SZ_256
+
+#define TEGRA_UARTA_BASE		0x70006000
+#define TEGRA_UARTA_SIZE		SZ_64
+
+#define TEGRA_UARTB_BASE		0x70006040
+#define TEGRA_UARTB_SIZE		SZ_64
+
+#define TEGRA_UARTC_BASE		0x70006200
+#define TEGRA_UARTC_SIZE		SZ_256
+
+#define TEGRA_UARTD_BASE		0x70006300
+#define TEGRA_UARTD_SIZE		SZ_256
+
+#define TEGRA_UARTE_BASE		0x70006400
+#define TEGRA_UARTE_SIZE		SZ_256
+
+#define TEGRA_NAND_BASE			0x70008000
+#define TEGRA_NAND_SIZE			SZ_256
+
+#define TEGRA_HSMMC_BASE		0x70008500
+#define TEGRA_HSMMC_SIZE		SZ_256
+
+#define TEGRA_SNOR_BASE			0x70009000
+#define TEGRA_SNOR_SIZE			SZ_4K
+
+#define TEGRA_PWFM_BASE			0x7000A000
+#define TEGRA_PWFM_SIZE			SZ_256
+
+#define TEGRA_MIPI_BASE			0x7000B000
+#define TEGRA_MIPI_SIZE			SZ_256
+
+#define TEGRA_I2C_BASE			0x7000C000
+#define TEGRA_I2C_SIZE			SZ_256
+
+#define TEGRA_TWC_BASE			0x7000C100
+#define TEGRA_TWC_SIZE			SZ_256
+
+#define TEGRA_SPI_BASE			0x7000C380
+#define TEGRA_SPI_SIZE			48
+
+#define TEGRA_I2C2_BASE			0x7000C400
+#define TEGRA_I2C2_SIZE			SZ_256
+
+#define TEGRA_I2C3_BASE			0x7000C500
+#define TEGRA_I2C3_SIZE			SZ_256
+
+#define TEGRA_OWR_BASE			0x7000D000
+#define TEGRA_OWR_SIZE			80
+
+#define TEGRA_DVC_BASE			0x7000D000
+#define TEGRA_DVC_SIZE			SZ_512
+
+#define TEGRA_SPI1_BASE			0x7000D400
+#define TEGRA_SPI1_SIZE			SZ_512
+
+#define TEGRA_SPI2_BASE			0x7000D600
+#define TEGRA_SPI2_SIZE			SZ_512
+
+#define TEGRA_SPI3_BASE			0x7000D800
+#define TEGRA_SPI3_SIZE			SZ_512
+
+#define TEGRA_SPI4_BASE			0x7000DA00
+#define TEGRA_SPI4_SIZE			SZ_512
+
+#define TEGRA_RTC_BASE			0x7000E000
+#define TEGRA_RTC_SIZE			SZ_256
+
+#define TEGRA_KBC_BASE			0x7000E200
+#define TEGRA_KBC_SIZE			SZ_256
+
+#define TEGRA_PMC_BASE			0x7000E400
+#define TEGRA_PMC_SIZE			SZ_256
+
+#define TEGRA_MC_BASE			0x7000F000
+#define TEGRA_MC_SIZE			SZ_1K
+
+#define TEGRA_EMC_BASE			0x7000F400
+#define TEGRA_EMC_SIZE			SZ_1K
+
+#define TEGRA_FUSE_BASE			0x7000F800
+#define TEGRA_FUSE_SIZE			SZ_1K
+
+#define TEGRA_KFUSE_BASE		0x7000FC00
+#define TEGRA_KFUSE_SIZE		SZ_1K
+
+#define TEGRA_CSITE_BASE		0x70040000
+#define TEGRA_CSITE_SIZE		SZ_256K
+
+#define TEGRA_USB_BASE			0xC5000000
+#define TEGRA_USB_SIZE			SZ_16K
+
+#define TEGRA_USB1_BASE			0xC5004000
+#define TEGRA_USB1_SIZE			SZ_16K
+
+#define TEGRA_USB2_BASE			0xC5008000
+#define TEGRA_USB2_SIZE			SZ_16K
+
+#define TEGRA_SDMMC1_BASE		0xC8000000
+#define TEGRA_SDMMC1_SIZE		SZ_512
+
+#define TEGRA_SDMMC2_BASE		0xC8000200
+#define TEGRA_SDMMC2_SIZE		SZ_512
+
+#define TEGRA_SDMMC3_BASE		0xC8000400
+#define TEGRA_SDMMC3_SIZE		SZ_512
+
+#define TEGRA_SDMMC4_BASE		0xC8000600
+#define TEGRA_SDMMC4_SIZE		SZ_512
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h
new file mode 100644
index 0000000..6151bab
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/memory.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-tegra/include/mach/memory.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_MEMORY_H
+#define __MACH_TEGRA_MEMORY_H
+
+/* physical offset of RAM */
+#define PHYS_OFFSET		UL(0)
+
+#endif
+
diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/include/mach/system.h
new file mode 100644
index 0000000..84d5d46
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/system.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-tegra/include/mach/system.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_SYSTEM_H
+#define __MACH_TEGRA_SYSTEM_H
+
+#include <mach/hardware.h>
+#include <mach/iomap.h>
+
+static inline void arch_idle(void)
+{
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+	void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
+	u32 reg = readl(reset);
+	reg |= 0x04;
+	writel(reg, reset);
+}
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/timex.h b/arch/arm/mach-tegra/include/mach/timex.h
new file mode 100644
index 0000000..a44ccbd
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/timex.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-tegra/include/mach/timex.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_TIMEX_H
+#define __MACH_TEGRA_TIMEX_H
+
+#define CLOCK_TICK_RATE		1000000
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
new file mode 100644
index 0000000..6c4dd81
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/mach-tegra/include/mach/uncompress.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_UNCOMPRESS_H
+#define __MACH_TEGRA_UNCOMPRESS_H
+
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+
+#include <mach/iomap.h>
+
+#if defined(CONFIG_TEGRA_DEBUG_UARTA)
+#define DEBUG_UART_BASE TEGRA_UARTA_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
+#define DEBUG_UART_BASE TEGRA_UARTB_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
+#define DEBUG_UART_BASE TEGRA_UARTC_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
+#define DEBUG_UART_BASE TEGRA_UARTD_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
+#define DEBUG_UART_BASE TEGRA_UARTE_BASE
+#else
+#define DEBUG_UART_BASE NULL
+#endif
+
+static void putc(int c)
+{
+	volatile u8 *uart = (volatile u8 *)DEBUG_UART_BASE;
+	int shift = 2;
+
+	if (uart == NULL)
+		return;
+
+	while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
+		barrier();
+	uart[UART_TX << shift] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+static inline void arch_decomp_setup(void)
+{
+	volatile u8 *uart = (volatile u8 *)DEBUG_UART_BASE;
+	int shift = 2;
+
+	if (uart == NULL)
+		return;
+
+	uart[UART_LCR << shift] |= UART_LCR_DLAB;
+	uart[UART_DLL << shift] = 0x75;
+	uart[UART_DLM << shift] = 0x0;
+	uart[UART_LCR << shift] = 3;
+}
+
+static inline void arch_decomp_wdog(void)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
new file mode 100644
index 0000000..267a141
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/vmalloc.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-tegra/include/mach/vmalloc.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_VMALLOC_H
+#define __MACH_TEGRA_VMALLOC_H
+
+#include <asm/sizes.h>
+
+#define VMALLOC_END        0xFE000000
+
+#endif
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
new file mode 100644
index 0000000..9fe2c5c
--- /dev/null
+++ b/arch/arm/mach-tegra/io.c
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/mach-tegra/io.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+
+#include "board.h"
+
+static struct map_desc tegra_io_desc[] __initdata = {
+	{
+		.virtual = IO_PPSB_VIRT,
+		.pfn = __phys_to_pfn(IO_PPSB_PHYS),
+		.length = IO_PPSB_SIZE,
+		.type = MT_DEVICE,
+	},
+	{
+		.virtual = IO_APB_VIRT,
+		.pfn = __phys_to_pfn(IO_APB_PHYS),
+		.length = IO_APB_SIZE,
+		.type = MT_DEVICE,
+	},
+	{
+		.virtual = IO_CPU_VIRT,
+		.pfn = __phys_to_pfn(IO_CPU_PHYS),
+		.length = IO_CPU_SIZE,
+		.type = MT_DEVICE,
+	},
+};
+
+void __init tegra_map_common_io(void)
+{
+	iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
+}
+
+/*
+ * Intercept ioremap() requests for addresses in our fixed mapping regions.
+ */
+void __iomem *tegra_ioremap(unsigned long p, size_t size, unsigned int type)
+{
+	void __iomem *v = IO_ADDRESS(p);
+	if (v == NULL)
+		v = __arm_ioremap(p, size, type);
+	return v;
+}
+EXPORT_SYMBOL(tegra_ioremap);
+
+void tegra_iounmap(volatile void __iomem *addr)
+{
+	unsigned long virt = (unsigned long)addr;
+
+	if (virt >= VMALLOC_START && virt < VMALLOC_END)
+		__iounmap(addr);
+}
+EXPORT_SYMBOL(tegra_iounmap);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 5bd7c89..b4f6c5e 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -760,7 +760,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
 	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
+		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4 || ARCH_TEGRA
 	default y
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC
-- 
1.5.6.5



From olof at lixom.net  Fri Jun  4 03:10:40 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri,  4 Jun 2010 02:10:40 -0500
Subject: [PATCH 08/10] [ARM] tegra: harmony: Add harmony board file
In-Reply-To: <1275635441-17378-8-git-send-email-olof@lixom.net>
References: <3478yvr76gerav> <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
	<1275635441-17378-3-git-send-email-olof@lixom.net>
	<1275635441-17378-4-git-send-email-olof@lixom.net>
	<1275635441-17378-5-git-send-email-olof@lixom.net>
	<1275635441-17378-6-git-send-email-olof@lixom.net>
	<1275635441-17378-7-git-send-email-olof@lixom.net>
	<1275635441-17378-8-git-send-email-olof@lixom.net>
Message-ID: <1275635441-17378-9-git-send-email-olof@lixom.net>

From: Colin Cross <ccross at android.com>

v2: fixes from Russell King
	- include linux/io.h instead of mach/io.h

Olof:
	- Removed board-harmony-panel, will be merged with the FB driver.
	- Minor cleanups

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Erik Gilling <konkers at android.com>
Signed-off-by: Olof Johansson <olof at lixom.net>

remove panel file
---
 arch/arm/mach-tegra/Makefile               |    3 +
 arch/arm/mach-tegra/board-harmony-pinmux.c |  144 ++++++++++++++++++++++++++++
 arch/arm/mach-tegra/board-harmony.c        |  129 +++++++++++++++++++++++++
 arch/arm/mach-tegra/board-harmony.h        |   22 ++++
 4 files changed, 298 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/board-harmony-pinmux.c
 create mode 100644 arch/arm/mach-tegra/board-harmony.c
 create mode 100644 arch/arm/mach-tegra/board-harmony.h

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 5e47a71..51e9370 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -9,3 +9,6 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
+
+obj-${CONFIG_MACH_HARMONY}              += board-harmony.o
+obj-${CONFIG_MACH_HARMONY}              += board-harmony-pinmux.o
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
new file mode 100644
index 0000000..50b15d5
--- /dev/null
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -0,0 +1,144 @@
+/*
+ * arch/arm/mach-tegra/board-harmony-pinmux.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <mach/pinmux.h>
+
+#include "board-harmony.h"
+
+static struct tegra_pingroup_config harmony_pinmux[] = {
+	{TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DDC,   TEGRA_MUX_I2C2,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_DTA,   TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DTB,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DTC,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DTD,   TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DTE,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GMC,   TEGRA_MUX_UARTD,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GMD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GPU,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LCSN,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LDC,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LM0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LM1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LPW0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LPW1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LPW2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LSC1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSCK,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSDA,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSDI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LVP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+};
+
+void harmony_pinmux_init(void)
+{
+	tegra_pinmux_config_table(harmony_pinmux, ARRAY_SIZE(harmony_pinmux));
+}
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
new file mode 100644
index 0000000..5e3bb7d
--- /dev/null
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -0,0 +1,129 @@
+/*
+ * arch/arm/mach-tegra/board-harmony.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/pda_power.h>
+#include <linux/io.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/setup.h>
+
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+
+#include "board.h"
+#include "board-harmony.h"
+
+/* NVidia bootloader tags */
+#define ATAG_NVIDIA		0x41000801
+
+#define ATAG_NVIDIA_RM			0x1
+#define ATAG_NVIDIA_DISPLAY		0x2
+#define ATAG_NVIDIA_FRAMEBUFFER		0x3
+#define ATAG_NVIDIA_CHIPSHMOO		0x4
+#define ATAG_NVIDIA_CHIPSHMOOPHYS	0x5
+#define ATAG_NVIDIA_PRESERVED_MEM_0	0x10000
+#define ATAG_NVIDIA_PRESERVED_MEM_N	2
+#define ATAG_NVIDIA_FORCE_32		0x7fffffff
+
+struct tag_tegra {
+	__u32 bootarg_key;
+	__u32 bootarg_len;
+	char bootarg[1];
+};
+
+static int __init parse_tag_nvidia(const struct tag *tag)
+{
+
+	return 0;
+}
+__tagtable(ATAG_NVIDIA, parse_tag_nvidia);
+
+static struct plat_serial8250_port debug_uart_platform_data[] = {
+	{
+		.membase	= IO_ADDRESS(TEGRA_UARTD_BASE),
+		.mapbase	= TEGRA_UARTD_BASE,
+		.irq		= INT_UARTD,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= 216000000/16 * 16,
+	}, {
+		.flags		= 0
+	}
+};
+
+static struct platform_device debug_uart = {
+	.name = "serial8250",
+	.id = PLAT8250_DEV_PLATFORM,
+	.dev = {
+		.platform_data = debug_uart_platform_data,
+	},
+};
+
+static struct platform_device *harmony_devices[] __initdata = {
+	&debug_uart,
+};
+
+static void __init tegra_harmony_fixup(struct machine_desc *desc,
+				       struct tag *tags,
+				       char **cmdline, struct meminfo *mi)
+{
+	mi->nr_banks = 2;
+	mi->bank[0].start = PHYS_OFFSET;
+	mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
+	mi->bank[0].size = 448 * SZ_1M;
+	mi->bank[1].start = SZ_512M;
+	mi->bank[1].node = PHYS_TO_NID(SZ_512M);
+	mi->bank[1].size = SZ_512M;
+}
+
+static void __init tegra_harmony_init(void)
+{
+	struct clk *clk;
+
+	tegra_common_init();
+
+	clk = clk_get_sys(NULL, "pll_p");
+	clk_enable(clk);
+	clk_set_rate(clk, 216000000);
+
+	clk = clk_get_sys("uart.3", NULL);
+	clk_set_rate(clk, 216000000);
+	clk_enable(clk);
+
+	harmony_pinmux_init();
+
+	platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
+}
+
+MACHINE_START(TEGRA_HARMONY, "tegra_harmony")
+	.boot_params  = 0x00000100,
+	.phys_io        = IO_APB_PHYS,
+	.io_pg_offst    = ((IO_APB_VIRT) >> 18) & 0xfffc,
+	.fixup		= tegra_harmony_fixup,
+	.init_irq       = tegra_init_irq,
+	.init_machine   = tegra_harmony_init,
+	.map_io         = tegra_map_common_io,
+	.timer          = &tegra_timer,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h
new file mode 100644
index 0000000..09ca775
--- /dev/null
+++ b/arch/arm/mach-tegra/board-harmony.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-tegra/board-harmony.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MACH_TEGRA_BOARD_HARMONY_H
+#define _MACH_TEGRA_BOARD_HARMONY_H
+
+void harmony_pinmux_init(void);
+
+#endif
-- 
1.5.6.5



From olof at lixom.net  Fri Jun  4 03:23:57 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri, 4 Jun 2010 02:23:57 -0500
Subject: [PATCH 10/10] [ARM] tegra: Add MAINTAINERS entry
In-Reply-To: <1275635441-17378-10-git-send-email-olof@lixom.net>
References: <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
	<1275635441-17378-3-git-send-email-olof@lixom.net>
	<1275635441-17378-4-git-send-email-olof@lixom.net>
	<1275635441-17378-5-git-send-email-olof@lixom.net>
	<1275635441-17378-6-git-send-email-olof@lixom.net>
	<1275635441-17378-7-git-send-email-olof@lixom.net>
	<1275635441-17378-8-git-send-email-olof@lixom.net>
	<1275635441-17378-9-git-send-email-olof@lixom.net>
	<1275635441-17378-10-git-send-email-olof@lixom.net>
Message-ID: <20100604072357.GA17910@lixom.net>


From olof at lixom.net  Fri Jun  4 02:51:11 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri, 4 Jun 2010 01:51:11 -0500
Subject: [PATCH 10/10] [ARM] tegra: Add MAINTAINERS entry
Message-ID: <mailman.473.1275636244.2170.linux-arm-kernel@lists.infradead.org>

Add maintainer entry for tegra support.

Signed-off-by: Olof Johansson <olof at lixom.net>

---
 MAINTAINERS |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index d329b05..e052077 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5396,6 +5396,13 @@ W:	http://tcp-lp-mod.sourceforge.net/
 S:	Maintained
 F:	net/ipv4/tcp_lp.c
 
+TEGRA PLATFORM SUPPORT
+M:	Olof Johansson <olof at lixom.net>
+L:	linux-tegra at vger.kernel.org
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
+S:	Supported
+F:	arch/arm/mach-tegra/
+
 TEHUTI ETHERNET DRIVER
 M:	Alexander Indenbaum <baum at tehutinetworks.net>
 M:	Andy Gospodarek <andy at greyhouse.net>
-- 
1.5.6.5



From maramaopercheseimorto at gmail.com  Fri Jun  4 03:29:43 2010
From: maramaopercheseimorto at gmail.com (Alberto Panizzo)
Date: Fri, 04 Jun 2010 09:29:43 +0200
Subject: [PATCH 2/2] backlight: Fix blanking for L4F00242T03 LCD
In-Reply-To: <1275630748-10722-2-git-send-email-marek.vasut@gmail.com>
References: <1275630748-10722-1-git-send-email-marek.vasut@gmail.com>
	<1275630748-10722-2-git-send-email-marek.vasut@gmail.com>
Message-ID: <1275636583.3210.37.camel@realization>

On ven, 2010-06-04 at 07:52 +0200, Marek Vasut wrote:
> The LCD was turned on if the variable power was > 0, but that was incorrect. The
> LCD has to be turned on in every case but POWERDOWN.
> 
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Ack

> ---
>  drivers/video/backlight/l4f00242t03.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/video/backlight/l4f00242t03.c b/drivers/video/backlight/l4f00242t03.c
> index 9093ef0..ac20b2e 100644
> --- a/drivers/video/backlight/l4f00242t03.c
> +++ b/drivers/video/backlight/l4f00242t03.c
> @@ -78,7 +78,7 @@ static int l4f00242t03_lcd_power_set(struct lcd_device *ld, int power)
>  	const u16 slpin = 0x10;
>  	const u16 disoff = 0x28;
>  
> -	if (power) {
> +	if (power < FB_BLANK_POWERDOWN) {
>  		if (priv->lcd_on)
>  			return 0;
>  

lcd.h states:
struct lcd_ops {
	/* Get the LCD panel power status (0: full on, 1..3: controller
	   power on, flat panel power off, 4: full off), see FB_BLANK_XXX */
	int (*get_power)(struct lcd_device *);
	/* Enable or disable power to the LCD (0: on; 4: off, see FB_BLANK_XXX) */
	int (*set_power)(struct lcd_device *, int power);

AFAIK the gray area between FB_BLANK_NORMAL and FB_BLANK_HSYNC_SUSPEND
can be chosen as needs.

Why not:

+ #define POWER_IS_ON(pwr)	((pwr) <= FB_BLANK_NORMAL)

...

-	if (power) {
+	if (POWER_IS_ON(power)) {
 		if (priv->lcd_on)
 			return 0;

So with FB_BLANK_NORMAL the lcd is active and on -> low latencies
in re-enabling the video out, but for !POWER_IS_ON(power) we will send  
the lcd to standby.

It have to be implemented for power == FB_BLANK_POWERDOWN to turn off the 
regulators of the lcd.

What do you think about?

Regards,

-- 
Alberto!

        Be Persistent!
                - Greg Kroah-Hartman (FOSDEM 2010)



From jeremy.kerr at canonical.com  Fri Jun  4 03:30:08 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Fri, 04 Jun 2010 15:30:08 +0800
Subject: [RFC,PATCH 0/2] Common struct clk implementation, v4
Message-ID: <1275636608.606606.450179637764.0.gpush@pororo>

Hi all,

These patches are an attempt to allow platforms to share clock code. At
present, the definitions of 'struct clk' are local to platform code,
which makes allocating and initialising cross-platform clock sources
difficult, and makes it impossible to compile a single image containing
support for two ARM platforms with different struct clks.

The two patches are for the architecture-independent kernel code,
introducing the common clk infrastructure. The changelog for the first
patch includes details about the new clock definitions.

As requested by rmk, I've put together a small series of patches
illustrating the usage of the common struct clock on the ARM imx51
platform. These are available in my git tree:

 git://kernel.ubuntu.com/jk/dt/linux-2.6

in the clk-common-mx51 branch (clk-common..clk-common-mx51).

The approach I've taken with the imx51 port is to temporarly duplicate
the platform-common clock code (ie, for all mxc-based boards) to enable
usage of the common struct clk on one machine (imx51), while leaving the
others as-is. For a proper platform-wide usage of the common struct clk,
we'd be better off doing the whole platform at once. However, mx51 is
the only mxc-based HW I have, hence the duplicated example port.

In the example port, the first change simply converts the mxc's struct
clk to a struct clk_mxc, using the new API.  The subsequent patches move
certain clocks to more specific data structures (eg clk_fixed and
clk_pll) where possible.

Ben Herrenschmidt is looking at using common struct clk code for powerpc
too, hence the kernel-wide approach.

Comments most welcome.

Cheers,


Jeremy

--
v4:
 * use mutex for enable/disable locking
 * DEFINE_CLK -> INIT_CLK, and pass the clk name for mutex init
 * struct clk_operations -> struct clk_ops

v3:
 * do clock usage refcounting in common code
 * provide sample port

v2:
 * no longer ARM-specific
 * use clk_operations

---
Jeremy Kerr (2):
      Add a common struct clk
      clk: Generic support for fixed-rate clocks



From jeremy.kerr at canonical.com  Fri Jun  4 03:30:08 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Fri, 04 Jun 2010 15:30:08 +0800
Subject: [RFC,PATCH 2/2] clk: Generic support for fixed-rate clocks
In-Reply-To: <1275636608.606606.450179637764.0.gpush@pororo>
Message-ID: <1275636608.607356.414998699566.2.gpush@pororo>

Since most platforms will need a fixed-rate clock, add one. This will
also serve as a basic example of an implementation of struct clk.

Signed-off-by: Jeremy Kerr <jeremy.kerr at canonical.com>

---
 include/linux/clk.h |   13 +++++++++++++
 kernel/Makefile     |    1 +
 kernel/clk.c        |   25 +++++++++++++++++++++++++
 3 files changed, 39 insertions(+)

diff --git a/include/linux/clk.h b/include/linux/clk.h
index bb6957a..6269b44 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -123,6 +123,19 @@ static inline struct clk *clk_get_parent(struct clk *clk)
 	return ERR_PTR(-ENOSYS);
 }
 
+/* Simple fixed-rate clock */
+struct clk_fixed {
+	struct clk	clk;
+	unsigned long	rate;
+};
+
+extern struct clk_ops clk_fixed_ops;
+
+#define INIT_CLK_FIXED(name, r) { \
+	.clk = INIT_CLK(name.clk, clk_fixed_ops), \
+	.rate = (r) \
+}
+
 #else /* !CONFIG_USE_COMMON_STRUCT_CLK */
 
 /*
diff --git a/kernel/Makefile b/kernel/Makefile
index 057472f..1ae15aa 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -105,6 +105,7 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o
 obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
 obj-$(CONFIG_USER_RETURN_NOTIFIER) += user-return-notifier.o
 obj-$(CONFIG_PADATA) += padata.o
+obj-$(CONFIG_USE_COMMON_STRUCT_CLK) += clk.o
 
 ifneq ($(CONFIG_SCHED_OMIT_FRAME_POINTER),y)
 # According to Alan Modra <alan at linuxcare.com.au>, the -fno-omit-frame-pointer is
diff --git a/kernel/clk.c b/kernel/clk.c
new file mode 100644
index 0000000..85c0670
--- /dev/null
+++ b/kernel/clk.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2010 Canonical Ltd <jeremy.kerr at canonical.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Standard functionality for the common clock API.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+
+#define to_clk_fixed(clk) (container_of(clk, struct clk_fixed, clk))
+
+static unsigned long clk_fixed_get_rate(struct clk *clk)
+{
+	return to_clk_fixed(clk)->rate;
+}
+
+struct clk_ops clk_fixed_ops = {
+	.get_rate = clk_fixed_get_rate,
+};
+
+EXPORT_SYMBOL_GPL(clk_fixed_ops);


From jeremy.kerr at canonical.com  Fri Jun  4 03:30:08 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Fri, 04 Jun 2010 15:30:08 +0800
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <1275636608.606606.450179637764.0.gpush@pororo>
Message-ID: <1275636608.607067.417709988883.1.gpush@pororo>

We currently have 21 definitions of struct clk in the ARM architecture,
each defined on a per-platform basis. This makes it difficult to define
platform- (or architecture-) independent clock sources without making
assumptions about struct clk, and impossible to compile two
platforms with different struct clks into a single image.

This change is an effort to unify struct clk where possible, by defining
a common struct clk, containing a set of clock operations. Different
clock implementations can set their own operations, and have a standard
interface for generic code. The callback interface is exposed to the
kernel proper, while the clock implementations only need to be seen by
the platform internals.

This allows us to share clock code among platforms, and makes it
possible to dynamically create clock devices in platform-independent
code.

Platforms can enable the generic struct clock through
CONFIG_USE_COMMON_STRUCT_CLK. In this case, the clock infrastructure
consists of a common struct clk:

struct clk {
	const struct clk_ops	*ops;
	unsigned int		enable_count;
	struct mutex		mutex;
};

And a set of clock operations (defined per type of clock):

struct clk_operations {
       int             (*enable)(struct clk *);
       void            (*disable)(struct clk *);
       unsigned long   (*get_rate)(struct clk *);
       [...]
};

To define a hardware-specific clock, machine code can "subclass" the
struct clock into a new struct (adding any device-specific data), and
provide a set of operations:

struct clk_foo {
	struct clk	clk;
	void __iomem	*some_register;
};

struct clk_operations clk_foo_ops = {
	.get_rate = clk_foo_get_rate,
};

The common clock definitions are based on a development patch from Ben
Herrenschmidt <benh at kernel.crashing.org>.

Signed-off-by: Jeremy Kerr <jeremy.kerr at canonical.com>

---
 arch/Kconfig        |    3 
 include/linux/clk.h |  159 ++++++++++++++++++++++++++++++++++++--------
 2 files changed, 135 insertions(+), 27 deletions(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index acda512..2458b5e 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -151,4 +151,7 @@ config HAVE_MIXED_BREAKPOINTS_REGS
 config HAVE_USER_RETURN_NOTIFIER
 	bool
 
+config USE_COMMON_STRUCT_CLK
+	bool
+
 source "kernel/gcov/Kconfig"
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 1d37f42..bb6957a 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -3,6 +3,7 @@
  *
  *  Copyright (C) 2004 ARM Limited.
  *  Written by Deep Blue Solutions Limited.
+ *  Copyright (c) 2010 Jeremy Kerr <jeremy.kerr at canonical.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -11,36 +12,125 @@
 #ifndef __LINUX_CLK_H
 #define __LINUX_CLK_H
 
-struct device;
+#include <linux/err.h>
+#include <linux/mutex.h>
 
-/*
- * The base API.
+#ifdef CONFIG_USE_COMMON_STRUCT_CLK
+
+/* If we're using the common struct clk, we define the base clk object here,
+ * which will be 'subclassed' by device-specific implementations. For example:
+ *
+ *  struct clk_foo {
+ *      struct clk;
+ *      [device specific fields]
+ *  };
+ *
+ * We define the common clock API through a set of static inlines that call the
+ * corresponding clk_operations. The API is exactly the same as that documented
+ * in the !CONFIG_USE_COMMON_STRUCT_CLK case.
  */
 
+struct clk {
+	const struct clk_ops	*ops;
+	unsigned int		enable_count;
+	struct mutex		mutex;
+};
+
+#define INIT_CLK(name, o) \
+	{ .ops = &o, .enable_count = 0, \
+		.mutex = __MUTEX_INITIALIZER(name.mutex) }
+
+struct clk_ops {
+       int             (*enable)(struct clk *);
+       void            (*disable)(struct clk *);
+       unsigned long   (*get_rate)(struct clk *);
+       void            (*put)(struct clk *);
+       long            (*round_rate)(struct clk *, unsigned long);
+       int             (*set_rate)(struct clk *, unsigned long);
+       int             (*set_parent)(struct clk *, struct clk *);
+       struct clk*     (*get_parent)(struct clk *);
+};
+
+static inline int clk_enable(struct clk *clk)
+{
+	int ret = 0;
+
+	if (!clk->ops->enable)
+		return 0;
+
+	mutex_lock(&clk->mutex);
+	if (!clk->enable_count)
+		ret = clk->ops->enable(clk);
+
+	if (!ret)
+		clk->enable_count++;
+	mutex_unlock(&clk->mutex);
+
+	return ret;
+}
+
+static inline void clk_disable(struct clk *clk)
+{
+	if (!clk->ops->enable)
+		return;
+
+	mutex_lock(&clk->mutex);
+
+	if (!--clk->enable_count)
+		clk->ops->disable(clk);
+
+	mutex_unlock(&clk->mutex);
+}
+
+static inline unsigned long clk_get_rate(struct clk *clk)
+{
+	if (clk->ops->get_rate)
+		return clk->ops->get_rate(clk);
+	return 0;
+}
+
+static inline void clk_put(struct clk *clk)
+{
+	if (clk->ops->put)
+		clk->ops->put(clk);
+}
+
+static inline long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	if (clk->ops->round_rate)
+		return clk->ops->round_rate(clk, rate);
+	return -ENOSYS;
+}
+
+static inline int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	if (clk->ops->set_rate)
+		return clk->ops->set_rate(clk, rate);
+	return -ENOSYS;
+}
+
+static inline int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	if (clk->ops->set_parent)
+		return clk->ops->set_parent(clk, parent);
+	return -ENOSYS;
+}
+
+static inline struct clk *clk_get_parent(struct clk *clk)
+{
+	if (clk->ops->get_parent)
+		return clk->ops->get_parent(clk);
+	return ERR_PTR(-ENOSYS);
+}
+
+#else /* !CONFIG_USE_COMMON_STRUCT_CLK */
 
 /*
- * struct clk - an machine class defined object / cookie.
+ * Global clock object, actual structure is declared per-machine
  */
 struct clk;
 
 /**
- * clk_get - lookup and obtain a reference to a clock producer.
- * @dev: device for clock "consumer"
- * @id: clock comsumer ID
- *
- * Returns a struct clk corresponding to the clock producer, or
- * valid IS_ERR() condition containing errno.  The implementation
- * uses @dev and @id to determine the clock consumer, and thereby
- * the clock producer.  (IOW, @id may be identical strings, but
- * clk_get may return different clock producers depending on @dev.)
- *
- * Drivers must assume that the clock source is not enabled.
- *
- * clk_get should not be called from within interrupt context.
- */
-struct clk *clk_get(struct device *dev, const char *id);
-
-/**
  * clk_enable - inform the system when the clock source should be running.
  * @clk: clock source
  *
@@ -83,12 +173,6 @@ unsigned long clk_get_rate(struct clk *clk);
  */
 void clk_put(struct clk *clk);
 
-
-/*
- * The remaining APIs are optional for machine class support.
- */
-
-
 /**
  * clk_round_rate - adjust a rate to the exact rate a clock can provide
  * @clk: clock source
@@ -125,6 +209,27 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
  */
 struct clk *clk_get_parent(struct clk *clk);
 
+#endif /* !CONFIG_USE_COMMON_STRUCT_CLK */
+
+struct device;
+
+/**
+ * clk_get - lookup and obtain a reference to a clock producer.
+ * @dev: device for clock "consumer"
+ * @id: clock comsumer ID
+ *
+ * Returns a struct clk corresponding to the clock producer, or
+ * valid IS_ERR() condition containing errno.  The implementation
+ * uses @dev and @id to determine the clock consumer, and thereby
+ * the clock producer.  (IOW, @id may be identical strings, but
+ * clk_get may return different clock producers depending on @dev.)
+ *
+ * Drivers must assume that the clock source is not enabled.
+ *
+ * clk_get should not be called from within interrupt context.
+ */
+struct clk *clk_get(struct device *dev, const char *id);
+
 /**
  * clk_get_sys - get a clock based upon the device name
  * @dev_id: device name


From r.schwebel at pengutronix.de  Fri Jun  4 03:31:30 2010
From: r.schwebel at pengutronix.de (Robert Schwebel)
Date: Fri, 4 Jun 2010 09:31:30 +0200
Subject: Please pull mxc patches for -rc
In-Reply-To: <20100603195239.GB9169@n2100.arm.linux.org.uk>
References: <20100603083522.GX26820@pengutronix.de>
	<20100603195239.GB9169@n2100.arm.linux.org.uk>
Message-ID: <20100604073130.GL13374@pengutronix.de>

On Thu, Jun 03, 2010 at 08:52:39PM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 03, 2010 at 10:35:22AM +0200, Sascha Hauer wrote:
> > Hi Russell,
> >
> > please pull the following for -rc.
>
> I won't be pulling this for a while; I've no idea at the moment where
> ARM as a community goes from where we find ourselves as of this morning
> given Linus' complaints about our "pointless churn".

Hmm, it would be great to get at least the functional patches in
somehow; almost all of the i.MX platforms compile-fail in our
autobuilder for days now because of the ULPI problem.

But as it's only rc1 time yet, there's probably some time to get things
sorted out.

rsc
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From eric.y.miao at gmail.com  Fri Jun  4 03:37:28 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 4 Jun 2010 15:37:28 +0800
Subject: Is it possible to fix the warning when including wm97xx_batt.h?
Message-ID: <AANLkTikX80CrjDVsJfdthnwoPsnXz15mIrr69afZg3af@mail.gmail.com>

Hi Marek,

Regard the annoying warnings below, is it currently possible not to include
wm97xx_batt.h and include wm97xx.h instead?

In file included from
/home/ycmiao/kernel/linux-2.6/arch/arm/mach-pxa/palmte2.c:26:
/home/ycmiao/kernel/linux-2.6/include/linux/wm97xx_batt.h:6: warning:
#warning This file will be removed soon, use wm97xx.h instead!
  CC      arch/arm/mach-pxa/palmtc.o
  CC      kernel/sysctl.o
  CC      arch/arm/mach-pxa/palmt5.o
In file included from
/home/ycmiao/kernel/linux-2.6/arch/arm/mach-pxa/palmt5.c:27:
/home/ycmiao/kernel/linux-2.6/include/linux/wm97xx_batt.h:6: warning:
#warning This file will be removed soon, use wm97xx.h instead!
  CC      arch/arm/mach-pxa/palmtx.o
In file included from
/home/ycmiao/kernel/linux-2.6/arch/arm/mach-pxa/palmtx.c:28:
/home/ycmiao/kernel/linux-2.6/include/linux/wm97xx_batt.h:6: warning:
#warning This file will be removed soon, use wm97xx.h instead!
  CC      arch/arm/mach-pxa/palmz72.o
In file included from
/home/ycmiao/kernel/linux-2.6/arch/arm/mach-pxa/palmz72.c:30:
/home/ycmiao/kernel/linux-2.6/include/linux/wm97xx_batt.h:6: warning:
#warning This file will be removed soon, use wm97xx.h instead!
  CC      kernel/sysctl_binary.o
  CC      arch/arm/mach-pxa/palmld.o
In file included from
/home/ycmiao/kernel/linux-2.6/arch/arm/mach-pxa/palmld.c:25:
/home/ycmiao/kernel/linux-2.6/include/linux/wm97xx_batt.h:6: warning:
#warning This file will be removed soon, use wm97xx.h instead!
  CC      arch/arm/mach-pxa/palmtreo.o
  CC      kernel/capability.o
In file included from
/home/ycmiao/kernel/linux-2.6/arch/arm/mach-pxa/palmtreo.c:26:
/home/ycmiao/kernel/linux-2.6/include/linux/wm97xx_batt.h:6: warning:
#warning This file will be removed soon, use wm97xx.h instead!


From eric.y.miao at gmail.com  Fri Jun  4 03:39:25 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 4 Jun 2010 15:39:25 +0800
Subject: Is it possible to fix the warning when including wm97xx_batt.h?
In-Reply-To: <AANLkTikX80CrjDVsJfdthnwoPsnXz15mIrr69afZg3af@mail.gmail.com>
References: <AANLkTikX80CrjDVsJfdthnwoPsnXz15mIrr69afZg3af@mail.gmail.com>
Message-ID: <AANLkTin1BqWBs7XrBcqmCx8Fg0dOz93C_aBWrtz3DV6L@mail.gmail.com>

On Fri, Jun 4, 2010 at 3:37 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> Hi Marek,
>
> Regard the annoying warnings below, is it currently possible not to include
> wm97xx_batt.h and include wm97xx.h instead?
>

Ignore this mail, I just found your patch for this issue. Sorry.


From eric.miao at canonical.com  Fri Jun  4 03:51:14 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Fri, 4 Jun 2010 15:51:14 +0800
Subject: [PATCH RFC] Make ISA_DMA_THRESHOLD and MAX_DMA_ADDRESS variables
Message-ID: <AANLkTinOh3iHS4JnKBYiQedufAdVEfJ5R_vSmntA4gJa@mail.gmail.com>

commit 969bc4d4aa226f4d44aa5f5f87b37c75972a9020
Author: Eric Miao <eric.y.miao at gmail.com>
Date:   Thu Jun 3 22:58:20 2010 +0800

    [ARM] Make ISA_DMA_THRESHOLD and MAX_DMA_ADDRESS variables

    This differs between SoCs and can be made as variables by encoding the
    DMA-able size into machine_desc, and initializing early.

    Signed-off-by: Eric Miao <eric.miao at canonical.com>

diff --git a/arch/arm/include/asm/dma-mapping.h
b/arch/arm/include/asm/dma-mapping.h
index 69ce072..9273cde 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -10,6 +10,19 @@
 #include <asm/memory.h>

 /*
+ * The DMA mask corresponding to the maximum bus address allocatable
+ * using GFP_DMA.  The default here places no restriction on DMA
+ * allocations.  This must be the smallest DMA mask in the system,
+ * so a successful GFP_DMA allocation will always satisfy this.
+ */
+extern unsigned long ISA_DMA_THRESHOLD;
+
+/*
+ * set_isa_dma_size() initializes both ISA_DMA_THRESHOLD and MAX_DMA_ADDRESS
+ */
+void __init set_isa_dma_size(unsigned long);
+
+/*
  * page_to_dma/dma_to_virt/virt_to_dma are architecture private functions
  * used internally by the DMA-mapping API to provide DMA addresses. They
  * must not be used by drivers.
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index ca51143..76e21ac 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -6,9 +6,7 @@
 /*
  * This is the maximum virtual address which can be DMA'd from.
  */
-#ifndef MAX_DMA_ADDRESS
-#define MAX_DMA_ADDRESS	0xffffffff
-#endif
+extern unsigned long MAX_DMA_ADDRESS;

 #ifdef CONFIG_ISA_DMA_API
 /*
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index c59842d..67f54c1 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -23,6 +23,7 @@ struct machine_desc {
 	unsigned int		phys_io;	/* start of physical io	*/
 	unsigned int		io_pg_offst;	/* byte offset for io
 						 * page tabe entry	*/
+	unsigned long		isa_dma_size;

 	const char		*name;		/* architecture name	*/
 	unsigned long		boot_params;	/* tagged list		*/
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index fb18aff..e7570bf 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -153,16 +153,6 @@ extern unsigned long phys_offset;
 #define PHYS_OFFSET	phys_offset
 #endif

-/*
- * The DMA mask corresponding to the maximum bus address allocatable
- * using GFP_DMA.  The default here places no restriction on DMA
- * allocations.  This must be the smallest DMA mask in the system,
- * so a successful GFP_DMA allocation will always satisfy this.
- */
-#ifndef ISA_DMA_THRESHOLD
-#define ISA_DMA_THRESHOLD	(0xffffffffULL)
-#endif
-
 #ifndef arch_adjust_zones
 #define arch_adjust_zones(node,size,holes) do { } while (0)
 #elif !defined(CONFIG_ZONE_DMA)
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index fc5ce30..660b40c 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -25,6 +25,7 @@
 #include <linux/smp.h>
 #include <linux/fs.h>
 #include <linux/proc_fs.h>
+#include <linux/dma-mapping.h>

 #include <asm/unified.h>
 #include <asm/cpu.h>
@@ -386,6 +387,9 @@ static struct machine_desc * __init
setup_machine(unsigned int nr)
 		while (1);
 	}

+	if (list->isa_dma_size)
+		set_isa_dma_size(list->isa_dma_size);
+
 	printk("Machine: %s\n", list->name);

 	return list;
diff --git a/arch/arm/mach-davinci/board-da830-evm.c
b/arch/arm/mach-davinci/board-da830-evm.c
index 212d970..5b0da02 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -570,6 +570,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci
DA830/OMAP-L137 EVM")
 	.phys_io	= IO_PHYS,
 	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params	= (DA8XX_DDR_BASE + 0x100),
+	.isa_dma_size	= SZ_128M,
 	.map_io		= da830_evm_map_io,
 	.init_irq	= cp_intc_init,
 	.timer		= &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c
b/arch/arm/mach-davinci/board-da850-evm.c
index 2ec3095..1d7430e 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -762,6 +762,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci
DA850/OMAP-L138 EVM")
 	.phys_io	= IO_PHYS,
 	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params	= (DA8XX_DDR_BASE + 0x100),
+	.isa_dma_size	= SZ_128M,
 	.map_io		= da850_evm_map_io,
 	.init_irq	= cp_intc_init,
 	.timer		= &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c
b/arch/arm/mach-davinci/board-dm355-evm.c
index a319101..5b4dbd4 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -354,6 +354,7 @@ MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (0x80000100),
+	.isa_dma_size = SZ_128M,
 	.map_io	      = dm355_evm_map_io,
 	.init_irq     = davinci_irq_init,
 	.timer	      = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c
b/arch/arm/mach-davinci/board-dm355-leopard.c
index f1d8132..4b2b632 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -273,6 +273,7 @@ MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (0x80000100),
+	.isa_dma_size = SZ_128M,
 	.map_io	      = dm355_leopard_map_io,
 	.init_irq     = davinci_irq_init,
 	.timer	      = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c
b/arch/arm/mach-davinci/board-dm365-evm.c
index 84acef1..702c9e2 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -616,6 +616,7 @@ MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
 	.phys_io	= IO_PHYS,
 	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params	= (0x80000100),
+	.isa_dma_size	= SZ_128M,
 	.map_io		= dm365_evm_map_io,
 	.init_irq	= davinci_irq_init,
 	.timer		= &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c
b/arch/arm/mach-davinci/board-dm644x-evm.c
index 34c8b41..cbfc4ee 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -709,6 +709,7 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (DAVINCI_DDR_BASE + 0x100),
+	.isa_dma_size = SZ_128M,
 	.map_io	      = davinci_evm_map_io,
 	.init_irq     = davinci_irq_init,
 	.timer	      = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c
b/arch/arm/mach-davinci/board-dm646x-evm.c
index 6d88893..252ddad 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -754,6 +754,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (0x80000100),
+	.isa_dma_size = SZ_128M,
 	.map_io       = davinci_map_io,
 	.init_irq     = davinci_irq_init,
 	.timer        = &davinci_timer,
@@ -764,6 +765,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (0x80000100),
+	.isa_dma_size = SZ_128M,
 	.map_io       = davinci_map_io,
 	.init_irq     = davinci_irq_init,
 	.timer        = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c
b/arch/arm/mach-davinci/board-neuros-osd2.c
index 4c30e92..b788927 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -278,6 +278,7 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
 	.phys_io	= IO_PHYS,
 	.io_pg_offst	= (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params	= (DAVINCI_DDR_BASE + 0x100),
+	.isa_dma_size	= SZ_128M,
 	.map_io		 = davinci_ntosd2_map_io,
 	.init_irq	= davinci_irq_init,
 	.timer		= &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-sffsdr.c
b/arch/arm/mach-davinci/board-sffsdr.c
index 23e664a..d02e0c8 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -157,6 +157,7 @@ MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
 	.phys_io      = IO_PHYS,
 	.io_pg_offst  = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
 	.boot_params  = (DAVINCI_DDR_BASE + 0x100),
+	.isa_dma_size = SZ_128M,
 	.map_io	      = davinci_sffsdr_map_io,
 	.init_irq     = davinci_irq_init,
 	.timer	      = &davinci_timer,
diff --git a/arch/arm/mach-davinci/include/mach/memory.h
b/arch/arm/mach-davinci/include/mach/memory.h
index a91edfb..e08eaf2 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -62,9 +62,6 @@ __arch_adjust_zones(int node, unsigned long *size,
unsigned long *holes)
 #define arch_adjust_zones(node, zone_size, holes) \
         if ((meminfo.bank[0].size >> 20) > 128)
__arch_adjust_zones(node, zone_size, holes)

-#define ISA_DMA_THRESHOLD	(PHYS_OFFSET + (128<<20) - 1)
-#define MAX_DMA_ADDRESS		(PAGE_OFFSET + (128<<20))
-
 #endif

 #endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c
index 78be457..abafa2b 100644
--- a/arch/arm/mach-h720x/h7201-eval.c
+++ b/arch/arm/mach-h720x/h7201-eval.c
@@ -33,6 +33,7 @@ MACHINE_START(H7201, "Hynix GMS30C7201")
 	.phys_io	= 0x80000000,
 	.io_pg_offst	= ((0xf0000000) >> 18) & 0xfffc,
 	.boot_params	= 0xc0001000,
+	.isa_dma_size	= SZ_256M,
 	.map_io		= h720x_map_io,
 	.init_irq	= h720x_init_irq,
 	.timer		= &h7201_timer,
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c
index 8c0ba99..f947b06 100644
--- a/arch/arm/mach-h720x/h7202-eval.c
+++ b/arch/arm/mach-h720x/h7202-eval.c
@@ -75,6 +75,7 @@ MACHINE_START(H7202, "Hynix HMS30C7202")
 	.phys_io	= 0x80000000,
 	.io_pg_offst	= ((0xf0000000) >> 18) & 0xfffc,
 	.boot_params	= 0x40000100,
+	.isa_dma_size	= SZ_256M,
 	.map_io		= h720x_map_io,
 	.init_irq	= h7202_init_irq,
 	.timer		= &h7202_timer,
diff --git a/arch/arm/mach-h720x/include/mach/memory.h
b/arch/arm/mach-h720x/include/mach/memory.h
index ef4c1e2..83a2fa0 100644
--- a/arch/arm/mach-h720x/include/mach/memory.h
+++ b/arch/arm/mach-h720x/include/mach/memory.h
@@ -8,12 +8,5 @@
 #define __ASM_ARCH_MEMORY_H

 #define PHYS_OFFSET	UL(0x40000000)
-/*
- * This is the maximum DMA address that can be DMAd to.
- * There should not be more than (0xd0000000 - 0xc0000000)
- * bytes of RAM.
- */
-#define ISA_DMA_THRESHOLD	(PHYS_OFFSET + SZ_256M - 1)
-#define MAX_DMA_ADDRESS		(PAGE_OFFSET + SZ_256M)

 #endif
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c
b/arch/arm/mach-ixp4xx/avila-setup.c
index d8bc86d..776fd9f 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -170,6 +170,7 @@ MACHINE_START(AVILA, "Gateworks Avila Network Platform")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= avila_init,
 MACHINE_END

@@ -187,6 +188,7 @@ MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= avila_init,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c
b/arch/arm/mach-ixp4xx/coyote-setup.c
index 31a47f6..111e40b 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -115,6 +115,7 @@ MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= coyote_init,
 MACHINE_END
 #endif
@@ -132,6 +133,7 @@ MACHINE_START(IXDPG425, "Intel IXDPG425")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= coyote_init,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c
b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 7c1fa54..1ef65d1 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -282,6 +282,7 @@ MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
 	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
 	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
 	.boot_params	= 0x00000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= ixp4xx_map_io,
 	.init_irq	= ixp4xx_init_irq,
 	.timer          = &dsmg600_timer,
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index e7f4bef..4a80c4d 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -276,6 +276,7 @@ MACHINE_START(FSG, "Freecom FSG-3")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= fsg_init,
 MACHINE_END

diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c
b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index 2583b2a..fc70112 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -102,6 +102,7 @@ MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= gateway7001_init,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c
b/arch/arm/mach-ixp4xx/goramo_mlr.c
index 1c28048..dc33279 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -502,5 +502,6 @@ MACHINE_START(GORAMO_MLR, "MultiLink")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= gmlr_init,
 MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index c67586b..ea2b547 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -170,6 +170,7 @@ MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= gtwx5715_init,
 MACHINE_END

diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h
b/arch/arm/mach-ixp4xx/include/mach/memory.h
index 98f5e5e..cca6492 100644
--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
@@ -21,9 +21,6 @@ void ixp4xx_adjust_zones(int node, unsigned long
*size, unsigned long *holes);
 #define arch_adjust_zones(node, size, holes) \
 	ixp4xx_adjust_zones(node, size, holes)

-#define ISA_DMA_THRESHOLD (SZ_64M - 1)
-#define MAX_DMA_ADDRESS		(PAGE_OFFSET + SZ_64M)
-
 #endif

 #endif
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c
b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 827cbc4..567ed0e 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -262,6 +262,7 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= ixdp425_init,
 MACHINE_END
 #endif
@@ -275,6 +276,7 @@ MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= ixdp425_init,
 MACHINE_END
 #endif
@@ -288,6 +290,7 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100
Development Platform")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= ixdp425_init,
 MACHINE_END
 #endif
@@ -301,6 +304,7 @@ MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= ixdp425_init,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c
b/arch/arm/mach-ixp4xx/nas100d-setup.c
index e3ee880..ab3ab60 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -317,6 +317,7 @@ MACHINE_START(NAS100D, "Iomega NAS 100d")
 	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
 	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
 	.boot_params	= 0x00000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= ixp4xx_map_io,
 	.init_irq	= ixp4xx_init_irq,
 	.timer          = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c
b/arch/arm/mach-ixp4xx/nslu2-setup.c
index c14e003..cbc6536 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -303,6 +303,7 @@ MACHINE_START(NSLU2, "Linksys NSLU2")
 	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
 	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xFFFC,
 	.boot_params	= 0x00000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= ixp4xx_map_io,
 	.init_irq	= ixp4xx_init_irq,
 	.timer          = &nslu2_timer,
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c
b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index 4dd7486..b8d2d28 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -103,6 +103,7 @@ MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
 	.init_irq	= ixp4xx_init_irq,
 	.timer		= &ixp4xx_timer,
 	.boot_params	= 0x0100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= wg302v2_init,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index f3b5ace..f7e693d 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -353,4 +353,5 @@ MACHINE_START(BALLOON3, "Balloon3")
 	.timer		= &pxa_timer,
 	.init_machine	= balloon3_init,
 	.boot_params	= PHYS_OFFSET + 0x100,
+	.isa_dma_size	= SZ_64M,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index bff6e78..932f593 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -511,6 +511,7 @@ static void __init cmx2xx_map_io(void)

 MACHINE_START(ARMCORE, "Compulab CM-X2XX")
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io		= cmx2xx_map_io,
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index fdda6be..65c04bd 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -779,6 +779,7 @@ static void __init cm_x300_fixup(struct
machine_desc *mdesc, struct tag *tags,
 MACHINE_START(CM_X300, "CM-X300 module")
 	.phys_io	= 0x40000000,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c
b/arch/arm/mach-pxa/colibri-pxa270.c
index 061c453..634561d 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -140,6 +140,7 @@ MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= COLIBRI_SDRAM_BASE + 0x100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= colibri_pxa270_init,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c
b/arch/arm/mach-pxa/colibri-pxa300.c
index 45c23fd..571919f 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -188,6 +188,7 @@ MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= COLIBRI_SDRAM_BASE + 0x100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= colibri_pxa300_init,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c
b/arch/arm/mach-pxa/colibri-pxa320.c
index ae835fa..a67d0b4 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -218,6 +218,7 @@ MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= COLIBRI_SDRAM_BASE + 0x100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= colibri_pxa320_init,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 91fd4fe..769aadc 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -274,6 +274,7 @@ static void __init csb726_init(void)
 MACHINE_START(CSB726, "Cogent CSB726")
 	.phys_io	= 0x40000000,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io         = pxa_map_io,
 	.init_irq       = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c
index 8fde338..d131863 100644
--- a/arch/arm/mach-pxa/e330.c
+++ b/arch/arm/mach-pxa/e330.c
@@ -69,6 +69,7 @@ MACHINE_START(E330, "Toshiba e330")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa25x_init_irq,
 	.fixup		= eseries_fixup,
diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c
index f50f055..ff8ea6f 100644
--- a/arch/arm/mach-pxa/e350.c
+++ b/arch/arm/mach-pxa/e350.c
@@ -70,6 +70,7 @@ MACHINE_START(E350, "Toshiba e350")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa25x_init_irq,
 	.fixup		= eseries_fixup,
diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c
index 55b950f..20152d1 100644
--- a/arch/arm/mach-pxa/e400.c
+++ b/arch/arm/mach-pxa/e400.c
@@ -146,6 +146,7 @@ MACHINE_START(E400, "Toshiba e400")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa25x_init_irq,
 	.fixup		= eseries_fixup,
diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c
index d578021..6be1175 100644
--- a/arch/arm/mach-pxa/e740.c
+++ b/arch/arm/mach-pxa/e740.c
@@ -216,6 +216,7 @@ MACHINE_START(E740, "Toshiba e740")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa25x_init_irq,
 	.fixup		= eseries_fixup,
diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c
index af83caa..cfa6ed6 100644
--- a/arch/arm/mach-pxa/e750.c
+++ b/arch/arm/mach-pxa/e750.c
@@ -217,6 +217,7 @@ MACHINE_START(E750, "Toshiba e750")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa25x_init_irq,
 	.fixup		= eseries_fixup,
diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c
index 8ea97bf..e6ceeb2 100644
--- a/arch/arm/mach-pxa/e800.c
+++ b/arch/arm/mach-pxa/e800.c
@@ -220,6 +220,7 @@ MACHINE_START(E800, "Toshiba e800")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa25x_init_irq,
 	.fixup		= eseries_fixup,
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 0517c17..8ff6e18 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1301,6 +1301,7 @@ static void __init em_x270_init(void)

 MACHINE_START(EM_X270, "Compulab EM-X270")
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io		= pxa_map_io,
@@ -1311,6 +1312,7 @@ MACHINE_END

 MACHINE_START(EXEDA, "Compulab eXeda")
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io		= pxa_map_io,
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index 96c3451..101c2d3 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -226,6 +226,7 @@ static void __init gumstix_init(void)
 MACHINE_START(GUMSTIX, "Gumstix")
 	.phys_io	= 0x40000000,
 	.boot_params	= 0xa0000100, /* match u-boot bi_boot_params */
+	.isa_dma_size	= SZ_64M,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 848c861..2a3e5ec 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -873,6 +873,7 @@ MACHINE_START(H4700, "HP iPAQ HX4700")
 	.phys_io      = 0x40000000,
 	.io_pg_offst  = (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params  = 0xa0000100,
+	.isa_dma_size = SZ_64M,
 	.map_io       = pxa_map_io,
 	.init_irq     = pxa27x_init_irq,
 	.init_machine = hx4700_init,
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index 5ccb0ce..6dc7ff0 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -193,6 +193,7 @@ static void __init icontrol_init(void)
 MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
 	.phys_io	= 0x40000000,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c
index 5161dca..3f9ab27 100644
--- a/arch/arm/mach-pxa/imote2.c
+++ b/arch/arm/mach-pxa/imote2.c
@@ -587,4 +587,5 @@ MACHINE_START(INTELMOTE2, "IMOTE 2")
 	.timer		= &pxa_timer,
 	.init_machine	= imote2_init,
 	.boot_params	= 0xA0000100,
+	.isa_dma_size	= SZ_64M,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/include/mach/memory.h
b/arch/arm/mach-pxa/include/mach/memory.h
index f626730..23e4ae9 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -35,9 +35,6 @@ void cmx2xx_pci_adjust_zones(int node, unsigned long *size,

 #define arch_adjust_zones(node, size, holes) \
 	cmx2xx_pci_adjust_zones(node, size, holes)
-
-#define ISA_DMA_THRESHOLD	(PHYS_OFFSET + SZ_64M - 1)
-#define MAX_DMA_ADDRESS		(PAGE_OFFSET + SZ_64M)
 #endif

 #endif
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 9b90461..5b3c62a 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -439,6 +439,7 @@ static void __init littleton_init(void)
 MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform
(aka Littleton)")
 	.phys_io	= 0x40000000,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index d279507..01a4d29 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -508,6 +508,7 @@ MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= lpd270_map_io,
 	.init_irq	= lpd270_init_irq,
 	.timer		= &pxa_timer,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 5543c64..9a2e512 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -626,6 +626,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0
Development Platform (aka Mainstone)")
 	/* Maintainer: MontaVista Software Inc. */
 	.phys_io	= 0x40000000,
 	.boot_params	= 0xa0000100,	/* BLOB boot parameter setting */
+	.isa_dma_size	= SZ_64M,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io		= mainstone_map_io,
 	.init_irq	= mainstone_init_irq,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index d60db87..e0614b1 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -818,6 +818,7 @@ MACHINE_START(MIOA701, "MIO A701")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= &pxa_map_io,
 	.init_irq	= &pxa27x_init_irq,
 	.init_machine	= mioa701_machine_init,
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index 6d45039..3109bec 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -94,6 +94,7 @@ static void __init mp900c_init(void)
 MACHINE_START(NEC_MP900, "MobilePro900/C")
 	.phys_io	= 0x40000000,
 	.boot_params	= 0xa0220100,
+	.isa_dma_size	= SZ_64M,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.timer		= &pxa_timer,
 	.map_io		= pxa_map_io,
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 1963819..03b0a5b 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -530,6 +530,7 @@ MACHINE_START(PALMLD, "Palm LifeDrive")
 	.phys_io	= PALMLD_PHYS_IO_START,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= palmld_map_io,
 	.init_irq	= pxa27x_init_irq,
 	.timer		= &pxa_timer,
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 5305a39..419db0e 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -420,6 +420,7 @@ MACHINE_START(PALMT5, "Palm Tungsten|T5")
 	.phys_io	= PALMT5_PHYS_IO_START,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
 	.timer		= &pxa_timer,
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 3d284ff..bd66b91 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -372,6 +372,7 @@ MACHINE_START(PALMTE2, "Palm Tungsten|E2")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa25x_init_irq,
 	.timer		= &pxa_timer,
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index ecc1a40..cf94dbd 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -571,6 +571,7 @@ MACHINE_START(PALMTX, "Palm T|X")
 	.phys_io	= PALMTX_PHYS_IO_START,
 	.io_pg_offst	= io_p2v(0x40000000),
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= palmtx_map_io,
 	.init_irq	= pxa27x_init_irq,
 	.timer		= &pxa_timer,
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 3a7925c..6a448e9 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -492,6 +492,7 @@ MACHINE_START(PALMZ72, "Palm Zire72")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= io_p2v(0x40000000),
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
 	.timer		= &pxa_timer,
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 2190af0..631361f 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -259,6 +259,7 @@ static void __init pcm027_map_io(void)
 MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
 	/* Maintainer: Pengutronix */
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io		= pcm027_map_io,
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index d4b61b3..eae2587 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -1073,6 +1073,7 @@ MACHINE_START(RAUMFELD_RC, "Raumfeld Controller")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= RAUMFELD_SDRAM_BASE + 0x100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= raumfeld_controller_init,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa3xx_init_irq,
@@ -1085,6 +1086,7 @@ MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= RAUMFELD_SDRAM_BASE + 0x100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= raumfeld_connector_init,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa3xx_init_irq,
@@ -1097,6 +1099,7 @@ MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= RAUMFELD_SDRAM_BASE + 0x100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= raumfeld_speaker_init,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 6968911..dff2671 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -562,6 +562,7 @@ MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= TRIZEPS4_SDRAM_BASE + 0x100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= trizeps4_init,
 	.map_io		= trizeps4_map_io,
 	.init_irq	= pxa27x_init_irq,
@@ -573,6 +574,7 @@ MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps
IV-WL module")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= TRIZEPS4_SDRAM_BASE + 0x100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= trizeps4_init,
 	.map_io		= trizeps4_map_io,
 	.init_irq	= pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index e90114a..550dc53 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -995,6 +995,7 @@ MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= viper_map_io,
 	.init_irq	= viper_init_irq,
 	.timer          = &pxa_timer,
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index 9884fa9..5fc7700 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -608,6 +608,7 @@ MACHINE_START(VPAC270, "Voipac PXA270")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
 	.timer		= &pxa_timer,
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
index d3b4e3f..113382f 100644
--- a/arch/arm/mach-pxa/xcep.c
+++ b/arch/arm/mach-pxa/xcep.c
@@ -184,6 +184,7 @@ MACHINE_START(XCEP, "Iskratel XCEP")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.init_machine	= xcep_init,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index f5d1ae3..9d7c2e4 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -601,6 +601,7 @@ static void __init z2_init(void)
 MACHINE_START(ZIPIT2, "Zipit Z2")
 	.phys_io	= 0x40000000,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 03b9cb9..6acd425 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -903,6 +903,7 @@ MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= ((io_p2v(0x40000000) >> 18) & 0xfffc),
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.map_io		= zeus_map_io,
 	.init_irq	= zeus_init_irq,
 	.timer		= &pxa_timer,
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index c479cbe..d9419ff 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -413,6 +413,7 @@ static void __init zylonite_init(void)
 MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
 	.phys_io	= 0x40000000,
 	.boot_params	= 0xa0000100,
+	.isa_dma_size	= SZ_64M,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa3xx_init_irq,
diff --git a/arch/arm/mach-realview/include/mach/memory.h
b/arch/arm/mach-realview/include/mach/memory.h
index 2417bbc..6f0dcae 100644
--- a/arch/arm/mach-realview/include/mach/memory.h
+++ b/arch/arm/mach-realview/include/mach/memory.h
@@ -35,8 +35,6 @@ extern void realview_adjust_zones(int node, unsigned
long *size,
 #define arch_adjust_zones(node, size, hole) \
 	realview_adjust_zones(node, size, hole)

-#define ISA_DMA_THRESHOLD	(PHYS_OFFSET + SZ_256M - 1)
-#define MAX_DMA_ADDRESS		(PAGE_OFFSET + SZ_256M)
 #endif

 #ifdef CONFIG_SPARSEMEM
diff --git a/arch/arm/mach-realview/realview_eb.c
b/arch/arm/mach-realview/realview_eb.c
index 422ccd7..88ff55f 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -460,6 +460,7 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
 	.phys_io	= REALVIEW_EB_UART0_BASE,
 	.io_pg_offst	= (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
 	.boot_params	= PHYS_OFFSET + 0x00000100,
+	.isa_dma_size	= SZ_256M,
 	.fixup		= realview_fixup,
 	.map_io		= realview_eb_map_io,
 	.init_irq	= gic_init_irq,
diff --git a/arch/arm/mach-realview/realview_pb1176.c
b/arch/arm/mach-realview/realview_pb1176.c
index 96568eb..e8f197c 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -354,6 +354,7 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
 	.phys_io	= REALVIEW_PB1176_UART0_BASE,
 	.io_pg_offst	= (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc,
 	.boot_params	= PHYS_OFFSET + 0x00000100,
+	.isa_dma_size	= SZ_256M,
 	.fixup		= realview_pb1176_fixup,
 	.map_io		= realview_pb1176_map_io,
 	.init_irq	= gic_init_irq,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c
b/arch/arm/mach-realview/realview_pb11mp.c
index 7fbefbb..ee05e2b 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -376,6 +376,7 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
 	.phys_io	= REALVIEW_PB11MP_UART0_BASE,
 	.io_pg_offst	= (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc,
 	.boot_params	= PHYS_OFFSET + 0x00000100,
+	.isa_dma_size	= SZ_256M,
 	.fixup		= realview_fixup,
 	.map_io		= realview_pb11mp_map_io,
 	.init_irq	= gic_init_irq,
diff --git a/arch/arm/mach-realview/realview_pba8.c
b/arch/arm/mach-realview/realview_pba8.c
index d3c113b..133c3fc 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -326,6 +326,7 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
 	.phys_io	= REALVIEW_PBA8_UART0_BASE,
 	.io_pg_offst	= (IO_ADDRESS(REALVIEW_PBA8_UART0_BASE) >> 18) & 0xfffc,
 	.boot_params	= PHYS_OFFSET + 0x00000100,
+	.isa_dma_size	= SZ_256M,
 	.fixup		= realview_fixup,
 	.map_io		= realview_pba8_map_io,
 	.init_irq	= gic_init_irq,
diff --git a/arch/arm/mach-realview/realview_pbx.c
b/arch/arm/mach-realview/realview_pbx.c
index a235ba3..eff8722 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -412,6 +412,7 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
 	.phys_io	= REALVIEW_PBX_UART0_BASE,
 	.io_pg_offst	= (IO_ADDRESS(REALVIEW_PBX_UART0_BASE) >> 18) & 0xfffc,
 	.boot_params	= PHYS_OFFSET + 0x00000100,
+	.isa_dma_size	= SZ_256M,
 	.fixup		= realview_pbx_fixup,
 	.map_io		= realview_pbx_map_io,
 	.init_irq	= gic_init_irq,
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 169e5b8..a16ae38 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -450,6 +450,9 @@ MACHINE_START(ASSABET, "Intel-Assabet")
 	.phys_io	= 0x80000000,
 	.io_pg_offst	= ((0xf8000000) >> 18) & 0xfffc,
 	.boot_params	= 0xc0000100,
+#ifdef CONFIG_SA1111
+	.isa_dma_size	= SZ_1M,
+#endif
 	.fixup		= fixup_assabet,
 	.map_io		= assabet_map_io,
 	.init_irq	= sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index 259cb2c..15bd5b9 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -305,6 +305,9 @@ MACHINE_START(BADGE4, "Hewlett-Packard
Laboratories BadgePAD 4")
 	.phys_io	= 0x80000000,
 	.io_pg_offst	= ((0xf8000000) >> 18) & 0xfffc,
 	.boot_params	= 0xc0000100,
+#ifdef CONFIG_SA1111
+	.isa_dma_size	= SZ_1M,
+#endif
 	.map_io		= badge4_map_io,
 	.init_irq	= sa1100_init_irq,
 	.timer		= &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h
b/arch/arm/mach-sa1100/include/mach/memory.h
index d5277f9..95558b4 100644
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -22,9 +22,6 @@ void sa1111_adjust_zones(int node, unsigned long
*size, unsigned long *holes);
 #define arch_adjust_zones(node, size, holes) \
 	sa1111_adjust_zones(node, size, holes)

-#define ISA_DMA_THRESHOLD	(PHYS_OFFSET + SZ_1M - 1)
-#define MAX_DMA_ADDRESS		(PAGE_OFFSET + SZ_1M)
-
 #endif
 #endif

diff --git a/arch/arm/mach-sa1100/jornada720.c
b/arch/arm/mach-sa1100/jornada720.c
index d3ec620..829bd1e 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -367,6 +367,9 @@ MACHINE_START(JORNADA720, "HP Jornada 720")
 	.phys_io	= 0x80000000,
 	.io_pg_offst	= ((0xf8000000) >> 18) & 0xfffc,
 	.boot_params	= 0xc0000100,
+#ifdef CONFIG_SA1111
+	.isa_dma_size	= SZ_1M,
+#endif
 	.map_io		= jornada720_map_io,
 	.init_irq	= sa1100_init_irq,
 	.timer		= &sa1100_timer,
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 358d875..7fc348c 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -155,6 +155,7 @@ MACHINE_START(SHARK, "Shark")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= ((0xe0000000) >> 18) & 0xfffc,
 	.boot_params	= 0x08003000,
+	.isa_dma_size	= SZ_4M,
 	.map_io		= shark_map_io,
 	.init_irq	= shark_init_irq,
 	.timer		= &shark_timer,
diff --git a/arch/arm/mach-shark/include/mach/memory.h
b/arch/arm/mach-shark/include/mach/memory.h
index 3053e5b..dd690f3 100644
--- a/arch/arm/mach-shark/include/mach/memory.h
+++ b/arch/arm/mach-shark/include/mach/memory.h
@@ -33,9 +33,6 @@ static inline void __arch_adjust_zones(int node,
unsigned long *zone_size, unsig
 #define arch_adjust_zones(node, size, holes) \
 	__arch_adjust_zones(node, size, holes)

-#define ISA_DMA_THRESHOLD	(PHYS_OFFSET + SZ_4M - 1)
-#define MAX_DMA_ADDRESS		(PAGE_OFFSET + SZ_4M)
-
 #endif

 /*
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 13fa536..e42f873 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -33,6 +33,18 @@
 #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) -
CONSISTENT_BASE) >> PGDIR_SHIFT)
 #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)

+unsigned long ISA_DMA_THRESHOLD = 0xffffffffUL;
+EXPORT_SYMBOL(ISA_DMA_THRESHOLD);
+
+unsigned long MAX_DMA_ADDRESS = 0xffffffffUL;
+EXPORT_SYMBOL(MAX_DMA_ADDRESS);
+
+void __init set_isa_dma_size(unsigned long size)
+{
+	ISA_DMA_THRESHOLD = PHYS_OFFSET + size - 1;
+	MAX_DMA_ADDRESS = PAGE_OFFSET + size;
+}
+
 static u64 get_coherent_dma_mask(struct device *dev)
 {
 	u64 mask = ISA_DMA_THRESHOLD;


From pieterg at gmx.com  Fri Jun  4 04:36:39 2010
From: pieterg at gmx.com (pieterg)
Date: Fri, 4 Jun 2010 10:36:39 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006040310.15019.marek.vasut@gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
Message-ID: <201006041036.39059.pieterg@gmx.com>

On Friday 04 June 2010 03:10:14 Marek Vasut wrote:
> I just tested, PXA (mach-pxa) probably can be compiled into single kernel
> supporting all the boards.

For my boards (colibri) I see only one exception; I haven't managed to build 
a single kernel with support for different AC97 chips.

I have to build separate WM9715 and UCB1400 kernels.

Rgds, Pieter


From martinwguy at gmail.com  Fri Jun  4 04:40:45 2010
From: martinwguy at gmail.com (Martin Guy)
Date: Fri, 4 Jun 2010 09:40:45 +0100
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
Message-ID: <AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>

I think you've missed the point.

Linus' problem is that he is spending MOST of his linux-kernel-support
time fielding patches from a dozen port maintainers, and dropping
defconfigs is a desperate attempt to cut the amount of arm fiddling he
is asked to do, and I guess droppiong defconfigs seems to him to be
they way to cut the least important and most verbose part of this
drudgery.
I'm sure he'd rather be writing programs.

While a defconfig restructuring does address the specific issue it's
pointless. He's going to drop defconfigs, so we'll all just have to
have our own web pages giving our suggested defconfigs for our own
boards.

Shame. I was about to post a Sim.One defconfig patch (while fully
realizing that the choice of options is largely arbitrary. and copied
ad-hoc from some other similar defconfig). While it's nice to be able
to tell people "make foobar_defconfig; make (z|u|bz)Image" in reality
the config is as arbitrary as the root filesystem in use (and should
be chosen to match it).

The best way to free up many hours every day of Linus' time is for one
person to isolate him from the port maintainers, so that he only has
to pull (ideally) once per release cycle from one repository.

The question is, do we have the resources and the organization to take
that constant burden of work off one of our brightest programmers so
that he can get on with what he's really interested in?

    M


From s.hauer at pengutronix.de  Fri Jun  4 04:53:21 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 4 Jun 2010 10:53:21 +0200
Subject: [V2 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <20100604085320.GB25357@pengutronix.de>

On Thu, Jun 03, 2010 at 08:05:44PM +0800, Jason Wang wrote:
> +
> +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
> +{

I'm not willing to accept another 3ds_debug board support in the kernel
given that it's no rocket science to seperate this into another file and
we still have plenty of time before the next merge window.
Jason, can you please move this to plat-mxc? I think we could find
someone else to switch the mx31_3ds support to the generic debug board
support then.


[snip]

>  #define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
>  #define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
> +#define MX51_PAD_EIM_D25__UART2_CTS	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT4, 0x0, 0, MX51_UART2_PAD_CTRL)
>  #define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
> -#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
> +#define MX51_PAD_EIM_D26__UART2_RTS	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
> +#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
>  
>  #define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
>  #define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
> @@ -202,8 +204,8 @@ typedef enum iomux_config {
>  #define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
>  #define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
>  
> -#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_UART3_PAD_CTRL)

Urgs, there really is something wrong here.

First of all, this define should be named MX51_PAD_UART3_RXD__GPIO_1_22
as it describes the pad UART3_RXD in GPIO_1_22 mode. This seems to be
wrong with many (all?) defines in this file. Amit, you should have read
the comment ontop of this file which you copied from the i.MX35 part:

/*
 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
 * If <padname> or <padmode> refers to a GPIO, it is named
 * GPIO_<unit>_<num> see also iomux-v3.h
 */

This should be fixed before doing any other change to this file.

Then Jason, what you are looking for is the following:

#define MX51_PAD_UART3_RXD__UART3_RXD

because you want the UART3_RXD pad in its native mode.

Here is how the defines in this file should look like (modulo bugs):


#define MX51_PAD_EIM_D16__GPIO_2_0		(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D17__GPIO_2_1		(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D18__GPIO_2_2		(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D19__GPIO_2_3		(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D20__GPIO_2_4		(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D21__GPIO_2_5		(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D22__GPIO_2_6		(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D23__GPIO_2_7		(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D24__UART3_CTS		(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D25__UART3_RXD		(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D26__UART3_TXD		(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D27__UART3_RTS		(0x41c, 0x088, 3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
#define MX51_PAD_EIM_D28__EIM_D28		(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D29__EIM_D29		(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D30__EIM_D30		(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_D31__EIM_D31		(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A16__GPIO_2_10		(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A17__GPIO_2_11		(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A18__GPIO_2_12		(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A19__GPIO_2_13		(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A20__GPIO_2_14		(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A21__GPIO_2_15		(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A22__GPIO_2_16		(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A23__GPIO_2_17		(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A24__GPIO_2_18		(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A25__GPIO_2_19		(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A26__GPIO_2_20		(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_A27__GPIO_2_21		(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB0__EIM_EB0		(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB1__EIM_EB1		(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB2__GPIO_2_22		(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_EB3__GPIO_2_23		(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_OE__GPIO_2_24		(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS0__GPIO_2_25		(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS1__GPIO_2_26		(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS2__GPIO_2_27		(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS3__GPIO_2_28		(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS4__GPIO_2_29		(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CS5__GPIO_2_30		(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_DTACK__GPIO_2_31		(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_LBA__GPIO_3_1		(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_EIM_CRE__GPIO_3_2		(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DRAM_CS1__DRAM_CS1		(0x4D0, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_WE_B__GPIO_3_3		(0x4E4, 0x108, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RE_B__GPIO_3_4		(0x4E8, 0x10C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_ALE__GPIO_3_5		(0x4EC, 0x110, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CLE__GPIO_3_6		(0x4F0, 0x114, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_WP_B__GPIO_3_7		(0x4F4, 0x118, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB0__GPIO_3_8		(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB1__GPIO_3_9		(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB2__GPIO_3_10		(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB3__GPIO_3_11		(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO_NAND__GPIO_3_12		(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RB6__GPIO_3_14		(0x5DC, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS0__GPIO_3_16		(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS1__GPIO_3_17		(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS2__GPIO_3_18		(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS3__GPIO_3_19		(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS4__GPIO_3_20		(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS5__GPIO_3_21		(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS6__GPIO_3_22		(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_CS7__GPIO_3_23		(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24	(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D15__GPIO_3_25		(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D14__GPIO_3_26		(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D13__GPIO_3_27		(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D12__GPIO_3_28		(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D11__GPIO_3_29		(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D10__GPIO_3_30		(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D9__GPIO_3_31		(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D8__GPIO_4_0		(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D7__GPIO_4_1		(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D6__GPIO_4_2		(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D5__GPIO_4_3		(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D4__GPIO_4_4		(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D3__GPIO_4_5		(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D2__GPIO_4_6		(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D1__GPIO_4_7		(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_NANDF_D0__GPIO_4_8		(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D8__GPIO_3_12		(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D9__GPIO_3_13		(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D10__CSI1_D10		(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D11__CSI1_D11		(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D12__CSI1_D12		(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D13__CSI1_D13		(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D14__CSI1_D14		(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D15__CSI1_D15		(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D16__CSI1_D16		(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D17__CSI1_D17		(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D18__CSI1_D18		(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_D19__CSI1_D19		(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC		(0x5AC, 0x1C4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC		(0x5B0, 0x1C8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK	(0x5B4, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_MCLK__CSI1_MCLK		(0x5B8, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI1_PKE0__CSI1_PKE0		(0x860, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D12__GPIO_4_9		(0x5BC, 0x1CC, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D13__GPIO_4_10		(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D14__GPIO_4_11		(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D15__GPIO_4_12		(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D16__GPIO_4_11		(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D17__GPIO_4_12		(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D18__GPIO_4_11		(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_D19__GPIO_4_12		(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_VSYNC__GPIO_4_13		(0x5DC, 0x1EC, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_HSYNC__GPIO_4_14		(0x5E0, 0x1F0, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15		(0x5E4, 0x1F4, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSI2_PKE0__CSI2_PKE0		(0x81C, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_I2C1_CLK__GPIO_4_16		(0x5E8, 0x1F8, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_I2C1_DAT__GPIO_4_17		(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18		(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19		(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_CK__GPIO_4_20		(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_AUD3_BB_FS__GPIO_4_21		(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_MOSI__GPIO_4_22		(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_MISO__GPIO_4_23		(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SS0__GPIO_4_24		(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SS1__GPIO_4_25		(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_RDY__GPIO_4_26		(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_CSPI1_SCLK__GPIO_4_27		(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_UART1_RXD__UART1_RXD		(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
#define MX51_PAD_UART1_TXD__UART1_TXD		(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
#define MX51_PAD_UART1_RTS__UART1_RTS		(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
#define MX51_PAD_UART1_CTS__UART1_CTS		(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
#define MX51_PAD_UART2_RXD__UART2_RXD		(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
#define MX51_PAD_UART2_TXD__UART2_TXD		(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
#define MX51_PAD_UART3_RXD__GPIO_1_22		(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_UART3_TXD__GPIO_1_23		(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_OWIRE_LINE__GPIO_1_24		(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW0__KEY_ROW0		(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW1__KEY_ROW1		(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW2__KEY_ROW2		(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_ROW3__KEY_ROW3		(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL0__KEY_COL0		(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL1__KEY_COL1		(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL2__KEY_COL2		(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL3__KEY_COL3		(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL4__KEY_COL4		(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_KEY_COL5__KEY_COL5		(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_USBH1_CLK__USBH1_CLK		(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DIR__USBH1_DIR		(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_STP__USBH1_STP		(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_STP__GPIO_1_27		(0x680, 0x280, 2, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_NXT__USBH1_NXT		(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
#define MX51_PAD_DI1_PIN11__GPIO_3_0		(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN12__GPIO_3_1		(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN13__GPIO_3_2		(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI1_D0_CS__GPIO_3_3		(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI1_D1_CS__GPIO_3_4		(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5	(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6	(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7	(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8	(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT0__DISP1_DAT0		(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT1__DISP1_DAT1		(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT2__DISP1_DAT2		(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT3__DISP1_DAT3		(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT4__DISP1_DAT4		(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT5__DISP1_DAT5		(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT6__DISP1_DAT6		(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT7__DISP1_DAT7		(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT8__DISP1_DAT8		(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT9__DISP1_DAT9		(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN3__DI1_PIN3		(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI1_PIN2__DI1_PIN2		(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP1__DI_GP1			(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP2__DI_GP2			(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP3__DI_GP3			(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI2_PIN4__DI2_PIN4		(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI2_PIN2__DI2_PIN2		(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI2_PIN3__DI2_PIN3		(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DI_GP4__DI_GP4			(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT0__DISP2_DAT0		(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT1__DISP2_DAT1		(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT2__DISP2_DAT2		(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT3__DISP2_DAT3		(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT4__DISP2_DAT4		(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT5__DISP2_DAT5		(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT6__GPIO_1_19		(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT7__GPIO_1_29		(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT8__GPIO_1_30		(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT9__GPIO_1_31		(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CMD__SD1_CMD		(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD1_CLK__SD1_CLK		(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA0__SD1_DATA0		(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA1__SD1_DATA1		(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA2__SD1_DATA2		(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD1_DATA3__SD1_DATA3		(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_0__GPIO_1_0		(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_1__GPIO_1_1		(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD2_CMD__SD2_CMD		(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD2_CLK__SD2_CLK		(0x7C0, 0x3B8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA0__SD2_DATA0		(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA1__SD2_DATA1		(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA2__SD2_DATA2		(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_SD2_DATA3__SD2_DATA3		(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_2__GPIO_1_2		(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_3__GPIO_1_3		(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_4__GPIO_1_4		(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_5__GPIO_1_5		(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_6__GPIO_1_6		(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
#define MX51_PAD_GPIO1_7__GPIO_1_7		(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO1_8__GPIO_1_8		(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
#define MX51_PAD_GPIO1_9__GPIO_1_9		(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From daniel at caiaq.de  Fri Jun  4 04:56:29 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Fri, 4 Jun 2010 10:56:29 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006041036.39059.pieterg@gmx.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<201006041036.39059.pieterg@gmx.com>
Message-ID: <20100604085629.GU2695@buzzloop.caiaq.de>

On Fri, Jun 04, 2010 at 10:36:39AM +0200, pieterg wrote:
> On Friday 04 June 2010 03:10:14 Marek Vasut wrote:
> > I just tested, PXA (mach-pxa) probably can be compiled into single kernel
> > supporting all the boards.
> 
> For my boards (colibri) I see only one exception; I haven't managed to build 
> a single kernel with support for different AC97 chips.

Which problems did you have when tring this?

Daniel


From mcuos.com at gmail.com  Fri Jun  4 05:28:41 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Fri, 04 Jun 2010 17:28:41 +0800
Subject: [PATCH]ARM/footbridge: fix wrong parenthesis
Message-ID: <4C08C749.3050700@gmail.com>

There is a wrong redundant right parenthesis in this code.


Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
---
 arch/arm/mach-footbridge/common.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index e3bc3f6..cdbea55 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -232,7 +232,7 @@ EXPORT_SYMBOL(__bus_to_virt);

 unsigned long __pfn_to_bus(unsigned long pfn)
 {
-	return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET));
+	return __pfn_to_phys(pfn + (fb_bus_sdram_offset() - PHYS_OFFSET));
 }
 EXPORT_SYMBOL(__pfn_to_bus);

-- 
1.6.3.3


From pieterg at gmx.com  Fri Jun  4 05:37:18 2010
From: pieterg at gmx.com (pieterg)
Date: Fri, 4 Jun 2010 11:37:18 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100604085629.GU2695@buzzloop.caiaq.de>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<201006041036.39059.pieterg@gmx.com>
	<20100604085629.GU2695@buzzloop.caiaq.de>
Message-ID: <201006041137.18270.pieterg@gmx.com>

On Friday 04 June 2010 10:56:29 Daniel Mack wrote:
> On Fri, Jun 04, 2010 at 10:36:39AM +0200, pieterg wrote:
> > On Friday 04 June 2010 03:10:14 Marek Vasut wrote:
> > > I just tested, PXA (mach-pxa) probably can be compiled into single
> > > kernel supporting all the boards.
> >
> > For my boards (colibri) I see only one exception; I haven't managed to
> > build a single kernel with support for different AC97 chips.
>
> Which problems did you have when tring this?

Hm, thanks for making me try this again. I was convinced a UCB1400 
touchscreen was not recognised when I had CONFIG_TOUCHSCREEN_WM97XX in the 
config, but trying this again now shows it works fine.
I must have drawn the wrong conclusion back then.
Glad I can use a single config for my boards now.

Rgds, Pieter


From maramaopercheseimorto at gmail.com  Fri Jun  4 05:48:54 2010
From: maramaopercheseimorto at gmail.com (Alberto Panizzo)
Date: Fri, 04 Jun 2010 11:48:54 +0200
Subject: [V2 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <20100604085320.GB25357@pengutronix.de>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100604085320.GB25357@pengutronix.de>
Message-ID: <1275644934.3210.46.camel@realization>

On ven, 2010-06-04 at 10:53 +0200, Sascha Hauer wrote:
> I'm not willing to accept another 3ds_debug board support in the
> kernel
> given that it's no rocket science to seperate this into another file
> and
> we still have plenty of time before the next merge window.
> Jason, can you please move this to plat-mxc? I think we could find
> someone else to switch the mx31_3ds support to the generic debug board
> support then. 

Sascha, what do you mean with: switch the mx31_3ds support to the generic
one in plat-mxc?
We are going to have a single machine file for all imx(2-3-5) based debug boards?
I think it will look so messy..

I read the Linus concerns about ARM stuffs and RMK answer to your ask for pull..
May we need to start a thread to discuss how we can restructure the imx support?

-- 
Alberto!

        Be Persistent!
                - Greg Kroah-Hartman (FOSDEM 2010)



From js at sig21.net  Fri Jun  4 06:38:51 2010
From: js at sig21.net (Johannes Stezenbach)
Date: Fri, 4 Jun 2010 12:38:51 +0200
Subject: [PATCH RFC] fix placement of the .note.gnu.build-id section
Message-ID: <20100604103851.GA5616@sig21.net>

Hi,

I've brought up the issue before but there was no conclusion:
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/015994.html

Now there was a thread on lkml that brought to my attention
that perf uses the build-id to match perf record files
to the matching vmlinux ELF file:
http://lkml.org/lkml/2010/6/3/445

I'm not sure about the state of perf on ARM, but I guess we
should follow x86, thus I'm proposing the following patch.

-------------
ARM: fix placement of the .note.gnu.build-id section

The build-id and other ELF notes should be made available
at runtime in /sys/kernel/notes because it is used by perf
to match record files to the vmlinux ELF file.

Correcting the placement of the build-id section in the vmlinux
ELF file also avoids problems for JTAG debuggers which cannot
load the ELF file with the misplaced section into target RAM.

Old layout:

Program Header:
    LOAD off    0x00008000 vaddr 0x00000000 paddr 0x00000000 align 2**15
         filesz 0x00000024 memsz 0x00000024 flags r--
    LOAD off    0x00010000 vaddr 0xc0008000 paddr 0xc0008000 align 2**15
         filesz 0x0033cb60 memsz 0x0036df04 flags rwx
    NOTE off    0x00008000 vaddr 0x00000000 paddr 0x00000000 align 2**2
         filesz 0x00000024 memsz 0x00000024 flags r--

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .note.gnu.build-id 00000024  00000000  00000000  00008000  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA, LINK_ONCE_DISCARD


New layout:

Program Header:
    LOAD off    0x00008000 vaddr 0xc0008000 paddr 0xc0008000 align 2**15
         filesz 0x0031b024 memsz 0x0031b024 flags r-x
    LOAD off    0x00324000 vaddr 0xc0324000 paddr 0xc0324000 align 2**15
         filesz 0x00020b60 memsz 0x00051f04 flags rwx
    NOTE off    0x00323000 vaddr 0xc0323000 paddr 0xc0323000 align 2**2
         filesz 0x00000024 memsz 0x00000024 flags ---

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  7 .notes        00000024  c0323000  c0323000  00323000  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA, LINK_ONCE_DISCARD


Signed-off-by: Johannes Stezenbach <js at sig21.net>

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 64ba313..f938736 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -15,7 +15,7 @@ ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux	+= --be8
 endif
 
-OBJCOPYFLAGS	:=-O binary -R .note -R .note.gnu.build-id -R .comment -S
+OBJCOPYFLAGS	:=-O binary -R .comment -S
 GZFLAGS		:=-9
 #KBUILD_CFLAGS	+=-pipe
 # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..2fca978 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -17,6 +17,12 @@ jiffies = jiffies_64;
 jiffies = jiffies_64 + 4;
 #endif
 
+PHDRS {
+	text PT_LOAD FLAGS(5);		/* R_E */
+	data PT_LOAD FLAGS(7);		/* RWE */
+	note PT_NOTE FLAGS(0);		/* ___ */
+}
+
 SECTIONS
 {
 #ifdef CONFIG_XIP_KERNEL
@@ -52,7 +58,7 @@ SECTIONS
 		__init_begin = _stext;
 		INIT_DATA
 #endif
-	}
+	} :text
 
 	PERCPU(PAGE_SIZE)
 
@@ -104,6 +110,8 @@ SECTIONS
 
 	RO_DATA(PAGE_SIZE)
 
+	NOTES :text :note
+
 	_etext = .;			/* End of text and rodata section */
 
 #ifdef CONFIG_ARM_UNWIND
@@ -115,7 +123,7 @@ SECTIONS
 		__start_unwind_idx = .;
 		*(.ARM.exidx*)
 		__stop_unwind_idx = .;
-	}
+	} :text
 	.ARM.unwind_tab : {
 		__start_unwind_tab = .;
 		*(.ARM.extab*)
@@ -169,7 +177,7 @@ SECTIONS
 		CONSTRUCTORS
 
 		_edata = .;
-	}
+	} :data
 	_edata_loc = __data_loc + SIZEOF(.data);
 
 #ifdef CONFIG_HAVE_TCM


From kgene.kim at samsung.com  Fri Jun  4 06:36:33 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri,  4 Jun 2010 19:36:33 +0900
Subject: [PATCH 1/2] MAINTAINERS: update files for SAMSUNG ARM ARCHITECTURES
Message-ID: <1275647794-30634-1-git-send-email-kgene.kim@samsung.com>

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 MAINTAINERS |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index a73dd80..1d41149 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -899,7 +899,7 @@ M:	Ben Dooks <ben-linux at fluff.org>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 W:	http://www.fluff.org/ben/linux/
 S:	Maintained
-F:	arch/arm/plat-s3c/
+F:	arch/arm/plat-samsung/
 F:	arch/arm/plat-s3c24xx/
 
 ARM/S3C2410 ARM ARCHITECTURE
-- 
1.6.2.5



From kgene.kim at samsung.com  Fri Jun  4 06:36:34 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri,  4 Jun 2010 19:36:34 +0900
Subject: [PATCH 2/2] MAINTAINERS: add maintainer for SAMSUNG ARM ARCHITECTURES
In-Reply-To: <1275647794-30634-1-git-send-email-kgene.kim@samsung.com>
References: <1275647794-30634-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1275647794-30634-2-git-send-email-kgene.kim@samsung.com>

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 MAINTAINERS |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 1d41149..f4e4c61 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -896,11 +896,13 @@ S:	Maintained
 
 ARM/SAMSUNG ARM ARCHITECTURES
 M:	Ben Dooks <ben-linux at fluff.org>
+M:	Kukjin Kim <kgene.kim at samsung.com>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 W:	http://www.fluff.org/ben/linux/
 S:	Maintained
 F:	arch/arm/plat-samsung/
 F:	arch/arm/plat-s3c24xx/
+F:	arch/arm/plat-s5p/
 
 ARM/S3C2410 ARM ARCHITECTURE
 M:	Ben Dooks <ben-linux at fluff.org>
-- 
1.6.2.5



From tony at atomide.com  Fri Jun  4 06:42:47 2010
From: tony at atomide.com (Tony Lindgren)
Date: Fri, 4 Jun 2010 13:42:47 +0300
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
Message-ID: <20100604104246.GD11111@atomide.com>

* Eric Miao <eric.y.miao at gmail.com> [100604 10:07]:
> On Fri, Jun 4, 2010 at 2:10 PM, Tony Lindgren <tony at atomide.com> wrote:
> > * Eric Miao <eric.y.miao at gmail.com> [100604 04:35]:
> >>
> >> Also, we are now working on a single kernel for multiple sub-arch (at least
> >> what Nicolas and I am doing now, and welcome to join us). It's tough (the
> >> way to handle different phys_offset is only the tip of the iceberg) and seems
> >> now more and more necessary. so hopefully by the end of the day, we may
> >> possible end up with only very few defconfig.
> >
> > Great, do you have some git branch for that somewhere?
> >
> 
> All the currently done work I've posted to the mailing list:
> 
> 1. SPARSEIRQ
> 2. MULTI_IRQ_HANDLER
> 3. Makefile.boot move to arch/arm/boot/bootp _only_
> 4. RUNTIME_PHYS_OFFSET (not really my work, but Uwe's)
> 
> Nico and I have setup a blueprint and wiki spec for this, I hope more
> can join us with the effort.
> 
> https://blueprints.launchpad.net/ubuntu/+spec/kernel-maverick-arm-single-zimage
> https://wiki.ubuntu.com/Specs/ARMSingleKernel
> 
> I'll push what I did to
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git
> unified-kernel
> 
> But it's a mess now.

OK thanks.
 
> > Parallel to dealing with different phys_offset we can also try combining
> > some two ARM platforms that have the same phy_offset. That already exposes
> > tons of conflicting defines that need to be sorted out..
> >
> 
> A first step to take might be looking at all those machine specific header
> files that will be included into generic <asm/*.h> and in turn included by
> other code. The PHYS_OFFSET is only a small tip of the iceberg I'm afraid.
> A very rough grep and analysis as below:

Nice analysis :) First I need to finish my earlier TLS patch for ARMv6 and 7
binaries, then I'll try to find some time to help on this stuff too.

Tony


From amit.kucheria at canonical.com  Fri Jun  4 06:53:47 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Fri, 4 Jun 2010 13:53:47 +0300
Subject: [V2 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <20100604085320.GB25357@pengutronix.de>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100604085320.GB25357@pengutronix.de>
Message-ID: <20100604105347.GA2982@matterhorn.lan>

On 10 Jun 04, Sascha Hauer wrote:
> On Thu, Jun 03, 2010 at 08:05:44PM +0800, Jason Wang wrote:
> >  
> > -#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
> > -#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
> > +#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
> > +#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_UART3_PAD_CTRL)
> 
> Urgs, there really is something wrong here.
> 
> First of all, this define should be named MX51_PAD_UART3_RXD__GPIO_1_22
> as it describes the pad UART3_RXD in GPIO_1_22 mode. This seems to be
> wrong with many (all?) defines in this file. Amit, you should have read
> the comment ontop of this file which you copied from the i.MX35 part:

I'll admit that I was not completely conversant with the naming scheme then.
All the GPIO-related names have been reversed. The others seem fine.

> /*
>  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
>  * If <padname> or <padmode> refers to a GPIO, it is named
>  * GPIO_<unit>_<num> see also iomux-v3.h
>  */

There was a comment below this:
/*
 * FIXME: This was converted using scripts from existing Freescale code to
 * this form used upstream. Need to verify the name format.
 */

I obviously reversed the naming for all the GPIO pads.

> This should be fixed before doing any other change to this file.

I'm preparing a patch now.

> Then Jason, what you are looking for is the following:
> 
> #define MX51_PAD_UART3_RXD__UART3_RXD
> 
> because you want the UART3_RXD pad in its native mode.

Cheers,
Amit

-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------


From u.kleine-koenig at pengutronix.de  Fri Jun  4 07:06:59 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 4 Jun 2010 13:06:59 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006032155.19349.marek.vasut@gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<201006032155.19349.marek.vasut@gmail.com>
Message-ID: <20100604110659.GA14543@pengutronix.de>

On Thu, Jun 03, 2010 at 09:55:19PM +0200, Marek Vasut wrote:
> Dne ?t 3. ?ervna 2010 21:24:59 Russell King - ARM Linux napsal(a):
> > The subject says everything you need to know.  Randy provided this
> > link earlier:
> > 
> >   http://lkml.org/lkml/2010/6/2/472
> > 
> > Linus doesn't appear to be listening to reason, so I see now this as
> > a fait accompli.  It'll apparantly happen at the next merge window.
> 
> The defconfigs age ... there's no point keeping them. They'll be useless crap 
> unless someone updates them often anyway.
Some time ago I wrote a little script that minimized a .config and
applied it to ns9xxx_defconfig.

The result is that ns9xxx_defconfig only has 79 lines while the average
is >1200.  (I have to admit that ns9xxx isn't complete by far as there
are no device drivers in tree, but anyhow, after $(make
ns9xxx_defconfig) the resulting .config has 1181 lines.) Would it already
help to apply it to all defconfigs?  A nice effect is that changes to
these small files are smaller and so easier to understand.  IIRC I posted
the script to linux-kbuild back then.  I can try to find and apply it
before the next merge window.

And I want to point out that there are efforts to merge all arch-mx* and
plat-mxc and so reduce the number of defconfigs from seven[1] to one.
Eric picked up on the runtime-physoffset patches that are currently a
stopper for (AFAIK) several merges.

Best regards
Uwe

[1] IIRC I recently saw a patch that adds mx25_defconfig, so there are
even eight imx defconfigs.

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From catalin.marinas at arm.com  Fri Jun  4 08:11:31 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 04 Jun 2010 13:11:31 +0100
Subject: [PATCH] ARM: Do not enable ARM_DMA_MEM_BUFFERABLE for some RealView
	boards
Message-ID: <20100604121130.20940.51309.stgit@e102109-lin.cambridge.arm.com>

RealView boards with certain revisions of the L210/L220 cache controller
may have issues with recent changes to the mb() barrier implementation
(DSB followed by an L2 cache sync).

Until an L2-specific workaround is added, this patch proposes that the
mb() barrier performs an outer cache sync only when
ARM_DMA_MEM_BUFFERABLE is enabled. When this is option is disabled, the
coherent DMA buffers are mapped as Strongly Ordered and there is no need
for an L2 cache sync.

The patch also disables ARM_DMA_MEM_BUFFERABLE for some of the RealView
boards with L210/L220.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Russell King <rmk at arm.linux.org.uk>
Cc: Linus Walleij <linus.ml.walleij at gmail.com>
Cc: Bjoern B. Brandenburg <bbb.lst at gmail.com>
---
 arch/arm/include/asm/system.h |    6 +++++-
 arch/arm/mm/Kconfig           |    2 ++
 2 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 5f4f480..3b2abcf 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -141,10 +141,14 @@ extern unsigned int user_debug;
 
 #ifdef CONFIG_ARCH_HAS_BARRIERS
 #include <mach/barriers.h>
-#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
+#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE)
 #define mb()		do { dsb(); outer_sync(); } while (0)
 #define rmb()		dmb()
 #define wmb()		mb()
+#elif defined(CONFIG_SMP)
+#define mb()		dsb()
+#define rmb()		dmb()
+#define wmb()		mb()
 #else
 #define mb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 #define rmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 3053731..9f10a9b 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -828,6 +828,8 @@ config ARM_L1_CACHE_SHIFT
 
 config ARM_DMA_MEM_BUFFERABLE
 	bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
+	depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
+		     MACH_REALVIEW_PB11MP)
 	default y if CPU_V6 || CPU_V7
 	help
 	  Historically, the kernel has used strongly ordered mappings to



From daniel at caiaq.de  Fri Jun  4 08:12:45 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Fri, 4 Jun 2010 14:12:45 +0200
Subject: Libertas/SDIO deep sleep mode
Message-ID: <20100604121245.GW2695@buzzloop.caiaq.de>

Hi,

I read about the recently added features in the libertas driver to send
the chip to its deep-sleep mode when the system suspends, so the wakeup
phase is shortened.

I tried this with a recent 2.6.35-rc1 kernel on a PXA300 based design,
and this is what I get:


[    0.721643] Freezing user space processes ... (elapsed 0.01 seconds) done.
[    0.740588] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
[    0.760687] Suspending console(s) (use no_console_suspend to debug)
[    0.879657] libertas: 00:19:88:3a:cb:ac, fw 9.70.3p36, cap 0x00000303
[    0.880567] ------------[ cut here ]------------
[    0.880622] WARNING: at drivers/base/power/main.c:101 device_pm_add+0x94/0xd8()
[    0.880639] Device: ieee80211
[    0.880646] Parentless device registered during a PM transaction (phy1)
[    0.880660] Modules linked in: eeti_ts libertas_sdio libertas pxamci ds2760_battery w1_ds2760 wire
[    0.880754] [<c00493a0>] (unwind_backtrace+0x0/0xec) from [<c0056db0>] (warn_slowpath_common+0x4c/0x7c)
[    0.880793] [<c0056db0>] (warn_slowpath_common+0x4c/0x7c) from [<c0056e74>] (warn_slowpath_fmt+0x30/0x40)
[    0.880829] [<c0056e74>] (warn_slowpath_fmt+0x30/0x40) from [<c01d4cc8>] (device_pm_add+0x94/0xd8)
[    0.880875] [<c01d4cc8>] (device_pm_add+0x94/0xd8) from [<c01ce4dc>] (device_add+0x350/0x510)
[    0.880910] [<c01ce4dc>] (device_add+0x350/0x510) from [<c032d500>] (wiphy_register+0x1ac/0x298)
[    0.881033] [<c032d500>] (wiphy_register+0x1ac/0x298) from [<bf0285dc>] (lbs_cfg_register+0x54/0x9c [libertas])
[    0.881142] [<bf0285dc>] (lbs_cfg_register+0x54/0x9c [libertas]) from [<bf02c228>] (lbs_start_card+0xa0/0x130 [libertas])
[    0.881226] [<bf02c228>] (lbs_start_card+0xa0/0x130 [libertas]) from [<bf040b94>] (if_sdio_probe+0x84c/0x954 [libertas_sdio])
[    0.881276] [<bf040b94>] (if_sdio_probe+0x84c/0x954 [libertas_sdio]) from [<c024fd98>] (sdio_bus_probe+0xcc/0xe8)
[    0.881322] [<c024fd98>] (sdio_bus_probe+0xcc/0xe8) from [<c01d069c>] (driver_probe_device+0xb4/0x198)
[    0.881359] [<c01d069c>] (driver_probe_device+0xb4/0x198) from [<c01cfc08>] (bus_for_each_drv+0x4c/0x8c)
[    0.881396] [<c01cfc08>] (bus_for_each_drv+0x4c/0x8c) from [<c01d08d4>] (device_attach+0x54/0x70)
[    0.881430] [<c01d08d4>] (device_attach+0x54/0x70) from [<c01cfa2c>] (bus_probe_device+0x28/0x50)
[    0.881464] [<c01cfa2c>] (bus_probe_device+0x28/0x50) from [<c01ce510>] (device_add+0x384/0x510)
[    0.881496] [<c01ce510>] (device_add+0x384/0x510) from [<c024fbd4>] (sdio_add_func+0x38/0x54)
[    0.881527] [<c024fbd4>] (sdio_add_func+0x38/0x54) from [<c024f28c>] (mmc_attach_sdio+0x21c/0x2a8)
[    0.881581] [<c024f28c>] (mmc_attach_sdio+0x21c/0x2a8) from [<c024b97c>] (mmc_rescan+0x1ec/0x28c)
[    0.881624] [<c024b97c>] (mmc_rescan+0x1ec/0x28c) from [<c0067a60>] (worker_thread+0x168/0x1f0)
[    0.881667] [<c0067a60>] (worker_thread+0x168/0x1f0) from [<c006abd8>] (kthread+0x78/0x80)
[    0.881720] [<c006abd8>] (kthread+0x78/0x80) from [<c00458bc>] (kernel_thread_exit+0x0/0x8)
[    0.881742] ---[ end trace 919a8d4b06013c07 ]---
[    0.884319] libertas: wlan0: Marvell WLAN 802.11 adapter
[    1.138756] mmc0: card 0001 removed
[    1.139448] PM: suspend of devices complete after 255.035 msecs
[    1.140076] PM: late suspend of devices complete after 0.598 msecs
[    0.000943] PM: early resume of devices complete after 0.634 msecs
[    0.060955] usb usb1: root hub lost power or was reset
[    0.136987] mmc0: new SDIO card at address 0001
[    0.137101] mmc mmc0:0001: parent mmc0 should not be sleeping
[    0.298199] PM: resume of devices complete after 297.118 msecs
[    0.571350] Restarting tasks ... 
[    0.768454] done.
[    1.179764] libertas: 00:19:88:3a:cb:ac, fw 9.70.3p36, cap 0x00000303
[    1.198354] libertas: wlan0: Marvell WLAN 802.11 adapter


Also, the 8686's supply voltage (which is controlled via a regulator in
the pxamci code) drops to zero during the suspend phase.

Here are some questions that I have about this:

* The "Parentless device registered during a PM transaction" looks like
  a bug to me. Note that I added kobject_name(&dev->kobj) to the output
  to get a clue about what's going on.

* The firmware survives the suspend/resume transition and works fine
  after that. I just wonder why, as the voltage was switched off?

* I believe that if we need to keep the power switched on, there should
  be a call to sdio_set_host_pm_flags(MMC_PM_KEEP_POWER) somewhere in
  the libertas_sdio layer, right? How should the pxamci core get to
  know it shouldn't switch off its regulator?

* Should the message about mmc0 which should not be sleeping go away
  once the other issues are solved?


Thanks,
Daniel



From kmpark at infradead.org  Fri Jun  4 08:14:27 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 04 Jun 2010 21:14:27 +0900
Subject: [PATCH] Add maintainer of s5pc100
Message-ID: <20100604121427.GA3190@july>

Add s5pc100 maintainer as Marek.
We already acked from original author, Byungho Min <bhmin at samsung.com>

Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
diff --git a/MAINTAINERS b/MAINTAINERS
index 2652ebc..d85b962 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -944,6 +944,12 @@ W:	http://www.fluff.org/ben/linux/
 S:	Maintained
 F:	arch/arm/mach-s3c6410/
 
+ARM/S5PC100 ARM ARCHITECTURE
+M:	Marek Szyprowski <m.szyprowski at samsung.com>
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
+S:	Maintained
+F:	arch/arm/mach-s5pc100/
+
 ARM/SHMOBILE ARM ARCHITECTURE
 M:	Paul Mundt <lethal at linux-sh.org>
 M:	Magnus Damm <magnus.damm at gmail.com>


From jason77.wang at gmail.com  Fri Jun  4 08:50:03 2010
From: jason77.wang at gmail.com (jason)
Date: Fri, 04 Jun 2010 20:50:03 +0800
Subject: [V2 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <20100604085320.GB25357@pengutronix.de>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100604085320.GB25357@pengutronix.de>
Message-ID: <4C08F67B.5040009@gmail.com>

Sascha Hauer wrote:
> On Thu, Jun 03, 2010 at 08:05:44PM +0800, Jason Wang wrote:
>   
>> +
>> +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
>> +{
>>     
>
> I'm not willing to accept another 3ds_debug board support in the kernel
> given that it's no rocket science to seperate this into another file and
> we still have plenty of time before the next merge window.
> Jason, can you please move this to plat-mxc? I think we could find
> someone else to switch the mx31_3ds support to the generic debug board
> support then.
>
>
> [snip]
>
>   
OK, i will add a common part for debug board in V3.

Thanks,
Jason.
>>  #define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
>>  #define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
>> +#define MX51_PAD_EIM_D25__UART2_CTS	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT4, 0x0, 0, MX51_UART2_PAD_CTRL)
>>  #define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
>> -#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
>> +#define MX51_PAD_EIM_D26__UART2_RTS	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
>>
>>     
<snip>
>
> Urgs, there really is something wrong here.
>
> First of all, this define should be named MX51_PAD_UART3_RXD__GPIO_1_22
> as it describes the pad UART3_RXD in GPIO_1_22 mode. This seems to be
> wrong with many (all?) defines in this file. Amit, you should have read
> the comment ontop of this file which you copied from the i.MX35 part:
>
> /*
>  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
>  * If <padname> or <padmode> refers to a GPIO, it is named
>  * GPIO_<unit>_<num> see also iomux-v3.h
>  */
>
> This should be fixed before doing any other change to this file.
>
> Then Jason, what you are looking for is the following:
>
> #define MX51_PAD_UART3_RXD__UART3_RXD
>
> because you want the UART3_RXD pad in its native mode.
>
> Here is how the defines in this file should look like (modulo bugs):
>
>
> #define MX51_PAD_EIM_D16__GPIO_2_0		(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
> #define MX51_PAD_EIM_D17__GPIO_2_1		(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
> #define MX51_PAD_EIM_D18__GPIO_2_2		(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
> #define MX51_PAD_EIM_D19__GPIO_2_3		(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
> #define MX51_PAD_EIM_D20__GPIO_2_4		(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
>   
Yes, some pin names are wrong. It seems that you have already got a
update for cleanup of those pad names, but it haven't pushed to upstream,
i will cherry pick this update and basing on it add mx51_3ds specific pads.

Thanks,
Jason.
> #define MX51_PAD_EIM_D21__GPIO_2_5		(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
> #define MX51_PAD_EIM_D22__GPIO_2_6		(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
> #define MX51_PAD_EIM_D23__GPIO_2_7		(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
>   
<snip>



From shankar.vk at gmail.com  Fri Jun  4 09:30:20 2010
From: shankar.vk at gmail.com (Uma shankar)
Date: Fri, 4 Jun 2010 19:00:20 +0530
Subject: setting 4-Kb page-size for kernel space in ARM-Cortex
Message-ID: <AANLkTilBfY9tX1ATynkGsnVV6Bn3umx9EzvRtg66LOTa@mail.gmail.com>

Hi,

? ? ? ? ?It is my understanding that ?in ARM, the MMU setting for
kernel VA ?range ( 0xc0000000 onwards excluding the vmalloc and
highmem space )  is set up using the section-sized
mapping ( 1 Mb in size ) , ?as this  range maps to a ?contiguous
physical address range.

I am trying out a memory-checking tool Kmemcheck on Cortex. ? ?This tool has the
requirement that it ?needs to be able to set up ?PTE for each 4 Kb
range of ?kernel address.

So, ?paging_init ( arch/arm/mm/mmu.c ) is modified for this.

But , with this MMU setting, ? the kernel hangs somewhere ?after
freeing init memory. ( "freeing init mem" ?is the
last print I see on console. )

For ?3-level page-table setting of kernel VA, ?do I have to change
somewhere else also ?

? ? ? ? ? ? ?thanks


From marek.vasut at gmail.com  Fri Jun  4 09:29:52 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 4 Jun 2010 15:29:52 +0200
Subject: Is it possible to fix the warning when including wm97xx_batt.h?
In-Reply-To: <AANLkTin1BqWBs7XrBcqmCx8Fg0dOz93C_aBWrtz3DV6L@mail.gmail.com>
References: <AANLkTikX80CrjDVsJfdthnwoPsnXz15mIrr69afZg3af@mail.gmail.com>
	<AANLkTin1BqWBs7XrBcqmCx8Fg0dOz93C_aBWrtz3DV6L@mail.gmail.com>
Message-ID: <201006041529.52215.marek.vasut@gmail.com>

Dne P? 4. ?ervna 2010 09:39:25 Eric Miao napsal(a):
> On Fri, Jun 4, 2010 at 3:37 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> > Hi Marek,
> > 
> > Regard the annoying warnings below, is it currently possible not to
> > include wm97xx_batt.h and include wm97xx.h instead?
> 
> Ignore this mail, I just found your patch for this issue. Sorry.

Hehe ... I'm reading your mind in advance, fear ;-)


From shiraz.hashim at st.com  Fri Jun  4 09:55:08 2010
From: shiraz.hashim at st.com (Shiraz HASHIM)
Date: Fri, 04 Jun 2010 19:25:08 +0530
Subject: facing undefined inconsistent cache issues on cortex-a9
In-Reply-To: <13B9B4C6EF24D648824FF11BE896716203BB37005A@dlee02.ent.ti.com>
References: <4BF9F5FB.6020306@st.com>	<EAF47CD23C76F840A9E7FCE10091EFAB02C57001F3@dbde02.ent.ti.com>	<4BFBBD83.5080302@st.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C57A5FC6@dbde02.ent.ti.com>
	<13B9B4C6EF24D648824FF11BE896716203BB37005A@dlee02.ent.ti.com>
Message-ID: <4C0905BC.1090301@st.com>

Hello Woodruff,

On 5/26/2010 12:27 AM, Woodruff, Richard wrote:
> 
>> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-kernel-
>> bounces at lists.infradead.org] On Behalf Of Shilimkar, Santosh
> 
>>>> Does this work if disable L1D as well on the processor you are running
>> Linux ??
>>>>
>>> If we disable the L1 DCache we are never able to boot.
>>> But this might be a different problem.
>>>
>>> If we disable ICache and leave DCache on it is much more stable, and
>>> I think it might be related to timing issue in the data path.
>>>
>> For me, it seems that Cache isn't invalidated properly which leads to this
>> issue.
>> May be you can report the complete crash-log which can give more idea on the
>> issue.
> 
> If you are unable to boot with dcache off then maybe your memory controller or memory part has timing issues.  Cache on will trigger burst accesses using different timings.  Such an early failure is more likely an issue outside of the arm unless you are doing something really odd.

thanks for your inputs. We have some updates in this regard.
In our architecture we have 2 ports coming out of the A9SM (multi core cortex)
block to the interconnect matrix and the transfers are distributed between them.

When we used the address filtering option of SCU to divide and mutually exclude
the traffic between port0 and port1 of A9SM(multi core cortex) block. Like, 
assigning 1 half of the address space to port 1 and rest goes through port0.
This solved the problem with the same set of cache and other system
configurations.
We are not using L2 cache and it is kept disabled. The SCU also is only used for
address filtering and its synchronisation function is disabled (as we are not
bringing up the second core)
Now, we are not able to understand what it means. Do we need to divide the
traffic between ports as described and it is normal. Or there is some problem in
the way the transfers are handled in the system.

regards
Shiraz


From jason77.wang at gmail.com  Fri Jun  4 10:09:21 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:09:21 +0800
Subject: [V3 0/7]Add i.MX51 3-stack board support
Message-ID: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>

I don't know why 2 patches([patch 2/3] and [patch 3/3]) are lost in
the V2 review.
In V3, i fix all comments both in V1 and V2.

Big diffs:
1) the number of patches increases from 3 to 7, because i add 1 3ds
common debug board patch, 2 iomux pad rename and update patches and
1 revert mx31_3ds debug board relating stuffs patch.

2) Though the smsc911x_platform_config is a little bit different
between mx31_3ds and mx51_3ds originally,  when using the common
configuration in the mxc debug board, they all works fine. I have
validated these two BSPs through mounting NFS rootfs.

3) the patch [3/7] is a rename and cleanup of iomux pad definition,
i don't know if this update has been merged, if so, please drop
it.





From amit.kucheria at canonical.com  Fri Jun  4 10:09:59 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Fri, 4 Jun 2010 17:09:59 +0300
Subject: [PATCH] mxc: Fix pad names for imx51
In-Reply-To: <20100604105347.GA2982@matterhorn.lan>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100604085320.GB25357@pengutronix.de>
	<20100604105347.GA2982@matterhorn.lan>
Message-ID: <20100604140959.GB2982@matterhorn.lan>

On 10 Jun 04, Amit Kucheria wrote:
> On 10 Jun 04, Sascha Hauer wrote:
> > On Thu, Jun 03, 2010 at 08:05:44PM +0800, Jason Wang wrote:
> > >  
> > > -#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
> > > -#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
> > > +#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
> > > +#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_UART3_PAD_CTRL)
> > 
> > Urgs, there really is something wrong here.
> > 
> > First of all, this define should be named MX51_PAD_UART3_RXD__GPIO_1_22
> > as it describes the pad UART3_RXD in GPIO_1_22 mode. This seems to be
> > wrong with many (all?) defines in this file. Amit, you should have read
> > the comment ontop of this file which you copied from the i.MX35 part:
> 
> I'll admit that I was not completely conversant with the naming scheme then.
> All the GPIO-related names have been reversed. The others seem fine.
> 
> > /*
> >  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
> >  * If <padname> or <padmode> refers to a GPIO, it is named
> >  * GPIO_<unit>_<num> see also iomux-v3.h
> >  */
> 
> There was a comment below this:
> /*
>  * FIXME: This was converted using scripts from existing Freescale code to
>  * this form used upstream. Need to verify the name format.
>  */
> 
> I obviously reversed the naming for all the GPIO pads.
> 
> > This should be fixed before doing any other change to this file.
> 
> I'm preparing a patch now.
> 

Please find the patch attached.

You can see the output of diff without the whitespace changes here:
http://paste.ubuntu.com/444628/



From amit.kucheria at canonical.com  Fri Jun  4 09:50:27 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Fri, 4 Jun 2010 16:50:27 +0300
Subject: [PATCH] mxc: Fix pad names for imx51
Message-ID: <00a83837915e2056367b09dfc322ced601e67658.1275659667.git.amit.kucheria@canonical.com>

The pads capable of being used as GPIOs had their pad-name and mode-name
switched. Also fix the following:

- Whitespace fixes
- Replace IOMUX_CONFIG_ALTn with 'n'

Signed-off-by: Amit Kucheria <amit.kucheria at canonical.com>
---
 arch/arm/mach-mx5/board-mx51_babbage.c      |    2 +-
 arch/arm/plat-mxc/include/mach/iomux-mx51.h |  533 +++++++++++++--------------
 2 files changed, 252 insertions(+), 283 deletions(-)

diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index ed885f9..4f96d9c 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -78,7 +78,7 @@ static struct pad_desc mx51babbage_pads[] = {
 	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 
 	/* USB HUB reset line*/
-	MX51_PAD_GPIO_1_7__GPIO1_7,
+	MX51_PAD_GPIO_1_7__GPIO_1_7,
 };
 
 /* Serial ports */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index ab0f95d..e8648bc 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -27,8 +27,8 @@ typedef enum iomux_config {
 	IOMUX_CONFIG_ALT5,
 	IOMUX_CONFIG_ALT6,
 	IOMUX_CONFIG_ALT7,
-	IOMUX_CONFIG_GPIO,	/* added to help user use GPIO mode */
-	IOMUX_CONFIG_SION = 0x1 << 4,	/* LOOPBACK:MUX SION bit */
+	IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
+	IOMUX_CONFIG_SION = 0x1 << 4,   /* LOOPBACK:MUX SION bit */
 } iomux_pin_cfg_t;
 
 /* Pad control groupings */
@@ -50,285 +50,254 @@ typedef enum iomux_config {
  * GPIO_<unit>_<num> see also iomux-v3.h
  */
 
-/*
- * FIXME: This was converted using scripts from existing Freescale code to
- * this form used upstream. Need to verify the name format.
- */
-
-/*						PAD      MUX   ALT INPSE PATH PADCTRL */
-
-#define MX51_PAD_GPIO_2_0__EIM_D16	IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_1__EIM_D17	IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_2__EIM_D18	IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_3__EIM_D19	IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_4__EIM_D20	IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_5__EIM_D21	IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO_2_5	IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_6__EIM_D22	IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_7__EIM_D23	IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
-
-/* Babbage UART3 */
-#define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
-
-#define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30	IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31	IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_10__EIM_A16	IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_11__EIM_A17	IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_12__EIM_A18	IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_13__EIM_A19	IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_14__EIM_A20	IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_15__EIM_A21	IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_16__EIM_A22	IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_17__EIM_A23	IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_18__EIM_A24	IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_19__EIM_A25	IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_20__EIM_A26	IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_21__EIM_A27	IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0	IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1	IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_22__EIM_EB2	IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_23__EIM_EB3	IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_24__EIM_OE	IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_25__EIM_CS0	IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_26__EIM_CS1	IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_27__EIM_CS2	IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_28__EIM_CS3	IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_29__EIM_CS4	IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_30__EIM_CS5	IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_31__EIM_DTACK	IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_3_1__EIM_LBA	IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__EIM_CRE	IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1	IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__NANDF_WE_B	IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__NANDF_RE_B	IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__NANDF_ALE	IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__NANDF_CLE	IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__NANDF_WP_B	IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__NANDF_RB0	IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_9__NANDF_RB1	IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_10__NANDF_RB2	IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_11__NANDF_RB3	IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__GPIO_NAND	IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
-/* REVISIT: Not sure of these values
-
-  #define MX51_PAD_GPIO_1___NANDF_RB4	IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_13__NANDF_RB5	IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_15__NANDF_RB7	IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-*/
-#define MX51_PAD_GPIO_3_14__NANDF_RB6	IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_16__NANDF_CS0	IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_17__NANDF_CS1	IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_18__NANDF_CS2	IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_19__NANDF_CS3	IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_20__NANDF_CS4	IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_21__NANDF_CS5	IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_22__NANDF_CS6	IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_23__NANDF_CS7	IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT	IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_25__NANDF_D15	IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_26__NANDF_D14	IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_27__NANDF_D13	IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_28__NANDF_D12	IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_29__NANDF_D11	IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_30__NANDF_D10	IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_31__NANDF_D9	IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_0__NANDF_D8	IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_1__NANDF_D7	IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_2__NANDF_D6	IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_3__NANDF_D5	IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_4__NANDF_D4	IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_5__NANDF_D3	IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_6__NANDF_D2	IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_7__NANDF_D1	IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_8__NANDF_D0	IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__CSI1_D8	IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_13__CSI1_D9	IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10	IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11	IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12	IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13	IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14	IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15	IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16	IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17	IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18	IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19	IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC	IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC	IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK	IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK	IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PKE0__CSI1_PKE0	IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_9__CSI2_D12	IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_10__CSI2_D13	IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D14	IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D15	IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D16	IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D17	IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D18	IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D19	IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_13__CSI2_VSYNC	IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_14__CSI2_HSYNC	IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK	IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PKE0__CSI2_PKE0	IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_16__I2C1_CLK	IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_17__I2C1_DAT	IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD	IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD	IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_20__AUD3_BB_CK	IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_21__AUD3_BB_FS	IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_22__CSPI1_MOSI	IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_23__CSPI1_MISO	IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_24__CSPI1_SS0	IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_25__CSPI1_SS1	IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_26__CSPI1_RDY	IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_27__CSPI1_SCLK	IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
-
-/* Babbage UART1 */
-#define MX51_PAD_UART1_RXD__UART1_RXD	IOMUX_PAD(0x618, 0x228,	IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_TXD__UART1_TXD	IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_RTS__UART1_RTS	IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS	IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
-
-/* Babbage UART2 */
-#define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
-
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_24__OWIRE_LINE	IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0	IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1	IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2	IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3	IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0	IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1	IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2	IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3	IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4	IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5	IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK	IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR	IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO_1_27	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT	IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_GPIO_3_0__DI1_PIN11	IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_1__DI1_PIN12	IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__DI1_PIN13	IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__DI1_D0_CS	IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__DI1_D1_CS	IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN	IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO	IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK	IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS	IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0	IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1	IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2	IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3	IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4	IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5	IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6	IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7	IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8	IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9	IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3	IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2	IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP1__DI_GP1	IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DI_GP2	IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DI_GP3	IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4	IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2	IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3	IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI_GP4	IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0	IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1	IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2	IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3	IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4	IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5	IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_19__DISP2_DAT6	IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_29__DISP2_DAT7	IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_30__DISP2_DAT8	IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_31__DISP2_DAT9	IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD	IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK	IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0	IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1	IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2	IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3	IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_0__GPIO1_0	IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_1__GPIO1_1	IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD	IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK	IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0	IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1	IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2	IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3	IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_2__GPIO1_2	IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_3__GPIO1_3	IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_4__GPIO1_4	IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_5__GPIO1_5	IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_7__GPIO1_7	IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_8__GPIO1_8	IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
-						(PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
-#define MX51_PAD_GPIO_1_9__GPIO1_9	IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
-
-/* EIM */
-#define MX51_PAD_EIM_DA0__EIM_DA0	IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1	IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2	IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3	IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4	IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5	IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6	IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7	IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_DA8__EIM_DA8	IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9	IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10	IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11	IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12	IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13	IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14	IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15	IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+/*							  PAD    MUX   ALT INPSE PATH PADCTRL */
+#define MX51_PAD_EIM_DA0__EIM_DA0		IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA1__EIM_DA1		IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA2__EIM_DA2		IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA3__EIM_DA3		IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA4__EIM_DA4		IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA5__EIM_DA5		IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA6__EIM_DA6		IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA7__EIM_DA7		IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA8__EIM_DA8		IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA9__EIM_DA9		IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA10__EIM_DA10		IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA11__EIM_DA11		IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA12__EIM_DA12		IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA13__EIM_DA13		IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA14__EIM_DA14		IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA15__EIM_DA15		IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__GPIO_2_0              IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__GPIO_2_1              IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__GPIO_2_2              IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__GPIO_2_3              IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__GPIO_2_4              IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO_2_5		IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__GPIO_2_6              IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__GPIO_2_7              IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__GPIO_2_10             IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__GPIO_2_11             IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__GPIO_2_12             IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__GPIO_2_13             IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO_2_14             IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__GPIO_2_15             IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__GPIO_2_16             IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__GPIO_2_17             IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__GPIO_2_18             IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__GPIO_2_19             IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__GPIO_2_20             IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__GPIO_2_21             IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__GPIO_2_22             IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPIO_2_23             IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__GPIO_2_24              IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__GPIO_2_25             IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__GPIO_2_26             IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__GPIO_2_27             IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__GPIO_2_28             IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__GPIO_2_29             IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__GPIO_2_30             IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__GPIO_2_31           IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__GPIO_3_1              IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__GPIO_3_2              IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4D0, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__GPIO_3_3           IOMUX_PAD(0x4E4, 0x108, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__GPIO_3_4           IOMUX_PAD(0x4E8, 0x10C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__GPIO_3_5            IOMUX_PAD(0x4EC, 0x110, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__GPIO_3_6            IOMUX_PAD(0x4F0, 0x114, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__GPIO_3_7           IOMUX_PAD(0x4F4, 0x118, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__GPIO_3_12           IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__GPIO_3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__GPIO_3_17           IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__GPIO_3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__GPIO_3_19           IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__GPIO_3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__GPIO_3_21           IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__GPIO_3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__GPIO_3_23           IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__GPIO_3_29           IOMUX_PAD(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__GPIO_3_30           IOMUX_PAD(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__GPIO_3_31            IOMUX_PAD(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__GPIO_4_0             IOMUX_PAD(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__GPIO_4_1             IOMUX_PAD(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__GPIO_4_2             IOMUX_PAD(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__GPIO_4_3             IOMUX_PAD(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__GPIO_4_4             IOMUX_PAD(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__GPIO_4_5             IOMUX_PAD(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__GPIO_4_6             IOMUX_PAD(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__GPIO_4_7             IOMUX_PAD(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__GPIO_4_8             IOMUX_PAD(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__GPIO_3_12             IOMUX_PAD(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__GPIO_3_13             IOMUX_PAD(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5B4, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5B8, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PKE0__CSI1_PKE0           IOMUX_PAD(0x860, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__GPIO_4_9             IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__GPIO_4_10            IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__GPIO_4_11            IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__GPIO_4_12            IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__GPIO_4_11            IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__GPIO_4_12            IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__GPIO_4_11            IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__GPIO_4_12            IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__GPIO_4_13          IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__GPIO_4_14          IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15         IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__GPIO_4_16            IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__GPIO_4_17            IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18         IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19         IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__GPIO_4_20          IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__GPIO_4_21          IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__GPIO_4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__GPIO_4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__GPIO_4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__GPIO_4_25           IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__GPIO_4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO_1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO_1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__GPIO_1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO_1_27           IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__GPIO_3_0            IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP1__DI_GP1                 IOMUX_PAD(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DI_GP2                 IOMUX_PAD(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DI_GP3                 IOMUX_PAD(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI_GP4                 IOMUX_PAD(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__GPIO_1_19          IOMUX_PAD(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__GPIO_1_29          IOMUX_PAD(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__GPIO_1_30          IOMUX_PAD(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__GPIO_1_31          IOMUX_PAD(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_0__GPIO_1_0		IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_1__GPIO_1_1		IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
 
 #endif /* __MACH_IOMUX_MX51_H__ */
-- 
1.7.0.4



-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------


From jason77.wang at gmail.com  Fri Jun  4 10:32:50 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:32:50 +0800
Subject: [PATCH V3 0/7]Add i.MX51 3-stack board support
Message-ID: <1275661977-8077-1-git-send-email-jason77.wang@gmail.com>

It seems that it is failed when sending my V3 patches, now
resend once more.
 
I don't know why 2 patches([patch 2/3] and [patch 3/3]) are lost in
the V2 review.
In V3, i fix all comments both in V1 and V2.

Big diffs:
1) the number of patches increases from 3 to 7, because i add 1 3ds
common debug board patch, 2 iomux pad rename and update patches and
1 revert mx31_3ds debug board relating stuffs patch.

2) Though the smsc911x_platform_config is a little bit different
between mx31_3ds and mx51_3ds originally,  when using the common
configuration in the mxc debug board, they all works fine. I have
validated these two BSPs through mounting NFS rootfs.

3) the patch [3/7] is a rename and cleanup of iomux pad definition,
i don't know if this update has been merged, if so, please drop
it.





From jason77.wang at gmail.com  Fri Jun  4 10:32:51 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:32:51 +0800
Subject: [PATCH V3 1/7] mxc: add common debug board for 3-stack platforms
In-Reply-To: <1275661977-8077-1-git-send-email-jason77.wang@gmail.com>
References: <1275661977-8077-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275661977-8077-2-git-send-email-jason77.wang@gmail.com>

The debug board is little different for all mxc 3-stack(PDK)
platforms, it is possible here to add a common implementation to
support this board.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/Kconfig                        |   11 ++
 arch/arm/plat-mxc/Makefile                       |    1 +
 arch/arm/plat-mxc/cpld_debugboard.c              |  161 ++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/cpld_debugboard.h |   60 ++++++++
 4 files changed, 233 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-mxc/cpld_debugboard.c
 create mode 100644 arch/arm/plat-mxc/include/mach/cpld_debugboard.h

diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 7f7ad6f..8bf917e 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -81,6 +81,17 @@ config MXC_PWM
 	help
 	  Enable support for the i.MX PWM controller(s).
 
+config MXC_DEBUG_BOARD
+	bool "Enable MXC debug board(for 3-stack)"
+	help
+	  The debug board is an integral part of the MXC 3-stack(PDK)
+	  platforms, it can be attached or removed from the peripheral
+	  board. On debug board, several debug devices(ethernet, UART,
+	  buttons, LEDs and JTAG) are implemented. Between the MCU and
+	  these devices, a CPLD is added as a bridge which performs
+	  data/address de-multiplexing and decode, signal level shift,
+	  interrupt control and various board functions.
+
 config MXC_ULPI
 	bool
 
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 895bc3c..b9e8c6f 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
+obj-$(CONFIG_MXC_DEBUG_BOARD) += cpld_debugboard.o
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
diff --git a/arch/arm/plat-mxc/cpld_debugboard.c b/arch/arm/plat-mxc/cpld_debugboard.c
new file mode 100644
index 0000000..0554fa0
--- /dev/null
+++ b/arch/arm/plat-mxc/cpld_debugboard.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <mach/hardware.h>
+#include <mach/cpld_debugboard.h>
+
+static void __iomem *brd_io;
+static void expio_ack_irq(u32 irq);
+
+static struct resource smsc911x_resources[] = {
+	{
+		.flags = IORESOURCE_MEM,
+	} , {
+		.start = EXPIO_INT_ENET,
+		.end = EXPIO_INT_ENET,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct smsc911x_platform_config smsc911x_config = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+};
+
+struct platform_device smsc_lan9217_device = {
+	.name = "smsc911x",
+	.id = 0,
+	.dev = {
+		.platform_data = &smsc911x_config,
+	},
+	.num_resources = ARRAY_SIZE(smsc911x_resources),
+	.resource = smsc911x_resources,
+};
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+	u32 imr_val;
+	u32 int_valid;
+	u32 expio_irq;
+
+	desc->chip->mask(irq);	/* irq = gpio irq number */
+
+	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
+	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
+
+	expio_irq = MXC_BOARD_IRQ_START;
+	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+		struct irq_desc *d;
+		if ((int_valid & 1) == 0)
+			continue;
+		d = irq_desc + expio_irq;
+		if (unlikely(!(d->handle_irq)))
+			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
+		else
+			d->handle_irq(expio_irq, d);
+	}
+
+	desc->chip->ack(irq);
+	desc->chip->unmask(irq);
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * Irq is an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg |= (1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static void expio_ack_irq(u32 irq)
+{
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	expio_mask_irq(irq);
+}
+
+static void expio_unmask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg &= ~(1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+	.ack = expio_ack_irq,
+	.mask = expio_mask_irq,
+	.unmask = expio_unmask_irq,
+};
+
+int __init mxc_expio_init(u32 base, u32 p_irq)
+{
+	int i;
+
+	brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
+	if (brd_io == NULL)
+		return -ENOMEM;
+
+	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
+		pr_info("3-Stack Debug board not detected\n");
+		iounmap(brd_io);
+		brd_io = NULL;
+		return -ENODEV;
+	}
+
+	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
+		readw(brd_io + CPLD_CODE_VER_REG));
+
+	smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
+	smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
+
+	/*
+	 * Configure INT line as GPIO input
+	 */
+	gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
+	gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
+
+	/* disable the interrupt and clear the status */
+	__raw_writew(0, brd_io + INTR_MASK_REG);
+	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
+	for (i = MXC_EXP_IO_BASE;
+	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
+		set_irq_chip(i, &expio_irq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+	set_irq_type(p_irq, IRQF_TRIGGER_LOW);
+	set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
+
+	return 0;
+}
diff --git a/arch/arm/plat-mxc/include/mach/cpld_debugboard.h b/arch/arm/plat-mxc/include/mach/cpld_debugboard.h
new file mode 100644
index 0000000..a1422d2
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/cpld_debugboard.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_CPLD_DB_H__
+#define __ASM_ARCH_MXC_CPLD_DB_H__
+
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR(n)	(n + 0x0)
+/* External UART */
+#define UARTA_BASE_ADDR(n)	(n + 0x8000)
+#define UARTB_BASE_ADDR(n)	(n + 0x10000)
+
+#define BOARD_IO_ADDR(n)	(n + 0x20000)
+/* LED switchs */
+#define LED_SWITCH_REG		0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG	0x08
+/* status, interrupt */
+#define INTR_STATUS_REG	0x10
+#define INTR_MASK_REG		0x38
+#define INTR_RESET_REG		0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG	0x40
+#define MAGIC_NUMBER2_REG	0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG	0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG	0x58
+/* module reset register*/
+#define MODULE_RESET_REG	0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG	0x68
+
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_GPIO(irq)	((irq) - MXC_INTERNAL_IRQS)
+
+#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
+#define MXC_MAX_EXP_IO_LINES	16
+
+/* interrupts like external uart , external ethernet etc*/
+#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
+#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
+#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
+#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
+#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
+
+extern struct platform_device smsc_lan9217_device;
+
+int __init mxc_expio_init(u32 base, u32 p_irq);
+
+#endif /* __ASM_ARCH_MXC_CPLD_DB_H__ */
-- 
1.5.6.5



From jason77.wang at gmail.com  Fri Jun  4 10:32:52 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:32:52 +0800
Subject: [PATCH V3 2/7] mxc/iomux: add GPIO bank offset for iomux v3 platforms
In-Reply-To: <1275661977-8077-2-git-send-email-jason77.wang@gmail.com>
References: <1275661977-8077-1-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275661977-8077-3-git-send-email-jason77.wang@gmail.com>

These GPIO bank offsets are useful when define a gpio number.
E.G. when GPIO PORTC pin 6 is used for irq request pin of external
expanding device, we can define it like:
  #define EXP_PARENT_IRQ_PIN (GPIO_PORTC + 6)

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/include/mach/iomux-v3.h |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index f2f73d3..0880a4a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -89,6 +89,21 @@ struct pad_desc {
 #define PAD_CTL_SRE_FAST		(1 << 0)
 #define PAD_CTL_SRE_SLOW		(0 << 0)
 
+
+#define MX51_NUM_GPIO_PORT	4
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA	(0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB	(1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC	(2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD	(3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE	(4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF	(5 << GPIO_PORT_SHIFT)
+
 /*
  * setups a single pad in the iomuxer
  */
-- 
1.5.6.5



From jason77.wang at gmail.com  Fri Jun  4 10:32:53 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:32:53 +0800
Subject: [PATCH V3 3/7] mx51/iomux: fix some pad names and make some cleanups
In-Reply-To: <1275661977-8077-3-git-send-email-jason77.wang@gmail.com>
References: <1275661977-8077-1-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-2-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-3-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275661977-8077-4-git-send-email-jason77.wang@gmail.com>

Fix some pad names according to the naming convention and make some
cleanups for vertical lineup.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/include/mach/iomux-mx51.h |  507 ++++++++++++--------------
 1 files changed, 234 insertions(+), 273 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index ab0f95d..df9ecdf 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -57,278 +57,239 @@ typedef enum iomux_config {
 
 /*						PAD      MUX   ALT INPSE PATH PADCTRL */
 
-#define MX51_PAD_GPIO_2_0__EIM_D16	IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_1__EIM_D17	IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_2__EIM_D18	IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_3__EIM_D19	IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_4__EIM_D20	IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_5__EIM_D21	IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO_2_5	IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_6__EIM_D22	IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_7__EIM_D23	IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
-
-/* Babbage UART3 */
-#define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
-
-#define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30	IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31	IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_10__EIM_A16	IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_11__EIM_A17	IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_12__EIM_A18	IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_13__EIM_A19	IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_14__EIM_A20	IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_15__EIM_A21	IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_16__EIM_A22	IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_17__EIM_A23	IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_18__EIM_A24	IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_19__EIM_A25	IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_20__EIM_A26	IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_21__EIM_A27	IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0	IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1	IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_22__EIM_EB2	IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_23__EIM_EB3	IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_24__EIM_OE	IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_25__EIM_CS0	IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_26__EIM_CS1	IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_27__EIM_CS2	IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_28__EIM_CS3	IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_29__EIM_CS4	IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_30__EIM_CS5	IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_31__EIM_DTACK	IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_3_1__EIM_LBA	IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__EIM_CRE	IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1	IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__NANDF_WE_B	IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__NANDF_RE_B	IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__NANDF_ALE	IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__NANDF_CLE	IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__NANDF_WP_B	IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__NANDF_RB0	IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_9__NANDF_RB1	IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_10__NANDF_RB2	IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_11__NANDF_RB3	IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__GPIO_NAND	IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
-/* REVISIT: Not sure of these values
-
-  #define MX51_PAD_GPIO_1___NANDF_RB4	IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_13__NANDF_RB5	IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_15__NANDF_RB7	IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-*/
-#define MX51_PAD_GPIO_3_14__NANDF_RB6	IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_16__NANDF_CS0	IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_17__NANDF_CS1	IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_18__NANDF_CS2	IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_19__NANDF_CS3	IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_20__NANDF_CS4	IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_21__NANDF_CS5	IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_22__NANDF_CS6	IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_23__NANDF_CS7	IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT	IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_25__NANDF_D15	IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_26__NANDF_D14	IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_27__NANDF_D13	IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_28__NANDF_D12	IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_29__NANDF_D11	IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_30__NANDF_D10	IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_31__NANDF_D9	IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_0__NANDF_D8	IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_1__NANDF_D7	IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_2__NANDF_D6	IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_3__NANDF_D5	IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_4__NANDF_D4	IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_5__NANDF_D3	IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_6__NANDF_D2	IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_7__NANDF_D1	IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_8__NANDF_D0	IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__CSI1_D8	IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_13__CSI1_D9	IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10	IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11	IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12	IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13	IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14	IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15	IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16	IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17	IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18	IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19	IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC	IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC	IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK	IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK	IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PKE0__CSI1_PKE0	IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_9__CSI2_D12	IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_10__CSI2_D13	IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D14	IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D15	IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D16	IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D17	IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D18	IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D19	IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_13__CSI2_VSYNC	IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_14__CSI2_HSYNC	IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK	IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PKE0__CSI2_PKE0	IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_16__I2C1_CLK	IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_17__I2C1_DAT	IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD	IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD	IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_20__AUD3_BB_CK	IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_21__AUD3_BB_FS	IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_22__CSPI1_MOSI	IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_23__CSPI1_MISO	IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_24__CSPI1_SS0	IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_25__CSPI1_SS1	IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_26__CSPI1_RDY	IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_27__CSPI1_SCLK	IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
-
-/* Babbage UART1 */
-#define MX51_PAD_UART1_RXD__UART1_RXD	IOMUX_PAD(0x618, 0x228,	IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_TXD__UART1_TXD	IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_RTS__UART1_RTS	IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS	IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
-
-/* Babbage UART2 */
-#define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
-
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_24__OWIRE_LINE	IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0	IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1	IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2	IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3	IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0	IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1	IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2	IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3	IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4	IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5	IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK	IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR	IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO_1_27	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT	IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_GPIO_3_0__DI1_PIN11	IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_1__DI1_PIN12	IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__DI1_PIN13	IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__DI1_D0_CS	IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__DI1_D1_CS	IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN	IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO	IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK	IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS	IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0	IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1	IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2	IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3	IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4	IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5	IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6	IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7	IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8	IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9	IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3	IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2	IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP1__DI_GP1	IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DI_GP2	IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DI_GP3	IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4	IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2	IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3	IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI_GP4	IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0	IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1	IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2	IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3	IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4	IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5	IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_19__DISP2_DAT6	IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_29__DISP2_DAT7	IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_30__DISP2_DAT8	IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_31__DISP2_DAT9	IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD	IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK	IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0	IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1	IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2	IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3	IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_0__GPIO1_0	IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_1__GPIO1_1	IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD	IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK	IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0	IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1	IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2	IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3	IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_2__GPIO1_2	IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_3__GPIO1_3	IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_4__GPIO1_4	IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_5__GPIO1_5	IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_7__GPIO1_7	IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_8__GPIO1_8	IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
-						(PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
-#define MX51_PAD_GPIO_1_9__GPIO1_9	IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
-
-/* EIM */
-#define MX51_PAD_EIM_DA0__EIM_DA0	IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1	IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2	IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3	IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4	IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5	IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6	IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7	IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_DA8__EIM_DA8	IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9	IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10	IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11	IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12	IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13	IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14	IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15	IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__GPIO_2_0		IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__GPIO_2_1		IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__GPIO_2_2		IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__GPIO_2_3		IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__GPIO_2_4		IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO_2_5		IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__GPIO_2_6		IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__GPIO_2_7		IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__UART3_CTS		IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART3_RXD		IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART3_TXD		IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS		IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28		IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29		IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30		IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31		IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__GPIO_2_10		IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__GPIO_2_11		IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__GPIO_2_12		IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__GPIO_2_13		IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO_2_14		IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__GPIO_2_15		IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__GPIO_2_16		IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__GPIO_2_17		IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__GPIO_2_18		IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__GPIO_2_19		IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__GPIO_2_20		IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__GPIO_2_21		IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0		IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1		IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__GPIO_2_22		IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPIO_2_23		IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__GPIO_2_24		IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__GPIO_2_25		IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__GPIO_2_26		IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__GPIO_2_27		IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__GPIO_2_28		IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__GPIO_2_29		IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__GPIO_2_30		IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__GPIO_2_31		IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__GPIO_3_1		IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__GPIO_3_2		IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1		IOMUX_PAD(0x4D0, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__GPIO_3_3		IOMUX_PAD(0x4E4, 0x108, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__GPIO_3_4		IOMUX_PAD(0x4E8, 0x10C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__GPIO_3_5		IOMUX_PAD(0x4EC, 0x110, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__GPIO_3_6		IOMUX_PAD(0x4F0, 0x114, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__GPIO_3_7		IOMUX_PAD(0x4F4, 0x118, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__GPIO_3_8		IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPIO_3_9		IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__GPIO_3_10		IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__GPIO_3_11		IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__GPIO_3_12		IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB6__GPIO_3_14		IOMUX_PAD(0x5DC, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__GPIO_3_16		IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__GPIO_3_17		IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__GPIO_3_18		IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__GPIO_3_19		IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__GPIO_3_20		IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__GPIO_3_21		IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__GPIO_3_22		IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__GPIO_3_23		IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24	IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__GPIO_3_25		IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__GPIO_3_26		IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__GPIO_3_27		IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__GPIO_3_28		IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__GPIO_3_29		IOMUX_PAD(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__GPIO_3_30		IOMUX_PAD(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__GPIO_3_31		IOMUX_PAD(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__GPIO_4_0		IOMUX_PAD(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__GPIO_4_1		IOMUX_PAD(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__GPIO_4_2		IOMUX_PAD(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__GPIO_4_3		IOMUX_PAD(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__GPIO_4_4		IOMUX_PAD(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__GPIO_4_5		IOMUX_PAD(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__GPIO_4_6		IOMUX_PAD(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__GPIO_4_7		IOMUX_PAD(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__GPIO_4_8		IOMUX_PAD(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__GPIO_3_12		IOMUX_PAD(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__GPIO_3_13		IOMUX_PAD(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10		IOMUX_PAD(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11		IOMUX_PAD(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12		IOMUX_PAD(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13		IOMUX_PAD(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14		IOMUX_PAD(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15		IOMUX_PAD(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16		IOMUX_PAD(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17		IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18		IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19		IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC		IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC		IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK	IOMUX_PAD(0x5B4, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK		IOMUX_PAD(0x5B8, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PKE0__CSI1_PKE0		IOMUX_PAD(0x860, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__GPIO_4_9		IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__GPIO_4_10		IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__GPIO_4_11		IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__GPIO_4_12		IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__GPIO_4_11		IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__GPIO_4_12		IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__GPIO_4_11		IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__GPIO_4_12		IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__GPIO_4_13		IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__GPIO_4_14		IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15		IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PKE0__CSI2_PKE0		IOMUX_PAD(0x81C, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__GPIO_4_16		IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__GPIO_4_17		IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18		IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19		IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__GPIO_4_20		IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__GPIO_4_21		IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__GPIO_4_22		IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__GPIO_4_23		IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__GPIO_4_24		IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__GPIO_4_25		IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__GPIO_4_26		IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27		IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD		IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_TXD__UART1_TXD		IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_RTS__UART1_RTS		IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS		IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD		IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD		IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO_1_22		IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO_1_23		IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__GPIO_1_24		IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0		IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1		IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2		IOMUX_PAD(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3		IOMUX_PAD(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0		IOMUX_PAD(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1		IOMUX_PAD(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2		IOMUX_PAD(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3		IOMUX_PAD(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4		IOMUX_PAD(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5		IOMUX_PAD(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK		IOMUX_PAD(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR		IOMUX_PAD(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP		IOMUX_PAD(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO_1_27		IOMUX_PAD(0x680, 0x280, 2, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT		IOMUX_PAD(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	IOMUX_PAD(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	IOMUX_PAD(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	IOMUX_PAD(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	IOMUX_PAD(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	IOMUX_PAD(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	IOMUX_PAD(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__GPIO_3_0		IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO_3_1		IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO_3_2		IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO_3_3		IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO_3_4		IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5	IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6	IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7	IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8	IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0		IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1		IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2		IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3		IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4		IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5		IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6		IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7		IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8		IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9		IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	IOMUX_PAD(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	IOMUX_PAD(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	IOMUX_PAD(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	IOMUX_PAD(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	IOMUX_PAD(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	IOMUX_PAD(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	IOMUX_PAD(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	IOMUX_PAD(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	IOMUX_PAD(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	IOMUX_PAD(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	IOMUX_PAD(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3		IOMUX_PAD(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2		IOMUX_PAD(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP1__DI_GP1			IOMUX_PAD(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DI_GP2			IOMUX_PAD(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DI_GP3			IOMUX_PAD(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4		IOMUX_PAD(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2		IOMUX_PAD(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3		IOMUX_PAD(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	IOMUX_PAD(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI_GP4			IOMUX_PAD(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0		IOMUX_PAD(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1		IOMUX_PAD(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2		IOMUX_PAD(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3		IOMUX_PAD(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4		IOMUX_PAD(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5		IOMUX_PAD(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__GPIO_1_19		IOMUX_PAD(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__GPIO_1_29		IOMUX_PAD(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__GPIO_1_30		IOMUX_PAD(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__GPIO_1_31		IOMUX_PAD(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	IOMUX_PAD(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	IOMUX_PAD(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	IOMUX_PAD(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	IOMUX_PAD(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD		IOMUX_PAD(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK		IOMUX_PAD(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0		IOMUX_PAD(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1		IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2		IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3		IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__GPIO_1_0		IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__GPIO_1_1		IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD		IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK		IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0		IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1		IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2		IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3		IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
 
 #endif /* __MACH_IOMUX_MX51_H__ */
-- 
1.5.6.5



From jason77.wang at gmail.com  Fri Jun  4 10:32:54 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:32:54 +0800
Subject: [PATCH V3 4/7] mx51/iomux: add pad definition for mx51_3ds
In-Reply-To: <1275661977-8077-4-git-send-email-jason77.wang@gmail.com>
References: <1275661977-8077-1-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-2-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-3-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-4-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275661977-8077-5-git-send-email-jason77.wang@gmail.com>

Add UART2, UART3 and GPIO_1_6 pad definitions for mx51_3ds board.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/include/mach/iomux-mx51.h |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index df9ecdf..76b1fbd 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -67,8 +67,10 @@ typedef enum iomux_config {
 #define MX51_PAD_EIM_D23__GPIO_2_7		IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D24__UART3_CTS		IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_EIM_D25__UART3_RXD		IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART2_CTS		IOMUX_PAD(0x414, 0x080, 4, 0x0, 0, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART3_TXD		IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS		IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS		IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS		IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_EIM_D28__EIM_D28		IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D29__EIM_D29		IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D30__EIM_D30		IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
@@ -183,8 +185,8 @@ typedef enum iomux_config {
 #define MX51_PAD_UART1_CTS__UART1_CTS		IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
 #define MX51_PAD_UART2_RXD__UART2_RXD		IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_UART2_TXD__UART2_TXD		IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__GPIO_1_22		IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__GPIO_1_23		IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO_1_22		IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO_1_23		IOMUX_PAD(0x634, 0x244, 1, 0x0, 0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_OWIRE_LINE__GPIO_1_24		IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_ROW0__KEY_ROW0		IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_ROW1__KEY_ROW1		IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
@@ -287,7 +289,7 @@ typedef enum iomux_config {
 #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
-- 
1.5.6.5



From jason77.wang at gmail.com  Fri Jun  4 10:32:55 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:32:55 +0800
Subject: [PATCH V3 5/7] mxc/mx51: Add support for the imx51 3-stack board
In-Reply-To: <1275661977-8077-5-git-send-email-jason77.wang@gmail.com>
References: <1275661977-8077-1-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-2-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-3-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-4-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-5-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275661977-8077-6-git-send-email-jason77.wang@gmail.com>

3-stack is a reference board from Freescale for their i.MX51 SoC.

Add board definition, Kconfig and Makefile to enable Freescale 3-stack
board.

Boot tested on a i.MX51 3-stack Rev2.0 board

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx5/Kconfig                       |    6 ++
 arch/arm/mach-mx5/Makefile                      |    2 +-
 arch/arm/mach-mx5/board-mx51_3ds.c              |  100 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   27 ++++++
 4 files changed, 134 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
 create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 1576d51..6ef3428 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -15,4 +15,10 @@ config MACH_MX51_BABBAGE
 	  u-boot. This includes specific configurations for the board and its
 	  peripherals.
 
+config MACH_MX51_3DS
+	bool "Support MX51PDK (3DS)"
+	select MXC_DEBUG_BOARD
+	help
+	  Include support for MX51PDK (3DS) platform. This includes specific
+	  configurations for the board and its peripherals.
 endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index bf23f86..c757c59 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -6,4 +6,4 @@
 obj-y   := cpu.o mm.o clock-mx51.o devices.o
 
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-
+obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
new file mode 100644
index 0000000..af0362c
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx51.h>
+#include <mach/board-mx51_3ds.h>
+#include <mach/imx-uart.h>
+#include <mach/cpld_debugboard.h>
+
+#include "devices.h"
+
+static struct pad_desc mx51_3ds_pads[] = {
+	/* UART1 */
+	MX51_PAD_UART1_RXD__UART1_RXD,
+	MX51_PAD_UART1_TXD__UART1_TXD,
+	MX51_PAD_UART1_RTS__UART1_RTS,
+	MX51_PAD_UART1_CTS__UART1_CTS,
+
+	/* UART2 */
+	MX51_PAD_UART2_RXD__UART2_RXD,
+	MX51_PAD_UART2_TXD__UART2_TXD,
+	MX51_PAD_EIM_D25__UART2_CTS,
+	MX51_PAD_EIM_D26__UART2_RTS,
+
+	/* UART3 */
+	MX51_PAD_UART3_RXD__UART3_RXD,
+	MX51_PAD_UART3_TXD__UART3_TXD,
+	MX51_PAD_EIM_D24__UART3_CTS,
+	MX51_PAD_EIM_D27__UART3_RTS,
+
+	/* CPLD PARENT IRQ PIN */
+	MX51_PAD_GPIO_1_6__GPIO1_6,
+};
+
+/* Serial ports */
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static struct imxuart_platform_data uart_pdata = {
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	mxc_register_device(&mxc_uart_device1, &uart_pdata);
+	mxc_register_device(&mxc_uart_device2, &uart_pdata);
+}
+#else /* !SERIAL_IMX */
+static inline void mxc_init_imx_uart(void)
+{
+}
+#endif /* SERIAL_IMX */
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
+					ARRAY_SIZE(mx51_3ds_pads));
+	mxc_init_imx_uart();
+
+	if (!mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+		platform_device_register(&smsc_lan9217_device);
+}
+
+static void __init mx51_3ds_timer_init(void)
+{
+	mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+	.init	= mx51_3ds_timer_init,
+};
+
+MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
+	.phys_io = MX51_AIPS1_BASE_ADDR,
+	.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+	.boot_params = PHYS_OFFSET + 0x100,
+	.map_io = mx51_map_io,
+	.init_irq = mx51_init_irq,
+	.init_machine = mxc_board_init,
+	.timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
new file mode 100644
index 0000000..c2aa016
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
+#define __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
+
+/*
+ * plat-mxc/include/mach/board-mx51_3ds.h
+ *
+ * This file contains all the board level configuration options.
+ *
+ * It currently hold the options defined for MX51 3Stack Platform.
+ *
+ */
+
+#define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+
+#endif	/* __ASM_ARCH_MXC_BOARD_MX51_3DS_H__ */
-- 
1.5.6.5



From jason77.wang at gmail.com  Fri Jun  4 10:32:56 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:32:56 +0800
Subject: [PATCH V3 6/7] mx51/keypad: add keypad support for i.MX51 platforms
In-Reply-To: <1275661977-8077-6-git-send-email-jason77.wang@gmail.com>
References: <1275661977-8077-1-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-2-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-3-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-4-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-5-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-6-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275661977-8077-7-git-send-email-jason77.wang@gmail.com>

Add keypad controller device definition for all i.MX51 platforms,
add a dummy kpp clock for imx keypad driver and add keypad device
registration on i.MX51 3-stack board.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx5/board-mx51_3ds.c |   61 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mx5/clock-mx51.c     |    5 +++
 arch/arm/mach-mx5/devices.c        |   19 +++++++++++
 arch/arm/mach-mx5/devices.h        |    1 +
 4 files changed, 86 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index af0362c..49f576f 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -12,6 +12,7 @@
 
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,6 +48,18 @@ static struct pad_desc mx51_3ds_pads[] = {
 
 	/* CPLD PARENT IRQ PIN */
 	MX51_PAD_GPIO_1_6__GPIO1_6,
+
+	/* KPP */
+	MX51_PAD_KEY_ROW0__KEY_ROW0,
+	MX51_PAD_KEY_ROW1__KEY_ROW1,
+	MX51_PAD_KEY_ROW2__KEY_ROW2,
+	MX51_PAD_KEY_ROW3__KEY_ROW3,
+	MX51_PAD_KEY_COL0__KEY_COL0,
+	MX51_PAD_KEY_COL1__KEY_COL1,
+	MX51_PAD_KEY_COL2__KEY_COL2,
+	MX51_PAD_KEY_COL3__KEY_COL3,
+	MX51_PAD_KEY_COL4__KEY_COL4,
+	MX51_PAD_KEY_COL5__KEY_COL5,
 };
 
 /* Serial ports */
@@ -67,6 +80,52 @@ static inline void mxc_init_imx_uart(void)
 }
 #endif /* SERIAL_IMX */
 
+#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
+static int mx51_3ds_board_keymap[] = {
+	KEY(0, 0, KEY_1),
+	KEY(0, 1, KEY_2),
+	KEY(0, 2, KEY_3),
+	KEY(0, 3, KEY_F1),
+	KEY(0, 4, KEY_UP),
+	KEY(0, 5, KEY_F2),
+
+	KEY(1, 0, KEY_4),
+	KEY(1, 1, KEY_5),
+	KEY(1, 2, KEY_6),
+	KEY(1, 3, KEY_LEFT),
+	KEY(1, 4, KEY_SELECT),
+	KEY(1, 5, KEY_RIGHT),
+
+	KEY(2, 0, KEY_7),
+	KEY(2, 1, KEY_8),
+	KEY(2, 2, KEY_9),
+	KEY(2, 3, KEY_F3),
+	KEY(2, 4, KEY_DOWN),
+	KEY(2, 5, KEY_F4),
+
+	KEY(3, 0, KEY_0),
+	KEY(3, 1, KEY_OK),
+	KEY(3, 2, KEY_ESC),
+	KEY(3, 3, KEY_ENTER),
+	KEY(3, 4, KEY_MENU),
+	KEY(3, 5, KEY_BACK)
+};
+
+static struct matrix_keymap_data mx51_3ds_map_data = {
+	.keymap		= mx51_3ds_board_keymap,
+	.keymap_size	= ARRAY_SIZE(mx51_3ds_board_keymap),
+};
+
+static void mxc_init_keypad(void)
+{
+	mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
+
 /*
  * Board specific initialization.
  */
@@ -78,6 +137,8 @@ static void __init mxc_board_init(void)
 
 	if (!mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
 		platform_device_register(&smsc_lan9217_device);
+
+	mxc_init_keypad();
 }
 
 static void __init mx51_3ds_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index d9f612d..60fced6 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
 	.parent = &ckil_clk,
 };
 
+static struct clk kpp_clk = {
+	.id = 0,
+};
+
 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
 	static struct clk name = {			\
 		.id		= i,			\
@@ -821,6 +825,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
+	_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 7130449..2aa4ea0 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -168,6 +168,25 @@ struct platform_device mxc_wdt = {
 	.resource = mxc_wdt_resources,
 };
 
+static struct resource mxc_kpp_resources[] = {
+	{
+		.start = MX51_MXC_INT_KPP,
+		.end = MX51_MXC_INT_KPP,
+		.flags = IORESOURCE_IRQ,
+	} , {
+		.start = MX51_KPP_BASE_ADDR,
+		.end = MX51_KPP_BASE_ADDR + 0x8 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct platform_device mxc_keypad_device = {
+	.name = "imx-keypad",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(mxc_kpp_resources),
+	.resource = mxc_kpp_resources,
+};
+
 static struct mxc_gpio_port mxc_gpio_ports[] = {
 	{
 		.chip.label = "gpio-0",
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index c879ae7..1fef140 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -6,3 +6,4 @@ extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbdr_udc_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device mxc_keypad_device;
-- 
1.5.6.5



From jason77.wang at gmail.com  Fri Jun  4 10:32:57 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:32:57 +0800
Subject: [PATCH V3 7/7] mx31_3ds: revert cpld debug board relate code
In-Reply-To: <1275661977-8077-7-git-send-email-jason77.wang@gmail.com>
References: <1275661977-8077-1-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-2-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-3-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-4-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-5-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-6-git-send-email-jason77.wang@gmail.com>
	<1275661977-8077-7-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275661977-8077-8-git-send-email-jason77.wang@gmail.com>

Because we add a cpld debug board support in mxc level, we remove
those redudent codes from board level.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx3/Kconfig                       |    1 +
 arch/arm/mach-mx3/mach-mx31_3ds.c               |  168 +----------------------
 arch/arm/plat-mxc/include/mach/board-mx31_3ds.h |   42 ------
 3 files changed, 4 insertions(+), 207 deletions(-)

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753f..fd422cf 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -58,6 +58,7 @@ config MACH_MX31LITE
 config MACH_MX31_3DS
 	bool "Support MX31PDK (3DS)"
 	select ARCH_MX31
+	select MXC_DEBUG_BOARD
 	help
 	  Include support for MX31PDK (3DS) platform. This includes specific
 	  configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 58e5729..d8af726 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -22,7 +22,6 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/smsc911x.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
@@ -38,6 +37,7 @@
 #include <asm/mach/map.h>
 #include <mach/common.h>
 #include <mach/board-mx31_3ds.h>
+#include <mach/cpld_debugboard.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/mxc_nand.h>
@@ -213,173 +213,11 @@ static struct imxuart_platform_data uart_pdata = {
 };
 
 /*
- * Support for the SMSC9217 on the Debug board.
- */
-
-static struct smsc911x_platform_config smsc911x_config = {
-	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
-	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-	.phy_interface	= PHY_INTERFACE_MODE_MII,
-};
-
-static struct resource smsc911x_resources[] = {
-	{
-		.start		= LAN9217_BASE_ADDR,
-		.end		= LAN9217_BASE_ADDR + 0xff,
-		.flags		= IORESOURCE_MEM,
-	}, {
-		.start		= EXPIO_INT_ENET,
-		.end		= EXPIO_INT_ENET,
-		.flags		= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device smsc911x_device = {
-	.name		= "smsc911x",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(smsc911x_resources),
-	.resource	= smsc911x_resources,
-	.dev		= {
-		.platform_data = &smsc911x_config,
-	},
-};
-
-/*
- * Routines for the CPLD on the debug board. It contains a CPLD handling
- * LEDs, switches, interrupts for Ethernet.
- */
-
-static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
-{
-	uint32_t imr_val;
-	uint32_t int_valid;
-	uint32_t expio_irq;
-
-	imr_val = __raw_readw(CPLD_INT_MASK_REG);
-	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
-
-	expio_irq = MXC_EXP_IO_BASE;
-	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
-		if ((int_valid & 1) == 0)
-			continue;
-		generic_handle_irq(expio_irq);
-	}
-}
-
-/*
- * Disable an expio pin's interrupt by setting the bit in the imr.
- * @param irq           an expio virtual irq number
- */
-static void expio_mask_irq(uint32_t irq)
-{
-	uint16_t reg;
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* mask the interrupt */
-	reg = __raw_readw(CPLD_INT_MASK_REG);
-	reg |= 1 << expio;
-	__raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-/*
- * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
- * @param irq           an expanded io virtual irq number
- */
-static void expio_ack_irq(uint32_t irq)
-{
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* clear the interrupt status */
-	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
-	__raw_writew(0, CPLD_INT_RESET_REG);
-	/* mask the interrupt */
-	expio_mask_irq(irq);
-}
-
-/*
- * Enable a expio pin's interrupt by clearing the bit in the imr.
- * @param irq           a expio virtual irq number
- */
-static void expio_unmask_irq(uint32_t irq)
-{
-	uint16_t reg;
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* unmask the interrupt */
-	reg = __raw_readw(CPLD_INT_MASK_REG);
-	reg &= ~(1 << expio);
-	__raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-static struct irq_chip expio_irq_chip = {
-	.ack = expio_ack_irq,
-	.mask = expio_mask_irq,
-	.unmask = expio_unmask_irq,
-};
-
-static int __init mx31_3ds_init_expio(void)
-{
-	int i;
-	int ret;
-
-	/* Check if there's a debug board connected */
-	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
-	    (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
-	    (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
-		/* No Debug board found */
-		return -ENODEV;
-	}
-
-	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
-		__raw_readw(CPLD_CODE_VER_REG));
-
-	/*
-	 * Configure INT line as GPIO input
-	 */
-	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
-	if (ret)
-		pr_warning("could not get LAN irq gpio\n");
-	else
-		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-
-	/* Disable the interrupts and clear the status */
-	__raw_writew(0, CPLD_INT_MASK_REG);
-	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
-	__raw_writew(0, CPLD_INT_RESET_REG);
-	__raw_writew(0x1F, CPLD_INT_MASK_REG);
-	for (i = MXC_EXP_IO_BASE;
-	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
-	     i++) {
-		set_irq_chip(i, &expio_irq_chip);
-		set_irq_handler(i, handle_level_irq);
-		set_irq_flags(i, IRQF_VALID);
-	}
-	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
-	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
-
-	return 0;
-}
-
-/*
- * This structure defines the MX31 memory map.
- */
-static struct map_desc mx31_3ds_io_desc[] __initdata = {
-	{
-		.virtual = MX31_CS5_BASE_ADDR_VIRT,
-		.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
-		.length = MX31_CS5_SIZE,
-		.type = MT_DEVICE,
-	},
-};
-
-/*
  * Set up static virtual mappings.
  */
 static void __init mx31_3ds_map_io(void)
 {
 	mx31_map_io();
-	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
 }
 
 /*!
@@ -402,8 +240,8 @@ static void __init mxc_board_init(void)
 	mx31_3ds_usbotg_init();
 	mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
 
-	if (!mx31_3ds_init_expio())
-		platform_device_register(&smsc911x_device);
+	if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
+		platform_device_register(&smsc_lan9217_device);
 }
 
 static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
index da92933..c26d88d 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
@@ -12,48 +12,6 @@
 #define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
 
 /* Definitions for components on the Debug board */
-
-/* Base address of CPLD controller on the Debug board */
-#define DEBUG_BASE_ADDRESS		CS5_IO_ADDRESS(CS5_BASE_ADDR)
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR		CS5_BASE_ADDR
-
-/* CPLD config and interrupt base address */
-#define CPLD_ADDR			(DEBUG_BASE_ADDRESS + 0x20000)
-
-/* LED switchs */
-#define CPLD_LED_REG			(CPLD_ADDR + 0x00)
-/* buttons */
-#define CPLD_SWITCH_BUTTONS_REG	(EXPIO_ADDR + 0x08)
-/* status, interrupt */
-#define CPLD_INT_STATUS_REG		(CPLD_ADDR + 0x10)
-#define CPLD_INT_MASK_REG		(CPLD_ADDR + 0x38)
-#define CPLD_INT_RESET_REG		(CPLD_ADDR + 0x20)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER1_REG		(CPLD_ADDR + 0x40)
-#define CPLD_MAGIC_NUMBER2_REG		(CPLD_ADDR + 0x48)
-/* CPLD code version */
-#define CPLD_CODE_VER_REG		(CPLD_ADDR + 0x50)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER3_REG		(CPLD_ADDR + 0x58)
-/* module reset register */
-#define CPLD_MODULE_RESET_REG		(CPLD_ADDR + 0x60)
-/* CPU ID and Personality ID */
-#define CPLD_MCU_BOARD_ID_REG		(CPLD_ADDR + 0x68)
-
-/* CPLD IRQ line for external uart, external ethernet etc */
 #define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
 
-#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_ENET		(MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_XUART_A	(MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_XUART_B	(MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_BUTTON_A	(MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_BUTTON_B	(MXC_EXP_IO_BASE + 4)
-
-#define MXC_MAX_EXP_IO_LINES	16
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
-- 
1.5.6.5



From amit.kucheria at canonical.com  Fri Jun  4 10:48:08 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Fri, 4 Jun 2010 17:48:08 +0300
Subject: [V3 0/7]Add i.MX51 3-stack board support
In-Reply-To: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>
References: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <20100604144808.GC2982@matterhorn.lan>

On 10 Jun 04, Jason Wang wrote:
> I don't know why 2 patches([patch 2/3] and [patch 3/3]) are lost in
> the V2 review.
> In V3, i fix all comments both in V1 and V2.
> 
> Big diffs:
> 1) the number of patches increases from 3 to 7, because i add 1 3ds
> common debug board patch, 2 iomux pad rename and update patches and
> 1 revert mx31_3ds debug board relating stuffs patch.
> 
> 2) Though the smsc911x_platform_config is a little bit different
> between mx31_3ds and mx51_3ds originally,  when using the common
> configuration in the mxc debug board, they all works fine. I have
> validated these two BSPs through mounting NFS rootfs.
> 
> 3) the patch [3/7] is a rename and cleanup of iomux pad definition,
> i don't know if this update has been merged, if so, please drop
> it.

It didn't fail. Give it some time. :)

-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------


From cjb at laptop.org  Fri Jun  4 10:59:14 2010
From: cjb at laptop.org (Chris Ball)
Date: Fri, 04 Jun 2010 10:59:14 -0400
Subject: Libertas/SDIO deep sleep mode
In-Reply-To: <20100604121245.GW2695@buzzloop.caiaq.de> (Daniel Mack's message
	of "Fri, 4 Jun 2010 14:12:45 +0200")
References: <20100604121245.GW2695@buzzloop.caiaq.de>
Message-ID: <m3631y7sjh.fsf@pullcord.laptop.org>

Hi,

   > Hi, I read about the recently added features in the libertas
   > driver to send the chip to its deep-sleep mode when the system
   > suspends, so the wakeup phase is shortened.

I think there might be a bit of terminology confusion here -- as
I understand it, "deep sleep" refers to putting the 8686 into a
power-saving mode after a certain amount of idle time, while the
rest of the system is running.

If you want to preserve power to the 8686 over a system suspend,
that's a largely different set of code, which isn't complete in
mainline yet; as you've seen, the MMC and SDHCI side of it is
upstream, but not libertas or pxamci code yet.

   > * The "Parentless device registered during a PM transaction"
   > looks like a bug to me. Note that I added kobject_name(&dev->kobj)
   > to the output to get a clue about what's going on.

Not sure what's going on there.

   > * The firmware survives the suspend/resume transition and works
   > fine after that. I just wonder why, as the voltage was switched
   > off?

That's odd.  Perhaps the 8686 is being alternatively powered somehow
on your hardware?

   > * I believe that if we need to keep the power switched on, there
   > should be a call to sdio_set_host_pm_flags(MMC_PM_KEEP_POWER)
   > somewhere in the libertas_sdio layer, right? How should the
   > pxamci core get to know it shouldn't switch off its regulator?

That's right.  We're using this code at OLPC, to go into system
suspend with the 8686 powered and then be woken when a new packet
arrives.  The libertas side of that code hasn't been submitted yet,
but you're welcome to check it out at our git repo:

http://dev.laptop.org/git/olpc-2.6/commit/?h=olpc-2.6.31&id=db09aa1f537f7d5eae6e52ecf59cdf3571150ee6
http://dev.laptop.org/git/olpc-2.6/log/drivers/net/wireless/libertas?h=olpc-2.6.31

- Chris.
-- 
Chris Ball   <cjb at laptop.org>
One Laptop Per Child


From darkstar6262 at gmail.com  Fri Jun  4 10:59:55 2010
From: darkstar6262 at gmail.com (Cory Maccarrone)
Date: Fri, 4 Jun 2010 14:59:55 +0000 (UTC)
Subject: Heads up: Linus plans to kill ARM defconfigs
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<201006040337.10593.marek.vasut@gmail.com>
	<201006040350.36944.marek.vasut@gmail.com>
	<201006040353.35816.marek.vasut@gmail.com>
	<20100604060338.GH6499@atomide.com>
Message-ID: <loom.20100604T165709-423@post.gmane.org>

Tony Lindgren <tony <at> atomide.com> writes:

> 
> 
> Yeah, we should have just one omap1_defconfig. It should already
> mostly work already for 15xx + 16xx. To build in 7xx, the entry-macro.S
> needs to be done the same way as for mach-omap2.
> 
> Regards,
> 
> Tony
> 

All the new omap7xx boards I plan to submit in the future should be able to work
fine in a single defconfig.  That's how I build now with my development tree.
I'd be perfectly happy to see my htcherald_defconfig get wrapped into a more
generic omap1_defconfig.

They might even be generic enough that I won't need separate board files for
them -- I'll have to see when I get to that point.

- Cory



From amit.kucheria at canonical.com  Fri Jun  4 11:13:07 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Fri, 4 Jun 2010 18:13:07 +0300
Subject: [V3 3/7] mx51/iomux: fix some pad names and make some cleanups
In-Reply-To: <1275660568-7738-4-git-send-email-jason77.wang@gmail.com>
References: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-2-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-3-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-4-git-send-email-jason77.wang@gmail.com>
Message-ID: <20100604151307.GD2982@matterhorn.lan>

On 10 Jun 04, Jason Wang wrote:
> Fix some pad names according to the naming convention and make some
> cleanups for vertical lineup.
> 
> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
> ---
>  arch/arm/plat-mxc/include/mach/iomux-mx51.h |  507 ++++++++++++--------------
>  1 files changed, 234 insertions(+), 273 deletions(-)
> 
> diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
> index ab0f95d..df9ecdf 100644
> --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
> +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
> @@ -57,278 +57,239 @@ typedef enum iomux_config {
>  
>  /*						PAD      MUX   ALT INPSE PATH PADCTRL */
>  
> -#define MX51_PAD_GPIO_2_0__EIM_D16	IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_1__EIM_D17	IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
<snip> 

Did you try compiling this? It fails to compile both babbage and 3ds boards.

This breaks the babbage board because a pad name was changed here. (An
underscore between GPIO and 1)

arch/arm/mach-mx5/board-mx51_babbage.c:81: error:
'MX51_PAD_GPIO_1_7__GPIO1_7' undeclared here (not in a function)
arch/arm/mach-mx5/board-mx51_babbage.c: In function 'initialize_otg_port':

For 3ds, the errors are:
arch/arm/mach-mx5/board-mx51_3ds.c:44: error: 'MX51_PAD_UART3_RXD__UART3_RXD'
undeclared here (not in a function)
arch/arm/mach-mx5/board-mx51_3ds.c:45: error: 'MX51_PAD_UART3_TXD__UART3_TXD'
undeclared here (not in a function)
arch/arm/mach-mx5/board-mx51_3ds.c:50: error: 'MX51_PAD_GPIO_1_6__GPIO1_6'
undeclared here (not in a function)

Perhaps you should wait till Sascha pulls in either of our patches to fixup
the padnames first.

Cheers,
Amit
-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------


From s.hauer at pengutronix.de  Fri Jun  4 11:22:58 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 4 Jun 2010 17:22:58 +0200
Subject: [V2 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <1275644934.3210.46.camel@realization>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100604085320.GB25357@pengutronix.de>
	<1275644934.3210.46.camel@realization>
Message-ID: <20100604152258.GC25357@pengutronix.de>

On Fri, Jun 04, 2010 at 11:48:54AM +0200, Alberto Panizzo wrote:
> On ven, 2010-06-04 at 10:53 +0200, Sascha Hauer wrote:
> > I'm not willing to accept another 3ds_debug board support in the
> > kernel
> > given that it's no rocket science to seperate this into another file
> > and
> > we still have plenty of time before the next merge window.
> > Jason, can you please move this to plat-mxc? I think we could find
> > someone else to switch the mx31_3ds support to the generic debug board
> > support then. 
> 
> Sascha, what do you mean with: switch the mx31_3ds support to the generic
> one in plat-mxc?

Only the 3ds debug board, not the mx31_3ds board as a whole.

> We are going to have a single machine file for all imx(2-3-5) based debug boards?
> I think it will look so messy..

Look at Jasons next patch, this is what I meant. We can reuse the 3ds
debug board stuff in the mx31_3ds.

> 
> I read the Linus concerns about ARM stuffs and RMK answer to your ask for pull..
> May we need to start a thread to discuss how we can restructure the imx support?

Well, the ultimate goal is to support all i.MX ports in one kernel, but
this is still a long way to go. We made quite some progress with Uwes
patches to avoid namespace collisions in the different register defines,
but there is still enough left to do. Try to tweak Kconfig to enable for
example i.MX27 and i.MX25 support and see what happens...

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From fachkar.datawind at gmail.com  Fri Jun  4 12:50:05 2010
From: fachkar.datawind at gmail.com (f. achkar)
Date: Fri, 04 Jun 2010 12:50:05 -0400
Subject: KERN_ERR error adding pwm scaler?
Message-ID: <4C092EBD.1010903@gmail.com>

hi,
newbie, testing linux-arm-2.6.32-9 on s3c2450. I'm stuck with the
s3c2450_init_clocks/s3c_pwmclk_init !
getting 'KERN_ERR error adding pwm scaler' in
"arch/arm/plat-s3c/pwm-clock.c:444" .

I'm not sure why I get the following:
442            if (ret < 0) {
(gdb)
444                return;
(gdb) bt
#0  s3c_pwmclk_init () at arch/arm/plat-s3c/pwm-clock.c:444
#1  0xc000e27c in s3c2450_init_clocks (xtal=<value optimized out>) at
arch/arm/mach-s3c2450/clock.c:1161
#2  0xc000f248 in s3c24xx_init_clocks (xtal=0) at
arch/arm/plat-s3c/init.c:86
#3  0xc000e3a0 in smdk2450_map_io () at
arch/arm/mach-s3c2450/mach-smdk2450.c:357
#4  0xc000d6ac in paging_init (mdesc=0xc0023088) at arch/arm/mm/mmu.c:993
#5  0xc000bc1c in setup_arch (cmdline_p=0xc04edfe4) at
arch/arm/kernel/setup.c:745
#6  0xc00088f4 in start_kernel () at init/main.c:551
#7  0x3000804c in ?? ()
#8  0x3000804c in ?? ()
(gdb) s
310        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
(gdb) s
316        divclk->divisor = tcfg_to_divisor(tcfg1);
(gdb) s
310        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
(gdb) s
(and never returns from that!!!)

anyone can give me a hint on why/how to address this issue?
the current code can be found at
http://github.com/ferarachkar/dw-ubi2-2.6.32-9/tree/chromiumos-s3c2450
thanks,
-------------------------------------------------------------
detailed gdb session below:

(gdb) thbreak start_kernel
Hardware assisted breakpoint 1 at 0xc00088a0: file init/main.c, line 522.
(gdb) c
Continuing.

Temporary breakpoint 1, start_kernel () at init/main.c:522
522        smp_setup_processor_id();
(gdb) thbreak s3c2450_init_clocks
Hardware assisted breakpoint 2 at 0xc000dff4: file
arch/arm/mach-s3c2450/clock.c, line 1088.
(gdb) c
Continuing.

Temporary breakpoint 2, s3c2450_init_clocks (xtal=12000000) at
arch/arm/mach-s3c2450/clock.c:1088
1088            unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
(gdb) thbreak arch/arm/mach-s3c2450/clock.c:1161
Hardware assisted breakpoint 3 at 0xc000e278: file
arch/arm/mach-s3c2450/clock.c, line 1161.
(gdb) c
Continuing.

Temporary breakpoint 3, s3c2450_init_clocks (xtal=<value optimized out>)
at arch/arm/mach-s3c2450/clock.c:1161
1161            s3c_pwmclk_init();
(gdb) s
s3c_pwmclk_init () at arch/arm/plat-s3c/pwm-clock.c:425
425        clk_timers = clk_get(NULL, "timers");
(gdb) s
clk_get (dev=0x0, id=0xc047057c "timers") at arch/arm/plat-s3c/clock.c:76
76        if (dev == NULL || dev->bus != &platform_bus_type)
(gdb) print *dev
$1 = {parent = 0x0, p = 0x0, kobj = {name = 0x0, entry = {next = 0x0,
prev = 0x0}, parent = 0x0, kset = 0x0, ktype = 0x0, sd = 0x0, kref =
{refcount = {
        counter = 0}}, state_initialized = 0, state_in_sysfs = 0,
state_add_uevent_sent = 0, state_remove_uevent_sent = 0, uevent_suppress
= 0},
  init_name = 0x0, type = 0x0, sem = {lock = {raw_lock = {<No data
fields>}}, count = 0, wait_list = {next = 0x0, prev = 0x0}}, bus = 0x0,
driver = 0x0,
  platform_data = 0x0, power = {power_state = {event = 0}, can_wakeup =
0, should_wakeup = 0, status = DPM_INVALID, entry = {next = 0x0, prev =
0x0}},
  dma_mask = 0x0, coherent_dma_mask = 0, dma_parms = 0x0, dma_pools =
{next = 0x0, prev = 0x0}, dma_mem = 0x0, archdata = {<No data fields>},
devt = 0,
  devres_lock = {raw_lock = {<No data fields>}}, devres_head = {next =
0x0, prev = 0x0}, knode_class = {n_klist = 0x0, n_node = {next = 0x0,
prev = 0x0},
    n_ref = {refcount = {counter = 0}}}, class = 0x0, groups = 0x0,
release = 0}
(gdb) s
79            idno = to_platform_device(dev)->id;
(gdb) s
81        spin_lock(&clocks_lock);
(gdb) s
add_preempt_count (val=1) at kernel/sched.c:5286
5286        if (DEBUG_LOCKS_WARN_ON((preempt_count() < 0)))
(gdb) s
97        return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
(gdb) s
5289        preempt_count() += val;
(gdb) s
5294        DEBUG_LOCKS_WARN_ON((preempt_count() & PREEMPT_MASK) >=
(gdb) s
clk_get (dev=<value optimized out>, id=0xc047057c "timers") at
arch/arm/plat-s3c/clock.c:83
83        list_for_each_entry(p, &clocks, list) {
(gdb) n
115        __asm__ __volatile__(
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb) n
87        return test_bit(flag, (unsigned long *)&ti->flags);
(gdb) n
482            unsigned int cpu = get_cpu();
(gdb) s
483            if (likely(module_is_live(module))) {
(gdb) s
83        list_for_each_entry(p, &clocks, list) {
(gdb) n
84            if (p->id == idno &&
(gdb) print *p
$2 = {list = {next = 0xc04f18c0, prev = 0xc04f44b4}, owner = 0x0, parent
= 0xc04f45d4, name = 0xc0470900 "spi", id = 1, usage = 0, rate = 0,
  ctrlbit = 32768, enable = 0xc00999a4 <s3c2443_clkcon_enable_p>,
set_rate = 0, get_rate = 0, round_rate = 0, set_parent = 0}
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb) n
115        __asm__ __volatile__(
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb) n
84            if (p->id == idno &&
(gdb) print *p
$3 = {list = {next = 0xc04f1888, prev = 0xc04f18f8}, owner = 0x0, parent
= 0xc04f45d4, name = 0xc0470900 "spi", id = 0, usage = 0, rate = 0,
  ctrlbit = 16384, enable = 0xc00999a4 <s3c2443_clkcon_enable_p>,
set_rate = 0, get_rate = 0, round_rate = 0, set_parent = 0}
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb) print *p
$4 = {list = {next = 0xc04f1850, prev = 0xc04f18c0}, owner = 0x0, parent
= 0xc04f45d4, name = 0xc04708b8 "iis", id = -1, usage = 0, rate = 0,
ctrlbit = 512,
  enable = 0xc00999a4 <s3c2443_clkcon_enable_p>, set_rate = 0, get_rate
= 0, round_rate = 0, set_parent = 0}
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb) 
84            if (p->id == idno &&
(gdb) print *p
$5 = {list = {next = 0xc04f1818, prev = 0xc04f1888}, owner = 0x0, parent
= 0xc04f45d4, name = 0xc04708ac "i2c", id = -1, usage = 0, rate = 0,
ctrlbit = 16,
  enable = 0xc00999a4 <s3c2443_clkcon_enable_p>, set_rate = 0, get_rate
= 0, round_rate = 0, set_parent = 0}
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb) print *p
$6 = {list = {next = 0xc04f17a8, prev = 0xc04f1818}, owner = 0x0, parent
= 0xc04f45d4, name = 0xc04708f4 "sdi", id = -1, usage = 0, rate = 0,
ctrlbit = 32,
  enable = 0xc00999a4 <s3c2443_clkcon_enable_p>, set_rate = 0, get_rate
= 0, round_rate = 0, set_parent = 0}
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb) print *p
$7 = {list = {next = 0xc04f1770, prev = 0xc04f17e0}, owner = 0x0, parent
= 0xc04f459c, name = 0xc0471890 "nand", id = -1, usage = 0, rate = 0,
ctrlbit = 0,
  enable = 0xc009cf24 <clk_null_enable>, set_rate = 0, get_rate = 0,
round_rate = 0, set_parent = 0}
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb) print *p
$8 = {list = {next = 0xc04f1738, prev = 0xc04f17a8}, owner = 0x0, parent
= 0xc04f45d4, name = 0xc04b30e0 "ac97", id = -1, usage = 0, rate = 0,
  ctrlbit = 256, enable = 0xc00999a4 <s3c2443_clkcon_enable_p>, set_rate
= 0, get_rate = 0, round_rate = 0, set_parent = 0}
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb) print *p
$9 = {list = {next = 0xc04f1700, prev = 0xc04f1770}, owner = 0x0, parent
= 0xc04f459c, name = 0xc0470594 "cfata", id = -1, usage = 0, rate = 0,
  ctrlbit = 131072, enable = 0xc0099978 <s3c2443_clkcon_enable_h>,
set_rate = 0, get_rate = 0, round_rate = 0, set_parent = 0}
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb)


83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)

83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb)



83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb) print *p
$10 = {list = {next = 0xc04f1620, prev = 0xc04f1690}, owner = 0x0,
parent = 0xc04f45d4, name = 0xc047028c "uart", id = 3, usage = 0, rate =
0, ctrlbit = 8,
  enable = 0xc00999a4 <s3c2443_clkcon_enable_p>, set_rate = 0, get_rate
= 0, round_rate = 0, set_parent = 0}
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb) print *p
$11 = {list = {next = 0xc04f15e8, prev = 0xc04f1658}, owner = 0x0,
parent = 0xc04f45d4, name = 0xc047028c "uart", id = 2, usage = 0, rate =
0, ctrlbit = 4,
  enable = 0xc00999a4 <s3c2443_clkcon_enable_p>, set_rate = 0, get_rate
= 0, round_rate = 0, set_parent = 0}
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb) print *p
$12 = {list = {next = 0xc04f15b0, prev = 0xc04f1620}, owner = 0x0,
parent = 0xc04f45d4, name = 0xc047028c "uart", id = 1, usage = 0, rate =
0, ctrlbit = 2,
  enable = 0xc00999a4 <s3c2443_clkcon_enable_p>, set_rate = 0, get_rate
= 0, round_rate = 0, set_parent = 0}
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb) print *p
$13 = {list = {next = 0xc04f1578, prev = 0xc04f15e8}, owner = 0x0,
parent = 0xc04f45d4, name = 0xc047028c "uart", id = 0, usage = 0, rate =
0, ctrlbit = 1,
  enable = 0xc00999a4 <s3c2443_clkcon_enable_p>, set_rate = 0, get_rate
= 0, round_rate = 0, set_parent = 0}
(gdb) n
83        list_for_each_entry(p, &clocks, list) {
(gdb)
115        __asm__ __volatile__(
(gdb)
83        list_for_each_entry(p, &clocks, list) {
(gdb)
84            if (p->id == idno &&
(gdb) print *p
$14 = {list = {next = 0xc04f1540, prev = 0xc04f15b0}, owner = 0x0,
parent = 0xc04f45d4, name = 0xc047057c "timers", id = -1, usage = 0,
rate = 0,
  ctrlbit = 1024, enable = 0xc00999a4 <s3c2443_clkcon_enable_p>,
set_rate = 0, get_rate = 0, round_rate = 0, set_parent = 0}
(gdb) n
481        if (module) {
(gdb) bt
#0  clk_get (dev=<value optimized out>, id=0xc047057c "timers") at
include/linux/module.h:481
#1  0xc000f62c in s3c_pwmclk_init () at arch/arm/plat-s3c/pwm-clock.c:425
#2  0xc000e27c in s3c2450_init_clocks (xtal=<value optimized out>) at
arch/arm/mach-s3c2450/clock.c:1161
#3  0xc000f248 in s3c24xx_init_clocks (xtal=0) at
arch/arm/plat-s3c/init.c:86
#4  0xc000e3a0 in smdk2450_map_io () at
arch/arm/mach-s3c2450/mach-smdk2450.c:357
#5  0xc000d6ac in paging_init (mdesc=0xc0023088) at arch/arm/mm/mmu.c:993
#6  0xc000bc1c in setup_arch (cmdline_p=0xc04edfe4) at
arch/arm/kernel/setup.c:745
#7  0xc00088f4 in start_kernel () at init/main.c:551
#8  0x3000804c in ?? ()
#9  0x3000804c in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt stack?)
(gdb) n
95        if (IS_ERR(clk)) {
(gdb)
105        spin_unlock(&clocks_lock);
(gdb) print *clk
$15 = {list = {next = 0xc04f1540, prev = 0xc04f15b0}, owner = 0x0,
parent = 0xc04f45d4, name = 0xc047057c "timers", id = -1, usage = 0,
rate = 0,
  ctrlbit = 1024, enable = 0xc00999a4 <s3c2443_clkcon_enable_p>,
set_rate = 0, get_rate = 0, round_rate = 0, set_parent = 0}
(gdb) print *(clk->parent)
$16 = {list = {next = 0xc04f459c, prev = 0xc04f460c}, owner = 0x0,
parent = 0xc04f10a8, name = 0xc04706ec "pclk", id = -1, usage = 0, rate
= 66666666,
  ctrlbit = 0, enable = 0xc009cf24 <clk_null_enable>, set_rate =
0xc009cfac <clk_default_setrate>, get_rate = 0, round_rate = 0,
set_parent = 0}
(gdb) n
87        return test_bit(flag, (unsigned long *)&ti->flags);
(gdb) bt
#0  clk_get (dev=<value optimized out>, id=0xc047057c "timers") at
include/linux/thread_info.h:87
#1  0xc000f62c in s3c_pwmclk_init () at arch/arm/plat-s3c/pwm-clock.c:425
#2  0xc000e27c in s3c2450_init_clocks (xtal=<value optimized out>) at
arch/arm/mach-s3c2450/clock.c:1161
#3  0xc000f248 in s3c24xx_init_clocks (xtal=1) at
arch/arm/plat-s3c/init.c:86
#4  0xc000e3a0 in smdk2450_map_io () at
arch/arm/mach-s3c2450/mach-smdk2450.c:357
#5  0xc000d6ac in paging_init (mdesc=0xc0023088) at arch/arm/mm/mmu.c:993
#6  0xc000bc1c in setup_arch (cmdline_p=0xc04edfe4) at
arch/arm/kernel/setup.c:745
#7  0xc00088f4 in start_kernel () at init/main.c:551
#8  0x3000804c in ?? ()
#9  0x3000804c in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt stack?)
(gdb) n
105        return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
(gdb) n
105        spin_unlock(&clocks_lock);
(gdb) n
107    }
(gdb) n
s3c_pwmclk_init () at arch/arm/plat-s3c/pwm-clock.c:426
426        if (IS_ERR(clk_timers)) {
(gdb) print *clk_timers
$17 = {list = {next = 0xc04f1540, prev = 0xc04f15b0}, owner = 0x0,
parent = 0xc04f45d4, name = 0xc047057c "timers", id = -1, usage = 0,
rate = 0,
  ctrlbit = 1024, enable = 0xc00999a4 <s3c2443_clkcon_enable_p>,
set_rate = 0, get_rate = 0, round_rate = 0, set_parent = 0}
(gdb) print *(clk_timers->parent)
$18 = {list = {next = 0xc04f459c, prev = 0xc04f460c}, owner = 0x0,
parent = 0xc04f10a8, name = 0xc04706ec "pclk", id = -1, usage = 0, rate
= 66666666,
  ctrlbit = 0, enable = 0xc009cf24 <clk_null_enable>, set_rate =
0xc009cfac <clk_default_setrate>, get_rate = 0, round_rate = 0,
set_parent = 0}
(gdb) n
432            clk_timer_scaler[clk].parent = clk_timers;
(gdb) print *(clk_timer_scaler[clk].parent)
$19 = {list = {next = 0x0, prev = 0x0}, owner = 0x0, parent = 0x0, name
= 0x0, id = 0, usage = 0, rate = 0, ctrlbit = 0, enable = 0, set_rate = 0,
  get_rate = 0, round_rate = 0, set_parent = 0}
(gdb) n
433            ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
(gdb) print *(clk_timer_scaler[clk].parent)
$20 = {list = {next = 0xc04f1540, prev = 0xc04f15b0}, owner = 0x0,
parent = 0xc04f45d4, name = 0xc047057c "timers", id = -1, usage = 0,
rate = 0,
  ctrlbit = 1024, enable = 0xc00999a4 <s3c2443_clkcon_enable_p>,
set_rate = 0, get_rate = 0, round_rate = 0, set_parent = 0}
(gdb) s
s3c24xx_register_clock (clk=0xc04f46b4) at arch/arm/plat-s3c/clock.c:311
311        if (clk->enable == NULL)
(gdb) print *clk
$21 = {list = {next = 0x0, prev = 0x0}, owner = 0x0, parent =
0xc04f1578, name = 0xc0471590 "pwm-scaler0", id = -1, usage = 0, rate =
0, ctrlbit = 0,
  enable = 0, set_rate = 0xc009d5c0 <clk_pwm_scaler_set_rate>, get_rate
= 0xc009d584 <clk_pwm_scaler_get_rate>,
  round_rate = 0xc009d544 <clk_pwm_scaler_round_rate>, set_parent = 0}
(gdb) n
312            clk->enable = clk_null_enable;
(gdb) n
317        BUG_ON(clk->list.prev != clk->list.next);
(gdb) print *clk
$22 = {list = {next = 0x0, prev = 0x0}, owner = 0x0, parent =
0xc04f1578, name = 0xc0471590 "pwm-scaler0", id = -1, usage = 0, rate =
0, ctrlbit = 0,
  enable = 0xc009cf24 <clk_null_enable>, set_rate = 0xc009d5c0
<clk_pwm_scaler_set_rate>, get_rate = 0xc009d584 <clk_pwm_scaler_get_rate>,
  round_rate = 0xc009d544 <clk_pwm_scaler_round_rate>, set_parent = 0}
(gdb) n
319        spin_lock(&clocks_lock);
(gdb)
66        __list_add(new, head, head->next);
(gdb)
45        next->prev = new;
(gdb)
46        new->next = next;
(gdb)
48        prev->next = new;
(gdb)
321        spin_unlock(&clocks_lock);
(gdb)
87        return test_bit(flag, (unsigned long *)&ti->flags);
(gdb)
105        return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
(gdb)
321        spin_unlock(&clocks_lock);
(gdb)
324    }
(gdb)
s3c_pwmclk_init () at arch/arm/plat-s3c/pwm-clock.c:434
434            if (ret < 0) {
(gdb) n
432            clk_timer_scaler[clk].parent = clk_timers;
(gdb) n
433            ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
(gdb) n
434            if (ret < 0) {
(gdb) n
441            ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
(gdb) s
s3c24xx_register_clock (clk=0xc04f4724) at arch/arm/plat-s3c/clock.c:311
311        if (clk->enable == NULL)
(gdb) print *clk
$23 = {list = {next = 0x0, prev = 0x0}, owner = 0x0, parent = 0x0, name
= 0xc04715a8 "pwm-tclk0", id = -1, usage = 0, rate = 0, ctrlbit = 0,
enable = 0,
  set_rate = 0, get_rate = 0, round_rate = 0, set_parent = 0}
(gdb) s
312            clk->enable = clk_null_enable;
(gdb) s
317        BUG_ON(clk->list.prev != clk->list.next);
(gdb) print *(clk->list.prev)
$24 = {next = 0x0, prev = 0x0}
(gdb) s                     
319        spin_lock(&clocks_lock);
(gdb) n
66        __list_add(new, head, head->next);
(gdb)
45        next->prev = new;
(gdb)
46        new->next = next;
(gdb)
48        prev->next = new;
(gdb)
321        spin_unlock(&clocks_lock);
(gdb)
87        return test_bit(flag, (unsigned long *)&ti->flags);
(gdb)
105        return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
(gdb)
321        spin_unlock(&clocks_lock);
(gdb)
324    }
(gdb)
s3c_pwmclk_init () at arch/arm/plat-s3c/pwm-clock.c:442
442            if (ret < 0) {
(gdb)
441            ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
(gdb) s
s3c24xx_register_clock (clk=0xc04f475c) at arch/arm/plat-s3c/clock.c:311
311        if (clk->enable == NULL)
(gdb)
312            clk->enable = clk_null_enable;
(gdb)
317        BUG_ON(clk->list.prev != clk->list.next);
(gdb) print *clk
$25 = {list = {next = 0x0, prev = 0x0}, owner = 0x0, parent = 0x0, name
= 0xc04715b4 "pwm-tclk1", id = -1, usage = 0, rate = 0, ctrlbit = 0,
  enable = 0xc009cf24 <clk_null_enable>, set_rate = 0, get_rate = 0,
round_rate = 0, set_parent = 0}
(gdb) l
312            clk->enable = clk_null_enable;
313   
314        /* add to the list of available clocks */
315   
316        /* Quick check to see if this clock has already been
registered. */
317        BUG_ON(clk->list.prev != clk->list.next);
318   
319        spin_lock(&clocks_lock);
320        list_add(&clk->list, &clocks);
321        spin_unlock(&clocks_lock);
(gdb) s
319        spin_lock(&clocks_lock);
(gdb)
add_preempt_count (val=1) at kernel/sched.c:5286
5286        if (DEBUG_LOCKS_WARN_ON((preempt_count() < 0)))
(gdb)
97        return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
(gdb)
5289        preempt_count() += val;
(gdb)
5294        DEBUG_LOCKS_WARN_ON((preempt_count() & PREEMPT_MASK) >=
(gdb)
s3c24xx_register_clock (clk=0xc04f475c) at include/linux/list.h:66
66        __list_add(new, head, head->next);
(gdb)
45        next->prev = new;
(gdb)
46        new->next = next;
(gdb)
48        prev->next = new;
(gdb)
321        spin_unlock(&clocks_lock);
(gdb)
sub_preempt_count (val=1) at kernel/sched.c:5308
5308        if (DEBUG_LOCKS_WARN_ON(val > preempt_count()))
(gdb)
5313        if (DEBUG_LOCKS_WARN_ON((val < PREEMPT_MASK) &&
(gdb)
97        return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
(gdb)
5320        preempt_count() -= val;
(gdb)
s3c24xx_register_clock (clk=0xc04f475c) at include/linux/thread_info.h:87
87        return test_bit(flag, (unsigned long *)&ti->flags);
(gdb) 
105        return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
(gdb)
321        spin_unlock(&clocks_lock);
(gdb)
324    }
(gdb)
s3c_pwmclk_init () at arch/arm/plat-s3c/pwm-clock.c:442
442            if (ret < 0) {
(gdb)
444                return;
(gdb) bt
#0  s3c_pwmclk_init () at arch/arm/plat-s3c/pwm-clock.c:444
#1  0xc000e27c in s3c2450_init_clocks (xtal=<value optimized out>) at
arch/arm/mach-s3c2450/clock.c:1161
#2  0xc000f248 in s3c24xx_init_clocks (xtal=0) at
arch/arm/plat-s3c/init.c:86
#3  0xc000e3a0 in smdk2450_map_io () at
arch/arm/mach-s3c2450/mach-smdk2450.c:357
#4  0xc000d6ac in paging_init (mdesc=0xc0023088) at arch/arm/mm/mmu.c:993
#5  0xc000bc1c in setup_arch (cmdline_p=0xc04edfe4) at
arch/arm/kernel/setup.c:745
#6  0xc00088f4 in start_kernel () at init/main.c:551
#7  0x3000804c in ?? ()
#8  0x3000804c in ?? ()
Backtrace stopped: previous frame identical to this frame (corrupt stack?)
(gdb) s
310        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
(gdb) s
316        divclk->divisor = tcfg_to_divisor(tcfg1);
(gdb) s
310        unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
(gdb) s



From nico at fluxnic.net  Fri Jun  4 14:08:55 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 04 Jun 2010 14:08:55 -0400 (EDT)
Subject: [PATCH 4/4 v2] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <4C08A6A7.8010904@alcatel-lucent.com>
References: <4C08A6A7.8010904@alcatel-lucent.com>
Message-ID: <alpine.LFD.2.00.1006041401540.22319@xanadu.home>

On Fri, 4 Jun 2010, Benjamin Zores wrote:

> The I/O Mapping has to be set conditionally. I'd propose the following
> approach:
> 
> /* I/O Mapping with 1 PEX controller */
> static struct map_desc kirkwood_io_desc_1[] __initdata = {
>     {
>         .virtual    = KIRKWOOD_PCIE_IO_VIRT_BASE,
>         .pfn        = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
>         .length        = KIRKWOOD_PCIE_IO_SIZE,
>         .type        = MT_DEVICE,
>     }, {
>         .virtual    = KIRKWOOD_REGS_VIRT_BASE,
>         .pfn        = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
>         .length        = KIRKWOOD_REGS_SIZE,
>         .type        = MT_DEVICE,
>     },
> };
> 
> /* I/O Mapping with 2 PEX controllers */
> static struct map_desc kirkwood_io_desc_2[] __initdata = {
>     {
>         .virtual    = KIRKWOOD_PCIE_IO_VIRT_BASE,
>         .pfn        = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
>         .length        = KIRKWOOD_PCIE_IO_SIZE,
>         .type        = MT_DEVICE,
>     }, {
>     {
>         .virtual    = KIRKWOOD_PCIE1_IO_VIRT_BASE,
>         .pfn        = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
>         .length        = KIRKWOOD_PCIE1_IO_SIZE,
>         .type        = MT_DEVICE,
>     }, {
>         .virtual    = KIRKWOOD_REGS_VIRT_BASE,
>         .pfn        = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
>         .length        = KIRKWOOD_REGS_SIZE,
>         .type        = MT_DEVICE,
>     },
> };

Please make the PCIE1 into a separate map_desc of its own rather than 
duplicating PCIE0 in both, and then do an additional call to 
iotable_init() when necessary.

> And 2nd PCIe PHY shutdown at init:
> 
> +    /* For PCIe #1: first shutdown the phy */
> +   if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
> +        writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
> +       while (1)
> +          if (readl(PCIE1_STATUS) & 0x1)
> +             break;
> +    writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
> +  }

You'd have to make sure you're actually on a 6282 before doing this I 
guess.

> Additionally, not sure it is needed for PCIe support but at least for F6282,
> you need to refine the MPP matrix in mpp.h. The 6282 MPP _really_ is different
> from 6281 one.
> I can send a patch for this if needed, I already have done the necessary
> changes in my tree.

That would be great.


Nicolas


From grant.likely at secretlab.ca  Fri Jun  4 16:01:08 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 4 Jun 2010 14:01:08 -0600
Subject: Boot interface for device trees on ARM
In-Reply-To: <alpine.LFD.2.00.1005191055180.12758@xanadu.home>
References: <201005181054.32325.jeremy.kerr@canonical.com> 
	<alpine.LFD.2.00.1005172341200.12758@xanadu.home>
	<AANLkTilJl9_NHiT1LITG7UbA9S7OYsnGMcDAsFEEx5Ob@mail.gmail.com> 
	<alpine.LFD.2.00.1005191055180.12758@xanadu.home>
Message-ID: <AANLkTilhqg270l-_m9raalqAPPRhvLJD9omHe8ysgLjg@mail.gmail.com>

On Wed, May 19, 2010 at 11:52 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> [ Complete boot description and proposal added at the end
> ?for those interested. ]

Alright, after much thinking, I'm okay with this approach.  None of my
remaining objections are showstoppers.

I've still got a few comments/questions.  I'll restrict them to the
full proposal to avoid confusion.

> Booting Linux on ARM
> ====================
>
> Two methods for passing boot information to the Linux kernel on ARM are
> possible:
>
> 1) the legacy method
>
> 2) the DT (device tree) method
>
> The legacy method
> -----------------
[...]
> The DT method
> -------------
>
> The DT method requires that a unique ID be registered for each SOC
> family for the DT purpose within the same ID space. ?But instead of
> having one ID for each possible machine, only one ID per SOC family is
> required. ?So the bootloader simply has to pass into r1 the ID
> corresponding to DT instead of the specific machine ID. ?This is a hard
> requirement.
>
> With this, the kernel can remain largely backward compatible with the
> legacy boot method, requiring _no_ change to the existing code, as the
> ID is sufficient to distinguish between both boot types. ?The machine
> record remains largely relevant even for a DT boot as the majority of
> its content is SOC specific anyway, and given a per SOC ID for DT usage
> means that the early boot facilities are still usable as is even in the
> DT context. ?And then the init_machine method in the machine record is
> naturally used to parse the device tree and do its work on multiple
> machines' behalf instead of relying on compiled-in static data for a
> specific machine.

There will still be instances of machine-specific setup code that
needs to be chosen at boot (based on the top level 'compatible'
property), but init_machine() appears to be early enough to handle
this.

hmmm... however, things the device tree blob and the initrd both need
to be marked as bootmem at paging_init() time, but init_machine()
doesn't run until later.  There will still need to be some hooks for
doing early DT processing, but none of that should be either board or
SoC specific.

> The bootloader must also store in memory the DT data and pass its
> location via r2. ?The r2 initialization therefore becomes a hard
> requirement when a DT is used. The boot_params field in the DT machine
> record could be set to -1 to disable ATAG parsing when a DT machine ID
> is used, and look into the DT data instead.
>
> Backward Compatibility Considerations
> -------------------------------------
>
> Now let's have a look at what happens when we mix this with bootloaders.
>
> If a kernel is too old, or was not configured with the "machine support"
> for DT, then only one thing may happen when a bootloader passes a DT
> machine ID to the kernel. ?The early boot code will fail to find the
> machine record for the provided ID and refuse to boot. ?If you have
> CONFIG_DEBUG_LL and are attempting to boot on the right SOC, then you'll
> probably get the error message on a serial port, along with a list of
> the actual machines and their IDs supported by that kernel. ?In other
> words, this is not a new failure mode. Two solutions: either reconfigure
> your kernel to add DT support for your SOC, or configure your bootloader
> to use the legacy boot method. ?And having a bootloader that can do DT
> only for a machine that has only legacy support in the kernel is
> senseless, so that case needs no be considered any longer.
>
> The opposite is the kernel being configured for DT _only_, and the
> bootloader being too old, or misconfigured, so it passes a non-DT
> machine ID to the kernel. ?In this case the same failure mode as above
> will be observed: kernel failing to find the matching machine record and
> halting (after attempting to display the error and the available machine
> supported). Solution: reconfigure your kernel with legacy support for
> that machine.
>
> If the goal is to experiment with DT support in the kernel, and the
> bootloader does not support DT, then some shim can be prepended to the
> kernel image to fix things up. ?Most bootloaders already have the
> ability to load arbitrary binary data in memory, and branch to arbitrary
> location too. ?So it should be pretty easy to tftp the kernel, then tftp
> the DT data, to finally branch into the kernel with appropriate values
> in r1 and r2.

A couple of other options here for experimenting is to carry a dtb as
a payload in the zImage wrapper, or to link dtbs directly into the
kernel proper and point to it from the machine structure.  Doing so
would allow even existing machines to use the same DT setup code.

My remaining objection is that the DT-only approach demands firmware
not just pass a dtb blob, but to also modify it.  The ATAG+DT approach
allows current firmware projects to continue passing data in the same
way it does now (less impact on firmware developers to add DT
support).

However, I'm not going to dwell on this point any longer because we
already have at least one firmware project (U-Boot) that understands
the device tree, and other firmware projects can use the shim approach
as a stop gap until native support is added.

It may make for a more painful transition, but you're probably right
in that it is better in the long run.

Go ahead and consider me "agreed".  :-)

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From jcrigby at gmail.com  Fri Jun  4 16:33:23 2010
From: jcrigby at gmail.com (John Rigby)
Date: Fri, 4 Jun 2010 14:33:23 -0600
Subject: Boot interface for device trees on ARM
In-Reply-To: <AANLkTilhqg270l-_m9raalqAPPRhvLJD9omHe8ysgLjg@mail.gmail.com>
References: <201005181054.32325.jeremy.kerr@canonical.com>
	<alpine.LFD.2.00.1005172341200.12758@xanadu.home>
	<AANLkTilJl9_NHiT1LITG7UbA9S7OYsnGMcDAsFEEx5Ob@mail.gmail.com>
	<alpine.LFD.2.00.1005191055180.12758@xanadu.home>
	<AANLkTilhqg270l-_m9raalqAPPRhvLJD9omHe8ysgLjg@mail.gmail.com>
Message-ID: <AANLkTilsEvl-_zz-Fs2hQqOagx-AN8PYHi0pqFrVZBKN@mail.gmail.com>

On Fri, Jun 4, 2010 at 2:01 PM, Grant Likely <grant.likely at secretlab.ca> wrote:

...

>
> Go ahead and consider me "agreed". ?:-)
>
> g.
>

And there was much rejoicing in the land.


From jdl at jdl.com  Fri Jun  4 16:37:49 2010
From: jdl at jdl.com (Jon Loeliger)
Date: Fri, 04 Jun 2010 15:37:49 -0500
Subject: Boot interface for device trees on ARM 
In-Reply-To: <AANLkTilsEvl-_zz-Fs2hQqOagx-AN8PYHi0pqFrVZBKN@mail.gmail.com> 
References: <201005181054.32325.jeremy.kerr@canonical.com>
	<alpine.LFD.2.00.1005172341200.12758@xanadu.home>
	<AANLkTilJl9_NHiT1LITG7UbA9S7OYsnGMcDAsFEEx5Ob@mail.gmail.com>
	<alpine.LFD.2.00.1005191055180.12758@xanadu.home>
	<AANLkTilhqg270l-_m9raalqAPPRhvLJD9omHe8ysgLjg@mail.gmail.com>
	<AANLkTilsEvl-_zz-Fs2hQqOagx-AN8PYHi0pqFrVZBKN@mail.gmail.com>
Message-ID: <E1OKdeH-00053a-U2@jdl.com>

>
> > Go ahead and consider me "agreed". =A0:-)
> >
> > g.
> 
> And there was much rejoicing in the land.

Really.  Let the record show that Grant is agreeable. :-)

jdl


From nico at fluxnic.net  Fri Jun  4 16:51:24 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 04 Jun 2010 16:51:24 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
Message-ID: <alpine.LFD.2.00.1006041418390.22319@xanadu.home>

On Fri, 4 Jun 2010, Martin Guy wrote:

> I think you've missed the point.
> 
> Linus' problem is that he is spending MOST of his linux-kernel-support
> time fielding patches from a dozen port maintainers, and dropping
> defconfigs is a desperate attempt to cut the amount of arm fiddling he
> is asked to do, and I guess droppiong defconfigs seems to him to be
> they way to cut the least important and most verbose part of this
> drudgery.

Not exactly.  If you read along the thread, you'll see that what Linus 
is actually complaining about is the fact that those defconfig files are 
huge and clutter the source tree for little value.  When someone sends 
him a pull request for some ARM target, the actual diffstat/dirstat is 
dominated by the defconfig file changes, making the review exercise 
futile (even if Linus is probably merely only looking at the diffstat 
for ARM merges).

> While a defconfig restructuring does address the specific issue it's
> pointless. He's going to drop defconfigs, so we'll all just have to
> have our own web pages giving our suggested defconfigs for our own
> boards.

Linus wants something to be done about the current defconfig mess which 
is perfectly legitimate.  He even suggested a possible solution.  I 
don't think he'll simply drop those defconfig files if we demonstrate 
that we're taking action to fix the actual problem.

In the mean time, anything that can be done today to reduce the number 
of defconfig files is a good thing.  In some cases we're even talking 
about merging 7 of those into 1.  Those are low hanging fruits that are 
absolutely worth the little effort required, and that would help with 
kernel compilation tests.

> Shame. I was about to post a Sim.One defconfig patch (while fully
> realizing that the choice of options is largely arbitrary. and copied
> ad-hoc from some other similar defconfig). While it's nice to be able
> to tell people "make foobar_defconfig; make (z|u|bz)Image" in reality
> the config is as arbitrary as the root filesystem in use (and should
> be chosen to match it).

Sure.  All the defconfigs are largely arbitrary.  What needs to be done, 
though, is some way to preserve the info for a default minimal 
configuration a given target require to support all its on-board 
soldered peripherals.  That is hardly arbitrary as those peripherals 
cannot be changed, and their config options are often buried down into 
the Kconfig jungle.

> The best way to free up many hours every day of Linus' time is for one
> person to isolate him from the port maintainers, so that he only has
> to pull (ideally) once per release cycle from one repository.

Possibly, but that's an orthogonal issue to the matter at hand.  It used 
to be RMK who did gather all the patches in addition to his current role 
as the gatekeeper and reviewer for core ARM patches.  And that didn't 
scale as RMK became overworked.  It was then proposed that large 
isolated subarchitecture changes be maintained separately from RMK's 
tree and pulled directly by Linus.

And even if only one person was gathering all the ARM patches together, 
then Linus would still be presented with a humongous amount of lines 
added/changed in arch/arm/configs/* which would still skew the diffstat 
and dirstat, effectively not solving the current issue at all.

What really needs to be done is to remove those defconfig files from the 
code churn picture, so when Linus is asked to pull ARM stuff he's not 
presented with defconfig crap shadowing the real changes.  To achieve 
that, we need to:

1) Collapse as many defconfig files together as possible.  That can be 
   done easily now (even during the -rc period IMHO) with immediate 
   advantages:
   a) reduce the weight of arch/arm/configs/
   b) make fewer machine configs to build for KAutobuild
   c) provide the beginning of a solution to tell Linus that we're 
      concerned too and dealing with the issue.

2) Consider alternative ways to encode those non arbitrary config 
   defaults in a human readable way (that's another of Linus' 
   complaints).  For that, some solutions were proposed, but they won't 
   be developed in a single day like (1) can.

Now the discussion around the ability to compile many machine classes 
(in addition to multiple machines from the same machine class as we 
already can do) together in a single kernel will certainly have some 
effect on the number of defconfig files, but there are other more 
important reasons for doing that other than this issue.


Nicolas


From grant.likely at secretlab.ca  Fri Jun  4 17:07:00 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 4 Jun 2010 15:07:00 -0600
Subject: Boot interface for device trees on ARM
In-Reply-To: <E1OKdeH-00053a-U2@jdl.com>
References: <201005181054.32325.jeremy.kerr@canonical.com> 
	<alpine.LFD.2.00.1005172341200.12758@xanadu.home>
	<AANLkTilJl9_NHiT1LITG7UbA9S7OYsnGMcDAsFEEx5Ob@mail.gmail.com> 
	<alpine.LFD.2.00.1005191055180.12758@xanadu.home>
	<AANLkTilhqg270l-_m9raalqAPPRhvLJD9omHe8ysgLjg@mail.gmail.com> 
	<AANLkTilsEvl-_zz-Fs2hQqOagx-AN8PYHi0pqFrVZBKN@mail.gmail.com> 
	<E1OKdeH-00053a-U2@jdl.com>
Message-ID: <AANLkTilgfQ6lSOn4PC_hmFnPX_cJucrVZQMznJD2AHuU@mail.gmail.com>

On Fri, Jun 4, 2010 at 2:37 PM, Jon Loeliger <jdl at jdl.com> wrote:
>>
>> > Go ahead and consider me "agreed". =A0:-)
>> >
>> > g.
>>
>> And there was much rejoicing in the land.
>
> Really. ?Let the record show that Grant is agreeable. :-)

hey now, let's not get carried away.

g.


From martin.ereth at arcor.de  Fri Jun  4 17:58:58 2010
From: martin.ereth at arcor.de (Martin Ereth)
Date: Fri, 04 Jun 2010 23:58:58 +0200
Subject: [PATCH 2.6.35-rc1] arm/mach-at91: Different crystal frequencies on
	AT91SAM9263 evaluation kit
Message-ID: <4C097722.7060704@arcor.de>

From: Martin Ereth <martin.ereth at arcor.de>

On newer evaluation boards for AT91SAM9263 Atmel changed the crystal where the
frequency of the processor is derived from. They changed it from 16.36766 MHz
to 18.432 MHz because it is easier to connect a gps receiver.

Using the wrong crystal frequency during board initialization results in the
wrong frequency of the processor which leads to strange characters on a serial
console.

With this patch the user is able to choose the crystal installed on his board.

Signed-off-by: Martin Ereth <martin.ereth at arcor.de>
---

Please be patient, this is my first patch. If I do things wrong
please tell me. What is the next step? Thanks.

diff -rupN linux-2.6.35-rc1-vanilla/arch/arm/mach-at91/board-sam9263ek.c linux-2.6.35-rc1/arch/arm/mach-at91/board-sam9263ek.c
--- linux-2.6.35-rc1-vanilla/arch/arm/mach-at91/board-sam9263ek.c       2010-06-04 15:40:55.000000000 +0200
+++ linux-2.6.35-rc1/arch/arm/mach-at91/board-sam9263ek.c       2010-06-04 16:43:18.000000000 +0200
@@ -54,8 +54,8 @@

  static void __init ek_map_io(void)
  {
-       /* Initialize processor: 16.367 MHz crystal */
-       at91sam9263_initialize(16367660);
+       /* Initialize processor: 16.36766 MHz or 18.432 MHz crystal */
+       at91sam9263_initialize(AT91SAM9263_CRYSTAL_HZ);

         /* DBGU on ttyS0. (Rx & Tx only) */
         at91_register_uart(0, 0, 0);
diff -rupN linux-2.6.35-rc1-vanilla/arch/arm/mach-at91/include/mach/at91sam9263.h linux-2.6.35-rc1/arch/arm/mach-at91/include/mach/at91sam9263.h
--- linux-2.6.35-rc1-vanilla/arch/arm/mach-at91/include/mach/at91sam9263.h      2010-06-04 15:40:55.000000000 +0200
+++ linux-2.6.35-rc1/arch/arm/mach-at91/include/mach/at91sam9263.h      2010-06-04 16:51:56.000000000 +0200
@@ -123,5 +123,13 @@
  #define AT91SAM9263_DMAC_BASE  0x00800000      /* DMA Controller */
  #define AT91SAM9263_UHP_BASE   0x00a00000      /* USB Host controller */

+/*
+ * Crystals.
+ */
+#if defined(CONFIG_HAVE_AT91SAM9263_CRYSTAL_16367660)
+#define AT91SAM9263_CRYSTAL_HZ 16367660
+#else /* CONFIG_HAVE_AT91SAM9263_CRYSTAL_18432000 */
+#define AT91SAM9263_CRYSTAL_HZ 18432000
+#endif

  #endif
diff -rupN linux-2.6.35-rc1-vanilla/arch/arm/mach-at91/Kconfig linux-2.6.35-rc1/arch/arm/mach-at91/Kconfig
--- linux-2.6.35-rc1-vanilla/arch/arm/mach-at91/Kconfig 2010-06-04 15:40:55.000000000 +0200
+++ linux-2.6.35-rc1/arch/arm/mach-at91/Kconfig 2010-06-04 16:22:19.000000000 +0200
@@ -448,6 +448,25 @@ config MTD_NAND_ATMEL_BUSWIDTH_16
           On AT91SAM926x boards both types of NAND flash can be present
           (8 and 16 bit data bus width).

+if MACH_AT91SAM9263EK
+
+choice
+       prompt "Choose crystal frequency on your board"
+
+config HAVE_AT91SAM9263_CRYSTAL_16367660
+       bool "16.36766 MHz"
+       help
+         Select this if you have a 16.36766 MHz crystal on your board.
+
+config HAVE_AT91SAM9263_CRYSTAL_18432000
+       bool "18.432 MHz"
+       help
+         Select this if you have a 18.432 MHz crystal on your board.
+
+endchoice
+
+endif
+
  # ----------------------------------------------------------

  comment "AT91 Feature Selections"



From khc at pm.waw.pl  Fri Jun  4 18:08:44 2010
From: khc at pm.waw.pl (Krzysztof Halasa)
Date: Sat, 05 Jun 2010 00:08:44 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <alpine.LFD.2.00.1006041418390.22319@xanadu.home> (Nicolas
	Pitre's message of "Fri, 04 Jun 2010 16:51:24 -0400 (EDT)")
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
Message-ID: <m38w6ulac3.fsf@intrepid.localdomain>

Nicolas Pitre <nico at fluxnic.net> writes:

> Linus wants something to be done about the current defconfig mess which 
> is perfectly legitimate.  He even suggested a possible solution.  I 
> don't think he'll simply drop those defconfig files if we demonstrate 
> that we're taking action to fix the actual problem.

To be honest, I see no usefulness in current defconfigs. Not only ARM
- in any and all defconfigs altogether.

Having this info somewhere on the web, maybe - just like we have the
build logs etc. But in the kernel source tree?

I wonder if I'm the only one frequently doing
grep CONFIG* ... | grep -v defconfig.

I think the issue will fix itself when the "select problem" is fixed.
And we should've fixed the "select problem" long ago (e.g. Kconfig*
should be able to select things without worrying about intermediate
steps, and it should be able to ask the user if needed).
-- 
Krzysztof Halasa


From vince at kyllikki.org  Fri Jun  4 18:28:20 2010
From: vince at kyllikki.org (Vincent Sanders)
Date: Fri, 4 Jun 2010 23:28:20 +0100
Subject: defconfig information
Message-ID: <20100604222820.GA4438@kyllikki.org>

With all the recent issues over default configurations I have decided
to release the Kernel autobuilder fifth anniversary statistics a bit
early.

http://armlinux.simtec.co.uk/reports/kautobuild-5year-report.pdf
http://armlinux.simtec.co.uk/reports/kautobuild-5year-stats.ods

The report is still a little raw but clearly illustrates the
proliferation of default configurations on ARM (although MIPS and PPC
are not all that far behind!) 

In brief, we could loose around 90% of the default configurations
(i.e. keep only 20 configurations) and "only" loose build coverage of
40% of the supported machines!

As always the ARM Kernel autobuilder is available at
http://armlinux.simtec.co.uk/kautobuild/ 

The community usage of this service has dropped to an all time low
(only six people actually used it in the last month) and I am
seriously considering if it serves a useful purpose any longer.

-- 
Regards Vincent



From marek.vasut at gmail.com  Fri Jun  4 20:46:48 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat,  5 Jun 2010 02:46:48 +0200
Subject: [PATCH] pxa2xx/cpufreq: Fix DRI computation
Message-ID: <1275698808-31166-1-git-send-email-marek.vasut@gmail.com>

The DRI field was incorrectly computed, causing various hangs and weird
behaviour on PXA2xx machines. This patch introduces the DRI computation
according to the PXA255 (January 2004) and PXA270 (MV-S301039-00 Rev. A)
datasheets.

NOTE: The CPU type is checked only once, so the code is a little bit faster now.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/cpufreq-pxa2xx.c |   33 +++++++++++++++++++++++++++++----
 1 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 9e4d981..5373db0 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -251,17 +251,42 @@ static void init_sdram_rows(void)
 	if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
 		drac0 = MDCNFG_DRAC0(mdcnfg);
 
-	sdram_rows = 1 << (11 + max(drac0, drac2));
+	sdram_rows = 11 + max(drac0, drac2);
 }
 
 static u32 mdrefr_dri(unsigned int freq)
 {
 	u32 dri = 0;
 
-	if (cpu_is_pxa25x())
-		dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
+	/* 
+	 * PXA255 (6.5.3):
+	 * 	DRI = (Refresh time / rows * memory clock frequency) / 32
+	 * PXA270 (Table 91):
+	 * 	DRI = (Refresh time / rows * memory clock frequency - 31) / 32
+	 * 
+	 * Memory clock frequency is in MHz here! (Refresh time is in ms).
+	 */
+
+	/*
+	 * SDRAM_TREF	Refresh time
+	 * freq		Memory clock frequency (in kHz)
+	 * sdram_rows	Rows
+	 *
+	 * Here we do the common part for both CPUs:
+	 * 	(Refresh time / rows * memory clock frequency)
+	 *
+	 * NOTE: We must convert freq from kHz to MHz, but we do the
+	 * multiplication prior to division to retain percision.
+	 */
+	dri = (SDRAM_TREF * freq) / (sdram_rows * 1000);
+
+	/* On PXA27x, substitute 31 from the value first (Table 91). */
 	if (cpu_is_pxa27x())
-		dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
+		dri -= 31;
+
+	/* Finaly, divide the result by 32. */
+	dri /= 32;
+
 	return dri;
 }
 
-- 
1.7.1



From jason77.wang at gmail.com  Fri Jun  4 20:54:47 2010
From: jason77.wang at gmail.com (jason)
Date: Sat, 05 Jun 2010 08:54:47 +0800
Subject: [V3 3/7] mx51/iomux: fix some pad names and make some cleanups
In-Reply-To: <20100604151307.GD2982@matterhorn.lan>
References: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-2-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-3-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-4-git-send-email-jason77.wang@gmail.com>
	<20100604151307.GD2982@matterhorn.lan>
Message-ID: <4C09A057.4090201@gmail.com>

Amit Kucheria wrote:
> On 10 Jun 04, Jason Wang wrote:
>   
>> Fix some pad names according to the naming convention and make some
>> cleanups for vertical lineup.
>>
>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>> ---
>>  arch/arm/plat-mxc/include/mach/iomux-mx51.h |  507 ++++++++++++--------------
>>  1 files changed, 234 insertions(+), 273 deletions(-)
>>
>> diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
>> index ab0f95d..df9ecdf 100644
>> --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
>> +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
>> @@ -57,278 +57,239 @@ typedef enum iomux_config {
>>  
>>  /*						PAD      MUX   ALT INPSE PATH PADCTRL */
>>  
>> -#define MX51_PAD_GPIO_2_0__EIM_D16	IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
>> -#define MX51_PAD_GPIO_2_1__EIM_D17	IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
>>     
> <snip> 
>
> Did you try compiling this? It fails to compile both babbage and 3ds boards.
>
> This breaks the babbage board because a pad name was changed here. (An
> underscore between GPIO and 1)
>
> arch/arm/mach-mx5/board-mx51_babbage.c:81: error:
> 'MX51_PAD_GPIO_1_7__GPIO1_7' undeclared here (not in a function)
> arch/arm/mach-mx5/board-mx51_babbage.c: In function 'initialize_otg_port':
>
> For 3ds, the errors are:
> arch/arm/mach-mx5/board-mx51_3ds.c:44: error: 'MX51_PAD_UART3_RXD__UART3_RXD'
> undeclared here (not in a function)
> arch/arm/mach-mx5/board-mx51_3ds.c:45: error: 'MX51_PAD_UART3_TXD__UART3_TXD'
> undeclared here (not in a function)
> arch/arm/mach-mx5/board-mx51_3ds.c:50: error: 'MX51_PAD_GPIO_1_6__GPIO1_6'
> undeclared here (not in a function)
>
> Perhaps you should wait till Sascha pulls in either of our patches to fixup
> the padnames first.
>
>   
Sorry, this is because just before i send V3, i make some changes for 
iomux-mx51.h in a hurry
and didn't make building test after change this part.
Take your advice.

Thanks,
Jason.
> Cheers,
> Amit
>   



From marek.vasut at gmail.com  Fri Jun  4 21:25:05 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat,  5 Jun 2010 03:25:05 +0200
Subject: [PATCH 1/2] backlight: Fix blanking for LMS283GF05 LCD
Message-ID: <1275701106-2832-1-git-send-email-marek.vasut@gmail.com>

The LCD was turned on if the variable power was > 0, but that was incorrect. The
LCD has to be turned on in every case but POWERDOWN.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/video/backlight/lms283gf05.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/video/backlight/lms283gf05.c b/drivers/video/backlight/lms283gf05.c
index abc43a0..5d3cf33 100644
--- a/drivers/video/backlight/lms283gf05.c
+++ b/drivers/video/backlight/lms283gf05.c
@@ -129,7 +129,7 @@ static int lms283gf05_power_set(struct lcd_device *ld, int power)
 	struct spi_device *spi = st->spi;
 	struct lms283gf05_pdata *pdata = spi->dev.platform_data;
 
-	if (power) {
+	if (power <= FB_BLANK_NORMAL) {
 		if (pdata)
 			lms283gf05_reset(pdata->reset_gpio,
 					pdata->reset_inverted);
-- 
1.7.1



From marek.vasut at gmail.com  Fri Jun  4 21:25:06 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat,  5 Jun 2010 03:25:06 +0200
Subject: [PATCH 2/2] backlight: Fix blanking for L4F00242T03 LCD
In-Reply-To: <1275701106-2832-1-git-send-email-marek.vasut@gmail.com>
References: <1275701106-2832-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1275701106-2832-2-git-send-email-marek.vasut@gmail.com>

The LCD was turned on if the variable power was > 0, but that was incorrect. The
LCD has to be turned on in every case but POWERDOWN.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/video/backlight/l4f00242t03.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/video/backlight/l4f00242t03.c b/drivers/video/backlight/l4f00242t03.c
index 9093ef0..c67801e 100644
--- a/drivers/video/backlight/l4f00242t03.c
+++ b/drivers/video/backlight/l4f00242t03.c
@@ -78,7 +78,7 @@ static int l4f00242t03_lcd_power_set(struct lcd_device *ld, int power)
 	const u16 slpin = 0x10;
 	const u16 disoff = 0x28;
 
-	if (power) {
+	if (power <= FB_BLANK_NORMAL) {
 		if (priv->lcd_on)
 			return 0;
 
-- 
1.7.1



From marek.vasut at gmail.com  Fri Jun  4 21:25:46 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat, 5 Jun 2010 03:25:46 +0200
Subject: [PATCH 2/2] backlight: Fix blanking for L4F00242T03 LCD
In-Reply-To: <1275636583.3210.37.camel@realization>
References: <1275630748-10722-1-git-send-email-marek.vasut@gmail.com>
	<1275630748-10722-2-git-send-email-marek.vasut@gmail.com>
	<1275636583.3210.37.camel@realization>
Message-ID: <201006050325.47060.marek.vasut@gmail.com>

Dne P? 4. ?ervna 2010 09:29:43 Alberto Panizzo napsal(a):
> On ven, 2010-06-04 at 07:52 +0200, Marek Vasut wrote:
> > The LCD was turned on if the variable power was > 0, but that was
> > incorrect. The LCD has to be turned on in every case but POWERDOWN.
> > 
> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> 
> Ack
> 
> > ---
> > 
> >  drivers/video/backlight/l4f00242t03.c |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> > 
> > diff --git a/drivers/video/backlight/l4f00242t03.c
> > b/drivers/video/backlight/l4f00242t03.c index 9093ef0..ac20b2e 100644
> > --- a/drivers/video/backlight/l4f00242t03.c
> > +++ b/drivers/video/backlight/l4f00242t03.c
> > @@ -78,7 +78,7 @@ static int l4f00242t03_lcd_power_set(struct lcd_device
> > *ld, int power)
> > 
> >  	const u16 slpin = 0x10;
> >  	const u16 disoff = 0x28;
> > 
> > -	if (power) {
> > +	if (power < FB_BLANK_POWERDOWN) {
> > 
> >  		if (priv->lcd_on)
> >  		
> >  			return 0;
> 
> lcd.h states:
> struct lcd_ops {
> 	/* Get the LCD panel power status (0: full on, 1..3: controller
> 	   power on, flat panel power off, 4: full off), see FB_BLANK_XXX */
> 	int (*get_power)(struct lcd_device *);
> 	/* Enable or disable power to the LCD (0: on; 4: off, see FB_BLANK_XXX) 
*/
> 	int (*set_power)(struct lcd_device *, int power);
> 
> AFAIK the gray area between FB_BLANK_NORMAL and FB_BLANK_HSYNC_SUSPEND
> can be chosen as needs.
> 
> Why not:
> 
> + #define POWER_IS_ON(pwr)	((pwr) <= FB_BLANK_NORMAL)
> 
> ...
> 
> -	if (power) {
> +	if (POWER_IS_ON(power)) {
>  		if (priv->lcd_on)
>  			return 0;
> 
> So with FB_BLANK_NORMAL the lcd is active and on -> low latencies
> in re-enabling the video out, but for !POWER_IS_ON(power) we will send
> the lcd to standby.
> 
> It have to be implemented for power == FB_BLANK_POWERDOWN to turn off the
> regulators of the lcd.
> 
> What do you think about?

Thanks! I sent a new (better) version. If you want credit in it, tell me how 
should I add you one ;-)
> 
> Regards,


From jeremy.kerr at canonical.com  Fri Jun  4 21:33:04 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Sat, 5 Jun 2010 09:33:04 +0800
Subject: Boot interface for device trees on ARM
In-Reply-To: <AANLkTilhqg270l-_m9raalqAPPRhvLJD9omHe8ysgLjg@mail.gmail.com>
References: <201005181054.32325.jeremy.kerr@canonical.com>
	<alpine.LFD.2.00.1005191055180.12758@xanadu.home>
	<AANLkTilhqg270l-_m9raalqAPPRhvLJD9omHe8ysgLjg@mail.gmail.com>
Message-ID: <201006050933.06714.jeremy.kerr@canonical.com>

All,

> > With this, the kernel can remain largely backward compatible with the
> > legacy boot method, requiring _no_ change to the existing code, as the
> > ID is sufficient to distinguish between both boot types.  The machine
> > record remains largely relevant even for a DT boot as the majority of
> > its content is SOC specific anyway, and given a per SOC ID for DT usage
> > means that the early boot facilities are still usable as is even in the
> > DT context.  And then the init_machine method in the machine record is
> > naturally used to parse the device tree and do its work on multiple
> > machines' behalf instead of relying on compiled-in static data for a
> > specific machine.
> 
> There will still be instances of machine-specific setup code that
> needs to be chosen at boot (based on the top level 'compatible'
> property), but init_machine() appears to be early enough to handle
> this.
> 
> hmmm... however, things the device tree blob and the initrd both need
> to be marked as bootmem at paging_init() time, but init_machine()
> doesn't run until later.  There will still need to be some hooks for
> doing early DT processing, but none of that should be either board or
> SoC specific.

If we're planning to keep the machine IDs around (even if they are now per-
SoC), I'd like to know what would be left using them. The only thing that I 
can see that we currently use is io_pg_offset for the DEBUG_LL builds, and 
that isn't a convincing case to keep them.

Cheers,


Jeremy


From kmpark at infradead.org  Fri Jun  4 22:24:44 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Sat, 5 Jun 2010 11:24:44 +0900
Subject: [PATCH 2/2] MAINTAINERS: add maintainer for SAMSUNG ARM 
	ARCHITECTURES
In-Reply-To: <1275647794-30634-2-git-send-email-kgene.kim@samsung.com>
References: <1275647794-30634-1-git-send-email-kgene.kim@samsung.com>
	<1275647794-30634-2-git-send-email-kgene.kim@samsung.com>
Message-ID: <AANLkTinpth-JO7pIOWXbnuUWXM3xQ1OnFKkfESwi0cP3@mail.gmail.com>

Hi Ben,

I'm waiting your comments.

Thank you,
Kyungmin Park

On Fri, Jun 4, 2010 at 7:36 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
> ?MAINTAINERS | ? ?2 ++
> ?1 files changed, 2 insertions(+), 0 deletions(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 1d41149..f4e4c61 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -896,11 +896,13 @@ S: ? ? ? ?Maintained
>
> ?ARM/SAMSUNG ARM ARCHITECTURES
> ?M: ? ? Ben Dooks <ben-linux at fluff.org>
> +M: ? ? Kukjin Kim <kgene.kim at samsung.com>
> ?L: ? ? linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> ?W: ? ? http://www.fluff.org/ben/linux/
> ?S: ? ? Maintained
> ?F: ? ? arch/arm/plat-samsung/
> ?F: ? ? arch/arm/plat-s3c24xx/
> +F: ? ? arch/arm/plat-s5p/
>
> ?ARM/S3C2410 ARM ARCHITECTURE
> ?M: ? ? Ben Dooks <ben-linux at fluff.org>
> --
> 1.6.2.5
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From nico at fluxnic.net  Fri Jun  4 22:29:11 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 04 Jun 2010 22:29:11 -0400 (EDT)
Subject: Boot interface for device trees on ARM
In-Reply-To: <201006050933.06714.jeremy.kerr@canonical.com>
References: <201005181054.32325.jeremy.kerr@canonical.com>
	<alpine.LFD.2.00.1005191055180.12758@xanadu.home>
	<AANLkTilhqg270l-_m9raalqAPPRhvLJD9omHe8ysgLjg@mail.gmail.com>
	<201006050933.06714.jeremy.kerr@canonical.com>
Message-ID: <alpine.LFD.2.00.1006042212400.30664@xanadu.home>

On Sat, 5 Jun 2010, Jeremy Kerr wrote:

> All,
> 
> > > With this, the kernel can remain largely backward compatible with the
> > > legacy boot method, requiring _no_ change to the existing code, as the
> > > ID is sufficient to distinguish between both boot types.  The machine
> > > record remains largely relevant even for a DT boot as the majority of
> > > its content is SOC specific anyway, and given a per SOC ID for DT usage
> > > means that the early boot facilities are still usable as is even in the
> > > DT context.  And then the init_machine method in the machine record is
> > > naturally used to parse the device tree and do its work on multiple
> > > machines' behalf instead of relying on compiled-in static data for a
> > > specific machine.
> > 
> > There will still be instances of machine-specific setup code that
> > needs to be chosen at boot (based on the top level 'compatible'
> > property), but init_machine() appears to be early enough to handle
> > this.
> > 
> > hmmm... however, things the device tree blob and the initrd both need
> > to be marked as bootmem at paging_init() time, but init_machine()
> > doesn't run until later.  There will still need to be some hooks for
> > doing early DT processing, but none of that should be either board or
> > SoC specific.
> 
> If we're planning to keep the machine IDs around (even if they are now per-
> SoC), I'd like to know what would be left using them. The only thing that I 
> can see that we currently use is io_pg_offset for the DEBUG_LL builds, and 
> that isn't a convincing case to keep them.

Why not?

Kernel infrastructure backward compatibility means that you need to keep 
struct machine_desc instances around.  Granted, for the DT case, many of 
the members could be NULL or initialized with dummy stubs.  But that is 
very cheap to keep around, and that allows the same kernel binary to be 
able to use both the DT boot and the legacy boot.

In 10 years we might realize that non DT setups are no longer relevant 
and then all we'll have to do is rip out struct machine_desc and ignore 
the r1 value from the bootloader.  Ignoring that now means a flag day. 
And nobody wants a flag day forced upon them.


Nicolas


From kmpark at infradead.org  Fri Jun  4 22:40:53 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Sat, 05 Jun 2010 11:40:53 +0900
Subject: [PATCH] s5pc110: SDHCI-s3c can override host capabilities
Message-ID: <20100605024053.GA23419@july>

Each board can override the default sdhci host capabilities.
Some board has broken features by hardwares and support 8-bit bandwidth.

Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index 4c05b39..d0887da 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -65,4 +65,6 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
 		set->cfg_gpio = pd->cfg_gpio;
 	if (pd->cfg_card)
 		set->cfg_card = pd->cfg_card;
+	if (pd->host_caps)
+		set->host_caps = pd->host_caps;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index e49bc4c..e45a82e 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -65,4 +65,6 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
 		set->cfg_gpio = pd->cfg_gpio;
 	if (pd->cfg_card)
 		set->cfg_card = pd->cfg_card;
+	if (pd->host_caps)
+		set->host_caps = pd->host_caps;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index 824580b..5ee3b89 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -66,4 +66,6 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
 		set->cfg_gpio = pd->cfg_gpio;
 	if (pd->cfg_card)
 		set->cfg_card = pd->cfg_card;
+	if (pd->host_caps)
+		set->host_caps = pd->host_caps;
 }


From grant.likely at secretlab.ca  Sat Jun  5 01:59:02 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 4 Jun 2010 23:59:02 -0600
Subject: Boot interface for device trees on ARM
In-Reply-To: <alpine.LFD.2.00.1006042212400.30664@xanadu.home>
References: <201005181054.32325.jeremy.kerr@canonical.com> 
	<alpine.LFD.2.00.1005191055180.12758@xanadu.home>
	<AANLkTilhqg270l-_m9raalqAPPRhvLJD9omHe8ysgLjg@mail.gmail.com> 
	<201006050933.06714.jeremy.kerr@canonical.com>
	<alpine.LFD.2.00.1006042212400.30664@xanadu.home>
Message-ID: <AANLkTin_PpsY6_hWKtJ9HZqk4nhEO0mcD5TdKpq0KbYk@mail.gmail.com>

On Fri, Jun 4, 2010 at 8:29 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Sat, 5 Jun 2010, Jeremy Kerr wrote:
>> > hmmm... however, things the device tree blob and the initrd both need
>> > to be marked as bootmem at paging_init() time, but init_machine()
>> > doesn't run until later. ?There will still need to be some hooks for
>> > doing early DT processing, but none of that should be either board or
>> > SoC specific.
>>
>> If we're planning to keep the machine IDs around (even if they are now per-
>> SoC), I'd like to know what would be left using them. The only thing that I
>> can see that we currently use is io_pg_offset for the DEBUG_LL builds, and
>> that isn't a convincing case to keep them.
>
> Why not?
>
> Kernel infrastructure backward compatibility means that you need to keep
> struct machine_desc instances around. ?Granted, for the DT case, many of
> the members could be NULL or initialized with dummy stubs. ?But that is
> very cheap to keep around, and that allows the same kernel binary to be
> able to use both the DT boot and the legacy boot.

I agree with Nicolas on this point.  He's convinced me that machine id
without ATAGs is sufficient to deal with the backwards compatibility
issues.  I have no problem with making machine_id in r1 part of the
boot requirements.

That being said; each DT must still be fully-formed.  Every DT still
needs a top level compatible property to uniquely identify the
machine.  If it turns out that Linux can ignore the machine ID and
rely solely on the DT data, then so be it.  I actually don't care much
since then it is just an internal Linux kernel implementation detail.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From ryan at bluewatersys.com  Sat Jun  5 02:05:50 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Sat,  5 Jun 2010 18:05:50 +1200
Subject: [PATCH 0/5] SPEAr3xx: Unify build of SPEAr3xx platforms
Message-ID: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>

Rework the SPEAr3xx code to allow all three SPEAr3xx platforms to be
built into a single kernel.

I do not have access to any SPEAr3xx hardware, so the patch series is
build tested only.

Ryan Mallon (5):
  SPEAr3xx: Make local structres static
  SPEAR3xx: Rename register/irq defines to remove naming conflicts
  SPEAr3xx: Rework pmx_dev code to remove conflicts
  SPEAr3xx: Rework KConfig to allow all boards to be compiled in
  SPEAr3xx: Replace defconfigs with single unfied defconfig

 arch/arm/configs/spear300_defconfig            |  773 -----------------------
 arch/arm/configs/spear310_defconfig            |  775 ------------------------
 arch/arm/configs/spear320_defconfig            |  775 ------------------------
 arch/arm/configs/spear3xx_defconfig            |  775 ++++++++++++++++++++++++
 arch/arm/mach-spear3xx/Kconfig                 |   30 +-
 arch/arm/mach-spear3xx/Kconfig300              |   17 -
 arch/arm/mach-spear3xx/Kconfig310              |   17 -
 arch/arm/mach-spear3xx/Kconfig320              |   17 -
 arch/arm/mach-spear3xx/include/mach/generic.h  |  139 ++---
 arch/arm/mach-spear3xx/include/mach/irqs.h     |  195 +++---
 arch/arm/mach-spear3xx/include/mach/spear300.h |   26 +-
 arch/arm/mach-spear3xx/include/mach/spear310.h |   44 +-
 arch/arm/mach-spear3xx/include/mach/spear320.h |   50 +-
 arch/arm/mach-spear3xx/spear300.c              |  135 ++--
 arch/arm/mach-spear3xx/spear300_evb.c          |   26 +-
 arch/arm/mach-spear3xx/spear310.c              |  137 +++--
 arch/arm/mach-spear3xx/spear310_evb.c          |   42 +-
 arch/arm/mach-spear3xx/spear320.c              |  247 ++++----
 arch/arm/mach-spear3xx/spear320_evb.c          |   36 +-
 arch/arm/mach-spear3xx/spear3xx.c              |  124 ++--
 20 files changed, 1387 insertions(+), 2993 deletions(-)
 delete mode 100644 arch/arm/configs/spear300_defconfig
 delete mode 100644 arch/arm/configs/spear310_defconfig
 delete mode 100644 arch/arm/configs/spear320_defconfig
 create mode 100644 arch/arm/configs/spear3xx_defconfig
 delete mode 100644 arch/arm/mach-spear3xx/Kconfig300
 delete mode 100644 arch/arm/mach-spear3xx/Kconfig310
 delete mode 100644 arch/arm/mach-spear3xx/Kconfig320



From ryan at bluewatersys.com  Sat Jun  5 02:05:54 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Sat,  5 Jun 2010 18:05:54 +1200
Subject: [PATCH 4/5] SPEAr3xx: Rework KConfig to allow all boards to be
	compiled in
In-Reply-To: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1275717955-14545-5-git-send-email-ryan@bluewatersys.com>

Now that all three SPEAr3xx platforms can be built into one kernel,
rework KConfig to allow this. Move everything into one KConfig file
while we are here.

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-spear3xx/Kconfig    |   30 ++++++++++++++++++++----------
 arch/arm/mach-spear3xx/Kconfig300 |   17 -----------------
 arch/arm/mach-spear3xx/Kconfig310 |   17 -----------------
 arch/arm/mach-spear3xx/Kconfig320 |   17 -----------------
 4 files changed, 20 insertions(+), 61 deletions(-)
 delete mode 100644 arch/arm/mach-spear3xx/Kconfig300
 delete mode 100644 arch/arm/mach-spear3xx/Kconfig310
 delete mode 100644 arch/arm/mach-spear3xx/Kconfig320

diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 20d1317..2cee6b0 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -4,9 +4,26 @@
 
 if ARCH_SPEAR3XX
 
-choice
-	prompt "SPEAr3XX Family"
-	default MACH_SPEAR300
+menu "SPEAr3xx Implementations"
+config BOARD_SPEAR300_EVB
+	bool "SPEAr300 Evaluation Board"
+	select MACH_SPEAR300
+	help
+	  Supports ST SPEAr300 Evaluation Board
+
+config BOARD_SPEAR310_EVB
+	bool "SPEAr310 Evaluation Board"
+	select MACH_SPEAR310
+	help
+	  Supports ST SPEAr310 Evaluation Board
+
+config BOARD_SPEAR320_EVB
+	bool "SPEAr320 Evaluation Board"
+	select MACH_SPEAR320
+	help
+	  Supports ST SPEAr320 Evaluation Board
+
+endmenu
 
 config MACH_SPEAR300
 	bool "SPEAr300"
@@ -23,11 +40,4 @@ config MACH_SPEAR320
 	help
 	  Supports ST SPEAr320 Machine
 
-endchoice
-
-# Adding SPEAr3XX machine specific configuration files
-source "arch/arm/mach-spear3xx/Kconfig300"
-source "arch/arm/mach-spear3xx/Kconfig310"
-source "arch/arm/mach-spear3xx/Kconfig320"
-
 endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Kconfig300 b/arch/arm/mach-spear3xx/Kconfig300
deleted file mode 100644
index c519a05..0000000
--- a/arch/arm/mach-spear3xx/Kconfig300
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr300 machine configuration file
-#
-
-if MACH_SPEAR300
-
-choice
-	prompt "SPEAr300 Boards"
-	default BOARD_SPEAR300_EVB
-
-config BOARD_SPEAR300_EVB
-	bool "SPEAr300 Evaluation Board"
-	help
-	  Supports ST SPEAr300 Evaluation Board
-endchoice
-
-endif	#MACH_SPEAR300
diff --git a/arch/arm/mach-spear3xx/Kconfig310 b/arch/arm/mach-spear3xx/Kconfig310
deleted file mode 100644
index 60e7442..0000000
--- a/arch/arm/mach-spear3xx/Kconfig310
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr310 machine configuration file
-#
-
-if MACH_SPEAR310
-
-choice
-	prompt "SPEAr310 Boards"
-	default BOARD_SPEAR310_EVB
-
-config BOARD_SPEAR310_EVB
-	bool "SPEAr310 Evaluation Board"
-	help
-	  Supports ST SPEAr310 Evaluation Board
-endchoice
-
-endif	#MACH_SPEAR310
diff --git a/arch/arm/mach-spear3xx/Kconfig320 b/arch/arm/mach-spear3xx/Kconfig320
deleted file mode 100644
index 1c1d438..0000000
--- a/arch/arm/mach-spear3xx/Kconfig320
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr320 machine configuration file
-#
-
-if MACH_SPEAR320
-
-choice
-	prompt "SPEAr320 Boards"
-	default BOARD_SPEAR320_EVB
-
-config BOARD_SPEAR320_EVB
-	bool "SPEAr320 Evaluation Board"
-	help
-	  Supports ST SPEAr320 Evaluation Board
-endchoice
-
-endif	#MACH_SPEAR320
-- 
1.5.5



From ryan at bluewatersys.com  Sat Jun  5 02:05:51 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Sat,  5 Jun 2010 18:05:51 +1200
Subject: [PATCH 1/5] SPEAr3xx: Make local structres static
In-Reply-To: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1275717955-14545-2-git-send-email-ryan@bluewatersys.com>

Several structures in arch/arm/mach-spear3xx are not marked static
like they should be. Fix this.

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-spear3xx/spear300.c |   33 ++++++++++----------
 arch/arm/mach-spear3xx/spear310.c |   16 +++++-----
 arch/arm/mach-spear3xx/spear320.c |   56 +++++++++++++++++-----------------
 arch/arm/mach-spear3xx/spear3xx.c |   60 ++++++++++++++++++------------------
 4 files changed, 83 insertions(+), 82 deletions(-)

diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 3560f8c..b71f996 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -119,7 +119,7 @@ struct pmx_mode caml_lcd_mode = {
 };
 
 /* devices */
-struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
+static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
 	{
 		.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
 			ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
@@ -134,7 +134,7 @@ struct pmx_dev pmx_fsmc_2_chips = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
+static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
 	{
 		.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
 			ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
@@ -149,7 +149,7 @@ struct pmx_dev pmx_fsmc_4_chips = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_keyboard_modes[] = {
+static struct pmx_dev_mode pmx_keyboard_modes[] = {
 	{
 		.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
 			LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
@@ -166,7 +166,7 @@ struct pmx_dev pmx_keyboard = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_clcd_modes[] = {
+static struct pmx_dev_mode pmx_clcd_modes[] = {
 	{
 		.ids = PHOTO_FRAME_MODE,
 		.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
@@ -184,7 +184,7 @@ struct pmx_dev pmx_clcd = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
+static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
 	{
 		.ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
 		.mask = PMX_MII_MASK,
@@ -211,7 +211,7 @@ struct pmx_dev pmx_telecom_gpio = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
+static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
 	{
 		.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
 			HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
@@ -229,7 +229,7 @@ struct pmx_dev pmx_telecom_tdm = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
+static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
 	{
 		.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
 			LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
@@ -246,7 +246,7 @@ struct pmx_dev pmx_telecom_spi_cs_i2c_clk = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_camera_modes[] = {
+static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
 	{
 		.ids = CAML_LCDW_MODE | CAML_LCD_MODE,
 		.mask = PMX_MII_MASK,
@@ -263,7 +263,7 @@ struct pmx_dev pmx_telecom_camera = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_dac_modes[] = {
+static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
 	{
 		.ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
 			| CAMU_WLCD_MODE | CAML_LCD_MODE,
@@ -278,7 +278,7 @@ struct pmx_dev pmx_telecom_dac = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
+static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
 	{
 		.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
 			| LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
@@ -295,7 +295,7 @@ struct pmx_dev pmx_telecom_i2s = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
+static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
 	{
 		.ids = NAND_MODE | NOR_MODE,
 		.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
@@ -310,7 +310,7 @@ struct pmx_dev pmx_telecom_boot_pins = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
+static struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
 	{
 		.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
 			HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
@@ -330,7 +330,7 @@ struct pmx_dev pmx_telecom_sdio_4bit = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
+static struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
 	{
 		.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
 			HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
@@ -349,7 +349,7 @@ struct pmx_dev pmx_telecom_sdio_8bit = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_gpio1_modes[] = {
+static struct pmx_dev_mode pmx_gpio1_modes[] = {
 	{
 		.ids = PHOTO_FRAME_MODE,
 		.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
@@ -391,7 +391,7 @@ struct amba_device gpio1_device = {
 };
 
 /* spear3xx shared irq */
-struct shirq_dev_config shirq_ras1_config[] = {
+static struct shirq_dev_config shirq_ras1_config[] = {
 	{
 		.virq = VIRQ_IT_PERS_S,
 		.enb_mask = IT_PERS_S_IRQ_MASK,
@@ -431,7 +431,8 @@ struct shirq_dev_config shirq_ras1_config[] = {
 	},
 };
 
-struct spear_shirq shirq_ras1 = {
+
+static struct spear_shirq shirq_ras1 = {
 	.irq = IRQ_GEN_RAS_1,
 	.dev_config = shirq_ras1_config,
 	.dev_count = ARRAY_SIZE(shirq_ras1_config),
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 96a1ab8..14698b8 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -142,7 +142,7 @@ struct pmx_driver pmx_driver = {
 /* Add spear310 specific devices here */
 
 /* spear3xx shared irq */
-struct shirq_dev_config shirq_ras1_config[] = {
+static struct shirq_dev_config shirq_ras1_config[] = {
 	{
 		.virq = VIRQ_SMII0,
 		.status_mask = SMII0_IRQ_MASK,
@@ -170,7 +170,7 @@ struct shirq_dev_config shirq_ras1_config[] = {
 	},
 };
 
-struct spear_shirq shirq_ras1 = {
+static struct spear_shirq shirq_ras1 = {
 	.irq = IRQ_GEN_RAS_1,
 	.dev_config = shirq_ras1_config,
 	.dev_count = ARRAY_SIZE(shirq_ras1_config),
@@ -182,7 +182,7 @@ struct spear_shirq shirq_ras1 = {
 	},
 };
 
-struct shirq_dev_config shirq_ras2_config[] = {
+static struct shirq_dev_config shirq_ras2_config[] = {
 	{
 		.virq = VIRQ_UART1,
 		.status_mask = UART1_IRQ_MASK,
@@ -201,7 +201,7 @@ struct shirq_dev_config shirq_ras2_config[] = {
 	},
 };
 
-struct spear_shirq shirq_ras2 = {
+static struct spear_shirq shirq_ras2 = {
 	.irq = IRQ_GEN_RAS_2,
 	.dev_config = shirq_ras2_config,
 	.dev_count = ARRAY_SIZE(shirq_ras2_config),
@@ -213,14 +213,14 @@ struct spear_shirq shirq_ras2 = {
 	},
 };
 
-struct shirq_dev_config shirq_ras3_config[] = {
+static struct shirq_dev_config shirq_ras3_config[] = {
 	{
 		.virq = VIRQ_EMI,
 		.status_mask = EMI_IRQ_MASK,
 	},
 };
 
-struct spear_shirq shirq_ras3 = {
+static struct spear_shirq shirq_ras3 = {
 	.irq = IRQ_GEN_RAS_3,
 	.dev_config = shirq_ras3_config,
 	.dev_count = ARRAY_SIZE(shirq_ras3_config),
@@ -232,7 +232,7 @@ struct spear_shirq shirq_ras3 = {
 	},
 };
 
-struct shirq_dev_config shirq_intrcomm_ras_config[] = {
+static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 	{
 		.virq = VIRQ_TDM_HDLC,
 		.status_mask = TDM_HDLC_IRQ_MASK,
@@ -245,7 +245,7 @@ struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 	},
 };
 
-struct spear_shirq shirq_intrcomm_ras = {
+static struct spear_shirq shirq_intrcomm_ras = {
 	.irq = IRQ_INTRCOMM_RAS_ARM,
 	.dev_config = shirq_intrcomm_ras_config,
 	.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 6a12195..958e52d 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -54,7 +54,7 @@ struct pmx_mode small_printers_mode = {
 };
 
 /* devices */
-struct pmx_dev_mode pmx_clcd_modes[] = {
+static struct pmx_dev_mode pmx_clcd_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE,
 		.mask = 0x0,
@@ -68,7 +68,7 @@ struct pmx_dev pmx_clcd = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_emi_modes[] = {
+static struct pmx_dev_mode pmx_emi_modes[] = {
 	{
 		.ids = AUTO_EXP_MODE,
 		.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
@@ -82,7 +82,7 @@ struct pmx_dev pmx_emi = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_fsmc_modes[] = {
+static struct pmx_dev_mode pmx_fsmc_modes[] = {
 	{
 		.ids = ALL_MODES,
 		.mask = 0x0,
@@ -96,7 +96,7 @@ struct pmx_dev pmx_fsmc = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_spp_modes[] = {
+static struct pmx_dev_mode pmx_spp_modes[] = {
 	{
 		.ids = SMALL_PRINTERS_MODE,
 		.mask = 0x0,
@@ -110,7 +110,7 @@ struct pmx_dev pmx_spp = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_sdio_modes[] = {
+static struct pmx_dev_mode pmx_sdio_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
 			SMALL_PRINTERS_MODE,
@@ -125,7 +125,7 @@ struct pmx_dev pmx_sdio = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_i2s_modes[] = {
+static struct pmx_dev_mode pmx_i2s_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 		.mask = PMX_UART0_MODEM_MASK,
@@ -139,7 +139,7 @@ struct pmx_dev pmx_i2s = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_uart1_modes[] = {
+static struct pmx_dev_mode pmx_uart1_modes[] = {
 	{
 		.ids = ALL_MODES,
 		.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
@@ -153,7 +153,7 @@ struct pmx_dev pmx_uart1 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_uart1_modem_modes[] = {
+static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
 	{
 		.ids = AUTO_EXP_MODE,
 		.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
@@ -172,7 +172,7 @@ struct pmx_dev pmx_uart1_modem = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_uart2_modes[] = {
+static struct pmx_dev_mode pmx_uart2_modes[] = {
 	{
 		.ids = ALL_MODES,
 		.mask = PMX_FIRDA_MASK,
@@ -186,7 +186,7 @@ struct pmx_dev pmx_uart2 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_touchscreen_modes[] = {
+static struct pmx_dev_mode pmx_touchscreen_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE,
 		.mask = PMX_SSP_CS_MASK,
@@ -200,7 +200,7 @@ struct pmx_dev pmx_touchscreen = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_can_modes[] = {
+static struct pmx_dev_mode pmx_can_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
 		.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
@@ -215,7 +215,7 @@ struct pmx_dev pmx_can = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_sdio_led_modes[] = {
+static struct pmx_dev_mode pmx_sdio_led_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 		.mask = PMX_SSP_CS_MASK,
@@ -229,7 +229,7 @@ struct pmx_dev pmx_sdio_led = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_pwm0_modes[] = {
+static struct pmx_dev_mode pmx_pwm0_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 		.mask = PMX_UART0_MODEM_MASK,
@@ -246,7 +246,7 @@ struct pmx_dev pmx_pwm0 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_pwm1_modes[] = {
+static struct pmx_dev_mode pmx_pwm1_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 		.mask = PMX_UART0_MODEM_MASK,
@@ -263,7 +263,7 @@ struct pmx_dev pmx_pwm1 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_pwm2_modes[] = {
+static struct pmx_dev_mode pmx_pwm2_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 		.mask = PMX_SSP_CS_MASK,
@@ -280,7 +280,7 @@ struct pmx_dev pmx_pwm2 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_pwm3_modes[] = {
+static struct pmx_dev_mode pmx_pwm3_modes[] = {
 	{
 		.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
 		.mask = PMX_MII_MASK,
@@ -294,7 +294,7 @@ struct pmx_dev pmx_pwm3 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_ssp1_modes[] = {
+static struct pmx_dev_mode pmx_ssp1_modes[] = {
 	{
 		.ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
 		.mask = PMX_MII_MASK,
@@ -308,7 +308,7 @@ struct pmx_dev pmx_ssp1 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_ssp2_modes[] = {
+static struct pmx_dev_mode pmx_ssp2_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE,
 		.mask = PMX_MII_MASK,
@@ -322,7 +322,7 @@ struct pmx_dev pmx_ssp2 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_mii1_modes[] = {
+static struct pmx_dev_mode pmx_mii1_modes[] = {
 	{
 		.ids = AUTO_NET_MII_MODE,
 		.mask = 0x0,
@@ -336,7 +336,7 @@ struct pmx_dev pmx_mii1 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_smii0_modes[] = {
+static struct pmx_dev_mode pmx_smii0_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
 		.mask = PMX_MII_MASK,
@@ -350,7 +350,7 @@ struct pmx_dev pmx_smii0 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_smii1_modes[] = {
+static struct pmx_dev_mode pmx_smii1_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
 		.mask = PMX_MII_MASK,
@@ -364,7 +364,7 @@ struct pmx_dev pmx_smii1 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_i2c1_modes[] = {
+static struct pmx_dev_mode pmx_i2c1_modes[] = {
 	{
 		.ids = AUTO_EXP_MODE,
 		.mask = 0x0,
@@ -387,7 +387,7 @@ struct pmx_driver pmx_driver = {
 /* Add spear320 specific devices here */
 
 /* spear3xx shared irq */
-struct shirq_dev_config shirq_ras1_config[] = {
+static struct shirq_dev_config shirq_ras1_config[] = {
 	{
 		.virq = VIRQ_EMI,
 		.status_mask = EMI_IRQ_MASK,
@@ -403,7 +403,7 @@ struct shirq_dev_config shirq_ras1_config[] = {
 	},
 };
 
-struct spear_shirq shirq_ras1 = {
+static struct spear_shirq shirq_ras1 = {
 	.irq = IRQ_GEN_RAS_1,
 	.dev_config = shirq_ras1_config,
 	.dev_count = ARRAY_SIZE(shirq_ras1_config),
@@ -416,7 +416,7 @@ struct spear_shirq shirq_ras1 = {
 	},
 };
 
-struct shirq_dev_config shirq_ras3_config[] = {
+static struct shirq_dev_config shirq_ras3_config[] = {
 	{
 		.virq = VIRQ_PLGPIO,
 		.enb_mask = GPIO_IRQ_MASK,
@@ -435,7 +435,7 @@ struct shirq_dev_config shirq_ras3_config[] = {
 	},
 };
 
-struct spear_shirq shirq_ras3 = {
+static struct spear_shirq shirq_ras3 = {
 	.irq = IRQ_GEN_RAS_3,
 	.dev_config = shirq_ras3_config,
 	.dev_count = ARRAY_SIZE(shirq_ras3_config),
@@ -449,7 +449,7 @@ struct spear_shirq shirq_ras3 = {
 	},
 };
 
-struct shirq_dev_config shirq_intrcomm_ras_config[] = {
+static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 	{
 		.virq = VIRQ_CANU,
 		.status_mask = CAN_U_IRQ_MASK,
@@ -497,7 +497,7 @@ struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 	},
 };
 
-struct spear_shirq shirq_intrcomm_ras = {
+static struct spear_shirq shirq_intrcomm_ras = {
 	.irq = IRQ_INTRCOMM_RAS_ARM,
 	.dev_config = shirq_intrcomm_ras_config,
 	.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index e87313a..5f2cddc 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -102,7 +102,7 @@ void __init spear3xx_map_io(void)
 
 /* pad multiplexing support */
 /* devices */
-struct pmx_dev_mode pmx_firda_modes[] = {
+static struct pmx_dev_mode pmx_firda_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_FIRDA_MASK,
@@ -116,7 +116,7 @@ struct pmx_dev pmx_firda = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_i2c_modes[] = {
+static struct pmx_dev_mode pmx_i2c_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_I2C_MASK,
@@ -130,7 +130,7 @@ struct pmx_dev pmx_i2c = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_ssp_cs_modes[] = {
+static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_SSP_CS_MASK,
@@ -144,7 +144,7 @@ struct pmx_dev pmx_ssp_cs = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_ssp_modes[] = {
+static struct pmx_dev_mode pmx_ssp_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_SSP_MASK,
@@ -158,7 +158,7 @@ struct pmx_dev pmx_ssp = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_mii_modes[] = {
+static struct pmx_dev_mode pmx_mii_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_MII_MASK,
@@ -172,7 +172,7 @@ struct pmx_dev pmx_mii = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
+static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_GPIO_PIN0_MASK,
@@ -186,7 +186,7 @@ struct pmx_dev pmx_gpio_pin0 = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
+static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_GPIO_PIN1_MASK,
@@ -200,7 +200,7 @@ struct pmx_dev pmx_gpio_pin1 = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
+static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_GPIO_PIN2_MASK,
@@ -214,7 +214,7 @@ struct pmx_dev pmx_gpio_pin2 = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
+static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_GPIO_PIN3_MASK,
@@ -228,7 +228,7 @@ struct pmx_dev pmx_gpio_pin3 = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
+static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_GPIO_PIN4_MASK,
@@ -242,7 +242,7 @@ struct pmx_dev pmx_gpio_pin4 = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
+static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_GPIO_PIN5_MASK,
@@ -256,7 +256,7 @@ struct pmx_dev pmx_gpio_pin5 = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_uart0_modem_modes[] = {
+static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_UART0_MODEM_MASK,
@@ -270,7 +270,7 @@ struct pmx_dev pmx_uart0_modem = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_uart0_modes[] = {
+static struct pmx_dev_mode pmx_uart0_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_UART0_MASK,
@@ -284,7 +284,7 @@ struct pmx_dev pmx_uart0 = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_timer_3_4_modes[] = {
+static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_TIMER_3_4_MASK,
@@ -298,7 +298,7 @@ struct pmx_dev pmx_timer_3_4 = {
 	.enb_on_reset = 0,
 };
 
-struct pmx_dev_mode pmx_timer_1_2_modes[] = {
+static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
 	{
 		.ids = 0xffffffff,
 		.mask = PMX_TIMER_1_2_MASK,
@@ -314,7 +314,7 @@ struct pmx_dev pmx_timer_1_2 = {
 
 #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
 /* plgpios devices */
-struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_FIRDA_MASK,
@@ -328,7 +328,7 @@ struct pmx_dev pmx_plgpio_0_1 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_UART0_MASK,
@@ -342,7 +342,7 @@ struct pmx_dev pmx_plgpio_2_3 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_I2C_MASK,
@@ -356,7 +356,7 @@ struct pmx_dev pmx_plgpio_4_5 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_SSP_MASK,
@@ -370,7 +370,7 @@ struct pmx_dev pmx_plgpio_6_9 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_MII_MASK,
@@ -384,7 +384,7 @@ struct pmx_dev pmx_plgpio_10_27 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_28_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_GPIO_PIN0_MASK,
@@ -398,7 +398,7 @@ struct pmx_dev pmx_plgpio_28 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_29_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_GPIO_PIN1_MASK,
@@ -412,7 +412,7 @@ struct pmx_dev pmx_plgpio_29 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_30_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_GPIO_PIN2_MASK,
@@ -426,7 +426,7 @@ struct pmx_dev pmx_plgpio_30 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_31_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_GPIO_PIN3_MASK,
@@ -440,7 +440,7 @@ struct pmx_dev pmx_plgpio_31 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_32_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_GPIO_PIN4_MASK,
@@ -454,7 +454,7 @@ struct pmx_dev pmx_plgpio_32 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_33_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_GPIO_PIN5_MASK,
@@ -468,7 +468,7 @@ struct pmx_dev pmx_plgpio_33 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_SSP_CS_MASK,
@@ -482,7 +482,7 @@ struct pmx_dev pmx_plgpio_34_36 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_UART0_MODEM_MASK,
@@ -496,7 +496,7 @@ struct pmx_dev pmx_plgpio_37_42 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_TIMER_1_2_MASK,
@@ -510,7 +510,7 @@ struct pmx_dev pmx_plgpio_43_44_47_48 = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
 	{
 		.ids = 0x00,
 		.mask = PMX_TIMER_3_4_MASK,
-- 
1.5.5



From ryan at bluewatersys.com  Sat Jun  5 02:05:52 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Sat,  5 Jun 2010 18:05:52 +1200
Subject: [PATCH 2/5] SPEAR3xx: Rename register/irq defines to remove naming
	conflicts
In-Reply-To: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1275717955-14545-3-git-send-email-ryan@bluewatersys.com>

Prefix register and irq defintions to remove naming conflicts between
the three SPEAr3xx platforms.

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-spear3xx/include/mach/generic.h  |    4 +-
 arch/arm/mach-spear3xx/include/mach/irqs.h     |  195 ++++++++++++------------
 arch/arm/mach-spear3xx/include/mach/spear300.h |   26 ++--
 arch/arm/mach-spear3xx/include/mach/spear310.h |   44 +++---
 arch/arm/mach-spear3xx/include/mach/spear320.h |   50 +++---
 arch/arm/mach-spear3xx/spear300.c              |   65 ++++----
 arch/arm/mach-spear3xx/spear310.c              |   92 ++++++------
 arch/arm/mach-spear3xx/spear320.c              |  134 ++++++++--------
 arch/arm/mach-spear3xx/spear3xx.c              |    4 +-
 9 files changed, 308 insertions(+), 306 deletions(-)

diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index af7e02c..48dfb9c 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -27,8 +27,8 @@
  * Following GPT channels will be used as clock source and clockevent
  */
 #define SPEAR_GPT0_BASE		SPEAR3XX_ML1_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ	IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ	IRQ_CPU_GPT1_2
+#define SPEAR_GPT0_CHAN0_IRQ	SPEAR3XX_IRQ_CPU_GPT1_1
+#define SPEAR_GPT0_CHAN1_IRQ	SPEAR3XX_IRQ_CPU_GPT1_2
 
 /* Add spear3xx family device structure declarations here */
 extern struct amba_device gpio_device;
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index 7f940b8..668bf72 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -15,138 +15,141 @@
 #define __MACH_IRQS_H
 
 /* SPEAr3xx IRQ definitions */
-#define IRQ_HW_ACCEL_MOD_0			0
-#define IRQ_INTRCOMM_RAS_ARM			1
-#define IRQ_CPU_GPT1_1				2
-#define IRQ_CPU_GPT1_2				3
-#define IRQ_BASIC_GPT1_1			4
-#define IRQ_BASIC_GPT1_2			5
-#define IRQ_BASIC_GPT2_1			6
-#define IRQ_BASIC_GPT2_2			7
-#define IRQ_BASIC_DMA				8
-#define IRQ_BASIC_SMI				9
-#define IRQ_BASIC_RTC				10
-#define IRQ_BASIC_GPIO				11
-#define IRQ_BASIC_WDT				12
-#define IRQ_DDR_CONTROLLER			13
-#define IRQ_SYS_ERROR				14
-#define IRQ_WAKEUP_RCV				15
-#define IRQ_JPEG				16
-#define IRQ_IRDA				17
-#define IRQ_ADC					18
-#define IRQ_UART				19
-#define IRQ_SSP					20
-#define IRQ_I2C					21
-#define IRQ_MAC_1				22
-#define IRQ_MAC_2				23
-#define IRQ_USB_DEV				24
-#define IRQ_USB_H_OHCI_0			25
-#define IRQ_USB_H_EHCI_0			26
-#define IRQ_USB_H_EHCI_1			IRQ_USB_H_EHCI_0
-#define IRQ_USB_H_OHCI_1			27
-#define IRQ_GEN_RAS_1				28
-#define IRQ_GEN_RAS_2				29
-#define IRQ_GEN_RAS_3				30
-#define IRQ_HW_ACCEL_MOD_1			31
-#define IRQ_VIC_END				32
-
-#define VIRQ_START				IRQ_VIC_END
+#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0		0
+#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM		1
+#define SPEAR3XX_IRQ_CPU_GPT1_1			2
+#define SPEAR3XX_IRQ_CPU_GPT1_2			3
+#define SPEAR3XX_IRQ_BASIC_GPT1_1		4
+#define SPEAR3XX_IRQ_BASIC_GPT1_2		5
+#define SPEAR3XX_IRQ_BASIC_GPT2_1		6
+#define SPEAR3XX_IRQ_BASIC_GPT2_2		7
+#define SPEAR3XX_IRQ_BASIC_DMA			8
+#define SPEAR3XX_IRQ_BASIC_SMI			9
+#define SPEAR3XX_IRQ_BASIC_RTC			10
+#define SPEAR3XX_IRQ_BASIC_GPIO			11
+#define SPEAR3XX_IRQ_BASIC_WDT			12
+#define SPEAR3XX_IRQ_DDR_CONTROLLER		13
+#define SPEAR3XX_IRQ_SYS_ERROR			14
+#define SPEAR3XX_IRQ_WAKEUP_RCV			15
+#define SPEAR3XX_IRQ_JPEG			16
+#define SPEAR3XX_IRQ_IRDA			17
+#define SPEAR3XX_IRQ_ADC			18
+#define SPEAR3XX_IRQ_UART			19
+#define SPEAR3XX_IRQ_SSP			20
+#define SPEAR3XX_IRQ_I2C			21
+#define SPEAR3XX_IRQ_MAC_1			22
+#define SPEAR3XX_IRQ_MAC_2			23
+#define SPEAR3XX_IRQ_USB_DEV			24
+#define SPEAR3XX_IRQ_USB_H_OHCI_0		25
+#define SPEAR3XX_IRQ_USB_H_EHCI_0		26
+#define SPEAR3XX_IRQ_USB_H_EHCI_1		SPEAR3XX_IRQ_USB_H_EHCI_0
+#define SPEAR3XX_IRQ_USB_H_OHCI_1		27
+#define SPEAR3XX_IRQ_GEN_RAS_1			28
+#define SPEAR3XX_IRQ_GEN_RAS_2			29
+#define SPEAR3XX_IRQ_GEN_RAS_3			30
+#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1		31
+#define SPEAR3XX_IRQ_VIC_END			32
+
+#define SPEAR3XX_VIRQ_START			SPEAR3XX_IRQ_VIC_END
 
 /* SPEAr300 Virtual irq definitions */
-#ifdef CONFIG_MACH_SPEAR300
 /* IRQs sharing IRQ_GEN_RAS_1 */
-#define VIRQ_IT_PERS_S				(VIRQ_START + 0)
-#define VIRQ_IT_CHANGE_S			(VIRQ_START + 1)
-#define VIRQ_I2S				(VIRQ_START + 2)
-#define VIRQ_TDM				(VIRQ_START + 3)
-#define VIRQ_CAMERA_L				(VIRQ_START + 4)
-#define VIRQ_CAMERA_F				(VIRQ_START + 5)
-#define VIRQ_CAMERA_V				(VIRQ_START + 6)
-#define VIRQ_KEYBOARD				(VIRQ_START + 7)
-#define VIRQ_GPIO1				(VIRQ_START + 8)
+#define SPEAR300_VIRQ_IT_PERS_S			(SPEAR3XX_VIRQ_START + 0)
+#define SPEAR300_VIRQ_IT_CHANGE_S		(SPEAR3XX_VIRQ_START + 1)
+#define SPEAR300_VIRQ_I2S			(SPEAR3XX_VIRQ_START + 2)
+#define SPEAR300_VIRQ_TDM			(SPEAR3XX_VIRQ_START + 3)
+#define SPEAR300_VIRQ_CAMERA_L			(SPEAR3XX_VIRQ_START + 4)
+#define SPEAR300_VIRQ_CAMERA_F			(SPEAR3XX_VIRQ_START + 5)
+#define SPEAR300_VIRQ_CAMERA_V			(SPEAR3XX_VIRQ_START + 6)
+#define SPEAR300_VIRQ_KEYBOARD			(SPEAR3XX_VIRQ_START + 7)
+#define SPEAR300_VIRQ_GPIO1			(SPEAR3XX_VIRQ_START + 8)
 
 /* IRQs sharing IRQ_GEN_RAS_3 */
-#define IRQ_CLCD				IRQ_GEN_RAS_3
+#define SPEAR300_IRQ_CLCD			SPEAR3XX_IRQ_GEN_RAS_3
 
 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define IRQ_SDIO				IRQ_INTRCOMM_RAS_ARM
+#define SPEAR300_IRQ_SDIO			SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
 
 /* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE			(VIRQ_START + 9)
 #define SPEAR_GPIO1_INT_BASE			(SPEAR_GPIO_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END			(SPEAR_GPIO1_INT_BASE + 8)
+//#define SPEAR_GPIO_INT_END			(SPEAR_GPIO1_INT_BASE + 8)
 
 /* SPEAr310 Virtual irq definitions */
-#elif defined(CONFIG_MACH_SPEAR310)
 /* IRQs sharing IRQ_GEN_RAS_1 */
-#define VIRQ_SMII0				(VIRQ_START + 0)
-#define VIRQ_SMII1				(VIRQ_START + 1)
-#define VIRQ_SMII2				(VIRQ_START + 2)
-#define VIRQ_SMII3				(VIRQ_START + 3)
-#define VIRQ_WAKEUP_SMII0			(VIRQ_START + 4)
-#define VIRQ_WAKEUP_SMII1			(VIRQ_START + 5)
-#define VIRQ_WAKEUP_SMII2			(VIRQ_START + 6)
-#define VIRQ_WAKEUP_SMII3			(VIRQ_START + 7)
+#define SPEAR310_VIRQ_SMII0			(SPEAR3XX_VIRQ_START + 0)
+#define SPEAR310_VIRQ_SMII1			(SPEAR3XX_VIRQ_START + 1)
+#define SPEAR310_VIRQ_SMII2			(SPEAR3XX_VIRQ_START + 2)
+#define SPEAR310_VIRQ_SMII3			(SPEAR3XX_VIRQ_START + 3)
+#define SPEAR310_VIRQ_WAKEUP_SMII0		(SPEAR3XX_VIRQ_START + 4)
+#define SPEAR310_VIRQ_WAKEUP_SMII1		(SPEAR3XX_VIRQ_START + 5)
+#define SPEAR310_VIRQ_WAKEUP_SMII2		(SPEAR3XX_VIRQ_START + 6)
+#define SPEAR310_VIRQ_WAKEUP_SMII3		(SPEAR3XX_VIRQ_START + 7)
 
 /* IRQs sharing IRQ_GEN_RAS_2 */
-#define VIRQ_UART1				(VIRQ_START + 8)
-#define VIRQ_UART2				(VIRQ_START + 9)
-#define VIRQ_UART3				(VIRQ_START + 10)
-#define VIRQ_UART4				(VIRQ_START + 11)
-#define VIRQ_UART5				(VIRQ_START + 12)
+#define SPEAR310_VIRQ_UART1			(SPEAR3XX_VIRQ_START + 8)
+#define SPEAR310_VIRQ_UART2			(SPEAR3XX_VIRQ_START + 9)
+#define SPEAR310_VIRQ_UART3			(SPEAR3XX_VIRQ_START + 10)
+#define SPEAR310_VIRQ_UART4			(SPEAR3XX_VIRQ_START + 11)
+#define SPEAR310_VIRQ_UART5			(SPEAR3XX_VIRQ_START + 12)
 
 /* IRQs sharing IRQ_GEN_RAS_3 */
-#define VIRQ_EMI				(VIRQ_START + 13)
-#define VIRQ_PLGPIO				(VIRQ_START + 14)
+#define SPEAR310_VIRQ_EMI			(SPEAR3XX_VIRQ_START + 13)
+#define SPEAR310_VIRQ_PLGPIO			(SPEAR3XX_VIRQ_START + 14)
 
 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define VIRQ_TDM_HDLC				(VIRQ_START + 15)
-#define VIRQ_RS485_0				(VIRQ_START + 16)
-#define VIRQ_RS485_1				(VIRQ_START + 17)
-
-/* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE			(VIRQ_START + 18)
+#define SPEAR310_VIRQ_TDM_HDLC			(SPEAR3XX_VIRQ_START + 15)
+#define SPEAR310_VIRQ_RS485_0			(SPEAR3XX_VIRQ_START + 16)
+#define SPEAR310_VIRQ_RS485_1			(SPEAR3XX_VIRQ_START + 17)
 
 /* SPEAr320 Virtual irq definitions */
-#else
 /* IRQs sharing IRQ_GEN_RAS_1 */
-#define VIRQ_EMI				(VIRQ_START + 0)
-#define VIRQ_CLCD				(VIRQ_START + 1)
-#define VIRQ_SPP				(VIRQ_START + 2)
+#define SPEAR320_VIRQ_EMI			(SPEAR3XX_VIRQ_START + 0)
+#define SPEAR320_VIRQ_CLCD			(SPEAR3XX_VIRQ_START + 1)
+#define SPEAR320_VIRQ_SPP			(SPEAR3XX_VIRQ_START + 2)
 
 /* IRQs sharing IRQ_GEN_RAS_2 */
-#define IRQ_SDIO				IRQ_GEN_RAS_2
+#define SPEAR320_IRQ_SDIO			SPEAR3XX_IRQ_GEN_RAS_2
 
 /* IRQs sharing IRQ_GEN_RAS_3 */
-#define VIRQ_PLGPIO				(VIRQ_START + 3)
-#define VIRQ_I2S_PLAY				(VIRQ_START + 4)
-#define VIRQ_I2S_REC				(VIRQ_START + 5)
+#define SPEAR320_VIRQ_PLGPIO			(SPEAR3XX_VIRQ_START + 3)
+#define SPEAR320_VIRQ_I2S_PLAY			(SPEAR3XX_VIRQ_START + 4)
+#define SPEAR320_VIRQ_I2S_REC			(SPEAR3XX_VIRQ_START + 5)
 
 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define VIRQ_CANU				(VIRQ_START + 6)
-#define VIRQ_CANL				(VIRQ_START + 7)
-#define VIRQ_UART1				(VIRQ_START + 8)
-#define VIRQ_UART2				(VIRQ_START + 9)
-#define VIRQ_SSP1				(VIRQ_START + 10)
-#define VIRQ_SSP2				(VIRQ_START + 11)
-#define VIRQ_SMII0				(VIRQ_START + 12)
-#define VIRQ_MII1_SMII1				(VIRQ_START + 13)
-#define VIRQ_WAKEUP_SMII0			(VIRQ_START + 14)
-#define VIRQ_WAKEUP_MII1_SMII1			(VIRQ_START + 15)
-#define VIRQ_I2C				(VIRQ_START + 16)
-
-/* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE			(VIRQ_START + 17)
+#define SPEAR320_VIRQ_CANU			(SPEAR3XX_VIRQ_START + 6)
+#define SPEAR320_VIRQ_CANL			(SPEAR3XX_VIRQ_START + 7)
+#define SPEAR320_VIRQ_UART1			(SPEAR3XX_VIRQ_START + 8)
+#define SPEAR320_VIRQ_UART2			(SPEAR3XX_VIRQ_START + 9)
+#define SPEAR320_VIRQ_SSP1			(SPEAR3XX_VIRQ_START + 10)
+#define SPEAR320_VIRQ_SSP2			(SPEAR3XX_VIRQ_START + 11)
+#define SPEAR320_VIRQ_SMII0			(SPEAR3XX_VIRQ_START + 12)
+#define SPEAR320_VIRQ_MII1_SMII1		(SPEAR3XX_VIRQ_START + 13)
+#define SPEAR320_VIRQ_WAKEUP_SMII0		(SPEAR3XX_VIRQ_START + 14)
+#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1		(SPEAR3XX_VIRQ_START + 15)
+#define SPEAR320_VIRQ_I2C			(SPEAR3XX_VIRQ_START + 16)
 
+/*
+ * GPIO pins virtual irqs
+ * Use the lowest number for the GPIO virtual IRQs base on which subarchs
+ * we have compiled in
+ */
+#if defined(CONFIG_MACH_SPEAR310)
+#define SPEAR_GPIO_INT_BASE			(SPEAR3XX_VIRQ_START + 18)
+#elif defined(CONFIG_MACH_SPEAR320)
+#define SPEAR_GPIO_INT_BASE			(SPEAR3XX_VIRQ_START + 17)
+#else
+#define SPEAR_GPIO_INT_BASE			(SPEAR3XX_VIRQ_START + 9)
 #endif
 
 /* PLGPIO Virtual IRQs */
 #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
 #define SPEAR_PLGPIO_INT_BASE			(SPEAR_GPIO_INT_BASE + 8)
 #define SPEAR_GPIO_INT_END			(SPEAR_PLGPIO_INT_BASE + 102)
+#else
+#define SPEAR_GPIO_INT_END			(SPEAR_GPIO1_INT_BASE + 8)
 #endif
 
-#define VIRQ_END				SPEAR_GPIO_INT_END
-#define NR_IRQS					VIRQ_END
+#define SPEAR3XX_VIRQ_END			SPEAR_GPIO_INT_END
+#define NR_IRQS					SPEAR3XX_VIRQ_END
 
 #endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index ccaa765..175e574 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -22,19 +22,19 @@
 
 /* Interrupt registers offsets and masks */
 #define SPEAR300_TELECOM_REG_SIZE	0x00010000
-#define INT_ENB_MASK_REG		0x54
-#define INT_STS_MASK_REG		0x58
-#define IT_PERS_S_IRQ_MASK		(1 << 0)
-#define IT_CHANGE_S_IRQ_MASK		(1 << 1)
-#define I2S_IRQ_MASK			(1 << 2)
-#define TDM_IRQ_MASK			(1 << 3)
-#define CAMERA_L_IRQ_MASK		(1 << 4)
-#define CAMERA_F_IRQ_MASK		(1 << 5)
-#define CAMERA_V_IRQ_MASK		(1 << 6)
-#define KEYBOARD_IRQ_MASK		(1 << 7)
-#define GPIO1_IRQ_MASK			(1 << 8)
-
-#define SHIRQ_RAS1_MASK			0x1FF
+#define SPEAR300_INT_ENB_MASK_REG	0x54
+#define SPEAR300_INT_STS_MASK_REG	0x58
+#define SPEAR300_IT_PERS_S_IRQ_MASK	(1 << 0)
+#define SPEAR300_IT_CHANGE_S_IRQ_MASK	(1 << 1)
+#define SPEAR300_I2S_IRQ_MASK		(1 << 2)
+#define SPEAR300_TDM_IRQ_MASK		(1 << 3)
+#define SPEAR300_CAMERA_L_IRQ_MASK	(1 << 4)
+#define SPEAR300_CAMERA_F_IRQ_MASK	(1 << 5)
+#define SPEAR300_CAMERA_V_IRQ_MASK	(1 << 6)
+#define SPEAR300_KEYBOARD_IRQ_MASK	(1 << 7)
+#define SPEAR300_GPIO1_IRQ_MASK		(1 << 8)
+
+#define SPEAR300_SHIRQ_RAS1_MASK	0x1FF
 
 #define SPEAR300_CLCD_BASE		0x60000000
 #define SPEAR300_CLCD_SIZE		0x10000000
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index b27bb8a..d52cd7c 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -41,29 +41,29 @@
 #define SPEAR310_SOC_CONFIG_BASE	0xB4000000
 #define SPEAR310_SOC_CONFIG_SIZE	0x00000070
 /* Interrupt registers offsets and masks */
-#define INT_STS_MASK_REG		0x04
-#define SMII0_IRQ_MASK			(1 << 0)
-#define SMII1_IRQ_MASK			(1 << 1)
-#define SMII2_IRQ_MASK			(1 << 2)
-#define SMII3_IRQ_MASK			(1 << 3)
-#define WAKEUP_SMII0_IRQ_MASK		(1 << 4)
-#define WAKEUP_SMII1_IRQ_MASK		(1 << 5)
-#define WAKEUP_SMII2_IRQ_MASK		(1 << 6)
-#define WAKEUP_SMII3_IRQ_MASK		(1 << 7)
-#define UART1_IRQ_MASK			(1 << 8)
-#define UART2_IRQ_MASK			(1 << 9)
-#define UART3_IRQ_MASK			(1 << 10)
-#define UART4_IRQ_MASK			(1 << 11)
-#define UART5_IRQ_MASK			(1 << 12)
-#define EMI_IRQ_MASK			(1 << 13)
-#define TDM_HDLC_IRQ_MASK		(1 << 14)
-#define RS485_0_IRQ_MASK		(1 << 15)
-#define RS485_1_IRQ_MASK		(1 << 16)
+#define SPEAR310_INT_STS_MASK_REG	0x04
+#define SPEAR310_SMII0_IRQ_MASK		(1 << 0)
+#define SPEAR310_SMII1_IRQ_MASK		(1 << 1)
+#define SPEAR310_SMII2_IRQ_MASK		(1 << 2)
+#define SPEAR310_SMII3_IRQ_MASK		(1 << 3)
+#define SPEAR310_WAKEUP_SMII0_IRQ_MASK	(1 << 4)
+#define SPEAR310_WAKEUP_SMII1_IRQ_MASK	(1 << 5)
+#define SPEAR310_WAKEUP_SMII2_IRQ_MASK	(1 << 6)
+#define SPEAR310_WAKEUP_SMII3_IRQ_MASK	(1 << 7)
+#define SPEAR310_UART1_IRQ_MASK		(1 << 8)
+#define SPEAR310_UART2_IRQ_MASK		(1 << 9)
+#define SPEAR310_UART3_IRQ_MASK		(1 << 10)
+#define SPEAR310_UART4_IRQ_MASK		(1 << 11)
+#define SPEAR310_UART5_IRQ_MASK		(1 << 12)
+#define SPEAR310_EMI_IRQ_MASK		(1 << 13)
+#define SPEAR310_TDM_HDLC_IRQ_MASK	(1 << 14)
+#define SPEAR310_RS485_0_IRQ_MASK	(1 << 15)
+#define SPEAR310_RS485_1_IRQ_MASK	(1 << 16)
 
-#define SHIRQ_RAS1_MASK			0x000FF
-#define SHIRQ_RAS2_MASK			0x01F00
-#define SHIRQ_RAS3_MASK			0x02000
-#define SHIRQ_INTRCOMM_RAS_MASK		0x1C000
+#define SPEAR310_SHIRQ_RAS1_MASK	0x000FF
+#define SPEAR310_SHIRQ_RAS2_MASK	0x01F00
+#define SPEAR310_SHIRQ_RAS3_MASK	0x02000
+#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK	0x1C000
 
 #endif /* __MACH_SPEAR310_H */
 
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index cacf17a..b7c2cab 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -65,31 +65,31 @@
 #define SPEAR320_SOC_CONFIG_BASE	0xB4000000
 #define SPEAR320_SOC_CONFIG_SIZE	0x00000070
 /* Interrupt registers offsets and masks */
-#define INT_STS_MASK_REG		0x04
-#define INT_CLR_MASK_REG		0x04
-#define INT_ENB_MASK_REG		0x08
-#define GPIO_IRQ_MASK			(1 << 0)
-#define I2S_PLAY_IRQ_MASK		(1 << 1)
-#define I2S_REC_IRQ_MASK		(1 << 2)
-#define EMI_IRQ_MASK			(1 << 7)
-#define CLCD_IRQ_MASK			(1 << 8)
-#define SPP_IRQ_MASK			(1 << 9)
-#define SDIO_IRQ_MASK			(1 << 10)
-#define CAN_U_IRQ_MASK			(1 << 11)
-#define CAN_L_IRQ_MASK			(1 << 12)
-#define UART1_IRQ_MASK			(1 << 13)
-#define UART2_IRQ_MASK			(1 << 14)
-#define SSP1_IRQ_MASK			(1 << 15)
-#define SSP2_IRQ_MASK			(1 << 16)
-#define SMII0_IRQ_MASK			(1 << 17)
-#define MII1_SMII1_IRQ_MASK		(1 << 18)
-#define WAKEUP_SMII0_IRQ_MASK		(1 << 19)
-#define WAKEUP_MII1_SMII1_IRQ_MASK	(1 << 20)
-#define I2C1_IRQ_MASK			(1 << 21)
-
-#define SHIRQ_RAS1_MASK			0x000380
-#define SHIRQ_RAS3_MASK			0x000007
-#define SHIRQ_INTRCOMM_RAS_MASK		0x3FF800
+#define SPEAR320_INT_STS_MASK_REG	0x04
+#define SPEAR320_INT_CLR_MASK_REG	0x04
+#define SPEAR320_INT_ENB_MASK_REG	0x08
+#define SPEAR320_GPIO_IRQ_MASK		(1 << 0)
+#define SPEAR320_I2S_PLAY_IRQ_MASK	(1 << 1)
+#define SPEAR320_I2S_REC_IRQ_MASK	(1 << 2)
+#define SPEAR320_EMI_IRQ_MASK		(1 << 7)
+#define SPEAR320_CLCD_IRQ_MASK		(1 << 8)
+#define SPEAR320_SPP_IRQ_MASK		(1 << 9)
+#define SPEAR320_SDIO_IRQ_MASK		(1 << 10)
+#define SPEAR320_CAN_U_IRQ_MASK		(1 << 11)
+#define SPEAR320_CAN_L_IRQ_MASK		(1 << 12)
+#define SPEAR320_UART1_IRQ_MASK		(1 << 13)
+#define SPEAR320_UART2_IRQ_MASK		(1 << 14)
+#define SPEAR320_SSP1_IRQ_MASK		(1 << 15)
+#define SPEAR320_SSP2_IRQ_MASK		(1 << 16)
+#define SPEAR320_SMII0_IRQ_MASK		(1 << 17)
+#define SPEAR320_MII1_SMII1_IRQ_MASK	(1 << 18)
+#define SPEAR320_WAKEUP_SMII0_IRQ_MASK	(1 << 19)
+#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK	(1 << 20)
+#define SPEAR320_I2C1_IRQ_MASK		(1 << 21)
+
+#define SPEAR320_SHIRQ_RAS1_MASK	0x000380
+#define SPEAR320_SHIRQ_RAS3_MASK	0x000007
+#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK	0x3FF800
 
 #endif /* __MACH_SPEAR320_H */
 
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index b71f996..4afe4d4 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -387,59 +387,58 @@ struct amba_device gpio1_device = {
 		.end = SPEAR300_GPIO_BASE + SPEAR300_GPIO_SIZE - 1,
 		.flags = IORESOURCE_MEM,
 	},
-	.irq = {VIRQ_GPIO1, NO_IRQ},
+	.irq = {SPEAR300_VIRQ_GPIO1, NO_IRQ},
 };
 
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
 	{
-		.virq = VIRQ_IT_PERS_S,
-		.enb_mask = IT_PERS_S_IRQ_MASK,
-		.status_mask = IT_PERS_S_IRQ_MASK,
+		.virq = SPEAR300_VIRQ_IT_PERS_S,
+		.enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
+		.status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
 	}, {
-		.virq = VIRQ_IT_CHANGE_S,
-		.enb_mask = IT_CHANGE_S_IRQ_MASK,
-		.status_mask = IT_CHANGE_S_IRQ_MASK,
+		.virq = SPEAR300_VIRQ_IT_CHANGE_S,
+		.enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
+		.status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
 	}, {
-		.virq = VIRQ_I2S,
-		.enb_mask = I2S_IRQ_MASK,
-		.status_mask = I2S_IRQ_MASK,
+		.virq = SPEAR300_VIRQ_I2S,
+		.enb_mask = SPEAR300_I2S_IRQ_MASK,
+		.status_mask = SPEAR300_I2S_IRQ_MASK,
 	}, {
-		.virq = VIRQ_TDM,
-		.enb_mask = TDM_IRQ_MASK,
-		.status_mask = TDM_IRQ_MASK,
+		.virq = SPEAR300_VIRQ_TDM,
+		.enb_mask = SPEAR300_TDM_IRQ_MASK,
+		.status_mask = SPEAR300_TDM_IRQ_MASK,
 	}, {
-		.virq = VIRQ_CAMERA_L,
-		.enb_mask = CAMERA_L_IRQ_MASK,
-		.status_mask = CAMERA_L_IRQ_MASK,
+		.virq = SPEAR300_VIRQ_CAMERA_L,
+		.enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
+		.status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
 	}, {
-		.virq = VIRQ_CAMERA_F,
-		.enb_mask = CAMERA_F_IRQ_MASK,
-		.status_mask = CAMERA_F_IRQ_MASK,
+		.virq = SPEAR300_VIRQ_CAMERA_F,
+		.enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
+		.status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
 	}, {
-		.virq = VIRQ_CAMERA_V,
-		.enb_mask = CAMERA_V_IRQ_MASK,
-		.status_mask = CAMERA_V_IRQ_MASK,
+		.virq = SPEAR300_VIRQ_CAMERA_V,
+		.enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
+		.status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
 	}, {
-		.virq = VIRQ_KEYBOARD,
-		.enb_mask = KEYBOARD_IRQ_MASK,
-		.status_mask = KEYBOARD_IRQ_MASK,
+		.virq = SPEAR300_VIRQ_KEYBOARD,
+		.enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
+		.status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
 	}, {
-		.virq = VIRQ_GPIO1,
-		.enb_mask = GPIO1_IRQ_MASK,
-		.status_mask = GPIO1_IRQ_MASK,
+		.virq = SPEAR300_VIRQ_GPIO1,
+		.enb_mask = SPEAR300_GPIO1_IRQ_MASK,
+		.status_mask = SPEAR300_GPIO1_IRQ_MASK,
 	},
 };
 
-
 static struct spear_shirq shirq_ras1 = {
-	.irq = IRQ_GEN_RAS_1,
+	.irq = SPEAR3XX_IRQ_GEN_RAS_1,
 	.dev_config = shirq_ras1_config,
 	.dev_count = ARRAY_SIZE(shirq_ras1_config),
 	.regs = {
-		.enb_reg = INT_ENB_MASK_REG,
-		.status_reg = INT_STS_MASK_REG,
-		.status_reg_mask = SHIRQ_RAS1_MASK,
+		.enb_reg = SPEAR300_INT_ENB_MASK_REG,
+		.status_reg = SPEAR300_INT_STS_MASK_REG,
+		.status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
 		.clear_reg = -1,
 	},
 };
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 14698b8..550f06f 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -144,115 +144,115 @@ struct pmx_driver pmx_driver = {
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
 	{
-		.virq = VIRQ_SMII0,
-		.status_mask = SMII0_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_SMII0,
+		.status_mask = SPEAR310_SMII0_IRQ_MASK,
 	}, {
-		.virq = VIRQ_SMII1,
-		.status_mask = SMII1_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_SMII1,
+		.status_mask = SPEAR310_SMII1_IRQ_MASK,
 	}, {
-		.virq = VIRQ_SMII2,
-		.status_mask = SMII2_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_SMII2,
+		.status_mask = SPEAR310_SMII2_IRQ_MASK,
 	}, {
-		.virq = VIRQ_SMII3,
-		.status_mask = SMII3_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_SMII3,
+		.status_mask = SPEAR310_SMII3_IRQ_MASK,
 	}, {
-		.virq = VIRQ_WAKEUP_SMII0,
-		.status_mask = WAKEUP_SMII0_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_WAKEUP_SMII0,
+		.status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
 	}, {
-		.virq = VIRQ_WAKEUP_SMII1,
-		.status_mask = WAKEUP_SMII1_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_WAKEUP_SMII1,
+		.status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
 	}, {
-		.virq = VIRQ_WAKEUP_SMII2,
-		.status_mask = WAKEUP_SMII2_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_WAKEUP_SMII2,
+		.status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
 	}, {
-		.virq = VIRQ_WAKEUP_SMII3,
-		.status_mask = WAKEUP_SMII3_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_WAKEUP_SMII3,
+		.status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
 	},
 };
 
 static struct spear_shirq shirq_ras1 = {
-	.irq = IRQ_GEN_RAS_1,
+	.irq = SPEAR3XX_IRQ_GEN_RAS_1,
 	.dev_config = shirq_ras1_config,
 	.dev_count = ARRAY_SIZE(shirq_ras1_config),
 	.regs = {
 		.enb_reg = -1,
-		.status_reg = INT_STS_MASK_REG,
-		.status_reg_mask = SHIRQ_RAS1_MASK,
+		.status_reg = SPEAR310_INT_STS_MASK_REG,
+		.status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
 		.clear_reg = -1,
 	},
 };
 
 static struct shirq_dev_config shirq_ras2_config[] = {
 	{
-		.virq = VIRQ_UART1,
-		.status_mask = UART1_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_UART1,
+		.status_mask = SPEAR310_UART1_IRQ_MASK,
 	}, {
-		.virq = VIRQ_UART2,
-		.status_mask = UART2_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_UART2,
+		.status_mask = SPEAR310_UART2_IRQ_MASK,
 	}, {
-		.virq = VIRQ_UART3,
-		.status_mask = UART3_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_UART3,
+		.status_mask = SPEAR310_UART3_IRQ_MASK,
 	}, {
-		.virq = VIRQ_UART4,
-		.status_mask = UART4_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_UART4,
+		.status_mask = SPEAR310_UART4_IRQ_MASK,
 	}, {
-		.virq = VIRQ_UART5,
-		.status_mask = UART5_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_UART5,
+		.status_mask = SPEAR310_UART5_IRQ_MASK,
 	},
 };
 
 static struct spear_shirq shirq_ras2 = {
-	.irq = IRQ_GEN_RAS_2,
+	.irq = SPEAR3XX_IRQ_GEN_RAS_2,
 	.dev_config = shirq_ras2_config,
 	.dev_count = ARRAY_SIZE(shirq_ras2_config),
 	.regs = {
 		.enb_reg = -1,
-		.status_reg = INT_STS_MASK_REG,
-		.status_reg_mask = SHIRQ_RAS2_MASK,
+		.status_reg = SPEAR310_INT_STS_MASK_REG,
+		.status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
 		.clear_reg = -1,
 	},
 };
 
 static struct shirq_dev_config shirq_ras3_config[] = {
 	{
-		.virq = VIRQ_EMI,
-		.status_mask = EMI_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_EMI,
+		.status_mask = SPEAR310_EMI_IRQ_MASK,
 	},
 };
 
 static struct spear_shirq shirq_ras3 = {
-	.irq = IRQ_GEN_RAS_3,
+	.irq = SPEAR3XX_IRQ_GEN_RAS_3,
 	.dev_config = shirq_ras3_config,
 	.dev_count = ARRAY_SIZE(shirq_ras3_config),
 	.regs = {
 		.enb_reg = -1,
-		.status_reg = INT_STS_MASK_REG,
-		.status_reg_mask = SHIRQ_RAS3_MASK,
+		.status_reg = SPEAR310_INT_STS_MASK_REG,
+		.status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
 		.clear_reg = -1,
 	},
 };
 
 static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 	{
-		.virq = VIRQ_TDM_HDLC,
-		.status_mask = TDM_HDLC_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_TDM_HDLC,
+		.status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
 	}, {
-		.virq = VIRQ_RS485_0,
-		.status_mask = RS485_0_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_RS485_0,
+		.status_mask = SPEAR310_RS485_0_IRQ_MASK,
 	}, {
-		.virq = VIRQ_RS485_1,
-		.status_mask = RS485_1_IRQ_MASK,
+		.virq = SPEAR310_VIRQ_RS485_1,
+		.status_mask = SPEAR310_RS485_1_IRQ_MASK,
 	},
 };
 
 static struct spear_shirq shirq_intrcomm_ras = {
-	.irq = IRQ_INTRCOMM_RAS_ARM,
+	.irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
 	.dev_config = shirq_intrcomm_ras_config,
 	.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
 	.regs = {
 		.enb_reg = -1,
-		.status_reg = INT_STS_MASK_REG,
-		.status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
+		.status_reg = SPEAR310_INT_STS_MASK_REG,
+		.status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
 		.clear_reg = -1,
 	},
 };
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 958e52d..768aa8c 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -389,123 +389,123 @@ struct pmx_driver pmx_driver = {
 /* spear3xx shared irq */
 static struct shirq_dev_config shirq_ras1_config[] = {
 	{
-		.virq = VIRQ_EMI,
-		.status_mask = EMI_IRQ_MASK,
-		.clear_mask = EMI_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_EMI,
+		.status_mask = SPEAR320_EMI_IRQ_MASK,
+		.clear_mask = SPEAR320_EMI_IRQ_MASK,
 	}, {
-		.virq = VIRQ_CLCD,
-		.status_mask = CLCD_IRQ_MASK,
-		.clear_mask = CLCD_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_CLCD,
+		.status_mask = SPEAR320_CLCD_IRQ_MASK,
+		.clear_mask = SPEAR320_CLCD_IRQ_MASK,
 	}, {
-		.virq = VIRQ_SPP,
-		.status_mask = SPP_IRQ_MASK,
-		.clear_mask = SPP_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_SPP,
+		.status_mask = SPEAR320_SPP_IRQ_MASK,
+		.clear_mask = SPEAR320_SPP_IRQ_MASK,
 	},
 };
 
 static struct spear_shirq shirq_ras1 = {
-	.irq = IRQ_GEN_RAS_1,
+	.irq = SPEAR3XX_IRQ_GEN_RAS_1,
 	.dev_config = shirq_ras1_config,
 	.dev_count = ARRAY_SIZE(shirq_ras1_config),
 	.regs = {
 		.enb_reg = -1,
-		.status_reg = INT_STS_MASK_REG,
-		.status_reg_mask = SHIRQ_RAS1_MASK,
-		.clear_reg = INT_CLR_MASK_REG,
+		.status_reg = SPEAR320_INT_STS_MASK_REG,
+		.status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
+		.clear_reg = SPEAR320_INT_CLR_MASK_REG,
 		.reset_to_clear = 1,
 	},
 };
 
 static struct shirq_dev_config shirq_ras3_config[] = {
 	{
-		.virq = VIRQ_PLGPIO,
-		.enb_mask = GPIO_IRQ_MASK,
-		.status_mask = GPIO_IRQ_MASK,
-		.clear_mask = GPIO_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_PLGPIO,
+		.enb_mask = SPEAR320_GPIO_IRQ_MASK,
+		.status_mask = SPEAR320_GPIO_IRQ_MASK,
+		.clear_mask = SPEAR320_GPIO_IRQ_MASK,
 	}, {
-		.virq = VIRQ_I2S_PLAY,
-		.enb_mask = I2S_PLAY_IRQ_MASK,
-		.status_mask = I2S_PLAY_IRQ_MASK,
-		.clear_mask = I2S_PLAY_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_I2S_PLAY,
+		.enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
+		.status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
+		.clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
 	}, {
-		.virq = VIRQ_I2S_REC,
-		.enb_mask = I2S_REC_IRQ_MASK,
-		.status_mask = I2S_REC_IRQ_MASK,
-		.clear_mask = I2S_REC_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_I2S_REC,
+		.enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
+		.status_mask = SPEAR320_I2S_REC_IRQ_MASK,
+		.clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
 	},
 };
 
 static struct spear_shirq shirq_ras3 = {
-	.irq = IRQ_GEN_RAS_3,
+	.irq = SPEAR3XX_IRQ_GEN_RAS_3,
 	.dev_config = shirq_ras3_config,
 	.dev_count = ARRAY_SIZE(shirq_ras3_config),
 	.regs = {
-		.enb_reg = INT_ENB_MASK_REG,
+		.enb_reg = SPEAR320_INT_ENB_MASK_REG,
 		.reset_to_enb = 1,
-		.status_reg = INT_STS_MASK_REG,
-		.status_reg_mask = SHIRQ_RAS3_MASK,
-		.clear_reg = INT_CLR_MASK_REG,
+		.status_reg = SPEAR320_INT_STS_MASK_REG,
+		.status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
+		.clear_reg = SPEAR320_INT_CLR_MASK_REG,
 		.reset_to_clear = 1,
 	},
 };
 
 static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
 	{
-		.virq = VIRQ_CANU,
-		.status_mask = CAN_U_IRQ_MASK,
-		.clear_mask = CAN_U_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_CANU,
+		.status_mask = SPEAR320_CAN_U_IRQ_MASK,
+		.clear_mask = SPEAR320_CAN_U_IRQ_MASK,
 	}, {
-		.virq = VIRQ_CANL,
-		.status_mask = CAN_L_IRQ_MASK,
-		.clear_mask = CAN_L_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_CANL,
+		.status_mask = SPEAR320_CAN_L_IRQ_MASK,
+		.clear_mask = SPEAR320_CAN_L_IRQ_MASK,
 	}, {
-		.virq = VIRQ_UART1,
-		.status_mask = UART1_IRQ_MASK,
-		.clear_mask = UART1_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_UART1,
+		.status_mask = SPEAR320_UART1_IRQ_MASK,
+		.clear_mask = SPEAR320_UART1_IRQ_MASK,
 	}, {
-		.virq = VIRQ_UART2,
-		.status_mask = UART2_IRQ_MASK,
-		.clear_mask = UART2_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_UART2,
+		.status_mask = SPEAR320_UART2_IRQ_MASK,
+		.clear_mask = SPEAR320_UART2_IRQ_MASK,
 	}, {
-		.virq = VIRQ_SSP1,
-		.status_mask = SSP1_IRQ_MASK,
-		.clear_mask = SSP1_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_SSP1,
+		.status_mask = SPEAR320_SSP1_IRQ_MASK,
+		.clear_mask = SPEAR320_SSP1_IRQ_MASK,
 	}, {
-		.virq = VIRQ_SSP2,
-		.status_mask = SSP2_IRQ_MASK,
-		.clear_mask = SSP2_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_SSP2,
+		.status_mask = SPEAR320_SSP2_IRQ_MASK,
+		.clear_mask = SPEAR320_SSP2_IRQ_MASK,
 	}, {
-		.virq = VIRQ_SMII0,
-		.status_mask = SMII0_IRQ_MASK,
-		.clear_mask = SMII0_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_SMII0,
+		.status_mask = SPEAR320_SMII0_IRQ_MASK,
+		.clear_mask = SPEAR320_SMII0_IRQ_MASK,
 	}, {
-		.virq = VIRQ_MII1_SMII1,
-		.status_mask = MII1_SMII1_IRQ_MASK,
-		.clear_mask = MII1_SMII1_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_MII1_SMII1,
+		.status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
+		.clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
 	}, {
-		.virq = VIRQ_WAKEUP_SMII0,
-		.status_mask = WAKEUP_SMII0_IRQ_MASK,
-		.clear_mask = WAKEUP_SMII0_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_WAKEUP_SMII0,
+		.status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
+		.clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
 	}, {
-		.virq = VIRQ_WAKEUP_MII1_SMII1,
-		.status_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
-		.clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
+		.status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
+		.clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
 	}, {
-		.virq = VIRQ_I2C,
-		.status_mask = I2C1_IRQ_MASK,
-		.clear_mask = I2C1_IRQ_MASK,
+		.virq = SPEAR320_VIRQ_I2C,
+		.status_mask = SPEAR320_I2C1_IRQ_MASK,
+		.clear_mask = SPEAR320_I2C1_IRQ_MASK,
 	},
 };
 
 static struct spear_shirq shirq_intrcomm_ras = {
-	.irq = IRQ_INTRCOMM_RAS_ARM,
+	.irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
 	.dev_config = shirq_intrcomm_ras_config,
 	.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
 	.regs = {
 		.enb_reg = -1,
-		.status_reg = INT_STS_MASK_REG,
-		.status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
-		.clear_reg = INT_CLR_MASK_REG,
+		.status_reg = SPEAR320_INT_STS_MASK_REG,
+		.status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
+		.clear_reg = SPEAR320_INT_CLR_MASK_REG,
 		.reset_to_clear = 1,
 	},
 };
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 5f2cddc..0efd8d7 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -38,7 +38,7 @@ struct amba_device gpio_device = {
 		.end = SPEAR3XX_ICM3_GPIO_BASE + SPEAR3XX_ICM3_GPIO_SIZE - 1,
 		.flags = IORESOURCE_MEM,
 	},
-	.irq = {IRQ_BASIC_GPIO, NO_IRQ},
+	.irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ},
 };
 
 /* uart device registeration */
@@ -51,7 +51,7 @@ struct amba_device uart_device = {
 		.end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1,
 		.flags = IORESOURCE_MEM,
 	},
-	.irq = {IRQ_UART, NO_IRQ},
+	.irq = {SPEAR3XX_IRQ_UART, NO_IRQ},
 };
 
 /* Do spear3xx familiy common initialization part here */
-- 
1.5.5



From ryan at bluewatersys.com  Sat Jun  5 02:05:53 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Sat,  5 Jun 2010 18:05:53 +1200
Subject: [PATCH 3/5] SPEAr3xx: Rework pmx_dev code to remove conflicts
In-Reply-To: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1275717955-14545-4-git-send-email-ryan@bluewatersys.com>

Prefix the pmx_devs to remove naming conflicts between the three
SPEAr3xx platforms. Also make pmx_driver static to each platform and
rework the init code to pass the devices rather than export the
pmx_driver structure.

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-spear3xx/include/mach/generic.h |  135 ++++++++++++-------------
 arch/arm/mach-spear3xx/spear300.c             |   39 ++++----
 arch/arm/mach-spear3xx/spear300_evb.c         |   26 ++---
 arch/arm/mach-spear3xx/spear310.c             |   29 +++---
 arch/arm/mach-spear3xx/spear310_evb.c         |   42 ++++-----
 arch/arm/mach-spear3xx/spear320.c             |   57 ++++++-----
 arch/arm/mach-spear3xx/spear320_evb.c         |   36 +++----
 arch/arm/mach-spear3xx/spear3xx.c             |   60 ++++++------
 8 files changed, 202 insertions(+), 222 deletions(-)

diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 48dfb9c..408d39f 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -60,21 +60,21 @@ void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size);
 #define PMX_TIMER_1_2_MASK	(1 << 0)
 
 /* pad mux devices */
-extern struct pmx_dev pmx_firda;
-extern struct pmx_dev pmx_i2c;
-extern struct pmx_dev pmx_ssp_cs;
-extern struct pmx_dev pmx_ssp;
-extern struct pmx_dev pmx_mii;
-extern struct pmx_dev pmx_gpio_pin0;
-extern struct pmx_dev pmx_gpio_pin1;
-extern struct pmx_dev pmx_gpio_pin2;
-extern struct pmx_dev pmx_gpio_pin3;
-extern struct pmx_dev pmx_gpio_pin4;
-extern struct pmx_dev pmx_gpio_pin5;
-extern struct pmx_dev pmx_uart0_modem;
-extern struct pmx_dev pmx_uart0;
-extern struct pmx_dev pmx_timer_3_4;
-extern struct pmx_dev pmx_timer_1_2;
+extern struct pmx_dev spear3xx_pmx_firda;
+extern struct pmx_dev spear3xx_pmx_i2c;
+extern struct pmx_dev spear3xx_pmx_ssp_cs;
+extern struct pmx_dev spear3xx_pmx_ssp;
+extern struct pmx_dev spear3xx_pmx_mii;
+extern struct pmx_dev spear3xx_pmx_gpio_pin0;
+extern struct pmx_dev spear3xx_pmx_gpio_pin1;
+extern struct pmx_dev spear3xx_pmx_gpio_pin2;
+extern struct pmx_dev spear3xx_pmx_gpio_pin3;
+extern struct pmx_dev spear3xx_pmx_gpio_pin4;
+extern struct pmx_dev spear3xx_pmx_gpio_pin5;
+extern struct pmx_dev spear3xx_pmx_uart0_modem;
+extern struct pmx_dev spear3xx_pmx_uart0;
+extern struct pmx_dev spear3xx_pmx_timer_3_4;
+extern struct pmx_dev spear3xx_pmx_timer_1_2;
 
 #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
 /* padmux plgpio devices */
@@ -95,8 +95,6 @@ extern struct pmx_dev pmx_plgpio_43_44_47_48;
 extern struct pmx_dev pmx_plgpio_45_46_49_50;
 #endif
 
-extern struct pmx_driver pmx_driver;
-
 /* spear300 declarations */
 #ifdef CONFIG_MACH_SPEAR300
 /* Add spear300 machine device structure declarations here */
@@ -118,25 +116,24 @@ extern struct pmx_mode camu_wlcd_mode;
 extern struct pmx_mode caml_lcd_mode;
 
 /* pad mux devices */
-extern struct pmx_dev pmx_fsmc_2_chips;
-extern struct pmx_dev pmx_fsmc_4_chips;
-extern struct pmx_dev pmx_keyboard;
-extern struct pmx_dev pmx_clcd;
-extern struct pmx_dev pmx_telecom_gpio;
-extern struct pmx_dev pmx_telecom_tdm;
-extern struct pmx_dev pmx_telecom_spi_cs_i2c_clk;
-extern struct pmx_dev pmx_telecom_camera;
-extern struct pmx_dev pmx_telecom_dac;
-extern struct pmx_dev pmx_telecom_i2s;
-extern struct pmx_dev pmx_telecom_boot_pins;
-extern struct pmx_dev pmx_telecom_sdio_4bit;
-extern struct pmx_dev pmx_telecom_sdio_8bit;
-extern struct pmx_dev pmx_gpio1;
-
-void spear300_pmx_init(void);
+extern struct pmx_dev spear300_pmx_fsmc_2_chips;
+extern struct pmx_dev spear300_pmx_fsmc_4_chips;
+extern struct pmx_dev spear300_pmx_keyboard;
+extern struct pmx_dev spear300_pmx_clcd;
+extern struct pmx_dev spear300_pmx_telecom_gpio;
+extern struct pmx_dev spear300_pmx_telecom_tdm;
+extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
+extern struct pmx_dev spear300_pmx_telecom_camera;
+extern struct pmx_dev spear300_pmx_telecom_dac;
+extern struct pmx_dev spear300_pmx_telecom_i2s;
+extern struct pmx_dev spear300_pmx_telecom_boot_pins;
+extern struct pmx_dev spear300_pmx_telecom_sdio_4bit;
+extern struct pmx_dev spear300_pmx_telecom_sdio_8bit;
+extern struct pmx_dev spear300_pmx_gpio1;
 
 /* Add spear300 machine function declarations here */
-void __init spear300_init(void);
+void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pxm_devs,
+			  u8 pmx_dev_count);
 
 #endif /* CONFIG_MACH_SPEAR300 */
 
@@ -145,19 +142,18 @@ void __init spear300_init(void);
 /* Add spear310 machine device structure declarations here */
 
 /* pad mux devices */
-extern struct pmx_dev pmx_emi_cs_0_1_4_5;
-extern struct pmx_dev pmx_emi_cs_2_3;
-extern struct pmx_dev pmx_uart1;
-extern struct pmx_dev pmx_uart2;
-extern struct pmx_dev pmx_uart3_4_5;
-extern struct pmx_dev pmx_fsmc;
-extern struct pmx_dev pmx_rs485_0_1;
-extern struct pmx_dev pmx_tdm0;
-
-void spear310_pmx_init(void);
+extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
+extern struct pmx_dev spear310_pmx_emi_cs_2_3;
+extern struct pmx_dev spear310_pmx_uart1;
+extern struct pmx_dev spear310_pmx_uart2;
+extern struct pmx_dev spear310_pmx_uart3_4_5;
+extern struct pmx_dev spear310_pmx_fsmc;
+extern struct pmx_dev spear310_pmx_rs485_0_1;
+extern struct pmx_dev spear310_pmx_tdm0;
 
 /* Add spear310 machine function declarations here */
-void __init spear310_init(void);
+void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pxm_devs,
+			  u8 pmx_dev_count);
 
 #endif /* CONFIG_MACH_SPEAR310 */
 
@@ -172,33 +168,32 @@ extern struct pmx_mode auto_exp_mode;
 extern struct pmx_mode small_printers_mode;
 
 /* pad mux devices */
-extern struct pmx_dev pmx_clcd;
-extern struct pmx_dev pmx_emi;
-extern struct pmx_dev pmx_fsmc;
-extern struct pmx_dev pmx_spp;
-extern struct pmx_dev pmx_sdio;
-extern struct pmx_dev pmx_i2s;
-extern struct pmx_dev pmx_uart1;
-extern struct pmx_dev pmx_uart1_modem;
-extern struct pmx_dev pmx_uart2;
-extern struct pmx_dev pmx_touchscreen;
-extern struct pmx_dev pmx_can;
-extern struct pmx_dev pmx_sdio_led;
-extern struct pmx_dev pmx_pwm0;
-extern struct pmx_dev pmx_pwm1;
-extern struct pmx_dev pmx_pwm2;
-extern struct pmx_dev pmx_pwm3;
-extern struct pmx_dev pmx_ssp1;
-extern struct pmx_dev pmx_ssp2;
-extern struct pmx_dev pmx_mii1;
-extern struct pmx_dev pmx_smii0;
-extern struct pmx_dev pmx_smii1;
-extern struct pmx_dev pmx_i2c1;
-
-void spear320_pmx_init(void);
+extern struct pmx_dev spear320_pmx_clcd;
+extern struct pmx_dev spear320_pmx_emi;
+extern struct pmx_dev spear320_pmx_fsmc;
+extern struct pmx_dev spear320_pmx_spp;
+extern struct pmx_dev spear320_pmx_sdio;
+extern struct pmx_dev spear320_pmx_i2s;
+extern struct pmx_dev spear320_pmx_uart1;
+extern struct pmx_dev spear320_pmx_uart1_modem;
+extern struct pmx_dev spear320_pmx_uart2;
+extern struct pmx_dev spear320_pmx_touchscreen;
+extern struct pmx_dev spear320_pmx_can;
+extern struct pmx_dev spear320_pmx_sdio_led;
+extern struct pmx_dev spear320_pmx_pwm0;
+extern struct pmx_dev spear320_pmx_pwm1;
+extern struct pmx_dev spear320_pmx_pwm2;
+extern struct pmx_dev spear320_pmx_pwm3;
+extern struct pmx_dev spear320_pmx_ssp1;
+extern struct pmx_dev spear320_pmx_ssp2;
+extern struct pmx_dev spear320_pmx_mii1;
+extern struct pmx_dev spear320_pmx_smii0;
+extern struct pmx_dev spear320_pmx_smii1;
+extern struct pmx_dev spear320_pmx_i2c1;
 
 /* Add spear320 machine function declarations here */
-void __init spear320_init(void);
+void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pxm_devs,
+			  u8 pmx_dev_count);
 
 #endif /* CONFIG_MACH_SPEAR320 */
 
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 4afe4d4..11acd8e 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -127,7 +127,7 @@ static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_fsmc_2_chips = {
+struct pmx_dev spear300_pmx_fsmc_2_chips = {
 	.name = "fsmc_2_chips",
 	.modes = pmx_fsmc_2_chips_modes,
 	.mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
@@ -142,7 +142,7 @@ static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_fsmc_4_chips = {
+struct pmx_dev spear300_pmx_fsmc_4_chips = {
 	.name = "fsmc_4_chips",
 	.modes = pmx_fsmc_4_chips_modes,
 	.mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
@@ -159,7 +159,7 @@ static struct pmx_dev_mode pmx_keyboard_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_keyboard = {
+struct pmx_dev spear300_pmx_keyboard = {
 	.name = "keyboard",
 	.modes = pmx_keyboard_modes,
 	.mode_count = ARRAY_SIZE(pmx_keyboard_modes),
@@ -177,7 +177,7 @@ static struct pmx_dev_mode pmx_clcd_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_clcd = {
+struct pmx_dev spear300_pmx_clcd = {
 	.name = "clcd",
 	.modes = pmx_clcd_modes,
 	.mode_count = ARRAY_SIZE(pmx_clcd_modes),
@@ -222,7 +222,7 @@ static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_telecom_tdm = {
+struct pmx_dev spear300_pmx_telecom_tdm = {
 	.name = "telecom_tdm",
 	.modes = pmx_telecom_tdm_modes,
 	.mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
@@ -239,7 +239,7 @@ static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_telecom_spi_cs_i2c_clk = {
+struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
 	.name = "telecom_spi_cs_i2c_clk",
 	.modes = pmx_telecom_spi_cs_i2c_clk_modes,
 	.mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
@@ -256,7 +256,7 @@ static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_telecom_camera = {
+struct pmx_dev spear300_pmx_telecom_camera = {
 	.name = "telecom_camera",
 	.modes = pmx_telecom_camera_modes,
 	.mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
@@ -271,7 +271,7 @@ static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_telecom_dac = {
+struct pmx_dev spear300_pmx_telecom_dac = {
 	.name = "telecom_dac",
 	.modes = pmx_telecom_dac_modes,
 	.mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
@@ -288,7 +288,7 @@ static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_telecom_i2s = {
+struct pmx_dev spear300_pmx_telecom_i2s = {
 	.name = "telecom_i2s",
 	.modes = pmx_telecom_i2s_modes,
 	.mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
@@ -303,7 +303,7 @@ static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_telecom_boot_pins = {
+struct pmx_dev spear300_pmx_telecom_boot_pins = {
 	.name = "telecom_boot_pins",
 	.modes = pmx_telecom_boot_pins_modes,
 	.mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
@@ -323,7 +323,7 @@ static struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_telecom_sdio_4bit = {
+struct pmx_dev spear300_pmx_telecom_sdio_4bit = {
 	.name = "telecom_sdio_4bit",
 	.modes = pmx_telecom_sdio_4bit_modes,
 	.mode_count = ARRAY_SIZE(pmx_telecom_sdio_4bit_modes),
@@ -342,7 +342,7 @@ static struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_telecom_sdio_8bit = {
+struct pmx_dev spear300_pmx_telecom_sdio_8bit = {
 	.name = "telecom_sdio_8bit",
 	.modes = pmx_telecom_sdio_8bit_modes,
 	.mode_count = ARRAY_SIZE(pmx_telecom_sdio_8bit_modes),
@@ -357,7 +357,7 @@ static struct pmx_dev_mode pmx_gpio1_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_gpio1 = {
+struct pmx_dev spear300_pmx_gpio1 = {
 	.name = "arm gpio1",
 	.modes = pmx_gpio1_modes,
 	.mode_count = ARRAY_SIZE(pmx_gpio1_modes),
@@ -365,7 +365,7 @@ struct pmx_dev pmx_gpio1 = {
 };
 
 /* pmx driver structure */
-struct pmx_driver pmx_driver = {
+static struct pmx_driver pmx_driver = {
 	.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
 	.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 };
@@ -444,7 +444,8 @@ static struct spear_shirq shirq_ras1 = {
 };
 
 /* spear300 routines */
-void __init spear300_init(void)
+void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+			  u8 pmx_dev_count)
 {
 	int ret = 0;
 
@@ -459,10 +460,10 @@ void __init spear300_init(void)
 		if (ret)
 			printk(KERN_ERR "Error registering Shared IRQ\n");
 	}
-}
 
-void spear300_pmx_init(void)
-{
+	pmx_driver.mode = pmx_mode;
+	pmx_driver.devs = pmx_devs;
+	pmx_driver.devs_count = pmx_dev_count;
 	spear_pmx_init(&pmx_driver, SPEAR300_SOC_CONFIG_BASE,
-			SPEAR300_SOC_CONFIG_SIZE);
+		       SPEAR300_SOC_CONFIG_SIZE);
 }
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index bb21db1..5ae5f6a 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -19,17 +19,17 @@
 /* padmux devices to enable */
 static struct pmx_dev *pmx_devs[] = {
 	/* spear3xx specific devices */
-	&pmx_i2c,
-	&pmx_ssp_cs,
-	&pmx_ssp,
-	&pmx_mii,
-	&pmx_uart0,
+	&spear3xx_pmx_i2c,
+	&spear3xx_pmx_ssp_cs,
+	&spear3xx_pmx_ssp,
+	&spear3xx_pmx_mii,
+	&spear3xx_pmx_uart0,
 
 	/* spear300 specific devices */
-	&pmx_fsmc_2_chips,
-	&pmx_clcd,
-	&pmx_telecom_sdio_4bit,
-	&pmx_gpio1,
+	&spear300_pmx_fsmc_2_chips,
+	&spear300_pmx_clcd,
+	&spear300_pmx_telecom_sdio_4bit,
+	&spear300_pmx_gpio1,
 };
 
 static struct amba_device *amba_devs[] __initdata = {
@@ -52,13 +52,7 @@ static void __init spear300_evb_init(void)
 	unsigned int i;
 
 	/* call spear300 machine init function */
-	spear300_init();
-
-	/* padmux initialization */
-	pmx_driver.mode = &photo_frame_mode;
-	pmx_driver.devs = pmx_devs;
-	pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-	spear300_pmx_init();
+	spear300_init(&photo_frame_mode, pmx_devs, ARRAY_SIZE(pmx_devs));
 
 	/* Add Platform Devices */
 	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 550f06f..0646170 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -29,7 +29,7 @@ struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_emi_cs_0_1_4_5 = {
+struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
 	.name = "emi_cs_0_1_4_5",
 	.modes = pmx_emi_cs_0_1_4_5_modes,
 	.mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
@@ -43,7 +43,7 @@ struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_emi_cs_2_3 = {
+struct pmx_dev spear310_pmx_emi_cs_2_3 = {
 	.name = "emi_cs_2_3",
 	.modes = pmx_emi_cs_2_3_modes,
 	.mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
@@ -57,7 +57,7 @@ struct pmx_dev_mode pmx_uart1_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_uart1 = {
+struct pmx_dev spear310_pmx_uart1 = {
 	.name = "uart1",
 	.modes = pmx_uart1_modes,
 	.mode_count = ARRAY_SIZE(pmx_uart1_modes),
@@ -71,7 +71,7 @@ struct pmx_dev_mode pmx_uart2_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_uart2 = {
+struct pmx_dev spear310_pmx_uart2 = {
 	.name = "uart2",
 	.modes = pmx_uart2_modes,
 	.mode_count = ARRAY_SIZE(pmx_uart2_modes),
@@ -85,7 +85,7 @@ struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_uart3_4_5 = {
+struct pmx_dev spear310_pmx_uart3_4_5 = {
 	.name = "uart3_4_5",
 	.modes = pmx_uart3_4_5_modes,
 	.mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
@@ -99,7 +99,7 @@ struct pmx_dev_mode pmx_fsmc_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_fsmc = {
+struct pmx_dev spear310_pmx_fsmc = {
 	.name = "fsmc",
 	.modes = pmx_fsmc_modes,
 	.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
@@ -113,7 +113,7 @@ struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_rs485_0_1 = {
+struct pmx_dev spear310_pmx_rs485_0_1 = {
 	.name = "rs485_0_1",
 	.modes = pmx_rs485_0_1_modes,
 	.mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
@@ -127,7 +127,7 @@ struct pmx_dev_mode pmx_tdm0_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_tdm0 = {
+struct pmx_dev spear310_pmx_tdm0 = {
 	.name = "tdm0",
 	.modes = pmx_tdm0_modes,
 	.mode_count = ARRAY_SIZE(pmx_tdm0_modes),
@@ -135,7 +135,7 @@ struct pmx_dev pmx_tdm0 = {
 };
 
 /* pmx driver structure */
-struct pmx_driver pmx_driver = {
+static struct pmx_driver pmx_driver = {
 	.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 };
 
@@ -258,7 +258,8 @@ static struct spear_shirq shirq_intrcomm_ras = {
 };
 
 /* spear310 routines */
-void __init spear310_init(void)
+void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+			  u8 pmx_dev_count)
 {
 	void __iomem *base;
 	int ret = 0;
@@ -293,10 +294,10 @@ void __init spear310_init(void)
 		if (ret)
 			printk(KERN_ERR "Error registering Shared IRQ 4\n");
 	}
-}
 
-void spear310_pmx_init(void)
-{
+	pmx_driver.mode = pmx_mode;
+	pmx_driver.devs = pmx_devs;
+	pmx_driver.devs_count = pmx_dev_count;
 	spear_pmx_init(&pmx_driver, SPEAR310_SOC_CONFIG_BASE,
-			SPEAR310_SOC_CONFIG_SIZE);
+		       SPEAR310_SOC_CONFIG_SIZE);
 }
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 7facf66..c9e3f41 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -19,25 +19,25 @@
 /* padmux devices to enable */
 static struct pmx_dev *pmx_devs[] = {
 	/* spear3xx specific devices */
-	&pmx_i2c,
-	&pmx_ssp,
-	&pmx_gpio_pin0,
-	&pmx_gpio_pin1,
-	&pmx_gpio_pin2,
-	&pmx_gpio_pin3,
-	&pmx_gpio_pin4,
-	&pmx_gpio_pin5,
-	&pmx_uart0,
+	&spear3xx_pmx_i2c,
+	&spear3xx_pmx_ssp,
+	&spear3xx_pmx_gpio_pin0,
+	&spear3xx_pmx_gpio_pin1,
+	&spear3xx_pmx_gpio_pin2,
+	&spear3xx_pmx_gpio_pin3,
+	&spear3xx_pmx_gpio_pin4,
+	&spear3xx_pmx_gpio_pin5,
+	&spear3xx_pmx_uart0,
 
 	/* spear310 specific devices */
-	&pmx_emi_cs_0_1_4_5,
-	&pmx_emi_cs_2_3,
-	&pmx_uart1,
-	&pmx_uart2,
-	&pmx_uart3_4_5,
-	&pmx_fsmc,
-	&pmx_rs485_0_1,
-	&pmx_tdm0,
+	&spear310_pmx_emi_cs_0_1_4_5,
+	&spear310_pmx_emi_cs_2_3,
+	&spear310_pmx_uart1,
+	&spear310_pmx_uart2,
+	&spear310_pmx_uart3_4_5,
+	&spear310_pmx_fsmc,
+	&spear310_pmx_rs485_0_1,
+	&spear310_pmx_tdm0,
 };
 
 static struct amba_device *amba_devs[] __initdata = {
@@ -59,13 +59,7 @@ static void __init spear310_evb_init(void)
 	unsigned int i;
 
 	/* call spear310 machine init function */
-	spear310_init();
-
-	/* padmux initialization */
-	pmx_driver.mode = NULL;
-	pmx_driver.devs = pmx_devs;
-	pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-	spear310_pmx_init();
+	spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
 
 	/* Add Platform Devices */
 	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 768aa8c..ad3679c 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -61,7 +61,7 @@ static struct pmx_dev_mode pmx_clcd_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_clcd = {
+struct pmx_dev spear320_pmx_clcd = {
 	.name = "clcd",
 	.modes = pmx_clcd_modes,
 	.mode_count = ARRAY_SIZE(pmx_clcd_modes),
@@ -75,7 +75,7 @@ static struct pmx_dev_mode pmx_emi_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_emi = {
+struct pmx_dev spear320_pmx_emi = {
 	.name = "emi",
 	.modes = pmx_emi_modes,
 	.mode_count = ARRAY_SIZE(pmx_emi_modes),
@@ -89,7 +89,7 @@ static struct pmx_dev_mode pmx_fsmc_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_fsmc = {
+struct pmx_dev spear320_pmx_fsmc = {
 	.name = "fsmc",
 	.modes = pmx_fsmc_modes,
 	.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
@@ -103,7 +103,7 @@ static struct pmx_dev_mode pmx_spp_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_spp = {
+struct pmx_dev spear320_pmx_spp = {
 	.name = "spp",
 	.modes = pmx_spp_modes,
 	.mode_count = ARRAY_SIZE(pmx_spp_modes),
@@ -118,7 +118,7 @@ static struct pmx_dev_mode pmx_sdio_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_sdio = {
+struct pmx_dev spear320_pmx_sdio = {
 	.name = "sdio",
 	.modes = pmx_sdio_modes,
 	.mode_count = ARRAY_SIZE(pmx_sdio_modes),
@@ -132,7 +132,7 @@ static struct pmx_dev_mode pmx_i2s_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_i2s = {
+struct pmx_dev spear320_pmx_i2s = {
 	.name = "i2s",
 	.modes = pmx_i2s_modes,
 	.mode_count = ARRAY_SIZE(pmx_i2s_modes),
@@ -146,7 +146,7 @@ static struct pmx_dev_mode pmx_uart1_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_uart1 = {
+struct pmx_dev spear320_pmx_uart1 = {
 	.name = "uart1",
 	.modes = pmx_uart1_modes,
 	.mode_count = ARRAY_SIZE(pmx_uart1_modes),
@@ -165,7 +165,7 @@ static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_uart1_modem = {
+struct pmx_dev spear320_pmx_uart1_modem = {
 	.name = "uart1_modem",
 	.modes = pmx_uart1_modem_modes,
 	.mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
@@ -179,7 +179,7 @@ static struct pmx_dev_mode pmx_uart2_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_uart2 = {
+struct pmx_dev spear320_pmx_uart2 = {
 	.name = "uart2",
 	.modes = pmx_uart2_modes,
 	.mode_count = ARRAY_SIZE(pmx_uart2_modes),
@@ -193,7 +193,7 @@ static struct pmx_dev_mode pmx_touchscreen_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_touchscreen = {
+struct pmx_dev spear320_pmx_touchscreen = {
 	.name = "touchscreen",
 	.modes = pmx_touchscreen_modes,
 	.mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
@@ -208,7 +208,7 @@ static struct pmx_dev_mode pmx_can_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_can = {
+struct pmx_dev spear320_pmx_can = {
 	.name = "can",
 	.modes = pmx_can_modes,
 	.mode_count = ARRAY_SIZE(pmx_can_modes),
@@ -222,7 +222,7 @@ static struct pmx_dev_mode pmx_sdio_led_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_sdio_led = {
+struct pmx_dev spear320_pmx_sdio_led = {
 	.name = "sdio_led",
 	.modes = pmx_sdio_led_modes,
 	.mode_count = ARRAY_SIZE(pmx_sdio_led_modes),
@@ -239,7 +239,7 @@ static struct pmx_dev_mode pmx_pwm0_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_pwm0 = {
+struct pmx_dev spear320_pmx_pwm0 = {
 	.name = "pwm0",
 	.modes = pmx_pwm0_modes,
 	.mode_count = ARRAY_SIZE(pmx_pwm0_modes),
@@ -256,7 +256,7 @@ static struct pmx_dev_mode pmx_pwm1_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_pwm1 = {
+struct pmx_dev spear320_pmx_pwm1 = {
 	.name = "pwm1",
 	.modes = pmx_pwm1_modes,
 	.mode_count = ARRAY_SIZE(pmx_pwm1_modes),
@@ -273,7 +273,7 @@ static struct pmx_dev_mode pmx_pwm2_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_pwm2 = {
+struct pmx_dev spear320_pmx_pwm2 = {
 	.name = "pwm2",
 	.modes = pmx_pwm2_modes,
 	.mode_count = ARRAY_SIZE(pmx_pwm2_modes),
@@ -287,7 +287,7 @@ static struct pmx_dev_mode pmx_pwm3_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_pwm3 = {
+struct pmx_dev spear320_pmx_pwm3 = {
 	.name = "pwm3",
 	.modes = pmx_pwm3_modes,
 	.mode_count = ARRAY_SIZE(pmx_pwm3_modes),
@@ -301,7 +301,7 @@ static struct pmx_dev_mode pmx_ssp1_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_ssp1 = {
+struct pmx_dev spear320_pmx_ssp1 = {
 	.name = "ssp1",
 	.modes = pmx_ssp1_modes,
 	.mode_count = ARRAY_SIZE(pmx_ssp1_modes),
@@ -315,7 +315,7 @@ static struct pmx_dev_mode pmx_ssp2_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_ssp2 = {
+struct pmx_dev spear320_pmx_ssp2 = {
 	.name = "ssp2",
 	.modes = pmx_ssp2_modes,
 	.mode_count = ARRAY_SIZE(pmx_ssp2_modes),
@@ -329,7 +329,7 @@ static struct pmx_dev_mode pmx_mii1_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_mii1 = {
+struct pmx_dev spear320_pmx_mii1 = {
 	.name = "mii1",
 	.modes = pmx_mii1_modes,
 	.mode_count = ARRAY_SIZE(pmx_mii1_modes),
@@ -343,7 +343,7 @@ static struct pmx_dev_mode pmx_smii0_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_smii0 = {
+struct pmx_dev spear320_pmx_smii0 = {
 	.name = "smii0",
 	.modes = pmx_smii0_modes,
 	.mode_count = ARRAY_SIZE(pmx_smii0_modes),
@@ -357,7 +357,7 @@ static struct pmx_dev_mode pmx_smii1_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_smii1 = {
+struct pmx_dev spear320_pmx_smii1 = {
 	.name = "smii1",
 	.modes = pmx_smii1_modes,
 	.mode_count = ARRAY_SIZE(pmx_smii1_modes),
@@ -371,7 +371,7 @@ static struct pmx_dev_mode pmx_i2c1_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_i2c1 = {
+struct pmx_dev spear320_pmx_i2c1 = {
 	.name = "i2c1",
 	.modes = pmx_i2c1_modes,
 	.mode_count = ARRAY_SIZE(pmx_i2c1_modes),
@@ -379,7 +379,7 @@ struct pmx_dev pmx_i2c1 = {
 };
 
 /* pmx driver structure */
-struct pmx_driver pmx_driver = {
+static struct pmx_driver pmx_driver = {
 	.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
 	.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 };
@@ -511,7 +511,8 @@ static struct spear_shirq shirq_intrcomm_ras = {
 };
 
 /* spear320 routines */
-void __init spear320_init(void)
+void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+			  u8 pmx_dev_count)
 {
 	void __iomem *base;
 	int ret = 0;
@@ -540,10 +541,10 @@ void __init spear320_init(void)
 		if (ret)
 			printk(KERN_ERR "Error registering Shared IRQ 4\n");
 	}
-}
 
-void spear320_pmx_init(void)
-{
+	pmx_driver.mode = pmx_mode;
+	pmx_driver.devs = pmx_devs;
+	pmx_driver.devs_count = pmx_dev_count;
 	spear_pmx_init(&pmx_driver, SPEAR320_SOC_CONFIG_BASE,
-			SPEAR320_SOC_CONFIG_SIZE);
+		       SPEAR320_SOC_CONFIG_SIZE);
 }
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 62ac685..4969fa9 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -19,22 +19,22 @@
 /* padmux devices to enable */
 static struct pmx_dev *pmx_devs[] = {
 	/* spear3xx specific devices */
-	&pmx_i2c,
-	&pmx_ssp,
-	&pmx_mii,
-	&pmx_uart0,
+	&spear3xx_pmx_i2c,
+	&spear3xx_pmx_ssp,
+	&spear3xx_pmx_mii,
+	&spear3xx_pmx_uart0,
 
 	/* spear320 specific devices */
-	&pmx_fsmc,
-	&pmx_sdio,
-	&pmx_i2s,
-	&pmx_uart1,
-	&pmx_uart2,
-	&pmx_can,
-	&pmx_pwm0,
-	&pmx_pwm1,
-	&pmx_pwm2,
-	&pmx_mii1,
+	&spear320_pmx_fsmc,
+	&spear320_pmx_sdio,
+	&spear320_pmx_i2s,
+	&spear320_pmx_uart1,
+	&spear320_pmx_uart2,
+	&spear320_pmx_can,
+	&spear320_pmx_pwm0,
+	&spear320_pmx_pwm1,
+	&spear320_pmx_pwm2,
+	&spear320_pmx_mii1,
 };
 
 static struct amba_device *amba_devs[] __initdata = {
@@ -56,13 +56,7 @@ static void __init spear320_evb_init(void)
 	unsigned int i;
 
 	/* call spear320 machine init function */
-	spear320_init();
-
-	/* padmux initialization */
-	pmx_driver.mode = &auto_net_mii_mode;
-	pmx_driver.devs = pmx_devs;
-	pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-	spear320_pmx_init();
+	spear320_init(&auto_net_mii_mode, pmx_devs, ARRAY_SIZE(pmx_devs));
 
 	/* Add Platform Devices */
 	platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 0efd8d7..545ac24 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -109,7 +109,7 @@ static struct pmx_dev_mode pmx_firda_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_firda = {
+struct pmx_dev spear3xx_pmx_firda = {
 	.name = "firda",
 	.modes = pmx_firda_modes,
 	.mode_count = ARRAY_SIZE(pmx_firda_modes),
@@ -123,7 +123,7 @@ static struct pmx_dev_mode pmx_i2c_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_i2c = {
+struct pmx_dev spear3xx_pmx_i2c = {
 	.name = "i2c",
 	.modes = pmx_i2c_modes,
 	.mode_count = ARRAY_SIZE(pmx_i2c_modes),
@@ -137,7 +137,7 @@ static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_ssp_cs = {
+struct pmx_dev spear3xx_pmx_ssp_cs = {
 	.name = "ssp_chip_selects",
 	.modes = pmx_ssp_cs_modes,
 	.mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
@@ -151,7 +151,7 @@ static struct pmx_dev_mode pmx_ssp_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_ssp = {
+struct pmx_dev spear3xx_pmx_ssp = {
 	.name = "ssp",
 	.modes = pmx_ssp_modes,
 	.mode_count = ARRAY_SIZE(pmx_ssp_modes),
@@ -165,7 +165,7 @@ static struct pmx_dev_mode pmx_mii_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_mii = {
+struct pmx_dev spear3xx_pmx_mii = {
 	.name = "mii",
 	.modes = pmx_mii_modes,
 	.mode_count = ARRAY_SIZE(pmx_mii_modes),
@@ -179,7 +179,7 @@ static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_gpio_pin0 = {
+struct pmx_dev spear3xx_pmx_gpio_pin0 = {
 	.name = "gpio_pin0",
 	.modes = pmx_gpio_pin0_modes,
 	.mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
@@ -193,7 +193,7 @@ static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_gpio_pin1 = {
+struct pmx_dev spear3xx_pmx_gpio_pin1 = {
 	.name = "gpio_pin1",
 	.modes = pmx_gpio_pin1_modes,
 	.mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
@@ -207,7 +207,7 @@ static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_gpio_pin2 = {
+struct pmx_dev spear3xx_pmx_gpio_pin2 = {
 	.name = "gpio_pin2",
 	.modes = pmx_gpio_pin2_modes,
 	.mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
@@ -221,7 +221,7 @@ static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_gpio_pin3 = {
+struct pmx_dev spear3xx_pmx_gpio_pin3 = {
 	.name = "gpio_pin3",
 	.modes = pmx_gpio_pin3_modes,
 	.mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
@@ -235,7 +235,7 @@ static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_gpio_pin4 = {
+struct pmx_dev spear3xx_pmx_gpio_pin4 = {
 	.name = "gpio_pin4",
 	.modes = pmx_gpio_pin4_modes,
 	.mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
@@ -249,7 +249,7 @@ static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_gpio_pin5 = {
+struct pmx_dev spear3xx_pmx_gpio_pin5 = {
 	.name = "gpio_pin5",
 	.modes = pmx_gpio_pin5_modes,
 	.mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
@@ -263,7 +263,7 @@ static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_uart0_modem = {
+struct pmx_dev spear3xx_pmx_uart0_modem = {
 	.name = "uart0_modem",
 	.modes = pmx_uart0_modem_modes,
 	.mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
@@ -277,7 +277,7 @@ static struct pmx_dev_mode pmx_uart0_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_uart0 = {
+struct pmx_dev spear3xx_pmx_uart0 = {
 	.name = "uart0",
 	.modes = pmx_uart0_modes,
 	.mode_count = ARRAY_SIZE(pmx_uart0_modes),
@@ -291,7 +291,7 @@ static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_timer_3_4 = {
+struct pmx_dev spear3xx_pmx_timer_3_4 = {
 	.name = "timer_3_4",
 	.modes = pmx_timer_3_4_modes,
 	.mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
@@ -305,7 +305,7 @@ static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_timer_1_2 = {
+struct pmx_dev spear3xx_pmx_timer_1_2 = {
 	.name = "timer_1_2",
 	.modes = pmx_timer_1_2_modes,
 	.mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
@@ -321,7 +321,7 @@ static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_0_1 = {
+struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
 	.name = "plgpio 0 and 1",
 	.modes = pmx_plgpio_0_1_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
@@ -335,7 +335,7 @@ static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_2_3 = {
+struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
 	.name = "plgpio 2 and 3",
 	.modes = pmx_plgpio_2_3_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
@@ -349,7 +349,7 @@ static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_4_5 = {
+struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
 	.name = "plgpio 4 and 5",
 	.modes = pmx_plgpio_4_5_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
@@ -363,7 +363,7 @@ static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_6_9 = {
+struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
 	.name = "plgpio 6 to 9",
 	.modes = pmx_plgpio_6_9_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
@@ -377,7 +377,7 @@ static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_10_27 = {
+struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
 	.name = "plgpio 10 to 27",
 	.modes = pmx_plgpio_10_27_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
@@ -391,7 +391,7 @@ static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_28 = {
+struct pmx_dev spear3xx_pmx_plgpio_28 = {
 	.name = "plgpio 28",
 	.modes = pmx_plgpio_28_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
@@ -405,7 +405,7 @@ static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_29 = {
+struct pmx_dev spear3xx_pmx_plgpio_29 = {
 	.name = "plgpio 29",
 	.modes = pmx_plgpio_29_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
@@ -419,7 +419,7 @@ static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_30 = {
+struct pmx_dev spear3xx_pmx_plgpio_30 = {
 	.name = "plgpio 30",
 	.modes = pmx_plgpio_30_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
@@ -433,7 +433,7 @@ static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_31 = {
+struct pmx_dev spear3xx_pmx_plgpio_31 = {
 	.name = "plgpio 31",
 	.modes = pmx_plgpio_31_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
@@ -447,7 +447,7 @@ static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_32 = {
+struct pmx_dev spear3xx_pmx_plgpio_32 = {
 	.name = "plgpio 32",
 	.modes = pmx_plgpio_32_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
@@ -461,7 +461,7 @@ static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_33 = {
+struct pmx_dev spear3xx_pmx_plgpio_33 = {
 	.name = "plgpio 33",
 	.modes = pmx_plgpio_33_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
@@ -475,7 +475,7 @@ static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_34_36 = {
+struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
 	.name = "plgpio 34 to 36",
 	.modes = pmx_plgpio_34_36_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
@@ -489,7 +489,7 @@ static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_37_42 = {
+struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
 	.name = "plgpio 37 to 42",
 	.modes = pmx_plgpio_37_42_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
@@ -503,7 +503,7 @@ static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_43_44_47_48 = {
+struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
 	.name = "plgpio 43, 44, 47 and 48",
 	.modes = pmx_plgpio_43_44_47_48_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
@@ -517,7 +517,7 @@ static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_plgpio_45_46_49_50 = {
+struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
 	.name = "plgpio 45, 46, 49 and 50",
 	.modes = pmx_plgpio_45_46_49_50_modes,
 	.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
-- 
1.5.5



From ryan at bluewatersys.com  Sat Jun  5 02:05:55 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Sat,  5 Jun 2010 18:05:55 +1200
Subject: [PATCH 5/5] SPEAr3xx: Replace defconfigs with single unfied defconfig
In-Reply-To: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1275717955-14545-6-git-send-email-ryan@bluewatersys.com>

We only need one defconfig for SPEAr3xx now since we can build all
three boards into one kernel.

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/configs/spear300_defconfig |  773 ----------------------------------
 arch/arm/configs/spear310_defconfig |  775 -----------------------------------
 arch/arm/configs/spear320_defconfig |  775 -----------------------------------
 arch/arm/configs/spear3xx_defconfig |  775 +++++++++++++++++++++++++++++++++++
 4 files changed, 775 insertions(+), 2323 deletions(-)
 delete mode 100644 arch/arm/configs/spear300_defconfig
 delete mode 100644 arch/arm/configs/spear310_defconfig
 delete mode 100644 arch/arm/configs/spear320_defconfig
 create mode 100644 arch/arm/configs/spear3xx_defconfig

diff --git a/arch/arm/configs/spear300_defconfig b/arch/arm/configs/spear300_defconfig
deleted file mode 100644
index 35e64d1..0000000
--- a/arch/arm/configs/spear300_defconfig
+++ /dev/null
@@ -1,773 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32
-# Tue Mar 23 14:36:23 2010
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-# CONFIG_EMBEDDED is not set
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_COMPAT_BRK=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-# CONFIG_SLOW_WORK is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-CONFIG_LBDAF=y
-CONFIG_BLK_DEV_BSG=y
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_FREEZER is not set
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-CONFIG_PLAT_SPEAR=y
-CONFIG_ARCH_SPEAR3XX=y
-# CONFIG_ARCH_SPEAR6XX is not set
-CONFIG_MACH_SPEAR300=y
-# CONFIG_MACH_SPEAR310 is not set
-# CONFIG_MACH_SPEAR320 is not set
-CONFIG_BOARD_SPEAR300_EVB=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_32=y
-CONFIG_CPU_ARM926T=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_VIC=y
-CONFIG_ARM_VIC_NR=2
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-CONFIG_ARM_AMBA=y
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-# CONFIG_AEABI is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-# CONFIG_FPE_NWFPE is not set
-# CONFIG_FPE_FASTFPE is not set
-# CONFIG_VFP is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_MISC=y
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_NET is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_DEVTMPFS is not set
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_MTD is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_93CX6 is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_FF_MEMLESS=y
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_AMBAKMI is not set
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_AMBA_PL010 is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=8192
-# CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
-# CONFIG_SPI is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-
-#
-# Memory mapped GPIO expanders:
-#
-CONFIG_GPIO_PL061=y
-
-#
-# I2C GPIO expanders:
-#
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_REGULATOR is not set
-# CONFIG_MEDIA_SUPPORT is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_SOUND is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_MMC is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_EXT2_FS_POSIX_ACL is not set
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-# CONFIG_INOTIFY is not set
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-CONFIG_AUTOFS4_FS=m
-# CONFIG_FUSE_FS is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-CONFIG_NLS_ASCII=m
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-CONFIG_DEBUG_SPINLOCK=y
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_CPU_STALL_DETECTOR=y
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_ENABLE_DEFAULT_TRACERS is not set
-# CONFIG_BOOT_TRACER is not set
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_ERRORS is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-# CONFIG_CRC32 is not set
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/spear310_defconfig b/arch/arm/configs/spear310_defconfig
deleted file mode 100644
index cbbfd29..0000000
--- a/arch/arm/configs/spear310_defconfig
+++ /dev/null
@@ -1,775 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32
-# Tue Mar 23 14:37:01 2010
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-# CONFIG_EMBEDDED is not set
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_COMPAT_BRK=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-# CONFIG_SLOW_WORK is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-CONFIG_LBDAF=y
-CONFIG_BLK_DEV_BSG=y
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_FREEZER is not set
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-CONFIG_PLAT_SPEAR=y
-CONFIG_ARCH_SPEAR3XX=y
-# CONFIG_ARCH_SPEAR6XX is not set
-# CONFIG_MACH_SPEAR300 is not set
-CONFIG_MACH_SPEAR310=y
-# CONFIG_MACH_SPEAR320 is not set
-# CONFIG_BOARD_SPEAR300_EVB is not set
-CONFIG_BOARD_SPEAR310_EVB=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_32=y
-CONFIG_CPU_ARM926T=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_VIC=y
-CONFIG_ARM_VIC_NR=2
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-CONFIG_ARM_AMBA=y
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-# CONFIG_AEABI is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-# CONFIG_FPE_NWFPE is not set
-# CONFIG_FPE_FASTFPE is not set
-# CONFIG_VFP is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_MISC=y
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_NET is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_DEVTMPFS is not set
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_MTD is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_MG_DISK is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_93CX6 is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_FF_MEMLESS=y
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_AMBAKMI is not set
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_AMBA_PL010 is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=8192
-# CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
-# CONFIG_SPI is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-
-#
-# Memory mapped GPIO expanders:
-#
-CONFIG_GPIO_PL061=y
-
-#
-# I2C GPIO expanders:
-#
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_REGULATOR is not set
-# CONFIG_MEDIA_SUPPORT is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_SOUND is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_MMC is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_EXT2_FS_POSIX_ACL is not set
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-# CONFIG_INOTIFY is not set
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-CONFIG_AUTOFS4_FS=m
-# CONFIG_FUSE_FS is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-CONFIG_NLS_ASCII=m
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-CONFIG_DEBUG_SPINLOCK=y
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_CPU_STALL_DETECTOR=y
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_ENABLE_DEFAULT_TRACERS is not set
-# CONFIG_BOOT_TRACER is not set
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_ERRORS is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-# CONFIG_CRC32 is not set
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/spear320_defconfig b/arch/arm/configs/spear320_defconfig
deleted file mode 100644
index 2ae3c11..0000000
--- a/arch/arm/configs/spear320_defconfig
+++ /dev/null
@@ -1,775 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32
-# Tue Mar 23 14:37:12 2010
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-# CONFIG_EMBEDDED is not set
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_COMPAT_BRK=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-# CONFIG_SLOW_WORK is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-CONFIG_LBDAF=y
-CONFIG_BLK_DEV_BSG=y
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_FREEZER is not set
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-CONFIG_PLAT_SPEAR=y
-CONFIG_ARCH_SPEAR3XX=y
-# CONFIG_ARCH_SPEAR6XX is not set
-# CONFIG_MACH_SPEAR300 is not set
-# CONFIG_MACH_SPEAR310 is not set
-CONFIG_MACH_SPEAR320=y
-# CONFIG_BOARD_SPEAR300_EVB is not set
-CONFIG_BOARD_SPEAR320_EVB=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_32=y
-CONFIG_CPU_ARM926T=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5TJ=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_COPY_V4WB=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
-# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_ARM_VIC=y
-CONFIG_ARM_VIC_NR=2
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-CONFIG_ARM_AMBA=y
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-# CONFIG_AEABI is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-# CONFIG_FPE_NWFPE is not set
-# CONFIG_FPE_FASTFPE is not set
-# CONFIG_VFP is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_MISC=y
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_NET is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_DEVTMPFS is not set
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_MTD is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=16384
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_MG_DISK is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_93CX6 is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_FF_MEMLESS=y
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_AMBAKMI is not set
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_AMBA_PL010 is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=8192
-# CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
-# CONFIG_SPI is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-
-#
-# Memory mapped GPIO expanders:
-#
-CONFIG_GPIO_PL061=y
-
-#
-# I2C GPIO expanders:
-#
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_REGULATOR is not set
-# CONFIG_MEDIA_SUPPORT is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_SOUND is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_MMC is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-# CONFIG_EXT2_FS_POSIX_ACL is not set
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-# CONFIG_INOTIFY is not set
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-CONFIG_AUTOFS4_FS=m
-# CONFIG_FUSE_FS is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-CONFIG_NLS_ASCII=m
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-CONFIG_DEBUG_SPINLOCK=y
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_RCU_CPU_STALL_DETECTOR=y
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_ENABLE_DEFAULT_TRACERS is not set
-# CONFIG_BOOT_TRACER is not set
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_ERRORS is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-# CONFIG_CRC32 is not set
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
new file mode 100644
index 0000000..f51b053
--- /dev/null
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -0,0 +1,775 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.32
+# Tue Mar 23 14:36:23 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5PC1XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_ARCH_BCMRING is not set
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR3XX=y
+# CONFIG_ARCH_SPEAR6XX is not set
+CONFIG_MACH_SPEAR300=y
+CONFIG_MACH_SPEAR310=y
+CONFIG_MACH_SPEAR320=y
+CONFIG_BOARD_SPEAR300_EVB=y
+CONFIG_BOARD_SPEAR310_EVB=y
+CONFIG_BOARD_SPEAR320_EVB=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_ARM_VIC=y
+CONFIG_ARM_VIC_NR=2
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_AMBAKMI is not set
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+CONFIG_GPIO_PL061=y
+
+#
+# I2C GPIO expanders:
+#
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+
+#
+# TI VLYNQ
+#
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=m
+# CONFIG_NLS_ISO8859_1 is not set
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_DETECTOR=y
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+# CONFIG_CRC32 is not set
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
-- 
1.5.5



From mcuos.com at gmail.com  Sat Jun  5 02:40:30 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Sat, 05 Jun 2010 14:40:30 +0800
Subject: [PATCH 1/3] MTD/pxa: patch for error return value method of
	pxa2xx-flash.c
Message-ID: <4C09F15E.9020408@gmail.com>

This patch is to re-implement the 'pxa2xx-flash.c' error return value method
of probe() and remove() function,the old return way can arouse the 'info' memory
leak risk.

Signed-off-by :Wan ZongShun <mcuos.com at gmail.com>

---
 drivers/mtd/maps/pxa2xx-flash.c |   47 ++++++++++++++++++++++++++++----------
 1 files changed, 34 insertions(+), 13 deletions(-)

diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
index dd90880..1d2583f 100644
--- a/drivers/mtd/maps/pxa2xx-flash.c
+++ b/drivers/mtd/maps/pxa2xx-flash.c
@@ -60,12 +60,21 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
 	int ret = 0;

 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (!res)
-		return -ENODEV;
+	if (!res) {
+		ret = -ENODEV;
+		goto fail0;
+	}
+
+	if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
+		ret = -EBUSY;
+		goto fail0;
+	}

 	info = kzalloc(sizeof(struct pxa2xx_flash_info), GFP_KERNEL);
-	if (!info)
-		return -ENOMEM;
+	if (!info) {
+		ret = -ENOMEM;
+		goto fail1;
+	}

 	info->map.name = (char *) flash->name;
 	info->map.bankwidth = flash->width;
@@ -78,13 +87,17 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
 	if (!info->map.virt) {
 		printk(KERN_WARNING "Failed to ioremap %s\n",
 		       info->map.name);
-		return -ENOMEM;
+		ret = -ENOMEM;
+		goto fail2;
 	}
 	info->map.cached =
 		ioremap_cached(info->map.phys, info->map.size);
-	if (!info->map.cached)
+	if (!info->map.cached) {
 		printk(KERN_WARNING "Failed to ioremap cached %s\n",
 		       info->map.name);
+		ret = -ENOMEM;
+		goto fail3;
+	}
 	info->map.inval_cache = pxa2xx_map_inval_cache;
 	simple_map_init(&info->map);

@@ -97,10 +110,8 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
 	info->mtd = do_map_probe(flash->map_name, &info->map);

 	if (!info->mtd) {
-		iounmap((void *)info->map.virt);
-		if (info->map.cached)
-			iounmap(info->map.cached);
-		return -EIO;
+		ret = -EIO;
+		goto fail4;
 	}
 	info->mtd->owner = THIS_MODULE;

@@ -124,13 +135,21 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)

 	platform_set_drvdata(pdev, info);
 	return 0;
+
+fail4:	iounmap(info->map.cached);
+fail3:	iounmap(info->map.virt);
+fail2:	kfree(info);
+fail1:	release_mem_region(res->start, resource_size(res));
+fail0:
+	return ret;
 }

 static int __devexit pxa2xx_flash_remove(struct platform_device *dev)
 {
 	struct pxa2xx_flash_info *info = platform_get_drvdata(dev);
+	struct resource *res;

-	platform_set_drvdata(dev, NULL);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

 #ifdef CONFIG_MTD_PARTITIONS
 	if (info->nr_parts)
@@ -141,10 +160,12 @@ static int __devexit pxa2xx_flash_remove(struct platform_device *dev)

 	map_destroy(info->mtd);
 	iounmap(info->map.virt);
-	if (info->map.cached)
-		iounmap(info->map.cached);
+	iounmap(info->map.cached);
 	kfree(info->parts);
 	kfree(info);
+	release_mem_region(res->start, resource_size(res));
+	platform_set_drvdata(dev, NULL);
+
 	return 0;
 }

-- 
1.6.3.3


From mcuos.com at gmail.com  Sat Jun  5 02:44:46 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Sat, 05 Jun 2010 14:44:46 +0800
Subject: [PATCH 2/3] MTD/pxa: use __devinit for pxa2xx_flash_probe
Message-ID: <4C09F25E.8090908@gmail.com>

This patch is to use the '__devinit' for pxa2xx_flash_probe.


Signed-off-by :Wan ZongShun <mcuos.com at gmail.com>
---
 drivers/mtd/maps/pxa2xx-flash.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
index 1d2583f..43f8bb8 100644
--- a/drivers/mtd/maps/pxa2xx-flash.c
+++ b/drivers/mtd/maps/pxa2xx-flash.c
@@ -51,7 +51,7 @@ struct pxa2xx_flash_info {
 static const char *probes[] = { "RedBoot", "cmdlinepart", NULL };


-static int __init pxa2xx_flash_probe(struct platform_device *pdev)
+static int __devinit pxa2xx_flash_probe(struct platform_device *pdev)
 {
 	struct flash_platform_data *flash = pdev->dev.platform_data;
 	struct pxa2xx_flash_info *info;
-- 
1.6.3.3


From mcuos.com at gmail.com  Sat Jun  5 02:48:57 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Sat, 05 Jun 2010 14:48:57 +0800
Subject: [PATCH 3/3] MTD/pxa: use resource_size(res) for pxa2xx-flash
Message-ID: <4C09F359.1000100@gmail.com>

The size calculation is end - start + 1. But,sometimes, the '1' can
be forgotten carelessly, witch will have potential risk, so use resource_size
should be good habit.

Signed-off-by :Wan ZongShun <mcuos.com at gmail.com>

---
 drivers/mtd/maps/pxa2xx-flash.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
index 43f8bb8..6ed9a2d 100644
--- a/drivers/mtd/maps/pxa2xx-flash.c
+++ b/drivers/mtd/maps/pxa2xx-flash.c
@@ -79,7 +79,7 @@ static int __devinit pxa2xx_flash_probe(struct platform_device *pdev)
 	info->map.name = (char *) flash->name;
 	info->map.bankwidth = flash->width;
 	info->map.phys = res->start;
-	info->map.size = res->end - res->start + 1;
+	info->map.size = resource_size(res);
 	info->parts = flash->parts;
 	info->nr_parts = flash->nr_parts;

-- 
1.6.3.3


From eric.y.miao at gmail.com  Sat Jun  5 03:14:21 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 5 Jun 2010 15:14:21 +0800
Subject: [PATCH 1/3] MTD/pxa: patch for error return value method of 
	pxa2xx-flash.c
In-Reply-To: <4C09F15E.9020408@gmail.com>
References: <4C09F15E.9020408@gmail.com>
Message-ID: <AANLkTinLfGD-x-861sFK9r2zW5aEZvyXIB4PFKJl8NDZ@mail.gmail.com>

2010/6/5 Wan ZongShun <mcuos.com at gmail.com>:
> This patch is to re-implement the 'pxa2xx-flash.c' error return value method
> of probe() and remove() function,the old return way can arouse the 'info' memory
> leak risk.
>
> Signed-off-by :Wan ZongShun <mcuos.com at gmail.com>
>
> ---
> ?drivers/mtd/maps/pxa2xx-flash.c | ? 47 ++++++++++++++++++++++++++++----------
> ?1 files changed, 34 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
> index dd90880..1d2583f 100644
> --- a/drivers/mtd/maps/pxa2xx-flash.c
> +++ b/drivers/mtd/maps/pxa2xx-flash.c
> @@ -60,12 +60,21 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
> ? ? ? ?int ret = 0;
>
> ? ? ? ?res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - ? ? ? if (!res)
> - ? ? ? ? ? ? ? return -ENODEV;
> + ? ? ? if (!res) {
> + ? ? ? ? ? ? ? ret = -ENODEV;
> + ? ? ? ? ? ? ? goto fail0;
> + ? ? ? }

Can just return -ENODEV, why bother goto here?

> +
> + ? ? ? if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
> + ? ? ? ? ? ? ? ret = -EBUSY;
> + ? ? ? ? ? ? ? goto fail0;
> + ? ? ? }
>

Same here, nothing to release, can just return -EBUSY here. Provided I
always doubt the necessity of request_mem_region() here since the resource
should have been claimed when the platform device is registered, this is
possibly going to claim a sub-region of that resource. But that's another
story.

> ? ? ? ?info = kzalloc(sizeof(struct pxa2xx_flash_info), GFP_KERNEL);
> - ? ? ? if (!info)
> - ? ? ? ? ? ? ? return -ENOMEM;
> + ? ? ? if (!info) {
> + ? ? ? ? ? ? ? ret = -ENOMEM;
> + ? ? ? ? ? ? ? goto fail1;
> + ? ? ? }
>
> ? ? ? ?info->map.name = (char *) flash->name;
> ? ? ? ?info->map.bankwidth = flash->width;
> @@ -78,13 +87,17 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
> ? ? ? ?if (!info->map.virt) {
> ? ? ? ? ? ? ? ?printk(KERN_WARNING "Failed to ioremap %s\n",
> ? ? ? ? ? ? ? ? ? ? ? info->map.name);
> - ? ? ? ? ? ? ? return -ENOMEM;
> + ? ? ? ? ? ? ? ret = -ENOMEM;
> + ? ? ? ? ? ? ? goto fail2;
> ? ? ? ?}
> ? ? ? ?info->map.cached =
> ? ? ? ? ? ? ? ?ioremap_cached(info->map.phys, info->map.size);
> - ? ? ? if (!info->map.cached)
> + ? ? ? if (!info->map.cached) {
> ? ? ? ? ? ? ? ?printk(KERN_WARNING "Failed to ioremap cached %s\n",
> ? ? ? ? ? ? ? ? ? ? ? info->map.name);


This might not be an error at all, it's a warning. The cached mapping is
for performance reason on some platforms, it should be working all right
without it.

> + ? ? ? ? ? ? ? ret = -ENOMEM;
> + ? ? ? ? ? ? ? goto fail3;
> + ? ? ? }
> ? ? ? ?info->map.inval_cache = pxa2xx_map_inval_cache;
> ? ? ? ?simple_map_init(&info->map);
>
> @@ -97,10 +110,8 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
> ? ? ? ?info->mtd = do_map_probe(flash->map_name, &info->map);
>
> ? ? ? ?if (!info->mtd) {
> - ? ? ? ? ? ? ? iounmap((void *)info->map.virt);
> - ? ? ? ? ? ? ? if (info->map.cached)
> - ? ? ? ? ? ? ? ? ? ? ? iounmap(info->map.cached);
> - ? ? ? ? ? ? ? return -EIO;
> + ? ? ? ? ? ? ? ret = -EIO;

See above.

> + ? ? ? ? ? ? ? goto fail4;
> ? ? ? ?}
> ? ? ? ?info->mtd->owner = THIS_MODULE;
>
> @@ -124,13 +135,21 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>
> ? ? ? ?platform_set_drvdata(pdev, info);
> ? ? ? ?return 0;
> +
> +fail4: iounmap(info->map.cached);
> +fail3: iounmap(info->map.virt);
> +fail2: kfree(info);
> +fail1: release_mem_region(res->start, resource_size(res));
> +fail0:
> + ? ? ? return ret;
> ?}
>
> ?static int __devexit pxa2xx_flash_remove(struct platform_device *dev)
> ?{
> ? ? ? ?struct pxa2xx_flash_info *info = platform_get_drvdata(dev);
> + ? ? ? struct resource *res;
>
> - ? ? ? platform_set_drvdata(dev, NULL);

What's wrong with the above statement? And normally there is some benefit
of setting drive data to be NULL, as the driver data could be used concurrently
during removal (i.e. an interrupt handler if the IRQ is not already disabled).
Though relying on this behavior to safely remove a device is _not_ by anyway
recommended.

> + ? ? ? res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>
> ?#ifdef CONFIG_MTD_PARTITIONS
> ? ? ? ?if (info->nr_parts)
> @@ -141,10 +160,12 @@ static int __devexit pxa2xx_flash_remove(struct platform_device *dev)
>
> ? ? ? ?map_destroy(info->mtd);
> ? ? ? ?iounmap(info->map.virt);
> - ? ? ? if (info->map.cached)
> - ? ? ? ? ? ? ? iounmap(info->map.cached);
> + ? ? ? iounmap(info->map.cached);

See above, the map.cached is supposed to be optional and can only
be removed if it's mapped, no force here.

> ? ? ? ?kfree(info->parts);
> ? ? ? ?kfree(info);
> + ? ? ? release_mem_region(res->start, resource_size(res));
> + ? ? ? platform_set_drvdata(dev, NULL);
> +
> ? ? ? ?return 0;
> ?}
>
> --
> 1.6.3.3
>


From eric.y.miao at gmail.com  Sat Jun  5 03:14:55 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 5 Jun 2010 15:14:55 +0800
Subject: [PATCH 2/3] MTD/pxa: use __devinit for pxa2xx_flash_probe
In-Reply-To: <4C09F25E.8090908@gmail.com>
References: <4C09F25E.8090908@gmail.com>
Message-ID: <AANLkTillJtAYn653DamU7_u3fmKt7rKGJtwfCHPPUVUF@mail.gmail.com>

2010/6/5 Wan ZongShun <mcuos.com at gmail.com>:
> This patch is to use the '__devinit' for pxa2xx_flash_probe.
>
>
> Signed-off-by :Wan ZongShun <mcuos.com at gmail.com>

Acked.

> ---
> ?drivers/mtd/maps/pxa2xx-flash.c | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
> index 1d2583f..43f8bb8 100644
> --- a/drivers/mtd/maps/pxa2xx-flash.c
> +++ b/drivers/mtd/maps/pxa2xx-flash.c
> @@ -51,7 +51,7 @@ struct pxa2xx_flash_info {
> ?static const char *probes[] = { "RedBoot", "cmdlinepart", NULL };
>
>
> -static int __init pxa2xx_flash_probe(struct platform_device *pdev)
> +static int __devinit pxa2xx_flash_probe(struct platform_device *pdev)
> ?{
> ? ? ? ?struct flash_platform_data *flash = pdev->dev.platform_data;
> ? ? ? ?struct pxa2xx_flash_info *info;
> --
> 1.6.3.3
>


From eric.y.miao at gmail.com  Sat Jun  5 03:15:12 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 5 Jun 2010 15:15:12 +0800
Subject: [PATCH 3/3] MTD/pxa: use resource_size(res) for pxa2xx-flash
In-Reply-To: <4C09F359.1000100@gmail.com>
References: <4C09F359.1000100@gmail.com>
Message-ID: <AANLkTilaptn-GhkoNC-CWLNP4XsTY7v-QCAypsF_BeKo@mail.gmail.com>

2010/6/5 Wan ZongShun <mcuos.com at gmail.com>:
> The size calculation is end - start + 1. But,sometimes, the '1' can
> be forgotten carelessly, witch will have potential risk, so use resource_size
> should be good habit.
>
> Signed-off-by :Wan ZongShun <mcuos.com at gmail.com>

Acked.

>
> ---
> ?drivers/mtd/maps/pxa2xx-flash.c | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
> index 43f8bb8..6ed9a2d 100644
> --- a/drivers/mtd/maps/pxa2xx-flash.c
> +++ b/drivers/mtd/maps/pxa2xx-flash.c
> @@ -79,7 +79,7 @@ static int __devinit pxa2xx_flash_probe(struct platform_device *pdev)
> ? ? ? ?info->map.name = (char *) flash->name;
> ? ? ? ?info->map.bankwidth = flash->width;
> ? ? ? ?info->map.phys = res->start;
> - ? ? ? info->map.size = res->end - res->start + 1;
> + ? ? ? info->map.size = resource_size(res);
> ? ? ? ?info->parts = flash->parts;
> ? ? ? ?info->nr_parts = flash->nr_parts;
>
> --
> 1.6.3.3
>


From mcuos.com at gmail.com  Sat Jun  5 03:38:10 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Sat, 5 Jun 2010 15:38:10 +0800
Subject: [PATCH 1/3] MTD/pxa: patch for error return value method of 
	pxa2xx-flash.c
In-Reply-To: <AANLkTinLfGD-x-861sFK9r2zW5aEZvyXIB4PFKJl8NDZ@mail.gmail.com>
References: <4C09F15E.9020408@gmail.com>
	<AANLkTinLfGD-x-861sFK9r2zW5aEZvyXIB4PFKJl8NDZ@mail.gmail.com>
Message-ID: <AANLkTikJiPjl3LKVqgqtlK2YEePXDf7K6EdOlUE4uzBb@mail.gmail.com>

Hi Eric,

Thanks for your review.

2010/6/5 Eric Miao <eric.y.miao at gmail.com>:
> 2010/6/5 Wan ZongShun <mcuos.com at gmail.com>:
>> This patch is to re-implement the 'pxa2xx-flash.c' error return value method
>> of probe() and remove() function,the old return way can arouse the 'info' memory
>> leak risk.
>>
>> Signed-off-by :Wan ZongShun <mcuos.com at gmail.com>
>>
>> ---
>> ?drivers/mtd/maps/pxa2xx-flash.c | ? 47 ++++++++++++++++++++++++++++----------
>> ?1 files changed, 34 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
>> index dd90880..1d2583f 100644
>> --- a/drivers/mtd/maps/pxa2xx-flash.c
>> +++ b/drivers/mtd/maps/pxa2xx-flash.c
>> @@ -60,12 +60,21 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>> ? ? ? ?int ret = 0;
>>
>> ? ? ? ?res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> - ? ? ? if (!res)
>> - ? ? ? ? ? ? ? return -ENODEV;
>> + ? ? ? if (!res) {
>> + ? ? ? ? ? ? ? ret = -ENODEV;
>> + ? ? ? ? ? ? ? goto fail0;
>> + ? ? ? }
>
> Can just return -ENODEV, why bother goto here?
>
>> +
>> + ? ? ? if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
>> + ? ? ? ? ? ? ? ret = -EBUSY;
>> + ? ? ? ? ? ? ? goto fail0;
>> + ? ? ? }
>>
>
> Same here, nothing to release, can just return -EBUSY here. Provided I
> always doubt the necessity of request_mem_region() here since the resource
> should have been claimed when the platform device is registered, this is
> possibly going to claim a sub-region of that resource. But that's another
> story.

I agree with you.
So, keep it be there or remove it?

Could Keeping it make a more compatibility code?


>
>> ? ? ? ?info = kzalloc(sizeof(struct pxa2xx_flash_info), GFP_KERNEL);
>> - ? ? ? if (!info)
>> - ? ? ? ? ? ? ? return -ENOMEM;
>> + ? ? ? if (!info) {
>> + ? ? ? ? ? ? ? ret = -ENOMEM;
>> + ? ? ? ? ? ? ? goto fail1;
>> + ? ? ? }
>>
>> ? ? ? ?info->map.name = (char *) flash->name;
>> ? ? ? ?info->map.bankwidth = flash->width;
>> @@ -78,13 +87,17 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>> ? ? ? ?if (!info->map.virt) {
>> ? ? ? ? ? ? ? ?printk(KERN_WARNING "Failed to ioremap %s\n",
>> ? ? ? ? ? ? ? ? ? ? ? info->map.name);
>> - ? ? ? ? ? ? ? return -ENOMEM;
>> + ? ? ? ? ? ? ? ret = -ENOMEM;
>> + ? ? ? ? ? ? ? goto fail2;
>> ? ? ? ?}
>> ? ? ? ?info->map.cached =
>> ? ? ? ? ? ? ? ?ioremap_cached(info->map.phys, info->map.size);
>> - ? ? ? if (!info->map.cached)
>> + ? ? ? if (!info->map.cached) {
>> ? ? ? ? ? ? ? ?printk(KERN_WARNING "Failed to ioremap cached %s\n",
>> ? ? ? ? ? ? ? ? ? ? ? info->map.name);
>
>
> This might not be an error at all, it's a warning. The cached mapping is
> for performance reason on some platforms, it should be working all right
> without it.

Thanks, I just have a doubt regarding this condition judement, so
thanks for your comments.

>
>> + ? ? ? ? ? ? ? ret = -ENOMEM;
>> + ? ? ? ? ? ? ? goto fail3;
>> + ? ? ? }
>> ? ? ? ?info->map.inval_cache = pxa2xx_map_inval_cache;
>> ? ? ? ?simple_map_init(&info->map);
>>
>> @@ -97,10 +110,8 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>> ? ? ? ?info->mtd = do_map_probe(flash->map_name, &info->map);
>>
>> ? ? ? ?if (!info->mtd) {
>> - ? ? ? ? ? ? ? iounmap((void *)info->map.virt);
>> - ? ? ? ? ? ? ? if (info->map.cached)
>> - ? ? ? ? ? ? ? ? ? ? ? iounmap(info->map.cached);
>> - ? ? ? ? ? ? ? return -EIO;
>> + ? ? ? ? ? ? ? ret = -EIO;
>
> See above.
>
>> + ? ? ? ? ? ? ? goto fail4;
>> ? ? ? ?}
>> ? ? ? ?info->mtd->owner = THIS_MODULE;
>>
>> @@ -124,13 +135,21 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>>
>> ? ? ? ?platform_set_drvdata(pdev, info);
>> ? ? ? ?return 0;
>> +
>> +fail4: iounmap(info->map.cached);
>> +fail3: iounmap(info->map.virt);
>> +fail2: kfree(info);
>> +fail1: release_mem_region(res->start, resource_size(res));
>> +fail0:
>> + ? ? ? return ret;
>> ?}
>>
>> ?static int __devexit pxa2xx_flash_remove(struct platform_device *dev)
>> ?{
>> ? ? ? ?struct pxa2xx_flash_info *info = platform_get_drvdata(dev);
>> + ? ? ? struct resource *res;
>>
>> - ? ? ? platform_set_drvdata(dev, NULL);
>
> What's wrong with the above statement? And normally there is some benefit
> of setting drive data to be NULL, as the driver data could be used concurrently
> during removal (i.e. an interrupt handler if the IRQ is not already disabled).
> Though relying on this behavior to safely remove a device is _not_ by anyway
> recommended.

I got it,so, setting the drive data to be NULL should be as early as possible.

>
>> + ? ? ? res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>
>> ?#ifdef CONFIG_MTD_PARTITIONS
>> ? ? ? ?if (info->nr_parts)
>> @@ -141,10 +160,12 @@ static int __devexit pxa2xx_flash_remove(struct platform_device *dev)
>>
>> ? ? ? ?map_destroy(info->mtd);
>> ? ? ? ?iounmap(info->map.virt);
>> - ? ? ? if (info->map.cached)
>> - ? ? ? ? ? ? ? iounmap(info->map.cached);
>> + ? ? ? iounmap(info->map.cached);
>
> See above, the map.cached is supposed to be optional and can only
> be removed if it's mapped, no force here.
>
>> ? ? ? ?kfree(info->parts);
>> ? ? ? ?kfree(info);
>> + ? ? ? release_mem_region(res->start, resource_size(res));
>> + ? ? ? platform_set_drvdata(dev, NULL);
>> +
>> ? ? ? ?return 0;
>> ?}
>>
>> --
>> 1.6.3.3
>>
>



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From mcuos.com at gmail.com  Sat Jun  5 03:53:25 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Sat, 5 Jun 2010 15:53:25 +0800
Subject: [PATCH 1/3] MTD/pxa: patch for error return value method of 
	pxa2xx-flash.c
In-Reply-To: <AANLkTikJiPjl3LKVqgqtlK2YEePXDf7K6EdOlUE4uzBb@mail.gmail.com>
References: <4C09F15E.9020408@gmail.com>
	<AANLkTinLfGD-x-861sFK9r2zW5aEZvyXIB4PFKJl8NDZ@mail.gmail.com>
	<AANLkTikJiPjl3LKVqgqtlK2YEePXDf7K6EdOlUE4uzBb@mail.gmail.com>
Message-ID: <AANLkTilydl5oKETCC69C_QY6xJa3mIXve097JU6qevfp@mail.gmail.com>

Hi Eric,

This following piece of code:

	if (!info->map.virt) {
		printk(KERN_WARNING "Failed to ioremap %s\n",
		       info->map.name);
		ret = -ENOMEM;
		goto fail2;
	}

Shouldn't  the 'KERN_ERR' in stead of the 'KERN_WARNING '?
Because the  'info->map.virt == NULL' can arouse the serious crash.

2010/6/5 Wan ZongShun <mcuos.com at gmail.com>:
> Hi Eric,
>
> Thanks for your review.
>
> 2010/6/5 Eric Miao <eric.y.miao at gmail.com>:
>> 2010/6/5 Wan ZongShun <mcuos.com at gmail.com>:
>>> This patch is to re-implement the 'pxa2xx-flash.c' error return value method
>>> of probe() and remove() function,the old return way can arouse the 'info' memory
>>> leak risk.
>>>
>>> Signed-off-by :Wan ZongShun <mcuos.com at gmail.com>
>>>
>>> ---
>>> ?drivers/mtd/maps/pxa2xx-flash.c | ? 47 ++++++++++++++++++++++++++++----------
>>> ?1 files changed, 34 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
>>> index dd90880..1d2583f 100644
>>> --- a/drivers/mtd/maps/pxa2xx-flash.c
>>> +++ b/drivers/mtd/maps/pxa2xx-flash.c
>>> @@ -60,12 +60,21 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>>> ? ? ? ?int ret = 0;
>>>
>>> ? ? ? ?res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> - ? ? ? if (!res)
>>> - ? ? ? ? ? ? ? return -ENODEV;
>>> + ? ? ? if (!res) {
>>> + ? ? ? ? ? ? ? ret = -ENODEV;
>>> + ? ? ? ? ? ? ? goto fail0;
>>> + ? ? ? }
>>
>> Can just return -ENODEV, why bother goto here?
>>
>>> +
>>> + ? ? ? if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
>>> + ? ? ? ? ? ? ? ret = -EBUSY;
>>> + ? ? ? ? ? ? ? goto fail0;
>>> + ? ? ? }
>>>
>>
>> Same here, nothing to release, can just return -EBUSY here. Provided I
>> always doubt the necessity of request_mem_region() here since the resource
>> should have been claimed when the platform device is registered, this is
>> possibly going to claim a sub-region of that resource. But that's another
>> story.
>
> I agree with you.
> So, keep it be there or remove it?
>
> Could Keeping it make a more compatibility code?
>
>
>>
>>> ? ? ? ?info = kzalloc(sizeof(struct pxa2xx_flash_info), GFP_KERNEL);
>>> - ? ? ? if (!info)
>>> - ? ? ? ? ? ? ? return -ENOMEM;
>>> + ? ? ? if (!info) {
>>> + ? ? ? ? ? ? ? ret = -ENOMEM;
>>> + ? ? ? ? ? ? ? goto fail1;
>>> + ? ? ? }
>>>
>>> ? ? ? ?info->map.name = (char *) flash->name;
>>> ? ? ? ?info->map.bankwidth = flash->width;
>>> @@ -78,13 +87,17 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>>> ? ? ? ?if (!info->map.virt) {
>>> ? ? ? ? ? ? ? ?printk(KERN_WARNING "Failed to ioremap %s\n",
>>> ? ? ? ? ? ? ? ? ? ? ? info->map.name);
>>> - ? ? ? ? ? ? ? return -ENOMEM;
>>> + ? ? ? ? ? ? ? ret = -ENOMEM;
>>> + ? ? ? ? ? ? ? goto fail2;
>>> ? ? ? ?}
>>> ? ? ? ?info->map.cached =
>>> ? ? ? ? ? ? ? ?ioremap_cached(info->map.phys, info->map.size);
>>> - ? ? ? if (!info->map.cached)
>>> + ? ? ? if (!info->map.cached) {
>>> ? ? ? ? ? ? ? ?printk(KERN_WARNING "Failed to ioremap cached %s\n",
>>> ? ? ? ? ? ? ? ? ? ? ? info->map.name);
>>
>>
>> This might not be an error at all, it's a warning. The cached mapping is
>> for performance reason on some platforms, it should be working all right
>> without it.
>
> Thanks, I just have a doubt regarding this condition judement, so
> thanks for your comments.
>
>>
>>> + ? ? ? ? ? ? ? ret = -ENOMEM;
>>> + ? ? ? ? ? ? ? goto fail3;
>>> + ? ? ? }
>>> ? ? ? ?info->map.inval_cache = pxa2xx_map_inval_cache;
>>> ? ? ? ?simple_map_init(&info->map);
>>>
>>> @@ -97,10 +110,8 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>>> ? ? ? ?info->mtd = do_map_probe(flash->map_name, &info->map);
>>>
>>> ? ? ? ?if (!info->mtd) {
>>> - ? ? ? ? ? ? ? iounmap((void *)info->map.virt);
>>> - ? ? ? ? ? ? ? if (info->map.cached)
>>> - ? ? ? ? ? ? ? ? ? ? ? iounmap(info->map.cached);
>>> - ? ? ? ? ? ? ? return -EIO;
>>> + ? ? ? ? ? ? ? ret = -EIO;
>>
>> See above.
>>
>>> + ? ? ? ? ? ? ? goto fail4;
>>> ? ? ? ?}
>>> ? ? ? ?info->mtd->owner = THIS_MODULE;
>>>
>>> @@ -124,13 +135,21 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>>>
>>> ? ? ? ?platform_set_drvdata(pdev, info);
>>> ? ? ? ?return 0;
>>> +
>>> +fail4: iounmap(info->map.cached);
>>> +fail3: iounmap(info->map.virt);
>>> +fail2: kfree(info);
>>> +fail1: release_mem_region(res->start, resource_size(res));
>>> +fail0:
>>> + ? ? ? return ret;
>>> ?}
>>>
>>> ?static int __devexit pxa2xx_flash_remove(struct platform_device *dev)
>>> ?{
>>> ? ? ? ?struct pxa2xx_flash_info *info = platform_get_drvdata(dev);
>>> + ? ? ? struct resource *res;
>>>
>>> - ? ? ? platform_set_drvdata(dev, NULL);
>>
>> What's wrong with the above statement? And normally there is some benefit
>> of setting drive data to be NULL, as the driver data could be used concurrently
>> during removal (i.e. an interrupt handler if the IRQ is not already disabled).
>> Though relying on this behavior to safely remove a device is _not_ by anyway
>> recommended.
>
> I got it,so, setting the drive data to be NULL should be as early as possible.
>
>>
>>> + ? ? ? res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>
>>> ?#ifdef CONFIG_MTD_PARTITIONS
>>> ? ? ? ?if (info->nr_parts)
>>> @@ -141,10 +160,12 @@ static int __devexit pxa2xx_flash_remove(struct platform_device *dev)
>>>
>>> ? ? ? ?map_destroy(info->mtd);
>>> ? ? ? ?iounmap(info->map.virt);
>>> - ? ? ? if (info->map.cached)
>>> - ? ? ? ? ? ? ? iounmap(info->map.cached);
>>> + ? ? ? iounmap(info->map.cached);
>>
>> See above, the map.cached is supposed to be optional and can only
>> be removed if it's mapped, no force here.
>>
>>> ? ? ? ?kfree(info->parts);
>>> ? ? ? ?kfree(info);
>>> + ? ? ? release_mem_region(res->start, resource_size(res));
>>> + ? ? ? platform_set_drvdata(dev, NULL);
>>> +
>>> ? ? ? ?return 0;
>>> ?}
>>>
>>> --
>>> 1.6.3.3
>>>
>>
>
>
>
> --
> *linux-arm-kernel mailing list
> mail addr:linux-arm-kernel at lists.infradead.org
> you can subscribe by:
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> * linux-arm-NUC900 mailing list
> mail addr:NUC900 at googlegroups.com
> main web: https://groups.google.com/group/NUC900
> you can subscribe it by sending me mail:
> mcuos.com at gmail.com
>



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From eric.y.miao at gmail.com  Sat Jun  5 03:55:34 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat,  5 Jun 2010 15:55:34 +0800
Subject: [PATCH 0/4] [ARM] Reduce the defconfig numbers for PXA
Message-ID: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com>

1. dma_needs_bounce() prevents it8152.c and sa1111.c from being built 
   together. Actually it8152.c is sane and dma_needs_bounce() can be
   removed simply. (Mike, could you give it a test?)

2. Currently, zaurus is not able to be built into a single kernel with
   other boards, since arch/arm/boot/compressed/head-sharpsl.S will
   try detecting the machine ID and will cause a dead loop on other
   boards at run-time. (if we stick with kexecboot or u-boot on
   zaurus, maybe we can remove head-sharpsl.S as well, and merge them
   into pxa2xx_defconfig as well)

3. All board configs with CONFIG_PXA2[57]x=y are now merged into pxa2xx_defconfig

4. All board configs with CONFIG_PXA3xx=y are now merged into pxa3xx_defconfig

The merge is rough, pxa2xx_defconfig as an example:

  1. $> cat mainstone_defconfig > .config
  2. $> for i in $(pxa2xx board defconfigs other than mainstone_defconfig); do
	    sed '/# CONFIG.*is not set/d' $i >> pxa2xx_defconfig
	done
  3. $> make oldconfig
  4. $> cp .config arch/arm/configs/pxa2xx_defconfig

The idea is to use mainstone_defconfig as a base, append all those
inclusive config options (not those "# CONFIG.*is not set").

Conflicts can happen with:

  - CONFIG_* being 'y' or 'm', this is less important provided the
    platform is sane enough to support both builtin and modules

  - CONFIG_* being a value type, the former will always be overwritten
    e.g. CONFIG_CMDLINE

That's why it's rough. I don't have time to look into those conflicts
though, I'd like each board maintainer to give it a test.



From eric.y.miao at gmail.com  Sat Jun  5 03:55:35 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat,  5 Jun 2010 15:55:35 +0800
Subject: [PATCH 1/4] [ARM] Remove now unnecessary dma_needs_bounce()
In-Reply-To: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1275724538-5075-2-git-send-email-eric.y.miao@gmail.com>

With a correct dev->dma_mask before calling dmabounce_register_dev(),
dma_needs_bounce() is not necessary.

The above is true for it8152.c and ixp4xx/common-pci.c.

The sa1111, though, is a bit complicated. Until it's fully understood
and fixed, dma_needs_bounce() for sa1111 is kept if CONFIG_SA1111 is
enabled with no side effect (with the condition of machine_is_*)

Signed-off-by: Eric Miao <eric.y.miao at gmail.com>
---
 arch/arm/common/it8152.c           |    8 --------
 arch/arm/include/asm/dma-mapping.h |    7 +++++++
 arch/arm/mach-ixp4xx/common-pci.c  |    5 -----
 3 files changed, 7 insertions(+), 13 deletions(-)

diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index 7974baa..6c09135 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -263,14 +263,6 @@ static int it8152_pci_platform_notify_remove(struct device *dev)
 	return 0;
 }
 
-int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
-{
-	dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
-		__func__, dma_addr, size);
-	return (dev->bus == &pci_bus_type) &&
-		((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
-}
-
 int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
 {
 	it8152_io.start = IT8152_IO_BASE + 0x12000;
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 69ce072..c80d4d2 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -298,7 +298,14 @@ extern void dmabounce_unregister_dev(struct device *);
  * DMA access and 1 if the buffer needs to be bounced.
  *
  */
+#ifdef CONFIG_SA1111
 extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
+#else
+static inline int dma_needs_bounce(struct device*, dma_addr_t, size_t)
+{
+	return 0;
+}
+#endif
 
 /*
  * The DMA API, implemented by dmabounce.c.  See below for descriptions.
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index e318153..c7aa0ac 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -337,11 +337,6 @@ static int ixp4xx_pci_platform_notify_remove(struct device *dev)
 	return 0;
 }
 
-int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
-{
-	return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
-}
-
 /*
  * Only first 64MB of memory can be accessed via PCI.
  * We use GFP_DMA to allocate safe buffers to do map/unmap.
-- 
1.7.0.4



From eric.y.miao at gmail.com  Sat Jun  5 03:58:32 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 5 Jun 2010 15:58:32 +0800
Subject: [PATCH 1/3] MTD/pxa: patch for error return value method of 
	pxa2xx-flash.c
In-Reply-To: <AANLkTikJiPjl3LKVqgqtlK2YEePXDf7K6EdOlUE4uzBb@mail.gmail.com>
References: <4C09F15E.9020408@gmail.com>
	<AANLkTinLfGD-x-861sFK9r2zW5aEZvyXIB4PFKJl8NDZ@mail.gmail.com> 
	<AANLkTikJiPjl3LKVqgqtlK2YEePXDf7K6EdOlUE4uzBb@mail.gmail.com>
Message-ID: <AANLkTilQQcjCCF1bG7qfJ27sOD8JcGzCYhCf3kVmzXw7@mail.gmail.com>

On Sat, Jun 5, 2010 at 3:38 PM, Wan ZongShun <mcuos.com at gmail.com> wrote:
> Hi Eric,
>
> Thanks for your review.
>
> 2010/6/5 Eric Miao <eric.y.miao at gmail.com>:
>> 2010/6/5 Wan ZongShun <mcuos.com at gmail.com>:
>>> This patch is to re-implement the 'pxa2xx-flash.c' error return value method
>>> of probe() and remove() function,the old return way can arouse the 'info' memory
>>> leak risk.
>>>
>>> Signed-off-by :Wan ZongShun <mcuos.com at gmail.com>
>>>
>>> ---
>>> ?drivers/mtd/maps/pxa2xx-flash.c | ? 47 ++++++++++++++++++++++++++++----------
>>> ?1 files changed, 34 insertions(+), 13 deletions(-)
>>>
>>> diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
>>> index dd90880..1d2583f 100644
>>> --- a/drivers/mtd/maps/pxa2xx-flash.c
>>> +++ b/drivers/mtd/maps/pxa2xx-flash.c
>>> @@ -60,12 +60,21 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>>> ? ? ? ?int ret = 0;
>>>
>>> ? ? ? ?res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> - ? ? ? if (!res)
>>> - ? ? ? ? ? ? ? return -ENODEV;
>>> + ? ? ? if (!res) {
>>> + ? ? ? ? ? ? ? ret = -ENODEV;
>>> + ? ? ? ? ? ? ? goto fail0;
>>> + ? ? ? }
>>
>> Can just return -ENODEV, why bother goto here?
>>
>>> +
>>> + ? ? ? if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
>>> + ? ? ? ? ? ? ? ret = -EBUSY;
>>> + ? ? ? ? ? ? ? goto fail0;
>>> + ? ? ? }
>>>
>>
>> Same here, nothing to release, can just return -EBUSY here. Provided I
>> always doubt the necessity of request_mem_region() here since the resource
>> should have been claimed when the platform device is registered, this is
>> possibly going to claim a sub-region of that resource. But that's another
>> story.
>
> I agree with you.
> So, keep it be there or remove it?
>

I'd recommend not to add it in this patch. You can have another patch
to add it if it's necessary.

> Could Keeping it make a more compatibility code?
>
>
>>
>>> ? ? ? ?info = kzalloc(sizeof(struct pxa2xx_flash_info), GFP_KERNEL);
>>> - ? ? ? if (!info)
>>> - ? ? ? ? ? ? ? return -ENOMEM;
>>> + ? ? ? if (!info) {
>>> + ? ? ? ? ? ? ? ret = -ENOMEM;
>>> + ? ? ? ? ? ? ? goto fail1;
>>> + ? ? ? }
>>>
>>> ? ? ? ?info->map.name = (char *) flash->name;
>>> ? ? ? ?info->map.bankwidth = flash->width;
>>> @@ -78,13 +87,17 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>>> ? ? ? ?if (!info->map.virt) {
>>> ? ? ? ? ? ? ? ?printk(KERN_WARNING "Failed to ioremap %s\n",
>>> ? ? ? ? ? ? ? ? ? ? ? info->map.name);
>>> - ? ? ? ? ? ? ? return -ENOMEM;
>>> + ? ? ? ? ? ? ? ret = -ENOMEM;
>>> + ? ? ? ? ? ? ? goto fail2;
>>> ? ? ? ?}
>>> ? ? ? ?info->map.cached =
>>> ? ? ? ? ? ? ? ?ioremap_cached(info->map.phys, info->map.size);
>>> - ? ? ? if (!info->map.cached)
>>> + ? ? ? if (!info->map.cached) {
>>> ? ? ? ? ? ? ? ?printk(KERN_WARNING "Failed to ioremap cached %s\n",
>>> ? ? ? ? ? ? ? ? ? ? ? info->map.name);
>>
>>
>> This might not be an error at all, it's a warning. The cached mapping is
>> for performance reason on some platforms, it should be working all right
>> without it.
>
> Thanks, I just have a doubt regarding this condition judement, so
> thanks for your comments.
>
>>
>>> + ? ? ? ? ? ? ? ret = -ENOMEM;
>>> + ? ? ? ? ? ? ? goto fail3;
>>> + ? ? ? }
>>> ? ? ? ?info->map.inval_cache = pxa2xx_map_inval_cache;
>>> ? ? ? ?simple_map_init(&info->map);
>>>
>>> @@ -97,10 +110,8 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>>> ? ? ? ?info->mtd = do_map_probe(flash->map_name, &info->map);
>>>
>>> ? ? ? ?if (!info->mtd) {
>>> - ? ? ? ? ? ? ? iounmap((void *)info->map.virt);
>>> - ? ? ? ? ? ? ? if (info->map.cached)
>>> - ? ? ? ? ? ? ? ? ? ? ? iounmap(info->map.cached);
>>> - ? ? ? ? ? ? ? return -EIO;
>>> + ? ? ? ? ? ? ? ret = -EIO;
>>
>> See above.
>>
>>> + ? ? ? ? ? ? ? goto fail4;
>>> ? ? ? ?}
>>> ? ? ? ?info->mtd->owner = THIS_MODULE;
>>>
>>> @@ -124,13 +135,21 @@ static int __init pxa2xx_flash_probe(struct platform_device *pdev)
>>>
>>> ? ? ? ?platform_set_drvdata(pdev, info);
>>> ? ? ? ?return 0;
>>> +
>>> +fail4: iounmap(info->map.cached);
>>> +fail3: iounmap(info->map.virt);
>>> +fail2: kfree(info);
>>> +fail1: release_mem_region(res->start, resource_size(res));
>>> +fail0:
>>> + ? ? ? return ret;
>>> ?}
>>>
>>> ?static int __devexit pxa2xx_flash_remove(struct platform_device *dev)
>>> ?{
>>> ? ? ? ?struct pxa2xx_flash_info *info = platform_get_drvdata(dev);
>>> + ? ? ? struct resource *res;
>>>
>>> - ? ? ? platform_set_drvdata(dev, NULL);
>>
>> What's wrong with the above statement? And normally there is some benefit
>> of setting drive data to be NULL, as the driver data could be used concurrently
>> during removal (i.e. an interrupt handler if the IRQ is not already disabled).
>> Though relying on this behavior to safely remove a device is _not_ by anyway
>> recommended.
>
> I got it,so, setting the drive data to be NULL should be as early as possible.
>

Normally yes. But I don't think that's a guarantee of a safe removal though.


From eric.y.miao at gmail.com  Sat Jun  5 03:59:56 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 5 Jun 2010 15:59:56 +0800
Subject: [PATCH 1/3] MTD/pxa: patch for error return value method of 
	pxa2xx-flash.c
In-Reply-To: <AANLkTilydl5oKETCC69C_QY6xJa3mIXve097JU6qevfp@mail.gmail.com>
References: <4C09F15E.9020408@gmail.com>
	<AANLkTinLfGD-x-861sFK9r2zW5aEZvyXIB4PFKJl8NDZ@mail.gmail.com> 
	<AANLkTikJiPjl3LKVqgqtlK2YEePXDf7K6EdOlUE4uzBb@mail.gmail.com> 
	<AANLkTilydl5oKETCC69C_QY6xJa3mIXve097JU6qevfp@mail.gmail.com>
Message-ID: <AANLkTile8PqagLri8n1Y0Xn03e8STx7XQODUx83woYNE@mail.gmail.com>

On Sat, Jun 5, 2010 at 3:53 PM, Wan ZongShun <mcuos.com at gmail.com> wrote:
> Hi Eric,
>
> This following piece of code:
>
> ? ? ? ?if (!info->map.virt) {
> ? ? ? ? ? ? ? ?printk(KERN_WARNING "Failed to ioremap %s\n",
> ? ? ? ? ? ? ? ? ? ? ? info->map.name);
> ? ? ? ? ? ? ? ?ret = -ENOMEM;
> ? ? ? ? ? ? ? ?goto fail2;
> ? ? ? ?}
>
> Shouldn't ?the 'KERN_ERR' in stead of the 'KERN_WARNING '?
> Because the ?'info->map.virt == NULL' can arouse the serious crash.
>

The thing is you need to figure out if it is mandatory because we
have another info->map.cached just in case. Disaster is both can
not be mapped.


From eric.y.miao at gmail.com  Sat Jun  5 04:04:59 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 5 Jun 2010 16:04:59 +0800
Subject: [PATCH 2/4] [ARM] pxa: merge all pxa2xx board configs into 
	pxa2xx_defconfig
In-Reply-To: <AANLkTin5mvdRG3R2JGOnAmakRaCXCTTJTGnwmA9gmTVP@mail.gmail.com>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com> 
	<1275724538-5075-3-git-send-email-eric.y.miao@gmail.com>
	<AANLkTin5mvdRG3R2JGOnAmakRaCXCTTJTGnwmA9gmTVP@mail.gmail.com>
Message-ID: <AANLkTint336Ik0HszyMbc748lcv7HU2LKxOvD14XZupm@mail.gmail.com>

On Sat, Jun 5, 2010 at 4:03 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> The change is apparently too much, I'm attaching the patch as an
> attachment here and compressed :-(
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From eric.y.miao at gmail.com  Sat Jun  5 04:05:28 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 5 Jun 2010 16:05:28 +0800
Subject: [PATCH 4/4] [ARM] pxa: merge {corgi,spitz}_defconfig into 
	zaurus_defconfig
In-Reply-To: <1275724538-5075-5-git-send-email-eric.y.miao@gmail.com>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com> 
	<1275724538-5075-5-git-send-email-eric.y.miao@gmail.com>
Message-ID: <AANLkTiliwWE4A7IypQp8zkxu_W_jyUiegBtb-tIAsNq6@mail.gmail.com>

Patch in attachment.
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From stefan at datenfreihafen.org  Sat Jun  5 04:05:56 2010
From: stefan at datenfreihafen.org (Stefan Schmidt)
Date: Sat, 5 Jun 2010 10:05:56 +0200
Subject: defconfig information
In-Reply-To: <20100604222820.GA4438@kyllikki.org>
References: <20100604222820.GA4438@kyllikki.org>
Message-ID: <20100605080556.GA6441@excalibur.local>

Hello.

On Fri, 2010-06-04 at 23:28, Vincent Sanders wrote:
> With all the recent issues over default configurations I have decided
> to release the Kernel autobuilder fifth anniversary statistics a bit
> early.

Thanks to the people involved keeping this working.

> The community usage of this service has dropped to an all time low
> (only six people actually used it in the last month) and I am
> seriously considering if it serves a useful purpose any longer.

What do you mean by "used it"? Is there anything else then subscribing to the ml
and get the build mails?

I found those mails very useful to have a fast overview if something broke most
of the arm builds. Getting a mail about the MIPS build showed useless to me tho
as none of the builds ever succeded.

regards
Stefan Schmidt


From balakrishnan at e-consystems.com  Tue Jun  1 01:44:18 2010
From: balakrishnan at e-consystems.com (balakrishnan)
Date: Tue, 01 Jun 2010 11:14:18 +0530
Subject: pxa300 - DDRAM base value
Message-ID: <1275371058.7001.35.camel@balakrishnan-desktop>

I am working on pxa300 based development board and using Linux 2.6.34.
This Linux kernel already has support for following boards
1. zylonite_pxa300
2. cm-x300 
3. colibri-pxa300
4. littleton

My doubt is that pxa300 based boards are using "0xa0000000"  as DDRAM
base and PHYS_OFFSET is also defined in
"arch/arm/mach-pxa/include/mach/memory.h" as 0xa0000000.
But in our board  DDR is mapped in 0x80000000. Does it make any
problem?. Because after mmu is turned ON, my board is hanging. 

"zreladdr-y   := 0x80008000" is defined in
"arch/arm/mach-pxa/Makefile.boot" file .
my machine_desc is as follows 
.phys_io        = 0x40000000, 
.io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,  
.boot_params    = 0x80000100,  

With Thanks
J.Balakrishnan 
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From vinayakpane at csu.fullerton.edu  Tue Jun  1 13:27:42 2010
From: vinayakpane at csu.fullerton.edu (Vinayak Pane)
Date: Tue, 1 Jun 2010 13:27:42 -0400
Subject: Preload engine in ARMv7 (cortex A8)
Message-ID: <AANLkTilGu3OC_tth-Wurgu1jcm5zKKntINGc-A8CwkxI@mail.gmail.com>

Hi Reader,

I am planning to utilize the PreLoad Engine for L2 cache. In past, I have
played with cache locking with line by line in ARM9. There I could recall
that tags and indexes are generated on basis of physical address of the
data. Now in case of PLE we have the start address and number of lines to
fill with. Does the PLE operation will leave some indexes empty ? Or does
the PLE populate all the lines in that way with the source data address ? Do
I need to start PLE for the block of size equal to that of way-size ? To
ensure no lines remain empty  and to ensure no line gets overwriten by other
line.

Appreciate your comments.

Thanks
vinayak
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From nobin.mathew at gmail.com  Wed Jun  2 12:08:52 2010
From: nobin.mathew at gmail.com (Nobin Mathew)
Date: Wed, 2 Jun 2010 21:38:52 +0530
Subject: make ARM=arm menuconfig problem in mainline
In-Reply-To: <20100602085748.6771e025.randy.dunlap@oracle.com>
References: <AANLkTikC61Y9g-WbqwgGDghDSy2XtgraFSRoZYkHRGTG@mail.gmail.com>
	<AANLkTilEYHVHJrj_KgF48OYCSEUcsKLi57Q_Y73d9va-@mail.gmail.com>
	<20100602085748.6771e025.randy.dunlap@oracle.com>
Message-ID: <AANLkTilpzeYVExQfLgpVmS3bPvb_h3kmWaatidekI-0r@mail.gmail.com>

Sorry if attachments are not allowed, when I go to select ARM system
type(OMAP, Davinci etc), I am not seeing any entries there in the pop
up window. When I remove  bool "Samsung S3C2410, S3C2412, S3C2413,
S3C2416, S3C2440,
>> S3C2442, S3C2443, S3C2450"  it is working fine. I feel it is something to do with length of that string.

Thanks
Nobin

On Wed, Jun 2, 2010 at 9:27 PM, Randy Dunlap <randy.dunlap at oracle.com> wrote:
> On Wed, 2 Jun 2010 20:04:28 +0530 Nobin Mathew wrote:
>
>> adding linux-arm-kernel at lists.infradead.org
>>
>> Hi,
>>
>> The following entry creates problem in ARM System type menu. I am
>> using a Fedora 12 system.
>
> What kind of problem does it create?
> It seems to work for me (on f11, not f12).
> Does it have something to do with F12 specifically?
>
>
>> Length of bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
>> S3C2442, S3C2443, S3C2450" is the problem. How can I fix it.
>
> Describe the problem, please.
>
>> config ARCH_S3C2410
>> ? ? ? ?bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
>> S3C2442, S3C2443, S3C2450"
>> ? ? ? ?select GENERIC_GPIO
>> ? ? ? ?select ARCH_HAS_CPUFREQ
>> ? ? ? ?select HAVE_CLK
>> ? ? ? ?select ARCH_USES_GETTIMEOFFSET
>> ? ? ? ?help
>> ? ? ? ? ?Samsung S3C2410X CPU based systems, such as the Simtec Electronics
>> ? ? ? ? ?BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
>> ? ? ? ? ?the Samsung SMDK2410 development board (and derivatives).
>>
>> ? ? ? ? ?Note, the S3C2416 and the S3C2450 are so close that they even share
>> ? ? ? ? ?the same SoC ID code. This means that there is no seperate machine
>> ? ? ? ? ?directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
>
>
> ---
> ~Randy
> *** Remember to use Documentation/SubmitChecklist when testing your code ***
>
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From jason77.wang at gmail.com  Thu Jun  3 08:05:44 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Thu,  3 Jun 2010 20:05:44 +0800
Subject: [V2 1/3] mxc: Add support for the imx51 3-stack board
In-Reply-To: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275566746-6510-2-git-send-email-jason77.wang@gmail.com>

3-stack is a reference board from Freescale for their i.MX51 SoC.

Add board definition, Kconfig and Makefile to enable Freescale 3-stack
board.

Boot tested on a i.MX51 3-stack Rev2.0 board

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx5/Kconfig                       |    5 +
 arch/arm/mach-mx5/Makefile                      |    2 +-
 arch/arm/mach-mx5/board-mx51_3ds.c              |  263 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   70 ++++++
 arch/arm/plat-mxc/include/mach/iomux-mx51.h     |   10 +-
 5 files changed, 345 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
 create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 1576d51..6d45f44 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -15,4 +15,9 @@ config MACH_MX51_BABBAGE
 	  u-boot. This includes specific configurations for the board and its
 	  peripherals.
 
+config MACH_MX51_3DS
+	bool "Support MX51PDK (3DS)"
+	help
+	  Include support for MX51PDK (3DS) platform. This includes specific
+	  configurations for the board and its peripherals.
 endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index bf23f86..c757c59 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -6,4 +6,4 @@
 obj-y   := cpu.o mm.o clock-mx51.o devices.o
 
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-
+obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
new file mode 100644
index 0000000..5da90e9
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx51.h>
+#include <mach/board-mx51_3ds.h>
+#include <mach/imx-uart.h>
+
+#include "devices.h"
+
+static void __iomem *brd_io;
+
+static void expio_ack_irq(u32 irq);
+
+static struct pad_desc mx51_3ds_pads[] = {
+	/* UART1 */
+	MX51_PAD_UART1_RXD__UART1_RXD,
+	MX51_PAD_UART1_TXD__UART1_TXD,
+	MX51_PAD_UART1_RTS__UART1_RTS,
+	MX51_PAD_UART1_CTS__UART1_CTS,
+
+	/* UART2 */
+	MX51_PAD_UART2_RXD__UART2_RXD,
+	MX51_PAD_UART2_TXD__UART2_TXD,
+	MX51_PAD_EIM_D25__UART2_CTS,
+	MX51_PAD_EIM_D26__UART2_RTS,
+
+	/* UART3 */
+	MX51_PAD_GPIO_1_22__UART3_RXD,
+	MX51_PAD_GPIO_1_23__UART3_TXD,
+	MX51_PAD_EIM_D24__UART3_CTS,
+	MX51_PAD_EIM_D27__UART3_RTS,
+
+	/* CPLD PARENT IRQ PIN */
+	MX51_PAD_GPIO_1_6__GPIO1_6,
+};
+
+
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+static struct resource smsc911x_resources[] = {
+	{
+		.start = LAN9217_BASE_ADDR,
+		.end = LAN9217_BASE_ADDR + 0x100 - 1,
+		.flags = IORESOURCE_MEM,
+	} , {
+		.start = EXPIO_INT_ENET,
+		.end = EXPIO_INT_ENET,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct smsc911x_platform_config smsc911x_config = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+};
+
+static struct platform_device smsc_lan9217_device = {
+	.name = "smsc911x",
+	.id = 0,
+	.dev = {
+		.platform_data = &smsc911x_config,
+	},
+	.num_resources = ARRAY_SIZE(smsc911x_resources),
+	.resource = smsc911x_resources,
+};
+
+static void mxc_init_enet(void)
+{
+	if (brd_io != NULL)
+		platform_device_register(&smsc_lan9217_device);
+}
+#else
+static inline void mxc_init_enet(void)
+{
+}
+#endif
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+	u32 imr_val;
+	u32 int_valid;
+	u32 expio_irq;
+
+	desc->chip->mask(irq);	/* irq = gpio irq number */
+
+	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
+	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
+
+	expio_irq = MXC_BOARD_IRQ_START;
+	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+		struct irq_desc *d;
+		if ((int_valid & 1) == 0)
+			continue;
+		d = irq_desc + expio_irq;
+		if (unlikely(!(d->handle_irq)))
+			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
+		else
+			d->handle_irq(expio_irq, d);
+	}
+
+	desc->chip->ack(irq);
+	desc->chip->unmask(irq);
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * @param irq		an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg |= (1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+/*
+ * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
+ * @param irq		an expanded io virtual irq number
+ */
+static void expio_ack_irq(u32 irq)
+{
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	expio_mask_irq(irq);
+}
+
+/*
+ * Enable a expio pin's interrupt by clearing the bit in the imr.
+ * @param irq		a expio virtual irq number
+ */
+static void expio_unmask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg &= ~(1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+	.ack = expio_ack_irq,
+	.mask = expio_mask_irq,
+	.unmask = expio_unmask_irq,
+};
+
+static int __init mxc_expio_init(void)
+{
+	int i;
+
+	brd_io = ioremap(BOARD_IO_ADDR, SZ_4K);
+	if (brd_io == NULL)
+		return -ENOMEM;
+
+	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
+		pr_info("3-Stack Debug board not detected\n");
+		iounmap(brd_io);
+		brd_io = NULL;
+		return -ENODEV;
+	}
+
+	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
+		readw(brd_io + CPLD_CODE_VER_REG));
+
+	/*
+	 * Configure INT line as GPIO input
+	 */
+	gpio_request(MX51_3DS_CPLD_IRQ_PIN, "gpio1_6");
+	gpio_direction_input(MX51_3DS_CPLD_IRQ_PIN);
+
+	/* disable the interrupt and clear the status */
+	__raw_writew(0, brd_io + INTR_MASK_REG);
+	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
+	for (i = MXC_EXP_IO_BASE;
+	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
+		set_irq_chip(i, &expio_irq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+	set_irq_type(EXPIO_PARENT_INT, IRQF_TRIGGER_LOW);
+	set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler);
+
+	return 0;
+}
+
+/* Serial ports */
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static struct imxuart_platform_data uart_pdata = {
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	mxc_register_device(&mxc_uart_device1, &uart_pdata);
+	mxc_register_device(&mxc_uart_device2, &uart_pdata);
+}
+#else /* !SERIAL_IMX */
+static inline void mxc_init_imx_uart(void)
+{
+}
+#endif /* SERIAL_IMX */
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
+					ARRAY_SIZE(mx51_3ds_pads));
+	mxc_init_imx_uart();
+	mxc_expio_init();
+	mxc_init_enet();
+}
+
+static void __init mx51_3ds_timer_init(void)
+{
+	mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+	.init	= mx51_3ds_timer_init,
+};
+
+MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
+	.phys_io = MX51_AIPS1_BASE_ADDR,
+	.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+	.boot_params = PHYS_OFFSET + 0x100,
+	.map_io = mx51_map_io,
+	.init_irq = mx51_init_irq,
+	.init_machine = mxc_board_init,
+	.timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
new file mode 100644
index 0000000..035f7bc
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
+#define __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
+
+/*
+ * @file plat-mxc/include/mach/board-mx51_3ds.h
+ *
+ * @brief This file contains all the board level configuration options.
+ *
+ * It currently hold the options defined for MX51 3Stack Platform.
+ *
+ */
+
+#define DEBUG_BOARD_BASE_ADDRESS MX51_CS5_BASE_ADDR
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR	(DEBUG_BOARD_BASE_ADDRESS + 0x0)
+/* External UART */
+#define UARTA_BASE_ADDR		(DEBUG_BOARD_BASE_ADDRESS + 0x8000)
+#define UARTB_BASE_ADDR		(DEBUG_BOARD_BASE_ADDRESS + 0x10000)
+
+#define BOARD_IO_ADDR		(DEBUG_BOARD_BASE_ADDRESS + 0x20000)
+/* LED switchs */
+#define LED_SWITCH_REG		0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG	0x08
+/* status, interrupt */
+#define INTR_STATUS_REG	0x10
+#define INTR_MASK_REG		0x38
+#define INTR_RESET_REG		0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG	0x40
+#define MAGIC_NUMBER2_REG	0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG	0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG	0x58
+/* module reset register*/
+#define MODULE_RESET_REG	0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG	0x68
+
+#define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
+
+#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
+#define MXC_MAX_EXP_IO_LINES	16
+
+/* interrupts like external uart , external ethernet etc*/
+#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
+#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
+#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
+#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
+#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
+
+/* Define CPLD interrupt pin */
+#define MX51_3DS_CPLD_IRQ_PIN	(GPIO_PORTA + 6)
+
+#endif	/* __ASM_ARCH_MXC_BOARD_MX51_3DS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index ab0f95d..895c750 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -70,8 +70,10 @@ typedef enum iomux_config {
 /* Babbage UART3 */
 #define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART2_CTS	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT4, 0x0, 0, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
 
 #define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
@@ -202,8 +204,8 @@ typedef enum iomux_config {
 #define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
 
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_GPIO_1_24__OWIRE_LINE	IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_ROW0__KEY_ROW0	IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_ROW1__KEY_ROW1	IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
@@ -306,7 +308,7 @@ typedef enum iomux_config {
 #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_4__GPIO1_4	IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_5__GPIO1_5	IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_7__GPIO1_7	IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_8__GPIO1_8	IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
 						(PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
-- 
1.5.6.5



From jason77.wang at gmail.com  Thu Jun  3 08:05:46 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Thu,  3 Jun 2010 20:05:46 +0800
Subject: [V2 3/3] mx51/keypad: add keypad support for i.MX51 platforms
In-Reply-To: <1275566746-6510-3-git-send-email-jason77.wang@gmail.com>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-3-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275566746-6510-4-git-send-email-jason77.wang@gmail.com>

Add keypad controller device definition for all i.MX51 platforms,
add a dummy kpp clock for imx keypad driver and add keypad device
registration on i.MX51 3-stack board.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx5/board-mx51_3ds.c |   59 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mx5/clock-mx51.c     |    5 +++
 arch/arm/mach-mx5/devices.c        |   19 +++++++++++
 arch/arm/mach-mx5/devices.h        |    1 +
 4 files changed, 84 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 5da90e9..abc9f87 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/smsc911x.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -54,8 +55,65 @@ static struct pad_desc mx51_3ds_pads[] = {
 
 	/* CPLD PARENT IRQ PIN */
 	MX51_PAD_GPIO_1_6__GPIO1_6,
+
+	/* KPP */
+	MX51_PAD_KEY_ROW0__KEY_ROW0,
+	MX51_PAD_KEY_ROW1__KEY_ROW1,
+	MX51_PAD_KEY_ROW2__KEY_ROW2,
+	MX51_PAD_KEY_ROW3__KEY_ROW3,
+	MX51_PAD_KEY_COL0__KEY_COL0,
+	MX51_PAD_KEY_COL1__KEY_COL1,
+	MX51_PAD_KEY_COL2__KEY_COL2,
+	MX51_PAD_KEY_COL3__KEY_COL3,
+	MX51_PAD_KEY_COL4__KEY_COL4,
+	MX51_PAD_KEY_COL5__KEY_COL5,
+};
+
+#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
+static int mx51_3ds_board_keymap[] = {
+	KEY(0, 0, KEY_1),
+	KEY(0, 1, KEY_2),
+	KEY(0, 2, KEY_3),
+	KEY(0, 3, KEY_F1),
+	KEY(0, 4, KEY_UP),
+	KEY(0, 5, KEY_F2),
+
+	KEY(1, 0, KEY_4),
+	KEY(1, 1, KEY_5),
+	KEY(1, 2, KEY_6),
+	KEY(1, 3, KEY_LEFT),
+	KEY(1, 4, KEY_SELECT),
+	KEY(1, 5, KEY_RIGHT),
+
+	KEY(2, 0, KEY_7),
+	KEY(2, 1, KEY_8),
+	KEY(2, 2, KEY_9),
+	KEY(2, 3, KEY_F3),
+	KEY(2, 4, KEY_DOWN),
+	KEY(2, 5, KEY_F4),
+
+	KEY(3, 0, KEY_0),
+	KEY(3, 1, KEY_OK),
+	KEY(3, 2, KEY_ESC),
+	KEY(3, 3, KEY_ENTER),
+	KEY(3, 4, KEY_MENU),
+	KEY(3, 5, KEY_BACK)
 };
 
+static struct matrix_keymap_data mx51_3ds_map_data = {
+	.keymap		= mx51_3ds_board_keymap,
+	.keymap_size	= ARRAY_SIZE(mx51_3ds_board_keymap),
+};
+
+static void mxc_init_keypad(void)
+{
+	mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
 
 #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
 static struct resource smsc911x_resources[] = {
@@ -241,6 +299,7 @@ static void __init mxc_board_init(void)
 	mxc_init_imx_uart();
 	mxc_expio_init();
 	mxc_init_enet();
+	mxc_init_keypad();
 }
 
 static void __init mx51_3ds_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index d9f612d..60fced6 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
 	.parent = &ckil_clk,
 };
 
+static struct clk kpp_clk = {
+	.id = 0,
+};
+
 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
 	static struct clk name = {			\
 		.id		= i,			\
@@ -821,6 +825,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
+	_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 7130449..2aa4ea0 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -168,6 +168,25 @@ struct platform_device mxc_wdt = {
 	.resource = mxc_wdt_resources,
 };
 
+static struct resource mxc_kpp_resources[] = {
+	{
+		.start = MX51_MXC_INT_KPP,
+		.end = MX51_MXC_INT_KPP,
+		.flags = IORESOURCE_IRQ,
+	} , {
+		.start = MX51_KPP_BASE_ADDR,
+		.end = MX51_KPP_BASE_ADDR + 0x8 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct platform_device mxc_keypad_device = {
+	.name = "imx-keypad",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(mxc_kpp_resources),
+	.resource = mxc_kpp_resources,
+};
+
 static struct mxc_gpio_port mxc_gpio_ports[] = {
 	{
 		.chip.label = "gpio-0",
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index c879ae7..1fef140 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -6,3 +6,4 @@ extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbdr_udc_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device mxc_keypad_device;
-- 
1.5.6.5



From jason77.wang at gmail.com  Thu Jun  3 08:05:45 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Thu,  3 Jun 2010 20:05:45 +0800
Subject: [V2 2/3] mxc/iomux: add GPIO bank offset for iomux v3 platforms
In-Reply-To: <1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275566746-6510-3-git-send-email-jason77.wang@gmail.com>

From: Wang Hui <Hui.Wang at windriver.com>

These GPIO bank offsets are useful when define a gpio number.
E.G. when GPIO PORTC pin 6 is used for irq request pin of external
expanding device, we can define it like:
  #define EXP_PARENT_IRQ_PIN (GPIO_PORTC + 6)

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/include/mach/iomux-v3.h |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index f2f73d3..0880a4a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -89,6 +89,21 @@ struct pad_desc {
 #define PAD_CTL_SRE_FAST		(1 << 0)
 #define PAD_CTL_SRE_SLOW		(0 << 0)
 
+
+#define MX51_NUM_GPIO_PORT	4
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA	(0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB	(1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC	(2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD	(3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE	(4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF	(5 << GPIO_PORT_SHIFT)
+
 /*
  * setups a single pad in the iomuxer
  */
-- 
1.5.6.5



From timyao at gmail.com  Thu Jun  3 19:22:02 2010
From: timyao at gmail.com (Tim Yao)
Date: Thu, 3 Jun 2010 16:22:02 -0700
Subject: Question about flush_dcache_all in kernel start up code
Message-ID: <AANLkTimWFpNC_tXJB84pzVrg14Ot_Nk7WGVE9Qwvg_pK@mail.gmail.com>

Hi,
I have a question regarding the data cache flush routine called at the
beginning of kernel start up. At the beginning of the start up code, after
processor type and machine type look up and simple page table created, a
__switch_data is called which goes to __v7_setup in my case (since the CPU
is A9). Then at the beginning of the function it calls v7_flush_dcache_all.
This cache routine is in cache-v7.S and I see it actually does "clean and
invalidate" operation as opposed to invalidate only.

From eric.y.miao at gmail.com  Fri Jun  4 04:42:00 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 4 Jun 2010 16:42:00 +0800
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <AANLkTilyIb8WDAanNHlQKHco6rSjzNjNS9Q3TpWQqt8o@mail.gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<201006041036.39059.pieterg@gmx.com>
	<AANLkTilyIb8WDAanNHlQKHco6rSjzNjNS9Q3TpWQqt8o@mail.gmail.com>
Message-ID: <AANLkTin1Kt5ydz0Ipq04zYnzEfp69xv0Etu2Iu7FyXAo@mail.gmail.com>

That's supposed to be possible with ASoC, what's the exact problem?

- eric from G1

On Jun 4, 2010 4:39 PM, "pieterg" <pieterg at gmx.com> wrote:

On Friday 04 June 2010 03:10:14 Marek Vasut wrote:
> I just tested, PXA (mach-pxa) probably can be c...
For my boards (colibri) I see only one exception; I haven't managed to build
a single kernel with support for different AC97 chips.

I have to build separate WM9715 and UCB1400 kernels.

Rgds, Pieter


_______________________________________________
linux-arm-kernel mailing list
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From jason77.wang at gmail.com  Fri Jun  4 10:09:22 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:09:22 +0800
Subject: [V3 1/7] mxc: add common debug board for 3-stack platforms
In-Reply-To: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>
References: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275660568-7738-2-git-send-email-jason77.wang@gmail.com>

The debug board is little different for all mxc 3-stack(PDK)
platforms, it is possible here to add a common implementation to
support this board.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/Kconfig                        |   11 ++
 arch/arm/plat-mxc/Makefile                       |    1 +
 arch/arm/plat-mxc/cpld_debugboard.c              |  161 ++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/cpld_debugboard.h |   60 ++++++++
 4 files changed, 233 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-mxc/cpld_debugboard.c
 create mode 100644 arch/arm/plat-mxc/include/mach/cpld_debugboard.h

diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 7f7ad6f..8bf917e 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -81,6 +81,17 @@ config MXC_PWM
 	help
 	  Enable support for the i.MX PWM controller(s).
 
+config MXC_DEBUG_BOARD
+	bool "Enable MXC debug board(for 3-stack)"
+	help
+	  The debug board is an integral part of the MXC 3-stack(PDK)
+	  platforms, it can be attached or removed from the peripheral
+	  board. On debug board, several debug devices(ethernet, UART,
+	  buttons, LEDs and JTAG) are implemented. Between the MCU and
+	  these devices, a CPLD is added as a bridge which performs
+	  data/address de-multiplexing and decode, signal level shift,
+	  interrupt control and various board functions.
+
 config MXC_ULPI
 	bool
 
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 895bc3c..b9e8c6f 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
+obj-$(CONFIG_MXC_DEBUG_BOARD) += cpld_debugboard.o
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
diff --git a/arch/arm/plat-mxc/cpld_debugboard.c b/arch/arm/plat-mxc/cpld_debugboard.c
new file mode 100644
index 0000000..0554fa0
--- /dev/null
+++ b/arch/arm/plat-mxc/cpld_debugboard.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <mach/hardware.h>
+#include <mach/cpld_debugboard.h>
+
+static void __iomem *brd_io;
+static void expio_ack_irq(u32 irq);
+
+static struct resource smsc911x_resources[] = {
+	{
+		.flags = IORESOURCE_MEM,
+	} , {
+		.start = EXPIO_INT_ENET,
+		.end = EXPIO_INT_ENET,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct smsc911x_platform_config smsc911x_config = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+};
+
+struct platform_device smsc_lan9217_device = {
+	.name = "smsc911x",
+	.id = 0,
+	.dev = {
+		.platform_data = &smsc911x_config,
+	},
+	.num_resources = ARRAY_SIZE(smsc911x_resources),
+	.resource = smsc911x_resources,
+};
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+	u32 imr_val;
+	u32 int_valid;
+	u32 expio_irq;
+
+	desc->chip->mask(irq);	/* irq = gpio irq number */
+
+	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
+	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
+
+	expio_irq = MXC_BOARD_IRQ_START;
+	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+		struct irq_desc *d;
+		if ((int_valid & 1) == 0)
+			continue;
+		d = irq_desc + expio_irq;
+		if (unlikely(!(d->handle_irq)))
+			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
+		else
+			d->handle_irq(expio_irq, d);
+	}
+
+	desc->chip->ack(irq);
+	desc->chip->unmask(irq);
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * Irq is an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg |= (1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static void expio_ack_irq(u32 irq)
+{
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	expio_mask_irq(irq);
+}
+
+static void expio_unmask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg &= ~(1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+	.ack = expio_ack_irq,
+	.mask = expio_mask_irq,
+	.unmask = expio_unmask_irq,
+};
+
+int __init mxc_expio_init(u32 base, u32 p_irq)
+{
+	int i;
+
+	brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
+	if (brd_io == NULL)
+		return -ENOMEM;
+
+	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
+		pr_info("3-Stack Debug board not detected\n");
+		iounmap(brd_io);
+		brd_io = NULL;
+		return -ENODEV;
+	}
+
+	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
+		readw(brd_io + CPLD_CODE_VER_REG));
+
+	smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
+	smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
+
+	/*
+	 * Configure INT line as GPIO input
+	 */
+	gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
+	gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
+
+	/* disable the interrupt and clear the status */
+	__raw_writew(0, brd_io + INTR_MASK_REG);
+	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
+	for (i = MXC_EXP_IO_BASE;
+	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
+		set_irq_chip(i, &expio_irq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+	set_irq_type(p_irq, IRQF_TRIGGER_LOW);
+	set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
+
+	return 0;
+}
diff --git a/arch/arm/plat-mxc/include/mach/cpld_debugboard.h b/arch/arm/plat-mxc/include/mach/cpld_debugboard.h
new file mode 100644
index 0000000..a1422d2
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/cpld_debugboard.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_CPLD_DB_H__
+#define __ASM_ARCH_MXC_CPLD_DB_H__
+
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR(n)	(n + 0x0)
+/* External UART */
+#define UARTA_BASE_ADDR(n)	(n + 0x8000)
+#define UARTB_BASE_ADDR(n)	(n + 0x10000)
+
+#define BOARD_IO_ADDR(n)	(n + 0x20000)
+/* LED switchs */
+#define LED_SWITCH_REG		0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG	0x08
+/* status, interrupt */
+#define INTR_STATUS_REG	0x10
+#define INTR_MASK_REG		0x38
+#define INTR_RESET_REG		0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG	0x40
+#define MAGIC_NUMBER2_REG	0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG	0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG	0x58
+/* module reset register*/
+#define MODULE_RESET_REG	0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG	0x68
+
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_GPIO(irq)	((irq) - MXC_INTERNAL_IRQS)
+
+#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
+#define MXC_MAX_EXP_IO_LINES	16
+
+/* interrupts like external uart , external ethernet etc*/
+#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
+#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
+#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
+#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
+#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
+
+extern struct platform_device smsc_lan9217_device;
+
+int __init mxc_expio_init(u32 base, u32 p_irq);
+
+#endif /* __ASM_ARCH_MXC_CPLD_DB_H__ */
-- 
1.5.6.5



From jason77.wang at gmail.com  Fri Jun  4 10:09:23 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:09:23 +0800
Subject: [V3 2/7] mxc/iomux: add GPIO bank offset for iomux v3 platforms
In-Reply-To: <1275660568-7738-2-git-send-email-jason77.wang@gmail.com>
References: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275660568-7738-3-git-send-email-jason77.wang@gmail.com>

These GPIO bank offsets are useful when define a gpio number.
E.G. when GPIO PORTC pin 6 is used for irq request pin of external
expanding device, we can define it like:
  #define EXP_PARENT_IRQ_PIN (GPIO_PORTC + 6)

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/include/mach/iomux-v3.h |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index f2f73d3..0880a4a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -89,6 +89,21 @@ struct pad_desc {
 #define PAD_CTL_SRE_FAST		(1 << 0)
 #define PAD_CTL_SRE_SLOW		(0 << 0)
 
+
+#define MX51_NUM_GPIO_PORT	4
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA	(0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB	(1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC	(2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD	(3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE	(4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF	(5 << GPIO_PORT_SHIFT)
+
 /*
  * setups a single pad in the iomuxer
  */
-- 
1.5.6.5



From jason77.wang at gmail.com  Fri Jun  4 10:09:24 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:09:24 +0800
Subject: [V3 3/7] mx51/iomux: fix some pad names and make some cleanups
In-Reply-To: <1275660568-7738-3-git-send-email-jason77.wang@gmail.com>
References: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-2-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-3-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275660568-7738-4-git-send-email-jason77.wang@gmail.com>

Fix some pad names according to the naming convention and make some
cleanups for vertical lineup.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/include/mach/iomux-mx51.h |  507 ++++++++++++--------------
 1 files changed, 234 insertions(+), 273 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index ab0f95d..df9ecdf 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -57,278 +57,239 @@ typedef enum iomux_config {
 
 /*						PAD      MUX   ALT INPSE PATH PADCTRL */
 
-#define MX51_PAD_GPIO_2_0__EIM_D16	IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_1__EIM_D17	IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_2__EIM_D18	IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_3__EIM_D19	IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_4__EIM_D20	IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_5__EIM_D21	IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO_2_5	IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_6__EIM_D22	IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_7__EIM_D23	IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
-
-/* Babbage UART3 */
-#define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
-
-#define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30	IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31	IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_10__EIM_A16	IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_11__EIM_A17	IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_12__EIM_A18	IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_13__EIM_A19	IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_14__EIM_A20	IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_15__EIM_A21	IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_16__EIM_A22	IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_17__EIM_A23	IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_18__EIM_A24	IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_19__EIM_A25	IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_20__EIM_A26	IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_21__EIM_A27	IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0	IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1	IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_22__EIM_EB2	IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_23__EIM_EB3	IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_24__EIM_OE	IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_25__EIM_CS0	IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_26__EIM_CS1	IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_27__EIM_CS2	IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_28__EIM_CS3	IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_29__EIM_CS4	IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_30__EIM_CS5	IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_31__EIM_DTACK	IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_3_1__EIM_LBA	IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__EIM_CRE	IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1	IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__NANDF_WE_B	IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__NANDF_RE_B	IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__NANDF_ALE	IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__NANDF_CLE	IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__NANDF_WP_B	IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__NANDF_RB0	IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_9__NANDF_RB1	IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_10__NANDF_RB2	IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_11__NANDF_RB3	IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__GPIO_NAND	IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
-/* REVISIT: Not sure of these values
-
-  #define MX51_PAD_GPIO_1___NANDF_RB4	IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_13__NANDF_RB5	IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_15__NANDF_RB7	IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-*/
-#define MX51_PAD_GPIO_3_14__NANDF_RB6	IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_16__NANDF_CS0	IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_17__NANDF_CS1	IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_18__NANDF_CS2	IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_19__NANDF_CS3	IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_20__NANDF_CS4	IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_21__NANDF_CS5	IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_22__NANDF_CS6	IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_23__NANDF_CS7	IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT	IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_25__NANDF_D15	IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_26__NANDF_D14	IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_27__NANDF_D13	IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_28__NANDF_D12	IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_29__NANDF_D11	IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_30__NANDF_D10	IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_31__NANDF_D9	IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_0__NANDF_D8	IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_1__NANDF_D7	IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_2__NANDF_D6	IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_3__NANDF_D5	IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_4__NANDF_D4	IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_5__NANDF_D3	IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_6__NANDF_D2	IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_7__NANDF_D1	IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_8__NANDF_D0	IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__CSI1_D8	IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_13__CSI1_D9	IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10	IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11	IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12	IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13	IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14	IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15	IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16	IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17	IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18	IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19	IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC	IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC	IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK	IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK	IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PKE0__CSI1_PKE0	IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_9__CSI2_D12	IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_10__CSI2_D13	IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D14	IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D15	IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D16	IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D17	IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D18	IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D19	IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_13__CSI2_VSYNC	IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_14__CSI2_HSYNC	IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK	IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PKE0__CSI2_PKE0	IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_16__I2C1_CLK	IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_17__I2C1_DAT	IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD	IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD	IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_20__AUD3_BB_CK	IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_21__AUD3_BB_FS	IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_22__CSPI1_MOSI	IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_23__CSPI1_MISO	IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_24__CSPI1_SS0	IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_25__CSPI1_SS1	IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_26__CSPI1_RDY	IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_27__CSPI1_SCLK	IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
-
-/* Babbage UART1 */
-#define MX51_PAD_UART1_RXD__UART1_RXD	IOMUX_PAD(0x618, 0x228,	IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_TXD__UART1_TXD	IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_RTS__UART1_RTS	IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS	IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
-
-/* Babbage UART2 */
-#define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
-
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_24__OWIRE_LINE	IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0	IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1	IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2	IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3	IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0	IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1	IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2	IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3	IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4	IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5	IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK	IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR	IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO_1_27	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT	IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_GPIO_3_0__DI1_PIN11	IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_1__DI1_PIN12	IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__DI1_PIN13	IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__DI1_D0_CS	IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__DI1_D1_CS	IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN	IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO	IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK	IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS	IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0	IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1	IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2	IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3	IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4	IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5	IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6	IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7	IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8	IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9	IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3	IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2	IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP1__DI_GP1	IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DI_GP2	IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DI_GP3	IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4	IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2	IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3	IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI_GP4	IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0	IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1	IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2	IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3	IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4	IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5	IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_19__DISP2_DAT6	IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_29__DISP2_DAT7	IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_30__DISP2_DAT8	IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_31__DISP2_DAT9	IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD	IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK	IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0	IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1	IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2	IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3	IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_0__GPIO1_0	IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_1__GPIO1_1	IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD	IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK	IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0	IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1	IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2	IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3	IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_2__GPIO1_2	IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_3__GPIO1_3	IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_4__GPIO1_4	IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_5__GPIO1_5	IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_7__GPIO1_7	IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_8__GPIO1_8	IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
-						(PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
-#define MX51_PAD_GPIO_1_9__GPIO1_9	IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
-
-/* EIM */
-#define MX51_PAD_EIM_DA0__EIM_DA0	IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1	IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2	IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3	IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4	IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5	IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6	IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7	IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_DA8__EIM_DA8	IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9	IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10	IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11	IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12	IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13	IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14	IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15	IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__GPIO_2_0		IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__GPIO_2_1		IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__GPIO_2_2		IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__GPIO_2_3		IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__GPIO_2_4		IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO_2_5		IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__GPIO_2_6		IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__GPIO_2_7		IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__UART3_CTS		IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART3_RXD		IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART3_TXD		IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS		IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28		IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29		IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30		IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31		IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__GPIO_2_10		IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__GPIO_2_11		IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__GPIO_2_12		IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__GPIO_2_13		IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO_2_14		IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__GPIO_2_15		IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__GPIO_2_16		IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__GPIO_2_17		IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__GPIO_2_18		IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__GPIO_2_19		IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__GPIO_2_20		IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__GPIO_2_21		IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0		IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1		IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__GPIO_2_22		IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPIO_2_23		IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__GPIO_2_24		IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__GPIO_2_25		IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__GPIO_2_26		IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__GPIO_2_27		IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__GPIO_2_28		IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__GPIO_2_29		IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__GPIO_2_30		IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__GPIO_2_31		IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__GPIO_3_1		IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__GPIO_3_2		IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1		IOMUX_PAD(0x4D0, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__GPIO_3_3		IOMUX_PAD(0x4E4, 0x108, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__GPIO_3_4		IOMUX_PAD(0x4E8, 0x10C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__GPIO_3_5		IOMUX_PAD(0x4EC, 0x110, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__GPIO_3_6		IOMUX_PAD(0x4F0, 0x114, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__GPIO_3_7		IOMUX_PAD(0x4F4, 0x118, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__GPIO_3_8		IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPIO_3_9		IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__GPIO_3_10		IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__GPIO_3_11		IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__GPIO_3_12		IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB6__GPIO_3_14		IOMUX_PAD(0x5DC, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__GPIO_3_16		IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__GPIO_3_17		IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__GPIO_3_18		IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__GPIO_3_19		IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__GPIO_3_20		IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__GPIO_3_21		IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__GPIO_3_22		IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__GPIO_3_23		IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24	IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__GPIO_3_25		IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__GPIO_3_26		IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__GPIO_3_27		IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__GPIO_3_28		IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__GPIO_3_29		IOMUX_PAD(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__GPIO_3_30		IOMUX_PAD(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__GPIO_3_31		IOMUX_PAD(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__GPIO_4_0		IOMUX_PAD(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__GPIO_4_1		IOMUX_PAD(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__GPIO_4_2		IOMUX_PAD(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__GPIO_4_3		IOMUX_PAD(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__GPIO_4_4		IOMUX_PAD(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__GPIO_4_5		IOMUX_PAD(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__GPIO_4_6		IOMUX_PAD(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__GPIO_4_7		IOMUX_PAD(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__GPIO_4_8		IOMUX_PAD(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__GPIO_3_12		IOMUX_PAD(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__GPIO_3_13		IOMUX_PAD(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10		IOMUX_PAD(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11		IOMUX_PAD(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12		IOMUX_PAD(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13		IOMUX_PAD(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14		IOMUX_PAD(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15		IOMUX_PAD(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16		IOMUX_PAD(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17		IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18		IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19		IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC		IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC		IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK	IOMUX_PAD(0x5B4, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK		IOMUX_PAD(0x5B8, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PKE0__CSI1_PKE0		IOMUX_PAD(0x860, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__GPIO_4_9		IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__GPIO_4_10		IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__GPIO_4_11		IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__GPIO_4_12		IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__GPIO_4_11		IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__GPIO_4_12		IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__GPIO_4_11		IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__GPIO_4_12		IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__GPIO_4_13		IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__GPIO_4_14		IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15		IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PKE0__CSI2_PKE0		IOMUX_PAD(0x81C, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__GPIO_4_16		IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__GPIO_4_17		IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18		IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19		IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__GPIO_4_20		IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__GPIO_4_21		IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__GPIO_4_22		IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__GPIO_4_23		IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__GPIO_4_24		IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__GPIO_4_25		IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__GPIO_4_26		IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27		IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD		IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_TXD__UART1_TXD		IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_RTS__UART1_RTS		IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS		IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD		IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD		IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO_1_22		IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO_1_23		IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__GPIO_1_24		IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0		IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1		IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2		IOMUX_PAD(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3		IOMUX_PAD(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0		IOMUX_PAD(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1		IOMUX_PAD(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2		IOMUX_PAD(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3		IOMUX_PAD(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4		IOMUX_PAD(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5		IOMUX_PAD(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK		IOMUX_PAD(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR		IOMUX_PAD(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP		IOMUX_PAD(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO_1_27		IOMUX_PAD(0x680, 0x280, 2, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT		IOMUX_PAD(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	IOMUX_PAD(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	IOMUX_PAD(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	IOMUX_PAD(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	IOMUX_PAD(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	IOMUX_PAD(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	IOMUX_PAD(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__GPIO_3_0		IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO_3_1		IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO_3_2		IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO_3_3		IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO_3_4		IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5	IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6	IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7	IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8	IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0		IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1		IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2		IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3		IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4		IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5		IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6		IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7		IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8		IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9		IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	IOMUX_PAD(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	IOMUX_PAD(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	IOMUX_PAD(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	IOMUX_PAD(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	IOMUX_PAD(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	IOMUX_PAD(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	IOMUX_PAD(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	IOMUX_PAD(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	IOMUX_PAD(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	IOMUX_PAD(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	IOMUX_PAD(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3		IOMUX_PAD(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2		IOMUX_PAD(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP1__DI_GP1			IOMUX_PAD(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DI_GP2			IOMUX_PAD(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DI_GP3			IOMUX_PAD(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4		IOMUX_PAD(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2		IOMUX_PAD(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3		IOMUX_PAD(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	IOMUX_PAD(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI_GP4			IOMUX_PAD(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0		IOMUX_PAD(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1		IOMUX_PAD(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2		IOMUX_PAD(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3		IOMUX_PAD(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4		IOMUX_PAD(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5		IOMUX_PAD(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__GPIO_1_19		IOMUX_PAD(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__GPIO_1_29		IOMUX_PAD(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__GPIO_1_30		IOMUX_PAD(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__GPIO_1_31		IOMUX_PAD(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	IOMUX_PAD(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	IOMUX_PAD(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	IOMUX_PAD(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	IOMUX_PAD(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD		IOMUX_PAD(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK		IOMUX_PAD(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0		IOMUX_PAD(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1		IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2		IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3		IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_0__GPIO_1_0		IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_1__GPIO_1_1		IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD		IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK		IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0		IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1		IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2		IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3		IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
 
 #endif /* __MACH_IOMUX_MX51_H__ */
-- 
1.5.6.5



From jason77.wang at gmail.com  Fri Jun  4 10:09:25 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:09:25 +0800
Subject: [V3 4/7] mx51/iomux: add pad definition for mx51_3ds
In-Reply-To: <1275660568-7738-4-git-send-email-jason77.wang@gmail.com>
References: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-2-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-3-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-4-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275660568-7738-5-git-send-email-jason77.wang@gmail.com>

Add UART2, UART3 and GPIO_1_6 pad definitions for mx51_3ds board.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/include/mach/iomux-mx51.h |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index df9ecdf..76b1fbd 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -67,8 +67,10 @@ typedef enum iomux_config {
 #define MX51_PAD_EIM_D23__GPIO_2_7		IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D24__UART3_CTS		IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_EIM_D25__UART3_RXD		IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART2_CTS		IOMUX_PAD(0x414, 0x080, 4, 0x0, 0, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART3_TXD		IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS		IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS		IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS		IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_EIM_D28__EIM_D28		IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D29__EIM_D29		IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D30__EIM_D30		IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
@@ -183,8 +185,8 @@ typedef enum iomux_config {
 #define MX51_PAD_UART1_CTS__UART1_CTS		IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
 #define MX51_PAD_UART2_RXD__UART2_RXD		IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_UART2_TXD__UART2_TXD		IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART3_RXD__GPIO_1_22		IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_UART3_TXD__GPIO_1_23		IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO_1_22		IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO_1_23		IOMUX_PAD(0x634, 0x244, 1, 0x0, 0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_OWIRE_LINE__GPIO_1_24		IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_ROW0__KEY_ROW0		IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_ROW1__KEY_ROW1		IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
@@ -287,7 +289,7 @@ typedef enum iomux_config {
 #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
-- 
1.5.6.5



From jason77.wang at gmail.com  Fri Jun  4 10:09:26 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:09:26 +0800
Subject: [V3 5/7] mxc/mx51: Add support for the imx51 3-stack board
In-Reply-To: <1275660568-7738-5-git-send-email-jason77.wang@gmail.com>
References: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-2-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-3-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-4-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-5-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275660568-7738-6-git-send-email-jason77.wang@gmail.com>

3-stack is a reference board from Freescale for their i.MX51 SoC.

Add board definition, Kconfig and Makefile to enable Freescale 3-stack
board.

Boot tested on a i.MX51 3-stack Rev2.0 board

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx5/Kconfig                       |    6 ++
 arch/arm/mach-mx5/Makefile                      |    2 +-
 arch/arm/mach-mx5/board-mx51_3ds.c              |  100 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h |   27 ++++++
 4 files changed, 134 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-mx5/board-mx51_3ds.c
 create mode 100644 arch/arm/plat-mxc/include/mach/board-mx51_3ds.h

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 1576d51..6ef3428 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -15,4 +15,10 @@ config MACH_MX51_BABBAGE
 	  u-boot. This includes specific configurations for the board and its
 	  peripherals.
 
+config MACH_MX51_3DS
+	bool "Support MX51PDK (3DS)"
+	select MXC_DEBUG_BOARD
+	help
+	  Include support for MX51PDK (3DS) platform. This includes specific
+	  configurations for the board and its peripherals.
 endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index bf23f86..c757c59 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -6,4 +6,4 @@
 obj-y   := cpu.o mm.o clock-mx51.o devices.o
 
 obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
-
+obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
new file mode 100644
index 0000000..af0362c
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx51.h>
+#include <mach/board-mx51_3ds.h>
+#include <mach/imx-uart.h>
+#include <mach/cpld_debugboard.h>
+
+#include "devices.h"
+
+static struct pad_desc mx51_3ds_pads[] = {
+	/* UART1 */
+	MX51_PAD_UART1_RXD__UART1_RXD,
+	MX51_PAD_UART1_TXD__UART1_TXD,
+	MX51_PAD_UART1_RTS__UART1_RTS,
+	MX51_PAD_UART1_CTS__UART1_CTS,
+
+	/* UART2 */
+	MX51_PAD_UART2_RXD__UART2_RXD,
+	MX51_PAD_UART2_TXD__UART2_TXD,
+	MX51_PAD_EIM_D25__UART2_CTS,
+	MX51_PAD_EIM_D26__UART2_RTS,
+
+	/* UART3 */
+	MX51_PAD_UART3_RXD__UART3_RXD,
+	MX51_PAD_UART3_TXD__UART3_TXD,
+	MX51_PAD_EIM_D24__UART3_CTS,
+	MX51_PAD_EIM_D27__UART3_RTS,
+
+	/* CPLD PARENT IRQ PIN */
+	MX51_PAD_GPIO_1_6__GPIO1_6,
+};
+
+/* Serial ports */
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static struct imxuart_platform_data uart_pdata = {
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	mxc_register_device(&mxc_uart_device1, &uart_pdata);
+	mxc_register_device(&mxc_uart_device2, &uart_pdata);
+}
+#else /* !SERIAL_IMX */
+static inline void mxc_init_imx_uart(void)
+{
+}
+#endif /* SERIAL_IMX */
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx51_3ds_pads,
+					ARRAY_SIZE(mx51_3ds_pads));
+	mxc_init_imx_uart();
+
+	if (!mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+		platform_device_register(&smsc_lan9217_device);
+}
+
+static void __init mx51_3ds_timer_init(void)
+{
+	mx51_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mxc_timer = {
+	.init	= mx51_3ds_timer_init,
+};
+
+MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
+	.phys_io = MX51_AIPS1_BASE_ADDR,
+	.io_pg_offst = ((MX51_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+	.boot_params = PHYS_OFFSET + 0x100,
+	.map_io = mx51_map_io,
+	.init_irq = mx51_init_irq,
+	.init_machine = mxc_board_init,
+	.timer = &mxc_timer,
+MACHINE_END
diff --git a/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
new file mode 100644
index 0000000..c2aa016
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-mx51_3ds.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
+#define __ASM_ARCH_MXC_BOARD_MX51_3DS_H__
+
+/*
+ * plat-mxc/include/mach/board-mx51_3ds.h
+ *
+ * This file contains all the board level configuration options.
+ *
+ * It currently hold the options defined for MX51 3Stack Platform.
+ *
+ */
+
+#define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+
+#endif	/* __ASM_ARCH_MXC_BOARD_MX51_3DS_H__ */
-- 
1.5.6.5



From jason77.wang at gmail.com  Fri Jun  4 10:09:27 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:09:27 +0800
Subject: [V3 6/7] mx51/keypad: add keypad support for i.MX51 platforms
In-Reply-To: <1275660568-7738-6-git-send-email-jason77.wang@gmail.com>
References: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-2-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-3-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-4-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-5-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-6-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275660568-7738-7-git-send-email-jason77.wang@gmail.com>

Add keypad controller device definition for all i.MX51 platforms,
add a dummy kpp clock for imx keypad driver and add keypad device
registration on i.MX51 3-stack board.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx5/board-mx51_3ds.c |   61 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mx5/clock-mx51.c     |    5 +++
 arch/arm/mach-mx5/devices.c        |   19 +++++++++++
 arch/arm/mach-mx5/devices.h        |    1 +
 4 files changed, 86 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index af0362c..49f576f 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -12,6 +12,7 @@
 
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/input/matrix_keypad.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -47,6 +48,18 @@ static struct pad_desc mx51_3ds_pads[] = {
 
 	/* CPLD PARENT IRQ PIN */
 	MX51_PAD_GPIO_1_6__GPIO1_6,
+
+	/* KPP */
+	MX51_PAD_KEY_ROW0__KEY_ROW0,
+	MX51_PAD_KEY_ROW1__KEY_ROW1,
+	MX51_PAD_KEY_ROW2__KEY_ROW2,
+	MX51_PAD_KEY_ROW3__KEY_ROW3,
+	MX51_PAD_KEY_COL0__KEY_COL0,
+	MX51_PAD_KEY_COL1__KEY_COL1,
+	MX51_PAD_KEY_COL2__KEY_COL2,
+	MX51_PAD_KEY_COL3__KEY_COL3,
+	MX51_PAD_KEY_COL4__KEY_COL4,
+	MX51_PAD_KEY_COL5__KEY_COL5,
 };
 
 /* Serial ports */
@@ -67,6 +80,52 @@ static inline void mxc_init_imx_uart(void)
 }
 #endif /* SERIAL_IMX */
 
+#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
+static int mx51_3ds_board_keymap[] = {
+	KEY(0, 0, KEY_1),
+	KEY(0, 1, KEY_2),
+	KEY(0, 2, KEY_3),
+	KEY(0, 3, KEY_F1),
+	KEY(0, 4, KEY_UP),
+	KEY(0, 5, KEY_F2),
+
+	KEY(1, 0, KEY_4),
+	KEY(1, 1, KEY_5),
+	KEY(1, 2, KEY_6),
+	KEY(1, 3, KEY_LEFT),
+	KEY(1, 4, KEY_SELECT),
+	KEY(1, 5, KEY_RIGHT),
+
+	KEY(2, 0, KEY_7),
+	KEY(2, 1, KEY_8),
+	KEY(2, 2, KEY_9),
+	KEY(2, 3, KEY_F3),
+	KEY(2, 4, KEY_DOWN),
+	KEY(2, 5, KEY_F4),
+
+	KEY(3, 0, KEY_0),
+	KEY(3, 1, KEY_OK),
+	KEY(3, 2, KEY_ESC),
+	KEY(3, 3, KEY_ENTER),
+	KEY(3, 4, KEY_MENU),
+	KEY(3, 5, KEY_BACK)
+};
+
+static struct matrix_keymap_data mx51_3ds_map_data = {
+	.keymap		= mx51_3ds_board_keymap,
+	.keymap_size	= ARRAY_SIZE(mx51_3ds_board_keymap),
+};
+
+static void mxc_init_keypad(void)
+{
+	mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data);
+}
+#else
+static inline void mxc_init_keypad(void)
+{
+}
+#endif
+
 /*
  * Board specific initialization.
  */
@@ -78,6 +137,8 @@ static void __init mxc_board_init(void)
 
 	if (!mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
 		platform_device_register(&smsc_lan9217_device);
+
+	mxc_init_keypad();
 }
 
 static void __init mx51_3ds_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index d9f612d..60fced6 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
 	.parent = &ckil_clk,
 };
 
+static struct clk kpp_clk = {
+	.id = 0,
+};
+
 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
 	static struct clk name = {			\
 		.id		= i,			\
@@ -821,6 +825,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
+	_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 7130449..2aa4ea0 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -168,6 +168,25 @@ struct platform_device mxc_wdt = {
 	.resource = mxc_wdt_resources,
 };
 
+static struct resource mxc_kpp_resources[] = {
+	{
+		.start = MX51_MXC_INT_KPP,
+		.end = MX51_MXC_INT_KPP,
+		.flags = IORESOURCE_IRQ,
+	} , {
+		.start = MX51_KPP_BASE_ADDR,
+		.end = MX51_KPP_BASE_ADDR + 0x8 - 1,
+		.flags = IORESOURCE_MEM,
+	},
+};
+
+struct platform_device mxc_keypad_device = {
+	.name = "imx-keypad",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(mxc_kpp_resources),
+	.resource = mxc_kpp_resources,
+};
+
 static struct mxc_gpio_port mxc_gpio_ports[] = {
 	{
 		.chip.label = "gpio-0",
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index c879ae7..1fef140 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -6,3 +6,4 @@ extern struct platform_device mxc_usbdr_host_device;
 extern struct platform_device mxc_usbh1_device;
 extern struct platform_device mxc_usbdr_udc_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device mxc_keypad_device;
-- 
1.5.6.5



From jason77.wang at gmail.com  Fri Jun  4 10:09:28 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Fri,  4 Jun 2010 22:09:28 +0800
Subject: [V3 7/7] mx31_3ds: revert cpld debug board relate code
In-Reply-To: <1275660568-7738-7-git-send-email-jason77.wang@gmail.com>
References: <1275660568-7738-1-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-2-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-3-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-4-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-5-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-6-git-send-email-jason77.wang@gmail.com>
	<1275660568-7738-7-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275660568-7738-8-git-send-email-jason77.wang@gmail.com>

Because we add a cpld debug board support in mxc level, we remove
those redudent codes from board level.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx3/Kconfig                       |    1 +
 arch/arm/mach-mx3/mach-mx31_3ds.c               |  168 +----------------------
 arch/arm/plat-mxc/include/mach/board-mx31_3ds.h |   42 ------
 3 files changed, 4 insertions(+), 207 deletions(-)

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753f..fd422cf 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -58,6 +58,7 @@ config MACH_MX31LITE
 config MACH_MX31_3DS
 	bool "Support MX31PDK (3DS)"
 	select ARCH_MX31
+	select MXC_DEBUG_BOARD
 	help
 	  Include support for MX31PDK (3DS) platform. This includes specific
 	  configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 58e5729..d8af726 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -22,7 +22,6 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/smsc911x.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
@@ -38,6 +37,7 @@
 #include <asm/mach/map.h>
 #include <mach/common.h>
 #include <mach/board-mx31_3ds.h>
+#include <mach/cpld_debugboard.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/mxc_nand.h>
@@ -213,173 +213,11 @@ static struct imxuart_platform_data uart_pdata = {
 };
 
 /*
- * Support for the SMSC9217 on the Debug board.
- */
-
-static struct smsc911x_platform_config smsc911x_config = {
-	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
-	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-	.phy_interface	= PHY_INTERFACE_MODE_MII,
-};
-
-static struct resource smsc911x_resources[] = {
-	{
-		.start		= LAN9217_BASE_ADDR,
-		.end		= LAN9217_BASE_ADDR + 0xff,
-		.flags		= IORESOURCE_MEM,
-	}, {
-		.start		= EXPIO_INT_ENET,
-		.end		= EXPIO_INT_ENET,
-		.flags		= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device smsc911x_device = {
-	.name		= "smsc911x",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(smsc911x_resources),
-	.resource	= smsc911x_resources,
-	.dev		= {
-		.platform_data = &smsc911x_config,
-	},
-};
-
-/*
- * Routines for the CPLD on the debug board. It contains a CPLD handling
- * LEDs, switches, interrupts for Ethernet.
- */
-
-static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
-{
-	uint32_t imr_val;
-	uint32_t int_valid;
-	uint32_t expio_irq;
-
-	imr_val = __raw_readw(CPLD_INT_MASK_REG);
-	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
-
-	expio_irq = MXC_EXP_IO_BASE;
-	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
-		if ((int_valid & 1) == 0)
-			continue;
-		generic_handle_irq(expio_irq);
-	}
-}
-
-/*
- * Disable an expio pin's interrupt by setting the bit in the imr.
- * @param irq           an expio virtual irq number
- */
-static void expio_mask_irq(uint32_t irq)
-{
-	uint16_t reg;
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* mask the interrupt */
-	reg = __raw_readw(CPLD_INT_MASK_REG);
-	reg |= 1 << expio;
-	__raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-/*
- * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
- * @param irq           an expanded io virtual irq number
- */
-static void expio_ack_irq(uint32_t irq)
-{
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* clear the interrupt status */
-	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
-	__raw_writew(0, CPLD_INT_RESET_REG);
-	/* mask the interrupt */
-	expio_mask_irq(irq);
-}
-
-/*
- * Enable a expio pin's interrupt by clearing the bit in the imr.
- * @param irq           a expio virtual irq number
- */
-static void expio_unmask_irq(uint32_t irq)
-{
-	uint16_t reg;
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* unmask the interrupt */
-	reg = __raw_readw(CPLD_INT_MASK_REG);
-	reg &= ~(1 << expio);
-	__raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-static struct irq_chip expio_irq_chip = {
-	.ack = expio_ack_irq,
-	.mask = expio_mask_irq,
-	.unmask = expio_unmask_irq,
-};
-
-static int __init mx31_3ds_init_expio(void)
-{
-	int i;
-	int ret;
-
-	/* Check if there's a debug board connected */
-	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
-	    (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
-	    (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
-		/* No Debug board found */
-		return -ENODEV;
-	}
-
-	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
-		__raw_readw(CPLD_CODE_VER_REG));
-
-	/*
-	 * Configure INT line as GPIO input
-	 */
-	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
-	if (ret)
-		pr_warning("could not get LAN irq gpio\n");
-	else
-		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-
-	/* Disable the interrupts and clear the status */
-	__raw_writew(0, CPLD_INT_MASK_REG);
-	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
-	__raw_writew(0, CPLD_INT_RESET_REG);
-	__raw_writew(0x1F, CPLD_INT_MASK_REG);
-	for (i = MXC_EXP_IO_BASE;
-	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
-	     i++) {
-		set_irq_chip(i, &expio_irq_chip);
-		set_irq_handler(i, handle_level_irq);
-		set_irq_flags(i, IRQF_VALID);
-	}
-	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
-	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
-
-	return 0;
-}
-
-/*
- * This structure defines the MX31 memory map.
- */
-static struct map_desc mx31_3ds_io_desc[] __initdata = {
-	{
-		.virtual = MX31_CS5_BASE_ADDR_VIRT,
-		.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
-		.length = MX31_CS5_SIZE,
-		.type = MT_DEVICE,
-	},
-};
-
-/*
  * Set up static virtual mappings.
  */
 static void __init mx31_3ds_map_io(void)
 {
 	mx31_map_io();
-	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
 }
 
 /*!
@@ -402,8 +240,8 @@ static void __init mxc_board_init(void)
 	mx31_3ds_usbotg_init();
 	mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
 
-	if (!mx31_3ds_init_expio())
-		platform_device_register(&smsc911x_device);
+	if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
+		platform_device_register(&smsc_lan9217_device);
 }
 
 static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
index da92933..c26d88d 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
@@ -12,48 +12,6 @@
 #define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
 
 /* Definitions for components on the Debug board */
-
-/* Base address of CPLD controller on the Debug board */
-#define DEBUG_BASE_ADDRESS		CS5_IO_ADDRESS(CS5_BASE_ADDR)
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR		CS5_BASE_ADDR
-
-/* CPLD config and interrupt base address */
-#define CPLD_ADDR			(DEBUG_BASE_ADDRESS + 0x20000)
-
-/* LED switchs */
-#define CPLD_LED_REG			(CPLD_ADDR + 0x00)
-/* buttons */
-#define CPLD_SWITCH_BUTTONS_REG	(EXPIO_ADDR + 0x08)
-/* status, interrupt */
-#define CPLD_INT_STATUS_REG		(CPLD_ADDR + 0x10)
-#define CPLD_INT_MASK_REG		(CPLD_ADDR + 0x38)
-#define CPLD_INT_RESET_REG		(CPLD_ADDR + 0x20)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER1_REG		(CPLD_ADDR + 0x40)
-#define CPLD_MAGIC_NUMBER2_REG		(CPLD_ADDR + 0x48)
-/* CPLD code version */
-#define CPLD_CODE_VER_REG		(CPLD_ADDR + 0x50)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER3_REG		(CPLD_ADDR + 0x58)
-/* module reset register */
-#define CPLD_MODULE_RESET_REG		(CPLD_ADDR + 0x60)
-/* CPU ID and Personality ID */
-#define CPLD_MCU_BOARD_ID_REG		(CPLD_ADDR + 0x68)
-
-/* CPLD IRQ line for external uart, external ethernet etc */
 #define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
 
-#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_ENET		(MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_XUART_A	(MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_XUART_B	(MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_BUTTON_A	(MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_BUTTON_B	(MXC_EXP_IO_BASE + 4)
-
-#define MXC_MAX_EXP_IO_LINES	16
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
-- 
1.5.6.5



From eric.y.miao at gmail.com  Sat Jun  5 03:55:36 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat,  5 Jun 2010 15:55:36 +0800
Subject: [PATCH 2/4] [ARM] pxa: merge all pxa2xx board configs into
	pxa2xx_defconfig
In-Reply-To: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1275724538-5075-3-git-send-email-eric.y.miao@gmail.com>

From: Eric Miao <eric.y.miao at canonical.com>

Signed-off-by: Eric Miao <eric.y.miao at gmail.com>
---
 arch/arm/configs/am200epdkit_defconfig    | 1148 ----------
 arch/arm/configs/cm_x2xx_defconfig        | 1961 -----------------
 arch/arm/configs/colibri_pxa270_defconfig | 1736 ---------------
 arch/arm/configs/em_x270_defconfig        | 1740 ---------------
 arch/arm/configs/eseries_pxa_defconfig    | 1246 -----------
 arch/arm/configs/ezx_defconfig            | 2000 -----------------
 arch/arm/configs/h5000_defconfig          |  995 ---------
 arch/arm/configs/imote2_defconfig         | 2039 -----------------
 arch/arm/configs/lpd270_defconfig         | 1031 ---------
 arch/arm/configs/lubbock_defconfig        |  800 -------
 arch/arm/configs/magician_defconfig       | 1536 -------------
 arch/arm/configs/mainstone_defconfig      |  794 -------
 arch/arm/configs/palmz72_defconfig        |  950 --------
 arch/arm/configs/pcm027_defconfig         | 1095 ---------
 arch/arm/configs/pxa255-idp_defconfig     |  796 -------
 arch/arm/configs/pxa2xx_defconfig         | 3408 +++++++++++++++++++++++++++++
 arch/arm/configs/trizeps4_defconfig       | 1704 --------------
 arch/arm/configs/viper_defconfig          | 1676 --------------
 arch/arm/configs/xcep_defconfig           | 1128 ----------
 arch/arm/configs/zeus_defconfig           | 2031 -----------------
 20 files changed, 3408 insertions(+), 26406 deletions(-)
 delete mode 100644 arch/arm/configs/am200epdkit_defconfig
 delete mode 100644 arch/arm/configs/cm_x2xx_defconfig
 delete mode 100644 arch/arm/configs/colibri_pxa270_defconfig
 delete mode 100644 arch/arm/configs/em_x270_defconfig
 delete mode 100644 arch/arm/configs/eseries_pxa_defconfig
 delete mode 100644 arch/arm/configs/ezx_defconfig
 delete mode 100644 arch/arm/configs/h5000_defconfig
 delete mode 100644 arch/arm/configs/imote2_defconfig
 delete mode 100644 arch/arm/configs/lpd270_defconfig
 delete mode 100644 arch/arm/configs/lubbock_defconfig
 delete mode 100644 arch/arm/configs/magician_defconfig
 delete mode 100644 arch/arm/configs/mainstone_defconfig
 delete mode 100644 arch/arm/configs/palmz72_defconfig
 delete mode 100644 arch/arm/configs/pcm027_defconfig
 delete mode 100644 arch/arm/configs/pxa255-idp_defconfig
 create mode 100644 arch/arm/configs/pxa2xx_defconfig
 delete mode 100644 arch/arm/configs/trizeps4_defconfig
 delete mode 100644 arch/arm/configs/viper_defconfig
 delete mode 100644 arch/arm/configs/xcep_defconfig
 delete mode 100644 arch/arm/configs/zeus_defconfig

diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig
deleted file mode 100644
index 30927ca..0000000
--- a/arch/arm/configs/am200epdkit_defconfig
+++ /dev/null
@@ -1,1148 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.25
-# Sun Apr 20 00:29:49 2008
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
-CONFIG_ZONE_DMA=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION="gum"
-CONFIG_LOCALVERSION_AUTO=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_CGROUPS is not set
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_USER_SCHED=y
-# CONFIG_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-# CONFIG_SYSCTL_SYSCALL is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-# CONFIG_EPOLL is not set
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-# CONFIG_SHMEM is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_TINY_SHMEM=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-# CONFIG_BLK_DEV_BSG is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_DEFAULT_IOSCHED="noop"
-CONFIG_CLASSIC_RCU=y
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_ORION is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM7X00A is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-CONFIG_ARCH_GUMSTIX=y
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_MACH_TRIZEPS4 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_PCM027 is not set
-CONFIG_MACH_GUMSTIX_F=y
-CONFIG_PXA25x=y
-
-#
-# Boot options
-#
-
-#
-# Power management
-#
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-# CONFIG_IWMMXT is not set
-CONFIG_XSCALE_PMU=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_PCCARD=y
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=y
-CONFIG_PCMCIA_LOAD_CIS=y
-# CONFIG_PCMCIA_IOCTL is not set
-
-#
-# PC-card bridges
-#
-CONFIG_PCMCIA_PXA2XX=y
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200n8 root=1f01 rootfstype=jffs2"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=m
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-# CONFIG_BT_BNEP_MC_FILTER is not set
-# CONFIG_BT_BNEP_PROTO_FILTER is not set
-# CONFIG_BT_HIDP is not set
-
-#
-# Bluetooth device drivers
-#
-# CONFIG_BT_HCIBTSDIO is not set
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-# CONFIG_BT_HCIUART_BCSP is not set
-# CONFIG_BT_HCIUART_LL is not set
-# CONFIG_BT_HCIDTL1 is not set
-# CONFIG_BT_HCIBT3C is not set
-# CONFIG_BT_HCIBLUECARD is not set
-# CONFIG_BT_HCIBTUART is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-# CONFIG_CFG80211 is not set
-CONFIG_WIRELESS_EXT=y
-# CONFIG_MAC80211 is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-# CONFIG_IEEE80211_CRYPT_CCMP is not set
-# CONFIG_IEEE80211_CRYPT_TKIP is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-# CONFIG_MTD_CFI_I2 is not set
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_OTP is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_PXA2XX=y
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_SHARP_SL is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-CONFIG_HAVE_IDE=y
-CONFIG_IDE=m
-CONFIG_IDE_MAX_HWIFS=2
-CONFIG_BLK_DEV_IDE=m
-
-#
-# Please see Documentation/ide/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=m
-# CONFIG_IDEDISK_MULTI_MODE is not set
-CONFIG_BLK_DEV_IDECS=m
-# CONFIG_BLK_DEV_IDECD is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_BLK_DEV_PLATFORM is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_BLK_DEV_HD_ONLY is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-# CONFIG_AX88796 is not set
-CONFIG_SMC91X=m
-# CONFIG_DM9000 is not set
-# CONFIG_SMC911X is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_B44 is not set
-CONFIG_NETDEV_1000=y
-# CONFIG_E1000E_ENABLED is not set
-CONFIG_NETDEV_10000=y
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
-# CONFIG_NET_PCMCIA is not set
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_GPIO is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-CONFIG_MOUSE_PS2_ALPS=y
-CONFIG_MOUSE_PS2_LOGIPS2PP=y
-CONFIG_MOUSE_PS2_SYNAPTICS=y
-CONFIG_MOUSE_PS2_LIFEBOOK=y
-CONFIG_MOUSE_PS2_TRACKPOINT=y
-# CONFIG_MOUSE_PS2_TOUCHKIT is not set
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_APPLETOUCH is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_MOUSE_GPIO is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_R3964 is not set
-
-#
-# PCMCIA character devices
-#
-# CONFIG_SYNCLINK_CS is not set
-# CONFIG_CARDMAN_4000 is not set
-# CONFIG_CARDMAN_4040 is not set
-# CONFIG_IPWIRELESS is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-CONFIG_HAVE_GPIO_LIB=y
-
-#
-# GPIO Support
-#
-# CONFIG_DEBUG_GPIO is not set
-
-#
-# I2C GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_SA1100_WATCHDOG=m
-
-#
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-CONFIG_DAB=y
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-CONFIG_FB_SYS_FILLRECT=m
-CONFIG_FB_SYS_COPYAREA=m
-CONFIG_FB_SYS_IMAGEBLIT=m
-CONFIG_FB_SYS_FOPS=m
-CONFIG_FB_DEFERRED_IO=y
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_FB_TILEBLITTING=y
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-CONFIG_FB_PXA_PARAMETERS=y
-CONFIG_FB_MBX=m
-# CONFIG_FB_METRONOME is not set
-CONFIG_FB_VIRTUAL=m
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE is not set
-# CONFIG_LOGO is not set
-
-#
-# Sound
-#
-CONFIG_SOUND=m
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-# CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-# CONFIG_SND_SUPPORT_OLD_API is not set
-# CONFIG_SND_VERBOSE_PROCFS is not set
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
-CONFIG_SND_AC97_CODEC=m
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-
-#
-# ALSA ARM devices
-#
-CONFIG_SND_PXA2XX_PCM=m
-CONFIG_SND_PXA2XX_AC97=m
-
-#
-# PCMCIA devices
-#
-# CONFIG_SND_VXPOCKET is not set
-# CONFIG_SND_PDAUDIOCF is not set
-
-#
-# System on Chip audio support
-#
-# CONFIG_SND_SOC is not set
-
-#
-# SoC Audio support for SuperH
-#
-
-#
-# ALSA SoC audio for Freescale SOCs
-#
-
-#
-# Open Sound System
-#
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=m
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-# CONFIG_HIDRAW is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-CONFIG_USB_GADGET_PXA2XX=y
-CONFIG_USB_PXA2XX=y
-# CONFIG_USB_PXA2XX_SMALL is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-# CONFIG_USB_GADGET_DUALSPEED is not set
-# CONFIG_USB_ZERO is not set
-CONFIG_USB_ETH=y
-CONFIG_USB_ETH_RNDIS=y
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-
-#
-# MMC/SD Host Controller Drivers
-#
-CONFIG_MMC_PXA=y
-# CONFIG_NEW_LEDS is not set
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-
-#
-# File systems
-#
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-# CONFIG_NFS_FS is not set
-# CONFIG_NFSD is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-# CONFIG_DETECT_SOFTLOCKUP is not set
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_SAMPLES is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_BLKCIPHER=m
-# CONFIG_CRYPTO_SEQIV is not set
-CONFIG_CRYPTO_MANAGER=m
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_XTS is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_LZO is not set
-CONFIG_CRYPTO_HW=y
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/cm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig
deleted file mode 100644
index 47d22d0..0000000
--- a/arch/arm/configs/cm_x2xx_defconfig
+++ /dev/null
@@ -1,1961 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc2
-# Sun Feb  1 16:31:36 2009
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_USER_SCHED=y
-# CONFIG_CGROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_PCI_QUIRKS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_W90X900 is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_VIPER is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_EXEDA is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-CONFIG_MACH_ARMCORE=y
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_PXA_EZX is not set
-CONFIG_PXA25x=y
-CONFIG_PXA27x=y
-CONFIG_PXA_SSP=y
-# CONFIG_PXA_PWM is not set
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-CONFIG_DMABOUNCE=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-CONFIG_PCI=y
-CONFIG_PCI_SYSCALL=y
-CONFIG_PCI_HOST_ITE8152=y
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_PCI_LEGACY=y
-# CONFIG_PCI_DEBUG is not set
-# CONFIG_PCI_STUB is not set
-CONFIG_PCCARD=m
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_IOCTL=y
-CONFIG_CARDBUS=y
-
-#
-# PC-card bridges
-#
-CONFIG_YENTA=m
-# CONFIG_YENTA_O2 is not set
-# CONFIG_YENTA_RICOH is not set
-CONFIG_YENTA_TI=y
-# CONFIG_YENTA_ENE_TUNE is not set
-# CONFIG_YENTA_TOSHIBA is not set
-# CONFIG_PD6729 is not set
-# CONFIG_I82092 is not set
-CONFIG_PCMCIA_PXA2XX=m
-CONFIG_PCCARD_NONSTATIC=m
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=1f03 mem=32M"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_FREQ is not set
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_APM_EMULATION=m
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_COMPAT_NET_DEV_OPS=y
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-# CONFIG_BT_RFCOMM_TTY is not set
-CONFIG_BT_BNEP=m
-# CONFIG_BT_BNEP_MC_FILTER is not set
-# CONFIG_BT_BNEP_PROTO_FILTER is not set
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-# CONFIG_BT_HCIBTUSB is not set
-# CONFIG_BT_HCIBTSDIO is not set
-# CONFIG_BT_HCIUART is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIDTL1 is not set
-# CONFIG_BT_HCIBT3C is not set
-# CONFIG_BT_HCIBLUECARD is not set
-# CONFIG_BT_HCIBTUART is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-CONFIG_WIRELESS_OLD_REGULATORY=y
-CONFIG_WIRELESS_EXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
-CONFIG_LIB80211=m
-# CONFIG_MAC80211 is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_OTP is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-CONFIG_MTD_PXA2XX=y
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_IMPA7 is not set
-# CONFIG_MTD_SHARP_SL is not set
-# CONFIG_MTD_INTEL_VR_NOR is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_PMC551 is not set
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND=y
-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_H1900 is not set
-CONFIG_MTD_NAND_GPIO=m
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_SHARPSL is not set
-# CONFIG_MTD_NAND_CAFE is not set
-CONFIG_MTD_NAND_CM_X270=y
-# CONFIG_MTD_NAND_NANDSIM is not set
-CONFIG_MTD_NAND_PLATFORM=y
-# CONFIG_MTD_ALAUDA is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-# CONFIG_MTD_QINFO_PROBE is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_CPQ_DA is not set
-# CONFIG_BLK_CPQ_CISS_DA is not set
-# CONFIG_BLK_DEV_DAC960 is not set
-# CONFIG_BLK_DEV_UMEM is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_SX8 is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
-# CONFIG_SCSI_3W_9XXX is not set
-# CONFIG_SCSI_ACARD is not set
-# CONFIG_SCSI_AACRAID is not set
-# CONFIG_SCSI_AIC7XXX is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_AIC79XX is not set
-# CONFIG_SCSI_AIC94XX is not set
-# CONFIG_SCSI_DPT_I2O is not set
-# CONFIG_SCSI_ADVANSYS is not set
-# CONFIG_SCSI_ARCMSR is not set
-# CONFIG_MEGARAID_NEWGEN is not set
-# CONFIG_MEGARAID_LEGACY is not set
-# CONFIG_MEGARAID_SAS is not set
-# CONFIG_SCSI_HPTIOP is not set
-# CONFIG_LIBFC is not set
-# CONFIG_FCOE is not set
-# CONFIG_SCSI_DMX3191D is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_IPS is not set
-# CONFIG_SCSI_INITIO is not set
-# CONFIG_SCSI_INIA100 is not set
-# CONFIG_SCSI_MVSAS is not set
-# CONFIG_SCSI_STEX is not set
-# CONFIG_SCSI_SYM53C8XX_2 is not set
-# CONFIG_SCSI_IPR is not set
-# CONFIG_SCSI_QLOGIC_1280 is not set
-# CONFIG_SCSI_QLA_FC is not set
-# CONFIG_SCSI_QLA_ISCSI is not set
-# CONFIG_SCSI_LPFC is not set
-# CONFIG_SCSI_DC395x is not set
-# CONFIG_SCSI_DC390T is not set
-# CONFIG_SCSI_NSP32 is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_SRP is not set
-# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
-# CONFIG_SCSI_DH is not set
-CONFIG_ATA=m
-# CONFIG_ATA_NONSTANDARD is not set
-# CONFIG_SATA_PMP is not set
-# CONFIG_SATA_AHCI is not set
-# CONFIG_SATA_SIL24 is not set
-CONFIG_ATA_SFF=y
-# CONFIG_SATA_SVW is not set
-# CONFIG_ATA_PIIX is not set
-# CONFIG_SATA_MV is not set
-# CONFIG_SATA_NV is not set
-# CONFIG_PDC_ADMA is not set
-# CONFIG_SATA_QSTOR is not set
-# CONFIG_SATA_PROMISE is not set
-# CONFIG_SATA_SX4 is not set
-# CONFIG_SATA_SIL is not set
-# CONFIG_SATA_SIS is not set
-# CONFIG_SATA_ULI is not set
-# CONFIG_SATA_VIA is not set
-# CONFIG_SATA_VITESSE is not set
-# CONFIG_SATA_INIC162X is not set
-# CONFIG_PATA_ALI is not set
-# CONFIG_PATA_AMD is not set
-# CONFIG_PATA_ARTOP is not set
-# CONFIG_PATA_ATIIXP is not set
-# CONFIG_PATA_CMD640_PCI is not set
-# CONFIG_PATA_CMD64X is not set
-# CONFIG_PATA_CS5520 is not set
-# CONFIG_PATA_CS5530 is not set
-# CONFIG_PATA_CYPRESS is not set
-# CONFIG_PATA_EFAR is not set
-# CONFIG_ATA_GENERIC is not set
-# CONFIG_PATA_HPT366 is not set
-# CONFIG_PATA_HPT37X is not set
-# CONFIG_PATA_HPT3X2N is not set
-# CONFIG_PATA_HPT3X3 is not set
-# CONFIG_PATA_IT821X is not set
-# CONFIG_PATA_IT8213 is not set
-# CONFIG_PATA_JMICRON is not set
-# CONFIG_PATA_TRIFLEX is not set
-# CONFIG_PATA_MARVELL is not set
-# CONFIG_PATA_MPIIX is not set
-# CONFIG_PATA_OLDPIIX is not set
-# CONFIG_PATA_NETCELL is not set
-# CONFIG_PATA_NINJA32 is not set
-# CONFIG_PATA_NS87410 is not set
-# CONFIG_PATA_NS87415 is not set
-# CONFIG_PATA_OPTI is not set
-# CONFIG_PATA_OPTIDMA is not set
-CONFIG_PATA_PCMCIA=m
-# CONFIG_PATA_PDC_OLD is not set
-# CONFIG_PATA_RADISYS is not set
-# CONFIG_PATA_RZ1000 is not set
-# CONFIG_PATA_SC1200 is not set
-# CONFIG_PATA_SERVERWORKS is not set
-# CONFIG_PATA_PDC2027X is not set
-# CONFIG_PATA_SIL680 is not set
-# CONFIG_PATA_SIS is not set
-# CONFIG_PATA_VIA is not set
-# CONFIG_PATA_WINBOND is not set
-# CONFIG_PATA_PLATFORM is not set
-# CONFIG_PATA_SCH is not set
-# CONFIG_MD is not set
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# Enable only one of the two stacks, unless you know what you are doing
-#
-# CONFIG_FIREWIRE is not set
-# CONFIG_IEEE1394 is not set
-# CONFIG_I2O is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_ARCNET is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_AX88796 is not set
-# CONFIG_HAPPYMEAL is not set
-# CONFIG_SUNGEM is not set
-# CONFIG_CASSINI is not set
-# CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_SMC91X is not set
-CONFIG_DM9000=y
-CONFIG_DM9000_DEBUGLEVEL=1
-# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
-# CONFIG_ENC28J60 is not set
-# CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_NET_TULIP is not set
-# CONFIG_HP100 is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-CONFIG_NET_PCI=y
-# CONFIG_PCNET32 is not set
-# CONFIG_AMD8111_ETH is not set
-# CONFIG_ADAPTEC_STARFIRE is not set
-# CONFIG_B44 is not set
-# CONFIG_FORCEDETH is not set
-# CONFIG_E100 is not set
-# CONFIG_FEALNX is not set
-# CONFIG_NATSEMI is not set
-# CONFIG_NE2K_PCI is not set
-# CONFIG_8139CP is not set
-CONFIG_8139TOO=m
-# CONFIG_8139TOO_PIO is not set
-# CONFIG_8139TOO_TUNE_TWISTER is not set
-# CONFIG_8139TOO_8129 is not set
-# CONFIG_8139_OLD_RX_RESET is not set
-# CONFIG_R6040 is not set
-# CONFIG_SIS900 is not set
-# CONFIG_EPIC100 is not set
-# CONFIG_SMSC9420 is not set
-# CONFIG_SUNDANCE is not set
-# CONFIG_TLAN is not set
-# CONFIG_VIA_RHINE is not set
-# CONFIG_SC92031 is not set
-# CONFIG_ATL2 is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-CONFIG_WLAN_80211=y
-# CONFIG_PCMCIA_RAYCS is not set
-CONFIG_LIBERTAS=m
-# CONFIG_LIBERTAS_USB is not set
-# CONFIG_LIBERTAS_CS is not set
-CONFIG_LIBERTAS_SDIO=m
-# CONFIG_LIBERTAS_DEBUG is not set
-# CONFIG_HERMES is not set
-# CONFIG_ATMEL is not set
-# CONFIG_AIRO_CS is not set
-# CONFIG_PCMCIA_WL3501 is not set
-# CONFIG_PRISM54 is not set
-# CONFIG_USB_ZD1201 is not set
-# CONFIG_USB_NET_RNDIS_WLAN is not set
-# CONFIG_IPW2100 is not set
-# CONFIG_IPW2200 is not set
-# CONFIG_IWLWIFI_LEDS is not set
-# CONFIG_HOSTAP is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_NET_PCMCIA is not set
-# CONFIG_WAN is not set
-# CONFIG_FDDI is not set
-# CONFIG_HIPPI is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_PPP_MPPE is not set
-# CONFIG_PPPOE is not set
-# CONFIG_PPPOL2TP is not set
-# CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_NET_FC is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-# CONFIG_INPUT_APMPOWER is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_PXA27x=m
-# CONFIG_KEYBOARD_GPIO is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-CONFIG_TOUCHSCREEN_UCB1400=m
-# CONFIG_TOUCHSCREEN_WM97XX is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_SERPORT is not set
-# CONFIG_SERIO_PCIPS2 is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-# CONFIG_NOZOMI is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_JSM is not set
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=16
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_R3964 is not set
-# CONFIG_APPLICOM is not set
-
-#
-# PCMCIA character devices
-#
-# CONFIG_SYNCLINK_CS is not set
-# CONFIG_CARDMAN_4000 is not set
-# CONFIG_CARDMAN_4040 is not set
-# CONFIG_IPWIRELESS is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_DEVPORT=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# PC SMBus host controller drivers
-#
-# CONFIG_I2C_ALI1535 is not set
-# CONFIG_I2C_ALI1563 is not set
-# CONFIG_I2C_ALI15X3 is not set
-# CONFIG_I2C_AMD756 is not set
-# CONFIG_I2C_AMD8111 is not set
-# CONFIG_I2C_I801 is not set
-# CONFIG_I2C_ISCH is not set
-# CONFIG_I2C_PIIX4 is not set
-# CONFIG_I2C_NFORCE2 is not set
-# CONFIG_I2C_SIS5595 is not set
-# CONFIG_I2C_SIS630 is not set
-# CONFIG_I2C_SIS96X is not set
-# CONFIG_I2C_VIA is not set
-# CONFIG_I2C_VIAPRO is not set
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Graphics adapter I2C/DDC channel drivers
-#
-# CONFIG_I2C_VOODOO3 is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_AT24 is not set
-# CONFIG_SENSORS_EEPROM is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_BITBANG is not set
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_PXA2XX=m
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_SPI_AT25 is not set
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_TLE62X0 is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-# CONFIG_GPIO_BT8XX is not set
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-CONFIG_UCB1400_CORE=m
-# CONFIG_TPS65010 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-CONFIG_VIDEO_DEV=m
-CONFIG_VIDEO_V4L2_COMMON=m
-# CONFIG_VIDEO_ALLOW_V4L1 is not set
-CONFIG_VIDEO_V4L1_COMPAT=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=m
-
-#
-# Multimedia drivers
-#
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=m
-CONFIG_MEDIA_TUNER_CUSTOMIZE=y
-# CONFIG_MEDIA_TUNER_SIMPLE is not set
-# CONFIG_MEDIA_TUNER_TDA8290 is not set
-# CONFIG_MEDIA_TUNER_TDA827X is not set
-# CONFIG_MEDIA_TUNER_TDA18271 is not set
-# CONFIG_MEDIA_TUNER_TDA9887 is not set
-# CONFIG_MEDIA_TUNER_TEA5761 is not set
-# CONFIG_MEDIA_TUNER_TEA5767 is not set
-# CONFIG_MEDIA_TUNER_MT20XX is not set
-# CONFIG_MEDIA_TUNER_MT2060 is not set
-# CONFIG_MEDIA_TUNER_MT2266 is not set
-# CONFIG_MEDIA_TUNER_MT2131 is not set
-# CONFIG_MEDIA_TUNER_QT1010 is not set
-# CONFIG_MEDIA_TUNER_XC2028 is not set
-# CONFIG_MEDIA_TUNER_XC5000 is not set
-# CONFIG_MEDIA_TUNER_MXL5005S is not set
-# CONFIG_MEDIA_TUNER_MXL5007T is not set
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_DMA_SG=m
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-
-#
-# Encoders/decoders and other helper chips
-#
-
-#
-# Audio decoders
-#
-# CONFIG_VIDEO_TVAUDIO is not set
-# CONFIG_VIDEO_TDA7432 is not set
-# CONFIG_VIDEO_TDA9840 is not set
-# CONFIG_VIDEO_TDA9875 is not set
-# CONFIG_VIDEO_TEA6415C is not set
-# CONFIG_VIDEO_TEA6420 is not set
-# CONFIG_VIDEO_MSP3400 is not set
-# CONFIG_VIDEO_CS5345 is not set
-# CONFIG_VIDEO_CS53L32A is not set
-# CONFIG_VIDEO_M52790 is not set
-# CONFIG_VIDEO_TLV320AIC23B is not set
-# CONFIG_VIDEO_WM8775 is not set
-# CONFIG_VIDEO_WM8739 is not set
-# CONFIG_VIDEO_VP27SMPX is not set
-
-#
-# Video decoders
-#
-# CONFIG_VIDEO_OV7670 is not set
-# CONFIG_VIDEO_TCM825X is not set
-# CONFIG_VIDEO_SAA711X is not set
-# CONFIG_VIDEO_SAA717X is not set
-# CONFIG_VIDEO_TVP514X is not set
-# CONFIG_VIDEO_TVP5150 is not set
-
-#
-# Video and audio decoders
-#
-# CONFIG_VIDEO_CX25840 is not set
-
-#
-# MPEG video encoders
-#
-# CONFIG_VIDEO_CX2341X is not set
-
-#
-# Video encoders
-#
-# CONFIG_VIDEO_SAA7127 is not set
-
-#
-# Video improvement chips
-#
-# CONFIG_VIDEO_UPD64031A is not set
-# CONFIG_VIDEO_UPD64083 is not set
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_BT848 is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-# CONFIG_VIDEO_SAA7134 is not set
-# CONFIG_VIDEO_HEXIUM_ORION is not set
-# CONFIG_VIDEO_HEXIUM_GEMINI is not set
-# CONFIG_VIDEO_CX88 is not set
-# CONFIG_VIDEO_IVTV is not set
-# CONFIG_VIDEO_CAFE_CCIC is not set
-CONFIG_SOC_CAMERA=m
-# CONFIG_SOC_CAMERA_MT9M001 is not set
-CONFIG_SOC_CAMERA_MT9M111=m
-# CONFIG_SOC_CAMERA_MT9T031 is not set
-# CONFIG_SOC_CAMERA_MT9V022 is not set
-# CONFIG_SOC_CAMERA_TW9910 is not set
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
-CONFIG_VIDEO_PXA27x=m
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
-# CONFIG_V4L_USB_DRIVERS is not set
-# CONFIG_RADIO_ADAPTERS is not set
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_DRM is not set
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_CIRRUS is not set
-# CONFIG_FB_PM2 is not set
-# CONFIG_FB_CYBER2000 is not set
-# CONFIG_FB_ASILIANT is not set
-# CONFIG_FB_IMSTT is not set
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_NVIDIA is not set
-# CONFIG_FB_RIVA is not set
-# CONFIG_FB_MATROX is not set
-# CONFIG_FB_RADEON is not set
-# CONFIG_FB_ATY128 is not set
-# CONFIG_FB_ATY is not set
-# CONFIG_FB_S3 is not set
-# CONFIG_FB_SAVAGE is not set
-# CONFIG_FB_SIS is not set
-# CONFIG_FB_VIA is not set
-# CONFIG_FB_NEOMAGIC is not set
-# CONFIG_FB_KYRO is not set
-# CONFIG_FB_3DFX is not set
-# CONFIG_FB_VOODOO1 is not set
-# CONFIG_FB_VT8623 is not set
-# CONFIG_FB_TRIDENT is not set
-# CONFIG_FB_ARK is not set
-# CONFIG_FB_PM3 is not set
-# CONFIG_FB_CARMINE is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_OVERLAY is not set
-# CONFIG_FB_PXA_SMARTPANEL is not set
-CONFIG_FB_PXA_PARAMETERS=y
-CONFIG_FB_MBX=m
-# CONFIG_FB_W100 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-# CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_VMASTER=y
-CONFIG_SND_AC97_CODEC=m
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_PCI is not set
-CONFIG_SND_ARM=y
-CONFIG_SND_PXA2XX_PCM=m
-CONFIG_SND_PXA2XX_LIB=m
-CONFIG_SND_PXA2XX_LIB_AC97=y
-CONFIG_SND_PXA2XX_AC97=m
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-# CONFIG_SND_PCMCIA is not set
-# CONFIG_SND_SOC is not set
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=m
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-CONFIG_HID_DEBUG=y
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_COMPAT=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-# CONFIG_HID_NTRIG is not set
-CONFIG_HID_PANTHERLORD=y
-# CONFIG_PANTHERLORD_FF is not set
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-# CONFIG_GREENASIA_FF is not set
-# CONFIG_HID_TOPSEED is not set
-# CONFIG_THRUSTMASTER_FF is not set
-# CONFIG_ZEROPLUS_FF is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-CONFIG_USB_ARCH_HAS_EHCI=y
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-CONFIG_USB_MON=y
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_EHCI_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-# CONFIG_USB_UHCI_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_WHCI_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-#
-
-#
-# see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-# CONFIG_USB_GADGET is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_UWB is not set
-CONFIG_MMC=m
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_PXA=m
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_TIFM_SD is not set
-# CONFIG_MMC_SPI is not set
-# CONFIG_MMC_SDRICOH_CS is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_PCA9532 is not set
-CONFIG_LEDS_GPIO=m
-# CONFIG_LEDS_PCA955X is not set
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-CONFIG_RTC_DRV_V3020=y
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_SA1100=y
-# CONFIG_RTC_DRV_PXA is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_REGULATOR is not set
-# CONFIG_UIO is not set
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-CONFIG_JFFS2_SUMMARY=y
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-CONFIG_ROOT_NFS=y
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-# CONFIG_CIFS_WEAK_PW_HASH is not set
-# CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=m
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=m
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=m
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=m
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=0
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-
-#
-# Tracers
-#
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-# CONFIG_CRYPTO_MANAGER is not set
-# CONFIG_CRYPTO_MANAGER2 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-# CONFIG_CRYPTO_ECB is not set
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_CRC_CCITT=m
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/colibri_pxa270_defconfig b/arch/arm/configs/colibri_pxa270_defconfig
deleted file mode 100644
index c962870..0000000
--- a/arch/arm/configs/colibri_pxa270_defconfig
+++ /dev/null
@@ -1,1736 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc8
-# Fri Mar 13 16:18:17 2009
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_COMPAT_BRK=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_BLOCK=y
-CONFIG_LBD=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_W90X900 is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_VIPER is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_EM_X270 is not set
-CONFIG_MACH_COLIBRI=y
-# CONFIG_MACH_COLIBRI300 is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_RAUMFELD_PROTO is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_PXA_EZX is not set
-CONFIG_PXA27x=y
-# CONFIG_PXA_PWM is not set
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_FREQ is not set
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_COMPAT_NET_DEV_OPS=y
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-CONFIG_NET_KEY=y
-# CONFIG_NET_KEY_MIGRATE is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETLABEL is not set
-# CONFIG_NETWORK_SECMARK is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-CONFIG_NETFILTER_ADVANCED=y
-
-#
-# Core Netfilter Configuration
-#
-# CONFIG_NETFILTER_NETLINK_QUEUE is not set
-# CONFIG_NETFILTER_NETLINK_LOG is not set
-# CONFIG_NF_CONNTRACK is not set
-# CONFIG_NETFILTER_XTABLES is not set
-# CONFIG_IP_VS is not set
-
-#
-# IP: Netfilter Configuration
-#
-# CONFIG_NF_DEFRAG_IPV4 is not set
-CONFIG_IP_NF_QUEUE=m
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-CONFIG_VLAN_8021Q=m
-# CONFIG_VLAN_8021Q_GVRP is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-CONFIG_IRDA=m
-
-#
-# IrDA protocols
-#
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_ULTRA=y
-
-#
-# IrDA options
-#
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-# CONFIG_IRDA_DEBUG is not set
-
-#
-# Infrared-port device drivers
-#
-
-#
-# SIR device drivers
-#
-CONFIG_IRTTY_SIR=m
-
-#
-# Dongle support
-#
-# CONFIG_DONGLE is not set
-# CONFIG_KINGSUN_DONGLE is not set
-# CONFIG_KSDAZZLE_DONGLE is not set
-# CONFIG_KS959_DONGLE is not set
-
-#
-# FIR device drivers
-#
-# CONFIG_USB_IRDA is not set
-# CONFIG_SIGMATEL_FIR is not set
-# CONFIG_PXA_FICP is not set
-# CONFIG_MCS_FIR is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-# CONFIG_BT_HCIBTUSB is not set
-# CONFIG_BT_HCIBTSDIO is not set
-# CONFIG_BT_HCIUART is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-CONFIG_WIRELESS=y
-CONFIG_CFG80211=y
-# CONFIG_CFG80211_REG_DEBUG is not set
-CONFIG_NL80211=y
-CONFIG_WIRELESS_OLD_REGULATORY=y
-CONFIG_WIRELESS_EXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
-CONFIG_LIB80211=y
-CONFIG_LIB80211_CRYPT_WEP=y
-CONFIG_LIB80211_CRYPT_CCMP=y
-CONFIG_LIB80211_CRYPT_TKIP=y
-# CONFIG_MAC80211 is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_NOSWAP is not set
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_LE_BYTE_SWAP=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_OTP is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-CONFIG_MTD_PXA2XX=y
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_IMPA7 is not set
-# CONFIG_MTD_SHARP_SL is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-CONFIG_MTD_BLOCK2MTD=y
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND=y
-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_H1900 is not set
-# CONFIG_MTD_NAND_GPIO is not set
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_NAND_DISKONCHIP=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
-CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
-# CONFIG_MTD_NAND_SHARPSL is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_ALAUDA is not set
-CONFIG_MTD_ONENAND=y
-# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
-# CONFIG_MTD_ONENAND_GENERIC is not set
-# CONFIG_MTD_ONENAND_OTP is not set
-# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
-# CONFIG_MTD_ONENAND_SIM is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=y
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=8
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_ISL29003 is not set
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_93CX6 is not set
-CONFIG_HAVE_IDE=y
-CONFIG_IDE=y
-
-#
-# Please see Documentation/ide/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_IDE_GD=y
-CONFIG_IDE_GD_ATA=y
-# CONFIG_IDE_GD_ATAPI is not set
-# CONFIG_BLK_DEV_IDECD is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_BLK_DEV_PLATFORM is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_NATIONAL_PHY is not set
-# CONFIG_STE10XP is not set
-# CONFIG_LSI_ET1011C_PHY is not set
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_AX88796 is not set
-# CONFIG_SMC91X is not set
-CONFIG_DM9000=y
-CONFIG_DM9000_DEBUGLEVEL=4
-# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
-# CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-CONFIG_WLAN_80211=y
-# CONFIG_LIBERTAS is not set
-# CONFIG_USB_ZD1201 is not set
-# CONFIG_USB_NET_RNDIS_WLAN is not set
-# CONFIG_IWLWIFI_LEDS is not set
-CONFIG_HOSTAP=y
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=m
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_PXA27x is not set
-# CONFIG_KEYBOARD_GPIO is not set
-CONFIG_INPUT_MOUSE=y
-# CONFIG_MOUSE_PS2 is not set
-CONFIG_MOUSE_SERIAL=m
-# CONFIG_MOUSE_APPLETOUCH is not set
-# CONFIG_MOUSE_BCM5974 is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_MOUSE_GPIO is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-CONFIG_INPUT_UINPUT=m
-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=y
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PXA is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-# CONFIG_SPI is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7462 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7473 is not set
-# CONFIG_SENSORS_ADT7475 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_LTC4245 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-# CONFIG_SA1100_WATCHDOG is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-CONFIG_DAB=y
-# CONFIG_USB_DABUSB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_UVESA is not set
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_OVERLAY is not set
-# CONFIG_FB_PXA_SMARTPANEL is not set
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_W100 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-# CONFIG_LCD_ILI9320 is not set
-# CONFIG_LCD_PLATFORM is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GENERIC=y
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_SOUND is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-# CONFIG_HID_PID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_COMPAT=y
-# CONFIG_HID_APPLE is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_OHCI_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-#
-
-#
-# see USB_STORAGE Help for more information
-#
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=m
-# CONFIG_USB_EZUSB is not set
-# CONFIG_USB_SERIAL_GENERIC is not set
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_CP2101 is not set
-# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_FUNSOFT is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_IPAQ is not set
-# CONFIG_USB_SERIAL_IR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-# CONFIG_USB_SERIAL_GARMIN is not set
-# CONFIG_USB_SERIAL_IPW is not set
-# CONFIG_USB_SERIAL_IUU is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KLSI is not set
-# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MOTOROLA is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_HP4X is not set
-# CONFIG_USB_SERIAL_SAFE is not set
-# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-# CONFIG_USB_SERIAL_TI is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
-# CONFIG_USB_SERIAL_OPTION is not set
-# CONFIG_USB_SERIAL_OMNINET is not set
-# CONFIG_USB_SERIAL_OPTICON is not set
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_PXA25X is not set
-# CONFIG_USB_GADGET_PXA27X is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_IMX is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_FSL_QE is not set
-# CONFIG_USB_GADGET_CI13XXX is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_GOKU is not set
-CONFIG_USB_GADGET_DUMMY_HCD=y
-CONFIG_USB_DUMMY_HCD=m
-CONFIG_USB_GADGET_DUALSPEED=y
-# CONFIG_USB_ZERO is not set
-# CONFIG_USB_ETH is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_USB_GPIO_VBUS is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-# CONFIG_MMC_PXA is not set
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_NEW_LEDS=y
-# CONFIG_LEDS_CLASS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-CONFIG_RTC_DRV_PCF8583=m
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-
-#
-# SPI RTC drivers
-#
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_RTC_DRV_SA1100 is not set
-# CONFIG_RTC_DRV_PXA is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_REGULATOR is not set
-# CONFIG_UIO is not set
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FILE_LOCKING=y
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-CONFIG_AUTOFS4_FS=y
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_CONFIGFS_FS=y
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=1
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=y
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-CONFIG_NFSD_V4=y
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-CONFIG_SUNRPC_GSS=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
-CONFIG_RPCSEC_GSS_KRB5=y
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-15"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-CONFIG_NLS_CODEPAGE_850=y
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=m
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=m
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
-CONFIG_DEBUG_PREEMPT=y
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-
-#
-# Tracers
-#
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-CONFIG_SECURITY=y
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_NETWORK is not set
-# CONFIG_SECURITY_PATH is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_SECURITY_ROOTPLUG is not set
-CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=y
-# CONFIG_CRYPTO_LRW is not set
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=y
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=m
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-CONFIG_LIBCRC32C=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC16=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig
deleted file mode 100644
index 2bee932..0000000
--- a/arch/arm/configs/em_x270_defconfig
+++ /dev/null
@@ -1,1740 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc2
-# Sun Feb  1 16:43:31 2009
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_USER_SCHED=y
-# CONFIG_CGROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_W90X900 is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_VIPER is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_H5000 is not set
-CONFIG_MACH_EM_X270=y
-CONFIG_MACH_EXEDA=y
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_PXA_EZX is not set
-CONFIG_PXA27x=y
-CONFIG_PXA_SSP=y
-# CONFIG_PXA_PWM is not set
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=1f03 mem=32M"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-# CONFIG_CPU_FREQ_DEBUG is not set
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-CONFIG_CPU_FREQ_GOV_USERSPACE=m
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_APM_EMULATION=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_COMPAT_NET_DEV_OPS=y
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-# CONFIG_BT_RFCOMM_TTY is not set
-CONFIG_BT_BNEP=m
-# CONFIG_BT_BNEP_MC_FILTER is not set
-# CONFIG_BT_BNEP_PROTO_FILTER is not set
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIBTUSB=m
-# CONFIG_BT_HCIBTSDIO is not set
-# CONFIG_BT_HCIUART is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-CONFIG_WIRELESS_OLD_REGULATORY=y
-CONFIG_WIRELESS_EXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
-CONFIG_LIB80211=m
-# CONFIG_MAC80211 is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_GEOMETRY is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_OTP is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-CONFIG_MTD_PXA2XX=y
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_IMPA7 is not set
-# CONFIG_MTD_SHARP_SL is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND=y
-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_H1900 is not set
-# CONFIG_MTD_NAND_GPIO is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_SHARPSL is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-CONFIG_MTD_NAND_PLATFORM=y
-# CONFIG_MTD_ALAUDA is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-# CONFIG_MTD_QINFO_PROBE is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_AX88796 is not set
-# CONFIG_SMC91X is not set
-CONFIG_DM9000=y
-CONFIG_DM9000_DEBUGLEVEL=1
-# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
-# CONFIG_ENC28J60 is not set
-# CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-CONFIG_WLAN_80211=y
-CONFIG_LIBERTAS=m
-# CONFIG_LIBERTAS_USB is not set
-CONFIG_LIBERTAS_SDIO=m
-# CONFIG_LIBERTAS_DEBUG is not set
-# CONFIG_USB_ZD1201 is not set
-# CONFIG_USB_NET_RNDIS_WLAN is not set
-# CONFIG_IWLWIFI_LEDS is not set
-# CONFIG_HOSTAP is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_PPP_MPPE is not set
-# CONFIG_PPPOE is not set
-# CONFIG_PPPOL2TP is not set
-# CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-CONFIG_INPUT_APMPOWER=y
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_PXA27x=y
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_DA9034 is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-CONFIG_TOUCHSCREEN_WM97XX=m
-# CONFIG_TOUCHSCREEN_WM9705 is not set
-CONFIG_TOUCHSCREEN_WM9712=y
-# CONFIG_TOUCHSCREEN_WM9713 is not set
-# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=16
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_BITBANG is not set
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_PXA2XX=y
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_SPI_AT25 is not set
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_TLE62X0 is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_APM_POWER is not set
-# CONFIG_BATTERY_DS2760 is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-CONFIG_BATTERY_DA9030=y
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_UCB1400_CORE is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-CONFIG_PMIC_DA903X=y
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-CONFIG_VIDEO_DEV=m
-CONFIG_VIDEO_V4L2_COMMON=m
-# CONFIG_VIDEO_ALLOW_V4L1 is not set
-CONFIG_VIDEO_V4L1_COMPAT=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=m
-
-#
-# Multimedia drivers
-#
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=m
-CONFIG_MEDIA_TUNER_CUSTOMIZE=y
-# CONFIG_MEDIA_TUNER_SIMPLE is not set
-# CONFIG_MEDIA_TUNER_TDA8290 is not set
-# CONFIG_MEDIA_TUNER_TDA827X is not set
-# CONFIG_MEDIA_TUNER_TDA18271 is not set
-# CONFIG_MEDIA_TUNER_TDA9887 is not set
-# CONFIG_MEDIA_TUNER_TEA5761 is not set
-# CONFIG_MEDIA_TUNER_TEA5767 is not set
-# CONFIG_MEDIA_TUNER_MT20XX is not set
-# CONFIG_MEDIA_TUNER_MT2060 is not set
-# CONFIG_MEDIA_TUNER_MT2266 is not set
-# CONFIG_MEDIA_TUNER_MT2131 is not set
-# CONFIG_MEDIA_TUNER_QT1010 is not set
-# CONFIG_MEDIA_TUNER_XC2028 is not set
-# CONFIG_MEDIA_TUNER_XC5000 is not set
-# CONFIG_MEDIA_TUNER_MXL5005S is not set
-# CONFIG_MEDIA_TUNER_MXL5007T is not set
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEOBUF_GEN=m
-CONFIG_VIDEOBUF_DMA_SG=m
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-
-#
-# Encoders/decoders and other helper chips
-#
-
-#
-# Audio decoders
-#
-# CONFIG_VIDEO_TVAUDIO is not set
-# CONFIG_VIDEO_TDA7432 is not set
-# CONFIG_VIDEO_TDA9840 is not set
-# CONFIG_VIDEO_TDA9875 is not set
-# CONFIG_VIDEO_TEA6415C is not set
-# CONFIG_VIDEO_TEA6420 is not set
-# CONFIG_VIDEO_MSP3400 is not set
-# CONFIG_VIDEO_CS5345 is not set
-# CONFIG_VIDEO_CS53L32A is not set
-# CONFIG_VIDEO_M52790 is not set
-# CONFIG_VIDEO_TLV320AIC23B is not set
-# CONFIG_VIDEO_WM8775 is not set
-# CONFIG_VIDEO_WM8739 is not set
-# CONFIG_VIDEO_VP27SMPX is not set
-
-#
-# Video decoders
-#
-# CONFIG_VIDEO_OV7670 is not set
-# CONFIG_VIDEO_TCM825X is not set
-# CONFIG_VIDEO_SAA711X is not set
-# CONFIG_VIDEO_SAA717X is not set
-# CONFIG_VIDEO_TVP514X is not set
-# CONFIG_VIDEO_TVP5150 is not set
-
-#
-# Video and audio decoders
-#
-# CONFIG_VIDEO_CX25840 is not set
-
-#
-# MPEG video encoders
-#
-# CONFIG_VIDEO_CX2341X is not set
-
-#
-# Video encoders
-#
-# CONFIG_VIDEO_SAA7127 is not set
-
-#
-# Video improvement chips
-#
-# CONFIG_VIDEO_UPD64031A is not set
-# CONFIG_VIDEO_UPD64083 is not set
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-CONFIG_SOC_CAMERA=m
-# CONFIG_SOC_CAMERA_MT9M001 is not set
-CONFIG_SOC_CAMERA_MT9M111=m
-# CONFIG_SOC_CAMERA_MT9T031 is not set
-# CONFIG_SOC_CAMERA_MT9V022 is not set
-# CONFIG_SOC_CAMERA_TW9910 is not set
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
-CONFIG_VIDEO_PXA27x=m
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
-# CONFIG_V4L_USB_DRIVERS is not set
-# CONFIG_RADIO_ADAPTERS is not set
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_OVERLAY is not set
-# CONFIG_FB_PXA_SMARTPANEL is not set
-CONFIG_FB_PXA_PARAMETERS=y
-CONFIG_FB_MBX=m
-# CONFIG_FB_MBX_DEBUG is not set
-# CONFIG_FB_W100 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-# CONFIG_LCD_LTV350QV is not set
-# CONFIG_LCD_ILI9320 is not set
-CONFIG_LCD_TDO24M=y
-# CONFIG_LCD_VGG2432A4 is not set
-# CONFIG_LCD_PLATFORM is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=m
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_DA903X=m
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-# CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_VMASTER=y
-CONFIG_SND_AC97_CODEC=m
-# CONFIG_SND_DRIVERS is not set
-CONFIG_SND_ARM=y
-CONFIG_SND_PXA2XX_LIB=m
-CONFIG_SND_PXA2XX_LIB_AC97=y
-# CONFIG_SND_PXA2XX_AC97 is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=m
-CONFIG_SND_SOC_AC97_BUS=y
-CONFIG_SND_PXA2XX_SOC=m
-CONFIG_SND_PXA2XX_SOC_AC97=m
-CONFIG_SND_PXA2XX_SOC_EM_X270=m
-CONFIG_SND_SOC_I2C_AND_SPI=m
-# CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_WM9712=m
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=m
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-CONFIG_HID_DEBUG=y
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_COMPAT=y
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_EZKEY=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_LOGITECH=y
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-# CONFIG_HID_NTRIG is not set
-CONFIG_HID_PANTHERLORD=y
-# CONFIG_PANTHERLORD_FF is not set
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-# CONFIG_GREENASIA_FF is not set
-# CONFIG_HID_TOPSEED is not set
-# CONFIG_THRUSTMASTER_FF is not set
-# CONFIG_ZEROPLUS_FF is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-CONFIG_USB_MON=y
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-#
-
-#
-# see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-# CONFIG_USB_GADGET is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_USB_GPIO_VBUS is not set
-CONFIG_MMC=m
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_PXA=m
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_SPI is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_PCA9532 is not set
-# CONFIG_LEDS_GPIO is not set
-# CONFIG_LEDS_PCA955X is not set
-CONFIG_LEDS_DA903X=y
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-CONFIG_RTC_DRV_V3020=y
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_SA1100=y
-# CONFIG_RTC_DRV_PXA is not set
-# CONFIG_DMADEVICES is not set
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-CONFIG_REGULATOR_DA903X=y
-# CONFIG_UIO is not set
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-CONFIG_JFFS2_SUMMARY=y
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-CONFIG_ROOT_NFS=y
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-# CONFIG_CIFS_WEAK_PW_HASH is not set
-# CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=m
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=m
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=m
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=m
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=0
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-
-#
-# Tracers
-#
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_ALGAPI2=m
-CONFIG_CRYPTO_AEAD2=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_BLKCIPHER2=m
-CONFIG_CRYPTO_HASH=m
-CONFIG_CRYPTO_HASH2=m
-CONFIG_CRYPTO_RNG2=m
-CONFIG_CRYPTO_MANAGER=m
-CONFIG_CRYPTO_MANAGER2=m
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-CONFIG_CRYPTO_MICHAEL_MIC=m
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=m
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_CRC_CCITT=m
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig
deleted file mode 100644
index 74baf57..0000000
--- a/arch/arm/configs/eseries_pxa_defconfig
+++ /dev/null
@@ -1,1246 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.28-rc8
-# Wed Dec 24 23:35:45 2008
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-# CONFIG_KALLSYMS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
-CONFIG_HAVE_OPROFILE=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_W90X900 is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_VIPER is not set
-CONFIG_ARCH_PXA_ESERIES=y
-CONFIG_MACH_E330=y
-CONFIG_MACH_E350=y
-CONFIG_MACH_E740=y
-CONFIG_MACH_E750=y
-CONFIG_MACH_E400=y
-CONFIG_MACH_E800=y
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_PXA_EZX is not set
-CONFIG_PXA25x=y
-# CONFIG_PXA_PWM is not set
-CONFIG_PXA_HAVE_BOARD_IRQS=y
-
-#
-# Boot options
-#
-
-#
-# Power management
-#
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-# CONFIG_ARM_THUMB is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_PCCARD=y
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_IOCTL=y
-
-#
-# PC-card bridges
-#
-CONFIG_PCMCIA_PXA2XX=m
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-CONFIG_KEXEC=y
-CONFIG_ATAGS_PROC=y
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_FREQ is not set
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-CONFIG_BINFMT_MISC=y
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_PACKET is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-CONFIG_IRDA=y
-
-#
-# IrDA protocols
-#
-CONFIG_IRLAN=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_ULTRA=y
-
-#
-# IrDA options
-#
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-# CONFIG_IRDA_DEBUG is not set
-
-#
-# Infrared-port device drivers
-#
-
-#
-# SIR device drivers
-#
-# CONFIG_IRTTY_SIR is not set
-
-#
-# Dongle support
-#
-
-#
-# FIR device drivers
-#
-CONFIG_PXA_FICP=y
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-CONFIG_WIRELESS=y
-CONFIG_CFG80211=m
-CONFIG_NL80211=y
-CONFIG_WIRELESS_OLD_REGULATORY=y
-CONFIG_WIRELESS_EXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
-CONFIG_MAC80211=m
-
-#
-# Rate control algorithm selection
-#
-CONFIG_MAC80211_RC_PID=y
-# CONFIG_MAC80211_RC_MINSTREL is not set
-CONFIG_MAC80211_RC_DEFAULT_PID=y
-# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
-CONFIG_MAC80211_RC_DEFAULT="pid"
-# CONFIG_MAC80211_MESH is not set
-# CONFIG_MAC80211_LEDS is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_CRYPT_TKIP=m
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_STANDALONE is not set
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=m
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-# CONFIG_MTD_PARTITIONS is not set
-
-#
-# User Modules And Translation Layers
-#
-# CONFIG_MTD_CHAR is not set
-# CONFIG_MTD_BLKDEVS is not set
-# CONFIG_MTD_BLOCK is not set
-# CONFIG_MTD_BLOCK_RO is not set
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_SHARP_SL is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND=m
-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_GPIO is not set
-CONFIG_MTD_NAND_IDS=m
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_SHARPSL is not set
-CONFIG_MTD_NAND_TMIO=m
-# CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_C2PORT is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=m
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_PROC_FS is not set
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=m
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
-# CONFIG_SCSI_DH is not set
-CONFIG_ATA=m
-# CONFIG_ATA_NONSTANDARD is not set
-# CONFIG_SATA_PMP is not set
-CONFIG_ATA_SFF=y
-# CONFIG_SATA_MV is not set
-CONFIG_PATA_PCMCIA=m
-# CONFIG_PATA_PLATFORM is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_NET_ETHERNET is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-CONFIG_WLAN_80211=y
-# CONFIG_PCMCIA_RAYCS is not set
-# CONFIG_LIBERTAS is not set
-# CONFIG_LIBERTAS_THINFIRM is not set
-CONFIG_HERMES=m
-CONFIG_PCMCIA_HERMES=m
-# CONFIG_PCMCIA_SPECTRUM is not set
-# CONFIG_ATMEL is not set
-# CONFIG_AIRO_CS is not set
-# CONFIG_PCMCIA_WL3501 is not set
-# CONFIG_MAC80211_HWSIM is not set
-# CONFIG_P54_COMMON is not set
-# CONFIG_IWLWIFI_LEDS is not set
-# CONFIG_HOSTAP is not set
-# CONFIG_B43 is not set
-# CONFIG_B43LEGACY is not set
-# CONFIG_RT2X00 is not set
-CONFIG_NET_PCMCIA=y
-# CONFIG_PCMCIA_3C589 is not set
-# CONFIG_PCMCIA_3C574 is not set
-# CONFIG_PCMCIA_FMVJ18X is not set
-# CONFIG_PCMCIA_PCNET is not set
-# CONFIG_PCMCIA_NMCLAN is not set
-# CONFIG_PCMCIA_SMC91C92 is not set
-# CONFIG_PCMCIA_XIRC2PS is not set
-# CONFIG_PCMCIA_AXNET is not set
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_GPIO=m
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-CONFIG_TOUCHSCREEN_WM97XX=m
-CONFIG_TOUCHSCREEN_WM9705=y
-CONFIG_TOUCHSCREEN_WM9712=y
-CONFIG_TOUCHSCREEN_WM9713=y
-# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-# CONFIG_SERIAL_PXA_CONSOLE is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_R3964 is not set
-
-#
-# PCMCIA character devices
-#
-# CONFIG_SYNCLINK_CS is not set
-# CONFIG_CARDMAN_4000 is not set
-# CONFIG_CARDMAN_4040 is not set
-# CONFIG_IPWIRELESS is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
-# CONFIG_SPI is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-CONFIG_MFD_CORE=y
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_UCB1400_CORE is not set
-CONFIG_MFD_TMIO=y
-CONFIG_MFD_T7L66XB=y
-CONFIG_MFD_TC6387XB=y
-CONFIG_MFD_TC6393XB=y
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_SMARTPANEL is not set
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_MBX is not set
-CONFIG_FB_W100=y
-# CONFIG_FB_TMIO is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-# CONFIG_LCD_ILI9320 is not set
-# CONFIG_LCD_PLATFORM is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CORGI=y
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FONTS=y
-# CONFIG_FONT_8x8 is not set
-# CONFIG_FONT_8x16 is not set
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-CONFIG_FONT_MINI_4x6=y
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_LOGO is not set
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-# CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-CONFIG_SND_DYNAMIC_MINORS=y
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_VERBOSE_PRINTK=y
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_VMASTER=y
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-# CONFIG_SND_AC97_POWER_SAVE is not set
-CONFIG_SND_ARM=y
-CONFIG_SND_PXA2XX_LIB=m
-CONFIG_SND_PXA2XX_LIB_AC97=y
-# CONFIG_SND_PXA2XX_AC97 is not set
-# CONFIG_SND_PCMCIA is not set
-CONFIG_SND_SOC=m
-CONFIG_SND_SOC_AC97_BUS=y
-CONFIG_SND_PXA2XX_SOC=m
-CONFIG_SND_PXA2XX_SOC_AC97=m
-CONFIG_SND_PXA2XX_SOC_E800=m
-CONFIG_SND_SOC_WM9712=m
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=m
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-# CONFIG_HIDRAW is not set
-# CONFIG_HID_PID is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_COMPAT=y
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_UNSAFE_RESUME=y
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-# CONFIG_MMC_PXA is not set
-# CONFIG_MMC_SDHCI is not set
-CONFIG_MMC_TMIO=y
-# CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
-# CONFIG_NEW_LEDS is not set
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_REGULATOR is not set
-# CONFIG_UIO is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=m
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=m
-CONFIG_FS_MBCACHE=m
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_FRAME_WARN=1024
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_LATENCYTOP is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_HAVE_FUNCTION_TRACER=y
-
-#
-# Tracers
-#
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_DEBUG_USER is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_ALGAPI2=m
-CONFIG_CRYPTO_AEAD2=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_BLKCIPHER2=m
-CONFIG_CRYPTO_HASH2=m
-CONFIG_CRYPTO_RNG2=m
-CONFIG_CRYPTO_MANAGER=m
-CONFIG_CRYPTO_MANAGER2=m
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=m
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_LRW is not set
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-CONFIG_CRYPTO_MICHAEL_MIC=m
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=m
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=y
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig
deleted file mode 100644
index 9e9057c..0000000
--- a/arch/arm/configs/ezx_defconfig
+++ /dev/null
@@ -1,2000 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32-rc5
-# Mon Nov  2 13:18:50 2009
-#
-CONFIG_ARM=y
-CONFIG_HAVE_PWM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION="-ezx200910312315"
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_USER_SCHED=y
-# CONFIG_CGROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_SLOW_WORK=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
-CONFIG_IOSCHED_DEADLINE=y
-# CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
-CONFIG_DEFAULT_DEADLINE=y
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="deadline"
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_MACH_STARGATE2 is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_MACH_BALLOON3 is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_VIPER is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_EXEDA is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_COLIBRI300 is not set
-# CONFIG_MACH_COLIBRI320 is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_H4700 is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_HIMALAYA is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_MACH_CSB726 is not set
-CONFIG_PXA_EZX=y
-CONFIG_MACH_EZX_A780=y
-CONFIG_MACH_EZX_E680=y
-CONFIG_MACH_EZX_A1200=y
-CONFIG_MACH_EZX_A910=y
-CONFIG_MACH_EZX_E6=y
-CONFIG_MACH_EZX_E2=y
-# CONFIG_MACH_XCEP is not set
-CONFIG_PXA27x=y
-CONFIG_PXA_SSP=y
-CONFIG_PXA_HAVE_BOARD_IRQS=y
-CONFIG_PLAT_PXA=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=3 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug"
-# CONFIG_XIP_KERNEL is not set
-CONFIG_KEXEC=y
-CONFIG_ATAGS_PROC=y
-
-#
-# CPU Power Management
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-CONFIG_CPU_FREQ_DEBUG=y
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
-CONFIG_CPU_FREQ_GOV_USERSPACE=m
-CONFIG_CPU_FREQ_GOV_ONDEMAND=m
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_APM_EMULATION=y
-CONFIG_PM_RUNTIME=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-CONFIG_XFRM_IPCOMP=m
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-CONFIG_INET_TUNNEL=m
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-CONFIG_IPV6=m
-# CONFIG_IPV6_PRIVACY is not set
-# CONFIG_IPV6_ROUTER_PREF is not set
-# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-CONFIG_INET6_XFRM_MODE_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_BEET=m
-# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-# CONFIG_IPV6_MROUTE is not set
-# CONFIG_NETWORK_SECMARK is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_BRIDGE_NETFILTER=y
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CT_ACCT=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-# CONFIG_NF_CT_PROTO_DCCP is not set
-CONFIG_NF_CT_PROTO_GRE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CT_PROTO_UDPLITE=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-# CONFIG_NETFILTER_TPROXY is not set
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
-# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
-CONFIG_NETFILTER_XT_TARGET_HL=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
-# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
-# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
-# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_HL=m
-# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-# CONFIG_NETFILTER_XT_MATCH_OSF is not set
-# CONFIG_IP_VS is not set
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV4=m
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
-CONFIG_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_NF_NAT_PROTO_GRE=m
-CONFIG_NF_NAT_PROTO_UDPLITE=m
-CONFIG_NF_NAT_PROTO_SCTP=m
-CONFIG_NF_NAT_FTP=m
-CONFIG_NF_NAT_IRC=m
-CONFIG_NF_NAT_TFTP=m
-CONFIG_NF_NAT_AMANDA=m
-CONFIG_NF_NAT_PPTP=m
-CONFIG_NF_NAT_H323=m
-CONFIG_NF_NAT_SIP=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-# CONFIG_BRIDGE_NF_EBTABLES is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-CONFIG_STP=m
-CONFIG_BRIDGE=m
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-CONFIG_LLC=m
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-# CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=y
-CONFIG_BT_L2CAP=y
-CONFIG_BT_SCO=y
-CONFIG_BT_RFCOMM=y
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=y
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=y
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIBTUSB=m
-CONFIG_BT_HCIBTSDIO=m
-CONFIG_BT_HCIUART=y
-CONFIG_BT_HCIUART_H4=y
-# CONFIG_BT_HCIUART_BCSP is not set
-# CONFIG_BT_HCIUART_LL is not set
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIVHCI=m
-CONFIG_BT_MRVL=m
-CONFIG_BT_MRVL_SDIO=m
-# CONFIG_AF_RXRPC is not set
-CONFIG_FIB_RULES=y
-# CONFIG_WIRELESS is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_DEVTMPFS is not set
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-CONFIG_CONNECTOR=m
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_HAVE_MTD_OTP=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-# CONFIG_MTD_CFI_I2 is not set
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_OTP=y
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_PXA2XX=y
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
-# CONFIG_MTD_SST25L is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_NET_ETHERNET is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_PPP_MPPE is not set
-# CONFIG_PPPOE is not set
-# CONFIG_PPPOL2TP is not set
-# CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-# CONFIG_INPUT_APMPOWER is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_LM8323 is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-CONFIG_KEYBOARD_PXA27x=y
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
-# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-CONFIG_TOUCHSCREEN_PCAP=y
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-CONFIG_INPUT_UINPUT=y
-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-CONFIG_INPUT_PCAP=y
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_MAX3100 is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=8
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_DESIGNWARE is not set
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_BITBANG is not set
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_PXA2XX=y
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_TLE62X0 is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_GPIO_MC33880 is not set
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_APM_POWER is not set
-# CONFIG_BATTERY_DS2760 is not set
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_MFD_MC13783 is not set
-# CONFIG_AB3100_CORE is not set
-CONFIG_EZX_PCAP=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DEBUG=y
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
-CONFIG_REGULATOR_USERSPACE_CONSUMER=y
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_REGULATOR_LP3971 is not set
-CONFIG_REGULATOR_PCAP=y
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-CONFIG_MEDIA_SUPPORT=y
-
-#
-# Multimedia core support
-#
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-CONFIG_VIDEO_ALLOW_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=y
-
-#
-# Multimedia drivers
-#
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=y
-CONFIG_MEDIA_TUNER_CUSTOMISE=y
-# CONFIG_MEDIA_TUNER_SIMPLE is not set
-# CONFIG_MEDIA_TUNER_TDA8290 is not set
-# CONFIG_MEDIA_TUNER_TDA827X is not set
-# CONFIG_MEDIA_TUNER_TDA18271 is not set
-# CONFIG_MEDIA_TUNER_TDA9887 is not set
-# CONFIG_MEDIA_TUNER_TEA5761 is not set
-# CONFIG_MEDIA_TUNER_TEA5767 is not set
-# CONFIG_MEDIA_TUNER_MT20XX is not set
-# CONFIG_MEDIA_TUNER_MT2060 is not set
-# CONFIG_MEDIA_TUNER_MT2266 is not set
-# CONFIG_MEDIA_TUNER_MT2131 is not set
-# CONFIG_MEDIA_TUNER_QT1010 is not set
-# CONFIG_MEDIA_TUNER_XC2028 is not set
-# CONFIG_MEDIA_TUNER_XC5000 is not set
-# CONFIG_MEDIA_TUNER_MXL5005S is not set
-# CONFIG_MEDIA_TUNER_MXL5007T is not set
-# CONFIG_MEDIA_TUNER_MC44S803 is not set
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF_DMA_SG=y
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-
-#
-# Encoders/decoders and other helper chips
-#
-
-#
-# Audio decoders
-#
-# CONFIG_VIDEO_TVAUDIO is not set
-# CONFIG_VIDEO_TDA7432 is not set
-# CONFIG_VIDEO_TDA9840 is not set
-# CONFIG_VIDEO_TDA9875 is not set
-# CONFIG_VIDEO_TEA6415C is not set
-# CONFIG_VIDEO_TEA6420 is not set
-# CONFIG_VIDEO_MSP3400 is not set
-# CONFIG_VIDEO_CS5345 is not set
-# CONFIG_VIDEO_CS53L32A is not set
-# CONFIG_VIDEO_M52790 is not set
-# CONFIG_VIDEO_TLV320AIC23B is not set
-# CONFIG_VIDEO_WM8775 is not set
-# CONFIG_VIDEO_WM8739 is not set
-# CONFIG_VIDEO_VP27SMPX is not set
-
-#
-# RDS decoders
-#
-# CONFIG_VIDEO_SAA6588 is not set
-
-#
-# Video decoders
-#
-# CONFIG_VIDEO_ADV7180 is not set
-# CONFIG_VIDEO_BT819 is not set
-# CONFIG_VIDEO_BT856 is not set
-# CONFIG_VIDEO_BT866 is not set
-# CONFIG_VIDEO_KS0127 is not set
-# CONFIG_VIDEO_OV7670 is not set
-# CONFIG_VIDEO_MT9V011 is not set
-# CONFIG_VIDEO_TCM825X is not set
-# CONFIG_VIDEO_SAA7110 is not set
-# CONFIG_VIDEO_SAA711X is not set
-# CONFIG_VIDEO_SAA717X is not set
-# CONFIG_VIDEO_SAA7191 is not set
-# CONFIG_VIDEO_TVP514X is not set
-# CONFIG_VIDEO_TVP5150 is not set
-# CONFIG_VIDEO_VPX3220 is not set
-
-#
-# Video and audio decoders
-#
-# CONFIG_VIDEO_CX25840 is not set
-
-#
-# MPEG video encoders
-#
-# CONFIG_VIDEO_CX2341X is not set
-
-#
-# Video encoders
-#
-# CONFIG_VIDEO_SAA7127 is not set
-# CONFIG_VIDEO_SAA7185 is not set
-# CONFIG_VIDEO_ADV7170 is not set
-# CONFIG_VIDEO_ADV7175 is not set
-# CONFIG_VIDEO_THS7303 is not set
-# CONFIG_VIDEO_ADV7343 is not set
-
-#
-# Video improvement chips
-#
-# CONFIG_VIDEO_UPD64031A is not set
-# CONFIG_VIDEO_UPD64083 is not set
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_MT9M001 is not set
-CONFIG_SOC_CAMERA_MT9M111=y
-# CONFIG_SOC_CAMERA_MT9T031 is not set
-# CONFIG_SOC_CAMERA_MT9V022 is not set
-# CONFIG_SOC_CAMERA_TW9910 is not set
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
-CONFIG_VIDEO_PXA27x=y
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
-# CONFIG_V4L_USB_DRIVERS is not set
-CONFIG_RADIO_ADAPTERS=y
-# CONFIG_I2C_SI4713 is not set
-# CONFIG_RADIO_SI4713 is not set
-# CONFIG_USB_DSBR is not set
-# CONFIG_RADIO_SI470X is not set
-# CONFIG_USB_MR800 is not set
-CONFIG_RADIO_TEA5764=y
-CONFIG_RADIO_TEA5764_XTAL=y
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_UVESA is not set
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-CONFIG_FB_PXA_OVERLAY=y
-# CONFIG_FB_PXA_SMARTPANEL is not set
-CONFIG_FB_PXA_PARAMETERS=y
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_W100 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_BROADSHEET is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GENERIC=y
-CONFIG_BACKLIGHT_PWM=y
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FONTS=y
-# CONFIG_FONT_8x8 is not set
-# CONFIG_FONT_8x16 is not set
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-CONFIG_FONT_MINI_4x6=y
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_LOGO is not set
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
-# CONFIG_SND_HRTIMER is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_PXA2XX_LIB=y
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_PXA2XX_SOC=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_ALL_CODECS is not set
-# CONFIG_SOUND_PRIME is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-# CONFIG_HID_PID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_APPLE=m
-# CONFIG_HID_WACOM is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-# CONFIG_USB_DEVICEFS is not set
-# CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_PXA25X is not set
-# CONFIG_USB_GADGET_R8A66597 is not set
-CONFIG_USB_GADGET_PXA27X=y
-CONFIG_USB_PXA27X=y
-# CONFIG_USB_GADGET_S3C_HSOTG is not set
-# CONFIG_USB_GADGET_IMX is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_FSL_QE is not set
-# CONFIG_USB_GADGET_CI13XXX is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LANGWELL is not set
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-# CONFIG_USB_GADGET_DUALSPEED is not set
-# CONFIG_USB_ZERO is not set
-# CONFIG_USB_AUDIO is not set
-CONFIG_USB_ETH=y
-# CONFIG_USB_ETH_RNDIS is not set
-# CONFIG_USB_ETH_EEM is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-
-#
-# OTG and related infrastructure
-#
-CONFIG_USB_OTG_UTILS=y
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_NOP_USB_XCEIV is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_UNSAFE_RESUME=y
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-CONFIG_SDIO_UART=m
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_PXA=y
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_AT91 is not set
-# CONFIG_MMC_ATMELMCI is not set
-CONFIG_MMC_SPI=y
-# CONFIG_MEMSTICK is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_PCA9532 is not set
-# CONFIG_LEDS_GPIO is not set
-CONFIG_LEDS_LP3944=y
-# CONFIG_LEDS_PCA955X is not set
-# CONFIG_LEDS_DAC124S085 is not set
-# CONFIG_LEDS_PWM is not set
-# CONFIG_LEDS_BD2802 is not set
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-# CONFIG_RTC_DRV_PCF2123 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_RTC_DRV_SA1100 is not set
-# CONFIG_RTC_DRV_PXA is not set
-CONFIG_RTC_DRV_PCAP=y
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=m
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=m
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=m
-CONFIG_REISERFS_FS=m
-# CONFIG_REISERFS_CHECK is not set
-# CONFIG_REISERFS_PROC_INFO is not set
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_XFS_FS=m
-# CONFIG_XFS_QUOTA is not set
-# CONFIG_XFS_POSIX_ACL is not set
-# CONFIG_XFS_RT is not set
-# CONFIG_XFS_DEBUG is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=m
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-CONFIG_CRAMFS=m
-CONFIG_SQUASHFS=m
-# CONFIG_SQUASHFS_EMBEDDED is not set
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-CONFIG_ROMFS_FS=m
-CONFIG_ROMFS_BACKED_BY_BLOCK=y
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-# CONFIG_ROMFS_BACKED_BY_BOTH is not set
-CONFIG_ROMFS_ON_BLOCK=y
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-# CONFIG_NFS_V4 is not set
-# CONFIG_ROOT_NFS is not set
-CONFIG_NFSD=m
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-# CONFIG_NFSD_V4 is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=m
-CONFIG_NFS_ACL_SUPPORT=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS=y
-# CONFIG_CIFS_STATS2 is not set
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_DEBUG_PI_LIST=y
-# CONFIG_RT_MUTEX_TESTER is not set
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_LOCK_ALLOC=y
-CONFIG_PROVE_LOCKING=y
-CONFIG_LOCKDEP=y
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_LOCKDEP is not set
-CONFIG_TRACE_IRQFLAGS=y
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-CONFIG_STACKTRACE=y
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARM_UNWIND=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_ALGAPI2=m
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_AEAD2=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_BLKCIPHER2=m
-CONFIG_CRYPTO_HASH=m
-CONFIG_CRYPTO_HASH2=m
-CONFIG_CRYPTO_RNG2=m
-CONFIG_CRYPTO_PCOMP=m
-CONFIG_CRYPTO_MANAGER=m
-CONFIG_CRYPTO_MANAGER2=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_WORKQUEUE=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=m
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_HMAC=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_GHASH=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=m
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLOWFISH=m
-# CONFIG_CRYPTO_CAMELLIA is not set
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-# CONFIG_CRYPTO_SALSA20 is not set
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=m
-# CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=y
-# CONFIG_CRC_T10DIF is not set
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC32=y
-CONFIG_CRC7=y
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=m
-CONFIG_LZO_COMPRESS=m
-CONFIG_LZO_DECOMPRESS=m
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_NLATTR=y
diff --git a/arch/arm/configs/h5000_defconfig b/arch/arm/configs/h5000_defconfig
deleted file mode 100644
index 5bb7372..0000000
--- a/arch/arm/configs/h5000_defconfig
+++ /dev/null
@@ -1,995 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc6
-# Tue Sep 16 16:13:48 2008
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
-CONFIG_ZONE_DMA=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_CGROUPS is not set
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_USER_SCHED=y
-# CONFIG_CGROUP_SCHED is not set
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-# CONFIG_UID16 is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-# CONFIG_HAVE_IOREMAP_PROT is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-# CONFIG_HAVE_DMA_ATTRS is not set
-# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-CONFIG_HAVE_CLK=y
-# CONFIG_PROC_PAGE_MONITOR is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM7X00A is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-CONFIG_MACH_H5000=y
-# CONFIG_MACH_TRIZEPS4 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_PXA_EZX is not set
-CONFIG_PXA25x=y
-# CONFIG_PXA_PWM is not set
-
-#
-# Boot options
-#
-
-#
-# Power management
-#
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-# CONFIG_IWMMXT is not set
-CONFIG_XSCALE_PMU=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="keepinitrd"
-# CONFIG_XIP_KERNEL is not set
-CONFIG_KEXEC=y
-CONFIG_ATAGS_PROC=y
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_APM_EMULATION=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-# CONFIG_MTD_CHAR is not set
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_OTP is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x8000000
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-# CONFIG_MTD_PXA2XX is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_SHARP_SL is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-# CONFIG_NETDEVICES is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-# CONFIG_INPUT_APMPOWER is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=32
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
-# CONFIG_SPI is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# I2C GPIO expanders:
-#
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
-# CONFIG_WATCHDOG is not set
-
-#
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_SOUND is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-CONFIG_USB_GADGET_PXA25X=y
-CONFIG_USB_PXA25X=y
-CONFIG_USB_PXA25X_SMALL=y
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_PXA27X is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-# CONFIG_USB_GADGET_DUALSPEED is not set
-# CONFIG_USB_ZERO is not set
-CONFIG_USB_ETH=y
-# CONFIG_USB_ETH_RNDIS is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-# CONFIG_MMC is not set
-# CONFIG_NEW_LEDS is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# SPI RTC drivers
-#
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_SA1100=y
-# CONFIG_DMADEVICES is not set
-
-#
-# Voltage and Current regulators
-#
-# CONFIG_REGULATOR is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_UIO is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_NLS is not set
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_HAVE_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-# CONFIG_FTRACE is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_ERRORS is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_MANAGER=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-# CONFIG_CRYPTO_ECB is not set
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_HMAC=y
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-CONFIG_CRYPTO_SHA1=y
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_LZO is not set
-# CONFIG_CRYPTO_HW is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-CONFIG_CRC_CCITT=y
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig
deleted file mode 100644
index 21f2bff..0000000
--- a/arch/arm/configs/imote2_defconfig
+++ /dev/null
@@ -1,2039 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.34-rc2
-# Thu Apr  8 14:49:08 2010
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_BZIP2 is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_LZO is not set
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_TINY_RCU is not set
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-# CONFIG_RD_LZO is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-
-#
-# Kernel Performance Events And Counters
-#
-# CONFIG_PERF_EVENTS is not set
-# CONFIG_PERF_COUNTERS is not set
-CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_SLOW_WORK=y
-# CONFIG_SLOW_WORK_DEBUG is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_DEADLINE=y
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_DEFAULT_DEADLINE=y
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="deadline"
-# CONFIG_INLINE_SPIN_TRYLOCK is not set
-# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK is not set
-# CONFIG_INLINE_SPIN_LOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_SPIN_UNLOCK is not set
-# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
-# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_READ_TRYLOCK is not set
-# CONFIG_INLINE_READ_LOCK is not set
-# CONFIG_INLINE_READ_LOCK_BH is not set
-# CONFIG_INLINE_READ_LOCK_IRQ is not set
-# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_READ_UNLOCK is not set
-# CONFIG_INLINE_READ_UNLOCK_BH is not set
-# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
-# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_WRITE_TRYLOCK is not set
-# CONFIG_INLINE_WRITE_LOCK is not set
-# CONFIG_INLINE_WRITE_LOCK_BH is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_WRITE_UNLOCK is not set
-# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
-# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
-# CONFIG_MUTEX_SPIN_ON_OWNER is not set
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_NUC93X is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_SHMOBILE is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5P6440 is not set
-# CONFIG_ARCH_S5P6442 is not set
-# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_S5PV210 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_U8500 is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-
-#
-# Intel/Marvell Dev Platforms (sorted by hardware release time)
-#
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_ZYLONITE300 is not set
-# CONFIG_MACH_ZYLONITE320 is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-
-#
-# Third Party Dev Platforms (sorted by vendor name)
-#
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_ARCH_VIPER is not set
-# CONFIG_MACH_ARCOM_ZEUS is not set
-# CONFIG_MACH_BALLOON3 is not set
-# CONFIG_MACH_CSB726 is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_EXEDA is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_CAPC7117 is not set
-# CONFIG_ARCH_GUMSTIX is not set
-CONFIG_MACH_INTELMOTE2=y
-# CONFIG_MACH_STARGATE2 is not set
-# CONFIG_MACH_XCEP is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_COLIBRI300 is not set
-# CONFIG_MACH_COLIBRI320 is not set
-
-#
-# End-user Products (sorted by vendor name)
-#
-# CONFIG_MACH_H4700 is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_HIMALAYA is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_PXA_EZX is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_MACH_RAUMFELD_RC is not set
-# CONFIG_MACH_RAUMFELD_CONNECTOR is not set
-# CONFIG_MACH_RAUMFELD_SPEAKER is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_MACH_ICONTROL is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-CONFIG_PXA27x=y
-CONFIG_PXA_SSP=y
-CONFIG_PXA_HAVE_BOARD_IRQS=y
-CONFIG_PLAT_PXA=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-CONFIG_CPU_HAS_PMU=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS2,115200 mem=32M"
-# CONFIG_XIP_KERNEL is not set
-CONFIG_KEXEC=y
-CONFIG_ATAGS_PROC=y
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_FREQ is not set
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_APM_EMULATION=y
-CONFIG_PM_RUNTIME=y
-CONFIG_PM_OPS=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-CONFIG_XFRM_IPCOMP=m
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-CONFIG_INET_TUNNEL=m
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-CONFIG_IPV6=m
-# CONFIG_IPV6_PRIVACY is not set
-# CONFIG_IPV6_ROUTER_PREF is not set
-# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_MIP6=m
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-CONFIG_INET6_XFRM_MODE_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_BEET=m
-# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-CONFIG_IPV6_SIT=m
-# CONFIG_IPV6_SIT_6RD is not set
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=m
-CONFIG_IPV6_MULTIPLE_TABLES=y
-CONFIG_IPV6_SUBTREES=y
-# CONFIG_IPV6_MROUTE is not set
-# CONFIG_NETWORK_SECMARK is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-CONFIG_NETFILTER_ADVANCED=y
-CONFIG_BRIDGE_NETFILTER=y
-
-#
-# Core Netfilter Configuration
-#
-CONFIG_NETFILTER_NETLINK=m
-CONFIG_NETFILTER_NETLINK_QUEUE=m
-CONFIG_NETFILTER_NETLINK_LOG=m
-CONFIG_NF_CONNTRACK=m
-CONFIG_NF_CT_ACCT=y
-CONFIG_NF_CONNTRACK_MARK=y
-CONFIG_NF_CONNTRACK_EVENTS=y
-# CONFIG_NF_CT_PROTO_DCCP is not set
-CONFIG_NF_CT_PROTO_GRE=m
-CONFIG_NF_CT_PROTO_SCTP=m
-CONFIG_NF_CT_PROTO_UDPLITE=m
-CONFIG_NF_CONNTRACK_AMANDA=m
-CONFIG_NF_CONNTRACK_FTP=m
-CONFIG_NF_CONNTRACK_H323=m
-CONFIG_NF_CONNTRACK_IRC=m
-CONFIG_NF_CONNTRACK_NETBIOS_NS=m
-CONFIG_NF_CONNTRACK_PPTP=m
-CONFIG_NF_CONNTRACK_SANE=m
-CONFIG_NF_CONNTRACK_SIP=m
-CONFIG_NF_CONNTRACK_TFTP=m
-CONFIG_NF_CT_NETLINK=m
-# CONFIG_NETFILTER_TPROXY is not set
-CONFIG_NETFILTER_XTABLES=m
-CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
-# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
-# CONFIG_NETFILTER_XT_TARGET_CT is not set
-# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
-CONFIG_NETFILTER_XT_TARGET_HL=m
-CONFIG_NETFILTER_XT_TARGET_LED=m
-CONFIG_NETFILTER_XT_TARGET_MARK=m
-CONFIG_NETFILTER_XT_TARGET_NFLOG=m
-CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
-# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
-# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
-# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
-CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
-# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
-# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
-CONFIG_NETFILTER_XT_MATCH_COMMENT=m
-CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
-CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
-CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
-CONFIG_NETFILTER_XT_MATCH_DCCP=m
-CONFIG_NETFILTER_XT_MATCH_DSCP=m
-CONFIG_NETFILTER_XT_MATCH_ESP=m
-CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
-CONFIG_NETFILTER_XT_MATCH_HELPER=m
-CONFIG_NETFILTER_XT_MATCH_HL=m
-# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
-CONFIG_NETFILTER_XT_MATCH_LENGTH=m
-CONFIG_NETFILTER_XT_MATCH_LIMIT=m
-CONFIG_NETFILTER_XT_MATCH_MAC=m
-CONFIG_NETFILTER_XT_MATCH_MARK=m
-CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
-# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
-CONFIG_NETFILTER_XT_MATCH_POLICY=m
-# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
-CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
-CONFIG_NETFILTER_XT_MATCH_QUOTA=m
-# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
-CONFIG_NETFILTER_XT_MATCH_REALM=m
-# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
-CONFIG_NETFILTER_XT_MATCH_SCTP=m
-CONFIG_NETFILTER_XT_MATCH_STATE=m
-CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
-CONFIG_NETFILTER_XT_MATCH_STRING=m
-CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
-CONFIG_NETFILTER_XT_MATCH_TIME=m
-CONFIG_NETFILTER_XT_MATCH_U32=m
-# CONFIG_NETFILTER_XT_MATCH_OSF is not set
-# CONFIG_IP_VS is not set
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_NF_DEFRAG_IPV4=m
-CONFIG_NF_CONNTRACK_IPV4=m
-CONFIG_NF_CONNTRACK_PROC_COMPAT=y
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-CONFIG_IP_NF_MATCH_AH=m
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_NF_NAT=m
-CONFIG_NF_NAT_NEEDED=y
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_TARGET_NETMAP=m
-CONFIG_IP_NF_TARGET_REDIRECT=m
-CONFIG_NF_NAT_SNMP_BASIC=m
-CONFIG_NF_NAT_PROTO_GRE=m
-CONFIG_NF_NAT_PROTO_UDPLITE=m
-CONFIG_NF_NAT_PROTO_SCTP=m
-CONFIG_NF_NAT_FTP=m
-CONFIG_NF_NAT_IRC=m
-CONFIG_NF_NAT_TFTP=m
-CONFIG_NF_NAT_AMANDA=m
-CONFIG_NF_NAT_PPTP=m
-CONFIG_NF_NAT_H323=m
-CONFIG_NF_NAT_SIP=m
-CONFIG_IP_NF_MANGLE=m
-CONFIG_IP_NF_TARGET_CLUSTERIP=m
-CONFIG_IP_NF_TARGET_ECN=m
-CONFIG_IP_NF_TARGET_TTL=m
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_NF_CONNTRACK_IPV6=m
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_MATCH_AH=m
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-CONFIG_IP6_NF_MATCH_MH=m
-CONFIG_IP6_NF_MATCH_RT=m
-CONFIG_IP6_NF_TARGET_HL=m
-CONFIG_IP6_NF_TARGET_LOG=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_RAW=m
-# CONFIG_BRIDGE_NF_EBTABLES is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-CONFIG_STP=m
-CONFIG_BRIDGE=m
-# CONFIG_BRIDGE_IGMP_SNOOPING is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-CONFIG_LLC=m
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_PHONET is not set
-CONFIG_IEEE802154=y
-# CONFIG_NET_SCHED is not set
-CONFIG_NET_CLS_ROUTE=y
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-CONFIG_FIB_RULES=y
-# CONFIG_WIRELESS is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-CONFIG_CONNECTOR=m
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_AFS_PARTS=y
-CONFIG_MTD_AR7_PARTS=y
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_HAVE_MTD_OTP=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-# CONFIG_MTD_CFI_I2 is not set
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_OTP=y
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_PXA2XX=y
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
-# CONFIG_MTD_SST25L is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-# CONFIG_BLK_DEV_DRBD is not set
-CONFIG_BLK_DEV_NBD=m
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=y
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=y
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_NET_ETHERNET is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-CONFIG_IEEE802154_DRIVERS=y
-# CONFIG_IEEE802154_FAKEHARD is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_PPP_MPPE is not set
-# CONFIG_PPPOE is not set
-# CONFIG_PPPOL2TP is not set
-# CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-# CONFIG_INPUT_SPARSEKMAP is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-# CONFIG_INPUT_APMPOWER is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_LM8323 is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-CONFIG_KEYBOARD_PXA27x=y
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
-# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-CONFIG_TOUCHSCREEN_DA9034=y
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-CONFIG_INPUT_UINPUT=y
-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_MAX3100 is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_TIMBERDALE is not set
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=8
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_DESIGNWARE is not set
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-# CONFIG_I2C_XILINX is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_BITBANG is not set
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_PXA2XX=y
-# CONFIG_SPI_XILINX is not set
-# CONFIG_SPI_DESIGNWARE is not set
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_TLE62X0 is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-
-#
-# Memory mapped GPIO expanders:
-#
-# CONFIG_GPIO_IT8761E is not set
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX7300 is not set
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-# CONFIG_GPIO_ADP5588 is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_GPIO_MC33880 is not set
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-# CONFIG_PDA_POWER is not set
-# CONFIG_APM_POWER is not set
-# CONFIG_BATTERY_DS2760 is not set
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_DA9030 is not set
-# CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_88PM860X is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_HTC_I2CPLD is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-CONFIG_PMIC_DA903X=y
-# CONFIG_PMIC_ADP5520 is not set
-# CONFIG_MFD_MAX8925 is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_WM8994 is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_MFD_MC13783 is not set
-# CONFIG_AB3100_CORE is not set
-# CONFIG_EZX_PCAP is not set
-# CONFIG_AB4500_CORE is not set
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DEBUG=y
-# CONFIG_REGULATOR_DUMMY is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
-CONFIG_REGULATOR_USERSPACE_CONSUMER=y
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-# CONFIG_REGULATOR_MAX8649 is not set
-# CONFIG_REGULATOR_MAX8660 is not set
-CONFIG_REGULATOR_DA903X=y
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-CONFIG_MEDIA_SUPPORT=y
-
-#
-# Multimedia core support
-#
-CONFIG_VIDEO_DEV=y
-CONFIG_VIDEO_V4L2_COMMON=y
-CONFIG_VIDEO_ALLOW_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=y
-
-#
-# Multimedia drivers
-#
-CONFIG_IR_CORE=y
-CONFIG_VIDEO_IR=y
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=y
-CONFIG_MEDIA_TUNER_CUSTOMISE=y
-# CONFIG_MEDIA_TUNER_SIMPLE is not set
-# CONFIG_MEDIA_TUNER_TDA8290 is not set
-# CONFIG_MEDIA_TUNER_TDA827X is not set
-# CONFIG_MEDIA_TUNER_TDA18271 is not set
-# CONFIG_MEDIA_TUNER_TDA9887 is not set
-# CONFIG_MEDIA_TUNER_TEA5761 is not set
-# CONFIG_MEDIA_TUNER_TEA5767 is not set
-# CONFIG_MEDIA_TUNER_MT20XX is not set
-# CONFIG_MEDIA_TUNER_MT2060 is not set
-# CONFIG_MEDIA_TUNER_MT2266 is not set
-# CONFIG_MEDIA_TUNER_MT2131 is not set
-# CONFIG_MEDIA_TUNER_QT1010 is not set
-# CONFIG_MEDIA_TUNER_XC2028 is not set
-# CONFIG_MEDIA_TUNER_XC5000 is not set
-# CONFIG_MEDIA_TUNER_MXL5005S is not set
-# CONFIG_MEDIA_TUNER_MXL5007T is not set
-# CONFIG_MEDIA_TUNER_MC44S803 is not set
-CONFIG_MEDIA_TUNER_MAX2165=m
-CONFIG_VIDEO_V4L2=y
-CONFIG_VIDEO_V4L1=y
-CONFIG_VIDEOBUF_GEN=y
-CONFIG_VIDEOBUF_DMA_SG=y
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
-CONFIG_VIDEO_IR_I2C=y
-
-#
-# Encoders/decoders and other helper chips
-#
-
-#
-# Audio decoders
-#
-# CONFIG_VIDEO_TVAUDIO is not set
-# CONFIG_VIDEO_TDA7432 is not set
-# CONFIG_VIDEO_TDA9840 is not set
-# CONFIG_VIDEO_TDA9875 is not set
-# CONFIG_VIDEO_TEA6415C is not set
-# CONFIG_VIDEO_TEA6420 is not set
-# CONFIG_VIDEO_MSP3400 is not set
-# CONFIG_VIDEO_CS5345 is not set
-# CONFIG_VIDEO_CS53L32A is not set
-# CONFIG_VIDEO_M52790 is not set
-# CONFIG_VIDEO_TLV320AIC23B is not set
-# CONFIG_VIDEO_WM8775 is not set
-# CONFIG_VIDEO_WM8739 is not set
-# CONFIG_VIDEO_VP27SMPX is not set
-
-#
-# RDS decoders
-#
-# CONFIG_VIDEO_SAA6588 is not set
-
-#
-# Video decoders
-#
-# CONFIG_VIDEO_ADV7180 is not set
-# CONFIG_VIDEO_BT819 is not set
-# CONFIG_VIDEO_BT856 is not set
-# CONFIG_VIDEO_BT866 is not set
-# CONFIG_VIDEO_KS0127 is not set
-# CONFIG_VIDEO_OV7670 is not set
-# CONFIG_VIDEO_MT9V011 is not set
-# CONFIG_VIDEO_TCM825X is not set
-# CONFIG_VIDEO_SAA7110 is not set
-# CONFIG_VIDEO_SAA711X is not set
-# CONFIG_VIDEO_SAA717X is not set
-# CONFIG_VIDEO_SAA7191 is not set
-# CONFIG_VIDEO_TVP514X is not set
-# CONFIG_VIDEO_TVP5150 is not set
-# CONFIG_VIDEO_TVP7002 is not set
-# CONFIG_VIDEO_VPX3220 is not set
-
-#
-# Video and audio decoders
-#
-# CONFIG_VIDEO_CX25840 is not set
-
-#
-# MPEG video encoders
-#
-# CONFIG_VIDEO_CX2341X is not set
-
-#
-# Video encoders
-#
-# CONFIG_VIDEO_SAA7127 is not set
-# CONFIG_VIDEO_SAA7185 is not set
-# CONFIG_VIDEO_ADV7170 is not set
-# CONFIG_VIDEO_ADV7175 is not set
-# CONFIG_VIDEO_THS7303 is not set
-# CONFIG_VIDEO_ADV7343 is not set
-
-#
-# Video improvement chips
-#
-# CONFIG_VIDEO_UPD64031A is not set
-# CONFIG_VIDEO_UPD64083 is not set
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-CONFIG_SOC_CAMERA=y
-# CONFIG_SOC_CAMERA_MT9M001 is not set
-CONFIG_SOC_CAMERA_MT9M111=y
-# CONFIG_SOC_CAMERA_MT9T031 is not set
-# CONFIG_SOC_CAMERA_MT9T112 is not set
-# CONFIG_SOC_CAMERA_MT9V022 is not set
-# CONFIG_SOC_CAMERA_RJ54N1 is not set
-# CONFIG_SOC_CAMERA_TW9910 is not set
-# CONFIG_SOC_CAMERA_PLATFORM is not set
-# CONFIG_SOC_CAMERA_OV772X is not set
-# CONFIG_SOC_CAMERA_OV9640 is not set
-CONFIG_VIDEO_PXA27x=y
-# CONFIG_VIDEO_SH_MOBILE_CEU is not set
-# CONFIG_V4L_USB_DRIVERS is not set
-# CONFIG_RADIO_ADAPTERS is not set
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_UVESA is not set
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-CONFIG_FB_PXA_OVERLAY=y
-# CONFIG_FB_PXA_SMARTPANEL is not set
-CONFIG_FB_PXA_PARAMETERS=y
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_W100 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_BROADSHEET is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_GENERIC=y
-# CONFIG_BACKLIGHT_DA903X is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FONTS=y
-# CONFIG_FONT_8x8 is not set
-# CONFIG_FONT_8x16 is not set
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-CONFIG_FONT_MINI_4x6=y
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_LOGO is not set
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
-# CONFIG_SND_HRTIMER is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_PXA2XX_LIB=y
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_PXA2XX_SOC=y
-# CONFIG_SND_PXA2XX_SOC_IMOTE2 is not set
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_ALL_CODECS is not set
-# CONFIG_SOUND_PRIME is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-# CONFIG_HID_PID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-
-#
-# Special HID drivers
-#
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-# CONFIG_USB_DEVICEFS is not set
-# CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_DEBUG_FS is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_PXA25X is not set
-# CONFIG_USB_GADGET_R8A66597 is not set
-CONFIG_USB_GADGET_PXA27X=y
-CONFIG_USB_PXA27X=y
-# CONFIG_USB_GADGET_S3C_HSOTG is not set
-# CONFIG_USB_GADGET_IMX is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_FSL_QE is not set
-# CONFIG_USB_GADGET_CI13XXX is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LANGWELL is not set
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-# CONFIG_USB_GADGET_DUALSPEED is not set
-# CONFIG_USB_ZERO is not set
-# CONFIG_USB_AUDIO is not set
-CONFIG_USB_ETH=y
-# CONFIG_USB_ETH_RNDIS is not set
-# CONFIG_USB_ETH_EEM is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_MASS_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-# CONFIG_USB_G_NOKIA is not set
-# CONFIG_USB_G_MULTI is not set
-
-#
-# OTG and related infrastructure
-#
-CONFIG_USB_OTG_UTILS=y
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_USB_ULPI is not set
-# CONFIG_NOP_USB_XCEIV is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_UNSAFE_RESUME=y
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-CONFIG_SDIO_UART=m
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_PXA=y
-# CONFIG_MMC_SDHCI is not set
-CONFIG_MMC_SPI=y
-# CONFIG_MEMSTICK is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_PCA9532 is not set
-# CONFIG_LEDS_GPIO is not set
-CONFIG_LEDS_LP3944=y
-# CONFIG_LEDS_PCA955X is not set
-# CONFIG_LEDS_DA903X is not set
-# CONFIG_LEDS_DAC124S085 is not set
-# CONFIG_LEDS_REGULATOR is not set
-# CONFIG_LEDS_BD2802 is not set
-# CONFIG_LEDS_LT3593 is not set
-CONFIG_LEDS_TRIGGERS=y
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_BQ32K is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-# CONFIG_RTC_DRV_PCF2123 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_MSM6242 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_RP5C01 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_RTC_DRV_SA1100 is not set
-CONFIG_RTC_DRV_PXA=y
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=m
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=m
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=m
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_AUTOFS_FS=y
-CONFIG_AUTOFS4_FS=y
-CONFIG_FUSE_FS=m
-CONFIG_CUSE=m
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_JFFS2_SUMMARY=y
-CONFIG_JFFS2_FS_XATTR=y
-CONFIG_JFFS2_FS_POSIX_ACL=y
-CONFIG_JFFS2_FS_SECURITY=y
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-# CONFIG_LOGFS is not set
-CONFIG_CRAMFS=m
-CONFIG_SQUASHFS=m
-# CONFIG_SQUASHFS_EMBEDDED is not set
-CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-CONFIG_ROMFS_FS=m
-CONFIG_ROMFS_BACKED_BY_BLOCK=y
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-# CONFIG_ROMFS_BACKED_BY_BOTH is not set
-CONFIG_ROMFS_ON_BLOCK=y
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-# CONFIG_NFS_V4 is not set
-# CONFIG_ROOT_NFS is not set
-CONFIG_NFSD=m
-CONFIG_NFSD_V2_ACL=y
-CONFIG_NFSD_V3=y
-CONFIG_NFSD_V3_ACL=y
-# CONFIG_NFSD_V4 is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=m
-CONFIG_NFS_ACL_SUPPORT=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
-# CONFIG_CEPH_FS is not set
-CONFIG_CIFS=m
-CONFIG_CIFS_STATS=y
-# CONFIG_CIFS_STATS2 is not set
-CONFIG_CIFS_WEAK_PW_HASH=y
-CONFIG_CIFS_XATTR=y
-CONFIG_CIFS_POSIX=y
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_NLS_UTF8=m
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-CONFIG_DEBUG_PREEMPT=y
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_DEBUG_PI_LIST=y
-# CONFIG_RT_MUTEX_TESTER is not set
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_MUTEXES=y
-CONFIG_DEBUG_LOCK_ALLOC=y
-CONFIG_PROVE_LOCKING=y
-# CONFIG_PROVE_RCU is not set
-CONFIG_LOCKDEP=y
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_LOCKDEP is not set
-CONFIG_TRACE_IRQFLAGS=y
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-CONFIG_STACKTRACE=y
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_LKDTM is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARM_UNWIND=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-# CONFIG_OC_ETM is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_DEFAULT_SECURITY_SELINUX is not set
-# CONFIG_DEFAULT_SECURITY_SMACK is not set
-# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_DEFAULT_SECURITY=""
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_ALGAPI2=m
-CONFIG_CRYPTO_AEAD=m
-CONFIG_CRYPTO_AEAD2=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_BLKCIPHER2=m
-CONFIG_CRYPTO_HASH=m
-CONFIG_CRYPTO_HASH2=m
-CONFIG_CRYPTO_RNG2=m
-CONFIG_CRYPTO_PCOMP=m
-CONFIG_CRYPTO_MANAGER=m
-CONFIG_CRYPTO_MANAGER2=m
-CONFIG_CRYPTO_GF128MUL=m
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_WORKQUEUE=m
-CONFIG_CRYPTO_CRYPTD=m
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=m
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_LRW=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRYPTO_XTS=m
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_HMAC=m
-CONFIG_CRYPTO_XCBC=m
-CONFIG_CRYPTO_VMAC=m
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_GHASH=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_TGR192=m
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=m
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLOWFISH=m
-# CONFIG_CRYPTO_CAMELLIA is not set
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=m
-CONFIG_CRYPTO_FCRYPT=m
-CONFIG_CRYPTO_KHAZAD=m
-# CONFIG_CRYPTO_SALSA20 is not set
-CONFIG_CRYPTO_SEED=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=m
-# CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=y
-# CONFIG_CRC_T10DIF is not set
-CONFIG_CRC_ITU_T=y
-CONFIG_CRC32=y
-CONFIG_CRC7=y
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_TEXTSEARCH=y
-CONFIG_TEXTSEARCH_KMP=m
-CONFIG_TEXTSEARCH_BM=m
-CONFIG_TEXTSEARCH_FSM=m
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_NLATTR=y
-CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig
deleted file mode 100644
index aeb7686..0000000
--- a/arch/arm/configs/lpd270_defconfig
+++ /dev/null
@@ -1,1031 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.20-rc1
-# Sat Dec 16 06:05:51 2006
-#
-CONFIG_ARM=y
-# CONFIG_GENERIC_TIME is not set
-CONFIG_MMU=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-# CONFIG_EMBEDDED is not set
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODULE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_OMAP is not set
-
-#
-# Intel PXA2xx Implementations
-#
-# CONFIG_ARCH_LUBBOCK is not set
-CONFIG_MACH_LOGICPD_PXA270=y
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_MACH_TRIZEPS4 is not set
-CONFIG_PXA27x=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-# CONFIG_ARM_THUMB is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-
-#
-# Bus support
-#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-# CONFIG_AEABI is not set
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M"
-# CONFIG_XIP_KERNEL is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-# CONFIG_ARTHUR is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-# CONFIG_APM is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_NETDEBUG is not set
-# CONFIG_PACKET is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-CONFIG_IPV6=y
-# CONFIG_IPV6_PRIVACY is not set
-# CONFIG_IPV6_ROUTER_PREF is not set
-# CONFIG_INET6_AH is not set
-# CONFIG_INET6_ESP is not set
-# CONFIG_INET6_IPCOMP is not set
-# CONFIG_IPV6_MIP6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET6_XFRM_MODE_BEET is not set
-# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-# CONFIG_IPV6_SIT is not set
-# CONFIG_IPV6_TUNNEL is not set
-# CONFIG_IPV6_MULTIPLE_TABLES is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_IEEE80211 is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-# CONFIG_CONNECTOR is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
-# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-# CONFIG_MTD_CFI_I1 is not set
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_OTP is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_SHARP_SL is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
-# CONFIG_MTD_NAND is not set
-
-#
-# OneNAND Flash Device Drivers
-#
-# CONFIG_MTD_ONENAND is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-CONFIG_BLK_DEV_NBD=y
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-# CONFIG_BLK_DEV_IDECD is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_IDE_ARM is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_NETLINK is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-# CONFIG_ATA is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# PHY device support
-#
-# CONFIG_PHYLIB is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_SMC91X=y
-# CONFIG_DM9000 is not set
-# CONFIG_SMC911X is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ABITUGURU is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Misc devices
-#
-# CONFIG_TIFM_CORE is not set
-
-#
-# LED devices
-#
-# CONFIG_NEW_LEDS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FIRMWARE_EDID is not set
-CONFIG_FB=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_VIRTUAL is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-# CONFIG_SND_SEQUENCER is not set
-# CONFIG_SND_MIXER_OSS is not set
-# CONFIG_SND_PCM_OSS is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-# CONFIG_SND_SUPPORT_OLD_API is not set
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
-CONFIG_SND_AC97_CODEC=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-
-#
-# ALSA ARM devices
-#
-CONFIG_SND_PXA2XX_PCM=y
-CONFIG_SND_PXA2XX_AC97=y
-
-#
-# Open Sound System
-#
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=y
-
-#
-# HID Devices
-#
-CONFIG_HID=y
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-# CONFIG_USB is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# Real Time Clock
-#
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-# CONFIG_VFAT_FS is not set
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Distributed Lock Manager
-#
-# CONFIG_DLM is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_RWSEMS is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_LIST is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_FORCED_INLINING=y
-# CONFIG_RCU_TORTURE_TEST is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-# CONFIG_CRYPTO is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_IOMAP_COPY=y
diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig
deleted file mode 100644
index 75c6293..0000000
--- a/arch/arm/configs/lubbock_defconfig
+++ /dev/null
@@ -1,800 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc1-bk2
-# Mon Mar 28 00:18:13 2005
-#
-CONFIG_ARM=y
-CONFIG_MMU=y
-CONFIG_UID16=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_IOMAP=y
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
-CONFIG_BROKEN_ON_SMP=y
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
-# CONFIG_IKCONFIG is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODULE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
-
-#
-# System Type
-#
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_IOP3XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_L7200 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
-
-#
-# Intel PXA2xx Implementations
-#
-CONFIG_ARCH_LUBBOCK=y
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-CONFIG_PXA25x=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_MINICACHE=y
-
-#
-# Processor Features
-#
-# CONFIG_ARM_THUMB is not set
-CONFIG_XSCALE_PMU=y
-CONFIG_SA1111=y
-CONFIG_DMABOUNCE=y
-CONFIG_FORCE_MAX_ZONEORDER=9
-
-#
-# Bus support
-#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-CONFIG_PCCARD=y
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=y
-
-#
-# PC-card bridges
-#
-# CONFIG_TCIC is not set
-CONFIG_PCMCIA_PXA2XX=y
-
-#
-# Kernel Features
-#
-# CONFIG_PREEMPT is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_TIMER=y
-CONFIG_LEDS_CPU=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M"
-# CONFIG_XIP_KERNEL is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-# CONFIG_ARTHUR is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
-# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-# CONFIG_MTD_CFI_I1 is not set
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_LUBBOCK=y
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_EDB7312 is not set
-# CONFIG_MTD_SHARP_SL is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
-# CONFIG_MTD_NAND is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_FD is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_CDROM_PKTCDVD is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_SCSI is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_PACKET is not set
-# CONFIG_NETLINK_DEV is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_IP_TCPDIAG is not set
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_SMC91X=y
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# PCMCIA network device support
-#
-CONFIG_NET_PCMCIA=y
-# CONFIG_PCMCIA_3C589 is not set
-# CONFIG_PCMCIA_3C574 is not set
-# CONFIG_PCMCIA_FMVJ18X is not set
-CONFIG_PCMCIA_PCNET=y
-# CONFIG_PCMCIA_NMCLAN is not set
-# CONFIG_PCMCIA_SMC91C92 is not set
-# CONFIG_PCMCIA_XIRC2PS is not set
-# CONFIG_PCMCIA_AXNET is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-CONFIG_INPUT_MOUSE=y
-CONFIG_MOUSE_PS2=y
-# CONFIG_MOUSE_SERIAL is not set
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_SA1111=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_NVRAM is not set
-# CONFIG_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
-
-#
-# PCMCIA character devices
-#
-# CONFIG_SYNCLINK_CS is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-# CONFIG_FB is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB is not set
-
-#
-# USB Gadget Support
-#
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-CONFIG_USB_GADGET_PXA2XX=y
-CONFIG_USB_PXA2XX=y
-CONFIG_USB_PXA2XX_SMALL=y
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_SA1100 is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_DUALSPEED is not set
-# CONFIG_USB_ZERO is not set
-# CONFIG_USB_ETH is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-CONFIG_USB_G_SERIAL=y
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-
-#
-# XFS support
-#
-# CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-# CONFIG_VFAT_FS is not set
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
-# CONFIG_TMPFS is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-# CONFIG_JFFS2_FS_NAND is not set
-# CONFIG_JFFS2_FS_NOR_ECC is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_FS is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-# CONFIG_CRYPTO is not set
-
-#
-# Hardware crypto devices
-#
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
deleted file mode 100644
index 8e9a723..0000000
--- a/arch/arm/configs/magician_defconfig
+++ /dev/null
@@ -1,1536 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc3
-# Fri Jan 30 12:42:03 2009
-#
-CONFIG_ARM=y
-CONFIG_HAVE_PWM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-# CONFIG_UID16 is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_DEFAULT_IOSCHED="noop"
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_W90X900 is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_VIPER is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_CM_X300 is not set
-CONFIG_MACH_H4700=y
-CONFIG_MACH_MAGICIAN=y
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_PXA_EZX is not set
-CONFIG_PXA27x=y
-CONFIG_PXA_SSP=y
-CONFIG_PXA_PWM=y
-CONFIG_PXA_HAVE_BOARD_IRQS=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="keepinitrd"
-# CONFIG_XIP_KERNEL is not set
-CONFIG_KEXEC=y
-CONFIG_ATAGS_PROC=y
-
-#
-# CPU Power Management
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-# CONFIG_CPU_FREQ_DEBUG is not set
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-CONFIG_CPU_FREQ_GOV_ONDEMAND=y
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_COMPAT_NET_DEV_OPS=y
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-CONFIG_IRDA=m
-
-#
-# IrDA protocols
-#
-CONFIG_IRLAN=m
-# CONFIG_IRNET is not set
-CONFIG_IRCOMM=m
-CONFIG_IRDA_ULTRA=y
-
-#
-# IrDA options
-#
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-CONFIG_IRDA_DEBUG=y
-
-#
-# Infrared-port device drivers
-#
-
-#
-# SIR device drivers
-#
-CONFIG_IRTTY_SIR=m
-
-#
-# Dongle support
-#
-# CONFIG_DONGLE is not set
-# CONFIG_KINGSUN_DONGLE is not set
-# CONFIG_KSDAZZLE_DONGLE is not set
-# CONFIG_KS959_DONGLE is not set
-
-#
-# FIR device drivers
-#
-# CONFIG_USB_IRDA is not set
-# CONFIG_SIGMATEL_FIR is not set
-CONFIG_PXA_FICP=m
-# CONFIG_MCS_FIR is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIBTUSB=m
-# CONFIG_BT_HCIBTSDIO is not set
-# CONFIG_BT_HCIUART is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-# CONFIG_WIRELESS is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_FIRMWARE_IN_KERNEL is not set
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-# CONFIG_MTD_PXA2XX is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_SHARP_SL is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-# CONFIG_MTD_QINFO_PROBE is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_NET_ETHERNET is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-CONFIG_PPP=m
-# CONFIG_PPP_MULTILINK is not set
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-# CONFIG_PPPOE is not set
-# CONFIG_PPPOL2TP is not set
-# CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_PXA27x is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-CONFIG_INPUT_UINPUT=m
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_DEVKMEM is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-# CONFIG_SERIAL_PXA_CONSOLE is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-# CONFIG_SPI is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-CONFIG_W1=y
-
-#
-# 1-wire Bus Masters
-#
-# CONFIG_W1_MASTER_DS2490 is not set
-# CONFIG_W1_MASTER_DS2482 is not set
-CONFIG_W1_MASTER_DS1WM=y
-# CONFIG_W1_MASTER_GPIO is not set
-
-#
-# 1-wire Slaves
-#
-# CONFIG_W1_SLAVE_THERM is not set
-# CONFIG_W1_SLAVE_SMEM is not set
-# CONFIG_W1_SLAVE_DS2433 is not set
-CONFIG_W1_SLAVE_DS2760=y
-# CONFIG_W1_SLAVE_BQ27000 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-CONFIG_PDA_POWER=y
-CONFIG_BATTERY_DS2760=y
-# CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-CONFIG_MFD_ASIC3=y
-CONFIG_HTC_EGPIO=y
-CONFIG_HTC_PASIC3=y
-# CONFIG_TPS65010 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-CONFIG_FB_PXA_OVERLAY=y
-# CONFIG_FB_PXA_SMARTPANEL is not set
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_MBX is not set
-CONFIG_FB_W100=y
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-# CONFIG_LCD_ILI9320 is not set
-# CONFIG_LCD_PLATFORM is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_PWM=y
-
-#
-# Display device support
-#
-CONFIG_DISPLAY_SUPPORT=y
-
-#
-# Display hardware drivers
-#
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-# CONFIG_FONT_8x8 is not set
-# CONFIG_FONT_8x16 is not set
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-CONFIG_FONT_MINI_4x6=y
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_LOGO is not set
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-# CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-# CONFIG_SND_ARM is not set
-CONFIG_SND_PXA2XX_LIB=m
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=m
-CONFIG_SND_PXA2XX_SOC=m
-CONFIG_SND_SOC_I2C_AND_SPI=m
-# CONFIG_SND_SOC_ALL_CODECS is not set
-# CONFIG_SOUND_PRIME is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_HID=m
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-# CONFIG_USB_DEVICEFS is not set
-# CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-CONFIG_USB_MON=m
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-#
-
-#
-# see USB_STORAGE Help for more information
-#
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_VBUS_DRAW=500
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_PXA25X is not set
-CONFIG_USB_GADGET_PXA27X=y
-CONFIG_USB_PXA27X=y
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_IMX is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_FSL_QE is not set
-# CONFIG_USB_GADGET_CI13XXX is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-# CONFIG_USB_GADGET_DUALSPEED is not set
-# CONFIG_USB_ZERO is not set
-CONFIG_USB_ETH=m
-# CONFIG_USB_ETH_RNDIS is not set
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-# CONFIG_USB_FILE_STORAGE_TEST is not set
-CONFIG_USB_G_SERIAL=m
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-CONFIG_USB_CDC_COMPOSITE=m
-
-#
-# OTG and related infrastructure
-#
-CONFIG_USB_OTG_UTILS=y
-CONFIG_USB_GPIO_VBUS=y
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-CONFIG_SDIO_UART=m
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_PXA=y
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_PCA9532 is not set
-CONFIG_LEDS_GPIO=y
-# CONFIG_LEDS_PCA955X is not set
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-CONFIG_RTC_DEBUG=y
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-
-#
-# SPI RTC drivers
-#
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_SA1100=y
-# CONFIG_RTC_DRV_PXA is not set
-# CONFIG_DMADEVICES is not set
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-CONFIG_REGULATOR_BQ24022=y
-# CONFIG_UIO is not set
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_LZO=y
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-CONFIG_ROOT_NFS=y
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-CONFIG_NLS_CODEPAGE_1251=m
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=y
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
-CONFIG_TIMER_STATS=y
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-
-#
-# Tracers
-#
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_ALGAPI2=m
-CONFIG_CRYPTO_AEAD2=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_BLKCIPHER2=m
-CONFIG_CRYPTO_HASH=m
-CONFIG_CRYPTO_HASH2=m
-CONFIG_CRYPTO_RNG2=m
-CONFIG_CRYPTO_MANAGER=m
-CONFIG_CRYPTO_MANAGER2=m
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-CONFIG_CRYPTO_SHA1=m
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_CRC_CCITT=y
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/mainstone_defconfig b/arch/arm/configs/mainstone_defconfig
deleted file mode 100644
index 1cddb61..0000000
--- a/arch/arm/configs/mainstone_defconfig
+++ /dev/null
@@ -1,794 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc1-bk2
-# Sat Mar 26 20:00:45 2005
-#
-CONFIG_ARM=y
-CONFIG_MMU=y
-CONFIG_UID16=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_IOMAP=y
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
-CONFIG_BROKEN_ON_SMP=y
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
-# CONFIG_IKCONFIG is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODULE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
-
-#
-# System Type
-#
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_IOP3XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_L7200 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
-
-#
-# Intel PXA2xx Implementations
-#
-# CONFIG_ARCH_LUBBOCK is not set
-CONFIG_MACH_MAINSTONE=y
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-CONFIG_PXA27x=y
-CONFIG_IWMMXT=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_MINICACHE=y
-
-#
-# Processor Features
-#
-# CONFIG_ARM_THUMB is not set
-CONFIG_XSCALE_PMU=y
-
-#
-# Bus support
-#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-# CONFIG_PREEMPT is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_TIMER=y
-CONFIG_LEDS_CPU=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M"
-# CONFIG_XIP_KERNEL is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-# CONFIG_ARTHUR is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
-# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-# CONFIG_MTD_CFI_I1 is not set
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_EDB7312 is not set
-# CONFIG_MTD_SHARP_SL is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
-# CONFIG_MTD_NAND is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_FD is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_CDROM_PKTCDVD is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-# CONFIG_BLK_DEV_IDECD is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_IDE_ARM is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_SCSI is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_PACKET is not set
-# CONFIG_NETLINK_DEV is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_IP_TCPDIAG=y
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_SMC91X=y
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_NVRAM is not set
-# CONFIG_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-CONFIG_FB=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SOFT_CURSOR=y
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_VIRTUAL is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-
-#
-# Logo configuration
-#
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-
-#
-# XFS support
-#
-# CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-# CONFIG_VFAT_FS is not set
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
-# CONFIG_TMPFS is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-# CONFIG_JFFS2_FS_NAND is not set
-# CONFIG_JFFS2_FS_NOR_ECC is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_FS is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-# CONFIG_CRYPTO is not set
-
-#
-# Hardware crypto devices
-#
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/arm/configs/palmz72_defconfig b/arch/arm/configs/palmz72_defconfig
deleted file mode 100644
index 6d162b1..0000000
--- a/arch/arm/configs/palmz72_defconfig
+++ /dev/null
@@ -1,950 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc4
-# Sun Aug 24 02:29:27 2008
-#
-CONFIG_ARM=y
-CONFIG_HAVE_PWM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
-CONFIG_ZONE_DMA=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
-# CONFIG_GROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-# CONFIG_EMBEDDED is not set
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-# CONFIG_HAVE_IOREMAP_PROT is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-# CONFIG_HAVE_DMA_ATTRS is not set
-# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-CONFIG_HAVE_CLK=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM7X00A is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_MACH_TRIZEPS4 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_PCM027 is not set
-CONFIG_ARCH_PXA_PALM=y
-# CONFIG_MACH_PALMTX is not set
-CONFIG_MACH_PALMZ72=y
-# CONFIG_PXA_EZX is not set
-CONFIG_PXA27x=y
-CONFIG_PXA_PWM=y
-
-#
-# Boot options
-#
-
-#
-# Power management
-#
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=32M console=tty root=/dev/mmcblk0"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Frequency scaling
-#
-# CONFIG_CPU_FREQ is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_APM_EMULATION=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-# CONFIG_MTD is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-# CONFIG_NETDEVICES is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_PXA27x=y
-# CONFIG_KEYBOARD_GPIO is not set
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_PXA is not set
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_CHARDEV is not set
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-CONFIG_SPI=y
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_BITBANG is not set
-# CONFIG_SPI_PXA2XX is not set
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_EEPROM_AT25 is not set
-CONFIG_SPI_SPIDEV=y
-# CONFIG_SPI_TLE62X0 is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_W1 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-CONFIG_PDA_POWER=y
-# CONFIG_APM_POWER is not set
-# CONFIG_BATTERY_DS2760 is not set
-# CONFIG_HWMON is not set
-# CONFIG_WATCHDOG is not set
-
-#
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_SMARTPANEL is not set
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_W100 is not set
-# CONFIG_FB_AM200EPD is not set
-# CONFIG_FB_VIRTUAL is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_CORGI is not set
-CONFIG_BACKLIGHT_PWM=y
-
-#
-# Display device support
-#
-CONFIG_DISPLAY_SUPPORT=y
-
-#
-# Display hardware drivers
-#
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-# CONFIG_FONT_8x16 is not set
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_LOGO is not set
-# CONFIG_SOUND is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_MMC=y
-CONFIG_MMC_DEBUG=y
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD Host Controller Drivers
-#
-CONFIG_MMC_PXA=y
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_SPI is not set
-# CONFIG_NEW_LEDS is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_SA1100=y
-# CONFIG_DMADEVICES is not set
-
-#
-# Voltage and Current regulators
-#
-# CONFIG_REGULATOR is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_UIO is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY is not set
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=866
-CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-CONFIG_NLS_CODEPAGE_866=y
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=y
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_MEMORY_INIT=y
-CONFIG_FRAME_POINTER=y
-# CONFIG_LATENCYTOP is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_HAVE_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-# CONFIG_FTRACE is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-CONFIG_DEBUG_USER=y
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-CONFIG_CRC_T10DIF=y
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig
deleted file mode 100644
index fa153f2..0000000
--- a/arch/arm/configs/pcm027_defconfig
+++ /dev/null
@@ -1,1095 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.24-rc6
-# Fri Dec 21 10:52:09 2007
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
-CONFIG_FAIR_GROUP_SCHED=y
-CONFIG_FAIR_USER_SCHED=y
-# CONFIG_FAIR_CGROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-# CONFIG_KALLSYMS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-# CONFIG_BLK_DEV_BSG is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-CONFIG_DEFAULT_NOOP=y
-CONFIG_DEFAULT_IOSCHED="noop"
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_MACH_TRIZEPS4 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_ARMCORE is not set
-CONFIG_MACH_PCM027=y
-CONFIG_MACH_PCM990_BASEBOARD=y
-CONFIG_PXA27x=y
-
-#
-# Boot options
-#
-
-#
-# Power management
-#
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE=""
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-CONFIG_SUSPEND_UP_POSSIBLE=y
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x00000000
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=0
-# CONFIG_MTD_PXA2XX is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_SHARP_SL is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-# CONFIG_BLK_DEV is not set
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-# CONFIG_SCSI_LOWLEVEL is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NETDEVICES_MULTIQUEUE is not set
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_AX88796 is not set
-CONFIG_SMC91X=y
-# CONFIG_DM9000 is not set
-# CONFIG_SMC911X is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_B44 is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_NVRAM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-
-#
-# I2C Algorithms
-#
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
-
-#
-# I2C Hardware Bus support
-#
-# CONFIG_I2C_GPIO is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_SIMTEC is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
-# CONFIG_DS1682 is not set
-CONFIG_EEPROM_LEGACY=y
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
-# CONFIG_WATCHDOG is not set
-
-#
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_SM501 is not set
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-
-#
-# Sound
-#
-CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-# CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-
-#
-# Generic devices
-#
-CONFIG_SND_AC97_CODEC=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-
-#
-# ALSA ARM devices
-#
-CONFIG_SND_PXA2XX_PCM=y
-CONFIG_SND_PXA2XX_AC97=y
-
-#
-# USB devices
-#
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_CAIAQ is not set
-
-#
-# System on Chip audio support
-#
-# CONFIG_SND_SOC is not set
-
-#
-# SoC Audio support for SuperH
-#
-
-#
-# Open Sound System
-#
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-# CONFIG_USB_MON is not set
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-
-#
-# MMC/SD Host Controller Drivers
-#
-CONFIG_MMC_PXA=y
-# CONFIG_NEW_LEDS is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-CONFIG_RTC_DRV_PCF8563=m
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-
-#
-# SPI RTC drivers
-#
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_SA1100=m
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=m
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=m
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=m
-CONFIG_FS_MBCACHE=m
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_INOTIFY is not set
-# CONFIG_QUOTA is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=850
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-CONFIG_NFS_DIRECTIO=y
-# CONFIG_NFSD is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_BIND34 is not set
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-15"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-CONFIG_NLS_CODEPAGE_850=y
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=y
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-# CONFIG_DLM is not set
-# CONFIG_INSTRUMENTATION is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_SAMPLES is not set
-# CONFIG_DEBUG_USER is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-# CONFIG_CRYPTO is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/pxa255-idp_defconfig b/arch/arm/configs/pxa255-idp_defconfig
deleted file mode 100644
index 3365c5d..0000000
--- a/arch/arm/configs/pxa255-idp_defconfig
+++ /dev/null
@@ -1,796 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.12-rc1-bk2
-# Sun Mar 27 22:20:17 2005
-#
-CONFIG_ARM=y
-CONFIG_MMU=y
-CONFIG_UID16=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_GENERIC_IOMAP=y
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_CLEAN_COMPILE=y
-CONFIG_BROKEN_ON_SMP=y
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-CONFIG_SYSCTL=y
-# CONFIG_AUDIT is not set
-CONFIG_HOTPLUG=y
-CONFIG_KOBJECT_UEVENT=y
-# CONFIG_IKCONFIG is not set
-# CONFIG_EMBEDDED is not set
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SHMEM=y
-CONFIG_CC_ALIGN_FUNCTIONS=0
-CONFIG_CC_ALIGN_LABELS=0
-CONFIG_CC_ALIGN_LOOPS=0
-CONFIG_CC_ALIGN_JUMPS=0
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-# CONFIG_MODULE_UNLOAD is not set
-CONFIG_OBSOLETE_MODPARM=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-# CONFIG_KMOD is not set
-
-#
-# System Type
-#
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_IOP3XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_L7200 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_H720X is not set
-
-#
-# Intel PXA2xx Implementations
-#
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_MAINSTONE is not set
-CONFIG_ARCH_PXA_IDP=y
-# CONFIG_PXA_SHARPSL is not set
-CONFIG_PXA25x=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_MINICACHE=y
-
-#
-# Processor Features
-#
-# CONFIG_ARM_THUMB is not set
-CONFIG_XSCALE_PMU=y
-
-#
-# Bus support
-#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-# CONFIG_PREEMPT is not set
-CONFIG_LEDS=y
-CONFIG_LEDS_TIMER=y
-CONFIG_LEDS_CPU=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs ip=dhcp console=ttyS0,115200 mem=64M"
-# CONFIG_XIP_KERNEL is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-# CONFIG_ARTHUR is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-
-#
-# Memory Technology Devices (MTD)
-#
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-# CONFIG_MTD_CFI_I1 is not set
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PHYSMAP is not set
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_EDB7312 is not set
-# CONFIG_MTD_SHARP_SL is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLKMTD is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-
-#
-# NAND Flash Device Drivers
-#
-# CONFIG_MTD_NAND is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_FD is not set
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_RAM is not set
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_INITRAMFS_SOURCE=""
-# CONFIG_CDROM_PKTCDVD is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=y
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
-# CONFIG_BLK_DEV_IDECD is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_IDE_GENERIC is not set
-# CONFIG_IDE_ARM is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_IDEDMA_AUTO is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_SCSI is not set
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Networking support
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-# CONFIG_PACKET is not set
-# CONFIG_NETLINK_DEV is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_IP_TCPDIAG=y
-# CONFIG_IP_TCPDIAG_IPV6 is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETFILTER is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_NET_DIVERT is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-# CONFIG_NET_CLS_ROUTE is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_SMC91X=y
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN (non-hamradio)
-#
-# CONFIG_NET_RADIO is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_TSDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-CONFIG_SOUND_GAMEPORT=y
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-# CONFIG_WATCHDOG is not set
-# CONFIG_NVRAM is not set
-# CONFIG_RTC is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-
-#
-# Ftape, the floppy tape device driver
-#
-# CONFIG_DRM is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-# CONFIG_I2C is not set
-
-#
-# Misc devices
-#
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-
-#
-# Graphics support
-#
-CONFIG_FB=y
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-CONFIG_FB_SOFT_CURSOR=y
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_VIRTUAL is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-
-#
-# Logo configuration
-#
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Sound
-#
-# CONFIG_SOUND is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB is not set
-
-#
-# USB Gadget Support
-#
-# CONFIG_USB_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-# CONFIG_MMC is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_JBD is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-
-#
-# XFS support
-#
-# CONFIG_XFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-# CONFIG_VFAT_FS is not set
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_SYSFS=y
-# CONFIG_DEVFS_FS is not set
-# CONFIG_DEVPTS_FS_XATTR is not set
-# CONFIG_TMPFS is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_JFFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-# CONFIG_JFFS2_FS_NAND is not set
-# CONFIG_JFFS2_FS_NOR_ECC is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-# CONFIG_NFS_V3 is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFS_DIRECTIO is not set
-# CONFIG_NFSD is not set
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_DEBUG_KERNEL=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_FS is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-
-#
-# Cryptographic options
-#
-# CONFIG_CRYPTO is not set
-
-#
-# Hardware crypto devices
-#
-
-#
-# Library routines
-#
-# CONFIG_CRC_CCITT is not set
-CONFIG_CRC32=y
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
diff --git a/arch/arm/configs/pxa2xx_defconfig b/arch/arm/configs/pxa2xx_defconfig
new file mode 100644
index 0000000..45d75f8
--- /dev/null
+++ b/arch/arm/configs/pxa2xx_defconfig
@@ -0,0 +1,3408 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.35-rc1
+# Sat Jun  5 13:32:23 2010
+#
+CONFIG_ARM=y
+CONFIG_HAVE_PWM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+# CONFIG_TREE_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
+CONFIG_TINY_RCU=y
+# CONFIG_TREE_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=13
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+# CONFIG_RD_LZO is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_KRETPROBES=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+# CONFIG_SLOW_WORK_DEBUG is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+CONFIG_BLK_DEV_BSG=y
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+
+#
+# Intel/Marvell Dev Platforms (sorted by hardware release time)
+#
+CONFIG_ARCH_LUBBOCK=y
+CONFIG_MACH_MAINSTONE=y
+# CONFIG_MACH_ZYLONITE300 is not set
+# CONFIG_MACH_ZYLONITE320 is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
+
+#
+# Third Party Dev Platforms (sorted by vendor name)
+#
+CONFIG_ARCH_PXA_IDP=y
+CONFIG_ARCH_VIPER=y
+CONFIG_MACH_ARCOM_ZEUS=y
+# CONFIG_MACH_BALLOON3 is not set
+# CONFIG_MACH_CSB726 is not set
+CONFIG_MACH_ARMCORE=y
+CONFIG_MACH_EM_X270=y
+CONFIG_MACH_EXEDA=y
+# CONFIG_MACH_CM_X300 is not set
+# CONFIG_MACH_CAPC7117 is not set
+CONFIG_ARCH_GUMSTIX=y
+CONFIG_GUMSTIX_AM200EPD=y
+# CONFIG_GUMSTIX_AM300EPD is not set
+CONFIG_MACH_INTELMOTE2=y
+# CONFIG_MACH_STARGATE2 is not set
+CONFIG_MACH_XCEP=y
+CONFIG_TRIZEPS_PXA=y
+CONFIG_MACH_TRIZEPS4=y
+# CONFIG_MACH_TRIZEPS4WL is not set
+CONFIG_MACH_TRIZEPS_CONXS=y
+# CONFIG_MACH_TRIZEPS_UCONXS is not set
+# CONFIG_MACH_TRIZEPS_ANY is not set
+CONFIG_ARCOM_PCMCIA=y
+CONFIG_TRIZEPS_PCMCIA=y
+CONFIG_MACH_LOGICPD_PXA270=y
+CONFIG_MACH_PCM027=y
+CONFIG_MACH_PCM990_BASEBOARD=y
+CONFIG_PCM990_DISPLAY_SHARP=y
+# CONFIG_PCM990_DISPLAY_NEC is not set
+# CONFIG_PCM990_DISPLAY_NONE is not set
+CONFIG_MACH_COLIBRI=y
+# CONFIG_MACH_COLIBRI_PXA270_EVALBOARD is not set
+# CONFIG_MACH_COLIBRI_PXA270_INCOME is not set
+# CONFIG_MACH_COLIBRI300 is not set
+# CONFIG_MACH_COLIBRI320 is not set
+# CONFIG_MACH_VPAC270 is not set
+
+#
+# End-user Products (sorted by vendor name)
+#
+CONFIG_MACH_H4700=y
+CONFIG_MACH_H5000=y
+# CONFIG_MACH_HIMALAYA is not set
+CONFIG_MACH_MAGICIAN=y
+# CONFIG_MACH_MIOA701 is not set
+CONFIG_PXA_EZX=y
+CONFIG_MACH_EZX_A780=y
+CONFIG_MACH_EZX_E680=y
+CONFIG_MACH_EZX_A1200=y
+CONFIG_MACH_EZX_A910=y
+CONFIG_MACH_EZX_E6=y
+CONFIG_MACH_EZX_E2=y
+# CONFIG_MACH_MP900C is not set
+CONFIG_ARCH_PXA_PALM=y
+CONFIG_MACH_PALMTE2=y
+CONFIG_MACH_PALMTC=y
+CONFIG_MACH_PALMT5=y
+CONFIG_MACH_PALMTX=y
+CONFIG_MACH_PALMZ72=y
+CONFIG_MACH_PALMLD=y
+CONFIG_PALM_TREO=y
+CONFIG_MACH_CENTRO=y
+CONFIG_MACH_TREO680=y
+# CONFIG_MACH_RAUMFELD_RC is not set
+# CONFIG_MACH_RAUMFELD_CONNECTOR is not set
+# CONFIG_MACH_RAUMFELD_SPEAKER is not set
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_MACH_ICONTROL is not set
+CONFIG_ARCH_PXA_ESERIES=y
+CONFIG_MACH_E330=y
+CONFIG_MACH_E350=y
+CONFIG_MACH_E740=y
+CONFIG_MACH_E750=y
+CONFIG_MACH_E400=y
+CONFIG_MACH_E800=y
+# CONFIG_MACH_ZIPIT2 is not set
+CONFIG_PXA25x=y
+CONFIG_PXA27x=y
+CONFIG_PXA_HAVE_BOARD_IRQS=y
+CONFIG_PXA_HAVE_ISA_IRQS=y
+CONFIG_PXA_SSP=y
+CONFIG_PLAT_PXA=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+CONFIG_CPU_HAS_PMU=y
+CONFIG_SA1111=y
+CONFIG_DMABOUNCE=y
+CONFIG_COMMON_CLKDEV=y
+CONFIG_FORCE_MAX_ZONEORDER=9
+
+#
+# Bus support
+#
+CONFIG_ISA=y
+CONFIG_PCI=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCI_HOST_ITE8152=y
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+CONFIG_PCCARD=m
+CONFIG_PCMCIA=m
+CONFIG_PCMCIA_LOAD_CIS=y
+CONFIG_CARDBUS=y
+
+#
+# PC-card bridges
+#
+CONFIG_YENTA=m
+CONFIG_YENTA_O2=y
+CONFIG_YENTA_RICOH=y
+CONFIG_YENTA_TI=y
+CONFIG_YENTA_ENE_TUNE=y
+CONFIG_YENTA_TOSHIBA=y
+# CONFIG_PD6729 is not set
+# CONFIG_I82092 is not set
+# CONFIG_I82365 is not set
+# CONFIG_TCIC is not set
+CONFIG_PCMCIA_SOC_COMMON=m
+CONFIG_PCMCIA_PXA2XX=m
+# CONFIG_PCMCIA_DEBUG is not set
+CONFIG_PCMCIA_PROBE=y
+CONFIG_PCCARD_NONSTATIC=y
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_LEDS=y
+CONFIG_LEDS_CPU=y
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_DEBUG=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=m
+CONFIG_CPU_FREQ_GOV_USERSPACE=m
+CONFIG_CPU_FREQ_GOV_ONDEMAND=m
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
+CONFIG_CPU_FREQ_PXA=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+CONFIG_FPE_NWFPE_XP=y
+CONFIG_FPE_FASTFPE=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=m
+CONFIG_BINFMT_MISC=m
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_OPS=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=m
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETLABEL is not set
+# CONFIG_NETWORK_SECMARK is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CT_ACCT=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+# CONFIG_NF_CT_PROTO_DCCP is not set
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+# CONFIG_NETFILTER_TPROXY is not set
+CONFIG_NETFILTER_XTABLES=m
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+
+#
+# Xtables targets
+#
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_CT is not set
+# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
+CONFIG_NETFILTER_XT_TARGET_HL=m
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
+# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
+# CONFIG_NETFILTER_XT_TARGET_TEE is not set
+# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
+
+#
+# Xtables matches
+#
+# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+# CONFIG_NETFILTER_XT_MATCH_OSF is not set
+# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_ADDRTYPE=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_NF_NAT_SNMP_BASIC=m
+CONFIG_NF_NAT_PROTO_GRE=m
+CONFIG_NF_NAT_PROTO_UDPLITE=m
+CONFIG_NF_NAT_PROTO_SCTP=m
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+CONFIG_NF_NAT_TFTP=m
+CONFIG_NF_NAT_AMANDA=m
+CONFIG_NF_NAT_PPTP=m
+CONFIG_NF_NAT_H323=m
+CONFIG_NF_NAT_SIP=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+# CONFIG_IP_NF_SECURITY is not set
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+# CONFIG_IP6_NF_SECURITY is not set
+# CONFIG_BRIDGE_NF_EBTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+CONFIG_STP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+# CONFIG_NET_DSA is not set
+CONFIG_VLAN_8021Q=m
+# CONFIG_VLAN_8021Q_GVRP is not set
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+CONFIG_IEEE802154=y
+# CONFIG_NET_SCHED is not set
+CONFIG_NET_CLS_ROUTE=y
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_IRDA=m
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=m
+CONFIG_IRNET=m
+CONFIG_IRCOMM=m
+CONFIG_IRDA_ULTRA=y
+
+#
+# IrDA options
+#
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRDA_FAST_RR=y
+CONFIG_IRDA_DEBUG=y
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+CONFIG_IRTTY_SIR=m
+
+#
+# Dongle support
+#
+# CONFIG_DONGLE is not set
+# CONFIG_KINGSUN_DONGLE is not set
+# CONFIG_KSDAZZLE_DONGLE is not set
+# CONFIG_KS959_DONGLE is not set
+
+#
+# FIR device drivers
+#
+# CONFIG_USB_IRDA is not set
+# CONFIG_SIGMATEL_FIR is not set
+# CONFIG_TOSHIBA_FIR is not set
+# CONFIG_VLSI_FIR is not set
+CONFIG_PXA_FICP=m
+# CONFIG_MCS_FIR is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+# CONFIG_BT_L2CAP_EXT_FEATURES is not set
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIBTSDIO=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+# CONFIG_BT_HCIUART_LL is not set
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+# CONFIG_BT_HCIDTL1 is not set
+# CONFIG_BT_HCIBT3C is not set
+# CONFIG_BT_HCIBLUECARD is not set
+# CONFIG_BT_HCIBTUART is not set
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+# CONFIG_BT_ATH3K is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_WEXT_PRIV=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=y
+CONFIG_LIB80211_CRYPT_WEP=y
+CONFIG_LIB80211_CRYPT_CCMP=y
+CONFIG_LIB80211_CRYPT_TKIP=y
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_RC_MINSTREL=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_REDBOOT_PARTS=y
+CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
+CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
+CONFIG_MTD_REDBOOT_PARTS_READONLY=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_AFS_PARTS=y
+CONFIG_MTD_AR7_PARTS=y
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_HAVE_MTD_OTP=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_OTP=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+# CONFIG_MTD_XIP is not set
+
+#
+# Mapping drivers for chip access
+#
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+CONFIG_MTD_PXA2XX=y
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_PCI is not set
+# CONFIG_MTD_PCMCIA is not set
+# CONFIG_MTD_GPIO_ADDR is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+CONFIG_MTD_BLOCK2MTD=y
+
+#
+# Disk-On-Chip Device Drivers
+#
+CONFIG_MTD_DOC2000=y
+CONFIG_MTD_DOC2001=y
+CONFIG_MTD_DOC2001PLUS=y
+CONFIG_MTD_DOCPROBE=y
+CONFIG_MTD_DOCECC=y
+CONFIG_MTD_DOCPROBE_ADVANCED=y
+CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000
+CONFIG_MTD_DOCPROBE_HIGH=y
+# CONFIG_MTD_DOCPROBE_55AA is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_DENALI is not set
+CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018
+# CONFIG_MTD_NAND_H1900 is not set
+CONFIG_MTD_NAND_GPIO=m
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_RICOH is not set
+CONFIG_MTD_NAND_DISKONCHIP=y
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
+CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
+CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
+# CONFIG_MTD_NAND_SHARPSL is not set
+# CONFIG_MTD_NAND_CAFE is not set
+CONFIG_MTD_NAND_CM_X270=y
+CONFIG_MTD_NAND_TMIO=m
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ALAUDA is not set
+CONFIG_MTD_ONENAND=y
+# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
+# CONFIG_MTD_ONENAND_GENERIC is not set
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+# CONFIG_PNP is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_DRBD is not set
+CONFIG_BLK_DEV_NBD=y
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=8
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=m
+# CONFIG_EEPROM_AT25 is not set
+CONFIG_EEPROM_LEGACY=y
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
+# CONFIG_IWMC3200TOP is not set
+CONFIG_HAVE_IDE=y
+CONFIG_IDE=y
+
+#
+# Please see Documentation/ide/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+CONFIG_IDE_GD=y
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
+CONFIG_BLK_DEV_IDECS=m
+# CONFIG_BLK_DEV_DELKIN is not set
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_IDE_TASK_IOCTL is not set
+CONFIG_IDE_PROC_FS=y
+
+#
+# IDE chipset support/bugfixes
+#
+# CONFIG_BLK_DEV_PLATFORM is not set
+
+#
+# PCI IDE chipsets support
+#
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+# CONFIG_BLK_DEV_PIIX is not set
+# CONFIG_BLK_DEV_IT8172 is not set
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SL82C105 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+# CONFIG_BLK_DEV_IDEDMA is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=m
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=m
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AHA152X is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_IN2000 is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_FCOE is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_DTC3280 is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GENERIC_NCR5380 is not set
+# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_NCR53C406A is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_PAS16 is not set
+# CONFIG_SCSI_QLOGIC_FAS is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_SYM53C416 is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_T128 is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_BFA_FC is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_PXA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PALMLD is not set
+CONFIG_PATA_PCMCIA=m
+CONFIG_PATA_PLATFORM=m
+# CONFIG_PATA_QDI is not set
+# CONFIG_PATA_RZ1000 is not set
+# CONFIG_PATA_WINBOND_VLB is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# You can enable one or both FireWire driver stacks.
+#
+
+#
+# The newer stack is recommended.
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+CONFIG_SMC91X=y
+CONFIG_DM9000=y
+CONFIG_DM9000_DEBUGLEVEL=4
+# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
+# CONFIG_ENC28J60 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_DNET is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+CONFIG_NET_PCI=y
+# CONFIG_PCNET32 is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_AC3200 is not set
+# CONFIG_KSZ884X_PCI is not set
+# CONFIG_APRICOT is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+# CONFIG_NE2K_PCI is not set
+# CONFIG_8139CP is not set
+CONFIG_8139TOO=m
+CONFIG_8139TOO_PIO=y
+# CONFIG_8139TOO_TUNE_TWISTER is not set
+# CONFIG_8139TOO_8129 is not set
+# CONFIG_8139_OLD_RX_RESET is not set
+# CONFIG_R6040 is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SMSC9420 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+# CONFIG_ATL2 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+CONFIG_CHELSIO_T3_DEPENDS=y
+# CONFIG_CHELSIO_T3 is not set
+CONFIG_CHELSIO_T4_DEPENDS=y
+# CONFIG_CHELSIO_T4 is not set
+# CONFIG_ENIC is not set
+# CONFIG_IXGBE is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_VXGE is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_NIU is not set
+# CONFIG_MLX4_EN is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TEHUTI is not set
+# CONFIG_BNX2X is not set
+# CONFIG_QLCNIC is not set
+# CONFIG_QLGE is not set
+# CONFIG_SFC is not set
+# CONFIG_BE2NET is not set
+# CONFIG_TR is not set
+CONFIG_WLAN=y
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+# CONFIG_ATH_COMMON is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+CONFIG_HOSTAP=y
+CONFIG_HOSTAP_FIRMWARE=y
+CONFIG_HOSTAP_FIRMWARE_NVRAM=y
+# CONFIG_HOSTAP_PLX is not set
+# CONFIG_HOSTAP_PCI is not set
+CONFIG_HOSTAP_CS=m
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWM is not set
+CONFIG_LIBERTAS=m
+# CONFIG_LIBERTAS_USB is not set
+# CONFIG_LIBERTAS_CS is not set
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_SPI is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_MESH is not set
+CONFIG_HERMES=m
+# CONFIG_HERMES_PRISM is not set
+CONFIG_HERMES_CACHE_FW_ON_INIT=y
+# CONFIG_PLX_HERMES is not set
+# CONFIG_TMD_HERMES is not set
+# CONFIG_NORTEL_HERMES is not set
+CONFIG_PCMCIA_HERMES=m
+CONFIG_PCMCIA_SPECTRUM=m
+# CONFIG_ORINOCO_USB is not set
+# CONFIG_P54_COMMON is not set
+CONFIG_RT2X00=m
+# CONFIG_RT2400PCI is not set
+# CONFIG_RT2500PCI is not set
+# CONFIG_RT61PCI is not set
+CONFIG_RT2800PCI_PCI=y
+# CONFIG_RT2800PCI is not set
+# CONFIG_RT2500USB is not set
+CONFIG_RT73USB=m
+# CONFIG_RT2800USB is not set
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+# CONFIG_WL12XX is not set
+# CONFIG_ZD1211RW is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+CONFIG_USB_PEGASUS=m
+# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+# CONFIG_USB_NET_CDC_EEM is not set
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_SMSC75XX is not set
+# CONFIG_USB_NET_SMSC95XX is not set
+# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_NET1080=m
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+# CONFIG_USB_NET_RNDIS_HOST is not set
+CONFIG_USB_NET_CDC_SUBSET=m
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_SIERRA_NET is not set
+CONFIG_NET_PCMCIA=y
+# CONFIG_PCMCIA_3C589 is not set
+# CONFIG_PCMCIA_3C574 is not set
+# CONFIG_PCMCIA_FMVJ18X is not set
+CONFIG_PCMCIA_PCNET=m
+# CONFIG_PCMCIA_NMCLAN is not set
+# CONFIG_PCMCIA_SMC91C92 is not set
+# CONFIG_PCMCIA_XIRC2PS is not set
+# CONFIG_PCMCIA_AXNET is not set
+# CONFIG_WAN is not set
+CONFIG_IEEE802154_DRIVERS=y
+# CONFIG_IEEE802154_FAKEHARD is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+# CONFIG_PPPOE is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_EVBUG is not set
+CONFIG_INPUT_APMPOWER=y
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+CONFIG_KEYBOARD_ATKBD=m
+# CONFIG_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+CONFIG_KEYBOARD_PXA27x=y
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_SERIAL=m
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_INPORT is not set
+# CONFIG_MOUSE_LOGIBM is not set
+# CONFIG_MOUSE_PC110PAD is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+CONFIG_TOUCHSCREEN_DA9034=y
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+CONFIG_TOUCHSCREEN_FUJITSU=m
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+CONFIG_TOUCHSCREEN_ELO=m
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+CONFIG_TOUCHSCREEN_MTOUCH=m
+CONFIG_TOUCHSCREEN_INEXIO=m
+# CONFIG_TOUCHSCREEN_MK712 is not set
+CONFIG_TOUCHSCREEN_HTCPEN=m
+CONFIG_TOUCHSCREEN_PENMOUNT=m
+CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
+CONFIG_TOUCHSCREEN_TOUCHWIN=m
+CONFIG_TOUCHSCREEN_UCB1400=m
+CONFIG_TOUCHSCREEN_WM97XX=m
+CONFIG_TOUCHSCREEN_WM9705=y
+CONFIG_TOUCHSCREEN_WM9712=y
+CONFIG_TOUCHSCREEN_WM9713=y
+# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+CONFIG_TOUCHSCREEN_TOUCHIT213=m
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+CONFIG_TOUCHSCREEN_PCAP=y
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=m
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+CONFIG_INPUT_PCAP=y
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_SA1111=m
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+# CONFIG_SERIAL_8250_CS is not set
+CONFIG_SERIAL_8250_NR_UARTS=7
+CONFIG_SERIAL_8250_RUNTIME_UARTS=7
+# CONFIG_SERIAL_8250_EXTENDED is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=m
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_DTLK is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_IPWIRELESS is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_PXA=y
+CONFIG_I2C_PXA_SLAVE=y
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_ELEKTOR is not set
+# CONFIG_I2C_PCA_ISA is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_PXA2XX=y
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_IT8761E is not set
+# CONFIG_GPIO_SCH is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+CONFIG_GPIO_PCA953X=y
+# CONFIG_GPIO_PCA953X_IRQ is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_CS5535 is not set
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_LANGWELL is not set
+# CONFIG_GPIO_RDC321X is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+# CONFIG_GPIO_UCB1400 is not set
+
+#
+# MODULbus GPIO expanders:
+#
+CONFIG_W1=y
+CONFIG_W1_CON=y
+
+#
+# 1-wire Bus Masters
+#
+# CONFIG_W1_MASTER_MATROX is not set
+# CONFIG_W1_MASTER_DS2490 is not set
+# CONFIG_W1_MASTER_DS2482 is not set
+CONFIG_W1_MASTER_DS1WM=y
+# CONFIG_W1_MASTER_GPIO is not set
+
+#
+# 1-wire Slaves
+#
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_DS2431 is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+CONFIG_W1_SLAVE_DS2760=y
+# CONFIG_W1_SLAVE_BQ27000 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+CONFIG_PDA_POWER=y
+# CONFIG_APM_POWER is not set
+# CONFIG_TEST_POWER is not set
+CONFIG_BATTERY_DS2760=y
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+CONFIG_BATTERY_DA9030=y
+# CONFIG_BATTERY_MAX17040 is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+CONFIG_SENSORS_ADM1021=m
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+CONFIG_SENSORS_LM75=m
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+CONFIG_SENSORS_MAX6650=m
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_SA1100_WATCHDOG=y
+# CONFIG_MAX63XX_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+
+#
+# ISA-based Watchdog Cards
+#
+# CONFIG_PCWATCHDOG is not set
+# CONFIG_MIXCOMWD is not set
+# CONFIG_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_MFD_SUPPORT=y
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+CONFIG_MFD_ASIC3=y
+CONFIG_HTC_EGPIO=y
+CONFIG_HTC_PASIC3=y
+# CONFIG_HTC_I2CPLD is not set
+CONFIG_UCB1400_CORE=m
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TC35892 is not set
+CONFIG_MFD_TMIO=y
+CONFIG_MFD_T7L66XB=y
+CONFIG_MFD_TC6387XB=y
+CONFIG_MFD_TC6393XB=y
+CONFIG_PMIC_DA903X=y
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_ABX500_CORE is not set
+CONFIG_EZX_PCAP=y
+# CONFIG_AB8500_CORE is not set
+# CONFIG_MFD_TIMBERDALE is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_DEBUG=y
+# CONFIG_REGULATOR_DUMMY is not set
+# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_USERSPACE_CONSUMER=y
+CONFIG_REGULATOR_BQ24022=y
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+CONFIG_REGULATOR_DA903X=y
+# CONFIG_REGULATOR_LP3971 is not set
+CONFIG_REGULATOR_PCAP=y
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2_COMMON=y
+CONFIG_VIDEO_ALLOW_V4L1=y
+CONFIG_VIDEO_V4L1_COMPAT=y
+# CONFIG_DVB_CORE is not set
+CONFIG_VIDEO_MEDIA=y
+
+#
+# Multimedia drivers
+#
+CONFIG_IR_CORE=y
+CONFIG_VIDEO_IR=y
+CONFIG_RC_MAP=y
+CONFIG_IR_NEC_DECODER=y
+CONFIG_IR_RC5_DECODER=y
+CONFIG_IR_RC6_DECODER=y
+CONFIG_IR_JVC_DECODER=y
+CONFIG_IR_SONY_DECODER=y
+# CONFIG_IR_IMON is not set
+# CONFIG_MEDIA_ATTACH is not set
+CONFIG_MEDIA_TUNER=y
+CONFIG_MEDIA_TUNER_CUSTOMISE=y
+CONFIG_MEDIA_TUNER_SIMPLE=m
+CONFIG_MEDIA_TUNER_TDA8290=m
+CONFIG_MEDIA_TUNER_TDA827X=m
+CONFIG_MEDIA_TUNER_TDA18271=m
+CONFIG_MEDIA_TUNER_TDA9887=m
+CONFIG_MEDIA_TUNER_TEA5761=m
+CONFIG_MEDIA_TUNER_TEA5767=m
+CONFIG_MEDIA_TUNER_MT20XX=m
+CONFIG_MEDIA_TUNER_MT2060=m
+CONFIG_MEDIA_TUNER_MT2266=m
+CONFIG_MEDIA_TUNER_MT2131=m
+CONFIG_MEDIA_TUNER_QT1010=m
+CONFIG_MEDIA_TUNER_XC2028=m
+CONFIG_MEDIA_TUNER_XC5000=m
+CONFIG_MEDIA_TUNER_MXL5005S=m
+CONFIG_MEDIA_TUNER_MXL5007T=m
+CONFIG_MEDIA_TUNER_MC44S803=m
+CONFIG_MEDIA_TUNER_MAX2165=m
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_V4L1=y
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_SG=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
+CONFIG_VIDEO_IR_I2C=y
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_BT848 is not set
+# CONFIG_VIDEO_PMS is not set
+# CONFIG_VIDEO_CPIA is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_STRADIS is not set
+# CONFIG_VIDEO_ZORAN is not set
+# CONFIG_VIDEO_SAA7134 is not set
+# CONFIG_VIDEO_MXB is not set
+# CONFIG_VIDEO_HEXIUM_ORION is not set
+# CONFIG_VIDEO_HEXIUM_GEMINI is not set
+# CONFIG_VIDEO_CX88 is not set
+# CONFIG_VIDEO_IVTV is not set
+# CONFIG_VIDEO_CAFE_CCIC is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+CONFIG_SOC_CAMERA_MT9M111=y
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9T112 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_RJ54N1 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+# CONFIG_SOC_CAMERA_OV9640 is not set
+CONFIG_VIDEO_PXA27x=y
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_USB_VIDEO_CLASS is not set
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_HDPVR is not set
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_VIDEO_CX231XX is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_VICAM is not set
+# CONFIG_USB_IBMCAM is not set
+# CONFIG_USB_KONICAWC is not set
+# CONFIG_USB_QUICKCAM_MESSENGER is not set
+# CONFIG_USB_ET61X251 is not set
+# CONFIG_VIDEO_OVCAMCHIP is not set
+# CONFIG_USB_OV511 is not set
+# CONFIG_USB_SE401 is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_STV680 is not set
+# CONFIG_USB_ZC0301 is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_RADIO_CADET is not set
+# CONFIG_RADIO_RTRACK is not set
+# CONFIG_RADIO_RTRACK2 is not set
+# CONFIG_RADIO_AZTECH is not set
+# CONFIG_RADIO_GEMTEK is not set
+# CONFIG_RADIO_GEMTEK_PCI is not set
+# CONFIG_RADIO_MAXIRADIO is not set
+# CONFIG_RADIO_MAESTRO is not set
+# CONFIG_RADIO_MIROPCM20 is not set
+# CONFIG_RADIO_SF16FMI is not set
+# CONFIG_RADIO_SF16FMR2 is not set
+# CONFIG_RADIO_TERRATEC is not set
+# CONFIG_RADIO_TRUST is not set
+# CONFIG_RADIO_TYPHOON is not set
+# CONFIG_RADIO_ZOLTRIX is not set
+# CONFIG_I2C_SI4713 is not set
+# CONFIG_RADIO_SI4713 is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_RADIO_SI470X is not set
+# CONFIG_USB_MR800 is not set
+CONFIG_RADIO_TEA5764=y
+CONFIG_RADIO_TEA5764_XTAL=y
+# CONFIG_RADIO_SAA7706H is not set
+# CONFIG_RADIO_TEF6862 is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+CONFIG_FB_SYS_FILLRECT=m
+CONFIG_FB_SYS_COPYAREA=m
+CONFIG_FB_SYS_IMAGEBLIT=m
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+CONFIG_FB_SYS_FOPS=m
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_VIA is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+CONFIG_FB_PXA=m
+CONFIG_FB_PXA_OVERLAY=y
+# CONFIG_FB_PXA_SMARTPANEL is not set
+CONFIG_FB_PXA_PARAMETERS=y
+CONFIG_FB_MBX=m
+# CONFIG_FB_MBX_DEBUG is not set
+CONFIG_FB_W100=y
+# CONFIG_FB_TMIO is not set
+CONFIG_FB_VIRTUAL=m
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=m
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+CONFIG_LCD_TDO24M=m
+# CONFIG_LCD_VGG2432A4 is not set
+# CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_S6E63M0 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=m
+CONFIG_BACKLIGHT_GENERIC=m
+CONFIG_BACKLIGHT_PWM=m
+CONFIG_BACKLIGHT_DA903X=m
+# CONFIG_BACKLIGHT_ADP8860 is not set
+
+#
+# Display device support
+#
+CONFIG_DISPLAY_SUPPORT=y
+
+#
+# Display hardware drivers
+#
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_MDA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=m
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+CONFIG_FONT_MINI_4x6=y
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+CONFIG_SOUND=m
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=m
+CONFIG_SND_TIMER=m
+CONFIG_SND_PCM=m
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_JACK=y
+CONFIG_SND_SEQUENCER=m
+# CONFIG_SND_SEQ_DUMMY is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_SEQUENCER_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+CONFIG_SND_DYNAMIC_MINORS=y
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_DEBUG=y
+# CONFIG_SND_DEBUG_VERBOSE is not set
+# CONFIG_SND_PCM_XRUN_DEBUG is not set
+CONFIG_SND_VMASTER=y
+CONFIG_SND_RAWMIDI_SEQ=m
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_AC97_CODEC=m
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_VIRMIDI is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_AC97_POWER_SAVE is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_CTXFI is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_INDIGOIOX is not set
+# CONFIG_SND_INDIGODJX is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_HIFIER is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_LX6464ES is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_PXA2XX_PCM=m
+CONFIG_SND_PXA2XX_LIB=m
+CONFIG_SND_PXA2XX_LIB_AC97=y
+CONFIG_SND_PXA2XX_AC97=m
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_PCMCIA=y
+# CONFIG_SND_VXPOCKET is not set
+# CONFIG_SND_PDAUDIOCF is not set
+CONFIG_SND_SOC=m
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_PXA2XX_SOC=m
+CONFIG_SND_PXA2XX_SOC_AC97=m
+# CONFIG_SND_PXA2XX_SOC_E740 is not set
+# CONFIG_SND_PXA2XX_SOC_E750 is not set
+CONFIG_SND_PXA2XX_SOC_E800=m
+CONFIG_SND_PXA2XX_SOC_EM_X270=m
+# CONFIG_SND_PXA2XX_SOC_PALM27X is not set
+# CONFIG_SND_PXA2XX_SOC_MAGICIAN is not set
+# CONFIG_SND_PXA2XX_SOC_IMOTE2 is not set
+CONFIG_SND_SOC_I2C_AND_SPI=m
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM9712=m
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=m
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=m
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# USB HID Boot Protocol drivers
+#
+# CONFIG_USB_KBD is not set
+# CONFIG_USB_MOUSE is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_3M_PCT is not set
+CONFIG_HID_A4TECH=m
+CONFIG_HID_APPLE=m
+CONFIG_HID_BELKIN=m
+# CONFIG_HID_CANDO is not set
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+# CONFIG_HID_PRODIKEYS is not set
+CONFIG_HID_CYPRESS=m
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EGALAX is not set
+CONFIG_HID_EZKEY=m
+# CONFIG_HID_KYE is not set
+CONFIG_HID_GYRATION=m
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+CONFIG_HID_LOGITECH=m
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGIG940_FF is not set
+# CONFIG_HID_MAGICMOUSE is not set
+CONFIG_HID_MICROSOFT=m
+# CONFIG_HID_MOSART is not set
+CONFIG_HID_MONTEREY=m
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+CONFIG_HID_PANTHERLORD=m
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=m
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_KONE is not set
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+# CONFIG_HID_STANTUM is not set
+CONFIG_HID_SUNPLUS=m
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=m
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_SUSPEND=y
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+CONFIG_USB_MON=m
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+CONFIG_USB_ISP116X_HCD=m
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=m
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+CONFIG_USB_SL811_HCD=m
+# CONFIG_USB_SL811_CS is not set
+CONFIG_USB_R8A66597_HCD=m
+# CONFIG_USB_WHCI_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=m
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=m
+# CONFIG_USB_EZUSB is not set
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+CONFIG_USB_SERIAL_MCT_U232=m
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+# CONFIG_USB_SERIAL_QUALCOMM is not set
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+CONFIG_USB_GADGET=m
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+CONFIG_USB_GADGET_PXA27X=y
+CONFIG_USB_PXA27X=m
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+CONFIG_USB_GADGETFS=m
+# CONFIG_USB_FUNCTIONFS is not set
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_MASS_STORAGE is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_USB_G_PRINTER=m
+CONFIG_USB_CDC_COMPOSITE=m
+# CONFIG_USB_G_NOKIA is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_WEBCAM is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+CONFIG_USB_GPIO_VBUS=m
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_UWB is not set
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=m
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_TIFM_SD is not set
+CONFIG_MMC_SPI=y
+# CONFIG_MMC_SDRICOH_CS is not set
+CONFIG_MMC_TMIO=y
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=m
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GPIO_PLATFORM=y
+CONFIG_LEDS_LP3944=m
+# CONFIG_LEDS_PCA955X is not set
+CONFIG_LEDS_DA903X=m
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_PWM is not set
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=m
+# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_GPIO=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=m
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=m
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+CONFIG_RTC_DRV_ISL1208=m
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_DRV_PCF8563=m
+CONFIG_RTC_DRV_PCF8583=m
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+CONFIG_RTC_DRV_V3020=m
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=m
+CONFIG_RTC_DRV_PXA=m
+CONFIG_RTC_DRV_PCAP=m
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+# CONFIG_TIMB_DMA is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+CONFIG_REISERFS_FS=m
+# CONFIG_REISERFS_CHECK is not set
+# CONFIG_REISERFS_PROC_INFO is not set
+CONFIG_REISERFS_FS_XATTR=y
+CONFIG_REISERFS_FS_POSIX_ACL=y
+CONFIG_REISERFS_FS_SECURITY=y
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_XFS_FS=m
+# CONFIG_XFS_QUOTA is not set
+# CONFIG_XFS_POSIX_ACL is not set
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+CONFIG_AUTOFS_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_CUSE=m
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=y
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+CONFIG_JFFS2_FS_SECURITY=y
+CONFIG_JFFS2_COMPRESSION_OPTIONS=y
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_LZO=y
+CONFIG_JFFS2_RTIME=y
+CONFIG_JFFS2_RUBIN=y
+# CONFIG_JFFS2_CMODE_NONE is not set
+CONFIG_JFFS2_CMODE_PRIORITY=y
+# CONFIG_JFFS2_CMODE_SIZE is not set
+# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=m
+# CONFIG_SQUASHFS_XATTRS is not set
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=m
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=m
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_EXPORTFS=m
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_CEPH_FS is not set
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+CONFIG_CIFS_WEAK_PW_HASH=y
+# CONFIG_CIFS_UPCALL is not set
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_DFS_UPCALL is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+CONFIG_LDM_PARTITION=y
+# CONFIG_LDM_DEBUG is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=m
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=m
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=m
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_LOCK_ALLOC=y
+CONFIG_PROVE_LOCKING=y
+# CONFIG_PROVE_RCU is not set
+CONFIG_LOCKDEP=y
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_LOCKDEP is not set
+CONFIG_TRACE_IRQFLAGS=y
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_KPROBES_SANITY_TEST is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_EARLY_PRINTK is not set
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITY=y
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_NETWORK is not set
+# CONFIG_SECURITY_PATH is not set
+# CONFIG_SECURITY_TOMOYO is not set
+# CONFIG_IMA is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=m
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=m
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=m
+# CONFIG_CRYPTO_CAMELLIA is not set
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=y
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+CONFIG_CRC_T10DIF=m
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=m
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_DEC16=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig
deleted file mode 100644
index 1e8f5a2..0000000
--- a/arch/arm/configs/trizeps4_defconfig
+++ /dev/null
@@ -1,1704 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.21
-# Mon Apr 30 21:23:20 2007
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ZONE_DMA=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# Code maturity level options
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-# CONFIG_IPC_NS is not set
-CONFIG_SYSVIPC_SYSCTL=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BSD_PROCESS_ACCT_V3=y
-# CONFIG_TASKSTATS is not set
-# CONFIG_UTS_NS is not set
-# CONFIG_AUDIT is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_SYSFS_DEPRECATED=y
-# CONFIG_RELAY is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SHMEM=y
-CONFIG_SLAB=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-# CONFIG_SLOB is not set
-
-#
-# Loadable module support
-#
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_KMOD=y
-
-#
-# Block layer
-#
-CONFIG_BLOCK=y
-CONFIG_LBD=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-CONFIG_LSF=y
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CO285 is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_OMAP is not set
-
-#
-# Intel PXA2xx Implementations
-#
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-CONFIG_TRIZEPS_PXA=y
-CONFIG_MACH_TRIZEPS4=y
-CONFIG_MACH_TRIZEPS4_CONXS=y
-# CONFIG_MACH_TRIZEPS4_ANY is not set
-CONFIG_PXA27x=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-
-#
-# Bus support
-#
-
-#
-# PCCARD (PCMCIA/CardBus) support
-#
-CONFIG_PCCARD=y
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=y
-# CONFIG_PCMCIA_LOAD_CIS is not set
-CONFIG_PCMCIA_IOCTL=y
-
-#
-# PC-card bridges
-#
-CONFIG_PCMCIA_PXA2XX=y
-
-#
-# Kernel Features
-#
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_LEDS=y
-CONFIG_LEDS_TIMER=y
-CONFIG_LEDS_CPU=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE="root=fe01 console=ttyS0,38400n8 loglevel=5"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-CONFIG_FPE_NWFPE_XP=y
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_LEGACY is not set
-# CONFIG_PM_DEBUG is not set
-# CONFIG_PM_SYSFS_DEPRECATED is not set
-# CONFIG_APM_EMULATION is not set
-
-#
-# Networking
-#
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-CONFIG_NET_KEY=y
-# CONFIG_NET_KEY_MIGRATE is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-
-#
-# IP: Virtual Server Configuration
-#
-# CONFIG_IP_VS is not set
-# CONFIG_IPV6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-# CONFIG_NETLABEL is not set
-# CONFIG_NETWORK_SECMARK is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-
-#
-# Core Netfilter Configuration
-#
-# CONFIG_NETFILTER_NETLINK is not set
-# CONFIG_NF_CONNTRACK_ENABLED is not set
-# CONFIG_NF_CONNTRACK is not set
-# CONFIG_NETFILTER_XTABLES is not set
-
-#
-# IP: Netfilter Configuration
-#
-CONFIG_IP_NF_QUEUE=m
-# CONFIG_IP_NF_IPTABLES is not set
-# CONFIG_IP_NF_ARPTABLES is not set
-
-#
-# DCCP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_DCCP is not set
-
-#
-# SCTP Configuration (EXPERIMENTAL)
-#
-# CONFIG_IP_SCTP is not set
-
-#
-# TIPC Configuration (EXPERIMENTAL)
-#
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-CONFIG_VLAN_8021Q=m
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-
-#
-# QoS and/or fair queueing
-#
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-CONFIG_IRDA=m
-
-#
-# IrDA protocols
-#
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-CONFIG_IRDA_ULTRA=y
-
-#
-# IrDA options
-#
-CONFIG_IRDA_CACHE_LAST_LSAP=y
-CONFIG_IRDA_FAST_RR=y
-# CONFIG_IRDA_DEBUG is not set
-
-#
-# Infrared-port device drivers
-#
-
-#
-# SIR device drivers
-#
-CONFIG_IRTTY_SIR=m
-
-#
-# Dongle support
-#
-# CONFIG_DONGLE is not set
-
-#
-# Old SIR device drivers
-#
-# CONFIG_IRPORT_SIR is not set
-
-#
-# Old Serial dongle support
-#
-
-#
-# FIR device drivers
-#
-# CONFIG_USB_IRDA is not set
-# CONFIG_SIGMATEL_FIR is not set
-# CONFIG_PXA_FICP is not set
-# CONFIG_MCS_FIR is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-# CONFIG_BT_HCIUSB is not set
-# CONFIG_BT_HCIUART is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIDTL1 is not set
-# CONFIG_BT_HCIBT3C is not set
-# CONFIG_BT_HCIBLUECARD is not set
-# CONFIG_BT_HCIBTUART is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-CONFIG_CFG80211=y
-CONFIG_WIRELESS_EXT=y
-CONFIG_IEEE80211=y
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=y
-CONFIG_IEEE80211_CRYPT_CCMP=m
-CONFIG_IEEE80211_CRYPT_TKIP=m
-CONFIG_IEEE80211_SOFTMAC=m
-# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-# CONFIG_SYS_HYPERVISOR is not set
-
-#
-# Connector - unified userspace <-> kernelspace linker
-#
-CONFIG_CONNECTOR=y
-CONFIG_PROC_EVENTS=y
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-# CONFIG_MTD_CFI_NOSWAP is not set
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_LE_BYTE_SWAP=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_OTP is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_OBSOLETE_CHIPS is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x0
-CONFIG_MTD_PHYSMAP_LEN=0x0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_IMPA7 is not set
-# CONFIG_MTD_SHARP_SL is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-CONFIG_MTD_BLOCK2MTD=y
-
-#
-# Disk-On-Chip Device Drivers
-#
-CONFIG_MTD_DOC2000=y
-CONFIG_MTD_DOC2001=y
-CONFIG_MTD_DOC2001PLUS=y
-CONFIG_MTD_DOCPROBE=y
-CONFIG_MTD_DOCECC=y
-CONFIG_MTD_DOCPROBE_ADVANCED=y
-CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000
-CONFIG_MTD_DOCPROBE_HIGH=y
-# CONFIG_MTD_DOCPROBE_55AA is not set
-CONFIG_MTD_NAND=y
-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_H1900 is not set
-CONFIG_MTD_NAND_IDS=y
-CONFIG_MTD_NAND_DISKONCHIP=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
-CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
-CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
-# CONFIG_MTD_NAND_SHARPSL is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-CONFIG_MTD_ONENAND=y
-# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
-# CONFIG_MTD_ONENAND_GENERIC is not set
-# CONFIG_MTD_ONENAND_OTP is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-
-#
-# Parallel port support
-#
-# CONFIG_PARPORT is not set
-
-#
-# Plug and Play support
-#
-# CONFIG_PNPACPI is not set
-
-#
-# Block devices
-#
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=m
-CONFIG_BLK_DEV_NBD=y
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=8
-CONFIG_BLK_DEV_RAM_SIZE=4096
-CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-
-#
-# ATA/ATAPI/MFM/RLL support
-#
-CONFIG_IDE=y
-CONFIG_IDE_MAX_HWIFS=4
-CONFIG_BLK_DEV_IDE=y
-
-#
-# Please see Documentation/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-CONFIG_IDEDISK_MULTI_MODE=y
-CONFIG_BLK_DEV_IDECS=m
-# CONFIG_BLK_DEV_IDECD is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-
-#
-# IDE chipset support/bugfixes
-#
-CONFIG_IDE_GENERIC=y
-# CONFIG_IDE_ARM is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-# CONFIG_BLK_DEV_HD is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-CONFIG_CHR_DEV_SG=y
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-
-#
-# SCSI low-level drivers
-#
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_ESP_CORE is not set
-
-#
-# PCMCIA SCSI adapter support
-#
-# CONFIG_PCMCIA_AHA152X is not set
-# CONFIG_PCMCIA_FDOMAIN is not set
-# CONFIG_PCMCIA_NINJA_SCSI is not set
-# CONFIG_PCMCIA_QLOGIC is not set
-# CONFIG_PCMCIA_SYM53C500 is not set
-
-#
-# Serial ATA (prod) and Parallel ATA (experimental) drivers
-#
-CONFIG_ATA=m
-# CONFIG_ATA_NONSTANDARD is not set
-CONFIG_PATA_PCMCIA=m
-CONFIG_PATA_PLATFORM=m
-
-#
-# Multi-device support (RAID and LVM)
-#
-# CONFIG_MD is not set
-
-#
-# Fusion MPT device support
-#
-# CONFIG_FUSION is not set
-
-#
-# IEEE 1394 (FireWire) support
-#
-
-#
-# I2O device support
-#
-
-#
-# Network device support
-#
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-
-#
-# PHY device support
-#
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_FIXED_PHY is not set
-
-#
-# Ethernet (10 or 100Mbit)
-#
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_SMC91X is not set
-CONFIG_DM9000=y
-# CONFIG_SMC911X is not set
-
-#
-# Ethernet (1000 Mbit)
-#
-
-#
-# Ethernet (10000 Mbit)
-#
-
-#
-# Token Ring devices
-#
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-CONFIG_WLAN_80211=y
-# CONFIG_PCMCIA_RAYCS is not set
-CONFIG_HERMES=y
-# CONFIG_ATMEL is not set
-CONFIG_PCMCIA_HERMES=y
-CONFIG_PCMCIA_SPECTRUM=y
-# CONFIG_AIRO_CS is not set
-# CONFIG_PCMCIA_WL3501 is not set
-# CONFIG_USB_ZD1201 is not set
-CONFIG_HOSTAP=y
-CONFIG_HOSTAP_FIRMWARE=y
-CONFIG_HOSTAP_FIRMWARE_NVRAM=y
-CONFIG_HOSTAP_CS=y
-# CONFIG_ZD1211RW is not set
-
-#
-# PCMCIA network device support
-#
-# CONFIG_NET_PCMCIA is not set
-
-#
-# Wan interfaces
-#
-# CONFIG_WAN is not set
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-# CONFIG_PPPOE is not set
-# CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_SHAPER is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-
-#
-# ISDN subsystem
-#
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_TSDEV=y
-CONFIG_INPUT_TSDEV_SCREEN_X=640
-CONFIG_INPUT_TSDEV_SCREEN_Y=480
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-CONFIG_KEYBOARD_ATKBD=m
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_GPIO is not set
-CONFIG_INPUT_MOUSE=y
-# CONFIG_MOUSE_PS2 is not set
-CONFIG_MOUSE_SERIAL=m
-# CONFIG_MOUSE_VSXXXAA is not set
-# CONFIG_INPUT_JOYSTICK is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-CONFIG_TOUCHSCREEN_UCB1400=y
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-
-#
-# IPMI
-#
-# CONFIG_IPMI_HANDLER is not set
-
-#
-# Watchdog Cards
-#
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-CONFIG_SA1100_WATCHDOG=y
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-CONFIG_HW_RANDOM=y
-# CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-
-#
-# PCMCIA character devices
-#
-# CONFIG_SYNCLINK_CS is not set
-# CONFIG_CARDMAN_4000 is not set
-# CONFIG_CARDMAN_4040 is not set
-# CONFIG_RAW_DRIVER is not set
-
-#
-# TPM devices
-#
-# CONFIG_TCG_TPM is not set
-
-#
-# I2C support
-#
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-
-#
-# I2C Algorithms
-#
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
-
-#
-# I2C Hardware Bus support
-#
-CONFIG_I2C_PXA=y
-CONFIG_I2C_PXA_SLAVE=y
-# CONFIG_I2C_OCORES is not set
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_STUB is not set
-# CONFIG_I2C_PCA_ISA is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_SENSORS_DS1337 is not set
-# CONFIG_SENSORS_DS1374 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-
-#
-# SPI support
-#
-# CONFIG_SPI is not set
-# CONFIG_SPI_MASTER is not set
-
-#
-# Dallas's 1-wire bus
-#
-# CONFIG_W1 is not set
-
-#
-# Hardware Monitoring support
-#
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_ABITUGURU is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ASB100 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_FSCHER is not set
-# CONFIG_SENSORS_FSCPOS is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Misc devices
-#
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_SM501 is not set
-
-#
-# LED devices
-#
-CONFIG_NEW_LEDS=y
-# CONFIG_LEDS_CLASS is not set
-
-#
-# LED drivers
-#
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-
-#
-# Multimedia devices
-#
-# CONFIG_VIDEO_DEV is not set
-
-#
-# Digital Video Broadcasting Devices
-#
-# CONFIG_DVB is not set
-# CONFIG_USB_DABUSB is not set
-
-#
-# Graphics support
-#
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_FB=y
-CONFIG_FIRMWARE_EDID=y
-# CONFIG_FB_DDC is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_VIRTUAL is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-
-#
-# Logo configuration
-#
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-
-#
-# Sound
-#
-CONFIG_SOUND=y
-
-#
-# Advanced Linux Sound Architecture
-#
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_HWDEP=m
-CONFIG_SND_RAWMIDI=m
-CONFIG_SND_SEQUENCER=y
-# CONFIG_SND_SEQ_DUMMY is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=y
-CONFIG_SND_PCM_OSS=y
-CONFIG_SND_PCM_OSS_PLUGINS=y
-# CONFIG_SND_SEQUENCER_OSS is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-CONFIG_SND_VERBOSE_PRINTK=y
-CONFIG_SND_DEBUG=y
-CONFIG_SND_DEBUG_DETECT=y
-# CONFIG_SND_PCM_XRUN_DEBUG is not set
-
-#
-# Generic devices
-#
-CONFIG_SND_AC97_CODEC=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_VIRMIDI is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-
-#
-# ALSA ARM devices
-#
-CONFIG_SND_PXA2XX_PCM=y
-CONFIG_SND_PXA2XX_AC97=y
-
-#
-# USB devices
-#
-CONFIG_SND_USB_AUDIO=m
-
-#
-# PCMCIA devices
-#
-# CONFIG_SND_VXPOCKET is not set
-# CONFIG_SND_PDAUDIOCF is not set
-
-#
-# SoC audio support
-#
-# CONFIG_SND_SOC is not set
-
-#
-# Open Sound System
-#
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=y
-
-#
-# HID Devices
-#
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_HID is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-
-#
-# USB support
-#
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_ISP116X_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-# CONFIG_USB_SL811_HCD is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Input Devices
-#
-# CONFIG_USB_AIPTEK is not set
-# CONFIG_USB_WACOM is not set
-# CONFIG_USB_ACECAD is not set
-# CONFIG_USB_KBTAB is not set
-# CONFIG_USB_POWERMATE is not set
-# CONFIG_USB_TOUCHSCREEN is not set
-# CONFIG_USB_YEALINK is not set
-# CONFIG_USB_XPAD is not set
-# CONFIG_USB_ATI_REMOTE is not set
-# CONFIG_USB_ATI_REMOTE2 is not set
-# CONFIG_USB_KEYSPAN_REMOTE is not set
-# CONFIG_USB_APPLETOUCH is not set
-# CONFIG_USB_GTCO is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET_MII is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_USB_MON is not set
-
-#
-# USB port drivers
-#
-
-#
-# USB Serial Converter support
-#
-CONFIG_USB_SERIAL=m
-# CONFIG_USB_SERIAL_GENERIC is not set
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_AIRPRIME is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_CP2101 is not set
-# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_FUNSOFT is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_IPAQ is not set
-# CONFIG_USB_SERIAL_IR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-# CONFIG_USB_SERIAL_GARMIN is not set
-# CONFIG_USB_SERIAL_IPW is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KLSI is not set
-# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-# CONFIG_USB_SERIAL_MCT_U232 is not set
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_HP4X is not set
-# CONFIG_USB_SERIAL_SAFE is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-# CONFIG_USB_SERIAL_TI is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
-# CONFIG_USB_SERIAL_OPTION is not set
-# CONFIG_USB_SERIAL_OMNINET is not set
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_AUERSWALD is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-
-#
-# USB DSL modem support
-#
-
-#
-# USB Gadget Support
-#
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_PXA2XX is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_AT91 is not set
-CONFIG_USB_GADGET_DUMMY_HCD=y
-CONFIG_USB_DUMMY_HCD=m
-CONFIG_USB_GADGET_DUALSPEED=y
-# CONFIG_USB_ZERO is not set
-# CONFIG_USB_ETH is not set
-# CONFIG_USB_GADGETFS is not set
-# CONFIG_USB_FILE_STORAGE is not set
-# CONFIG_USB_G_SERIAL is not set
-# CONFIG_USB_MIDI_GADGET is not set
-
-#
-# MMC/SD Card support
-#
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_PXA=y
-
-#
-# Real Time Clock
-#
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_HCTOSYS is not set
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-
-#
-# RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-CONFIG_RTC_DRV_PCF8583=m
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-CONFIG_RTC_DRV_SA1100=y
-# CONFIG_RTC_DRV_TEST is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-CONFIG_DNOTIFY=y
-# CONFIG_AUTOFS_FS is not set
-CONFIG_AUTOFS4_FS=y
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-CONFIG_RAMFS=y
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_ECRYPT_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Network File Systems
-#
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-CONFIG_NFS_V4=y
-# CONFIG_NFS_DIRECTIO is not set
-CONFIG_NFSD=y
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-CONFIG_NFSD_V4=y
-CONFIG_NFSD_TCP=y
-CONFIG_ROOT_NFS=y
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-CONFIG_SUNRPC_GSS=y
-CONFIG_RPCSEC_GSS_KRB5=y
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-# CONFIG_CIFS_WEAK_PW_HASH is not set
-# CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-# CONFIG_9P_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-CONFIG_LDM_PARTITION=y
-# CONFIG_LDM_DEBUG is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-
-#
-# Native Language Support
-#
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-15"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-CONFIG_NLS_CODEPAGE_850=y
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=m
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=m
-
-#
-# Distributed Lock Manager
-#
-# CONFIG_DLM is not set
-
-#
-# Profiling support
-#
-# CONFIG_PROFILING is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-# CONFIG_DEBUG_KERNEL is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_FRAME_POINTER=y
-CONFIG_DEBUG_USER=y
-
-#
-# Security options
-#
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-CONFIG_SECURITY=y
-# CONFIG_SECURITY_NETWORK is not set
-CONFIG_SECURITY_CAPABILITIES=y
-# CONFIG_SECURITY_ROOTPLUG is not set
-
-#
-# Cryptographic options
-#
-CONFIG_CRYPTO=y
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_MANAGER=y
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-# CONFIG_CRYPTO_WP512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_CBC=y
-CONFIG_CRYPTO_PCBC=m
-# CONFIG_CRYPTO_LRW is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-# CONFIG_CRYPTO_SERPENT is not set
-CONFIG_CRYPTO_AES=m
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_TEA is not set
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_DEFLATE=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_CRC32C=y
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Hardware crypto devices
-#
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_CRC32=y
-CONFIG_LIBCRC32C=y
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_REED_SOLOMON=y
-CONFIG_REED_SOLOMON_DEC16=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig
deleted file mode 100644
index 909887a..0000000
--- a/arch/arm/configs/viper_defconfig
+++ /dev/null
@@ -1,1676 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc4
-# Thu Aug 21 17:12:07 2008
-#
-CONFIG_ARM=y
-CONFIG_HAVE_PWM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
-CONFIG_ZONE_DMA=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=13
-# CONFIG_CGROUPS is not set
-# CONFIG_GROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-# CONFIG_ELF_CORE is not set
-CONFIG_COMPAT_BRK=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-# CONFIG_SHMEM is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-# CONFIG_HAVE_IOREMAP_PROT is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-# CONFIG_HAVE_DMA_ATTRS is not set
-# CONFIG_USE_GENERIC_SMP_HELPERS is not set
-CONFIG_HAVE_CLK=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_TINY_SHMEM=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-# CONFIG_IOSCHED_AS is not set
-CONFIG_IOSCHED_DEADLINE=y
-# CONFIG_IOSCHED_CFQ is not set
-# CONFIG_DEFAULT_AS is not set
-CONFIG_DEFAULT_DEADLINE=y
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="deadline"
-CONFIG_CLASSIC_RCU=y
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM7X00A is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-CONFIG_ARCH_VIPER=y
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_MACH_TRIZEPS4 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_PXA_EZX is not set
-CONFIG_PXA25x=y
-CONFIG_PXA_PWM=m
-CONFIG_PXA_HAVE_ISA_IRQS=y
-
-#
-# Boot options
-#
-
-#
-# Power management
-#
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-
-#
-# Bus support
-#
-CONFIG_ISA=y
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_PCCARD=m
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_IOCTL=y
-
-#
-# PC-card bridges
-#
-# CONFIG_I82365 is not set
-# CONFIG_TCIC is not set
-CONFIG_PCMCIA_PXA2XX=m
-CONFIG_PCMCIA_PROBE=y
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=1
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=31:02 rootfstype=jffs2 ro console=ttyS0,115200"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Frequency scaling
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-# CONFIG_CPU_FREQ_DEBUG is not set
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
-CONFIG_CPU_FREQ_GOV_USERSPACE=m
-CONFIG_CPU_FREQ_GOV_ONDEMAND=m
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-# CONFIG_FPE_NWFPE is not set
-CONFIG_FPE_FASTFPE=y
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-# CONFIG_APM_EMULATION is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-# CONFIG_BT_SCO is not set
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-# CONFIG_BT_BNEP_MC_FILTER is not set
-# CONFIG_BT_BNEP_PROTO_FILTER is not set
-# CONFIG_BT_HIDP is not set
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIUSB=m
-# CONFIG_BT_HCIUSB_SCO is not set
-# CONFIG_BT_HCIBTUSB is not set
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-# CONFIG_BT_HCIUART_LL is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIDTL1 is not set
-# CONFIG_BT_HCIBT3C is not set
-# CONFIG_BT_HCIBLUECARD is not set
-# CONFIG_BT_HCIBTUART is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_AF_RXRPC is not set
-
-#
-# Wireless
-#
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-# CONFIG_IEEE80211_CRYPT_CCMP is not set
-# CONFIG_IEEE80211_CRYPT_TKIP is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=m
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=0
-# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
-# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-# CONFIG_MTD_CFI_I2 is not set
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_OTP is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-CONFIG_MTD_RAM=y
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_START=0x8000000
-CONFIG_MTD_PHYSMAP_LEN=0
-CONFIG_MTD_PHYSMAP_BANKWIDTH=2
-CONFIG_MTD_PXA2XX=y
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_IMPA7 is not set
-# CONFIG_MTD_SHARP_SL is not set
-# CONFIG_MTD_PLATRAM is not set
-CONFIG_MTD_SPARSE_RAM=y
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-# CONFIG_PNP is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=m
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_PROC_FS is not set
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=m
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_AHA152X is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_ADVANSYS is not set
-# CONFIG_SCSI_IN2000 is not set
-# CONFIG_SCSI_DTC3280 is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_GENERIC_NCR5380 is not set
-# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
-# CONFIG_SCSI_NCR53C406A is not set
-# CONFIG_SCSI_PAS16 is not set
-# CONFIG_SCSI_QLOGIC_FAS is not set
-# CONFIG_SCSI_SYM53C416 is not set
-# CONFIG_SCSI_T128 is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
-# CONFIG_SCSI_DH is not set
-CONFIG_ATA=m
-# CONFIG_ATA_NONSTANDARD is not set
-# CONFIG_SATA_PMP is not set
-CONFIG_ATA_SFF=y
-# CONFIG_SATA_MV is not set
-# CONFIG_PATA_LEGACY is not set
-CONFIG_PATA_PCMCIA=m
-# CONFIG_PATA_QDI is not set
-# CONFIG_PATA_WINBOND_VLB is not set
-# CONFIG_PATA_PLATFORM is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_ARCNET is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_AX88796 is not set
-# CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_NET_VENDOR_SMC is not set
-CONFIG_SMC91X=y
-# CONFIG_DM9000 is not set
-# CONFIG_SMC911X is not set
-# CONFIG_NET_VENDOR_RACAL is not set
-# CONFIG_AT1700 is not set
-# CONFIG_DEPCA is not set
-# CONFIG_HP100 is not set
-# CONFIG_NET_ISA is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_NET_PCI is not set
-# CONFIG_B44 is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_TR is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-CONFIG_USB_PEGASUS=m
-# CONFIG_USB_RTL8150 is not set
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_CDCETHER=m
-# CONFIG_USB_NET_DM9601 is not set
-# CONFIG_USB_NET_GL620A is not set
-CONFIG_USB_NET_NET1080=m
-# CONFIG_USB_NET_PLUSB is not set
-# CONFIG_USB_NET_MCS7830 is not set
-# CONFIG_USB_NET_RNDIS_HOST is not set
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_NET_PCMCIA=y
-# CONFIG_PCMCIA_3C589 is not set
-# CONFIG_PCMCIA_3C574 is not set
-# CONFIG_PCMCIA_FMVJ18X is not set
-# CONFIG_PCMCIA_PCNET is not set
-# CONFIG_PCMCIA_NMCLAN is not set
-# CONFIG_PCMCIA_SMC91C92 is not set
-# CONFIG_PCMCIA_XIRC2PS is not set
-# CONFIG_PCMCIA_AXNET is not set
-# CONFIG_WAN is not set
-CONFIG_PPP=m
-# CONFIG_PPP_MULTILINK is not set
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_PPP_MPPE is not set
-# CONFIG_PPPOE is not set
-# CONFIG_PPPOL2TP is not set
-# CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=m
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_FUJITSU=m
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-CONFIG_TOUCHSCREEN_ELO=m
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_INEXIO=m
-# CONFIG_TOUCHSCREEN_MK712 is not set
-CONFIG_TOUCHSCREEN_HTCPEN=m
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
-# CONFIG_TOUCHSCREEN_WM97XX is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-CONFIG_INPUT_UINPUT=m
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_LIBPS2 is not set
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-# CONFIG_CONSOLE_TRANSLATIONS is not set
-# CONFIG_VT_CONSOLE is not set
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=m
-# CONFIG_SERIAL_8250_CS is not set
-CONFIG_SERIAL_8250_NR_UARTS=5
-CONFIG_SERIAL_8250_RUNTIME_UARTS=5
-# CONFIG_SERIAL_8250_EXTENDED is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=m
-# CONFIG_NVRAM is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-
-#
-# PCMCIA character devices
-#
-# CONFIG_SYNCLINK_CS is not set
-# CONFIG_CARDMAN_4000 is not set
-# CONFIG_CARDMAN_4040 is not set
-# CONFIG_IPWIRELESS is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_DEVPORT=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-
-#
-# I2C Algorithms
-#
-CONFIG_I2C_ALGOBIT=y
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-CONFIG_I2C_GPIO=y
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_ELEKTOR is not set
-# CONFIG_I2C_PCA_ISA is not set
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-# CONFIG_SPI is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7473 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-# CONFIG_SA1100_WATCHDOG is not set
-
-#
-# ISA-based Watchdog Cards
-#
-# CONFIG_PCWATCHDOG is not set
-# CONFIG_MIXCOMWD is not set
-# CONFIG_WDT is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-
-#
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-CONFIG_FB_CFB_FILLRECT=m
-CONFIG_FB_CFB_COPYAREA=m
-CONFIG_FB_CFB_IMAGEBLIT=m
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=m
-# CONFIG_FB_PXA_SMARTPANEL is not set
-CONFIG_FB_PXA_PARAMETERS=y
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_W100 is not set
-# CONFIG_FB_AM200EPD is not set
-# CONFIG_FB_VIRTUAL is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=m
-# CONFIG_LCD_ILI9320 is not set
-# CONFIG_LCD_PLATFORM is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=m
-# CONFIG_BACKLIGHT_CORGI is not set
-CONFIG_BACKLIGHT_PWM=m
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_MDA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=m
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-# CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_VMASTER=y
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-# CONFIG_SND_AC97_POWER_SAVE is not set
-CONFIG_SND_ARM=y
-CONFIG_SND_PXA2XX_PCM=m
-CONFIG_SND_PXA2XX_AC97=m
-CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_CAIAQ is not set
-CONFIG_SND_PCMCIA=y
-# CONFIG_SND_VXPOCKET is not set
-# CONFIG_SND_PDAUDIOCF is not set
-# CONFIG_SND_SOC is not set
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=m
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=m
-# CONFIG_USB_HIDINPUT_POWERBOOK is not set
-# CONFIG_HID_FF is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-# CONFIG_USB_KBD is not set
-# CONFIG_USB_MOUSE is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=m
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-# CONFIG_USB_MON is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-CONFIG_USB_ISP116X_HCD=m
-# CONFIG_USB_ISP1760_HCD is not set
-CONFIG_USB_SL811_HCD=m
-# CONFIG_USB_SL811_CS is not set
-CONFIG_USB_R8A66597_HCD=m
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_SIERRA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=m
-# CONFIG_USB_EZUSB is not set
-CONFIG_USB_SERIAL_GENERIC=y
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_CP2101 is not set
-# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_FUNSOFT is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_IPAQ is not set
-# CONFIG_USB_SERIAL_IR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-# CONFIG_USB_SERIAL_GARMIN is not set
-# CONFIG_USB_SERIAL_IPW is not set
-# CONFIG_USB_SERIAL_IUU is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KLSI is not set
-# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-CONFIG_USB_SERIAL_MCT_U232=m
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MOTOROLA is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_HP4X is not set
-# CONFIG_USB_SERIAL_SAFE is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-# CONFIG_USB_SERIAL_TI is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
-# CONFIG_USB_SERIAL_OPTION is not set
-# CONFIG_USB_SERIAL_OMNINET is not set
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-CONFIG_USB_GADGET_PXA25X=y
-CONFIG_USB_PXA25X=m
-# CONFIG_USB_PXA25X_SMALL is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_PXA27X is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-# CONFIG_USB_GADGET_DUALSPEED is not set
-# CONFIG_USB_ZERO is not set
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-# CONFIG_USB_FILE_STORAGE_TEST is not set
-CONFIG_USB_G_SERIAL=m
-# CONFIG_USB_MIDI_GADGET is not set
-CONFIG_USB_G_PRINTER=m
-# CONFIG_USB_CDC_COMPOSITE is not set
-# CONFIG_MMC is not set
-# CONFIG_NEW_LEDS is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=m
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-CONFIG_RTC_DRV_DS1307=m
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-
-#
-# SPI RTC drivers
-#
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_SA1100=m
-# CONFIG_DMADEVICES is not set
-
-#
-# Voltage and Current regulators
-#
-# CONFIG_REGULATOR is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_UIO is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=m
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=m
-# CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4DEV_FS is not set
-CONFIG_JBD=m
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-# CONFIG_NFSD_V4 is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=m
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=m
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-CONFIG_NLS_CODEPAGE_850=m
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=m
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=m
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=m
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_HAVE_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-# CONFIG_FTRACE is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_MANAGER=m
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_LZO is not set
-CONFIG_CRYPTO_HW=y
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
-CONFIG_CRC_CCITT=m
-# CONFIG_CRC16 is not set
-CONFIG_CRC_T10DIF=m
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/xcep_defconfig b/arch/arm/configs/xcep_defconfig
deleted file mode 100644
index 84a72ac..0000000
--- a/arch/arm/configs/xcep_defconfig
+++ /dev/null
@@ -1,1128 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc6
-# Thu Aug 20 09:02:37 2009
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=".xcep-itech"
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-CONFIG_EMBEDDED=y
-# CONFIG_UID16 is not set
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-# CONFIG_SHMEM is not set
-CONFIG_AIO=y
-
-#
-# Performance Counters
-#
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_STRIP_ASM_SYMS=y
-# CONFIG_COMPAT_BRK is not set
-# CONFIG_SLAB is not set
-# CONFIG_SLUB is not set
-CONFIG_SLOB=y
-# CONFIG_PROFILING is not set
-CONFIG_TRACEPOINTS=y
-CONFIG_MARKERS=y
-CONFIG_HAVE_OPROFILE=y
-CONFIG_KPROBES=y
-CONFIG_KRETPROBES=y
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_SLOW_WORK is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLOCK is not set
-# CONFIG_FREEZER is not set
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_MACH_STARGATE2 is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_VIPER is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_EXEDA is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_COLIBRI300 is not set
-# CONFIG_MACH_COLIBRI320 is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_H4700 is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_HIMALAYA is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_MACH_CSB726 is not set
-# CONFIG_PXA_EZX is not set
-CONFIG_MACH_XCEP=y
-CONFIG_PXA25x=y
-CONFIG_PXA_SSP=y
-CONFIG_PLAT_PXA=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=mtd4 rootfstype=jffs2 ro console=ttyS0,115200"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_FREQ is not set
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=m
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-CONFIG_NET_KEY=y
-# CONFIG_NET_KEY_MIGRATE is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-CONFIG_INET_LRO=y
-# CONFIG_INET_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_NET_TCPPROBE is not set
-# CONFIG_NET_DROP_MONITOR is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_WIRELESS is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
-# CONFIG_FW_LOADER is not set
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_GEN_PROBE=y
-# CONFIG_MTD_CFI_ADV_OPTIONS is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-CONFIG_MTD_CFI_INTELEXT=y
-# CONFIG_MTD_CFI_AMDSTD is not set
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-CONFIG_MTD_PXA2XX=y
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_HAVE_IDE=y
-
-#
-# SCSI device support
-#
-# CONFIG_SCSI_DMA is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_AX88796 is not set
-CONFIG_SMC91X=y
-# CONFIG_DM9000 is not set
-# CONFIG_ETHOC is not set
-# CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_DNET is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-# CONFIG_KS8842 is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-# CONFIG_DEVKMEM is not set
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_I2C=m
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_DESIGNWARE is not set
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=m
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-# CONFIG_SPI is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-CONFIG_HWMON=m
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-CONFIG_SENSORS_ADM1021=m
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7462 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7473 is not set
-# CONFIG_SENSORS_ADT7475 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_G760A is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_LTC4215 is not set
-# CONFIG_SENSORS_LTC4245 is not set
-# CONFIG_SENSORS_LM95241 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-CONFIG_SENSORS_MAX6650=m
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_SHT15 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_TMP401 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_AB3100_CORE is not set
-# CONFIG_MEDIA_SUPPORT is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_SOUND is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_MMC is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
-# CONFIG_NEW_LEDS is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=m
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-
-#
-# SPI RTC drivers
-#
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-CONFIG_RTC_DRV_SA1100=m
-# CONFIG_RTC_DRV_PXA is not set
-CONFIG_DMADEVICES=y
-
-#
-# DMA Devices
-#
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_REGULATOR is not set
-# CONFIG_UIO is not set
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_FILE_LOCKING=y
-# CONFIG_FSNOTIFY is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_ROMFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-CONFIG_NLS=m
-CONFIG_NLS_DEFAULT="utf8"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=m
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_KPROBES_SANITY_TEST is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_ARM_UNWIND is not set
-# CONFIG_DEBUG_USER is not set
-# CONFIG_DEBUG_ERRORS is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_ALGAPI2=m
-CONFIG_CRYPTO_HASH=m
-CONFIG_CRYPTO_HASH2=m
-# CONFIG_CRYPTO_MANAGER is not set
-# CONFIG_CRYPTO_MANAGER2 is not set
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-# CONFIG_CRYPTO_ECB is not set
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=m
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-# CONFIG_CRYPTO_AES is not set
-# CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_ARC4 is not set
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_NLATTR=y
diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig
deleted file mode 100644
index fca5ff6..0000000
--- a/arch/arm/configs/zeus_defconfig
+++ /dev/null
@@ -1,2031 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32
-# Tue Dec  8 20:27:05 2009
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-
-#
-# RCU Subsystem
-#
-# CONFIG_TREE_RCU is not set
-# CONFIG_TREE_PREEMPT_RCU is not set
-CONFIG_TINY_RCU=y
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=13
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-# CONFIG_NET_NS is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-# CONFIG_EMBEDDED is not set
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_COMPAT_BRK=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_SLOW_WORK is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-CONFIG_LBDAF=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_DEADLINE=y
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_DEFAULT_DEADLINE=y
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="deadline"
-# CONFIG_INLINE_SPIN_TRYLOCK is not set
-# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK is not set
-# CONFIG_INLINE_SPIN_LOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
-CONFIG_INLINE_SPIN_UNLOCK=y
-# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
-CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
-# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_READ_TRYLOCK is not set
-# CONFIG_INLINE_READ_LOCK is not set
-# CONFIG_INLINE_READ_LOCK_BH is not set
-# CONFIG_INLINE_READ_LOCK_IRQ is not set
-# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
-CONFIG_INLINE_READ_UNLOCK=y
-# CONFIG_INLINE_READ_UNLOCK_BH is not set
-CONFIG_INLINE_READ_UNLOCK_IRQ=y
-# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_WRITE_TRYLOCK is not set
-# CONFIG_INLINE_WRITE_LOCK is not set
-# CONFIG_INLINE_WRITE_LOCK_BH is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
-CONFIG_INLINE_WRITE_UNLOCK=y
-# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
-CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
-# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
-# CONFIG_MUTEX_SPIN_ON_OWNER is not set
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_U8500 is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-
-#
-# Intel/Marvell Dev Platforms (sorted by hardware release time)
-#
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_ZYLONITE300 is not set
-# CONFIG_MACH_ZYLONITE320 is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-
-#
-# Third Party Dev Platforms (sorted by vendor name)
-#
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_ARCH_VIPER is not set
-CONFIG_MACH_ARCOM_ZEUS=y
-# CONFIG_MACH_BALLOON3 is not set
-# CONFIG_MACH_CSB726 is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_EXEDA is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_MACH_STARGATE2 is not set
-# CONFIG_MACH_XCEP is not set
-# CONFIG_TRIZEPS_PXA is not set
-CONFIG_ARCOM_PCMCIA=y
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_COLIBRI300 is not set
-# CONFIG_MACH_COLIBRI320 is not set
-
-#
-# End-user Products (sorted by vendor name)
-#
-# CONFIG_MACH_H4700 is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_HIMALAYA is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_PXA_EZX is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-CONFIG_PXA27x=y
-CONFIG_PXA_SSP=y
-CONFIG_PXA_HAVE_BOARD_IRQS=y
-CONFIG_PXA_HAVE_ISA_IRQS=y
-CONFIG_PLAT_PXA=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-CONFIG_ISA=y
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_PCCARD=m
-CONFIG_PCMCIA=m
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_IOCTL=y
-
-#
-# PC-card bridges
-#
-# CONFIG_I82365 is not set
-# CONFIG_TCIC is not set
-CONFIG_PCMCIA_SOC_COMMON=m
-CONFIG_PCMCIA_PXA2XX=m
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA_PROBE=y
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=31:02 rootfstype=jffs2 ro console=ttyS0,115200"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-# CONFIG_CPU_FREQ_DEBUG is not set
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-CONFIG_CPU_FREQ_GOV_POWERSAVE=m
-CONFIG_CPU_FREQ_GOV_USERSPACE=m
-CONFIG_CPU_FREQ_GOV_ONDEMAND=m
-CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_APM_EMULATION=y
-# CONFIG_PM_RUNTIME is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-# CONFIG_BT_SCO is not set
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-# CONFIG_BT_BNEP_MC_FILTER is not set
-# CONFIG_BT_BNEP_PROTO_FILTER is not set
-# CONFIG_BT_HIDP is not set
-
-#
-# Bluetooth device drivers
-#
-# CONFIG_BT_HCIBTUSB is not set
-# CONFIG_BT_HCIBTSDIO is not set
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-# CONFIG_BT_HCIUART_LL is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIDTL1 is not set
-# CONFIG_BT_HCIBT3C is not set
-# CONFIG_BT_HCIBLUECARD is not set
-# CONFIG_BT_HCIBTUART is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_BT_MRVL is not set
-# CONFIG_AF_RXRPC is not set
-CONFIG_WIRELESS=y
-CONFIG_WIRELESS_EXT=y
-CONFIG_WEXT_CORE=y
-CONFIG_WEXT_PROC=y
-CONFIG_WEXT_SPY=y
-CONFIG_WEXT_PRIV=y
-CONFIG_CFG80211=m
-# CONFIG_NL80211_TESTMODE is not set
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-# CONFIG_CFG80211_REG_DEBUG is not set
-CONFIG_CFG80211_DEFAULT_PS=y
-# CONFIG_WIRELESS_OLD_REGULATORY is not set
-CONFIG_CFG80211_WEXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
-CONFIG_LIB80211=m
-# CONFIG_LIB80211_DEBUG is not set
-CONFIG_MAC80211=m
-CONFIG_MAC80211_RC_MINSTREL=y
-# CONFIG_MAC80211_RC_DEFAULT_PID is not set
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT="minstrel"
-# CONFIG_MAC80211_MESH is not set
-# CONFIG_MAC80211_LEDS is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_DEVTMPFS is not set
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
-# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
-CONFIG_MTD_REDBOOT_PARTS_READONLY=y
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_GEN_PROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_NOSWAP=y
-# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
-# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-# CONFIG_MTD_CFI_I2 is not set
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_OTP is not set
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-# CONFIG_MTD_CFI_STAA is not set
-CONFIG_MTD_CFI_UTIL=y
-CONFIG_MTD_RAM=y
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-# CONFIG_MTD_XIP is not set
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-CONFIG_MTD_PHYSMAP=y
-# CONFIG_MTD_PHYSMAP_COMPAT is not set
-CONFIG_MTD_PXA2XX=y
-# CONFIG_MTD_ARM_INTEGRATOR is not set
-# CONFIG_MTD_IMPA7 is not set
-# CONFIG_MTD_GPIO_ADDR is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
-# CONFIG_MTD_SST25L is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-# CONFIG_MTD_NAND is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-# CONFIG_PNP is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-
-#
-# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
-#
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-# CONFIG_ISL29003 is not set
-# CONFIG_DS1682 is not set
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-CONFIG_EEPROM_AT24=m
-# CONFIG_EEPROM_AT25 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_IWMC3200TOP is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=m
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-# CONFIG_SCSI_PROC_FS is not set
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=m
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_AHA152X is not set
-# CONFIG_SCSI_AIC7XXX_OLD is not set
-# CONFIG_SCSI_ADVANSYS is not set
-# CONFIG_SCSI_IN2000 is not set
-# CONFIG_LIBFC is not set
-# CONFIG_LIBFCOE is not set
-# CONFIG_SCSI_DTC3280 is not set
-# CONFIG_SCSI_FUTURE_DOMAIN is not set
-# CONFIG_SCSI_GENERIC_NCR5380 is not set
-# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
-# CONFIG_SCSI_NCR53C406A is not set
-# CONFIG_SCSI_PAS16 is not set
-# CONFIG_SCSI_QLOGIC_FAS is not set
-# CONFIG_SCSI_SYM53C416 is not set
-# CONFIG_SCSI_T128 is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-CONFIG_ATA=m
-# CONFIG_ATA_NONSTANDARD is not set
-CONFIG_ATA_VERBOSE_ERROR=y
-# CONFIG_SATA_PMP is not set
-CONFIG_ATA_SFF=y
-# CONFIG_SATA_MV is not set
-# CONFIG_PATA_LEGACY is not set
-CONFIG_PATA_PCMCIA=m
-# CONFIG_PATA_QDI is not set
-# CONFIG_PATA_WINBOND_VLB is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_ARCNET is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_AX88796 is not set
-# CONFIG_NET_VENDOR_3COM is not set
-# CONFIG_NET_VENDOR_SMC is not set
-# CONFIG_SMC91X is not set
-CONFIG_DM9000=y
-CONFIG_DM9000_DEBUGLEVEL=4
-# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
-# CONFIG_ENC28J60 is not set
-# CONFIG_ETHOC is not set
-# CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_NET_VENDOR_RACAL is not set
-# CONFIG_DNET is not set
-# CONFIG_AT1700 is not set
-# CONFIG_DEPCA is not set
-# CONFIG_HP100 is not set
-# CONFIG_NET_ISA is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_NET_PCI is not set
-# CONFIG_B44 is not set
-# CONFIG_CS89x0 is not set
-# CONFIG_KS8842 is not set
-# CONFIG_KS8851 is not set
-# CONFIG_KS8851_MLL is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_TR is not set
-CONFIG_WLAN=y
-# CONFIG_PCMCIA_RAYCS is not set
-# CONFIG_LIBERTAS_THINFIRM is not set
-# CONFIG_ATMEL is not set
-# CONFIG_AT76C50X_USB is not set
-# CONFIG_AIRO_CS is not set
-# CONFIG_PCMCIA_WL3501 is not set
-# CONFIG_USB_ZD1201 is not set
-# CONFIG_USB_NET_RNDIS_WLAN is not set
-# CONFIG_RTL8187 is not set
-# CONFIG_MAC80211_HWSIM is not set
-# CONFIG_ATH_COMMON is not set
-# CONFIG_B43 is not set
-# CONFIG_B43LEGACY is not set
-# CONFIG_HOSTAP is not set
-# CONFIG_IWM is not set
-# CONFIG_LIBERTAS is not set
-CONFIG_HERMES=m
-CONFIG_HERMES_CACHE_FW_ON_INIT=y
-CONFIG_PCMCIA_HERMES=m
-# CONFIG_PCMCIA_SPECTRUM is not set
-# CONFIG_P54_COMMON is not set
-CONFIG_RT2X00=m
-# CONFIG_RT2500USB is not set
-CONFIG_RT73USB=m
-# CONFIG_RT2800USB is not set
-CONFIG_RT2X00_LIB_USB=m
-CONFIG_RT2X00_LIB=m
-CONFIG_RT2X00_LIB_FIRMWARE=y
-CONFIG_RT2X00_LIB_CRYPTO=y
-CONFIG_RT2X00_LIB_LEDS=y
-# CONFIG_RT2X00_DEBUG is not set
-# CONFIG_WL12XX is not set
-# CONFIG_ZD1211RW is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-CONFIG_NET_PCMCIA=y
-# CONFIG_PCMCIA_3C589 is not set
-# CONFIG_PCMCIA_3C574 is not set
-# CONFIG_PCMCIA_FMVJ18X is not set
-# CONFIG_PCMCIA_PCNET is not set
-# CONFIG_PCMCIA_NMCLAN is not set
-# CONFIG_PCMCIA_SMC91C92 is not set
-# CONFIG_PCMCIA_XIRC2PS is not set
-# CONFIG_PCMCIA_AXNET is not set
-# CONFIG_WAN is not set
-CONFIG_PPP=m
-# CONFIG_PPP_MULTILINK is not set
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_PPP_MPPE is not set
-# CONFIG_PPPOE is not set
-# CONFIG_PPPOL2TP is not set
-# CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=m
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
-# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-CONFIG_TOUCHSCREEN_FUJITSU=m
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-CONFIG_TOUCHSCREEN_ELO=m
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-CONFIG_TOUCHSCREEN_MTOUCH=m
-CONFIG_TOUCHSCREEN_INEXIO=m
-# CONFIG_TOUCHSCREEN_MK712 is not set
-CONFIG_TOUCHSCREEN_HTCPEN=m
-CONFIG_TOUCHSCREEN_PENMOUNT=m
-CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
-CONFIG_TOUCHSCREEN_TOUCHWIN=m
-# CONFIG_TOUCHSCREEN_WM97XX is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-CONFIG_TOUCHSCREEN_TOUCHIT213=m
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-CONFIG_INPUT_UINPUT=m
-# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_SERIAL_8250_CS is not set
-CONFIG_SERIAL_8250_NR_UARTS=7
-CONFIG_SERIAL_8250_RUNTIME_UARTS=7
-# CONFIG_SERIAL_8250_EXTENDED is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_MAX3100 is not set
-# CONFIG_SERIAL_PXA is not set
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=m
-# CONFIG_HW_RANDOM_TIMERIOMEM is not set
-# CONFIG_DTLK is not set
-# CONFIG_R3964 is not set
-
-#
-# PCMCIA character devices
-#
-# CONFIG_SYNCLINK_CS is not set
-# CONFIG_CARDMAN_4000 is not set
-# CONFIG_CARDMAN_4040 is not set
-# CONFIG_IPWIRELESS is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_DEVPORT=y
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=y
-# CONFIG_I2C_HELPER_AUTO is not set
-
-#
-# I2C Algorithms
-#
-CONFIG_I2C_ALGOBIT=y
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_DESIGNWARE is not set
-CONFIG_I2C_GPIO=y
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_ELEKTOR is not set
-# CONFIG_I2C_PCA_ISA is not set
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_BITBANG is not set
-# CONFIG_SPI_GPIO is not set
-CONFIG_SPI_PXA2XX=y
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_TLE62X0 is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-CONFIG_GPIO_PCA953X=y
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_GPIO_MC33880 is not set
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADCXX is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7462 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7473 is not set
-# CONFIG_SENSORS_ADT7475 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_G760A is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM70 is not set
-CONFIG_SENSORS_LM75=m
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_LTC4215 is not set
-# CONFIG_SENSORS_LTC4245 is not set
-# CONFIG_SENSORS_LM95241 is not set
-# CONFIG_SENSORS_MAX1111 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_SHT15 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_TMP401 is not set
-# CONFIG_SENSORS_TMP421 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_SENSORS_LIS3_SPI is not set
-# CONFIG_THERMAL is not set
-CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
-
-#
-# Watchdog Device Drivers
-#
-# CONFIG_SOFT_WATCHDOG is not set
-# CONFIG_SA1100_WATCHDOG is not set
-
-#
-# ISA-based Watchdog Cards
-#
-# CONFIG_PCWATCHDOG is not set
-# CONFIG_MIXCOMWD is not set
-# CONFIG_WDT is not set
-
-#
-# USB-based Watchdog Cards
-#
-# CONFIG_USBPCWATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_UCB1400_CORE is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_MFD_MC13783 is not set
-# CONFIG_AB3100_CORE is not set
-# CONFIG_EZX_PCAP is not set
-# CONFIG_REGULATOR is not set
-# CONFIG_MEDIA_SUPPORT is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=m
-CONFIG_FB_CFB_COPYAREA=m
-CONFIG_FB_CFB_IMAGEBLIT=m
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=m
-# CONFIG_FB_PXA_OVERLAY is not set
-# CONFIG_FB_PXA_SMARTPANEL is not set
-CONFIG_FB_PXA_PARAMETERS=y
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_W100 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_BROADSHEET is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=m
-# CONFIG_LCD_LMS283GF05 is not set
-# CONFIG_LCD_LTV350QV is not set
-# CONFIG_LCD_ILI9320 is not set
-# CONFIG_LCD_TDO24M is not set
-# CONFIG_LCD_VGG2432A4 is not set
-# CONFIG_LCD_PLATFORM is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=m
-CONFIG_BACKLIGHT_GENERIC=m
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_MDA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=m
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-# CONFIG_SND_SUPPORT_OLD_API is not set
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_VMASTER=y
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-CONFIG_SND_AC97_CODEC=m
-CONFIG_SND_DRIVERS=y
-# CONFIG_SND_DUMMY is not set
-# CONFIG_SND_MTPAV is not set
-# CONFIG_SND_SERIAL_U16550 is not set
-# CONFIG_SND_MPU401 is not set
-# CONFIG_SND_AC97_POWER_SAVE is not set
-CONFIG_SND_ARM=y
-CONFIG_SND_PXA2XX_PCM=m
-CONFIG_SND_PXA2XX_LIB=m
-CONFIG_SND_PXA2XX_LIB_AC97=y
-CONFIG_SND_PXA2XX_AC97=m
-# CONFIG_SND_SPI is not set
-CONFIG_SND_USB=y
-# CONFIG_SND_USB_AUDIO is not set
-# CONFIG_SND_USB_CAIAQ is not set
-# CONFIG_SND_PCMCIA is not set
-CONFIG_SND_SOC=m
-CONFIG_SND_PXA2XX_SOC=m
-CONFIG_SND_SOC_I2C_AND_SPI=m
-# CONFIG_SND_SOC_ALL_CODECS is not set
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=m
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=m
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-CONFIG_USB_SUSPEND=y
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_MON is not set
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=m
-# CONFIG_USB_EZUSB is not set
-CONFIG_USB_SERIAL_GENERIC=y
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-# CONFIG_USB_SERIAL_BELKIN is not set
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
-# CONFIG_USB_SERIAL_CP210X is not set
-# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
-# CONFIG_USB_SERIAL_EMPEG is not set
-# CONFIG_USB_SERIAL_FTDI_SIO is not set
-# CONFIG_USB_SERIAL_FUNSOFT is not set
-# CONFIG_USB_SERIAL_VISOR is not set
-# CONFIG_USB_SERIAL_IPAQ is not set
-# CONFIG_USB_SERIAL_IR is not set
-# CONFIG_USB_SERIAL_EDGEPORT is not set
-# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
-# CONFIG_USB_SERIAL_GARMIN is not set
-# CONFIG_USB_SERIAL_IPW is not set
-# CONFIG_USB_SERIAL_IUU is not set
-# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
-# CONFIG_USB_SERIAL_KEYSPAN is not set
-# CONFIG_USB_SERIAL_KLSI is not set
-# CONFIG_USB_SERIAL_KOBIL_SCT is not set
-CONFIG_USB_SERIAL_MCT_U232=m
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MOTOROLA is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-# CONFIG_USB_SERIAL_PL2303 is not set
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_QUALCOMM is not set
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_HP4X is not set
-# CONFIG_USB_SERIAL_SAFE is not set
-# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-# CONFIG_USB_SERIAL_SYMBOL is not set
-# CONFIG_USB_SERIAL_TI is not set
-# CONFIG_USB_SERIAL_CYBERJACK is not set
-# CONFIG_USB_SERIAL_XIRCOM is not set
-# CONFIG_USB_SERIAL_OPTION is not set
-# CONFIG_USB_SERIAL_OMNINET is not set
-# CONFIG_USB_SERIAL_OPTICON is not set
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_PXA25X is not set
-# CONFIG_USB_GADGET_R8A66597 is not set
-CONFIG_USB_GADGET_PXA27X=y
-CONFIG_USB_PXA27X=m
-# CONFIG_USB_GADGET_S3C_HSOTG is not set
-# CONFIG_USB_GADGET_IMX is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_FSL_QE is not set
-# CONFIG_USB_GADGET_CI13XXX is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_LANGWELL is not set
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-# CONFIG_USB_GADGET_DUALSPEED is not set
-# CONFIG_USB_ZERO is not set
-# CONFIG_USB_AUDIO is not set
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-# CONFIG_USB_ETH_EEM is not set
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-# CONFIG_USB_FILE_STORAGE_TEST is not set
-CONFIG_USB_G_SERIAL=m
-# CONFIG_USB_MIDI_GADGET is not set
-CONFIG_USB_G_PRINTER=m
-# CONFIG_USB_CDC_COMPOSITE is not set
-
-#
-# OTG and related infrastructure
-#
-CONFIG_USB_OTG_UTILS=y
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_NOP_USB_XCEIV is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_PXA=y
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_AT91 is not set
-# CONFIG_MMC_ATMELMCI is not set
-# CONFIG_MMC_SPI is not set
-# CONFIG_MEMSTICK is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=m
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_PCA9532 is not set
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_GPIO_PLATFORM=y
-# CONFIG_LEDS_LP3944 is not set
-# CONFIG_LEDS_PCA955X is not set
-# CONFIG_LEDS_DAC124S085 is not set
-# CONFIG_LEDS_BD2802 is not set
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
-CONFIG_LEDS_TRIGGER_GPIO=m
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=m
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-CONFIG_RTC_DRV_ISL1208=m
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-# CONFIG_RTC_DRV_PCF2123 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_MSM6242 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_RP5C01 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_RTC_DRV_SA1100 is not set
-CONFIG_RTC_DRV_PXA=m
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-# CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-# CONFIG_DNOTIFY is not set
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-# CONFIG_MSDOS_FS is not set
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-# CONFIG_JFFS2_SUMMARY is not set
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V3=y
-# CONFIG_NFSD_V3_ACL is not set
-# CONFIG_NFSD_V4 is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_EXPORTFS=m
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=m
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=m
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-CONFIG_NLS_CODEPAGE_850=m
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=m
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-CONFIG_NLS_ISO8859_15=m
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=m
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_ENABLE_DEFAULT_TRACERS is not set
-# CONFIG_BOOT_TRACER is not set
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARM_UNWIND=y
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
-# CONFIG_OC_ETM is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_DEFAULT_SECURITY_SELINUX is not set
-# CONFIG_DEFAULT_SECURITY_SMACK is not set
-# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_DEFAULT_SECURITY=""
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=m
-CONFIG_CRYPTO_ALGAPI2=m
-CONFIG_CRYPTO_AEAD2=m
-CONFIG_CRYPTO_BLKCIPHER=m
-CONFIG_CRYPTO_BLKCIPHER2=m
-CONFIG_CRYPTO_HASH=m
-CONFIG_CRYPTO_HASH2=m
-CONFIG_CRYPTO_RNG2=m
-CONFIG_CRYPTO_PCOMP=m
-CONFIG_CRYPTO_MANAGER=m
-CONFIG_CRYPTO_MANAGER2=m
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-CONFIG_CRYPTO_WORKQUEUE=m
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_VMAC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_GHASH is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-CONFIG_CRYPTO_MICHAEL_MIC=m
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=m
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=m
-CONFIG_CRC_T10DIF=m
-CONFIG_CRC_ITU_T=m
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_NLATTR=y
-- 
1.7.0.4



From eric.y.miao at gmail.com  Sat Jun  5 03:55:37 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat,  5 Jun 2010 15:55:37 +0800
Subject: [PATCH 3/4] [ARM] pxa: merge all pxa3xx board configs into
	pxa3xx_defconfig
In-Reply-To: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1275724538-5075-4-git-send-email-eric.y.miao@gmail.com>

Signed-off-by: Eric Miao <eric.y.miao at gmail.com>
---
 arch/arm/configs/cm_x300_defconfig        | 1753 --------------------------
 arch/arm/configs/colibri_pxa300_defconfig | 1155 ------------------
 arch/arm/configs/pxa3xx_defconfig         | 1343 +++++++++++++++++----
 arch/arm/configs/raumfeld_defconfig       | 1898 -----------------------------
 4 files changed, 1100 insertions(+), 5049 deletions(-)
 delete mode 100644 arch/arm/configs/cm_x300_defconfig
 delete mode 100644 arch/arm/configs/colibri_pxa300_defconfig
 delete mode 100644 arch/arm/configs/raumfeld_defconfig

diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig
deleted file mode 100644
index a334069..0000000
--- a/arch/arm/configs/cm_x300_defconfig
+++ /dev/null
@@ -1,1753 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32-rc4
-# Tue Oct 13 19:03:13 2009
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION="-cm-x300"
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=18
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_USER_SCHED=y
-# CONFIG_CGROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_IPC_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-# CONFIG_NET_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-# CONFIG_EMBEDDED is not set
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_COMPAT_BRK=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_GCOV_KERNEL is not set
-CONFIG_SLOW_WORK=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-CONFIG_LBDAF=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-
-#
-# Supported PXA3xx Processor Variants
-#
-CONFIG_CPU_PXA300=y
-CONFIG_CPU_PXA310=y
-# CONFIG_CPU_PXA320 is not set
-# CONFIG_CPU_PXA930 is not set
-# CONFIG_CPU_PXA935 is not set
-# CONFIG_CPU_PXA950 is not set
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_MACH_STARGATE2 is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_MACH_BALLOON3 is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_VIPER is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_EXEDA is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_COLIBRI300 is not set
-# CONFIG_MACH_COLIBRI320 is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-CONFIG_MACH_CM_X300=y
-# CONFIG_MACH_H4700 is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_HIMALAYA is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_MACH_CSB726 is not set
-# CONFIG_PXA_EZX is not set
-# CONFIG_MACH_XCEP is not set
-CONFIG_PXA3xx=y
-CONFIG_PLAT_PXA=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSC3=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_IO_36=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_OUTER_CACHE=y
-CONFIG_CACHE_XSC3L2=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_IWMMXT=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_HIGHMEM=y
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_BOUNCE=y
-CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/mtdblock5 rootfstype=ubifs console=ttyS2,38400"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-# CONFIG_CPU_FREQ_DEBUG is not set
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-CONFIG_CPU_FREQ_GOV_USERSPACE=y
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_APM_EMULATION=y
-# CONFIG_PM_RUNTIME is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
-CONFIG_UNIX=y
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_PNP_RARP=y
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIBTUSB=m
-# CONFIG_BT_HCIBTSDIO is not set
-# CONFIG_BT_HCIUART is not set
-# CONFIG_BT_HCIBCM203X is not set
-# CONFIG_BT_HCIBPA10X is not set
-# CONFIG_BT_HCIBFUSB is not set
-# CONFIG_BT_HCIVHCI is not set
-# CONFIG_BT_MRVL is not set
-# CONFIG_AF_RXRPC is not set
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-CONFIG_CFG80211_DEFAULT_PS_VALUE=0
-# CONFIG_WIRELESS_OLD_REGULATORY is not set
-CONFIG_WIRELESS_EXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
-CONFIG_LIB80211=m
-# CONFIG_LIB80211_DEBUG is not set
-
-#
-# CFG80211 needs to be enabled for MAC80211
-#
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_DEVTMPFS is not set
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_TESTS is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
-# CONFIG_MTD_SST25L is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND=y
-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_H1900 is not set
-# CONFIG_MTD_NAND_GPIO is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_SHARPSL is not set
-CONFIG_MTD_NAND_PXA3xx=y
-# CONFIG_MTD_NAND_PXA3xx_BUILTIN is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_ALAUDA is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-
-#
-# UBI - Unsorted block images
-#
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_RESERVE=1
-# CONFIG_MTD_UBI_GLUEBI is not set
-
-#
-# UBI debugging options
-#
-# CONFIG_MTD_UBI_DEBUG is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=4096
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-# CONFIG_CHR_DEV_SG is not set
-# CONFIG_CHR_DEV_SCH is not set
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_LIBFC is not set
-# CONFIG_LIBFCOE is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_AX88796 is not set
-# CONFIG_SMC91X is not set
-CONFIG_DM9000=y
-CONFIG_DM9000_DEBUGLEVEL=0
-CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
-# CONFIG_ENC28J60 is not set
-# CONFIG_ETHOC is not set
-# CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_DNET is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-# CONFIG_KS8842 is not set
-# CONFIG_KS8851 is not set
-# CONFIG_KS8851_MLL is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN=y
-# CONFIG_WLAN_PRE80211 is not set
-CONFIG_WLAN_80211=y
-CONFIG_LIBERTAS=m
-# CONFIG_LIBERTAS_USB is not set
-CONFIG_LIBERTAS_SDIO=m
-# CONFIG_LIBERTAS_SPI is not set
-# CONFIG_LIBERTAS_DEBUG is not set
-# CONFIG_USB_ZD1201 is not set
-# CONFIG_HOSTAP is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ADP5588 is not set
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_GPIO is not set
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_LM8323 is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-CONFIG_KEYBOARD_PXA27x=m
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
-# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_DA9034 is not set
-# CONFIG_TOUCHSCREEN_EETI is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-CONFIG_TOUCHSCREEN_WM97XX=m
-# CONFIG_TOUCHSCREEN_WM9705 is not set
-CONFIG_TOUCHSCREEN_WM9712=y
-# CONFIG_TOUCHSCREEN_WM9713 is not set
-# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_MAX3100 is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-# CONFIG_I2C_CHARDEV is not set
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_DESIGNWARE is not set
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-# CONFIG_SPI_PXA2XX is not set
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_TLE62X0 is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-CONFIG_GPIO_SYSFS=y
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-CONFIG_GPIO_PCA953X=y
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_GPIO_MC33880 is not set
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_UCB1400_CORE is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-CONFIG_PMIC_DA903X=y
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_MFD_MC13783 is not set
-# CONFIG_AB3100_CORE is not set
-# CONFIG_EZX_PCAP is not set
-CONFIG_REGULATOR=y
-# CONFIG_REGULATOR_DEBUG is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-CONFIG_REGULATOR_DA903X=y
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_MEDIA_SUPPORT is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_OVERLAY is not set
-# CONFIG_FB_PXA_SMARTPANEL is not set
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_W100 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_BROADSHEET is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-# CONFIG_LCD_LMS283GF05 is not set
-# CONFIG_LCD_LTV350QV is not set
-# CONFIG_LCD_ILI9320 is not set
-CONFIG_LCD_TDO24M=y
-# CONFIG_LCD_VGG2432A4 is not set
-# CONFIG_LCD_PLATFORM is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=m
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_DA903X=m
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FONTS=y
-# CONFIG_FONT_8x8 is not set
-# CONFIG_FONT_8x16 is not set
-CONFIG_FONT_6x11=y
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-CONFIG_SOUND=m
-CONFIG_SOUND_OSS_CORE=y
-CONFIG_SOUND_OSS_CORE_PRECLAIM=y
-CONFIG_SND=m
-CONFIG_SND_TIMER=m
-CONFIG_SND_PCM=m
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-CONFIG_SND_OSSEMUL=y
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_PCM_OSS_PLUGINS=y
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-CONFIG_SND_VMASTER=y
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-CONFIG_SND_AC97_CODEC=m
-# CONFIG_SND_DRIVERS is not set
-CONFIG_SND_ARM=y
-CONFIG_SND_PXA2XX_LIB=m
-CONFIG_SND_PXA2XX_LIB_AC97=y
-# CONFIG_SND_PXA2XX_AC97 is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=m
-CONFIG_SND_SOC_AC97_BUS=y
-CONFIG_SND_PXA2XX_SOC=m
-CONFIG_SND_PXA2XX_SOC_AC97=m
-CONFIG_SND_PXA2XX_SOC_EM_X270=m
-CONFIG_SND_SOC_I2C_AND_SPI=m
-# CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_WM9712=m
-# CONFIG_SOUND_PRIME is not set
-CONFIG_AC97_BUS=m
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-# CONFIG_DRAGONRISE_FF is not set
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KYE=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LOGITECH=y
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_PANTHERLORD=y
-# CONFIG_PANTHERLORD_FF is not set
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-# CONFIG_GREENASIA_FF is not set
-CONFIG_HID_SMARTJOYPLUS=y
-# CONFIG_SMARTJOYPLUS_FF is not set
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-# CONFIG_THRUSTMASTER_FF is not set
-CONFIG_HID_WACOM=m
-CONFIG_HID_ZEROPLUS=y
-# CONFIG_ZEROPLUS_FF is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-# CONFIG_USB_DEVICE_CLASS is not set
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-CONFIG_USB_MON=y
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-# CONFIG_USB_GADGET is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_NOP_USB_XCEIV is not set
-CONFIG_MMC=m
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=m
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_PXA=m
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_AT91 is not set
-# CONFIG_MMC_ATMELMCI is not set
-# CONFIG_MEMSTICK is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_PCA9532 is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_GPIO_PLATFORM=y
-# CONFIG_LEDS_LP3944 is not set
-# CONFIG_LEDS_PCA955X is not set
-# CONFIG_LEDS_DA903X is not set
-# CONFIG_LEDS_DAC124S085 is not set
-# CONFIG_LEDS_BD2802 is not set
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
-# CONFIG_LEDS_TRIGGER_GPIO is not set
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-# CONFIG_RTC_DRV_PCF2123 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-CONFIG_RTC_DRV_V3020=y
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_RTC_DRV_SA1100 is not set
-CONFIG_RTC_DRV_PXA=y
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-
-#
-# TI VLYNQ
-#
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-# CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-# CONFIG_JBD_DEBUG is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-CONFIG_JFFS2_SUMMARY=y
-# CONFIG_JFFS2_FS_XATTR is not set
-# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-# CONFIG_JFFS2_RUBIN is not set
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_XATTR is not set
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-# CONFIG_UBIFS_FS_DEBUG is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-# CONFIG_NFS_V4_1 is not set
-CONFIG_ROOT_NFS=y
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_ACL_SUPPORT=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-CONFIG_SUNRPC_GSS=y
-CONFIG_RPCSEC_GSS_KRB5=y
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-# CONFIG_SMB_NLS_DEFAULT is not set
-CONFIG_CIFS=m
-# CONFIG_CIFS_STATS is not set
-CONFIG_CIFS_WEAK_PW_HASH=y
-# CONFIG_CIFS_XATTR is not set
-# CONFIG_CIFS_DEBUG2 is not set
-# CONFIG_CIFS_EXPERIMENTAL is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=m
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=m
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-CONFIG_DEBUG_FS=y
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-# CONFIG_DETECT_SOFTLOCKUP is not set
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-# CONFIG_DEBUG_HIGHMEM is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
-# CONFIG_DYNAMIC_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARM_UNWIND=y
-CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_ERRORS is not set
-# CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=y
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_VMAC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_GHASH is not set
-# CONFIG_CRYPTO_MD4 is not set
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=m
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=m
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-CONFIG_CRYPTO_DES=y
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_ZLIB is not set
-CONFIG_CRYPTO_LZO=y
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_CRC_CCITT is not set
-CONFIG_CRC16=y
-CONFIG_CRC_T10DIF=y
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_NLATTR=y
diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig
deleted file mode 100644
index 11fdb5a..0000000
--- a/arch/arm/configs/colibri_pxa300_defconfig
+++ /dev/null
@@ -1,1155 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.29-rc8
-# Fri Mar 13 16:13:20 2009
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-# CONFIG_SYSVIPC is not set
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_CLASSIC_RCU=y
-# CONFIG_TREE_RCU is not set
-# CONFIG_PREEMPT_RCU is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-# CONFIG_NET_NS is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-# CONFIG_EMBEDDED is not set
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_COMPAT_BRK=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_FREEZER is not set
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_W90X900 is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-
-#
-# Supported PXA3xx Processor Variants
-#
-CONFIG_CPU_PXA300=y
-# CONFIG_CPU_PXA310 is not set
-# CONFIG_CPU_PXA320 is not set
-# CONFIG_CPU_PXA930 is not set
-# CONFIG_CPU_PXA935 is not set
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_VIPER is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_COLIBRI is not set
-CONFIG_MACH_COLIBRI300=y
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_RAUMFELD_PROTO is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_PXA_EZX is not set
-CONFIG_PXA3xx=y
-# CONFIG_PXA_PWM is not set
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSC3=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_IO_36=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_OUTER_CACHE=y
-CONFIG_CACHE_XSC3L2=y
-CONFIG_IWMMXT=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_UNEVICTABLE_LRU=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE="console=ttyS0,115200 rw"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_FREQ is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_COMPAT_NET_DEV_OPS=y
-# CONFIG_PACKET is not set
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-CONFIG_INET_TUNNEL=y
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-CONFIG_IPV6=y
-# CONFIG_IPV6_PRIVACY is not set
-# CONFIG_IPV6_ROUTER_PREF is not set
-# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-# CONFIG_INET6_AH is not set
-# CONFIG_INET6_ESP is not set
-# CONFIG_INET6_IPCOMP is not set
-# CONFIG_IPV6_MIP6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-CONFIG_INET6_XFRM_MODE_TUNNEL=y
-CONFIG_INET6_XFRM_MODE_BEET=y
-# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-CONFIG_IPV6_SIT=y
-CONFIG_IPV6_NDISC_NODETYPE=y
-# CONFIG_IPV6_TUNNEL is not set
-# CONFIG_IPV6_MULTIPLE_TABLES is not set
-# CONFIG_IPV6_MROUTE is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-# CONFIG_WIRELESS is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-# CONFIG_MTD is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-# CONFIG_BLK_DEV_LOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-CONFIG_CHR_DEV_SG=y
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_LIBFC is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_AX88796=y
-# CONFIG_AX88796_93CX6 is not set
-# CONFIG_SMC91X is not set
-# CONFIG_DM9000 is not set
-# CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-# CONFIG_USB_USBNET is not set
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-# CONFIG_INPUT_TOUCHSCREEN is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-# CONFIG_INPUT_UINPUT is not set
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=y
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=y
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
-# CONFIG_SPI is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-CONFIG_DEBUG_GPIO=y
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_OVERLAY is not set
-# CONFIG_FB_PXA_SMARTPANEL is not set
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_W100 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-CONFIG_LOGO_LINUX_MONO=y
-CONFIG_LOGO_LINUX_VGA16=y
-CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_SOUND is not set
-# CONFIG_HID_SUPPORT is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_OTG is not set
-CONFIG_USB_MON=y
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_OHCI_HCD is not set
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
-#
-
-#
-# see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_PHIDGET is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-# CONFIG_USB_GADGET is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_USB_GPIO_VBUS is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-# CONFIG_MMC_BLOCK_BOUNCE is not set
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_PXA=y
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
-# CONFIG_NEW_LEDS is not set
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_REGULATOR is not set
-# CONFIG_UIO is not set
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-# CONFIG_EXT2_FS is not set
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-CONFIG_ROOT_NFS=y
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_SUNRPC_REGISTER_V4 is not set
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_NLS is not set
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-
-#
-# Tracers
-#
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_BOOT_TRACER is not set
-# CONFIG_TRACE_BRANCH_PROFILING is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=y
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-# CONFIG_CRYPTO_DEFLATE is not set
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig
index 82ca6c8..82d6ea5 100644
--- a/arch/arm/configs/pxa3xx_defconfig
+++ b/arch/arm/configs/pxa3xx_defconfig
@@ -1,15 +1,16 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.31-rc1
-# Mon Jul 13 22:48:49 2009
+# Linux kernel version: 2.6.35-rc1
+# Sat Jun  5 15:29:03 2010
 #
 CONFIG_ARM=y
 CONFIG_HAVE_PWM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
 CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
 CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
+CONFIG_HAVE_PROC_CPU=y
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -18,8 +19,10 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
@@ -31,10 +34,16 @@ CONFIG_CONSTRUCTORS=y
 #
 CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
 CONFIG_SWAP=y
 CONFIG_SYSVIPC=y
 CONFIG_SYSVIPC_SYSCTL=y
@@ -46,21 +55,16 @@ CONFIG_SYSVIPC_SYSCTL=y
 #
 # RCU Subsystem
 #
-# CONFIG_CLASSIC_RCU is not set
 CONFIG_TREE_RCU=y
-# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
 # CONFIG_RCU_TRACE is not set
 CONFIG_RCU_FANOUT=32
 # CONFIG_RCU_FANOUT_EXACT is not set
 # CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_PREEMPT_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=18
-CONFIG_GROUP_SCHED=y
-CONFIG_FAIR_GROUP_SCHED=y
-# CONFIG_RT_GROUP_SCHED is not set
-CONFIG_USER_SCHED=y
-# CONFIG_CGROUP_SCHED is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=17
 # CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
@@ -71,8 +75,13 @@ CONFIG_NAMESPACES=y
 # CONFIG_USER_NS is not set
 # CONFIG_PID_NS is not set
 # CONFIG_NET_NS is not set
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_LZO=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
 CONFIG_ANON_INODES=y
 # CONFIG_EMBEDDED is not set
@@ -93,18 +102,21 @@ CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
 CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
 
 #
-# Performance Counters
+# Kernel Performance Events And Counters
 #
+# CONFIG_PERF_EVENTS is not set
+# CONFIG_PERF_COUNTERS is not set
 CONFIG_VM_EVENT_COUNTERS=y
-# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_SLUB_DEBUG=y
 CONFIG_COMPAT_BRK=y
-CONFIG_SLAB=y
-# CONFIG_SLUB is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
 # CONFIG_SLOB is not set
 # CONFIG_PROFILING is not set
-# CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
 CONFIG_HAVE_KPROBES=y
@@ -114,14 +126,17 @@ CONFIG_HAVE_CLK=y
 #
 # GCOV-based kernel profiling
 #
-# CONFIG_SLOW_WORK is not set
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_SLOW_WORK=y
+# CONFIG_SLOW_WORK_DEBUG is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
-# CONFIG_MODULE_UNLOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
 CONFIG_BLOCK=y
@@ -133,25 +148,56 @@ CONFIG_LBDAF=y
 # IO Schedulers
 #
 CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
 CONFIG_IOSCHED_DEADLINE=y
 CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
 # CONFIG_DEFAULT_DEADLINE is not set
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_FREEZER is not set
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_SPIN_UNLOCK is not set
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_READ_UNLOCK is not set
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+# CONFIG_INLINE_WRITE_UNLOCK is not set
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
 
 #
 # System Type
 #
+CONFIG_MMU=y
 # CONFIG_ARCH_AAEC2000 is not set
 # CONFIG_ARCH_INTEGRATOR is not set
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
 # CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
 # CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
 # CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
@@ -167,6 +213,7 @@ CONFIG_DEFAULT_IOSCHED="cfq"
 # CONFIG_ARCH_IXP2000 is not set
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_DOVE is not set
 # CONFIG_ARCH_KIRKWOOD is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
@@ -175,66 +222,91 @@ CONFIG_DEFAULT_IOSCHED="cfq"
 # CONFIG_ARCH_KS8695 is not set
 # CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
 # CONFIG_ARCH_PNX4008 is not set
 CONFIG_ARCH_PXA=y
 # CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
 # CONFIG_ARCH_RPC is not set
 # CONFIG_ARCH_SA1100 is not set
 # CONFIG_ARCH_S3C2410 is not set
 # CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
 # CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
 
 #
 # Intel PXA2xx/PXA3xx Implementations
 #
 
 #
-# Supported PXA3xx Processor Variants
+# Intel/Marvell Dev Platforms (sorted by hardware release time)
 #
-CONFIG_CPU_PXA300=y
-CONFIG_CPU_PXA310=y
-CONFIG_CPU_PXA320=y
-CONFIG_CPU_PXA930=y
-CONFIG_CPU_PXA935=y
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_MACH_STARGATE2 is not set
 # CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
 # CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MP900C is not set
+# CONFIG_MACH_ZYLONITE300 is not set
+# CONFIG_MACH_ZYLONITE320 is not set
+CONFIG_MACH_LITTLETON=y
+CONFIG_MACH_TAVOREVB=y
+CONFIG_MACH_SAAR=y
+
+#
+# Third Party Dev Platforms (sorted by vendor name)
+#
 # CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_PXA_SHARPSL is not set
 # CONFIG_ARCH_VIPER is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_H5000 is not set
+# CONFIG_MACH_ARCOM_ZEUS is not set
+# CONFIG_MACH_BALLOON3 is not set
+# CONFIG_MACH_CSB726 is not set
+# CONFIG_MACH_ARMCORE is not set
 # CONFIG_MACH_EM_X270 is not set
 # CONFIG_MACH_EXEDA is not set
+CONFIG_MACH_CM_X300=y
+# CONFIG_MACH_CAPC7117 is not set
+# CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_MACH_INTELMOTE2 is not set
+# CONFIG_MACH_STARGATE2 is not set
+# CONFIG_MACH_XCEP is not set
+# CONFIG_TRIZEPS_PXA is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_PCM027 is not set
 # CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_COLIBRI300 is not set
+CONFIG_MACH_COLIBRI300=y
 # CONFIG_MACH_COLIBRI320 is not set
-CONFIG_MACH_ZYLONITE=y
-CONFIG_MACH_LITTLETON=y
-CONFIG_MACH_TAVOREVB=y
-CONFIG_MACH_SAAR=y
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_CM_X300 is not set
+# CONFIG_MACH_VPAC270 is not set
+
+#
+# End-user Products (sorted by vendor name)
+#
 # CONFIG_MACH_H4700 is not set
-# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_H5000 is not set
 # CONFIG_MACH_HIMALAYA is not set
+# CONFIG_MACH_MAGICIAN is not set
 # CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_MACH_CSB726 is not set
 # CONFIG_PXA_EZX is not set
+# CONFIG_MACH_MP900C is not set
+# CONFIG_ARCH_PXA_PALM is not set
+CONFIG_MACH_RAUMFELD_RC=y
+CONFIG_MACH_RAUMFELD_CONNECTOR=y
+CONFIG_MACH_RAUMFELD_SPEAKER=y
+# CONFIG_PXA_SHARPSL is not set
+# CONFIG_MACH_ICONTROL is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_MACH_ZIPIT2 is not set
 CONFIG_PXA3xx=y
+CONFIG_CPU_PXA300=y
+CONFIG_CPU_PXA310=y
+CONFIG_CPU_PXA930=y
 CONFIG_PXA_SSP=y
-CONFIG_PXA_HAVE_BOARD_IRQS=y
 CONFIG_PLAT_PXA=y
 
 #
@@ -243,7 +315,7 @@ CONFIG_PLAT_PXA=y
 CONFIG_CPU_XSC3=y
 CONFIG_CPU_32v5=y
 CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_PABRT_LEGACY=y
 CONFIG_CPU_CACHE_VIVT=y
 CONFIG_CPU_TLB_V4WBI=y
 CONFIG_CPU_CP15=y
@@ -258,6 +330,7 @@ CONFIG_ARM_THUMB=y
 # CONFIG_CPU_BPREDICT_DISABLE is not set
 CONFIG_OUTER_CACHE=y
 CONFIG_CACHE_XSC3L2=y
+CONFIG_ARM_L1_CACHE_SHIFT=5
 CONFIG_IWMMXT=y
 CONFIG_COMMON_CLKDEV=y
 
@@ -272,20 +345,22 @@ CONFIG_COMMON_CLKDEV=y
 # Kernel Features
 #
 CONFIG_TICK_ONESHOT=y
-# CONFIG_NO_HZ is not set
+CONFIG_NO_HZ=y
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
 CONFIG_VMSPLIT_3G=y
 # CONFIG_VMSPLIT_2G is not set
 # CONFIG_VMSPLIT_1G is not set
 CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PREEMPT=y
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
 CONFIG_HZ=100
 CONFIG_AEABI=y
 CONFIG_OABI_COMPAT=y
 # CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
 # CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
+CONFIG_HIGHMEM=y
 CONFIG_SELECT_MEMORY_MODEL=y
 CONFIG_FLATMEM_MANUAL=y
 # CONFIG_DISCONTIGMEM_MANUAL is not set
@@ -293,12 +368,12 @@ CONFIG_FLATMEM_MANUAL=y
 CONFIG_FLATMEM=y
 CONFIG_FLAT_NODE_MEM_MAP=y
 CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
+CONFIG_SPLIT_PTLOCK_CPUS=999999
 # CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+# CONFIG_KSM is not set
 CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 CONFIG_ALIGNMENT_TRAP=y
 # CONFIG_UACCESS_WITH_MEMCPY is not set
@@ -306,17 +381,34 @@ CONFIG_ALIGNMENT_TRAP=y
 #
 # Boot options
 #
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=64M debug"
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE=""
+# CONFIG_CMDLINE_FORCE is not set
 # CONFIG_XIP_KERNEL is not set
 # CONFIG_KEXEC is not set
 
 #
 # CPU Power Management
 #
-# CONFIG_CPU_FREQ is not set
-# CONFIG_CPU_IDLE is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+# CONFIG_CPU_FREQ_DEBUG is not set
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
 
 #
 # Floating point emulation
@@ -341,7 +433,14 @@ CONFIG_HAVE_AOUT=y
 #
 # Power management options
 #
-# CONFIG_PM is not set
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+# CONFIG_PM_RUNTIME is not set
+CONFIG_PM_OPS=y
 CONFIG_ARCH_SUSPEND_POSSIBLE=y
 CONFIG_NET=y
 
@@ -349,42 +448,69 @@ CONFIG_NET=y
 # Networking options
 #
 CONFIG_PACKET=y
-# CONFIG_PACKET_MMAP is not set
 CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
 # CONFIG_NET_KEY is not set
 CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
+CONFIG_IP_MULTICAST=y
 # CONFIG_IP_ADVANCED_ROUTER is not set
 CONFIG_IP_FIB_HASH=y
 CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
 # CONFIG_NET_IPIP is not set
 # CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
 # CONFIG_ARPD is not set
-# CONFIG_SYN_COOKIES is not set
+CONFIG_SYN_COOKIES=y
 # CONFIG_INET_AH is not set
 # CONFIG_INET_ESP is not set
 # CONFIG_INET_IPCOMP is not set
 # CONFIG_INET_XFRM_TUNNEL is not set
-# CONFIG_INET_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
 # CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
 # CONFIG_TCP_CONG_ADVANCED is not set
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IPV6 is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
 # CONFIG_NETWORK_SECMARK is not set
 # CONFIG_NETFILTER is not set
 # CONFIG_IP_DCCP is not set
 # CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
+# CONFIG_L2TP is not set
 # CONFIG_BRIDGE is not set
 # CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
@@ -408,12 +534,60 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_HAMRADIO is not set
 # CONFIG_CAN is not set
 # CONFIG_IRDA is not set
-# CONFIG_BT is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+# CONFIG_BT_L2CAP_EXT_FEATURES is not set
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIBTUSB=m
+# CONFIG_BT_HCIBTSDIO is not set
+# CONFIG_BT_HCIUART is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_BT_ATH3K is not set
 # CONFIG_AF_RXRPC is not set
-# CONFIG_WIRELESS is not set
+CONFIG_WIRELESS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_CORE=y
+CONFIG_WEXT_PROC=y
+CONFIG_WEXT_SPY=y
+CONFIG_CFG80211=y
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+CONFIG_CFG80211_REG_DEBUG=y
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+CONFIG_CFG80211_WEXT=y
+CONFIG_WIRELESS_EXT_SYSFS=y
+CONFIG_LIB80211=y
+# CONFIG_LIB80211_DEBUG is not set
+CONFIG_MAC80211=y
+CONFIG_MAC80211_HAS_RC=y
+CONFIG_MAC80211_RC_MINSTREL=y
+# CONFIG_MAC80211_RC_DEFAULT_PID is not set
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
 # CONFIG_WIMAX is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
 
 #
 # Device Drivers
@@ -423,8 +597,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
 # Generic Driver Options
 #
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_STANDALONE is not set
-# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
 CONFIG_FW_LOADER=y
 CONFIG_FIRMWARE_IN_KERNEL=y
 CONFIG_EXTRA_FIRMWARE=""
@@ -434,9 +609,9 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_CONNECTOR is not set
 CONFIG_MTD=y
 # CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
 CONFIG_MTD_CONCAT=y
 CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_TESTS is not set
 # CONFIG_MTD_REDBOOT_PARTS is not set
 # CONFIG_MTD_CMDLINE_PARTS is not set
 # CONFIG_MTD_AFS_PARTS is not set
@@ -449,10 +624,12 @@ CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
-# CONFIG_NFTL is not set
+CONFIG_NFTL=y
+CONFIG_NFTL_RW=y
 # CONFIG_INFTL is not set
 # CONFIG_RFD_FTL is not set
 # CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
 # CONFIG_MTD_OOPS is not set
 
 #
@@ -485,10 +662,11 @@ CONFIG_MTD_CFI_I2=y
 #
 # CONFIG_MTD_DATAFLASH is not set
 # CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
 # CONFIG_MTD_SLRAM is not set
 # CONFIG_MTD_PHRAM is not set
 # CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
+CONFIG_MTD_BLOCK2MTD=y
 
 #
 # Disk-On-Chip Device Drivers
@@ -497,9 +675,12 @@ CONFIG_MTD_CFI_I2=y
 # CONFIG_MTD_DOC2001 is not set
 # CONFIG_MTD_DOC2001PLUS is not set
 CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
+CONFIG_MTD_NAND_ECC=y
 # CONFIG_MTD_NAND_ECC_SMC is not set
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_SM_COMMON is not set
 # CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018
 # CONFIG_MTD_NAND_H1900 is not set
 # CONFIG_MTD_NAND_GPIO is not set
 CONFIG_MTD_NAND_IDS=y
@@ -509,6 +690,7 @@ CONFIG_MTD_NAND_PXA3xx=y
 CONFIG_MTD_NAND_PXA3xx_BUILTIN=y
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
 CONFIG_MTD_ONENAND=y
 CONFIG_MTD_ONENAND_VERIFY_WRITE=y
 CONFIG_MTD_ONENAND_GENERIC=y
@@ -524,13 +706,26 @@ CONFIG_MTD_ONENAND_GENERIC=y
 #
 # UBI - Unsorted block images
 #
-# CONFIG_MTD_UBI is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
 # CONFIG_PARPORT is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
 CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
 # CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_UB is not set
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=16
 CONFIG_BLK_DEV_RAM_SIZE=4096
@@ -538,17 +733,69 @@ CONFIG_BLK_DEV_RAM_SIZE=4096
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
 # CONFIG_MG_DISK is not set
-# CONFIG_MISC_DEVICES is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+CONFIG_ISL29003=y
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_DS1682 is not set
+CONFIG_TI_DAC7512=y
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_AT25 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_IWMC3200TOP is not set
 CONFIG_HAVE_IDE=y
 # CONFIG_IDE is not set
 
 #
 # SCSI device support
 #
+CONFIG_SCSI_MOD=y
 # CONFIG_RAID_ATTRS is not set
-# CONFIG_SCSI is not set
-# CONFIG_SCSI_DMA is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
 # CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
 # CONFIG_ATA is not set
 # CONFIG_MD is not set
 CONFIG_NETDEVICES=y
@@ -558,16 +805,39 @@ CONFIG_NETDEVICES=y
 # CONFIG_EQUALIZER is not set
 # CONFIG_TUN is not set
 # CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-# CONFIG_AX88796 is not set
+CONFIG_AX88796=y
+# CONFIG_AX88796_93CX6 is not set
 CONFIG_SMC91X=y
-# CONFIG_DM9000 is not set
+CONFIG_DM9000=y
+CONFIG_DM9000_DEBUGLEVEL=0
+CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
 # CONFIG_ENC28J60 is not set
 # CONFIG_ETHOC is not set
 # CONFIG_SMC911X is not set
-# CONFIG_SMSC911X is not set
+CONFIG_SMSC911X=y
 # CONFIG_DNET is not set
 # CONFIG_IBM_NEW_EMAC_ZMII is not set
 # CONFIG_IBM_NEW_EMAC_RGMII is not set
@@ -578,18 +848,67 @@ CONFIG_SMC91X=y
 # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
 # CONFIG_B44 is not set
 # CONFIG_KS8842 is not set
+# CONFIG_KS8851 is not set
+# CONFIG_KS8851_MLL is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_ATH_COMMON is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IWM is not set
+CONFIG_LIBERTAS=y
+# CONFIG_LIBERTAS_USB is not set
+CONFIG_LIBERTAS_SDIO=m
+# CONFIG_LIBERTAS_SPI is not set
+# CONFIG_LIBERTAS_DEBUG is not set
+# CONFIG_LIBERTAS_MESH is not set
+# CONFIG_P54_COMMON is not set
+# CONFIG_RT2X00 is not set
+# CONFIG_WL12XX is not set
+# CONFIG_ZD1211RW is not set
 
 #
-# Wireless LAN
+# Enable WiMAX (Networking options) to see the WiMAX drivers
 #
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
 
 #
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_CDCETHER=y
+# CONFIG_USB_NET_CDC_EEM is not set
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_SMSC75XX is not set
+# CONFIG_USB_NET_SMSC95XX is not set
+# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_NET1080=y
+# CONFIG_USB_NET_PLUSB is not set
+CONFIG_USB_NET_MCS7830=y
+# CONFIG_USB_NET_RNDIS_HOST is not set
+CONFIG_USB_NET_CDC_SUBSET=y
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=y
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_SIERRA_NET is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -597,39 +916,47 @@ CONFIG_SMC91X=y
 # CONFIG_NETPOLL is not set
 # CONFIG_NET_POLL_CONTROLLER is not set
 # CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
 
 #
 # Input device support
 #
 CONFIG_INPUT=y
 # CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_SPARSEKMAP is not set
 
 #
 # Userland interfaces
 #
 CONFIG_INPUT_MOUSEDEV=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
 # CONFIG_INPUT_JOYDEV is not set
-# CONFIG_INPUT_EVDEV is not set
+CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_EVBUG is not set
 
 #
 # Input Device Drivers
 #
 CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_ADP5588 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_QT2160 is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
 # CONFIG_KEYBOARD_LM8323 is not set
-CONFIG_KEYBOARD_PXA27x=y
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+CONFIG_KEYBOARD_PXA27x=m
 CONFIG_KEYBOARD_PXA930_ROTARY=y
-CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
 CONFIG_INPUT_MOUSE=y
 CONFIG_MOUSE_PS2=y
 CONFIG_MOUSE_PS2_ALPS=y
@@ -637,8 +964,11 @@ CONFIG_MOUSE_PS2_LOGIPS2PP=y
 CONFIG_MOUSE_PS2_SYNAPTICS=y
 CONFIG_MOUSE_PS2_TRACKPOINT=y
 # CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_SENTELIC is not set
 # CONFIG_MOUSE_PS2_TOUCHKIT is not set
 # CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
 # CONFIG_MOUSE_VSXXXAA is not set
 # CONFIG_MOUSE_GPIO is not set
 CONFIG_MOUSE_PXA930_TRKBALL=y
@@ -652,21 +982,41 @@ CONFIG_INPUT_TOUCHSCREEN=y
 # CONFIG_TOUCHSCREEN_AD7879_SPI is not set
 # CONFIG_TOUCHSCREEN_AD7879 is not set
 CONFIG_TOUCHSCREEN_DA9034=y
-# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+CONFIG_TOUCHSCREEN_EETI=m
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
 # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
 # CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+CONFIG_TOUCHSCREEN_WM97XX=m
+CONFIG_TOUCHSCREEN_WM9705=y
+CONFIG_TOUCHSCREEN_WM9712=y
+CONFIG_TOUCHSCREEN_WM9713=y
+# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
 # CONFIG_TOUCHSCREEN_TSC2007 is not set
 # CONFIG_TOUCHSCREEN_W90X900 is not set
-# CONFIG_INPUT_MISC is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+# CONFIG_INPUT_UINPUT is not set
+# CONFIG_INPUT_PCF8574 is not set
+CONFIG_INPUT_GPIO_ROTARY_ENCODER=y
 
 #
 # Hardware I/O ports
@@ -675,6 +1025,7 @@ CONFIG_SERIO=y
 CONFIG_SERIO_SERPORT=y
 CONFIG_SERIO_LIBPS2=y
 # CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
 # CONFIG_GAMEPORT is not set
 
 #
@@ -687,6 +1038,7 @@ CONFIG_HW_CONSOLE=y
 # CONFIG_VT_HW_CONSOLE_BINDING is not set
 CONFIG_DEVKMEM=y
 # CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
 
 #
 # Serial drivers
@@ -701,25 +1053,25 @@ CONFIG_SERIAL_PXA=y
 CONFIG_SERIAL_PXA_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
 CONFIG_UNIX98_PTYS=y
 # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-# CONFIG_LEGACY_PTYS is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
 # CONFIG_IPMI_HANDLER is not set
-# CONFIG_HW_RANDOM is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
+# CONFIG_RAMOOPS is not set
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_CHARDEV is not set
-# CONFIG_I2C_HELPER_AUTO is not set
-
-#
-# I2C Algorithms
-#
-# CONFIG_I2C_ALGOBIT is not set
-# CONFIG_I2C_ALGOPCF is not set
-# CONFIG_I2C_ALGOPCA is not set
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
 
 #
 # I2C Hardware Bus support
@@ -734,59 +1086,67 @@ CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_PXA=y
 # CONFIG_I2C_PXA_SLAVE is not set
 # CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
 
 #
 # External I2C/SMBus adapter drivers
 #
 # CONFIG_I2C_PARPORT_LIGHT is not set
 # CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
 
 #
 # Other I2C/SMBus bus drivers
 #
 # CONFIG_I2C_PCA_PLATFORM is not set
 # CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_TSL2550 is not set
 # CONFIG_I2C_DEBUG_CORE is not set
 # CONFIG_I2C_DEBUG_ALGO is not set
 # CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
 CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_DEBUG=y
 CONFIG_SPI_MASTER=y
 
 #
 # SPI Master Controller Drivers
 #
-# CONFIG_SPI_BITBANG is not set
-# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_BITBANG=y
+CONFIG_SPI_GPIO=y
 CONFIG_SPI_PXA2XX=y
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
 
 #
 # SPI Protocol Masters
 #
-# CONFIG_SPI_SPIDEV is not set
+CONFIG_SPI_SPIDEV=y
 # CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
 CONFIG_ARCH_REQUIRE_GPIOLIB=y
 CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_MAX730X=y
 
 #
 # Memory mapped GPIO expanders:
 #
+# CONFIG_GPIO_IT8761E is not set
 
 #
 # I2C GPIO expanders:
 #
+# CONFIG_GPIO_MAX7300 is not set
 CONFIG_GPIO_MAX732X=y
+# CONFIG_GPIO_MAX732X_IRQ is not set
 CONFIG_GPIO_PCA953X=y
+# CONFIG_GPIO_PCA953X_IRQ is not set
 CONFIG_GPIO_PCF857X=y
+# CONFIG_GPIO_ADP5588 is not set
 
 #
 # PCI GPIO expanders:
@@ -797,17 +1157,121 @@ CONFIG_GPIO_PCF857X=y
 #
 CONFIG_GPIO_MAX7301=y
 # CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_W1 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+CONFIG_W1=m
+
+#
+# 1-wire Bus Masters
+#
+# CONFIG_W1_MASTER_DS2490 is not set
+# CONFIG_W1_MASTER_DS2482 is not set
+# CONFIG_W1_MASTER_DS1WM is not set
+CONFIG_W1_MASTER_GPIO=m
+
+#
+# 1-wire Slaves
+#
+# CONFIG_W1_SLAVE_THERM is not set
+# CONFIG_W1_SLAVE_SMEM is not set
+# CONFIG_W1_SLAVE_DS2431 is not set
+# CONFIG_W1_SLAVE_DS2433 is not set
+CONFIG_W1_SLAVE_DS2760=m
+# CONFIG_W1_SLAVE_BQ27000 is not set
 CONFIG_POWER_SUPPLY=y
 CONFIG_POWER_SUPPLY_DEBUG=y
 CONFIG_PDA_POWER=y
-# CONFIG_BATTERY_DS2760 is not set
+# CONFIG_APM_POWER is not set
+# CONFIG_TEST_POWER is not set
+CONFIG_BATTERY_DS2760=m
+# CONFIG_BATTERY_DS2782 is not set
 # CONFIG_BATTERY_BQ27x00 is not set
 CONFIG_BATTERY_DA9030=y
 # CONFIG_BATTERY_MAX17040 is not set
-# CONFIG_HWMON is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+CONFIG_SENSORS_LIS3_SPI=y
+# CONFIG_SENSORS_LIS3_I2C is not set
 # CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
 CONFIG_SSB_POSSIBLE=y
 
@@ -815,27 +1279,49 @@ CONFIG_SSB_POSSIBLE=y
 # Sonics Silicon Backplane
 #
 # CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
+CONFIG_MFD_SUPPORT=y
 # CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_UCB1400_CORE is not set
 # CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
 # CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TC35892 is not set
 # CONFIG_MFD_TMIO is not set
 # CONFIG_MFD_T7L66XB is not set
 # CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
 CONFIG_PMIC_DA903X=y
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
 # CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
 # CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
 # CONFIG_MFD_PCF50633 is not set
-# CONFIG_AB3100_CORE is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_ABX500_CORE is not set
 # CONFIG_EZX_PCAP is not set
+# CONFIG_AB8500_CORE is not set
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_DEBUG=y
+# CONFIG_REGULATOR_DUMMY is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_BQ24022 is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+CONFIG_REGULATOR_MAX8660=y
+CONFIG_REGULATOR_DA903X=y
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
 # CONFIG_MEDIA_SUPPORT is not set
 
 #
@@ -878,15 +1364,18 @@ CONFIG_FB_PXA=y
 # CONFIG_FB_BROADSHEET is not set
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
 # CONFIG_LCD_LTV350QV is not set
-# CONFIG_LCD_ILI9320 is not set
 CONFIG_LCD_TDO24M=y
 # CONFIG_LCD_VGG2432A4 is not set
 # CONFIG_LCD_PLATFORM is not set
+# CONFIG_LCD_S6E63M0 is not set
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_BACKLIGHT_GENERIC is not set
 CONFIG_BACKLIGHT_PWM=y
-CONFIG_BACKLIGHT_DA903X=y
+CONFIG_BACKLIGHT_DA903X=m
+# CONFIG_BACKLIGHT_ADP8860 is not set
 
 #
 # Display device support
@@ -902,8 +1391,8 @@ CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
 CONFIG_FONTS=y
-# CONFIG_FONT_8x8 is not set
-# CONFIG_FONT_8x16 is not set
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
 CONFIG_FONT_6x11=y
 # CONFIG_FONT_7x14 is not set
 # CONFIG_FONT_PEARL_8x8 is not set
@@ -916,9 +1405,228 @@ CONFIG_LOGO=y
 CONFIG_LOGO_LINUX_MONO=y
 CONFIG_LOGO_LINUX_VGA16=y
 CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_SOUND is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+CONFIG_SND_VMASTER=y
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_AC97_CODEC=y
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+# CONFIG_SND_AC97_POWER_SAVE is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_PXA2XX_LIB=y
+CONFIG_SND_PXA2XX_LIB_AC97=y
+# CONFIG_SND_PXA2XX_AC97 is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_AC97_BUS=y
+CONFIG_SND_PXA2XX_SOC=y
+CONFIG_SND_PXA2XX_SOC_AC97=m
+CONFIG_SND_PXA_SOC_SSP=y
+CONFIG_SND_PXA2XX_SOC_EM_X270=m
+CONFIG_SND_SOC_RAUMFELD=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_AK4104=y
+CONFIG_SND_SOC_CS4270=y
+CONFIG_SND_SOC_WM9712=m
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HIDRAW is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+# CONFIG_USB_HIDDEV is not set
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_3M_PCT is not set
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+# CONFIG_HID_CANDO is not set
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+# CONFIG_HID_PRODIKEYS is not set
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DRAGONRISE=y
+# CONFIG_DRAGONRISE_FF is not set
+# CONFIG_HID_EGALAX is not set
+CONFIG_HID_EZKEY=y
+CONFIG_HID_KYE=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_TWINHAN=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LOGITECH=y
+# CONFIG_LOGITECH_FF is not set
+# CONFIG_LOGIRUMBLEPAD2_FF is not set
+# CONFIG_LOGIG940_FF is not set
+# CONFIG_HID_MAGICMOUSE is not set
+CONFIG_HID_MICROSOFT=y
+# CONFIG_HID_MOSART is not set
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_NTRIG=y
+# CONFIG_HID_ORTEK is not set
+CONFIG_HID_PANTHERLORD=y
+# CONFIG_PANTHERLORD_FF is not set
+CONFIG_HID_PETALYNX=y
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_QUANTA is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_ROCCAT_KONE is not set
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+# CONFIG_HID_STANTUM is not set
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
+# CONFIG_GREENASIA_FF is not set
+CONFIG_HID_SMARTJOYPLUS=y
+# CONFIG_SMARTJOYPLUS_FF is not set
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
+# CONFIG_THRUSTMASTER_FF is not set
+CONFIG_HID_WACOM=m
+# CONFIG_HID_WACOM_POWER_SUPPLY is not set
+CONFIG_HID_ZEROPLUS=y
+# CONFIG_ZEROPLUS_FF is not set
+# CONFIG_HID_ZYDACRON is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_DEVICE_CLASS=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+CONFIG_USB_MON=y
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_ISD200=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
 CONFIG_MMC=y
 # CONFIG_MMC_DEBUG is not set
 # CONFIG_MMC_UNSAFE_RESUME is not set
@@ -934,62 +1642,138 @@ CONFIG_MMC_BLOCK_BOUNCE=y
 #
 # MMC/SD/SDIO Host Controller Drivers
 #
-CONFIG_MMC_PXA=y
+CONFIG_MMC_PXA=m
 # CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_SPI is not set
 # CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
 CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=m
+CONFIG_LEDS_CLASS=y
 
 #
 # LED drivers
 #
 # CONFIG_LEDS_PCA9532 is not set
-CONFIG_LEDS_GPIO=m
+CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_GPIO_PLATFORM=y
-# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP3944 is not set
 # CONFIG_LEDS_PCA955X is not set
 CONFIG_LEDS_DA903X=m
 # CONFIG_LEDS_DAC124S085 is not set
 # CONFIG_LEDS_PWM is not set
+# CONFIG_LEDS_REGULATOR is not set
 # CONFIG_LEDS_BD2802 is not set
+CONFIG_LEDS_LT3593=y
+CONFIG_LEDS_TRIGGERS=y
 
 #
 # LED Triggers
 #
-CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_LEDS_TRIGGER_BACKLIGHT=m
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
 CONFIG_LEDS_TRIGGER_GPIO=m
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
 
 #
 # iptables trigger is under Netfilter config (LED target)
 #
+# CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+CONFIG_RTC_DRV_V3020=y
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_SA1100 is not set
+CONFIG_RTC_DRV_PXA=y
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+# CONFIG_TIMB_DMA is not set
 # CONFIG_AUXDISPLAY is not set
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DEBUG=y
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-CONFIG_REGULATOR_DA903X=y
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_UIO is not set
+CONFIG_UIO=y
+# CONFIG_UIO_PDRV is not set
+# CONFIG_UIO_PDRV_GENIRQ is not set
 # CONFIG_STAGING is not set
 
 #
 # File systems
 #
-# CONFIG_EXT2_FS is not set
-# CONFIG_EXT3_FS is not set
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
 # CONFIG_EXT4_FS is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 CONFIG_FS_POSIX_ACL=y
@@ -997,10 +1781,11 @@ CONFIG_FS_POSIX_ACL=y
 # CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
 # CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 CONFIG_FILE_LOCKING=y
 CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
-# CONFIG_INOTIFY is not set
+CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
 # CONFIG_QUOTA is not set
 # CONFIG_AUTOFS_FS is not set
@@ -1010,7 +1795,14 @@ CONFIG_INOTIFY_USER=y
 #
 # Caches
 #
-# CONFIG_FSCACHE is not set
+CONFIG_FSCACHE=y
+CONFIG_FSCACHE_STATS=y
+# CONFIG_FSCACHE_HISTOGRAM is not set
+# CONFIG_FSCACHE_DEBUG is not set
+# CONFIG_FSCACHE_OBJECT_LIST is not set
+CONFIG_CACHEFILES=y
+# CONFIG_CACHEFILES_DEBUG is not set
+# CONFIG_CACHEFILES_HISTOGRAM is not set
 
 #
 # CD-ROM/DVD Filesystems
@@ -1021,8 +1813,11 @@ CONFIG_INOTIFY_USER=y
 #
 # DOS/FAT/NT Filesystems
 #
-# CONFIG_MSDOS_FS is not set
-# CONFIG_VFAT_FS is not set
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 # CONFIG_NTFS_FS is not set
 
 #
@@ -1032,7 +1827,8 @@ CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
 CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
-# CONFIG_TMPFS is not set
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
 CONFIG_MISC_FILESYSTEMS=y
@@ -1047,7 +1843,7 @@ CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_DEBUG=0
 CONFIG_JFFS2_FS_WRITEBUFFER=y
 CONFIG_JFFS2_FS_WBUF_VERIFY=y
-# CONFIG_JFFS2_SUMMARY is not set
+CONFIG_JFFS2_SUMMARY=y
 # CONFIG_JFFS2_FS_XATTR is not set
 CONFIG_JFFS2_COMPRESSION_OPTIONS=y
 CONFIG_JFFS2_ZLIB=y
@@ -1058,6 +1854,13 @@ CONFIG_JFFS2_RUBIN=y
 CONFIG_JFFS2_CMODE_PRIORITY=y
 # CONFIG_JFFS2_CMODE_SIZE is not set
 # CONFIG_JFFS2_CMODE_FAVOURLZO is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_LOGFS is not set
 # CONFIG_CRAMFS is not set
 # CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
@@ -1068,7 +1871,6 @@ CONFIG_JFFS2_CMODE_PRIORITY=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
-# CONFIG_NILFS2_FS is not set
 CONFIG_NETWORK_FILESYSTEMS=y
 CONFIG_NFS_FS=y
 CONFIG_NFS_V3=y
@@ -1076,6 +1878,7 @@ CONFIG_NFS_V3_ACL=y
 CONFIG_NFS_V4=y
 # CONFIG_NFS_V4_1 is not set
 CONFIG_ROOT_NFS=y
+CONFIG_NFS_FSCACHE=y
 # CONFIG_NFSD is not set
 CONFIG_LOCKD=y
 CONFIG_LOCKD_V4=y
@@ -1085,8 +1888,15 @@ CONFIG_SUNRPC=y
 CONFIG_SUNRPC_GSS=y
 CONFIG_RPCSEC_GSS_KRB5=y
 # CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+# CONFIG_CEPH_FS is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+CONFIG_CIFS_WEAK_PW_HASH=y
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
 # CONFIG_NCP_FS is not set
 # CONFIG_CODA_FS is not set
 # CONFIG_AFS_FS is not set
@@ -1094,48 +1904,64 @@ CONFIG_RPCSEC_GSS_KRB5=y
 #
 # Partition Types
 #
-# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
 CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
 CONFIG_NLS=y
 CONFIG_NLS_DEFAULT="iso8859-1"
-# CONFIG_NLS_CODEPAGE_437 is not set
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-# CONFIG_NLS_ISO8859_1 is not set
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_UTF8=y
 # CONFIG_DLM is not set
 
 #
@@ -1146,8 +1972,9 @@ CONFIG_ENABLE_WARN_DEPRECATED=y
 CONFIG_ENABLE_MUST_CHECK=y
 CONFIG_FRAME_WARN=1024
 CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
 # CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
+CONFIG_DEBUG_FS=y
 # CONFIG_HEADERS_CHECK is not set
 CONFIG_DEBUG_KERNEL=y
 CONFIG_DEBUG_SHIRQ=y
@@ -1157,13 +1984,13 @@ CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=1
 CONFIG_DETECT_HUNG_TASK=y
 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
 CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-# CONFIG_SCHED_DEBUG is not set
+CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_DEBUG_SLAB is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
 # CONFIG_DEBUG_KMEMLEAK is not set
-CONFIG_DEBUG_PREEMPT=y
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 CONFIG_DEBUG_SPINLOCK=y
@@ -1174,35 +2001,55 @@ CONFIG_DEBUG_SPINLOCK=y
 CONFIG_DEBUG_SPINLOCK_SLEEP=y
 # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
 # CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
 CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
+CONFIG_DEBUG_INFO=y
 # CONFIG_DEBUG_VM is not set
 # CONFIG_DEBUG_WRITECOUNT is not set
 CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
 # CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
 # CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
 # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_PAGE_POISONING is not set
 CONFIG_HAVE_FUNCTION_TRACER=y
 CONFIG_TRACING_SUPPORT=y
-# CONFIG_FTRACE is not set
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
-# CONFIG_KMEMCHECK is not set
 CONFIG_ARM_UNWIND=y
 CONFIG_DEBUG_USER=y
-# CONFIG_DEBUG_ERRORS is not set
+CONFIG_DEBUG_ERRORS=y
 # CONFIG_DEBUG_STACK_USAGE is not set
-# CONFIG_DEBUG_LL is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_EARLY_PRINTK is not set
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_OC_ETM is not set
 
 #
 # Security options
@@ -1210,13 +2057,16 @@ CONFIG_DEBUG_USER=y
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
 # CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
 CONFIG_CRYPTO=y
 
 #
 # Crypto core or helper
 #
-# CONFIG_CRYPTO_FIPS is not set
 CONFIG_CRYPTO_ALGAPI=y
 CONFIG_CRYPTO_ALGAPI2=y
 CONFIG_CRYPTO_AEAD2=y
@@ -1248,7 +2098,7 @@ CONFIG_CRYPTO_WORKQUEUE=y
 CONFIG_CRYPTO_CBC=y
 # CONFIG_CRYPTO_CTR is not set
 # CONFIG_CRYPTO_CTS is not set
-# CONFIG_CRYPTO_ECB is not set
+CONFIG_CRYPTO_ECB=y
 # CONFIG_CRYPTO_LRW is not set
 # CONFIG_CRYPTO_PCBC is not set
 # CONFIG_CRYPTO_XTS is not set
@@ -1258,14 +2108,16 @@ CONFIG_CRYPTO_CBC=y
 #
 # CONFIG_CRYPTO_HMAC is not set
 # CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
 
 #
 # Digest
 #
 # CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
 # CONFIG_CRYPTO_MD4 is not set
 CONFIG_CRYPTO_MD5=y
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
+CONFIG_CRYPTO_MICHAEL_MIC=m
 # CONFIG_CRYPTO_RMD128 is not set
 # CONFIG_CRYPTO_RMD160 is not set
 # CONFIG_CRYPTO_RMD256 is not set
@@ -1279,9 +2131,9 @@ CONFIG_CRYPTO_MD5=y
 #
 # Ciphers
 #
-# CONFIG_CRYPTO_AES is not set
+CONFIG_CRYPTO_AES=y
 # CONFIG_CRYPTO_ANUBIS is not set
-# CONFIG_CRYPTO_ARC4 is not set
+CONFIG_CRYPTO_ARC4=y
 # CONFIG_CRYPTO_BLOWFISH is not set
 # CONFIG_CRYPTO_CAMELLIA is not set
 # CONFIG_CRYPTO_CAST5 is not set
@@ -1298,15 +2150,15 @@ CONFIG_CRYPTO_DES=y
 #
 # Compression
 #
-# CONFIG_CRYPTO_DEFLATE is not set
+CONFIG_CRYPTO_DEFLATE=y
 # CONFIG_CRYPTO_ZLIB is not set
-# CONFIG_CRYPTO_LZO is not set
+CONFIG_CRYPTO_LZO=y
 
 #
 # Random Number Generation
 #
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
+CONFIG_CRYPTO_HW=y
 # CONFIG_BINARY_PRINTF is not set
 
 #
@@ -1315,8 +2167,8 @@ CONFIG_CRYPTO_DES=y
 CONFIG_BITREVERSE=y
 CONFIG_GENERIC_FIND_LAST_BIT=y
 # CONFIG_CRC_CCITT is not set
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
 # CONFIG_CRC_ITU_T is not set
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
@@ -1325,7 +2177,12 @@ CONFIG_ZLIB_INFLATE=y
 CONFIG_ZLIB_DEFLATE=y
 CONFIG_LZO_COMPRESS=y
 CONFIG_LZO_DECOMPRESS=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_DECOMPRESS_LZO=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
 CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
diff --git a/arch/arm/configs/raumfeld_defconfig b/arch/arm/configs/raumfeld_defconfig
deleted file mode 100644
index acb1a8f..0000000
--- a/arch/arm/configs/raumfeld_defconfig
+++ /dev/null
@@ -1,1898 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.32-rc5
-# Sun Nov  1 21:57:32 2009
-#
-CONFIG_ARM=y
-CONFIG_HAVE_PWM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_ARCH_HAS_CPUFREQ=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-# CONFIG_LOCALVERSION_AUTO is not set
-# CONFIG_SWAP is not set
-# CONFIG_SYSVIPC is not set
-# CONFIG_POSIX_MQUEUE is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_GROUP_SCHED is not set
-# CONFIG_CGROUPS is not set
-# CONFIG_SYSFS_DEPRECATED_V2 is not set
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-# CONFIG_NET_NS is not set
-# CONFIG_BLK_DEV_INITRD is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-# CONFIG_EMBEDDED is not set
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-
-#
-# Kernel Performance Events And Counters
-#
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_COMPAT_BRK=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-CONFIG_SLOW_WORK=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-# CONFIG_LBDAF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_AS is not set
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_FREEZER=y
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5PC1XX is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_BCMRING is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-
-#
-# Supported PXA3xx Processor Variants
-#
-CONFIG_CPU_PXA300=y
-# CONFIG_CPU_PXA310 is not set
-CONFIG_CPU_PXA320=y
-# CONFIG_CPU_PXA930 is not set
-# CONFIG_CPU_PXA935 is not set
-# CONFIG_CPU_PXA950 is not set
-
-#
-# Intel/Marvell Dev Platforms (sorted by hardware release time)
-#
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-
-#
-# Third Party Dev Platforms (sorted by vendor name)
-#
-# CONFIG_ARCH_PXA_IDP is not set
-# CONFIG_ARCH_VIPER is not set
-# CONFIG_MACH_BALLOON3 is not set
-# CONFIG_MACH_CSB726 is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_EXEDA is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_MACH_INTELMOTE2 is not set
-# CONFIG_MACH_STARGATE2 is not set
-# CONFIG_MACH_XCEP is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_COLIBRI300 is not set
-# CONFIG_MACH_COLIBRI320 is not set
-
-#
-# End-user Products (sorted by vendor name)
-#
-# CONFIG_MACH_H4700 is not set
-# CONFIG_MACH_H5000 is not set
-# CONFIG_MACH_HIMALAYA is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_PXA_EZX is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_ARCH_PXA_PALM is not set
-CONFIG_MACH_RAUMFELD_RC=y
-CONFIG_MACH_RAUMFELD_CONNECTOR=y
-CONFIG_MACH_RAUMFELD_PROTO=y
-CONFIG_MACH_RAUMFELD_SPEAKER=y
-# CONFIG_PXA_SHARPSL is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-CONFIG_PXA3xx=y
-CONFIG_PXA_SSP=y
-CONFIG_PLAT_PXA=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_32=y
-CONFIG_CPU_XSC3=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_LEGACY=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-CONFIG_IO_36=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_OUTER_CACHE=y
-CONFIG_CACHE_XSC3L2=y
-CONFIG_ARM_L1_CACHE_SHIFT=5
-CONFIG_IWMMXT=y
-CONFIG_COMMON_CLKDEV=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-CONFIG_NO_HZ=y
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PREEMPT_NONE=y
-# CONFIG_PREEMPT_VOLUNTARY is not set
-# CONFIG_PREEMPT is not set
-CONFIG_HZ=100
-CONFIG_AEABI=y
-# CONFIG_OABI_COMPAT is not set
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_HAVE_MLOCK=y
-CONFIG_HAVE_MLOCKED_PAGE_BIT=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE="console=ttyS0,115200 rw"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-CONFIG_CPU_FREQ=y
-CONFIG_CPU_FREQ_TABLE=y
-# CONFIG_CPU_FREQ_DEBUG is not set
-CONFIG_CPU_FREQ_STAT=y
-# CONFIG_CPU_FREQ_STAT_DETAILS is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
-CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
-# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
-# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-CONFIG_CPU_IDLE=y
-CONFIG_CPU_IDLE_GOV_LADDER=y
-CONFIG_CPU_IDLE_GOV_MENU=y
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_APM_EMULATION=y
-# CONFIG_PM_RUNTIME is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-CONFIG_IP_PNP=y
-# CONFIG_IP_PNP_DHCP is not set
-# CONFIG_IP_PNP_BOOTP is not set
-# CONFIG_IP_PNP_RARP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_IP_MROUTE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-CONFIG_INET_TUNNEL=y
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-CONFIG_IPV6=y
-# CONFIG_IPV6_PRIVACY is not set
-# CONFIG_IPV6_ROUTER_PREF is not set
-# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-# CONFIG_INET6_AH is not set
-# CONFIG_INET6_ESP is not set
-# CONFIG_INET6_IPCOMP is not set
-# CONFIG_IPV6_MIP6 is not set
-# CONFIG_INET6_XFRM_TUNNEL is not set
-# CONFIG_INET6_TUNNEL is not set
-CONFIG_INET6_XFRM_MODE_TRANSPORT=y
-CONFIG_INET6_XFRM_MODE_TUNNEL=y
-CONFIG_INET6_XFRM_MODE_BEET=y
-# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-CONFIG_IPV6_SIT=y
-CONFIG_IPV6_NDISC_NODETYPE=y
-# CONFIG_IPV6_TUNNEL is not set
-# CONFIG_IPV6_MULTIPLE_TABLES is not set
-# CONFIG_IPV6_MROUTE is not set
-# CONFIG_NETWORK_SECMARK is not set
-# CONFIG_NETFILTER is not set
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_RDS is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_PHONET is not set
-# CONFIG_IEEE802154 is not set
-# CONFIG_NET_SCHED is not set
-# CONFIG_DCB is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-# CONFIG_IRDA is not set
-# CONFIG_BT is not set
-# CONFIG_AF_RXRPC is not set
-CONFIG_WIRELESS=y
-CONFIG_CFG80211=y
-# CONFIG_NL80211_TESTMODE is not set
-# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
-CONFIG_CFG80211_REG_DEBUG=y
-CONFIG_CFG80211_DEFAULT_PS=y
-CONFIG_CFG80211_DEFAULT_PS_VALUE=1
-CONFIG_WIRELESS_OLD_REGULATORY=y
-CONFIG_WIRELESS_EXT=y
-CONFIG_WIRELESS_EXT_SYSFS=y
-CONFIG_LIB80211=y
-# CONFIG_LIB80211_DEBUG is not set
-CONFIG_MAC80211=y
-CONFIG_MAC80211_RC_MINSTREL=y
-# CONFIG_MAC80211_RC_DEFAULT_PID is not set
-CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
-CONFIG_MAC80211_RC_DEFAULT="minstrel"
-# CONFIG_MAC80211_MESH is not set
-# CONFIG_MAC80211_LEDS is not set
-# CONFIG_MAC80211_DEBUG_MENU is not set
-# CONFIG_WIMAX is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_DEVTMPFS is not set
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_TESTS is not set
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-# CONFIG_MTD_CMDLINE_PARTS is not set
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-CONFIG_NFTL=y
-CONFIG_NFTL_RW=y
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-# CONFIG_MTD_ROM is not set
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-# CONFIG_MTD_COMPLEX_MAPPINGS is not set
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
-# CONFIG_MTD_SST25L is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-CONFIG_MTD_BLOCK2MTD=y
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND=y
-# CONFIG_MTD_NAND_VERIFY_WRITE is not set
-# CONFIG_MTD_NAND_ECC_SMC is not set
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_H1900 is not set
-# CONFIG_MTD_NAND_GPIO is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_SHARPSL is not set
-CONFIG_MTD_NAND_PXA3xx=y
-# CONFIG_MTD_NAND_PXA3xx_BUILTIN is not set
-# CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_ALAUDA is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# LPDDR flash memory drivers
-#
-# CONFIG_MTD_LPDDR is not set
-
-#
-# UBI - Unsorted block images
-#
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_WL_THRESHOLD=4096
-CONFIG_MTD_UBI_BEB_RESERVE=1
-# CONFIG_MTD_UBI_GLUEBI is not set
-
-#
-# UBI debugging options
-#
-# CONFIG_MTD_UBI_DEBUG is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-# CONFIG_MG_DISK is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_ICS932S401 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-CONFIG_ISL29003=y
-CONFIG_TI_DAC7512=y
-# CONFIG_C2PORT is not set
-
-#
-# EEPROM support
-#
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_AT25 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_EEPROM_MAX6875 is not set
-# CONFIG_EEPROM_93CX6 is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-CONFIG_CHR_DEV_SG=y
-# CONFIG_CHR_DEV_SCH is not set
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_LIBFC is not set
-# CONFIG_LIBFCOE is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-CONFIG_PHYLIB=y
-
-#
-# MII PHY device drivers
-#
-# CONFIG_MARVELL_PHY is not set
-# CONFIG_DAVICOM_PHY is not set
-# CONFIG_QSEMI_PHY is not set
-# CONFIG_LXT_PHY is not set
-# CONFIG_CICADA_PHY is not set
-# CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
-# CONFIG_BROADCOM_PHY is not set
-# CONFIG_ICPLUS_PHY is not set
-# CONFIG_REALTEK_PHY is not set
-# CONFIG_NATIONAL_PHY is not set
-# CONFIG_STE10XP is not set
-# CONFIG_LSI_ET1011C_PHY is not set
-# CONFIG_FIXED_PHY is not set
-# CONFIG_MDIO_BITBANG is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-# CONFIG_AX88796 is not set
-# CONFIG_SMC91X is not set
-# CONFIG_DM9000 is not set
-# CONFIG_ENC28J60 is not set
-# CONFIG_ETHOC is not set
-# CONFIG_SMC911X is not set
-CONFIG_SMSC911X=y
-# CONFIG_DNET is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-# CONFIG_KS8842 is not set
-# CONFIG_KS8851 is not set
-# CONFIG_KS8851_MLL is not set
-# CONFIG_NETDEV_1000 is not set
-# CONFIG_NETDEV_10000 is not set
-CONFIG_WLAN=y
-# CONFIG_WLAN_PRE80211 is not set
-CONFIG_WLAN_80211=y
-CONFIG_LIBERTAS=y
-# CONFIG_LIBERTAS_USB is not set
-CONFIG_LIBERTAS_SDIO=m
-# CONFIG_LIBERTAS_SPI is not set
-# CONFIG_LIBERTAS_DEBUG is not set
-# CONFIG_LIBERTAS_THINFIRM is not set
-# CONFIG_AT76C50X_USB is not set
-# CONFIG_USB_ZD1201 is not set
-# CONFIG_USB_NET_RNDIS_WLAN is not set
-# CONFIG_RTL8187 is not set
-# CONFIG_MAC80211_HWSIM is not set
-# CONFIG_P54_COMMON is not set
-# CONFIG_ATH_COMMON is not set
-# CONFIG_HOSTAP is not set
-# CONFIG_B43 is not set
-# CONFIG_B43LEGACY is not set
-# CONFIG_ZD1211RW is not set
-# CONFIG_RT2X00 is not set
-# CONFIG_WL12XX is not set
-# CONFIG_IWM is not set
-
-#
-# Enable WiMAX (Networking options) to see the WiMAX drivers
-#
-
-#
-# USB Network Adapters
-#
-# CONFIG_USB_CATC is not set
-# CONFIG_USB_KAWETH is not set
-# CONFIG_USB_PEGASUS is not set
-# CONFIG_USB_RTL8150 is not set
-CONFIG_USB_USBNET=y
-# CONFIG_USB_NET_AX8817X is not set
-CONFIG_USB_NET_CDCETHER=y
-# CONFIG_USB_NET_CDC_EEM is not set
-# CONFIG_USB_NET_DM9601 is not set
-# CONFIG_USB_NET_SMSC95XX is not set
-# CONFIG_USB_NET_GL620A is not set
-# CONFIG_USB_NET_NET1080 is not set
-# CONFIG_USB_NET_PLUSB is not set
-CONFIG_USB_NET_MCS7830=y
-# CONFIG_USB_NET_RNDIS_HOST is not set
-# CONFIG_USB_NET_CDC_SUBSET is not set
-# CONFIG_USB_NET_ZAURUS is not set
-# CONFIG_USB_NET_INT51X1 is not set
-# CONFIG_WAN is not set
-# CONFIG_PPP is not set
-# CONFIG_SLIP is not set
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-CONFIG_INPUT_POLLDEV=y
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ADP5588 is not set
-CONFIG_KEYBOARD_ATKBD=y
-# CONFIG_QT2160 is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-# CONFIG_KEYBOARD_MATRIX is not set
-# CONFIG_KEYBOARD_LM8323 is not set
-# CONFIG_KEYBOARD_MAX7359 is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_OPENCORES is not set
-# CONFIG_KEYBOARD_PXA27x is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_ADS7846 is not set
-# CONFIG_TOUCHSCREEN_AD7877 is not set
-# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
-# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-CONFIG_TOUCHSCREEN_EETI=m
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MCS5000 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_TSC2007 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-# CONFIG_INPUT_UINPUT is not set
-CONFIG_INPUT_GPIO_ROTARY_ENCODER=y
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-# CONFIG_SERIAL_8250 is not set
-
-#
-# Non-8250 serial port support
-#
-# CONFIG_SERIAL_MAX3100 is not set
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=y
-# CONFIG_HW_RANDOM_TIMERIOMEM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-CONFIG_I2C_COMPAT=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_DESIGNWARE is not set
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-CONFIG_SPI=y
-CONFIG_SPI_DEBUG=y
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-CONFIG_SPI_BITBANG=y
-CONFIG_SPI_GPIO=y
-# CONFIG_SPI_PXA2XX is not set
-
-#
-# SPI Protocol Masters
-#
-CONFIG_SPI_SPIDEV=y
-# CONFIG_SPI_TLE62X0 is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-CONFIG_DEBUG_GPIO=y
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO expanders:
-#
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_GPIO_MC33880 is not set
-
-#
-# AC97 GPIO expanders:
-#
-CONFIG_W1=m
-
-#
-# 1-wire Bus Masters
-#
-# CONFIG_W1_MASTER_DS2490 is not set
-# CONFIG_W1_MASTER_DS2482 is not set
-# CONFIG_W1_MASTER_DS1WM is not set
-CONFIG_W1_MASTER_GPIO=m
-
-#
-# 1-wire Slaves
-#
-# CONFIG_W1_SLAVE_THERM is not set
-# CONFIG_W1_SLAVE_SMEM is not set
-# CONFIG_W1_SLAVE_DS2431 is not set
-# CONFIG_W1_SLAVE_DS2433 is not set
-CONFIG_W1_SLAVE_DS2760=m
-# CONFIG_W1_SLAVE_BQ27000 is not set
-CONFIG_POWER_SUPPLY=y
-# CONFIG_POWER_SUPPLY_DEBUG is not set
-CONFIG_PDA_POWER=y
-# CONFIG_APM_POWER is not set
-CONFIG_BATTERY_DS2760=m
-# CONFIG_BATTERY_DS2782 is not set
-# CONFIG_BATTERY_BQ27x00 is not set
-# CONFIG_BATTERY_MAX17040 is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-
-#
-# Native drivers
-#
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADCXX is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7462 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7473 is not set
-# CONFIG_SENSORS_ADT7475 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_G760A is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM70 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-# CONFIG_SENSORS_LTC4215 is not set
-# CONFIG_SENSORS_LTC4245 is not set
-# CONFIG_SENSORS_LM95241 is not set
-# CONFIG_SENSORS_MAX1111 is not set
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_SENSORS_SHT15 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_TMP401 is not set
-# CONFIG_SENSORS_TMP421 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-CONFIG_SENSORS_LIS3_SPI=y
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_TWL4030_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_PMIC_DA903X is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM831X is not set
-# CONFIG_MFD_WM8350_I2C is not set
-# CONFIG_MFD_PCF50633 is not set
-# CONFIG_MFD_MC13783 is not set
-# CONFIG_AB3100_CORE is not set
-# CONFIG_EZX_PCAP is not set
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_DEBUG=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_REGULATOR_MAX1586 is not set
-CONFIG_REGULATOR_MAX8660=y
-# CONFIG_REGULATOR_LP3971 is not set
-# CONFIG_REGULATOR_TPS65023 is not set
-# CONFIG_REGULATOR_TPS6507X is not set
-# CONFIG_MEDIA_SUPPORT is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_OVERLAY is not set
-# CONFIG_FB_PXA_SMARTPANEL is not set
-# CONFIG_FB_PXA_PARAMETERS is not set
-CONFIG_PXA3XX_GCU=y
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_W100 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-# CONFIG_FB_MB862XX is not set
-# CONFIG_FB_BROADSHEET is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-# CONFIG_LCD_CLASS_DEVICE is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_GENERIC is not set
-CONFIG_BACKLIGHT_PWM=y
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-# CONFIG_FONTS is not set
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-# CONFIG_LOGO_LINUX_CLUT224 is not set
-CONFIG_LOGO_RAUMFELD_CLUT224=y
-CONFIG_SOUND=y
-# CONFIG_SOUND_OSS_CORE is not set
-CONFIG_SND=y
-CONFIG_SND_TIMER=y
-CONFIG_SND_PCM=y
-CONFIG_SND_JACK=y
-# CONFIG_SND_SEQUENCER is not set
-# CONFIG_SND_MIXER_OSS is not set
-# CONFIG_SND_PCM_OSS is not set
-# CONFIG_SND_DYNAMIC_MINORS is not set
-CONFIG_SND_SUPPORT_OLD_API=y
-CONFIG_SND_VERBOSE_PROCFS=y
-# CONFIG_SND_VERBOSE_PRINTK is not set
-# CONFIG_SND_DEBUG is not set
-# CONFIG_SND_RAWMIDI_SEQ is not set
-# CONFIG_SND_OPL3_LIB_SEQ is not set
-# CONFIG_SND_OPL4_LIB_SEQ is not set
-# CONFIG_SND_SBAWE_SEQ is not set
-# CONFIG_SND_EMU10K1_SEQ is not set
-# CONFIG_SND_DRIVERS is not set
-CONFIG_SND_ARM=y
-CONFIG_SND_PXA2XX_LIB=y
-# CONFIG_SND_PXA2XX_AC97 is not set
-CONFIG_SND_SPI=y
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_SND_PXA2XX_SOC=y
-CONFIG_SND_PXA_SOC_SSP=y
-CONFIG_SND_SOC_RAUMFELD=y
-CONFIG_SND_SOC_I2C_AND_SPI=y
-# CONFIG_SND_SOC_ALL_CODECS is not set
-CONFIG_SND_SOC_AK4104=y
-CONFIG_SND_SOC_CS4270=y
-# CONFIG_SOUND_PRIME is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=y
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# Special HID drivers
-#
-CONFIG_HID_A4TECH=y
-CONFIG_HID_APPLE=y
-CONFIG_HID_BELKIN=y
-CONFIG_HID_CHERRY=y
-CONFIG_HID_CHICONY=y
-CONFIG_HID_CYPRESS=y
-CONFIG_HID_DRAGONRISE=y
-# CONFIG_DRAGONRISE_FF is not set
-CONFIG_HID_EZKEY=y
-CONFIG_HID_KYE=y
-CONFIG_HID_GYRATION=y
-CONFIG_HID_TWINHAN=y
-CONFIG_HID_KENSINGTON=y
-CONFIG_HID_LOGITECH=y
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-CONFIG_HID_MICROSOFT=y
-CONFIG_HID_MONTEREY=y
-CONFIG_HID_NTRIG=y
-CONFIG_HID_PANTHERLORD=y
-# CONFIG_PANTHERLORD_FF is not set
-CONFIG_HID_PETALYNX=y
-CONFIG_HID_SAMSUNG=y
-CONFIG_HID_SONY=y
-CONFIG_HID_SUNPLUS=y
-CONFIG_HID_GREENASIA=y
-# CONFIG_GREENASIA_FF is not set
-CONFIG_HID_SMARTJOYPLUS=y
-# CONFIG_SMARTJOYPLUS_FF is not set
-CONFIG_HID_TOPSEED=y
-CONFIG_HID_THRUSTMASTER=y
-# CONFIG_THRUSTMASTER_FF is not set
-CONFIG_HID_ZEROPLUS=y
-# CONFIG_ZEROPLUS_FF is not set
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-
-#
-# Miscellaneous USB options
-#
-# CONFIG_USB_DEVICEFS is not set
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-CONFIG_USB_MON=y
-# CONFIG_USB_WUSB is not set
-# CONFIG_USB_WUSB_CBAF is not set
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_OXU210HP_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-# CONFIG_USB_ISP1362_HCD is not set
-CONFIG_USB_OHCI_HCD=y
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-# CONFIG_USB_SL811_HCD is not set
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_HWA_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-# CONFIG_USB_ACM is not set
-# CONFIG_USB_PRINTER is not set
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
-#
-
-#
-# also be needed; see USB_STORAGE Help for more info
-#
-CONFIG_USB_STORAGE=y
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_ISD200=y
-CONFIG_USB_STORAGE_USBAT=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-# CONFIG_USB_MDC800 is not set
-# CONFIG_USB_MICROTEK is not set
-
-#
-# USB port drivers
-#
-# CONFIG_USB_SERIAL is not set
-
-#
-# USB Miscellaneous drivers
-#
-# CONFIG_USB_EMI62 is not set
-# CONFIG_USB_EMI26 is not set
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-# CONFIG_USB_RIO500 is not set
-# CONFIG_USB_LEGOTOWER is not set
-# CONFIG_USB_LCD is not set
-# CONFIG_USB_BERRY_CHARGE is not set
-# CONFIG_USB_LED is not set
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-# CONFIG_USB_CYTHERM is not set
-# CONFIG_USB_IDMOUSE is not set
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-# CONFIG_USB_GADGET is not set
-
-#
-# OTG and related infrastructure
-#
-# CONFIG_USB_GPIO_VBUS is not set
-# CONFIG_NOP_USB_XCEIV is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_PXA=m
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_AT91 is not set
-# CONFIG_MMC_ATMELMCI is not set
-# CONFIG_MMC_SPI is not set
-# CONFIG_MEMSTICK is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-
-#
-# LED drivers
-#
-# CONFIG_LEDS_PCA9532 is not set
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_GPIO_PLATFORM=y
-# CONFIG_LEDS_LP3944 is not set
-# CONFIG_LEDS_PCA955X is not set
-# CONFIG_LEDS_DAC124S085 is not set
-# CONFIG_LEDS_PWM is not set
-# CONFIG_LEDS_BD2802 is not set
-CONFIG_LEDS_LT3593=y
-
-#
-# LED Triggers
-#
-CONFIG_LEDS_TRIGGERS=y
-# CONFIG_LEDS_TRIGGER_TIMER is not set
-# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-# CONFIG_LEDS_TRIGGER_GPIO is not set
-# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
-
-#
-# iptables trigger is under Netfilter config (LED target)
-#
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_HCTOSYS=y
-CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
-# CONFIG_RTC_DEBUG is not set
-
-#
-# RTC interfaces
-#
-CONFIG_RTC_INTF_SYSFS=y
-CONFIG_RTC_INTF_PROC=y
-CONFIG_RTC_INTF_DEV=y
-# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
-# CONFIG_RTC_DRV_TEST is not set
-
-#
-# I2C RTC drivers
-#
-# CONFIG_RTC_DRV_DS1307 is not set
-# CONFIG_RTC_DRV_DS1374 is not set
-# CONFIG_RTC_DRV_DS1672 is not set
-# CONFIG_RTC_DRV_MAX6900 is not set
-# CONFIG_RTC_DRV_RS5C372 is not set
-# CONFIG_RTC_DRV_ISL1208 is not set
-# CONFIG_RTC_DRV_X1205 is not set
-# CONFIG_RTC_DRV_PCF8563 is not set
-# CONFIG_RTC_DRV_PCF8583 is not set
-# CONFIG_RTC_DRV_M41T80 is not set
-# CONFIG_RTC_DRV_S35390A is not set
-# CONFIG_RTC_DRV_FM3130 is not set
-# CONFIG_RTC_DRV_RX8581 is not set
-# CONFIG_RTC_DRV_RX8025 is not set
-
-#
-# SPI RTC drivers
-#
-# CONFIG_RTC_DRV_M41T94 is not set
-# CONFIG_RTC_DRV_DS1305 is not set
-# CONFIG_RTC_DRV_DS1390 is not set
-# CONFIG_RTC_DRV_MAX6902 is not set
-# CONFIG_RTC_DRV_R9701 is not set
-# CONFIG_RTC_DRV_RS5C348 is not set
-# CONFIG_RTC_DRV_DS3234 is not set
-# CONFIG_RTC_DRV_PCF2123 is not set
-
-#
-# Platform RTC drivers
-#
-# CONFIG_RTC_DRV_CMOS is not set
-# CONFIG_RTC_DRV_DS1286 is not set
-# CONFIG_RTC_DRV_DS1511 is not set
-# CONFIG_RTC_DRV_DS1553 is not set
-# CONFIG_RTC_DRV_DS1742 is not set
-# CONFIG_RTC_DRV_STK17TA8 is not set
-# CONFIG_RTC_DRV_M48T86 is not set
-# CONFIG_RTC_DRV_M48T35 is not set
-# CONFIG_RTC_DRV_M48T59 is not set
-# CONFIG_RTC_DRV_BQ4802 is not set
-# CONFIG_RTC_DRV_V3020 is not set
-
-#
-# on-CPU RTC drivers
-#
-# CONFIG_RTC_DRV_SA1100 is not set
-CONFIG_RTC_DRV_PXA=y
-CONFIG_DMADEVICES=y
-
-#
-# DMA Devices
-#
-# CONFIG_AUXDISPLAY is not set
-CONFIG_UIO=y
-# CONFIG_UIO_PDRV is not set
-# CONFIG_UIO_PDRV_GENIRQ is not set
-# CONFIG_UIO_SMX is not set
-# CONFIG_UIO_SERCOS3 is not set
-
-#
-# TI VLYNQ
-#
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-CONFIG_EXT2_FS_XIP=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT3_FS_XATTR=y
-# CONFIG_EXT3_FS_POSIX_ACL is not set
-# CONFIG_EXT3_FS_SECURITY is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_FS_XIP=y
-CONFIG_JBD=y
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# Caches
-#
-CONFIG_FSCACHE=y
-CONFIG_FSCACHE_STATS=y
-# CONFIG_FSCACHE_HISTOGRAM is not set
-# CONFIG_FSCACHE_DEBUG is not set
-CONFIG_CACHEFILES=y
-# CONFIG_CACHEFILES_DEBUG is not set
-# CONFIG_CACHEFILES_HISTOGRAM is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_JFFS2_FS is not set
-CONFIG_UBIFS_FS=y
-# CONFIG_UBIFS_FS_XATTR is not set
-# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
-CONFIG_UBIFS_FS_LZO=y
-CONFIG_UBIFS_FS_ZLIB=y
-# CONFIG_UBIFS_FS_DEBUG is not set
-# CONFIG_CRAMFS is not set
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-# CONFIG_NFS_V4 is not set
-CONFIG_ROOT_NFS=y
-CONFIG_NFS_FSCACHE=y
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=y
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=y
-# CONFIG_RPCSEC_GSS_KRB5 is not set
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-# CONFIG_SMB_FS is not set
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-# CONFIG_PARTITION_ADVANCED is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_737=y
-CONFIG_NLS_CODEPAGE_775=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_CODEPAGE_852=y
-CONFIG_NLS_CODEPAGE_855=y
-CONFIG_NLS_CODEPAGE_857=y
-CONFIG_NLS_CODEPAGE_860=y
-CONFIG_NLS_CODEPAGE_861=y
-CONFIG_NLS_CODEPAGE_862=y
-CONFIG_NLS_CODEPAGE_863=y
-CONFIG_NLS_CODEPAGE_864=y
-CONFIG_NLS_CODEPAGE_865=y
-CONFIG_NLS_CODEPAGE_866=y
-CONFIG_NLS_CODEPAGE_869=y
-CONFIG_NLS_CODEPAGE_936=y
-CONFIG_NLS_CODEPAGE_950=y
-CONFIG_NLS_CODEPAGE_932=y
-CONFIG_NLS_CODEPAGE_949=y
-CONFIG_NLS_CODEPAGE_874=y
-CONFIG_NLS_ISO8859_8=y
-CONFIG_NLS_CODEPAGE_1250=y
-CONFIG_NLS_CODEPAGE_1251=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_NLS_ISO8859_3=y
-CONFIG_NLS_ISO8859_4=y
-CONFIG_NLS_ISO8859_5=y
-CONFIG_NLS_ISO8859_6=y
-CONFIG_NLS_ISO8859_7=y
-CONFIG_NLS_ISO8859_9=y
-CONFIG_NLS_ISO8859_13=y
-CONFIG_NLS_ISO8859_14=y
-CONFIG_NLS_ISO8859_15=y
-CONFIG_NLS_KOI8_R=y
-CONFIG_NLS_KOI8_U=y
-CONFIG_NLS_UTF8=y
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-CONFIG_PRINTK_TIME=y
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-# CONFIG_MAGIC_SYSRQ is not set
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_ENABLE_DEFAULT_TRACERS is not set
-# CONFIG_BOOT_TRACER is not set
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARM_UNWIND=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_ALGAPI2=y
-CONFIG_CRYPTO_AEAD2=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_BLKCIPHER2=y
-CONFIG_CRYPTO_HASH2=y
-CONFIG_CRYPTO_RNG2=y
-CONFIG_CRYPTO_PCOMP=y
-CONFIG_CRYPTO_MANAGER=y
-CONFIG_CRYPTO_MANAGER2=y
-# CONFIG_CRYPTO_GF128MUL is not set
-# CONFIG_CRYPTO_NULL is not set
-CONFIG_CRYPTO_WORKQUEUE=y
-# CONFIG_CRYPTO_CRYPTD is not set
-# CONFIG_CRYPTO_AUTHENC is not set
-# CONFIG_CRYPTO_TEST is not set
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-# CONFIG_CRYPTO_CBC is not set
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=y
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-# CONFIG_CRYPTO_HMAC is not set
-# CONFIG_CRYPTO_XCBC is not set
-# CONFIG_CRYPTO_VMAC is not set
-
-#
-# Digest
-#
-# CONFIG_CRYPTO_CRC32C is not set
-# CONFIG_CRYPTO_GHASH is not set
-# CONFIG_CRYPTO_MD4 is not set
-# CONFIG_CRYPTO_MD5 is not set
-# CONFIG_CRYPTO_MICHAEL_MIC is not set
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-# CONFIG_CRYPTO_SHA1 is not set
-# CONFIG_CRYPTO_SHA256 is not set
-# CONFIG_CRYPTO_SHA512 is not set
-# CONFIG_CRYPTO_TGR192 is not set
-# CONFIG_CRYPTO_WP512 is not set
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=y
-# CONFIG_CRYPTO_ANUBIS is not set
-CONFIG_CRYPTO_ARC4=y
-# CONFIG_CRYPTO_BLOWFISH is not set
-# CONFIG_CRYPTO_CAMELLIA is not set
-# CONFIG_CRYPTO_CAST5 is not set
-# CONFIG_CRYPTO_CAST6 is not set
-# CONFIG_CRYPTO_DES is not set
-# CONFIG_CRYPTO_FCRYPT is not set
-# CONFIG_CRYPTO_KHAZAD is not set
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-# CONFIG_CRYPTO_SERPENT is not set
-# CONFIG_CRYPTO_TEA is not set
-# CONFIG_CRYPTO_TWOFISH is not set
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=y
-# CONFIG_CRYPTO_ZLIB is not set
-CONFIG_CRYPTO_LZO=y
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_CRC_CCITT is not set
-CONFIG_CRC16=y
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_LZO_COMPRESS=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
-CONFIG_NLATTR=y
-- 
1.7.0.4



From eric.y.miao at gmail.com  Sat Jun  5 03:55:38 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat,  5 Jun 2010 15:55:38 +0800
Subject: [PATCH 4/4] [ARM] pxa: merge {corgi,
	spitz}_defconfig into zaurus_defconfig
In-Reply-To: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1275724538-5075-5-git-send-email-eric.y.miao@gmail.com>

Signed-off-by: Eric Miao <eric.y.miao at gmail.com>
---
 arch/arm/configs/corgi_defconfig  | 1893 -------------------------------------
 arch/arm/configs/spitz_defconfig  | 1820 -----------------------------------
 arch/arm/configs/zaurus_defconfig | 1726 +++++++++++++++++++++++++++++++++
 3 files changed, 1726 insertions(+), 3713 deletions(-)
 delete mode 100644 arch/arm/configs/corgi_defconfig
 delete mode 100644 arch/arm/configs/spitz_defconfig
 create mode 100644 arch/arm/configs/zaurus_defconfig

diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
deleted file mode 100644
index 5e4069f..0000000
--- a/arch/arm/configs/corgi_defconfig
+++ /dev/null
@@ -1,1893 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27
-# Mon Oct 20 10:12:23 2008
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
-# CONFIG_GROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-CONFIG_PROFILING=y
-# CONFIG_MARKERS is not set
-CONFIG_OPROFILE=m
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM7X00A is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_ARCH_PXA_IDP is not set
-CONFIG_PXA_SHARPSL=y
-CONFIG_MACH_POODLE=y
-CONFIG_MACH_CORGI=y
-CONFIG_MACH_SHEPHERD=y
-CONFIG_MACH_HUSKY=y
-# CONFIG_MACH_AKITA is not set
-# CONFIG_MACH_SPITZ is not set
-# CONFIG_MACH_BORZOI is not set
-# CONFIG_MACH_TOSA is not set
-# CONFIG_ARCH_VIPER is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_PXA_EZX is not set
-CONFIG_PXA25x=y
-CONFIG_PXA_SHARP_C7xx=y
-CONFIG_PXA_SSP=y
-# CONFIG_PXA_PWM is not set
-# CONFIG_TOSA_BT is not set
-CONFIG_PXA_HAVE_BOARD_IRQS=y
-
-#
-# Boot options
-#
-
-#
-# Power management
-#
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-# CONFIG_IWMMXT is not set
-CONFIG_XSCALE_PMU=y
-CONFIG_SHARP_LOCOMO=y
-CONFIG_SHARP_PARAM=y
-CONFIG_SHARPSL_PM=y
-CONFIG_SHARP_SCOOP=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_PCCARD=y
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=y
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_IOCTL=y
-
-#
-# PC-card bridges
-#
-CONFIG_PCMCIA_PXA2XX=y
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-# CONFIG_AEABI is not set
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200n8 console=tty1 noinitrd root=/dev/mtdblock2 rootfstype=jffs2   debug"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_FREQ is not set
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_HAVE_AOUT=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-# CONFIG_ARTHUR is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_APM_EMULATION=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-CONFIG_XFRM_USER=m
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-CONFIG_XFRM_IPCOMP=m
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-CONFIG_IPV6=m
-# CONFIG_IPV6_PRIVACY is not set
-# CONFIG_IPV6_ROUTER_PREF is not set
-# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-# CONFIG_IPV6_MIP6 is not set
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-CONFIG_INET6_XFRM_MODE_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_BEET=m
-# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=m
-# CONFIG_IPV6_MULTIPLE_TABLES is not set
-# CONFIG_IPV6_MROUTE is not set
-# CONFIG_NETWORK_SECMARK is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-CONFIG_NETFILTER_ADVANCED=y
-
-#
-# Core Netfilter Configuration
-#
-# CONFIG_NETFILTER_NETLINK_QUEUE is not set
-# CONFIG_NETFILTER_NETLINK_LOG is not set
-# CONFIG_NF_CONNTRACK is not set
-CONFIG_NETFILTER_XTABLES=m
-# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
-# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
-# CONFIG_NETFILTER_XT_TARGET_MARK is not set
-# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
-# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
-# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
-# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
-# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
-# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
-# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
-# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
-# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
-# CONFIG_NETFILTER_XT_MATCH_ESP is not set
-# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
-# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
-# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
-# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
-# CONFIG_NETFILTER_XT_MATCH_MAC is not set
-# CONFIG_NETFILTER_XT_MATCH_MARK is not set
-# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
-# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
-# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
-# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
-# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
-# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
-# CONFIG_NETFILTER_XT_MATCH_REALM is not set
-# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
-# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
-# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
-# CONFIG_NETFILTER_XT_MATCH_STRING is not set
-# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
-# CONFIG_NETFILTER_XT_MATCH_TIME is not set
-# CONFIG_NETFILTER_XT_MATCH_U32 is not set
-# CONFIG_IP_VS is not set
-
-#
-# IP: Netfilter Configuration
-#
-# CONFIG_NF_DEFRAG_IPV4 is not set
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-# CONFIG_IP_NF_MATCH_AH is not set
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-# CONFIG_IP_NF_TARGET_REJECT is not set
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_MANGLE=m
-# CONFIG_IP_NF_TARGET_ECN is not set
-# CONFIG_IP_NF_TARGET_TTL is not set
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_IP6_NF_IPTABLES=m
-# CONFIG_IP6_NF_MATCH_AH is not set
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-# CONFIG_IP6_NF_MATCH_MH is not set
-CONFIG_IP6_NF_MATCH_RT=m
-# CONFIG_IP6_NF_TARGET_LOG is not set
-CONFIG_IP6_NF_FILTER=m
-# CONFIG_IP6_NF_TARGET_REJECT is not set
-CONFIG_IP6_NF_MANGLE=m
-# CONFIG_IP6_NF_TARGET_HL is not set
-CONFIG_IP6_NF_RAW=m
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-CONFIG_IRDA=m
-
-#
-# IrDA protocols
-#
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-# CONFIG_IRDA_ULTRA is not set
-
-#
-# IrDA options
-#
-# CONFIG_IRDA_CACHE_LAST_LSAP is not set
-# CONFIG_IRDA_FAST_RR is not set
-# CONFIG_IRDA_DEBUG is not set
-
-#
-# Infrared-port device drivers
-#
-
-#
-# SIR device drivers
-#
-# CONFIG_IRTTY_SIR is not set
-
-#
-# Dongle support
-#
-# CONFIG_KINGSUN_DONGLE is not set
-# CONFIG_KSDAZZLE_DONGLE is not set
-# CONFIG_KS959_DONGLE is not set
-
-#
-# FIR device drivers
-#
-# CONFIG_USB_IRDA is not set
-# CONFIG_SIGMATEL_FIR is not set
-CONFIG_PXA_FICP=m
-# CONFIG_MCS_FIR is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIUSB=m
-# CONFIG_BT_HCIUSB_SCO is not set
-# CONFIG_BT_HCIBTUSB is not set
-# CONFIG_BT_HCIBTSDIO is not set
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-# CONFIG_BT_HCIUART_LL is not set
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIDTL1=m
-CONFIG_BT_HCIBT3C=m
-CONFIG_BT_HCIBLUECARD=m
-CONFIG_BT_HCIBTUART=m
-CONFIG_BT_HCIVHCI=m
-# CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_OLD_REGULATORY is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-# CONFIG_IEEE80211_CRYPT_CCMP is not set
-# CONFIG_IEEE80211_CRYPT_TKIP is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-CONFIG_MTD_ROM=y
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_SHARP_SL=y
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-# CONFIG_MTD_NAND_ECC_SMC is not set
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_H1900 is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_SHARPSL=y
-# CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_ALAUDA is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-CONFIG_HAVE_IDE=y
-CONFIG_IDE=y
-
-#
-# Please see Documentation/ide/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-CONFIG_BLK_DEV_IDECS=y
-# CONFIG_BLK_DEV_IDECD is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_BLK_DEV_PLATFORM is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=m
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-# CONFIG_BLK_DEV_SR_VENDOR is not set
-CONFIG_CHR_DEV_SG=m
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-# CONFIG_AX88796 is not set
-# CONFIG_SMC91X is not set
-# CONFIG_DM9000 is not set
-# CONFIG_ENC28J60 is not set
-# CONFIG_SMC911X is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-CONFIG_NETDEV_1000=y
-CONFIG_NETDEV_10000=y
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
-
-#
-# USB Network Adapters
-#
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_CDCETHER=m
-# CONFIG_USB_NET_DM9601 is not set
-# CONFIG_USB_NET_SMSC95XX is not set
-# CONFIG_USB_NET_GL620A is not set
-CONFIG_USB_NET_NET1080=m
-# CONFIG_USB_NET_PLUSB is not set
-# CONFIG_USB_NET_MCS7830 is not set
-# CONFIG_USB_NET_RNDIS_HOST is not set
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_NET_PCMCIA=y
-# CONFIG_PCMCIA_3C589 is not set
-# CONFIG_PCMCIA_3C574 is not set
-# CONFIG_PCMCIA_FMVJ18X is not set
-CONFIG_PCMCIA_PCNET=m
-# CONFIG_PCMCIA_NMCLAN is not set
-# CONFIG_PCMCIA_SMC91C92 is not set
-# CONFIG_PCMCIA_XIRC2PS is not set
-# CONFIG_PCMCIA_AXNET is not set
-# CONFIG_WAN is not set
-CONFIG_PPP=m
-# CONFIG_PPP_MULTILINK is not set
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-# CONFIG_PPP_DEFLATE is not set
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_PPP_MPPE is not set
-# CONFIG_PPPOE is not set
-# CONFIG_PPPOL2TP is not set
-# CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-# CONFIG_INPUT_APMPOWER is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_LOCOMO is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_CORGI=y
-CONFIG_KEYBOARD_SPITZ=y
-CONFIG_KEYBOARD_TOSA=y
-# CONFIG_KEYBOARD_TOSA_USE_EXT_KEYCODES is not set
-# CONFIG_KEYBOARD_GPIO is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_TOUCHSCREEN_CORGI is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-CONFIG_INPUT_UINPUT=m
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=m
-CONFIG_SERIAL_8250_CS=m
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SERIAL_8250_EXTENDED is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=m
-# CONFIG_NVRAM is not set
-# CONFIG_R3964 is not set
-
-#
-# PCMCIA character devices
-#
-# CONFIG_SYNCLINK_CS is not set
-# CONFIG_CARDMAN_4000 is not set
-# CONFIG_CARDMAN_4040 is not set
-# CONFIG_IPWIRELESS is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_CHARDEV is not set
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_BITBANG is not set
-CONFIG_SPI_PXA2XX=y
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_EEPROM_AT25 is not set
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_TLE62X0 is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADCXX is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7473 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM70 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-CONFIG_SENSORS_MAX1111=y
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-# CONFIG_WATCHDOG is not set
-
-#
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_UCB1400_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM8350_I2C is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-CONFIG_VIDEO_DEV=m
-CONFIG_VIDEO_V4L2_COMMON=m
-CONFIG_VIDEO_ALLOW_V4L1=y
-CONFIG_VIDEO_V4L1_COMPAT=y
-# CONFIG_DVB_CORE is not set
-CONFIG_VIDEO_MEDIA=m
-
-#
-# Multimedia drivers
-#
-# CONFIG_MEDIA_ATTACH is not set
-CONFIG_MEDIA_TUNER=m
-# CONFIG_MEDIA_TUNER_CUSTOMIZE is not set
-CONFIG_MEDIA_TUNER_SIMPLE=m
-CONFIG_MEDIA_TUNER_TDA8290=m
-CONFIG_MEDIA_TUNER_TDA9887=m
-CONFIG_MEDIA_TUNER_TEA5761=m
-CONFIG_MEDIA_TUNER_TEA5767=m
-CONFIG_MEDIA_TUNER_MT20XX=m
-CONFIG_MEDIA_TUNER_XC2028=m
-CONFIG_MEDIA_TUNER_XC5000=m
-CONFIG_VIDEO_V4L2=m
-CONFIG_VIDEO_V4L1=m
-CONFIG_VIDEO_CAPTURE_DRIVERS=y
-# CONFIG_VIDEO_ADV_DEBUG is not set
-# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
-CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
-# CONFIG_VIDEO_VIVI is not set
-# CONFIG_VIDEO_CPIA is not set
-# CONFIG_VIDEO_CPIA2 is not set
-# CONFIG_VIDEO_SAA5246A is not set
-# CONFIG_VIDEO_SAA5249 is not set
-# CONFIG_SOC_CAMERA is not set
-CONFIG_V4L_USB_DRIVERS=y
-# CONFIG_USB_VIDEO_CLASS is not set
-CONFIG_USB_GSPCA=m
-# CONFIG_USB_M5602 is not set
-# CONFIG_USB_GSPCA_CONEX is not set
-# CONFIG_USB_GSPCA_ETOMS is not set
-# CONFIG_USB_GSPCA_FINEPIX is not set
-# CONFIG_USB_GSPCA_MARS is not set
-# CONFIG_USB_GSPCA_OV519 is not set
-# CONFIG_USB_GSPCA_PAC207 is not set
-# CONFIG_USB_GSPCA_PAC7311 is not set
-# CONFIG_USB_GSPCA_SONIXB is not set
-# CONFIG_USB_GSPCA_SONIXJ is not set
-# CONFIG_USB_GSPCA_SPCA500 is not set
-# CONFIG_USB_GSPCA_SPCA501 is not set
-# CONFIG_USB_GSPCA_SPCA505 is not set
-# CONFIG_USB_GSPCA_SPCA506 is not set
-# CONFIG_USB_GSPCA_SPCA508 is not set
-# CONFIG_USB_GSPCA_SPCA561 is not set
-# CONFIG_USB_GSPCA_STK014 is not set
-# CONFIG_USB_GSPCA_SUNPLUS is not set
-# CONFIG_USB_GSPCA_T613 is not set
-# CONFIG_USB_GSPCA_TV8532 is not set
-# CONFIG_USB_GSPCA_VC032X is not set
-# CONFIG_USB_GSPCA_ZC3XX is not set
-# CONFIG_VIDEO_PVRUSB2 is not set
-# CONFIG_VIDEO_EM28XX is not set
-# CONFIG_VIDEO_USBVISION is not set
-CONFIG_VIDEO_USBVIDEO=m
-CONFIG_USB_VICAM=m
-CONFIG_USB_IBMCAM=m
-CONFIG_USB_KONICAWC=m
-# CONFIG_USB_QUICKCAM_MESSENGER is not set
-# CONFIG_USB_ET61X251 is not set
-# CONFIG_VIDEO_OVCAMCHIP is not set
-CONFIG_USB_OV511=m
-CONFIG_USB_SE401=m
-CONFIG_USB_SN9C102=m
-CONFIG_USB_STV680=m
-# CONFIG_USB_ZC0301 is not set
-# CONFIG_USB_PWC is not set
-# CONFIG_USB_ZR364XX is not set
-# CONFIG_USB_STKWEBCAM is not set
-# CONFIG_USB_S2255 is not set
-CONFIG_RADIO_ADAPTERS=y
-CONFIG_USB_DSBR=m
-# CONFIG_USB_SI470X is not set
-# CONFIG_USB_MR800 is not set
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-# CONFIG_FB_PXA is not set
-# CONFIG_FB_MBX is not set
-CONFIG_FB_W100=y
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_CORGI=y
-# CONFIG_LCD_LTV350QV is not set
-# CONFIG_LCD_ILI9320 is not set
-# CONFIG_LCD_TDO24M is not set
-# CONFIG_LCD_VGG2432A4 is not set
-# CONFIG_LCD_PLATFORM is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_CORGI is not set
-CONFIG_BACKLIGHT_LOCOMO=y
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_LOGO is not set
-CONFIG_SOUND=y
-CONFIG_SOUND_OSS_CORE=y
-# CONFIG_SND is not set
-CONFIG_SOUND_PRIME=y
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=m
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-
-#
-# Special HID drivers
-#
-CONFIG_HID_COMPAT=y
-CONFIG_HID_A4TECH=m
-CONFIG_HID_APPLE=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BRIGHT=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DELL=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_LOGITECH=m
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_PANTHERLORD=m
-# CONFIG_PANTHERLORD_FF is not set
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SONY=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_THRUSTMASTER_FF=m
-CONFIG_ZEROPLUS_FF=m
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-# CONFIG_USB_ARCH_HAS_OHCI is not set
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=m
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-CONFIG_USB_MON=y
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-CONFIG_USB_SL811_HCD=m
-CONFIG_USB_SL811_CS=m
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=m
-CONFIG_USB_EZUSB=y
-CONFIG_USB_SERIAL_GENERIC=y
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-CONFIG_USB_SERIAL_BELKIN=m
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-# CONFIG_USB_SERIAL_CP2101 is not set
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-# CONFIG_USB_SERIAL_FUNSOFT is not set
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-# CONFIG_USB_SERIAL_IUU is not set
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MOTOROLA is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-CONFIG_USB_SERIAL_PL2303=m
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_HP4X is not set
-CONFIG_USB_SERIAL_SAFE=m
-# CONFIG_USB_SERIAL_SAFE_PADDED is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-# CONFIG_USB_SERIAL_OPTION is not set
-CONFIG_USB_SERIAL_OMNINET=m
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-CONFIG_USB_RIO500=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-# CONFIG_USB_BERRY_CHARGE is not set
-CONFIG_USB_LED=m
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-CONFIG_USB_CYTHERM=m
-# CONFIG_USB_PHIDGET is not set
-CONFIG_USB_IDMOUSE=m
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-CONFIG_USB_GADGET=y
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-CONFIG_USB_GADGET_PXA25X=y
-CONFIG_USB_PXA25X=y
-# CONFIG_USB_PXA25X_SMALL is not set
-# CONFIG_USB_GADGET_PXA27X is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_FSL_QE is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_GOKU is not set
-# CONFIG_USB_GADGET_DUMMY_HCD is not set
-# CONFIG_USB_GADGET_DUALSPEED is not set
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-# CONFIG_USB_FILE_STORAGE_TEST is not set
-CONFIG_USB_G_SERIAL=m
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_PXA=y
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_SPI is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
-# CONFIG_NEW_LEDS is not set
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-
-#
-# Voltage and Current regulators
-#
-# CONFIG_REGULATOR is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_UIO is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-# CONFIG_FS_POSIX_ACL is not set
-CONFIG_FILE_LOCKING=y
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-CONFIG_JFFS2_SUMMARY=y
-# CONFIG_JFFS2_FS_XATTR is not set
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-CONFIG_CRAMFS=m
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-CONFIG_NFS_V4=y
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-# CONFIG_SUNRPC_REGISTER_V4 is not set
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_SMB_NLS_REMOTE="cp437"
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=y
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-CONFIG_HAVE_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-# CONFIG_FTRACE is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_MANAGER=y
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_NULL=m
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=m
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_HMAC=y
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-# CONFIG_CRYPTO_TGR192 is not set
-CONFIG_CRYPTO_WP512=m
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLOWFISH=m
-# CONFIG_CRYPTO_CAMELLIA is not set
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=m
-# CONFIG_CRYPTO_FCRYPT is not set
-CONFIG_CRYPTO_KHAZAD=m
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=m
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=y
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
deleted file mode 100644
index 7d89489..0000000
--- a/arch/arm/configs/spitz_defconfig
+++ /dev/null
@@ -1,1820 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27
-# Mon Oct 20 10:25:37 2008
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_GENERIC_CLOCKEVENTS=y
-CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_MTD_XIP=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_SWAP=y
-CONFIG_SYSVIPC=y
-CONFIG_SYSVIPC_SYSCTL=y
-# CONFIG_POSIX_MQUEUE is not set
-CONFIG_BSD_PROCESS_ACCT=y
-# CONFIG_BSD_PROCESS_ACCT_V3 is not set
-# CONFIG_TASKSTATS is not set
-# CONFIG_AUDIT is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
-# CONFIG_GROUP_SCHED is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-# CONFIG_NAMESPACES is not set
-# CONFIG_BLK_DEV_INITRD is not set
-# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
-CONFIG_SYSCTL=y
-CONFIG_EMBEDDED=y
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-# CONFIG_KALLSYMS_ALL is not set
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-CONFIG_PROFILING=y
-# CONFIG_MARKERS is not set
-CONFIG_OPROFILE=m
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
-CONFIG_BLOCK=y
-# CONFIG_LBD is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_AS=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-CONFIG_DEFAULT_AS=y
-# CONFIG_DEFAULT_DEADLINE is not set
-# CONFIG_DEFAULT_CFQ is not set
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="anticipatory"
-CONFIG_CLASSIC_RCU=y
-
-#
-# System Type
-#
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_PNX4008 is not set
-CONFIG_ARCH_PXA=y
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM7X00A is not set
-
-#
-# Intel PXA2xx/PXA3xx Implementations
-#
-# CONFIG_ARCH_GUMSTIX is not set
-# CONFIG_ARCH_LUBBOCK is not set
-# CONFIG_MACH_LOGICPD_PXA270 is not set
-# CONFIG_MACH_MAINSTONE is not set
-# CONFIG_MACH_MP900C is not set
-# CONFIG_ARCH_PXA_IDP is not set
-CONFIG_PXA_SHARPSL=y
-# CONFIG_MACH_POODLE is not set
-# CONFIG_MACH_CORGI is not set
-# CONFIG_MACH_SHEPHERD is not set
-# CONFIG_MACH_HUSKY is not set
-CONFIG_MACH_AKITA=y
-CONFIG_MACH_SPITZ=y
-CONFIG_MACH_BORZOI=y
-# CONFIG_MACH_TOSA is not set
-# CONFIG_ARCH_VIPER is not set
-# CONFIG_ARCH_PXA_ESERIES is not set
-# CONFIG_TRIZEPS_PXA is not set
-# CONFIG_MACH_EM_X270 is not set
-# CONFIG_MACH_COLIBRI is not set
-# CONFIG_MACH_ZYLONITE is not set
-# CONFIG_MACH_LITTLETON is not set
-# CONFIG_MACH_TAVOREVB is not set
-# CONFIG_MACH_SAAR is not set
-# CONFIG_MACH_ARMCORE is not set
-# CONFIG_MACH_CM_X300 is not set
-# CONFIG_MACH_MAGICIAN is not set
-# CONFIG_MACH_MIOA701 is not set
-# CONFIG_MACH_PCM027 is not set
-# CONFIG_ARCH_PXA_PALM is not set
-# CONFIG_PXA_EZX is not set
-CONFIG_PXA27x=y
-CONFIG_PXA_SHARP_Cxx00=y
-CONFIG_PXA_SSP=y
-# CONFIG_PXA_PWM is not set
-
-#
-# Boot options
-#
-
-#
-# Power management
-#
-
-#
-# Processor Type
-#
-CONFIG_CPU_XSCALE=y
-CONFIG_CPU_32v5=y
-CONFIG_CPU_ABRT_EV5T=y
-CONFIG_CPU_PABRT_NOIFAR=y
-CONFIG_CPU_CACHE_VIVT=y
-CONFIG_CPU_TLB_V4WBI=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
-CONFIG_IWMMXT=y
-CONFIG_XSCALE_PMU=y
-CONFIG_SHARP_PARAM=y
-CONFIG_SHARPSL_PM=y
-CONFIG_SHARP_SCOOP=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-CONFIG_PCCARD=y
-# CONFIG_PCMCIA_DEBUG is not set
-CONFIG_PCMCIA=y
-CONFIG_PCMCIA_LOAD_CIS=y
-CONFIG_PCMCIA_IOCTL=y
-
-#
-# PC-card bridges
-#
-CONFIG_PCMCIA_PXA2XX=y
-
-#
-# Kernel Features
-#
-CONFIG_TICK_ONESHOT=y
-# CONFIG_NO_HZ is not set
-# CONFIG_HIGH_RES_TIMERS is not set
-CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
-CONFIG_VMSPLIT_3G=y
-# CONFIG_VMSPLIT_2G is not set
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0xC0000000
-CONFIG_PREEMPT=y
-CONFIG_HZ=100
-# CONFIG_AEABI is not set
-CONFIG_ARCH_FLATMEM_HAS_HOLES=y
-# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-CONFIG_FLATMEM_MANUAL=y
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
-CONFIG_FLATMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
-CONFIG_PAGEFLAGS_EXTENDED=y
-CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-CONFIG_ALIGNMENT_TRAP=y
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,115200n8 console=tty1 noinitrd root=/dev/mtdblock2 rootfstype=jffs2   debug"
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_FREQ is not set
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-CONFIG_FPE_NWFPE=y
-# CONFIG_FPE_NWFPE_XP is not set
-# CONFIG_FPE_FASTFPE is not set
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-CONFIG_HAVE_AOUT=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-# CONFIG_ARTHUR is not set
-
-#
-# Power management options
-#
-CONFIG_PM=y
-# CONFIG_PM_DEBUG is not set
-CONFIG_PM_SLEEP=y
-CONFIG_SUSPEND=y
-CONFIG_SUSPEND_FREEZER=y
-CONFIG_APM_EMULATION=y
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-CONFIG_NET=y
-
-#
-# Networking options
-#
-CONFIG_PACKET=y
-CONFIG_PACKET_MMAP=y
-CONFIG_UNIX=y
-CONFIG_XFRM=y
-# CONFIG_XFRM_USER is not set
-# CONFIG_XFRM_SUB_POLICY is not set
-# CONFIG_XFRM_MIGRATE is not set
-# CONFIG_XFRM_STATISTICS is not set
-CONFIG_XFRM_IPCOMP=m
-# CONFIG_NET_KEY is not set
-CONFIG_INET=y
-# CONFIG_IP_MULTICAST is not set
-# CONFIG_IP_ADVANCED_ROUTER is not set
-CONFIG_IP_FIB_HASH=y
-# CONFIG_IP_PNP is not set
-# CONFIG_NET_IPIP is not set
-# CONFIG_NET_IPGRE is not set
-# CONFIG_ARPD is not set
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_AH is not set
-# CONFIG_INET_ESP is not set
-# CONFIG_INET_IPCOMP is not set
-# CONFIG_INET_XFRM_TUNNEL is not set
-CONFIG_INET_TUNNEL=m
-CONFIG_INET_XFRM_MODE_TRANSPORT=y
-CONFIG_INET_XFRM_MODE_TUNNEL=y
-CONFIG_INET_XFRM_MODE_BEET=y
-# CONFIG_INET_LRO is not set
-CONFIG_INET_DIAG=y
-CONFIG_INET_TCP_DIAG=y
-# CONFIG_TCP_CONG_ADVANCED is not set
-CONFIG_TCP_CONG_CUBIC=y
-CONFIG_DEFAULT_TCP_CONG="cubic"
-# CONFIG_TCP_MD5SIG is not set
-CONFIG_IPV6=m
-# CONFIG_IPV6_PRIVACY is not set
-# CONFIG_IPV6_ROUTER_PREF is not set
-# CONFIG_IPV6_OPTIMISTIC_DAD is not set
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-# CONFIG_IPV6_MIP6 is not set
-CONFIG_INET6_XFRM_TUNNEL=m
-CONFIG_INET6_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_TRANSPORT=m
-CONFIG_INET6_XFRM_MODE_TUNNEL=m
-CONFIG_INET6_XFRM_MODE_BEET=m
-# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
-CONFIG_IPV6_SIT=m
-CONFIG_IPV6_NDISC_NODETYPE=y
-CONFIG_IPV6_TUNNEL=m
-# CONFIG_IPV6_MULTIPLE_TABLES is not set
-# CONFIG_IPV6_MROUTE is not set
-# CONFIG_NETWORK_SECMARK is not set
-CONFIG_NETFILTER=y
-# CONFIG_NETFILTER_DEBUG is not set
-CONFIG_NETFILTER_ADVANCED=y
-
-#
-# Core Netfilter Configuration
-#
-# CONFIG_NETFILTER_NETLINK_QUEUE is not set
-# CONFIG_NETFILTER_NETLINK_LOG is not set
-# CONFIG_NF_CONNTRACK is not set
-CONFIG_NETFILTER_XTABLES=m
-# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
-# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
-# CONFIG_NETFILTER_XT_TARGET_MARK is not set
-# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
-# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
-# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
-# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
-# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
-# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
-# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
-# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
-# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
-# CONFIG_NETFILTER_XT_MATCH_ESP is not set
-# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
-# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
-# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
-# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
-# CONFIG_NETFILTER_XT_MATCH_MAC is not set
-# CONFIG_NETFILTER_XT_MATCH_MARK is not set
-# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
-# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
-# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
-# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
-# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
-# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
-# CONFIG_NETFILTER_XT_MATCH_REALM is not set
-# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
-# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
-# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
-# CONFIG_NETFILTER_XT_MATCH_STRING is not set
-# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
-# CONFIG_NETFILTER_XT_MATCH_TIME is not set
-# CONFIG_NETFILTER_XT_MATCH_U32 is not set
-# CONFIG_IP_VS is not set
-
-#
-# IP: Netfilter Configuration
-#
-# CONFIG_NF_DEFRAG_IPV4 is not set
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_MATCH_ADDRTYPE=m
-# CONFIG_IP_NF_MATCH_AH is not set
-CONFIG_IP_NF_MATCH_ECN=m
-CONFIG_IP_NF_MATCH_TTL=m
-CONFIG_IP_NF_FILTER=m
-# CONFIG_IP_NF_TARGET_REJECT is not set
-CONFIG_IP_NF_TARGET_LOG=m
-CONFIG_IP_NF_TARGET_ULOG=m
-CONFIG_IP_NF_MANGLE=m
-# CONFIG_IP_NF_TARGET_ECN is not set
-# CONFIG_IP_NF_TARGET_TTL is not set
-CONFIG_IP_NF_RAW=m
-CONFIG_IP_NF_ARPTABLES=m
-CONFIG_IP_NF_ARPFILTER=m
-CONFIG_IP_NF_ARP_MANGLE=m
-
-#
-# IPv6: Netfilter Configuration
-#
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_IP6_NF_IPTABLES=m
-# CONFIG_IP6_NF_MATCH_AH is not set
-CONFIG_IP6_NF_MATCH_EUI64=m
-CONFIG_IP6_NF_MATCH_FRAG=m
-CONFIG_IP6_NF_MATCH_OPTS=m
-CONFIG_IP6_NF_MATCH_HL=m
-CONFIG_IP6_NF_MATCH_IPV6HEADER=m
-# CONFIG_IP6_NF_MATCH_MH is not set
-CONFIG_IP6_NF_MATCH_RT=m
-# CONFIG_IP6_NF_TARGET_LOG is not set
-CONFIG_IP6_NF_FILTER=m
-# CONFIG_IP6_NF_TARGET_REJECT is not set
-CONFIG_IP6_NF_MANGLE=m
-# CONFIG_IP6_NF_TARGET_HL is not set
-CONFIG_IP6_NF_RAW=m
-# CONFIG_IP_DCCP is not set
-# CONFIG_IP_SCTP is not set
-# CONFIG_TIPC is not set
-# CONFIG_ATM is not set
-# CONFIG_BRIDGE is not set
-# CONFIG_NET_DSA is not set
-# CONFIG_VLAN_8021Q is not set
-# CONFIG_DECNET is not set
-# CONFIG_LLC2 is not set
-# CONFIG_IPX is not set
-# CONFIG_ATALK is not set
-# CONFIG_X25 is not set
-# CONFIG_LAPB is not set
-# CONFIG_ECONET is not set
-# CONFIG_WAN_ROUTER is not set
-# CONFIG_NET_SCHED is not set
-
-#
-# Network testing
-#
-# CONFIG_NET_PKTGEN is not set
-# CONFIG_HAMRADIO is not set
-# CONFIG_CAN is not set
-CONFIG_IRDA=m
-
-#
-# IrDA protocols
-#
-CONFIG_IRLAN=m
-CONFIG_IRNET=m
-CONFIG_IRCOMM=m
-# CONFIG_IRDA_ULTRA is not set
-
-#
-# IrDA options
-#
-# CONFIG_IRDA_CACHE_LAST_LSAP is not set
-# CONFIG_IRDA_FAST_RR is not set
-# CONFIG_IRDA_DEBUG is not set
-
-#
-# Infrared-port device drivers
-#
-
-#
-# SIR device drivers
-#
-# CONFIG_IRTTY_SIR is not set
-
-#
-# Dongle support
-#
-# CONFIG_KINGSUN_DONGLE is not set
-# CONFIG_KSDAZZLE_DONGLE is not set
-# CONFIG_KS959_DONGLE is not set
-
-#
-# FIR device drivers
-#
-# CONFIG_USB_IRDA is not set
-# CONFIG_SIGMATEL_FIR is not set
-CONFIG_PXA_FICP=m
-# CONFIG_MCS_FIR is not set
-CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
-CONFIG_BT_RFCOMM=m
-CONFIG_BT_RFCOMM_TTY=y
-CONFIG_BT_BNEP=m
-CONFIG_BT_BNEP_MC_FILTER=y
-CONFIG_BT_BNEP_PROTO_FILTER=y
-CONFIG_BT_HIDP=m
-
-#
-# Bluetooth device drivers
-#
-CONFIG_BT_HCIUSB=m
-# CONFIG_BT_HCIUSB_SCO is not set
-# CONFIG_BT_HCIBTUSB is not set
-# CONFIG_BT_HCIBTSDIO is not set
-CONFIG_BT_HCIUART=m
-CONFIG_BT_HCIUART_H4=y
-CONFIG_BT_HCIUART_BCSP=y
-# CONFIG_BT_HCIUART_LL is not set
-CONFIG_BT_HCIBCM203X=m
-CONFIG_BT_HCIBPA10X=m
-CONFIG_BT_HCIBFUSB=m
-CONFIG_BT_HCIDTL1=m
-CONFIG_BT_HCIBT3C=m
-CONFIG_BT_HCIBLUECARD=m
-CONFIG_BT_HCIBTUART=m
-CONFIG_BT_HCIVHCI=m
-# CONFIG_AF_RXRPC is not set
-# CONFIG_PHONET is not set
-CONFIG_WIRELESS=y
-# CONFIG_CFG80211 is not set
-# CONFIG_WIRELESS_OLD_REGULATORY is not set
-# CONFIG_WIRELESS_EXT is not set
-# CONFIG_MAC80211 is not set
-CONFIG_IEEE80211=m
-# CONFIG_IEEE80211_DEBUG is not set
-CONFIG_IEEE80211_CRYPT_WEP=m
-# CONFIG_IEEE80211_CRYPT_CCMP is not set
-# CONFIG_IEEE80211_CRYPT_TKIP is not set
-# CONFIG_RFKILL is not set
-# CONFIG_NET_9P is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_CONNECTOR is not set
-CONFIG_MTD=y
-# CONFIG_MTD_DEBUG is not set
-# CONFIG_MTD_CONCAT is not set
-CONFIG_MTD_PARTITIONS=y
-# CONFIG_MTD_REDBOOT_PARTS is not set
-CONFIG_MTD_CMDLINE_PARTS=y
-# CONFIG_MTD_AFS_PARTS is not set
-# CONFIG_MTD_AR7_PARTS is not set
-
-#
-# User Modules And Translation Layers
-#
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLKDEVS=y
-CONFIG_MTD_BLOCK=y
-# CONFIG_FTL is not set
-# CONFIG_NFTL is not set
-# CONFIG_INFTL is not set
-# CONFIG_RFD_FTL is not set
-# CONFIG_SSFDC is not set
-# CONFIG_MTD_OOPS is not set
-
-#
-# RAM/ROM/Flash chip drivers
-#
-# CONFIG_MTD_CFI is not set
-# CONFIG_MTD_JEDECPROBE is not set
-CONFIG_MTD_MAP_BANK_WIDTH_1=y
-CONFIG_MTD_MAP_BANK_WIDTH_2=y
-CONFIG_MTD_MAP_BANK_WIDTH_4=y
-# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
-# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
-CONFIG_MTD_CFI_I1=y
-CONFIG_MTD_CFI_I2=y
-# CONFIG_MTD_CFI_I4 is not set
-# CONFIG_MTD_CFI_I8 is not set
-# CONFIG_MTD_RAM is not set
-CONFIG_MTD_ROM=y
-# CONFIG_MTD_ABSENT is not set
-
-#
-# Mapping drivers for chip access
-#
-CONFIG_MTD_COMPLEX_MAPPINGS=y
-# CONFIG_MTD_PHYSMAP is not set
-CONFIG_MTD_SHARP_SL=y
-# CONFIG_MTD_PLATRAM is not set
-
-#
-# Self-contained MTD device drivers
-#
-# CONFIG_MTD_DATAFLASH is not set
-# CONFIG_MTD_M25P80 is not set
-# CONFIG_MTD_SLRAM is not set
-# CONFIG_MTD_PHRAM is not set
-# CONFIG_MTD_MTDRAM is not set
-# CONFIG_MTD_BLOCK2MTD is not set
-
-#
-# Disk-On-Chip Device Drivers
-#
-# CONFIG_MTD_DOC2000 is not set
-# CONFIG_MTD_DOC2001 is not set
-# CONFIG_MTD_DOC2001PLUS is not set
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-# CONFIG_MTD_NAND_ECC_SMC is not set
-# CONFIG_MTD_NAND_MUSEUM_IDS is not set
-# CONFIG_MTD_NAND_H1900 is not set
-CONFIG_MTD_NAND_IDS=y
-# CONFIG_MTD_NAND_DISKONCHIP is not set
-CONFIG_MTD_NAND_SHARPSL=y
-# CONFIG_MTD_NAND_NANDSIM is not set
-# CONFIG_MTD_NAND_PLATFORM is not set
-# CONFIG_MTD_ALAUDA is not set
-# CONFIG_MTD_ONENAND is not set
-
-#
-# UBI - Unsorted block images
-#
-# CONFIG_MTD_UBI is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-# CONFIG_BLK_DEV_NBD is not set
-# CONFIG_BLK_DEV_UB is not set
-# CONFIG_BLK_DEV_RAM is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_ATA_OVER_ETH is not set
-CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
-# CONFIG_ENCLOSURE_SERVICES is not set
-CONFIG_HAVE_IDE=y
-CONFIG_IDE=y
-
-#
-# Please see Documentation/ide/ide.txt for help/info on IDE drives
-#
-# CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
-CONFIG_BLK_DEV_IDECS=y
-# CONFIG_BLK_DEV_IDECD is not set
-# CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
-# CONFIG_BLK_DEV_IDESCSI is not set
-# CONFIG_IDE_TASK_IOCTL is not set
-CONFIG_IDE_PROC_FS=y
-
-#
-# IDE chipset support/bugfixes
-#
-# CONFIG_BLK_DEV_PLATFORM is not set
-# CONFIG_BLK_DEV_IDEDMA is not set
-
-#
-# SCSI device support
-#
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=m
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-# CONFIG_BLK_DEV_SR_VENDOR is not set
-CONFIG_CHR_DEV_SG=m
-# CONFIG_CHR_DEV_SCH is not set
-
-#
-# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
-#
-CONFIG_SCSI_MULTI_LUN=y
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_ISCSI_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_ISCSI_TCP is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-CONFIG_NETDEVICES=y
-# CONFIG_DUMMY is not set
-# CONFIG_BONDING is not set
-# CONFIG_MACVLAN is not set
-# CONFIG_EQUALIZER is not set
-# CONFIG_TUN is not set
-# CONFIG_VETH is not set
-# CONFIG_PHYLIB is not set
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=m
-# CONFIG_AX88796 is not set
-# CONFIG_SMC91X is not set
-# CONFIG_DM9000 is not set
-# CONFIG_ENC28J60 is not set
-# CONFIG_SMC911X is not set
-# CONFIG_IBM_NEW_EMAC_ZMII is not set
-# CONFIG_IBM_NEW_EMAC_RGMII is not set
-# CONFIG_IBM_NEW_EMAC_TAH is not set
-# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
-# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
-# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
-# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
-# CONFIG_B44 is not set
-CONFIG_NETDEV_1000=y
-CONFIG_NETDEV_10000=y
-
-#
-# Wireless LAN
-#
-# CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
-# CONFIG_IWLWIFI_LEDS is not set
-
-#
-# USB Network Adapters
-#
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-CONFIG_USB_NET_AX8817X=m
-CONFIG_USB_NET_CDCETHER=m
-# CONFIG_USB_NET_DM9601 is not set
-# CONFIG_USB_NET_SMSC95XX is not set
-# CONFIG_USB_NET_GL620A is not set
-CONFIG_USB_NET_NET1080=m
-# CONFIG_USB_NET_PLUSB is not set
-# CONFIG_USB_NET_MCS7830 is not set
-# CONFIG_USB_NET_RNDIS_HOST is not set
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_USB_NET_ZAURUS=m
-CONFIG_NET_PCMCIA=y
-# CONFIG_PCMCIA_3C589 is not set
-# CONFIG_PCMCIA_3C574 is not set
-# CONFIG_PCMCIA_FMVJ18X is not set
-CONFIG_PCMCIA_PCNET=m
-# CONFIG_PCMCIA_NMCLAN is not set
-# CONFIG_PCMCIA_SMC91C92 is not set
-# CONFIG_PCMCIA_XIRC2PS is not set
-# CONFIG_PCMCIA_AXNET is not set
-# CONFIG_WAN is not set
-CONFIG_PPP=m
-# CONFIG_PPP_MULTILINK is not set
-# CONFIG_PPP_FILTER is not set
-CONFIG_PPP_ASYNC=m
-# CONFIG_PPP_SYNC_TTY is not set
-# CONFIG_PPP_DEFLATE is not set
-CONFIG_PPP_BSDCOMP=m
-# CONFIG_PPP_MPPE is not set
-# CONFIG_PPPOE is not set
-# CONFIG_PPPOL2TP is not set
-# CONFIG_SLIP is not set
-CONFIG_SLHC=m
-# CONFIG_NETCONSOLE is not set
-# CONFIG_NETPOLL is not set
-# CONFIG_NET_POLL_CONTROLLER is not set
-# CONFIG_ISDN is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-CONFIG_INPUT_FF_MEMLESS=m
-# CONFIG_INPUT_POLLDEV is not set
-
-#
-# Userland interfaces
-#
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-# CONFIG_INPUT_APMPOWER is not set
-
-#
-# Input Device Drivers
-#
-CONFIG_INPUT_KEYBOARD=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
-# CONFIG_KEYBOARD_NEWTON is not set
-# CONFIG_KEYBOARD_STOWAWAY is not set
-# CONFIG_KEYBOARD_CORGI is not set
-CONFIG_KEYBOARD_SPITZ=y
-# CONFIG_KEYBOARD_PXA27x is not set
-# CONFIG_KEYBOARD_GPIO is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ADS7846=y
-# CONFIG_TOUCHSCREEN_CORGI is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-CONFIG_INPUT_MISC=y
-# CONFIG_INPUT_ATI_REMOTE is not set
-# CONFIG_INPUT_ATI_REMOTE2 is not set
-# CONFIG_INPUT_KEYSPAN_REMOTE is not set
-# CONFIG_INPUT_POWERMATE is not set
-# CONFIG_INPUT_YEALINK is not set
-# CONFIG_INPUT_CM109 is not set
-CONFIG_INPUT_UINPUT=m
-
-#
-# Hardware I/O ports
-#
-# CONFIG_SERIO is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=m
-CONFIG_SERIAL_8250_CS=m
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SERIAL_8250_EXTENDED is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_PXA=y
-CONFIG_SERIAL_PXA_CONSOLE=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-CONFIG_UNIX98_PTYS=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=m
-# CONFIG_NVRAM is not set
-# CONFIG_R3964 is not set
-
-#
-# PCMCIA character devices
-#
-# CONFIG_SYNCLINK_CS is not set
-# CONFIG_CARDMAN_4000 is not set
-# CONFIG_CARDMAN_4040 is not set
-# CONFIG_IPWIRELESS is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-CONFIG_I2C=y
-CONFIG_I2C_BOARDINFO=y
-# CONFIG_I2C_CHARDEV is not set
-CONFIG_I2C_HELPER_AUTO=y
-
-#
-# I2C Hardware Bus support
-#
-
-#
-# I2C system bus drivers (mostly embedded / system-on-chip)
-#
-# CONFIG_I2C_GPIO is not set
-# CONFIG_I2C_OCORES is not set
-CONFIG_I2C_PXA=y
-# CONFIG_I2C_PXA_SLAVE is not set
-# CONFIG_I2C_SIMTEC is not set
-
-#
-# External I2C/SMBus adapter drivers
-#
-# CONFIG_I2C_PARPORT_LIGHT is not set
-# CONFIG_I2C_TAOS_EVM is not set
-# CONFIG_I2C_TINY_USB is not set
-
-#
-# Other I2C/SMBus bus drivers
-#
-# CONFIG_I2C_PCA_PLATFORM is not set
-# CONFIG_I2C_STUB is not set
-
-#
-# Miscellaneous I2C Chip support
-#
-# CONFIG_DS1682 is not set
-# CONFIG_EEPROM_AT24 is not set
-# CONFIG_EEPROM_LEGACY is not set
-# CONFIG_SENSORS_PCF8574 is not set
-# CONFIG_PCF8575 is not set
-# CONFIG_SENSORS_PCA9539 is not set
-# CONFIG_SENSORS_PCF8591 is not set
-# CONFIG_TPS65010 is not set
-# CONFIG_SENSORS_MAX6875 is not set
-# CONFIG_SENSORS_TSL2550 is not set
-# CONFIG_I2C_DEBUG_CORE is not set
-# CONFIG_I2C_DEBUG_ALGO is not set
-# CONFIG_I2C_DEBUG_BUS is not set
-# CONFIG_I2C_DEBUG_CHIP is not set
-CONFIG_SPI=y
-# CONFIG_SPI_DEBUG is not set
-CONFIG_SPI_MASTER=y
-
-#
-# SPI Master Controller Drivers
-#
-# CONFIG_SPI_BITBANG is not set
-CONFIG_SPI_PXA2XX=y
-
-#
-# SPI Protocol Masters
-#
-# CONFIG_EEPROM_AT25 is not set
-# CONFIG_SPI_SPIDEV is not set
-# CONFIG_SPI_TLE62X0 is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# I2C GPIO expanders:
-#
-# CONFIG_GPIO_MAX732X is not set
-# CONFIG_GPIO_PCA953X is not set
-# CONFIG_GPIO_PCF857X is not set
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-# CONFIG_GPIO_MAX7301 is not set
-# CONFIG_GPIO_MCP23S08 is not set
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-CONFIG_HWMON=y
-# CONFIG_HWMON_VID is not set
-# CONFIG_SENSORS_AD7414 is not set
-# CONFIG_SENSORS_AD7418 is not set
-# CONFIG_SENSORS_ADCXX is not set
-# CONFIG_SENSORS_ADM1021 is not set
-# CONFIG_SENSORS_ADM1025 is not set
-# CONFIG_SENSORS_ADM1026 is not set
-# CONFIG_SENSORS_ADM1029 is not set
-# CONFIG_SENSORS_ADM1031 is not set
-# CONFIG_SENSORS_ADM9240 is not set
-# CONFIG_SENSORS_ADT7470 is not set
-# CONFIG_SENSORS_ADT7473 is not set
-# CONFIG_SENSORS_ATXP1 is not set
-# CONFIG_SENSORS_DS1621 is not set
-# CONFIG_SENSORS_F71805F is not set
-# CONFIG_SENSORS_F71882FG is not set
-# CONFIG_SENSORS_F75375S is not set
-# CONFIG_SENSORS_GL518SM is not set
-# CONFIG_SENSORS_GL520SM is not set
-# CONFIG_SENSORS_IT87 is not set
-# CONFIG_SENSORS_LM63 is not set
-# CONFIG_SENSORS_LM70 is not set
-# CONFIG_SENSORS_LM75 is not set
-# CONFIG_SENSORS_LM77 is not set
-# CONFIG_SENSORS_LM78 is not set
-# CONFIG_SENSORS_LM80 is not set
-# CONFIG_SENSORS_LM83 is not set
-# CONFIG_SENSORS_LM85 is not set
-# CONFIG_SENSORS_LM87 is not set
-# CONFIG_SENSORS_LM90 is not set
-# CONFIG_SENSORS_LM92 is not set
-# CONFIG_SENSORS_LM93 is not set
-CONFIG_SENSORS_MAX1111=y
-# CONFIG_SENSORS_MAX1619 is not set
-# CONFIG_SENSORS_MAX6650 is not set
-# CONFIG_SENSORS_PC87360 is not set
-# CONFIG_SENSORS_PC87427 is not set
-# CONFIG_SENSORS_DME1737 is not set
-# CONFIG_SENSORS_SMSC47M1 is not set
-# CONFIG_SENSORS_SMSC47M192 is not set
-# CONFIG_SENSORS_SMSC47B397 is not set
-# CONFIG_SENSORS_ADS7828 is not set
-# CONFIG_SENSORS_THMC50 is not set
-# CONFIG_SENSORS_VT1211 is not set
-# CONFIG_SENSORS_W83781D is not set
-# CONFIG_SENSORS_W83791D is not set
-# CONFIG_SENSORS_W83792D is not set
-# CONFIG_SENSORS_W83793 is not set
-# CONFIG_SENSORS_W83L785TS is not set
-# CONFIG_SENSORS_W83L786NG is not set
-# CONFIG_SENSORS_W83627HF is not set
-# CONFIG_SENSORS_W83627EHF is not set
-# CONFIG_HWMON_DEBUG_CHIP is not set
-# CONFIG_THERMAL is not set
-# CONFIG_THERMAL_HWMON is not set
-# CONFIG_WATCHDOG is not set
-
-#
-# Sonics Silicon Backplane
-#
-CONFIG_SSB_POSSIBLE=y
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_UCB1400_CORE is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_MFD_WM8400 is not set
-# CONFIG_MFD_WM8350_I2C is not set
-
-#
-# Multimedia devices
-#
-
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-CONFIG_FB=y
-# CONFIG_FIRMWARE_EDID is not set
-# CONFIG_FB_DDC is not set
-# CONFIG_FB_BOOT_VESA_SUPPORT is not set
-CONFIG_FB_CFB_FILLRECT=y
-CONFIG_FB_CFB_COPYAREA=y
-CONFIG_FB_CFB_IMAGEBLIT=y
-# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
-# CONFIG_FB_SYS_FILLRECT is not set
-# CONFIG_FB_SYS_COPYAREA is not set
-# CONFIG_FB_SYS_IMAGEBLIT is not set
-# CONFIG_FB_FOREIGN_ENDIAN is not set
-# CONFIG_FB_SYS_FOPS is not set
-# CONFIG_FB_SVGALIB is not set
-# CONFIG_FB_MACMODES is not set
-# CONFIG_FB_BACKLIGHT is not set
-# CONFIG_FB_MODE_HELPERS is not set
-# CONFIG_FB_TILEBLITTING is not set
-
-#
-# Frame buffer hardware drivers
-#
-# CONFIG_FB_S1D13XXX is not set
-CONFIG_FB_PXA=y
-# CONFIG_FB_PXA_SMARTPANEL is not set
-# CONFIG_FB_PXA_PARAMETERS is not set
-# CONFIG_FB_MBX is not set
-# CONFIG_FB_W100 is not set
-# CONFIG_FB_VIRTUAL is not set
-# CONFIG_FB_METRONOME is not set
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_LCD_CORGI=y
-# CONFIG_LCD_LTV350QV is not set
-# CONFIG_LCD_ILI9320 is not set
-# CONFIG_LCD_TDO24M is not set
-# CONFIG_LCD_VGG2432A4 is not set
-# CONFIG_LCD_PLATFORM is not set
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_BACKLIGHT_CORGI is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
-CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
-CONFIG_FONTS=y
-CONFIG_FONT_8x8=y
-CONFIG_FONT_8x16=y
-# CONFIG_FONT_6x11 is not set
-# CONFIG_FONT_7x14 is not set
-# CONFIG_FONT_PEARL_8x8 is not set
-# CONFIG_FONT_ACORN_8x8 is not set
-# CONFIG_FONT_MINI_4x6 is not set
-# CONFIG_FONT_SUN8x16 is not set
-# CONFIG_FONT_SUN12x22 is not set
-# CONFIG_FONT_10x18 is not set
-# CONFIG_LOGO is not set
-# CONFIG_SOUND is not set
-CONFIG_HID_SUPPORT=y
-CONFIG_HID=y
-# CONFIG_HID_DEBUG is not set
-# CONFIG_HIDRAW is not set
-
-#
-# USB Input Devices
-#
-CONFIG_USB_HID=m
-# CONFIG_HID_PID is not set
-# CONFIG_USB_HIDDEV is not set
-
-#
-# USB HID Boot Protocol drivers
-#
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-
-#
-# Special HID drivers
-#
-CONFIG_HID_COMPAT=y
-CONFIG_HID_A4TECH=m
-CONFIG_HID_APPLE=m
-CONFIG_HID_BELKIN=m
-CONFIG_HID_BRIGHT=m
-CONFIG_HID_CHERRY=m
-CONFIG_HID_CHICONY=m
-CONFIG_HID_CYPRESS=m
-CONFIG_HID_DELL=m
-CONFIG_HID_EZKEY=m
-CONFIG_HID_GYRATION=m
-CONFIG_HID_LOGITECH=m
-# CONFIG_LOGITECH_FF is not set
-# CONFIG_LOGIRUMBLEPAD2_FF is not set
-CONFIG_HID_MICROSOFT=m
-CONFIG_HID_MONTEREY=m
-CONFIG_HID_PANTHERLORD=m
-# CONFIG_PANTHERLORD_FF is not set
-CONFIG_HID_PETALYNX=m
-CONFIG_HID_SAMSUNG=m
-CONFIG_HID_SONY=m
-CONFIG_HID_SUNPLUS=m
-CONFIG_THRUSTMASTER_FF=m
-CONFIG_ZEROPLUS_FF=m
-CONFIG_USB_SUPPORT=y
-CONFIG_USB_ARCH_HAS_HCD=y
-CONFIG_USB_ARCH_HAS_OHCI=y
-# CONFIG_USB_ARCH_HAS_EHCI is not set
-CONFIG_USB=m
-# CONFIG_USB_DEBUG is not set
-# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
-
-#
-# Miscellaneous USB options
-#
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_DEVICE_CLASS=y
-# CONFIG_USB_DYNAMIC_MINORS is not set
-# CONFIG_USB_SUSPEND is not set
-# CONFIG_USB_OTG is not set
-# CONFIG_USB_OTG_WHITELIST is not set
-# CONFIG_USB_OTG_BLACKLIST_HUB is not set
-CONFIG_USB_MON=y
-
-#
-# USB Host Controller Drivers
-#
-# CONFIG_USB_C67X00_HCD is not set
-# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
-CONFIG_USB_OHCI_HCD=m
-# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
-# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
-CONFIG_USB_OHCI_LITTLE_ENDIAN=y
-CONFIG_USB_SL811_HCD=m
-CONFIG_USB_SL811_CS=m
-# CONFIG_USB_R8A66597_HCD is not set
-# CONFIG_USB_MUSB_HDRC is not set
-# CONFIG_USB_GADGET_MUSB_HDRC is not set
-
-#
-# USB Device Class drivers
-#
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-# CONFIG_USB_WDM is not set
-# CONFIG_USB_TMC is not set
-
-#
-# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
-#
-
-#
-# may also be needed; see USB_STORAGE Help for more information
-#
-CONFIG_USB_STORAGE=m
-# CONFIG_USB_STORAGE_DEBUG is not set
-# CONFIG_USB_STORAGE_DATAFAB is not set
-# CONFIG_USB_STORAGE_FREECOM is not set
-# CONFIG_USB_STORAGE_ISD200 is not set
-# CONFIG_USB_STORAGE_DPCM is not set
-# CONFIG_USB_STORAGE_USBAT is not set
-# CONFIG_USB_STORAGE_SDDR09 is not set
-# CONFIG_USB_STORAGE_SDDR55 is not set
-# CONFIG_USB_STORAGE_JUMPSHOT is not set
-# CONFIG_USB_STORAGE_ALAUDA is not set
-# CONFIG_USB_STORAGE_ONETOUCH is not set
-# CONFIG_USB_STORAGE_KARMA is not set
-# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
-# CONFIG_USB_LIBUSUAL is not set
-
-#
-# USB Imaging devices
-#
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-
-#
-# USB port drivers
-#
-CONFIG_USB_SERIAL=m
-CONFIG_USB_EZUSB=y
-CONFIG_USB_SERIAL_GENERIC=y
-# CONFIG_USB_SERIAL_AIRCABLE is not set
-# CONFIG_USB_SERIAL_ARK3116 is not set
-CONFIG_USB_SERIAL_BELKIN=m
-# CONFIG_USB_SERIAL_CH341 is not set
-# CONFIG_USB_SERIAL_WHITEHEAT is not set
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-# CONFIG_USB_SERIAL_CP2101 is not set
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-# CONFIG_USB_SERIAL_FUNSOFT is not set
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_GARMIN=m
-CONFIG_USB_SERIAL_IPW=m
-# CONFIG_USB_SERIAL_IUU is not set
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
-# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-# CONFIG_USB_SERIAL_MOS7720 is not set
-# CONFIG_USB_SERIAL_MOS7840 is not set
-# CONFIG_USB_SERIAL_MOTOROLA is not set
-# CONFIG_USB_SERIAL_NAVMAN is not set
-CONFIG_USB_SERIAL_PL2303=m
-# CONFIG_USB_SERIAL_OTI6858 is not set
-# CONFIG_USB_SERIAL_SPCP8X5 is not set
-# CONFIG_USB_SERIAL_HP4X is not set
-CONFIG_USB_SERIAL_SAFE=m
-# CONFIG_USB_SERIAL_SAFE_PADDED is not set
-# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
-CONFIG_USB_SERIAL_TI=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-# CONFIG_USB_SERIAL_OPTION is not set
-CONFIG_USB_SERIAL_OMNINET=m
-# CONFIG_USB_SERIAL_DEBUG is not set
-
-#
-# USB Miscellaneous drivers
-#
-CONFIG_USB_EMI62=m
-CONFIG_USB_EMI26=m
-# CONFIG_USB_ADUTUX is not set
-# CONFIG_USB_SEVSEG is not set
-CONFIG_USB_RIO500=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-# CONFIG_USB_BERRY_CHARGE is not set
-CONFIG_USB_LED=m
-# CONFIG_USB_CYPRESS_CY7C63 is not set
-CONFIG_USB_CYTHERM=m
-# CONFIG_USB_PHIDGET is not set
-CONFIG_USB_IDMOUSE=m
-# CONFIG_USB_FTDI_ELAN is not set
-# CONFIG_USB_APPLEDISPLAY is not set
-# CONFIG_USB_LD is not set
-# CONFIG_USB_TRANCEVIBRATOR is not set
-# CONFIG_USB_IOWARRIOR is not set
-# CONFIG_USB_TEST is not set
-# CONFIG_USB_ISIGHTFW is not set
-# CONFIG_USB_VST is not set
-CONFIG_USB_GADGET=m
-# CONFIG_USB_GADGET_DEBUG is not set
-# CONFIG_USB_GADGET_DEBUG_FILES is not set
-CONFIG_USB_GADGET_VBUS_DRAW=2
-CONFIG_USB_GADGET_SELECTED=y
-# CONFIG_USB_GADGET_AT91 is not set
-# CONFIG_USB_GADGET_ATMEL_USBA is not set
-# CONFIG_USB_GADGET_FSL_USB2 is not set
-# CONFIG_USB_GADGET_LH7A40X is not set
-# CONFIG_USB_GADGET_OMAP is not set
-# CONFIG_USB_GADGET_PXA25X is not set
-# CONFIG_USB_GADGET_PXA27X is not set
-# CONFIG_USB_GADGET_S3C2410 is not set
-# CONFIG_USB_GADGET_M66592 is not set
-# CONFIG_USB_GADGET_AMD5536UDC is not set
-# CONFIG_USB_GADGET_FSL_QE is not set
-# CONFIG_USB_GADGET_NET2280 is not set
-# CONFIG_USB_GADGET_GOKU is not set
-CONFIG_USB_GADGET_DUMMY_HCD=y
-CONFIG_USB_DUMMY_HCD=m
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_ETH_RNDIS=y
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-# CONFIG_USB_FILE_STORAGE_TEST is not set
-CONFIG_USB_G_SERIAL=m
-# CONFIG_USB_MIDI_GADGET is not set
-# CONFIG_USB_G_PRINTER is not set
-# CONFIG_USB_CDC_COMPOSITE is not set
-CONFIG_MMC=y
-# CONFIG_MMC_DEBUG is not set
-# CONFIG_MMC_UNSAFE_RESUME is not set
-
-#
-# MMC/SD/SDIO Card Drivers
-#
-CONFIG_MMC_BLOCK=y
-CONFIG_MMC_BLOCK_BOUNCE=y
-# CONFIG_SDIO_UART is not set
-# CONFIG_MMC_TEST is not set
-
-#
-# MMC/SD/SDIO Host Controller Drivers
-#
-CONFIG_MMC_PXA=y
-# CONFIG_MMC_SDHCI is not set
-# CONFIG_MMC_SPI is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_ACCESSIBILITY is not set
-# CONFIG_NEW_LEDS is not set
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-
-#
-# Voltage and Current regulators
-#
-# CONFIG_REGULATOR is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
-# CONFIG_UIO is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-# CONFIG_EXT2_FS_XIP is not set
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-# CONFIG_EXT4_FS is not set
-CONFIG_JBD=y
-CONFIG_FS_MBCACHE=y
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-CONFIG_FILE_LOCKING=y
-# CONFIG_XFS_FS is not set
-# CONFIG_OCFS2_FS is not set
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-# CONFIG_TMPFS_POSIX_ACL is not set
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-
-#
-# Miscellaneous filesystems
-#
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_DEBUG=0
-CONFIG_JFFS2_FS_WRITEBUFFER=y
-# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
-CONFIG_JFFS2_SUMMARY=y
-# CONFIG_JFFS2_FS_XATTR is not set
-CONFIG_JFFS2_COMPRESSION_OPTIONS=y
-CONFIG_JFFS2_ZLIB=y
-# CONFIG_JFFS2_LZO is not set
-CONFIG_JFFS2_RTIME=y
-CONFIG_JFFS2_RUBIN=y
-# CONFIG_JFFS2_CMODE_NONE is not set
-CONFIG_JFFS2_CMODE_PRIORITY=y
-# CONFIG_JFFS2_CMODE_SIZE is not set
-# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
-CONFIG_CRAMFS=m
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-# CONFIG_ROMFS_FS is not set
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-CONFIG_NETWORK_FILESYSTEMS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-# CONFIG_NFS_V3_ACL is not set
-CONFIG_NFS_V4=y
-# CONFIG_NFSD is not set
-CONFIG_LOCKD=m
-CONFIG_LOCKD_V4=y
-CONFIG_NFS_COMMON=y
-CONFIG_SUNRPC=m
-CONFIG_SUNRPC_GSS=m
-# CONFIG_SUNRPC_REGISTER_V4 is not set
-CONFIG_RPCSEC_GSS_KRB5=m
-# CONFIG_RPCSEC_GSS_SPKM3 is not set
-CONFIG_SMB_FS=m
-CONFIG_SMB_NLS_DEFAULT=y
-CONFIG_SMB_NLS_REMOTE="cp437"
-# CONFIG_CIFS is not set
-# CONFIG_NCP_FS is not set
-# CONFIG_CODA_FS is not set
-# CONFIG_AFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-# CONFIG_BSD_DISKLABEL is not set
-# CONFIG_MINIX_SUBPARTITION is not set
-# CONFIG_SOLARIS_X86_PARTITION is not set
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-# CONFIG_NLS_ASCII is not set
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-CONFIG_NLS_UTF8=y
-# CONFIG_DLM is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_DEBUG_RT_MUTEXES is not set
-# CONFIG_RT_MUTEX_TESTER is not set
-# CONFIG_DEBUG_SPINLOCK is not set
-# CONFIG_DEBUG_MUTEXES is not set
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-# CONFIG_DEBUG_INFO is not set
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-# CONFIG_DEBUG_MEMORY_INIT is not set
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-CONFIG_FRAME_POINTER=y
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-# CONFIG_SYSCTL_SYSCALL_CHECK is not set
-CONFIG_HAVE_FTRACE=y
-CONFIG_HAVE_DYNAMIC_FTRACE=y
-# CONFIG_FTRACE is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
-# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-# CONFIG_DEBUG_USER is not set
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-# CONFIG_DEBUG_ICEDCC is not set
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_SECURITY_FILE_CAPABILITIES is not set
-CONFIG_CRYPTO=y
-
-#
-# Crypto core or helper
-#
-# CONFIG_CRYPTO_FIPS is not set
-CONFIG_CRYPTO_ALGAPI=y
-CONFIG_CRYPTO_AEAD=y
-CONFIG_CRYPTO_BLKCIPHER=y
-CONFIG_CRYPTO_HASH=y
-CONFIG_CRYPTO_RNG=y
-CONFIG_CRYPTO_MANAGER=y
-# CONFIG_CRYPTO_GF128MUL is not set
-CONFIG_CRYPTO_NULL=m
-# CONFIG_CRYPTO_CRYPTD is not set
-CONFIG_CRYPTO_AUTHENC=m
-CONFIG_CRYPTO_TEST=m
-
-#
-# Authenticated Encryption with Associated Data
-#
-# CONFIG_CRYPTO_CCM is not set
-# CONFIG_CRYPTO_GCM is not set
-# CONFIG_CRYPTO_SEQIV is not set
-
-#
-# Block modes
-#
-CONFIG_CRYPTO_CBC=m
-# CONFIG_CRYPTO_CTR is not set
-# CONFIG_CRYPTO_CTS is not set
-CONFIG_CRYPTO_ECB=m
-# CONFIG_CRYPTO_LRW is not set
-# CONFIG_CRYPTO_PCBC is not set
-# CONFIG_CRYPTO_XTS is not set
-
-#
-# Hash modes
-#
-CONFIG_CRYPTO_HMAC=y
-# CONFIG_CRYPTO_XCBC is not set
-
-#
-# Digest
-#
-CONFIG_CRYPTO_CRC32C=m
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MD5=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-# CONFIG_CRYPTO_RMD128 is not set
-# CONFIG_CRYPTO_RMD160 is not set
-# CONFIG_CRYPTO_RMD256 is not set
-# CONFIG_CRYPTO_RMD320 is not set
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-# CONFIG_CRYPTO_TGR192 is not set
-CONFIG_CRYPTO_WP512=m
-
-#
-# Ciphers
-#
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_ARC4=m
-CONFIG_CRYPTO_BLOWFISH=m
-# CONFIG_CRYPTO_CAMELLIA is not set
-CONFIG_CRYPTO_CAST5=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_DES=m
-# CONFIG_CRYPTO_FCRYPT is not set
-CONFIG_CRYPTO_KHAZAD=m
-# CONFIG_CRYPTO_SALSA20 is not set
-# CONFIG_CRYPTO_SEED is not set
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRYPTO_TWOFISH_COMMON=m
-
-#
-# Compression
-#
-CONFIG_CRYPTO_DEFLATE=m
-# CONFIG_CRYPTO_LZO is not set
-
-#
-# Random Number Generation
-#
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRYPTO_HW=y
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_CRC_CCITT=y
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-CONFIG_LIBCRC32C=m
-CONFIG_ZLIB_INFLATE=y
-CONFIG_ZLIB_DEFLATE=y
-CONFIG_PLIST=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_IOPORT=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/zaurus_defconfig b/arch/arm/configs/zaurus_defconfig
new file mode 100644
index 0000000..a9904bb
--- /dev/null
+++ b/arch/arm/configs/zaurus_defconfig
@@ -0,0 +1,1726 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.35-rc1
+# Fri Jun  4 13:43:35 2010
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_ARCH_MTD_XIP=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_LZO=y
+CONFIG_KERNEL_GZIP=y
+# CONFIG_KERNEL_BZIP2 is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_LZO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_TREE_PREEMPT_RCU is not set
+# CONFIG_TINY_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=20
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_PERF_COUNTERS is not set
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+# CONFIG_OPROFILE is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+# CONFIG_MUTEX_SPIN_ON_OWNER is not set
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_BCMRING is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_CNS3XXX is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_NUC93X is not set
+# CONFIG_ARCH_PNX4008 is not set
+CONFIG_ARCH_PXA=y
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P6440 is not set
+# CONFIG_ARCH_S5P6442 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_NOMADIK is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+# CONFIG_PLAT_SPEAR is not set
+
+#
+# Intel PXA2xx/PXA3xx Implementations
+#
+
+#
+# Intel/Marvell Dev Platforms (sorted by hardware release time)
+#
+# CONFIG_ARCH_LUBBOCK is not set
+# CONFIG_MACH_MAINSTONE is not set
+# CONFIG_MACH_ZYLONITE300 is not set
+# CONFIG_MACH_ZYLONITE320 is not set
+# CONFIG_MACH_LITTLETON is not set
+# CONFIG_MACH_TAVOREVB is not set
+# CONFIG_MACH_SAAR is not set
+
+#
+# Third Party Dev Platforms (sorted by vendor name)
+#
+# CONFIG_ARCH_PXA_IDP is not set
+# CONFIG_ARCH_VIPER is not set
+# CONFIG_MACH_ARCOM_ZEUS is not set
+# CONFIG_MACH_BALLOON3 is not set
+# CONFIG_MACH_CSB726 is not set
+# CONFIG_MACH_ARMCORE is not set
+# CONFIG_MACH_EM_X270 is not set
+# CONFIG_MACH_EXEDA is not set
+# CONFIG_MACH_CM_X300 is not set
+# CONFIG_MACH_CAPC7117 is not set
+# CONFIG_ARCH_GUMSTIX is not set
+# CONFIG_MACH_INTELMOTE2 is not set
+# CONFIG_MACH_STARGATE2 is not set
+# CONFIG_MACH_XCEP is not set
+# CONFIG_TRIZEPS_PXA is not set
+# CONFIG_MACH_LOGICPD_PXA270 is not set
+# CONFIG_MACH_PCM027 is not set
+# CONFIG_MACH_COLIBRI is not set
+# CONFIG_MACH_COLIBRI300 is not set
+# CONFIG_MACH_COLIBRI320 is not set
+# CONFIG_MACH_VPAC270 is not set
+
+#
+# End-user Products (sorted by vendor name)
+#
+# CONFIG_MACH_H4700 is not set
+# CONFIG_MACH_H5000 is not set
+# CONFIG_MACH_HIMALAYA is not set
+# CONFIG_MACH_MAGICIAN is not set
+# CONFIG_MACH_MIOA701 is not set
+# CONFIG_PXA_EZX is not set
+# CONFIG_MACH_MP900C is not set
+# CONFIG_ARCH_PXA_PALM is not set
+# CONFIG_MACH_RAUMFELD_RC is not set
+# CONFIG_MACH_RAUMFELD_CONNECTOR is not set
+# CONFIG_MACH_RAUMFELD_SPEAKER is not set
+CONFIG_PXA_SHARPSL=y
+CONFIG_SHARPSL_PM=y
+CONFIG_SHARPSL_PM_MAX1111=y
+CONFIG_MACH_POODLE=y
+CONFIG_MACH_CORGI=y
+CONFIG_MACH_SHEPHERD=y
+CONFIG_MACH_HUSKY=y
+CONFIG_MACH_AKITA=y
+CONFIG_MACH_SPITZ=y
+CONFIG_MACH_BORZOI=y
+CONFIG_MACH_TOSA=y
+# CONFIG_MACH_ICONTROL is not set
+# CONFIG_ARCH_PXA_ESERIES is not set
+# CONFIG_MACH_ZIPIT2 is not set
+CONFIG_PXA25x=y
+CONFIG_PXA27x=y
+CONFIG_PXA_SHARP_C7xx=y
+CONFIG_PXA_SHARP_Cxx00=y
+CONFIG_TOSA_BT=m
+# CONFIG_TOSA_USE_EXT_KEYCODES is not set
+CONFIG_PXA_HAVE_BOARD_IRQS=y
+CONFIG_PXA_SSP=y
+CONFIG_PLAT_PXA=y
+
+#
+# Processor Type
+#
+CONFIG_CPU_XSCALE=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5T=y
+CONFIG_CPU_PABRT_LEGACY=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_DCACHE_DISABLE is not set
+CONFIG_ARM_L1_CACHE_SHIFT=5
+CONFIG_IWMMXT=y
+CONFIG_XSCALE_PMU=y
+CONFIG_CPU_HAS_PMU=y
+CONFIG_SHARP_LOCOMO=y
+CONFIG_SHARP_PARAM=y
+CONFIG_SHARP_SCOOP=y
+CONFIG_COMMON_CLKDEV=y
+
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCCARD=y
+CONFIG_PCMCIA=y
+CONFIG_PCMCIA_LOAD_CIS=y
+
+#
+# PC-card bridges
+#
+CONFIG_PCMCIA_SOC_COMMON=y
+CONFIG_PCMCIA_PXA2XX=y
+# CONFIG_PCMCIA_DEBUG is not set
+
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT_NONE is not set
+CONFIG_PREEMPT_VOLUNTARY=y
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=999999
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="root=/dev/mmcblk0p1 rootfstype=ext2 rootwait console=ttyS0,115200n8 noinitrd debug no_console_suspend"
+CONFIG_CMDLINE_FORCE=y
+# CONFIG_XIP_KERNEL is not set
+CONFIG_KEXEC=y
+CONFIG_ATAGS_PROC=y
+
+#
+# CPU Power Management
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_DEBUG=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_PXA=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+CONFIG_BINFMT_AOUT=y
+CONFIG_BINFMT_MISC=y
+
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_APM_EMULATION=y
+# CONFIG_PM_RUNTIME is not set
+CONFIG_PM_OPS=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+CONFIG_IRDA=y
+
+#
+# IrDA protocols
+#
+CONFIG_IRLAN=y
+CONFIG_IRCOMM=y
+CONFIG_IRDA_ULTRA=y
+
+#
+# IrDA options
+#
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRDA_FAST_RR=y
+# CONFIG_IRDA_DEBUG is not set
+
+#
+# Infrared-port device drivers
+#
+
+#
+# SIR device drivers
+#
+# CONFIG_IRTTY_SIR is not set
+
+#
+# Dongle support
+#
+
+#
+# FIR device drivers
+#
+CONFIG_PXA_FICP=y
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=m
+CONFIG_RFKILL_LEDS=y
+# CONFIG_RFKILL_INPUT is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_DATAFLASH is not set
+# CONFIG_MTD_M25P80 is not set
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_SM_COMMON is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018
+# CONFIG_MTD_NAND_H1900 is not set
+CONFIG_MTD_NAND_GPIO=y
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_SHARPSL=y
+# CONFIG_MTD_NAND_NANDSIM is not set
+CONFIG_MTD_NAND_PLATFORM=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+# CONFIG_INPUT_APMPOWER is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_TCA6416 is not set
+CONFIG_KEYBOARD_MATRIX=y
+# CONFIG_KEYBOARD_LM8323 is not set
+CONFIG_KEYBOARD_LOCOMO=y
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_PXA27x is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ADS7846=y
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
+# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_N_GSM is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+CONFIG_SERIAL_PXA=y
+CONFIG_SERIAL_PXA_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_SYNCLINK_CS is not set
+# CONFIG_CARDMAN_4000 is not set
+# CONFIG_CARDMAN_4040 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+CONFIG_I2C_PXA=y
+# CONFIG_I2C_PXA_SLAVE is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_BITBANG is not set
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_PXA2XX=y
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+# CONFIG_SPI_SPIDEV is not set
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_IT8761E is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_ADP5588 is not set
+
+#
+# PCI GPIO expanders:
+#
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+CONFIG_SENSORS_MAX1111=y
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_SA1100_WATCHDOG=y
+# CONFIG_MAX63XX_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TC35892 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_MC13783 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_AB8500_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+# CONFIG_FB_MODE_HELPERS is not set
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_S1D13XXX is not set
+CONFIG_FB_PXA=y
+# CONFIG_FB_PXA_OVERLAY is not set
+# CONFIG_FB_PXA_SMARTPANEL is not set
+# CONFIG_FB_PXA_PARAMETERS is not set
+# CONFIG_FB_MBX is not set
+CONFIG_FB_W100=y
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_CORGI is not set
+# CONFIG_LCD_L4F00242T03 is not set
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=y
+CONFIG_LCD_TOSA=y
+# CONFIG_LCD_S6E63M0 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_LOCOMO=y
+CONFIG_BACKLIGHT_TOSA=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+# CONFIG_FONT_8x16 is not set
+CONFIG_FONT_6x11=y
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+CONFIG_FONT_MINI_4x6=y
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+# CONFIG_LOGO is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+CONFIG_SND_PXA2XX_LIB=y
+# CONFIG_SND_PXA2XX_AC97 is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_PCMCIA=y
+# CONFIG_SND_VXPOCKET is not set
+# CONFIG_SND_PDAUDIOCF is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_PXA2XX_SOC=y
+CONFIG_SND_PXA2XX_SOC_I2S=y
+CONFIG_SND_PXA2XX_SOC_CORGI=y
+CONFIG_SND_PXA2XX_SOC_SPITZ=y
+CONFIG_SND_PXA2XX_SOC_POODLE=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_WM8731=y
+CONFIG_SND_SOC_WM8750=y
+# CONFIG_SOUND_PRIME is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AT91 is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+CONFIG_USB_GADGET_PXA25X=y
+CONFIG_USB_PXA25X=y
+# CONFIG_USB_PXA25X_SMALL is not set
+# CONFIG_USB_GADGET_R8A66597 is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_MASS_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_NOKIA is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_WEBCAM is not set
+
+#
+# OTG and related infrastructure
+#
+CONFIG_USB_OTG_UTILS=y
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_PXA=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_MMC_SPI is not set
+# CONFIG_MEMSTICK is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+CONFIG_LEDS_LOCOMO=y
+CONFIG_LEDS_PCA9532=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_DAC124S085 is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_SA1100=y
+CONFIG_RTC_DRV_PXA=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+# CONFIG_EXT4_FS_POSIX_ACL is not set
+# CONFIG_EXT4_FS_SECURITY is not set
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+# CONFIG_NFS_FS is not set
+# CONFIG_NFSD is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_DEBUG_ICEDCC is not set
+# CONFIG_OC_ETM is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_DEFAULT_SECURITY_SELINUX is not set
+# CONFIG_DEFAULT_SECURITY_SMACK is not set
+# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=m
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=m
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
+CONFIG_GENERIC_ATOMIC64=y
-- 
1.7.0.4



From eric.y.miao at gmail.com  Sat Jun  5 04:03:44 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 5 Jun 2010 16:03:44 +0800
Subject: [PATCH 2/4] [ARM] pxa: merge all pxa2xx board configs into 
	pxa2xx_defconfig
In-Reply-To: <1275724538-5075-3-git-send-email-eric.y.miao@gmail.com>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com> 
	<1275724538-5075-3-git-send-email-eric.y.miao@gmail.com>
Message-ID: <AANLkTin5mvdRG3R2JGOnAmakRaCXCTTJTGnwmA9gmTVP@mail.gmail.com>

The change is apparently too much, I'm attaching the patch as an
attachment here and compressed :-(

On Sat, Jun 5, 2010 at 3:55 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> From: Eric Miao <eric.y.miao at canonical.com>
>
> Signed-off-by: Eric Miao <eric.y.miao at gmail.com>
> ---
> ?arch/arm/configs/am200epdkit_defconfig ? ?| 1148 ----------
> ?arch/arm/configs/cm_x2xx_defconfig ? ? ? ?| 1961 -----------------
> ?arch/arm/configs/colibri_pxa270_defconfig | 1736 ---------------
> ?arch/arm/configs/em_x270_defconfig ? ? ? ?| 1740 ---------------
> ?arch/arm/configs/eseries_pxa_defconfig ? ?| 1246 -----------
> ?arch/arm/configs/ezx_defconfig ? ? ? ? ? ?| 2000 -----------------
> ?arch/arm/configs/h5000_defconfig ? ? ? ? ?| ?995 ---------
> ?arch/arm/configs/imote2_defconfig ? ? ? ? | 2039 -----------------
> ?arch/arm/configs/lpd270_defconfig ? ? ? ? | 1031 ---------
> ?arch/arm/configs/lubbock_defconfig ? ? ? ?| ?800 -------
> ?arch/arm/configs/magician_defconfig ? ? ? | 1536 -------------
> ?arch/arm/configs/mainstone_defconfig ? ? ?| ?794 -------
> ?arch/arm/configs/palmz72_defconfig ? ? ? ?| ?950 --------
> ?arch/arm/configs/pcm027_defconfig ? ? ? ? | 1095 ---------
> ?arch/arm/configs/pxa255-idp_defconfig ? ? | ?796 -------
> ?arch/arm/configs/pxa2xx_defconfig ? ? ? ? | 3408 +++++++++++++++++++++++++++++
> ?arch/arm/configs/trizeps4_defconfig ? ? ? | 1704 --------------
> ?arch/arm/configs/viper_defconfig ? ? ? ? ?| 1676 --------------
> ?arch/arm/configs/xcep_defconfig ? ? ? ? ? | 1128 ----------
> ?arch/arm/configs/zeus_defconfig ? ? ? ? ? | 2031 -----------------
> ?20 files changed, 3408 insertions(+), 26406 deletions(-)
> ?delete mode 100644 arch/arm/configs/am200epdkit_defconfig
> ?delete mode 100644 arch/arm/configs/cm_x2xx_defconfig
> ?delete mode 100644 arch/arm/configs/colibri_pxa270_defconfig
> ?delete mode 100644 arch/arm/configs/em_x270_defconfig
> ?delete mode 100644 arch/arm/configs/eseries_pxa_defconfig
> ?delete mode 100644 arch/arm/configs/ezx_defconfig
> ?delete mode 100644 arch/arm/configs/h5000_defconfig
> ?delete mode 100644 arch/arm/configs/imote2_defconfig
> ?delete mode 100644 arch/arm/configs/lpd270_defconfig
> ?delete mode 100644 arch/arm/configs/lubbock_defconfig
> ?delete mode 100644 arch/arm/configs/magician_defconfig
> ?delete mode 100644 arch/arm/configs/mainstone_defconfig
> ?delete mode 100644 arch/arm/configs/palmz72_defconfig
> ?delete mode 100644 arch/arm/configs/pcm027_defconfig
> ?delete mode 100644 arch/arm/configs/pxa255-idp_defconfig
> ?create mode 100644 arch/arm/configs/pxa2xx_defconfig
> ?delete mode 100644 arch/arm/configs/trizeps4_defconfig
> ?delete mode 100644 arch/arm/configs/viper_defconfig
> ?delete mode 100644 arch/arm/configs/xcep_defconfig
> ?delete mode 100644 arch/arm/configs/zeus_defconfig
>
> diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig
> deleted file mode 100644
> index 30927ca..0000000
> --- a/arch/arm/configs/am200epdkit_defconfig
> +++ /dev/null
> @@ -1,1148 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.25
> -# Sun Apr 20 00:29:49 2008
> -#
> -CONFIG_ARM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_MMU=y
> -# CONFIG_NO_IOPORT is not set
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -# CONFIG_ARCH_HAS_ILOG2_U32 is not set
> -# CONFIG_ARCH_HAS_ILOG2_U64 is not set
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ARCH_SUPPORTS_AOUT=y
> -CONFIG_ZONE_DMA=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_LOCK_KERNEL=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION="gum"
> -CONFIG_LOCALVERSION_AUTO=y
> -# CONFIG_SWAP is not set
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -# CONFIG_IKCONFIG is not set
> -CONFIG_LOG_BUF_SHIFT=17
> -# CONFIG_CGROUPS is not set
> -CONFIG_GROUP_SCHED=y
> -CONFIG_FAIR_GROUP_SCHED=y
> -# CONFIG_RT_GROUP_SCHED is not set
> -CONFIG_USER_SCHED=y
> -# CONFIG_CGROUP_SCHED is not set
> -CONFIG_SYSFS_DEPRECATED=y
> -CONFIG_SYSFS_DEPRECATED_V2=y
> -# CONFIG_RELAY is not set
> -# CONFIG_NAMESPACES is not set
> -# CONFIG_BLK_DEV_INITRD is not set
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -CONFIG_EMBEDDED=y
> -CONFIG_UID16=y
> -# CONFIG_SYSCTL_SYSCALL is not set
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_COMPAT_BRK=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_ANON_INODES=y
> -# CONFIG_EPOLL is not set
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -# CONFIG_SHMEM is not set
> -# CONFIG_VM_EVENT_COUNTERS is not set
> -CONFIG_SLAB=y
> -# CONFIG_SLUB is not set
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -# CONFIG_MARKERS is not set
> -CONFIG_HAVE_OPROFILE=y
> -# CONFIG_KPROBES is not set
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -CONFIG_PROC_PAGE_MONITOR=y
> -CONFIG_SLABINFO=y
> -CONFIG_RT_MUTEXES=y
> -CONFIG_TINY_SHMEM=y
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -CONFIG_MODULE_UNLOAD=y
> -# CONFIG_MODULE_FORCE_UNLOAD is not set
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -CONFIG_KMOD=y
> -CONFIG_BLOCK=y
> -# CONFIG_LBD is not set
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_LSF is not set
> -# CONFIG_BLK_DEV_BSG is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -# CONFIG_IOSCHED_AS is not set
> -# CONFIG_IOSCHED_DEADLINE is not set
> -# CONFIG_IOSCHED_CFQ is not set
> -# CONFIG_DEFAULT_AS is not set
> -# CONFIG_DEFAULT_DEADLINE is not set
> -# CONFIG_DEFAULT_CFQ is not set
> -CONFIG_DEFAULT_NOOP=y
> -CONFIG_DEFAULT_IOSCHED="noop"
> -CONFIG_CLASSIC_RCU=y
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS7500 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_CO285 is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_ORION is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_MSM7X00A is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -CONFIG_ARCH_GUMSTIX=y
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_ARCH_PXA_ESERIES is not set
> -# CONFIG_MACH_TRIZEPS4 is not set
> -# CONFIG_MACH_EM_X270 is not set
> -# CONFIG_MACH_COLIBRI is not set
> -# CONFIG_MACH_ZYLONITE is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_ARMCORE is not set
> -# CONFIG_MACH_MAGICIAN is not set
> -# CONFIG_MACH_PCM027 is not set
> -CONFIG_MACH_GUMSTIX_F=y
> -CONFIG_PXA25x=y
> -
> -#
> -# Boot options
> -#
> -
> -#
> -# Power management
> -#
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -# CONFIG_OUTER_CACHE is not set
> -# CONFIG_IWMMXT is not set
> -CONFIG_XSCALE_PMU=y
> -
> -#
> -# Bus support
> -#
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -CONFIG_PCCARD=y
> -# CONFIG_PCMCIA_DEBUG is not set
> -CONFIG_PCMCIA=y
> -CONFIG_PCMCIA_LOAD_CIS=y
> -# CONFIG_PCMCIA_IOCTL is not set
> -
> -#
> -# PC-card bridges
> -#
> -CONFIG_PCMCIA_PXA2XX=y
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -# CONFIG_NO_HZ is not set
> -# CONFIG_HIGH_RES_TIMERS is not set
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -CONFIG_PREEMPT=y
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -# CONFIG_OABI_COMPAT is not set
> -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -# CONFIG_SPARSEMEM_STATIC is not set
> -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_RESOURCES_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=1
> -CONFIG_BOUNCE=y
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="console=ttyS0,115200n8 root=1f01 rootfstype=jffs2"
> -# CONFIG_XIP_KERNEL is not set
> -# CONFIG_KEXEC is not set
> -
> -#
> -# CPU Frequency scaling
> -#
> -# CONFIG_CPU_FREQ is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -# CONFIG_PM is not set
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -
> -#
> -# Networking
> -#
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_PACKET=m
> -CONFIG_PACKET_MMAP=y
> -CONFIG_UNIX=y
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -# CONFIG_IP_PNP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_BEET is not set
> -# CONFIG_INET_LRO is not set
> -# CONFIG_INET_DIAG is not set
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -# CONFIG_NETFILTER is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_NET_SCHED is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -# CONFIG_IRDA is not set
> -CONFIG_BT=m
> -CONFIG_BT_L2CAP=m
> -CONFIG_BT_SCO=m
> -CONFIG_BT_RFCOMM=m
> -CONFIG_BT_RFCOMM_TTY=y
> -CONFIG_BT_BNEP=m
> -# CONFIG_BT_BNEP_MC_FILTER is not set
> -# CONFIG_BT_BNEP_PROTO_FILTER is not set
> -# CONFIG_BT_HIDP is not set
> -
> -#
> -# Bluetooth device drivers
> -#
> -# CONFIG_BT_HCIBTSDIO is not set
> -CONFIG_BT_HCIUART=m
> -CONFIG_BT_HCIUART_H4=y
> -# CONFIG_BT_HCIUART_BCSP is not set
> -# CONFIG_BT_HCIUART_LL is not set
> -# CONFIG_BT_HCIDTL1 is not set
> -# CONFIG_BT_HCIBT3C is not set
> -# CONFIG_BT_HCIBLUECARD is not set
> -# CONFIG_BT_HCIBTUART is not set
> -# CONFIG_BT_HCIVHCI is not set
> -# CONFIG_AF_RXRPC is not set
> -
> -#
> -# Wireless
> -#
> -# CONFIG_CFG80211 is not set
> -CONFIG_WIRELESS_EXT=y
> -# CONFIG_MAC80211 is not set
> -CONFIG_IEEE80211=m
> -# CONFIG_IEEE80211_DEBUG is not set
> -CONFIG_IEEE80211_CRYPT_WEP=m
> -# CONFIG_IEEE80211_CRYPT_CCMP is not set
> -# CONFIG_IEEE80211_CRYPT_TKIP is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=y
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_DEBUG_DEVRES is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -# CONFIG_CONNECTOR is not set
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -# CONFIG_MTD_REDBOOT_PARTS is not set
> -# CONFIG_MTD_CMDLINE_PARTS is not set
> -# CONFIG_MTD_AFS_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_MTD_BLKDEVS=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -# CONFIG_MTD_JEDECPROBE is not set
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_NOSWAP=y
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> -CONFIG_MTD_CFI_GEOMETRY=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -# CONFIG_MTD_CFI_I2 is not set
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -# CONFIG_MTD_OTP is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -# CONFIG_MTD_CFI_AMDSTD is not set
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -CONFIG_MTD_COMPLEX_MAPPINGS=y
> -# CONFIG_MTD_PHYSMAP is not set
> -CONFIG_MTD_PXA2XX=y
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -# CONFIG_MTD_NAND is not set
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -CONFIG_BLK_DEV_LOOP=m
> -# CONFIG_BLK_DEV_CRYPTOLOOP is not set
> -# CONFIG_BLK_DEV_NBD is not set
> -# CONFIG_BLK_DEV_RAM is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -CONFIG_MISC_DEVICES=y
> -# CONFIG_EEPROM_93CX6 is not set
> -# CONFIG_ENCLOSURE_SERVICES is not set
> -CONFIG_HAVE_IDE=y
> -CONFIG_IDE=m
> -CONFIG_IDE_MAX_HWIFS=2
> -CONFIG_BLK_DEV_IDE=m
> -
> -#
> -# Please see Documentation/ide/ide.txt for help/info on IDE drives
> -#
> -# CONFIG_BLK_DEV_IDE_SATA is not set
> -CONFIG_BLK_DEV_IDEDISK=m
> -# CONFIG_IDEDISK_MULTI_MODE is not set
> -CONFIG_BLK_DEV_IDECS=m
> -# CONFIG_BLK_DEV_IDECD is not set
> -# CONFIG_BLK_DEV_IDETAPE is not set
> -# CONFIG_BLK_DEV_IDEFLOPPY is not set
> -# CONFIG_IDE_TASK_IOCTL is not set
> -CONFIG_IDE_PROC_FS=y
> -
> -#
> -# IDE chipset support/bugfixes
> -#
> -# CONFIG_BLK_DEV_PLATFORM is not set
> -# CONFIG_BLK_DEV_IDEDMA is not set
> -# CONFIG_BLK_DEV_HD_ONLY is not set
> -# CONFIG_BLK_DEV_HD is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -# CONFIG_SCSI is not set
> -# CONFIG_SCSI_DMA is not set
> -# CONFIG_SCSI_NETLINK is not set
> -# CONFIG_ATA is not set
> -# CONFIG_MD is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_NETDEVICES_MULTIQUEUE is not set
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_MACVLAN is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -# CONFIG_VETH is not set
> -# CONFIG_PHYLIB is not set
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=m
> -# CONFIG_AX88796 is not set
> -CONFIG_SMC91X=m
> -# CONFIG_DM9000 is not set
> -# CONFIG_SMC911X is not set
> -# CONFIG_IBM_NEW_EMAC_ZMII is not set
> -# CONFIG_IBM_NEW_EMAC_RGMII is not set
> -# CONFIG_IBM_NEW_EMAC_TAH is not set
> -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
> -# CONFIG_B44 is not set
> -CONFIG_NETDEV_1000=y
> -# CONFIG_E1000E_ENABLED is not set
> -CONFIG_NETDEV_10000=y
> -
> -#
> -# Wireless LAN
> -#
> -# CONFIG_WLAN_PRE80211 is not set
> -# CONFIG_WLAN_80211 is not set
> -# CONFIG_IWLWIFI_LEDS is not set
> -# CONFIG_NET_PCMCIA is not set
> -# CONFIG_WAN is not set
> -# CONFIG_PPP is not set
> -# CONFIG_SLIP is not set
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -CONFIG_INPUT_MOUSEDEV_PSAUX=y
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> -# CONFIG_INPUT_JOYDEV is not set
> -# CONFIG_INPUT_EVDEV is not set
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -CONFIG_KEYBOARD_ATKBD=y
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_KEYBOARD_STOWAWAY is not set
> -# CONFIG_KEYBOARD_GPIO is not set
> -CONFIG_INPUT_MOUSE=y
> -CONFIG_MOUSE_PS2=y
> -CONFIG_MOUSE_PS2_ALPS=y
> -CONFIG_MOUSE_PS2_LOGIPS2PP=y
> -CONFIG_MOUSE_PS2_SYNAPTICS=y
> -CONFIG_MOUSE_PS2_LIFEBOOK=y
> -CONFIG_MOUSE_PS2_TRACKPOINT=y
> -# CONFIG_MOUSE_PS2_TOUCHKIT is not set
> -# CONFIG_MOUSE_SERIAL is not set
> -# CONFIG_MOUSE_APPLETOUCH is not set
> -# CONFIG_MOUSE_VSXXXAA is not set
> -# CONFIG_MOUSE_GPIO is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -# CONFIG_INPUT_TOUCHSCREEN is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -CONFIG_SERIO=y
> -CONFIG_SERIO_SERPORT=y
> -CONFIG_SERIO_LIBPS2=y
> -# CONFIG_SERIO_RAW is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_LEGACY_PTYS is not set
> -# CONFIG_IPMI_HANDLER is not set
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_NVRAM is not set
> -# CONFIG_R3964 is not set
> -
> -#
> -# PCMCIA character devices
> -#
> -# CONFIG_SYNCLINK_CS is not set
> -# CONFIG_CARDMAN_4000 is not set
> -# CONFIG_CARDMAN_4040 is not set
> -# CONFIG_IPWIRELESS is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -# CONFIG_I2C is not set
> -
> -#
> -# SPI support
> -#
> -# CONFIG_SPI is not set
> -# CONFIG_SPI_MASTER is not set
> -CONFIG_HAVE_GPIO_LIB=y
> -
> -#
> -# GPIO Support
> -#
> -# CONFIG_DEBUG_GPIO is not set
> -
> -#
> -# I2C GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -# CONFIG_W1 is not set
> -# CONFIG_POWER_SUPPLY is not set
> -# CONFIG_HWMON is not set
> -CONFIG_WATCHDOG=y
> -# CONFIG_WATCHDOG_NOWAYOUT is not set
> -
> -#
> -# Watchdog Device Drivers
> -#
> -# CONFIG_SOFT_WATCHDOG is not set
> -CONFIG_SA1100_WATCHDOG=m
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -CONFIG_SSB_POSSIBLE=y
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_MFD_ASIC3 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -
> -#
> -# Multimedia devices
> -#
> -# CONFIG_VIDEO_DEV is not set
> -# CONFIG_DVB_CORE is not set
> -CONFIG_DAB=y
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -CONFIG_FB=y
> -# CONFIG_FIRMWARE_EDID is not set
> -# CONFIG_FB_DDC is not set
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> -CONFIG_FB_SYS_FILLRECT=m
> -CONFIG_FB_SYS_COPYAREA=m
> -CONFIG_FB_SYS_IMAGEBLIT=m
> -CONFIG_FB_SYS_FOPS=m
> -CONFIG_FB_DEFERRED_IO=y
> -# CONFIG_FB_SVGALIB is not set
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -CONFIG_FB_MODE_HELPERS=y
> -CONFIG_FB_TILEBLITTING=y
> -
> -#
> -# Frame buffer hardware drivers
> -#
> -# CONFIG_FB_S1D13XXX is not set
> -CONFIG_FB_PXA=y
> -CONFIG_FB_PXA_PARAMETERS=y
> -CONFIG_FB_MBX=m
> -# CONFIG_FB_METRONOME is not set
> -CONFIG_FB_VIRTUAL=m
> -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -# CONFIG_FRAMEBUFFER_CONSOLE is not set
> -# CONFIG_LOGO is not set
> -
> -#
> -# Sound
> -#
> -CONFIG_SOUND=m
> -
> -#
> -# Advanced Linux Sound Architecture
> -#
> -CONFIG_SND=m
> -CONFIG_SND_TIMER=m
> -CONFIG_SND_PCM=m
> -# CONFIG_SND_SEQUENCER is not set
> -CONFIG_SND_OSSEMUL=y
> -CONFIG_SND_MIXER_OSS=m
> -CONFIG_SND_PCM_OSS=m
> -CONFIG_SND_PCM_OSS_PLUGINS=y
> -# CONFIG_SND_DYNAMIC_MINORS is not set
> -# CONFIG_SND_SUPPORT_OLD_API is not set
> -# CONFIG_SND_VERBOSE_PROCFS is not set
> -# CONFIG_SND_VERBOSE_PRINTK is not set
> -# CONFIG_SND_DEBUG is not set
> -
> -#
> -# Generic devices
> -#
> -CONFIG_SND_AC97_CODEC=m
> -# CONFIG_SND_DUMMY is not set
> -# CONFIG_SND_MTPAV is not set
> -# CONFIG_SND_SERIAL_U16550 is not set
> -# CONFIG_SND_MPU401 is not set
> -
> -#
> -# ALSA ARM devices
> -#
> -CONFIG_SND_PXA2XX_PCM=m
> -CONFIG_SND_PXA2XX_AC97=m
> -
> -#
> -# PCMCIA devices
> -#
> -# CONFIG_SND_VXPOCKET is not set
> -# CONFIG_SND_PDAUDIOCF is not set
> -
> -#
> -# System on Chip audio support
> -#
> -# CONFIG_SND_SOC is not set
> -
> -#
> -# SoC Audio support for SuperH
> -#
> -
> -#
> -# ALSA SoC audio for Freescale SOCs
> -#
> -
> -#
> -# Open Sound System
> -#
> -# CONFIG_SOUND_PRIME is not set
> -CONFIG_AC97_BUS=m
> -CONFIG_HID_SUPPORT=y
> -CONFIG_HID=y
> -# CONFIG_HID_DEBUG is not set
> -# CONFIG_HIDRAW is not set
> -CONFIG_USB_SUPPORT=y
> -CONFIG_USB_ARCH_HAS_HCD=y
> -# CONFIG_USB_ARCH_HAS_OHCI is not set
> -# CONFIG_USB_ARCH_HAS_EHCI is not set
> -# CONFIG_USB is not set
> -
> -#
> -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
> -#
> -CONFIG_USB_GADGET=y
> -# CONFIG_USB_GADGET_DEBUG is not set
> -# CONFIG_USB_GADGET_DEBUG_FILES is not set
> -CONFIG_USB_GADGET_SELECTED=y
> -# CONFIG_USB_GADGET_AMD5536UDC is not set
> -# CONFIG_USB_GADGET_ATMEL_USBA is not set
> -# CONFIG_USB_GADGET_FSL_USB2 is not set
> -# CONFIG_USB_GADGET_NET2280 is not set
> -CONFIG_USB_GADGET_PXA2XX=y
> -CONFIG_USB_PXA2XX=y
> -# CONFIG_USB_PXA2XX_SMALL is not set
> -# CONFIG_USB_GADGET_M66592 is not set
> -# CONFIG_USB_GADGET_GOKU is not set
> -# CONFIG_USB_GADGET_LH7A40X is not set
> -# CONFIG_USB_GADGET_OMAP is not set
> -# CONFIG_USB_GADGET_S3C2410 is not set
> -# CONFIG_USB_GADGET_AT91 is not set
> -# CONFIG_USB_GADGET_DUMMY_HCD is not set
> -# CONFIG_USB_GADGET_DUALSPEED is not set
> -# CONFIG_USB_ZERO is not set
> -CONFIG_USB_ETH=y
> -CONFIG_USB_ETH_RNDIS=y
> -# CONFIG_USB_GADGETFS is not set
> -# CONFIG_USB_FILE_STORAGE is not set
> -# CONFIG_USB_G_SERIAL is not set
> -# CONFIG_USB_MIDI_GADGET is not set
> -# CONFIG_USB_G_PRINTER is not set
> -CONFIG_MMC=y
> -# CONFIG_MMC_DEBUG is not set
> -# CONFIG_MMC_UNSAFE_RESUME is not set
> -
> -#
> -# MMC/SD Card Drivers
> -#
> -CONFIG_MMC_BLOCK=y
> -CONFIG_MMC_BLOCK_BOUNCE=y
> -# CONFIG_SDIO_UART is not set
> -
> -#
> -# MMC/SD Host Controller Drivers
> -#
> -CONFIG_MMC_PXA=y
> -# CONFIG_NEW_LEDS is not set
> -CONFIG_RTC_LIB=y
> -# CONFIG_RTC_CLASS is not set
> -
> -#
> -# File systems
> -#
> -# CONFIG_EXT2_FS is not set
> -# CONFIG_EXT3_FS is not set
> -# CONFIG_EXT4DEV_FS is not set
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -# CONFIG_FS_POSIX_ACL is not set
> -# CONFIG_XFS_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_DNOTIFY is not set
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=y
> -# CONFIG_MSDOS_FS is not set
> -CONFIG_VFAT_FS=y
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -
> -#
> -# Miscellaneous filesystems
> -#
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
> -# CONFIG_JFFS2_SUMMARY is not set
> -# CONFIG_JFFS2_FS_XATTR is not set
> -CONFIG_JFFS2_COMPRESSION_OPTIONS=y
> -CONFIG_JFFS2_ZLIB=y
> -# CONFIG_JFFS2_LZO is not set
> -CONFIG_JFFS2_RTIME=y
> -CONFIG_JFFS2_RUBIN=y
> -# CONFIG_JFFS2_CMODE_NONE is not set
> -CONFIG_JFFS2_CMODE_PRIORITY=y
> -# CONFIG_JFFS2_CMODE_SIZE is not set
> -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -CONFIG_NETWORK_FILESYSTEMS=y
> -# CONFIG_NFS_FS is not set
> -# CONFIG_NFSD is not set
> -# CONFIG_SMB_FS is not set
> -# CONFIG_CIFS is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -CONFIG_PARTITION_ADVANCED=y
> -# CONFIG_ACORN_PARTITION is not set
> -# CONFIG_OSF_PARTITION is not set
> -# CONFIG_AMIGA_PARTITION is not set
> -# CONFIG_ATARI_PARTITION is not set
> -# CONFIG_MAC_PARTITION is not set
> -CONFIG_MSDOS_PARTITION=y
> -# CONFIG_BSD_DISKLABEL is not set
> -# CONFIG_MINIX_SUBPARTITION is not set
> -# CONFIG_SOLARIS_X86_PARTITION is not set
> -# CONFIG_UNIXWARE_DISKLABEL is not set
> -# CONFIG_LDM_PARTITION is not set
> -# CONFIG_SGI_PARTITION is not set
> -# CONFIG_ULTRIX_PARTITION is not set
> -# CONFIG_SUN_PARTITION is not set
> -# CONFIG_KARMA_PARTITION is not set
> -# CONFIG_EFI_PARTITION is not set
> -# CONFIG_SYSV68_PARTITION is not set
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -CONFIG_NLS_CODEPAGE_437=y
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -# CONFIG_NLS_CODEPAGE_850 is not set
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -CONFIG_NLS_ISO8859_1=y
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -# CONFIG_NLS_ISO8859_15 is not set
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -# CONFIG_NLS_UTF8 is not set
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -# CONFIG_MAGIC_SYSRQ is not set
> -# CONFIG_UNUSED_SYMBOLS is not set
> -# CONFIG_DEBUG_FS is not set
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DEBUG_SHIRQ is not set
> -# CONFIG_DETECT_SOFTLOCKUP is not set
> -CONFIG_SCHED_DEBUG=y
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_TIMER_STATS is not set
> -# CONFIG_DEBUG_SLAB is not set
> -# CONFIG_DEBUG_PREEMPT is not set
> -# CONFIG_DEBUG_RT_MUTEXES is not set
> -# CONFIG_RT_MUTEX_TESTER is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -# CONFIG_DEBUG_MUTEXES is not set
> -# CONFIG_DEBUG_LOCK_ALLOC is not set
> -# CONFIG_PROVE_LOCKING is not set
> -# CONFIG_LOCK_STAT is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -# CONFIG_DEBUG_INFO is not set
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_LIST is not set
> -# CONFIG_DEBUG_SG is not set
> -CONFIG_FRAME_POINTER=y
> -# CONFIG_BOOT_PRINTK_DELAY is not set
> -# CONFIG_RCU_TORTURE_TEST is not set
> -# CONFIG_BACKTRACE_SELF_TEST is not set
> -# CONFIG_FAULT_INJECTION is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> -# CONFIG_DEBUG_STACK_USAGE is not set
> -# CONFIG_DEBUG_LL is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITY_FILE_CAPABILITIES is not set
> -CONFIG_CRYPTO=y
> -CONFIG_CRYPTO_ALGAPI=m
> -CONFIG_CRYPTO_BLKCIPHER=m
> -# CONFIG_CRYPTO_SEQIV is not set
> -CONFIG_CRYPTO_MANAGER=m
> -# CONFIG_CRYPTO_HMAC is not set
> -# CONFIG_CRYPTO_XCBC is not set
> -# CONFIG_CRYPTO_NULL is not set
> -# CONFIG_CRYPTO_MD4 is not set
> -# CONFIG_CRYPTO_MD5 is not set
> -# CONFIG_CRYPTO_SHA1 is not set
> -# CONFIG_CRYPTO_SHA256 is not set
> -# CONFIG_CRYPTO_SHA512 is not set
> -# CONFIG_CRYPTO_WP512 is not set
> -# CONFIG_CRYPTO_TGR192 is not set
> -# CONFIG_CRYPTO_GF128MUL is not set
> -CONFIG_CRYPTO_ECB=m
> -CONFIG_CRYPTO_CBC=m
> -CONFIG_CRYPTO_PCBC=m
> -# CONFIG_CRYPTO_LRW is not set
> -# CONFIG_CRYPTO_XTS is not set
> -# CONFIG_CRYPTO_CTR is not set
> -# CONFIG_CRYPTO_GCM is not set
> -# CONFIG_CRYPTO_CCM is not set
> -# CONFIG_CRYPTO_CRYPTD is not set
> -# CONFIG_CRYPTO_DES is not set
> -# CONFIG_CRYPTO_FCRYPT is not set
> -# CONFIG_CRYPTO_BLOWFISH is not set
> -# CONFIG_CRYPTO_TWOFISH is not set
> -# CONFIG_CRYPTO_SERPENT is not set
> -# CONFIG_CRYPTO_AES is not set
> -# CONFIG_CRYPTO_CAST5 is not set
> -# CONFIG_CRYPTO_CAST6 is not set
> -# CONFIG_CRYPTO_TEA is not set
> -CONFIG_CRYPTO_ARC4=m
> -# CONFIG_CRYPTO_KHAZAD is not set
> -# CONFIG_CRYPTO_ANUBIS is not set
> -# CONFIG_CRYPTO_SEED is not set
> -# CONFIG_CRYPTO_SALSA20 is not set
> -# CONFIG_CRYPTO_DEFLATE is not set
> -# CONFIG_CRYPTO_MICHAEL_MIC is not set
> -# CONFIG_CRYPTO_CRC32C is not set
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -# CONFIG_CRYPTO_TEST is not set
> -# CONFIG_CRYPTO_AUTHENC is not set
> -# CONFIG_CRYPTO_LZO is not set
> -CONFIG_CRYPTO_HW=y
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -# CONFIG_CRC_CCITT is not set
> -# CONFIG_CRC16 is not set
> -# CONFIG_CRC_ITU_T is not set
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_PLIST=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> diff --git a/arch/arm/configs/cm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig
> deleted file mode 100644
> index 47d22d0..0000000
> --- a/arch/arm/configs/cm_x2xx_defconfig
> +++ /dev/null
> @@ -1,1961 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.29-rc2
> -# Sun Feb ?1 16:31:36 2009
> -#
> -CONFIG_ARM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_MMU=y
> -# CONFIG_NO_IOPORT is not set
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -# CONFIG_ARCH_HAS_ILOG2_U32 is not set
> -# CONFIG_ARCH_HAS_ILOG2_U64 is not set
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ZONE_DMA=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=""
> -# CONFIG_LOCALVERSION_AUTO is not set
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -CONFIG_IKCONFIG=y
> -CONFIG_IKCONFIG_PROC=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_GROUP_SCHED=y
> -CONFIG_FAIR_GROUP_SCHED=y
> -# CONFIG_RT_GROUP_SCHED is not set
> -CONFIG_USER_SCHED=y
> -# CONFIG_CGROUP_SCHED is not set
> -# CONFIG_CGROUPS is not set
> -CONFIG_SYSFS_DEPRECATED=y
> -CONFIG_SYSFS_DEPRECATED_V2=y
> -# CONFIG_RELAY is not set
> -# CONFIG_NAMESPACES is not set
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_INITRAMFS_SOURCE=""
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -CONFIG_EMBEDDED=y
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -# CONFIG_COMPAT_BRK is not set
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_ANON_INODES=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -CONFIG_SHMEM=y
> -CONFIG_AIO=y
> -# CONFIG_VM_EVENT_COUNTERS is not set
> -CONFIG_PCI_QUIRKS=y
> -# CONFIG_SLUB_DEBUG is not set
> -# CONFIG_SLAB is not set
> -CONFIG_SLUB=y
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -CONFIG_HAVE_OPROFILE=y
> -# CONFIG_KPROBES is not set
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -CONFIG_HAVE_CLK=y
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_RT_MUTEXES=y
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -# CONFIG_MODULE_FORCE_UNLOAD is not set
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -CONFIG_BLOCK=y
> -# CONFIG_LBD is not set
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_BLK_DEV_INTEGRITY is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_AS=y
> -CONFIG_IOSCHED_DEADLINE=y
> -CONFIG_IOSCHED_CFQ=y
> -# CONFIG_DEFAULT_AS is not set
> -# CONFIG_DEFAULT_DEADLINE is not set
> -CONFIG_DEFAULT_CFQ=y
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="cfq"
> -CONFIG_CLASSIC_RCU=y
> -# CONFIG_TREE_RCU is not set
> -# CONFIG_PREEMPT_RCU is not set
> -# CONFIG_TREE_RCU_TRACE is not set
> -# CONFIG_PREEMPT_RCU_TRACE is not set
> -CONFIG_FREEZER=y
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_S3C64XX is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_MSM is not set
> -# CONFIG_ARCH_W90X900 is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -# CONFIG_ARCH_GUMSTIX is not set
> -# CONFIG_MACH_INTELMOTE2 is not set
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_MACH_MP900C is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_ARCH_VIPER is not set
> -# CONFIG_ARCH_PXA_ESERIES is not set
> -# CONFIG_TRIZEPS_PXA is not set
> -# CONFIG_MACH_H5000 is not set
> -# CONFIG_MACH_EM_X270 is not set
> -# CONFIG_MACH_EXEDA is not set
> -# CONFIG_MACH_COLIBRI is not set
> -# CONFIG_MACH_ZYLONITE is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_TAVOREVB is not set
> -# CONFIG_MACH_SAAR is not set
> -CONFIG_MACH_ARMCORE=y
> -# CONFIG_MACH_CM_X300 is not set
> -# CONFIG_MACH_MAGICIAN is not set
> -# CONFIG_MACH_MIOA701 is not set
> -# CONFIG_MACH_PCM027 is not set
> -# CONFIG_ARCH_PXA_PALM is not set
> -# CONFIG_PXA_EZX is not set
> -CONFIG_PXA25x=y
> -CONFIG_PXA27x=y
> -CONFIG_PXA_SSP=y
> -# CONFIG_PXA_PWM is not set
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_PABRT_NOIFAR=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -# CONFIG_OUTER_CACHE is not set
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -CONFIG_DMABOUNCE=y
> -CONFIG_COMMON_CLKDEV=y
> -
> -#
> -# Bus support
> -#
> -CONFIG_PCI=y
> -CONFIG_PCI_SYSCALL=y
> -CONFIG_PCI_HOST_ITE8152=y
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -CONFIG_PCI_LEGACY=y
> -# CONFIG_PCI_DEBUG is not set
> -# CONFIG_PCI_STUB is not set
> -CONFIG_PCCARD=m
> -# CONFIG_PCMCIA_DEBUG is not set
> -CONFIG_PCMCIA=m
> -CONFIG_PCMCIA_LOAD_CIS=y
> -CONFIG_PCMCIA_IOCTL=y
> -CONFIG_CARDBUS=y
> -
> -#
> -# PC-card bridges
> -#
> -CONFIG_YENTA=m
> -# CONFIG_YENTA_O2 is not set
> -# CONFIG_YENTA_RICOH is not set
> -CONFIG_YENTA_TI=y
> -# CONFIG_YENTA_ENE_TUNE is not set
> -# CONFIG_YENTA_TOSHIBA is not set
> -# CONFIG_PD6729 is not set
> -# CONFIG_I82092 is not set
> -CONFIG_PCMCIA_PXA2XX=m
> -CONFIG_PCCARD_NONSTATIC=m
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -CONFIG_NO_HZ=y
> -# CONFIG_HIGH_RES_TIMERS is not set
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -CONFIG_VMSPLIT_3G=y
> -# CONFIG_VMSPLIT_2G is not set
> -# CONFIG_VMSPLIT_1G is not set
> -CONFIG_PAGE_OFFSET=0xC0000000
> -# CONFIG_PREEMPT is not set
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -CONFIG_ARCH_FLATMEM_HAS_HOLES=y
> -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -CONFIG_PAGEFLAGS_EXTENDED=y
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_PHYS_ADDR_T_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=1
> -CONFIG_BOUNCE=y
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_UNEVICTABLE_LRU=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="root=1f03 mem=32M"
> -# CONFIG_XIP_KERNEL is not set
> -# CONFIG_KEXEC is not set
> -
> -#
> -# CPU Power Management
> -#
> -# CONFIG_CPU_FREQ is not set
> -# CONFIG_CPU_IDLE is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> -CONFIG_HAVE_AOUT=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -CONFIG_PM=y
> -# CONFIG_PM_DEBUG is not set
> -CONFIG_PM_SLEEP=y
> -CONFIG_SUSPEND=y
> -CONFIG_SUSPEND_FREEZER=y
> -CONFIG_APM_EMULATION=m
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_COMPAT_NET_DEV_OPS=y
> -CONFIG_PACKET=y
> -CONFIG_PACKET_MMAP=y
> -CONFIG_UNIX=y
> -CONFIG_XFRM=y
> -# CONFIG_XFRM_USER is not set
> -# CONFIG_XFRM_SUB_POLICY is not set
> -# CONFIG_XFRM_MIGRATE is not set
> -# CONFIG_XFRM_STATISTICS is not set
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -CONFIG_IP_MULTICAST=y
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -CONFIG_IP_PNP_BOOTP=y
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_IP_MROUTE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -CONFIG_INET_XFRM_MODE_TRANSPORT=y
> -CONFIG_INET_XFRM_MODE_TUNNEL=y
> -CONFIG_INET_XFRM_MODE_BEET=y
> -# CONFIG_INET_LRO is not set
> -# CONFIG_INET_DIAG is not set
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -# CONFIG_NETFILTER is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_NET_DSA is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_NET_SCHED is not set
> -# CONFIG_DCB is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -# CONFIG_IRDA is not set
> -CONFIG_BT=m
> -CONFIG_BT_L2CAP=m
> -CONFIG_BT_SCO=m
> -CONFIG_BT_RFCOMM=m
> -# CONFIG_BT_RFCOMM_TTY is not set
> -CONFIG_BT_BNEP=m
> -# CONFIG_BT_BNEP_MC_FILTER is not set
> -# CONFIG_BT_BNEP_PROTO_FILTER is not set
> -CONFIG_BT_HIDP=m
> -
> -#
> -# Bluetooth device drivers
> -#
> -# CONFIG_BT_HCIBTUSB is not set
> -# CONFIG_BT_HCIBTSDIO is not set
> -# CONFIG_BT_HCIUART is not set
> -# CONFIG_BT_HCIBCM203X is not set
> -# CONFIG_BT_HCIBPA10X is not set
> -# CONFIG_BT_HCIBFUSB is not set
> -# CONFIG_BT_HCIDTL1 is not set
> -# CONFIG_BT_HCIBT3C is not set
> -# CONFIG_BT_HCIBLUECARD is not set
> -# CONFIG_BT_HCIBTUART is not set
> -# CONFIG_BT_HCIVHCI is not set
> -# CONFIG_AF_RXRPC is not set
> -# CONFIG_PHONET is not set
> -CONFIG_WIRELESS=y
> -# CONFIG_CFG80211 is not set
> -CONFIG_WIRELESS_OLD_REGULATORY=y
> -CONFIG_WIRELESS_EXT=y
> -CONFIG_WIRELESS_EXT_SYSFS=y
> -CONFIG_LIB80211=m
> -# CONFIG_MAC80211 is not set
> -# CONFIG_WIMAX is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=m
> -CONFIG_FIRMWARE_IN_KERNEL=y
> -CONFIG_EXTRA_FIRMWARE=""
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_DEBUG_DEVRES is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -# CONFIG_CONNECTOR is not set
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -# CONFIG_MTD_TESTS is not set
> -# CONFIG_MTD_REDBOOT_PARTS is not set
> -CONFIG_MTD_CMDLINE_PARTS=y
> -# CONFIG_MTD_AFS_PARTS is not set
> -# CONFIG_MTD_AR7_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_MTD_BLKDEVS=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_JEDECPROBE=y
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_NOSWAP=y
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_GEOMETRY is not set
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -# CONFIG_MTD_OTP is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_CFI_AMDSTD=y
> -CONFIG_MTD_CFI_STAA=y
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> -CONFIG_MTD_PHYSMAP=y
> -# CONFIG_MTD_PHYSMAP_COMPAT is not set
> -CONFIG_MTD_PXA2XX=y
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_IMPA7 is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -# CONFIG_MTD_INTEL_VR_NOR is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_PMC551 is not set
> -# CONFIG_MTD_DATAFLASH is not set
> -# CONFIG_MTD_M25P80 is not set
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -CONFIG_MTD_NAND=y
> -# CONFIG_MTD_NAND_VERIFY_WRITE is not set
> -# CONFIG_MTD_NAND_ECC_SMC is not set
> -# CONFIG_MTD_NAND_MUSEUM_IDS is not set
> -# CONFIG_MTD_NAND_H1900 is not set
> -CONFIG_MTD_NAND_GPIO=m
> -CONFIG_MTD_NAND_IDS=y
> -# CONFIG_MTD_NAND_DISKONCHIP is not set
> -# CONFIG_MTD_NAND_SHARPSL is not set
> -# CONFIG_MTD_NAND_CAFE is not set
> -CONFIG_MTD_NAND_CM_X270=y
> -# CONFIG_MTD_NAND_NANDSIM is not set
> -CONFIG_MTD_NAND_PLATFORM=y
> -# CONFIG_MTD_ALAUDA is not set
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# LPDDR flash memory drivers
> -#
> -# CONFIG_MTD_LPDDR is not set
> -# CONFIG_MTD_QINFO_PROBE is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_CPQ_DA is not set
> -# CONFIG_BLK_CPQ_CISS_DA is not set
> -# CONFIG_BLK_DEV_DAC960 is not set
> -# CONFIG_BLK_DEV_UMEM is not set
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -CONFIG_BLK_DEV_LOOP=y
> -# CONFIG_BLK_DEV_CRYPTOLOOP is not set
> -# CONFIG_BLK_DEV_NBD is not set
> -# CONFIG_BLK_DEV_SX8 is not set
> -# CONFIG_BLK_DEV_UB is not set
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_COUNT=16
> -CONFIG_BLK_DEV_RAM_SIZE=4096
> -# CONFIG_BLK_DEV_XIP is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -# CONFIG_MISC_DEVICES is not set
> -CONFIG_HAVE_IDE=y
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -CONFIG_SCSI=y
> -CONFIG_SCSI_DMA=y
> -# CONFIG_SCSI_TGT is not set
> -# CONFIG_SCSI_NETLINK is not set
> -CONFIG_SCSI_PROC_FS=y
> -
> -#
> -# SCSI support type (disk, tape, CD-ROM)
> -#
> -CONFIG_BLK_DEV_SD=y
> -# CONFIG_CHR_DEV_ST is not set
> -# CONFIG_CHR_DEV_OSST is not set
> -# CONFIG_BLK_DEV_SR is not set
> -# CONFIG_CHR_DEV_SG is not set
> -# CONFIG_CHR_DEV_SCH is not set
> -
> -#
> -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
> -#
> -# CONFIG_SCSI_MULTI_LUN is not set
> -# CONFIG_SCSI_CONSTANTS is not set
> -# CONFIG_SCSI_LOGGING is not set
> -# CONFIG_SCSI_SCAN_ASYNC is not set
> -CONFIG_SCSI_WAIT_SCAN=m
> -
> -#
> -# SCSI Transports
> -#
> -# CONFIG_SCSI_SPI_ATTRS is not set
> -# CONFIG_SCSI_FC_ATTRS is not set
> -# CONFIG_SCSI_ISCSI_ATTRS is not set
> -# CONFIG_SCSI_SAS_LIBSAS is not set
> -# CONFIG_SCSI_SRP_ATTRS is not set
> -CONFIG_SCSI_LOWLEVEL=y
> -# CONFIG_ISCSI_TCP is not set
> -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
> -# CONFIG_SCSI_3W_9XXX is not set
> -# CONFIG_SCSI_ACARD is not set
> -# CONFIG_SCSI_AACRAID is not set
> -# CONFIG_SCSI_AIC7XXX is not set
> -# CONFIG_SCSI_AIC7XXX_OLD is not set
> -# CONFIG_SCSI_AIC79XX is not set
> -# CONFIG_SCSI_AIC94XX is not set
> -# CONFIG_SCSI_DPT_I2O is not set
> -# CONFIG_SCSI_ADVANSYS is not set
> -# CONFIG_SCSI_ARCMSR is not set
> -# CONFIG_MEGARAID_NEWGEN is not set
> -# CONFIG_MEGARAID_LEGACY is not set
> -# CONFIG_MEGARAID_SAS is not set
> -# CONFIG_SCSI_HPTIOP is not set
> -# CONFIG_LIBFC is not set
> -# CONFIG_FCOE is not set
> -# CONFIG_SCSI_DMX3191D is not set
> -# CONFIG_SCSI_FUTURE_DOMAIN is not set
> -# CONFIG_SCSI_IPS is not set
> -# CONFIG_SCSI_INITIO is not set
> -# CONFIG_SCSI_INIA100 is not set
> -# CONFIG_SCSI_MVSAS is not set
> -# CONFIG_SCSI_STEX is not set
> -# CONFIG_SCSI_SYM53C8XX_2 is not set
> -# CONFIG_SCSI_IPR is not set
> -# CONFIG_SCSI_QLOGIC_1280 is not set
> -# CONFIG_SCSI_QLA_FC is not set
> -# CONFIG_SCSI_QLA_ISCSI is not set
> -# CONFIG_SCSI_LPFC is not set
> -# CONFIG_SCSI_DC395x is not set
> -# CONFIG_SCSI_DC390T is not set
> -# CONFIG_SCSI_NSP32 is not set
> -# CONFIG_SCSI_DEBUG is not set
> -# CONFIG_SCSI_SRP is not set
> -# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
> -# CONFIG_SCSI_DH is not set
> -CONFIG_ATA=m
> -# CONFIG_ATA_NONSTANDARD is not set
> -# CONFIG_SATA_PMP is not set
> -# CONFIG_SATA_AHCI is not set
> -# CONFIG_SATA_SIL24 is not set
> -CONFIG_ATA_SFF=y
> -# CONFIG_SATA_SVW is not set
> -# CONFIG_ATA_PIIX is not set
> -# CONFIG_SATA_MV is not set
> -# CONFIG_SATA_NV is not set
> -# CONFIG_PDC_ADMA is not set
> -# CONFIG_SATA_QSTOR is not set
> -# CONFIG_SATA_PROMISE is not set
> -# CONFIG_SATA_SX4 is not set
> -# CONFIG_SATA_SIL is not set
> -# CONFIG_SATA_SIS is not set
> -# CONFIG_SATA_ULI is not set
> -# CONFIG_SATA_VIA is not set
> -# CONFIG_SATA_VITESSE is not set
> -# CONFIG_SATA_INIC162X is not set
> -# CONFIG_PATA_ALI is not set
> -# CONFIG_PATA_AMD is not set
> -# CONFIG_PATA_ARTOP is not set
> -# CONFIG_PATA_ATIIXP is not set
> -# CONFIG_PATA_CMD640_PCI is not set
> -# CONFIG_PATA_CMD64X is not set
> -# CONFIG_PATA_CS5520 is not set
> -# CONFIG_PATA_CS5530 is not set
> -# CONFIG_PATA_CYPRESS is not set
> -# CONFIG_PATA_EFAR is not set
> -# CONFIG_ATA_GENERIC is not set
> -# CONFIG_PATA_HPT366 is not set
> -# CONFIG_PATA_HPT37X is not set
> -# CONFIG_PATA_HPT3X2N is not set
> -# CONFIG_PATA_HPT3X3 is not set
> -# CONFIG_PATA_IT821X is not set
> -# CONFIG_PATA_IT8213 is not set
> -# CONFIG_PATA_JMICRON is not set
> -# CONFIG_PATA_TRIFLEX is not set
> -# CONFIG_PATA_MARVELL is not set
> -# CONFIG_PATA_MPIIX is not set
> -# CONFIG_PATA_OLDPIIX is not set
> -# CONFIG_PATA_NETCELL is not set
> -# CONFIG_PATA_NINJA32 is not set
> -# CONFIG_PATA_NS87410 is not set
> -# CONFIG_PATA_NS87415 is not set
> -# CONFIG_PATA_OPTI is not set
> -# CONFIG_PATA_OPTIDMA is not set
> -CONFIG_PATA_PCMCIA=m
> -# CONFIG_PATA_PDC_OLD is not set
> -# CONFIG_PATA_RADISYS is not set
> -# CONFIG_PATA_RZ1000 is not set
> -# CONFIG_PATA_SC1200 is not set
> -# CONFIG_PATA_SERVERWORKS is not set
> -# CONFIG_PATA_PDC2027X is not set
> -# CONFIG_PATA_SIL680 is not set
> -# CONFIG_PATA_SIS is not set
> -# CONFIG_PATA_VIA is not set
> -# CONFIG_PATA_WINBOND is not set
> -# CONFIG_PATA_PLATFORM is not set
> -# CONFIG_PATA_SCH is not set
> -# CONFIG_MD is not set
> -# CONFIG_FUSION is not set
> -
> -#
> -# IEEE 1394 (FireWire) support
> -#
> -
> -#
> -# Enable only one of the two stacks, unless you know what you are doing
> -#
> -# CONFIG_FIREWIRE is not set
> -# CONFIG_IEEE1394 is not set
> -# CONFIG_I2O is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_MACVLAN is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -# CONFIG_VETH is not set
> -# CONFIG_ARCNET is not set
> -# CONFIG_PHYLIB is not set
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=y
> -# CONFIG_AX88796 is not set
> -# CONFIG_HAPPYMEAL is not set
> -# CONFIG_SUNGEM is not set
> -# CONFIG_CASSINI is not set
> -# CONFIG_NET_VENDOR_3COM is not set
> -# CONFIG_SMC91X is not set
> -CONFIG_DM9000=y
> -CONFIG_DM9000_DEBUGLEVEL=1
> -# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
> -# CONFIG_ENC28J60 is not set
> -# CONFIG_SMC911X is not set
> -# CONFIG_SMSC911X is not set
> -# CONFIG_NET_TULIP is not set
> -# CONFIG_HP100 is not set
> -# CONFIG_IBM_NEW_EMAC_ZMII is not set
> -# CONFIG_IBM_NEW_EMAC_RGMII is not set
> -# CONFIG_IBM_NEW_EMAC_TAH is not set
> -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
> -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
> -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
> -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
> -CONFIG_NET_PCI=y
> -# CONFIG_PCNET32 is not set
> -# CONFIG_AMD8111_ETH is not set
> -# CONFIG_ADAPTEC_STARFIRE is not set
> -# CONFIG_B44 is not set
> -# CONFIG_FORCEDETH is not set
> -# CONFIG_E100 is not set
> -# CONFIG_FEALNX is not set
> -# CONFIG_NATSEMI is not set
> -# CONFIG_NE2K_PCI is not set
> -# CONFIG_8139CP is not set
> -CONFIG_8139TOO=m
> -# CONFIG_8139TOO_PIO is not set
> -# CONFIG_8139TOO_TUNE_TWISTER is not set
> -# CONFIG_8139TOO_8129 is not set
> -# CONFIG_8139_OLD_RX_RESET is not set
> -# CONFIG_R6040 is not set
> -# CONFIG_SIS900 is not set
> -# CONFIG_EPIC100 is not set
> -# CONFIG_SMSC9420 is not set
> -# CONFIG_SUNDANCE is not set
> -# CONFIG_TLAN is not set
> -# CONFIG_VIA_RHINE is not set
> -# CONFIG_SC92031 is not set
> -# CONFIG_ATL2 is not set
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -# CONFIG_TR is not set
> -
> -#
> -# Wireless LAN
> -#
> -# CONFIG_WLAN_PRE80211 is not set
> -CONFIG_WLAN_80211=y
> -# CONFIG_PCMCIA_RAYCS is not set
> -CONFIG_LIBERTAS=m
> -# CONFIG_LIBERTAS_USB is not set
> -# CONFIG_LIBERTAS_CS is not set
> -CONFIG_LIBERTAS_SDIO=m
> -# CONFIG_LIBERTAS_DEBUG is not set
> -# CONFIG_HERMES is not set
> -# CONFIG_ATMEL is not set
> -# CONFIG_AIRO_CS is not set
> -# CONFIG_PCMCIA_WL3501 is not set
> -# CONFIG_PRISM54 is not set
> -# CONFIG_USB_ZD1201 is not set
> -# CONFIG_USB_NET_RNDIS_WLAN is not set
> -# CONFIG_IPW2100 is not set
> -# CONFIG_IPW2200 is not set
> -# CONFIG_IWLWIFI_LEDS is not set
> -# CONFIG_HOSTAP is not set
> -
> -#
> -# Enable WiMAX (Networking options) to see the WiMAX drivers
> -#
> -
> -#
> -# USB Network Adapters
> -#
> -# CONFIG_USB_CATC is not set
> -# CONFIG_USB_KAWETH is not set
> -# CONFIG_USB_PEGASUS is not set
> -# CONFIG_USB_RTL8150 is not set
> -# CONFIG_USB_USBNET is not set
> -# CONFIG_NET_PCMCIA is not set
> -# CONFIG_WAN is not set
> -# CONFIG_FDDI is not set
> -# CONFIG_HIPPI is not set
> -CONFIG_PPP=m
> -CONFIG_PPP_MULTILINK=y
> -CONFIG_PPP_FILTER=y
> -CONFIG_PPP_ASYNC=m
> -# CONFIG_PPP_SYNC_TTY is not set
> -CONFIG_PPP_DEFLATE=m
> -CONFIG_PPP_BSDCOMP=m
> -# CONFIG_PPP_MPPE is not set
> -# CONFIG_PPPOE is not set
> -# CONFIG_PPPOL2TP is not set
> -# CONFIG_SLIP is not set
> -CONFIG_SLHC=m
> -# CONFIG_NET_FC is not set
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -CONFIG_INPUT_MOUSEDEV_PSAUX=y
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> -# CONFIG_INPUT_JOYDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -# CONFIG_INPUT_APMPOWER is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -CONFIG_KEYBOARD_ATKBD=y
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_KEYBOARD_STOWAWAY is not set
> -CONFIG_KEYBOARD_PXA27x=m
> -# CONFIG_KEYBOARD_GPIO is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -# CONFIG_TOUCHSCREEN_ADS7846 is not set
> -# CONFIG_TOUCHSCREEN_FUJITSU is not set
> -# CONFIG_TOUCHSCREEN_GUNZE is not set
> -# CONFIG_TOUCHSCREEN_ELO is not set
> -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
> -# CONFIG_TOUCHSCREEN_MTOUCH is not set
> -# CONFIG_TOUCHSCREEN_INEXIO is not set
> -# CONFIG_TOUCHSCREEN_MK712 is not set
> -# CONFIG_TOUCHSCREEN_PENMOUNT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
> -CONFIG_TOUCHSCREEN_UCB1400=m
> -# CONFIG_TOUCHSCREEN_WM97XX is not set
> -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
> -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
> -# CONFIG_TOUCHSCREEN_TSC2007 is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -CONFIG_SERIO=y
> -# CONFIG_SERIO_SERPORT is not set
> -# CONFIG_SERIO_PCIPS2 is not set
> -CONFIG_SERIO_LIBPS2=y
> -# CONFIG_SERIO_RAW is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_CONSOLE_TRANSLATIONS=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -CONFIG_DEVKMEM=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -# CONFIG_NOZOMI is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -# CONFIG_SERIAL_JSM is not set
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=16
> -# CONFIG_IPMI_HANDLER is not set
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_NVRAM is not set
> -# CONFIG_R3964 is not set
> -# CONFIG_APPLICOM is not set
> -
> -#
> -# PCMCIA character devices
> -#
> -# CONFIG_SYNCLINK_CS is not set
> -# CONFIG_CARDMAN_4000 is not set
> -# CONFIG_CARDMAN_4040 is not set
> -# CONFIG_IPWIRELESS is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -CONFIG_DEVPORT=y
> -CONFIG_I2C=y
> -CONFIG_I2C_BOARDINFO=y
> -CONFIG_I2C_CHARDEV=m
> -CONFIG_I2C_HELPER_AUTO=y
> -
> -#
> -# I2C Hardware Bus support
> -#
> -
> -#
> -# PC SMBus host controller drivers
> -#
> -# CONFIG_I2C_ALI1535 is not set
> -# CONFIG_I2C_ALI1563 is not set
> -# CONFIG_I2C_ALI15X3 is not set
> -# CONFIG_I2C_AMD756 is not set
> -# CONFIG_I2C_AMD8111 is not set
> -# CONFIG_I2C_I801 is not set
> -# CONFIG_I2C_ISCH is not set
> -# CONFIG_I2C_PIIX4 is not set
> -# CONFIG_I2C_NFORCE2 is not set
> -# CONFIG_I2C_SIS5595 is not set
> -# CONFIG_I2C_SIS630 is not set
> -# CONFIG_I2C_SIS96X is not set
> -# CONFIG_I2C_VIA is not set
> -# CONFIG_I2C_VIAPRO is not set
> -
> -#
> -# I2C system bus drivers (mostly embedded / system-on-chip)
> -#
> -# CONFIG_I2C_GPIO is not set
> -# CONFIG_I2C_OCORES is not set
> -CONFIG_I2C_PXA=y
> -# CONFIG_I2C_PXA_SLAVE is not set
> -# CONFIG_I2C_SIMTEC is not set
> -
> -#
> -# External I2C/SMBus adapter drivers
> -#
> -# CONFIG_I2C_PARPORT_LIGHT is not set
> -# CONFIG_I2C_TAOS_EVM is not set
> -# CONFIG_I2C_TINY_USB is not set
> -
> -#
> -# Graphics adapter I2C/DDC channel drivers
> -#
> -# CONFIG_I2C_VOODOO3 is not set
> -
> -#
> -# Other I2C/SMBus bus drivers
> -#
> -# CONFIG_I2C_PCA_PLATFORM is not set
> -# CONFIG_I2C_STUB is not set
> -
> -#
> -# Miscellaneous I2C Chip support
> -#
> -# CONFIG_DS1682 is not set
> -# CONFIG_AT24 is not set
> -# CONFIG_SENSORS_EEPROM is not set
> -# CONFIG_SENSORS_PCF8574 is not set
> -# CONFIG_PCF8575 is not set
> -# CONFIG_SENSORS_PCA9539 is not set
> -# CONFIG_SENSORS_PCF8591 is not set
> -# CONFIG_SENSORS_MAX6875 is not set
> -# CONFIG_SENSORS_TSL2550 is not set
> -# CONFIG_I2C_DEBUG_CORE is not set
> -# CONFIG_I2C_DEBUG_ALGO is not set
> -# CONFIG_I2C_DEBUG_BUS is not set
> -# CONFIG_I2C_DEBUG_CHIP is not set
> -CONFIG_SPI=y
> -# CONFIG_SPI_DEBUG is not set
> -CONFIG_SPI_MASTER=y
> -
> -#
> -# SPI Master Controller Drivers
> -#
> -# CONFIG_SPI_BITBANG is not set
> -# CONFIG_SPI_GPIO is not set
> -CONFIG_SPI_PXA2XX=m
> -
> -#
> -# SPI Protocol Masters
> -#
> -# CONFIG_SPI_AT25 is not set
> -# CONFIG_SPI_SPIDEV is not set
> -# CONFIG_SPI_TLE62X0 is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -# CONFIG_DEBUG_GPIO is not set
> -# CONFIG_GPIO_SYSFS is not set
> -
> -#
> -# Memory mapped GPIO expanders:
> -#
> -
> -#
> -# I2C GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX732X is not set
> -# CONFIG_GPIO_PCA953X is not set
> -# CONFIG_GPIO_PCF857X is not set
> -
> -#
> -# PCI GPIO expanders:
> -#
> -# CONFIG_GPIO_BT8XX is not set
> -
> -#
> -# SPI GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX7301 is not set
> -# CONFIG_GPIO_MCP23S08 is not set
> -# CONFIG_W1 is not set
> -# CONFIG_POWER_SUPPLY is not set
> -# CONFIG_HWMON is not set
> -# CONFIG_THERMAL is not set
> -# CONFIG_THERMAL_HWMON is not set
> -# CONFIG_WATCHDOG is not set
> -CONFIG_SSB_POSSIBLE=y
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_CORE is not set
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_MFD_ASIC3 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -CONFIG_UCB1400_CORE=m
> -# CONFIG_TPS65010 is not set
> -# CONFIG_TWL4030_CORE is not set
> -# CONFIG_MFD_TMIO is not set
> -# CONFIG_MFD_T7L66XB is not set
> -# CONFIG_MFD_TC6387XB is not set
> -# CONFIG_MFD_TC6393XB is not set
> -# CONFIG_PMIC_DA903X is not set
> -# CONFIG_MFD_WM8400 is not set
> -# CONFIG_MFD_WM8350_I2C is not set
> -# CONFIG_MFD_PCF50633 is not set
> -
> -#
> -# Multimedia devices
> -#
> -
> -#
> -# Multimedia core support
> -#
> -CONFIG_VIDEO_DEV=m
> -CONFIG_VIDEO_V4L2_COMMON=m
> -# CONFIG_VIDEO_ALLOW_V4L1 is not set
> -CONFIG_VIDEO_V4L1_COMPAT=y
> -# CONFIG_DVB_CORE is not set
> -CONFIG_VIDEO_MEDIA=m
> -
> -#
> -# Multimedia drivers
> -#
> -# CONFIG_MEDIA_ATTACH is not set
> -CONFIG_MEDIA_TUNER=m
> -CONFIG_MEDIA_TUNER_CUSTOMIZE=y
> -# CONFIG_MEDIA_TUNER_SIMPLE is not set
> -# CONFIG_MEDIA_TUNER_TDA8290 is not set
> -# CONFIG_MEDIA_TUNER_TDA827X is not set
> -# CONFIG_MEDIA_TUNER_TDA18271 is not set
> -# CONFIG_MEDIA_TUNER_TDA9887 is not set
> -# CONFIG_MEDIA_TUNER_TEA5761 is not set
> -# CONFIG_MEDIA_TUNER_TEA5767 is not set
> -# CONFIG_MEDIA_TUNER_MT20XX is not set
> -# CONFIG_MEDIA_TUNER_MT2060 is not set
> -# CONFIG_MEDIA_TUNER_MT2266 is not set
> -# CONFIG_MEDIA_TUNER_MT2131 is not set
> -# CONFIG_MEDIA_TUNER_QT1010 is not set
> -# CONFIG_MEDIA_TUNER_XC2028 is not set
> -# CONFIG_MEDIA_TUNER_XC5000 is not set
> -# CONFIG_MEDIA_TUNER_MXL5005S is not set
> -# CONFIG_MEDIA_TUNER_MXL5007T is not set
> -CONFIG_VIDEO_V4L2=m
> -CONFIG_VIDEOBUF_GEN=m
> -CONFIG_VIDEOBUF_DMA_SG=m
> -CONFIG_VIDEO_CAPTURE_DRIVERS=y
> -# CONFIG_VIDEO_ADV_DEBUG is not set
> -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
> -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
> -
> -#
> -# Encoders/decoders and other helper chips
> -#
> -
> -#
> -# Audio decoders
> -#
> -# CONFIG_VIDEO_TVAUDIO is not set
> -# CONFIG_VIDEO_TDA7432 is not set
> -# CONFIG_VIDEO_TDA9840 is not set
> -# CONFIG_VIDEO_TDA9875 is not set
> -# CONFIG_VIDEO_TEA6415C is not set
> -# CONFIG_VIDEO_TEA6420 is not set
> -# CONFIG_VIDEO_MSP3400 is not set
> -# CONFIG_VIDEO_CS5345 is not set
> -# CONFIG_VIDEO_CS53L32A is not set
> -# CONFIG_VIDEO_M52790 is not set
> -# CONFIG_VIDEO_TLV320AIC23B is not set
> -# CONFIG_VIDEO_WM8775 is not set
> -# CONFIG_VIDEO_WM8739 is not set
> -# CONFIG_VIDEO_VP27SMPX is not set
> -
> -#
> -# Video decoders
> -#
> -# CONFIG_VIDEO_OV7670 is not set
> -# CONFIG_VIDEO_TCM825X is not set
> -# CONFIG_VIDEO_SAA711X is not set
> -# CONFIG_VIDEO_SAA717X is not set
> -# CONFIG_VIDEO_TVP514X is not set
> -# CONFIG_VIDEO_TVP5150 is not set
> -
> -#
> -# Video and audio decoders
> -#
> -# CONFIG_VIDEO_CX25840 is not set
> -
> -#
> -# MPEG video encoders
> -#
> -# CONFIG_VIDEO_CX2341X is not set
> -
> -#
> -# Video encoders
> -#
> -# CONFIG_VIDEO_SAA7127 is not set
> -
> -#
> -# Video improvement chips
> -#
> -# CONFIG_VIDEO_UPD64031A is not set
> -# CONFIG_VIDEO_UPD64083 is not set
> -# CONFIG_VIDEO_VIVI is not set
> -# CONFIG_VIDEO_BT848 is not set
> -# CONFIG_VIDEO_SAA5246A is not set
> -# CONFIG_VIDEO_SAA5249 is not set
> -# CONFIG_VIDEO_SAA7134 is not set
> -# CONFIG_VIDEO_HEXIUM_ORION is not set
> -# CONFIG_VIDEO_HEXIUM_GEMINI is not set
> -# CONFIG_VIDEO_CX88 is not set
> -# CONFIG_VIDEO_IVTV is not set
> -# CONFIG_VIDEO_CAFE_CCIC is not set
> -CONFIG_SOC_CAMERA=m
> -# CONFIG_SOC_CAMERA_MT9M001 is not set
> -CONFIG_SOC_CAMERA_MT9M111=m
> -# CONFIG_SOC_CAMERA_MT9T031 is not set
> -# CONFIG_SOC_CAMERA_MT9V022 is not set
> -# CONFIG_SOC_CAMERA_TW9910 is not set
> -# CONFIG_SOC_CAMERA_PLATFORM is not set
> -# CONFIG_SOC_CAMERA_OV772X is not set
> -CONFIG_VIDEO_PXA27x=m
> -# CONFIG_VIDEO_SH_MOBILE_CEU is not set
> -# CONFIG_V4L_USB_DRIVERS is not set
> -# CONFIG_RADIO_ADAPTERS is not set
> -# CONFIG_DAB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_DRM is not set
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -CONFIG_FB=y
> -# CONFIG_FIRMWARE_EDID is not set
> -# CONFIG_FB_DDC is not set
> -# CONFIG_FB_BOOT_VESA_SUPPORT is not set
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> -# CONFIG_FB_SYS_FILLRECT is not set
> -# CONFIG_FB_SYS_COPYAREA is not set
> -# CONFIG_FB_SYS_IMAGEBLIT is not set
> -# CONFIG_FB_FOREIGN_ENDIAN is not set
> -# CONFIG_FB_SYS_FOPS is not set
> -# CONFIG_FB_SVGALIB is not set
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -
> -#
> -# Frame buffer hardware drivers
> -#
> -# CONFIG_FB_CIRRUS is not set
> -# CONFIG_FB_PM2 is not set
> -# CONFIG_FB_CYBER2000 is not set
> -# CONFIG_FB_ASILIANT is not set
> -# CONFIG_FB_IMSTT is not set
> -# CONFIG_FB_S1D13XXX is not set
> -# CONFIG_FB_NVIDIA is not set
> -# CONFIG_FB_RIVA is not set
> -# CONFIG_FB_MATROX is not set
> -# CONFIG_FB_RADEON is not set
> -# CONFIG_FB_ATY128 is not set
> -# CONFIG_FB_ATY is not set
> -# CONFIG_FB_S3 is not set
> -# CONFIG_FB_SAVAGE is not set
> -# CONFIG_FB_SIS is not set
> -# CONFIG_FB_VIA is not set
> -# CONFIG_FB_NEOMAGIC is not set
> -# CONFIG_FB_KYRO is not set
> -# CONFIG_FB_3DFX is not set
> -# CONFIG_FB_VOODOO1 is not set
> -# CONFIG_FB_VT8623 is not set
> -# CONFIG_FB_TRIDENT is not set
> -# CONFIG_FB_ARK is not set
> -# CONFIG_FB_PM3 is not set
> -# CONFIG_FB_CARMINE is not set
> -CONFIG_FB_PXA=y
> -# CONFIG_FB_PXA_OVERLAY is not set
> -# CONFIG_FB_PXA_SMARTPANEL is not set
> -CONFIG_FB_PXA_PARAMETERS=y
> -CONFIG_FB_MBX=m
> -# CONFIG_FB_W100 is not set
> -# CONFIG_FB_VIRTUAL is not set
> -# CONFIG_FB_METRONOME is not set
> -# CONFIG_FB_MB862XX is not set
> -CONFIG_BACKLIGHT_LCD_SUPPORT=y
> -# CONFIG_LCD_CLASS_DEVICE is not set
> -# CONFIG_BACKLIGHT_CLASS_DEVICE is not set
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
> -# CONFIG_FONTS is not set
> -CONFIG_FONT_8x8=y
> -CONFIG_FONT_8x16=y
> -CONFIG_LOGO=y
> -CONFIG_LOGO_LINUX_MONO=y
> -CONFIG_LOGO_LINUX_VGA16=y
> -CONFIG_LOGO_LINUX_CLUT224=y
> -CONFIG_SOUND=m
> -CONFIG_SOUND_OSS_CORE=y
> -CONFIG_SND=m
> -CONFIG_SND_TIMER=m
> -CONFIG_SND_PCM=m
> -# CONFIG_SND_SEQUENCER is not set
> -CONFIG_SND_OSSEMUL=y
> -CONFIG_SND_MIXER_OSS=m
> -CONFIG_SND_PCM_OSS=m
> -CONFIG_SND_PCM_OSS_PLUGINS=y
> -# CONFIG_SND_DYNAMIC_MINORS is not set
> -CONFIG_SND_SUPPORT_OLD_API=y
> -CONFIG_SND_VERBOSE_PROCFS=y
> -# CONFIG_SND_VERBOSE_PRINTK is not set
> -# CONFIG_SND_DEBUG is not set
> -CONFIG_SND_VMASTER=y
> -CONFIG_SND_AC97_CODEC=m
> -# CONFIG_SND_DRIVERS is not set
> -# CONFIG_SND_PCI is not set
> -CONFIG_SND_ARM=y
> -CONFIG_SND_PXA2XX_PCM=m
> -CONFIG_SND_PXA2XX_LIB=m
> -CONFIG_SND_PXA2XX_LIB_AC97=y
> -CONFIG_SND_PXA2XX_AC97=m
> -# CONFIG_SND_SPI is not set
> -# CONFIG_SND_USB is not set
> -# CONFIG_SND_PCMCIA is not set
> -# CONFIG_SND_SOC is not set
> -# CONFIG_SOUND_PRIME is not set
> -CONFIG_AC97_BUS=m
> -CONFIG_HID_SUPPORT=y
> -CONFIG_HID=y
> -CONFIG_HID_DEBUG=y
> -# CONFIG_HIDRAW is not set
> -
> -#
> -# USB Input Devices
> -#
> -CONFIG_USB_HID=y
> -# CONFIG_HID_PID is not set
> -# CONFIG_USB_HIDDEV is not set
> -
> -#
> -# Special HID drivers
> -#
> -CONFIG_HID_COMPAT=y
> -CONFIG_HID_A4TECH=y
> -CONFIG_HID_APPLE=y
> -CONFIG_HID_BELKIN=y
> -CONFIG_HID_CHERRY=y
> -CONFIG_HID_CHICONY=y
> -CONFIG_HID_CYPRESS=y
> -CONFIG_HID_EZKEY=y
> -CONFIG_HID_GYRATION=y
> -CONFIG_HID_LOGITECH=y
> -# CONFIG_LOGITECH_FF is not set
> -# CONFIG_LOGIRUMBLEPAD2_FF is not set
> -CONFIG_HID_MICROSOFT=y
> -CONFIG_HID_MONTEREY=y
> -# CONFIG_HID_NTRIG is not set
> -CONFIG_HID_PANTHERLORD=y
> -# CONFIG_PANTHERLORD_FF is not set
> -CONFIG_HID_PETALYNX=y
> -CONFIG_HID_SAMSUNG=y
> -CONFIG_HID_SONY=y
> -CONFIG_HID_SUNPLUS=y
> -# CONFIG_GREENASIA_FF is not set
> -# CONFIG_HID_TOPSEED is not set
> -# CONFIG_THRUSTMASTER_FF is not set
> -# CONFIG_ZEROPLUS_FF is not set
> -CONFIG_USB_SUPPORT=y
> -CONFIG_USB_ARCH_HAS_HCD=y
> -CONFIG_USB_ARCH_HAS_OHCI=y
> -CONFIG_USB_ARCH_HAS_EHCI=y
> -CONFIG_USB=y
> -# CONFIG_USB_DEBUG is not set
> -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
> -
> -#
> -# Miscellaneous USB options
> -#
> -CONFIG_USB_DEVICEFS=y
> -# CONFIG_USB_DEVICE_CLASS is not set
> -# CONFIG_USB_DYNAMIC_MINORS is not set
> -# CONFIG_USB_SUSPEND is not set
> -# CONFIG_USB_OTG is not set
> -# CONFIG_USB_OTG_WHITELIST is not set
> -# CONFIG_USB_OTG_BLACKLIST_HUB is not set
> -CONFIG_USB_MON=y
> -# CONFIG_USB_WUSB is not set
> -# CONFIG_USB_WUSB_CBAF is not set
> -
> -#
> -# USB Host Controller Drivers
> -#
> -# CONFIG_USB_C67X00_HCD is not set
> -# CONFIG_USB_EHCI_HCD is not set
> -# CONFIG_USB_OXU210HP_HCD is not set
> -# CONFIG_USB_ISP116X_HCD is not set
> -# CONFIG_USB_ISP1760_HCD is not set
> -CONFIG_USB_OHCI_HCD=y
> -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
> -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
> -CONFIG_USB_OHCI_LITTLE_ENDIAN=y
> -# CONFIG_USB_UHCI_HCD is not set
> -# CONFIG_USB_SL811_HCD is not set
> -# CONFIG_USB_R8A66597_HCD is not set
> -# CONFIG_USB_WHCI_HCD is not set
> -# CONFIG_USB_HWA_HCD is not set
> -# CONFIG_USB_MUSB_HDRC is not set
> -
> -#
> -# USB Device Class drivers
> -#
> -# CONFIG_USB_ACM is not set
> -# CONFIG_USB_PRINTER is not set
> -# CONFIG_USB_WDM is not set
> -# CONFIG_USB_TMC is not set
> -
> -#
> -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
> -#
> -
> -#
> -# see USB_STORAGE Help for more information
> -#
> -CONFIG_USB_STORAGE=y
> -# CONFIG_USB_STORAGE_DEBUG is not set
> -# CONFIG_USB_STORAGE_DATAFAB is not set
> -# CONFIG_USB_STORAGE_FREECOM is not set
> -# CONFIG_USB_STORAGE_ISD200 is not set
> -# CONFIG_USB_STORAGE_USBAT is not set
> -# CONFIG_USB_STORAGE_SDDR09 is not set
> -# CONFIG_USB_STORAGE_SDDR55 is not set
> -# CONFIG_USB_STORAGE_JUMPSHOT is not set
> -# CONFIG_USB_STORAGE_ALAUDA is not set
> -# CONFIG_USB_STORAGE_ONETOUCH is not set
> -# CONFIG_USB_STORAGE_KARMA is not set
> -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
> -# CONFIG_USB_LIBUSUAL is not set
> -
> -#
> -# USB Imaging devices
> -#
> -# CONFIG_USB_MDC800 is not set
> -# CONFIG_USB_MICROTEK is not set
> -
> -#
> -# USB port drivers
> -#
> -# CONFIG_USB_SERIAL is not set
> -
> -#
> -# USB Miscellaneous drivers
> -#
> -# CONFIG_USB_EMI62 is not set
> -# CONFIG_USB_EMI26 is not set
> -# CONFIG_USB_ADUTUX is not set
> -# CONFIG_USB_SEVSEG is not set
> -# CONFIG_USB_RIO500 is not set
> -# CONFIG_USB_LEGOTOWER is not set
> -# CONFIG_USB_LCD is not set
> -# CONFIG_USB_BERRY_CHARGE is not set
> -# CONFIG_USB_LED is not set
> -# CONFIG_USB_CYPRESS_CY7C63 is not set
> -# CONFIG_USB_CYTHERM is not set
> -# CONFIG_USB_PHIDGET is not set
> -# CONFIG_USB_IDMOUSE is not set
> -# CONFIG_USB_FTDI_ELAN is not set
> -# CONFIG_USB_APPLEDISPLAY is not set
> -# CONFIG_USB_LD is not set
> -# CONFIG_USB_TRANCEVIBRATOR is not set
> -# CONFIG_USB_IOWARRIOR is not set
> -# CONFIG_USB_TEST is not set
> -# CONFIG_USB_ISIGHTFW is not set
> -# CONFIG_USB_VST is not set
> -# CONFIG_USB_GADGET is not set
> -
> -#
> -# OTG and related infrastructure
> -#
> -# CONFIG_USB_GPIO_VBUS is not set
> -# CONFIG_UWB is not set
> -CONFIG_MMC=m
> -# CONFIG_MMC_DEBUG is not set
> -# CONFIG_MMC_UNSAFE_RESUME is not set
> -
> -#
> -# MMC/SD/SDIO Card Drivers
> -#
> -CONFIG_MMC_BLOCK=m
> -CONFIG_MMC_BLOCK_BOUNCE=y
> -# CONFIG_SDIO_UART is not set
> -# CONFIG_MMC_TEST is not set
> -
> -#
> -# MMC/SD/SDIO Host Controller Drivers
> -#
> -CONFIG_MMC_PXA=m
> -# CONFIG_MMC_SDHCI is not set
> -# CONFIG_MMC_TIFM_SD is not set
> -# CONFIG_MMC_SPI is not set
> -# CONFIG_MMC_SDRICOH_CS is not set
> -# CONFIG_MEMSTICK is not set
> -# CONFIG_ACCESSIBILITY is not set
> -CONFIG_NEW_LEDS=y
> -CONFIG_LEDS_CLASS=y
> -
> -#
> -# LED drivers
> -#
> -# CONFIG_LEDS_PCA9532 is not set
> -CONFIG_LEDS_GPIO=m
> -# CONFIG_LEDS_PCA955X is not set
> -
> -#
> -# LED Triggers
> -#
> -CONFIG_LEDS_TRIGGERS=y
> -# CONFIG_LEDS_TRIGGER_TIMER is not set
> -CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> -# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
> -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_HCTOSYS=y
> -CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
> -# CONFIG_RTC_DEBUG is not set
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -# CONFIG_RTC_DRV_TEST is not set
> -
> -#
> -# I2C RTC drivers
> -#
> -# CONFIG_RTC_DRV_DS1307 is not set
> -# CONFIG_RTC_DRV_DS1374 is not set
> -# CONFIG_RTC_DRV_DS1672 is not set
> -# CONFIG_RTC_DRV_MAX6900 is not set
> -# CONFIG_RTC_DRV_RS5C372 is not set
> -# CONFIG_RTC_DRV_ISL1208 is not set
> -# CONFIG_RTC_DRV_X1205 is not set
> -# CONFIG_RTC_DRV_PCF8563 is not set
> -# CONFIG_RTC_DRV_PCF8583 is not set
> -# CONFIG_RTC_DRV_M41T80 is not set
> -# CONFIG_RTC_DRV_S35390A is not set
> -# CONFIG_RTC_DRV_FM3130 is not set
> -# CONFIG_RTC_DRV_RX8581 is not set
> -
> -#
> -# SPI RTC drivers
> -#
> -# CONFIG_RTC_DRV_M41T94 is not set
> -# CONFIG_RTC_DRV_DS1305 is not set
> -# CONFIG_RTC_DRV_DS1390 is not set
> -# CONFIG_RTC_DRV_MAX6902 is not set
> -# CONFIG_RTC_DRV_R9701 is not set
> -# CONFIG_RTC_DRV_RS5C348 is not set
> -# CONFIG_RTC_DRV_DS3234 is not set
> -
> -#
> -# Platform RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_DS1286 is not set
> -# CONFIG_RTC_DRV_DS1511 is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_STK17TA8 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -# CONFIG_RTC_DRV_M48T35 is not set
> -# CONFIG_RTC_DRV_M48T59 is not set
> -# CONFIG_RTC_DRV_BQ4802 is not set
> -CONFIG_RTC_DRV_V3020=y
> -
> -#
> -# on-CPU RTC drivers
> -#
> -CONFIG_RTC_DRV_SA1100=y
> -# CONFIG_RTC_DRV_PXA is not set
> -# CONFIG_DMADEVICES is not set
> -# CONFIG_REGULATOR is not set
> -# CONFIG_UIO is not set
> -# CONFIG_STAGING is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -CONFIG_EXT3_FS=y
> -CONFIG_EXT3_FS_XATTR=y
> -# CONFIG_EXT3_FS_POSIX_ACL is not set
> -# CONFIG_EXT3_FS_SECURITY is not set
> -# CONFIG_EXT4_FS is not set
> -CONFIG_JBD=y
> -CONFIG_FS_MBCACHE=y
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -# CONFIG_FS_POSIX_ACL is not set
> -CONFIG_FILE_LOCKING=y
> -# CONFIG_XFS_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_BTRFS_FS is not set
> -CONFIG_DNOTIFY=y
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=m
> -# CONFIG_MSDOS_FS is not set
> -CONFIG_VFAT_FS=m
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -# CONFIG_PROC_PAGE_MONITOR is not set
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -CONFIG_MISC_FILESYSTEMS=y
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
> -CONFIG_JFFS2_SUMMARY=y
> -# CONFIG_JFFS2_FS_XATTR is not set
> -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
> -CONFIG_JFFS2_ZLIB=y
> -# CONFIG_JFFS2_LZO is not set
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_SQUASHFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_OMFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -CONFIG_NETWORK_FILESYSTEMS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -# CONFIG_NFS_V3_ACL is not set
> -# CONFIG_NFS_V4 is not set
> -CONFIG_ROOT_NFS=y
> -# CONFIG_NFSD is not set
> -CONFIG_LOCKD=y
> -CONFIG_LOCKD_V4=y
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=y
> -# CONFIG_SUNRPC_REGISTER_V4 is not set
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -CONFIG_CIFS=m
> -# CONFIG_CIFS_STATS is not set
> -# CONFIG_CIFS_WEAK_PW_HASH is not set
> -# CONFIG_CIFS_XATTR is not set
> -# CONFIG_CIFS_DEBUG2 is not set
> -# CONFIG_CIFS_EXPERIMENTAL is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -CONFIG_PARTITION_ADVANCED=y
> -# CONFIG_ACORN_PARTITION is not set
> -# CONFIG_OSF_PARTITION is not set
> -# CONFIG_AMIGA_PARTITION is not set
> -# CONFIG_ATARI_PARTITION is not set
> -# CONFIG_MAC_PARTITION is not set
> -CONFIG_MSDOS_PARTITION=y
> -# CONFIG_BSD_DISKLABEL is not set
> -# CONFIG_MINIX_SUBPARTITION is not set
> -# CONFIG_SOLARIS_X86_PARTITION is not set
> -# CONFIG_UNIXWARE_DISKLABEL is not set
> -# CONFIG_LDM_PARTITION is not set
> -# CONFIG_SGI_PARTITION is not set
> -# CONFIG_ULTRIX_PARTITION is not set
> -# CONFIG_SUN_PARTITION is not set
> -# CONFIG_KARMA_PARTITION is not set
> -# CONFIG_EFI_PARTITION is not set
> -# CONFIG_SYSV68_PARTITION is not set
> -CONFIG_NLS=m
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -CONFIG_NLS_CODEPAGE_437=m
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -# CONFIG_NLS_CODEPAGE_850 is not set
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -CONFIG_NLS_ISO8859_1=m
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -# CONFIG_NLS_ISO8859_15 is not set
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -CONFIG_NLS_UTF8=m
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_FRAME_WARN=0
> -# CONFIG_MAGIC_SYSRQ is not set
> -# CONFIG_UNUSED_SYMBOLS is not set
> -# CONFIG_DEBUG_FS is not set
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DEBUG_SHIRQ is not set
> -# CONFIG_DETECT_SOFTLOCKUP is not set
> -# CONFIG_SCHED_DEBUG is not set
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_TIMER_STATS is not set
> -# CONFIG_DEBUG_OBJECTS is not set
> -# CONFIG_DEBUG_RT_MUTEXES is not set
> -# CONFIG_RT_MUTEX_TESTER is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -# CONFIG_DEBUG_MUTEXES is not set
> -# CONFIG_DEBUG_LOCK_ALLOC is not set
> -# CONFIG_PROVE_LOCKING is not set
> -# CONFIG_LOCK_STAT is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -# CONFIG_DEBUG_INFO is not set
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_WRITECOUNT is not set
> -# CONFIG_DEBUG_MEMORY_INIT is not set
> -# CONFIG_DEBUG_LIST is not set
> -# CONFIG_DEBUG_SG is not set
> -# CONFIG_DEBUG_NOTIFIERS is not set
> -CONFIG_FRAME_POINTER=y
> -# CONFIG_BOOT_PRINTK_DELAY is not set
> -# CONFIG_RCU_TORTURE_TEST is not set
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -# CONFIG_BACKTRACE_SELF_TEST is not set
> -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
> -# CONFIG_FAULT_INJECTION is not set
> -# CONFIG_LATENCYTOP is not set
> -CONFIG_SYSCTL_SYSCALL_CHECK=y
> -CONFIG_HAVE_FUNCTION_TRACER=y
> -
> -#
> -# Tracers
> -#
> -# CONFIG_FUNCTION_TRACER is not set
> -# CONFIG_IRQSOFF_TRACER is not set
> -# CONFIG_SCHED_TRACER is not set
> -# CONFIG_CONTEXT_SWITCH_TRACER is not set
> -# CONFIG_BOOT_TRACER is not set
> -# CONFIG_TRACE_BRANCH_PROFILING is not set
> -# CONFIG_STACK_TRACER is not set
> -# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -# CONFIG_KGDB is not set
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> -# CONFIG_DEBUG_STACK_USAGE is not set
> -CONFIG_DEBUG_LL=y
> -# CONFIG_DEBUG_ICEDCC is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITYFS is not set
> -# CONFIG_SECURITY_FILE_CAPABILITIES is not set
> -CONFIG_CRYPTO=y
> -
> -#
> -# Crypto core or helper
> -#
> -# CONFIG_CRYPTO_FIPS is not set
> -# CONFIG_CRYPTO_MANAGER is not set
> -# CONFIG_CRYPTO_MANAGER2 is not set
> -# CONFIG_CRYPTO_GF128MUL is not set
> -# CONFIG_CRYPTO_NULL is not set
> -# CONFIG_CRYPTO_CRYPTD is not set
> -# CONFIG_CRYPTO_AUTHENC is not set
> -# CONFIG_CRYPTO_TEST is not set
> -
> -#
> -# Authenticated Encryption with Associated Data
> -#
> -# CONFIG_CRYPTO_CCM is not set
> -# CONFIG_CRYPTO_GCM is not set
> -# CONFIG_CRYPTO_SEQIV is not set
> -
> -#
> -# Block modes
> -#
> -# CONFIG_CRYPTO_CBC is not set
> -# CONFIG_CRYPTO_CTR is not set
> -# CONFIG_CRYPTO_CTS is not set
> -# CONFIG_CRYPTO_ECB is not set
> -# CONFIG_CRYPTO_LRW is not set
> -# CONFIG_CRYPTO_PCBC is not set
> -# CONFIG_CRYPTO_XTS is not set
> -
> -#
> -# Hash modes
> -#
> -# CONFIG_CRYPTO_HMAC is not set
> -# CONFIG_CRYPTO_XCBC is not set
> -
> -#
> -# Digest
> -#
> -# CONFIG_CRYPTO_CRC32C is not set
> -# CONFIG_CRYPTO_MD4 is not set
> -# CONFIG_CRYPTO_MD5 is not set
> -# CONFIG_CRYPTO_MICHAEL_MIC is not set
> -# CONFIG_CRYPTO_RMD128 is not set
> -# CONFIG_CRYPTO_RMD160 is not set
> -# CONFIG_CRYPTO_RMD256 is not set
> -# CONFIG_CRYPTO_RMD320 is not set
> -# CONFIG_CRYPTO_SHA1 is not set
> -# CONFIG_CRYPTO_SHA256 is not set
> -# CONFIG_CRYPTO_SHA512 is not set
> -# CONFIG_CRYPTO_TGR192 is not set
> -# CONFIG_CRYPTO_WP512 is not set
> -
> -#
> -# Ciphers
> -#
> -# CONFIG_CRYPTO_AES is not set
> -# CONFIG_CRYPTO_ANUBIS is not set
> -# CONFIG_CRYPTO_ARC4 is not set
> -# CONFIG_CRYPTO_BLOWFISH is not set
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -# CONFIG_CRYPTO_CAST5 is not set
> -# CONFIG_CRYPTO_CAST6 is not set
> -# CONFIG_CRYPTO_DES is not set
> -# CONFIG_CRYPTO_FCRYPT is not set
> -# CONFIG_CRYPTO_KHAZAD is not set
> -# CONFIG_CRYPTO_SALSA20 is not set
> -# CONFIG_CRYPTO_SEED is not set
> -# CONFIG_CRYPTO_SERPENT is not set
> -# CONFIG_CRYPTO_TEA is not set
> -# CONFIG_CRYPTO_TWOFISH is not set
> -
> -#
> -# Compression
> -#
> -# CONFIG_CRYPTO_DEFLATE is not set
> -# CONFIG_CRYPTO_LZO is not set
> -
> -#
> -# Random Number Generation
> -#
> -# CONFIG_CRYPTO_ANSI_CPRNG is not set
> -# CONFIG_CRYPTO_HW is not set
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -CONFIG_GENERIC_FIND_LAST_BIT=y
> -CONFIG_CRC_CCITT=m
> -# CONFIG_CRC16 is not set
> -# CONFIG_CRC_T10DIF is not set
> -# CONFIG_CRC_ITU_T is not set
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_PLIST=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> diff --git a/arch/arm/configs/colibri_pxa270_defconfig b/arch/arm/configs/colibri_pxa270_defconfig
> deleted file mode 100644
> index c962870..0000000
> --- a/arch/arm/configs/colibri_pxa270_defconfig
> +++ /dev/null
> @@ -1,1736 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.29-rc8
> -# Fri Mar 13 16:18:17 2009
> -#
> -CONFIG_ARM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_MMU=y
> -# CONFIG_NO_IOPORT is not set
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -# CONFIG_ARCH_HAS_ILOG2_U32 is not set
> -# CONFIG_ARCH_HAS_ILOG2_U64 is not set
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_LOCK_KERNEL=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=""
> -CONFIG_LOCALVERSION_AUTO=y
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -CONFIG_POSIX_MQUEUE=y
> -CONFIG_BSD_PROCESS_ACCT=y
> -CONFIG_BSD_PROCESS_ACCT_V3=y
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -
> -#
> -# RCU Subsystem
> -#
> -CONFIG_CLASSIC_RCU=y
> -# CONFIG_TREE_RCU is not set
> -# CONFIG_PREEMPT_RCU is not set
> -# CONFIG_TREE_RCU_TRACE is not set
> -# CONFIG_PREEMPT_RCU_TRACE is not set
> -CONFIG_IKCONFIG=y
> -CONFIG_IKCONFIG_PROC=y
> -CONFIG_LOG_BUF_SHIFT=14
> -# CONFIG_GROUP_SCHED is not set
> -# CONFIG_CGROUPS is not set
> -CONFIG_SYSFS_DEPRECATED=y
> -CONFIG_SYSFS_DEPRECATED_V2=y
> -# CONFIG_RELAY is not set
> -# CONFIG_NAMESPACES is not set
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_INITRAMFS_SOURCE=""
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -CONFIG_ANON_INODES=y
> -CONFIG_EMBEDDED=y
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -CONFIG_KALLSYMS_EXTRA_PASS=y
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -CONFIG_SHMEM=y
> -CONFIG_AIO=y
> -CONFIG_VM_EVENT_COUNTERS=y
> -CONFIG_COMPAT_BRK=y
> -CONFIG_SLAB=y
> -# CONFIG_SLUB is not set
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -CONFIG_HAVE_OPROFILE=y
> -# CONFIG_KPROBES is not set
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -CONFIG_HAVE_CLK=y
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_SLABINFO=y
> -CONFIG_RT_MUTEXES=y
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_MODULE_FORCE_UNLOAD=y
> -CONFIG_MODVERSIONS=y
> -CONFIG_MODULE_SRCVERSION_ALL=y
> -CONFIG_BLOCK=y
> -CONFIG_LBD=y
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_BLK_DEV_INTEGRITY is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_AS=y
> -CONFIG_IOSCHED_DEADLINE=y
> -CONFIG_IOSCHED_CFQ=y
> -CONFIG_DEFAULT_AS=y
> -# CONFIG_DEFAULT_DEADLINE is not set
> -# CONFIG_DEFAULT_CFQ is not set
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="anticipatory"
> -CONFIG_FREEZER=y
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_S3C64XX is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_MSM is not set
> -# CONFIG_ARCH_W90X900 is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -# CONFIG_ARCH_GUMSTIX is not set
> -# CONFIG_MACH_INTELMOTE2 is not set
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_MACH_MP900C is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_ARCH_VIPER is not set
> -# CONFIG_ARCH_PXA_ESERIES is not set
> -# CONFIG_TRIZEPS_PXA is not set
> -# CONFIG_MACH_H5000 is not set
> -# CONFIG_MACH_EM_X270 is not set
> -CONFIG_MACH_COLIBRI=y
> -# CONFIG_MACH_COLIBRI300 is not set
> -# CONFIG_MACH_ZYLONITE is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_RAUMFELD_PROTO is not set
> -# CONFIG_MACH_TAVOREVB is not set
> -# CONFIG_MACH_SAAR is not set
> -# CONFIG_MACH_ARMCORE is not set
> -# CONFIG_MACH_CM_X300 is not set
> -# CONFIG_MACH_MAGICIAN is not set
> -# CONFIG_MACH_MIOA701 is not set
> -# CONFIG_MACH_PCM027 is not set
> -# CONFIG_ARCH_PXA_PALM is not set
> -# CONFIG_PXA_EZX is not set
> -CONFIG_PXA27x=y
> -# CONFIG_PXA_PWM is not set
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_PABRT_NOIFAR=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -# CONFIG_OUTER_CACHE is not set
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -CONFIG_COMMON_CLKDEV=y
> -
> -#
> -# Bus support
> -#
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -# CONFIG_NO_HZ is not set
> -# CONFIG_HIGH_RES_TIMERS is not set
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -CONFIG_VMSPLIT_3G=y
> -# CONFIG_VMSPLIT_2G is not set
> -# CONFIG_VMSPLIT_1G is not set
> -CONFIG_PAGE_OFFSET=0xC0000000
> -CONFIG_PREEMPT=y
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -CONFIG_ARCH_FLATMEM_HAS_HOLES=y
> -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -CONFIG_PAGEFLAGS_EXTENDED=y
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_PHYS_ADDR_T_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=0
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_UNEVICTABLE_LRU=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0
> -CONFIG_ZBOOT_ROM_BSS=0
> -CONFIG_CMDLINE=""
> -# CONFIG_XIP_KERNEL is not set
> -# CONFIG_KEXEC is not set
> -
> -#
> -# CPU Power Management
> -#
> -# CONFIG_CPU_FREQ is not set
> -# CONFIG_CPU_IDLE is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> -CONFIG_HAVE_AOUT=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -CONFIG_PM=y
> -# CONFIG_PM_DEBUG is not set
> -CONFIG_PM_SLEEP=y
> -CONFIG_SUSPEND=y
> -CONFIG_SUSPEND_FREEZER=y
> -# CONFIG_APM_EMULATION is not set
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_COMPAT_NET_DEV_OPS=y
> -CONFIG_PACKET=y
> -CONFIG_PACKET_MMAP=y
> -CONFIG_UNIX=y
> -CONFIG_XFRM=y
> -CONFIG_XFRM_USER=m
> -# CONFIG_XFRM_SUB_POLICY is not set
> -# CONFIG_XFRM_MIGRATE is not set
> -# CONFIG_XFRM_STATISTICS is not set
> -CONFIG_NET_KEY=y
> -# CONFIG_NET_KEY_MIGRATE is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -CONFIG_IP_PNP_BOOTP=y
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -CONFIG_INET_XFRM_MODE_TRANSPORT=y
> -CONFIG_INET_XFRM_MODE_TUNNEL=y
> -CONFIG_INET_XFRM_MODE_BEET=y
> -# CONFIG_INET_LRO is not set
> -CONFIG_INET_DIAG=y
> -CONFIG_INET_TCP_DIAG=y
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETLABEL is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -CONFIG_NETFILTER=y
> -# CONFIG_NETFILTER_DEBUG is not set
> -CONFIG_NETFILTER_ADVANCED=y
> -
> -#
> -# Core Netfilter Configuration
> -#
> -# CONFIG_NETFILTER_NETLINK_QUEUE is not set
> -# CONFIG_NETFILTER_NETLINK_LOG is not set
> -# CONFIG_NF_CONNTRACK is not set
> -# CONFIG_NETFILTER_XTABLES is not set
> -# CONFIG_IP_VS is not set
> -
> -#
> -# IP: Netfilter Configuration
> -#
> -# CONFIG_NF_DEFRAG_IPV4 is not set
> -CONFIG_IP_NF_QUEUE=m
> -# CONFIG_IP_NF_IPTABLES is not set
> -# CONFIG_IP_NF_ARPTABLES is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_NET_DSA is not set
> -CONFIG_VLAN_8021Q=m
> -# CONFIG_VLAN_8021Q_GVRP is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_NET_SCHED is not set
> -# CONFIG_DCB is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -CONFIG_IRDA=m
> -
> -#
> -# IrDA protocols
> -#
> -CONFIG_IRLAN=m
> -CONFIG_IRCOMM=m
> -CONFIG_IRDA_ULTRA=y
> -
> -#
> -# IrDA options
> -#
> -CONFIG_IRDA_CACHE_LAST_LSAP=y
> -CONFIG_IRDA_FAST_RR=y
> -# CONFIG_IRDA_DEBUG is not set
> -
> -#
> -# Infrared-port device drivers
> -#
> -
> -#
> -# SIR device drivers
> -#
> -CONFIG_IRTTY_SIR=m
> -
> -#
> -# Dongle support
> -#
> -# CONFIG_DONGLE is not set
> -# CONFIG_KINGSUN_DONGLE is not set
> -# CONFIG_KSDAZZLE_DONGLE is not set
> -# CONFIG_KS959_DONGLE is not set
> -
> -#
> -# FIR device drivers
> -#
> -# CONFIG_USB_IRDA is not set
> -# CONFIG_SIGMATEL_FIR is not set
> -# CONFIG_PXA_FICP is not set
> -# CONFIG_MCS_FIR is not set
> -CONFIG_BT=m
> -CONFIG_BT_L2CAP=m
> -CONFIG_BT_SCO=m
> -CONFIG_BT_RFCOMM=m
> -CONFIG_BT_RFCOMM_TTY=y
> -CONFIG_BT_BNEP=m
> -CONFIG_BT_BNEP_MC_FILTER=y
> -CONFIG_BT_BNEP_PROTO_FILTER=y
> -CONFIG_BT_HIDP=m
> -
> -#
> -# Bluetooth device drivers
> -#
> -# CONFIG_BT_HCIBTUSB is not set
> -# CONFIG_BT_HCIBTSDIO is not set
> -# CONFIG_BT_HCIUART is not set
> -# CONFIG_BT_HCIBCM203X is not set
> -# CONFIG_BT_HCIBPA10X is not set
> -# CONFIG_BT_HCIBFUSB is not set
> -# CONFIG_BT_HCIVHCI is not set
> -# CONFIG_AF_RXRPC is not set
> -# CONFIG_PHONET is not set
> -CONFIG_WIRELESS=y
> -CONFIG_CFG80211=y
> -# CONFIG_CFG80211_REG_DEBUG is not set
> -CONFIG_NL80211=y
> -CONFIG_WIRELESS_OLD_REGULATORY=y
> -CONFIG_WIRELESS_EXT=y
> -CONFIG_WIRELESS_EXT_SYSFS=y
> -CONFIG_LIB80211=y
> -CONFIG_LIB80211_CRYPT_WEP=y
> -CONFIG_LIB80211_CRYPT_CCMP=y
> -CONFIG_LIB80211_CRYPT_TKIP=y
> -# CONFIG_MAC80211 is not set
> -# CONFIG_WIMAX is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=y
> -CONFIG_FIRMWARE_IN_KERNEL=y
> -CONFIG_EXTRA_FIRMWARE=""
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_DEBUG_DEVRES is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -CONFIG_CONNECTOR=y
> -CONFIG_PROC_EVENTS=y
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -CONFIG_MTD_CONCAT=y
> -CONFIG_MTD_PARTITIONS=y
> -# CONFIG_MTD_TESTS is not set
> -# CONFIG_MTD_REDBOOT_PARTS is not set
> -# CONFIG_MTD_CMDLINE_PARTS is not set
> -# CONFIG_MTD_AFS_PARTS is not set
> -# CONFIG_MTD_AR7_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_MTD_BLKDEVS=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_JEDECPROBE=y
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -# CONFIG_MTD_CFI_NOSWAP is not set
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -CONFIG_MTD_CFI_LE_BYTE_SWAP=y
> -CONFIG_MTD_CFI_GEOMETRY=y
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -# CONFIG_MTD_OTP is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_CFI_AMDSTD=y
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -CONFIG_MTD_COMPLEX_MAPPINGS=y
> -CONFIG_MTD_PHYSMAP=y
> -# CONFIG_MTD_PHYSMAP_COMPAT is not set
> -CONFIG_MTD_PXA2XX=y
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_IMPA7 is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -CONFIG_MTD_BLOCK2MTD=y
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -CONFIG_MTD_NAND=y
> -# CONFIG_MTD_NAND_VERIFY_WRITE is not set
> -# CONFIG_MTD_NAND_ECC_SMC is not set
> -# CONFIG_MTD_NAND_MUSEUM_IDS is not set
> -# CONFIG_MTD_NAND_H1900 is not set
> -# CONFIG_MTD_NAND_GPIO is not set
> -CONFIG_MTD_NAND_IDS=y
> -CONFIG_MTD_NAND_DISKONCHIP=y
> -CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
> -CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
> -CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
> -CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
> -# CONFIG_MTD_NAND_SHARPSL is not set
> -# CONFIG_MTD_NAND_NANDSIM is not set
> -# CONFIG_MTD_NAND_PLATFORM is not set
> -# CONFIG_MTD_ALAUDA is not set
> -CONFIG_MTD_ONENAND=y
> -# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
> -# CONFIG_MTD_ONENAND_GENERIC is not set
> -# CONFIG_MTD_ONENAND_OTP is not set
> -# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
> -# CONFIG_MTD_ONENAND_SIM is not set
> -
> -#
> -# LPDDR flash memory drivers
> -#
> -# CONFIG_MTD_LPDDR is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -CONFIG_BLK_DEV_LOOP=y
> -CONFIG_BLK_DEV_CRYPTOLOOP=m
> -CONFIG_BLK_DEV_NBD=y
> -# CONFIG_BLK_DEV_UB is not set
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_COUNT=8
> -CONFIG_BLK_DEV_RAM_SIZE=4096
> -# CONFIG_BLK_DEV_XIP is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -CONFIG_MISC_DEVICES=y
> -# CONFIG_ICS932S401 is not set
> -# CONFIG_ENCLOSURE_SERVICES is not set
> -# CONFIG_ISL29003 is not set
> -# CONFIG_C2PORT is not set
> -
> -#
> -# EEPROM support
> -#
> -# CONFIG_EEPROM_AT24 is not set
> -# CONFIG_EEPROM_LEGACY is not set
> -# CONFIG_EEPROM_93CX6 is not set
> -CONFIG_HAVE_IDE=y
> -CONFIG_IDE=y
> -
> -#
> -# Please see Documentation/ide/ide.txt for help/info on IDE drives
> -#
> -# CONFIG_BLK_DEV_IDE_SATA is not set
> -CONFIG_IDE_GD=y
> -CONFIG_IDE_GD_ATA=y
> -# CONFIG_IDE_GD_ATAPI is not set
> -# CONFIG_BLK_DEV_IDECD is not set
> -# CONFIG_BLK_DEV_IDETAPE is not set
> -# CONFIG_IDE_TASK_IOCTL is not set
> -CONFIG_IDE_PROC_FS=y
> -
> -#
> -# IDE chipset support/bugfixes
> -#
> -# CONFIG_BLK_DEV_PLATFORM is not set
> -# CONFIG_BLK_DEV_IDEDMA is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -# CONFIG_SCSI is not set
> -# CONFIG_SCSI_DMA is not set
> -# CONFIG_SCSI_NETLINK is not set
> -# CONFIG_ATA is not set
> -# CONFIG_MD is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_MACVLAN is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -# CONFIG_VETH is not set
> -CONFIG_PHYLIB=y
> -
> -#
> -# MII PHY device drivers
> -#
> -# CONFIG_MARVELL_PHY is not set
> -# CONFIG_DAVICOM_PHY is not set
> -# CONFIG_QSEMI_PHY is not set
> -# CONFIG_LXT_PHY is not set
> -# CONFIG_CICADA_PHY is not set
> -# CONFIG_VITESSE_PHY is not set
> -# CONFIG_SMSC_PHY is not set
> -# CONFIG_BROADCOM_PHY is not set
> -# CONFIG_ICPLUS_PHY is not set
> -# CONFIG_REALTEK_PHY is not set
> -# CONFIG_NATIONAL_PHY is not set
> -# CONFIG_STE10XP is not set
> -# CONFIG_LSI_ET1011C_PHY is not set
> -# CONFIG_FIXED_PHY is not set
> -# CONFIG_MDIO_BITBANG is not set
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=y
> -# CONFIG_AX88796 is not set
> -# CONFIG_SMC91X is not set
> -CONFIG_DM9000=y
> -CONFIG_DM9000_DEBUGLEVEL=4
> -# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
> -# CONFIG_SMC911X is not set
> -# CONFIG_SMSC911X is not set
> -# CONFIG_IBM_NEW_EMAC_ZMII is not set
> -# CONFIG_IBM_NEW_EMAC_RGMII is not set
> -# CONFIG_IBM_NEW_EMAC_TAH is not set
> -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
> -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
> -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
> -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
> -# CONFIG_B44 is not set
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -
> -#
> -# Wireless LAN
> -#
> -# CONFIG_WLAN_PRE80211 is not set
> -CONFIG_WLAN_80211=y
> -# CONFIG_LIBERTAS is not set
> -# CONFIG_USB_ZD1201 is not set
> -# CONFIG_USB_NET_RNDIS_WLAN is not set
> -# CONFIG_IWLWIFI_LEDS is not set
> -CONFIG_HOSTAP=y
> -CONFIG_HOSTAP_FIRMWARE=y
> -CONFIG_HOSTAP_FIRMWARE_NVRAM=y
> -
> -#
> -# Enable WiMAX (Networking options) to see the WiMAX drivers
> -#
> -
> -#
> -# USB Network Adapters
> -#
> -# CONFIG_USB_CATC is not set
> -# CONFIG_USB_KAWETH is not set
> -# CONFIG_USB_PEGASUS is not set
> -# CONFIG_USB_RTL8150 is not set
> -# CONFIG_USB_USBNET is not set
> -# CONFIG_WAN is not set
> -# CONFIG_PPP is not set
> -# CONFIG_SLIP is not set
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -CONFIG_INPUT_MOUSEDEV_PSAUX=y
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
> -# CONFIG_INPUT_JOYDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -CONFIG_KEYBOARD_ATKBD=m
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_KEYBOARD_STOWAWAY is not set
> -# CONFIG_KEYBOARD_PXA27x is not set
> -# CONFIG_KEYBOARD_GPIO is not set
> -CONFIG_INPUT_MOUSE=y
> -# CONFIG_MOUSE_PS2 is not set
> -CONFIG_MOUSE_SERIAL=m
> -# CONFIG_MOUSE_APPLETOUCH is not set
> -# CONFIG_MOUSE_BCM5974 is not set
> -# CONFIG_MOUSE_VSXXXAA is not set
> -# CONFIG_MOUSE_GPIO is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -# CONFIG_TOUCHSCREEN_FUJITSU is not set
> -# CONFIG_TOUCHSCREEN_GUNZE is not set
> -# CONFIG_TOUCHSCREEN_ELO is not set
> -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
> -# CONFIG_TOUCHSCREEN_MTOUCH is not set
> -# CONFIG_TOUCHSCREEN_INEXIO is not set
> -# CONFIG_TOUCHSCREEN_MK712 is not set
> -# CONFIG_TOUCHSCREEN_PENMOUNT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
> -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
> -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
> -# CONFIG_TOUCHSCREEN_TSC2007 is not set
> -CONFIG_INPUT_MISC=y
> -# CONFIG_INPUT_ATI_REMOTE is not set
> -# CONFIG_INPUT_ATI_REMOTE2 is not set
> -# CONFIG_INPUT_KEYSPAN_REMOTE is not set
> -# CONFIG_INPUT_POWERMATE is not set
> -# CONFIG_INPUT_YEALINK is not set
> -# CONFIG_INPUT_CM109 is not set
> -CONFIG_INPUT_UINPUT=m
> -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -CONFIG_SERIO=y
> -CONFIG_SERIO_SERPORT=y
> -CONFIG_SERIO_LIBPS2=y
> -# CONFIG_SERIO_RAW is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_CONSOLE_TRANSLATIONS=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -CONFIG_DEVKMEM=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=256
> -# CONFIG_IPMI_HANDLER is not set
> -CONFIG_HW_RANDOM=y
> -# CONFIG_R3964 is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -CONFIG_I2C=y
> -CONFIG_I2C_BOARDINFO=y
> -CONFIG_I2C_CHARDEV=y
> -CONFIG_I2C_HELPER_AUTO=y
> -
> -#
> -# I2C Hardware Bus support
> -#
> -
> -#
> -# I2C system bus drivers (mostly embedded / system-on-chip)
> -#
> -# CONFIG_I2C_GPIO is not set
> -# CONFIG_I2C_OCORES is not set
> -# CONFIG_I2C_PXA is not set
> -# CONFIG_I2C_SIMTEC is not set
> -
> -#
> -# External I2C/SMBus adapter drivers
> -#
> -# CONFIG_I2C_PARPORT_LIGHT is not set
> -# CONFIG_I2C_TAOS_EVM is not set
> -# CONFIG_I2C_TINY_USB is not set
> -
> -#
> -# Other I2C/SMBus bus drivers
> -#
> -# CONFIG_I2C_PCA_PLATFORM is not set
> -# CONFIG_I2C_STUB is not set
> -
> -#
> -# Miscellaneous I2C Chip support
> -#
> -# CONFIG_DS1682 is not set
> -# CONFIG_SENSORS_PCF8574 is not set
> -# CONFIG_PCF8575 is not set
> -# CONFIG_SENSORS_PCA9539 is not set
> -# CONFIG_SENSORS_PCF8591 is not set
> -# CONFIG_SENSORS_MAX6875 is not set
> -# CONFIG_SENSORS_TSL2550 is not set
> -# CONFIG_I2C_DEBUG_CORE is not set
> -# CONFIG_I2C_DEBUG_ALGO is not set
> -# CONFIG_I2C_DEBUG_BUS is not set
> -# CONFIG_I2C_DEBUG_CHIP is not set
> -# CONFIG_SPI is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -# CONFIG_DEBUG_GPIO is not set
> -# CONFIG_GPIO_SYSFS is not set
> -
> -#
> -# Memory mapped GPIO expanders:
> -#
> -
> -#
> -# I2C GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX732X is not set
> -# CONFIG_GPIO_PCA953X is not set
> -# CONFIG_GPIO_PCF857X is not set
> -
> -#
> -# PCI GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -# CONFIG_W1 is not set
> -# CONFIG_POWER_SUPPLY is not set
> -CONFIG_HWMON=y
> -# CONFIG_HWMON_VID is not set
> -# CONFIG_SENSORS_AD7414 is not set
> -# CONFIG_SENSORS_AD7418 is not set
> -# CONFIG_SENSORS_ADM1021 is not set
> -# CONFIG_SENSORS_ADM1025 is not set
> -# CONFIG_SENSORS_ADM1026 is not set
> -# CONFIG_SENSORS_ADM1029 is not set
> -# CONFIG_SENSORS_ADM1031 is not set
> -# CONFIG_SENSORS_ADM9240 is not set
> -# CONFIG_SENSORS_ADT7462 is not set
> -# CONFIG_SENSORS_ADT7470 is not set
> -# CONFIG_SENSORS_ADT7473 is not set
> -# CONFIG_SENSORS_ADT7475 is not set
> -# CONFIG_SENSORS_ATXP1 is not set
> -# CONFIG_SENSORS_DS1621 is not set
> -# CONFIG_SENSORS_F71805F is not set
> -# CONFIG_SENSORS_F71882FG is not set
> -# CONFIG_SENSORS_F75375S is not set
> -# CONFIG_SENSORS_GL518SM is not set
> -# CONFIG_SENSORS_GL520SM is not set
> -# CONFIG_SENSORS_IT87 is not set
> -# CONFIG_SENSORS_LM63 is not set
> -# CONFIG_SENSORS_LM75 is not set
> -# CONFIG_SENSORS_LM77 is not set
> -# CONFIG_SENSORS_LM78 is not set
> -# CONFIG_SENSORS_LM80 is not set
> -# CONFIG_SENSORS_LM83 is not set
> -# CONFIG_SENSORS_LM85 is not set
> -# CONFIG_SENSORS_LM87 is not set
> -# CONFIG_SENSORS_LM90 is not set
> -# CONFIG_SENSORS_LM92 is not set
> -# CONFIG_SENSORS_LM93 is not set
> -# CONFIG_SENSORS_LTC4245 is not set
> -# CONFIG_SENSORS_MAX1619 is not set
> -# CONFIG_SENSORS_MAX6650 is not set
> -# CONFIG_SENSORS_PC87360 is not set
> -# CONFIG_SENSORS_PC87427 is not set
> -# CONFIG_SENSORS_DME1737 is not set
> -# CONFIG_SENSORS_SMSC47M1 is not set
> -# CONFIG_SENSORS_SMSC47M192 is not set
> -# CONFIG_SENSORS_SMSC47B397 is not set
> -# CONFIG_SENSORS_ADS7828 is not set
> -# CONFIG_SENSORS_THMC50 is not set
> -# CONFIG_SENSORS_VT1211 is not set
> -# CONFIG_SENSORS_W83781D is not set
> -# CONFIG_SENSORS_W83791D is not set
> -# CONFIG_SENSORS_W83792D is not set
> -# CONFIG_SENSORS_W83793 is not set
> -# CONFIG_SENSORS_W83L785TS is not set
> -# CONFIG_SENSORS_W83L786NG is not set
> -# CONFIG_SENSORS_W83627HF is not set
> -# CONFIG_SENSORS_W83627EHF is not set
> -# CONFIG_HWMON_DEBUG_CHIP is not set
> -# CONFIG_THERMAL is not set
> -# CONFIG_THERMAL_HWMON is not set
> -CONFIG_WATCHDOG=y
> -# CONFIG_WATCHDOG_NOWAYOUT is not set
> -
> -#
> -# Watchdog Device Drivers
> -#
> -# CONFIG_SOFT_WATCHDOG is not set
> -# CONFIG_SA1100_WATCHDOG is not set
> -
> -#
> -# USB-based Watchdog Cards
> -#
> -# CONFIG_USBPCWATCHDOG is not set
> -CONFIG_SSB_POSSIBLE=y
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_CORE is not set
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_MFD_ASIC3 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -# CONFIG_TPS65010 is not set
> -# CONFIG_TWL4030_CORE is not set
> -# CONFIG_MFD_TMIO is not set
> -# CONFIG_MFD_T7L66XB is not set
> -# CONFIG_MFD_TC6387XB is not set
> -# CONFIG_MFD_TC6393XB is not set
> -# CONFIG_PMIC_DA903X is not set
> -# CONFIG_MFD_WM8400 is not set
> -# CONFIG_MFD_WM8350_I2C is not set
> -# CONFIG_MFD_PCF50633 is not set
> -
> -#
> -# Multimedia devices
> -#
> -
> -#
> -# Multimedia core support
> -#
> -# CONFIG_VIDEO_DEV is not set
> -# CONFIG_DVB_CORE is not set
> -# CONFIG_VIDEO_MEDIA is not set
> -
> -#
> -# Multimedia drivers
> -#
> -CONFIG_DAB=y
> -# CONFIG_USB_DABUSB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -CONFIG_FB=y
> -CONFIG_FIRMWARE_EDID=y
> -# CONFIG_FB_DDC is not set
> -# CONFIG_FB_BOOT_VESA_SUPPORT is not set
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> -# CONFIG_FB_SYS_FILLRECT is not set
> -# CONFIG_FB_SYS_COPYAREA is not set
> -# CONFIG_FB_SYS_IMAGEBLIT is not set
> -# CONFIG_FB_FOREIGN_ENDIAN is not set
> -# CONFIG_FB_SYS_FOPS is not set
> -# CONFIG_FB_SVGALIB is not set
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -
> -#
> -# Frame buffer hardware drivers
> -#
> -# CONFIG_FB_UVESA is not set
> -# CONFIG_FB_S1D13XXX is not set
> -CONFIG_FB_PXA=y
> -# CONFIG_FB_PXA_OVERLAY is not set
> -# CONFIG_FB_PXA_SMARTPANEL is not set
> -# CONFIG_FB_PXA_PARAMETERS is not set
> -# CONFIG_FB_MBX is not set
> -# CONFIG_FB_W100 is not set
> -# CONFIG_FB_VIRTUAL is not set
> -# CONFIG_FB_METRONOME is not set
> -# CONFIG_FB_MB862XX is not set
> -CONFIG_BACKLIGHT_LCD_SUPPORT=y
> -CONFIG_LCD_CLASS_DEVICE=y
> -# CONFIG_LCD_ILI9320 is not set
> -# CONFIG_LCD_PLATFORM is not set
> -CONFIG_BACKLIGHT_CLASS_DEVICE=y
> -CONFIG_BACKLIGHT_GENERIC=y
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
> -CONFIG_FONTS=y
> -CONFIG_FONT_8x8=y
> -CONFIG_FONT_8x16=y
> -# CONFIG_FONT_6x11 is not set
> -# CONFIG_FONT_7x14 is not set
> -# CONFIG_FONT_PEARL_8x8 is not set
> -# CONFIG_FONT_ACORN_8x8 is not set
> -# CONFIG_FONT_MINI_4x6 is not set
> -# CONFIG_FONT_SUN8x16 is not set
> -# CONFIG_FONT_SUN12x22 is not set
> -# CONFIG_FONT_10x18 is not set
> -CONFIG_LOGO=y
> -CONFIG_LOGO_LINUX_MONO=y
> -CONFIG_LOGO_LINUX_VGA16=y
> -CONFIG_LOGO_LINUX_CLUT224=y
> -# CONFIG_SOUND is not set
> -CONFIG_HID_SUPPORT=y
> -CONFIG_HID=y
> -# CONFIG_HID_DEBUG is not set
> -# CONFIG_HIDRAW is not set
> -
> -#
> -# USB Input Devices
> -#
> -# CONFIG_USB_HID is not set
> -# CONFIG_HID_PID is not set
> -
> -#
> -# USB HID Boot Protocol drivers
> -#
> -# CONFIG_USB_KBD is not set
> -# CONFIG_USB_MOUSE is not set
> -
> -#
> -# Special HID drivers
> -#
> -CONFIG_HID_COMPAT=y
> -# CONFIG_HID_APPLE is not set
> -CONFIG_USB_SUPPORT=y
> -CONFIG_USB_ARCH_HAS_HCD=y
> -CONFIG_USB_ARCH_HAS_OHCI=y
> -# CONFIG_USB_ARCH_HAS_EHCI is not set
> -CONFIG_USB=y
> -# CONFIG_USB_DEBUG is not set
> -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
> -
> -#
> -# Miscellaneous USB options
> -#
> -CONFIG_USB_DEVICEFS=y
> -# CONFIG_USB_DEVICE_CLASS is not set
> -# CONFIG_USB_DYNAMIC_MINORS is not set
> -# CONFIG_USB_SUSPEND is not set
> -# CONFIG_USB_OTG is not set
> -# CONFIG_USB_OTG_WHITELIST is not set
> -# CONFIG_USB_OTG_BLACKLIST_HUB is not set
> -# CONFIG_USB_MON is not set
> -# CONFIG_USB_WUSB is not set
> -# CONFIG_USB_WUSB_CBAF is not set
> -
> -#
> -# USB Host Controller Drivers
> -#
> -# CONFIG_USB_C67X00_HCD is not set
> -# CONFIG_USB_OXU210HP_HCD is not set
> -# CONFIG_USB_ISP116X_HCD is not set
> -# CONFIG_USB_OHCI_HCD is not set
> -# CONFIG_USB_SL811_HCD is not set
> -# CONFIG_USB_R8A66597_HCD is not set
> -# CONFIG_USB_HWA_HCD is not set
> -# CONFIG_USB_MUSB_HDRC is not set
> -# CONFIG_USB_GADGET_MUSB_HDRC is not set
> -
> -#
> -# USB Device Class drivers
> -#
> -# CONFIG_USB_ACM is not set
> -# CONFIG_USB_PRINTER is not set
> -# CONFIG_USB_WDM is not set
> -# CONFIG_USB_TMC is not set
> -
> -#
> -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
> -#
> -
> -#
> -# see USB_STORAGE Help for more information
> -#
> -# CONFIG_USB_LIBUSUAL is not set
> -
> -#
> -# USB Imaging devices
> -#
> -# CONFIG_USB_MDC800 is not set
> -
> -#
> -# USB port drivers
> -#
> -CONFIG_USB_SERIAL=m
> -# CONFIG_USB_EZUSB is not set
> -# CONFIG_USB_SERIAL_GENERIC is not set
> -# CONFIG_USB_SERIAL_AIRCABLE is not set
> -# CONFIG_USB_SERIAL_ARK3116 is not set
> -# CONFIG_USB_SERIAL_BELKIN is not set
> -# CONFIG_USB_SERIAL_CH341 is not set
> -# CONFIG_USB_SERIAL_WHITEHEAT is not set
> -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
> -# CONFIG_USB_SERIAL_CP2101 is not set
> -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
> -# CONFIG_USB_SERIAL_EMPEG is not set
> -# CONFIG_USB_SERIAL_FTDI_SIO is not set
> -# CONFIG_USB_SERIAL_FUNSOFT is not set
> -# CONFIG_USB_SERIAL_VISOR is not set
> -# CONFIG_USB_SERIAL_IPAQ is not set
> -# CONFIG_USB_SERIAL_IR is not set
> -# CONFIG_USB_SERIAL_EDGEPORT is not set
> -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
> -# CONFIG_USB_SERIAL_GARMIN is not set
> -# CONFIG_USB_SERIAL_IPW is not set
> -# CONFIG_USB_SERIAL_IUU is not set
> -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
> -# CONFIG_USB_SERIAL_KEYSPAN is not set
> -# CONFIG_USB_SERIAL_KLSI is not set
> -# CONFIG_USB_SERIAL_KOBIL_SCT is not set
> -# CONFIG_USB_SERIAL_MCT_U232 is not set
> -# CONFIG_USB_SERIAL_MOS7720 is not set
> -# CONFIG_USB_SERIAL_MOS7840 is not set
> -# CONFIG_USB_SERIAL_MOTOROLA is not set
> -# CONFIG_USB_SERIAL_NAVMAN is not set
> -# CONFIG_USB_SERIAL_PL2303 is not set
> -# CONFIG_USB_SERIAL_OTI6858 is not set
> -# CONFIG_USB_SERIAL_SPCP8X5 is not set
> -# CONFIG_USB_SERIAL_HP4X is not set
> -# CONFIG_USB_SERIAL_SAFE is not set
> -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
> -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
> -# CONFIG_USB_SERIAL_TI is not set
> -# CONFIG_USB_SERIAL_CYBERJACK is not set
> -# CONFIG_USB_SERIAL_XIRCOM is not set
> -# CONFIG_USB_SERIAL_OPTION is not set
> -# CONFIG_USB_SERIAL_OMNINET is not set
> -# CONFIG_USB_SERIAL_OPTICON is not set
> -# CONFIG_USB_SERIAL_DEBUG is not set
> -
> -#
> -# USB Miscellaneous drivers
> -#
> -# CONFIG_USB_EMI62 is not set
> -# CONFIG_USB_EMI26 is not set
> -# CONFIG_USB_ADUTUX is not set
> -# CONFIG_USB_SEVSEG is not set
> -# CONFIG_USB_RIO500 is not set
> -# CONFIG_USB_LEGOTOWER is not set
> -# CONFIG_USB_LCD is not set
> -# CONFIG_USB_BERRY_CHARGE is not set
> -# CONFIG_USB_LED is not set
> -# CONFIG_USB_CYPRESS_CY7C63 is not set
> -# CONFIG_USB_CYTHERM is not set
> -# CONFIG_USB_PHIDGET is not set
> -# CONFIG_USB_IDMOUSE is not set
> -# CONFIG_USB_FTDI_ELAN is not set
> -# CONFIG_USB_APPLEDISPLAY is not set
> -# CONFIG_USB_LD is not set
> -# CONFIG_USB_TRANCEVIBRATOR is not set
> -# CONFIG_USB_IOWARRIOR is not set
> -# CONFIG_USB_TEST is not set
> -# CONFIG_USB_ISIGHTFW is not set
> -# CONFIG_USB_VST is not set
> -CONFIG_USB_GADGET=m
> -# CONFIG_USB_GADGET_DEBUG is not set
> -# CONFIG_USB_GADGET_DEBUG_FILES is not set
> -# CONFIG_USB_GADGET_DEBUG_FS is not set
> -CONFIG_USB_GADGET_VBUS_DRAW=2
> -CONFIG_USB_GADGET_SELECTED=y
> -# CONFIG_USB_GADGET_AT91 is not set
> -# CONFIG_USB_GADGET_ATMEL_USBA is not set
> -# CONFIG_USB_GADGET_FSL_USB2 is not set
> -# CONFIG_USB_GADGET_LH7A40X is not set
> -# CONFIG_USB_GADGET_OMAP is not set
> -# CONFIG_USB_GADGET_PXA25X is not set
> -# CONFIG_USB_GADGET_PXA27X is not set
> -# CONFIG_USB_GADGET_S3C2410 is not set
> -# CONFIG_USB_GADGET_IMX is not set
> -# CONFIG_USB_GADGET_M66592 is not set
> -# CONFIG_USB_GADGET_AMD5536UDC is not set
> -# CONFIG_USB_GADGET_FSL_QE is not set
> -# CONFIG_USB_GADGET_CI13XXX is not set
> -# CONFIG_USB_GADGET_NET2280 is not set
> -# CONFIG_USB_GADGET_GOKU is not set
> -CONFIG_USB_GADGET_DUMMY_HCD=y
> -CONFIG_USB_DUMMY_HCD=m
> -CONFIG_USB_GADGET_DUALSPEED=y
> -# CONFIG_USB_ZERO is not set
> -# CONFIG_USB_ETH is not set
> -# CONFIG_USB_GADGETFS is not set
> -# CONFIG_USB_FILE_STORAGE is not set
> -# CONFIG_USB_G_SERIAL is not set
> -# CONFIG_USB_MIDI_GADGET is not set
> -# CONFIG_USB_G_PRINTER is not set
> -# CONFIG_USB_CDC_COMPOSITE is not set
> -
> -#
> -# OTG and related infrastructure
> -#
> -# CONFIG_USB_GPIO_VBUS is not set
> -CONFIG_MMC=y
> -# CONFIG_MMC_DEBUG is not set
> -# CONFIG_MMC_UNSAFE_RESUME is not set
> -
> -#
> -# MMC/SD/SDIO Card Drivers
> -#
> -CONFIG_MMC_BLOCK=y
> -CONFIG_MMC_BLOCK_BOUNCE=y
> -# CONFIG_SDIO_UART is not set
> -# CONFIG_MMC_TEST is not set
> -
> -#
> -# MMC/SD/SDIO Host Controller Drivers
> -#
> -# CONFIG_MMC_PXA is not set
> -# CONFIG_MMC_SDHCI is not set
> -# CONFIG_MEMSTICK is not set
> -# CONFIG_ACCESSIBILITY is not set
> -CONFIG_NEW_LEDS=y
> -# CONFIG_LEDS_CLASS is not set
> -
> -#
> -# LED drivers
> -#
> -
> -#
> -# LED Triggers
> -#
> -CONFIG_LEDS_TRIGGERS=y
> -CONFIG_LEDS_TRIGGER_TIMER=y
> -# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
> -CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> -# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
> -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=y
> -# CONFIG_RTC_HCTOSYS is not set
> -# CONFIG_RTC_DEBUG is not set
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -# CONFIG_RTC_DRV_TEST is not set
> -
> -#
> -# I2C RTC drivers
> -#
> -# CONFIG_RTC_DRV_DS1307 is not set
> -# CONFIG_RTC_DRV_DS1374 is not set
> -# CONFIG_RTC_DRV_DS1672 is not set
> -# CONFIG_RTC_DRV_MAX6900 is not set
> -# CONFIG_RTC_DRV_RS5C372 is not set
> -# CONFIG_RTC_DRV_ISL1208 is not set
> -# CONFIG_RTC_DRV_X1205 is not set
> -# CONFIG_RTC_DRV_PCF8563 is not set
> -CONFIG_RTC_DRV_PCF8583=m
> -# CONFIG_RTC_DRV_M41T80 is not set
> -# CONFIG_RTC_DRV_S35390A is not set
> -# CONFIG_RTC_DRV_FM3130 is not set
> -# CONFIG_RTC_DRV_RX8581 is not set
> -
> -#
> -# SPI RTC drivers
> -#
> -
> -#
> -# Platform RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_DS1286 is not set
> -# CONFIG_RTC_DRV_DS1511 is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_STK17TA8 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -# CONFIG_RTC_DRV_M48T35 is not set
> -# CONFIG_RTC_DRV_M48T59 is not set
> -# CONFIG_RTC_DRV_BQ4802 is not set
> -# CONFIG_RTC_DRV_V3020 is not set
> -
> -#
> -# on-CPU RTC drivers
> -#
> -# CONFIG_RTC_DRV_SA1100 is not set
> -# CONFIG_RTC_DRV_PXA is not set
> -# CONFIG_DMADEVICES is not set
> -# CONFIG_REGULATOR is not set
> -# CONFIG_UIO is not set
> -# CONFIG_STAGING is not set
> -
> -#
> -# File systems
> -#
> -# CONFIG_EXT2_FS is not set
> -# CONFIG_EXT3_FS is not set
> -# CONFIG_EXT4_FS is not set
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -CONFIG_FS_POSIX_ACL=y
> -CONFIG_FILE_LOCKING=y
> -# CONFIG_XFS_FS is not set
> -# CONFIG_GFS2_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_BTRFS_FS is not set
> -CONFIG_DNOTIFY=y
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -# CONFIG_AUTOFS_FS is not set
> -CONFIG_AUTOFS4_FS=y
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=m
> -CONFIG_MSDOS_FS=m
> -CONFIG_VFAT_FS=m
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_PROC_PAGE_MONITOR=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -CONFIG_CONFIGFS_FS=y
> -CONFIG_MISC_FILESYSTEMS=y
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_ECRYPT_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=1
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -CONFIG_JFFS2_FS_WBUF_VERIFY=y
> -# CONFIG_JFFS2_SUMMARY is not set
> -# CONFIG_JFFS2_FS_XATTR is not set
> -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
> -CONFIG_JFFS2_ZLIB=y
> -# CONFIG_JFFS2_LZO is not set
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_SQUASHFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_OMFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -CONFIG_NETWORK_FILESYSTEMS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -# CONFIG_NFS_V3_ACL is not set
> -CONFIG_NFS_V4=y
> -CONFIG_ROOT_NFS=y
> -CONFIG_NFSD=y
> -CONFIG_NFSD_V3=y
> -# CONFIG_NFSD_V3_ACL is not set
> -CONFIG_NFSD_V4=y
> -CONFIG_LOCKD=y
> -CONFIG_LOCKD_V4=y
> -CONFIG_EXPORTFS=y
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=y
> -CONFIG_SUNRPC_GSS=y
> -# CONFIG_SUNRPC_REGISTER_V4 is not set
> -CONFIG_RPCSEC_GSS_KRB5=y
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -# CONFIG_CIFS is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -# CONFIG_PARTITION_ADVANCED is not set
> -CONFIG_MSDOS_PARTITION=y
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="iso8859-15"
> -CONFIG_NLS_CODEPAGE_437=y
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -CONFIG_NLS_CODEPAGE_850=y
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -CONFIG_NLS_ASCII=y
> -CONFIG_NLS_ISO8859_1=m
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -CONFIG_NLS_ISO8859_15=m
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -CONFIG_NLS_UTF8=m
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -CONFIG_PRINTK_TIME=y
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_FRAME_WARN=1024
> -CONFIG_MAGIC_SYSRQ=y
> -# CONFIG_UNUSED_SYMBOLS is not set
> -CONFIG_DEBUG_FS=y
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DEBUG_SHIRQ is not set
> -CONFIG_DETECT_SOFTLOCKUP=y
> -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
> -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
> -CONFIG_SCHED_DEBUG=y
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_TIMER_STATS is not set
> -# CONFIG_DEBUG_OBJECTS is not set
> -# CONFIG_DEBUG_SLAB is not set
> -CONFIG_DEBUG_PREEMPT=y
> -# CONFIG_DEBUG_RT_MUTEXES is not set
> -# CONFIG_RT_MUTEX_TESTER is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -# CONFIG_DEBUG_MUTEXES is not set
> -# CONFIG_DEBUG_LOCK_ALLOC is not set
> -# CONFIG_PROVE_LOCKING is not set
> -# CONFIG_LOCK_STAT is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -CONFIG_DEBUG_BUGVERBOSE=y
> -CONFIG_DEBUG_INFO=y
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_WRITECOUNT is not set
> -# CONFIG_DEBUG_MEMORY_INIT is not set
> -# CONFIG_DEBUG_LIST is not set
> -# CONFIG_DEBUG_SG is not set
> -# CONFIG_DEBUG_NOTIFIERS is not set
> -CONFIG_FRAME_POINTER=y
> -# CONFIG_BOOT_PRINTK_DELAY is not set
> -# CONFIG_RCU_TORTURE_TEST is not set
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -# CONFIG_BACKTRACE_SELF_TEST is not set
> -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
> -# CONFIG_FAULT_INJECTION is not set
> -# CONFIG_LATENCYTOP is not set
> -# CONFIG_SYSCTL_SYSCALL_CHECK is not set
> -CONFIG_HAVE_FUNCTION_TRACER=y
> -
> -#
> -# Tracers
> -#
> -# CONFIG_FUNCTION_TRACER is not set
> -# CONFIG_IRQSOFF_TRACER is not set
> -# CONFIG_PREEMPT_TRACER is not set
> -# CONFIG_SCHED_TRACER is not set
> -# CONFIG_CONTEXT_SWITCH_TRACER is not set
> -# CONFIG_BOOT_TRACER is not set
> -# CONFIG_TRACE_BRANCH_PROFILING is not set
> -# CONFIG_STACK_TRACER is not set
> -# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -# CONFIG_KGDB is not set
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> -# CONFIG_DEBUG_STACK_USAGE is not set
> -CONFIG_DEBUG_LL=y
> -# CONFIG_DEBUG_ICEDCC is not set
> -
> -#
> -# Security options
> -#
> -CONFIG_KEYS=y
> -CONFIG_KEYS_DEBUG_PROC_KEYS=y
> -CONFIG_SECURITY=y
> -# CONFIG_SECURITYFS is not set
> -# CONFIG_SECURITY_NETWORK is not set
> -# CONFIG_SECURITY_PATH is not set
> -# CONFIG_SECURITY_FILE_CAPABILITIES is not set
> -# CONFIG_SECURITY_ROOTPLUG is not set
> -CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
> -CONFIG_CRYPTO=y
> -
> -#
> -# Crypto core or helper
> -#
> -# CONFIG_CRYPTO_FIPS is not set
> -CONFIG_CRYPTO_ALGAPI=y
> -CONFIG_CRYPTO_ALGAPI2=y
> -CONFIG_CRYPTO_AEAD2=y
> -CONFIG_CRYPTO_BLKCIPHER=y
> -CONFIG_CRYPTO_BLKCIPHER2=y
> -CONFIG_CRYPTO_HASH=y
> -CONFIG_CRYPTO_HASH2=y
> -CONFIG_CRYPTO_RNG2=y
> -CONFIG_CRYPTO_MANAGER=y
> -CONFIG_CRYPTO_MANAGER2=y
> -# CONFIG_CRYPTO_GF128MUL is not set
> -# CONFIG_CRYPTO_NULL is not set
> -# CONFIG_CRYPTO_CRYPTD is not set
> -# CONFIG_CRYPTO_AUTHENC is not set
> -# CONFIG_CRYPTO_TEST is not set
> -
> -#
> -# Authenticated Encryption with Associated Data
> -#
> -# CONFIG_CRYPTO_CCM is not set
> -# CONFIG_CRYPTO_GCM is not set
> -# CONFIG_CRYPTO_SEQIV is not set
> -
> -#
> -# Block modes
> -#
> -CONFIG_CRYPTO_CBC=y
> -# CONFIG_CRYPTO_CTR is not set
> -# CONFIG_CRYPTO_CTS is not set
> -CONFIG_CRYPTO_ECB=y
> -# CONFIG_CRYPTO_LRW is not set
> -CONFIG_CRYPTO_PCBC=m
> -# CONFIG_CRYPTO_XTS is not set
> -
> -#
> -# Hash modes
> -#
> -# CONFIG_CRYPTO_HMAC is not set
> -# CONFIG_CRYPTO_XCBC is not set
> -
> -#
> -# Digest
> -#
> -CONFIG_CRYPTO_CRC32C=y
> -# CONFIG_CRYPTO_MD4 is not set
> -CONFIG_CRYPTO_MD5=y
> -CONFIG_CRYPTO_MICHAEL_MIC=y
> -# CONFIG_CRYPTO_RMD128 is not set
> -# CONFIG_CRYPTO_RMD160 is not set
> -# CONFIG_CRYPTO_RMD256 is not set
> -# CONFIG_CRYPTO_RMD320 is not set
> -CONFIG_CRYPTO_SHA1=m
> -CONFIG_CRYPTO_SHA256=m
> -CONFIG_CRYPTO_SHA512=m
> -# CONFIG_CRYPTO_TGR192 is not set
> -# CONFIG_CRYPTO_WP512 is not set
> -
> -#
> -# Ciphers
> -#
> -CONFIG_CRYPTO_AES=y
> -# CONFIG_CRYPTO_ANUBIS is not set
> -CONFIG_CRYPTO_ARC4=y
> -# CONFIG_CRYPTO_BLOWFISH is not set
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -# CONFIG_CRYPTO_CAST5 is not set
> -# CONFIG_CRYPTO_CAST6 is not set
> -CONFIG_CRYPTO_DES=y
> -# CONFIG_CRYPTO_FCRYPT is not set
> -# CONFIG_CRYPTO_KHAZAD is not set
> -# CONFIG_CRYPTO_SALSA20 is not set
> -# CONFIG_CRYPTO_SEED is not set
> -# CONFIG_CRYPTO_SERPENT is not set
> -# CONFIG_CRYPTO_TEA is not set
> -# CONFIG_CRYPTO_TWOFISH is not set
> -
> -#
> -# Compression
> -#
> -CONFIG_CRYPTO_DEFLATE=m
> -# CONFIG_CRYPTO_LZO is not set
> -
> -#
> -# Random Number Generation
> -#
> -# CONFIG_CRYPTO_ANSI_CPRNG is not set
> -CONFIG_CRYPTO_HW=y
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -CONFIG_GENERIC_FIND_LAST_BIT=y
> -CONFIG_CRC_CCITT=y
> -CONFIG_CRC16=y
> -# CONFIG_CRC_T10DIF is not set
> -# CONFIG_CRC_ITU_T is not set
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -CONFIG_LIBCRC32C=y
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_REED_SOLOMON=y
> -CONFIG_REED_SOLOMON_DEC16=y
> -CONFIG_PLIST=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig
> deleted file mode 100644
> index 2bee932..0000000
> --- a/arch/arm/configs/em_x270_defconfig
> +++ /dev/null
> @@ -1,1740 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.29-rc2
> -# Sun Feb ?1 16:43:31 2009
> -#
> -CONFIG_ARM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_MMU=y
> -# CONFIG_NO_IOPORT is not set
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -# CONFIG_ARCH_HAS_ILOG2_U32 is not set
> -# CONFIG_ARCH_HAS_ILOG2_U64 is not set
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=""
> -# CONFIG_LOCALVERSION_AUTO is not set
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -CONFIG_IKCONFIG=y
> -CONFIG_IKCONFIG_PROC=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_GROUP_SCHED=y
> -CONFIG_FAIR_GROUP_SCHED=y
> -# CONFIG_RT_GROUP_SCHED is not set
> -CONFIG_USER_SCHED=y
> -# CONFIG_CGROUP_SCHED is not set
> -# CONFIG_CGROUPS is not set
> -CONFIG_SYSFS_DEPRECATED=y
> -CONFIG_SYSFS_DEPRECATED_V2=y
> -# CONFIG_RELAY is not set
> -# CONFIG_NAMESPACES is not set
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_INITRAMFS_SOURCE=""
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -CONFIG_EMBEDDED=y
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -# CONFIG_COMPAT_BRK is not set
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_ANON_INODES=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -CONFIG_SHMEM=y
> -CONFIG_AIO=y
> -# CONFIG_VM_EVENT_COUNTERS is not set
> -# CONFIG_SLUB_DEBUG is not set
> -# CONFIG_SLAB is not set
> -CONFIG_SLUB=y
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -CONFIG_HAVE_OPROFILE=y
> -# CONFIG_KPROBES is not set
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -CONFIG_HAVE_CLK=y
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_RT_MUTEXES=y
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -# CONFIG_MODULE_FORCE_UNLOAD is not set
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -CONFIG_BLOCK=y
> -# CONFIG_LBD is not set
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_BLK_DEV_INTEGRITY is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_AS=y
> -CONFIG_IOSCHED_DEADLINE=y
> -CONFIG_IOSCHED_CFQ=y
> -# CONFIG_DEFAULT_AS is not set
> -# CONFIG_DEFAULT_DEADLINE is not set
> -CONFIG_DEFAULT_CFQ=y
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="cfq"
> -CONFIG_CLASSIC_RCU=y
> -# CONFIG_TREE_RCU is not set
> -# CONFIG_PREEMPT_RCU is not set
> -# CONFIG_TREE_RCU_TRACE is not set
> -# CONFIG_PREEMPT_RCU_TRACE is not set
> -CONFIG_FREEZER=y
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_S3C64XX is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_MSM is not set
> -# CONFIG_ARCH_W90X900 is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -# CONFIG_ARCH_GUMSTIX is not set
> -# CONFIG_MACH_INTELMOTE2 is not set
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_MACH_MP900C is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_ARCH_VIPER is not set
> -# CONFIG_ARCH_PXA_ESERIES is not set
> -# CONFIG_TRIZEPS_PXA is not set
> -# CONFIG_MACH_H5000 is not set
> -CONFIG_MACH_EM_X270=y
> -CONFIG_MACH_EXEDA=y
> -# CONFIG_MACH_COLIBRI is not set
> -# CONFIG_MACH_ZYLONITE is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_TAVOREVB is not set
> -# CONFIG_MACH_SAAR is not set
> -# CONFIG_MACH_ARMCORE is not set
> -# CONFIG_MACH_CM_X300 is not set
> -# CONFIG_MACH_MAGICIAN is not set
> -# CONFIG_MACH_MIOA701 is not set
> -# CONFIG_MACH_PCM027 is not set
> -# CONFIG_ARCH_PXA_PALM is not set
> -# CONFIG_PXA_EZX is not set
> -CONFIG_PXA27x=y
> -CONFIG_PXA_SSP=y
> -# CONFIG_PXA_PWM is not set
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_PABRT_NOIFAR=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -# CONFIG_OUTER_CACHE is not set
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -CONFIG_COMMON_CLKDEV=y
> -
> -#
> -# Bus support
> -#
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -CONFIG_NO_HZ=y
> -# CONFIG_HIGH_RES_TIMERS is not set
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -CONFIG_VMSPLIT_3G=y
> -# CONFIG_VMSPLIT_2G is not set
> -# CONFIG_VMSPLIT_1G is not set
> -CONFIG_PAGE_OFFSET=0xC0000000
> -# CONFIG_PREEMPT is not set
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -CONFIG_ARCH_FLATMEM_HAS_HOLES=y
> -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -CONFIG_PAGEFLAGS_EXTENDED=y
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_PHYS_ADDR_T_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=0
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_UNEVICTABLE_LRU=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="root=1f03 mem=32M"
> -# CONFIG_XIP_KERNEL is not set
> -# CONFIG_KEXEC is not set
> -
> -#
> -# CPU Power Management
> -#
> -CONFIG_CPU_FREQ=y
> -CONFIG_CPU_FREQ_TABLE=y
> -# CONFIG_CPU_FREQ_DEBUG is not set
> -CONFIG_CPU_FREQ_STAT=y
> -# CONFIG_CPU_FREQ_STAT_DETAILS is not set
> -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
> -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
> -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
> -CONFIG_CPU_FREQ_GOV_USERSPACE=m
> -# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
> -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
> -# CONFIG_CPU_IDLE is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> -CONFIG_HAVE_AOUT=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -CONFIG_PM=y
> -# CONFIG_PM_DEBUG is not set
> -CONFIG_PM_SLEEP=y
> -CONFIG_SUSPEND=y
> -CONFIG_SUSPEND_FREEZER=y
> -CONFIG_APM_EMULATION=y
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_COMPAT_NET_DEV_OPS=y
> -CONFIG_PACKET=y
> -CONFIG_PACKET_MMAP=y
> -CONFIG_UNIX=y
> -CONFIG_XFRM=y
> -# CONFIG_XFRM_USER is not set
> -# CONFIG_XFRM_SUB_POLICY is not set
> -# CONFIG_XFRM_MIGRATE is not set
> -# CONFIG_XFRM_STATISTICS is not set
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -CONFIG_IP_MULTICAST=y
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -CONFIG_IP_PNP_BOOTP=y
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_IP_MROUTE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -CONFIG_INET_XFRM_MODE_TRANSPORT=y
> -CONFIG_INET_XFRM_MODE_TUNNEL=y
> -CONFIG_INET_XFRM_MODE_BEET=y
> -# CONFIG_INET_LRO is not set
> -# CONFIG_INET_DIAG is not set
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -# CONFIG_NETFILTER is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_NET_DSA is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_NET_SCHED is not set
> -# CONFIG_DCB is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -# CONFIG_IRDA is not set
> -CONFIG_BT=m
> -CONFIG_BT_L2CAP=m
> -CONFIG_BT_SCO=m
> -CONFIG_BT_RFCOMM=m
> -# CONFIG_BT_RFCOMM_TTY is not set
> -CONFIG_BT_BNEP=m
> -# CONFIG_BT_BNEP_MC_FILTER is not set
> -# CONFIG_BT_BNEP_PROTO_FILTER is not set
> -CONFIG_BT_HIDP=m
> -
> -#
> -# Bluetooth device drivers
> -#
> -CONFIG_BT_HCIBTUSB=m
> -# CONFIG_BT_HCIBTSDIO is not set
> -# CONFIG_BT_HCIUART is not set
> -# CONFIG_BT_HCIBCM203X is not set
> -# CONFIG_BT_HCIBPA10X is not set
> -# CONFIG_BT_HCIBFUSB is not set
> -# CONFIG_BT_HCIVHCI is not set
> -# CONFIG_AF_RXRPC is not set
> -# CONFIG_PHONET is not set
> -CONFIG_WIRELESS=y
> -# CONFIG_CFG80211 is not set
> -CONFIG_WIRELESS_OLD_REGULATORY=y
> -CONFIG_WIRELESS_EXT=y
> -CONFIG_WIRELESS_EXT_SYSFS=y
> -CONFIG_LIB80211=m
> -# CONFIG_MAC80211 is not set
> -# CONFIG_WIMAX is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=m
> -CONFIG_FIRMWARE_IN_KERNEL=y
> -CONFIG_EXTRA_FIRMWARE=""
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_DEBUG_DEVRES is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -# CONFIG_CONNECTOR is not set
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -# CONFIG_MTD_TESTS is not set
> -# CONFIG_MTD_REDBOOT_PARTS is not set
> -CONFIG_MTD_CMDLINE_PARTS=y
> -# CONFIG_MTD_AFS_PARTS is not set
> -# CONFIG_MTD_AR7_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_MTD_BLKDEVS=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_JEDECPROBE=y
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_NOSWAP=y
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_GEOMETRY is not set
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -# CONFIG_MTD_OTP is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_CFI_AMDSTD=y
> -CONFIG_MTD_CFI_STAA=y
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> -CONFIG_MTD_PHYSMAP=y
> -# CONFIG_MTD_PHYSMAP_COMPAT is not set
> -CONFIG_MTD_PXA2XX=y
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_IMPA7 is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_DATAFLASH is not set
> -# CONFIG_MTD_M25P80 is not set
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -CONFIG_MTD_NAND=y
> -# CONFIG_MTD_NAND_VERIFY_WRITE is not set
> -# CONFIG_MTD_NAND_ECC_SMC is not set
> -# CONFIG_MTD_NAND_MUSEUM_IDS is not set
> -# CONFIG_MTD_NAND_H1900 is not set
> -# CONFIG_MTD_NAND_GPIO is not set
> -CONFIG_MTD_NAND_IDS=y
> -# CONFIG_MTD_NAND_DISKONCHIP is not set
> -# CONFIG_MTD_NAND_SHARPSL is not set
> -# CONFIG_MTD_NAND_NANDSIM is not set
> -CONFIG_MTD_NAND_PLATFORM=y
> -# CONFIG_MTD_ALAUDA is not set
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# LPDDR flash memory drivers
> -#
> -# CONFIG_MTD_LPDDR is not set
> -# CONFIG_MTD_QINFO_PROBE is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -CONFIG_BLK_DEV_LOOP=y
> -# CONFIG_BLK_DEV_CRYPTOLOOP is not set
> -# CONFIG_BLK_DEV_NBD is not set
> -# CONFIG_BLK_DEV_UB is not set
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_COUNT=16
> -CONFIG_BLK_DEV_RAM_SIZE=4096
> -# CONFIG_BLK_DEV_XIP is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -# CONFIG_MISC_DEVICES is not set
> -CONFIG_HAVE_IDE=y
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -CONFIG_SCSI=y
> -CONFIG_SCSI_DMA=y
> -# CONFIG_SCSI_TGT is not set
> -# CONFIG_SCSI_NETLINK is not set
> -CONFIG_SCSI_PROC_FS=y
> -
> -#
> -# SCSI support type (disk, tape, CD-ROM)
> -#
> -CONFIG_BLK_DEV_SD=y
> -# CONFIG_CHR_DEV_ST is not set
> -# CONFIG_CHR_DEV_OSST is not set
> -# CONFIG_BLK_DEV_SR is not set
> -# CONFIG_CHR_DEV_SG is not set
> -# CONFIG_CHR_DEV_SCH is not set
> -
> -#
> -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
> -#
> -# CONFIG_SCSI_MULTI_LUN is not set
> -# CONFIG_SCSI_CONSTANTS is not set
> -# CONFIG_SCSI_LOGGING is not set
> -# CONFIG_SCSI_SCAN_ASYNC is not set
> -CONFIG_SCSI_WAIT_SCAN=m
> -
> -#
> -# SCSI Transports
> -#
> -# CONFIG_SCSI_SPI_ATTRS is not set
> -# CONFIG_SCSI_FC_ATTRS is not set
> -# CONFIG_SCSI_ISCSI_ATTRS is not set
> -# CONFIG_SCSI_SAS_LIBSAS is not set
> -# CONFIG_SCSI_SRP_ATTRS is not set
> -# CONFIG_SCSI_LOWLEVEL is not set
> -# CONFIG_SCSI_DH is not set
> -# CONFIG_ATA is not set
> -# CONFIG_MD is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_MACVLAN is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -# CONFIG_VETH is not set
> -# CONFIG_PHYLIB is not set
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=y
> -# CONFIG_AX88796 is not set
> -# CONFIG_SMC91X is not set
> -CONFIG_DM9000=y
> -CONFIG_DM9000_DEBUGLEVEL=1
> -# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
> -# CONFIG_ENC28J60 is not set
> -# CONFIG_SMC911X is not set
> -# CONFIG_SMSC911X is not set
> -# CONFIG_IBM_NEW_EMAC_ZMII is not set
> -# CONFIG_IBM_NEW_EMAC_RGMII is not set
> -# CONFIG_IBM_NEW_EMAC_TAH is not set
> -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
> -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
> -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
> -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
> -# CONFIG_B44 is not set
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -
> -#
> -# Wireless LAN
> -#
> -# CONFIG_WLAN_PRE80211 is not set
> -CONFIG_WLAN_80211=y
> -CONFIG_LIBERTAS=m
> -# CONFIG_LIBERTAS_USB is not set
> -CONFIG_LIBERTAS_SDIO=m
> -# CONFIG_LIBERTAS_DEBUG is not set
> -# CONFIG_USB_ZD1201 is not set
> -# CONFIG_USB_NET_RNDIS_WLAN is not set
> -# CONFIG_IWLWIFI_LEDS is not set
> -# CONFIG_HOSTAP is not set
> -
> -#
> -# Enable WiMAX (Networking options) to see the WiMAX drivers
> -#
> -
> -#
> -# USB Network Adapters
> -#
> -# CONFIG_USB_CATC is not set
> -# CONFIG_USB_KAWETH is not set
> -# CONFIG_USB_PEGASUS is not set
> -# CONFIG_USB_RTL8150 is not set
> -# CONFIG_USB_USBNET is not set
> -# CONFIG_WAN is not set
> -CONFIG_PPP=m
> -CONFIG_PPP_MULTILINK=y
> -CONFIG_PPP_FILTER=y
> -CONFIG_PPP_ASYNC=m
> -# CONFIG_PPP_SYNC_TTY is not set
> -CONFIG_PPP_DEFLATE=m
> -CONFIG_PPP_BSDCOMP=m
> -# CONFIG_PPP_MPPE is not set
> -# CONFIG_PPPOE is not set
> -# CONFIG_PPPOL2TP is not set
> -# CONFIG_SLIP is not set
> -CONFIG_SLHC=m
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -CONFIG_INPUT_MOUSEDEV_PSAUX=y
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> -# CONFIG_INPUT_JOYDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -CONFIG_INPUT_APMPOWER=y
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -CONFIG_KEYBOARD_ATKBD=y
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_KEYBOARD_STOWAWAY is not set
> -CONFIG_KEYBOARD_PXA27x=y
> -CONFIG_KEYBOARD_GPIO=y
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -# CONFIG_TOUCHSCREEN_ADS7846 is not set
> -# CONFIG_TOUCHSCREEN_DA9034 is not set
> -# CONFIG_TOUCHSCREEN_FUJITSU is not set
> -# CONFIG_TOUCHSCREEN_GUNZE is not set
> -# CONFIG_TOUCHSCREEN_ELO is not set
> -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
> -# CONFIG_TOUCHSCREEN_MTOUCH is not set
> -# CONFIG_TOUCHSCREEN_INEXIO is not set
> -# CONFIG_TOUCHSCREEN_MK712 is not set
> -# CONFIG_TOUCHSCREEN_PENMOUNT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
> -CONFIG_TOUCHSCREEN_WM97XX=m
> -# CONFIG_TOUCHSCREEN_WM9705 is not set
> -CONFIG_TOUCHSCREEN_WM9712=y
> -# CONFIG_TOUCHSCREEN_WM9713 is not set
> -# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
> -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
> -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
> -# CONFIG_TOUCHSCREEN_TSC2007 is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -CONFIG_SERIO=y
> -# CONFIG_SERIO_SERPORT is not set
> -CONFIG_SERIO_LIBPS2=y
> -# CONFIG_SERIO_RAW is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_CONSOLE_TRANSLATIONS=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -CONFIG_DEVKMEM=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=16
> -# CONFIG_IPMI_HANDLER is not set
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_NVRAM is not set
> -# CONFIG_R3964 is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -CONFIG_I2C=y
> -CONFIG_I2C_BOARDINFO=y
> -CONFIG_I2C_CHARDEV=m
> -CONFIG_I2C_HELPER_AUTO=y
> -
> -#
> -# I2C Hardware Bus support
> -#
> -
> -#
> -# I2C system bus drivers (mostly embedded / system-on-chip)
> -#
> -# CONFIG_I2C_GPIO is not set
> -# CONFIG_I2C_OCORES is not set
> -CONFIG_I2C_PXA=y
> -# CONFIG_I2C_PXA_SLAVE is not set
> -# CONFIG_I2C_SIMTEC is not set
> -
> -#
> -# External I2C/SMBus adapter drivers
> -#
> -# CONFIG_I2C_PARPORT_LIGHT is not set
> -# CONFIG_I2C_TAOS_EVM is not set
> -# CONFIG_I2C_TINY_USB is not set
> -
> -#
> -# Other I2C/SMBus bus drivers
> -#
> -# CONFIG_I2C_PCA_PLATFORM is not set
> -# CONFIG_I2C_STUB is not set
> -
> -#
> -# Miscellaneous I2C Chip support
> -#
> -# CONFIG_DS1682 is not set
> -# CONFIG_EEPROM_AT24 is not set
> -# CONFIG_EEPROM_LEGACY is not set
> -# CONFIG_SENSORS_PCF8574 is not set
> -# CONFIG_PCF8575 is not set
> -# CONFIG_SENSORS_PCA9539 is not set
> -# CONFIG_SENSORS_PCF8591 is not set
> -# CONFIG_SENSORS_MAX6875 is not set
> -# CONFIG_SENSORS_TSL2550 is not set
> -# CONFIG_I2C_DEBUG_CORE is not set
> -# CONFIG_I2C_DEBUG_ALGO is not set
> -# CONFIG_I2C_DEBUG_BUS is not set
> -# CONFIG_I2C_DEBUG_CHIP is not set
> -CONFIG_SPI=y
> -# CONFIG_SPI_DEBUG is not set
> -CONFIG_SPI_MASTER=y
> -
> -#
> -# SPI Master Controller Drivers
> -#
> -# CONFIG_SPI_BITBANG is not set
> -# CONFIG_SPI_GPIO is not set
> -CONFIG_SPI_PXA2XX=y
> -
> -#
> -# SPI Protocol Masters
> -#
> -# CONFIG_SPI_AT25 is not set
> -# CONFIG_SPI_SPIDEV is not set
> -# CONFIG_SPI_TLE62X0 is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -# CONFIG_DEBUG_GPIO is not set
> -# CONFIG_GPIO_SYSFS is not set
> -
> -#
> -# Memory mapped GPIO expanders:
> -#
> -
> -#
> -# I2C GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX732X is not set
> -# CONFIG_GPIO_PCA953X is not set
> -# CONFIG_GPIO_PCF857X is not set
> -
> -#
> -# PCI GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX7301 is not set
> -# CONFIG_GPIO_MCP23S08 is not set
> -# CONFIG_W1 is not set
> -CONFIG_POWER_SUPPLY=y
> -# CONFIG_POWER_SUPPLY_DEBUG is not set
> -# CONFIG_PDA_POWER is not set
> -# CONFIG_APM_POWER is not set
> -# CONFIG_BATTERY_DS2760 is not set
> -# CONFIG_BATTERY_BQ27x00 is not set
> -CONFIG_BATTERY_DA9030=y
> -# CONFIG_HWMON is not set
> -# CONFIG_THERMAL is not set
> -# CONFIG_THERMAL_HWMON is not set
> -# CONFIG_WATCHDOG is not set
> -CONFIG_SSB_POSSIBLE=y
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_CORE is not set
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_MFD_ASIC3 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -# CONFIG_UCB1400_CORE is not set
> -# CONFIG_TPS65010 is not set
> -# CONFIG_TWL4030_CORE is not set
> -# CONFIG_MFD_TMIO is not set
> -# CONFIG_MFD_T7L66XB is not set
> -# CONFIG_MFD_TC6387XB is not set
> -# CONFIG_MFD_TC6393XB is not set
> -CONFIG_PMIC_DA903X=y
> -# CONFIG_MFD_WM8400 is not set
> -# CONFIG_MFD_WM8350_I2C is not set
> -# CONFIG_MFD_PCF50633 is not set
> -
> -#
> -# Multimedia devices
> -#
> -
> -#
> -# Multimedia core support
> -#
> -CONFIG_VIDEO_DEV=m
> -CONFIG_VIDEO_V4L2_COMMON=m
> -# CONFIG_VIDEO_ALLOW_V4L1 is not set
> -CONFIG_VIDEO_V4L1_COMPAT=y
> -# CONFIG_DVB_CORE is not set
> -CONFIG_VIDEO_MEDIA=m
> -
> -#
> -# Multimedia drivers
> -#
> -# CONFIG_MEDIA_ATTACH is not set
> -CONFIG_MEDIA_TUNER=m
> -CONFIG_MEDIA_TUNER_CUSTOMIZE=y
> -# CONFIG_MEDIA_TUNER_SIMPLE is not set
> -# CONFIG_MEDIA_TUNER_TDA8290 is not set
> -# CONFIG_MEDIA_TUNER_TDA827X is not set
> -# CONFIG_MEDIA_TUNER_TDA18271 is not set
> -# CONFIG_MEDIA_TUNER_TDA9887 is not set
> -# CONFIG_MEDIA_TUNER_TEA5761 is not set
> -# CONFIG_MEDIA_TUNER_TEA5767 is not set
> -# CONFIG_MEDIA_TUNER_MT20XX is not set
> -# CONFIG_MEDIA_TUNER_MT2060 is not set
> -# CONFIG_MEDIA_TUNER_MT2266 is not set
> -# CONFIG_MEDIA_TUNER_MT2131 is not set
> -# CONFIG_MEDIA_TUNER_QT1010 is not set
> -# CONFIG_MEDIA_TUNER_XC2028 is not set
> -# CONFIG_MEDIA_TUNER_XC5000 is not set
> -# CONFIG_MEDIA_TUNER_MXL5005S is not set
> -# CONFIG_MEDIA_TUNER_MXL5007T is not set
> -CONFIG_VIDEO_V4L2=m
> -CONFIG_VIDEOBUF_GEN=m
> -CONFIG_VIDEOBUF_DMA_SG=m
> -CONFIG_VIDEO_CAPTURE_DRIVERS=y
> -# CONFIG_VIDEO_ADV_DEBUG is not set
> -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
> -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
> -
> -#
> -# Encoders/decoders and other helper chips
> -#
> -
> -#
> -# Audio decoders
> -#
> -# CONFIG_VIDEO_TVAUDIO is not set
> -# CONFIG_VIDEO_TDA7432 is not set
> -# CONFIG_VIDEO_TDA9840 is not set
> -# CONFIG_VIDEO_TDA9875 is not set
> -# CONFIG_VIDEO_TEA6415C is not set
> -# CONFIG_VIDEO_TEA6420 is not set
> -# CONFIG_VIDEO_MSP3400 is not set
> -# CONFIG_VIDEO_CS5345 is not set
> -# CONFIG_VIDEO_CS53L32A is not set
> -# CONFIG_VIDEO_M52790 is not set
> -# CONFIG_VIDEO_TLV320AIC23B is not set
> -# CONFIG_VIDEO_WM8775 is not set
> -# CONFIG_VIDEO_WM8739 is not set
> -# CONFIG_VIDEO_VP27SMPX is not set
> -
> -#
> -# Video decoders
> -#
> -# CONFIG_VIDEO_OV7670 is not set
> -# CONFIG_VIDEO_TCM825X is not set
> -# CONFIG_VIDEO_SAA711X is not set
> -# CONFIG_VIDEO_SAA717X is not set
> -# CONFIG_VIDEO_TVP514X is not set
> -# CONFIG_VIDEO_TVP5150 is not set
> -
> -#
> -# Video and audio decoders
> -#
> -# CONFIG_VIDEO_CX25840 is not set
> -
> -#
> -# MPEG video encoders
> -#
> -# CONFIG_VIDEO_CX2341X is not set
> -
> -#
> -# Video encoders
> -#
> -# CONFIG_VIDEO_SAA7127 is not set
> -
> -#
> -# Video improvement chips
> -#
> -# CONFIG_VIDEO_UPD64031A is not set
> -# CONFIG_VIDEO_UPD64083 is not set
> -# CONFIG_VIDEO_VIVI is not set
> -# CONFIG_VIDEO_SAA5246A is not set
> -# CONFIG_VIDEO_SAA5249 is not set
> -CONFIG_SOC_CAMERA=m
> -# CONFIG_SOC_CAMERA_MT9M001 is not set
> -CONFIG_SOC_CAMERA_MT9M111=m
> -# CONFIG_SOC_CAMERA_MT9T031 is not set
> -# CONFIG_SOC_CAMERA_MT9V022 is not set
> -# CONFIG_SOC_CAMERA_TW9910 is not set
> -# CONFIG_SOC_CAMERA_PLATFORM is not set
> -# CONFIG_SOC_CAMERA_OV772X is not set
> -CONFIG_VIDEO_PXA27x=m
> -# CONFIG_VIDEO_SH_MOBILE_CEU is not set
> -# CONFIG_V4L_USB_DRIVERS is not set
> -# CONFIG_RADIO_ADAPTERS is not set
> -# CONFIG_DAB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -CONFIG_FB=y
> -# CONFIG_FIRMWARE_EDID is not set
> -# CONFIG_FB_DDC is not set
> -# CONFIG_FB_BOOT_VESA_SUPPORT is not set
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> -# CONFIG_FB_SYS_FILLRECT is not set
> -# CONFIG_FB_SYS_COPYAREA is not set
> -# CONFIG_FB_SYS_IMAGEBLIT is not set
> -# CONFIG_FB_FOREIGN_ENDIAN is not set
> -# CONFIG_FB_SYS_FOPS is not set
> -# CONFIG_FB_SVGALIB is not set
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -
> -#
> -# Frame buffer hardware drivers
> -#
> -# CONFIG_FB_S1D13XXX is not set
> -CONFIG_FB_PXA=y
> -# CONFIG_FB_PXA_OVERLAY is not set
> -# CONFIG_FB_PXA_SMARTPANEL is not set
> -CONFIG_FB_PXA_PARAMETERS=y
> -CONFIG_FB_MBX=m
> -# CONFIG_FB_MBX_DEBUG is not set
> -# CONFIG_FB_W100 is not set
> -# CONFIG_FB_VIRTUAL is not set
> -# CONFIG_FB_METRONOME is not set
> -# CONFIG_FB_MB862XX is not set
> -CONFIG_BACKLIGHT_LCD_SUPPORT=y
> -CONFIG_LCD_CLASS_DEVICE=y
> -# CONFIG_LCD_LTV350QV is not set
> -# CONFIG_LCD_ILI9320 is not set
> -CONFIG_LCD_TDO24M=y
> -# CONFIG_LCD_VGG2432A4 is not set
> -# CONFIG_LCD_PLATFORM is not set
> -CONFIG_BACKLIGHT_CLASS_DEVICE=m
> -# CONFIG_BACKLIGHT_GENERIC is not set
> -CONFIG_BACKLIGHT_DA903X=m
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
> -# CONFIG_FONTS is not set
> -CONFIG_FONT_8x8=y
> -CONFIG_FONT_8x16=y
> -CONFIG_LOGO=y
> -CONFIG_LOGO_LINUX_MONO=y
> -CONFIG_LOGO_LINUX_VGA16=y
> -CONFIG_LOGO_LINUX_CLUT224=y
> -CONFIG_SOUND=m
> -CONFIG_SOUND_OSS_CORE=y
> -CONFIG_SND=m
> -CONFIG_SND_TIMER=m
> -CONFIG_SND_PCM=m
> -# CONFIG_SND_SEQUENCER is not set
> -CONFIG_SND_OSSEMUL=y
> -CONFIG_SND_MIXER_OSS=m
> -CONFIG_SND_PCM_OSS=m
> -CONFIG_SND_PCM_OSS_PLUGINS=y
> -# CONFIG_SND_DYNAMIC_MINORS is not set
> -CONFIG_SND_SUPPORT_OLD_API=y
> -CONFIG_SND_VERBOSE_PROCFS=y
> -# CONFIG_SND_VERBOSE_PRINTK is not set
> -# CONFIG_SND_DEBUG is not set
> -CONFIG_SND_VMASTER=y
> -CONFIG_SND_AC97_CODEC=m
> -# CONFIG_SND_DRIVERS is not set
> -CONFIG_SND_ARM=y
> -CONFIG_SND_PXA2XX_LIB=m
> -CONFIG_SND_PXA2XX_LIB_AC97=y
> -# CONFIG_SND_PXA2XX_AC97 is not set
> -# CONFIG_SND_SPI is not set
> -# CONFIG_SND_USB is not set
> -CONFIG_SND_SOC=m
> -CONFIG_SND_SOC_AC97_BUS=y
> -CONFIG_SND_PXA2XX_SOC=m
> -CONFIG_SND_PXA2XX_SOC_AC97=m
> -CONFIG_SND_PXA2XX_SOC_EM_X270=m
> -CONFIG_SND_SOC_I2C_AND_SPI=m
> -# CONFIG_SND_SOC_ALL_CODECS is not set
> -CONFIG_SND_SOC_WM9712=m
> -# CONFIG_SOUND_PRIME is not set
> -CONFIG_AC97_BUS=m
> -CONFIG_HID_SUPPORT=y
> -CONFIG_HID=y
> -CONFIG_HID_DEBUG=y
> -# CONFIG_HIDRAW is not set
> -
> -#
> -# USB Input Devices
> -#
> -CONFIG_USB_HID=y
> -# CONFIG_HID_PID is not set
> -# CONFIG_USB_HIDDEV is not set
> -
> -#
> -# Special HID drivers
> -#
> -CONFIG_HID_COMPAT=y
> -CONFIG_HID_A4TECH=y
> -CONFIG_HID_APPLE=y
> -CONFIG_HID_BELKIN=y
> -CONFIG_HID_CHERRY=y
> -CONFIG_HID_CHICONY=y
> -CONFIG_HID_CYPRESS=y
> -CONFIG_HID_EZKEY=y
> -CONFIG_HID_GYRATION=y
> -CONFIG_HID_LOGITECH=y
> -# CONFIG_LOGITECH_FF is not set
> -# CONFIG_LOGIRUMBLEPAD2_FF is not set
> -CONFIG_HID_MICROSOFT=y
> -CONFIG_HID_MONTEREY=y
> -# CONFIG_HID_NTRIG is not set
> -CONFIG_HID_PANTHERLORD=y
> -# CONFIG_PANTHERLORD_FF is not set
> -CONFIG_HID_PETALYNX=y
> -CONFIG_HID_SAMSUNG=y
> -CONFIG_HID_SONY=y
> -CONFIG_HID_SUNPLUS=y
> -# CONFIG_GREENASIA_FF is not set
> -# CONFIG_HID_TOPSEED is not set
> -# CONFIG_THRUSTMASTER_FF is not set
> -# CONFIG_ZEROPLUS_FF is not set
> -CONFIG_USB_SUPPORT=y
> -CONFIG_USB_ARCH_HAS_HCD=y
> -CONFIG_USB_ARCH_HAS_OHCI=y
> -# CONFIG_USB_ARCH_HAS_EHCI is not set
> -CONFIG_USB=y
> -# CONFIG_USB_DEBUG is not set
> -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
> -
> -#
> -# Miscellaneous USB options
> -#
> -CONFIG_USB_DEVICEFS=y
> -# CONFIG_USB_DEVICE_CLASS is not set
> -# CONFIG_USB_DYNAMIC_MINORS is not set
> -# CONFIG_USB_SUSPEND is not set
> -# CONFIG_USB_OTG is not set
> -# CONFIG_USB_OTG_WHITELIST is not set
> -# CONFIG_USB_OTG_BLACKLIST_HUB is not set
> -CONFIG_USB_MON=y
> -# CONFIG_USB_WUSB is not set
> -# CONFIG_USB_WUSB_CBAF is not set
> -
> -#
> -# USB Host Controller Drivers
> -#
> -# CONFIG_USB_C67X00_HCD is not set
> -# CONFIG_USB_OXU210HP_HCD is not set
> -# CONFIG_USB_ISP116X_HCD is not set
> -CONFIG_USB_OHCI_HCD=y
> -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
> -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
> -CONFIG_USB_OHCI_LITTLE_ENDIAN=y
> -# CONFIG_USB_SL811_HCD is not set
> -# CONFIG_USB_R8A66597_HCD is not set
> -# CONFIG_USB_HWA_HCD is not set
> -# CONFIG_USB_MUSB_HDRC is not set
> -
> -#
> -# USB Device Class drivers
> -#
> -# CONFIG_USB_ACM is not set
> -# CONFIG_USB_PRINTER is not set
> -# CONFIG_USB_WDM is not set
> -# CONFIG_USB_TMC is not set
> -
> -#
> -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
> -#
> -
> -#
> -# see USB_STORAGE Help for more information
> -#
> -CONFIG_USB_STORAGE=y
> -# CONFIG_USB_STORAGE_DEBUG is not set
> -# CONFIG_USB_STORAGE_DATAFAB is not set
> -# CONFIG_USB_STORAGE_FREECOM is not set
> -# CONFIG_USB_STORAGE_ISD200 is not set
> -# CONFIG_USB_STORAGE_USBAT is not set
> -# CONFIG_USB_STORAGE_SDDR09 is not set
> -# CONFIG_USB_STORAGE_SDDR55 is not set
> -# CONFIG_USB_STORAGE_JUMPSHOT is not set
> -# CONFIG_USB_STORAGE_ALAUDA is not set
> -# CONFIG_USB_STORAGE_ONETOUCH is not set
> -# CONFIG_USB_STORAGE_KARMA is not set
> -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
> -# CONFIG_USB_LIBUSUAL is not set
> -
> -#
> -# USB Imaging devices
> -#
> -# CONFIG_USB_MDC800 is not set
> -# CONFIG_USB_MICROTEK is not set
> -
> -#
> -# USB port drivers
> -#
> -# CONFIG_USB_SERIAL is not set
> -
> -#
> -# USB Miscellaneous drivers
> -#
> -# CONFIG_USB_EMI62 is not set
> -# CONFIG_USB_EMI26 is not set
> -# CONFIG_USB_ADUTUX is not set
> -# CONFIG_USB_SEVSEG is not set
> -# CONFIG_USB_RIO500 is not set
> -# CONFIG_USB_LEGOTOWER is not set
> -# CONFIG_USB_LCD is not set
> -# CONFIG_USB_BERRY_CHARGE is not set
> -# CONFIG_USB_LED is not set
> -# CONFIG_USB_CYPRESS_CY7C63 is not set
> -# CONFIG_USB_CYTHERM is not set
> -# CONFIG_USB_PHIDGET is not set
> -# CONFIG_USB_IDMOUSE is not set
> -# CONFIG_USB_FTDI_ELAN is not set
> -# CONFIG_USB_APPLEDISPLAY is not set
> -# CONFIG_USB_LD is not set
> -# CONFIG_USB_TRANCEVIBRATOR is not set
> -# CONFIG_USB_IOWARRIOR is not set
> -# CONFIG_USB_TEST is not set
> -# CONFIG_USB_ISIGHTFW is not set
> -# CONFIG_USB_VST is not set
> -# CONFIG_USB_GADGET is not set
> -
> -#
> -# OTG and related infrastructure
> -#
> -# CONFIG_USB_GPIO_VBUS is not set
> -CONFIG_MMC=m
> -# CONFIG_MMC_DEBUG is not set
> -# CONFIG_MMC_UNSAFE_RESUME is not set
> -
> -#
> -# MMC/SD/SDIO Card Drivers
> -#
> -CONFIG_MMC_BLOCK=m
> -CONFIG_MMC_BLOCK_BOUNCE=y
> -# CONFIG_SDIO_UART is not set
> -# CONFIG_MMC_TEST is not set
> -
> -#
> -# MMC/SD/SDIO Host Controller Drivers
> -#
> -CONFIG_MMC_PXA=m
> -# CONFIG_MMC_SDHCI is not set
> -# CONFIG_MMC_SPI is not set
> -# CONFIG_MEMSTICK is not set
> -# CONFIG_ACCESSIBILITY is not set
> -CONFIG_NEW_LEDS=y
> -CONFIG_LEDS_CLASS=y
> -
> -#
> -# LED drivers
> -#
> -# CONFIG_LEDS_PCA9532 is not set
> -# CONFIG_LEDS_GPIO is not set
> -# CONFIG_LEDS_PCA955X is not set
> -CONFIG_LEDS_DA903X=y
> -
> -#
> -# LED Triggers
> -#
> -CONFIG_LEDS_TRIGGERS=y
> -# CONFIG_LEDS_TRIGGER_TIMER is not set
> -CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> -# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
> -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_HCTOSYS=y
> -CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
> -# CONFIG_RTC_DEBUG is not set
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -# CONFIG_RTC_DRV_TEST is not set
> -
> -#
> -# I2C RTC drivers
> -#
> -# CONFIG_RTC_DRV_DS1307 is not set
> -# CONFIG_RTC_DRV_DS1374 is not set
> -# CONFIG_RTC_DRV_DS1672 is not set
> -# CONFIG_RTC_DRV_MAX6900 is not set
> -# CONFIG_RTC_DRV_RS5C372 is not set
> -# CONFIG_RTC_DRV_ISL1208 is not set
> -# CONFIG_RTC_DRV_X1205 is not set
> -# CONFIG_RTC_DRV_PCF8563 is not set
> -# CONFIG_RTC_DRV_PCF8583 is not set
> -# CONFIG_RTC_DRV_M41T80 is not set
> -# CONFIG_RTC_DRV_S35390A is not set
> -# CONFIG_RTC_DRV_FM3130 is not set
> -# CONFIG_RTC_DRV_RX8581 is not set
> -
> -#
> -# SPI RTC drivers
> -#
> -# CONFIG_RTC_DRV_M41T94 is not set
> -# CONFIG_RTC_DRV_DS1305 is not set
> -# CONFIG_RTC_DRV_DS1390 is not set
> -# CONFIG_RTC_DRV_MAX6902 is not set
> -# CONFIG_RTC_DRV_R9701 is not set
> -# CONFIG_RTC_DRV_RS5C348 is not set
> -# CONFIG_RTC_DRV_DS3234 is not set
> -
> -#
> -# Platform RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_DS1286 is not set
> -# CONFIG_RTC_DRV_DS1511 is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_STK17TA8 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -# CONFIG_RTC_DRV_M48T35 is not set
> -# CONFIG_RTC_DRV_M48T59 is not set
> -# CONFIG_RTC_DRV_BQ4802 is not set
> -CONFIG_RTC_DRV_V3020=y
> -
> -#
> -# on-CPU RTC drivers
> -#
> -CONFIG_RTC_DRV_SA1100=y
> -# CONFIG_RTC_DRV_PXA is not set
> -# CONFIG_DMADEVICES is not set
> -CONFIG_REGULATOR=y
> -# CONFIG_REGULATOR_DEBUG is not set
> -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
> -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
> -# CONFIG_REGULATOR_BQ24022 is not set
> -CONFIG_REGULATOR_DA903X=y
> -# CONFIG_UIO is not set
> -# CONFIG_STAGING is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -CONFIG_EXT3_FS=y
> -CONFIG_EXT3_FS_XATTR=y
> -# CONFIG_EXT3_FS_POSIX_ACL is not set
> -# CONFIG_EXT3_FS_SECURITY is not set
> -# CONFIG_EXT4_FS is not set
> -CONFIG_JBD=y
> -# CONFIG_JBD_DEBUG is not set
> -CONFIG_FS_MBCACHE=y
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -# CONFIG_FS_POSIX_ACL is not set
> -CONFIG_FILE_LOCKING=y
> -# CONFIG_XFS_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_BTRFS_FS is not set
> -CONFIG_DNOTIFY=y
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=m
> -# CONFIG_MSDOS_FS is not set
> -CONFIG_VFAT_FS=m
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -# CONFIG_PROC_PAGE_MONITOR is not set
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -CONFIG_MISC_FILESYSTEMS=y
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
> -CONFIG_JFFS2_SUMMARY=y
> -# CONFIG_JFFS2_FS_XATTR is not set
> -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
> -CONFIG_JFFS2_ZLIB=y
> -# CONFIG_JFFS2_LZO is not set
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_SQUASHFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_OMFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -CONFIG_NETWORK_FILESYSTEMS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -# CONFIG_NFS_V3_ACL is not set
> -# CONFIG_NFS_V4 is not set
> -CONFIG_ROOT_NFS=y
> -# CONFIG_NFSD is not set
> -CONFIG_LOCKD=y
> -CONFIG_LOCKD_V4=y
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=y
> -# CONFIG_SUNRPC_REGISTER_V4 is not set
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -CONFIG_CIFS=m
> -# CONFIG_CIFS_STATS is not set
> -# CONFIG_CIFS_WEAK_PW_HASH is not set
> -# CONFIG_CIFS_XATTR is not set
> -# CONFIG_CIFS_DEBUG2 is not set
> -# CONFIG_CIFS_EXPERIMENTAL is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -CONFIG_PARTITION_ADVANCED=y
> -# CONFIG_ACORN_PARTITION is not set
> -# CONFIG_OSF_PARTITION is not set
> -# CONFIG_AMIGA_PARTITION is not set
> -# CONFIG_ATARI_PARTITION is not set
> -# CONFIG_MAC_PARTITION is not set
> -CONFIG_MSDOS_PARTITION=y
> -# CONFIG_BSD_DISKLABEL is not set
> -# CONFIG_MINIX_SUBPARTITION is not set
> -# CONFIG_SOLARIS_X86_PARTITION is not set
> -# CONFIG_UNIXWARE_DISKLABEL is not set
> -# CONFIG_LDM_PARTITION is not set
> -# CONFIG_SGI_PARTITION is not set
> -# CONFIG_ULTRIX_PARTITION is not set
> -# CONFIG_SUN_PARTITION is not set
> -# CONFIG_KARMA_PARTITION is not set
> -# CONFIG_EFI_PARTITION is not set
> -# CONFIG_SYSV68_PARTITION is not set
> -CONFIG_NLS=m
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -CONFIG_NLS_CODEPAGE_437=m
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -# CONFIG_NLS_CODEPAGE_850 is not set
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -CONFIG_NLS_ISO8859_1=m
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -# CONFIG_NLS_ISO8859_15 is not set
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -CONFIG_NLS_UTF8=m
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_FRAME_WARN=0
> -# CONFIG_MAGIC_SYSRQ is not set
> -# CONFIG_UNUSED_SYMBOLS is not set
> -CONFIG_DEBUG_FS=y
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DEBUG_SHIRQ is not set
> -# CONFIG_DETECT_SOFTLOCKUP is not set
> -# CONFIG_SCHED_DEBUG is not set
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_TIMER_STATS is not set
> -# CONFIG_DEBUG_OBJECTS is not set
> -# CONFIG_DEBUG_RT_MUTEXES is not set
> -# CONFIG_RT_MUTEX_TESTER is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -# CONFIG_DEBUG_MUTEXES is not set
> -# CONFIG_DEBUG_LOCK_ALLOC is not set
> -# CONFIG_PROVE_LOCKING is not set
> -# CONFIG_LOCK_STAT is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -# CONFIG_DEBUG_INFO is not set
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_WRITECOUNT is not set
> -# CONFIG_DEBUG_MEMORY_INIT is not set
> -# CONFIG_DEBUG_LIST is not set
> -# CONFIG_DEBUG_SG is not set
> -# CONFIG_DEBUG_NOTIFIERS is not set
> -CONFIG_FRAME_POINTER=y
> -# CONFIG_BOOT_PRINTK_DELAY is not set
> -# CONFIG_RCU_TORTURE_TEST is not set
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -# CONFIG_BACKTRACE_SELF_TEST is not set
> -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
> -# CONFIG_FAULT_INJECTION is not set
> -# CONFIG_LATENCYTOP is not set
> -CONFIG_SYSCTL_SYSCALL_CHECK=y
> -CONFIG_HAVE_FUNCTION_TRACER=y
> -
> -#
> -# Tracers
> -#
> -# CONFIG_FUNCTION_TRACER is not set
> -# CONFIG_IRQSOFF_TRACER is not set
> -# CONFIG_SCHED_TRACER is not set
> -# CONFIG_CONTEXT_SWITCH_TRACER is not set
> -# CONFIG_BOOT_TRACER is not set
> -# CONFIG_TRACE_BRANCH_PROFILING is not set
> -# CONFIG_STACK_TRACER is not set
> -# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -# CONFIG_KGDB is not set
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> -# CONFIG_DEBUG_STACK_USAGE is not set
> -CONFIG_DEBUG_LL=y
> -# CONFIG_DEBUG_ICEDCC is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITYFS is not set
> -# CONFIG_SECURITY_FILE_CAPABILITIES is not set
> -CONFIG_CRYPTO=y
> -
> -#
> -# Crypto core or helper
> -#
> -# CONFIG_CRYPTO_FIPS is not set
> -CONFIG_CRYPTO_ALGAPI=m
> -CONFIG_CRYPTO_ALGAPI2=m
> -CONFIG_CRYPTO_AEAD2=m
> -CONFIG_CRYPTO_BLKCIPHER=m
> -CONFIG_CRYPTO_BLKCIPHER2=m
> -CONFIG_CRYPTO_HASH=m
> -CONFIG_CRYPTO_HASH2=m
> -CONFIG_CRYPTO_RNG2=m
> -CONFIG_CRYPTO_MANAGER=m
> -CONFIG_CRYPTO_MANAGER2=m
> -# CONFIG_CRYPTO_GF128MUL is not set
> -# CONFIG_CRYPTO_NULL is not set
> -# CONFIG_CRYPTO_CRYPTD is not set
> -# CONFIG_CRYPTO_AUTHENC is not set
> -# CONFIG_CRYPTO_TEST is not set
> -
> -#
> -# Authenticated Encryption with Associated Data
> -#
> -# CONFIG_CRYPTO_CCM is not set
> -# CONFIG_CRYPTO_GCM is not set
> -# CONFIG_CRYPTO_SEQIV is not set
> -
> -#
> -# Block modes
> -#
> -# CONFIG_CRYPTO_CBC is not set
> -# CONFIG_CRYPTO_CTR is not set
> -# CONFIG_CRYPTO_CTS is not set
> -CONFIG_CRYPTO_ECB=m
> -# CONFIG_CRYPTO_LRW is not set
> -# CONFIG_CRYPTO_PCBC is not set
> -# CONFIG_CRYPTO_XTS is not set
> -
> -#
> -# Hash modes
> -#
> -# CONFIG_CRYPTO_HMAC is not set
> -# CONFIG_CRYPTO_XCBC is not set
> -
> -#
> -# Digest
> -#
> -# CONFIG_CRYPTO_CRC32C is not set
> -# CONFIG_CRYPTO_MD4 is not set
> -# CONFIG_CRYPTO_MD5 is not set
> -CONFIG_CRYPTO_MICHAEL_MIC=m
> -# CONFIG_CRYPTO_RMD128 is not set
> -# CONFIG_CRYPTO_RMD160 is not set
> -# CONFIG_CRYPTO_RMD256 is not set
> -# CONFIG_CRYPTO_RMD320 is not set
> -# CONFIG_CRYPTO_SHA1 is not set
> -# CONFIG_CRYPTO_SHA256 is not set
> -# CONFIG_CRYPTO_SHA512 is not set
> -# CONFIG_CRYPTO_TGR192 is not set
> -# CONFIG_CRYPTO_WP512 is not set
> -
> -#
> -# Ciphers
> -#
> -CONFIG_CRYPTO_AES=m
> -# CONFIG_CRYPTO_ANUBIS is not set
> -CONFIG_CRYPTO_ARC4=m
> -# CONFIG_CRYPTO_BLOWFISH is not set
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -# CONFIG_CRYPTO_CAST5 is not set
> -# CONFIG_CRYPTO_CAST6 is not set
> -# CONFIG_CRYPTO_DES is not set
> -# CONFIG_CRYPTO_FCRYPT is not set
> -# CONFIG_CRYPTO_KHAZAD is not set
> -# CONFIG_CRYPTO_SALSA20 is not set
> -# CONFIG_CRYPTO_SEED is not set
> -# CONFIG_CRYPTO_SERPENT is not set
> -# CONFIG_CRYPTO_TEA is not set
> -# CONFIG_CRYPTO_TWOFISH is not set
> -
> -#
> -# Compression
> -#
> -# CONFIG_CRYPTO_DEFLATE is not set
> -# CONFIG_CRYPTO_LZO is not set
> -
> -#
> -# Random Number Generation
> -#
> -# CONFIG_CRYPTO_ANSI_CPRNG is not set
> -# CONFIG_CRYPTO_HW is not set
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -CONFIG_GENERIC_FIND_LAST_BIT=y
> -CONFIG_CRC_CCITT=m
> -# CONFIG_CRC16 is not set
> -# CONFIG_CRC_T10DIF is not set
> -# CONFIG_CRC_ITU_T is not set
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_PLIST=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig
> deleted file mode 100644
> index 74baf57..0000000
> --- a/arch/arm/configs/eseries_pxa_defconfig
> +++ /dev/null
> @@ -1,1246 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.28-rc8
> -# Wed Dec 24 23:35:45 2008
> -#
> -CONFIG_ARM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_MMU=y
> -# CONFIG_NO_IOPORT is not set
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -# CONFIG_ARCH_HAS_ILOG2_U32 is not set
> -# CONFIG_ARCH_HAS_ILOG2_U64 is not set
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=""
> -CONFIG_LOCALVERSION_AUTO=y
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -# CONFIG_IKCONFIG is not set
> -CONFIG_LOG_BUF_SHIFT=14
> -# CONFIG_CGROUPS is not set
> -# CONFIG_GROUP_SCHED is not set
> -# CONFIG_SYSFS_DEPRECATED_V2 is not set
> -# CONFIG_RELAY is not set
> -# CONFIG_NAMESPACES is not set
> -# CONFIG_BLK_DEV_INITRD is not set
> -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
> -CONFIG_SYSCTL=y
> -CONFIG_EMBEDDED=y
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -# CONFIG_KALLSYMS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -# CONFIG_COMPAT_BRK is not set
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_ANON_INODES=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -CONFIG_SHMEM=y
> -CONFIG_AIO=y
> -CONFIG_VM_EVENT_COUNTERS=y
> -CONFIG_SLAB=y
> -# CONFIG_SLUB is not set
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -# CONFIG_MARKERS is not set
> -CONFIG_HAVE_OPROFILE=y
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -CONFIG_HAVE_CLK=y
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_SLABINFO=y
> -CONFIG_RT_MUTEXES=y
> -# CONFIG_TINY_SHMEM is not set
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_MODULE_FORCE_UNLOAD=y
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -CONFIG_KMOD=y
> -CONFIG_BLOCK=y
> -# CONFIG_LBD is not set
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_LSF is not set
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_BLK_DEV_INTEGRITY is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_AS=y
> -# CONFIG_IOSCHED_DEADLINE is not set
> -# CONFIG_IOSCHED_CFQ is not set
> -CONFIG_DEFAULT_AS=y
> -# CONFIG_DEFAULT_DEADLINE is not set
> -# CONFIG_DEFAULT_CFQ is not set
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="anticipatory"
> -CONFIG_CLASSIC_RCU=y
> -CONFIG_FREEZER=y
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_MSM is not set
> -# CONFIG_ARCH_W90X900 is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -# CONFIG_ARCH_GUMSTIX is not set
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_MACH_MP900C is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_ARCH_VIPER is not set
> -CONFIG_ARCH_PXA_ESERIES=y
> -CONFIG_MACH_E330=y
> -CONFIG_MACH_E350=y
> -CONFIG_MACH_E740=y
> -CONFIG_MACH_E750=y
> -CONFIG_MACH_E400=y
> -CONFIG_MACH_E800=y
> -# CONFIG_TRIZEPS_PXA is not set
> -# CONFIG_MACH_H5000 is not set
> -# CONFIG_MACH_EM_X270 is not set
> -# CONFIG_MACH_COLIBRI is not set
> -# CONFIG_MACH_ZYLONITE is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_TAVOREVB is not set
> -# CONFIG_MACH_SAAR is not set
> -# CONFIG_MACH_ARMCORE is not set
> -# CONFIG_MACH_CM_X300 is not set
> -# CONFIG_MACH_MAGICIAN is not set
> -# CONFIG_MACH_MIOA701 is not set
> -# CONFIG_MACH_PCM027 is not set
> -# CONFIG_ARCH_PXA_PALM is not set
> -# CONFIG_PXA_EZX is not set
> -CONFIG_PXA25x=y
> -# CONFIG_PXA_PWM is not set
> -CONFIG_PXA_HAVE_BOARD_IRQS=y
> -
> -#
> -# Boot options
> -#
> -
> -#
> -# Power management
> -#
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_PABRT_NOIFAR=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -# CONFIG_ARM_THUMB is not set
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -# CONFIG_OUTER_CACHE is not set
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -CONFIG_COMMON_CLKDEV=y
> -
> -#
> -# Bus support
> -#
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -CONFIG_PCCARD=y
> -# CONFIG_PCMCIA_DEBUG is not set
> -CONFIG_PCMCIA=m
> -CONFIG_PCMCIA_LOAD_CIS=y
> -CONFIG_PCMCIA_IOCTL=y
> -
> -#
> -# PC-card bridges
> -#
> -CONFIG_PCMCIA_PXA2XX=m
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -# CONFIG_NO_HZ is not set
> -# CONFIG_HIGH_RES_TIMERS is not set
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -CONFIG_VMSPLIT_3G=y
> -# CONFIG_VMSPLIT_2G is not set
> -# CONFIG_VMSPLIT_1G is not set
> -CONFIG_PAGE_OFFSET=0xC0000000
> -# CONFIG_PREEMPT is not set
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -CONFIG_ARCH_FLATMEM_HAS_HOLES=y
> -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -CONFIG_PAGEFLAGS_EXTENDED=y
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_RESOURCES_64BIT is not set
> -# CONFIG_PHYS_ADDR_T_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=0
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_UNEVICTABLE_LRU=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE=""
> -# CONFIG_XIP_KERNEL is not set
> -CONFIG_KEXEC=y
> -CONFIG_ATAGS_PROC=y
> -
> -#
> -# CPU Power Management
> -#
> -# CONFIG_CPU_FREQ is not set
> -# CONFIG_CPU_IDLE is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> -CONFIG_HAVE_AOUT=y
> -# CONFIG_BINFMT_AOUT is not set
> -CONFIG_BINFMT_MISC=y
> -
> -#
> -# Power management options
> -#
> -CONFIG_PM=y
> -# CONFIG_PM_DEBUG is not set
> -CONFIG_PM_SLEEP=y
> -CONFIG_SUSPEND=y
> -CONFIG_SUSPEND_FREEZER=y
> -# CONFIG_APM_EMULATION is not set
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -# CONFIG_PACKET is not set
> -CONFIG_UNIX=y
> -CONFIG_XFRM=y
> -# CONFIG_XFRM_USER is not set
> -# CONFIG_XFRM_SUB_POLICY is not set
> -# CONFIG_XFRM_MIGRATE is not set
> -# CONFIG_XFRM_STATISTICS is not set
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -# CONFIG_IP_PNP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -CONFIG_INET_XFRM_MODE_TRANSPORT=y
> -CONFIG_INET_XFRM_MODE_TUNNEL=y
> -CONFIG_INET_XFRM_MODE_BEET=y
> -# CONFIG_INET_LRO is not set
> -CONFIG_INET_DIAG=y
> -CONFIG_INET_TCP_DIAG=y
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -# CONFIG_NETFILTER is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_NET_DSA is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_NET_SCHED is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -CONFIG_IRDA=y
> -
> -#
> -# IrDA protocols
> -#
> -CONFIG_IRLAN=m
> -CONFIG_IRCOMM=m
> -CONFIG_IRDA_ULTRA=y
> -
> -#
> -# IrDA options
> -#
> -CONFIG_IRDA_CACHE_LAST_LSAP=y
> -CONFIG_IRDA_FAST_RR=y
> -# CONFIG_IRDA_DEBUG is not set
> -
> -#
> -# Infrared-port device drivers
> -#
> -
> -#
> -# SIR device drivers
> -#
> -# CONFIG_IRTTY_SIR is not set
> -
> -#
> -# Dongle support
> -#
> -
> -#
> -# FIR device drivers
> -#
> -CONFIG_PXA_FICP=y
> -# CONFIG_BT is not set
> -# CONFIG_AF_RXRPC is not set
> -# CONFIG_PHONET is not set
> -CONFIG_WIRELESS=y
> -CONFIG_CFG80211=m
> -CONFIG_NL80211=y
> -CONFIG_WIRELESS_OLD_REGULATORY=y
> -CONFIG_WIRELESS_EXT=y
> -CONFIG_WIRELESS_EXT_SYSFS=y
> -CONFIG_MAC80211=m
> -
> -#
> -# Rate control algorithm selection
> -#
> -CONFIG_MAC80211_RC_PID=y
> -# CONFIG_MAC80211_RC_MINSTREL is not set
> -CONFIG_MAC80211_RC_DEFAULT_PID=y
> -# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
> -CONFIG_MAC80211_RC_DEFAULT="pid"
> -# CONFIG_MAC80211_MESH is not set
> -# CONFIG_MAC80211_LEDS is not set
> -# CONFIG_MAC80211_DEBUG_MENU is not set
> -CONFIG_IEEE80211=m
> -# CONFIG_IEEE80211_DEBUG is not set
> -CONFIG_IEEE80211_CRYPT_WEP=m
> -CONFIG_IEEE80211_CRYPT_CCMP=m
> -CONFIG_IEEE80211_CRYPT_TKIP=m
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -# CONFIG_STANDALONE is not set
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=y
> -CONFIG_FIRMWARE_IN_KERNEL=y
> -CONFIG_EXTRA_FIRMWARE=""
> -# CONFIG_SYS_HYPERVISOR is not set
> -# CONFIG_CONNECTOR is not set
> -CONFIG_MTD=m
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_CONCAT is not set
> -# CONFIG_MTD_PARTITIONS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -# CONFIG_MTD_CHAR is not set
> -# CONFIG_MTD_BLKDEVS is not set
> -# CONFIG_MTD_BLOCK is not set
> -# CONFIG_MTD_BLOCK_RO is not set
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -# CONFIG_MTD_CFI is not set
> -# CONFIG_MTD_JEDECPROBE is not set
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -CONFIG_MTD_NAND=m
> -# CONFIG_MTD_NAND_VERIFY_WRITE is not set
> -# CONFIG_MTD_NAND_ECC_SMC is not set
> -# CONFIG_MTD_NAND_MUSEUM_IDS is not set
> -# CONFIG_MTD_NAND_GPIO is not set
> -CONFIG_MTD_NAND_IDS=m
> -# CONFIG_MTD_NAND_DISKONCHIP is not set
> -# CONFIG_MTD_NAND_SHARPSL is not set
> -CONFIG_MTD_NAND_TMIO=m
> -# CONFIG_MTD_NAND_PLATFORM is not set
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -CONFIG_BLK_DEV_LOOP=m
> -# CONFIG_BLK_DEV_CRYPTOLOOP is not set
> -# CONFIG_BLK_DEV_NBD is not set
> -# CONFIG_BLK_DEV_RAM is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -CONFIG_MISC_DEVICES=y
> -# CONFIG_EEPROM_93CX6 is not set
> -# CONFIG_ENCLOSURE_SERVICES is not set
> -# CONFIG_C2PORT is not set
> -CONFIG_HAVE_IDE=y
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -CONFIG_SCSI=m
> -CONFIG_SCSI_DMA=y
> -# CONFIG_SCSI_TGT is not set
> -# CONFIG_SCSI_NETLINK is not set
> -# CONFIG_SCSI_PROC_FS is not set
> -
> -#
> -# SCSI support type (disk, tape, CD-ROM)
> -#
> -CONFIG_BLK_DEV_SD=m
> -# CONFIG_CHR_DEV_ST is not set
> -# CONFIG_CHR_DEV_OSST is not set
> -# CONFIG_BLK_DEV_SR is not set
> -# CONFIG_CHR_DEV_SG is not set
> -# CONFIG_CHR_DEV_SCH is not set
> -
> -#
> -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
> -#
> -# CONFIG_SCSI_MULTI_LUN is not set
> -# CONFIG_SCSI_CONSTANTS is not set
> -# CONFIG_SCSI_LOGGING is not set
> -# CONFIG_SCSI_SCAN_ASYNC is not set
> -CONFIG_SCSI_WAIT_SCAN=m
> -
> -#
> -# SCSI Transports
> -#
> -# CONFIG_SCSI_SPI_ATTRS is not set
> -# CONFIG_SCSI_FC_ATTRS is not set
> -# CONFIG_SCSI_ISCSI_ATTRS is not set
> -# CONFIG_SCSI_SAS_LIBSAS is not set
> -# CONFIG_SCSI_SRP_ATTRS is not set
> -# CONFIG_SCSI_LOWLEVEL is not set
> -# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
> -# CONFIG_SCSI_DH is not set
> -CONFIG_ATA=m
> -# CONFIG_ATA_NONSTANDARD is not set
> -# CONFIG_SATA_PMP is not set
> -CONFIG_ATA_SFF=y
> -# CONFIG_SATA_MV is not set
> -CONFIG_PATA_PCMCIA=m
> -# CONFIG_PATA_PLATFORM is not set
> -# CONFIG_MD is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_MACVLAN is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -# CONFIG_VETH is not set
> -# CONFIG_NET_ETHERNET is not set
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -
> -#
> -# Wireless LAN
> -#
> -# CONFIG_WLAN_PRE80211 is not set
> -CONFIG_WLAN_80211=y
> -# CONFIG_PCMCIA_RAYCS is not set
> -# CONFIG_LIBERTAS is not set
> -# CONFIG_LIBERTAS_THINFIRM is not set
> -CONFIG_HERMES=m
> -CONFIG_PCMCIA_HERMES=m
> -# CONFIG_PCMCIA_SPECTRUM is not set
> -# CONFIG_ATMEL is not set
> -# CONFIG_AIRO_CS is not set
> -# CONFIG_PCMCIA_WL3501 is not set
> -# CONFIG_MAC80211_HWSIM is not set
> -# CONFIG_P54_COMMON is not set
> -# CONFIG_IWLWIFI_LEDS is not set
> -# CONFIG_HOSTAP is not set
> -# CONFIG_B43 is not set
> -# CONFIG_B43LEGACY is not set
> -# CONFIG_RT2X00 is not set
> -CONFIG_NET_PCMCIA=y
> -# CONFIG_PCMCIA_3C589 is not set
> -# CONFIG_PCMCIA_3C574 is not set
> -# CONFIG_PCMCIA_FMVJ18X is not set
> -# CONFIG_PCMCIA_PCNET is not set
> -# CONFIG_PCMCIA_NMCLAN is not set
> -# CONFIG_PCMCIA_SMC91C92 is not set
> -# CONFIG_PCMCIA_XIRC2PS is not set
> -# CONFIG_PCMCIA_AXNET is not set
> -# CONFIG_WAN is not set
> -# CONFIG_PPP is not set
> -# CONFIG_SLIP is not set
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -# CONFIG_INPUT_MOUSEDEV is not set
> -# CONFIG_INPUT_JOYDEV is not set
> -CONFIG_INPUT_EVDEV=m
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -# CONFIG_KEYBOARD_ATKBD is not set
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_KEYBOARD_STOWAWAY is not set
> -CONFIG_KEYBOARD_GPIO=m
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -# CONFIG_TOUCHSCREEN_FUJITSU is not set
> -# CONFIG_TOUCHSCREEN_GUNZE is not set
> -# CONFIG_TOUCHSCREEN_ELO is not set
> -# CONFIG_TOUCHSCREEN_MTOUCH is not set
> -# CONFIG_TOUCHSCREEN_INEXIO is not set
> -# CONFIG_TOUCHSCREEN_MK712 is not set
> -# CONFIG_TOUCHSCREEN_PENMOUNT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
> -CONFIG_TOUCHSCREEN_WM97XX=m
> -CONFIG_TOUCHSCREEN_WM9705=y
> -CONFIG_TOUCHSCREEN_WM9712=y
> -CONFIG_TOUCHSCREEN_WM9713=y
> -# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
> -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -# CONFIG_SERIO is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_CONSOLE_TRANSLATIONS=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -CONFIG_DEVKMEM=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -# CONFIG_SERIAL_PXA_CONSOLE is not set
> -CONFIG_SERIAL_CORE=y
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_LEGACY_PTYS is not set
> -# CONFIG_IPMI_HANDLER is not set
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_NVRAM is not set
> -# CONFIG_R3964 is not set
> -
> -#
> -# PCMCIA character devices
> -#
> -# CONFIG_SYNCLINK_CS is not set
> -# CONFIG_CARDMAN_4000 is not set
> -# CONFIG_CARDMAN_4040 is not set
> -# CONFIG_IPWIRELESS is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -# CONFIG_I2C is not set
> -# CONFIG_SPI is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -# CONFIG_GPIO_SYSFS is not set
> -
> -#
> -# Memory mapped GPIO expanders:
> -#
> -
> -#
> -# I2C GPIO expanders:
> -#
> -
> -#
> -# PCI GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -# CONFIG_W1 is not set
> -# CONFIG_POWER_SUPPLY is not set
> -# CONFIG_HWMON is not set
> -# CONFIG_THERMAL is not set
> -# CONFIG_THERMAL_HWMON is not set
> -# CONFIG_WATCHDOG is not set
> -CONFIG_SSB_POSSIBLE=y
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -CONFIG_MFD_CORE=y
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_MFD_ASIC3 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -# CONFIG_UCB1400_CORE is not set
> -CONFIG_MFD_TMIO=y
> -CONFIG_MFD_T7L66XB=y
> -CONFIG_MFD_TC6387XB=y
> -CONFIG_MFD_TC6393XB=y
> -
> -#
> -# Multimedia devices
> -#
> -
> -#
> -# Multimedia core support
> -#
> -# CONFIG_VIDEO_DEV is not set
> -# CONFIG_DVB_CORE is not set
> -# CONFIG_VIDEO_MEDIA is not set
> -
> -#
> -# Multimedia drivers
> -#
> -# CONFIG_DAB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -CONFIG_FB=y
> -# CONFIG_FIRMWARE_EDID is not set
> -# CONFIG_FB_DDC is not set
> -# CONFIG_FB_BOOT_VESA_SUPPORT is not set
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> -# CONFIG_FB_SYS_FILLRECT is not set
> -# CONFIG_FB_SYS_COPYAREA is not set
> -# CONFIG_FB_SYS_IMAGEBLIT is not set
> -# CONFIG_FB_FOREIGN_ENDIAN is not set
> -# CONFIG_FB_SYS_FOPS is not set
> -# CONFIG_FB_SVGALIB is not set
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -
> -#
> -# Frame buffer hardware drivers
> -#
> -# CONFIG_FB_S1D13XXX is not set
> -CONFIG_FB_PXA=y
> -# CONFIG_FB_PXA_SMARTPANEL is not set
> -# CONFIG_FB_PXA_PARAMETERS is not set
> -# CONFIG_FB_MBX is not set
> -CONFIG_FB_W100=y
> -# CONFIG_FB_TMIO is not set
> -# CONFIG_FB_VIRTUAL is not set
> -# CONFIG_FB_METRONOME is not set
> -# CONFIG_FB_MB862XX is not set
> -CONFIG_BACKLIGHT_LCD_SUPPORT=y
> -CONFIG_LCD_CLASS_DEVICE=y
> -# CONFIG_LCD_ILI9320 is not set
> -# CONFIG_LCD_PLATFORM is not set
> -CONFIG_BACKLIGHT_CLASS_DEVICE=y
> -CONFIG_BACKLIGHT_CORGI=y
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
> -CONFIG_FONTS=y
> -# CONFIG_FONT_8x8 is not set
> -# CONFIG_FONT_8x16 is not set
> -# CONFIG_FONT_6x11 is not set
> -# CONFIG_FONT_7x14 is not set
> -# CONFIG_FONT_PEARL_8x8 is not set
> -# CONFIG_FONT_ACORN_8x8 is not set
> -CONFIG_FONT_MINI_4x6=y
> -# CONFIG_FONT_SUN8x16 is not set
> -# CONFIG_FONT_SUN12x22 is not set
> -# CONFIG_FONT_10x18 is not set
> -# CONFIG_LOGO is not set
> -CONFIG_SOUND=y
> -CONFIG_SOUND_OSS_CORE=y
> -CONFIG_SND=m
> -CONFIG_SND_TIMER=m
> -CONFIG_SND_PCM=m
> -# CONFIG_SND_SEQUENCER is not set
> -CONFIG_SND_OSSEMUL=y
> -CONFIG_SND_MIXER_OSS=m
> -CONFIG_SND_PCM_OSS=m
> -CONFIG_SND_PCM_OSS_PLUGINS=y
> -CONFIG_SND_DYNAMIC_MINORS=y
> -CONFIG_SND_SUPPORT_OLD_API=y
> -CONFIG_SND_VERBOSE_PROCFS=y
> -CONFIG_SND_VERBOSE_PRINTK=y
> -# CONFIG_SND_DEBUG is not set
> -CONFIG_SND_VMASTER=y
> -CONFIG_SND_AC97_CODEC=m
> -CONFIG_SND_DRIVERS=y
> -# CONFIG_SND_DUMMY is not set
> -# CONFIG_SND_MTPAV is not set
> -# CONFIG_SND_SERIAL_U16550 is not set
> -# CONFIG_SND_MPU401 is not set
> -# CONFIG_SND_AC97_POWER_SAVE is not set
> -CONFIG_SND_ARM=y
> -CONFIG_SND_PXA2XX_LIB=m
> -CONFIG_SND_PXA2XX_LIB_AC97=y
> -# CONFIG_SND_PXA2XX_AC97 is not set
> -# CONFIG_SND_PCMCIA is not set
> -CONFIG_SND_SOC=m
> -CONFIG_SND_SOC_AC97_BUS=y
> -CONFIG_SND_PXA2XX_SOC=m
> -CONFIG_SND_PXA2XX_SOC_AC97=m
> -CONFIG_SND_PXA2XX_SOC_E800=m
> -CONFIG_SND_SOC_WM9712=m
> -# CONFIG_SOUND_PRIME is not set
> -CONFIG_AC97_BUS=m
> -CONFIG_HID_SUPPORT=y
> -CONFIG_HID=y
> -# CONFIG_HID_DEBUG is not set
> -# CONFIG_HIDRAW is not set
> -# CONFIG_HID_PID is not set
> -
> -#
> -# Special HID drivers
> -#
> -CONFIG_HID_COMPAT=y
> -# CONFIG_USB_SUPPORT is not set
> -CONFIG_MMC=y
> -# CONFIG_MMC_DEBUG is not set
> -CONFIG_MMC_UNSAFE_RESUME=y
> -
> -#
> -# MMC/SD/SDIO Card Drivers
> -#
> -CONFIG_MMC_BLOCK=y
> -CONFIG_MMC_BLOCK_BOUNCE=y
> -# CONFIG_SDIO_UART is not set
> -# CONFIG_MMC_TEST is not set
> -
> -#
> -# MMC/SD/SDIO Host Controller Drivers
> -#
> -# CONFIG_MMC_PXA is not set
> -# CONFIG_MMC_SDHCI is not set
> -CONFIG_MMC_TMIO=y
> -# CONFIG_MEMSTICK is not set
> -# CONFIG_ACCESSIBILITY is not set
> -# CONFIG_NEW_LEDS is not set
> -CONFIG_RTC_LIB=y
> -# CONFIG_RTC_CLASS is not set
> -# CONFIG_DMADEVICES is not set
> -# CONFIG_REGULATOR is not set
> -# CONFIG_UIO is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -CONFIG_EXT3_FS=m
> -CONFIG_EXT3_FS_XATTR=y
> -# CONFIG_EXT3_FS_POSIX_ACL is not set
> -# CONFIG_EXT3_FS_SECURITY is not set
> -# CONFIG_EXT4_FS is not set
> -CONFIG_JBD=m
> -CONFIG_FS_MBCACHE=m
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -# CONFIG_FS_POSIX_ACL is not set
> -CONFIG_FILE_LOCKING=y
> -# CONFIG_XFS_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -CONFIG_DNOTIFY=y
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=y
> -# CONFIG_MSDOS_FS is not set
> -CONFIG_VFAT_FS=y
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_PROC_PAGE_MONITOR=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -
> -#
> -# Miscellaneous filesystems
> -#
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -# CONFIG_JFFS2_FS is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_OMFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -CONFIG_NETWORK_FILESYSTEMS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -# CONFIG_NFS_V3_ACL is not set
> -# CONFIG_NFS_V4 is not set
> -# CONFIG_NFSD is not set
> -CONFIG_LOCKD=y
> -CONFIG_LOCKD_V4=y
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=y
> -# CONFIG_SUNRPC_REGISTER_V4 is not set
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -# CONFIG_CIFS is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -CONFIG_PARTITION_ADVANCED=y
> -# CONFIG_ACORN_PARTITION is not set
> -# CONFIG_OSF_PARTITION is not set
> -# CONFIG_AMIGA_PARTITION is not set
> -# CONFIG_ATARI_PARTITION is not set
> -# CONFIG_MAC_PARTITION is not set
> -CONFIG_MSDOS_PARTITION=y
> -# CONFIG_BSD_DISKLABEL is not set
> -# CONFIG_MINIX_SUBPARTITION is not set
> -# CONFIG_SOLARIS_X86_PARTITION is not set
> -# CONFIG_UNIXWARE_DISKLABEL is not set
> -# CONFIG_LDM_PARTITION is not set
> -# CONFIG_SGI_PARTITION is not set
> -# CONFIG_ULTRIX_PARTITION is not set
> -# CONFIG_SUN_PARTITION is not set
> -# CONFIG_KARMA_PARTITION is not set
> -# CONFIG_EFI_PARTITION is not set
> -# CONFIG_SYSV68_PARTITION is not set
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -CONFIG_NLS_CODEPAGE_437=y
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -# CONFIG_NLS_CODEPAGE_850 is not set
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -CONFIG_NLS_ISO8859_1=y
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -# CONFIG_NLS_ISO8859_15 is not set
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -# CONFIG_NLS_UTF8 is not set
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -# CONFIG_ENABLE_WARN_DEPRECATED is not set
> -# CONFIG_ENABLE_MUST_CHECK is not set
> -CONFIG_FRAME_WARN=1024
> -# CONFIG_MAGIC_SYSRQ is not set
> -# CONFIG_UNUSED_SYMBOLS is not set
> -# CONFIG_DEBUG_FS is not set
> -# CONFIG_HEADERS_CHECK is not set
> -# CONFIG_DEBUG_KERNEL is not set
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -# CONFIG_DEBUG_MEMORY_INIT is not set
> -CONFIG_FRAME_POINTER=y
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -# CONFIG_LATENCYTOP is not set
> -CONFIG_SYSCTL_SYSCALL_CHECK=y
> -CONFIG_HAVE_FUNCTION_TRACER=y
> -
> -#
> -# Tracers
> -#
> -# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -# CONFIG_DEBUG_USER is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITYFS is not set
> -# CONFIG_SECURITY_FILE_CAPABILITIES is not set
> -CONFIG_CRYPTO=y
> -
> -#
> -# Crypto core or helper
> -#
> -# CONFIG_CRYPTO_FIPS is not set
> -CONFIG_CRYPTO_ALGAPI=m
> -CONFIG_CRYPTO_ALGAPI2=m
> -CONFIG_CRYPTO_AEAD2=m
> -CONFIG_CRYPTO_BLKCIPHER=m
> -CONFIG_CRYPTO_BLKCIPHER2=m
> -CONFIG_CRYPTO_HASH2=m
> -CONFIG_CRYPTO_RNG2=m
> -CONFIG_CRYPTO_MANAGER=m
> -CONFIG_CRYPTO_MANAGER2=m
> -# CONFIG_CRYPTO_GF128MUL is not set
> -# CONFIG_CRYPTO_NULL is not set
> -# CONFIG_CRYPTO_CRYPTD is not set
> -# CONFIG_CRYPTO_AUTHENC is not set
> -# CONFIG_CRYPTO_TEST is not set
> -
> -#
> -# Authenticated Encryption with Associated Data
> -#
> -# CONFIG_CRYPTO_CCM is not set
> -# CONFIG_CRYPTO_GCM is not set
> -# CONFIG_CRYPTO_SEQIV is not set
> -
> -#
> -# Block modes
> -#
> -CONFIG_CRYPTO_CBC=m
> -# CONFIG_CRYPTO_CTR is not set
> -# CONFIG_CRYPTO_CTS is not set
> -CONFIG_CRYPTO_ECB=m
> -# CONFIG_CRYPTO_LRW is not set
> -CONFIG_CRYPTO_PCBC=m
> -# CONFIG_CRYPTO_XTS is not set
> -
> -#
> -# Hash modes
> -#
> -# CONFIG_CRYPTO_HMAC is not set
> -# CONFIG_CRYPTO_XCBC is not set
> -
> -#
> -# Digest
> -#
> -# CONFIG_CRYPTO_CRC32C is not set
> -# CONFIG_CRYPTO_MD4 is not set
> -# CONFIG_CRYPTO_MD5 is not set
> -CONFIG_CRYPTO_MICHAEL_MIC=m
> -# CONFIG_CRYPTO_RMD128 is not set
> -# CONFIG_CRYPTO_RMD160 is not set
> -# CONFIG_CRYPTO_RMD256 is not set
> -# CONFIG_CRYPTO_RMD320 is not set
> -# CONFIG_CRYPTO_SHA1 is not set
> -# CONFIG_CRYPTO_SHA256 is not set
> -# CONFIG_CRYPTO_SHA512 is not set
> -# CONFIG_CRYPTO_TGR192 is not set
> -# CONFIG_CRYPTO_WP512 is not set
> -
> -#
> -# Ciphers
> -#
> -CONFIG_CRYPTO_AES=m
> -# CONFIG_CRYPTO_ANUBIS is not set
> -CONFIG_CRYPTO_ARC4=m
> -# CONFIG_CRYPTO_BLOWFISH is not set
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -# CONFIG_CRYPTO_CAST5 is not set
> -# CONFIG_CRYPTO_CAST6 is not set
> -# CONFIG_CRYPTO_DES is not set
> -# CONFIG_CRYPTO_FCRYPT is not set
> -# CONFIG_CRYPTO_KHAZAD is not set
> -# CONFIG_CRYPTO_SALSA20 is not set
> -# CONFIG_CRYPTO_SEED is not set
> -# CONFIG_CRYPTO_SERPENT is not set
> -# CONFIG_CRYPTO_TEA is not set
> -# CONFIG_CRYPTO_TWOFISH is not set
> -
> -#
> -# Compression
> -#
> -# CONFIG_CRYPTO_DEFLATE is not set
> -# CONFIG_CRYPTO_LZO is not set
> -
> -#
> -# Random Number Generation
> -#
> -# CONFIG_CRYPTO_ANSI_CPRNG is not set
> -CONFIG_CRYPTO_HW=y
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -CONFIG_CRC_CCITT=y
> -# CONFIG_CRC16 is not set
> -# CONFIG_CRC_T10DIF is not set
> -# CONFIG_CRC_ITU_T is not set
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_PLIST=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig
> deleted file mode 100644
> index 9e9057c..0000000
> --- a/arch/arm/configs/ezx_defconfig
> +++ /dev/null
> @@ -1,2000 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.32-rc5
> -# Mon Nov ?2 13:18:50 2009
> -#
> -CONFIG_ARM=y
> -CONFIG_HAVE_PWM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -CONFIG_ARCH_HAS_CPUFREQ=y
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -CONFIG_CONSTRUCTORS=y
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_LOCK_KERNEL=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION="-ezx200910312315"
> -# CONFIG_LOCALVERSION_AUTO is not set
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -
> -#
> -# RCU Subsystem
> -#
> -CONFIG_TREE_RCU=y
> -# CONFIG_TREE_PREEMPT_RCU is not set
> -# CONFIG_RCU_TRACE is not set
> -CONFIG_RCU_FANOUT=32
> -# CONFIG_RCU_FANOUT_EXACT is not set
> -# CONFIG_TREE_RCU_TRACE is not set
> -# CONFIG_IKCONFIG is not set
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_GROUP_SCHED=y
> -CONFIG_FAIR_GROUP_SCHED=y
> -# CONFIG_RT_GROUP_SCHED is not set
> -CONFIG_USER_SCHED=y
> -# CONFIG_CGROUP_SCHED is not set
> -# CONFIG_CGROUPS is not set
> -CONFIG_SYSFS_DEPRECATED=y
> -CONFIG_SYSFS_DEPRECATED_V2=y
> -# CONFIG_RELAY is not set
> -# CONFIG_NAMESPACES is not set
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_INITRAMFS_SOURCE=""
> -CONFIG_RD_GZIP=y
> -CONFIG_RD_BZIP2=y
> -CONFIG_RD_LZMA=y
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -CONFIG_ANON_INODES=y
> -CONFIG_EMBEDDED=y
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -CONFIG_KALLSYMS_ALL=y
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -CONFIG_SHMEM=y
> -CONFIG_AIO=y
> -
> -#
> -# Kernel Performance Events And Counters
> -#
> -CONFIG_VM_EVENT_COUNTERS=y
> -# CONFIG_COMPAT_BRK is not set
> -CONFIG_SLAB=y
> -# CONFIG_SLUB is not set
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -CONFIG_HAVE_OPROFILE=y
> -# CONFIG_KPROBES is not set
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -CONFIG_HAVE_CLK=y
> -
> -#
> -# GCOV-based kernel profiling
> -#
> -# CONFIG_GCOV_KERNEL is not set
> -CONFIG_SLOW_WORK=y
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_SLABINFO=y
> -CONFIG_RT_MUTEXES=y
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_MODULE_FORCE_UNLOAD=y
> -CONFIG_MODVERSIONS=y
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -CONFIG_BLOCK=y
> -# CONFIG_LBDAF is not set
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_BLK_DEV_INTEGRITY is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -# CONFIG_IOSCHED_AS is not set
> -CONFIG_IOSCHED_DEADLINE=y
> -# CONFIG_IOSCHED_CFQ is not set
> -# CONFIG_DEFAULT_AS is not set
> -CONFIG_DEFAULT_DEADLINE=y
> -# CONFIG_DEFAULT_CFQ is not set
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="deadline"
> -CONFIG_FREEZER=y
> -
> -#
> -# System Type
> -#
> -CONFIG_MMU=y
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_GEMINI is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_STMP3XXX is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_NOMADIK is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_MMP is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_W90X900 is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_MSM is not set
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_S3C64XX is not set
> -# CONFIG_ARCH_S5PC1XX is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_U300 is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_BCMRING is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -# CONFIG_ARCH_GUMSTIX is not set
> -# CONFIG_MACH_INTELMOTE2 is not set
> -# CONFIG_MACH_STARGATE2 is not set
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_MACH_MP900C is not set
> -# CONFIG_MACH_BALLOON3 is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_ARCH_VIPER is not set
> -# CONFIG_ARCH_PXA_ESERIES is not set
> -# CONFIG_TRIZEPS_PXA is not set
> -# CONFIG_MACH_H5000 is not set
> -# CONFIG_MACH_EM_X270 is not set
> -# CONFIG_MACH_EXEDA is not set
> -# CONFIG_MACH_COLIBRI is not set
> -# CONFIG_MACH_COLIBRI300 is not set
> -# CONFIG_MACH_COLIBRI320 is not set
> -# CONFIG_MACH_ZYLONITE is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_TAVOREVB is not set
> -# CONFIG_MACH_SAAR is not set
> -# CONFIG_MACH_ARMCORE is not set
> -# CONFIG_MACH_CM_X300 is not set
> -# CONFIG_MACH_H4700 is not set
> -# CONFIG_MACH_MAGICIAN is not set
> -# CONFIG_MACH_HIMALAYA is not set
> -# CONFIG_MACH_MIOA701 is not set
> -# CONFIG_MACH_PCM027 is not set
> -# CONFIG_ARCH_PXA_PALM is not set
> -# CONFIG_MACH_CSB726 is not set
> -CONFIG_PXA_EZX=y
> -CONFIG_MACH_EZX_A780=y
> -CONFIG_MACH_EZX_E680=y
> -CONFIG_MACH_EZX_A1200=y
> -CONFIG_MACH_EZX_A910=y
> -CONFIG_MACH_EZX_E6=y
> -CONFIG_MACH_EZX_E2=y
> -# CONFIG_MACH_XCEP is not set
> -CONFIG_PXA27x=y
> -CONFIG_PXA_SSP=y
> -CONFIG_PXA_HAVE_BOARD_IRQS=y
> -CONFIG_PLAT_PXA=y
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_PABRT_LEGACY=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -CONFIG_ARM_L1_CACHE_SHIFT=5
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -CONFIG_COMMON_CLKDEV=y
> -
> -#
> -# Bus support
> -#
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -CONFIG_NO_HZ=y
> -CONFIG_HIGH_RES_TIMERS=y
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -CONFIG_VMSPLIT_3G=y
> -# CONFIG_VMSPLIT_2G is not set
> -# CONFIG_VMSPLIT_1G is not set
> -CONFIG_PAGE_OFFSET=0xC0000000
> -# CONFIG_PREEMPT_NONE is not set
> -# CONFIG_PREEMPT_VOLUNTARY is not set
> -CONFIG_PREEMPT=y
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> -# CONFIG_HIGHMEM is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -CONFIG_PAGEFLAGS_EXTENDED=y
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_PHYS_ADDR_T_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=0
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_HAVE_MLOCK=y
> -CONFIG_HAVE_MLOCKED_PAGE_BIT=y
> -# CONFIG_KSM is not set
> -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
> -CONFIG_ALIGNMENT_TRAP=y
> -# CONFIG_UACCESS_WITH_MEMCPY is not set
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=3 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug"
> -# CONFIG_XIP_KERNEL is not set
> -CONFIG_KEXEC=y
> -CONFIG_ATAGS_PROC=y
> -
> -#
> -# CPU Power Management
> -#
> -CONFIG_CPU_FREQ=y
> -CONFIG_CPU_FREQ_TABLE=y
> -CONFIG_CPU_FREQ_DEBUG=y
> -CONFIG_CPU_FREQ_STAT=y
> -# CONFIG_CPU_FREQ_STAT_DETAILS is not set
> -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
> -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
> -CONFIG_CPU_FREQ_GOV_POWERSAVE=m
> -CONFIG_CPU_FREQ_GOV_USERSPACE=m
> -CONFIG_CPU_FREQ_GOV_ONDEMAND=m
> -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
> -CONFIG_CPU_IDLE=y
> -CONFIG_CPU_IDLE_GOV_LADDER=y
> -CONFIG_CPU_IDLE_GOV_MENU=y
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> -CONFIG_HAVE_AOUT=y
> -CONFIG_BINFMT_AOUT=m
> -CONFIG_BINFMT_MISC=m
> -
> -#
> -# Power management options
> -#
> -CONFIG_PM=y
> -# CONFIG_PM_DEBUG is not set
> -CONFIG_PM_SLEEP=y
> -CONFIG_SUSPEND=y
> -CONFIG_SUSPEND_FREEZER=y
> -CONFIG_APM_EMULATION=y
> -CONFIG_PM_RUNTIME=y
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_PACKET=y
> -CONFIG_PACKET_MMAP=y
> -CONFIG_UNIX=y
> -CONFIG_XFRM=y
> -# CONFIG_XFRM_USER is not set
> -# CONFIG_XFRM_SUB_POLICY is not set
> -# CONFIG_XFRM_MIGRATE is not set
> -# CONFIG_XFRM_STATISTICS is not set
> -CONFIG_XFRM_IPCOMP=m
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -CONFIG_IP_PNP_BOOTP=y
> -CONFIG_IP_PNP_RARP=y
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -CONFIG_SYN_COOKIES=y
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -CONFIG_INET_TUNNEL=m
> -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_BEET is not set
> -# CONFIG_INET_LRO is not set
> -# CONFIG_INET_DIAG is not set
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -CONFIG_IPV6=m
> -# CONFIG_IPV6_PRIVACY is not set
> -# CONFIG_IPV6_ROUTER_PREF is not set
> -# CONFIG_IPV6_OPTIMISTIC_DAD is not set
> -CONFIG_INET6_AH=m
> -CONFIG_INET6_ESP=m
> -CONFIG_INET6_IPCOMP=m
> -CONFIG_IPV6_MIP6=m
> -CONFIG_INET6_XFRM_TUNNEL=m
> -CONFIG_INET6_TUNNEL=m
> -CONFIG_INET6_XFRM_MODE_TRANSPORT=m
> -CONFIG_INET6_XFRM_MODE_TUNNEL=m
> -CONFIG_INET6_XFRM_MODE_BEET=m
> -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
> -CONFIG_IPV6_SIT=m
> -CONFIG_IPV6_NDISC_NODETYPE=y
> -CONFIG_IPV6_TUNNEL=m
> -CONFIG_IPV6_MULTIPLE_TABLES=y
> -CONFIG_IPV6_SUBTREES=y
> -# CONFIG_IPV6_MROUTE is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -CONFIG_NETFILTER=y
> -# CONFIG_NETFILTER_DEBUG is not set
> -CONFIG_NETFILTER_ADVANCED=y
> -CONFIG_BRIDGE_NETFILTER=y
> -
> -#
> -# Core Netfilter Configuration
> -#
> -CONFIG_NETFILTER_NETLINK=m
> -CONFIG_NETFILTER_NETLINK_QUEUE=m
> -CONFIG_NETFILTER_NETLINK_LOG=m
> -CONFIG_NF_CONNTRACK=m
> -CONFIG_NF_CT_ACCT=y
> -CONFIG_NF_CONNTRACK_MARK=y
> -CONFIG_NF_CONNTRACK_EVENTS=y
> -# CONFIG_NF_CT_PROTO_DCCP is not set
> -CONFIG_NF_CT_PROTO_GRE=m
> -CONFIG_NF_CT_PROTO_SCTP=m
> -CONFIG_NF_CT_PROTO_UDPLITE=m
> -CONFIG_NF_CONNTRACK_AMANDA=m
> -CONFIG_NF_CONNTRACK_FTP=m
> -CONFIG_NF_CONNTRACK_H323=m
> -CONFIG_NF_CONNTRACK_IRC=m
> -CONFIG_NF_CONNTRACK_NETBIOS_NS=m
> -CONFIG_NF_CONNTRACK_PPTP=m
> -CONFIG_NF_CONNTRACK_SANE=m
> -CONFIG_NF_CONNTRACK_SIP=m
> -CONFIG_NF_CONNTRACK_TFTP=m
> -CONFIG_NF_CT_NETLINK=m
> -# CONFIG_NETFILTER_TPROXY is not set
> -CONFIG_NETFILTER_XTABLES=m
> -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
> -# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
> -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
> -CONFIG_NETFILTER_XT_TARGET_HL=m
> -CONFIG_NETFILTER_XT_TARGET_LED=m
> -CONFIG_NETFILTER_XT_TARGET_MARK=m
> -CONFIG_NETFILTER_XT_TARGET_NFLOG=m
> -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
> -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
> -# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
> -# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
> -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
> -# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
> -# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
> -CONFIG_NETFILTER_XT_MATCH_COMMENT=m
> -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
> -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
> -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
> -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
> -CONFIG_NETFILTER_XT_MATCH_DCCP=m
> -CONFIG_NETFILTER_XT_MATCH_DSCP=m
> -CONFIG_NETFILTER_XT_MATCH_ESP=m
> -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
> -CONFIG_NETFILTER_XT_MATCH_HELPER=m
> -CONFIG_NETFILTER_XT_MATCH_HL=m
> -# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
> -CONFIG_NETFILTER_XT_MATCH_LENGTH=m
> -CONFIG_NETFILTER_XT_MATCH_LIMIT=m
> -CONFIG_NETFILTER_XT_MATCH_MAC=m
> -CONFIG_NETFILTER_XT_MATCH_MARK=m
> -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
> -# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
> -CONFIG_NETFILTER_XT_MATCH_POLICY=m
> -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
> -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
> -CONFIG_NETFILTER_XT_MATCH_QUOTA=m
> -# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
> -CONFIG_NETFILTER_XT_MATCH_REALM=m
> -# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
> -CONFIG_NETFILTER_XT_MATCH_SCTP=m
> -CONFIG_NETFILTER_XT_MATCH_STATE=m
> -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
> -CONFIG_NETFILTER_XT_MATCH_STRING=m
> -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
> -CONFIG_NETFILTER_XT_MATCH_TIME=m
> -CONFIG_NETFILTER_XT_MATCH_U32=m
> -# CONFIG_NETFILTER_XT_MATCH_OSF is not set
> -# CONFIG_IP_VS is not set
> -
> -#
> -# IP: Netfilter Configuration
> -#
> -CONFIG_NF_DEFRAG_IPV4=m
> -CONFIG_NF_CONNTRACK_IPV4=m
> -CONFIG_NF_CONNTRACK_PROC_COMPAT=y
> -CONFIG_IP_NF_QUEUE=m
> -CONFIG_IP_NF_IPTABLES=m
> -CONFIG_IP_NF_MATCH_ADDRTYPE=m
> -CONFIG_IP_NF_MATCH_AH=m
> -CONFIG_IP_NF_MATCH_ECN=m
> -CONFIG_IP_NF_MATCH_TTL=m
> -CONFIG_IP_NF_FILTER=m
> -CONFIG_IP_NF_TARGET_REJECT=m
> -CONFIG_IP_NF_TARGET_LOG=m
> -CONFIG_IP_NF_TARGET_ULOG=m
> -CONFIG_NF_NAT=m
> -CONFIG_NF_NAT_NEEDED=y
> -CONFIG_IP_NF_TARGET_MASQUERADE=m
> -CONFIG_IP_NF_TARGET_NETMAP=m
> -CONFIG_IP_NF_TARGET_REDIRECT=m
> -CONFIG_NF_NAT_SNMP_BASIC=m
> -CONFIG_NF_NAT_PROTO_GRE=m
> -CONFIG_NF_NAT_PROTO_UDPLITE=m
> -CONFIG_NF_NAT_PROTO_SCTP=m
> -CONFIG_NF_NAT_FTP=m
> -CONFIG_NF_NAT_IRC=m
> -CONFIG_NF_NAT_TFTP=m
> -CONFIG_NF_NAT_AMANDA=m
> -CONFIG_NF_NAT_PPTP=m
> -CONFIG_NF_NAT_H323=m
> -CONFIG_NF_NAT_SIP=m
> -CONFIG_IP_NF_MANGLE=m
> -CONFIG_IP_NF_TARGET_CLUSTERIP=m
> -CONFIG_IP_NF_TARGET_ECN=m
> -CONFIG_IP_NF_TARGET_TTL=m
> -CONFIG_IP_NF_RAW=m
> -CONFIG_IP_NF_ARPTABLES=m
> -CONFIG_IP_NF_ARPFILTER=m
> -CONFIG_IP_NF_ARP_MANGLE=m
> -
> -#
> -# IPv6: Netfilter Configuration
> -#
> -CONFIG_NF_CONNTRACK_IPV6=m
> -CONFIG_IP6_NF_QUEUE=m
> -CONFIG_IP6_NF_IPTABLES=m
> -CONFIG_IP6_NF_MATCH_AH=m
> -CONFIG_IP6_NF_MATCH_EUI64=m
> -CONFIG_IP6_NF_MATCH_FRAG=m
> -CONFIG_IP6_NF_MATCH_OPTS=m
> -CONFIG_IP6_NF_MATCH_HL=m
> -CONFIG_IP6_NF_MATCH_IPV6HEADER=m
> -CONFIG_IP6_NF_MATCH_MH=m
> -CONFIG_IP6_NF_MATCH_RT=m
> -CONFIG_IP6_NF_TARGET_HL=m
> -CONFIG_IP6_NF_TARGET_LOG=m
> -CONFIG_IP6_NF_FILTER=m
> -CONFIG_IP6_NF_TARGET_REJECT=m
> -CONFIG_IP6_NF_MANGLE=m
> -CONFIG_IP6_NF_RAW=m
> -# CONFIG_BRIDGE_NF_EBTABLES is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_RDS is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -CONFIG_STP=m
> -CONFIG_BRIDGE=m
> -# CONFIG_NET_DSA is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -CONFIG_LLC=m
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_PHONET is not set
> -# CONFIG_IEEE802154 is not set
> -# CONFIG_NET_SCHED is not set
> -CONFIG_NET_CLS_ROUTE=y
> -# CONFIG_DCB is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -# CONFIG_IRDA is not set
> -CONFIG_BT=y
> -CONFIG_BT_L2CAP=y
> -CONFIG_BT_SCO=y
> -CONFIG_BT_RFCOMM=y
> -CONFIG_BT_RFCOMM_TTY=y
> -CONFIG_BT_BNEP=y
> -CONFIG_BT_BNEP_MC_FILTER=y
> -CONFIG_BT_BNEP_PROTO_FILTER=y
> -CONFIG_BT_HIDP=y
> -
> -#
> -# Bluetooth device drivers
> -#
> -CONFIG_BT_HCIBTUSB=m
> -CONFIG_BT_HCIBTSDIO=m
> -CONFIG_BT_HCIUART=y
> -CONFIG_BT_HCIUART_H4=y
> -# CONFIG_BT_HCIUART_BCSP is not set
> -# CONFIG_BT_HCIUART_LL is not set
> -CONFIG_BT_HCIBCM203X=m
> -CONFIG_BT_HCIBPA10X=m
> -CONFIG_BT_HCIBFUSB=m
> -CONFIG_BT_HCIVHCI=m
> -CONFIG_BT_MRVL=m
> -CONFIG_BT_MRVL_SDIO=m
> -# CONFIG_AF_RXRPC is not set
> -CONFIG_FIB_RULES=y
> -# CONFIG_WIRELESS is not set
> -# CONFIG_WIMAX is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -# CONFIG_DEVTMPFS is not set
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=m
> -CONFIG_FIRMWARE_IN_KERNEL=y
> -CONFIG_EXTRA_FIRMWARE=""
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_DEBUG_DEVRES is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -CONFIG_CONNECTOR=m
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_TESTS is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -# CONFIG_MTD_REDBOOT_PARTS is not set
> -# CONFIG_MTD_CMDLINE_PARTS is not set
> -# CONFIG_MTD_AFS_PARTS is not set
> -# CONFIG_MTD_AR7_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_HAVE_MTD_OTP=y
> -CONFIG_MTD_BLKDEVS=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -# CONFIG_MTD_JEDECPROBE is not set
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_NOSWAP=y
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> -CONFIG_MTD_CFI_GEOMETRY=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -# CONFIG_MTD_CFI_I2 is not set
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -CONFIG_MTD_OTP=y
> -CONFIG_MTD_CFI_INTELEXT=y
> -# CONFIG_MTD_CFI_AMDSTD is not set
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> -# CONFIG_MTD_PHYSMAP is not set
> -CONFIG_MTD_PXA2XX=y
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_DATAFLASH is not set
> -# CONFIG_MTD_M25P80 is not set
> -# CONFIG_MTD_SST25L is not set
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -# CONFIG_MTD_NAND is not set
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# LPDDR flash memory drivers
> -#
> -# CONFIG_MTD_LPDDR is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -CONFIG_BLK_DEV_LOOP=m
> -CONFIG_BLK_DEV_CRYPTOLOOP=m
> -CONFIG_BLK_DEV_NBD=m
> -# CONFIG_BLK_DEV_UB is not set
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_COUNT=16
> -CONFIG_BLK_DEV_RAM_SIZE=4096
> -# CONFIG_BLK_DEV_XIP is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -# CONFIG_MG_DISK is not set
> -# CONFIG_MISC_DEVICES is not set
> -CONFIG_HAVE_IDE=y
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -# CONFIG_SCSI is not set
> -# CONFIG_SCSI_DMA is not set
> -# CONFIG_SCSI_NETLINK is not set
> -# CONFIG_ATA is not set
> -# CONFIG_MD is not set
> -CONFIG_NETDEVICES=y
> -CONFIG_DUMMY=y
> -# CONFIG_BONDING is not set
> -# CONFIG_MACVLAN is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -# CONFIG_VETH is not set
> -# CONFIG_NET_ETHERNET is not set
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -# CONFIG_WLAN is not set
> -
> -#
> -# Enable WiMAX (Networking options) to see the WiMAX drivers
> -#
> -
> -#
> -# USB Network Adapters
> -#
> -# CONFIG_USB_CATC is not set
> -# CONFIG_USB_KAWETH is not set
> -# CONFIG_USB_PEGASUS is not set
> -# CONFIG_USB_RTL8150 is not set
> -# CONFIG_USB_USBNET is not set
> -# CONFIG_WAN is not set
> -CONFIG_PPP=m
> -CONFIG_PPP_MULTILINK=y
> -CONFIG_PPP_FILTER=y
> -CONFIG_PPP_ASYNC=m
> -CONFIG_PPP_SYNC_TTY=m
> -CONFIG_PPP_DEFLATE=m
> -CONFIG_PPP_BSDCOMP=m
> -# CONFIG_PPP_MPPE is not set
> -# CONFIG_PPPOE is not set
> -# CONFIG_PPPOL2TP is not set
> -# CONFIG_SLIP is not set
> -CONFIG_SLHC=m
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_ISDN is not set
> -# CONFIG_PHONE is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -# CONFIG_INPUT_MOUSEDEV is not set
> -# CONFIG_INPUT_JOYDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -# CONFIG_INPUT_APMPOWER is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -# CONFIG_KEYBOARD_ADP5588 is not set
> -# CONFIG_KEYBOARD_ATKBD is not set
> -# CONFIG_QT2160 is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -CONFIG_KEYBOARD_GPIO=y
> -# CONFIG_KEYBOARD_MATRIX is not set
> -# CONFIG_KEYBOARD_LM8323 is not set
> -# CONFIG_KEYBOARD_MAX7359 is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_KEYBOARD_OPENCORES is not set
> -CONFIG_KEYBOARD_PXA27x=y
> -# CONFIG_KEYBOARD_STOWAWAY is not set
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -# CONFIG_TOUCHSCREEN_ADS7846 is not set
> -# CONFIG_TOUCHSCREEN_AD7877 is not set
> -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
> -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
> -# CONFIG_TOUCHSCREEN_AD7879 is not set
> -# CONFIG_TOUCHSCREEN_EETI is not set
> -# CONFIG_TOUCHSCREEN_FUJITSU is not set
> -# CONFIG_TOUCHSCREEN_GUNZE is not set
> -# CONFIG_TOUCHSCREEN_ELO is not set
> -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
> -# CONFIG_TOUCHSCREEN_MCS5000 is not set
> -# CONFIG_TOUCHSCREEN_MTOUCH is not set
> -# CONFIG_TOUCHSCREEN_INEXIO is not set
> -# CONFIG_TOUCHSCREEN_MK712 is not set
> -# CONFIG_TOUCHSCREEN_PENMOUNT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
> -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
> -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
> -# CONFIG_TOUCHSCREEN_TSC2007 is not set
> -# CONFIG_TOUCHSCREEN_W90X900 is not set
> -CONFIG_TOUCHSCREEN_PCAP=y
> -CONFIG_INPUT_MISC=y
> -# CONFIG_INPUT_ATI_REMOTE is not set
> -# CONFIG_INPUT_ATI_REMOTE2 is not set
> -# CONFIG_INPUT_KEYSPAN_REMOTE is not set
> -# CONFIG_INPUT_POWERMATE is not set
> -# CONFIG_INPUT_YEALINK is not set
> -# CONFIG_INPUT_CM109 is not set
> -CONFIG_INPUT_UINPUT=y
> -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
> -CONFIG_INPUT_PCAP=y
> -
> -#
> -# Hardware I/O ports
> -#
> -# CONFIG_SERIO is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_CONSOLE_TRANSLATIONS=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -CONFIG_DEVKMEM=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -# CONFIG_SERIAL_MAX3100 is not set
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=8
> -# CONFIG_IPMI_HANDLER is not set
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_R3964 is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -CONFIG_I2C=y
> -CONFIG_I2C_BOARDINFO=y
> -CONFIG_I2C_COMPAT=y
> -CONFIG_I2C_CHARDEV=y
> -CONFIG_I2C_HELPER_AUTO=y
> -
> -#
> -# I2C Hardware Bus support
> -#
> -
> -#
> -# I2C system bus drivers (mostly embedded / system-on-chip)
> -#
> -# CONFIG_I2C_DESIGNWARE is not set
> -# CONFIG_I2C_GPIO is not set
> -# CONFIG_I2C_OCORES is not set
> -CONFIG_I2C_PXA=y
> -# CONFIG_I2C_PXA_SLAVE is not set
> -# CONFIG_I2C_SIMTEC is not set
> -
> -#
> -# External I2C/SMBus adapter drivers
> -#
> -# CONFIG_I2C_PARPORT_LIGHT is not set
> -# CONFIG_I2C_TAOS_EVM is not set
> -# CONFIG_I2C_TINY_USB is not set
> -
> -#
> -# Other I2C/SMBus bus drivers
> -#
> -# CONFIG_I2C_PCA_PLATFORM is not set
> -# CONFIG_I2C_STUB is not set
> -
> -#
> -# Miscellaneous I2C Chip support
> -#
> -# CONFIG_DS1682 is not set
> -# CONFIG_SENSORS_TSL2550 is not set
> -# CONFIG_I2C_DEBUG_CORE is not set
> -# CONFIG_I2C_DEBUG_ALGO is not set
> -# CONFIG_I2C_DEBUG_BUS is not set
> -# CONFIG_I2C_DEBUG_CHIP is not set
> -CONFIG_SPI=y
> -# CONFIG_SPI_DEBUG is not set
> -CONFIG_SPI_MASTER=y
> -
> -#
> -# SPI Master Controller Drivers
> -#
> -# CONFIG_SPI_BITBANG is not set
> -# CONFIG_SPI_GPIO is not set
> -CONFIG_SPI_PXA2XX=y
> -
> -#
> -# SPI Protocol Masters
> -#
> -# CONFIG_SPI_SPIDEV is not set
> -# CONFIG_SPI_TLE62X0 is not set
> -
> -#
> -# PPS support
> -#
> -# CONFIG_PPS is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -# CONFIG_DEBUG_GPIO is not set
> -CONFIG_GPIO_SYSFS=y
> -
> -#
> -# Memory mapped GPIO expanders:
> -#
> -
> -#
> -# I2C GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX732X is not set
> -# CONFIG_GPIO_PCA953X is not set
> -# CONFIG_GPIO_PCF857X is not set
> -
> -#
> -# PCI GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX7301 is not set
> -# CONFIG_GPIO_MCP23S08 is not set
> -# CONFIG_GPIO_MC33880 is not set
> -
> -#
> -# AC97 GPIO expanders:
> -#
> -# CONFIG_W1 is not set
> -CONFIG_POWER_SUPPLY=y
> -# CONFIG_POWER_SUPPLY_DEBUG is not set
> -# CONFIG_PDA_POWER is not set
> -# CONFIG_APM_POWER is not set
> -# CONFIG_BATTERY_DS2760 is not set
> -# CONFIG_BATTERY_DS2782 is not set
> -# CONFIG_BATTERY_BQ27x00 is not set
> -# CONFIG_BATTERY_MAX17040 is not set
> -# CONFIG_HWMON is not set
> -# CONFIG_THERMAL is not set
> -# CONFIG_WATCHDOG is not set
> -CONFIG_SSB_POSSIBLE=y
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_CORE is not set
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_MFD_ASIC3 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -# CONFIG_TPS65010 is not set
> -# CONFIG_TWL4030_CORE is not set
> -# CONFIG_MFD_TMIO is not set
> -# CONFIG_MFD_T7L66XB is not set
> -# CONFIG_MFD_TC6387XB is not set
> -# CONFIG_MFD_TC6393XB is not set
> -# CONFIG_PMIC_DA903X is not set
> -# CONFIG_MFD_WM8400 is not set
> -# CONFIG_MFD_WM831X is not set
> -# CONFIG_MFD_WM8350_I2C is not set
> -# CONFIG_MFD_PCF50633 is not set
> -# CONFIG_MFD_MC13783 is not set
> -# CONFIG_AB3100_CORE is not set
> -CONFIG_EZX_PCAP=y
> -CONFIG_REGULATOR=y
> -CONFIG_REGULATOR_DEBUG=y
> -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
> -CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
> -CONFIG_REGULATOR_USERSPACE_CONSUMER=y
> -# CONFIG_REGULATOR_BQ24022 is not set
> -# CONFIG_REGULATOR_MAX1586 is not set
> -# CONFIG_REGULATOR_LP3971 is not set
> -CONFIG_REGULATOR_PCAP=y
> -# CONFIG_REGULATOR_TPS65023 is not set
> -# CONFIG_REGULATOR_TPS6507X is not set
> -CONFIG_MEDIA_SUPPORT=y
> -
> -#
> -# Multimedia core support
> -#
> -CONFIG_VIDEO_DEV=y
> -CONFIG_VIDEO_V4L2_COMMON=y
> -CONFIG_VIDEO_ALLOW_V4L1=y
> -CONFIG_VIDEO_V4L1_COMPAT=y
> -# CONFIG_DVB_CORE is not set
> -CONFIG_VIDEO_MEDIA=y
> -
> -#
> -# Multimedia drivers
> -#
> -# CONFIG_MEDIA_ATTACH is not set
> -CONFIG_MEDIA_TUNER=y
> -CONFIG_MEDIA_TUNER_CUSTOMISE=y
> -# CONFIG_MEDIA_TUNER_SIMPLE is not set
> -# CONFIG_MEDIA_TUNER_TDA8290 is not set
> -# CONFIG_MEDIA_TUNER_TDA827X is not set
> -# CONFIG_MEDIA_TUNER_TDA18271 is not set
> -# CONFIG_MEDIA_TUNER_TDA9887 is not set
> -# CONFIG_MEDIA_TUNER_TEA5761 is not set
> -# CONFIG_MEDIA_TUNER_TEA5767 is not set
> -# CONFIG_MEDIA_TUNER_MT20XX is not set
> -# CONFIG_MEDIA_TUNER_MT2060 is not set
> -# CONFIG_MEDIA_TUNER_MT2266 is not set
> -# CONFIG_MEDIA_TUNER_MT2131 is not set
> -# CONFIG_MEDIA_TUNER_QT1010 is not set
> -# CONFIG_MEDIA_TUNER_XC2028 is not set
> -# CONFIG_MEDIA_TUNER_XC5000 is not set
> -# CONFIG_MEDIA_TUNER_MXL5005S is not set
> -# CONFIG_MEDIA_TUNER_MXL5007T is not set
> -# CONFIG_MEDIA_TUNER_MC44S803 is not set
> -CONFIG_VIDEO_V4L2=y
> -CONFIG_VIDEO_V4L1=y
> -CONFIG_VIDEOBUF_GEN=y
> -CONFIG_VIDEOBUF_DMA_SG=y
> -CONFIG_VIDEO_CAPTURE_DRIVERS=y
> -# CONFIG_VIDEO_ADV_DEBUG is not set
> -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
> -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
> -
> -#
> -# Encoders/decoders and other helper chips
> -#
> -
> -#
> -# Audio decoders
> -#
> -# CONFIG_VIDEO_TVAUDIO is not set
> -# CONFIG_VIDEO_TDA7432 is not set
> -# CONFIG_VIDEO_TDA9840 is not set
> -# CONFIG_VIDEO_TDA9875 is not set
> -# CONFIG_VIDEO_TEA6415C is not set
> -# CONFIG_VIDEO_TEA6420 is not set
> -# CONFIG_VIDEO_MSP3400 is not set
> -# CONFIG_VIDEO_CS5345 is not set
> -# CONFIG_VIDEO_CS53L32A is not set
> -# CONFIG_VIDEO_M52790 is not set
> -# CONFIG_VIDEO_TLV320AIC23B is not set
> -# CONFIG_VIDEO_WM8775 is not set
> -# CONFIG_VIDEO_WM8739 is not set
> -# CONFIG_VIDEO_VP27SMPX is not set
> -
> -#
> -# RDS decoders
> -#
> -# CONFIG_VIDEO_SAA6588 is not set
> -
> -#
> -# Video decoders
> -#
> -# CONFIG_VIDEO_ADV7180 is not set
> -# CONFIG_VIDEO_BT819 is not set
> -# CONFIG_VIDEO_BT856 is not set
> -# CONFIG_VIDEO_BT866 is not set
> -# CONFIG_VIDEO_KS0127 is not set
> -# CONFIG_VIDEO_OV7670 is not set
> -# CONFIG_VIDEO_MT9V011 is not set
> -# CONFIG_VIDEO_TCM825X is not set
> -# CONFIG_VIDEO_SAA7110 is not set
> -# CONFIG_VIDEO_SAA711X is not set
> -# CONFIG_VIDEO_SAA717X is not set
> -# CONFIG_VIDEO_SAA7191 is not set
> -# CONFIG_VIDEO_TVP514X is not set
> -# CONFIG_VIDEO_TVP5150 is not set
> -# CONFIG_VIDEO_VPX3220 is not set
> -
> -#
> -# Video and audio decoders
> -#
> -# CONFIG_VIDEO_CX25840 is not set
> -
> -#
> -# MPEG video encoders
> -#
> -# CONFIG_VIDEO_CX2341X is not set
> -
> -#
> -# Video encoders
> -#
> -# CONFIG_VIDEO_SAA7127 is not set
> -# CONFIG_VIDEO_SAA7185 is not set
> -# CONFIG_VIDEO_ADV7170 is not set
> -# CONFIG_VIDEO_ADV7175 is not set
> -# CONFIG_VIDEO_THS7303 is not set
> -# CONFIG_VIDEO_ADV7343 is not set
> -
> -#
> -# Video improvement chips
> -#
> -# CONFIG_VIDEO_UPD64031A is not set
> -# CONFIG_VIDEO_UPD64083 is not set
> -# CONFIG_VIDEO_VIVI is not set
> -# CONFIG_VIDEO_CPIA is not set
> -# CONFIG_VIDEO_CPIA2 is not set
> -# CONFIG_VIDEO_SAA5246A is not set
> -# CONFIG_VIDEO_SAA5249 is not set
> -CONFIG_SOC_CAMERA=y
> -# CONFIG_SOC_CAMERA_MT9M001 is not set
> -CONFIG_SOC_CAMERA_MT9M111=y
> -# CONFIG_SOC_CAMERA_MT9T031 is not set
> -# CONFIG_SOC_CAMERA_MT9V022 is not set
> -# CONFIG_SOC_CAMERA_TW9910 is not set
> -# CONFIG_SOC_CAMERA_PLATFORM is not set
> -# CONFIG_SOC_CAMERA_OV772X is not set
> -CONFIG_VIDEO_PXA27x=y
> -# CONFIG_VIDEO_SH_MOBILE_CEU is not set
> -# CONFIG_V4L_USB_DRIVERS is not set
> -CONFIG_RADIO_ADAPTERS=y
> -# CONFIG_I2C_SI4713 is not set
> -# CONFIG_RADIO_SI4713 is not set
> -# CONFIG_USB_DSBR is not set
> -# CONFIG_RADIO_SI470X is not set
> -# CONFIG_USB_MR800 is not set
> -CONFIG_RADIO_TEA5764=y
> -CONFIG_RADIO_TEA5764_XTAL=y
> -# CONFIG_DAB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -CONFIG_FB=y
> -# CONFIG_FIRMWARE_EDID is not set
> -# CONFIG_FB_DDC is not set
> -# CONFIG_FB_BOOT_VESA_SUPPORT is not set
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> -# CONFIG_FB_SYS_FILLRECT is not set
> -# CONFIG_FB_SYS_COPYAREA is not set
> -# CONFIG_FB_SYS_IMAGEBLIT is not set
> -# CONFIG_FB_FOREIGN_ENDIAN is not set
> -# CONFIG_FB_SYS_FOPS is not set
> -# CONFIG_FB_SVGALIB is not set
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -
> -#
> -# Frame buffer hardware drivers
> -#
> -# CONFIG_FB_UVESA is not set
> -# CONFIG_FB_S1D13XXX is not set
> -CONFIG_FB_PXA=y
> -CONFIG_FB_PXA_OVERLAY=y
> -# CONFIG_FB_PXA_SMARTPANEL is not set
> -CONFIG_FB_PXA_PARAMETERS=y
> -# CONFIG_FB_MBX is not set
> -# CONFIG_FB_W100 is not set
> -# CONFIG_FB_VIRTUAL is not set
> -# CONFIG_FB_METRONOME is not set
> -# CONFIG_FB_MB862XX is not set
> -# CONFIG_FB_BROADSHEET is not set
> -CONFIG_BACKLIGHT_LCD_SUPPORT=y
> -# CONFIG_LCD_CLASS_DEVICE is not set
> -CONFIG_BACKLIGHT_CLASS_DEVICE=y
> -CONFIG_BACKLIGHT_GENERIC=y
> -CONFIG_BACKLIGHT_PWM=y
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
> -CONFIG_FONTS=y
> -# CONFIG_FONT_8x8 is not set
> -# CONFIG_FONT_8x16 is not set
> -# CONFIG_FONT_6x11 is not set
> -# CONFIG_FONT_7x14 is not set
> -# CONFIG_FONT_PEARL_8x8 is not set
> -# CONFIG_FONT_ACORN_8x8 is not set
> -CONFIG_FONT_MINI_4x6=y
> -# CONFIG_FONT_SUN8x16 is not set
> -# CONFIG_FONT_SUN12x22 is not set
> -# CONFIG_FONT_10x18 is not set
> -# CONFIG_LOGO is not set
> -CONFIG_SOUND=y
> -CONFIG_SOUND_OSS_CORE=y
> -CONFIG_SOUND_OSS_CORE_PRECLAIM=y
> -CONFIG_SND=y
> -CONFIG_SND_TIMER=y
> -CONFIG_SND_PCM=y
> -CONFIG_SND_JACK=y
> -# CONFIG_SND_SEQUENCER is not set
> -CONFIG_SND_OSSEMUL=y
> -CONFIG_SND_MIXER_OSS=y
> -CONFIG_SND_PCM_OSS=y
> -CONFIG_SND_PCM_OSS_PLUGINS=y
> -# CONFIG_SND_HRTIMER is not set
> -# CONFIG_SND_DYNAMIC_MINORS is not set
> -CONFIG_SND_SUPPORT_OLD_API=y
> -CONFIG_SND_VERBOSE_PROCFS=y
> -# CONFIG_SND_VERBOSE_PRINTK is not set
> -# CONFIG_SND_DEBUG is not set
> -# CONFIG_SND_RAWMIDI_SEQ is not set
> -# CONFIG_SND_OPL3_LIB_SEQ is not set
> -# CONFIG_SND_OPL4_LIB_SEQ is not set
> -# CONFIG_SND_SBAWE_SEQ is not set
> -# CONFIG_SND_EMU10K1_SEQ is not set
> -# CONFIG_SND_DRIVERS is not set
> -# CONFIG_SND_ARM is not set
> -CONFIG_SND_PXA2XX_LIB=y
> -# CONFIG_SND_SPI is not set
> -# CONFIG_SND_USB is not set
> -CONFIG_SND_SOC=y
> -CONFIG_SND_PXA2XX_SOC=y
> -CONFIG_SND_SOC_I2C_AND_SPI=y
> -# CONFIG_SND_SOC_ALL_CODECS is not set
> -# CONFIG_SOUND_PRIME is not set
> -CONFIG_HID_SUPPORT=y
> -CONFIG_HID=y
> -# CONFIG_HIDRAW is not set
> -
> -#
> -# USB Input Devices
> -#
> -# CONFIG_USB_HID is not set
> -# CONFIG_HID_PID is not set
> -
> -#
> -# USB HID Boot Protocol drivers
> -#
> -# CONFIG_USB_KBD is not set
> -# CONFIG_USB_MOUSE is not set
> -
> -#
> -# Special HID drivers
> -#
> -CONFIG_HID_APPLE=m
> -# CONFIG_HID_WACOM is not set
> -CONFIG_USB_SUPPORT=y
> -CONFIG_USB_ARCH_HAS_HCD=y
> -CONFIG_USB_ARCH_HAS_OHCI=y
> -# CONFIG_USB_ARCH_HAS_EHCI is not set
> -CONFIG_USB=y
> -# CONFIG_USB_DEBUG is not set
> -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
> -
> -#
> -# Miscellaneous USB options
> -#
> -# CONFIG_USB_DEVICEFS is not set
> -# CONFIG_USB_DEVICE_CLASS is not set
> -# CONFIG_USB_DYNAMIC_MINORS is not set
> -# CONFIG_USB_SUSPEND is not set
> -# CONFIG_USB_OTG is not set
> -# CONFIG_USB_OTG_WHITELIST is not set
> -# CONFIG_USB_OTG_BLACKLIST_HUB is not set
> -# CONFIG_USB_MON is not set
> -# CONFIG_USB_WUSB is not set
> -# CONFIG_USB_WUSB_CBAF is not set
> -
> -#
> -# USB Host Controller Drivers
> -#
> -# CONFIG_USB_C67X00_HCD is not set
> -# CONFIG_USB_OXU210HP_HCD is not set
> -# CONFIG_USB_ISP116X_HCD is not set
> -# CONFIG_USB_ISP1760_HCD is not set
> -# CONFIG_USB_ISP1362_HCD is not set
> -CONFIG_USB_OHCI_HCD=y
> -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
> -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
> -CONFIG_USB_OHCI_LITTLE_ENDIAN=y
> -# CONFIG_USB_SL811_HCD is not set
> -# CONFIG_USB_R8A66597_HCD is not set
> -# CONFIG_USB_HWA_HCD is not set
> -# CONFIG_USB_MUSB_HDRC is not set
> -# CONFIG_USB_GADGET_MUSB_HDRC is not set
> -
> -#
> -# USB Device Class drivers
> -#
> -# CONFIG_USB_ACM is not set
> -# CONFIG_USB_PRINTER is not set
> -# CONFIG_USB_WDM is not set
> -# CONFIG_USB_TMC is not set
> -
> -#
> -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
> -#
> -
> -#
> -# also be needed; see USB_STORAGE Help for more info
> -#
> -# CONFIG_USB_LIBUSUAL is not set
> -
> -#
> -# USB Imaging devices
> -#
> -# CONFIG_USB_MDC800 is not set
> -
> -#
> -# USB port drivers
> -#
> -# CONFIG_USB_SERIAL is not set
> -
> -#
> -# USB Miscellaneous drivers
> -#
> -# CONFIG_USB_EMI62 is not set
> -# CONFIG_USB_EMI26 is not set
> -# CONFIG_USB_ADUTUX is not set
> -# CONFIG_USB_SEVSEG is not set
> -# CONFIG_USB_RIO500 is not set
> -# CONFIG_USB_LEGOTOWER is not set
> -# CONFIG_USB_LCD is not set
> -# CONFIG_USB_BERRY_CHARGE is not set
> -# CONFIG_USB_LED is not set
> -# CONFIG_USB_CYPRESS_CY7C63 is not set
> -# CONFIG_USB_CYTHERM is not set
> -# CONFIG_USB_IDMOUSE is not set
> -# CONFIG_USB_FTDI_ELAN is not set
> -# CONFIG_USB_APPLEDISPLAY is not set
> -# CONFIG_USB_LD is not set
> -# CONFIG_USB_TRANCEVIBRATOR is not set
> -# CONFIG_USB_IOWARRIOR is not set
> -# CONFIG_USB_TEST is not set
> -# CONFIG_USB_ISIGHTFW is not set
> -# CONFIG_USB_VST is not set
> -CONFIG_USB_GADGET=y
> -# CONFIG_USB_GADGET_DEBUG is not set
> -# CONFIG_USB_GADGET_DEBUG_FILES is not set
> -# CONFIG_USB_GADGET_DEBUG_FS is not set
> -CONFIG_USB_GADGET_VBUS_DRAW=2
> -CONFIG_USB_GADGET_SELECTED=y
> -# CONFIG_USB_GADGET_AT91 is not set
> -# CONFIG_USB_GADGET_ATMEL_USBA is not set
> -# CONFIG_USB_GADGET_FSL_USB2 is not set
> -# CONFIG_USB_GADGET_LH7A40X is not set
> -# CONFIG_USB_GADGET_OMAP is not set
> -# CONFIG_USB_GADGET_PXA25X is not set
> -# CONFIG_USB_GADGET_R8A66597 is not set
> -CONFIG_USB_GADGET_PXA27X=y
> -CONFIG_USB_PXA27X=y
> -# CONFIG_USB_GADGET_S3C_HSOTG is not set
> -# CONFIG_USB_GADGET_IMX is not set
> -# CONFIG_USB_GADGET_S3C2410 is not set
> -# CONFIG_USB_GADGET_M66592 is not set
> -# CONFIG_USB_GADGET_AMD5536UDC is not set
> -# CONFIG_USB_GADGET_FSL_QE is not set
> -# CONFIG_USB_GADGET_CI13XXX is not set
> -# CONFIG_USB_GADGET_NET2280 is not set
> -# CONFIG_USB_GADGET_GOKU is not set
> -# CONFIG_USB_GADGET_LANGWELL is not set
> -# CONFIG_USB_GADGET_DUMMY_HCD is not set
> -# CONFIG_USB_GADGET_DUALSPEED is not set
> -# CONFIG_USB_ZERO is not set
> -# CONFIG_USB_AUDIO is not set
> -CONFIG_USB_ETH=y
> -# CONFIG_USB_ETH_RNDIS is not set
> -# CONFIG_USB_ETH_EEM is not set
> -# CONFIG_USB_GADGETFS is not set
> -# CONFIG_USB_FILE_STORAGE is not set
> -# CONFIG_USB_G_SERIAL is not set
> -# CONFIG_USB_MIDI_GADGET is not set
> -# CONFIG_USB_G_PRINTER is not set
> -# CONFIG_USB_CDC_COMPOSITE is not set
> -
> -#
> -# OTG and related infrastructure
> -#
> -CONFIG_USB_OTG_UTILS=y
> -# CONFIG_USB_GPIO_VBUS is not set
> -# CONFIG_NOP_USB_XCEIV is not set
> -CONFIG_MMC=y
> -# CONFIG_MMC_DEBUG is not set
> -CONFIG_MMC_UNSAFE_RESUME=y
> -
> -#
> -# MMC/SD/SDIO Card Drivers
> -#
> -CONFIG_MMC_BLOCK=y
> -CONFIG_MMC_BLOCK_BOUNCE=y
> -CONFIG_SDIO_UART=m
> -# CONFIG_MMC_TEST is not set
> -
> -#
> -# MMC/SD/SDIO Host Controller Drivers
> -#
> -CONFIG_MMC_PXA=y
> -# CONFIG_MMC_SDHCI is not set
> -# CONFIG_MMC_AT91 is not set
> -# CONFIG_MMC_ATMELMCI is not set
> -CONFIG_MMC_SPI=y
> -# CONFIG_MEMSTICK is not set
> -CONFIG_NEW_LEDS=y
> -CONFIG_LEDS_CLASS=y
> -
> -#
> -# LED drivers
> -#
> -# CONFIG_LEDS_PCA9532 is not set
> -# CONFIG_LEDS_GPIO is not set
> -CONFIG_LEDS_LP3944=y
> -# CONFIG_LEDS_PCA955X is not set
> -# CONFIG_LEDS_DAC124S085 is not set
> -# CONFIG_LEDS_PWM is not set
> -# CONFIG_LEDS_BD2802 is not set
> -
> -#
> -# LED Triggers
> -#
> -CONFIG_LEDS_TRIGGERS=y
> -CONFIG_LEDS_TRIGGER_TIMER=y
> -CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> -CONFIG_LEDS_TRIGGER_BACKLIGHT=y
> -CONFIG_LEDS_TRIGGER_GPIO=y
> -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
> -
> -#
> -# iptables trigger is under Netfilter config (LED target)
> -#
> -# CONFIG_ACCESSIBILITY is not set
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_HCTOSYS=y
> -CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
> -# CONFIG_RTC_DEBUG is not set
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -# CONFIG_RTC_DRV_TEST is not set
> -
> -#
> -# I2C RTC drivers
> -#
> -# CONFIG_RTC_DRV_DS1307 is not set
> -# CONFIG_RTC_DRV_DS1374 is not set
> -# CONFIG_RTC_DRV_DS1672 is not set
> -# CONFIG_RTC_DRV_MAX6900 is not set
> -# CONFIG_RTC_DRV_RS5C372 is not set
> -# CONFIG_RTC_DRV_ISL1208 is not set
> -# CONFIG_RTC_DRV_X1205 is not set
> -# CONFIG_RTC_DRV_PCF8563 is not set
> -# CONFIG_RTC_DRV_PCF8583 is not set
> -# CONFIG_RTC_DRV_M41T80 is not set
> -# CONFIG_RTC_DRV_S35390A is not set
> -# CONFIG_RTC_DRV_FM3130 is not set
> -# CONFIG_RTC_DRV_RX8581 is not set
> -# CONFIG_RTC_DRV_RX8025 is not set
> -
> -#
> -# SPI RTC drivers
> -#
> -# CONFIG_RTC_DRV_M41T94 is not set
> -# CONFIG_RTC_DRV_DS1305 is not set
> -# CONFIG_RTC_DRV_DS1390 is not set
> -# CONFIG_RTC_DRV_MAX6902 is not set
> -# CONFIG_RTC_DRV_R9701 is not set
> -# CONFIG_RTC_DRV_RS5C348 is not set
> -# CONFIG_RTC_DRV_DS3234 is not set
> -# CONFIG_RTC_DRV_PCF2123 is not set
> -
> -#
> -# Platform RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_DS1286 is not set
> -# CONFIG_RTC_DRV_DS1511 is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_STK17TA8 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -# CONFIG_RTC_DRV_M48T35 is not set
> -# CONFIG_RTC_DRV_M48T59 is not set
> -# CONFIG_RTC_DRV_BQ4802 is not set
> -# CONFIG_RTC_DRV_V3020 is not set
> -
> -#
> -# on-CPU RTC drivers
> -#
> -# CONFIG_RTC_DRV_SA1100 is not set
> -# CONFIG_RTC_DRV_PXA is not set
> -CONFIG_RTC_DRV_PCAP=y
> -# CONFIG_DMADEVICES is not set
> -# CONFIG_AUXDISPLAY is not set
> -# CONFIG_UIO is not set
> -
> -#
> -# TI VLYNQ
> -#
> -# CONFIG_STAGING is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -CONFIG_EXT3_FS=m
> -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
> -CONFIG_EXT3_FS_XATTR=y
> -# CONFIG_EXT3_FS_POSIX_ACL is not set
> -# CONFIG_EXT3_FS_SECURITY is not set
> -# CONFIG_EXT4_FS is not set
> -CONFIG_JBD=m
> -# CONFIG_JBD_DEBUG is not set
> -CONFIG_FS_MBCACHE=m
> -CONFIG_REISERFS_FS=m
> -# CONFIG_REISERFS_CHECK is not set
> -# CONFIG_REISERFS_PROC_INFO is not set
> -CONFIG_REISERFS_FS_XATTR=y
> -CONFIG_REISERFS_FS_POSIX_ACL=y
> -CONFIG_REISERFS_FS_SECURITY=y
> -# CONFIG_JFS_FS is not set
> -CONFIG_FS_POSIX_ACL=y
> -CONFIG_XFS_FS=m
> -# CONFIG_XFS_QUOTA is not set
> -# CONFIG_XFS_POSIX_ACL is not set
> -# CONFIG_XFS_RT is not set
> -# CONFIG_XFS_DEBUG is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_BTRFS_FS is not set
> -# CONFIG_NILFS2_FS is not set
> -CONFIG_FILE_LOCKING=y
> -CONFIG_FSNOTIFY=y
> -CONFIG_DNOTIFY=y
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -CONFIG_AUTOFS_FS=y
> -CONFIG_AUTOFS4_FS=y
> -CONFIG_FUSE_FS=m
> -CONFIG_CUSE=m
> -
> -#
> -# Caches
> -#
> -# CONFIG_FSCACHE is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -CONFIG_ISO9660_FS=m
> -CONFIG_JOLIET=y
> -CONFIG_ZISOFS=y
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=m
> -CONFIG_MSDOS_FS=m
> -CONFIG_VFAT_FS=m
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_PROC_PAGE_MONITOR=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -CONFIG_MISC_FILESYSTEMS=y
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -CONFIG_JFFS2_FS=m
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
> -# CONFIG_JFFS2_SUMMARY is not set
> -# CONFIG_JFFS2_FS_XATTR is not set
> -CONFIG_JFFS2_COMPRESSION_OPTIONS=y
> -CONFIG_JFFS2_ZLIB=y
> -CONFIG_JFFS2_LZO=y
> -CONFIG_JFFS2_RTIME=y
> -CONFIG_JFFS2_RUBIN=y
> -# CONFIG_JFFS2_CMODE_NONE is not set
> -CONFIG_JFFS2_CMODE_PRIORITY=y
> -# CONFIG_JFFS2_CMODE_SIZE is not set
> -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
> -CONFIG_CRAMFS=m
> -CONFIG_SQUASHFS=m
> -# CONFIG_SQUASHFS_EMBEDDED is not set
> -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_OMFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -CONFIG_ROMFS_FS=m
> -CONFIG_ROMFS_BACKED_BY_BLOCK=y
> -# CONFIG_ROMFS_BACKED_BY_MTD is not set
> -# CONFIG_ROMFS_BACKED_BY_BOTH is not set
> -CONFIG_ROMFS_ON_BLOCK=y
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -CONFIG_NETWORK_FILESYSTEMS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -CONFIG_NFS_V3_ACL=y
> -# CONFIG_NFS_V4 is not set
> -# CONFIG_ROOT_NFS is not set
> -CONFIG_NFSD=m
> -CONFIG_NFSD_V2_ACL=y
> -CONFIG_NFSD_V3=y
> -CONFIG_NFSD_V3_ACL=y
> -# CONFIG_NFSD_V4 is not set
> -CONFIG_LOCKD=y
> -CONFIG_LOCKD_V4=y
> -CONFIG_EXPORTFS=m
> -CONFIG_NFS_ACL_SUPPORT=y
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=y
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -CONFIG_SMB_FS=m
> -# CONFIG_SMB_NLS_DEFAULT is not set
> -CONFIG_CIFS=m
> -CONFIG_CIFS_STATS=y
> -# CONFIG_CIFS_STATS2 is not set
> -CONFIG_CIFS_WEAK_PW_HASH=y
> -CONFIG_CIFS_XATTR=y
> -CONFIG_CIFS_POSIX=y
> -# CONFIG_CIFS_DEBUG2 is not set
> -# CONFIG_CIFS_EXPERIMENTAL is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -# CONFIG_PARTITION_ADVANCED is not set
> -CONFIG_MSDOS_PARTITION=y
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -CONFIG_NLS_CODEPAGE_437=m
> -CONFIG_NLS_CODEPAGE_737=m
> -CONFIG_NLS_CODEPAGE_775=m
> -CONFIG_NLS_CODEPAGE_850=m
> -CONFIG_NLS_CODEPAGE_852=m
> -CONFIG_NLS_CODEPAGE_855=m
> -CONFIG_NLS_CODEPAGE_857=m
> -CONFIG_NLS_CODEPAGE_860=m
> -CONFIG_NLS_CODEPAGE_861=m
> -CONFIG_NLS_CODEPAGE_862=m
> -CONFIG_NLS_CODEPAGE_863=m
> -CONFIG_NLS_CODEPAGE_864=m
> -CONFIG_NLS_CODEPAGE_865=m
> -CONFIG_NLS_CODEPAGE_866=m
> -CONFIG_NLS_CODEPAGE_869=m
> -CONFIG_NLS_CODEPAGE_936=m
> -CONFIG_NLS_CODEPAGE_950=m
> -CONFIG_NLS_CODEPAGE_932=m
> -CONFIG_NLS_CODEPAGE_949=m
> -CONFIG_NLS_CODEPAGE_874=m
> -CONFIG_NLS_ISO8859_8=m
> -CONFIG_NLS_CODEPAGE_1250=m
> -CONFIG_NLS_CODEPAGE_1251=m
> -CONFIG_NLS_ASCII=m
> -CONFIG_NLS_ISO8859_1=m
> -CONFIG_NLS_ISO8859_2=m
> -CONFIG_NLS_ISO8859_3=m
> -CONFIG_NLS_ISO8859_4=m
> -CONFIG_NLS_ISO8859_5=m
> -CONFIG_NLS_ISO8859_6=m
> -CONFIG_NLS_ISO8859_7=m
> -CONFIG_NLS_ISO8859_9=m
> -CONFIG_NLS_ISO8859_13=m
> -CONFIG_NLS_ISO8859_14=m
> -CONFIG_NLS_ISO8859_15=m
> -CONFIG_NLS_KOI8_R=m
> -CONFIG_NLS_KOI8_U=m
> -CONFIG_NLS_UTF8=m
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -CONFIG_PRINTK_TIME=y
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_FRAME_WARN=1024
> -# CONFIG_MAGIC_SYSRQ is not set
> -# CONFIG_STRIP_ASM_SYMS is not set
> -# CONFIG_UNUSED_SYMBOLS is not set
> -CONFIG_DEBUG_FS=y
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DEBUG_SHIRQ is not set
> -CONFIG_DETECT_SOFTLOCKUP=y
> -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
> -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
> -CONFIG_DETECT_HUNG_TASK=y
> -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
> -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
> -# CONFIG_SCHED_DEBUG is not set
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_TIMER_STATS is not set
> -# CONFIG_DEBUG_OBJECTS is not set
> -# CONFIG_DEBUG_SLAB is not set
> -# CONFIG_DEBUG_KMEMLEAK is not set
> -CONFIG_DEBUG_PREEMPT=y
> -CONFIG_DEBUG_RT_MUTEXES=y
> -CONFIG_DEBUG_PI_LIST=y
> -# CONFIG_RT_MUTEX_TESTER is not set
> -CONFIG_DEBUG_SPINLOCK=y
> -CONFIG_DEBUG_MUTEXES=y
> -CONFIG_DEBUG_LOCK_ALLOC=y
> -CONFIG_PROVE_LOCKING=y
> -CONFIG_LOCKDEP=y
> -# CONFIG_LOCK_STAT is not set
> -# CONFIG_DEBUG_LOCKDEP is not set
> -CONFIG_TRACE_IRQFLAGS=y
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -CONFIG_STACKTRACE=y
> -# CONFIG_DEBUG_KOBJECT is not set
> -CONFIG_DEBUG_BUGVERBOSE=y
> -# CONFIG_DEBUG_INFO is not set
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_WRITECOUNT is not set
> -# CONFIG_DEBUG_MEMORY_INIT is not set
> -# CONFIG_DEBUG_LIST is not set
> -# CONFIG_DEBUG_SG is not set
> -# CONFIG_DEBUG_NOTIFIERS is not set
> -# CONFIG_DEBUG_CREDENTIALS is not set
> -# CONFIG_BOOT_PRINTK_DELAY is not set
> -# CONFIG_RCU_TORTURE_TEST is not set
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -# CONFIG_BACKTRACE_SELF_TEST is not set
> -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
> -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
> -# CONFIG_FAULT_INJECTION is not set
> -# CONFIG_LATENCYTOP is not set
> -# CONFIG_SYSCTL_SYSCALL_CHECK is not set
> -# CONFIG_PAGE_POISONING is not set
> -CONFIG_HAVE_FUNCTION_TRACER=y
> -CONFIG_TRACING_SUPPORT=y
> -# CONFIG_FTRACE is not set
> -# CONFIG_DYNAMIC_DEBUG is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -# CONFIG_KGDB is not set
> -CONFIG_ARM_UNWIND=y
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> -# CONFIG_DEBUG_STACK_USAGE is not set
> -# CONFIG_DEBUG_LL is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITYFS is not set
> -# CONFIG_SECURITY_FILE_CAPABILITIES is not set
> -CONFIG_CRYPTO=y
> -
> -#
> -# Crypto core or helper
> -#
> -CONFIG_CRYPTO_ALGAPI=m
> -CONFIG_CRYPTO_ALGAPI2=m
> -CONFIG_CRYPTO_AEAD=m
> -CONFIG_CRYPTO_AEAD2=m
> -CONFIG_CRYPTO_BLKCIPHER=m
> -CONFIG_CRYPTO_BLKCIPHER2=m
> -CONFIG_CRYPTO_HASH=m
> -CONFIG_CRYPTO_HASH2=m
> -CONFIG_CRYPTO_RNG2=m
> -CONFIG_CRYPTO_PCOMP=m
> -CONFIG_CRYPTO_MANAGER=m
> -CONFIG_CRYPTO_MANAGER2=m
> -CONFIG_CRYPTO_GF128MUL=m
> -CONFIG_CRYPTO_NULL=m
> -CONFIG_CRYPTO_WORKQUEUE=m
> -CONFIG_CRYPTO_CRYPTD=m
> -CONFIG_CRYPTO_AUTHENC=m
> -CONFIG_CRYPTO_TEST=m
> -
> -#
> -# Authenticated Encryption with Associated Data
> -#
> -# CONFIG_CRYPTO_CCM is not set
> -# CONFIG_CRYPTO_GCM is not set
> -# CONFIG_CRYPTO_SEQIV is not set
> -
> -#
> -# Block modes
> -#
> -CONFIG_CRYPTO_CBC=m
> -# CONFIG_CRYPTO_CTR is not set
> -# CONFIG_CRYPTO_CTS is not set
> -CONFIG_CRYPTO_ECB=m
> -CONFIG_CRYPTO_LRW=m
> -CONFIG_CRYPTO_PCBC=m
> -CONFIG_CRYPTO_XTS=m
> -
> -#
> -# Hash modes
> -#
> -CONFIG_CRYPTO_HMAC=m
> -CONFIG_CRYPTO_XCBC=m
> -CONFIG_CRYPTO_VMAC=m
> -
> -#
> -# Digest
> -#
> -CONFIG_CRYPTO_CRC32C=m
> -CONFIG_CRYPTO_GHASH=m
> -CONFIG_CRYPTO_MD4=m
> -CONFIG_CRYPTO_MD5=m
> -CONFIG_CRYPTO_MICHAEL_MIC=m
> -# CONFIG_CRYPTO_RMD128 is not set
> -# CONFIG_CRYPTO_RMD160 is not set
> -# CONFIG_CRYPTO_RMD256 is not set
> -# CONFIG_CRYPTO_RMD320 is not set
> -CONFIG_CRYPTO_SHA1=m
> -CONFIG_CRYPTO_SHA256=m
> -CONFIG_CRYPTO_SHA512=m
> -CONFIG_CRYPTO_TGR192=m
> -# CONFIG_CRYPTO_WP512 is not set
> -
> -#
> -# Ciphers
> -#
> -CONFIG_CRYPTO_AES=m
> -# CONFIG_CRYPTO_ANUBIS is not set
> -CONFIG_CRYPTO_ARC4=m
> -CONFIG_CRYPTO_BLOWFISH=m
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -CONFIG_CRYPTO_CAST5=m
> -CONFIG_CRYPTO_CAST6=m
> -CONFIG_CRYPTO_DES=m
> -CONFIG_CRYPTO_FCRYPT=m
> -CONFIG_CRYPTO_KHAZAD=m
> -# CONFIG_CRYPTO_SALSA20 is not set
> -CONFIG_CRYPTO_SEED=m
> -CONFIG_CRYPTO_SERPENT=m
> -CONFIG_CRYPTO_TEA=m
> -CONFIG_CRYPTO_TWOFISH=m
> -CONFIG_CRYPTO_TWOFISH_COMMON=m
> -
> -#
> -# Compression
> -#
> -CONFIG_CRYPTO_DEFLATE=m
> -# CONFIG_CRYPTO_ZLIB is not set
> -# CONFIG_CRYPTO_LZO is not set
> -
> -#
> -# Random Number Generation
> -#
> -# CONFIG_CRYPTO_ANSI_CPRNG is not set
> -CONFIG_CRYPTO_HW=y
> -# CONFIG_BINARY_PRINTF is not set
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -CONFIG_GENERIC_FIND_LAST_BIT=y
> -CONFIG_CRC_CCITT=m
> -CONFIG_CRC16=y
> -# CONFIG_CRC_T10DIF is not set
> -CONFIG_CRC_ITU_T=y
> -CONFIG_CRC32=y
> -CONFIG_CRC7=y
> -CONFIG_LIBCRC32C=m
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=m
> -CONFIG_LZO_COMPRESS=m
> -CONFIG_LZO_DECOMPRESS=m
> -CONFIG_DECOMPRESS_GZIP=y
> -CONFIG_DECOMPRESS_BZIP2=y
> -CONFIG_DECOMPRESS_LZMA=y
> -CONFIG_TEXTSEARCH=y
> -CONFIG_TEXTSEARCH_KMP=m
> -CONFIG_TEXTSEARCH_BM=m
> -CONFIG_TEXTSEARCH_FSM=m
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> -CONFIG_NLATTR=y
> diff --git a/arch/arm/configs/h5000_defconfig b/arch/arm/configs/h5000_defconfig
> deleted file mode 100644
> index 5bb7372..0000000
> --- a/arch/arm/configs/h5000_defconfig
> +++ /dev/null
> @@ -1,995 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.27-rc6
> -# Tue Sep 16 16:13:48 2008
> -#
> -CONFIG_ARM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_MMU=y
> -# CONFIG_NO_IOPORT is not set
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -# CONFIG_ARCH_HAS_ILOG2_U32 is not set
> -# CONFIG_ARCH_HAS_ILOG2_U64 is not set
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ARCH_SUPPORTS_AOUT=y
> -CONFIG_ZONE_DMA=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=""
> -CONFIG_LOCALVERSION_AUTO=y
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -CONFIG_IKCONFIG=y
> -CONFIG_IKCONFIG_PROC=y
> -CONFIG_LOG_BUF_SHIFT=16
> -# CONFIG_CGROUPS is not set
> -CONFIG_GROUP_SCHED=y
> -CONFIG_FAIR_GROUP_SCHED=y
> -# CONFIG_RT_GROUP_SCHED is not set
> -CONFIG_USER_SCHED=y
> -# CONFIG_CGROUP_SCHED is not set
> -# CONFIG_SYSFS_DEPRECATED_V2 is not set
> -# CONFIG_RELAY is not set
> -# CONFIG_NAMESPACES is not set
> -# CONFIG_BLK_DEV_INITRD is not set
> -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
> -CONFIG_SYSCTL=y
> -CONFIG_EMBEDDED=y
> -# CONFIG_UID16 is not set
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_COMPAT_BRK=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_ANON_INODES=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -CONFIG_SHMEM=y
> -CONFIG_VM_EVENT_COUNTERS=y
> -CONFIG_SLAB=y
> -# CONFIG_SLUB is not set
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -# CONFIG_MARKERS is not set
> -CONFIG_HAVE_OPROFILE=y
> -# CONFIG_KPROBES is not set
> -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
> -# CONFIG_HAVE_IOREMAP_PROT is not set
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -# CONFIG_HAVE_ARCH_TRACEHOOK is not set
> -# CONFIG_HAVE_DMA_ATTRS is not set
> -# CONFIG_USE_GENERIC_SMP_HELPERS is not set
> -CONFIG_HAVE_CLK=y
> -# CONFIG_PROC_PAGE_MONITOR is not set
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_SLABINFO=y
> -CONFIG_RT_MUTEXES=y
> -# CONFIG_TINY_SHMEM is not set
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_MODULE_FORCE_UNLOAD=y
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -CONFIG_KMOD=y
> -CONFIG_BLOCK=y
> -# CONFIG_LBD is not set
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_LSF is not set
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_BLK_DEV_INTEGRITY is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_AS=y
> -CONFIG_IOSCHED_DEADLINE=y
> -# CONFIG_IOSCHED_CFQ is not set
> -CONFIG_DEFAULT_AS=y
> -# CONFIG_DEFAULT_DEADLINE is not set
> -# CONFIG_DEFAULT_CFQ is not set
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="anticipatory"
> -CONFIG_CLASSIC_RCU=y
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS7500 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_MSM7X00A is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -# CONFIG_ARCH_GUMSTIX is not set
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_ARCH_PXA_ESERIES is not set
> -CONFIG_MACH_H5000=y
> -# CONFIG_MACH_TRIZEPS4 is not set
> -# CONFIG_MACH_EM_X270 is not set
> -# CONFIG_MACH_COLIBRI is not set
> -# CONFIG_MACH_ZYLONITE is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_TAVOREVB is not set
> -# CONFIG_MACH_SAAR is not set
> -# CONFIG_MACH_ARMCORE is not set
> -# CONFIG_MACH_MAGICIAN is not set
> -# CONFIG_MACH_PCM027 is not set
> -# CONFIG_ARCH_PXA_PALM is not set
> -# CONFIG_PXA_EZX is not set
> -CONFIG_PXA25x=y
> -# CONFIG_PXA_PWM is not set
> -
> -#
> -# Boot options
> -#
> -
> -#
> -# Power management
> -#
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_PABRT_NOIFAR=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -# CONFIG_OUTER_CACHE is not set
> -# CONFIG_IWMMXT is not set
> -CONFIG_XSCALE_PMU=y
> -
> -#
> -# Bus support
> -#
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -# CONFIG_NO_HZ is not set
> -# CONFIG_HIGH_RES_TIMERS is not set
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -# CONFIG_PREEMPT is not set
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -CONFIG_ARCH_FLATMEM_HAS_HOLES=y
> -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -# CONFIG_SPARSEMEM_STATIC is not set
> -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
> -CONFIG_PAGEFLAGS_EXTENDED=y
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_RESOURCES_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=1
> -CONFIG_BOUNCE=y
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="keepinitrd"
> -# CONFIG_XIP_KERNEL is not set
> -CONFIG_KEXEC=y
> -CONFIG_ATAGS_PROC=y
> -
> -#
> -# CPU Frequency scaling
> -#
> -# CONFIG_CPU_FREQ is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -CONFIG_PM=y
> -# CONFIG_PM_DEBUG is not set
> -CONFIG_PM_SLEEP=y
> -CONFIG_SUSPEND=y
> -CONFIG_SUSPEND_FREEZER=y
> -CONFIG_APM_EMULATION=y
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_PACKET=y
> -CONFIG_PACKET_MMAP=y
> -CONFIG_UNIX=y
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -CONFIG_IP_MULTICAST=y
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -# CONFIG_IP_PNP_DHCP is not set
> -# CONFIG_IP_PNP_BOOTP is not set
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_IP_MROUTE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_BEET is not set
> -# CONFIG_INET_LRO is not set
> -# CONFIG_INET_DIAG is not set
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -# CONFIG_NETFILTER is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_NET_SCHED is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -# CONFIG_IRDA is not set
> -# CONFIG_BT is not set
> -# CONFIG_AF_RXRPC is not set
> -
> -#
> -# Wireless
> -#
> -# CONFIG_CFG80211 is not set
> -# CONFIG_WIRELESS_EXT is not set
> -# CONFIG_MAC80211 is not set
> -# CONFIG_IEEE80211 is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=y
> -CONFIG_FIRMWARE_IN_KERNEL=y
> -CONFIG_EXTRA_FIRMWARE=""
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_DEBUG_DEVRES is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -# CONFIG_CONNECTOR is not set
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -# CONFIG_MTD_REDBOOT_PARTS is not set
> -# CONFIG_MTD_CMDLINE_PARTS is not set
> -# CONFIG_MTD_AFS_PARTS is not set
> -# CONFIG_MTD_AR7_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -# CONFIG_MTD_CHAR is not set
> -CONFIG_MTD_BLKDEVS=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -# CONFIG_MTD_JEDECPROBE is not set
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_NOSWAP=y
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> -CONFIG_MTD_CFI_GEOMETRY=y
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -# CONFIG_MTD_OTP is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -# CONFIG_MTD_CFI_AMDSTD is not set
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> -CONFIG_MTD_PHYSMAP=y
> -CONFIG_MTD_PHYSMAP_START=0x8000000
> -CONFIG_MTD_PHYSMAP_LEN=0x0
> -CONFIG_MTD_PHYSMAP_BANKWIDTH=2
> -# CONFIG_MTD_PXA2XX is not set
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -# CONFIG_MTD_NAND is not set
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -# CONFIG_BLK_DEV_LOOP is not set
> -# CONFIG_BLK_DEV_NBD is not set
> -# CONFIG_BLK_DEV_RAM is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -CONFIG_MISC_DEVICES=y
> -# CONFIG_EEPROM_93CX6 is not set
> -# CONFIG_ENCLOSURE_SERVICES is not set
> -CONFIG_HAVE_IDE=y
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -# CONFIG_SCSI is not set
> -# CONFIG_SCSI_DMA is not set
> -# CONFIG_SCSI_NETLINK is not set
> -# CONFIG_ATA is not set
> -# CONFIG_MD is not set
> -# CONFIG_NETDEVICES is not set
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -# CONFIG_INPUT_MOUSEDEV is not set
> -# CONFIG_INPUT_JOYDEV is not set
> -# CONFIG_INPUT_EVDEV is not set
> -# CONFIG_INPUT_EVBUG is not set
> -# CONFIG_INPUT_APMPOWER is not set
> -
> -#
> -# Input Device Drivers
> -#
> -# CONFIG_INPUT_KEYBOARD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -# CONFIG_INPUT_TOUCHSCREEN is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -# CONFIG_SERIO is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_CONSOLE_TRANSLATIONS=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -CONFIG_DEVKMEM=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=32
> -# CONFIG_IPMI_HANDLER is not set
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_NVRAM is not set
> -# CONFIG_R3964 is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -# CONFIG_I2C is not set
> -# CONFIG_SPI is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -# CONFIG_DEBUG_GPIO is not set
> -# CONFIG_GPIO_SYSFS is not set
> -
> -#
> -# I2C GPIO expanders:
> -#
> -
> -#
> -# PCI GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -# CONFIG_W1 is not set
> -# CONFIG_POWER_SUPPLY is not set
> -# CONFIG_HWMON is not set
> -# CONFIG_WATCHDOG is not set
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -CONFIG_SSB_POSSIBLE=y
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_CORE is not set
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -# CONFIG_MFD_TMIO is not set
> -# CONFIG_MFD_T7L66XB is not set
> -# CONFIG_MFD_TC6387XB is not set
> -# CONFIG_MFD_TC6393XB is not set
> -
> -#
> -# Multimedia devices
> -#
> -
> -#
> -# Multimedia core support
> -#
> -# CONFIG_VIDEO_DEV is not set
> -# CONFIG_DVB_CORE is not set
> -# CONFIG_VIDEO_MEDIA is not set
> -
> -#
> -# Multimedia drivers
> -#
> -# CONFIG_DAB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -# CONFIG_FB is not set
> -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -# CONFIG_SOUND is not set
> -# CONFIG_HID_SUPPORT is not set
> -CONFIG_USB_SUPPORT=y
> -CONFIG_USB_ARCH_HAS_HCD=y
> -# CONFIG_USB_ARCH_HAS_OHCI is not set
> -# CONFIG_USB_ARCH_HAS_EHCI is not set
> -# CONFIG_USB is not set
> -# CONFIG_USB_OTG_WHITELIST is not set
> -# CONFIG_USB_OTG_BLACKLIST_HUB is not set
> -# CONFIG_USB_MUSB_HDRC is not set
> -# CONFIG_USB_GADGET_MUSB_HDRC is not set
> -
> -#
> -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
> -#
> -CONFIG_USB_GADGET=y
> -# CONFIG_USB_GADGET_DEBUG is not set
> -# CONFIG_USB_GADGET_DEBUG_FILES is not set
> -CONFIG_USB_GADGET_SELECTED=y
> -# CONFIG_USB_GADGET_AMD5536UDC is not set
> -# CONFIG_USB_GADGET_ATMEL_USBA is not set
> -# CONFIG_USB_GADGET_FSL_USB2 is not set
> -# CONFIG_USB_GADGET_NET2280 is not set
> -CONFIG_USB_GADGET_PXA25X=y
> -CONFIG_USB_PXA25X=y
> -CONFIG_USB_PXA25X_SMALL=y
> -# CONFIG_USB_GADGET_M66592 is not set
> -# CONFIG_USB_GADGET_PXA27X is not set
> -# CONFIG_USB_GADGET_GOKU is not set
> -# CONFIG_USB_GADGET_LH7A40X is not set
> -# CONFIG_USB_GADGET_OMAP is not set
> -# CONFIG_USB_GADGET_S3C2410 is not set
> -# CONFIG_USB_GADGET_AT91 is not set
> -# CONFIG_USB_GADGET_DUMMY_HCD is not set
> -# CONFIG_USB_GADGET_DUALSPEED is not set
> -# CONFIG_USB_ZERO is not set
> -CONFIG_USB_ETH=y
> -# CONFIG_USB_ETH_RNDIS is not set
> -# CONFIG_USB_GADGETFS is not set
> -# CONFIG_USB_FILE_STORAGE is not set
> -# CONFIG_USB_G_SERIAL is not set
> -# CONFIG_USB_MIDI_GADGET is not set
> -# CONFIG_USB_G_PRINTER is not set
> -# CONFIG_USB_CDC_COMPOSITE is not set
> -# CONFIG_MMC is not set
> -# CONFIG_NEW_LEDS is not set
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_HCTOSYS=y
> -CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
> -# CONFIG_RTC_DEBUG is not set
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -# CONFIG_RTC_DRV_TEST is not set
> -
> -#
> -# SPI RTC drivers
> -#
> -
> -#
> -# Platform RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_DS1511 is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_STK17TA8 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -# CONFIG_RTC_DRV_M48T59 is not set
> -# CONFIG_RTC_DRV_V3020 is not set
> -
> -#
> -# on-CPU RTC drivers
> -#
> -CONFIG_RTC_DRV_SA1100=y
> -# CONFIG_DMADEVICES is not set
> -
> -#
> -# Voltage and Current regulators
> -#
> -# CONFIG_REGULATOR is not set
> -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
> -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
> -# CONFIG_REGULATOR_BQ24022 is not set
> -# CONFIG_UIO is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -# CONFIG_EXT3_FS is not set
> -# CONFIG_EXT4DEV_FS is not set
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -# CONFIG_FS_POSIX_ACL is not set
> -# CONFIG_XFS_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -CONFIG_DNOTIFY=y
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -# CONFIG_MSDOS_FS is not set
> -# CONFIG_VFAT_FS is not set
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -
> -#
> -# Miscellaneous filesystems
> -#
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
> -# CONFIG_JFFS2_SUMMARY is not set
> -# CONFIG_JFFS2_FS_XATTR is not set
> -CONFIG_JFFS2_COMPRESSION_OPTIONS=y
> -CONFIG_JFFS2_ZLIB=y
> -# CONFIG_JFFS2_LZO is not set
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_JFFS2_CMODE_NONE is not set
> -CONFIG_JFFS2_CMODE_PRIORITY=y
> -# CONFIG_JFFS2_CMODE_SIZE is not set
> -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_OMFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -# CONFIG_NETWORK_FILESYSTEMS is not set
> -
> -#
> -# Partition Types
> -#
> -# CONFIG_PARTITION_ADVANCED is not set
> -CONFIG_MSDOS_PARTITION=y
> -# CONFIG_NLS is not set
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -CONFIG_PRINTK_TIME=y
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_FRAME_WARN=1024
> -# CONFIG_MAGIC_SYSRQ is not set
> -# CONFIG_UNUSED_SYMBOLS is not set
> -# CONFIG_DEBUG_FS is not set
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DEBUG_SHIRQ is not set
> -CONFIG_DETECT_SOFTLOCKUP=y
> -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
> -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
> -# CONFIG_SCHED_DEBUG is not set
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_TIMER_STATS is not set
> -# CONFIG_DEBUG_OBJECTS is not set
> -# CONFIG_DEBUG_SLAB is not set
> -# CONFIG_DEBUG_RT_MUTEXES is not set
> -# CONFIG_RT_MUTEX_TESTER is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -# CONFIG_DEBUG_MUTEXES is not set
> -# CONFIG_DEBUG_LOCK_ALLOC is not set
> -# CONFIG_PROVE_LOCKING is not set
> -# CONFIG_LOCK_STAT is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -# CONFIG_DEBUG_INFO is not set
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_WRITECOUNT is not set
> -# CONFIG_DEBUG_MEMORY_INIT is not set
> -# CONFIG_DEBUG_LIST is not set
> -# CONFIG_DEBUG_SG is not set
> -CONFIG_FRAME_POINTER=y
> -# CONFIG_BOOT_PRINTK_DELAY is not set
> -# CONFIG_RCU_TORTURE_TEST is not set
> -# CONFIG_BACKTRACE_SELF_TEST is not set
> -# CONFIG_FAULT_INJECTION is not set
> -# CONFIG_LATENCYTOP is not set
> -CONFIG_SYSCTL_SYSCALL_CHECK=y
> -CONFIG_HAVE_FTRACE=y
> -CONFIG_HAVE_DYNAMIC_FTRACE=y
> -# CONFIG_FTRACE is not set
> -# CONFIG_IRQSOFF_TRACER is not set
> -# CONFIG_SCHED_TRACER is not set
> -# CONFIG_CONTEXT_SWITCH_TRACER is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -# CONFIG_KGDB is not set
> -# CONFIG_DEBUG_USER is not set
> -# CONFIG_DEBUG_ERRORS is not set
> -# CONFIG_DEBUG_STACK_USAGE is not set
> -# CONFIG_DEBUG_LL is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITY_FILE_CAPABILITIES is not set
> -CONFIG_CRYPTO=y
> -
> -#
> -# Crypto core or helper
> -#
> -CONFIG_CRYPTO_ALGAPI=y
> -CONFIG_CRYPTO_HASH=y
> -CONFIG_CRYPTO_MANAGER=y
> -# CONFIG_CRYPTO_GF128MUL is not set
> -# CONFIG_CRYPTO_NULL is not set
> -# CONFIG_CRYPTO_CRYPTD is not set
> -# CONFIG_CRYPTO_AUTHENC is not set
> -# CONFIG_CRYPTO_TEST is not set
> -
> -#
> -# Authenticated Encryption with Associated Data
> -#
> -# CONFIG_CRYPTO_CCM is not set
> -# CONFIG_CRYPTO_GCM is not set
> -# CONFIG_CRYPTO_SEQIV is not set
> -
> -#
> -# Block modes
> -#
> -# CONFIG_CRYPTO_CBC is not set
> -# CONFIG_CRYPTO_CTR is not set
> -# CONFIG_CRYPTO_CTS is not set
> -# CONFIG_CRYPTO_ECB is not set
> -# CONFIG_CRYPTO_LRW is not set
> -# CONFIG_CRYPTO_PCBC is not set
> -# CONFIG_CRYPTO_XTS is not set
> -
> -#
> -# Hash modes
> -#
> -CONFIG_CRYPTO_HMAC=y
> -# CONFIG_CRYPTO_XCBC is not set
> -
> -#
> -# Digest
> -#
> -# CONFIG_CRYPTO_CRC32C is not set
> -# CONFIG_CRYPTO_MD4 is not set
> -CONFIG_CRYPTO_MD5=y
> -# CONFIG_CRYPTO_MICHAEL_MIC is not set
> -# CONFIG_CRYPTO_RMD128 is not set
> -# CONFIG_CRYPTO_RMD160 is not set
> -# CONFIG_CRYPTO_RMD256 is not set
> -# CONFIG_CRYPTO_RMD320 is not set
> -CONFIG_CRYPTO_SHA1=y
> -# CONFIG_CRYPTO_SHA256 is not set
> -# CONFIG_CRYPTO_SHA512 is not set
> -# CONFIG_CRYPTO_TGR192 is not set
> -# CONFIG_CRYPTO_WP512 is not set
> -
> -#
> -# Ciphers
> -#
> -# CONFIG_CRYPTO_AES is not set
> -# CONFIG_CRYPTO_ANUBIS is not set
> -# CONFIG_CRYPTO_ARC4 is not set
> -# CONFIG_CRYPTO_BLOWFISH is not set
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -# CONFIG_CRYPTO_CAST5 is not set
> -# CONFIG_CRYPTO_CAST6 is not set
> -CONFIG_CRYPTO_DES=y
> -# CONFIG_CRYPTO_FCRYPT is not set
> -# CONFIG_CRYPTO_KHAZAD is not set
> -# CONFIG_CRYPTO_SALSA20 is not set
> -# CONFIG_CRYPTO_SEED is not set
> -# CONFIG_CRYPTO_SERPENT is not set
> -# CONFIG_CRYPTO_TEA is not set
> -# CONFIG_CRYPTO_TWOFISH is not set
> -
> -#
> -# Compression
> -#
> -CONFIG_CRYPTO_DEFLATE=y
> -# CONFIG_CRYPTO_LZO is not set
> -# CONFIG_CRYPTO_HW is not set
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -# CONFIG_GENERIC_FIND_FIRST_BIT is not set
> -# CONFIG_GENERIC_FIND_NEXT_BIT is not set
> -CONFIG_CRC_CCITT=y
> -# CONFIG_CRC16 is not set
> -# CONFIG_CRC_T10DIF is not set
> -# CONFIG_CRC_ITU_T is not set
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_PLIST=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> diff --git a/arch/arm/configs/imote2_defconfig b/arch/arm/configs/imote2_defconfig
> deleted file mode 100644
> index 21f2bff..0000000
> --- a/arch/arm/configs/imote2_defconfig
> +++ /dev/null
> @@ -1,2039 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.34-rc2
> -# Thu Apr ?8 14:49:08 2010
> -#
> -CONFIG_ARM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_HAVE_PROC_CPU=y
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -CONFIG_ARCH_HAS_CPUFREQ=y
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_NEED_DMA_MAP_STATE=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -CONFIG_CONSTRUCTORS=y
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_LOCK_KERNEL=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=""
> -# CONFIG_LOCALVERSION_AUTO is not set
> -CONFIG_HAVE_KERNEL_GZIP=y
> -CONFIG_HAVE_KERNEL_LZO=y
> -CONFIG_KERNEL_GZIP=y
> -# CONFIG_KERNEL_BZIP2 is not set
> -# CONFIG_KERNEL_LZMA is not set
> -# CONFIG_KERNEL_LZO is not set
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -
> -#
> -# RCU Subsystem
> -#
> -CONFIG_TREE_RCU=y
> -# CONFIG_TREE_PREEMPT_RCU is not set
> -# CONFIG_TINY_RCU is not set
> -# CONFIG_RCU_TRACE is not set
> -CONFIG_RCU_FANOUT=32
> -# CONFIG_RCU_FANOUT_EXACT is not set
> -# CONFIG_TREE_RCU_TRACE is not set
> -# CONFIG_IKCONFIG is not set
> -CONFIG_LOG_BUF_SHIFT=14
> -# CONFIG_CGROUPS is not set
> -CONFIG_SYSFS_DEPRECATED=y
> -CONFIG_SYSFS_DEPRECATED_V2=y
> -# CONFIG_RELAY is not set
> -# CONFIG_NAMESPACES is not set
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_INITRAMFS_SOURCE=""
> -CONFIG_RD_GZIP=y
> -CONFIG_RD_BZIP2=y
> -CONFIG_RD_LZMA=y
> -# CONFIG_RD_LZO is not set
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -CONFIG_ANON_INODES=y
> -CONFIG_EMBEDDED=y
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -CONFIG_KALLSYMS_ALL=y
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -CONFIG_SHMEM=y
> -CONFIG_AIO=y
> -CONFIG_HAVE_PERF_EVENTS=y
> -CONFIG_PERF_USE_VMALLOC=y
> -
> -#
> -# Kernel Performance Events And Counters
> -#
> -# CONFIG_PERF_EVENTS is not set
> -# CONFIG_PERF_COUNTERS is not set
> -CONFIG_VM_EVENT_COUNTERS=y
> -# CONFIG_COMPAT_BRK is not set
> -CONFIG_SLAB=y
> -# CONFIG_SLUB is not set
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -CONFIG_HAVE_OPROFILE=y
> -# CONFIG_KPROBES is not set
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -CONFIG_HAVE_CLK=y
> -
> -#
> -# GCOV-based kernel profiling
> -#
> -# CONFIG_GCOV_KERNEL is not set
> -CONFIG_SLOW_WORK=y
> -# CONFIG_SLOW_WORK_DEBUG is not set
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_SLABINFO=y
> -CONFIG_RT_MUTEXES=y
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_MODULE_FORCE_UNLOAD=y
> -CONFIG_MODVERSIONS=y
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -CONFIG_BLOCK=y
> -# CONFIG_LBDAF is not set
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_BLK_DEV_INTEGRITY is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_DEADLINE=y
> -# CONFIG_IOSCHED_CFQ is not set
> -CONFIG_DEFAULT_DEADLINE=y
> -# CONFIG_DEFAULT_CFQ is not set
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="deadline"
> -# CONFIG_INLINE_SPIN_TRYLOCK is not set
> -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
> -# CONFIG_INLINE_SPIN_LOCK is not set
> -# CONFIG_INLINE_SPIN_LOCK_BH is not set
> -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
> -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
> -# CONFIG_INLINE_SPIN_UNLOCK is not set
> -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
> -# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
> -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
> -# CONFIG_INLINE_READ_TRYLOCK is not set
> -# CONFIG_INLINE_READ_LOCK is not set
> -# CONFIG_INLINE_READ_LOCK_BH is not set
> -# CONFIG_INLINE_READ_LOCK_IRQ is not set
> -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
> -# CONFIG_INLINE_READ_UNLOCK is not set
> -# CONFIG_INLINE_READ_UNLOCK_BH is not set
> -# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
> -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
> -# CONFIG_INLINE_WRITE_TRYLOCK is not set
> -# CONFIG_INLINE_WRITE_LOCK is not set
> -# CONFIG_INLINE_WRITE_LOCK_BH is not set
> -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
> -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
> -# CONFIG_INLINE_WRITE_UNLOCK is not set
> -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
> -# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
> -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
> -# CONFIG_MUTEX_SPIN_ON_OWNER is not set
> -CONFIG_FREEZER=y
> -
> -#
> -# System Type
> -#
> -CONFIG_MMU=y
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_BCMRING is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_GEMINI is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_STMP3XXX is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_DOVE is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_MMP is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_W90X900 is not set
> -# CONFIG_ARCH_NUC93X is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_MSM is not set
> -# CONFIG_ARCH_SHMOBILE is not set
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_S3C64XX is not set
> -# CONFIG_ARCH_S5P6440 is not set
> -# CONFIG_ARCH_S5P6442 is not set
> -# CONFIG_ARCH_S5PC1XX is not set
> -# CONFIG_ARCH_S5PV210 is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_U300 is not set
> -# CONFIG_ARCH_U8500 is not set
> -# CONFIG_ARCH_NOMADIK is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -
> -#
> -# Intel/Marvell Dev Platforms (sorted by hardware release time)
> -#
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_MACH_ZYLONITE300 is not set
> -# CONFIG_MACH_ZYLONITE320 is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_TAVOREVB is not set
> -# CONFIG_MACH_SAAR is not set
> -
> -#
> -# Third Party Dev Platforms (sorted by vendor name)
> -#
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_ARCH_VIPER is not set
> -# CONFIG_MACH_ARCOM_ZEUS is not set
> -# CONFIG_MACH_BALLOON3 is not set
> -# CONFIG_MACH_CSB726 is not set
> -# CONFIG_MACH_ARMCORE is not set
> -# CONFIG_MACH_EM_X270 is not set
> -# CONFIG_MACH_EXEDA is not set
> -# CONFIG_MACH_CM_X300 is not set
> -# CONFIG_MACH_CAPC7117 is not set
> -# CONFIG_ARCH_GUMSTIX is not set
> -CONFIG_MACH_INTELMOTE2=y
> -# CONFIG_MACH_STARGATE2 is not set
> -# CONFIG_MACH_XCEP is not set
> -# CONFIG_TRIZEPS_PXA is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_PCM027 is not set
> -# CONFIG_MACH_COLIBRI is not set
> -# CONFIG_MACH_COLIBRI300 is not set
> -# CONFIG_MACH_COLIBRI320 is not set
> -
> -#
> -# End-user Products (sorted by vendor name)
> -#
> -# CONFIG_MACH_H4700 is not set
> -# CONFIG_MACH_H5000 is not set
> -# CONFIG_MACH_HIMALAYA is not set
> -# CONFIG_MACH_MAGICIAN is not set
> -# CONFIG_MACH_MIOA701 is not set
> -# CONFIG_PXA_EZX is not set
> -# CONFIG_MACH_MP900C is not set
> -# CONFIG_ARCH_PXA_PALM is not set
> -# CONFIG_MACH_RAUMFELD_RC is not set
> -# CONFIG_MACH_RAUMFELD_CONNECTOR is not set
> -# CONFIG_MACH_RAUMFELD_SPEAKER is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_MACH_ICONTROL is not set
> -# CONFIG_ARCH_PXA_ESERIES is not set
> -CONFIG_PXA27x=y
> -CONFIG_PXA_SSP=y
> -CONFIG_PXA_HAVE_BOARD_IRQS=y
> -CONFIG_PLAT_PXA=y
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_PABRT_LEGACY=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -CONFIG_ARM_L1_CACHE_SHIFT=5
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -CONFIG_CPU_HAS_PMU=y
> -CONFIG_COMMON_CLKDEV=y
> -
> -#
> -# Bus support
> -#
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -CONFIG_NO_HZ=y
> -CONFIG_HIGH_RES_TIMERS=y
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -CONFIG_VMSPLIT_3G=y
> -# CONFIG_VMSPLIT_2G is not set
> -# CONFIG_VMSPLIT_1G is not set
> -CONFIG_PAGE_OFFSET=0xC0000000
> -# CONFIG_PREEMPT_NONE is not set
> -# CONFIG_PREEMPT_VOLUNTARY is not set
> -CONFIG_PREEMPT=y
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> -# CONFIG_HIGHMEM is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -CONFIG_PAGEFLAGS_EXTENDED=y
> -CONFIG_SPLIT_PTLOCK_CPUS=999999
> -# CONFIG_PHYS_ADDR_T_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=0
> -CONFIG_VIRT_TO_BUS=y
> -# CONFIG_KSM is not set
> -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
> -CONFIG_ALIGNMENT_TRAP=y
> -# CONFIG_UACCESS_WITH_MEMCPY is not set
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=jffs2 console=ttyS2,115200 mem=32M"
> -# CONFIG_XIP_KERNEL is not set
> -CONFIG_KEXEC=y
> -CONFIG_ATAGS_PROC=y
> -
> -#
> -# CPU Power Management
> -#
> -# CONFIG_CPU_FREQ is not set
> -# CONFIG_CPU_IDLE is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> -CONFIG_HAVE_AOUT=y
> -CONFIG_BINFMT_AOUT=m
> -CONFIG_BINFMT_MISC=m
> -
> -#
> -# Power management options
> -#
> -CONFIG_PM=y
> -# CONFIG_PM_DEBUG is not set
> -CONFIG_PM_SLEEP=y
> -CONFIG_SUSPEND=y
> -CONFIG_SUSPEND_FREEZER=y
> -CONFIG_APM_EMULATION=y
> -CONFIG_PM_RUNTIME=y
> -CONFIG_PM_OPS=y
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_PACKET=y
> -CONFIG_UNIX=y
> -CONFIG_XFRM=y
> -# CONFIG_XFRM_USER is not set
> -# CONFIG_XFRM_SUB_POLICY is not set
> -# CONFIG_XFRM_MIGRATE is not set
> -# CONFIG_XFRM_STATISTICS is not set
> -CONFIG_XFRM_IPCOMP=m
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -CONFIG_IP_PNP_BOOTP=y
> -CONFIG_IP_PNP_RARP=y
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -CONFIG_SYN_COOKIES=y
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -CONFIG_INET_TUNNEL=m
> -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_BEET is not set
> -# CONFIG_INET_LRO is not set
> -# CONFIG_INET_DIAG is not set
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -CONFIG_IPV6=m
> -# CONFIG_IPV6_PRIVACY is not set
> -# CONFIG_IPV6_ROUTER_PREF is not set
> -# CONFIG_IPV6_OPTIMISTIC_DAD is not set
> -CONFIG_INET6_AH=m
> -CONFIG_INET6_ESP=m
> -CONFIG_INET6_IPCOMP=m
> -CONFIG_IPV6_MIP6=m
> -CONFIG_INET6_XFRM_TUNNEL=m
> -CONFIG_INET6_TUNNEL=m
> -CONFIG_INET6_XFRM_MODE_TRANSPORT=m
> -CONFIG_INET6_XFRM_MODE_TUNNEL=m
> -CONFIG_INET6_XFRM_MODE_BEET=m
> -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
> -CONFIG_IPV6_SIT=m
> -# CONFIG_IPV6_SIT_6RD is not set
> -CONFIG_IPV6_NDISC_NODETYPE=y
> -CONFIG_IPV6_TUNNEL=m
> -CONFIG_IPV6_MULTIPLE_TABLES=y
> -CONFIG_IPV6_SUBTREES=y
> -# CONFIG_IPV6_MROUTE is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -CONFIG_NETFILTER=y
> -# CONFIG_NETFILTER_DEBUG is not set
> -CONFIG_NETFILTER_ADVANCED=y
> -CONFIG_BRIDGE_NETFILTER=y
> -
> -#
> -# Core Netfilter Configuration
> -#
> -CONFIG_NETFILTER_NETLINK=m
> -CONFIG_NETFILTER_NETLINK_QUEUE=m
> -CONFIG_NETFILTER_NETLINK_LOG=m
> -CONFIG_NF_CONNTRACK=m
> -CONFIG_NF_CT_ACCT=y
> -CONFIG_NF_CONNTRACK_MARK=y
> -CONFIG_NF_CONNTRACK_EVENTS=y
> -# CONFIG_NF_CT_PROTO_DCCP is not set
> -CONFIG_NF_CT_PROTO_GRE=m
> -CONFIG_NF_CT_PROTO_SCTP=m
> -CONFIG_NF_CT_PROTO_UDPLITE=m
> -CONFIG_NF_CONNTRACK_AMANDA=m
> -CONFIG_NF_CONNTRACK_FTP=m
> -CONFIG_NF_CONNTRACK_H323=m
> -CONFIG_NF_CONNTRACK_IRC=m
> -CONFIG_NF_CONNTRACK_NETBIOS_NS=m
> -CONFIG_NF_CONNTRACK_PPTP=m
> -CONFIG_NF_CONNTRACK_SANE=m
> -CONFIG_NF_CONNTRACK_SIP=m
> -CONFIG_NF_CONNTRACK_TFTP=m
> -CONFIG_NF_CT_NETLINK=m
> -# CONFIG_NETFILTER_TPROXY is not set
> -CONFIG_NETFILTER_XTABLES=m
> -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
> -# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
> -# CONFIG_NETFILTER_XT_TARGET_CT is not set
> -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
> -CONFIG_NETFILTER_XT_TARGET_HL=m
> -CONFIG_NETFILTER_XT_TARGET_LED=m
> -CONFIG_NETFILTER_XT_TARGET_MARK=m
> -CONFIG_NETFILTER_XT_TARGET_NFLOG=m
> -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
> -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
> -# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
> -# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
> -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
> -# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
> -# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
> -CONFIG_NETFILTER_XT_MATCH_COMMENT=m
> -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
> -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
> -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
> -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
> -CONFIG_NETFILTER_XT_MATCH_DCCP=m
> -CONFIG_NETFILTER_XT_MATCH_DSCP=m
> -CONFIG_NETFILTER_XT_MATCH_ESP=m
> -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
> -CONFIG_NETFILTER_XT_MATCH_HELPER=m
> -CONFIG_NETFILTER_XT_MATCH_HL=m
> -# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
> -CONFIG_NETFILTER_XT_MATCH_LENGTH=m
> -CONFIG_NETFILTER_XT_MATCH_LIMIT=m
> -CONFIG_NETFILTER_XT_MATCH_MAC=m
> -CONFIG_NETFILTER_XT_MATCH_MARK=m
> -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
> -# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
> -CONFIG_NETFILTER_XT_MATCH_POLICY=m
> -# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
> -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
> -CONFIG_NETFILTER_XT_MATCH_QUOTA=m
> -# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
> -CONFIG_NETFILTER_XT_MATCH_REALM=m
> -# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
> -CONFIG_NETFILTER_XT_MATCH_SCTP=m
> -CONFIG_NETFILTER_XT_MATCH_STATE=m
> -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
> -CONFIG_NETFILTER_XT_MATCH_STRING=m
> -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
> -CONFIG_NETFILTER_XT_MATCH_TIME=m
> -CONFIG_NETFILTER_XT_MATCH_U32=m
> -# CONFIG_NETFILTER_XT_MATCH_OSF is not set
> -# CONFIG_IP_VS is not set
> -
> -#
> -# IP: Netfilter Configuration
> -#
> -CONFIG_NF_DEFRAG_IPV4=m
> -CONFIG_NF_CONNTRACK_IPV4=m
> -CONFIG_NF_CONNTRACK_PROC_COMPAT=y
> -CONFIG_IP_NF_QUEUE=m
> -CONFIG_IP_NF_IPTABLES=m
> -CONFIG_IP_NF_MATCH_ADDRTYPE=m
> -CONFIG_IP_NF_MATCH_AH=m
> -CONFIG_IP_NF_MATCH_ECN=m
> -CONFIG_IP_NF_MATCH_TTL=m
> -CONFIG_IP_NF_FILTER=m
> -CONFIG_IP_NF_TARGET_REJECT=m
> -CONFIG_IP_NF_TARGET_LOG=m
> -CONFIG_IP_NF_TARGET_ULOG=m
> -CONFIG_NF_NAT=m
> -CONFIG_NF_NAT_NEEDED=y
> -CONFIG_IP_NF_TARGET_MASQUERADE=m
> -CONFIG_IP_NF_TARGET_NETMAP=m
> -CONFIG_IP_NF_TARGET_REDIRECT=m
> -CONFIG_NF_NAT_SNMP_BASIC=m
> -CONFIG_NF_NAT_PROTO_GRE=m
> -CONFIG_NF_NAT_PROTO_UDPLITE=m
> -CONFIG_NF_NAT_PROTO_SCTP=m
> -CONFIG_NF_NAT_FTP=m
> -CONFIG_NF_NAT_IRC=m
> -CONFIG_NF_NAT_TFTP=m
> -CONFIG_NF_NAT_AMANDA=m
> -CONFIG_NF_NAT_PPTP=m
> -CONFIG_NF_NAT_H323=m
> -CONFIG_NF_NAT_SIP=m
> -CONFIG_IP_NF_MANGLE=m
> -CONFIG_IP_NF_TARGET_CLUSTERIP=m
> -CONFIG_IP_NF_TARGET_ECN=m
> -CONFIG_IP_NF_TARGET_TTL=m
> -CONFIG_IP_NF_RAW=m
> -CONFIG_IP_NF_ARPTABLES=m
> -CONFIG_IP_NF_ARPFILTER=m
> -CONFIG_IP_NF_ARP_MANGLE=m
> -
> -#
> -# IPv6: Netfilter Configuration
> -#
> -CONFIG_NF_CONNTRACK_IPV6=m
> -CONFIG_IP6_NF_QUEUE=m
> -CONFIG_IP6_NF_IPTABLES=m
> -CONFIG_IP6_NF_MATCH_AH=m
> -CONFIG_IP6_NF_MATCH_EUI64=m
> -CONFIG_IP6_NF_MATCH_FRAG=m
> -CONFIG_IP6_NF_MATCH_OPTS=m
> -CONFIG_IP6_NF_MATCH_HL=m
> -CONFIG_IP6_NF_MATCH_IPV6HEADER=m
> -CONFIG_IP6_NF_MATCH_MH=m
> -CONFIG_IP6_NF_MATCH_RT=m
> -CONFIG_IP6_NF_TARGET_HL=m
> -CONFIG_IP6_NF_TARGET_LOG=m
> -CONFIG_IP6_NF_FILTER=m
> -CONFIG_IP6_NF_TARGET_REJECT=m
> -CONFIG_IP6_NF_MANGLE=m
> -CONFIG_IP6_NF_RAW=m
> -# CONFIG_BRIDGE_NF_EBTABLES is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_RDS is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -CONFIG_STP=m
> -CONFIG_BRIDGE=m
> -# CONFIG_BRIDGE_IGMP_SNOOPING is not set
> -# CONFIG_NET_DSA is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -CONFIG_LLC=m
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_PHONET is not set
> -CONFIG_IEEE802154=y
> -# CONFIG_NET_SCHED is not set
> -CONFIG_NET_CLS_ROUTE=y
> -# CONFIG_DCB is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -# CONFIG_IRDA is not set
> -# CONFIG_BT is not set
> -# CONFIG_AF_RXRPC is not set
> -CONFIG_FIB_RULES=y
> -# CONFIG_WIRELESS is not set
> -# CONFIG_WIMAX is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -CONFIG_DEVTMPFS=y
> -CONFIG_DEVTMPFS_MOUNT=y
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=m
> -CONFIG_FIRMWARE_IN_KERNEL=y
> -CONFIG_EXTRA_FIRMWARE=""
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_DEBUG_DEVRES is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -CONFIG_CONNECTOR=m
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_TESTS is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -# CONFIG_MTD_REDBOOT_PARTS is not set
> -CONFIG_MTD_CMDLINE_PARTS=y
> -CONFIG_MTD_AFS_PARTS=y
> -CONFIG_MTD_AR7_PARTS=y
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_HAVE_MTD_OTP=y
> -CONFIG_MTD_BLKDEVS=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -# CONFIG_MTD_JEDECPROBE is not set
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_NOSWAP=y
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> -CONFIG_MTD_CFI_GEOMETRY=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -# CONFIG_MTD_CFI_I2 is not set
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -CONFIG_MTD_OTP=y
> -CONFIG_MTD_CFI_INTELEXT=y
> -# CONFIG_MTD_CFI_AMDSTD is not set
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> -# CONFIG_MTD_PHYSMAP is not set
> -CONFIG_MTD_PXA2XX=y
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_DATAFLASH is not set
> -# CONFIG_MTD_M25P80 is not set
> -# CONFIG_MTD_SST25L is not set
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -# CONFIG_MTD_NAND is not set
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# LPDDR flash memory drivers
> -#
> -# CONFIG_MTD_LPDDR is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -CONFIG_BLK_DEV_LOOP=m
> -CONFIG_BLK_DEV_CRYPTOLOOP=m
> -# CONFIG_BLK_DEV_DRBD is not set
> -CONFIG_BLK_DEV_NBD=m
> -# CONFIG_BLK_DEV_UB is not set
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_COUNT=16
> -CONFIG_BLK_DEV_RAM_SIZE=4096
> -# CONFIG_BLK_DEV_XIP is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -# CONFIG_MG_DISK is not set
> -# CONFIG_MISC_DEVICES is not set
> -CONFIG_HAVE_IDE=y
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -CONFIG_SCSI_MOD=y
> -# CONFIG_RAID_ATTRS is not set
> -# CONFIG_SCSI is not set
> -# CONFIG_SCSI_DMA is not set
> -# CONFIG_SCSI_NETLINK is not set
> -# CONFIG_ATA is not set
> -# CONFIG_MD is not set
> -CONFIG_NETDEVICES=y
> -CONFIG_DUMMY=y
> -# CONFIG_BONDING is not set
> -# CONFIG_MACVLAN is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -# CONFIG_VETH is not set
> -# CONFIG_NET_ETHERNET is not set
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -# CONFIG_WLAN is not set
> -
> -#
> -# Enable WiMAX (Networking options) to see the WiMAX drivers
> -#
> -
> -#
> -# USB Network Adapters
> -#
> -# CONFIG_USB_CATC is not set
> -# CONFIG_USB_KAWETH is not set
> -# CONFIG_USB_PEGASUS is not set
> -# CONFIG_USB_RTL8150 is not set
> -# CONFIG_USB_USBNET is not set
> -# CONFIG_WAN is not set
> -CONFIG_IEEE802154_DRIVERS=y
> -# CONFIG_IEEE802154_FAKEHARD is not set
> -CONFIG_PPP=m
> -CONFIG_PPP_MULTILINK=y
> -CONFIG_PPP_FILTER=y
> -CONFIG_PPP_ASYNC=m
> -CONFIG_PPP_SYNC_TTY=m
> -CONFIG_PPP_DEFLATE=m
> -CONFIG_PPP_BSDCOMP=m
> -# CONFIG_PPP_MPPE is not set
> -# CONFIG_PPPOE is not set
> -# CONFIG_PPPOL2TP is not set
> -# CONFIG_SLIP is not set
> -CONFIG_SLHC=m
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_ISDN is not set
> -# CONFIG_PHONE is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -# CONFIG_INPUT_SPARSEKMAP is not set
> -
> -#
> -# Userland interfaces
> -#
> -# CONFIG_INPUT_MOUSEDEV is not set
> -# CONFIG_INPUT_JOYDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -# CONFIG_INPUT_APMPOWER is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -# CONFIG_KEYBOARD_ADP5588 is not set
> -# CONFIG_KEYBOARD_ATKBD is not set
> -# CONFIG_QT2160 is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -CONFIG_KEYBOARD_GPIO=y
> -# CONFIG_KEYBOARD_MATRIX is not set
> -# CONFIG_KEYBOARD_LM8323 is not set
> -# CONFIG_KEYBOARD_MAX7359 is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_KEYBOARD_OPENCORES is not set
> -CONFIG_KEYBOARD_PXA27x=y
> -# CONFIG_KEYBOARD_STOWAWAY is not set
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -# CONFIG_TOUCHSCREEN_ADS7846 is not set
> -# CONFIG_TOUCHSCREEN_AD7877 is not set
> -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
> -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
> -# CONFIG_TOUCHSCREEN_AD7879 is not set
> -CONFIG_TOUCHSCREEN_DA9034=y
> -# CONFIG_TOUCHSCREEN_DYNAPRO is not set
> -# CONFIG_TOUCHSCREEN_EETI is not set
> -# CONFIG_TOUCHSCREEN_FUJITSU is not set
> -# CONFIG_TOUCHSCREEN_GUNZE is not set
> -# CONFIG_TOUCHSCREEN_ELO is not set
> -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
> -# CONFIG_TOUCHSCREEN_MCS5000 is not set
> -# CONFIG_TOUCHSCREEN_MTOUCH is not set
> -# CONFIG_TOUCHSCREEN_INEXIO is not set
> -# CONFIG_TOUCHSCREEN_MK712 is not set
> -# CONFIG_TOUCHSCREEN_PENMOUNT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
> -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
> -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
> -# CONFIG_TOUCHSCREEN_TSC2007 is not set
> -# CONFIG_TOUCHSCREEN_W90X900 is not set
> -CONFIG_INPUT_MISC=y
> -# CONFIG_INPUT_ATI_REMOTE is not set
> -# CONFIG_INPUT_ATI_REMOTE2 is not set
> -# CONFIG_INPUT_KEYSPAN_REMOTE is not set
> -# CONFIG_INPUT_POWERMATE is not set
> -# CONFIG_INPUT_YEALINK is not set
> -# CONFIG_INPUT_CM109 is not set
> -CONFIG_INPUT_UINPUT=y
> -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -# CONFIG_SERIO is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_CONSOLE_TRANSLATIONS=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -CONFIG_DEVKMEM=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -# CONFIG_SERIAL_MAX3100 is not set
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -# CONFIG_SERIAL_TIMBERDALE is not set
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=8
> -# CONFIG_IPMI_HANDLER is not set
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_R3964 is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -CONFIG_I2C=y
> -CONFIG_I2C_BOARDINFO=y
> -CONFIG_I2C_COMPAT=y
> -CONFIG_I2C_CHARDEV=y
> -CONFIG_I2C_HELPER_AUTO=y
> -
> -#
> -# I2C Hardware Bus support
> -#
> -
> -#
> -# I2C system bus drivers (mostly embedded / system-on-chip)
> -#
> -# CONFIG_I2C_DESIGNWARE is not set
> -# CONFIG_I2C_GPIO is not set
> -# CONFIG_I2C_OCORES is not set
> -CONFIG_I2C_PXA=y
> -# CONFIG_I2C_PXA_SLAVE is not set
> -# CONFIG_I2C_SIMTEC is not set
> -# CONFIG_I2C_XILINX is not set
> -
> -#
> -# External I2C/SMBus adapter drivers
> -#
> -# CONFIG_I2C_PARPORT_LIGHT is not set
> -# CONFIG_I2C_TAOS_EVM is not set
> -# CONFIG_I2C_TINY_USB is not set
> -
> -#
> -# Other I2C/SMBus bus drivers
> -#
> -# CONFIG_I2C_PCA_PLATFORM is not set
> -# CONFIG_I2C_STUB is not set
> -# CONFIG_I2C_DEBUG_CORE is not set
> -# CONFIG_I2C_DEBUG_ALGO is not set
> -# CONFIG_I2C_DEBUG_BUS is not set
> -CONFIG_SPI=y
> -# CONFIG_SPI_DEBUG is not set
> -CONFIG_SPI_MASTER=y
> -
> -#
> -# SPI Master Controller Drivers
> -#
> -# CONFIG_SPI_BITBANG is not set
> -# CONFIG_SPI_GPIO is not set
> -CONFIG_SPI_PXA2XX=y
> -# CONFIG_SPI_XILINX is not set
> -# CONFIG_SPI_DESIGNWARE is not set
> -
> -#
> -# SPI Protocol Masters
> -#
> -# CONFIG_SPI_SPIDEV is not set
> -# CONFIG_SPI_TLE62X0 is not set
> -
> -#
> -# PPS support
> -#
> -# CONFIG_PPS is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -# CONFIG_DEBUG_GPIO is not set
> -CONFIG_GPIO_SYSFS=y
> -
> -#
> -# Memory mapped GPIO expanders:
> -#
> -# CONFIG_GPIO_IT8761E is not set
> -
> -#
> -# I2C GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX7300 is not set
> -# CONFIG_GPIO_MAX732X is not set
> -# CONFIG_GPIO_PCA953X is not set
> -# CONFIG_GPIO_PCF857X is not set
> -# CONFIG_GPIO_ADP5588 is not set
> -
> -#
> -# PCI GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX7301 is not set
> -# CONFIG_GPIO_MCP23S08 is not set
> -# CONFIG_GPIO_MC33880 is not set
> -
> -#
> -# AC97 GPIO expanders:
> -#
> -# CONFIG_W1 is not set
> -CONFIG_POWER_SUPPLY=y
> -# CONFIG_POWER_SUPPLY_DEBUG is not set
> -# CONFIG_PDA_POWER is not set
> -# CONFIG_APM_POWER is not set
> -# CONFIG_BATTERY_DS2760 is not set
> -# CONFIG_BATTERY_DS2782 is not set
> -# CONFIG_BATTERY_BQ27x00 is not set
> -# CONFIG_BATTERY_DA9030 is not set
> -# CONFIG_BATTERY_MAX17040 is not set
> -# CONFIG_HWMON is not set
> -# CONFIG_THERMAL is not set
> -# CONFIG_WATCHDOG is not set
> -CONFIG_SSB_POSSIBLE=y
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_CORE is not set
> -# CONFIG_MFD_88PM860X is not set
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_MFD_ASIC3 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -# CONFIG_HTC_I2CPLD is not set
> -# CONFIG_TPS65010 is not set
> -# CONFIG_TWL4030_CORE is not set
> -# CONFIG_MFD_TMIO is not set
> -# CONFIG_MFD_T7L66XB is not set
> -# CONFIG_MFD_TC6387XB is not set
> -# CONFIG_MFD_TC6393XB is not set
> -CONFIG_PMIC_DA903X=y
> -# CONFIG_PMIC_ADP5520 is not set
> -# CONFIG_MFD_MAX8925 is not set
> -# CONFIG_MFD_WM8400 is not set
> -# CONFIG_MFD_WM831X is not set
> -# CONFIG_MFD_WM8350_I2C is not set
> -# CONFIG_MFD_WM8994 is not set
> -# CONFIG_MFD_PCF50633 is not set
> -# CONFIG_MFD_MC13783 is not set
> -# CONFIG_AB3100_CORE is not set
> -# CONFIG_EZX_PCAP is not set
> -# CONFIG_AB4500_CORE is not set
> -CONFIG_REGULATOR=y
> -CONFIG_REGULATOR_DEBUG=y
> -# CONFIG_REGULATOR_DUMMY is not set
> -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
> -CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
> -CONFIG_REGULATOR_USERSPACE_CONSUMER=y
> -# CONFIG_REGULATOR_BQ24022 is not set
> -# CONFIG_REGULATOR_MAX1586 is not set
> -# CONFIG_REGULATOR_MAX8649 is not set
> -# CONFIG_REGULATOR_MAX8660 is not set
> -CONFIG_REGULATOR_DA903X=y
> -# CONFIG_REGULATOR_LP3971 is not set
> -# CONFIG_REGULATOR_TPS65023 is not set
> -# CONFIG_REGULATOR_TPS6507X is not set
> -CONFIG_MEDIA_SUPPORT=y
> -
> -#
> -# Multimedia core support
> -#
> -CONFIG_VIDEO_DEV=y
> -CONFIG_VIDEO_V4L2_COMMON=y
> -CONFIG_VIDEO_ALLOW_V4L1=y
> -CONFIG_VIDEO_V4L1_COMPAT=y
> -# CONFIG_DVB_CORE is not set
> -CONFIG_VIDEO_MEDIA=y
> -
> -#
> -# Multimedia drivers
> -#
> -CONFIG_IR_CORE=y
> -CONFIG_VIDEO_IR=y
> -# CONFIG_MEDIA_ATTACH is not set
> -CONFIG_MEDIA_TUNER=y
> -CONFIG_MEDIA_TUNER_CUSTOMISE=y
> -# CONFIG_MEDIA_TUNER_SIMPLE is not set
> -# CONFIG_MEDIA_TUNER_TDA8290 is not set
> -# CONFIG_MEDIA_TUNER_TDA827X is not set
> -# CONFIG_MEDIA_TUNER_TDA18271 is not set
> -# CONFIG_MEDIA_TUNER_TDA9887 is not set
> -# CONFIG_MEDIA_TUNER_TEA5761 is not set
> -# CONFIG_MEDIA_TUNER_TEA5767 is not set
> -# CONFIG_MEDIA_TUNER_MT20XX is not set
> -# CONFIG_MEDIA_TUNER_MT2060 is not set
> -# CONFIG_MEDIA_TUNER_MT2266 is not set
> -# CONFIG_MEDIA_TUNER_MT2131 is not set
> -# CONFIG_MEDIA_TUNER_QT1010 is not set
> -# CONFIG_MEDIA_TUNER_XC2028 is not set
> -# CONFIG_MEDIA_TUNER_XC5000 is not set
> -# CONFIG_MEDIA_TUNER_MXL5005S is not set
> -# CONFIG_MEDIA_TUNER_MXL5007T is not set
> -# CONFIG_MEDIA_TUNER_MC44S803 is not set
> -CONFIG_MEDIA_TUNER_MAX2165=m
> -CONFIG_VIDEO_V4L2=y
> -CONFIG_VIDEO_V4L1=y
> -CONFIG_VIDEOBUF_GEN=y
> -CONFIG_VIDEOBUF_DMA_SG=y
> -CONFIG_VIDEO_CAPTURE_DRIVERS=y
> -# CONFIG_VIDEO_ADV_DEBUG is not set
> -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
> -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
> -CONFIG_VIDEO_IR_I2C=y
> -
> -#
> -# Encoders/decoders and other helper chips
> -#
> -
> -#
> -# Audio decoders
> -#
> -# CONFIG_VIDEO_TVAUDIO is not set
> -# CONFIG_VIDEO_TDA7432 is not set
> -# CONFIG_VIDEO_TDA9840 is not set
> -# CONFIG_VIDEO_TDA9875 is not set
> -# CONFIG_VIDEO_TEA6415C is not set
> -# CONFIG_VIDEO_TEA6420 is not set
> -# CONFIG_VIDEO_MSP3400 is not set
> -# CONFIG_VIDEO_CS5345 is not set
> -# CONFIG_VIDEO_CS53L32A is not set
> -# CONFIG_VIDEO_M52790 is not set
> -# CONFIG_VIDEO_TLV320AIC23B is not set
> -# CONFIG_VIDEO_WM8775 is not set
> -# CONFIG_VIDEO_WM8739 is not set
> -# CONFIG_VIDEO_VP27SMPX is not set
> -
> -#
> -# RDS decoders
> -#
> -# CONFIG_VIDEO_SAA6588 is not set
> -
> -#
> -# Video decoders
> -#
> -# CONFIG_VIDEO_ADV7180 is not set
> -# CONFIG_VIDEO_BT819 is not set
> -# CONFIG_VIDEO_BT856 is not set
> -# CONFIG_VIDEO_BT866 is not set
> -# CONFIG_VIDEO_KS0127 is not set
> -# CONFIG_VIDEO_OV7670 is not set
> -# CONFIG_VIDEO_MT9V011 is not set
> -# CONFIG_VIDEO_TCM825X is not set
> -# CONFIG_VIDEO_SAA7110 is not set
> -# CONFIG_VIDEO_SAA711X is not set
> -# CONFIG_VIDEO_SAA717X is not set
> -# CONFIG_VIDEO_SAA7191 is not set
> -# CONFIG_VIDEO_TVP514X is not set
> -# CONFIG_VIDEO_TVP5150 is not set
> -# CONFIG_VIDEO_TVP7002 is not set
> -# CONFIG_VIDEO_VPX3220 is not set
> -
> -#
> -# Video and audio decoders
> -#
> -# CONFIG_VIDEO_CX25840 is not set
> -
> -#
> -# MPEG video encoders
> -#
> -# CONFIG_VIDEO_CX2341X is not set
> -
> -#
> -# Video encoders
> -#
> -# CONFIG_VIDEO_SAA7127 is not set
> -# CONFIG_VIDEO_SAA7185 is not set
> -# CONFIG_VIDEO_ADV7170 is not set
> -# CONFIG_VIDEO_ADV7175 is not set
> -# CONFIG_VIDEO_THS7303 is not set
> -# CONFIG_VIDEO_ADV7343 is not set
> -
> -#
> -# Video improvement chips
> -#
> -# CONFIG_VIDEO_UPD64031A is not set
> -# CONFIG_VIDEO_UPD64083 is not set
> -# CONFIG_VIDEO_VIVI is not set
> -# CONFIG_VIDEO_CPIA is not set
> -# CONFIG_VIDEO_CPIA2 is not set
> -# CONFIG_VIDEO_SAA5246A is not set
> -# CONFIG_VIDEO_SAA5249 is not set
> -CONFIG_SOC_CAMERA=y
> -# CONFIG_SOC_CAMERA_MT9M001 is not set
> -CONFIG_SOC_CAMERA_MT9M111=y
> -# CONFIG_SOC_CAMERA_MT9T031 is not set
> -# CONFIG_SOC_CAMERA_MT9T112 is not set
> -# CONFIG_SOC_CAMERA_MT9V022 is not set
> -# CONFIG_SOC_CAMERA_RJ54N1 is not set
> -# CONFIG_SOC_CAMERA_TW9910 is not set
> -# CONFIG_SOC_CAMERA_PLATFORM is not set
> -# CONFIG_SOC_CAMERA_OV772X is not set
> -# CONFIG_SOC_CAMERA_OV9640 is not set
> -CONFIG_VIDEO_PXA27x=y
> -# CONFIG_VIDEO_SH_MOBILE_CEU is not set
> -# CONFIG_V4L_USB_DRIVERS is not set
> -# CONFIG_RADIO_ADAPTERS is not set
> -# CONFIG_DAB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -CONFIG_FB=y
> -# CONFIG_FIRMWARE_EDID is not set
> -# CONFIG_FB_DDC is not set
> -# CONFIG_FB_BOOT_VESA_SUPPORT is not set
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> -# CONFIG_FB_SYS_FILLRECT is not set
> -# CONFIG_FB_SYS_COPYAREA is not set
> -# CONFIG_FB_SYS_IMAGEBLIT is not set
> -# CONFIG_FB_FOREIGN_ENDIAN is not set
> -# CONFIG_FB_SYS_FOPS is not set
> -# CONFIG_FB_SVGALIB is not set
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -
> -#
> -# Frame buffer hardware drivers
> -#
> -# CONFIG_FB_UVESA is not set
> -# CONFIG_FB_S1D13XXX is not set
> -CONFIG_FB_PXA=y
> -CONFIG_FB_PXA_OVERLAY=y
> -# CONFIG_FB_PXA_SMARTPANEL is not set
> -CONFIG_FB_PXA_PARAMETERS=y
> -# CONFIG_FB_MBX is not set
> -# CONFIG_FB_W100 is not set
> -# CONFIG_FB_VIRTUAL is not set
> -# CONFIG_FB_METRONOME is not set
> -# CONFIG_FB_MB862XX is not set
> -# CONFIG_FB_BROADSHEET is not set
> -CONFIG_BACKLIGHT_LCD_SUPPORT=y
> -# CONFIG_LCD_CLASS_DEVICE is not set
> -CONFIG_BACKLIGHT_CLASS_DEVICE=y
> -CONFIG_BACKLIGHT_GENERIC=y
> -# CONFIG_BACKLIGHT_DA903X is not set
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
> -CONFIG_FONTS=y
> -# CONFIG_FONT_8x8 is not set
> -# CONFIG_FONT_8x16 is not set
> -# CONFIG_FONT_6x11 is not set
> -# CONFIG_FONT_7x14 is not set
> -# CONFIG_FONT_PEARL_8x8 is not set
> -# CONFIG_FONT_ACORN_8x8 is not set
> -CONFIG_FONT_MINI_4x6=y
> -# CONFIG_FONT_SUN8x16 is not set
> -# CONFIG_FONT_SUN12x22 is not set
> -# CONFIG_FONT_10x18 is not set
> -# CONFIG_LOGO is not set
> -CONFIG_SOUND=y
> -CONFIG_SOUND_OSS_CORE=y
> -CONFIG_SOUND_OSS_CORE_PRECLAIM=y
> -CONFIG_SND=y
> -CONFIG_SND_TIMER=y
> -CONFIG_SND_PCM=y
> -CONFIG_SND_JACK=y
> -# CONFIG_SND_SEQUENCER is not set
> -CONFIG_SND_OSSEMUL=y
> -CONFIG_SND_MIXER_OSS=y
> -CONFIG_SND_PCM_OSS=y
> -CONFIG_SND_PCM_OSS_PLUGINS=y
> -# CONFIG_SND_HRTIMER is not set
> -# CONFIG_SND_DYNAMIC_MINORS is not set
> -CONFIG_SND_SUPPORT_OLD_API=y
> -CONFIG_SND_VERBOSE_PROCFS=y
> -# CONFIG_SND_VERBOSE_PRINTK is not set
> -# CONFIG_SND_DEBUG is not set
> -# CONFIG_SND_RAWMIDI_SEQ is not set
> -# CONFIG_SND_OPL3_LIB_SEQ is not set
> -# CONFIG_SND_OPL4_LIB_SEQ is not set
> -# CONFIG_SND_SBAWE_SEQ is not set
> -# CONFIG_SND_EMU10K1_SEQ is not set
> -# CONFIG_SND_DRIVERS is not set
> -# CONFIG_SND_ARM is not set
> -CONFIG_SND_PXA2XX_LIB=y
> -# CONFIG_SND_SPI is not set
> -# CONFIG_SND_USB is not set
> -CONFIG_SND_SOC=y
> -CONFIG_SND_PXA2XX_SOC=y
> -# CONFIG_SND_PXA2XX_SOC_IMOTE2 is not set
> -CONFIG_SND_SOC_I2C_AND_SPI=y
> -# CONFIG_SND_SOC_ALL_CODECS is not set
> -# CONFIG_SOUND_PRIME is not set
> -CONFIG_HID_SUPPORT=y
> -CONFIG_HID=y
> -# CONFIG_HIDRAW is not set
> -
> -#
> -# USB Input Devices
> -#
> -# CONFIG_USB_HID is not set
> -# CONFIG_HID_PID is not set
> -
> -#
> -# USB HID Boot Protocol drivers
> -#
> -# CONFIG_USB_KBD is not set
> -# CONFIG_USB_MOUSE is not set
> -
> -#
> -# Special HID drivers
> -#
> -CONFIG_USB_SUPPORT=y
> -CONFIG_USB_ARCH_HAS_HCD=y
> -CONFIG_USB_ARCH_HAS_OHCI=y
> -# CONFIG_USB_ARCH_HAS_EHCI is not set
> -CONFIG_USB=y
> -# CONFIG_USB_DEBUG is not set
> -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
> -
> -#
> -# Miscellaneous USB options
> -#
> -# CONFIG_USB_DEVICEFS is not set
> -# CONFIG_USB_DEVICE_CLASS is not set
> -# CONFIG_USB_DYNAMIC_MINORS is not set
> -# CONFIG_USB_SUSPEND is not set
> -# CONFIG_USB_OTG is not set
> -# CONFIG_USB_OTG_WHITELIST is not set
> -# CONFIG_USB_OTG_BLACKLIST_HUB is not set
> -# CONFIG_USB_MON is not set
> -# CONFIG_USB_WUSB is not set
> -# CONFIG_USB_WUSB_CBAF is not set
> -
> -#
> -# USB Host Controller Drivers
> -#
> -# CONFIG_USB_C67X00_HCD is not set
> -# CONFIG_USB_OXU210HP_HCD is not set
> -# CONFIG_USB_ISP116X_HCD is not set
> -# CONFIG_USB_ISP1760_HCD is not set
> -# CONFIG_USB_ISP1362_HCD is not set
> -CONFIG_USB_OHCI_HCD=y
> -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
> -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
> -CONFIG_USB_OHCI_LITTLE_ENDIAN=y
> -# CONFIG_USB_SL811_HCD is not set
> -# CONFIG_USB_R8A66597_HCD is not set
> -# CONFIG_USB_HWA_HCD is not set
> -# CONFIG_USB_MUSB_HDRC is not set
> -# CONFIG_USB_GADGET_MUSB_HDRC is not set
> -
> -#
> -# USB Device Class drivers
> -#
> -# CONFIG_USB_ACM is not set
> -# CONFIG_USB_PRINTER is not set
> -# CONFIG_USB_WDM is not set
> -# CONFIG_USB_TMC is not set
> -
> -#
> -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
> -#
> -
> -#
> -# also be needed; see USB_STORAGE Help for more info
> -#
> -# CONFIG_USB_LIBUSUAL is not set
> -
> -#
> -# USB Imaging devices
> -#
> -# CONFIG_USB_MDC800 is not set
> -
> -#
> -# USB port drivers
> -#
> -# CONFIG_USB_SERIAL is not set
> -
> -#
> -# USB Miscellaneous drivers
> -#
> -# CONFIG_USB_EMI62 is not set
> -# CONFIG_USB_EMI26 is not set
> -# CONFIG_USB_ADUTUX is not set
> -# CONFIG_USB_SEVSEG is not set
> -# CONFIG_USB_RIO500 is not set
> -# CONFIG_USB_LEGOTOWER is not set
> -# CONFIG_USB_LCD is not set
> -# CONFIG_USB_LED is not set
> -# CONFIG_USB_CYPRESS_CY7C63 is not set
> -# CONFIG_USB_CYTHERM is not set
> -# CONFIG_USB_IDMOUSE is not set
> -# CONFIG_USB_FTDI_ELAN is not set
> -# CONFIG_USB_APPLEDISPLAY is not set
> -# CONFIG_USB_LD is not set
> -# CONFIG_USB_TRANCEVIBRATOR is not set
> -# CONFIG_USB_IOWARRIOR is not set
> -# CONFIG_USB_TEST is not set
> -# CONFIG_USB_ISIGHTFW is not set
> -CONFIG_USB_GADGET=y
> -# CONFIG_USB_GADGET_DEBUG is not set
> -# CONFIG_USB_GADGET_DEBUG_FILES is not set
> -# CONFIG_USB_GADGET_DEBUG_FS is not set
> -CONFIG_USB_GADGET_VBUS_DRAW=2
> -CONFIG_USB_GADGET_SELECTED=y
> -# CONFIG_USB_GADGET_AT91 is not set
> -# CONFIG_USB_GADGET_ATMEL_USBA is not set
> -# CONFIG_USB_GADGET_FSL_USB2 is not set
> -# CONFIG_USB_GADGET_LH7A40X is not set
> -# CONFIG_USB_GADGET_OMAP is not set
> -# CONFIG_USB_GADGET_PXA25X is not set
> -# CONFIG_USB_GADGET_R8A66597 is not set
> -CONFIG_USB_GADGET_PXA27X=y
> -CONFIG_USB_PXA27X=y
> -# CONFIG_USB_GADGET_S3C_HSOTG is not set
> -# CONFIG_USB_GADGET_IMX is not set
> -# CONFIG_USB_GADGET_S3C2410 is not set
> -# CONFIG_USB_GADGET_M66592 is not set
> -# CONFIG_USB_GADGET_AMD5536UDC is not set
> -# CONFIG_USB_GADGET_FSL_QE is not set
> -# CONFIG_USB_GADGET_CI13XXX is not set
> -# CONFIG_USB_GADGET_NET2280 is not set
> -# CONFIG_USB_GADGET_GOKU is not set
> -# CONFIG_USB_GADGET_LANGWELL is not set
> -# CONFIG_USB_GADGET_DUMMY_HCD is not set
> -# CONFIG_USB_GADGET_DUALSPEED is not set
> -# CONFIG_USB_ZERO is not set
> -# CONFIG_USB_AUDIO is not set
> -CONFIG_USB_ETH=y
> -# CONFIG_USB_ETH_RNDIS is not set
> -# CONFIG_USB_ETH_EEM is not set
> -# CONFIG_USB_GADGETFS is not set
> -# CONFIG_USB_FILE_STORAGE is not set
> -# CONFIG_USB_MASS_STORAGE is not set
> -# CONFIG_USB_G_SERIAL is not set
> -# CONFIG_USB_MIDI_GADGET is not set
> -# CONFIG_USB_G_PRINTER is not set
> -# CONFIG_USB_CDC_COMPOSITE is not set
> -# CONFIG_USB_G_NOKIA is not set
> -# CONFIG_USB_G_MULTI is not set
> -
> -#
> -# OTG and related infrastructure
> -#
> -CONFIG_USB_OTG_UTILS=y
> -# CONFIG_USB_GPIO_VBUS is not set
> -# CONFIG_USB_ULPI is not set
> -# CONFIG_NOP_USB_XCEIV is not set
> -CONFIG_MMC=y
> -# CONFIG_MMC_DEBUG is not set
> -CONFIG_MMC_UNSAFE_RESUME=y
> -
> -#
> -# MMC/SD/SDIO Card Drivers
> -#
> -CONFIG_MMC_BLOCK=y
> -CONFIG_MMC_BLOCK_BOUNCE=y
> -CONFIG_SDIO_UART=m
> -# CONFIG_MMC_TEST is not set
> -
> -#
> -# MMC/SD/SDIO Host Controller Drivers
> -#
> -CONFIG_MMC_PXA=y
> -# CONFIG_MMC_SDHCI is not set
> -CONFIG_MMC_SPI=y
> -# CONFIG_MEMSTICK is not set
> -CONFIG_NEW_LEDS=y
> -CONFIG_LEDS_CLASS=y
> -
> -#
> -# LED drivers
> -#
> -# CONFIG_LEDS_PCA9532 is not set
> -# CONFIG_LEDS_GPIO is not set
> -CONFIG_LEDS_LP3944=y
> -# CONFIG_LEDS_PCA955X is not set
> -# CONFIG_LEDS_DA903X is not set
> -# CONFIG_LEDS_DAC124S085 is not set
> -# CONFIG_LEDS_REGULATOR is not set
> -# CONFIG_LEDS_BD2802 is not set
> -# CONFIG_LEDS_LT3593 is not set
> -CONFIG_LEDS_TRIGGERS=y
> -
> -#
> -# LED Triggers
> -#
> -CONFIG_LEDS_TRIGGER_TIMER=y
> -CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> -CONFIG_LEDS_TRIGGER_BACKLIGHT=y
> -CONFIG_LEDS_TRIGGER_GPIO=y
> -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
> -
> -#
> -# iptables trigger is under Netfilter config (LED target)
> -#
> -# CONFIG_ACCESSIBILITY is not set
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_HCTOSYS=y
> -CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
> -# CONFIG_RTC_DEBUG is not set
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -# CONFIG_RTC_DRV_TEST is not set
> -
> -#
> -# I2C RTC drivers
> -#
> -# CONFIG_RTC_DRV_DS1307 is not set
> -# CONFIG_RTC_DRV_DS1374 is not set
> -# CONFIG_RTC_DRV_DS1672 is not set
> -# CONFIG_RTC_DRV_MAX6900 is not set
> -# CONFIG_RTC_DRV_RS5C372 is not set
> -# CONFIG_RTC_DRV_ISL1208 is not set
> -# CONFIG_RTC_DRV_X1205 is not set
> -# CONFIG_RTC_DRV_PCF8563 is not set
> -# CONFIG_RTC_DRV_PCF8583 is not set
> -# CONFIG_RTC_DRV_M41T80 is not set
> -# CONFIG_RTC_DRV_BQ32K is not set
> -# CONFIG_RTC_DRV_S35390A is not set
> -# CONFIG_RTC_DRV_FM3130 is not set
> -# CONFIG_RTC_DRV_RX8581 is not set
> -# CONFIG_RTC_DRV_RX8025 is not set
> -
> -#
> -# SPI RTC drivers
> -#
> -# CONFIG_RTC_DRV_M41T94 is not set
> -# CONFIG_RTC_DRV_DS1305 is not set
> -# CONFIG_RTC_DRV_DS1390 is not set
> -# CONFIG_RTC_DRV_MAX6902 is not set
> -# CONFIG_RTC_DRV_R9701 is not set
> -# CONFIG_RTC_DRV_RS5C348 is not set
> -# CONFIG_RTC_DRV_DS3234 is not set
> -# CONFIG_RTC_DRV_PCF2123 is not set
> -
> -#
> -# Platform RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_DS1286 is not set
> -# CONFIG_RTC_DRV_DS1511 is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_STK17TA8 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -# CONFIG_RTC_DRV_M48T35 is not set
> -# CONFIG_RTC_DRV_M48T59 is not set
> -# CONFIG_RTC_DRV_MSM6242 is not set
> -# CONFIG_RTC_DRV_BQ4802 is not set
> -# CONFIG_RTC_DRV_RP5C01 is not set
> -# CONFIG_RTC_DRV_V3020 is not set
> -
> -#
> -# on-CPU RTC drivers
> -#
> -# CONFIG_RTC_DRV_SA1100 is not set
> -CONFIG_RTC_DRV_PXA=y
> -# CONFIG_DMADEVICES is not set
> -# CONFIG_AUXDISPLAY is not set
> -# CONFIG_UIO is not set
> -
> -#
> -# TI VLYNQ
> -#
> -# CONFIG_STAGING is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -CONFIG_EXT3_FS=m
> -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
> -CONFIG_EXT3_FS_XATTR=y
> -# CONFIG_EXT3_FS_POSIX_ACL is not set
> -# CONFIG_EXT3_FS_SECURITY is not set
> -# CONFIG_EXT4_FS is not set
> -CONFIG_JBD=m
> -# CONFIG_JBD_DEBUG is not set
> -CONFIG_FS_MBCACHE=m
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -CONFIG_FS_POSIX_ACL=y
> -# CONFIG_XFS_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_BTRFS_FS is not set
> -# CONFIG_NILFS2_FS is not set
> -CONFIG_FILE_LOCKING=y
> -CONFIG_FSNOTIFY=y
> -CONFIG_DNOTIFY=y
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -CONFIG_AUTOFS_FS=y
> -CONFIG_AUTOFS4_FS=y
> -CONFIG_FUSE_FS=m
> -CONFIG_CUSE=m
> -
> -#
> -# Caches
> -#
> -# CONFIG_FSCACHE is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=m
> -CONFIG_MSDOS_FS=m
> -CONFIG_VFAT_FS=m
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_PROC_PAGE_MONITOR=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -CONFIG_MISC_FILESYSTEMS=y
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -CONFIG_JFFS2_FS_WBUF_VERIFY=y
> -CONFIG_JFFS2_SUMMARY=y
> -CONFIG_JFFS2_FS_XATTR=y
> -CONFIG_JFFS2_FS_POSIX_ACL=y
> -CONFIG_JFFS2_FS_SECURITY=y
> -CONFIG_JFFS2_COMPRESSION_OPTIONS=y
> -CONFIG_JFFS2_ZLIB=y
> -CONFIG_JFFS2_LZO=y
> -CONFIG_JFFS2_RTIME=y
> -CONFIG_JFFS2_RUBIN=y
> -# CONFIG_JFFS2_CMODE_NONE is not set
> -CONFIG_JFFS2_CMODE_PRIORITY=y
> -# CONFIG_JFFS2_CMODE_SIZE is not set
> -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
> -# CONFIG_LOGFS is not set
> -CONFIG_CRAMFS=m
> -CONFIG_SQUASHFS=m
> -# CONFIG_SQUASHFS_EMBEDDED is not set
> -CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_OMFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -CONFIG_ROMFS_FS=m
> -CONFIG_ROMFS_BACKED_BY_BLOCK=y
> -# CONFIG_ROMFS_BACKED_BY_MTD is not set
> -# CONFIG_ROMFS_BACKED_BY_BOTH is not set
> -CONFIG_ROMFS_ON_BLOCK=y
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -CONFIG_NETWORK_FILESYSTEMS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -CONFIG_NFS_V3_ACL=y
> -# CONFIG_NFS_V4 is not set
> -# CONFIG_ROOT_NFS is not set
> -CONFIG_NFSD=m
> -CONFIG_NFSD_V2_ACL=y
> -CONFIG_NFSD_V3=y
> -CONFIG_NFSD_V3_ACL=y
> -# CONFIG_NFSD_V4 is not set
> -CONFIG_LOCKD=y
> -CONFIG_LOCKD_V4=y
> -CONFIG_EXPORTFS=m
> -CONFIG_NFS_ACL_SUPPORT=y
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=y
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -CONFIG_SMB_FS=m
> -# CONFIG_SMB_NLS_DEFAULT is not set
> -# CONFIG_CEPH_FS is not set
> -CONFIG_CIFS=m
> -CONFIG_CIFS_STATS=y
> -# CONFIG_CIFS_STATS2 is not set
> -CONFIG_CIFS_WEAK_PW_HASH=y
> -CONFIG_CIFS_XATTR=y
> -CONFIG_CIFS_POSIX=y
> -# CONFIG_CIFS_DEBUG2 is not set
> -# CONFIG_CIFS_EXPERIMENTAL is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -# CONFIG_PARTITION_ADVANCED is not set
> -CONFIG_MSDOS_PARTITION=y
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -CONFIG_NLS_CODEPAGE_437=m
> -CONFIG_NLS_CODEPAGE_737=m
> -CONFIG_NLS_CODEPAGE_775=m
> -CONFIG_NLS_CODEPAGE_850=m
> -CONFIG_NLS_CODEPAGE_852=m
> -CONFIG_NLS_CODEPAGE_855=m
> -CONFIG_NLS_CODEPAGE_857=m
> -CONFIG_NLS_CODEPAGE_860=m
> -CONFIG_NLS_CODEPAGE_861=m
> -CONFIG_NLS_CODEPAGE_862=m
> -CONFIG_NLS_CODEPAGE_863=m
> -CONFIG_NLS_CODEPAGE_864=m
> -CONFIG_NLS_CODEPAGE_865=m
> -CONFIG_NLS_CODEPAGE_866=m
> -CONFIG_NLS_CODEPAGE_869=m
> -CONFIG_NLS_CODEPAGE_936=m
> -CONFIG_NLS_CODEPAGE_950=m
> -CONFIG_NLS_CODEPAGE_932=m
> -CONFIG_NLS_CODEPAGE_949=m
> -CONFIG_NLS_CODEPAGE_874=m
> -CONFIG_NLS_ISO8859_8=m
> -CONFIG_NLS_CODEPAGE_1250=m
> -CONFIG_NLS_CODEPAGE_1251=m
> -CONFIG_NLS_ASCII=m
> -CONFIG_NLS_ISO8859_1=m
> -CONFIG_NLS_ISO8859_2=m
> -CONFIG_NLS_ISO8859_3=m
> -CONFIG_NLS_ISO8859_4=m
> -CONFIG_NLS_ISO8859_5=m
> -CONFIG_NLS_ISO8859_6=m
> -CONFIG_NLS_ISO8859_7=m
> -CONFIG_NLS_ISO8859_9=m
> -CONFIG_NLS_ISO8859_13=m
> -CONFIG_NLS_ISO8859_14=m
> -CONFIG_NLS_ISO8859_15=m
> -CONFIG_NLS_KOI8_R=m
> -CONFIG_NLS_KOI8_U=m
> -CONFIG_NLS_UTF8=m
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -CONFIG_PRINTK_TIME=y
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_FRAME_WARN=1024
> -# CONFIG_MAGIC_SYSRQ is not set
> -# CONFIG_STRIP_ASM_SYMS is not set
> -# CONFIG_UNUSED_SYMBOLS is not set
> -CONFIG_DEBUG_FS=y
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DEBUG_SHIRQ is not set
> -CONFIG_DETECT_SOFTLOCKUP=y
> -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
> -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
> -CONFIG_DETECT_HUNG_TASK=y
> -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
> -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
> -# CONFIG_SCHED_DEBUG is not set
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_TIMER_STATS is not set
> -# CONFIG_DEBUG_OBJECTS is not set
> -# CONFIG_DEBUG_SLAB is not set
> -# CONFIG_DEBUG_KMEMLEAK is not set
> -CONFIG_DEBUG_PREEMPT=y
> -CONFIG_DEBUG_RT_MUTEXES=y
> -CONFIG_DEBUG_PI_LIST=y
> -# CONFIG_RT_MUTEX_TESTER is not set
> -CONFIG_DEBUG_SPINLOCK=y
> -CONFIG_DEBUG_MUTEXES=y
> -CONFIG_DEBUG_LOCK_ALLOC=y
> -CONFIG_PROVE_LOCKING=y
> -# CONFIG_PROVE_RCU is not set
> -CONFIG_LOCKDEP=y
> -# CONFIG_LOCK_STAT is not set
> -# CONFIG_DEBUG_LOCKDEP is not set
> -CONFIG_TRACE_IRQFLAGS=y
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -CONFIG_STACKTRACE=y
> -# CONFIG_DEBUG_KOBJECT is not set
> -CONFIG_DEBUG_BUGVERBOSE=y
> -# CONFIG_DEBUG_INFO is not set
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_WRITECOUNT is not set
> -# CONFIG_DEBUG_MEMORY_INIT is not set
> -# CONFIG_DEBUG_LIST is not set
> -# CONFIG_DEBUG_SG is not set
> -# CONFIG_DEBUG_NOTIFIERS is not set
> -# CONFIG_DEBUG_CREDENTIALS is not set
> -# CONFIG_BOOT_PRINTK_DELAY is not set
> -# CONFIG_RCU_TORTURE_TEST is not set
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -# CONFIG_BACKTRACE_SELF_TEST is not set
> -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
> -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
> -# CONFIG_LKDTM is not set
> -# CONFIG_FAULT_INJECTION is not set
> -# CONFIG_LATENCYTOP is not set
> -# CONFIG_SYSCTL_SYSCALL_CHECK is not set
> -# CONFIG_PAGE_POISONING is not set
> -CONFIG_HAVE_FUNCTION_TRACER=y
> -CONFIG_TRACING_SUPPORT=y
> -# CONFIG_FTRACE is not set
> -# CONFIG_DYNAMIC_DEBUG is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -# CONFIG_KGDB is not set
> -CONFIG_ARM_UNWIND=y
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> -# CONFIG_DEBUG_STACK_USAGE is not set
> -# CONFIG_DEBUG_LL is not set
> -# CONFIG_OC_ETM is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITYFS is not set
> -# CONFIG_DEFAULT_SECURITY_SELINUX is not set
> -# CONFIG_DEFAULT_SECURITY_SMACK is not set
> -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
> -CONFIG_DEFAULT_SECURITY_DAC=y
> -CONFIG_DEFAULT_SECURITY=""
> -CONFIG_CRYPTO=y
> -
> -#
> -# Crypto core or helper
> -#
> -CONFIG_CRYPTO_ALGAPI=m
> -CONFIG_CRYPTO_ALGAPI2=m
> -CONFIG_CRYPTO_AEAD=m
> -CONFIG_CRYPTO_AEAD2=m
> -CONFIG_CRYPTO_BLKCIPHER=m
> -CONFIG_CRYPTO_BLKCIPHER2=m
> -CONFIG_CRYPTO_HASH=m
> -CONFIG_CRYPTO_HASH2=m
> -CONFIG_CRYPTO_RNG2=m
> -CONFIG_CRYPTO_PCOMP=m
> -CONFIG_CRYPTO_MANAGER=m
> -CONFIG_CRYPTO_MANAGER2=m
> -CONFIG_CRYPTO_GF128MUL=m
> -CONFIG_CRYPTO_NULL=m
> -CONFIG_CRYPTO_WORKQUEUE=m
> -CONFIG_CRYPTO_CRYPTD=m
> -CONFIG_CRYPTO_AUTHENC=m
> -CONFIG_CRYPTO_TEST=m
> -
> -#
> -# Authenticated Encryption with Associated Data
> -#
> -# CONFIG_CRYPTO_CCM is not set
> -# CONFIG_CRYPTO_GCM is not set
> -# CONFIG_CRYPTO_SEQIV is not set
> -
> -#
> -# Block modes
> -#
> -CONFIG_CRYPTO_CBC=m
> -# CONFIG_CRYPTO_CTR is not set
> -# CONFIG_CRYPTO_CTS is not set
> -CONFIG_CRYPTO_ECB=m
> -CONFIG_CRYPTO_LRW=m
> -CONFIG_CRYPTO_PCBC=m
> -CONFIG_CRYPTO_XTS=m
> -
> -#
> -# Hash modes
> -#
> -CONFIG_CRYPTO_HMAC=m
> -CONFIG_CRYPTO_XCBC=m
> -CONFIG_CRYPTO_VMAC=m
> -
> -#
> -# Digest
> -#
> -CONFIG_CRYPTO_CRC32C=m
> -CONFIG_CRYPTO_GHASH=m
> -CONFIG_CRYPTO_MD4=m
> -CONFIG_CRYPTO_MD5=m
> -CONFIG_CRYPTO_MICHAEL_MIC=m
> -# CONFIG_CRYPTO_RMD128 is not set
> -# CONFIG_CRYPTO_RMD160 is not set
> -# CONFIG_CRYPTO_RMD256 is not set
> -# CONFIG_CRYPTO_RMD320 is not set
> -CONFIG_CRYPTO_SHA1=m
> -CONFIG_CRYPTO_SHA256=m
> -CONFIG_CRYPTO_SHA512=m
> -CONFIG_CRYPTO_TGR192=m
> -# CONFIG_CRYPTO_WP512 is not set
> -
> -#
> -# Ciphers
> -#
> -CONFIG_CRYPTO_AES=m
> -# CONFIG_CRYPTO_ANUBIS is not set
> -CONFIG_CRYPTO_ARC4=m
> -CONFIG_CRYPTO_BLOWFISH=m
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -CONFIG_CRYPTO_CAST5=m
> -CONFIG_CRYPTO_CAST6=m
> -CONFIG_CRYPTO_DES=m
> -CONFIG_CRYPTO_FCRYPT=m
> -CONFIG_CRYPTO_KHAZAD=m
> -# CONFIG_CRYPTO_SALSA20 is not set
> -CONFIG_CRYPTO_SEED=m
> -CONFIG_CRYPTO_SERPENT=m
> -CONFIG_CRYPTO_TEA=m
> -CONFIG_CRYPTO_TWOFISH=m
> -CONFIG_CRYPTO_TWOFISH_COMMON=m
> -
> -#
> -# Compression
> -#
> -CONFIG_CRYPTO_DEFLATE=m
> -# CONFIG_CRYPTO_ZLIB is not set
> -# CONFIG_CRYPTO_LZO is not set
> -
> -#
> -# Random Number Generation
> -#
> -# CONFIG_CRYPTO_ANSI_CPRNG is not set
> -CONFIG_CRYPTO_HW=y
> -# CONFIG_BINARY_PRINTF is not set
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -CONFIG_GENERIC_FIND_LAST_BIT=y
> -CONFIG_CRC_CCITT=m
> -CONFIG_CRC16=y
> -# CONFIG_CRC_T10DIF is not set
> -CONFIG_CRC_ITU_T=y
> -CONFIG_CRC32=y
> -CONFIG_CRC7=y
> -CONFIG_LIBCRC32C=m
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_LZO_COMPRESS=y
> -CONFIG_LZO_DECOMPRESS=y
> -CONFIG_DECOMPRESS_GZIP=y
> -CONFIG_DECOMPRESS_BZIP2=y
> -CONFIG_DECOMPRESS_LZMA=y
> -CONFIG_TEXTSEARCH=y
> -CONFIG_TEXTSEARCH_KMP=m
> -CONFIG_TEXTSEARCH_BM=m
> -CONFIG_TEXTSEARCH_FSM=m
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> -CONFIG_NLATTR=y
> -CONFIG_GENERIC_ATOMIC64=y
> diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig
> deleted file mode 100644
> index aeb7686..0000000
> --- a/arch/arm/configs/lpd270_defconfig
> +++ /dev/null
> @@ -1,1031 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.20-rc1
> -# Sat Dec 16 06:05:51 2006
> -#
> -CONFIG_ARM=y
> -# CONFIG_GENERIC_TIME is not set
> -CONFIG_MMU=y
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -# CONFIG_ARCH_HAS_ILOG2_U32 is not set
> -# CONFIG_ARCH_HAS_ILOG2_U64 is not set
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -
> -#
> -# Code maturity level options
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -
> -#
> -# General setup
> -#
> -CONFIG_LOCALVERSION=""
> -CONFIG_LOCALVERSION_AUTO=y
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -# CONFIG_IPC_NS is not set
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_UTS_NS is not set
> -# CONFIG_AUDIT is not set
> -# CONFIG_IKCONFIG is not set
> -CONFIG_SYSFS_DEPRECATED=y
> -# CONFIG_RELAY is not set
> -CONFIG_INITRAMFS_SOURCE=""
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -# CONFIG_EMBEDDED is not set
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_EPOLL=y
> -CONFIG_SHMEM=y
> -CONFIG_SLAB=y
> -CONFIG_VM_EVENT_COUNTERS=y
> -CONFIG_RT_MUTEXES=y
> -# CONFIG_TINY_SHMEM is not set
> -CONFIG_BASE_SMALL=0
> -# CONFIG_SLOB is not set
> -
> -#
> -# Loadable module support
> -#
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_UNLOAD is not set
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -# CONFIG_KMOD is not set
> -
> -#
> -# Block layer
> -#
> -CONFIG_BLOCK=y
> -# CONFIG_LBD is not set
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_LSF is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_AS=y
> -CONFIG_IOSCHED_DEADLINE=y
> -CONFIG_IOSCHED_CFQ=y
> -CONFIG_DEFAULT_AS=y
> -# CONFIG_DEFAULT_DEADLINE is not set
> -# CONFIG_DEFAULT_CFQ is not set
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="anticipatory"
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS7500 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_CO285 is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_OMAP is not set
> -
> -#
> -# Intel PXA2xx Implementations
> -#
> -# CONFIG_ARCH_LUBBOCK is not set
> -CONFIG_MACH_LOGICPD_PXA270=y
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_MACH_TRIZEPS4 is not set
> -CONFIG_PXA27x=y
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -# CONFIG_ARM_THUMB is not set
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -
> -#
> -# Bus support
> -#
> -
> -#
> -# PCCARD (PCMCIA/CardBus) support
> -#
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -# CONFIG_PREEMPT is not set
> -CONFIG_HZ=100
> -# CONFIG_AEABI is not set
> -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -# CONFIG_SPARSEMEM_STATIC is not set
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_RESOURCES_64BIT is not set
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M"
> -# CONFIG_XIP_KERNEL is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -# CONFIG_ARTHUR is not set
> -
> -#
> -# Power management options
> -#
> -# CONFIG_PM is not set
> -# CONFIG_APM is not set
> -
> -#
> -# Networking
> -#
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -# CONFIG_NETDEBUG is not set
> -# CONFIG_PACKET is not set
> -CONFIG_UNIX=y
> -CONFIG_XFRM=y
> -# CONFIG_XFRM_USER is not set
> -# CONFIG_XFRM_SUB_POLICY is not set
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -# CONFIG_IP_PNP_DHCP is not set
> -CONFIG_IP_PNP_BOOTP=y
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -CONFIG_INET_XFRM_MODE_TRANSPORT=y
> -CONFIG_INET_XFRM_MODE_TUNNEL=y
> -CONFIG_INET_XFRM_MODE_BEET=y
> -CONFIG_INET_DIAG=y
> -CONFIG_INET_TCP_DIAG=y
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -CONFIG_IPV6=y
> -# CONFIG_IPV6_PRIVACY is not set
> -# CONFIG_IPV6_ROUTER_PREF is not set
> -# CONFIG_INET6_AH is not set
> -# CONFIG_INET6_ESP is not set
> -# CONFIG_INET6_IPCOMP is not set
> -# CONFIG_IPV6_MIP6 is not set
> -# CONFIG_INET6_XFRM_TUNNEL is not set
> -# CONFIG_INET6_TUNNEL is not set
> -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET6_XFRM_MODE_BEET is not set
> -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
> -# CONFIG_IPV6_SIT is not set
> -# CONFIG_IPV6_TUNNEL is not set
> -# CONFIG_IPV6_MULTIPLE_TABLES is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -# CONFIG_NETFILTER is not set
> -
> -#
> -# DCCP Configuration (EXPERIMENTAL)
> -#
> -# CONFIG_IP_DCCP is not set
> -
> -#
> -# SCTP Configuration (EXPERIMENTAL)
> -#
> -# CONFIG_IP_SCTP is not set
> -
> -#
> -# TIPC Configuration (EXPERIMENTAL)
> -#
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -
> -#
> -# QoS and/or fair queueing
> -#
> -# CONFIG_NET_SCHED is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_IRDA is not set
> -# CONFIG_BT is not set
> -# CONFIG_IEEE80211 is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -# CONFIG_FW_LOADER is not set
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -
> -#
> -# Connector - unified userspace <-> kernelspace linker
> -#
> -# CONFIG_CONNECTOR is not set
> -
> -#
> -# Memory Technology Devices (MTD)
> -#
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -CONFIG_MTD_REDBOOT_PARTS=y
> -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
> -# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
> -# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
> -# CONFIG_MTD_CMDLINE_PARTS is not set
> -# CONFIG_MTD_AFS_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -# CONFIG_MTD_JEDECPROBE is not set
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_NOSWAP=y
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> -CONFIG_MTD_CFI_GEOMETRY=y
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -# CONFIG_MTD_CFI_I1 is not set
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -# CONFIG_MTD_OTP is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -# CONFIG_MTD_CFI_AMDSTD is not set
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_OBSOLETE_CHIPS is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> -# CONFIG_MTD_PHYSMAP is not set
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -
> -#
> -# NAND Flash Device Drivers
> -#
> -# CONFIG_MTD_NAND is not set
> -
> -#
> -# OneNAND Flash Device Drivers
> -#
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# Parallel port support
> -#
> -# CONFIG_PARPORT is not set
> -
> -#
> -# Plug and Play support
> -#
> -
> -#
> -# Block devices
> -#
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -# CONFIG_BLK_DEV_LOOP is not set
> -CONFIG_BLK_DEV_NBD=y
> -# CONFIG_BLK_DEV_RAM is not set
> -# CONFIG_BLK_DEV_INITRD is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -
> -#
> -# ATA/ATAPI/MFM/RLL support
> -#
> -CONFIG_IDE=y
> -CONFIG_BLK_DEV_IDE=y
> -
> -#
> -# Please see Documentation/ide.txt for help/info on IDE drives
> -#
> -# CONFIG_BLK_DEV_IDE_SATA is not set
> -CONFIG_BLK_DEV_IDEDISK=y
> -# CONFIG_IDEDISK_MULTI_MODE is not set
> -# CONFIG_BLK_DEV_IDECD is not set
> -# CONFIG_BLK_DEV_IDETAPE is not set
> -# CONFIG_BLK_DEV_IDEFLOPPY is not set
> -# CONFIG_IDE_TASK_IOCTL is not set
> -
> -#
> -# IDE chipset support/bugfixes
> -#
> -# CONFIG_IDE_GENERIC is not set
> -# CONFIG_IDE_ARM is not set
> -# CONFIG_BLK_DEV_IDEDMA is not set
> -# CONFIG_IDEDMA_AUTO is not set
> -# CONFIG_BLK_DEV_HD is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -# CONFIG_SCSI is not set
> -# CONFIG_SCSI_NETLINK is not set
> -
> -#
> -# Serial ATA (prod) and Parallel ATA (experimental) drivers
> -#
> -# CONFIG_ATA is not set
> -
> -#
> -# Multi-device support (RAID and LVM)
> -#
> -# CONFIG_MD is not set
> -
> -#
> -# Fusion MPT device support
> -#
> -# CONFIG_FUSION is not set
> -
> -#
> -# IEEE 1394 (FireWire) support
> -#
> -
> -#
> -# I2O device support
> -#
> -
> -#
> -# Network device support
> -#
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -
> -#
> -# PHY device support
> -#
> -# CONFIG_PHYLIB is not set
> -
> -#
> -# Ethernet (10 or 100Mbit)
> -#
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=y
> -CONFIG_SMC91X=y
> -# CONFIG_DM9000 is not set
> -# CONFIG_SMC911X is not set
> -
> -#
> -# Ethernet (1000 Mbit)
> -#
> -
> -#
> -# Ethernet (10000 Mbit)
> -#
> -
> -#
> -# Token Ring devices
> -#
> -
> -#
> -# Wireless LAN (non-hamradio)
> -#
> -# CONFIG_NET_RADIO is not set
> -
> -#
> -# Wan interfaces
> -#
> -# CONFIG_WAN is not set
> -# CONFIG_PPP is not set
> -# CONFIG_SLIP is not set
> -# CONFIG_SHAPER is not set
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -
> -#
> -# ISDN subsystem
> -#
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -CONFIG_INPUT_MOUSEDEV_PSAUX=y
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> -# CONFIG_INPUT_JOYDEV is not set
> -# CONFIG_INPUT_TSDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -CONFIG_KEYBOARD_ATKBD=y
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_KEYBOARD_STOWAWAY is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TOUCHSCREEN is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -CONFIG_SERIO=y
> -# CONFIG_SERIO_SERPORT is not set
> -CONFIG_SERIO_LIBPS2=y
> -# CONFIG_SERIO_RAW is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=256
> -
> -#
> -# IPMI
> -#
> -# CONFIG_IPMI_HANDLER is not set
> -
> -#
> -# Watchdog Cards
> -#
> -# CONFIG_WATCHDOG is not set
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_NVRAM is not set
> -# CONFIG_DTLK is not set
> -# CONFIG_R3964 is not set
> -# CONFIG_RAW_DRIVER is not set
> -
> -#
> -# TPM devices
> -#
> -# CONFIG_TCG_TPM is not set
> -
> -#
> -# I2C support
> -#
> -# CONFIG_I2C is not set
> -
> -#
> -# SPI support
> -#
> -# CONFIG_SPI is not set
> -# CONFIG_SPI_MASTER is not set
> -
> -#
> -# Dallas's 1-wire bus
> -#
> -# CONFIG_W1 is not set
> -
> -#
> -# Hardware Monitoring support
> -#
> -CONFIG_HWMON=y
> -# CONFIG_HWMON_VID is not set
> -# CONFIG_SENSORS_ABITUGURU is not set
> -# CONFIG_SENSORS_F71805F is not set
> -# CONFIG_SENSORS_PC87427 is not set
> -# CONFIG_SENSORS_VT1211 is not set
> -# CONFIG_HWMON_DEBUG_CHIP is not set
> -
> -#
> -# Misc devices
> -#
> -# CONFIG_TIFM_CORE is not set
> -
> -#
> -# LED devices
> -#
> -# CONFIG_NEW_LEDS is not set
> -
> -#
> -# LED drivers
> -#
> -
> -#
> -# LED Triggers
> -#
> -
> -#
> -# Multimedia devices
> -#
> -# CONFIG_VIDEO_DEV is not set
> -
> -#
> -# Digital Video Broadcasting Devices
> -#
> -# CONFIG_DVB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_FIRMWARE_EDID is not set
> -CONFIG_FB=y
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -# CONFIG_FB_S1D13XXX is not set
> -CONFIG_FB_PXA=y
> -# CONFIG_FB_PXA_PARAMETERS is not set
> -# CONFIG_FB_MBX is not set
> -# CONFIG_FB_VIRTUAL is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
> -# CONFIG_FONTS is not set
> -CONFIG_FONT_8x8=y
> -CONFIG_FONT_8x16=y
> -
> -#
> -# Logo configuration
> -#
> -CONFIG_LOGO=y
> -CONFIG_LOGO_LINUX_MONO=y
> -CONFIG_LOGO_LINUX_VGA16=y
> -CONFIG_LOGO_LINUX_CLUT224=y
> -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
> -
> -#
> -# Sound
> -#
> -CONFIG_SOUND=y
> -
> -#
> -# Advanced Linux Sound Architecture
> -#
> -CONFIG_SND=y
> -CONFIG_SND_TIMER=y
> -CONFIG_SND_PCM=y
> -# CONFIG_SND_SEQUENCER is not set
> -# CONFIG_SND_MIXER_OSS is not set
> -# CONFIG_SND_PCM_OSS is not set
> -# CONFIG_SND_DYNAMIC_MINORS is not set
> -# CONFIG_SND_SUPPORT_OLD_API is not set
> -CONFIG_SND_VERBOSE_PROCFS=y
> -# CONFIG_SND_VERBOSE_PRINTK is not set
> -# CONFIG_SND_DEBUG is not set
> -
> -#
> -# Generic devices
> -#
> -CONFIG_SND_AC97_CODEC=y
> -# CONFIG_SND_DUMMY is not set
> -# CONFIG_SND_MTPAV is not set
> -# CONFIG_SND_SERIAL_U16550 is not set
> -# CONFIG_SND_MPU401 is not set
> -
> -#
> -# ALSA ARM devices
> -#
> -CONFIG_SND_PXA2XX_PCM=y
> -CONFIG_SND_PXA2XX_AC97=y
> -
> -#
> -# Open Sound System
> -#
> -# CONFIG_SOUND_PRIME is not set
> -CONFIG_AC97_BUS=y
> -
> -#
> -# HID Devices
> -#
> -CONFIG_HID=y
> -
> -#
> -# USB support
> -#
> -CONFIG_USB_ARCH_HAS_HCD=y
> -CONFIG_USB_ARCH_HAS_OHCI=y
> -# CONFIG_USB_ARCH_HAS_EHCI is not set
> -# CONFIG_USB is not set
> -
> -#
> -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
> -#
> -
> -#
> -# USB Gadget Support
> -#
> -# CONFIG_USB_GADGET is not set
> -
> -#
> -# MMC/SD Card support
> -#
> -# CONFIG_MMC is not set
> -
> -#
> -# Real Time Clock
> -#
> -CONFIG_RTC_LIB=y
> -# CONFIG_RTC_CLASS is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -# CONFIG_EXT3_FS is not set
> -# CONFIG_EXT4DEV_FS is not set
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -# CONFIG_FS_POSIX_ACL is not set
> -# CONFIG_XFS_FS is not set
> -# CONFIG_GFS2_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -CONFIG_DNOTIFY=y
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=y
> -CONFIG_MSDOS_FS=y
> -# CONFIG_VFAT_FS is not set
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_SYSFS=y
> -# CONFIG_TMPFS is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -CONFIG_RAMFS=y
> -# CONFIG_CONFIGFS_FS is not set
> -
> -#
> -# Miscellaneous filesystems
> -#
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -# CONFIG_JFFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -# CONFIG_JFFS2_SUMMARY is not set
> -# CONFIG_JFFS2_FS_XATTR is not set
> -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
> -CONFIG_JFFS2_ZLIB=y
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -
> -#
> -# Network File Systems
> -#
> -CONFIG_NFS_FS=y
> -# CONFIG_NFS_V3 is not set
> -# CONFIG_NFS_V4 is not set
> -# CONFIG_NFS_DIRECTIO is not set
> -# CONFIG_NFSD is not set
> -CONFIG_ROOT_NFS=y
> -CONFIG_LOCKD=y
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=y
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -# CONFIG_CIFS is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -# CONFIG_9P_FS is not set
> -
> -#
> -# Partition Types
> -#
> -# CONFIG_PARTITION_ADVANCED is not set
> -CONFIG_MSDOS_PARTITION=y
> -
> -#
> -# Native Language Support
> -#
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -# CONFIG_NLS_CODEPAGE_437 is not set
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -# CONFIG_NLS_CODEPAGE_850 is not set
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -CONFIG_NLS_ISO8859_1=y
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -# CONFIG_NLS_ISO8859_15 is not set
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -# CONFIG_NLS_UTF8 is not set
> -
> -#
> -# Distributed Lock Manager
> -#
> -# CONFIG_DLM is not set
> -
> -#
> -# Profiling support
> -#
> -# CONFIG_PROFILING is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_MAGIC_SYSRQ=y
> -# CONFIG_UNUSED_SYMBOLS is not set
> -# CONFIG_DEBUG_FS is not set
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -CONFIG_LOG_BUF_SHIFT=14
> -CONFIG_DETECT_SOFTLOCKUP=y
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_DEBUG_SLAB is not set
> -# CONFIG_DEBUG_RT_MUTEXES is not set
> -# CONFIG_RT_MUTEX_TESTER is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -# CONFIG_DEBUG_MUTEXES is not set
> -# CONFIG_DEBUG_RWSEMS is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -CONFIG_DEBUG_BUGVERBOSE=y
> -CONFIG_DEBUG_INFO=y
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_LIST is not set
> -CONFIG_FRAME_POINTER=y
> -CONFIG_FORCED_INLINING=y
> -# CONFIG_RCU_TORTURE_TEST is not set
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> -CONFIG_DEBUG_LL=y
> -# CONFIG_DEBUG_ICEDCC is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -
> -#
> -# Cryptographic options
> -#
> -# CONFIG_CRYPTO is not set
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -# CONFIG_CRC_CCITT is not set
> -# CONFIG_CRC16 is not set
> -CONFIG_CRC32=y
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_PLIST=y
> -CONFIG_IOMAP_COPY=y
> diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig
> deleted file mode 100644
> index 75c6293..0000000
> --- a/arch/arm/configs/lubbock_defconfig
> +++ /dev/null
> @@ -1,800 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.12-rc1-bk2
> -# Mon Mar 28 00:18:13 2005
> -#
> -CONFIG_ARM=y
> -CONFIG_MMU=y
> -CONFIG_UID16=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_GENERIC_IOMAP=y
> -
> -#
> -# Code maturity level options
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_CLEAN_COMPILE=y
> -CONFIG_BROKEN_ON_SMP=y
> -
> -#
> -# General setup
> -#
> -CONFIG_LOCALVERSION=""
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -CONFIG_SYSCTL=y
> -# CONFIG_AUDIT is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_KOBJECT_UEVENT=y
> -# CONFIG_IKCONFIG is not set
> -# CONFIG_EMBEDDED is not set
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_EPOLL=y
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SHMEM=y
> -CONFIG_CC_ALIGN_FUNCTIONS=0
> -CONFIG_CC_ALIGN_LABELS=0
> -CONFIG_CC_ALIGN_LOOPS=0
> -CONFIG_CC_ALIGN_JUMPS=0
> -# CONFIG_TINY_SHMEM is not set
> -CONFIG_BASE_SMALL=0
> -
> -#
> -# Loadable module support
> -#
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_UNLOAD is not set
> -CONFIG_OBSOLETE_MODPARM=y
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -# CONFIG_KMOD is not set
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_CLPS7500 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_CO285 is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_IOP3XX is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_L7200 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_H720X is not set
> -
> -#
> -# Intel PXA2xx Implementations
> -#
> -CONFIG_ARCH_LUBBOCK=y
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -CONFIG_PXA25x=y
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_MINICACHE=y
> -
> -#
> -# Processor Features
> -#
> -# CONFIG_ARM_THUMB is not set
> -CONFIG_XSCALE_PMU=y
> -CONFIG_SA1111=y
> -CONFIG_DMABOUNCE=y
> -CONFIG_FORCE_MAX_ZONEORDER=9
> -
> -#
> -# Bus support
> -#
> -
> -#
> -# PCCARD (PCMCIA/CardBus) support
> -#
> -CONFIG_PCCARD=y
> -# CONFIG_PCMCIA_DEBUG is not set
> -CONFIG_PCMCIA=y
> -
> -#
> -# PC-card bridges
> -#
> -# CONFIG_TCIC is not set
> -CONFIG_PCMCIA_PXA2XX=y
> -
> -#
> -# Kernel Features
> -#
> -# CONFIG_PREEMPT is not set
> -CONFIG_LEDS=y
> -CONFIG_LEDS_TIMER=y
> -CONFIG_LEDS_CPU=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M"
> -# CONFIG_XIP_KERNEL is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -# CONFIG_ARTHUR is not set
> -
> -#
> -# Power management options
> -#
> -# CONFIG_PM is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -# CONFIG_FW_LOADER is not set
> -# CONFIG_DEBUG_DRIVER is not set
> -
> -#
> -# Memory Technology Devices (MTD)
> -#
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -CONFIG_MTD_REDBOOT_PARTS=y
> -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
> -# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
> -# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
> -# CONFIG_MTD_CMDLINE_PARTS is not set
> -# CONFIG_MTD_AFS_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -# CONFIG_MTD_JEDECPROBE is not set
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_NOSWAP=y
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> -CONFIG_MTD_CFI_GEOMETRY=y
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -# CONFIG_MTD_CFI_I1 is not set
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -# CONFIG_MTD_CFI_AMDSTD is not set
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> -# CONFIG_MTD_PHYSMAP is not set
> -CONFIG_MTD_LUBBOCK=y
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_EDB7312 is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLKMTD is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -
> -#
> -# NAND Flash Device Drivers
> -#
> -# CONFIG_MTD_NAND is not set
> -
> -#
> -# Parallel port support
> -#
> -# CONFIG_PARPORT is not set
> -
> -#
> -# Plug and Play support
> -#
> -
> -#
> -# Block devices
> -#
> -# CONFIG_BLK_DEV_FD is not set
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -# CONFIG_BLK_DEV_LOOP is not set
> -# CONFIG_BLK_DEV_NBD is not set
> -# CONFIG_BLK_DEV_RAM is not set
> -CONFIG_BLK_DEV_RAM_COUNT=16
> -CONFIG_INITRAMFS_SOURCE=""
> -# CONFIG_CDROM_PKTCDVD is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_AS=y
> -CONFIG_IOSCHED_DEADLINE=y
> -CONFIG_IOSCHED_CFQ=y
> -# CONFIG_ATA_OVER_ETH is not set
> -
> -#
> -# ATA/ATAPI/MFM/RLL support
> -#
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_SCSI is not set
> -
> -#
> -# Multi-device support (RAID and LVM)
> -#
> -# CONFIG_MD is not set
> -
> -#
> -# Fusion MPT device support
> -#
> -
> -#
> -# IEEE 1394 (FireWire) support
> -#
> -
> -#
> -# I2O device support
> -#
> -
> -#
> -# Networking support
> -#
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -# CONFIG_PACKET is not set
> -# CONFIG_NETLINK_DEV is not set
> -CONFIG_UNIX=y
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_PNP=y
> -# CONFIG_IP_PNP_DHCP is not set
> -CONFIG_IP_PNP_BOOTP=y
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_TUNNEL is not set
> -# CONFIG_IP_TCPDIAG is not set
> -# CONFIG_IP_TCPDIAG_IPV6 is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETFILTER is not set
> -
> -#
> -# SCTP Configuration (EXPERIMENTAL)
> -#
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_NET_DIVERT is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -
> -#
> -# QoS and/or fair queueing
> -#
> -# CONFIG_NET_SCHED is not set
> -# CONFIG_NET_CLS_ROUTE is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_IRDA is not set
> -# CONFIG_BT is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -
> -#
> -# Ethernet (10 or 100Mbit)
> -#
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=y
> -CONFIG_SMC91X=y
> -
> -#
> -# Ethernet (1000 Mbit)
> -#
> -
> -#
> -# Ethernet (10000 Mbit)
> -#
> -
> -#
> -# Token Ring devices
> -#
> -
> -#
> -# Wireless LAN (non-hamradio)
> -#
> -# CONFIG_NET_RADIO is not set
> -
> -#
> -# PCMCIA network device support
> -#
> -CONFIG_NET_PCMCIA=y
> -# CONFIG_PCMCIA_3C589 is not set
> -# CONFIG_PCMCIA_3C574 is not set
> -# CONFIG_PCMCIA_FMVJ18X is not set
> -CONFIG_PCMCIA_PCNET=y
> -# CONFIG_PCMCIA_NMCLAN is not set
> -# CONFIG_PCMCIA_SMC91C92 is not set
> -# CONFIG_PCMCIA_XIRC2PS is not set
> -# CONFIG_PCMCIA_AXNET is not set
> -
> -#
> -# Wan interfaces
> -#
> -# CONFIG_WAN is not set
> -# CONFIG_PPP is not set
> -# CONFIG_SLIP is not set
> -# CONFIG_SHAPER is not set
> -# CONFIG_NETCONSOLE is not set
> -
> -#
> -# ISDN subsystem
> -#
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -CONFIG_INPUT_MOUSEDEV_PSAUX=y
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> -# CONFIG_INPUT_JOYDEV is not set
> -# CONFIG_INPUT_TSDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -CONFIG_KEYBOARD_ATKBD=y
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -CONFIG_INPUT_MOUSE=y
> -CONFIG_MOUSE_PS2=y
> -# CONFIG_MOUSE_SERIAL is not set
> -# CONFIG_MOUSE_VSXXXAA is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TOUCHSCREEN is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -CONFIG_SERIO=y
> -# CONFIG_SERIO_SERPORT is not set
> -CONFIG_SERIO_SA1111=y
> -CONFIG_SERIO_LIBPS2=y
> -# CONFIG_SERIO_RAW is not set
> -# CONFIG_GAMEPORT is not set
> -CONFIG_SOUND_GAMEPORT=y
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=256
> -
> -#
> -# IPMI
> -#
> -# CONFIG_IPMI_HANDLER is not set
> -
> -#
> -# Watchdog Cards
> -#
> -# CONFIG_WATCHDOG is not set
> -# CONFIG_NVRAM is not set
> -# CONFIG_RTC is not set
> -# CONFIG_DTLK is not set
> -# CONFIG_R3964 is not set
> -
> -#
> -# Ftape, the floppy tape device driver
> -#
> -# CONFIG_DRM is not set
> -
> -#
> -# PCMCIA character devices
> -#
> -# CONFIG_SYNCLINK_CS is not set
> -# CONFIG_RAW_DRIVER is not set
> -
> -#
> -# TPM devices
> -#
> -# CONFIG_TCG_TPM is not set
> -
> -#
> -# I2C support
> -#
> -# CONFIG_I2C is not set
> -
> -#
> -# Misc devices
> -#
> -
> -#
> -# Multimedia devices
> -#
> -# CONFIG_VIDEO_DEV is not set
> -
> -#
> -# Digital Video Broadcasting Devices
> -#
> -# CONFIG_DVB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_FB is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -
> -#
> -# Sound
> -#
> -# CONFIG_SOUND is not set
> -
> -#
> -# USB support
> -#
> -CONFIG_USB_ARCH_HAS_HCD=y
> -CONFIG_USB_ARCH_HAS_OHCI=y
> -# CONFIG_USB is not set
> -
> -#
> -# USB Gadget Support
> -#
> -CONFIG_USB_GADGET=y
> -# CONFIG_USB_GADGET_DEBUG_FILES is not set
> -# CONFIG_USB_GADGET_NET2280 is not set
> -CONFIG_USB_GADGET_PXA2XX=y
> -CONFIG_USB_PXA2XX=y
> -CONFIG_USB_PXA2XX_SMALL=y
> -# CONFIG_USB_GADGET_GOKU is not set
> -# CONFIG_USB_GADGET_SA1100 is not set
> -# CONFIG_USB_GADGET_LH7A40X is not set
> -# CONFIG_USB_GADGET_DUMMY_HCD is not set
> -# CONFIG_USB_GADGET_OMAP is not set
> -# CONFIG_USB_GADGET_DUALSPEED is not set
> -# CONFIG_USB_ZERO is not set
> -# CONFIG_USB_ETH is not set
> -# CONFIG_USB_GADGETFS is not set
> -# CONFIG_USB_FILE_STORAGE is not set
> -CONFIG_USB_G_SERIAL=y
> -
> -#
> -# MMC/SD Card support
> -#
> -# CONFIG_MMC is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT3_FS is not set
> -# CONFIG_JBD is not set
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -
> -#
> -# XFS support
> -#
> -# CONFIG_XFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_QUOTA is not set
> -CONFIG_DNOTIFY=y
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=y
> -CONFIG_MSDOS_FS=y
> -# CONFIG_VFAT_FS is not set
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_SYSFS=y
> -# CONFIG_DEVFS_FS is not set
> -# CONFIG_DEVPTS_FS_XATTR is not set
> -# CONFIG_TMPFS is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -CONFIG_RAMFS=y
> -
> -#
> -# Miscellaneous filesystems
> -#
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -# CONFIG_JFFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -# CONFIG_JFFS2_FS_NAND is not set
> -# CONFIG_JFFS2_FS_NOR_ECC is not set
> -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
> -CONFIG_JFFS2_ZLIB=y
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -
> -#
> -# Network File Systems
> -#
> -CONFIG_NFS_FS=y
> -# CONFIG_NFS_V3 is not set
> -# CONFIG_NFS_V4 is not set
> -# CONFIG_NFS_DIRECTIO is not set
> -# CONFIG_NFSD is not set
> -CONFIG_ROOT_NFS=y
> -CONFIG_LOCKD=y
> -CONFIG_SUNRPC=y
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -# CONFIG_CIFS is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -# CONFIG_PARTITION_ADVANCED is not set
> -CONFIG_MSDOS_PARTITION=y
> -
> -#
> -# Native Language Support
> -#
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -# CONFIG_NLS_CODEPAGE_437 is not set
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -# CONFIG_NLS_CODEPAGE_850 is not set
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -CONFIG_NLS_ISO8859_1=y
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -# CONFIG_NLS_ISO8859_15 is not set
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -# CONFIG_NLS_UTF8 is not set
> -
> -#
> -# Profiling support
> -#
> -# CONFIG_PROFILING is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_DEBUG_KERNEL=y
> -CONFIG_MAGIC_SYSRQ=y
> -CONFIG_LOG_BUF_SHIFT=14
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_DEBUG_SLAB is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -CONFIG_DEBUG_BUGVERBOSE=y
> -CONFIG_DEBUG_INFO=y
> -# CONFIG_DEBUG_FS is not set
> -CONFIG_FRAME_POINTER=y
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> -CONFIG_DEBUG_LL=y
> -# CONFIG_DEBUG_ICEDCC is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -
> -#
> -# Cryptographic options
> -#
> -# CONFIG_CRYPTO is not set
> -
> -#
> -# Hardware crypto devices
> -#
> -
> -#
> -# Library routines
> -#
> -# CONFIG_CRC_CCITT is not set
> -CONFIG_CRC32=y
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig
> deleted file mode 100644
> index 8e9a723..0000000
> --- a/arch/arm/configs/magician_defconfig
> +++ /dev/null
> @@ -1,1536 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.29-rc3
> -# Fri Jan 30 12:42:03 2009
> -#
> -CONFIG_ARM=y
> -CONFIG_HAVE_PWM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_MMU=y
> -# CONFIG_NO_IOPORT is not set
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -# CONFIG_ARCH_HAS_ILOG2_U32 is not set
> -# CONFIG_ARCH_HAS_ILOG2_U64 is not set
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_LOCK_KERNEL=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=""
> -CONFIG_LOCALVERSION_AUTO=y
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -
> -#
> -# RCU Subsystem
> -#
> -CONFIG_CLASSIC_RCU=y
> -# CONFIG_TREE_RCU is not set
> -# CONFIG_PREEMPT_RCU is not set
> -# CONFIG_TREE_RCU_TRACE is not set
> -# CONFIG_PREEMPT_RCU_TRACE is not set
> -CONFIG_IKCONFIG=y
> -CONFIG_IKCONFIG_PROC=y
> -CONFIG_LOG_BUF_SHIFT=16
> -# CONFIG_GROUP_SCHED is not set
> -# CONFIG_CGROUPS is not set
> -# CONFIG_SYSFS_DEPRECATED_V2 is not set
> -# CONFIG_RELAY is not set
> -# CONFIG_NAMESPACES is not set
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_INITRAMFS_SOURCE=""
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -CONFIG_EMBEDDED=y
> -# CONFIG_UID16 is not set
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_COMPAT_BRK=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_ANON_INODES=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -CONFIG_SHMEM=y
> -CONFIG_AIO=y
> -CONFIG_VM_EVENT_COUNTERS=y
> -CONFIG_SLAB=y
> -# CONFIG_SLUB is not set
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -CONFIG_HAVE_OPROFILE=y
> -# CONFIG_KPROBES is not set
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -CONFIG_HAVE_CLK=y
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_SLABINFO=y
> -CONFIG_RT_MUTEXES=y
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -# CONFIG_MODULE_FORCE_UNLOAD is not set
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -CONFIG_BLOCK=y
> -# CONFIG_LBD is not set
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_BLK_DEV_INTEGRITY is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -# CONFIG_IOSCHED_AS is not set
> -# CONFIG_IOSCHED_DEADLINE is not set
> -# CONFIG_IOSCHED_CFQ is not set
> -# CONFIG_DEFAULT_AS is not set
> -# CONFIG_DEFAULT_DEADLINE is not set
> -# CONFIG_DEFAULT_CFQ is not set
> -CONFIG_DEFAULT_NOOP=y
> -CONFIG_DEFAULT_IOSCHED="noop"
> -CONFIG_FREEZER=y
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_S3C64XX is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_MSM is not set
> -# CONFIG_ARCH_W90X900 is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -# CONFIG_ARCH_GUMSTIX is not set
> -# CONFIG_MACH_INTELMOTE2 is not set
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_MACH_MP900C is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_ARCH_VIPER is not set
> -# CONFIG_ARCH_PXA_ESERIES is not set
> -# CONFIG_TRIZEPS_PXA is not set
> -# CONFIG_MACH_H5000 is not set
> -# CONFIG_MACH_EM_X270 is not set
> -# CONFIG_MACH_COLIBRI is not set
> -# CONFIG_MACH_ZYLONITE is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_TAVOREVB is not set
> -# CONFIG_MACH_SAAR is not set
> -# CONFIG_MACH_ARMCORE is not set
> -# CONFIG_MACH_CM_X300 is not set
> -CONFIG_MACH_H4700=y
> -CONFIG_MACH_MAGICIAN=y
> -# CONFIG_MACH_MIOA701 is not set
> -# CONFIG_MACH_PCM027 is not set
> -# CONFIG_ARCH_PXA_PALM is not set
> -# CONFIG_PXA_EZX is not set
> -CONFIG_PXA27x=y
> -CONFIG_PXA_SSP=y
> -CONFIG_PXA_PWM=y
> -CONFIG_PXA_HAVE_BOARD_IRQS=y
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_PABRT_NOIFAR=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -# CONFIG_OUTER_CACHE is not set
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -CONFIG_COMMON_CLKDEV=y
> -
> -#
> -# Bus support
> -#
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -CONFIG_NO_HZ=y
> -# CONFIG_HIGH_RES_TIMERS is not set
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -CONFIG_VMSPLIT_3G=y
> -# CONFIG_VMSPLIT_2G is not set
> -# CONFIG_VMSPLIT_1G is not set
> -CONFIG_PAGE_OFFSET=0xC0000000
> -CONFIG_PREEMPT=y
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -CONFIG_ARCH_FLATMEM_HAS_HOLES=y
> -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -CONFIG_PAGEFLAGS_EXTENDED=y
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_PHYS_ADDR_T_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=0
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_UNEVICTABLE_LRU=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="keepinitrd"
> -# CONFIG_XIP_KERNEL is not set
> -CONFIG_KEXEC=y
> -CONFIG_ATAGS_PROC=y
> -
> -#
> -# CPU Power Management
> -#
> -CONFIG_CPU_FREQ=y
> -CONFIG_CPU_FREQ_TABLE=y
> -# CONFIG_CPU_FREQ_DEBUG is not set
> -CONFIG_CPU_FREQ_STAT=y
> -# CONFIG_CPU_FREQ_STAT_DETAILS is not set
> -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
> -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
> -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set
> -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set
> -CONFIG_CPU_FREQ_GOV_ONDEMAND=y
> -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
> -# CONFIG_CPU_IDLE is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> -CONFIG_HAVE_AOUT=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -CONFIG_PM=y
> -# CONFIG_PM_DEBUG is not set
> -CONFIG_PM_SLEEP=y
> -CONFIG_SUSPEND=y
> -CONFIG_SUSPEND_FREEZER=y
> -# CONFIG_APM_EMULATION is not set
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_COMPAT_NET_DEV_OPS=y
> -CONFIG_PACKET=y
> -CONFIG_PACKET_MMAP=y
> -CONFIG_UNIX=y
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -CONFIG_IP_MULTICAST=y
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -# CONFIG_IP_PNP_DHCP is not set
> -# CONFIG_IP_PNP_BOOTP is not set
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_IP_MROUTE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_BEET is not set
> -# CONFIG_INET_LRO is not set
> -# CONFIG_INET_DIAG is not set
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -# CONFIG_NETFILTER is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_NET_DSA is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_NET_SCHED is not set
> -# CONFIG_DCB is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -CONFIG_IRDA=m
> -
> -#
> -# IrDA protocols
> -#
> -CONFIG_IRLAN=m
> -# CONFIG_IRNET is not set
> -CONFIG_IRCOMM=m
> -CONFIG_IRDA_ULTRA=y
> -
> -#
> -# IrDA options
> -#
> -CONFIG_IRDA_CACHE_LAST_LSAP=y
> -CONFIG_IRDA_FAST_RR=y
> -CONFIG_IRDA_DEBUG=y
> -
> -#
> -# Infrared-port device drivers
> -#
> -
> -#
> -# SIR device drivers
> -#
> -CONFIG_IRTTY_SIR=m
> -
> -#
> -# Dongle support
> -#
> -# CONFIG_DONGLE is not set
> -# CONFIG_KINGSUN_DONGLE is not set
> -# CONFIG_KSDAZZLE_DONGLE is not set
> -# CONFIG_KS959_DONGLE is not set
> -
> -#
> -# FIR device drivers
> -#
> -# CONFIG_USB_IRDA is not set
> -# CONFIG_SIGMATEL_FIR is not set
> -CONFIG_PXA_FICP=m
> -# CONFIG_MCS_FIR is not set
> -CONFIG_BT=m
> -CONFIG_BT_L2CAP=m
> -CONFIG_BT_SCO=m
> -CONFIG_BT_RFCOMM=m
> -CONFIG_BT_RFCOMM_TTY=y
> -CONFIG_BT_BNEP=m
> -CONFIG_BT_BNEP_MC_FILTER=y
> -CONFIG_BT_BNEP_PROTO_FILTER=y
> -CONFIG_BT_HIDP=m
> -
> -#
> -# Bluetooth device drivers
> -#
> -CONFIG_BT_HCIBTUSB=m
> -# CONFIG_BT_HCIBTSDIO is not set
> -# CONFIG_BT_HCIUART is not set
> -# CONFIG_BT_HCIBCM203X is not set
> -# CONFIG_BT_HCIBPA10X is not set
> -# CONFIG_BT_HCIBFUSB is not set
> -# CONFIG_BT_HCIVHCI is not set
> -# CONFIG_AF_RXRPC is not set
> -# CONFIG_PHONET is not set
> -# CONFIG_WIRELESS is not set
> -# CONFIG_WIMAX is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=y
> -# CONFIG_FIRMWARE_IN_KERNEL is not set
> -CONFIG_EXTRA_FIRMWARE=""
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_DEBUG_DEVRES is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -# CONFIG_CONNECTOR is not set
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -# CONFIG_MTD_TESTS is not set
> -# CONFIG_MTD_REDBOOT_PARTS is not set
> -CONFIG_MTD_CMDLINE_PARTS=y
> -# CONFIG_MTD_AFS_PARTS is not set
> -# CONFIG_MTD_AR7_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_MTD_BLKDEVS=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -# CONFIG_MTD_JEDECPROBE is not set
> -CONFIG_MTD_GEN_PROBE=y
> -# CONFIG_MTD_CFI_ADV_OPTIONS is not set
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -# CONFIG_MTD_CFI_AMDSTD is not set
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> -CONFIG_MTD_PHYSMAP=y
> -# CONFIG_MTD_PHYSMAP_COMPAT is not set
> -# CONFIG_MTD_PXA2XX is not set
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -# CONFIG_MTD_NAND is not set
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# LPDDR flash memory drivers
> -#
> -# CONFIG_MTD_LPDDR is not set
> -# CONFIG_MTD_QINFO_PROBE is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -# CONFIG_BLK_DEV_LOOP is not set
> -# CONFIG_BLK_DEV_NBD is not set
> -# CONFIG_BLK_DEV_UB is not set
> -# CONFIG_BLK_DEV_RAM is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -# CONFIG_MISC_DEVICES is not set
> -CONFIG_HAVE_IDE=y
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -# CONFIG_SCSI is not set
> -# CONFIG_SCSI_DMA is not set
> -# CONFIG_SCSI_NETLINK is not set
> -# CONFIG_ATA is not set
> -# CONFIG_MD is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_MACVLAN is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -# CONFIG_VETH is not set
> -# CONFIG_NET_ETHERNET is not set
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -
> -#
> -# Wireless LAN
> -#
> -# CONFIG_WLAN_PRE80211 is not set
> -# CONFIG_WLAN_80211 is not set
> -# CONFIG_IWLWIFI_LEDS is not set
> -
> -#
> -# Enable WiMAX (Networking options) to see the WiMAX drivers
> -#
> -
> -#
> -# USB Network Adapters
> -#
> -# CONFIG_USB_CATC is not set
> -# CONFIG_USB_KAWETH is not set
> -# CONFIG_USB_PEGASUS is not set
> -# CONFIG_USB_RTL8150 is not set
> -# CONFIG_USB_USBNET is not set
> -# CONFIG_WAN is not set
> -CONFIG_PPP=m
> -# CONFIG_PPP_MULTILINK is not set
> -# CONFIG_PPP_FILTER is not set
> -CONFIG_PPP_ASYNC=m
> -# CONFIG_PPP_SYNC_TTY is not set
> -CONFIG_PPP_DEFLATE=m
> -CONFIG_PPP_BSDCOMP=m
> -CONFIG_PPP_MPPE=m
> -# CONFIG_PPPOE is not set
> -# CONFIG_PPPOL2TP is not set
> -# CONFIG_SLIP is not set
> -CONFIG_SLHC=m
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -# CONFIG_INPUT_MOUSEDEV is not set
> -# CONFIG_INPUT_JOYDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -# CONFIG_KEYBOARD_ATKBD is not set
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_KEYBOARD_STOWAWAY is not set
> -# CONFIG_KEYBOARD_PXA27x is not set
> -CONFIG_KEYBOARD_GPIO=y
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -# CONFIG_TOUCHSCREEN_FUJITSU is not set
> -# CONFIG_TOUCHSCREEN_GUNZE is not set
> -# CONFIG_TOUCHSCREEN_ELO is not set
> -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
> -# CONFIG_TOUCHSCREEN_MTOUCH is not set
> -# CONFIG_TOUCHSCREEN_INEXIO is not set
> -# CONFIG_TOUCHSCREEN_MK712 is not set
> -# CONFIG_TOUCHSCREEN_PENMOUNT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
> -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
> -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
> -# CONFIG_TOUCHSCREEN_TSC2007 is not set
> -CONFIG_INPUT_MISC=y
> -# CONFIG_INPUT_ATI_REMOTE is not set
> -# CONFIG_INPUT_ATI_REMOTE2 is not set
> -# CONFIG_INPUT_KEYSPAN_REMOTE is not set
> -# CONFIG_INPUT_POWERMATE is not set
> -# CONFIG_INPUT_YEALINK is not set
> -# CONFIG_INPUT_CM109 is not set
> -CONFIG_INPUT_UINPUT=m
> -
> -#
> -# Hardware I/O ports
> -#
> -# CONFIG_SERIO is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_CONSOLE_TRANSLATIONS=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -# CONFIG_DEVKMEM is not set
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -# CONFIG_SERIAL_PXA_CONSOLE is not set
> -CONFIG_SERIAL_CORE=y
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
> -# CONFIG_LEGACY_PTYS is not set
> -# CONFIG_IPMI_HANDLER is not set
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_NVRAM is not set
> -# CONFIG_R3964 is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -CONFIG_I2C=y
> -CONFIG_I2C_BOARDINFO=y
> -CONFIG_I2C_CHARDEV=m
> -CONFIG_I2C_HELPER_AUTO=y
> -
> -#
> -# I2C Hardware Bus support
> -#
> -
> -#
> -# I2C system bus drivers (mostly embedded / system-on-chip)
> -#
> -# CONFIG_I2C_GPIO is not set
> -# CONFIG_I2C_OCORES is not set
> -CONFIG_I2C_PXA=y
> -# CONFIG_I2C_PXA_SLAVE is not set
> -# CONFIG_I2C_SIMTEC is not set
> -
> -#
> -# External I2C/SMBus adapter drivers
> -#
> -# CONFIG_I2C_PARPORT_LIGHT is not set
> -# CONFIG_I2C_TAOS_EVM is not set
> -# CONFIG_I2C_TINY_USB is not set
> -
> -#
> -# Other I2C/SMBus bus drivers
> -#
> -# CONFIG_I2C_PCA_PLATFORM is not set
> -# CONFIG_I2C_STUB is not set
> -
> -#
> -# Miscellaneous I2C Chip support
> -#
> -# CONFIG_DS1682 is not set
> -# CONFIG_AT24 is not set
> -# CONFIG_EEPROM_LEGACY is not set
> -# CONFIG_SENSORS_PCF8574 is not set
> -# CONFIG_PCF8575 is not set
> -# CONFIG_SENSORS_PCA9539 is not set
> -# CONFIG_SENSORS_PCF8591 is not set
> -# CONFIG_SENSORS_MAX6875 is not set
> -# CONFIG_SENSORS_TSL2550 is not set
> -# CONFIG_I2C_DEBUG_CORE is not set
> -# CONFIG_I2C_DEBUG_ALGO is not set
> -# CONFIG_I2C_DEBUG_BUS is not set
> -# CONFIG_I2C_DEBUG_CHIP is not set
> -# CONFIG_SPI is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -# CONFIG_DEBUG_GPIO is not set
> -# CONFIG_GPIO_SYSFS is not set
> -
> -#
> -# Memory mapped GPIO expanders:
> -#
> -
> -#
> -# I2C GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX732X is not set
> -# CONFIG_GPIO_PCA953X is not set
> -# CONFIG_GPIO_PCF857X is not set
> -
> -#
> -# PCI GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -CONFIG_W1=y
> -
> -#
> -# 1-wire Bus Masters
> -#
> -# CONFIG_W1_MASTER_DS2490 is not set
> -# CONFIG_W1_MASTER_DS2482 is not set
> -CONFIG_W1_MASTER_DS1WM=y
> -# CONFIG_W1_MASTER_GPIO is not set
> -
> -#
> -# 1-wire Slaves
> -#
> -# CONFIG_W1_SLAVE_THERM is not set
> -# CONFIG_W1_SLAVE_SMEM is not set
> -# CONFIG_W1_SLAVE_DS2433 is not set
> -CONFIG_W1_SLAVE_DS2760=y
> -# CONFIG_W1_SLAVE_BQ27000 is not set
> -CONFIG_POWER_SUPPLY=y
> -# CONFIG_POWER_SUPPLY_DEBUG is not set
> -CONFIG_PDA_POWER=y
> -CONFIG_BATTERY_DS2760=y
> -# CONFIG_BATTERY_BQ27x00 is not set
> -# CONFIG_HWMON is not set
> -# CONFIG_THERMAL is not set
> -# CONFIG_THERMAL_HWMON is not set
> -# CONFIG_WATCHDOG is not set
> -CONFIG_SSB_POSSIBLE=y
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_CORE is not set
> -# CONFIG_MFD_SM501 is not set
> -CONFIG_MFD_ASIC3=y
> -CONFIG_HTC_EGPIO=y
> -CONFIG_HTC_PASIC3=y
> -# CONFIG_TPS65010 is not set
> -# CONFIG_TWL4030_CORE is not set
> -# CONFIG_MFD_TMIO is not set
> -# CONFIG_MFD_T7L66XB is not set
> -# CONFIG_MFD_TC6387XB is not set
> -# CONFIG_MFD_TC6393XB is not set
> -# CONFIG_PMIC_DA903X is not set
> -# CONFIG_MFD_WM8400 is not set
> -# CONFIG_MFD_WM8350_I2C is not set
> -# CONFIG_MFD_PCF50633 is not set
> -
> -#
> -# Multimedia devices
> -#
> -
> -#
> -# Multimedia core support
> -#
> -# CONFIG_VIDEO_DEV is not set
> -# CONFIG_DVB_CORE is not set
> -# CONFIG_VIDEO_MEDIA is not set
> -
> -#
> -# Multimedia drivers
> -#
> -# CONFIG_DAB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -CONFIG_FB=y
> -# CONFIG_FIRMWARE_EDID is not set
> -# CONFIG_FB_DDC is not set
> -# CONFIG_FB_BOOT_VESA_SUPPORT is not set
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> -# CONFIG_FB_SYS_FILLRECT is not set
> -# CONFIG_FB_SYS_COPYAREA is not set
> -# CONFIG_FB_SYS_IMAGEBLIT is not set
> -# CONFIG_FB_FOREIGN_ENDIAN is not set
> -# CONFIG_FB_SYS_FOPS is not set
> -# CONFIG_FB_SVGALIB is not set
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -
> -#
> -# Frame buffer hardware drivers
> -#
> -# CONFIG_FB_S1D13XXX is not set
> -CONFIG_FB_PXA=y
> -CONFIG_FB_PXA_OVERLAY=y
> -# CONFIG_FB_PXA_SMARTPANEL is not set
> -# CONFIG_FB_PXA_PARAMETERS is not set
> -# CONFIG_FB_MBX is not set
> -CONFIG_FB_W100=y
> -# CONFIG_FB_VIRTUAL is not set
> -# CONFIG_FB_METRONOME is not set
> -# CONFIG_FB_MB862XX is not set
> -CONFIG_BACKLIGHT_LCD_SUPPORT=y
> -CONFIG_LCD_CLASS_DEVICE=y
> -# CONFIG_LCD_ILI9320 is not set
> -# CONFIG_LCD_PLATFORM is not set
> -CONFIG_BACKLIGHT_CLASS_DEVICE=y
> -# CONFIG_BACKLIGHT_GENERIC is not set
> -CONFIG_BACKLIGHT_PWM=y
> -
> -#
> -# Display device support
> -#
> -CONFIG_DISPLAY_SUPPORT=y
> -
> -#
> -# Display hardware drivers
> -#
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
> -CONFIG_FONTS=y
> -# CONFIG_FONT_8x8 is not set
> -# CONFIG_FONT_8x16 is not set
> -# CONFIG_FONT_6x11 is not set
> -# CONFIG_FONT_7x14 is not set
> -# CONFIG_FONT_PEARL_8x8 is not set
> -# CONFIG_FONT_ACORN_8x8 is not set
> -CONFIG_FONT_MINI_4x6=y
> -# CONFIG_FONT_SUN8x16 is not set
> -# CONFIG_FONT_SUN12x22 is not set
> -# CONFIG_FONT_10x18 is not set
> -# CONFIG_LOGO is not set
> -CONFIG_SOUND=y
> -CONFIG_SOUND_OSS_CORE=y
> -CONFIG_SND=m
> -CONFIG_SND_TIMER=m
> -CONFIG_SND_PCM=m
> -# CONFIG_SND_SEQUENCER is not set
> -CONFIG_SND_OSSEMUL=y
> -CONFIG_SND_MIXER_OSS=m
> -CONFIG_SND_PCM_OSS=m
> -CONFIG_SND_PCM_OSS_PLUGINS=y
> -# CONFIG_SND_DYNAMIC_MINORS is not set
> -CONFIG_SND_SUPPORT_OLD_API=y
> -CONFIG_SND_VERBOSE_PROCFS=y
> -# CONFIG_SND_VERBOSE_PRINTK is not set
> -# CONFIG_SND_DEBUG is not set
> -CONFIG_SND_DRIVERS=y
> -# CONFIG_SND_DUMMY is not set
> -# CONFIG_SND_MTPAV is not set
> -# CONFIG_SND_SERIAL_U16550 is not set
> -# CONFIG_SND_MPU401 is not set
> -# CONFIG_SND_ARM is not set
> -CONFIG_SND_PXA2XX_LIB=m
> -# CONFIG_SND_USB is not set
> -CONFIG_SND_SOC=m
> -CONFIG_SND_PXA2XX_SOC=m
> -CONFIG_SND_SOC_I2C_AND_SPI=m
> -# CONFIG_SND_SOC_ALL_CODECS is not set
> -# CONFIG_SOUND_PRIME is not set
> -# CONFIG_HID_SUPPORT is not set
> -CONFIG_HID=m
> -CONFIG_USB_SUPPORT=y
> -CONFIG_USB_ARCH_HAS_HCD=y
> -CONFIG_USB_ARCH_HAS_OHCI=y
> -# CONFIG_USB_ARCH_HAS_EHCI is not set
> -CONFIG_USB=y
> -# CONFIG_USB_DEBUG is not set
> -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
> -
> -#
> -# Miscellaneous USB options
> -#
> -# CONFIG_USB_DEVICEFS is not set
> -# CONFIG_USB_DEVICE_CLASS is not set
> -# CONFIG_USB_DYNAMIC_MINORS is not set
> -# CONFIG_USB_SUSPEND is not set
> -# CONFIG_USB_OTG is not set
> -# CONFIG_USB_OTG_WHITELIST is not set
> -# CONFIG_USB_OTG_BLACKLIST_HUB is not set
> -CONFIG_USB_MON=m
> -# CONFIG_USB_WUSB is not set
> -# CONFIG_USB_WUSB_CBAF is not set
> -
> -#
> -# USB Host Controller Drivers
> -#
> -# CONFIG_USB_C67X00_HCD is not set
> -# CONFIG_USB_OXU210HP_HCD is not set
> -# CONFIG_USB_ISP116X_HCD is not set
> -CONFIG_USB_OHCI_HCD=y
> -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
> -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
> -CONFIG_USB_OHCI_LITTLE_ENDIAN=y
> -# CONFIG_USB_SL811_HCD is not set
> -# CONFIG_USB_R8A66597_HCD is not set
> -# CONFIG_USB_HWA_HCD is not set
> -# CONFIG_USB_MUSB_HDRC is not set
> -# CONFIG_USB_GADGET_MUSB_HDRC is not set
> -
> -#
> -# USB Device Class drivers
> -#
> -# CONFIG_USB_ACM is not set
> -# CONFIG_USB_PRINTER is not set
> -# CONFIG_USB_WDM is not set
> -# CONFIG_USB_TMC is not set
> -
> -#
> -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed;
> -#
> -
> -#
> -# see USB_STORAGE Help for more information
> -#
> -# CONFIG_USB_LIBUSUAL is not set
> -
> -#
> -# USB Imaging devices
> -#
> -# CONFIG_USB_MDC800 is not set
> -
> -#
> -# USB port drivers
> -#
> -# CONFIG_USB_SERIAL is not set
> -
> -#
> -# USB Miscellaneous drivers
> -#
> -# CONFIG_USB_EMI62 is not set
> -# CONFIG_USB_EMI26 is not set
> -# CONFIG_USB_ADUTUX is not set
> -# CONFIG_USB_SEVSEG is not set
> -# CONFIG_USB_RIO500 is not set
> -# CONFIG_USB_LEGOTOWER is not set
> -# CONFIG_USB_LCD is not set
> -# CONFIG_USB_BERRY_CHARGE is not set
> -# CONFIG_USB_LED is not set
> -# CONFIG_USB_CYPRESS_CY7C63 is not set
> -# CONFIG_USB_CYTHERM is not set
> -# CONFIG_USB_PHIDGET is not set
> -# CONFIG_USB_IDMOUSE is not set
> -# CONFIG_USB_FTDI_ELAN is not set
> -# CONFIG_USB_APPLEDISPLAY is not set
> -# CONFIG_USB_LD is not set
> -# CONFIG_USB_TRANCEVIBRATOR is not set
> -# CONFIG_USB_IOWARRIOR is not set
> -# CONFIG_USB_ISIGHTFW is not set
> -# CONFIG_USB_VST is not set
> -CONFIG_USB_GADGET=y
> -# CONFIG_USB_GADGET_DEBUG is not set
> -# CONFIG_USB_GADGET_DEBUG_FILES is not set
> -CONFIG_USB_GADGET_VBUS_DRAW=500
> -CONFIG_USB_GADGET_SELECTED=y
> -# CONFIG_USB_GADGET_AT91 is not set
> -# CONFIG_USB_GADGET_ATMEL_USBA is not set
> -# CONFIG_USB_GADGET_FSL_USB2 is not set
> -# CONFIG_USB_GADGET_LH7A40X is not set
> -# CONFIG_USB_GADGET_OMAP is not set
> -# CONFIG_USB_GADGET_PXA25X is not set
> -CONFIG_USB_GADGET_PXA27X=y
> -CONFIG_USB_PXA27X=y
> -# CONFIG_USB_GADGET_S3C2410 is not set
> -# CONFIG_USB_GADGET_IMX is not set
> -# CONFIG_USB_GADGET_M66592 is not set
> -# CONFIG_USB_GADGET_AMD5536UDC is not set
> -# CONFIG_USB_GADGET_FSL_QE is not set
> -# CONFIG_USB_GADGET_CI13XXX is not set
> -# CONFIG_USB_GADGET_NET2280 is not set
> -# CONFIG_USB_GADGET_GOKU is not set
> -# CONFIG_USB_GADGET_DUMMY_HCD is not set
> -# CONFIG_USB_GADGET_DUALSPEED is not set
> -# CONFIG_USB_ZERO is not set
> -CONFIG_USB_ETH=m
> -# CONFIG_USB_ETH_RNDIS is not set
> -CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> -# CONFIG_USB_FILE_STORAGE_TEST is not set
> -CONFIG_USB_G_SERIAL=m
> -# CONFIG_USB_MIDI_GADGET is not set
> -# CONFIG_USB_G_PRINTER is not set
> -CONFIG_USB_CDC_COMPOSITE=m
> -
> -#
> -# OTG and related infrastructure
> -#
> -CONFIG_USB_OTG_UTILS=y
> -CONFIG_USB_GPIO_VBUS=y
> -CONFIG_MMC=y
> -# CONFIG_MMC_DEBUG is not set
> -# CONFIG_MMC_UNSAFE_RESUME is not set
> -
> -#
> -# MMC/SD/SDIO Card Drivers
> -#
> -CONFIG_MMC_BLOCK=y
> -CONFIG_MMC_BLOCK_BOUNCE=y
> -CONFIG_SDIO_UART=m
> -# CONFIG_MMC_TEST is not set
> -
> -#
> -# MMC/SD/SDIO Host Controller Drivers
> -#
> -CONFIG_MMC_PXA=y
> -# CONFIG_MMC_SDHCI is not set
> -# CONFIG_MEMSTICK is not set
> -# CONFIG_ACCESSIBILITY is not set
> -CONFIG_NEW_LEDS=y
> -CONFIG_LEDS_CLASS=y
> -
> -#
> -# LED drivers
> -#
> -# CONFIG_LEDS_PCA9532 is not set
> -CONFIG_LEDS_GPIO=y
> -# CONFIG_LEDS_PCA955X is not set
> -
> -#
> -# LED Triggers
> -#
> -CONFIG_LEDS_TRIGGERS=y
> -# CONFIG_LEDS_TRIGGER_TIMER is not set
> -# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set
> -CONFIG_LEDS_TRIGGER_BACKLIGHT=y
> -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_HCTOSYS=y
> -CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
> -CONFIG_RTC_DEBUG=y
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -# CONFIG_RTC_DRV_TEST is not set
> -
> -#
> -# I2C RTC drivers
> -#
> -# CONFIG_RTC_DRV_DS1307 is not set
> -# CONFIG_RTC_DRV_DS1374 is not set
> -# CONFIG_RTC_DRV_DS1672 is not set
> -# CONFIG_RTC_DRV_MAX6900 is not set
> -# CONFIG_RTC_DRV_RS5C372 is not set
> -# CONFIG_RTC_DRV_ISL1208 is not set
> -# CONFIG_RTC_DRV_X1205 is not set
> -# CONFIG_RTC_DRV_PCF8563 is not set
> -# CONFIG_RTC_DRV_PCF8583 is not set
> -# CONFIG_RTC_DRV_M41T80 is not set
> -# CONFIG_RTC_DRV_S35390A is not set
> -# CONFIG_RTC_DRV_FM3130 is not set
> -# CONFIG_RTC_DRV_RX8581 is not set
> -
> -#
> -# SPI RTC drivers
> -#
> -
> -#
> -# Platform RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_DS1286 is not set
> -# CONFIG_RTC_DRV_DS1511 is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_STK17TA8 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -# CONFIG_RTC_DRV_M48T35 is not set
> -# CONFIG_RTC_DRV_M48T59 is not set
> -# CONFIG_RTC_DRV_BQ4802 is not set
> -# CONFIG_RTC_DRV_V3020 is not set
> -
> -#
> -# on-CPU RTC drivers
> -#
> -CONFIG_RTC_DRV_SA1100=y
> -# CONFIG_RTC_DRV_PXA is not set
> -# CONFIG_DMADEVICES is not set
> -CONFIG_REGULATOR=y
> -# CONFIG_REGULATOR_DEBUG is not set
> -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
> -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
> -CONFIG_REGULATOR_BQ24022=y
> -# CONFIG_UIO is not set
> -# CONFIG_STAGING is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -# CONFIG_EXT3_FS is not set
> -# CONFIG_EXT4_FS is not set
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -# CONFIG_FS_POSIX_ACL is not set
> -CONFIG_FILE_LOCKING=y
> -# CONFIG_XFS_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_BTRFS_FS is not set
> -CONFIG_DNOTIFY=y
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=m
> -CONFIG_MSDOS_FS=m
> -CONFIG_VFAT_FS=m
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_PROC_PAGE_MONITOR=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -CONFIG_MISC_FILESYSTEMS=y
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
> -# CONFIG_JFFS2_SUMMARY is not set
> -# CONFIG_JFFS2_FS_XATTR is not set
> -CONFIG_JFFS2_COMPRESSION_OPTIONS=y
> -CONFIG_JFFS2_ZLIB=y
> -CONFIG_JFFS2_LZO=y
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_JFFS2_CMODE_NONE is not set
> -CONFIG_JFFS2_CMODE_PRIORITY=y
> -# CONFIG_JFFS2_CMODE_SIZE is not set
> -# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_SQUASHFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_OMFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -CONFIG_NETWORK_FILESYSTEMS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -# CONFIG_NFS_V3_ACL is not set
> -# CONFIG_NFS_V4 is not set
> -CONFIG_ROOT_NFS=y
> -# CONFIG_NFSD is not set
> -CONFIG_LOCKD=y
> -CONFIG_LOCKD_V4=y
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=y
> -# CONFIG_SUNRPC_REGISTER_V4 is not set
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -# CONFIG_CIFS is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -# CONFIG_PARTITION_ADVANCED is not set
> -CONFIG_MSDOS_PARTITION=y
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="utf8"
> -CONFIG_NLS_CODEPAGE_437=y
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -# CONFIG_NLS_CODEPAGE_850 is not set
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -CONFIG_NLS_CODEPAGE_1251=m
> -# CONFIG_NLS_ASCII is not set
> -CONFIG_NLS_ISO8859_1=y
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -# CONFIG_NLS_ISO8859_15 is not set
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -CONFIG_NLS_UTF8=y
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -CONFIG_PRINTK_TIME=y
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_FRAME_WARN=1024
> -# CONFIG_MAGIC_SYSRQ is not set
> -# CONFIG_UNUSED_SYMBOLS is not set
> -# CONFIG_DEBUG_FS is not set
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DEBUG_SHIRQ is not set
> -CONFIG_DETECT_SOFTLOCKUP=y
> -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
> -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
> -# CONFIG_SCHED_DEBUG is not set
> -# CONFIG_SCHEDSTATS is not set
> -CONFIG_TIMER_STATS=y
> -# CONFIG_DEBUG_OBJECTS is not set
> -# CONFIG_DEBUG_SLAB is not set
> -# CONFIG_DEBUG_PREEMPT is not set
> -# CONFIG_DEBUG_RT_MUTEXES is not set
> -# CONFIG_RT_MUTEX_TESTER is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -# CONFIG_DEBUG_MUTEXES is not set
> -# CONFIG_DEBUG_LOCK_ALLOC is not set
> -# CONFIG_PROVE_LOCKING is not set
> -# CONFIG_LOCK_STAT is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -CONFIG_DEBUG_BUGVERBOSE=y
> -# CONFIG_DEBUG_INFO is not set
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_WRITECOUNT is not set
> -# CONFIG_DEBUG_MEMORY_INIT is not set
> -# CONFIG_DEBUG_LIST is not set
> -# CONFIG_DEBUG_SG is not set
> -# CONFIG_DEBUG_NOTIFIERS is not set
> -CONFIG_FRAME_POINTER=y
> -# CONFIG_BOOT_PRINTK_DELAY is not set
> -# CONFIG_RCU_TORTURE_TEST is not set
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -# CONFIG_BACKTRACE_SELF_TEST is not set
> -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
> -# CONFIG_FAULT_INJECTION is not set
> -# CONFIG_LATENCYTOP is not set
> -# CONFIG_SYSCTL_SYSCALL_CHECK is not set
> -CONFIG_HAVE_FUNCTION_TRACER=y
> -
> -#
> -# Tracers
> -#
> -# CONFIG_FUNCTION_TRACER is not set
> -# CONFIG_IRQSOFF_TRACER is not set
> -# CONFIG_PREEMPT_TRACER is not set
> -# CONFIG_SCHED_TRACER is not set
> -# CONFIG_CONTEXT_SWITCH_TRACER is not set
> -# CONFIG_BOOT_TRACER is not set
> -# CONFIG_TRACE_BRANCH_PROFILING is not set
> -# CONFIG_STACK_TRACER is not set
> -# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -# CONFIG_KGDB is not set
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> -# CONFIG_DEBUG_STACK_USAGE is not set
> -CONFIG_DEBUG_LL=y
> -# CONFIG_DEBUG_ICEDCC is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITYFS is not set
> -# CONFIG_SECURITY_FILE_CAPABILITIES is not set
> -CONFIG_CRYPTO=y
> -
> -#
> -# Crypto core or helper
> -#
> -# CONFIG_CRYPTO_FIPS is not set
> -CONFIG_CRYPTO_ALGAPI=m
> -CONFIG_CRYPTO_ALGAPI2=m
> -CONFIG_CRYPTO_AEAD2=m
> -CONFIG_CRYPTO_BLKCIPHER=m
> -CONFIG_CRYPTO_BLKCIPHER2=m
> -CONFIG_CRYPTO_HASH=m
> -CONFIG_CRYPTO_HASH2=m
> -CONFIG_CRYPTO_RNG2=m
> -CONFIG_CRYPTO_MANAGER=m
> -CONFIG_CRYPTO_MANAGER2=m
> -# CONFIG_CRYPTO_GF128MUL is not set
> -# CONFIG_CRYPTO_NULL is not set
> -# CONFIG_CRYPTO_CRYPTD is not set
> -# CONFIG_CRYPTO_AUTHENC is not set
> -# CONFIG_CRYPTO_TEST is not set
> -
> -#
> -# Authenticated Encryption with Associated Data
> -#
> -# CONFIG_CRYPTO_CCM is not set
> -# CONFIG_CRYPTO_GCM is not set
> -# CONFIG_CRYPTO_SEQIV is not set
> -
> -#
> -# Block modes
> -#
> -# CONFIG_CRYPTO_CBC is not set
> -# CONFIG_CRYPTO_CTR is not set
> -# CONFIG_CRYPTO_CTS is not set
> -CONFIG_CRYPTO_ECB=m
> -# CONFIG_CRYPTO_LRW is not set
> -# CONFIG_CRYPTO_PCBC is not set
> -# CONFIG_CRYPTO_XTS is not set
> -
> -#
> -# Hash modes
> -#
> -# CONFIG_CRYPTO_HMAC is not set
> -# CONFIG_CRYPTO_XCBC is not set
> -
> -#
> -# Digest
> -#
> -# CONFIG_CRYPTO_CRC32C is not set
> -# CONFIG_CRYPTO_MD4 is not set
> -# CONFIG_CRYPTO_MD5 is not set
> -# CONFIG_CRYPTO_MICHAEL_MIC is not set
> -# CONFIG_CRYPTO_RMD128 is not set
> -# CONFIG_CRYPTO_RMD160 is not set
> -# CONFIG_CRYPTO_RMD256 is not set
> -# CONFIG_CRYPTO_RMD320 is not set
> -CONFIG_CRYPTO_SHA1=m
> -# CONFIG_CRYPTO_SHA256 is not set
> -# CONFIG_CRYPTO_SHA512 is not set
> -# CONFIG_CRYPTO_TGR192 is not set
> -# CONFIG_CRYPTO_WP512 is not set
> -
> -#
> -# Ciphers
> -#
> -# CONFIG_CRYPTO_AES is not set
> -# CONFIG_CRYPTO_ANUBIS is not set
> -CONFIG_CRYPTO_ARC4=m
> -# CONFIG_CRYPTO_BLOWFISH is not set
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -# CONFIG_CRYPTO_CAST5 is not set
> -# CONFIG_CRYPTO_CAST6 is not set
> -# CONFIG_CRYPTO_DES is not set
> -# CONFIG_CRYPTO_FCRYPT is not set
> -# CONFIG_CRYPTO_KHAZAD is not set
> -# CONFIG_CRYPTO_SALSA20 is not set
> -# CONFIG_CRYPTO_SEED is not set
> -# CONFIG_CRYPTO_SERPENT is not set
> -# CONFIG_CRYPTO_TEA is not set
> -# CONFIG_CRYPTO_TWOFISH is not set
> -
> -#
> -# Compression
> -#
> -# CONFIG_CRYPTO_DEFLATE is not set
> -# CONFIG_CRYPTO_LZO is not set
> -
> -#
> -# Random Number Generation
> -#
> -# CONFIG_CRYPTO_ANSI_CPRNG is not set
> -# CONFIG_CRYPTO_HW is not set
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -CONFIG_GENERIC_FIND_LAST_BIT=y
> -CONFIG_CRC_CCITT=y
> -# CONFIG_CRC16 is not set
> -# CONFIG_CRC_T10DIF is not set
> -# CONFIG_CRC_ITU_T is not set
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_LZO_COMPRESS=y
> -CONFIG_LZO_DECOMPRESS=y
> -CONFIG_PLIST=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> diff --git a/arch/arm/configs/mainstone_defconfig b/arch/arm/configs/mainstone_defconfig
> deleted file mode 100644
> index 1cddb61..0000000
> --- a/arch/arm/configs/mainstone_defconfig
> +++ /dev/null
> @@ -1,794 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.12-rc1-bk2
> -# Sat Mar 26 20:00:45 2005
> -#
> -CONFIG_ARM=y
> -CONFIG_MMU=y
> -CONFIG_UID16=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_GENERIC_IOMAP=y
> -
> -#
> -# Code maturity level options
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_CLEAN_COMPILE=y
> -CONFIG_BROKEN_ON_SMP=y
> -
> -#
> -# General setup
> -#
> -CONFIG_LOCALVERSION=""
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -CONFIG_SYSCTL=y
> -# CONFIG_AUDIT is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_KOBJECT_UEVENT=y
> -# CONFIG_IKCONFIG is not set
> -# CONFIG_EMBEDDED is not set
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_EPOLL=y
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SHMEM=y
> -CONFIG_CC_ALIGN_FUNCTIONS=0
> -CONFIG_CC_ALIGN_LABELS=0
> -CONFIG_CC_ALIGN_LOOPS=0
> -CONFIG_CC_ALIGN_JUMPS=0
> -# CONFIG_TINY_SHMEM is not set
> -CONFIG_BASE_SMALL=0
> -
> -#
> -# Loadable module support
> -#
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_UNLOAD is not set
> -CONFIG_OBSOLETE_MODPARM=y
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -# CONFIG_KMOD is not set
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_CLPS7500 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_CO285 is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_IOP3XX is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_L7200 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_H720X is not set
> -
> -#
> -# Intel PXA2xx Implementations
> -#
> -# CONFIG_ARCH_LUBBOCK is not set
> -CONFIG_MACH_MAINSTONE=y
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -CONFIG_PXA27x=y
> -CONFIG_IWMMXT=y
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_MINICACHE=y
> -
> -#
> -# Processor Features
> -#
> -# CONFIG_ARM_THUMB is not set
> -CONFIG_XSCALE_PMU=y
> -
> -#
> -# Bus support
> -#
> -
> -#
> -# PCCARD (PCMCIA/CardBus) support
> -#
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -# CONFIG_PREEMPT is not set
> -CONFIG_LEDS=y
> -CONFIG_LEDS_TIMER=y
> -CONFIG_LEDS_CPU=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M"
> -# CONFIG_XIP_KERNEL is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -# CONFIG_ARTHUR is not set
> -
> -#
> -# Power management options
> -#
> -# CONFIG_PM is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -# CONFIG_FW_LOADER is not set
> -# CONFIG_DEBUG_DRIVER is not set
> -
> -#
> -# Memory Technology Devices (MTD)
> -#
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -CONFIG_MTD_REDBOOT_PARTS=y
> -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
> -# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
> -# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
> -# CONFIG_MTD_CMDLINE_PARTS is not set
> -# CONFIG_MTD_AFS_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -# CONFIG_MTD_JEDECPROBE is not set
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_NOSWAP=y
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> -CONFIG_MTD_CFI_GEOMETRY=y
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -# CONFIG_MTD_CFI_I1 is not set
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -# CONFIG_MTD_CFI_AMDSTD is not set
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> -# CONFIG_MTD_PHYSMAP is not set
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_EDB7312 is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLKMTD is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -
> -#
> -# NAND Flash Device Drivers
> -#
> -# CONFIG_MTD_NAND is not set
> -
> -#
> -# Parallel port support
> -#
> -# CONFIG_PARPORT is not set
> -
> -#
> -# Plug and Play support
> -#
> -
> -#
> -# Block devices
> -#
> -# CONFIG_BLK_DEV_FD is not set
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -# CONFIG_BLK_DEV_LOOP is not set
> -# CONFIG_BLK_DEV_NBD is not set
> -# CONFIG_BLK_DEV_RAM is not set
> -CONFIG_BLK_DEV_RAM_COUNT=16
> -CONFIG_INITRAMFS_SOURCE=""
> -# CONFIG_CDROM_PKTCDVD is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_AS=y
> -CONFIG_IOSCHED_DEADLINE=y
> -CONFIG_IOSCHED_CFQ=y
> -# CONFIG_ATA_OVER_ETH is not set
> -
> -#
> -# ATA/ATAPI/MFM/RLL support
> -#
> -CONFIG_IDE=y
> -CONFIG_BLK_DEV_IDE=y
> -
> -#
> -# Please see Documentation/ide.txt for help/info on IDE drives
> -#
> -# CONFIG_BLK_DEV_IDE_SATA is not set
> -CONFIG_BLK_DEV_IDEDISK=y
> -# CONFIG_IDEDISK_MULTI_MODE is not set
> -# CONFIG_BLK_DEV_IDECD is not set
> -# CONFIG_BLK_DEV_IDETAPE is not set
> -# CONFIG_BLK_DEV_IDEFLOPPY is not set
> -# CONFIG_IDE_TASK_IOCTL is not set
> -
> -#
> -# IDE chipset support/bugfixes
> -#
> -# CONFIG_IDE_GENERIC is not set
> -# CONFIG_IDE_ARM is not set
> -# CONFIG_BLK_DEV_IDEDMA is not set
> -# CONFIG_IDEDMA_AUTO is not set
> -# CONFIG_BLK_DEV_HD is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_SCSI is not set
> -
> -#
> -# Multi-device support (RAID and LVM)
> -#
> -# CONFIG_MD is not set
> -
> -#
> -# Fusion MPT device support
> -#
> -
> -#
> -# IEEE 1394 (FireWire) support
> -#
> -
> -#
> -# I2O device support
> -#
> -
> -#
> -# Networking support
> -#
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -# CONFIG_PACKET is not set
> -# CONFIG_NETLINK_DEV is not set
> -CONFIG_UNIX=y
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_PNP=y
> -# CONFIG_IP_PNP_DHCP is not set
> -CONFIG_IP_PNP_BOOTP=y
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_TUNNEL is not set
> -CONFIG_IP_TCPDIAG=y
> -# CONFIG_IP_TCPDIAG_IPV6 is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETFILTER is not set
> -
> -#
> -# SCTP Configuration (EXPERIMENTAL)
> -#
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_NET_DIVERT is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -
> -#
> -# QoS and/or fair queueing
> -#
> -# CONFIG_NET_SCHED is not set
> -# CONFIG_NET_CLS_ROUTE is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_IRDA is not set
> -# CONFIG_BT is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -
> -#
> -# Ethernet (10 or 100Mbit)
> -#
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=y
> -CONFIG_SMC91X=y
> -
> -#
> -# Ethernet (1000 Mbit)
> -#
> -
> -#
> -# Ethernet (10000 Mbit)
> -#
> -
> -#
> -# Token Ring devices
> -#
> -
> -#
> -# Wireless LAN (non-hamradio)
> -#
> -# CONFIG_NET_RADIO is not set
> -
> -#
> -# Wan interfaces
> -#
> -# CONFIG_WAN is not set
> -# CONFIG_PPP is not set
> -# CONFIG_SLIP is not set
> -# CONFIG_SHAPER is not set
> -# CONFIG_NETCONSOLE is not set
> -
> -#
> -# ISDN subsystem
> -#
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -CONFIG_INPUT_MOUSEDEV_PSAUX=y
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> -# CONFIG_INPUT_JOYDEV is not set
> -# CONFIG_INPUT_TSDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -CONFIG_KEYBOARD_ATKBD=y
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TOUCHSCREEN is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -CONFIG_SERIO=y
> -# CONFIG_SERIO_SERPORT is not set
> -CONFIG_SERIO_LIBPS2=y
> -# CONFIG_SERIO_RAW is not set
> -# CONFIG_GAMEPORT is not set
> -CONFIG_SOUND_GAMEPORT=y
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=256
> -
> -#
> -# IPMI
> -#
> -# CONFIG_IPMI_HANDLER is not set
> -
> -#
> -# Watchdog Cards
> -#
> -# CONFIG_WATCHDOG is not set
> -# CONFIG_NVRAM is not set
> -# CONFIG_RTC is not set
> -# CONFIG_DTLK is not set
> -# CONFIG_R3964 is not set
> -
> -#
> -# Ftape, the floppy tape device driver
> -#
> -# CONFIG_DRM is not set
> -# CONFIG_RAW_DRIVER is not set
> -
> -#
> -# TPM devices
> -#
> -# CONFIG_TCG_TPM is not set
> -
> -#
> -# I2C support
> -#
> -# CONFIG_I2C is not set
> -
> -#
> -# Misc devices
> -#
> -
> -#
> -# Multimedia devices
> -#
> -# CONFIG_VIDEO_DEV is not set
> -
> -#
> -# Digital Video Broadcasting Devices
> -#
> -# CONFIG_DVB is not set
> -
> -#
> -# Graphics support
> -#
> -CONFIG_FB=y
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -CONFIG_FB_SOFT_CURSOR=y
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -CONFIG_FB_PXA=y
> -# CONFIG_FB_PXA_PARAMETERS is not set
> -# CONFIG_FB_VIRTUAL is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -# CONFIG_FONTS is not set
> -CONFIG_FONT_8x8=y
> -CONFIG_FONT_8x16=y
> -
> -#
> -# Logo configuration
> -#
> -CONFIG_LOGO=y
> -CONFIG_LOGO_LINUX_MONO=y
> -CONFIG_LOGO_LINUX_VGA16=y
> -CONFIG_LOGO_LINUX_CLUT224=y
> -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
> -
> -#
> -# Sound
> -#
> -# CONFIG_SOUND is not set
> -
> -#
> -# USB support
> -#
> -CONFIG_USB_ARCH_HAS_HCD=y
> -CONFIG_USB_ARCH_HAS_OHCI=y
> -# CONFIG_USB is not set
> -
> -#
> -# USB Gadget Support
> -#
> -# CONFIG_USB_GADGET is not set
> -
> -#
> -# MMC/SD Card support
> -#
> -# CONFIG_MMC is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT3_FS is not set
> -# CONFIG_JBD is not set
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -
> -#
> -# XFS support
> -#
> -# CONFIG_XFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_QUOTA is not set
> -CONFIG_DNOTIFY=y
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=y
> -CONFIG_MSDOS_FS=y
> -# CONFIG_VFAT_FS is not set
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_SYSFS=y
> -# CONFIG_DEVFS_FS is not set
> -# CONFIG_DEVPTS_FS_XATTR is not set
> -# CONFIG_TMPFS is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -CONFIG_RAMFS=y
> -
> -#
> -# Miscellaneous filesystems
> -#
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -# CONFIG_JFFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -# CONFIG_JFFS2_FS_NAND is not set
> -# CONFIG_JFFS2_FS_NOR_ECC is not set
> -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
> -CONFIG_JFFS2_ZLIB=y
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -
> -#
> -# Network File Systems
> -#
> -CONFIG_NFS_FS=y
> -# CONFIG_NFS_V3 is not set
> -# CONFIG_NFS_V4 is not set
> -# CONFIG_NFS_DIRECTIO is not set
> -# CONFIG_NFSD is not set
> -CONFIG_ROOT_NFS=y
> -CONFIG_LOCKD=y
> -CONFIG_SUNRPC=y
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -# CONFIG_CIFS is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -# CONFIG_PARTITION_ADVANCED is not set
> -CONFIG_MSDOS_PARTITION=y
> -
> -#
> -# Native Language Support
> -#
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -# CONFIG_NLS_CODEPAGE_437 is not set
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -# CONFIG_NLS_CODEPAGE_850 is not set
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -CONFIG_NLS_ISO8859_1=y
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -# CONFIG_NLS_ISO8859_15 is not set
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -# CONFIG_NLS_UTF8 is not set
> -
> -#
> -# Profiling support
> -#
> -# CONFIG_PROFILING is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_DEBUG_KERNEL=y
> -CONFIG_MAGIC_SYSRQ=y
> -CONFIG_LOG_BUF_SHIFT=14
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_DEBUG_SLAB is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -CONFIG_DEBUG_BUGVERBOSE=y
> -CONFIG_DEBUG_INFO=y
> -# CONFIG_DEBUG_FS is not set
> -CONFIG_FRAME_POINTER=y
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> -CONFIG_DEBUG_LL=y
> -# CONFIG_DEBUG_ICEDCC is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -
> -#
> -# Cryptographic options
> -#
> -# CONFIG_CRYPTO is not set
> -
> -#
> -# Hardware crypto devices
> -#
> -
> -#
> -# Library routines
> -#
> -# CONFIG_CRC_CCITT is not set
> -CONFIG_CRC32=y
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> diff --git a/arch/arm/configs/palmz72_defconfig b/arch/arm/configs/palmz72_defconfig
> deleted file mode 100644
> index 6d162b1..0000000
> --- a/arch/arm/configs/palmz72_defconfig
> +++ /dev/null
> @@ -1,950 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.27-rc4
> -# Sun Aug 24 02:29:27 2008
> -#
> -CONFIG_ARM=y
> -CONFIG_HAVE_PWM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_MMU=y
> -# CONFIG_NO_IOPORT is not set
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -# CONFIG_ARCH_HAS_ILOG2_U32 is not set
> -# CONFIG_ARCH_HAS_ILOG2_U64 is not set
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ARCH_SUPPORTS_AOUT=y
> -CONFIG_ZONE_DMA=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_LOCK_KERNEL=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=""
> -# CONFIG_LOCALVERSION_AUTO is not set
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -# CONFIG_IKCONFIG is not set
> -CONFIG_LOG_BUF_SHIFT=14
> -# CONFIG_CGROUPS is not set
> -# CONFIG_GROUP_SCHED is not set
> -CONFIG_SYSFS_DEPRECATED=y
> -CONFIG_SYSFS_DEPRECATED_V2=y
> -# CONFIG_RELAY is not set
> -CONFIG_NAMESPACES=y
> -# CONFIG_UTS_NS is not set
> -# CONFIG_IPC_NS is not set
> -# CONFIG_USER_NS is not set
> -# CONFIG_PID_NS is not set
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_INITRAMFS_SOURCE=""
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -# CONFIG_EMBEDDED is not set
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_COMPAT_BRK=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_ANON_INODES=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -CONFIG_SHMEM=y
> -CONFIG_VM_EVENT_COUNTERS=y
> -CONFIG_SLAB=y
> -# CONFIG_SLUB is not set
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -# CONFIG_MARKERS is not set
> -CONFIG_HAVE_OPROFILE=y
> -# CONFIG_KPROBES is not set
> -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
> -# CONFIG_HAVE_IOREMAP_PROT is not set
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -# CONFIG_HAVE_ARCH_TRACEHOOK is not set
> -# CONFIG_HAVE_DMA_ATTRS is not set
> -# CONFIG_USE_GENERIC_SMP_HELPERS is not set
> -CONFIG_HAVE_CLK=y
> -CONFIG_PROC_PAGE_MONITOR=y
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_SLABINFO=y
> -CONFIG_RT_MUTEXES=y
> -# CONFIG_TINY_SHMEM is not set
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -# CONFIG_MODULE_FORCE_UNLOAD is not set
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -CONFIG_KMOD=y
> -CONFIG_BLOCK=y
> -# CONFIG_LBD is not set
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_LSF is not set
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_BLK_DEV_INTEGRITY is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_AS=y
> -# CONFIG_IOSCHED_DEADLINE is not set
> -# CONFIG_IOSCHED_CFQ is not set
> -CONFIG_DEFAULT_AS=y
> -# CONFIG_DEFAULT_DEADLINE is not set
> -# CONFIG_DEFAULT_CFQ is not set
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="anticipatory"
> -CONFIG_CLASSIC_RCU=y
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS7500 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_MSM7X00A is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -# CONFIG_ARCH_GUMSTIX is not set
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_ARCH_PXA_ESERIES is not set
> -# CONFIG_MACH_TRIZEPS4 is not set
> -# CONFIG_MACH_EM_X270 is not set
> -# CONFIG_MACH_COLIBRI is not set
> -# CONFIG_MACH_ZYLONITE is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_TAVOREVB is not set
> -# CONFIG_MACH_SAAR is not set
> -# CONFIG_MACH_ARMCORE is not set
> -# CONFIG_MACH_MAGICIAN is not set
> -# CONFIG_MACH_PCM027 is not set
> -CONFIG_ARCH_PXA_PALM=y
> -# CONFIG_MACH_PALMTX is not set
> -CONFIG_MACH_PALMZ72=y
> -# CONFIG_PXA_EZX is not set
> -CONFIG_PXA27x=y
> -CONFIG_PXA_PWM=y
> -
> -#
> -# Boot options
> -#
> -
> -#
> -# Power management
> -#
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_PABRT_NOIFAR=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -# CONFIG_OUTER_CACHE is not set
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -
> -#
> -# Bus support
> -#
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -# CONFIG_NO_HZ is not set
> -# CONFIG_HIGH_RES_TIMERS is not set
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -CONFIG_PREEMPT=y
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -# CONFIG_SPARSEMEM_STATIC is not set
> -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
> -CONFIG_PAGEFLAGS_EXTENDED=y
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_RESOURCES_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=1
> -CONFIG_BOUNCE=y
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="mem=32M console=tty root=/dev/mmcblk0"
> -# CONFIG_XIP_KERNEL is not set
> -# CONFIG_KEXEC is not set
> -
> -#
> -# CPU Frequency scaling
> -#
> -# CONFIG_CPU_FREQ is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -CONFIG_PM=y
> -# CONFIG_PM_DEBUG is not set
> -CONFIG_PM_SLEEP=y
> -CONFIG_SUSPEND=y
> -CONFIG_SUSPEND_FREEZER=y
> -CONFIG_APM_EMULATION=y
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_PACKET=y
> -# CONFIG_PACKET_MMAP is not set
> -CONFIG_UNIX=y
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -# CONFIG_IP_PNP_DHCP is not set
> -CONFIG_IP_PNP_BOOTP=y
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_BEET is not set
> -# CONFIG_INET_LRO is not set
> -CONFIG_INET_DIAG=y
> -CONFIG_INET_TCP_DIAG=y
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -# CONFIG_NETFILTER is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_NET_SCHED is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -# CONFIG_IRDA is not set
> -# CONFIG_BT is not set
> -# CONFIG_AF_RXRPC is not set
> -
> -#
> -# Wireless
> -#
> -# CONFIG_CFG80211 is not set
> -# CONFIG_WIRELESS_EXT is not set
> -# CONFIG_MAC80211 is not set
> -# CONFIG_IEEE80211 is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=y
> -CONFIG_FIRMWARE_IN_KERNEL=y
> -CONFIG_EXTRA_FIRMWARE=""
> -# CONFIG_SYS_HYPERVISOR is not set
> -# CONFIG_CONNECTOR is not set
> -# CONFIG_MTD is not set
> -# CONFIG_PARPORT is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -CONFIG_BLK_DEV_LOOP=y
> -# CONFIG_BLK_DEV_CRYPTOLOOP is not set
> -# CONFIG_BLK_DEV_NBD is not set
> -# CONFIG_BLK_DEV_RAM is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -# CONFIG_MISC_DEVICES is not set
> -CONFIG_HAVE_IDE=y
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -# CONFIG_SCSI is not set
> -# CONFIG_SCSI_DMA is not set
> -# CONFIG_SCSI_NETLINK is not set
> -# CONFIG_ATA is not set
> -# CONFIG_MD is not set
> -# CONFIG_NETDEVICES is not set
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> -# CONFIG_INPUT_JOYDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -# CONFIG_KEYBOARD_ATKBD is not set
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_KEYBOARD_STOWAWAY is not set
> -CONFIG_KEYBOARD_PXA27x=y
> -# CONFIG_KEYBOARD_GPIO is not set
> -# CONFIG_KEYBOARD_MATRIX is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -# CONFIG_INPUT_TOUCHSCREEN is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -# CONFIG_SERIO is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_CONSOLE_TRANSLATIONS=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -CONFIG_DEVKMEM=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -# CONFIG_SERIAL_PXA is not set
> -CONFIG_UNIX98_PTYS=y
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=256
> -# CONFIG_IPMI_HANDLER is not set
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_NVRAM is not set
> -# CONFIG_R3964 is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -CONFIG_I2C=y
> -CONFIG_I2C_BOARDINFO=y
> -# CONFIG_I2C_CHARDEV is not set
> -CONFIG_I2C_HELPER_AUTO=y
> -
> -#
> -# I2C Hardware Bus support
> -#
> -
> -#
> -# I2C system bus drivers (mostly embedded / system-on-chip)
> -#
> -# CONFIG_I2C_GPIO is not set
> -# CONFIG_I2C_OCORES is not set
> -CONFIG_I2C_PXA=y
> -# CONFIG_I2C_PXA_SLAVE is not set
> -# CONFIG_I2C_SIMTEC is not set
> -
> -#
> -# External I2C/SMBus adapter drivers
> -#
> -# CONFIG_I2C_PARPORT_LIGHT is not set
> -# CONFIG_I2C_TAOS_EVM is not set
> -
> -#
> -# Other I2C/SMBus bus drivers
> -#
> -# CONFIG_I2C_PCA_PLATFORM is not set
> -# CONFIG_I2C_STUB is not set
> -
> -#
> -# Miscellaneous I2C Chip support
> -#
> -# CONFIG_DS1682 is not set
> -# CONFIG_EEPROM_AT24 is not set
> -# CONFIG_EEPROM_LEGACY is not set
> -# CONFIG_SENSORS_PCF8574 is not set
> -# CONFIG_PCF8575 is not set
> -# CONFIG_SENSORS_PCA9539 is not set
> -# CONFIG_SENSORS_PCF8591 is not set
> -# CONFIG_TPS65010 is not set
> -# CONFIG_SENSORS_MAX6875 is not set
> -# CONFIG_SENSORS_TSL2550 is not set
> -# CONFIG_I2C_DEBUG_CORE is not set
> -# CONFIG_I2C_DEBUG_ALGO is not set
> -# CONFIG_I2C_DEBUG_BUS is not set
> -# CONFIG_I2C_DEBUG_CHIP is not set
> -CONFIG_SPI=y
> -CONFIG_SPI_MASTER=y
> -
> -#
> -# SPI Master Controller Drivers
> -#
> -# CONFIG_SPI_BITBANG is not set
> -# CONFIG_SPI_PXA2XX is not set
> -
> -#
> -# SPI Protocol Masters
> -#
> -# CONFIG_EEPROM_AT25 is not set
> -CONFIG_SPI_SPIDEV=y
> -# CONFIG_SPI_TLE62X0 is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -CONFIG_GPIO_SYSFS=y
> -
> -#
> -# I2C GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX732X is not set
> -# CONFIG_GPIO_PCA953X is not set
> -# CONFIG_GPIO_PCF857X is not set
> -
> -#
> -# PCI GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX7301 is not set
> -# CONFIG_GPIO_MCP23S08 is not set
> -# CONFIG_W1 is not set
> -CONFIG_POWER_SUPPLY=y
> -# CONFIG_POWER_SUPPLY_DEBUG is not set
> -CONFIG_PDA_POWER=y
> -# CONFIG_APM_POWER is not set
> -# CONFIG_BATTERY_DS2760 is not set
> -# CONFIG_HWMON is not set
> -# CONFIG_WATCHDOG is not set
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -CONFIG_SSB_POSSIBLE=y
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_CORE is not set
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -# CONFIG_MFD_TMIO is not set
> -# CONFIG_MFD_T7L66XB is not set
> -# CONFIG_MFD_TC6387XB is not set
> -# CONFIG_MFD_TC6393XB is not set
> -
> -#
> -# Multimedia devices
> -#
> -
> -#
> -# Multimedia core support
> -#
> -# CONFIG_VIDEO_DEV is not set
> -# CONFIG_DVB_CORE is not set
> -# CONFIG_VIDEO_MEDIA is not set
> -
> -#
> -# Multimedia drivers
> -#
> -# CONFIG_DAB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -CONFIG_FB=y
> -# CONFIG_FIRMWARE_EDID is not set
> -# CONFIG_FB_DDC is not set
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> -# CONFIG_FB_SYS_FILLRECT is not set
> -# CONFIG_FB_SYS_COPYAREA is not set
> -# CONFIG_FB_SYS_IMAGEBLIT is not set
> -# CONFIG_FB_FOREIGN_ENDIAN is not set
> -# CONFIG_FB_SYS_FOPS is not set
> -# CONFIG_FB_SVGALIB is not set
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -
> -#
> -# Frame buffer hardware drivers
> -#
> -# CONFIG_FB_S1D13XXX is not set
> -CONFIG_FB_PXA=y
> -# CONFIG_FB_PXA_SMARTPANEL is not set
> -# CONFIG_FB_PXA_PARAMETERS is not set
> -# CONFIG_FB_MBX is not set
> -# CONFIG_FB_W100 is not set
> -# CONFIG_FB_AM200EPD is not set
> -# CONFIG_FB_VIRTUAL is not set
> -CONFIG_BACKLIGHT_LCD_SUPPORT=y
> -# CONFIG_LCD_CLASS_DEVICE is not set
> -CONFIG_BACKLIGHT_CLASS_DEVICE=y
> -# CONFIG_BACKLIGHT_CORGI is not set
> -CONFIG_BACKLIGHT_PWM=y
> -
> -#
> -# Display device support
> -#
> -CONFIG_DISPLAY_SUPPORT=y
> -
> -#
> -# Display hardware drivers
> -#
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
> -CONFIG_FONTS=y
> -CONFIG_FONT_8x8=y
> -# CONFIG_FONT_8x16 is not set
> -# CONFIG_FONT_6x11 is not set
> -# CONFIG_FONT_7x14 is not set
> -# CONFIG_FONT_PEARL_8x8 is not set
> -# CONFIG_FONT_ACORN_8x8 is not set
> -# CONFIG_FONT_MINI_4x6 is not set
> -# CONFIG_FONT_SUN8x16 is not set
> -# CONFIG_FONT_SUN12x22 is not set
> -# CONFIG_FONT_10x18 is not set
> -# CONFIG_LOGO is not set
> -# CONFIG_SOUND is not set
> -# CONFIG_HID_SUPPORT is not set
> -# CONFIG_USB_SUPPORT is not set
> -CONFIG_MMC=y
> -CONFIG_MMC_DEBUG=y
> -# CONFIG_MMC_UNSAFE_RESUME is not set
> -
> -#
> -# MMC/SD Card Drivers
> -#
> -CONFIG_MMC_BLOCK=y
> -CONFIG_MMC_BLOCK_BOUNCE=y
> -# CONFIG_SDIO_UART is not set
> -# CONFIG_MMC_TEST is not set
> -
> -#
> -# MMC/SD Host Controller Drivers
> -#
> -CONFIG_MMC_PXA=y
> -# CONFIG_MMC_SDHCI is not set
> -# CONFIG_MMC_SPI is not set
> -# CONFIG_NEW_LEDS is not set
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_HCTOSYS=y
> -CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
> -# CONFIG_RTC_DEBUG is not set
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -# CONFIG_RTC_DRV_TEST is not set
> -
> -#
> -# I2C RTC drivers
> -#
> -# CONFIG_RTC_DRV_DS1307 is not set
> -# CONFIG_RTC_DRV_DS1374 is not set
> -# CONFIG_RTC_DRV_DS1672 is not set
> -# CONFIG_RTC_DRV_MAX6900 is not set
> -# CONFIG_RTC_DRV_RS5C372 is not set
> -# CONFIG_RTC_DRV_ISL1208 is not set
> -# CONFIG_RTC_DRV_X1205 is not set
> -# CONFIG_RTC_DRV_PCF8563 is not set
> -# CONFIG_RTC_DRV_PCF8583 is not set
> -# CONFIG_RTC_DRV_M41T80 is not set
> -# CONFIG_RTC_DRV_S35390A is not set
> -# CONFIG_RTC_DRV_FM3130 is not set
> -
> -#
> -# SPI RTC drivers
> -#
> -# CONFIG_RTC_DRV_M41T94 is not set
> -# CONFIG_RTC_DRV_DS1305 is not set
> -# CONFIG_RTC_DRV_MAX6902 is not set
> -# CONFIG_RTC_DRV_R9701 is not set
> -# CONFIG_RTC_DRV_RS5C348 is not set
> -
> -#
> -# Platform RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_DS1511 is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_STK17TA8 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -# CONFIG_RTC_DRV_M48T59 is not set
> -# CONFIG_RTC_DRV_V3020 is not set
> -
> -#
> -# on-CPU RTC drivers
> -#
> -CONFIG_RTC_DRV_SA1100=y
> -# CONFIG_DMADEVICES is not set
> -
> -#
> -# Voltage and Current regulators
> -#
> -# CONFIG_REGULATOR is not set
> -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
> -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
> -# CONFIG_REGULATOR_BQ24022 is not set
> -# CONFIG_UIO is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -CONFIG_EXT3_FS=y
> -CONFIG_EXT3_FS_XATTR=y
> -# CONFIG_EXT3_FS_POSIX_ACL is not set
> -# CONFIG_EXT3_FS_SECURITY is not set
> -# CONFIG_EXT4DEV_FS is not set
> -CONFIG_JBD=y
> -CONFIG_FS_MBCACHE=y
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -# CONFIG_FS_POSIX_ACL is not set
> -# CONFIG_XFS_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_DNOTIFY is not set
> -# CONFIG_INOTIFY is not set
> -# CONFIG_QUOTA is not set
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=y
> -CONFIG_MSDOS_FS=y
> -CONFIG_VFAT_FS=y
> -CONFIG_FAT_DEFAULT_CODEPAGE=866
> -CONFIG_FAT_DEFAULT_IOCHARSET="utf8"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -
> -#
> -# Miscellaneous filesystems
> -#
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_OMFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -# CONFIG_NETWORK_FILESYSTEMS is not set
> -
> -#
> -# Partition Types
> -#
> -# CONFIG_PARTITION_ADVANCED is not set
> -CONFIG_MSDOS_PARTITION=y
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="utf8"
> -# CONFIG_NLS_CODEPAGE_437 is not set
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -# CONFIG_NLS_CODEPAGE_850 is not set
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -CONFIG_NLS_CODEPAGE_866=y
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -# CONFIG_NLS_ISO8859_1 is not set
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -# CONFIG_NLS_ISO8859_15 is not set
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -CONFIG_NLS_UTF8=y
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_FRAME_WARN=1024
> -# CONFIG_MAGIC_SYSRQ is not set
> -# CONFIG_UNUSED_SYMBOLS is not set
> -# CONFIG_DEBUG_FS is not set
> -# CONFIG_HEADERS_CHECK is not set
> -# CONFIG_DEBUG_KERNEL is not set
> -CONFIG_DEBUG_BUGVERBOSE=y
> -CONFIG_DEBUG_MEMORY_INIT=y
> -CONFIG_FRAME_POINTER=y
> -# CONFIG_LATENCYTOP is not set
> -CONFIG_SYSCTL_SYSCALL_CHECK=y
> -CONFIG_HAVE_FTRACE=y
> -CONFIG_HAVE_DYNAMIC_FTRACE=y
> -# CONFIG_FTRACE is not set
> -# CONFIG_IRQSOFF_TRACER is not set
> -# CONFIG_PREEMPT_TRACER is not set
> -# CONFIG_SCHED_TRACER is not set
> -# CONFIG_CONTEXT_SWITCH_TRACER is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -CONFIG_DEBUG_USER=y
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITY_FILE_CAPABILITIES is not set
> -# CONFIG_CRYPTO is not set
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -# CONFIG_GENERIC_FIND_FIRST_BIT is not set
> -# CONFIG_GENERIC_FIND_NEXT_BIT is not set
> -# CONFIG_CRC_CCITT is not set
> -# CONFIG_CRC16 is not set
> -CONFIG_CRC_T10DIF=y
> -# CONFIG_CRC_ITU_T is not set
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_PLIST=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig
> deleted file mode 100644
> index fa153f2..0000000
> --- a/arch/arm/configs/pcm027_defconfig
> +++ /dev/null
> @@ -1,1095 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.24-rc6
> -# Fri Dec 21 10:52:09 2007
> -#
> -CONFIG_ARM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_MMU=y
> -# CONFIG_NO_IOPORT is not set
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -# CONFIG_ARCH_HAS_ILOG2_U32 is not set
> -# CONFIG_ARCH_HAS_ILOG2_U64 is not set
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ZONE_DMA=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_LOCK_KERNEL=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=""
> -CONFIG_LOCALVERSION_AUTO=y
> -# CONFIG_SWAP is not set
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -CONFIG_POSIX_MQUEUE=y
> -CONFIG_BSD_PROCESS_ACCT=y
> -# CONFIG_BSD_PROCESS_ACCT_V3 is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_USER_NS is not set
> -# CONFIG_PID_NS is not set
> -# CONFIG_AUDIT is not set
> -CONFIG_IKCONFIG=y
> -CONFIG_IKCONFIG_PROC=y
> -CONFIG_LOG_BUF_SHIFT=14
> -# CONFIG_CGROUPS is not set
> -CONFIG_FAIR_GROUP_SCHED=y
> -CONFIG_FAIR_USER_SCHED=y
> -# CONFIG_FAIR_CGROUP_SCHED is not set
> -CONFIG_SYSFS_DEPRECATED=y
> -# CONFIG_RELAY is not set
> -# CONFIG_BLK_DEV_INITRD is not set
> -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
> -CONFIG_SYSCTL=y
> -CONFIG_EMBEDDED=y
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -# CONFIG_KALLSYMS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_ANON_INODES=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_EVENTFD=y
> -CONFIG_SHMEM=y
> -CONFIG_VM_EVENT_COUNTERS=y
> -CONFIG_SLAB=y
> -# CONFIG_SLUB is not set
> -# CONFIG_SLOB is not set
> -CONFIG_RT_MUTEXES=y
> -# CONFIG_TINY_SHMEM is not set
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_MODULE_FORCE_UNLOAD=y
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -# CONFIG_KMOD is not set
> -CONFIG_BLOCK=y
> -# CONFIG_LBD is not set
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_LSF is not set
> -# CONFIG_BLK_DEV_BSG is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -# CONFIG_IOSCHED_AS is not set
> -# CONFIG_IOSCHED_DEADLINE is not set
> -# CONFIG_IOSCHED_CFQ is not set
> -# CONFIG_DEFAULT_AS is not set
> -# CONFIG_DEFAULT_DEADLINE is not set
> -# CONFIG_DEFAULT_CFQ is not set
> -CONFIG_DEFAULT_NOOP=y
> -CONFIG_DEFAULT_IOSCHED="noop"
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS7500 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_CO285 is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_MACH_TRIZEPS4 is not set
> -# CONFIG_MACH_EM_X270 is not set
> -# CONFIG_MACH_ZYLONITE is not set
> -# CONFIG_MACH_ARMCORE is not set
> -CONFIG_MACH_PCM027=y
> -CONFIG_MACH_PCM990_BASEBOARD=y
> -CONFIG_PXA27x=y
> -
> -#
> -# Boot options
> -#
> -
> -#
> -# Power management
> -#
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -# CONFIG_OUTER_CACHE is not set
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -
> -#
> -# Bus support
> -#
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -CONFIG_NO_HZ=y
> -CONFIG_HIGH_RES_TIMERS=y
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -CONFIG_PREEMPT=y
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -# CONFIG_OABI_COMPAT is not set
> -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -# CONFIG_SPARSEMEM_STATIC is not set
> -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_RESOURCES_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=1
> -CONFIG_BOUNCE=y
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE=""
> -# CONFIG_XIP_KERNEL is not set
> -# CONFIG_KEXEC is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -# CONFIG_PM is not set
> -CONFIG_SUSPEND_UP_POSSIBLE=y
> -
> -#
> -# Networking
> -#
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_PACKET=y
> -CONFIG_PACKET_MMAP=y
> -CONFIG_UNIX=y
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -# CONFIG_IP_PNP_DHCP is not set
> -# CONFIG_IP_PNP_BOOTP is not set
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_BEET is not set
> -# CONFIG_INET_LRO is not set
> -# CONFIG_INET_DIAG is not set
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_INET6_XFRM_TUNNEL is not set
> -# CONFIG_INET6_TUNNEL is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -# CONFIG_NETFILTER is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_NET_SCHED is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_IRDA is not set
> -# CONFIG_BT is not set
> -# CONFIG_AF_RXRPC is not set
> -
> -#
> -# Wireless
> -#
> -# CONFIG_CFG80211 is not set
> -# CONFIG_WIRELESS_EXT is not set
> -# CONFIG_MAC80211 is not set
> -# CONFIG_IEEE80211 is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=y
> -# CONFIG_SYS_HYPERVISOR is not set
> -# CONFIG_CONNECTOR is not set
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -# CONFIG_MTD_REDBOOT_PARTS is not set
> -CONFIG_MTD_CMDLINE_PARTS=y
> -# CONFIG_MTD_AFS_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_MTD_BLKDEVS=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -# CONFIG_MTD_JEDECPROBE is not set
> -CONFIG_MTD_GEN_PROBE=y
> -# CONFIG_MTD_CFI_ADV_OPTIONS is not set
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -# CONFIG_MTD_CFI_AMDSTD is not set
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> -CONFIG_MTD_PHYSMAP=y
> -CONFIG_MTD_PHYSMAP_START=0x00000000
> -CONFIG_MTD_PHYSMAP_LEN=0x0
> -CONFIG_MTD_PHYSMAP_BANKWIDTH=0
> -# CONFIG_MTD_PXA2XX is not set
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -# CONFIG_MTD_NAND is not set
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -# CONFIG_BLK_DEV is not set
> -# CONFIG_MISC_DEVICES is not set
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -CONFIG_SCSI=y
> -CONFIG_SCSI_DMA=y
> -# CONFIG_SCSI_TGT is not set
> -# CONFIG_SCSI_NETLINK is not set
> -CONFIG_SCSI_PROC_FS=y
> -
> -#
> -# SCSI support type (disk, tape, CD-ROM)
> -#
> -CONFIG_BLK_DEV_SD=y
> -# CONFIG_CHR_DEV_ST is not set
> -# CONFIG_CHR_DEV_OSST is not set
> -# CONFIG_BLK_DEV_SR is not set
> -# CONFIG_CHR_DEV_SG is not set
> -# CONFIG_CHR_DEV_SCH is not set
> -
> -#
> -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
> -#
> -# CONFIG_SCSI_MULTI_LUN is not set
> -# CONFIG_SCSI_CONSTANTS is not set
> -# CONFIG_SCSI_LOGGING is not set
> -# CONFIG_SCSI_SCAN_ASYNC is not set
> -CONFIG_SCSI_WAIT_SCAN=m
> -
> -#
> -# SCSI Transports
> -#
> -# CONFIG_SCSI_SPI_ATTRS is not set
> -# CONFIG_SCSI_FC_ATTRS is not set
> -# CONFIG_SCSI_ISCSI_ATTRS is not set
> -# CONFIG_SCSI_SAS_LIBSAS is not set
> -# CONFIG_SCSI_SRP_ATTRS is not set
> -# CONFIG_SCSI_LOWLEVEL is not set
> -# CONFIG_ATA is not set
> -# CONFIG_MD is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_NETDEVICES_MULTIQUEUE is not set
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_MACVLAN is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -# CONFIG_VETH is not set
> -# CONFIG_PHYLIB is not set
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=y
> -# CONFIG_AX88796 is not set
> -CONFIG_SMC91X=y
> -# CONFIG_DM9000 is not set
> -# CONFIG_SMC911X is not set
> -# CONFIG_IBM_NEW_EMAC_ZMII is not set
> -# CONFIG_IBM_NEW_EMAC_RGMII is not set
> -# CONFIG_IBM_NEW_EMAC_TAH is not set
> -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
> -# CONFIG_B44 is not set
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -
> -#
> -# Wireless LAN
> -#
> -# CONFIG_WLAN_PRE80211 is not set
> -# CONFIG_WLAN_80211 is not set
> -
> -#
> -# USB Network Adapters
> -#
> -# CONFIG_USB_CATC is not set
> -# CONFIG_USB_KAWETH is not set
> -# CONFIG_USB_PEGASUS is not set
> -# CONFIG_USB_RTL8150 is not set
> -# CONFIG_USB_USBNET is not set
> -# CONFIG_WAN is not set
> -# CONFIG_PPP is not set
> -# CONFIG_SLIP is not set
> -# CONFIG_SHAPER is not set
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> -# CONFIG_INPUT_JOYDEV is not set
> -# CONFIG_INPUT_EVDEV is not set
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -# CONFIG_INPUT_KEYBOARD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -# CONFIG_INPUT_TOUCHSCREEN is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -# CONFIG_SERIO is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_LEGACY_PTYS is not set
> -# CONFIG_IPMI_HANDLER is not set
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_NVRAM is not set
> -# CONFIG_R3964 is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -CONFIG_I2C=y
> -CONFIG_I2C_BOARDINFO=y
> -CONFIG_I2C_CHARDEV=y
> -
> -#
> -# I2C Algorithms
> -#
> -# CONFIG_I2C_ALGOBIT is not set
> -# CONFIG_I2C_ALGOPCF is not set
> -# CONFIG_I2C_ALGOPCA is not set
> -
> -#
> -# I2C Hardware Bus support
> -#
> -# CONFIG_I2C_GPIO is not set
> -CONFIG_I2C_PXA=y
> -# CONFIG_I2C_PXA_SLAVE is not set
> -# CONFIG_I2C_OCORES is not set
> -# CONFIG_I2C_PARPORT_LIGHT is not set
> -# CONFIG_I2C_SIMTEC is not set
> -# CONFIG_I2C_TAOS_EVM is not set
> -# CONFIG_I2C_STUB is not set
> -# CONFIG_I2C_TINY_USB is not set
> -
> -#
> -# Miscellaneous I2C Chip support
> -#
> -# CONFIG_SENSORS_DS1337 is not set
> -# CONFIG_SENSORS_DS1374 is not set
> -# CONFIG_DS1682 is not set
> -CONFIG_EEPROM_LEGACY=y
> -# CONFIG_SENSORS_PCF8574 is not set
> -# CONFIG_SENSORS_PCA9539 is not set
> -# CONFIG_SENSORS_PCF8591 is not set
> -# CONFIG_SENSORS_MAX6875 is not set
> -# CONFIG_SENSORS_TSL2550 is not set
> -# CONFIG_I2C_DEBUG_CORE is not set
> -# CONFIG_I2C_DEBUG_ALGO is not set
> -# CONFIG_I2C_DEBUG_BUS is not set
> -# CONFIG_I2C_DEBUG_CHIP is not set
> -
> -#
> -# SPI support
> -#
> -# CONFIG_SPI is not set
> -# CONFIG_SPI_MASTER is not set
> -# CONFIG_W1 is not set
> -# CONFIG_POWER_SUPPLY is not set
> -# CONFIG_HWMON is not set
> -# CONFIG_WATCHDOG is not set
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -CONFIG_SSB_POSSIBLE=y
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_SM501 is not set
> -
> -#
> -# Multimedia devices
> -#
> -# CONFIG_VIDEO_DEV is not set
> -# CONFIG_DVB_CORE is not set
> -# CONFIG_DAB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -# CONFIG_FB is not set
> -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -
> -#
> -# Sound
> -#
> -CONFIG_SOUND=y
> -
> -#
> -# Advanced Linux Sound Architecture
> -#
> -CONFIG_SND=y
> -CONFIG_SND_TIMER=y
> -CONFIG_SND_PCM=y
> -# CONFIG_SND_SEQUENCER is not set
> -CONFIG_SND_OSSEMUL=y
> -CONFIG_SND_MIXER_OSS=y
> -CONFIG_SND_PCM_OSS=y
> -CONFIG_SND_PCM_OSS_PLUGINS=y
> -# CONFIG_SND_DYNAMIC_MINORS is not set
> -CONFIG_SND_SUPPORT_OLD_API=y
> -CONFIG_SND_VERBOSE_PROCFS=y
> -# CONFIG_SND_VERBOSE_PRINTK is not set
> -# CONFIG_SND_DEBUG is not set
> -
> -#
> -# Generic devices
> -#
> -CONFIG_SND_AC97_CODEC=y
> -# CONFIG_SND_DUMMY is not set
> -# CONFIG_SND_MTPAV is not set
> -# CONFIG_SND_SERIAL_U16550 is not set
> -# CONFIG_SND_MPU401 is not set
> -
> -#
> -# ALSA ARM devices
> -#
> -CONFIG_SND_PXA2XX_PCM=y
> -CONFIG_SND_PXA2XX_AC97=y
> -
> -#
> -# USB devices
> -#
> -# CONFIG_SND_USB_AUDIO is not set
> -# CONFIG_SND_USB_CAIAQ is not set
> -
> -#
> -# System on Chip audio support
> -#
> -# CONFIG_SND_SOC is not set
> -
> -#
> -# SoC Audio support for SuperH
> -#
> -
> -#
> -# Open Sound System
> -#
> -# CONFIG_SOUND_PRIME is not set
> -CONFIG_AC97_BUS=y
> -# CONFIG_HID_SUPPORT is not set
> -CONFIG_USB_SUPPORT=y
> -CONFIG_USB_ARCH_HAS_HCD=y
> -CONFIG_USB_ARCH_HAS_OHCI=y
> -# CONFIG_USB_ARCH_HAS_EHCI is not set
> -CONFIG_USB=y
> -# CONFIG_USB_DEBUG is not set
> -
> -#
> -# Miscellaneous USB options
> -#
> -CONFIG_USB_DEVICEFS=y
> -CONFIG_USB_DEVICE_CLASS=y
> -# CONFIG_USB_DYNAMIC_MINORS is not set
> -# CONFIG_USB_OTG is not set
> -
> -#
> -# USB Host Controller Drivers
> -#
> -# CONFIG_USB_ISP116X_HCD is not set
> -CONFIG_USB_OHCI_HCD=y
> -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
> -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
> -CONFIG_USB_OHCI_LITTLE_ENDIAN=y
> -# CONFIG_USB_SL811_HCD is not set
> -# CONFIG_USB_R8A66597_HCD is not set
> -
> -#
> -# USB Device Class drivers
> -#
> -# CONFIG_USB_ACM is not set
> -# CONFIG_USB_PRINTER is not set
> -
> -#
> -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
> -#
> -
> -#
> -# may also be needed; see USB_STORAGE Help for more information
> -#
> -CONFIG_USB_STORAGE=y
> -# CONFIG_USB_STORAGE_DEBUG is not set
> -# CONFIG_USB_STORAGE_DATAFAB is not set
> -# CONFIG_USB_STORAGE_FREECOM is not set
> -# CONFIG_USB_STORAGE_ISD200 is not set
> -# CONFIG_USB_STORAGE_DPCM is not set
> -# CONFIG_USB_STORAGE_USBAT is not set
> -# CONFIG_USB_STORAGE_SDDR09 is not set
> -# CONFIG_USB_STORAGE_SDDR55 is not set
> -# CONFIG_USB_STORAGE_JUMPSHOT is not set
> -# CONFIG_USB_STORAGE_ALAUDA is not set
> -# CONFIG_USB_STORAGE_KARMA is not set
> -# CONFIG_USB_LIBUSUAL is not set
> -
> -#
> -# USB Imaging devices
> -#
> -# CONFIG_USB_MDC800 is not set
> -# CONFIG_USB_MICROTEK is not set
> -# CONFIG_USB_MON is not set
> -
> -#
> -# USB port drivers
> -#
> -
> -#
> -# USB Serial Converter support
> -#
> -# CONFIG_USB_SERIAL is not set
> -
> -#
> -# USB Miscellaneous drivers
> -#
> -# CONFIG_USB_EMI62 is not set
> -# CONFIG_USB_EMI26 is not set
> -# CONFIG_USB_ADUTUX is not set
> -# CONFIG_USB_AUERSWALD is not set
> -# CONFIG_USB_RIO500 is not set
> -# CONFIG_USB_LEGOTOWER is not set
> -# CONFIG_USB_LCD is not set
> -# CONFIG_USB_BERRY_CHARGE is not set
> -# CONFIG_USB_LED is not set
> -# CONFIG_USB_CYPRESS_CY7C63 is not set
> -# CONFIG_USB_CYTHERM is not set
> -# CONFIG_USB_PHIDGET is not set
> -# CONFIG_USB_IDMOUSE is not set
> -# CONFIG_USB_FTDI_ELAN is not set
> -# CONFIG_USB_APPLEDISPLAY is not set
> -# CONFIG_USB_LD is not set
> -# CONFIG_USB_TRANCEVIBRATOR is not set
> -# CONFIG_USB_IOWARRIOR is not set
> -# CONFIG_USB_TEST is not set
> -
> -#
> -# USB DSL modem support
> -#
> -
> -#
> -# USB Gadget Support
> -#
> -# CONFIG_USB_GADGET is not set
> -CONFIG_MMC=y
> -# CONFIG_MMC_DEBUG is not set
> -# CONFIG_MMC_UNSAFE_RESUME is not set
> -
> -#
> -# MMC/SD Card Drivers
> -#
> -CONFIG_MMC_BLOCK=y
> -CONFIG_MMC_BLOCK_BOUNCE=y
> -# CONFIG_SDIO_UART is not set
> -
> -#
> -# MMC/SD Host Controller Drivers
> -#
> -CONFIG_MMC_PXA=y
> -# CONFIG_NEW_LEDS is not set
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=y
> -CONFIG_RTC_HCTOSYS=y
> -CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
> -# CONFIG_RTC_DEBUG is not set
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -# CONFIG_RTC_DRV_TEST is not set
> -
> -#
> -# I2C RTC drivers
> -#
> -# CONFIG_RTC_DRV_DS1307 is not set
> -# CONFIG_RTC_DRV_DS1374 is not set
> -# CONFIG_RTC_DRV_DS1672 is not set
> -# CONFIG_RTC_DRV_MAX6900 is not set
> -# CONFIG_RTC_DRV_RS5C372 is not set
> -# CONFIG_RTC_DRV_ISL1208 is not set
> -# CONFIG_RTC_DRV_X1205 is not set
> -CONFIG_RTC_DRV_PCF8563=m
> -# CONFIG_RTC_DRV_PCF8583 is not set
> -# CONFIG_RTC_DRV_M41T80 is not set
> -
> -#
> -# SPI RTC drivers
> -#
> -
> -#
> -# Platform RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_STK17TA8 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -# CONFIG_RTC_DRV_M48T59 is not set
> -# CONFIG_RTC_DRV_V3020 is not set
> -
> -#
> -# on-CPU RTC drivers
> -#
> -CONFIG_RTC_DRV_SA1100=m
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=m
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -CONFIG_EXT3_FS=m
> -CONFIG_EXT3_FS_XATTR=y
> -# CONFIG_EXT3_FS_POSIX_ACL is not set
> -# CONFIG_EXT3_FS_SECURITY is not set
> -# CONFIG_EXT4DEV_FS is not set
> -CONFIG_JBD=m
> -CONFIG_FS_MBCACHE=m
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -# CONFIG_FS_POSIX_ACL is not set
> -# CONFIG_XFS_FS is not set
> -# CONFIG_GFS2_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_INOTIFY is not set
> -# CONFIG_QUOTA is not set
> -# CONFIG_DNOTIFY is not set
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=m
> -# CONFIG_MSDOS_FS is not set
> -CONFIG_VFAT_FS=m
> -CONFIG_FAT_DEFAULT_CODEPAGE=850
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -
> -#
> -# Miscellaneous filesystems
> -#
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
> -# CONFIG_JFFS2_SUMMARY is not set
> -# CONFIG_JFFS2_FS_XATTR is not set
> -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
> -CONFIG_JFFS2_ZLIB=y
> -# CONFIG_JFFS2_LZO is not set
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -CONFIG_NETWORK_FILESYSTEMS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -# CONFIG_NFS_V3_ACL is not set
> -# CONFIG_NFS_V4 is not set
> -CONFIG_NFS_DIRECTIO=y
> -# CONFIG_NFSD is not set
> -CONFIG_ROOT_NFS=y
> -CONFIG_LOCKD=y
> -CONFIG_LOCKD_V4=y
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=y
> -# CONFIG_SUNRPC_BIND34 is not set
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -# CONFIG_CIFS is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -CONFIG_PARTITION_ADVANCED=y
> -# CONFIG_ACORN_PARTITION is not set
> -# CONFIG_OSF_PARTITION is not set
> -# CONFIG_AMIGA_PARTITION is not set
> -# CONFIG_ATARI_PARTITION is not set
> -# CONFIG_MAC_PARTITION is not set
> -CONFIG_MSDOS_PARTITION=y
> -# CONFIG_BSD_DISKLABEL is not set
> -# CONFIG_MINIX_SUBPARTITION is not set
> -# CONFIG_SOLARIS_X86_PARTITION is not set
> -# CONFIG_UNIXWARE_DISKLABEL is not set
> -# CONFIG_LDM_PARTITION is not set
> -# CONFIG_SGI_PARTITION is not set
> -# CONFIG_ULTRIX_PARTITION is not set
> -# CONFIG_SUN_PARTITION is not set
> -# CONFIG_KARMA_PARTITION is not set
> -# CONFIG_EFI_PARTITION is not set
> -# CONFIG_SYSV68_PARTITION is not set
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="iso8859-15"
> -# CONFIG_NLS_CODEPAGE_437 is not set
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -CONFIG_NLS_CODEPAGE_850=y
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -# CONFIG_NLS_ISO8859_1 is not set
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -CONFIG_NLS_ISO8859_15=y
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -# CONFIG_NLS_UTF8 is not set
> -# CONFIG_DLM is not set
> -# CONFIG_INSTRUMENTATION is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_MAGIC_SYSRQ=y
> -# CONFIG_UNUSED_SYMBOLS is not set
> -# CONFIG_DEBUG_FS is not set
> -# CONFIG_HEADERS_CHECK is not set
> -# CONFIG_DEBUG_KERNEL is not set
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -CONFIG_FRAME_POINTER=y
> -# CONFIG_SAMPLES is not set
> -# CONFIG_DEBUG_USER is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITY_FILE_CAPABILITIES is not set
> -# CONFIG_CRYPTO is not set
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -# CONFIG_CRC_CCITT is not set
> -# CONFIG_CRC16 is not set
> -# CONFIG_CRC_ITU_T is not set
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_PLIST=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> diff --git a/arch/arm/configs/pxa255-idp_defconfig b/arch/arm/configs/pxa255-idp_defconfig
> deleted file mode 100644
> index 3365c5d..0000000
> --- a/arch/arm/configs/pxa255-idp_defconfig
> +++ /dev/null
> @@ -1,796 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.12-rc1-bk2
> -# Sun Mar 27 22:20:17 2005
> -#
> -CONFIG_ARM=y
> -CONFIG_MMU=y
> -CONFIG_UID16=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_GENERIC_IOMAP=y
> -
> -#
> -# Code maturity level options
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_CLEAN_COMPILE=y
> -CONFIG_BROKEN_ON_SMP=y
> -
> -#
> -# General setup
> -#
> -CONFIG_LOCALVERSION=""
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -CONFIG_SYSCTL=y
> -# CONFIG_AUDIT is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_KOBJECT_UEVENT=y
> -# CONFIG_IKCONFIG is not set
> -# CONFIG_EMBEDDED is not set
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_EPOLL=y
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SHMEM=y
> -CONFIG_CC_ALIGN_FUNCTIONS=0
> -CONFIG_CC_ALIGN_LABELS=0
> -CONFIG_CC_ALIGN_LOOPS=0
> -CONFIG_CC_ALIGN_JUMPS=0
> -# CONFIG_TINY_SHMEM is not set
> -CONFIG_BASE_SMALL=0
> -
> -#
> -# Loadable module support
> -#
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_UNLOAD is not set
> -CONFIG_OBSOLETE_MODPARM=y
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -# CONFIG_KMOD is not set
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_CLPS7500 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_CO285 is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_IOP3XX is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_L7200 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_H720X is not set
> -
> -#
> -# Intel PXA2xx Implementations
> -#
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -CONFIG_ARCH_PXA_IDP=y
> -# CONFIG_PXA_SHARPSL is not set
> -CONFIG_PXA25x=y
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_MINICACHE=y
> -
> -#
> -# Processor Features
> -#
> -# CONFIG_ARM_THUMB is not set
> -CONFIG_XSCALE_PMU=y
> -
> -#
> -# Bus support
> -#
> -
> -#
> -# PCCARD (PCMCIA/CardBus) support
> -#
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -# CONFIG_PREEMPT is not set
> -CONFIG_LEDS=y
> -CONFIG_LEDS_TIMER=y
> -CONFIG_LEDS_CPU=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="root=/dev/nfs ip=dhcp console=ttyS0,115200 mem=64M"
> -# CONFIG_XIP_KERNEL is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -# CONFIG_ARTHUR is not set
> -
> -#
> -# Power management options
> -#
> -# CONFIG_PM is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -# CONFIG_FW_LOADER is not set
> -# CONFIG_DEBUG_DRIVER is not set
> -
> -#
> -# Memory Technology Devices (MTD)
> -#
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -# CONFIG_MTD_REDBOOT_PARTS is not set
> -# CONFIG_MTD_CMDLINE_PARTS is not set
> -# CONFIG_MTD_AFS_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -# CONFIG_MTD_JEDECPROBE is not set
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_NOSWAP=y
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> -CONFIG_MTD_CFI_GEOMETRY=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -# CONFIG_MTD_CFI_I1 is not set
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -# CONFIG_MTD_CFI_AMDSTD is not set
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -# CONFIG_MTD_COMPLEX_MAPPINGS is not set
> -# CONFIG_MTD_PHYSMAP is not set
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_EDB7312 is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLKMTD is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -
> -#
> -# NAND Flash Device Drivers
> -#
> -# CONFIG_MTD_NAND is not set
> -
> -#
> -# Parallel port support
> -#
> -# CONFIG_PARPORT is not set
> -
> -#
> -# Plug and Play support
> -#
> -
> -#
> -# Block devices
> -#
> -# CONFIG_BLK_DEV_FD is not set
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -# CONFIG_BLK_DEV_LOOP is not set
> -# CONFIG_BLK_DEV_NBD is not set
> -# CONFIG_BLK_DEV_RAM is not set
> -CONFIG_BLK_DEV_RAM_COUNT=16
> -CONFIG_INITRAMFS_SOURCE=""
> -# CONFIG_CDROM_PKTCDVD is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_AS=y
> -CONFIG_IOSCHED_DEADLINE=y
> -CONFIG_IOSCHED_CFQ=y
> -# CONFIG_ATA_OVER_ETH is not set
> -
> -#
> -# ATA/ATAPI/MFM/RLL support
> -#
> -CONFIG_IDE=y
> -CONFIG_BLK_DEV_IDE=y
> -
> -#
> -# Please see Documentation/ide.txt for help/info on IDE drives
> -#
> -# CONFIG_BLK_DEV_IDE_SATA is not set
> -CONFIG_BLK_DEV_IDEDISK=y
> -# CONFIG_IDEDISK_MULTI_MODE is not set
> -# CONFIG_BLK_DEV_IDECD is not set
> -# CONFIG_BLK_DEV_IDETAPE is not set
> -# CONFIG_BLK_DEV_IDEFLOPPY is not set
> -# CONFIG_IDE_TASK_IOCTL is not set
> -
> -#
> -# IDE chipset support/bugfixes
> -#
> -# CONFIG_IDE_GENERIC is not set
> -# CONFIG_IDE_ARM is not set
> -# CONFIG_BLK_DEV_IDEDMA is not set
> -# CONFIG_IDEDMA_AUTO is not set
> -# CONFIG_BLK_DEV_HD is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_SCSI is not set
> -
> -#
> -# Multi-device support (RAID and LVM)
> -#
> -# CONFIG_MD is not set
> -
> -#
> -# Fusion MPT device support
> -#
> -
> -#
> -# IEEE 1394 (FireWire) support
> -#
> -
> -#
> -# I2O device support
> -#
> -
> -#
> -# Networking support
> -#
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -# CONFIG_PACKET is not set
> -# CONFIG_NETLINK_DEV is not set
> -CONFIG_UNIX=y
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -# CONFIG_IP_PNP_BOOTP is not set
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_TUNNEL is not set
> -CONFIG_IP_TCPDIAG=y
> -# CONFIG_IP_TCPDIAG_IPV6 is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETFILTER is not set
> -
> -#
> -# SCTP Configuration (EXPERIMENTAL)
> -#
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_NET_DIVERT is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -
> -#
> -# QoS and/or fair queueing
> -#
> -# CONFIG_NET_SCHED is not set
> -# CONFIG_NET_CLS_ROUTE is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_IRDA is not set
> -# CONFIG_BT is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -
> -#
> -# Ethernet (10 or 100Mbit)
> -#
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=y
> -CONFIG_SMC91X=y
> -
> -#
> -# Ethernet (1000 Mbit)
> -#
> -
> -#
> -# Ethernet (10000 Mbit)
> -#
> -
> -#
> -# Token Ring devices
> -#
> -
> -#
> -# Wireless LAN (non-hamradio)
> -#
> -# CONFIG_NET_RADIO is not set
> -
> -#
> -# Wan interfaces
> -#
> -# CONFIG_WAN is not set
> -# CONFIG_PPP is not set
> -# CONFIG_SLIP is not set
> -# CONFIG_SHAPER is not set
> -# CONFIG_NETCONSOLE is not set
> -
> -#
> -# ISDN subsystem
> -#
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -CONFIG_INPUT_MOUSEDEV_PSAUX=y
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> -# CONFIG_INPUT_JOYDEV is not set
> -# CONFIG_INPUT_TSDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -CONFIG_KEYBOARD_ATKBD=y
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TOUCHSCREEN is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -CONFIG_SERIO=y
> -# CONFIG_SERIO_SERPORT is not set
> -CONFIG_SERIO_LIBPS2=y
> -# CONFIG_SERIO_RAW is not set
> -# CONFIG_GAMEPORT is not set
> -CONFIG_SOUND_GAMEPORT=y
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=256
> -
> -#
> -# IPMI
> -#
> -# CONFIG_IPMI_HANDLER is not set
> -
> -#
> -# Watchdog Cards
> -#
> -# CONFIG_WATCHDOG is not set
> -# CONFIG_NVRAM is not set
> -# CONFIG_RTC is not set
> -# CONFIG_DTLK is not set
> -# CONFIG_R3964 is not set
> -
> -#
> -# Ftape, the floppy tape device driver
> -#
> -# CONFIG_DRM is not set
> -# CONFIG_RAW_DRIVER is not set
> -
> -#
> -# TPM devices
> -#
> -# CONFIG_TCG_TPM is not set
> -
> -#
> -# I2C support
> -#
> -# CONFIG_I2C is not set
> -
> -#
> -# Misc devices
> -#
> -
> -#
> -# Multimedia devices
> -#
> -# CONFIG_VIDEO_DEV is not set
> -
> -#
> -# Digital Video Broadcasting Devices
> -#
> -# CONFIG_DVB is not set
> -
> -#
> -# Graphics support
> -#
> -CONFIG_FB=y
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -CONFIG_FB_SOFT_CURSOR=y
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -CONFIG_FB_PXA=y
> -# CONFIG_FB_PXA_PARAMETERS is not set
> -# CONFIG_FB_VIRTUAL is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -CONFIG_FONTS=y
> -CONFIG_FONT_8x8=y
> -CONFIG_FONT_8x16=y
> -# CONFIG_FONT_6x11 is not set
> -# CONFIG_FONT_PEARL_8x8 is not set
> -# CONFIG_FONT_ACORN_8x8 is not set
> -# CONFIG_FONT_MINI_4x6 is not set
> -# CONFIG_FONT_SUN8x16 is not set
> -# CONFIG_FONT_SUN12x22 is not set
> -
> -#
> -# Logo configuration
> -#
> -CONFIG_LOGO=y
> -CONFIG_LOGO_LINUX_MONO=y
> -CONFIG_LOGO_LINUX_VGA16=y
> -CONFIG_LOGO_LINUX_CLUT224=y
> -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
> -
> -#
> -# Sound
> -#
> -# CONFIG_SOUND is not set
> -
> -#
> -# USB support
> -#
> -CONFIG_USB_ARCH_HAS_HCD=y
> -# CONFIG_USB_ARCH_HAS_OHCI is not set
> -# CONFIG_USB is not set
> -
> -#
> -# USB Gadget Support
> -#
> -# CONFIG_USB_GADGET is not set
> -
> -#
> -# MMC/SD Card support
> -#
> -# CONFIG_MMC is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT3_FS is not set
> -# CONFIG_JBD is not set
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -
> -#
> -# XFS support
> -#
> -# CONFIG_XFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_QUOTA is not set
> -CONFIG_DNOTIFY=y
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=y
> -CONFIG_MSDOS_FS=y
> -# CONFIG_VFAT_FS is not set
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_SYSFS=y
> -# CONFIG_DEVFS_FS is not set
> -# CONFIG_DEVPTS_FS_XATTR is not set
> -# CONFIG_TMPFS is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -CONFIG_RAMFS=y
> -
> -#
> -# Miscellaneous filesystems
> -#
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -# CONFIG_JFFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -# CONFIG_JFFS2_FS_NAND is not set
> -# CONFIG_JFFS2_FS_NOR_ECC is not set
> -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
> -CONFIG_JFFS2_ZLIB=y
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -
> -#
> -# Network File Systems
> -#
> -CONFIG_NFS_FS=y
> -# CONFIG_NFS_V3 is not set
> -# CONFIG_NFS_V4 is not set
> -# CONFIG_NFS_DIRECTIO is not set
> -# CONFIG_NFSD is not set
> -CONFIG_ROOT_NFS=y
> -CONFIG_LOCKD=y
> -CONFIG_SUNRPC=y
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -# CONFIG_CIFS is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -# CONFIG_PARTITION_ADVANCED is not set
> -CONFIG_MSDOS_PARTITION=y
> -
> -#
> -# Native Language Support
> -#
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -# CONFIG_NLS_CODEPAGE_437 is not set
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -# CONFIG_NLS_CODEPAGE_850 is not set
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -CONFIG_NLS_ISO8859_1=y
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -# CONFIG_NLS_ISO8859_15 is not set
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -# CONFIG_NLS_UTF8 is not set
> -
> -#
> -# Profiling support
> -#
> -# CONFIG_PROFILING is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_DEBUG_KERNEL=y
> -CONFIG_MAGIC_SYSRQ=y
> -CONFIG_LOG_BUF_SHIFT=14
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_DEBUG_SLAB is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -CONFIG_DEBUG_BUGVERBOSE=y
> -CONFIG_DEBUG_INFO=y
> -# CONFIG_DEBUG_FS is not set
> -CONFIG_FRAME_POINTER=y
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> -CONFIG_DEBUG_LL=y
> -# CONFIG_DEBUG_ICEDCC is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -
> -#
> -# Cryptographic options
> -#
> -# CONFIG_CRYPTO is not set
> -
> -#
> -# Hardware crypto devices
> -#
> -
> -#
> -# Library routines
> -#
> -# CONFIG_CRC_CCITT is not set
> -CONFIG_CRC32=y
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> diff --git a/arch/arm/configs/pxa2xx_defconfig b/arch/arm/configs/pxa2xx_defconfig
> new file mode 100644
> index 0000000..45d75f8
> --- /dev/null
> +++ b/arch/arm/configs/pxa2xx_defconfig
> @@ -0,0 +1,3408 @@
> +#
> +# Automatically generated make config: don't edit
> +# Linux kernel version: 2.6.35-rc1
> +# Sat Jun ?5 13:32:23 2010
> +#
> +CONFIG_ARM=y
> +CONFIG_HAVE_PWM=y
> +CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> +CONFIG_GENERIC_GPIO=y
> +CONFIG_GENERIC_TIME=y
> +# CONFIG_ARCH_USES_GETTIMEOFFSET is not set
> +CONFIG_GENERIC_CLOCKEVENTS=y
> +CONFIG_HAVE_PROC_CPU=y
> +CONFIG_GENERIC_HARDIRQS=y
> +CONFIG_STACKTRACE_SUPPORT=y
> +CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> +CONFIG_LOCKDEP_SUPPORT=y
> +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> +CONFIG_HARDIRQS_SW_RESEND=y
> +CONFIG_GENERIC_IRQ_PROBE=y
> +CONFIG_RWSEM_GENERIC_SPINLOCK=y
> +CONFIG_ARCH_HAS_CPUFREQ=y
> +CONFIG_GENERIC_HWEIGHT=y
> +CONFIG_GENERIC_CALIBRATE_DELAY=y
> +CONFIG_ZONE_DMA=y
> +CONFIG_NEED_DMA_MAP_STATE=y
> +CONFIG_ARCH_MTD_XIP=y
> +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> +CONFIG_VECTORS_BASE=0xffff0000
> +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> +CONFIG_CONSTRUCTORS=y
> +
> +#
> +# General setup
> +#
> +CONFIG_EXPERIMENTAL=y
> +CONFIG_BROKEN_ON_SMP=y
> +CONFIG_INIT_ENV_ARG_LIMIT=32
> +CONFIG_LOCALVERSION=""
> +CONFIG_LOCALVERSION_AUTO=y
> +CONFIG_HAVE_KERNEL_GZIP=y
> +CONFIG_HAVE_KERNEL_LZMA=y
> +CONFIG_HAVE_KERNEL_LZO=y
> +CONFIG_KERNEL_GZIP=y
> +# CONFIG_KERNEL_BZIP2 is not set
> +# CONFIG_KERNEL_LZMA is not set
> +# CONFIG_KERNEL_LZO is not set
> +CONFIG_SWAP=y
> +CONFIG_SYSVIPC=y
> +CONFIG_SYSVIPC_SYSCTL=y
> +CONFIG_POSIX_MQUEUE=y
> +CONFIG_POSIX_MQUEUE_SYSCTL=y
> +CONFIG_BSD_PROCESS_ACCT=y
> +CONFIG_BSD_PROCESS_ACCT_V3=y
> +# CONFIG_TASKSTATS is not set
> +# CONFIG_AUDIT is not set
> +
> +#
> +# RCU Subsystem
> +#
> +# CONFIG_TREE_RCU is not set
> +# CONFIG_TREE_PREEMPT_RCU is not set
> +CONFIG_TINY_RCU=y
> +# CONFIG_TREE_RCU_TRACE is not set
> +CONFIG_IKCONFIG=y
> +CONFIG_IKCONFIG_PROC=y
> +CONFIG_LOG_BUF_SHIFT=13
> +# CONFIG_CGROUPS is not set
> +CONFIG_SYSFS_DEPRECATED=y
> +CONFIG_SYSFS_DEPRECATED_V2=y
> +# CONFIG_RELAY is not set
> +CONFIG_NAMESPACES=y
> +# CONFIG_UTS_NS is not set
> +# CONFIG_IPC_NS is not set
> +# CONFIG_USER_NS is not set
> +# CONFIG_PID_NS is not set
> +# CONFIG_NET_NS is not set
> +CONFIG_BLK_DEV_INITRD=y
> +CONFIG_INITRAMFS_SOURCE=""
> +CONFIG_RD_GZIP=y
> +CONFIG_RD_BZIP2=y
> +CONFIG_RD_LZMA=y
> +# CONFIG_RD_LZO is not set
> +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> +CONFIG_SYSCTL=y
> +CONFIG_ANON_INODES=y
> +CONFIG_EMBEDDED=y
> +CONFIG_UID16=y
> +CONFIG_SYSCTL_SYSCALL=y
> +CONFIG_KALLSYMS=y
> +CONFIG_KALLSYMS_ALL=y
> +CONFIG_KALLSYMS_EXTRA_PASS=y
> +CONFIG_HOTPLUG=y
> +CONFIG_PRINTK=y
> +CONFIG_BUG=y
> +CONFIG_ELF_CORE=y
> +CONFIG_BASE_FULL=y
> +CONFIG_FUTEX=y
> +CONFIG_EPOLL=y
> +CONFIG_SIGNALFD=y
> +CONFIG_TIMERFD=y
> +CONFIG_EVENTFD=y
> +CONFIG_SHMEM=y
> +CONFIG_AIO=y
> +CONFIG_HAVE_PERF_EVENTS=y
> +CONFIG_PERF_USE_VMALLOC=y
> +
> +#
> +# Kernel Performance Events And Counters
> +#
> +# CONFIG_PERF_EVENTS is not set
> +# CONFIG_PERF_COUNTERS is not set
> +CONFIG_VM_EVENT_COUNTERS=y
> +CONFIG_PCI_QUIRKS=y
> +CONFIG_SLUB_DEBUG=y
> +CONFIG_COMPAT_BRK=y
> +# CONFIG_SLAB is not set
> +CONFIG_SLUB=y
> +# CONFIG_SLOB is not set
> +# CONFIG_PROFILING is not set
> +CONFIG_HAVE_OPROFILE=y
> +CONFIG_KPROBES=y
> +CONFIG_KRETPROBES=y
> +CONFIG_HAVE_KPROBES=y
> +CONFIG_HAVE_KRETPROBES=y
> +CONFIG_HAVE_CLK=y
> +
> +#
> +# GCOV-based kernel profiling
> +#
> +# CONFIG_GCOV_KERNEL is not set
> +CONFIG_SLOW_WORK=y
> +# CONFIG_SLOW_WORK_DEBUG is not set
> +CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> +CONFIG_SLABINFO=y
> +CONFIG_RT_MUTEXES=y
> +CONFIG_BASE_SMALL=0
> +CONFIG_MODULES=y
> +# CONFIG_MODULE_FORCE_LOAD is not set
> +CONFIG_MODULE_UNLOAD=y
> +CONFIG_MODULE_FORCE_UNLOAD=y
> +CONFIG_MODVERSIONS=y
> +CONFIG_MODULE_SRCVERSION_ALL=y
> +CONFIG_BLOCK=y
> +CONFIG_LBDAF=y
> +CONFIG_BLK_DEV_BSG=y
> +# CONFIG_BLK_DEV_INTEGRITY is not set
> +
> +#
> +# IO Schedulers
> +#
> +CONFIG_IOSCHED_NOOP=y
> +CONFIG_IOSCHED_DEADLINE=y
> +CONFIG_IOSCHED_CFQ=y
> +CONFIG_DEFAULT_DEADLINE=y
> +# CONFIG_DEFAULT_CFQ is not set
> +# CONFIG_DEFAULT_NOOP is not set
> +CONFIG_DEFAULT_IOSCHED="deadline"
> +# CONFIG_INLINE_SPIN_TRYLOCK is not set
> +# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
> +# CONFIG_INLINE_SPIN_LOCK is not set
> +# CONFIG_INLINE_SPIN_LOCK_BH is not set
> +# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
> +# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
> +# CONFIG_INLINE_SPIN_UNLOCK is not set
> +# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
> +# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
> +# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
> +# CONFIG_INLINE_READ_TRYLOCK is not set
> +# CONFIG_INLINE_READ_LOCK is not set
> +# CONFIG_INLINE_READ_LOCK_BH is not set
> +# CONFIG_INLINE_READ_LOCK_IRQ is not set
> +# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
> +# CONFIG_INLINE_READ_UNLOCK is not set
> +# CONFIG_INLINE_READ_UNLOCK_BH is not set
> +# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
> +# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
> +# CONFIG_INLINE_WRITE_TRYLOCK is not set
> +# CONFIG_INLINE_WRITE_LOCK is not set
> +# CONFIG_INLINE_WRITE_LOCK_BH is not set
> +# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
> +# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
> +# CONFIG_INLINE_WRITE_UNLOCK is not set
> +# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
> +# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
> +# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
> +# CONFIG_MUTEX_SPIN_ON_OWNER is not set
> +CONFIG_FREEZER=y
> +
> +#
> +# System Type
> +#
> +CONFIG_MMU=y
> +# CONFIG_ARCH_AAEC2000 is not set
> +# CONFIG_ARCH_INTEGRATOR is not set
> +# CONFIG_ARCH_REALVIEW is not set
> +# CONFIG_ARCH_VERSATILE is not set
> +# CONFIG_ARCH_VEXPRESS is not set
> +# CONFIG_ARCH_AT91 is not set
> +# CONFIG_ARCH_BCMRING is not set
> +# CONFIG_ARCH_CLPS711X is not set
> +# CONFIG_ARCH_CNS3XXX is not set
> +# CONFIG_ARCH_GEMINI is not set
> +# CONFIG_ARCH_EBSA110 is not set
> +# CONFIG_ARCH_EP93XX is not set
> +# CONFIG_ARCH_FOOTBRIDGE is not set
> +# CONFIG_ARCH_MXC is not set
> +# CONFIG_ARCH_STMP3XXX is not set
> +# CONFIG_ARCH_NETX is not set
> +# CONFIG_ARCH_H720X is not set
> +# CONFIG_ARCH_IOP13XX is not set
> +# CONFIG_ARCH_IOP32X is not set
> +# CONFIG_ARCH_IOP33X is not set
> +# CONFIG_ARCH_IXP23XX is not set
> +# CONFIG_ARCH_IXP2000 is not set
> +# CONFIG_ARCH_IXP4XX is not set
> +# CONFIG_ARCH_L7200 is not set
> +# CONFIG_ARCH_DOVE is not set
> +# CONFIG_ARCH_KIRKWOOD is not set
> +# CONFIG_ARCH_LOKI is not set
> +# CONFIG_ARCH_MV78XX0 is not set
> +# CONFIG_ARCH_ORION5X is not set
> +# CONFIG_ARCH_MMP is not set
> +# CONFIG_ARCH_KS8695 is not set
> +# CONFIG_ARCH_NS9XXX is not set
> +# CONFIG_ARCH_W90X900 is not set
> +# CONFIG_ARCH_NUC93X is not set
> +# CONFIG_ARCH_PNX4008 is not set
> +CONFIG_ARCH_PXA=y
> +# CONFIG_ARCH_MSM is not set
> +# CONFIG_ARCH_SHMOBILE is not set
> +# CONFIG_ARCH_RPC is not set
> +# CONFIG_ARCH_SA1100 is not set
> +# CONFIG_ARCH_S3C2410 is not set
> +# CONFIG_ARCH_S3C64XX is not set
> +# CONFIG_ARCH_S5P6440 is not set
> +# CONFIG_ARCH_S5P6442 is not set
> +# CONFIG_ARCH_S5PC100 is not set
> +# CONFIG_ARCH_S5PV210 is not set
> +# CONFIG_ARCH_SHARK is not set
> +# CONFIG_ARCH_LH7A40X is not set
> +# CONFIG_ARCH_U300 is not set
> +# CONFIG_ARCH_U8500 is not set
> +# CONFIG_ARCH_NOMADIK is not set
> +# CONFIG_ARCH_DAVINCI is not set
> +# CONFIG_ARCH_OMAP is not set
> +# CONFIG_PLAT_SPEAR is not set
> +
> +#
> +# Intel PXA2xx/PXA3xx Implementations
> +#
> +
> +#
> +# Intel/Marvell Dev Platforms (sorted by hardware release time)
> +#
> +CONFIG_ARCH_LUBBOCK=y
> +CONFIG_MACH_MAINSTONE=y
> +# CONFIG_MACH_ZYLONITE300 is not set
> +# CONFIG_MACH_ZYLONITE320 is not set
> +# CONFIG_MACH_LITTLETON is not set
> +# CONFIG_MACH_TAVOREVB is not set
> +# CONFIG_MACH_SAAR is not set
> +
> +#
> +# Third Party Dev Platforms (sorted by vendor name)
> +#
> +CONFIG_ARCH_PXA_IDP=y
> +CONFIG_ARCH_VIPER=y
> +CONFIG_MACH_ARCOM_ZEUS=y
> +# CONFIG_MACH_BALLOON3 is not set
> +# CONFIG_MACH_CSB726 is not set
> +CONFIG_MACH_ARMCORE=y
> +CONFIG_MACH_EM_X270=y
> +CONFIG_MACH_EXEDA=y
> +# CONFIG_MACH_CM_X300 is not set
> +# CONFIG_MACH_CAPC7117 is not set
> +CONFIG_ARCH_GUMSTIX=y
> +CONFIG_GUMSTIX_AM200EPD=y
> +# CONFIG_GUMSTIX_AM300EPD is not set
> +CONFIG_MACH_INTELMOTE2=y
> +# CONFIG_MACH_STARGATE2 is not set
> +CONFIG_MACH_XCEP=y
> +CONFIG_TRIZEPS_PXA=y
> +CONFIG_MACH_TRIZEPS4=y
> +# CONFIG_MACH_TRIZEPS4WL is not set
> +CONFIG_MACH_TRIZEPS_CONXS=y
> +# CONFIG_MACH_TRIZEPS_UCONXS is not set
> +# CONFIG_MACH_TRIZEPS_ANY is not set
> +CONFIG_ARCOM_PCMCIA=y
> +CONFIG_TRIZEPS_PCMCIA=y
> +CONFIG_MACH_LOGICPD_PXA270=y
> +CONFIG_MACH_PCM027=y
> +CONFIG_MACH_PCM990_BASEBOARD=y
> +CONFIG_PCM990_DISPLAY_SHARP=y
> +# CONFIG_PCM990_DISPLAY_NEC is not set
> +# CONFIG_PCM990_DISPLAY_NONE is not set
> +CONFIG_MACH_COLIBRI=y
> +# CONFIG_MACH_COLIBRI_PXA270_EVALBOARD is not set
> +# CONFIG_MACH_COLIBRI_PXA270_INCOME is not set
> +# CONFIG_MACH_COLIBRI300 is not set
> +# CONFIG_MACH_COLIBRI320 is not set
> +# CONFIG_MACH_VPAC270 is not set
> +
> +#
> +# End-user Products (sorted by vendor name)
> +#
> +CONFIG_MACH_H4700=y
> +CONFIG_MACH_H5000=y
> +# CONFIG_MACH_HIMALAYA is not set
> +CONFIG_MACH_MAGICIAN=y
> +# CONFIG_MACH_MIOA701 is not set
> +CONFIG_PXA_EZX=y
> +CONFIG_MACH_EZX_A780=y
> +CONFIG_MACH_EZX_E680=y
> +CONFIG_MACH_EZX_A1200=y
> +CONFIG_MACH_EZX_A910=y
> +CONFIG_MACH_EZX_E6=y
> +CONFIG_MACH_EZX_E2=y
> +# CONFIG_MACH_MP900C is not set
> +CONFIG_ARCH_PXA_PALM=y
> +CONFIG_MACH_PALMTE2=y
> +CONFIG_MACH_PALMTC=y
> +CONFIG_MACH_PALMT5=y
> +CONFIG_MACH_PALMTX=y
> +CONFIG_MACH_PALMZ72=y
> +CONFIG_MACH_PALMLD=y
> +CONFIG_PALM_TREO=y
> +CONFIG_MACH_CENTRO=y
> +CONFIG_MACH_TREO680=y
> +# CONFIG_MACH_RAUMFELD_RC is not set
> +# CONFIG_MACH_RAUMFELD_CONNECTOR is not set
> +# CONFIG_MACH_RAUMFELD_SPEAKER is not set
> +# CONFIG_PXA_SHARPSL is not set
> +# CONFIG_MACH_ICONTROL is not set
> +CONFIG_ARCH_PXA_ESERIES=y
> +CONFIG_MACH_E330=y
> +CONFIG_MACH_E350=y
> +CONFIG_MACH_E740=y
> +CONFIG_MACH_E750=y
> +CONFIG_MACH_E400=y
> +CONFIG_MACH_E800=y
> +# CONFIG_MACH_ZIPIT2 is not set
> +CONFIG_PXA25x=y
> +CONFIG_PXA27x=y
> +CONFIG_PXA_HAVE_BOARD_IRQS=y
> +CONFIG_PXA_HAVE_ISA_IRQS=y
> +CONFIG_PXA_SSP=y
> +CONFIG_PLAT_PXA=y
> +
> +#
> +# Processor Type
> +#
> +CONFIG_CPU_XSCALE=y
> +CONFIG_CPU_32v5=y
> +CONFIG_CPU_ABRT_EV5T=y
> +CONFIG_CPU_PABRT_LEGACY=y
> +CONFIG_CPU_CACHE_VIVT=y
> +CONFIG_CPU_TLB_V4WBI=y
> +CONFIG_CPU_CP15=y
> +CONFIG_CPU_CP15_MMU=y
> +
> +#
> +# Processor Features
> +#
> +CONFIG_ARM_THUMB=y
> +# CONFIG_CPU_DCACHE_DISABLE is not set
> +CONFIG_ARM_L1_CACHE_SHIFT=5
> +CONFIG_IWMMXT=y
> +CONFIG_XSCALE_PMU=y
> +CONFIG_CPU_HAS_PMU=y
> +CONFIG_SA1111=y
> +CONFIG_DMABOUNCE=y
> +CONFIG_COMMON_CLKDEV=y
> +CONFIG_FORCE_MAX_ZONEORDER=9
> +
> +#
> +# Bus support
> +#
> +CONFIG_ISA=y
> +CONFIG_PCI=y
> +CONFIG_PCI_SYSCALL=y
> +CONFIG_PCI_HOST_ITE8152=y
> +# CONFIG_ARCH_SUPPORTS_MSI is not set
> +# CONFIG_PCI_DEBUG is not set
> +# CONFIG_PCI_STUB is not set
> +# CONFIG_PCI_IOV is not set
> +CONFIG_PCCARD=m
> +CONFIG_PCMCIA=m
> +CONFIG_PCMCIA_LOAD_CIS=y
> +CONFIG_CARDBUS=y
> +
> +#
> +# PC-card bridges
> +#
> +CONFIG_YENTA=m
> +CONFIG_YENTA_O2=y
> +CONFIG_YENTA_RICOH=y
> +CONFIG_YENTA_TI=y
> +CONFIG_YENTA_ENE_TUNE=y
> +CONFIG_YENTA_TOSHIBA=y
> +# CONFIG_PD6729 is not set
> +# CONFIG_I82092 is not set
> +# CONFIG_I82365 is not set
> +# CONFIG_TCIC is not set
> +CONFIG_PCMCIA_SOC_COMMON=m
> +CONFIG_PCMCIA_PXA2XX=m
> +# CONFIG_PCMCIA_DEBUG is not set
> +CONFIG_PCMCIA_PROBE=y
> +CONFIG_PCCARD_NONSTATIC=y
> +
> +#
> +# Kernel Features
> +#
> +CONFIG_TICK_ONESHOT=y
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> +CONFIG_VMSPLIT_3G=y
> +# CONFIG_VMSPLIT_2G is not set
> +# CONFIG_VMSPLIT_1G is not set
> +CONFIG_PAGE_OFFSET=0xC0000000
> +CONFIG_PREEMPT_NONE=y
> +# CONFIG_PREEMPT_VOLUNTARY is not set
> +# CONFIG_PREEMPT is not set
> +CONFIG_HZ=100
> +CONFIG_AEABI=y
> +CONFIG_OABI_COMPAT=y
> +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> +# CONFIG_HIGHMEM is not set
> +CONFIG_SELECT_MEMORY_MODEL=y
> +CONFIG_FLATMEM_MANUAL=y
> +# CONFIG_DISCONTIGMEM_MANUAL is not set
> +# CONFIG_SPARSEMEM_MANUAL is not set
> +CONFIG_FLATMEM=y
> +CONFIG_FLAT_NODE_MEM_MAP=y
> +CONFIG_PAGEFLAGS_EXTENDED=y
> +CONFIG_SPLIT_PTLOCK_CPUS=999999
> +# CONFIG_PHYS_ADDR_T_64BIT is not set
> +CONFIG_ZONE_DMA_FLAG=1
> +CONFIG_BOUNCE=y
> +CONFIG_VIRT_TO_BUS=y
> +# CONFIG_KSM is not set
> +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
> +CONFIG_LEDS=y
> +CONFIG_LEDS_CPU=y
> +CONFIG_ALIGNMENT_TRAP=y
> +# CONFIG_UACCESS_WITH_MEMCPY is not set
> +
> +#
> +# Boot options
> +#
> +CONFIG_ZBOOT_ROM_TEXT=0x0
> +CONFIG_ZBOOT_ROM_BSS=0x0
> +CONFIG_CMDLINE=""
> +# CONFIG_CMDLINE_FORCE is not set
> +# CONFIG_XIP_KERNEL is not set
> +CONFIG_KEXEC=y
> +CONFIG_ATAGS_PROC=y
> +
> +#
> +# CPU Power Management
> +#
> +CONFIG_CPU_FREQ=y
> +CONFIG_CPU_FREQ_TABLE=y
> +CONFIG_CPU_FREQ_DEBUG=y
> +CONFIG_CPU_FREQ_STAT=y
> +# CONFIG_CPU_FREQ_STAT_DETAILS is not set
> +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
> +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
> +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
> +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
> +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
> +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
> +CONFIG_CPU_FREQ_GOV_POWERSAVE=m
> +CONFIG_CPU_FREQ_GOV_USERSPACE=m
> +CONFIG_CPU_FREQ_GOV_ONDEMAND=m
> +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
> +CONFIG_CPU_FREQ_PXA=y
> +CONFIG_CPU_IDLE=y
> +CONFIG_CPU_IDLE_GOV_LADDER=y
> +CONFIG_CPU_IDLE_GOV_MENU=y
> +
> +#
> +# Floating point emulation
> +#
> +
> +#
> +# At least one emulation must be selected
> +#
> +CONFIG_FPE_NWFPE=y
> +CONFIG_FPE_NWFPE_XP=y
> +CONFIG_FPE_FASTFPE=y
> +
> +#
> +# Userspace binary formats
> +#
> +CONFIG_BINFMT_ELF=y
> +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> +CONFIG_HAVE_AOUT=y
> +CONFIG_BINFMT_AOUT=m
> +CONFIG_BINFMT_MISC=m
> +
> +#
> +# Power management options
> +#
> +CONFIG_PM=y
> +# CONFIG_PM_DEBUG is not set
> +CONFIG_PM_SLEEP=y
> +CONFIG_SUSPEND=y
> +CONFIG_SUSPEND_FREEZER=y
> +CONFIG_APM_EMULATION=y
> +CONFIG_PM_RUNTIME=y
> +CONFIG_PM_OPS=y
> +CONFIG_ARCH_SUSPEND_POSSIBLE=y
> +CONFIG_NET=y
> +
> +#
> +# Networking options
> +#
> +CONFIG_PACKET=y
> +CONFIG_UNIX=y
> +CONFIG_XFRM=y
> +CONFIG_XFRM_USER=m
> +# CONFIG_XFRM_SUB_POLICY is not set
> +# CONFIG_XFRM_MIGRATE is not set
> +# CONFIG_XFRM_STATISTICS is not set
> +CONFIG_XFRM_IPCOMP=m
> +CONFIG_NET_KEY=y
> +# CONFIG_NET_KEY_MIGRATE is not set
> +CONFIG_INET=y
> +CONFIG_IP_MULTICAST=y
> +# CONFIG_IP_ADVANCED_ROUTER is not set
> +CONFIG_IP_FIB_HASH=y
> +CONFIG_IP_PNP=y
> +CONFIG_IP_PNP_DHCP=y
> +CONFIG_IP_PNP_BOOTP=y
> +CONFIG_IP_PNP_RARP=y
> +# CONFIG_NET_IPIP is not set
> +# CONFIG_NET_IPGRE is not set
> +# CONFIG_IP_MROUTE is not set
> +# CONFIG_ARPD is not set
> +CONFIG_SYN_COOKIES=y
> +# CONFIG_INET_AH is not set
> +# CONFIG_INET_ESP is not set
> +# CONFIG_INET_IPCOMP is not set
> +# CONFIG_INET_XFRM_TUNNEL is not set
> +CONFIG_INET_TUNNEL=m
> +CONFIG_INET_XFRM_MODE_TRANSPORT=y
> +CONFIG_INET_XFRM_MODE_TUNNEL=y
> +CONFIG_INET_XFRM_MODE_BEET=y
> +CONFIG_INET_LRO=y
> +CONFIG_INET_DIAG=y
> +CONFIG_INET_TCP_DIAG=y
> +# CONFIG_TCP_CONG_ADVANCED is not set
> +CONFIG_TCP_CONG_CUBIC=y
> +CONFIG_DEFAULT_TCP_CONG="cubic"
> +# CONFIG_TCP_MD5SIG is not set
> +CONFIG_IPV6=y
> +# CONFIG_IPV6_PRIVACY is not set
> +# CONFIG_IPV6_ROUTER_PREF is not set
> +# CONFIG_IPV6_OPTIMISTIC_DAD is not set
> +CONFIG_INET6_AH=m
> +CONFIG_INET6_ESP=m
> +CONFIG_INET6_IPCOMP=m
> +CONFIG_IPV6_MIP6=m
> +CONFIG_INET6_XFRM_TUNNEL=m
> +CONFIG_INET6_TUNNEL=m
> +CONFIG_INET6_XFRM_MODE_TRANSPORT=m
> +CONFIG_INET6_XFRM_MODE_TUNNEL=m
> +CONFIG_INET6_XFRM_MODE_BEET=m
> +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
> +CONFIG_IPV6_SIT=m
> +# CONFIG_IPV6_SIT_6RD is not set
> +CONFIG_IPV6_NDISC_NODETYPE=y
> +CONFIG_IPV6_TUNNEL=m
> +CONFIG_IPV6_MULTIPLE_TABLES=y
> +CONFIG_IPV6_SUBTREES=y
> +# CONFIG_IPV6_MROUTE is not set
> +# CONFIG_NETLABEL is not set
> +# CONFIG_NETWORK_SECMARK is not set
> +CONFIG_NETFILTER=y
> +# CONFIG_NETFILTER_DEBUG is not set
> +CONFIG_NETFILTER_ADVANCED=y
> +CONFIG_BRIDGE_NETFILTER=y
> +
> +#
> +# Core Netfilter Configuration
> +#
> +CONFIG_NETFILTER_NETLINK=m
> +CONFIG_NETFILTER_NETLINK_QUEUE=m
> +CONFIG_NETFILTER_NETLINK_LOG=m
> +CONFIG_NF_CONNTRACK=m
> +CONFIG_NF_CT_ACCT=y
> +CONFIG_NF_CONNTRACK_MARK=y
> +CONFIG_NF_CONNTRACK_EVENTS=y
> +# CONFIG_NF_CT_PROTO_DCCP is not set
> +CONFIG_NF_CT_PROTO_GRE=m
> +CONFIG_NF_CT_PROTO_SCTP=m
> +CONFIG_NF_CT_PROTO_UDPLITE=m
> +CONFIG_NF_CONNTRACK_AMANDA=m
> +CONFIG_NF_CONNTRACK_FTP=m
> +CONFIG_NF_CONNTRACK_H323=m
> +CONFIG_NF_CONNTRACK_IRC=m
> +CONFIG_NF_CONNTRACK_NETBIOS_NS=m
> +CONFIG_NF_CONNTRACK_PPTP=m
> +CONFIG_NF_CONNTRACK_SANE=m
> +CONFIG_NF_CONNTRACK_SIP=m
> +CONFIG_NF_CONNTRACK_TFTP=m
> +CONFIG_NF_CT_NETLINK=m
> +# CONFIG_NETFILTER_TPROXY is not set
> +CONFIG_NETFILTER_XTABLES=m
> +
> +#
> +# Xtables combined modules
> +#
> +CONFIG_NETFILTER_XT_MARK=m
> +CONFIG_NETFILTER_XT_CONNMARK=m
> +
> +#
> +# Xtables targets
> +#
> +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
> +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
> +# CONFIG_NETFILTER_XT_TARGET_CT is not set
> +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
> +CONFIG_NETFILTER_XT_TARGET_HL=m
> +CONFIG_NETFILTER_XT_TARGET_LED=m
> +CONFIG_NETFILTER_XT_TARGET_MARK=m
> +CONFIG_NETFILTER_XT_TARGET_NFLOG=m
> +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
> +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set
> +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
> +# CONFIG_NETFILTER_XT_TARGET_TEE is not set
> +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
> +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
> +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
> +
> +#
> +# Xtables matches
> +#
> +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
> +CONFIG_NETFILTER_XT_MATCH_COMMENT=m
> +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
> +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
> +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
> +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
> +CONFIG_NETFILTER_XT_MATCH_DCCP=m
> +CONFIG_NETFILTER_XT_MATCH_DSCP=m
> +CONFIG_NETFILTER_XT_MATCH_ESP=m
> +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
> +CONFIG_NETFILTER_XT_MATCH_HELPER=m
> +CONFIG_NETFILTER_XT_MATCH_HL=m
> +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
> +CONFIG_NETFILTER_XT_MATCH_LENGTH=m
> +CONFIG_NETFILTER_XT_MATCH_LIMIT=m
> +CONFIG_NETFILTER_XT_MATCH_MAC=m
> +CONFIG_NETFILTER_XT_MATCH_MARK=m
> +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
> +# CONFIG_NETFILTER_XT_MATCH_OSF is not set
> +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
> +CONFIG_NETFILTER_XT_MATCH_POLICY=m
> +# CONFIG_NETFILTER_XT_MATCH_PHYSDEV is not set
> +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
> +CONFIG_NETFILTER_XT_MATCH_QUOTA=m
> +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
> +CONFIG_NETFILTER_XT_MATCH_REALM=m
> +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
> +CONFIG_NETFILTER_XT_MATCH_SCTP=m
> +CONFIG_NETFILTER_XT_MATCH_STATE=m
> +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
> +CONFIG_NETFILTER_XT_MATCH_STRING=m
> +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
> +CONFIG_NETFILTER_XT_MATCH_TIME=m
> +CONFIG_NETFILTER_XT_MATCH_U32=m
> +# CONFIG_IP_VS is not set
> +
> +#
> +# IP: Netfilter Configuration
> +#
> +CONFIG_NF_DEFRAG_IPV4=m
> +CONFIG_NF_CONNTRACK_IPV4=m
> +CONFIG_NF_CONNTRACK_PROC_COMPAT=y
> +CONFIG_IP_NF_QUEUE=m
> +CONFIG_IP_NF_IPTABLES=m
> +CONFIG_IP_NF_MATCH_ADDRTYPE=m
> +CONFIG_IP_NF_MATCH_AH=m
> +CONFIG_IP_NF_MATCH_ECN=m
> +CONFIG_IP_NF_MATCH_TTL=m
> +CONFIG_IP_NF_FILTER=m
> +CONFIG_IP_NF_TARGET_REJECT=m
> +CONFIG_IP_NF_TARGET_LOG=m
> +CONFIG_IP_NF_TARGET_ULOG=m
> +CONFIG_NF_NAT=m
> +CONFIG_NF_NAT_NEEDED=y
> +CONFIG_IP_NF_TARGET_MASQUERADE=m
> +CONFIG_IP_NF_TARGET_NETMAP=m
> +CONFIG_IP_NF_TARGET_REDIRECT=m
> +CONFIG_NF_NAT_SNMP_BASIC=m
> +CONFIG_NF_NAT_PROTO_GRE=m
> +CONFIG_NF_NAT_PROTO_UDPLITE=m
> +CONFIG_NF_NAT_PROTO_SCTP=m
> +CONFIG_NF_NAT_FTP=m
> +CONFIG_NF_NAT_IRC=m
> +CONFIG_NF_NAT_TFTP=m
> +CONFIG_NF_NAT_AMANDA=m
> +CONFIG_NF_NAT_PPTP=m
> +CONFIG_NF_NAT_H323=m
> +CONFIG_NF_NAT_SIP=m
> +CONFIG_IP_NF_MANGLE=m
> +CONFIG_IP_NF_TARGET_CLUSTERIP=m
> +CONFIG_IP_NF_TARGET_ECN=m
> +CONFIG_IP_NF_TARGET_TTL=m
> +CONFIG_IP_NF_RAW=m
> +# CONFIG_IP_NF_SECURITY is not set
> +CONFIG_IP_NF_ARPTABLES=m
> +CONFIG_IP_NF_ARPFILTER=m
> +CONFIG_IP_NF_ARP_MANGLE=m
> +
> +#
> +# IPv6: Netfilter Configuration
> +#
> +CONFIG_NF_CONNTRACK_IPV6=m
> +CONFIG_IP6_NF_QUEUE=m
> +CONFIG_IP6_NF_IPTABLES=m
> +CONFIG_IP6_NF_MATCH_AH=m
> +CONFIG_IP6_NF_MATCH_EUI64=m
> +CONFIG_IP6_NF_MATCH_FRAG=m
> +CONFIG_IP6_NF_MATCH_OPTS=m
> +CONFIG_IP6_NF_MATCH_HL=m
> +CONFIG_IP6_NF_MATCH_IPV6HEADER=m
> +CONFIG_IP6_NF_MATCH_MH=m
> +CONFIG_IP6_NF_MATCH_RT=m
> +CONFIG_IP6_NF_TARGET_HL=m
> +CONFIG_IP6_NF_TARGET_LOG=m
> +CONFIG_IP6_NF_FILTER=m
> +CONFIG_IP6_NF_TARGET_REJECT=m
> +CONFIG_IP6_NF_MANGLE=m
> +CONFIG_IP6_NF_RAW=m
> +# CONFIG_IP6_NF_SECURITY is not set
> +# CONFIG_BRIDGE_NF_EBTABLES is not set
> +# CONFIG_IP_DCCP is not set
> +# CONFIG_IP_SCTP is not set
> +# CONFIG_RDS is not set
> +# CONFIG_TIPC is not set
> +# CONFIG_ATM is not set
> +# CONFIG_L2TP is not set
> +CONFIG_STP=m
> +CONFIG_BRIDGE=m
> +CONFIG_BRIDGE_IGMP_SNOOPING=y
> +# CONFIG_NET_DSA is not set
> +CONFIG_VLAN_8021Q=m
> +# CONFIG_VLAN_8021Q_GVRP is not set
> +# CONFIG_DECNET is not set
> +CONFIG_LLC=m
> +# CONFIG_LLC2 is not set
> +# CONFIG_IPX is not set
> +# CONFIG_ATALK is not set
> +# CONFIG_X25 is not set
> +# CONFIG_LAPB is not set
> +# CONFIG_ECONET is not set
> +# CONFIG_WAN_ROUTER is not set
> +# CONFIG_PHONET is not set
> +CONFIG_IEEE802154=y
> +# CONFIG_NET_SCHED is not set
> +CONFIG_NET_CLS_ROUTE=y
> +# CONFIG_DCB is not set
> +
> +#
> +# Network testing
> +#
> +# CONFIG_NET_PKTGEN is not set
> +# CONFIG_NET_TCPPROBE is not set
> +# CONFIG_HAMRADIO is not set
> +# CONFIG_CAN is not set
> +CONFIG_IRDA=m
> +
> +#
> +# IrDA protocols
> +#
> +CONFIG_IRLAN=m
> +CONFIG_IRNET=m
> +CONFIG_IRCOMM=m
> +CONFIG_IRDA_ULTRA=y
> +
> +#
> +# IrDA options
> +#
> +CONFIG_IRDA_CACHE_LAST_LSAP=y
> +CONFIG_IRDA_FAST_RR=y
> +CONFIG_IRDA_DEBUG=y
> +
> +#
> +# Infrared-port device drivers
> +#
> +
> +#
> +# SIR device drivers
> +#
> +CONFIG_IRTTY_SIR=m
> +
> +#
> +# Dongle support
> +#
> +# CONFIG_DONGLE is not set
> +# CONFIG_KINGSUN_DONGLE is not set
> +# CONFIG_KSDAZZLE_DONGLE is not set
> +# CONFIG_KS959_DONGLE is not set
> +
> +#
> +# FIR device drivers
> +#
> +# CONFIG_USB_IRDA is not set
> +# CONFIG_SIGMATEL_FIR is not set
> +# CONFIG_TOSHIBA_FIR is not set
> +# CONFIG_VLSI_FIR is not set
> +CONFIG_PXA_FICP=m
> +# CONFIG_MCS_FIR is not set
> +CONFIG_BT=m
> +CONFIG_BT_L2CAP=m
> +# CONFIG_BT_L2CAP_EXT_FEATURES is not set
> +CONFIG_BT_SCO=m
> +CONFIG_BT_RFCOMM=m
> +CONFIG_BT_RFCOMM_TTY=y
> +CONFIG_BT_BNEP=m
> +CONFIG_BT_BNEP_MC_FILTER=y
> +CONFIG_BT_BNEP_PROTO_FILTER=y
> +CONFIG_BT_HIDP=m
> +
> +#
> +# Bluetooth device drivers
> +#
> +CONFIG_BT_HCIBTUSB=m
> +CONFIG_BT_HCIBTSDIO=m
> +CONFIG_BT_HCIUART=m
> +CONFIG_BT_HCIUART_H4=y
> +CONFIG_BT_HCIUART_BCSP=y
> +# CONFIG_BT_HCIUART_LL is not set
> +CONFIG_BT_HCIBCM203X=m
> +CONFIG_BT_HCIBPA10X=m
> +CONFIG_BT_HCIBFUSB=m
> +# CONFIG_BT_HCIDTL1 is not set
> +# CONFIG_BT_HCIBT3C is not set
> +# CONFIG_BT_HCIBLUECARD is not set
> +# CONFIG_BT_HCIBTUART is not set
> +CONFIG_BT_HCIVHCI=m
> +CONFIG_BT_MRVL=m
> +CONFIG_BT_MRVL_SDIO=m
> +# CONFIG_BT_ATH3K is not set
> +# CONFIG_AF_RXRPC is not set
> +CONFIG_FIB_RULES=y
> +CONFIG_WIRELESS=y
> +CONFIG_WIRELESS_EXT=y
> +CONFIG_WEXT_CORE=y
> +CONFIG_WEXT_PROC=y
> +CONFIG_WEXT_SPY=y
> +CONFIG_WEXT_PRIV=y
> +CONFIG_CFG80211=m
> +# CONFIG_NL80211_TESTMODE is not set
> +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
> +# CONFIG_CFG80211_REG_DEBUG is not set
> +CONFIG_CFG80211_DEFAULT_PS=y
> +# CONFIG_CFG80211_DEBUGFS is not set
> +# CONFIG_CFG80211_INTERNAL_REGDB is not set
> +CONFIG_CFG80211_WEXT=y
> +CONFIG_WIRELESS_EXT_SYSFS=y
> +CONFIG_LIB80211=y
> +CONFIG_LIB80211_CRYPT_WEP=y
> +CONFIG_LIB80211_CRYPT_CCMP=y
> +CONFIG_LIB80211_CRYPT_TKIP=y
> +# CONFIG_LIB80211_DEBUG is not set
> +CONFIG_MAC80211=m
> +CONFIG_MAC80211_HAS_RC=y
> +CONFIG_MAC80211_RC_PID=y
> +CONFIG_MAC80211_RC_MINSTREL=y
> +# CONFIG_MAC80211_RC_DEFAULT_PID is not set
> +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
> +CONFIG_MAC80211_RC_DEFAULT="minstrel"
> +# CONFIG_MAC80211_MESH is not set
> +# CONFIG_MAC80211_LEDS is not set
> +# CONFIG_MAC80211_DEBUGFS is not set
> +# CONFIG_MAC80211_DEBUG_MENU is not set
> +# CONFIG_WIMAX is not set
> +# CONFIG_RFKILL is not set
> +# CONFIG_NET_9P is not set
> +# CONFIG_CAIF is not set
> +
> +#
> +# Device Drivers
> +#
> +
> +#
> +# Generic Driver Options
> +#
> +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
> +CONFIG_STANDALONE=y
> +CONFIG_PREVENT_FIRMWARE_BUILD=y
> +CONFIG_FW_LOADER=y
> +CONFIG_FIRMWARE_IN_KERNEL=y
> +CONFIG_EXTRA_FIRMWARE=""
> +# CONFIG_DEBUG_DRIVER is not set
> +# CONFIG_DEBUG_DEVRES is not set
> +# CONFIG_SYS_HYPERVISOR is not set
> +CONFIG_CONNECTOR=y
> +CONFIG_PROC_EVENTS=y
> +CONFIG_MTD=y
> +# CONFIG_MTD_DEBUG is not set
> +# CONFIG_MTD_TESTS is not set
> +CONFIG_MTD_CONCAT=y
> +CONFIG_MTD_PARTITIONS=y
> +CONFIG_MTD_REDBOOT_PARTS=y
> +CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
> +CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
> +CONFIG_MTD_REDBOOT_PARTS_READONLY=y
> +CONFIG_MTD_CMDLINE_PARTS=y
> +CONFIG_MTD_AFS_PARTS=y
> +CONFIG_MTD_AR7_PARTS=y
> +
> +#
> +# User Modules And Translation Layers
> +#
> +CONFIG_MTD_CHAR=y
> +CONFIG_HAVE_MTD_OTP=y
> +CONFIG_MTD_BLKDEVS=y
> +CONFIG_MTD_BLOCK=y
> +# CONFIG_FTL is not set
> +# CONFIG_NFTL is not set
> +# CONFIG_INFTL is not set
> +# CONFIG_RFD_FTL is not set
> +# CONFIG_SSFDC is not set
> +# CONFIG_SM_FTL is not set
> +# CONFIG_MTD_OOPS is not set
> +
> +#
> +# RAM/ROM/Flash chip drivers
> +#
> +CONFIG_MTD_CFI=y
> +CONFIG_MTD_JEDECPROBE=y
> +CONFIG_MTD_GEN_PROBE=y
> +CONFIG_MTD_CFI_ADV_OPTIONS=y
> +CONFIG_MTD_CFI_NOSWAP=y
> +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> +CONFIG_MTD_CFI_GEOMETRY=y
> +CONFIG_MTD_MAP_BANK_WIDTH_1=y
> +CONFIG_MTD_MAP_BANK_WIDTH_2=y
> +CONFIG_MTD_MAP_BANK_WIDTH_4=y
> +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> +CONFIG_MTD_CFI_I1=y
> +CONFIG_MTD_CFI_I2=y
> +# CONFIG_MTD_CFI_I4 is not set
> +# CONFIG_MTD_CFI_I8 is not set
> +CONFIG_MTD_OTP=y
> +CONFIG_MTD_CFI_INTELEXT=y
> +CONFIG_MTD_CFI_AMDSTD=y
> +CONFIG_MTD_CFI_STAA=y
> +CONFIG_MTD_CFI_UTIL=y
> +CONFIG_MTD_RAM=y
> +# CONFIG_MTD_ROM is not set
> +# CONFIG_MTD_ABSENT is not set
> +# CONFIG_MTD_XIP is not set
> +
> +#
> +# Mapping drivers for chip access
> +#
> +CONFIG_MTD_COMPLEX_MAPPINGS=y
> +CONFIG_MTD_PHYSMAP=y
> +# CONFIG_MTD_PHYSMAP_COMPAT is not set
> +CONFIG_MTD_PXA2XX=y
> +# CONFIG_MTD_ARM_INTEGRATOR is not set
> +# CONFIG_MTD_IMPA7 is not set
> +# CONFIG_MTD_PCI is not set
> +# CONFIG_MTD_PCMCIA is not set
> +# CONFIG_MTD_GPIO_ADDR is not set
> +# CONFIG_MTD_INTEL_VR_NOR is not set
> +# CONFIG_MTD_PLATRAM is not set
> +
> +#
> +# Self-contained MTD device drivers
> +#
> +# CONFIG_MTD_PMC551 is not set
> +# CONFIG_MTD_DATAFLASH is not set
> +# CONFIG_MTD_M25P80 is not set
> +# CONFIG_MTD_SST25L is not set
> +# CONFIG_MTD_SLRAM is not set
> +# CONFIG_MTD_PHRAM is not set
> +# CONFIG_MTD_MTDRAM is not set
> +CONFIG_MTD_BLOCK2MTD=y
> +
> +#
> +# Disk-On-Chip Device Drivers
> +#
> +CONFIG_MTD_DOC2000=y
> +CONFIG_MTD_DOC2001=y
> +CONFIG_MTD_DOC2001PLUS=y
> +CONFIG_MTD_DOCPROBE=y
> +CONFIG_MTD_DOCECC=y
> +CONFIG_MTD_DOCPROBE_ADVANCED=y
> +CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000
> +CONFIG_MTD_DOCPROBE_HIGH=y
> +# CONFIG_MTD_DOCPROBE_55AA is not set
> +CONFIG_MTD_NAND=y
> +CONFIG_MTD_NAND_ECC=y
> +# CONFIG_MTD_NAND_ECC_SMC is not set
> +# CONFIG_MTD_NAND_VERIFY_WRITE is not set
> +# CONFIG_MTD_SM_COMMON is not set
> +# CONFIG_MTD_NAND_MUSEUM_IDS is not set
> +# CONFIG_MTD_NAND_DENALI is not set
> +CONFIG_MTD_NAND_DENALI_SCRATCH_REG_ADDR=0xFF108018
> +# CONFIG_MTD_NAND_H1900 is not set
> +CONFIG_MTD_NAND_GPIO=m
> +CONFIG_MTD_NAND_IDS=y
> +# CONFIG_MTD_NAND_RICOH is not set
> +CONFIG_MTD_NAND_DISKONCHIP=y
> +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
> +CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
> +CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
> +CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
> +# CONFIG_MTD_NAND_SHARPSL is not set
> +# CONFIG_MTD_NAND_CAFE is not set
> +CONFIG_MTD_NAND_CM_X270=y
> +CONFIG_MTD_NAND_TMIO=m
> +# CONFIG_MTD_NAND_NANDSIM is not set
> +CONFIG_MTD_NAND_PLATFORM=y
> +# CONFIG_MTD_ALAUDA is not set
> +CONFIG_MTD_ONENAND=y
> +# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
> +# CONFIG_MTD_ONENAND_GENERIC is not set
> +# CONFIG_MTD_ONENAND_OTP is not set
> +# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
> +# CONFIG_MTD_ONENAND_SIM is not set
> +
> +#
> +# LPDDR flash memory drivers
> +#
> +# CONFIG_MTD_LPDDR is not set
> +
> +#
> +# UBI - Unsorted block images
> +#
> +# CONFIG_MTD_UBI is not set
> +# CONFIG_PARPORT is not set
> +# CONFIG_PNP is not set
> +CONFIG_BLK_DEV=y
> +# CONFIG_BLK_CPQ_DA is not set
> +# CONFIG_BLK_CPQ_CISS_DA is not set
> +# CONFIG_BLK_DEV_DAC960 is not set
> +# CONFIG_BLK_DEV_UMEM is not set
> +# CONFIG_BLK_DEV_COW_COMMON is not set
> +CONFIG_BLK_DEV_LOOP=m
> +CONFIG_BLK_DEV_CRYPTOLOOP=m
> +# CONFIG_BLK_DEV_DRBD is not set
> +CONFIG_BLK_DEV_NBD=y
> +# CONFIG_BLK_DEV_SX8 is not set
> +# CONFIG_BLK_DEV_UB is not set
> +CONFIG_BLK_DEV_RAM=y
> +CONFIG_BLK_DEV_RAM_COUNT=8
> +CONFIG_BLK_DEV_RAM_SIZE=4096
> +# CONFIG_BLK_DEV_XIP is not set
> +# CONFIG_CDROM_PKTCDVD is not set
> +# CONFIG_ATA_OVER_ETH is not set
> +# CONFIG_MG_DISK is not set
> +CONFIG_MISC_DEVICES=y
> +# CONFIG_AD525X_DPOT is not set
> +# CONFIG_PHANTOM is not set
> +# CONFIG_SGI_IOC4 is not set
> +# CONFIG_TIFM_CORE is not set
> +# CONFIG_ICS932S401 is not set
> +# CONFIG_ENCLOSURE_SERVICES is not set
> +# CONFIG_HP_ILO is not set
> +# CONFIG_ISL29003 is not set
> +# CONFIG_SENSORS_TSL2550 is not set
> +# CONFIG_DS1682 is not set
> +# CONFIG_TI_DAC7512 is not set
> +# CONFIG_C2PORT is not set
> +
> +#
> +# EEPROM support
> +#
> +CONFIG_EEPROM_AT24=m
> +# CONFIG_EEPROM_AT25 is not set
> +CONFIG_EEPROM_LEGACY=y
> +# CONFIG_EEPROM_MAX6875 is not set
> +# CONFIG_EEPROM_93CX6 is not set
> +# CONFIG_CB710_CORE is not set
> +# CONFIG_IWMC3200TOP is not set
> +CONFIG_HAVE_IDE=y
> +CONFIG_IDE=y
> +
> +#
> +# Please see Documentation/ide/ide.txt for help/info on IDE drives
> +#
> +# CONFIG_BLK_DEV_IDE_SATA is not set
> +CONFIG_IDE_GD=y
> +CONFIG_IDE_GD_ATA=y
> +# CONFIG_IDE_GD_ATAPI is not set
> +CONFIG_BLK_DEV_IDECS=m
> +# CONFIG_BLK_DEV_DELKIN is not set
> +# CONFIG_BLK_DEV_IDECD is not set
> +# CONFIG_BLK_DEV_IDETAPE is not set
> +# CONFIG_IDE_TASK_IOCTL is not set
> +CONFIG_IDE_PROC_FS=y
> +
> +#
> +# IDE chipset support/bugfixes
> +#
> +# CONFIG_BLK_DEV_PLATFORM is not set
> +
> +#
> +# PCI IDE chipsets support
> +#
> +# CONFIG_BLK_DEV_GENERIC is not set
> +# CONFIG_BLK_DEV_OPTI621 is not set
> +# CONFIG_BLK_DEV_AEC62XX is not set
> +# CONFIG_BLK_DEV_ALI15X3 is not set
> +# CONFIG_BLK_DEV_CMD64X is not set
> +# CONFIG_BLK_DEV_TRIFLEX is not set
> +# CONFIG_BLK_DEV_CS5520 is not set
> +# CONFIG_BLK_DEV_CS5530 is not set
> +# CONFIG_BLK_DEV_HPT366 is not set
> +# CONFIG_BLK_DEV_JMICRON is not set
> +# CONFIG_BLK_DEV_SC1200 is not set
> +# CONFIG_BLK_DEV_PIIX is not set
> +# CONFIG_BLK_DEV_IT8172 is not set
> +# CONFIG_BLK_DEV_IT8213 is not set
> +# CONFIG_BLK_DEV_IT821X is not set
> +# CONFIG_BLK_DEV_NS87415 is not set
> +# CONFIG_BLK_DEV_PDC202XX_OLD is not set
> +# CONFIG_BLK_DEV_PDC202XX_NEW is not set
> +# CONFIG_BLK_DEV_SVWKS is not set
> +# CONFIG_BLK_DEV_SIIMAGE is not set
> +# CONFIG_BLK_DEV_SL82C105 is not set
> +# CONFIG_BLK_DEV_SLC90E66 is not set
> +# CONFIG_BLK_DEV_TRM290 is not set
> +# CONFIG_BLK_DEV_VIA82CXXX is not set
> +# CONFIG_BLK_DEV_TC86C001 is not set
> +# CONFIG_BLK_DEV_IDEDMA is not set
> +
> +#
> +# SCSI device support
> +#
> +CONFIG_SCSI_MOD=m
> +# CONFIG_RAID_ATTRS is not set
> +CONFIG_SCSI=m
> +CONFIG_SCSI_DMA=y
> +# CONFIG_SCSI_TGT is not set
> +# CONFIG_SCSI_NETLINK is not set
> +CONFIG_SCSI_PROC_FS=y
> +
> +#
> +# SCSI support type (disk, tape, CD-ROM)
> +#
> +CONFIG_BLK_DEV_SD=m
> +# CONFIG_CHR_DEV_ST is not set
> +# CONFIG_CHR_DEV_OSST is not set
> +# CONFIG_BLK_DEV_SR is not set
> +CONFIG_CHR_DEV_SG=m
> +# CONFIG_CHR_DEV_SCH is not set
> +CONFIG_SCSI_MULTI_LUN=y
> +# CONFIG_SCSI_CONSTANTS is not set
> +# CONFIG_SCSI_LOGGING is not set
> +# CONFIG_SCSI_SCAN_ASYNC is not set
> +CONFIG_SCSI_WAIT_SCAN=m
> +
> +#
> +# SCSI Transports
> +#
> +# CONFIG_SCSI_SPI_ATTRS is not set
> +# CONFIG_SCSI_FC_ATTRS is not set
> +# CONFIG_SCSI_ISCSI_ATTRS is not set
> +# CONFIG_SCSI_SAS_ATTRS is not set
> +# CONFIG_SCSI_SAS_LIBSAS is not set
> +# CONFIG_SCSI_SRP_ATTRS is not set
> +CONFIG_SCSI_LOWLEVEL=y
> +# CONFIG_ISCSI_TCP is not set
> +# CONFIG_SCSI_CXGB3_ISCSI is not set
> +# CONFIG_SCSI_BNX2_ISCSI is not set
> +# CONFIG_BE2ISCSI is not set
> +# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
> +# CONFIG_SCSI_HPSA is not set
> +# CONFIG_SCSI_3W_9XXX is not set
> +# CONFIG_SCSI_3W_SAS is not set
> +# CONFIG_SCSI_ACARD is not set
> +# CONFIG_SCSI_AHA152X is not set
> +# CONFIG_SCSI_AACRAID is not set
> +# CONFIG_SCSI_AIC7XXX is not set
> +# CONFIG_SCSI_AIC7XXX_OLD is not set
> +# CONFIG_SCSI_AIC79XX is not set
> +# CONFIG_SCSI_AIC94XX is not set
> +# CONFIG_SCSI_MVSAS is not set
> +# CONFIG_SCSI_DPT_I2O is not set
> +# CONFIG_SCSI_ADVANSYS is not set
> +# CONFIG_SCSI_IN2000 is not set
> +# CONFIG_SCSI_ARCMSR is not set
> +# CONFIG_MEGARAID_NEWGEN is not set
> +# CONFIG_MEGARAID_LEGACY is not set
> +# CONFIG_MEGARAID_SAS is not set
> +# CONFIG_SCSI_MPT2SAS is not set
> +# CONFIG_SCSI_HPTIOP is not set
> +# CONFIG_LIBFC is not set
> +# CONFIG_LIBFCOE is not set
> +# CONFIG_FCOE is not set
> +# CONFIG_SCSI_DMX3191D is not set
> +# CONFIG_SCSI_DTC3280 is not set
> +# CONFIG_SCSI_FUTURE_DOMAIN is not set
> +# CONFIG_SCSI_GENERIC_NCR5380 is not set
> +# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
> +# CONFIG_SCSI_IPS is not set
> +# CONFIG_SCSI_INITIO is not set
> +# CONFIG_SCSI_INIA100 is not set
> +# CONFIG_SCSI_NCR53C406A is not set
> +# CONFIG_SCSI_STEX is not set
> +# CONFIG_SCSI_SYM53C8XX_2 is not set
> +# CONFIG_SCSI_IPR is not set
> +# CONFIG_SCSI_PAS16 is not set
> +# CONFIG_SCSI_QLOGIC_FAS is not set
> +# CONFIG_SCSI_QLOGIC_1280 is not set
> +# CONFIG_SCSI_QLA_FC is not set
> +# CONFIG_SCSI_QLA_ISCSI is not set
> +# CONFIG_SCSI_LPFC is not set
> +# CONFIG_SCSI_SYM53C416 is not set
> +# CONFIG_SCSI_DC395x is not set
> +# CONFIG_SCSI_DC390T is not set
> +# CONFIG_SCSI_T128 is not set
> +# CONFIG_SCSI_NSP32 is not set
> +# CONFIG_SCSI_DEBUG is not set
> +# CONFIG_SCSI_PMCRAID is not set
> +# CONFIG_SCSI_PM8001 is not set
> +# CONFIG_SCSI_SRP is not set
> +# CONFIG_SCSI_BFA_FC is not set
> +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
> +# CONFIG_SCSI_DH is not set
> +# CONFIG_SCSI_OSD_INITIATOR is not set
> +CONFIG_ATA=m
> +# CONFIG_ATA_NONSTANDARD is not set
> +CONFIG_ATA_VERBOSE_ERROR=y
> +CONFIG_SATA_PMP=y
> +
> +#
> +# Controllers with non-SFF native interface
> +#
> +# CONFIG_SATA_AHCI is not set
> +# CONFIG_SATA_AHCI_PLATFORM is not set
> +# CONFIG_SATA_INIC162X is not set
> +# CONFIG_SATA_SIL24 is not set
> +CONFIG_ATA_SFF=y
> +
> +#
> +# SFF controllers with custom DMA interface
> +#
> +# CONFIG_PDC_ADMA is not set
> +# CONFIG_SATA_QSTOR is not set
> +# CONFIG_SATA_SX4 is not set
> +CONFIG_ATA_BMDMA=y
> +
> +#
> +# SATA SFF controllers with BMDMA
> +#
> +# CONFIG_ATA_PIIX is not set
> +# CONFIG_SATA_MV is not set
> +# CONFIG_SATA_NV is not set
> +# CONFIG_SATA_PROMISE is not set
> +# CONFIG_SATA_SIL is not set
> +# CONFIG_SATA_SIS is not set
> +# CONFIG_SATA_SVW is not set
> +# CONFIG_SATA_ULI is not set
> +# CONFIG_SATA_VIA is not set
> +# CONFIG_SATA_VITESSE is not set
> +
> +#
> +# PATA SFF controllers with BMDMA
> +#
> +# CONFIG_PATA_ALI is not set
> +# CONFIG_PATA_AMD is not set
> +# CONFIG_PATA_ARTOP is not set
> +# CONFIG_PATA_ATIIXP is not set
> +# CONFIG_PATA_ATP867X is not set
> +# CONFIG_PATA_CMD64X is not set
> +# CONFIG_PATA_CS5520 is not set
> +# CONFIG_PATA_CS5530 is not set
> +# CONFIG_PATA_CYPRESS is not set
> +# CONFIG_PATA_EFAR is not set
> +# CONFIG_PATA_HPT366 is not set
> +# CONFIG_PATA_HPT37X is not set
> +# CONFIG_PATA_HPT3X2N is not set
> +# CONFIG_PATA_HPT3X3 is not set
> +# CONFIG_PATA_IT8213 is not set
> +# CONFIG_PATA_IT821X is not set
> +# CONFIG_PATA_JMICRON is not set
> +# CONFIG_PATA_MARVELL is not set
> +# CONFIG_PATA_NETCELL is not set
> +# CONFIG_PATA_NINJA32 is not set
> +# CONFIG_PATA_NS87415 is not set
> +# CONFIG_PATA_OLDPIIX is not set
> +# CONFIG_PATA_OPTIDMA is not set
> +# CONFIG_PATA_PDC2027X is not set
> +# CONFIG_PATA_PDC_OLD is not set
> +# CONFIG_PATA_RADISYS is not set
> +# CONFIG_PATA_RDC is not set
> +# CONFIG_PATA_SC1200 is not set
> +# CONFIG_PATA_SCH is not set
> +# CONFIG_PATA_SERVERWORKS is not set
> +# CONFIG_PATA_SIL680 is not set
> +# CONFIG_PATA_SIS is not set
> +# CONFIG_PATA_TOSHIBA is not set
> +# CONFIG_PATA_TRIFLEX is not set
> +# CONFIG_PATA_VIA is not set
> +# CONFIG_PATA_PXA is not set
> +# CONFIG_PATA_WINBOND is not set
> +
> +#
> +# PIO-only SFF controllers
> +#
> +# CONFIG_PATA_CMD640_PCI is not set
> +# CONFIG_PATA_MPIIX is not set
> +# CONFIG_PATA_NS87410 is not set
> +# CONFIG_PATA_OPTI is not set
> +# CONFIG_PATA_PALMLD is not set
> +CONFIG_PATA_PCMCIA=m
> +CONFIG_PATA_PLATFORM=m
> +# CONFIG_PATA_QDI is not set
> +# CONFIG_PATA_RZ1000 is not set
> +# CONFIG_PATA_WINBOND_VLB is not set
> +
> +#
> +# Generic fallback / legacy drivers
> +#
> +# CONFIG_ATA_GENERIC is not set
> +# CONFIG_PATA_LEGACY is not set
> +# CONFIG_MD is not set
> +# CONFIG_FUSION is not set
> +
> +#
> +# IEEE 1394 (FireWire) support
> +#
> +
> +#
> +# You can enable one or both FireWire driver stacks.
> +#
> +
> +#
> +# The newer stack is recommended.
> +#
> +# CONFIG_FIREWIRE is not set
> +# CONFIG_IEEE1394 is not set
> +# CONFIG_I2O is not set
> +CONFIG_NETDEVICES=y
> +CONFIG_DUMMY=y
> +# CONFIG_BONDING is not set
> +# CONFIG_MACVLAN is not set
> +# CONFIG_EQUALIZER is not set
> +# CONFIG_TUN is not set
> +# CONFIG_VETH is not set
> +# CONFIG_ARCNET is not set
> +CONFIG_PHYLIB=y
> +
> +#
> +# MII PHY device drivers
> +#
> +# CONFIG_MARVELL_PHY is not set
> +# CONFIG_DAVICOM_PHY is not set
> +# CONFIG_QSEMI_PHY is not set
> +# CONFIG_LXT_PHY is not set
> +# CONFIG_CICADA_PHY is not set
> +# CONFIG_VITESSE_PHY is not set
> +# CONFIG_SMSC_PHY is not set
> +# CONFIG_BROADCOM_PHY is not set
> +# CONFIG_ICPLUS_PHY is not set
> +# CONFIG_REALTEK_PHY is not set
> +# CONFIG_NATIONAL_PHY is not set
> +# CONFIG_STE10XP is not set
> +# CONFIG_LSI_ET1011C_PHY is not set
> +# CONFIG_MICREL_PHY is not set
> +# CONFIG_FIXED_PHY is not set
> +# CONFIG_MDIO_BITBANG is not set
> +CONFIG_NET_ETHERNET=y
> +CONFIG_MII=y
> +# CONFIG_AX88796 is not set
> +# CONFIG_HAPPYMEAL is not set
> +# CONFIG_SUNGEM is not set
> +# CONFIG_CASSINI is not set
> +# CONFIG_NET_VENDOR_3COM is not set
> +# CONFIG_NET_VENDOR_SMC is not set
> +CONFIG_SMC91X=y
> +CONFIG_DM9000=y
> +CONFIG_DM9000_DEBUGLEVEL=4
> +# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
> +# CONFIG_ENC28J60 is not set
> +# CONFIG_ETHOC is not set
> +# CONFIG_SMC911X is not set
> +# CONFIG_SMSC911X is not set
> +# CONFIG_NET_VENDOR_RACAL is not set
> +# CONFIG_DNET is not set
> +# CONFIG_NET_TULIP is not set
> +# CONFIG_AT1700 is not set
> +# CONFIG_DEPCA is not set
> +# CONFIG_HP100 is not set
> +# CONFIG_NET_ISA is not set
> +# CONFIG_IBM_NEW_EMAC_ZMII is not set
> +# CONFIG_IBM_NEW_EMAC_RGMII is not set
> +# CONFIG_IBM_NEW_EMAC_TAH is not set
> +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
> +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
> +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
> +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
> +CONFIG_NET_PCI=y
> +# CONFIG_PCNET32 is not set
> +# CONFIG_AMD8111_ETH is not set
> +# CONFIG_ADAPTEC_STARFIRE is not set
> +# CONFIG_AC3200 is not set
> +# CONFIG_KSZ884X_PCI is not set
> +# CONFIG_APRICOT is not set
> +# CONFIG_B44 is not set
> +# CONFIG_FORCEDETH is not set
> +# CONFIG_CS89x0 is not set
> +# CONFIG_E100 is not set
> +# CONFIG_FEALNX is not set
> +# CONFIG_NATSEMI is not set
> +# CONFIG_NE2K_PCI is not set
> +# CONFIG_8139CP is not set
> +CONFIG_8139TOO=m
> +CONFIG_8139TOO_PIO=y
> +# CONFIG_8139TOO_TUNE_TWISTER is not set
> +# CONFIG_8139TOO_8129 is not set
> +# CONFIG_8139_OLD_RX_RESET is not set
> +# CONFIG_R6040 is not set
> +# CONFIG_SIS900 is not set
> +# CONFIG_EPIC100 is not set
> +# CONFIG_SMSC9420 is not set
> +# CONFIG_SUNDANCE is not set
> +# CONFIG_TLAN is not set
> +# CONFIG_KS8842 is not set
> +# CONFIG_KS8851 is not set
> +# CONFIG_KS8851_MLL is not set
> +# CONFIG_VIA_RHINE is not set
> +# CONFIG_SC92031 is not set
> +# CONFIG_ATL2 is not set
> +CONFIG_NETDEV_1000=y
> +# CONFIG_ACENIC is not set
> +# CONFIG_DL2K is not set
> +# CONFIG_E1000 is not set
> +# CONFIG_E1000E is not set
> +# CONFIG_IP1000 is not set
> +# CONFIG_IGB is not set
> +# CONFIG_IGBVF is not set
> +# CONFIG_NS83820 is not set
> +# CONFIG_HAMACHI is not set
> +# CONFIG_YELLOWFIN is not set
> +# CONFIG_R8169 is not set
> +# CONFIG_SIS190 is not set
> +# CONFIG_SKGE is not set
> +# CONFIG_SKY2 is not set
> +# CONFIG_VIA_VELOCITY is not set
> +# CONFIG_TIGON3 is not set
> +# CONFIG_BNX2 is not set
> +# CONFIG_CNIC is not set
> +# CONFIG_QLA3XXX is not set
> +# CONFIG_ATL1 is not set
> +# CONFIG_ATL1E is not set
> +# CONFIG_ATL1C is not set
> +# CONFIG_JME is not set
> +CONFIG_NETDEV_10000=y
> +# CONFIG_CHELSIO_T1 is not set
> +CONFIG_CHELSIO_T3_DEPENDS=y
> +# CONFIG_CHELSIO_T3 is not set
> +CONFIG_CHELSIO_T4_DEPENDS=y
> +# CONFIG_CHELSIO_T4 is not set
> +# CONFIG_ENIC is not set
> +# CONFIG_IXGBE is not set
> +# CONFIG_IXGB is not set
> +# CONFIG_S2IO is not set
> +# CONFIG_VXGE is not set
> +# CONFIG_MYRI10GE is not set
> +# CONFIG_NETXEN_NIC is not set
> +# CONFIG_NIU is not set
> +# CONFIG_MLX4_EN is not set
> +# CONFIG_MLX4_CORE is not set
> +# CONFIG_TEHUTI is not set
> +# CONFIG_BNX2X is not set
> +# CONFIG_QLCNIC is not set
> +# CONFIG_QLGE is not set
> +# CONFIG_SFC is not set
> +# CONFIG_BE2NET is not set
> +# CONFIG_TR is not set
> +CONFIG_WLAN=y
> +# CONFIG_PCMCIA_RAYCS is not set
> +# CONFIG_LIBERTAS_THINFIRM is not set
> +# CONFIG_ATMEL is not set
> +# CONFIG_AT76C50X_USB is not set
> +# CONFIG_AIRO_CS is not set
> +# CONFIG_PCMCIA_WL3501 is not set
> +# CONFIG_PRISM54 is not set
> +# CONFIG_USB_ZD1201 is not set
> +# CONFIG_USB_NET_RNDIS_WLAN is not set
> +# CONFIG_RTL8180 is not set
> +# CONFIG_RTL8187 is not set
> +# CONFIG_ADM8211 is not set
> +# CONFIG_MAC80211_HWSIM is not set
> +# CONFIG_MWL8K is not set
> +# CONFIG_ATH_COMMON is not set
> +# CONFIG_B43 is not set
> +# CONFIG_B43LEGACY is not set
> +CONFIG_HOSTAP=y
> +CONFIG_HOSTAP_FIRMWARE=y
> +CONFIG_HOSTAP_FIRMWARE_NVRAM=y
> +# CONFIG_HOSTAP_PLX is not set
> +# CONFIG_HOSTAP_PCI is not set
> +CONFIG_HOSTAP_CS=m
> +# CONFIG_IPW2100 is not set
> +# CONFIG_IPW2200 is not set
> +# CONFIG_IWLWIFI is not set
> +# CONFIG_IWM is not set
> +CONFIG_LIBERTAS=m
> +# CONFIG_LIBERTAS_USB is not set
> +# CONFIG_LIBERTAS_CS is not set
> +CONFIG_LIBERTAS_SDIO=m
> +# CONFIG_LIBERTAS_SPI is not set
> +# CONFIG_LIBERTAS_DEBUG is not set
> +# CONFIG_LIBERTAS_MESH is not set
> +CONFIG_HERMES=m
> +# CONFIG_HERMES_PRISM is not set
> +CONFIG_HERMES_CACHE_FW_ON_INIT=y
> +# CONFIG_PLX_HERMES is not set
> +# CONFIG_TMD_HERMES is not set
> +# CONFIG_NORTEL_HERMES is not set
> +CONFIG_PCMCIA_HERMES=m
> +CONFIG_PCMCIA_SPECTRUM=m
> +# CONFIG_ORINOCO_USB is not set
> +# CONFIG_P54_COMMON is not set
> +CONFIG_RT2X00=m
> +# CONFIG_RT2400PCI is not set
> +# CONFIG_RT2500PCI is not set
> +# CONFIG_RT61PCI is not set
> +CONFIG_RT2800PCI_PCI=y
> +# CONFIG_RT2800PCI is not set
> +# CONFIG_RT2500USB is not set
> +CONFIG_RT73USB=m
> +# CONFIG_RT2800USB is not set
> +CONFIG_RT2X00_LIB_USB=m
> +CONFIG_RT2X00_LIB=m
> +CONFIG_RT2X00_LIB_FIRMWARE=y
> +CONFIG_RT2X00_LIB_CRYPTO=y
> +CONFIG_RT2X00_LIB_LEDS=y
> +# CONFIG_RT2X00_DEBUG is not set
> +# CONFIG_WL12XX is not set
> +# CONFIG_ZD1211RW is not set
> +
> +#
> +# Enable WiMAX (Networking options) to see the WiMAX drivers
> +#
> +
> +#
> +# USB Network Adapters
> +#
> +# CONFIG_USB_CATC is not set
> +# CONFIG_USB_KAWETH is not set
> +CONFIG_USB_PEGASUS=m
> +# CONFIG_USB_RTL8150 is not set
> +CONFIG_USB_USBNET=m
> +CONFIG_USB_NET_AX8817X=m
> +CONFIG_USB_NET_CDCETHER=m
> +# CONFIG_USB_NET_CDC_EEM is not set
> +# CONFIG_USB_NET_DM9601 is not set
> +# CONFIG_USB_NET_SMSC75XX is not set
> +# CONFIG_USB_NET_SMSC95XX is not set
> +# CONFIG_USB_NET_GL620A is not set
> +CONFIG_USB_NET_NET1080=m
> +# CONFIG_USB_NET_PLUSB is not set
> +# CONFIG_USB_NET_MCS7830 is not set
> +# CONFIG_USB_NET_RNDIS_HOST is not set
> +CONFIG_USB_NET_CDC_SUBSET=m
> +# CONFIG_USB_ALI_M5632 is not set
> +# CONFIG_USB_AN2720 is not set
> +CONFIG_USB_BELKIN=y
> +CONFIG_USB_ARMLINUX=y
> +# CONFIG_USB_EPSON2888 is not set
> +# CONFIG_USB_KC2190 is not set
> +CONFIG_USB_NET_ZAURUS=m
> +# CONFIG_USB_NET_INT51X1 is not set
> +# CONFIG_USB_IPHETH is not set
> +# CONFIG_USB_SIERRA_NET is not set
> +CONFIG_NET_PCMCIA=y
> +# CONFIG_PCMCIA_3C589 is not set
> +# CONFIG_PCMCIA_3C574 is not set
> +# CONFIG_PCMCIA_FMVJ18X is not set
> +CONFIG_PCMCIA_PCNET=m
> +# CONFIG_PCMCIA_NMCLAN is not set
> +# CONFIG_PCMCIA_SMC91C92 is not set
> +# CONFIG_PCMCIA_XIRC2PS is not set
> +# CONFIG_PCMCIA_AXNET is not set
> +# CONFIG_WAN is not set
> +CONFIG_IEEE802154_DRIVERS=y
> +# CONFIG_IEEE802154_FAKEHARD is not set
> +# CONFIG_FDDI is not set
> +# CONFIG_HIPPI is not set
> +CONFIG_PPP=m
> +CONFIG_PPP_MULTILINK=y
> +CONFIG_PPP_FILTER=y
> +CONFIG_PPP_ASYNC=m
> +CONFIG_PPP_SYNC_TTY=m
> +CONFIG_PPP_DEFLATE=m
> +CONFIG_PPP_BSDCOMP=m
> +CONFIG_PPP_MPPE=m
> +# CONFIG_PPPOE is not set
> +# CONFIG_SLIP is not set
> +CONFIG_SLHC=m
> +# CONFIG_NET_FC is not set
> +# CONFIG_NETCONSOLE is not set
> +# CONFIG_NETPOLL is not set
> +# CONFIG_NET_POLL_CONTROLLER is not set
> +# CONFIG_VMXNET3 is not set
> +# CONFIG_ISDN is not set
> +# CONFIG_PHONE is not set
> +
> +#
> +# Input device support
> +#
> +CONFIG_INPUT=y
> +# CONFIG_INPUT_FF_MEMLESS is not set
> +# CONFIG_INPUT_POLLDEV is not set
> +# CONFIG_INPUT_SPARSEKMAP is not set
> +
> +#
> +# Userland interfaces
> +#
> +CONFIG_INPUT_MOUSEDEV=y
> +CONFIG_INPUT_MOUSEDEV_PSAUX=y
> +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> +# CONFIG_INPUT_JOYDEV is not set
> +CONFIG_INPUT_EVDEV=m
> +# CONFIG_INPUT_EVBUG is not set
> +CONFIG_INPUT_APMPOWER=y
> +
> +#
> +# Input Device Drivers
> +#
> +CONFIG_INPUT_KEYBOARD=y
> +# CONFIG_KEYBOARD_ADP5588 is not set
> +CONFIG_KEYBOARD_ATKBD=m
> +# CONFIG_QT2160 is not set
> +# CONFIG_KEYBOARD_LKKBD is not set
> +CONFIG_KEYBOARD_GPIO=y
> +# CONFIG_KEYBOARD_TCA6416 is not set
> +# CONFIG_KEYBOARD_MATRIX is not set
> +# CONFIG_KEYBOARD_LM8323 is not set
> +# CONFIG_KEYBOARD_MAX7359 is not set
> +# CONFIG_KEYBOARD_NEWTON is not set
> +# CONFIG_KEYBOARD_OPENCORES is not set
> +CONFIG_KEYBOARD_PXA27x=y
> +# CONFIG_KEYBOARD_STOWAWAY is not set
> +# CONFIG_KEYBOARD_SUNKBD is not set
> +# CONFIG_KEYBOARD_XTKBD is not set
> +CONFIG_INPUT_MOUSE=y
> +CONFIG_MOUSE_PS2=y
> +CONFIG_MOUSE_PS2_ALPS=y
> +CONFIG_MOUSE_PS2_LOGIPS2PP=y
> +CONFIG_MOUSE_PS2_SYNAPTICS=y
> +CONFIG_MOUSE_PS2_TRACKPOINT=y
> +# CONFIG_MOUSE_PS2_ELANTECH is not set
> +# CONFIG_MOUSE_PS2_SENTELIC is not set
> +# CONFIG_MOUSE_PS2_TOUCHKIT is not set
> +CONFIG_MOUSE_SERIAL=m
> +# CONFIG_MOUSE_APPLETOUCH is not set
> +# CONFIG_MOUSE_BCM5974 is not set
> +# CONFIG_MOUSE_INPORT is not set
> +# CONFIG_MOUSE_LOGIBM is not set
> +# CONFIG_MOUSE_PC110PAD is not set
> +# CONFIG_MOUSE_VSXXXAA is not set
> +# CONFIG_MOUSE_GPIO is not set
> +# CONFIG_MOUSE_SYNAPTICS_I2C is not set
> +# CONFIG_INPUT_JOYSTICK is not set
> +# CONFIG_INPUT_TABLET is not set
> +CONFIG_INPUT_TOUCHSCREEN=y
> +# CONFIG_TOUCHSCREEN_ADS7846 is not set
> +# CONFIG_TOUCHSCREEN_AD7877 is not set
> +# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
> +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
> +# CONFIG_TOUCHSCREEN_AD7879 is not set
> +CONFIG_TOUCHSCREEN_DA9034=y
> +# CONFIG_TOUCHSCREEN_DYNAPRO is not set
> +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
> +# CONFIG_TOUCHSCREEN_EETI is not set
> +CONFIG_TOUCHSCREEN_FUJITSU=m
> +# CONFIG_TOUCHSCREEN_GUNZE is not set
> +CONFIG_TOUCHSCREEN_ELO=m
> +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
> +# CONFIG_TOUCHSCREEN_MCS5000 is not set
> +CONFIG_TOUCHSCREEN_MTOUCH=m
> +CONFIG_TOUCHSCREEN_INEXIO=m
> +# CONFIG_TOUCHSCREEN_MK712 is not set
> +CONFIG_TOUCHSCREEN_HTCPEN=m
> +CONFIG_TOUCHSCREEN_PENMOUNT=m
> +CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
> +CONFIG_TOUCHSCREEN_TOUCHWIN=m
> +CONFIG_TOUCHSCREEN_UCB1400=m
> +CONFIG_TOUCHSCREEN_WM97XX=m
> +CONFIG_TOUCHSCREEN_WM9705=y
> +CONFIG_TOUCHSCREEN_WM9712=y
> +CONFIG_TOUCHSCREEN_WM9713=y
> +# CONFIG_TOUCHSCREEN_WM97XX_MAINSTONE is not set
> +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
> +CONFIG_TOUCHSCREEN_TOUCHIT213=m
> +# CONFIG_TOUCHSCREEN_TSC2007 is not set
> +# CONFIG_TOUCHSCREEN_W90X900 is not set
> +CONFIG_TOUCHSCREEN_PCAP=y
> +# CONFIG_TOUCHSCREEN_TPS6507X is not set
> +CONFIG_INPUT_MISC=y
> +# CONFIG_INPUT_AD714X is not set
> +# CONFIG_INPUT_ATI_REMOTE is not set
> +# CONFIG_INPUT_ATI_REMOTE2 is not set
> +# CONFIG_INPUT_KEYSPAN_REMOTE is not set
> +# CONFIG_INPUT_POWERMATE is not set
> +# CONFIG_INPUT_YEALINK is not set
> +# CONFIG_INPUT_CM109 is not set
> +CONFIG_INPUT_UINPUT=m
> +# CONFIG_INPUT_PCF8574 is not set
> +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
> +CONFIG_INPUT_PCAP=y
> +
> +#
> +# Hardware I/O ports
> +#
> +CONFIG_SERIO=y
> +CONFIG_SERIO_SERPORT=y
> +CONFIG_SERIO_SA1111=m
> +# CONFIG_SERIO_PCIPS2 is not set
> +CONFIG_SERIO_LIBPS2=y
> +# CONFIG_SERIO_RAW is not set
> +# CONFIG_SERIO_ALTERA_PS2 is not set
> +# CONFIG_GAMEPORT is not set
> +
> +#
> +# Character devices
> +#
> +CONFIG_VT=y
> +CONFIG_CONSOLE_TRANSLATIONS=y
> +CONFIG_VT_CONSOLE=y
> +CONFIG_HW_CONSOLE=y
> +# CONFIG_VT_HW_CONSOLE_BINDING is not set
> +CONFIG_DEVKMEM=y
> +# CONFIG_SERIAL_NONSTANDARD is not set
> +# CONFIG_N_GSM is not set
> +# CONFIG_NOZOMI is not set
> +
> +#
> +# Serial drivers
> +#
> +CONFIG_SERIAL_8250=y
> +CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_8250_PCI=y
> +# CONFIG_SERIAL_8250_CS is not set
> +CONFIG_SERIAL_8250_NR_UARTS=7
> +CONFIG_SERIAL_8250_RUNTIME_UARTS=7
> +# CONFIG_SERIAL_8250_EXTENDED is not set
> +
> +#
> +# Non-8250 serial port support
> +#
> +# CONFIG_SERIAL_MAX3100 is not set
> +CONFIG_SERIAL_PXA=y
> +CONFIG_SERIAL_PXA_CONSOLE=y
> +CONFIG_SERIAL_CORE=y
> +CONFIG_SERIAL_CORE_CONSOLE=y
> +# CONFIG_SERIAL_JSM is not set
> +# CONFIG_SERIAL_TIMBERDALE is not set
> +# CONFIG_SERIAL_ALTERA_JTAGUART is not set
> +# CONFIG_SERIAL_ALTERA_UART is not set
> +CONFIG_UNIX98_PTYS=y
> +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
> +CONFIG_LEGACY_PTYS=y
> +CONFIG_LEGACY_PTY_COUNT=256
> +# CONFIG_IPMI_HANDLER is not set
> +CONFIG_HW_RANDOM=m
> +# CONFIG_HW_RANDOM_TIMERIOMEM is not set
> +# CONFIG_DTLK is not set
> +# CONFIG_R3964 is not set
> +# CONFIG_APPLICOM is not set
> +
> +#
> +# PCMCIA character devices
> +#
> +# CONFIG_SYNCLINK_CS is not set
> +# CONFIG_CARDMAN_4000 is not set
> +# CONFIG_CARDMAN_4040 is not set
> +# CONFIG_IPWIRELESS is not set
> +# CONFIG_RAW_DRIVER is not set
> +# CONFIG_TCG_TPM is not set
> +CONFIG_DEVPORT=y
> +# CONFIG_RAMOOPS is not set
> +CONFIG_I2C=y
> +CONFIG_I2C_BOARDINFO=y
> +CONFIG_I2C_COMPAT=y
> +CONFIG_I2C_CHARDEV=y
> +CONFIG_I2C_HELPER_AUTO=y
> +CONFIG_I2C_ALGOBIT=y
> +
> +#
> +# I2C Hardware Bus support
> +#
> +
> +#
> +# PC SMBus host controller drivers
> +#
> +# CONFIG_I2C_ALI1535 is not set
> +# CONFIG_I2C_ALI1563 is not set
> +# CONFIG_I2C_ALI15X3 is not set
> +# CONFIG_I2C_AMD756 is not set
> +# CONFIG_I2C_AMD8111 is not set
> +# CONFIG_I2C_I801 is not set
> +# CONFIG_I2C_ISCH is not set
> +# CONFIG_I2C_PIIX4 is not set
> +# CONFIG_I2C_NFORCE2 is not set
> +# CONFIG_I2C_SIS5595 is not set
> +# CONFIG_I2C_SIS630 is not set
> +# CONFIG_I2C_SIS96X is not set
> +# CONFIG_I2C_VIA is not set
> +# CONFIG_I2C_VIAPRO is not set
> +
> +#
> +# I2C system bus drivers (mostly embedded / system-on-chip)
> +#
> +# CONFIG_I2C_DESIGNWARE is not set
> +CONFIG_I2C_GPIO=y
> +# CONFIG_I2C_OCORES is not set
> +CONFIG_I2C_PXA=y
> +CONFIG_I2C_PXA_SLAVE=y
> +# CONFIG_I2C_SIMTEC is not set
> +# CONFIG_I2C_XILINX is not set
> +
> +#
> +# External I2C/SMBus adapter drivers
> +#
> +# CONFIG_I2C_PARPORT_LIGHT is not set
> +# CONFIG_I2C_TAOS_EVM is not set
> +# CONFIG_I2C_TINY_USB is not set
> +
> +#
> +# Other I2C/SMBus bus drivers
> +#
> +# CONFIG_I2C_ELEKTOR is not set
> +# CONFIG_I2C_PCA_ISA is not set
> +# CONFIG_I2C_PCA_PLATFORM is not set
> +# CONFIG_I2C_STUB is not set
> +# CONFIG_I2C_DEBUG_CORE is not set
> +# CONFIG_I2C_DEBUG_ALGO is not set
> +# CONFIG_I2C_DEBUG_BUS is not set
> +CONFIG_SPI=y
> +# CONFIG_SPI_DEBUG is not set
> +CONFIG_SPI_MASTER=y
> +
> +#
> +# SPI Master Controller Drivers
> +#
> +# CONFIG_SPI_BITBANG is not set
> +# CONFIG_SPI_GPIO is not set
> +CONFIG_SPI_PXA2XX=y
> +# CONFIG_SPI_XILINX is not set
> +# CONFIG_SPI_DESIGNWARE is not set
> +
> +#
> +# SPI Protocol Masters
> +#
> +CONFIG_SPI_SPIDEV=y
> +# CONFIG_SPI_TLE62X0 is not set
> +
> +#
> +# PPS support
> +#
> +# CONFIG_PPS is not set
> +CONFIG_ARCH_REQUIRE_GPIOLIB=y
> +CONFIG_GPIOLIB=y
> +# CONFIG_DEBUG_GPIO is not set
> +CONFIG_GPIO_SYSFS=y
> +
> +#
> +# Memory mapped GPIO expanders:
> +#
> +# CONFIG_GPIO_IT8761E is not set
> +# CONFIG_GPIO_SCH is not set
> +
> +#
> +# I2C GPIO expanders:
> +#
> +# CONFIG_GPIO_MAX7300 is not set
> +# CONFIG_GPIO_MAX732X is not set
> +CONFIG_GPIO_PCA953X=y
> +# CONFIG_GPIO_PCA953X_IRQ is not set
> +# CONFIG_GPIO_PCF857X is not set
> +# CONFIG_GPIO_ADP5588 is not set
> +
> +#
> +# PCI GPIO expanders:
> +#
> +# CONFIG_GPIO_CS5535 is not set
> +# CONFIG_GPIO_BT8XX is not set
> +# CONFIG_GPIO_LANGWELL is not set
> +# CONFIG_GPIO_RDC321X is not set
> +
> +#
> +# SPI GPIO expanders:
> +#
> +# CONFIG_GPIO_MAX7301 is not set
> +# CONFIG_GPIO_MCP23S08 is not set
> +# CONFIG_GPIO_MC33880 is not set
> +
> +#
> +# AC97 GPIO expanders:
> +#
> +# CONFIG_GPIO_UCB1400 is not set
> +
> +#
> +# MODULbus GPIO expanders:
> +#
> +CONFIG_W1=y
> +CONFIG_W1_CON=y
> +
> +#
> +# 1-wire Bus Masters
> +#
> +# CONFIG_W1_MASTER_MATROX is not set
> +# CONFIG_W1_MASTER_DS2490 is not set
> +# CONFIG_W1_MASTER_DS2482 is not set
> +CONFIG_W1_MASTER_DS1WM=y
> +# CONFIG_W1_MASTER_GPIO is not set
> +
> +#
> +# 1-wire Slaves
> +#
> +# CONFIG_W1_SLAVE_THERM is not set
> +# CONFIG_W1_SLAVE_SMEM is not set
> +# CONFIG_W1_SLAVE_DS2431 is not set
> +# CONFIG_W1_SLAVE_DS2433 is not set
> +CONFIG_W1_SLAVE_DS2760=y
> +# CONFIG_W1_SLAVE_BQ27000 is not set
> +CONFIG_POWER_SUPPLY=y
> +# CONFIG_POWER_SUPPLY_DEBUG is not set
> +CONFIG_PDA_POWER=y
> +# CONFIG_APM_POWER is not set
> +# CONFIG_TEST_POWER is not set
> +CONFIG_BATTERY_DS2760=y
> +# CONFIG_BATTERY_DS2782 is not set
> +# CONFIG_BATTERY_BQ27x00 is not set
> +CONFIG_BATTERY_DA9030=y
> +# CONFIG_BATTERY_MAX17040 is not set
> +CONFIG_HWMON=y
> +# CONFIG_HWMON_VID is not set
> +# CONFIG_HWMON_DEBUG_CHIP is not set
> +
> +#
> +# Native drivers
> +#
> +# CONFIG_SENSORS_AD7414 is not set
> +# CONFIG_SENSORS_AD7418 is not set
> +# CONFIG_SENSORS_ADCXX is not set
> +CONFIG_SENSORS_ADM1021=m
> +# CONFIG_SENSORS_ADM1025 is not set
> +# CONFIG_SENSORS_ADM1026 is not set
> +# CONFIG_SENSORS_ADM1029 is not set
> +# CONFIG_SENSORS_ADM1031 is not set
> +# CONFIG_SENSORS_ADM9240 is not set
> +# CONFIG_SENSORS_ADT7411 is not set
> +# CONFIG_SENSORS_ADT7462 is not set
> +# CONFIG_SENSORS_ADT7470 is not set
> +# CONFIG_SENSORS_ADT7475 is not set
> +# CONFIG_SENSORS_ASC7621 is not set
> +# CONFIG_SENSORS_ATXP1 is not set
> +# CONFIG_SENSORS_DS1621 is not set
> +# CONFIG_SENSORS_I5K_AMB is not set
> +# CONFIG_SENSORS_F71805F is not set
> +# CONFIG_SENSORS_F71882FG is not set
> +# CONFIG_SENSORS_F75375S is not set
> +# CONFIG_SENSORS_G760A is not set
> +# CONFIG_SENSORS_GL518SM is not set
> +# CONFIG_SENSORS_GL520SM is not set
> +# CONFIG_SENSORS_IT87 is not set
> +# CONFIG_SENSORS_LM63 is not set
> +# CONFIG_SENSORS_LM70 is not set
> +# CONFIG_SENSORS_LM73 is not set
> +CONFIG_SENSORS_LM75=m
> +# CONFIG_SENSORS_LM77 is not set
> +# CONFIG_SENSORS_LM78 is not set
> +# CONFIG_SENSORS_LM80 is not set
> +# CONFIG_SENSORS_LM83 is not set
> +# CONFIG_SENSORS_LM85 is not set
> +# CONFIG_SENSORS_LM87 is not set
> +# CONFIG_SENSORS_LM90 is not set
> +# CONFIG_SENSORS_LM92 is not set
> +# CONFIG_SENSORS_LM93 is not set
> +# CONFIG_SENSORS_LTC4215 is not set
> +# CONFIG_SENSORS_LTC4245 is not set
> +# CONFIG_SENSORS_LM95241 is not set
> +# CONFIG_SENSORS_MAX1111 is not set
> +# CONFIG_SENSORS_MAX1619 is not set
> +CONFIG_SENSORS_MAX6650=m
> +# CONFIG_SENSORS_PC87360 is not set
> +# CONFIG_SENSORS_PC87427 is not set
> +# CONFIG_SENSORS_PCF8591 is not set
> +# CONFIG_SENSORS_SHT15 is not set
> +# CONFIG_SENSORS_SIS5595 is not set
> +# CONFIG_SENSORS_DME1737 is not set
> +# CONFIG_SENSORS_EMC1403 is not set
> +# CONFIG_SENSORS_SMSC47M1 is not set
> +# CONFIG_SENSORS_SMSC47M192 is not set
> +# CONFIG_SENSORS_SMSC47B397 is not set
> +# CONFIG_SENSORS_ADS7828 is not set
> +# CONFIG_SENSORS_ADS7871 is not set
> +# CONFIG_SENSORS_AMC6821 is not set
> +# CONFIG_SENSORS_THMC50 is not set
> +# CONFIG_SENSORS_TMP102 is not set
> +# CONFIG_SENSORS_TMP401 is not set
> +# CONFIG_SENSORS_TMP421 is not set
> +# CONFIG_SENSORS_VIA686A is not set
> +# CONFIG_SENSORS_VT1211 is not set
> +# CONFIG_SENSORS_VT8231 is not set
> +# CONFIG_SENSORS_W83781D is not set
> +# CONFIG_SENSORS_W83791D is not set
> +# CONFIG_SENSORS_W83792D is not set
> +# CONFIG_SENSORS_W83793 is not set
> +# CONFIG_SENSORS_W83L785TS is not set
> +# CONFIG_SENSORS_W83L786NG is not set
> +# CONFIG_SENSORS_W83627HF is not set
> +# CONFIG_SENSORS_W83627EHF is not set
> +# CONFIG_SENSORS_LIS3_SPI is not set
> +# CONFIG_SENSORS_LIS3_I2C is not set
> +# CONFIG_THERMAL is not set
> +CONFIG_WATCHDOG=y
> +# CONFIG_WATCHDOG_NOWAYOUT is not set
> +
> +#
> +# Watchdog Device Drivers
> +#
> +# CONFIG_SOFT_WATCHDOG is not set
> +CONFIG_SA1100_WATCHDOG=y
> +# CONFIG_MAX63XX_WATCHDOG is not set
> +# CONFIG_ALIM7101_WDT is not set
> +
> +#
> +# ISA-based Watchdog Cards
> +#
> +# CONFIG_PCWATCHDOG is not set
> +# CONFIG_MIXCOMWD is not set
> +# CONFIG_WDT is not set
> +
> +#
> +# PCI-based Watchdog Cards
> +#
> +# CONFIG_PCIPCWATCHDOG is not set
> +# CONFIG_WDTPCI is not set
> +
> +#
> +# USB-based Watchdog Cards
> +#
> +# CONFIG_USBPCWATCHDOG is not set
> +CONFIG_SSB_POSSIBLE=y
> +
> +#
> +# Sonics Silicon Backplane
> +#
> +# CONFIG_SSB is not set
> +CONFIG_MFD_SUPPORT=y
> +CONFIG_MFD_CORE=y
> +# CONFIG_MFD_88PM860X is not set
> +# CONFIG_MFD_SM501 is not set
> +CONFIG_MFD_ASIC3=y
> +CONFIG_HTC_EGPIO=y
> +CONFIG_HTC_PASIC3=y
> +# CONFIG_HTC_I2CPLD is not set
> +CONFIG_UCB1400_CORE=m
> +# CONFIG_TPS65010 is not set
> +# CONFIG_TPS6507X is not set
> +# CONFIG_TWL4030_CORE is not set
> +# CONFIG_MFD_TC35892 is not set
> +CONFIG_MFD_TMIO=y
> +CONFIG_MFD_T7L66XB=y
> +CONFIG_MFD_TC6387XB=y
> +CONFIG_MFD_TC6393XB=y
> +CONFIG_PMIC_DA903X=y
> +# CONFIG_PMIC_ADP5520 is not set
> +# CONFIG_MFD_MAX8925 is not set
> +# CONFIG_MFD_WM8400 is not set
> +# CONFIG_MFD_WM831X is not set
> +# CONFIG_MFD_WM8350_I2C is not set
> +# CONFIG_MFD_WM8994 is not set
> +# CONFIG_MFD_PCF50633 is not set
> +# CONFIG_MFD_MC13783 is not set
> +# CONFIG_ABX500_CORE is not set
> +CONFIG_EZX_PCAP=y
> +# CONFIG_AB8500_CORE is not set
> +# CONFIG_MFD_TIMBERDALE is not set
> +# CONFIG_LPC_SCH is not set
> +# CONFIG_MFD_RDC321X is not set
> +# CONFIG_MFD_JANZ_CMODIO is not set
> +CONFIG_REGULATOR=y
> +CONFIG_REGULATOR_DEBUG=y
> +# CONFIG_REGULATOR_DUMMY is not set
> +# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
> +CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
> +CONFIG_REGULATOR_USERSPACE_CONSUMER=y
> +CONFIG_REGULATOR_BQ24022=y
> +# CONFIG_REGULATOR_MAX1586 is not set
> +# CONFIG_REGULATOR_MAX8649 is not set
> +# CONFIG_REGULATOR_MAX8660 is not set
> +CONFIG_REGULATOR_DA903X=y
> +# CONFIG_REGULATOR_LP3971 is not set
> +CONFIG_REGULATOR_PCAP=y
> +# CONFIG_REGULATOR_TPS65023 is not set
> +# CONFIG_REGULATOR_TPS6507X is not set
> +CONFIG_MEDIA_SUPPORT=y
> +
> +#
> +# Multimedia core support
> +#
> +CONFIG_VIDEO_DEV=y
> +CONFIG_VIDEO_V4L2_COMMON=y
> +CONFIG_VIDEO_ALLOW_V4L1=y
> +CONFIG_VIDEO_V4L1_COMPAT=y
> +# CONFIG_DVB_CORE is not set
> +CONFIG_VIDEO_MEDIA=y
> +
> +#
> +# Multimedia drivers
> +#
> +CONFIG_IR_CORE=y
> +CONFIG_VIDEO_IR=y
> +CONFIG_RC_MAP=y
> +CONFIG_IR_NEC_DECODER=y
> +CONFIG_IR_RC5_DECODER=y
> +CONFIG_IR_RC6_DECODER=y
> +CONFIG_IR_JVC_DECODER=y
> +CONFIG_IR_SONY_DECODER=y
> +# CONFIG_IR_IMON is not set
> +# CONFIG_MEDIA_ATTACH is not set
> +CONFIG_MEDIA_TUNER=y
> +CONFIG_MEDIA_TUNER_CUSTOMISE=y
> +CONFIG_MEDIA_TUNER_SIMPLE=m
> +CONFIG_MEDIA_TUNER_TDA8290=m
> +CONFIG_MEDIA_TUNER_TDA827X=m
> +CONFIG_MEDIA_TUNER_TDA18271=m
> +CONFIG_MEDIA_TUNER_TDA9887=m
> +CONFIG_MEDIA_TUNER_TEA5761=m
> +CONFIG_MEDIA_TUNER_TEA5767=m
> +CONFIG_MEDIA_TUNER_MT20XX=m
> +CONFIG_MEDIA_TUNER_MT2060=m
> +CONFIG_MEDIA_TUNER_MT2266=m
> +CONFIG_MEDIA_TUNER_MT2131=m
> +CONFIG_MEDIA_TUNER_QT1010=m
> +CONFIG_MEDIA_TUNER_XC2028=m
> +CONFIG_MEDIA_TUNER_XC5000=m
> +CONFIG_MEDIA_TUNER_MXL5005S=m
> +CONFIG_MEDIA_TUNER_MXL5007T=m
> +CONFIG_MEDIA_TUNER_MC44S803=m
> +CONFIG_MEDIA_TUNER_MAX2165=m
> +CONFIG_VIDEO_V4L2=y
> +CONFIG_VIDEO_V4L1=y
> +CONFIG_VIDEOBUF_GEN=y
> +CONFIG_VIDEOBUF_DMA_SG=y
> +CONFIG_VIDEO_CAPTURE_DRIVERS=y
> +# CONFIG_VIDEO_ADV_DEBUG is not set
> +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
> +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y
> +CONFIG_VIDEO_IR_I2C=y
> +# CONFIG_VIDEO_VIVI is not set
> +# CONFIG_VIDEO_BT848 is not set
> +# CONFIG_VIDEO_PMS is not set
> +# CONFIG_VIDEO_CPIA is not set
> +# CONFIG_VIDEO_CPIA2 is not set
> +# CONFIG_VIDEO_SAA5246A is not set
> +# CONFIG_VIDEO_SAA5249 is not set
> +# CONFIG_VIDEO_STRADIS is not set
> +# CONFIG_VIDEO_ZORAN is not set
> +# CONFIG_VIDEO_SAA7134 is not set
> +# CONFIG_VIDEO_MXB is not set
> +# CONFIG_VIDEO_HEXIUM_ORION is not set
> +# CONFIG_VIDEO_HEXIUM_GEMINI is not set
> +# CONFIG_VIDEO_CX88 is not set
> +# CONFIG_VIDEO_IVTV is not set
> +# CONFIG_VIDEO_CAFE_CCIC is not set
> +CONFIG_SOC_CAMERA=y
> +# CONFIG_SOC_CAMERA_MT9M001 is not set
> +CONFIG_SOC_CAMERA_MT9M111=y
> +# CONFIG_SOC_CAMERA_MT9T031 is not set
> +# CONFIG_SOC_CAMERA_MT9T112 is not set
> +# CONFIG_SOC_CAMERA_MT9V022 is not set
> +# CONFIG_SOC_CAMERA_RJ54N1 is not set
> +# CONFIG_SOC_CAMERA_TW9910 is not set
> +# CONFIG_SOC_CAMERA_PLATFORM is not set
> +# CONFIG_SOC_CAMERA_OV772X is not set
> +# CONFIG_SOC_CAMERA_OV9640 is not set
> +CONFIG_VIDEO_PXA27x=y
> +# CONFIG_VIDEO_SH_MOBILE_CEU is not set
> +CONFIG_V4L_USB_DRIVERS=y
> +# CONFIG_USB_VIDEO_CLASS is not set
> +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
> +CONFIG_USB_GSPCA=m
> +# CONFIG_USB_M5602 is not set
> +# CONFIG_USB_STV06XX is not set
> +# CONFIG_USB_GL860 is not set
> +# CONFIG_USB_GSPCA_BENQ is not set
> +# CONFIG_USB_GSPCA_CONEX is not set
> +# CONFIG_USB_GSPCA_CPIA1 is not set
> +# CONFIG_USB_GSPCA_ETOMS is not set
> +# CONFIG_USB_GSPCA_FINEPIX is not set
> +# CONFIG_USB_GSPCA_JEILINJ is not set
> +# CONFIG_USB_GSPCA_MARS is not set
> +# CONFIG_USB_GSPCA_MR97310A is not set
> +# CONFIG_USB_GSPCA_OV519 is not set
> +# CONFIG_USB_GSPCA_OV534 is not set
> +# CONFIG_USB_GSPCA_OV534_9 is not set
> +# CONFIG_USB_GSPCA_PAC207 is not set
> +# CONFIG_USB_GSPCA_PAC7302 is not set
> +# CONFIG_USB_GSPCA_PAC7311 is not set
> +# CONFIG_USB_GSPCA_SN9C2028 is not set
> +# CONFIG_USB_GSPCA_SN9C20X is not set
> +# CONFIG_USB_GSPCA_SONIXB is not set
> +# CONFIG_USB_GSPCA_SONIXJ is not set
> +# CONFIG_USB_GSPCA_SPCA500 is not set
> +# CONFIG_USB_GSPCA_SPCA501 is not set
> +# CONFIG_USB_GSPCA_SPCA505 is not set
> +# CONFIG_USB_GSPCA_SPCA506 is not set
> +# CONFIG_USB_GSPCA_SPCA508 is not set
> +# CONFIG_USB_GSPCA_SPCA561 is not set
> +# CONFIG_USB_GSPCA_SQ905 is not set
> +# CONFIG_USB_GSPCA_SQ905C is not set
> +# CONFIG_USB_GSPCA_STK014 is not set
> +# CONFIG_USB_GSPCA_STV0680 is not set
> +# CONFIG_USB_GSPCA_SUNPLUS is not set
> +# CONFIG_USB_GSPCA_T613 is not set
> +# CONFIG_USB_GSPCA_TV8532 is not set
> +# CONFIG_USB_GSPCA_VC032X is not set
> +# CONFIG_USB_GSPCA_ZC3XX is not set
> +# CONFIG_VIDEO_PVRUSB2 is not set
> +# CONFIG_VIDEO_HDPVR is not set
> +# CONFIG_VIDEO_EM28XX is not set
> +# CONFIG_VIDEO_CX231XX is not set
> +# CONFIG_VIDEO_USBVISION is not set
> +# CONFIG_USB_VICAM is not set
> +# CONFIG_USB_IBMCAM is not set
> +# CONFIG_USB_KONICAWC is not set
> +# CONFIG_USB_QUICKCAM_MESSENGER is not set
> +# CONFIG_USB_ET61X251 is not set
> +# CONFIG_VIDEO_OVCAMCHIP is not set
> +# CONFIG_USB_OV511 is not set
> +# CONFIG_USB_SE401 is not set
> +# CONFIG_USB_SN9C102 is not set
> +# CONFIG_USB_STV680 is not set
> +# CONFIG_USB_ZC0301 is not set
> +# CONFIG_USB_PWC is not set
> +# CONFIG_USB_ZR364XX is not set
> +# CONFIG_USB_STKWEBCAM is not set
> +# CONFIG_USB_S2255 is not set
> +# CONFIG_V4L_MEM2MEM_DRIVERS is not set
> +CONFIG_RADIO_ADAPTERS=y
> +# CONFIG_RADIO_CADET is not set
> +# CONFIG_RADIO_RTRACK is not set
> +# CONFIG_RADIO_RTRACK2 is not set
> +# CONFIG_RADIO_AZTECH is not set
> +# CONFIG_RADIO_GEMTEK is not set
> +# CONFIG_RADIO_GEMTEK_PCI is not set
> +# CONFIG_RADIO_MAXIRADIO is not set
> +# CONFIG_RADIO_MAESTRO is not set
> +# CONFIG_RADIO_MIROPCM20 is not set
> +# CONFIG_RADIO_SF16FMI is not set
> +# CONFIG_RADIO_SF16FMR2 is not set
> +# CONFIG_RADIO_TERRATEC is not set
> +# CONFIG_RADIO_TRUST is not set
> +# CONFIG_RADIO_TYPHOON is not set
> +# CONFIG_RADIO_ZOLTRIX is not set
> +# CONFIG_I2C_SI4713 is not set
> +# CONFIG_RADIO_SI4713 is not set
> +# CONFIG_USB_DSBR is not set
> +# CONFIG_RADIO_SI470X is not set
> +# CONFIG_USB_MR800 is not set
> +CONFIG_RADIO_TEA5764=y
> +CONFIG_RADIO_TEA5764_XTAL=y
> +# CONFIG_RADIO_SAA7706H is not set
> +# CONFIG_RADIO_TEF6862 is not set
> +CONFIG_DAB=y
> +# CONFIG_USB_DABUSB is not set
> +
> +#
> +# Graphics support
> +#
> +CONFIG_VGA_ARB=y
> +CONFIG_VGA_ARB_MAX_GPUS=16
> +# CONFIG_DRM is not set
> +# CONFIG_VGASTATE is not set
> +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> +CONFIG_FB=y
> +CONFIG_FIRMWARE_EDID=y
> +# CONFIG_FB_DDC is not set
> +# CONFIG_FB_BOOT_VESA_SUPPORT is not set
> +CONFIG_FB_CFB_FILLRECT=y
> +CONFIG_FB_CFB_COPYAREA=y
> +CONFIG_FB_CFB_IMAGEBLIT=y
> +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> +CONFIG_FB_SYS_FILLRECT=m
> +CONFIG_FB_SYS_COPYAREA=m
> +CONFIG_FB_SYS_IMAGEBLIT=m
> +# CONFIG_FB_FOREIGN_ENDIAN is not set
> +CONFIG_FB_SYS_FOPS=m
> +# CONFIG_FB_SVGALIB is not set
> +# CONFIG_FB_MACMODES is not set
> +# CONFIG_FB_BACKLIGHT is not set
> +CONFIG_FB_MODE_HELPERS=y
> +CONFIG_FB_TILEBLITTING=y
> +
> +#
> +# Frame buffer hardware drivers
> +#
> +# CONFIG_FB_CIRRUS is not set
> +# CONFIG_FB_PM2 is not set
> +# CONFIG_FB_CYBER2000 is not set
> +# CONFIG_FB_ASILIANT is not set
> +# CONFIG_FB_IMSTT is not set
> +# CONFIG_FB_UVESA is not set
> +# CONFIG_FB_S1D13XXX is not set
> +# CONFIG_FB_NVIDIA is not set
> +# CONFIG_FB_RIVA is not set
> +# CONFIG_FB_MATROX is not set
> +# CONFIG_FB_RADEON is not set
> +# CONFIG_FB_ATY128 is not set
> +# CONFIG_FB_ATY is not set
> +# CONFIG_FB_S3 is not set
> +# CONFIG_FB_SAVAGE is not set
> +# CONFIG_FB_SIS is not set
> +# CONFIG_FB_VIA is not set
> +# CONFIG_FB_NEOMAGIC is not set
> +# CONFIG_FB_KYRO is not set
> +# CONFIG_FB_3DFX is not set
> +# CONFIG_FB_VOODOO1 is not set
> +# CONFIG_FB_VT8623 is not set
> +# CONFIG_FB_TRIDENT is not set
> +# CONFIG_FB_ARK is not set
> +# CONFIG_FB_PM3 is not set
> +# CONFIG_FB_CARMINE is not set
> +CONFIG_FB_PXA=m
> +CONFIG_FB_PXA_OVERLAY=y
> +# CONFIG_FB_PXA_SMARTPANEL is not set
> +CONFIG_FB_PXA_PARAMETERS=y
> +CONFIG_FB_MBX=m
> +# CONFIG_FB_MBX_DEBUG is not set
> +CONFIG_FB_W100=y
> +# CONFIG_FB_TMIO is not set
> +CONFIG_FB_VIRTUAL=m
> +# CONFIG_FB_METRONOME is not set
> +# CONFIG_FB_MB862XX is not set
> +# CONFIG_FB_BROADSHEET is not set
> +CONFIG_BACKLIGHT_LCD_SUPPORT=y
> +CONFIG_LCD_CLASS_DEVICE=m
> +# CONFIG_LCD_L4F00242T03 is not set
> +# CONFIG_LCD_LMS283GF05 is not set
> +# CONFIG_LCD_LTV350QV is not set
> +CONFIG_LCD_TDO24M=m
> +# CONFIG_LCD_VGG2432A4 is not set
> +# CONFIG_LCD_PLATFORM is not set
> +# CONFIG_LCD_S6E63M0 is not set
> +CONFIG_BACKLIGHT_CLASS_DEVICE=m
> +CONFIG_BACKLIGHT_GENERIC=m
> +CONFIG_BACKLIGHT_PWM=m
> +CONFIG_BACKLIGHT_DA903X=m
> +# CONFIG_BACKLIGHT_ADP8860 is not set
> +
> +#
> +# Display device support
> +#
> +CONFIG_DISPLAY_SUPPORT=y
> +
> +#
> +# Display hardware drivers
> +#
> +
> +#
> +# Console display driver support
> +#
> +# CONFIG_VGA_CONSOLE is not set
> +# CONFIG_MDA_CONSOLE is not set
> +CONFIG_DUMMY_CONSOLE=y
> +CONFIG_FRAMEBUFFER_CONSOLE=m
> +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
> +CONFIG_FONTS=y
> +CONFIG_FONT_8x8=y
> +CONFIG_FONT_8x16=y
> +# CONFIG_FONT_6x11 is not set
> +# CONFIG_FONT_7x14 is not set
> +# CONFIG_FONT_PEARL_8x8 is not set
> +# CONFIG_FONT_ACORN_8x8 is not set
> +CONFIG_FONT_MINI_4x6=y
> +# CONFIG_FONT_SUN8x16 is not set
> +# CONFIG_FONT_SUN12x22 is not set
> +# CONFIG_FONT_10x18 is not set
> +CONFIG_LOGO=y
> +CONFIG_LOGO_LINUX_MONO=y
> +CONFIG_LOGO_LINUX_VGA16=y
> +CONFIG_LOGO_LINUX_CLUT224=y
> +CONFIG_SOUND=m
> +CONFIG_SOUND_OSS_CORE=y
> +CONFIG_SOUND_OSS_CORE_PRECLAIM=y
> +CONFIG_SND=m
> +CONFIG_SND_TIMER=m
> +CONFIG_SND_PCM=m
> +CONFIG_SND_HWDEP=m
> +CONFIG_SND_RAWMIDI=m
> +CONFIG_SND_JACK=y
> +CONFIG_SND_SEQUENCER=m
> +# CONFIG_SND_SEQ_DUMMY is not set
> +CONFIG_SND_OSSEMUL=y
> +CONFIG_SND_MIXER_OSS=m
> +CONFIG_SND_PCM_OSS=m
> +CONFIG_SND_PCM_OSS_PLUGINS=y
> +# CONFIG_SND_SEQUENCER_OSS is not set
> +# CONFIG_SND_HRTIMER is not set
> +CONFIG_SND_DYNAMIC_MINORS=y
> +CONFIG_SND_SUPPORT_OLD_API=y
> +CONFIG_SND_VERBOSE_PROCFS=y
> +CONFIG_SND_VERBOSE_PRINTK=y
> +CONFIG_SND_DEBUG=y
> +# CONFIG_SND_DEBUG_VERBOSE is not set
> +# CONFIG_SND_PCM_XRUN_DEBUG is not set
> +CONFIG_SND_VMASTER=y
> +CONFIG_SND_RAWMIDI_SEQ=m
> +# CONFIG_SND_OPL3_LIB_SEQ is not set
> +# CONFIG_SND_OPL4_LIB_SEQ is not set
> +# CONFIG_SND_SBAWE_SEQ is not set
> +# CONFIG_SND_EMU10K1_SEQ is not set
> +CONFIG_SND_AC97_CODEC=m
> +CONFIG_SND_DRIVERS=y
> +# CONFIG_SND_DUMMY is not set
> +# CONFIG_SND_VIRMIDI is not set
> +# CONFIG_SND_MTPAV is not set
> +# CONFIG_SND_SERIAL_U16550 is not set
> +# CONFIG_SND_MPU401 is not set
> +# CONFIG_SND_AC97_POWER_SAVE is not set
> +CONFIG_SND_PCI=y
> +# CONFIG_SND_AD1889 is not set
> +# CONFIG_SND_ALS300 is not set
> +# CONFIG_SND_ALI5451 is not set
> +# CONFIG_SND_ATIIXP is not set
> +# CONFIG_SND_ATIIXP_MODEM is not set
> +# CONFIG_SND_AU8810 is not set
> +# CONFIG_SND_AU8820 is not set
> +# CONFIG_SND_AU8830 is not set
> +# CONFIG_SND_AW2 is not set
> +# CONFIG_SND_AZT3328 is not set
> +# CONFIG_SND_BT87X is not set
> +# CONFIG_SND_CA0106 is not set
> +# CONFIG_SND_CMIPCI is not set
> +# CONFIG_SND_OXYGEN is not set
> +# CONFIG_SND_CS4281 is not set
> +# CONFIG_SND_CS46XX is not set
> +# CONFIG_SND_CS5535AUDIO is not set
> +# CONFIG_SND_CTXFI is not set
> +# CONFIG_SND_DARLA20 is not set
> +# CONFIG_SND_GINA20 is not set
> +# CONFIG_SND_LAYLA20 is not set
> +# CONFIG_SND_DARLA24 is not set
> +# CONFIG_SND_GINA24 is not set
> +# CONFIG_SND_LAYLA24 is not set
> +# CONFIG_SND_MONA is not set
> +# CONFIG_SND_MIA is not set
> +# CONFIG_SND_ECHO3G is not set
> +# CONFIG_SND_INDIGO is not set
> +# CONFIG_SND_INDIGOIO is not set
> +# CONFIG_SND_INDIGODJ is not set
> +# CONFIG_SND_INDIGOIOX is not set
> +# CONFIG_SND_INDIGODJX is not set
> +# CONFIG_SND_EMU10K1 is not set
> +# CONFIG_SND_EMU10K1X is not set
> +# CONFIG_SND_ENS1370 is not set
> +# CONFIG_SND_ENS1371 is not set
> +# CONFIG_SND_ES1938 is not set
> +# CONFIG_SND_ES1968 is not set
> +# CONFIG_SND_FM801 is not set
> +# CONFIG_SND_HDA_INTEL is not set
> +# CONFIG_SND_HDSP is not set
> +# CONFIG_SND_HDSPM is not set
> +# CONFIG_SND_HIFIER is not set
> +# CONFIG_SND_ICE1712 is not set
> +# CONFIG_SND_ICE1724 is not set
> +# CONFIG_SND_INTEL8X0 is not set
> +# CONFIG_SND_INTEL8X0M is not set
> +# CONFIG_SND_KORG1212 is not set
> +# CONFIG_SND_LX6464ES is not set
> +# CONFIG_SND_MAESTRO3 is not set
> +# CONFIG_SND_MIXART is not set
> +# CONFIG_SND_NM256 is not set
> +# CONFIG_SND_PCXHR is not set
> +# CONFIG_SND_RIPTIDE is not set
> +# CONFIG_SND_RME32 is not set
> +# CONFIG_SND_RME96 is not set
> +# CONFIG_SND_RME9652 is not set
> +# CONFIG_SND_SONICVIBES is not set
> +# CONFIG_SND_TRIDENT is not set
> +# CONFIG_SND_VIA82XX is not set
> +# CONFIG_SND_VIA82XX_MODEM is not set
> +# CONFIG_SND_VIRTUOSO is not set
> +# CONFIG_SND_VX222 is not set
> +# CONFIG_SND_YMFPCI is not set
> +CONFIG_SND_ARM=y
> +CONFIG_SND_PXA2XX_PCM=m
> +CONFIG_SND_PXA2XX_LIB=m
> +CONFIG_SND_PXA2XX_LIB_AC97=y
> +CONFIG_SND_PXA2XX_AC97=m
> +CONFIG_SND_SPI=y
> +CONFIG_SND_USB=y
> +CONFIG_SND_USB_AUDIO=m
> +# CONFIG_SND_USB_UA101 is not set
> +# CONFIG_SND_USB_CAIAQ is not set
> +CONFIG_SND_PCMCIA=y
> +# CONFIG_SND_VXPOCKET is not set
> +# CONFIG_SND_PDAUDIOCF is not set
> +CONFIG_SND_SOC=m
> +CONFIG_SND_SOC_AC97_BUS=y
> +CONFIG_SND_PXA2XX_SOC=m
> +CONFIG_SND_PXA2XX_SOC_AC97=m
> +# CONFIG_SND_PXA2XX_SOC_E740 is not set
> +# CONFIG_SND_PXA2XX_SOC_E750 is not set
> +CONFIG_SND_PXA2XX_SOC_E800=m
> +CONFIG_SND_PXA2XX_SOC_EM_X270=m
> +# CONFIG_SND_PXA2XX_SOC_PALM27X is not set
> +# CONFIG_SND_PXA2XX_SOC_MAGICIAN is not set
> +# CONFIG_SND_PXA2XX_SOC_IMOTE2 is not set
> +CONFIG_SND_SOC_I2C_AND_SPI=m
> +# CONFIG_SND_SOC_ALL_CODECS is not set
> +CONFIG_SND_SOC_WM9712=m
> +# CONFIG_SOUND_PRIME is not set
> +CONFIG_AC97_BUS=m
> +CONFIG_HID_SUPPORT=y
> +CONFIG_HID=y
> +# CONFIG_HIDRAW is not set
> +
> +#
> +# USB Input Devices
> +#
> +CONFIG_USB_HID=m
> +# CONFIG_HID_PID is not set
> +# CONFIG_USB_HIDDEV is not set
> +
> +#
> +# USB HID Boot Protocol drivers
> +#
> +# CONFIG_USB_KBD is not set
> +# CONFIG_USB_MOUSE is not set
> +
> +#
> +# Special HID drivers
> +#
> +# CONFIG_HID_3M_PCT is not set
> +CONFIG_HID_A4TECH=m
> +CONFIG_HID_APPLE=m
> +CONFIG_HID_BELKIN=m
> +# CONFIG_HID_CANDO is not set
> +CONFIG_HID_CHERRY=m
> +CONFIG_HID_CHICONY=m
> +# CONFIG_HID_PRODIKEYS is not set
> +CONFIG_HID_CYPRESS=m
> +# CONFIG_HID_DRAGONRISE is not set
> +# CONFIG_HID_EGALAX is not set
> +CONFIG_HID_EZKEY=m
> +# CONFIG_HID_KYE is not set
> +CONFIG_HID_GYRATION=m
> +# CONFIG_HID_TWINHAN is not set
> +# CONFIG_HID_KENSINGTON is not set
> +CONFIG_HID_LOGITECH=m
> +# CONFIG_LOGITECH_FF is not set
> +# CONFIG_LOGIRUMBLEPAD2_FF is not set
> +# CONFIG_LOGIG940_FF is not set
> +# CONFIG_HID_MAGICMOUSE is not set
> +CONFIG_HID_MICROSOFT=m
> +# CONFIG_HID_MOSART is not set
> +CONFIG_HID_MONTEREY=m
> +# CONFIG_HID_NTRIG is not set
> +# CONFIG_HID_ORTEK is not set
> +CONFIG_HID_PANTHERLORD=m
> +# CONFIG_PANTHERLORD_FF is not set
> +CONFIG_HID_PETALYNX=m
> +# CONFIG_HID_PICOLCD is not set
> +# CONFIG_HID_QUANTA is not set
> +# CONFIG_HID_ROCCAT is not set
> +# CONFIG_HID_ROCCAT_KONE is not set
> +CONFIG_HID_SAMSUNG=m
> +CONFIG_HID_SONY=m
> +# CONFIG_HID_STANTUM is not set
> +CONFIG_HID_SUNPLUS=m
> +# CONFIG_HID_GREENASIA is not set
> +# CONFIG_HID_SMARTJOYPLUS is not set
> +# CONFIG_HID_TOPSEED is not set
> +# CONFIG_HID_THRUSTMASTER is not set
> +# CONFIG_HID_WACOM is not set
> +# CONFIG_HID_ZEROPLUS is not set
> +# CONFIG_HID_ZYDACRON is not set
> +CONFIG_USB_SUPPORT=y
> +CONFIG_USB_ARCH_HAS_HCD=y
> +CONFIG_USB_ARCH_HAS_OHCI=y
> +CONFIG_USB_ARCH_HAS_EHCI=y
> +CONFIG_USB=m
> +# CONFIG_USB_DEBUG is not set
> +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
> +
> +#
> +# Miscellaneous USB options
> +#
> +CONFIG_USB_DEVICEFS=y
> +CONFIG_USB_DEVICE_CLASS=y
> +# CONFIG_USB_DYNAMIC_MINORS is not set
> +CONFIG_USB_SUSPEND=y
> +# CONFIG_USB_OTG is not set
> +# CONFIG_USB_OTG_WHITELIST is not set
> +# CONFIG_USB_OTG_BLACKLIST_HUB is not set
> +CONFIG_USB_MON=m
> +# CONFIG_USB_WUSB is not set
> +# CONFIG_USB_WUSB_CBAF is not set
> +
> +#
> +# USB Host Controller Drivers
> +#
> +# CONFIG_USB_C67X00_HCD is not set
> +# CONFIG_USB_XHCI_HCD is not set
> +# CONFIG_USB_EHCI_HCD is not set
> +# CONFIG_USB_OXU210HP_HCD is not set
> +CONFIG_USB_ISP116X_HCD=m
> +# CONFIG_USB_ISP1760_HCD is not set
> +# CONFIG_USB_ISP1362_HCD is not set
> +CONFIG_USB_OHCI_HCD=m
> +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
> +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
> +CONFIG_USB_OHCI_LITTLE_ENDIAN=y
> +# CONFIG_USB_UHCI_HCD is not set
> +CONFIG_USB_SL811_HCD=m
> +# CONFIG_USB_SL811_CS is not set
> +CONFIG_USB_R8A66597_HCD=m
> +# CONFIG_USB_WHCI_HCD is not set
> +# CONFIG_USB_HWA_HCD is not set
> +# CONFIG_USB_MUSB_HDRC is not set
> +# CONFIG_USB_GADGET_MUSB_HDRC is not set
> +
> +#
> +# USB Device Class drivers
> +#
> +CONFIG_USB_ACM=m
> +# CONFIG_USB_PRINTER is not set
> +# CONFIG_USB_WDM is not set
> +# CONFIG_USB_TMC is not set
> +
> +#
> +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
> +#
> +
> +#
> +# also be needed; see USB_STORAGE Help for more info
> +#
> +CONFIG_USB_STORAGE=m
> +# CONFIG_USB_STORAGE_DEBUG is not set
> +# CONFIG_USB_STORAGE_DATAFAB is not set
> +# CONFIG_USB_STORAGE_FREECOM is not set
> +# CONFIG_USB_STORAGE_ISD200 is not set
> +# CONFIG_USB_STORAGE_USBAT is not set
> +# CONFIG_USB_STORAGE_SDDR09 is not set
> +# CONFIG_USB_STORAGE_SDDR55 is not set
> +# CONFIG_USB_STORAGE_JUMPSHOT is not set
> +# CONFIG_USB_STORAGE_ALAUDA is not set
> +# CONFIG_USB_STORAGE_ONETOUCH is not set
> +# CONFIG_USB_STORAGE_KARMA is not set
> +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
> +# CONFIG_USB_LIBUSUAL is not set
> +
> +#
> +# USB Imaging devices
> +#
> +# CONFIG_USB_MDC800 is not set
> +# CONFIG_USB_MICROTEK is not set
> +
> +#
> +# USB port drivers
> +#
> +CONFIG_USB_SERIAL=m
> +# CONFIG_USB_EZUSB is not set
> +CONFIG_USB_SERIAL_GENERIC=y
> +# CONFIG_USB_SERIAL_AIRCABLE is not set
> +# CONFIG_USB_SERIAL_ARK3116 is not set
> +# CONFIG_USB_SERIAL_BELKIN is not set
> +# CONFIG_USB_SERIAL_CH341 is not set
> +# CONFIG_USB_SERIAL_WHITEHEAT is not set
> +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
> +# CONFIG_USB_SERIAL_CP210X is not set
> +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
> +# CONFIG_USB_SERIAL_EMPEG is not set
> +# CONFIG_USB_SERIAL_FTDI_SIO is not set
> +# CONFIG_USB_SERIAL_FUNSOFT is not set
> +# CONFIG_USB_SERIAL_VISOR is not set
> +# CONFIG_USB_SERIAL_IPAQ is not set
> +# CONFIG_USB_SERIAL_IR is not set
> +# CONFIG_USB_SERIAL_EDGEPORT is not set
> +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
> +# CONFIG_USB_SERIAL_GARMIN is not set
> +# CONFIG_USB_SERIAL_IPW is not set
> +# CONFIG_USB_SERIAL_IUU is not set
> +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
> +# CONFIG_USB_SERIAL_KEYSPAN is not set
> +# CONFIG_USB_SERIAL_KLSI is not set
> +# CONFIG_USB_SERIAL_KOBIL_SCT is not set
> +CONFIG_USB_SERIAL_MCT_U232=m
> +# CONFIG_USB_SERIAL_MOS7720 is not set
> +# CONFIG_USB_SERIAL_MOS7840 is not set
> +# CONFIG_USB_SERIAL_MOTOROLA is not set
> +# CONFIG_USB_SERIAL_NAVMAN is not set
> +# CONFIG_USB_SERIAL_PL2303 is not set
> +# CONFIG_USB_SERIAL_OTI6858 is not set
> +# CONFIG_USB_SERIAL_QCAUX is not set
> +# CONFIG_USB_SERIAL_QUALCOMM is not set
> +# CONFIG_USB_SERIAL_SPCP8X5 is not set
> +# CONFIG_USB_SERIAL_HP4X is not set
> +# CONFIG_USB_SERIAL_SAFE is not set
> +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
> +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
> +# CONFIG_USB_SERIAL_SYMBOL is not set
> +# CONFIG_USB_SERIAL_TI is not set
> +# CONFIG_USB_SERIAL_CYBERJACK is not set
> +# CONFIG_USB_SERIAL_XIRCOM is not set
> +# CONFIG_USB_SERIAL_OPTION is not set
> +# CONFIG_USB_SERIAL_OMNINET is not set
> +# CONFIG_USB_SERIAL_OPTICON is not set
> +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
> +# CONFIG_USB_SERIAL_ZIO is not set
> +# CONFIG_USB_SERIAL_DEBUG is not set
> +
> +#
> +# USB Miscellaneous drivers
> +#
> +# CONFIG_USB_EMI62 is not set
> +# CONFIG_USB_EMI26 is not set
> +# CONFIG_USB_ADUTUX is not set
> +# CONFIG_USB_SEVSEG is not set
> +# CONFIG_USB_RIO500 is not set
> +# CONFIG_USB_LEGOTOWER is not set
> +# CONFIG_USB_LCD is not set
> +# CONFIG_USB_LED is not set
> +# CONFIG_USB_CYPRESS_CY7C63 is not set
> +# CONFIG_USB_CYTHERM is not set
> +# CONFIG_USB_IDMOUSE is not set
> +# CONFIG_USB_FTDI_ELAN is not set
> +# CONFIG_USB_APPLEDISPLAY is not set
> +# CONFIG_USB_LD is not set
> +# CONFIG_USB_TRANCEVIBRATOR is not set
> +# CONFIG_USB_IOWARRIOR is not set
> +# CONFIG_USB_TEST is not set
> +# CONFIG_USB_ISIGHTFW is not set
> +CONFIG_USB_GADGET=m
> +# CONFIG_USB_GADGET_DEBUG is not set
> +# CONFIG_USB_GADGET_DEBUG_FILES is not set
> +# CONFIG_USB_GADGET_DEBUG_FS is not set
> +CONFIG_USB_GADGET_VBUS_DRAW=2
> +CONFIG_USB_GADGET_SELECTED=y
> +# CONFIG_USB_GADGET_AT91 is not set
> +# CONFIG_USB_GADGET_ATMEL_USBA is not set
> +# CONFIG_USB_GADGET_FSL_USB2 is not set
> +# CONFIG_USB_GADGET_LH7A40X is not set
> +# CONFIG_USB_GADGET_OMAP is not set
> +# CONFIG_USB_GADGET_PXA25X is not set
> +# CONFIG_USB_GADGET_R8A66597 is not set
> +CONFIG_USB_GADGET_PXA27X=y
> +CONFIG_USB_PXA27X=m
> +# CONFIG_USB_GADGET_S3C_HSOTG is not set
> +# CONFIG_USB_GADGET_IMX is not set
> +# CONFIG_USB_GADGET_S3C2410 is not set
> +# CONFIG_USB_GADGET_M66592 is not set
> +# CONFIG_USB_GADGET_AMD5536UDC is not set
> +# CONFIG_USB_GADGET_FSL_QE is not set
> +# CONFIG_USB_GADGET_CI13XXX is not set
> +# CONFIG_USB_GADGET_NET2280 is not set
> +# CONFIG_USB_GADGET_GOKU is not set
> +# CONFIG_USB_GADGET_LANGWELL is not set
> +# CONFIG_USB_GADGET_DUMMY_HCD is not set
> +# CONFIG_USB_GADGET_DUALSPEED is not set
> +# CONFIG_USB_ZERO is not set
> +# CONFIG_USB_AUDIO is not set
> +CONFIG_USB_ETH=m
> +CONFIG_USB_ETH_RNDIS=y
> +# CONFIG_USB_ETH_EEM is not set
> +CONFIG_USB_GADGETFS=m
> +# CONFIG_USB_FUNCTIONFS is not set
> +CONFIG_USB_FILE_STORAGE=m
> +# CONFIG_USB_FILE_STORAGE_TEST is not set
> +# CONFIG_USB_MASS_STORAGE is not set
> +CONFIG_USB_G_SERIAL=m
> +# CONFIG_USB_MIDI_GADGET is not set
> +CONFIG_USB_G_PRINTER=m
> +CONFIG_USB_CDC_COMPOSITE=m
> +# CONFIG_USB_G_NOKIA is not set
> +# CONFIG_USB_G_MULTI is not set
> +# CONFIG_USB_G_HID is not set
> +# CONFIG_USB_G_WEBCAM is not set
> +
> +#
> +# OTG and related infrastructure
> +#
> +CONFIG_USB_OTG_UTILS=y
> +CONFIG_USB_GPIO_VBUS=m
> +# CONFIG_USB_ULPI is not set
> +# CONFIG_NOP_USB_XCEIV is not set
> +# CONFIG_UWB is not set
> +CONFIG_MMC=y
> +CONFIG_MMC_DEBUG=y
> +CONFIG_MMC_UNSAFE_RESUME=y
> +
> +#
> +# MMC/SD/SDIO Card Drivers
> +#
> +CONFIG_MMC_BLOCK=y
> +CONFIG_MMC_BLOCK_BOUNCE=y
> +CONFIG_SDIO_UART=m
> +# CONFIG_MMC_TEST is not set
> +
> +#
> +# MMC/SD/SDIO Host Controller Drivers
> +#
> +CONFIG_MMC_PXA=y
> +# CONFIG_MMC_SDHCI is not set
> +# CONFIG_MMC_TIFM_SD is not set
> +CONFIG_MMC_SPI=y
> +# CONFIG_MMC_SDRICOH_CS is not set
> +CONFIG_MMC_TMIO=y
> +# CONFIG_MMC_CB710 is not set
> +# CONFIG_MMC_VIA_SDMMC is not set
> +# CONFIG_MEMSTICK is not set
> +CONFIG_NEW_LEDS=y
> +CONFIG_LEDS_CLASS=m
> +
> +#
> +# LED drivers
> +#
> +# CONFIG_LEDS_PCA9532 is not set
> +CONFIG_LEDS_GPIO=m
> +CONFIG_LEDS_GPIO_PLATFORM=y
> +CONFIG_LEDS_LP3944=m
> +# CONFIG_LEDS_PCA955X is not set
> +CONFIG_LEDS_DA903X=m
> +# CONFIG_LEDS_DAC124S085 is not set
> +# CONFIG_LEDS_PWM is not set
> +# CONFIG_LEDS_REGULATOR is not set
> +# CONFIG_LEDS_BD2802 is not set
> +# CONFIG_LEDS_LT3593 is not set
> +CONFIG_LEDS_TRIGGERS=y
> +
> +#
> +# LED Triggers
> +#
> +CONFIG_LEDS_TRIGGER_TIMER=m
> +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
> +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
> +CONFIG_LEDS_TRIGGER_BACKLIGHT=m
> +CONFIG_LEDS_TRIGGER_GPIO=m
> +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
> +
> +#
> +# iptables trigger is under Netfilter config (LED target)
> +#
> +# CONFIG_ACCESSIBILITY is not set
> +# CONFIG_INFINIBAND is not set
> +CONFIG_RTC_LIB=y
> +CONFIG_RTC_CLASS=m
> +
> +#
> +# RTC interfaces
> +#
> +CONFIG_RTC_INTF_SYSFS=y
> +CONFIG_RTC_INTF_PROC=y
> +CONFIG_RTC_INTF_DEV=y
> +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> +# CONFIG_RTC_DRV_TEST is not set
> +
> +#
> +# I2C RTC drivers
> +#
> +CONFIG_RTC_DRV_DS1307=m
> +# CONFIG_RTC_DRV_DS1374 is not set
> +# CONFIG_RTC_DRV_DS1672 is not set
> +# CONFIG_RTC_DRV_MAX6900 is not set
> +# CONFIG_RTC_DRV_RS5C372 is not set
> +CONFIG_RTC_DRV_ISL1208=m
> +# CONFIG_RTC_DRV_X1205 is not set
> +CONFIG_RTC_DRV_PCF8563=m
> +CONFIG_RTC_DRV_PCF8583=m
> +# CONFIG_RTC_DRV_M41T80 is not set
> +# CONFIG_RTC_DRV_BQ32K is not set
> +# CONFIG_RTC_DRV_S35390A is not set
> +# CONFIG_RTC_DRV_FM3130 is not set
> +# CONFIG_RTC_DRV_RX8581 is not set
> +# CONFIG_RTC_DRV_RX8025 is not set
> +
> +#
> +# SPI RTC drivers
> +#
> +# CONFIG_RTC_DRV_M41T94 is not set
> +# CONFIG_RTC_DRV_DS1305 is not set
> +# CONFIG_RTC_DRV_DS1390 is not set
> +# CONFIG_RTC_DRV_MAX6902 is not set
> +# CONFIG_RTC_DRV_R9701 is not set
> +# CONFIG_RTC_DRV_RS5C348 is not set
> +# CONFIG_RTC_DRV_DS3234 is not set
> +# CONFIG_RTC_DRV_PCF2123 is not set
> +
> +#
> +# Platform RTC drivers
> +#
> +# CONFIG_RTC_DRV_CMOS is not set
> +# CONFIG_RTC_DRV_DS1286 is not set
> +# CONFIG_RTC_DRV_DS1511 is not set
> +# CONFIG_RTC_DRV_DS1553 is not set
> +# CONFIG_RTC_DRV_DS1742 is not set
> +# CONFIG_RTC_DRV_STK17TA8 is not set
> +# CONFIG_RTC_DRV_M48T86 is not set
> +# CONFIG_RTC_DRV_M48T35 is not set
> +# CONFIG_RTC_DRV_M48T59 is not set
> +# CONFIG_RTC_DRV_MSM6242 is not set
> +# CONFIG_RTC_DRV_BQ4802 is not set
> +# CONFIG_RTC_DRV_RP5C01 is not set
> +CONFIG_RTC_DRV_V3020=m
> +
> +#
> +# on-CPU RTC drivers
> +#
> +CONFIG_RTC_DRV_SA1100=m
> +CONFIG_RTC_DRV_PXA=m
> +CONFIG_RTC_DRV_PCAP=m
> +CONFIG_DMADEVICES=y
> +# CONFIG_DMADEVICES_DEBUG is not set
> +
> +#
> +# DMA Devices
> +#
> +# CONFIG_TIMB_DMA is not set
> +# CONFIG_AUXDISPLAY is not set
> +# CONFIG_UIO is not set
> +# CONFIG_STAGING is not set
> +
> +#
> +# File systems
> +#
> +CONFIG_EXT2_FS=y
> +CONFIG_EXT2_FS_XATTR=y
> +CONFIG_EXT2_FS_POSIX_ACL=y
> +CONFIG_EXT2_FS_SECURITY=y
> +# CONFIG_EXT2_FS_XIP is not set
> +CONFIG_EXT3_FS=y
> +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
> +CONFIG_EXT3_FS_XATTR=y
> +CONFIG_EXT3_FS_POSIX_ACL=y
> +CONFIG_EXT3_FS_SECURITY=y
> +# CONFIG_EXT4_FS is not set
> +CONFIG_JBD=y
> +# CONFIG_JBD_DEBUG is not set
> +CONFIG_FS_MBCACHE=y
> +CONFIG_REISERFS_FS=m
> +# CONFIG_REISERFS_CHECK is not set
> +# CONFIG_REISERFS_PROC_INFO is not set
> +CONFIG_REISERFS_FS_XATTR=y
> +CONFIG_REISERFS_FS_POSIX_ACL=y
> +CONFIG_REISERFS_FS_SECURITY=y
> +# CONFIG_JFS_FS is not set
> +CONFIG_FS_POSIX_ACL=y
> +CONFIG_XFS_FS=m
> +# CONFIG_XFS_QUOTA is not set
> +# CONFIG_XFS_POSIX_ACL is not set
> +# CONFIG_XFS_RT is not set
> +# CONFIG_XFS_DEBUG is not set
> +# CONFIG_GFS2_FS is not set
> +# CONFIG_OCFS2_FS is not set
> +# CONFIG_BTRFS_FS is not set
> +# CONFIG_NILFS2_FS is not set
> +CONFIG_FILE_LOCKING=y
> +CONFIG_FSNOTIFY=y
> +CONFIG_DNOTIFY=y
> +CONFIG_INOTIFY=y
> +CONFIG_INOTIFY_USER=y
> +# CONFIG_QUOTA is not set
> +CONFIG_AUTOFS_FS=y
> +CONFIG_AUTOFS4_FS=y
> +CONFIG_FUSE_FS=m
> +CONFIG_CUSE=m
> +
> +#
> +# Caches
> +#
> +# CONFIG_FSCACHE is not set
> +
> +#
> +# CD-ROM/DVD Filesystems
> +#
> +CONFIG_ISO9660_FS=m
> +CONFIG_JOLIET=y
> +CONFIG_ZISOFS=y
> +# CONFIG_UDF_FS is not set
> +
> +#
> +# DOS/FAT/NT Filesystems
> +#
> +CONFIG_FAT_FS=m
> +CONFIG_MSDOS_FS=m
> +CONFIG_VFAT_FS=m
> +CONFIG_FAT_DEFAULT_CODEPAGE=437
> +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> +# CONFIG_NTFS_FS is not set
> +
> +#
> +# Pseudo filesystems
> +#
> +CONFIG_PROC_FS=y
> +CONFIG_PROC_SYSCTL=y
> +CONFIG_PROC_PAGE_MONITOR=y
> +CONFIG_SYSFS=y
> +CONFIG_TMPFS=y
> +# CONFIG_TMPFS_POSIX_ACL is not set
> +# CONFIG_HUGETLB_PAGE is not set
> +CONFIG_CONFIGFS_FS=y
> +CONFIG_MISC_FILESYSTEMS=y
> +# CONFIG_ADFS_FS is not set
> +# CONFIG_AFFS_FS is not set
> +# CONFIG_ECRYPT_FS is not set
> +# CONFIG_HFS_FS is not set
> +# CONFIG_HFSPLUS_FS is not set
> +# CONFIG_BEFS_FS is not set
> +# CONFIG_BFS_FS is not set
> +# CONFIG_EFS_FS is not set
> +CONFIG_JFFS2_FS=y
> +CONFIG_JFFS2_FS_DEBUG=0
> +CONFIG_JFFS2_FS_WRITEBUFFER=y
> +CONFIG_JFFS2_FS_WBUF_VERIFY=y
> +CONFIG_JFFS2_SUMMARY=y
> +CONFIG_JFFS2_FS_XATTR=y
> +CONFIG_JFFS2_FS_POSIX_ACL=y
> +CONFIG_JFFS2_FS_SECURITY=y
> +CONFIG_JFFS2_COMPRESSION_OPTIONS=y
> +CONFIG_JFFS2_ZLIB=y
> +CONFIG_JFFS2_LZO=y
> +CONFIG_JFFS2_RTIME=y
> +CONFIG_JFFS2_RUBIN=y
> +# CONFIG_JFFS2_CMODE_NONE is not set
> +CONFIG_JFFS2_CMODE_PRIORITY=y
> +# CONFIG_JFFS2_CMODE_SIZE is not set
> +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
> +# CONFIG_LOGFS is not set
> +CONFIG_CRAMFS=m
> +CONFIG_SQUASHFS=m
> +# CONFIG_SQUASHFS_XATTRS is not set
> +# CONFIG_SQUASHFS_EMBEDDED is not set
> +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
> +# CONFIG_VXFS_FS is not set
> +# CONFIG_MINIX_FS is not set
> +# CONFIG_OMFS_FS is not set
> +# CONFIG_HPFS_FS is not set
> +# CONFIG_QNX4FS_FS is not set
> +CONFIG_ROMFS_FS=m
> +CONFIG_ROMFS_BACKED_BY_BLOCK=y
> +# CONFIG_ROMFS_BACKED_BY_MTD is not set
> +# CONFIG_ROMFS_BACKED_BY_BOTH is not set
> +CONFIG_ROMFS_ON_BLOCK=y
> +# CONFIG_SYSV_FS is not set
> +# CONFIG_UFS_FS is not set
> +CONFIG_NETWORK_FILESYSTEMS=y
> +CONFIG_NFS_FS=y
> +CONFIG_NFS_V3=y
> +CONFIG_NFS_V3_ACL=y
> +CONFIG_NFS_V4=y
> +# CONFIG_NFS_V4_1 is not set
> +CONFIG_ROOT_NFS=y
> +CONFIG_NFSD=m
> +CONFIG_NFSD_V2_ACL=y
> +CONFIG_NFSD_V3=y
> +CONFIG_NFSD_V3_ACL=y
> +CONFIG_NFSD_V4=y
> +CONFIG_LOCKD=y
> +CONFIG_LOCKD_V4=y
> +CONFIG_EXPORTFS=m
> +CONFIG_NFS_ACL_SUPPORT=y
> +CONFIG_NFS_COMMON=y
> +CONFIG_SUNRPC=y
> +CONFIG_SUNRPC_GSS=y
> +CONFIG_RPCSEC_GSS_KRB5=y
> +# CONFIG_RPCSEC_GSS_SPKM3 is not set
> +CONFIG_SMB_FS=m
> +# CONFIG_SMB_NLS_DEFAULT is not set
> +# CONFIG_CEPH_FS is not set
> +CONFIG_CIFS=m
> +CONFIG_CIFS_STATS=y
> +# CONFIG_CIFS_STATS2 is not set
> +CONFIG_CIFS_WEAK_PW_HASH=y
> +# CONFIG_CIFS_UPCALL is not set
> +CONFIG_CIFS_XATTR=y
> +CONFIG_CIFS_POSIX=y
> +# CONFIG_CIFS_DEBUG2 is not set
> +# CONFIG_CIFS_DFS_UPCALL is not set
> +# CONFIG_CIFS_EXPERIMENTAL is not set
> +# CONFIG_NCP_FS is not set
> +# CONFIG_CODA_FS is not set
> +# CONFIG_AFS_FS is not set
> +
> +#
> +# Partition Types
> +#
> +CONFIG_PARTITION_ADVANCED=y
> +# CONFIG_ACORN_PARTITION is not set
> +# CONFIG_OSF_PARTITION is not set
> +# CONFIG_AMIGA_PARTITION is not set
> +# CONFIG_ATARI_PARTITION is not set
> +# CONFIG_MAC_PARTITION is not set
> +CONFIG_MSDOS_PARTITION=y
> +# CONFIG_BSD_DISKLABEL is not set
> +# CONFIG_MINIX_SUBPARTITION is not set
> +# CONFIG_SOLARIS_X86_PARTITION is not set
> +# CONFIG_UNIXWARE_DISKLABEL is not set
> +CONFIG_LDM_PARTITION=y
> +# CONFIG_LDM_DEBUG is not set
> +# CONFIG_SGI_PARTITION is not set
> +# CONFIG_ULTRIX_PARTITION is not set
> +# CONFIG_SUN_PARTITION is not set
> +# CONFIG_KARMA_PARTITION is not set
> +# CONFIG_EFI_PARTITION is not set
> +# CONFIG_SYSV68_PARTITION is not set
> +CONFIG_NLS=m
> +CONFIG_NLS_DEFAULT="iso8859-1"
> +CONFIG_NLS_CODEPAGE_437=m
> +CONFIG_NLS_CODEPAGE_737=m
> +CONFIG_NLS_CODEPAGE_775=m
> +CONFIG_NLS_CODEPAGE_850=m
> +CONFIG_NLS_CODEPAGE_852=m
> +CONFIG_NLS_CODEPAGE_855=m
> +CONFIG_NLS_CODEPAGE_857=m
> +CONFIG_NLS_CODEPAGE_860=m
> +CONFIG_NLS_CODEPAGE_861=m
> +CONFIG_NLS_CODEPAGE_862=m
> +CONFIG_NLS_CODEPAGE_863=m
> +CONFIG_NLS_CODEPAGE_864=m
> +CONFIG_NLS_CODEPAGE_865=m
> +CONFIG_NLS_CODEPAGE_866=m
> +CONFIG_NLS_CODEPAGE_869=m
> +CONFIG_NLS_CODEPAGE_936=m
> +CONFIG_NLS_CODEPAGE_950=m
> +CONFIG_NLS_CODEPAGE_932=m
> +CONFIG_NLS_CODEPAGE_949=m
> +CONFIG_NLS_CODEPAGE_874=m
> +CONFIG_NLS_ISO8859_8=m
> +CONFIG_NLS_CODEPAGE_1250=m
> +CONFIG_NLS_CODEPAGE_1251=m
> +CONFIG_NLS_ASCII=m
> +CONFIG_NLS_ISO8859_1=m
> +CONFIG_NLS_ISO8859_2=m
> +CONFIG_NLS_ISO8859_3=m
> +CONFIG_NLS_ISO8859_4=m
> +CONFIG_NLS_ISO8859_5=m
> +CONFIG_NLS_ISO8859_6=m
> +CONFIG_NLS_ISO8859_7=m
> +CONFIG_NLS_ISO8859_9=m
> +CONFIG_NLS_ISO8859_13=m
> +CONFIG_NLS_ISO8859_14=m
> +CONFIG_NLS_ISO8859_15=m
> +CONFIG_NLS_KOI8_R=m
> +CONFIG_NLS_KOI8_U=m
> +CONFIG_NLS_UTF8=m
> +# CONFIG_DLM is not set
> +
> +#
> +# Kernel hacking
> +#
> +CONFIG_PRINTK_TIME=y
> +CONFIG_ENABLE_WARN_DEPRECATED=y
> +CONFIG_ENABLE_MUST_CHECK=y
> +CONFIG_FRAME_WARN=1024
> +CONFIG_MAGIC_SYSRQ=y
> +CONFIG_STRIP_ASM_SYMS=y
> +# CONFIG_UNUSED_SYMBOLS is not set
> +CONFIG_DEBUG_FS=y
> +# CONFIG_HEADERS_CHECK is not set
> +CONFIG_DEBUG_KERNEL=y
> +# CONFIG_DEBUG_SHIRQ is not set
> +CONFIG_DETECT_SOFTLOCKUP=y
> +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
> +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
> +CONFIG_DETECT_HUNG_TASK=y
> +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
> +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
> +CONFIG_SCHED_DEBUG=y
> +# CONFIG_SCHEDSTATS is not set
> +CONFIG_TIMER_STATS=y
> +# CONFIG_DEBUG_OBJECTS is not set
> +# CONFIG_SLUB_DEBUG_ON is not set
> +# CONFIG_SLUB_STATS is not set
> +# CONFIG_DEBUG_KMEMLEAK is not set
> +CONFIG_DEBUG_RT_MUTEXES=y
> +CONFIG_DEBUG_PI_LIST=y
> +# CONFIG_RT_MUTEX_TESTER is not set
> +CONFIG_DEBUG_SPINLOCK=y
> +CONFIG_DEBUG_MUTEXES=y
> +CONFIG_DEBUG_LOCK_ALLOC=y
> +CONFIG_PROVE_LOCKING=y
> +# CONFIG_PROVE_RCU is not set
> +CONFIG_LOCKDEP=y
> +# CONFIG_LOCK_STAT is not set
> +# CONFIG_DEBUG_LOCKDEP is not set
> +CONFIG_TRACE_IRQFLAGS=y
> +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> +CONFIG_STACKTRACE=y
> +# CONFIG_DEBUG_KOBJECT is not set
> +CONFIG_DEBUG_BUGVERBOSE=y
> +CONFIG_DEBUG_INFO=y
> +# CONFIG_DEBUG_VM is not set
> +# CONFIG_DEBUG_WRITECOUNT is not set
> +CONFIG_DEBUG_MEMORY_INIT=y
> +# CONFIG_DEBUG_LIST is not set
> +# CONFIG_DEBUG_SG is not set
> +# CONFIG_DEBUG_NOTIFIERS is not set
> +# CONFIG_DEBUG_CREDENTIALS is not set
> +# CONFIG_BOOT_PRINTK_DELAY is not set
> +# CONFIG_RCU_TORTURE_TEST is not set
> +# CONFIG_KPROBES_SANITY_TEST is not set
> +# CONFIG_BACKTRACE_SELF_TEST is not set
> +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
> +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
> +# CONFIG_LKDTM is not set
> +# CONFIG_FAULT_INJECTION is not set
> +# CONFIG_LATENCYTOP is not set
> +CONFIG_SYSCTL_SYSCALL_CHECK=y
> +# CONFIG_PAGE_POISONING is not set
> +CONFIG_HAVE_FUNCTION_TRACER=y
> +CONFIG_TRACING_SUPPORT=y
> +CONFIG_FTRACE=y
> +# CONFIG_FUNCTION_TRACER is not set
> +# CONFIG_IRQSOFF_TRACER is not set
> +# CONFIG_SCHED_TRACER is not set
> +# CONFIG_ENABLE_DEFAULT_TRACERS is not set
> +# CONFIG_BOOT_TRACER is not set
> +CONFIG_BRANCH_PROFILE_NONE=y
> +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
> +# CONFIG_PROFILE_ALL_BRANCHES is not set
> +# CONFIG_STACK_TRACER is not set
> +# CONFIG_KMEMTRACE is not set
> +# CONFIG_WORKQUEUE_TRACER is not set
> +# CONFIG_BLK_DEV_IO_TRACE is not set
> +# CONFIG_DYNAMIC_DEBUG is not set
> +# CONFIG_ATOMIC64_SELFTEST is not set
> +# CONFIG_SAMPLES is not set
> +CONFIG_HAVE_ARCH_KGDB=y
> +# CONFIG_KGDB is not set
> +CONFIG_ARM_UNWIND=y
> +CONFIG_DEBUG_USER=y
> +CONFIG_DEBUG_ERRORS=y
> +# CONFIG_DEBUG_STACK_USAGE is not set
> +CONFIG_DEBUG_LL=y
> +# CONFIG_EARLY_PRINTK is not set
> +# CONFIG_DEBUG_ICEDCC is not set
> +# CONFIG_OC_ETM is not set
> +
> +#
> +# Security options
> +#
> +CONFIG_KEYS=y
> +CONFIG_KEYS_DEBUG_PROC_KEYS=y
> +CONFIG_SECURITY=y
> +# CONFIG_SECURITYFS is not set
> +# CONFIG_SECURITY_NETWORK is not set
> +# CONFIG_SECURITY_PATH is not set
> +# CONFIG_SECURITY_TOMOYO is not set
> +# CONFIG_IMA is not set
> +# CONFIG_DEFAULT_SECURITY_SELINUX is not set
> +# CONFIG_DEFAULT_SECURITY_SMACK is not set
> +# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
> +CONFIG_DEFAULT_SECURITY_DAC=y
> +CONFIG_DEFAULT_SECURITY=""
> +CONFIG_CRYPTO=y
> +
> +#
> +# Crypto core or helper
> +#
> +# CONFIG_CRYPTO_FIPS is not set
> +CONFIG_CRYPTO_ALGAPI=y
> +CONFIG_CRYPTO_ALGAPI2=y
> +CONFIG_CRYPTO_AEAD=m
> +CONFIG_CRYPTO_AEAD2=y
> +CONFIG_CRYPTO_BLKCIPHER=y
> +CONFIG_CRYPTO_BLKCIPHER2=y
> +CONFIG_CRYPTO_HASH=y
> +CONFIG_CRYPTO_HASH2=y
> +CONFIG_CRYPTO_RNG=m
> +CONFIG_CRYPTO_RNG2=y
> +CONFIG_CRYPTO_PCOMP=y
> +CONFIG_CRYPTO_MANAGER=y
> +CONFIG_CRYPTO_MANAGER2=y
> +CONFIG_CRYPTO_GF128MUL=m
> +CONFIG_CRYPTO_NULL=m
> +CONFIG_CRYPTO_WORKQUEUE=y
> +CONFIG_CRYPTO_CRYPTD=m
> +CONFIG_CRYPTO_AUTHENC=m
> +CONFIG_CRYPTO_TEST=m
> +
> +#
> +# Authenticated Encryption with Associated Data
> +#
> +# CONFIG_CRYPTO_CCM is not set
> +# CONFIG_CRYPTO_GCM is not set
> +# CONFIG_CRYPTO_SEQIV is not set
> +
> +#
> +# Block modes
> +#
> +CONFIG_CRYPTO_CBC=y
> +# CONFIG_CRYPTO_CTR is not set
> +# CONFIG_CRYPTO_CTS is not set
> +CONFIG_CRYPTO_ECB=y
> +CONFIG_CRYPTO_LRW=m
> +CONFIG_CRYPTO_PCBC=m
> +CONFIG_CRYPTO_XTS=m
> +
> +#
> +# Hash modes
> +#
> +CONFIG_CRYPTO_HMAC=m
> +CONFIG_CRYPTO_XCBC=m
> +CONFIG_CRYPTO_VMAC=m
> +
> +#
> +# Digest
> +#
> +CONFIG_CRYPTO_CRC32C=m
> +CONFIG_CRYPTO_GHASH=m
> +CONFIG_CRYPTO_MD4=m
> +CONFIG_CRYPTO_MD5=y
> +CONFIG_CRYPTO_MICHAEL_MIC=y
> +# CONFIG_CRYPTO_RMD128 is not set
> +# CONFIG_CRYPTO_RMD160 is not set
> +# CONFIG_CRYPTO_RMD256 is not set
> +# CONFIG_CRYPTO_RMD320 is not set
> +CONFIG_CRYPTO_SHA1=m
> +CONFIG_CRYPTO_SHA256=m
> +CONFIG_CRYPTO_SHA512=m
> +CONFIG_CRYPTO_TGR192=m
> +# CONFIG_CRYPTO_WP512 is not set
> +
> +#
> +# Ciphers
> +#
> +CONFIG_CRYPTO_AES=y
> +# CONFIG_CRYPTO_ANUBIS is not set
> +CONFIG_CRYPTO_ARC4=y
> +CONFIG_CRYPTO_BLOWFISH=m
> +# CONFIG_CRYPTO_CAMELLIA is not set
> +CONFIG_CRYPTO_CAST5=m
> +CONFIG_CRYPTO_CAST6=m
> +CONFIG_CRYPTO_DES=y
> +CONFIG_CRYPTO_FCRYPT=m
> +CONFIG_CRYPTO_KHAZAD=m
> +# CONFIG_CRYPTO_SALSA20 is not set
> +CONFIG_CRYPTO_SEED=m
> +CONFIG_CRYPTO_SERPENT=m
> +CONFIG_CRYPTO_TEA=m
> +CONFIG_CRYPTO_TWOFISH=m
> +CONFIG_CRYPTO_TWOFISH_COMMON=m
> +
> +#
> +# Compression
> +#
> +CONFIG_CRYPTO_DEFLATE=m
> +# CONFIG_CRYPTO_ZLIB is not set
> +# CONFIG_CRYPTO_LZO is not set
> +
> +#
> +# Random Number Generation
> +#
> +CONFIG_CRYPTO_ANSI_CPRNG=m
> +CONFIG_CRYPTO_HW=y
> +# CONFIG_CRYPTO_DEV_HIFN_795X is not set
> +# CONFIG_BINARY_PRINTF is not set
> +
> +#
> +# Library routines
> +#
> +CONFIG_BITREVERSE=y
> +CONFIG_GENERIC_FIND_LAST_BIT=y
> +CONFIG_CRC_CCITT=m
> +CONFIG_CRC16=m
> +CONFIG_CRC_T10DIF=m
> +CONFIG_CRC_ITU_T=y
> +CONFIG_CRC32=y
> +CONFIG_CRC7=y
> +CONFIG_LIBCRC32C=m
> +CONFIG_ZLIB_INFLATE=y
> +CONFIG_ZLIB_DEFLATE=y
> +CONFIG_LZO_COMPRESS=y
> +CONFIG_LZO_DECOMPRESS=y
> +CONFIG_DECOMPRESS_GZIP=y
> +CONFIG_DECOMPRESS_BZIP2=y
> +CONFIG_DECOMPRESS_LZMA=y
> +CONFIG_REED_SOLOMON=y
> +CONFIG_REED_SOLOMON_DEC16=y
> +CONFIG_TEXTSEARCH=y
> +CONFIG_TEXTSEARCH_KMP=m
> +CONFIG_TEXTSEARCH_BM=m
> +CONFIG_TEXTSEARCH_FSM=m
> +CONFIG_HAS_IOMEM=y
> +CONFIG_HAS_IOPORT=y
> +CONFIG_HAS_DMA=y
> +CONFIG_NLATTR=y
> +CONFIG_GENERIC_ATOMIC64=y
> diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig
> deleted file mode 100644
> index 1e8f5a2..0000000
> --- a/arch/arm/configs/trizeps4_defconfig
> +++ /dev/null
> @@ -1,1704 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.21
> -# Mon Apr 30 21:23:20 2007
> -#
> -CONFIG_ARM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_MMU=y
> -# CONFIG_NO_IOPORT is not set
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -# CONFIG_ARCH_HAS_ILOG2_U32 is not set
> -# CONFIG_ARCH_HAS_ILOG2_U64 is not set
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ZONE_DMA=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -
> -#
> -# Code maturity level options
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_LOCK_KERNEL=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -
> -#
> -# General setup
> -#
> -CONFIG_LOCALVERSION=""
> -CONFIG_LOCALVERSION_AUTO=y
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -# CONFIG_IPC_NS is not set
> -CONFIG_SYSVIPC_SYSCTL=y
> -CONFIG_POSIX_MQUEUE=y
> -CONFIG_BSD_PROCESS_ACCT=y
> -CONFIG_BSD_PROCESS_ACCT_V3=y
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_UTS_NS is not set
> -# CONFIG_AUDIT is not set
> -CONFIG_IKCONFIG=y
> -CONFIG_IKCONFIG_PROC=y
> -CONFIG_SYSFS_DEPRECATED=y
> -# CONFIG_RELAY is not set
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_INITRAMFS_SOURCE=""
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -CONFIG_EMBEDDED=y
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -CONFIG_KALLSYMS_EXTRA_PASS=y
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_EPOLL=y
> -CONFIG_SHMEM=y
> -CONFIG_SLAB=y
> -CONFIG_VM_EVENT_COUNTERS=y
> -CONFIG_RT_MUTEXES=y
> -# CONFIG_TINY_SHMEM is not set
> -CONFIG_BASE_SMALL=0
> -# CONFIG_SLOB is not set
> -
> -#
> -# Loadable module support
> -#
> -CONFIG_MODULES=y
> -CONFIG_MODULE_UNLOAD=y
> -CONFIG_MODULE_FORCE_UNLOAD=y
> -CONFIG_MODVERSIONS=y
> -CONFIG_MODULE_SRCVERSION_ALL=y
> -CONFIG_KMOD=y
> -
> -#
> -# Block layer
> -#
> -CONFIG_BLOCK=y
> -CONFIG_LBD=y
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -CONFIG_LSF=y
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_AS=y
> -CONFIG_IOSCHED_DEADLINE=y
> -CONFIG_IOSCHED_CFQ=y
> -CONFIG_DEFAULT_AS=y
> -# CONFIG_DEFAULT_DEADLINE is not set
> -# CONFIG_DEFAULT_CFQ is not set
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="anticipatory"
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS7500 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_CO285 is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_OMAP is not set
> -
> -#
> -# Intel PXA2xx Implementations
> -#
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -CONFIG_TRIZEPS_PXA=y
> -CONFIG_MACH_TRIZEPS4=y
> -CONFIG_MACH_TRIZEPS4_CONXS=y
> -# CONFIG_MACH_TRIZEPS4_ANY is not set
> -CONFIG_PXA27x=y
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -# CONFIG_OUTER_CACHE is not set
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -
> -#
> -# Bus support
> -#
> -
> -#
> -# PCCARD (PCMCIA/CardBus) support
> -#
> -CONFIG_PCCARD=y
> -# CONFIG_PCMCIA_DEBUG is not set
> -CONFIG_PCMCIA=y
> -# CONFIG_PCMCIA_LOAD_CIS is not set
> -CONFIG_PCMCIA_IOCTL=y
> -
> -#
> -# PC-card bridges
> -#
> -CONFIG_PCMCIA_PXA2XX=y
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_PREEMPT=y
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -# CONFIG_SPARSEMEM_STATIC is not set
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_RESOURCES_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=1
> -CONFIG_LEDS=y
> -CONFIG_LEDS_TIMER=y
> -CONFIG_LEDS_CPU=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0
> -CONFIG_ZBOOT_ROM_BSS=0
> -CONFIG_CMDLINE="root=fe01 console=ttyS0,38400n8 loglevel=5"
> -# CONFIG_XIP_KERNEL is not set
> -# CONFIG_KEXEC is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -CONFIG_FPE_NWFPE_XP=y
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -CONFIG_PM=y
> -# CONFIG_PM_LEGACY is not set
> -# CONFIG_PM_DEBUG is not set
> -# CONFIG_PM_SYSFS_DEPRECATED is not set
> -# CONFIG_APM_EMULATION is not set
> -
> -#
> -# Networking
> -#
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_PACKET=y
> -CONFIG_PACKET_MMAP=y
> -CONFIG_UNIX=y
> -CONFIG_XFRM=y
> -CONFIG_XFRM_USER=m
> -# CONFIG_XFRM_SUB_POLICY is not set
> -# CONFIG_XFRM_MIGRATE is not set
> -CONFIG_NET_KEY=y
> -# CONFIG_NET_KEY_MIGRATE is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -CONFIG_IP_PNP_BOOTP=y
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -CONFIG_INET_XFRM_MODE_TRANSPORT=y
> -CONFIG_INET_XFRM_MODE_TUNNEL=y
> -CONFIG_INET_XFRM_MODE_BEET=y
> -CONFIG_INET_DIAG=y
> -CONFIG_INET_TCP_DIAG=y
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -
> -#
> -# IP: Virtual Server Configuration
> -#
> -# CONFIG_IP_VS is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_INET6_XFRM_TUNNEL is not set
> -# CONFIG_INET6_TUNNEL is not set
> -# CONFIG_NETLABEL is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -CONFIG_NETFILTER=y
> -# CONFIG_NETFILTER_DEBUG is not set
> -
> -#
> -# Core Netfilter Configuration
> -#
> -# CONFIG_NETFILTER_NETLINK is not set
> -# CONFIG_NF_CONNTRACK_ENABLED is not set
> -# CONFIG_NF_CONNTRACK is not set
> -# CONFIG_NETFILTER_XTABLES is not set
> -
> -#
> -# IP: Netfilter Configuration
> -#
> -CONFIG_IP_NF_QUEUE=m
> -# CONFIG_IP_NF_IPTABLES is not set
> -# CONFIG_IP_NF_ARPTABLES is not set
> -
> -#
> -# DCCP Configuration (EXPERIMENTAL)
> -#
> -# CONFIG_IP_DCCP is not set
> -
> -#
> -# SCTP Configuration (EXPERIMENTAL)
> -#
> -# CONFIG_IP_SCTP is not set
> -
> -#
> -# TIPC Configuration (EXPERIMENTAL)
> -#
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -CONFIG_VLAN_8021Q=m
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -
> -#
> -# QoS and/or fair queueing
> -#
> -# CONFIG_NET_SCHED is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -CONFIG_IRDA=m
> -
> -#
> -# IrDA protocols
> -#
> -CONFIG_IRLAN=m
> -CONFIG_IRNET=m
> -CONFIG_IRCOMM=m
> -CONFIG_IRDA_ULTRA=y
> -
> -#
> -# IrDA options
> -#
> -CONFIG_IRDA_CACHE_LAST_LSAP=y
> -CONFIG_IRDA_FAST_RR=y
> -# CONFIG_IRDA_DEBUG is not set
> -
> -#
> -# Infrared-port device drivers
> -#
> -
> -#
> -# SIR device drivers
> -#
> -CONFIG_IRTTY_SIR=m
> -
> -#
> -# Dongle support
> -#
> -# CONFIG_DONGLE is not set
> -
> -#
> -# Old SIR device drivers
> -#
> -# CONFIG_IRPORT_SIR is not set
> -
> -#
> -# Old Serial dongle support
> -#
> -
> -#
> -# FIR device drivers
> -#
> -# CONFIG_USB_IRDA is not set
> -# CONFIG_SIGMATEL_FIR is not set
> -# CONFIG_PXA_FICP is not set
> -# CONFIG_MCS_FIR is not set
> -CONFIG_BT=m
> -CONFIG_BT_L2CAP=m
> -CONFIG_BT_SCO=m
> -CONFIG_BT_RFCOMM=m
> -CONFIG_BT_RFCOMM_TTY=y
> -CONFIG_BT_BNEP=m
> -CONFIG_BT_BNEP_MC_FILTER=y
> -CONFIG_BT_BNEP_PROTO_FILTER=y
> -CONFIG_BT_HIDP=m
> -
> -#
> -# Bluetooth device drivers
> -#
> -# CONFIG_BT_HCIUSB is not set
> -# CONFIG_BT_HCIUART is not set
> -# CONFIG_BT_HCIBCM203X is not set
> -# CONFIG_BT_HCIBPA10X is not set
> -# CONFIG_BT_HCIBFUSB is not set
> -# CONFIG_BT_HCIDTL1 is not set
> -# CONFIG_BT_HCIBT3C is not set
> -# CONFIG_BT_HCIBLUECARD is not set
> -# CONFIG_BT_HCIBTUART is not set
> -# CONFIG_BT_HCIVHCI is not set
> -# CONFIG_AF_RXRPC is not set
> -
> -#
> -# Wireless
> -#
> -CONFIG_CFG80211=y
> -CONFIG_WIRELESS_EXT=y
> -CONFIG_IEEE80211=y
> -# CONFIG_IEEE80211_DEBUG is not set
> -CONFIG_IEEE80211_CRYPT_WEP=y
> -CONFIG_IEEE80211_CRYPT_CCMP=m
> -CONFIG_IEEE80211_CRYPT_TKIP=m
> -CONFIG_IEEE80211_SOFTMAC=m
> -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=y
> -# CONFIG_SYS_HYPERVISOR is not set
> -
> -#
> -# Connector - unified userspace <-> kernelspace linker
> -#
> -CONFIG_CONNECTOR=y
> -CONFIG_PROC_EVENTS=y
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -CONFIG_MTD_CONCAT=y
> -CONFIG_MTD_PARTITIONS=y
> -CONFIG_MTD_REDBOOT_PARTS=y
> -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
> -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
> -CONFIG_MTD_REDBOOT_PARTS_READONLY=y
> -# CONFIG_MTD_CMDLINE_PARTS is not set
> -# CONFIG_MTD_AFS_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -CONFIG_MTD_BLKDEVS=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_JEDECPROBE=y
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -# CONFIG_MTD_CFI_NOSWAP is not set
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -CONFIG_MTD_CFI_LE_BYTE_SWAP=y
> -CONFIG_MTD_CFI_GEOMETRY=y
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -# CONFIG_MTD_OTP is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_CFI_AMDSTD=y
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_OBSOLETE_CHIPS is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -CONFIG_MTD_COMPLEX_MAPPINGS=y
> -CONFIG_MTD_PHYSMAP=y
> -CONFIG_MTD_PHYSMAP_START=0x0
> -CONFIG_MTD_PHYSMAP_LEN=0x0
> -CONFIG_MTD_PHYSMAP_BANKWIDTH=2
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_IMPA7 is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -CONFIG_MTD_BLOCK2MTD=y
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -CONFIG_MTD_DOC2000=y
> -CONFIG_MTD_DOC2001=y
> -CONFIG_MTD_DOC2001PLUS=y
> -CONFIG_MTD_DOCPROBE=y
> -CONFIG_MTD_DOCECC=y
> -CONFIG_MTD_DOCPROBE_ADVANCED=y
> -CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000
> -CONFIG_MTD_DOCPROBE_HIGH=y
> -# CONFIG_MTD_DOCPROBE_55AA is not set
> -CONFIG_MTD_NAND=y
> -# CONFIG_MTD_NAND_VERIFY_WRITE is not set
> -# CONFIG_MTD_NAND_ECC_SMC is not set
> -# CONFIG_MTD_NAND_MUSEUM_IDS is not set
> -# CONFIG_MTD_NAND_H1900 is not set
> -CONFIG_MTD_NAND_IDS=y
> -CONFIG_MTD_NAND_DISKONCHIP=y
> -CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y
> -CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000
> -CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y
> -CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y
> -# CONFIG_MTD_NAND_SHARPSL is not set
> -# CONFIG_MTD_NAND_NANDSIM is not set
> -CONFIG_MTD_ONENAND=y
> -# CONFIG_MTD_ONENAND_VERIFY_WRITE is not set
> -# CONFIG_MTD_ONENAND_GENERIC is not set
> -# CONFIG_MTD_ONENAND_OTP is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -
> -#
> -# Parallel port support
> -#
> -# CONFIG_PARPORT is not set
> -
> -#
> -# Plug and Play support
> -#
> -# CONFIG_PNPACPI is not set
> -
> -#
> -# Block devices
> -#
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -CONFIG_BLK_DEV_LOOP=y
> -CONFIG_BLK_DEV_CRYPTOLOOP=m
> -CONFIG_BLK_DEV_NBD=y
> -# CONFIG_BLK_DEV_UB is not set
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_COUNT=8
> -CONFIG_BLK_DEV_RAM_SIZE=4096
> -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -
> -#
> -# ATA/ATAPI/MFM/RLL support
> -#
> -CONFIG_IDE=y
> -CONFIG_IDE_MAX_HWIFS=4
> -CONFIG_BLK_DEV_IDE=y
> -
> -#
> -# Please see Documentation/ide.txt for help/info on IDE drives
> -#
> -# CONFIG_BLK_DEV_IDE_SATA is not set
> -CONFIG_BLK_DEV_IDEDISK=y
> -CONFIG_IDEDISK_MULTI_MODE=y
> -CONFIG_BLK_DEV_IDECS=m
> -# CONFIG_BLK_DEV_IDECD is not set
> -# CONFIG_BLK_DEV_IDETAPE is not set
> -# CONFIG_BLK_DEV_IDEFLOPPY is not set
> -# CONFIG_BLK_DEV_IDESCSI is not set
> -# CONFIG_IDE_TASK_IOCTL is not set
> -
> -#
> -# IDE chipset support/bugfixes
> -#
> -CONFIG_IDE_GENERIC=y
> -# CONFIG_IDE_ARM is not set
> -# CONFIG_BLK_DEV_IDEDMA is not set
> -# CONFIG_BLK_DEV_HD is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -CONFIG_SCSI=y
> -# CONFIG_SCSI_TGT is not set
> -# CONFIG_SCSI_NETLINK is not set
> -CONFIG_SCSI_PROC_FS=y
> -
> -#
> -# SCSI support type (disk, tape, CD-ROM)
> -#
> -CONFIG_BLK_DEV_SD=y
> -# CONFIG_CHR_DEV_ST is not set
> -# CONFIG_CHR_DEV_OSST is not set
> -# CONFIG_BLK_DEV_SR is not set
> -CONFIG_CHR_DEV_SG=y
> -# CONFIG_CHR_DEV_SCH is not set
> -
> -#
> -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
> -#
> -CONFIG_SCSI_MULTI_LUN=y
> -# CONFIG_SCSI_CONSTANTS is not set
> -# CONFIG_SCSI_LOGGING is not set
> -# CONFIG_SCSI_SCAN_ASYNC is not set
> -
> -#
> -# SCSI Transports
> -#
> -# CONFIG_SCSI_SPI_ATTRS is not set
> -# CONFIG_SCSI_FC_ATTRS is not set
> -# CONFIG_SCSI_ISCSI_ATTRS is not set
> -# CONFIG_SCSI_SAS_ATTRS is not set
> -# CONFIG_SCSI_SAS_LIBSAS is not set
> -
> -#
> -# SCSI low-level drivers
> -#
> -# CONFIG_ISCSI_TCP is not set
> -# CONFIG_SCSI_DEBUG is not set
> -# CONFIG_SCSI_ESP_CORE is not set
> -
> -#
> -# PCMCIA SCSI adapter support
> -#
> -# CONFIG_PCMCIA_AHA152X is not set
> -# CONFIG_PCMCIA_FDOMAIN is not set
> -# CONFIG_PCMCIA_NINJA_SCSI is not set
> -# CONFIG_PCMCIA_QLOGIC is not set
> -# CONFIG_PCMCIA_SYM53C500 is not set
> -
> -#
> -# Serial ATA (prod) and Parallel ATA (experimental) drivers
> -#
> -CONFIG_ATA=m
> -# CONFIG_ATA_NONSTANDARD is not set
> -CONFIG_PATA_PCMCIA=m
> -CONFIG_PATA_PLATFORM=m
> -
> -#
> -# Multi-device support (RAID and LVM)
> -#
> -# CONFIG_MD is not set
> -
> -#
> -# Fusion MPT device support
> -#
> -# CONFIG_FUSION is not set
> -
> -#
> -# IEEE 1394 (FireWire) support
> -#
> -
> -#
> -# I2O device support
> -#
> -
> -#
> -# Network device support
> -#
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -
> -#
> -# PHY device support
> -#
> -CONFIG_PHYLIB=y
> -
> -#
> -# MII PHY device drivers
> -#
> -# CONFIG_MARVELL_PHY is not set
> -# CONFIG_DAVICOM_PHY is not set
> -# CONFIG_QSEMI_PHY is not set
> -# CONFIG_LXT_PHY is not set
> -# CONFIG_CICADA_PHY is not set
> -# CONFIG_VITESSE_PHY is not set
> -# CONFIG_SMSC_PHY is not set
> -# CONFIG_BROADCOM_PHY is not set
> -# CONFIG_FIXED_PHY is not set
> -
> -#
> -# Ethernet (10 or 100Mbit)
> -#
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=y
> -# CONFIG_SMC91X is not set
> -CONFIG_DM9000=y
> -# CONFIG_SMC911X is not set
> -
> -#
> -# Ethernet (1000 Mbit)
> -#
> -
> -#
> -# Ethernet (10000 Mbit)
> -#
> -
> -#
> -# Token Ring devices
> -#
> -
> -#
> -# Wireless LAN
> -#
> -# CONFIG_WLAN_PRE80211 is not set
> -CONFIG_WLAN_80211=y
> -# CONFIG_PCMCIA_RAYCS is not set
> -CONFIG_HERMES=y
> -# CONFIG_ATMEL is not set
> -CONFIG_PCMCIA_HERMES=y
> -CONFIG_PCMCIA_SPECTRUM=y
> -# CONFIG_AIRO_CS is not set
> -# CONFIG_PCMCIA_WL3501 is not set
> -# CONFIG_USB_ZD1201 is not set
> -CONFIG_HOSTAP=y
> -CONFIG_HOSTAP_FIRMWARE=y
> -CONFIG_HOSTAP_FIRMWARE_NVRAM=y
> -CONFIG_HOSTAP_CS=y
> -# CONFIG_ZD1211RW is not set
> -
> -#
> -# PCMCIA network device support
> -#
> -# CONFIG_NET_PCMCIA is not set
> -
> -#
> -# Wan interfaces
> -#
> -# CONFIG_WAN is not set
> -CONFIG_PPP=m
> -CONFIG_PPP_MULTILINK=y
> -CONFIG_PPP_FILTER=y
> -CONFIG_PPP_ASYNC=m
> -CONFIG_PPP_SYNC_TTY=m
> -CONFIG_PPP_DEFLATE=m
> -CONFIG_PPP_BSDCOMP=m
> -CONFIG_PPP_MPPE=m
> -# CONFIG_PPPOE is not set
> -# CONFIG_SLIP is not set
> -CONFIG_SLHC=m
> -# CONFIG_SHAPER is not set
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -
> -#
> -# ISDN subsystem
> -#
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -CONFIG_INPUT_MOUSEDEV_PSAUX=y
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=640
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480
> -# CONFIG_INPUT_JOYDEV is not set
> -CONFIG_INPUT_TSDEV=y
> -CONFIG_INPUT_TSDEV_SCREEN_X=640
> -CONFIG_INPUT_TSDEV_SCREEN_Y=480
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -CONFIG_INPUT_KEYBOARD=y
> -CONFIG_KEYBOARD_ATKBD=m
> -# CONFIG_KEYBOARD_SUNKBD is not set
> -# CONFIG_KEYBOARD_LKKBD is not set
> -# CONFIG_KEYBOARD_XTKBD is not set
> -# CONFIG_KEYBOARD_NEWTON is not set
> -# CONFIG_KEYBOARD_STOWAWAY is not set
> -# CONFIG_KEYBOARD_GPIO is not set
> -CONFIG_INPUT_MOUSE=y
> -# CONFIG_MOUSE_PS2 is not set
> -CONFIG_MOUSE_SERIAL=m
> -# CONFIG_MOUSE_VSXXXAA is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -# CONFIG_TOUCHSCREEN_GUNZE is not set
> -# CONFIG_TOUCHSCREEN_ELO is not set
> -# CONFIG_TOUCHSCREEN_MTOUCH is not set
> -# CONFIG_TOUCHSCREEN_MK712 is not set
> -# CONFIG_TOUCHSCREEN_PENMOUNT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
> -CONFIG_TOUCHSCREEN_UCB1400=y
> -CONFIG_INPUT_MISC=y
> -CONFIG_INPUT_UINPUT=m
> -
> -#
> -# Hardware I/O ports
> -#
> -CONFIG_SERIO=y
> -CONFIG_SERIO_SERPORT=y
> -CONFIG_SERIO_LIBPS2=y
> -# CONFIG_SERIO_RAW is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=256
> -
> -#
> -# IPMI
> -#
> -# CONFIG_IPMI_HANDLER is not set
> -
> -#
> -# Watchdog Cards
> -#
> -CONFIG_WATCHDOG=y
> -# CONFIG_WATCHDOG_NOWAYOUT is not set
> -
> -#
> -# Watchdog Device Drivers
> -#
> -# CONFIG_SOFT_WATCHDOG is not set
> -CONFIG_SA1100_WATCHDOG=y
> -
> -#
> -# USB-based Watchdog Cards
> -#
> -# CONFIG_USBPCWATCHDOG is not set
> -CONFIG_HW_RANDOM=y
> -# CONFIG_NVRAM is not set
> -# CONFIG_DTLK is not set
> -# CONFIG_R3964 is not set
> -
> -#
> -# PCMCIA character devices
> -#
> -# CONFIG_SYNCLINK_CS is not set
> -# CONFIG_CARDMAN_4000 is not set
> -# CONFIG_CARDMAN_4040 is not set
> -# CONFIG_RAW_DRIVER is not set
> -
> -#
> -# TPM devices
> -#
> -# CONFIG_TCG_TPM is not set
> -
> -#
> -# I2C support
> -#
> -CONFIG_I2C=y
> -CONFIG_I2C_CHARDEV=y
> -
> -#
> -# I2C Algorithms
> -#
> -# CONFIG_I2C_ALGOBIT is not set
> -# CONFIG_I2C_ALGOPCF is not set
> -# CONFIG_I2C_ALGOPCA is not set
> -
> -#
> -# I2C Hardware Bus support
> -#
> -CONFIG_I2C_PXA=y
> -CONFIG_I2C_PXA_SLAVE=y
> -# CONFIG_I2C_OCORES is not set
> -# CONFIG_I2C_PARPORT_LIGHT is not set
> -# CONFIG_I2C_STUB is not set
> -# CONFIG_I2C_PCA_ISA is not set
> -
> -#
> -# Miscellaneous I2C Chip support
> -#
> -# CONFIG_SENSORS_DS1337 is not set
> -# CONFIG_SENSORS_DS1374 is not set
> -# CONFIG_EEPROM_LEGACY is not set
> -# CONFIG_SENSORS_PCF8574 is not set
> -# CONFIG_SENSORS_PCA9539 is not set
> -# CONFIG_SENSORS_PCF8591 is not set
> -# CONFIG_SENSORS_MAX6875 is not set
> -# CONFIG_I2C_DEBUG_CORE is not set
> -# CONFIG_I2C_DEBUG_ALGO is not set
> -# CONFIG_I2C_DEBUG_BUS is not set
> -# CONFIG_I2C_DEBUG_CHIP is not set
> -
> -#
> -# SPI support
> -#
> -# CONFIG_SPI is not set
> -# CONFIG_SPI_MASTER is not set
> -
> -#
> -# Dallas's 1-wire bus
> -#
> -# CONFIG_W1 is not set
> -
> -#
> -# Hardware Monitoring support
> -#
> -CONFIG_HWMON=y
> -# CONFIG_HWMON_VID is not set
> -# CONFIG_SENSORS_ABITUGURU is not set
> -# CONFIG_SENSORS_ADM1021 is not set
> -# CONFIG_SENSORS_ADM1025 is not set
> -# CONFIG_SENSORS_ADM1026 is not set
> -# CONFIG_SENSORS_ADM1029 is not set
> -# CONFIG_SENSORS_ADM1031 is not set
> -# CONFIG_SENSORS_ADM9240 is not set
> -# CONFIG_SENSORS_ASB100 is not set
> -# CONFIG_SENSORS_ATXP1 is not set
> -# CONFIG_SENSORS_DS1621 is not set
> -# CONFIG_SENSORS_F71805F is not set
> -# CONFIG_SENSORS_FSCHER is not set
> -# CONFIG_SENSORS_FSCPOS is not set
> -# CONFIG_SENSORS_GL518SM is not set
> -# CONFIG_SENSORS_GL520SM is not set
> -# CONFIG_SENSORS_IT87 is not set
> -# CONFIG_SENSORS_LM63 is not set
> -# CONFIG_SENSORS_LM75 is not set
> -# CONFIG_SENSORS_LM77 is not set
> -# CONFIG_SENSORS_LM78 is not set
> -# CONFIG_SENSORS_LM80 is not set
> -# CONFIG_SENSORS_LM83 is not set
> -# CONFIG_SENSORS_LM85 is not set
> -# CONFIG_SENSORS_LM87 is not set
> -# CONFIG_SENSORS_LM90 is not set
> -# CONFIG_SENSORS_LM92 is not set
> -# CONFIG_SENSORS_MAX1619 is not set
> -# CONFIG_SENSORS_PC87360 is not set
> -# CONFIG_SENSORS_PC87427 is not set
> -# CONFIG_SENSORS_SMSC47M1 is not set
> -# CONFIG_SENSORS_SMSC47M192 is not set
> -# CONFIG_SENSORS_SMSC47B397 is not set
> -# CONFIG_SENSORS_VT1211 is not set
> -# CONFIG_SENSORS_W83781D is not set
> -# CONFIG_SENSORS_W83791D is not set
> -# CONFIG_SENSORS_W83792D is not set
> -# CONFIG_SENSORS_W83793 is not set
> -# CONFIG_SENSORS_W83L785TS is not set
> -# CONFIG_SENSORS_W83627HF is not set
> -# CONFIG_SENSORS_W83627EHF is not set
> -# CONFIG_HWMON_DEBUG_CHIP is not set
> -
> -#
> -# Misc devices
> -#
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_SM501 is not set
> -
> -#
> -# LED devices
> -#
> -CONFIG_NEW_LEDS=y
> -# CONFIG_LEDS_CLASS is not set
> -
> -#
> -# LED drivers
> -#
> -
> -#
> -# LED Triggers
> -#
> -CONFIG_LEDS_TRIGGERS=y
> -CONFIG_LEDS_TRIGGER_TIMER=y
> -# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
> -CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> -
> -#
> -# Multimedia devices
> -#
> -# CONFIG_VIDEO_DEV is not set
> -
> -#
> -# Digital Video Broadcasting Devices
> -#
> -# CONFIG_DVB is not set
> -# CONFIG_USB_DABUSB is not set
> -
> -#
> -# Graphics support
> -#
> -CONFIG_BACKLIGHT_LCD_SUPPORT=y
> -CONFIG_BACKLIGHT_CLASS_DEVICE=y
> -CONFIG_LCD_CLASS_DEVICE=y
> -CONFIG_FB=y
> -CONFIG_FIRMWARE_EDID=y
> -# CONFIG_FB_DDC is not set
> -CONFIG_FB_CFB_FILLRECT=y
> -CONFIG_FB_CFB_COPYAREA=y
> -CONFIG_FB_CFB_IMAGEBLIT=y
> -# CONFIG_FB_SVGALIB is not set
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -
> -#
> -# Frame buffer hardware drivers
> -#
> -# CONFIG_FB_S1D13XXX is not set
> -CONFIG_FB_PXA=y
> -# CONFIG_FB_PXA_PARAMETERS is not set
> -# CONFIG_FB_MBX is not set
> -# CONFIG_FB_VIRTUAL is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
> -CONFIG_FONTS=y
> -CONFIG_FONT_8x8=y
> -CONFIG_FONT_8x16=y
> -# CONFIG_FONT_6x11 is not set
> -# CONFIG_FONT_7x14 is not set
> -# CONFIG_FONT_PEARL_8x8 is not set
> -# CONFIG_FONT_ACORN_8x8 is not set
> -# CONFIG_FONT_MINI_4x6 is not set
> -# CONFIG_FONT_SUN8x16 is not set
> -# CONFIG_FONT_SUN12x22 is not set
> -# CONFIG_FONT_10x18 is not set
> -
> -#
> -# Logo configuration
> -#
> -CONFIG_LOGO=y
> -CONFIG_LOGO_LINUX_MONO=y
> -CONFIG_LOGO_LINUX_VGA16=y
> -CONFIG_LOGO_LINUX_CLUT224=y
> -
> -#
> -# Sound
> -#
> -CONFIG_SOUND=y
> -
> -#
> -# Advanced Linux Sound Architecture
> -#
> -CONFIG_SND=y
> -CONFIG_SND_TIMER=y
> -CONFIG_SND_PCM=y
> -CONFIG_SND_HWDEP=m
> -CONFIG_SND_RAWMIDI=m
> -CONFIG_SND_SEQUENCER=y
> -# CONFIG_SND_SEQ_DUMMY is not set
> -CONFIG_SND_OSSEMUL=y
> -CONFIG_SND_MIXER_OSS=y
> -CONFIG_SND_PCM_OSS=y
> -CONFIG_SND_PCM_OSS_PLUGINS=y
> -# CONFIG_SND_SEQUENCER_OSS is not set
> -# CONFIG_SND_DYNAMIC_MINORS is not set
> -CONFIG_SND_SUPPORT_OLD_API=y
> -CONFIG_SND_VERBOSE_PROCFS=y
> -CONFIG_SND_VERBOSE_PRINTK=y
> -CONFIG_SND_DEBUG=y
> -CONFIG_SND_DEBUG_DETECT=y
> -# CONFIG_SND_PCM_XRUN_DEBUG is not set
> -
> -#
> -# Generic devices
> -#
> -CONFIG_SND_AC97_CODEC=y
> -# CONFIG_SND_DUMMY is not set
> -# CONFIG_SND_VIRMIDI is not set
> -# CONFIG_SND_MTPAV is not set
> -# CONFIG_SND_SERIAL_U16550 is not set
> -# CONFIG_SND_MPU401 is not set
> -
> -#
> -# ALSA ARM devices
> -#
> -CONFIG_SND_PXA2XX_PCM=y
> -CONFIG_SND_PXA2XX_AC97=y
> -
> -#
> -# USB devices
> -#
> -CONFIG_SND_USB_AUDIO=m
> -
> -#
> -# PCMCIA devices
> -#
> -# CONFIG_SND_VXPOCKET is not set
> -# CONFIG_SND_PDAUDIOCF is not set
> -
> -#
> -# SoC audio support
> -#
> -# CONFIG_SND_SOC is not set
> -
> -#
> -# Open Sound System
> -#
> -# CONFIG_SOUND_PRIME is not set
> -CONFIG_AC97_BUS=y
> -
> -#
> -# HID Devices
> -#
> -CONFIG_HID=y
> -# CONFIG_HID_DEBUG is not set
> -
> -#
> -# USB Input Devices
> -#
> -# CONFIG_USB_HID is not set
> -
> -#
> -# USB HID Boot Protocol drivers
> -#
> -# CONFIG_USB_KBD is not set
> -# CONFIG_USB_MOUSE is not set
> -
> -#
> -# USB support
> -#
> -CONFIG_USB_ARCH_HAS_HCD=y
> -CONFIG_USB_ARCH_HAS_OHCI=y
> -# CONFIG_USB_ARCH_HAS_EHCI is not set
> -CONFIG_USB=y
> -# CONFIG_USB_DEBUG is not set
> -
> -#
> -# Miscellaneous USB options
> -#
> -CONFIG_USB_DEVICEFS=y
> -# CONFIG_USB_DEVICE_CLASS is not set
> -# CONFIG_USB_DYNAMIC_MINORS is not set
> -# CONFIG_USB_SUSPEND is not set
> -# CONFIG_USB_OTG is not set
> -
> -#
> -# USB Host Controller Drivers
> -#
> -# CONFIG_USB_ISP116X_HCD is not set
> -CONFIG_USB_OHCI_HCD=y
> -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
> -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
> -CONFIG_USB_OHCI_LITTLE_ENDIAN=y
> -# CONFIG_USB_SL811_HCD is not set
> -
> -#
> -# USB Device Class drivers
> -#
> -# CONFIG_USB_ACM is not set
> -# CONFIG_USB_PRINTER is not set
> -
> -#
> -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
> -#
> -
> -#
> -# may also be needed; see USB_STORAGE Help for more information
> -#
> -CONFIG_USB_STORAGE=m
> -# CONFIG_USB_STORAGE_DEBUG is not set
> -# CONFIG_USB_STORAGE_DATAFAB is not set
> -# CONFIG_USB_STORAGE_FREECOM is not set
> -# CONFIG_USB_STORAGE_ISD200 is not set
> -# CONFIG_USB_STORAGE_DPCM is not set
> -# CONFIG_USB_STORAGE_USBAT is not set
> -# CONFIG_USB_STORAGE_SDDR09 is not set
> -# CONFIG_USB_STORAGE_SDDR55 is not set
> -# CONFIG_USB_STORAGE_JUMPSHOT is not set
> -# CONFIG_USB_STORAGE_ALAUDA is not set
> -# CONFIG_USB_STORAGE_KARMA is not set
> -# CONFIG_USB_LIBUSUAL is not set
> -
> -#
> -# USB Input Devices
> -#
> -# CONFIG_USB_AIPTEK is not set
> -# CONFIG_USB_WACOM is not set
> -# CONFIG_USB_ACECAD is not set
> -# CONFIG_USB_KBTAB is not set
> -# CONFIG_USB_POWERMATE is not set
> -# CONFIG_USB_TOUCHSCREEN is not set
> -# CONFIG_USB_YEALINK is not set
> -# CONFIG_USB_XPAD is not set
> -# CONFIG_USB_ATI_REMOTE is not set
> -# CONFIG_USB_ATI_REMOTE2 is not set
> -# CONFIG_USB_KEYSPAN_REMOTE is not set
> -# CONFIG_USB_APPLETOUCH is not set
> -# CONFIG_USB_GTCO is not set
> -
> -#
> -# USB Imaging devices
> -#
> -# CONFIG_USB_MDC800 is not set
> -# CONFIG_USB_MICROTEK is not set
> -
> -#
> -# USB Network Adapters
> -#
> -# CONFIG_USB_CATC is not set
> -# CONFIG_USB_KAWETH is not set
> -# CONFIG_USB_PEGASUS is not set
> -# CONFIG_USB_RTL8150 is not set
> -# CONFIG_USB_USBNET_MII is not set
> -# CONFIG_USB_USBNET is not set
> -# CONFIG_USB_MON is not set
> -
> -#
> -# USB port drivers
> -#
> -
> -#
> -# USB Serial Converter support
> -#
> -CONFIG_USB_SERIAL=m
> -# CONFIG_USB_SERIAL_GENERIC is not set
> -# CONFIG_USB_SERIAL_AIRCABLE is not set
> -# CONFIG_USB_SERIAL_AIRPRIME is not set
> -# CONFIG_USB_SERIAL_ARK3116 is not set
> -# CONFIG_USB_SERIAL_BELKIN is not set
> -# CONFIG_USB_SERIAL_WHITEHEAT is not set
> -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
> -# CONFIG_USB_SERIAL_CP2101 is not set
> -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
> -# CONFIG_USB_SERIAL_EMPEG is not set
> -# CONFIG_USB_SERIAL_FTDI_SIO is not set
> -# CONFIG_USB_SERIAL_FUNSOFT is not set
> -# CONFIG_USB_SERIAL_VISOR is not set
> -# CONFIG_USB_SERIAL_IPAQ is not set
> -# CONFIG_USB_SERIAL_IR is not set
> -# CONFIG_USB_SERIAL_EDGEPORT is not set
> -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
> -# CONFIG_USB_SERIAL_GARMIN is not set
> -# CONFIG_USB_SERIAL_IPW is not set
> -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
> -# CONFIG_USB_SERIAL_KEYSPAN is not set
> -# CONFIG_USB_SERIAL_KLSI is not set
> -# CONFIG_USB_SERIAL_KOBIL_SCT is not set
> -# CONFIG_USB_SERIAL_MCT_U232 is not set
> -# CONFIG_USB_SERIAL_MOS7720 is not set
> -# CONFIG_USB_SERIAL_MOS7840 is not set
> -# CONFIG_USB_SERIAL_NAVMAN is not set
> -# CONFIG_USB_SERIAL_PL2303 is not set
> -# CONFIG_USB_SERIAL_HP4X is not set
> -# CONFIG_USB_SERIAL_SAFE is not set
> -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
> -# CONFIG_USB_SERIAL_TI is not set
> -# CONFIG_USB_SERIAL_CYBERJACK is not set
> -# CONFIG_USB_SERIAL_XIRCOM is not set
> -# CONFIG_USB_SERIAL_OPTION is not set
> -# CONFIG_USB_SERIAL_OMNINET is not set
> -# CONFIG_USB_SERIAL_DEBUG is not set
> -
> -#
> -# USB Miscellaneous drivers
> -#
> -# CONFIG_USB_EMI62 is not set
> -# CONFIG_USB_EMI26 is not set
> -# CONFIG_USB_ADUTUX is not set
> -# CONFIG_USB_AUERSWALD is not set
> -# CONFIG_USB_RIO500 is not set
> -# CONFIG_USB_LEGOTOWER is not set
> -# CONFIG_USB_LCD is not set
> -# CONFIG_USB_BERRY_CHARGE is not set
> -# CONFIG_USB_LED is not set
> -# CONFIG_USB_CYPRESS_CY7C63 is not set
> -# CONFIG_USB_CYTHERM is not set
> -# CONFIG_USB_PHIDGET is not set
> -# CONFIG_USB_IDMOUSE is not set
> -# CONFIG_USB_FTDI_ELAN is not set
> -# CONFIG_USB_APPLEDISPLAY is not set
> -# CONFIG_USB_LD is not set
> -# CONFIG_USB_TRANCEVIBRATOR is not set
> -# CONFIG_USB_IOWARRIOR is not set
> -# CONFIG_USB_TEST is not set
> -
> -#
> -# USB DSL modem support
> -#
> -
> -#
> -# USB Gadget Support
> -#
> -CONFIG_USB_GADGET=m
> -# CONFIG_USB_GADGET_DEBUG_FILES is not set
> -CONFIG_USB_GADGET_SELECTED=y
> -# CONFIG_USB_GADGET_FSL_USB2 is not set
> -# CONFIG_USB_GADGET_NET2280 is not set
> -# CONFIG_USB_GADGET_PXA2XX is not set
> -# CONFIG_USB_GADGET_GOKU is not set
> -# CONFIG_USB_GADGET_LH7A40X is not set
> -# CONFIG_USB_GADGET_OMAP is not set
> -# CONFIG_USB_GADGET_AT91 is not set
> -CONFIG_USB_GADGET_DUMMY_HCD=y
> -CONFIG_USB_DUMMY_HCD=m
> -CONFIG_USB_GADGET_DUALSPEED=y
> -# CONFIG_USB_ZERO is not set
> -# CONFIG_USB_ETH is not set
> -# CONFIG_USB_GADGETFS is not set
> -# CONFIG_USB_FILE_STORAGE is not set
> -# CONFIG_USB_G_SERIAL is not set
> -# CONFIG_USB_MIDI_GADGET is not set
> -
> -#
> -# MMC/SD Card support
> -#
> -CONFIG_MMC=y
> -# CONFIG_MMC_DEBUG is not set
> -CONFIG_MMC_BLOCK=y
> -CONFIG_MMC_PXA=y
> -
> -#
> -# Real Time Clock
> -#
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=y
> -# CONFIG_RTC_HCTOSYS is not set
> -# CONFIG_RTC_DEBUG is not set
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -
> -#
> -# RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_X1205 is not set
> -# CONFIG_RTC_DRV_DS1307 is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_ISL1208 is not set
> -# CONFIG_RTC_DRV_DS1672 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_PCF8563 is not set
> -CONFIG_RTC_DRV_PCF8583=m
> -# CONFIG_RTC_DRV_RS5C372 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -CONFIG_RTC_DRV_SA1100=y
> -# CONFIG_RTC_DRV_TEST is not set
> -# CONFIG_RTC_DRV_V3020 is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -CONFIG_EXT2_FS_XATTR=y
> -CONFIG_EXT2_FS_POSIX_ACL=y
> -CONFIG_EXT2_FS_SECURITY=y
> -# CONFIG_EXT2_FS_XIP is not set
> -CONFIG_EXT3_FS=y
> -CONFIG_EXT3_FS_XATTR=y
> -CONFIG_EXT3_FS_POSIX_ACL=y
> -CONFIG_EXT3_FS_SECURITY=y
> -# CONFIG_EXT4DEV_FS is not set
> -CONFIG_JBD=y
> -# CONFIG_JBD_DEBUG is not set
> -CONFIG_FS_MBCACHE=y
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -CONFIG_FS_POSIX_ACL=y
> -# CONFIG_XFS_FS is not set
> -# CONFIG_GFS2_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -CONFIG_DNOTIFY=y
> -# CONFIG_AUTOFS_FS is not set
> -CONFIG_AUTOFS4_FS=y
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=m
> -CONFIG_MSDOS_FS=m
> -CONFIG_VFAT_FS=m
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -CONFIG_RAMFS=y
> -# CONFIG_CONFIGFS_FS is not set
> -
> -#
> -# Miscellaneous filesystems
> -#
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_ECRYPT_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -# CONFIG_JFFS2_SUMMARY is not set
> -# CONFIG_JFFS2_FS_XATTR is not set
> -CONFIG_JFFS2_COMPRESSION_OPTIONS=y
> -CONFIG_JFFS2_ZLIB=y
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_JFFS2_CMODE_NONE is not set
> -CONFIG_JFFS2_CMODE_PRIORITY=y
> -# CONFIG_JFFS2_CMODE_SIZE is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -
> -#
> -# Network File Systems
> -#
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -# CONFIG_NFS_V3_ACL is not set
> -CONFIG_NFS_V4=y
> -# CONFIG_NFS_DIRECTIO is not set
> -CONFIG_NFSD=y
> -CONFIG_NFSD_V3=y
> -# CONFIG_NFSD_V3_ACL is not set
> -CONFIG_NFSD_V4=y
> -CONFIG_NFSD_TCP=y
> -CONFIG_ROOT_NFS=y
> -CONFIG_LOCKD=y
> -CONFIG_LOCKD_V4=y
> -CONFIG_EXPORTFS=y
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=y
> -CONFIG_SUNRPC_GSS=y
> -CONFIG_RPCSEC_GSS_KRB5=y
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -CONFIG_SMB_FS=m
> -# CONFIG_SMB_NLS_DEFAULT is not set
> -CONFIG_CIFS=m
> -# CONFIG_CIFS_STATS is not set
> -# CONFIG_CIFS_WEAK_PW_HASH is not set
> -# CONFIG_CIFS_XATTR is not set
> -# CONFIG_CIFS_DEBUG2 is not set
> -# CONFIG_CIFS_EXPERIMENTAL is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -# CONFIG_9P_FS is not set
> -
> -#
> -# Partition Types
> -#
> -CONFIG_PARTITION_ADVANCED=y
> -# CONFIG_ACORN_PARTITION is not set
> -# CONFIG_OSF_PARTITION is not set
> -# CONFIG_AMIGA_PARTITION is not set
> -# CONFIG_ATARI_PARTITION is not set
> -# CONFIG_MAC_PARTITION is not set
> -CONFIG_MSDOS_PARTITION=y
> -# CONFIG_BSD_DISKLABEL is not set
> -# CONFIG_MINIX_SUBPARTITION is not set
> -# CONFIG_SOLARIS_X86_PARTITION is not set
> -# CONFIG_UNIXWARE_DISKLABEL is not set
> -CONFIG_LDM_PARTITION=y
> -# CONFIG_LDM_DEBUG is not set
> -# CONFIG_SGI_PARTITION is not set
> -# CONFIG_ULTRIX_PARTITION is not set
> -# CONFIG_SUN_PARTITION is not set
> -# CONFIG_KARMA_PARTITION is not set
> -# CONFIG_EFI_PARTITION is not set
> -
> -#
> -# Native Language Support
> -#
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="iso8859-15"
> -CONFIG_NLS_CODEPAGE_437=y
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -CONFIG_NLS_CODEPAGE_850=y
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -CONFIG_NLS_ASCII=y
> -CONFIG_NLS_ISO8859_1=m
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -CONFIG_NLS_ISO8859_15=m
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -CONFIG_NLS_UTF8=m
> -
> -#
> -# Distributed Lock Manager
> -#
> -# CONFIG_DLM is not set
> -
> -#
> -# Profiling support
> -#
> -# CONFIG_PROFILING is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_MAGIC_SYSRQ=y
> -# CONFIG_UNUSED_SYMBOLS is not set
> -CONFIG_DEBUG_FS=y
> -# CONFIG_HEADERS_CHECK is not set
> -# CONFIG_DEBUG_KERNEL is not set
> -CONFIG_LOG_BUF_SHIFT=14
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -CONFIG_FRAME_POINTER=y
> -CONFIG_DEBUG_USER=y
> -
> -#
> -# Security options
> -#
> -CONFIG_KEYS=y
> -CONFIG_KEYS_DEBUG_PROC_KEYS=y
> -CONFIG_SECURITY=y
> -# CONFIG_SECURITY_NETWORK is not set
> -CONFIG_SECURITY_CAPABILITIES=y
> -# CONFIG_SECURITY_ROOTPLUG is not set
> -
> -#
> -# Cryptographic options
> -#
> -CONFIG_CRYPTO=y
> -CONFIG_CRYPTO_ALGAPI=y
> -CONFIG_CRYPTO_BLKCIPHER=y
> -CONFIG_CRYPTO_MANAGER=y
> -# CONFIG_CRYPTO_HMAC is not set
> -# CONFIG_CRYPTO_XCBC is not set
> -# CONFIG_CRYPTO_NULL is not set
> -# CONFIG_CRYPTO_MD4 is not set
> -CONFIG_CRYPTO_MD5=y
> -CONFIG_CRYPTO_SHA1=m
> -CONFIG_CRYPTO_SHA256=m
> -CONFIG_CRYPTO_SHA512=m
> -# CONFIG_CRYPTO_WP512 is not set
> -# CONFIG_CRYPTO_TGR192 is not set
> -# CONFIG_CRYPTO_GF128MUL is not set
> -CONFIG_CRYPTO_ECB=y
> -CONFIG_CRYPTO_CBC=y
> -CONFIG_CRYPTO_PCBC=m
> -# CONFIG_CRYPTO_LRW is not set
> -CONFIG_CRYPTO_DES=y
> -# CONFIG_CRYPTO_FCRYPT is not set
> -# CONFIG_CRYPTO_BLOWFISH is not set
> -# CONFIG_CRYPTO_TWOFISH is not set
> -# CONFIG_CRYPTO_SERPENT is not set
> -CONFIG_CRYPTO_AES=m
> -# CONFIG_CRYPTO_CAST5 is not set
> -# CONFIG_CRYPTO_CAST6 is not set
> -# CONFIG_CRYPTO_TEA is not set
> -CONFIG_CRYPTO_ARC4=y
> -# CONFIG_CRYPTO_KHAZAD is not set
> -# CONFIG_CRYPTO_ANUBIS is not set
> -CONFIG_CRYPTO_DEFLATE=m
> -CONFIG_CRYPTO_MICHAEL_MIC=m
> -CONFIG_CRYPTO_CRC32C=y
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -# CONFIG_CRYPTO_TEST is not set
> -
> -#
> -# Hardware crypto devices
> -#
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -CONFIG_CRC_CCITT=y
> -CONFIG_CRC16=y
> -CONFIG_CRC32=y
> -CONFIG_LIBCRC32C=y
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_REED_SOLOMON=y
> -CONFIG_REED_SOLOMON_DEC16=y
> -CONFIG_PLIST=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig
> deleted file mode 100644
> index 909887a..0000000
> --- a/arch/arm/configs/viper_defconfig
> +++ /dev/null
> @@ -1,1676 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.27-rc4
> -# Thu Aug 21 17:12:07 2008
> -#
> -CONFIG_ARM=y
> -CONFIG_HAVE_PWM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_MMU=y
> -# CONFIG_NO_IOPORT is not set
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -# CONFIG_ARCH_HAS_ILOG2_U32 is not set
> -# CONFIG_ARCH_HAS_ILOG2_U64 is not set
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ARCH_SUPPORTS_AOUT=y
> -CONFIG_ZONE_DMA=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=""
> -CONFIG_LOCALVERSION_AUTO=y
> -# CONFIG_SWAP is not set
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -# CONFIG_IKCONFIG is not set
> -CONFIG_LOG_BUF_SHIFT=13
> -# CONFIG_CGROUPS is not set
> -# CONFIG_GROUP_SCHED is not set
> -CONFIG_SYSFS_DEPRECATED=y
> -CONFIG_SYSFS_DEPRECATED_V2=y
> -# CONFIG_RELAY is not set
> -# CONFIG_NAMESPACES is not set
> -# CONFIG_BLK_DEV_INITRD is not set
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -CONFIG_EMBEDDED=y
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -# CONFIG_ELF_CORE is not set
> -CONFIG_COMPAT_BRK=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_ANON_INODES=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -# CONFIG_SHMEM is not set
> -CONFIG_VM_EVENT_COUNTERS=y
> -CONFIG_SLAB=y
> -# CONFIG_SLUB is not set
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -# CONFIG_MARKERS is not set
> -CONFIG_HAVE_OPROFILE=y
> -# CONFIG_KPROBES is not set
> -# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
> -# CONFIG_HAVE_IOREMAP_PROT is not set
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -# CONFIG_HAVE_ARCH_TRACEHOOK is not set
> -# CONFIG_HAVE_DMA_ATTRS is not set
> -# CONFIG_USE_GENERIC_SMP_HELPERS is not set
> -CONFIG_HAVE_CLK=y
> -CONFIG_PROC_PAGE_MONITOR=y
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_SLABINFO=y
> -CONFIG_RT_MUTEXES=y
> -CONFIG_TINY_SHMEM=y
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -# CONFIG_MODULE_FORCE_UNLOAD is not set
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -CONFIG_KMOD=y
> -CONFIG_BLOCK=y
> -# CONFIG_LBD is not set
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_LSF is not set
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_BLK_DEV_INTEGRITY is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -# CONFIG_IOSCHED_AS is not set
> -CONFIG_IOSCHED_DEADLINE=y
> -# CONFIG_IOSCHED_CFQ is not set
> -# CONFIG_DEFAULT_AS is not set
> -CONFIG_DEFAULT_DEADLINE=y
> -# CONFIG_DEFAULT_CFQ is not set
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="deadline"
> -CONFIG_CLASSIC_RCU=y
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS7500 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IMX is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_MSM7X00A is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -# CONFIG_ARCH_GUMSTIX is not set
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -CONFIG_ARCH_VIPER=y
> -# CONFIG_ARCH_PXA_ESERIES is not set
> -# CONFIG_MACH_TRIZEPS4 is not set
> -# CONFIG_MACH_EM_X270 is not set
> -# CONFIG_MACH_COLIBRI is not set
> -# CONFIG_MACH_ZYLONITE is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_TAVOREVB is not set
> -# CONFIG_MACH_SAAR is not set
> -# CONFIG_MACH_ARMCORE is not set
> -# CONFIG_MACH_MAGICIAN is not set
> -# CONFIG_MACH_PCM027 is not set
> -# CONFIG_ARCH_PXA_PALM is not set
> -# CONFIG_PXA_EZX is not set
> -CONFIG_PXA25x=y
> -CONFIG_PXA_PWM=m
> -CONFIG_PXA_HAVE_ISA_IRQS=y
> -
> -#
> -# Boot options
> -#
> -
> -#
> -# Power management
> -#
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_PABRT_NOIFAR=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -# CONFIG_OUTER_CACHE is not set
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -
> -#
> -# Bus support
> -#
> -CONFIG_ISA=y
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -CONFIG_PCCARD=m
> -# CONFIG_PCMCIA_DEBUG is not set
> -CONFIG_PCMCIA=m
> -CONFIG_PCMCIA_LOAD_CIS=y
> -CONFIG_PCMCIA_IOCTL=y
> -
> -#
> -# PC-card bridges
> -#
> -# CONFIG_I82365 is not set
> -# CONFIG_TCIC is not set
> -CONFIG_PCMCIA_PXA2XX=m
> -CONFIG_PCMCIA_PROBE=y
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -# CONFIG_NO_HZ is not set
> -# CONFIG_HIGH_RES_TIMERS is not set
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -# CONFIG_PREEMPT is not set
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -# CONFIG_SPARSEMEM_STATIC is not set
> -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
> -CONFIG_PAGEFLAGS_EXTENDED=y
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_RESOURCES_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=1
> -CONFIG_BOUNCE=y
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_ALIGNMENT_TRAP=y
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="root=31:02 rootfstype=jffs2 ro console=ttyS0,115200"
> -# CONFIG_XIP_KERNEL is not set
> -# CONFIG_KEXEC is not set
> -
> -#
> -# CPU Frequency scaling
> -#
> -CONFIG_CPU_FREQ=y
> -CONFIG_CPU_FREQ_TABLE=y
> -# CONFIG_CPU_FREQ_DEBUG is not set
> -CONFIG_CPU_FREQ_STAT=y
> -# CONFIG_CPU_FREQ_STAT_DETAILS is not set
> -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
> -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
> -CONFIG_CPU_FREQ_GOV_POWERSAVE=m
> -CONFIG_CPU_FREQ_GOV_USERSPACE=m
> -CONFIG_CPU_FREQ_GOV_ONDEMAND=m
> -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -# CONFIG_FPE_NWFPE is not set
> -CONFIG_FPE_FASTFPE=y
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -CONFIG_PM=y
> -# CONFIG_PM_DEBUG is not set
> -CONFIG_PM_SLEEP=y
> -CONFIG_SUSPEND=y
> -CONFIG_SUSPEND_FREEZER=y
> -# CONFIG_APM_EMULATION is not set
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_PACKET=y
> -# CONFIG_PACKET_MMAP is not set
> -CONFIG_UNIX=y
> -CONFIG_XFRM=y
> -# CONFIG_XFRM_USER is not set
> -# CONFIG_XFRM_SUB_POLICY is not set
> -# CONFIG_XFRM_MIGRATE is not set
> -# CONFIG_XFRM_STATISTICS is not set
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -# CONFIG_IP_PNP_BOOTP is not set
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -CONFIG_SYN_COOKIES=y
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -CONFIG_INET_XFRM_MODE_TRANSPORT=y
> -CONFIG_INET_XFRM_MODE_TUNNEL=y
> -CONFIG_INET_XFRM_MODE_BEET=y
> -# CONFIG_INET_LRO is not set
> -CONFIG_INET_DIAG=y
> -CONFIG_INET_TCP_DIAG=y
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -# CONFIG_NETFILTER is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_NET_SCHED is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -# CONFIG_IRDA is not set
> -CONFIG_BT=m
> -CONFIG_BT_L2CAP=m
> -# CONFIG_BT_SCO is not set
> -CONFIG_BT_RFCOMM=m
> -CONFIG_BT_RFCOMM_TTY=y
> -CONFIG_BT_BNEP=m
> -# CONFIG_BT_BNEP_MC_FILTER is not set
> -# CONFIG_BT_BNEP_PROTO_FILTER is not set
> -# CONFIG_BT_HIDP is not set
> -
> -#
> -# Bluetooth device drivers
> -#
> -CONFIG_BT_HCIUSB=m
> -# CONFIG_BT_HCIUSB_SCO is not set
> -# CONFIG_BT_HCIBTUSB is not set
> -CONFIG_BT_HCIUART=m
> -CONFIG_BT_HCIUART_H4=y
> -CONFIG_BT_HCIUART_BCSP=y
> -# CONFIG_BT_HCIUART_LL is not set
> -# CONFIG_BT_HCIBCM203X is not set
> -# CONFIG_BT_HCIBPA10X is not set
> -# CONFIG_BT_HCIBFUSB is not set
> -# CONFIG_BT_HCIDTL1 is not set
> -# CONFIG_BT_HCIBT3C is not set
> -# CONFIG_BT_HCIBLUECARD is not set
> -# CONFIG_BT_HCIBTUART is not set
> -# CONFIG_BT_HCIVHCI is not set
> -# CONFIG_AF_RXRPC is not set
> -
> -#
> -# Wireless
> -#
> -# CONFIG_CFG80211 is not set
> -# CONFIG_WIRELESS_EXT is not set
> -# CONFIG_MAC80211 is not set
> -CONFIG_IEEE80211=m
> -# CONFIG_IEEE80211_DEBUG is not set
> -CONFIG_IEEE80211_CRYPT_WEP=m
> -# CONFIG_IEEE80211_CRYPT_CCMP is not set
> -# CONFIG_IEEE80211_CRYPT_TKIP is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=m
> -CONFIG_FIRMWARE_IN_KERNEL=y
> -CONFIG_EXTRA_FIRMWARE=""
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_DEBUG_DEVRES is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -# CONFIG_CONNECTOR is not set
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -CONFIG_MTD_REDBOOT_PARTS=y
> -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=0
> -# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
> -# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
> -# CONFIG_MTD_CMDLINE_PARTS is not set
> -# CONFIG_MTD_AFS_PARTS is not set
> -# CONFIG_MTD_AR7_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=m
> -CONFIG_MTD_BLKDEVS=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_JEDECPROBE=y
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_NOSWAP=y
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> -CONFIG_MTD_CFI_GEOMETRY=y
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -# CONFIG_MTD_CFI_I2 is not set
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -# CONFIG_MTD_OTP is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_CFI_AMDSTD=y
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -CONFIG_MTD_RAM=y
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -CONFIG_MTD_COMPLEX_MAPPINGS=y
> -CONFIG_MTD_PHYSMAP=y
> -CONFIG_MTD_PHYSMAP_START=0x8000000
> -CONFIG_MTD_PHYSMAP_LEN=0
> -CONFIG_MTD_PHYSMAP_BANKWIDTH=2
> -CONFIG_MTD_PXA2XX=y
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_IMPA7 is not set
> -# CONFIG_MTD_SHARP_SL is not set
> -# CONFIG_MTD_PLATRAM is not set
> -CONFIG_MTD_SPARSE_RAM=y
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -# CONFIG_MTD_NAND is not set
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -# CONFIG_PNP is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -CONFIG_BLK_DEV_LOOP=m
> -# CONFIG_BLK_DEV_CRYPTOLOOP is not set
> -# CONFIG_BLK_DEV_NBD is not set
> -# CONFIG_BLK_DEV_UB is not set
> -# CONFIG_BLK_DEV_RAM is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -CONFIG_MISC_DEVICES=y
> -# CONFIG_EEPROM_93CX6 is not set
> -# CONFIG_ENCLOSURE_SERVICES is not set
> -CONFIG_HAVE_IDE=y
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -CONFIG_SCSI=m
> -CONFIG_SCSI_DMA=y
> -# CONFIG_SCSI_TGT is not set
> -# CONFIG_SCSI_NETLINK is not set
> -# CONFIG_SCSI_PROC_FS is not set
> -
> -#
> -# SCSI support type (disk, tape, CD-ROM)
> -#
> -CONFIG_BLK_DEV_SD=m
> -# CONFIG_CHR_DEV_ST is not set
> -# CONFIG_CHR_DEV_OSST is not set
> -# CONFIG_BLK_DEV_SR is not set
> -# CONFIG_CHR_DEV_SG is not set
> -# CONFIG_CHR_DEV_SCH is not set
> -
> -#
> -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
> -#
> -# CONFIG_SCSI_MULTI_LUN is not set
> -# CONFIG_SCSI_CONSTANTS is not set
> -# CONFIG_SCSI_LOGGING is not set
> -# CONFIG_SCSI_SCAN_ASYNC is not set
> -CONFIG_SCSI_WAIT_SCAN=m
> -
> -#
> -# SCSI Transports
> -#
> -# CONFIG_SCSI_SPI_ATTRS is not set
> -# CONFIG_SCSI_FC_ATTRS is not set
> -# CONFIG_SCSI_ISCSI_ATTRS is not set
> -# CONFIG_SCSI_SAS_LIBSAS is not set
> -# CONFIG_SCSI_SRP_ATTRS is not set
> -CONFIG_SCSI_LOWLEVEL=y
> -# CONFIG_ISCSI_TCP is not set
> -# CONFIG_SCSI_AHA152X is not set
> -# CONFIG_SCSI_AIC7XXX_OLD is not set
> -# CONFIG_SCSI_ADVANSYS is not set
> -# CONFIG_SCSI_IN2000 is not set
> -# CONFIG_SCSI_DTC3280 is not set
> -# CONFIG_SCSI_FUTURE_DOMAIN is not set
> -# CONFIG_SCSI_GENERIC_NCR5380 is not set
> -# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
> -# CONFIG_SCSI_NCR53C406A is not set
> -# CONFIG_SCSI_PAS16 is not set
> -# CONFIG_SCSI_QLOGIC_FAS is not set
> -# CONFIG_SCSI_SYM53C416 is not set
> -# CONFIG_SCSI_T128 is not set
> -# CONFIG_SCSI_DEBUG is not set
> -# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
> -# CONFIG_SCSI_DH is not set
> -CONFIG_ATA=m
> -# CONFIG_ATA_NONSTANDARD is not set
> -# CONFIG_SATA_PMP is not set
> -CONFIG_ATA_SFF=y
> -# CONFIG_SATA_MV is not set
> -# CONFIG_PATA_LEGACY is not set
> -CONFIG_PATA_PCMCIA=m
> -# CONFIG_PATA_QDI is not set
> -# CONFIG_PATA_WINBOND_VLB is not set
> -# CONFIG_PATA_PLATFORM is not set
> -# CONFIG_MD is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_MACVLAN is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -# CONFIG_VETH is not set
> -# CONFIG_ARCNET is not set
> -# CONFIG_PHYLIB is not set
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=y
> -# CONFIG_AX88796 is not set
> -# CONFIG_NET_VENDOR_3COM is not set
> -# CONFIG_NET_VENDOR_SMC is not set
> -CONFIG_SMC91X=y
> -# CONFIG_DM9000 is not set
> -# CONFIG_SMC911X is not set
> -# CONFIG_NET_VENDOR_RACAL is not set
> -# CONFIG_AT1700 is not set
> -# CONFIG_DEPCA is not set
> -# CONFIG_HP100 is not set
> -# CONFIG_NET_ISA is not set
> -# CONFIG_IBM_NEW_EMAC_ZMII is not set
> -# CONFIG_IBM_NEW_EMAC_RGMII is not set
> -# CONFIG_IBM_NEW_EMAC_TAH is not set
> -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
> -# CONFIG_NET_PCI is not set
> -# CONFIG_B44 is not set
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -# CONFIG_TR is not set
> -
> -#
> -# Wireless LAN
> -#
> -# CONFIG_WLAN_PRE80211 is not set
> -# CONFIG_WLAN_80211 is not set
> -# CONFIG_IWLWIFI_LEDS is not set
> -
> -#
> -# USB Network Adapters
> -#
> -# CONFIG_USB_CATC is not set
> -# CONFIG_USB_KAWETH is not set
> -CONFIG_USB_PEGASUS=m
> -# CONFIG_USB_RTL8150 is not set
> -CONFIG_USB_USBNET=m
> -CONFIG_USB_NET_AX8817X=m
> -CONFIG_USB_NET_CDCETHER=m
> -# CONFIG_USB_NET_DM9601 is not set
> -# CONFIG_USB_NET_GL620A is not set
> -CONFIG_USB_NET_NET1080=m
> -# CONFIG_USB_NET_PLUSB is not set
> -# CONFIG_USB_NET_MCS7830 is not set
> -# CONFIG_USB_NET_RNDIS_HOST is not set
> -# CONFIG_USB_NET_CDC_SUBSET is not set
> -CONFIG_USB_NET_ZAURUS=m
> -CONFIG_NET_PCMCIA=y
> -# CONFIG_PCMCIA_3C589 is not set
> -# CONFIG_PCMCIA_3C574 is not set
> -# CONFIG_PCMCIA_FMVJ18X is not set
> -# CONFIG_PCMCIA_PCNET is not set
> -# CONFIG_PCMCIA_NMCLAN is not set
> -# CONFIG_PCMCIA_SMC91C92 is not set
> -# CONFIG_PCMCIA_XIRC2PS is not set
> -# CONFIG_PCMCIA_AXNET is not set
> -# CONFIG_WAN is not set
> -CONFIG_PPP=m
> -# CONFIG_PPP_MULTILINK is not set
> -# CONFIG_PPP_FILTER is not set
> -CONFIG_PPP_ASYNC=m
> -# CONFIG_PPP_SYNC_TTY is not set
> -CONFIG_PPP_DEFLATE=m
> -CONFIG_PPP_BSDCOMP=m
> -# CONFIG_PPP_MPPE is not set
> -# CONFIG_PPPOE is not set
> -# CONFIG_PPPOL2TP is not set
> -# CONFIG_SLIP is not set
> -CONFIG_SLHC=m
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=m
> -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> -# CONFIG_INPUT_JOYDEV is not set
> -CONFIG_INPUT_EVDEV=m
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -# CONFIG_INPUT_KEYBOARD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -CONFIG_TOUCHSCREEN_FUJITSU=m
> -# CONFIG_TOUCHSCREEN_GUNZE is not set
> -CONFIG_TOUCHSCREEN_ELO=m
> -CONFIG_TOUCHSCREEN_MTOUCH=m
> -CONFIG_TOUCHSCREEN_INEXIO=m
> -# CONFIG_TOUCHSCREEN_MK712 is not set
> -CONFIG_TOUCHSCREEN_HTCPEN=m
> -CONFIG_TOUCHSCREEN_PENMOUNT=m
> -CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
> -CONFIG_TOUCHSCREEN_TOUCHWIN=m
> -# CONFIG_TOUCHSCREEN_UCB1400 is not set
> -# CONFIG_TOUCHSCREEN_WM97XX is not set
> -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
> -CONFIG_TOUCHSCREEN_TOUCHIT213=m
> -CONFIG_INPUT_MISC=y
> -# CONFIG_INPUT_ATI_REMOTE is not set
> -# CONFIG_INPUT_ATI_REMOTE2 is not set
> -# CONFIG_INPUT_KEYSPAN_REMOTE is not set
> -# CONFIG_INPUT_POWERMATE is not set
> -# CONFIG_INPUT_YEALINK is not set
> -CONFIG_INPUT_UINPUT=m
> -
> -#
> -# Hardware I/O ports
> -#
> -CONFIG_SERIO=y
> -CONFIG_SERIO_SERPORT=y
> -# CONFIG_SERIO_LIBPS2 is not set
> -# CONFIG_SERIO_RAW is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -# CONFIG_CONSOLE_TRANSLATIONS is not set
> -# CONFIG_VT_CONSOLE is not set
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -CONFIG_DEVKMEM=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -CONFIG_SERIAL_8250=m
> -# CONFIG_SERIAL_8250_CS is not set
> -CONFIG_SERIAL_8250_NR_UARTS=5
> -CONFIG_SERIAL_8250_RUNTIME_UARTS=5
> -# CONFIG_SERIAL_8250_EXTENDED is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_LEGACY_PTYS is not set
> -# CONFIG_IPMI_HANDLER is not set
> -CONFIG_HW_RANDOM=m
> -# CONFIG_NVRAM is not set
> -# CONFIG_DTLK is not set
> -# CONFIG_R3964 is not set
> -
> -#
> -# PCMCIA character devices
> -#
> -# CONFIG_SYNCLINK_CS is not set
> -# CONFIG_CARDMAN_4000 is not set
> -# CONFIG_CARDMAN_4040 is not set
> -# CONFIG_IPWIRELESS is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -CONFIG_DEVPORT=y
> -CONFIG_I2C=y
> -CONFIG_I2C_BOARDINFO=y
> -CONFIG_I2C_CHARDEV=y
> -# CONFIG_I2C_HELPER_AUTO is not set
> -
> -#
> -# I2C Algorithms
> -#
> -CONFIG_I2C_ALGOBIT=y
> -# CONFIG_I2C_ALGOPCF is not set
> -# CONFIG_I2C_ALGOPCA is not set
> -
> -#
> -# I2C Hardware Bus support
> -#
> -
> -#
> -# I2C system bus drivers (mostly embedded / system-on-chip)
> -#
> -CONFIG_I2C_GPIO=y
> -# CONFIG_I2C_OCORES is not set
> -CONFIG_I2C_PXA=y
> -# CONFIG_I2C_PXA_SLAVE is not set
> -# CONFIG_I2C_SIMTEC is not set
> -
> -#
> -# External I2C/SMBus adapter drivers
> -#
> -# CONFIG_I2C_PARPORT_LIGHT is not set
> -# CONFIG_I2C_TAOS_EVM is not set
> -# CONFIG_I2C_TINY_USB is not set
> -
> -#
> -# Other I2C/SMBus bus drivers
> -#
> -# CONFIG_I2C_ELEKTOR is not set
> -# CONFIG_I2C_PCA_ISA is not set
> -# CONFIG_I2C_PCA_PLATFORM is not set
> -# CONFIG_I2C_STUB is not set
> -
> -#
> -# Miscellaneous I2C Chip support
> -#
> -# CONFIG_DS1682 is not set
> -# CONFIG_EEPROM_AT24 is not set
> -# CONFIG_EEPROM_LEGACY is not set
> -# CONFIG_SENSORS_PCF8574 is not set
> -# CONFIG_PCF8575 is not set
> -# CONFIG_SENSORS_PCA9539 is not set
> -# CONFIG_SENSORS_PCF8591 is not set
> -# CONFIG_TPS65010 is not set
> -# CONFIG_SENSORS_MAX6875 is not set
> -# CONFIG_SENSORS_TSL2550 is not set
> -# CONFIG_I2C_DEBUG_CORE is not set
> -# CONFIG_I2C_DEBUG_ALGO is not set
> -# CONFIG_I2C_DEBUG_BUS is not set
> -# CONFIG_I2C_DEBUG_CHIP is not set
> -# CONFIG_SPI is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -# CONFIG_DEBUG_GPIO is not set
> -CONFIG_GPIO_SYSFS=y
> -
> -#
> -# I2C GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX732X is not set
> -# CONFIG_GPIO_PCA953X is not set
> -# CONFIG_GPIO_PCF857X is not set
> -
> -#
> -# PCI GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -# CONFIG_W1 is not set
> -# CONFIG_POWER_SUPPLY is not set
> -CONFIG_HWMON=y
> -# CONFIG_HWMON_VID is not set
> -# CONFIG_SENSORS_AD7414 is not set
> -# CONFIG_SENSORS_AD7418 is not set
> -# CONFIG_SENSORS_ADM1021 is not set
> -# CONFIG_SENSORS_ADM1025 is not set
> -# CONFIG_SENSORS_ADM1026 is not set
> -# CONFIG_SENSORS_ADM1029 is not set
> -# CONFIG_SENSORS_ADM1031 is not set
> -# CONFIG_SENSORS_ADM9240 is not set
> -# CONFIG_SENSORS_ADT7470 is not set
> -# CONFIG_SENSORS_ADT7473 is not set
> -# CONFIG_SENSORS_ATXP1 is not set
> -# CONFIG_SENSORS_DS1621 is not set
> -# CONFIG_SENSORS_F71805F is not set
> -# CONFIG_SENSORS_F71882FG is not set
> -# CONFIG_SENSORS_F75375S is not set
> -# CONFIG_SENSORS_GL518SM is not set
> -# CONFIG_SENSORS_GL520SM is not set
> -# CONFIG_SENSORS_IT87 is not set
> -# CONFIG_SENSORS_LM63 is not set
> -# CONFIG_SENSORS_LM75 is not set
> -# CONFIG_SENSORS_LM77 is not set
> -# CONFIG_SENSORS_LM78 is not set
> -# CONFIG_SENSORS_LM80 is not set
> -# CONFIG_SENSORS_LM83 is not set
> -# CONFIG_SENSORS_LM85 is not set
> -# CONFIG_SENSORS_LM87 is not set
> -# CONFIG_SENSORS_LM90 is not set
> -# CONFIG_SENSORS_LM92 is not set
> -# CONFIG_SENSORS_LM93 is not set
> -# CONFIG_SENSORS_MAX1619 is not set
> -# CONFIG_SENSORS_MAX6650 is not set
> -# CONFIG_SENSORS_PC87360 is not set
> -# CONFIG_SENSORS_PC87427 is not set
> -# CONFIG_SENSORS_DME1737 is not set
> -# CONFIG_SENSORS_SMSC47M1 is not set
> -# CONFIG_SENSORS_SMSC47M192 is not set
> -# CONFIG_SENSORS_SMSC47B397 is not set
> -# CONFIG_SENSORS_ADS7828 is not set
> -# CONFIG_SENSORS_THMC50 is not set
> -# CONFIG_SENSORS_VT1211 is not set
> -# CONFIG_SENSORS_W83781D is not set
> -# CONFIG_SENSORS_W83791D is not set
> -# CONFIG_SENSORS_W83792D is not set
> -# CONFIG_SENSORS_W83793 is not set
> -# CONFIG_SENSORS_W83L785TS is not set
> -# CONFIG_SENSORS_W83L786NG is not set
> -# CONFIG_SENSORS_W83627HF is not set
> -# CONFIG_SENSORS_W83627EHF is not set
> -# CONFIG_HWMON_DEBUG_CHIP is not set
> -CONFIG_WATCHDOG=y
> -# CONFIG_WATCHDOG_NOWAYOUT is not set
> -
> -#
> -# Watchdog Device Drivers
> -#
> -# CONFIG_SOFT_WATCHDOG is not set
> -# CONFIG_SA1100_WATCHDOG is not set
> -
> -#
> -# ISA-based Watchdog Cards
> -#
> -# CONFIG_PCWATCHDOG is not set
> -# CONFIG_MIXCOMWD is not set
> -# CONFIG_WDT is not set
> -
> -#
> -# USB-based Watchdog Cards
> -#
> -# CONFIG_USBPCWATCHDOG is not set
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -CONFIG_SSB_POSSIBLE=y
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_CORE is not set
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -# CONFIG_MFD_TMIO is not set
> -# CONFIG_MFD_T7L66XB is not set
> -# CONFIG_MFD_TC6387XB is not set
> -# CONFIG_MFD_TC6393XB is not set
> -
> -#
> -# Multimedia devices
> -#
> -
> -#
> -# Multimedia core support
> -#
> -# CONFIG_VIDEO_DEV is not set
> -# CONFIG_DVB_CORE is not set
> -# CONFIG_VIDEO_MEDIA is not set
> -
> -#
> -# Multimedia drivers
> -#
> -# CONFIG_DAB is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -CONFIG_FB=y
> -# CONFIG_FIRMWARE_EDID is not set
> -# CONFIG_FB_DDC is not set
> -CONFIG_FB_CFB_FILLRECT=m
> -CONFIG_FB_CFB_COPYAREA=m
> -CONFIG_FB_CFB_IMAGEBLIT=m
> -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> -# CONFIG_FB_SYS_FILLRECT is not set
> -# CONFIG_FB_SYS_COPYAREA is not set
> -# CONFIG_FB_SYS_IMAGEBLIT is not set
> -# CONFIG_FB_FOREIGN_ENDIAN is not set
> -# CONFIG_FB_SYS_FOPS is not set
> -# CONFIG_FB_SVGALIB is not set
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -
> -#
> -# Frame buffer hardware drivers
> -#
> -# CONFIG_FB_S1D13XXX is not set
> -CONFIG_FB_PXA=m
> -# CONFIG_FB_PXA_SMARTPANEL is not set
> -CONFIG_FB_PXA_PARAMETERS=y
> -# CONFIG_FB_MBX is not set
> -# CONFIG_FB_W100 is not set
> -# CONFIG_FB_AM200EPD is not set
> -# CONFIG_FB_VIRTUAL is not set
> -CONFIG_BACKLIGHT_LCD_SUPPORT=y
> -CONFIG_LCD_CLASS_DEVICE=m
> -# CONFIG_LCD_ILI9320 is not set
> -# CONFIG_LCD_PLATFORM is not set
> -CONFIG_BACKLIGHT_CLASS_DEVICE=m
> -# CONFIG_BACKLIGHT_CORGI is not set
> -CONFIG_BACKLIGHT_PWM=m
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -# CONFIG_MDA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=m
> -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
> -# CONFIG_FONTS is not set
> -CONFIG_FONT_8x8=y
> -CONFIG_FONT_8x16=y
> -CONFIG_LOGO=y
> -CONFIG_LOGO_LINUX_MONO=y
> -CONFIG_LOGO_LINUX_VGA16=y
> -CONFIG_LOGO_LINUX_CLUT224=y
> -CONFIG_SOUND=m
> -CONFIG_SND=m
> -CONFIG_SND_TIMER=m
> -CONFIG_SND_PCM=m
> -# CONFIG_SND_SEQUENCER is not set
> -CONFIG_SND_OSSEMUL=y
> -CONFIG_SND_MIXER_OSS=m
> -CONFIG_SND_PCM_OSS=m
> -CONFIG_SND_PCM_OSS_PLUGINS=y
> -# CONFIG_SND_DYNAMIC_MINORS is not set
> -CONFIG_SND_SUPPORT_OLD_API=y
> -CONFIG_SND_VERBOSE_PROCFS=y
> -# CONFIG_SND_VERBOSE_PRINTK is not set
> -# CONFIG_SND_DEBUG is not set
> -CONFIG_SND_VMASTER=y
> -CONFIG_SND_AC97_CODEC=m
> -CONFIG_SND_DRIVERS=y
> -# CONFIG_SND_DUMMY is not set
> -# CONFIG_SND_MTPAV is not set
> -# CONFIG_SND_SERIAL_U16550 is not set
> -# CONFIG_SND_MPU401 is not set
> -# CONFIG_SND_AC97_POWER_SAVE is not set
> -CONFIG_SND_ARM=y
> -CONFIG_SND_PXA2XX_PCM=m
> -CONFIG_SND_PXA2XX_AC97=m
> -CONFIG_SND_USB=y
> -# CONFIG_SND_USB_AUDIO is not set
> -# CONFIG_SND_USB_CAIAQ is not set
> -CONFIG_SND_PCMCIA=y
> -# CONFIG_SND_VXPOCKET is not set
> -# CONFIG_SND_PDAUDIOCF is not set
> -# CONFIG_SND_SOC is not set
> -# CONFIG_SOUND_PRIME is not set
> -CONFIG_AC97_BUS=m
> -CONFIG_HID_SUPPORT=y
> -CONFIG_HID=y
> -# CONFIG_HID_DEBUG is not set
> -# CONFIG_HIDRAW is not set
> -
> -#
> -# USB Input Devices
> -#
> -CONFIG_USB_HID=m
> -# CONFIG_USB_HIDINPUT_POWERBOOK is not set
> -# CONFIG_HID_FF is not set
> -# CONFIG_USB_HIDDEV is not set
> -
> -#
> -# USB HID Boot Protocol drivers
> -#
> -# CONFIG_USB_KBD is not set
> -# CONFIG_USB_MOUSE is not set
> -CONFIG_USB_SUPPORT=y
> -CONFIG_USB_ARCH_HAS_HCD=y
> -# CONFIG_USB_ARCH_HAS_OHCI is not set
> -# CONFIG_USB_ARCH_HAS_EHCI is not set
> -CONFIG_USB=m
> -# CONFIG_USB_DEBUG is not set
> -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
> -
> -#
> -# Miscellaneous USB options
> -#
> -CONFIG_USB_DEVICEFS=y
> -CONFIG_USB_DEVICE_CLASS=y
> -# CONFIG_USB_DYNAMIC_MINORS is not set
> -CONFIG_USB_SUSPEND=y
> -# CONFIG_USB_OTG is not set
> -# CONFIG_USB_OTG_WHITELIST is not set
> -# CONFIG_USB_OTG_BLACKLIST_HUB is not set
> -# CONFIG_USB_MON is not set
> -
> -#
> -# USB Host Controller Drivers
> -#
> -# CONFIG_USB_C67X00_HCD is not set
> -CONFIG_USB_ISP116X_HCD=m
> -# CONFIG_USB_ISP1760_HCD is not set
> -CONFIG_USB_SL811_HCD=m
> -# CONFIG_USB_SL811_CS is not set
> -CONFIG_USB_R8A66597_HCD=m
> -# CONFIG_USB_MUSB_HDRC is not set
> -# CONFIG_USB_GADGET_MUSB_HDRC is not set
> -
> -#
> -# USB Device Class drivers
> -#
> -CONFIG_USB_ACM=m
> -# CONFIG_USB_PRINTER is not set
> -# CONFIG_USB_WDM is not set
> -
> -#
> -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
> -#
> -
> -#
> -# may also be needed; see USB_STORAGE Help for more information
> -#
> -CONFIG_USB_STORAGE=m
> -# CONFIG_USB_STORAGE_DEBUG is not set
> -# CONFIG_USB_STORAGE_DATAFAB is not set
> -# CONFIG_USB_STORAGE_FREECOM is not set
> -# CONFIG_USB_STORAGE_ISD200 is not set
> -# CONFIG_USB_STORAGE_DPCM is not set
> -# CONFIG_USB_STORAGE_USBAT is not set
> -# CONFIG_USB_STORAGE_SDDR09 is not set
> -# CONFIG_USB_STORAGE_SDDR55 is not set
> -# CONFIG_USB_STORAGE_JUMPSHOT is not set
> -# CONFIG_USB_STORAGE_ALAUDA is not set
> -# CONFIG_USB_STORAGE_ONETOUCH is not set
> -# CONFIG_USB_STORAGE_KARMA is not set
> -# CONFIG_USB_STORAGE_SIERRA is not set
> -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
> -# CONFIG_USB_LIBUSUAL is not set
> -
> -#
> -# USB Imaging devices
> -#
> -# CONFIG_USB_MDC800 is not set
> -# CONFIG_USB_MICROTEK is not set
> -
> -#
> -# USB port drivers
> -#
> -CONFIG_USB_SERIAL=m
> -# CONFIG_USB_EZUSB is not set
> -CONFIG_USB_SERIAL_GENERIC=y
> -# CONFIG_USB_SERIAL_AIRCABLE is not set
> -# CONFIG_USB_SERIAL_ARK3116 is not set
> -# CONFIG_USB_SERIAL_BELKIN is not set
> -# CONFIG_USB_SERIAL_CH341 is not set
> -# CONFIG_USB_SERIAL_WHITEHEAT is not set
> -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
> -# CONFIG_USB_SERIAL_CP2101 is not set
> -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
> -# CONFIG_USB_SERIAL_EMPEG is not set
> -# CONFIG_USB_SERIAL_FTDI_SIO is not set
> -# CONFIG_USB_SERIAL_FUNSOFT is not set
> -# CONFIG_USB_SERIAL_VISOR is not set
> -# CONFIG_USB_SERIAL_IPAQ is not set
> -# CONFIG_USB_SERIAL_IR is not set
> -# CONFIG_USB_SERIAL_EDGEPORT is not set
> -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
> -# CONFIG_USB_SERIAL_GARMIN is not set
> -# CONFIG_USB_SERIAL_IPW is not set
> -# CONFIG_USB_SERIAL_IUU is not set
> -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
> -# CONFIG_USB_SERIAL_KEYSPAN is not set
> -# CONFIG_USB_SERIAL_KLSI is not set
> -# CONFIG_USB_SERIAL_KOBIL_SCT is not set
> -CONFIG_USB_SERIAL_MCT_U232=m
> -# CONFIG_USB_SERIAL_MOS7720 is not set
> -# CONFIG_USB_SERIAL_MOS7840 is not set
> -# CONFIG_USB_SERIAL_MOTOROLA is not set
> -# CONFIG_USB_SERIAL_NAVMAN is not set
> -# CONFIG_USB_SERIAL_PL2303 is not set
> -# CONFIG_USB_SERIAL_OTI6858 is not set
> -# CONFIG_USB_SERIAL_SPCP8X5 is not set
> -# CONFIG_USB_SERIAL_HP4X is not set
> -# CONFIG_USB_SERIAL_SAFE is not set
> -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
> -# CONFIG_USB_SERIAL_TI is not set
> -# CONFIG_USB_SERIAL_CYBERJACK is not set
> -# CONFIG_USB_SERIAL_XIRCOM is not set
> -# CONFIG_USB_SERIAL_OPTION is not set
> -# CONFIG_USB_SERIAL_OMNINET is not set
> -# CONFIG_USB_SERIAL_DEBUG is not set
> -
> -#
> -# USB Miscellaneous drivers
> -#
> -# CONFIG_USB_EMI62 is not set
> -# CONFIG_USB_EMI26 is not set
> -# CONFIG_USB_ADUTUX is not set
> -# CONFIG_USB_RIO500 is not set
> -# CONFIG_USB_LEGOTOWER is not set
> -# CONFIG_USB_LCD is not set
> -# CONFIG_USB_BERRY_CHARGE is not set
> -# CONFIG_USB_LED is not set
> -# CONFIG_USB_CYPRESS_CY7C63 is not set
> -# CONFIG_USB_CYTHERM is not set
> -# CONFIG_USB_PHIDGET is not set
> -# CONFIG_USB_IDMOUSE is not set
> -# CONFIG_USB_FTDI_ELAN is not set
> -# CONFIG_USB_APPLEDISPLAY is not set
> -# CONFIG_USB_LD is not set
> -# CONFIG_USB_TRANCEVIBRATOR is not set
> -# CONFIG_USB_IOWARRIOR is not set
> -# CONFIG_USB_TEST is not set
> -# CONFIG_USB_ISIGHTFW is not set
> -CONFIG_USB_GADGET=m
> -# CONFIG_USB_GADGET_DEBUG is not set
> -# CONFIG_USB_GADGET_DEBUG_FILES is not set
> -CONFIG_USB_GADGET_SELECTED=y
> -# CONFIG_USB_GADGET_AMD5536UDC is not set
> -# CONFIG_USB_GADGET_ATMEL_USBA is not set
> -# CONFIG_USB_GADGET_FSL_USB2 is not set
> -# CONFIG_USB_GADGET_NET2280 is not set
> -CONFIG_USB_GADGET_PXA25X=y
> -CONFIG_USB_PXA25X=m
> -# CONFIG_USB_PXA25X_SMALL is not set
> -# CONFIG_USB_GADGET_M66592 is not set
> -# CONFIG_USB_GADGET_PXA27X is not set
> -# CONFIG_USB_GADGET_GOKU is not set
> -# CONFIG_USB_GADGET_LH7A40X is not set
> -# CONFIG_USB_GADGET_OMAP is not set
> -# CONFIG_USB_GADGET_S3C2410 is not set
> -# CONFIG_USB_GADGET_AT91 is not set
> -# CONFIG_USB_GADGET_DUMMY_HCD is not set
> -# CONFIG_USB_GADGET_DUALSPEED is not set
> -# CONFIG_USB_ZERO is not set
> -CONFIG_USB_ETH=m
> -CONFIG_USB_ETH_RNDIS=y
> -CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> -# CONFIG_USB_FILE_STORAGE_TEST is not set
> -CONFIG_USB_G_SERIAL=m
> -# CONFIG_USB_MIDI_GADGET is not set
> -CONFIG_USB_G_PRINTER=m
> -# CONFIG_USB_CDC_COMPOSITE is not set
> -# CONFIG_MMC is not set
> -# CONFIG_NEW_LEDS is not set
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=m
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -# CONFIG_RTC_DRV_TEST is not set
> -
> -#
> -# I2C RTC drivers
> -#
> -CONFIG_RTC_DRV_DS1307=m
> -# CONFIG_RTC_DRV_DS1374 is not set
> -# CONFIG_RTC_DRV_DS1672 is not set
> -# CONFIG_RTC_DRV_MAX6900 is not set
> -# CONFIG_RTC_DRV_RS5C372 is not set
> -# CONFIG_RTC_DRV_ISL1208 is not set
> -# CONFIG_RTC_DRV_X1205 is not set
> -# CONFIG_RTC_DRV_PCF8563 is not set
> -# CONFIG_RTC_DRV_PCF8583 is not set
> -# CONFIG_RTC_DRV_M41T80 is not set
> -# CONFIG_RTC_DRV_S35390A is not set
> -# CONFIG_RTC_DRV_FM3130 is not set
> -
> -#
> -# SPI RTC drivers
> -#
> -
> -#
> -# Platform RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_DS1511 is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_STK17TA8 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -# CONFIG_RTC_DRV_M48T59 is not set
> -# CONFIG_RTC_DRV_V3020 is not set
> -
> -#
> -# on-CPU RTC drivers
> -#
> -CONFIG_RTC_DRV_SA1100=m
> -# CONFIG_DMADEVICES is not set
> -
> -#
> -# Voltage and Current regulators
> -#
> -# CONFIG_REGULATOR is not set
> -# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
> -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
> -# CONFIG_REGULATOR_BQ24022 is not set
> -# CONFIG_UIO is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=m
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -CONFIG_EXT3_FS=m
> -# CONFIG_EXT3_FS_XATTR is not set
> -# CONFIG_EXT4DEV_FS is not set
> -CONFIG_JBD=m
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -# CONFIG_FS_POSIX_ACL is not set
> -# CONFIG_XFS_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_DNOTIFY is not set
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=m
> -# CONFIG_MSDOS_FS is not set
> -CONFIG_VFAT_FS=m
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -
> -#
> -# Miscellaneous filesystems
> -#
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
> -# CONFIG_JFFS2_SUMMARY is not set
> -# CONFIG_JFFS2_FS_XATTR is not set
> -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
> -CONFIG_JFFS2_ZLIB=y
> -# CONFIG_JFFS2_LZO is not set
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_OMFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -CONFIG_NETWORK_FILESYSTEMS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -# CONFIG_NFS_V3_ACL is not set
> -# CONFIG_NFS_V4 is not set
> -CONFIG_ROOT_NFS=y
> -CONFIG_NFSD=m
> -CONFIG_NFSD_V3=y
> -# CONFIG_NFSD_V3_ACL is not set
> -# CONFIG_NFSD_V4 is not set
> -CONFIG_LOCKD=y
> -CONFIG_LOCKD_V4=y
> -CONFIG_EXPORTFS=m
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=y
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -# CONFIG_CIFS is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -CONFIG_PARTITION_ADVANCED=y
> -# CONFIG_ACORN_PARTITION is not set
> -# CONFIG_OSF_PARTITION is not set
> -# CONFIG_AMIGA_PARTITION is not set
> -# CONFIG_ATARI_PARTITION is not set
> -# CONFIG_MAC_PARTITION is not set
> -CONFIG_MSDOS_PARTITION=y
> -# CONFIG_BSD_DISKLABEL is not set
> -# CONFIG_MINIX_SUBPARTITION is not set
> -# CONFIG_SOLARIS_X86_PARTITION is not set
> -# CONFIG_UNIXWARE_DISKLABEL is not set
> -# CONFIG_LDM_PARTITION is not set
> -# CONFIG_SGI_PARTITION is not set
> -# CONFIG_ULTRIX_PARTITION is not set
> -# CONFIG_SUN_PARTITION is not set
> -# CONFIG_KARMA_PARTITION is not set
> -# CONFIG_EFI_PARTITION is not set
> -# CONFIG_SYSV68_PARTITION is not set
> -CONFIG_NLS=m
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -CONFIG_NLS_CODEPAGE_437=m
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -CONFIG_NLS_CODEPAGE_850=m
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -CONFIG_NLS_ISO8859_1=m
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -CONFIG_NLS_ISO8859_15=m
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -CONFIG_NLS_UTF8=m
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_FRAME_WARN=1024
> -CONFIG_MAGIC_SYSRQ=y
> -# CONFIG_UNUSED_SYMBOLS is not set
> -# CONFIG_DEBUG_FS is not set
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DEBUG_SHIRQ is not set
> -CONFIG_DETECT_SOFTLOCKUP=y
> -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
> -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
> -CONFIG_SCHED_DEBUG=y
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_TIMER_STATS is not set
> -# CONFIG_DEBUG_OBJECTS is not set
> -# CONFIG_DEBUG_SLAB is not set
> -# CONFIG_DEBUG_RT_MUTEXES is not set
> -# CONFIG_RT_MUTEX_TESTER is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -CONFIG_DEBUG_MUTEXES=y
> -# CONFIG_DEBUG_LOCK_ALLOC is not set
> -# CONFIG_PROVE_LOCKING is not set
> -# CONFIG_LOCK_STAT is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -CONFIG_DEBUG_BUGVERBOSE=y
> -# CONFIG_DEBUG_INFO is not set
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_WRITECOUNT is not set
> -# CONFIG_DEBUG_MEMORY_INIT is not set
> -# CONFIG_DEBUG_LIST is not set
> -# CONFIG_DEBUG_SG is not set
> -CONFIG_FRAME_POINTER=y
> -# CONFIG_BOOT_PRINTK_DELAY is not set
> -# CONFIG_RCU_TORTURE_TEST is not set
> -# CONFIG_BACKTRACE_SELF_TEST is not set
> -# CONFIG_FAULT_INJECTION is not set
> -# CONFIG_LATENCYTOP is not set
> -CONFIG_SYSCTL_SYSCALL_CHECK=y
> -CONFIG_HAVE_FTRACE=y
> -CONFIG_HAVE_DYNAMIC_FTRACE=y
> -# CONFIG_FTRACE is not set
> -# CONFIG_IRQSOFF_TRACER is not set
> -# CONFIG_SCHED_TRACER is not set
> -# CONFIG_CONTEXT_SWITCH_TRACER is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -# CONFIG_KGDB is not set
> -# CONFIG_DEBUG_USER is not set
> -CONFIG_DEBUG_ERRORS=y
> -# CONFIG_DEBUG_STACK_USAGE is not set
> -# CONFIG_DEBUG_LL is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITY_FILE_CAPABILITIES is not set
> -CONFIG_CRYPTO=y
> -
> -#
> -# Crypto core or helper
> -#
> -CONFIG_CRYPTO_ALGAPI=m
> -CONFIG_CRYPTO_BLKCIPHER=m
> -CONFIG_CRYPTO_MANAGER=m
> -# CONFIG_CRYPTO_GF128MUL is not set
> -# CONFIG_CRYPTO_NULL is not set
> -# CONFIG_CRYPTO_CRYPTD is not set
> -# CONFIG_CRYPTO_AUTHENC is not set
> -# CONFIG_CRYPTO_TEST is not set
> -
> -#
> -# Authenticated Encryption with Associated Data
> -#
> -# CONFIG_CRYPTO_CCM is not set
> -# CONFIG_CRYPTO_GCM is not set
> -# CONFIG_CRYPTO_SEQIV is not set
> -
> -#
> -# Block modes
> -#
> -# CONFIG_CRYPTO_CBC is not set
> -# CONFIG_CRYPTO_CTR is not set
> -# CONFIG_CRYPTO_CTS is not set
> -CONFIG_CRYPTO_ECB=m
> -# CONFIG_CRYPTO_LRW is not set
> -# CONFIG_CRYPTO_PCBC is not set
> -# CONFIG_CRYPTO_XTS is not set
> -
> -#
> -# Hash modes
> -#
> -# CONFIG_CRYPTO_HMAC is not set
> -# CONFIG_CRYPTO_XCBC is not set
> -
> -#
> -# Digest
> -#
> -# CONFIG_CRYPTO_CRC32C is not set
> -# CONFIG_CRYPTO_MD4 is not set
> -# CONFIG_CRYPTO_MD5 is not set
> -# CONFIG_CRYPTO_MICHAEL_MIC is not set
> -# CONFIG_CRYPTO_RMD128 is not set
> -# CONFIG_CRYPTO_RMD160 is not set
> -# CONFIG_CRYPTO_RMD256 is not set
> -# CONFIG_CRYPTO_RMD320 is not set
> -# CONFIG_CRYPTO_SHA1 is not set
> -# CONFIG_CRYPTO_SHA256 is not set
> -# CONFIG_CRYPTO_SHA512 is not set
> -# CONFIG_CRYPTO_TGR192 is not set
> -# CONFIG_CRYPTO_WP512 is not set
> -
> -#
> -# Ciphers
> -#
> -# CONFIG_CRYPTO_AES is not set
> -# CONFIG_CRYPTO_ANUBIS is not set
> -CONFIG_CRYPTO_ARC4=m
> -# CONFIG_CRYPTO_BLOWFISH is not set
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -# CONFIG_CRYPTO_CAST5 is not set
> -# CONFIG_CRYPTO_CAST6 is not set
> -# CONFIG_CRYPTO_DES is not set
> -# CONFIG_CRYPTO_FCRYPT is not set
> -# CONFIG_CRYPTO_KHAZAD is not set
> -# CONFIG_CRYPTO_SALSA20 is not set
> -# CONFIG_CRYPTO_SEED is not set
> -# CONFIG_CRYPTO_SERPENT is not set
> -# CONFIG_CRYPTO_TEA is not set
> -# CONFIG_CRYPTO_TWOFISH is not set
> -
> -#
> -# Compression
> -#
> -# CONFIG_CRYPTO_DEFLATE is not set
> -# CONFIG_CRYPTO_LZO is not set
> -CONFIG_CRYPTO_HW=y
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -# CONFIG_GENERIC_FIND_FIRST_BIT is not set
> -# CONFIG_GENERIC_FIND_NEXT_BIT is not set
> -CONFIG_CRC_CCITT=m
> -# CONFIG_CRC16 is not set
> -CONFIG_CRC_T10DIF=m
> -# CONFIG_CRC_ITU_T is not set
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_PLIST=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> diff --git a/arch/arm/configs/xcep_defconfig b/arch/arm/configs/xcep_defconfig
> deleted file mode 100644
> index 84a72ac..0000000
> --- a/arch/arm/configs/xcep_defconfig
> +++ /dev/null
> @@ -1,1128 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.31-rc6
> -# Thu Aug 20 09:02:37 2009
> -#
> -CONFIG_ARM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_MMU=y
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -CONFIG_CONSTRUCTORS=y
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=".xcep-itech"
> -# CONFIG_LOCALVERSION_AUTO is not set
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -# CONFIG_POSIX_MQUEUE is not set
> -CONFIG_BSD_PROCESS_ACCT=y
> -# CONFIG_BSD_PROCESS_ACCT_V3 is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -
> -#
> -# RCU Subsystem
> -#
> -CONFIG_CLASSIC_RCU=y
> -# CONFIG_TREE_RCU is not set
> -# CONFIG_PREEMPT_RCU is not set
> -# CONFIG_TREE_RCU_TRACE is not set
> -# CONFIG_PREEMPT_RCU_TRACE is not set
> -CONFIG_IKCONFIG=y
> -CONFIG_IKCONFIG_PROC=y
> -CONFIG_LOG_BUF_SHIFT=16
> -# CONFIG_GROUP_SCHED is not set
> -# CONFIG_CGROUPS is not set
> -CONFIG_SYSFS_DEPRECATED=y
> -CONFIG_SYSFS_DEPRECATED_V2=y
> -# CONFIG_RELAY is not set
> -# CONFIG_NAMESPACES is not set
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_INITRAMFS_SOURCE=""
> -CONFIG_RD_GZIP=y
> -# CONFIG_RD_BZIP2 is not set
> -# CONFIG_RD_LZMA is not set
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -CONFIG_ANON_INODES=y
> -CONFIG_EMBEDDED=y
> -# CONFIG_UID16 is not set
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -# CONFIG_SHMEM is not set
> -CONFIG_AIO=y
> -
> -#
> -# Performance Counters
> -#
> -# CONFIG_VM_EVENT_COUNTERS is not set
> -CONFIG_STRIP_ASM_SYMS=y
> -# CONFIG_COMPAT_BRK is not set
> -# CONFIG_SLAB is not set
> -# CONFIG_SLUB is not set
> -CONFIG_SLOB=y
> -# CONFIG_PROFILING is not set
> -CONFIG_TRACEPOINTS=y
> -CONFIG_MARKERS=y
> -CONFIG_HAVE_OPROFILE=y
> -CONFIG_KPROBES=y
> -CONFIG_KRETPROBES=y
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -CONFIG_HAVE_CLK=y
> -
> -#
> -# GCOV-based kernel profiling
> -#
> -# CONFIG_SLOW_WORK is not set
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_RT_MUTEXES=y
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -# CONFIG_MODULE_FORCE_UNLOAD is not set
> -CONFIG_MODVERSIONS=y
> -CONFIG_MODULE_SRCVERSION_ALL=y
> -# CONFIG_BLOCK is not set
> -# CONFIG_FREEZER is not set
> -
> -#
> -# System Type
> -#
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_GEMINI is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_STMP3XXX is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_MMP is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_W90X900 is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_MSM is not set
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_S3C64XX is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_U300 is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -# CONFIG_ARCH_GUMSTIX is not set
> -# CONFIG_MACH_INTELMOTE2 is not set
> -# CONFIG_MACH_STARGATE2 is not set
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_MACH_MP900C is not set
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_ARCH_VIPER is not set
> -# CONFIG_ARCH_PXA_ESERIES is not set
> -# CONFIG_TRIZEPS_PXA is not set
> -# CONFIG_MACH_H5000 is not set
> -# CONFIG_MACH_EM_X270 is not set
> -# CONFIG_MACH_EXEDA is not set
> -# CONFIG_MACH_COLIBRI is not set
> -# CONFIG_MACH_COLIBRI300 is not set
> -# CONFIG_MACH_COLIBRI320 is not set
> -# CONFIG_MACH_ZYLONITE is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_TAVOREVB is not set
> -# CONFIG_MACH_SAAR is not set
> -# CONFIG_MACH_ARMCORE is not set
> -# CONFIG_MACH_CM_X300 is not set
> -# CONFIG_MACH_H4700 is not set
> -# CONFIG_MACH_MAGICIAN is not set
> -# CONFIG_MACH_HIMALAYA is not set
> -# CONFIG_MACH_MIOA701 is not set
> -# CONFIG_MACH_PCM027 is not set
> -# CONFIG_ARCH_PXA_PALM is not set
> -# CONFIG_MACH_CSB726 is not set
> -# CONFIG_PXA_EZX is not set
> -CONFIG_MACH_XCEP=y
> -CONFIG_PXA25x=y
> -CONFIG_PXA_SSP=y
> -CONFIG_PLAT_PXA=y
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_PABRT_NOIFAR=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -CONFIG_COMMON_CLKDEV=y
> -
> -#
> -# Bus support
> -#
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -CONFIG_NO_HZ=y
> -CONFIG_HIGH_RES_TIMERS=y
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -CONFIG_VMSPLIT_3G=y
> -# CONFIG_VMSPLIT_2G is not set
> -# CONFIG_VMSPLIT_1G is not set
> -CONFIG_PAGE_OFFSET=0xC0000000
> -# CONFIG_PREEMPT is not set
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> -# CONFIG_HIGHMEM is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -CONFIG_PAGEFLAGS_EXTENDED=y
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_PHYS_ADDR_T_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=0
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_HAVE_MLOCK=y
> -CONFIG_HAVE_MLOCKED_PAGE_BIT=y
> -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
> -CONFIG_ALIGNMENT_TRAP=y
> -# CONFIG_UACCESS_WITH_MEMCPY is not set
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="root=mtd4 rootfstype=jffs2 ro console=ttyS0,115200"
> -# CONFIG_XIP_KERNEL is not set
> -# CONFIG_KEXEC is not set
> -
> -#
> -# CPU Power Management
> -#
> -# CONFIG_CPU_FREQ is not set
> -# CONFIG_CPU_IDLE is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> -CONFIG_HAVE_AOUT=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -# CONFIG_PM is not set
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_PACKET=m
> -CONFIG_PACKET_MMAP=y
> -CONFIG_UNIX=y
> -CONFIG_XFRM=y
> -# CONFIG_XFRM_USER is not set
> -# CONFIG_XFRM_SUB_POLICY is not set
> -# CONFIG_XFRM_MIGRATE is not set
> -# CONFIG_XFRM_STATISTICS is not set
> -CONFIG_NET_KEY=y
> -# CONFIG_NET_KEY_MIGRATE is not set
> -CONFIG_INET=y
> -CONFIG_IP_MULTICAST=y
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -CONFIG_IP_PNP_BOOTP=y
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_IP_MROUTE is not set
> -# CONFIG_ARPD is not set
> -# CONFIG_SYN_COOKIES is not set
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> -# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> -# CONFIG_INET_XFRM_MODE_BEET is not set
> -CONFIG_INET_LRO=y
> -# CONFIG_INET_DIAG is not set
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -# CONFIG_NETFILTER is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_NET_DSA is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_PHONET is not set
> -# CONFIG_IEEE802154 is not set
> -# CONFIG_NET_SCHED is not set
> -# CONFIG_DCB is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_NET_TCPPROBE is not set
> -# CONFIG_NET_DROP_MONITOR is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -# CONFIG_IRDA is not set
> -# CONFIG_BT is not set
> -# CONFIG_AF_RXRPC is not set
> -# CONFIG_WIRELESS is not set
> -# CONFIG_WIMAX is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -CONFIG_STANDALONE=y
> -# CONFIG_PREVENT_FIRMWARE_BUILD is not set
> -# CONFIG_FW_LOADER is not set
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_DEBUG_DEVRES is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -# CONFIG_CONNECTOR is not set
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -CONFIG_MTD_CONCAT=y
> -CONFIG_MTD_PARTITIONS=y
> -# CONFIG_MTD_TESTS is not set
> -# CONFIG_MTD_REDBOOT_PARTS is not set
> -# CONFIG_MTD_CMDLINE_PARTS is not set
> -# CONFIG_MTD_AFS_PARTS is not set
> -# CONFIG_MTD_AR7_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=y
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -# CONFIG_MTD_JEDECPROBE is not set
> -CONFIG_MTD_GEN_PROBE=y
> -# CONFIG_MTD_CFI_ADV_OPTIONS is not set
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -CONFIG_MTD_MAP_BANK_WIDTH_4=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -CONFIG_MTD_CFI_I2=y
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -# CONFIG_MTD_CFI_AMDSTD is not set
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -# CONFIG_MTD_RAM is not set
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -CONFIG_MTD_COMPLEX_MAPPINGS=y
> -CONFIG_MTD_PHYSMAP=y
> -# CONFIG_MTD_PHYSMAP_COMPAT is not set
> -CONFIG_MTD_PXA2XX=y
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -# CONFIG_MTD_NAND is not set
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# LPDDR flash memory drivers
> -#
> -# CONFIG_MTD_LPDDR is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -# CONFIG_MISC_DEVICES is not set
> -CONFIG_HAVE_IDE=y
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_SCSI_DMA is not set
> -# CONFIG_SCSI_NETLINK is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_MACVLAN is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -# CONFIG_VETH is not set
> -# CONFIG_PHYLIB is not set
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=y
> -# CONFIG_AX88796 is not set
> -CONFIG_SMC91X=y
> -# CONFIG_DM9000 is not set
> -# CONFIG_ETHOC is not set
> -# CONFIG_SMC911X is not set
> -# CONFIG_SMSC911X is not set
> -# CONFIG_DNET is not set
> -# CONFIG_IBM_NEW_EMAC_ZMII is not set
> -# CONFIG_IBM_NEW_EMAC_RGMII is not set
> -# CONFIG_IBM_NEW_EMAC_TAH is not set
> -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
> -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
> -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
> -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
> -# CONFIG_B44 is not set
> -# CONFIG_KS8842 is not set
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -
> -#
> -# Wireless LAN
> -#
> -# CONFIG_WLAN_PRE80211 is not set
> -# CONFIG_WLAN_80211 is not set
> -
> -#
> -# Enable WiMAX (Networking options) to see the WiMAX drivers
> -#
> -# CONFIG_WAN is not set
> -# CONFIG_PPP is not set
> -# CONFIG_SLIP is not set
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_ISDN is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -# CONFIG_INPUT_MOUSEDEV is not set
> -# CONFIG_INPUT_JOYDEV is not set
> -# CONFIG_INPUT_EVDEV is not set
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -# CONFIG_INPUT_KEYBOARD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -# CONFIG_INPUT_TOUCHSCREEN is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -# CONFIG_SERIO is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_CONSOLE_TRANSLATIONS=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -# CONFIG_DEVKMEM is not set
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -# CONFIG_SERIAL_8250 is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_PXA=y
> -CONFIG_SERIAL_PXA_CONSOLE=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
> -# CONFIG_LEGACY_PTYS is not set
> -# CONFIG_IPMI_HANDLER is not set
> -# CONFIG_HW_RANDOM is not set
> -# CONFIG_R3964 is not set
> -# CONFIG_TCG_TPM is not set
> -CONFIG_I2C=m
> -CONFIG_I2C_BOARDINFO=y
> -CONFIG_I2C_CHARDEV=m
> -CONFIG_I2C_HELPER_AUTO=y
> -
> -#
> -# I2C Hardware Bus support
> -#
> -
> -#
> -# I2C system bus drivers (mostly embedded / system-on-chip)
> -#
> -# CONFIG_I2C_DESIGNWARE is not set
> -# CONFIG_I2C_GPIO is not set
> -# CONFIG_I2C_OCORES is not set
> -CONFIG_I2C_PXA=m
> -# CONFIG_I2C_PXA_SLAVE is not set
> -# CONFIG_I2C_SIMTEC is not set
> -
> -#
> -# External I2C/SMBus adapter drivers
> -#
> -# CONFIG_I2C_PARPORT_LIGHT is not set
> -# CONFIG_I2C_TAOS_EVM is not set
> -
> -#
> -# Other I2C/SMBus bus drivers
> -#
> -# CONFIG_I2C_PCA_PLATFORM is not set
> -# CONFIG_I2C_STUB is not set
> -
> -#
> -# Miscellaneous I2C Chip support
> -#
> -# CONFIG_DS1682 is not set
> -# CONFIG_SENSORS_PCF8574 is not set
> -# CONFIG_PCF8575 is not set
> -# CONFIG_SENSORS_PCA9539 is not set
> -# CONFIG_SENSORS_TSL2550 is not set
> -# CONFIG_I2C_DEBUG_CORE is not set
> -# CONFIG_I2C_DEBUG_ALGO is not set
> -# CONFIG_I2C_DEBUG_BUS is not set
> -# CONFIG_I2C_DEBUG_CHIP is not set
> -# CONFIG_SPI is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -# CONFIG_DEBUG_GPIO is not set
> -# CONFIG_GPIO_SYSFS is not set
> -
> -#
> -# Memory mapped GPIO expanders:
> -#
> -
> -#
> -# I2C GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX732X is not set
> -# CONFIG_GPIO_PCA953X is not set
> -# CONFIG_GPIO_PCF857X is not set
> -
> -#
> -# PCI GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -# CONFIG_W1 is not set
> -# CONFIG_POWER_SUPPLY is not set
> -CONFIG_HWMON=m
> -# CONFIG_HWMON_VID is not set
> -# CONFIG_SENSORS_AD7414 is not set
> -# CONFIG_SENSORS_AD7418 is not set
> -CONFIG_SENSORS_ADM1021=m
> -# CONFIG_SENSORS_ADM1025 is not set
> -# CONFIG_SENSORS_ADM1026 is not set
> -# CONFIG_SENSORS_ADM1029 is not set
> -# CONFIG_SENSORS_ADM1031 is not set
> -# CONFIG_SENSORS_ADM9240 is not set
> -# CONFIG_SENSORS_ADT7462 is not set
> -# CONFIG_SENSORS_ADT7470 is not set
> -# CONFIG_SENSORS_ADT7473 is not set
> -# CONFIG_SENSORS_ADT7475 is not set
> -# CONFIG_SENSORS_ATXP1 is not set
> -# CONFIG_SENSORS_DS1621 is not set
> -# CONFIG_SENSORS_F71805F is not set
> -# CONFIG_SENSORS_F71882FG is not set
> -# CONFIG_SENSORS_F75375S is not set
> -# CONFIG_SENSORS_G760A is not set
> -# CONFIG_SENSORS_GL518SM is not set
> -# CONFIG_SENSORS_GL520SM is not set
> -# CONFIG_SENSORS_IT87 is not set
> -# CONFIG_SENSORS_LM63 is not set
> -# CONFIG_SENSORS_LM75 is not set
> -# CONFIG_SENSORS_LM77 is not set
> -# CONFIG_SENSORS_LM78 is not set
> -# CONFIG_SENSORS_LM80 is not set
> -# CONFIG_SENSORS_LM83 is not set
> -# CONFIG_SENSORS_LM85 is not set
> -# CONFIG_SENSORS_LM87 is not set
> -# CONFIG_SENSORS_LM90 is not set
> -# CONFIG_SENSORS_LM92 is not set
> -# CONFIG_SENSORS_LM93 is not set
> -# CONFIG_SENSORS_LTC4215 is not set
> -# CONFIG_SENSORS_LTC4245 is not set
> -# CONFIG_SENSORS_LM95241 is not set
> -# CONFIG_SENSORS_MAX1619 is not set
> -CONFIG_SENSORS_MAX6650=m
> -# CONFIG_SENSORS_PC87360 is not set
> -# CONFIG_SENSORS_PC87427 is not set
> -# CONFIG_SENSORS_PCF8591 is not set
> -# CONFIG_SENSORS_SHT15 is not set
> -# CONFIG_SENSORS_DME1737 is not set
> -# CONFIG_SENSORS_SMSC47M1 is not set
> -# CONFIG_SENSORS_SMSC47M192 is not set
> -# CONFIG_SENSORS_SMSC47B397 is not set
> -# CONFIG_SENSORS_ADS7828 is not set
> -# CONFIG_SENSORS_THMC50 is not set
> -# CONFIG_SENSORS_TMP401 is not set
> -# CONFIG_SENSORS_VT1211 is not set
> -# CONFIG_SENSORS_W83781D is not set
> -# CONFIG_SENSORS_W83791D is not set
> -# CONFIG_SENSORS_W83792D is not set
> -# CONFIG_SENSORS_W83793 is not set
> -# CONFIG_SENSORS_W83L785TS is not set
> -# CONFIG_SENSORS_W83L786NG is not set
> -# CONFIG_SENSORS_W83627HF is not set
> -# CONFIG_SENSORS_W83627EHF is not set
> -# CONFIG_HWMON_DEBUG_CHIP is not set
> -# CONFIG_THERMAL is not set
> -# CONFIG_WATCHDOG is not set
> -CONFIG_SSB_POSSIBLE=y
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_CORE is not set
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_MFD_ASIC3 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -# CONFIG_TPS65010 is not set
> -# CONFIG_MFD_TMIO is not set
> -# CONFIG_MFD_T7L66XB is not set
> -# CONFIG_MFD_TC6387XB is not set
> -# CONFIG_MFD_TC6393XB is not set
> -# CONFIG_MFD_WM8400 is not set
> -# CONFIG_MFD_WM8350_I2C is not set
> -# CONFIG_MFD_PCF50633 is not set
> -# CONFIG_AB3100_CORE is not set
> -# CONFIG_MEDIA_SUPPORT is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -# CONFIG_FB is not set
> -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -# CONFIG_SOUND is not set
> -# CONFIG_HID_SUPPORT is not set
> -# CONFIG_USB_SUPPORT is not set
> -# CONFIG_MMC is not set
> -# CONFIG_MEMSTICK is not set
> -# CONFIG_ACCESSIBILITY is not set
> -# CONFIG_NEW_LEDS is not set
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=m
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -# CONFIG_RTC_DRV_TEST is not set
> -
> -#
> -# I2C RTC drivers
> -#
> -# CONFIG_RTC_DRV_DS1307 is not set
> -# CONFIG_RTC_DRV_DS1374 is not set
> -# CONFIG_RTC_DRV_DS1672 is not set
> -# CONFIG_RTC_DRV_MAX6900 is not set
> -# CONFIG_RTC_DRV_RS5C372 is not set
> -# CONFIG_RTC_DRV_ISL1208 is not set
> -# CONFIG_RTC_DRV_X1205 is not set
> -# CONFIG_RTC_DRV_PCF8563 is not set
> -# CONFIG_RTC_DRV_PCF8583 is not set
> -# CONFIG_RTC_DRV_M41T80 is not set
> -# CONFIG_RTC_DRV_S35390A is not set
> -# CONFIG_RTC_DRV_FM3130 is not set
> -# CONFIG_RTC_DRV_RX8581 is not set
> -# CONFIG_RTC_DRV_RX8025 is not set
> -
> -#
> -# SPI RTC drivers
> -#
> -
> -#
> -# Platform RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_DS1286 is not set
> -# CONFIG_RTC_DRV_DS1511 is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_STK17TA8 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -# CONFIG_RTC_DRV_M48T35 is not set
> -# CONFIG_RTC_DRV_M48T59 is not set
> -# CONFIG_RTC_DRV_BQ4802 is not set
> -# CONFIG_RTC_DRV_V3020 is not set
> -
> -#
> -# on-CPU RTC drivers
> -#
> -CONFIG_RTC_DRV_SA1100=m
> -# CONFIG_RTC_DRV_PXA is not set
> -CONFIG_DMADEVICES=y
> -
> -#
> -# DMA Devices
> -#
> -# CONFIG_AUXDISPLAY is not set
> -# CONFIG_REGULATOR is not set
> -# CONFIG_UIO is not set
> -# CONFIG_STAGING is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_FILE_LOCKING=y
> -# CONFIG_FSNOTIFY is not set
> -# CONFIG_DNOTIFY is not set
> -# CONFIG_INOTIFY is not set
> -# CONFIG_INOTIFY_USER is not set
> -# CONFIG_QUOTA is not set
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# Caches
> -#
> -# CONFIG_FSCACHE is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_PROC_PAGE_MONITOR=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -CONFIG_MISC_FILESYSTEMS=y
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -CONFIG_JFFS2_FS_WBUF_VERIFY=y
> -# CONFIG_JFFS2_SUMMARY is not set
> -# CONFIG_JFFS2_FS_XATTR is not set
> -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
> -CONFIG_JFFS2_ZLIB=y
> -# CONFIG_JFFS2_LZO is not set
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_ROMFS_FS is not set
> -CONFIG_NETWORK_FILESYSTEMS=y
> -CONFIG_NFS_FS=m
> -CONFIG_NFS_V3=y
> -# CONFIG_NFS_V3_ACL is not set
> -# CONFIG_NFS_V4 is not set
> -# CONFIG_NFSD is not set
> -CONFIG_LOCKD=m
> -CONFIG_LOCKD_V4=y
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=m
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -# CONFIG_CIFS is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -CONFIG_NLS=m
> -CONFIG_NLS_DEFAULT="utf8"
> -# CONFIG_NLS_CODEPAGE_437 is not set
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -# CONFIG_NLS_CODEPAGE_850 is not set
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -# CONFIG_NLS_ISO8859_1 is not set
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -# CONFIG_NLS_ISO8859_15 is not set
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -CONFIG_NLS_UTF8=m
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -CONFIG_PRINTK_TIME=y
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_FRAME_WARN=1024
> -# CONFIG_MAGIC_SYSRQ is not set
> -# CONFIG_UNUSED_SYMBOLS is not set
> -# CONFIG_DEBUG_FS is not set
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DEBUG_SHIRQ is not set
> -CONFIG_DETECT_SOFTLOCKUP=y
> -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
> -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
> -CONFIG_DETECT_HUNG_TASK=y
> -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
> -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
> -# CONFIG_SCHED_DEBUG is not set
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_TIMER_STATS is not set
> -# CONFIG_DEBUG_OBJECTS is not set
> -# CONFIG_DEBUG_KMEMLEAK is not set
> -# CONFIG_DEBUG_RT_MUTEXES is not set
> -# CONFIG_RT_MUTEX_TESTER is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -# CONFIG_DEBUG_MUTEXES is not set
> -# CONFIG_DEBUG_LOCK_ALLOC is not set
> -# CONFIG_PROVE_LOCKING is not set
> -# CONFIG_LOCK_STAT is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -# CONFIG_DEBUG_BUGVERBOSE is not set
> -# CONFIG_DEBUG_INFO is not set
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_WRITECOUNT is not set
> -# CONFIG_DEBUG_MEMORY_INIT is not set
> -# CONFIG_DEBUG_LIST is not set
> -# CONFIG_DEBUG_SG is not set
> -# CONFIG_DEBUG_NOTIFIERS is not set
> -CONFIG_FRAME_POINTER=y
> -# CONFIG_BOOT_PRINTK_DELAY is not set
> -# CONFIG_RCU_TORTURE_TEST is not set
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -# CONFIG_KPROBES_SANITY_TEST is not set
> -# CONFIG_BACKTRACE_SELF_TEST is not set
> -# CONFIG_FAULT_INJECTION is not set
> -# CONFIG_LATENCYTOP is not set
> -CONFIG_SYSCTL_SYSCALL_CHECK=y
> -# CONFIG_PAGE_POISONING is not set
> -CONFIG_HAVE_FUNCTION_TRACER=y
> -CONFIG_TRACING_SUPPORT=y
> -# CONFIG_FTRACE is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -# CONFIG_KGDB is not set
> -# CONFIG_ARM_UNWIND is not set
> -# CONFIG_DEBUG_USER is not set
> -# CONFIG_DEBUG_ERRORS is not set
> -# CONFIG_DEBUG_STACK_USAGE is not set
> -# CONFIG_DEBUG_LL is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITYFS is not set
> -# CONFIG_SECURITY_FILE_CAPABILITIES is not set
> -CONFIG_CRYPTO=y
> -
> -#
> -# Crypto core or helper
> -#
> -# CONFIG_CRYPTO_FIPS is not set
> -CONFIG_CRYPTO_ALGAPI=m
> -CONFIG_CRYPTO_ALGAPI2=m
> -CONFIG_CRYPTO_HASH=m
> -CONFIG_CRYPTO_HASH2=m
> -# CONFIG_CRYPTO_MANAGER is not set
> -# CONFIG_CRYPTO_MANAGER2 is not set
> -# CONFIG_CRYPTO_GF128MUL is not set
> -# CONFIG_CRYPTO_NULL is not set
> -# CONFIG_CRYPTO_CRYPTD is not set
> -# CONFIG_CRYPTO_AUTHENC is not set
> -# CONFIG_CRYPTO_TEST is not set
> -
> -#
> -# Authenticated Encryption with Associated Data
> -#
> -# CONFIG_CRYPTO_CCM is not set
> -# CONFIG_CRYPTO_GCM is not set
> -# CONFIG_CRYPTO_SEQIV is not set
> -
> -#
> -# Block modes
> -#
> -# CONFIG_CRYPTO_CBC is not set
> -# CONFIG_CRYPTO_CTR is not set
> -# CONFIG_CRYPTO_CTS is not set
> -# CONFIG_CRYPTO_ECB is not set
> -# CONFIG_CRYPTO_LRW is not set
> -# CONFIG_CRYPTO_PCBC is not set
> -# CONFIG_CRYPTO_XTS is not set
> -
> -#
> -# Hash modes
> -#
> -# CONFIG_CRYPTO_HMAC is not set
> -# CONFIG_CRYPTO_XCBC is not set
> -
> -#
> -# Digest
> -#
> -CONFIG_CRYPTO_CRC32C=m
> -# CONFIG_CRYPTO_MD4 is not set
> -# CONFIG_CRYPTO_MD5 is not set
> -# CONFIG_CRYPTO_MICHAEL_MIC is not set
> -# CONFIG_CRYPTO_RMD128 is not set
> -# CONFIG_CRYPTO_RMD160 is not set
> -# CONFIG_CRYPTO_RMD256 is not set
> -# CONFIG_CRYPTO_RMD320 is not set
> -# CONFIG_CRYPTO_SHA1 is not set
> -# CONFIG_CRYPTO_SHA256 is not set
> -# CONFIG_CRYPTO_SHA512 is not set
> -# CONFIG_CRYPTO_TGR192 is not set
> -# CONFIG_CRYPTO_WP512 is not set
> -
> -#
> -# Ciphers
> -#
> -# CONFIG_CRYPTO_AES is not set
> -# CONFIG_CRYPTO_ANUBIS is not set
> -# CONFIG_CRYPTO_ARC4 is not set
> -# CONFIG_CRYPTO_BLOWFISH is not set
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -# CONFIG_CRYPTO_CAST5 is not set
> -# CONFIG_CRYPTO_CAST6 is not set
> -# CONFIG_CRYPTO_DES is not set
> -# CONFIG_CRYPTO_FCRYPT is not set
> -# CONFIG_CRYPTO_KHAZAD is not set
> -# CONFIG_CRYPTO_SALSA20 is not set
> -# CONFIG_CRYPTO_SEED is not set
> -# CONFIG_CRYPTO_SERPENT is not set
> -# CONFIG_CRYPTO_TEA is not set
> -# CONFIG_CRYPTO_TWOFISH is not set
> -
> -#
> -# Compression
> -#
> -# CONFIG_CRYPTO_DEFLATE is not set
> -# CONFIG_CRYPTO_ZLIB is not set
> -# CONFIG_CRYPTO_LZO is not set
> -
> -#
> -# Random Number Generation
> -#
> -# CONFIG_CRYPTO_ANSI_CPRNG is not set
> -# CONFIG_CRYPTO_HW is not set
> -# CONFIG_BINARY_PRINTF is not set
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -CONFIG_GENERIC_FIND_LAST_BIT=y
> -# CONFIG_CRC_CCITT is not set
> -# CONFIG_CRC16 is not set
> -# CONFIG_CRC_T10DIF is not set
> -# CONFIG_CRC_ITU_T is not set
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -CONFIG_LIBCRC32C=m
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_DECOMPRESS_GZIP=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> -CONFIG_NLATTR=y
> diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig
> deleted file mode 100644
> index fca5ff6..0000000
> --- a/arch/arm/configs/zeus_defconfig
> +++ /dev/null
> @@ -1,2031 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.32
> -# Tue Dec ?8 20:27:05 2009
> -#
> -CONFIG_ARM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_GENERIC_CLOCKEVENTS=y
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -CONFIG_ARCH_HAS_CPUFREQ=y
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_ARCH_MTD_XIP=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -CONFIG_CONSTRUCTORS=y
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=""
> -CONFIG_LOCALVERSION_AUTO=y
> -CONFIG_SWAP=y
> -CONFIG_SYSVIPC=y
> -CONFIG_SYSVIPC_SYSCTL=y
> -# CONFIG_POSIX_MQUEUE is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -# CONFIG_TASKSTATS is not set
> -# CONFIG_AUDIT is not set
> -
> -#
> -# RCU Subsystem
> -#
> -# CONFIG_TREE_RCU is not set
> -# CONFIG_TREE_PREEMPT_RCU is not set
> -CONFIG_TINY_RCU=y
> -# CONFIG_TREE_RCU_TRACE is not set
> -# CONFIG_IKCONFIG is not set
> -CONFIG_LOG_BUF_SHIFT=13
> -# CONFIG_GROUP_SCHED is not set
> -# CONFIG_CGROUPS is not set
> -# CONFIG_SYSFS_DEPRECATED_V2 is not set
> -# CONFIG_RELAY is not set
> -CONFIG_NAMESPACES=y
> -# CONFIG_UTS_NS is not set
> -# CONFIG_IPC_NS is not set
> -# CONFIG_USER_NS is not set
> -# CONFIG_PID_NS is not set
> -# CONFIG_NET_NS is not set
> -# CONFIG_BLK_DEV_INITRD is not set
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -CONFIG_ANON_INODES=y
> -# CONFIG_EMBEDDED is not set
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -# CONFIG_KALLSYMS_ALL is not set
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -CONFIG_SHMEM=y
> -CONFIG_AIO=y
> -
> -#
> -# Kernel Performance Events And Counters
> -#
> -CONFIG_VM_EVENT_COUNTERS=y
> -CONFIG_SLUB_DEBUG=y
> -CONFIG_COMPAT_BRK=y
> -# CONFIG_SLAB is not set
> -CONFIG_SLUB=y
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -CONFIG_HAVE_OPROFILE=y
> -# CONFIG_KPROBES is not set
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -CONFIG_HAVE_CLK=y
> -
> -#
> -# GCOV-based kernel profiling
> -#
> -# CONFIG_SLOW_WORK is not set
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_SLABINFO=y
> -CONFIG_RT_MUTEXES=y
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -# CONFIG_MODULE_FORCE_UNLOAD is not set
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -CONFIG_BLOCK=y
> -CONFIG_LBDAF=y
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_BLK_DEV_INTEGRITY is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_DEADLINE=y
> -# CONFIG_IOSCHED_CFQ is not set
> -CONFIG_DEFAULT_DEADLINE=y
> -# CONFIG_DEFAULT_CFQ is not set
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="deadline"
> -# CONFIG_INLINE_SPIN_TRYLOCK is not set
> -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
> -# CONFIG_INLINE_SPIN_LOCK is not set
> -# CONFIG_INLINE_SPIN_LOCK_BH is not set
> -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
> -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
> -CONFIG_INLINE_SPIN_UNLOCK=y
> -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
> -CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
> -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
> -# CONFIG_INLINE_READ_TRYLOCK is not set
> -# CONFIG_INLINE_READ_LOCK is not set
> -# CONFIG_INLINE_READ_LOCK_BH is not set
> -# CONFIG_INLINE_READ_LOCK_IRQ is not set
> -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
> -CONFIG_INLINE_READ_UNLOCK=y
> -# CONFIG_INLINE_READ_UNLOCK_BH is not set
> -CONFIG_INLINE_READ_UNLOCK_IRQ=y
> -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
> -# CONFIG_INLINE_WRITE_TRYLOCK is not set
> -# CONFIG_INLINE_WRITE_LOCK is not set
> -# CONFIG_INLINE_WRITE_LOCK_BH is not set
> -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
> -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
> -CONFIG_INLINE_WRITE_UNLOCK=y
> -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
> -CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
> -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
> -# CONFIG_MUTEX_SPIN_ON_OWNER is not set
> -CONFIG_FREEZER=y
> -
> -#
> -# System Type
> -#
> -CONFIG_MMU=y
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_GEMINI is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_STMP3XXX is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_NOMADIK is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_DOVE is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_MMP is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_W90X900 is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -CONFIG_ARCH_PXA=y
> -# CONFIG_ARCH_MSM is not set
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_S3C64XX is not set
> -# CONFIG_ARCH_S5PC1XX is not set
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_U300 is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_ARCH_BCMRING is not set
> -# CONFIG_ARCH_U8500 is not set
> -
> -#
> -# Intel PXA2xx/PXA3xx Implementations
> -#
> -
> -#
> -# Intel/Marvell Dev Platforms (sorted by hardware release time)
> -#
> -# CONFIG_ARCH_LUBBOCK is not set
> -# CONFIG_MACH_MAINSTONE is not set
> -# CONFIG_MACH_ZYLONITE300 is not set
> -# CONFIG_MACH_ZYLONITE320 is not set
> -# CONFIG_MACH_LITTLETON is not set
> -# CONFIG_MACH_TAVOREVB is not set
> -# CONFIG_MACH_SAAR is not set
> -
> -#
> -# Third Party Dev Platforms (sorted by vendor name)
> -#
> -# CONFIG_ARCH_PXA_IDP is not set
> -# CONFIG_ARCH_VIPER is not set
> -CONFIG_MACH_ARCOM_ZEUS=y
> -# CONFIG_MACH_BALLOON3 is not set
> -# CONFIG_MACH_CSB726 is not set
> -# CONFIG_MACH_ARMCORE is not set
> -# CONFIG_MACH_EM_X270 is not set
> -# CONFIG_MACH_EXEDA is not set
> -# CONFIG_MACH_CM_X300 is not set
> -# CONFIG_ARCH_GUMSTIX is not set
> -# CONFIG_MACH_INTELMOTE2 is not set
> -# CONFIG_MACH_STARGATE2 is not set
> -# CONFIG_MACH_XCEP is not set
> -# CONFIG_TRIZEPS_PXA is not set
> -CONFIG_ARCOM_PCMCIA=y
> -# CONFIG_MACH_LOGICPD_PXA270 is not set
> -# CONFIG_MACH_PCM027 is not set
> -# CONFIG_MACH_COLIBRI is not set
> -# CONFIG_MACH_COLIBRI300 is not set
> -# CONFIG_MACH_COLIBRI320 is not set
> -
> -#
> -# End-user Products (sorted by vendor name)
> -#
> -# CONFIG_MACH_H4700 is not set
> -# CONFIG_MACH_H5000 is not set
> -# CONFIG_MACH_HIMALAYA is not set
> -# CONFIG_MACH_MAGICIAN is not set
> -# CONFIG_MACH_MIOA701 is not set
> -# CONFIG_PXA_EZX is not set
> -# CONFIG_MACH_MP900C is not set
> -# CONFIG_ARCH_PXA_PALM is not set
> -# CONFIG_PXA_SHARPSL is not set
> -# CONFIG_ARCH_PXA_ESERIES is not set
> -CONFIG_PXA27x=y
> -CONFIG_PXA_SSP=y
> -CONFIG_PXA_HAVE_BOARD_IRQS=y
> -CONFIG_PXA_HAVE_ISA_IRQS=y
> -CONFIG_PLAT_PXA=y
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_XSCALE=y
> -CONFIG_CPU_32v5=y
> -CONFIG_CPU_ABRT_EV5T=y
> -CONFIG_CPU_PABRT_LEGACY=y
> -CONFIG_CPU_CACHE_VIVT=y
> -CONFIG_CPU_TLB_V4WBI=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -CONFIG_ARM_L1_CACHE_SHIFT=5
> -CONFIG_IWMMXT=y
> -CONFIG_XSCALE_PMU=y
> -CONFIG_COMMON_CLKDEV=y
> -
> -#
> -# Bus support
> -#
> -CONFIG_ISA=y
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -CONFIG_PCCARD=m
> -CONFIG_PCMCIA=m
> -CONFIG_PCMCIA_LOAD_CIS=y
> -CONFIG_PCMCIA_IOCTL=y
> -
> -#
> -# PC-card bridges
> -#
> -# CONFIG_I82365 is not set
> -# CONFIG_TCIC is not set
> -CONFIG_PCMCIA_SOC_COMMON=m
> -CONFIG_PCMCIA_PXA2XX=m
> -# CONFIG_PCMCIA_DEBUG is not set
> -CONFIG_PCMCIA_PROBE=y
> -
> -#
> -# Kernel Features
> -#
> -CONFIG_TICK_ONESHOT=y
> -# CONFIG_NO_HZ is not set
> -# CONFIG_HIGH_RES_TIMERS is not set
> -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
> -CONFIG_VMSPLIT_3G=y
> -# CONFIG_VMSPLIT_2G is not set
> -# CONFIG_VMSPLIT_1G is not set
> -CONFIG_PAGE_OFFSET=0xC0000000
> -CONFIG_PREEMPT_NONE=y
> -# CONFIG_PREEMPT_VOLUNTARY is not set
> -# CONFIG_PREEMPT is not set
> -CONFIG_HZ=100
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
> -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> -# CONFIG_HIGHMEM is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -CONFIG_FLATMEM_MANUAL=y
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -# CONFIG_SPARSEMEM_MANUAL is not set
> -CONFIG_FLATMEM=y
> -CONFIG_FLAT_NODE_MEM_MAP=y
> -CONFIG_PAGEFLAGS_EXTENDED=y
> -CONFIG_SPLIT_PTLOCK_CPUS=4096
> -# CONFIG_PHYS_ADDR_T_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=0
> -CONFIG_VIRT_TO_BUS=y
> -CONFIG_HAVE_MLOCK=y
> -CONFIG_HAVE_MLOCKED_PAGE_BIT=y
> -# CONFIG_KSM is not set
> -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
> -CONFIG_ALIGNMENT_TRAP=y
> -# CONFIG_UACCESS_WITH_MEMCPY is not set
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0x0
> -CONFIG_ZBOOT_ROM_BSS=0x0
> -CONFIG_CMDLINE="root=31:02 rootfstype=jffs2 ro console=ttyS0,115200"
> -# CONFIG_XIP_KERNEL is not set
> -# CONFIG_KEXEC is not set
> -
> -#
> -# CPU Power Management
> -#
> -CONFIG_CPU_FREQ=y
> -CONFIG_CPU_FREQ_TABLE=y
> -# CONFIG_CPU_FREQ_DEBUG is not set
> -CONFIG_CPU_FREQ_STAT=y
> -# CONFIG_CPU_FREQ_STAT_DETAILS is not set
> -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
> -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
> -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
> -CONFIG_CPU_FREQ_GOV_POWERSAVE=m
> -CONFIG_CPU_FREQ_GOV_USERSPACE=m
> -CONFIG_CPU_FREQ_GOV_ONDEMAND=m
> -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
> -# CONFIG_CPU_IDLE is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -CONFIG_FPE_NWFPE=y
> -# CONFIG_FPE_NWFPE_XP is not set
> -# CONFIG_FPE_FASTFPE is not set
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> -CONFIG_HAVE_AOUT=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -CONFIG_PM=y
> -# CONFIG_PM_DEBUG is not set
> -CONFIG_PM_SLEEP=y
> -CONFIG_SUSPEND=y
> -CONFIG_SUSPEND_FREEZER=y
> -CONFIG_APM_EMULATION=y
> -# CONFIG_PM_RUNTIME is not set
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -CONFIG_NET=y
> -
> -#
> -# Networking options
> -#
> -CONFIG_PACKET=y
> -# CONFIG_PACKET_MMAP is not set
> -CONFIG_UNIX=y
> -CONFIG_XFRM=y
> -# CONFIG_XFRM_USER is not set
> -# CONFIG_XFRM_SUB_POLICY is not set
> -# CONFIG_XFRM_MIGRATE is not set
> -# CONFIG_XFRM_STATISTICS is not set
> -# CONFIG_NET_KEY is not set
> -CONFIG_INET=y
> -# CONFIG_IP_MULTICAST is not set
> -# CONFIG_IP_ADVANCED_ROUTER is not set
> -CONFIG_IP_FIB_HASH=y
> -CONFIG_IP_PNP=y
> -CONFIG_IP_PNP_DHCP=y
> -# CONFIG_IP_PNP_BOOTP is not set
> -# CONFIG_IP_PNP_RARP is not set
> -# CONFIG_NET_IPIP is not set
> -# CONFIG_NET_IPGRE is not set
> -# CONFIG_ARPD is not set
> -CONFIG_SYN_COOKIES=y
> -# CONFIG_INET_AH is not set
> -# CONFIG_INET_ESP is not set
> -# CONFIG_INET_IPCOMP is not set
> -# CONFIG_INET_XFRM_TUNNEL is not set
> -# CONFIG_INET_TUNNEL is not set
> -CONFIG_INET_XFRM_MODE_TRANSPORT=y
> -CONFIG_INET_XFRM_MODE_TUNNEL=y
> -CONFIG_INET_XFRM_MODE_BEET=y
> -# CONFIG_INET_LRO is not set
> -CONFIG_INET_DIAG=y
> -CONFIG_INET_TCP_DIAG=y
> -# CONFIG_TCP_CONG_ADVANCED is not set
> -CONFIG_TCP_CONG_CUBIC=y
> -CONFIG_DEFAULT_TCP_CONG="cubic"
> -# CONFIG_TCP_MD5SIG is not set
> -# CONFIG_IPV6 is not set
> -# CONFIG_NETWORK_SECMARK is not set
> -# CONFIG_NETFILTER is not set
> -# CONFIG_IP_DCCP is not set
> -# CONFIG_IP_SCTP is not set
> -# CONFIG_RDS is not set
> -# CONFIG_TIPC is not set
> -# CONFIG_ATM is not set
> -# CONFIG_BRIDGE is not set
> -# CONFIG_NET_DSA is not set
> -# CONFIG_VLAN_8021Q is not set
> -# CONFIG_DECNET is not set
> -# CONFIG_LLC2 is not set
> -# CONFIG_IPX is not set
> -# CONFIG_ATALK is not set
> -# CONFIG_X25 is not set
> -# CONFIG_LAPB is not set
> -# CONFIG_ECONET is not set
> -# CONFIG_WAN_ROUTER is not set
> -# CONFIG_PHONET is not set
> -# CONFIG_IEEE802154 is not set
> -# CONFIG_NET_SCHED is not set
> -# CONFIG_DCB is not set
> -
> -#
> -# Network testing
> -#
> -# CONFIG_NET_PKTGEN is not set
> -# CONFIG_HAMRADIO is not set
> -# CONFIG_CAN is not set
> -# CONFIG_IRDA is not set
> -CONFIG_BT=m
> -CONFIG_BT_L2CAP=m
> -# CONFIG_BT_SCO is not set
> -CONFIG_BT_RFCOMM=m
> -CONFIG_BT_RFCOMM_TTY=y
> -CONFIG_BT_BNEP=m
> -# CONFIG_BT_BNEP_MC_FILTER is not set
> -# CONFIG_BT_BNEP_PROTO_FILTER is not set
> -# CONFIG_BT_HIDP is not set
> -
> -#
> -# Bluetooth device drivers
> -#
> -# CONFIG_BT_HCIBTUSB is not set
> -# CONFIG_BT_HCIBTSDIO is not set
> -CONFIG_BT_HCIUART=m
> -CONFIG_BT_HCIUART_H4=y
> -CONFIG_BT_HCIUART_BCSP=y
> -# CONFIG_BT_HCIUART_LL is not set
> -# CONFIG_BT_HCIBCM203X is not set
> -# CONFIG_BT_HCIBPA10X is not set
> -# CONFIG_BT_HCIBFUSB is not set
> -# CONFIG_BT_HCIDTL1 is not set
> -# CONFIG_BT_HCIBT3C is not set
> -# CONFIG_BT_HCIBLUECARD is not set
> -# CONFIG_BT_HCIBTUART is not set
> -# CONFIG_BT_HCIVHCI is not set
> -# CONFIG_BT_MRVL is not set
> -# CONFIG_AF_RXRPC is not set
> -CONFIG_WIRELESS=y
> -CONFIG_WIRELESS_EXT=y
> -CONFIG_WEXT_CORE=y
> -CONFIG_WEXT_PROC=y
> -CONFIG_WEXT_SPY=y
> -CONFIG_WEXT_PRIV=y
> -CONFIG_CFG80211=m
> -# CONFIG_NL80211_TESTMODE is not set
> -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
> -# CONFIG_CFG80211_REG_DEBUG is not set
> -CONFIG_CFG80211_DEFAULT_PS=y
> -# CONFIG_WIRELESS_OLD_REGULATORY is not set
> -CONFIG_CFG80211_WEXT=y
> -CONFIG_WIRELESS_EXT_SYSFS=y
> -CONFIG_LIB80211=m
> -# CONFIG_LIB80211_DEBUG is not set
> -CONFIG_MAC80211=m
> -CONFIG_MAC80211_RC_MINSTREL=y
> -# CONFIG_MAC80211_RC_DEFAULT_PID is not set
> -CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
> -CONFIG_MAC80211_RC_DEFAULT="minstrel"
> -# CONFIG_MAC80211_MESH is not set
> -# CONFIG_MAC80211_LEDS is not set
> -# CONFIG_MAC80211_DEBUG_MENU is not set
> -# CONFIG_WIMAX is not set
> -# CONFIG_RFKILL is not set
> -# CONFIG_NET_9P is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -# CONFIG_DEVTMPFS is not set
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=y
> -CONFIG_FIRMWARE_IN_KERNEL=y
> -CONFIG_EXTRA_FIRMWARE=""
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_DEBUG_DEVRES is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -# CONFIG_CONNECTOR is not set
> -CONFIG_MTD=y
> -# CONFIG_MTD_DEBUG is not set
> -# CONFIG_MTD_TESTS is not set
> -# CONFIG_MTD_CONCAT is not set
> -CONFIG_MTD_PARTITIONS=y
> -CONFIG_MTD_REDBOOT_PARTS=y
> -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
> -# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
> -CONFIG_MTD_REDBOOT_PARTS_READONLY=y
> -# CONFIG_MTD_CMDLINE_PARTS is not set
> -# CONFIG_MTD_AFS_PARTS is not set
> -# CONFIG_MTD_AR7_PARTS is not set
> -
> -#
> -# User Modules And Translation Layers
> -#
> -CONFIG_MTD_CHAR=m
> -CONFIG_MTD_BLKDEVS=y
> -CONFIG_MTD_BLOCK=y
> -# CONFIG_FTL is not set
> -# CONFIG_NFTL is not set
> -# CONFIG_INFTL is not set
> -# CONFIG_RFD_FTL is not set
> -# CONFIG_SSFDC is not set
> -# CONFIG_MTD_OOPS is not set
> -
> -#
> -# RAM/ROM/Flash chip drivers
> -#
> -CONFIG_MTD_CFI=y
> -CONFIG_MTD_JEDECPROBE=y
> -CONFIG_MTD_GEN_PROBE=y
> -CONFIG_MTD_CFI_ADV_OPTIONS=y
> -CONFIG_MTD_CFI_NOSWAP=y
> -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
> -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
> -CONFIG_MTD_CFI_GEOMETRY=y
> -CONFIG_MTD_MAP_BANK_WIDTH_1=y
> -CONFIG_MTD_MAP_BANK_WIDTH_2=y
> -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
> -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
> -CONFIG_MTD_CFI_I1=y
> -# CONFIG_MTD_CFI_I2 is not set
> -# CONFIG_MTD_CFI_I4 is not set
> -# CONFIG_MTD_CFI_I8 is not set
> -# CONFIG_MTD_OTP is not set
> -CONFIG_MTD_CFI_INTELEXT=y
> -CONFIG_MTD_CFI_AMDSTD=y
> -# CONFIG_MTD_CFI_STAA is not set
> -CONFIG_MTD_CFI_UTIL=y
> -CONFIG_MTD_RAM=y
> -# CONFIG_MTD_ROM is not set
> -# CONFIG_MTD_ABSENT is not set
> -# CONFIG_MTD_XIP is not set
> -
> -#
> -# Mapping drivers for chip access
> -#
> -CONFIG_MTD_COMPLEX_MAPPINGS=y
> -CONFIG_MTD_PHYSMAP=y
> -# CONFIG_MTD_PHYSMAP_COMPAT is not set
> -CONFIG_MTD_PXA2XX=y
> -# CONFIG_MTD_ARM_INTEGRATOR is not set
> -# CONFIG_MTD_IMPA7 is not set
> -# CONFIG_MTD_GPIO_ADDR is not set
> -# CONFIG_MTD_PLATRAM is not set
> -
> -#
> -# Self-contained MTD device drivers
> -#
> -# CONFIG_MTD_DATAFLASH is not set
> -# CONFIG_MTD_M25P80 is not set
> -# CONFIG_MTD_SST25L is not set
> -# CONFIG_MTD_SLRAM is not set
> -# CONFIG_MTD_PHRAM is not set
> -# CONFIG_MTD_MTDRAM is not set
> -# CONFIG_MTD_BLOCK2MTD is not set
> -
> -#
> -# Disk-On-Chip Device Drivers
> -#
> -# CONFIG_MTD_DOC2000 is not set
> -# CONFIG_MTD_DOC2001 is not set
> -# CONFIG_MTD_DOC2001PLUS is not set
> -# CONFIG_MTD_NAND is not set
> -# CONFIG_MTD_ONENAND is not set
> -
> -#
> -# LPDDR flash memory drivers
> -#
> -# CONFIG_MTD_LPDDR is not set
> -
> -#
> -# UBI - Unsorted block images
> -#
> -# CONFIG_MTD_UBI is not set
> -# CONFIG_PARPORT is not set
> -# CONFIG_PNP is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -CONFIG_BLK_DEV_LOOP=m
> -# CONFIG_BLK_DEV_CRYPTOLOOP is not set
> -
> -#
> -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
> -#
> -# CONFIG_BLK_DEV_NBD is not set
> -# CONFIG_BLK_DEV_UB is not set
> -# CONFIG_BLK_DEV_RAM is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_ATA_OVER_ETH is not set
> -# CONFIG_MG_DISK is not set
> -CONFIG_MISC_DEVICES=y
> -# CONFIG_ICS932S401 is not set
> -# CONFIG_ENCLOSURE_SERVICES is not set
> -# CONFIG_ISL29003 is not set
> -# CONFIG_DS1682 is not set
> -# CONFIG_C2PORT is not set
> -
> -#
> -# EEPROM support
> -#
> -CONFIG_EEPROM_AT24=m
> -# CONFIG_EEPROM_AT25 is not set
> -# CONFIG_EEPROM_LEGACY is not set
> -# CONFIG_EEPROM_MAX6875 is not set
> -# CONFIG_EEPROM_93CX6 is not set
> -# CONFIG_IWMC3200TOP is not set
> -CONFIG_HAVE_IDE=y
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -# CONFIG_RAID_ATTRS is not set
> -CONFIG_SCSI=m
> -CONFIG_SCSI_DMA=y
> -# CONFIG_SCSI_TGT is not set
> -# CONFIG_SCSI_NETLINK is not set
> -# CONFIG_SCSI_PROC_FS is not set
> -
> -#
> -# SCSI support type (disk, tape, CD-ROM)
> -#
> -CONFIG_BLK_DEV_SD=m
> -# CONFIG_CHR_DEV_ST is not set
> -# CONFIG_CHR_DEV_OSST is not set
> -# CONFIG_BLK_DEV_SR is not set
> -# CONFIG_CHR_DEV_SG is not set
> -# CONFIG_CHR_DEV_SCH is not set
> -# CONFIG_SCSI_MULTI_LUN is not set
> -# CONFIG_SCSI_CONSTANTS is not set
> -# CONFIG_SCSI_LOGGING is not set
> -# CONFIG_SCSI_SCAN_ASYNC is not set
> -CONFIG_SCSI_WAIT_SCAN=m
> -
> -#
> -# SCSI Transports
> -#
> -# CONFIG_SCSI_SPI_ATTRS is not set
> -# CONFIG_SCSI_FC_ATTRS is not set
> -# CONFIG_SCSI_ISCSI_ATTRS is not set
> -# CONFIG_SCSI_SAS_LIBSAS is not set
> -# CONFIG_SCSI_SRP_ATTRS is not set
> -CONFIG_SCSI_LOWLEVEL=y
> -# CONFIG_ISCSI_TCP is not set
> -# CONFIG_SCSI_AHA152X is not set
> -# CONFIG_SCSI_AIC7XXX_OLD is not set
> -# CONFIG_SCSI_ADVANSYS is not set
> -# CONFIG_SCSI_IN2000 is not set
> -# CONFIG_LIBFC is not set
> -# CONFIG_LIBFCOE is not set
> -# CONFIG_SCSI_DTC3280 is not set
> -# CONFIG_SCSI_FUTURE_DOMAIN is not set
> -# CONFIG_SCSI_GENERIC_NCR5380 is not set
> -# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
> -# CONFIG_SCSI_NCR53C406A is not set
> -# CONFIG_SCSI_PAS16 is not set
> -# CONFIG_SCSI_QLOGIC_FAS is not set
> -# CONFIG_SCSI_SYM53C416 is not set
> -# CONFIG_SCSI_T128 is not set
> -# CONFIG_SCSI_DEBUG is not set
> -# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
> -# CONFIG_SCSI_DH is not set
> -# CONFIG_SCSI_OSD_INITIATOR is not set
> -CONFIG_ATA=m
> -# CONFIG_ATA_NONSTANDARD is not set
> -CONFIG_ATA_VERBOSE_ERROR=y
> -# CONFIG_SATA_PMP is not set
> -CONFIG_ATA_SFF=y
> -# CONFIG_SATA_MV is not set
> -# CONFIG_PATA_LEGACY is not set
> -CONFIG_PATA_PCMCIA=m
> -# CONFIG_PATA_QDI is not set
> -# CONFIG_PATA_WINBOND_VLB is not set
> -# CONFIG_MD is not set
> -CONFIG_NETDEVICES=y
> -# CONFIG_DUMMY is not set
> -# CONFIG_BONDING is not set
> -# CONFIG_MACVLAN is not set
> -# CONFIG_EQUALIZER is not set
> -# CONFIG_TUN is not set
> -# CONFIG_VETH is not set
> -# CONFIG_ARCNET is not set
> -# CONFIG_PHYLIB is not set
> -CONFIG_NET_ETHERNET=y
> -CONFIG_MII=y
> -# CONFIG_AX88796 is not set
> -# CONFIG_NET_VENDOR_3COM is not set
> -# CONFIG_NET_VENDOR_SMC is not set
> -# CONFIG_SMC91X is not set
> -CONFIG_DM9000=y
> -CONFIG_DM9000_DEBUGLEVEL=4
> -# CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL is not set
> -# CONFIG_ENC28J60 is not set
> -# CONFIG_ETHOC is not set
> -# CONFIG_SMC911X is not set
> -# CONFIG_SMSC911X is not set
> -# CONFIG_NET_VENDOR_RACAL is not set
> -# CONFIG_DNET is not set
> -# CONFIG_AT1700 is not set
> -# CONFIG_DEPCA is not set
> -# CONFIG_HP100 is not set
> -# CONFIG_NET_ISA is not set
> -# CONFIG_IBM_NEW_EMAC_ZMII is not set
> -# CONFIG_IBM_NEW_EMAC_RGMII is not set
> -# CONFIG_IBM_NEW_EMAC_TAH is not set
> -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
> -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
> -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
> -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
> -# CONFIG_NET_PCI is not set
> -# CONFIG_B44 is not set
> -# CONFIG_CS89x0 is not set
> -# CONFIG_KS8842 is not set
> -# CONFIG_KS8851 is not set
> -# CONFIG_KS8851_MLL is not set
> -# CONFIG_NETDEV_1000 is not set
> -# CONFIG_NETDEV_10000 is not set
> -# CONFIG_TR is not set
> -CONFIG_WLAN=y
> -# CONFIG_PCMCIA_RAYCS is not set
> -# CONFIG_LIBERTAS_THINFIRM is not set
> -# CONFIG_ATMEL is not set
> -# CONFIG_AT76C50X_USB is not set
> -# CONFIG_AIRO_CS is not set
> -# CONFIG_PCMCIA_WL3501 is not set
> -# CONFIG_USB_ZD1201 is not set
> -# CONFIG_USB_NET_RNDIS_WLAN is not set
> -# CONFIG_RTL8187 is not set
> -# CONFIG_MAC80211_HWSIM is not set
> -# CONFIG_ATH_COMMON is not set
> -# CONFIG_B43 is not set
> -# CONFIG_B43LEGACY is not set
> -# CONFIG_HOSTAP is not set
> -# CONFIG_IWM is not set
> -# CONFIG_LIBERTAS is not set
> -CONFIG_HERMES=m
> -CONFIG_HERMES_CACHE_FW_ON_INIT=y
> -CONFIG_PCMCIA_HERMES=m
> -# CONFIG_PCMCIA_SPECTRUM is not set
> -# CONFIG_P54_COMMON is not set
> -CONFIG_RT2X00=m
> -# CONFIG_RT2500USB is not set
> -CONFIG_RT73USB=m
> -# CONFIG_RT2800USB is not set
> -CONFIG_RT2X00_LIB_USB=m
> -CONFIG_RT2X00_LIB=m
> -CONFIG_RT2X00_LIB_FIRMWARE=y
> -CONFIG_RT2X00_LIB_CRYPTO=y
> -CONFIG_RT2X00_LIB_LEDS=y
> -# CONFIG_RT2X00_DEBUG is not set
> -# CONFIG_WL12XX is not set
> -# CONFIG_ZD1211RW is not set
> -
> -#
> -# Enable WiMAX (Networking options) to see the WiMAX drivers
> -#
> -
> -#
> -# USB Network Adapters
> -#
> -# CONFIG_USB_CATC is not set
> -# CONFIG_USB_KAWETH is not set
> -# CONFIG_USB_PEGASUS is not set
> -# CONFIG_USB_RTL8150 is not set
> -# CONFIG_USB_USBNET is not set
> -CONFIG_NET_PCMCIA=y
> -# CONFIG_PCMCIA_3C589 is not set
> -# CONFIG_PCMCIA_3C574 is not set
> -# CONFIG_PCMCIA_FMVJ18X is not set
> -# CONFIG_PCMCIA_PCNET is not set
> -# CONFIG_PCMCIA_NMCLAN is not set
> -# CONFIG_PCMCIA_SMC91C92 is not set
> -# CONFIG_PCMCIA_XIRC2PS is not set
> -# CONFIG_PCMCIA_AXNET is not set
> -# CONFIG_WAN is not set
> -CONFIG_PPP=m
> -# CONFIG_PPP_MULTILINK is not set
> -# CONFIG_PPP_FILTER is not set
> -CONFIG_PPP_ASYNC=m
> -# CONFIG_PPP_SYNC_TTY is not set
> -CONFIG_PPP_DEFLATE=m
> -CONFIG_PPP_BSDCOMP=m
> -# CONFIG_PPP_MPPE is not set
> -# CONFIG_PPPOE is not set
> -# CONFIG_PPPOL2TP is not set
> -# CONFIG_SLIP is not set
> -CONFIG_SLHC=m
> -# CONFIG_NETCONSOLE is not set
> -# CONFIG_NETPOLL is not set
> -# CONFIG_NET_POLL_CONTROLLER is not set
> -# CONFIG_ISDN is not set
> -# CONFIG_PHONE is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> -# CONFIG_INPUT_JOYDEV is not set
> -CONFIG_INPUT_EVDEV=m
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -# CONFIG_INPUT_KEYBOARD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -# CONFIG_TOUCHSCREEN_ADS7846 is not set
> -# CONFIG_TOUCHSCREEN_AD7877 is not set
> -# CONFIG_TOUCHSCREEN_AD7879_I2C is not set
> -# CONFIG_TOUCHSCREEN_AD7879_SPI is not set
> -# CONFIG_TOUCHSCREEN_AD7879 is not set
> -# CONFIG_TOUCHSCREEN_EETI is not set
> -CONFIG_TOUCHSCREEN_FUJITSU=m
> -# CONFIG_TOUCHSCREEN_GUNZE is not set
> -CONFIG_TOUCHSCREEN_ELO=m
> -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
> -# CONFIG_TOUCHSCREEN_MCS5000 is not set
> -CONFIG_TOUCHSCREEN_MTOUCH=m
> -CONFIG_TOUCHSCREEN_INEXIO=m
> -# CONFIG_TOUCHSCREEN_MK712 is not set
> -CONFIG_TOUCHSCREEN_HTCPEN=m
> -CONFIG_TOUCHSCREEN_PENMOUNT=m
> -CONFIG_TOUCHSCREEN_TOUCHRIGHT=m
> -CONFIG_TOUCHSCREEN_TOUCHWIN=m
> -# CONFIG_TOUCHSCREEN_WM97XX is not set
> -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
> -CONFIG_TOUCHSCREEN_TOUCHIT213=m
> -# CONFIG_TOUCHSCREEN_TSC2007 is not set
> -# CONFIG_TOUCHSCREEN_W90X900 is not set
> -CONFIG_INPUT_MISC=y
> -# CONFIG_INPUT_ATI_REMOTE is not set
> -# CONFIG_INPUT_ATI_REMOTE2 is not set
> -# CONFIG_INPUT_KEYSPAN_REMOTE is not set
> -# CONFIG_INPUT_POWERMATE is not set
> -# CONFIG_INPUT_YEALINK is not set
> -# CONFIG_INPUT_CM109 is not set
> -CONFIG_INPUT_UINPUT=m
> -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -CONFIG_SERIO=y
> -CONFIG_SERIO_SERPORT=y
> -# CONFIG_SERIO_RAW is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_CONSOLE_TRANSLATIONS=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -CONFIG_DEVKMEM=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -CONFIG_SERIAL_8250=y
> -CONFIG_SERIAL_8250_CONSOLE=y
> -# CONFIG_SERIAL_8250_CS is not set
> -CONFIG_SERIAL_8250_NR_UARTS=7
> -CONFIG_SERIAL_8250_RUNTIME_UARTS=7
> -# CONFIG_SERIAL_8250_EXTENDED is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -# CONFIG_SERIAL_MAX3100 is not set
> -# CONFIG_SERIAL_PXA is not set
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
> -# CONFIG_LEGACY_PTYS is not set
> -# CONFIG_IPMI_HANDLER is not set
> -CONFIG_HW_RANDOM=m
> -# CONFIG_HW_RANDOM_TIMERIOMEM is not set
> -# CONFIG_DTLK is not set
> -# CONFIG_R3964 is not set
> -
> -#
> -# PCMCIA character devices
> -#
> -# CONFIG_SYNCLINK_CS is not set
> -# CONFIG_CARDMAN_4000 is not set
> -# CONFIG_CARDMAN_4040 is not set
> -# CONFIG_IPWIRELESS is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -CONFIG_DEVPORT=y
> -CONFIG_I2C=y
> -CONFIG_I2C_BOARDINFO=y
> -CONFIG_I2C_COMPAT=y
> -CONFIG_I2C_CHARDEV=y
> -# CONFIG_I2C_HELPER_AUTO is not set
> -
> -#
> -# I2C Algorithms
> -#
> -CONFIG_I2C_ALGOBIT=y
> -# CONFIG_I2C_ALGOPCF is not set
> -# CONFIG_I2C_ALGOPCA is not set
> -
> -#
> -# I2C Hardware Bus support
> -#
> -
> -#
> -# I2C system bus drivers (mostly embedded / system-on-chip)
> -#
> -# CONFIG_I2C_DESIGNWARE is not set
> -CONFIG_I2C_GPIO=y
> -# CONFIG_I2C_OCORES is not set
> -CONFIG_I2C_PXA=y
> -# CONFIG_I2C_PXA_SLAVE is not set
> -# CONFIG_I2C_SIMTEC is not set
> -
> -#
> -# External I2C/SMBus adapter drivers
> -#
> -# CONFIG_I2C_PARPORT_LIGHT is not set
> -# CONFIG_I2C_TAOS_EVM is not set
> -# CONFIG_I2C_TINY_USB is not set
> -
> -#
> -# Other I2C/SMBus bus drivers
> -#
> -# CONFIG_I2C_ELEKTOR is not set
> -# CONFIG_I2C_PCA_ISA is not set
> -# CONFIG_I2C_PCA_PLATFORM is not set
> -# CONFIG_I2C_STUB is not set
> -
> -#
> -# Miscellaneous I2C Chip support
> -#
> -# CONFIG_SENSORS_TSL2550 is not set
> -# CONFIG_I2C_DEBUG_CORE is not set
> -# CONFIG_I2C_DEBUG_ALGO is not set
> -# CONFIG_I2C_DEBUG_BUS is not set
> -# CONFIG_I2C_DEBUG_CHIP is not set
> -CONFIG_SPI=y
> -# CONFIG_SPI_DEBUG is not set
> -CONFIG_SPI_MASTER=y
> -
> -#
> -# SPI Master Controller Drivers
> -#
> -# CONFIG_SPI_BITBANG is not set
> -# CONFIG_SPI_GPIO is not set
> -CONFIG_SPI_PXA2XX=y
> -
> -#
> -# SPI Protocol Masters
> -#
> -# CONFIG_SPI_SPIDEV is not set
> -# CONFIG_SPI_TLE62X0 is not set
> -
> -#
> -# PPS support
> -#
> -# CONFIG_PPS is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -# CONFIG_DEBUG_GPIO is not set
> -CONFIG_GPIO_SYSFS=y
> -
> -#
> -# Memory mapped GPIO expanders:
> -#
> -
> -#
> -# I2C GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX732X is not set
> -CONFIG_GPIO_PCA953X=y
> -# CONFIG_GPIO_PCF857X is not set
> -
> -#
> -# PCI GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -# CONFIG_GPIO_MAX7301 is not set
> -# CONFIG_GPIO_MCP23S08 is not set
> -# CONFIG_GPIO_MC33880 is not set
> -
> -#
> -# AC97 GPIO expanders:
> -#
> -# CONFIG_W1 is not set
> -# CONFIG_POWER_SUPPLY is not set
> -CONFIG_HWMON=y
> -# CONFIG_HWMON_VID is not set
> -# CONFIG_HWMON_DEBUG_CHIP is not set
> -
> -#
> -# Native drivers
> -#
> -# CONFIG_SENSORS_AD7414 is not set
> -# CONFIG_SENSORS_AD7418 is not set
> -# CONFIG_SENSORS_ADCXX is not set
> -# CONFIG_SENSORS_ADM1021 is not set
> -# CONFIG_SENSORS_ADM1025 is not set
> -# CONFIG_SENSORS_ADM1026 is not set
> -# CONFIG_SENSORS_ADM1029 is not set
> -# CONFIG_SENSORS_ADM1031 is not set
> -# CONFIG_SENSORS_ADM9240 is not set
> -# CONFIG_SENSORS_ADT7462 is not set
> -# CONFIG_SENSORS_ADT7470 is not set
> -# CONFIG_SENSORS_ADT7473 is not set
> -# CONFIG_SENSORS_ADT7475 is not set
> -# CONFIG_SENSORS_ATXP1 is not set
> -# CONFIG_SENSORS_DS1621 is not set
> -# CONFIG_SENSORS_F71805F is not set
> -# CONFIG_SENSORS_F71882FG is not set
> -# CONFIG_SENSORS_F75375S is not set
> -# CONFIG_SENSORS_G760A is not set
> -# CONFIG_SENSORS_GL518SM is not set
> -# CONFIG_SENSORS_GL520SM is not set
> -# CONFIG_SENSORS_IT87 is not set
> -# CONFIG_SENSORS_LM63 is not set
> -# CONFIG_SENSORS_LM70 is not set
> -CONFIG_SENSORS_LM75=m
> -# CONFIG_SENSORS_LM77 is not set
> -# CONFIG_SENSORS_LM78 is not set
> -# CONFIG_SENSORS_LM80 is not set
> -# CONFIG_SENSORS_LM83 is not set
> -# CONFIG_SENSORS_LM85 is not set
> -# CONFIG_SENSORS_LM87 is not set
> -# CONFIG_SENSORS_LM90 is not set
> -# CONFIG_SENSORS_LM92 is not set
> -# CONFIG_SENSORS_LM93 is not set
> -# CONFIG_SENSORS_LTC4215 is not set
> -# CONFIG_SENSORS_LTC4245 is not set
> -# CONFIG_SENSORS_LM95241 is not set
> -# CONFIG_SENSORS_MAX1111 is not set
> -# CONFIG_SENSORS_MAX1619 is not set
> -# CONFIG_SENSORS_MAX6650 is not set
> -# CONFIG_SENSORS_PC87360 is not set
> -# CONFIG_SENSORS_PC87427 is not set
> -# CONFIG_SENSORS_PCF8591 is not set
> -# CONFIG_SENSORS_SHT15 is not set
> -# CONFIG_SENSORS_DME1737 is not set
> -# CONFIG_SENSORS_SMSC47M1 is not set
> -# CONFIG_SENSORS_SMSC47M192 is not set
> -# CONFIG_SENSORS_SMSC47B397 is not set
> -# CONFIG_SENSORS_ADS7828 is not set
> -# CONFIG_SENSORS_THMC50 is not set
> -# CONFIG_SENSORS_TMP401 is not set
> -# CONFIG_SENSORS_TMP421 is not set
> -# CONFIG_SENSORS_VT1211 is not set
> -# CONFIG_SENSORS_W83781D is not set
> -# CONFIG_SENSORS_W83791D is not set
> -# CONFIG_SENSORS_W83792D is not set
> -# CONFIG_SENSORS_W83793 is not set
> -# CONFIG_SENSORS_W83L785TS is not set
> -# CONFIG_SENSORS_W83L786NG is not set
> -# CONFIG_SENSORS_W83627HF is not set
> -# CONFIG_SENSORS_W83627EHF is not set
> -# CONFIG_SENSORS_LIS3_SPI is not set
> -# CONFIG_THERMAL is not set
> -CONFIG_WATCHDOG=y
> -# CONFIG_WATCHDOG_NOWAYOUT is not set
> -
> -#
> -# Watchdog Device Drivers
> -#
> -# CONFIG_SOFT_WATCHDOG is not set
> -# CONFIG_SA1100_WATCHDOG is not set
> -
> -#
> -# ISA-based Watchdog Cards
> -#
> -# CONFIG_PCWATCHDOG is not set
> -# CONFIG_MIXCOMWD is not set
> -# CONFIG_WDT is not set
> -
> -#
> -# USB-based Watchdog Cards
> -#
> -# CONFIG_USBPCWATCHDOG is not set
> -CONFIG_SSB_POSSIBLE=y
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_CORE is not set
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_MFD_ASIC3 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -# CONFIG_UCB1400_CORE is not set
> -# CONFIG_TPS65010 is not set
> -# CONFIG_TWL4030_CORE is not set
> -# CONFIG_MFD_TMIO is not set
> -# CONFIG_MFD_T7L66XB is not set
> -# CONFIG_MFD_TC6387XB is not set
> -# CONFIG_MFD_TC6393XB is not set
> -# CONFIG_PMIC_DA903X is not set
> -# CONFIG_MFD_WM8400 is not set
> -# CONFIG_MFD_WM831X is not set
> -# CONFIG_MFD_WM8350_I2C is not set
> -# CONFIG_MFD_PCF50633 is not set
> -# CONFIG_MFD_MC13783 is not set
> -# CONFIG_AB3100_CORE is not set
> -# CONFIG_EZX_PCAP is not set
> -# CONFIG_REGULATOR is not set
> -# CONFIG_MEDIA_SUPPORT is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -CONFIG_FB=y
> -# CONFIG_FIRMWARE_EDID is not set
> -# CONFIG_FB_DDC is not set
> -# CONFIG_FB_BOOT_VESA_SUPPORT is not set
> -CONFIG_FB_CFB_FILLRECT=m
> -CONFIG_FB_CFB_COPYAREA=m
> -CONFIG_FB_CFB_IMAGEBLIT=m
> -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
> -# CONFIG_FB_SYS_FILLRECT is not set
> -# CONFIG_FB_SYS_COPYAREA is not set
> -# CONFIG_FB_SYS_IMAGEBLIT is not set
> -# CONFIG_FB_FOREIGN_ENDIAN is not set
> -# CONFIG_FB_SYS_FOPS is not set
> -# CONFIG_FB_SVGALIB is not set
> -# CONFIG_FB_MACMODES is not set
> -# CONFIG_FB_BACKLIGHT is not set
> -# CONFIG_FB_MODE_HELPERS is not set
> -# CONFIG_FB_TILEBLITTING is not set
> -
> -#
> -# Frame buffer hardware drivers
> -#
> -# CONFIG_FB_S1D13XXX is not set
> -CONFIG_FB_PXA=m
> -# CONFIG_FB_PXA_OVERLAY is not set
> -# CONFIG_FB_PXA_SMARTPANEL is not set
> -CONFIG_FB_PXA_PARAMETERS=y
> -# CONFIG_FB_MBX is not set
> -# CONFIG_FB_W100 is not set
> -# CONFIG_FB_VIRTUAL is not set
> -# CONFIG_FB_METRONOME is not set
> -# CONFIG_FB_MB862XX is not set
> -# CONFIG_FB_BROADSHEET is not set
> -CONFIG_BACKLIGHT_LCD_SUPPORT=y
> -CONFIG_LCD_CLASS_DEVICE=m
> -# CONFIG_LCD_LMS283GF05 is not set
> -# CONFIG_LCD_LTV350QV is not set
> -# CONFIG_LCD_ILI9320 is not set
> -# CONFIG_LCD_TDO24M is not set
> -# CONFIG_LCD_VGG2432A4 is not set
> -# CONFIG_LCD_PLATFORM is not set
> -CONFIG_BACKLIGHT_CLASS_DEVICE=m
> -CONFIG_BACKLIGHT_GENERIC=m
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -# CONFIG_MDA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -CONFIG_FRAMEBUFFER_CONSOLE=m
> -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
> -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
> -# CONFIG_FONTS is not set
> -CONFIG_FONT_8x8=y
> -CONFIG_FONT_8x16=y
> -CONFIG_LOGO=y
> -CONFIG_LOGO_LINUX_MONO=y
> -CONFIG_LOGO_LINUX_VGA16=y
> -CONFIG_LOGO_LINUX_CLUT224=y
> -CONFIG_SOUND=m
> -CONFIG_SOUND_OSS_CORE=y
> -CONFIG_SOUND_OSS_CORE_PRECLAIM=y
> -CONFIG_SND=m
> -CONFIG_SND_TIMER=m
> -CONFIG_SND_PCM=m
> -CONFIG_SND_JACK=y
> -# CONFIG_SND_SEQUENCER is not set
> -CONFIG_SND_OSSEMUL=y
> -CONFIG_SND_MIXER_OSS=m
> -CONFIG_SND_PCM_OSS=m
> -CONFIG_SND_PCM_OSS_PLUGINS=y
> -# CONFIG_SND_DYNAMIC_MINORS is not set
> -# CONFIG_SND_SUPPORT_OLD_API is not set
> -CONFIG_SND_VERBOSE_PROCFS=y
> -# CONFIG_SND_VERBOSE_PRINTK is not set
> -# CONFIG_SND_DEBUG is not set
> -CONFIG_SND_VMASTER=y
> -# CONFIG_SND_RAWMIDI_SEQ is not set
> -# CONFIG_SND_OPL3_LIB_SEQ is not set
> -# CONFIG_SND_OPL4_LIB_SEQ is not set
> -# CONFIG_SND_SBAWE_SEQ is not set
> -# CONFIG_SND_EMU10K1_SEQ is not set
> -CONFIG_SND_AC97_CODEC=m
> -CONFIG_SND_DRIVERS=y
> -# CONFIG_SND_DUMMY is not set
> -# CONFIG_SND_MTPAV is not set
> -# CONFIG_SND_SERIAL_U16550 is not set
> -# CONFIG_SND_MPU401 is not set
> -# CONFIG_SND_AC97_POWER_SAVE is not set
> -CONFIG_SND_ARM=y
> -CONFIG_SND_PXA2XX_PCM=m
> -CONFIG_SND_PXA2XX_LIB=m
> -CONFIG_SND_PXA2XX_LIB_AC97=y
> -CONFIG_SND_PXA2XX_AC97=m
> -# CONFIG_SND_SPI is not set
> -CONFIG_SND_USB=y
> -# CONFIG_SND_USB_AUDIO is not set
> -# CONFIG_SND_USB_CAIAQ is not set
> -# CONFIG_SND_PCMCIA is not set
> -CONFIG_SND_SOC=m
> -CONFIG_SND_PXA2XX_SOC=m
> -CONFIG_SND_SOC_I2C_AND_SPI=m
> -# CONFIG_SND_SOC_ALL_CODECS is not set
> -# CONFIG_SOUND_PRIME is not set
> -CONFIG_AC97_BUS=m
> -# CONFIG_HID_SUPPORT is not set
> -CONFIG_USB_SUPPORT=y
> -CONFIG_USB_ARCH_HAS_HCD=y
> -CONFIG_USB_ARCH_HAS_OHCI=y
> -# CONFIG_USB_ARCH_HAS_EHCI is not set
> -CONFIG_USB=m
> -# CONFIG_USB_DEBUG is not set
> -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
> -
> -#
> -# Miscellaneous USB options
> -#
> -CONFIG_USB_DEVICEFS=y
> -CONFIG_USB_DEVICE_CLASS=y
> -# CONFIG_USB_DYNAMIC_MINORS is not set
> -CONFIG_USB_SUSPEND=y
> -# CONFIG_USB_OTG is not set
> -# CONFIG_USB_MON is not set
> -# CONFIG_USB_WUSB is not set
> -# CONFIG_USB_WUSB_CBAF is not set
> -
> -#
> -# USB Host Controller Drivers
> -#
> -# CONFIG_USB_C67X00_HCD is not set
> -# CONFIG_USB_OXU210HP_HCD is not set
> -# CONFIG_USB_ISP116X_HCD is not set
> -# CONFIG_USB_ISP1760_HCD is not set
> -# CONFIG_USB_ISP1362_HCD is not set
> -CONFIG_USB_OHCI_HCD=m
> -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
> -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
> -CONFIG_USB_OHCI_LITTLE_ENDIAN=y
> -# CONFIG_USB_SL811_HCD is not set
> -# CONFIG_USB_R8A66597_HCD is not set
> -# CONFIG_USB_HWA_HCD is not set
> -# CONFIG_USB_MUSB_HDRC is not set
> -# CONFIG_USB_GADGET_MUSB_HDRC is not set
> -
> -#
> -# USB Device Class drivers
> -#
> -CONFIG_USB_ACM=m
> -# CONFIG_USB_PRINTER is not set
> -# CONFIG_USB_WDM is not set
> -# CONFIG_USB_TMC is not set
> -
> -#
> -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
> -#
> -
> -#
> -# also be needed; see USB_STORAGE Help for more info
> -#
> -CONFIG_USB_STORAGE=m
> -# CONFIG_USB_STORAGE_DEBUG is not set
> -# CONFIG_USB_STORAGE_DATAFAB is not set
> -# CONFIG_USB_STORAGE_FREECOM is not set
> -# CONFIG_USB_STORAGE_ISD200 is not set
> -# CONFIG_USB_STORAGE_USBAT is not set
> -# CONFIG_USB_STORAGE_SDDR09 is not set
> -# CONFIG_USB_STORAGE_SDDR55 is not set
> -# CONFIG_USB_STORAGE_JUMPSHOT is not set
> -# CONFIG_USB_STORAGE_ALAUDA is not set
> -# CONFIG_USB_STORAGE_ONETOUCH is not set
> -# CONFIG_USB_STORAGE_KARMA is not set
> -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
> -# CONFIG_USB_LIBUSUAL is not set
> -
> -#
> -# USB Imaging devices
> -#
> -# CONFIG_USB_MDC800 is not set
> -# CONFIG_USB_MICROTEK is not set
> -
> -#
> -# USB port drivers
> -#
> -CONFIG_USB_SERIAL=m
> -# CONFIG_USB_EZUSB is not set
> -CONFIG_USB_SERIAL_GENERIC=y
> -# CONFIG_USB_SERIAL_AIRCABLE is not set
> -# CONFIG_USB_SERIAL_ARK3116 is not set
> -# CONFIG_USB_SERIAL_BELKIN is not set
> -# CONFIG_USB_SERIAL_CH341 is not set
> -# CONFIG_USB_SERIAL_WHITEHEAT is not set
> -# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
> -# CONFIG_USB_SERIAL_CP210X is not set
> -# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
> -# CONFIG_USB_SERIAL_EMPEG is not set
> -# CONFIG_USB_SERIAL_FTDI_SIO is not set
> -# CONFIG_USB_SERIAL_FUNSOFT is not set
> -# CONFIG_USB_SERIAL_VISOR is not set
> -# CONFIG_USB_SERIAL_IPAQ is not set
> -# CONFIG_USB_SERIAL_IR is not set
> -# CONFIG_USB_SERIAL_EDGEPORT is not set
> -# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
> -# CONFIG_USB_SERIAL_GARMIN is not set
> -# CONFIG_USB_SERIAL_IPW is not set
> -# CONFIG_USB_SERIAL_IUU is not set
> -# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
> -# CONFIG_USB_SERIAL_KEYSPAN is not set
> -# CONFIG_USB_SERIAL_KLSI is not set
> -# CONFIG_USB_SERIAL_KOBIL_SCT is not set
> -CONFIG_USB_SERIAL_MCT_U232=m
> -# CONFIG_USB_SERIAL_MOS7720 is not set
> -# CONFIG_USB_SERIAL_MOS7840 is not set
> -# CONFIG_USB_SERIAL_MOTOROLA is not set
> -# CONFIG_USB_SERIAL_NAVMAN is not set
> -# CONFIG_USB_SERIAL_PL2303 is not set
> -# CONFIG_USB_SERIAL_OTI6858 is not set
> -# CONFIG_USB_SERIAL_QUALCOMM is not set
> -# CONFIG_USB_SERIAL_SPCP8X5 is not set
> -# CONFIG_USB_SERIAL_HP4X is not set
> -# CONFIG_USB_SERIAL_SAFE is not set
> -# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
> -# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
> -# CONFIG_USB_SERIAL_SYMBOL is not set
> -# CONFIG_USB_SERIAL_TI is not set
> -# CONFIG_USB_SERIAL_CYBERJACK is not set
> -# CONFIG_USB_SERIAL_XIRCOM is not set
> -# CONFIG_USB_SERIAL_OPTION is not set
> -# CONFIG_USB_SERIAL_OMNINET is not set
> -# CONFIG_USB_SERIAL_OPTICON is not set
> -# CONFIG_USB_SERIAL_DEBUG is not set
> -
> -#
> -# USB Miscellaneous drivers
> -#
> -# CONFIG_USB_EMI62 is not set
> -# CONFIG_USB_EMI26 is not set
> -# CONFIG_USB_ADUTUX is not set
> -# CONFIG_USB_SEVSEG is not set
> -# CONFIG_USB_RIO500 is not set
> -# CONFIG_USB_LEGOTOWER is not set
> -# CONFIG_USB_LCD is not set
> -# CONFIG_USB_BERRY_CHARGE is not set
> -# CONFIG_USB_LED is not set
> -# CONFIG_USB_CYPRESS_CY7C63 is not set
> -# CONFIG_USB_CYTHERM is not set
> -# CONFIG_USB_IDMOUSE is not set
> -# CONFIG_USB_FTDI_ELAN is not set
> -# CONFIG_USB_APPLEDISPLAY is not set
> -# CONFIG_USB_LD is not set
> -# CONFIG_USB_TRANCEVIBRATOR is not set
> -# CONFIG_USB_IOWARRIOR is not set
> -# CONFIG_USB_TEST is not set
> -# CONFIG_USB_ISIGHTFW is not set
> -# CONFIG_USB_VST is not set
> -CONFIG_USB_GADGET=m
> -# CONFIG_USB_GADGET_DEBUG is not set
> -# CONFIG_USB_GADGET_DEBUG_FILES is not set
> -CONFIG_USB_GADGET_VBUS_DRAW=2
> -CONFIG_USB_GADGET_SELECTED=y
> -# CONFIG_USB_GADGET_AT91 is not set
> -# CONFIG_USB_GADGET_ATMEL_USBA is not set
> -# CONFIG_USB_GADGET_FSL_USB2 is not set
> -# CONFIG_USB_GADGET_LH7A40X is not set
> -# CONFIG_USB_GADGET_OMAP is not set
> -# CONFIG_USB_GADGET_PXA25X is not set
> -# CONFIG_USB_GADGET_R8A66597 is not set
> -CONFIG_USB_GADGET_PXA27X=y
> -CONFIG_USB_PXA27X=m
> -# CONFIG_USB_GADGET_S3C_HSOTG is not set
> -# CONFIG_USB_GADGET_IMX is not set
> -# CONFIG_USB_GADGET_S3C2410 is not set
> -# CONFIG_USB_GADGET_M66592 is not set
> -# CONFIG_USB_GADGET_AMD5536UDC is not set
> -# CONFIG_USB_GADGET_FSL_QE is not set
> -# CONFIG_USB_GADGET_CI13XXX is not set
> -# CONFIG_USB_GADGET_NET2280 is not set
> -# CONFIG_USB_GADGET_GOKU is not set
> -# CONFIG_USB_GADGET_LANGWELL is not set
> -# CONFIG_USB_GADGET_DUMMY_HCD is not set
> -# CONFIG_USB_GADGET_DUALSPEED is not set
> -# CONFIG_USB_ZERO is not set
> -# CONFIG_USB_AUDIO is not set
> -CONFIG_USB_ETH=m
> -CONFIG_USB_ETH_RNDIS=y
> -# CONFIG_USB_ETH_EEM is not set
> -CONFIG_USB_GADGETFS=m
> -CONFIG_USB_FILE_STORAGE=m
> -# CONFIG_USB_FILE_STORAGE_TEST is not set
> -CONFIG_USB_G_SERIAL=m
> -# CONFIG_USB_MIDI_GADGET is not set
> -CONFIG_USB_G_PRINTER=m
> -# CONFIG_USB_CDC_COMPOSITE is not set
> -
> -#
> -# OTG and related infrastructure
> -#
> -CONFIG_USB_OTG_UTILS=y
> -# CONFIG_USB_GPIO_VBUS is not set
> -# CONFIG_NOP_USB_XCEIV is not set
> -CONFIG_MMC=y
> -# CONFIG_MMC_DEBUG is not set
> -# CONFIG_MMC_UNSAFE_RESUME is not set
> -
> -#
> -# MMC/SD/SDIO Card Drivers
> -#
> -CONFIG_MMC_BLOCK=y
> -# CONFIG_MMC_BLOCK_BOUNCE is not set
> -# CONFIG_SDIO_UART is not set
> -# CONFIG_MMC_TEST is not set
> -
> -#
> -# MMC/SD/SDIO Host Controller Drivers
> -#
> -CONFIG_MMC_PXA=y
> -# CONFIG_MMC_SDHCI is not set
> -# CONFIG_MMC_AT91 is not set
> -# CONFIG_MMC_ATMELMCI is not set
> -# CONFIG_MMC_SPI is not set
> -# CONFIG_MEMSTICK is not set
> -CONFIG_NEW_LEDS=y
> -CONFIG_LEDS_CLASS=m
> -
> -#
> -# LED drivers
> -#
> -# CONFIG_LEDS_PCA9532 is not set
> -CONFIG_LEDS_GPIO=m
> -CONFIG_LEDS_GPIO_PLATFORM=y
> -# CONFIG_LEDS_LP3944 is not set
> -# CONFIG_LEDS_PCA955X is not set
> -# CONFIG_LEDS_DAC124S085 is not set
> -# CONFIG_LEDS_BD2802 is not set
> -
> -#
> -# LED Triggers
> -#
> -CONFIG_LEDS_TRIGGERS=y
> -CONFIG_LEDS_TRIGGER_TIMER=m
> -CONFIG_LEDS_TRIGGER_HEARTBEAT=m
> -CONFIG_LEDS_TRIGGER_BACKLIGHT=m
> -CONFIG_LEDS_TRIGGER_GPIO=m
> -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
> -
> -#
> -# iptables trigger is under Netfilter config (LED target)
> -#
> -# CONFIG_ACCESSIBILITY is not set
> -CONFIG_RTC_LIB=y
> -CONFIG_RTC_CLASS=m
> -
> -#
> -# RTC interfaces
> -#
> -CONFIG_RTC_INTF_SYSFS=y
> -CONFIG_RTC_INTF_PROC=y
> -CONFIG_RTC_INTF_DEV=y
> -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
> -# CONFIG_RTC_DRV_TEST is not set
> -
> -#
> -# I2C RTC drivers
> -#
> -# CONFIG_RTC_DRV_DS1307 is not set
> -# CONFIG_RTC_DRV_DS1374 is not set
> -# CONFIG_RTC_DRV_DS1672 is not set
> -# CONFIG_RTC_DRV_MAX6900 is not set
> -# CONFIG_RTC_DRV_RS5C372 is not set
> -CONFIG_RTC_DRV_ISL1208=m
> -# CONFIG_RTC_DRV_X1205 is not set
> -# CONFIG_RTC_DRV_PCF8563 is not set
> -# CONFIG_RTC_DRV_PCF8583 is not set
> -# CONFIG_RTC_DRV_M41T80 is not set
> -# CONFIG_RTC_DRV_S35390A is not set
> -# CONFIG_RTC_DRV_FM3130 is not set
> -# CONFIG_RTC_DRV_RX8581 is not set
> -# CONFIG_RTC_DRV_RX8025 is not set
> -
> -#
> -# SPI RTC drivers
> -#
> -# CONFIG_RTC_DRV_M41T94 is not set
> -# CONFIG_RTC_DRV_DS1305 is not set
> -# CONFIG_RTC_DRV_DS1390 is not set
> -# CONFIG_RTC_DRV_MAX6902 is not set
> -# CONFIG_RTC_DRV_R9701 is not set
> -# CONFIG_RTC_DRV_RS5C348 is not set
> -# CONFIG_RTC_DRV_DS3234 is not set
> -# CONFIG_RTC_DRV_PCF2123 is not set
> -
> -#
> -# Platform RTC drivers
> -#
> -# CONFIG_RTC_DRV_CMOS is not set
> -# CONFIG_RTC_DRV_DS1286 is not set
> -# CONFIG_RTC_DRV_DS1511 is not set
> -# CONFIG_RTC_DRV_DS1553 is not set
> -# CONFIG_RTC_DRV_DS1742 is not set
> -# CONFIG_RTC_DRV_STK17TA8 is not set
> -# CONFIG_RTC_DRV_M48T86 is not set
> -# CONFIG_RTC_DRV_M48T35 is not set
> -# CONFIG_RTC_DRV_M48T59 is not set
> -# CONFIG_RTC_DRV_MSM6242 is not set
> -# CONFIG_RTC_DRV_BQ4802 is not set
> -# CONFIG_RTC_DRV_RP5C01 is not set
> -# CONFIG_RTC_DRV_V3020 is not set
> -
> -#
> -# on-CPU RTC drivers
> -#
> -# CONFIG_RTC_DRV_SA1100 is not set
> -CONFIG_RTC_DRV_PXA=m
> -# CONFIG_DMADEVICES is not set
> -# CONFIG_AUXDISPLAY is not set
> -# CONFIG_UIO is not set
> -
> -#
> -# TI VLYNQ
> -#
> -# CONFIG_STAGING is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -CONFIG_EXT3_FS=y
> -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
> -# CONFIG_EXT3_FS_XATTR is not set
> -# CONFIG_EXT4_FS is not set
> -CONFIG_JBD=y
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -# CONFIG_FS_POSIX_ACL is not set
> -# CONFIG_XFS_FS is not set
> -# CONFIG_GFS2_FS is not set
> -# CONFIG_OCFS2_FS is not set
> -# CONFIG_BTRFS_FS is not set
> -# CONFIG_NILFS2_FS is not set
> -CONFIG_FILE_LOCKING=y
> -CONFIG_FSNOTIFY=y
> -# CONFIG_DNOTIFY is not set
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -
> -#
> -# Caches
> -#
> -# CONFIG_FSCACHE is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=m
> -# CONFIG_MSDOS_FS is not set
> -CONFIG_VFAT_FS=m
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_PROC_PAGE_MONITOR=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -# CONFIG_TMPFS_POSIX_ACL is not set
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -CONFIG_MISC_FILESYSTEMS=y
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -CONFIG_JFFS2_FS=y
> -CONFIG_JFFS2_FS_DEBUG=0
> -CONFIG_JFFS2_FS_WRITEBUFFER=y
> -# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
> -# CONFIG_JFFS2_SUMMARY is not set
> -# CONFIG_JFFS2_FS_XATTR is not set
> -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
> -CONFIG_JFFS2_ZLIB=y
> -# CONFIG_JFFS2_LZO is not set
> -CONFIG_JFFS2_RTIME=y
> -# CONFIG_JFFS2_RUBIN is not set
> -# CONFIG_CRAMFS is not set
> -# CONFIG_SQUASHFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_OMFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -# CONFIG_ROMFS_FS is not set
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -CONFIG_NETWORK_FILESYSTEMS=y
> -CONFIG_NFS_FS=y
> -CONFIG_NFS_V3=y
> -# CONFIG_NFS_V3_ACL is not set
> -# CONFIG_NFS_V4 is not set
> -CONFIG_ROOT_NFS=y
> -CONFIG_NFSD=m
> -CONFIG_NFSD_V3=y
> -# CONFIG_NFSD_V3_ACL is not set
> -# CONFIG_NFSD_V4 is not set
> -CONFIG_LOCKD=y
> -CONFIG_LOCKD_V4=y
> -CONFIG_EXPORTFS=m
> -CONFIG_NFS_COMMON=y
> -CONFIG_SUNRPC=y
> -# CONFIG_RPCSEC_GSS_KRB5 is not set
> -# CONFIG_RPCSEC_GSS_SPKM3 is not set
> -# CONFIG_SMB_FS is not set
> -# CONFIG_CIFS is not set
> -# CONFIG_NCP_FS is not set
> -# CONFIG_CODA_FS is not set
> -# CONFIG_AFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -CONFIG_PARTITION_ADVANCED=y
> -# CONFIG_ACORN_PARTITION is not set
> -# CONFIG_OSF_PARTITION is not set
> -# CONFIG_AMIGA_PARTITION is not set
> -# CONFIG_ATARI_PARTITION is not set
> -# CONFIG_MAC_PARTITION is not set
> -CONFIG_MSDOS_PARTITION=y
> -# CONFIG_BSD_DISKLABEL is not set
> -# CONFIG_MINIX_SUBPARTITION is not set
> -# CONFIG_SOLARIS_X86_PARTITION is not set
> -# CONFIG_UNIXWARE_DISKLABEL is not set
> -# CONFIG_LDM_PARTITION is not set
> -# CONFIG_SGI_PARTITION is not set
> -# CONFIG_ULTRIX_PARTITION is not set
> -# CONFIG_SUN_PARTITION is not set
> -# CONFIG_KARMA_PARTITION is not set
> -# CONFIG_EFI_PARTITION is not set
> -# CONFIG_SYSV68_PARTITION is not set
> -CONFIG_NLS=m
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -CONFIG_NLS_CODEPAGE_437=m
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -CONFIG_NLS_CODEPAGE_850=m
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -# CONFIG_NLS_ASCII is not set
> -CONFIG_NLS_ISO8859_1=m
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -CONFIG_NLS_ISO8859_15=m
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -CONFIG_NLS_UTF8=m
> -# CONFIG_DLM is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_FRAME_WARN=1024
> -CONFIG_MAGIC_SYSRQ=y
> -# CONFIG_STRIP_ASM_SYMS is not set
> -# CONFIG_UNUSED_SYMBOLS is not set
> -# CONFIG_DEBUG_FS is not set
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DEBUG_SHIRQ is not set
> -CONFIG_DETECT_SOFTLOCKUP=y
> -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
> -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
> -CONFIG_DETECT_HUNG_TASK=y
> -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
> -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
> -CONFIG_SCHED_DEBUG=y
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_TIMER_STATS is not set
> -# CONFIG_DEBUG_OBJECTS is not set
> -# CONFIG_SLUB_DEBUG_ON is not set
> -# CONFIG_SLUB_STATS is not set
> -# CONFIG_DEBUG_KMEMLEAK is not set
> -# CONFIG_DEBUG_RT_MUTEXES is not set
> -# CONFIG_RT_MUTEX_TESTER is not set
> -# CONFIG_DEBUG_SPINLOCK is not set
> -CONFIG_DEBUG_MUTEXES=y
> -# CONFIG_DEBUG_LOCK_ALLOC is not set
> -# CONFIG_PROVE_LOCKING is not set
> -# CONFIG_LOCK_STAT is not set
> -# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -CONFIG_DEBUG_BUGVERBOSE=y
> -# CONFIG_DEBUG_INFO is not set
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_WRITECOUNT is not set
> -CONFIG_DEBUG_MEMORY_INIT=y
> -# CONFIG_DEBUG_LIST is not set
> -# CONFIG_DEBUG_SG is not set
> -# CONFIG_DEBUG_NOTIFIERS is not set
> -# CONFIG_DEBUG_CREDENTIALS is not set
> -# CONFIG_BOOT_PRINTK_DELAY is not set
> -# CONFIG_RCU_TORTURE_TEST is not set
> -# CONFIG_BACKTRACE_SELF_TEST is not set
> -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
> -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
> -# CONFIG_FAULT_INJECTION is not set
> -# CONFIG_LATENCYTOP is not set
> -CONFIG_SYSCTL_SYSCALL_CHECK=y
> -# CONFIG_PAGE_POISONING is not set
> -CONFIG_HAVE_FUNCTION_TRACER=y
> -CONFIG_TRACING_SUPPORT=y
> -CONFIG_FTRACE=y
> -# CONFIG_FUNCTION_TRACER is not set
> -# CONFIG_IRQSOFF_TRACER is not set
> -# CONFIG_SCHED_TRACER is not set
> -# CONFIG_ENABLE_DEFAULT_TRACERS is not set
> -# CONFIG_BOOT_TRACER is not set
> -CONFIG_BRANCH_PROFILE_NONE=y
> -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
> -# CONFIG_PROFILE_ALL_BRANCHES is not set
> -# CONFIG_STACK_TRACER is not set
> -# CONFIG_KMEMTRACE is not set
> -# CONFIG_WORKQUEUE_TRACER is not set
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -# CONFIG_KGDB is not set
> -CONFIG_ARM_UNWIND=y
> -# CONFIG_DEBUG_USER is not set
> -CONFIG_DEBUG_ERRORS=y
> -# CONFIG_DEBUG_STACK_USAGE is not set
> -# CONFIG_DEBUG_LL is not set
> -# CONFIG_OC_ETM is not set
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITYFS is not set
> -# CONFIG_DEFAULT_SECURITY_SELINUX is not set
> -# CONFIG_DEFAULT_SECURITY_SMACK is not set
> -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
> -CONFIG_DEFAULT_SECURITY_DAC=y
> -CONFIG_DEFAULT_SECURITY=""
> -CONFIG_CRYPTO=y
> -
> -#
> -# Crypto core or helper
> -#
> -CONFIG_CRYPTO_ALGAPI=m
> -CONFIG_CRYPTO_ALGAPI2=m
> -CONFIG_CRYPTO_AEAD2=m
> -CONFIG_CRYPTO_BLKCIPHER=m
> -CONFIG_CRYPTO_BLKCIPHER2=m
> -CONFIG_CRYPTO_HASH=m
> -CONFIG_CRYPTO_HASH2=m
> -CONFIG_CRYPTO_RNG2=m
> -CONFIG_CRYPTO_PCOMP=m
> -CONFIG_CRYPTO_MANAGER=m
> -CONFIG_CRYPTO_MANAGER2=m
> -# CONFIG_CRYPTO_GF128MUL is not set
> -# CONFIG_CRYPTO_NULL is not set
> -CONFIG_CRYPTO_WORKQUEUE=m
> -# CONFIG_CRYPTO_CRYPTD is not set
> -# CONFIG_CRYPTO_AUTHENC is not set
> -# CONFIG_CRYPTO_TEST is not set
> -
> -#
> -# Authenticated Encryption with Associated Data
> -#
> -# CONFIG_CRYPTO_CCM is not set
> -# CONFIG_CRYPTO_GCM is not set
> -# CONFIG_CRYPTO_SEQIV is not set
> -
> -#
> -# Block modes
> -#
> -# CONFIG_CRYPTO_CBC is not set
> -# CONFIG_CRYPTO_CTR is not set
> -# CONFIG_CRYPTO_CTS is not set
> -CONFIG_CRYPTO_ECB=m
> -# CONFIG_CRYPTO_LRW is not set
> -# CONFIG_CRYPTO_PCBC is not set
> -# CONFIG_CRYPTO_XTS is not set
> -
> -#
> -# Hash modes
> -#
> -# CONFIG_CRYPTO_HMAC is not set
> -# CONFIG_CRYPTO_XCBC is not set
> -# CONFIG_CRYPTO_VMAC is not set
> -
> -#
> -# Digest
> -#
> -# CONFIG_CRYPTO_CRC32C is not set
> -# CONFIG_CRYPTO_GHASH is not set
> -# CONFIG_CRYPTO_MD4 is not set
> -# CONFIG_CRYPTO_MD5 is not set
> -CONFIG_CRYPTO_MICHAEL_MIC=m
> -# CONFIG_CRYPTO_RMD128 is not set
> -# CONFIG_CRYPTO_RMD160 is not set
> -# CONFIG_CRYPTO_RMD256 is not set
> -# CONFIG_CRYPTO_RMD320 is not set
> -# CONFIG_CRYPTO_SHA1 is not set
> -# CONFIG_CRYPTO_SHA256 is not set
> -# CONFIG_CRYPTO_SHA512 is not set
> -# CONFIG_CRYPTO_TGR192 is not set
> -# CONFIG_CRYPTO_WP512 is not set
> -
> -#
> -# Ciphers
> -#
> -CONFIG_CRYPTO_AES=m
> -# CONFIG_CRYPTO_ANUBIS is not set
> -CONFIG_CRYPTO_ARC4=m
> -# CONFIG_CRYPTO_BLOWFISH is not set
> -# CONFIG_CRYPTO_CAMELLIA is not set
> -# CONFIG_CRYPTO_CAST5 is not set
> -# CONFIG_CRYPTO_CAST6 is not set
> -# CONFIG_CRYPTO_DES is not set
> -# CONFIG_CRYPTO_FCRYPT is not set
> -# CONFIG_CRYPTO_KHAZAD is not set
> -# CONFIG_CRYPTO_SALSA20 is not set
> -# CONFIG_CRYPTO_SEED is not set
> -# CONFIG_CRYPTO_SERPENT is not set
> -# CONFIG_CRYPTO_TEA is not set
> -# CONFIG_CRYPTO_TWOFISH is not set
> -
> -#
> -# Compression
> -#
> -# CONFIG_CRYPTO_DEFLATE is not set
> -# CONFIG_CRYPTO_ZLIB is not set
> -# CONFIG_CRYPTO_LZO is not set
> -
> -#
> -# Random Number Generation
> -#
> -# CONFIG_CRYPTO_ANSI_CPRNG is not set
> -CONFIG_CRYPTO_HW=y
> -# CONFIG_BINARY_PRINTF is not set
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -CONFIG_GENERIC_FIND_LAST_BIT=y
> -CONFIG_CRC_CCITT=m
> -CONFIG_CRC16=m
> -CONFIG_CRC_T10DIF=m
> -CONFIG_CRC_ITU_T=m
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_ZLIB_DEFLATE=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_IOPORT=y
> -CONFIG_HAS_DMA=y
> -CONFIG_NLATTR=y
> --
> 1.7.0.4
>
>
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From eric.y.miao at gmail.com  Sat Jun  5 04:04:25 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 5 Jun 2010 16:04:25 +0800
Subject: [PATCH 3/4] [ARM] pxa: merge all pxa3xx board configs into 
	pxa3xx_defconfig
In-Reply-To: <1275724538-5075-4-git-send-email-eric.y.miao@gmail.com>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com> 
	<1275724538-5075-4-git-send-email-eric.y.miao@gmail.com>
Message-ID: <AANLkTinO49Mpt2wEft08xJnrAULQcuR1GvLw90Q9ggZ6@mail.gmail.com>

Patch as in attachment.
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From mcuos.com at gmail.com  Sat Jun  5 05:07:06 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Sat, 05 Jun 2010 17:07:06 +0800
Subject: [PATCHv2 1/3] MTD/pxa: use __devinit for pxa2xx_flash_probe
Message-ID: <4C0A13BA.6050700@gmail.com>

This patch is to use the '__devinit' for pxa2xx_flash_probe.

Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
Acked-by: Eric Miao <eric.y.miao at gmail.com>

---
 drivers/mtd/maps/pxa2xx-flash.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
index dd90880..d8ae634 100644
--- a/drivers/mtd/maps/pxa2xx-flash.c
+++ b/drivers/mtd/maps/pxa2xx-flash.c
@@ -51,7 +51,7 @@ struct pxa2xx_flash_info {
 static const char *probes[] = { "RedBoot", "cmdlinepart", NULL };


-static int __init pxa2xx_flash_probe(struct platform_device *pdev)
+static int __devinit pxa2xx_flash_probe(struct platform_device *pdev)
 {
 	struct flash_platform_data *flash = pdev->dev.platform_data;
 	struct pxa2xx_flash_info *info;
-- 
1.6.3.3


From mcuos.com at gmail.com  Sat Jun  5 05:10:03 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Sat, 05 Jun 2010 17:10:03 +0800
Subject: [PATCHv2 2/3] MTD/pxa: use resource_size(res) for pxa2xx-flash
Message-ID: <4C0A146B.1060306@gmail.com>

The size calculation is end - start + 1. But,sometimes, the '1' can
be forgotten carelessly, witch will have potential risk, so use resource_size
should be good habit.

Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
Acked-by: Eric Miao <eric.y.miao at gmail.com>

---
 drivers/mtd/maps/pxa2xx-flash.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
index d8ae634..b5bb1a4 100644
--- a/drivers/mtd/maps/pxa2xx-flash.c
+++ b/drivers/mtd/maps/pxa2xx-flash.c
@@ -70,7 +70,7 @@ static int __devinit pxa2xx_flash_probe(struct platform_device *pdev)
 	info->map.name = (char *) flash->name;
 	info->map.bankwidth = flash->width;
 	info->map.phys = res->start;
-	info->map.size = res->end - res->start + 1;
+	info->map.size = resource_size(res);
 	info->parts = flash->parts;
 	info->nr_parts = flash->nr_parts;

-- 
1.6.3.3


From mcuos.com at gmail.com  Sat Jun  5 05:14:36 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Sat, 05 Jun 2010 17:14:36 +0800
Subject: [PATCHv2 3/3] MTD/pxa: patch for error return value method of
	pxa2xx-flash
Message-ID: <4C0A157C.1050909@gmail.com>

This patch is to re-implement the 'pxa2xx-flash.c' error return value method
of probe() and remove() function,the old return way can arouse the 'info' memory
leak risk.

This patch has been reviewed by Eric, according to his advice, I modify some wrong
issues of previous patch and resend to maillist.

Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>

---
 drivers/mtd/maps/pxa2xx-flash.c |   15 ++++++++++-----
 1 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/maps/pxa2xx-flash.c b/drivers/mtd/maps/pxa2xx-flash.c
index b5bb1a4..e789358 100644
--- a/drivers/mtd/maps/pxa2xx-flash.c
+++ b/drivers/mtd/maps/pxa2xx-flash.c
@@ -78,7 +78,8 @@ static int __devinit pxa2xx_flash_probe(struct platform_device *pdev)
 	if (!info->map.virt) {
 		printk(KERN_WARNING "Failed to ioremap %s\n",
 		       info->map.name);
-		return -ENOMEM;
+		ret = -ENOMEM;
+		goto fail1;
 	}
 	info->map.cached =
 		ioremap_cached(info->map.phys, info->map.size);
@@ -97,10 +98,8 @@ static int __devinit pxa2xx_flash_probe(struct platform_device *pdev)
 	info->mtd = do_map_probe(flash->map_name, &info->map);

 	if (!info->mtd) {
-		iounmap((void *)info->map.virt);
-		if (info->map.cached)
-			iounmap(info->map.cached);
-		return -EIO;
+		ret = -EIO;
+		goto fail2;
 	}
 	info->mtd->owner = THIS_MODULE;

@@ -124,6 +123,12 @@ static int __devinit pxa2xx_flash_probe(struct platform_device *pdev)

 	platform_set_drvdata(pdev, info);
 	return 0;
+
+fail2:	iounmap(info->map.virt);
+	if (info->map.cached)
+		iounmap(info->map.cached);
+fail1:	kfree(info);
+	return ret;
 }

 static int __devexit pxa2xx_flash_remove(struct platform_device *dev)
-- 
1.6.3.3


From maramaopercheseimorto at gmail.com  Sat Jun  5 05:22:02 2010
From: maramaopercheseimorto at gmail.com (Alberto Panizzo)
Date: Sat, 05 Jun 2010 11:22:02 +0200
Subject: [PATCH 2/2] backlight: Fix blanking for L4F00242T03 LCD
In-Reply-To: <201006050325.47060.marek.vasut@gmail.com>
References: <1275630748-10722-1-git-send-email-marek.vasut@gmail.com>
	<1275630748-10722-2-git-send-email-marek.vasut@gmail.com>
	<1275636583.3210.37.camel@realization>
	<201006050325.47060.marek.vasut@gmail.com>
Message-ID: <1275729722.3446.10.camel@realization>

On sab, 2010-06-05 at 03:25 +0200, Marek Vasut wrote:
> Dne P? 4. ?ervna 2010 09:29:43 Alberto Panizzo napsal(a):
> > On ven, 2010-06-04 at 07:52 +0200, Marek Vasut wrote:
> > > The LCD was turned on if the variable power was > 0, but that was
> > > incorrect. The LCD has to be turned on in every case but POWERDOWN.
> > > 
> > > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> > 
> > Ack
> > 
> > > ---
> > > 
> > >  drivers/video/backlight/l4f00242t03.c |    2 +-
> > >  1 files changed, 1 insertions(+), 1 deletions(-)
> > > 
> > > diff --git a/drivers/video/backlight/l4f00242t03.c
> > > b/drivers/video/backlight/l4f00242t03.c index 9093ef0..ac20b2e 100644
> > > --- a/drivers/video/backlight/l4f00242t03.c
> > > +++ b/drivers/video/backlight/l4f00242t03.c
> > > @@ -78,7 +78,7 @@ static int l4f00242t03_lcd_power_set(struct lcd_device
> > > *ld, int power)
> > > 
> > >  	const u16 slpin = 0x10;
> > >  	const u16 disoff = 0x28;
> > > 
> > > -	if (power) {
> > > +	if (power < FB_BLANK_POWERDOWN) {
> > > 
> > >  		if (priv->lcd_on)
> > >  		
> > >  			return 0;
> > 
> > lcd.h states:
> > struct lcd_ops {
> > 	/* Get the LCD panel power status (0: full on, 1..3: controller
> > 	   power on, flat panel power off, 4: full off), see FB_BLANK_XXX */
> > 	int (*get_power)(struct lcd_device *);
> > 	/* Enable or disable power to the LCD (0: on; 4: off, see FB_BLANK_XXX) 
> */
> > 	int (*set_power)(struct lcd_device *, int power);
> > 
> > AFAIK the gray area between FB_BLANK_NORMAL and FB_BLANK_HSYNC_SUSPEND
> > can be chosen as needs.
> > 
> > Why not:
> > 
> > + #define POWER_IS_ON(pwr)	((pwr) <= FB_BLANK_NORMAL)
> > 
> > ...
> > 
> > -	if (power) {
> > +	if (POWER_IS_ON(power)) {
> >  		if (priv->lcd_on)
> >  			return 0;
> > 
> > So with FB_BLANK_NORMAL the lcd is active and on -> low latencies
> > in re-enabling the video out, but for !POWER_IS_ON(power) we will send
> > the lcd to standby.
> > 
> > It have to be implemented for power == FB_BLANK_POWERDOWN to turn off the
> > regulators of the lcd.
> > 
> > What do you think about?
> 
> Thanks! I sent a new (better) version. If you want credit in it, tell me how 
> should I add you one ;-)

Oh no, you have the credit on it. I admit that my L4F00242T03 is not my 
best driver, but soon I will work on it again ;)

Thank you for your fix!

Regards,

-- 
Alberto!

        Be Persistent!
                - Greg Kroah-Hartman (FOSDEM 2010)



From maramaopercheseimorto at gmail.com  Sat Jun  5 05:25:24 2010
From: maramaopercheseimorto at gmail.com (Alberto Panizzo)
Date: Sat, 05 Jun 2010 11:25:24 +0200
Subject: [PATCH 2/2] backlight: Fix blanking for L4F00242T03 LCD
In-Reply-To: <1275701106-2832-2-git-send-email-marek.vasut@gmail.com>
References: <1275701106-2832-1-git-send-email-marek.vasut@gmail.com>
	<1275701106-2832-2-git-send-email-marek.vasut@gmail.com>
Message-ID: <1275729924.3446.13.camel@realization>

On sab, 2010-06-05 at 03:25 +0200, Marek Vasut wrote:
> The LCD was turned on if the variable power was > 0, but that was incorrect. The
> LCD has to be turned on in every case but POWERDOWN.

The patch is ok for me, but the comment could much more reflect what
the patch does, no?

> 
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> ---
>  drivers/video/backlight/l4f00242t03.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/video/backlight/l4f00242t03.c b/drivers/video/backlight/l4f00242t03.c
> index 9093ef0..c67801e 100644
> --- a/drivers/video/backlight/l4f00242t03.c
> +++ b/drivers/video/backlight/l4f00242t03.c
> @@ -78,7 +78,7 @@ static int l4f00242t03_lcd_power_set(struct lcd_device *ld, int power)
>  	const u16 slpin = 0x10;
>  	const u16 disoff = 0x28;
>  
> -	if (power) {
> +	if (power <= FB_BLANK_NORMAL) {
>  		if (priv->lcd_on)
>  			return 0;
>  




From maramaopercheseimorto at gmail.com  Sat Jun  5 05:35:58 2010
From: maramaopercheseimorto at gmail.com (Alberto Panizzo)
Date: Sat, 05 Jun 2010 11:35:58 +0200
Subject: [V2 3/3] mx51/keypad: add keypad support for i.MX51 platforms
In-Reply-To: <1275566746-6510-4-git-send-email-jason77.wang@gmail.com>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-3-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-4-git-send-email-jason77.wang@gmail.com>
Message-ID: <1275730558.3446.23.camel@realization>

On gio, 2010-06-03 at 20:05 +0800, Jason Wang wrote:
> Add keypad controller device definition for all i.MX51 platforms,
> add a dummy kpp clock for imx keypad driver and add keypad device
> registration on i.MX51 3-stack board.
> 
> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
> ---
>  arch/arm/mach-mx5/board-mx51_3ds.c |   59 ++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-mx5/clock-mx51.c     |    5 +++
>  arch/arm/mach-mx5/devices.c        |   19 +++++++++++
>  arch/arm/mach-mx5/devices.h        |    1 +
>  4 files changed, 84 insertions(+), 0 deletions(-)

May you wont divide platform vs machine code in two different patches.

and, Eric B?nard is working on imx_keypad suspend/resume features[1] and
about it, he is going to modify the platform interface that make us able
to register the device.. this patch could look old in a few.

[1]http://thread.gmane.org/gmane.linux.ports.arm.kernel/80968/focus=13131

Best regards,
Alberto!

> 
> diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
> index 5da90e9..abc9f87 100644
> --- a/arch/arm/mach-mx5/board-mx51_3ds.c
> +++ b/arch/arm/mach-mx5/board-mx51_3ds.c
> @@ -16,6 +16,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/gpio.h>
>  #include <linux/smsc911x.h>
> +#include <linux/input/matrix_keypad.h>
>  
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
> @@ -54,8 +55,65 @@ static struct pad_desc mx51_3ds_pads[] = {
>  
>  	/* CPLD PARENT IRQ PIN */
>  	MX51_PAD_GPIO_1_6__GPIO1_6,
> +
> +	/* KPP */
> +	MX51_PAD_KEY_ROW0__KEY_ROW0,
> +	MX51_PAD_KEY_ROW1__KEY_ROW1,
> +	MX51_PAD_KEY_ROW2__KEY_ROW2,
> +	MX51_PAD_KEY_ROW3__KEY_ROW3,
> +	MX51_PAD_KEY_COL0__KEY_COL0,
> +	MX51_PAD_KEY_COL1__KEY_COL1,
> +	MX51_PAD_KEY_COL2__KEY_COL2,
> +	MX51_PAD_KEY_COL3__KEY_COL3,
> +	MX51_PAD_KEY_COL4__KEY_COL4,
> +	MX51_PAD_KEY_COL5__KEY_COL5,
> +};
> +
> +#if defined(CONFIG_KEYBOARD_IMX) || defined(CONFIG_KEYBOARD_IMX_MODULE)
> +static int mx51_3ds_board_keymap[] = {
> +	KEY(0, 0, KEY_1),
> +	KEY(0, 1, KEY_2),
> +	KEY(0, 2, KEY_3),
> +	KEY(0, 3, KEY_F1),
> +	KEY(0, 4, KEY_UP),
> +	KEY(0, 5, KEY_F2),
> +
> +	KEY(1, 0, KEY_4),
> +	KEY(1, 1, KEY_5),
> +	KEY(1, 2, KEY_6),
> +	KEY(1, 3, KEY_LEFT),
> +	KEY(1, 4, KEY_SELECT),
> +	KEY(1, 5, KEY_RIGHT),
> +
> +	KEY(2, 0, KEY_7),
> +	KEY(2, 1, KEY_8),
> +	KEY(2, 2, KEY_9),
> +	KEY(2, 3, KEY_F3),
> +	KEY(2, 4, KEY_DOWN),
> +	KEY(2, 5, KEY_F4),
> +
> +	KEY(3, 0, KEY_0),
> +	KEY(3, 1, KEY_OK),
> +	KEY(3, 2, KEY_ESC),
> +	KEY(3, 3, KEY_ENTER),
> +	KEY(3, 4, KEY_MENU),
> +	KEY(3, 5, KEY_BACK)
>  };
>  
> +static struct matrix_keymap_data mx51_3ds_map_data = {
> +	.keymap		= mx51_3ds_board_keymap,
> +	.keymap_size	= ARRAY_SIZE(mx51_3ds_board_keymap),
> +};
> +
> +static void mxc_init_keypad(void)
> +{
> +	mxc_register_device(&mxc_keypad_device, &mx51_3ds_map_data);
> +}
> +#else
> +static inline void mxc_init_keypad(void)
> +{
> +}
> +#endif
>  
>  #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
>  static struct resource smsc911x_resources[] = {
> @@ -241,6 +299,7 @@ static void __init mxc_board_init(void)
>  	mxc_init_imx_uart();
>  	mxc_expio_init();
>  	mxc_init_enet();
> +	mxc_init_keypad();
>  }
>  
>  static void __init mx51_3ds_timer_init(void)
> diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
> index d9f612d..60fced6 100644
> --- a/arch/arm/mach-mx5/clock-mx51.c
> +++ b/arch/arm/mach-mx5/clock-mx51.c
> @@ -758,6 +758,10 @@ static struct clk gpt_32k_clk = {
>  	.parent = &ckil_clk,
>  };
>  
> +static struct clk kpp_clk = {
> +	.id = 0,
> +};
> +
>  #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
>  	static struct clk name = {			\
>  		.id		= i,			\
> @@ -821,6 +825,7 @@ static struct clk_lookup lookups[] = {
>  	_REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
>  	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
>  	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
> +	_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
>  };
>  
>  static void clk_tree_init(void)
> diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
> index 7130449..2aa4ea0 100644
> --- a/arch/arm/mach-mx5/devices.c
> +++ b/arch/arm/mach-mx5/devices.c
> @@ -168,6 +168,25 @@ struct platform_device mxc_wdt = {
>  	.resource = mxc_wdt_resources,
>  };
>  
> +static struct resource mxc_kpp_resources[] = {
> +	{
> +		.start = MX51_MXC_INT_KPP,
> +		.end = MX51_MXC_INT_KPP,
> +		.flags = IORESOURCE_IRQ,
> +	} , {
> +		.start = MX51_KPP_BASE_ADDR,
> +		.end = MX51_KPP_BASE_ADDR + 0x8 - 1,
> +		.flags = IORESOURCE_MEM,
> +	},
> +};
> +
> +struct platform_device mxc_keypad_device = {
> +	.name = "imx-keypad",
> +	.id = 0,
> +	.num_resources = ARRAY_SIZE(mxc_kpp_resources),
> +	.resource = mxc_kpp_resources,
> +};
> +
>  static struct mxc_gpio_port mxc_gpio_ports[] = {
>  	{
>  		.chip.label = "gpio-0",
> diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
> index c879ae7..1fef140 100644
> --- a/arch/arm/mach-mx5/devices.h
> +++ b/arch/arm/mach-mx5/devices.h
> @@ -6,3 +6,4 @@ extern struct platform_device mxc_usbdr_host_device;
>  extern struct platform_device mxc_usbh1_device;
>  extern struct platform_device mxc_usbdr_udc_device;
>  extern struct platform_device mxc_wdt;
> +extern struct platform_device mxc_keypad_device;




From mcuos.com at gmail.com  Sat Jun  5 05:37:21 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Sat, 05 Jun 2010 17:37:21 +0800
Subject: [PATCH] MTD/pxa: use __devexit, __devinit  and __devexit_p for pxa3xx
	nand
Message-ID: <4C0A1AD1.5090008@gmail.com>

This patch is to use __devexit, __devinit  and __devexit_p for pxa3xx nand driver.

Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>

---
 drivers/mtd/nand/pxa3xx_nand.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index e02fa4f..7ba1853 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1206,7 +1206,7 @@ static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
 	this->chip_delay = 25;
 }

-static int pxa3xx_nand_probe(struct platform_device *pdev)
+static int __devinit pxa3xx_nand_probe(struct platform_device *pdev)
 {
 	struct pxa3xx_nand_platform_data *pdata;
 	struct pxa3xx_nand_info *info;
@@ -1354,7 +1354,7 @@ fail_free_mtd:
 	return ret;
 }

-static int pxa3xx_nand_remove(struct platform_device *pdev)
+static int __devexit pxa3xx_nand_remove(struct platform_device *pdev)
 {
 	struct mtd_info *mtd = platform_get_drvdata(pdev);
 	struct pxa3xx_nand_info *info = mtd->priv;
@@ -1419,7 +1419,7 @@ static struct platform_driver pxa3xx_nand_driver = {
 		.name	= "pxa3xx-nand",
 	},
 	.probe		= pxa3xx_nand_probe,
-	.remove		= pxa3xx_nand_remove,
+	.remove		= __devexit_p(pxa3xx_nand_remove),
 	.suspend	= pxa3xx_nand_suspend,
 	.resume		= pxa3xx_nand_resume,
 };
-- 
1.6.3.3


From marek.vasut at gmail.com  Sat Jun  5 05:46:59 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat, 5 Jun 2010 11:46:59 +0200
Subject: [PATCH 2/2] backlight: Fix blanking for L4F00242T03 LCD
In-Reply-To: <1275729722.3446.10.camel@realization>
References: <1275630748-10722-1-git-send-email-marek.vasut@gmail.com>
	<201006050325.47060.marek.vasut@gmail.com>
	<1275729722.3446.10.camel@realization>
Message-ID: <201006051146.59731.marek.vasut@gmail.com>

Dne So 5. ?ervna 2010 11:22:02 Alberto Panizzo napsal(a):
> On sab, 2010-06-05 at 03:25 +0200, Marek Vasut wrote:
> > Dne P? 4. ?ervna 2010 09:29:43 Alberto Panizzo napsal(a):
> > > On ven, 2010-06-04 at 07:52 +0200, Marek Vasut wrote:
> > > > The LCD was turned on if the variable power was > 0, but that was
> > > > incorrect. The LCD has to be turned on in every case but POWERDOWN.
> > > > 
> > > > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> > > 
> > > Ack
> > > 
> > > > ---
> > > > 
> > > >  drivers/video/backlight/l4f00242t03.c |    2 +-
> > > >  1 files changed, 1 insertions(+), 1 deletions(-)
> > > > 
> > > > diff --git a/drivers/video/backlight/l4f00242t03.c
> > > > b/drivers/video/backlight/l4f00242t03.c index 9093ef0..ac20b2e 100644
> > > > --- a/drivers/video/backlight/l4f00242t03.c
> > > > +++ b/drivers/video/backlight/l4f00242t03.c
> > > > @@ -78,7 +78,7 @@ static int l4f00242t03_lcd_power_set(struct
> > > > lcd_device *ld, int power)
> > > > 
> > > >  	const u16 slpin = 0x10;
> > > >  	const u16 disoff = 0x28;
> > > > 
> > > > -	if (power) {
> > > > +	if (power < FB_BLANK_POWERDOWN) {
> > > > 
> > > >  		if (priv->lcd_on)
> > > >  		
> > > >  			return 0;
> > > 
> > > lcd.h states:
> > > struct lcd_ops {
> > > 
> > > 	/* Get the LCD panel power status (0: full on, 1..3: controller
> > > 	
> > > 	   power on, flat panel power off, 4: full off), see FB_BLANK_XXX */
> > > 	
> > > 	int (*get_power)(struct lcd_device *);
> > > 	/* Enable or disable power to the LCD (0: on; 4: off, see
> > > 	FB_BLANK_XXX)
> > 
> > */
> > 
> > > 	int (*set_power)(struct lcd_device *, int power);
> > > 
> > > AFAIK the gray area between FB_BLANK_NORMAL and FB_BLANK_HSYNC_SUSPEND
> > > can be chosen as needs.
> > > 
> > > Why not:
> > > 
> > > + #define POWER_IS_ON(pwr)	((pwr) <= FB_BLANK_NORMAL)
> > > 
> > > ...
> > > 
> > > -	if (power) {
> > > +	if (POWER_IS_ON(power)) {
> > > 
> > >  		if (priv->lcd_on)
> > >  		
> > >  			return 0;
> > > 
> > > So with FB_BLANK_NORMAL the lcd is active and on -> low latencies
> > > in re-enabling the video out, but for !POWER_IS_ON(power) we will send
> > > the lcd to standby.
> > > 
> > > It have to be implemented for power == FB_BLANK_POWERDOWN to turn off
> > > the regulators of the lcd.
> > > 
> > > What do you think about?
> > 
> > Thanks! I sent a new (better) version. If you want credit in it, tell me
> > how should I add you one ;-)
> 
> Oh no, you have the credit on it. I admit that my L4F00242T03 is not my
> best driver, but soon I will work on it again ;)

You're very welcome, you did a great job!
> 
> Thank you for your fix!
> 
> Regards,


From marek.vasut at gmail.com  Sat Jun  5 05:47:22 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat, 5 Jun 2010 11:47:22 +0200
Subject: [PATCH 2/2] backlight: Fix blanking for L4F00242T03 LCD
In-Reply-To: <1275729924.3446.13.camel@realization>
References: <1275701106-2832-1-git-send-email-marek.vasut@gmail.com>
	<1275701106-2832-2-git-send-email-marek.vasut@gmail.com>
	<1275729924.3446.13.camel@realization>
Message-ID: <201006051147.22655.marek.vasut@gmail.com>

Dne So 5. ?ervna 2010 11:25:24 Alberto Panizzo napsal(a):
> On sab, 2010-06-05 at 03:25 +0200, Marek Vasut wrote:
> > The LCD was turned on if the variable power was > 0, but that was
> > incorrect. The LCD has to be turned on in every case but POWERDOWN.
> 
> The patch is ok for me, but the comment could much more reflect what
> the patch does, no?

Thanks for validating my work, we'll have another round ;)
> 
> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> > ---
> > 
> >  drivers/video/backlight/l4f00242t03.c |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> > 
> > diff --git a/drivers/video/backlight/l4f00242t03.c
> > b/drivers/video/backlight/l4f00242t03.c index 9093ef0..c67801e 100644
> > --- a/drivers/video/backlight/l4f00242t03.c
> > +++ b/drivers/video/backlight/l4f00242t03.c
> > @@ -78,7 +78,7 @@ static int l4f00242t03_lcd_power_set(struct lcd_device
> > *ld, int power)
> > 
> >  	const u16 slpin = 0x10;
> >  	const u16 disoff = 0x28;
> > 
> > -	if (power) {
> > +	if (power <= FB_BLANK_NORMAL) {
> > 
> >  		if (priv->lcd_on)
> >  		
> >  			return 0;


From marek.vasut at gmail.com  Sat Jun  5 05:50:40 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat,  5 Jun 2010 11:50:40 +0200
Subject: [PATCH 1/2] backlight: Fix blanking for LMS283GF05 LCD
Message-ID: <1275731441-7612-1-git-send-email-marek.vasut@gmail.com>

The LCD was turned on if the variable power was > 0, but that was incorrect. The
LCD has to be turned on in NORMAL and UNBLANK case.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/video/backlight/lms283gf05.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/video/backlight/lms283gf05.c b/drivers/video/backlight/lms283gf05.c
index abc43a0..5d3cf33 100644
--- a/drivers/video/backlight/lms283gf05.c
+++ b/drivers/video/backlight/lms283gf05.c
@@ -129,7 +129,7 @@ static int lms283gf05_power_set(struct lcd_device *ld, int power)
 	struct spi_device *spi = st->spi;
 	struct lms283gf05_pdata *pdata = spi->dev.platform_data;
 
-	if (power) {
+	if (power <= FB_BLANK_NORMAL) {
 		if (pdata)
 			lms283gf05_reset(pdata->reset_gpio,
 					pdata->reset_inverted);
-- 
1.7.1



From marek.vasut at gmail.com  Sat Jun  5 05:50:41 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat,  5 Jun 2010 11:50:41 +0200
Subject: [PATCH 2/2] backlight: Fix blanking for L4F00242T03 LCD
In-Reply-To: <1275731441-7612-1-git-send-email-marek.vasut@gmail.com>
References: <1275731441-7612-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1275731441-7612-2-git-send-email-marek.vasut@gmail.com>

The LCD was turned on if the variable power was > 0, but that was incorrect. The
LCD has to be turned on in NORMAL and UNBLANK case.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/video/backlight/l4f00242t03.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/video/backlight/l4f00242t03.c b/drivers/video/backlight/l4f00242t03.c
index 9093ef0..c67801e 100644
--- a/drivers/video/backlight/l4f00242t03.c
+++ b/drivers/video/backlight/l4f00242t03.c
@@ -78,7 +78,7 @@ static int l4f00242t03_lcd_power_set(struct lcd_device *ld, int power)
 	const u16 slpin = 0x10;
 	const u16 disoff = 0x28;
 
-	if (power) {
+	if (power <= FB_BLANK_NORMAL) {
 		if (priv->lcd_on)
 			return 0;
 
-- 
1.7.1



From davem at davemloft.net  Sat Jun  5 05:55:01 2010
From: davem at davemloft.net (David Miller)
Date: Sat, 05 Jun 2010 02:55:01 -0700 (PDT)
Subject: [PATCH] fec: convert legacy PM hooks to dem_pm_ops
In-Reply-To: <20100602192704.GA22726@hera.kernel.org>
References: <20100602192704.GA22726@hera.kernel.org>
Message-ID: <20100605.025501.68155297.davem@davemloft.net>

From: Denis Kirjanov <dkirjanov at hera.kernel.org>
Date: Wed, 2 Jun 2010 19:27:04 +0000

> This patch compile tested only.
> 
> Convert legacy PM hooks to dev_pm_ops
> Signed-off-by: Denis Kirjanov <dkirjanov at kernel.org>

Applied, thanks.


From jason77.wang at gmail.com  Sat Jun  5 10:13:34 2010
From: jason77.wang at gmail.com (jason)
Date: Sat, 05 Jun 2010 22:13:34 +0800
Subject: [V2 3/3] mx51/keypad: add keypad support for i.MX51 platforms
In-Reply-To: <1275730558.3446.23.camel@realization>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>	
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>	
	<1275566746-6510-3-git-send-email-jason77.wang@gmail.com>	
	<1275566746-6510-4-git-send-email-jason77.wang@gmail.com>
	<1275730558.3446.23.camel@realization>
Message-ID: <4C0A5B8E.4020906@gmail.com>

Alberto Panizzo wrote:
> On gio, 2010-06-03 at 20:05 +0800, Jason Wang wrote:
>   
>> Add keypad controller device definition for all i.MX51 platforms,
>> add a dummy kpp clock for imx keypad driver and add keypad device
>> registration on i.MX51 3-stack board.
>>
>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>> ---
>>  arch/arm/mach-mx5/board-mx51_3ds.c |   59 ++++++++++++++++++++++++++++++++++++
>>  arch/arm/mach-mx5/clock-mx51.c     |    5 +++
>>  arch/arm/mach-mx5/devices.c        |   19 +++++++++++
>>  arch/arm/mach-mx5/devices.h        |    1 +
>>  4 files changed, 84 insertions(+), 0 deletions(-)
>>     
>
> May you wont divide platform vs machine code in two different patches.
>   
Thanks for your comments, but here i don't really know what you mean,
should i divide this patch to 2 patches or ?
> and, Eric B?nard is working on imx_keypad suspend/resume features[1] and
> about it, he is going to modify the platform interface that make us able
> to register the device.. this patch could look old in a few.
>
> [1]http://thread.gmane.org/gmane.linux.ports.arm.kernel/80968/focus=13131
>
> Best regards,
> Alberto!
>
>   
Yes, reading this thread, my platform interface is old.
I just git pull the upstream, it seems that new interface change hasn't 
been merged,
i will modify this interface if it is merged into the upstream.

Thanks,
Jason.
>> diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
>> index 5da90e9..abc9f87 100644
>> --- a/arch/arm/mach-mx5/board-mx51_3ds.c
>> +++ b/arch/arm/mach-mx5/board-mx51_3ds.c
>> @@ -16,6 +16,7 @@
>>     
<snip>



From mcuos.com at gmail.com  Sat Jun  5 10:29:39 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Sat, 05 Jun 2010 22:29:39 +0800
Subject: [PATCH] RTC/pxa: remove unnecessary private ops->ioctl()
Message-ID: <4C0A5F53.6070600@gmail.com>

Please, do not implement private ops->ioctl() unless absolutely necessary.
pxa series RTC driver's ioctl() is unnecessary, since RTC subsystem has implement
the ioctl() very well,so we can only use the API of '.alarm_irq_enable' and
'.update_irq_enable' to do enable irq action.

Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
---
 drivers/rtc/rtc-pxa.c |   41 ++++++++++++++++++++++-------------------
 1 files changed, 22 insertions(+), 19 deletions(-)

diff --git a/drivers/rtc/rtc-pxa.c b/drivers/rtc/rtc-pxa.c
index e9c6fa0..8ba4af8 100644
--- a/drivers/rtc/rtc-pxa.c
+++ b/drivers/rtc/rtc-pxa.c
@@ -236,32 +236,34 @@ static int pxa_periodic_irq_set_state(struct device *dev, int enabled)
 	return 0;
 }

-static int pxa_rtc_ioctl(struct device *dev, unsigned int cmd,
-		unsigned long arg)
+static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
 {
 	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
-	int ret = 0;

 	spin_lock_irq(&pxa_rtc->lock);
-	switch (cmd) {
-	case RTC_AIE_OFF:
-		rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
-		break;
-	case RTC_AIE_ON:
+
+	if (enabled)
 		rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
-		break;
-	case RTC_UIE_OFF:
-		rtsr_clear_bits(pxa_rtc, RTSR_HZE);
-		break;
-	case RTC_UIE_ON:
+	else
+		rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
+
+	spin_unlock_irq(&pxa_rtc->lock);
+	return 0;
+}
+
+static int pxa_update_irq_enable(struct device *dev, unsigned int enabled)
+{
+	struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
+
+	spin_lock_irq(&pxa_rtc->lock);
+
+	if (enabled)
 		rtsr_set_bits(pxa_rtc, RTSR_HZE);
-		break;
-	default:
-		ret = -ENOIOCTLCMD;
-	}
+	else
+		rtsr_clear_bits(pxa_rtc, RTSR_HZE);

 	spin_unlock_irq(&pxa_rtc->lock);
-	return ret;
+	return 0;
 }

 static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
@@ -340,11 +342,12 @@ static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
 static const struct rtc_class_ops pxa_rtc_ops = {
 	.open = pxa_rtc_open,
 	.release = pxa_rtc_release,
-	.ioctl = pxa_rtc_ioctl,
 	.read_time = pxa_rtc_read_time,
 	.set_time = pxa_rtc_set_time,
 	.read_alarm = pxa_rtc_read_alarm,
 	.set_alarm = pxa_rtc_set_alarm,
+	.alarm_irq_enable = pxa_alarm_irq_enable,
+	.update_irq_enable = pxa_update_irq_enable,
 	.proc = pxa_rtc_proc,
 	.irq_set_state = pxa_periodic_irq_set_state,
 	.irq_set_freq = pxa_periodic_irq_set_freq,
-- 
1.6.3.3


From sshtylyov at mvista.com  Sat Jun  5 13:18:17 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Sat, 05 Jun 2010 21:18:17 +0400
Subject: [PATCHv2 1/3] MTD/pxa: use __devinit for pxa2xx_flash_probe
In-Reply-To: <4C0A13BA.6050700@gmail.com>
References: <4C0A13BA.6050700@gmail.com>
Message-ID: <4C0A86D9.2070106@mvista.com>

Wan ZongShun wrote:

> This patch is to use the '__devinit' for pxa2xx_flash_probe.

    Why? Is it hot-pluggable device? I guess not...

> Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
> Acked-by: Eric Miao <eric.y.miao at gmail.com>

WBR, Sergei



From marek.vasut at gmail.com  Sat Jun  5 13:19:17 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat, 5 Jun 2010 19:19:17 +0200
Subject: pxa300 - DDRAM base value
In-Reply-To: <1275371058.7001.35.camel@balakrishnan-desktop>
References: <1275371058.7001.35.camel@balakrishnan-desktop>
Message-ID: <201006051919.17738.marek.vasut@gmail.com>

Dne ?t 1. ?ervna 2010 07:44:18 balakrishnan napsal(a):
> I am working on pxa300 based development board and using Linux 2.6.34.
> This Linux kernel already has support for following boards
> 1. zylonite_pxa300
> 2. cm-x300
> 3. colibri-pxa300
> 4. littleton
> 
> My doubt is that pxa300 based boards are using "0xa0000000"  as DDRAM
> base and PHYS_OFFSET is also defined in
> "arch/arm/mach-pxa/include/mach/memory.h" as 0xa0000000.
> But in our board  DDR is mapped in 0x80000000. Does it make any
> problem?. Because after mmu is turned ON, my board is hanging.
> 
> "zreladdr-y   := 0x80008000" is defined in
> "arch/arm/mach-pxa/Makefile.boot" file .
> my machine_desc is as follows
> .phys_io        = 0x40000000,
> .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
> .boot_params    = 0x80000100,
> 

Try editing both arch/arm/mach-pxa/Makefile.boot and 
arch/arm/mach/pxa/include/mach/memory.h

> With Thanks
> J.Balakrishnan

The 0x80000000 should be aliased to 0xa0000000, but looking into the PXA docs, 
it is only on pxa320. Eric, any ideas on this ?


From grant.likely at secretlab.ca  Sat Jun  5 14:19:40 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sat, 5 Jun 2010 12:19:40 -0600
Subject: [PATCH 0/10] Tegra platform support
In-Reply-To: <1275635441-17378-1-git-send-email-olof@lixom.net>
References: <3478yvr76gerav> <1275635441-17378-1-git-send-email-olof@lixom.net>
Message-ID: <AANLkTimbXbSWsNEjlTCsDK0IdYO6Ys4lttr7C8ICq8Ct@mail.gmail.com>

On Fri, Jun 4, 2010 at 1:10 AM, Olof Johansson <olof at lixom.net> wrote:
>
> Hi,
>
> This is for the most part a repost of the arch/arm/mach-tegra parts of
> Erik Gilling's post of the Tegra series from April 13. I've done some
> minor cleanups and picked up a couple of bugfixes from later patches,
> but I wanted to keep the original series bite size for easier review.
>
> There is more to come once this is in.
>
> Russell, do you prefer to take the initial series and feed it to Linus, or
> should I send a direct pull request with your acked-by (once you give it)?

Hey Olof,  What is the url of your git tree?

Thanks,
g.


From kmpark at infradead.org  Sun Jun  6 01:03:39 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Sun, 6 Jun 2010 14:03:39 +0900
Subject: FYI: Qemu support on s5pc110
Message-ID: <AANLkTil8bmtwXNYpMhtPqK21_Z-kEi9wZSOoZtd1n7ML@mail.gmail.com>

Dear all,

FYI: My team release the qemu support on s5pc110 at
http://en.sourceforge.jp/projects/sfnet_slp-emulator/

You can find a s5pc110 files at hw directories.

The current mainline kernel, aquila and goni is will be run with this qemu.

Thank you,
Kyungmin Park


From grinberg at compulab.co.il  Sun Jun  6 02:15:10 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Sun, 06 Jun 2010 09:15:10 +0300
Subject: [PATCH 0/5] Enable pxa310 usb otg port host mode.
In-Reply-To: <AANLkTil7KUMIqP76bXAOOCiAfISzCiixtMzNDAHo7kNo@mail.gmail.com>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
	<AANLkTil7KUMIqP76bXAOOCiAfISzCiixtMzNDAHo7kNo@mail.gmail.com>
Message-ID: <4C0B3CEE.80000@compulab.co.il>

ping!

On 06/02/10 11:29, Eric Miao wrote:
> On Wed, Jun 2, 2010 at 3:40 PM, Igor Grinberg <grinberg at compulab.co.il> wrote:
>   
>> This patch series extends the existing usb ulpi generic driver
>> with support for Function and Interface control of the ULPI PHYs,
>> adds support for SMSC USB3319 ulpi phy,
>> implement the pxa310 specific ulpi functionality and make pxa specific ohci
>> implementation aware of pxa310 usb otg port host mode.
>>
>>     
> Looks like a right way to go, include Haojian and Jing for review.
>
>   
>> Igor Grinberg (5):
>>  usb/otg/ulpi: extend the generic ulpi driver.
>>  usb/otg/ulpi: add support for SMSC USB3319 ulpi phy.
>>  [ARM] pxa: add PXA310 specific ULPI implementation
>>  [ARM] usb/host/ohci-pxa27x: make PXA310 USB OTG port work in host
>>    mode.
>>  [ARM] pxa/cm-x300: enable USB host port 2 on CM-X300 with PXA310 cpu.
>>
>>  arch/arm/mach-mx2/mach-pca100.c              |   10 +-
>>  arch/arm/mach-mx3/mach-armadillo5x0.c        |   10 +-
>>  arch/arm/mach-mx3/mach-mx31lite.c            |    5 +-
>>  arch/arm/mach-mx3/mach-mx31moboard.c         |    5 +-
>>  arch/arm/mach-mx3/mach-pcm037.c              |   10 +-
>>  arch/arm/mach-mx3/mach-pcm043.c              |    5 +-
>>  arch/arm/mach-pxa/Kconfig                    |    4 +
>>  arch/arm/mach-pxa/Makefile                   |    1 +
>>  arch/arm/mach-pxa/cm-x300.c                  |  102 ++++++++++++++
>>  arch/arm/mach-pxa/include/mach/ohci.h        |    3 +
>>  arch/arm/mach-pxa/include/mach/pxa310-ulpi.h |   19 +++
>>  arch/arm/mach-pxa/include/mach/regs-u2d.h    |    2 +
>>  arch/arm/mach-pxa/pxa310-ulpi.c              |  110 +++++++++++++++
>>  drivers/usb/host/ohci-pxa27x.c               |  183 ++++++++++++++++++++++++++
>>  drivers/usb/otg/Kconfig                      |    2 -
>>  drivers/usb/otg/ulpi.c                       |   65 ++++++++-
>>  include/linux/usb/ulpi.h                     |   25 ++++-
>>  17 files changed, 542 insertions(+), 19 deletions(-)
>>  create mode 100644 arch/arm/mach-pxa/include/mach/pxa310-ulpi.h
>>  create mode 100644 arch/arm/mach-pxa/pxa310-ulpi.c
>>
>>
>>     
>   

-- 
Regards,
Igor.



From eric.y.miao at gmail.com  Sun Jun  6 04:17:00 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sun, 6 Jun 2010 16:17:00 +0800
Subject: pxa300 - DDRAM base value
In-Reply-To: <201006051919.17738.marek.vasut@gmail.com>
References: <1275371058.7001.35.camel@balakrishnan-desktop> 
	<201006051919.17738.marek.vasut@gmail.com>
Message-ID: <AANLkTil5TWYILcdp872as8S8LMqQWhPYWLt7cxs2lUm5@mail.gmail.com>

On Sun, Jun 6, 2010 at 1:19 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dne ?t 1. ?ervna 2010 07:44:18 balakrishnan napsal(a):
>> I am working on pxa300 based development board and using Linux 2.6.34.
>> This Linux kernel already has support for following boards
>> 1. zylonite_pxa300
>> 2. cm-x300
>> 3. colibri-pxa300
>> 4. littleton
>>
>> My doubt is that pxa300 based boards are using "0xa0000000" ?as DDRAM
>> base and PHYS_OFFSET is also defined in
>> "arch/arm/mach-pxa/include/mach/memory.h" as 0xa0000000.
>> But in our board ?DDR is mapped in 0x80000000. Does it make any
>> problem?. Because after mmu is turned ON, my board is hanging.
>>
>> "zreladdr-y ? := 0x80008000" is defined in
>> "arch/arm/mach-pxa/Makefile.boot" file .
>> my machine_desc is as follows
>> .phys_io ? ? ? ?= 0x40000000,
>> .io_pg_offst ? ?= (io_p2v(0x40000000) >> 18) & 0xfffc,
>> .boot_params ? ?= 0x80000100,
>>
>
> Try editing both arch/arm/mach-pxa/Makefile.boot and
> arch/arm/mach/pxa/include/mach/memory.h
>
>> With Thanks
>> J.Balakrishnan
>
> The 0x80000000 should be aliased to 0xa0000000, but looking into the PXA docs,
> it is only on pxa320. Eric, any ideas on this ?
>

Should be working on pxa300/310 as well. If it doesn't, check you bootloader
to make sure the mapping is OK, and memory doesn't exceed
(0xa000_0000 - 0x8000_0000).


From eric.y.miao at gmail.com  Sun Jun  6 05:27:58 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sun, 6 Jun 2010 17:27:58 +0800
Subject: [PATCHv2 1/3] MTD/pxa: use __devinit for pxa2xx_flash_probe
In-Reply-To: <4C0A86D9.2070106@mvista.com>
References: <4C0A13BA.6050700@gmail.com> <4C0A86D9.2070106@mvista.com>
Message-ID: <AANLkTinRQ2TwU0fj2k70GdNFKmOVQ4DLc2xELu7HnnZ5@mail.gmail.com>

On Sun, Jun 6, 2010 at 1:18 AM, Sergei Shtylyov <sshtylyov at mvista.com> wrote:
> Wan ZongShun wrote:
>
>> This patch is to use the '__devinit' for pxa2xx_flash_probe.
>
> ? Why? Is it hot-pluggable device? I guess not...
>

Then I guess the __devexit is not applicable to pxa2xx_flash_remove as well.
Apart from the _probe() being unnecessarily built in when HOTPLUG is
defined, is there any drawbacks. It does make code a little bit consistent
from my POV.

>> Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
>> Acked-by: Eric Miao <eric.y.miao at gmail.com>
>
> WBR, Sergei
>
>


From saeed at marvell.com  Sun Jun  6 06:24:42 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Sun,  6 Jun 2010 13:24:42 +0300
Subject: [PATCH 3/3 v3] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <alpine.LFD.2.00.1006031224180.24526@xanadu.home>
References: <alpine.LFD.2.00.1006031224180.24526@xanadu.home>
Message-ID: <1275819882-8373-1-git-send-email-saeed@marvell.com>

This patch extens the kirkwood's PCIe support up to 2 controllers as in the 6282 devices.

Signed-off-by: Saeed Bishara <saeed at marvell.com>
---
 arch/arm/mach-kirkwood/addr-map.c                 |   10 +-
 arch/arm/mach-kirkwood/common.h                   |    5 +-
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c       |   10 +-
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h |    1 +
 arch/arm/mach-kirkwood/include/mach/irqs.h        |    1 +
 arch/arm/mach-kirkwood/include/mach/kirkwood.h    |   10 +
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c    |    2 +-
 arch/arm/mach-kirkwood/openrd-setup.c             |    2 +-
 arch/arm/mach-kirkwood/pcie.c                     |  187 +++++++++++++++-----
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c      |    2 +-
 arch/arm/mach-kirkwood/rd88f6281-setup.c          |    2 +-
 arch/arm/mach-kirkwood/ts219-setup.c              |    6 +-
 arch/arm/mach-kirkwood/ts41x-setup.c              |    2 +-
 13 files changed, 180 insertions(+), 60 deletions(-)

diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168..8d03bce 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
 #define ATTR_DEV_CS0		0x3e
 #define ATTR_PCIE_IO		0xe0
 #define ATTR_PCIE_MEM		0xe8
+#define ATTR_PCIE1_IO		0xd0
+#define ATTR_PCIE1_MEM		0xd8
 #define ATTR_SRAM		0x01
 
 /*
@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
 		      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
 	setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
 		      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
+	setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
+		      TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
+	setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
+		      TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
 
 	/*
 	 * Setup window for NAND controller.
 	 */
-	setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+	setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
 		      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
 
 	/*
 	 * Setup window for SRAM.
 	 */
-	setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+	setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
 		      TARGET_SRAM, ATTR_SRAM, -1);
 
 	/*
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05e8a8a..5b2c1c1 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -18,6 +18,9 @@ struct mvsdio_platform_data;
 struct mtd_partition;
 struct mtd_info;
 
+#define KW_PCIE0	(1 << 0)
+#define KW_PCIE1	(1 << 1)
+
 /*
  * Basic Kirkwood init functions used early by machine-setup.
  */
@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);
 void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
-void kirkwood_pcie_init(void);
+void kirkwood_pcie_init(unsigned int portmask);
 void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
 void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
 void kirkwood_spi_init(void);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4b..c428348 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -74,9 +74,15 @@ static void __init db88f6281_init(void)
 
 static int __init db88f6281_pci_init(void)
 {
-	if (machine_is_db88f6281_bp())
-		kirkwood_pcie_init();
+	if (machine_is_db88f6281_bp()) {
+		u32 dev, rev;
 
+		kirkwood_pcie_id(&dev, &rev);
+		if (dev == MV88F6282_DEV_ID)
+			kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
+		else
+			kirkwood_pcie_init(KW_PCIE0);
+	}
 	return 0;
 }
 subsys_initcall(db88f6281_pci_init);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f501..2026b30 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,6 +59,7 @@
 #define CGC_SATA1		(1 << 15)
 #define CGC_XOR1		(1 << 16)
 #define CGC_CRYPTO		(1 << 17)
+#define CGC_PEX1		(1 << 18)
 #define CGC_GE1			(1 << 19)
 #define CGC_TDM			(1 << 20)
 #define CGC_RESERVED		((1 << 18) | (0x6 << 21))
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index f00a0a4..9da2eb5 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -23,6 +23,7 @@
 #define IRQ_KIRKWOOD_XOR_10	7
 #define IRQ_KIRKWOOD_XOR_11	8
 #define IRQ_KIRKWOOD_PCIE	9
+#define IRQ_KIRKWOOD_PCIE1	10
 #define IRQ_KIRKWOOD_GE00_SUM	11
 #define IRQ_KIRKWOOD_GE01_SUM	15
 #define IRQ_KIRKWOOD_USB	19
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index dd7eddb..058f06b 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -38,6 +38,11 @@
 #define KIRKWOOD_PCIE_IO_BUS_BASE	0x00000000
 #define KIRKWOOD_PCIE_IO_SIZE		SZ_1M
 
+#define KIRKWOOD_PCIE1_IO_PHYS_BASE	0xf5000000
+#define KIRKWOOD_PCIE1_IO_VIRT_BASE	0xfed00000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE	0x00000000
+#define KIRKWOOD_PCIE1_IO_SIZE		SZ_1M
+
 #define KIRKWOOD_REGS_PHYS_BASE		0xf1000000
 #define KIRKWOOD_REGS_VIRT_BASE		0xfee00000
 #define KIRKWOOD_REGS_SIZE		SZ_1M
@@ -46,6 +51,10 @@
 #define KIRKWOOD_PCIE_MEM_BUS_BASE	0xe0000000
 #define KIRKWOOD_PCIE_MEM_SIZE		SZ_128M
 
+#define KIRKWOOD_PCIE1_MEM_PHYS_BASE	0xd8000000
+#define KIRKWOOD_PCIE1_MEM_BUS_BASE	0xd8000000
+#define KIRKWOOD_PCIE1_MEM_SIZE		SZ_128M
+
 /*
  * Register Map
  */
@@ -72,6 +81,7 @@
 #define PCIE_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x40000)
 #define PCIE_LINK_CTRL		(PCIE_VIRT_BASE | 0x70)
 #define PCIE_STATUS		(PCIE_VIRT_BASE | 0x1a04)
+#define PCIE1_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x44000)
 
 #define USB_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x50000)
 
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 5e6f711..c6b92b4 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
 static int __init mv88f6281gtw_ge_pci_init(void)
 {
 	if (machine_is_mv88f6281gtw_ge())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec..2400207 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -85,7 +85,7 @@ static void __init openrd_init(void)
 static int __init openrd_pci_init(void)
 {
 	if (machine_is_openrd_base() || machine_is_openrd_client())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index dee1eff..89201a9 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,29 +18,43 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
+void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+{
+	*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
+	*rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+}
 
-#define PCIE_BASE	((void __iomem *)PCIE_VIRT_BASE)
+struct pcie_port {
+	u8			root_bus_nr;
+	void __iomem		*base;
+	spinlock_t		conf_lock;
+	int			irq;
+	struct resource		res[2];
+};
 
-void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+static int pcie_port_map[2];
+static int num_pcie_ports;
+
+static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
 {
-	*dev = orion_pcie_dev_id(PCIE_BASE);
-	*rev = orion_pcie_rev(PCIE_BASE);
+	struct pci_sys_data *sys = bus->sysdata;
+	return sys->private_data;
 }
 
-static int pcie_valid_config(int bus, int dev)
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 {
 	/*
 	 * Don't go out when trying to access --
 	 * 1. nonexisting device on local bus
 	 * 2. where there's no device connected (no link)
 	 */
-	if (bus == 0 && dev == 0)
+	if (bus == pp->root_bus_nr && dev == 0)
 		return 1;
 
-	if (!orion_pcie_link_up(PCIE_BASE))
+	if (!orion_pcie_link_up(pp->base))
 		return 0;
 
-	if (bus == 0 && dev != 1)
+	if (bus == pp->root_bus_nr && dev != 1)
 		return 0;
 
 	return 1;
@@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev)
  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  * transactions are atomic.
  */
-static DEFINE_SPINLOCK(kirkwood_pcie_lock);
 
 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 			int size, u32 *val)
 {
+	struct pcie_port *pp = bus_to_port(bus);
 	unsigned long flags;
 	int ret;
 
-	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
 		*val = 0xffffffff;
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
 
-	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
-	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+	spin_lock_irqsave(&pp->conf_lock, flags);
+	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+	spin_unlock_irqrestore(&pp->conf_lock, flags);
 
 	return ret;
 }
@@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 			int where, int size, u32 val)
 {
+	struct pcie_port *pp = bus_to_port(bus);
 	unsigned long flags;
 	int ret;
 
-	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
-	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
-	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+	spin_lock_irqsave(&pp->conf_lock, flags);
+	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+	spin_unlock_irqrestore(&pp->conf_lock, flags);
 
 	return ret;
 }
@@ -93,50 +108,109 @@ static struct pci_ops pcie_ops = {
 	.write = pcie_wr_conf,
 };
 
-
-static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+static int __init pcie0_ioresouces_setup(struct pci_sys_data *sys)
 {
-	struct resource *res;
-	extern unsigned int kirkwood_clk_ctrl;
-
+	struct pcie_port *pp = (struct pcie_port *)sys->private_data;
 	/*
-	 * Generic PCIe unit setup.
+	 * IORESOURCE_IO
 	 */
-	orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
+	pp->res[0].name = "PCIe 0 I/O Space";
+	pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+	pp->res[0].flags = IORESOURCE_IO;
+	if (request_resource(&ioport_resource, &pp->res[0]))
+		panic("Request PCIe 0 IO resource failed\n");
+	sys->resource[0] = &pp->res[0];
 
 	/*
-	 * Request resources.
+	 * IORESOURCE_MEM
 	 */
-	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-	if (!res)
-		panic("pcie_setup unable to alloc resources");
+	pp->res[1].name = "PCIe 0 MEM";
+	pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+	pp->res[1].flags = IORESOURCE_MEM;
+	if (request_resource(&iomem_resource, &pp->res[1]))
+		panic("Request PCIe 0 Memory resource failed\n");
+	sys->resource[1] = &pp->res[1];
+
+	sys->resource[2] = NULL;
+	sys->io_offset = 0;
 
+	return 1;
+}
+
+static int __init pcie1_ioresouces_setup(struct pci_sys_data *sys)
+{
+	struct pcie_port *pp = (struct pcie_port *)sys->private_data;
 	/*
 	 * IORESOURCE_IO
 	 */
-	res[0].name = "PCIe I/O Space";
-	res[0].flags = IORESOURCE_IO;
-	res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-	res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
-	if (request_resource(&ioport_resource, &res[0]))
-		panic("Request PCIe IO resource failed\n");
-	sys->resource[0] = &res[0];
+	pp->res[0].name = "PCIe 1 I/O Space";
+	pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
+	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
+	pp->res[0].flags = IORESOURCE_IO;
+	if (request_resource(&ioport_resource, &pp->res[0]))
+		panic("Request PCIe 1 IO resource failed\n");
+	sys->resource[0] = &pp->res[0];
 
 	/*
 	 * IORESOURCE_MEM
 	 */
-	res[1].name = "PCIe Memory Space";
-	res[1].flags = IORESOURCE_MEM;
-	res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
-	res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-	if (request_resource(&iomem_resource, &res[1]))
-		panic("Request PCIe Memory resource failed\n");
-	sys->resource[1] = &res[1];
+	pp->res[1].name = "PCIe 1 MEM";
+	pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+	pp->res[1].flags = IORESOURCE_MEM;
+	if (request_resource(&iomem_resource, &pp->res[1]))
+		panic("Request PCIe 1 Memory resource failed\n");
+	sys->resource[1] = &pp->res[1];
 
 	sys->resource[2] = NULL;
 	sys->io_offset = 0;
 
-	kirkwood_clk_ctrl |= CGC_PEX0;
+	return 1;
+}
+
+static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+	extern unsigned int kirkwood_clk_ctrl;
+	struct pcie_port *pp;
+	int index;
+	if (nr >= num_pcie_ports)
+		return 0;
+
+	index = pcie_port_map[nr];
+	printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
+
+	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
+	if (!pp)
+		panic("PCIe: failed to allocate pcie_port data");
+	sys->private_data = pp;
+	pp->root_bus_nr = sys->busnr;
+	spin_lock_init(&pp->conf_lock);
+
+	switch (index) {
+	case 0:
+		pp->base = (void __iomem *)PCIE_VIRT_BASE;
+		pp->irq	= IRQ_KIRKWOOD_PCIE;
+		kirkwood_clk_ctrl |= CGC_PEX0;
+		pcie0_ioresouces_setup(sys);
+		break;
+	case 1:
+		pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+		pp->irq	= IRQ_KIRKWOOD_PCIE1;
+		kirkwood_clk_ctrl |= CGC_PEX1;
+		pcie1_ioresouces_setup(sys);
+		break;
+	default:
+		panic("PCIe setup: invalid controller");
+	}
+
+	/*
+	 * Generic PCIe unit setup.
+	 */
+	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+
+	orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
 
 	return 1;
 }
@@ -163,7 +237,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 {
 	struct pci_bus *bus;
 
-	if (nr == 0) {
+	if (nr < num_pcie_ports) {
 		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
 	} else {
 		bus = NULL;
@@ -175,18 +249,37 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 
 static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-	return IRQ_KIRKWOOD_PCIE;
+	struct pcie_port *pp = bus_to_port(dev->bus);
+
+	return pp->irq;
 }
 
 static struct hw_pci kirkwood_pci __initdata = {
-	.nr_controllers	= 1,
 	.swizzle	= pci_std_swizzle,
 	.setup		= kirkwood_pcie_setup,
 	.scan		= kirkwood_pcie_scan_bus,
 	.map_irq	= kirkwood_pcie_map_irq,
 };
 
-void __init kirkwood_pcie_init(void)
+static void __init add_pcie_port(int index, unsigned long base)
+{
+	printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
+
+	if (orion_pcie_link_up((void __iomem *)base)) {
+		printk(KERN_INFO "link up\n");
+		pcie_port_map[num_pcie_ports++] = index;
+	} else
+		printk(KERN_INFO "link down, ignoring\n");
+}
+
+void __init kirkwood_pcie_init(unsigned int portmask)
 {
+	if (portmask & KW_PCIE0)
+		add_pcie_port(0, PCIE_VIRT_BASE);
+
+	if (portmask & KW_PCIE1)
+		add_pcie_port(1, PCIE1_VIRT_BASE);
+
+	kirkwood_pci.nr_controllers = num_pcie_ports;
 	pci_common_init(&kirkwood_pci);
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 3bf6304..c34718c 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
 static int __init rd88f6192_pci_init(void)
 {
 	if (machine_is_rd88f6192_nas())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31708dd..3d14771 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
 static int __init rd88f6281_pci_init(void)
 {
 	if (machine_is_rd88f6281())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0f..7250087 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -110,10 +110,10 @@ static void __init qnap_ts219_init(void)
 
 static int __init ts219_pci_init(void)
 {
-   if (machine_is_ts219())
-           kirkwood_pcie_init();
+	if (machine_is_ts219())
+		kirkwood_pcie_init(KW_PCIE0);
 
-   return 0;
+	return 0;
 }
 subsys_initcall(ts219_pci_init);
 
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index de49c2d..a122868 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -136,7 +136,7 @@ static void __init qnap_ts41x_init(void)
 static int __init ts41x_pci_init(void)
 {
 	if (machine_is_ts41x())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
    return 0;
 }
-- 
1.6.0.4



From saeed.bishara at gmail.com  Sun Jun  6 06:28:01 2010
From: saeed.bishara at gmail.com (saeed bishara)
Date: Sun, 6 Jun 2010 13:28:01 +0300
Subject: [PATCH 3/5] USB: add clk structure for systems that support 
	clkdev framework
In-Reply-To: <20100502160555.GE4233@n2100.arm.linux.org.uk>
References: <1272810162-14858-1-git-send-email-saeed@marvell.com>
	<1272810162-14858-2-git-send-email-saeed@marvell.com>
	<1272810162-14858-3-git-send-email-saeed@marvell.com>
	<1272810162-14858-4-git-send-email-saeed@marvell.com>
	<20100502143602.GA4233@n2100.arm.linux.org.uk>
	<r2oc70ff3ad1005020805zc80ad8b9n1e56d4a0a6ce5b9c@mail.gmail.com>
	<20100502151425.GC4233@n2100.arm.linux.org.uk>
	<u2wc70ff3ad1005020821z5eb3eec5y5a64b1d5dd3652a@mail.gmail.com>
	<20100502153157.GD4233@n2100.arm.linux.org.uk>
	<i2ic70ff3ad1005020854l2738ace8l3c7c291cf07c9402@mail.gmail.com>
	<20100502160555.GE4233@n2100.arm.linux.org.uk>
Message-ID: <AANLkTik_HV9jx75Pk5IpSdkr0xL6W4S0vihpoKh2bJpJ@mail.gmail.com>

On Sun, May 2, 2010 at 7:05 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Sun, May 02, 2010 at 06:54:15PM +0300, saeed bishara wrote:
>> >> well, I think that those drivers that have more than one clk can be
>> >> redesigned by adding virtual clk for the the usb host, and the clk
>> >> implementation for that soc should manage all the underlying physical
>> >> clocks. I've looked at the omap,at91 and atmel, and it looks to me
>> >> that this is doable. you see can see that the clk stuff in those
>> >> driver has nothing to do with usb itself. what do you think?
>> >
>> > Not happy with this for two reasons:
>> > 1. You're assuming that they can be managed as one entity; that doesn't seem
>> > ? true for some of the drivers.
>> can you please give an example?
>
> drivers/usb/host/ohci-da8xx.c has two clocks, and needs to know the
> configuration of the USB block to know whether to manage the USB2.0
> clock:
>
> ? ? ? ?cfgchip2 = __raw_readl(CFGCHIP2);
> ? ? ? ?if (on) {
> ? ? ? ? ? ? ? ?clk_enable(usb11_clk);
>
> ? ? ? ? ? ? ? ?/*
> ? ? ? ? ? ? ? ? * If USB 1.1 reference clock is sourced from USB 2.0 PHY, we
> ? ? ? ? ? ? ? ? * need to enable the USB 2.0 module clocking, start its PHY,
> ? ? ? ? ? ? ? ? * and not allow it to stop the clock during USB 2.0 suspend.
> ? ? ? ? ? ? ? ? */
> ? ? ? ? ? ? ? ?if (!(cfgchip2 & CFGCHIP2_USB1PHYCLKMUX)) {
> ? ? ? ? ? ? ? ? ? ? ? ?clk_enable(usb20_clk);
>
guys, can I've your opinion about this patch? adding the clk struct
to the hcd struct will save the orion-ehci driver from having private
data structure.

saeed


From saeed at marvell.com  Sun Jun  6 08:28:55 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Sun,  6 Jun 2010 15:28:55 +0300
Subject: [PATCH 1/2] mv643xx_eth: disable csum offloading if the hw limited by
	max size
Message-ID: <1275827336-31111-1-git-send-email-saeed@marvell.com>

Some controllers (KW, Dove) limits the TX IP/layer4 checksum offloading to a max size.

Signed-off-by: Saeed Bishara <saeed at marvell.com>
---
 drivers/net/mv643xx_eth.c   |   10 ++++++++++
 include/linux/mv643xx_eth.h |    4 ++++
 2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index e345ec8..79243dd 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -289,6 +289,7 @@ struct mv643xx_eth_shared_private {
 	unsigned int t_clk;
 	int extended_rx_coal_limit;
 	int tx_bw_control;
+	int tx_csum_limit;
 };
 
 #define TX_BW_CONTROL_ABSENT		0
@@ -2468,6 +2469,14 @@ static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
 	mv643xx_eth_recalc_skb_size(mp);
 	tx_set_rate(mp, 1000000000, 16777216);
 
+	if (mp->shared->tx_csum_limit && dev->mtu > mp->shared->tx_csum_limit) {
+		dev->features &= ~NETIF_F_IP_CSUM;
+		dev->vlan_features &= ~NETIF_F_IP_CSUM;
+	} else {
+		dev->features |= NETIF_F_IP_CSUM;
+		dev->vlan_features |= NETIF_F_IP_CSUM;
+	}
+
 	if (!netif_running(dev))
 		return 0;
 
@@ -2666,6 +2675,7 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 	 * Detect hardware parameters.
 	 */
 	msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
+	msp->tx_csum_limit = pd->tx_csum_limit;
 	infer_hw_params(msp);
 
 	platform_set_drvdata(pdev, msp);
diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
index cbbbe9b..7402718 100644
--- a/include/linux/mv643xx_eth.h
+++ b/include/linux/mv643xx_eth.h
@@ -19,6 +19,10 @@ struct mv643xx_eth_shared_platform_data {
 	struct mbus_dram_target_info	*dram;
 	struct platform_device	*shared_smi;
 	unsigned int		t_clk;
+	/*
+	 * Max packet size for Tx IP/Layer 4 checksum (0 -> no limit)
+	 */
+	int			tx_csum_limit;
 };
 
 #define MV643XX_ETH_PHY_ADDR_DEFAULT	0
-- 
1.6.0.4



From saeed at marvell.com  Sun Jun  6 08:28:56 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Sun,  6 Jun 2010 15:28:56 +0300
Subject: [PATCH 2/2] set packet size limit for the mv643xx csum offloading
In-Reply-To: <1275827336-31111-1-git-send-email-saeed@marvell.com>
References: <1275827336-31111-1-git-send-email-saeed@marvell.com>
Message-ID: <1275827336-31111-2-git-send-email-saeed@marvell.com>

The mv643xx ethernet controller limits the packet size for the TX
checksum offloading. this patch sets this limits for the needed
devices.

Signed-off-by: Saeed Bishara <saeed at marvell.com>
---
 arch/arm/mach-dove/common.c     |    1 +
 arch/arm/mach-kirkwood/common.c |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 5da2cf4..473ce0b 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -149,6 +149,7 @@ void __init dove_ehci1_init(void)
 struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
 	.t_clk		= 0,
 	.dram		= &dove_mbus_dram_info,
+	.tx_csum_limit	= 1600,
 };
 
 static struct resource dove_ge00_shared_resources[] = {
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 4ccfdf9..c4bd8cb 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -114,6 +114,7 @@ void __init kirkwood_ehci_init(void)
  ****************************************************************************/
 struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
 	.dram		= &kirkwood_mbus_dram_info,
+	.tx_csum_limit	= 1600,
 };
 
 static struct resource kirkwood_ge00_shared_resources[] = {
-- 
1.6.0.4



From jic23 at cam.ac.uk  Sun Jun  6 09:55:02 2010
From: jic23 at cam.ac.uk (Jonathan Cameron)
Date: Sun,  6 Jun 2010 14:55:02 +0100
Subject: [RFC PATCH] stargate2 and imote2 board file merge
Message-ID: <1275832502-28552-1-git-send-email-jic23@cam.ac.uk>

Signed-off-by: Jonathan Cameron <jic23 at cam.ac.uk>
---
 These two boards are extremely similar in many ways and hence
 the board configs overlap a lot.  This patch merges the two
 board files.  Do people think this is worth doing?  Traditionally
 we always built a kernel supporting both devices anyway but the
 ifdefs allow one to be picked if people really want to.

 There are a couple of annoying really minor differences in wiring
 that result in most of the non shared code (leds on gpios on the imote2
 and on the da9030 led drivers on the stargate2).

 arch/arm/mach-pxa/Makefile    |    2 +-
 arch/arm/mach-pxa/imote2.c    |  590 -----------------------------------
 arch/arm/mach-pxa/stargate2.c |  679 +++++++++++++++++++++++++++--------------
 3 files changed, 454 insertions(+), 817 deletions(-)

diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index b8f1f4b..31d80ba 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -51,7 +51,7 @@ obj-$(CONFIG_MACH_CAPC7117)     += capc7117.o mxm8x10.o
 obj-$(CONFIG_ARCH_GUMSTIX)	+= gumstix.o
 obj-$(CONFIG_GUMSTIX_AM200EPD)	+= am200epd.o
 obj-$(CONFIG_GUMSTIX_AM300EPD)	+= am300epd.o
-obj-$(CONFIG_MACH_INTELMOTE2)   += imote2.o
+obj-$(CONFIG_MACH_INTELMOTE2)	+= stargate2.o
 obj-$(CONFIG_MACH_STARGATE2)	+= stargate2.o
 obj-$(CONFIG_MACH_XCEP)         += xcep.o
 obj-$(CONFIG_MACH_TRIZEPS4)	+= trizeps4.o
diff --git a/arch/arm/mach-pxa/imote2.c b/arch/arm/mach-pxa/imote2.c
deleted file mode 100644
index 5161dca..0000000
--- a/arch/arm/mach-pxa/imote2.c
+++ /dev/null
@@ -1,590 +0,0 @@
-/*
- * linux/arch/arm/mach-pxa/imote2.c
- *
- * Author:	Ed C. Epp
- * Created:	Nov 05, 2002
- * Copyright:	Intel Corp.
- *
- * Modified 2008:  Jonathan Cameron
- *
- * The Imote2 is a wireless sensor node platform sold
- * by Crossbow (www.xbow.com).
- */
-
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/partitions.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/machine.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/spi/spi.h>
-#include <linux/i2c.h>
-#include <linux/mfd/da903x.h>
-#include <linux/sht15.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-
-#include <mach/pxa27x.h>
-#include <plat/i2c.h>
-#include <mach/udc.h>
-#include <mach/mmc.h>
-#include <mach/pxa2xx_spi.h>
-#include <mach/pxa27x-udc.h>
-
-#include "devices.h"
-#include "generic.h"
-
-static unsigned long imote2_pin_config[] __initdata = {
-
-	/* Device Identification for wakeup*/
-	GPIO102_GPIO,
-
-	/* Button */
-	GPIO91_GPIO,
-
-	/* DA9030 */
-	GPIO1_GPIO,
-
-	/* MMC */
-	GPIO32_MMC_CLK,
-	GPIO112_MMC_CMD,
-	GPIO92_MMC_DAT_0,
-	GPIO109_MMC_DAT_1,
-	GPIO110_MMC_DAT_2,
-	GPIO111_MMC_DAT_3,
-
-	/* 802.15.4 radio - driver out of mainline */
-	GPIO22_GPIO,			/* CC_RSTN */
-	GPIO114_GPIO,			/* CC_FIFO */
-	GPIO116_GPIO,			/* CC_CCA */
-	GPIO0_GPIO,			/* CC_FIFOP */
-	GPIO16_GPIO,			/* CCSFD */
-	GPIO115_GPIO,			/* Power enable */
-
-	/* I2C */
-	GPIO117_I2C_SCL,
-	GPIO118_I2C_SDA,
-
-	/* SSP 3 - 802.15.4 radio */
-	GPIO39_GPIO,			/* Chip Select */
-	GPIO34_SSP3_SCLK,
-	GPIO35_SSP3_TXD,
-	GPIO41_SSP3_RXD,
-
-	/* SSP 2 - to daughter boards */
-	GPIO37_GPIO,			/* Chip Select */
-	GPIO36_SSP2_SCLK,
-	GPIO38_SSP2_TXD,
-	GPIO11_SSP2_RXD,
-
-	/* SSP 1 - to daughter boards */
-	GPIO24_GPIO,			/* Chip Select */
-	GPIO23_SSP1_SCLK,
-	GPIO25_SSP1_TXD,
-	GPIO26_SSP1_RXD,
-
-	/* BTUART Basic Connector*/
-	GPIO42_BTUART_RXD,
-	GPIO43_BTUART_TXD,
-	GPIO44_BTUART_CTS,
-	GPIO45_BTUART_RTS,
-
-	/* STUART Serial console via debug board*/
-	GPIO46_STUART_RXD,
-	GPIO47_STUART_TXD,
-
-	/* Basic sensor board */
-	GPIO96_GPIO,	/* accelerometer interrupt */
-	GPIO99_GPIO,	/* ADC interrupt */
-
-	/* SHT15 */
-	GPIO100_GPIO,
-	GPIO98_GPIO,
-
-	/* Connector pins specified as gpios */
-	GPIO94_GPIO, /* large basic connector pin 14 */
-	GPIO10_GPIO, /* large basic connector pin 23 */
-
-	/* LEDS */
-	GPIO103_GPIO, /* red led */
-	GPIO104_GPIO, /* green led */
-	GPIO105_GPIO, /* blue led */
-};
-
-static struct sht15_platform_data platform_data_sht15 = {
-	.gpio_data =  100,
-	.gpio_sck  =  98,
-};
-
-static struct platform_device sht15 = {
-	.name = "sht15",
-	.id = -1,
-	.dev = {
-		.platform_data = &platform_data_sht15,
-	},
-};
-
-static struct regulator_consumer_supply imote2_sensor_3_con[] = {
-	{
-		.dev = &sht15.dev,
-		.supply = "vcc",
-	},
-};
-
-static struct gpio_led imote2_led_pins[] = {
-	{
-		.name       =  "imote2:red",
-		.gpio       = 103,
-		.active_low = 1,
-	}, {
-		.name       = "imote2:green",
-		.gpio       = 104,
-		.active_low = 1,
-	}, {
-		.name       = "imote2:blue",
-		.gpio       = 105,
-		.active_low = 1,
-	},
-};
-
-static struct gpio_led_platform_data imote2_led_data = {
-	.num_leds = ARRAY_SIZE(imote2_led_pins),
-	.leds     = imote2_led_pins,
-};
-
-static struct platform_device imote2_leds = {
-	.name = "leds-gpio",
-	.id   = -1,
-	.dev = {
-		.platform_data = &imote2_led_data,
-	},
-};
-
-/* Reverse engineered partly from Platformx drivers */
-enum imote2_ldos{
-	vcc_vref,
-	vcc_cc2420,
-	vcc_mica,
-	vcc_bt,
-	/* The two voltages available to sensor boards */
-	vcc_sensor_1_8,
-	vcc_sensor_3,
-
-	vcc_sram_ext, /* directly connected to the pxa271 */
-	vcc_pxa_pll,
-	vcc_pxa_usim, /* Reference voltage for certain gpios */
-	vcc_pxa_mem,
-	vcc_pxa_flash,
-	vcc_pxa_core, /*Dc-Dc buck not yet supported */
-	vcc_lcd,
-	vcc_bb,
-	vcc_bbio,
-	vcc_io, /* cc2420 802.15.4 radio and pxa vcc_io ?*/
-};
-
-/* The values of the various regulator constraints are obviously dependent
- * on exactly what is wired to each ldo.  Unfortunately this information is
- * not generally available.  More information has been requested from Xbow
- * but as of yet they haven't been forthcoming.
- *
- * Some of these are clearly Stargate 2 related (no way of plugging
- * in an lcd on the IM2 for example!).
- */
-static struct regulator_init_data imote2_ldo_init_data[] = {
-	[vcc_bbio] = {
-		.constraints = { /* board default 1.8V */
-			.name = "vcc_bbio",
-			.min_uV = 1800000,
-			.max_uV = 1800000,
-		},
-	},
-	[vcc_bb] = {
-		.constraints = { /* board default 2.8V */
-			.name = "vcc_bb",
-			.min_uV = 2700000,
-			.max_uV = 3000000,
-		},
-	},
-	[vcc_pxa_flash] = {
-		.constraints = {/* default is 1.8V */
-			.name = "vcc_pxa_flash",
-			.min_uV = 1800000,
-			.max_uV = 1800000,
-		},
-	},
-	[vcc_cc2420] = { /* also vcc_io */
-		.constraints = {
-			/* board default is 2.8V */
-			.name = "vcc_cc2420",
-			.min_uV = 2700000,
-			.max_uV = 3300000,
-		},
-	},
-	[vcc_vref] = { /* Reference for what? */
-		.constraints = { /* default 1.8V */
-			.name = "vcc_vref",
-			.min_uV = 1800000,
-			.max_uV = 1800000,
-		},
-	},
-	[vcc_sram_ext] = {
-		.constraints = { /* default 2.8V */
-			.name = "vcc_sram_ext",
-			.min_uV = 2800000,
-			.max_uV = 2800000,
-		},
-	},
-	[vcc_mica] = {
-		.constraints = { /* default 2.8V */
-			.name = "vcc_mica",
-			.min_uV = 2800000,
-			.max_uV = 2800000,
-		},
-	},
-	[vcc_bt] = {
-		.constraints = { /* default 2.8V */
-			.name = "vcc_bt",
-			.min_uV = 2800000,
-			.max_uV = 2800000,
-		},
-	},
-	[vcc_lcd] = {
-		.constraints = { /* default 2.8V */
-			.name = "vcc_lcd",
-			.min_uV = 2700000,
-			.max_uV = 3300000,
-		},
-	},
-	[vcc_io] = { /* Same or higher than everything
-			  * bar vccbat and vccusb */
-		.constraints = { /* default 2.8V */
-			.name = "vcc_io",
-			.min_uV = 2692000,
-			.max_uV = 3300000,
-		},
-	},
-	[vcc_sensor_1_8] = {
-		.constraints = { /* default 1.8V */
-			.name = "vcc_sensor_1_8",
-			.min_uV = 1800000,
-			.max_uV = 1800000,
-		},
-	},
-	[vcc_sensor_3] = { /* curiously default 2.8V */
-		.constraints = {
-			.name = "vcc_sensor_3",
-			.min_uV = 2800000,
-			.max_uV = 3000000,
-		},
-		.num_consumer_supplies = ARRAY_SIZE(imote2_sensor_3_con),
-		.consumer_supplies = imote2_sensor_3_con,
-	},
-	[vcc_pxa_pll] = { /* 1.17V - 1.43V, default 1.3V*/
-		.constraints = {
-			.name = "vcc_pxa_pll",
-			.min_uV = 1170000,
-			.max_uV = 1430000,
-		},
-	},
-	[vcc_pxa_usim] = {
-		.constraints = { /* default 1.8V */
-			.name = "vcc_pxa_usim",
-			.min_uV = 1710000,
-			.max_uV = 2160000,
-		},
-	},
-	[vcc_pxa_mem] = {
-		.constraints = { /* default 1.8V */
-			.name = "vcc_pxa_mem",
-			.min_uV = 1800000,
-			.max_uV = 1800000,
-		},
-	},
-};
-
-static struct da903x_subdev_info imote2_da9030_subdevs[] = {
-	{
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO2,
-		.platform_data = &imote2_ldo_init_data[vcc_bbio],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO3,
-		.platform_data = &imote2_ldo_init_data[vcc_bb],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO4,
-		.platform_data = &imote2_ldo_init_data[vcc_pxa_flash],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO5,
-		.platform_data = &imote2_ldo_init_data[vcc_cc2420],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO6,
-		.platform_data = &imote2_ldo_init_data[vcc_vref],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO7,
-		.platform_data = &imote2_ldo_init_data[vcc_sram_ext],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO8,
-		.platform_data = &imote2_ldo_init_data[vcc_mica],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO9,
-		.platform_data = &imote2_ldo_init_data[vcc_bt],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO10,
-		.platform_data = &imote2_ldo_init_data[vcc_sensor_1_8],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO11,
-		.platform_data = &imote2_ldo_init_data[vcc_sensor_3],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO12,
-		.platform_data = &imote2_ldo_init_data[vcc_lcd],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO15,
-		.platform_data = &imote2_ldo_init_data[vcc_pxa_pll],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO17,
-		.platform_data = &imote2_ldo_init_data[vcc_pxa_usim],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO18,
-		.platform_data = &imote2_ldo_init_data[vcc_io],
-	}, {
-		.name = "da903x-regulator",
-		.id = DA9030_ID_LDO19,
-		.platform_data = &imote2_ldo_init_data[vcc_pxa_mem],
-	},
-};
-
-static struct da903x_platform_data imote2_da9030_pdata = {
-	.num_subdevs = ARRAY_SIZE(imote2_da9030_subdevs),
-	.subdevs = imote2_da9030_subdevs,
-};
-
-/* As the the imote2 doesn't currently have a conventional SD slot
- * there is no option to hotplug cards, making all this rather simple
- */
-static int imote2_mci_get_ro(struct device *dev)
-{
-	return 0;
-}
-
-/* Rather simple case as hotplugging not possible */
-static struct pxamci_platform_data imote2_mci_platform_data = {
-	.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* default anyway */
-	.get_ro = imote2_mci_get_ro,
-	.gpio_card_detect = -1,
-	.gpio_card_ro	= -1,
-	.gpio_power = -1,
-};
-
-static struct mtd_partition imote2flash_partitions[] = {
-	{
-		.name = "Bootloader",
-		.size = 0x00040000,
-		.offset = 0,
-		.mask_flags = MTD_WRITEABLE,
-	}, {
-		.name = "Kernel",
-		.size = 0x00200000,
-		.offset = 0x00040000,
-		.mask_flags = 0,
-	}, {
-		.name = "Filesystem",
-		.size = 0x01DC0000,
-		.offset = 0x00240000,
-		.mask_flags = 0,
-	},
-};
-
-static struct resource flash_resources = {
-	.start = PXA_CS0_PHYS,
-	.end = PXA_CS0_PHYS + SZ_32M - 1,
-	.flags = IORESOURCE_MEM,
-};
-
-static struct flash_platform_data imote2_flash_data = {
-	.map_name = "cfi_probe",
-	.parts = imote2flash_partitions,
-	.nr_parts = ARRAY_SIZE(imote2flash_partitions),
-	.name = "PXA27xOnChipROM",
-	.width = 2,
-};
-
-static struct platform_device imote2_flash_device = {
-	.name = "pxa2xx-flash",
-	.id = 0,
-	.dev = {
-		.platform_data = &imote2_flash_data,
-	},
-	.resource = &flash_resources,
-	.num_resources = 1,
-};
-
-/* Some of the drivers here are out of kernel at the moment (parts of IIO)
- * and it may be a while before they are in the mainline.
- */
-static struct i2c_board_info __initdata imote2_i2c_board_info[] = {
-	{ /* UCAM sensor board */
-		.type = "max1239",
-		.addr = 0x35,
-	}, { /* ITS400 Sensor board only */
-		.type = "max1363",
-		.addr = 0x34,
-		/* Through a nand gate - Also beware, on V2 sensor board the
-		 * pull up resistors are missing.
-		 */
-		.irq = IRQ_GPIO(99),
-	}, { /* ITS400 Sensor board only */
-		.type = "tsl2561",
-		.addr = 0x49,
-		/* Through a nand gate - Also beware, on V2 sensor board the
-		 * pull up resistors are missing.
-		 */
-		.irq = IRQ_GPIO(99),
-	}, { /* ITS400 Sensor board only */
-		.type = "tmp175",
-		.addr = 0x4A,
-		.irq = IRQ_GPIO(96),
-	}, { /* IMB400 Multimedia board */
-		.type = "wm8940",
-		.addr = 0x1A,
-	},
-};
-
-static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = {
-	{
-		.type = "da9030",
-		.addr = 0x49,
-		.platform_data = &imote2_da9030_pdata,
-		.irq = gpio_to_irq(1),
-	},
-};
-
-static struct pxa2xx_spi_master pxa_ssp_master_0_info = {
-	.num_chipselect = 1,
-};
-
-static struct pxa2xx_spi_master pxa_ssp_master_1_info = {
-	.num_chipselect = 1,
-};
-
-static struct pxa2xx_spi_master pxa_ssp_master_2_info = {
-	.num_chipselect = 1,
-};
-
-static struct pxa2xx_spi_chip staccel_chip_info = {
-	.tx_threshold = 8,
-	.rx_threshold = 8,
-	.dma_burst_size = 8,
-	.timeout = 235,
-	.gpio_cs = 24,
-};
-
-static struct pxa2xx_spi_chip cc2420_info = {
-	.tx_threshold = 8,
-	.rx_threshold = 8,
-	.dma_burst_size = 8,
-	.timeout = 235,
-	.gpio_cs = 39,
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
-	{ /* Driver in IIO */
-		.modalias = "lis3l02dq",
-		.max_speed_hz = 8000000,/* 8MHz max spi frequency at 3V */
-		.bus_num = 1,
-		.chip_select = 0,
-		.controller_data = &staccel_chip_info,
-		.irq = IRQ_GPIO(96),
-	}, { /* Driver out of kernel as it needs considerable rewriting */
-		.modalias = "cc2420",
-		.max_speed_hz = 6500000,
-		.bus_num = 3,
-		.chip_select = 0,
-		.controller_data = &cc2420_info,
-	},
-};
-
-static void im2_udc_command(int cmd)
-{
-	switch (cmd) {
-	case PXA2XX_UDC_CMD_CONNECT:
-		UP2OCR |=  UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE;
-		break;
-	case PXA2XX_UDC_CMD_DISCONNECT:
-		UP2OCR &= ~(UP2OCR_HXOE | UP2OCR_DPPUE | UP2OCR_DPPUBE);
-		break;
-	}
-}
-
-static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = {
-	.udc_command		= im2_udc_command,
-};
-
-static struct platform_device *imote2_devices[] = {
-	&imote2_flash_device,
-	&imote2_leds,
-	&sht15,
-};
-
-static struct i2c_pxa_platform_data i2c_pwr_pdata = {
-	.fast_mode = 1,
-};
-
-static struct i2c_pxa_platform_data i2c_pdata = {
-	.fast_mode = 1,
-};
-
-static void __init imote2_init(void)
-{
-	pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config));
-
-	pxa_set_ffuart_info(NULL);
-	pxa_set_btuart_info(NULL);
-	pxa_set_stuart_info(NULL);
-
-	platform_add_devices(imote2_devices, ARRAY_SIZE(imote2_devices));
-
-	pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info);
-	pxa2xx_set_spi_info(2, &pxa_ssp_master_1_info);
-	pxa2xx_set_spi_info(3, &pxa_ssp_master_2_info);
-
-	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-
-	i2c_register_board_info(0, imote2_i2c_board_info,
-				ARRAY_SIZE(imote2_i2c_board_info));
-	i2c_register_board_info(1, imote2_pwr_i2c_board_info,
-				ARRAY_SIZE(imote2_pwr_i2c_board_info));
-
-	pxa27x_set_i2c_power_info(&i2c_pwr_pdata);
-	pxa_set_i2c_info(&i2c_pdata);
-
-	pxa_set_mci_info(&imote2_mci_platform_data);
-	pxa_set_udc_info(&imote2_udc_info);
-}
-
-MACHINE_START(INTELMOTE2, "IMOTE 2")
-	.phys_io	= 0x40000000,
-	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.map_io		= pxa_map_io,
-	.init_irq	= pxa27x_init_irq,
-	.timer		= &pxa_timer,
-	.init_machine	= imote2_init,
-	.boot_params	= 0xA0000100,
-MACHINE_END
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index af40d2a..a654d1e 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -29,6 +29,7 @@
 #include <linux/i2c/at24.h>
 #include <linux/smc91x.h>
 #include <linux/gpio.h>
+#include <linux/leds.h>
 
 #include <asm/types.h>
 #include <asm/setup.h>
@@ -62,37 +63,12 @@
 #define SG2_GPIO_nSD_DETECT	90
 #define SG2_SD_POWER_ENABLE	89
 
-static unsigned long stargate2_pin_config[] __initdata = {
-
-	GPIO15_nCS_1, /* SRAM */
-	/* SMC91x */
-	GPIO80_nCS_4,
-	GPIO40_GPIO, /*cable detect?*/
+static unsigned long sg2_im2_unified_pin_config[] __initdata = {
 	/* Device Identification for wakeup*/
 	GPIO102_GPIO,
-
-	/* Button */
-	GPIO91_GPIO | WAKEUP_ON_LEVEL_HIGH,
-
 	/* DA9030 */
 	GPIO1_GPIO,
 
-	/* Compact Flash */
-	GPIO79_PSKTSEL,
-	GPIO48_nPOE,
-	GPIO49_nPWE,
-	GPIO50_nPIOR,
-	GPIO51_nPIOW,
-	GPIO85_nPCE_1,
-	GPIO54_nPCE_2,
-	GPIO55_nPREG,
-	GPIO56_nPWAIT,
-	GPIO57_nIOIS16,
-	GPIO120_GPIO, /* Buff ctrl */
-	GPIO108_GPIO, /* Power ctrl */
-	GPIO82_GPIO, /* Reset */
-	GPIO53_GPIO, /* SG2_S0_GPIO_DETECT */
-
 	/* MMC */
 	GPIO32_MMC_CLK,
 	GPIO112_MMC_CMD,
@@ -100,49 +76,44 @@ static unsigned long stargate2_pin_config[] __initdata = {
 	GPIO109_MMC_DAT_1,
 	GPIO110_MMC_DAT_2,
 	GPIO111_MMC_DAT_3,
-	GPIO90_GPIO, /* nSD detect */
-	GPIO89_GPIO, /* SD_POWER_ENABLE */
 
-	/* Bluetooth */
-	GPIO81_GPIO, /* reset */
-
-	/* cc2420 802.15.4 radio */
-	GPIO22_GPIO,		/* CC_RSTN  (out)*/
-	GPIO114_GPIO,		/* CC_FIFO (in) */
-	GPIO116_GPIO, 		/* CC_CCA (in) */
-	GPIO0_GPIO,		/* CC_FIFOP (in) */
-	GPIO16_GPIO,		/* CCSFD (in) */
-	GPIO39_GPIO,		/* CSn (out) */
+	/* 802.15.4 radio - driver out of mainline */
+	GPIO22_GPIO,			/* CC_RSTN */
+	GPIO114_GPIO,			/* CC_FIFO */
+	GPIO116_GPIO,			/* CC_CCA */
+	GPIO0_GPIO,			/* CC_FIFOP */
+	GPIO16_GPIO,			/* CCSFD */
+	GPIO115_GPIO,			/* Power enable */
 
 	/* I2C */
 	GPIO117_I2C_SCL,
 	GPIO118_I2C_SDA,
 
 	/* SSP 3 - 802.15.4 radio */
-	GPIO39_GPIO, /* chip select */
+	GPIO39_GPIO,			/* Chip Select */
 	GPIO34_SSP3_SCLK,
 	GPIO35_SSP3_TXD,
 	GPIO41_SSP3_RXD,
 
-	/* SSP 2 */
+	/* SSP 2 to daughter boards */
 	GPIO11_SSP2_RXD,
 	GPIO38_SSP2_TXD,
 	GPIO36_SSP2_SCLK,
 	GPIO37_GPIO, /* chip select */
 
-	/* SSP 1 */
-	GPIO26_SSP1_RXD,
-	GPIO25_SSP1_TXD,
+	/* SSP 1 - to daughter boards */
+	GPIO24_GPIO,			/* Chip Select */
 	GPIO23_SSP1_SCLK,
-	GPIO24_GPIO, /* chip select */
+	GPIO25_SSP1_TXD,
+	GPIO26_SSP1_RXD,
 
-	/* BTUART */
+	/* BTUART Basic Connector*/
 	GPIO42_BTUART_RXD,
 	GPIO43_BTUART_TXD,
 	GPIO44_BTUART_CTS,
 	GPIO45_BTUART_RTS,
 
-	/* STUART */
+	/* STUART  - IM2 via debug board not sure on SG2*/
 	GPIO46_STUART_RXD,
 	GPIO47_STUART_TXD,
 
@@ -150,47 +121,17 @@ static unsigned long stargate2_pin_config[] __initdata = {
 	GPIO96_GPIO,	/* accelerometer interrupt */
 	GPIO99_GPIO,	/* ADC interrupt */
 
-	/* Connector pins specified as gpios */
-	GPIO94_GPIO, /* large basic connector pin 14 */
-	GPIO10_GPIO, /* large basic connector pin 23 */
-
 	/* SHT15 */
 	GPIO100_GPIO,
 	GPIO98_GPIO,
-};
 
-/**
- * stargate2_reset_bluetooth() reset the bluecore to ensure consistent state
- **/
-static int stargate2_reset_bluetooth(void)
-{
-	int err;
-	err = gpio_request(SG2_BT_RESET, "SG2_BT_RESET");
-	if (err) {
-		printk(KERN_ERR "Could not get gpio for bluetooth reset \n");
-		return err;
-	}
-	gpio_direction_output(SG2_BT_RESET, 1);
-	mdelay(5);
-	/* now reset it - 5 msec minimum */
-	gpio_set_value(SG2_BT_RESET, 0);
-	mdelay(10);
-	gpio_set_value(SG2_BT_RESET, 1);
-	gpio_free(SG2_BT_RESET);
-	return 0;
-}
+	/* Basic sensor board */
+	GPIO96_GPIO,	/* accelerometer interrupt */
+	GPIO99_GPIO,	/* ADC interrupt */
 
-static struct led_info stargate2_leds[] = {
-	{
-		.name = "sg2:red",
-		.flags = DA9030_LED_RATE_ON,
-	}, {
-		.name = "sg2:blue",
-		.flags = DA9030_LED_RATE_ON,
-	}, {
-		.name = "sg2:green",
-		.flags = DA9030_LED_RATE_ON,
-	},
+	/* Connector pins specified as gpios */
+	GPIO94_GPIO, /* large basic connector pin 14 */
+	GPIO10_GPIO, /* large basic connector pin 23 */
 };
 
 static struct sht15_platform_data platform_data_sht15 = {
@@ -352,20 +293,184 @@ static struct regulator_init_data stargate2_ldo_init_data[] = {
 	},
 };
 
-static struct da903x_subdev_info stargate2_da9030_subdevs[] = {
+static struct mtd_partition stargate2flash_partitions[] = {
 	{
-		.name = "da903x-led",
-		.id = DA9030_ID_LED_2,
-		.platform_data = &stargate2_leds[0],
+		.name = "Bootloader",
+		.size = 0x00040000,
+		.offset = 0,
+		.mask_flags = 0,
 	}, {
-		.name = "da903x-led",
-		.id = DA9030_ID_LED_3,
-		.platform_data = &stargate2_leds[2],
+		.name = "Kernel",
+		.size = 0x00200000,
+		.offset = 0x00040000,
+		.mask_flags = 0
 	}, {
-		.name = "da903x-led",
-		.id = DA9030_ID_LED_4,
-		.platform_data = &stargate2_leds[1],
+		.name = "Filesystem",
+		.size = 0x01DC0000,
+		.offset = 0x00240000,
+		.mask_flags = 0
+	},
+};
+
+static struct resource flash_resources = {
+	.start = PXA_CS0_PHYS,
+	.end = PXA_CS0_PHYS + SZ_32M - 1,
+	.flags = IORESOURCE_MEM,
+};
+
+static struct flash_platform_data stargate2_flash_data = {
+	.map_name = "cfi_probe",
+	.parts = stargate2flash_partitions,
+	.nr_parts = ARRAY_SIZE(stargate2flash_partitions),
+	.name = "PXA27xOnChipROM",
+	.width = 2,
+};
+
+static struct platform_device stargate2_flash_device = {
+	.name = "pxa2xx-flash",
+	.id = 0,
+	.dev = {
+		.platform_data = &stargate2_flash_data,
+	},
+	.resource = &flash_resources,
+	.num_resources = 1,
+};
+
+static struct pxa2xx_spi_master pxa_ssp_master_0_info = {
+	.num_chipselect = 1,
+};
+
+static struct pxa2xx_spi_master pxa_ssp_master_1_info = {
+	.num_chipselect = 1,
+};
+
+static struct pxa2xx_spi_master pxa_ssp_master_2_info = {
+	.num_chipselect = 1,
+};
+
+/* An upcoming kernel change will scrap SFRM usage so these
+ * drivers have been moved to use gpio's via cs_control */
+static struct pxa2xx_spi_chip staccel_chip_info = {
+	.tx_threshold = 8,
+	.rx_threshold = 8,
+	.dma_burst_size = 8,
+	.timeout = 235,
+	.gpio_cs = 24,
+};
+
+static struct pxa2xx_spi_chip cc2420_info = {
+	.tx_threshold = 8,
+	.rx_threshold = 8,
+	.dma_burst_size = 8,
+	.timeout = 235,
+	.gpio_cs = 39,
+};
+
+static struct spi_board_info spi_board_info[] __initdata = {
+	{
+		.modalias = "lis3l02dq",
+		.max_speed_hz = 8000000,/* 8MHz max spi frequency at 3V */
+		.bus_num = 1,
+		.chip_select = 0,
+		.controller_data = &staccel_chip_info,
+		.irq = IRQ_GPIO(96),
 	}, {
+		.modalias = "cc2420",
+		.max_speed_hz = 6500000,
+		.bus_num = 3,
+		.chip_select = 0,
+		.controller_data = &cc2420_info,
+	},
+};
+
+static void sg2_udc_command(int cmd)
+{
+	switch (cmd) {
+	case PXA2XX_UDC_CMD_CONNECT:
+		UP2OCR |=  UP2OCR_HXOE  | UP2OCR_DPPUE | UP2OCR_DPPUBE;
+		break;
+	case PXA2XX_UDC_CMD_DISCONNECT:
+		UP2OCR &= ~(UP2OCR_HXOE  | UP2OCR_DPPUE | UP2OCR_DPPUBE);
+		break;
+	}
+}
+
+static struct i2c_pxa_platform_data i2c_pwr_pdata = {
+	.fast_mode = 1,
+};
+
+static struct i2c_pxa_platform_data i2c_pdata = {
+	.fast_mode = 1,
+};
+
+static void __init imote2_stargate2_init(void)
+{
+
+	pxa2xx_mfp_config(ARRAY_AND_SIZE(sg2_im2_unified_pin_config));
+
+	pxa_set_ffuart_info(NULL);
+	pxa_set_btuart_info(NULL);
+	pxa_set_stuart_info(NULL);
+
+	pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info);
+	pxa2xx_set_spi_info(2, &pxa_ssp_master_1_info);
+	pxa2xx_set_spi_info(3, &pxa_ssp_master_2_info);
+	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+
+
+	pxa27x_set_i2c_power_info(&i2c_pwr_pdata);
+	pxa_set_i2c_info(&i2c_pdata);
+}
+
+#ifdef CONFIG_MACH_INTELMOTE2
+/* As the the imote2 doesn't currently have a conventional SD slot
+ * there is no option to hotplug cards, making all this rather simple
+ */
+static int imote2_mci_get_ro(struct device *dev)
+{
+	return 0;
+}
+
+/* Rather simple case as hotplugging not possible */
+static struct pxamci_platform_data imote2_mci_platform_data = {
+	.ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, /* default anyway */
+	.get_ro = imote2_mci_get_ro,
+	.gpio_card_detect = -1,
+	.gpio_card_ro	= -1,
+	.gpio_power = -1,
+};
+
+static struct gpio_led imote2_led_pins[] = {
+	{
+		.name       =  "imote2:red",
+		.gpio       = 103,
+		.active_low = 1,
+	}, {
+		.name       = "imote2:green",
+		.gpio       = 104,
+		.active_low = 1,
+	}, {
+		.name       = "imote2:blue",
+		.gpio       = 105,
+		.active_low = 1,
+	},
+};
+
+static struct gpio_led_platform_data imote2_led_data = {
+	.num_leds = ARRAY_SIZE(imote2_led_pins),
+	.leds     = imote2_led_pins,
+};
+
+static struct platform_device imote2_leds = {
+	.name = "leds-gpio",
+	.id   = -1,
+	.dev = {
+		.platform_data = &imote2_led_data,
+	},
+};
+
+static struct da903x_subdev_info imote2_da9030_subdevs[] = {
+	{
 		.name = "da903x-regulator",
 		.id = DA9030_ID_LDO2,
 		.platform_data = &stargate2_ldo_init_data[vcc_bbio],
@@ -428,9 +533,121 @@ static struct da903x_subdev_info stargate2_da9030_subdevs[] = {
 	},
 };
 
-static struct da903x_platform_data stargate2_da9030_pdata = {
-	.num_subdevs = ARRAY_SIZE(stargate2_da9030_subdevs),
-	.subdevs = stargate2_da9030_subdevs,
+static struct da903x_platform_data imote2_da9030_pdata = {
+	.num_subdevs = ARRAY_SIZE(imote2_da9030_subdevs),
+	.subdevs = imote2_da9030_subdevs,
+};
+
+static struct i2c_board_info __initdata imote2_pwr_i2c_board_info[] = {
+	{
+		.type = "da9030",
+		.addr = 0x49,
+		.platform_data = &imote2_da9030_pdata,
+		.irq = gpio_to_irq(1),
+	},
+};
+
+static struct i2c_board_info __initdata imote2_i2c_board_info[] = {
+	{ /* UCAM sensor board */
+		.type = "max1239",
+		.addr = 0x35,
+	}, { /* ITS400 Sensor board only */
+		.type = "max1363",
+		.addr = 0x34,
+		/* Through a nand gate - Also beware, on V2 sensor board the
+		 * pull up resistors are missing.
+		 */
+		.irq = IRQ_GPIO(99),
+	}, { /* ITS400 Sensor board only */
+		.type = "tsl2561",
+		.addr = 0x49,
+		/* Through a nand gate - Also beware, on V2 sensor board the
+		 * pull up resistors are missing.
+		 */
+		.irq = IRQ_GPIO(99),
+	}, { /* ITS400 Sensor board only */
+		.type = "tmp175",
+		.addr = 0x4A,
+		.irq = IRQ_GPIO(96),
+	}, { /* IMB400 Multimedia board */
+		.type = "wm8940",
+		.addr = 0x1A,
+	},
+};
+
+static unsigned long imote2_pin_config[] __initdata = {
+
+	/* Button */
+	GPIO91_GPIO,
+
+	/* LEDS */
+	GPIO103_GPIO, /* red led */
+	GPIO104_GPIO, /* green led */
+	GPIO105_GPIO, /* blue led */
+};
+
+static struct pxa2xx_udc_mach_info imote2_udc_info __initdata = {
+	.udc_command		= sg2_udc_command,
+};
+
+static struct platform_device *imote2_devices[] = {
+	&stargate2_flash_device,
+	&imote2_leds,
+	&sht15,
+};
+
+static void __init imote2_init(void)
+{
+	pxa2xx_mfp_config(ARRAY_AND_SIZE(imote2_pin_config));
+
+	imote2_stargate2_init();
+
+	platform_add_devices(imote2_devices, ARRAY_SIZE(imote2_devices));
+
+	i2c_register_board_info(0, imote2_i2c_board_info,
+				ARRAY_SIZE(imote2_i2c_board_info));
+	i2c_register_board_info(1, imote2_pwr_i2c_board_info,
+				ARRAY_SIZE(imote2_pwr_i2c_board_info));
+
+	pxa_set_mci_info(&imote2_mci_platform_data);
+	pxa_set_udc_info(&imote2_udc_info);
+}
+#endif
+
+#ifdef CONFIG_MACH_STARGATE2
+
+static unsigned long stargate2_pin_config[] __initdata = {
+
+	GPIO15_nCS_1, /* SRAM */
+	/* SMC91x */
+	GPIO80_nCS_4,
+	GPIO40_GPIO, /*cable detect?*/
+
+	/* Button */
+	GPIO91_GPIO | WAKEUP_ON_LEVEL_HIGH,
+
+	/* Compact Flash */
+	GPIO79_PSKTSEL,
+	GPIO48_nPOE,
+	GPIO49_nPWE,
+	GPIO50_nPIOR,
+	GPIO51_nPIOW,
+	GPIO85_nPCE_1,
+	GPIO54_nPCE_2,
+	GPIO55_nPREG,
+	GPIO56_nPWAIT,
+	GPIO57_nIOIS16,
+	GPIO120_GPIO, /* Buff ctrl */
+	GPIO108_GPIO, /* Power ctrl */
+	GPIO82_GPIO, /* Reset */
+	GPIO53_GPIO, /* SG2_S0_GPIO_DETECT */
+
+	/* MMC not shared with imote2 */
+	GPIO90_GPIO, /* nSD detect */
+	GPIO89_GPIO, /* SD_POWER_ENABLE */
+
+	/* Bluetooth */
+	GPIO81_GPIO, /* reset */
 };
 
 static struct resource smc91x_resources[] = {
@@ -463,7 +680,6 @@ static struct platform_device smc91x_device = {
 };
 
 
-
 /*
  * The card detect interrupt isn't debounced so we delay it by 250ms
  * to give the card a chance to fully insert / eject.
@@ -532,48 +748,6 @@ static struct pxamci_platform_data stargate2_mci_platform_data = {
 	.exit = stargate2_mci_exit,
 };
 
-static struct mtd_partition stargate2flash_partitions[] = {
-	{
-		.name = "Bootloader",
-		.size = 0x00040000,
-		.offset = 0,
-		.mask_flags = 0,
-	}, {
-		.name = "Kernel",
-		.size = 0x00200000,
-		.offset = 0x00040000,
-		.mask_flags = 0
-	}, {
-		.name = "Filesystem",
-		.size = 0x01DC0000,
-		.offset = 0x00240000,
-		.mask_flags = 0
-	},
-};
-
-static struct resource flash_resources = {
-	.start = PXA_CS0_PHYS,
-	.end = PXA_CS0_PHYS + SZ_32M - 1,
-	.flags = IORESOURCE_MEM,
-};
-
-static struct flash_platform_data stargate2_flash_data = {
-	.map_name = "cfi_probe",
-	.parts = stargate2flash_partitions,
-	.nr_parts = ARRAY_SIZE(stargate2flash_partitions),
-	.name = "PXA27xOnChipROM",
-	.width = 2,
-};
-
-static struct platform_device stargate2_flash_device = {
-	.name = "pxa2xx-flash",
-	.id = 0,
-	.dev = {
-		.platform_data = &stargate2_flash_data,
-	},
-	.resource = &flash_resources,
-	.num_resources = 1,
-};
 
 /*
  * SRAM - The Stargate 2 has 32MB of SRAM.
@@ -616,6 +790,129 @@ static struct at24_platform_data pca9500_eeprom_pdata = {
 	.page_size = 4,
 };
 
+/**
+ * stargate2_reset_bluetooth() reset the bluecore to ensure consistent state
+ **/
+static int stargate2_reset_bluetooth(void)
+{
+	int err;
+	err = gpio_request(SG2_BT_RESET, "SG2_BT_RESET");
+	if (err) {
+		printk(KERN_ERR "Could not get gpio for bluetooth reset\n");
+		return err;
+	}
+	gpio_direction_output(SG2_BT_RESET, 1);
+	mdelay(5);
+	/* now reset it - 5 msec minimum */
+	gpio_set_value(SG2_BT_RESET, 0);
+	mdelay(10);
+	gpio_set_value(SG2_BT_RESET, 1);
+	gpio_free(SG2_BT_RESET);
+	return 0;
+}
+
+static struct led_info stargate2_leds[] = {
+	{
+		.name = "sg2:red",
+		.flags = DA9030_LED_RATE_ON,
+	}, {
+		.name = "sg2:blue",
+		.flags = DA9030_LED_RATE_ON,
+	}, {
+		.name = "sg2:green",
+		.flags = DA9030_LED_RATE_ON,
+	},
+};
+
+static struct da903x_subdev_info stargate2_da9030_subdevs[] = {
+	{
+		.name = "da903x-led",
+		.id = DA9030_ID_LED_2,
+		.platform_data = &stargate2_leds[0],
+	}, {
+		.name = "da903x-led",
+		.id = DA9030_ID_LED_3,
+		.platform_data = &stargate2_leds[2],
+	}, {
+		.name = "da903x-led",
+		.id = DA9030_ID_LED_4,
+		.platform_data = &stargate2_leds[1],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO2,
+		.platform_data = &stargate2_ldo_init_data[vcc_bbio],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO3,
+		.platform_data = &stargate2_ldo_init_data[vcc_bb],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO4,
+		.platform_data = &stargate2_ldo_init_data[vcc_pxa_flash],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO5,
+		.platform_data = &stargate2_ldo_init_data[vcc_cc2420],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO6,
+		.platform_data = &stargate2_ldo_init_data[vcc_vref],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO7,
+		.platform_data = &stargate2_ldo_init_data[vcc_sram_ext],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO8,
+		.platform_data = &stargate2_ldo_init_data[vcc_mica],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO9,
+		.platform_data = &stargate2_ldo_init_data[vcc_bt],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO10,
+		.platform_data = &stargate2_ldo_init_data[vcc_sensor_1_8],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO11,
+		.platform_data = &stargate2_ldo_init_data[vcc_sensor_3],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO12,
+		.platform_data = &stargate2_ldo_init_data[vcc_lcd],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO15,
+		.platform_data = &stargate2_ldo_init_data[vcc_pxa_pll],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO17,
+		.platform_data = &stargate2_ldo_init_data[vcc_pxa_usim],
+	}, {
+		.name = "da903x-regulator", /*pxa vcc i/o and cc2420 vcc i/o */
+		.id = DA9030_ID_LDO18,
+		.platform_data = &stargate2_ldo_init_data[vcc_io],
+	}, {
+		.name = "da903x-regulator",
+		.id = DA9030_ID_LDO19,
+		.platform_data = &stargate2_ldo_init_data[vcc_pxa_mem],
+	},
+};
+
+static struct da903x_platform_data stargate2_da9030_pdata = {
+	.num_subdevs = ARRAY_SIZE(stargate2_da9030_subdevs),
+	.subdevs = stargate2_da9030_subdevs,
+};
+
+static struct i2c_board_info __initdata stargate2_pwr_i2c_board_info[] = {
+	{
+		.type = "da9030",
+		.addr = 0x49,
+		.platform_data = &stargate2_da9030_pdata,
+		.irq = gpio_to_irq(1),
+	},
+};
 
 static struct i2c_board_info __initdata stargate2_i2c_board_info[] = {
 	/* Techically this a pca9500 - but it's compatible with the 8574
@@ -653,74 +950,6 @@ static struct i2c_board_info __initdata stargate2_i2c_board_info[] = {
 	},
 };
 
-static struct i2c_board_info __initdata stargate2_pwr_i2c_board_info[] = {
-	{
-		.type = "da9030",
-		.addr = 0x49,
-		.platform_data = &stargate2_da9030_pdata,
-		.irq = gpio_to_irq(1),
-	},
-};
-
-static struct pxa2xx_spi_master pxa_ssp_master_0_info = {
-	.num_chipselect = 1,
-};
-
-static struct pxa2xx_spi_master pxa_ssp_master_1_info = {
-	.num_chipselect = 1,
-};
-
-static struct pxa2xx_spi_master pxa_ssp_master_2_info = {
-	.num_chipselect = 1,
-};
-
-/* An upcoming kernel change will scrap SFRM usage so these
- * drivers have been moved to use gpio's via cs_control */
-static struct pxa2xx_spi_chip staccel_chip_info = {
-	.tx_threshold = 8,
-	.rx_threshold = 8,
-	.dma_burst_size = 8,
-	.timeout = 235,
-	.gpio_cs = 24,
-};
-
-static struct pxa2xx_spi_chip cc2420_info = {
-	.tx_threshold = 8,
-	.rx_threshold = 8,
-	.dma_burst_size = 8,
-	.timeout = 235,
-	.gpio_cs = 39,
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
-	{
-		.modalias = "lis3l02dq",
-		.max_speed_hz = 8000000,/* 8MHz max spi frequency at 3V */
-		.bus_num = 1,
-		.chip_select = 0,
-		.controller_data = &staccel_chip_info,
-		.irq = IRQ_GPIO(96),
-	}, {
-		.modalias = "cc2420",
-		.max_speed_hz = 6500000,
-		.bus_num = 3,
-		.chip_select = 0,
-		.controller_data = &cc2420_info,
-	},
-};
-
-static void sg2_udc_command(int cmd)
-{
-	switch (cmd) {
-	case PXA2XX_UDC_CMD_CONNECT:
-		UP2OCR |=  UP2OCR_HXOE  | UP2OCR_DPPUE | UP2OCR_DPPUBE;
-		break;
-	case PXA2XX_UDC_CMD_DISCONNECT:
-		UP2OCR &= ~(UP2OCR_HXOE  | UP2OCR_DPPUE | UP2OCR_DPPUBE);
-		break;
-	}
-}
-
 /* Board doesn't support cable detection - so always lie and say
  * something is there.
  */
@@ -741,14 +970,6 @@ static struct platform_device *stargate2_devices[] = {
 	&sht15,
 };
 
-static struct i2c_pxa_platform_data i2c_pwr_pdata = {
-	.fast_mode = 1,
-};
-
-static struct i2c_pxa_platform_data i2c_pdata = {
-	.fast_mode = 1,
-};
-
 static void __init stargate2_init(void)
 {
 	/* This is probably a board specific hack as this must be set
@@ -757,22 +978,13 @@ static void __init stargate2_init(void)
 
 	pxa2xx_mfp_config(ARRAY_AND_SIZE(stargate2_pin_config));
 
-	pxa_set_ffuart_info(NULL);
-	pxa_set_btuart_info(NULL);
-	pxa_set_stuart_info(NULL);
+	imote2_stargate2_init();
 
 	platform_add_devices(ARRAY_AND_SIZE(stargate2_devices));
 
-	pxa2xx_set_spi_info(1, &pxa_ssp_master_0_info);
-	pxa2xx_set_spi_info(2, &pxa_ssp_master_1_info);
-	pxa2xx_set_spi_info(3, &pxa_ssp_master_2_info);
-	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-
 	i2c_register_board_info(0, ARRAY_AND_SIZE(stargate2_i2c_board_info));
-	i2c_register_board_info(1,
-				ARRAY_AND_SIZE(stargate2_pwr_i2c_board_info));
-	pxa27x_set_i2c_power_info(&i2c_pwr_pdata);
-	pxa_set_i2c_info(&i2c_pdata);
+	i2c_register_board_info(1, stargate2_pwr_i2c_board_info,
+				ARRAY_SIZE(stargate2_pwr_i2c_board_info));
 
 	pxa_set_mci_info(&stargate2_mci_platform_data);
 
@@ -780,7 +992,21 @@ static void __init stargate2_init(void)
 
 	stargate2_reset_bluetooth();
 }
+#endif
+
+#ifdef CONFIG_MACH_INTELMOTE2
+MACHINE_START(INTELMOTE2, "IMOTE 2")
+	.phys_io	= 0x40000000,
+	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
+	.map_io		= pxa_map_io,
+	.init_irq	= pxa27x_init_irq,
+	.timer		= &pxa_timer,
+	.init_machine	= imote2_init,
+	.boot_params	= 0xA0000100,
+MACHINE_END
+#endif
 
+#ifdef CONFIG_MACH_STARGATE2
 MACHINE_START(STARGATE2, "Stargate 2")
 	.phys_io = 0x40000000,
 	.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
@@ -790,3 +1016,4 @@ MACHINE_START(STARGATE2, "Stargate 2")
 	.init_machine = stargate2_init,
 	.boot_params = 0xA0000100,
 MACHINE_END
+#endif
-- 
1.7.0.4



From marek.vasut at gmail.com  Sun Jun  6 12:34:50 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sun, 6 Jun 2010 18:34:50 +0200
Subject: pxa300 - DDRAM base value
In-Reply-To: <AANLkTil5TWYILcdp872as8S8LMqQWhPYWLt7cxs2lUm5@mail.gmail.com>
References: <1275371058.7001.35.camel@balakrishnan-desktop>
	<201006051919.17738.marek.vasut@gmail.com>
	<AANLkTil5TWYILcdp872as8S8LMqQWhPYWLt7cxs2lUm5@mail.gmail.com>
Message-ID: <201006061834.50297.marek.vasut@gmail.com>

Dne Ne 6. ?ervna 2010 10:17:00 Eric Miao napsal(a):
> On Sun, Jun 6, 2010 at 1:19 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > Dne ?t 1. ?ervna 2010 07:44:18 balakrishnan napsal(a):
> >> I am working on pxa300 based development board and using Linux 2.6.34.
> >> This Linux kernel already has support for following boards
> >> 1. zylonite_pxa300
> >> 2. cm-x300
> >> 3. colibri-pxa300
> >> 4. littleton
> >> 
> >> My doubt is that pxa300 based boards are using "0xa0000000"  as DDRAM
> >> base and PHYS_OFFSET is also defined in
> >> "arch/arm/mach-pxa/include/mach/memory.h" as 0xa0000000.
> >> But in our board  DDR is mapped in 0x80000000. Does it make any
> >> problem?. Because after mmu is turned ON, my board is hanging.
> >> 
> >> "zreladdr-y   := 0x80008000" is defined in
> >> "arch/arm/mach-pxa/Makefile.boot" file .
> >> my machine_desc is as follows
> >> .phys_io        = 0x40000000,
> >> .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
> >> .boot_params    = 0x80000100,
> > 
> > Try editing both arch/arm/mach-pxa/Makefile.boot and
> > arch/arm/mach/pxa/include/mach/memory.h
> > 
> >> With Thanks
> >> J.Balakrishnan
> > 
> > The 0x80000000 should be aliased to 0xa0000000, but looking into the PXA
> > docs, it is only on pxa320. Eric, any ideas on this ?
> 
> Should be working on pxa300/310 as well. If it doesn't, check you
> bootloader to make sure the mapping is OK, and memory doesn't exceed
> (0xa000_0000 - 0x8000_0000).

It worked last time I used the pxa310 littleton board, but I can't check on the 
pxa300 zylonite board just yet.

Could you give us your bootloader details ?


From mike.rapoport at gmail.com  Sun Jun  6 13:03:32 2010
From: mike.rapoport at gmail.com (Mike Rapoport)
Date: Sun, 6 Jun 2010 20:03:32 +0300
Subject: pxa300 - DDRAM base value
In-Reply-To: <AANLkTil5TWYILcdp872as8S8LMqQWhPYWLt7cxs2lUm5@mail.gmail.com>
References: <1275371058.7001.35.camel@balakrishnan-desktop>
	<201006051919.17738.marek.vasut@gmail.com>
	<AANLkTil5TWYILcdp872as8S8LMqQWhPYWLt7cxs2lUm5@mail.gmail.com>
Message-ID: <AANLkTikMTZ8bl_B0kvowJmtKyRrPbF7Qds3YMeVCWw7E@mail.gmail.com>

On Sun, Jun 6, 2010 at 11:17 AM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Sun, Jun 6, 2010 at 1:19 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
>> Dne ?t 1. ?ervna 2010 07:44:18 balakrishnan napsal(a):
>>> I am working on pxa300 based development board and using Linux 2.6.34.
>>> This Linux kernel already has support for following boards
>>> 1. zylonite_pxa300
>>> 2. cm-x300
>>> 3. colibri-pxa300
>>> 4. littleton
>>>
>>> My doubt is that pxa300 based boards are using "0xa0000000" ?as DDRAM
>>> base and PHYS_OFFSET is also defined in
>>> "arch/arm/mach-pxa/include/mach/memory.h" as 0xa0000000.
>>> But in our board ?DDR is mapped in 0x80000000. Does it make any
>>> problem?. Because after mmu is turned ON, my board is hanging.
>>>
>>> "zreladdr-y ? := 0x80008000" is defined in
>>> "arch/arm/mach-pxa/Makefile.boot" file .
>>> my machine_desc is as follows
>>> .phys_io ? ? ? ?= 0x40000000,
>>> .io_pg_offst ? ?= (io_p2v(0x40000000) >> 18) & 0xfffc,
>>> .boot_params ? ?= 0x80000100,
>>>
>>
>> Try editing both arch/arm/mach-pxa/Makefile.boot and
>> arch/arm/mach/pxa/include/mach/memory.h
>>
>>> With Thanks
>>> J.Balakrishnan
>>
>> The 0x80000000 should be aliased to 0xa0000000, but looking into the PXA docs,
>> it is only on pxa320. Eric, any ideas on this ?
>>
>
> Should be working on pxa300/310 as well. If it doesn't, check you bootloader
> to make sure the mapping is OK, and memory doesn't exceed
> (0xa000_0000 - 0x8000_0000).

works on CM-X300 with both pxa300 and pxa310

> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at ?http://www.tux.org/lkml/
>



-- 
	Sincerely Yours,
		Mike.


From robert.jarzmik at free.fr  Sun Jun  6 13:46:37 2010
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Sun, 06 Jun 2010 19:46:37 +0200
Subject: [PATCH 2/3] pxa: Fix all devices using wm97xx_batt.h
In-Reply-To: <1275613654-23918-2-git-send-email-marek.vasut@gmail.com> (Marek
	Vasut's message of "Fri\, 4 Jun 2010 03\:07\:33 +0200")
References: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>
	<1275613654-23918-2-git-send-email-marek.vasut@gmail.com>
Message-ID: <87pr04oxz6.fsf@free.fr>

Marek Vasut <marek.vasut at gmail.com> writes:

> This file is scheduled for removal, therefore fix all devices that use this
> file to use the suggested wm97xx.h and pass platform data properly.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> ---
>  arch/arm/mach-pxa/mioa701.c  |   10 +++++++---
>  arch/arm/mach-pxa/palmld.c   |   19 ++++++++++---------
>  arch/arm/mach-pxa/palmt5.c   |   19 ++++++++++---------
>  arch/arm/mach-pxa/palmte2.c  |   20 ++++++++++++--------
>  arch/arm/mach-pxa/palmtreo.c |    1 -
>  arch/arm/mach-pxa/palmtx.c   |   19 ++++++++++---------
>  arch/arm/mach-pxa/palmz72.c  |   20 ++++++++++++--------
>  7 files changed, 61 insertions(+), 47 deletions(-)

For mioa701:
Acked-by: Robert Jarzmik <robert.jarzmik at free.fr>

Cheers.

--
Robert


From sleep_walker at suse.cz  Sun Jun  6 14:10:57 2010
From: sleep_walker at suse.cz (=?utf-8?q?Tom=C3=A1=C5=A1_=27Sleep=5FWalker=27?=
	=?utf-8?q?_=C4=8Cech?=)
Date: Sun, 6 Jun 2010 20:10:57 +0200
Subject: [PATCH 2/3] pxa: Fix all devices using wm97xx_batt.h
In-Reply-To: <1275613654-23918-2-git-send-email-marek.vasut@gmail.com>
References: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>
	<1275613654-23918-2-git-send-email-marek.vasut@gmail.com>
Message-ID: <201006062010.58423.sleep_walker@suse.cz>

Dne P? 4. ?ervna 2010 03:07:33 Marek Vasut napsal(a):
> This file is scheduled for removal, therefore fix all devices that use this
> file to use the suggested wm97xx.h and pass platform data properly.
> 
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> ---
>  arch/arm/mach-pxa/mioa701.c  |   10 +++++++---
>  arch/arm/mach-pxa/palmld.c   |   19 ++++++++++---------
>  arch/arm/mach-pxa/palmt5.c   |   19 ++++++++++---------
>  arch/arm/mach-pxa/palmte2.c  |   20 ++++++++++++--------
>  arch/arm/mach-pxa/palmtreo.c |    1 -
>  arch/arm/mach-pxa/palmtx.c   |   19 ++++++++++---------
>  arch/arm/mach-pxa/palmz72.c  |   20 ++++++++++++--------
>  7 files changed, 61 insertions(+), 47 deletions(-)
> 
...

> diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
> index d8b4469..4eb0258 100644
> --- a/arch/arm/mach-pxa/palmtreo.c
> +++ b/arch/arm/mach-pxa/palmtreo.c
> @@ -23,7 +23,6 @@
>  #include <linux/pda_power.h>
>  #include <linux/pwm_backlight.h>
>  #include <linux/gpio.h>
> -#include <linux/wm97xx_batt.h>
>  #include <linux/power_supply.h>
>  #include <linux/sysdev.h>
>  #include <linux/w1-gpio.h>


Thanks for this one.

For palmtreo.c:

Acked-by: Tomas Cech <sleep_walker at suse.cz>

Best regards,

Tomas Cech


From maramaopercheseimorto at gmail.com  Sun Jun  6 14:11:27 2010
From: maramaopercheseimorto at gmail.com (Alberto Panizzo)
Date: Sun, 06 Jun 2010 20:11:27 +0200
Subject: [V2 3/3] mx51/keypad: add keypad support for i.MX51 platforms
In-Reply-To: <4C0A5B8E.4020906@gmail.com>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-3-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-4-git-send-email-jason77.wang@gmail.com>
	<1275730558.3446.23.camel@realization>  <4C0A5B8E.4020906@gmail.com>
Message-ID: <1275847887.11528.13.camel@realization>

Hi Jason,

On sab, 2010-06-05 at 22:13 +0800, jason wrote:
> Alberto Panizzo wrote:
> > On gio, 2010-06-03 at 20:05 +0800, Jason Wang wrote:
> >   
> >> Add keypad controller device definition for all i.MX51 platforms,
> >> add a dummy kpp clock for imx keypad driver and add keypad device
> >> registration on i.MX51 3-stack board.
> >>
> >> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
> >> ---
> >>  arch/arm/mach-mx5/board-mx51_3ds.c |   59 ++++++++++++++++++++++++++++++++++++
> >>  arch/arm/mach-mx5/clock-mx51.c     |    5 +++
> >>  arch/arm/mach-mx5/devices.c        |   19 +++++++++++
> >>  arch/arm/mach-mx5/devices.h        |    1 +
> >>  4 files changed, 84 insertions(+), 0 deletions(-)
> >>     
> >
> > May you wont divide platform vs machine code in two different patches.
> >   
> Thanks for your comments, but here i don't really know what you mean,
> should i divide this patch to 2 patches or ?

Code that stays into devices.[c|h] is general code that shall not be 
modified together with machine code (board-mx51_3ds.c).


> > and, Eric B?nard is working on imx_keypad suspend/resume features[1] and
> > about it, he is going to modify the platform interface that make us able
> > to register the device.. this patch could look old in a few.
> >
> > [1]http://thread.gmane.org/gmane.linux.ports.arm.kernel/80968/focus=13131
> >
> > Best regards,
> > Alberto!
> >
> >   
> Yes, reading this thread, my platform interface is old.
> I just git pull the upstream, it seems that new interface change hasn't 
> been merged,
> i will modify this interface if it is merged into the upstream.

Well Dmitry (linux input maintainer) asked Eric some clarifications 
before merging his work.
In all case, Eric work is going to be part of the next merge window
through the linux input tree if all goes in the right way.
So in the imx tree you would see it at least since .35

Sascha, what is your policy about this? Shall Jason support the keypad
with the current interface and update it's support in the next merge
window? or it is better to wait?

Alberto!




From walsimou at walsimou.com  Sun Jun  6 15:13:14 2010
From: walsimou at walsimou.com (Abdoulaye Walsimou Gaye)
Date: Sun, 06 Jun 2010 21:13:14 +0200
Subject: mini2440 (likely more boards) boot failure because of recent changes
	in s3c gpio
Message-ID: <4C0BF34A.1060805@walsimou.com>

Hello list,
Recent changes in s3c gpio break mini2440 board.
The problem is that mach-mini2440.c: mini2440_init() (where we call 
s3c_gpio_setpull())
is called before s3c2440.c: s3c2440_init() (where we initialize 
s3c24xx_gpiocfg_default.set_pull function pointer).
This causes dereferencing of NULL pointer at boot time and a kernel panic.
The following change (probably not what needs to be done) lets the board 
boot again:

diff --git a/arch/arm/plat-s3c24xx/gpiolib.c 
b/arch/arm/plat-s3c24xx/gpiolib.c
index 4c0896f..ae9d3c2 100644
--- a/arch/arm/plat-s3c24xx/gpiolib.c
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -87,6 +87,8 @@ static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
  struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
         .set_config     = s3c_gpio_setcfg_s3c24xx,
         .get_config     = s3c_gpio_getcfg_s3c24xx,
+       .set_pull       = s3c_gpio_setpull_1up,
+       .get_pull       = s3c_gpio_getpull_1up,
  };

Best regards,
AWG


From marek.vasut at gmail.com  Sun Jun  6 23:40:20 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon,  7 Jun 2010 05:40:20 +0200
Subject: [PATCH] pxa/z2: Add regulator support
Message-ID: <1275882020-30159-1-git-send-email-marek.vasut@gmail.com>

Register TPS65023 regulator as found in Z2. The Z2 actually contains a TPS65021,
but this chip is apparently compatible.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/z2.c |   45 +++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 45 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index 967e8cb..c9c9857 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -27,6 +27,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/delay.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -610,6 +611,49 @@ static inline void z2_spi_init(void) {}
 #endif
 
 /******************************************************************************
+ * Core power regulator
+ ******************************************************************************/
+#if defined(CONFIG_REGULATOR_TPS65023) || \
+	defined(CONFIG_REGULATOR_TPS65023_MODULE)
+static struct regulator_consumer_supply z2_tps65021_consumers[] = {
+	{
+		.supply	= "vcc_core",
+	}
+};
+
+static struct regulator_init_data z2_tps65021_info[] = {
+	{
+		.constraints = {
+			.name		= "vcc_core range",
+			.min_uV		= 800000,
+			.max_uV		= 1600000,
+			.always_on	= 1,
+			.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		},
+		.consumer_supplies	= z2_tps65021_consumers,
+		.num_consumer_supplies	= ARRAY_SIZE(z2_tps65021_consumers),
+	},
+	/* The rest of the LDOs is unused */
+	{},{},{},{},
+};
+
+static struct i2c_board_info __initdata z2_pi2c_board_info[] = {
+	{
+		I2C_BOARD_INFO("tps65023", 0x48),
+		.platform_data	= &z2_tps65021_info,
+	},
+};
+
+static void __init z2_pmic_init(void)
+{
+	pxa27x_set_i2c_power_info(NULL);
+	i2c_register_board_info(1, ARRAY_AND_SIZE(z2_pi2c_board_info));
+}
+#else
+static inline void z2_pmic_init(void) {}
+#endif
+
+/******************************************************************************
  * Machine init
  ******************************************************************************/
 static void __init z2_init(void)
@@ -629,6 +673,7 @@ static void __init z2_init(void)
 	z2_pwm_init();
 	z2_leds_init();
 	z2_keys_init();
+	z2_pmic_init();
 }
 
 MACHINE_START(ZIPIT2, "Zipit Z2")
-- 
1.7.1



From marek.vasut at gmail.com  Sun Jun  6 23:59:03 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon,  7 Jun 2010 05:59:03 +0200
Subject: [PATCH v2] pxa/z2: Add regulator support
Message-ID: <1275883143-3512-1-git-send-email-marek.vasut@gmail.com>

Register TPS65023 regulator as found in Z2. The Z2 actually contains a TPS65021,
but this chip is apparently compatible.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/z2.c |   71 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 71 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index 967e8cb..cceffeb 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -27,6 +27,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/delay.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -610,6 +611,75 @@ static inline void z2_spi_init(void) {}
 #endif
 
 /******************************************************************************
+ * Core power regulator
+ ******************************************************************************/
+#if defined(CONFIG_REGULATOR_TPS65023) || \
+	defined(CONFIG_REGULATOR_TPS65023_MODULE)
+static struct regulator_consumer_supply z2_tps65021_consumers[] = {
+	{
+		.supply	= "vcc_core",
+	}
+};
+
+static struct regulator_init_data z2_tps65021_info[] = {
+	{
+		.constraints = {
+			.name		= "vcc_core range",
+			.min_uV		= 800000,
+			.max_uV		= 1600000,
+			.always_on	= 1,
+			.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		},
+		.consumer_supplies	= z2_tps65021_consumers,
+		.num_consumer_supplies	= ARRAY_SIZE(z2_tps65021_consumers),
+	}, {
+		.constraints = {
+			.name		= "DCDC2",
+			.min_uV		= 3300000,
+			.max_uV		= 3300000,
+			.always_on	= 1,
+		},
+	}, {
+		.constraints = {
+			.name		= "DCDC3",
+			.min_uV		= 1800000,
+			.max_uV		= 1800000,
+			.always_on	= 1,
+		},
+	}, {
+		.constraints = {
+			.name		= "LDO1",
+			.min_uV		= 1000000,
+			.max_uV		= 3150000,
+			.always_on	= 1,
+		},
+	}, {
+		.constraints = {
+			.name		= "LDO2",
+			.min_uV		= 1050000,
+			.max_uV		= 3300000,
+			.always_on	= 1,
+		},
+	}
+};
+
+static struct i2c_board_info __initdata z2_pi2c_board_info[] = {
+	{
+		I2C_BOARD_INFO("tps65023", 0x48),
+		.platform_data	= &z2_tps65021_info,
+	},
+};
+
+static void __init z2_pmic_init(void)
+{
+	pxa27x_set_i2c_power_info(NULL);
+	i2c_register_board_info(1, ARRAY_AND_SIZE(z2_pi2c_board_info));
+}
+#else
+static inline void z2_pmic_init(void) {}
+#endif
+
+/******************************************************************************
  * Machine init
  ******************************************************************************/
 static void __init z2_init(void)
@@ -629,6 +699,7 @@ static void __init z2_init(void)
 	z2_pwm_init();
 	z2_leds_init();
 	z2_keys_init();
+	z2_pmic_init();
 }
 
 MACHINE_START(ZIPIT2, "Zipit Z2")
-- 
1.7.1



From marek.vasut at gmail.com  Mon Jun  7 01:18:28 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon,  7 Jun 2010 07:18:28 +0200
Subject: [PATCH 2/2] pxa/spitz: Add isl6271a voltage regulator
In-Reply-To: <1275887908-22285-1-git-send-email-marek.vasut@gmail.com>
References: <1275887908-22285-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1275887908-22285-2-git-send-email-marek.vasut@gmail.com>

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/spitz.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index c1048a3..97c207d 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -709,6 +709,13 @@ static struct platform_device sharpsl_rom_device = {
 	.dev.platform_data = &sharpsl_rom_data,
 };
 
+static struct i2c_board_info spitz_pi2c_board_info[] = {
+	{
+		.type		= "isl6271a",
+		.addr		= 0x1b,
+	},
+};
+
 static struct platform_device *devices[] __initdata = {
 	&spitzscoop_device,
 	&spitzkbd_device,
@@ -765,6 +772,9 @@ static void __init common_init(void)
 	pxa_set_ficp_info(&spitz_ficp_platform_data);
 	set_pxa_fb_info(&spitz_pxafb_info);
 	pxa_set_i2c_info(NULL);
+
+	pxa27x_set_i2c_power_info(NULL);
+	i2c_register_board_info(1, ARRAY_AND_SIZE(spitz_pi2c_board_info));
 }
 
 #if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI)
-- 
1.7.1



From marek.vasut at gmail.com  Mon Jun  7 01:18:27 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon,  7 Jun 2010 07:18:27 +0200
Subject: [PATCH 1/2] ISL6271A voltage regulator support.
Message-ID: <1275887908-22285-1-git-send-email-marek.vasut@gmail.com>

This device is very simple, it supports only one LDO. This single LDO is
programmed over I2C to 16 possible voltages.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/regulator/Kconfig              |    6 +
 drivers/regulator/Makefile             |    1 +
 drivers/regulator/isl6271a-regulator.c |  202 ++++++++++++++++++++++++++++++++
 3 files changed, 209 insertions(+), 0 deletions(-)
 create mode 100644 drivers/regulator/isl6271a-regulator.c

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 04f2e08..6772ca7 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -201,5 +201,11 @@ config REGULATOR_88PM8607
 	help
 	  This driver supports 88PM8607 voltage regulator chips.
 
+config REGULATOR_ISL6271A
+	tristate "Intersil ISL6271A Power regulator"
+	depends on I2C
+	help
+	  This driver supports ISL6271A voltage regulator chip.
+
 endif
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 4e7feec..e2191bf 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
 obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o
 obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
 obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
+obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/isl6271a-regulator.c b/drivers/regulator/isl6271a-regulator.c
new file mode 100644
index 0000000..c6fd20f
--- /dev/null
+++ b/drivers/regulator/isl6271a-regulator.c
@@ -0,0 +1,202 @@
+/*
+ * isl6271a-regulator.c
+ *
+ * Support for Intersil ISL6271A voltage regulator
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+/* Supported voltage values for regulators */
+static const u16 core_buck_table[] = {
+	850, 900, 950, 1000,
+	1050, 1100, 1150, 1200,
+	1250, 1300, 1350, 1400,
+	1450, 1500, 1550, 1600,
+};
+
+/* PMIC details */
+struct isl_pmic {
+	struct regulator_desc	desc;
+	struct i2c_client	*client;
+	struct regulator_dev	*rdev;
+	struct mutex		mtx;
+};
+
+static int isl6271a_get_voltage(struct regulator_dev *dev)
+{
+	struct isl_pmic *pmic = rdev_get_drvdata(dev);
+	int idx, data;
+
+	mutex_lock(&pmic->mtx);
+
+	idx = i2c_smbus_read_byte_data(pmic->client, 0);
+	if (idx < 0) {
+		dev_err(&pmic->client->dev, "Error getting voltage\n");
+		data = idx;
+		goto out;
+	}
+
+	data = core_buck_table[idx & 0xf];
+
+out:
+	mutex_unlock(&pmic->mtx);
+	return idx;
+}
+
+static int isl6271a_set_voltage(struct regulator_dev *dev, int minuV, int maxuV)
+{
+	struct isl_pmic *pmic = rdev_get_drvdata(dev);
+	int vsel, err;
+	int pmic_minuV = core_buck_table[0];
+	int pmic_maxuV = core_buck_table[ARRAY_SIZE(core_buck_table) - 1];
+
+	if (minuV < pmic_minuV || minuV > pmic_maxuV)
+		return -EINVAL;
+	if (maxuV < pmic_minuV || maxuV > pmic_maxuV)
+		return -EINVAL;
+
+	for (vsel = 0; vsel < ARRAY_SIZE(core_buck_table); vsel++) {
+		int uV = core_buck_table[vsel];
+
+		if (minuV <= uV && uV <= maxuV)
+			break;
+	}
+
+	if (vsel == ARRAY_SIZE(core_buck_table))
+		return -EINVAL;
+
+	mutex_lock(&pmic->mtx);
+
+	err = i2c_smbus_write_byte_data(pmic->client, 0, vsel);
+	if (err < 0)
+		dev_err(&pmic->client->dev, "Error setting voltage\n");
+
+	mutex_unlock(&pmic->mtx);
+	return err;
+}
+
+static int isl6271a_list_voltage(struct regulator_dev *dev, unsigned selector)
+{
+	return core_buck_table[selector];
+}
+
+static struct regulator_ops isl_core_ops = {
+	.get_voltage	= isl6271a_get_voltage,
+	.set_voltage	= isl6271a_set_voltage,
+	.list_voltage	= isl6271a_list_voltage,
+};
+
+static int __devinit isl6271a_probe(struct i2c_client *client,
+				     const struct i2c_device_id *id)
+{
+	struct regulator_init_data *init_data	= client->dev.platform_data;
+	struct isl_pmic *pmic;
+	int err;
+
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+		return -EIO;
+
+	if (!init_data)
+		return -EIO;
+
+	pmic = kzalloc(sizeof(struct isl_pmic), GFP_KERNEL);
+	if (!pmic)
+		return -ENOMEM;
+
+	pmic->client = client;
+
+	mutex_init(&pmic->mtx);
+
+	pmic->desc.name	= "Core Buck";
+	pmic->desc.id	= 0;
+	pmic->desc.n_voltages = ARRAY_SIZE(core_buck_table);
+	pmic->desc.ops	= &isl_core_ops;
+	pmic->desc.type	= REGULATOR_VOLTAGE;
+	pmic->desc.owner = THIS_MODULE;
+
+	pmic->rdev = regulator_register(&pmic->desc, &client->dev,
+					init_data, pmic);
+	if (IS_ERR(pmic->rdev)) {
+		dev_err(&client->dev, "failed to register %s\n",
+			id->name);
+		err = PTR_ERR(pmic->rdev);
+		goto error;
+	}
+
+	i2c_set_clientdata(client, pmic);
+
+	return 0;
+
+error:
+	regulator_unregister(pmic->rdev);
+
+	kfree(pmic);
+	return err;
+}
+
+static int __devexit isl6271a_remove(struct i2c_client *client)
+{
+	struct isl_pmic *pmic = i2c_get_clientdata(client);
+
+	i2c_set_clientdata(client, NULL);
+
+	regulator_unregister(pmic->rdev);
+
+	kfree(pmic);
+
+	return 0;
+}
+
+static const struct i2c_device_id isl6271a_id[] = {
+	{.name = "isl6271a", 0 },
+	{ },
+};
+
+MODULE_DEVICE_TABLE(i2c, isl6271a_id);
+
+static struct i2c_driver isl6271a_i2c_driver = {
+	.driver = {
+		.name = "isl6271a",
+		.owner = THIS_MODULE,
+	},
+	.probe = isl6271a_probe,
+	.remove = __devexit_p(isl6271a_remove),
+	.id_table = isl6271a_id,
+};
+
+static int __init isl6271a_init(void)
+{
+	return i2c_add_driver(&isl6271a_i2c_driver);
+}
+
+static void __exit isl6271a_cleanup(void)
+{
+	i2c_del_driver(&isl6271a_i2c_driver);
+}
+
+subsys_initcall(isl6271a_init);
+module_exit(isl6271a_cleanup);
+
+MODULE_AUTHOR("Marek Vasut <marek.vasut at gmail.com>");
+MODULE_DESCRIPTION("Intersil ISL6271A voltage regulator driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.1



From marek.vasut at gmail.com  Mon Jun  7 01:27:53 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon,  7 Jun 2010 07:27:53 +0200
Subject: [PATCH 2/2] pxa/spitz: Add isl6271a voltage regulator
In-Reply-To: <1275888473-22512-1-git-send-email-marek.vasut@gmail.com>
References: <1275888473-22512-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1275888473-22512-2-git-send-email-marek.vasut@gmail.com>

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/spitz.c |   32 ++++++++++++++++++++++++++++++++
 1 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index c1048a3..5767ceb 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -26,6 +26,7 @@
 #include <linux/spi/corgi_lcd.h>
 #include <linux/mtd/sharpsl.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -709,6 +710,34 @@ static struct platform_device sharpsl_rom_device = {
 	.dev.platform_data = &sharpsl_rom_data,
 };
 
+static struct regulator_consumer_supply isl6271a_consumers[] = {
+	{
+		.supply	= "vcc_core",
+	}
+};
+
+static struct regulator_init_data isl6271a_info[] = {
+	{
+		.constraints = {
+			.name		= "vcc_core range",
+			.min_uV		= 850000,
+			.max_uV		= 1600000,
+			.always_on	= 1,
+			.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		},
+		.consumer_supplies	= isl6271_consumers,
+		.num_consumer_supplies	= ARRAY_SIZE(isl6271_consumers),
+	}
+};
+
+static struct i2c_board_info spitz_pi2c_board_info[] = {
+	{
+		.type		= "isl6271a",
+		.addr		= 0x1b,
+		.platform_data	= &isl6271_info,
+	},
+};
+
 static struct platform_device *devices[] __initdata = {
 	&spitzscoop_device,
 	&spitzkbd_device,
@@ -765,6 +794,9 @@ static void __init common_init(void)
 	pxa_set_ficp_info(&spitz_ficp_platform_data);
 	set_pxa_fb_info(&spitz_pxafb_info);
 	pxa_set_i2c_info(NULL);
+
+	pxa27x_set_i2c_power_info(NULL);
+	i2c_register_board_info(1, ARRAY_AND_SIZE(spitz_pi2c_board_info));
 }
 
 #if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI)
-- 
1.7.1



From marek.vasut at gmail.com  Mon Jun  7 01:27:52 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon,  7 Jun 2010 07:27:52 +0200
Subject: [PATCH 1/2] ISL6271A voltage regulator support.
Message-ID: <1275888473-22512-1-git-send-email-marek.vasut@gmail.com>

This device is very simple, it supports only one LDO. This single LDO is
programmed over I2C to 16 possible voltages.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/regulator/Kconfig              |    6 +
 drivers/regulator/Makefile             |    1 +
 drivers/regulator/isl6271a-regulator.c |  202 ++++++++++++++++++++++++++++++++
 3 files changed, 209 insertions(+), 0 deletions(-)
 create mode 100644 drivers/regulator/isl6271a-regulator.c

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 04f2e08..6772ca7 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -201,5 +201,11 @@ config REGULATOR_88PM8607
 	help
 	  This driver supports 88PM8607 voltage regulator chips.
 
+config REGULATOR_ISL6271A
+	tristate "Intersil ISL6271A Power regulator"
+	depends on I2C
+	help
+	  This driver supports ISL6271A voltage regulator chip.
+
 endif
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 4e7feec..e2191bf 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
 obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o
 obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
 obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
+obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/isl6271a-regulator.c b/drivers/regulator/isl6271a-regulator.c
new file mode 100644
index 0000000..c6fd20f
--- /dev/null
+++ b/drivers/regulator/isl6271a-regulator.c
@@ -0,0 +1,202 @@
+/*
+ * isl6271a-regulator.c
+ *
+ * Support for Intersil ISL6271A voltage regulator
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+/* Supported voltage values for regulators */
+static const u16 core_buck_table[] = {
+	850, 900, 950, 1000,
+	1050, 1100, 1150, 1200,
+	1250, 1300, 1350, 1400,
+	1450, 1500, 1550, 1600,
+};
+
+/* PMIC details */
+struct isl_pmic {
+	struct regulator_desc	desc;
+	struct i2c_client	*client;
+	struct regulator_dev	*rdev;
+	struct mutex		mtx;
+};
+
+static int isl6271a_get_voltage(struct regulator_dev *dev)
+{
+	struct isl_pmic *pmic = rdev_get_drvdata(dev);
+	int idx, data;
+
+	mutex_lock(&pmic->mtx);
+
+	idx = i2c_smbus_read_byte_data(pmic->client, 0);
+	if (idx < 0) {
+		dev_err(&pmic->client->dev, "Error getting voltage\n");
+		data = idx;
+		goto out;
+	}
+
+	data = core_buck_table[idx & 0xf];
+
+out:
+	mutex_unlock(&pmic->mtx);
+	return idx;
+}
+
+static int isl6271a_set_voltage(struct regulator_dev *dev, int minuV, int maxuV)
+{
+	struct isl_pmic *pmic = rdev_get_drvdata(dev);
+	int vsel, err;
+	int pmic_minuV = core_buck_table[0];
+	int pmic_maxuV = core_buck_table[ARRAY_SIZE(core_buck_table) - 1];
+
+	if (minuV < pmic_minuV || minuV > pmic_maxuV)
+		return -EINVAL;
+	if (maxuV < pmic_minuV || maxuV > pmic_maxuV)
+		return -EINVAL;
+
+	for (vsel = 0; vsel < ARRAY_SIZE(core_buck_table); vsel++) {
+		int uV = core_buck_table[vsel];
+
+		if (minuV <= uV && uV <= maxuV)
+			break;
+	}
+
+	if (vsel == ARRAY_SIZE(core_buck_table))
+		return -EINVAL;
+
+	mutex_lock(&pmic->mtx);
+
+	err = i2c_smbus_write_byte_data(pmic->client, 0, vsel);
+	if (err < 0)
+		dev_err(&pmic->client->dev, "Error setting voltage\n");
+
+	mutex_unlock(&pmic->mtx);
+	return err;
+}
+
+static int isl6271a_list_voltage(struct regulator_dev *dev, unsigned selector)
+{
+	return core_buck_table[selector];
+}
+
+static struct regulator_ops isl_core_ops = {
+	.get_voltage	= isl6271a_get_voltage,
+	.set_voltage	= isl6271a_set_voltage,
+	.list_voltage	= isl6271a_list_voltage,
+};
+
+static int __devinit isl6271a_probe(struct i2c_client *client,
+				     const struct i2c_device_id *id)
+{
+	struct regulator_init_data *init_data	= client->dev.platform_data;
+	struct isl_pmic *pmic;
+	int err;
+
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+		return -EIO;
+
+	if (!init_data)
+		return -EIO;
+
+	pmic = kzalloc(sizeof(struct isl_pmic), GFP_KERNEL);
+	if (!pmic)
+		return -ENOMEM;
+
+	pmic->client = client;
+
+	mutex_init(&pmic->mtx);
+
+	pmic->desc.name	= "Core Buck";
+	pmic->desc.id	= 0;
+	pmic->desc.n_voltages = ARRAY_SIZE(core_buck_table);
+	pmic->desc.ops	= &isl_core_ops;
+	pmic->desc.type	= REGULATOR_VOLTAGE;
+	pmic->desc.owner = THIS_MODULE;
+
+	pmic->rdev = regulator_register(&pmic->desc, &client->dev,
+					init_data, pmic);
+	if (IS_ERR(pmic->rdev)) {
+		dev_err(&client->dev, "failed to register %s\n",
+			id->name);
+		err = PTR_ERR(pmic->rdev);
+		goto error;
+	}
+
+	i2c_set_clientdata(client, pmic);
+
+	return 0;
+
+error:
+	regulator_unregister(pmic->rdev);
+
+	kfree(pmic);
+	return err;
+}
+
+static int __devexit isl6271a_remove(struct i2c_client *client)
+{
+	struct isl_pmic *pmic = i2c_get_clientdata(client);
+
+	i2c_set_clientdata(client, NULL);
+
+	regulator_unregister(pmic->rdev);
+
+	kfree(pmic);
+
+	return 0;
+}
+
+static const struct i2c_device_id isl6271a_id[] = {
+	{.name = "isl6271a", 0 },
+	{ },
+};
+
+MODULE_DEVICE_TABLE(i2c, isl6271a_id);
+
+static struct i2c_driver isl6271a_i2c_driver = {
+	.driver = {
+		.name = "isl6271a",
+		.owner = THIS_MODULE,
+	},
+	.probe = isl6271a_probe,
+	.remove = __devexit_p(isl6271a_remove),
+	.id_table = isl6271a_id,
+};
+
+static int __init isl6271a_init(void)
+{
+	return i2c_add_driver(&isl6271a_i2c_driver);
+}
+
+static void __exit isl6271a_cleanup(void)
+{
+	i2c_del_driver(&isl6271a_i2c_driver);
+}
+
+subsys_initcall(isl6271a_init);
+module_exit(isl6271a_cleanup);
+
+MODULE_AUTHOR("Marek Vasut <marek.vasut at gmail.com>");
+MODULE_DESCRIPTION("Intersil ISL6271A voltage regulator driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.1



From marek.vasut at gmail.com  Mon Jun  7 01:28:25 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 7 Jun 2010 07:28:25 +0200
Subject: [PATCH 1/2] ISL6271A voltage regulator support.
In-Reply-To: <1275887908-22285-1-git-send-email-marek.vasut@gmail.com>
References: <1275887908-22285-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <201006070728.25620.marek.vasut@gmail.com>

Dne Po 7. ?ervna 2010 07:18:27 Marek Vasut napsal(a):
> This device is very simple, it supports only one LDO. This single LDO is
> programmed over I2C to 16 possible voltages.
> 
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

I need to test this ... Cyril, will you do me the favour? I'll return that 
Zaurus to you, I was unable to compile kernel for it (I dunno what options to 
select and I don't feel like trying to figure out).

Also, see the comment below, if it doesn't boot for you, maybe adjust it (try 
setting it to 1, 2, 3).

btw. I made modification to 2/2 patch of this series, use the updated patchset.

Thanks!

> ---
>  drivers/regulator/Kconfig              |    6 +
>  drivers/regulator/Makefile             |    1 +
>  drivers/regulator/isl6271a-regulator.c |  202
> ++++++++++++++++++++++++++++++++ 3 files changed, 209 insertions(+), 0
> deletions(-)
>  create mode 100644 drivers/regulator/isl6271a-regulator.c
> 
> diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
> index 04f2e08..6772ca7 100644
> --- a/drivers/regulator/Kconfig
> +++ b/drivers/regulator/Kconfig
> @@ -201,5 +201,11 @@ config REGULATOR_88PM8607
>  	help
>  	  This driver supports 88PM8607 voltage regulator chips.
> 
> +config REGULATOR_ISL6271A
> +	tristate "Intersil ISL6271A Power regulator"
> +	depends on I2C
> +	help
> +	  This driver supports ISL6271A voltage regulator chip.
> +
>  endif
> 
> diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
> index 4e7feec..e2191bf 100644
> --- a/drivers/regulator/Makefile
> +++ b/drivers/regulator/Makefile
> @@ -31,5 +31,6 @@ obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
>  obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o
>  obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
>  obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
> +obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
> 
>  ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
> diff --git a/drivers/regulator/isl6271a-regulator.c
> b/drivers/regulator/isl6271a-regulator.c new file mode 100644
> index 0000000..c6fd20f
> --- /dev/null
> +++ b/drivers/regulator/isl6271a-regulator.c
> @@ -0,0 +1,202 @@
> +/*
> + * isl6271a-regulator.c
> + *
> + * Support for Intersil ISL6271A voltage regulator
> + *
> + * Copyright (C) 2010 Marek Vasut <marek.vasut at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation version 2.
> + *
> + * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
> + * whether express or implied; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * General Public License for more details.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/driver.h>
> +#include <linux/regulator/machine.h>
> +#include <linux/i2c.h>
> +#include <linux/delay.h>
> +#include <linux/slab.h>
> +
> +/* Supported voltage values for regulators */
> +static const u16 core_buck_table[] = {
> +	850, 900, 950, 1000,
> +	1050, 1100, 1150, 1200,
> +	1250, 1300, 1350, 1400,
> +	1450, 1500, 1550, 1600,
> +};
> +
> +/* PMIC details */
> +struct isl_pmic {
> +	struct regulator_desc	desc;
> +	struct i2c_client	*client;
> +	struct regulator_dev	*rdev;
> +	struct mutex		mtx;
> +};
> +
> +static int isl6271a_get_voltage(struct regulator_dev *dev)
> +{
> +	struct isl_pmic *pmic = rdev_get_drvdata(dev);
> +	int idx, data;
> +
> +	mutex_lock(&pmic->mtx);
> +
> +	idx = i2c_smbus_read_byte_data(pmic->client, 0);
> +	if (idx < 0) {
> +		dev_err(&pmic->client->dev, "Error getting voltage\n");
> +		data = idx;
> +		goto out;
> +	}
> +
> +	data = core_buck_table[idx & 0xf];
> +
> +out:
> +	mutex_unlock(&pmic->mtx);
> +	return idx;
> +}
> +
> +static int isl6271a_set_voltage(struct regulator_dev *dev, int minuV, int
> maxuV) +{
> +	struct isl_pmic *pmic = rdev_get_drvdata(dev);
> +	int vsel, err;
> +	int pmic_minuV = core_buck_table[0];
> +	int pmic_maxuV = core_buck_table[ARRAY_SIZE(core_buck_table) - 1];
> +
> +	if (minuV < pmic_minuV || minuV > pmic_maxuV)
> +		return -EINVAL;
> +	if (maxuV < pmic_minuV || maxuV > pmic_maxuV)
> +		return -EINVAL;
> +
> +	for (vsel = 0; vsel < ARRAY_SIZE(core_buck_table); vsel++) {
> +		int uV = core_buck_table[vsel];
> +
> +		if (minuV <= uV && uV <= maxuV)
> +			break;
> +	}
> +
> +	if (vsel == ARRAY_SIZE(core_buck_table))
> +		return -EINVAL;
> +
> +	mutex_lock(&pmic->mtx);

maybe here we should adjust the vsel with slew-rate (page 9 of the datasheet):

vsel |= slew_rate << 4; // slew_rate is in range 0..3

> +
> +	err = i2c_smbus_write_byte_data(pmic->client, 0, vsel);
> +	if (err < 0)
> +		dev_err(&pmic->client->dev, "Error setting voltage\n");
> +
> +	mutex_unlock(&pmic->mtx);
> +	return err;
> +}
> +
> +static int isl6271a_list_voltage(struct regulator_dev *dev, unsigned
> selector) +{
> +	return core_buck_table[selector];
> +}
> +
> +static struct regulator_ops isl_core_ops = {
> +	.get_voltage	= isl6271a_get_voltage,
> +	.set_voltage	= isl6271a_set_voltage,
> +	.list_voltage	= isl6271a_list_voltage,
> +};
> +
> +static int __devinit isl6271a_probe(struct i2c_client *client,
> +				     const struct i2c_device_id *id)
> +{
> +	struct regulator_init_data *init_data	= client->dev.platform_data;
> +	struct isl_pmic *pmic;
> +	int err;
> +
> +	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
> +		return -EIO;
> +
> +	if (!init_data)
> +		return -EIO;
> +
> +	pmic = kzalloc(sizeof(struct isl_pmic), GFP_KERNEL);
> +	if (!pmic)
> +		return -ENOMEM;
> +
> +	pmic->client = client;
> +
> +	mutex_init(&pmic->mtx);
> +
> +	pmic->desc.name	= "Core Buck";
> +	pmic->desc.id	= 0;
> +	pmic->desc.n_voltages = ARRAY_SIZE(core_buck_table);
> +	pmic->desc.ops	= &isl_core_ops;
> +	pmic->desc.type	= REGULATOR_VOLTAGE;
> +	pmic->desc.owner = THIS_MODULE;
> +
> +	pmic->rdev = regulator_register(&pmic->desc, &client->dev,
> +					init_data, pmic);
> +	if (IS_ERR(pmic->rdev)) {
> +		dev_err(&client->dev, "failed to register %s\n",
> +			id->name);
> +		err = PTR_ERR(pmic->rdev);
> +		goto error;
> +	}
> +
> +	i2c_set_clientdata(client, pmic);
> +
> +	return 0;
> +
> +error:
> +	regulator_unregister(pmic->rdev);
> +
> +	kfree(pmic);
> +	return err;
> +}
> +
> +static int __devexit isl6271a_remove(struct i2c_client *client)
> +{
> +	struct isl_pmic *pmic = i2c_get_clientdata(client);
> +
> +	i2c_set_clientdata(client, NULL);
> +
> +	regulator_unregister(pmic->rdev);
> +
> +	kfree(pmic);
> +
> +	return 0;
> +}
> +
> +static const struct i2c_device_id isl6271a_id[] = {
> +	{.name = "isl6271a", 0 },
> +	{ },
> +};
> +
> +MODULE_DEVICE_TABLE(i2c, isl6271a_id);
> +
> +static struct i2c_driver isl6271a_i2c_driver = {
> +	.driver = {
> +		.name = "isl6271a",
> +		.owner = THIS_MODULE,
> +	},
> +	.probe = isl6271a_probe,
> +	.remove = __devexit_p(isl6271a_remove),
> +	.id_table = isl6271a_id,
> +};
> +
> +static int __init isl6271a_init(void)
> +{
> +	return i2c_add_driver(&isl6271a_i2c_driver);
> +}
> +
> +static void __exit isl6271a_cleanup(void)
> +{
> +	i2c_del_driver(&isl6271a_i2c_driver);
> +}
> +
> +subsys_initcall(isl6271a_init);
> +module_exit(isl6271a_cleanup);
> +
> +MODULE_AUTHOR("Marek Vasut <marek.vasut at gmail.com>");
> +MODULE_DESCRIPTION("Intersil ISL6271A voltage regulator driver");
> +MODULE_LICENSE("GPL v2");


From marek.vasut at gmail.com  Mon Jun  7 01:32:02 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 7 Jun 2010 07:32:02 +0200
Subject: [PATCH 2/2] pxa/spitz: Add isl6271a voltage regulator
In-Reply-To: <1275888473-22512-2-git-send-email-marek.vasut@gmail.com>
References: <1275888473-22512-1-git-send-email-marek.vasut@gmail.com>
	<1275888473-22512-2-git-send-email-marek.vasut@gmail.com>
Message-ID: <201006070732.02675.marek.vasut@gmail.com>

Dne Po 7. ?ervna 2010 07:27:53 Marek Vasut napsal(a):
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> ---
>  arch/arm/mach-pxa/spitz.c |   32 ++++++++++++++++++++++++++++++++
>  1 files changed, 32 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
> index c1048a3..5767ceb 100644
> --- a/arch/arm/mach-pxa/spitz.c
> +++ b/arch/arm/mach-pxa/spitz.c
> @@ -26,6 +26,7 @@
>  #include <linux/spi/corgi_lcd.h>
>  #include <linux/mtd/sharpsl.h>
>  #include <linux/input/matrix_keypad.h>
> +#include <linux/regulator/machine.h>
> 
>  #include <asm/setup.h>
>  #include <asm/mach-types.h>
> @@ -709,6 +710,34 @@ static struct platform_device sharpsl_rom_device = {
>  	.dev.platform_data = &sharpsl_rom_data,
>  };
> 
> +static struct regulator_consumer_supply isl6271a_consumers[] = {
> +	{
> +		.supply	= "vcc_core",
> +	}
> +};
> +
> +static struct regulator_init_data isl6271a_info[] = {
> +	{
> +		.constraints = {
> +			.name		= "vcc_core range",
> +			.min_uV		= 850000,
> +			.max_uV		= 1600000,
> +			.always_on	= 1,
> +			.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
> +		},
> +		.consumer_supplies	= isl6271_consumers,
> +		.num_consumer_supplies	= ARRAY_SIZE(isl6271_consumers),
> +	}
> +};
> +
> +static struct i2c_board_info spitz_pi2c_board_info[] = {
> +	{
> +		.type		= "isl6271a",
> +		.addr		= 0x1b,

btw. also change this -- i2c_detect will tell you what address the chip have if 
you don't know it yet.

> +		.platform_data	= &isl6271_info,
> +	},
> +};
> +
>  static struct platform_device *devices[] __initdata = {
>  	&spitzscoop_device,
>  	&spitzkbd_device,
> @@ -765,6 +794,9 @@ static void __init common_init(void)
>  	pxa_set_ficp_info(&spitz_ficp_platform_data);
>  	set_pxa_fb_info(&spitz_pxafb_info);
>  	pxa_set_i2c_info(NULL);
> +
> +	pxa27x_set_i2c_power_info(NULL);
> +	i2c_register_board_info(1, ARRAY_AND_SIZE(spitz_pi2c_board_info));
>  }
> 
>  #if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI)


From marek.vasut at gmail.com  Mon Jun  7 02:58:36 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 7 Jun 2010 08:58:36 +0200
Subject: pxa300 - DDRAM base value
In-Reply-To: <1275892191.3501.17.camel@balakrishnan-desktop>
References: <1275371058.7001.35.camel@balakrishnan-desktop>
	<201006061834.50297.marek.vasut@gmail.com>
	<1275892191.3501.17.camel@balakrishnan-desktop>
Message-ID: <201006070858.36341.marek.vasut@gmail.com>

Dne Po 7. ?ervna 2010 08:29:51 balakrishnan napsal(a):
> On Sun, 2010-06-06 at 18:34 +0200, Marek Vasut wrote:
> > Dne Ne 6. ?ervna 2010 10:17:00 Eric Miao napsal(a):
> > > On Sun, Jun 6, 2010 at 1:19 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > > > Dne ?t 1. ?ervna 2010 07:44:18 balakrishnan napsal(a):
> > > >> I am working on pxa300 based development board and using Linux
> > > >> 2.6.34. This Linux kernel already has support for following boards
> > > >> 1. zylonite_pxa300
> > > >> 2. cm-x300
> > > >> 3. colibri-pxa300
> > > >> 4. littleton
> > > >> 
> > > >> My doubt is that pxa300 based boards are using "0xa0000000"  as
> > > >> DDRAM base and PHYS_OFFSET is also defined in
> > > >> "arch/arm/mach-pxa/include/mach/memory.h" as 0xa0000000.
> > > >> But in our board  DDR is mapped in 0x80000000. Does it make any
> > > >> problem?. Because after mmu is turned ON, my board is hanging.
> > > >> 
> > > >> "zreladdr-y   := 0x80008000" is defined in
> > > >> "arch/arm/mach-pxa/Makefile.boot" file .
> > > >> my machine_desc is as follows
> > > >> .phys_io        = 0x40000000,
> > > >> .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
> > > >> .boot_params    = 0x80000100,
> > > > 
> > > > Try editing both arch/arm/mach-pxa/Makefile.boot and
> > > > arch/arm/mach/pxa/include/mach/memory.h
> > > > 
> > > >> With Thanks
> > > >> J.Balakrishnan
> > > > 
> > > > The 0x80000000 should be aliased to 0xa0000000, but looking into the
> > > > PXA docs, it is only on pxa320. Eric, any ideas on this ?
> > > 
> > > Should be working on pxa300/310 as well. If it doesn't, check you
> > > bootloader to make sure the mapping is OK, and memory doesn't exceed
> > > (0xa000_0000 - 0x8000_0000).
> > 
> > It worked last time I used the pxa310 littleton board, but I can't check
> > on the pxa300 zylonite board just yet.
> > 
> > Could you give us your bootloader details ?
> 
> hi,
>       Now, I can able to boot after editing following files
> arch/arm/mach-pxa/Makefile.boot and
> arch/arm/mach/pxa/include/mach/memory.h (0x80000000 changed to
> 0xa0000000). My doubt is

It was always set to 0xa0000000, both of them.

> 1.why 0x80000000 (DDR phy address) is aliased to 0xa0000000 in pxa
> architecture?

Because that's how the HW guys did it and because it's written in TRM (which is 
the holy bible(substitute any other holy object) of the CPU) ;-)

> 2.In my development board two DDRAMs mapped at 0x80000000-0x88000000 and
> 0xc0000000-0xc8000000, how can I inform to kernel about this different
> bank and size?.

Check LAKML and look for:
"[PATCH] pxa/vpac270: Enable SparseMEM for 256 MB of RAM"

This might give you an idea ... though it's a hack. All this goo about 
PHYS_OFFSET etc. will be gone in hopefully near future.

Cheers!

> 
> My Boot loader details,
> ------------------------------
> =>bdi
> arch_number = 0x00000B04
> env_t       = 0x00000000
> boot_params = 0x80000100
> DRAM bank   = 0x00000000
> -> start    = 0x80000000
> -> size     = 0x08000000
> DRAM bank   = 0x00000001
> -> start    = 0xC0000000
> -> size     = 0x08000000
> ethaddr     = 08:00:3e:26:0a:5b
> ip_addr     = 192.168.0.21
> baudrate    = 115200 bps
> =>ver
> U-Boot 2010.03 (Jun 01 2010 - 14:27:43)
> 
> 
> With Thanks
> J.Balakrishnan


From stefan at datenfreihafen.org  Mon Jun  7 03:07:24 2010
From: stefan at datenfreihafen.org (Stefan Schmidt)
Date: Mon, 7 Jun 2010 09:07:24 +0200
Subject: [RFC PATCH] stargate2 and imote2 board file merge
In-Reply-To: <1275832502-28552-1-git-send-email-jic23@cam.ac.uk>
References: <1275832502-28552-1-git-send-email-jic23@cam.ac.uk>
Message-ID: <20100607070724.GB2702@excalibur.local>

Hello.

On Sun, 2010-06-06 at 14:55, Jonathan Cameron wrote:
> Signed-off-by: Jonathan Cameron <jic23 at cam.ac.uk>
> ---
>  These two boards are extremely similar in many ways and hence
>  the board configs overlap a lot.  This patch merges the two
>  board files.  Do people think this is worth doing?  Traditionally
>  we always built a kernel supporting both devices anyway but the
>  ifdefs allow one to be picked if people really want to.

I find it an interesting idea. We have done this on EZX with 6 devices. One
thing that jumps into my face is that we should provide a way to let people know
that the stargate2.c file does indeed also provide support for imote2. At least
updated comments in KConfig and the header of the c file would be needed. That
would allow people to discover it during configuration or greping.

I don't know much about the Crossbow product palette but maybe we should even
rename it to crossbow.c

>  arch/arm/mach-pxa/Makefile    |    2 +-
>  arch/arm/mach-pxa/imote2.c    |  590 -----------------------------------
>  arch/arm/mach-pxa/stargate2.c |  679 +++++++++++++++++++++++++++--------------
>  3 files changed, 454 insertions(+), 817 deletions(-)

Given that we can eliminate nearly 400 lines of code and one board file I think
it is worth it. I looked over the patch and it does look good so far. Will give
it a runtime test the next days. If that truns out well I'm fine to ack it.

regards
Stefan Schmidt


From baruch at tkos.co.il  Mon Jun  7 03:06:53 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Mon,  7 Jun 2010 10:06:53 +0300
Subject: [PATCHv5] rtc: driver for the DryIce block found in i.MX25 chips
Message-ID: <b434dc76f4ea6d09009e8b7087f860f4eed593b6.1275893468.git.baruch@tkos.co.il>

This driver is based on code from Freescale which accompanies their i.MX25 PDK
board, with some cleanup.

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
Cc: Alessandro Zummo <a.zummo at towertech.it>
---
Changes v4 -> v5:

Address the comments of Andrew Morton:

	* uninline functions
	* remove infinite loop
	* correctly handel wait_event_interruptible_timeout return value
	* use flush_work() instead of flush_scheduled_work()

Address the comments of Wan ZongShun:

	* don't disable interrupts when calling rtc_update_irq()
	* use platform_driver_probe instead of platform_driver_register
	* move platform_set_drvdata() call to a better place

Changes v3 -> v4:

	Merge in a patch fixing an "irq: nobody cared" race.

Changes v2 -> v3:

Add spaces around the '+' operator as suggested by Alessandro Zummo and Lothar 
Wa??mann.

Address other comments of Alessandro Zummo:

	* add implementation of the alarm_irq_enable rtc op
	* use devres in .probe
	* remove unneeded initializations

Changes v1 -> v2:

Address the comments of Alessandro Zummo:

	* remove the .ioctl implementation
	* implement .set_mmss instead of .set_time
	* reorder the .probe implementation
	* make sure not to have enabled interrupts when registering or 
	  unregistering the rtc device
	* add MODULE_AUTHOR() with my email

Address the comment of Lothar Wa??mann:

	* return PTR_ERR on clk_get failure

Slightly change MODULE_DESCRIPTION().
Use timeout which is independent of HZ for wait_event_interruptible_timeout().

 drivers/rtc/Kconfig     |   10 +
 drivers/rtc/Makefile    |    1 +
 drivers/rtc/rtc-imxdi.c |  519 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 530 insertions(+), 0 deletions(-)
 create mode 100644 drivers/rtc/rtc-imxdi.c

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 10ba12c..f7dab3b 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -537,6 +537,16 @@ config RTC_DRV_MSM6242
 	  This driver can also be built as a module. If so, the module
 	  will be called rtc-msm6242.
 
+config RTC_DRV_IMXDI
+	tristate "Freescale IMX DryIce Real Time Clock"
+	depends on ARCH_MX25
+	depends on RTC_CLASS
+	help
+	   Support for Freescale IMX DryIce RTC
+
+	   This driver can also be built as a module, if so, the module
+	   will be called "rtc-imxdi".
+
 config RTC_MXC
 	tristate "Freescale MXC Real Time Clock"
 	depends on ARCH_MXC
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 5adbba7..e0f6fd5 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_RTC_DRV_EFI)	+= rtc-efi.o
 obj-$(CONFIG_RTC_DRV_EP93XX)	+= rtc-ep93xx.o
 obj-$(CONFIG_RTC_DRV_FM3130)	+= rtc-fm3130.o
 obj-$(CONFIG_RTC_DRV_GENERIC)	+= rtc-generic.o
+obj-$(CONFIG_RTC_DRV_IMXDI)	+= rtc-imxdi.o
 obj-$(CONFIG_RTC_DRV_ISL1208)	+= rtc-isl1208.o
 obj-$(CONFIG_RTC_DRV_M41T80)	+= rtc-m41t80.o
 obj-$(CONFIG_RTC_DRV_M41T94)	+= rtc-m41t94.o
diff --git a/drivers/rtc/rtc-imxdi.c b/drivers/rtc/rtc-imxdi.c
new file mode 100644
index 0000000..2dd3c01
--- /dev/null
+++ b/drivers/rtc/rtc-imxdi.c
@@ -0,0 +1,519 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2010 Orex Computed Radiography
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/* based on rtc-mc13892.c */
+
+/*
+ * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
+ * to implement a Linux RTC. Times and alarms are truncated to seconds.
+ * Since the RTC framework performs API locking via rtc->ops_lock the
+ * only simultaneous accesses we need to deal with is updating DryIce
+ * registers while servicing an alarm.
+ *
+ * Note that reading the DSR (DryIce Status Register) automatically clears
+ * the WCF (Write Complete Flag). All DryIce writes are synchronized to the
+ * LP (Low Power) domain and set the WCF upon completion. Writes to the
+ * DIER (DryIce Interrupt Enable Register) are the only exception. These
+ * occur at normal bus speeds and do not set WCF.  Periodic interrupts are
+ * not supported by the hardware.
+ */
+
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+#include <linux/workqueue.h>
+
+/* DryIce Register Definitions */
+
+#define DTCMR     0x00           /* Time Counter MSB Reg */
+#define DTCLR     0x04           /* Time Counter LSB Reg */
+
+#define DCAMR     0x08           /* Clock Alarm MSB Reg */
+#define DCALR     0x0c           /* Clock Alarm LSB Reg */
+#define DCAMR_UNSET  0xFFFFFFFF  /* doomsday - 1 sec */
+
+#define DCR       0x10           /* Control Reg */
+#define DCR_TCE   (1 << 3)       /* Time Counter Enable */
+
+#define DSR       0x14           /* Status Reg */
+#define DSR_WBF   (1 << 10)      /* Write Busy Flag */
+#define DSR_WNF   (1 << 9)       /* Write Next Flag */
+#define DSR_WCF   (1 << 8)       /* Write Complete Flag */
+#define DSR_WEF   (1 << 7)       /* Write Error Flag */
+#define DSR_CAF   (1 << 4)       /* Clock Alarm Flag */
+#define DSR_NVF   (1 << 1)       /* Non-Valid Flag */
+#define DSR_SVF   (1 << 0)       /* Security Violation Flag */
+
+#define DIER      0x18           /* Interrupt Enable Reg */
+#define DIER_WNIE (1 << 9)       /* Write Next Interrupt Enable */
+#define DIER_WCIE (1 << 8)       /* Write Complete Interrupt Enable */
+#define DIER_WEIE (1 << 7)       /* Write Error Interrupt Enable */
+#define DIER_CAIE (1 << 4)       /* Clock Alarm Interrupt Enable */
+
+/**
+ * struct imxdi_dev - private imxdi rtc data
+ * @pdev: pionter to platform dev
+ * @rtc: pointer to rtc struct
+ * @ioaddr: IO registers pointer
+ * @irq: dryice normal interrupt
+ * @clk: input reference clock
+ * @dsr: copy of the DSR register
+ * @irq_lock: interrupt enable register (DIER) lock
+ * @write_wait: registers write complete queue
+ * @write_mutex: serialize registers write
+ * @work: schedule alarm work
+ */
+struct imxdi_dev {
+	struct platform_device *pdev;
+	struct rtc_device *rtc;
+	void __iomem *ioaddr;
+	int irq;
+	struct clk *clk;
+	u32 dsr;
+	spinlock_t irq_lock;
+	wait_queue_head_t write_wait;
+	struct mutex write_mutex;
+	struct work_struct work;
+};
+
+/*
+ * enable a dryice interrupt
+ */
+static void di_int_enable(struct imxdi_dev *imxdi, u32 intr)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&imxdi->irq_lock, flags);
+	__raw_writel(__raw_readl(imxdi->ioaddr + DIER) | intr,
+			imxdi->ioaddr + DIER);
+	spin_unlock_irqrestore(&imxdi->irq_lock, flags);
+}
+
+/*
+ * disable a dryice interrupt
+ */
+static void di_int_disable(struct imxdi_dev *imxdi, u32 intr)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&imxdi->irq_lock, flags);
+	__raw_writel(__raw_readl(imxdi->ioaddr + DIER) & ~intr,
+			imxdi->ioaddr + DIER);
+	spin_unlock_irqrestore(&imxdi->irq_lock, flags);
+}
+
+/*
+ * This function attempts to clear the dryice write-error flag.
+ *
+ * A dryice write error is similar to a bus fault and should not occur in
+ * normal operation.  Clearing the flag requires another write, so the root
+ * cause of the problem may need to be fixed before the flag can be cleared.
+ */
+static void clear_write_error(struct imxdi_dev *imxdi)
+{
+	int cnt;
+
+	dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n");
+
+	/* clear the write error flag */
+	__raw_writel(DSR_WEF, imxdi->ioaddr + DSR);
+
+	/* wait for it to take effect */
+	for (cnt = 0; cnt < 1000; cnt++) {
+		if ((__raw_readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
+			return;
+		udelay(10);
+	}
+	dev_err(&imxdi->pdev->dev,
+			"ERROR: Cannot clear write-error flag!\n");
+}
+
+/*
+ * Write a dryice register and wait until it completes.
+ *
+ * This function uses interrupts to determine when the
+ * write has completed.
+ */
+static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg)
+{
+	int ret;
+	int rc = 0;
+
+	/* serialize register writes */
+	mutex_lock(&imxdi->write_mutex);
+
+	/* enable the write-complete interrupt */
+	di_int_enable(imxdi, DIER_WCIE);
+
+	imxdi->dsr = 0;
+
+	/* do the register write */
+	__raw_writel(val, imxdi->ioaddr + reg);
+
+	/* wait for the write to finish */
+	ret = wait_event_interruptible_timeout(imxdi->write_wait,
+			imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));
+	if (ret < 0) {
+		rc = ret;
+		goto out;
+	} else if (ret == 0) {
+		dev_warn(&imxdi->pdev->dev,
+				"Write-wait timeout "
+				"val = 0x%08x reg = 0x%08x\n", val, reg);
+	}
+
+	/* check for write error */
+	if (imxdi->dsr & DSR_WEF) {
+		clear_write_error(imxdi);
+		rc = -EIO;
+	}
+
+out:
+	mutex_unlock(&imxdi->write_mutex);
+
+	return rc;
+}
+
+/*
+ * read the seconds portion of the current time from the dryice time counter
+ */
+static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
+	unsigned long now;
+
+	now = __raw_readl(imxdi->ioaddr + DTCMR);
+	rtc_time_to_tm(now, tm);
+
+	return 0;
+}
+
+/*
+ * set the seconds portion of dryice time counter and clear the
+ * fractional part.
+ */
+static int dryice_rtc_set_mmss(struct device *dev, unsigned long secs)
+{
+	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
+	int rc;
+
+	/* zero the fractional part first */
+	rc = di_write_wait(imxdi, 0, DTCLR);
+	if (rc == 0)
+		rc = di_write_wait(imxdi, secs, DTCMR);
+
+	return rc;
+}
+
+static int dryice_rtc_alarm_irq_enable(struct device *dev,
+		unsigned int enabled)
+{
+	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
+
+	if (enabled)
+		di_int_enable(imxdi, DIER_CAIE);
+	else
+		di_int_disable(imxdi, DIER_CAIE);
+
+	return 0;
+}
+
+/*
+ * read the seconds portion of the alarm register.
+ * the fractional part of the alarm register is always zero.
+ */
+static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
+{
+	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
+	u32 dcamr;
+
+	dcamr = __raw_readl(imxdi->ioaddr + DCAMR);
+	rtc_time_to_tm(dcamr, &alarm->time);
+
+	/* alarm is enabled if the interrupt is enabled */
+	alarm->enabled = (__raw_readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0;
+
+	/* don't allow the DSR read to mess up DSR_WCF */
+	mutex_lock(&imxdi->write_mutex);
+
+	/* alarm is pending if the alarm flag is set */
+	alarm->pending = (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;
+
+	mutex_unlock(&imxdi->write_mutex);
+
+	return 0;
+}
+
+/*
+ * set the seconds portion of dryice alarm register
+ */
+static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
+{
+	struct imxdi_dev *imxdi = dev_get_drvdata(dev);
+	unsigned long now;
+	unsigned long alarm_time;
+	int rc;
+
+	rc = rtc_tm_to_time(&alarm->time, &alarm_time);
+	if (rc)
+		return rc;
+
+	/* don't allow setting alarm in the past */
+	now = __raw_readl(imxdi->ioaddr + DTCMR);
+	if (alarm_time < now)
+		return -EINVAL;
+
+	/* write the new alarm time */
+	rc = di_write_wait(imxdi, (u32)alarm_time, DCAMR);
+	if (rc)
+		return rc;
+
+	if (alarm->enabled)
+		di_int_enable(imxdi, DIER_CAIE);  /* enable alarm intr */
+	else
+		di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */
+
+	return 0;
+}
+
+static struct rtc_class_ops dryice_rtc_ops = {
+	.read_time		= dryice_rtc_read_time,
+	.set_mmss		= dryice_rtc_set_mmss,
+	.alarm_irq_enable	= dryice_rtc_alarm_irq_enable,
+	.read_alarm		= dryice_rtc_read_alarm,
+	.set_alarm		= dryice_rtc_set_alarm,
+};
+
+/*
+ * dryice "normal" interrupt handler
+ */
+static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
+{
+	struct imxdi_dev *imxdi = dev_id;
+	u32 dsr, dier;
+	irqreturn_t rc = IRQ_NONE;
+
+	dier = __raw_readl(imxdi->ioaddr + DIER);
+
+	/* handle write complete and write error cases */
+	if ((dier & DIER_WCIE)) {
+		/*If the write wait queue is empty then there is no pending
+		  operations. It means the interrupt is for DryIce -Security.
+		  IRQ must be returned as none.*/
+		if (list_empty_careful(&imxdi->write_wait.task_list))
+			return rc;
+
+		/* DSR_WCF clears itself on DSR read */
+		dsr = __raw_readl(imxdi->ioaddr + DSR);
+		if ((dsr & (DSR_WCF | DSR_WEF))) {
+			/* mask the interrupt */
+			di_int_disable(imxdi, DIER_WCIE);
+
+			/* save the dsr value for the wait queue */
+			imxdi->dsr |= dsr;
+
+			wake_up_interruptible(&imxdi->write_wait);
+			rc = IRQ_HANDLED;
+		}
+	}
+
+	/* handle the alarm case */
+	if ((dier & DIER_CAIE)) {
+		/* DSR_WCF clears itself on DSR read */
+		dsr = __raw_readl(imxdi->ioaddr + DSR);
+		if (dsr & DSR_CAF) {
+			/* mask the interrupt */
+			di_int_disable(imxdi, DIER_CAIE);
+
+			/* finish alarm in user context */
+			schedule_work(&imxdi->work);
+			rc = IRQ_HANDLED;
+		}
+	}
+	return rc;
+}
+
+/*
+ * post the alarm event from user context so it can sleep
+ * on the write completion.
+ */
+static void dryice_work(struct work_struct *work)
+{
+	struct imxdi_dev *imxdi = container_of(work,
+			struct imxdi_dev, work);
+
+	/* dismiss the interrupt (ignore error) */
+	di_write_wait(imxdi, DSR_CAF, DSR);
+
+	/* pass the alarm event to the rtc framework. */
+	rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF);
+}
+
+/*
+ * probe for dryice rtc device
+ */
+static int dryice_rtc_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	struct imxdi_dev *imxdi;
+	int rc;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL);
+	if (!imxdi)
+		return -ENOMEM;
+
+	imxdi->pdev = pdev;
+
+	if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
+				pdev->name))
+		return -EBUSY;
+
+	imxdi->ioaddr = devm_ioremap(&pdev->dev, res->start,
+			resource_size(res));
+	if (imxdi->ioaddr == NULL)
+		return -ENOMEM;
+
+	imxdi->irq = platform_get_irq(pdev, 0);
+	if (imxdi->irq < 0)
+		return imxdi->irq;
+
+	init_waitqueue_head(&imxdi->write_wait);
+
+	INIT_WORK(&imxdi->work, dryice_work);
+
+	mutex_init(&imxdi->write_mutex);
+
+	imxdi->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(imxdi->clk))
+		return PTR_ERR(imxdi->clk);
+	clk_enable(imxdi->clk);
+
+	/*
+	 * Initialize dryice hardware
+	 */
+
+	/* mask all interrupts */
+	__raw_writel(0, imxdi->ioaddr + DIER);
+
+	rc = devm_request_irq(&pdev->dev, imxdi->irq, dryice_norm_irq,
+			IRQF_SHARED, pdev->name, imxdi);
+	if (rc) {
+		dev_warn(&pdev->dev, "interrupt not available.\n");
+		goto err;
+	}
+
+	/* put dryice into valid state */
+	if (__raw_readl(imxdi->ioaddr + DSR) & DSR_NVF) {
+		rc = di_write_wait(imxdi, DSR_NVF | DSR_SVF, DSR);
+		if (rc)
+			goto err;
+	}
+
+	/* initialize alarm */
+	rc = di_write_wait(imxdi, DCAMR_UNSET, DCAMR);
+	if (rc)
+		goto err;
+	rc = di_write_wait(imxdi, 0, DCALR);
+	if (rc)
+		goto err;
+
+	/* clear alarm flag */
+	if (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) {
+		rc = di_write_wait(imxdi, DSR_CAF, DSR);
+		if (rc)
+			goto err;
+	}
+
+	/* the timer won't count if it has never been written to */
+	if (__raw_readl(imxdi->ioaddr + DTCMR) == 0) {
+		rc = di_write_wait(imxdi, 0, DTCMR);
+		if (rc)
+			goto err;
+	}
+
+	/* start keeping time */
+	if (!(__raw_readl(imxdi->ioaddr + DCR) & DCR_TCE)) {
+		rc = di_write_wait(imxdi,
+				__raw_readl(imxdi->ioaddr + DCR) | DCR_TCE,
+				DCR);
+		if (rc)
+			goto err;
+	}
+
+	platform_set_drvdata(pdev, imxdi);
+	imxdi->rtc = rtc_device_register(pdev->name, &pdev->dev,
+				  &dryice_rtc_ops, THIS_MODULE);
+	if (IS_ERR(imxdi->rtc)) {
+		rc = PTR_ERR(imxdi->rtc);
+		goto err;
+	}
+
+	return 0;
+
+err:
+	clk_disable(imxdi->clk);
+	clk_put(imxdi->clk);
+
+	return rc;
+}
+
+static int __devexit dryice_rtc_remove(struct platform_device *pdev)
+{
+	struct imxdi_dev *imxdi = platform_get_drvdata(pdev);
+
+	flush_work(&imxdi->work);
+
+	/* mask all interrupts */
+	__raw_writel(0, imxdi->ioaddr + DIER);
+
+	rtc_device_unregister(imxdi->rtc);
+
+	clk_disable(imxdi->clk);
+	clk_put(imxdi->clk);
+
+	return 0;
+}
+
+static struct platform_driver dryice_rtc_driver = {
+	.driver = {
+		   .name = "imxdi_rtc",
+		   .owner = THIS_MODULE,
+		   },
+	.remove = __devexit_p(dryice_rtc_remove),
+};
+
+static int __init dryice_rtc_init(void)
+{
+	return platform_driver_probe(&dryice_rtc_driver, dryice_rtc_probe);
+}
+
+static void __exit dryice_rtc_exit(void)
+{
+	platform_driver_unregister(&dryice_rtc_driver);
+}
+
+module_init(dryice_rtc_init);
+module_exit(dryice_rtc_exit);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_AUTHOR("Baruch Siach <baruch at tkos.co.il>");
+MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)");
+MODULE_LICENSE("GPL");
-- 
1.7.1



From mcuos.com at gmail.com  Mon Jun  7 03:14:51 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Mon, 7 Jun 2010 15:14:51 +0800
Subject: [PATCHv5] rtc: driver for the DryIce block found in i.MX25 chips
In-Reply-To: <b434dc76f4ea6d09009e8b7087f860f4eed593b6.1275893468.git.baruch@tkos.co.il>
References: <b434dc76f4ea6d09009e8b7087f860f4eed593b6.1275893468.git.baruch@tkos.co.il>
Message-ID: <AANLkTinaOM9R2SFDaQQa0M-uH48DKbsfnbL5NTGArzxP@mail.gmail.com>

2010/6/7 Baruch Siach <baruch at tkos.co.il>:
> This driver is based on code from Freescale which accompanies their i.MX25 PDK
> board, with some cleanup.
>
> Signed-off-by: Baruch Siach <baruch at tkos.co.il>

Acked-by: Wan ZongShun <mcuos.com at gmail.com>

Thanks for your patch.

> Cc: Alessandro Zummo <a.zummo at towertech.it>
> ---
> Changes v4 -> v5:
>
> Address the comments of Andrew Morton:
>
> ? ? ? ?* uninline functions
> ? ? ? ?* remove infinite loop
> ? ? ? ?* correctly handel wait_event_interruptible_timeout return value
> ? ? ? ?* use flush_work() instead of flush_scheduled_work()
>
> Address the comments of Wan ZongShun:
>
> ? ? ? ?* don't disable interrupts when calling rtc_update_irq()
> ? ? ? ?* use platform_driver_probe instead of platform_driver_register
> ? ? ? ?* move platform_set_drvdata() call to a better place
>
> Changes v3 -> v4:
>
> ? ? ? ?Merge in a patch fixing an "irq: nobody cared" race.
>
> Changes v2 -> v3:
>
> Add spaces around the '+' operator as suggested by Alessandro Zummo and Lothar
> Wa?mann.
>
> Address other comments of Alessandro Zummo:
>
> ? ? ? ?* add implementation of the alarm_irq_enable rtc op
> ? ? ? ?* use devres in .probe
> ? ? ? ?* remove unneeded initializations
>
> Changes v1 -> v2:
>
> Address the comments of Alessandro Zummo:
>
> ? ? ? ?* remove the .ioctl implementation
> ? ? ? ?* implement .set_mmss instead of .set_time
> ? ? ? ?* reorder the .probe implementation
> ? ? ? ?* make sure not to have enabled interrupts when registering or
> ? ? ? ? ?unregistering the rtc device
> ? ? ? ?* add MODULE_AUTHOR() with my email
>
> Address the comment of Lothar Wa?mann:
>
> ? ? ? ?* return PTR_ERR on clk_get failure
>
> Slightly change MODULE_DESCRIPTION().
> Use timeout which is independent of HZ for wait_event_interruptible_timeout().
>
> ?drivers/rtc/Kconfig ? ? | ? 10 +
> ?drivers/rtc/Makefile ? ?| ? ?1 +
> ?drivers/rtc/rtc-imxdi.c | ?519 +++++++++++++++++++++++++++++++++++++++++++++++
> ?3 files changed, 530 insertions(+), 0 deletions(-)
> ?create mode 100644 drivers/rtc/rtc-imxdi.c
>
> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
> index 10ba12c..f7dab3b 100644
> --- a/drivers/rtc/Kconfig
> +++ b/drivers/rtc/Kconfig
> @@ -537,6 +537,16 @@ config RTC_DRV_MSM6242
> ? ? ? ? ?This driver can also be built as a module. If so, the module
> ? ? ? ? ?will be called rtc-msm6242.
>
> +config RTC_DRV_IMXDI
> + ? ? ? tristate "Freescale IMX DryIce Real Time Clock"
> + ? ? ? depends on ARCH_MX25
> + ? ? ? depends on RTC_CLASS
> + ? ? ? help
> + ? ? ? ? ?Support for Freescale IMX DryIce RTC
> +
> + ? ? ? ? ?This driver can also be built as a module, if so, the module
> + ? ? ? ? ?will be called "rtc-imxdi".
> +
> ?config RTC_MXC
> ? ? ? ?tristate "Freescale MXC Real Time Clock"
> ? ? ? ?depends on ARCH_MXC
> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
> index 5adbba7..e0f6fd5 100644
> --- a/drivers/rtc/Makefile
> +++ b/drivers/rtc/Makefile
> @@ -46,6 +46,7 @@ obj-$(CONFIG_RTC_DRV_EFI) ? ? += rtc-efi.o
> ?obj-$(CONFIG_RTC_DRV_EP93XX) ? += rtc-ep93xx.o
> ?obj-$(CONFIG_RTC_DRV_FM3130) ? += rtc-fm3130.o
> ?obj-$(CONFIG_RTC_DRV_GENERIC) ?+= rtc-generic.o
> +obj-$(CONFIG_RTC_DRV_IMXDI) ? ?+= rtc-imxdi.o
> ?obj-$(CONFIG_RTC_DRV_ISL1208) ?+= rtc-isl1208.o
> ?obj-$(CONFIG_RTC_DRV_M41T80) ? += rtc-m41t80.o
> ?obj-$(CONFIG_RTC_DRV_M41T94) ? += rtc-m41t94.o
> diff --git a/drivers/rtc/rtc-imxdi.c b/drivers/rtc/rtc-imxdi.c
> new file mode 100644
> index 0000000..2dd3c01
> --- /dev/null
> +++ b/drivers/rtc/rtc-imxdi.c
> @@ -0,0 +1,519 @@
> +/*
> + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + * Copyright 2010 Orex Computed Radiography
> + */
> +
> +/*
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +/* based on rtc-mc13892.c */
> +
> +/*
> + * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
> + * to implement a Linux RTC. Times and alarms are truncated to seconds.
> + * Since the RTC framework performs API locking via rtc->ops_lock the
> + * only simultaneous accesses we need to deal with is updating DryIce
> + * registers while servicing an alarm.
> + *
> + * Note that reading the DSR (DryIce Status Register) automatically clears
> + * the WCF (Write Complete Flag). All DryIce writes are synchronized to the
> + * LP (Low Power) domain and set the WCF upon completion. Writes to the
> + * DIER (DryIce Interrupt Enable Register) are the only exception. These
> + * occur at normal bus speeds and do not set WCF. ?Periodic interrupts are
> + * not supported by the hardware.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/rtc.h>
> +#include <linux/workqueue.h>
> +
> +/* DryIce Register Definitions */
> +
> +#define DTCMR ? ? 0x00 ? ? ? ? ? /* Time Counter MSB Reg */
> +#define DTCLR ? ? 0x04 ? ? ? ? ? /* Time Counter LSB Reg */
> +
> +#define DCAMR ? ? 0x08 ? ? ? ? ? /* Clock Alarm MSB Reg */
> +#define DCALR ? ? 0x0c ? ? ? ? ? /* Clock Alarm LSB Reg */
> +#define DCAMR_UNSET ?0xFFFFFFFF ?/* doomsday - 1 sec */
> +
> +#define DCR ? ? ? 0x10 ? ? ? ? ? /* Control Reg */
> +#define DCR_TCE ? (1 << 3) ? ? ? /* Time Counter Enable */
> +
> +#define DSR ? ? ? 0x14 ? ? ? ? ? /* Status Reg */
> +#define DSR_WBF ? (1 << 10) ? ? ?/* Write Busy Flag */
> +#define DSR_WNF ? (1 << 9) ? ? ? /* Write Next Flag */
> +#define DSR_WCF ? (1 << 8) ? ? ? /* Write Complete Flag */
> +#define DSR_WEF ? (1 << 7) ? ? ? /* Write Error Flag */
> +#define DSR_CAF ? (1 << 4) ? ? ? /* Clock Alarm Flag */
> +#define DSR_NVF ? (1 << 1) ? ? ? /* Non-Valid Flag */
> +#define DSR_SVF ? (1 << 0) ? ? ? /* Security Violation Flag */
> +
> +#define DIER ? ? ?0x18 ? ? ? ? ? /* Interrupt Enable Reg */
> +#define DIER_WNIE (1 << 9) ? ? ? /* Write Next Interrupt Enable */
> +#define DIER_WCIE (1 << 8) ? ? ? /* Write Complete Interrupt Enable */
> +#define DIER_WEIE (1 << 7) ? ? ? /* Write Error Interrupt Enable */
> +#define DIER_CAIE (1 << 4) ? ? ? /* Clock Alarm Interrupt Enable */
> +
> +/**
> + * struct imxdi_dev - private imxdi rtc data
> + * @pdev: pionter to platform dev
> + * @rtc: pointer to rtc struct
> + * @ioaddr: IO registers pointer
> + * @irq: dryice normal interrupt
> + * @clk: input reference clock
> + * @dsr: copy of the DSR register
> + * @irq_lock: interrupt enable register (DIER) lock
> + * @write_wait: registers write complete queue
> + * @write_mutex: serialize registers write
> + * @work: schedule alarm work
> + */
> +struct imxdi_dev {
> + ? ? ? struct platform_device *pdev;
> + ? ? ? struct rtc_device *rtc;
> + ? ? ? void __iomem *ioaddr;
> + ? ? ? int irq;
> + ? ? ? struct clk *clk;
> + ? ? ? u32 dsr;
> + ? ? ? spinlock_t irq_lock;
> + ? ? ? wait_queue_head_t write_wait;
> + ? ? ? struct mutex write_mutex;
> + ? ? ? struct work_struct work;
> +};
> +
> +/*
> + * enable a dryice interrupt
> + */
> +static void di_int_enable(struct imxdi_dev *imxdi, u32 intr)
> +{
> + ? ? ? unsigned long flags;
> +
> + ? ? ? spin_lock_irqsave(&imxdi->irq_lock, flags);
> + ? ? ? __raw_writel(__raw_readl(imxdi->ioaddr + DIER) | intr,
> + ? ? ? ? ? ? ? ? ? ? ? imxdi->ioaddr + DIER);
> + ? ? ? spin_unlock_irqrestore(&imxdi->irq_lock, flags);
> +}
> +
> +/*
> + * disable a dryice interrupt
> + */
> +static void di_int_disable(struct imxdi_dev *imxdi, u32 intr)
> +{
> + ? ? ? unsigned long flags;
> +
> + ? ? ? spin_lock_irqsave(&imxdi->irq_lock, flags);
> + ? ? ? __raw_writel(__raw_readl(imxdi->ioaddr + DIER) & ~intr,
> + ? ? ? ? ? ? ? ? ? ? ? imxdi->ioaddr + DIER);
> + ? ? ? spin_unlock_irqrestore(&imxdi->irq_lock, flags);
> +}
> +
> +/*
> + * This function attempts to clear the dryice write-error flag.
> + *
> + * A dryice write error is similar to a bus fault and should not occur in
> + * normal operation. ?Clearing the flag requires another write, so the root
> + * cause of the problem may need to be fixed before the flag can be cleared.
> + */
> +static void clear_write_error(struct imxdi_dev *imxdi)
> +{
> + ? ? ? int cnt;
> +
> + ? ? ? dev_warn(&imxdi->pdev->dev, "WARNING: Register write error!\n");
> +
> + ? ? ? /* clear the write error flag */
> + ? ? ? __raw_writel(DSR_WEF, imxdi->ioaddr + DSR);
> +
> + ? ? ? /* wait for it to take effect */
> + ? ? ? for (cnt = 0; cnt < 1000; cnt++) {
> + ? ? ? ? ? ? ? if ((__raw_readl(imxdi->ioaddr + DSR) & DSR_WEF) == 0)
> + ? ? ? ? ? ? ? ? ? ? ? return;
> + ? ? ? ? ? ? ? udelay(10);
> + ? ? ? }
> + ? ? ? dev_err(&imxdi->pdev->dev,
> + ? ? ? ? ? ? ? ? ? ? ? "ERROR: Cannot clear write-error flag!\n");
> +}
> +
> +/*
> + * Write a dryice register and wait until it completes.
> + *
> + * This function uses interrupts to determine when the
> + * write has completed.
> + */
> +static int di_write_wait(struct imxdi_dev *imxdi, u32 val, int reg)
> +{
> + ? ? ? int ret;
> + ? ? ? int rc = 0;
> +
> + ? ? ? /* serialize register writes */
> + ? ? ? mutex_lock(&imxdi->write_mutex);
> +
> + ? ? ? /* enable the write-complete interrupt */
> + ? ? ? di_int_enable(imxdi, DIER_WCIE);
> +
> + ? ? ? imxdi->dsr = 0;
> +
> + ? ? ? /* do the register write */
> + ? ? ? __raw_writel(val, imxdi->ioaddr + reg);
> +
> + ? ? ? /* wait for the write to finish */
> + ? ? ? ret = wait_event_interruptible_timeout(imxdi->write_wait,
> + ? ? ? ? ? ? ? ? ? ? ? imxdi->dsr & (DSR_WCF | DSR_WEF), msecs_to_jiffies(1));
> + ? ? ? if (ret < 0) {
> + ? ? ? ? ? ? ? rc = ret;
> + ? ? ? ? ? ? ? goto out;
> + ? ? ? } else if (ret == 0) {
> + ? ? ? ? ? ? ? dev_warn(&imxdi->pdev->dev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "Write-wait timeout "
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "val = 0x%08x reg = 0x%08x\n", val, reg);
> + ? ? ? }
> +
> + ? ? ? /* check for write error */
> + ? ? ? if (imxdi->dsr & DSR_WEF) {
> + ? ? ? ? ? ? ? clear_write_error(imxdi);
> + ? ? ? ? ? ? ? rc = -EIO;
> + ? ? ? }
> +
> +out:
> + ? ? ? mutex_unlock(&imxdi->write_mutex);
> +
> + ? ? ? return rc;
> +}
> +
> +/*
> + * read the seconds portion of the current time from the dryice time counter
> + */
> +static int dryice_rtc_read_time(struct device *dev, struct rtc_time *tm)
> +{
> + ? ? ? struct imxdi_dev *imxdi = dev_get_drvdata(dev);
> + ? ? ? unsigned long now;
> +
> + ? ? ? now = __raw_readl(imxdi->ioaddr + DTCMR);
> + ? ? ? rtc_time_to_tm(now, tm);
> +
> + ? ? ? return 0;
> +}
> +
> +/*
> + * set the seconds portion of dryice time counter and clear the
> + * fractional part.
> + */
> +static int dryice_rtc_set_mmss(struct device *dev, unsigned long secs)
> +{
> + ? ? ? struct imxdi_dev *imxdi = dev_get_drvdata(dev);
> + ? ? ? int rc;
> +
> + ? ? ? /* zero the fractional part first */
> + ? ? ? rc = di_write_wait(imxdi, 0, DTCLR);
> + ? ? ? if (rc == 0)
> + ? ? ? ? ? ? ? rc = di_write_wait(imxdi, secs, DTCMR);
> +
> + ? ? ? return rc;
> +}
> +
> +static int dryice_rtc_alarm_irq_enable(struct device *dev,
> + ? ? ? ? ? ? ? unsigned int enabled)
> +{
> + ? ? ? struct imxdi_dev *imxdi = dev_get_drvdata(dev);
> +
> + ? ? ? if (enabled)
> + ? ? ? ? ? ? ? di_int_enable(imxdi, DIER_CAIE);
> + ? ? ? else
> + ? ? ? ? ? ? ? di_int_disable(imxdi, DIER_CAIE);
> +
> + ? ? ? return 0;
> +}
> +
> +/*
> + * read the seconds portion of the alarm register.
> + * the fractional part of the alarm register is always zero.
> + */
> +static int dryice_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
> +{
> + ? ? ? struct imxdi_dev *imxdi = dev_get_drvdata(dev);
> + ? ? ? u32 dcamr;
> +
> + ? ? ? dcamr = __raw_readl(imxdi->ioaddr + DCAMR);
> + ? ? ? rtc_time_to_tm(dcamr, &alarm->time);
> +
> + ? ? ? /* alarm is enabled if the interrupt is enabled */
> + ? ? ? alarm->enabled = (__raw_readl(imxdi->ioaddr + DIER) & DIER_CAIE) != 0;
> +
> + ? ? ? /* don't allow the DSR read to mess up DSR_WCF */
> + ? ? ? mutex_lock(&imxdi->write_mutex);
> +
> + ? ? ? /* alarm is pending if the alarm flag is set */
> + ? ? ? alarm->pending = (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) != 0;
> +
> + ? ? ? mutex_unlock(&imxdi->write_mutex);
> +
> + ? ? ? return 0;
> +}
> +
> +/*
> + * set the seconds portion of dryice alarm register
> + */
> +static int dryice_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
> +{
> + ? ? ? struct imxdi_dev *imxdi = dev_get_drvdata(dev);
> + ? ? ? unsigned long now;
> + ? ? ? unsigned long alarm_time;
> + ? ? ? int rc;
> +
> + ? ? ? rc = rtc_tm_to_time(&alarm->time, &alarm_time);
> + ? ? ? if (rc)
> + ? ? ? ? ? ? ? return rc;
> +
> + ? ? ? /* don't allow setting alarm in the past */
> + ? ? ? now = __raw_readl(imxdi->ioaddr + DTCMR);
> + ? ? ? if (alarm_time < now)
> + ? ? ? ? ? ? ? return -EINVAL;
> +
> + ? ? ? /* write the new alarm time */
> + ? ? ? rc = di_write_wait(imxdi, (u32)alarm_time, DCAMR);
> + ? ? ? if (rc)
> + ? ? ? ? ? ? ? return rc;
> +
> + ? ? ? if (alarm->enabled)
> + ? ? ? ? ? ? ? di_int_enable(imxdi, DIER_CAIE); ?/* enable alarm intr */
> + ? ? ? else
> + ? ? ? ? ? ? ? di_int_disable(imxdi, DIER_CAIE); /* disable alarm intr */
> +
> + ? ? ? return 0;
> +}
> +
> +static struct rtc_class_ops dryice_rtc_ops = {
> + ? ? ? .read_time ? ? ? ? ? ? ?= dryice_rtc_read_time,
> + ? ? ? .set_mmss ? ? ? ? ? ? ? = dryice_rtc_set_mmss,
> + ? ? ? .alarm_irq_enable ? ? ? = dryice_rtc_alarm_irq_enable,
> + ? ? ? .read_alarm ? ? ? ? ? ? = dryice_rtc_read_alarm,
> + ? ? ? .set_alarm ? ? ? ? ? ? ?= dryice_rtc_set_alarm,
> +};
> +
> +/*
> + * dryice "normal" interrupt handler
> + */
> +static irqreturn_t dryice_norm_irq(int irq, void *dev_id)
> +{
> + ? ? ? struct imxdi_dev *imxdi = dev_id;
> + ? ? ? u32 dsr, dier;
> + ? ? ? irqreturn_t rc = IRQ_NONE;
> +
> + ? ? ? dier = __raw_readl(imxdi->ioaddr + DIER);
> +
> + ? ? ? /* handle write complete and write error cases */
> + ? ? ? if ((dier & DIER_WCIE)) {
> + ? ? ? ? ? ? ? /*If the write wait queue is empty then there is no pending
> + ? ? ? ? ? ? ? ? operations. It means the interrupt is for DryIce -Security.
> + ? ? ? ? ? ? ? ? IRQ must be returned as none.*/
> + ? ? ? ? ? ? ? if (list_empty_careful(&imxdi->write_wait.task_list))
> + ? ? ? ? ? ? ? ? ? ? ? return rc;
> +
> + ? ? ? ? ? ? ? /* DSR_WCF clears itself on DSR read */
> + ? ? ? ? ? ? ? dsr = __raw_readl(imxdi->ioaddr + DSR);
> + ? ? ? ? ? ? ? if ((dsr & (DSR_WCF | DSR_WEF))) {
> + ? ? ? ? ? ? ? ? ? ? ? /* mask the interrupt */
> + ? ? ? ? ? ? ? ? ? ? ? di_int_disable(imxdi, DIER_WCIE);
> +
> + ? ? ? ? ? ? ? ? ? ? ? /* save the dsr value for the wait queue */
> + ? ? ? ? ? ? ? ? ? ? ? imxdi->dsr |= dsr;
> +
> + ? ? ? ? ? ? ? ? ? ? ? wake_up_interruptible(&imxdi->write_wait);
> + ? ? ? ? ? ? ? ? ? ? ? rc = IRQ_HANDLED;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? /* handle the alarm case */
> + ? ? ? if ((dier & DIER_CAIE)) {
> + ? ? ? ? ? ? ? /* DSR_WCF clears itself on DSR read */
> + ? ? ? ? ? ? ? dsr = __raw_readl(imxdi->ioaddr + DSR);
> + ? ? ? ? ? ? ? if (dsr & DSR_CAF) {
> + ? ? ? ? ? ? ? ? ? ? ? /* mask the interrupt */
> + ? ? ? ? ? ? ? ? ? ? ? di_int_disable(imxdi, DIER_CAIE);
> +
> + ? ? ? ? ? ? ? ? ? ? ? /* finish alarm in user context */
> + ? ? ? ? ? ? ? ? ? ? ? schedule_work(&imxdi->work);
> + ? ? ? ? ? ? ? ? ? ? ? rc = IRQ_HANDLED;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> + ? ? ? return rc;
> +}
> +
> +/*
> + * post the alarm event from user context so it can sleep
> + * on the write completion.
> + */
> +static void dryice_work(struct work_struct *work)
> +{
> + ? ? ? struct imxdi_dev *imxdi = container_of(work,
> + ? ? ? ? ? ? ? ? ? ? ? struct imxdi_dev, work);
> +
> + ? ? ? /* dismiss the interrupt (ignore error) */
> + ? ? ? di_write_wait(imxdi, DSR_CAF, DSR);
> +
> + ? ? ? /* pass the alarm event to the rtc framework. */
> + ? ? ? rtc_update_irq(imxdi->rtc, 1, RTC_AF | RTC_IRQF);
> +}
> +
> +/*
> + * probe for dryice rtc device
> + */
> +static int dryice_rtc_probe(struct platform_device *pdev)
> +{
> + ? ? ? struct resource *res;
> + ? ? ? struct imxdi_dev *imxdi;
> + ? ? ? int rc;
> +
> + ? ? ? res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + ? ? ? if (!res)
> + ? ? ? ? ? ? ? return -ENODEV;
> +
> + ? ? ? imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL);
> + ? ? ? if (!imxdi)
> + ? ? ? ? ? ? ? return -ENOMEM;
> +
> + ? ? ? imxdi->pdev = pdev;
> +
> + ? ? ? if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? pdev->name))
> + ? ? ? ? ? ? ? return -EBUSY;
> +
> + ? ? ? imxdi->ioaddr = devm_ioremap(&pdev->dev, res->start,
> + ? ? ? ? ? ? ? ? ? ? ? resource_size(res));
> + ? ? ? if (imxdi->ioaddr == NULL)
> + ? ? ? ? ? ? ? return -ENOMEM;
> +
> + ? ? ? imxdi->irq = platform_get_irq(pdev, 0);
> + ? ? ? if (imxdi->irq < 0)
> + ? ? ? ? ? ? ? return imxdi->irq;
> +
> + ? ? ? init_waitqueue_head(&imxdi->write_wait);
> +
> + ? ? ? INIT_WORK(&imxdi->work, dryice_work);
> +
> + ? ? ? mutex_init(&imxdi->write_mutex);
> +
> + ? ? ? imxdi->clk = clk_get(&pdev->dev, NULL);
> + ? ? ? if (IS_ERR(imxdi->clk))
> + ? ? ? ? ? ? ? return PTR_ERR(imxdi->clk);
> + ? ? ? clk_enable(imxdi->clk);
> +
> + ? ? ? /*
> + ? ? ? ?* Initialize dryice hardware
> + ? ? ? ?*/
> +
> + ? ? ? /* mask all interrupts */
> + ? ? ? __raw_writel(0, imxdi->ioaddr + DIER);
> +
> + ? ? ? rc = devm_request_irq(&pdev->dev, imxdi->irq, dryice_norm_irq,
> + ? ? ? ? ? ? ? ? ? ? ? IRQF_SHARED, pdev->name, imxdi);
> + ? ? ? if (rc) {
> + ? ? ? ? ? ? ? dev_warn(&pdev->dev, "interrupt not available.\n");
> + ? ? ? ? ? ? ? goto err;
> + ? ? ? }
> +
> + ? ? ? /* put dryice into valid state */
> + ? ? ? if (__raw_readl(imxdi->ioaddr + DSR) & DSR_NVF) {
> + ? ? ? ? ? ? ? rc = di_write_wait(imxdi, DSR_NVF | DSR_SVF, DSR);
> + ? ? ? ? ? ? ? if (rc)
> + ? ? ? ? ? ? ? ? ? ? ? goto err;
> + ? ? ? }
> +
> + ? ? ? /* initialize alarm */
> + ? ? ? rc = di_write_wait(imxdi, DCAMR_UNSET, DCAMR);
> + ? ? ? if (rc)
> + ? ? ? ? ? ? ? goto err;
> + ? ? ? rc = di_write_wait(imxdi, 0, DCALR);
> + ? ? ? if (rc)
> + ? ? ? ? ? ? ? goto err;
> +
> + ? ? ? /* clear alarm flag */
> + ? ? ? if (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) {
> + ? ? ? ? ? ? ? rc = di_write_wait(imxdi, DSR_CAF, DSR);
> + ? ? ? ? ? ? ? if (rc)
> + ? ? ? ? ? ? ? ? ? ? ? goto err;
> + ? ? ? }
> +
> + ? ? ? /* the timer won't count if it has never been written to */
> + ? ? ? if (__raw_readl(imxdi->ioaddr + DTCMR) == 0) {
> + ? ? ? ? ? ? ? rc = di_write_wait(imxdi, 0, DTCMR);
> + ? ? ? ? ? ? ? if (rc)
> + ? ? ? ? ? ? ? ? ? ? ? goto err;
> + ? ? ? }
> +
> + ? ? ? /* start keeping time */
> + ? ? ? if (!(__raw_readl(imxdi->ioaddr + DCR) & DCR_TCE)) {
> + ? ? ? ? ? ? ? rc = di_write_wait(imxdi,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? __raw_readl(imxdi->ioaddr + DCR) | DCR_TCE,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? DCR);
> + ? ? ? ? ? ? ? if (rc)
> + ? ? ? ? ? ? ? ? ? ? ? goto err;
> + ? ? ? }
> +
> + ? ? ? platform_set_drvdata(pdev, imxdi);
> + ? ? ? imxdi->rtc = rtc_device_register(pdev->name, &pdev->dev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? &dryice_rtc_ops, THIS_MODULE);
> + ? ? ? if (IS_ERR(imxdi->rtc)) {
> + ? ? ? ? ? ? ? rc = PTR_ERR(imxdi->rtc);
> + ? ? ? ? ? ? ? goto err;
> + ? ? ? }
> +
> + ? ? ? return 0;
> +
> +err:
> + ? ? ? clk_disable(imxdi->clk);
> + ? ? ? clk_put(imxdi->clk);
> +
> + ? ? ? return rc;
> +}
> +
> +static int __devexit dryice_rtc_remove(struct platform_device *pdev)
> +{
> + ? ? ? struct imxdi_dev *imxdi = platform_get_drvdata(pdev);
> +
> + ? ? ? flush_work(&imxdi->work);
> +
> + ? ? ? /* mask all interrupts */
> + ? ? ? __raw_writel(0, imxdi->ioaddr + DIER);
> +
> + ? ? ? rtc_device_unregister(imxdi->rtc);
> +
> + ? ? ? clk_disable(imxdi->clk);
> + ? ? ? clk_put(imxdi->clk);
> +
> + ? ? ? return 0;
> +}
> +
> +static struct platform_driver dryice_rtc_driver = {
> + ? ? ? .driver = {
> + ? ? ? ? ? ? ? ? ?.name = "imxdi_rtc",
> + ? ? ? ? ? ? ? ? ?.owner = THIS_MODULE,
> + ? ? ? ? ? ? ? ? ?},
> + ? ? ? .remove = __devexit_p(dryice_rtc_remove),
> +};
> +
> +static int __init dryice_rtc_init(void)
> +{
> + ? ? ? return platform_driver_probe(&dryice_rtc_driver, dryice_rtc_probe);
> +}
> +
> +static void __exit dryice_rtc_exit(void)
> +{
> + ? ? ? platform_driver_unregister(&dryice_rtc_driver);
> +}
> +
> +module_init(dryice_rtc_init);
> +module_exit(dryice_rtc_exit);
> +
> +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
> +MODULE_AUTHOR("Baruch Siach <baruch at tkos.co.il>");
> +MODULE_DESCRIPTION("IMX DryIce Realtime Clock Driver (RTC)");
> +MODULE_LICENSE("GPL");
> --
> 1.7.1
>
>



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mail addr:linux-arm-kernel at lists.infradead.org
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you can subscribe it by sending me mail:
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From m.szyprowski at samsung.com  Mon Jun  7 03:30:36 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 07 Jun 2010 09:30:36 +0200
Subject: [PATCH v2 5/5] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <20100603010025.GA14272@trinity.fluff.org>
References: <1275188784-23395-1-git-send-email-jy0922.shim@samsung.com>
	<1275188784-23395-5-git-send-email-jy0922.shim@samsung.com>
	<20100530034250.GK7248@trinity.fluff.org>
	<4C01EB2E.4020600@samsung.com>
	<20100603010025.GA14272@trinity.fluff.org>
Message-ID: <000b01cb0613$5545bc90$ffd135b0$%szyprowski@samsung.com>

Hello,

On Thursday, June 03, 2010 3:00 AM Ben Dooks wrote:

> > >> +	keypad->clk = clk_get(&pdev->dev, "keypad");
> 
> I'm going to get rid of this practice, it should be clk_get(&pdev->dev,
> NULL),
> see up-comming clock changes.

Good idea, but how do you want to handle some special/additional clocks?
Like for example mmc_bus or fimc_sclk clocks?

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center




From tony at atomide.com  Mon Jun  7 03:41:48 2010
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 7 Jun 2010 10:41:48 +0300
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <loom.20100604T165709-423@post.gmane.org>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<201006040337.10593.marek.vasut@gmail.com>
	<201006040350.36944.marek.vasut@gmail.com>
	<201006040353.35816.marek.vasut@gmail.com>
	<20100604060338.GH6499@atomide.com>
	<loom.20100604T165709-423@post.gmane.org>
Message-ID: <20100607074147.GB15515@atomide.com>

* Cory Maccarrone <darkstar6262 at gmail.com> [100604 18:05]:
> Tony Lindgren <tony <at> atomide.com> writes:
> 
> All the new omap7xx boards I plan to submit in the future should be able to work
> fine in a single defconfig.  That's how I build now with my development tree.
> I'd be perfectly happy to see my htcherald_defconfig get wrapped into a more
> generic omap1_defconfig.

OK. Do you want to take a look at fixing the omap1 entry-macro.S in a similar
way to omap2 entry-macro.S so it works on 7xx too? See the ifdef MULTI_OMAP2
in entry-macro.S. 15xx is ARM925 based, so that's easy to detect. But for
detecting between ARM926 based 7xx and 16xx you would have to use some other
register.
 
> They might even be generic enough that I won't need separate board files for
> them -- I'll have to see when I get to that point.

OK

Regards,

Tony


From benjamin.zores at alcatel-lucent.com  Mon Jun  7 04:04:08 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Mon, 07 Jun 2010 10:04:08 +0200
Subject: [PATCH 3/3 v3] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <1275819882-8373-1-git-send-email-saeed@marvell.com>
References: <alpine.LFD.2.00.1006031224180.24526@xanadu.home>
	<1275819882-8373-1-git-send-email-saeed@marvell.com>
Message-ID: <4C0CA7F8.3080506@alcatel-lucent.com>

On 06/06/2010 12:24, Saeed Bishara wrote:
> This patch extens the kirkwood's PCIe support up to 2 controllers as in the 6282 devices.
>
> diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
> index 39bdf4b..c428348 100644
> --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
> +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
> @@ -74,9 +74,15 @@ static void __init db88f6281_init(void)
>
>   static int __init db88f6281_pci_init(void)
>   {
> -	if (machine_is_db88f6281_bp())
> -		kirkwood_pcie_init();
> +	if (machine_is_db88f6281_bp()) {
> +		u32 dev, rev;
>
> +		kirkwood_pcie_id(&dev,&rev);
> +		if (dev == MV88F6282_DEV_ID)
> +			kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
> +		else
> +			kirkwood_pcie_init(KW_PCIE0);
> +	}
>   	return 0;
>    

This is still not likely to be possible: I don't think a given board can 
have 2 different SoCs.

> +#define CGC_PEX1		(1<<  18)
>   #define CGC_GE1			(1<<  19)
>   #define CGC_TDM			(1<<  20)
>   #define CGC_RESERVED		((1<<  18) | (0x6<<  21))
>    

(1 << 18) is no longer reserved.

Except from that you still miss the mapping definition and phy 
initialization in common.c

See 
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/017176.html 
for details.

Ben



From mike at compulab.co.il  Mon Jun  7 04:10:45 2010
From: mike at compulab.co.il (Mike Rapoport)
Date: Mon, 07 Jun 2010 11:10:45 +0300
Subject: [PATCH 01/10] [ARM] tegra: initial tegra support
In-Reply-To: <1275635441-17378-2-git-send-email-olof@lixom.net>
References: <3478yvr76gerav> <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
Message-ID: <4C0CA985.1020704@compulab.co.il>

Olof Johansson wrote:
> From: Erik Gilling <konkers at android.com>
> 
> v2: Fixes from Mike Rapoport
> 	- remove unused header files (mach/dma.h and mach/nand.h)
> 	- remove tegra 1 references from Makefile.boot
> 
> v2: fixes from Russell King
> 	- remove mach/io.h include from mach/iomap.h
> 	- fix whitespace in Kconfig
> 
> v2: from Colin Cross
> 	- fix invalid immediate in debug-macro.S
> 
> Signed-off-by: Colin Cross <ccross at android.com>
> Signed-off-by: Erik Gilling <konkers at android.com>
> Signed-off-by: Olof Johansson <olof at lixom.net>
> ---
>  arch/arm/Kconfig                               |   13 ++
>  arch/arm/Makefile                              |    1 +
>  arch/arm/mach-tegra/Kconfig                    |   53 ++++++
>  arch/arm/mach-tegra/Makefile                   |    2 +
>  arch/arm/mach-tegra/Makefile.boot              |    3 +
>  arch/arm/mach-tegra/board.h                    |   32 ++++
>  arch/arm/mach-tegra/common.c                   |   44 +++++
>  arch/arm/mach-tegra/include/mach/barriers.h    |   30 ++++
>  arch/arm/mach-tegra/include/mach/debug-macro.S |   46 ++++++
>  arch/arm/mach-tegra/include/mach/entry-macro.S |  118 ++++++++++++++
>  arch/arm/mach-tegra/include/mach/hardware.h    |   24 +++
>  arch/arm/mach-tegra/include/mach/io.h          |   79 +++++++++
>  arch/arm/mach-tegra/include/mach/iomap.h       |  203 ++++++++++++++++++++++++
>  arch/arm/mach-tegra/include/mach/memory.h      |   28 ++++
>  arch/arm/mach-tegra/include/mach/system.h      |   39 +++++
>  arch/arm/mach-tegra/include/mach/timex.h       |   26 +++
>  arch/arm/mach-tegra/include/mach/uncompress.h  |   78 +++++++++
>  arch/arm/mach-tegra/include/mach/vmalloc.h     |   28 ++++
>  arch/arm/mach-tegra/io.c                       |   78 +++++++++
>  arch/arm/mm/Kconfig                            |    2 +-
>  20 files changed, 926 insertions(+), 1 deletions(-)
>  create mode 100644 arch/arm/mach-tegra/Kconfig
>  create mode 100644 arch/arm/mach-tegra/Makefile
>  create mode 100644 arch/arm/mach-tegra/Makefile.boot
>  create mode 100644 arch/arm/mach-tegra/board.h
>  create mode 100644 arch/arm/mach-tegra/common.c
>  create mode 100644 arch/arm/mach-tegra/include/mach/barriers.h
>  create mode 100644 arch/arm/mach-tegra/include/mach/debug-macro.S
>  create mode 100644 arch/arm/mach-tegra/include/mach/entry-macro.S
>  create mode 100644 arch/arm/mach-tegra/include/mach/hardware.h
>  create mode 100644 arch/arm/mach-tegra/include/mach/io.h
>  create mode 100644 arch/arm/mach-tegra/include/mach/iomap.h
>  create mode 100644 arch/arm/mach-tegra/include/mach/memory.h
>  create mode 100644 arch/arm/mach-tegra/include/mach/system.h
>  create mode 100644 arch/arm/mach-tegra/include/mach/timex.h
>  create mode 100644 arch/arm/mach-tegra/include/mach/uncompress.h
>  create mode 100644 arch/arm/mach-tegra/include/mach/vmalloc.h
>  create mode 100644 arch/arm/mach-tegra/io.c
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 92622eb..388f371 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -575,6 +575,17 @@ config ARCH_NUC93X
>  	  Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
>  	  low-power and high performance MPEG-4/JPEG multimedia controller chip.
>  
> +config ARCH_TEGRA
> +	bool "NVIDIA Tegra"
> +	select GENERIC_TIME
> +	select GENERIC_CLOCKEVENTS
> +	select GENERIC_GPIO
> +	select HAVE_CLK
> +	select ARCH_HAS_BARRIERS if CACHE_L2X0
> +	help
> +	  This enables support for NVIDIA Tegra based systems (Tegra APX,
> +	  Tegra 6xx and Tegra 2 series).
> +
>  config ARCH_PNX4008
>  	bool "Philips Nexperia PNX4008 Mobile"
>  	select CPU_ARM926T
> @@ -914,6 +925,8 @@ source "arch/arm/mach-shmobile/Kconfig"
>  
>  source "arch/arm/plat-stmp3xxx/Kconfig"
>  
> +source "arch/arm/mach-tegra/Kconfig"
> +
>  source "arch/arm/mach-u300/Kconfig"
>  
>  source "arch/arm/mach-ux500/Kconfig"
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index ed820e7..ddc6cb6 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -172,6 +172,7 @@ machine-$(CONFIG_ARCH_SHARK)		:= shark
>  machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile
>  machine-$(CONFIG_ARCH_STMP378X)		:= stmp378x
>  machine-$(CONFIG_ARCH_STMP37XX)		:= stmp37xx
> +machine-$(CONFIG_ARCH_TEGRA)		:= tegra
>  machine-$(CONFIG_ARCH_U300)		:= u300
>  machine-$(CONFIG_ARCH_U8500)		:= ux500
>  machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
> diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
> new file mode 100644
> index 0000000..64ab14f
> --- /dev/null
> +++ b/arch/arm/mach-tegra/Kconfig
> @@ -0,0 +1,53 @@
> +if ARCH_TEGRA
> +
> +comment "NVIDIA Tegra options"
> +
> +choice
> +	prompt "Select Tegra processor family for target system"
> +
> +config ARCH_TEGRA_2x_SOC
> +	bool "Tegra 2 family"
> +	select CPU_V7
> +	select ARM_GIC
> +	help
> +	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
> +	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
> +
> +endchoice
> +
> +
> +choice
> +	prompt "Select Tegra-based product"

Maybe we'd aim to support multiple boards in the single from the 
beginning and convert the "choice" to "comment"?

> +config MACH_HARMONY
> +       bool "Harmony board"
> +       help
> +         Support for nVidia Harmony development platform
> +
> +endchoice
> +
> +choice
> +        prompt "Low-level debug console UART"
> +        default TEGRA_DEBUG_UART_NONE
> +
> +config TEGRA_DEBUG_UART_NONE
> +        bool "None"
> +
> +config TEGRA_DEBUG_UARTA
> +        bool "UART-A"
> +
> +config TEGRA_DEBUG_UARTB
> +        bool "UART-B"
> +
> +config TEGRA_DEBUG_UARTC
> +        bool "UART-C"
> +
> +config TEGRA_DEBUG_UARTD
> +        bool "UART-D"
> +
> +config TEGRA_DEBUG_UARTE
> +        bool "UART-E"
> +
> +endchoice
> +
> +endif
> diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
> new file mode 100644
> index 0000000..81f003d
> --- /dev/null
> +++ b/arch/arm/mach-tegra/Makefile
> @@ -0,0 +1,2 @@
> +obj-y                                   += common.o
> +obj-y                                   += io.o
> diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
> new file mode 100644
> index 0000000..db52d61
> --- /dev/null
> +++ b/arch/arm/mach-tegra/Makefile.boot
> @@ -0,0 +1,3 @@
> +zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00008000
> +params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00000100
> +initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00800000
> diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
> new file mode 100644
> index 0000000..3d06354
> --- /dev/null
> +++ b/arch/arm/mach-tegra/board.h
> @@ -0,0 +1,32 @@
> +/*
> + * arch/arm/mach-tegra/board.h
> + *
> + * Copyright (C) 2010 Google, Inc.
> + *
> + * Author:
> + *	Colin Cross <ccross at google.com>
> + *	Erik Gilling <konkers at google.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __MACH_TEGRA_BOARD_H
> +#define __MACH_TEGRA_BOARD_H
> +
> +#include <linux/types.h>
> +
> +void __init tegra_common_init(void);
> +void __init tegra_map_common_io(void);
> +void __init tegra_init_irq(void);
> +void __init tegra_init_clock(void);
> +
> +extern struct sys_timer tegra_timer;
> +#endif
> diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
> new file mode 100644
> index 0000000..20875ee
> --- /dev/null
> +++ b/arch/arm/mach-tegra/common.c
> @@ -0,0 +1,44 @@
> +/*
> + * arch/arm/mach-tegra/board-harmony.c
> + *
> + * Copyright (C) 2010 Google, Inc.
> + *
> + * Author:
> + *	Colin Cross <ccross at android.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/init.h>
> +#include <linux/io.h>
> +
> +#include <asm/hardware/cache-l2x0.h>
> +
> +#include <mach/iomap.h>
> +
> +#include "board.h"
> +
> +void __init tegra_init_cache(void)
> +{
> +#ifdef CONFIG_CACHE_L2X0
> +	void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
> +
> +	writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
> +	writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
> +
> +	l2x0_init(p, 0x6C080001, 0x8200c3fe);
> +#endif
> +}
> +
> +void __init tegra_common_init(void)
> +{
> +	tegra_init_cache();
> +}
> diff --git a/arch/arm/mach-tegra/include/mach/barriers.h b/arch/arm/mach-tegra/include/mach/barriers.h
> new file mode 100644
> index 0000000..cc11517
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/barriers.h
> @@ -0,0 +1,30 @@
> +/*
> + * arch/arm/mach-realview/include/mach/barriers.h
> + *
> + * Copyright (C) 2010 ARM Ltd.
> + * Written by Catalin Marinas <catalin.marinas at arm.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + */
> +
> +#ifndef __MACH_BARRIERS_H
> +#define __MACH_BARRIERS_H
> +
> +#include <asm/outercache.h>
> +
> +#define rmb()		dmb()
> +#define wmb()		do { dsb(); outer_sync(); } while (0)
> +#define mb()		wmb()
> +
> +#endif	/* __MACH_BARRIERS_H */
> diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
> new file mode 100644
> index 0000000..55a3956
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
> @@ -0,0 +1,46 @@
> +/*
> + * arch/arm/mach-tegra/include/mach/debug-macro.S
> + *
> + * Copyright (C) 2010 Google, Inc.
> + *
> + * Author:
> + *	Colin Cross <ccross at google.com>
> + *	Erik Gilling <konkers at google.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <mach/io.h>
> +
> +	.macro  addruart,rx, tmp
> +        mrc     p15, 0, \rx, c1, c0
> +        tst     \rx, #1                 @ MMU enabled?
> +        ldreq   \rx, =IO_APB_PHYS       @ physical
> +        ldrne   \rx, =IO_APB_VIRT        @ virtual
> +#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
> +#error "A debug UART must be selected in the kernel config to use DEBUG_LL"
> +#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
> +        orr     \rx, \rx, #0x6000
> +#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
> +	ldr	\tmp, =0x6040
> +        orr     \rx, \rx, \tmp
> +#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
> +        orr     \rx, \rx, #0x6200
> +#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
> +        orr     \rx, \rx, #0x6300
> +#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
> +        orr     \rx, \rx, #0x6400
> +#endif
> +	.endm
> +
> +#define UART_SHIFT	2
> +#include <asm/hardware/debug-8250.S>
> +
> diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
> new file mode 100644
> index 0000000..2ba9e5c
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
> @@ -0,0 +1,118 @@
> +/* arch/arm/mach-tegra/include/mach/entry-macro.S
> + *
> + * Copyright (C) 2009 Palm, Inc.
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +#include <mach/iomap.h>
> +#include <mach/io.h>
> +
> +#if defined(CONFIG_ARM_GIC)
> +
> +#include <asm/hardware/gic.h>
> +
> +	/* Uses the GIC interrupt controller built into the cpu */
> +#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
> +
> +	.macro	disable_fiq
> +	.endm
> +
> +	.macro	get_irqnr_preamble, base, tmp
> +	movw \base, #(ICTRL_BASE & 0x0000ffff)
> +	movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
> +	.endm
> +
> +	.macro  arch_ret_to_user, tmp1, tmp2
> +	.endm
> +
> +	/*
> +	 * The interrupt numbering scheme is defined in the
> +	 * interrupt controller spec.  To wit:
> +	 *
> +	 * Interrupts 0-15 are IPI
> +	 * 16-28 are reserved
> +	 * 29-31 are local.  We allow 30 to be used for the watchdog.
> +	 * 32-1020 are global
> +	 * 1021-1022 are reserved
> +	 * 1023 is "spurious" (no interrupt)
> +	 *
> +	 * For now, we ignore all local interrupts so only return an interrupt
> +	 * if it's between 30 and 1020.  The test_for_ipi routine below will
> +	 * pick up on IPIs.
> +	 *
> +	 * A simple read from the controller will tell us the number of the
> +	 * highest priority enabled interrupt.  We then just need to check
> +	 * whether it is in the valid range for an IRQ (30-1020 inclusive).
> +	 */
> +
> +	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
> +
> +	/* bits 12-10 = src CPU, 9-0 = int # */
> +	ldr     \irqstat, [\base, #GIC_CPU_INTACK]
> +
> +	ldr		\tmp, =1021
> +
> +	bic     \irqnr, \irqstat, #0x1c00
> +
> +	cmp     \irqnr, #29
> +	cmpcc	\irqnr, \irqnr
> +	cmpne	\irqnr, \tmp
> +	cmpcs	\irqnr, \irqnr
> +
> +	.endm
> +
> +	/* We assume that irqstat (the raw value of the IRQ acknowledge
> +	 * register) is preserved from the macro above.
> +	 * If there is an IPI, we immediately signal end of interrupt on the
> +	 * controller, since this requires the original irqstat value which
> +	 * we won't easily be able to recreate later.
> +	 */
> +
> +	.macro test_for_ipi, irqnr, irqstat, base, tmp
> +	bic	\irqnr, \irqstat, #0x1c00
> +	cmp	\irqnr, #16
> +	strcc	\irqstat, [\base, #GIC_CPU_EOI]
> +	cmpcs	\irqnr, \irqnr
> +	.endm
> +
> +	/* As above, this assumes that irqstat and base are preserved.. */
> +
> +	.macro test_for_ltirq, irqnr, irqstat, base, tmp
> +	bic	\irqnr, \irqstat, #0x1c00
> +	mov 	\tmp, #0
> +	cmp	\irqnr, #29
> +	moveq	\tmp, #1
> +	streq	\irqstat, [\base, #GIC_CPU_EOI]
> +	cmp	\tmp, #0
> +	.endm
> +
> +#else
> +	/* legacy interrupt controller for AP16 */
> +	.macro	disable_fiq
> +	.endm
> +
> +	.macro	get_irqnr_preamble, base, tmp
> +	@ enable imprecise aborts
> +	cpsie	a
> +	@ EVP base at 0xf010f000
> +	mov \base, #0xf0000000
> +	orr \base, #0x00100000
> +	orr \base, #0x0000f000
> +	.endm
> +
> +	.macro	arch_ret_to_user, tmp1, tmp2
> +	.endm
> +
> +	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
> +	ldr \irqnr, [\base, #0x20]	@ EVT_IRQ_STS
> +	cmp \irqnr, #0x80
> +	.endm
> +#endif
> diff --git a/arch/arm/mach-tegra/include/mach/hardware.h b/arch/arm/mach-tegra/include/mach/hardware.h
> new file mode 100644
> index 0000000..6014edf
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/hardware.h
> @@ -0,0 +1,24 @@
> +/*
> + * arch/arm/mach-tegra/include/mach/hardware.h
> + *
> + * Copyright (C) 2010 Google, Inc.
> + *
> + * Author:
> + *	Colin Cross <ccross at google.com>
> + *	Erik Gilling <konkers at google.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __MACH_TEGRA_HARDWARE_H
> +#define __MACH_TEGRA_HARDWARE_H
> +
> +#endif
> diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
> new file mode 100644
> index 0000000..35edfc3
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/io.h
> @@ -0,0 +1,79 @@
> +/*
> + * arch/arm/mach-tegra/include/mach/io.h
> + *
> + * Copyright (C) 2010 Google, Inc.
> + *
> + * Author:
> + *	Colin Cross <ccross at google.com>
> + *	Erik Gilling <konkers at google.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __MACH_TEGRA_IO_H
> +#define __MACH_TEGRA_IO_H
> +
> +#define IO_SPACE_LIMIT 0xffffffff
> +
> +/* On TEGRA, many peripherals are very closely packed in
> + * two 256MB io windows (that actually only use about 64KB
> + * at the start of each).
> + *
> + * We will just map the first 1MB of each window (to minimize
> + * pt entries needed) and provide a macro to transform physical
> + * io addresses to an appropriate void __iomem *.
> + *
> + */
> +
> +#define IO_CPU_PHYS     0x50040000
> +#define IO_CPU_VIRT     0xFE000000
> +#define IO_CPU_SIZE	SZ_16K
> +
> +#define IO_PPSB_PHYS	0x60000000
> +#define IO_PPSB_VIRT	0xFE200000
> +#define IO_PPSB_SIZE	SZ_1M
> +
> +#define IO_APB_PHYS	0x70000000
> +#define IO_APB_VIRT	0xFE300000
> +#define IO_APB_SIZE	SZ_1M
> +
> +#define IO_TO_VIRT_BETWEEN(p, st, sz)	((p) >= (st) && (p) < ((st) + (sz)))
> +#define IO_TO_VIRT_XLATE(p, pst, vst)	(((p) - (pst) + (vst)))
> +
> +#define IO_TO_VIRT(n) ( \
> +	IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ?		\
> +		IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) :	\
> +	IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ?		\
> +		IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) :	\
> +	IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ?		\
> +		IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :	\
> +	0)
> +
> +#ifndef __ASSEMBLER__
> +
> +#define __arch_ioremap(p, s, t)	tegra_ioremap(p, s, t)
> +#define __arch_iounmap(v)	tegra_iounmap(v)
> +
> +void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
> +void tegra_iounmap(volatile void __iomem *addr);
> +
> +#define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n))
> +
> +static inline void __iomem *__io(unsigned long addr)
> +{
> +	return (void __iomem *)addr;
> +}
> +#define __io(a)         __io(a)
> +#define __mem_pci(a)    (a)
> +
> +#endif
> +
> +#endif
> diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
> new file mode 100644
> index 0000000..1741f7d
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/iomap.h
> @@ -0,0 +1,203 @@
> +/*
> + * arch/arm/mach-tegra/include/mach/iomap.h
> + *
> + * Copyright (C) 2010 Google, Inc.
> + *
> + * Author:
> + *	Colin Cross <ccross at google.com>
> + *	Erik Gilling <konkers at google.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __MACH_TEGRA_IOMAP_H
> +#define __MACH_TEGRA_IOMAP_H
> +
> +#include <asm/sizes.h>
> +
> +#define TEGRA_ARM_PERIF_BASE		0x50040000
> +#define TEGRA_ARM_PERIF_SIZE		SZ_8K
> +
> +#define TEGRA_ARM_INT_DIST_BASE		0x50041000
> +#define TEGRA_ARM_INT_DIST_SIZE		SZ_4K
> +
> +#define TEGRA_DISPLAY_BASE		0x54200000
> +#define TEGRA_DISPLAY_SIZE		SZ_256K
> +
> +#define TEGRA_DISPLAY2_BASE		0x54240000
> +#define TEGRA_DISPLAY2_SIZE		SZ_256K
> +
> +#define TEGRA_PRIMARY_ICTLR_BASE	0x60004000
> +#define TEGRA_PRIMARY_ICTLR_SIZE	SZ_64
> +
> +#define TEGRA_SECONDARY_ICTLR_BASE	0x60004100
> +#define TEGRA_SECONDARY_ICTLR_SIZE	SZ_64
> +
> +#define TEGRA_TERTIARY_ICTLR_BASE	0x60004200
> +#define TEGRA_TERTIARY_ICTLR_SIZE	SZ_64
> +
> +#define TEGRA_QUATERNARY_ICTLR_BASE	0x60004300
> +#define TEGRA_QUATERNARY_ICTLR_SIZE	SZ_64
> +
> +#define TEGRA_TMR1_BASE			0x60005000
> +#define TEGRA_TMR1_SIZE			SZ_8
> +
> +#define TEGRA_TMR2_BASE			0x60005008
> +#define TEGRA_TMR2_SIZE			SZ_8
> +
> +#define TEGRA_TMRUS_BASE		0x60005010
> +#define TEGRA_TMRUS_SIZE		SZ_64
> +
> +#define TEGRA_TMR3_BASE			0x60005050
> +#define TEGRA_TMR3_SIZE			SZ_8
> +
> +#define TEGRA_TMR4_BASE			0x60005058
> +#define TEGRA_TMR4_SIZE			SZ_8
> +
> +#define TEGRA_CLK_RESET_BASE		0x60006000
> +#define TEGRA_CLK_RESET_SIZE		SZ_4K
> +
> +#define TEGRA_FLOW_CTRL_BASE		0x60007000
> +#define TEGRA_FLOW_CTRL_SIZE		20
> +
> +#define TEGRA_STATMON_BASE		0x6000C4000
> +#define TEGRA_STATMON_SIZE		SZ_1K
> +
> +#define TEGRA_GPIO_BASE			0x6000D000
> +#define TEGRA_GPIO_SIZE			SZ_4K
> +
> +#define TEGRA_EXCEPTION_VECTORS_BASE    0x6000F000
> +#define TEGRA_EXCEPTION_VECTORS_SIZE    SZ_4K
> +
> +#define TEGRA_APB_MISC_BASE		0x70000000
> +#define TEGRA_APB_MISC_SIZE		SZ_4K
> +
> +#define TEGRA_AC97_BASE			0x70002000
> +#define TEGRA_AC97_SIZE			SZ_512
> +
> +#define TEGRA_SPDIF_BASE		0x70002400
> +#define TEGRA_SPDIF_SIZE		SZ_512
> +
> +#define TEGRA_I2S1_BASE			0x70002800
> +#define TEGRA_I2S1_SIZE			SZ_256
> +
> +#define TEGRA_I2S2_BASE			0x70002A00
> +#define TEGRA_I2S2_SIZE			SZ_256
> +
> +#define TEGRA_UARTA_BASE		0x70006000
> +#define TEGRA_UARTA_SIZE		SZ_64
> +
> +#define TEGRA_UARTB_BASE		0x70006040
> +#define TEGRA_UARTB_SIZE		SZ_64
> +
> +#define TEGRA_UARTC_BASE		0x70006200
> +#define TEGRA_UARTC_SIZE		SZ_256
> +
> +#define TEGRA_UARTD_BASE		0x70006300
> +#define TEGRA_UARTD_SIZE		SZ_256
> +
> +#define TEGRA_UARTE_BASE		0x70006400
> +#define TEGRA_UARTE_SIZE		SZ_256
> +
> +#define TEGRA_NAND_BASE			0x70008000
> +#define TEGRA_NAND_SIZE			SZ_256
> +
> +#define TEGRA_HSMMC_BASE		0x70008500
> +#define TEGRA_HSMMC_SIZE		SZ_256
> +
> +#define TEGRA_SNOR_BASE			0x70009000
> +#define TEGRA_SNOR_SIZE			SZ_4K
> +
> +#define TEGRA_PWFM_BASE			0x7000A000
> +#define TEGRA_PWFM_SIZE			SZ_256
> +
> +#define TEGRA_MIPI_BASE			0x7000B000
> +#define TEGRA_MIPI_SIZE			SZ_256
> +
> +#define TEGRA_I2C_BASE			0x7000C000
> +#define TEGRA_I2C_SIZE			SZ_256
> +
> +#define TEGRA_TWC_BASE			0x7000C100
> +#define TEGRA_TWC_SIZE			SZ_256
> +
> +#define TEGRA_SPI_BASE			0x7000C380
> +#define TEGRA_SPI_SIZE			48
> +
> +#define TEGRA_I2C2_BASE			0x7000C400
> +#define TEGRA_I2C2_SIZE			SZ_256
> +
> +#define TEGRA_I2C3_BASE			0x7000C500
> +#define TEGRA_I2C3_SIZE			SZ_256
> +
> +#define TEGRA_OWR_BASE			0x7000D000
> +#define TEGRA_OWR_SIZE			80
> +
> +#define TEGRA_DVC_BASE			0x7000D000
> +#define TEGRA_DVC_SIZE			SZ_512
> +
> +#define TEGRA_SPI1_BASE			0x7000D400
> +#define TEGRA_SPI1_SIZE			SZ_512
> +
> +#define TEGRA_SPI2_BASE			0x7000D600
> +#define TEGRA_SPI2_SIZE			SZ_512
> +
> +#define TEGRA_SPI3_BASE			0x7000D800
> +#define TEGRA_SPI3_SIZE			SZ_512
> +
> +#define TEGRA_SPI4_BASE			0x7000DA00
> +#define TEGRA_SPI4_SIZE			SZ_512
> +
> +#define TEGRA_RTC_BASE			0x7000E000
> +#define TEGRA_RTC_SIZE			SZ_256
> +
> +#define TEGRA_KBC_BASE			0x7000E200
> +#define TEGRA_KBC_SIZE			SZ_256
> +
> +#define TEGRA_PMC_BASE			0x7000E400
> +#define TEGRA_PMC_SIZE			SZ_256
> +
> +#define TEGRA_MC_BASE			0x7000F000
> +#define TEGRA_MC_SIZE			SZ_1K
> +
> +#define TEGRA_EMC_BASE			0x7000F400
> +#define TEGRA_EMC_SIZE			SZ_1K
> +
> +#define TEGRA_FUSE_BASE			0x7000F800
> +#define TEGRA_FUSE_SIZE			SZ_1K
> +
> +#define TEGRA_KFUSE_BASE		0x7000FC00
> +#define TEGRA_KFUSE_SIZE		SZ_1K
> +
> +#define TEGRA_CSITE_BASE		0x70040000
> +#define TEGRA_CSITE_SIZE		SZ_256K
> +
> +#define TEGRA_USB_BASE			0xC5000000
> +#define TEGRA_USB_SIZE			SZ_16K
> +
> +#define TEGRA_USB1_BASE			0xC5004000
> +#define TEGRA_USB1_SIZE			SZ_16K
> +
> +#define TEGRA_USB2_BASE			0xC5008000
> +#define TEGRA_USB2_SIZE			SZ_16K
> +
> +#define TEGRA_SDMMC1_BASE		0xC8000000
> +#define TEGRA_SDMMC1_SIZE		SZ_512
> +
> +#define TEGRA_SDMMC2_BASE		0xC8000200
> +#define TEGRA_SDMMC2_SIZE		SZ_512
> +
> +#define TEGRA_SDMMC3_BASE		0xC8000400
> +#define TEGRA_SDMMC3_SIZE		SZ_512
> +
> +#define TEGRA_SDMMC4_BASE		0xC8000600
> +#define TEGRA_SDMMC4_SIZE		SZ_512
> +
> +#endif
> diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h
> new file mode 100644
> index 0000000..6151bab
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/memory.h
> @@ -0,0 +1,28 @@
> +/*
> + * arch/arm/mach-tegra/include/mach/memory.h
> + *
> + * Copyright (C) 2010 Google, Inc.
> + *
> + * Author:
> + *	Colin Cross <ccross at google.com>
> + *	Erik Gilling <konkers at google.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __MACH_TEGRA_MEMORY_H
> +#define __MACH_TEGRA_MEMORY_H
> +
> +/* physical offset of RAM */
> +#define PHYS_OFFSET		UL(0)
> +
> +#endif
> +
> diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/include/mach/system.h
> new file mode 100644
> index 0000000..84d5d46
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/system.h
> @@ -0,0 +1,39 @@
> +/*
> + * arch/arm/mach-tegra/include/mach/system.h
> + *
> + * Copyright (C) 2010 Google, Inc.
> + *
> + * Author:
> + *	Colin Cross <ccross at google.com>
> + *	Erik Gilling <konkers at google.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __MACH_TEGRA_SYSTEM_H
> +#define __MACH_TEGRA_SYSTEM_H
> +
> +#include <mach/hardware.h>
> +#include <mach/iomap.h>
> +
> +static inline void arch_idle(void)
> +{
> +}
> +
> +static inline void arch_reset(char mode, const char *cmd)
> +{
> +	void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
> +	u32 reg = readl(reset);
> +	reg |= 0x04;
> +	writel(reg, reset);
> +}
> +
> +#endif
> diff --git a/arch/arm/mach-tegra/include/mach/timex.h b/arch/arm/mach-tegra/include/mach/timex.h
> new file mode 100644
> index 0000000..a44ccbd
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/timex.h
> @@ -0,0 +1,26 @@
> +/*
> + * arch/arm/mach-tegra/include/mach/timex.h
> + *
> + * Copyright (C) 2010 Google, Inc.
> + *
> + * Author:
> + *	Colin Cross <ccross at google.com>
> + *	Erik Gilling <konkers at google.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __MACH_TEGRA_TIMEX_H
> +#define __MACH_TEGRA_TIMEX_H
> +
> +#define CLOCK_TICK_RATE		1000000
> +
> +#endif
> diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
> new file mode 100644
> index 0000000..6c4dd81
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/uncompress.h
> @@ -0,0 +1,78 @@
> +/*
> + * arch/arm/mach-tegra/include/mach/uncompress.h
> + *
> + * Copyright (C) 2010 Google, Inc.
> + *
> + * Author:
> + *	Colin Cross <ccross at google.com>
> + *	Erik Gilling <konkers at google.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __MACH_TEGRA_UNCOMPRESS_H
> +#define __MACH_TEGRA_UNCOMPRESS_H
> +
> +#include <linux/types.h>
> +#include <linux/serial_reg.h>
> +
> +#include <mach/iomap.h>
> +
> +#if defined(CONFIG_TEGRA_DEBUG_UARTA)
> +#define DEBUG_UART_BASE TEGRA_UARTA_BASE
> +#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
> +#define DEBUG_UART_BASE TEGRA_UARTB_BASE
> +#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
> +#define DEBUG_UART_BASE TEGRA_UARTC_BASE
> +#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
> +#define DEBUG_UART_BASE TEGRA_UARTD_BASE
> +#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
> +#define DEBUG_UART_BASE TEGRA_UARTE_BASE
> +#else
> +#define DEBUG_UART_BASE NULL
> +#endif
> +
> +static void putc(int c)
> +{
> +	volatile u8 *uart = (volatile u8 *)DEBUG_UART_BASE;
> +	int shift = 2;
> +
> +	if (uart == NULL)
> +		return;
> +
> +	while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
> +		barrier();
> +	uart[UART_TX << shift] = c;
> +}
> +
> +static inline void flush(void)
> +{
> +}
> +
> +static inline void arch_decomp_setup(void)
> +{
> +	volatile u8 *uart = (volatile u8 *)DEBUG_UART_BASE;
> +	int shift = 2;
> +
> +	if (uart == NULL)
> +		return;
> +
> +	uart[UART_LCR << shift] |= UART_LCR_DLAB;
> +	uart[UART_DLL << shift] = 0x75;
> +	uart[UART_DLM << shift] = 0x0;
> +	uart[UART_LCR << shift] = 3;
> +}
> +
> +static inline void arch_decomp_wdog(void)
> +{
> +}
> +
> +#endif
> diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
> new file mode 100644
> index 0000000..267a141
> --- /dev/null
> +++ b/arch/arm/mach-tegra/include/mach/vmalloc.h
> @@ -0,0 +1,28 @@
> +/*
> + * arch/arm/mach-tegra/include/mach/vmalloc.h
> + *
> + * Copyright (C) 2010 Google, Inc.
> + *
> + * Author:
> + *	Colin Cross <ccross at google.com>
> + *	Erik Gilling <konkers at google.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#ifndef __MACH_TEGRA_VMALLOC_H
> +#define __MACH_TEGRA_VMALLOC_H
> +
> +#include <asm/sizes.h>
> +
> +#define VMALLOC_END        0xFE000000
> +
> +#endif
> diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
> new file mode 100644
> index 0000000..9fe2c5c
> --- /dev/null
> +++ b/arch/arm/mach-tegra/io.c
> @@ -0,0 +1,78 @@
> +/*
> + * arch/arm/mach-tegra/io.c
> + *
> + * Copyright (C) 2010 Google, Inc.
> + *
> + * Author:
> + *	Colin Cross <ccross at google.com>
> + *	Erik Gilling <konkers at google.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/mm.h>
> +#include <linux/io.h>
> +
> +#include <mach/hardware.h>
> +#include <asm/page.h>
> +#include <asm/mach/map.h>
> +
> +#include "board.h"
> +
> +static struct map_desc tegra_io_desc[] __initdata = {
> +	{
> +		.virtual = IO_PPSB_VIRT,
> +		.pfn = __phys_to_pfn(IO_PPSB_PHYS),
> +		.length = IO_PPSB_SIZE,
> +		.type = MT_DEVICE,
> +	},
> +	{
> +		.virtual = IO_APB_VIRT,
> +		.pfn = __phys_to_pfn(IO_APB_PHYS),
> +		.length = IO_APB_SIZE,
> +		.type = MT_DEVICE,
> +	},
> +	{
> +		.virtual = IO_CPU_VIRT,
> +		.pfn = __phys_to_pfn(IO_CPU_PHYS),
> +		.length = IO_CPU_SIZE,
> +		.type = MT_DEVICE,
> +	},
> +};
> +
> +void __init tegra_map_common_io(void)
> +{
> +	iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
> +}
> +
> +/*
> + * Intercept ioremap() requests for addresses in our fixed mapping regions.
> + */
> +void __iomem *tegra_ioremap(unsigned long p, size_t size, unsigned int type)
> +{
> +	void __iomem *v = IO_ADDRESS(p);
> +	if (v == NULL)
> +		v = __arm_ioremap(p, size, type);
> +	return v;
> +}
> +EXPORT_SYMBOL(tegra_ioremap);
> +
> +void tegra_iounmap(volatile void __iomem *addr)
> +{
> +	unsigned long virt = (unsigned long)addr;
> +
> +	if (virt >= VMALLOC_START && virt < VMALLOC_END)
> +		__iounmap(addr);
> +}
> +EXPORT_SYMBOL(tegra_iounmap);
> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> index 5bd7c89..b4f6c5e 100644
> --- a/arch/arm/mm/Kconfig
> +++ b/arch/arm/mm/Kconfig
> @@ -760,7 +760,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
>  config CACHE_L2X0
>  	bool "Enable the L2x0 outer cache controller"
>  	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
> -		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
> +		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4 || ARCH_TEGRA
>  	default y
>  	select OUTER_CACHE
>  	select OUTER_CACHE_SYNC


-- 
Sincerely yours,
Mike.


From robert.jarzmik at free.fr  Mon Jun  7 04:47:05 2010
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Mon, 07 Jun 2010 10:47:05 +0200
Subject: [PATCH] RTC/pxa: remove unnecessary private ops->ioctl()
In-Reply-To: <4C0A5F53.6070600@gmail.com> (Wan ZongShun's message of "Sat, 05
	Jun 2010 22:29:39 +0800")
References: <4C0A5F53.6070600@gmail.com>
Message-ID: <877hmbcjqu.fsf@free.fr>

Wan ZongShun <mcuos.com at gmail.com> writes:
> Please, do not implement private ops->ioctl() unless absolutely necessary.
> pxa series RTC driver's ioctl() is unnecessary, since RTC subsystem has implement
> the ioctl() very well,so we can only use the API of '.alarm_irq_enable' and
> '.update_irq_enable' to do enable irq action.
>
> Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik at free.fr>

This is not an urgent fix, but a cleanup. Whoever gets it in (Alessandro through
rtc tree, Eric through arm/pxa tree, or Andrew) is to be defined.

I would go for Alessandro, as he handles the RTC tree.

Cheers.

--
Robert

PS: Removed alsa-devel list, as this is not alsa material


From tony at atomide.com  Mon Jun  7 04:51:12 2010
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 7 Jun 2010 11:51:12 +0300
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option
	for exceptions
In-Reply-To: <1275550613-9553-5-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
Message-ID: <20100607085112.GD15515@atomide.com>

* Eric Miao <eric.miao at canonical.com> [100603 10:36]:
> From: Eric Miao <eric.y.miao at gmail.com>
> 
> Original idea and prototype came from Nicolas Pitre.
> 
> As long as the zImage is placed within the 256MB range from the
> start of the memory, ZRELADDR (Address where the decompressed
> kernel will be placed, usually  == PHYS_OFFSET + TEXT_OFFSET)
> can be determined at run-time by masking PC with 0xf000_0000.
> 
> Running through all the Makefile.boot, all those zreladdr-y
> address == 0x[0-f]000_0000 + TEXT_OFFSET can be determined at
> run-time.
> 
> Option CONFIG_AUTO_ZRELADDR and CONFIG_ZRELADDR are introduced,
> CONFIG_ZRELADDR _must_ be explicitly specified if:
> 
>  - ((zreladdr-y - TEXT_OFFSET) & ~0xf0000000) != 0, which means
>    a maksing of PC with 0xf000_0000 will result an incorrect
>    address.
> 
>  - or the assumption of the zImage being loaded by the boot
>    loader within 256MB from the start address is simply
>    incorrect
> 
>  - or when ZBOOT_ROM is used, where the above assumption is
>    normally wrong

Nice series of patches!

> +config ZRELADDR
> +	hex "Physical address of the decompressed kernel image"
> +	depends on !AUTO_ZRELADDR
> +	default 0x00008000 if ARCH_BCMRING || ARCH_CNS3XXX || ARCH_DOVE ||\
> +			      ARCH_EBSA110 || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR ||\
> +			      ARCH_IOP13XX || ARCH_IOP33X || ARCH_IXP2000 ||\
> +			      ARCH_IXP23XX || ARCH_IXP4XX || ARCH_KIRKWOOD ||\
> +			      ARCH_KS8695  || ARCH_LOKI || ARCH_MMP || ARCH_MV78XX0 ||\
> +			      ARCH_NOMADIK || ARCH_NUC93X || ARCH_NS9XXX ||\
> +			      ARCH_ORION5X || ARCH_SPEAR3XX || ARCH_SPEAR6XX ||\
> +			      ARCH_UX5XX || ARCH_VERSATILE || ARCH_W90X900
> +	default 0x08008000 if ARCH_MX1 || ARCH_SHARK
> +	default 0x10008000 if ARCH_MSM || ARCH_OMAP1 || ARCH_RPC
> +	default 0x20008000 if ARCH_S5P6440 || ARCH_S5P6442 ||\
> +			      ARCH_S5PC100 || ARCH_S5PV210
> +	default 0x30008000 if ARCH_S3C2410 || ARCH_S3C2400 || ARCH_S3C2412 ||\
> +			      ARCH_S3C2416 || ARCH_S3C2440 || ARCH_S3C2443
> +	default 0x40008000 if ARCH_STMP378X || ARCH_STMP37XX || ARCH_SH7372 ||\
> +			      ARCH_SH7377
> +	default 0x50008000 if ARCH_S3C64XX || ARCH_SH7367
> +	default 0x60008000 if ARCH_VEXPRESS
> +	default 0x80008000 if ARCH_MX25 || ARCH_MX3 || ARCH_NETX ||\
> +			      ARCH_OMAP2 || ARCH_PNX4008

Please s/ARCH_OMAP2/ARCH_OMAP2PLUS/ above, then it covers ARCH_OMAP2, 3 and 4.

Regards,

Tony


From mcuos.com at gmail.com  Mon Jun  7 04:57:32 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Mon, 7 Jun 2010 16:57:32 +0800
Subject: [PATCH] RTC/pxa: remove unnecessary private ops->ioctl()
In-Reply-To: <877hmbcjqu.fsf@free.fr>
References: <4C0A5F53.6070600@gmail.com>
	<877hmbcjqu.fsf@free.fr>
Message-ID: <AANLkTilJntnk11OZJt5oeKv4bk5qv8nlDnuGHc2hTGOt@mail.gmail.com>

2010/6/7 Robert Jarzmik <robert.jarzmik at free.fr>:
> Wan ZongShun <mcuos.com at gmail.com> writes:
>> Please, do not implement private ops->ioctl() unless absolutely necessary.
>> pxa series RTC driver's ioctl() is unnecessary, since RTC subsystem has implement
>> the ioctl() very well,so we can only use the API of '.alarm_irq_enable' and
>> '.update_irq_enable' to do enable irq action.
>>
>> Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
> Acked-by: Robert Jarzmik <robert.jarzmik at free.fr>
>
> This is not an urgent fix, but a cleanup. Whoever gets it in (Alessandro through
> rtc tree, Eric through arm/pxa tree, or Andrew) is to be defined.
>

I will ping Andrew to apply it as soon as I get the owner's ACK.

> I would go for Alessandro, as he handles the RTC tree.
>
> Cheers.
>
> --
> Robert
>
> PS: Removed alsa-devel list, as this is not alsa material

Yes, I think I am careless for this. sorry.
>



-- 
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mail addr:linux-arm-kernel at lists.infradead.org
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you can subscribe it by sending me mail:
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From catalin.marinas at arm.com  Mon Jun  7 05:04:52 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 07 Jun 2010 10:04:52 +0100
Subject: Preload engine in ARMv7 (cortex A8)
In-Reply-To: <AANLkTilGu3OC_tth-Wurgu1jcm5zKKntINGc-A8CwkxI@mail.gmail.com>
References: <AANLkTilGu3OC_tth-Wurgu1jcm5zKKntINGc-A8CwkxI@mail.gmail.com>
Message-ID: <1275901492.7258.6.camel@toshiba-laptop>

On Tue, 2010-06-01 at 18:27 +0100, Vinayak Pane wrote:
> I am planning to utilize the PreLoad Engine for L2 cache. In past, I
> have played with cache locking with line by line in ARM9. There I
> could recall that tags and indexes are generated on basis of physical
> address of the data. Now in case of PLE we have the start address and
> number of lines to fill with. Does the PLE operation will leave some
> indexes empty ? Or does the PLE populate all the lines in that way
> with the source data address ? Do I need to start PLE for the block of
> size equal to that of way-size ? To ensure no lines remain empty  and
> to ensure no line gets overwriten by other line.

I couldn't fully understand your question. It looks more like
hardware-related (you could try support at arm.com).

Anyway, in general you should not make any assumptions about which lines
are present or not in the cache. With speculative loads on newer cores,
you can get other lines in the cache than what you were expecting and
they may evict some the you explicitly tried to preload.

Catalin



From jic23 at cam.ac.uk  Mon Jun  7 05:08:16 2010
From: jic23 at cam.ac.uk (Jonathan Cameron)
Date: Mon, 07 Jun 2010 10:08:16 +0100
Subject: [RFC PATCH] stargate2 and imote2 board file merge
In-Reply-To: <20100607070724.GB2702@excalibur.local>
References: <1275832502-28552-1-git-send-email-jic23@cam.ac.uk>
	<20100607070724.GB2702@excalibur.local>
Message-ID: <4C0CB700.8080300@cam.ac.uk>

On 06/07/10 08:07, Stefan Schmidt wrote:
> Hello.
> 
> On Sun, 2010-06-06 at 14:55, Jonathan Cameron wrote:
>> Signed-off-by: Jonathan Cameron <jic23 at cam.ac.uk>
>> ---
>>  These two boards are extremely similar in many ways and hence
>>  the board configs overlap a lot.  This patch merges the two
>>  board files.  Do people think this is worth doing?  Traditionally
>>  we always built a kernel supporting both devices anyway but the
>>  ifdefs allow one to be picked if people really want to.
> 
> I find it an interesting idea. We have done this on EZX with 6 devices. One
> thing that jumps into my face is that we should provide a way to let people know
> that the stargate2.c file does indeed also provide support for imote2. At least
> updated comments in KConfig and the header of the c file would be needed. That
> would allow people to discover it during configuration or greping.
Not sure we care particularly in the kconfig as it doesn't make any difference
to someone configuring. Either way they just select the platforms they want.
As for the c, greping will still work, it'll just get the machine definition
rather than the comments at the top.  Still I agree a few comments wouldn't hurt!
> 
> I don't know much about the Crossbow product palette but maybe we should even
> rename it to crossbow.c
Sadly not.  The devices were both originally Intel Research.  They sold the imote2
to crossbow. I think they gave the stargate2 designs to UCLA but I haven't seen any
sign of them doing anything with them and no one has posted anything to the platformx
users list for a while.  To complicate things further the imote2 is now owned by Memsic
after they bought the relevant bit of Crossbow. No idea what their plans are.

I'm inclined just to pick one or the other.  Perhaps we go with imote2
as I suspect there are a lot more them out there! Can't even use platformx
(Intel's code word for these sorts of devices) as that covered the original stargate.
> 
>>  arch/arm/mach-pxa/Makefile    |    2 +-
>>  arch/arm/mach-pxa/imote2.c    |  590 -----------------------------------
>>  arch/arm/mach-pxa/stargate2.c |  679 +++++++++++++++++++++++++++--------------
>>  3 files changed, 454 insertions(+), 817 deletions(-)
> 
> Given that we can eliminate nearly 400 lines of code and one board file I think
> it is worth it. I looked over the patch and it does look good so far. Will give
> it a runtime test the next days. If that truns out well I'm fine to ack it.
:) I'll admit I haven't tested it myself yet.  Didn't have the debug board to hand
to be able to flash it to an imote2 and my sg2's were all in use testing the radio
driver (that is dependent on mac802154 mainlining).  One day we will have these devices
fully supported in mainline.

Jonathan


From broonie at opensource.wolfsonmicro.com  Mon Jun  7 05:17:43 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 7 Jun 2010 10:17:43 +0100
Subject: [PATCH 2/3] pxa: Fix all devices using wm97xx_batt.h
In-Reply-To: <1275613654-23918-2-git-send-email-marek.vasut@gmail.com>
References: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>
	<1275613654-23918-2-git-send-email-marek.vasut@gmail.com>
Message-ID: <20100607091743.GB23093@rakim.wolfsonmicro.main>

On Fri, Jun 04, 2010 at 03:07:33AM +0200, Marek Vasut wrote:
> This file is scheduled for removal, therefore fix all devices that use this
> file to use the suggested wm97xx.h and pass platform data properly.
> 
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>


From broonie at opensource.wolfsonmicro.com  Mon Jun  7 05:18:01 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 7 Jun 2010 10:18:01 +0100
Subject: [PATCH 3/3] wm97xx_batt: Remove redundant header file
In-Reply-To: <1275613654-23918-3-git-send-email-marek.vasut@gmail.com>
References: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>
	<1275613654-23918-3-git-send-email-marek.vasut@gmail.com>
Message-ID: <20100607091801.GC23093@rakim.wolfsonmicro.main>

On Fri, Jun 04, 2010 at 03:07:34AM +0200, Marek Vasut wrote:
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>


From stefan at datenfreihafen.org  Mon Jun  7 05:24:58 2010
From: stefan at datenfreihafen.org (Stefan Schmidt)
Date: Mon, 7 Jun 2010 11:24:58 +0200
Subject: [RFC PATCH] stargate2 and imote2 board file merge
In-Reply-To: <4C0CB700.8080300@cam.ac.uk>
References: <1275832502-28552-1-git-send-email-jic23@cam.ac.uk>
	<20100607070724.GB2702@excalibur.local>
	<4C0CB700.8080300@cam.ac.uk>
Message-ID: <20100607092458.GE2702@excalibur.local>

Hello.

On Mon, 2010-06-07 at 10:08, Jonathan Cameron wrote:
> On 06/07/10 08:07, Stefan Schmidt wrote:
> > 
> > On Sun, 2010-06-06 at 14:55, Jonathan Cameron wrote:
> >> Signed-off-by: Jonathan Cameron <jic23 at cam.ac.uk>
> >> ---
> >>  These two boards are extremely similar in many ways and hence
> >>  the board configs overlap a lot.  This patch merges the two
> >>  board files.  Do people think this is worth doing?  Traditionally
> >>  we always built a kernel supporting both devices anyway but the
> >>  ifdefs allow one to be picked if people really want to.
> > 
> > I find it an interesting idea. We have done this on EZX with 6 devices. One
> > thing that jumps into my face is that we should provide a way to let people know
> > that the stargate2.c file does indeed also provide support for imote2. At least
> > updated comments in KConfig and the header of the c file would be needed. That
> > would allow people to discover it during configuration or greping.
> Not sure we care particularly in the kconfig as it doesn't make any difference
> to someone configuring. Either way they just select the platforms they want.
> As for the c, greping will still work, it'll just get the machine definition
> rather than the comments at the top.  Still I agree a few comments wouldn't hurt!

Yeah, I somehow missed that imote2 is still available as before in Kconfig just
maps to another board file. My bad. That fine then.

> > I don't know much about the Crossbow product palette but maybe we should even
> > rename it to crossbow.c
> Sadly not.  The devices were both originally Intel Research.  They sold the imote2
> to crossbow. I think they gave the stargate2 designs to UCLA but I haven't seen any
> sign of them doing anything with them and no one has posted anything to the platformx
> users list for a while.  To complicate things further the imote2 is now owned by Memsic
> after they bought the relevant bit of Crossbow. No idea what their plans are.
> 
> I'm inclined just to pick one or the other.  Perhaps we go with imote2
> as I suspect there are a lot more them out there! Can't even use platformx
> (Intel's code word for these sorts of devices) as that covered the original stargate.

Thanks for the background info. I'm fine with either one.

> >>  arch/arm/mach-pxa/Makefile    |    2 +-
> >>  arch/arm/mach-pxa/imote2.c    |  590 -----------------------------------
> >>  arch/arm/mach-pxa/stargate2.c |  679 +++++++++++++++++++++++++++--------------
> >>  3 files changed, 454 insertions(+), 817 deletions(-)
> > 
> > Given that we can eliminate nearly 400 lines of code and one board file I think
> > it is worth it. I looked over the patch and it does look good so far. Will give
> > it a runtime test the next days. If that truns out well I'm fine to ack it.

> :) I'll admit I haven't tested it myself yet.  Didn't have the debug board to hand
> to be able to flash it to an imote2 and my sg2's were all in use testing the radio
> driver (that is dependent on mac802154 mainlining).  One day we will have these devices
> fully supported in mainline.

I should be able to flash it onto the imote2 today or tomorrow. Will let you
know my results.

mfg
Stefan Schmidt


From balakrishnan at e-consystems.com  Mon Jun  7 02:29:51 2010
From: balakrishnan at e-consystems.com (balakrishnan)
Date: Mon, 07 Jun 2010 11:59:51 +0530
Subject: pxa300 - DDRAM base value
In-Reply-To: <201006061834.50297.marek.vasut@gmail.com>
References: <1275371058.7001.35.camel@balakrishnan-desktop>
	<201006051919.17738.marek.vasut@gmail.com>
	<AANLkTil5TWYILcdp872as8S8LMqQWhPYWLt7cxs2lUm5@mail.gmail.com>
	<201006061834.50297.marek.vasut@gmail.com>
Message-ID: <1275892191.3501.17.camel@balakrishnan-desktop>

On Sun, 2010-06-06 at 18:34 +0200, Marek Vasut wrote:

> Dne Ne 6. ?ervna 2010 10:17:00 Eric Miao napsal(a):
> > On Sun, Jun 6, 2010 at 1:19 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > > Dne ?t 1. ?ervna 2010 07:44:18 balakrishnan napsal(a):
> > >> I am working on pxa300 based development board and using Linux 2.6.34.
> > >> This Linux kernel already has support for following boards
> > >> 1. zylonite_pxa300
> > >> 2. cm-x300
> > >> 3. colibri-pxa300
> > >> 4. littleton
> > >> 
> > >> My doubt is that pxa300 based boards are using "0xa0000000"  as DDRAM
> > >> base and PHYS_OFFSET is also defined in
> > >> "arch/arm/mach-pxa/include/mach/memory.h" as 0xa0000000.
> > >> But in our board  DDR is mapped in 0x80000000. Does it make any
> > >> problem?. Because after mmu is turned ON, my board is hanging.
> > >> 
> > >> "zreladdr-y   := 0x80008000" is defined in
> > >> "arch/arm/mach-pxa/Makefile.boot" file .
> > >> my machine_desc is as follows
> > >> .phys_io        = 0x40000000,
> > >> .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
> > >> .boot_params    = 0x80000100,
> > > 
> > > Try editing both arch/arm/mach-pxa/Makefile.boot and
> > > arch/arm/mach/pxa/include/mach/memory.h
> > > 
> > >> With Thanks
> > >> J.Balakrishnan
> > > 
> > > The 0x80000000 should be aliased to 0xa0000000, but looking into the PXA
> > > docs, it is only on pxa320. Eric, any ideas on this ?
> > 
> > Should be working on pxa300/310 as well. If it doesn't, check you
> > bootloader to make sure the mapping is OK, and memory doesn't exceed
> > (0xa000_0000 - 0x8000_0000).
> 
> It worked last time I used the pxa310 littleton board, but I can't check on the 
> pxa300 zylonite board just yet.
> 
> Could you give us your bootloader details ?

hi, 
      Now, I can able to boot after editing following files
arch/arm/mach-pxa/Makefile.boot and
arch/arm/mach/pxa/include/mach/memory.h (0x80000000 changed to
0xa0000000). My doubt is 
1.why 0x80000000 (DDR phy address) is aliased to 0xa0000000 in pxa
architecture?
2.In my development board two DDRAMs mapped at 0x80000000-0x88000000 and
0xc0000000-0xc8000000, how can I inform to kernel about this different
bank and size?.

My Boot loader details,
------------------------------
=>bdi
arch_number = 0x00000B04
env_t       = 0x00000000
boot_params = 0x80000100
DRAM bank   = 0x00000000
-> start    = 0x80000000
-> size     = 0x08000000
DRAM bank   = 0x00000001
-> start    = 0xC0000000
-> size     = 0x08000000
ethaddr     = 08:00:3e:26:0a:5b
ip_addr     = 192.168.0.21
baudrate    = 115200 bps
=>ver
U-Boot 2010.03 (Jun 01 2010 - 14:27:43)


With Thanks
J.Balakrishnan
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From eric.y.miao at gmail.com  Mon Jun  7 05:31:46 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 7 Jun 2010 17:31:46 +0800
Subject: [PATCH] RTC/pxa: remove unnecessary private ops->ioctl()
In-Reply-To: <877hmbcjqu.fsf@free.fr>
References: <4C0A5F53.6070600@gmail.com> <877hmbcjqu.fsf@free.fr>
Message-ID: <AANLkTik8kwpB1rdGU6oSqP9f_sREGPapku7XtrQfgOWp@mail.gmail.com>

On Mon, Jun 7, 2010 at 4:47 PM, Robert Jarzmik <robert.jarzmik at free.fr> wrote:
> Wan ZongShun <mcuos.com at gmail.com> writes:
>> Please, do not implement private ops->ioctl() unless absolutely necessary.
>> pxa series RTC driver's ioctl() is unnecessary, since RTC subsystem has implement
>> the ioctl() very well,so we can only use the API of '.alarm_irq_enable' and
>> '.update_irq_enable' to do enable irq action.
>>
>> Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
> Acked-by: Robert Jarzmik <robert.jarzmik at free.fr>
>
> This is not an urgent fix, but a cleanup. Whoever gets it in (Alessandro through
> rtc tree, Eric through arm/pxa tree, or Andrew) is to be defined.
>
> I would go for Alessandro, as he handles the RTC tree.
>

Yeah, Acked-by: Eric Miao <eric.y.miao at gmail.com>


From linus.ml.walleij at gmail.com  Mon Jun  7 05:33:05 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Mon, 7 Jun 2010 11:33:05 +0200
Subject: [PATCH] ARM: PL011 baudrate extension for ST-Ericssons derivative
In-Reply-To: <1275507433-32644-1-git-send-email-linus.walleij@stericsson.com>
References: <1275507433-32644-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <AANLkTingPGmsrG_7Kn6X1xSKVozRFfQ6AAoYkZMXIA3R@mail.gmail.com>

Quoting self

2010/6/2 Linus Walleij <linus.walleij at stericsson.com>:

> Implementation of the ST-Ericsson baudrate extension in the PL011
> block. In this modified variant it is possible to change the
> sampling factor from 16 to 8, and thanks to this we can get higher
> baudrates while still using the same peripheral clock.
>
> Also replace the simple division to determine the baud divisor
> with DIV_ROUND_CLOSEST() rather than a simple integer division.
> (...)
> -       baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
> -       quot = port->uartclk * 4 / baud;
> + ? ? ? baud = uart_get_baud_rate(port, termios, old, 0,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? port->uartclk/(uap->oversampling ? 8 : 16));
> +
> + ? ? ? if (baud > port->uartclk/16)
> + ? ? ? ? ? ? ? quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
> + ? ? ? else
> + ? ? ? ? ? ? ? quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);

I should add that we have measured some hard data on this change,
and it fixes a real-life bug for us: below you can see what are diversions from
fixed baudrates for the two algorithms,
first: original, second: DIV_ROUND_CLOSEST:

baud=   9600, FBRD=0x00 IBRD=0xFA os=0, real baud=   9600 (0.00%)
baud=   9600, FBRD=0x00 IBRD=0xFA os=0, real baud=   9600 (0.00%)
----
baud=  19200, FBRD=0x00 IBRD=0x7D os=0, real baud=  19200 (0.00%)
baud=  19200, FBRD=0x00 IBRD=0x7D os=0, real baud=  19200 (0.00%)
----
baud=  38400, FBRD=0x20 IBRD=0x3E os=0, real baud=  38400 (0.00%)
baud=  38400, FBRD=0x20 IBRD=0x3E os=0, real baud=  38400 (0.00%)
----
baud=  57600, FBRD=0x2A IBRD=0x29 os=0, real baud=  57614 (0.02%)
baud=  57600, FBRD=0x2B IBRD=0x29 os=0, real baud=  57592 (0.01%)
----
baud= 115200, FBRD=0x35 IBRD=0x14 os=0, real baud= 115228 (0.02%)
baud= 115200, FBRD=0x35 IBRD=0x14 os=0, real baud= 115228 (0.02%)
----
baud= 230400, FBRD=0x1A IBRD=0x0A os=0, real baud= 230630 (0.10%)
baud= 230400, FBRD=0x1B IBRD=0x0A os=0, real baud= 230284 (0.05%)
----
baud= 460800, FBRD=0x0D IBRD=0x05 os=0, real baud= 461261 (0.10%)
baud= 460800, FBRD=0x0D IBRD=0x05 os=0, real baud= 461261 (0.10%)
----
baud= 500000, FBRD=0x33 IBRD=0x04 os=0, real baud= 500325 (0.07%)
baud= 500000, FBRD=0x33 IBRD=0x04 os=0, real baud= 500325 (0.07%)
----
baud= 576000, FBRD=0x0A IBRD=0x04 os=0, real baud= 577443 (0.25%)
baud= 576000, FBRD=0x0B IBRD=0x04 os=0, real baud= 575280 (0.13%)
----
baud= 921600, FBRD=0x26 IBRD=0x02 os=0, real baud= 925301 (0.40%)
baud= 921600, FBRD=0x27 IBRD=0x02 os=0, real baud= 919760 (0.20%)
----
baud=1000000, FBRD=0x19 IBRD=0x02 os=0, real baud=1003921 (0.39%)
baud=1000000, FBRD=0x1A IBRD=0x02 os=0, real baud= 997402 (0.26%)
----
baud=1152000, FBRD=0x05 IBRD=0x02 os=0, real baud=1154887 (0.25%)
baud=1152000, FBRD=0x05 IBRD=0x02 os=0, real baud=1154887 (0.25%)
----
baud=1500000, FBRD=0x26 IBRD=0x01 os=0, real baud=1505882 (0.39%)
baud=1500000, FBRD=0x26 IBRD=0x01 os=0, real baud=1505882 (0.39%)
----
baud=2000000, FBRD=0x0C IBRD=0x01 os=0, real baud=2021052 (1.05%)
baud=2000000, FBRD=0x0D IBRD=0x01 os=0, real baud=1994805 (0.26%)
----
baud=2500000, FBRD=0x3A IBRD=0x01 os=1, real baud=2518032 (0.72%)
baud=2500000, FBRD=0x3B IBRD=0x01 os=1, real baud=2497560 (0.10%)
----
baud=3000000, FBRD=0x26 IBRD=0x01 os=1, real baud=3011764 (0.39%)
baud=3000000, FBRD=0x26 IBRD=0x01 os=1, real baud=3011764 (0.39%)
----
baud=3500000, FBRD=0x17 IBRD=0x01 os=1, real baud=3531034 (0.89%)
baud=3500000, FBRD=0x18 IBRD=0x01 os=1, real baud=3490908 (0.26%)
----
baud=4000000, FBRD=0x0C IBRD=0x01 os=1, real baud=4042104 (1.05%)
baud=4000000, FBRD=0x0D IBRD=0x01 os=1, real baud=3989610 (0.26%)

As you see, the effect kicks in at the higher baudrates in the ST-Ericsson
derivative, but it's still marginally improving the non-exended case as well.

Yours,
Linus Walleij


From will.deacon at arm.com  Mon Jun  7 05:53:50 2010
From: will.deacon at arm.com (Will Deacon)
Date: Mon,  7 Jun 2010 10:53:50 +0100
Subject: [PATCH] Versatile Express: add support for local timers on CA9X4
	daughterboard
Message-ID: <1275904430-15995-1-git-send-email-will.deacon@arm.com>

This patch adds support for the Cortex-A9 local timers available when
using the CA9X4 daughterboard with the Versatile Express.

Cc: Russell King - ARM Linux <linux at arm.linux.org.uk>
Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/Kconfig                               |    5 +++--
 arch/arm/mach-vexpress/ct-ca9x4.c              |   14 ++++++++------
 arch/arm/mach-vexpress/include/mach/ct-ca9x4.h |    1 +
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 98922f7..7b117b1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1172,9 +1172,10 @@ config HOTPLUG_CPU
 config LOCAL_TIMERS
 	bool "Use local timer interrupts"
 	depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
-		REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
+		REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+		ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
 	default y
-	select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
+	select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_VEXPRESS || ARCH_OMAP4 || ARCH_U8500)
 	help
 	  Enable support for local timers on SMP platforms, rather then the
 	  legacy IPI broadcast method.  Local timers allows the system
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index e6f7303..3762fc8 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -14,6 +14,7 @@
 #include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
+#include <asm/smp_twd.h>
 
 #include <mach/clkdev.h>
 #include <mach/ct-ca9x4.h>
@@ -63,20 +64,25 @@ static void __init ct_ca9x4_init_irq(void)
 	gic_cpu_init(0, gic_cpu_base_addr);
 }
 
-#if 0
 static void ct_ca9x4_timer_init(void)
 {
+#if 0
 	writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
 	writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
 
 	sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
 	sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
+#endif
+
+#ifdef CONFIG_LOCAL_TIMERS
+	twd_base = MMIO_P2V(A9_MPCORE_TWD);
+#endif
+	v2m_timer.init();
 }
 
 static struct sys_timer ct_ca9x4_timer = {
 	.init	= ct_ca9x4_timer_init,
 };
-#endif
 
 static struct clcd_panel xvga_panel = {
 	.mode		= {
@@ -240,10 +246,6 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
 	.boot_params	= PHYS_OFFSET + 0x00000100,
 	.map_io		= ct_ca9x4_map_io,
 	.init_irq	= ct_ca9x4_init_irq,
-#if 0
 	.timer		= &ct_ca9x4_timer,
-#else
-	.timer		= &v2m_timer,
-#endif
 	.init_machine	= ct_ca9x4_init,
 MACHINE_END
diff --git a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
index 8650f04..f9e2f8d 100644
--- a/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
+++ b/arch/arm/mach-vexpress/include/mach/ct-ca9x4.h
@@ -28,6 +28,7 @@
 #define A9_MPCORE_SCU		(CT_CA9X4_MPIC + 0x0000)
 #define A9_MPCORE_GIC_CPU	(CT_CA9X4_MPIC + 0x0100)
 #define A9_MPCORE_GIT		(CT_CA9X4_MPIC + 0x0200)
+#define A9_MPCORE_TWD		(CT_CA9X4_MPIC + 0x0600)
 #define A9_MPCORE_GIC_DIST	(CT_CA9X4_MPIC + 0x1000)
 
 /*
-- 
1.6.3.3



From r.schwebel at pengutronix.de  Mon Jun  7 05:54:22 2010
From: r.schwebel at pengutronix.de (Robert Schwebel)
Date: Mon, 7 Jun 2010 11:54:22 +0200
Subject: defconfig information
In-Reply-To: <20100604222820.GA4438@kyllikki.org>
References: <20100604222820.GA4438@kyllikki.org>
Message-ID: <20100607095422.GF8767@pengutronix.de>

Hi Vincent,

On Fri, Jun 04, 2010 at 11:28:20PM +0100, Vincent Sanders wrote:
> As always the ARM Kernel autobuilder is available at
> http://armlinux.simtec.co.uk/kautobuild/
>
> The community usage of this service has dropped to an all time low
> (only six people actually used it in the last month) and I am
> seriously considering if it serves a useful purpose any longer.

It would be cool to have some kind of filter: I read the autobuilder
mails on a daily base, but usually, we are only interested in the state
of machines we are maintaining, which is difficult to find out if you
always get the whole list. So for my daily checks, I'm relying more on
the mails of our internal autobuilder, which allows better filtering
plus runtime tests.

But anyway: the service is great!

rsc
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From stefan at datenfreihafen.org  Mon Jun  7 05:54:36 2010
From: stefan at datenfreihafen.org (Stefan Schmidt)
Date: Mon, 7 Jun 2010 11:54:36 +0200
Subject: [RFC PATCH] stargate2 and imote2 board file merge
In-Reply-To: <20100607092458.GE2702@excalibur.local>
References: <1275832502-28552-1-git-send-email-jic23@cam.ac.uk>
	<20100607070724.GB2702@excalibur.local>
	<4C0CB700.8080300@cam.ac.uk>
	<20100607092458.GE2702@excalibur.local>
Message-ID: <20100607095436.GF2702@excalibur.local>

Hello.

On Mon, 2010-06-07 at 11:24, Stefan Schmidt wrote:
> On Mon, 2010-06-07 at 10:08, Jonathan Cameron wrote:
> 
> > :) I'll admit I haven't tested it myself yet.  Didn't have the debug board to hand
> > to be able to flash it to an imote2 and my sg2's were all in use testing the radio
> > driver (that is dependent on mac802154 mainlining).  One day we will have these devices
> > fully supported in mainline.
> 
> I should be able to flash it onto the imote2 today or tomorrow. Will let you
> know my results.

I can confirm that it boots fine on my imote2.

Acked-by: Stefan Schmidt <stefan at datenfreihafen.org>

I guess its Eric's call if he would like to see them merged.

regards
Stefan Schmidt


From tony at atomide.com  Mon Jun  7 07:23:47 2010
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 7 Jun 2010 14:23:47 +0300
Subject: defconfig information
In-Reply-To: <20100607095422.GF8767@pengutronix.de>
References: <20100604222820.GA4438@kyllikki.org>
	<20100607095422.GF8767@pengutronix.de>
Message-ID: <20100607112347.GN15515@atomide.com>

* Robert Schwebel <r.schwebel at pengutronix.de> [100607 12:53]:
> Hi Vincent,
> 
> On Fri, Jun 04, 2010 at 11:28:20PM +0100, Vincent Sanders wrote:
> > As always the ARM Kernel autobuilder is available at
> > http://armlinux.simtec.co.uk/kautobuild/
> >
> > The community usage of this service has dropped to an all time low
> > (only six people actually used it in the last month) and I am
> > seriously considering if it serves a useful purpose any longer.
> 
> It would be cool to have some kind of filter: I read the autobuilder
> mails on a daily base, but usually, we are only interested in the state
> of machines we are maintaining, which is difficult to find out if you
> always get the whole list. So for my daily checks, I'm relying more on
> the mails of our internal autobuilder, which allows better filtering
> plus runtime tests.
> 
> But anyway: the service is great!

Yes I too use it for checking after each -rc has been tagged or so.

Tony


From broonie at opensource.wolfsonmicro.com  Mon Jun  7 07:38:03 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 7 Jun 2010 12:38:03 +0100
Subject: [PATCH] pxa/z2: Add regulator support
In-Reply-To: <1275882020-30159-1-git-send-email-marek.vasut@gmail.com>
References: <1275882020-30159-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <20100607113802.GB5993@sirena.org.uk>

On Mon, Jun 07, 2010 at 05:40:20AM +0200, Marek Vasut wrote:
> Register TPS65023 regulator as found in Z2. The Z2 actually contains a TPS65021,
> but this chip is apparently compatible.

If you're doing this you should register the chip that is actually
present on the board and then modify the driver to bind to both device
IDs.  That way the driver will be able to handle any differences that do
exist.


From broonie at opensource.wolfsonmicro.com  Mon Jun  7 07:39:10 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 7 Jun 2010 12:39:10 +0100
Subject: [PATCH v2] pxa/z2: Add regulator support
In-Reply-To: <1275883143-3512-1-git-send-email-marek.vasut@gmail.com>
References: <1275883143-3512-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <20100607113910.GC5993@sirena.org.uk>

On Mon, Jun 07, 2010 at 05:59:03AM +0200, Marek Vasut wrote:

> +	}, {
> +		.constraints = {
> +			.name		= "LDO1",
> +			.min_uV		= 1000000,
> +			.max_uV		= 3150000,
> +			.always_on	= 1,
> +		},
> +	}, {
> +		.constraints = {
> +			.name		= "LDO2",
> +			.min_uV		= 1050000,
> +			.max_uV		= 3300000,
> +			.always_on	= 1,
> +		},
> +	}

Are you *sure* that the voltages for these regulators can be varied this
much (especailly given that there are no consumers set up)?


From broonie at opensource.wolfsonmicro.com  Mon Jun  7 07:48:56 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 7 Jun 2010 12:48:56 +0100
Subject: [PATCH 1/2] ISL6271A voltage regulator support.
In-Reply-To: <1275887908-22285-1-git-send-email-marek.vasut@gmail.com>
References: <1275887908-22285-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <20100607114856.GD5993@sirena.org.uk>

On Mon, Jun 07, 2010 at 07:18:27AM +0200, Marek Vasut wrote:

> This device is very simple, it supports only one LDO. This single LDO is
> programmed over I2C to 16 possible voltages.

Marek, you really should know to CC patches to maintainers by now.  This
is not CCed to myself, Liam or lkml.

> +#include <linux/regulator/driver.h>
> +#include <linux/regulator/machine.h>

Why are you including machine.h here?  I can't actually see any suspect
code in the driver so I suspect it's unused.

Otherwise this looks good.


From lrg at slimlogic.co.uk  Mon Jun  7 08:45:32 2010
From: lrg at slimlogic.co.uk (Liam Girdwood)
Date: Mon, 07 Jun 2010 13:45:32 +0100
Subject: [alsa-devel] [RFC PATCH v3 0/3] ep93xx i2s audio
In-Reply-To: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
References: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1275914732.3045.105.camel@odin>

On Fri, 2010-06-04 at 17:11 +1200, Ryan Mallon wrote:
> The following patch series adds support for i2s audio on the ep93xx,
> with the Snapper CL15 used as an example implementation.
> 
> This version fixes a number of things from the previous round:
>  - Removed unused #defines
>  - Set symmetric rates for the cpu dai
>  - Fixed the sdiv/lrdiv calculation loop
>  - Moved the cpu dai registration
>  - Removed empty ep93xx_pcm_prepare callback
>  - Fixed enable/disable when both capture and playback are running
>  
> Capture still does not work. The dma is running, but the captured data
> is all zeros (tested used arecord and loopback). I have a 2.6.20
> kernel with ep93xx i2s audio working an capture works there on the
> same hardware. I have spent sometime looking into this, but can't see
> the problem. Would appreciate if someone can lend some insight as to
> what I have done wrong.
> 
> Ryan Mallon (3):
>   ep93xx i2s core support
>   ep93xx i2s audio driver
>   Snapper cl15 audio support

All

Acked-by: Liam Girdwood <lrg at slimlogic.co.uk>
-- 
Freelance Developer, SlimLogic Ltd
ASoC and Voltage Regulator Maintainer.
http://www.slimlogic.co.uk



From broonie at opensource.wolfsonmicro.com  Mon Jun  7 09:26:37 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 7 Jun 2010 14:26:37 +0100
Subject: [alsa-devel] [RFC PATCH v3 0/3] ep93xx i2s audio
In-Reply-To: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
References: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <20100607132634.GE5993@sirena.org.uk>

On Fri, Jun 04, 2010 at 05:11:22PM +1200, Ryan Mallon wrote:
> The following patch series adds support for i2s audio on the ep93xx,
> with the Snapper CL15 used as an example implementation.

Please do remember to CC maintainers on patches.  I've had to remind you
about this before, it's really not helpful to drop the people you're
expecting to review the patches - it'll tend to delay things or lead to
the patches getting missed.  From a code point of view this looks fine
but we'll need an arch maintainer to sign off on that bit of the code.
I've applied 2/3 since that has no arch/arm elements.


From linux at arm.linux.org.uk  Mon Jun  7 10:01:31 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 7 Jun 2010 15:01:31 +0100
Subject: [PATCH]ARM/footbridge: fix wrong parenthesis
In-Reply-To: <4C08C749.3050700@gmail.com>
References: <4C08C749.3050700@gmail.com>
Message-ID: <20100607140131.GA7220@n2100.arm.linux.org.uk>

On Fri, Jun 04, 2010 at 05:28:41PM +0800, Wan ZongShun wrote:
> There is a wrong redundant right parenthesis in this code.

This patch is wrong.

>  unsigned long __pfn_to_bus(unsigned long pfn)
>  {
> -	return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET));
> +	return __pfn_to_phys(pfn + (fb_bus_sdram_offset() - PHYS_OFFSET));

It makes no sense to add byte address offsets to a PFN.  The correct
solution is to delete the right paren at the end of the line instead.


From mcuos.com at gmail.com  Mon Jun  7 10:12:45 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Mon, 7 Jun 2010 22:12:45 +0800
Subject: [PATCH]ARM/footbridge: fix wrong parenthesis
In-Reply-To: <20100607140131.GA7220@n2100.arm.linux.org.uk>
References: <4C08C749.3050700@gmail.com>
	<20100607140131.GA7220@n2100.arm.linux.org.uk>
Message-ID: <AANLkTin8Crq0F76TmXsLGsd9tXcYQKbDhxZgoDjvvazV@mail.gmail.com>

So should I send  a true one again or fix it by your self?

2010/6/7, Russell King - ARM Linux <linux at arm.linux.org.uk>:
> On Fri, Jun 04, 2010 at 05:28:41PM +0800, Wan ZongShun wrote:
>> There is a wrong redundant right parenthesis in this code.
>
> This patch is wrong.
>
>>  unsigned long __pfn_to_bus(unsigned long pfn)
>>  {
>> -	return __pfn_to_phys(pfn) + (fb_bus_sdram_offset() - PHYS_OFFSET));
>> +	return __pfn_to_phys(pfn + (fb_bus_sdram_offset() - PHYS_OFFSET));
>
> It makes no sense to add byte address offsets to a PFN.  The correct
> solution is to delete the right paren at the end of the line instead.
>


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From marek.vasut at gmail.com  Mon Jun  7 10:54:51 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 7 Jun 2010 16:54:51 +0200
Subject: [PATCH 1/2] ISL6271A voltage regulator support.
In-Reply-To: <20100607114856.GD5993@sirena.org.uk>
References: <1275887908-22285-1-git-send-email-marek.vasut@gmail.com>
	<20100607114856.GD5993@sirena.org.uk>
Message-ID: <201006071654.51324.marek.vasut@gmail.com>

Dne Po 7. ?ervna 2010 13:48:56 Mark Brown napsal(a):
> On Mon, Jun 07, 2010 at 07:18:27AM +0200, Marek Vasut wrote:
> > This device is very simple, it supports only one LDO. This single LDO is
> > programmed over I2C to 16 possible voltages.
> 
> Marek, you really should know to CC patches to maintainers by now.  This
> is not CCed to myself, Liam or lkml.

I rather should have marked this RFC ... this code probably doesn't even work, I 
just want someone who has zaurus to test it (they are CCed). Sorry for the 
confusion.
> 
> > +#include <linux/regulator/driver.h>
> > +#include <linux/regulator/machine.h>
> 
> Why are you including machine.h here?  I can't actually see any suspect
> code in the driver so I suspect it's unused.
> 
> Otherwise this looks good.


From marek.vasut at gmail.com  Mon Jun  7 10:56:33 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 7 Jun 2010 16:56:33 +0200
Subject: [PATCH v2] pxa/z2: Add regulator support
In-Reply-To: <20100607113910.GC5993@sirena.org.uk>
References: <1275883143-3512-1-git-send-email-marek.vasut@gmail.com>
	<20100607113910.GC5993@sirena.org.uk>
Message-ID: <201006071656.33063.marek.vasut@gmail.com>

Dne Po 7. ?ervna 2010 13:39:10 Mark Brown napsal(a):
> On Mon, Jun 07, 2010 at 05:59:03AM +0200, Marek Vasut wrote:
> > +	}, {
> > +		.constraints = {
> > +			.name		= "LDO1",
> > +			.min_uV		= 1000000,
> > +			.max_uV		= 3150000,
> > +			.always_on	= 1,
> > +		},
> > +	}, {
> > +		.constraints = {
> > +			.name		= "LDO2",
> > +			.min_uV		= 1050000,
> > +			.max_uV		= 3300000,
> > +			.always_on	= 1,
> > +		},
> > +	}
> 
> Are you *sure* that the voltages for these regulators can be varied this
> much (especailly given that there are no consumers set up)?

These are not connected so I believe it doesn't matter. Though I'm still 
slightly unfamiliar with the regulator API. Here I should have CCed you, sorry.

Is this the correct way or is there some other way to just shut these off ?

Cheers


From marek.vasut at gmail.com  Mon Jun  7 10:57:47 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 7 Jun 2010 16:57:47 +0200
Subject: [PATCH] pxa/z2: Add regulator support
In-Reply-To: <20100607113802.GB5993@sirena.org.uk>
References: <1275882020-30159-1-git-send-email-marek.vasut@gmail.com>
	<20100607113802.GB5993@sirena.org.uk>
Message-ID: <201006071657.47186.marek.vasut@gmail.com>

Dne Po 7. ?ervna 2010 13:38:03 Mark Brown napsal(a):
> On Mon, Jun 07, 2010 at 05:40:20AM +0200, Marek Vasut wrote:
> > Register TPS65023 regulator as found in Z2. The Z2 actually contains a
> > TPS65021, but this chip is apparently compatible.
> 
> If you're doing this you should register the chip that is actually
> present on the board and then modify the driver to bind to both device
> IDs.  That way the driver will be able to handle any differences that do
> exist.

Ok, I'll send a patch for this.


From marek.vasut at gmail.com  Mon Jun  7 11:12:20 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 7 Jun 2010 17:12:20 +0200
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option for
	exceptions
In-Reply-To: <1275550613-9553-5-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
Message-ID: <201006071712.20888.marek.vasut@gmail.com>

Dne ?t 3. ?ervna 2010 09:36:52 Eric Miao napsal(a):
> From: Eric Miao <eric.y.miao at gmail.com>
> 
> Original idea and prototype came from Nicolas Pitre.
> 
> As long as the zImage is placed within the 256MB range from the
> start of the memory, ZRELADDR (Address where the decompressed
> kernel will be placed, usually  == PHYS_OFFSET + TEXT_OFFSET)
> can be determined at run-time by masking PC with 0xf000_0000.
> 
> Running through all the Makefile.boot, all those zreladdr-y
> address == 0x[0-f]000_0000 + TEXT_OFFSET can be determined at
> run-time.
> 
> Option CONFIG_AUTO_ZRELADDR and CONFIG_ZRELADDR are introduced,
> CONFIG_ZRELADDR _must_ be explicitly specified if:
> 
>  - ((zreladdr-y - TEXT_OFFSET) & ~0xf0000000) != 0, which means
>    a maksing of PC with 0xf000_0000 will result an incorrect
>    address.
> 
>  - or the assumption of the zImage being loaded by the boot
>    loader within 256MB from the start address is simply
>    incorrect
> 
>  - or when ZBOOT_ROM is used, where the above assumption is
>    normally wrong
> 
> List of all Makefile.boot:
> 
> Hardcoded, and can be auto calculated by masking PC with 0xf000_0000:
> 
> arch/arm/mach-cns3xxx/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-dove/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-ebsa110/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-footbridge/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-integrator/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-iop13xx/Makefile.boot:	   zreladdr-y   := 0x00008000
> arch/arm/mach-iop33x/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-ixp2000/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-ixp23xx/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-ixp4xx/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-kirkwood/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-ks8695/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-loki/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-mmp/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-mv78xx0/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-nomadik/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-nuc93x/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-ns9xxx/Makefile.boot:	   zreladdr-y	:= 0x8000
> arch/arm/mach-orion5x/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-spear3xx/Makefile.boot:      zreladdr-y	:= 0x00008000
> arch/arm/mach-spear6xx/Makefile.boot:      zreladdr-y	:= 0x00008000
> arch/arm/mach-ux500/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-versatile/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-w90x900/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-msm/Makefile.boot:	   zreladdr-y	:= 0x10008000
> arch/arm/mach-omap1/Makefile.boot:	   zreladdr-y	:= 0x10008000
> arch/arm/mach-rpc/Makefile.boot:	   zreladdr-y	:= 0x10008000
> arch/arm/mach-s5p6440/Makefile.boot:	   zreladdr-y	:= 0x20008000
> arch/arm/mach-s5p6442/Makefile.boot:	   zreladdr-y	:= 0x20008000
> arch/arm/mach-s5pc100/Makefile.boot:	   zreladdr-y	:= 0x20008000
> arch/arm/mach-s5pv210/Makefile.boot:	   zreladdr-y	:= 0x20008000
> arch/arm/mach-s3c2410/Makefile.boot:	   zreladdr-y	:= 0x30008000
> arch/arm/mach-s3c2410/Makefile.boot:	   zreladdr-y	:= 0x30108000
> arch/arm/mach-stmp378x/Makefile.boot:	   zreladdr-y	:= 0x40008000
> arch/arm/mach-stmp37xx/Makefile.boot:	   zreladdr-y	:= 0x40008000
> arch/arm/mach-s3c64xx/Makefile.boot:	   zreladdr-y	:= 0x50008000
> arch/arm/mach-vexpress/Makefile.boot:	   zreladdr-y	:= 0x60008000
> arch/arm/mach-mx25/Makefile.boot:	   zreladdr-y	:= 0x80008000
> arch/arm/mach-mx3/Makefile.boot:	   zreladdr-y	:= 0x80008000
> arch/arm/mach-netx/Makefile.boot:	   zreladdr-y	:= 0x80008000
> arch/arm/mach-omap2/Makefile.boot:	   zreladdr-y	:= 0x80008000
> arch/arm/mach-pnx4008/Makefile.boot:	   zreladdr-y	:= 0x80008000
> arch/arm/mach-mx5/Makefile.boot:	   zreladdr-y	:= 0x90008000
> arch/arm/mach-mxc91231/Makefile.boot:	   zreladdr-y	:= 0x90008000
> arch/arm/mach-iop32x/Makefile.boot:	   zreladdr-y	:= 0xa0008000
> arch/arm/mach-pxa/Makefile.boot:	   zreladdr-y	:= 0xa0008000
> arch/arm/mach-lh7a40x/Makefile.boot:	   zreladdr-y	:= 0xc0008000
> arch/arm/mach-clps711x/Makefile.boot:	   zreladdr-y	:= 0xc0028000
> arch/arm/mach-aaec2000/Makefile.boot:	   zreladdr-y	:= 0xf0008000
> arch/arm/mach-l7200/Makefile.boot:	   zreladdr-y	:= 0xf0008000
> 
> Depends on other options/macros, but still can be auto calculated by
> masking PC with 0xf000_0000:
> 
> arch/arm/mach-bcmring/Makefile.boot:	   zreladdr-y   :=
> $(CONFIG_BCM_ZRELADDR) * refer to
> arch/arm/configs/bcmring_defconfig:CONFIG_BCM_ZRELADDR=0x8000
> arch/arm/mach-h720x/Makefile.boot:	   zreladdr-$(CONFIG_ARCH_H720X) :=
> 0x40008000 arch/arm/mach-shmobile/Makefile.boot:	   zreladdr-y   :=
> $(__ZRELADDR) * __ZRELADDR depends on CONFIG_MEMORY_START
> arch/arm/configs/ap4evb_defconfig:	CONFIG_MEMORY_START=0x40000000 (SH7372)
> arch/arm/configs/g3evm_defconfig:	CONFIG_MEMORY_START=0x50000000 (SH7367)
> arch/arm/configs/g4evm_defconfig:	CONFIG_MEMORY_START=0x40000000 (SH7377)
> 
> arch/arm/mach-at91/Makefile.boot:	   zreladdr-y	:= 0x70008000
> (CONFIG_ARCH_AT91CAP9) arch/arm/mach-at91/Makefile.boot:	   zreladdr-y	
:=
> 0x70008000 (CONFIG_ARCH_AT91SAM9G45) arch/arm/mach-at91/Makefile.boot:	  
> zreladdr-y	:= 0x20008000 (CONFIG_ARCH_AT91)
> arch/arm/mach-davinci/Makefile.boot:	   zreladdr-y	:= 0xc0008000
> (CONFIG_ARCH_DAVINCI_DA8XX) arch/arm/mach-davinci/Makefile.boot:	  
> zreladdr-y	:= 0x80008000 (!CONFIG_ARCH_DAVINCI_DA8XX)
> arch/arm/mach-ep93xx/Makefile.boot:	  
> zreladdr-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET)	:= 0x00008000
> arch/arm/mach-ep93xx/Makefile.boot:	  
> zreladdr-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET)		:= 0xc0008000
> arch/arm/mach-ep93xx/Makefile.boot:	  
> zreladdr-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET)		:= 0xd0008000
> arch/arm/mach-ep93xx/Makefile.boot:	  
> zreladdr-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET)		:= 0xe0008000
> arch/arm/mach-ep93xx/Makefile.boot:	  
> zreladdr-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET)	:= 0xf0008000
> arch/arm/mach-gemini/Makefile.boot:	   zreladdr-y	:= 0x00008000
> (CONFIG_GEMINI_MEM_SWAP) arch/arm/mach-gemini/Makefile.boot:	  
> zreladdr-y	:= 0x10008000 (!CONFIG_GEMINI_MEM_SWAP)
> arch/arm/mach-mx2/Makefile.boot:	   zreladdr-$(CONFIG_MACH_MX21) :=
> 0xC0008000 arch/arm/mach-mx2/Makefile.boot:	  
> zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
> arch/arm/mach-realview/Makefile.boot:	   zreladdr-y	:= 0x70008000
> (CONFIG_REALVIEW_HIGH_PHYS_OFFSET) arch/arm/mach-realview/Makefile.boot:	 
>  zreladdr-y	:= 0x00008000 (CONFIG_REALVIEW_HIGH_PHYS_OFFSET)
> arch/arm/mach-sa1100/Makefile.boot:	   zreladdr-y	:= 0xc0008000
> arch/arm/mach-sa1100/Makefile.boot:	   zreladdr-$(CONFIG_SA1111) :=
> 0xc0208000
> 
> Machines where ZRELADDR cannot be auto calcuated:
> 
> arch/arm/mach-mx1/Makefile.boot:	   zreladdr-y	:= 0x08008000
> arch/arm/mach-shark/Makefile.boot:	   zreladdr-y	:= 0x08008000
> arch/arm/mach-u300/Makefile.boot:	   zreladdr-y	:= 0x28E08000
> arch/arm/mach-u300/Makefile.boot:	   zreladdr-y	:= 0x48008000
> 
> Signed-off-by: Eric Miao <eric.miao at canonical.com>
> ---
>  arch/arm/Kconfig                  |   63
> +++++++++++++++++++++++++++++++++++++ arch/arm/boot/Makefile            | 
>  10 +++---
>  arch/arm/boot/compressed/Makefile |    4 +-
>  arch/arm/boot/compressed/head.S   |   12 +++++--
>  4 files changed, 79 insertions(+), 10 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index e340193..818f731 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1497,6 +1497,69 @@ config TEXT_OFFSET
>  	  TEXT_OFFSET is the offset of the decompressed kernel image from
>  	  memory start. Currently, it is expected the least significant 16
>  	  bits to be 0x8000, so to leave space for the initial page table.
> +
> +config AUTO_ZRELADDR
> +	bool "Auto calculation of the decompressed kernel image address"
> +	depends on !ZBOOT_ROM && !(ARCH_MX1 || ARCH_SHARK || ARCH_U300)
> +	help
> +	  ZRELADDR is the physical address where the decompressed kernel
> +	  image will be placed. If AUTO_ZRELADDR is selected, the address
> +	  will be determined at run-time by masking the current IP with
> +	  0xf000_0000. This assumes the zImage being placed in the 256MB
> +	  range from the start of memory.
> +
> +config ZRELADDR
> +	hex "Physical address of the decompressed kernel image"
> +	depends on !AUTO_ZRELADDR
> +	default 0x00008000 if ARCH_BCMRING || ARCH_CNS3XXX || ARCH_DOVE ||\
> +			      ARCH_EBSA110 || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR 
||\
> +			      ARCH_IOP13XX || ARCH_IOP33X || ARCH_IXP2000 ||\
> +			      ARCH_IXP23XX || ARCH_IXP4XX || ARCH_KIRKWOOD ||\
> +			      ARCH_KS8695  || ARCH_LOKI || ARCH_MMP || 
ARCH_MV78XX0 ||\
> +			      ARCH_NOMADIK || ARCH_NUC93X || ARCH_NS9XXX ||\
> +			      ARCH_ORION5X || ARCH_SPEAR3XX || ARCH_SPEAR6XX ||\
> +			      ARCH_UX5XX || ARCH_VERSATILE || ARCH_W90X900
> +	default 0x08008000 if ARCH_MX1 || ARCH_SHARK
> +	default 0x10008000 if ARCH_MSM || ARCH_OMAP1 || ARCH_RPC
> +	default 0x20008000 if ARCH_S5P6440 || ARCH_S5P6442 ||\
> +			      ARCH_S5PC100 || ARCH_S5PV210
> +	default 0x30008000 if ARCH_S3C2410 || ARCH_S3C2400 || ARCH_S3C2412 ||\
> +			      ARCH_S3C2416 || ARCH_S3C2440 || ARCH_S3C2443
> +	default 0x40008000 if ARCH_STMP378X || ARCH_STMP37XX || ARCH_SH7372 ||\
> +			      ARCH_SH7377
> +	default 0x50008000 if ARCH_S3C64XX || ARCH_SH7367
> +	default 0x60008000 if ARCH_VEXPRESS
> +	default 0x80008000 if ARCH_MX25 || ARCH_MX3 || ARCH_NETX ||\
> +			      ARCH_OMAP2 || ARCH_PNX4008
> +	default 0x90008000 if ARCH_MX5 || ARCH_MX91231
> +	default 0xa0008000 if ARCH_IOP32X || ARCH_PXA || MACH_MX27
> +	default 0xc0008000 if ARCH_LH7A40X || MACH_MX21
> +	default 0xf0008000 if ARCH_AAEC2000 || ARCH_L7200
> +	default 0xc0028000 if ARCH_CLPS711X
> +	default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
> +	default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
> +	default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX
> +	default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX
> +	default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET
> +	default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET
> +	default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET
> +	default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET
> +	default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET
> +	default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP
> +	default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP
> +	default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET
> +	default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET
> +	default 0xc0208000 if ARCH_SA1100 && SA1111
> +	default 0xc0008000 if ARCH_SA1100 && !SA1111
> +	default 0x30108000 if ARCH_S3C2410 && PM_H1940
> +	default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM
> +	default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM
> +	help
> +	  ZRELADDR is the physical address where the decompressed kernel
> +	  image will be placed. ZRELADDR has to be specified when the
> +	  assumption of AUTO_ZRELADDR is not valid, or when ZBOOT_ROM is
> +	  selected.
> +
>  endmenu
> 

Hi,
what about the PXA based devices, where RAM begins at 0x80000000 ?

Cheers

>  menu "CPU Power Management"
> diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
> index 4a590f4..8cc4669 100644
> --- a/arch/arm/boot/Makefile
> +++ b/arch/arm/boot/Makefile
> @@ -14,18 +14,16 @@
>  MKIMAGE         := $(srctree)/scripts/mkuboot.sh
> 
>  ifneq ($(MACHINE),)
> -include $(srctree)/$(MACHINE)/Makefile.boot
> +-include $(srctree)/$(MACHINE)/Makefile.boot
>  endif
> 
>  # Note: the following conditions must always be true:
> -#   ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
>  #   PARAMS_PHYS must be within 4MB of ZRELADDR
>  #   INITRD_PHYS must be in RAM
> -ZRELADDR    := $(zreladdr-y)
>  PARAMS_PHYS := $(params_phys-y)
>  INITRD_PHYS := $(initrd_phys-y)
> 
> -export ZRELADDR INITRD_PHYS PARAMS_PHYS
> +export INITRD_PHYS PARAMS_PHYS
> 
>  targets := Image zImage xipImage bootpImage uImage
> 
> @@ -67,7 +65,7 @@ quiet_cmd_uimage = UIMAGE  $@
>  ifeq ($(CONFIG_ZBOOT_ROM),y)
>  $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
>  else
> -$(obj)/uImage: LOADADDR=$(ZRELADDR)
> +$(obj)/uImage: LOADADDR=$(CONFIG_ZRELADDR)
>  endif
> 
>  ifeq ($(CONFIG_THUMB2_KERNEL),y)
> @@ -78,6 +76,8 @@ $(obj)/uImage: STARTADDR=$(LOADADDR)
>  endif
> 
>  $(obj)/uImage:	$(obj)/zImage FORCE
> +	@test "$(CONFIG_AUTO_ZRELADDR)" == "y" ||\
> +	(echo CONFIG_ZRELADDR must be specified for uImage; exit -1)
>  	$(call if_changed,uimage)
>  	@echo '  Image $@ is ready'
> 
> diff --git a/arch/arm/boot/compressed/Makefile
> b/arch/arm/boot/compressed/Makefile index dbd3fe8..45b0f48 100644
> --- a/arch/arm/boot/compressed/Makefile
> +++ b/arch/arm/boot/compressed/Makefile
> @@ -4,6 +4,8 @@
>  # create a compressed vmlinuz image from the original vmlinux
>  #
> 
> +AFLAGS_head.o        := -DTEXT_OFFSET=$(CONFIG_TEXT_OFFSET)
> +
>  HEAD	= head.o
>  OBJS	= misc.o decompress.o
>  FONTC	= $(srctree)/drivers/video/console/font_acorn_8x8.c
> @@ -79,8 +81,6 @@ endif
>  EXTRA_CFLAGS  := -fpic -fno-builtin
>  EXTRA_AFLAGS  := -Wa,-march=all
> 
> -# Supply ZRELADDR to the decompressor via linker symbols.
> -LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
>  ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
>  LDFLAGS_vmlinux += --be8
>  endif
> diff --git a/arch/arm/boot/compressed/head.S
> b/arch/arm/boot/compressed/head.S index 0765990..17d19dc 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -170,9 +170,16 @@ not_angel:
> 
>  		.text
>  		adr	r0, LC0
> - ARM(		ldmia	r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
> - THUMB(		ldmia	r0, {r1, r2, r3, r4, r5, r6, r11, ip}	)
> + ARM(		ldmia	r0, {r1, r2, r3, r5, r6, r11, ip, sp})
> + THUMB(		ldmia	r0, {r1, r2, r3, r5, r6, r11, ip}	)
>   THUMB(		ldr	sp, [r0, #32]				)
> +#ifdef CONFIG_AUTO_ZRELADDR
> +		@ determine final kernel image address
> +		and	r4, pc, #0xf0000000
> +		add	r4, r4, #TEXT_OFFSET
> +#else
> +		ldr	r4, =CONFIG_ZRELADDR
> +#endif
>  		subs	r0, r0, r1		@ calculate the delta offset
> 
>  						@ if delta is zero, we are
> @@ -310,7 +317,6 @@ wont_overwrite:	mov	r0, r4
>  LC0:		.word	LC0			@ r1
>  		.word	__bss_start		@ r2
>  		.word	_end			@ r3
> -		.word	zreladdr		@ r4
>  		.word	_start			@ r5
>  		.word	_image_size		@ r6
>  		.word	_got_start		@ r11


From broonie at opensource.wolfsonmicro.com  Mon Jun  7 11:35:34 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 7 Jun 2010 16:35:34 +0100
Subject: [PATCH v2] pxa/z2: Add regulator support
In-Reply-To: <201006071656.33063.marek.vasut@gmail.com>
References: <1275883143-3512-1-git-send-email-marek.vasut@gmail.com>
	<20100607113910.GC5993@sirena.org.uk>
	<201006071656.33063.marek.vasut@gmail.com>
Message-ID: <20100607153534.GH13287@rakim.wolfsonmicro.main>

On Mon, Jun 07, 2010 at 04:56:33PM +0200, Marek Vasut wrote:
> Dne Po 7. ?ervna 2010 13:39:10 Mark Brown napsal(a):

> > Are you *sure* that the voltages for these regulators can be varied this
> > much (especailly given that there are no consumers set up)?

> These are not connected so I believe it doesn't matter. Though I'm still 
> slightly unfamiliar with the regulator API. Here I should have CCed you, sorry.
> 
> Is this the correct way or is there some other way to just shut these off ?

Call regulator_has_full_constraints() in your machine driver, they'll be
shut off at the end of boot when nothing is using them.


From linux at dominikbrodowski.net  Mon Jun  7 12:24:57 2010
From: linux at dominikbrodowski.net (Dominik Brodowski)
Date: Mon, 7 Jun 2010 18:24:57 +0200
Subject: [PATCH Resend] PCMCIA: add Cogent CSB726 PCMCIA support
In-Reply-To: <1275571550-24437-1-git-send-email-vzapolskiy@gmail.com>
References: <1275571550-24437-1-git-send-email-vzapolskiy@gmail.com>
Message-ID: <20100607162457.GA10712@isilmar-3.linta.de>

Russell,

have you had a chance to review this patch, and/or decide which way it
should take upstream?

Best,
	Dominik

On Thu, Jun 03, 2010 at 05:25:50PM +0400, Vladimir Zapolskiy wrote:
> This patch adds support for CompactFlash socket found in CSB726 board.
> 
> Signed-off-by: Vladimir Zapolskiy <vzapolskiy at gmail.com>
> Cc: Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>
> Cc: Dominik Brodowski <linux at dominikbrodowski.net>
> Acked-by: Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>
> Acked-by: Dominik Brodowski<linux at dominikbrodowski.net>
> ---
>  drivers/pcmcia/Kconfig         |    3 +-
>  drivers/pcmcia/Makefile        |    1 +
>  drivers/pcmcia/pxa2xx_csb726.c |  156 ++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 159 insertions(+), 1 deletions(-)
>  create mode 100644 drivers/pcmcia/pxa2xx_csb726.c
> 
> diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
> index 9f3adbd..168219b 100644
> --- a/drivers/pcmcia/Kconfig
> +++ b/drivers/pcmcia/Kconfig
> @@ -208,7 +208,8 @@ config PCMCIA_PXA2XX
>  	depends on ARM && ARCH_PXA && PCMCIA
>  	depends on (ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL \
>  		    || MACH_ARMCORE || ARCH_PXA_PALM || TRIZEPS_PCMCIA \
> -		    || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2)
> +		    || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2 \
> +		    || MACH_CSB726)
>  	select PCMCIA_SOC_COMMON
>  	help
>  	  Say Y here to include support for the PXA2xx PCMCIA controller
> diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
> index 83ff802..efcda3f 100644
> --- a/drivers/pcmcia/Makefile
> +++ b/drivers/pcmcia/Makefile
> @@ -74,5 +74,6 @@ pxa2xx-obj-$(CONFIG_MACH_PALMTC)		+= pxa2xx_palmtc.o
>  pxa2xx-obj-$(CONFIG_MACH_PALMLD)		+= pxa2xx_palmld.o
>  pxa2xx-obj-$(CONFIG_MACH_E740)			+= pxa2xx_e740.o
>  pxa2xx-obj-$(CONFIG_MACH_STARGATE2)		+= pxa2xx_stargate2.o
> +pxa2xx-obj-$(CONFIG_MACH_CSB726)		+= pxa2xx_csb726.o
>  
>  obj-$(CONFIG_PCMCIA_PXA2XX)			+= pxa2xx_base.o $(pxa2xx-obj-y)
> diff --git a/drivers/pcmcia/pxa2xx_csb726.c b/drivers/pcmcia/pxa2xx_csb726.c
> new file mode 100644
> index 0000000..bd86e90
> --- /dev/null
> +++ b/drivers/pcmcia/pxa2xx_csb726.c
> @@ -0,0 +1,156 @@
> +/*
> + * linux/drivers/pcmcia/pxa2xx_csb726.c
> + *
> + * Cogent CSB726 Compact Flash specific routines.
> + *
> + * Copyright 2010 Vladimir Zapolskiy <vzapolskiy at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/interrupt.h>
> +#include <linux/delay.h>
> +#include <linux/platform_device.h>
> +#include <linux/gpio.h>
> +
> +#include <pcmcia/ss.h>
> +
> +#include <asm/irq.h>
> +#include <asm/mach-types.h>
> +
> +#include "soc_common.h"
> +
> +#define GPIO_CF_RDY     98
> +#define GPIO_CF_CD      99
> +#define GPIO_CF_RST     103
> +
> +static struct pcmcia_irqs irqs[] = {
> +	{
> +		.sock = 0,
> +		.irq  = IRQ_GPIO(GPIO_CF_CD),
> +		.str  = "PCMCIA0 CD",
> +	},
> +};
> +
> +static int csb726_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
> +{
> +	int ret;
> +
> +	ret = gpio_request(GPIO_CF_RST, "CF reset");
> +	if (ret)
> +		return ret;
> +	gpio_direction_output(GPIO_CF_RST, 0);
> +
> +	skt->socket.pci_irq = IRQ_GPIO(GPIO_CF_RDY);
> +	ret = soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
> +	if (!ret)
> +		gpio_free(GPIO_CF_RST);
> +
> +	return ret;
> +}
> +
> +static void csb726_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
> +{
> +	soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs));
> +	gpio_free(GPIO_CF_RST);
> +}
> +
> +static void csb726_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
> +				       struct pcmcia_state *state)
> +{
> +	state->detect = !gpio_get_value(GPIO_CF_CD);
> +	state->ready  = !!gpio_get_value(GPIO_CF_RDY);
> +	state->bvd1   = 0; /* not available - battery detect on card */
> +	state->bvd2   = 0; /* not available */
> +	state->vs_3v  = 1; /* not available - voltage detect for card */
> +	state->vs_Xv  = 0; /* not available */
> +	state->wrprot = 0; /* not available - write protect */
> +}
> +
> +static int csb726_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
> +					  const socket_state_t *state)
> +{
> +	switch (skt->nr) {
> +	case 0:
> +		if (state->flags & SS_RESET) {
> +			/* reset */
> +			gpio_set_value(GPIO_CF_RST, 1);
> +			udelay(10);
> +			gpio_set_value(GPIO_CF_RST, 0);
> +		}
> +		break;
> +	}
> +
> +	return 0;
> +}
> +
> +static void csb726_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
> +{
> +	soc_pcmcia_enable_irqs(skt, irqs, ARRAY_SIZE(irqs));
> +}
> +
> +static void csb726_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
> +{
> +	soc_pcmcia_disable_irqs(skt, irqs, ARRAY_SIZE(irqs));
> +}
> +
> +static struct pcmcia_low_level csb726_pcmcia_ops __initdata = {
> +	.owner			= THIS_MODULE,
> +	.hw_init		= csb726_pcmcia_hw_init,
> +	.hw_shutdown		= csb726_pcmcia_hw_shutdown,
> +	.socket_state		= csb726_pcmcia_socket_state,
> +	.configure_socket	= csb726_pcmcia_configure_socket,
> +	.socket_init		= csb726_pcmcia_socket_init,
> +	.socket_suspend		= csb726_pcmcia_socket_suspend,
> +	.nr			= 1,
> +};
> +
> +static struct platform_device *csb726_pcmcia_device;
> +
> +static int __init csb726_pcmcia_init(void)
> +{
> +	int ret;
> +
> +	if (!machine_is_csb726())
> +		return -ENODEV;
> +
> +	csb726_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
> +	if (!csb726_pcmcia_device)
> +		return -ENOMEM;
> +
> +	ret = platform_device_add_data(csb726_pcmcia_device,
> +				       &csb726_pcmcia_ops,
> +				       sizeof(csb726_pcmcia_ops));
> +	if (ret)
> +		goto error_put_platform_device;
> +
> +	ret = platform_device_add(csb726_pcmcia_device);
> +	if (ret)
> +		goto error_put_platform_device;
> +
> +	return 0;
> +
> +error_put_platform_device:
> +	platform_device_put(csb726_pcmcia_device);
> +
> +	return ret;
> +}
> +
> +static void __exit csb726_pcmcia_exit(void)
> +{
> +	platform_device_unregister(csb726_pcmcia_device);
> +}
> +
> +fs_initcall(csb726_pcmcia_init);
> +module_exit(csb726_pcmcia_exit);
> +
> +MODULE_DESCRIPTION("Cogent CSB726 Compact Flash Driver");
> +MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy at gmail.com>");
> +MODULE_LICENSE("GPL v2");
> +MODULE_ALIAS("platform:pxa2xx-pcmcia");
> -- 
> 1.7.0.4
> 


From marek.vasut at gmail.com  Mon Jun  7 12:56:56 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 7 Jun 2010 18:56:56 +0200
Subject: [PATCH Resend] PCMCIA: add Cogent CSB726 PCMCIA support
In-Reply-To: <20100607162457.GA10712@isilmar-3.linta.de>
References: <1275571550-24437-1-git-send-email-vzapolskiy@gmail.com>
	<20100607162457.GA10712@isilmar-3.linta.de>
Message-ID: <201006071856.56960.marek.vasut@gmail.com>

Dne Po 7. ?ervna 2010 18:24:57 Dominik Brodowski napsal(a):
> Russell,
> 
> have you had a chance to review this patch, and/or decide which way it
> should take upstream?
> 
> Best,
> 	Dominik
> 
> On Thu, Jun 03, 2010 at 05:25:50PM +0400, Vladimir Zapolskiy wrote:
> > This patch adds support for CompactFlash socket found in CSB726 board.
> > 
> > Signed-off-by: Vladimir Zapolskiy <vzapolskiy at gmail.com>
> > Cc: Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>
> > Cc: Dominik Brodowski <linux at dominikbrodowski.net>
> > Acked-by: Dmitry Eremin-Solenikov <dbaryshkov at gmail.com>
> > Acked-by: Dominik Brodowski<linux at dominikbrodowski.net>
> > ---
> > 
> >  drivers/pcmcia/Kconfig         |    3 +-
> >  drivers/pcmcia/Makefile        |    1 +
> >  drivers/pcmcia/pxa2xx_csb726.c |  156
> >  ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 159
> >  insertions(+), 1 deletions(-)
> >  create mode 100644 drivers/pcmcia/pxa2xx_csb726.c
> > 
> > diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig
> > index 9f3adbd..168219b 100644
> > --- a/drivers/pcmcia/Kconfig
> > +++ b/drivers/pcmcia/Kconfig
> > @@ -208,7 +208,8 @@ config PCMCIA_PXA2XX
> > 
> >  	depends on ARM && ARCH_PXA && PCMCIA
> >  	depends on (ARCH_LUBBOCK || MACH_MAINSTONE || PXA_SHARPSL \
> >  	
> >  		    || MACH_ARMCORE || ARCH_PXA_PALM || TRIZEPS_PCMCIA \
> > 
> > -		    || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2)
> > +		    || ARCOM_PCMCIA || ARCH_PXA_ESERIES || MACH_STARGATE2 \
> > +		    || MACH_CSB726)
> > 
> >  	select PCMCIA_SOC_COMMON
> >  	help
> >  	
> >  	  Say Y here to include support for the PXA2xx PCMCIA controller
> > 
> > diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile
> > index 83ff802..efcda3f 100644
> > --- a/drivers/pcmcia/Makefile
> > +++ b/drivers/pcmcia/Makefile
> > @@ -74,5 +74,6 @@ pxa2xx-obj-$(CONFIG_MACH_PALMTC)		+= 
pxa2xx_palmtc.o
> > 
> >  pxa2xx-obj-$(CONFIG_MACH_PALMLD)		+= pxa2xx_palmld.o
> >  pxa2xx-obj-$(CONFIG_MACH_E740)			+= pxa2xx_e740.o
> >  pxa2xx-obj-$(CONFIG_MACH_STARGATE2)		+= pxa2xx_stargate2.o
> > 
> > +pxa2xx-obj-$(CONFIG_MACH_CSB726)		+= pxa2xx_csb726.o
> > 
> >  obj-$(CONFIG_PCMCIA_PXA2XX)			+= pxa2xx_base.o 
$(pxa2xx-obj-y)
> > 
> > diff --git a/drivers/pcmcia/pxa2xx_csb726.c
> > b/drivers/pcmcia/pxa2xx_csb726.c new file mode 100644
> > index 0000000..bd86e90
> > --- /dev/null
> > +++ b/drivers/pcmcia/pxa2xx_csb726.c
> > @@ -0,0 +1,156 @@
> > +/*
> > + * linux/drivers/pcmcia/pxa2xx_csb726.c
> > + *
> > + * Cogent CSB726 Compact Flash specific routines.
> > + *
> > + * Copyright 2010 Vladimir Zapolskiy <vzapolskiy at gmail.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + */
> > +
> > +#include <linux/module.h>
> > +#include <linux/init.h>
> > +#include <linux/kernel.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/delay.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/gpio.h>
> > +
> > +#include <pcmcia/ss.h>
> > +
> > +#include <asm/irq.h>
> > +#include <asm/mach-types.h>
> > +
> > +#include "soc_common.h"
> > +
> > +#define GPIO_CF_RDY     98
> > +#define GPIO_CF_CD      99
> > +#define GPIO_CF_RST     103
> > +
> > +static struct pcmcia_irqs irqs[] = {
> > +	{
> > +		.sock = 0,
> > +		.irq  = IRQ_GPIO(GPIO_CF_CD),
> > +		.str  = "PCMCIA0 CD",
> > +	},
> > +};
> > +
> > +static int csb726_pcmcia_hw_init(struct soc_pcmcia_socket *skt)
> > +{
> > +	int ret;
> > +
> > +	ret = gpio_request(GPIO_CF_RST, "CF reset");
> > +	if (ret)
> > +		return ret;
> > +	gpio_direction_output(GPIO_CF_RST, 0);

This can also fail.

> > +
> > +	skt->socket.pci_irq = IRQ_GPIO(GPIO_CF_RDY);

gpio_to_irq();

> > +	ret = soc_pcmcia_request_irqs(skt, irqs, ARRAY_SIZE(irqs));
> > +	if (!ret)
> > +		gpio_free(GPIO_CF_RST);

Use a failpath here:
if (ret) { dev_err(); goto err1; }
return 0;
err1:
...

> > +
> > +	return ret;
> > +}
> > +
> > +static void csb726_pcmcia_hw_shutdown(struct soc_pcmcia_socket *skt)
> > +{
> > +	soc_pcmcia_free_irqs(skt, irqs, ARRAY_SIZE(irqs));
> > +	gpio_free(GPIO_CF_RST);
> > +}
> > +
> > +static void csb726_pcmcia_socket_state(struct soc_pcmcia_socket *skt,
> > +				       struct pcmcia_state *state)
> > +{
> > +	state->detect = !gpio_get_value(GPIO_CF_CD);
> > +	state->ready  = !!gpio_get_value(GPIO_CF_RDY);

Is the double negation (!!) needed here?

> > +	state->bvd1   = 0; /* not available - battery detect on card */
> > +	state->bvd2   = 0; /* not available */
> > +	state->vs_3v  = 1; /* not available - voltage detect for card */
> > +	state->vs_Xv  = 0; /* not available */
> > +	state->wrprot = 0; /* not available - write protect */
> > +}
> > +
> > +static int csb726_pcmcia_configure_socket(struct soc_pcmcia_socket *skt,
> > +					  const socket_state_t *state)
> > +{
> > +	switch (skt->nr) {
> > +	case 0:

You registered just one socket anyway ... how can socket->nr be != 0?

> > +		if (state->flags & SS_RESET) {
> > +			/* reset */
> > +			gpio_set_value(GPIO_CF_RST, 1);
> > +			udelay(10);
> > +			gpio_set_value(GPIO_CF_RST, 0);
> > +		}
> > +		break;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static void csb726_pcmcia_socket_init(struct soc_pcmcia_socket *skt)
> > +{
> > +	soc_pcmcia_enable_irqs(skt, irqs, ARRAY_SIZE(irqs));
> > +}
> > +
> > +static void csb726_pcmcia_socket_suspend(struct soc_pcmcia_socket *skt)
> > +{
> > +	soc_pcmcia_disable_irqs(skt, irqs, ARRAY_SIZE(irqs));
> > +}
> > +
> > +static struct pcmcia_low_level csb726_pcmcia_ops __initdata = {
> > +	.owner			= THIS_MODULE,
> > +	.hw_init		= csb726_pcmcia_hw_init,
> > +	.hw_shutdown		= csb726_pcmcia_hw_shutdown,
> > +	.socket_state		= csb726_pcmcia_socket_state,
> > +	.configure_socket	= csb726_pcmcia_configure_socket,
> > +	.socket_init		= csb726_pcmcia_socket_init,
> > +	.socket_suspend		= csb726_pcmcia_socket_suspend,
> > +	.nr			= 1,
> > +};
> > +
> > +static struct platform_device *csb726_pcmcia_device;
> > +
> > +static int __init csb726_pcmcia_init(void)
> > +{
> > +	int ret;
> > +
> > +	if (!machine_is_csb726())
> > +		return -ENODEV;
> > +
> > +	csb726_pcmcia_device = platform_device_alloc("pxa2xx-pcmcia", -1);
> > +	if (!csb726_pcmcia_device)
> > +		return -ENOMEM;
> > +
> > +	ret = platform_device_add_data(csb726_pcmcia_device,
> > +				       &csb726_pcmcia_ops,
> > +				       sizeof(csb726_pcmcia_ops));
> > +	if (ret)
> > +		goto error_put_platform_device;
> > +
> > +	ret = platform_device_add(csb726_pcmcia_device);
> > +	if (ret)
> > +		goto error_put_platform_device;
> > +
> > +	return 0;
> > +
> > +error_put_platform_device:
> > +	platform_device_put(csb726_pcmcia_device);
> > +
> > +	return ret;
> > +}
> > +
> > +static void __exit csb726_pcmcia_exit(void)
> > +{
> > +	platform_device_unregister(csb726_pcmcia_device);
> > +}
> > +
> > +fs_initcall(csb726_pcmcia_init);

module_init();

> > +module_exit(csb726_pcmcia_exit);
> > +
> > +MODULE_DESCRIPTION("Cogent CSB726 Compact Flash Driver");
> > +MODULE_AUTHOR("Vladimir Zapolskiy <vzapolskiy at gmail.com>");
> > +MODULE_LICENSE("GPL v2");
> > +MODULE_ALIAS("platform:pxa2xx-pcmcia");
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Cheers!


From ben-linux at fluff.org  Mon Jun  7 13:30:41 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Mon, 7 Jun 2010 18:30:41 +0100
Subject: FYI: Qemu support on s5pc110
In-Reply-To: <AANLkTil8bmtwXNYpMhtPqK21_Z-kEi9wZSOoZtd1n7ML@mail.gmail.com>
References: <AANLkTil8bmtwXNYpMhtPqK21_Z-kEi9wZSOoZtd1n7ML@mail.gmail.com>
Message-ID: <20100607173041.GS7248@trinity.fluff.org>


On Sun, Jun 06, 2010 at 02:03:39PM +0900, Kyungmin Park wrote:
> Dear all,
> 
> FYI: My team release the qemu support on s5pc110 at
> http://en.sourceforge.jp/projects/sfnet_slp-emulator/

Interesting, any plans on merginging it back into qemu?
 
> You can find a s5pc110 files at hw directories.
> 
> The current mainline kernel, aquila and goni is will be run with this qemu.
> 
> Thank you,
> Kyungmin Park
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From cbouatmailru at gmail.com  Mon Jun  7 13:36:30 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Mon, 7 Jun 2010 21:36:30 +0400
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
Message-ID: <20100607173630.GA10489@oksana.dev.rtsoft.ru>

To support PI or robust mutexes, the kernel needs to perform some
operations atomically on userspace addresses, and yet ARM lacked
the support for the SMP case.

ARMv6 adds exclusive access variants of ldr and str instructions,
which means that support for PI/robust mutexes should now be
relatively straightforward.

Note that with this patch, if we run ARMv6 or greater, we'll use
atomic instructions no matter if it's SMP or UP kernel (just as we
do in atomic.h).

This has been tested on an ARM11 MPCore machine (ARMv6K), but I
also plan to test it with some Cortex-A9 (ARMv7) soon.

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/include/asm/futex.h |  125 +++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 122 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 540a044..acdbebb 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -3,17 +3,134 @@
 
 #ifdef __KERNEL__
 
-#ifdef CONFIG_SMP
+#if defined(CONFIG_SMP) && __LINUX_ARM_ARCH__ < 6
 
 #include <asm-generic/futex.h>
 
-#else /* !SMP, we can work around lack of atomic ops by disabling preemption */
+#else
 
 #include <linux/futex.h>
 #include <linux/preempt.h>
 #include <linux/uaccess.h>
 #include <asm/errno.h>
 
+#if __LINUX_ARM_ARCH__ >= 6
+
+#define __futex_atomic_op(insn, res, ret, oldval, uaddr, oparg)	\
+	__asm__ __volatile__(					\
+	"1:	ldrex	%2, [%3]\n"				\
+	"	" insn "\n"					\
+	"2:	strex	%0, %1, [%3]\n"				\
+	"	teq	%0, #0\n"				\
+	"	bne 1b\n"					\
+	"	mov	%1, #0\n"				\
+	"3:\n"							\
+	"	.pushsection __ex_table,\"a\"\n"		\
+	"	.align	3\n"					\
+	"	.long	1b, 4f, 2b, 4f\n"			\
+	"	.popsection\n"					\
+	"	.pushsection .fixup,\"ax\"\n"			\
+	"4:	mov	%1, %5\n"				\
+	"	b	3b\n"					\
+	"	.popsection"					\
+	: "=&r" (res), "=&r" (ret), "=&r" (oldval)		\
+	: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT)		\
+	: "cc", "memory")
+
+static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
+{
+	int op = (encoded_op >> 28) & 7;
+	int cmp = (encoded_op >> 24) & 15;
+	int oparg = (encoded_op << 8) >> 20;
+	int cmparg = (encoded_op << 20) >> 20;
+	int oldval = 0, ret;
+	unsigned long res;
+
+	if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
+		oparg = 1 << oparg;
+
+	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+		return -EFAULT;
+
+	pagefault_disable();	/* implies preempt_disable() */
+
+	switch (op) {
+	case FUTEX_OP_SET:
+		__futex_atomic_op("mov	%1, %4", res, ret, oldval, uaddr, oparg);
+		break;
+	case FUTEX_OP_ADD:
+		__futex_atomic_op("add	%1, %2, %4", res, ret, oldval, uaddr, oparg);
+		break;
+	case FUTEX_OP_OR:
+		__futex_atomic_op("orr	%1, %2, %4", res, ret, oldval, uaddr, oparg);
+		break;
+	case FUTEX_OP_ANDN:
+		__futex_atomic_op("and	%1, %2, %4", res, ret, oldval, uaddr, ~oparg);
+		break;
+	case FUTEX_OP_XOR:
+		__futex_atomic_op("eor	%1, %2, %4", res, ret, oldval, uaddr, oparg);
+		break;
+	default:
+		ret = -ENOSYS;
+	}
+
+	pagefault_enable();	/* subsumes preempt_enable() */
+
+	if (!ret) {
+		switch (cmp) {
+		case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
+		case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
+		case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
+		case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
+		case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
+		case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
+		default: ret = -ENOSYS;
+		}
+	}
+	return ret;
+}
+
+static inline int
+futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
+{
+	unsigned long ret;
+	unsigned long res;
+
+	if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+		return -EFAULT;
+
+	smp_mb();
+
+	do {
+		asm volatile("@futex_atomic_cmpxchg_inatomic\n"
+		"1:	ldrex	%1, [%2]\n"
+		"	mov	%0, #0\n"
+		"	teq	%1, %3\n"
+		"	it      eq @ explicit IT needed for the 2b label\n"
+		"2:	strexeq %0, %4, [%2]\n"
+		"3:\n"
+		"	.pushsection __ex_table,\"a\"\n"
+		"	.align	3\n"
+		"	.long	1b, 4f, 2b, 4f\n"
+		"	.popsection\n"
+		"	.pushsection .fixup,\"ax\"\n"
+		"4:	mov	%0, #0\n"
+		"	mov	%1, %5\n"
+		"	b	3b\n"
+		"	.popsection"
+			: "=&r" (res), "=&r" (ret)
+			: "r" (uaddr), "Ir" (oldval), "r" (newval),
+			  "Ir" (-EFAULT)
+			: "memory", "cc");
+	} while (res);
+
+	smp_mb();
+
+	return ret;
+}
+
+#else /* we can work around lack of atomic ops by disabling preemption */
+
 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)	\
 	__asm__ __volatile__(					\
 	"1:	ldrt	%1, [%2]\n"				\
@@ -119,7 +236,9 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
 	return val;
 }
 
-#endif /* !SMP */
+#endif
+
+#endif
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_ARM_FUTEX_H */
-- 
1.7.0.5


From jic23 at cam.ac.uk  Mon Jun  7 13:49:19 2010
From: jic23 at cam.ac.uk (Jonathan Cameron)
Date: Mon,  7 Jun 2010 18:49:19 +0100
Subject: [PATCH] pxa168 and pxa930 build fix - plat-pxa/pmu.c dependent on
	ARCH_PXA for IRQ_PMU
Message-ID: <1275932959-474-1-git-send-email-jic23@cam.ac.uk>

Signed-off-by: Jonathan Cameron <jic23 at cam.ac.uk>
---
 Found this build issue whilst browsing kautobuild logs.
 There may well be a better fix but until someone with
 a board in ARCH_MMP can test it, lets just not build
 pmu.c.  Can't find equivalent fix in Eric's tree so I
 think this is still a live problem.

 arch/arm/plat-pxa/Makefile |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index 6187edf..a17cc0c 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -2,8 +2,9 @@
 # Makefile for code common across different PXA processor families
 #
 
-obj-y	:= dma.o pmu.o
+obj-y	:= dma.o
 
+obj-$(CONFIG_ARCH_PXA)		+= pmu.o
 obj-$(CONFIG_GENERIC_GPIO)	+= gpio.o
 obj-$(CONFIG_PXA3xx)		+= mfp.o
 obj-$(CONFIG_ARCH_MMP)		+= mfp.o
-- 
1.6.4.4



From dhylands at gmail.com  Mon Jun  7 13:58:04 2010
From: dhylands at gmail.com (Dave Hylands)
Date: Mon, 7 Jun 2010 10:58:04 -0700
Subject: No subject
Message-ID: <AANLkTikxfktI7Heocg8kaBFziT3CXMzRzr-RJcXSQhbG@mail.gmail.com>

Hi,

I'm trying to understand what I need to be concerned about with SMP
processors and sharing global data (in particular a dual Cortex-A9)

I'm familiar with spinlocks, but in this case I'm trying to work with
some lockless data structures.

What I'm not sure is whether the following would work. Suppose I have
a couple of 8-bit get/put indicies which are in adjacent memory
locations (within the same 32-bit word).

If I have an ISR and a thread running on an SMP core, and the ISR is
running on one core and the thread is running on a second core, if the
ISR were to only write to the put pointer and the thread were only to
write to the get pointer, does the cache maintain consistency? Or do
the get and put pointers need to be in separate cache lines?

Another way of asking this: If both cores are writing to the same
32-bit word (but different bytes) do the writes collide?

--
Dave Hylands
Shuswap, BC, Canada
http://www.DaveHylands.com/


From jic23 at cam.ac.uk  Mon Jun  7 14:49:33 2010
From: jic23 at cam.ac.uk (Jonathan Cameron)
Date: Mon,  7 Jun 2010 19:49:33 +0100
Subject: [PATCH] mx31lilly: prevent ulpi calls if !USB_CONFIG_ULPI
Message-ID: <1275936573-21108-1-git-send-email-jic23@cam.ac.uk>

Signed-off-by: Jonathan Cameron <jic23 at cam.ac.uk>
---
 All of the mx3 boards that use ulpi are suitably protected.
 This currently makes mx3_defconfig fail as highlighted by
 Kautobuild.  Sorry for noise if a fix is already on it's way!

 arch/arm/mach-mx3/mach-mx31lilly.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index d3d5877..6827c68 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -114,6 +114,7 @@ static struct platform_device physmap_flash_device = {
 };
 
 /* USB */
+#if defined(CONFIG_USB_ULPI)
 
 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
 			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
@@ -243,6 +244,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
 	.portsc	= MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
 	.flags	= MXC_EHCI_POWER_PINS_ENABLED,
 };
+#endif /* USB_ULPI */
 
 static struct platform_device *devices[] __initdata = {
 	&smsc91x_device,
@@ -321,6 +323,7 @@ static void __init mx31lilly_board_init(void)
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	/* USB */
+#if defined(CONFIG_USB_ULPI)
 	usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
 				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
 	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
@@ -328,6 +331,7 @@ static void __init mx31lilly_board_init(void)
 
 	mxc_register_device(&mxc_usbh1, &usbh1_pdata);
 	mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
 }
 
 static void __init mx31lilly_timer_init(void)
-- 
1.6.4.4



From daniel at caiaq.de  Mon Jun  7 15:01:17 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Mon, 7 Jun 2010 21:01:17 +0200
Subject: [PATCH] mx31lilly: prevent ulpi calls if !USB_CONFIG_ULPI
In-Reply-To: <1275936573-21108-1-git-send-email-jic23@cam.ac.uk>
References: <1275936573-21108-1-git-send-email-jic23@cam.ac.uk>
Message-ID: <20100607190117.GA2695@buzzloop.caiaq.de>

On Mon, Jun 07, 2010 at 07:49:33PM +0100, Jonathan Cameron wrote:
> Signed-off-by: Jonathan Cameron <jic23 at cam.ac.uk>
> ---
>  All of the mx3 boards that use ulpi are suitably protected.
>  This currently makes mx3_defconfig fail as highlighted by
>  Kautobuild.  Sorry for noise if a fix is already on it's way!

There is actually. Have a look at Sascha's mxc trees.

Thanks, anyway :)

Daniel


> 
>  arch/arm/mach-mx3/mach-mx31lilly.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
> index d3d5877..6827c68 100644
> --- a/arch/arm/mach-mx3/mach-mx31lilly.c
> +++ b/arch/arm/mach-mx3/mach-mx31lilly.c
> @@ -114,6 +114,7 @@ static struct platform_device physmap_flash_device = {
>  };
>  
>  /* USB */
> +#if defined(CONFIG_USB_ULPI)
>  
>  #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
>  			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
> @@ -243,6 +244,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
>  	.portsc	= MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
>  	.flags	= MXC_EHCI_POWER_PINS_ENABLED,
>  };
> +#endif /* USB_ULPI */
>  
>  static struct platform_device *devices[] __initdata = {
>  	&smsc91x_device,
> @@ -321,6 +323,7 @@ static void __init mx31lilly_board_init(void)
>  	platform_add_devices(devices, ARRAY_SIZE(devices));
>  
>  	/* USB */
> +#if defined(CONFIG_USB_ULPI)
>  	usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
>  				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
>  	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
> @@ -328,6 +331,7 @@ static void __init mx31lilly_board_init(void)
>  
>  	mxc_register_device(&mxc_usbh1, &usbh1_pdata);
>  	mxc_register_device(&mxc_usbh2, &usbh2_pdata);
> +#endif
>  }
>  
>  static void __init mx31lilly_timer_init(void)
> -- 
> 1.6.4.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From mike.rapoport at gmail.com  Mon Jun  7 15:37:16 2010
From: mike.rapoport at gmail.com (Mike Rapoport)
Date: Mon, 7 Jun 2010 22:37:16 +0300
Subject: pxa300 - DDRAM base value
In-Reply-To: <1275892191.3501.17.camel@balakrishnan-desktop>
References: <1275371058.7001.35.camel@balakrishnan-desktop>
	<201006051919.17738.marek.vasut@gmail.com>
	<AANLkTil5TWYILcdp872as8S8LMqQWhPYWLt7cxs2lUm5@mail.gmail.com>
	<201006061834.50297.marek.vasut@gmail.com>
	<1275892191.3501.17.camel@balakrishnan-desktop>
Message-ID: <AANLkTinKc9Uc6QeKYogK3h1kHsOU1p6Qp1kWgn0J8cMA@mail.gmail.com>

> hi,
> ????? Now, I can able to boot after editing following files
> arch/arm/mach-pxa/Makefile.boot and arch/arm/mach/pxa/include/mach/memory.h
> (0x80000000 changed to 0xa0000000). My doubt is
> 1.why 0x80000000 (DDR phy address) is aliased to 0xa0000000 in pxa
> architecture?
> 2.In my development board two DDRAMs mapped at 0x80000000-0x88000000 and
> 0xc0000000-0xc8000000, how can I inform to kernel about this different bank
> and size?.

enable CONFIG_HIGHMEM

> My Boot loader details,
> ------------------------------
> =>bdi
> arch_number = 0x00000B04
> env_t?????? = 0x00000000
> boot_params = 0x80000100
> DRAM bank?? = 0x00000000
> -> start??? = 0x80000000
> -> size???? = 0x08000000
> DRAM bank?? = 0x00000001
> -> start??? = 0xC0000000
> -> size???? = 0x08000000
> ethaddr???? = 08:00:3e:26:0a:5b
> ip_addr???? = 192.168.0.21
> baudrate??? = 115200 bps
> =>ver
> U-Boot 2010.03 (Jun 01 2010 - 14:27:43)
>
>
> With Thanks
> J.Balakrishnan
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>



-- 
	Sincerely Yours,
		Mike.


From robert.jarzmik at free.fr  Mon Jun  7 15:41:37 2010
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Mon, 07 Jun 2010 21:41:37 +0200
Subject: [PATCH] pxa2xx/cpufreq: Fix DRI computation
In-Reply-To: <1275698808-31166-1-git-send-email-marek.vasut@gmail.com> (Marek
	Vasut's message of "Sat\, 5 Jun 2010 02\:46\:48 +0200")
References: <1275698808-31166-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <87bpbmocjy.fsf@free.fr>

Marek Vasut <marek.vasut at gmail.com> writes:

> The DRI field was incorrectly computed, causing various hangs and weird
> behaviour on PXA2xx machines. This patch introduces the DRI computation
> according to the PXA255 (January 2004) and PXA270 (MV-S301039-00 Rev. A)
> datasheets.

Hi Marek,

I'll help a bit in the review here, but I need a few days.

Meanwhile, I began the review and I have a question : did you check
MDCNFG_DRAC0() and MDCNFG_DRAC2() definitions ? As I check my TRM, it should be,
according to my manual :
+ #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 19) & 0x3)
+ #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 3) & 0x3)
- #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
- #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)

While I was checking the calculation, that rows calculation doesn't fit. Hence I
wonder if init_sdram_rows() will be correct.
I'll send a full review soon, don't be too quick with V2 please.

Cheers.

--
Robert


From linux at arm.linux.org.uk  Mon Jun  7 15:44:57 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 7 Jun 2010 20:44:57 +0100
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
In-Reply-To: <20100607173630.GA10489@oksana.dev.rtsoft.ru>
References: <20100607173630.GA10489@oksana.dev.rtsoft.ru>
Message-ID: <20100607194457.GC7220@n2100.arm.linux.org.uk>

On Mon, Jun 07, 2010 at 09:36:30PM +0400, Anton Vorontsov wrote:
> To support PI or robust mutexes, the kernel needs to perform some
> operations atomically on userspace addresses, and yet ARM lacked
> the support for the SMP case.
> 
> ARMv6 adds exclusive access variants of ldr and str instructions,
> which means that support for PI/robust mutexes should now be
> relatively straightforward.

It isn't this straight forward.  You're now bypassing the MMU protections
in that 'strex' can bypass the read-only protection of the user page.
This can result in the zero BSS page being corrupted, or worse corruption
to page cache pages.


From marek.vasut at gmail.com  Mon Jun  7 15:43:16 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 7 Jun 2010 21:43:16 +0200
Subject: pxa300 - DDRAM base value
In-Reply-To: <AANLkTinKc9Uc6QeKYogK3h1kHsOU1p6Qp1kWgn0J8cMA@mail.gmail.com>
References: <1275371058.7001.35.camel@balakrishnan-desktop>
	<1275892191.3501.17.camel@balakrishnan-desktop>
	<AANLkTinKc9Uc6QeKYogK3h1kHsOU1p6Qp1kWgn0J8cMA@mail.gmail.com>
Message-ID: <201006072143.16136.marek.vasut@gmail.com>

Dne Po 7. ?ervna 2010 21:37:16 Mike Rapoport napsal(a):
> > hi,
> >       Now, I can able to boot after editing following files
> > arch/arm/mach-pxa/Makefile.boot and
> > arch/arm/mach/pxa/include/mach/memory.h (0x80000000 changed to
> > 0xa0000000). My doubt is
> > 1.why 0x80000000 (DDR phy address) is aliased to 0xa0000000 in pxa
> > architecture?
> > 2.In my development board two DDRAMs mapped at 0x80000000-0x88000000 and
> > 0xc0000000-0xc8000000, how can I inform to kernel about this different
> > bank and size?.
> 
> enable CONFIG_HIGHMEM

Mike, that wont help him as he has PHYS_OFFSET=0xa0000000 . Selecting 
CONFIG_HIGHMEM will only cause the pages for RAM below 0xa0000000 to have 
incorrectly computated descriptor addresses (or maybe will be ignored).

The page descriptors for RAM at PA 0xa0000000 are at VA 0xc0000000 + some offset 
(there's an easy linear formula to compute their offset). Now if you feed that 
formula with 0x80000000, the page descriptors will end below 0xc0000000, which 
isn't a valid VA, therefore the descriptors will not be valid either (in the 
better case, but it will hang the kernel at early stage anyway).

Therefore there are two ways -- either use what I suggested earlier or wait 
until the PHYS_OFFSET is dynamically computated (check Eric's patchset).

Cheers
> 
> > My Boot loader details,
> > ------------------------------
> > =>bdi
> > arch_number = 0x00000B04
> > env_t       = 0x00000000
> > boot_params = 0x80000100
> > DRAM bank   = 0x00000000
> > -> start    = 0x80000000
> > -> size     = 0x08000000
> > DRAM bank   = 0x00000001
> > -> start    = 0xC0000000
> > -> size     = 0x08000000
> > ethaddr     = 08:00:3e:26:0a:5b
> > ip_addr     = 192.168.0.21
> > baudrate    = 115200 bps
> > =>ver
> > U-Boot 2010.03 (Jun 01 2010 - 14:27:43)
> > 
> > 
> > With Thanks
> > J.Balakrishnan
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From dhylands at gmail.com  Mon Jun  7 16:11:17 2010
From: dhylands at gmail.com (Dave Hylands)
Date: Mon, 7 Jun 2010 13:11:17 -0700
Subject: Question about SMP
Message-ID: <AANLkTilJOUmarsLJJtNzbVwrZLbLAD29gp2SHL0TZCUQ@mail.gmail.com>

Hi,

(filled in subject line this time - Doh).

I'm trying to understand what I need to be concerned about with SMP
processors and sharing global data (in particular a dual Cortex-A9)

I'm familiar with spinlocks, but in this case I'm trying to work with
some lockless data structures.

What I'm not sure is whether the following would work. Suppose I have
a couple of 8-bit get/put indicies which are in adjacent memory
locations (within the same 32-bit word).

If I have an ISR and a thread running on an SMP core, and the ISR is
running on one core and the thread is running on a second core, if the
ISR were to only write to the put pointer and the thread were only to
write to the get pointer, does the cache maintain consistency? Or do
the get and put pointers need to be in separate cache lines?

Another way of asking this: If both cores are writing to the same
32-bit word (but different bytes) do the writes collide?

--
Dave Hylands
Shuswap, BC, Canada
http://www.DaveHylands.com/


From cbouatmailru at gmail.com  Mon Jun  7 16:27:01 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 8 Jun 2010 00:27:01 +0400
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
In-Reply-To: <20100607194457.GC7220@n2100.arm.linux.org.uk>
References: <20100607173630.GA10489@oksana.dev.rtsoft.ru>
	<20100607194457.GC7220@n2100.arm.linux.org.uk>
Message-ID: <20100607202701.GA14529@oksana.dev.rtsoft.ru>

On Mon, Jun 07, 2010 at 08:44:57PM +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 07, 2010 at 09:36:30PM +0400, Anton Vorontsov wrote:
> > To support PI or robust mutexes, the kernel needs to perform some
> > operations atomically on userspace addresses, and yet ARM lacked
> > the support for the SMP case.
> > 
> > ARMv6 adds exclusive access variants of ldr and str instructions,
> > which means that support for PI/robust mutexes should now be
> > relatively straightforward.
> 
> It isn't this straight forward.  You're now bypassing the MMU protections
> in that 'strex' can bypass the read-only protection of the user page.
> This can result in the zero BSS page being corrupted, or worse corruption
> to page cache pages.

Interesting. I don't pretend I understand all MMU details, but arm.com
says "If a processor does an STR on a memory region that it has already
marked as exclusive, this does not clear the tag."

So, can we solve this by

ldrex
...
strt newval
   ^ may cause exception, but doesn't clear the tag, so we're still atomic
strex <- clears the tag

.fixup
	strex oldval <- just clear the tag
	return -EFAULT;

Thanks!

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2


From ryan at bluewatersys.com  Mon Jun  7 16:35:42 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Tue, 08 Jun 2010 08:35:42 +1200
Subject: [alsa-devel] [RFC PATCH v3 0/3] ep93xx i2s audio
In-Reply-To: <20100607132634.GE5993@sirena.org.uk>
References: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
	<20100607132634.GE5993@sirena.org.uk>
Message-ID: <4C0D581E.3010802@bluewatersys.com>

Mark Brown wrote:
> On Fri, Jun 04, 2010 at 05:11:22PM +1200, Ryan Mallon wrote:
>> The following patch series adds support for i2s audio on the ep93xx,
>> with the Snapper CL15 used as an example implementation.
> 
> Please do remember to CC maintainers on patches.  I've had to remind you
> about this before, it's really not helpful to drop the people you're
> expecting to review the patches - it'll tend to delay things or lead to
> the patches getting missed.  From a code point of view this looks fine
> but we'll need an arch maintainer to sign off on that bit of the code.
> I've applied 2/3 since that has no arch/arm elements.

Sorry, again. I copied the CC list from the last series I sent. I must
have missed you accidentally.

Thanks for picking this up.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From ryan at bluewatersys.com  Mon Jun  7 16:38:19 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Tue, 08 Jun 2010 08:38:19 +1200
Subject: [alsa-devel] [RFC PATCH v3 0/3] ep93xx i2s audio
In-Reply-To: <1275914732.3045.105.camel@odin>
References: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
	<1275914732.3045.105.camel@odin>
Message-ID: <4C0D58BB.5030505@bluewatersys.com>

Liam Girdwood wrote:
> On Fri, 2010-06-04 at 17:11 +1200, Ryan Mallon wrote:
>> The following patch series adds support for i2s audio on the ep93xx,
>> with the Snapper CL15 used as an example implementation.
>>
>> This version fixes a number of things from the previous round:
>>  - Removed unused #defines
>>  - Set symmetric rates for the cpu dai
>>  - Fixed the sdiv/lrdiv calculation loop
>>  - Moved the cpu dai registration
>>  - Removed empty ep93xx_pcm_prepare callback
>>  - Fixed enable/disable when both capture and playback are running
>>  
>> Capture still does not work. The dma is running, but the captured data
>> is all zeros (tested used arecord and loopback). I have a 2.6.20
>> kernel with ep93xx i2s audio working an capture works there on the
>> same hardware. I have spent sometime looking into this, but can't see
>> the problem. Would appreciate if someone can lend some insight as to
>> what I have done wrong.
>>
>> Ryan Mallon (3):
>>   ep93xx i2s core support
>>   ep93xx i2s audio driver
>>   Snapper cl15 audio support
> 
> All
> 
> Acked-by: Liam Girdwood <lrg at slimlogic.co.uk>

Russell, Mark has picked up patch 2/3 via the alsa tree. Should I submit
1/3 and 3/3 via the arm patch system with Liam's ack?

Thanks,
~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From troy.kisky at boundarydevices.com  Mon Jun  7 16:41:58 2010
From: troy.kisky at boundarydevices.com (Troy Kisky)
Date: Mon, 07 Jun 2010 13:41:58 -0700
Subject: [PATCH] mxc: Fix pad names for imx51
In-Reply-To: <20100604140959.GB2982@matterhorn.lan>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>	<20100604085320.GB25357@pengutronix.de>	<20100604105347.GA2982@matterhorn.lan>
	<20100604140959.GB2982@matterhorn.lan>
Message-ID: <4C0D5996.9050906@boundarydevices.com>

Amit Kucheria wrote:
> On 10 Jun 04, Amit Kucheria wrote:
>> On 10 Jun 04, Sascha Hauer wrote:
>>> On Thu, Jun 03, 2010 at 08:05:44PM +0800, Jason Wang wrote:
>>>>  
>>>> -#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
>>>> -#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
>>>> +#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, IOMUX_CONFIG_ALT1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
>>>> +#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, IOMUX_CONFIG_ALT1, 0x0, 0, MX51_UART3_PAD_CTRL)
>>> Urgs, there really is something wrong here.
>>>
>>> First of all, this define should be named MX51_PAD_UART3_RXD__GPIO_1_22
>>> as it describes the pad UART3_RXD in GPIO_1_22 mode. This seems to be
>>> wrong with many (all?) defines in this file. Amit, you should have read
>>> the comment ontop of this file which you copied from the i.MX35 part:
>> I'll admit that I was not completely conversant with the naming scheme then.
>> All the GPIO-related names have been reversed. The others seem fine.
>>
>>> /*
>>>  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
>>>  * If <padname> or <padmode> refers to a GPIO, it is named
>>>  * GPIO_<unit>_<num> see also iomux-v3.h
>>>  */
>> There was a comment below this:
>> /*
>>  * FIXME: This was converted using scripts from existing Freescale code to
>>  * this form used upstream. Need to verify the name format.
>>  */
>>
>> I obviously reversed the naming for all the GPIO pads.
>>
>>> This should be fixed before doing any other change to this file.
>> I'm preparing a patch now.
>>
> 
> Please find the patch attached.
> 
> You can see the output of diff without the whitespace changes here:
> http://paste.ubuntu.com/444628/
> 
> 
>>From 00a83837915e2056367b09dfc322ced601e67658 Mon Sep 17 00:00:00 2001
> Message-Id: <00a83837915e2056367b09dfc322ced601e67658.1275659667.git.amit.kucheria at canonical.com>
> From: Amit Kucheria <amit.kucheria at canonical.com>
> Date: Fri, 4 Jun 2010 16:50:27 +0300
> Subject: [PATCH] mxc: Fix pad names for imx51
> 
> The pads capable of being used as GPIOs had their pad-name and mode-name
> switched. Also fix the following:
> 
> - Whitespace fixes
> - Replace IOMUX_CONFIG_ALTn with 'n'
> 
> Signed-off-by: Amit Kucheria <amit.kucheria at canonical.com>
> ---
>  arch/arm/mach-mx5/board-mx51_babbage.c      |    2 +-
>  arch/arm/plat-mxc/include/mach/iomux-mx51.h |  533 +++++++++++++--------------
>  2 files changed, 252 insertions(+), 283 deletions(-)
> 
> diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
> index ed885f9..4f96d9c 100644
> --- a/arch/arm/mach-mx5/board-mx51_babbage.c
> +++ b/arch/arm/mach-mx5/board-mx51_babbage.c
> @@ -78,7 +78,7 @@ static struct pad_desc mx51babbage_pads[] = {
>  	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
>  
>  	/* USB HUB reset line*/
> -	MX51_PAD_GPIO_1_7__GPIO1_7,
> +	MX51_PAD_GPIO_1_7__GPIO_1_7,
>  };
>  
>  /* Serial ports */
> diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
> index ab0f95d..e8648bc 100644
> --- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
> +++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
> @@ -27,8 +27,8 @@ typedef enum iomux_config {
>  	IOMUX_CONFIG_ALT5,
>  	IOMUX_CONFIG_ALT6,
>  	IOMUX_CONFIG_ALT7,
> -	IOMUX_CONFIG_GPIO,	/* added to help user use GPIO mode */
> -	IOMUX_CONFIG_SION = 0x1 << 4,	/* LOOPBACK:MUX SION bit */
> +	IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
> +	IOMUX_CONFIG_SION = 0x1 << 4,   /* LOOPBACK:MUX SION bit */
>  } iomux_pin_cfg_t;
>  
>  /* Pad control groupings */
> @@ -50,285 +50,254 @@ typedef enum iomux_config {
>   * GPIO_<unit>_<num> see also iomux-v3.h
>   */
>  
> -/*
> - * FIXME: This was converted using scripts from existing Freescale code to
> - * this form used upstream. Need to verify the name format.
> - */
> -
> -/*						PAD      MUX   ALT INPSE PATH PADCTRL */
> -
> -#define MX51_PAD_GPIO_2_0__EIM_D16	IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_1__EIM_D17	IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_2__EIM_D18	IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_3__EIM_D19	IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_4__EIM_D20	IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_5__EIM_D21	IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_D21__GPIO_2_5	IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0,   0, MX51_GPIO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_6__EIM_D22	IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_7__EIM_D23	IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
> -
> -/* Babbage UART3 */
> -#define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
> -#define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
> -#define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
> -#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
> -
> -#define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_D30__EIM_D30	IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_D31__EIM_D31	IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
> -
> -#define MX51_PAD_GPIO_2_10__EIM_A16	IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_11__EIM_A17	IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_12__EIM_A18	IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_13__EIM_A19	IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_14__EIM_A20	IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_15__EIM_A21	IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_16__EIM_A22	IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_17__EIM_A23	IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
> -
> -#define MX51_PAD_GPIO_2_18__EIM_A24	IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_19__EIM_A25	IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_20__EIM_A26	IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_21__EIM_A27	IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_EB0__EIM_EB0	IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_EB1__EIM_EB1	IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_22__EIM_EB2	IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_23__EIM_EB3	IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
> -
> -#define MX51_PAD_GPIO_2_24__EIM_OE	IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_25__EIM_CS0	IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_26__EIM_CS1	IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_27__EIM_CS2	IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_28__EIM_CS3	IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_29__EIM_CS4	IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_30__EIM_CS5	IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_2_31__EIM_DTACK	IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
> -
> -#define MX51_PAD_GPIO_3_1__EIM_LBA	IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_2__EIM_CRE	IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DRAM_CS1__DRAM_CS1	IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_3__NANDF_WE_B	IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_4__NANDF_RE_B	IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_5__NANDF_ALE	IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_6__NANDF_CLE	IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_7__NANDF_WP_B	IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_8__NANDF_RB0	IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_9__NANDF_RB1	IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_10__NANDF_RB2	IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_11__NANDF_RB3	IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_12__GPIO_NAND	IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
> -/* REVISIT: Not sure of these values
> -
> -  #define MX51_PAD_GPIO_1___NANDF_RB4	IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
> -  #define MX51_PAD_GPIO_3_13__NANDF_RB5	IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
> -  #define MX51_PAD_GPIO_3_15__NANDF_RB7	IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
> -*/
> -#define MX51_PAD_GPIO_3_14__NANDF_RB6	IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_16__NANDF_CS0	IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_17__NANDF_CS1	IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_18__NANDF_CS2	IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_19__NANDF_CS3	IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_20__NANDF_CS4	IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_21__NANDF_CS5	IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_22__NANDF_CS6	IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_23__NANDF_CS7	IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT	IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_25__NANDF_D15	IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_26__NANDF_D14	IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_27__NANDF_D13	IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_28__NANDF_D12	IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_29__NANDF_D11	IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_30__NANDF_D10	IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_31__NANDF_D9	IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_0__NANDF_D8	IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_1__NANDF_D7	IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_2__NANDF_D6	IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_3__NANDF_D5	IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_4__NANDF_D4	IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_5__NANDF_D3	IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_6__NANDF_D2	IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_7__NANDF_D1	IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_8__NANDF_D0	IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_12__CSI1_D8	IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_13__CSI1_D9	IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_D10__CSI1_D10	IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_D11__CSI1_D11	IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_D12__CSI1_D12	IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_D13__CSI1_D13	IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_D14__CSI1_D14	IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_D15__CSI1_D15	IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_D16__CSI1_D16	IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_D17__CSI1_D17	IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_D18__CSI1_D18	IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_D19__CSI1_D19	IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC	IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC	IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK	IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_MCLK__CSI1_MCLK	IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI1_PKE0__CSI1_PKE0	IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_9__CSI2_D12	IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_10__CSI2_D13	IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_11__CSI2_D14	IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_12__CSI2_D15	IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_11__CSI2_D16	IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_12__CSI2_D17	IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_11__CSI2_D18	IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_12__CSI2_D19	IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_13__CSI2_VSYNC	IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_14__CSI2_HSYNC	IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK	IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_CSI2_PKE0__CSI2_PKE0	IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_16__I2C1_CLK	IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_17__I2C1_DAT	IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD	IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD	IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_20__AUD3_BB_CK	IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_21__AUD3_BB_FS	IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_22__CSPI1_MOSI	IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_23__CSPI1_MISO	IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_24__CSPI1_SS0	IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_25__CSPI1_SS1	IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_26__CSPI1_RDY	IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_4_27__CSPI1_SCLK	IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
> -
> -/* Babbage UART1 */
> -#define MX51_PAD_UART1_RXD__UART1_RXD	IOMUX_PAD(0x618, 0x228,	IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
> -#define MX51_PAD_UART1_TXD__UART1_TXD	IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
> -#define MX51_PAD_UART1_RTS__UART1_RTS	IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
> -#define MX51_PAD_UART1_CTS__UART1_CTS	IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
> -
> -/* Babbage UART2 */
> -#define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
> -#define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
> -
> -#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_24__OWIRE_LINE	IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_KEY_ROW0__KEY_ROW0	IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_KEY_ROW1__KEY_ROW1	IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_KEY_ROW2__KEY_ROW2	IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_KEY_ROW3__KEY_ROW3	IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_KEY_COL0__KEY_COL0	IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_KEY_COL1__KEY_COL1	IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_KEY_COL2__KEY_COL2	IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_KEY_COL3__KEY_COL3	IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_KEY_COL4__KEY_COL4	IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_KEY_COL5__KEY_COL5	IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_USBH1_CLK__USBH1_CLK	IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_USBH1_DIR__USBH1_DIR	IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_USBH1_STP__USBH1_STP	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_USBH1_STP__GPIO_1_27	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_USBH1_NXT__USBH1_NXT	IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_0__DI1_PIN11	IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_1__DI1_PIN12	IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_2__DI1_PIN13	IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_3__DI1_D0_CS	IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_4__DI1_D1_CS	IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN	IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO	IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK	IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS	IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT0__DISP1_DAT0	IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT1__DISP1_DAT1	IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT2__DISP1_DAT2	IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT3__DISP1_DAT3	IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT4__DISP1_DAT4	IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT5__DISP1_DAT5	IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT6__DISP1_DAT6	IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT7__DISP1_DAT7	IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT8__DISP1_DAT8	IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT9__DISP1_DAT9	IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DI1_PIN3__DI1_PIN3	IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DI1_PIN2__DI1_PIN2	IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DI_GP1__DI_GP1	IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DI_GP2__DI_GP2	IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DI_GP3__DI_GP3	IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DI2_PIN4__DI2_PIN4	IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DI2_PIN2__DI2_PIN2	IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DI2_PIN3__DI2_PIN3	IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DI_GP4__DI_GP4	IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP2_DAT0__DISP2_DAT0	IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP2_DAT1__DISP2_DAT1	IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP2_DAT2__DISP2_DAT2	IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP2_DAT3__DISP2_DAT3	IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP2_DAT4__DISP2_DAT4	IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP2_DAT5__DISP2_DAT5	IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_19__DISP2_DAT6	IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_29__DISP2_DAT7	IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_30__DISP2_DAT8	IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_31__DISP2_DAT9	IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_SD1_CMD__SD1_CMD	IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_SD1_CLK__SD1_CLK	IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_SD1_DATA0__SD1_DATA0	IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_SD1_DATA1__SD1_DATA1	IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_SD1_DATA2__SD1_DATA2	IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_SD1_DATA3__SD1_DATA3	IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_0__GPIO1_0	IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_1__GPIO1_1	IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_SD2_CMD__SD2_CMD	IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_SD2_CLK__SD2_CLK	IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_SD2_DATA0__SD2_DATA0	IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_SD2_DATA1__SD2_DATA1	IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_SD2_DATA2__SD2_DATA2	IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_SD2_DATA3__SD2_DATA3	IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_2__GPIO1_2	IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_3__GPIO1_3	IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_4__GPIO1_4	IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_5__GPIO1_5	IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_7__GPIO1_7	IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
> -#define MX51_PAD_GPIO_1_8__GPIO1_8	IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
> -						(PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
> -#define MX51_PAD_GPIO_1_9__GPIO1_9	IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
> -
> -/* EIM */
> -#define MX51_PAD_EIM_DA0__EIM_DA0	IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA1__EIM_DA1	IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA2__EIM_DA2	IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA3__EIM_DA3	IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA4__EIM_DA4	IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA5__EIM_DA5	IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA6__EIM_DA6	IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA7__EIM_DA7	IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
> -
> -#define MX51_PAD_EIM_DA8__EIM_DA8	IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA9__EIM_DA9	IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA10__EIM_DA10	IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA11__EIM_DA11	IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA12__EIM_DA12	IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA13__EIM_DA13	IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA14__EIM_DA14	IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
> -#define MX51_PAD_EIM_DA15__EIM_DA15	IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
> +/*							  PAD    MUX   ALT INPSE PATH PADCTRL */
> +#define MX51_PAD_EIM_DA0__EIM_DA0		IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA1__EIM_DA1		IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA2__EIM_DA2		IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA3__EIM_DA3		IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA4__EIM_DA4		IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA5__EIM_DA5		IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA6__EIM_DA6		IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA7__EIM_DA7		IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA8__EIM_DA8		IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA9__EIM_DA9		IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA10__EIM_DA10		IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA11__EIM_DA11		IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA12__EIM_DA12		IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA13__EIM_DA13		IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA14__EIM_DA14		IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DA15__EIM_DA15		IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_D16__GPIO_2_0              IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_D17__GPIO_2_1              IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_D18__GPIO_2_2              IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_D19__GPIO_2_3              IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_D20__GPIO_2_4              IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_D21__GPIO_2_5		IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
> +#define MX51_PAD_EIM_D22__GPIO_2_6              IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_D23__GPIO_2_7              IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
> +#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
> +#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
> +#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
> +#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_A16__GPIO_2_10             IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_A17__GPIO_2_11             IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_A18__GPIO_2_12             IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_A19__GPIO_2_13             IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_A20__GPIO_2_14             IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_A21__GPIO_2_15             IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_A22__GPIO_2_16             IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_A23__GPIO_2_17             IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_A24__GPIO_2_18             IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_A25__GPIO_2_19             IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_A26__GPIO_2_20             IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_A27__GPIO_2_21             IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_EB2__GPIO_2_22             IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_EB3__GPIO_2_23             IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_OE__GPIO_2_24              IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_CS0__GPIO_2_25             IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_CS1__GPIO_2_26             IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_CS2__GPIO_2_27             IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_CS3__GPIO_2_28             IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_CS4__GPIO_2_29             IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_CS5__GPIO_2_30             IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_DTACK__GPIO_2_31           IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_LBA__GPIO_3_1              IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_EIM_CRE__GPIO_3_2              IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4D0, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_WE_B__GPIO_3_3           IOMUX_PAD(0x4E4, 0x108, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_RE_B__GPIO_3_4           IOMUX_PAD(0x4E8, 0x10C, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_ALE__GPIO_3_5            IOMUX_PAD(0x4EC, 0x110, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_CLE__GPIO_3_6            IOMUX_PAD(0x4F0, 0x114, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_WP_B__GPIO_3_7           IOMUX_PAD(0x4F4, 0x118, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_GPIO_NAND__GPIO_3_12           IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_CS0__GPIO_3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_CS1__GPIO_3_17           IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_CS2__GPIO_3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_CS3__GPIO_3_19           IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_CS4__GPIO_3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_CS5__GPIO_3_21           IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_CS6__GPIO_3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_CS7__GPIO_3_23           IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D11__GPIO_3_29           IOMUX_PAD(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D10__GPIO_3_30           IOMUX_PAD(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D9__GPIO_3_31            IOMUX_PAD(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D8__GPIO_4_0             IOMUX_PAD(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D7__GPIO_4_1             IOMUX_PAD(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D6__GPIO_4_2             IOMUX_PAD(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D5__GPIO_4_3             IOMUX_PAD(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D4__GPIO_4_4             IOMUX_PAD(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D3__GPIO_4_5             IOMUX_PAD(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D2__GPIO_4_6             IOMUX_PAD(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D1__GPIO_4_7             IOMUX_PAD(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_NANDF_D0__GPIO_4_8             IOMUX_PAD(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_D8__GPIO_3_12             IOMUX_PAD(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_D9__GPIO_3_13             IOMUX_PAD(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5B4, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5B8, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI1_PKE0__CSI1_PKE0           IOMUX_PAD(0x860, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI2_D12__GPIO_4_9             IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI2_D13__GPIO_4_10            IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI2_D14__GPIO_4_11            IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI2_D15__GPIO_4_12            IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI2_D16__GPIO_4_11            IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI2_D17__GPIO_4_12            IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI2_D18__GPIO_4_11            IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI2_D19__GPIO_4_12            IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI2_VSYNC__GPIO_4_13          IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI2_HSYNC__GPIO_4_14          IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15         IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_I2C1_CLK__GPIO_4_16            IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_I2C1_DAT__GPIO_4_17            IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18         IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19         IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_AUD3_BB_CK__GPIO_4_20          IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_AUD3_BB_FS__GPIO_4_21          IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSPI1_MOSI__GPIO_4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSPI1_MISO__GPIO_4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSPI1_SS0__GPIO_4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSPI1_SS1__GPIO_4_25           IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSPI1_RDY__GPIO_4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
> +#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
> +#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
> +#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
> +#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
> +#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
> +#define MX51_PAD_UART3_RXD__GPIO_1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_UART3_TXD__GPIO_1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_OWIRE_LINE__GPIO_1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_USBH1_STP__GPIO_1_27           IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
> +#define MX51_PAD_DI1_PIN11__GPIO_3_0            IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI_GP1__DI_GP1                 IOMUX_PAD(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI_GP2__DI_GP2                 IOMUX_PAD(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI_GP3__DI_GP3                 IOMUX_PAD(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DI_GP4__DI_GP4                 IOMUX_PAD(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT6__GPIO_1_19          IOMUX_PAD(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT7__GPIO_1_29          IOMUX_PAD(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT8__GPIO_1_30          IOMUX_PAD(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT9__GPIO_1_31          IOMUX_PAD(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_0__GPIO_1_0		IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_1__GPIO_1_1		IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
> +#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)

Why all the stuttering?
Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?

>  
>  #endif /* __MACH_IOMUX_MX51_H__ */



From catalin.marinas at arm.com  Mon Jun  7 16:56:10 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 07 Jun 2010 21:56:10 +0100
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
In-Reply-To: <20100607194457.GC7220@n2100.arm.linux.org.uk>
References: <20100607173630.GA10489@oksana.dev.rtsoft.ru>
	<20100607194457.GC7220@n2100.arm.linux.org.uk>
Message-ID: <1275944170.11056.7.camel@toshiba-laptop>

On Mon, 2010-06-07 at 20:44 +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 07, 2010 at 09:36:30PM +0400, Anton Vorontsov wrote:
> > To support PI or robust mutexes, the kernel needs to perform some
> > operations atomically on userspace addresses, and yet ARM lacked
> > the support for the SMP case.
> >
> > ARMv6 adds exclusive access variants of ldr and str instructions,
> > which means that support for PI/robust mutexes should now be
> > relatively straightforward.
> 
> It isn't this straight forward.  You're now bypassing the MMU protections
> in that 'strex' can bypass the read-only protection of the user page.
> This can result in the zero BSS page being corrupted, or worse corruption
> to page cache pages.

Do you mean STREX in SVC mode targeting user pages? I keep posting a
patch for more than a year :) which removes the domains switching and
makes user pages read-only for both kernel and user space.

Making user RO / kernel RO pages doesn't necessarily require the full
domains patch, just the parts that deal with the vectors page and FIQ
setting (though we really need the whole domains patch in the kernel for
many reasons).

Such permissions are also required for Leif's patch which handles SWP
emulation via STREX/LDREX.

-- 
Catalin



From amit.kucheria at canonical.com  Mon Jun  7 17:04:48 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Tue, 8 Jun 2010 00:04:48 +0300
Subject: [PATCH] mxc: Fix pad names for imx51
In-Reply-To: <4C0D5996.9050906@boundarydevices.com>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100604085320.GB25357@pengutronix.de>
	<20100604105347.GA2982@matterhorn.lan>
	<20100604140959.GB2982@matterhorn.lan>
	<4C0D5996.9050906@boundarydevices.com>
Message-ID: <20100607210448.GA2446@matterhorn.lan>

On 10 Jun 07, Troy Kisky wrote:

> > On 10 Jun 04, Amit Kucheria wrote:
> >

<snip>

> > +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27		IOMUX_PAD(0x614, 0x224,  3, 0x0,   0, NO_PAD_CTRL)

<snip>

> > +#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
> > +#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
> > +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
> > +#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
> > +#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
> > +#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
> > +#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
> > +#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
> > +#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
> 
> Why all the stuttering?
> Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
> 

Just following the convention use in the rest of imx devices. See the
following comment at the top of the file:

/*
 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
 * If <padname> or <padmode> refers to a GPIO, it is named
 * GPIO_<unit>_<num> see also iomux-v3.h
 */

We could use the short names for pads being used in their "native mode".
But as soon as we use the pad in a different mode, such as
PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.

Regards,
Amit

-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------


From catalin.marinas at arm.com  Mon Jun  7 17:05:57 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 07 Jun 2010 22:05:57 +0100
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
In-Reply-To: <20100607202701.GA14529@oksana.dev.rtsoft.ru>
References: <20100607173630.GA10489@oksana.dev.rtsoft.ru>
	<20100607194457.GC7220@n2100.arm.linux.org.uk>
	<20100607202701.GA14529@oksana.dev.rtsoft.ru>
Message-ID: <1275944757.11056.16.camel@toshiba-laptop>

On Mon, 2010-06-07 at 21:27 +0100, Anton Vorontsov wrote:
> On Mon, Jun 07, 2010 at 08:44:57PM +0100, Russell King - ARM Linux wrote:
> > On Mon, Jun 07, 2010 at 09:36:30PM +0400, Anton Vorontsov wrote:
> > > To support PI or robust mutexes, the kernel needs to perform some
> > > operations atomically on userspace addresses, and yet ARM lacked
> > > the support for the SMP case.
> > >
> > > ARMv6 adds exclusive access variants of ldr and str instructions,
> > > which means that support for PI/robust mutexes should now be
> > > relatively straightforward.
> >
> > It isn't this straight forward.  You're now bypassing the MMU protections
> > in that 'strex' can bypass the read-only protection of the user page.
> > This can result in the zero BSS page being corrupted, or worse corruption
> > to page cache pages.
> 
> Interesting. I don't pretend I understand all MMU details, but arm.com
> says "If a processor does an STR on a memory region that it has already
> marked as exclusive, this does not clear the tag."

Russell is probably referring to a STR or STREX in kernel mode that
writes to a read-only user page (currently mapped as kernel read/write).
Such write would succeed and it breaks the copy-on-write mechanism that
Linux uses for duplicating various pages. The original futex code uses
STRT which is executed with user permissions even if in kernel mode, so
it won't succeed (but raise a data abort which is handled by the
kernel).

But as I said, we already have patches to change the kernel R/W
permission for RO user pages.

-- 
Catalin



From ryan at bluewatersys.com  Mon Jun  7 17:09:26 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Tue, 08 Jun 2010 09:09:26 +1200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>	<4C083BCF.2060500@bluewatersys.com>	<201006040310.15019.marek.vasut@gmail.com>	<4C0853E1.1080005@bluewatersys.com>	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>	<20100604061034.GI6499@atomide.com>	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
Message-ID: <4C0D6006.7030700@bluewatersys.com>

Martin Guy wrote:
> Shame. I was about to post a Sim.One defconfig patch (while fully
> realizing that the choice of options is largely arbitrary. and copied
> ad-hoc from some other similar defconfig). While it's nice to be able
> to tell people "make foobar_defconfig; make (z|u|bz)Image" in reality
> the config is as arbitrary as the root filesystem in use (and should
> be chosen to match it).

Once the support runtime phys offset is merged it will be possible for
ep93xx_defconfig to support all of the ep93xx boards.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From troy.kisky at boundarydevices.com  Mon Jun  7 17:15:47 2010
From: troy.kisky at boundarydevices.com (Troy Kisky)
Date: Mon, 07 Jun 2010 14:15:47 -0700
Subject: [PATCH] mxc: Fix pad names for imx51
In-Reply-To: <20100607210448.GA2446@matterhorn.lan>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>	<20100604085320.GB25357@pengutronix.de>	<20100604105347.GA2982@matterhorn.lan>	<20100604140959.GB2982@matterhorn.lan>	<4C0D5996.9050906@boundarydevices.com>
	<20100607210448.GA2446@matterhorn.lan>
Message-ID: <4C0D6183.1010501@boundarydevices.com>

Amit Kucheria wrote:
> On 10 Jun 07, Troy Kisky wrote:
> 
>>> On 10 Jun 04, Amit Kucheria wrote:
>>>
> 
> <snip>
> 
>>> +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27		IOMUX_PAD(0x614, 0x224,  3, 0x0,   0, NO_PAD_CTRL)
> 
> <snip>
> 
>>> +#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
>>> +#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
>>> +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
>>> +#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
>>> +#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
>>> +#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
>>> +#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
>>> +#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
>>> +#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
>> Why all the stuttering?
>> Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
>>
> 
> Just following the convention use in the rest of imx devices. See the
> following comment at the top of the file:
> 
> /*
>  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
>  * If <padname> or <padmode> refers to a GPIO, it is named
>  * GPIO_<unit>_<num> see also iomux-v3.h
>  */
> 
> We could use the short names for pads being used in their "native mode".
> But as soon as we use the pad in a different mode, such as
> PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
> 
> Regards,
> Amit
> 

I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for
MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to

 /*
  * The naming convention for the pad modes is MX51_PAD_<padname>
  * or MX51_PAD_<padname>__<padmode> if padname != padmode.
  * If <padname> or <padmode> refers to a GPIO, it is named
  * GPIO_<unit>_<num> see also iomux-v3.h
  */




From marek.vasut at gmail.com  Mon Jun  7 17:20:35 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 7 Jun 2010 23:20:35 +0200
Subject: [PATCH] pxa2xx/cpufreq: Fix DRI computation
In-Reply-To: <87bpbmocjy.fsf@free.fr>
References: <1275698808-31166-1-git-send-email-marek.vasut@gmail.com>
	<87bpbmocjy.fsf@free.fr>
Message-ID: <201006072320.35473.marek.vasut@gmail.com>

Dne Po 7. ?ervna 2010 21:41:37 Robert Jarzmik napsal(a):
> Marek Vasut <marek.vasut at gmail.com> writes:
> > The DRI field was incorrectly computed, causing various hangs and weird
> > behaviour on PXA2xx machines. This patch introduces the DRI computation
> > according to the PXA255 (January 2004) and PXA270 (MV-S301039-00 Rev. A)
> > datasheets.
> 
> Hi Marek,
> 
> I'll help a bit in the review here, but I need a few days.
> 
> Meanwhile, I began the review and I have a question : did you check
> MDCNFG_DRAC0() and MDCNFG_DRAC2() definitions ? As I check my TRM, it
> should be, according to my manual :
> + #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 19) & 0x3)
> + #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 3) & 0x3)
> - #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
> - #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
> 
> While I was checking the calculation, that rows calculation doesn't fit.
> Hence I wonder if init_sdram_rows() will be correct.
> I'll send a full review soon, don't be too quick with V2 please.

Robert, this is actually a good catch, I'll try with this change, maybe it'll 
stop hanging finally.

Thanks!
> 
> Cheers.
> 
> --
> Robert


From marek.vasut at gmail.com  Mon Jun  7 17:26:09 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 7 Jun 2010 23:26:09 +0200
Subject: [PATCH] pxa2xx/cpufreq: Fix DRI computation
In-Reply-To: <87bpbmocjy.fsf@free.fr>
References: <1275698808-31166-1-git-send-email-marek.vasut@gmail.com>
	<87bpbmocjy.fsf@free.fr>
Message-ID: <201006072326.09722.marek.vasut@gmail.com>

Dne Po 7. ?ervna 2010 21:41:37 Robert Jarzmik napsal(a):
> Marek Vasut <marek.vasut at gmail.com> writes:
> > The DRI field was incorrectly computed, causing various hangs and weird
> > behaviour on PXA2xx machines. This patch introduces the DRI computation
> > according to the PXA255 (January 2004) and PXA270 (MV-S301039-00 Rev. A)
> > datasheets.
> 
> Hi Marek,
> 
> I'll help a bit in the review here, but I need a few days.
> 
> Meanwhile, I began the review and I have a question : did you check
> MDCNFG_DRAC0() and MDCNFG_DRAC2() definitions ? As I check my TRM, it
> should be, according to my manual :
> + #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 19) & 0x3)
> + #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 3) & 0x3)
> - #define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
> - #define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
> 
> While I was checking the calculation, that rows calculation doesn't fit.
> Hence I wonder if init_sdram_rows() will be correct.
> I'll send a full review soon, don't be too quick with V2 please.
> 

No actually, the definitions are correct. I just looked and what you are looking 
at is DCAC, not DRAC. Cheers
> Cheers.
> 
> --
> Robert


From cbouatmailru at gmail.com  Mon Jun  7 17:31:45 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 8 Jun 2010 01:31:45 +0400
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
In-Reply-To: <1275944170.11056.7.camel@toshiba-laptop>
References: <20100607173630.GA10489@oksana.dev.rtsoft.ru>
	<20100607194457.GC7220@n2100.arm.linux.org.uk>
	<1275944170.11056.7.camel@toshiba-laptop>
Message-ID: <20100607213145.GA23421@oksana.dev.rtsoft.ru>

On Mon, Jun 07, 2010 at 09:56:10PM +0100, Catalin Marinas wrote:
> On Mon, 2010-06-07 at 20:44 +0100, Russell King - ARM Linux wrote:
> > On Mon, Jun 07, 2010 at 09:36:30PM +0400, Anton Vorontsov wrote:
> > > To support PI or robust mutexes, the kernel needs to perform some
> > > operations atomically on userspace addresses, and yet ARM lacked
> > > the support for the SMP case.
> > >
> > > ARMv6 adds exclusive access variants of ldr and str instructions,
> > > which means that support for PI/robust mutexes should now be
> > > relatively straightforward.
> > 
> > It isn't this straight forward.  You're now bypassing the MMU protections
> > in that 'strex' can bypass the read-only protection of the user page.
> > This can result in the zero BSS page being corrupted, or worse corruption
> > to page cache pages.
> 
> Do you mean STREX in SVC mode targeting user pages? I keep posting a
> patch for more than a year :) which removes the domains switching and
> makes user pages read-only for both kernel and user space.

Wow. Then I should just make PI/robust mutexes depend on
!CONFIG_CPU_USE_DOMAINS (which is actually always true for SMP :-).

Thanks!

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2


From cbouatmailru at gmail.com  Mon Jun  7 17:35:17 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 8 Jun 2010 01:35:17 +0400
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
In-Reply-To: <alpine.LFD.2.00.1006071634340.30664@xanadu.home>
References: <20100607173630.GA10489@oksana.dev.rtsoft.ru>
	<20100607194457.GC7220@n2100.arm.linux.org.uk>
	<20100607202701.GA14529@oksana.dev.rtsoft.ru>
	<alpine.LFD.2.00.1006071634340.30664@xanadu.home>
Message-ID: <20100607213517.GA25479@oksana.dev.rtsoft.ru>

On Mon, Jun 07, 2010 at 04:40:01PM -0400, Nicolas Pitre wrote:
> On Tue, 8 Jun 2010, Anton Vorontsov wrote:
> 
> > So, can we solve this by
> > 
> > ldrex
> > ...
> > strt newval
> >    ^ may cause exception, but doesn't clear the tag, so we're still atomic
> > strex <- clears the tag
> 
> No, you're not atomic anymore, as some other ldrex/strex might have come 
> through by the time the strt is executed, and while this strex wouldn't 
> be executed as the tag would be cleared at that point, the strt has no 
> such concerns with atomic tags and would indeed corrupt whatever new 
> value has been stored in the mean time.

Ugh, surely right you are, thanks!

It seems Catalin's "Remove the domain switching" patch comes handy
here.

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2


From nico at fluxnic.net  Mon Jun  7 16:40:01 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 07 Jun 2010 16:40:01 -0400 (EDT)
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
In-Reply-To: <20100607202701.GA14529@oksana.dev.rtsoft.ru>
References: <20100607173630.GA10489@oksana.dev.rtsoft.ru>
	<20100607194457.GC7220@n2100.arm.linux.org.uk>
	<20100607202701.GA14529@oksana.dev.rtsoft.ru>
Message-ID: <alpine.LFD.2.00.1006071634340.30664@xanadu.home>

On Tue, 8 Jun 2010, Anton Vorontsov wrote:

> So, can we solve this by
> 
> ldrex
> ...
> strt newval
>    ^ may cause exception, but doesn't clear the tag, so we're still atomic
> strex <- clears the tag

No, you're not atomic anymore, as some other ldrex/strex might have come 
through by the time the strt is executed, and while this strex wouldn't 
be executed as the tag would be cleared at that point, the strt has no 
such concerns with atomic tags and would indeed corrupt whatever new 
value has been stored in the mean time.



Nicolas


From linux at arm.linux.org.uk  Mon Jun  7 17:52:24 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 7 Jun 2010 22:52:24 +0100
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
In-Reply-To: <1275944757.11056.16.camel@toshiba-laptop>
References: <20100607173630.GA10489@oksana.dev.rtsoft.ru>
	<20100607194457.GC7220@n2100.arm.linux.org.uk>
	<20100607202701.GA14529@oksana.dev.rtsoft.ru>
	<1275944757.11056.16.camel@toshiba-laptop>
Message-ID: <20100607215224.GD7220@n2100.arm.linux.org.uk>

On Mon, Jun 07, 2010 at 10:05:57PM +0100, Catalin Marinas wrote:
> But as I said, we already have patches to change the kernel R/W
> permission for RO user pages.

... but they introduce their own problem.


From jamie at shareable.org  Mon Jun  7 18:10:47 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Mon, 7 Jun 2010 23:10:47 +0100
Subject: your mail
In-Reply-To: <AANLkTikxfktI7Heocg8kaBFziT3CXMzRzr-RJcXSQhbG@mail.gmail.com>
References: <AANLkTikxfktI7Heocg8kaBFziT3CXMzRzr-RJcXSQhbG@mail.gmail.com>
Message-ID: <20100607221047.GA27304@shareable.org>

Dave Hylands wrote:
> I'm trying to understand what I need to be concerned about with SMP
> processors and sharing global data (in particular a dual Cortex-A9)
> 
> I'm familiar with spinlocks, but in this case I'm trying to work with
> some lockless data structures.
> 
> What I'm not sure is whether the following would work. Suppose I have
> a couple of 8-bit get/put indicies which are in adjacent memory
> locations (within the same 32-bit word).
> 
> If I have an ISR and a thread running on an SMP core, and the ISR is
> running on one core and the thread is running on a second core, if the
> ISR were to only write to the put pointer and the thread were only to
> write to the get pointer, does the cache maintain consistency? Or do
> the get and put pointers need to be in separate cache lines?
> 
> Another way of asking this: If both cores are writing to the same
> 32-bit word (but different bytes) do the writes collide?

I'm pretty sure any system compatible with pthreads has to be fine
with the variables being independent, because the bytes could be
variables protected by separate mutexes.

However, other questions for your lockless structures are whether
writes by one processor are seen in a reasonable or even bounded time
by reads on another processor (write buffering), and which barrier
instructions to use between the index accesses and accessing some
array they might indexing (only a problem for userspace, because the
kernel already provides barriers).

-- Jamie


From ryan at bluewatersys.com  Mon Jun  7 18:21:53 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Tue, 08 Jun 2010 10:21:53 +1200
Subject: [RFC PATCH v3 1/3] ep93xx i2s core support
In-Reply-To: <0D753D10438DA54287A00B0270842697636F83B425@AUSP01VMBX24.collaborationhost.net>
References: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
	<1275628285-12642-2-git-send-email-ryan@bluewatersys.com>
	<0D753D10438DA54287A00B0270842697636F83B425@AUSP01VMBX24.collaborationhost.net>
Message-ID: <4C0D7101.6030506@bluewatersys.com>

H Hartley Sweeten wrote:
> On Thursday, June 03, 2010 10:11 PM, Ryan Mallon wrote:
>> Add ep93xx core support for i2s audio
>>
>> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
>> ---
>>  arch/arm/mach-ep93xx/clock.c                    |   69 ++++++++++++++++++++++-
>>  arch/arm/mach-ep93xx/core.c                     |   31 ++++++++++
>>  arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |   10 +++
>>  arch/arm/mach-ep93xx/include/mach/platform.h    |    1 +
>>  4 files changed, 110 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
>> index 5f80092..503d430 100644
>> --- a/arch/arm/mach-ep93xx/clock.c
>> +++ b/arch/arm/mach-ep93xx/clock.c
>> @@ -43,7 +43,8 @@ static unsigned long get_uart_rate(struct clk *clk);
>>  
>>  static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
>>  static int set_div_rate(struct clk *clk, unsigned long rate);
>> -
>> +static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
>> +static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
>>  
>>  static struct clk clk_xtali = {
>>  	.rate		= EP93XX_EXT_CLK_RATE,
>> @@ -108,6 +109,31 @@ static struct clk clk_video = {
>>  	.set_rate	= set_div_rate,
>>  };
>>  
>> +static struct clk clk_i2s_mclk = {
>> +	.sw_locked	= 1,
>> +	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
>> +	.enable_mask	= (EP93XX_SYSCON_CLKDIV_ENABLE  |
>> +			   EP93XX_SYSCON_I2SCLKDIV_SPOL |
>> +			   EP93XX_SYSCON_I2SCLKDIV_ORIDE),
> 
> Setting the SPOL and ORIDE bits here might cause problems in the future.
> Granted, your i2s driver is currently the only user so its probably ok
> for now.
> 
> But, you might want to move the setting of those two bits along with the
> SLAVE and DROP bits to the core registration function.  The clock support
> should only be enabling/disabling and setting the rates for the clocks.

Okay, sounds sensible. Possibly I should add acquire/release functions
in addition to the register, something like:

void __init ep93xx_register_i2s(void)
{
	platform_device_register(&ep93xx_i2s_device);
}

int ep93xx_i2s_acquire(unsigned pins, int override, int sclk_falling)
{
	unsigned set_bits = pins,
		 clear_bits = EP93XX_SYSCON_DEVCFG_I2SONSSP |
			      EP93XX_SYSCON_DEVCFG_I2SONAC97;

	if (pins != EP93XX_SYSCON_DEVCFG_I2SONSSP &&
	    pins != EP93XX_SYSCON_DEVCFG_I2SONAC97)
		return -EINVAL;

	if (override)
		set_bits |= EP93XX_SYSCON_I2SCLKDIV_ORIDE;
	else
		clear_bits |= EP93XX_SYSCON_I2SCLKDIV_ORIDE;

	if (sclk_falling)
		set_bits |= EP93XX_SYSCON_I2SCLKDIV_SPOL;
	else
		clear_bits |= EP93XX_SYSCON_I2SCLKDIV_SPOL;

	ep93xx_devcfg_clear_bits(clear_bits);
	ep93xx_devcfg_set_bits(set_bits);
	return 0;
}

>> +	.set_rate	= set_div_rate,
> 
> By calling the set_div_rate routine your only updating the master clock
> rate.  Should the new rate be pushed down to the children?  Actually the
> new rates for the children will be established automatically when the
> master clock rate is changed.  But a clk_get_rate for the children will
> return an incorrect value.  Maybe just add a get_rate method for the
> children?

The code basically assumes that the clocks will always be set in the
order: mclk, sclk, lrclk. Since the i2s driver is the only user, this
should be a valid assumption. Possibly a comment should be put in to
state that this assumption is made.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From mbohan at codeaurora.org  Mon Jun  7 18:40:05 2010
From: mbohan at codeaurora.org (Michael Bohan)
Date: Mon,  7 Jun 2010 15:40:05 -0700
Subject: [PATCH][RESEND] arm: mm: Don't free prohibited memmap entries
Message-ID: <1275950405-1437-1-git-send-email-mbohan@codeaurora.org>

The VM subsystem assumes that there are valid memmap entries to
the bank end aligned to MAX_ORDER_NR_PAGES. It will try and read
these page structs, and so we cannot free any memmap entries that
it may inspect.

Signed-off-by: Michael Bohan <mbohan at codeaurora.org>
---
 arch/arm/mm/init.c |   19 +++++++++----------
 1 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 1ba6cf5..233bcfd 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -495,28 +495,27 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi)
 	unsigned int i;
 
 	/*
-	 * [FIXME] This relies on each bank being in address order.  This
-	 * may not be the case, especially if the user has provided the
-	 * information on the command line.
+	 * This relies on each bank being in address order.
+	 * The banks are sorted previously in bootmem_init().
 	 */
 	for_each_nodebank(i, mi, node) {
 		struct membank *bank = &mi->bank[i];
 
 		bank_start = bank_pfn_start(bank);
-		if (bank_start < prev_bank_end) {
-			printk(KERN_ERR "MEM: unordered memory banks.  "
-				"Not freeing memmap.\n");
-			break;
-		}
 
 		/*
 		 * If we had a previous bank, and there is a space
 		 * between the current bank and the previous, free it.
 		 */
-		if (prev_bank_end && prev_bank_end != bank_start)
+		if (prev_bank_end && prev_bank_end < bank_start)
 			free_memmap(node, prev_bank_end, bank_start);
 
-		prev_bank_end = bank_pfn_end(bank);
+		/*
+		 * Align up here since the VM subsystem insists that the
+		 * memmap entries are valid from the bank end aligned to
+		 * MAX_ORDER_NR_PAGES.
+		 */
+		prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES);
 	}
 }
 
-- 
1.7.1



From dhylands at gmail.com  Mon Jun  7 18:44:16 2010
From: dhylands at gmail.com (Dave Hylands)
Date: Mon, 7 Jun 2010 15:44:16 -0700
Subject: your mail
In-Reply-To: <20100607221047.GA27304@shareable.org>
References: <AANLkTikxfktI7Heocg8kaBFziT3CXMzRzr-RJcXSQhbG@mail.gmail.com>
	<20100607221047.GA27304@shareable.org>
Message-ID: <AANLkTikA_eXw1fMwOtuPxLqlDdzz4IYJfsXkpuCSkOUw@mail.gmail.com>

HI Jamie,

On Mon, Jun 7, 2010 at 3:10 PM, Jamie Lokier wrote:
> Dave Hylands wrote:
[...]
>> Another way of asking this: If both cores are writing to the same
>> 32-bit word (but different bytes) do the writes collide?
>
> I'm pretty sure any system compatible with pthreads has to be fine
> with the variables being independent, because the bytes could be
> variables protected by separate mutexes.
>
> However, other questions for your lockless structures are whether
> writes by one processor are seen in a reasonable or even bounded time
> by reads on another processor (write buffering), and which barrier
> instructions to use between the index accesses and accessing some
> array they might indexing (only a problem for userspace, because the
> kernel already provides barriers).

After lots of reading - I think that the Snoop Control Unit takes care
of moving the cache lines from one core to the other when both cores
are trying to access data from the same cache line.

So it's not very efficient to have both cores accessing data from the
same cache line - but it seems that the integrity of the data should
be maintained (or at least this is my current understanding).

-- 
Dave Hylands
Shuswap, BC, Canada
http://www.DaveHylands.com/


From ben-linux at fluff.org  Mon Jun  7 18:54:10 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Mon, 7 Jun 2010 23:54:10 +0100
Subject: mini2440 (likely more boards) boot failure because of recent
	changes in s3c gpio
In-Reply-To: <4C0BF34A.1060805@walsimou.com>
References: <4C0BF34A.1060805@walsimou.com>
Message-ID: <20100607225410.GT7248@trinity.fluff.org>

On Sun, Jun 06, 2010 at 09:13:14PM +0200, Abdoulaye Walsimou Gaye wrote:
> Hello list,
> Recent changes in s3c gpio break mini2440 board.
> The problem is that mach-mini2440.c: mini2440_init() (where we call  
> s3c_gpio_setpull())
> is called before s3c2440.c: s3c2440_init() (where we initialize  
> s3c24xx_gpiocfg_default.set_pull function pointer).
> This causes dereferencing of NULL pointer at boot time and a kernel panic.
> The following change (probably not what needs to be done) lets the board  
> boot again:

ok, thankyou for reporting this. will look into it as soon as possible.

> diff --git a/arch/arm/plat-s3c24xx/gpiolib.c  
> b/arch/arm/plat-s3c24xx/gpiolib.c
> index 4c0896f..ae9d3c2 100644
> --- a/arch/arm/plat-s3c24xx/gpiolib.c
> +++ b/arch/arm/plat-s3c24xx/gpiolib.c
> @@ -87,6 +87,8 @@ static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = {
>  struct s3c_gpio_cfg s3c24xx_gpiocfg_default = {
>         .set_config     = s3c_gpio_setcfg_s3c24xx,
>         .get_config     = s3c_gpio_getcfg_s3c24xx,
> +       .set_pull       = s3c_gpio_setpull_1up,
> +       .get_pull       = s3c_gpio_getpull_1up,
>  };
>
> Best regards,
> AWG
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From mans at mansr.com  Mon Jun  7 19:09:43 2010
From: mans at mansr.com (=?iso-8859-1?Q?M=E5ns_Rullg=E5rd?=)
Date: Tue, 08 Jun 2010 00:09:43 +0100
Subject: Preload engine in ARMv7 (cortex A8)
References: <AANLkTilGu3OC_tth-Wurgu1jcm5zKKntINGc-A8CwkxI@mail.gmail.com>
	<1275901492.7258.6.camel@toshiba-laptop>
Message-ID: <yw1xk4qaxww8.fsf@unicorn.mansr.com>

Catalin Marinas <catalin.marinas at arm.com> writes:

> On Tue, 2010-06-01 at 18:27 +0100, Vinayak Pane wrote:
>> I am planning to utilize the PreLoad Engine for L2 cache. In past, I
>> have played with cache locking with line by line in ARM9. There I
>> could recall that tags and indexes are generated on basis of physical
>> address of the data. Now in case of PLE we have the start address and
>> number of lines to fill with. Does the PLE operation will leave some
>> indexes empty ? Or does the PLE populate all the lines in that way
>> with the source data address ? Do I need to start PLE for the block of
>> size equal to that of way-size ? To ensure no lines remain empty  and
>> to ensure no line gets overwriten by other line.
>
> I couldn't fully understand your question. It looks more like
> hardware-related (you could try support at arm.com).
>
> Anyway, in general you should not make any assumptions about which lines
> are present or not in the cache. With speculative loads on newer cores,
> you can get other lines in the cache than what you were expecting and
> they may evict some the you explicitly tried to preload.

Locking a cache way before loading it with the PLE would avoid
unrelated loads, speculative or otherwise, evicting the preloaded data
early.  This of course gets complicated quickly, so it's generally
better to not assume anything.  Cache is not TCM and should not be
treated as such.

-- 
M?ns Rullg?rd
mans at mansr.com



From jason77.wang at gmail.com  Mon Jun  7 19:22:18 2010
From: jason77.wang at gmail.com (jason)
Date: Tue, 08 Jun 2010 07:22:18 +0800
Subject: [V2 3/3] mx51/keypad: add keypad support for i.MX51 platforms
In-Reply-To: <1275847887.11528.13.camel@realization>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>	
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>	
	<1275566746-6510-3-git-send-email-jason77.wang@gmail.com>	
	<1275566746-6510-4-git-send-email-jason77.wang@gmail.com>	
	<1275730558.3446.23.camel@realization> <4C0A5B8E.4020906@gmail.com>
	<1275847887.11528.13.camel@realization>
Message-ID: <4C0D7F2A.5050706@gmail.com>

Alberto Panizzo wrote:
> Hi Jason,
>
> On sab, 2010-06-05 at 22:13 +0800, jason wrote:
>   
>> Alberto Panizzo wrote:
>>     
>>> On gio, 2010-06-03 at 20:05 +0800, Jason Wang wrote:
>>>   
>>>       
>>>> Add keypad controller device definition for all i.MX51 platforms,
>>>> add a dummy kpp clock for imx keypad driver and add keypad device
>>>> registration on i.MX51 3-stack board.
>>>>
>>>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>>>> ---
>>>>  arch/arm/mach-mx5/board-mx51_3ds.c |   59 ++++++++++++++++++++++++++++++++++++
>>>>  arch/arm/mach-mx5/clock-mx51.c     |    5 +++
>>>>  arch/arm/mach-mx5/devices.c        |   19 +++++++++++
>>>>  arch/arm/mach-mx5/devices.h        |    1 +
>>>>  4 files changed, 84 insertions(+), 0 deletions(-)
>>>>     
>>>>         
>>> May you wont divide platform vs machine code in two different patches.
>>>   
>>>       
>> Thanks for your comments, but here i don't really know what you mean,
>> should i divide this patch to 2 patches or ?
>>     
>
> Code that stays into devices.[c|h] is general code that shall not be 
> modified together with machine code (board-mx51_3ds.c).
>
>   
OK, accept.

Thanks,
Jason.
>>> and, Eric B?nard is working on imx_keypad suspend/resume features[1] and
>>> about it, he is going to modify the platform interface that make us able
>>> to register the device.. this patch could look old in a few.
>>>
>>> [1]http://thread.gmane.org/gmane.linux.ports.arm.kernel/80968/focus=13131
>>>
>>> Best regards,
>>> Alberto!
>>>
>>>   
>>>       
>> Yes, reading this thread, my platform interface is old.
>> I just git pull the upstream, it seems that new interface change hasn't 
>> been merged,
>> i will modify this interface if it is merged into the upstream.
>>     
>
> Well Dmitry (linux input maintainer) asked Eric some clarifications 
> before merging his work.
> In all case, Eric work is going to be part of the next merge window
> through the linux input tree if all goes in the right way.
> So in the imx tree you would see it at least since .35
>
> Sascha, what is your policy about this? Shall Jason support the keypad
> with the current interface and update it's support in the next merge
> window? or it is better to wait?
>
> Alberto!
>
>
>
>   



From linus.ml.walleij at gmail.com  Mon Jun  7 19:34:25 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Tue, 8 Jun 2010 01:34:25 +0200
Subject: [PATCH 01/10] [ARM] tegra: initial tegra support
In-Reply-To: <1275635441-17378-2-git-send-email-olof@lixom.net>
References: <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
Message-ID: <AANLkTinPJuvApEVRdx5M6Oi88_-avWr_Q63atSOfTruK@mail.gmail.com>

2010/6/4 Olof Johansson <olof at lixom.net>:

> (...)
> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> index 5bd7c89..b4f6c5e 100644
> --- a/arch/arm/mm/Kconfig
> +++ b/arch/arm/mm/Kconfig
> @@ -760,7 +760,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
> ?config CACHE_L2X0
> ? ? ? ?bool "Enable the L2x0 outer cache controller"
> ? ? ? ?depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
> - ? ? ? ? ? ? ? ? ?REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
> + ? ? ? ? ? ? ? ? ?REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4 || ARCH_TEGRA

What are you actually basing your patches on? You will
need to bring your patches to the head, there are already
two more machines using the L2x0 for example, so this
won't apply.

Yours,
Linus Walleij


From linus.ml.walleij at gmail.com  Mon Jun  7 19:43:00 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Tue, 8 Jun 2010 01:43:00 +0200
Subject: [PATCH 05/10] [ARM] tegra: Add timer support
In-Reply-To: <1275635441-17378-6-git-send-email-olof@lixom.net>
References: <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
	<1275635441-17378-3-git-send-email-olof@lixom.net>
	<1275635441-17378-4-git-send-email-olof@lixom.net>
	<1275635441-17378-5-git-send-email-olof@lixom.net>
	<1275635441-17378-6-git-send-email-olof@lixom.net>
Message-ID: <AANLkTilitoPKhSCk1gxwyzOdu8LZD-9xA3EesFKkDsLy@mail.gmail.com>

2010/6/4 Olof Johansson <olof at lixom.net>:

> (....)
> +static struct clock_event_device tegra_clockevent = {
> + ? ? ? .name ? ? ? ? ? = "timer0",
> + ? ? ? .rating ? ? ? ? = 300,
> + ? ? ? .features ? ? ? = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
> + ? ? ? .mult ? ? ? ? ? = 16777,
> + ? ? ? .shift ? ? ? ? ?= 24,
> + ? ? ? .set_next_event = tegra_timer_set_next_event,
> + ? ? ? .set_mode ? ? ? = tegra_timer_set_mode,
> +};
> +
> +static struct clocksource tegra_clocksource = {
> + ? ? ? .name ? = "timer_us",
> + ? ? ? .rating = 300,
> + ? ? ? .read ? = tegra_clocksource_read,
> + ? ? ? .mask ? = 0xFFFFFFFFUL,
> + ? ? ? .mult ? = 1000,
> + ? ? ? .shift ?= 0,
> + ? ? ? .flags ?= CLOCK_SOURCE_IS_CONTINUOUS,
> +};

How did you calculate the magic mult/shift numbers 16777/24 and
1000/0 above? Especially the latter intuitively seem very inappropriate,
and I guess there will be revisions of this platform with new frequencies
for the timer as well, making these hard-coded values a bug source.

I would consider using the
clocksource_calc_mult_shift() and
clockevents_calc_mult_shift()
functions based on the frequency of the timer counter and a minimum wakeup
range if you don't know exactly why you want these mult+shifts.

I posted some patches to encourage the use of these recently.

Yours,
Linus Walleij


From linus.ml.walleij at gmail.com  Mon Jun  7 19:47:16 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Tue, 8 Jun 2010 01:47:16 +0200
Subject: [PATCH 08/10] [ARM] tegra: harmony: Add harmony board file
In-Reply-To: <1275635441-17378-9-git-send-email-olof@lixom.net>
References: <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
	<1275635441-17378-3-git-send-email-olof@lixom.net>
	<1275635441-17378-4-git-send-email-olof@lixom.net>
	<1275635441-17378-5-git-send-email-olof@lixom.net>
	<1275635441-17378-6-git-send-email-olof@lixom.net>
	<1275635441-17378-7-git-send-email-olof@lixom.net>
	<1275635441-17378-8-git-send-email-olof@lixom.net>
	<1275635441-17378-9-git-send-email-olof@lixom.net>
Message-ID: <AANLkTim-vAk1f0gLzvk1o0iPhfiRSClRcjZsandp269v@mail.gmail.com>

2010/6/4 Olof Johansson <olof at lixom.net>:

> (...)
> +static struct plat_serial8250_port debug_uart_platform_data[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .membase ? ? ? ?= IO_ADDRESS(TEGRA_UARTD_BASE),
> + ? ? ? ? ? ? ? .mapbase ? ? ? ?= TEGRA_UARTD_BASE,
> + ? ? ? ? ? ? ? .irq ? ? ? ? ? ?= INT_UARTD,
> + ? ? ? ? ? ? ? .flags ? ? ? ? ?= UPF_BOOT_AUTOCONF,
> + ? ? ? ? ? ? ? .iotype ? ? ? ? = UPIO_MEM,
> + ? ? ? ? ? ? ? .regshift ? ? ? = 2,
> + ? ? ? ? ? ? ? .uartclk ? ? ? ?= 216000000/16 * 16,
> + ? ? ? }, {
> + ? ? ? ? ? ? ? .flags ? ? ? ? ?= 0
> + ? ? ? }
> +};

Ummmm what is this = 216000000/16 * 16?

I think the compiler will optimize that to 216000000 so why not set
it to that.

Yours,
Linus Walleij


From broonie at opensource.wolfsonmicro.com  Mon Jun  7 19:52:16 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 8 Jun 2010 00:52:16 +0100
Subject: [alsa-devel] [RFC PATCH v3 0/3] ep93xx i2s audio
In-Reply-To: <4C0D58BB.5030505@bluewatersys.com>
	(sfid-20100607_213827_729716_0AEBDFD1)
References: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
	<1275914732.3045.105.camel@odin>
	<4C0D58BB.5030505@bluewatersys.com>
	(sfid-20100607_213827_729716_0AEBDFD1)
Message-ID: <F302D76F-8D7D-4F4B-ACC5-D7F76998AA4A@opensource.wolfsonmicro.com>

On 7 Jun 2010, at 21:38, Ryan Mallon wrote:

> Russell, Mark has picked up patch 2/3 via the alsa tree. Should I submit
> 1/3 and 3/3 via the arm patch system with Liam's ack?

At least 3/3 needs to go via the ASoC tree since it depends on 2/3. It may make sense for all of them to go that way, or perhaps 1/3 could go separately via the ARM tree (in which case I'd ack it too).

From hartleys at visionengravers.com  Mon Jun  7 17:55:30 2010
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Mon, 7 Jun 2010 16:55:30 -0500
Subject: [RFC PATCH v3 1/3] ep93xx i2s core support
In-Reply-To: <1275628285-12642-2-git-send-email-ryan@bluewatersys.com>
References: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
	<1275628285-12642-2-git-send-email-ryan@bluewatersys.com>
Message-ID: <0D753D10438DA54287A00B0270842697636F83B425@AUSP01VMBX24.collaborationhost.net>

On Thursday, June 03, 2010 10:11 PM, Ryan Mallon wrote:
> Add ep93xx core support for i2s audio
> 
> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
> ---
>  arch/arm/mach-ep93xx/clock.c                    |   69 ++++++++++++++++++++++-
>  arch/arm/mach-ep93xx/core.c                     |   31 ++++++++++
>  arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |   10 +++
>  arch/arm/mach-ep93xx/include/mach/platform.h    |    1 +
>  4 files changed, 110 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
> index 5f80092..503d430 100644
> --- a/arch/arm/mach-ep93xx/clock.c
> +++ b/arch/arm/mach-ep93xx/clock.c
> @@ -43,7 +43,8 @@ static unsigned long get_uart_rate(struct clk *clk);
>  
>  static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
>  static int set_div_rate(struct clk *clk, unsigned long rate);
> -
> +static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
> +static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
>  
>  static struct clk clk_xtali = {
>  	.rate		= EP93XX_EXT_CLK_RATE,
> @@ -108,6 +109,31 @@ static struct clk clk_video = {
>  	.set_rate	= set_div_rate,
>  };
>  
> +static struct clk clk_i2s_mclk = {
> +	.sw_locked	= 1,
> +	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
> +	.enable_mask	= (EP93XX_SYSCON_CLKDIV_ENABLE  |
> +			   EP93XX_SYSCON_I2SCLKDIV_SPOL |
> +			   EP93XX_SYSCON_I2SCLKDIV_ORIDE),

Setting the SPOL and ORIDE bits here might cause problems in the future.
Granted, your i2s driver is currently the only user so its probably ok
for now.

But, you might want to move the setting of those two bits along with the
SLAVE and DROP bits to the core registration function.  The clock support
should only be enabling/disabling and setting the rates for the clocks.

> +	.set_rate	= set_div_rate,

By calling the set_div_rate routine your only updating the master clock
rate.  Should the new rate be pushed down to the children?  Actually the
new rates for the children will be established automatically when the
master clock rate is changed.  But a clk_get_rate for the children will
return an incorrect value.  Maybe just add a get_rate method for the
children?

> +};
> +
> +static struct clk clk_i2s_sclk = {
> +	.sw_locked	= 1,
> +	.parent		= &clk_i2s_mclk,
> +	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
> +	.enable_mask	= EP93XX_SYSCON_I2SCLKDIV_SENA,
> +	.set_rate	= set_i2s_sclk_rate,
> +};
> +
> +static struct clk clk_i2s_lrclk = {
> +	.sw_locked	= 1,
> +	.parent		= &clk_i2s_sclk,
> +	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
> +	.enable_mask	= EP93XX_SYSCON_I2SCLKDIV_SENA,
> +	.set_rate	= set_i2s_lrclk_rate,
> +};
> +
>  /* DMA Clocks */
>  static struct clk clk_m2p0 = {
>  	.parent		= &clk_h,
> @@ -186,6 +212,9 @@ static struct clk_lookup clocks[] = {
>  	INIT_CK("ep93xx-ohci",		NULL,		&clk_usb_host),
>  	INIT_CK("ep93xx-keypad",	NULL,		&clk_keypad),
>  	INIT_CK("ep93xx-fb",		NULL,		&clk_video),
> +	INIT_CK("ep93xx-i2s",		"mclk",		&clk_i2s_mclk),
> +	INIT_CK("ep93xx-i2s",		"sclk",		&clk_i2s_sclk),
> +	INIT_CK("ep93xx-i2s",		"lrclk",	&clk_i2s_lrclk),
>  	INIT_CK(NULL,			"pwm_clk",	&clk_pwm),
>  	INIT_CK(NULL,			"m2p0",		&clk_m2p0),
>  	INIT_CK(NULL,			"m2p1",		&clk_m2p1),
> @@ -396,6 +425,44 @@ static int set_div_rate(struct clk *clk, unsigned long rate)
>  	return 0;
>  }
>  
> +static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate)
> +{
> +	unsigned val = __raw_readl(clk->enable_reg);
> +
> +	if (rate == clk_i2s_mclk.rate / 2)
> +		ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV, 
> +					     clk->enable_reg);
> +	else if (rate == clk_i2s_mclk.rate / 4)
> +		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV, 
> +					     clk->enable_reg);
> +	else
> +		return -EINVAL;
> +
> +	clk_i2s_sclk.rate = rate;
> +	return 0;
> +}
> +
> +static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate)
> +{
> +	unsigned val = __raw_readl(clk->enable_reg) & 
> +		~EP93XX_I2SCLKDIV_LRDIV_MASK;
> +	
> +	if (rate == clk_i2s_sclk.rate / 32)
> +		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32,
> +					     clk->enable_reg);
> +	else if (rate == clk_i2s_sclk.rate / 64)
> +		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64,
> +					     clk->enable_reg);
> +	else if (rate == clk_i2s_sclk.rate / 128)
> +		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128,
> +					     clk->enable_reg);
> +	else
> +		return -EINVAL;
> +
> +	clk_i2s_lrclk.rate = rate;
> +	return 0;
> +}
> +
>  int clk_set_rate(struct clk *clk, unsigned long rate)
>  {
>  	if (clk->set_rate)
> diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
> index 90fb591..c04fd6f 100644
> --- a/arch/arm/mach-ep93xx/core.c
> +++ b/arch/arm/mach-ep93xx/core.c
> @@ -617,6 +617,37 @@ void ep93xx_keypad_release_gpio(struct platform_device *pdev)
>  }
>  EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
>  
> +/*************************************************************************
> + * EP93xx I2S audio peripheral handling
> + *************************************************************************/
> +static struct resource ep93xx_i2s_resource[] = {
> +	{
> +		.start	= EP93XX_I2S_PHYS_BASE,
> +		.end	= EP93XX_I2S_PHYS_BASE + 0x100 - 1,
> +		.flags	= IORESOURCE_MEM,
> +	},
> +};
> +
> +static struct platform_device ep93xx_i2s_device = {
> +	.name		= "ep93xx-i2s",
> +	.id		= -1,
> +	.num_resources	= ARRAY_SIZE(ep93xx_i2s_resource),
> +	.resource	= ep93xx_i2s_resource,
> +};
> +
> +void __init ep93xx_register_i2s(unsigned pins)
> +{
> +	if (pins != EP93XX_SYSCON_DEVCFG_I2SONSSP &&
> +	    pins != EP93XX_SYSCON_DEVCFG_I2SONAC97) {
> +		pr_err("Invalid I2S pin configuration - not registering\n");
> +		return;
> +	}
> +
> +	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2SONSSP |
> +				 EP93XX_SYSCON_DEVCFG_I2SONAC97);
> +	ep93xx_devcfg_set_bits(pins);
> +	platform_device_register(&ep93xx_i2s_device);
> +}
>  
>  extern void ep93xx_gpio_init(void);
>  
> diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
> index 93e2ecc..3fbb095 100644
> --- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
> +++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
> @@ -93,6 +93,7 @@
>  /* APB peripherals */
>  #define EP93XX_TIMER_BASE		EP93XX_APB_IOMEM(0x00010000)
>  
> +#define EP93XX_I2S_PHYS_BASE		EP93XX_APB_PHYS(0x00020000)
>  #define EP93XX_I2S_BASE			EP93XX_APB_IOMEM(0x00020000)
>  
>  #define EP93XX_SECURITY_BASE		EP93XX_APB_IOMEM(0x00030000)
> @@ -193,6 +194,15 @@
>  #define EP93XX_SYSCON_CLKDIV_ESEL	(1<<14)
>  #define EP93XX_SYSCON_CLKDIV_PSEL	(1<<13)
>  #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT	8
> +#define EP93XX_SYSCON_I2SCLKDIV		EP93XX_SYSCON_REG(0x8c)
> +#define EP93XX_SYSCON_I2SCLKDIV_SENA	(1<<31)
> +#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
> +#define EP93XX_SYSCON_I2SCLKDIV_SPOL	(1<<19)
> +#define EP93XX_I2SCLKDIV_SDIV		(1 << 16)
> +#define EP93XX_I2SCLKDIV_LRDIV32	(0 << 17)
> +#define EP93XX_I2SCLKDIV_LRDIV64	(1 << 17)
> +#define EP93XX_I2SCLKDIV_LRDIV128 	(2 << 17)
> +#define EP93XX_I2SCLKDIV_LRDIV_MASK 	(3 << 17)
>  #define EP93XX_SYSCON_KEYTCHCLKDIV	EP93XX_SYSCON_REG(0x90)
>  #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	(1<<31)
>  #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	(1<<16)
> diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
> index c6dc14d..9252adf 100644
> --- a/arch/arm/mach-ep93xx/include/mach/platform.h
> +++ b/arch/arm/mach-ep93xx/include/mach/platform.h
> @@ -43,6 +43,7 @@ void ep93xx_pwm_release_gpio(struct platform_device *pdev);
>  void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data);
>  int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
>  void ep93xx_keypad_release_gpio(struct platform_device *pdev);
> +void ep93xx_register_i2s(unsigned pins);
>  
>  void ep93xx_init_devices(void);
>  extern struct sys_timer ep93xx_timer;

Other than the comments above I'm ok with this.

Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>


From ryan at bluewatersys.com  Mon Jun  7 20:38:18 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Tue, 08 Jun 2010 12:38:18 +1200
Subject: [alsa-devel] [RFC PATCH v3 0/3] ep93xx i2s audio
In-Reply-To: <F302D76F-8D7D-4F4B-ACC5-D7F76998AA4A@opensource.wolfsonmicro.com>
References: <1275628285-12642-1-git-send-email-ryan@bluewatersys.com>
	<1275914732.3045.105.camel@odin>
	<4C0D58BB.5030505@bluewatersys.com>
	(sfid-20100607_213827_729716_0AEBDFD1)
	<F302D76F-8D7D-4F4B-ACC5-D7F76998AA4A@opensource.wolfsonmicro.com>
Message-ID: <4C0D90FA.5020400@bluewatersys.com>

Mark Brown wrote:
> On 7 Jun 2010, at 21:38, Ryan Mallon wrote:
> 
>> Russell, Mark has picked up patch 2/3 via the alsa tree. Should I submit
>> 1/3 and 3/3 via the arm patch system with Liam's ack?
> 
> At least 3/3 needs to go via the ASoC tree since it depends on 2/3. It may make sense for all of them to go that way, or perhaps 1/3 could go separately via the ARM tree (in which case I'd ack it too).

I really don't mind either way, unless Russell has objections to the
core patches going via the alsa tree.

I want to make a couple of changes suggested by Hartley to patches 1/3
and 3/3 which will cleanup the registration interface a little. I will
repost the patches hopefully later today.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From kuninori.morimoto.gx at renesas.com  Mon Jun  7 22:16:37 2010
From: kuninori.morimoto.gx at renesas.com (Kuninori Morimoto)
Date: Tue, 08 Jun 2010 11:16:37 +0900 (JST)
Subject: Current menuconfig (ARM system type) is broken
Message-ID: <w3pfx0yuv3x.wl%kuninori.morimoto.gx@renesas.com>


Dear all

Is current menuconfig broken ?
It mean

[Sytem Type] - [ARM system type]

In my environment, string output is broken.

I think 
${LINUX}/arch/arm/Kconfig

config ARCH_S3C2410
	bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"

this line is very long.
If I modify it to more short, it works correct.

Best regards
--
Kuninori Morimoto
 


From marek.vasut at gmail.com  Mon Jun  7 22:35:17 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Tue, 8 Jun 2010 04:35:17 +0200
Subject: Current menuconfig (ARM system type) is broken
In-Reply-To: <w3pfx0yuv3x.wl%kuninori.morimoto.gx@renesas.com>
References: <w3pfx0yuv3x.wl%kuninori.morimoto.gx@renesas.com>
Message-ID: <201006080435.17113.marek.vasut@gmail.com>

Dne ?t 8. ?ervna 2010 04:16:37 Kuninori Morimoto napsal(a):
> Dear all
> 
> Is current menuconfig broken ?
> It mean
> 
> [Sytem Type] - [ARM system type]
> 
> In my environment, string output is broken.
> 
> I think
> ${LINUX}/arch/arm/Kconfig
> 
> config ARCH_S3C2410
> 	bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442,
> S3C2443, S3C2450"
> 
> this line is very long.
> If I modify it to more short, it works correct.

hey, this was discussed here not long ago, look for:

[PATCH 2/2] menuconfig: truncate list items
> 
> Best regards
> --
> Kuninori Morimoto
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From kuninori.morimoto.gx at renesas.com  Tue Jun  8 00:33:59 2010
From: kuninori.morimoto.gx at renesas.com (Kuninori Morimoto)
Date: Tue, 08 Jun 2010 13:33:59 +0900 (JST)
Subject: Current menuconfig (ARM system type) is broken
In-Reply-To: <201006080435.17113.marek.vasut@gmail.com>
References: <w3pfx0yuv3x.wl%kuninori.morimoto.gx@renesas.com>
	<201006080435.17113.marek.vasut@gmail.com>
Message-ID: <w3pbpbmuoqx.wl%kuninori.morimoto.gx@renesas.com>


Dear Marek

> > If I modify it to more short, it works correct.
> 
> hey, this was discussed here not long ago, look for:
> 
> [PATCH 2/2] menuconfig: truncate list items

Ohh Thanks.
Sorry, I didn't know that.

Best regards
--
Kuninori Morimoto
 


From eric.y.miao at gmail.com  Tue Jun  8 02:12:47 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 8 Jun 2010 14:12:47 +0800
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option for 
	exceptions
In-Reply-To: <201006071712.20888.marek.vasut@gmail.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com> 
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com> 
	<201006071712.20888.marek.vasut@gmail.com>
Message-ID: <AANLkTilJoleT450L4-H8ZEeuXKzSmYBVDI9h81KCXZZk@mail.gmail.com>

> Hi,
> what about the PXA based devices, where RAM begins at 0x80000000 ?
>

I hope at this stage, it's a 1:1 direct mapping from the original zreladdr-y
variables to CONFIG_ZRELADDR.

But yeah, we can make that change some time later based on this.


From mike at compulab.co.il  Tue Jun  8 02:21:25 2010
From: mike at compulab.co.il (Mike Rapoport)
Date: Tue, 08 Jun 2010 09:21:25 +0300
Subject: pxa300 - DDRAM base value
In-Reply-To: <201006072143.16136.marek.vasut@gmail.com>
References: <1275371058.7001.35.camel@balakrishnan-desktop>	<1275892191.3501.17.camel@balakrishnan-desktop>	<AANLkTinKc9Uc6QeKYogK3h1kHsOU1p6Qp1kWgn0J8cMA@mail.gmail.com>
	<201006072143.16136.marek.vasut@gmail.com>
Message-ID: <4C0DE165.5010206@compulab.co.il>

Marek Vasut wrote:
> Dne Po 7. ?ervna 2010 21:37:16 Mike Rapoport napsal(a):
>>> hi,
>>>       Now, I can able to boot after editing following files
>>> arch/arm/mach-pxa/Makefile.boot and
>>> arch/arm/mach/pxa/include/mach/memory.h (0x80000000 changed to
>>> 0xa0000000). My doubt is
>>> 1.why 0x80000000 (DDR phy address) is aliased to 0xa0000000 in pxa
>>> architecture?
>>> 2.In my development board two DDRAMs mapped at 0x80000000-0x88000000 and
>>> 0xc0000000-0xc8000000, how can I inform to kernel about this different
>>> bank and size?.
>> enable CONFIG_HIGHMEM
> 
> Mike, that wont help him as he has PHYS_OFFSET=0xa0000000 . Selecting 
> CONFIG_HIGHMEM will only cause the pages for RAM below 0xa0000000 to have 
> incorrectly computated descriptor addresses (or maybe will be ignored).
> 
> The page descriptors for RAM at PA 0xa0000000 are at VA 0xc0000000 + some offset 
> (there's an easy linear formula to compute their offset). Now if you feed that 
> formula with 0x80000000, the page descriptors will end below 0xc0000000, which 
> isn't a valid VA, therefore the descriptors will not be valid either (in the 
> better case, but it will hang the kernel at early stage anyway).
> 
> Therefore there are two ways -- either use what I suggested earlier or wait 
> until the PHYS_OFFSET is dynamically computated (check Eric's patchset).

Not quite. I have it working with CONFIG_HIGHMEM, I've just forgotten 
about cm_x300_fixup:

static void __init cm_x300_fixup(struct machine_desc *mdesc, struct tag 
*tags,
                                  char **cmdline, struct meminfo *mi)
{
         /* Make sure that mi->bank[0].start = PHYS_ADDR */
         for (; tags->hdr.size; tags = tag_next(tags))
                 if (tags->hdr.tag == ATAG_MEM &&
                         tags->u.mem.start == 0x80000000) {
                         tags->u.mem.start = 0xa0000000;
                         break;
                 }
}


> Cheers
>>> My Boot loader details,
>>> ------------------------------
>>> =>bdi
>>> arch_number = 0x00000B04
>>> env_t       = 0x00000000
>>> boot_params = 0x80000100
>>> DRAM bank   = 0x00000000
>>> -> start    = 0x80000000
>>> -> size     = 0x08000000
>>> DRAM bank   = 0x00000001
>>> -> start    = 0xC0000000
>>> -> size     = 0x08000000
>>> ethaddr     = 08:00:3e:26:0a:5b
>>> ip_addr     = 192.168.0.21
>>> baudrate    = 115200 bps
>>> =>ver
>>> U-Boot 2010.03 (Jun 01 2010 - 14:27:43)
>>>
>>>
>>> With Thanks
>>> J.Balakrishnan
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


-- 
Sincerely yours,
Mike.


From mcuos.com at gmail.com  Tue Jun  8 02:57:43 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Tue, 8 Jun 2010 14:57:43 +0800
Subject: [PATCH] pxa168 and pxa930 build fix - plat-pxa/pmu.c dependent on
	ARCH_PXA for IRQ_PMU
In-Reply-To: <1275932959-474-1-git-send-email-jic23@cam.ac.uk>
References: <1275932959-474-1-git-send-email-jic23@cam.ac.uk>
Message-ID: <AANLkTilXErDZHWf71e7pwUbt1i66MVrfP_lPisgoBZ0G@mail.gmail.com>

2010/6/8 Jonathan Cameron <jic23 at cam.ac.uk>:
> Signed-off-by: Jonathan Cameron <jic23 at cam.ac.uk>
> ---
> ?Found this build issue whilst browsing kautobuild logs.
> ?There may well be a better fix but until someone with
> ?a board in ARCH_MMP can test it, lets just not build
> ?pmu.c. ?Can't find equivalent fix in Eric's tree so I
> ?think this is still a live problem.
>

When building pxa168 platform, IRQ_PMU cannot be find and error occurs.
Eric, before delete it from MMP, should not we check whether the
performance counter function
is necessary for MMP or not?

If necessary , we should fix this issue by define IRQ_PMU to
IRQ_PXA168_PMU, or we can delete it.

> ?arch/arm/plat-pxa/Makefile | ? ?3 ++-
> ?1 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
> index 6187edf..a17cc0c 100644
> --- a/arch/arm/plat-pxa/Makefile
> +++ b/arch/arm/plat-pxa/Makefile
> @@ -2,8 +2,9 @@
> ?# Makefile for code common across different PXA processor families
> ?#
>
> -obj-y ?:= dma.o pmu.o
> +obj-y ?:= dma.o
>
> +obj-$(CONFIG_ARCH_PXA) ? ? ? ? += pmu.o
> ?obj-$(CONFIG_GENERIC_GPIO) ? ? += gpio.o
> ?obj-$(CONFIG_PXA3xx) ? ? ? ? ? += mfp.o
> ?obj-$(CONFIG_ARCH_MMP) ? ? ? ? += mfp.o
> --
> 1.6.4.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
*linux-arm-kernel mailing list
mail addr:linux-arm-kernel at lists.infradead.org
you can subscribe by:
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

* linux-arm-NUC900 mailing list
mail addr:NUC900 at googlegroups.com
main web: https://groups.google.com/group/NUC900
you can subscribe it by sending me mail:
mcuos.com at gmail.com


From eric.y.miao at gmail.com  Tue Jun  8 02:57:57 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 8 Jun 2010 14:57:57 +0800
Subject: [PATCH] Add battery support into Zipit Z2
In-Reply-To: <201005280500.36443.marek.vasut@gmail.com>
References: <1275015564-21803-1-git-send-email-marek.vasut@gmail.com> 
	<201005280500.36443.marek.vasut@gmail.com>
Message-ID: <AANLkTintQbzQjC_lsnvYGW0ZizJBqA1PIYe4_V5Jp8YH@mail.gmail.com>

On Fri, May 28, 2010 at 11:00 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dne P? 28. kv?tna 2010 04:59:24 Marek Vasut napsal(a):
>> This patch adds support for the AER915 battery chip into Zipit Z2
>> platform file.
>>
>> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Applied to 'devel'.


From eric.y.miao at gmail.com  Tue Jun  8 03:22:25 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 8 Jun 2010 15:22:25 +0800
Subject: [PATCH 3/3] pxa/z2: Register WM8750
In-Reply-To: <1275317512-4239-3-git-send-email-marek.vasut@gmail.com>
References: <1275317512-4239-1-git-send-email-marek.vasut@gmail.com> 
	<1275317512-4239-3-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTimZqz2YQfMZwbrt9ptUjEvsyZgW012J_vSVA2vQ@mail.gmail.com>

On Mon, May 31, 2010 at 10:51 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> This patch registers the WM8750 codec on a proper place on the ZipitZ2
> machine after the WM8750 driver was converted to new API.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Applied to 'devel'.


From eric.y.miao at gmail.com  Tue Jun  8 03:43:52 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 8 Jun 2010 15:43:52 +0800
Subject: [GIT PULL] pxa: fixes for v2.6.34-rc1
In-Reply-To: <201005311650.54729.marek.vasut@gmail.com>
References: <AANLkTillgu4x49AMo9f6NMmmZvoMQRFaenfwi9d62W__@mail.gmail.com> 
	<4C036207.5070701@canonical.com>
	<AANLkTikF62qGENmyl9mYKXZskVKb8pgD8f-t7G6PsLxo@mail.gmail.com> 
	<201005311650.54729.marek.vasut@gmail.com>
Message-ID: <AANLkTikh60F913vF_JS_ITvFYulv1LsfStnQ3St2Fs5y@mail.gmail.com>

On Mon, May 31, 2010 at 10:50 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dne Po 31. kv?tna 2010 09:42:59 Eric Miao napsal(a):
>> On Mon, May 31, 2010 at 3:15 PM, Bryan Wu <bryan.wu at canonical.com> wrote:
>> > Just a minor thing, the subject of this email should be "[GIT PULL] pxa:
>> > fixes for v2.6.35-rc1"
>>
>> Ah right, it was popped out with gmail's auto completion, which is smart
>> doing a good job at most times, but apparently not always.
>
> Didn't you miss the Z2 patches possibly? There were for the same thing (wm8750
> and battery ... I'll resend). Of course, they'll go through later.

Marek,

They don't actually fix anything and are merged into 'devel'.

Russell,

Please pull again, sorry about the delay to clarify the above.


From eric.y.miao at gmail.com  Tue Jun  8 03:55:29 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 8 Jun 2010 15:55:29 +0800
Subject: [PATCH] pxa168 and pxa930 build fix - plat-pxa/pmu.c dependent on
	ARCH_PXA for IRQ_PMU
In-Reply-To: <AANLkTilXErDZHWf71e7pwUbt1i66MVrfP_lPisgoBZ0G@mail.gmail.com>
References: <1275932959-474-1-git-send-email-jic23@cam.ac.uk> 
	<AANLkTilXErDZHWf71e7pwUbt1i66MVrfP_lPisgoBZ0G@mail.gmail.com>
Message-ID: <AANLkTinm5ZU1tLR8CYwU4K8FPbCdLTdAyrfXq54nYkl_@mail.gmail.com>

On Tue, Jun 8, 2010 at 2:57 PM, Wan ZongShun <mcuos.com at gmail.com> wrote:
> 2010/6/8 Jonathan Cameron <jic23 at cam.ac.uk>:
>> Signed-off-by: Jonathan Cameron <jic23 at cam.ac.uk>
>> ---
>> ?Found this build issue whilst browsing kautobuild logs.
>> ?There may well be a better fix but until someone with
>> ?a board in ARCH_MMP can test it, lets just not build
>> ?pmu.c. ?Can't find equivalent fix in Eric's tree so I
>> ?think this is still a live problem.
>>
>
> When building pxa168 platform, IRQ_PMU cannot be find and error occurs.
> Eric, before delete it from MMP, should not we check whether the
> performance counter function
> is necessary for MMP or not?
>
> If necessary , we should fix this issue by define IRQ_PMU to
> IRQ_PXA168_PMU, or we can delete it.
>

We have different ways to handle this:

1. register different platform devices with different IRQs for pxa[23]xx, pxa168
2. modify the IRQ at run-time to a correct one
3. move the platform device registration back into arch/arm/mach-pxa/<soc>.c
(or arch/arm/mach-pxa/common.c) and arch/arm/mach-mmp/<soc>.c

We need to figure out if there are some other differences between these
PMUs (or in the future), which will make solution 3) stand out.

>> ?arch/arm/plat-pxa/Makefile | ? ?3 ++-
>> ?1 files changed, 2 insertions(+), 1 deletions(-)
>>
>> diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
>> index 6187edf..a17cc0c 100644
>> --- a/arch/arm/plat-pxa/Makefile
>> +++ b/arch/arm/plat-pxa/Makefile
>> @@ -2,8 +2,9 @@
>> ?# Makefile for code common across different PXA processor families
>> ?#
>>
>> -obj-y ?:= dma.o pmu.o
>> +obj-y ?:= dma.o
>>
>> +obj-$(CONFIG_ARCH_PXA) ? ? ? ? += pmu.o
>> ?obj-$(CONFIG_GENERIC_GPIO) ? ? += gpio.o
>> ?obj-$(CONFIG_PXA3xx) ? ? ? ? ? += mfp.o
>> ?obj-$(CONFIG_ARCH_MMP) ? ? ? ? += mfp.o
>> --
>> 1.6.4.4
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>
>
>
> --
> *linux-arm-kernel mailing list
> mail addr:linux-arm-kernel at lists.infradead.org
> you can subscribe by:
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> * linux-arm-NUC900 mailing list
> mail addr:NUC900 at googlegroups.com
> main web: https://groups.google.com/group/NUC900
> you can subscribe it by sending me mail:
> mcuos.com at gmail.com
>


From ben-linux at fluff.org  Tue Jun  8 04:22:13 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Tue, 8 Jun 2010 09:22:13 +0100
Subject: away 7th - 14th
Message-ID: <20100608082213.GB14272@trinity.fluff.org>

As an FYI, away from 7th-14th June, and then will be back on BST

Will have some access to email, but not to boards.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From will.deacon at arm.com  Tue Jun  8 04:52:31 2010
From: will.deacon at arm.com (Will Deacon)
Date: Tue, 8 Jun 2010 09:52:31 +0100
Subject: [PATCH] pxa168 and pxa930 build fix - plat-pxa/pmu.c dependent on
	ARCH_PXA for IRQ_PMU
In-Reply-To: <AANLkTinm5ZU1tLR8CYwU4K8FPbCdLTdAyrfXq54nYkl_@mail.gmail.com>
References: <1275932959-474-1-git-send-email-jic23@cam.ac.uk>
	<AANLkTilXErDZHWf71e7pwUbt1i66MVrfP_lPisgoBZ0G@mail.gmail.com>
	<AANLkTinm5ZU1tLR8CYwU4K8FPbCdLTdAyrfXq54nYkl_@mail.gmail.com>
Message-ID: <003001cb06e7$ee5aa100$cb0fe300$@deacon@arm.com>

Hi Eric,

> We have different ways to handle this:
> 
> 1. register different platform devices with different IRQs for pxa[23]xx, pxa168
> 2. modify the IRQ at run-time to a correct one
> 3. move the platform device registration back into arch/arm/mach-pxa/<soc>.c
> (or arch/arm/mach-pxa/common.c) and arch/arm/mach-mmp/<soc>.c

For the RealView boards, we take approach number (1). This is largely for two
reasons:

1.) The PMU IRQ doesn't have a consistent naming scheme
2.) SMP RealView platforms need to have an extra resource in the
    platform_device for each CPU.

However, looking at the PXA168 description and the perf-events code,
I don't think we support the PMU anyway [see init_hw_perf_events in
arch/arm/kernel/perf_event.c]. If the PMU present is accessible in the
same way as one of the other supported PMUs, then it would be easy to
add it to the perf-events code. Otherwise, a new PMU driver will need
to be written if people want to use it.

Without access to a TRM, I can't tell whether or not supporting the PMU
is trivial, so I guess we go with option (3) for the time being.

> We need to figure out if there are some other differences between these
> PMUs (or in the future), which will make solution 3) stand out.

In the future I reckon PMU devices will be memory-mapped and live inside
components other than the CPU. PMU registration will then be highly SoC-specific.
Perf events doesn't yet support any of this, so it depends how future-proof you
want to be!

Will

> >>  arch/arm/plat-pxa/Makefile |    3 ++-
> >>  1 files changed, 2 insertions(+), 1 deletions(-)
> >>
> >> diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
> >> index 6187edf..a17cc0c 100644
> >> --- a/arch/arm/plat-pxa/Makefile
> >> +++ b/arch/arm/plat-pxa/Makefile
> >> @@ -2,8 +2,9 @@
> >>  # Makefile for code common across different PXA processor families
> >>  #
> >>
> >> -obj-y  := dma.o pmu.o
> >> +obj-y  := dma.o
> >>
> >> +obj-$(CONFIG_ARCH_PXA)         += pmu.o
> >>  obj-$(CONFIG_GENERIC_GPIO)     += gpio.o
> >>  obj-$(CONFIG_PXA3xx)           += mfp.o
> >>  obj-$(CONFIG_ARCH_MMP)         += mfp.o
> >> --
> >> 1.6.4.4




From mcuos.com at gmail.com  Tue Jun  8 04:58:19 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Tue, 8 Jun 2010 16:58:19 +0800
Subject: [RFC] pxa: about ac97 for public use
Message-ID: <AANLkTinVD25v8HyOHDPWjpev7yp_tFqy_8S8Wa5njgYs@mail.gmail.com>

Hi Eric,

Now, our pxa168 ac97 driver need the regs-ac97.h file support, but
this file was located in mach-pxa/include.
Should we move the public 'regs-ac97.h' to plat-pxa/ or create a new
one in mach-mmp/include for pxa168 ac97 driver?

-- 
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mail addr:linux-arm-kernel at lists.infradead.org
you can subscribe by:
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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mail addr:NUC900 at googlegroups.com
main web: https://groups.google.com/group/NUC900
you can subscribe it by sending me mail:
mcuos.com at gmail.com


From eric at eukrea.com  Tue Jun  8 05:02:55 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Tue,  8 Jun 2010 11:02:55 +0200
Subject: [PATCH 1/8] MX25: put define for OTG base address in right include
Message-ID: <1275987782-16094-1-git-send-email-eric@eukrea.com>

the standard place for this define is include/mach/mx25.h

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/mach-mx25/devices.c          |    2 --
 arch/arm/plat-mxc/include/mach/mx25.h |    1 +
 2 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 3a405fa..032a347 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -117,8 +117,6 @@ struct platform_device mxc_uart_device4 = {
 	.num_resources = ARRAY_SIZE(uart4),
 };
 
-#define MX25_OTG_BASE_ADDR 0x53FF4000
-
 static u64 otg_dmamask = DMA_BIT_MASK(32);
 
 static struct resource mxc_otg_resources[] = {
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 4eb6e33..bc0ba27 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -34,6 +34,7 @@
 #define MX25_NFC_BASE_ADDR		0xbb000000
 #define MX25_DRYICE_BASE_ADDR		0x53ffc000
 #define MX25_LCDC_BASE_ADDR		0x53fbc000
+#define MX25_OTG_BASE_ADDR		0x53ff4000
 
 #define MX25_INT_DRYICE	25
 #define MX25_INT_FEC	57
-- 
1.6.3.3



From eric at eukrea.com  Tue Jun  8 05:02:56 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Tue,  8 Jun 2010 11:02:56 +0200
Subject: [PATCH 2/8] plat-mxc/ehci.c: add i.MX25 support
In-Reply-To: <1275987782-16094-1-git-send-email-eric@eukrea.com>
References: <1275987782-16094-1-git-send-email-eric@eukrea.com>
Message-ID: <1275987782-16094-2-git-send-email-eric@eukrea.com>

i.MX25's OTG has the same USBCTRL registers than i.MX35 so reuse
most of the i.MX35's defines.

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/plat-mxc/ehci.c |   46 +++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 45 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 2a86461..6184792 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -73,7 +73,51 @@
 int mxc_initialize_usb_hw(int port, unsigned int flags)
 {
 	unsigned int v;
-#ifdef CONFIG_ARCH_MX3
+#if defined(CONFIG_ARCH_MX25)
+	if (cpu_is_mx25()) {
+		v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
+				     USBCTRL_OTGBASE_OFFSET));
+
+		switch (port) {
+		case 0:	/* OTG port */
+			v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
+			v |= (flags & MXC_EHCI_INTERFACE_MASK)
+					<< MX35_OTG_SIC_SHIFT;
+			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+				v |= MX35_OTG_PM_BIT;
+
+			break;
+		case 1: /* H1 port */
+			v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+				MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+			v |= (flags & MXC_EHCI_INTERFACE_MASK)
+						<< MX35_H1_SIC_SHIFT;
+			if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+				v |= MX35_H1_PM_BIT;
+
+			if (!(flags & MXC_EHCI_TTL_ENABLED))
+				v |= MX35_H1_TLL_BIT;
+
+			if (flags & MXC_EHCI_INTERNAL_PHY)
+				v |= MX35_H1_USBTE_BIT;
+
+			if (flags & MXC_EHCI_IPPUE_DOWN)
+				v |= MX35_H1_IPPUE_DOWN_BIT;
+
+			if (flags & MXC_EHCI_IPPUE_UP)
+				v |= MX35_H1_IPPUE_UP_BIT;
+
+			break;
+		default:
+			return -EINVAL;
+		}
+
+		writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR +
+				     USBCTRL_OTGBASE_OFFSET));
+		return 0;
+	}
+#endif /* CONFIG_ARCH_MX25 */
+#if defined(CONFIG_ARCH_MX3)
 	if (cpu_is_mx31()) {
 		v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
 				     USBCTRL_OTGBASE_OFFSET));
-- 
1.6.3.3



From eric at eukrea.com  Tue Jun  8 05:02:57 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Tue,  8 Jun 2010 11:02:57 +0200
Subject: [PATCH 3/8] i.MX25: fix get_rate_otg to return the correct value
In-Reply-To: <1275987782-16094-2-git-send-email-eric@eukrea.com>
References: <1275987782-16094-1-git-send-email-eric@eukrea.com>
	<1275987782-16094-2-git-send-email-eric@eukrea.com>
Message-ID: <1275987782-16094-3-git-send-email-eric@eukrea.com>

usb drivers need to get the right value for otg clock so
calculate and return it

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/mach-mx25/clock.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 1550149..d2835ff 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -131,7 +131,10 @@ static unsigned long get_rate_lcdc(struct clk *clk)
 
 static unsigned long get_rate_otg(struct clk *clk)
 {
-	return 48000000; /* FIXME */
+	unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+	unsigned long rate = get_rate_upll();
+
+	return (cctl & (1 << 23)) ? 0 : rate / ((0x3F & (cctl >> 16)) + 1);
 }
 
 static int clk_cgcr_enable(struct clk *clk)
-- 
1.6.3.3



From eric at eukrea.com  Tue Jun  8 05:02:58 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Tue,  8 Jun 2010 11:02:58 +0200
Subject: [PATCH 4/8] i.MX25: fix EHCI support
In-Reply-To: <1275987782-16094-3-git-send-email-eric@eukrea.com>
References: <1275987782-16094-1-git-send-email-eric@eukrea.com>
	<1275987782-16094-2-git-send-email-eric@eukrea.com>
	<1275987782-16094-3-git-send-email-eric@eukrea.com>
Message-ID: <1275987782-16094-4-git-send-email-eric@eukrea.com>

i.MX25's EHCI is the same as i.MX35's one.

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 drivers/usb/host/ehci-mxc.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index 544ccfd..56f2750 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -182,7 +182,7 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
 	}
 	clk_enable(priv->usbclk);
 
-	if (!cpu_is_mx35()) {
+	if (!cpu_is_mx35() && !cpu_is_mx25()) {
 		priv->ahbclk = clk_get(dev, "usb_ahb");
 		if (IS_ERR(priv->ahbclk)) {
 			ret = PTR_ERR(priv->ahbclk);
-- 
1.6.3.3



From eric at eukrea.com  Tue Jun  8 05:02:59 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Tue,  8 Jun 2010 11:02:59 +0200
Subject: [PATCH 5/8] i.MX25: fix USB gadget support
In-Reply-To: <1275987782-16094-4-git-send-email-eric@eukrea.com>
References: <1275987782-16094-1-git-send-email-eric@eukrea.com>
	<1275987782-16094-2-git-send-email-eric@eukrea.com>
	<1275987782-16094-3-git-send-email-eric@eukrea.com>
	<1275987782-16094-4-git-send-email-eric@eukrea.com>
Message-ID: <1275987782-16094-5-git-send-email-eric@eukrea.com>

i.MX25's udc port is the same as i.MX35's one

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 drivers/usb/gadget/fsl_mxc_udc.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/gadget/fsl_mxc_udc.c b/drivers/usb/gadget/fsl_mxc_udc.c
index d0b8bde..eafa6d2 100644
--- a/drivers/usb/gadget/fsl_mxc_udc.c
+++ b/drivers/usb/gadget/fsl_mxc_udc.c
@@ -30,7 +30,7 @@ int fsl_udc_clk_init(struct platform_device *pdev)
 
 	pdata = pdev->dev.platform_data;
 
-	if (!cpu_is_mx35()) {
+	if (!cpu_is_mx35() && !cpu_is_mx25()) {
 		mxc_ahb_clk = clk_get(&pdev->dev, "usb_ahb");
 		if (IS_ERR(mxc_ahb_clk))
 			return PTR_ERR(mxc_ahb_clk);
-- 
1.6.3.3



From eric at eukrea.com  Tue Jun  8 05:03:00 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Tue,  8 Jun 2010 11:03:00 +0200
Subject: [PATCH 6/8] i.MX25: add AUDMUX and SSI support
In-Reply-To: <1275987782-16094-5-git-send-email-eric@eukrea.com>
References: <1275987782-16094-1-git-send-email-eric@eukrea.com>
	<1275987782-16094-2-git-send-email-eric@eukrea.com>
	<1275987782-16094-3-git-send-email-eric@eukrea.com>
	<1275987782-16094-4-git-send-email-eric@eukrea.com>
	<1275987782-16094-5-git-send-email-eric@eukrea.com>
Message-ID: <1275987782-16094-6-git-send-email-eric@eukrea.com>

* add clocks for audmux and ssi 1 & 2
* add irq for ssi 1 & 2
* add devices platform for ssi1 & 2
* update audmux-v2 for i.MX25
* add base addresses for audmux & ssi 1 & 2
* add iomux configuration for GPIO for AUD5 port

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/mach-mx25/clock.c                  |   18 ++++++++++++
 arch/arm/mach-mx25/devices.c                |   38 +++++++++++++++++++++++++++
 arch/arm/mach-mx25/devices.h                |    2 +
 arch/arm/plat-mxc/Kconfig                   |    1 +
 arch/arm/plat-mxc/audmux-v2.c               |   15 ++++++++++-
 arch/arm/plat-mxc/include/mach/iomux-mx25.h |    4 +++
 arch/arm/plat-mxc/include/mach/mx25.h       |    7 ++++-
 7 files changed, 83 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index d2835ff..bdf6e76 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -109,6 +109,16 @@ static unsigned long get_rate_uart(struct clk *clk)
 	return get_rate_per(15);
 }
 
+static unsigned long get_rate_ssi2(struct clk *clk)
+{
+	return get_rate_per(14);
+}
+
+static unsigned long get_rate_ssi1(struct clk *clk)
+{
+	return get_rate_per(13);
+}
+
 static unsigned long get_rate_i2c(struct clk *clk)
 {
 	return get_rate_per(6);
@@ -171,6 +181,8 @@ static void clk_cgcr_disable(struct clk *clk)
 
 DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_gpt, NULL, NULL);
 DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
+DEFINE_CLOCK(ssi1_per_clk, 0, CCM_CGCR0, 13, get_rate_ipg, NULL, NULL);
+DEFINE_CLOCK(ssi2_per_clk, 0, CCM_CGCR0, 14, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);
@@ -194,6 +206,9 @@ DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
 DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
 DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
+DEFINE_CLOCK(ssi1_clk,  0, CCM_CGCR2, 11, get_rate_ssi1, NULL, &ssi1_per_clk);
+DEFINE_CLOCK(ssi2_clk,  1, CCM_CGCR2, 12, get_rate_ssi2, NULL, &ssi2_per_clk);
+DEFINE_CLOCK(audmux_clk, 0, CCM_CGCR1, 0, NULL, NULL, NULL);
 
 #define _REGISTER_CLOCK(d, n, c)	\
 	{				\
@@ -228,6 +243,9 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("fec.0", NULL, fec_clk)
 	_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
 	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+	_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+	_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+	_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
 };
 
 int __init mx25_clocks_init(void)
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 032a347..1382fcf 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -513,3 +513,41 @@ struct platform_device mxc_wdt = {
 	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
 	.resource = mxc_wdt_resources,
 };
+
+static struct resource imx_ssi_resources0[] = {
+	{
+		.start	= MX25_SSI1_BASE_ADDR,
+		.end	= MX25_SSI1_BASE_ADDR + 0x3fff,
+		.flags	= IORESOURCE_MEM,
+	}, {
+		.start	= MX25_INT_SSI1,
+		.end	= MX25_INT_SSI1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct resource imx_ssi_resources1[] = {
+	{
+		.start	= MX25_SSI2_BASE_ADDR,
+		.end	= MX25_SSI2_BASE_ADDR + 0x3fff,
+		.flags	= IORESOURCE_MEM
+	}, {
+		.start	= MX25_INT_SSI2,
+		.end	= MX25_INT_SSI2,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device imx_ssi_device0 = {
+	.name = "imx-ssi",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(imx_ssi_resources0),
+	.resource = imx_ssi_resources0,
+};
+
+struct platform_device imx_ssi_device1 = {
+	.name = "imx-ssi",
+	.id = 1,
+	.num_resources = ARRAY_SIZE(imx_ssi_resources1),
+	.resource = imx_ssi_resources1,
+};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index cee12c0..f886e82 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -22,3 +22,5 @@ extern struct platform_device mxc_nand_device;
 extern struct platform_device mx25_rtc_device;
 extern struct platform_device mx25_fb_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device imx_ssi_device0;
+extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 7f7ad6f..902ba9e 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -25,6 +25,7 @@ config ARCH_MX25
 	select CPU_ARM926T
 	select ARCH_MXC_IOMUX_V3
 	select HAVE_FB_IMX
+	select ARCH_MXC_AUDMUX_V2
 	help
 	  This enables support for systems based on the Freescale i.MX25 family
 
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 0c2cc5c..ab94d78 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -191,6 +191,7 @@ static int mxc_audmux_v2_init(void)
 {
 	int ret;
 
+#if defined(CONFIG_ARCH_MX3)
 	if (cpu_is_mx31())
 		audmux_base = MX31_IO_ADDRESS(MX31_AUDMUX_BASE_ADDR);
 
@@ -204,7 +205,19 @@ static int mxc_audmux_v2_init(void)
 		}
 		audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
 	}
-
+#endif
+#if defined(CONFIG_ARCH_MX25)
+	if (cpu_is_mx25()) {
+		audmux_clk = clk_get(NULL, "audmux");
+		if (IS_ERR(audmux_clk)) {
+			ret = PTR_ERR(audmux_clk);
+			printk(KERN_ERR "%s: cannot get clock: %d\n", __func__,
+					ret);
+			return ret;
+		}
+		audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
+	}
+#endif
 	audmux_debugfs_init();
 
 	return 0;
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index f39220d..5bea603 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -386,15 +386,19 @@
 #define MX25_PAD_KPP_ROW3__GPIO_3_0	IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_KPP_COL0__KPP_COL0	IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL0__AUD5_TXD	IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL0__GPIO_3_1	IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_KPP_COL1__KPP_COL1	IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL1__AUD5_RXD	IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL1__GPIO_3_2	IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_KPP_COL2__KPP_COL2	IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL2__AUD5_TXC	IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL2__GPIO_3_3	IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_KPP_COL3__KPP_COL3	IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL3__AUD5_TXFS	IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL3__GPIO_3_4	IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_FEC_MDC__FEC_MDC	IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index bc0ba27..2a5cd18 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -29,17 +29,22 @@
 
 #define MX25_UART1_BASE_ADDR		0x43f90000
 #define MX25_UART2_BASE_ADDR		0x43f94000
+#define MX25_AUDMUX_BASE_ADDR		0x43fb0000
 
 #define MX25_FEC_BASE_ADDR		0x50038000
+#define MX25_SSI2_BASE_ADDR		0x50014000
+#define MX25_SSI1_BASE_ADDR		0x50034000
 #define MX25_NFC_BASE_ADDR		0xbb000000
 #define MX25_DRYICE_BASE_ADDR		0x53ffc000
 #define MX25_LCDC_BASE_ADDR		0x53fbc000
 #define MX25_OTG_BASE_ADDR		0x53ff4000
 
+#define MX25_INT_SSI2	11
+#define MX25_INT_SSI1	12
 #define MX25_INT_DRYICE	25
-#define MX25_INT_FEC	57
 #define MX25_INT_NANDFC	33
 #define MX25_INT_LCDC	39
+#define MX25_INT_FEC	57
 
 #if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
 #define UART1_BASE_ADDR			MX25_UART1_BASE_ADDR
-- 
1.6.3.3



From eric at eukrea.com  Tue Jun  8 05:03:01 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Tue,  8 Jun 2010 11:03:01 +0200
Subject: [PATCH 7/8] i.MX25: add cpuimx25 module and its baseboard
In-Reply-To: <1275987782-16094-6-git-send-email-eric@eukrea.com>
References: <1275987782-16094-1-git-send-email-eric@eukrea.com>
	<1275987782-16094-2-git-send-email-eric@eukrea.com>
	<1275987782-16094-3-git-send-email-eric@eukrea.com>
	<1275987782-16094-4-git-send-email-eric@eukrea.com>
	<1275987782-16094-5-git-send-email-eric@eukrea.com>
	<1275987782-16094-6-git-send-email-eric@eukrea.com>
Message-ID: <1275987782-16094-7-git-send-email-eric@eukrea.com>

* cpuimx25 integrates i.MX25, RAM, NAND, Ethernet, I2C RTC, USB Host
and USB OTG
* mbimxsd provides access to LCD, Audio, LED, Switch button, UART ...

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/mach-mx25/Kconfig                         |   18 ++
 arch/arm/mach-mx25/Makefile                        |    2 +
 arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c      |  260 ++++++++++++++++++++
 arch/arm/mach-mx25/mach-cpuimx25.c                 |  172 +++++++++++++
 .../plat-mxc/include/mach/board-eukrea_cpuimx25.h  |   40 +++
 5 files changed, 492 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
 create mode 100644 arch/arm/mach-mx25/mach-cpuimx25.c
 create mode 100644 arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx25.h

diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index 54d2173..3a6668e 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -5,4 +5,22 @@ comment "MX25 platforms:"
 config MACH_MX25_3DS
 	bool "Support MX25PDK (3DS) Platform"
 
+config MACH_EUKREA_CPUIMX25
+	bool "Support Eukrea CPUIMX25 Platform"
+	select MXC_ULPI if USB_ULPI
+
+choice
+	prompt "Baseboard"
+	depends on MACH_EUKREA_CPUIMX25
+	default MACH_EUKREA_MBIMXSD_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD_BASEBOARD
+	prompt "Eukrea MBIMXSD development board"
+	bool
+	help
+	  This adds board specific devices that can be found on Eukrea's
+	  MBIMXSD evaluation board.
+
+endchoice
+
 endif
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
index 10cebc5..83ab5d8 100644
--- a/arch/arm/mach-mx25/Makefile
+++ b/arch/arm/mach-mx25/Makefile
@@ -1,3 +1,5 @@
 obj-y				:= mm.o devices.o
 obj-$(CONFIG_ARCH_MX25)		+= clock.o
 obj-$(CONFIG_MACH_MX25_3DS)	+= mach-mx25pdk.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX25)		+= mach-cpuimx25.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD)	+= eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 0000000..e0f0dfd
--- /dev/null
+++ b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,260 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric at eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel at pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <video/platform_lcd.h>
+
+#include <mach/board-eukrea_cpuimx25.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx25.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/mx25.h>
+#include <mach/imx-uart.h>
+#include <mach/imxfb.h>
+#include <mach/ssi.h>
+#include <mach/audmux.h>
+
+#include "devices.h"
+
+static struct pad_desc eukrea_mbimxsd_pads[] = {
+	/* LCD */
+	MX25_PAD_LD0__LD0,
+	MX25_PAD_LD1__LD1,
+	MX25_PAD_LD2__LD2,
+	MX25_PAD_LD3__LD3,
+	MX25_PAD_LD4__LD4,
+	MX25_PAD_LD5__LD5,
+	MX25_PAD_LD6__LD6,
+	MX25_PAD_LD7__LD7,
+	MX25_PAD_LD8__LD8,
+	MX25_PAD_LD9__LD9,
+	MX25_PAD_LD10__LD10,
+	MX25_PAD_LD11__LD11,
+	MX25_PAD_LD12__LD12,
+	MX25_PAD_LD13__LD13,
+	MX25_PAD_LD14__LD14,
+	MX25_PAD_LD15__LD15,
+	MX25_PAD_GPIO_E__LD16,
+	MX25_PAD_GPIO_F__LD17,
+	MX25_PAD_HSYNC__HSYNC,
+	MX25_PAD_VSYNC__VSYNC,
+	MX25_PAD_LSCLK__LSCLK,
+	MX25_PAD_OE_ACD__OE_ACD,
+	MX25_PAD_CONTRAST__CONTRAST,
+	/* LCD_PWR */
+	MX25_PAD_PWM__GPIO_1_26,
+	/* LED */
+	MX25_PAD_POWER_FAIL__GPIO_3_19,
+	/* SWITCH */
+	MX25_PAD_VSTBY_ACK__GPIO_3_18,
+	/* UART2 */
+	MX25_PAD_UART2_RTS__UART2_RTS,
+	MX25_PAD_UART2_CTS__UART2_CTS,
+	MX25_PAD_UART2_TXD__UART2_TXD,
+	MX25_PAD_UART2_RXD__UART2_RXD,
+	/* SD1 */
+	MX25_PAD_SD1_CMD__SD1_CMD,
+	MX25_PAD_SD1_CLK__SD1_CLK,
+	MX25_PAD_SD1_DATA0__SD1_DATA0,
+	MX25_PAD_SD1_DATA1__SD1_DATA1,
+	MX25_PAD_SD1_DATA2__SD1_DATA2,
+	MX25_PAD_SD1_DATA3__SD1_DATA3,
+	/* SD1 CD */
+	MX25_PAD_DE_B__GPIO_2_20,
+	/* I2S */
+	MX25_PAD_KPP_COL3__AUD5_TXFS,
+	MX25_PAD_KPP_COL2__AUD5_TXC,
+	MX25_PAD_KPP_COL1__AUD5_RXD,
+	MX25_PAD_KPP_COL0__AUD5_TXD,
+};
+
+#define GPIO_LED1	83
+#define GPIO_SWITCH1	82
+#define GPIO_SD1CD	52
+#define GPIO_LCDPWR	26
+
+static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
+	{
+		.mode	= {
+			.name		= "CMO-QVGA",
+			.refresh	= 60,
+			.xres		= 320,
+			.yres		= 240,
+			.pixclock	= KHZ2PICOS(6500),
+			.left_margin	= 30,
+			.right_margin	= 38,
+			.upper_margin	= 20,
+			.lower_margin	= 3,
+			.hsync_len	= 15,
+			.vsync_len	= 4,
+		},
+		.bpp	= 16,
+		.pcr	= 0xCAD08B80,
+	},
+};
+
+static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
+	.mode		= eukrea_mximxsd_modes,
+	.num_modes	= ARRAY_SIZE(eukrea_mximxsd_modes),
+	.pwmr		= 0x00A903FF,
+	.lscr1		= 0x00120300,
+	.dmacr		= 0x00040060,
+};
+
+static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
+				   unsigned int power)
+{
+	if (power)
+		gpio_direction_output(GPIO_LCDPWR, 1);
+	else
+		gpio_direction_output(GPIO_LCDPWR, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
+	.set_power		= eukrea_mbimxsd_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
+	.name			= "platform-lcd",
+	.dev.platform_data	= &eukrea_mbimxsd_lcd_power_data,
+};
+
+static struct gpio_led eukrea_mbimxsd_leds[] = {
+	{
+		.name			= "led1",
+		.default_trigger	= "heartbeat",
+		.active_low		= 1,
+		.gpio			= GPIO_LED1,
+	},
+};
+
+static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+	.leds		= eukrea_mbimxsd_leds,
+	.num_leds	= ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct platform_device eukrea_mbimxsd_leds_gpio = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &eukrea_mbimxsd_led_info,
+	},
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+	{
+		.gpio		= GPIO_SWITCH1,
+		.code		= BTN_0,
+		.desc		= "BP1",
+		.active_low	= 1,
+		.wakeup		= 1,
+	},
+};
+
+static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+	.buttons	= eukrea_mbimxsd_gpio_buttons,
+	.nbuttons	= ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static struct platform_device eukrea_mbimxsd_button_device = {
+	.name		= "gpio-keys",
+	.id		= -1,
+	.num_resources	= 0,
+	.dev		= {
+		.platform_data	= &eukrea_mbimxsd_button_data,
+	}
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+	&eukrea_mbimxsd_leds_gpio,
+	&eukrea_mbimxsd_button_device,
+	&eukrea_mbimxsd_lcd_powerdev,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("tlv320aic23", 0x1a),
+	},
+};
+
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+	.flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx25 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd_baseboard_init(void)
+{
+	if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+			ARRAY_SIZE(eukrea_mbimxsd_pads)))
+		printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+	/* SSI unit master I2S codec connected to SSI_AUD5*/
+	mxc_audmux_v2_configure_port(0,
+			MXC_AUDMUX_V2_PTCR_SYN |
+			MXC_AUDMUX_V2_PTCR_TFSDIR |
+			MXC_AUDMUX_V2_PTCR_TFSEL(4) |
+			MXC_AUDMUX_V2_PTCR_TCLKDIR |
+			MXC_AUDMUX_V2_PTCR_TCSEL(4),
+			MXC_AUDMUX_V2_PDCR_RXDSEL(4)
+	);
+	mxc_audmux_v2_configure_port(4,
+			MXC_AUDMUX_V2_PTCR_SYN,
+			MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+	);
+#endif
+
+	mxc_register_device(&mxc_uart_device1, &uart_pdata);
+	mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
+	mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+
+	gpio_request(GPIO_LED1, "LED1");
+	gpio_direction_output(GPIO_LED1, 1);
+	gpio_free(GPIO_LED1);
+
+	gpio_request(GPIO_SWITCH1, "SWITCH1");
+	gpio_direction_input(GPIO_SWITCH1);
+	gpio_free(GPIO_SWITCH1);
+
+	gpio_request(GPIO_LCDPWR, "LCDPWR");
+	gpio_direction_output(GPIO_LCDPWR, 1);
+	gpio_free(GPIO_SWITCH1);
+
+	i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+				ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
new file mode 100644
index 0000000..4796484
--- /dev/null
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -0,0 +1,172 @@
+/*
+ * Copyright 2009 Sascha Hauer, <kernel at pengutronix.de>
+ * Copyright 2010 Eric B?nard - Eukr?a Electromatique, <eric at eukrea.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/fec.h>
+#include <linux/platform_device.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
+
+#include <mach/board-eukrea_cpuimx25.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/i2c.h>
+#include <mach/mx25.h>
+#include <mach/mxc_nand.h>
+#include <mach/imxfb.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+
+#include "devices.h"
+#include <mach/iomux-mx25.h>
+
+static struct imxuart_platform_data uart_pdata = {
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct pad_desc eukrea_cpuimx25_pads[] = {
+	/* FEC - RMII */
+	MX25_PAD_FEC_MDC__FEC_MDC,
+	MX25_PAD_FEC_MDIO__FEC_MDIO,
+	MX25_PAD_FEC_TDATA0__FEC_TDATA0,
+	MX25_PAD_FEC_TDATA1__FEC_TDATA1,
+	MX25_PAD_FEC_TX_EN__FEC_TX_EN,
+	MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+	MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+	MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+	/* I2C1 */
+	MX25_PAD_I2C1_CLK__I2C1_CLK,
+	MX25_PAD_I2C1_DAT__I2C1_DAT,
+};
+
+static struct fec_platform_data mx25_fec_pdata = {
+	.phy	= PHY_INTERFACE_MODE_RMII,
+};
+
+static struct mxc_nand_platform_data eukrea_cpuimx25_nand_board_info = {
+	.width		= 1,
+	.hw_ecc		= 1,
+	.flash_bbt	= 1,
+};
+
+static struct imxi2c_platform_data eukrea_cpuimx25_i2c_1_data = {
+	.bitrate = 100000,
+};
+
+static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("pcf8563", 0x51),
+	},
+};
+
+static struct mxc_usbh_platform_data otg_pdata = {
+	.portsc	= MXC_EHCI_MODE_UTMI,
+	.flags	= MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata = {
+	.portsc	= MXC_EHCI_MODE_SERIAL,
+	.flags	= MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
+		  MXC_EHCI_IPPUE_DOWN,
+};
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+	.operating_mode = FSL_USB2_DR_DEVICE,
+	.phy_mode       = FSL_USB2_PHY_UTMI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx25_otg_mode(char *options)
+{
+	if (!strcmp(options, "host"))
+		otg_mode_host = 1;
+	else if (!strcmp(options, "device"))
+		otg_mode_host = 0;
+	else
+		pr_info("otg_mode neither \"host\" nor \"device\". "
+			"Defaulting to device\n");
+	return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx25_otg_mode);
+
+static void __init eukrea_cpuimx25_init(void)
+{
+	if (mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx25_pads,
+			ARRAY_SIZE(eukrea_cpuimx25_pads)))
+		printk(KERN_ERR "error setting cpuimx25 pads !\n");
+
+	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	mxc_register_device(&mxc_nand_device, &eukrea_cpuimx25_nand_board_info);
+	mxc_register_device(&mx25_rtc_device, NULL);
+	mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+
+	i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
+				ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
+	mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx25_i2c_1_data);
+
+#if defined(CONFIG_USB_ULPI)
+	if (otg_mode_host) {
+		otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+		mxc_register_device(&mxc_otg, &otg_pdata);
+	}
+	mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+#endif
+	if (!otg_mode_host)
+		mxc_register_device(&otg_udc_device, &otg_device_pdata);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
+	eukrea_mbimxsd_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx25_timer_init(void)
+{
+	mx25_clocks_init();
+}
+
+static struct sys_timer eukrea_cpuimx25_timer = {
+	.init   = eukrea_cpuimx25_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX25, "Eukrea CPUIMX25")
+	/* Maintainer: Eukrea Electromatique */
+	.phys_io	= MX25_AIPS1_BASE_ADDR,
+	.io_pg_offst	= ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+	.boot_params    = MX25_PHYS_OFFSET + 0x100,
+	.map_io         = mx25_map_io,
+	.init_irq       = mx25_init_irq,
+	.init_machine   = eukrea_cpuimx25_init,
+	.timer          = &eukrea_cpuimx25_timer,
+MACHINE_END
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx25.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx25.h
new file mode 100644
index 0000000..5c9901e
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx25.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric at eukrea.com
+ *
+ * Based on board-pcm038.h which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel at pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX25_H__
+#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX25_H__
+
+#ifndef __ASSEMBLY__
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ * TODO: Add your own baseboard init function and call it from
+ * inside eukrea_cpuimx25_init().
+ *
+ * This example here is for the development board. Refer
+ * eukrea_mbimx25-baseboard.c
+ */
+
+extern void eukrea_mbimxsd_baseboard_init(void);
+
+#endif
+
+#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX25_H__ */
-- 
1.6.3.3



From eric at eukrea.com  Tue Jun  8 05:03:02 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Tue,  8 Jun 2010 11:03:02 +0200
Subject: [PATCH 8/8] eukrea-tlv320: add support for our i.MX25 board
In-Reply-To: <1275987782-16094-7-git-send-email-eric@eukrea.com>
References: <1275987782-16094-1-git-send-email-eric@eukrea.com>
	<1275987782-16094-2-git-send-email-eric@eukrea.com>
	<1275987782-16094-3-git-send-email-eric@eukrea.com>
	<1275987782-16094-4-git-send-email-eric@eukrea.com>
	<1275987782-16094-5-git-send-email-eric@eukrea.com>
	<1275987782-16094-6-git-send-email-eric@eukrea.com>
	<1275987782-16094-7-git-send-email-eric@eukrea.com>
Message-ID: <1275987782-16094-8-git-send-email-eric@eukrea.com>

* tdm slot has to be configured to get sound working on i.MX25

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 sound/soc/imx/Kconfig         |    2 +-
 sound/soc/imx/eukrea-tlv320.c |    3 ++-
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/sound/soc/imx/Kconfig b/sound/soc/imx/Kconfig
index fd292f1..fd616ae 100644
--- a/sound/soc/imx/Kconfig
+++ b/sound/soc/imx/Kconfig
@@ -31,7 +31,7 @@ config SND_SOC_PHYCORE_AC97
 
 config SND_SOC_EUKREA_TLV320
 	bool "Eukrea TLV320"
-	depends on MACH_EUKREA_MBIMX27_BASEBOARD
+	depends on MACH_EUKREA_MBIMX27_BASEBOARD || MACH_EUKREA_MBIMXSD_BASEBOARD
 	select SND_MXC_SOC_SSI
 	select SND_SOC_TLV320AIC23
 	help
diff --git a/sound/soc/imx/eukrea-tlv320.c b/sound/soc/imx/eukrea-tlv320.c
index 968380a..45f5e4b 100644
--- a/sound/soc/imx/eukrea-tlv320.c
+++ b/sound/soc/imx/eukrea-tlv320.c
@@ -60,6 +60,7 @@ static int eukrea_tlv320_hw_params(struct snd_pcm_substream *substream,
 		pr_err("%s: failed setting codec sysclk\n", __func__);
 		return ret;
 	}
+	snd_soc_dai_set_tdm_slot(cpu_dai, 0xffffffc, 0xffffffc, 2, 0);
 
 	ret = snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0,
 				SND_SOC_CLOCK_IN);
@@ -100,7 +101,7 @@ static int __init eukrea_tlv320_init(void)
 {
 	int ret;
 
-	if (!machine_is_eukrea_cpuimx27())
+	if (!machine_is_eukrea_cpuimx27() && !machine_is_eukrea_cpuimx25sd())
 		/* return happy. We might run on a totally different machine */
 		return 0;
 
-- 
1.6.3.3



From kgene.kim at samsung.com  Tue Jun  8 05:06:55 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue,  8 Jun 2010 18:06:55 +0900
Subject: [PATCH v2 0/5] Add support for Samsung CF controller
Message-ID: <1275988020-29000-1-git-send-email-kgene.kim@samsung.com>

This is v2 of the patchset adding support for Samsung's CF controller. 
Note: Depends on Ben Dook's platform_data helper patch

Changes since v1:

	- Made a seperate patch for plat-samsung changes
	- Moved CF true-ide configuration to driver code from
	  platform-specific setup code
	- Reduced memory allocated for CF device  
	- Renamed driver file to pata_samsung_cf.c
	- Used resource_size() function in ioremap
	- Used new dev_pm_ops

	- readl/writel functions consistently used
	- Used ata_pio_need_iordy, ata_timing_find_mode for setting up
	  pio mode instead of using own timing parameters
	- Removed useless checks in tf functions
	- Added overrides for sff_dev_select, sff_check_altstatus and
	  sff_set_devctl
	- Used platform_get_drvdata/platform_set_drvdata
	- Added request_mem_region which was missing 
	- Misc coding guideline changes - typos, extra includes,
	  parenthesis etc.

	- Changed the device naming override to follow onenand/iic style.

	- Removed the qc_prep override
	- Based the new patch on upstream branch of libata-dev

	- Used 'linux/gpio.h' in place of 'mach/gpio.h'

This patch set includes the following patches:

[PATCH v2 1/5] libata: pata_samsung: Add Samsung PATA controller driver
[PATCH v2 2/5] ARM: SAMSUNG: Add Compact Flash device support for Samsung SoCs
[PATCH v2 3/5] ARM: S3C64XX: Add support for Compact Flash driver on SMDK6410
[PATCH v2 4/5] ARM: S5PC100: Add support for Compact Flash driver on SMDKC100
[PATCH v2 5/5] ARM: S5PV210: Add support for Compact Flash driver on SMDKV210/C110


From kgene.kim at samsung.com  Tue Jun  8 05:06:58 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue,  8 Jun 2010 18:06:58 +0900
Subject: [PATCH v2 3/5] ARM: S3C64XX: Add support for Compact Flash driver on
	SMDK6410
In-Reply-To: <1275988020-29000-1-git-send-email-kgene.kim@samsung.com>
References: <1275988020-29000-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1275988020-29000-4-git-send-email-kgene.kim@samsung.com>

From: Abhilash Kesavan <a.kesavan at samsung.com>

Following is added for the CF-ATA driver:
	- Platform data strucure instantiation
	- Platform device enabling code
	- Addition of cfcon clock
	- Platform-specific gpio setup code

Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
Signed-off-by: Thomas Abraham <thomas.ab at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s3c64xx/Kconfig                   |    7 +++
 arch/arm/mach-s3c64xx/Makefile                  |    1 +
 arch/arm/mach-s3c64xx/clock.c                   |    6 +++
 arch/arm/mach-s3c64xx/include/mach/map.h        |    4 ++
 arch/arm/mach-s3c64xx/include/mach/regs-clock.h |    5 ++
 arch/arm/mach-s3c64xx/mach-smdk6410.c           |    8 ++++
 arch/arm/mach-s3c64xx/s3c6410.c                 |    2 +
 arch/arm/mach-s3c64xx/setup-ide.c               |   46 +++++++++++++++++++++++
 8 files changed, 79 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s3c64xx/setup-ide.c

diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index f5a5972..12f063b 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -57,6 +57,11 @@ config S3C64XX_SETUP_I2C1
 	help
 	  Common setup code for i2c bus 1.
 
+config S3C64XX_SETUP_IDE
+	bool
+	help
+	  Common setup code for S3C64XX IDE.
+
 config S3C64XX_SETUP_FB_24BPP
 	bool
 	help
@@ -95,6 +100,7 @@ config MACH_SMDK6410
 	select S3C_DEV_HSMMC
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_I2C1
+	select SAMSUNG_DEV_IDE
 	select S3C_DEV_FB
 	select SAMSUNG_DEV_TS
 	select S3C_DEV_USB_HOST
@@ -103,6 +109,7 @@ config MACH_SMDK6410
 	select HAVE_S3C2410_WATCHDOG
 	select S3C64XX_SETUP_SDHCI
 	select S3C64XX_SETUP_I2C1
+	select S3C64XX_SETUP_IDE
 	select S3C64XX_SETUP_FB_24BPP
 	help
 	  Machine support for the Samsung SMDK6410
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 9d10069..aa5c367 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_S3C64XX_DMA)	+= dma.o
 
 obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
 obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
+obj-$(CONFIG_S3C64XX_SETUP_IDE) += setup-ide.o
 obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
 obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
 obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index fbd85a9..7772f92 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -310,6 +310,12 @@ static struct clk init_clocks[] = {
 		.id		= -1,
 		.parent		= &clk_p,
 		.ctrlbit	= S3C_CLKCON_PCLK_AC97,
+	}, {
+		.name		= "cfcon",
+		.id		= -1,
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_IHOST,
 	}
 };
 
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index e1eab3c..1caaa5f 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -86,6 +86,9 @@
 #define S3C64XX_SZ_GPIO		SZ_4K
 
 #define S3C64XX_PA_SDRAM	(0x50000000)
+
+#define S3C64XX_PA_CFCON	(0x70300000)
+
 #define S3C64XX_PA_VIC0		(0x71200000)
 #define S3C64XX_PA_VIC1		(0x71300000)
 
@@ -120,5 +123,6 @@
 #define S3C_PA_WDT		S3C64XX_PA_WATCHDOG
 
 #define SAMSUNG_PA_ADC		S3C64XX_PA_ADC
+#define SAMSUNG_PA_CFCON	S3C64XX_PA_CFCON
 
 #endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
index 0114eb0..05332b9 100644
--- a/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-clock.h
@@ -34,6 +34,7 @@
 #define S3C_SCLK_GATE		S3C_CLKREG(0x38)
 #define S3C_MEM0_GATE		S3C_CLKREG(0x3C)
 #define S3C6410_CLK_SRC2	S3C_CLKREG(0x10C)
+#define S3C_MEM_SYS_CFG		S3C_CLKREG(0x120)
 
 /* CLKDIV0 */
 #define S3C6400_CLKDIV0_PCLK_MASK	(0xf << 12)
@@ -154,4 +155,8 @@
 #define S3C6400_CLKSRC_EPLL_MOUT_SHIFT	(2)
 #define S3C6400_CLKSRC_MFC		(1 << 4)
 
+/* MEM_SYS_CFG */
+#define MEM_SYS_CFG_INDEP_CF		0x4000
+#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON	0x30
+
 #endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index d9a0355..0d7d93f 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -56,6 +56,7 @@
 #include <mach/regs-gpio.h>
 #include <mach/regs-sys.h>
 #include <mach/regs-srom.h>
+#include <plat/ata.h>
 #include <plat/iic.h>
 #include <plat/fb.h>
 #include <plat/gpio-cfg.h>
@@ -242,6 +243,10 @@ static struct platform_device smdk6410_b_pwr_5v = {
 };
 #endif
 
+static struct s3c_ide_platdata smdk6410_ide_pdata __initdata = {
+	.setup_gpio	= s3c64xx_ide_setup_gpio,
+};
+
 static struct map_desc smdk6410_iodesc[] = {};
 
 static struct platform_device *smdk6410_devices[] __initdata = {
@@ -265,6 +270,7 @@ static struct platform_device *smdk6410_devices[] __initdata = {
 
 	&smdk6410_smsc911x,
 	&s3c_device_adc,
+	&s3c_device_cfcon,
 	&s3c_device_ts,
 	&s3c_device_wdt,
 };
@@ -665,6 +671,8 @@ static void __init smdk6410_machine_init(void)
 	i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 
+	s3c_ide_set_platdata(&smdk6410_ide_pdata);
+
 	platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
 }
 
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 014401c..3ad25d2 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -37,6 +37,7 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
 #include <plat/sdhci.h>
+#include <plat/ata-core.h>
 #include <plat/iic-core.h>
 #include <plat/adc.h>
 #include <plat/onenand-core.h>
@@ -58,6 +59,7 @@ void __init s3c6410_map_io(void)
 	s3c_device_nand.name = "s3c6400-nand";
 	s3c_onenand_setname("s3c6410-onenand");
 	s3c64xx_onenand1_setname("s3c6410-onenand");
+	s3c_cfcon_setname("s3c64xx-pata");
 }
 
 void __init s3c6410_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c64xx/setup-ide.c b/arch/arm/mach-s3c64xx/setup-ide.c
new file mode 100644
index 0000000..c12c315
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-ide.c
@@ -0,0 +1,46 @@
+/* linux/arch/arm/mach-s3c64xx/setup-ide.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S3C64XX setup information for IDE
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+#include <plat/gpio-cfg.h>
+
+void s3c64xx_ide_setup_gpio(void)
+{
+	u32 reg;
+	u32 gpio = 0;
+
+	reg = readl(S3C_MEM_SYS_CFG) & (~0x3f);
+
+	/* Independent CF interface, CF chip select configuration */
+	writel(reg | MEM_SYS_CFG_INDEP_CF |
+		MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S3C_MEM_SYS_CFG);
+
+	s3c_gpio_cfgpin(S3C64XX_GPB(4), S3C_GPIO_SFN(4));
+
+	/* Set XhiDATA[15:0] pins as CF Data[15:0] */
+	for (gpio = S3C64XX_GPK(0); gpio <= S3C64XX_GPK(15); gpio++)
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(5));
+
+	/* Set XhiADDR[2:0] pins as CF ADDR[2:0] */
+	for (gpio = S3C64XX_GPL(0); gpio <= S3C64XX_GPL(2); gpio++)
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
+
+	/* Set Xhi ctrl pins as CF ctrl pins(IORDY, IOWR, IORD, CE[0:1]) */
+	s3c_gpio_cfgpin(S3C64XX_GPM(5), S3C_GPIO_SFN(1));
+	for (gpio = S3C64XX_GPM(0); gpio <= S3C64XX_GPM(4); gpio++)
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(6));
+}
-- 
1.6.2.5



From kgene.kim at samsung.com  Tue Jun  8 05:06:59 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue,  8 Jun 2010 18:06:59 +0900
Subject: [PATCH v2 4/5] ARM: S5PC100: Add support for Compact Flash driver on
	SMDKC100
In-Reply-To: <1275988020-29000-1-git-send-email-kgene.kim@samsung.com>
References: <1275988020-29000-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1275988020-29000-5-git-send-email-kgene.kim@samsung.com>

From: Abhilash Kesavan <a.kesavan at samsung.com>

Following is added for the CF-ATA driver:
	- Platform data strucure instantiation
	- Platform device enabling code
	- Platform-specific gpio setup code

Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pc100/Kconfig                   |    7 ++
 arch/arm/mach-s5pc100/Makefile                  |    1 +
 arch/arm/mach-s5pc100/cpu.c                     |    2 +
 arch/arm/mach-s5pc100/include/mach/irqs.h       |    2 +-
 arch/arm/mach-s5pc100/include/mach/map.h        |    4 +
 arch/arm/mach-s5pc100/include/mach/regs-clock.h |    3 +
 arch/arm/mach-s5pc100/mach-smdkc100.c           |    7 ++
 arch/arm/mach-s5pc100/setup-ide.c               |   70 +++++++++++++++++++++++
 8 files changed, 95 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-s5pc100/setup-ide.c

diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b2a11df..34350ae 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -25,6 +25,11 @@ config S5PC100_SETUP_I2C1
 	help
 	  Common setup code for i2c bus 1.
 
+config S5PC100_SETUP_IDE
+	bool
+	help
+	  Common setup code for S5PC100 IDE GPIO configurations
+
 config S5PC100_SETUP_SDHCI
 	bool
 	select S5PC100_SETUP_SDHCI_GPIO
@@ -41,11 +46,13 @@ config MACH_SMDKC100
 	select CPU_S5PC100
 	select S3C_DEV_FB
 	select S3C_DEV_I2C1
+	select SAMSUNG_DEV_IDE
 	select S3C_DEV_HSMMC
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_HSMMC2
 	select S5PC100_SETUP_FB_24BPP
 	select S5PC100_SETUP_I2C1
+	select S5PC100_SETUP_IDE
 	select S5PC100_SETUP_SDHCI
 	help
 	  Machine support for the Samsung SMDKC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 543f3de..ab3ebe2 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_CPU_S5PC100)	+= dma.o
 
 obj-$(CONFIG_S5PC100_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
 obj-$(CONFIG_S5PC100_SETUP_I2C1)	+= setup-i2c1.o
+obj-$(CONFIG_S5PC100_SETUP_IDE)		+= setup-ide.o
 obj-$(CONFIG_S5PC100_SETUP_SDHCI)	+= setup-sdhci.o
 obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
 
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 7b5bdbc..5ce66de 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -38,6 +38,7 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
+#include <plat/ata-core.h>
 #include <plat/iic-core.h>
 #include <plat/sdhci.h>
 #include <plat/onenand-core.h>
@@ -92,6 +93,7 @@ void __init s5pc100_map_io(void)
 	s3c_i2c1_setname("s3c2440-i2c");
 
 	s3c_onenand_setname("s5pc100-onenand");
+	s3c_cfcon_setname("s5pc100-pata");
 }
 
 void __init s5pc100_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 28aa551..bfcc0b9 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -38,7 +38,7 @@
 #define IRQ_IEMIEC		S5P_IRQ_VIC1(6)
 #define IRQ_ONENAND		S5P_IRQ_VIC1(7)
 #define IRQ_NFC			S5P_IRQ_VIC1(8)
-#define IRQ_CFC			S5P_IRQ_VIC1(9)
+#define IRQ_CFCON		S5P_IRQ_VIC1(9)
 #define IRQ_UART0		S5P_IRQ_VIC1(10)
 #define IRQ_UART1		S5P_IRQ_VIC1(11)
 #define IRQ_UART2		S5P_IRQ_VIC1(12)
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index cadae43..aa25190 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -61,6 +61,8 @@
 
 #define S5PC100_PA_ONENAND	(0xE7100000)
 
+#define S5PC100_PA_CFCON	(0xE7800000)
+
 /* DMA */
 #define S5PC100_PA_MDMA		(0xE8100000)
 #define S5PC100_PA_PDMA0	(0xE9000000)
@@ -135,4 +137,6 @@
 #define S3C_PA_ONENAND_BUF	S5PC100_PA_ONENAND_BUF
 #define S3C_SZ_ONENAND_BUF	S5PC100_SZ_ONENAND_BUF
 
+#define SAMSUNG_PA_CFCON	S5PC100_PA_CFCON
+
 #endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
index 5d27d28..bc92da2 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
@@ -71,7 +71,10 @@
 #define S5P_CLKDIV1_PCLKD1_SHIFT	(16)
 
 #define S5PC100_SWRESET		S5PC100_REG_OTHERS(0x000)
+#define S5PC100_MEM_SYS_CFG	S5PC100_REG_OTHERS(0x200)
 
 #define S5PC100_SWRESET_RESETVAL	0xc100
 
+#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON	0x30
+
 #endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index af22f82..b97830a 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -42,6 +42,7 @@
 #include <plat/s5pc100.h>
 #include <plat/fb.h>
 #include <plat/iic.h>
+#include <plat/ata.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define S5PC100_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
@@ -149,7 +150,12 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
 	.setup_gpio	= s5pc100_fb_gpio_setup_24bpp,
 };
 
+static struct s3c_ide_platdata smdkc100_ide_pdata __initdata = {
+	.setup_gpio	= s5pc100_ide_setup_gpio,
+};
+
 static struct platform_device *smdkc100_devices[] __initdata = {
+	&s3c_device_cfcon,
 	&s3c_device_i2c0,
 	&s3c_device_i2c1,
 	&s3c_device_fb,
@@ -177,6 +183,7 @@ static void __init smdkc100_machine_init(void)
 	i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 
 	s3c_fb_set_platdata(&smdkc100_lcd_pdata);
+	s3c_ide_set_platdata(&smdkc100_ide_pdata);
 
 	/* LCD init */
 	gpio_request(S5PC100_GPD(0), "GPD");
diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c
new file mode 100644
index 0000000..8357567
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-ide.c
@@ -0,0 +1,70 @@
+/* linux/arch/arm/mach-s5pc100/setup-ide.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * S5PC100 setup information for IDE
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/io.h>
+
+#include <mach/regs-clock.h>
+#include <plat/gpio-cfg.h>
+
+void s5pc100_ide_setup_gpio(void)
+{
+	u32 reg;
+	u32 gpio = 0;
+
+	/* Independent CF interface, CF chip select configuration */
+	reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f);
+	writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG);
+
+	/* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
+	for (gpio = S5PC100_GPJ0(0); gpio <= S5PC100_GPJ0(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	/*CF_Data[0 - 7] */
+	for (gpio = S5PC100_GPJ2(0); gpio <= S5PC100_GPJ2(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	/* CF_Data[8 - 15] */
+	for (gpio = S5PC100_GPJ3(0); gpio <= S5PC100_GPJ3(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	/* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
+	for (gpio = S5PC100_GPJ4(0); gpio <= S5PC100_GPJ4(3); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	/* EBI_OE, EBI_WE */
+	for (gpio = S5PC100_GPK0(6); gpio <= S5PC100_GPK0(7); gpio++)
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0));
+
+	/* CF_OE, CF_WE */
+	for (gpio = S5PC100_GPK1(6); gpio <= S5PC100_GPK1(7); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* CF_CD */
+	s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S5PC100_GPK3(5), S3C_GPIO_PULL_NONE);
+}
-- 
1.6.2.5



From kgene.kim at samsung.com  Tue Jun  8 05:07:00 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue,  8 Jun 2010 18:07:00 +0900
Subject: [PATCH v2 5/5] ARM: S5PV210: Add support for Compact Flash driver on
	SMDKV210/C110
In-Reply-To: <1275988020-29000-1-git-send-email-kgene.kim@samsung.com>
References: <1275988020-29000-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1275988020-29000-6-git-send-email-kgene.kim@samsung.com>

From: Abhilash Kesavan <a.kesavan at samsung.com>

Following is added for the CF-ATA driver:
	- Platform data strucure instantiation
	- Platform device enabling code
	- Platform-specific gpio setup code
	- Fixed IRQ naming to match across 64xx and v210

Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pv210/Kconfig             |    9 +++++
 arch/arm/mach-s5pv210/Makefile            |    1 +
 arch/arm/mach-s5pv210/cpu.c               |    4 ++-
 arch/arm/mach-s5pv210/include/mach/irqs.h |    2 +-
 arch/arm/mach-s5pv210/include/mach/map.h  |    3 ++
 arch/arm/mach-s5pv210/mach-smdkc110.c     |    8 +++++
 arch/arm/mach-s5pv210/mach-smdkv210.c     |    8 +++++
 arch/arm/mach-s5pv210/setup-ide.c         |   50 +++++++++++++++++++++++++++++
 8 files changed, 83 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-s5pv210/setup-ide.c

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0761eac..4068c91 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -27,6 +27,11 @@ config S5PV210_SETUP_I2C2
 	help
 	  Common setup code for i2c bus 2.
 
+config S5PV210_SETUP_IDE
+	bool
+	help
+	  Common setup code for S5PV210 IDE GPIO configurations
+
 config S5PV210_SETUP_FB_24BPP
 	bool
 	help
@@ -72,9 +77,11 @@ config MACH_SMDKV210
 	select CPU_S5PV210
 	select ARCH_SPARSEMEM_ENABLE
 	select SAMSUNG_DEV_ADC
+	select SAMSUNG_DEV_IDE
 	select SAMSUNG_DEV_TS
 	select S3C_DEV_WDT
 	select HAVE_S3C2410_WATCHDOG
+	select S5PV210_SETUP_IDE
 	help
 	  Machine support for Samsung SMDKV210
 
@@ -82,8 +89,10 @@ config MACH_SMDKC110
 	bool "SMDKC110"
 	select CPU_S5PV210
 	select ARCH_SPARSEMEM_ENABLE
+	select SAMSUNG_DEV_IDE
 	select S3C_DEV_WDT
 	select HAVE_S3C2410_WATCHDOG
+	select S5PV210_SETUP_IDE
 	help
 	  Machine support for Samsung SMDKC110
 	  S5PC110(MCP) is one of package option of S5PV210
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 30be9a6..af55785 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o
 obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
 obj-$(CONFIG_S5PV210_SETUP_I2C1) 	+= setup-i2c1.o
 obj-$(CONFIG_S5PV210_SETUP_I2C2) 	+= setup-i2c2.o
+obj-$(CONFIG_S5PV210_SETUP_IDE)		+= setup-ide.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 411a4a9..8c4fdcd 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -32,6 +32,7 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
 #include <plat/s5pv210.h>
+#include <plat/ata-core.h>
 #include <plat/iic-core.h>
 #include <plat/sdhci.h>
 
@@ -79,7 +80,6 @@ void __init s5pv210_map_io(void)
 #ifdef CONFIG_S3C_DEV_ADC
 	s3c_device_adc.name	= "s3c64xx-adc";
 #endif
-
 	iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
 
 	/* initialise device information early */
@@ -87,6 +87,8 @@ void __init s5pv210_map_io(void)
 	s5pv210_default_sdhci1();
 	s5pv210_default_sdhci2();
 
+	s3c_cfcon_setname("s5pv210-pata");
+
 	/* the i2c devices are directly compatible with s3c2440 */
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 9689537..e1d3c45 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -45,7 +45,7 @@
 #define IRQ_IEMIEC		S5P_IRQ_VIC1(6)
 #define IRQ_ONENAND		S5P_IRQ_VIC1(7)
 #define IRQ_NFC			S5P_IRQ_VIC1(8)
-#define IRQ_CFC			S5P_IRQ_VIC1(9)
+#define IRQ_CFCON		S5P_IRQ_VIC1(9)
 #define IRQ_UART0		S5P_IRQ_VIC1(10)
 #define IRQ_UART1		S5P_IRQ_VIC1(11)
 #define IRQ_UART2		S5P_IRQ_VIC1(12)
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 34eb168..3846a0b 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -54,6 +54,8 @@
 
 #define S5PV210_PA_SROMC	(0xE8000000)
 
+#define S5PV210_PA_CFCON	(0xE8200000)
+
 #define S5PV210_PA_MDMA		0xFA200000
 #define S5PV210_PA_PDMA0	0xE0900000
 #define S5PV210_PA_PDMA1	0xE0A00000
@@ -104,5 +106,6 @@
 #define S3C_PA_WDT		S5PV210_PA_WATCHDOG
 
 #define SAMSUNG_PA_ADC		S5PV210_PA_ADC
+#define SAMSUNG_PA_CFCON	S5PV210_PA_CFCON
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 4c8903c..723e607 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -25,6 +25,7 @@
 #include <plat/s5pv210.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/ata.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
@@ -71,9 +72,14 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
 	},
 };
 
+static struct s3c_ide_platdata smdkv210_ide_pdata __initdata = {
+	.setup_gpio	= s5pv210_ide_setup_gpio,
+};
+
 static struct platform_device *smdkc110_devices[] __initdata = {
 	&s5pv210_device_iis0,
 	&s5pv210_device_ac97,
+	&s3c_device_cfcon,
 	&s3c_device_wdt,
 };
 
@@ -86,6 +92,8 @@ static void __init smdkc110_map_io(void)
 
 static void __init smdkc110_machine_init(void)
 {
+	s3c_ide_set_platdata(&smdkv210_ide_pdata);
+
 	platform_add_devices(smdkc110_devices, ARRAY_SIZE(smdkc110_devices));
 }
 
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 0d46279..cc902c1 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -27,6 +27,7 @@
 #include <plat/cpu.h>
 #include <plat/adc.h>
 #include <plat/ts.h>
+#include <plat/ata.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
@@ -73,10 +74,15 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
 	},
 };
 
+static struct s3c_ide_platdata smdkv210_ide_pdata __initdata = {
+	.setup_gpio	= s5pv210_ide_setup_gpio,
+};
+
 static struct platform_device *smdkv210_devices[] __initdata = {
 	&s5pv210_device_iis0,
 	&s5pv210_device_ac97,
 	&s3c_device_adc,
+	&s3c_device_cfcon,
 	&s3c_device_ts,
 	&s3c_device_wdt,
 };
@@ -97,6 +103,8 @@ static void __init smdkv210_map_io(void)
 static void __init smdkv210_machine_init(void)
 {
 	s3c24xx_ts_set_platdata(&s3c_ts_platform);
+	s3c_ide_set_platdata(&smdkv210_ide_pdata);
+
 	platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
 }
 
diff --git a/arch/arm/mach-s5pv210/setup-ide.c b/arch/arm/mach-s5pv210/setup-ide.c
new file mode 100644
index 0000000..b558b1c
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-ide.c
@@ -0,0 +1,50 @@
+/* linux/arch/arm/mach-s5pv210/setup-ide.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * S5PV210 setup information for IDE
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-cfg.h>
+
+void s5pv210_ide_setup_gpio(void)
+{
+	unsigned int gpio = 0;
+
+	for (gpio = S5PV210_GPJ0(0); gpio <= S5PV210_GPJ0(7); gpio++) {
+		/* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST,
+			CF_DMACK */
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	for (gpio = S5PV210_GPJ2(0); gpio <= S5PV210_GPJ2(7); gpio++) {
+		/*CF_Data[0 - 7] */
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	for (gpio = S5PV210_GPJ3(0); gpio <= S5PV210_GPJ3(7); gpio++) {
+		/* CF_Data[8 - 15] */
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+
+	for (gpio = S5PV210_GPJ4(0); gpio <= S5PV210_GPJ4(3); gpio++) {
+		/* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(4));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+		s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
+	}
+}
-- 
1.6.2.5



From kgene.kim at samsung.com  Tue Jun  8 05:06:57 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue,  8 Jun 2010 18:06:57 +0900
Subject: [PATCH v2 2/5] ARM: SAMSUNG: Add Compact Flash device support for
	Samsung SoCs
In-Reply-To: <1275988020-29000-1-git-send-email-kgene.kim@samsung.com>
References: <1275988020-29000-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1275988020-29000-3-git-send-email-kgene.kim@samsung.com>

From: Abhilash Kesavan <a.kesavan at samsung.com>

Following has been added:
	- Common CF Platform device definition
	- Platform data strucure definition
	- CF controller register definitions

Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/plat-samsung/Kconfig                 |    5 ++
 arch/arm/plat-samsung/Makefile                |    1 +
 arch/arm/plat-samsung/dev-ide.c               |   44 +++++++++++++++++++
 arch/arm/plat-samsung/include/plat/ata-core.h |   28 ++++++++++++
 arch/arm/plat-samsung/include/plat/ata.h      |   36 ++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h     |    1 +
 arch/arm/plat-samsung/include/plat/regs-ata.h |   56 +++++++++++++++++++++++++
 7 files changed, 171 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-samsung/dev-ide.c
 create mode 100644 arch/arm/plat-samsung/include/plat/ata-core.h
 create mode 100644 arch/arm/plat-samsung/include/plat/ata.h
 create mode 100644 arch/arm/plat-samsung/include/plat/regs-ata.h

diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 2753fb3..12c647c 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -216,6 +216,11 @@ config SAMSUNG_DEV_ADC
 	help
 	  Compile in platform device definition for ADC controller
 
+config SAMSUNG_DEV_IDE
+	bool
+	help
+	  Compile in platform device definitions for IDE
+
 config S3C64XX_DEV_SPI
 	bool
 	help
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 228c2ad..e7a9755 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_S3C_DEV_ONENAND)	+= dev-onenand.o
 obj-$(CONFIG_S3C_DEV_RTC)	+= dev-rtc.o
 
 obj-$(CONFIG_SAMSUNG_DEV_ADC)	+= dev-adc.o
+obj-$(CONFIG_SAMSUNG_DEV_IDE)	+= dev-ide.o
 obj-$(CONFIG_SAMSUNG_DEV_TS)	+= dev-ts.o
 
 # DMA support
diff --git a/arch/arm/plat-samsung/dev-ide.c b/arch/arm/plat-samsung/dev-ide.c
new file mode 100644
index 0000000..b497982
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-ide.c
@@ -0,0 +1,44 @@
+/* linux/arch/arm/plat-samsung/dev-ide.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung CF-ATA device definition.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+
+#include <mach/map.h>
+#include <plat/ata.h>
+#include <plat/devs.h>
+
+static struct resource s3c_cfcon_resource[] = {
+	[0] = {
+		.start	= SAMSUNG_PA_CFCON,
+		.end	= SAMSUNG_PA_CFCON + SZ_16K - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_CFCON,
+		.end	= IRQ_CFCON,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device s3c_device_cfcon = {
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(s3c_cfcon_resource),
+	.resource	= s3c_cfcon_resource,
+};
+
+void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
+{
+	s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
+			 &s3c_device_cfcon);
+}
diff --git a/arch/arm/plat-samsung/include/plat/ata-core.h b/arch/arm/plat-samsung/include/plat/ata-core.h
new file mode 100644
index 0000000..f5a4ec7
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/ata-core.h
@@ -0,0 +1,28 @@
+/* linux/arch/arm/plat-samsung/include/plat/ata-core.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung CF-ATA Controller core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_ATA_CORE_H
+#define __ASM_PLAT_ATA_CORE_H __FILE__
+
+/* These functions are only for use with the core support code, such as
+ * the cpu specific initialisation code
+*/
+
+/* re-define device name depending on support. */
+static inline void s3c_cfcon_setname(char *name)
+{
+#ifdef CONFIG_SAMSUNG_DEV_IDE
+	s3c_device_cfcon.name = name;
+#endif
+}
+
+#endif /* __ASM_PLAT_ATA_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/ata.h b/arch/arm/plat-samsung/include/plat/ata.h
new file mode 100644
index 0000000..2a3855a
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/ata.h
@@ -0,0 +1,36 @@
+/* linux/arch/arm/plat-samsung/include/plat/ata.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung CF-ATA platform_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_ATA_H
+#define __ASM_PLAT_ATA_H __FILE__
+
+/**
+ * struct s3c_ide_platdata - S3C IDE driver platform data.
+ * @setup_gpio: Setup the external GPIO pins to the right state for data
+ * transfer in true-ide mode.
+ */
+struct s3c_ide_platdata {
+	void (*setup_gpio)(void);
+};
+
+/*
+ * s3c_ide_set_platdata() - Setup the platform specifc data for IDE driver.
+ * @pdata: Platform data for IDE driver.
+ */
+extern void s3c_ide_set_platdata(struct s3c_ide_platdata *pdata);
+
+/* architecture-specific IDE configuration */
+extern void s3c64xx_ide_setup_gpio(void);
+extern void s5pc100_ide_setup_gpio(void);
+extern void s5pv210_ide_setup_gpio(void);
+
+#endif /*__ASM_PLAT_ATA_H */
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 6760999..4a66130 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -54,6 +54,7 @@ extern struct platform_device s3c_device_hwmon;
 extern struct platform_device s3c_device_hsmmc0;
 extern struct platform_device s3c_device_hsmmc1;
 extern struct platform_device s3c_device_hsmmc2;
+extern struct platform_device s3c_device_cfcon;
 
 extern struct platform_device s3c_device_spi0;
 extern struct platform_device s3c_device_spi1;
diff --git a/arch/arm/plat-samsung/include/plat/regs-ata.h b/arch/arm/plat-samsung/include/plat/regs-ata.h
new file mode 100644
index 0000000..f5df92f
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-ata.h
@@ -0,0 +1,56 @@
+/* linux/arch/arm/plat-samsung/include/plat/regs-ata.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Samsung CF-ATA register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_REGS_ATA_H
+#define __ASM_PLAT_REGS_ATA_H __FILE__
+
+#define S3C_CFATA_REG(x)	(x)
+
+#define S3C_CFATA_MUX		S3C_CFATA_REG(0x0)
+
+#define S3C_ATA_CTRL		S3C_CFATA_REG(0x0)
+#define S3C_ATA_STATUS		S3C_CFATA_REG(0x4)
+#define S3C_ATA_CMD		S3C_CFATA_REG(0x8)
+#define S3C_ATA_SWRST		S3C_CFATA_REG(0xc)
+#define S3C_ATA_IRQ		S3C_CFATA_REG(0x10)
+#define S3C_ATA_IRQ_MSK		S3C_CFATA_REG(0x14)
+#define S3C_ATA_CFG		S3C_CFATA_REG(0x18)
+
+#define S3C_ATA_MDMA_TIME	S3C_CFATA_REG(0x28)
+#define S3C_ATA_PIO_TIME	S3C_CFATA_REG(0x2c)
+#define S3C_ATA_UDMA_TIME	S3C_CFATA_REG(0x30)
+#define S3C_ATA_XFR_NUM		S3C_CFATA_REG(0x34)
+#define S3C_ATA_XFR_CNT		S3C_CFATA_REG(0x38)
+#define S3C_ATA_TBUF_START	S3C_CFATA_REG(0x3c)
+#define S3C_ATA_TBUF_SIZE	S3C_CFATA_REG(0x40)
+#define S3C_ATA_SBUF_START	S3C_CFATA_REG(0x44)
+#define S3C_ATA_SBUF_SIZE	S3C_CFATA_REG(0x48)
+#define S3C_ATA_CADR_TBUF	S3C_CFATA_REG(0x4c)
+#define S3C_ATA_CADR_SBUF	S3C_CFATA_REG(0x50)
+#define S3C_ATA_PIO_DTR		S3C_CFATA_REG(0x54)
+#define S3C_ATA_PIO_FED		S3C_CFATA_REG(0x58)
+#define S3C_ATA_PIO_SCR		S3C_CFATA_REG(0x5c)
+#define S3C_ATA_PIO_LLR		S3C_CFATA_REG(0x60)
+#define S3C_ATA_PIO_LMR		S3C_CFATA_REG(0x64)
+#define S3C_ATA_PIO_LHR		S3C_CFATA_REG(0x68)
+#define S3C_ATA_PIO_DVR		S3C_CFATA_REG(0x6c)
+#define S3C_ATA_PIO_CSD		S3C_CFATA_REG(0x70)
+#define S3C_ATA_PIO_DAD		S3C_CFATA_REG(0x74)
+#define S3C_ATA_PIO_READY	S3C_CFATA_REG(0x78)
+#define S3C_ATA_PIO_RDATA	S3C_CFATA_REG(0x7c)
+
+#define S3C_CFATA_MUX_TRUEIDE	0x01
+
+#define S3C_ATA_CFG_SWAP	0x40
+#define S3C_ATA_CFG_IORDYEN	0x02
+
+#endif /* __ASM_PLAT_REGS_ATA_H */
-- 
1.6.2.5



From kgene.kim at samsung.com  Tue Jun  8 05:06:56 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue,  8 Jun 2010 18:06:56 +0900
Subject: [PATCH v2 1/5] libata: pata_samsung: Add Samsung PATA controller
	driver
In-Reply-To: <1275988020-29000-1-git-send-email-kgene.kim@samsung.com>
References: <1275988020-29000-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1275988020-29000-2-git-send-email-kgene.kim@samsung.com>

From: Abhilash Kesavan <a.kesavan at samsung.com>

Adds support for the Samsung PATA controller. This driver is based on the
Libata subsystem and references the earlier patches sent for IDE subsystem.

Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 drivers/ata/Kconfig           |    9 +
 drivers/ata/Makefile          |    1 +
 drivers/ata/pata_samsung_cf.c |  608 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 618 insertions(+), 0 deletions(-)
 create mode 100644 drivers/ata/pata_samsung_cf.c

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index aa85a98..1b5facf 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -796,6 +796,15 @@ config PATA_RZ1000
 
 	  If unsure, say N.
 
+config PATA_SAMSUNG_CF
+	tristate "Samsung SoC PATA support"
+	depends on SAMSUNG_DEV_IDE
+	help
+	  This option enables basic support for Samsung's S3C/S5P board
+	  PATA controllers via the new ATA layer
+
+	  If unsure, say N.
+
 config PATA_WINBOND_VLB
 	tristate "Winbond W83759A VLB PATA support (Experimental)"
 	depends on ISA && EXPERIMENTAL
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 7ef89d7..9576776 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_PATA_OF_PLATFORM)	+= pata_of_platform.o
 obj-$(CONFIG_PATA_QDI)		+= pata_qdi.o
 obj-$(CONFIG_PATA_RB532)	+= pata_rb532_cf.o
 obj-$(CONFIG_PATA_RZ1000)	+= pata_rz1000.o
+obj-$(CONFIG_PATA_SAMSUNG_CF)	+= pata_samsung_cf.o
 obj-$(CONFIG_PATA_WINBOND_VLB)	+= pata_winbond.o
 
 # Should be last but two libata driver
diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
new file mode 100644
index 0000000..c1d845b
--- /dev/null
+++ b/drivers/ata/pata_samsung_cf.c
@@ -0,0 +1,608 @@
+/* linux/drivers/ata/pata_samsung_cf.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * PATA driver for Samsung SoCs.
+ * Supports CF Interface in True IDE mode. Currently only PIO mode has been
+ * implemented; UDMA support has to be added.
+ *
+ * Based on:
+ *	PATA driver for AT91SAM9260 Static Memory Controller
+ *	PATA driver for Toshiba SCC controller
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/libata.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <plat/ata.h>
+#include <plat/regs-ata.h>
+
+#define DRV_NAME "pata_samsung"
+#define DRV_VERSION "0.1"
+
+enum s3c_cpu_type {
+	TYPE_S3C64XX,
+	TYPE_S5PC100,
+	TYPE_S5PV210,
+};
+
+/*
+ * struct s3c_ide_info - S3C PATA instance.
+ * @clk: The clock resource for this controller.
+ * @ide_addr: The area mapped for the hardware registers.
+ * @sfr_addr: The area mapped for the special function registers.
+ * @irq: The IRQ number we are using.
+ * @cpu_type: The exact type of this controller.
+ * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
+ */
+struct s3c_ide_info {
+	struct clk *clk;
+	void __iomem *ide_addr;
+	void __iomem *sfr_addr;
+	unsigned int irq;
+	enum s3c_cpu_type cpu_type;
+	unsigned int fifo_status_reg;
+};
+
+static void pata_s3c_set_endian(void *s3c_ide_regbase, u8 mode)
+{
+	u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
+	reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
+	writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
+}
+
+static void pata_s3c_cfg_mode(void *s3c_ide_sfrbase)
+{
+	/* Select true-ide as the internal operating mode */
+	writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
+		s3c_ide_sfrbase + S3C_CFATA_MUX);
+}
+
+static unsigned long
+pata_s3c_setup_timing(struct s3c_ide_info *info, struct ata_device *adev)
+{
+	const struct ata_timing *timing;
+	int cycle_time;
+	int t1;
+	int t2;
+	int t2i;
+	ulong piotime;
+
+	cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
+
+	timing = ata_timing_find_mode(adev->pio_mode);
+	t1	= (timing->setup / cycle_time) & 0xf;
+	t2	= (timing->act8b / cycle_time) & 0xff;
+	t2i	= (timing->rec8b / cycle_time) & 0xff;
+
+	piotime = (t2i << 12) | (t2 << 4) | t1;
+
+	return piotime;
+}
+
+static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+	int mode = adev->pio_mode - XFER_PIO_0;
+	struct s3c_ide_info *info = ap->host->private_data;
+	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
+	ulong piotime;
+
+	/* Calculates timing parameters for PIO mode */
+	piotime = pata_s3c_setup_timing(info, adev);
+
+	/* Enables IORDY if mode requires it */
+	if (ata_pio_need_iordy(adev))
+		ata_cfg |= S3C_ATA_CFG_IORDYEN;
+	else
+		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
+
+	/* Host controller supports upto PIO4 only */
+	if (mode >= 0 && mode <= 4) {
+		writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
+		writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
+	}
+}
+
+/*
+ * Waits until the IDE controller is able to perform next read/write
+ * operation to the disk. Needed for 64XX series boards only.
+ */
+static int wait_for_host_ready(struct s3c_ide_info *info)
+{
+	ulong timeout;
+
+	/* wait for maximum of 20 msec */
+	timeout = jiffies + msecs_to_jiffies(20);
+	while (time_before(jiffies, timeout)) {
+		if ((readl(info->ide_addr + info->fifo_status_reg) >> 28) == 0)
+			return 0;
+	}
+	return -EBUSY;
+}
+
+/*
+ * Writes to one of the task file registers.
+ */
+static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
+{
+	struct s3c_ide_info *info = host->private_data;
+
+	wait_for_host_ready(info);
+	writeb(addr, reg);
+}
+
+/*
+ * Reads from one of the task file registers.
+ */
+static u8 ata_inb(struct ata_host *host, void __iomem *reg)
+{
+	struct s3c_ide_info *info = host->private_data;
+	u8 temp;
+
+	wait_for_host_ready(info);
+	temp = readb(reg);
+	wait_for_host_ready(info);
+	temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
+	return temp;
+}
+
+/*
+ * pata_s3c_tf_load - send taskfile registers to host controller
+ */
+static void pata_s3c_tf_load(struct ata_port *ap,
+				const struct ata_taskfile *tf)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
+
+	if (tf->ctl != ap->last_ctl) {
+		ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
+		ap->last_ctl = tf->ctl;
+		ata_wait_idle(ap);
+	}
+
+	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
+		ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
+		ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
+		ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
+		ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
+		ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
+	}
+
+	if (is_addr) {
+		ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
+		ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
+		ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
+		ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
+		ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
+	}
+
+	if (tf->flags & ATA_TFLAG_DEVICE)
+		ata_outb(ap->host, tf->device, ioaddr->device_addr);
+
+	ata_wait_idle(ap);
+}
+
+/*
+ * pata_s3c_tf_read - input device's ATA taskfile shadow registers
+ */
+static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+
+	tf->feature = ata_inb(ap->host, ioaddr->error_addr);
+	tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+	tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+	tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
+	tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
+	tf->device = ata_inb(ap->host, ioaddr->device_addr);
+
+	if (tf->flags & ATA_TFLAG_LBA48) {
+		iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
+		tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
+		tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+		tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+		tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
+		tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
+		iowrite8(tf->ctl, ioaddr->ctl_addr);
+		ap->last_ctl = tf->ctl;
+	}
+}
+
+/*
+ * pata_s3c_exec_command - issue ATA command to host controller
+ */
+static void pata_s3c_exec_command(struct ata_port *ap,
+				const struct ata_taskfile *tf)
+{
+	ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
+	ata_sff_pause(ap);
+}
+
+/*
+ * pata_s3c_check_status - Read device status register
+ */
+static u8 pata_s3c_check_status(struct ata_port *ap)
+{
+	return ata_inb(ap->host, ap->ioaddr.status_addr);
+}
+
+/*
+ * pata_s3c_check_altstatus - Read alternate device status register
+ */
+static u8 pata_s3c_check_altstatus(struct ata_port *ap)
+{
+	return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
+}
+
+/*
+ * pata_s3c_data_xfer - Transfer data by PIO
+ */
+unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char *buf,
+				unsigned int buflen, int rw)
+{
+	struct ata_port *ap = dev->link->ap;
+	struct s3c_ide_info *info = ap->host->private_data;
+	void __iomem *data_addr = ap->ioaddr.data_addr;
+	unsigned int words = buflen >> 1, i;
+	u16 *data_ptr = (u16 *)buf;
+
+	if (rw == READ)
+		for (i = 0; i < words; i++, data_ptr++) {
+			wait_for_host_ready(info);
+			*data_ptr = readw(data_addr);
+			wait_for_host_ready(info);
+			*data_ptr = readw(info->ide_addr
+					+ S3C_ATA_PIO_RDATA);
+		}
+	else
+		for (i = 0; i < words; i++, data_ptr++) {
+			wait_for_host_ready(info);
+			writel(*data_ptr, data_addr);
+		}
+
+	return words << 1;
+}
+
+/*
+ * pata_s3c_dev_select - Select device on ATA bus
+ */
+static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
+{
+	u8 tmp;
+
+	if (device == 0)
+		tmp = ATA_DEVICE_OBS;
+	else
+		tmp = ATA_DEVICE_OBS | ATA_DEV1;
+
+	ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
+	ata_sff_pause(ap);
+}
+
+/*
+ * pata_s3c_set_devctl - Write device control register
+ */
+static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
+{
+	ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
+}
+
+static struct scsi_host_template pata_s3c_sht = {
+	ATA_PIO_SHT(DRV_NAME),
+};
+
+static struct ata_port_operations pata_s3c_port_ops = {
+	.inherits		= &ata_sff_port_ops,
+	.sff_check_status	= pata_s3c_check_status,
+	.sff_check_altstatus    = pata_s3c_check_altstatus,
+	.sff_tf_load		= pata_s3c_tf_load,
+	.sff_tf_read		= pata_s3c_tf_read,
+	.sff_data_xfer		= pata_s3c_data_xfer,
+	.sff_exec_command	= pata_s3c_exec_command,
+	.sff_dev_select         = pata_s3c_dev_select,
+	.sff_set_devctl         = pata_s3c_set_devctl,
+	.set_piomode		= pata_s3c_set_piomode,
+};
+
+static struct ata_port_operations pata_s5p_port_ops = {
+	.inherits		= &ata_sff_port_ops,
+	.set_piomode		= pata_s3c_set_piomode,
+};
+
+static void pata_s3c_enable(void *s3c_ide_regbase, u8 state)
+{
+	u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
+	temp = state ? (temp | 1) : (temp & ~1);
+	writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
+}
+
+static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
+{
+	struct ata_host *host = dev_instance;
+	struct s3c_ide_info *info = host->private_data;
+	u32 reg;
+
+	reg = readl(info->ide_addr + S3C_ATA_IRQ);
+	writel(reg, info->ide_addr + S3C_ATA_IRQ);
+
+	return ata_sff_interrupt(irq, dev_instance);
+}
+
+static void pata_s3c_hwinit(struct s3c_ide_info *info,
+				struct s3c_ide_platdata *pdata)
+{
+	switch (info->cpu_type) {
+	case TYPE_S3C64XX:
+		/* Configure as big endian */
+		pata_s3c_cfg_mode(info->sfr_addr);
+		pata_s3c_set_endian(info->ide_addr, 1);
+		pata_s3c_enable(info->ide_addr, 1);
+		mdelay(100);
+
+		/* Remove IRQ Status */
+		writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
+		writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
+	break;
+
+	case TYPE_S5PC100:
+		pata_s3c_cfg_mode(info->sfr_addr);
+
+	case TYPE_S5PV210:
+		/* Configure as little endian */
+		pata_s3c_set_endian(info->ide_addr, 0);
+		pata_s3c_enable(info->ide_addr, 1);
+		mdelay(100);
+
+		/* Remove IRQ Status */
+		writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
+		writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
+	break;
+
+	default:
+		BUG();
+	}
+}
+
+static int __devinit pata_s3c_probe(struct platform_device *pdev)
+{
+	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
+	struct device *dev = &pdev->dev;
+	struct s3c_ide_info *info;
+	struct resource *res;
+	struct ata_port *ap;
+	struct ata_host *host;
+	enum s3c_cpu_type cpu_type;
+	int ret;
+
+	cpu_type = platform_get_device_id(pdev)->driver_data;
+
+	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
+	if (!info) {
+		dev_err(dev, "failed to allocate memory for device data\n");
+		return -ENOMEM;
+	}
+
+	info->irq = platform_get_irq(pdev, 0);
+	if (info->irq < 0) {
+		dev_err(dev, "could not obtain irq number\n");
+		ret = -EINVAL;
+		goto release_device_mem;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(dev, "failed to get mem resource\n");
+		ret = -EINVAL;
+		goto release_device_mem;
+	}
+
+	if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
+		dev_err(dev, "error requesting register region\n");
+		return -EBUSY;
+	}
+
+	info->ide_addr = devm_ioremap(dev, res->start, resource_size(res));
+	if (!info->ide_addr) {
+		dev_err(dev, "failed to map IO base address\n");
+		ret = -ENOMEM;
+		goto release_mem;
+	}
+
+	info->clk = clk_get(&pdev->dev, "cfcon");
+	if (IS_ERR(info->clk)) {
+		dev_err(dev, "failed to get access to cf controller clock\n");
+		ret = PTR_ERR(info->clk);
+		info->clk = NULL;
+	}
+
+	clk_enable(info->clk);
+
+	/* init ata host */
+	host = ata_host_alloc(dev, 1);
+	if (!host) {
+		dev_err(dev, "failed to allocate ide host\n");
+		ret = -ENOMEM;
+		goto stop_clk;
+	}
+
+	ap = host->ports[0];
+	ap->flags |= ATA_FLAG_MMIO;
+	ap->pio_mask = ATA_PIO4;
+
+	if (cpu_type == TYPE_S3C64XX) {
+		ap->ops = &pata_s3c_port_ops;
+		info->sfr_addr = info->ide_addr + 0x1800;
+		info->ide_addr += 0x1900;
+		info->fifo_status_reg = 0x94;
+	} else if (cpu_type == TYPE_S5PC100) {
+		ap->ops = &pata_s5p_port_ops;
+		info->sfr_addr = info->ide_addr + 0x1800;
+		info->ide_addr += 0x1900;
+		info->fifo_status_reg = 0x84;
+	} else {
+		ap->ops = &pata_s5p_port_ops;
+		info->fifo_status_reg = 0x84;
+	}
+
+	info->cpu_type = cpu_type;
+
+	if (!info->irq) {
+		ap->flags |= ATA_FLAG_PIO_POLLING;
+		ata_port_desc(ap, "no IRQ, using PIO polling\n");
+	}
+
+	ap->ioaddr.cmd_addr =  info->ide_addr + S3C_ATA_CMD;
+	ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
+	ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
+	ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
+	ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
+	ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
+	ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
+	ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
+	ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
+	ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
+	ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
+	ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
+	ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
+
+	ata_port_desc(ap, "mmio cmd 0x%llx ",
+			(unsigned long long)res->start);
+
+	host->private_data = info;
+
+	if (pdata && pdata->setup_gpio)
+		pdata->setup_gpio();
+
+	/* Set endianness and enable the interface */
+	pata_s3c_hwinit(info, pdata);
+
+	return ata_host_activate(host, info->irq,
+			info->irq ? pata_s3c_irq : NULL,
+			0, &pata_s3c_sht);
+
+	platform_set_drvdata(pdev, host);
+
+stop_clk:
+	clk_disable(info->clk);
+release_mem:
+	release_mem_region(res->start, resource_size(res));
+release_device_mem:
+	kfree(info);
+return ret;
+}
+
+static int __devexit pata_s3c_remove(struct platform_device *pdev)
+{
+	struct ata_host *host = platform_get_drvdata(pdev);
+	struct s3c_ide_info *info;
+	struct resource *res;
+
+	if (!host)
+		return 0;
+	info = host->private_data;
+
+	ata_host_detach(host);
+
+	clk_disable(info->clk);
+	clk_put(info->clk);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(res->start, resource_size(res));
+	kfree(info);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int pata_s3c_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ata_host *host = platform_get_drvdata(pdev);
+	pm_message_t state = PMSG_SUSPEND;
+
+	if (host)
+		return ata_host_suspend(host, state);
+	else
+		return 0;
+}
+
+static int pata_s3c_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ata_host *host = platform_get_drvdata(pdev);
+	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
+	struct s3c_ide_info *info;
+
+	info = host->private_data;
+
+	if (host) {
+		pata_s3c_hwinit(info, pdata);
+		ata_host_resume(host);
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops pata_s3c_pm_ops = {
+	.suspend	= pata_s3c_suspend,
+	.resume		= pata_s3c_resume,
+};
+#endif
+
+/* driver device registration */
+static struct platform_device_id pata_s3c_driver_ids[] = {
+	{
+		.name		= "s3c64xx-pata",
+		.driver_data	= TYPE_S3C64XX,
+	}, {
+		.name		= "s5pc100-pata",
+		.driver_data	= TYPE_S5PC100,
+	}, {
+		.name		= "s5pv210-pata",
+		.driver_data	= TYPE_S5PV210,
+	},
+	{ }
+};
+
+MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
+
+static struct platform_driver pata_s3c_driver = {
+	.probe		= pata_s3c_probe,
+	.remove		= __devexit_p(pata_s3c_remove),
+	.id_table	= pata_s3c_driver_ids,
+	.driver		= {
+		.name	= DRV_NAME,
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &pata_s3c_pm_ops,
+#endif
+	},
+};
+
+static int __init pata_s3c_init(void)
+{
+	return platform_driver_register(&pata_s3c_driver);
+}
+
+static void __exit pata_s3c_exit(void)
+{
+	platform_driver_unregister(&pata_s3c_driver);
+}
+
+module_init(pata_s3c_init);
+module_exit(pata_s3c_exit);
+
+MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan at samsung.com>");
+MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
-- 
1.6.2.5



From eric.y.miao at gmail.com  Tue Jun  8 05:13:40 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 8 Jun 2010 17:13:40 +0800
Subject: [RFC] pxa: about ac97 for public use
In-Reply-To: <AANLkTinVD25v8HyOHDPWjpev7yp_tFqy_8S8Wa5njgYs@mail.gmail.com>
References: <AANLkTinVD25v8HyOHDPWjpev7yp_tFqy_8S8Wa5njgYs@mail.gmail.com>
Message-ID: <AANLkTik-JOU5UFRR44Iw74QH9iXyafJ7kiZ4QzChkDPR@mail.gmail.com>

On Tue, Jun 8, 2010 at 4:58 PM, Wan ZongShun <mcuos.com at gmail.com> wrote:
> Hi Eric,
>
> Now, our pxa168 ac97 driver need the regs-ac97.h file support, but
> this file was located in mach-pxa/include.
> Should we move the public 'regs-ac97.h' to plat-pxa/ or create a new
> one in mach-mmp/include for pxa168 ac97 driver?

I'd rather to remove that file completely, to keep the register definitions
private to the relevant driver _only_.


From ryan at bluewatersys.com  Tue Jun  8 06:01:09 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Tue,  8 Jun 2010 22:01:09 +1200
Subject: [PATCH 0/3] EP93xx: Add i2s audio support
Message-ID: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>

Repost of the i2s audio series for ep93xx. Patch 2/3 is unchanged. The
core support has been modified to move setting of the SPOL and ORIDE
bits of the i2sclkdiv register, as well as the i2s pin strapping
configuration, to a new function called ep93xx_i2s_acquire which is
called from the audio board drivers.

Ryan Mallon (3):
  EP93xx: Add i2s core support
  EP93xx: Add i2s audio driver
  EP93xx: Add Snapper CL15 i2s audio support

 arch/arm/mach-ep93xx/clock.c                    |   67 +++-
 arch/arm/mach-ep93xx/core.c                     |   67 +++
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |   10 +
 arch/arm/mach-ep93xx/include/mach/platform.h    |    3 +
 arch/arm/mach-ep93xx/snappercl15.c              |    1 +
 sound/soc/Kconfig                               |    1 +
 sound/soc/Makefile                              |    1 +
 sound/soc/ep93xx/Kconfig                        |   18 +
 sound/soc/ep93xx/Makefile                       |   11 +
 sound/soc/ep93xx/ep93xx-i2s.c                   |  487 +++++++++++++++++++++++
 sound/soc/ep93xx/ep93xx-i2s.h                   |   18 +
 sound/soc/ep93xx/ep93xx-pcm.c                   |  319 +++++++++++++++
 sound/soc/ep93xx/ep93xx-pcm.h                   |   22 +
 sound/soc/ep93xx/snappercl15.c                  |  150 +++++++
 14 files changed, 1174 insertions(+), 1 deletions(-)
 create mode 100644 sound/soc/ep93xx/Kconfig
 create mode 100644 sound/soc/ep93xx/Makefile
 create mode 100644 sound/soc/ep93xx/ep93xx-i2s.c
 create mode 100644 sound/soc/ep93xx/ep93xx-i2s.h
 create mode 100644 sound/soc/ep93xx/ep93xx-pcm.c
 create mode 100644 sound/soc/ep93xx/ep93xx-pcm.h
 create mode 100644 sound/soc/ep93xx/snappercl15.c



From ryan at bluewatersys.com  Tue Jun  8 06:01:10 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Tue,  8 Jun 2010 22:01:10 +1200
Subject: [PATCH 1/3] EP93xx: Add i2s core support
In-Reply-To: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1275991272-30122-2-git-send-email-ryan@bluewatersys.com>

Add core support for EP93xx i2s audio

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-ep93xx/clock.c                    |   67 ++++++++++++++++++++++-
 arch/arm/mach-ep93xx/core.c                     |   67 +++++++++++++++++++++++
 arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h |   10 ++++
 arch/arm/mach-ep93xx/include/mach/platform.h    |    3 +
 4 files changed, 146 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 5f80092..e782af1 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -43,7 +43,8 @@ static unsigned long get_uart_rate(struct clk *clk);
 
 static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
 static int set_div_rate(struct clk *clk, unsigned long rate);
-
+static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate);
+static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate);
 
 static struct clk clk_xtali = {
 	.rate		= EP93XX_EXT_CLK_RATE,
@@ -108,6 +109,29 @@ static struct clk clk_video = {
 	.set_rate	= set_div_rate,
 };
 
+static struct clk clk_i2s_mclk = {
+	.sw_locked	= 1,
+	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
+	.enable_mask	= EP93XX_SYSCON_CLKDIV_ENABLE,
+	.set_rate	= set_div_rate,
+};
+
+static struct clk clk_i2s_sclk = {
+	.sw_locked	= 1,
+	.parent		= &clk_i2s_mclk,
+	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
+	.enable_mask	= EP93XX_SYSCON_I2SCLKDIV_SENA,
+	.set_rate	= set_i2s_sclk_rate,
+};
+
+static struct clk clk_i2s_lrclk = {
+	.sw_locked	= 1,
+	.parent		= &clk_i2s_sclk,
+	.enable_reg	= EP93XX_SYSCON_I2SCLKDIV,
+	.enable_mask	= EP93XX_SYSCON_I2SCLKDIV_SENA,
+	.set_rate	= set_i2s_lrclk_rate,
+};
+
 /* DMA Clocks */
 static struct clk clk_m2p0 = {
 	.parent		= &clk_h,
@@ -186,6 +210,9 @@ static struct clk_lookup clocks[] = {
 	INIT_CK("ep93xx-ohci",		NULL,		&clk_usb_host),
 	INIT_CK("ep93xx-keypad",	NULL,		&clk_keypad),
 	INIT_CK("ep93xx-fb",		NULL,		&clk_video),
+	INIT_CK("ep93xx-i2s",		"mclk",		&clk_i2s_mclk),
+	INIT_CK("ep93xx-i2s",		"sclk",		&clk_i2s_sclk),
+	INIT_CK("ep93xx-i2s",		"lrclk",	&clk_i2s_lrclk),
 	INIT_CK(NULL,			"pwm_clk",	&clk_pwm),
 	INIT_CK(NULL,			"m2p0",		&clk_m2p0),
 	INIT_CK(NULL,			"m2p1",		&clk_m2p1),
@@ -396,6 +423,44 @@ static int set_div_rate(struct clk *clk, unsigned long rate)
 	return 0;
 }
 
+static int set_i2s_sclk_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned val = __raw_readl(clk->enable_reg);
+
+	if (rate == clk_i2s_mclk.rate / 2)
+		ep93xx_syscon_swlocked_write(val & ~EP93XX_I2SCLKDIV_SDIV, 
+					     clk->enable_reg);
+	else if (rate == clk_i2s_mclk.rate / 4)
+		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_SDIV, 
+					     clk->enable_reg);
+	else
+		return -EINVAL;
+
+	clk_i2s_sclk.rate = rate;
+	return 0;
+}
+
+static int set_i2s_lrclk_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned val = __raw_readl(clk->enable_reg) & 
+		~EP93XX_I2SCLKDIV_LRDIV_MASK;
+	
+	if (rate == clk_i2s_sclk.rate / 32)
+		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV32,
+					     clk->enable_reg);
+	else if (rate == clk_i2s_sclk.rate / 64)
+		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV64,
+					     clk->enable_reg);
+	else if (rate == clk_i2s_sclk.rate / 128)
+		ep93xx_syscon_swlocked_write(val | EP93XX_I2SCLKDIV_LRDIV128,
+					     clk->enable_reg);
+	else
+		return -EINVAL;
+
+	clk_i2s_lrclk.rate = rate;
+	return 0;
+}
+
 int clk_set_rate(struct clk *clk, unsigned long rate)
 {
 	if (clk->set_rate)
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 90fb591..005af0f 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -617,6 +617,73 @@ void ep93xx_keypad_release_gpio(struct platform_device *pdev)
 }
 EXPORT_SYMBOL(ep93xx_keypad_release_gpio);
 
+/*************************************************************************
+ * EP93xx I2S audio peripheral handling
+ *************************************************************************/
+static struct resource ep93xx_i2s_resource[] = {
+	{
+		.start	= EP93XX_I2S_PHYS_BASE,
+		.end	= EP93XX_I2S_PHYS_BASE + 0x100 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device ep93xx_i2s_device = {
+	.name		= "ep93xx-i2s",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(ep93xx_i2s_resource),
+	.resource	= ep93xx_i2s_resource,
+};
+
+void __init ep93xx_register_i2s(void)
+{
+	platform_device_register(&ep93xx_i2s_device);
+}
+
+#define EP93XX_SYSCON_DEVCFG_I2S_MASK	(EP93XX_SYSCON_DEVCFG_I2SONSSP | \
+					 EP93XX_SYSCON_DEVCFG_I2SONAC97)
+
+#define EP93XX_I2SCLKDIV_MASK		(EP93XX_SYSCON_I2SCLKDIV_ORIDE | \
+					 EP93XX_SYSCON_I2SCLKDIV_SPOL)
+
+int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config)
+{
+	unsigned val;
+
+	/* Sanity check */
+	if (i2s_pins & ~EP93XX_SYSCON_DEVCFG_I2S_MASK)
+		return -EINVAL;
+	if (i2s_config & ~EP93XX_I2SCLKDIV_MASK)
+		return -EINVAL;
+
+	/* Must have only one of I2SONSSP/I2SONAC97 set */
+	if ((i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONSSP) ==
+	    (i2s_pins & EP93XX_SYSCON_DEVCFG_I2SONAC97))
+		return -EINVAL;
+
+	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
+	ep93xx_devcfg_set_bits(i2s_pins);
+
+	/*
+	 * This is potentially racy with the clock api for i2s_mclk, sclk and 
+	 * lrclk. Since the i2s driver is the only user of those clocks we
+	 * rely on it to prevent parallel use of this function and the 
+	 * clock api for the i2s clocks.
+	 */
+	val = __raw_readl(EP93XX_SYSCON_I2SCLKDIV);
+	val &= ~EP93XX_I2SCLKDIV_MASK;
+	val |= i2s_config;
+	ep93xx_syscon_swlocked_write(val, EP93XX_SYSCON_I2SCLKDIV);
+
+	return 0;
+}
+EXPORT_SYMBOL(ep93xx_i2s_acquire);
+
+void ep93xx_i2s_release(void)
+{
+	ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_I2S_MASK);
+}
+EXPORT_SYMBOL(ep93xx_i2s_release);
 
 extern void ep93xx_gpio_init(void);
 
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 93e2ecc..3fbb095 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -93,6 +93,7 @@
 /* APB peripherals */
 #define EP93XX_TIMER_BASE		EP93XX_APB_IOMEM(0x00010000)
 
+#define EP93XX_I2S_PHYS_BASE		EP93XX_APB_PHYS(0x00020000)
 #define EP93XX_I2S_BASE			EP93XX_APB_IOMEM(0x00020000)
 
 #define EP93XX_SECURITY_BASE		EP93XX_APB_IOMEM(0x00030000)
@@ -193,6 +194,15 @@
 #define EP93XX_SYSCON_CLKDIV_ESEL	(1<<14)
 #define EP93XX_SYSCON_CLKDIV_PSEL	(1<<13)
 #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT	8
+#define EP93XX_SYSCON_I2SCLKDIV		EP93XX_SYSCON_REG(0x8c)
+#define EP93XX_SYSCON_I2SCLKDIV_SENA	(1<<31)
+#define EP93XX_SYSCON_I2SCLKDIV_ORIDE   (1<<29)
+#define EP93XX_SYSCON_I2SCLKDIV_SPOL	(1<<19)
+#define EP93XX_I2SCLKDIV_SDIV		(1 << 16)
+#define EP93XX_I2SCLKDIV_LRDIV32	(0 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV64	(1 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV128 	(2 << 17)
+#define EP93XX_I2SCLKDIV_LRDIV_MASK 	(3 << 17)
 #define EP93XX_SYSCON_KEYTCHCLKDIV	EP93XX_SYSCON_REG(0x90)
 #define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN	(1<<31)
 #define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV	(1<<16)
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index c6dc14d..0f2822d 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -43,6 +43,9 @@ void ep93xx_pwm_release_gpio(struct platform_device *pdev);
 void ep93xx_register_keypad(struct ep93xx_keypad_platform_data *data);
 int ep93xx_keypad_acquire_gpio(struct platform_device *pdev);
 void ep93xx_keypad_release_gpio(struct platform_device *pdev);
+void ep93xx_register_i2s(void);
+int ep93xx_i2s_acquire(unsigned i2s_pins, unsigned i2s_config);
+void ep93xx_i2s_release(void);
 
 void ep93xx_init_devices(void);
 extern struct sys_timer ep93xx_timer;
-- 
1.6.0.4



From ryan at bluewatersys.com  Tue Jun  8 06:01:11 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Tue,  8 Jun 2010 22:01:11 +1200
Subject: [PATCH 2/3] EP93xx: Add i2s audio driver
In-Reply-To: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1275991272-30122-3-git-send-email-ryan@bluewatersys.com>

Add pcm and i2s SoC audio drivers for EP93xx

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 sound/soc/Kconfig             |    1 +
 sound/soc/Makefile            |    1 +
 sound/soc/ep93xx/Kconfig      |    9 +
 sound/soc/ep93xx/Makefile     |    8 +
 sound/soc/ep93xx/ep93xx-i2s.c |  487 +++++++++++++++++++++++++++++++++++++++++
 sound/soc/ep93xx/ep93xx-i2s.h |   18 ++
 sound/soc/ep93xx/ep93xx-pcm.c |  319 +++++++++++++++++++++++++++
 sound/soc/ep93xx/ep93xx-pcm.h |   22 ++
 8 files changed, 865 insertions(+), 0 deletions(-)
 create mode 100644 sound/soc/ep93xx/Kconfig
 create mode 100644 sound/soc/ep93xx/Makefile
 create mode 100644 sound/soc/ep93xx/ep93xx-i2s.c
 create mode 100644 sound/soc/ep93xx/ep93xx-i2s.h
 create mode 100644 sound/soc/ep93xx/ep93xx-pcm.c
 create mode 100644 sound/soc/ep93xx/ep93xx-pcm.h

diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
index b1749bc..f7cb451 100644
--- a/sound/soc/Kconfig
+++ b/sound/soc/Kconfig
@@ -28,6 +28,7 @@ source "sound/soc/atmel/Kconfig"
 source "sound/soc/au1x/Kconfig"
 source "sound/soc/blackfin/Kconfig"
 source "sound/soc/davinci/Kconfig"
+source "sound/soc/ep93xx/Kconfig"
 source "sound/soc/fsl/Kconfig"
 source "sound/soc/imx/Kconfig"
 source "sound/soc/omap/Kconfig"
diff --git a/sound/soc/Makefile b/sound/soc/Makefile
index 1470141..55b711a 100644
--- a/sound/soc/Makefile
+++ b/sound/soc/Makefile
@@ -6,6 +6,7 @@ obj-$(CONFIG_SND_SOC)	+= atmel/
 obj-$(CONFIG_SND_SOC)	+= au1x/
 obj-$(CONFIG_SND_SOC)	+= blackfin/
 obj-$(CONFIG_SND_SOC)	+= davinci/
+obj-$(CONFIG_SND_SOC)	+= ep93xx/
 obj-$(CONFIG_SND_SOC)	+= fsl/
 obj-$(CONFIG_SND_SOC)   += imx/
 obj-$(CONFIG_SND_SOC)	+= omap/
diff --git a/sound/soc/ep93xx/Kconfig b/sound/soc/ep93xx/Kconfig
new file mode 100644
index 0000000..ba66ac8
--- /dev/null
+++ b/sound/soc/ep93xx/Kconfig
@@ -0,0 +1,9 @@
+config SND_EP93XX_SOC
+	tristate "SoC Audio support for the Cirrus Logic EP93xx series"
+	depends on ARCH_EP93XX && SND_SOC
+	help
+	  Say Y or M if you want to add support for codecs attached to
+	  the EP93xx I2S interface.
+
+config SND_EP93XX_SOC_I2S
+	tristate
diff --git a/sound/soc/ep93xx/Makefile b/sound/soc/ep93xx/Makefile
new file mode 100644
index 0000000..0239da3
--- /dev/null
+++ b/sound/soc/ep93xx/Makefile
@@ -0,0 +1,8 @@
+# EP93xx Platform Support
+snd-soc-ep93xx-objs				:= ep93xx-pcm.o
+snd-soc-ep93xx-i2s-objs	 			:= ep93xx-i2s.o
+
+obj-$(CONFIG_SND_EP93XX_SOC)			+= snd-soc-ep93xx.o
+obj-$(CONFIG_SND_EP93XX_SOC_I2S)		+= snd-soc-ep93xx-i2s.o
+
+# EP93XX Machine Support
diff --git a/sound/soc/ep93xx/ep93xx-i2s.c b/sound/soc/ep93xx/ep93xx-i2s.c
new file mode 100644
index 0000000..00b9466
--- /dev/null
+++ b/sound/soc/ep93xx/ep93xx-i2s.c
@@ -0,0 +1,487 @@
+/*
+ * linux/sound/soc/ep93xx-i2s.c
+ * EP93xx I2S driver
+ *
+ * Copyright (C) 2010 Ryan Mallon <ryan at bluewatersys.com>
+ *
+ * Based on the original driver by:
+ *   Copyright (C) 2007 Chase Douglas <chasedouglas at gmail>
+ *   Copyright (C) 2006 Lennert Buytenhek <buytenh at wantstofly.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/initval.h>
+#include <sound/soc.h>
+
+#include <mach/hardware.h>
+#include <mach/ep93xx-regs.h>
+#include <mach/dma.h>
+
+#include "ep93xx-pcm.h"
+#include "ep93xx-i2s.h"
+
+#define EP93XX_I2S_TXCLKCFG		0x00
+#define EP93XX_I2S_RXCLKCFG		0x04
+#define EP93XX_I2S_GLCTRL		0x0C
+
+#define EP93XX_I2S_TXLINCTRLDATA	0x28
+#define EP93XX_I2S_TXCTRL		0x2C
+#define EP93XX_I2S_TXWRDLEN		0x30
+#define EP93XX_I2S_TX0EN		0x34
+
+#define EP93XX_I2S_RXLINCTRLDATA	0x58
+#define EP93XX_I2S_RXCTRL		0x5C
+#define EP93XX_I2S_RXWRDLEN		0x60
+#define EP93XX_I2S_RX0EN		0x64
+
+#define EP93XX_I2S_WRDLEN_16		(0 << 0)
+#define EP93XX_I2S_WRDLEN_24		(1 << 0)
+#define EP93XX_I2S_WRDLEN_32		(2 << 0)
+
+#define EP93XX_I2S_LINCTRLDATA_R_JUST	(1 << 2) /* Right justify */
+
+#define EP93XX_I2S_CLKCFG_LRS		(1 << 0) /* lrclk polarity */
+#define EP93XX_I2S_CLKCFG_CKP		(1 << 1) /* Bit clock polarity */
+#define EP93XX_I2S_CLKCFG_REL		(1 << 2) /* First bit transition */
+#define EP93XX_I2S_CLKCFG_MASTER	(1 << 3) /* Master mode */
+#define EP93XX_I2S_CLKCFG_NBCG		(1 << 4) /* Not bit clock gating */
+
+struct ep93xx_i2s_info {
+	struct clk			*mclk;
+	struct clk			*sclk;
+	struct clk			*lrclk;
+	struct ep93xx_pcm_dma_params	*dma_params;
+	struct resource			*mem;
+	void __iomem			*regs;
+};
+
+struct ep93xx_pcm_dma_params ep93xx_i2s_dma_params[] = {
+	[SNDRV_PCM_STREAM_PLAYBACK] = {
+		.name		= "i2s-pcm-out",
+		.dma_port	= EP93XX_DMA_M2P_PORT_I2S1,
+	},
+	[SNDRV_PCM_STREAM_CAPTURE] = {
+		.name		= "i2s-pcm-in",
+		.dma_port	= EP93XX_DMA_M2P_PORT_I2S1,
+	},
+};
+
+static inline void ep93xx_i2s_write_reg(struct ep93xx_i2s_info *info,
+					unsigned reg, unsigned val)
+{
+	__raw_writel(val, info->regs + reg);
+}
+
+static inline unsigned ep93xx_i2s_read_reg(struct ep93xx_i2s_info *info,
+					   unsigned reg)
+{
+	return __raw_readl(info->regs + reg);
+}
+
+static void ep93xx_i2s_enable(struct ep93xx_i2s_info *info, int stream)
+{
+	unsigned base_reg;
+	int i;
+
+	if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
+	    (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
+		/* Enable clocks */
+		clk_enable(info->mclk);
+		clk_enable(info->sclk);
+		clk_enable(info->lrclk);
+
+		/* Enable i2s */
+		ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 1);
+	}
+
+	/* Enable fifos */
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+		base_reg = EP93XX_I2S_TX0EN;
+	else
+		base_reg = EP93XX_I2S_RX0EN;
+	for (i = 0; i < 3; i++)
+		ep93xx_i2s_write_reg(info, base_reg + (i * 4), 1);
+}
+
+static void ep93xx_i2s_disable(struct ep93xx_i2s_info *info, int stream)
+{
+	unsigned base_reg;
+	int i;
+
+	/* Disable fifos */
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
+		base_reg = EP93XX_I2S_TX0EN;
+	else
+		base_reg = EP93XX_I2S_RX0EN;
+	for (i = 0; i < 3; i++)
+		ep93xx_i2s_write_reg(info, base_reg + (i * 4), 0);
+
+	if ((ep93xx_i2s_read_reg(info, EP93XX_I2S_TX0EN) & 0x1) == 0 &&
+	    (ep93xx_i2s_read_reg(info, EP93XX_I2S_RX0EN) & 0x1) == 0) {
+		/* Disable i2s */
+		ep93xx_i2s_write_reg(info, EP93XX_I2S_GLCTRL, 0);
+
+		/* Disable clocks */
+		clk_disable(info->lrclk);
+		clk_disable(info->sclk);
+		clk_disable(info->mclk);
+	}
+}
+
+static int ep93xx_i2s_startup(struct snd_pcm_substream *substream,
+			      struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct ep93xx_i2s_info *info = rtd->dai->cpu_dai->private_data;
+
+	snd_soc_dai_set_dma_data(cpu_dai, substream,
+				 &info->dma_params[substream->stream]);
+	return 0;
+}
+
+static void ep93xx_i2s_shutdown(struct snd_pcm_substream *substream,
+				struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct ep93xx_i2s_info *info = rtd->dai->cpu_dai->private_data;
+
+	ep93xx_i2s_disable(info, substream->stream);
+}
+
+static int ep93xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
+				  unsigned int fmt)
+{
+	struct ep93xx_i2s_info *info = cpu_dai->private_data;
+	unsigned int clk_cfg, lin_ctrl;
+
+	clk_cfg  = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXCLKCFG);
+	lin_ctrl = ep93xx_i2s_read_reg(info, EP93XX_I2S_RXLINCTRLDATA);
+
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_I2S:
+		clk_cfg |= EP93XX_I2S_CLKCFG_REL;
+		lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
+		break;
+
+	case SND_SOC_DAIFMT_LEFT_J:
+		clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
+		lin_ctrl &= ~EP93XX_I2S_LINCTRLDATA_R_JUST;
+		break;
+
+	case SND_SOC_DAIFMT_RIGHT_J:
+		clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
+		lin_ctrl |= EP93XX_I2S_LINCTRLDATA_R_JUST;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBS_CFS:
+		/* CPU is master */
+		clk_cfg |= EP93XX_I2S_CLKCFG_MASTER;
+		break;
+
+	case SND_SOC_DAIFMT_CBM_CFM:
+		/* Codec is master */
+		clk_cfg &= ~EP93XX_I2S_CLKCFG_MASTER;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+	case SND_SOC_DAIFMT_NB_NF:
+		/* Negative bit clock, lrclk low on left word */
+		clk_cfg &= ~(EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL);
+		break;
+
+	case SND_SOC_DAIFMT_NB_IF:
+		/* Negative bit clock, lrclk low on right word */
+		clk_cfg &= ~EP93XX_I2S_CLKCFG_CKP;
+		clk_cfg |= EP93XX_I2S_CLKCFG_REL;
+		break;
+
+	case SND_SOC_DAIFMT_IB_NF:
+		/* Positive bit clock, lrclk low on left word */
+		clk_cfg |= EP93XX_I2S_CLKCFG_CKP;
+		clk_cfg &= ~EP93XX_I2S_CLKCFG_REL;
+		break;
+
+	case SND_SOC_DAIFMT_IB_IF:
+		/* Positive bit clock, lrclk low on right word */
+		clk_cfg |= EP93XX_I2S_CLKCFG_CKP | EP93XX_I2S_CLKCFG_REL;
+		break;
+	}
+
+	/* Write new register values */
+	ep93xx_i2s_write_reg(info, EP93XX_I2S_RXCLKCFG, clk_cfg);
+	ep93xx_i2s_write_reg(info, EP93XX_I2S_TXCLKCFG, clk_cfg);
+	ep93xx_i2s_write_reg(info, EP93XX_I2S_RXLINCTRLDATA, lin_ctrl);
+	ep93xx_i2s_write_reg(info, EP93XX_I2S_TXLINCTRLDATA, lin_ctrl);
+	return 0;
+}
+
+static int ep93xx_i2s_hw_params(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params,
+				struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	struct ep93xx_i2s_info *info = cpu_dai->private_data;
+	unsigned word_len, div, sdiv, lrdiv;
+	int found = 0, err;
+
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+		word_len = EP93XX_I2S_WRDLEN_16;
+		break;
+
+	case SNDRV_PCM_FORMAT_S24_LE:
+		word_len = EP93XX_I2S_WRDLEN_24;
+		break;
+
+	case SNDRV_PCM_FORMAT_S32_LE:
+		word_len = EP93XX_I2S_WRDLEN_32;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+		ep93xx_i2s_write_reg(info, EP93XX_I2S_TXWRDLEN, word_len);
+	else
+		ep93xx_i2s_write_reg(info, EP93XX_I2S_RXWRDLEN, word_len);
+
+	/*
+	 * Calculate the sdiv (bit clock) and lrdiv (left/right clock) values.
+	 * If the lrclk is pulse length is larger than the word size, then the
+	 * bit clock will be gated for the unused bits.
+	 */
+	div = (clk_get_rate(info->mclk) / params_rate(params)) *
+		params_channels(params);
+	for (sdiv = 2; sdiv <= 4; sdiv += 2)
+		for (lrdiv = 32; lrdiv <= 128; lrdiv <<= 1)
+			if (sdiv * lrdiv == div) {
+				found = 1;
+				goto out;
+			}
+out:
+	if (!found)
+		return -EINVAL;
+
+	err = clk_set_rate(info->sclk, clk_get_rate(info->mclk) / sdiv);
+	if (err)
+		return err;
+
+	err = clk_set_rate(info->lrclk, clk_get_rate(info->sclk) / lrdiv);
+	if (err)
+		return err;
+
+	ep93xx_i2s_enable(info, substream->stream);
+	return 0;
+}
+
+static int ep93xx_i2s_set_sysclk(struct snd_soc_dai *cpu_dai, int clk_id,
+				 unsigned int freq, int dir)
+{
+	struct ep93xx_i2s_info *info = cpu_dai->private_data;
+
+	if (dir == SND_SOC_CLOCK_IN || clk_id != 0)
+		return -EINVAL;
+
+	return clk_set_rate(info->mclk, freq);
+}
+
+#ifdef CONFIG_PM
+static int ep93xx_i2s_suspend(struct snd_soc_dai *dai)
+{
+	struct ep93xx_i2s_info *info = dai->private_data;
+
+	if (!dai->active)
+		return;
+
+	ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_PLAYBACK);
+	ep93xx_i2s_disable(info, SNDRV_PCM_STREAM_CAPTURE);
+}
+
+static int ep93xx_i2s_resume(struct snd_soc_dai *dai)
+{
+	struct ep93xx_i2s_info *info = dai->private_data;
+
+	if (!dai->active)
+		return;
+
+	ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_PLAYBACK);
+	ep93xx_i2s_enable(info, SNDRV_PCM_STREAM_CAPTURE);
+}
+#else
+#define ep93xx_i2s_suspend	NULL
+#define ep93xx_i2s_resume	NULL
+#endif
+
+static struct snd_soc_dai_ops ep93xx_i2s_dai_ops = {
+	.startup	= ep93xx_i2s_startup,
+	.shutdown	= ep93xx_i2s_shutdown,
+	.hw_params	= ep93xx_i2s_hw_params,
+	.set_sysclk	= ep93xx_i2s_set_sysclk,
+	.set_fmt	= ep93xx_i2s_set_dai_fmt,
+};
+
+#define EP93XX_I2S_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+			    SNDRV_PCM_FMTBIT_S24_LE | \
+			    SNDRV_PCM_FMTBIT_S32_LE)
+
+struct snd_soc_dai ep93xx_i2s_dai = {
+	.name		= "ep93xx-i2s",
+	.id		= 0,
+	.symmetric_rates= 1,
+	.suspend	= ep93xx_i2s_suspend,
+	.resume		= ep93xx_i2s_resume,
+	.playback	= {
+		.channels_min	= 2,
+		.channels_max	= 2,
+		.rates		= SNDRV_PCM_RATE_8000_48000,
+		.formats	= EP93XX_I2S_FORMATS,
+	},
+	.capture	= {
+		 .channels_min	= 2,
+		 .channels_max	= 2,
+		 .rates		= SNDRV_PCM_RATE_8000_48000,
+		 .formats	= EP93XX_I2S_FORMATS,
+	},
+	.ops		= &ep93xx_i2s_dai_ops,
+};
+EXPORT_SYMBOL_GPL(ep93xx_i2s_dai);
+
+static int ep93xx_i2s_probe(struct platform_device *pdev)
+{
+	struct ep93xx_i2s_info *info;
+	struct resource *res;
+	int err;
+
+	info = kzalloc(sizeof(struct ep93xx_i2s_info), GFP_KERNEL);
+	if (!info) {
+		err = -ENOMEM;
+		goto fail;
+	}
+
+	ep93xx_i2s_dai.dev = &pdev->dev;
+	ep93xx_i2s_dai.private_data = info;
+	info->dma_params = ep93xx_i2s_dma_params;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		err = -ENODEV;
+		goto fail;
+	}
+
+	info->mem = request_mem_region(res->start, resource_size(res),
+				       pdev->name);
+	if (!info->mem) {
+		err = -EBUSY;
+		goto fail;
+	}
+
+	info->regs = ioremap(info->mem->start, resource_size(info->mem));
+	if (!info->regs) {
+		err = -ENXIO;
+		goto fail_release_mem;
+	}
+
+	info->mclk = clk_get(&pdev->dev, "mclk");
+	if (IS_ERR(info->mclk)) {
+		err = PTR_ERR(info->mclk);
+		goto fail_unmap_mem;
+	}
+
+	info->sclk = clk_get(&pdev->dev, "sclk");
+	if (IS_ERR(info->sclk)) {
+		err = PTR_ERR(info->sclk);
+		goto fail_put_mclk;
+	}
+
+	info->lrclk = clk_get(&pdev->dev, "lrclk");
+	if (IS_ERR(info->lrclk)) {
+		err = PTR_ERR(info->lrclk);
+		goto fail_put_sclk;
+	}
+
+	err = snd_soc_register_dai(&ep93xx_i2s_dai);
+	if (err)
+		goto fail_put_lrclk;
+
+	return 0;
+
+fail_put_lrclk:
+	clk_put(info->lrclk);
+fail_put_sclk:
+	clk_put(info->sclk);
+fail_put_mclk:
+	clk_put(info->mclk);
+fail_unmap_mem:
+	iounmap(info->regs);
+fail_release_mem:
+	release_mem_region(info->mem->start, resource_size(info->mem));
+	kfree(info);
+fail:
+	return err;
+}
+
+static int __devexit ep93xx_i2s_remove(struct platform_device *pdev)
+{
+	struct ep93xx_i2s_info *info = ep93xx_i2s_dai.private_data;
+
+	snd_soc_unregister_dai(&ep93xx_i2s_dai);
+	clk_put(info->lrclk);
+	clk_put(info->sclk);
+	clk_put(info->mclk);
+	iounmap(info->regs);
+	release_mem_region(info->mem->start, resource_size(info->mem));
+	kfree(info);
+	return 0;
+}
+
+static struct platform_driver ep93xx_i2s_driver = {
+	.probe	= ep93xx_i2s_probe,
+	.remove	= __devexit_p(ep93xx_i2s_remove),
+	.driver	= {
+		.name	= "ep93xx-i2s",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init ep93xx_i2s_init(void)
+{
+	return platform_driver_register(&ep93xx_i2s_driver);
+}
+
+static void __exit ep93xx_i2s_exit(void)
+{
+	platform_driver_unregister(&ep93xx_i2s_driver);
+}
+
+module_init(ep93xx_i2s_init);
+module_exit(ep93xx_i2s_exit);
+
+MODULE_ALIAS("platform:ep93xx-i2s");
+MODULE_AUTHOR("Ryan Mallon <ryan at bluewatersys.com>");
+MODULE_DESCRIPTION("EP93XX I2S driver");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/ep93xx/ep93xx-i2s.h b/sound/soc/ep93xx/ep93xx-i2s.h
new file mode 100644
index 0000000..3bd4ebf
--- /dev/null
+++ b/sound/soc/ep93xx/ep93xx-i2s.h
@@ -0,0 +1,18 @@
+/*
+ * linux/sound/soc/ep93xx-i2s.h
+ * EP93xx I2S driver
+ *
+ * Copyright (C) 2010 Ryan Mallon <ryan at bluewatersys.com>
+ *  
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _EP93XX_SND_SOC_I2S_H
+#define _EP93XX_SND_SOC_I2S_H
+
+extern struct snd_soc_dai ep93xx_i2s_dai;
+
+#endif /* _EP93XX_SND_SOC_I2S_H */
diff --git a/sound/soc/ep93xx/ep93xx-pcm.c b/sound/soc/ep93xx/ep93xx-pcm.c
new file mode 100644
index 0000000..4ba9384
--- /dev/null
+++ b/sound/soc/ep93xx/ep93xx-pcm.c
@@ -0,0 +1,319 @@
+/*
+ * linux/sound/arm/ep93xx-pcm.c - EP93xx ALSA PCM interface
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh at wantstofly.org>
+ * Copyright (C) 2006 Applied Data Systems
+ *
+ * Rewritten for the SoC audio subsystem (Based on PXA2xx code):
+ *   Copyright (c) 2008 Ryan Mallon <ryan at bluewatersys.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <mach/dma.h>
+#include <mach/hardware.h>
+#include <mach/ep93xx-regs.h>
+
+#include "ep93xx-pcm.h"
+
+static const struct snd_pcm_hardware ep93xx_pcm_hardware = {
+	.info			= (SNDRV_PCM_INFO_MMAP		|
+				   SNDRV_PCM_INFO_MMAP_VALID	|
+				   SNDRV_PCM_INFO_INTERLEAVED	|
+				   SNDRV_PCM_INFO_BLOCK_TRANSFER),
+				   
+	.rates			= SNDRV_PCM_RATE_8000_48000,
+	.rate_min		= SNDRV_PCM_RATE_8000,
+	.rate_max		= SNDRV_PCM_RATE_48000,
+	
+	.formats		= (SNDRV_PCM_FMTBIT_S16_LE |
+				   SNDRV_PCM_FMTBIT_S24_LE |
+				   SNDRV_PCM_FMTBIT_S32_LE),
+	
+	.buffer_bytes_max	= 131072,
+	.period_bytes_min	= 32,
+	.period_bytes_max	= 32768,
+	.periods_min		= 1,
+	.periods_max		= 32,
+	.fifo_size		= 32,
+};
+
+struct ep93xx_runtime_data
+{
+	struct ep93xx_dma_m2p_client	cl;
+	struct ep93xx_pcm_dma_params	*params;
+	int				pointer_bytes;
+	struct tasklet_struct		period_tasklet;
+	int				periods;
+	struct ep93xx_dma_buffer	buf[32];
+};
+
+static void ep93xx_pcm_period_elapsed(unsigned long data)
+{
+	struct snd_pcm_substream *substream = (struct snd_pcm_substream *)data;
+	snd_pcm_period_elapsed(substream);
+}
+
+static void ep93xx_pcm_buffer_started(void *cookie,
+				      struct ep93xx_dma_buffer *buf)
+{
+}
+
+static void ep93xx_pcm_buffer_finished(void *cookie, 
+				       struct ep93xx_dma_buffer *buf, 
+				       int bytes, int error)
+{
+	struct snd_pcm_substream *substream = cookie;
+	struct ep93xx_runtime_data *rtd = substream->runtime->private_data;
+
+	if (buf == rtd->buf + rtd->periods - 1)
+		rtd->pointer_bytes = 0;
+	else
+		rtd->pointer_bytes += buf->size;
+
+	if (!error) {
+		ep93xx_dma_m2p_submit_recursive(&rtd->cl, buf);
+		tasklet_schedule(&rtd->period_tasklet);
+	} else {
+		snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
+	}
+}
+
+static int ep93xx_pcm_open(struct snd_pcm_substream *substream)
+{
+	struct snd_soc_pcm_runtime *soc_rtd = substream->private_data;
+	struct snd_soc_dai *cpu_dai = soc_rtd->dai->cpu_dai;
+	struct ep93xx_pcm_dma_params *dma_params;
+	struct ep93xx_runtime_data *rtd;    
+	int ret;
+
+	dma_params = snd_soc_dai_get_dma_data(cpu_dai, substream);
+	snd_soc_set_runtime_hwparams(substream, &ep93xx_pcm_hardware);
+
+	rtd = kmalloc(sizeof(*rtd), GFP_KERNEL);
+	if (!rtd) 
+		return -ENOMEM;
+
+	memset(&rtd->period_tasklet, 0, sizeof(rtd->period_tasklet));
+	rtd->period_tasklet.func = ep93xx_pcm_period_elapsed;
+	rtd->period_tasklet.data = (unsigned long)substream;
+
+	rtd->cl.name = dma_params->name;
+	rtd->cl.flags = dma_params->dma_port | EP93XX_DMA_M2P_IGNORE_ERROR |
+		((substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
+		 EP93XX_DMA_M2P_TX : EP93XX_DMA_M2P_RX);
+	rtd->cl.cookie = substream;
+	rtd->cl.buffer_started = ep93xx_pcm_buffer_started;
+	rtd->cl.buffer_finished = ep93xx_pcm_buffer_finished;
+	ret = ep93xx_dma_m2p_client_register(&rtd->cl);
+	if (ret < 0) {
+		kfree(rtd);
+		return ret;
+	}
+	
+	substream->runtime->private_data = rtd;
+	return 0;
+}
+
+static int ep93xx_pcm_close(struct snd_pcm_substream *substream)
+{
+	struct ep93xx_runtime_data *rtd = substream->runtime->private_data;
+
+	ep93xx_dma_m2p_client_unregister(&rtd->cl);
+	kfree(rtd);
+	return 0;
+}
+
+static int ep93xx_pcm_hw_params(struct snd_pcm_substream *substream,
+				struct snd_pcm_hw_params *params)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct ep93xx_runtime_data *rtd = runtime->private_data;
+	size_t totsize = params_buffer_bytes(params);
+	size_t period = params_period_bytes(params);
+	int i;
+
+	snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
+	runtime->dma_bytes = totsize;
+
+	rtd->periods = (totsize + period - 1) / period;
+	for (i = 0; i < rtd->periods; i++) {
+		rtd->buf[i].bus_addr = runtime->dma_addr + (i * period);
+		rtd->buf[i].size = period;
+		if ((i + 1) * period > totsize)
+			rtd->buf[i].size = totsize - (i * period);
+	}
+
+	return 0;
+}
+
+static int ep93xx_pcm_hw_free(struct snd_pcm_substream *substream)
+{
+	snd_pcm_set_runtime_buffer(substream, NULL);
+	return 0;
+}
+
+static int ep93xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
+{
+	struct ep93xx_runtime_data *rtd = substream->runtime->private_data;
+	int ret;
+	int i;
+
+	ret = 0;
+	switch (cmd) {
+	case SNDRV_PCM_TRIGGER_START:
+	case SNDRV_PCM_TRIGGER_RESUME:
+	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+		rtd->pointer_bytes = 0;
+		for (i = 0; i < rtd->periods; i++)
+			ep93xx_dma_m2p_submit(&rtd->cl, rtd->buf + i);
+		break;
+
+	case SNDRV_PCM_TRIGGER_STOP:
+	case SNDRV_PCM_TRIGGER_SUSPEND:
+	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+		ep93xx_dma_m2p_flush(&rtd->cl);
+		break;
+
+	default:
+		ret = -EINVAL;
+		break;
+	}
+
+	return ret;
+}
+
+static snd_pcm_uframes_t ep93xx_pcm_pointer(struct snd_pcm_substream *substream)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+	struct ep93xx_runtime_data *rtd = substream->runtime->private_data;
+
+	/* FIXME: implement this with sub-period granularity */
+	return bytes_to_frames(runtime, rtd->pointer_bytes);
+}
+
+static int ep93xx_pcm_mmap(struct snd_pcm_substream *substream,
+			   struct vm_area_struct *vma)
+{
+	struct snd_pcm_runtime *runtime = substream->runtime;
+
+	return dma_mmap_writecombine(substream->pcm->card->dev, vma,
+				     runtime->dma_area,
+				     runtime->dma_addr,
+				     runtime->dma_bytes);
+}
+
+static struct snd_pcm_ops ep93xx_pcm_ops = {
+	.open		= ep93xx_pcm_open,
+	.close		= ep93xx_pcm_close,
+	.ioctl		= snd_pcm_lib_ioctl,
+	.hw_params	= ep93xx_pcm_hw_params,
+	.hw_free	= ep93xx_pcm_hw_free,
+	.trigger	= ep93xx_pcm_trigger,
+	.pointer	= ep93xx_pcm_pointer,
+	.mmap		= ep93xx_pcm_mmap,
+};
+
+static int ep93xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream)
+{
+	struct snd_pcm_substream *substream = pcm->streams[stream].substream;
+	struct snd_dma_buffer *buf = &substream->dma_buffer;
+	size_t size = ep93xx_pcm_hardware.buffer_bytes_max;
+
+	buf->dev.type = SNDRV_DMA_TYPE_DEV;
+	buf->dev.dev = pcm->card->dev;
+	buf->private_data = NULL;
+	buf->area = dma_alloc_writecombine(pcm->card->dev, size,
+					   &buf->addr, GFP_KERNEL);
+	buf->bytes = size;
+
+	return (buf->area == NULL) ? -ENOMEM : 0;
+}
+
+static void ep93xx_pcm_free_dma_buffers(struct snd_pcm *pcm)
+{
+	struct snd_pcm_substream *substream;
+	struct snd_dma_buffer *buf;
+	int stream;
+
+	for (stream = 0; stream < 2; stream++) {		
+		substream = pcm->streams[stream].substream;
+		if (!substream)
+			continue;
+		
+		buf = &substream->dma_buffer;
+		if (!buf->area)
+			continue;
+
+		dma_free_writecombine(pcm->card->dev, buf->bytes, buf->area,
+				      buf->addr);
+		buf->area = NULL;
+	}
+}
+
+static u64 ep93xx_pcm_dmamask = 0xffffffff;
+
+static int ep93xx_pcm_new(struct snd_card *card, struct snd_soc_dai *dai,
+			  struct snd_pcm *pcm)
+{
+	int ret = 0;
+
+	if (!card->dev->dma_mask)
+		card->dev->dma_mask = &ep93xx_pcm_dmamask;
+	if (!card->dev->coherent_dma_mask)
+		card->dev->coherent_dma_mask = 0xffffffff;
+
+	if (dai->playback.channels_min) {
+		ret = ep93xx_pcm_preallocate_dma_buffer(pcm,
+					SNDRV_PCM_STREAM_PLAYBACK);
+		if (ret)
+			return ret;
+	}
+
+	if (dai->capture.channels_min) {
+		ret = ep93xx_pcm_preallocate_dma_buffer(pcm,
+					SNDRV_PCM_STREAM_CAPTURE);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+struct snd_soc_platform ep93xx_soc_platform = {
+	.name		= "ep93xx-audio",
+	.pcm_ops	= &ep93xx_pcm_ops,
+	.pcm_new	= &ep93xx_pcm_new,
+	.pcm_free	= &ep93xx_pcm_free_dma_buffers,
+};
+EXPORT_SYMBOL_GPL(ep93xx_soc_platform);
+
+static int __init ep93xx_soc_platform_init(void)
+{
+	return snd_soc_register_platform(&ep93xx_soc_platform);
+}
+
+static void __exit ep93xx_soc_platform_exit(void)
+{
+	snd_soc_unregister_platform(&ep93xx_soc_platform);
+}
+
+module_init(ep93xx_soc_platform_init);
+module_exit(ep93xx_soc_platform_exit);
+
+MODULE_AUTHOR("Ryan Mallon <ryan at bluewatersys.com>");
+MODULE_DESCRIPTION("EP93xx ALSA PCM interface");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/ep93xx/ep93xx-pcm.h b/sound/soc/ep93xx/ep93xx-pcm.h
new file mode 100644
index 0000000..4ffdd3f
--- /dev/null
+++ b/sound/soc/ep93xx/ep93xx-pcm.h
@@ -0,0 +1,22 @@
+/*
+ * sound/soc/ep93xx/ep93xx-pcm.h - EP93xx ALSA PCM interface
+ *
+ * Copyright (C) 2006 Lennert Buytenhek <buytenh at wantstofly.org>
+ * Copyright (C) 2006 Applied Data Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EP93XX_SND_SOC_PCM_H
+#define _EP93XX_SND_SOC_PCM_H
+
+struct ep93xx_pcm_dma_params {
+	char	*name;
+	int	dma_port;
+};
+
+extern struct snd_soc_platform ep93xx_soc_platform;
+
+#endif /* _EP93XX_SND_SOC_PCM_H */
-- 
1.6.0.4



From ryan at bluewatersys.com  Tue Jun  8 06:01:12 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Tue,  8 Jun 2010 22:01:12 +1200
Subject: [PATCH 3/3] EP93xx: Add Snapper CL15 i2s audio support
In-Reply-To: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1275991272-30122-4-git-send-email-ryan@bluewatersys.com>

Add support for i2s audio on Bluewater Systems Snapper CL15 module

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-ep93xx/snappercl15.c |    1 +
 sound/soc/ep93xx/Kconfig           |    9 ++
 sound/soc/ep93xx/Makefile          |    3 +
 sound/soc/ep93xx/snappercl15.c     |  150 ++++++++++++++++++++++++++++++++++++
 4 files changed, 163 insertions(+), 0 deletions(-)
 create mode 100644 sound/soc/ep93xx/snappercl15.c

diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index 51134b0..fee53a4 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -157,6 +157,7 @@ static void __init snappercl15_init_machine(void)
 	ep93xx_register_i2c(&snappercl15_i2c_gpio_data, snappercl15_i2c_data,
 			    ARRAY_SIZE(snappercl15_i2c_data));
 	ep93xx_register_fb(&snappercl15_fb_info);
+	ep93xx_register_i2s();
 	platform_device_register(&snappercl15_nand_device);
 }
 
diff --git a/sound/soc/ep93xx/Kconfig b/sound/soc/ep93xx/Kconfig
index ba66ac8..f617f56 100644
--- a/sound/soc/ep93xx/Kconfig
+++ b/sound/soc/ep93xx/Kconfig
@@ -7,3 +7,12 @@ config SND_EP93XX_SOC
 
 config SND_EP93XX_SOC_I2S
 	tristate
+
+config SND_EP93XX_SOC_SNAPPERCL15
+        tristate "SoC Audio support for Bluewater Systems Snapper CL15 module"
+        depends on SND_EP93XX_SOC && MACH_SNAPPER_CL15
+        select SND_EP93XX_SOC_I2S
+        select SND_SOC_TLV320AIC23
+        help
+          Say Y or M here if you want to add support for I2S audio on the
+          Bluewater Systems Snapper CL15 module.
diff --git a/sound/soc/ep93xx/Makefile b/sound/soc/ep93xx/Makefile
index 0239da3..272e60f 100644
--- a/sound/soc/ep93xx/Makefile
+++ b/sound/soc/ep93xx/Makefile
@@ -6,3 +6,6 @@ obj-$(CONFIG_SND_EP93XX_SOC)			+= snd-soc-ep93xx.o
 obj-$(CONFIG_SND_EP93XX_SOC_I2S)		+= snd-soc-ep93xx-i2s.o
 
 # EP93XX Machine Support
+snd-soc-snappercl15-objs			:= snappercl15.o
+
+obj-$(CONFIG_SND_EP93XX_SOC_SNAPPERCL15)	+= snd-soc-snappercl15.o
diff --git a/sound/soc/ep93xx/snappercl15.c b/sound/soc/ep93xx/snappercl15.c
new file mode 100644
index 0000000..6495534
--- /dev/null
+++ b/sound/soc/ep93xx/snappercl15.c
@@ -0,0 +1,150 @@
+/*
+ * snappercl15.c -- SoC audio for Bluewater Systems Snapper CL15 module
+ *
+ * Copyright (C) 2008 Bluewater Systems Ltd
+ * Author: Ryan Mallon <ryan at bluewatersys.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+
+#include <asm/mach-types.h>
+#include <mach/hardware.h>
+
+#include "../codecs/tlv320aic23.h"
+#include "ep93xx-pcm.h"
+#include "ep93xx-i2s.h"
+
+#define CODEC_CLOCK 5644800
+
+static int snappercl15_hw_params(struct snd_pcm_substream *substream,
+				 struct snd_pcm_hw_params *params)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_dai *codec_dai = rtd->dai->codec_dai;
+	struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
+	int err;
+
+	err = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+				  SND_SOC_DAIFMT_NB_IF |
+				  SND_SOC_DAIFMT_CBS_CFS);
+
+	err = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | 
+				  SND_SOC_DAIFMT_NB_IF |		  
+				  SND_SOC_DAIFMT_CBS_CFS);
+	if (err)
+		return err;
+
+	err = snd_soc_dai_set_sysclk(codec_dai, 0, CODEC_CLOCK, 
+				     SND_SOC_CLOCK_IN);
+	if (err)
+		return err;
+
+	err = snd_soc_dai_set_sysclk(cpu_dai, 0, CODEC_CLOCK, 
+				     SND_SOC_CLOCK_OUT);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+static struct snd_soc_ops snappercl15_ops = {
+	.hw_params	= snappercl15_hw_params,
+};
+
+static const struct snd_soc_dapm_widget tlv320aic23_dapm_widgets[] = {
+	SND_SOC_DAPM_HP("Headphone Jack", NULL),
+	SND_SOC_DAPM_LINE("Line In", NULL),
+	SND_SOC_DAPM_MIC("Mic Jack", NULL),
+};
+
+static const struct snd_soc_dapm_route audio_map[] = {
+	{"Headphone Jack", NULL, "LHPOUT"},
+	{"Headphone Jack", NULL, "RHPOUT"},
+
+	{"LLINEIN", NULL, "Line In"},
+	{"RLINEIN", NULL, "Line In"},
+
+	{"MICIN", NULL, "Mic Jack"},
+};
+
+static int snappercl15_tlv320aic23_init(struct snd_soc_codec *codec)
+{
+	snd_soc_dapm_new_controls(codec, tlv320aic23_dapm_widgets,
+				  ARRAY_SIZE(tlv320aic23_dapm_widgets));
+
+	snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
+	return 0;
+}
+
+static struct snd_soc_dai_link snappercl15_dai = {
+	.name		= "tlv320aic23",
+	.stream_name	= "AIC23",
+	.cpu_dai	= &ep93xx_i2s_dai,
+	.codec_dai	= &tlv320aic23_dai,
+	.init		= snappercl15_tlv320aic23_init,
+	.ops		= &snappercl15_ops,
+};
+
+static struct snd_soc_card snd_soc_snappercl15 = {
+	.name		= "Snapper CL15",
+	.platform	= &ep93xx_soc_platform,
+	.dai_link	= &snappercl15_dai,
+	.num_links	= 1,
+};
+
+static struct snd_soc_device snappercl15_snd_devdata = {
+	.card		= &snd_soc_snappercl15,
+	.codec_dev	= &soc_codec_dev_tlv320aic23,
+};
+
+static struct platform_device *snappercl15_snd_device;
+
+static int __init snappercl15_init(void)
+{
+	int ret;
+
+	if (!machine_is_snapper_cl15())
+		return -ENODEV;
+
+	ret = ep93xx_i2s_acquire(EP93XX_SYSCON_DEVCFG_I2SONAC97,
+				 EP93XX_SYSCON_I2SCLKDIV_ORIDE |
+				 EP93XX_SYSCON_I2SCLKDIV_SPOL);
+	if (ret)
+		return ret;
+
+	snappercl15_snd_device = platform_device_alloc("soc-audio", -1);
+	if (!snappercl15_snd_device)
+		return -ENOMEM;
+	
+	platform_set_drvdata(snappercl15_snd_device, &snappercl15_snd_devdata);
+	snappercl15_snd_devdata.dev = &snappercl15_snd_device->dev;
+	ret = platform_device_add(snappercl15_snd_device);
+	if (ret)
+		platform_device_put(snappercl15_snd_device);
+
+	return ret;
+}
+
+static void __exit snappercl15_exit(void)
+{
+	platform_device_unregister(snappercl15_snd_device);
+	ep93xx_i2s_release();
+}
+
+module_init(snappercl15_init);
+module_exit(snappercl15_exit);
+
+MODULE_AUTHOR("Ryan Mallon <ryan at bluewatersys.com>");
+MODULE_DESCRIPTION("ALSA SoC Snapper CL15");
+MODULE_LICENSE("GPL");
+
-- 
1.6.0.4



From catalin.marinas at arm.com  Tue Jun  8 06:04:15 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 08 Jun 2010 11:04:15 +0100
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
In-Reply-To: <20100607215224.GD7220@n2100.arm.linux.org.uk>
References: <20100607173630.GA10489@oksana.dev.rtsoft.ru>
	<20100607194457.GC7220@n2100.arm.linux.org.uk>
	<20100607202701.GA14529@oksana.dev.rtsoft.ru>
	<1275944757.11056.16.camel@toshiba-laptop>
	<20100607215224.GD7220@n2100.arm.linux.org.uk>
Message-ID: <1275991455.2127.2.camel@e102109-lin.cambridge.arm.com>

On Mon, 2010-06-07 at 22:52 +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 07, 2010 at 10:05:57PM +0100, Catalin Marinas wrote:
> > But as I said, we already have patches to change the kernel R/W
> > permission for RO user pages.
> 
> ... but they introduce their own problem.

And these problem are ...

-- 
Catalin



From broonie at opensource.wolfsonmicro.com  Tue Jun  8 06:05:14 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 8 Jun 2010 11:05:14 +0100
Subject: [PATCH 2/3] EP93xx: Add i2s audio driver
In-Reply-To: <1275991272-30122-3-git-send-email-ryan@bluewatersys.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<1275991272-30122-3-git-send-email-ryan@bluewatersys.com>
Message-ID: <20100608100514.GA7624@rakim.wolfsonmicro.main>

On Tue, Jun 08, 2010 at 10:01:11PM +1200, Ryan Mallon wrote:
> Add pcm and i2s SoC audio drivers for EP93xx
> 
> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>

As I said yesterday I have applied this patch already.  If there are any
changes in the new version please send incremental patches updating the
driver.


From ryan at bluewatersys.com  Tue Jun  8 06:09:27 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Tue, 08 Jun 2010 22:09:27 +1200
Subject: [alsa-devel] [PATCH 2/3] EP93xx: Add i2s audio driver
In-Reply-To: <20100608100514.GA7624@rakim.wolfsonmicro.main>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>	<1275991272-30122-3-git-send-email-ryan@bluewatersys.com>
	<20100608100514.GA7624@rakim.wolfsonmicro.main>
Message-ID: <4C0E16D7.5070506@bluewatersys.com>

Mark Brown wrote:
> On Tue, Jun 08, 2010 at 10:01:11PM +1200, Ryan Mallon wrote:
>> Add pcm and i2s SoC audio drivers for EP93xx
>>
>> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
> 
> As I said yesterday I have applied this patch already.  If there are any
> changes in the new version please send incremental patches updating the
> driver.

There are no changes to the patch which you have picked up, only the
other two. I reposted the whole series for completeness. Will post
incremental patches if there are changes to patch 2/3.

~Ryan


From catalin.marinas at arm.com  Tue Jun  8 06:14:37 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 08 Jun 2010 11:14:37 +0100
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
In-Reply-To: <20100607213517.GA25479@oksana.dev.rtsoft.ru>
References: <20100607173630.GA10489@oksana.dev.rtsoft.ru>
	<20100607194457.GC7220@n2100.arm.linux.org.uk>
	<20100607202701.GA14529@oksana.dev.rtsoft.ru>
	<alpine.LFD.2.00.1006071634340.30664@xanadu.home>
	<20100607213517.GA25479@oksana.dev.rtsoft.ru>
Message-ID: <1275992077.2127.13.camel@e102109-lin.cambridge.arm.com>

On Mon, 2010-06-07 at 22:35 +0100, Anton Vorontsov wrote:
> On Mon, Jun 07, 2010 at 04:40:01PM -0400, Nicolas Pitre wrote:
> > On Tue, 8 Jun 2010, Anton Vorontsov wrote:
> >
> > > So, can we solve this by
> > >
> > > ldrex
> > > ...
> > > strt newval
> > >    ^ may cause exception, but doesn't clear the tag, so we're still atomic
> > > strex <- clears the tag
> >
> > No, you're not atomic anymore, as some other ldrex/strex might have come
> > through by the time the strt is executed, and while this strex wouldn't
> > be executed as the tag would be cleared at that point, the strt has no
> > such concerns with atomic tags and would indeed corrupt whatever new
> > value has been stored in the mean time.
> 
> Ugh, surely right you are, thanks!
> 
> It seems Catalin's "Remove the domain switching" patch comes handy
> here.

As I said, not all the domains patch is needed for your specific case,
just the parts dealing with page permissions.

-- 
Catalin



From broonie at opensource.wolfsonmicro.com  Tue Jun  8 06:24:44 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 8 Jun 2010 11:24:44 +0100
Subject: [alsa-devel] [PATCH 2/3] EP93xx: Add i2s audio driver
In-Reply-To: <4C0E16D7.5070506@bluewatersys.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<1275991272-30122-3-git-send-email-ryan@bluewatersys.com>
	<20100608100514.GA7624@rakim.wolfsonmicro.main>
	<4C0E16D7.5070506@bluewatersys.com>
Message-ID: <20100608102443.GB7129@sirena.org.uk>

On Tue, Jun 08, 2010 at 10:09:27PM +1200, Ryan Mallon wrote:

> There are no changes to the patch which you have picked up, only the
> other two. I reposted the whole series for completeness. Will post
> incremental patches if there are changes to patch 2/3.

OK, please add something to that effect to the changelog when reposting
without change so I know what's going on.


From linux at arm.linux.org.uk  Tue Jun  8 06:26:30 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 8 Jun 2010 11:26:30 +0100
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
In-Reply-To: <1275991455.2127.2.camel@e102109-lin.cambridge.arm.com>
References: <20100607173630.GA10489@oksana.dev.rtsoft.ru>
	<20100607194457.GC7220@n2100.arm.linux.org.uk>
	<20100607202701.GA14529@oksana.dev.rtsoft.ru>
	<1275944757.11056.16.camel@toshiba-laptop>
	<20100607215224.GD7220@n2100.arm.linux.org.uk>
	<1275991455.2127.2.camel@e102109-lin.cambridge.arm.com>
Message-ID: <20100608102630.GA22993@n2100.arm.linux.org.uk>

On Tue, Jun 08, 2010 at 11:04:15AM +0100, Catalin Marinas wrote:
> On Mon, 2010-06-07 at 22:52 +0100, Russell King - ARM Linux wrote:
> > On Mon, Jun 07, 2010 at 10:05:57PM +0100, Catalin Marinas wrote:
> > > But as I said, we already have patches to change the kernel R/W
> > > permission for RO user pages.
> > 
> > ... but they introduce their own problem.
> 
> And these problem are ...

As pointed out in May.


From catalin.marinas at arm.com  Tue Jun  8 06:42:28 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 08 Jun 2010 11:42:28 +0100
Subject: [PATCH] ARM: Add PI/robust mutexes support for SMP kernels
In-Reply-To: <20100608102630.GA22993@n2100.arm.linux.org.uk>
References: <20100608102630.GA22993@n2100.arm.linux.org.uk>
Message-ID: <1275993748.2127.21.camel@e102109-lin.cambridge.arm.com>

On Tue, 2010-06-08 at 11:26 +0100, Russell King - ARM Linux wrote:
> On Tue, Jun 08, 2010 at 11:04:15AM +0100, Catalin Marinas wrote:
> > On Mon, 2010-06-07 at 22:52 +0100, Russell King - ARM Linux wrote:
> > > On Mon, Jun 07, 2010 at 10:05:57PM +0100, Catalin Marinas wrote:
> > > > But as I said, we already have patches to change the kernel R/W
> > > > permission for RO user pages.
> > >
> > > ... but they introduce their own problem.
> >
> > And these problem are ...
> 
> As pointed out in May.

Your first point was FIQ handlers and I updated the patch.

Your second point was I/D cache coherency and I also replied saying that
it doesn't matter on non-aliasing VIPT caches. There was no further
reply from you.

-- 
Catalin



From mcuos.com at gmail.com  Tue Jun  8 06:44:58 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Tue, 08 Jun 2010 18:44:58 +0800
Subject: [PATCH 1/2] pxa: Move 'regs-ac97.h' from /mach-pxa/inlude/ to
	/plat-pxa/include
Message-ID: <4C0E1F2A.1060306@gmail.com>

There is two kinds of changes:
(1) Move 'regs-ac97.h' from /mach-pxa/inlude/ to /plat-pxa/include.

It will be the public header file If pxa168 ac97 driver was submitted.

(2) Modify the path of including header file.

Apply to (1).

Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>

---
 .../mach => plat-pxa/include/plat}/regs-ac97.h     |    0
 sound/arm/pxa2xx-ac97-lib.c                        |    2 +-
 sound/arm/pxa2xx-ac97.c                            |    2 +-
 sound/soc/pxa/pxa2xx-ac97.c                        |    2 +-
 4 files changed, 3 insertions(+), 3 deletions(-)
 rename arch/arm/{mach-pxa/include/mach => plat-pxa/include/plat}/regs-ac97.h (100%)

diff --git a/arch/arm/mach-pxa/include/mach/regs-ac97.h b/arch/arm/plat-pxa/include/plat/regs-ac97.h
similarity index 100%
rename from arch/arm/mach-pxa/include/mach/regs-ac97.h
rename to arch/arm/plat-pxa/include/plat/regs-ac97.h
diff --git a/sound/arm/pxa2xx-ac97-lib.c b/sound/arm/pxa2xx-ac97-lib.c
index 88eec38..e40093c 100644
--- a/sound/arm/pxa2xx-ac97-lib.c
+++ b/sound/arm/pxa2xx-ac97-lib.c
@@ -21,7 +21,7 @@
 #include <sound/pxa2xx-lib.h>

 #include <asm/irq.h>
-#include <mach/regs-ac97.h>
+#include <plat/regs-ac97.h>
 #include <mach/audio.h>

 static DEFINE_MUTEX(car_mutex);
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c
index 5d94118..246d0a1 100644
--- a/sound/arm/pxa2xx-ac97.c
+++ b/sound/arm/pxa2xx-ac97.c
@@ -20,7 +20,7 @@
 #include <sound/initval.h>
 #include <sound/pxa2xx-lib.h>

-#include <mach/regs-ac97.h>
+#include <plat/regs-ac97.h>
 #include <mach/audio.h>

 #include "pxa2xx-pcm.h"
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
index d314115..173c476 100644
--- a/sound/soc/pxa/pxa2xx-ac97.c
+++ b/sound/soc/pxa/pxa2xx-ac97.c
@@ -20,9 +20,9 @@
 #include <sound/pxa2xx-lib.h>

 #include <mach/hardware.h>
-#include <mach/regs-ac97.h>
 #include <mach/dma.h>
 #include <mach/audio.h>
+#include <plat/regs-ac97.h>

 #include "pxa2xx-pcm.h"
 #include "pxa2xx-ac97.h"
-- 
1.6.3.3


From mcuos.com at gmail.com  Tue Jun  8 06:55:29 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Tue, 08 Jun 2010 18:55:29 +0800
Subject: [PATCH 2/2] pxa: modify the pxa2xx-ac97 file for pxa168
Message-ID: <4C0E21A1.4000909@gmail.com>

In order to allow the sharing of the pxa2xx-ac97 driver file with pxa168,
we have to do a little change to pxa2xx-ac97 file.

All private register addresses were located in mach/include/ac97.h.

Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
---
 arch/arm/mach-pxa/include/mach/ac97.h      |   27 ++++++++++++++++++
 arch/arm/plat-pxa/include/plat/regs-ac97.h |   42 ++++++++++++++--------------
 sound/arm/pxa2xx-ac97.c                    |    4 +-
 sound/soc/pxa/pxa2xx-ac97.c                |   10 +++---
 4 files changed, 55 insertions(+), 28 deletions(-)
 create mode 100644 arch/arm/mach-pxa/include/mach/ac97.h

diff --git a/arch/arm/mach-pxa/include/mach/ac97.h b/arch/arm/mach-pxa/include/mach/ac97.h
new file mode 100644
index 0000000..c8db278
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/ac97.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-pxa/include/mach/ac97.h
+ *
+ * PXA AC97 header file
+ *
+ * Written by Wan ZongShun <mcuos.com at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ */
+
+#ifndef __ASM_ARCH_PXA_AC97_H
+#define __ASM_ARCH_PXA_AC97_H
+
+#include <mach/hardware.h>
+
+# define AC97_REG(x)		__REG((x) + 0x40500000)
+
+#define AC97_AUDIO_TX		12
+#define AC97_AUDIO_RX		11
+#define AC97_MODEM_TX		10
+#define AC97_MODEM_RX		9
+#define AC97_MIC		8
+
+#endif /* __ASM_ARCH_PXA_AC97_H */
diff --git a/arch/arm/plat-pxa/include/plat/regs-ac97.h b/arch/arm/plat-pxa/include/plat/regs-ac97.h
index b8d14bd..95d6cc5 100644
--- a/arch/arm/plat-pxa/include/plat/regs-ac97.h
+++ b/arch/arm/plat-pxa/include/plat/regs-ac97.h
@@ -1,25 +1,25 @@
 #ifndef __ASM_ARCH_REGS_AC97_H
 #define __ASM_ARCH_REGS_AC97_H

-#include <mach/hardware.h>
+#include <mach/ac97.h>

 /*
  * AC97 Controller registers
  */

-#define POCR		__REG(0x40500000)  /* PCM Out Control Register */
+#define POCR		AC97_REG(0x0000)  /* PCM Out Control Register */
 #define POCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
 #define POCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */

-#define PICR		__REG(0x40500004)  /* PCM In Control Register */
+#define PICR		AC97_REG(0x0004)  /* PCM In Control Register */
 #define PICR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
 #define PICR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */

-#define MCCR		__REG(0x40500008)  /* Mic In Control Register */
+#define MCCR		AC97_REG(0x0008)  /* Mic In Control Register */
 #define MCCR_FEIE	(1 << 3)	/* FIFO Error Interrupt Enable */
 #define MCCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */

-#define GCR		__REG(0x4050000C)  /* Global Control Register */
+#define GCR		AC97_REG(0x000C)  /* Global Control Register */
 #ifdef CONFIG_PXA3xx
 #define GCR_CLKBPB	(1 << 31)	/* Internal clock enable */
 #endif
@@ -35,21 +35,21 @@
 #define GCR_COLD_RST	(1 << 1)	/* AC'97 Cold Reset (0 = active) */
 #define GCR_GIE		(1 << 0)	/* Codec GPI Interrupt Enable */

-#define POSR		__REG(0x40500010)  /* PCM Out Status Register */
+#define POSR		AC97_REG(0x0010)  /* PCM Out Status Register */
 #define POSR_FIFOE	(1 << 4)	/* FIFO error */
 #define POSR_FSR	(1 << 2)	/* FIFO Service Request */

-#define PISR		__REG(0x40500014)  /* PCM In Status Register */
+#define PISR		AC97_REG(0x0014)  /* PCM In Status Register */
 #define PISR_FIFOE	(1 << 4)	/* FIFO error */
 #define PISR_EOC	(1 << 3)	/* DMA End-of-Chain (exclusive clear) */
 #define PISR_FSR	(1 << 2)	/* FIFO Service Request */

-#define MCSR		__REG(0x40500018)  /* Mic In Status Register */
+#define MCSR		AC97_REG(0x0018)  /* Mic In Status Register */
 #define MCSR_FIFOE	(1 << 4)	/* FIFO error */
 #define MCSR_EOC	(1 << 3)	/* DMA End-of-Chain (exclusive clear) */
 #define MCSR_FSR	(1 << 2)	/* FIFO Service Request */

-#define GSR		__REG(0x4050001C)  /* Global Status Register */
+#define GSR		AC97_REG(0x001C)  /* Global Status Register */
 #define GSR_CDONE	(1 << 19)	/* Command Done */
 #define GSR_SDONE	(1 << 18)	/* Status Done */
 #define GSR_RDCS	(1 << 15)	/* Read Completion Status */
@@ -68,34 +68,34 @@
 #define GSR_MIINT	(1 << 1)	/* Modem In Interrupt */
 #define GSR_GSCI	(1 << 0)	/* Codec GPI Status Change Interrupt */

-#define CAR		__REG(0x40500020)  /* CODEC Access Register */
+#define CAR		AC97_REG(0x0020)  /* CODEC Access Register */
 #define CAR_CAIP	(1 << 0)	/* Codec Access In Progress */

-#define PCDR		__REG(0x40500040)  /* PCM FIFO Data Register */
-#define MCDR		__REG(0x40500060)  /* Mic-in FIFO Data Register */
+#define PCDR		AC97_REG(0x0040)  /* PCM FIFO Data Register */
+#define MCDR		AC97_REG(0x0060)  /* Mic-in FIFO Data Register */

-#define MOCR		__REG(0x40500100)  /* Modem Out Control Register */
+#define MOCR		AC97_REG(0x0100)  /* Modem Out Control Register */
 #define MOCR_FEIE	(1 << 3)	/* FIFO Error */
 #define MOCR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */

-#define MICR		__REG(0x40500108)  /* Modem In Control Register */
+#define MICR		AC97_REG(0x0108)  /* Modem In Control Register */
 #define MICR_FEIE	(1 << 3)	/* FIFO Error */
 #define MICR_FSRIE	(1 << 1)	/* FIFO Service Request Interrupt Enable */

-#define MOSR		__REG(0x40500110)  /* Modem Out Status Register */
+#define MOSR		AC97_REG(0x0110)  /* Modem Out Status Register */
 #define MOSR_FIFOE	(1 << 4)	/* FIFO error */
 #define MOSR_FSR	(1 << 2)	/* FIFO Service Request */

-#define MISR		__REG(0x40500118)  /* Modem In Status Register */
+#define MISR		AC97_REG(0x0118)  /* Modem In Status Register */
 #define MISR_FIFOE	(1 << 4)	/* FIFO error */
 #define MISR_EOC	(1 << 3)	/* DMA End-of-Chain (exclusive clear) */
 #define MISR_FSR	(1 << 2)	/* FIFO Service Request */

-#define MODR		__REG(0x40500140)  /* Modem FIFO Data Register */
+#define MODR		AC97_REG(0x0140)  /* Modem FIFO Data Register */

-#define PAC_REG_BASE	__REG(0x40500200)  /* Primary Audio Codec */
-#define SAC_REG_BASE	__REG(0x40500300)  /* Secondary Audio Codec */
-#define PMC_REG_BASE	__REG(0x40500400)  /* Primary Modem Codec */
-#define SMC_REG_BASE	__REG(0x40500500)  /* Secondary Modem Codec */
+#define PAC_REG_BASE	AC97_REG(0x0200)  /* Primary Audio Codec */
+#define SAC_REG_BASE	AC97_REG(0x0300)  /* Secondary Audio Codec */
+#define PMC_REG_BASE	AC97_REG(0x0400)  /* Primary Modem Codec */
+#define SMC_REG_BASE	AC97_REG(0x0500)  /* Secondary Modem Codec */

 #endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/sound/arm/pxa2xx-ac97.c b/sound/arm/pxa2xx-ac97.c
index 246d0a1..4b66545 100644
--- a/sound/arm/pxa2xx-ac97.c
+++ b/sound/arm/pxa2xx-ac97.c
@@ -43,7 +43,7 @@ static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
 	.name			= "AC97 PCM out",
 	.dev_addr		= __PREG(PCDR),
-	.drcmr			= &DRCMR(12),
+	.drcmr			= &DRCMR(AC97_AUDIO_TX),
 	.dcmd			= DCMD_INCSRCADDR | DCMD_FLOWTRG |
 				  DCMD_BURST32 | DCMD_WIDTH4,
 };
@@ -51,7 +51,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_in = {
 	.name			= "AC97 PCM in",
 	.dev_addr		= __PREG(PCDR),
-	.drcmr			= &DRCMR(11),
+	.drcmr			= &DRCMR(AC97_AUDIO_RX),
 	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
 				  DCMD_BURST32 | DCMD_WIDTH4,
 };
diff --git a/sound/soc/pxa/pxa2xx-ac97.c b/sound/soc/pxa/pxa2xx-ac97.c
index 173c476..abb735c 100644
--- a/sound/soc/pxa/pxa2xx-ac97.c
+++ b/sound/soc/pxa/pxa2xx-ac97.c
@@ -51,7 +51,7 @@ struct snd_ac97_bus_ops soc_ac97_ops = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = {
 	.name			= "AC97 PCM Stereo out",
 	.dev_addr		= __PREG(PCDR),
-	.drcmr			= &DRCMR(12),
+	.drcmr			= &DRCMR(AC97_AUDIO_TX),
 	.dcmd			= DCMD_INCSRCADDR | DCMD_FLOWTRG |
 				  DCMD_BURST32 | DCMD_WIDTH4,
 };
@@ -59,7 +59,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = {
 	.name			= "AC97 PCM Stereo in",
 	.dev_addr		= __PREG(PCDR),
-	.drcmr			= &DRCMR(11),
+	.drcmr			= &DRCMR(AC97_AUDIO_RX),
 	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
 				  DCMD_BURST32 | DCMD_WIDTH4,
 };
@@ -67,7 +67,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = {
 	.name			= "AC97 Aux PCM (Slot 5) Mono out",
 	.dev_addr		= __PREG(MODR),
-	.drcmr			= &DRCMR(10),
+	.drcmr			= &DRCMR(AC97_MODEM_TX),
 	.dcmd			= DCMD_INCSRCADDR | DCMD_FLOWTRG |
 				  DCMD_BURST16 | DCMD_WIDTH2,
 };
@@ -75,7 +75,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = {
 	.name			= "AC97 Aux PCM (Slot 5) Mono in",
 	.dev_addr		= __PREG(MODR),
-	.drcmr			= &DRCMR(9),
+	.drcmr			= &DRCMR(AC97_MODEM_RX),
 	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
 				  DCMD_BURST16 | DCMD_WIDTH2,
 };
@@ -83,7 +83,7 @@ static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = {
 static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = {
 	.name			= "AC97 Mic PCM (Slot 6) Mono in",
 	.dev_addr		= __PREG(MCDR),
-	.drcmr			= &DRCMR(8),
+	.drcmr			= &DRCMR(AC97_MIC),
 	.dcmd			= DCMD_INCTRGADDR | DCMD_FLOWSRC |
 				  DCMD_BURST16 | DCMD_WIDTH2,
 };
-- 
1.6.3.3


From saeed.bishara at gmail.com  Tue Jun  8 07:20:18 2010
From: saeed.bishara at gmail.com (saeed bishara)
Date: Tue, 8 Jun 2010 14:20:18 +0300
Subject: [PATCH 3/3 v3] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <4C0CA7F8.3080506@alcatel-lucent.com>
References: <alpine.LFD.2.00.1006031224180.24526@xanadu.home>
	<1275819882-8373-1-git-send-email-saeed@marvell.com>
	<4C0CA7F8.3080506@alcatel-lucent.com>
Message-ID: <AANLkTilEM81aUCdIaTyN1s8es6LMETuMOGXh3a67sWgf@mail.gmail.com>

On Mon, Jun 7, 2010 at 11:04 AM, Benjamin Zores
<benjamin.zores at alcatel-lucent.com> wrote:
> On 06/06/2010 12:24, Saeed Bishara wrote:
>>
>> This patch extens the kirkwood's PCIe support up to 2 controllers as in
>> the 6282 devices.
>>
>> diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
>> b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
>> index 39bdf4b..c428348 100644
>> --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
>> +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
>> @@ -74,9 +74,15 @@ static void __init db88f6281_init(void)
>>
>> ?static int __init db88f6281_pci_init(void)
>> ?{
>> - ? ? ? if (machine_is_db88f6281_bp())
>> - ? ? ? ? ? ? ? kirkwood_pcie_init();
>> + ? ? ? if (machine_is_db88f6281_bp()) {
>> + ? ? ? ? ? ? ? u32 dev, rev;
>>
>> + ? ? ? ? ? ? ? kirkwood_pcie_id(&dev,&rev);
>> + ? ? ? ? ? ? ? if (dev == MV88F6282_DEV_ID)
>> + ? ? ? ? ? ? ? ? ? ? ? kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
>> + ? ? ? ? ? ? ? else
>> + ? ? ? ? ? ? ? ? ? ? ? kirkwood_pcie_init(KW_PCIE0);
>> + ? ? ? }
>> ? ? ? ?return 0;
>>
>
> This is still not likely to be possible: I don't think a given board can
> have 2 different SoCs.
well, it works because the 6282 is "pin-compatible" to 6281 and the
differences between the two boards are the additional pcie and few
mpps that set by the bootloader.
>
>> +#define CGC_PEX1 ? ? ? ? ? ? ? (1<< ?18)
>> ?#define CGC_GE1 ? ? ? ? ? ? ? ? ? ? ? (1<< ?19)
>> ?#define CGC_TDM ? ? ? ? ? ? ? ? ? ? ? (1<< ?20)
>> ?#define CGC_RESERVED ? ? ? ? ?((1<< ?18) | (0x6<< ?21))
>>
>
> (1 << 18) is no longer reserved.
>
> Except from that you still miss the mapping definition and phy
> initialization in common.c
>
> See
> http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/017176.html
> for details.
I applied your comments except to the io table, I don't think it's
worth to add, the pcie0 entry is always added even if that interface
is not used.
saeed


From saeed at marvell.com  Tue Jun  8 07:21:34 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Tue,  8 Jun 2010 14:21:34 +0300
Subject: [PATCH 3/3 v4] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <AANLkTilEM81aUCdIaTyN1s8es6LMETuMOGXh3a67sWgf@mail.gmail.com>
References: <AANLkTilEM81aUCdIaTyN1s8es6LMETuMOGXh3a67sWgf@mail.gmail.com>
Message-ID: <1275996094-16929-1-git-send-email-saeed@marvell.com>

This patch extens the kirkwood's PCIe support up to 2 controllers as in the 6282 devices.

Signed-off-by: Saeed Bishara <saeed at marvell.com>
---
 arch/arm/mach-kirkwood/addr-map.c                 |   10 +-
 arch/arm/mach-kirkwood/common.c                   |   21 +++-
 arch/arm/mach-kirkwood/common.h                   |    5 +-
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c       |   10 +-
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h |    3 +-
 arch/arm/mach-kirkwood/include/mach/irqs.h        |    1 +
 arch/arm/mach-kirkwood/include/mach/kirkwood.h    |   35 +++-
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c    |    2 +-
 arch/arm/mach-kirkwood/openrd-setup.c             |    2 +-
 arch/arm/mach-kirkwood/pcie.c                     |  187 +++++++++++++++-----
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c      |    2 +-
 arch/arm/mach-kirkwood/rd88f6281-setup.c          |    2 +-
 arch/arm/mach-kirkwood/ts219-setup.c              |    6 +-
 arch/arm/mach-kirkwood/ts41x-setup.c              |    2 +-
 14 files changed, 216 insertions(+), 72 deletions(-)

diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168..8d03bce 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
 #define ATTR_DEV_CS0		0x3e
 #define ATTR_PCIE_IO		0xe0
 #define ATTR_PCIE_MEM		0xe8
+#define ATTR_PCIE1_IO		0xd0
+#define ATTR_PCIE1_MEM		0xd8
 #define ATTR_SRAM		0x01
 
 /*
@@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
 		      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
 	setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
 		      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
+	setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
+		      TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
+	setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
+		      TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
 
 	/*
 	 * Setup window for NAND controller.
 	 */
-	setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+	setup_cpu_win(4, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
 		      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
 
 	/*
 	 * Setup window for SRAM.
 	 */
-	setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+	setup_cpu_win(5, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
 		      TARGET_SRAM, ATTR_SRAM, -1);
 
 	/*
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 4ccfdf9..9dd67c7 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -44,6 +44,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
 		.length		= KIRKWOOD_PCIE_IO_SIZE,
 		.type		= MT_DEVICE,
 	}, {
+		.virtual	= KIRKWOOD_PCIE1_IO_VIRT_BASE,
+		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
+		.length		= KIRKWOOD_PCIE1_IO_SIZE,
+		.type		= MT_DEVICE,
+	}, {
 		.virtual	= KIRKWOOD_REGS_VIRT_BASE,
 		.pfn		= __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
 		.length		= KIRKWOOD_REGS_SIZE,
@@ -960,12 +965,14 @@ void __init kirkwood_init(void)
 static int __init kirkwood_clock_gate(void)
 {
 	unsigned int curr = readl(CLOCK_GATING_CTRL);
+	u32 dev, rev;
 
+	kirkwood_pcie_id(&dev, &rev);
 	printk(KERN_DEBUG "Gating clock of unused units\n");
 	printk(KERN_DEBUG "before: 0x%08x\n", curr);
 
 	/* Make sure those units are accessible */
-	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);
+	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
 
 	/* For SATA: first shutdown the phy */
 	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
@@ -990,6 +997,18 @@ static int __init kirkwood_clock_gate(void)
 		writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
 	}
 
+	/* For PCIe 1: first shutdown the phy */
+	if (dev == MV88F6282_DEV_ID) {
+		if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
+			writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
+			while (1)
+				if (readl(PCIE1_STATUS) & 0x1)
+					break;
+			writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
+		}
+	} else  /* keep this bit set for devices that don't have PCIe1 */
+		kirkwood_clk_ctrl |= CGC_PEX1;
+
 	/* Now gate clock the required units */
 	writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
 	printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05e8a8a..5b2c1c1 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -18,6 +18,9 @@ struct mvsdio_platform_data;
 struct mtd_partition;
 struct mtd_info;
 
+#define KW_PCIE0	(1 << 0)
+#define KW_PCIE1	(1 << 1)
+
 /*
  * Basic Kirkwood init functions used early by machine-setup.
  */
@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);
 void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
-void kirkwood_pcie_init(void);
+void kirkwood_pcie_init(unsigned int portmask);
 void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
 void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
 void kirkwood_spi_init(void);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4b..c428348 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -74,9 +74,15 @@ static void __init db88f6281_init(void)
 
 static int __init db88f6281_pci_init(void)
 {
-	if (machine_is_db88f6281_bp())
-		kirkwood_pcie_init();
+	if (machine_is_db88f6281_bp()) {
+		u32 dev, rev;
 
+		kirkwood_pcie_id(&dev, &rev);
+		if (dev == MV88F6282_DEV_ID)
+			kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
+		else
+			kirkwood_pcie_init(KW_PCIE0);
+	}
 	return 0;
 }
 subsys_initcall(db88f6281_pci_init);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f501..aff0e13 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,8 +59,9 @@
 #define CGC_SATA1		(1 << 15)
 #define CGC_XOR1		(1 << 16)
 #define CGC_CRYPTO		(1 << 17)
+#define CGC_PEX1		(1 << 18)
 #define CGC_GE1			(1 << 19)
 #define CGC_TDM			(1 << 20)
-#define CGC_RESERVED		((1 << 18) | (0x6 << 21))
+#define CGC_RESERVED		(0x6 << 21)
 
 #endif
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index f00a0a4..9da2eb5 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -23,6 +23,7 @@
 #define IRQ_KIRKWOOD_XOR_10	7
 #define IRQ_KIRKWOOD_XOR_11	8
 #define IRQ_KIRKWOOD_PCIE	9
+#define IRQ_KIRKWOOD_PCIE1	10
 #define IRQ_KIRKWOOD_GE00_SUM	11
 #define IRQ_KIRKWOOD_GE01_SUM	15
 #define IRQ_KIRKWOOD_USB	19
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index dd7eddb..d141af4 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -16,36 +16,48 @@
  * Marvell Kirkwood address maps.
  *
  * phys
- * e0000000	PCIe Memory space
+ * e0000000	PCIe #0 Memory space
+ * e8000000	PCIe #1 Memory space
  * f1000000	on-chip peripheral registers
- * f2000000	PCIe I/O space
- * f3000000	NAND controller address window
- * f4000000	Security Accelerator SRAM
+ * f2000000	PCIe #0 I/O space
+ * f3000000	PCIe #1 I/O space
+ * f4000000	NAND controller address window
+ * f5000000	Security Accelerator SRAM
  *
  * virt		phys		size
- * fee00000	f1000000	1M	on-chip peripheral registers
- * fef00000	f2000000	1M	PCIe I/O space
+ * fed00000	f1000000	1M	on-chip peripheral registers
+ * fee00000	f2000000	1M	PCIe #0 I/O space
+ * fef00000	f3000000	1M	PCIe #1 I/O space
  */
 
-#define KIRKWOOD_SRAM_PHYS_BASE		0xf4000000
+#define KIRKWOOD_SRAM_PHYS_BASE		0xf5000000
 #define KIRKWOOD_SRAM_SIZE		SZ_2K
 
-#define KIRKWOOD_NAND_MEM_PHYS_BASE	0xf3000000
+#define KIRKWOOD_NAND_MEM_PHYS_BASE	0xf4000000
 #define KIRKWOOD_NAND_MEM_SIZE		SZ_1K
 
+#define KIRKWOOD_PCIE1_IO_PHYS_BASE	0xf3000000
+#define KIRKWOOD_PCIE1_IO_VIRT_BASE	0xfef00000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE	0x00000000
+#define KIRKWOOD_PCIE1_IO_SIZE		SZ_1M
+
 #define KIRKWOOD_PCIE_IO_PHYS_BASE	0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE	0xfef00000
+#define KIRKWOOD_PCIE_IO_VIRT_BASE	0xfee00000
 #define KIRKWOOD_PCIE_IO_BUS_BASE	0x00000000
 #define KIRKWOOD_PCIE_IO_SIZE		SZ_1M
 
 #define KIRKWOOD_REGS_PHYS_BASE		0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE		0xfee00000
+#define KIRKWOOD_REGS_VIRT_BASE		0xfed00000
 #define KIRKWOOD_REGS_SIZE		SZ_1M
 
 #define KIRKWOOD_PCIE_MEM_PHYS_BASE	0xe0000000
 #define KIRKWOOD_PCIE_MEM_BUS_BASE	0xe0000000
 #define KIRKWOOD_PCIE_MEM_SIZE		SZ_128M
 
+#define KIRKWOOD_PCIE1_MEM_PHYS_BASE	0xe8000000
+#define KIRKWOOD_PCIE1_MEM_BUS_BASE	0xe8000000
+#define KIRKWOOD_PCIE1_MEM_SIZE		SZ_128M
+
 /*
  * Register Map
  */
@@ -72,6 +84,9 @@
 #define PCIE_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x40000)
 #define PCIE_LINK_CTRL		(PCIE_VIRT_BASE | 0x70)
 #define PCIE_STATUS		(PCIE_VIRT_BASE | 0x1a04)
+#define PCIE1_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x44000)
+#define PCIE1_LINK_CTRL		(PCIE1_VIRT_BASE | 0x70)
+#define PCIE1_STATUS		(PCIE1_VIRT_BASE | 0x1a04)
 
 #define USB_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x50000)
 
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 5e6f711..c6b92b4 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
 static int __init mv88f6281gtw_ge_pci_init(void)
 {
 	if (machine_is_mv88f6281gtw_ge())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec..2400207 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -85,7 +85,7 @@ static void __init openrd_init(void)
 static int __init openrd_pci_init(void)
 {
 	if (machine_is_openrd_base() || machine_is_openrd_client())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index dee1eff..89201a9 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,29 +18,43 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
+void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+{
+	*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
+	*rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+}
 
-#define PCIE_BASE	((void __iomem *)PCIE_VIRT_BASE)
+struct pcie_port {
+	u8			root_bus_nr;
+	void __iomem		*base;
+	spinlock_t		conf_lock;
+	int			irq;
+	struct resource		res[2];
+};
 
-void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+static int pcie_port_map[2];
+static int num_pcie_ports;
+
+static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
 {
-	*dev = orion_pcie_dev_id(PCIE_BASE);
-	*rev = orion_pcie_rev(PCIE_BASE);
+	struct pci_sys_data *sys = bus->sysdata;
+	return sys->private_data;
 }
 
-static int pcie_valid_config(int bus, int dev)
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 {
 	/*
 	 * Don't go out when trying to access --
 	 * 1. nonexisting device on local bus
 	 * 2. where there's no device connected (no link)
 	 */
-	if (bus == 0 && dev == 0)
+	if (bus == pp->root_bus_nr && dev == 0)
 		return 1;
 
-	if (!orion_pcie_link_up(PCIE_BASE))
+	if (!orion_pcie_link_up(pp->base))
 		return 0;
 
-	if (bus == 0 && dev != 1)
+	if (bus == pp->root_bus_nr && dev != 1)
 		return 0;
 
 	return 1;
@@ -52,22 +66,22 @@ static int pcie_valid_config(int bus, int dev)
  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  * transactions are atomic.
  */
-static DEFINE_SPINLOCK(kirkwood_pcie_lock);
 
 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 			int size, u32 *val)
 {
+	struct pcie_port *pp = bus_to_port(bus);
 	unsigned long flags;
 	int ret;
 
-	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
 		*val = 0xffffffff;
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
 
-	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
-	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+	spin_lock_irqsave(&pp->conf_lock, flags);
+	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+	spin_unlock_irqrestore(&pp->conf_lock, flags);
 
 	return ret;
 }
@@ -75,15 +89,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 			int where, int size, u32 val)
 {
+	struct pcie_port *pp = bus_to_port(bus);
 	unsigned long flags;
 	int ret;
 
-	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
-	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
-	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+	spin_lock_irqsave(&pp->conf_lock, flags);
+	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+	spin_unlock_irqrestore(&pp->conf_lock, flags);
 
 	return ret;
 }
@@ -93,50 +108,109 @@ static struct pci_ops pcie_ops = {
 	.write = pcie_wr_conf,
 };
 
-
-static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+static int __init pcie0_ioresouces_setup(struct pci_sys_data *sys)
 {
-	struct resource *res;
-	extern unsigned int kirkwood_clk_ctrl;
-
+	struct pcie_port *pp = (struct pcie_port *)sys->private_data;
 	/*
-	 * Generic PCIe unit setup.
+	 * IORESOURCE_IO
 	 */
-	orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
+	pp->res[0].name = "PCIe 0 I/O Space";
+	pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+	pp->res[0].flags = IORESOURCE_IO;
+	if (request_resource(&ioport_resource, &pp->res[0]))
+		panic("Request PCIe 0 IO resource failed\n");
+	sys->resource[0] = &pp->res[0];
 
 	/*
-	 * Request resources.
+	 * IORESOURCE_MEM
 	 */
-	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-	if (!res)
-		panic("pcie_setup unable to alloc resources");
+	pp->res[1].name = "PCIe 0 MEM";
+	pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+	pp->res[1].flags = IORESOURCE_MEM;
+	if (request_resource(&iomem_resource, &pp->res[1]))
+		panic("Request PCIe 0 Memory resource failed\n");
+	sys->resource[1] = &pp->res[1];
+
+	sys->resource[2] = NULL;
+	sys->io_offset = 0;
 
+	return 1;
+}
+
+static int __init pcie1_ioresouces_setup(struct pci_sys_data *sys)
+{
+	struct pcie_port *pp = (struct pcie_port *)sys->private_data;
 	/*
 	 * IORESOURCE_IO
 	 */
-	res[0].name = "PCIe I/O Space";
-	res[0].flags = IORESOURCE_IO;
-	res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-	res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
-	if (request_resource(&ioport_resource, &res[0]))
-		panic("Request PCIe IO resource failed\n");
-	sys->resource[0] = &res[0];
+	pp->res[0].name = "PCIe 1 I/O Space";
+	pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
+	pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
+	pp->res[0].flags = IORESOURCE_IO;
+	if (request_resource(&ioport_resource, &pp->res[0]))
+		panic("Request PCIe 1 IO resource failed\n");
+	sys->resource[0] = &pp->res[0];
 
 	/*
 	 * IORESOURCE_MEM
 	 */
-	res[1].name = "PCIe Memory Space";
-	res[1].flags = IORESOURCE_MEM;
-	res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
-	res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-	if (request_resource(&iomem_resource, &res[1]))
-		panic("Request PCIe Memory resource failed\n");
-	sys->resource[1] = &res[1];
+	pp->res[1].name = "PCIe 1 MEM";
+	pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+	pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+	pp->res[1].flags = IORESOURCE_MEM;
+	if (request_resource(&iomem_resource, &pp->res[1]))
+		panic("Request PCIe 1 Memory resource failed\n");
+	sys->resource[1] = &pp->res[1];
 
 	sys->resource[2] = NULL;
 	sys->io_offset = 0;
 
-	kirkwood_clk_ctrl |= CGC_PEX0;
+	return 1;
+}
+
+static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+	extern unsigned int kirkwood_clk_ctrl;
+	struct pcie_port *pp;
+	int index;
+	if (nr >= num_pcie_ports)
+		return 0;
+
+	index = pcie_port_map[nr];
+	printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
+
+	pp = kzalloc(sizeof(*pp), GFP_KERNEL);
+	if (!pp)
+		panic("PCIe: failed to allocate pcie_port data");
+	sys->private_data = pp;
+	pp->root_bus_nr = sys->busnr;
+	spin_lock_init(&pp->conf_lock);
+
+	switch (index) {
+	case 0:
+		pp->base = (void __iomem *)PCIE_VIRT_BASE;
+		pp->irq	= IRQ_KIRKWOOD_PCIE;
+		kirkwood_clk_ctrl |= CGC_PEX0;
+		pcie0_ioresouces_setup(sys);
+		break;
+	case 1:
+		pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+		pp->irq	= IRQ_KIRKWOOD_PCIE1;
+		kirkwood_clk_ctrl |= CGC_PEX1;
+		pcie1_ioresouces_setup(sys);
+		break;
+	default:
+		panic("PCIe setup: invalid controller");
+	}
+
+	/*
+	 * Generic PCIe unit setup.
+	 */
+	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+
+	orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
 
 	return 1;
 }
@@ -163,7 +237,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 {
 	struct pci_bus *bus;
 
-	if (nr == 0) {
+	if (nr < num_pcie_ports) {
 		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
 	} else {
 		bus = NULL;
@@ -175,18 +249,37 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 
 static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-	return IRQ_KIRKWOOD_PCIE;
+	struct pcie_port *pp = bus_to_port(dev->bus);
+
+	return pp->irq;
 }
 
 static struct hw_pci kirkwood_pci __initdata = {
-	.nr_controllers	= 1,
 	.swizzle	= pci_std_swizzle,
 	.setup		= kirkwood_pcie_setup,
 	.scan		= kirkwood_pcie_scan_bus,
 	.map_irq	= kirkwood_pcie_map_irq,
 };
 
-void __init kirkwood_pcie_init(void)
+static void __init add_pcie_port(int index, unsigned long base)
+{
+	printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
+
+	if (orion_pcie_link_up((void __iomem *)base)) {
+		printk(KERN_INFO "link up\n");
+		pcie_port_map[num_pcie_ports++] = index;
+	} else
+		printk(KERN_INFO "link down, ignoring\n");
+}
+
+void __init kirkwood_pcie_init(unsigned int portmask)
 {
+	if (portmask & KW_PCIE0)
+		add_pcie_port(0, PCIE_VIRT_BASE);
+
+	if (portmask & KW_PCIE1)
+		add_pcie_port(1, PCIE1_VIRT_BASE);
+
+	kirkwood_pci.nr_controllers = num_pcie_ports;
 	pci_common_init(&kirkwood_pci);
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 3bf6304..c34718c 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
 static int __init rd88f6192_pci_init(void)
 {
 	if (machine_is_rd88f6192_nas())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31708dd..3d14771 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
 static int __init rd88f6281_pci_init(void)
 {
 	if (machine_is_rd88f6281())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0f..7250087 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -110,10 +110,10 @@ static void __init qnap_ts219_init(void)
 
 static int __init ts219_pci_init(void)
 {
-   if (machine_is_ts219())
-           kirkwood_pcie_init();
+	if (machine_is_ts219())
+		kirkwood_pcie_init(KW_PCIE0);
 
-   return 0;
+	return 0;
 }
 subsys_initcall(ts219_pci_init);
 
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index de49c2d..a122868 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -136,7 +136,7 @@ static void __init qnap_ts41x_init(void)
 static int __init ts41x_pci_init(void)
 {
 	if (machine_is_ts41x())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
    return 0;
 }
-- 
1.6.0.4



From robert.jarzmik at free.fr  Tue Jun  8 07:23:06 2010
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Tue, 08 Jun 2010 13:23:06 +0200
Subject: [PATCH] pxa2xx/cpufreq: Fix DRI computation
In-Reply-To: <1275698808-31166-1-git-send-email-marek.vasut@gmail.com> (Marek
	Vasut's message of "Sat, 5 Jun 2010 02:46:48 +0200")
References: <1275698808-31166-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <87ljap7opx.fsf@free.fr>

Marek Vasut <marek.vasut at gmail.com> writes:

> The DRI field was incorrectly computed, causing various hangs and weird
> behaviour on PXA2xx machines. This patch introduces the DRI computation
> according to the PXA255 (January 2004) and PXA270 (MV-S301039-00 Rev. A)
> datasheets.
>
> NOTE: The CPU type is checked only once, so the code is a little bit faster now.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> ---
>  arch/arm/mach-pxa/cpufreq-pxa2xx.c |   33 +++++++++++++++++++++++++++++----
>  1 files changed, 29 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> index 9e4d981..5373db0 100644
> --- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> +++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> @@ -251,17 +251,42 @@ static void init_sdram_rows(void)
>  	if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
>  		drac0 = MDCNFG_DRAC0(mdcnfg);
>  
> -	sdram_rows = 1 << (11 + max(drac0, drac2));
> +	sdram_rows = 11 + max(drac0, drac2);
I don't think that's correct.

From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.0.1275996205.27306.linux-arm-kernel@lists.infradead.org>

that if drac == 2, then the SDRAM row is a number between 0 and (11+drac0) - 1.
That in turn means that the number of SDRAM rows is : 2 ^ (11 + drac0).
Example:
 - drac0 = 2 : row encoded on 13 bits => 2^13 rows (ie. 1 << (11 + 2)).

>  
>  static u32 mdrefr_dri(unsigned int freq)
>  {
>  	u32 dri = 0;
>  
> -	if (cpu_is_pxa25x())
> -		dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
> +	/* 
> +	 * PXA255 (6.5.3):
> +	 * 	DRI = (Refresh time / rows * memory clock frequency) / 32
> +	 * PXA270 (Table 91):
> +	 * 	DRI = (Refresh time / rows * memory clock frequency - 31) / 32
> +	 * 
> +	 * Memory clock frequency is in MHz here! (Refresh time is in ms).
> +	 */
I don't agree here either. The "freq" variable is in kHz. It comes from
"new_freq_mem = pxa_freq_settings[idx].membus;" in pxa_set_target(). The membus
value is in kHz, as in tables pxaXXX_freqs (see 104000 and 208000, second column
in pxa27x_freqs for example). As refresh time is in ms, there is no need for a
1000th multiplier.

And my understanding is that the legacy formula is incorrect, as you discovered
it. Yet it should be, IMO :
    if (cpu_is_pxa27x())
-       dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
+       dri = ((freq * SDRAM_TREF) / sdram_rows - 31) / 32;

This is the only change to apply IMHO.

Can you confirm my analysis ?

-- 
Robert


From eric.y.miao at gmail.com  Tue Jun  8 07:23:34 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 8 Jun 2010 19:23:34 +0800
Subject: [PATCH 2/2] pxa: modify the pxa2xx-ac97 file for pxa168
In-Reply-To: <4C0E21A1.4000909@gmail.com>
References: <4C0E21A1.4000909@gmail.com>
Message-ID: <AANLkTimNwtScfKYVc4qPZFEP6GYklPoHLgr2AE7yquQL@mail.gmail.com>

2010/6/8 Wan ZongShun <mcuos.com at gmail.com>:
> In order to allow the sharing of the pxa2xx-ac97 driver file with pxa168,
> we have to do a little change to pxa2xx-ac97 file.
>
> All private register addresses were located in mach/include/ac97.h.

This is not the right way to go, as suggested already. I hope the ac97
driver is more self-contained. i.e. having a platform device for:

 - where the registers are mapped from
 - drcmr channel numbers can be encoded within dma resource
 - ac97 register definitions are not exposed everywhere


From saeed at marvell.com  Tue Jun  8 07:30:37 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Tue,  8 Jun 2010 14:30:37 +0300
Subject: [PATCH] [ARM] Kirkwood: configure NAND mpp's for db88f6281
Message-ID: <1275996637-25273-1-git-send-email-saeed@marvell.com>

In case the board is configured to boot from spi flash, the mpps
will not be configured to select the NAND I/Os. This patch makes
sure to select the NAND I/O's regardless to the boot device type.

Signed-off-by: Saeed Bishara <saeed at marvell.com>
---
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index c428348..16f6691 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -51,6 +51,14 @@ static struct mvsdio_platform_data db88f6281_mvsdio_data = {
 };
 
 static unsigned int db88f6281_mpp_config[] __initdata = {
+	MPP0_NF_IO2,
+	MPP1_NF_IO3,
+	MPP2_NF_IO4,
+	MPP3_NF_IO5,
+	MPP4_NF_IO6,
+	MPP5_NF_IO7,
+	MPP18_NF_IO0,
+	MPP19_NF_IO1,
 	MPP37_GPIO,
 	MPP38_GPIO,
 	0
-- 
1.6.0.4



From benjamin.zores at alcatel-lucent.com  Tue Jun  8 07:43:44 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Tue, 08 Jun 2010 13:43:44 +0200
Subject: [PATCH 3/3 v4] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <1275996094-16929-1-git-send-email-saeed@marvell.com>
References: <AANLkTilEM81aUCdIaTyN1s8es6LMETuMOGXh3a67sWgf@mail.gmail.com>
	<1275996094-16929-1-git-send-email-saeed@marvell.com>
Message-ID: <4C0E2CF0.3050307@alcatel-lucent.com>

On 08/06/2010 13:21, Saeed Bishara wrote:
> @@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
>   		      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
>   	setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
>   		      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
> +	setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
> +		      TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
> +	setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
> +		      TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
>
>    

I'd have used an id, and incremented it at each setup_cpu_win() call.
Also only doing the last 2 calls on 6282.

>   	/* Make sure those units are accessible */
> -	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);
> +	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
>
>    

Why not (pseudo code):

int flags = curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0;
if (6282) flags |= CGC_PEX1;
writel(flags, ...);

> +	/* For PCIe 1: first shutdown the phy */
> +	if (dev == MV88F6282_DEV_ID) {
> +		if (!(kirkwood_clk_ctrl&  CGC_PEX1)) {
> +			writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
> +			while (1)
> +				if (readl(PCIE1_STATUS)&  0x1)
> +					break;
> +			writel(readl(PCIE1_LINK_CTRL)&  ~0x10, PCIE1_LINK_CTRL);
> +		}
> +	} else  /* keep this bit set for devices that don't have PCIe1 */
> +		kirkwood_clk_ctrl |= CGC_PEX1;
>
>    

the else part is useless with the proposal above i guess.

Except from that, when using your patch I was unable to boot kernel 
anymore on 6281 boards.
I have a quite similar patch that however uses preinit() calls in pcie.c 
for the board to boot again.

I'd like to send it but I'm in discussion with your company whether or 
not I'm allowed to do so.
In the same way I do have patches for MPP and 2nd TWSI interface support 
if it may help.

Ben




From linux at arm.linux.org.uk  Tue Jun  8 07:58:32 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 8 Jun 2010 12:58:32 +0100
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <alpine.LFD.2.00.1006041418390.22319@xanadu.home>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
Message-ID: <20100608115832.GB25370@n2100.arm.linux.org.uk>

On Fri, Jun 04, 2010 at 04:51:24PM -0400, Nicolas Pitre wrote:
> Linus wants something to be done about the current defconfig mess which 
> is perfectly legitimate.  He even suggested a possible solution.  I 
> don't think he'll simply drop those defconfig files if we demonstrate 
> that we're taking action to fix the actual problem.

However, having a set of patches which combine a load of defconfig
files into one is not going to solve the problem.

If you're hypothesis that Linus is only looking at the diffstat, then
what are patches to combine the defconfigs going to do?  It's going
to create lots of noise in arch/arm/configs/ - which is precisely what
Linus is complaining about.  In fact, patch-wise it's going to create
an extremely large patch.  And if we do this time and time again while
progressively reducing the defconfigs.  No, this isn't the answer -
it's only going to make the problem worse.

I believe the only acceptable solution is to get an alterative method
in place - no matter what it is - and remove the all but one of the
defconfig files from the mainline kernel.  _And_, most importantly,
kautobuild needs to be fixed so that we still get build coverage.

The loss of kautobuild is a major concern here, and I believe it trumps
everything else for the next merge window.  Kautobuild is an extremely
important resource that we simply can not afford to lose.


From tony at atomide.com  Tue Jun  8 08:03:05 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 08 Jun 2010 15:03:05 +0300
Subject: [PATCH 0/5] omap fixes for 2.6.35-rc2
Message-ID: <20100608120104.24902.36055.stgit@baageli.muru.com>

Hi all,

Here are few omap fixes for review. I've moved anything that's not
absolutely needed as a fix into for-next as requested by Linus.

Regards,

Tony

---

Amit Kucheria (1):
      omap: fix build failure due to missing include dma-mapping.h

Kevin Hilman (2):
      omap: GPIO: fix auto-disable of debounce clock
      OMAP3: PM: fix IO daisy chain enable to use PM_WKEN reg

Santosh Shilimkar (1):
      omap: Stalker board: switch over to gpio_set_debounce

Tero Kristo (1):
      omap: DMTIMER: Ack pending interrupt always when stopping a timer


 arch/arm/mach-omap2/board-omap3stalker.c |    4 +---
 arch/arm/mach-omap2/pm34xx.c             |    4 ++--
 arch/arm/mach-omap2/usb-ehci.c           |    2 ++
 arch/arm/plat-omap/dmtimer.c             |    6 +++---
 arch/arm/plat-omap/gpio.c                |    1 +
 5 files changed, 9 insertions(+), 8 deletions(-)

-- 
Signature


From tony at atomide.com  Tue Jun  8 08:03:13 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 08 Jun 2010 15:03:13 +0300
Subject: [PATCH 1/5] omap: fix build failure due to missing include
	dma-mapping.h
In-Reply-To: <20100608120104.24902.36055.stgit@baageli.muru.com>
References: <20100608120104.24902.36055.stgit@baageli.muru.com>
Message-ID: <20100608120313.24902.69896.stgit@baageli.muru.com>

From: Amit Kucheria <amit.kucheria at canonical.com>

Fixes following error,

CC      arch/arm/mach-omap2/usb-ehci.o
arch/arm/mach-omap2/usb-ehci.c:263: error: implicit declaration of function
'DMA_BIT_MASK'
arch/arm/mach-omap2/usb-ehci.c:263: error: initializer element is not constant
make[1]: *** [arch/arm/mach-omap2/usb-ehci.o] Error 1

Signed-off-by: Amit Kucheria <amit.kucheria at canonical.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/usb-ehci.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
index c68f799..d72d1ac 100644
--- a/arch/arm/mach-omap2/usb-ehci.c
+++ b/arch/arm/mach-omap2/usb-ehci.c
@@ -20,6 +20,8 @@
 #include <linux/delay.h>
 #include <linux/platform_device.h>
 #include <linux/clk.h>
+#include <linux/dma-mapping.h>
+
 #include <asm/io.h>
 #include <plat/mux.h>
 



From tony at atomide.com  Tue Jun  8 08:03:25 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 08 Jun 2010 15:03:25 +0300
Subject: [PATCH 2/5] omap: Stalker board: switch over to gpio_set_debounce
In-Reply-To: <20100608120104.24902.36055.stgit@baageli.muru.com>
References: <20100608120104.24902.36055.stgit@baageli.muru.com>
Message-ID: <20100608120325.24902.42622.stgit@baageli.muru.com>

From: Santosh Shilimkar <santosh.shilimkar at ti.com>

With latest linus's tip, omap3_defconfig is broken.

 LD      init/built-in.o
  LD      .tmp_vmlinux1
arch/arm/mach-omap2/built-in.o: In function `ads7846_dev_init':
linux-2.6/arch/arm/mach-omap2/board-omap3stalker.c:542: undefined reference to `omap_set_gpio_debounce'
linux-2.6/arch/arm/mach-omap2/board-omap3stalker.c:543: undefined reference to `omap_set_gpio_debounce_time'
make: *** [.tmp_vmlinux1] Error 1

>From the commit 48feb337475a ( arm: omap: switch over to gpio_set_debounce),
board-omap3stalker.c seems to be missed out or got merged later.
The patch was to remove omap-specific implementations for gpio debouncing
in favor of gpiolib function.

Cc: Felipe Balbi <felipe.balbi at nokia.com>
Cc: Kevin Hilman <khilman at deeprootsystems.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-omap3stalker.c |    4 +---
 1 files changed, 1 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index f848ba8..a04cffd 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -538,9 +538,7 @@ static void ads7846_dev_init(void)
 		printk(KERN_ERR "can't get ads7846 pen down GPIO\n");
 
 	gpio_direction_input(OMAP3_STALKER_TS_GPIO);
-
-	omap_set_gpio_debounce(OMAP3_STALKER_TS_GPIO, 1);
-	omap_set_gpio_debounce_time(OMAP3_STALKER_TS_GPIO, 0xa);
+	gpio_set_debounce(OMAP3_STALKER_TS_GPIO, 310);
 }
 
 static int ads7846_get_pendown_state(void)



From tony at atomide.com  Tue Jun  8 08:03:31 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 08 Jun 2010 15:03:31 +0300
Subject: [PATCH 3/5] omap: DMTIMER: Ack pending interrupt always when stopping
	a timer
In-Reply-To: <20100608120104.24902.36055.stgit@baageli.muru.com>
References: <20100608120104.24902.36055.stgit@baageli.muru.com>
Message-ID: <20100608120331.24902.90256.stgit@baageli.muru.com>

From: Tero Kristo <tero.kristo at nokia.com>

The kernel timer queue is being run currently from a GP timer running in a one
shot mode, which works in a way that when it expires, it will also stop.
Usually during this situation, the interrupt handler will ack the interrupt,
load a new value to the timer and start it again. During suspend, the
situation is slightly different, as we disable interrupts just before
timekeeping is suspended, which leaves a small window where the timer can
expire before it is stopped, and will leave the interrupt flag pending.
This pending interrupt will prevent ARM sleep entry, thus now we ack it always
when we are attempting to stop a timer.

Signed-off-by: Tero Kristo <tero.kristo at nokia.com>
Acked-by: Kevin Hilman <khilman at deeprootsystems.com>
[tony at atomide.com: removed the ifdef to make the patch cover omap1 also]
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/plat-omap/dmtimer.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index c64875f..44bafda 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -541,11 +541,11 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer)
 		  * timer is stopped
 		  */
 		udelay(3500000 / clk_get_rate(timer->fclk) + 1);
-		/* Ack possibly pending interrupt */
-		omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
-				OMAP_TIMER_INT_OVERFLOW);
 #endif
 	}
+	/* Ack possibly pending interrupt */
+	omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
+			OMAP_TIMER_INT_OVERFLOW);
 }
 EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
 



From tony at atomide.com  Tue Jun  8 08:03:35 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 08 Jun 2010 15:03:35 +0300
Subject: [PATCH 4/5] omap: GPIO: fix auto-disable of debounce clock
In-Reply-To: <20100608120104.24902.36055.stgit@baageli.muru.com>
References: <20100608120104.24902.36055.stgit@baageli.muru.com>
Message-ID: <20100608120335.24902.28296.stgit@baageli.muru.com>

From: Kevin Hilman <khilman at deeprootsystems.com>

The addition of the new debounce code (commit
168ef3d9a56bd8bffe0ef4189c450888b4aefefe) broke the auto-disable of
debounce clocks on idle by forgetting to update the debounce clock
enable mask.

Add back the updating of bank->dbck_enable_mask so debounce clocks are
auto-disabled.

Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/plat-omap/gpio.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 393e921..9b7e354 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -673,6 +673,7 @@ static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
 		if (cpu_is_omap34xx() || cpu_is_omap44xx())
 			clk_disable(bank->dbck);
 	}
+	bank->dbck_enable_mask = val;
 
 	__raw_writel(val, reg);
 }



From tony at atomide.com  Tue Jun  8 08:03:40 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 08 Jun 2010 15:03:40 +0300
Subject: [PATCH 5/5] OMAP3: PM: fix IO daisy chain enable to use PM_WKEN reg
In-Reply-To: <20100608120104.24902.36055.stgit@baageli.muru.com>
References: <20100608120104.24902.36055.stgit@baageli.muru.com>
Message-ID: <20100608120340.24902.73479.stgit@baageli.muru.com>

From: Kevin Hilman <khilman at deeprootsystems.com>

Checking to se if the IO daisy chain is enabled should be checking the
PM_WKEN register, not the PM_WKST register.  Reading PM_WKST tells us
if an event occurred, not whether or not it is enabled.

Apparently, we've been lucky until now in that a pending event has not
been there during enable.  However, on 3630/Zoom3, I noticed because
of the WARN that this timeout was always happening.

Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/pm34xx.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2e96771..b88737f 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -99,7 +99,7 @@ static void omap3_enable_io_chain(void)
 		/* Do a readback to assure write has been done */
 		prm_read_mod_reg(WKUP_MOD, PM_WKEN);
 
-		while (!(prm_read_mod_reg(WKUP_MOD, PM_WKST) &
+		while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
 			 OMAP3430_ST_IO_CHAIN_MASK)) {
 			timeout++;
 			if (timeout > 1000) {
@@ -108,7 +108,7 @@ static void omap3_enable_io_chain(void)
 				return;
 			}
 			prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
-					     WKUP_MOD, PM_WKST);
+					     WKUP_MOD, PM_WKEN);
 		}
 	}
 }



From saeed.bishara at gmail.com  Tue Jun  8 08:20:56 2010
From: saeed.bishara at gmail.com (saeed bishara)
Date: Tue, 8 Jun 2010 15:20:56 +0300
Subject: [PATCH 3/3 v4] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <4C0E2CF0.3050307@alcatel-lucent.com>
References: <AANLkTilEM81aUCdIaTyN1s8es6LMETuMOGXh3a67sWgf@mail.gmail.com>
	<1275996094-16929-1-git-send-email-saeed@marvell.com>
	<4C0E2CF0.3050307@alcatel-lucent.com>
Message-ID: <AANLkTilq6R6_9aEBZ66mSnMe5GsOLYDqP4qbQQHJsb8b@mail.gmail.com>

On Tue, Jun 8, 2010 at 2:43 PM, Benjamin Zores
<benjamin.zores at alcatel-lucent.com> wrote:
> On 08/06/2010 13:21, Saeed Bishara wrote:
>>
>> @@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
>> ? ? ? ? ? ? ? ? ? ? ?TARGET_PCIE, ATTR_PCIE_IO,
>> KIRKWOOD_PCIE_IO_BUS_BASE);
>> ? ? ? ?setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE,
>> KIRKWOOD_PCIE_MEM_SIZE,
>> ? ? ? ? ? ? ? ? ? ? ?TARGET_PCIE, ATTR_PCIE_MEM,
>> KIRKWOOD_PCIE_MEM_BUS_BASE);
>> + ? ? ? setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE,
>> KIRKWOOD_PCIE1_IO_SIZE,
>> + ? ? ? ? ? ? ? ? ? ? TARGET_PCIE, ATTR_PCIE1_IO,
>> KIRKWOOD_PCIE1_IO_BUS_BASE);
>> + ? ? ? setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE,
>> KIRKWOOD_PCIE1_MEM_SIZE,
>> + ? ? ? ? ? ? ? ? ? ? TARGET_PCIE, ATTR_PCIE1_MEM,
>> KIRKWOOD_PCIE1_MEM_BUS_BASE);
>>
>>
>
> I'd have used an id, and incremented it at each setup_cpu_win() call.
> Also only doing the last 2 calls on 6282.
>
>> ? ? ? ?/* Make sure those units are accessible */
>> - ? ? ? writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0,
>> CLOCK_GATING_CTRL);
>> + ? ? ? writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1,
>> CLOCK_GATING_CTRL);
>>
>>
>
> Why not (pseudo code):
>
> int flags = curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0;
> if (6282) flags |= CGC_PEX1;
> writel(flags, ...);
>
>> + ? ? ? /* For PCIe 1: first shutdown the phy */
>> + ? ? ? if (dev == MV88F6282_DEV_ID) {
>> + ? ? ? ? ? ? ? if (!(kirkwood_clk_ctrl& ?CGC_PEX1)) {
>> + ? ? ? ? ? ? ? ? ? ? ? writel(readl(PCIE1_LINK_CTRL) | 0x10,
>> PCIE1_LINK_CTRL);
>> + ? ? ? ? ? ? ? ? ? ? ? while (1)
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? if (readl(PCIE1_STATUS)& ?0x1)
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? break;
>> + ? ? ? ? ? ? ? ? ? ? ? writel(readl(PCIE1_LINK_CTRL)& ?~0x10,
>> PCIE1_LINK_CTRL);
>> + ? ? ? ? ? ? ? }
>> + ? ? ? } else ?/* keep this bit set for devices that don't have PCIe1 */
>> + ? ? ? ? ? ? ? kirkwood_clk_ctrl |= CGC_PEX1;
>>
>>
>
> the else part is useless with the proposal above i guess.
>
> Except from that, when using your patch I was unable to boot kernel anymore
> on 6281 boards.
can you try the patch I send regarding nand mpps?


From tony at atomide.com  Tue Jun  8 08:31:03 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 8 Jun 2010 15:31:03 +0300
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100608115832.GB25370@n2100.arm.linux.org.uk>
References: <alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
Message-ID: <20100608123102.GT15515@atomide.com>

* Russell King - ARM Linux <linux at arm.linux.org.uk> [100608 14:53]:
> On Fri, Jun 04, 2010 at 04:51:24PM -0400, Nicolas Pitre wrote:
> > Linus wants something to be done about the current defconfig mess which 
> > is perfectly legitimate.  He even suggested a possible solution.  I 
> > don't think he'll simply drop those defconfig files if we demonstrate 
> > that we're taking action to fix the actual problem.
> 
> However, having a set of patches which combine a load of defconfig
> files into one is not going to solve the problem.
> 
> If you're hypothesis that Linus is only looking at the diffstat, then
> what are patches to combine the defconfigs going to do?  It's going
> to create lots of noise in arch/arm/configs/ - which is precisely what
> Linus is complaining about.  In fact, patch-wise it's going to create
> an extremely large patch.  And if we do this time and time again while
> progressively reducing the defconfigs.  No, this isn't the answer -
> it's only going to make the problem worse.
> 
> I believe the only acceptable solution is to get an alterative method
> in place - no matter what it is - and remove the all but one of the
> defconfig files from the mainline kernel.  _And_, most importantly,
> kautobuild needs to be fixed so that we still get build coverage.
> 
> The loss of kautobuild is a major concern here, and I believe it trumps
> everything else for the next merge window.  Kautobuild is an extremely
> important resource that we simply can not afford to lose.

How about the following strategy for the next merge window:

- Update kautobuild to temporarily host the current defconfigs

- Remove all the arm defconfigs except one

Then over the next few merge cycles:

- Make the ARM platform specific Kconfig or similar option to work

- Drop the old defconfigs from kautobuild once we have the new solution

Then over yet unknown lenght of time:

- Work towards building in more features (TLS/SMP/VFPvX) into the same kernel

- Work towards building in multiple ARM platforms into the same kernel

Regards,

Tony


From benjamin.zores at alcatel-lucent.com  Tue Jun  8 08:43:24 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Tue, 08 Jun 2010 14:43:24 +0200
Subject: [PATCH 3/3 v4] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <AANLkTilq6R6_9aEBZ66mSnMe5GsOLYDqP4qbQQHJsb8b@mail.gmail.com>
References: <AANLkTilEM81aUCdIaTyN1s8es6LMETuMOGXh3a67sWgf@mail.gmail.com>	<1275996094-16929-1-git-send-email-saeed@marvell.com>	<4C0E2CF0.3050307@alcatel-lucent.com>
	<AANLkTilq6R6_9aEBZ66mSnMe5GsOLYDqP4qbQQHJsb8b@mail.gmail.com>
Message-ID: <4C0E3AEC.8040304@alcatel-lucent.com>

On 08/06/2010 14:20, saeed bishara wrote:
> On Tue, Jun 8, 2010 at 2:43 PM, Benjamin Zores
> <benjamin.zores at alcatel-lucent.com>  wrote:
>    
>> On 08/06/2010 13:21, Saeed Bishara wrote:
>>      
>>> @@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
>>>                       TARGET_PCIE, ATTR_PCIE_IO,
>>> KIRKWOOD_PCIE_IO_BUS_BASE);
>>>         setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE,
>>> KIRKWOOD_PCIE_MEM_SIZE,
>>>                       TARGET_PCIE, ATTR_PCIE_MEM,
>>> KIRKWOOD_PCIE_MEM_BUS_BASE);
>>> +       setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE,
>>> KIRKWOOD_PCIE1_IO_SIZE,
>>> +                     TARGET_PCIE, ATTR_PCIE1_IO,
>>> KIRKWOOD_PCIE1_IO_BUS_BASE);
>>> +       setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE,
>>> KIRKWOOD_PCIE1_MEM_SIZE,
>>> +                     TARGET_PCIE, ATTR_PCIE1_MEM,
>>> KIRKWOOD_PCIE1_MEM_BUS_BASE);
>>>
>>>
>>>        
>> I'd have used an id, and incremented it at each setup_cpu_win() call.
>> Also only doing the last 2 calls on 6282.
>>
>>      
>>>         /* Make sure those units are accessible */
>>> -       writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0,
>>> CLOCK_GATING_CTRL);
>>> +       writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1,
>>> CLOCK_GATING_CTRL);
>>>
>>>
>>>        
>> Why not (pseudo code):
>>
>> int flags = curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0;
>> if (6282) flags |= CGC_PEX1;
>> writel(flags, ...);
>>
>>      
>>> +       /* For PCIe 1: first shutdown the phy */
>>> +       if (dev == MV88F6282_DEV_ID) {
>>> +               if (!(kirkwood_clk_ctrl&    CGC_PEX1)) {
>>> +                       writel(readl(PCIE1_LINK_CTRL) | 0x10,
>>> PCIE1_LINK_CTRL);
>>> +                       while (1)
>>> +                               if (readl(PCIE1_STATUS)&    0x1)
>>> +                                       break;
>>> +                       writel(readl(PCIE1_LINK_CTRL)&    ~0x10,
>>> PCIE1_LINK_CTRL);
>>> +               }
>>> +       } else  /* keep this bit set for devices that don't have PCIe1 */
>>> +               kirkwood_clk_ctrl |= CGC_PEX1;
>>>
>>>
>>>        
>> the else part is useless with the proposal above i guess.
>>
>> Except from that, when using your patch I was unable to boot kernel anymore
>> on 6281 boards.
>>      
> can you try the patch I send regarding nand mpps?
>    

Unfortunately no, I'm running on OpenRD currently.

Ben


From davidjon at xenontk.org  Tue Jun  8 08:43:54 2010
From: davidjon at xenontk.org (David John)
Date: Tue, 08 Jun 2010 18:13:54 +0530
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100608115832.GB25370@n2100.arm.linux.org.uk>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>	<4C083BCF.2060500@bluewatersys.com>	<201006040310.15019.marek.vasut@gmail.com>	<4C0853E1.1080005@bluewatersys.com>	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>	<20100604061034.GI6499@atomide.com>	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
Message-ID: <4C0E3B0A.4040304@xenontk.org>

On 06/08/2010 05:28 PM, Russell King - ARM Linux wrote:
> On Fri, Jun 04, 2010 at 04:51:24PM -0400, Nicolas Pitre wrote:
>> Linus wants something to be done about the current defconfig mess which 
>> is perfectly legitimate.  He even suggested a possible solution.  I 
>> don't think he'll simply drop those defconfig files if we demonstrate 
>> that we're taking action to fix the actual problem.
> 
> However, having a set of patches which combine a load of defconfig
> files into one is not going to solve the problem.
> 
> If you're hypothesis that Linus is only looking at the diffstat, then
> what are patches to combine the defconfigs going to do?  It's going
> to create lots of noise in arch/arm/configs/ - which is precisely what
> Linus is complaining about.  In fact, patch-wise it's going to create
> an extremely large patch.  And if we do this time and time again while
> progressively reducing the defconfigs.  No, this isn't the answer -
> it's only going to make the problem worse.
> 

Hi,

I don't know if this is acceptable and it's just a suggestion - Once the
defconfig 'mess' is fixed, why not move it to Documentation/arm/configs
or somewhere similar where it won't interfere with the arch diffstat?

Regards,
David.


From eric.y.miao at gmail.com  Tue Jun  8 08:43:13 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 8 Jun 2010 20:43:13 +0800
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100608123102.GT15515@atomide.com>
References: <alpine.LFD.2.00.1006031829020.24526@xanadu.home> 
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com> 
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com> 
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com> 
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com> 
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk> 
	<20100608123102.GT15515@atomide.com>
Message-ID: <AANLkTilyaRYigz2LoirclkNHyj3g3CUogM6OmnpUfM4M@mail.gmail.com>

On Tue, Jun 8, 2010 at 8:31 PM, Tony Lindgren <tony at atomide.com> wrote:
> * Russell King - ARM Linux <linux at arm.linux.org.uk> [100608 14:53]:
>> On Fri, Jun 04, 2010 at 04:51:24PM -0400, Nicolas Pitre wrote:
>> > Linus wants something to be done about the current defconfig mess which
>> > is perfectly legitimate. ?He even suggested a possible solution. ?I
>> > don't think he'll simply drop those defconfig files if we demonstrate
>> > that we're taking action to fix the actual problem.
>>
>> However, having a set of patches which combine a load of defconfig
>> files into one is not going to solve the problem.
>>
>> If you're hypothesis that Linus is only looking at the diffstat, then
>> what are patches to combine the defconfigs going to do? ?It's going
>> to create lots of noise in arch/arm/configs/ - which is precisely what
>> Linus is complaining about. ?In fact, patch-wise it's going to create
>> an extremely large patch. ?And if we do this time and time again while
>> progressively reducing the defconfigs. ?No, this isn't the answer -
>> it's only going to make the problem worse.
>>
>> I believe the only acceptable solution is to get an alterative method
>> in place - no matter what it is - and remove the all but one of the
>> defconfig files from the mainline kernel. ?_And_, most importantly,
>> kautobuild needs to be fixed so that we still get build coverage.
>>
>> The loss of kautobuild is a major concern here, and I believe it trumps
>> everything else for the next merge window. ?Kautobuild is an extremely
>> important resource that we simply can not afford to lose.
>
> How about the following strategy for the next merge window:
>
> - Update kautobuild to temporarily host the current defconfigs
>
> - Remove all the arm defconfigs except one
>

This is actually a bit unfair and brutally. The number of defconfig is not
an ARM _only_ problem, although it's a bit significant on ARM due to
the diversity.

ycmiao at macbook-lucid:~/kernel/linux-2.6$ find arch/ -name
"*_defconfig" | grep "arch/sh" | wc -l
50
ycmiao at macbook-lucid:~/kernel/linux-2.6$ find arch/ -name
"*_defconfig" | grep "arch/powerpc" | wc -l
100
ycmiao at macbook-lucid:~/kernel/linux-2.6$ find arch/ -name
"*_defconfig" | grep "arch/mips" | wc -l
47
ycmiao at macbook-lucid:~/kernel/linux-2.6$ find arch/ -name
"*_defconfig" | grep "arch/blackfin" | wc -l
24

Removing all the _defconfig will anyway generate a super BIG patch as
well, which is also going to generate a lot noise in diffstat.

Just wondering if a migration path is possible. Does anyone seriously think
about the solution Linus proposed and maybe we can have an implementation
and have all defconfig going that way before they are completely purged?

> Then over the next few merge cycles:
>
> - Make the ARM platform specific Kconfig or similar option to work
>
> - Drop the old defconfigs from kautobuild once we have the new solution
>
> Then over yet unknown lenght of time:
>
> - Work towards building in more features (TLS/SMP/VFPvX) into the same kernel
>
> - Work towards building in multiple ARM platforms into the same kernel
>
> Regards,
>
> Tony
>


From nico at fluxnic.net  Tue Jun  8 08:44:52 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 08 Jun 2010 08:44:52 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100608115832.GB25370@n2100.arm.linux.org.uk>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.00.1006080839240.30664@xanadu.home>

On Tue, 8 Jun 2010, Russell King - ARM Linux wrote:

> On Fri, Jun 04, 2010 at 04:51:24PM -0400, Nicolas Pitre wrote:
> > Linus wants something to be done about the current defconfig mess which 
> > is perfectly legitimate.  He even suggested a possible solution.  I 
> > don't think he'll simply drop those defconfig files if we demonstrate 
> > that we're taking action to fix the actual problem.
> 
> However, having a set of patches which combine a load of defconfig
> files into one is not going to solve the problem.

It is an absolutely needed first step.

> If you're hypothesis that Linus is only looking at the diffstat, then
> what are patches to combine the defconfigs going to do?  It's going
> to create lots of noise in arch/arm/configs/ - which is precisely what
> Linus is complaining about.  In fact, patch-wise it's going to create
> an extremely large patch.  And if we do this time and time again while
> progressively reducing the defconfigs.  No, this isn't the answer -
> it's only going to make the problem worse.

I don't think that has to reach Linus' tree.  But that greatly helps 
figuring out a common config pattern that can be applied to a group of 
targets.

> I believe the only acceptable solution is to get an alterative method
> in place - no matter what it is - and remove the all but one of the
> defconfig files from the mainline kernel.  _And_, most importantly,
> kautobuild needs to be fixed so that we still get build coverage.

I personally think that your suggestion using STD_CONFIG or similar is a 
good way forward.  Specific needs for given targets can then be 
expressed along with the Kconfig menu item describing that target.


Nicolas


From eric.y.miao at gmail.com  Tue Jun  8 08:44:57 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 8 Jun 2010 20:44:57 +0800
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C0E3B0A.4040304@xenontk.org>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk> 
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com> 
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com> 
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com> 
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com> 
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com> 
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk> 
	<4C0E3B0A.4040304@xenontk.org>
Message-ID: <AANLkTimVC9ceX3cO5bS81yVvKYcrce1BQjVv-AGQ3Yp6@mail.gmail.com>

On Tue, Jun 8, 2010 at 8:43 PM, David John <davidjon at xenontk.org> wrote:
> On 06/08/2010 05:28 PM, Russell King - ARM Linux wrote:
>> On Fri, Jun 04, 2010 at 04:51:24PM -0400, Nicolas Pitre wrote:
>>> Linus wants something to be done about the current defconfig mess which
>>> is perfectly legitimate. ?He even suggested a possible solution. ?I
>>> don't think he'll simply drop those defconfig files if we demonstrate
>>> that we're taking action to fix the actual problem.
>>
>> However, having a set of patches which combine a load of defconfig
>> files into one is not going to solve the problem.
>>
>> If you're hypothesis that Linus is only looking at the diffstat, then
>> what are patches to combine the defconfigs going to do? ?It's going
>> to create lots of noise in arch/arm/configs/ - which is precisely what
>> Linus is complaining about. ?In fact, patch-wise it's going to create
>> an extremely large patch. ?And if we do this time and time again while
>> progressively reducing the defconfigs. ?No, this isn't the answer -
>> it's only going to make the problem worse.
>>
>
> Hi,
>
> I don't know if this is acceptable and it's just a suggestion - Once the
> defconfig 'mess' is fixed, why not move it to Documentation/arm/configs
> or somewhere similar where it won't interfere with the arch diffstat?
>

That's doable but my understanding is once it is fixed, the configs each
platform needs are actually encoded by the fix already. And the git history
can serve as a reference.


From linux at arm.linux.org.uk  Tue Jun  8 08:49:13 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 8 Jun 2010 13:49:13 +0100
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <AANLkTilyaRYigz2LoirclkNHyj3g3CUogM6OmnpUfM4M@mail.gmail.com>
References: <201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<20100608123102.GT15515@atomide.com>
	<AANLkTilyaRYigz2LoirclkNHyj3g3CUogM6OmnpUfM4M@mail.gmail.com>
Message-ID: <20100608124913.GC25370@n2100.arm.linux.org.uk>

On Tue, Jun 08, 2010 at 08:43:13PM +0800, Eric Miao wrote:
> Just wondering if a migration path is possible. Does anyone seriously think
> about the solution Linus proposed and maybe we can have an implementation
> and have all defconfig going that way before they are completely purged?

Doesn't select from an 'm' symbol cause the target of the select to end
up being 'm' ?  If yes, we have a way to solve this today.

config ARM_PLATFORM_FOO
	bool "Default configuration for FOO"
	select ARCH_FOO
	select VIDEO_WHATEVER

config ARM_PLATFORM_FOO_MOD
	tristate
	default m if ARM_PLATFORM_FOO
	select I2C
	select SPI

etc.  We just need to be very careful about dependencies for things like
I2C, SPI, etc.


From saeed.bishara at gmail.com  Tue Jun  8 08:49:43 2010
From: saeed.bishara at gmail.com (saeed bishara)
Date: Tue, 8 Jun 2010 15:49:43 +0300
Subject: [PATCH 3/3 v4] [ARM] Kirkwood: add support for PCIe1
In-Reply-To: <4C0E3AEC.8040304@alcatel-lucent.com>
References: <AANLkTilEM81aUCdIaTyN1s8es6LMETuMOGXh3a67sWgf@mail.gmail.com>
	<1275996094-16929-1-git-send-email-saeed@marvell.com>
	<4C0E2CF0.3050307@alcatel-lucent.com>
	<AANLkTilq6R6_9aEBZ66mSnMe5GsOLYDqP4qbQQHJsb8b@mail.gmail.com>
	<4C0E3AEC.8040304@alcatel-lucent.com>
Message-ID: <AANLkTikCo3oDxCiBrIMYjTlbvvvSt0ugR8MvsJQ0lPdn@mail.gmail.com>

On Tue, Jun 8, 2010 at 3:43 PM, Benjamin Zores
<benjamin.zores at alcatel-lucent.com> wrote:
> On 08/06/2010 14:20, saeed bishara wrote:
>>
>> On Tue, Jun 8, 2010 at 2:43 PM, Benjamin Zores
>> <benjamin.zores at alcatel-lucent.com> ?wrote:
>>
>>>
>>> On 08/06/2010 13:21, Saeed Bishara wrote:
>>>
>>>>
>>>> @@ -106,17 +108,21 @@ void __init kirkwood_setup_cpu_mbus(void)
>>>> ? ? ? ? ? ? ? ? ? ? ?TARGET_PCIE, ATTR_PCIE_IO,
>>>> KIRKWOOD_PCIE_IO_BUS_BASE);
>>>> ? ? ? ?setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE,
>>>> KIRKWOOD_PCIE_MEM_SIZE,
>>>> ? ? ? ? ? ? ? ? ? ? ?TARGET_PCIE, ATTR_PCIE_MEM,
>>>> KIRKWOOD_PCIE_MEM_BUS_BASE);
>>>> + ? ? ? setup_cpu_win(2, KIRKWOOD_PCIE1_IO_PHYS_BASE,
>>>> KIRKWOOD_PCIE1_IO_SIZE,
>>>> + ? ? ? ? ? ? ? ? ? ? TARGET_PCIE, ATTR_PCIE1_IO,
>>>> KIRKWOOD_PCIE1_IO_BUS_BASE);
>>>> + ? ? ? setup_cpu_win(3, KIRKWOOD_PCIE1_MEM_PHYS_BASE,
>>>> KIRKWOOD_PCIE1_MEM_SIZE,
>>>> + ? ? ? ? ? ? ? ? ? ? TARGET_PCIE, ATTR_PCIE1_MEM,
>>>> KIRKWOOD_PCIE1_MEM_BUS_BASE);
>>>>
>>>>
>>>>
>>>
>>> I'd have used an id, and incremented it at each setup_cpu_win() call.
>>> Also only doing the last 2 calls on 6282.
>>>
>>>
>>>>
>>>> ? ? ? ?/* Make sure those units are accessible */
>>>> - ? ? ? writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0,
>>>> CLOCK_GATING_CTRL);
>>>> + ? ? ? writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1,
>>>> CLOCK_GATING_CTRL);
>>>>
>>>>
>>>>
>>>
>>> Why not (pseudo code):
>>>
>>> int flags = curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0;
>>> if (6282) flags |= CGC_PEX1;
>>> writel(flags, ...);
>>>
>>>
>>>>
>>>> + ? ? ? /* For PCIe 1: first shutdown the phy */
>>>> + ? ? ? if (dev == MV88F6282_DEV_ID) {
>>>> + ? ? ? ? ? ? ? if (!(kirkwood_clk_ctrl& ? ?CGC_PEX1)) {
>>>> + ? ? ? ? ? ? ? ? ? ? ? writel(readl(PCIE1_LINK_CTRL) | 0x10,
>>>> PCIE1_LINK_CTRL);
>>>> + ? ? ? ? ? ? ? ? ? ? ? while (1)
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? if (readl(PCIE1_STATUS)& ? ?0x1)
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? break;
>>>> + ? ? ? ? ? ? ? ? ? ? ? writel(readl(PCIE1_LINK_CTRL)& ? ?~0x10,
>>>> PCIE1_LINK_CTRL);
>>>> + ? ? ? ? ? ? ? }
>>>> + ? ? ? } else ?/* keep this bit set for devices that don't have PCIe1
>>>> */
>>>> + ? ? ? ? ? ? ? kirkwood_clk_ctrl |= CGC_PEX1;
>>>>
>>>>
>>>>
>>>
>>> the else part is useless with the proposal above i guess.
>>>
>>> Except from that, when using your patch I was unable to boot kernel
>>> anymore
>>> on 6281 boards.
>>>
>>
>> can you try the patch I send regarding nand mpps?
>>
>
> Unfortunately no, I'm running on OpenRD currently.
does it boot if you remove the kirkwood_nand_init?
> Ben
>


From nico at fluxnic.net  Tue Jun  8 08:50:39 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 08 Jun 2010 08:50:39 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C0E3B0A.4040304@xenontk.org>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>
	<4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<4C0E3B0A.4040304@xenontk.org>
Message-ID: <alpine.LFD.2.00.1006080849540.30664@xanadu.home>

On Tue, 8 Jun 2010, David John wrote:

> On 06/08/2010 05:28 PM, Russell King - ARM Linux wrote:
> > On Fri, Jun 04, 2010 at 04:51:24PM -0400, Nicolas Pitre wrote:
> >> Linus wants something to be done about the current defconfig mess which 
> >> is perfectly legitimate.  He even suggested a possible solution.  I 
> >> don't think he'll simply drop those defconfig files if we demonstrate 
> >> that we're taking action to fix the actual problem.
> > 
> > However, having a set of patches which combine a load of defconfig
> > files into one is not going to solve the problem.
> > 
> > If you're hypothesis that Linus is only looking at the diffstat, then
> > what are patches to combine the defconfigs going to do?  It's going
> > to create lots of noise in arch/arm/configs/ - which is precisely what
> > Linus is complaining about.  In fact, patch-wise it's going to create
> > an extremely large patch.  And if we do this time and time again while
> > progressively reducing the defconfigs.  No, this isn't the answer -
> > it's only going to make the problem worse.
> > 
> 
> Hi,
> 
> I don't know if this is acceptable and it's just a suggestion - Once the
> defconfig 'mess' is fixed, why not move it to Documentation/arm/configs
> or somewhere similar where it won't interfere with the arch diffstat?

This would only _move_ the problem instead of fixing it.


Nicolas


From linux at arm.linux.org.uk  Tue Jun  8 08:50:53 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 8 Jun 2010 13:50:53 +0100
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <alpine.LFD.2.00.1006080839240.30664@xanadu.home>
References: <4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006080839240.30664@xanadu.home>
Message-ID: <20100608125053.GD25370@n2100.arm.linux.org.uk>

On Tue, Jun 08, 2010 at 08:44:52AM -0400, Nicolas Pitre wrote:
> On Tue, 8 Jun 2010, Russell King - ARM Linux wrote:
> > I believe the only acceptable solution is to get an alterative method
> > in place - no matter what it is - and remove the all but one of the
> > defconfig files from the mainline kernel.  _And_, most importantly,
> > kautobuild needs to be fixed so that we still get build coverage.
> 
> I personally think that your suggestion using STD_CONFIG or similar is a 
> good way forward.  Specific needs for given targets can then be 
> expressed along with the Kconfig menu item describing that target.

It would've been nice, but Linus appears to have ruled that option out too.


From christer at weinigel.se  Tue Jun  8 08:50:55 2010
From: christer at weinigel.se (Christer Weinigel)
Date: Tue, 08 Jun 2010 14:50:55 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100608115832.GB25370@n2100.arm.linux.org.uk>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>	<alpine.LFD.2.00.1006031829020.24526@xanadu.home>	<4C083BCF.2060500@bluewatersys.com>	<201006040310.15019.marek.vasut@gmail.com>	<4C0853E1.1080005@bluewatersys.com>	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>	<20100604061034.GI6499@atomide.com>	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
Message-ID: <4C0E3CAF.4050409@weinigel.se>

On 06/08/2010 01:58 PM, Russell King - ARM Linux wrote:

> If you're hypothesis that Linus is only looking at the diffstat, then
> what are patches to combine the defconfigs going to do?  It's going
> to create lots of noise in arch/arm/configs/ - which is precisely what
> Linus is complaining about.  In fact, patch-wise it's going to create
> an extremely large patch.  And if we do this time and time again while
> progressively reducing the defconfigs.  No, this isn't the answer -
> it's only going to make the problem worse.


Linus isn't stupid.  If you explain what you are doing and that the goal 
is to reduce the set of defconfigs to just one per processor family, and 
that it will reduce the churn in the end, I think Linus will listen.

Actually, why not just ask Linus if the the way Ben Dooks has structured 
the Samsung defconfigs would be ok with him.  It's only one defconfig 
per CPU family and each defconfig supports a lot of boards.
s3c2410_defconfig supports most ARM9 based Samsung SoCs, S3C2410, 
S3C2412, S3C2413, S3C2440 and S3C2442, all in all some 20-odd boards. 
So for someone who wants to start a new S3C port they can just use the 
s3c2410_defconfig as a base, which I think is how Linus want's the 
defconfigs to be used.

   /Christer



From eric.y.miao at gmail.com  Tue Jun  8 09:00:11 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 8 Jun 2010 21:00:11 +0800
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100608124913.GC25370@n2100.arm.linux.org.uk>
References: <201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com> 
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com> 
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com> 
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com> 
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk> 
	<20100608123102.GT15515@atomide.com>
	<AANLkTilyaRYigz2LoirclkNHyj3g3CUogM6OmnpUfM4M@mail.gmail.com> 
	<20100608124913.GC25370@n2100.arm.linux.org.uk>
Message-ID: <AANLkTilnzP--UT_Jwr8PfODhp4GVjhfDvBETLsRv-slG@mail.gmail.com>

On Tue, Jun 8, 2010 at 8:49 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Tue, Jun 08, 2010 at 08:43:13PM +0800, Eric Miao wrote:
>> Just wondering if a migration path is possible. Does anyone seriously think
>> about the solution Linus proposed and maybe we can have an implementation
>> and have all defconfig going that way before they are completely purged?
>
> Doesn't select from an 'm' symbol cause the target of the select to end
> up being 'm' ? ?If yes, we have a way to solve this today.
>

Have a quick test and it seems to be the case.

> config ARM_PLATFORM_FOO
> ? ? ? ?bool "Default configuration for FOO"
> ? ? ? ?select ARCH_FOO
> ? ? ? ?select VIDEO_WHATEVER
>
> config ARM_PLATFORM_FOO_MOD
> ? ? ? ?tristate
> ? ? ? ?default m if ARM_PLATFORM_FOO
> ? ? ? ?select I2C
> ? ? ? ?select SPI
>
> etc. ?We just need to be very careful about dependencies for things like
> I2C, SPI, etc.
>


From nico at fluxnic.net  Tue Jun  8 09:01:35 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 08 Jun 2010 09:01:35 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100608125053.GD25370@n2100.arm.linux.org.uk>
References: <4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006080839240.30664@xanadu.home>
	<20100608125053.GD25370@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.00.1006080857390.30664@xanadu.home>

On Tue, 8 Jun 2010, Russell King - ARM Linux wrote:

> On Tue, Jun 08, 2010 at 08:44:52AM -0400, Nicolas Pitre wrote:
> > On Tue, 8 Jun 2010, Russell King - ARM Linux wrote:
> > > I believe the only acceptable solution is to get an alterative method
> > > in place - no matter what it is - and remove the all but one of the
> > > defconfig files from the mainline kernel.  _And_, most importantly,
> > > kautobuild needs to be fixed so that we still get build coverage.
> > 
> > I personally think that your suggestion using STD_CONFIG or similar is a 
> > good way forward.  Specific needs for given targets can then be 
> > expressed along with the Kconfig menu item describing that target.
> 
> It would've been nice, but Linus appears to have ruled that option out too.

I wouldn't give up on that option just yet though.  I don't think he 
fully understood your idea, and without an actual patch it might be hard 
to understand as well, especially for people who are not used to deal 
with the target varieties we have on ARM.  Linus is also known to change 
his mind when presented with evidences.


Nicolas


From linux at arm.linux.org.uk  Tue Jun  8 09:10:07 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 8 Jun 2010 14:10:07 +0100
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C0E3CAF.4050409@weinigel.se>
References: <4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<4C0E3CAF.4050409@weinigel.se>
Message-ID: <20100608131007.GE25370@n2100.arm.linux.org.uk>

On Tue, Jun 08, 2010 at 02:50:55PM +0200, Christer Weinigel wrote:
> Linus isn't stupid.  If you explain what you are doing and that the goal  
> is to reduce the set of defconfigs to just one per processor family, and  
> that it will reduce the churn in the end, I think Linus will listen.

Linus has said in no uncertain terms that all but one or two ARM defconfigs
will be deleted at the next merge window.  That's not "one or two defconfigs
per platform class".

> Actually, why not just ask Linus if the the way Ben Dooks has structured  
> the Samsung defconfigs would be ok with him.  It's only one defconfig  
> per CPU family and each defconfig supports a lot of boards.

When you look at what Linus is complaining about in the diffstat, you
realise that the S3C stuff is part of the problem.  This is what the
diffstat for arch/arm/configs looks like for the period covering
2.6.34 to 2.6.35-rc1 - which is the one which provoked Linus' reaction.

 arch/arm/configs/am3517_evm_defconfig        |  144 +++-
 arch/arm/configs/ams_delta_defconfig         |   10 +-
 arch/arm/configs/cns3420vb_defconfig         |  831 +++++++++++++
 arch/arm/configs/devkit8000_defconfig        |  157 ++-
 arch/arm/configs/mmp2_defconfig              |   75 +-
 arch/arm/configs/mx51_defconfig              |   17 +-
 arch/arm/configs/omap3_defconfig             |  151 ++-
 arch/arm/configs/omap3_evm_defconfig         |   51 +-
 arch/arm/configs/omap3_stalker_lks_defconfig | 1691 ++++++++++++++++++++++++++
 arch/arm/configs/omap_4430sdp_defconfig      |  448 +++++++-
 arch/arm/configs/rx51_defconfig              |   39 +-
 arch/arm/configs/s3c2410_defconfig           |  719 ++++++-----
 arch/arm/configs/s3c6400_defconfig           |  637 +++++++++-
 arch/arm/configs/s5p6440_defconfig           |   87 +-
 arch/arm/configs/s5p6442_defconfig           |   66 +-
 arch/arm/configs/s5pc100_defconfig           |  235 +++-
 arch/arm/configs/s5pc110_defconfig           |   52 +-
 arch/arm/configs/s5pv210_defconfig           |   55 +-
 arch/arm/configs/spear300_defconfig          |  773 ++++++++++++
 arch/arm/configs/spear310_defconfig          |  775 ++++++++++++
 arch/arm/configs/spear320_defconfig          |  775 ++++++++++++
 arch/arm/configs/spear600_defconfig          |  760 ++++++++++++
 arch/arm/configs/stamp9g20_defconfig         | 1456 ++++++++++++++++++++++
 23 files changed, 9323 insertions(+), 681 deletions(-)

Notice that almost a third (7/23) of the files were Samsung related.

It's also not just about the number of defconfigs.  Linus had other
valid points too - for example, you can't review the changes to them
properly, because any change to them is far too noisy.  That point
doesn't go away by reducing the number of defconfigs.

> s3c2410_defconfig supports most ARM9 based Samsung SoCs, S3C2410,  
> S3C2412, S3C2413, S3C2440 and S3C2442, all in all some 20-odd boards. So 
> for someone who wants to start a new S3C port they can just use the  
> s3c2410_defconfig as a base, which I think is how Linus want's the  
> defconfigs to be used.

I think Linus has made up his mind about what he wants to see, and that's
what we have to provide him with.  However, if you think you've got a
great alternative, please get involved with the thread on LKML and see if
_you_ can change his mind.


From linux at arm.linux.org.uk  Tue Jun  8 09:13:19 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 8 Jun 2010 14:13:19 +0100
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <alpine.LFD.2.00.1006080857390.30664@xanadu.home>
References: <4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006080839240.30664@xanadu.home>
	<20100608125053.GD25370@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006080857390.30664@xanadu.home>
Message-ID: <20100608131319.GF25370@n2100.arm.linux.org.uk>

On Tue, Jun 08, 2010 at 09:01:35AM -0400, Nicolas Pitre wrote:
> I wouldn't give up on that option just yet though.  I don't think he 
> fully understood your idea, and without an actual patch it might be hard 
> to understand as well, especially for people who are not used to deal 
> with the target varieties we have on ARM.  Linus is also known to change 
> his mind when presented with evidences.

The two ideas are very close to each other - and can be generated
together.

If we create something like Linus' preferred solution, we can then do
in the main arch/arm/Kconfig:

config STD_CONFIG
	bool "blah"

if STD_CONFIG

if MACH_WHATEVER
include arch/arm/config/Kconfig.whatever
endif

if MACH_BLAH
include arch/arm/config/Kconfig.blah
endif

endif

which should work as per my idea.


From anfei.zhou at gmail.com  Tue Jun  8 09:29:40 2010
From: anfei.zhou at gmail.com (anfei)
Date: Tue, 8 Jun 2010 21:29:40 +0800
Subject: kernel virtual memory access (from app) does not generate segfault
In-Reply-To: <20100421131149.GB9408@desktop>
References: <4BCD7076.9030802@browserseal.com>
	<20100420093441.GD6684@trinity.fluff.org>
	<000001cae074$1b564ff0$4044010a@Emea.Arm.com>
	<20100420142047.GA7398@desktop>
	<20100420170944.GE2234@trinity.fluff.org>
	<20100420192813.GA29831@n2100.arm.linux.org.uk>
	<20100421131149.GB9408@desktop>
Message-ID: <20100608132940.GA6874@desktop>

Hi Russell,

On Wed, Apr 21, 2010 at 09:11:49PM +0800, anfei wrote:
> On Tue, Apr 20, 2010 at 08:28:14PM +0100, Russell King - ARM Linux wrote:
> > On Tue, Apr 20, 2010 at 06:09:44PM +0100, Ben Dooks wrote:
> > > On Tue, Apr 20, 2010 at 10:20:47PM +0800, anfei wrote:
> > > > On Tue, Apr 20, 2010 at 11:27:40AM +0100, Dave P. Martin wrote:
> > > > >  
> > > > > 
> > > > > > -----Original Message-----
> > > > > > From: linux-arm-kernel-bounces at lists.infradead.org 
> > > > > > [mailto:linux-arm-kernel-bounces at lists.infradead.org] On 
> > > > > > Behalf Of Ben Dooks
> > > > > > Sent: 20 April 2010 10:35
> > > > > > To: Sasha Sirotkin
> > > > > > Cc: linux-arm-kernel at lists.infradead.org
> > > > > > Subject: Re: kernel virtual memory access (from app) does not 
> > > > > 
> > > > > [..]
> > > > > 
> > > > > > > For instance, this code generates a segfault allright
> > > > > > >
> > > > > > > int * aa;
> > > > > > > aa = 0xc0000000;
> > > > > > > *aa=42;
> > > > > > >
> > > > > > > However this code does not, instead the process simply 
> > > > > > hangs (and can 
> > > > > > > be
> > > > > > > killed)
> > > > > > >
> > > > > > > void (*func)(void);
> > > > > > > func = 0xc0000000;
> > > > > > > func();
> > > > > > 
> > > > > > Your first example writes to an area, your second is 
> > > > > > execution. IIRC, this version of the ARM architecture equates 
> > > > > > read and execute permission and so you may actually have 
> > > > > > permission to read this area and thus execute code in it.
> > 
> > User programs do not have permission to read kernel addresses.  Trying to
> > do so _should_ generate a permission fault.
> > 
> > > > > I tried reading that address (albeit on an old 2.6.28 kernel), and I get a
> > > > > segfault.
> > 
> > ... which is correct behaviour.
> > 
> > > > > Trying to execute in kernel space is the only thing that appears to hang.
> > > > > Attaching to the process in gdb, I observed that pc is always 0xc0000000
> > > > > when the process is stopped.
> > > > > 
> > > > > top accounts most of the CPU time as being consumed in the kernel.
> > > > > 
> > > > > I think what is going on here is that the kernel is catching the expected
> > > > > prefetch abort, but the handler fails to send SIGSEGV to the user process
> > > > > --- the process is resumed with the same pc and we end up in an endless
> > > > > spin.
> > 
> > Yes, that'd make sense.
> > 
> > > > diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> > > > index 9d40c34..cd4d15c 100644
> > > > --- a/arch/arm/mm/fault.c
> > > > +++ b/arch/arm/mm/fault.c
> > > > @@ -393,6 +393,9 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
> > > >  	if (addr < TASK_SIZE)
> > > >  		return do_page_fault(addr, fsr, regs);
> > > >  
> > > > +	if (user_mode(regs) && addr >= TASK_SIZE)
> > > > +		goto bad_area;
> > > > +
> > > 
> > > technically, addr >= TASK_SIZE was guaranteed by the previous test
> > > on addr. The user_mode(regs) may well be a good idea, although I'm
> > > not sure if we get entered here if the kernel is attempting to access
> > > user-mode memory by forcing unpriveldged accesses.
> > > 
> > > probably best to get Russell's opinion.
> > 
> > 	if (user_mode(regs))
> > 		goto bad_area;
> > 
> > should be sufficient, since userspace should not be accessing anything
> > above TASK_SIZE, except for the exception page, which will always be
> > mapped.
> 
> Patch updated, and with comment log.
> 
> ===
> ARM: Proper prefetch abort handling on pre-ARMv6
> 
> Instruction faults on pre-ARMv6 CPUs are interpreted as
> a 'translation fault', but do_translation_fault doesn't
> handle well if user mode trying to run instruction above
> TASK_SIZE, and result in the infinite retry of that
> instruction.
> 
> Signed-off-by: Anfei Zhou <anfei.zhou at gmail.com>
> ---
>  arch/arm/mm/fault.c |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> index 9d40c34..8ad75e9 100644
> --- a/arch/arm/mm/fault.c
> +++ b/arch/arm/mm/fault.c
> @@ -393,6 +393,9 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
>  	if (addr < TASK_SIZE)
>  		return do_page_fault(addr, fsr, regs);
>  
> +	if (user_mode(regs))
> +		goto bad_area;
> +
>  	index = pgd_index(addr);
>  
>  	/*

This patch is still not into the mainline, will you plan to apply it?

Thanks,
Anfei.

> -- 
> 1.6.4.rc1
> 


From linux at arm.linux.org.uk  Tue Jun  8 09:36:05 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 8 Jun 2010 14:36:05 +0100
Subject: kernel virtual memory access (from app) does not generate segfault
In-Reply-To: <20100608132940.GA6874@desktop>
References: <4BCD7076.9030802@browserseal.com>
	<20100420093441.GD6684@trinity.fluff.org>
	<000001cae074$1b564ff0$4044010a@Emea.Arm.com>
	<20100420142047.GA7398@desktop>
	<20100420170944.GE2234@trinity.fluff.org>
	<20100420192813.GA29831@n2100.arm.linux.org.uk>
	<20100421131149.GB9408@desktop> <20100608132940.GA6874@desktop>
Message-ID: <20100608133605.GG25370@n2100.arm.linux.org.uk>

On Tue, Jun 08, 2010 at 09:29:40PM +0800, anfei wrote:
> Hi Russell,
> 
> On Wed, Apr 21, 2010 at 09:11:49PM +0800, anfei wrote:
> > Patch updated, and with comment log.
> > 
> > ===
> > ARM: Proper prefetch abort handling on pre-ARMv6
> > 
> > Instruction faults on pre-ARMv6 CPUs are interpreted as
> > a 'translation fault', but do_translation_fault doesn't
> > handle well if user mode trying to run instruction above
> > TASK_SIZE, and result in the infinite retry of that
> > instruction.
> > 
> > Signed-off-by: Anfei Zhou <anfei.zhou at gmail.com>
> > ---
> >  arch/arm/mm/fault.c |    3 +++
> >  1 files changed, 3 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> > index 9d40c34..8ad75e9 100644
> > --- a/arch/arm/mm/fault.c
> > +++ b/arch/arm/mm/fault.c
> > @@ -393,6 +393,9 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
> >  	if (addr < TASK_SIZE)
> >  		return do_page_fault(addr, fsr, regs);
> >  
> > +	if (user_mode(regs))
> > +		goto bad_area;
> > +
> >  	index = pgd_index(addr);
> >  
> >  	/*
> 
> This patch is still not into the mainline, will you plan to apply it?

I had, but as it isn't in the patch system, it got buried and forgotten.
Could you submit it to the patch system please?  Just emailing it in
a similar manner to that above, but with a subject of
"Proper prefetch abort handling on pre-ARMv6" and an additional
"KernelVersion: 2.6.whatever" line to the patch system should suffice.


From anfei.zhou at gmail.com  Tue Jun  8 10:19:34 2010
From: anfei.zhou at gmail.com (anfei)
Date: Tue, 8 Jun 2010 22:19:34 +0800
Subject: kernel virtual memory access (from app) does not generate segfault
In-Reply-To: <20100608133605.GG25370@n2100.arm.linux.org.uk>
References: <4BCD7076.9030802@browserseal.com>
	<20100420093441.GD6684@trinity.fluff.org>
	<000001cae074$1b564ff0$4044010a@Emea.Arm.com>
	<20100420142047.GA7398@desktop>
	<20100420170944.GE2234@trinity.fluff.org>
	<20100420192813.GA29831@n2100.arm.linux.org.uk>
	<20100421131149.GB9408@desktop> <20100608132940.GA6874@desktop>
	<20100608133605.GG25370@n2100.arm.linux.org.uk>
Message-ID: <20100608141934.GB6874@desktop>

On Tue, Jun 08, 2010 at 02:36:05PM +0100, Russell King - ARM Linux wrote:
> On Tue, Jun 08, 2010 at 09:29:40PM +0800, anfei wrote:
> > Hi Russell,
> > 
> > On Wed, Apr 21, 2010 at 09:11:49PM +0800, anfei wrote:
> > > Patch updated, and with comment log.
> > > 
> > > ===
> > > ARM: Proper prefetch abort handling on pre-ARMv6
> > > 
> > > Instruction faults on pre-ARMv6 CPUs are interpreted as
> > > a 'translation fault', but do_translation_fault doesn't
> > > handle well if user mode trying to run instruction above
> > > TASK_SIZE, and result in the infinite retry of that
> > > instruction.
> > > 
> > > Signed-off-by: Anfei Zhou <anfei.zhou at gmail.com>
> > > ---
> > >  arch/arm/mm/fault.c |    3 +++
> > >  1 files changed, 3 insertions(+), 0 deletions(-)
> > > 
> > > diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
> > > index 9d40c34..8ad75e9 100644
> > > --- a/arch/arm/mm/fault.c
> > > +++ b/arch/arm/mm/fault.c
> > > @@ -393,6 +393,9 @@ do_translation_fault(unsigned long addr, unsigned int fsr,
> > >  	if (addr < TASK_SIZE)
> > >  		return do_page_fault(addr, fsr, regs);
> > >  
> > > +	if (user_mode(regs))
> > > +		goto bad_area;
> > > +
> > >  	index = pgd_index(addr);
> > >  
> > >  	/*
> > 
> > This patch is still not into the mainline, will you plan to apply it?
> 
> I had, but as it isn't in the patch system, it got buried and forgotten.
> Could you submit it to the patch system please?  Just emailing it in
> a similar manner to that above, but with a subject of
> "Proper prefetch abort handling on pre-ARMv6" and an additional
> "KernelVersion: 2.6.whatever" line to the patch system should suffice.

Done, thanks!
Anfei.


From shanevolpe at gmail.com  Tue Jun  8 10:38:36 2010
From: shanevolpe at gmail.com (Shane Volpe)
Date: Tue, 8 Jun 2010 10:38:36 -0400
Subject: Kernel 2.6.33: PXA270 Audio does not resume after resume from suspend
	state
Message-ID: <AANLkTiloYpM6LBNFHOfHGdvoHZ03cavW8vdmVZjHxSKC@mail.gmail.com>

I have upgraded an embedded system (PXA270) to the 2.6.33 kernel (from
2.6.23).  Now when I run an audio program (ogg123) and put the system
into standby then wake the system up the audio does not work (continue
playing) after resume until I terminate ogg123 and start again.  After
restarting ogg123 the audio works fine with out reseting the system or
changing anything else on the system.

The system is using the UCB1400 AC97 codec and just as added
information when the audio is locked up, after resume, the touchscreen
on the system still works which is also controlled by the UCB1400
audio codec.  I have also tried several other audio players and the
results are the same.   Has anyone else seen this bug and does anyone
have suggestions on further tests to perform to narrow down were the
bug may reside?
Regards,
Shane


From linux at arm.linux.org.uk  Tue Jun  8 10:41:06 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 8 Jun 2010 15:41:06 +0100
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006032227.56429.marek.vasut@gmail.com>
References: <20100603192459.GA9169@n2100.arm.linux.org.uk>
	<201006032155.19349.marek.vasut@gmail.com>
	<20100603200109.GC9169@n2100.arm.linux.org.uk>
	<201006032227.56429.marek.vasut@gmail.com>
Message-ID: <20100608144106.GH25370@n2100.arm.linux.org.uk>

On Thu, Jun 03, 2010 at 10:27:56PM +0200, Marek Vasut wrote:
> btw. Maybe updating the machine registry so it allows pasting/attaching a 
> defconfig with information about kernel version the defconfig corresponds
> with ?

That means persisting with defconfigs, and the problems of keeping
them updated with the kernel.

Moreover, it encourages "one defconfig per machine", which will
cause the number of defconfigs to grow even more - and I don't see
such a system being usable with kautobuild.

Given that it'd mean we still need to solve the problem, I don't see
much point in expanding the machine database to store defconfigs.  It
seems to me it only moves the problem elsewhere, and at the same time
means we end up with two concurrently running systems - the fixed
in-kernel method and the external defconfig file.


From eric.y.miao at gmail.com  Tue Jun  8 10:51:38 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 8 Jun 2010 22:51:38 +0800
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100608131319.GF25370@n2100.arm.linux.org.uk>
References: <4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com> 
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com> 
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com> 
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk> 
	<alpine.LFD.2.00.1006080839240.30664@xanadu.home>
	<20100608125053.GD25370@n2100.arm.linux.org.uk> 
	<alpine.LFD.2.00.1006080857390.30664@xanadu.home>
	<20100608131319.GF25370@n2100.arm.linux.org.uk>
Message-ID: <AANLkTinWCRIKyMUseSpkRfEC0Cba4JRGBiUwb_jD_MkZ@mail.gmail.com>

On Tue, Jun 8, 2010 at 9:13 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Tue, Jun 08, 2010 at 09:01:35AM -0400, Nicolas Pitre wrote:
>> I wouldn't give up on that option just yet though. ?I don't think he
>> fully understood your idea, and without an actual patch it might be hard
>> to understand as well, especially for people who are not used to deal
>> with the target varieties we have on ARM. ?Linus is also known to change
>> his mind when presented with evidences.
>
> The two ideas are very close to each other - and can be generated
> together.
>
> If we create something like Linus' preferred solution, we can then do
> in the main arch/arm/Kconfig:
>
> config STD_CONFIG
> ? ? ? ?bool "blah"
>
> if STD_CONFIG
>
> if MACH_WHATEVER
> include arch/arm/config/Kconfig.whatever
> endif
>
> if MACH_BLAH
> include arch/arm/config/Kconfig.blah
> endif
>
> endif
>
> which should work as per my idea.
>

Anyway, we might need a tool to analyze those common config options across all
boards, and those not. Attached is a script used when updating debian kernel
configs, which I found might be useful. The result is still a _big_
mess to sort out
though. Below is what I did:

1. Generating a complete list of configs (updated)
ycmiao at macbook-lucid:~/kernel/linux-2.6$ for i in arch/arm/configs/*;
do j=`echo $i | sed 's/.*configs\/\(.*\)_defconfig/\1/'`; echo $j;
mkdir ../build/tmp; make ARCH=arm O=../build/tmp `basename $i`; make
ARCH=arm O=../build/tmp oldconfig; cp ../build/tmp/.config
../configs/config.$j; rm -fr ../build/tmp; done

2. Use splitconfigs.pl shows the reduction of config options

ycmiao at macbook-lucid:~/kernel/configs$ cat * | wc -l
258408

ycmiao at macbook-lucid:~/kernel/configs$ splitconfig.pl .
Reading config's ...
Merging lists ...
Creating common config ... done.
Creating stub configs ...

ycmiao at macbook-lucid:~/kernel/configs$ cat * | wc -l
142062

3. A config.common includes those options common to all config.* and
the remaining
config.* now only includes those could be different across boards.
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From lrg at slimlogic.co.uk  Tue Jun  8 11:01:55 2010
From: lrg at slimlogic.co.uk (Liam Girdwood)
Date: Tue, 08 Jun 2010 16:01:55 +0100
Subject: [PATCH 2/2] pxa: modify the pxa2xx-ac97 file for pxa168
In-Reply-To: <AANLkTimZjKvAAcK9xiXng7wJ0tVBJrmTIvMgyzrS7HqH@mail.gmail.com>
References: <4C0E21A1.4000909@gmail.com>
	<AANLkTimNwtScfKYVc4qPZFEP6GYklPoHLgr2AE7yquQL@mail.gmail.com>
	<AANLkTimZjKvAAcK9xiXng7wJ0tVBJrmTIvMgyzrS7HqH@mail.gmail.com>
Message-ID: <1276009315.3003.346.camel@odin>

On Tue, 2010-06-08 at 22:49 +0800, Wan ZongShun wrote:
> 2010/6/8 Eric Miao <eric.y.miao at gmail.com>:
> > 2010/6/8 Wan ZongShun <mcuos.com at gmail.com>:
> >> In order to allow the sharing of the pxa2xx-ac97 driver file with pxa168,
> >> we have to do a little change to pxa2xx-ac97 file.
> >>
> >> All private register addresses were located in mach/include/ac97.h.
> >
> > This is not the right way to go, as suggested already. I hope the ac97
> > driver is more self-contained. i.e. having a platform device for:
> >
> >  - where the registers are mapped from
> >  - drcmr channel numbers can be encoded within dma resource
> >  - ac97 register definitions are not exposed everywhere
> >
> 
> Got it, so I should put above to platform_device and remove regs-ac97.h,
> any private bit definition should be removed to driver directory as
> driver _only_.
> 

...and could you also CC Mark on any ASoC related changes too.

Thanks

Liam
-- 
Freelance Developer, SlimLogic Ltd
ASoC and Voltage Regulator Maintainer.
http://www.slimlogic.co.uk



From hartleys at visionengravers.com  Tue Jun  8 11:01:44 2010
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 8 Jun 2010 10:01:44 -0500
Subject: [PATCH 1/3] EP93xx: Add i2s core support
In-Reply-To: <1275991272-30122-2-git-send-email-ryan@bluewatersys.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<1275991272-30122-2-git-send-email-ryan@bluewatersys.com>
Message-ID: <0D753D10438DA54287A00B027084269763708AFD76@AUSP01VMBX24.collaborationhost.net>

On Tuesday, June 08, 2010 3:01 AM, Ryan Mallon wrote:
>
> Add core support for EP93xx i2s audio
>
> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>

Looks good.

Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>



From mcuos.com at gmail.com  Tue Jun  8 10:49:09 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Tue, 8 Jun 2010 22:49:09 +0800
Subject: [PATCH 2/2] pxa: modify the pxa2xx-ac97 file for pxa168
In-Reply-To: <AANLkTimNwtScfKYVc4qPZFEP6GYklPoHLgr2AE7yquQL@mail.gmail.com>
References: <4C0E21A1.4000909@gmail.com>
	<AANLkTimNwtScfKYVc4qPZFEP6GYklPoHLgr2AE7yquQL@mail.gmail.com>
Message-ID: <AANLkTimZjKvAAcK9xiXng7wJ0tVBJrmTIvMgyzrS7HqH@mail.gmail.com>

2010/6/8 Eric Miao <eric.y.miao at gmail.com>:
> 2010/6/8 Wan ZongShun <mcuos.com at gmail.com>:
>> In order to allow the sharing of the pxa2xx-ac97 driver file with pxa168,
>> we have to do a little change to pxa2xx-ac97 file.
>>
>> All private register addresses were located in mach/include/ac97.h.
>
> This is not the right way to go, as suggested already. I hope the ac97
> driver is more self-contained. i.e. having a platform device for:
>
> ?- where the registers are mapped from
> ?- drcmr channel numbers can be encoded within dma resource
> ?- ac97 register definitions are not exposed everywhere
>

Got it, so I should put above to platform_device and remove regs-ac97.h,
any private bit definition should be removed to driver directory as
driver _only_.


-- 
*linux-arm-kernel mailing list
mail addr:linux-arm-kernel at lists.infradead.org
you can subscribe by:
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

* linux-arm-NUC900 mailing list
mail addr:NUC900 at googlegroups.com
main web: https://groups.google.com/group/NUC900
you can subscribe it by sending me mail:
mcuos.com at gmail.com


From hartleys at visionengravers.com  Tue Jun  8 11:41:10 2010
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 8 Jun 2010 10:41:10 -0500
Subject: [PATCH] ep93xx: register backlight driver
In-Reply-To: <0D753D10438DA54287A00B0270842697636EE74BB1@AUSP01VMBX24.collaborationhost.net>
References: <0D753D10438DA54287A00B0270842697636EE74BB1@AUSP01VMBX24.collaborationhost.net>
Message-ID: <0D753D10438DA54287A00B027084269763708AFE70@AUSP01VMBX24.collaborationhost.net>

On Monday, May 10, 2010 6:58 PM, H Hartley Sweeten wrote:
>
> Add the platform registration for the ep93xx backlight driver
> that is now queued in the backlight tree.
>
> Since the pwm BRIGHT signal only functions if the video system
> is operating, register the backlight when the framebuffer device
> is registered.
>
> Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <ryan at bluewatersys.com>

Ryan,

The EP93xx backlight driver is now merged.
commit 08b3924b24cdb1942393dc3009335a2153bd2eac

Do you have any issues with this patch to enable it?

Regards,
Hartley

---

This is based off next-20100510, if needed I can rebase it off
another tree.

diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 8d3f77e..07d7bb9 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -568,6 +568,11 @@ static struct platform_device ep93xx_fb_device = {
 	.resource		= ep93xx_fb_resource,
 };
 
+static struct platform_device ep93xx_bl_device = {
+	.name		= "ep93xx-bl",
+	.id		= -1,
+};
+
 /**
  * ep93xx_register_fb - Register the framebuffer platform device.
  * @data:	platform specific framebuffer configuration (__initdata)
@@ -576,6 +581,7 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
 {
 	ep93xxfb_data = *data;
 	platform_device_register(&ep93xx_fb_device);
+	platform_device_register(&ep93xx_bl_device);
 }
 
 
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From eric at eukrea.com  Tue Jun  8 12:07:05 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Tue,  8 Jun 2010 18:07:05 +0200
Subject: [PATCH] i.MX35: return IPU clock's value for mx3fb
Message-ID: <1276013225-11982-1-git-send-email-eric@eukrea.com>

without this patch, ipu_clk's value is 0 thus preventing mx3fb from
calculating the right divisor for pixel clock generator.

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/mach-mx3/clock-imx35.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 9f3e943..28be011 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -359,7 +359,7 @@ DEFINE_CLOCK(i2c1_clk,   0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(i2c2_clk,   1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(i2c3_clk,   2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
 DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
-DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, NULL, NULL);
+DEFINE_CLOCK(ipu_clk,    0, CCM_CGR1, 18, get_rate_ahb, NULL);
 DEFINE_CLOCK(kpp_clk,    0, CCM_CGR1, 20, get_rate_ipg, NULL);
 DEFINE_CLOCK(mlb_clk,    0, CCM_CGR1, 22, get_rate_ahb, NULL);
 DEFINE_CLOCK(mshc_clk,   0, CCM_CGR1, 24, get_rate_mshc, NULL);
-- 
1.6.3.3



From nico at fluxnic.net  Tue Jun  8 12:55:52 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 08 Jun 2010 12:55:52 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <AANLkTinWCRIKyMUseSpkRfEC0Cba4JRGBiUwb_jD_MkZ@mail.gmail.com>
References: <4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006080839240.30664@xanadu.home>
	<20100608125053.GD25370@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006080857390.30664@xanadu.home>
	<20100608131319.GF25370@n2100.arm.linux.org.uk>
	<AANLkTinWCRIKyMUseSpkRfEC0Cba4JRGBiUwb_jD_MkZ@mail.gmail.com>
Message-ID: <alpine.LFD.2.00.1006081213190.30664@xanadu.home>

On Tue, 8 Jun 2010, Eric Miao wrote:

> On Tue, Jun 8, 2010 at 9:13 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> > On Tue, Jun 08, 2010 at 09:01:35AM -0400, Nicolas Pitre wrote:
> >> I wouldn't give up on that option just yet though. ?I don't think he
> >> fully understood your idea, and without an actual patch it might be hard
> >> to understand as well, especially for people who are not used to deal
> >> with the target varieties we have on ARM. ?Linus is also known to change
> >> his mind when presented with evidences.
> >
> > The two ideas are very close to each other - and can be generated
> > together.
> >
> > If we create something like Linus' preferred solution, we can then do
> > in the main arch/arm/Kconfig:
> >
> > config STD_CONFIG
> > ? ? ? ?bool "blah"
> >
> > if STD_CONFIG
> >
> > if MACH_WHATEVER
> > include arch/arm/config/Kconfig.whatever
> > endif
> >
> > if MACH_BLAH
> > include arch/arm/config/Kconfig.blah
> > endif
> >
> > endif
> >
> > which should work as per my idea.
> >
> 
> Anyway, we might need a tool to analyze those common config options across all
> boards, and those not. Attached is a script used when updating debian kernel
> configs, which I found might be useful. The result is still a _big_
> mess to sort out
> though.

I doubt this can be automated.  The idea is to have something human 
readable, and the only information we really care about is the set of 
drivers each individual target needs.

For example, let's have a look at the SheevaPlug target which is quite 
simple.

config MACH_SHEEVAPLUG
	bool "blah"
	if BASE_STUFF=y
	    select MTD_PARTITIONS
	    select MTD_NAND_ORION
	    select MV643XX_ETH
	    select SERIAL_8250_CONSOLE
	    select USB_EHCI_HCD
	    select MMC_MVSDIO
	    select LEDS_GPIO_PLATFORM
	    select RTC_DRV_MV
	    select MV_XOR
	    select CRYPTO_DEV_MV_CESA
	endif

So the idea is really to describe the built-in hardware and 
automatically selects the _minimum_ set of options (including the 
options they depend on) for all that built-in hardware to work properly.  
All the rest is arbitrary and should probably not be encoded in the 
kernel tree.  The rule of thumb here is to specify any driver set that 
otherwise requires the target's data sheet and/or schematics for a 
proper selection.  All the rest such as filesystems, network protocols, 
USB devices and so on are optional stuff that need no particular 
information from that target and therefore need not to be explicitly 
selected here.

Hence with the above you immediately get a sense of what this particular 
hardware target needs in a fairly human readable form without having to 
dig and guess through all the Kconfig options.  And having that 
information next to the very Kconfig entry concerned is also much easier 
to maintain rather than having that located in a separate file.

Yet in this example, it would probably make sense to move RTC_DRV_MV, 
MV_XOR and CRYPTO_DEV_MV_CESA to where CONFIG_ARCH_KIRKWOOD is selected 
instead of repeating those for every Kirkwood target, as those are 
always available since they're built into the SOC and require no 
external wiring.


Nicolas

From cbouatmailru at gmail.com  Tue Jun  8 13:00:30 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 8 Jun 2010 21:00:30 +0400
Subject: [GIT PULL v2] Some Cavium CNS3xxx updates for 2.6.36
Message-ID: <20100608170030.GA26992@oksana.dev.rtsoft.ru>

Hi Russell,

The main reason for the v2 is, obviously, the defconfigs situation.
I dropped the defconfig update in this pull request.

There are also few improvements as suggested by by Ben Dooks and
Sergei Shtylyov, plus there is no longer the ugly
"../../../drivers/mmc/host/sdhci.h" include anymore.

As usual, I'm posting the updated patches as well.

The following changes since commit 9dda696f0de87a2e5cfabb147e28c76b7d3c6846:
  Linus Torvalds (1):
        Merge branch 'release' of git://git.kernel.org/.../aegl/linux-2.6

are available in the git repository at:

  git://git.infradead.org/users/cbou/linux-cns3xxx.git master

Anton Vorontsov (4):
      ARM: cns3xxx: Use IO memory accessors everywhere
      ARM: cns3xxx: Add support for PCI Express ports
      ARM: cns3xxx: Add support for SDHCI controllers
      ARM: cns3xxx: Add support for AHCI controllers

 arch/arm/Kconfig                             |    3 +-
 arch/arm/mach-cns3xxx/Makefile               |    3 +-
 arch/arm/mach-cns3xxx/cns3420vb.c            |    4 +
 arch/arm/mach-cns3xxx/devices.c              |  111 ++++++++
 arch/arm/mach-cns3xxx/devices.h              |   20 ++
 arch/arm/mach-cns3xxx/include/mach/cns3xxx.h |   91 +++---
 arch/arm/mach-cns3xxx/pcie.c                 |  389 ++++++++++++++++++++++++++
 arch/arm/mach-cns3xxx/pm.c                   |   31 ++-
 8 files changed, 596 insertions(+), 56 deletions(-)
 create mode 100644 arch/arm/mach-cns3xxx/devices.c
 create mode 100644 arch/arm/mach-cns3xxx/devices.h
 create mode 100644 arch/arm/mach-cns3xxx/pcie.c


From cbouatmailru at gmail.com  Tue Jun  8 13:01:23 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 8 Jun 2010 21:01:23 +0400
Subject: [PATCH 1/4] ARM: cns3xxx: Use IO memory accessors everywhere
In-Reply-To: <20100608170030.GA26992@oksana.dev.rtsoft.ru>
References: <20100608170030.GA26992@oksana.dev.rtsoft.ru>
Message-ID: <20100608170123.GA22516@oksana.dev.rtsoft.ru>

Before it isn't too late let's switch to IO memory accessors.
This patch converts all current _REG users and _REG definitions.
There should be no functional changes.

Suggested-by: Ben Dooks <ben-linux at fluff.org>
Suggested-by: Sergei Shtylyov <sshtylyov at mvista.com>
Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/mach-cns3xxx/include/mach/cns3xxx.h |   91 +++++++++++++-------------
 arch/arm/mach-cns3xxx/pm.c                   |   31 +++++++--
 2 files changed, 68 insertions(+), 54 deletions(-)

diff --git a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
index 8a2f5a2..6dbce13 100644
--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
@@ -247,37 +247,36 @@
  * Misc block
  */
 #define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs))
-#define MISC_MEM_MAP_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_MISC_BASE_VIRT + (offset))))
-
-#define MISC_MEMORY_REMAP_REG			MISC_MEM_MAP_VALUE(0x00)
-#define MISC_CHIP_CONFIG_REG			MISC_MEM_MAP_VALUE(0x04)
-#define MISC_DEBUG_PROBE_DATA_REG		MISC_MEM_MAP_VALUE(0x08)
-#define MISC_DEBUG_PROBE_SELECTION_REG		MISC_MEM_MAP_VALUE(0x0C)
-#define MISC_IO_PIN_FUNC_SELECTION_REG		MISC_MEM_MAP_VALUE(0x10)
-#define MISC_GPIOA_PIN_ENABLE_REG		MISC_MEM_MAP_VALUE(0x14)
-#define MISC_GPIOB_PIN_ENABLE_REG		MISC_MEM_MAP_VALUE(0x18)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A	MISC_MEM_MAP_VALUE(0x1C)
-#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B	MISC_MEM_MAP_VALUE(0x20)
-#define MISC_GPIOA_15_0_PULL_CTRL_REG		MISC_MEM_MAP_VALUE(0x24)
-#define MISC_GPIOA_16_31_PULL_CTRL_REG		MISC_MEM_MAP_VALUE(0x28)
-#define MISC_GPIOB_15_0_PULL_CTRL_REG		MISC_MEM_MAP_VALUE(0x2C)
-#define MISC_GPIOB_16_31_PULL_CTRL_REG		MISC_MEM_MAP_VALUE(0x30)
-#define MISC_IO_PULL_CTRL_REG			MISC_MEM_MAP_VALUE(0x34)
-#define MISC_E_FUSE_31_0_REG			MISC_MEM_MAP_VALUE(0x40)
-#define MISC_E_FUSE_63_32_REG			MISC_MEM_MAP_VALUE(0x44)
-#define MISC_E_FUSE_95_64_REG			MISC_MEM_MAP_VALUE(0x48)
-#define MISC_E_FUSE_127_96_REG			MISC_MEM_MAP_VALUE(0x4C)
-#define MISC_SOFTWARE_TEST_1_REG		MISC_MEM_MAP_VALUE(0x50)
-#define MISC_SOFTWARE_TEST_2_REG		MISC_MEM_MAP_VALUE(0x54)
-
-#define MISC_SATA_POWER_MODE			MISC_MEM_MAP_VALUE(0x310)
-
-#define MISC_USB_CFG_REG			MISC_MEM_MAP_VALUE(0x800)
-#define MISC_USB_STS_REG			MISC_MEM_MAP_VALUE(0x804)
-#define MISC_USBPHY00_CFG_REG			MISC_MEM_MAP_VALUE(0x808)
-#define MISC_USBPHY01_CFG_REG			MISC_MEM_MAP_VALUE(0x80c)
-#define MISC_USBPHY10_CFG_REG			MISC_MEM_MAP_VALUE(0x810)
-#define MISC_USBPHY11_CFG_REG			MISC_MEM_MAP_VALUE(0x814)
+
+#define MISC_MEMORY_REMAP_REG			MISC_MEM_MAP(0x00)
+#define MISC_CHIP_CONFIG_REG			MISC_MEM_MAP(0x04)
+#define MISC_DEBUG_PROBE_DATA_REG		MISC_MEM_MAP(0x08)
+#define MISC_DEBUG_PROBE_SELECTION_REG		MISC_MEM_MAP(0x0C)
+#define MISC_IO_PIN_FUNC_SELECTION_REG		MISC_MEM_MAP(0x10)
+#define MISC_GPIOA_PIN_ENABLE_REG		MISC_MEM_MAP(0x14)
+#define MISC_GPIOB_PIN_ENABLE_REG		MISC_MEM_MAP(0x18)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A	MISC_MEM_MAP(0x1C)
+#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B	MISC_MEM_MAP(0x20)
+#define MISC_GPIOA_15_0_PULL_CTRL_REG		MISC_MEM_MAP(0x24)
+#define MISC_GPIOA_16_31_PULL_CTRL_REG		MISC_MEM_MAP(0x28)
+#define MISC_GPIOB_15_0_PULL_CTRL_REG		MISC_MEM_MAP(0x2C)
+#define MISC_GPIOB_16_31_PULL_CTRL_REG		MISC_MEM_MAP(0x30)
+#define MISC_IO_PULL_CTRL_REG			MISC_MEM_MAP(0x34)
+#define MISC_E_FUSE_31_0_REG			MISC_MEM_MAP(0x40)
+#define MISC_E_FUSE_63_32_REG			MISC_MEM_MAP(0x44)
+#define MISC_E_FUSE_95_64_REG			MISC_MEM_MAP(0x48)
+#define MISC_E_FUSE_127_96_REG			MISC_MEM_MAP(0x4C)
+#define MISC_SOFTWARE_TEST_1_REG		MISC_MEM_MAP(0x50)
+#define MISC_SOFTWARE_TEST_2_REG		MISC_MEM_MAP(0x54)
+
+#define MISC_SATA_POWER_MODE			MISC_MEM_MAP(0x310)
+
+#define MISC_USB_CFG_REG			MISC_MEM_MAP(0x800)
+#define MISC_USB_STS_REG			MISC_MEM_MAP(0x804)
+#define MISC_USBPHY00_CFG_REG			MISC_MEM_MAP(0x808)
+#define MISC_USBPHY01_CFG_REG			MISC_MEM_MAP(0x80c)
+#define MISC_USBPHY10_CFG_REG			MISC_MEM_MAP(0x810)
+#define MISC_USBPHY11_CFG_REG			MISC_MEM_MAP(0x814)
 
 #define MISC_PCIEPHY_CMCTL(x)			MISC_MEM_MAP(0x900 + (x) * 0x004)
 #define MISC_PCIEPHY_CTL(x)			MISC_MEM_MAP(0x940 + (x) * 0x100)
@@ -300,21 +299,21 @@
 /*
  * Power management and clock control
  */
-#define PMU_REG_VALUE(offset) (*((volatile unsigned int *)(CNS3XXX_PM_BASE_VIRT + (offset))))
-
-#define PM_CLK_GATE_REG					PMU_REG_VALUE(0x000)
-#define PM_SOFT_RST_REG					PMU_REG_VALUE(0x004)
-#define PM_HS_CFG_REG					PMU_REG_VALUE(0x008)
-#define PM_CACTIVE_STA_REG				PMU_REG_VALUE(0x00C)
-#define PM_PWR_STA_REG					PMU_REG_VALUE(0x010)
-#define PM_CLK_CTRL_REG					PMU_REG_VALUE(0x014)
-#define PM_PLL_LCD_I2S_CTRL_REG				PMU_REG_VALUE(0x018)
-#define PM_PLL_HM_PD_CTRL_REG				PMU_REG_VALUE(0x01C)
-#define PM_REGULAT_CTRL_REG				PMU_REG_VALUE(0x020)
-#define PM_WDT_CTRL_REG					PMU_REG_VALUE(0x024)
-#define PM_WU_CTRL0_REG					PMU_REG_VALUE(0x028)
-#define PM_WU_CTRL1_REG					PMU_REG_VALUE(0x02C)
-#define PM_CSR_REG					PMU_REG_VALUE(0x030)
+#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs))
+
+#define PM_CLK_GATE_REG					PMU_MEM_MAP(0x000)
+#define PM_SOFT_RST_REG					PMU_MEM_MAP(0x004)
+#define PM_HS_CFG_REG					PMU_MEM_MAP(0x008)
+#define PM_CACTIVE_STA_REG				PMU_MEM_MAP(0x00C)
+#define PM_PWR_STA_REG					PMU_MEM_MAP(0x010)
+#define PM_CLK_CTRL_REG					PMU_MEM_MAP(0x014)
+#define PM_PLL_LCD_I2S_CTRL_REG				PMU_MEM_MAP(0x018)
+#define PM_PLL_HM_PD_CTRL_REG				PMU_MEM_MAP(0x01C)
+#define PM_REGULAT_CTRL_REG				PMU_MEM_MAP(0x020)
+#define PM_WDT_CTRL_REG					PMU_MEM_MAP(0x024)
+#define PM_WU_CTRL0_REG					PMU_MEM_MAP(0x028)
+#define PM_WU_CTRL1_REG					PMU_MEM_MAP(0x02C)
+#define PM_CSR_REG					PMU_MEM_MAP(0x030)
 
 /* PM_CLK_GATE_REG */
 #define PM_CLK_GATE_REG_OFFSET_SDIO			(25)
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 725e1a4..38e4470 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -6,18 +6,25 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/io.h>
 #include <linux/delay.h>
 #include <mach/system.h>
 #include <mach/cns3xxx.h>
 
 void cns3xxx_pwr_clk_en(unsigned int block)
 {
-	PM_CLK_GATE_REG |= (block & PM_CLK_GATE_REG_MASK);
+	u32 reg = __raw_readl(PM_CLK_GATE_REG);
+
+	reg |= (block & PM_CLK_GATE_REG_MASK);
+	__raw_writel(reg, PM_CLK_GATE_REG);
 }
 
 void cns3xxx_pwr_power_up(unsigned int block)
 {
-	PM_PLL_HM_PD_CTRL_REG &= ~(block & CNS3XXX_PWR_PLL_ALL);
+	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
+	reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
+	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 
 	/* Wait for 300us for the PLL output clock locked. */
 	udelay(300);
@@ -25,22 +32,29 @@ void cns3xxx_pwr_power_up(unsigned int block)
 
 void cns3xxx_pwr_power_down(unsigned int block)
 {
+	u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
+
 	/* write '1' to power down */
-	PM_PLL_HM_PD_CTRL_REG |= (block & CNS3XXX_PWR_PLL_ALL);
+	reg |= (block & CNS3XXX_PWR_PLL_ALL);
+	__raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
 };
 
 static void cns3xxx_pwr_soft_rst_force(unsigned int block)
 {
+	u32 reg = __raw_readl(PM_SOFT_RST_REG);
+
 	/*
 	 * bit 0, 28, 29 => program low to reset,
 	 * the other else program low and then high
 	 */
 	if (block & 0x30000001) {
-		PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
+		reg &= ~(block & PM_SOFT_RST_REG_MASK);
 	} else {
-		PM_SOFT_RST_REG &= ~(block & PM_SOFT_RST_REG_MASK);
-		PM_SOFT_RST_REG |= (block & PM_SOFT_RST_REG_MASK);
+		reg &= ~(block & PM_SOFT_RST_REG_MASK);
+		reg |= (block & PM_SOFT_RST_REG_MASK);
 	}
+
+	__raw_writel(reg, PM_SOFT_RST_REG);
 }
 
 void cns3xxx_pwr_soft_rst(unsigned int block)
@@ -73,12 +87,13 @@ void arch_reset(char mode, const char *cmd)
  */
 int cns3xxx_cpu_clock(void)
 {
+	u32 reg = __raw_readl(PM_CLK_CTRL_REG);
 	int cpu;
 	int cpu_sel;
 	int div_sel;
 
-	cpu_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
-	div_sel = (PM_CLK_CTRL_REG >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
+	cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
+	div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
 
 	cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
 
-- 
1.7.0.5



From cbouatmailru at gmail.com  Tue Jun  8 13:01:40 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 8 Jun 2010 21:01:40 +0400
Subject: [PATCH 2/4] ARM: cns3xxx: Add support for PCI Express ports
In-Reply-To: <20100608170030.GA26992@oksana.dev.rtsoft.ru>
References: <20100608170030.GA26992@oksana.dev.rtsoft.ru>
Message-ID: <20100608170140.GB22516@oksana.dev.rtsoft.ru>

This patch adds PCIe support for CNS3xxx-based boards. The support
was tested with a directly attached SKY2 NIC, and EHCI USB controller
behind the PLX PEX8112 P2P bridge (to make sure that type1 cfg cycles
work as expected).

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/Kconfig               |    3 +-
 arch/arm/mach-cns3xxx/Makefile |    1 +
 arch/arm/mach-cns3xxx/pcie.c   |  389 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 392 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-cns3xxx/pcie.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..fab2ddd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -301,6 +301,7 @@ config ARCH_CNS3XXX
 	select CPU_V6
 	select GENERIC_CLOCKEVENTS
 	select ARM_GIC
+	select PCI_DOMAINS if PCI
 	help
 	  Support for Cavium Networks CNS3XXX platform.
 
@@ -1059,7 +1060,7 @@ config ISA_DMA_API
 	bool
 
 config PCI
-	bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE
+	bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
 	help
 	  Find out whether you have a PCI motherboard. PCI is the name of a
 	  bus system, i.e. the way the CPU talks to the other stuff inside
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 427507a..683f117 100644
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o pm.o
+obj-$(CONFIG_PCI)			+= pcie.o
 obj-$(CONFIG_MACH_CNS3420VB)		+= cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
new file mode 100644
index 0000000..38088c3
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -0,0 +1,389 @@
+/*
+ * PCI-E support for CNS3xxx
+ *
+ * Copyright 2008 Cavium Networks
+ *		  Richard Liu <richard.liu at caviumnetworks.com>
+ * Copyright 2010 MontaVista Software, LLC.
+ *		  Anton Vorontsov <avorontsov at mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/bug.h>
+#include <linux/pci.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+#include <asm/mach/map.h>
+#include <mach/cns3xxx.h>
+#include "core.h"
+
+enum cns3xxx_access_type {
+	CNS3XXX_HOST_TYPE = 0,
+	CNS3XXX_CFG0_TYPE,
+	CNS3XXX_CFG1_TYPE,
+	CNS3XXX_NUM_ACCESS_TYPES,
+};
+
+struct cns3xxx_pcie {
+	struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
+	unsigned int irqs[2];
+	struct resource res_io;
+	struct resource res_mem;
+	struct hw_pci hw_pci;
+
+	bool linked;
+};
+
+static struct cns3xxx_pcie cns3xxx_pcie[]; /* forward decl. */
+
+static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata)
+{
+	struct pci_sys_data *root = sysdata;
+
+	return &cns3xxx_pcie[root->domain];
+}
+
+static struct cns3xxx_pcie *pdev_to_cnspci(struct pci_dev *dev)
+{
+	return sysdata_to_cnspci(dev->sysdata);
+}
+
+static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus)
+{
+	return sysdata_to_cnspci(bus->sysdata);
+}
+
+static void __iomem *cns3xxx_pci_cfg_base(struct pci_bus *bus,
+				  unsigned int devfn, int where)
+{
+	struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus);
+	int busno = bus->number;
+	int slot = PCI_SLOT(devfn);
+	int offset;
+	enum cns3xxx_access_type type;
+	void __iomem *base;
+
+	/* If there is no link, just show the CNS PCI bridge. */
+	if (!cnspci->linked && (busno > 0 || slot > 0))
+		return NULL;
+
+	/*
+	 * The CNS PCI bridge doesn't fit into the PCI hierarchy, though
+	 * we still want to access it. For this to work, we must place
+	 * the first device on the same bus as the CNS PCI bridge.
+	 */
+	if (busno == 0) {
+		if (slot > 1)
+			return NULL;
+		type = slot;
+	} else {
+		type = CNS3XXX_CFG1_TYPE;
+	}
+
+	base = (void __iomem *)cnspci->cfg_bases[type].virtual;
+	offset = ((busno & 0xf) << 20) | (devfn << 12) | (where & 0xffc);
+
+	return base + offset;
+}
+
+static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+				   int where, int size, u32 *val)
+{
+	u32 v;
+	void __iomem *base;
+	u32 mask = (0x1ull << (size * 8)) - 1;
+	int shift = (where % 4) * 8;
+
+	base = cns3xxx_pci_cfg_base(bus, devfn, where);
+	if (!base) {
+		*val = 0xffffffff;
+		return PCIBIOS_SUCCESSFUL;
+	}
+
+	v = __raw_readl(base);
+
+	if (bus->number == 0 && devfn == 0 &&
+			(where & 0xffc) == PCI_CLASS_REVISION) {
+		/*
+		 * RC's class is 0xb, but Linux PCI driver needs 0x604
+		 * for a PCIe bridge. So we must fixup the class code
+		 * to 0x604 here.
+		 */
+		v &= 0xff;
+		v |= 0x604 << 16;
+	}
+
+	*val = (v >> shift) & mask;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int cns3xxx_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+				    int where, int size, u32 val)
+{
+	u32 v;
+	void __iomem *base;
+	u32 mask = (0x1ull << (size * 8)) - 1;
+	int shift = (where % 4) * 8;
+
+	base = cns3xxx_pci_cfg_base(bus, devfn, where);
+	if (!base)
+		return PCIBIOS_SUCCESSFUL;
+
+	v = __raw_readl(base);
+
+	v &= ~(mask << shift);
+	v |= (val & mask) << shift;
+
+	__raw_writel(v, base);
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys)
+{
+	struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys);
+	struct resource *res_io = &cnspci->res_io;
+	struct resource *res_mem = &cnspci->res_mem;
+	struct resource **sysres = sys->resource;
+
+	BUG_ON(request_resource(&iomem_resource, res_io) ||
+	       request_resource(&iomem_resource, res_mem));
+
+	sysres[0] = res_io;
+	sysres[1] = res_mem;
+
+	return 1;
+}
+
+static struct pci_ops cns3xxx_pcie_ops = {
+	.read = cns3xxx_pci_read_config,
+	.write = cns3xxx_pci_write_config,
+};
+
+static struct pci_bus *cns3xxx_pci_scan_bus(int nr, struct pci_sys_data *sys)
+{
+	return pci_scan_bus(sys->busnr, &cns3xxx_pcie_ops, sys);
+}
+
+static int cns3xxx_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
+{
+	struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
+	int irq = cnspci->irqs[slot];
+
+	pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
+		pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
+		PCI_FUNC(dev->devfn), slot, pin, irq);
+
+	return irq;
+}
+
+static struct cns3xxx_pcie cns3xxx_pcie[] = {
+	[0] = {
+		.cfg_bases = {
+			[CNS3XXX_HOST_TYPE] = {
+				.virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT,
+				.pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE),
+				.length = SZ_16M,
+				.type = MT_DEVICE,
+			},
+			[CNS3XXX_CFG0_TYPE] = {
+				.virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT,
+				.pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE),
+				.length = SZ_16M,
+				.type = MT_DEVICE,
+			},
+			[CNS3XXX_CFG1_TYPE] = {
+				.virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT,
+				.pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE),
+				.length = SZ_16M,
+				.type = MT_DEVICE,
+			},
+		},
+		.res_io = {
+			.name = "PCIe0 I/O space",
+			.start = CNS3XXX_PCIE0_IO_BASE,
+			.end = CNS3XXX_PCIE0_IO_BASE + SZ_16M - 1,
+			.flags = IORESOURCE_IO,
+		},
+		.res_mem = {
+			.name = "PCIe0 non-prefetchable",
+			.start = CNS3XXX_PCIE0_MEM_BASE,
+			.end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
+			.flags = IORESOURCE_MEM,
+		},
+		.irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
+		.hw_pci = {
+			.domain = 0,
+			.swizzle = pci_std_swizzle,
+			.nr_controllers = 1,
+			.setup = cns3xxx_pci_setup,
+			.scan = cns3xxx_pci_scan_bus,
+			.map_irq = cns3xxx_pcie_map_irq,
+		},
+	},
+	[1] = {
+		.cfg_bases = {
+			[CNS3XXX_HOST_TYPE] = {
+				.virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT,
+				.pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE),
+				.length = SZ_16M,
+				.type = MT_DEVICE,
+			},
+			[CNS3XXX_CFG0_TYPE] = {
+				.virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT,
+				.pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE),
+				.length = SZ_16M,
+				.type = MT_DEVICE,
+			},
+			[CNS3XXX_CFG1_TYPE] = {
+				.virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT,
+				.pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE),
+				.length = SZ_16M,
+				.type = MT_DEVICE,
+			},
+		},
+		.res_io = {
+			.name = "PCIe1 I/O space",
+			.start = CNS3XXX_PCIE1_IO_BASE,
+			.end = CNS3XXX_PCIE1_IO_BASE + SZ_16M - 1,
+			.flags = IORESOURCE_IO,
+		},
+		.res_mem = {
+			.name = "PCIe1 non-prefetchable",
+			.start = CNS3XXX_PCIE1_MEM_BASE,
+			.end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
+			.flags = IORESOURCE_MEM,
+		},
+		.irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
+		.hw_pci = {
+			.domain = 1,
+			.swizzle = pci_std_swizzle,
+			.nr_controllers = 1,
+			.setup = cns3xxx_pci_setup,
+			.scan = cns3xxx_pci_scan_bus,
+			.map_irq = cns3xxx_pcie_map_irq,
+		},
+	},
+};
+
+static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci)
+{
+	int port = cnspci->hw_pci.domain;
+	u32 reg;
+	unsigned long time;
+
+	reg = __raw_readl(MISC_PCIE_CTRL(port));
+	/*
+	 * Enable Application Request to 1, it will exit L1 automatically,
+	 * but when chip back, it will use another clock, still can use 0x1.
+	 */
+	reg |= 0x3;
+	__raw_writel(reg, MISC_PCIE_CTRL(port));
+
+	pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port);
+	pr_info("PCIe: Port[%d] Check data link layer...", port);
+
+	time = jiffies;
+	while (1) {
+		reg = __raw_readl(MISC_PCIE_PM_DEBUG(port));
+		if (reg & 0x1) {
+			pr_info("Link up.\n");
+			cnspci->linked = 1;
+			break;
+		} else if (time_after(jiffies, time + 50)) {
+			pr_info("Device not found.\n");
+			break;
+		}
+	}
+}
+
+static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci)
+{
+	int port = cnspci->hw_pci.domain;
+	struct pci_sys_data sd = {
+		.domain = port,
+	};
+	struct pci_bus bus = {
+		.number = 0,
+		.ops = &cns3xxx_pcie_ops,
+		.sysdata = &sd,
+	};
+	u32 io_base = cnspci->res_io.start >> 16;
+	u32 mem_base = cnspci->res_mem.start >> 16;
+	u32 host_base = cnspci->cfg_bases[CNS3XXX_HOST_TYPE].pfn;
+	u32 cfg0_base = cnspci->cfg_bases[CNS3XXX_CFG0_TYPE].pfn;
+	u32 devfn = 0;
+	u8 tmp8;
+	u16 pos;
+	u16 dc;
+
+	host_base = (__pfn_to_phys(host_base) - 1) >> 16;
+	cfg0_base = (__pfn_to_phys(cfg0_base) - 1) >> 16;
+
+	pci_bus_write_config_byte(&bus, devfn, PCI_PRIMARY_BUS, 0);
+	pci_bus_write_config_byte(&bus, devfn, PCI_SECONDARY_BUS, 1);
+	pci_bus_write_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, 1);
+
+	pci_bus_read_config_byte(&bus, devfn, PCI_PRIMARY_BUS, &tmp8);
+	pci_bus_read_config_byte(&bus, devfn, PCI_SECONDARY_BUS, &tmp8);
+	pci_bus_read_config_byte(&bus, devfn, PCI_SUBORDINATE_BUS, &tmp8);
+
+	pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_BASE, mem_base);
+	pci_bus_write_config_word(&bus, devfn, PCI_MEMORY_LIMIT, host_base);
+	pci_bus_write_config_word(&bus, devfn, PCI_IO_BASE_UPPER16, io_base);
+	pci_bus_write_config_word(&bus, devfn, PCI_IO_LIMIT_UPPER16, cfg0_base);
+
+	if (!cnspci->linked)
+		return;
+
+	/* Set Device Max_Read_Request_Size to 128 byte */
+	devfn = PCI_DEVFN(1, 0);
+	pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
+	pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+	dc &= ~(0x3 << 12);	/* Clear Device Control Register [14:12] */
+	pci_bus_write_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, dc);
+	pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
+	if (!(dc & (0x3 << 12)))
+		pr_info("PCIe: Set Device Max_Read_Request_Size to 128 byte\n");
+
+	/* Disable PCIe0 Interrupt Mask INTA to INTD */
+	__raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(port));
+}
+
+static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr,
+				      struct pt_regs *regs)
+{
+	if (fsr & (1 << 10))
+		regs->ARM_pc += 4;
+	return 0;
+}
+
+static int __init cns3xxx_pcie_init(void)
+{
+	int i;
+
+	hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS,
+			"imprecise external abort");
+
+	for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) {
+		iotable_init(cns3xxx_pcie[i].cfg_bases,
+			     ARRAY_SIZE(cns3xxx_pcie[i].cfg_bases));
+		cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i));
+		cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i));
+		cns3xxx_pcie_check_link(&cns3xxx_pcie[i]);
+		cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]);
+		pci_common_init(&cns3xxx_pcie[i].hw_pci);
+	}
+
+	pci_assign_unassigned_resources();
+
+	return 0;
+}
+device_initcall(cns3xxx_pcie_init);
-- 
1.7.0.5



From cbouatmailru at gmail.com  Tue Jun  8 13:01:59 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 8 Jun 2010 21:01:59 +0400
Subject: [PATCH 3/4] ARM: cns3xxx: Add support for SDHCI controllers
In-Reply-To: <20100608170030.GA26992@oksana.dev.rtsoft.ru>
References: <20100608170030.GA26992@oksana.dev.rtsoft.ru>
Message-ID: <20100608170159.GC22516@oksana.dev.rtsoft.ru>

CNS3xxx chips have SDHCI-compatible SDIO/SD/MMC controller. This patch
adds the support using sdhci-cns3xxx driver.

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/mach-cns3xxx/Makefile    |    2 +-
 arch/arm/mach-cns3xxx/cns3420vb.c |    3 ++
 arch/arm/mach-cns3xxx/devices.c   |   59 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-cns3xxx/devices.h   |   19 ++++++++++++
 4 files changed, 82 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-cns3xxx/devices.c
 create mode 100644 arch/arm/mach-cns3xxx/devices.h

diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 683f117..11033f1 100644
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,3 +1,3 @@
-obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o pm.o
+obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o pm.o devices.o
 obj-$(CONFIG_PCI)			+= pcie.o
 obj-$(CONFIG_MACH_CNS3420VB)		+= cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 2e30c82..04ae1ce 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -32,6 +32,7 @@
 #include <mach/cns3xxx.h>
 #include <mach/irqs.h>
 #include "core.h"
+#include "devices.h"
 
 /*
  * NOR Flash
@@ -117,6 +118,8 @@ static void __init cns3420_init(void)
 {
 	platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
 
+	cns3xxx_sdhci_init();
+
 	pm_power_off = cns3xxx_power_off;
 }
 
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
new file mode 100644
index 0000000..b01a301
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -0,0 +1,59 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *		  Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *		  Anton Vorontsov <avorontsov at mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/compiler.h>
+#include <linux/platform_device.h>
+#include <mach/cns3xxx.h>
+#include <mach/irqs.h>
+#include "core.h"
+#include "devices.h"
+
+/*
+ * SDHCI
+ */
+static struct resource cns3xxx_sdhci_resources[] = {
+	[0] = {
+		.start = CNS3XXX_SDIO_BASE,
+		.end   = CNS3XXX_SDIO_BASE + SZ_4K - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_CNS3XXX_SDIO,
+		.end   = IRQ_CNS3XXX_SDIO,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device cns3xxx_sdhci_pdev = {
+	.name		= "sdhci-cns3xxx",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(cns3xxx_sdhci_resources),
+	.resource	= cns3xxx_sdhci_resources,
+};
+
+void __init cns3xxx_sdhci_init(void)
+{
+	u32 __iomem *gpioa = __io(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+	u32 gpioa_pins = __raw_readl(gpioa);
+
+	/* MMC/SD pins share with GPIOA */
+	gpioa_pins |= 0x1fff0004;
+	__raw_writel(gpioa_pins, gpioa);
+
+	cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO));
+	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO));
+
+	platform_device_register(&cns3xxx_sdhci_pdev);
+}
diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h
new file mode 100644
index 0000000..0735a45
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/devices.h
@@ -0,0 +1,19 @@
+/*
+ * CNS3xxx common devices
+ *
+ * Copyright 2008 Cavium Networks
+ *		  Scott Shu
+ * Copyright 2010 MontaVista Software, LLC.
+ *		  Anton Vorontsov <avorontsov at mvista.com>
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __CNS3XXX_DEVICES_H_
+#define __CNS3XXX_DEVICES_H_
+
+void __init cns3xxx_sdhci_init(void);
+
+#endif /* __CNS3XXX_DEVICES_H_ */
-- 
1.7.0.5



From cbouatmailru at gmail.com  Tue Jun  8 13:02:17 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 8 Jun 2010 21:02:17 +0400
Subject: [PATCH 4/4] ARM: cns3xxx: Add support for AHCI controllers
In-Reply-To: <20100608170030.GA26992@oksana.dev.rtsoft.ru>
References: <20100608170030.GA26992@oksana.dev.rtsoft.ru>
Message-ID: <20100608170217.GD22516@oksana.dev.rtsoft.ru>

CNS3xxx chips have AHCI-compatible SATA controller. This patch adds
the support using generic ahci_platform driver.

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/mach-cns3xxx/cns3420vb.c |    1 +
 arch/arm/mach-cns3xxx/devices.c   |   52 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-cns3xxx/devices.h   |    1 +
 3 files changed, 54 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 04ae1ce..9df8391 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -118,6 +118,7 @@ static void __init cns3420_init(void)
 {
 	platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
 
+	cns3xxx_ahci_init();
 	cns3xxx_sdhci_init();
 
 	pm_power_off = cns3xxx_power_off;
diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c
index b01a301..50b4d31 100644
--- a/arch/arm/mach-cns3xxx/devices.c
+++ b/arch/arm/mach-cns3xxx/devices.c
@@ -14,6 +14,7 @@
 #include <linux/io.h>
 #include <linux/init.h>
 #include <linux/compiler.h>
+#include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <mach/cns3xxx.h>
 #include <mach/irqs.h>
@@ -21,6 +22,57 @@
 #include "devices.h"
 
 /*
+ * AHCI
+ */
+static struct resource cns3xxx_ahci_resource[] = {
+	[0] = {
+		.start	= CNS3XXX_SATA2_BASE,
+		.end	= CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_CNS3XXX_SATA,
+		.end	= IRQ_CNS3XXX_SATA,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device cns3xxx_ahci_pdev = {
+	.name		= "ahci",
+	.id		= 0,
+	.resource	= cns3xxx_ahci_resource,
+	.num_resources	= ARRAY_SIZE(cns3xxx_ahci_resource),
+	.dev		= {
+		.dma_mask		= &cns3xxx_ahci_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+	},
+};
+
+void __init cns3xxx_ahci_init(void)
+{
+	u32 tmp;
+
+	tmp = __raw_readl(MISC_SATA_POWER_MODE);
+	tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */
+	tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */
+	__raw_writel(tmp, MISC_SATA_POWER_MODE);
+
+	/* Enable SATA PHY */
+	cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0);
+	cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1);
+
+	/* Enable SATA Clock */
+	cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA);
+
+	/* De-Asscer SATA Reset */
+	cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA));
+
+	platform_device_register(&cns3xxx_ahci_pdev);
+}
+
+/*
  * SDHCI
  */
 static struct resource cns3xxx_sdhci_resources[] = {
diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h
index 0735a45..27e15a1 100644
--- a/arch/arm/mach-cns3xxx/devices.h
+++ b/arch/arm/mach-cns3xxx/devices.h
@@ -14,6 +14,7 @@
 #ifndef __CNS3XXX_DEVICES_H_
 #define __CNS3XXX_DEVICES_H_
 
+void __init cns3xxx_ahci_init(void);
 void __init cns3xxx_sdhci_init(void);
 
 #endif /* __CNS3XXX_DEVICES_H_ */
-- 
1.7.0.5


From buytenh at wantstofly.org  Tue Jun  8 13:08:46 2010
From: buytenh at wantstofly.org (Lennert Buytenhek)
Date: Tue, 8 Jun 2010 19:08:46 +0200
Subject: [PATCH 1/2] mv643xx_eth: disable csum offloading if the hw
	limited by max size
In-Reply-To: <1275827336-31111-1-git-send-email-saeed@marvell.com>
References: <1275827336-31111-1-git-send-email-saeed@marvell.com>
Message-ID: <20100608170846.GR1743@mail.wantstofly.org>

On Sun, Jun 06, 2010 at 03:28:55PM +0300, Saeed Bishara wrote:

> diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
> index e345ec8..79243dd 100644
> --- a/drivers/net/mv643xx_eth.c
> +++ b/drivers/net/mv643xx_eth.c
> @@ -289,6 +289,7 @@ struct mv643xx_eth_shared_private {
>  	unsigned int t_clk;
>  	int extended_rx_coal_limit;
>  	int tx_bw_control;
> +	int tx_csum_limit;
>  };
>  
>  #define TX_BW_CONTROL_ABSENT		0
> @@ -2468,6 +2469,14 @@ static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
>  	mv643xx_eth_recalc_skb_size(mp);
>  	tx_set_rate(mp, 1000000000, 16777216);
>  
> +	if (mp->shared->tx_csum_limit && dev->mtu > mp->shared->tx_csum_limit) {
> +		dev->features &= ~NETIF_F_IP_CSUM;
> +		dev->vlan_features &= ~NETIF_F_IP_CSUM;
> +	} else {
> +		dev->features |= NETIF_F_IP_CSUM;
> +		dev->vlan_features |= NETIF_F_IP_CSUM;
> +	}

I wonder if it would be better to still advertise NETIF_F_IP_CSUM in
this case, but just call skb_checksum_help() if skb->len is > dev->mtu
in txq_submit_skb(), like we do for the case where the ethernet header
is of an unsupported length -- that way, we'd still have hardware
checksum offload for TX packets that _do_ fit inside the hardware TX
fifo, e.g. when communicating with hosts on another subnet where the
default MTU is used.


> diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
> index cbbbe9b..7402718 100644
> --- a/include/linux/mv643xx_eth.h
> +++ b/include/linux/mv643xx_eth.h
> @@ -19,6 +19,10 @@ struct mv643xx_eth_shared_platform_data {
>  	struct mbus_dram_target_info	*dram;
>  	struct platform_device	*shared_smi;
>  	unsigned int		t_clk;
> +	/*
> +	 * Max packet size for Tx IP/Layer 4 checksum (0 -> no limit)

There's always a limit. :-)  You might as well just fill in the right
values for orion5x/kw/dd/loki while you're at it.


thanks,
Lennert


From buytenh at wantstofly.org  Tue Jun  8 13:09:48 2010
From: buytenh at wantstofly.org (Lennert Buytenhek)
Date: Tue, 8 Jun 2010 19:09:48 +0200
Subject: [PATCH 2/2] set packet size limit for the mv643xx csum offloading
In-Reply-To: <1275827336-31111-2-git-send-email-saeed@marvell.com>
References: <1275827336-31111-1-git-send-email-saeed@marvell.com>
	<1275827336-31111-2-git-send-email-saeed@marvell.com>
Message-ID: <20100608170948.GS1743@mail.wantstofly.org>

On Sun, Jun 06, 2010 at 03:28:56PM +0300, Saeed Bishara wrote:

> The mv643xx ethernet controller limits the packet size for the TX
> checksum offloading. this patch sets this limits for the needed
> devices.
> 
> Signed-off-by: Saeed Bishara <saeed at marvell.com>
> ---
>  arch/arm/mach-dove/common.c     |    1 +
>  arch/arm/mach-kirkwood/common.c |    1 +
>  2 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
> index 5da2cf4..473ce0b 100644
> --- a/arch/arm/mach-dove/common.c
> +++ b/arch/arm/mach-dove/common.c
> @@ -149,6 +149,7 @@ void __init dove_ehci1_init(void)
>  struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
>  	.t_clk		= 0,
>  	.dram		= &dove_mbus_dram_info,
> +	.tx_csum_limit	= 1600,

Assuming that 1600 is exactly the right value (and not 1599 or 1601 etc),

Acked-by: Lennert Buytenhek <buytenh at wantstofly.org>

Can you fill in for orion5x/dd/loki as well?


From milinevskyy at gmail.com  Tue Jun  8 13:24:40 2010
From: milinevskyy at gmail.com (Dmytro Milinevskyy)
Date: Tue, 08 Jun 2010 20:24:40 +0300
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
Message-ID: <4c0e7d5a.0c3ddf0a.2771.ffffd485@mx.google.com>

Hello!
This patch adds support for the OpenRD Ultimate machine(could be found at http://www.arm.linux.org.uk/developer/machines/list.php?id=2884)

It slightly differs from Client version.

Also this patch adds correction for PHY address for Ultimate version.

Regards,

-- Dmytro Milinevskyy

Signed-off-by: Dmytro Milinevskyy <milinevskyy at gmail.com>
---
 arch/arm/mach-kirkwood/Kconfig        |    7 ++++++
 arch/arm/mach-kirkwood/openrd-setup.c |   34 +++++++++++++++++++++++++++++---
 2 files changed, 37 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 29b2163..110a3b8 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell OpenRD Client Board.
 
+config MACH_OPENRD_ULTIMATE
+	bool "Marvell OpenRD Ultimate Board"
+	select MACH_OPENRD
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell OpenRD Ultimate Board.
+
 config MACH_NETSPACE_V2
 	bool "LaCie Network Space v2 NAS Board"
 	help
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec..5d6797a 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -47,6 +47,14 @@ static struct mv643xx_eth_platform_data openrd_ge01_data = {
 	.phy_addr	= MV643XX_ETH_PHY_ADDR(24),
 };
 
+static struct mv643xx_eth_platform_data openrd_ultimate_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct mv643xx_eth_platform_data openrd_ultimate_ge01_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
+};
+
 static struct mv_sata_platform_data openrd_sata_data = {
 	.n_ports	= 2,
 };
@@ -73,9 +81,14 @@ static void __init openrd_init(void)
 
 	kirkwood_ehci_init();
 
-	kirkwood_ge00_init(&openrd_ge00_data);
-	if (machine_is_openrd_client())
-		kirkwood_ge01_init(&openrd_ge01_data);
+	if (machine_is_openrd_ultimate()) {
+		kirkwood_ge00_init(&openrd_ultimate_ge00_data);
+		kirkwood_ge01_init(&openrd_ultimate_ge01_data);
+	} else {
+		kirkwood_ge00_init(&openrd_ge00_data);
+		if (machine_is_openrd_client())
+			kirkwood_ge01_init(&openrd_ge01_data);
+	}
 	kirkwood_sata_init(&openrd_sata_data);
 	kirkwood_sdio_init(&openrd_mvsdio_data);
 
@@ -84,7 +97,7 @@ static void __init openrd_init(void)
 
 static int __init openrd_pci_init(void)
 {
-	if (machine_is_openrd_base() || machine_is_openrd_client())
+	if (machine_is_openrd_base() || machine_is_openrd_client() || machine_is_openrd_ultimate())
 		kirkwood_pcie_init();
 
 	return 0;
@@ -116,3 +129,16 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
 	.timer		= &kirkwood_timer,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_MACH_OPENRD_ULTIMATE
+MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
+	/* Maintainer: Dhaval Vasa <dhaval.vasa at einfochips.com> */
+	.phys_io	= KIRKWOOD_REGS_PHYS_BASE,
+	.io_pg_offst	= ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+	.boot_params	= 0x00000100,
+	.init_machine	= openrd_init,
+	.map_io		= kirkwood_map_io,
+	.init_irq	= kirkwood_init_irq,
+	.timer		= &kirkwood_timer,
+MACHINE_END
+#endif
-- 
1.7.1



From robert.jarzmik at free.fr  Tue Jun  8 13:31:58 2010
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Tue, 08 Jun 2010 19:31:58 +0200
Subject: [PATCH] mioa701: fix camera regression
In-Reply-To: <Pine.LNX.4.64.1006032058380.19573@axis700.grange> (Guennadi
	Liakhovetski's message of "Thu\,
	3 Jun 2010 20\:59\:09 +0200 \(CEST\)")
References: <1275514190-32006-1-git-send-email-robert.jarzmik@free.fr>
	<Pine.LNX.4.64.1006032058380.19573@axis700.grange>
Message-ID: <87pr01mnw1.fsf@free.fr>

> On Wed, 2 Jun 2010, Robert Jarzmik wrote:
>
>> Since commit a48c24a696f0d93c49f913b7818e9819612b1f4e, the
>> camera is not working anymore.
>> 
>> After the v4l2 migration, the mt9m111 camera board
>> information was not passed to the i2c layer anymore, but
>> stored for future use of v4l2 (through soc_camera).
>> 
>> Because mioa701_i2c_devices[] was tagged as "__initdata",
>> and because after the v4l2 migration, the new structure
>> "iclink" references it, the mt9m111 driver is not probed
>> anymore, as part of "iclink" is not valid (discarded after
>> kernel init).
>> 
>> Although there is not compilation error, nor runtime oops,
>> this patch restores a working camera on the mioa701 board.
>> 
>> Signed-off-by: Robert Jarzmik <robert.jarzmik at free.fr>
>
> Acked-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
>
>> 
>> --
>> Eric, could you schedule that into your fix branch please ?

Ping.

--
Robert


From joe at perches.com  Tue Jun  8 13:38:51 2010
From: joe at perches.com (Joe Perches)
Date: Tue, 08 Jun 2010 10:38:51 -0700
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
In-Reply-To: <4c0e7d5a.0c3ddf0a.2771.ffffd485@mx.google.com>
References: <4c0e7d5a.0c3ddf0a.2771.ffffd485@mx.google.com>
Message-ID: <1276018731.1571.518.camel@Joe-Laptop.home>

On Tue, 2010-06-08 at 20:24 +0300, Dmytro Milinevskyy wrote:
> @@ -73,9 +81,14 @@ static void __init openrd_init(void)
>  
>  	kirkwood_ehci_init();
>  
> -	kirkwood_ge00_init(&openrd_ge00_data);
> -	if (machine_is_openrd_client())
> -		kirkwood_ge01_init(&openrd_ge01_data);
> +	if (machine_is_openrd_ultimate()) {
> +		kirkwood_ge00_init(&openrd_ultimate_ge00_data);
> +		kirkwood_ge01_init(&openrd_ultimate_ge01_data);
> +	} else {
> +		kirkwood_ge00_init(&openrd_ge00_data);
> +		if (machine_is_openrd_client())
> +			kirkwood_ge01_init(&openrd_ge01_data);
> +	}

Perhaps some utility functions like:

	if (kirkwood_has_multiple_ethernets())?

> @@ -84,7 +97,7 @@ static void __init openrd_init(void)
>  
>  static int __init openrd_pci_init(void)
>  {
> -	if (machine_is_openrd_base() || machine_is_openrd_client())
> +	if (machine_is_openrd_base() || machine_is_openrd_client() || machine_is_openrd_ultimate())

	if (kirkwood_has_pcie()?




From buytenh at wantstofly.org  Tue Jun  8 13:45:36 2010
From: buytenh at wantstofly.org (Lennert Buytenhek)
Date: Tue, 8 Jun 2010 19:45:36 +0200
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
In-Reply-To: <4c0e7d5a.0c3ddf0a.2771.ffffd485@mx.google.com>
References: <4c0e7d5a.0c3ddf0a.2771.ffffd485@mx.google.com>
Message-ID: <20100608174536.GW1743@mail.wantstofly.org>

On Tue, Jun 08, 2010 at 08:24:40PM +0300, Dmytro Milinevskyy wrote:

> diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
> index ad3f1ec..5d6797a 100644
> --- a/arch/arm/mach-kirkwood/openrd-setup.c
> +++ b/arch/arm/mach-kirkwood/openrd-setup.c
> @@ -47,6 +47,14 @@ static struct mv643xx_eth_platform_data openrd_ge01_data = {
>  	.phy_addr	= MV643XX_ETH_PHY_ADDR(24),
>  };
>  
> +static struct mv643xx_eth_platform_data openrd_ultimate_ge00_data = {
> +	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
> +};
> +
> +static struct mv643xx_eth_platform_data openrd_ultimate_ge01_data = {
> +	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
> +};
> +
>  static struct mv_sata_platform_data openrd_sata_data = {
>  	.n_ports	= 2,
>  };
> @@ -73,9 +81,14 @@ static void __init openrd_init(void)
>  
>  	kirkwood_ehci_init();
>  
> -	kirkwood_ge00_init(&openrd_ge00_data);
> -	if (machine_is_openrd_client())
> -		kirkwood_ge01_init(&openrd_ge01_data);
> +	if (machine_is_openrd_ultimate()) {
> +		kirkwood_ge00_init(&openrd_ultimate_ge00_data);
> +		kirkwood_ge01_init(&openrd_ultimate_ge01_data);
> +	} else {
> +		kirkwood_ge00_init(&openrd_ge00_data);
> +		if (machine_is_openrd_client())
> +			kirkwood_ge01_init(&openrd_ge01_data);
> +	}

Just write the PHY addresses into openrd_ge0[01]_data here iff
machine_is_openrd_ultimate()?


From ryan at bluewatersys.com  Tue Jun  8 15:27:03 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Wed, 09 Jun 2010 07:27:03 +1200
Subject: [PATCH 1/3] EP93xx: Add i2s core support
In-Reply-To: <0D753D10438DA54287A00B027084269763708AFD76@AUSP01VMBX24.collaborationhost.net>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<1275991272-30122-2-git-send-email-ryan@bluewatersys.com>
	<0D753D10438DA54287A00B027084269763708AFD76@AUSP01VMBX24.collaborationhost.net>
Message-ID: <4C0E9987.2010907@bluewatersys.com>

H Hartley Sweeten wrote:
> On Tuesday, June 08, 2010 3:01 AM, Ryan Mallon wrote:
>> Add core support for EP93xx i2s audio
>>
>> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
> 
> Looks good.
> 
> Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>
> 

Okay, I have Liam and Hartley's acks on this one and Liam's on 3/3.
Mark, do you want to apply the other two patches to your tree, or should
they go via the arm tree?

Thanks,
~Ryan



From marek.vasut at gmail.com  Tue Jun  8 15:36:30 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Tue, 8 Jun 2010 21:36:30 +0200
Subject: [PATCH] pxa2xx/cpufreq: Fix DRI computation
In-Reply-To: <87ljap7opx.fsf@free.fr>
References: <1275698808-31166-1-git-send-email-marek.vasut@gmail.com>
	<87ljap7opx.fsf@free.fr>
Message-ID: <201006082136.30785.marek.vasut@gmail.com>

Dne ?t 8. ?ervna 2010 13:23:06 Robert Jarzmik napsal(a):
> Marek Vasut <marek.vasut at gmail.com> writes:
> > The DRI field was incorrectly computed, causing various hangs and weird
> > behaviour on PXA2xx machines. This patch introduces the DRI computation
> > according to the PXA255 (January 2004) and PXA270 (MV-S301039-00 Rev. A)
> > datasheets.
> > 
> > NOTE: The CPU type is checked only once, so the code is a little bit
> > faster now.
> > 
> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> > ---
> > 
> >  arch/arm/mach-pxa/cpufreq-pxa2xx.c |   33
> >  +++++++++++++++++++++++++++++---- 1 files changed, 29 insertions(+), 4
> >  deletions(-)
> > 
> > diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> > b/arch/arm/mach-pxa/cpufreq-pxa2xx.c index 9e4d981..5373db0 100644
> > --- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> > +++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> > @@ -251,17 +251,42 @@ static void init_sdram_rows(void)
> > 
> >  	if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
> >  	
> >  		drac0 = MDCNFG_DRAC0(mdcnfg);
> > 
> > -	sdram_rows = 1 << (11 + max(drac0, drac2));
> > +	sdram_rows = 11 + max(drac0, drac2);
> 
> I don't think that's correct.
> From DRACn, you learn that SDRAM row is selected from 11+DRACn bits. That
> means that if drac == 2, then the SDRAM row is a number between 0 and
> (11+drac0) - 1. That in turn means that the number of SDRAM rows is : 2 ^
> (11 + drac0). Example:
>  - drac0 = 2 : row encoded on 13 bits => 2^13 rows (ie. 1 << (11 + 2)).

That I'm aware of, but are you sure the TRM means it that way ?
> 
> >  static u32 mdrefr_dri(unsigned int freq)
> >  {
> >  
> >  	u32 dri = 0;
> > 
> > -	if (cpu_is_pxa25x())
> > -		dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
> > +	/*
> > +	 * PXA255 (6.5.3):
> > +	 * 	DRI = (Refresh time / rows * memory clock frequency) / 32
> > +	 * PXA270 (Table 91):
> > +	 * 	DRI = (Refresh time / rows * memory clock frequency - 31) / 32
> > +	 *
> > +	 * Memory clock frequency is in MHz here! (Refresh time is in ms).
> > +	 */
> 
> I don't agree here either. The "freq" variable is in kHz.

That's concerning the TRM, not the freq value. In TRM, it's in MHz.

> It comes from
> "new_freq_mem = pxa_freq_settings[idx].membus;" in pxa_set_target(). The
> membus value is in kHz, as in tables pxaXXX_freqs (see 104000 and 208000,
> second column in pxa27x_freqs for example). As refresh time is in ms,
> there is no need for a 1000th multiplier.
> 
> And my understanding is that the legacy formula is incorrect, as you
> discovered it. Yet it should be, IMO :
>     if (cpu_is_pxa27x())
> -       dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
> +       dri = ((freq * SDRAM_TREF) / sdram_rows - 31) / 32;
> 
> This is the only change to apply IMHO.

Ok, but still, even though I fixed it your way, it doesn't fix the real problem, 
I'll recheck though, I just need a few days too.

Cheers
> 
> Can you confirm my analysis ?


From milinevskyy at gmail.com  Tue Jun  8 15:47:47 2010
From: milinevskyy at gmail.com (Dmytro Milinevskyy)
Date: Tue, 08 Jun 2010 22:47:47 +0300
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
Message-ID: <4c0e9ee6.8704df0a.2e71.ffffdf65@mx.google.com>

Hi!
This patch adds support for the OpenRD Ultimate machine(could be found at http://www.arm.linux.org.uk/developer/machines/list.php?id=2884)

Besides adding machine description this patch adds correction for PHY address for Ultimate version.

Differences from the previous attempt:
 - Applied suggestion from Lennert Buytenhek to change PHY addresses in instances of mv643xx_eth_platform_data in case of ultimate version.

Regards,

-- Dmytro Milinevskyy

Signed-off-by: Dmytro Milinevskyy <milinevskyy at gmail.com>
---
 arch/arm/mach-kirkwood/Kconfig        |    7 ++++++
 arch/arm/mach-kirkwood/openrd-setup.c |   34 +++++++++++++++++++++++++++++---
 2 files changed, 37 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 29b2163..110a3b8 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell OpenRD Client Board.
 
+config MACH_OPENRD_ULTIMATE
+	bool "Marvell OpenRD Ultimate Board"
+	select MACH_OPENRD
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell OpenRD Ultimate Board.
+
 config MACH_NETSPACE_V2
 	bool "LaCie Network Space v2 NAS Board"
 	help
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec..5d6797a 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -47,6 +47,14 @@ static struct mv643xx_eth_platform_data openrd_ge01_data = {
 	.phy_addr	= MV643XX_ETH_PHY_ADDR(24),
 };
 
+static struct mv643xx_eth_platform_data openrd_ultimate_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(0),
+};
+
+static struct mv643xx_eth_platform_data openrd_ultimate_ge01_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(1),
+};
+
 static struct mv_sata_platform_data openrd_sata_data = {
 	.n_ports	= 2,
 };
@@ -73,9 +81,14 @@ static void __init openrd_init(void)
 
 	kirkwood_ehci_init();
 
-	kirkwood_ge00_init(&openrd_ge00_data);
-	if (machine_is_openrd_client())
-		kirkwood_ge01_init(&openrd_ge01_data);
+	if (machine_is_openrd_ultimate()) {
+		kirkwood_ge00_init(&openrd_ultimate_ge00_data);
+		kirkwood_ge01_init(&openrd_ultimate_ge01_data);
+	} else {
+		kirkwood_ge00_init(&openrd_ge00_data);
+		if (machine_is_openrd_client())
+			kirkwood_ge01_init(&openrd_ge01_data);
+	}
 	kirkwood_sata_init(&openrd_sata_data);
 	kirkwood_sdio_init(&openrd_mvsdio_data);
 
@@ -84,7 +97,7 @@ static void __init openrd_init(void)
 
 static int __init openrd_pci_init(void)
 {
-	if (machine_is_openrd_base() || machine_is_openrd_client())
+	if (machine_is_openrd_base() || machine_is_openrd_client() || machine_is_openrd_ultimate())
 		kirkwood_pcie_init();
 
 	return 0;
@@ -116,3 +129,16 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
 	.timer		= &kirkwood_timer,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_MACH_OPENRD_ULTIMATE
+MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
+	/* Maintainer: Dhaval Vasa <dhaval.vasa at einfochips.com> */
+	.phys_io	= KIRKWOOD_REGS_PHYS_BASE,
+	.io_pg_offst	= ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+	.boot_params	= 0x00000100,
+	.init_machine	= openrd_init,
+	.map_io		= kirkwood_map_io,
+	.init_irq	= kirkwood_init_irq,
+	.timer		= &kirkwood_timer,
+MACHINE_END
+#endif
-- 
1.7.1



From linus.walleij at stericsson.com  Tue Jun  8 16:28:11 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 8 Jun 2010 22:28:11 +0200
Subject: [PATCH] ARM: correct PL080 editor mistake
Message-ID: <1276028891-20389-1-git-send-email-linus.walleij@stericsson.com>

This PL008 among all other variabled named PL080 doesn't seem
right. Fix it.

Cc: Ben Dooks <ben-linux at fluff.org>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/include/asm/hardware/pl080.h |    2 +-
 arch/arm/mach-s3c64xx/dma.c           |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
index 6a6c66b..f70e1e9 100644
--- a/arch/arm/include/asm/hardware/pl080.h
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -43,7 +43,7 @@
 
 /* Per channel configuration registers */
 
-#define PL008_Cx_STRIDE				(0x20)
+#define PL080_Cx_STRIDE				(0x20)
 #define PL080_Cx_BASE(x)			((0x100 + (x * 0x20)))
 #define PL080_Cx_SRC_ADDR(x)			((0x100 + (x * 0x20)))
 #define PL080_Cx_DST_ADDR(x)			((0x104 + (x * 0x20)))
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 5567e03..e7d03ab 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -697,7 +697,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
 		chptr->number = chno;
 		chptr->dmac = dmac;
 		chptr->regs = regptr;
-		regptr += PL008_Cx_STRIDE;
+		regptr += PL080_Cx_STRIDE;
 	}
 
 	/* for the moment, permanently enable the controller */
-- 
1.6.3.3



From linux at arm.linux.org.uk  Tue Jun  8 16:39:09 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 8 Jun 2010 21:39:09 +0100
Subject: Kernel development news
Message-ID: <20100608203909.GI25370@n2100.arm.linux.org.uk>

Please see Linus' release notes for -rc2.

Linus is unwilling to even take the fixes which are in my master
branch, so I guess there's not much point committing anything
further until Linus returns from his vacation, and even then post
-rc3, whenever that may be.

There's no clue if Linus will even take what's in the master branch
for an -rc kernel...

So I guess we have even more time to concentrate on fixing the
defconfig problem...


From razzor at kopf-tisch.de  Tue Jun  8 16:32:38 2010
From: razzor at kopf-tisch.de (Olaf Rempel)
Date: Tue,  8 Jun 2010 22:32:38 +0200
Subject: [PATCH] orion/kirkwood: reset PCIe unit on boot
Message-ID: <1276029158-22159-1-git-send-email-razzor@kopf-tisch.de>

Patch found in QNAPs vendor source package, with some cleanups
(proper defines, shortened max. timeout from 1s to 200ms).

Without this patch the PCIe SATA controller (Marvell 88sx7042/sata_mv)
in my QNAP TS-419P (Marvell 88f6281/Kirkwood) stops working after a
few minutes.
The symptomes are described in this thread:
http://marc.info/?l=linux-ide&m=124822863706181&w=2
---
 arch/arm/plat-orion/pcie.c |   34 ++++++++++++++++++++++++++++++++++
 1 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index 54c84a4..779553a 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -13,6 +13,7 @@
 #include <linux/mbus.h>
 #include <asm/mach/pci.h>
 #include <plat/pcie.h>
+#include <linux/delay.h>
 
 /*
  * PCIe unit register offsets.
@@ -46,6 +47,8 @@
 #define  PCIE_STAT_BUS_OFFS		8
 #define  PCIE_STAT_BUS_MASK		0xff
 #define  PCIE_STAT_LINK_DOWN		1
+#define PCIE_DEBUG_CTRL         0x1a60
+#define  PCIE_DEBUG_SOFT_RESET		(1<<20)
 
 
 u32 __init orion_pcie_dev_id(void __iomem *base)
@@ -85,6 +88,32 @@ void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
 	writel(stat, base + PCIE_STAT_OFF);
 }
 
+void __init orion_pcie_reset(void __iomem *base)
+{
+	u32 reg;
+	int i;
+
+	/*
+	 * MV-S104860-U0, Rev. C:
+	 * PCI Express Unit Soft Reset
+	 * When set, generates an internal reset in the PCI Express unit.
+	 * This bit should be cleared after the link is re-established.
+	 */
+	reg = readl(base + PCIE_DEBUG_CTRL);
+	reg |= PCIE_DEBUG_SOFT_RESET;
+	writel(reg, base + PCIE_DEBUG_CTRL);
+
+	for (i = 0; i < 20; i++) {
+		mdelay(10);
+
+		if (orion_pcie_link_up(base))
+			break;
+	}
+
+	reg &= ~(PCIE_DEBUG_SOFT_RESET);
+	writel(reg, base + PCIE_DEBUG_CTRL);
+}
+
 /*
  * Setup PCIE BARs and Address Decode Wins:
  * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
@@ -153,6 +182,11 @@ void __init orion_pcie_setup(void __iomem *base,
 	u32 mask;
 
 	/*
+	 * soft reset PCIe unit
+	 */
+	orion_pcie_reset(base);
+
+	/*
 	 * Point PCIe unit MBUS decode windows to DRAM space.
 	 */
 	orion_pcie_setup_wins(base, dram);
-- 
1.6.3.3



From ryan at bluewatersys.com  Tue Jun  8 16:51:07 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Wed, 09 Jun 2010 08:51:07 +1200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100608131007.GE25370@n2100.arm.linux.org.uk>
References: <4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<4C0E3CAF.4050409@weinigel.se>
	<20100608131007.GE25370@n2100.arm.linux.org.uk>
Message-ID: <4C0EAD3B.8010404@bluewatersys.com>

Russell King - ARM Linux wrote:
> On Tue, Jun 08, 2010 at 02:50:55PM +0200, Christer Weinigel wrote:
>> Linus isn't stupid.  If you explain what you are doing and that the goal  
>> is to reduce the set of defconfigs to just one per processor family, and  
>> that it will reduce the churn in the end, I think Linus will listen.
>
> It's also not just about the number of defconfigs.  Linus had other
> valid points too - for example, you can't review the changes to them
> properly, because any change to them is far too noisy.  That point
> doesn't go away by reducing the number of defconfigs.

Part of the problem with the defconfigs is that they are auto-generated
and contain a lot of useless information. As you point out, diffs on
defconfigs tend to result in a lot of noise which makes viewing changes
very difficult.

Striping the spitz defconfig back for example:

  ryan at okiwi:configs$ wc -l spitz_defconfig
  1820 spitz_defconfig

  ryan at okiwi:configs$ grep -v "is not set" spitz_defconfig | grep -v
"^#" | wc -l
  641

So removing all the comments and non-set options makes the defconfig
about 1/3 the size. If the defconfigs were generated by hand, or a
proper set of tools, then they could be much less verbose and diffs for
things like adding or removing a single config option would actually be
readable.

If we want to have individual board configurations in the kernel, then
the information has to live somewhere. Whether it is defconfig, KConfig,
Documentation, whatever, the information will still take up a similar
amount of space, and the process of moving the information will generate
a load of diffstat noise.

I think deleting defconfigs is a good first step. Although there will be
diffstat noise, it will also be clear that the net result is that
thousands of lines are being removed, which is a good thing. Having a
better way of generating defconfigs (or however the information is
stored) would fix the general problem of diffstat noise when changes are
made.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From ryan at bluewatersys.com  Tue Jun  8 16:52:24 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Wed, 09 Jun 2010 08:52:24 +1200
Subject: [PATCH] ep93xx: register backlight driver
In-Reply-To: <0D753D10438DA54287A00B027084269763708AFE70@AUSP01VMBX24.collaborationhost.net>
References: <0D753D10438DA54287A00B0270842697636EE74BB1@AUSP01VMBX24.collaborationhost.net>
	<0D753D10438DA54287A00B027084269763708AFE70@AUSP01VMBX24.collaborationhost.net>
Message-ID: <4C0EAD88.3070300@bluewatersys.com>

H Hartley Sweeten wrote:
> On Monday, May 10, 2010 6:58 PM, H Hartley Sweeten wrote:
>> Add the platform registration for the ep93xx backlight driver
>> that is now queued in the backlight tree.
>>
>> Since the pwm BRIGHT signal only functions if the video system
>> is operating, register the backlight when the framebuffer device
>> is registered.
>>
>> Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
>> Cc: Ryan Mallon <ryan at bluewatersys.com>
> 
> Ryan,
> 
> The EP93xx backlight driver is now merged.
> commit 08b3924b24cdb1942393dc3009335a2153bd2eac
> 
> Do you have any issues with this patch to enable it?
> 
> Regards,
> Hartley
> 
> ---
> 
> This is based off next-20100510, if needed I can rebase it off
> another tree.
> 
> diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
> index 8d3f77e..07d7bb9 100644
> --- a/arch/arm/mach-ep93xx/core.c
> +++ b/arch/arm/mach-ep93xx/core.c
> @@ -568,6 +568,11 @@ static struct platform_device ep93xx_fb_device = {
>  	.resource		= ep93xx_fb_resource,
>  };
>  
> +static struct platform_device ep93xx_bl_device = {
> +	.name		= "ep93xx-bl",
> +	.id		= -1,
> +};
> +
>  /**
>   * ep93xx_register_fb - Register the framebuffer platform device.
>   * @data:	platform specific framebuffer configuration (__initdata)
> @@ -576,6 +581,7 @@ void __init ep93xx_register_fb(struct ep93xxfb_mach_info *data)
>  {
>  	ep93xxfb_data = *data;
>  	platform_device_register(&ep93xx_fb_device);
> +	platform_device_register(&ep93xx_bl_device);
>  }

This is fine.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From linux at arm.linux.org.uk  Tue Jun  8 17:22:53 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 8 Jun 2010 22:22:53 +0100
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C0EAD3B.8010404@bluewatersys.com>
References: <4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<4C0E3CAF.4050409@weinigel.se>
	<20100608131007.GE25370@n2100.arm.linux.org.uk>
	<4C0EAD3B.8010404@bluewatersys.com>
Message-ID: <20100608212253.GJ25370@n2100.arm.linux.org.uk>

On Wed, Jun 09, 2010 at 08:51:07AM +1200, Ryan Mallon wrote:
> Striping the spitz defconfig back for example:
> 
>   ryan at okiwi:configs$ wc -l spitz_defconfig
>   1820 spitz_defconfig
> 
>   ryan at okiwi:configs$ grep -v "is not set" spitz_defconfig | grep -v
> "^#" | wc -l
>   641
> 
> So removing all the comments and non-set options makes the defconfig
> about 1/3 the size. If the defconfigs were generated by hand, or a
> proper set of tools, then they could be much less verbose and diffs for
> things like adding or removing a single config option would actually be
> readable.

Have you tried to use this stripped back defconfig file?

> I think deleting defconfigs is a good first step. Although there will be
> diffstat noise, it will also be clear that the net result is that
> thousands of lines are being removed, which is a good thing.

You're forgetting that if the defconfigs go, then kautobuild might as
well be taken offline because it'll have nothing to build.  It also
means it'll be pointless participating in the build side of linux-next
since that too won't have any useful build coverage.

And at that point, I won't know if the changes I make to the kernel
start breaking EP93xx or whatever other platform - and the same will
be true for other kernel developers.

What's at stake here is not just a bunch of files in the kernel.  It's
much more than that - it's our build testing coverage.

Of course, if people don't mind kernels being broken, and don't mind
changes not being integrated tested in linux-next, we should delete
the defconfig files right now because they wouldn't be serving much
of a useful purpose.


From ryan at bluewatersys.com  Tue Jun  8 17:32:20 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Wed, 09 Jun 2010 09:32:20 +1200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100608212253.GJ25370@n2100.arm.linux.org.uk>
References: <4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<4C0E3CAF.4050409@weinigel.se>
	<20100608131007.GE25370@n2100.arm.linux.org.uk>
	<4C0EAD3B.8010404@bluewatersys.com>
	<20100608212253.GJ25370@n2100.arm.linux.org.uk>
Message-ID: <4C0EB6E4.3070900@bluewatersys.com>

Russell King - ARM Linux wrote:
> On Wed, Jun 09, 2010 at 08:51:07AM +1200, Ryan Mallon wrote:
>> Striping the spitz defconfig back for example:
>>
>>   ryan at okiwi:configs$ wc -l spitz_defconfig
>>   1820 spitz_defconfig
>>
>>   ryan at okiwi:configs$ grep -v "is not set" spitz_defconfig | grep -v
>> "^#" | wc -l
>>   641
>>
>> So removing all the comments and non-set options makes the defconfig
>> about 1/3 the size. If the defconfigs were generated by hand, or a
>> proper set of tools, then they could be much less verbose and diffs for
>> things like adding or removing a single config option would actually be
>> readable.
> 
> Have you tried to use this stripped back defconfig file?

No, I haven't. I'm guessing it doesn't work straight off, but the point
is that the defconfigs do contain a lot of unneeded noise.

>> I think deleting defconfigs is a good first step. Although there will be
>> diffstat noise, it will also be clear that the net result is that
>> thousands of lines are being removed, which is a good thing.
> 
> You're forgetting that if the defconfigs go, then kautobuild might as
> well be taken offline because it'll have nothing to build.  It also
> means it'll be pointless participating in the build side of linux-next
> since that too won't have any useful build coverage.

I'm not suggesting deleting all of the defconfigs, I meant removing them
until we have one or two per mach directory. I haven't used kautobuild,
but surely having to build less kernels to support the same number of
boards is good?

Getting the defconfigs down to one or two per mach is, IMHO, a good
first step. Whatever gets decided as the best approach from there will
be easier since it will be a case of migrating ~30 defconfigs to the new
format rather than ~170. It also has the side effect benefit getting
developers to start writing the mach directories with single kernel
building in mind.

The SPEAr300, for example, couldn't be built into one kernel because of
a bunch of naming conflicts in #defines, etc. The patch series I posted
makes it possible to build all of them into one basically by doing a
mass rename. Yeah, I know, more noise :-), but the result is better. If
we do it once, and do it now, and enforce stricter rules in the future,
then the noise will be far greatly reduced in future, at the cost of
slightly noisier diffstats while it all gets fixed.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From nico at fluxnic.net  Tue Jun  8 19:02:29 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 08 Jun 2010 19:02:29 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C0EAD3B.8010404@bluewatersys.com>
References: <4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<4C0E3CAF.4050409@weinigel.se>
	<20100608131007.GE25370@n2100.arm.linux.org.uk>
	<4C0EAD3B.8010404@bluewatersys.com>
Message-ID: <alpine.LFD.2.00.1006081655350.30664@xanadu.home>

On Wed, 9 Jun 2010, Ryan Mallon wrote:

> Striping the spitz defconfig back for example:
> 
>   ryan at okiwi:configs$ wc -l spitz_defconfig
>   1820 spitz_defconfig
> 
>   ryan at okiwi:configs$ grep -v "is not set" spitz_defconfig | grep -v
> "^#" | wc -l
>   641
> 
> So removing all the comments and non-set options makes the defconfig
> about 1/3 the size. If the defconfigs were generated by hand, or a
> proper set of tools, then they could be much less verbose and diffs for
> things like adding or removing a single config option would actually be
> readable.
> 
> If we want to have individual board configurations in the kernel, then
> the information has to live somewhere. Whether it is defconfig, KConfig,
> Documentation, whatever, the information will still take up a similar
> amount of space, and the process of moving the information will generate
> a load of diffstat noise.

Did you see the SheevaPlug example I posted earlier?  It contains only 
10 lines of added information.  Certainly not similar amount of space to 
the existing defconfig files.


Nicolas


From ryan at bluewatersys.com  Tue Jun  8 19:21:24 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Wed, 09 Jun 2010 11:21:24 +1200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <alpine.LFD.2.00.1006081655350.30664@xanadu.home>
References: <4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<4C0E3CAF.4050409@weinigel.se>
	<20100608131007.GE25370@n2100.arm.linux.org.uk>
	<4C0EAD3B.8010404@bluewatersys.com>
	<alpine.LFD.2.00.1006081655350.30664@xanadu.home>
Message-ID: <4C0ED074.7050700@bluewatersys.com>

Nicolas Pitre wrote:
> On Wed, 9 Jun 2010, Ryan Mallon wrote:
> 
>> Striping the spitz defconfig back for example:
>>
>>   ryan at okiwi:configs$ wc -l spitz_defconfig
>>   1820 spitz_defconfig
>>
>>   ryan at okiwi:configs$ grep -v "is not set" spitz_defconfig | grep -v
>> "^#" | wc -l
>>   641
>>
>> So removing all the comments and non-set options makes the defconfig
>> about 1/3 the size. If the defconfigs were generated by hand, or a
>> proper set of tools, then they could be much less verbose and diffs for
>> things like adding or removing a single config option would actually be
>> readable.
>>
>> If we want to have individual board configurations in the kernel, then
>> the information has to live somewhere. Whether it is defconfig, KConfig,
>> Documentation, whatever, the information will still take up a similar
>> amount of space, and the process of moving the information will generate
>> a load of diffstat noise.
> 
> Did you see the SheevaPlug example I posted earlier?  It contains only 
> 10 lines of added information.  Certainly not similar amount of space to 
> the existing defconfig files.
> 

Yes. I thought the problem was that Kconfig doesn't work correctly for
this though. Does having 'select MTD_PARTITIONS' automatically cause
CONFIG_MTD to be set? If not, then you basically need to have the full
config option list, which is basically what defconfig is.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From broonie at opensource.wolfsonmicro.com  Tue Jun  8 19:21:34 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 9 Jun 2010 00:21:34 +0100
Subject: [PATCH 1/3] EP93xx: Add i2s core support
In-Reply-To: <4C0E9987.2010907@bluewatersys.com>
	(sfid-20100608_202716_363612_846D1CC6)
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<1275991272-30122-2-git-send-email-ryan@bluewatersys.com>
	<0D753D10438DA54287A00B027084269763708AFD76@AUSP01VMBX24.collaborationhost.net>
	<4C0E9987.2010907@bluewatersys.com>
	(sfid-20100608_202716_363612_846D1CC6)
Message-ID: <94CDC52C-12BD-447E-B0ED-5E3950FF89BA@opensource.wolfsonmicro.com>

On 8 Jun 2010, at 20:27, Ryan Mallon wrote:

> Okay, I have Liam and Hartley's acks on this one and Liam's on 3/3.
> Mark, do you want to apply the other two patches to your tree, or should
> they go via the arm tree?

I don't urgently mind for patch 1 since there's no build time dependency - in order to avoid possible merge issues in the ARM tree it's as well if it goes that way, though I can pick it up if it makes sense for you guys to keep stuff together and you don't anticipate colliding with any work in the arch/arm code for the CPU.

Patch 3 I'll apply to ASoC tomorrow, it depends on the I2S driver for the CPU which is most definitely ASoC (and it's going to get caught up in the multi-CODEC API changes soon as well so would get build issues in -next if merged via a different tree anyway).



From dwalker at codeaurora.org  Tue Jun  8 19:23:41 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Tue, 08 Jun 2010 16:23:41 -0700
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <alpine.LFD.2.00.1006081213190.30664@xanadu.home>
References: <4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006080839240.30664@xanadu.home>
	<20100608125053.GD25370@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006080857390.30664@xanadu.home>
	<20100608131319.GF25370@n2100.arm.linux.org.uk>
	<AANLkTinWCRIKyMUseSpkRfEC0Cba4JRGBiUwb_jD_MkZ@mail.gmail.com>
	<alpine.LFD.2.00.1006081213190.30664@xanadu.home>
Message-ID: <1276039421.14529.29.camel@c-dwalke-linux.qualcomm.com>

On Tue, 2010-06-08 at 12:55 -0400, Nicolas Pitre wrote:

> Hence with the above you immediately get a sense of what this particular 
> hardware target needs in a fairly human readable form without having to 
> dig and guess through all the Kconfig options.  And having that 
> information next to the very Kconfig entry concerned is also much easier 
> to maintain rather than having that located in a separate file.


I think this is what Linus wants .. I tested this to make a OK msm
config for trout, and it does that although I didn't boot test it. I
couldn't get the select statement to select inside a choice menu, so I
had to convert to a regular menu.

You use it like this,

KBUILD_KCONFIG=arch/arm/Kconfig.trout make ARCH=arm allnoconfig

For me, I don't like this method.

Daniel

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..ce18fb0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -206,9 +206,7 @@ config MMU
 # The "ARM system type" choice list is ordered alphabetically by option
 # text.  Please add new entries in the option alphabetic order.
 #
-choice
-	prompt "ARM system type"
-	default ARCH_VERSATILE
+menu "ARM system type"
 
 config ARCH_AAEC2000
 	bool "Agilent AAEC-2000 based"
@@ -794,7 +792,7 @@ config PLAT_SPEAR
 	help
 	  Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
 
-endchoice
+endmenu
 
 #
 # This is sorted alphabetically by mach-* pathname.  However, plat-*
diff --git a/arch/arm/configs/Kconfig.trout b/arch/arm/configs/Kconfig.trout
new file mode 100644
index 0000000..cf81793
--- /dev/null
+++ b/arch/arm/configs/Kconfig.trout
@@ -0,0 +1,12 @@
+
+config TROUT_BASE_CONFIG
+	bool
+	default y
+	select ARCH_MSM
+	select ARCH_MSM7X00A 
+	select MACH_TROUT
+	select MSM_DEBUG_UART3
+	select MMC
+	select MMC_MSM7X00A
+
+source "arch/arm/Kconfig"




From ryan at bluewatersys.com  Tue Jun  8 19:26:49 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Wed, 09 Jun 2010 11:26:49 +1200
Subject: [PATCH 1/3] EP93xx: Add i2s core support
In-Reply-To: <94CDC52C-12BD-447E-B0ED-5E3950FF89BA@opensource.wolfsonmicro.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<1275991272-30122-2-git-send-email-ryan@bluewatersys.com>
	<0D753D10438DA54287A00B027084269763708AFD76@AUSP01VMBX24.collaborationhost.net>
	<4C0E9987.2010907@bluewatersys.com>
	(sfid-20100608_202716_363612_846D1CC6)
	<94CDC52C-12BD-447E-B0ED-5E3950FF89BA@opensource.wolfsonmicro.com>
Message-ID: <4C0ED1B9.7020106@bluewatersys.com>

Mark Brown wrote:
> On 8 Jun 2010, at 20:27, Ryan Mallon wrote:
> 
>> Okay, I have Liam and Hartley's acks on this one and Liam's on 3/3.
>> Mark, do you want to apply the other two patches to your tree, or should
>> they go via the arm tree?
> 
> I don't urgently mind for patch 1 since there's no build time dependency - in order to avoid possible merge issues in the ARM tree it's as well if it goes that way, though I can pick it up if it makes sense for you guys to keep stuff together and you don't anticipate colliding with any work in the arch/arm code for the CPU.
> 
> Patch 3 I'll apply to ASoC tomorrow, it depends on the I2S driver for the CPU which is most definitely ASoC (and it's going to get caught up in the multi-CODEC API changes soon as well so would get build issues in -next if merged via a different tree anyway).
> 

Patch 3 at least has a dependency on patch 1 for some #defines and the
ep93xx_i2s functions calls.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From dwalker at codeaurora.org  Tue Jun  8 19:26:58 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Tue, 08 Jun 2010 16:26:58 -0700
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C0ED074.7050700@bluewatersys.com>
References: <4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<4C0E3CAF.4050409@weinigel.se>
	<20100608131007.GE25370@n2100.arm.linux.org.uk>
	<4C0EAD3B.8010404@bluewatersys.com>
	<alpine.LFD.2.00.1006081655350.30664@xanadu.home>
	<4C0ED074.7050700@bluewatersys.com>
Message-ID: <1276039618.14529.30.camel@c-dwalke-linux.qualcomm.com>

On Wed, 2010-06-09 at 11:21 +1200, Ryan Mallon wrote:
> Nicolas Pitre wrote:
> > On Wed, 9 Jun 2010, Ryan Mallon wrote:
> > 
> >> Striping the spitz defconfig back for example:
> >>
> >>   ryan at okiwi:configs$ wc -l spitz_defconfig
> >>   1820 spitz_defconfig
> >>
> >>   ryan at okiwi:configs$ grep -v "is not set" spitz_defconfig | grep -v
> >> "^#" | wc -l
> >>   641
> >>
> >> So removing all the comments and non-set options makes the defconfig
> >> about 1/3 the size. If the defconfigs were generated by hand, or a
> >> proper set of tools, then they could be much less verbose and diffs for
> >> things like adding or removing a single config option would actually be
> >> readable.
> >>
> >> If we want to have individual board configurations in the kernel, then
> >> the information has to live somewhere. Whether it is defconfig, KConfig,
> >> Documentation, whatever, the information will still take up a similar
> >> amount of space, and the process of moving the information will generate
> >> a load of diffstat noise.
> > 
> > Did you see the SheevaPlug example I posted earlier?  It contains only 
> > 10 lines of added information.  Certainly not similar amount of space to 
> > the existing defconfig files.
> > 
> 
> Yes. I thought the problem was that Kconfig doesn't work correctly for
> this though. Does having 'select MTD_PARTITIONS' automatically cause
> CONFIG_MTD to be set? If not, then you basically need to have the full
> config option list, which is basically what defconfig is.

Yeah, you need all the dependencies .. At least in my testing you do,
since select doesn't auto-select dependencies .. It's still smaller than
the normal defconfig tho.

Daniel



From hartleys at visionengravers.com  Tue Jun  8 19:26:31 2010
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Tue, 8 Jun 2010 18:26:31 -0500
Subject: [PATCH 1/3] EP93xx: Add i2s core support
In-Reply-To: <4C0E9987.2010907@bluewatersys.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<1275991272-30122-2-git-send-email-ryan@bluewatersys.com>
	<0D753D10438DA54287A00B027084269763708AFD76@AUSP01VMBX24.collaborationhost.net>
	<4C0E9987.2010907@bluewatersys.com>
Message-ID: <0D753D10438DA54287A00B02708426976370DCDC51@AUSP01VMBX24.collaborationhost.net>

On Tuesday, June 08, 2010 12:27 PM, Ryan Mallon wrote:
> H Hartley Sweeten wrote:
>> On Tuesday, June 08, 2010 3:01 AM, Ryan Mallon wrote:
>>> Add core support for EP93xx i2s audio
>>>
>>> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
>> 
>> Looks good.
>> 
>> Acked-by: H Hartley Sweeten <hsweeten at visionengravers.com>
>> 
>
> Okay, I have Liam and Hartley's acks on this one and Liam's on 3/3.
> Mark, do you want to apply the other two patches to your tree, or should
> they go via the arm tree?

Ryan,

It appears Mark doesn't see ant reason to apply patch 1 to his tree.  It's
probably better to send that one thru Russell's patch system in case any
other changes are made to the ep93xx core files.

Regards,
Hartley

From broonie at opensource.wolfsonmicro.com  Tue Jun  8 19:29:01 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 9 Jun 2010 00:29:01 +0100
Subject: [PATCH 1/3] EP93xx: Add i2s core support
In-Reply-To: <4C0ED1B9.7020106@bluewatersys.com>
	(sfid-20100609_002659_105352_75064CA0)
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<1275991272-30122-2-git-send-email-ryan@bluewatersys.com>
	<0D753D10438DA54287A00B027084269763708AFD76@AUSP01VMBX24.collaborationhost.net>
	<4C0E9987.2010907@bluewatersys.com>
	(sfid-20100608_202716_363612_846D1CC6)
	<94CDC52C-12BD-447E-B0ED-5E3950FF89BA@opensource.wolfsonmicro.com>
	<4C0ED1B9.7020106@bluewatersys.com>
	(sfid-20100609_002659_105352_75064CA0)
Message-ID: <079055B9-F238-400E-A94D-4B950A5C8C7B@opensource.wolfsonmicro.com>

On 9 Jun 2010, at 00:26, Ryan Mallon wrote:

> Patch 3 at least has a dependency on patch 1 for some #defines and the
> ep93xx_i2s functions calls.

Oh, in that case best if I take them both through ASoC unless someone anticipates issues there. I'll arrange things so they can also be merged into the ARM tree in case of issues.

From nico at fluxnic.net  Tue Jun  8 19:31:50 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 08 Jun 2010 19:31:50 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C0ED074.7050700@bluewatersys.com>
References: <4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<4C0E3CAF.4050409@weinigel.se>
	<20100608131007.GE25370@n2100.arm.linux.org.uk>
	<4C0EAD3B.8010404@bluewatersys.com>
	<alpine.LFD.2.00.1006081655350.30664@xanadu.home>
	<4C0ED074.7050700@bluewatersys.com>
Message-ID: <alpine.LFD.2.00.1006081930570.30664@xanadu.home>

On Wed, 9 Jun 2010, Ryan Mallon wrote:

> Nicolas Pitre wrote:
> > On Wed, 9 Jun 2010, Ryan Mallon wrote:
> > 
> >> Striping the spitz defconfig back for example:
> >>
> >>   ryan at okiwi:configs$ wc -l spitz_defconfig
> >>   1820 spitz_defconfig
> >>
> >>   ryan at okiwi:configs$ grep -v "is not set" spitz_defconfig | grep -v
> >> "^#" | wc -l
> >>   641
> >>
> >> So removing all the comments and non-set options makes the defconfig
> >> about 1/3 the size. If the defconfigs were generated by hand, or a
> >> proper set of tools, then they could be much less verbose and diffs for
> >> things like adding or removing a single config option would actually be
> >> readable.
> >>
> >> If we want to have individual board configurations in the kernel, then
> >> the information has to live somewhere. Whether it is defconfig, KConfig,
> >> Documentation, whatever, the information will still take up a similar
> >> amount of space, and the process of moving the information will generate
> >> a load of diffstat noise.
> > 
> > Did you see the SheevaPlug example I posted earlier?  It contains only 
> > 10 lines of added information.  Certainly not similar amount of space to 
> > the existing defconfig files.
> > 
> 
> Yes. I thought the problem was that Kconfig doesn't work correctly for
> this though. Does having 'select MTD_PARTITIONS' automatically cause
> CONFIG_MTD to be set? If not, then you basically need to have the full
> config option list, which is basically what defconfig is.

Please read my email again and ponder on the rule of thumb I proposed to 
decide what needs to be explicitly provided.


Nicolas


From ryan at bluewatersys.com  Tue Jun  8 19:32:13 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Wed, 09 Jun 2010 11:32:13 +1200
Subject: [PATCH 1/3] EP93xx: Add i2s core support
In-Reply-To: <079055B9-F238-400E-A94D-4B950A5C8C7B@opensource.wolfsonmicro.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<1275991272-30122-2-git-send-email-ryan@bluewatersys.com>
	<0D753D10438DA54287A00B027084269763708AFD76@AUSP01VMBX24.collaborationhost.net>
	<4C0E9987.2010907@bluewatersys.com>
	(sfid-20100608_202716_363612_846D1CC6)
	<94CDC52C-12BD-447E-B0ED-5E3950FF89BA@opensource.wolfsonmicro.com>
	<4C0ED1B9.7020106@bluewatersys.com>
	(sfid-20100609_002659_105352_75064CA0)
	<079055B9-F238-400E-A94D-4B950A5C8C7B@opensource.wolfsonmicro.com>
Message-ID: <4C0ED2FD.8090402@bluewatersys.com>

Mark Brown wrote:
> On 9 Jun 2010, at 00:26, Ryan Mallon wrote:
> 
>> Patch 3 at least has a dependency on patch 1 for some #defines and the
>> ep93xx_i2s functions calls.
> 
> Oh, in that case best if I take them both through ASoC unless someone anticipates issues there. I'll arrange things so they can also be merged into the ARM tree in case of issues.

Ok, thanks.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From ryan at bluewatersys.com  Tue Jun  8 19:52:39 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Wed, 09 Jun 2010 11:52:39 +1200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <alpine.LFD.2.00.1006081930570.30664@xanadu.home>
References: <4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<4C0E3CAF.4050409@weinigel.se>
	<20100608131007.GE25370@n2100.arm.linux.org.uk>
	<4C0EAD3B.8010404@bluewatersys.com>
	<alpine.LFD.2.00.1006081655350.30664@xanadu.home>
	<4C0ED074.7050700@bluewatersys.com>
	<alpine.LFD.2.00.1006081930570.30664@xanadu.home>
Message-ID: <4C0ED7C7.1060403@bluewatersys.com>

Nicolas Pitre wrote:
> On Wed, 9 Jun 2010, Ryan Mallon wrote:
> 
>> Nicolas Pitre wrote:
>>> On Wed, 9 Jun 2010, Ryan Mallon wrote:
>>>
>>>> Striping the spitz defconfig back for example:
>>>>
>>>>   ryan at okiwi:configs$ wc -l spitz_defconfig
>>>>   1820 spitz_defconfig
>>>>
>>>>   ryan at okiwi:configs$ grep -v "is not set" spitz_defconfig | grep -v
>>>> "^#" | wc -l
>>>>   641
>>>>
>>>> So removing all the comments and non-set options makes the defconfig
>>>> about 1/3 the size. If the defconfigs were generated by hand, or a
>>>> proper set of tools, then they could be much less verbose and diffs for
>>>> things like adding or removing a single config option would actually be
>>>> readable.
>>>>
>>>> If we want to have individual board configurations in the kernel, then
>>>> the information has to live somewhere. Whether it is defconfig, KConfig,
>>>> Documentation, whatever, the information will still take up a similar
>>>> amount of space, and the process of moving the information will generate
>>>> a load of diffstat noise.
>>> Did you see the SheevaPlug example I posted earlier?  It contains only 
>>> 10 lines of added information.  Certainly not similar amount of space to 
>>> the existing defconfig files.
>>>
>> Yes. I thought the problem was that Kconfig doesn't work correctly for
>> this though. Does having 'select MTD_PARTITIONS' automatically cause
>> CONFIG_MTD to be set? If not, then you basically need to have the full
>> config option list, which is basically what defconfig is.
> 
> Please read my email again and ponder on the rule of thumb I proposed to 
> decide what needs to be explicitly provided.

I agree that is probably a better solution than the defconfigs. However,
 your SheevaPlug example doesn't really show how big that config list is
going to get. Because Kconfig doesn't properly select dependencies, you
will have to list all of them. Granted, the list will be smaller than a
defconfig file, but the Kconfig files are going to become substantially
larger with this approach.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From nico at fluxnic.net  Tue Jun  8 20:14:17 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 08 Jun 2010 20:14:17 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C0ED7C7.1060403@bluewatersys.com>
References: <4C083BCF.2060500@bluewatersys.com>
	<201006040310.15019.marek.vasut@gmail.com>
	<4C0853E1.1080005@bluewatersys.com>
	<AANLkTinEq99_8UyVNnmzNEreDoyHKEnxpuJmaAo_kpPN@mail.gmail.com>
	<20100604061034.GI6499@atomide.com>
	<AANLkTikrK-RkDntgrpptBaG6TvnesNFncOw3DW4Jt-TY@mail.gmail.com>
	<AANLkTil1IetX6koHVRrgnWs3DqhPtZVqR2euEdg9lZUa@mail.gmail.com>
	<alpine.LFD.2.00.1006041418390.22319@xanadu.home>
	<20100608115832.GB25370@n2100.arm.linux.org.uk>
	<4C0E3CAF.4050409@weinigel.se>
	<20100608131007.GE25370@n2100.arm.linux.org.uk>
	<4C0EAD3B.8010404@bluewatersys.com>
	<alpine.LFD.2.00.1006081655350.30664@xanadu.home>
	<4C0ED074.7050700@bluewatersys.com>
	<alpine.LFD.2.00.1006081930570.30664@xanadu.home>
	<4C0ED7C7.1060403@bluewatersys.com>
Message-ID: <alpine.LFD.2.00.1006082008540.30664@xanadu.home>

On Wed, 9 Jun 2010, Ryan Mallon wrote:

> Nicolas Pitre wrote:
> > On Wed, 9 Jun 2010, Ryan Mallon wrote:
> > 
> >> Nicolas Pitre wrote:
> >>> On Wed, 9 Jun 2010, Ryan Mallon wrote:
> >>>
> >>>> Striping the spitz defconfig back for example:
> >>>>
> >>>>   ryan at okiwi:configs$ wc -l spitz_defconfig
> >>>>   1820 spitz_defconfig
> >>>>
> >>>>   ryan at okiwi:configs$ grep -v "is not set" spitz_defconfig | grep -v
> >>>> "^#" | wc -l
> >>>>   641
> >>>>
> >>>> So removing all the comments and non-set options makes the defconfig
> >>>> about 1/3 the size. If the defconfigs were generated by hand, or a
> >>>> proper set of tools, then they could be much less verbose and diffs for
> >>>> things like adding or removing a single config option would actually be
> >>>> readable.
> >>>>
> >>>> If we want to have individual board configurations in the kernel, then
> >>>> the information has to live somewhere. Whether it is defconfig, KConfig,
> >>>> Documentation, whatever, the information will still take up a similar
> >>>> amount of space, and the process of moving the information will generate
> >>>> a load of diffstat noise.
> >>> Did you see the SheevaPlug example I posted earlier?  It contains only 
> >>> 10 lines of added information.  Certainly not similar amount of space to 
> >>> the existing defconfig files.
> >>>
> >> Yes. I thought the problem was that Kconfig doesn't work correctly for
> >> this though. Does having 'select MTD_PARTITIONS' automatically cause
> >> CONFIG_MTD to be set? If not, then you basically need to have the full
> >> config option list, which is basically what defconfig is.
> > 
> > Please read my email again and ponder on the rule of thumb I proposed to 
> > decide what needs to be explicitly provided.
> 
> I agree that is probably a better solution than the defconfigs. However,
>  your SheevaPlug example doesn't really show how big that config list is
> going to get. Because Kconfig doesn't properly select dependencies, you
> will have to list all of them.

Let's say it doubles.  So 20 lines instead of 10, which is still 
readable and much much smaller than defconfigs.

But the real solution in this case would be to have another 
Kconfig keyword to automatically select the needed dependencies.

> Granted, the list will be smaller than a
> defconfig file, but the Kconfig files are going to become substantially
> larger with this approach.

Sure.  But there is no problem with that if the growth is made of 
valuable information, which in my example I think it is.


Nicolas


From rene.sapiens at ti.com  Tue Jun  8 20:16:02 2010
From: rene.sapiens at ti.com (Sapiens, Rene)
Date: Tue, 8 Jun 2010 19:16:02 -0500
Subject: [PATCH 09/10] omap: mailbox: convert block api to kfifo
In-Reply-To: <1275546858-29507-10-git-send-email-Hiroshi.DOYU@nokia.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
	<1275546858-29507-10-git-send-email-Hiroshi.DOYU@nokia.com>
Message-ID: <D2943F03B81C9C458E44DFB213905E02B6325C6A@dlee04.ent.ti.com>

Hi Ohad,

In mbox_rx_work() you are removing the lines that enable back the  mbox irq for the RX case, but inside  __mbox_rx_interrupt() this interrupt  is disabled in the case that the kfifo for Rx mailbox gets full. So I think that we need to enable it back as soon as there is space in this kfifo. 

Regards,
Rene


> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Hiroshi DOYU
> Sent: Thursday, June 03, 2010 1:34 AM
> To: linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Cc: Ohad Ben-Cohen; Kanigeri, Hari; Hiroshi DOYU
> Subject: [PATCH 09/10] omap: mailbox: convert block api to kfifo
> 
> From: Ohad Ben-Cohen <ohad at wizery.com>
> 
> The underlying buffering implementation of mailbox
> is converted from block API to kfifo due to the simplicity
> and speed of kfifo.
> 
> The default size of the kfifo buffer is set to 256 bytes.
> This value is configurable at compile time (via
> CONFIG_OMAP_MBOX_KFIFO_SIZE), and can be changed at
> runtime (via the mbox_kfifo_size module parameter).
> 
> Signed-off-by: Ohad Ben-Cohen <ohad at wizery.com>
> Signed-off-by: Hari Kanigeri <h-kanigeri2 at ti.com>
> Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
> ---
>  arch/arm/plat-omap/Kconfig                |    9 ++
>  arch/arm/plat-omap/include/plat/mailbox.h |    4 +-
>  arch/arm/plat-omap/mailbox.c              |  119 +++++++++++++-----------
> -----
>  3 files changed, 64 insertions(+), 68 deletions(-)
> 
> diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
> index 78b49a6..111d39a 100644
> --- a/arch/arm/plat-omap/Kconfig
> +++ b/arch/arm/plat-omap/Kconfig
> @@ -106,6 +106,15 @@ config OMAP_MBOX_FWK
>  	  Say Y here if you want to use OMAP Mailbox framework support for
>  	  DSP, IVA1.0 and IVA2 in OMAP1/2/3.
> 
> +config OMAP_MBOX_KFIFO_SIZE
> +	int "Mailbox kfifo default buffer size (bytes)"
> +	depends on OMAP_MBOX_FWK
> +	default 256
> +	help
> +	  Specify the default size of mailbox's kfifo buffers (bytes).
> +	  This can also be changed at runtime (via the mbox_kfifo_size
> +	  module parameter).
> +
>  config OMAP_IOMMU
>  	tristate
> 
> diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-
> omap/include/plat/mailbox.h
> index 729166b..0c3c4a5 100644
> --- a/arch/arm/plat-omap/include/plat/mailbox.h
> +++ b/arch/arm/plat-omap/include/plat/mailbox.h
> @@ -5,8 +5,8 @@
> 
>  #include <linux/wait.h>
>  #include <linux/workqueue.h>
> -#include <linux/blkdev.h>
>  #include <linux/interrupt.h>
> +#include <linux/kfifo.h>
> 
>  typedef u32 mbox_msg_t;
>  struct omap_mbox;
> @@ -42,7 +42,7 @@ struct omap_mbox_ops {
> 
>  struct omap_mbox_queue {
>  	spinlock_t		lock;
> -	struct request_queue	*queue;
> +	struct kfifo		fifo;
>  	struct work_struct	work;
>  	struct tasklet_struct	tasklet;
>  	int	(*callback)(void *);
> diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
> index 81076b5..ec0e159 100644
> --- a/arch/arm/plat-omap/mailbox.c
> +++ b/arch/arm/plat-omap/mailbox.c
> @@ -21,11 +21,14 @@
>   *
>   */
> 
> +#include <linux/kernel.h>
>  #include <linux/module.h>
>  #include <linux/interrupt.h>
>  #include <linux/device.h>
>  #include <linux/delay.h>
>  #include <linux/slab.h>
> +#include <linux/kfifo.h>
> +#include <linux/err.h>
> 
>  #include <plat/mailbox.h>
> 
> @@ -37,6 +40,10 @@ static bool rq_full;
>  static int mbox_configured;
>  static DEFINE_MUTEX(mbox_configured_lock);
> 
> +static unsigned int mbox_kfifo_size = CONFIG_OMAP_MBOX_KFIFO_SIZE;
> +module_param(mbox_kfifo_size, uint, S_IRUGO);
> +MODULE_PARM_DESC(mbox_kfifo_size, "Size of omap's mailbox kfifo
> (bytes)");
> +
>  /* Mailbox FIFO handle functions */
>  static inline mbox_msg_t mbox_fifo_read(struct omap_mbox *mbox)
>  {
> @@ -69,7 +76,7 @@ static inline int is_mbox_irq(struct omap_mbox *mbox,
> omap_mbox_irq_t irq)
>  /*
>   * message sender
>   */
> -static int __mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
> +static int __mbox_poll_for_space(struct omap_mbox *mbox)
>  {
>  	int ret = 0, i = 1000;
> 
> @@ -80,49 +87,50 @@ static int __mbox_msg_send(struct omap_mbox *mbox,
> mbox_msg_t msg)
>  			return -1;
>  		udelay(1);
>  	}
> -	mbox_fifo_write(mbox, msg);
>  	return ret;
>  }
> 
> -
>  int omap_mbox_msg_send(struct omap_mbox *mbox, mbox_msg_t msg)
>  {
> +	struct omap_mbox_queue *mq = mbox->txq;
> +	int ret = 0, len;
> 
> -	struct request *rq;
> -	struct request_queue *q = mbox->txq->queue;
> +	spin_lock(&mq->lock);
> 
> -	rq = blk_get_request(q, WRITE, GFP_ATOMIC);
> -	if (unlikely(!rq))
> -		return -ENOMEM;
> +	if (kfifo_avail(&mq->fifo) < sizeof(msg)) {
> +		ret = -ENOMEM;
> +		goto out;
> +	}
> +
> +	len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
> +	WARN_ON(len != sizeof(msg));
> 
> -	blk_insert_request(q, rq, 0, (void *) msg);
>  	tasklet_schedule(&mbox->txq->tasklet);
> 
> -	return 0;
> +out:
> +	spin_unlock(&mq->lock);
> +	return ret;
>  }
>  EXPORT_SYMBOL(omap_mbox_msg_send);
> 
>  static void mbox_tx_tasklet(unsigned long tx_data)
>  {
> -	int ret;
> -	struct request *rq;
>  	struct omap_mbox *mbox = (struct omap_mbox *)tx_data;
> -	struct request_queue *q = mbox->txq->queue;
> -
> -	while (1) {
> -
> -		rq = blk_fetch_request(q);
> -
> -		if (!rq)
> -			break;
> +	struct omap_mbox_queue *mq = mbox->txq;
> +	mbox_msg_t msg;
> +	int ret;
> 
> -		ret = __mbox_msg_send(mbox, (mbox_msg_t)rq->special);
> -		if (ret) {
> +	while (kfifo_len(&mq->fifo)) {
> +		if (__mbox_poll_for_space(mbox)) {
>  			omap_mbox_enable_irq(mbox, IRQ_TX);
> -			blk_requeue_request(q, rq);
> -			return;
> +			break;
>  		}
> -		blk_end_request_all(rq, 0);
> +
> +		ret = kfifo_out(&mq->fifo, (unsigned char *)&msg,
> +								sizeof(msg));
> +		WARN_ON(ret != sizeof(msg));
> +
> +		mbox_fifo_write(mbox, msg);
>  	}
>  }
> 
> @@ -133,41 +141,21 @@ static void mbox_rx_work(struct work_struct *work)
>  {
>  	struct omap_mbox_queue *mq =
>  			container_of(work, struct omap_mbox_queue, work);
> -	struct omap_mbox *mbox = mq->queue->queuedata;
> -	struct request_queue *q = mbox->rxq->queue;
> -	struct request *rq;
>  	mbox_msg_t msg;
> -	unsigned long flags;
> -
> -	while (1) {
> -		spin_lock_irqsave(q->queue_lock, flags);
> -		rq = blk_fetch_request(q);
> -		if (rq_full) {
> -			omap_mbox_enable_irq(mbox, IRQ_RX);
> -			rq_full = false;
> -		}
> -		spin_unlock_irqrestore(q->queue_lock, flags);
> -		if (!rq)
> -			break;
> +	int len;
> +
> +	while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
> +		len = kfifo_out(&mq->fifo, (unsigned char *)&msg,
> sizeof(msg));
> +		WARN_ON(len != sizeof(msg));
> 
> -		msg = (mbox_msg_t)rq->special;
> -		blk_end_request_all(rq, 0);
> -		if (mbox->rxq->callback)
> -			mbox->rxq->callback((void *)msg);
> +		if (mq->callback)
> +			mq->callback((void *)msg);
>  	}
>  }
> 
>  /*
>   * Mailbox interrupt handler
>   */
> -static void mbox_txq_fn(struct request_queue *q)
> -{
> -}
> -
> -static void mbox_rxq_fn(struct request_queue *q)
> -{
> -}
> -
>  static void __mbox_tx_interrupt(struct omap_mbox *mbox)
>  {
>  	omap_mbox_disable_irq(mbox, IRQ_TX);
> @@ -177,13 +165,12 @@ static void __mbox_tx_interrupt(struct omap_mbox
> *mbox)
> 
>  static void __mbox_rx_interrupt(struct omap_mbox *mbox)
>  {
> -	struct request *rq;
> +	struct omap_mbox_queue *mq = mbox->rxq;
>  	mbox_msg_t msg;
> -	struct request_queue *q = mbox->rxq->queue;
> +	int len;
> 
>  	while (!mbox_fifo_empty(mbox)) {
> -		rq = blk_get_request(q, WRITE, GFP_ATOMIC);
> -		if (unlikely(!rq)) {
> +		if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
>  			omap_mbox_disable_irq(mbox, IRQ_RX);
>  			rq_full = true;
>  			goto nomem;
> @@ -191,8 +178,9 @@ static void __mbox_rx_interrupt(struct omap_mbox
> *mbox)
> 
>  		msg = mbox_fifo_read(mbox);
> 
> +		len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
> +		WARN_ON(len != sizeof(msg));
> 
> -		blk_insert_request(q, rq, 0, (void *)msg);
>  		if (mbox->ops->type == OMAP_MBOX_TYPE1)
>  			break;
>  	}
> @@ -217,11 +205,9 @@ static irqreturn_t mbox_interrupt(int irq, void *p)
>  }
> 
>  static struct omap_mbox_queue *mbox_queue_alloc(struct omap_mbox *mbox,
> -					request_fn_proc *proc,
>  					void (*work) (struct work_struct *),
>  					void (*tasklet)(unsigned long))
>  {
> -	struct request_queue *q;
>  	struct omap_mbox_queue *mq;
> 
>  	mq = kzalloc(sizeof(struct omap_mbox_queue), GFP_KERNEL);
> @@ -230,11 +216,8 @@ static struct omap_mbox_queue
> *mbox_queue_alloc(struct omap_mbox *mbox,
> 
>  	spin_lock_init(&mq->lock);
> 
> -	q = blk_init_queue(proc, &mq->lock);
> -	if (!q)
> +	if (kfifo_alloc(&mq->fifo, mbox_kfifo_size, GFP_KERNEL))
>  		goto error;
> -	q->queuedata = mbox;
> -	mq->queue = q;
> 
>  	if (work)
>  		INIT_WORK(&mq->work, work);
> @@ -249,7 +232,7 @@ error:
> 
>  static void mbox_queue_free(struct omap_mbox_queue *q)
>  {
> -	blk_cleanup_queue(q->queue);
> +	kfifo_free(&q->fifo);
>  	kfree(q);
>  }
> 
> @@ -279,14 +262,14 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
>  		goto fail_request_irq;
>  	}
> 
> -	mq = mbox_queue_alloc(mbox, mbox_txq_fn, NULL, mbox_tx_tasklet);
> +	mq = mbox_queue_alloc(mbox, NULL, mbox_tx_tasklet);
>  	if (!mq) {
>  		ret = -ENOMEM;
>  		goto fail_alloc_txq;
>  	}
>  	mbox->txq = mq;
> 
> -	mq = mbox_queue_alloc(mbox, mbox_rxq_fn, mbox_rx_work, NULL);
> +	mq = mbox_queue_alloc(mbox, mbox_rx_work, NULL);
>  	if (!mq) {
>  		ret = -ENOMEM;
>  		goto fail_alloc_rxq;
> @@ -418,6 +401,10 @@ static int __init omap_mbox_init(void)
>  	if (!mboxd)
>  		return -ENOMEM;
> 
> +	/* kfifo size sanity check: alignment and minimal size */
> +	mbox_kfifo_size = ALIGN(mbox_kfifo_size, sizeof(mbox_msg_t));
> +	mbox_kfifo_size = max_t(unsigned int, mbox_kfifo_size,
> sizeof(mbox_msg_t));
> +
>  	return 0;
>  }
>  module_init(omap_mbox_init);
> --
> 1.7.1.rc1
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From kgene.kim at samsung.com  Tue Jun  8 22:25:49 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 09 Jun 2010 11:25:49 +0900
Subject: Current menuconfig (ARM system type) is broken
In-Reply-To: <w3pfx0yuv3x.wl%kuninori.morimoto.gx@renesas.com>
References: <w3pfx0yuv3x.wl%kuninori.morimoto.gx@renesas.com>
Message-ID: <00cc01cb077b$16333e60$4299bb20$%kim@samsung.com>

Kuninori Morimoto wrote:
> 
> Dear all
> 
Hi,

> Is current menuconfig broken ?
> It mean
> 
> [Sytem Type] - [ARM system type]
> 
> In my environment, string output is broken.
> 
> I think
> ${LINUX}/arch/arm/Kconfig
> 
> config ARCH_S3C2410
> 	bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440,
> S3C2442, S3C2443, S3C2450"
> 
> this line is very long.
> If I modify it to more short, it works correct.
> 

It was already reported.

Please refer to below thread.

http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/017001.html

Ben Dooks' comments:
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/017030.html


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From ohad at wizery.com  Tue Jun  8 22:35:30 2010
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Tue, 8 Jun 2010 21:35:30 -0500
Subject: [PATCH 09/10] omap: mailbox: convert block api to kfifo
In-Reply-To: <D2943F03B81C9C458E44DFB213905E02B6325C6A@dlee04.ent.ti.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com> 
	<1275546858-29507-10-git-send-email-Hiroshi.DOYU@nokia.com> 
	<D2943F03B81C9C458E44DFB213905E02B6325C6A@dlee04.ent.ti.com>
Message-ID: <AANLkTik4lW3_xP_e4BStJEYpHlVoNjemEz8zWfIE7gRU@mail.gmail.com>

Hi Rene,

On Tue, Jun 8, 2010 at 7:16 PM, Sapiens, Rene <rene.sapiens at ti.com> wrote:
> In mbox_rx_work() you are removing the lines that enable back the ?mbox irq for the RX case, but inside ?__mbox_rx_interrupt() this interrupt ?is disabled in the case that the kfifo for Rx mailbox gets full. So I think that we need to enable it back as soon as there is space in this kfifo.



Actually these irq on/off lines are not part of my patch; they are
introduced by patch 05/10 on top of which my patches were rebased.

Nevertheless I agree with you - the kfifo migration patch should not
affect that irq on/off behavior. It's probably just a rebase gotcha.

But now that you point me to this irq on/off thing, it looks a bit
broken in terms of multiple concurrent mbox support since it relies on
a global rq_full state. I guess it'd be better to hold that rq_full
state in the relevant mbox queue state itself.

Fernando what do you think ?

Thanks,
Ohad.


From jeremy.kerr at canonical.com  Wed Jun  9 00:26:13 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Wed, 9 Jun 2010 12:26:13 +0800
Subject: Boot interface for device trees on ARM
In-Reply-To: <alpine.LFD.2.00.1006042212400.30664@xanadu.home>
References: <201005181054.32325.jeremy.kerr@canonical.com>
	<201006050933.06714.jeremy.kerr@canonical.com>
	<alpine.LFD.2.00.1006042212400.30664@xanadu.home>
Message-ID: <201006091226.15438.jeremy.kerr@canonical.com>

Hi Nicolas,

> > If we're planning to keep the machine IDs around (even if they are now
> > per- SoC), I'd like to know what would be left using them. The only
> > thing that I can see that we currently use is io_pg_offset for the
> > DEBUG_LL builds, and that isn't a convincing case to keep them.
> 
> Why not?

Because it's something we can justifiably replace with a single compile-time 
constant, since it's only for low-level debug. I don't see that as a reason 
for keeping these machine numbers around if that's all they're used for.

However...

> Kernel infrastructure backward compatibility means that you need to keep
> struct machine_desc instances around.  Granted, for the DT case, many of
> the members could be NULL or initialized with dummy stubs.  But that is
> very cheap to keep around, and that allows the same kernel binary to be
> able to use both the DT boot and the legacy boot.

... this is a good point; if it helps with the transition, then this is 
probably a decent reason to keep it in the interface.

I'd like to keep my "only use the device tree" value (MACH_TYPE_DT = 
0xffffffff) though, so we don't needlessly allocate machine numbers where they 
aren't actually used.

Cheers,


Jeremy


From fernando.lugo at ti.com  Wed Jun  9 01:38:55 2010
From: fernando.lugo at ti.com (Guzman Lugo, Fernando)
Date: Wed, 9 Jun 2010 00:38:55 -0500
Subject: [PATCH 09/10] omap: mailbox: convert block api to kfifo
In-Reply-To: <AANLkTik4lW3_xP_e4BStJEYpHlVoNjemEz8zWfIE7gRU@mail.gmail.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com>
	<1275546858-29507-10-git-send-email-Hiroshi.DOYU@nokia.com>
	<D2943F03B81C9C458E44DFB213905E02B6325C6A@dlee04.ent.ti.com>,
	<AANLkTik4lW3_xP_e4BStJEYpHlVoNjemEz8zWfIE7gRU@mail.gmail.com>
Message-ID: <496565EC904933469F292DDA3F1663E602CA4D88F3@dlee06.ent.ti.com>


Hi Ohad,

________________________________________
>From: Ohad Ben-Cohen [ohad at wizery.com]
>Sent: Tuesday, June 08, 2010 9:35 PM
>To: Sapiens, Rene; Guzman Lugo, Fernando
>Cc: Hiroshi DOYU; linux-omap at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Kanigeri, Hari
>Subject: Re: [PATCH 09/10] omap: mailbox: convert block api to kfifo
>
>Hi Rene,
>
>On Tue, Jun 8, 2010 at 7:16 PM, Sapiens, Rene <rene.sapiens at ti.com> wrote:
>> In mbox_rx_work() you are removing the lines that enable back the  mbox irq for the RX case, but inside  __mbox_rx_interrupt() this interrupt  is disabled in the case that the kfifo for Rx >mailbox gets full. So I think that we need to enable it back as soon as there is space in this kfifo.
>
>
>
>Actually these irq on/off lines are not part of my patch; they are
>introduced by patch 05/10 on top of which my patches were rebased.
>
>Nevertheless I agree with you - the kfifo migration patch should not
>affect that irq on/off behavior. It's probably just a rebase gotcha.
>
>But now that you point me to this irq on/off thing, it looks a bit
>broken in terms of multiple concurrent mbox support since it relies on
>a global rq_full state. I guess it'd be better to hold that rq_full
>state in the relevant mbox queue state itself.
>
>Fernando what do you think ?

Yes, you are right Ohad. Only should be disable the "new message" interrupt of the mailbox which kfifo is full.

regards,
Fernando.

>
>Thanks,
>Ohad.


From post at hendrik-sattler.de  Wed Jun  9 02:07:20 2010
From: post at hendrik-sattler.de (Hendrik Sattler)
Date: Wed, 9 Jun 2010 08:07:20 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <4C0ED074.7050700@bluewatersys.com>
References: <4C083BCF.2060500@bluewatersys.com>
	<alpine.LFD.2.00.1006081655350.30664@xanadu.home>
	<4C0ED074.7050700@bluewatersys.com>
Message-ID: <201006090807.20810.post@hendrik-sattler.de>

Am Mittwoch 09 Juni 2010, 01:21:24 schrieb Ryan Mallon:
> Yes. I thought the problem was that Kconfig doesn't work correctly for
> this though. Does having 'select MTD_PARTITIONS' automatically cause
> CONFIG_MTD to be set? If not, then you basically need to have the full
> config option list, which is basically what defconfig is.

Anybody thought about improving Kconfig to make this possible?
Specifying CONFIG_MTD and CONFIG_MTD_PARTITIONS again and again will just 
repeat information (that CONFIG_MTD_PARTITIONS depends on CONFIG_MTD).
The recursive 'select' could have a different name.

HS


From buytenh at wantstofly.org  Wed Jun  9 03:25:46 2010
From: buytenh at wantstofly.org (Lennert Buytenhek)
Date: Wed, 9 Jun 2010 09:25:46 +0200
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
In-Reply-To: <4c0e9ee6.8704df0a.2e71.ffffdf65@mx.google.com>
References: <4c0e9ee6.8704df0a.2e71.ffffdf65@mx.google.com>
Message-ID: <20100609072546.GB1743@mail.wantstofly.org>

On Tue, Jun 08, 2010 at 10:47:47PM +0300, Dmytro Milinevskyy wrote:

> Differences from the previous attempt:
>  - Applied suggestion from Lennert Buytenhek to change PHY addresses in instances of mv643xx_eth_platform_data in case of ultimate version.

The patch looks exactly like the old patch, though?


From milinevskyy at gmail.com  Wed Jun  9 03:37:05 2010
From: milinevskyy at gmail.com (Dmytro Milinevskyy)
Date: Wed, 9 Jun 2010 10:37:05 +0300
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
In-Reply-To: <20100609072546.GB1743@mail.wantstofly.org>
References: <4c0e9ee6.8704df0a.2e71.ffffdf65@mx.google.com> 
	<20100609072546.GB1743@mail.wantstofly.org>
Message-ID: <AANLkTilfrP0e3RaBV_GnpwG8NBsS4eXWnWOVaQxMrMfo@mail.gmail.com>

Oh, I've sent the old version.

My apologies. Will resend the updates version as soon as I get access
to the box.

-- Dima

On Wed, Jun 9, 2010 at 10:25 AM, Lennert Buytenhek
<buytenh at wantstofly.org> wrote:
> On Tue, Jun 08, 2010 at 10:47:47PM +0300, Dmytro Milinevskyy wrote:
>
>> Differences from the previous attempt:
>> ?- Applied suggestion from Lennert Buytenhek to change PHY addresses in instances of mv643xx_eth_platform_data in case of ultimate version.
>
> The patch looks exactly like the old patch, though?
>


From saeed at marvell.com  Wed Jun  9 04:21:47 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Wed, 9 Jun 2010 11:21:47 +0300
Subject: [PATCH 1/2] mv643xx_eth: disable csum offloading if the hw
	limited by max size
In-Reply-To: <20100608170846.GR1743@mail.wantstofly.org>
References: <1275827336-31111-1-git-send-email-saeed@marvell.com>
	<20100608170846.GR1743@mail.wantstofly.org>
Message-ID: <FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>

 

>-----Original Message-----
>From: Lennert Buytenhek [mailto:buytenh at wantstofly.org] 
>Sent: Tuesday, June 08, 2010 8:09 PM
>To: Saeed Bishara
>Cc: linux-net at vger.kernel.org; linux-arm-kernel at lists.infradead.org
>Subject: Re: [PATCH 1/2] mv643xx_eth: disable csum offloading 
>if the hw limited by max size
>
>On Sun, Jun 06, 2010 at 03:28:55PM +0300, Saeed Bishara wrote:
>
>> diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
>> index e345ec8..79243dd 100644
>> --- a/drivers/net/mv643xx_eth.c
>> +++ b/drivers/net/mv643xx_eth.c
>> @@ -289,6 +289,7 @@ struct mv643xx_eth_shared_private {
>>  	unsigned int t_clk;
>>  	int extended_rx_coal_limit;
>>  	int tx_bw_control;
>> +	int tx_csum_limit;
>>  };
>>  
>>  #define TX_BW_CONTROL_ABSENT		0
>> @@ -2468,6 +2469,14 @@ static int 
>mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
>>  	mv643xx_eth_recalc_skb_size(mp);
>>  	tx_set_rate(mp, 1000000000, 16777216);
>>  
>> +	if (mp->shared->tx_csum_limit && dev->mtu > 
>mp->shared->tx_csum_limit) {
>> +		dev->features &= ~NETIF_F_IP_CSUM;
>> +		dev->vlan_features &= ~NETIF_F_IP_CSUM;
>> +	} else {
>> +		dev->features |= NETIF_F_IP_CSUM;
>> +		dev->vlan_features |= NETIF_F_IP_CSUM;
>> +	}
>
>I wonder if it would be better to still advertise NETIF_F_IP_CSUM in
>this case, but just call skb_checksum_help() if skb->len is > dev->mtu
>in txq_submit_skb(), like we do for the case where the ethernet header
>is of an unsupported length -- that way, we'd still have hardware
>checksum offload for TX packets that _do_ fit inside the hardware TX
>fifo, e.g. when communicating with hosts on another subnet where the
>default MTU is used.
Goog idea, I'll add a check to skb->len > mp->shared->tx_csum_limit.
>
>
>> diff --git a/include/linux/mv643xx_eth.h 
>b/include/linux/mv643xx_eth.h
>> index cbbbe9b..7402718 100644
>> --- a/include/linux/mv643xx_eth.h
>> +++ b/include/linux/mv643xx_eth.h
>> @@ -19,6 +19,10 @@ struct mv643xx_eth_shared_platform_data {
>>  	struct mbus_dram_target_info	*dram;
>>  	struct platform_device	*shared_smi;
>>  	unsigned int		t_clk;
>> +	/*
>> +	 * Max packet size for Tx IP/Layer 4 checksum (0 -> no limit)
>
>There's always a limit. :-)  You might as well just fill in the right
>values for orion5x/kw/dd/loki while you're at it.
Right, kirkwood and dove are limited to 1600, the others to 9*1024. Don't know about loki.
>
>
>thanks,
>Lennert
>

From m.szyprowski at samsung.com  Wed Jun  9 04:40:33 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 09 Jun 2010 10:40:33 +0200
Subject: [PATCH] arm: s5pv210: add more banks to gpiolib
Message-ID: <1276072833-4862-1-git-send-email-m.szyprowski@samsung.com>

This patch adds support for MP04 and MP05 gpio banks. Pins from these
banks will be used by Samsung Aquila board.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>

---
 arch/arm/mach-s5pv210/gpiolib.c           |   17 +++++++++++++++++
 arch/arm/mach-s5pv210/include/mach/gpio.h |   10 ++++++++--
 2 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
index f4ac81f..6f74a98 100644
--- a/arch/arm/mach-s5pv210/gpiolib.c
+++ b/arch/arm/mach-s5pv210/gpiolib.c
@@ -208,6 +208,22 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.label	= "MP03",
 		},
 	}, {
+		.base	= (S5P_VA_GPIO + 0x340),
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PV210_MP04(0),
+			.ngpio	= S5PV210_GPIO_MP04_NR,
+			.label	= "MP04",
+		},
+	}, {
+		.base	= (S5P_VA_GPIO + 0x360),
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PV210_MP05(0),
+			.ngpio	= S5PV210_GPIO_MP05_NR,
+			.label	= "MP05",
+		},
+	}, {
 		.base	= (S5P_VA_GPIO + 0xC00),
 		.config	= &gpio_cfg_noint,
 		.chip	= {
@@ -244,6 +260,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.to_irq = s5p_gpiolib_eint_to_irq,
 		},
 	},
+
 };
 
 static __init int s5pv210_gpiolib_init(void)
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h
index d6461ba..33a9867 100644
--- a/arch/arm/mach-s5pv210/include/mach/gpio.h
+++ b/arch/arm/mach-s5pv210/include/mach/gpio.h
@@ -52,6 +52,8 @@
 #define S5PV210_GPIO_MP01_NR	(8)
 #define S5PV210_GPIO_MP02_NR	(4)
 #define S5PV210_GPIO_MP03_NR	(8)
+#define S5PV210_GPIO_MP04_NR	(8)
+#define S5PV210_GPIO_MP05_NR	(8)
 
 /* GPIO bank numbers */
 
@@ -94,6 +96,8 @@ enum s5p_gpio_number {
 	S5PV210_GPIO_MP01_START	= S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
 	S5PV210_GPIO_MP02_START	= S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
 	S5PV210_GPIO_MP03_START	= S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
+	S5PV210_GPIO_MP04_START	= S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03),
+	S5PV210_GPIO_MP05_START	= S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04),
 };
 
 /* S5PV210 GPIO number definitions */
@@ -127,13 +131,15 @@ enum s5p_gpio_number {
 #define S5PV210_MP01(_nr)	(S5PV210_GPIO_MP01_START + (_nr))
 #define S5PV210_MP02(_nr)	(S5PV210_GPIO_MP02_START + (_nr))
 #define S5PV210_MP03(_nr)	(S5PV210_GPIO_MP03_START + (_nr))
+#define S5PV210_MP04(_nr)	(S5PV210_GPIO_MP04_START + (_nr))
+#define S5PV210_MP05(_nr)	(S5PV210_GPIO_MP05_START + (_nr))
 
 /* the end of the S5PV210 specific gpios */
-#define S5PV210_GPIO_END	(S5PV210_MP03(S5PV210_GPIO_MP03_NR) + 1)
+#define S5PV210_GPIO_END	(S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1)
 #define S3C_GPIO_END		S5PV210_GPIO_END
 
 /* define the number of gpios we need to the one after the MP03() range */
-#define ARCH_NR_GPIOS		(S5PV210_MP03(S5PV210_GPIO_MP03_NR) +	\
+#define ARCH_NR_GPIOS		(S5PV210_MP05(S5PV210_GPIO_MP05_NR) +	\
 				 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
 
 #include <asm-generic/gpio.h>
-- 
1.7.1.240.g225c



From saeed at marvell.com  Wed Jun  9 04:51:23 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Wed,  9 Jun 2010 11:51:23 +0300
Subject: [PATCH 1/2 v2] mv643xx_eth: use sw csum for big packets
In-Reply-To: <FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>
References: <FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>
Message-ID: <1276073483-17208-1-git-send-email-saeed@marvell.com>

Some controllers (KW, Dove) limits the TX IP/layer4 checksum offloading to a max size.

Signed-off-by: Saeed Bishara <saeed at marvell.com>
---
 drivers/net/mv643xx_eth.c   |    7 ++++++-
 include/linux/mv643xx_eth.h |    5 +++++
 2 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index e345ec8..2d0e06b 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -289,6 +289,7 @@ struct mv643xx_eth_shared_private {
 	unsigned int t_clk;
 	int extended_rx_coal_limit;
 	int tx_bw_control;
+	int tx_csum_limit;
 };
 
 #define TX_BW_CONTROL_ABSENT		0
@@ -782,7 +783,8 @@ static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
 		       skb->protocol != htons(ETH_P_8021Q));
 
 		tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
-		if (unlikely(tag_bytes & ~12)) {
+		if (unlikely(tag_bytes & ~12) ||
+			skb->len > mp->shared->tx_csum_limit) {
 			if (skb_checksum_help(skb) == 0)
 				goto no_csum;
 			kfree_skb(skb);
@@ -2666,6 +2668,9 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 	 * Detect hardware parameters.
 	 */
 	msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
+	msp->tx_csum_limit = pd->tx_csum_limit ? pd->tx_csum_limit : 9 * 1024;
+	/* add header count so we can compare against skb->len */
+	msp->tx_csum_limit += ETH_HLEN;
 	infer_hw_params(msp);
 
 	platform_set_drvdata(pdev, msp);
diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
index cbbbe9b..30b0c4e 100644
--- a/include/linux/mv643xx_eth.h
+++ b/include/linux/mv643xx_eth.h
@@ -19,6 +19,11 @@ struct mv643xx_eth_shared_platform_data {
 	struct mbus_dram_target_info	*dram;
 	struct platform_device	*shared_smi;
 	unsigned int		t_clk;
+	/*
+	 * Max packet size for Tx IP/Layer 4 checksum, when set to 0, default
+	 * limit of 9KiB will be used.
+	 */
+	int			tx_csum_limit;
 };
 
 #define MV643XX_ETH_PHY_ADDR_DEFAULT	0
-- 
1.6.0.4



From s.hauer at pengutronix.de  Tue Jun  8 02:30:36 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Tue, 8 Jun 2010 08:30:36 +0200
Subject: [PATCH] mxc: Fix pad names for imx51
In-Reply-To: <4C0D6183.1010501@boundarydevices.com>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100604085320.GB25357@pengutronix.de>
	<20100604105347.GA2982@matterhorn.lan>
	<20100604140959.GB2982@matterhorn.lan>
	<4C0D5996.9050906@boundarydevices.com>
	<20100607210448.GA2446@matterhorn.lan>
	<4C0D6183.1010501@boundarydevices.com>
Message-ID: <20100608063036.GB20799@pengutronix.de>

On Mon, Jun 07, 2010 at 02:15:47PM -0700, Troy Kisky wrote:
> Amit Kucheria wrote:
> > On 10 Jun 07, Troy Kisky wrote:
> > 
> >>> On 10 Jun 04, Amit Kucheria wrote:
> >>>
> > 
> > <snip>
> > 
> >>> +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27		IOMUX_PAD(0x614, 0x224,  3, 0x0,   0, NO_PAD_CTRL)
> > 
> > <snip>
> > 
> >>> +#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
> >>> +#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
> >>> +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
> >>> +#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
> >>> +#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
> >>> +#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
> >>> +#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
> >>> +#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
> >>> +#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
> >> Why all the stuttering?
> >> Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
> >>
> > 
> > Just following the convention use in the rest of imx devices. See the
> > following comment at the top of the file:
> > 
> > /*
> >  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
> >  * If <padname> or <padmode> refers to a GPIO, it is named
> >  * GPIO_<unit>_<num> see also iomux-v3.h
> >  */
> > 
> > We could use the short names for pads being used in their "native mode".
> > But as soon as we use the pad in a different mode, such as
> > PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
> > 
> > Regards,
> > Amit
> > 
> 
> I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for
> MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to
> 
>  /*
>   * The naming convention for the pad modes is MX51_PAD_<padname>
>   * or MX51_PAD_<padname>__<padmode> if padname != padmode.
>   * If <padname> or <padmode> refers to a GPIO, it is named
>   * GPIO_<unit>_<num> see also iomux-v3.h
>   */

If anything then MX51_PAD_GPIO_<unit>_<num>. I chose to use the long
name to get a consistent naming and to express the fact that the pad has
a name and the mode has a name which can but don't has to be the same.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From m.szyprowski at samsung.com  Wed Jun  9 05:39:02 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 09 Jun 2010 11:39:02 +0200
Subject: [PATCH] SDHCI-S3C fixes and enhancements (platform specific code)
Message-ID: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>

Hello,

This series includes various fixes to sdhci-s3c driver as well as a
major feature enhancement. This patch series is prepared to get complete
sdhci support on Samsung Aquila board.

A quick overview on the patches:

#1 - trivial compilation break fix
#2 - add support for various methods of notifying the host driver about
     the card insertion/removal (should be compatible with existing code)
#3 - add sdhci driver platform data for all hsmmc controllers on Samsung
     Aquila board

Changes to the sdhci-s3c driver itself will be posted in a separate
patch series for easier merging, please refer to the "[PATCH] SDHCI-S3C
fixes and enhancements (driver specific code)" thread.

A complete list of patches:

[PATCH 1/3] s3c64xx: Fix build without SDHCI controllers
[PATCH 2/3] Samsung: sdhci-s3c: add support for new card detection methods
[PATCH 3/3] s5pv210: Aquila: add definitions for sdhci devices

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center


From m.szyprowski at samsung.com  Wed Jun  9 05:39:05 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 09 Jun 2010 11:39:05 +0200
Subject: [PATCH 3/3] s5pv210: Aquila: add definitions for sdhci devices
In-Reply-To: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
References: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276076345-24370-4-git-send-email-m.szyprowski@samsung.com>

This patch add support for SDHCI blocks on Samsung Aquila board. The
following host controllers are defined:
1. Internal MoviNAND device (permanently wired to the controller)
2. Internal WiFI SDIO device (card is activated by power regualor)
3. External MMC/SD socket (card detection is provided by external
gpio interrupt)

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pv210/Kconfig       |    4 ++
 arch/arm/mach-s5pv210/mach-aquila.c |   66 +++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index b7a2f38..dcc9d74 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -57,7 +57,11 @@ config MACH_AQUILA
 	select CPU_S5PV210
 	select ARCH_SPARSEMEM_ENABLE
 	select S5PV210_SETUP_FB_24BPP
+	select S5PV210_SETUP_SDHCI
 	select S3C_DEV_FB
+	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC1
+	select S3C_DEV_HSMMC2
 	select S5PC110_DEV_ONENAND
 	help
 	  Machine support for the Samsung Aquila target based on S5PC110 SoC
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index fb9dbb2..1b7fe79 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/fb.h>
+#include <linux/gpio.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -22,12 +23,15 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-fb.h>
+#include <mach/regs-gpio.h>
 
 #include <plat/regs-serial.h>
 #include <plat/s5pv210.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+#include <plat/sdhci.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
@@ -116,9 +120,66 @@ static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
 	.setup_gpio	= s5pv210_fb_gpio_setup_24bpp,
 };
 
+/* MoviNAND */
+static struct s3c_sdhci_platdata aquila_hsmmc0_data __initdata = {
+	.max_width		= 4,
+	.cd_type		= S3C_SDHCI_CD_PERMANENT,
+};
+
+/* Wireless LAN */
+static struct s3c_sdhci_platdata aquila_hsmmc1_data __initdata = {
+	.max_width		= 4,
+	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
+	/* ext_cd_{init,cleanup} callbacks will be added later */
+};
+
+/* External Flash */
+#define AQUILA_EXT_FLASH_IRQ	IRQ_EINT(28)	/* S5PV210_GPH3(4) */
+#define AQUILA_EXT_FLASH_EN	S5PV210_MP05(4)
+#define AQUILA_EXT_FLASH_CD	S5PV210_GPH3(4)
+
+static irqreturn_t aquila_ext_flash_card_detect_isr(int irq, void *dev_id)
+{
+	void (*notify_func)(struct platform_device *, int state) = dev_id;
+	notify_func(&s3c_device_hsmmc2, !gpio_get_value(AQUILA_EXT_FLASH_CD));
+	return IRQ_HANDLED;
+}
+
+static int aquila_ext_flash_card_detect_init(
+		void (*notify_func)(struct platform_device *, int state))
+{
+	gpio_request(AQUILA_EXT_FLASH_EN, "FLASH_EN");
+	gpio_direction_output(AQUILA_EXT_FLASH_EN, 1);
+
+	if (request_irq(AQUILA_EXT_FLASH_IRQ, aquila_ext_flash_card_detect_isr,
+				IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+				"SDHCI card detect", notify_func))
+		printk(KERN_ERR "Error: cannot request irq for External Flash\n");
+	return 0;
+}
+
+static int aquila_ext_flash_card_detect_cleanup(
+		void (*notify_func)(struct platform_device *, int state))
+{
+	free_irq(AQUILA_EXT_FLASH_IRQ, notify_func);
+	gpio_direction_output(AQUILA_EXT_FLASH_EN, 0);
+	gpio_free(AQUILA_EXT_FLASH_EN);
+	return 0;
+}
+
+static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = {
+	.max_width		= 4,
+	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
+	.ext_cd_init		= aquila_ext_flash_card_detect_init,
+	.ext_cd_cleanup		= aquila_ext_flash_card_detect_cleanup,
+};
+
 static struct platform_device *aquila_devices[] __initdata = {
 	&s3c_device_fb,
 	&s5pc110_device_onenand,
+	&s3c_device_hsmmc0,
+	&s3c_device_hsmmc1,
+	&s3c_device_hsmmc2,
 };
 
 static void __init aquila_map_io(void)
@@ -130,6 +191,11 @@ static void __init aquila_map_io(void)
 
 static void __init aquila_machine_init(void)
 {
+	/* SDHCI */
+	s3c_sdhci0_set_platdata(&aquila_hsmmc0_data);
+	s3c_sdhci1_set_platdata(&aquila_hsmmc1_data);
+	s3c_sdhci2_set_platdata(&aquila_hsmmc2_data);
+
 	/* FB */
 	s3c_fb_set_platdata(&aquila_lcd_pdata);
 
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun  9 05:39:03 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 09 Jun 2010 11:39:03 +0200
Subject: [PATCH 1/3] s3c64xx: Fix build without SDHCI controllers
In-Reply-To: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
References: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276076345-24370-2-git-send-email-m.szyprowski@samsung.com>

This patch fixes the following compilation problem if only NCP machine
is selected:

arch/arm/mach-s3c64xx/s3c6410.c: In function ?s3c6410_map_io?:
arch/arm/mach-s3c64xx/s3c6410.c:51: error: implicit declaration of function ?s3c6410_default_sdhci2?

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-samsung/include/plat/sdhci.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 13f9fb2..c2044e5 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -166,6 +166,7 @@ static inline void s3c6410_default_sdhci2(void) { }
 #else
 static inline void s3c6410_default_sdhci0(void) { }
 static inline void s3c6410_default_sdhci1(void) { }
+static inline void s3c6410_default_sdhci2(void) { }
 static inline void s3c6400_default_sdhci0(void) { }
 static inline void s3c6400_default_sdhci1(void) { }
 
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun  9 05:39:04 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 09 Jun 2010 11:39:04 +0200
Subject: [PATCH 2/3] Samsung: sdhci-s3c: add support for new card detection
	methods
In-Reply-To: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
References: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276076345-24370-3-git-send-email-m.szyprowski@samsung.com>

On some Samsung SoCs not all SDHCI controllers have card detect (CD)
line. For some embedded designs it is not even needed, because ususally
the device (like SDIO flash memory or wifi controller) is permanently
wired to the controller. There are also systems which have a card detect
line connected to some of the external interrupt lines or the presence
of the card depends on some other actions (like enabling a power
regulator).

This patch adds support for all these cases. The following card
detection methods are possible:

1. internal sdhci host card detect line
2. external event
3. no card detect line, controller will poll for the card
4. no card detect line, card is permanently wired to the controller
(once detected host won't poll it any more)

By default, all existing code would use method #1, what is compatible
with the previous version of the driver.

In case of external event, two callbacks must be provided in platdata:
ext_cd_init and ext_cd_cleanup. Both of them get a callback to a
function that notifies the s3c-sdhci host contoller as their argument.
That callback function should be called from the even dispatcher to let
host notice the card insertion/removal.

This patch adds all required changes to platform support code.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s3c64xx/setup-sdhci-gpio.c   |   14 ++++++++++----
 arch/arm/mach-s5pc100/setup-sdhci-gpio.c   |   21 +++++++++++++++------
 arch/arm/mach-s5pv210/setup-sdhci-gpio.c   |   22 ++++++++++++++++------
 arch/arm/plat-samsung/dev-hsmmc.c          |    3 +++
 arch/arm/plat-samsung/dev-hsmmc1.c         |    3 +++
 arch/arm/plat-samsung/dev-hsmmc2.c         |    3 +++
 arch/arm/plat-samsung/include/plat/sdhci.h |   23 +++++++++++++++++++++++
 7 files changed, 73 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
index a58c0cc..54c311c 100644
--- a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
@@ -22,6 +22,7 @@
 
 void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 	unsigned int end;
 
@@ -33,12 +34,15 @@ void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
 	}
 
-	s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
+	}
 }
 
 void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 	unsigned int end;
 
@@ -50,8 +54,10 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
 	}
 
-	s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
+	}
 }
 
 void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
index 7769c76..e4b6739 100644
--- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
@@ -23,6 +23,7 @@
 
 void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 	unsigned int end;
 	unsigned int num;
@@ -47,12 +48,15 @@ void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 		}
 	}
 
-	s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
+	}
 }
 
 void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 	unsigned int end;
 
@@ -64,12 +68,15 @@ void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
 	}
 
-	s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
+	}
 }
 
 void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 	unsigned int end;
 
@@ -81,6 +88,8 @@ void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
 	}
 
-	s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
+	}
 }
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
index fe7d86d..b3ad243 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
@@ -21,9 +21,11 @@
 #include <mach/gpio.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
 
 void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 
 	/* Set all the necessary GPG0/GPG1 pins to special-function 2 */
@@ -48,12 +50,15 @@ void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 		break;
 	}
 
-	s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2));
+	}
 }
 
 void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 
 	/* Set all the necessary GPG1[0:1] pins to special-function 2 */
@@ -68,12 +73,15 @@ void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
 	}
 
-	s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2));
+	}
 }
 
 void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 
 	/* Set all the necessary GPG2[0:1] pins to special-function 2 */
@@ -99,6 +107,8 @@ void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 		break;
 	}
 
-	s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
+	}
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index 4c05b39..238c6a1 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -60,6 +60,9 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
 	struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
 
 	set->max_width = pd->max_width;
+	set->cd_type = pd->cd_type;
+	set->ext_cd_init = pd->ext_cd_init;
+	set->ext_cd_cleanup = pd->ext_cd_cleanup;
 
 	if (pd->cfg_gpio)
 		set->cfg_gpio = pd->cfg_gpio;
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index e49bc4c..1da8481 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -60,6 +60,9 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
 	struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
 
 	set->max_width = pd->max_width;
+	set->cd_type = pd->cd_type;
+	set->ext_cd_init = pd->ext_cd_init;
+	set->ext_cd_cleanup = pd->ext_cd_cleanup;
 
 	if (pd->cfg_gpio)
 		set->cfg_gpio = pd->cfg_gpio;
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index 824580b..f11b1ca 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -61,6 +61,9 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
 	struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata;
 
 	set->max_width = pd->max_width;
+	set->cd_type = pd->cd_type;
+	set->ext_cd_init = pd->ext_cd_init;
+	set->ext_cd_cleanup = pd->ext_cd_cleanup;
 
 	if (pd->cfg_gpio)
 		set->cfg_gpio = pd->cfg_gpio;
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index c2044e5..6f00a76 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -20,10 +20,27 @@ struct mmc_host;
 struct mmc_card;
 struct mmc_ios;
 
+enum cd_types {
+	S3C_SDHCI_CD_INTERNAL,	/* use mmc internal CD line */
+	S3C_SDHCI_CD_EXTERNAL,	/* use external method (like GPIO interrupt) */
+	S3C_SDHCI_CD_NONE,	/* no CD line, use polling to detect card */
+	S3C_SDHCI_CD_PERMANENT,	/* no CD line, card permanently wired to host */
+};
+
 /**
  * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
  * @max_width: The maximum number of data bits supported.
  * @host_caps: Standard MMC host capabilities bit field.
+ * @cd_type: Type of Card Detection method (see cd_types enum above)
+ * @ext_cd_init: Initialize external card detect subsystem. Called on
+ *		 sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL.
+ *		 notify_func argument is a callback to the sdhci-s3c driver
+ *		 that triggers the card detection event. Callback arguments:
+ *		 dev is pointer to platform device of the host controller,
+ *		 state is new state of the card (0 - removed, 1 - inserted).
+ * @ext_cd_cleanup: Cleanup external card detect subsystem. Called on
+ *		 sdhci-s3c driver remove when cd_type == S3C_SDHCI_CD_EXTERNAL.
+ *		 notify_func argument is the same callback as for ext_cd_init.
  * @cfg_gpio: Configure the GPIO for a specific card bit-width
  * @cfg_card: Configure the interface for a specific card and speed. This
  *            is necessary the controllers and/or GPIO blocks require the
@@ -37,9 +54,15 @@ struct mmc_ios;
 struct s3c_sdhci_platdata {
 	unsigned int	max_width;
 	unsigned int	host_caps;
+	enum cd_types	cd_type;
 
 	char		**clocks;	/* set of clock sources */
 
+	int 	(*ext_cd_init)(void (*notify_func)(struct platform_device *,
+						   int state));
+	int 	(*ext_cd_cleanup)(void (*notify_func)(struct platform_device *,
+						      int state));
+
 	void	(*cfg_gpio)(struct platform_device *dev, int width);
 	void	(*cfg_card)(struct platform_device *dev,
 			    void __iomem *regbase,
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun  9 05:39:38 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 09 Jun 2010 11:39:38 +0200
Subject: [PATCH] SDHCI-S3C fixes and enhancements (driver specific code)
Message-ID: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>

Hello,

This series includes various fixes to sdhci-s3c driver as well as a
major feature enhancement. This patch series is prepared to get complete
sdhci support on Samsung Aquila board.

A quick overview on the patches:

#1 - enable sdhci-s3c driver on all Samsung platforms
#2 - add missing sdhci_s3c_driver_remove() function
#3 - use sdhci quirk to increase the transaction timeout (let me know if
     this can break any exitsting code)
#4 - introduce new sdhci quirk to get rid of anoying runtime warning and
     possible problems with slow mmc/sd cards
#5 - add support for various methods of notifying the host driver about
     the card insertion/removal (should be compatible with existing code)

Last patch requires changes to the Samsung platform setup code, which
has been posted in a separate patch series for easier merging, please
refer to the "[PATCH] SDHCI-S3C fixes and enhancements (platform
specific code)" thread.

A complete list of patches:

[PATCH 1/5] sdhci-s3c: depend on plat-samsung
[PATCH 2/5] sdhci-s3c: add missing remove function
[PATCH 3/5] sdhci-s3c: increase the timeout value
[PATCH 4/5] sdhci-s3c: add support for the non standard minimal clock value
[PATCH 5/5] sdhci-s3c: add support for new card detection methods

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center


From m.szyprowski at samsung.com  Wed Jun  9 05:39:40 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 09 Jun 2010 11:39:40 +0200
Subject: [PATCH 2/5] sdhci-s3c: add missing remove function
In-Reply-To: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
References: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276076383-24825-3-git-send-email-m.szyprowski@samsung.com>

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/mmc/host/sdhci-s3c.c |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index af21792..ad30f07 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -365,6 +365,26 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 
 static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
 {
+	struct sdhci_host *host =  platform_get_drvdata(pdev);
+	struct sdhci_s3c *sc = sdhci_priv(host);
+	int ptr;
+
+	sdhci_remove_host(host, 1);
+
+	for (ptr = 0; ptr < 3; ptr++) {
+		clk_disable(sc->clk_bus[ptr]);
+		clk_put(sc->clk_bus[ptr]);
+	}
+	clk_disable(sc->clk_io);
+	clk_put(sc->clk_io);
+
+	iounmap(host->ioaddr);
+	release_resource(sc->ioarea);
+	kfree(sc->ioarea);
+
+	sdhci_free_host(host);
+	platform_set_drvdata(pdev, NULL);
+
 	return 0;
 }
 
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun  9 05:39:42 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 09 Jun 2010 11:39:42 +0200
Subject: [PATCH 4/5] sdhci-s3c: add support for the non standard minimal clock
	value
In-Reply-To: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
References: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276076383-24825-5-git-send-email-m.szyprowski@samsung.com>

S3C SDHCI host controller can change the source for generating mmc clock.
By default host bus clock is used, what causes some problems on machines
with 133MHz bus, because the SDHCI divider cannot be as high get proper
clock value for identification mode. This is not a problem for the
controller, because it can generate lower frequencies from other clock
sources. This patch adds a new quirk to SDHCI driver to calculate the
minimal supported clock frequency.

This fixes the flood of the following warnings on Samsung S5PV210 SoCs:
mmc0: Minimum clock frequency too high for identification mode

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/mmc/host/sdhci-of-esdhc.c |    1 +
 drivers/mmc/host/sdhci-s3c.c      |   29 +++++++++++++++++++++++++++++
 drivers/mmc/host/sdhci.c          |    2 +-
 drivers/mmc/host/sdhci.h          |    2 ++
 4 files changed, 33 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index c8623de..64b3f79 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -124,6 +124,7 @@ struct sdhci_of_data sdhci_esdhc = {
 		  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 		  SDHCI_QUIRK_NO_BUSY_IRQ |
 		  SDHCI_QUIRK_NONSTANDARD_CLOCK |
+		  SDHCI_QUIRK_NONSTANDARD_MINCLOCK |
 		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 		  SDHCI_QUIRK_PIO_NEEDS_DELAY |
 		  SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 2b6cb44..615008d 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -209,10 +209,37 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
 	}
 }
 
+/**
+ * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
+ * @host: The SDHCI host being queried
+ *
+ * To init mmc host properly a minimal clock value is needed. For high system
+ * bus clock's values the standard formula gives values out of allowed range.
+ * The clock still can be set to lower values, if clock source other then
+ * system bus is selected.
+*/
+static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
+{
+	struct sdhci_s3c *ourhost = to_s3c(host);
+	unsigned int delta, min = UINT_MAX;
+	int src;
+
+	for (src = 0; src < MAX_BUS_CLK; src++) {
+		delta = sdhci_s3c_consider_clock(ourhost, src, 0);
+		if (delta == UINT_MAX)
+			continue;
+		/* delta is a negative value in this case */
+		if (-delta < min)
+			min = -delta;
+	}
+	return min;
+}
+
 static struct sdhci_ops sdhci_s3c_ops = {
 	.get_max_clock		= sdhci_s3c_get_max_clk,
 	.get_timeout_clock	= sdhci_s3c_get_timeout_clk,
 	.set_clock		= sdhci_s3c_set_clock,
+	.get_min_clock		= sdhci_s3c_get_min_clock,
 };
 
 static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
@@ -316,6 +343,8 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	host->quirks = 0;
 	host->irq = irq;
 
+	host->quirks |= SDHCI_QUIRK_NONSTANDARD_MINCLOCK;
+
 	/* Setup quirks for the controller */
 	host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
 
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index c6d1bd8..8b3ee53 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1785,7 +1785,7 @@ int sdhci_add_host(struct sdhci_host *host)
 	 * Set host parameters.
 	 */
 	mmc->ops = &sdhci_ops;
-	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK &&
+	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_MINCLOCK &&
 			host->ops->set_clock && host->ops->get_min_clock)
 		mmc->f_min = host->ops->get_min_clock(host);
 	else
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c846813..3fd87c2 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -240,6 +240,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN		(1<<25)
 /* Controller cannot support End Attribute in NOP ADMA descriptor */
 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC		(1<<26)
+/* Controller has nonstandard clock management */
+#define SDHCI_QUIRK_NONSTANDARD_MINCLOCK		(1<<27)
 
 	int			irq;		/* Device IRQ */
 	void __iomem *		ioaddr;		/* Mapped address */
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun  9 05:39:39 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 09 Jun 2010 11:39:39 +0200
Subject: [PATCH 1/5] sdhci-s3c: depend on plat-samsung
In-Reply-To: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
References: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276076383-24825-2-git-send-email-m.szyprowski@samsung.com>

Most Samsung SoC have support for SDHCI block, so make the driver
dependent on the Samsung platform instead on listing all SoCs in the
Kconfig (and updating it again when support for the new SoC variant is
added).

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/mmc/host/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index e171e77..acf5bf6 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -123,7 +123,7 @@ config MMC_SDHCI_PLTFM
 
 config MMC_SDHCI_S3C
 	tristate "SDHCI support on Samsung S3C SoC"
-	depends on MMC_SDHCI && (PLAT_S3C24XX || PLAT_S3C64XX)
+	depends on MMC_SDHCI && PLAT_SAMSUNG
 	help
 	  This selects the Secure Digital Host Controller Interface (SDHCI)
 	  often referrered to as the HSMMC block in some of the Samsung S3C
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun  9 05:39:41 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 09 Jun 2010 11:39:41 +0200
Subject: [PATCH 3/5] sdhci-s3c: increase the timeout value
In-Reply-To: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
References: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276076383-24825-4-git-send-email-m.szyprowski@samsung.com>

This patch increases the timeout value on sdhci-s3c controller by using
SDHCI_QUIRK_BROKEN_TIMEOUT_VAL quirk. Without it most transfers from
external mmc cards fails on Samsung s5pv210 SoCs based systems. Tested
on Samsung Aquila board.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/mmc/host/sdhci-s3c.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index ad30f07..2b6cb44 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -331,6 +331,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	 * transfers, not sure if this is a problem with this specific
 	 * SDHCI block, or a missing configuration that needs to be set. */
 	host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
+	host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 
 	host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
 			 SDHCI_QUIRK_32BIT_DMA_SIZE);
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun  9 05:39:43 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 09 Jun 2010 11:39:43 +0200
Subject: [PATCH 5/5] sdhci-s3c: add support for new card detection methods
In-Reply-To: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
References: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276076383-24825-6-git-send-email-m.szyprowski@samsung.com>

On some Samsung SoCs not all SDHCI controllers have card detect (CD)
line. For some embedded designs it is not even needed, because ususally
the device (like SDIO flash memory or wifi controller) is permanently
wired to the controller. There are also systems which have a card detect
line connected to some of the external interrupt lines or the presence
of the card depends on some other actions (like enabling a power
regulator).

This patch adds support for all these cases. The following card
detection methods are possible:

1. internal sdhci host card detect line
2. external event
3. no card detect line, controller will poll for the card
4. no card detect line, card is permanently wired to the controller
(once detected host won't poll it any more)

By default, all existing code would use method #1, what is compatible
with the previous version of the driver.

In case of external event, two callbacks must be provided in platdata:
ext_cd_init and ext_cd_cleanup. Both of them get a callback to a
function that notifies the s3c-sdhci host contoller as their argument.
That callback function should be called from the even dispatcher to let
host notice the card insertion/removal.

This patch adds changes to sdhci-s3c driver.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/mmc/host/sdhci-s3c.c |   38 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 615008d..7de801d 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -242,6 +242,29 @@ static struct sdhci_ops sdhci_s3c_ops = {
 	.get_min_clock		= sdhci_s3c_get_min_clock,
 };
 
+static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
+{
+	struct sdhci_host *host;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	host = platform_get_drvdata(dev);
+	if (host) {
+		if (state) {
+			dev_info(&dev->dev, "card inserted.\n");
+			host->flags &= ~SDHCI_DEVICE_DEAD;
+			host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+			tasklet_schedule(&host->card_tasklet);
+		} else {
+			dev_info(&dev->dev, "card removed.\n");
+			host->flags |= SDHCI_DEVICE_DEAD;
+			host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+			tasklet_schedule(&host->card_tasklet);
+		}
+	}
+	local_irq_restore(flags);
+}
+
 static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 {
 	struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
@@ -362,6 +385,13 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
 	host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 
+	if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
+	    pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
+		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+
+	if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
+		host->mmc->caps = MMC_CAP_NONREMOVABLE;
+
 	host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
 			 SDHCI_QUIRK_32BIT_DMA_SIZE);
 
@@ -371,6 +401,11 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 		goto err_add_host;
 	}
 
+	/* pdata->ext_cd_init might call sdhci_s3c_notify_change immediately,
+	   so it can be called only after sdhci_add_host() */
+	if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init)
+		pdata->ext_cd_init(&sdhci_s3c_notify_change);
+
 	return 0;
 
  err_add_host:
@@ -399,6 +434,9 @@ static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
 	struct sdhci_s3c *sc = sdhci_priv(host);
 	int ptr;
 
+	if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup)
+		pdata->ext_cd_cleanup(&sdhci_s3c_notify_change);
+
 	sdhci_remove_host(host, 1);
 
 	for (ptr = 0; ptr < 3; ptr++) {
-- 
1.7.1.240.g225c



From broonie at opensource.wolfsonmicro.com  Wed Jun  9 06:17:43 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 9 Jun 2010 11:17:43 +0100
Subject: [PATCH 0/3] EP93xx: Add i2s audio support
In-Reply-To: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <20100609101742.GA5618@opensource.wolfsonmicro.com>

On Tue, Jun 08, 2010 at 10:01:09PM +1200, Ryan Mallon wrote:
> Repost of the i2s audio series for ep93xx. Patch 2/3 is unchanged. The
> core support has been modified to move setting of the SPOL and ORIDE
> bits of the i2sclkdiv register, as well as the i2s pin strapping
> configuration, to a new function called ep93xx_i2s_acquire which is
> called from the audio board drivers.

I've now applied both patches.  There was a trivial fixup required for
the clocks due to an add/add overlap with the SPI clock - I think it's
OK but please check.


From baruch at tkos.co.il  Wed Jun  9 07:06:59 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed,  9 Jun 2010 14:06:59 +0300
Subject: [PATCH 0/3] MX25 watchdog
Message-ID: <cover.1276081393.git.baruch@tkos.co.il>

This series adds support for the new watchdog driver on the i.MX25 PDK 
platform. A little fix to the watchdog driver itself is also added.

Baruch Siach (3):
  mx25: add watchdog clock
  mx25pdk: register watchdog device
  imx2_wdt: fix section mismatch

 arch/arm/mach-mx25/clock.c        |    2 ++
 arch/arm/mach-mx25/mach-mx25pdk.c |    1 +
 drivers/watchdog/imx2_wdt.c       |    1 -
 3 files changed, 3 insertions(+), 1 deletions(-)



From baruch at tkos.co.il  Wed Jun  9 07:07:00 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed,  9 Jun 2010 14:07:00 +0300
Subject: [PATCH 1/3] mx25: add watchdog clock
In-Reply-To: <cover.1276081393.git.baruch@tkos.co.il>
References: <cover.1276081393.git.baruch@tkos.co.il>
Message-ID: <bc8385e0c903851918839a66f9e582a507434e93.1276081393.git.baruch@tkos.co.il>

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 arch/arm/mach-mx25/clock.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 1550149..f9662d9 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -191,6 +191,7 @@ DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
 DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
 DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
+DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR1, 19, get_rate_ipg, NULL,  NULL);
 
 #define _REGISTER_CLOCK(d, n, c)	\
 	{				\
@@ -225,6 +226,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("fec.0", NULL, fec_clk)
 	_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
 	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+	_REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
 };
 
 int __init mx25_clocks_init(void)
-- 
1.7.1



From baruch at tkos.co.il  Wed Jun  9 07:07:01 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed,  9 Jun 2010 14:07:01 +0300
Subject: [PATCH 2/3] mx25pdk: register watchdog device
In-Reply-To: <cover.1276081393.git.baruch@tkos.co.il>
References: <cover.1276081393.git.baruch@tkos.co.il>
Message-ID: <a8fd2ca108974bd7fac663c470b3b22e0543d41c.1276081393.git.baruch@tkos.co.il>

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 arch/arm/mach-mx25/mach-mx25pdk.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx25/mach-mx25pdk.c b/arch/arm/mach-mx25/mach-mx25pdk.c
index 83d7410..9ef99f8 100644
--- a/arch/arm/mach-mx25/mach-mx25pdk.c
+++ b/arch/arm/mach-mx25/mach-mx25pdk.c
@@ -147,6 +147,7 @@ static void __init mx25pdk_init(void)
 	mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info);
 	mxc_register_device(&mx25_rtc_device, NULL);
 	mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
+	mxc_register_device(&mxc_wdt, NULL);
 
 	mx25pdk_fec_reset();
 	mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
-- 
1.7.1



From baruch at tkos.co.il  Wed Jun  9 07:07:02 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed,  9 Jun 2010 14:07:02 +0300
Subject: [PATCH 3/3] imx2_wdt: fix section mismatch
In-Reply-To: <cover.1276081393.git.baruch@tkos.co.il>
References: <cover.1276081393.git.baruch@tkos.co.il>
Message-ID: <31360d4c97db0e754d15f27567b4592010bdd831.1276081393.git.baruch@tkos.co.il>

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
Cc: Wim Van Sebroeck <wim at iguana.be>
---
 drivers/watchdog/imx2_wdt.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
index ea25885..2ee7dac 100644
--- a/drivers/watchdog/imx2_wdt.c
+++ b/drivers/watchdog/imx2_wdt.c
@@ -330,7 +330,6 @@ static void imx2_wdt_shutdown(struct platform_device *pdev)
 }
 
 static struct platform_driver imx2_wdt_driver = {
-	.probe		= imx2_wdt_probe,
 	.remove		= __exit_p(imx2_wdt_remove),
 	.shutdown	= imx2_wdt_shutdown,
 	.driver		= {
-- 
1.7.1



From mike at compulab.co.il  Wed Jun  9 07:49:51 2010
From: mike at compulab.co.il (Mike Rapoport)
Date: Wed, 09 Jun 2010 14:49:51 +0300
Subject: [PATCH 0/5] Enable pxa310 usb otg port host mode.
In-Reply-To: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <4C0F7FDF.2000702@compulab.co.il>

Eric, Greg,
Any comments on this?

Igor Grinberg wrote:
> This patch series extends the existing usb ulpi generic driver
> with support for Function and Interface control of the ULPI PHYs,
> adds support for SMSC USB3319 ulpi phy,
> implement the pxa310 specific ulpi functionality and make pxa specific ohci
> implementation aware of pxa310 usb otg port host mode.
> 
> Igor Grinberg (5):
>   usb/otg/ulpi: extend the generic ulpi driver.
>   usb/otg/ulpi: add support for SMSC USB3319 ulpi phy.
>   [ARM] pxa: add PXA310 specific ULPI implementation
>   [ARM] usb/host/ohci-pxa27x: make PXA310 USB OTG port work in host
>     mode.
>   [ARM] pxa/cm-x300: enable USB host port 2 on CM-X300 with PXA310 cpu.
> 
>  arch/arm/mach-mx2/mach-pca100.c              |   10 +-
>  arch/arm/mach-mx3/mach-armadillo5x0.c        |   10 +-
>  arch/arm/mach-mx3/mach-mx31lite.c            |    5 +-
>  arch/arm/mach-mx3/mach-mx31moboard.c         |    5 +-
>  arch/arm/mach-mx3/mach-pcm037.c              |   10 +-
>  arch/arm/mach-mx3/mach-pcm043.c              |    5 +-
>  arch/arm/mach-pxa/Kconfig                    |    4 +
>  arch/arm/mach-pxa/Makefile                   |    1 +
>  arch/arm/mach-pxa/cm-x300.c                  |  102 ++++++++++++++
>  arch/arm/mach-pxa/include/mach/ohci.h        |    3 +
>  arch/arm/mach-pxa/include/mach/pxa310-ulpi.h |   19 +++
>  arch/arm/mach-pxa/include/mach/regs-u2d.h    |    2 +
>  arch/arm/mach-pxa/pxa310-ulpi.c              |  110 +++++++++++++++
>  drivers/usb/host/ohci-pxa27x.c               |  183 ++++++++++++++++++++++++++
>  drivers/usb/otg/Kconfig                      |    2 -
>  drivers/usb/otg/ulpi.c                       |   65 ++++++++-
>  include/linux/usb/ulpi.h                     |   25 ++++-
>  17 files changed, 542 insertions(+), 19 deletions(-)
>  create mode 100644 arch/arm/mach-pxa/include/mach/pxa310-ulpi.h
>  create mode 100644 arch/arm/mach-pxa/pxa310-ulpi.c
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


-- 
Sincerely yours,
Mike.


From kgene.kim at samsung.com  Wed Jun  9 08:10:38 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 09 Jun 2010 21:10:38 +0900
Subject: [PATCH] arm: s5pv210: add more banks to gpiolib
In-Reply-To: <1276072833-4862-1-git-send-email-m.szyprowski@samsung.com>
References: <1276072833-4862-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <010301cb07cc$c8affa50$5a0feef0$%kim@samsung.com>

Marek Szyprowski wrote:
> 
> This patch adds support for MP04 and MP05 gpio banks. Pins from these
> banks will be used by Samsung Aquila board.
> 
Hi,

> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> 
> ---
>  arch/arm/mach-s5pv210/gpiolib.c           |   17 +++++++++++++++++
>  arch/arm/mach-s5pv210/include/mach/gpio.h |   10 ++++++++--
>  2 files changed, 25 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/gpiolib.c
b/arch/arm/mach-s5pv210/gpiolib.c
> index f4ac81f..6f74a98 100644
> --- a/arch/arm/mach-s5pv210/gpiolib.c
> +++ b/arch/arm/mach-s5pv210/gpiolib.c
> @@ -208,6 +208,22 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
>  			.label	= "MP03",
>  		},
>  	}, {
> +		.base	= (S5P_VA_GPIO + 0x340),

don't need .base
it can be calculated in s5pv210_gpiolib_init()

> +		.config	= &gpio_cfg_noint,
> +		.chip	= {
> +			.base	= S5PV210_MP04(0),
> +			.ngpio	= S5PV210_GPIO_MP04_NR,
> +			.label	= "MP04",
> +		},
> +	}, {
> +		.base	= (S5P_VA_GPIO + 0x360),

same

> +		.config	= &gpio_cfg_noint,
> +		.chip	= {
> +			.base	= S5PV210_MP05(0),
> +			.ngpio	= S5PV210_GPIO_MP05_NR,
> +			.label	= "MP05",
> +		},
> +	}, {
>  		.base	= (S5P_VA_GPIO + 0xC00),
>  		.config	= &gpio_cfg_noint,
>  		.chip	= {
> @@ -244,6 +260,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
>  			.to_irq = s5p_gpiolib_eint_to_irq,
>  		},
>  	},
> +

redundant empty line

>  };
> 
>  static __init int s5pv210_gpiolib_init(void)
> diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-
> s5pv210/include/mach/gpio.h
> index d6461ba..33a9867 100644
> --- a/arch/arm/mach-s5pv210/include/mach/gpio.h
> +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h
> @@ -52,6 +52,8 @@
>  #define S5PV210_GPIO_MP01_NR	(8)
>  #define S5PV210_GPIO_MP02_NR	(4)
>  #define S5PV210_GPIO_MP03_NR	(8)
> +#define S5PV210_GPIO_MP04_NR	(8)
> +#define S5PV210_GPIO_MP05_NR	(8)
> 
>  /* GPIO bank numbers */
> 
> @@ -94,6 +96,8 @@ enum s5p_gpio_number {
>  	S5PV210_GPIO_MP01_START	=
> S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
>  	S5PV210_GPIO_MP02_START	=
> S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
>  	S5PV210_GPIO_MP03_START	=
> S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
> +	S5PV210_GPIO_MP04_START	=
> S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03),
> +	S5PV210_GPIO_MP05_START	=
> S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04),
>  };
> 
>  /* S5PV210 GPIO number definitions */
> @@ -127,13 +131,15 @@ enum s5p_gpio_number {
>  #define S5PV210_MP01(_nr)	(S5PV210_GPIO_MP01_START + (_nr))
>  #define S5PV210_MP02(_nr)	(S5PV210_GPIO_MP02_START + (_nr))
>  #define S5PV210_MP03(_nr)	(S5PV210_GPIO_MP03_START + (_nr))
> +#define S5PV210_MP04(_nr)	(S5PV210_GPIO_MP04_START + (_nr))
> +#define S5PV210_MP05(_nr)	(S5PV210_GPIO_MP05_START + (_nr))
> 
>  /* the end of the S5PV210 specific gpios */
> -#define S5PV210_GPIO_END	(S5PV210_MP03(S5PV210_GPIO_MP03_NR) +
> 1)
> +#define S5PV210_GPIO_END	(S5PV210_MP05(S5PV210_GPIO_MP05_NR) +
> 1)
>  #define S3C_GPIO_END		S5PV210_GPIO_END
> 
>  /* define the number of gpios we need to the one after the MP03() range */

need to modify to MP05()

> -#define ARCH_NR_GPIOS
> 	(S5PV210_MP03(S5PV210_GPIO_MP03_NR) +	\
> +#define ARCH_NR_GPIOS
> 	(S5PV210_MP05(S5PV210_GPIO_MP05_NR) +	\
>  				 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
> 
>  #include <asm-generic/gpio.h>
> --

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From eric.y.miao at gmail.com  Wed Jun  9 08:43:02 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 9 Jun 2010 20:43:02 +0800
Subject: [PATCH 0/5] Enable pxa310 usb otg port host mode.
In-Reply-To: <4C0F7FDF.2000702@compulab.co.il>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il> 
	<4C0F7FDF.2000702@compulab.co.il>
Message-ID: <AANLkTikr0b9e7LZZL4RqlHP3BBhIn-wjfgK8e2Ybztdn@mail.gmail.com>

On Wed, Jun 9, 2010 at 7:49 PM, Mike Rapoport <mike at compulab.co.il> wrote:
> Eric, Greg,
> Any comments on this?
>

The basic idea looks OK to me, but I need some time to look into the
detail esp. those HW specific where Marvell guys are a bit silent :-/


From m.szyprowski at samsung.com  Wed Jun  9 09:08:39 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 09 Jun 2010 15:08:39 +0200
Subject: [PATCH v2] arm: s5pv210: add more banks to gpiolib
Message-ID: <1276088919-20730-1-git-send-email-m.szyprowski@samsung.com>

This patch adds support for MP04 and MP05 gpio banks.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>

---

Changes since v1:
- fixed style issues reported by Kukjin Kim

 arch/arm/mach-s5pv210/gpiolib.c           |   14 ++++++++++++++
 arch/arm/mach-s5pv210/include/mach/gpio.h |   12 +++++++++---
 2 files changed, 23 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
index f4ac81f..0261908 100644
--- a/arch/arm/mach-s5pv210/gpiolib.c
+++ b/arch/arm/mach-s5pv210/gpiolib.c
@@ -208,6 +208,20 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.label	= "MP03",
 		},
 	}, {
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PV210_MP04(0),
+			.ngpio	= S5PV210_GPIO_MP04_NR,
+			.label	= "MP04",
+		},
+	}, {
+		.config	= &gpio_cfg_noint,
+		.chip	= {
+			.base	= S5PV210_MP05(0),
+			.ngpio	= S5PV210_GPIO_MP05_NR,
+			.label	= "MP05",
+		},
+	}, {
 		.base	= (S5P_VA_GPIO + 0xC00),
 		.config	= &gpio_cfg_noint,
 		.chip	= {
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio.h
index d6461ba..1f4b595 100644
--- a/arch/arm/mach-s5pv210/include/mach/gpio.h
+++ b/arch/arm/mach-s5pv210/include/mach/gpio.h
@@ -52,6 +52,8 @@
 #define S5PV210_GPIO_MP01_NR	(8)
 #define S5PV210_GPIO_MP02_NR	(4)
 #define S5PV210_GPIO_MP03_NR	(8)
+#define S5PV210_GPIO_MP04_NR	(8)
+#define S5PV210_GPIO_MP05_NR	(8)
 
 /* GPIO bank numbers */
 
@@ -94,6 +96,8 @@ enum s5p_gpio_number {
 	S5PV210_GPIO_MP01_START	= S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
 	S5PV210_GPIO_MP02_START	= S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
 	S5PV210_GPIO_MP03_START	= S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
+	S5PV210_GPIO_MP04_START	= S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03),
+	S5PV210_GPIO_MP05_START	= S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04),
 };
 
 /* S5PV210 GPIO number definitions */
@@ -127,13 +131,15 @@ enum s5p_gpio_number {
 #define S5PV210_MP01(_nr)	(S5PV210_GPIO_MP01_START + (_nr))
 #define S5PV210_MP02(_nr)	(S5PV210_GPIO_MP02_START + (_nr))
 #define S5PV210_MP03(_nr)	(S5PV210_GPIO_MP03_START + (_nr))
+#define S5PV210_MP04(_nr)	(S5PV210_GPIO_MP04_START + (_nr))
+#define S5PV210_MP05(_nr)	(S5PV210_GPIO_MP05_START + (_nr))
 
 /* the end of the S5PV210 specific gpios */
-#define S5PV210_GPIO_END	(S5PV210_MP03(S5PV210_GPIO_MP03_NR) + 1)
+#define S5PV210_GPIO_END	(S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1)
 #define S3C_GPIO_END		S5PV210_GPIO_END
 
-/* define the number of gpios we need to the one after the MP03() range */
-#define ARCH_NR_GPIOS		(S5PV210_MP03(S5PV210_GPIO_MP03_NR) +	\
+/* define the number of gpios we need to the one after the MP05() range */
+#define ARCH_NR_GPIOS		(S5PV210_MP05(S5PV210_GPIO_MP05_NR) +	\
 				 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
 
 #include <asm-generic/gpio.h>
-- 
1.7.1.240.g225c



From amit.kucheria at canonical.com  Wed Jun  9 09:09:04 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Wed, 9 Jun 2010 15:09:04 +0200
Subject: [PATCH] mxc: Fix pad names for imx51
In-Reply-To: <20100608063036.GB20799@pengutronix.de>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100604085320.GB25357@pengutronix.de>
	<20100604105347.GA2982@matterhorn.lan>
	<20100604140959.GB2982@matterhorn.lan>
	<4C0D5996.9050906@boundarydevices.com>
	<20100607210448.GA2446@matterhorn.lan>
	<4C0D6183.1010501@boundarydevices.com>
	<20100608063036.GB20799@pengutronix.de>
Message-ID: <20100609130904.GA2599@eyjafjallajokull>

On 10 Jun 08, Sascha Hauer wrote:
> On Mon, Jun 07, 2010 at 02:15:47PM -0700, Troy Kisky wrote:
> > Amit Kucheria wrote:
> > > On 10 Jun 07, Troy Kisky wrote:
> > > 
> > >>> On 10 Jun 04, Amit Kucheria wrote:
> > >>>
> > > 
> > > <snip>
> > > 
> > >>> +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27		IOMUX_PAD(0x614, 0x224,  3, 0x0,   0, NO_PAD_CTRL)
> > > 
> > > <snip>
> > > 
> > >>> +#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
> > >>> +#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
> > >>> +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
> > >>> +#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
> > >>> +#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
> > >>> +#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
> > >>> +#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
> > >>> +#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
> > >>> +#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
> > >> Why all the stuttering?
> > >> Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
> > >>
> > > 
> > > Just following the convention use in the rest of imx devices. See the
> > > following comment at the top of the file:
> > > 
> > > /*
> > >  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
> > >  * If <padname> or <padmode> refers to a GPIO, it is named
> > >  * GPIO_<unit>_<num> see also iomux-v3.h
> > >  */
> > > 
> > > We could use the short names for pads being used in their "native mode".
> > > But as soon as we use the pad in a different mode, such as
> > > PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
> > > 
> > > Regards,
> > > Amit
> > > 
> > 
> > I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for
> > MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to
> > 
> >  /*
> >   * The naming convention for the pad modes is MX51_PAD_<padname>
> >   * or MX51_PAD_<padname>__<padmode> if padname != padmode.
> >   * If <padname> or <padmode> refers to a GPIO, it is named
> >   * GPIO_<unit>_<num> see also iomux-v3.h
> >   */
> 
> If anything then MX51_PAD_GPIO_<unit>_<num>. I chose to use the long
> name to get a consistent naming and to express the fact that the pad has
> a name and the mode has a name which can but don't has to be the same.
> 

So will you take a modified patch to reflect this new naming convention?

Regards,
Amit
-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------


From nico at fluxnic.net  Wed Jun  9 09:09:54 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 09 Jun 2010 09:09:54 -0400 (EDT)
Subject: Boot interface for device trees on ARM
In-Reply-To: <201006091226.15438.jeremy.kerr@canonical.com>
References: <201005181054.32325.jeremy.kerr@canonical.com>
	<201006050933.06714.jeremy.kerr@canonical.com>
	<alpine.LFD.2.00.1006042212400.30664@xanadu.home>
	<201006091226.15438.jeremy.kerr@canonical.com>
Message-ID: <alpine.LFD.2.00.1006090841310.30664@xanadu.home>

On Wed, 9 Jun 2010, Jeremy Kerr wrote:

> Hi Nicolas,
> 
> > > If we're planning to keep the machine IDs around (even if they are now
> > > per- SoC), I'd like to know what would be left using them. The only
> > > thing that I can see that we currently use is io_pg_offset for the
> > > DEBUG_LL builds, and that isn't a convincing case to keep them.
> > 
> > Why not?
> 
> Because it's something we can justifiably replace with a single compile-time 
> constant, since it's only for low-level debug. I don't see that as a reason 
> for keeping these machine numbers around if that's all they're used for.

it's not only for that.  As I said below:

> > Kernel infrastructure backward compatibility means that you need to keep
> > struct machine_desc instances around.  Granted, for the DT case, many of
> > the members could be NULL or initialized with dummy stubs.  But that is
> > very cheap to keep around, and that allows the same kernel binary to be
> > able to use both the DT boot and the legacy boot.
> 
> ... this is a good point; if it helps with the transition, then this is 
> probably a decent reason to keep it in the interface.
> 
> I'd like to keep my "only use the device tree" value (MACH_TYPE_DT = 
> 0xffffffff) though, so we don't needlessly allocate machine numbers where they 
> aren't actually used.

There isn't such thing as "only use the device tree".  To keep the low 
level code _unmodified_ and _useful_ you'll have to allocate a number 
per machine class otherwise you won't be able to support more than one 
machine class in the same kernel binary at the same time.  You can't 
just say that those machine IDs aren't used.

I don't see the point of crippling that existing support just for the 
sake of using 0xffffffff, if it is only to save you a few machine ID 
registrations.  Because let's be honest, we won't DT-ify old machine 
targets anytime soon.  So only the recent and future machine classes 
will require a number, and that's probably on the order of 2 or 3 new 
IDs per year (meaning less than 5 minutes on RMK's automatic 
registration website).  Certainly much much less than the current 2000+ 
IDs that have been already allocated to date.


Nicolas


From dwalker at codeaurora.org  Wed Jun  9 09:32:58 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Wed, 09 Jun 2010 06:32:58 -0700
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006090807.20810.post@hendrik-sattler.de>
References: <4C083BCF.2060500@bluewatersys.com>
	<alpine.LFD.2.00.1006081655350.30664@xanadu.home>
	<4C0ED074.7050700@bluewatersys.com>
	<201006090807.20810.post@hendrik-sattler.de>
Message-ID: <1276090378.2006.11.camel@m0nster>

On Wed, 2010-06-09 at 08:07 +0200, Hendrik Sattler wrote:
> Am Mittwoch 09 Juni 2010, 01:21:24 schrieb Ryan Mallon:
> > Yes. I thought the problem was that Kconfig doesn't work correctly for
> > this though. Does having 'select MTD_PARTITIONS' automatically cause
> > CONFIG_MTD to be set? If not, then you basically need to have the full
> > config option list, which is basically what defconfig is.
> 
> Anybody thought about improving Kconfig to make this possible?
> Specifying CONFIG_MTD and CONFIG_MTD_PARTITIONS again and again will just 
> repeat information (that CONFIG_MTD_PARTITIONS depends on CONFIG_MTD).
> The recursive 'select' could have a different name.

There is work going on to create a SAT solver because the depends lines
are often expression instead of just specifying a single other config
option. So updating the select to work correctly isn't entirely trivial.

The other thing the SAT solver _could_ do is trivialize the current
defconfig into files to only 10 lines or so depending on which arm ..
For instance a defconfig file for trout under mach-msm (the one I
maintain) would look like this,

CONFIG_MACH_TROUT=y
CONFIG_MSM_DEBUG_UART3=y
CONFIG_MMC_MSM7X00A=y

then the solver would just deduce every other option. So three lines vs.
the current 1800+ lines. The files would become manageable, and readable
since they're so much smaller. However, we would still have all the
current files we have now.

That's all speculation still, since this solver thing doesn't exist yet.
We would have to drive it in this direction.

Daniel




From robert.jarzmik at free.fr  Wed Jun  9 09:59:52 2010
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Wed, 09 Jun 2010 15:59:52 +0200
Subject: [PATCH] pxa2xx/cpufreq: Fix DRI computation
In-Reply-To: <201006082136.30785.marek.vasut@gmail.com> (Marek Vasut's message
	of "Tue, 8 Jun 2010 21:36:30 +0200")
References: <1275698808-31166-1-git-send-email-marek.vasut@gmail.com>
	<87ljap7opx.fsf@free.fr> <201006082136.30785.marek.vasut@gmail.com>
Message-ID: <87typcwbl3.fsf@free.fr>

Marek Vasut <marek.vasut at gmail.com> writes:
>> > @@ -251,17 +251,42 @@ static void init_sdram_rows(void)
>> > 
>> >  	if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
>> >  	
>> >  		drac0 = MDCNFG_DRAC0(mdcnfg);
>> > 
>> > -	sdram_rows = 1 << (11 + max(drac0, drac2));
>> > +	sdram_rows = 11 + max(drac0, drac2);
>> 
>> I don't think that's correct.
>> From DRACn, you learn that SDRAM row is selected from 11+DRACn bits. That
>> means that if drac == 2, then the SDRAM row is a number between 0 and
>> (11+drac0) - 1. That in turn means that the number of SDRAM rows is : 2 ^
>> (11 + drac0). Example:
>>  - drac0 = 2 : row encoded on 13 bits => 2^13 rows (ie. 1 << (11 + 2)).
>
> That I'm aware of, but are you sure the TRM means it that way ?
Not entirely sure, but quite. I'll check against values in WinCE on 2 different
platforms (mioa701 and hx4700) to be sure.

>> I don't agree here either. The "freq" variable is in kHz.
>
> That's concerning the TRM, not the freq value. In TRM, it's in MHz.
In mine, there is no unit, which means that frequency is in Hz, and refresh time
in seconds (equivalent to freq in kHz and refresh in ms).
Moreover, my TRM states :
 dri = (Number of CLK_MEM cycles ? 31) / 32
     = (Refresh time / rows x memory clock frequency ? 31) / 32.
This means :
  Number of CLK_MEM cycles = Refresh time / rows x memory clock frequency
You have to balance the physical units, so :
  number (no unit) = refresh_time(s) / rows (no unit) * mem_clock_freq(hz=1/s)
If you had refresh_time in ms and mem_clock_freq in MHz, the units would not be
balanced :
  no_unit = ms / no_unit * MHz
          = 1/1000s / no_unit * 1000000 * 1/s
          = 1000 / no_unit
  => 1 = 1000
  => can't be true, can it ?

>> And my understanding is that the legacy formula is incorrect, as you
>> discovered it. Yet it should be, IMO :
>>     if (cpu_is_pxa27x())
>> -       dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
>> +       dri = ((freq * SDRAM_TREF) / sdram_rows - 31) / 32;
>> 
>> This is the only change to apply IMHO.
>
> Ok, but still, even though I fixed it your way, it doesn't fix the real problem, 
> I'll recheck though, I just need a few days too.
Okay, even if that settles the issue on my platform, there might be something
left. If your platform runs under another OS, could you post the values of
MDREFR and MDCNFG (ie. physical range from 0x48000000 to 0x48000008) ?

Cheers.

--
Robert


From jason.mcmullan at netronome.com  Wed Jun  9 10:35:37 2010
From: jason.mcmullan at netronome.com (Jason S. McMullan)
Date: Wed,  9 Jun 2010 10:35:37 -0400
Subject: kirkwood: USB OTG support
Message-ID: <1276094138-13497-1-git-send-email-jason.mcmullan@netronome.com>

The following patch leverages the Freescale USB OTG driver
to provide support for the Kirkwood. Both SoCs use the
ARC International USB OTG core IP.

diffstat:
 arch/arm/mach-kirkwood/common.c |   34 +++++++++++++++++++++++++++++-----
 arch/arm/mach-kirkwood/common.h |    1 +
 drivers/usb/gadget/Kconfig      |    2 +-
 3 files changed, 31 insertions(+), 6 deletions(-)



From jason.mcmullan at netronome.com  Wed Jun  9 10:35:38 2010
From: jason.mcmullan at netronome.com (Jason S. McMullan)
Date: Wed,  9 Jun 2010 10:35:38 -0400
Subject: [PATCH] [kirkwood-otg] Leverage the Freescale OTG driver for Kirkwood
	OTG
In-Reply-To: <1276094138-13497-1-git-send-email-jason.mcmullan@netronome.com>
References: <1276094138-13497-1-git-send-email-jason.mcmullan@netronome.com>
Message-ID: <1276094138-13497-2-git-send-email-jason.mcmullan@netronome.com>

The Freescale USB Gadget driver is based off of the
same USB OTG core that is used in the Kirkwood.

NOTE: Your bootloader must ensure that the Kirkwood
      USB 2.0 Bridge Window registers are set correctly,
      or the driver will stall on the first DMA.

Signed-off-by: Jason S. McMullan <jason.mcmullan at netronome.com>
---
 arch/arm/mach-kirkwood/common.c |   34 +++++++++++++++++++++++++++++-----
 arch/arm/mach-kirkwood/common.h |    1 +
 drivers/usb/gadget/Kconfig      |    2 +-
 3 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 6072eaa..a1aef59 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -18,6 +18,7 @@
 #include <linux/ata_platform.h>
 #include <linux/mtd/nand.h>
 #include <linux/spi/orion_spi.h>
+#include <linux/fsl_devices.h>
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
@@ -63,7 +64,6 @@ void __init kirkwood_map_io(void)
  */
 unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
 	
-
 /*****************************************************************************
  * EHCI
  ****************************************************************************/
@@ -78,7 +78,7 @@ static u64 ehci_dmamask = 0xffffffffUL;
 /*****************************************************************************
  * EHCI0
  ****************************************************************************/
-static struct resource kirkwood_ehci_resources[] = {
+static struct resource kirkwood_usb_resources[] = {
 	{
 		.start	= USB_PHYS_BASE,
 		.end	= USB_PHYS_BASE + 0x0fff,
@@ -98,8 +98,8 @@ static struct platform_device kirkwood_ehci = {
 		.coherent_dma_mask	= 0xffffffff,
 		.platform_data		= &kirkwood_ehci_data,
 	},
-	.resource	= kirkwood_ehci_resources,
-	.num_resources	= ARRAY_SIZE(kirkwood_ehci_resources),
+	.resource	= kirkwood_usb_resources,
+	.num_resources	= ARRAY_SIZE(kirkwood_usb_resources),
 };
 
 void __init kirkwood_ehci_init(void)
@@ -108,6 +108,31 @@ void __init kirkwood_ehci_init(void)
 	platform_device_register(&kirkwood_ehci);
 }
 
+static struct fsl_usb2_platform_data kirkwood_otg_data = {
+	.operating_mode = FSL_USB2_DR_DEVICE,
+	.phy_mode       = FSL_USB2_PHY_UTMI,
+};
+
+static u64 otg_dmamask = DMA_BIT_MASK(32);
+
+/* OTG gadget device */
+struct platform_device kirkwood_otg = {
+	.name		= "fsl-usb2-udc",
+	.id		= -1,
+	.dev		= {
+		.dma_mask		= &otg_dmamask,
+		.coherent_dma_mask	= DMA_BIT_MASK(32),
+		.platform_data		= &kirkwood_otg_data,
+	},
+	.resource	= kirkwood_usb_resources,
+	.num_resources	= ARRAY_SIZE(kirkwood_usb_resources),
+};
+
+void __init kirkwood_otg_init(void)
+{
+	kirkwood_clk_ctrl |= CGC_USB0;
+	platform_device_register(&kirkwood_otg);
+}
 
 /*****************************************************************************
  * GE00
@@ -568,7 +593,6 @@ void __init kirkwood_uart1_init(void)
 	platform_device_register(&kirkwood_uart1);
 }
 
-
 /*****************************************************************************
  * Cryptographic Engines and Security Accelerator (CESA)
  ****************************************************************************/
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05e8a8a..9bf400c 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -30,6 +30,7 @@ void kirkwood_setup_cpu_mbus(void);
 
 void kirkwood_pcie_id(u32 *dev, u32 *rev);
 
+void kirkwood_otg_init(void);
 void kirkwood_ehci_init(void);
 void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index 591ae9f..aca3f7a 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -156,7 +156,7 @@ config USB_ATMEL_USBA
 
 config USB_GADGET_FSL_USB2
 	boolean "Freescale Highspeed USB DR Peripheral Controller"
-	depends on FSL_SOC || ARCH_MXC
+	depends on FSL_SOC || ARCH_MXC || ARCH_KIRKWOOD
 	select USB_GADGET_DUALSPEED
 	help
 	   Some of Freescale PowerPC processors have a High Speed
-- 
1.7.0.4



From nico at fluxnic.net  Wed Jun  9 13:17:43 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 09 Jun 2010 13:17:43 -0400 (EDT)
Subject: [PATCH] [kirkwood-otg] Leverage the Freescale OTG driver for
	Kirkwood OTG
In-Reply-To: <1276094138-13497-2-git-send-email-jason.mcmullan@netronome.com>
References: <1276094138-13497-1-git-send-email-jason.mcmullan@netronome.com>
	<1276094138-13497-2-git-send-email-jason.mcmullan@netronome.com>
Message-ID: <alpine.LFD.2.00.1006091307321.30664@xanadu.home>

On Wed, 9 Jun 2010, Jason S. McMullan wrote:

> The Freescale USB Gadget driver is based off of the
> same USB OTG core that is used in the Kirkwood.
> 
> NOTE: Your bootloader must ensure that the Kirkwood
>       USB 2.0 Bridge Window registers are set correctly,
>       or the driver will stall on the first DMA.

Could you add the code to sets that up in the kernel instead?  

> @@ -156,7 +156,7 @@ config USB_ATMEL_USBA
>  
>  config USB_GADGET_FSL_USB2
>  	boolean "Freescale Highspeed USB DR Peripheral Controller"
> -	depends on FSL_SOC || ARCH_MXC
> +	depends on FSL_SOC || ARCH_MXC || ARCH_KIRKWOOD
>  	select USB_GADGET_DUALSPEED
>  	help
>  	   Some of Freescale PowerPC processors have a High Speed

Maybe the help text should be extended to mention Kirkwood?


Nicolas


From jgarzik at pobox.com  Wed Jun  9 13:31:23 2010
From: jgarzik at pobox.com (Jeff Garzik)
Date: Wed, 09 Jun 2010 13:31:23 -0400
Subject: [PATCH v2 1/5] libata: pata_samsung: Add Samsung PATA controller
	driver
In-Reply-To: <1275988020-29000-2-git-send-email-kgene.kim@samsung.com>
References: <1275988020-29000-1-git-send-email-kgene.kim@samsung.com>
	<1275988020-29000-2-git-send-email-kgene.kim@samsung.com>
Message-ID: <4C0FCFEB.6030603@pobox.com>

On 06/08/2010 05:06 AM, Kukjin Kim wrote:
> From: Abhilash Kesavan<a.kesavan at samsung.com>
>
> Adds support for the Samsung PATA controller. This driver is based on the
> Libata subsystem and references the earlier patches sent for IDE subsystem.
>
> Signed-off-by: Abhilash Kesavan<a.kesavan at samsung.com>
> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
> ---
>   drivers/ata/Kconfig           |    9 +
>   drivers/ata/Makefile          |    1 +
>   drivers/ata/pata_samsung_cf.c |  608 +++++++++++++++++++++++++++++++++++++++++
>   3 files changed, 618 insertions(+), 0 deletions(-)
>   create mode 100644 drivers/ata/pata_samsung_cf.c

Looks OK to me, minor nits only...



> +#define DRV_NAME "pata_samsung"

this should be "pata_samsung_cf"


> +static void pata_s3c_hwinit(struct s3c_ide_info *info,
> +				struct s3c_ide_platdata *pdata)
> +{
> +	switch (info->cpu_type) {
> +	case TYPE_S3C64XX:
> +		/* Configure as big endian */
> +		pata_s3c_cfg_mode(info->sfr_addr);
> +		pata_s3c_set_endian(info->ide_addr, 1);
> +		pata_s3c_enable(info->ide_addr, 1);
> +		mdelay(100);
> +
> +		/* Remove IRQ Status */
> +		writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
> +		writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
> +	break;
> +
> +	case TYPE_S5PC100:
> +		pata_s3c_cfg_mode(info->sfr_addr);
> +
> +	case TYPE_S5PV210:
> +		/* Configure as little endian */
> +		pata_s3c_set_endian(info->ide_addr, 0);
> +		pata_s3c_enable(info->ide_addr, 1);
> +		mdelay(100);
> +
> +		/* Remove IRQ Status */
> +		writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
> +		writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
> +	break;
> +
> +	default:
> +		BUG();

Use of msleep() is preferred, in cases where you can sleep (such as this)



From jason.mcmullan at netronome.com  Wed Jun  9 14:06:53 2010
From: jason.mcmullan at netronome.com (Jason McMullan)
Date: Wed, 9 Jun 2010 14:06:53 -0400
Subject: [PATCH] [kirkwood-otg] Leverage the Freescale OTG driver for 
	Kirkwood OTG
In-Reply-To: <alpine.LFD.2.00.1006091307321.30664@xanadu.home>
References: <1276094138-13497-1-git-send-email-jason.mcmullan@netronome.com>
	<1276094138-13497-2-git-send-email-jason.mcmullan@netronome.com>
	<alpine.LFD.2.00.1006091307321.30664@xanadu.home>
Message-ID: <AANLkTikVeVBdSfeS_p0k4dRwFopELw2OIXUrS1NjEdt6@mail.gmail.com>

On Wed, Jun 9, 2010 at 1:17 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Wed, 9 Jun 2010, Jason S. McMullan wrote:
>> NOTE: Your bootloader must ensure that the Kirkwood
>> ? ? ? USB 2.0 Bridge Window registers are set correctly,
>> ? ? ? or the driver will stall on the first DMA.
>
> Could you add the code to sets that up in the kernel instead?

Will do.

>> ?config USB_GADGET_FSL_USB2
>
> Maybe the help text should be extended to mention Kirkwood?

Again, good idea, will do.

-- 
Jason S. McMullan
Netronome Systems, Inc.


From nico at fluxnic.net  Wed Jun  9 15:10:16 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 09 Jun 2010 15:10:16 -0400 (EDT)
Subject: [PATCH v2 1/4] ARM: Remove the domain switching on ARMv6k/v7 CPUs
In-Reply-To: <20100602164841.17783.94825.stgit@e102109-lin.cambridge.arm.com>
References: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
	<20100602164841.17783.94825.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <alpine.LFD.2.00.1006091447460.30664@xanadu.home>

Sorry for the delay... I'm just starting to seriously look at this.

On Wed, 2 Jun 2010, Catalin Marinas wrote:

> This patch removes the domain switching functionality via the set_fs and
> __switch_to functions on cores that have a TLS register.
[...]
> The user pages access rights are also modified for kernel read-only
> access rather than read/write so that the copy-on-write mechanism still
> works. CPU_USE_DOMAINS gets disabled only if HAS_TLS_REG is defined
> since writing the TLS value to the high vectors page isn't possible.

I don't like this limitation much.

Since the vector page has to be accessed somehow for FIQs anyway, and 
the current solution for that involves accesses through the direct 
mapping of the vector page, then this patch could be made to work on 
pre-ARMv6 systems too simply by adding the necessary cache ops around 
the TLS and FIQ updates.

Or even better: on those VIVT systems, the domain switching could be 
used _only_ when direct modifications to the vector page is performed.

This way, this patch could get a wider base for test coverage.  And this 
could even remove the need for the uaccess_with_memcpy.c hack at some 
point.


Nicolas


From buytenh at wantstofly.org  Wed Jun  9 15:10:56 2010
From: buytenh at wantstofly.org (Lennert Buytenhek)
Date: Wed, 9 Jun 2010 21:10:56 +0200
Subject: [PATCH 1/2] mv643xx_eth: disable csum offloading if the hw
	limited by max size
In-Reply-To: <FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>
References: <1275827336-31111-1-git-send-email-saeed@marvell.com>
	<20100608170846.GR1743@mail.wantstofly.org>
	<FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>
Message-ID: <20100609191056.GI1743@mail.wantstofly.org>

On Wed, Jun 09, 2010 at 11:21:47AM +0300, Saeed Bishara wrote:

> >> diff --git a/include/linux/mv643xx_eth.h 
> >b/include/linux/mv643xx_eth.h
> >> index cbbbe9b..7402718 100644
> >> --- a/include/linux/mv643xx_eth.h
> >> +++ b/include/linux/mv643xx_eth.h
> >> @@ -19,6 +19,10 @@ struct mv643xx_eth_shared_platform_data {
> >>  	struct mbus_dram_target_info	*dram;
> >>  	struct platform_device	*shared_smi;
> >>  	unsigned int		t_clk;
> >> +	/*
> >> +	 * Max packet size for Tx IP/Layer 4 checksum (0 -> no limit)
> >
> >There's always a limit. :-)  You might as well just fill in the right
> >values for orion5x/kw/dd/loki while you're at it.
>
> Right, kirkwood and dove are limited to 1600, the others to 9*1024. Don't know about loki.

As I know Loki to be able to tx jumbo frames with hw checksum
offload, it is likely 9*1024 also.


From u.kleine-koenig at pengutronix.de  Wed Jun  9 15:17:33 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 9 Jun 2010 21:17:33 +0200
Subject: [PATCH 3/3] imx2_wdt: fix section mismatch
In-Reply-To: <31360d4c97db0e754d15f27567b4592010bdd831.1276081393.git.baruch@tkos.co.il>
References: <cover.1276081393.git.baruch@tkos.co.il>
	<31360d4c97db0e754d15f27567b4592010bdd831.1276081393.git.baruch@tkos.co.il>
Message-ID: <20100609191733.GA6181@pengutronix.de>

On Wed, Jun 09, 2010 at 02:07:02PM +0300, Baruch Siach wrote:
> Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> Cc: Wim Van Sebroeck <wim at iguana.be>
Acked-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

Thanks
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From abhijeet at marvell.com  Wed Jun  9 15:22:26 2010
From: abhijeet at marvell.com (Abhijeet Gole)
Date: Wed, 9 Jun 2010 12:22:26 -0700
Subject: [PATCH 1/2] mv643xx_eth: disable csum offloading if the hw
	limited by max size
In-Reply-To: <20100609191056.GI1743@mail.wantstofly.org>
References: <1275827336-31111-1-git-send-email-saeed@marvell.com>
	<20100608170846.GR1743@mail.wantstofly.org>
	<FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>
	<20100609191056.GI1743@mail.wantstofly.org>
Message-ID: <5FF020A1CFFEEC49BD1E09530C4FF595056D62F9DD@SC-VEXCH1.marvell.com>


Yes, Loki is 9*1024.

-----Original Message-----
From: Lennert Buytenhek [mailto:buytenh at wantstofly.org] 
Sent: Wednesday, June 09, 2010 12:11 PM
To: Saeed Bishara
Cc: linux-net at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Abhijeet Gole
Subject: Re: [PATCH 1/2] mv643xx_eth: disable csum offloading if the hw limited by max size

On Wed, Jun 09, 2010 at 11:21:47AM +0300, Saeed Bishara wrote:

> >> diff --git a/include/linux/mv643xx_eth.h 
> >b/include/linux/mv643xx_eth.h
> >> index cbbbe9b..7402718 100644
> >> --- a/include/linux/mv643xx_eth.h
> >> +++ b/include/linux/mv643xx_eth.h
> >> @@ -19,6 +19,10 @@ struct mv643xx_eth_shared_platform_data {
> >>  	struct mbus_dram_target_info	*dram;
> >>  	struct platform_device	*shared_smi;
> >>  	unsigned int		t_clk;
> >> +	/*
> >> +	 * Max packet size for Tx IP/Layer 4 checksum (0 -> no limit)
> >
> >There's always a limit. :-)  You might as well just fill in the right
> >values for orion5x/kw/dd/loki while you're at it.
>
> Right, kirkwood and dove are limited to 1600, the others to 9*1024. Don't know about loki.

As I know Loki to be able to tx jumbo frames with hw checksum
offload, it is likely 9*1024 also.


From milinevskyy at gmail.com  Wed Jun  9 16:14:39 2010
From: milinevskyy at gmail.com (Dmytro Milinevskyy)
Date: Wed, 09 Jun 2010 23:14:39 +0300
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
Message-ID: <4c0ff6b2.0c3ddf0a.2185.2e09@mx.google.com>

Hi!
This patch adds support for the OpenRD Ultimate machine(could be found at http://www.arm.linux.org.uk/developer/machines/list.php?id=2884)

Besides adding machine description this patch adds correction for PHY address for Ultimate version.

Differences from the previous attempt:
 - Applied suggestion from Lennert Buytenhek to change PHY addresses in instances of mv643xx_eth_platform_data in case of ultimate version.

Regards,

-- Dmytro Milinevskyy


Signed-off-by: Dmytro Milinevskyy <milinevskyy at gmail.com>
---
 arch/arm/mach-kirkwood/Kconfig        |    7 +++++++
 arch/arm/mach-kirkwood/openrd-setup.c |   28 +++++++++++++++++++++++++---
 2 files changed, 32 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 29b2163..110a3b8 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell OpenRD Client Board.
 
+config MACH_OPENRD_ULTIMATE
+	bool "Marvell OpenRD Ultimate Board"
+	select MACH_OPENRD
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell OpenRD Ultimate Board.
+
 config MACH_NETSPACE_V2
 	bool "LaCie Network Space v2 NAS Board"
 	help
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec..81b330d 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-kirkwood/openrd-setup.c
  *
- * Marvell OpenRD (Base|Client) Board Setup
+ * Marvell OpenRD (Base|Client|Ultimate) Board Setup
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
@@ -73,9 +73,16 @@ static void __init openrd_init(void)
 
 	kirkwood_ehci_init();
 
+	if (machine_is_openrd_ultimate()) {
+		openrd_ge00_data.phy = 0;
+		openrd_ge01_data.phy = 1;
+	}
+
 	kirkwood_ge00_init(&openrd_ge00_data);
-	if (machine_is_openrd_client())
+	if (machine_is_openrd_client() ||
+		machine_is_openrd_ultimate())
 		kirkwood_ge01_init(&openrd_ge01_data);
+
 	kirkwood_sata_init(&openrd_sata_data);
 	kirkwood_sdio_init(&openrd_mvsdio_data);
 
@@ -84,7 +91,9 @@ static void __init openrd_init(void)
 
 static int __init openrd_pci_init(void)
 {
-	if (machine_is_openrd_base() || machine_is_openrd_client())
+	if (machine_is_openrd_base() ||
+		machine_is_openrd_client() ||
+		machine_is_openrd_ultimate())
 		kirkwood_pcie_init();
 
 	return 0;
@@ -116,3 +125,16 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
 	.timer		= &kirkwood_timer,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_MACH_OPENRD_ULTIMATE
+MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
+	/* Maintainer: Dhaval Vasa <dhaval.vasa at einfochips.com> */
+	.phys_io	= KIRKWOOD_REGS_PHYS_BASE,
+	.io_pg_offst	= ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+	.boot_params	= 0x00000100,
+	.init_machine	= openrd_init,
+	.map_io		= kirkwood_map_io,
+	.init_irq	= kirkwood_init_irq,
+	.timer		= &kirkwood_timer,
+MACHINE_END
+#endif
-- 
1.7.1



From alex at digriz.org.uk  Wed Jun  9 16:37:20 2010
From: alex at digriz.org.uk (Alexander Clouter)
Date: Wed, 9 Jun 2010 21:37:20 +0100
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
In-Reply-To: <4c0ff6b2.0c3ddf0a.2185.2e09@mx.google.com>
References: <4c0ff6b2.0c3ddf0a.2185.2e09@mx.google.com>
Message-ID: <20100609203720.GK7660@chipmunk>

Hi,

* Dmytro Milinevskyy <milinevskyy at gmail.com> [2010-06-09 23:14:39+0300]:
>
> This patch adds support for the OpenRD Ultimate machine(could be found 
> at http://www.arm.linux.org.uk/developer/machines/list.php?id=2884)
> 
> Besides adding machine description this patch adds correction for PHY 
> address for Ultimate version.
> 
> Differences from the previous attempt:
>  - Applied suggestion from Lennert Buytenhek to change PHY addresses 
>  in instances of mv643xx_eth_platform_data in case of ultimate 
>  version.
> 
> Signed-off-by: Dmytro Milinevskyy <milinevskyy at gmail.com>
> ---
>  
> +	if (machine_is_openrd_ultimate()) {
> +		openrd_ge00_data.phy = 0;
> +		openrd_ge01_data.phy = 1;
> +	}
> +
>
Does this even work?  Surely you mean the following instead:
----
if (machine_is_openrd_ultimate()) {
	openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
	openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
}
----

>  	kirkwood_ge00_init(&openrd_ge00_data);
> -	if (machine_is_openrd_client())
> +	if (machine_is_openrd_client() ||      \__same line
> +		machine_is_openrd_ultimate())  /
>  		kirkwood_ge01_init(&openrd_ge01_data);
> +  <------- REMOVE
>  	kirkwood_sata_init(&openrd_sata_data);
>  	kirkwood_sdio_init(&openrd_mvsdio_data);
>  
As that 'if()' clause is still less than 77 chars wide:
----
kirkwood_ge00_init(&openrd_ge00_data);
if (machine_is_openrd_client() || machine_is_openrd_ultimate())
	kirkwood_ge01_init(&openrd_ge01_data);
kirkwood_sata_init(&openrd_sata_data);
kirkwood_sdio_init(&openrd_mvsdio_data);
----

Cheers

-- 
Alexander Clouter
.sigmonster says: People respond to people who respond.


From buytenh at wantstofly.org  Wed Jun  9 16:42:57 2010
From: buytenh at wantstofly.org (Lennert Buytenhek)
Date: Wed, 9 Jun 2010 22:42:57 +0200
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
In-Reply-To: <20100609203929.GL7660@chipmunk>
References: <4c0ff6b2.0c3ddf0a.2185.2e09@mx.google.com>
	<20100609203720.GK7660@chipmunk> <20100609203929.GL7660@chipmunk>
Message-ID: <20100609204257.GJ1743@mail.wantstofly.org>

On Wed, Jun 09, 2010 at 09:39:29PM +0100, Alexander Clouter wrote:

> > >  	kirkwood_ge00_init(&openrd_ge00_data);
> > > -	if (machine_is_openrd_client())
> > > +	if (machine_is_openrd_client() ||      \__same line
> > > +		machine_is_openrd_ultimate())  /
> > >  		kirkwood_ge01_init(&openrd_ge01_data);
> > > +  <------- REMOVE
> > >  	kirkwood_sata_init(&openrd_sata_data);
> > >  	kirkwood_sdio_init(&openrd_mvsdio_data);
> > >  
> > As that 'if()' clause is still less than 77 chars wide:
> > ----
> > kirkwood_ge00_init(&openrd_ge00_data);
> > if (machine_is_openrd_client() || machine_is_openrd_ultimate())
> > 	kirkwood_ge01_init(&openrd_ge01_data);
> > kirkwood_sata_init(&openrd_sata_data);
> > kirkwood_sdio_init(&openrd_mvsdio_data);
> > ----
> 
> Better still, just make this 'if(!machine_is_openrd_base())'.

That form is more error prone when someone adds the OpenRD-SuperDuper,
though.


From alex at digriz.org.uk  Wed Jun  9 16:39:29 2010
From: alex at digriz.org.uk (Alexander Clouter)
Date: Wed, 9 Jun 2010 21:39:29 +0100
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
In-Reply-To: <20100609203720.GK7660@chipmunk>
References: <4c0ff6b2.0c3ddf0a.2185.2e09@mx.google.com>
	<20100609203720.GK7660@chipmunk>
Message-ID: <20100609203929.GL7660@chipmunk>

Hi,

* Alexander Clouter <alex at digriz.org.uk> [2010-06-09 21:37:20+0100]:
>
> >  	kirkwood_ge00_init(&openrd_ge00_data);
> > -	if (machine_is_openrd_client())
> > +	if (machine_is_openrd_client() ||      \__same line
> > +		machine_is_openrd_ultimate())  /
> >  		kirkwood_ge01_init(&openrd_ge01_data);
> > +  <------- REMOVE
> >  	kirkwood_sata_init(&openrd_sata_data);
> >  	kirkwood_sdio_init(&openrd_mvsdio_data);
> >  
> As that 'if()' clause is still less than 77 chars wide:
> ----
> kirkwood_ge00_init(&openrd_ge00_data);
> if (machine_is_openrd_client() || machine_is_openrd_ultimate())
> 	kirkwood_ge01_init(&openrd_ge01_data);
> kirkwood_sata_init(&openrd_sata_data);
> kirkwood_sdio_init(&openrd_mvsdio_data);
> ----
> 
Better still, just make this 'if(!machine_is_openrd_base())'.

Cheers

-- 
Alexander Clouter
.sigmonster says: What this country needs is a good five cent microcomputer.


From hartleys at visionengravers.com  Wed Jun  9 16:49:18 2010
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 9 Jun 2010 15:49:18 -0500
Subject: [PATCH v3] ep93xx: move physmap flash registration into core.c
In-Reply-To: <0D753D10438DA54287A00B0270842697636F3238EC@AUSP01VMBX24.collaborationhost.net>
References: <AcrcNxXi/1OpCfUUTQ2+Xkz9P4CSMQ==>
	<0D753D10438DA54287A00B0270842697636D62B066@AUSP01VMBX24.collaborationhost.net>
	<t2h56d259a01004200333gfc5b6307vb34c20e60db28aa1@mail.gmail.com>
	<0D753D10438DA54287A00B0270842697636F3238EC@AUSP01VMBX24.collaborationhost.net>
Message-ID: <0D753D10438DA54287A00B02708426976370F421F7@AUSP01VMBX24.collaborationhost.net>

Create a core.c __init function to handle the physmap flash
registration for all the ep93xx platforms.  Also, modify all
the ep93xx platforms to use this new function.

This simplifies all the ep93xx platform init code and removes
all the static variables that would exist in a unified kernel
supporting multiple ep93xx platforms.

Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
Cc: Ryan Mallon <ryan at bluewatersys.com>
Acked-by: Martin Guy <martinwguy at gmail.com>

---

v3 - Rebased to 2.6.35-rc2

 arch/arm/mach-ep93xx/adssphere.c             |   24 +---------------
 arch/arm/mach-ep93xx/core.c                  |   38 ++++++++++++++++++++++++++
 arch/arm/mach-ep93xx/edb93xx.c               |   31 +-------------------
 arch/arm/mach-ep93xx/gesbc9312.c             |   24 +---------------
 arch/arm/mach-ep93xx/include/mach/platform.h |    3 ++
 arch/arm/mach-ep93xx/micro9.c                |   37 ++++++-------------------
 arch/arm/mach-ep93xx/simone.c                |   24 +---------------
 arch/arm/mach-ep93xx/ts72xx.c                |   27 +++---------------
 8 files changed, 59 insertions(+), 149 deletions(-)

diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 3a1a855..f744f67 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -13,7 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 
 #include <mach/hardware.h>
 
@@ -21,26 +20,6 @@
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data adssphere_flash_data = {
-	.width		= 4,
-};
-
-static struct resource adssphere_flash_resource = {
-	.start		= EP93XX_CS6_PHYS_BASE,
-	.end		= EP93XX_CS6_PHYS_BASE + SZ_32M - 1,
-	.flags		= IORESOURCE_MEM,
-};
-
-static struct platform_device adssphere_flash = {
-	.name		= "physmap-flash",
-	.id		= 0,
-	.dev		= {
-		.platform_data	= &adssphere_flash_data,
-	},
-	.num_resources	= 1,
-	.resource	= &adssphere_flash_resource,
-};
-
 static struct ep93xx_eth_data __initdata adssphere_eth_data = {
 	.phy_id		= 1,
 };
@@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata adssphere_eth_data = {
 static void __init adssphere_init_machine(void)
 {
 	ep93xx_init_devices();
-	platform_device_register(&adssphere_flash);
-
+	ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
 	ep93xx_register_eth(&adssphere_eth_data, 1);
 }
 
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 9092677..b87c85f 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -29,6 +29,7 @@
 #include <linux/termios.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
+#include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
 #include <linux/spi/spi.h>
@@ -348,6 +349,43 @@ static struct platform_device ep93xx_ohci_device = {
 
 
 /*************************************************************************
+ * EP93xx physmap'ed flash
+ *************************************************************************/
+static struct physmap_flash_data ep93xx_flash_data;
+
+static struct resource ep93xx_flash_resource = {
+	.flags		= IORESOURCE_MEM,
+};
+
+static struct platform_device ep93xx_flash = {
+	.name		= "physmap-flash",
+	.id		= 0,
+	.dev		= {
+		.platform_data	= &ep93xx_flash_data,
+	},
+	.num_resources	= 1,
+	.resource	= &ep93xx_flash_resource,
+};
+
+/**
+ * ep93xx_register_flash() - Register the external flash device.
+ * @width:	bank width in octets
+ * @start:	resource start address
+ * @size:	resource size
+ */
+void __init ep93xx_register_flash(unsigned int width,
+				  resource_size_t start, resource_size_t size)
+{
+	ep93xx_flash_data.width		= width;
+
+	ep93xx_flash_resource.start	= start;
+	ep93xx_flash_resource.end	= start + size - 1;
+
+	platform_device_register(&ep93xx_flash);
+}
+
+
+/*************************************************************************
  * EP93xx ethernet peripheral handling
  *************************************************************************/
 static struct ep93xx_eth_data ep93xx_eth_data;
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 3884182..c2ce903 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -27,7 +27,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
@@ -38,39 +37,13 @@
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data edb93xx_flash_data;
-
-static struct resource edb93xx_flash_resource = {
-	.flags		= IORESOURCE_MEM,
-};
-
-static struct platform_device edb93xx_flash = {
-	.name		= "physmap-flash",
-	.id		= 0,
-	.dev		= {
-		.platform_data	= &edb93xx_flash_data,
-	},
-	.num_resources	= 1,
-	.resource	= &edb93xx_flash_resource,
-};
-
-static void __init __edb93xx_register_flash(unsigned int width,
-			resource_size_t start, resource_size_t size)
-{
-	edb93xx_flash_data.width	= width;
-	edb93xx_flash_resource.start	= start;
-	edb93xx_flash_resource.end	= start + size - 1;
-
-	platform_device_register(&edb93xx_flash);
-}
-
 static void __init edb93xx_register_flash(void)
 {
 	if (machine_is_edb9307() || machine_is_edb9312() ||
 	    machine_is_edb9315()) {
-		__edb93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
+		ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
 	} else {
-		__edb93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
+		ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
 	}
 }
 
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index a809618..d97168c 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -13,7 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 
 #include <mach/hardware.h>
 
@@ -21,26 +20,6 @@
 #include <asm/mach/arch.h>
 
 
-static struct physmap_flash_data gesbc9312_flash_data = {
-	.width		= 4,
-};
-
-static struct resource gesbc9312_flash_resource = {
-	.start		= EP93XX_CS6_PHYS_BASE,
-	.end		= EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
-	.flags		= IORESOURCE_MEM,
-};
-
-static struct platform_device gesbc9312_flash = {
-	.name		= "physmap-flash",
-	.id		= 0,
-	.dev		= {
-		.platform_data	= &gesbc9312_flash_data,
-	},
-	.num_resources	= 1,
-	.resource	= &gesbc9312_flash_resource,
-};
-
 static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
 	.phy_id		= 1,
 };
@@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
 static void __init gesbc9312_init_machine(void)
 {
 	ep93xx_init_devices();
-	platform_device_register(&gesbc9312_flash);
-
+	ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_8M);
 	ep93xx_register_eth(&gesbc9312_eth_data, 0);
 }
 
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 9a4413d..a6c0917 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -43,6 +43,9 @@ static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
 
 unsigned int ep93xx_chip_revision(void);
 
+void ep93xx_register_flash(unsigned int width,
+			   resource_size_t start, resource_size_t size);
+
 void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
 void ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
 			 struct i2c_board_info *devices, int num);
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 1cc911b..2ba7763 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -14,7 +14,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -31,31 +30,6 @@
  * Micro9-Lite uses a separate MTD map driver for flash support
  * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1
  *************************************************************************/
-static struct physmap_flash_data micro9_flash_data;
-
-static struct resource micro9_flash_resource = {
-	.start		= EP93XX_CS1_PHYS_BASE,
-	.end		= EP93XX_CS1_PHYS_BASE + SZ_64M - 1,
-	.flags		= IORESOURCE_MEM,
-};
-
-static struct platform_device micro9_flash = {
-	.name		= "physmap-flash",
-	.id		= 0,
-	.dev		= {
-		.platform_data	= &micro9_flash_data,
-	},
-	.num_resources	= 1,
-	.resource	= &micro9_flash_resource,
-};
-
-static void __init __micro9_register_flash(unsigned int width)
-{
-	micro9_flash_data.width = width;
-
-	platform_device_register(&micro9_flash);
-}
-
 static unsigned int __init micro9_detect_bootwidth(void)
 {
 	u32 v;
@@ -70,10 +44,17 @@ static unsigned int __init micro9_detect_bootwidth(void)
 
 static void __init micro9_register_flash(void)
 {
+	unsigned int width;
+
 	if (machine_is_micro9())
-		__micro9_register_flash(4);
+		width = 4;
 	else if (machine_is_micro9m() || machine_is_micro9s())
-		__micro9_register_flash(micro9_detect_bootwidth());
+		width = micro9_detect_bootwidth();
+	else
+		width = 0;
+
+	if (width)
+		ep93xx_register_flash(width, EP93XX_CS1_PHYS_BASE, SZ_64M);
 }
 
 
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 388aec9..5dded58 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -18,7 +18,6 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
@@ -29,26 +28,6 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 
-static struct physmap_flash_data simone_flash_data = {
-	.width		= 2,
-};
-
-static struct resource simone_flash_resource = {
-	.start		= EP93XX_CS6_PHYS_BASE,
-	.end		= EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
-	.flags		= IORESOURCE_MEM,
-};
-
-static struct platform_device simone_flash = {
-	.name		= "physmap-flash",
-	.id		= 0,
-	.num_resources	= 1,
-	.resource	= &simone_flash_resource,
-	.dev = {
-		.platform_data	= &simone_flash_data,
-	},
-};
-
 static struct ep93xx_eth_data __initdata simone_eth_data = {
 	.phy_id		= 1,
 };
@@ -77,8 +56,7 @@ static struct i2c_board_info __initdata simone_i2c_board_info[] = {
 static void __init simone_init_machine(void)
 {
 	ep93xx_init_devices();
-
-	platform_device_register(&simone_flash);
+	ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M);
 	ep93xx_register_eth(&simone_eth_data, 1);
 	ep93xx_register_fb(&simone_fb_info);
 	ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index ae7319e..93aeab8 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -17,7 +17,6 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/m48t86.h>
-#include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 
@@ -173,31 +172,13 @@ static struct platform_device ts72xx_nand_flash = {
 };
 
 
-/*************************************************************************
- * NOR flash (TS-7200 only)
- *************************************************************************/
-static struct physmap_flash_data ts72xx_nor_data = {
-	.width		= 2,
-};
-
-static struct resource ts72xx_nor_resource = {
-	.start		= EP93XX_CS6_PHYS_BASE,
-	.end		= EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
-	.flags		= IORESOURCE_MEM,
-};
-
-static struct platform_device ts72xx_nor_flash = {
-	.name			= "physmap-flash",
-	.id			= 0,
-	.dev.platform_data	= &ts72xx_nor_data,
-	.resource		= &ts72xx_nor_resource,
-	.num_resources		= 1,
-};
-
 static void __init ts72xx_register_flash(void)
 {
+	/*
+	 * TS7200 has NOR flash all other TS72xx board have NAND flash.
+	 */
 	if (board_is_ts7200()) {
-		platform_device_register(&ts72xx_nor_flash);
+		ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
 	} else {
 		resource_size_t start;
 




From ryan at bluewatersys.com  Wed Jun  9 16:59:07 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Thu, 10 Jun 2010 08:59:07 +1200
Subject: [PATCH v3] ep93xx: move physmap flash registration into core.c
In-Reply-To: <0D753D10438DA54287A00B02708426976370F421F7@AUSP01VMBX24.collaborationhost.net>
References: <AcrcNxXi/1OpCfUUTQ2+Xkz9P4CSMQ==>	<0D753D10438DA54287A00B0270842697636D62B066@AUSP01VMBX24.collaborationhost.net>	<t2h56d259a01004200333gfc5b6307vb34c20e60db28aa1@mail.gmail.com>
	<0D753D10438DA54287A00B0270842697636F3238EC@AUSP01VMBX24.collaborationhost.net>
	<0D753D10438DA54287A00B02708426976370F421F7@AUSP01VMBX24.collaborationhost.net>
Message-ID: <4C10009B.2010607@bluewatersys.com>

H Hartley Sweeten wrote:
> Create a core.c __init function to handle the physmap flash
> registration for all the ep93xx platforms.  Also, modify all
> the ep93xx platforms to use this new function.
> 
> This simplifies all the ep93xx platform init code and removes
> all the static variables that would exist in a unified kernel
> supporting multiple ep93xx platforms.

Looks fine. Not sure I understand the second part about the unified
kernel though. Can't we already build all ep93xx boards (at least those
at the same phys offset) into one kernel?

~Ryan

> Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <ryan at bluewatersys.com>
> Acked-by: Martin Guy <martinwguy at gmail.com>
> 
> ---
> 
> v3 - Rebased to 2.6.35-rc2
> 
>  arch/arm/mach-ep93xx/adssphere.c             |   24 +---------------
>  arch/arm/mach-ep93xx/core.c                  |   38 ++++++++++++++++++++++++++
>  arch/arm/mach-ep93xx/edb93xx.c               |   31 +-------------------
>  arch/arm/mach-ep93xx/gesbc9312.c             |   24 +---------------
>  arch/arm/mach-ep93xx/include/mach/platform.h |    3 ++
>  arch/arm/mach-ep93xx/micro9.c                |   37 ++++++-------------------
>  arch/arm/mach-ep93xx/simone.c                |   24 +---------------
>  arch/arm/mach-ep93xx/ts72xx.c                |   27 +++---------------
>  8 files changed, 59 insertions(+), 149 deletions(-)
> 
> diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
> index 3a1a855..f744f67 100644
> --- a/arch/arm/mach-ep93xx/adssphere.c
> +++ b/arch/arm/mach-ep93xx/adssphere.c
> @@ -13,7 +13,6 @@
>  #include <linux/kernel.h>
>  #include <linux/init.h>
>  #include <linux/platform_device.h>
> -#include <linux/mtd/physmap.h>
>  
>  #include <mach/hardware.h>
>  
> @@ -21,26 +20,6 @@
>  #include <asm/mach/arch.h>
>  
>  
> -static struct physmap_flash_data adssphere_flash_data = {
> -	.width		= 4,
> -};
> -
> -static struct resource adssphere_flash_resource = {
> -	.start		= EP93XX_CS6_PHYS_BASE,
> -	.end		= EP93XX_CS6_PHYS_BASE + SZ_32M - 1,
> -	.flags		= IORESOURCE_MEM,
> -};
> -
> -static struct platform_device adssphere_flash = {
> -	.name		= "physmap-flash",
> -	.id		= 0,
> -	.dev		= {
> -		.platform_data	= &adssphere_flash_data,
> -	},
> -	.num_resources	= 1,
> -	.resource	= &adssphere_flash_resource,
> -};
> -
>  static struct ep93xx_eth_data __initdata adssphere_eth_data = {
>  	.phy_id		= 1,
>  };
> @@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata adssphere_eth_data = {
>  static void __init adssphere_init_machine(void)
>  {
>  	ep93xx_init_devices();
> -	platform_device_register(&adssphere_flash);
> -
> +	ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
>  	ep93xx_register_eth(&adssphere_eth_data, 1);
>  }
>  
> diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
> index 9092677..b87c85f 100644
> --- a/arch/arm/mach-ep93xx/core.c
> +++ b/arch/arm/mach-ep93xx/core.c
> @@ -29,6 +29,7 @@
>  #include <linux/termios.h>
>  #include <linux/amba/bus.h>
>  #include <linux/amba/serial.h>
> +#include <linux/mtd/physmap.h>
>  #include <linux/i2c.h>
>  #include <linux/i2c-gpio.h>
>  #include <linux/spi/spi.h>
> @@ -348,6 +349,43 @@ static struct platform_device ep93xx_ohci_device = {
>  
>  
>  /*************************************************************************
> + * EP93xx physmap'ed flash
> + *************************************************************************/
> +static struct physmap_flash_data ep93xx_flash_data;
> +
> +static struct resource ep93xx_flash_resource = {
> +	.flags		= IORESOURCE_MEM,
> +};
> +
> +static struct platform_device ep93xx_flash = {
> +	.name		= "physmap-flash",
> +	.id		= 0,
> +	.dev		= {
> +		.platform_data	= &ep93xx_flash_data,
> +	},
> +	.num_resources	= 1,
> +	.resource	= &ep93xx_flash_resource,
> +};
> +
> +/**
> + * ep93xx_register_flash() - Register the external flash device.
> + * @width:	bank width in octets
> + * @start:	resource start address
> + * @size:	resource size
> + */
> +void __init ep93xx_register_flash(unsigned int width,
> +				  resource_size_t start, resource_size_t size)
> +{
> +	ep93xx_flash_data.width		= width;
> +
> +	ep93xx_flash_resource.start	= start;
> +	ep93xx_flash_resource.end	= start + size - 1;
> +
> +	platform_device_register(&ep93xx_flash);
> +}
> +
> +
> +/*************************************************************************
>   * EP93xx ethernet peripheral handling
>   *************************************************************************/
>  static struct ep93xx_eth_data ep93xx_eth_data;
> diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
> index 3884182..c2ce903 100644
> --- a/arch/arm/mach-ep93xx/edb93xx.c
> +++ b/arch/arm/mach-ep93xx/edb93xx.c
> @@ -27,7 +27,6 @@
>  #include <linux/kernel.h>
>  #include <linux/init.h>
>  #include <linux/platform_device.h>
> -#include <linux/mtd/physmap.h>
>  #include <linux/gpio.h>
>  #include <linux/i2c.h>
>  #include <linux/i2c-gpio.h>
> @@ -38,39 +37,13 @@
>  #include <asm/mach/arch.h>
>  
>  
> -static struct physmap_flash_data edb93xx_flash_data;
> -
> -static struct resource edb93xx_flash_resource = {
> -	.flags		= IORESOURCE_MEM,
> -};
> -
> -static struct platform_device edb93xx_flash = {
> -	.name		= "physmap-flash",
> -	.id		= 0,
> -	.dev		= {
> -		.platform_data	= &edb93xx_flash_data,
> -	},
> -	.num_resources	= 1,
> -	.resource	= &edb93xx_flash_resource,
> -};
> -
> -static void __init __edb93xx_register_flash(unsigned int width,
> -			resource_size_t start, resource_size_t size)
> -{
> -	edb93xx_flash_data.width	= width;
> -	edb93xx_flash_resource.start	= start;
> -	edb93xx_flash_resource.end	= start + size - 1;
> -
> -	platform_device_register(&edb93xx_flash);
> -}
> -
>  static void __init edb93xx_register_flash(void)
>  {
>  	if (machine_is_edb9307() || machine_is_edb9312() ||
>  	    machine_is_edb9315()) {
> -		__edb93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
> +		ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_32M);
>  	} else {
> -		__edb93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
> +		ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
>  	}
>  }
>  
> diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
> index a809618..d97168c 100644
> --- a/arch/arm/mach-ep93xx/gesbc9312.c
> +++ b/arch/arm/mach-ep93xx/gesbc9312.c
> @@ -13,7 +13,6 @@
>  #include <linux/kernel.h>
>  #include <linux/init.h>
>  #include <linux/platform_device.h>
> -#include <linux/mtd/physmap.h>
>  
>  #include <mach/hardware.h>
>  
> @@ -21,26 +20,6 @@
>  #include <asm/mach/arch.h>
>  
>  
> -static struct physmap_flash_data gesbc9312_flash_data = {
> -	.width		= 4,
> -};
> -
> -static struct resource gesbc9312_flash_resource = {
> -	.start		= EP93XX_CS6_PHYS_BASE,
> -	.end		= EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
> -	.flags		= IORESOURCE_MEM,
> -};
> -
> -static struct platform_device gesbc9312_flash = {
> -	.name		= "physmap-flash",
> -	.id		= 0,
> -	.dev		= {
> -		.platform_data	= &gesbc9312_flash_data,
> -	},
> -	.num_resources	= 1,
> -	.resource	= &gesbc9312_flash_resource,
> -};
> -
>  static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
>  	.phy_id		= 1,
>  };
> @@ -48,8 +27,7 @@ static struct ep93xx_eth_data __initdata gesbc9312_eth_data = {
>  static void __init gesbc9312_init_machine(void)
>  {
>  	ep93xx_init_devices();
> -	platform_device_register(&gesbc9312_flash);
> -
> +	ep93xx_register_flash(4, EP93XX_CS6_PHYS_BASE, SZ_8M);
>  	ep93xx_register_eth(&gesbc9312_eth_data, 0);
>  }
>  
> diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
> index 9a4413d..a6c0917 100644
> --- a/arch/arm/mach-ep93xx/include/mach/platform.h
> +++ b/arch/arm/mach-ep93xx/include/mach/platform.h
> @@ -43,6 +43,9 @@ static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
>  
>  unsigned int ep93xx_chip_revision(void);
>  
> +void ep93xx_register_flash(unsigned int width,
> +			   resource_size_t start, resource_size_t size);
> +
>  void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
>  void ep93xx_register_i2c(struct i2c_gpio_platform_data *data,
>  			 struct i2c_board_info *devices, int num);
> diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
> index 1cc911b..2ba7763 100644
> --- a/arch/arm/mach-ep93xx/micro9.c
> +++ b/arch/arm/mach-ep93xx/micro9.c
> @@ -14,7 +14,6 @@
>  #include <linux/kernel.h>
>  #include <linux/init.h>
>  #include <linux/platform_device.h>
> -#include <linux/mtd/physmap.h>
>  #include <linux/io.h>
>  
>  #include <mach/hardware.h>
> @@ -31,31 +30,6 @@
>   * Micro9-Lite uses a separate MTD map driver for flash support
>   * Micro9-Slim has up to 64MB of either 32-bit or 16-bit flash on CS1
>   *************************************************************************/
> -static struct physmap_flash_data micro9_flash_data;
> -
> -static struct resource micro9_flash_resource = {
> -	.start		= EP93XX_CS1_PHYS_BASE,
> -	.end		= EP93XX_CS1_PHYS_BASE + SZ_64M - 1,
> -	.flags		= IORESOURCE_MEM,
> -};
> -
> -static struct platform_device micro9_flash = {
> -	.name		= "physmap-flash",
> -	.id		= 0,
> -	.dev		= {
> -		.platform_data	= &micro9_flash_data,
> -	},
> -	.num_resources	= 1,
> -	.resource	= &micro9_flash_resource,
> -};
> -
> -static void __init __micro9_register_flash(unsigned int width)
> -{
> -	micro9_flash_data.width = width;
> -
> -	platform_device_register(&micro9_flash);
> -}
> -
>  static unsigned int __init micro9_detect_bootwidth(void)
>  {
>  	u32 v;
> @@ -70,10 +44,17 @@ static unsigned int __init micro9_detect_bootwidth(void)
>  
>  static void __init micro9_register_flash(void)
>  {
> +	unsigned int width;
> +
>  	if (machine_is_micro9())
> -		__micro9_register_flash(4);
> +		width = 4;
>  	else if (machine_is_micro9m() || machine_is_micro9s())
> -		__micro9_register_flash(micro9_detect_bootwidth());
> +		width = micro9_detect_bootwidth();
> +	else
> +		width = 0;
> +
> +	if (width)
> +		ep93xx_register_flash(width, EP93XX_CS1_PHYS_BASE, SZ_64M);
>  }
>  
>  
> diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
> index 388aec9..5dded58 100644
> --- a/arch/arm/mach-ep93xx/simone.c
> +++ b/arch/arm/mach-ep93xx/simone.c
> @@ -18,7 +18,6 @@
>  #include <linux/kernel.h>
>  #include <linux/init.h>
>  #include <linux/platform_device.h>
> -#include <linux/mtd/physmap.h>
>  #include <linux/gpio.h>
>  #include <linux/i2c.h>
>  #include <linux/i2c-gpio.h>
> @@ -29,26 +28,6 @@
>  #include <asm/mach-types.h>
>  #include <asm/mach/arch.h>
>  
> -static struct physmap_flash_data simone_flash_data = {
> -	.width		= 2,
> -};
> -
> -static struct resource simone_flash_resource = {
> -	.start		= EP93XX_CS6_PHYS_BASE,
> -	.end		= EP93XX_CS6_PHYS_BASE + SZ_8M - 1,
> -	.flags		= IORESOURCE_MEM,
> -};
> -
> -static struct platform_device simone_flash = {
> -	.name		= "physmap-flash",
> -	.id		= 0,
> -	.num_resources	= 1,
> -	.resource	= &simone_flash_resource,
> -	.dev = {
> -		.platform_data	= &simone_flash_data,
> -	},
> -};
> -
>  static struct ep93xx_eth_data __initdata simone_eth_data = {
>  	.phy_id		= 1,
>  };
> @@ -77,8 +56,7 @@ static struct i2c_board_info __initdata simone_i2c_board_info[] = {
>  static void __init simone_init_machine(void)
>  {
>  	ep93xx_init_devices();
> -
> -	platform_device_register(&simone_flash);
> +	ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_8M);
>  	ep93xx_register_eth(&simone_eth_data, 1);
>  	ep93xx_register_fb(&simone_fb_info);
>  	ep93xx_register_i2c(&simone_i2c_gpio_data, simone_i2c_board_info,
> diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
> index ae7319e..93aeab8 100644
> --- a/arch/arm/mach-ep93xx/ts72xx.c
> +++ b/arch/arm/mach-ep93xx/ts72xx.c
> @@ -17,7 +17,6 @@
>  #include <linux/platform_device.h>
>  #include <linux/io.h>
>  #include <linux/m48t86.h>
> -#include <linux/mtd/physmap.h>
>  #include <linux/mtd/nand.h>
>  #include <linux/mtd/partitions.h>
>  
> @@ -173,31 +172,13 @@ static struct platform_device ts72xx_nand_flash = {
>  };
>  
>  
> -/*************************************************************************
> - * NOR flash (TS-7200 only)
> - *************************************************************************/
> -static struct physmap_flash_data ts72xx_nor_data = {
> -	.width		= 2,
> -};
> -
> -static struct resource ts72xx_nor_resource = {
> -	.start		= EP93XX_CS6_PHYS_BASE,
> -	.end		= EP93XX_CS6_PHYS_BASE + SZ_16M - 1,
> -	.flags		= IORESOURCE_MEM,
> -};
> -
> -static struct platform_device ts72xx_nor_flash = {
> -	.name			= "physmap-flash",
> -	.id			= 0,
> -	.dev.platform_data	= &ts72xx_nor_data,
> -	.resource		= &ts72xx_nor_resource,
> -	.num_resources		= 1,
> -};
> -
>  static void __init ts72xx_register_flash(void)
>  {
> +	/*
> +	 * TS7200 has NOR flash all other TS72xx board have NAND flash.
> +	 */
>  	if (board_is_ts7200()) {
> -		platform_device_register(&ts72xx_nor_flash);
> +		ep93xx_register_flash(2, EP93XX_CS6_PHYS_BASE, SZ_16M);
>  	} else {
>  		resource_size_t start;
>  
> 
> 


-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From hartleys at visionengravers.com  Wed Jun  9 17:10:18 2010
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 9 Jun 2010 16:10:18 -0500
Subject: [PATCH v3] ep93xx: move physmap flash registration into core.c
In-Reply-To: <4C10009B.2010607@bluewatersys.com>
References: <AcrcNxXi/1OpCfUUTQ2+Xkz9P4CSMQ==>
	<0D753D10438DA54287A00B0270842697636D62B066@AUSP01VMBX24.collaborationhost.net>
	<t2h56d259a01004200333gfc5b6307vb34c20e60db28aa1@mail.gmail.com>
	<0D753D10438DA54287A00B0270842697636F3238EC@AUSP01VMBX24.collaborationhost.net>
	<0D753D10438DA54287A00B02708426976370F421F7@AUSP01VMBX24.collaborationhost.net>
	<4C10009B.2010607@bluewatersys.com>
Message-ID: <0D753D10438DA54287A00B02708426976370F422A7@AUSP01VMBX24.collaborationhost.net>

On Wednesday, June 09, 2010 1:59 PM, Ryan Mallon wrote:
> H Hartley Sweeten wrote:
>> Create a core.c __init function to handle the physmap flash
>> registration for all the ep93xx platforms.  Also, modify all
>> the ep93xx platforms to use this new function.
>> 
>> This simplifies all the ep93xx platform init code and removes
>> all the static variables that would exist in a unified kernel
>> supporting multiple ep93xx platforms.
>
> Looks fine. Not sure I understand the second part about the unified
> kernel though. Can't we already build all ep93xx boards (at least those
> at the same phys offset) into one kernel?

Yes, we already build a unified kernel for boards with the same phys
offset.  But with the current code each platform has a private static
Resource and platform device for the flash.  Since this data is not
tagged as __initdata it just takes up space after initialization.  If
a working runtime PHYS_OFFSET patch is ever worked out this static
data will increase for each ep93xx platform added.

Maybe "unified" is not the right term...

Regards,
Hartley


From ryan at bluewatersys.com  Wed Jun  9 17:34:04 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Thu, 10 Jun 2010 09:34:04 +1200
Subject: [PATCH v3] ep93xx: move physmap flash registration into core.c
In-Reply-To: <0D753D10438DA54287A00B02708426976370F422A7@AUSP01VMBX24.collaborationhost.net>
References: <AcrcNxXi/1OpCfUUTQ2+Xkz9P4CSMQ==>	<0D753D10438DA54287A00B0270842697636D62B066@AUSP01VMBX24.collaborationhost.net>	<t2h56d259a01004200333gfc5b6307vb34c20e60db28aa1@mail.gmail.com>
	<0D753D10438DA54287A00B0270842697636F3238EC@AUSP01VMBX24.collaborationhost.net>
	<0D753D10438DA54287A00B02708426976370F421F7@AUSP01VMBX24.collaborationhost.net>
	<4C10009B.2010607@bluewatersys.com>
	<0D753D10438DA54287A00B02708426976370F422A7@AUSP01VMBX24.collaborationhost.net>
Message-ID: <4C1008CC.2000201@bluewatersys.com>

H Hartley Sweeten wrote:
> On Wednesday, June 09, 2010 1:59 PM, Ryan Mallon wrote:
>> H Hartley Sweeten wrote:
>>> Create a core.c __init function to handle the physmap flash
>>> registration for all the ep93xx platforms.  Also, modify all
>>> the ep93xx platforms to use this new function.
>>>
>>> This simplifies all the ep93xx platform init code and removes
>>> all the static variables that would exist in a unified kernel
>>> supporting multiple ep93xx platforms.
>> Looks fine. Not sure I understand the second part about the unified
>> kernel though. Can't we already build all ep93xx boards (at least those
>> at the same phys offset) into one kernel?
> 
> Yes, we already build a unified kernel for boards with the same phys
> offset.  But with the current code each platform has a private static
> Resource and platform device for the flash.  Since this data is not
> tagged as __initdata it just takes up space after initialization.  If
> a working runtime PHYS_OFFSET patch is ever worked out this static
> data will increase for each ep93xx platform added.

Ah, that makes sense. Just say that it reduces the size of the kernel
when including multiple ep93xx boards.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From hartleys at visionengravers.com  Wed Jun  9 17:39:03 2010
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Wed, 9 Jun 2010 16:39:03 -0500
Subject: [PATCH v3] ep93xx: move physmap flash registration into core.c
In-Reply-To: <4C1008CC.2000201@bluewatersys.com>
References: <AcrcNxXi/1OpCfUUTQ2+Xkz9P4CSMQ==>
	<0D753D10438DA54287A00B0270842697636D62B066@AUSP01VMBX24.collaborationhost.net>
	<t2h56d259a01004200333gfc5b6307vb34c20e60db28aa1@mail.gmail.com>
	<0D753D10438DA54287A00B0270842697636F3238EC@AUSP01VMBX24.collaborationhost.net>
	<0D753D10438DA54287A00B02708426976370F421F7@AUSP01VMBX24.collaborationhost.net>
	<4C10009B.2010607@bluewatersys.com>
	<0D753D10438DA54287A00B02708426976370F422A7@AUSP01VMBX24.collaborationhost.net>
	<4C1008CC.2000201@bluewatersys.com>
Message-ID: <0D753D10438DA54287A00B02708426976370F42366@AUSP01VMBX24.collaborationhost.net>

On Wednesday, June 09, 2010 2:34 PM, Ryan Mallon wrote:
> H Hartley Sweeten wrote:
>> On Wednesday, June 09, 2010 1:59 PM, Ryan Mallon wrote:
>>> H Hartley Sweeten wrote:
>>>> Create a core.c __init function to handle the physmap flash
>>>> registration for all the ep93xx platforms.  Also, modify all
>>>> the ep93xx platforms to use this new function.
>>>>
>>>> This simplifies all the ep93xx platform init code and removes
>>>> all the static variables that would exist in a unified kernel
>>>> supporting multiple ep93xx platforms.
>>> Looks fine. Not sure I understand the second part about the unified
>>> kernel though. Can't we already build all ep93xx boards (at least those
>>> at the same phys offset) into one kernel?
>> 
>> Yes, we already build a unified kernel for boards with the same phys
>> offset.  But with the current code each platform has a private static
>> Resource and platform device for the flash.  Since this data is not
>> tagged as __initdata it just takes up space after initialization.  If
>> a working runtime PHYS_OFFSET patch is ever worked out this static
>> data will increase for each ep93xx platform added.
>
> Ah, that makes sense. Just say that it reduces the size of the kernel
> when including multiple ep93xx boards.

I'll change the commit message when I put the patch into Russell's patch
system.  I'll wait a couple days incase anyone else has a comment.

Regards,
Hartley

From ryan at bluewatersys.com  Wed Jun  9 17:40:02 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Thu, 10 Jun 2010 09:40:02 +1200
Subject: [PATCH 0/3] EP93xx: Add i2s audio support
In-Reply-To: <20100609101742.GA5618@opensource.wolfsonmicro.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<20100609101742.GA5618@opensource.wolfsonmicro.com>
Message-ID: <4C100A32.7010403@bluewatersys.com>

Mark Brown wrote:
> On Tue, Jun 08, 2010 at 10:01:09PM +1200, Ryan Mallon wrote:
>> Repost of the i2s audio series for ep93xx. Patch 2/3 is unchanged. The
>> core support has been modified to move setting of the SPOL and ORIDE
>> bits of the i2sclkdiv register, as well as the i2s pin strapping
>> configuration, to a new function called ep93xx_i2s_acquire which is
>> called from the audio board drivers.
> 
> I've now applied both patches.  There was a trivial fixup required for
> the clocks due to an add/add overlap with the SPI clock - I think it's
> OK but please check.

Stupid question, but where was it applied? I can't find it in any of the
branches at:
http://opensource.wolfsonmicro.com/cgi-bin/gitweb.cgi?p=linux-2.6-asoc.git;a=summary

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From ryan at bluewatersys.com  Wed Jun  9 17:56:07 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Thu, 10 Jun 2010 09:56:07 +1200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006090807.20810.post@hendrik-sattler.de>
References: <4C083BCF.2060500@bluewatersys.com>	<alpine.LFD.2.00.1006081655350.30664@xanadu.home>	<4C0ED074.7050700@bluewatersys.com>
	<201006090807.20810.post@hendrik-sattler.de>
Message-ID: <4C100DF7.3040907@bluewatersys.com>

Hendrik Sattler wrote:
> Am Mittwoch 09 Juni 2010, 01:21:24 schrieb Ryan Mallon:
>> Yes. I thought the problem was that Kconfig doesn't work correctly for
>> this though. Does having 'select MTD_PARTITIONS' automatically cause
>> CONFIG_MTD to be set? If not, then you basically need to have the full
>> config option list, which is basically what defconfig is.
> 
> Anybody thought about improving Kconfig to make this possible?
> Specifying CONFIG_MTD and CONFIG_MTD_PARTITIONS again and again will just 
> repeat information (that CONFIG_MTD_PARTITIONS depends on CONFIG_MTD).
> The recursive 'select' could have a different name.

This could be done by manually fixing the Kconfig files and using the
select keyword to specify mandatory dependencies. For example CONFIG_MTD
should select CONFIG_MTD_PARTITIONS since it cannot work without it. The
MTD_PARTITIONS option will still be hidden until MTD is selected because
of the 'if MTD' at the top of drivers/mtd/Kconfig, but it means the
other Kconfig files doing a select MTD_PARTITIONS would work correctly.

Would be a lot of work to go through all of the Kconfig files and fix
this though.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From broonie at opensource.wolfsonmicro.com  Wed Jun  9 18:22:03 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 9 Jun 2010 23:22:03 +0100
Subject: [PATCH 0/3] EP93xx: Add i2s audio support
In-Reply-To: <4C100A32.7010403@bluewatersys.com>
	(sfid-20100609_224011_305149_EE792DDC)
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<20100609101742.GA5618@opensource.wolfsonmicro.com>
	<4C100A32.7010403@bluewatersys.com>
	(sfid-20100609_224011_305149_EE792DDC)
Message-ID: <C54C83DB-A9D3-4A7A-837B-17644B257251@opensource.wolfsonmicro.com>

On 9 Jun 2010, at 22:40, Ryan Mallon wrote:

> Stupid question, but where was it applied? I can't find it in any of the
> branches at:
> http://opensource.wolfsonmicro.com/cgi-bin/gitweb.cgi?p=linux-2.6-asoc.git;a=summary

Look in my kernel.org repository referenced in MAINTAINERS

   git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound-2.6.git

From catalin.marinas at arm.com  Wed Jun  9 18:26:45 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 09 Jun 2010 23:26:45 +0100
Subject: [PATCH v2 1/4] ARM: Remove the domain switching on ARMv6k/v7 CPUs
In-Reply-To: <alpine.LFD.2.00.1006091447460.30664@xanadu.home>
References: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
	<20100602164841.17783.94825.stgit@e102109-lin.cambridge.arm.com>
	<alpine.LFD.2.00.1006091447460.30664@xanadu.home>
Message-ID: <1276122405.17056.47.camel@toshiba-laptop>

On Wed, 2010-06-09 at 20:10 +0100, Nicolas Pitre wrote:
> Sorry for the delay... I'm just starting to seriously look at this.
> 
> On Wed, 2 Jun 2010, Catalin Marinas wrote:
> 
> > This patch removes the domain switching functionality via the set_fs and
> > __switch_to functions on cores that have a TLS register.
> [...]
> > The user pages access rights are also modified for kernel read-only
> > access rather than read/write so that the copy-on-write mechanism still
> > works. CPU_USE_DOMAINS gets disabled only if HAS_TLS_REG is defined
> > since writing the TLS value to the high vectors page isn't possible.
> 
> I don't like this limitation much.
> 
> Since the vector page has to be accessed somehow for FIQs anyway, and
> the current solution for that involves accesses through the direct
> mapping of the vector page, then this patch could be made to work on
> pre-ARMv6 systems too simply by adding the necessary cache ops around
> the TLS and FIQ updates.

Getting rid of domains in Linux requires that several functions no
longer use LDRT/STRT but LDR/STR. This implies that RO user pages should
also have RO permissions for the kernel. I don't have the old ARM ARM at
hand now but I recall there were some issues with user RO kernel RO
permission on pre-ARMv6 processors (there is an R bit in the CP15
control register which may help, I need to check the documentation).

-- 
Catalin



From nico at fluxnic.net  Wed Jun  9 20:56:28 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 09 Jun 2010 20:56:28 -0400 (EDT)
Subject: [PATCH v2 1/4] ARM: Remove the domain switching on ARMv6k/v7 CPUs
In-Reply-To: <1276122405.17056.47.camel@toshiba-laptop>
References: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
	<20100602164841.17783.94825.stgit@e102109-lin.cambridge.arm.com>
	<alpine.LFD.2.00.1006091447460.30664@xanadu.home>
	<1276122405.17056.47.camel@toshiba-laptop>
Message-ID: <alpine.LFD.2.00.1006092039000.30664@xanadu.home>

On Wed, 9 Jun 2010, Catalin Marinas wrote:

> On Wed, 2010-06-09 at 20:10 +0100, Nicolas Pitre wrote:
> > Sorry for the delay... I'm just starting to seriously look at this.
> > 
> > On Wed, 2 Jun 2010, Catalin Marinas wrote:
> > 
> > > This patch removes the domain switching functionality via the set_fs and
> > > __switch_to functions on cores that have a TLS register.
> > [...]
> > > The user pages access rights are also modified for kernel read-only
> > > access rather than read/write so that the copy-on-write mechanism still
> > > works. CPU_USE_DOMAINS gets disabled only if HAS_TLS_REG is defined
> > > since writing the TLS value to the high vectors page isn't possible.
> > 
> > I don't like this limitation much.
> > 
> > Since the vector page has to be accessed somehow for FIQs anyway, and
> > the current solution for that involves accesses through the direct
> > mapping of the vector page, then this patch could be made to work on
> > pre-ARMv6 systems too simply by adding the necessary cache ops around
> > the TLS and FIQ updates.
> 
> Getting rid of domains in Linux requires that several functions no
> longer use LDRT/STRT but LDR/STR. This implies that RO user pages should
> also have RO permissions for the kernel. I don't have the old ARM ARM at
> hand now but I recall there were some issues with user RO kernel RO
> permission on pre-ARMv6 processors (there is an R bit in the CP15
> control register which may help, I need to check the documentation).

I just checked.  It says:

   The access permission bits in section and page descriptors control 
   access to the corresponding section or page. The access permissions 
   are modified by the System (S) and ROM (R) control bits in CP15 
   register 1.

But those bits are of no use as they are effective only when the MMU 
access permission bits are all 0, otherwise they're ignored.

What I mean, though, is for this patch to work as well on VIVT systems 
by using the domain switching _only_ when updating the TLS value or the 
FIQ handler in the vector page.  So it is simply:

 1) disable IRQs and FIQs

 2) switch domain to manager mode

 3) store data into the vector page

 4) switch the domain back

 5) restore IRQs and FIQs states

On VIPT systems you need only to access the vector page through its 
direct mapping in kernel memory without any domain switching.


Nicolas


From milinevskyy at gmail.com  Wed Jun  9 21:56:27 2010
From: milinevskyy at gmail.com (Dmytro Milinevskyy)
Date: Thu, 10 Jun 2010 04:56:27 +0300
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
In-Reply-To: <20100609204257.GJ1743@mail.wantstofly.org>
References: <4c0ff6b2.0c3ddf0a.2185.2e09@mx.google.com>
	<20100609203720.GK7660@chipmunk> <20100609203929.GL7660@chipmunk>
	<20100609204257.GJ1743@mail.wantstofly.org>
Message-ID: <AANLkTimYjHs29xfc7WpwJROXM4maAlquJb-7REo1GmFy@mail.gmail.com>

Hi!

>>
>> Better still, just make this 'if(!machine_is_openrd_base())'.
>
> That form is more error prone when someone adds the OpenRD-SuperDuper,
> though.
>

I agree, and the similar could be done in pcie initialization.

-- Dima


From milinevskyy at gmail.com  Wed Jun  9 22:24:56 2010
From: milinevskyy at gmail.com (Dmytro Milinevskyy)
Date: Thu, 10 Jun 2010 05:24:56 +0300
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
Message-ID: <4c104d7a.0c3ddf0a.2185.329a@mx.google.com>

Hi!
This patch adds support for the OpenRD Ultimate machine(could be found at http://www.arm.linux.org.uk/developer/machines/list.php?id=2884)

Besides adding machine description this patch adds correction for PHY address for Ultimate version.

Differences from the previous attempt:
 - Correctly filled instances of mv643xx_eth_platform_data in case of ultimate version.
 - Do PCIE initialization w/o additional checks since all openrd types have it
 - Init ge01 if (!openrd-base) to make the code cleaner

Regards,

-- Dmytro Milinevskyy

Signed-off-by: Dmytro Milinevskyy <milinevskyy at gmail.com>
---
 arch/arm/mach-kirkwood/Kconfig        |    7 +++++++
 arch/arm/mach-kirkwood/openrd-setup.c |   26 ++++++++++++++++++++++----
 2 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 29b2163..110a3b8 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell OpenRD Client Board.
 
+config MACH_OPENRD_ULTIMATE
+	bool "Marvell OpenRD Ultimate Board"
+	select MACH_OPENRD
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell OpenRD Ultimate Board.
+
 config MACH_NETSPACE_V2
 	bool "LaCie Network Space v2 NAS Board"
 	help
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec..c3d8c60 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-kirkwood/openrd-setup.c
  *
- * Marvell OpenRD (Base|Client) Board Setup
+ * Marvell OpenRD (Base|Client|Ultimate) Board Setup
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
@@ -73,9 +73,15 @@ static void __init openrd_init(void)
 
 	kirkwood_ehci_init();
 
+	if (machine_is_openrd_ultimate()) {
+		openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
+		openrd_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
+	}
+
 	kirkwood_ge00_init(&openrd_ge00_data);
-	if (machine_is_openrd_client())
+	if (!machine_is_openrd_base())
 		kirkwood_ge01_init(&openrd_ge01_data);
+
 	kirkwood_sata_init(&openrd_sata_data);
 	kirkwood_sdio_init(&openrd_mvsdio_data);
 
@@ -84,8 +90,7 @@ static void __init openrd_init(void)
 
 static int __init openrd_pci_init(void)
 {
-	if (machine_is_openrd_base() || machine_is_openrd_client())
-		kirkwood_pcie_init();
+	kirkwood_pcie_init();
 
 	return 0;
 }
@@ -116,3 +121,16 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
 	.timer		= &kirkwood_timer,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_MACH_OPENRD_ULTIMATE
+MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
+	/* Maintainer: Dhaval Vasa <dhaval.vasa at einfochips.com> */
+	.phys_io	= KIRKWOOD_REGS_PHYS_BASE,
+	.io_pg_offst	= ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+	.boot_params	= 0x00000100,
+	.init_machine	= openrd_init,
+	.map_io		= kirkwood_map_io,
+	.init_irq	= kirkwood_init_irq,
+	.timer		= &kirkwood_timer,
+MACHINE_END
+#endif
-- 
1.7.1



From ohad at wizery.com  Thu Jun 10 00:01:18 2010
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Wed, 9 Jun 2010 23:01:18 -0500
Subject: [PATCH 09/10] omap: mailbox: convert block api to kfifo
In-Reply-To: <496565EC904933469F292DDA3F1663E602CA4D88F3@dlee06.ent.ti.com>
References: <1275546858-29507-1-git-send-email-Hiroshi.DOYU@nokia.com> 
	<1275546858-29507-10-git-send-email-Hiroshi.DOYU@nokia.com> 
	<D2943F03B81C9C458E44DFB213905E02B6325C6A@dlee04.ent.ti.com> 
	<AANLkTik4lW3_xP_e4BStJEYpHlVoNjemEz8zWfIE7gRU@mail.gmail.com> 
	<496565EC904933469F292DDA3F1663E602CA4D88F3@dlee06.ent.ti.com>
Message-ID: <AANLkTik8I7NXU-rdKeUfNToBOPLs2WneoBTtgHiYF_WJ@mail.gmail.com>

On Wed, Jun 9, 2010 at 12:38 AM, Guzman Lugo, Fernando
<fernando.lugo at ti.com> wrote:
>>From: Ohad Ben-Cohen [ohad at wizery.com]
>>But now that you point me to this irq on/off thing, it looks a bit
>>broken in terms of multiple concurrent mbox support since it relies on
>>a global rq_full state. I guess it'd be better to hold that rq_full
>>state in the relevant mbox queue state itself.
>
> Yes, you are right Ohad. Only should be disable the "new message" interrupt of the mailbox which kfifo is full.


Great! do you plan to submit a fix to patch 05/10 then ?

Thanks,
Ohad.

>
> regards,
> Fernando.
>
>>
>>Thanks,
>>Ohad.
>


From jy0922.shim at samsung.com  Thu Jun 10 00:36:35 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 10 Jun 2010 13:36:35 +0900
Subject: [PATCH] [ARM] VIC: Remove resume_sources
Message-ID: <1276144595-17411-1-git-send-email-jy0922.shim@samsung.com>

The resume_sources is the bitmask of interrupts allowed for resume
sources, but it's value is zero in the all machine using VIC then
vic_set_wake returns always error.

The interrupt sources to allow can use to resume sources too and
vic_set_wake called by set_irq_wake desides whether enable or disable
interrupt sources to resume sources, so we don't have any reason to
control resume sources by resume_sources.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
---
 arch/arm/common/vic.c               |   16 ++++------------
 arch/arm/include/asm/hardware/vic.h |    2 +-
 arch/arm/mach-ep93xx/core.c         |    4 ++--
 arch/arm/mach-netx/generic.c        |    2 +-
 arch/arm/mach-nomadik/cpu-8815.c    |    4 ++--
 arch/arm/mach-s3c64xx/irq.c         |    4 ++--
 arch/arm/mach-spear3xx/spear3xx.c   |    2 +-
 arch/arm/mach-spear6xx/spear6xx.c   |    4 ++--
 arch/arm/mach-u300/core.c           |    4 ++--
 arch/arm/mach-versatile/core.c      |    2 +-
 arch/arm/plat-s5p/irq.c             |    2 +-
 11 files changed, 19 insertions(+), 27 deletions(-)

diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index ba65f6e..2a3c8fd 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -35,7 +35,6 @@
  * @sysdev: The system device which is registered.
  * @irq: The IRQ number for the base of the VIC.
  * @base: The register base for the VIC.
- * @resume_sources: A bitmask of interrupts for resume.
  * @resume_irqs: The IRQs enabled for resume.
  * @int_select: Save for VIC_INT_SELECT.
  * @int_enable: Save for VIC_INT_ENABLE.
@@ -47,7 +46,6 @@ struct vic_device {
 
 	void __iomem	*base;
 	int		irq;
-	u32		resume_sources;
 	u32		resume_irqs;
 	u32		int_select;
 	u32		int_enable;
@@ -180,13 +178,12 @@ late_initcall(vic_pm_init);
  * vic_pm_register - Register a VIC for later power management control
  * @base: The base address of the VIC.
  * @irq: The base IRQ for the VIC.
- * @resume_sources: bitmask of interrupts allowed for resume sources.
  *
  * Register the VIC with the system device tree so that it can be notified
  * of suspend and resume requests and ensure that the correct actions are
  * taken to re-instate the settings on resume.
  */
-static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 resume_sources)
+static void __init vic_pm_register(void __iomem *base, unsigned int irq)
 {
 	struct vic_device *v;
 
@@ -195,13 +192,12 @@ static void __init vic_pm_register(void __iomem *base, unsigned int irq, u32 res
 	else {
 		v = &vic_devices[vic_id];
 		v->base = base;
-		v->resume_sources = resume_sources;
 		v->irq = irq;
 		vic_id++;
 	}
 }
 #else
-static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg1) { }
+static inline void vic_pm_register(void __iomem *base, unsigned int irq) { }
 #endif /* CONFIG_PM */
 
 static void vic_ack_irq(unsigned int irq)
@@ -251,9 +247,6 @@ static int vic_set_wake(unsigned int irq, unsigned int on)
 	if (!v)
 		return -EINVAL;
 
-	if (!(bit & v->resume_sources))
-		return -EINVAL;
-
 	if (on)
 		v->resume_irqs |= bit;
 	else
@@ -355,10 +348,9 @@ static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
  * @base: iomem base address
  * @irq_start: starting interrupt number, must be muliple of 32
  * @vic_sources: bitmask of interrupt sources to allow
- * @resume_sources: bitmask of interrupt sources to allow for resume
  */
 void __init vic_init(void __iomem *base, unsigned int irq_start,
-		     u32 vic_sources, u32 resume_sources)
+		     u32 vic_sources)
 {
 	unsigned int i;
 	u32 cellid = 0;
@@ -394,5 +386,5 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
 
 	vic_set_irq_sources(base, irq_start, vic_sources);
 
-	vic_pm_register(base, irq_start, resume_sources);
+	vic_pm_register(base, irq_start);
 }
diff --git a/arch/arm/include/asm/hardware/vic.h b/arch/arm/include/asm/hardware/vic.h
index 5d72550..f87328d 100644
--- a/arch/arm/include/asm/hardware/vic.h
+++ b/arch/arm/include/asm/hardware/vic.h
@@ -41,7 +41,7 @@
 #define VIC_PL192_VECT_ADDR		0xF00
 
 #ifndef __ASSEMBLY__
-void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources, u32 resume_sources);
+void vic_init(void __iomem *base, unsigned int irq_start, u32 vic_sources);
 #endif
 
 #endif
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 9092677..2cfa5c8 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -177,8 +177,8 @@ extern void ep93xx_gpio_init_irq(void);
 
 void __init ep93xx_init_irq(void)
 {
-	vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
-	vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
+	vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
+	vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
 
 	ep93xx_gpio_init_irq();
 }
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 43da8bb..79df60c 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -168,7 +168,7 @@ void __init netx_init_irq(void)
 {
 	int irq;
 
-	vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
+	vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0);
 
 	for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
 		set_irq_chip(irq, &netx_hif_chip);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 91c3c90..aea6dae 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -141,8 +141,8 @@ void __init cpu8815_map_io(void)
 void __init cpu8815_init_irq(void)
 {
 	/* This modified VIC cell has two register blocks, at 0 and 0x20 */
-	vic_init(io_p2v(NOMADIK_IC_BASE + 0x00), IRQ_VIC_START +  0, ~0, 0);
-	vic_init(io_p2v(NOMADIK_IC_BASE + 0x20), IRQ_VIC_START + 32, ~0, 0);
+	vic_init(io_p2v(NOMADIK_IC_BASE + 0x00), IRQ_VIC_START +  0, ~0);
+	vic_init(io_p2v(NOMADIK_IC_BASE + 0x20), IRQ_VIC_START + 32, ~0);
 }
 
 /*
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
index 67a145d..ae34225 100644
--- a/arch/arm/mach-s3c64xx/irq.c
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -54,8 +54,8 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
 	printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
 
 	/* initialise the pair of VICs */
-	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0);
-	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);
+	vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid);
+	vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid);
 
 	/* add the timer sub-irqs */
 
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index e87313a..0e579c8 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -63,7 +63,7 @@ void __init spear3xx_init(void)
 /* This will initialize vic */
 void __init spear3xx_init_irq(void)
 {
-	vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0, 0);
+	vic_init((void __iomem *)VA_SPEAR3XX_ML1_VIC_BASE, 0, ~0);
 }
 
 /* Following will create static virtual/physical mappings */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index baf6bcc..c5dd57e 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -113,8 +113,8 @@ void __init spear6xx_init(void)
 /* This will initialize vic */
 void __init spear6xx_init_irq(void)
 {
-	vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_PRI_BASE, 0, ~0, 0);
-	vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_SEC_BASE, 32, ~0, 0);
+	vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_PRI_BASE, 0, ~0);
+	vic_init((void __iomem *)VA_SPEAR6XX_CPU_VIC_SEC_BASE, 32, ~0);
 }
 
 /* Following will create static virtual/physical mappings */
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 5f34eb6..d887414 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1482,8 +1482,8 @@ void __init u300_init_irq(void)
 	for (i = 0; i < NR_IRQS; i++)
 		set_bit(i, (unsigned long *) &mask[0]);
 	u300_enable_intcon_clock();
-	vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
-	vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
+	vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0]);
+	vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1]);
 }
 
 
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 3dff864..224bfc0 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -116,7 +116,7 @@ void __init versatile_init_irq(void)
 {
 	unsigned int i;
 
-	vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0, 0);
+	vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0);
 
 	set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq);
 
diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c
index 25e1eb6..2ba3ff9 100644
--- a/arch/arm/plat-s5p/irq.c
+++ b/arch/arm/plat-s5p/irq.c
@@ -60,7 +60,7 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic)
 
 	/* initialize the VICs */
 	for (irq = 0; irq < num_vic; irq++)
-		vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
+		vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq]);
 
 	s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
 	s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
-- 
1.7.0.4



From baruch at tkos.co.il  Thu Jun 10 01:26:19 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Thu, 10 Jun 2010 08:26:19 +0300
Subject: [PATCH v3 0/3] Driver for the i.MX2x CMOS Sensor Interface
In-Reply-To: <cover.1274865040.git.baruch@tkos.co.il>
References: <cover.1274865040.git.baruch@tkos.co.il>
Message-ID: <20100610052618.GA31840@jasper.tkos.co.il>

Hi linux-media list,

Ping?
Any news on this?

baruch

On Wed, May 26, 2010 at 12:13:15PM +0300, Baruch Siach wrote:
> This series contains a soc_camera driver for the i.MX25/i.MX27 CSI device, and
> platform code for the i.MX25 and i.MX27 chips. This driver is based on a 
> driver for i.MX27 CSI from Sascha Hauer, that  Alan Carvalho de Assis has 
> posted in linux-media last December[1]. I tested the mx2_camera driver on the 
> i.MX25 PDK. Sascha Hauer has tested a earlier version of this driver on an 
> i.MX27 based board. I included in this version some fixes from Sascha that 
> enable i.MX27 support.
> 
> [1] https://patchwork.kernel.org/patch/67636/
> 
> Changes v2 -> v3
>     Address more comments from Guennadi Liakhovetski.
> 
>     Applied part of Sashca's patch that I forgot in v2.
> 
> Changes v1 -> v2
>     Addressed the comments of Guennadi Liakhovetski except from the following:
> 
>     1. The mclk_get_divisor implementation, since I don't know what this code 
>        is good for
> 
>     2. mx2_videobuf_release should not set pcdev->active on i.MX27, because 
>        mx27_camera_frame_done needs this pointer
> 
>     3. In mx27_camera_emma_buf_init I don't know the meaning of those hard 
>        coded magic numbers
> 
>     Applied i.MX27 fixes from Sascha.
> 
> Baruch Siach (3):
>   mx2_camera: Add soc_camera support for i.MX25/i.MX27
>   mx27: add support for the CSI device
>   mx25: add support for the CSI device
> 
>  arch/arm/mach-mx2/clock_imx27.c          |    2 +-
>  arch/arm/mach-mx2/devices.c              |   31 +
>  arch/arm/mach-mx2/devices.h              |    1 +
>  arch/arm/mach-mx25/clock.c               |   14 +-
>  arch/arm/mach-mx25/devices.c             |   22 +
>  arch/arm/mach-mx25/devices.h             |    1 +
>  arch/arm/plat-mxc/include/mach/memory.h  |    4 +-
>  arch/arm/plat-mxc/include/mach/mx25.h    |    2 +
>  arch/arm/plat-mxc/include/mach/mx2_cam.h |   46 +
>  drivers/media/video/Kconfig              |   13 +
>  drivers/media/video/Makefile             |    1 +
>  drivers/media/video/mx2_camera.c         | 1488 ++++++++++++++++++++++++++++++
>  12 files changed, 1620 insertions(+), 5 deletions(-)
>  create mode 100644 arch/arm/plat-mxc/include/mach/mx2_cam.h
>  create mode 100644 drivers/media/video/mx2_camera.c
> 

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From alex at digriz.org.uk  Thu Jun 10 01:50:26 2010
From: alex at digriz.org.uk (Alexander Clouter)
Date: Thu, 10 Jun 2010 06:50:26 +0100
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
In-Reply-To: <4c104d7a.0c3ddf0a.2185.329a@mx.google.com>
References: <4c104d7a.0c3ddf0a.2185.329a@mx.google.com>
Message-ID: <20100610055026.GM7660@chipmunk>

Hi,

* Dmytro Milinevskyy <milinevskyy at gmail.com> [2010-06-10 05:24:56+0300]:
>
> [snipped]
>
> @@ -84,8 +90,7 @@ static void __init openrd_init(void)
>  
>  static int __init openrd_pci_init(void)
>  {
> -	if (machine_is_openrd_base() || machine_is_openrd_client())
> -		kirkwood_pcie_init();
> +	kirkwood_pcie_init();
>  
>  	return 0;
>  }
>
You just 'broke' kirkwood, welcome to the club.  We all have done this:

http://marc.info/?l=linux-arm-kernel&m=125624586625065&w=2
http://marc.info/?l=linux-arm-kernel&m=125804222219159&w=2

Put that 'if()' clause back in, the 'subsys_initcall(openrd_pci_init)' 
causes that code to run on *all* compiled in boards (think of the case 
where you have SheevaPlug's also enabled).

Cheers

-- 
Alexander Clouter
.sigmonster says: Poverty begins at home.


From g.liakhovetski at gmx.de  Thu Jun 10 02:00:40 2010
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Thu, 10 Jun 2010 08:00:40 +0200 (CEST)
Subject: [PATCH v3 0/3] Driver for the i.MX2x CMOS Sensor Interface
In-Reply-To: <20100610052618.GA31840@jasper.tkos.co.il>
References: <cover.1274865040.git.baruch@tkos.co.il>
	<20100610052618.GA31840@jasper.tkos.co.il>
Message-ID: <Pine.LNX.4.64.1006100759010.12192@axis700.grange>

On Thu, 10 Jun 2010, Baruch Siach wrote:

> Hi linux-media list,
> 
> Ping?
> Any news on this?

Hi Baruch

Sorry for taking longer to review this version, having a bit of a stressed 
week. I did look through this version briefly, looks good so far. I'll 
look at it again and come back to you, perhaps, end of the next week, or, 
with a lot of luck, today / tomorrow.

Thanks
Guennadi

> 
> baruch
> 
> On Wed, May 26, 2010 at 12:13:15PM +0300, Baruch Siach wrote:
> > This series contains a soc_camera driver for the i.MX25/i.MX27 CSI device, and
> > platform code for the i.MX25 and i.MX27 chips. This driver is based on a 
> > driver for i.MX27 CSI from Sascha Hauer, that  Alan Carvalho de Assis has 
> > posted in linux-media last December[1]. I tested the mx2_camera driver on the 
> > i.MX25 PDK. Sascha Hauer has tested a earlier version of this driver on an 
> > i.MX27 based board. I included in this version some fixes from Sascha that 
> > enable i.MX27 support.
> > 
> > [1] https://patchwork.kernel.org/patch/67636/
> > 
> > Changes v2 -> v3
> >     Address more comments from Guennadi Liakhovetski.
> > 
> >     Applied part of Sashca's patch that I forgot in v2.
> > 
> > Changes v1 -> v2
> >     Addressed the comments of Guennadi Liakhovetski except from the following:
> > 
> >     1. The mclk_get_divisor implementation, since I don't know what this code 
> >        is good for
> > 
> >     2. mx2_videobuf_release should not set pcdev->active on i.MX27, because 
> >        mx27_camera_frame_done needs this pointer
> > 
> >     3. In mx27_camera_emma_buf_init I don't know the meaning of those hard 
> >        coded magic numbers
> > 
> >     Applied i.MX27 fixes from Sascha.
> > 
> > Baruch Siach (3):
> >   mx2_camera: Add soc_camera support for i.MX25/i.MX27
> >   mx27: add support for the CSI device
> >   mx25: add support for the CSI device
> > 
> >  arch/arm/mach-mx2/clock_imx27.c          |    2 +-
> >  arch/arm/mach-mx2/devices.c              |   31 +
> >  arch/arm/mach-mx2/devices.h              |    1 +
> >  arch/arm/mach-mx25/clock.c               |   14 +-
> >  arch/arm/mach-mx25/devices.c             |   22 +
> >  arch/arm/mach-mx25/devices.h             |    1 +
> >  arch/arm/plat-mxc/include/mach/memory.h  |    4 +-
> >  arch/arm/plat-mxc/include/mach/mx25.h    |    2 +
> >  arch/arm/plat-mxc/include/mach/mx2_cam.h |   46 +
> >  drivers/media/video/Kconfig              |   13 +
> >  drivers/media/video/Makefile             |    1 +
> >  drivers/media/video/mx2_camera.c         | 1488 ++++++++++++++++++++++++++++++
> >  12 files changed, 1620 insertions(+), 5 deletions(-)
> >  create mode 100644 arch/arm/plat-mxc/include/mach/mx2_cam.h
> >  create mode 100644 drivers/media/video/mx2_camera.c
> > 
> 
> -- 
>                                                      ~. .~   Tk Open Systems
> =}------------------------------------------------ooO--U--Ooo------------{=
>    - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
> 

---
Guennadi Liakhovetski


From eric.y.miao at gmail.com  Thu Jun 10 02:10:22 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Thu, 10 Jun 2010 14:10:22 +0800
Subject: usb gadget on zaurus and kexec
In-Reply-To: <AANLkTim49akRJK0BN_Qk1wL6e5mrdjZioDjGNWlrjUVQ@mail.gmail.com>
References: <20100519154618.GA26381@atrey.karlin.mff.cuni.cz> 
	<AANLkTim49akRJK0BN_Qk1wL6e5mrdjZioDjGNWlrjUVQ@mail.gmail.com>
Message-ID: <AANLkTilCvgvf9Ch55f878nTNTue8tHYmcrLEywsjnylY@mail.gmail.com>

On Thu, May 20, 2010 at 1:05 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Wed, May 19, 2010 at 11:46 PM, Cyril Hrubis <metan at ucw.cz> wrote:
>> Hi!
>> After some testing I found out that no usb gadget (g_ether, g_mass_storage, ...)
>> is working after zaurus boots with kexec. So it seems like some missing
>> initalization (it's working after doing reboot again) anybody has any clue,
>> patch or ideas how to debug this?
>>
>
> Dumping out the registers of the two situations and doing a comparison then
> might be a quick way.
>

Any debugging update on this?


From milinevskyy at gmail.com  Thu Jun 10 02:15:24 2010
From: milinevskyy at gmail.com (Dmytro Milinevskyy)
Date: Thu, 10 Jun 2010 09:15:24 +0300
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
In-Reply-To: <20100610055026.GM7660@chipmunk>
References: <4c104d7a.0c3ddf0a.2185.329a@mx.google.com>
	<20100610055026.GM7660@chipmunk>
Message-ID: <AANLkTilVxQBnoLNT_Z7aoPqjHqNqqXS58Av2txdsuTWm@mail.gmail.com>

Hi!

You are right, I didn't notice that it's called via subsys_initcall.

-- Dima

On Thu, Jun 10, 2010 at 8:50 AM, Alexander Clouter <alex at digriz.org.uk> wrote:
> Hi,
>
> * Dmytro Milinevskyy <milinevskyy at gmail.com> [2010-06-10 05:24:56+0300]:
>>
>> [snipped]
>>
>> @@ -84,8 +90,7 @@ static void __init openrd_init(void)
>>
>> ?static int __init openrd_pci_init(void)
>> ?{
>> - ? ? if (machine_is_openrd_base() || machine_is_openrd_client())
>> - ? ? ? ? ? ? kirkwood_pcie_init();
>> + ? ? kirkwood_pcie_init();
>>
>> ? ? ? return 0;
>> ?}
>>
> You just 'broke' kirkwood, welcome to the club. ?We all have done this:
>
> http://marc.info/?l=linux-arm-kernel&m=125624586625065&w=2
> http://marc.info/?l=linux-arm-kernel&m=125804222219159&w=2
>
> Put that 'if()' clause back in, the 'subsys_initcall(openrd_pci_init)'
> causes that code to run on *all* compiled in boards (think of the case
> where you have SheevaPlug's also enabled).
>
> Cheers
>
> --
> Alexander Clouter
> .sigmonster says: Poverty begins at home.
>


From u.kleine-koenig at pengutronix.de  Thu Jun 10 02:32:34 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 10 Jun 2010 08:32:34 +0200
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <1276090378.2006.11.camel@m0nster>
References: <4C083BCF.2060500@bluewatersys.com>
	<alpine.LFD.2.00.1006081655350.30664@xanadu.home>
	<4C0ED074.7050700@bluewatersys.com>
	<201006090807.20810.post@hendrik-sattler.de>
	<1276090378.2006.11.camel@m0nster>
Message-ID: <20100610063234.GA22533@pengutronix.de>

Hello,

On Wed, Jun 09, 2010 at 06:32:58AM -0700, Daniel Walker wrote:
> On Wed, 2010-06-09 at 08:07 +0200, Hendrik Sattler wrote:
> > Am Mittwoch 09 Juni 2010, 01:21:24 schrieb Ryan Mallon:
> > > Yes. I thought the problem was that Kconfig doesn't work correctly for
> > > this though. Does having 'select MTD_PARTITIONS' automatically cause
> > > CONFIG_MTD to be set? If not, then you basically need to have the full
> > > config option list, which is basically what defconfig is.
> > 
> > Anybody thought about improving Kconfig to make this possible?
> > Specifying CONFIG_MTD and CONFIG_MTD_PARTITIONS again and again will just 
> > repeat information (that CONFIG_MTD_PARTITIONS depends on CONFIG_MTD).
> > The recursive 'select' could have a different name.
> 
> There is work going on to create a SAT solver because the depends lines
> are often expression instead of just specifying a single other config
> option. So updating the select to work correctly isn't entirely trivial.
> 
> The other thing the SAT solver _could_ do is trivialize the current
> defconfig into files to only 10 lines or so depending on which arm ..
> For instance a defconfig file for trout under mach-msm (the one I
> maintain) would look like this,
> 
> CONFIG_MACH_TROUT=y
> CONFIG_MSM_DEBUG_UART3=y
> CONFIG_MMC_MSM7X00A=y
I removed all lines from all defconfigs that don't affect the resulting
.config basing on .35-rc1.  The diffstat is below.  As far as I checked
there are no added lines and the 'pluses' are only context noise.  So
the defconfigs are down to 124.4 (from 1214.4) lines on average.
You can see the result at

	http://git.pengutronix.de/?p=ukl/linux-2.6.git;a=commitdiff;h=arm/defconfig/reduced-v2.6.35-rc1

I'm currently reducing the defconfigs in .34 to be able to compare the
diffstats between (.34 -> .35-rc1) and between (.34-reduced ->
.35-reduced).  I would expect the diff is more or less the same as with
the Kconfig idea.

Compared to the Kconfig idea I see a few advantages:
 - Assuming that kautobuild would only use a base config + per arch
   selections we would loose compile coverage of e.g. CONFIG_AEABI.
 - I have a script that reduces a config, so there is a bit less manual
   work.
 - No need to change kautobuild

Best regards
Uwe

 arch/arm/configs/acs5k_defconfig               | 1146 --------------
 arch/arm/configs/acs5k_tiny_defconfig          |  860 ----------
 arch/arm/configs/afeb9260_defconfig            | 1157 +--------------
 arch/arm/configs/am200epdkit_defconfig         | 1044 +------------
 arch/arm/configs/am3517_evm_defconfig          | 1250 ---------------
 arch/arm/configs/ams_delta_defconfig           | 1224 +--------------
 arch/arm/configs/ap4evb_defconfig              |  722 ---------
 arch/arm/configs/assabet_defconfig             |  862 +----------
 arch/arm/configs/at572d940hfek_defconfig       | 1318 +---------------
 arch/arm/configs/at91cap9adk_defconfig         | 1107 +-------------
 arch/arm/configs/at91rm9200dk_defconfig        |  955 +-----------
 arch/arm/configs/at91rm9200ek_defconfig        |  942 +-----------
 arch/arm/configs/at91sam9260ek_defconfig       |  958 +-----------
 arch/arm/configs/at91sam9261ek_defconfig       | 1087 +-------------
 arch/arm/configs/at91sam9263ek_defconfig       | 1103 +-------------
 arch/arm/configs/at91sam9g20ek_defconfig       | 1049 +------------
 arch/arm/configs/at91sam9rlek_defconfig        |  864 +----------
 arch/arm/configs/ateb9200_defconfig            | 1222 +--------------
 arch/arm/configs/badge4_defconfig              | 1178 +--------------
 arch/arm/configs/bcmring_defconfig             |  721 ---------
 arch/arm/configs/cam60_defconfig               | 1089 +-------------
 arch/arm/configs/carmeva_defconfig             |  696 +--------
 arch/arm/configs/cerfcube_defconfig            |  851 +----------
 arch/arm/configs/cm_t35_defconfig              | 1577 +------------------
 arch/arm/configs/cm_x2xx_defconfig             | 1774 +---------------------
 arch/arm/configs/cm_x300_defconfig             | 1565 ------------------
 arch/arm/configs/cns3420vb_defconfig           |  759 ---------
 arch/arm/configs/colibri_pxa270_defconfig      | 1556 ------------------
 arch/arm/configs/colibri_pxa300_defconfig      | 1082 -------------
 arch/arm/configs/collie_defconfig              |  887 +----------
 arch/arm/configs/corgi_defconfig               | 1621 +-------------------
 arch/arm/configs/cpu9260_defconfig             | 1225 +--------------
 arch/arm/configs/cpu9g20_defconfig             | 1215 +--------------
 arch/arm/configs/cpuat91_defconfig             | 1207 +--------------
 arch/arm/configs/csb337_defconfig              | 1113 +-------------
 arch/arm/configs/csb637_defconfig              | 1124 +-------------
 arch/arm/configs/da8xx_omapl_defconfig         | 1205 --------------
 arch/arm/configs/davinci_all_defconfig         | 1641 -------------------
 arch/arm/configs/devkit8000_defconfig          | 1732 +--------------------
 arch/arm/configs/dove_defconfig                | 1482 -----------------
 arch/arm/configs/ebsa110_defconfig             |  692 +--------
 arch/arm/configs/ecbat91_defconfig             | 1226 +--------------
 arch/arm/configs/edb7211_defconfig             |  554 +-------
 arch/arm/configs/em_x270_defconfig             | 1554 +------------------
 arch/arm/configs/ep93xx_defconfig              | 1340 ----------------
 arch/arm/configs/eseries_pxa_defconfig         | 1128 -------------
 arch/arm/configs/ezx_defconfig                 | 1582 +-------------------
 arch/arm/configs/footbridge_defconfig          | 1185 +--------------
 arch/arm/configs/fortunet_defconfig            |  538 +-------
 arch/arm/configs/g3evm_defconfig               |  717 ---------
 arch/arm/configs/g4evm_defconfig               |  722 ---------
 arch/arm/configs/h3600_defconfig               | 1084 -------------
 arch/arm/configs/h5000_defconfig               |  917 +-----------
 arch/arm/configs/h7201_defconfig               |  542 +-------
 arch/arm/configs/h7202_defconfig               |  697 +--------
 arch/arm/configs/hackkit_defconfig             |  735 +---------
 arch/arm/configs/htcherald_defconfig           | 1073 +-------------
 arch/arm/configs/igep0020_defconfig            | 1467 -----------------
 arch/arm/configs/imote2_defconfig              | 1649 +-------------------
 arch/arm/configs/integrator_defconfig          |  817 +----------
 arch/arm/configs/iop13xx_defconfig             | 1061 +------------
 arch/arm/configs/iop32x_defconfig              | 1282 +---------------
 arch/arm/configs/iop33x_defconfig              | 1300 ---------------
 arch/arm/configs/ixp2000_defconfig             | 1024 +------------
 arch/arm/configs/ixp23xx_defconfig             | 1315 +---------------
 arch/arm/configs/ixp4xx_defconfig              | 1394 +----------------
 arch/arm/configs/jornada720_defconfig          | 1062 -------------
 arch/arm/configs/kafa_defconfig                |  830 +----------
 arch/arm/configs/kb9202_defconfig              | 1179 +--------------
 arch/arm/configs/kirkwood_defconfig            | 1700 --------------------
 arch/arm/configs/ks8695_defconfig              |  946 -----------
 arch/arm/configs/lart_defconfig                |  824 +----------
 arch/arm/configs/loki_defconfig                | 1028 +------------
 arch/arm/configs/lpd270_defconfig              |  968 +------------
 arch/arm/configs/lpd7a400_defconfig            |  835 +----------
 arch/arm/configs/lpd7a404_defconfig            | 1050 +------------
 arch/arm/configs/lubbock_defconfig             |  762 +---------
 arch/arm/configs/lusl7200_defconfig            |  436 +-----
 arch/arm/configs/magician_defconfig            | 1358 +----------------
 arch/arm/configs/mainstone_defconfig           |  755 +---------
 arch/arm/configs/mini2440_defconfig            | 1722 +--------------------
 arch/arm/configs/mmp2_defconfig                | 1135 -------------
 arch/arm/configs/msm_defconfig                 |  830 +----------
 arch/arm/configs/mv78xx0_defconfig             | 1547 ------------------
 arch/arm/configs/mx1_defconfig                 | 1018 +------------
 arch/arm/configs/mx21_defconfig                | 1072 -------------
 arch/arm/configs/mx27_defconfig                | 1152 --------------
 arch/arm/configs/mx31pdk_defconfig             |  728 ---------
 arch/arm/configs/mx3_defconfig                 | 1089 -------------
 arch/arm/configs/mx51_defconfig                | 1130 -------------
 arch/arm/configs/n770_defconfig                | 1283 ---------------
 arch/arm/configs/n8x0_defconfig                | 1134 +-------------
 arch/arm/configs/neocore926_defconfig          | 1205 +--------------
 arch/arm/configs/neponset_defconfig            | 1081 +-------------
 arch/arm/configs/netwinder_defconfig           |  978 +------------
 arch/arm/configs/netx_defconfig                |  845 +----------
 arch/arm/configs/nhk8815_defconfig             | 1185 +--------------
 arch/arm/configs/ns9xxx_defconfig              |   23 -
 arch/arm/configs/nuc910_defconfig              |  844 ----------
 arch/arm/configs/nuc950_defconfig              |  896 -----------
 arch/arm/configs/nuc960_defconfig              |  855 ----------
 arch/arm/configs/omap3_beagle_defconfig        | 1258 +---------------
 arch/arm/configs/omap3_defconfig               | 1969 -----------------------
 arch/arm/configs/omap3_evm_defconfig           | 1429 +-----------------
 arch/arm/configs/omap3_pandora_defconfig       | 1640 +-------------------
 arch/arm/configs/omap3_stalker_lks_defconfig   | 1541 ------------------
 arch/arm/configs/omap3_touchbook_defconfig     | 1809 ---------------------
 arch/arm/configs/omap_2430sdp_defconfig        | 1181 +--------------
 arch/arm/configs/omap_3430sdp_defconfig        | 1553 +------------------
 arch/arm/configs/omap_3630sdp_defconfig        | 1456 -----------------
 arch/arm/configs/omap_4430sdp_defconfig        | 1157 --------------
 arch/arm/configs/omap_apollon_2420_defconfig   |  873 +----------
 arch/arm/configs/omap_generic_1510_defconfig   | 1089 +-------------
 arch/arm/configs/omap_generic_1610_defconfig   | 1092 +-------------
 arch/arm/configs/omap_generic_1710_defconfig   | 1014 +------------
 arch/arm/configs/omap_generic_2420_defconfig   |  619 +--------
 arch/arm/configs/omap_h2_1610_defconfig        | 1234 +---------------
 arch/arm/configs/omap_h4_2420_defconfig        | 1018 +------------
 arch/arm/configs/omap_innovator_1510_defconfig | 1152 +--------------
 arch/arm/configs/omap_innovator_1610_defconfig |  780 ---------
 arch/arm/configs/omap_ldp_defconfig            | 1124 -------------
 arch/arm/configs/omap_osk_5912_defconfig       | 1003 ------------
 arch/arm/configs/omap_perseus2_730_defconfig   |  862 ----------
 arch/arm/configs/omap_zoom2_defconfig          | 1408 +-----------------
 arch/arm/configs/omap_zoom3_defconfig          | 1455 -----------------
 arch/arm/configs/onearm_defconfig              | 1067 +-------------
 arch/arm/configs/orion5x_defconfig             | 1693 --------------------
 arch/arm/configs/overo_defconfig               | 1621 +-------------------
 arch/arm/configs/palmte_defconfig              |  712 ---------
 arch/arm/configs/palmtt_defconfig              |  801 +----------
 arch/arm/configs/palmz71_defconfig             |  839 +----------
 arch/arm/configs/palmz72_defconfig             |  865 ----------
 arch/arm/configs/pcm027_defconfig              |  993 ------------
 arch/arm/configs/picotux200_defconfig          | 1207 +--------------
 arch/arm/configs/pleb_defconfig                |  712 +--------
 arch/arm/configs/pnx4008_defconfig             | 1286 +---------------
 arch/arm/configs/pxa168_defconfig              |  903 -----------
 arch/arm/configs/pxa255-idp_defconfig          |  753 +---------
 arch/arm/configs/pxa3xx_defconfig              | 1207 +--------------
 arch/arm/configs/pxa910_defconfig              |  820 ----------
 arch/arm/configs/qil-a9260_defconfig           | 1146 +--------------
 arch/arm/configs/raumfeld_defconfig            | 1690 --------------------
 arch/arm/configs/realview-smp_defconfig        | 1005 ------------
 arch/arm/configs/realview_defconfig            | 1001 ------------
 arch/arm/configs/rpc_defconfig                 |  882 +-----------
 arch/arm/configs/rx51_defconfig                | 1648 +-------------------
 arch/arm/configs/s3c2410_defconfig             | 2018 ------------------------
 arch/arm/configs/s3c6400_defconfig             | 1445 -----------------
 arch/arm/configs/s5p6440_defconfig             |  947 -----------
 arch/arm/configs/s5p6442_defconfig             |  842 ----------
 arch/arm/configs/s5pc100_defconfig             |  977 ------------
 arch/arm/configs/s5pc110_defconfig             |  858 ----------
 arch/arm/configs/s5pv210_defconfig             |  861 ----------
 arch/arm/configs/sam9_l9260_defconfig          |  962 +-----------
 arch/arm/configs/shannon_defconfig             |  837 +----------
 arch/arm/configs/shark_defconfig               | 1167 --------------
 arch/arm/configs/simpad_defconfig              |  886 +----------
 arch/arm/configs/spear300_defconfig            |  722 ---------
 arch/arm/configs/spear310_defconfig            |  723 ---------
 arch/arm/configs/spear320_defconfig            |  723 ---------
 arch/arm/configs/spear600_defconfig            |  711 ---------
 arch/arm/configs/spitz_defconfig               | 1547 +------------------
 arch/arm/configs/stamp9g20_defconfig           | 1327 ----------------
 arch/arm/configs/stmp378x_defconfig            | 1014 +------------
 arch/arm/configs/stmp37xx_defconfig            |  895 +-----------
 arch/arm/configs/sx1_defconfig                 | 1015 +------------
 arch/arm/configs/tct_hammer_defconfig          |  817 +----------
 arch/arm/configs/trizeps4_defconfig            | 1502 +-----------------
 arch/arm/configs/u300_defconfig                | 1118 -------------
 arch/arm/configs/u8500_defconfig               |  621 --------
 arch/arm/configs/usb-a9260_defconfig           | 1039 +------------
 arch/arm/configs/usb-a9263_defconfig           | 1031 +------------
 arch/arm/configs/versatile_defconfig           |  928 +-----------
 arch/arm/configs/viper_defconfig               | 1502 ------------------
 arch/arm/configs/xcep_defconfig                | 1031 +------------
 arch/arm/configs/yl9200_defconfig              | 1084 +-------------
 arch/arm/configs/zeus_defconfig                | 1842 ---------------------
 177 files changed, 652 insertions(+), 194157 deletions(-)

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From buytenh at wantstofly.org  Thu Jun 10 02:43:30 2010
From: buytenh at wantstofly.org (Lennert Buytenhek)
Date: Thu, 10 Jun 2010 08:43:30 +0200
Subject: [PATCH 1/2 v2] mv643xx_eth: use sw csum for big packets
In-Reply-To: <1276073483-17208-1-git-send-email-saeed@marvell.com>
References: <FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>
	<1276073483-17208-1-git-send-email-saeed@marvell.com>
Message-ID: <20100610064330.GK1743@mail.wantstofly.org>

On Wed, Jun 09, 2010 at 11:51:23AM +0300, Saeed Bishara wrote:

> diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
> index e345ec8..2d0e06b 100644
> --- a/drivers/net/mv643xx_eth.c
> +++ b/drivers/net/mv643xx_eth.c
> @@ -289,6 +289,7 @@ struct mv643xx_eth_shared_private {
>  	unsigned int t_clk;
>  	int extended_rx_coal_limit;
>  	int tx_bw_control;
> +	int tx_csum_limit;
>  };
>  
>  #define TX_BW_CONTROL_ABSENT		0
> @@ -782,7 +783,8 @@ static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
>  		       skb->protocol != htons(ETH_P_8021Q));
>  
>  		tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
> -		if (unlikely(tag_bytes & ~12)) {
> +		if (unlikely(tag_bytes & ~12) ||
> +			skb->len > mp->shared->tx_csum_limit) {

Please line up skb->len with unlikely() on the line above it.


> @@ -2666,6 +2668,9 @@ static int mv643xx_eth_shared_probe(struct platform_device *pdev)
>  	 * Detect hardware parameters.
>  	 */
>  	msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
> +	msp->tx_csum_limit = pd->tx_csum_limit ? pd->tx_csum_limit : 9 * 1024;
> +	/* add header count so we can compare against skb->len */
> +	msp->tx_csum_limit += ETH_HLEN;
>  	infer_hw_params(msp);

Is the limit 9 * 1024 + 14 for the whole packet, or 9 * 1024 for the IP
part?

I.e. what happens if skb->len is 9 * 1024 + 15, but there is one VLAN
tag present -- will the hardware be able to do the checksum offload or
not?


From s.hauer at pengutronix.de  Thu Jun 10 02:36:28 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 10 Jun 2010 08:36:28 +0200
Subject: [PATCH 1/8] MX25: put define for OTG base address in right include
In-Reply-To: <1275987782-16094-1-git-send-email-eric@eukrea.com>
References: <1275987782-16094-1-git-send-email-eric@eukrea.com>
Message-ID: <20100610063627.GF20799@pengutronix.de>

Hi Eric,

applied all but the last one which needs another patch.

Sascha

On Tue, Jun 08, 2010 at 11:02:55AM +0200, Eric B?nard wrote:
> the standard place for this define is include/mach/mx25.h
> 
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> ---
>  arch/arm/mach-mx25/devices.c          |    2 --
>  arch/arm/plat-mxc/include/mach/mx25.h |    1 +
>  2 files changed, 1 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
> index 3a405fa..032a347 100644
> --- a/arch/arm/mach-mx25/devices.c
> +++ b/arch/arm/mach-mx25/devices.c
> @@ -117,8 +117,6 @@ struct platform_device mxc_uart_device4 = {
>  	.num_resources = ARRAY_SIZE(uart4),
>  };
>  
> -#define MX25_OTG_BASE_ADDR 0x53FF4000
> -
>  static u64 otg_dmamask = DMA_BIT_MASK(32);
>  
>  static struct resource mxc_otg_resources[] = {
> diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
> index 4eb6e33..bc0ba27 100644
> --- a/arch/arm/plat-mxc/include/mach/mx25.h
> +++ b/arch/arm/plat-mxc/include/mach/mx25.h
> @@ -34,6 +34,7 @@
>  #define MX25_NFC_BASE_ADDR		0xbb000000
>  #define MX25_DRYICE_BASE_ADDR		0x53ffc000
>  #define MX25_LCDC_BASE_ADDR		0x53fbc000
> +#define MX25_OTG_BASE_ADDR		0x53ff4000
>  
>  #define MX25_INT_DRYICE	25
>  #define MX25_INT_FEC	57
> -- 
> 1.6.3.3
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From eric at eukrea.com  Thu Jun 10 03:00:23 2010
From: eric at eukrea.com (=?ISO-8859-15?Q?Eric_B=E9nard?=)
Date: Thu, 10 Jun 2010 09:00:23 +0200
Subject: [PATCH 1/8] MX25: put define for OTG base address in right include
In-Reply-To: <20100610063627.GF20799@pengutronix.de>
References: <1275987782-16094-1-git-send-email-eric@eukrea.com>
	<20100610063627.GF20799@pengutronix.de>
Message-ID: <4C108D87.5070909@eukrea.com>

Hi Sascha,

Le 10/06/2010 08:36, Sascha Hauer a ?crit :
> applied all but the last one which needs another patch.
>
ok, I'm sending the last one to alsa-devel.

Thanks
Eric


From marek.vasut at gmail.com  Thu Jun 10 03:00:23 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 10 Jun 2010 09:00:23 +0200
Subject: usb gadget on zaurus and kexec
In-Reply-To: <AANLkTilCvgvf9Ch55f878nTNTue8tHYmcrLEywsjnylY@mail.gmail.com>
References: <20100519154618.GA26381@atrey.karlin.mff.cuni.cz>
	<AANLkTim49akRJK0BN_Qk1wL6e5mrdjZioDjGNWlrjUVQ@mail.gmail.com>
	<AANLkTilCvgvf9Ch55f878nTNTue8tHYmcrLEywsjnylY@mail.gmail.com>
Message-ID: <201006100900.23981.marek.vasut@gmail.com>

Dne ?t 10. ?ervna 2010 08:10:22 Eric Miao napsal(a):
> On Thu, May 20, 2010 at 1:05 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> > On Wed, May 19, 2010 at 11:46 PM, Cyril Hrubis <metan at ucw.cz> wrote:
> >> Hi!
> >> After some testing I found out that no usb gadget (g_ether,
> >> g_mass_storage, ...) is working after zaurus boots with kexec. So it
> >> seems like some missing initalization (it's working after doing reboot
> >> again) anybody has any clue, patch or ideas how to debug this?
> > 
> > Dumping out the registers of the two situations and doing a comparison
> > then might be a quick way.
> 
> Any debugging update on this?

Yeah, there's a workaround. Cyril's working on a proper fix, but that might take 
some time. Simply -- UP2OCR is misconfigured.
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From saeed at marvell.com  Thu Jun 10 03:26:17 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Thu, 10 Jun 2010 10:26:17 +0300
Subject: [PATCH] [kirkwood-otg] Leverage the Freescale OTG driver for
	Kirkwood OTG
In-Reply-To: <AANLkTikVeVBdSfeS_p0k4dRwFopELw2OIXUrS1NjEdt6@mail.gmail.com>
References: <1276094138-13497-1-git-send-email-jason.mcmullan@netronome.com>
	<1276094138-13497-2-git-send-email-jason.mcmullan@netronome.com>
	<alpine.LFD.2.00.1006091307321.30664@xanadu.home>
	<AANLkTikVeVBdSfeS_p0k4dRwFopELw2OIXUrS1NjEdt6@mail.gmail.com>
Message-ID: <FCBE654890C0334289D0AD3AF4EF009F9FAC75AA7B@IL-MB01.marvell.com>

 

>-----Original Message-----
>From: Jason McMullan [mailto:jason.mcmullan at netronome.com] 
>Sent: Wednesday, June 09, 2010 9:07 PM
>To: Nicolas Pitre
>Cc: linux-arm-kernel at lists.infradead.org; Haavard Skinnemoen; 
>Ronen Shitrit; Saeed Bishara; Rabeeh Khoury; Guennadi 
>Liakhovetski; Li Yang; Lennert Buytenhek
>Subject: Re: [PATCH] [kirkwood-otg] Leverage the Freescale OTG 
>driver for Kirkwood OTG
>
>On Wed, Jun 9, 2010 at 1:17 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
>> On Wed, 9 Jun 2010, Jason S. McMullan wrote:
>>> NOTE: Your bootloader must ensure that the Kirkwood
>>> ? ? ? USB 2.0 Bridge Window registers are set correctly,
>>> ? ? ? or the driver will stall on the first DMA.
>>
>> Could you add the code to sets that up in the kernel instead?
The ehci-orion.c has the code for setting the DMA. Also, the Marvell
controllers have different usb phy, and the ehci-orion also has the code that
initializes the phy. So we shuold look for the methode for sharing this code
between the host mode and device mode drivers.

>
>Will do.
>
>>> ?config USB_GADGET_FSL_USB2
>>
>> Maybe the help text should be extended to mention Kirkwood?
>
>Again, good idea, will do.
All the orion devices actually have the same usb core.
>
>-- 
>Jason S. McMullan
>Netronome Systems, Inc.
>

From saeed at marvell.com  Thu Jun 10 03:38:05 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Thu, 10 Jun 2010 10:38:05 +0300
Subject: [PATCH 1/2 v2] mv643xx_eth: use sw csum for big packets
In-Reply-To: <20100610064330.GK1743@mail.wantstofly.org>
References: <FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>
	<1276073483-17208-1-git-send-email-saeed@marvell.com>
	<20100610064330.GK1743@mail.wantstofly.org>
Message-ID: <FCBE654890C0334289D0AD3AF4EF009F9FAC75AA96@IL-MB01.marvell.com>

 

>-----Original Message-----
>From: Lennert Buytenhek [mailto:buytenh at wantstofly.org] 
>Sent: Thursday, June 10, 2010 9:44 AM
>To: Saeed Bishara
>Cc: linux-net at vger.kernel.org; linux-arm-kernel at lists.infradead.org
>Subject: Re: [PATCH 1/2 v2] mv643xx_eth: use sw csum for big packets
>
>On Wed, Jun 09, 2010 at 11:51:23AM +0300, Saeed Bishara wrote:
>
>> diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
>> index e345ec8..2d0e06b 100644
>> --- a/drivers/net/mv643xx_eth.c
>> +++ b/drivers/net/mv643xx_eth.c
>> @@ -289,6 +289,7 @@ struct mv643xx_eth_shared_private {
>>  	unsigned int t_clk;
>>  	int extended_rx_coal_limit;
>>  	int tx_bw_control;
>> +	int tx_csum_limit;
>>  };
>>  
>>  #define TX_BW_CONTROL_ABSENT		0
>> @@ -782,7 +783,8 @@ static int txq_submit_skb(struct 
>tx_queue *txq, struct sk_buff *skb)
>>  		       skb->protocol != htons(ETH_P_8021Q));
>>  
>>  		tag_bytes = (void *)ip_hdr(skb) - (void 
>*)skb->data - ETH_HLEN;
>> -		if (unlikely(tag_bytes & ~12)) {
>> +		if (unlikely(tag_bytes & ~12) ||
>> +			skb->len > mp->shared->tx_csum_limit) {
>
>Please line up skb->len with unlikely() on the line above it.
>
>
>> @@ -2666,6 +2668,9 @@ static int 
>mv643xx_eth_shared_probe(struct platform_device *pdev)
>>  	 * Detect hardware parameters.
>>  	 */
>>  	msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk 
>: 133000000;
>> +	msp->tx_csum_limit = pd->tx_csum_limit ? 
>pd->tx_csum_limit : 9 * 1024;
>> +	/* add header count so we can compare against skb->len */
>> +	msp->tx_csum_limit += ETH_HLEN;
>>  	infer_hw_params(msp);
>
>Is the limit 9 * 1024 + 14 for the whole packet, or 9 * 1024 for the IP
>part?
the limit is for the IP part, but I thought that adding the header length, then comparing agains skb->len will be the same. What do you suggest?

>
>I.e. what happens if skb->len is 9 * 1024 + 15, but there is one VLAN
>tag present -- will the hardware be able to do the checksum offload or
>not?
>

From kgene.kim at samsung.com  Thu Jun 10 03:50:41 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 10 Jun 2010 16:50:41 +0900
Subject: [PATCH v3] libata: pata_samsung_cf: Add Samsung PATA controller driver
Message-ID: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>

From: Abhilash Kesavan <a.kesavan at samsung.com>

Adds support for the Samsung PATA controller. This driver is based on the
Libata subsystem and references the earlier patches sent for IDE subsystem.

Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---

Changes since v2:
- Changed the DRV_NAME to pata_samsung_cf
- Used msleep instead of mdelay

 drivers/ata/Makefile          |    1 +
 drivers/ata/pata_samsung_cf.c |  608 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 618 insertions(+), 0 deletions(-)
 create mode 100644 drivers/ata/pata_samsung_cf.c

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index aa85a98..1b5facf 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -796,6 +796,15 @@ config PATA_RZ1000
 
 	  If unsure, say N.
 
+config PATA_SAMSUNG_CF
+	tristate "Samsung SoC PATA support"
+	depends on SAMSUNG_DEV_IDE
+	help
+	  This option enables basic support for Samsung's S3C/S5P board
+	  PATA controllers via the new ATA layer
+
+	  If unsure, say N.
+
 config PATA_WINBOND_VLB
 	tristate "Winbond W83759A VLB PATA support (Experimental)"
 	depends on ISA && EXPERIMENTAL
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 7ef89d7..9576776 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_PATA_OF_PLATFORM)	+= pata_of_platform.o
 obj-$(CONFIG_PATA_QDI)		+= pata_qdi.o
 obj-$(CONFIG_PATA_RB532)	+= pata_rb532_cf.o
 obj-$(CONFIG_PATA_RZ1000)	+= pata_rz1000.o
+obj-$(CONFIG_PATA_SAMSUNG_CF)	+= pata_samsung_cf.o
 obj-$(CONFIG_PATA_WINBOND_VLB)	+= pata_winbond.o
 
 # Should be last but two libata driver
diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
new file mode 100644
index 0000000..fef5515
--- /dev/null
+++ b/drivers/ata/pata_samsung_cf.c
@@ -0,0 +1,608 @@
+/* linux/drivers/ata/pata_samsung_cf.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * PATA driver for Samsung SoCs.
+ * Supports CF Interface in True IDE mode. Currently only PIO mode has been
+ * implemented; UDMA support has to be added.
+ *
+ * Based on:
+ *	PATA driver for AT91SAM9260 Static Memory Controller
+ *	PATA driver for Toshiba SCC controller
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/libata.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <plat/ata.h>
+#include <plat/regs-ata.h>
+
+#define DRV_NAME "pata_samsung_cf"
+#define DRV_VERSION "0.1"
+
+enum s3c_cpu_type {
+	TYPE_S3C64XX,
+	TYPE_S5PC100,
+	TYPE_S5PV210,
+};
+
+/*
+ * struct s3c_ide_info - S3C PATA instance.
+ * @clk: The clock resource for this controller.
+ * @ide_addr: The area mapped for the hardware registers.
+ * @sfr_addr: The area mapped for the special function registers.
+ * @irq: The IRQ number we are using.
+ * @cpu_type: The exact type of this controller.
+ * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
+ */
+struct s3c_ide_info {
+	struct clk *clk;
+	void __iomem *ide_addr;
+	void __iomem *sfr_addr;
+	unsigned int irq;
+	enum s3c_cpu_type cpu_type;
+	unsigned int fifo_status_reg;
+};
+
+static void pata_s3c_set_endian(void *s3c_ide_regbase, u8 mode)
+{
+	u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
+	reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
+	writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
+}
+
+static void pata_s3c_cfg_mode(void *s3c_ide_sfrbase)
+{
+	/* Select true-ide as the internal operating mode */
+	writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
+		s3c_ide_sfrbase + S3C_CFATA_MUX);
+}
+
+static unsigned long
+pata_s3c_setup_timing(struct s3c_ide_info *info, struct ata_device *adev)
+{
+	const struct ata_timing *timing;
+	int cycle_time;
+	int t1;
+	int t2;
+	int t2i;
+	ulong piotime;
+
+	cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
+
+	timing = ata_timing_find_mode(adev->pio_mode);
+	t1	= (timing->setup / cycle_time) & 0xf;
+	t2	= (timing->act8b / cycle_time) & 0xff;
+	t2i	= (timing->rec8b / cycle_time) & 0xff;
+
+	piotime = (t2i << 12) | (t2 << 4) | t1;
+
+	return piotime;
+}
+
+static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+	int mode = adev->pio_mode - XFER_PIO_0;
+	struct s3c_ide_info *info = ap->host->private_data;
+	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
+	ulong piotime;
+
+	/* Calculates timing parameters for PIO mode */
+	piotime = pata_s3c_setup_timing(info, adev);
+
+	/* Enables IORDY if mode requires it */
+	if (ata_pio_need_iordy(adev))
+		ata_cfg |= S3C_ATA_CFG_IORDYEN;
+	else
+		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
+
+	/* Host controller supports upto PIO4 only */
+	if (mode >= 0 && mode <= 4) {
+		writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
+		writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
+	}
+}
+
+/*
+ * Waits until the IDE controller is able to perform next read/write
+ * operation to the disk. Needed for 64XX series boards only.
+ */
+static int wait_for_host_ready(struct s3c_ide_info *info)
+{
+	ulong timeout;
+
+	/* wait for maximum of 20 msec */
+	timeout = jiffies + msecs_to_jiffies(20);
+	while (time_before(jiffies, timeout)) {
+		if ((readl(info->ide_addr + info->fifo_status_reg) >> 28) == 0)
+			return 0;
+	}
+	return -EBUSY;
+}
+
+/*
+ * Writes to one of the task file registers.
+ */
+static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
+{
+	struct s3c_ide_info *info = host->private_data;
+
+	wait_for_host_ready(info);
+	writeb(addr, reg);
+}
+
+/*
+ * Reads from one of the task file registers.
+ */
+static u8 ata_inb(struct ata_host *host, void __iomem *reg)
+{
+	struct s3c_ide_info *info = host->private_data;
+	u8 temp;
+
+	wait_for_host_ready(info);
+	temp = readb(reg);
+	wait_for_host_ready(info);
+	temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
+	return temp;
+}
+
+/*
+ * pata_s3c_tf_load - send taskfile registers to host controller
+ */
+static void pata_s3c_tf_load(struct ata_port *ap,
+				const struct ata_taskfile *tf)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
+
+	if (tf->ctl != ap->last_ctl) {
+		ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
+		ap->last_ctl = tf->ctl;
+		ata_wait_idle(ap);
+	}
+
+	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
+		ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
+		ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
+		ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
+		ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
+		ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
+	}
+
+	if (is_addr) {
+		ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
+		ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
+		ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
+		ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
+		ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
+	}
+
+	if (tf->flags & ATA_TFLAG_DEVICE)
+		ata_outb(ap->host, tf->device, ioaddr->device_addr);
+
+	ata_wait_idle(ap);
+}
+
+/*
+ * pata_s3c_tf_read - input device's ATA taskfile shadow registers
+ */
+static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+
+	tf->feature = ata_inb(ap->host, ioaddr->error_addr);
+	tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+	tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+	tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
+	tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
+	tf->device = ata_inb(ap->host, ioaddr->device_addr);
+
+	if (tf->flags & ATA_TFLAG_LBA48) {
+		iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
+		tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
+		tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+		tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+		tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
+		tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
+		iowrite8(tf->ctl, ioaddr->ctl_addr);
+		ap->last_ctl = tf->ctl;
+	}
+}
+
+/*
+ * pata_s3c_exec_command - issue ATA command to host controller
+ */
+static void pata_s3c_exec_command(struct ata_port *ap,
+				const struct ata_taskfile *tf)
+{
+	ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
+	ata_sff_pause(ap);
+}
+
+/*
+ * pata_s3c_check_status - Read device status register
+ */
+static u8 pata_s3c_check_status(struct ata_port *ap)
+{
+	return ata_inb(ap->host, ap->ioaddr.status_addr);
+}
+
+/*
+ * pata_s3c_check_altstatus - Read alternate device status register
+ */
+static u8 pata_s3c_check_altstatus(struct ata_port *ap)
+{
+	return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
+}
+
+/*
+ * pata_s3c_data_xfer - Transfer data by PIO
+ */
+unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char *buf,
+				unsigned int buflen, int rw)
+{
+	struct ata_port *ap = dev->link->ap;
+	struct s3c_ide_info *info = ap->host->private_data;
+	void __iomem *data_addr = ap->ioaddr.data_addr;
+	unsigned int words = buflen >> 1, i;
+	u16 *data_ptr = (u16 *)buf;
+
+	if (rw == READ)
+		for (i = 0; i < words; i++, data_ptr++) {
+			wait_for_host_ready(info);
+			*data_ptr = readw(data_addr);
+			wait_for_host_ready(info);
+			*data_ptr = readw(info->ide_addr
+					+ S3C_ATA_PIO_RDATA);
+		}
+	else
+		for (i = 0; i < words; i++, data_ptr++) {
+			wait_for_host_ready(info);
+			writel(*data_ptr, data_addr);
+		}
+
+	return words << 1;
+}
+
+/*
+ * pata_s3c_dev_select - Select device on ATA bus
+ */
+static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
+{
+	u8 tmp;
+
+	if (device == 0)
+		tmp = ATA_DEVICE_OBS;
+	else
+		tmp = ATA_DEVICE_OBS | ATA_DEV1;
+
+	ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
+	ata_sff_pause(ap);
+}
+
+/*
+ * pata_s3c_set_devctl - Write device control register
+ */
+static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
+{
+	ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
+}
+
+static struct scsi_host_template pata_s3c_sht = {
+	ATA_PIO_SHT(DRV_NAME),
+};
+
+static struct ata_port_operations pata_s3c_port_ops = {
+	.inherits		= &ata_sff_port_ops,
+	.sff_check_status	= pata_s3c_check_status,
+	.sff_check_altstatus    = pata_s3c_check_altstatus,
+	.sff_tf_load		= pata_s3c_tf_load,
+	.sff_tf_read		= pata_s3c_tf_read,
+	.sff_data_xfer		= pata_s3c_data_xfer,
+	.sff_exec_command	= pata_s3c_exec_command,
+	.sff_dev_select         = pata_s3c_dev_select,
+	.sff_set_devctl         = pata_s3c_set_devctl,
+	.set_piomode		= pata_s3c_set_piomode,
+};
+
+static struct ata_port_operations pata_s5p_port_ops = {
+	.inherits		= &ata_sff_port_ops,
+	.set_piomode		= pata_s3c_set_piomode,
+};
+
+static void pata_s3c_enable(void *s3c_ide_regbase, u8 state)
+{
+	u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
+	temp = state ? (temp | 1) : (temp & ~1);
+	writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
+}
+
+static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
+{
+	struct ata_host *host = dev_instance;
+	struct s3c_ide_info *info = host->private_data;
+	u32 reg;
+
+	reg = readl(info->ide_addr + S3C_ATA_IRQ);
+	writel(reg, info->ide_addr + S3C_ATA_IRQ);
+
+	return ata_sff_interrupt(irq, dev_instance);
+}
+
+static void pata_s3c_hwinit(struct s3c_ide_info *info,
+				struct s3c_ide_platdata *pdata)
+{
+	switch (info->cpu_type) {
+	case TYPE_S3C64XX:
+		/* Configure as big endian */
+		pata_s3c_cfg_mode(info->sfr_addr);
+		pata_s3c_set_endian(info->ide_addr, 1);
+		pata_s3c_enable(info->ide_addr, 1);
+		msleep(100);
+
+		/* Remove IRQ Status */
+		writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
+		writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
+	break;
+
+	case TYPE_S5PC100:
+		pata_s3c_cfg_mode(info->sfr_addr);
+
+	case TYPE_S5PV210:
+		/* Configure as little endian */
+		pata_s3c_set_endian(info->ide_addr, 0);
+		pata_s3c_enable(info->ide_addr, 1);
+		msleep(100);
+
+		/* Remove IRQ Status */
+		writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
+		writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
+	break;
+
+	default:
+		BUG();
+	}
+}
+
+static int __devinit pata_s3c_probe(struct platform_device *pdev)
+{
+	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
+	struct device *dev = &pdev->dev;
+	struct s3c_ide_info *info;
+	struct resource *res;
+	struct ata_port *ap;
+	struct ata_host *host;
+	enum s3c_cpu_type cpu_type;
+	int ret;
+
+	cpu_type = platform_get_device_id(pdev)->driver_data;
+
+	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
+	if (!info) {
+		dev_err(dev, "failed to allocate memory for device data\n");
+		return -ENOMEM;
+	}
+
+	info->irq = platform_get_irq(pdev, 0);
+	if (info->irq < 0) {
+		dev_err(dev, "could not obtain irq number\n");
+		ret = -EINVAL;
+		goto release_device_mem;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(dev, "failed to get mem resource\n");
+		ret = -EINVAL;
+		goto release_device_mem;
+	}
+
+	if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
+		dev_err(dev, "error requesting register region\n");
+		return -EBUSY;
+	}
+
+	info->ide_addr = devm_ioremap(dev, res->start, resource_size(res));
+	if (!info->ide_addr) {
+		dev_err(dev, "failed to map IO base address\n");
+		ret = -ENOMEM;
+		goto release_mem;
+	}
+
+	info->clk = clk_get(&pdev->dev, "cfcon");
+	if (IS_ERR(info->clk)) {
+		dev_err(dev, "failed to get access to cf controller clock\n");
+		ret = PTR_ERR(info->clk);
+		info->clk = NULL;
+	}
+
+	clk_enable(info->clk);
+
+	/* init ata host */
+	host = ata_host_alloc(dev, 1);
+	if (!host) {
+		dev_err(dev, "failed to allocate ide host\n");
+		ret = -ENOMEM;
+		goto stop_clk;
+	}
+
+	ap = host->ports[0];
+	ap->flags |= ATA_FLAG_MMIO;
+	ap->pio_mask = ATA_PIO4;
+
+	if (cpu_type == TYPE_S3C64XX) {
+		ap->ops = &pata_s3c_port_ops;
+		info->sfr_addr = info->ide_addr + 0x1800;
+		info->ide_addr += 0x1900;
+		info->fifo_status_reg = 0x94;
+	} else if (cpu_type == TYPE_S5PC100) {
+		ap->ops = &pata_s5p_port_ops;
+		info->sfr_addr = info->ide_addr + 0x1800;
+		info->ide_addr += 0x1900;
+		info->fifo_status_reg = 0x84;
+	} else {
+		ap->ops = &pata_s5p_port_ops;
+		info->fifo_status_reg = 0x84;
+	}
+
+	info->cpu_type = cpu_type;
+
+	if (!info->irq) {
+		ap->flags |= ATA_FLAG_PIO_POLLING;
+		ata_port_desc(ap, "no IRQ, using PIO polling\n");
+	}
+
+	ap->ioaddr.cmd_addr =  info->ide_addr + S3C_ATA_CMD;
+	ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
+	ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
+	ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
+	ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
+	ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
+	ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
+	ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
+	ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
+	ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
+	ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
+	ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
+	ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
+
+	ata_port_desc(ap, "mmio cmd 0x%llx ",
+			(unsigned long long)res->start);
+
+	host->private_data = info;
+
+	if (pdata && pdata->setup_gpio)
+		pdata->setup_gpio();
+
+	/* Set endianness and enable the interface */
+	pata_s3c_hwinit(info, pdata);
+
+	return ata_host_activate(host, info->irq,
+			info->irq ? pata_s3c_irq : NULL,
+			0, &pata_s3c_sht);
+
+	platform_set_drvdata(pdev, host);
+
+stop_clk:
+	clk_disable(info->clk);
+release_mem:
+	release_mem_region(res->start, resource_size(res));
+release_device_mem:
+	kfree(info);
+return ret;
+}
+
+static int __devexit pata_s3c_remove(struct platform_device *pdev)
+{
+	struct ata_host *host = platform_get_drvdata(pdev);
+	struct s3c_ide_info *info;
+	struct resource *res;
+
+	if (!host)
+		return 0;
+	info = host->private_data;
+
+	ata_host_detach(host);
+
+	clk_disable(info->clk);
+	clk_put(info->clk);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	release_mem_region(res->start, resource_size(res));
+	kfree(info);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int pata_s3c_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ata_host *host = platform_get_drvdata(pdev);
+	pm_message_t state = PMSG_SUSPEND;
+
+	if (host)
+		return ata_host_suspend(host, state);
+	else
+		return 0;
+}
+
+static int pata_s3c_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ata_host *host = platform_get_drvdata(pdev);
+	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
+	struct s3c_ide_info *info;
+
+	info = host->private_data;
+
+	if (host) {
+		pata_s3c_hwinit(info, pdata);
+		ata_host_resume(host);
+	}
+
+	return 0;
+}
+
+static const struct dev_pm_ops pata_s3c_pm_ops = {
+	.suspend	= pata_s3c_suspend,
+	.resume		= pata_s3c_resume,
+};
+#endif
+
+/* driver device registration */
+static struct platform_device_id pata_s3c_driver_ids[] = {
+	{
+		.name		= "s3c64xx-pata",
+		.driver_data	= TYPE_S3C64XX,
+	}, {
+		.name		= "s5pc100-pata",
+		.driver_data	= TYPE_S5PC100,
+	}, {
+		.name		= "s5pv210-pata",
+		.driver_data	= TYPE_S5PV210,
+	},
+	{ }
+};
+
+MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
+
+static struct platform_driver pata_s3c_driver = {
+	.probe		= pata_s3c_probe,
+	.remove		= __devexit_p(pata_s3c_remove),
+	.id_table	= pata_s3c_driver_ids,
+	.driver		= {
+		.name	= DRV_NAME,
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &pata_s3c_pm_ops,
+#endif
+	},
+};
+
+static int __init pata_s3c_init(void)
+{
+	return platform_driver_register(&pata_s3c_driver);
+}
+
+static void __exit pata_s3c_exit(void)
+{
+	platform_driver_unregister(&pata_s3c_driver);
+}
+
+module_init(pata_s3c_init);
+module_exit(pata_s3c_exit);
+
+MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan at samsung.com>");
+MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
-- 
1.6.2.5



From w.sang at pengutronix.de  Thu Jun 10 04:10:42 2010
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Thu, 10 Jun 2010 10:10:42 +0200
Subject: [PATCH 1/3] mx25: add watchdog clock
In-Reply-To: <bc8385e0c903851918839a66f9e582a507434e93.1276081393.git.baruch@tkos.co.il>
References: <cover.1276081393.git.baruch@tkos.co.il>
	<bc8385e0c903851918839a66f9e582a507434e93.1276081393.git.baruch@tkos.co.il>
Message-ID: <20100610081042.GB5333@pengutronix.de>

Hi Baruch,

On Wed, Jun 09, 2010 at 02:07:00PM +0300, Baruch Siach wrote:
> Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> ---
>  arch/arm/mach-mx25/clock.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
> index 1550149..f9662d9 100644
> --- a/arch/arm/mach-mx25/clock.c
> +++ b/arch/arm/mach-mx25/clock.c
> @@ -191,6 +191,7 @@ DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
>  DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
>  DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
>  DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
> +DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR1, 19, get_rate_ipg, NULL,  NULL);

That is clk_gpt1 according to my RM (Rev 1)?

>  
>  #define _REGISTER_CLOCK(d, n, c)	\
>  	{				\
> @@ -225,6 +226,7 @@ static struct clk_lookup lookups[] = {
>  	_REGISTER_CLOCK("fec.0", NULL, fec_clk)
>  	_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
>  	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
> +	_REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
>  };
>  
>  int __init mx25_clocks_init(void)
> -- 
> 1.7.1
> 

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From baruch at tkos.co.il  Thu Jun 10 04:18:06 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Thu, 10 Jun 2010 11:18:06 +0300
Subject: [PATCH 1/3] mx25: add watchdog clock
In-Reply-To: <20100610081042.GB5333@pengutronix.de>
References: <cover.1276081393.git.baruch@tkos.co.il>
	<bc8385e0c903851918839a66f9e582a507434e93.1276081393.git.baruch@tkos.co.il>
	<20100610081042.GB5333@pengutronix.de>
Message-ID: <20100610081806.GC31840@jasper.tkos.co.il>

Hi Wolfram,

On Thu, Jun 10, 2010 at 10:10:42AM +0200, Wolfram Sang wrote:
> On Wed, Jun 09, 2010 at 02:07:00PM +0300, Baruch Siach wrote:
> > Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> > ---
> >  arch/arm/mach-mx25/clock.c |    2 ++
> >  1 files changed, 2 insertions(+), 0 deletions(-)
> > 
> > diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
> > index 1550149..f9662d9 100644
> > --- a/arch/arm/mach-mx25/clock.c
> > +++ b/arch/arm/mach-mx25/clock.c
> > @@ -191,6 +191,7 @@ DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
> >  DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
> >  DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
> >  DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
> > +DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR1, 19, get_rate_ipg, NULL,  NULL);
> 
> That is clk_gpt1 according to my RM (Rev 1)?

Right. It should be CCM_CGCR2. I'll fix this.

Note that this bit is marked "Reserved" in the RM. But a look at the Freescale 
supplied BSP reveals the following line in crm_regs.h:

#define MXC_CCM_CGCR2_WDOG_OFFSET        (51-32)

baruch

> >  
> >  #define _REGISTER_CLOCK(d, n, c)	\
> >  	{				\
> > @@ -225,6 +226,7 @@ static struct clk_lookup lookups[] = {
> >  	_REGISTER_CLOCK("fec.0", NULL, fec_clk)
> >  	_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
> >  	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
> > +	_REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
> >  };
> >  
> >  int __init mx25_clocks_init(void)
> > -- 
> > 1.7.1

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From w.sang at pengutronix.de  Thu Jun 10 04:21:45 2010
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Thu, 10 Jun 2010 10:21:45 +0200
Subject: [PATCH 1/3] mx25: add watchdog clock
In-Reply-To: <20100610081806.GC31840@jasper.tkos.co.il>
References: <cover.1276081393.git.baruch@tkos.co.il>
	<bc8385e0c903851918839a66f9e582a507434e93.1276081393.git.baruch@tkos.co.il>
	<20100610081042.GB5333@pengutronix.de>
	<20100610081806.GC31840@jasper.tkos.co.il>
Message-ID: <20100610082145.GC5333@pengutronix.de>

On Thu, Jun 10, 2010 at 11:18:06AM +0300, Baruch Siach wrote:
> Hi Wolfram,
> 
> On Thu, Jun 10, 2010 at 10:10:42AM +0200, Wolfram Sang wrote:
> > On Wed, Jun 09, 2010 at 02:07:00PM +0300, Baruch Siach wrote:
> > > Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> > > ---
> > >  arch/arm/mach-mx25/clock.c |    2 ++
> > >  1 files changed, 2 insertions(+), 0 deletions(-)
> > > 
> > > diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
> > > index 1550149..f9662d9 100644
> > > --- a/arch/arm/mach-mx25/clock.c
> > > +++ b/arch/arm/mach-mx25/clock.c
> > > @@ -191,6 +191,7 @@ DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
> > >  DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
> > >  DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
> > >  DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
> > > +DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR1, 19, get_rate_ipg, NULL,  NULL);
> > 
> > That is clk_gpt1 according to my RM (Rev 1)?
> 
> Right. It should be CCM_CGCR2. I'll fix this.
> 
> Note that this bit is marked "Reserved" in the RM. But a look at the Freescale 
> supplied BSP reveals the following line in crm_regs.h:
> 
> #define MXC_CCM_CGCR2_WDOG_OFFSET        (51-32)

OK. Please add this information also in a short comment above the clock
definition.

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From u.kleine-koenig at pengutronix.de  Thu Jun 10 04:27:17 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 10 Jun 2010 10:27:17 +0200
Subject: [PATCH 2/5] [ARM] Remove unused INITRD_PHYS from
	arch/arm/boot/compressed
In-Reply-To: <1275550613-9553-3-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-3-git-send-email-eric.miao@canonical.com>
Message-ID: <20100610082716.GA3422@pengutronix.de>

Hello,

On Thu, Jun 03, 2010 at 03:36:50PM +0800, Eric Miao wrote:
> From: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> 
> Original patch from Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>.
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> Signed-off-by: Eric Miao <eric.miao at canonical.com>
The patch is OK, but the commit log of my patch was (IMHO) better.
Something like:

Only arch/arm/boot/bootp/init.S uses initrd_phys, so there is no need to
pass it in arch/arm/boot/compressed.

And I would prefer not to have this "Original patch from ..." in the
commit log.  Do you use it because the patch system doesn't offer to
specify the author of a commit?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From baruch at tkos.co.il  Thu Jun 10 04:27:56 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Thu, 10 Jun 2010 11:27:56 +0300
Subject: [PATCH 1/3] mx25: add watchdog clock
In-Reply-To: <20100610082145.GC5333@pengutronix.de>
References: <cover.1276081393.git.baruch@tkos.co.il>
	<bc8385e0c903851918839a66f9e582a507434e93.1276081393.git.baruch@tkos.co.il>
	<20100610081042.GB5333@pengutronix.de>
	<20100610081806.GC31840@jasper.tkos.co.il>
	<20100610082145.GC5333@pengutronix.de>
Message-ID: <20100610082756.GD31840@jasper.tkos.co.il>

Hi Wolfram,
On Thu, Jun 10, 2010 at 10:21:45AM +0200, Wolfram Sang wrote:
> On Thu, Jun 10, 2010 at 11:18:06AM +0300, Baruch Siach wrote:
> > On Thu, Jun 10, 2010 at 10:10:42AM +0200, Wolfram Sang wrote:
> > > On Wed, Jun 09, 2010 at 02:07:00PM +0300, Baruch Siach wrote:
> > > > Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> > > > ---
> > > >  arch/arm/mach-mx25/clock.c |    2 ++
> > > >  1 files changed, 2 insertions(+), 0 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
> > > > index 1550149..f9662d9 100644
> > > > --- a/arch/arm/mach-mx25/clock.c
> > > > +++ b/arch/arm/mach-mx25/clock.c
> > > > @@ -191,6 +191,7 @@ DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
> > > >  DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
> > > >  DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
> > > >  DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
> > > > +DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR1, 19, get_rate_ipg, NULL,  NULL);
> > > 
> > > That is clk_gpt1 according to my RM (Rev 1)?
> > 
> > Right. It should be CCM_CGCR2. I'll fix this.
> > 
> > Note that this bit is marked "Reserved" in the RM. But a look at the Freescale 
> > supplied BSP reveals the following line in crm_regs.h:
> > 
> > #define MXC_CCM_CGCR2_WDOG_OFFSET        (51-32)
> 
> OK. Please add this information also in a short comment above the clock
> definition.

There are 12 other IPG clock bit that are wrongly marked "Reserved" in the RM.  
Should we add a comment for each?

baruch

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From w.sang at pengutronix.de  Thu Jun 10 04:34:54 2010
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Thu, 10 Jun 2010 10:34:54 +0200
Subject: [PATCH 1/3] mx25: add watchdog clock
In-Reply-To: <20100610082756.GD31840@jasper.tkos.co.il>
References: <cover.1276081393.git.baruch@tkos.co.il>
	<bc8385e0c903851918839a66f9e582a507434e93.1276081393.git.baruch@tkos.co.il>
	<20100610081042.GB5333@pengutronix.de>
	<20100610081806.GC31840@jasper.tkos.co.il>
	<20100610082145.GC5333@pengutronix.de>
	<20100610082756.GD31840@jasper.tkos.co.il>
Message-ID: <20100610083454.GD5333@pengutronix.de>

On Thu, Jun 10, 2010 at 11:27:56AM +0300, Baruch Siach wrote:
> Hi Wolfram,
> On Thu, Jun 10, 2010 at 10:21:45AM +0200, Wolfram Sang wrote:
> > On Thu, Jun 10, 2010 at 11:18:06AM +0300, Baruch Siach wrote:
> > > On Thu, Jun 10, 2010 at 10:10:42AM +0200, Wolfram Sang wrote:
> > > > On Wed, Jun 09, 2010 at 02:07:00PM +0300, Baruch Siach wrote:
> > > > > Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> > > > > ---
> > > > >  arch/arm/mach-mx25/clock.c |    2 ++
> > > > >  1 files changed, 2 insertions(+), 0 deletions(-)
> > > > > 
> > > > > diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
> > > > > index 1550149..f9662d9 100644
> > > > > --- a/arch/arm/mach-mx25/clock.c
> > > > > +++ b/arch/arm/mach-mx25/clock.c
> > > > > @@ -191,6 +191,7 @@ DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
> > > > >  DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
> > > > >  DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
> > > > >  DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
> > > > > +DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR1, 19, get_rate_ipg, NULL,  NULL);
> > > > 
> > > > That is clk_gpt1 according to my RM (Rev 1)?
> > > 
> > > Right. It should be CCM_CGCR2. I'll fix this.
> > > 
> > > Note that this bit is marked "Reserved" in the RM. But a look at the Freescale 
> > > supplied BSP reveals the following line in crm_regs.h:
> > > 
> > > #define MXC_CCM_CGCR2_WDOG_OFFSET        (51-32)
> > 
> > OK. Please add this information also in a short comment above the clock
> > definition.
> 
> There are 12 other IPG clock bit that are wrongly marked "Reserved" in the RM.  
> Should we add a comment for each?

Hmm, an introductory "global" comment should do IMO. Like "Some bits are marked
reserved in the reference manual (v1), but have been used in the official
BSPs, so we copied that". What do you think?

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From baruch at tkos.co.il  Thu Jun 10 04:45:11 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Thu, 10 Jun 2010 11:45:11 +0300
Subject: [PATCH 1/3] mx25: add watchdog clock
In-Reply-To: <20100610083454.GD5333@pengutronix.de>
References: <cover.1276081393.git.baruch@tkos.co.il>
	<bc8385e0c903851918839a66f9e582a507434e93.1276081393.git.baruch@tkos.co.il>
	<20100610081042.GB5333@pengutronix.de>
	<20100610081806.GC31840@jasper.tkos.co.il>
	<20100610082145.GC5333@pengutronix.de>
	<20100610082756.GD31840@jasper.tkos.co.il>
	<20100610083454.GD5333@pengutronix.de>
Message-ID: <20100610084511.GE31840@jasper.tkos.co.il>

On Thu, Jun 10, 2010 at 10:34:54AM +0200, Wolfram Sang wrote:
> On Thu, Jun 10, 2010 at 11:27:56AM +0300, Baruch Siach wrote:
> > Hi Wolfram,
> > On Thu, Jun 10, 2010 at 10:21:45AM +0200, Wolfram Sang wrote:
> > > On Thu, Jun 10, 2010 at 11:18:06AM +0300, Baruch Siach wrote:
> > > > On Thu, Jun 10, 2010 at 10:10:42AM +0200, Wolfram Sang wrote:
> > > > > On Wed, Jun 09, 2010 at 02:07:00PM +0300, Baruch Siach wrote:
> > > > > > Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> > > > > > ---
> > > > > >  arch/arm/mach-mx25/clock.c |    2 ++
> > > > > >  1 files changed, 2 insertions(+), 0 deletions(-)
> > > > > > 
> > > > > > diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
> > > > > > index 1550149..f9662d9 100644
> > > > > > --- a/arch/arm/mach-mx25/clock.c
> > > > > > +++ b/arch/arm/mach-mx25/clock.c
> > > > > > @@ -191,6 +191,7 @@ DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
> > > > > >  DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
> > > > > >  DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
> > > > > >  DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
> > > > > > +DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR1, 19, get_rate_ipg, NULL,  NULL);
> > > > > 
> > > > > That is clk_gpt1 according to my RM (Rev 1)?
> > > > 
> > > > Right. It should be CCM_CGCR2. I'll fix this.
> > > > 
> > > > Note that this bit is marked "Reserved" in the RM. But a look at the Freescale 
> > > > supplied BSP reveals the following line in crm_regs.h:
> > > > 
> > > > #define MXC_CCM_CGCR2_WDOG_OFFSET        (51-32)
> > > 
> > > OK. Please add this information also in a short comment above the clock
> > > definition.
> > 
> > There are 12 other IPG clock bit that are wrongly marked "Reserved" in the RM.  
> > Should we add a comment for each?
> 
> Hmm, an introductory "global" comment should do IMO. Like "Some bits are marked
> reserved in the reference manual (v1), but have been used in the official
> BSPs, so we copied that". What do you think?

OK. But I think this should be in a separate patch, since this comment covers 
clocks already in use, and some others not yet in use.

I'll post a patch later today.

baruch

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From u.kleine-koenig at pengutronix.de  Thu Jun 10 04:48:34 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 10 Jun 2010 10:48:34 +0200
Subject: [PATCH 1/5] [ARM] Remove unused PARAMS_PHYS from
	arch/arm/boot/compressed
In-Reply-To: <1275550613-9553-2-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-2-git-send-email-eric.miao@canonical.com>
Message-ID: <20100610084834.GB3422@pengutronix.de>

Hallo,

On Thu, Jun 03, 2010 at 03:36:49PM +0800, Eric Miao wrote:
> From: Eric Miao <eric.y.miao at gmail.com>
> 
> The only reference in arch/arm/boot/compressed to PARAMS_PHYS is
> params() in head.S, which can be directly converted to the exact
> address as specified by arch/arm/mach-rpc/Makefile.boot.
> 
> Signed-off-by: Eric Miao <eric.miao at canonical.com>
Acked-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

So params_phys-y is only used in arch/arm/boot/bootp.  Is this still
used?  It doesn't check r2 for finding the atag list but only uses
params_phys-y.  So according to Keith's fail-safe method for the removal
of cruft[1] bootp can be deleted.   (Unless I didn't see that the kernel
still finds the atag list at params_phys-y if r2 isn't pointing to the
correct address.)  (OK, if r2 and params_phys-y agree, it could still
work.)

Who cares to fix bootp?  Should we delete it?

Best regards
Uwe

[1] 1. promise that there will be long-term support.
    2. Realize failure.
    3. "Accidentally" break things in the code.
    4. Let a few years go by, and note that nobody has complained about
       the broken features.
    5. Remove the code since it is obviously not being used.

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From u.kleine-koenig at pengutronix.de  Thu Jun 10 04:50:53 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 10 Jun 2010 10:50:53 +0200
Subject: [PATCH 3/5] [ARM] Make TEXT_OFFSET a configurable option
In-Reply-To: <1275550613-9553-4-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-4-git-send-email-eric.miao@canonical.com>
Message-ID: <20100610085053.GC3422@pengutronix.de>

On Thu, Jun 03, 2010 at 03:36:51PM +0800, Eric Miao wrote:
> From: Eric Miao <eric.y.miao at gmail.com>
> 
> Signed-off-by: Eric Miao <eric.miao at canonical.com>
> ---
>  arch/arm/Kconfig         |   13 +++++++++++++
>  arch/arm/Makefile        |   13 +------------
>  arch/arm/kernel/Makefile |    4 ++--
>  3 files changed, 16 insertions(+), 14 deletions(-)
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 1f254bd..e340193 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1484,6 +1484,19 @@ config ATAGS_PROC
>  	  Should the atags used to boot the kernel be exported in an "atags"
>  	  file in procfs. Useful with kexec.
>  
> +config TEXT_OFFSET
> +	hex "Offset of the kernel image from the start of RAM"
IMHO this should not be user configurable.

> +	default 0x00008000
> +	default 0x00028000 if ARCH_CLPS711X
> +	# We don't want the htc bootloader to corrupt kernel during resume
> +	default 0x00108000 if PM_H1940
> +	# SA1111 DMA bug: we don't want the kernel to live in precious
> +	# DMA-able memory
> +	default 0x00208000 if (ARCH_SA1100 && SA1111)
> +	help
> +	  TEXT_OFFSET is the offset of the decompressed kernel image from
> +	  memory start. Currently, it is expected the least significant 16
> +	  bits to be 0x8000, so to leave space for the initial page table.
>  endmenu
>  
>  menu "CPU Power Management"
> diff --git a/arch/arm/Makefile b/arch/arm/Makefile
> index 64ba313..df8f73d 100644
> --- a/arch/arm/Makefile
> +++ b/arch/arm/Makefile
> @@ -108,14 +108,6 @@ CHECKFLAGS	+= -D__arm__
>  
>  #Default value
>  head-y		:= arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o
> -textofs-y	:= 0x00008000
> -textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
> -# We don't want the htc bootloader to corrupt kernel during resume
> -textofs-$(CONFIG_PM_H1940)      := 0x00108000
> -# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
> -ifeq ($(CONFIG_ARCH_SA1100),y)
> -textofs-$(CONFIG_SA1111) := 0x00208000
> -endif
>  
>  # Machine directory name.  This list is sorted alphanumerically
>  # by CONFIG_* macro name.
> @@ -209,9 +201,6 @@ CFLAGS_3c589_cs.o :=-DISA_SIXTEEN_BIT_PERIPHERAL
>  export CFLAGS_3c589_cs.o
>  endif
>  
> -# The byte offset of the kernel image in RAM from the start of RAM.
> -TEXT_OFFSET := $(textofs-y)
> -
>  # The first directory contains additional information for the boot setup code
>  ifneq ($(machine-y),)
>  MACHINE  := arch/arm/mach-$(word 1,$(machine-y))/
> @@ -228,7 +217,7 @@ else
>  KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
>  endif
>  
> -export	TEXT_OFFSET GZFLAGS MMUEXT
> +export	GZFLAGS MMUEXT
>  
>  # Do we have FASTFPE?
>  FASTFPE		:=arch/arm/fastfpe
> diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
> index 26d302c..50a0d7e 100644
> --- a/arch/arm/kernel/Makefile
> +++ b/arch/arm/kernel/Makefile
> @@ -2,8 +2,8 @@
>  # Makefile for the linux kernel.
>  #
>  
> -CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET)
> -AFLAGS_head.o        := -DTEXT_OFFSET=$(TEXT_OFFSET)
> +CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(CONFIG_TEXT_OFFSET)
> +AFLAGS_head.o        := -DTEXT_OFFSET=$(CONFIG_TEXT_OFFSET)
Why not use CONFIG_TEXT_OFFSET directly in head.S?
Is CONFIG_TEXT_OFFSET available in vmlinux.lds?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From jgarzik at pobox.com  Thu Jun 10 04:52:07 2010
From: jgarzik at pobox.com (Jeff Garzik)
Date: Thu, 10 Jun 2010 04:52:07 -0400
Subject: [PATCH v3] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
References: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <4C10A7B7.4090601@pobox.com>

On 06/10/2010 03:50 AM, Kukjin Kim wrote:
> From: Abhilash Kesavan<a.kesavan at samsung.com>
>
> Adds support for the Samsung PATA controller. This driver is based on the
> Libata subsystem and references the earlier patches sent for IDE subsystem.
>
> Signed-off-by: Abhilash Kesavan<a.kesavan at samsung.com>
> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
> ---
>
> Changes since v2:
> - Changed the DRV_NAME to pata_samsung_cf
> - Used msleep instead of mdelay
>
>   drivers/ata/Makefile          |    1 +
>   drivers/ata/pata_samsung_cf.c |  608 +++++++++++++++++++++++++++++++++++++++++
>   3 files changed, 618 insertions(+), 0 deletions(-)
>   create mode 100644 drivers/ata/pata_samsung_cf.c

Acked-by: Jeff Garzik <jgarzik at redhat.com>


I presume you'll send this upstream via the appropriate ARM tree.




From ben-linux at fluff.org  Thu Jun 10 04:56:39 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Thu, 10 Jun 2010 09:56:39 +0100
Subject: [PATCH v3] libata: pata_samsung_cf: Add Samsung PATA
	controller driver
In-Reply-To: <4C10A7B7.4090601@pobox.com>
References: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
	<4C10A7B7.4090601@pobox.com>
Message-ID: <20100610085639.GU7248@trinity.fluff.org>

On Thu, Jun 10, 2010 at 04:52:07AM -0400, Jeff Garzik wrote:
> On 06/10/2010 03:50 AM, Kukjin Kim wrote:
>> From: Abhilash Kesavan<a.kesavan at samsung.com>
>>
>> Adds support for the Samsung PATA controller. This driver is based on the
>> Libata subsystem and references the earlier patches sent for IDE subsystem.
>>
>> Signed-off-by: Abhilash Kesavan<a.kesavan at samsung.com>
>> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
>> ---
>>
>> Changes since v2:
>> - Changed the DRV_NAME to pata_samsung_cf
>> - Used msleep instead of mdelay
>>
>>   drivers/ata/Makefile          |    1 +
>>   drivers/ata/pata_samsung_cf.c |  608 +++++++++++++++++++++++++++++++++++++++++
>>   3 files changed, 618 insertions(+), 0 deletions(-)
>>   create mode 100644 drivers/ata/pata_samsung_cf.c
>
> Acked-by: Jeff Garzik <jgarzik at redhat.com>
>
>
> I presume you'll send this upstream via the appropriate ARM tree.

It depends on whether Linus un-declares his current suspensio nof
ARM based work. The machine updtaes should go via the samsung tree
but whether to send the driver that was is another matter (I prefer
to have drivers go via the driver's tree to avoid clashes in
Makefile and Kconfig).

PS, what's your policy on -rc inclusion of completely new code
such as this?

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From u.kleine-koenig at pengutronix.de  Thu Jun 10 05:00:15 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 10 Jun 2010 11:00:15 +0200
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option
	for exceptions
In-Reply-To: <1275550613-9553-5-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
Message-ID: <20100610090015.GD3422@pengutronix.de>

On Thu, Jun 03, 2010 at 03:36:52PM +0800, Eric Miao wrote:
> From: Eric Miao <eric.y.miao at gmail.com>
> 
> Original idea and prototype came from Nicolas Pitre.
> 
> As long as the zImage is placed within the 256MB range from the
> start of the memory, ZRELADDR (Address where the decompressed
> kernel will be placed, usually  == PHYS_OFFSET + TEXT_OFFSET)
s/  / /

> can be determined at run-time by masking PC with 0xf000_0000.
> 
> Running through all the Makefile.boot, all those zreladdr-y
> address == 0x[0-f]000_0000 + TEXT_OFFSET can be determined at
> run-time.
> 
> Option CONFIG_AUTO_ZRELADDR and CONFIG_ZRELADDR are introduced,
> CONFIG_ZRELADDR _must_ be explicitly specified if:
> 
>  - ((zreladdr-y - TEXT_OFFSET) & ~0xf0000000) != 0, which means
>    a maksing of PC with 0xf000_0000 will result an incorrect
s/maksing of/masking/ (note: there are 2 changes)

>    address.
> 
>  - or the assumption of the zImage being loaded by the boot
>    loader within 256MB from the start address is simply
>    incorrect
Hmmm, this makes the image depending on the bootloader.  Not that nice.

>  - or when ZBOOT_ROM is used, where the above assumption is
>    normally wrong
So guess based on sp :-)

> List of all Makefile.boot:
> 
> Hardcoded, and can be auto calculated by masking PC with 0xf000_0000:
> 
> arch/arm/mach-cns3xxx/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-dove/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-ebsa110/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-footbridge/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-integrator/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-iop13xx/Makefile.boot:	   zreladdr-y   := 0x00008000
> arch/arm/mach-iop33x/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-ixp2000/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-ixp23xx/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-ixp4xx/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-kirkwood/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-ks8695/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-loki/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-mmp/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-mv78xx0/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-nomadik/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-nuc93x/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-ns9xxx/Makefile.boot:	   zreladdr-y	:= 0x8000
> arch/arm/mach-orion5x/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-spear3xx/Makefile.boot:      zreladdr-y	:= 0x00008000
> arch/arm/mach-spear6xx/Makefile.boot:      zreladdr-y	:= 0x00008000
> arch/arm/mach-ux500/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-versatile/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-w90x900/Makefile.boot:	   zreladdr-y	:= 0x00008000
> arch/arm/mach-msm/Makefile.boot:	   zreladdr-y	:= 0x10008000
> arch/arm/mach-omap1/Makefile.boot:	   zreladdr-y	:= 0x10008000
> arch/arm/mach-rpc/Makefile.boot:	   zreladdr-y	:= 0x10008000
> arch/arm/mach-s5p6440/Makefile.boot:	   zreladdr-y	:= 0x20008000
> arch/arm/mach-s5p6442/Makefile.boot:	   zreladdr-y	:= 0x20008000
> arch/arm/mach-s5pc100/Makefile.boot:	   zreladdr-y	:= 0x20008000
> arch/arm/mach-s5pv210/Makefile.boot:	   zreladdr-y	:= 0x20008000
> arch/arm/mach-s3c2410/Makefile.boot:	   zreladdr-y	:= 0x30008000
> arch/arm/mach-s3c2410/Makefile.boot:	   zreladdr-y	:= 0x30108000
> arch/arm/mach-stmp378x/Makefile.boot:	   zreladdr-y	:= 0x40008000
> arch/arm/mach-stmp37xx/Makefile.boot:	   zreladdr-y	:= 0x40008000
> arch/arm/mach-s3c64xx/Makefile.boot:	   zreladdr-y	:= 0x50008000
> arch/arm/mach-vexpress/Makefile.boot:	   zreladdr-y	:= 0x60008000
> arch/arm/mach-mx25/Makefile.boot:	   zreladdr-y	:= 0x80008000
> arch/arm/mach-mx3/Makefile.boot:	   zreladdr-y	:= 0x80008000
> arch/arm/mach-netx/Makefile.boot:	   zreladdr-y	:= 0x80008000
> arch/arm/mach-omap2/Makefile.boot:	   zreladdr-y	:= 0x80008000
> arch/arm/mach-pnx4008/Makefile.boot:	   zreladdr-y	:= 0x80008000
> arch/arm/mach-mx5/Makefile.boot:	   zreladdr-y	:= 0x90008000
> arch/arm/mach-mxc91231/Makefile.boot:	   zreladdr-y	:= 0x90008000
> arch/arm/mach-iop32x/Makefile.boot:	   zreladdr-y	:= 0xa0008000
> arch/arm/mach-pxa/Makefile.boot:	   zreladdr-y	:= 0xa0008000
> arch/arm/mach-lh7a40x/Makefile.boot:	   zreladdr-y	:= 0xc0008000
> arch/arm/mach-clps711x/Makefile.boot:	   zreladdr-y	:= 0xc0028000
> arch/arm/mach-aaec2000/Makefile.boot:	   zreladdr-y	:= 0xf0008000
> arch/arm/mach-l7200/Makefile.boot:	   zreladdr-y	:= 0xf0008000
> 
> Depends on other options/macros, but still can be auto calculated by
> masking PC with 0xf000_0000:
> 
> arch/arm/mach-bcmring/Makefile.boot:	   zreladdr-y   := $(CONFIG_BCM_ZRELADDR)
> * refer to arch/arm/configs/bcmring_defconfig:CONFIG_BCM_ZRELADDR=0x8000
> arch/arm/mach-h720x/Makefile.boot:	   zreladdr-$(CONFIG_ARCH_H720X) := 0x40008000
> arch/arm/mach-shmobile/Makefile.boot:	   zreladdr-y   := $(__ZRELADDR)
> * __ZRELADDR depends on CONFIG_MEMORY_START
> arch/arm/configs/ap4evb_defconfig:	CONFIG_MEMORY_START=0x40000000 (SH7372)
> arch/arm/configs/g3evm_defconfig:	CONFIG_MEMORY_START=0x50000000 (SH7367)
> arch/arm/configs/g4evm_defconfig:	CONFIG_MEMORY_START=0x40000000 (SH7377)
> 
> arch/arm/mach-at91/Makefile.boot:	   zreladdr-y	:= 0x70008000 (CONFIG_ARCH_AT91CAP9)
> arch/arm/mach-at91/Makefile.boot:	   zreladdr-y	:= 0x70008000 (CONFIG_ARCH_AT91SAM9G45)
> arch/arm/mach-at91/Makefile.boot:	   zreladdr-y	:= 0x20008000 (CONFIG_ARCH_AT91)
> arch/arm/mach-davinci/Makefile.boot:	   zreladdr-y	:= 0xc0008000 (CONFIG_ARCH_DAVINCI_DA8XX)
> arch/arm/mach-davinci/Makefile.boot:	   zreladdr-y	:= 0x80008000 (!CONFIG_ARCH_DAVINCI_DA8XX)
> arch/arm/mach-ep93xx/Makefile.boot:	   zreladdr-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET)	:= 0x00008000
> arch/arm/mach-ep93xx/Makefile.boot:	   zreladdr-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET)		:= 0xc0008000
> arch/arm/mach-ep93xx/Makefile.boot:	   zreladdr-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET)		:= 0xd0008000
> arch/arm/mach-ep93xx/Makefile.boot:	   zreladdr-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET)		:= 0xe0008000
> arch/arm/mach-ep93xx/Makefile.boot:	   zreladdr-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET)	:= 0xf0008000
> arch/arm/mach-gemini/Makefile.boot:	   zreladdr-y	:= 0x00008000 (CONFIG_GEMINI_MEM_SWAP)
> arch/arm/mach-gemini/Makefile.boot:	   zreladdr-y	:= 0x10008000 (!CONFIG_GEMINI_MEM_SWAP)
> arch/arm/mach-mx2/Makefile.boot:	   zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000
> arch/arm/mach-mx2/Makefile.boot:	   zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
> arch/arm/mach-realview/Makefile.boot:	   zreladdr-y	:= 0x70008000 (CONFIG_REALVIEW_HIGH_PHYS_OFFSET)
> arch/arm/mach-realview/Makefile.boot:	   zreladdr-y	:= 0x00008000 (CONFIG_REALVIEW_HIGH_PHYS_OFFSET)
> arch/arm/mach-sa1100/Makefile.boot:	   zreladdr-y	:= 0xc0008000
> arch/arm/mach-sa1100/Makefile.boot:	   zreladdr-$(CONFIG_SA1111) := 0xc0208000
> 
> Machines where ZRELADDR cannot be auto calcuated:
> 
> arch/arm/mach-mx1/Makefile.boot:	   zreladdr-y	:= 0x08008000
> arch/arm/mach-shark/Makefile.boot:	   zreladdr-y	:= 0x08008000
> arch/arm/mach-u300/Makefile.boot:	   zreladdr-y	:= 0x28E08000
> arch/arm/mach-u300/Makefile.boot:	   zreladdr-y	:= 0x48008000
I care about mx1, so I would prefer using 0xf8000000.

What do you think about requiring r4 to be set to physoffset as I did in
my series?  This way zImage would already know PHYSOFFSET and so didn't
need to guess ZRELADDR.  OK, until most bootloaders are fixed we need
to guess, too.  But at least this would provide a way to stop guessing
wrong for the affected platforms.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From u.kleine-koenig at pengutronix.de  Thu Jun 10 05:01:14 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 10 Jun 2010 11:01:14 +0200
Subject: [PATCH 5/5] [ARM] Move inclusion of Makefile.boot into
	arch/arm/boot/bootp
In-Reply-To: <1275550613-9553-6-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-6-git-send-email-eric.miao@canonical.com>
Message-ID: <20100610090114.GE3422@pengutronix.de>

On Thu, Jun 03, 2010 at 03:36:53PM +0800, Eric Miao wrote:
> From: Eric Miao <eric.y.miao at gmail.com>
> 
> Since zreladdr-y, params_phys-y and initrd_phys-y are no longer
> used in arch/arm/boot/compressed, move the inclusion into bootp/.
> 
> Now unless you are building for an bootpImage, no per machine
> class Makefile.boot needs to be included.
> 
> Signed-off-by: Eric Miao <eric.miao at canonical.com>
Acked-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
>  arch/arm/boot/Makefile       |   21 +--------------------
>  arch/arm/boot/bootp/Makefile |   19 ++++++++++++++++++-
>  2 files changed, 19 insertions(+), 21 deletions(-)
> 
> diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
> index 8cc4669..5e1b5f4 100644
> --- a/arch/arm/boot/Makefile
> +++ b/arch/arm/boot/Makefile
> @@ -13,18 +13,6 @@
>  
>  MKIMAGE         := $(srctree)/scripts/mkuboot.sh
>  
> -ifneq ($(MACHINE),)
> --include $(srctree)/$(MACHINE)/Makefile.boot
> -endif
> -
> -# Note: the following conditions must always be true:
> -#   PARAMS_PHYS must be within 4MB of ZRELADDR
> -#   INITRD_PHYS must be in RAM
> -PARAMS_PHYS := $(params_phys-y)
> -INITRD_PHYS := $(initrd_phys-y)
> -
> -export INITRD_PHYS PARAMS_PHYS
> -
>  targets := Image zImage xipImage bootpImage uImage
>  
>  ifeq ($(CONFIG_XIP_KERNEL),y)
> @@ -81,7 +69,7 @@ $(obj)/uImage:	$(obj)/zImage FORCE
>  	$(call if_changed,uimage)
>  	@echo '  Image $@ is ready'
>  
> -$(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
> +$(obj)/bootp/bootp: $(obj)/zImage FORCE
>  	$(Q)$(MAKE) $(build)=$(obj)/bootp $@
>  	@:
>  
> @@ -89,13 +77,6 @@ $(obj)/bootpImage: $(obj)/bootp/bootp FORCE
>  	$(call if_changed,objcopy)
>  	@echo '  Kernel: $@ is ready'
>  
> -PHONY += initrd FORCE
> -initrd:
> -	@test "$(INITRD_PHYS)" != "" || \
> -	(echo This machine does not support INITRD; exit -1)
> -	@test "$(INITRD)" != "" || \
> -	(echo You must specify INITRD; exit -1)
> -
>  install: $(obj)/Image
>  	$(CONFIG_SHELL) $(srctree)/$(src)/install.sh $(KERNELRELEASE) \
>  	$(obj)/Image System.map "$(INSTALL_PATH)"
> diff --git a/arch/arm/boot/bootp/Makefile b/arch/arm/boot/bootp/Makefile
> index c394e30..4b32d92 100644
> --- a/arch/arm/boot/bootp/Makefile
> +++ b/arch/arm/boot/bootp/Makefile
> @@ -5,6 +5,16 @@
>  # architecture-specific flags and dependencies.
>  #
>  
> +ifneq ($(MACHINE),)
> +-include $(srctree)/$(MACHINE)/Makefile.boot
> +endif
> +
> +# Note: the following conditions must always be true:
> +#   PARAMS_PHYS must be within 4MB of ZRELADDR
> +#   INITRD_PHYS must be in RAM
> +PARAMS_PHYS := $(params_phys-y)
> +INITRD_PHYS := $(initrd_phys-y)
> +
>  LDFLAGS_bootp	:=-p --no-undefined -X \
>  		 --defsym initrd_phys=$(INITRD_PHYS) \
>  		 --defsym params_phys=$(PARAMS_PHYS) -T
> @@ -17,11 +27,18 @@ $(obj)/bootp:	$(src)/bootp.lds $(addprefix $(obj)/,init.o kernel.o initrd.o) FOR
>  	$(call if_changed,ld)
>  	@:
>  
> +PHONY += initrd FORCE
> +initrd:
> +	@test "$(INITRD_PHYS)" != "" || \
> +	(echo This machine does not support INITRD; exit -1)
> +	@test "$(INITRD)" != "" || \
> +	(echo You must specify INITRD; exit -1)
> +
>  # kernel.o and initrd.o includes a binary image using
>  # .incbin, a dependency which is not tracked automatically
>  
>  $(obj)/kernel.o: arch/arm/boot/zImage FORCE
>  
> -$(obj)/initrd.o: $(INITRD) FORCE
> +$(obj)/initrd.o: $(INITRD) initrd FORCE
>  
>  PHONY += $(INITRD) FORCE
> -- 
> 1.7.0.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From baruch at tkos.co.il  Thu Jun 10 05:14:32 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Thu, 10 Jun 2010 12:14:32 +0300
Subject: [PATCH] mx25: add a comment documenting undocumented IPG clocks
Message-ID: <19a61a0788a899caf2be6126769b20bbf662f90a.1276161160.git.baruch@tkos.co.il>

The information in the i.MX25 Reference Manual is lacking. Add information from
the Freescale BSP.

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 arch/arm/mach-mx25/clock.c |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index f9662d9..43d6045 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -166,6 +166,28 @@ static void clk_cgcr_disable(struct clk *clk)
 		.secondary	= s,			\
 	}
 
+/*
+ * Note: the following IPG clock gating bits are wrongly marked "Reserved" in
+ * the i.MX25 Reference Manual Rev 1, table 15-13. The information below is
+ * taken from the Freescale released BSP.
+ *
+ * bit	reg	offset	clock
+ *
+ * 0	CGCR1	0	AUDMUX
+ * 12	CGCR1	12	ESAI
+ * 16	CGCR1	16	GPIO1
+ * 17	CGCR1	17	GPIO2
+ * 18	CGCR1	18	GPIO3
+ * 23	CGCR1	23	I2C1
+ * 24	CGCR1	24	I2C2
+ * 25	CGCR1	25	I2C3
+ * 27	CGCR1	27	IOMUXC
+ * 28	CGCR1	28	KPP
+ * 30	CGCR1	30	OWIRE
+ * 36	CGCR2	4	RTIC
+ * 51	CGCR2	19	WDOG
+ */
+
 DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_gpt, NULL, NULL);
 DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
 DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL, NULL);
-- 
1.7.1



From linux at arm.linux.org.uk  Thu Jun 10 05:16:08 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 10 Jun 2010 10:16:08 +0100
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option
	for exceptions
In-Reply-To: <20100610090015.GD3422@pengutronix.de>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
	<20100610090015.GD3422@pengutronix.de>
Message-ID: <20100610091608.GA28305@n2100.arm.linux.org.uk>

On Thu, Jun 10, 2010 at 11:00:15AM +0200, Uwe Kleine-K?nig wrote:
> What do you think about requiring r4 to be set to physoffset as I did in
> my series?  This way zImage would already know PHYSOFFSET and so didn't
> need to guess ZRELADDR.  OK, until most bootloaders are fixed we need
> to guess, too.  But at least this would provide a way to stop guessing
> wrong for the affected platforms.

That means it won't get implemented.  Look at the facts.  It's taken
_years_ (5+ years) for boot loaders to start passing a value in r1.
We then switched to the ATAG stuff, and it's again taking years for
boot loaders to start passing right ATAG stuff - and most of them don't
get it right.  Eg, lots of uboot are happy to print out the memory
information on the terminal as they start up, but don't pass memory
information to the kernel.

So if we want phys offset in r4, we better realise that it'll take
something like five years of nagging to get it in place, and even then
people will continue to use boot loaders which don't have support.
And if it's only necessary for a handful of platforms, I doubt anyone's
really going to bother - or even validate that r4 is correct.

You have a whole set of other problems - how do you cope with existing
boot loaders which happen to call the kernel with a value in r4 which
_could_ potentially be valid, but should not be used?  At the moment,
r4 could contain _any_ value what so ever.

Let's face it - advertising that "the kernel will eventually start using
r4" doesn't solve the problem either - we did that with the ATAG list
and we know the results from that.

Maybe the right experiment to try this time - if we want r4 to contain
a value - is to say that kernel 2.6.37 will require a value in r4, and
won't boot without it, and will therefore be incompatible with old
boot loaders.


From w.sang at pengutronix.de  Thu Jun 10 05:18:44 2010
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Thu, 10 Jun 2010 11:18:44 +0200
Subject: [PATCH 0/3] MX25 watchdog
In-Reply-To: <cover.1276081393.git.baruch@tkos.co.il>
References: <cover.1276081393.git.baruch@tkos.co.il>
Message-ID: <20100610091844.GF5333@pengutronix.de>

On Wed, Jun 09, 2010 at 02:06:59PM +0300, Baruch Siach wrote:
> This series adds support for the new watchdog driver on the i.MX25 PDK 
> platform. A little fix to the watchdog driver itself is also added.
> 
> Baruch Siach (3):
>   mx25: add watchdog clock
>   mx25pdk: register watchdog device
>   imx2_wdt: fix section mismatch
> 
>  arch/arm/mach-mx25/clock.c        |    2 ++
>  arch/arm/mach-mx25/mach-mx25pdk.c |    1 +
>  drivers/watchdog/imx2_wdt.c       |    1 -
>  3 files changed, 3 insertions(+), 1 deletions(-)

Assuming the fixed register in patch 1, whole series is:

Reviewed-by: Wolfram Sang <w.sang at pengutronix.de>

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From eric.miao at canonical.com  Thu Jun 10 05:18:57 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 10 Jun 2010 17:18:57 +0800
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option for 
	exceptions
In-Reply-To: <20100610090015.GD3422@pengutronix.de>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com> 
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com> 
	<20100610090015.GD3422@pengutronix.de>
Message-ID: <AANLkTin9qGAJGSgu9Y2YjI_W8UwBITd-QYyGERcLLUgP@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> On Thu, Jun 03, 2010 at 03:36:52PM +0800, Eric Miao wrote:
>> From: Eric Miao <eric.y.miao at gmail.com>
>>
>> Original idea and prototype came from Nicolas Pitre.
>>
>> As long as the zImage is placed within the 256MB range from the
>> start of the memory, ZRELADDR (Address where the decompressed
>> kernel will be placed, usually ?== PHYS_OFFSET + TEXT_OFFSET)
> s/ ?/ /
>
>> can be determined at run-time by masking PC with 0xf000_0000.
>>
>> Running through all the Makefile.boot, all those zreladdr-y
>> address == 0x[0-f]000_0000 + TEXT_OFFSET can be determined at
>> run-time.
>>
>> Option CONFIG_AUTO_ZRELADDR and CONFIG_ZRELADDR are introduced,
>> CONFIG_ZRELADDR _must_ be explicitly specified if:
>>
>> ?- ((zreladdr-y - TEXT_OFFSET) & ~0xf0000000) != 0, which means
>> ? ?a maksing of PC with 0xf000_0000 will result an incorrect
> s/maksing of/masking/ (note: there are 2 changes)
>
>> ? ?address.
>>
>> ?- or the assumption of the zImage being loaded by the boot
>> ? ?loader within 256MB from the start address is simply
>> ? ?incorrect
> Hmmm, this makes the image depending on the bootloader. ?Not that nice.

Yes, that's a negative side. And that's why I'm still keeping CONFIG_ZRELADDR
instead of guessing all the time, so platforms where this assumption isn't true
have to build their kernel with this option set correctly.

I've actually discussed this with Nicolas and his opinion is this is some
thing we can afford, e.g. in PC/x86 world, there are already a lot restrictions
on kernel placement.

My original idea is to embed the machine_desc() section into zImage itself
and invent a machine_desc.phys_offset field so that both the zImage header
and the kernel itself will be both happy. There are some patches actually
ready for this, and I can submit them just in case anyone is interested.

>
>> ?- or when ZBOOT_ROM is used, where the above assumption is
>> ? ?normally wrong
> So guess based on sp :-)
>
>> List of all Makefile.boot:
>>
>> Hardcoded, and can be auto calculated by masking PC with 0xf000_0000:
>>
>> arch/arm/mach-cns3xxx/Makefile.boot: ? ? zreladdr-y ? := 0x00008000
>> arch/arm/mach-dove/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x00008000
>> arch/arm/mach-ebsa110/Makefile.boot: ? ? zreladdr-y ? := 0x00008000
>> arch/arm/mach-footbridge/Makefile.boot: ? ? ? ? ?zreladdr-y ? := 0x00008000
>> arch/arm/mach-integrator/Makefile.boot: ? ? ? ? ?zreladdr-y ? := 0x00008000
>> arch/arm/mach-iop13xx/Makefile.boot: ? ? zreladdr-y ? := 0x00008000
>> arch/arm/mach-iop33x/Makefile.boot: ? ? ?zreladdr-y ? := 0x00008000
>> arch/arm/mach-ixp2000/Makefile.boot: ? ? zreladdr-y ? := 0x00008000
>> arch/arm/mach-ixp23xx/Makefile.boot: ? ? zreladdr-y ? := 0x00008000
>> arch/arm/mach-ixp4xx/Makefile.boot: ? ? ?zreladdr-y ? := 0x00008000
>> arch/arm/mach-kirkwood/Makefile.boot: ? ?zreladdr-y ? := 0x00008000
>> arch/arm/mach-ks8695/Makefile.boot: ? ? ?zreladdr-y ? := 0x00008000
>> arch/arm/mach-loki/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x00008000
>> arch/arm/mach-mmp/Makefile.boot: ? ? ? ? zreladdr-y ? := 0x00008000
>> arch/arm/mach-mv78xx0/Makefile.boot: ? ? zreladdr-y ? := 0x00008000
>> arch/arm/mach-nomadik/Makefile.boot: ? ? zreladdr-y ? := 0x00008000
>> arch/arm/mach-nuc93x/Makefile.boot: ? ? ?zreladdr-y ? := 0x00008000
>> arch/arm/mach-ns9xxx/Makefile.boot: ? ? ?zreladdr-y ? := 0x8000
>> arch/arm/mach-orion5x/Makefile.boot: ? ? zreladdr-y ? := 0x00008000
>> arch/arm/mach-spear3xx/Makefile.boot: ? ? ?zreladdr-y := 0x00008000
>> arch/arm/mach-spear6xx/Makefile.boot: ? ? ?zreladdr-y := 0x00008000
>> arch/arm/mach-ux500/Makefile.boot: ? ? ? zreladdr-y ? := 0x00008000
>> arch/arm/mach-versatile/Makefile.boot: ? ? ? ? ? zreladdr-y ? := 0x00008000
>> arch/arm/mach-w90x900/Makefile.boot: ? ? zreladdr-y ? := 0x00008000
>> arch/arm/mach-msm/Makefile.boot: ? ? ? ? zreladdr-y ? := 0x10008000
>> arch/arm/mach-omap1/Makefile.boot: ? ? ? zreladdr-y ? := 0x10008000
>> arch/arm/mach-rpc/Makefile.boot: ? ? ? ? zreladdr-y ? := 0x10008000
>> arch/arm/mach-s5p6440/Makefile.boot: ? ? zreladdr-y ? := 0x20008000
>> arch/arm/mach-s5p6442/Makefile.boot: ? ? zreladdr-y ? := 0x20008000
>> arch/arm/mach-s5pc100/Makefile.boot: ? ? zreladdr-y ? := 0x20008000
>> arch/arm/mach-s5pv210/Makefile.boot: ? ? zreladdr-y ? := 0x20008000
>> arch/arm/mach-s3c2410/Makefile.boot: ? ? zreladdr-y ? := 0x30008000
>> arch/arm/mach-s3c2410/Makefile.boot: ? ? zreladdr-y ? := 0x30108000
>> arch/arm/mach-stmp378x/Makefile.boot: ? ?zreladdr-y ? := 0x40008000
>> arch/arm/mach-stmp37xx/Makefile.boot: ? ?zreladdr-y ? := 0x40008000
>> arch/arm/mach-s3c64xx/Makefile.boot: ? ? zreladdr-y ? := 0x50008000
>> arch/arm/mach-vexpress/Makefile.boot: ? ?zreladdr-y ? := 0x60008000
>> arch/arm/mach-mx25/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x80008000
>> arch/arm/mach-mx3/Makefile.boot: ? ? ? ? zreladdr-y ? := 0x80008000
>> arch/arm/mach-netx/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x80008000
>> arch/arm/mach-omap2/Makefile.boot: ? ? ? zreladdr-y ? := 0x80008000
>> arch/arm/mach-pnx4008/Makefile.boot: ? ? zreladdr-y ? := 0x80008000
>> arch/arm/mach-mx5/Makefile.boot: ? ? ? ? zreladdr-y ? := 0x90008000
>> arch/arm/mach-mxc91231/Makefile.boot: ? ?zreladdr-y ? := 0x90008000
>> arch/arm/mach-iop32x/Makefile.boot: ? ? ?zreladdr-y ? := 0xa0008000
>> arch/arm/mach-pxa/Makefile.boot: ? ? ? ? zreladdr-y ? := 0xa0008000
>> arch/arm/mach-lh7a40x/Makefile.boot: ? ? zreladdr-y ? := 0xc0008000
>> arch/arm/mach-clps711x/Makefile.boot: ? ?zreladdr-y ? := 0xc0028000
>> arch/arm/mach-aaec2000/Makefile.boot: ? ?zreladdr-y ? := 0xf0008000
>> arch/arm/mach-l7200/Makefile.boot: ? ? ? zreladdr-y ? := 0xf0008000
>>
>> Depends on other options/macros, but still can be auto calculated by
>> masking PC with 0xf000_0000:
>>
>> arch/arm/mach-bcmring/Makefile.boot: ? ? zreladdr-y ? := $(CONFIG_BCM_ZRELADDR)
>> * refer to arch/arm/configs/bcmring_defconfig:CONFIG_BCM_ZRELADDR=0x8000
>> arch/arm/mach-h720x/Makefile.boot: ? ? ? zreladdr-$(CONFIG_ARCH_H720X) := 0x40008000
>> arch/arm/mach-shmobile/Makefile.boot: ? ?zreladdr-y ? := $(__ZRELADDR)
>> * __ZRELADDR depends on CONFIG_MEMORY_START
>> arch/arm/configs/ap4evb_defconfig: ? ?CONFIG_MEMORY_START=0x40000000 (SH7372)
>> arch/arm/configs/g3evm_defconfig: ? ? CONFIG_MEMORY_START=0x50000000 (SH7367)
>> arch/arm/configs/g4evm_defconfig: ? ? CONFIG_MEMORY_START=0x40000000 (SH7377)
>>
>> arch/arm/mach-at91/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x70008000 (CONFIG_ARCH_AT91CAP9)
>> arch/arm/mach-at91/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x70008000 (CONFIG_ARCH_AT91SAM9G45)
>> arch/arm/mach-at91/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x20008000 (CONFIG_ARCH_AT91)
>> arch/arm/mach-davinci/Makefile.boot: ? ? zreladdr-y ? := 0xc0008000 (CONFIG_ARCH_DAVINCI_DA8XX)
>> arch/arm/mach-davinci/Makefile.boot: ? ? zreladdr-y ? := 0x80008000 (!CONFIG_ARCH_DAVINCI_DA8XX)
>> arch/arm/mach-ep93xx/Makefile.boot: ? ? ?zreladdr-$(CONFIG_EP93XX_SDCE3_SYNC_PHYS_OFFSET) ? ? := 0x00008000
>> arch/arm/mach-ep93xx/Makefile.boot: ? ? ?zreladdr-$(CONFIG_EP93XX_SDCE0_PHYS_OFFSET) ? ? ? ? ?:= 0xc0008000
>> arch/arm/mach-ep93xx/Makefile.boot: ? ? ?zreladdr-$(CONFIG_EP93XX_SDCE1_PHYS_OFFSET) ? ? ? ? ?:= 0xd0008000
>> arch/arm/mach-ep93xx/Makefile.boot: ? ? ?zreladdr-$(CONFIG_EP93XX_SDCE2_PHYS_OFFSET) ? ? ? ? ?:= 0xe0008000
>> arch/arm/mach-ep93xx/Makefile.boot: ? ? ?zreladdr-$(CONFIG_EP93XX_SDCE3_ASYNC_PHYS_OFFSET) ? ?:= 0xf0008000
>> arch/arm/mach-gemini/Makefile.boot: ? ? ?zreladdr-y ? := 0x00008000 (CONFIG_GEMINI_MEM_SWAP)
>> arch/arm/mach-gemini/Makefile.boot: ? ? ?zreladdr-y ? := 0x10008000 (!CONFIG_GEMINI_MEM_SWAP)
>> arch/arm/mach-mx2/Makefile.boot: ? ? ? ? zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000
>> arch/arm/mach-mx2/Makefile.boot: ? ? ? ? zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
>> arch/arm/mach-realview/Makefile.boot: ? ?zreladdr-y ? := 0x70008000 (CONFIG_REALVIEW_HIGH_PHYS_OFFSET)
>> arch/arm/mach-realview/Makefile.boot: ? ?zreladdr-y ? := 0x00008000 (CONFIG_REALVIEW_HIGH_PHYS_OFFSET)
>> arch/arm/mach-sa1100/Makefile.boot: ? ? ?zreladdr-y ? := 0xc0008000
>> arch/arm/mach-sa1100/Makefile.boot: ? ? ?zreladdr-$(CONFIG_SA1111) := 0xc0208000
>>
>> Machines where ZRELADDR cannot be auto calcuated:
>>
>> arch/arm/mach-mx1/Makefile.boot: ? ? ? ? zreladdr-y ? := 0x08008000
>> arch/arm/mach-shark/Makefile.boot: ? ? ? zreladdr-y ? := 0x08008000
>> arch/arm/mach-u300/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x28E08000
>> arch/arm/mach-u300/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x48008000
> I care about mx1, so I would prefer using 0xf8000000.

Fair enough actually. And my guess of the u300 architecture is the phys
offset actually starts from 0x2800_0000 or 0x4800_0000 which is also
covered by 0xf800_0000. And I think u300 can actually get rid of those
inconsistent addresses by other means though we all know it might be
suffering from the communication processor side of the memory allocation.

>
> What do you think about requiring r4 to be set to physoffset as I did in
> my series?

My only concern is to impose less restrictions on the boot loaders.
And zImage is only one of the possible headers we may have:

 * vmlinux can actually directly booted into as long as it's placed at the
   right place
 * uImage, with zImage or vmlinux (raw or compressed) encapsulated
 * zImage
 * xipImage
 * bootpImage

I'd really like to separate the guess work into two parts so they don't
have dependencies.

> This way zImage would already know PHYSOFFSET and so didn't
> need to guess ZRELADDR. ?OK, until most bootloaders are fixed we need
> to guess, too. ?But at least this would provide a way to stop guessing
> wrong for the affected platforms.
>


From w.sang at pengutronix.de  Thu Jun 10 05:22:32 2010
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Thu, 10 Jun 2010 11:22:32 +0200
Subject: [PATCH] mx25: add a comment documenting undocumented IPG clocks
In-Reply-To: <19a61a0788a899caf2be6126769b20bbf662f90a.1276161160.git.baruch@tkos.co.il>
References: <19a61a0788a899caf2be6126769b20bbf662f90a.1276161160.git.baruch@tkos.co.il>
Message-ID: <20100610092232.GG5333@pengutronix.de>

On Thu, Jun 10, 2010 at 12:14:32PM +0300, Baruch Siach wrote:
> The information in the i.MX25 Reference Manual is lacking. Add information from
> the Freescale BSP.
> 
> Signed-off-by: Baruch Siach <baruch at tkos.co.il>

Acked-by: Wolfram Sang <w.sang at pengutronix.de> 

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From kgene.kim at samsung.com  Thu Jun 10 05:18:36 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 10 Jun 2010 18:18:36 +0900
Subject: [PATCH] ARM: SAMSUNG: Fix on wrong function name for S5PV210 sdhci0
Message-ID: <1276161516-17480-1-git-send-email-kgene.kim@samsung.com>

From: Lee Hyuk <hyuk1.lee at samsung.com>

This patch fixes on wrong function name in include/plat/sdhci.h for Samsung.
The 's5pc100_default_sdhci0()' function should be chnaged to
's5pv210_default_sdhci0()'. Because 's5pv210_default_sdhci0()' must be pair.

Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/plat-samsung/include/plat/sdhci.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 13f9fb2..98ebd50 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -239,7 +239,7 @@ static inline void s5pv210_default_sdhci0(void)
 	s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
 }
 #else
-static inline void s5pc100_default_sdhci0(void) { }
+static inline void s5pv210_default_sdhci0(void) { }
 #endif /* CONFIG_S3C_DEV_HSMMC */
 
 #ifdef CONFIG_S3C_DEV_HSMMC1
-- 
1.6.2.5



From kgene.kim at samsung.com  Thu Jun 10 05:21:49 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 10 Jun 2010 18:21:49 +0900
Subject: [PATCH] ARM: Add support HSMMC on Samsung SMDKV210
Message-ID: <1276161711-17523-1-git-send-email-kgene.kim@samsung.com>

This patches add support HSMMC for S5PV210.

[PATCH 1/2] ARM: SAMSUNG: Add device definition for HSMMC3
[PATCH 2/2] ARM: S5PV210: Add support HSMMC on Samsung SMDKV210


From kgene.kim at samsung.com  Thu Jun 10 05:21:51 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 10 Jun 2010 18:21:51 +0900
Subject: [PATCH 2/2] ARM: S5PV210: Add support HSMMC on Samsung SMDKV210
In-Reply-To: <1276161711-17523-1-git-send-email-kgene.kim@samsung.com>
References: <1276161711-17523-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1276161711-17523-3-git-send-email-kgene.kim@samsung.com>

From: Lee Hyuk <hyuk1.lee at samsung.com>

This patch adds support HSMMC on Samsung SMDKV210, and gpio configuration for
S5PV210 hsmmc3.

Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pv210/Kconfig            |    5 +++++
 arch/arm/mach-s5pv210/include/mach/map.h |    1 +
 arch/arm/mach-s5pv210/mach-smdkv210.c    |    4 ++++
 arch/arm/mach-s5pv210/setup-sdhci-gpio.c |   20 ++++++++++++++++++++
 4 files changed, 30 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0761eac..6aee967 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -72,9 +72,14 @@ config MACH_SMDKV210
 	select CPU_S5PV210
 	select ARCH_SPARSEMEM_ENABLE
 	select SAMSUNG_DEV_ADC
+	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC1
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
 	select SAMSUNG_DEV_TS
 	select S3C_DEV_WDT
 	select HAVE_S3C2410_WATCHDOG
+	select S5PV210_SETUP_SDHCI
 	help
 	  Machine support for Samsung SMDKV210
 
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 34eb168..fa9d7c2 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -97,6 +97,7 @@
 #define S3C_PA_HSMMC0		S5PV210_PA_HSMMC(0)
 #define S3C_PA_HSMMC1		S5PV210_PA_HSMMC(1)
 #define S3C_PA_HSMMC2		S5PV210_PA_HSMMC(2)
+#define S3C_PA_HSMMC3		S5PV210_PA_HSMMC(3)
 #define S3C_PA_IIC		S5PV210_PA_IIC0
 #define S3C_PA_IIC1		S5PV210_PA_IIC1
 #define S3C_PA_IIC2		S5PV210_PA_IIC2
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 0d46279..b08f376 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -77,6 +77,10 @@ static struct platform_device *smdkv210_devices[] __initdata = {
 	&s5pv210_device_iis0,
 	&s5pv210_device_ac97,
 	&s3c_device_adc,
+	&s3c_device_hsmmc0,
+	&s3c_device_hsmmc1,
+	&s3c_device_hsmmc2,
+	&s3c_device_hsmmc3,
 	&s3c_device_ts,
 	&s3c_device_wdt,
 };
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
index fe7d86d..415f62c 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
@@ -102,3 +102,23 @@ void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 	s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
 	s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
 }
+
+void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+
+	/* Set all the necessary GPG1[0:2] pins to special-function 2 */
+	for (gpio = S5PV210_GPG3(0); gpio < S5PV210_GPG3(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* Data pin GPG1[3:6] to special-function 2 */
+	for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PV210_GPG3(2), S3C_GPIO_SFN(2));
+}
-- 
1.6.2.5



From kgene.kim at samsung.com  Thu Jun 10 05:21:50 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 10 Jun 2010 18:21:50 +0900
Subject: [PATCH 1/2] ARM: SAMSUNG: Add device definition for HSMMC3
In-Reply-To: <1276161711-17523-1-git-send-email-kgene.kim@samsung.com>
References: <1276161711-17523-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1276161711-17523-2-git-send-email-kgene.kim@samsung.com>

From: Lee Hyuk <hyuk1.lee at samsung.com>

This patch adds hsmmc3 device definition in plat-samsung. Because now S5PV210
can support 4 hsmmc, and that can be used in further Samsung SoCs.

Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/plat-samsung/Kconfig              |    5 ++
 arch/arm/plat-samsung/Makefile             |    1 +
 arch/arm/plat-samsung/dev-hsmmc3.c         |   72 ++++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h  |    1 +
 arch/arm/plat-samsung/include/plat/sdhci.h |   15 ++++++
 5 files changed, 94 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-samsung/dev-hsmmc3.c

diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 2753fb3..8efb012 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -160,6 +160,11 @@ config S3C_DEV_HSMMC2
 	help
 	  Compile in platform device definitions for HSMMC channel 2
 
+config S3C_DEV_HSMMC3
+	bool
+	help
+	  Compile in platform device definitions for HSMMC channel 3
+
 config S3C_DEV_HWMON
 	bool
 	help
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index b1d82cc..c9abae5 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_S3C_ADC)	+= adc.o
 obj-$(CONFIG_S3C_DEV_HSMMC)	+= dev-hsmmc.o
 obj-$(CONFIG_S3C_DEV_HSMMC1)	+= dev-hsmmc1.o
 obj-$(CONFIG_S3C_DEV_HSMMC2)	+= dev-hsmmc2.o
+obj-$(CONFIG_S3C_DEV_HSMMC3)	+= dev-hsmmc3.o
 obj-$(CONFIG_S3C_DEV_HWMON)	+= dev-hwmon.o
 obj-y				+= dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)	+= dev-i2c1.o
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c
new file mode 100644
index 0000000..05d5ea4
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-hsmmc3.c
@@ -0,0 +1,72 @@
+/* linux/arch/arm/plat-samsung/dev-hsmmc3.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *	Ben Dooks <ben at simtec.co.uk>
+ *	http://armlinux.simtec.co.uk/
+ *
+ * Based on arch/arm/plat-samsung/dev-hsmmc1.c
+ *
+ * S3C series device definition for hsmmc device 3
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+
+#include <mach/map.h>
+#include <plat/sdhci.h>
+#include <plat/devs.h>
+
+#define S3C_SZ_HSMMC	(0x1000)
+
+static struct resource s3c_hsmmc3_resource[] = {
+	[0] = {
+		.start = S3C_PA_HSMMC3,
+		.end   = S3C_PA_HSMMC3 + S3C_SZ_HSMMC - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_MMC3,
+		.end   = IRQ_MMC3,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+
+static u64 s3c_device_hsmmc3_dmamask = 0xffffffffUL;
+
+struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
+	.max_width	= 4,
+	.host_caps	= (MMC_CAP_4_BIT_DATA |
+			   MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+};
+
+struct platform_device s3c_device_hsmmc3 = {
+	.name		= "s3c-sdhci",
+	.id		= 3,
+	.num_resources	= ARRAY_SIZE(s3c_hsmmc3_resource),
+	.resource	= s3c_hsmmc3_resource,
+	.dev		= {
+		.dma_mask		= &s3c_device_hsmmc3_dmamask,
+		.coherent_dma_mask	= 0xffffffffUL,
+		.platform_data		= &s3c_hsmmc3_def_platdata,
+	},
+};
+
+void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
+{
+	struct s3c_sdhci_platdata *set = &s3c_hsmmc3_def_platdata;
+
+	set->max_width = pd->max_width;
+
+	if (pd->cfg_gpio)
+		set->cfg_gpio = pd->cfg_gpio;
+	if (pd->cfg_card)
+		set->cfg_card = pd->cfg_card;
+}
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index e6144e4..7842acd 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -54,6 +54,7 @@ extern struct platform_device s3c_device_hwmon;
 extern struct platform_device s3c_device_hsmmc0;
 extern struct platform_device s3c_device_hsmmc1;
 extern struct platform_device s3c_device_hsmmc2;
+extern struct platform_device s3c_device_hsmmc3;
 
 extern struct platform_device s3c_device_spi0;
 extern struct platform_device s3c_device_spi1;
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 98ebd50..1314ffa 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -58,6 +58,7 @@ struct s3c_sdhci_platdata {
 extern void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd);
 extern void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd);
 extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd);
+extern void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd);
 
 /* Default platform data, exported so that per-cpu initialisation can
  * set the correct one when there are more than one cpu type selected.
@@ -66,6 +67,7 @@ extern void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd);
 extern struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata;
 extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
 extern struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata;
+extern struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata;
 
 /* Helper function availablity */
 
@@ -78,6 +80,7 @@ extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
 
 /* S3C6400 SDHCI setup */
 
@@ -264,10 +267,22 @@ static inline void s5pv210_default_sdhci2(void)
 static inline void s5pv210_default_sdhci2(void) { }
 #endif /* CONFIG_S3C_DEV_HSMMC2 */
 
+#ifdef CONFIG_S3C_DEV_HSMMC3
+static inline void s5pv210_default_sdhci3(void)
+{
+	s3c_hsmmc3_def_platdata.clocks = s5pv210_hsmmc_clksrcs;
+	s3c_hsmmc3_def_platdata.cfg_gpio = s5pv210_setup_sdhci3_cfg_gpio;
+	s3c_hsmmc3_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card;
+}
+#else
+static inline void s5pv210_default_sdhci3(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC3 */
+
 #else
 static inline void s5pv210_default_sdhci0(void) { }
 static inline void s5pv210_default_sdhci1(void) { }
 static inline void s5pv210_default_sdhci2(void) { }
+static inline void s5pv210_default_sdhci3(void) { }
 #endif /* CONFIG_S5PC100_SETUP_SDHCI */
 
 
-- 
1.6.2.5



From baruch at tkos.co.il  Thu Jun 10 05:32:15 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Thu, 10 Jun 2010 12:32:15 +0300
Subject: [PATCH] mx25: add watchdog clock
In-Reply-To: <20100610081042.GB5333@pengutronix.de>
References: <20100610081042.GB5333@pengutronix.de>
Message-ID: <943ad2932e83e0734e445d0258dd1efa4a60f44b.1276162295.git.baruch@tkos.co.il>

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 arch/arm/mach-mx25/clock.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 1550149..6342840 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -191,6 +191,7 @@ DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
 DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
 DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
+DEFINE_CLOCK(wdt_clk,    0, CCM_CGCR2, 19, get_rate_ipg, NULL,  NULL);
 
 #define _REGISTER_CLOCK(d, n, c)	\
 	{				\
@@ -225,6 +226,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("fec.0", NULL, fec_clk)
 	_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
 	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+	_REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk)
 };
 
 int __init mx25_clocks_init(void)
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 10 05:35:54 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 10 Jun 2010 11:35:54 +0200
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option
	for exceptions
In-Reply-To: <20100610091608.GA28305@n2100.arm.linux.org.uk>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
	<20100610090015.GD3422@pengutronix.de>
	<20100610091608.GA28305@n2100.arm.linux.org.uk>
Message-ID: <20100610093554.GF3422@pengutronix.de>

Hello Russell,

On Thu, Jun 10, 2010 at 10:16:08AM +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 10, 2010 at 11:00:15AM +0200, Uwe Kleine-K?nig wrote:
> > What do you think about requiring r4 to be set to physoffset as I did in
> > my series?  This way zImage would already know PHYSOFFSET and so didn't
> > need to guess ZRELADDR.  OK, until most bootloaders are fixed we need
> > to guess, too.  But at least this would provide a way to stop guessing
> > wrong for the affected platforms.
> 
> That means it won't get implemented.  Look at the facts.  It's taken
> _years_ (5+ years) for boot loaders to start passing a value in r1.
> We then switched to the ATAG stuff, and it's again taking years for
> boot loaders to start passing right ATAG stuff - and most of them don't
> get it right.  Eg, lots of uboot are happy to print out the memory
> information on the terminal as they start up, but don't pass memory
> information to the kernel.
> 
> So if we want phys offset in r4, we better realise that it'll take
> something like five years of nagging to get it in place, and even then
> people will continue to use boot loaders which don't have support.
> And if it's only necessary for a handful of platforms, I doubt anyone's
> really going to bother - or even validate that r4 is correct.
> 
> You have a whole set of other problems - how do you cope with existing
> boot loaders which happen to call the kernel with a value in r4 which
> _could_ potentially be valid, but should not be used?  At the moment,
> r4 could contain _any_ value what so ever.
> 
> Let's face it - advertising that "the kernel will eventually start using
> r4" doesn't solve the problem either - we did that with the ATAG list
> and we know the results from that.
> 
> Maybe the right experiment to try this time - if we want r4 to contain
> a value - is to say that kernel 2.6.37 will require a value in r4, and
> won't boot without it, and will therefore be incompatible with old
> boot loaders.
I agree with you.  Either we need to completly break bootloaders that
don't pass the right value or it should work without new requirements
for most machines.
For the machines that fail to guess correctly IMHO the better approach
is to let the bootloader pass the information instead of letting the
user guess the right value.  Maybe this is because I work for a company
that usually sells support for both bootloader and kernel.  The people
that don't want/cannot to touch their bootloader might have a different
mileage.

And note we could implement both ways (if provided via .config use this
value otherwise use r4 if it looks valid else guess).  If we choose that
all values in r4 look valid we have the needed breakage :-)

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From jgarzik at pobox.com  Thu Jun 10 05:37:53 2010
From: jgarzik at pobox.com (Jeff Garzik)
Date: Thu, 10 Jun 2010 05:37:53 -0400
Subject: [PATCH v3] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <20100610085639.GU7248@trinity.fluff.org>
References: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
	<4C10A7B7.4090601@pobox.com>
	<20100610085639.GU7248@trinity.fluff.org>
Message-ID: <4C10B271.6040908@pobox.com>

On 06/10/2010 04:56 AM, Ben Dooks wrote:
> On Thu, Jun 10, 2010 at 04:52:07AM -0400, Jeff Garzik wrote:
>> On 06/10/2010 03:50 AM, Kukjin Kim wrote:
>>> From: Abhilash Kesavan<a.kesavan at samsung.com>
>>>
>>> Adds support for the Samsung PATA controller. This driver is based on the
>>> Libata subsystem and references the earlier patches sent for IDE subsystem.
>>>
>>> Signed-off-by: Abhilash Kesavan<a.kesavan at samsung.com>
>>> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
>>> ---
>>>
>>> Changes since v2:
>>> - Changed the DRV_NAME to pata_samsung_cf
>>> - Used msleep instead of mdelay
>>>
>>>    drivers/ata/Makefile          |    1 +
>>>    drivers/ata/pata_samsung_cf.c |  608 +++++++++++++++++++++++++++++++++++++++++
>>>    3 files changed, 618 insertions(+), 0 deletions(-)
>>>    create mode 100644 drivers/ata/pata_samsung_cf.c
>>
>> Acked-by: Jeff Garzik<jgarzik at redhat.com>
>>
>>
>> I presume you'll send this upstream via the appropriate ARM tree.
>
> It depends on whether Linus un-declares his current suspensio nof
> ARM based work. The machine updtaes should go via the samsung tree
> but whether to send the driver that was is another matter (I prefer
> to have drivers go via the driver's tree to avoid clashes in
> Makefile and Kconfig).

I don't mind merging it, but usually platform drivers do not build 
and/or work without additional platform glue.  Isn't that the case here?


> PS, what's your policy on -rc inclusion of completely new code
> such as this?

New drivers are fine (which is standard policy outside libata, too), as 
they will not cause regressions, and will enable new users.

	Jeff





From eric.y.miao at gmail.com  Thu Jun 10 05:38:27 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Thu, 10 Jun 2010 17:38:27 +0800
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option for 
	exceptions
In-Reply-To: <20100610091608.GA28305@n2100.arm.linux.org.uk>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com> 
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com> 
	<20100610090015.GD3422@pengutronix.de>
	<20100610091608.GA28305@n2100.arm.linux.org.uk>
Message-ID: <AANLkTilOaHD12oxQZNaWJzKw1gcoT-1LTzpEtULUSLU4@mail.gmail.com>

2010/6/10 Russell King - ARM Linux <linux at arm.linux.org.uk>:
> On Thu, Jun 10, 2010 at 11:00:15AM +0200, Uwe Kleine-K?nig wrote:
>> What do you think about requiring r4 to be set to physoffset as I did in
>> my series? ?This way zImage would already know PHYSOFFSET and so didn't
>> need to guess ZRELADDR. ?OK, until most bootloaders are fixed we need
>> to guess, too. ?But at least this would provide a way to stop guessing
>> wrong for the affected platforms.
>
> That means it won't get implemented. ?Look at the facts. ?It's taken
> _years_ (5+ years) for boot loaders to start passing a value in r1.
> We then switched to the ATAG stuff, and it's again taking years for
> boot loaders to start passing right ATAG stuff - and most of them don't
> get it right. ?Eg, lots of uboot are happy to print out the memory
> information on the terminal as they start up, but don't pass memory
> information to the kernel.
>
> So if we want phys offset in r4, we better realise that it'll take
> something like five years of nagging to get it in place, and even then
> people will continue to use boot loaders which don't have support.
> And if it's only necessary for a handful of platforms, I doubt anyone's
> really going to bother - or even validate that r4 is correct.
>
> You have a whole set of other problems - how do you cope with existing
> boot loaders which happen to call the kernel with a value in r4 which
> _could_ potentially be valid, but should not be used? ?At the moment,
> r4 could contain _any_ value what so ever.
>
> Let's face it - advertising that "the kernel will eventually start using
> r4" doesn't solve the problem either - we did that with the ATAG list
> and we know the results from that.
>
> Maybe the right experiment to try this time - if we want r4 to contain
> a value - is to say that kernel 2.6.37 will require a value in r4, and
> won't boot without it, and will therefore be incompatible with old
> boot loaders.
>

It might be difficult to guess if it's a correct value in r4 and we might
not need it. We know which boards can be compiled together and
the phys_offset can be guessed and we make a single kernel for them,
otherwise we end up building a specific kernel. Although my observation
is that most platforms can guess phys_offset automatically, but due to
the fact there are so many ARM variants out there, and each is doing
things differently, what we can do now is to provide both choices.

And you reminded me that it might be better if we can make RUNTIME_PHYS_OFFSET
depends on the architecture this is test-proofed, so when the day that

RUNTIME_PHYS_OFFSET
        depends on {ALL_ARCH}

happens we can just simplify the mess a bit.


From u.kleine-koenig at pengutronix.de  Thu Jun 10 05:43:10 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 10 Jun 2010 11:43:10 +0200
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option
	for exceptions
In-Reply-To: <AANLkTilOaHD12oxQZNaWJzKw1gcoT-1LTzpEtULUSLU4@mail.gmail.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
	<20100610090015.GD3422@pengutronix.de>
	<20100610091608.GA28305@n2100.arm.linux.org.uk>
	<AANLkTilOaHD12oxQZNaWJzKw1gcoT-1LTzpEtULUSLU4@mail.gmail.com>
Message-ID: <20100610094310.GG3422@pengutronix.de>

On Thu, Jun 10, 2010 at 05:38:27PM +0800, Eric Miao wrote:
> 2010/6/10 Russell King - ARM Linux <linux at arm.linux.org.uk>:
> > On Thu, Jun 10, 2010 at 11:00:15AM +0200, Uwe Kleine-K?nig wrote:
> >> What do you think about requiring r4 to be set to physoffset as I did in
> >> my series? ?This way zImage would already know PHYSOFFSET and so didn't
> >> need to guess ZRELADDR. ?OK, until most bootloaders are fixed we need
> >> to guess, too. ?But at least this would provide a way to stop guessing
> >> wrong for the affected platforms.
> >
> > That means it won't get implemented. ?Look at the facts. ?It's taken
> > _years_ (5+ years) for boot loaders to start passing a value in r1.
> > We then switched to the ATAG stuff, and it's again taking years for
> > boot loaders to start passing right ATAG stuff - and most of them don't
> > get it right. ?Eg, lots of uboot are happy to print out the memory
> > information on the terminal as they start up, but don't pass memory
> > information to the kernel.
> >
> > So if we want phys offset in r4, we better realise that it'll take
> > something like five years of nagging to get it in place, and even then
> > people will continue to use boot loaders which don't have support.
> > And if it's only necessary for a handful of platforms, I doubt anyone's
> > really going to bother - or even validate that r4 is correct.
> >
> > You have a whole set of other problems - how do you cope with existing
> > boot loaders which happen to call the kernel with a value in r4 which
> > _could_ potentially be valid, but should not be used? ?At the moment,
> > r4 could contain _any_ value what so ever.
> >
> > Let's face it - advertising that "the kernel will eventually start using
> > r4" doesn't solve the problem either - we did that with the ATAG list
> > and we know the results from that.
> >
> > Maybe the right experiment to try this time - if we want r4 to contain
> > a value - is to say that kernel 2.6.37 will require a value in r4, and
> > won't boot without it, and will therefore be incompatible with old
> > boot loaders.
> >
> 
> It might be difficult to guess if it's a correct value in r4 and we might
> not need it. We know which boards can be compiled together and
> the phys_offset can be guessed and we make a single kernel for them,
> otherwise we end up building a specific kernel. Although my observation
> is that most platforms can guess phys_offset automatically, but due to
> the fact there are so many ARM variants out there, and each is doing
> things differently, what we can do now is to provide both choices.
> 
> And you reminded me that it might be better if we can make RUNTIME_PHYS_OFFSET
> depends on the architecture this is test-proofed, so when the day that
> 
> RUNTIME_PHYS_OFFSET
>         depends on {ALL_ARCH}
I would prefer

	config HAVE_RUNTIME_PHYS_OFFSET
		bool

	config RUNTIME_PHYS_OFFSET
		depens on HAVE_RUNTIME_PHYS_OFFSET

	config ARCH_FOO
		select HAVE_RUNTIME_PHYS_OFFSET

for the usual reasons.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From eric.miao at canonical.com  Thu Jun 10 05:45:53 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 10 Jun 2010 17:45:53 +0800
Subject: [PATCH 3/5] [ARM] Make TEXT_OFFSET a configurable option
In-Reply-To: <20100610085053.GC3422@pengutronix.de>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com> 
	<1275550613-9553-4-git-send-email-eric.miao@canonical.com> 
	<20100610085053.GC3422@pengutronix.de>
Message-ID: <AANLkTilNMqC0q65GzRiyyX091390TaHFD7ffaxkWWyf8@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> On Thu, Jun 03, 2010 at 03:36:51PM +0800, Eric Miao wrote:
>> From: Eric Miao <eric.y.miao at gmail.com>
>>
>> Signed-off-by: Eric Miao <eric.miao at canonical.com>
>> ---
>> ?arch/arm/Kconfig ? ? ? ? | ? 13 +++++++++++++
>> ?arch/arm/Makefile ? ? ? ?| ? 13 +------------
>> ?arch/arm/kernel/Makefile | ? ?4 ++--
>> ?3 files changed, 16 insertions(+), 14 deletions(-)
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index 1f254bd..e340193 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -1484,6 +1484,19 @@ config ATAGS_PROC
>> ? ? ? ? Should the atags used to boot the kernel be exported in an "atags"
>> ? ? ? ? file in procfs. Useful with kexec.
>>
>> +config TEXT_OFFSET
>> + ? ? hex "Offset of the kernel image from the start of RAM"
> IMHO this should not be user configurable.
>

That's true. The reason I don't want to keep this in Makefile is the
concern about future change to Makefile (that machine-y could be
composed of all the mach-*), and make it a kernel config option at
least provide a way to fix that by the user interactively.

>>

... snip

>> -CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(TEXT_OFFSET)
>> -AFLAGS_head.o ? ? ? ?:= -DTEXT_OFFSET=$(TEXT_OFFSET)
>> +CPPFLAGS_vmlinux.lds := -DTEXT_OFFSET=$(CONFIG_TEXT_OFFSET)
>> +AFLAGS_head.o ? ? ? ?:= -DTEXT_OFFSET=$(CONFIG_TEXT_OFFSET)
> Why not use CONFIG_TEXT_OFFSET directly in head.S?
> Is CONFIG_TEXT_OFFSET available in vmlinux.lds?

I think so, and I'm fine to either way.


From eric.y.miao at gmail.com  Thu Jun 10 05:47:25 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Thu, 10 Jun 2010 17:47:25 +0800
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option for 
	exceptions
In-Reply-To: <20100610094310.GG3422@pengutronix.de>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com> 
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com> 
	<20100610090015.GD3422@pengutronix.de>
	<20100610091608.GA28305@n2100.arm.linux.org.uk> 
	<AANLkTilOaHD12oxQZNaWJzKw1gcoT-1LTzpEtULUSLU4@mail.gmail.com> 
	<20100610094310.GG3422@pengutronix.de>
Message-ID: <AANLkTinzvZtYa2KhbR0lF5GUB7ramRbBQsE3nYjiiucI@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> On Thu, Jun 10, 2010 at 05:38:27PM +0800, Eric Miao wrote:
>> 2010/6/10 Russell King - ARM Linux <linux at arm.linux.org.uk>:
>> > On Thu, Jun 10, 2010 at 11:00:15AM +0200, Uwe Kleine-K?nig wrote:
>> >> What do you think about requiring r4 to be set to physoffset as I did in
>> >> my series? ?This way zImage would already know PHYSOFFSET and so didn't
>> >> need to guess ZRELADDR. ?OK, until most bootloaders are fixed we need
>> >> to guess, too. ?But at least this would provide a way to stop guessing
>> >> wrong for the affected platforms.
>> >
>> > That means it won't get implemented. ?Look at the facts. ?It's taken
>> > _years_ (5+ years) for boot loaders to start passing a value in r1.
>> > We then switched to the ATAG stuff, and it's again taking years for
>> > boot loaders to start passing right ATAG stuff - and most of them don't
>> > get it right. ?Eg, lots of uboot are happy to print out the memory
>> > information on the terminal as they start up, but don't pass memory
>> > information to the kernel.
>> >
>> > So if we want phys offset in r4, we better realise that it'll take
>> > something like five years of nagging to get it in place, and even then
>> > people will continue to use boot loaders which don't have support.
>> > And if it's only necessary for a handful of platforms, I doubt anyone's
>> > really going to bother - or even validate that r4 is correct.
>> >
>> > You have a whole set of other problems - how do you cope with existing
>> > boot loaders which happen to call the kernel with a value in r4 which
>> > _could_ potentially be valid, but should not be used? ?At the moment,
>> > r4 could contain _any_ value what so ever.
>> >
>> > Let's face it - advertising that "the kernel will eventually start using
>> > r4" doesn't solve the problem either - we did that with the ATAG list
>> > and we know the results from that.
>> >
>> > Maybe the right experiment to try this time - if we want r4 to contain
>> > a value - is to say that kernel 2.6.37 will require a value in r4, and
>> > won't boot without it, and will therefore be incompatible with old
>> > boot loaders.
>> >
>>
>> It might be difficult to guess if it's a correct value in r4 and we might
>> not need it. We know which boards can be compiled together and
>> the phys_offset can be guessed and we make a single kernel for them,
>> otherwise we end up building a specific kernel. Although my observation
>> is that most platforms can guess phys_offset automatically, but due to
>> the fact there are so many ARM variants out there, and each is doing
>> things differently, what we can do now is to provide both choices.
>>
>> And you reminded me that it might be better if we can make RUNTIME_PHYS_OFFSET
>> depends on the architecture this is test-proofed, so when the day that
>>
>> RUNTIME_PHYS_OFFSET
>> ? ? ? ? depends on {ALL_ARCH}
> I would prefer
>
> ? ? ? ?config HAVE_RUNTIME_PHYS_OFFSET
> ? ? ? ? ? ? ? ?bool
>
> ? ? ? ?config RUNTIME_PHYS_OFFSET
> ? ? ? ? ? ? ? ?depens on HAVE_RUNTIME_PHYS_OFFSET
>
> ? ? ? ?config ARCH_FOO
> ? ? ? ? ? ? ? ?select HAVE_RUNTIME_PHYS_OFFSET
>
> for the usual reasons.
>

That's a good way to go.


From eric.miao at canonical.com  Thu Jun 10 05:55:10 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 10 Jun 2010 17:55:10 +0800
Subject: [PATCH 2/5] [ARM] Remove unused INITRD_PHYS from 
	arch/arm/boot/compressed
In-Reply-To: <20100610082716.GA3422@pengutronix.de>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com> 
	<1275550613-9553-3-git-send-email-eric.miao@canonical.com> 
	<20100610082716.GA3422@pengutronix.de>
Message-ID: <AANLkTinTbYyoMzQ8hgNPL9UF_7XSMxTJkICO8zVsCcm9@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> Hello,
>
> On Thu, Jun 03, 2010 at 03:36:50PM +0800, Eric Miao wrote:
>> From: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
>>
>> Original patch from Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>.
>>
>> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
>> Signed-off-by: Eric Miao <eric.miao at canonical.com>
> The patch is OK, but the commit log of my patch was (IMHO) better.
> Something like:
>
> Only arch/arm/boot/bootp/init.S uses initrd_phys, so there is no need to
> pass it in arch/arm/boot/compressed.
>

OK.

> And I would prefer not to have this "Original patch from ..." in the
> commit log. ?Do you use it because the patch system doesn't offer to
> specify the author of a commit?

It's actually a common practice by many other who I cannot remember.
But yeah, it's there because I need to remind me it's not my patch and
don't get the author wrong :-)


From rabin.vincent at stericsson.com  Thu Jun 10 05:55:59 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Thu, 10 Jun 2010 15:25:59 +0530
Subject: [PATCH 1/3] nomadik-gpio: implement set_wake
Message-ID: <1276163761-28342-1-git-send-email-rabin.vincent@stericsson.com>

So that set_irq_wake() works.

Cc: Alessandro Rubini <rubini at unipv.it>
Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 arch/arm/plat-nomadik/gpio.c |   53 ++++++++++++++++++++++++++++++-----------
 1 files changed, 39 insertions(+), 14 deletions(-)

diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 12d1c7c..a98f618 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -301,32 +301,41 @@ static void nmk_gpio_irq_ack(unsigned int irq)
 	writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
 }
 
+enum nmk_gpio_irq_type {
+	NORMAL,
+	WAKE,
+};
+
 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
-				  int gpio, bool enable)
+				  int gpio, enum nmk_gpio_irq_type which,
+				  bool enable)
 {
+	u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC;
+	u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC;
 	u32 bitmask = nmk_gpio_get_bitmask(gpio);
 	u32 reg;
 
 	/* we must individually set/clear the two edges */
 	if (nmk_chip->edge_rising & bitmask) {
-		reg = readl(nmk_chip->addr + NMK_GPIO_RIMSC);
+		reg = readl(nmk_chip->addr + rimsc);
 		if (enable)
 			reg |= bitmask;
 		else
 			reg &= ~bitmask;
-		writel(reg, nmk_chip->addr + NMK_GPIO_RIMSC);
+		writel(reg, nmk_chip->addr + rimsc);
 	}
 	if (nmk_chip->edge_falling & bitmask) {
-		reg = readl(nmk_chip->addr + NMK_GPIO_FIMSC);
+		reg = readl(nmk_chip->addr + fimsc);
 		if (enable)
 			reg |= bitmask;
 		else
 			reg &= ~bitmask;
-		writel(reg, nmk_chip->addr + NMK_GPIO_FIMSC);
+		writel(reg, nmk_chip->addr + fimsc);
 	}
 }
 
-static void nmk_gpio_irq_modify(unsigned int irq, bool enable)
+static int nmk_gpio_irq_modify(unsigned int irq, enum nmk_gpio_irq_type which,
+			       bool enable)
 {
 	int gpio;
 	struct nmk_gpio_chip *nmk_chip;
@@ -337,26 +346,35 @@ static void nmk_gpio_irq_modify(unsigned int irq, bool enable)
 	nmk_chip = get_irq_chip_data(irq);
 	bitmask = nmk_gpio_get_bitmask(gpio);
 	if (!nmk_chip)
-		return;
+		return -EINVAL;
 
 	spin_lock_irqsave(&nmk_chip->lock, flags);
-	__nmk_gpio_irq_modify(nmk_chip, gpio, enable);
+	__nmk_gpio_irq_modify(nmk_chip, gpio, which, enable);
 	spin_unlock_irqrestore(&nmk_chip->lock, flags);
+
+	return 0;
 }
 
 static void nmk_gpio_irq_mask(unsigned int irq)
 {
-	nmk_gpio_irq_modify(irq, false);
-};
+	nmk_gpio_irq_modify(irq, NORMAL, false);
+}
 
 static void nmk_gpio_irq_unmask(unsigned int irq)
 {
-	nmk_gpio_irq_modify(irq, true);
+	nmk_gpio_irq_modify(irq, NORMAL, true);
+}
+
+static int nmk_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+{
+	return nmk_gpio_irq_modify(irq, WAKE, on);
 }
 
 static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
 {
-	bool enabled = !(irq_to_desc(irq)->status & IRQ_DISABLED);
+	struct irq_desc *desc = irq_to_desc(irq);
+	bool enabled = !(desc->status & IRQ_DISABLED);
+	bool wake = desc->wake_depth;
 	int gpio;
 	struct nmk_gpio_chip *nmk_chip;
 	unsigned long flags;
@@ -376,7 +394,10 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
 	spin_lock_irqsave(&nmk_chip->lock, flags);
 
 	if (enabled)
-		__nmk_gpio_irq_modify(nmk_chip, gpio, false);
+		__nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false);
+
+	if (wake)
+		__nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false);
 
 	nmk_chip->edge_rising &= ~bitmask;
 	if (type & IRQ_TYPE_EDGE_RISING)
@@ -387,7 +408,10 @@ static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
 		nmk_chip->edge_falling |= bitmask;
 
 	if (enabled)
-		__nmk_gpio_irq_modify(nmk_chip, gpio, true);
+		__nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true);
+
+	if (wake)
+		__nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true);
 
 	spin_unlock_irqrestore(&nmk_chip->lock, flags);
 
@@ -400,6 +424,7 @@ static struct irq_chip nmk_gpio_irq_chip = {
 	.mask		= nmk_gpio_irq_mask,
 	.unmask		= nmk_gpio_irq_unmask,
 	.set_type	= nmk_gpio_irq_set_type,
+	.set_wake	= nmk_gpio_irq_set_wake,
 };
 
 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
-- 
1.7.0



From u.kleine-koenig at pengutronix.de  Thu Jun 10 05:58:08 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 10 Jun 2010 11:58:08 +0200
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option
	for exceptions
In-Reply-To: <AANLkTin9qGAJGSgu9Y2YjI_W8UwBITd-QYyGERcLLUgP@mail.gmail.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
	<20100610090015.GD3422@pengutronix.de>
	<AANLkTin9qGAJGSgu9Y2YjI_W8UwBITd-QYyGERcLLUgP@mail.gmail.com>
Message-ID: <20100610095808.GA31057@pengutronix.de>

Hello Eric,

> > What do you think about requiring r4 to be set to physoffset as I did in
> > my series?
> 
> My only concern is to impose less restrictions on the boot loaders.
While it remains optional without runtime physoffset it's OK if you ask
me.

> And zImage is only one of the possible headers we may have:
> 
>  * vmlinux can actually directly booted into as long as it's placed at the
>    right place
>  * uImage, with zImage or vmlinux (raw or compressed) encapsulated
>  * zImage
>  * xipImage
>  * bootpImage
bootpimage is still used?  In a different thread I suggested to remove
it.
The others are just a wrapped vmlinux that needs to be aware anyhow.
And the wrappers only need to pass r4 additionally to r2 and r3 through.

> I'd really like to separate the guess work into two parts so they don't
> have dependencies.
But zreladdr is always physoffset + textoffset, isn't it?  So you should
use the same guess for both physoffset and zreladdr, no?

And if you do it properly, it should even be possible to reuse the same
code for all locations.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From rabin.vincent at stericsson.com  Thu Jun 10 05:56:00 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Thu, 10 Jun 2010 15:26:00 +0530
Subject: [PATCH 2/3] nomadik-gpio: implement to_irq
In-Reply-To: <1276163761-28342-1-git-send-email-rabin.vincent@stericsson.com>
References: <1276163761-28342-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1276163761-28342-2-git-send-email-rabin.vincent@stericsson.com>

So that gpio_to_irq() works.

Acked-by: Alessandro Rubini <rubini at unipv.it>
Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 arch/arm/plat-nomadik/gpio.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index a98f618..b4aa299 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -515,12 +515,21 @@ static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
 	return 0;
 }
 
+static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
+{
+	struct nmk_gpio_chip *nmk_chip =
+		container_of(chip, struct nmk_gpio_chip, chip);
+
+	return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset;
+}
+
 /* This structure is replicated for each GPIO block allocated at probe time */
 static struct gpio_chip nmk_gpio_template = {
 	.direction_input	= nmk_gpio_make_input,
 	.get			= nmk_gpio_get_input,
 	.direction_output	= nmk_gpio_make_output,
 	.set			= nmk_gpio_set_output,
+	.to_irq			= nmk_gpio_to_irq,
 	.ngpio			= NMK_GPIO_PER_CHIP,
 	.can_sleep		= 0,
 };
-- 
1.7.0



From rabin.vincent at stericsson.com  Thu Jun 10 05:56:01 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Thu, 10 Jun 2010 15:26:01 +0530
Subject: [PATCH 3/3] nomadik-gpio: fix "ignoring return value" warning
In-Reply-To: <1276163761-28342-1-git-send-email-rabin.vincent@stericsson.com>
References: <1276163761-28342-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1276163761-28342-3-git-send-email-rabin.vincent@stericsson.com>

arch/arm/plat-nomadik/gpio.c: In function 'nmk_gpio_remove':
arch/arm/plat-nomadik/gpio.c:630: warning: ignoring return value of 'gpiochip_remove', declared with attribute warn_unused_result

Because this function is marked __exit and this code can't be built as a
module, this function is never used.  So just remove it, fixing the
warning in the process.

Acked-by: Alessandro Rubini <rubini at unipv.it>
Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 arch/arm/plat-nomadik/gpio.c |   18 ------------------
 1 files changed, 0 insertions(+), 18 deletions(-)

diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index b4aa299..dc736d2 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -619,30 +619,12 @@ out:
 	return ret;
 }
 
-static int __exit nmk_gpio_remove(struct platform_device *dev)
-{
-	struct nmk_gpio_chip *nmk_chip;
-	struct resource *res;
-
-	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
-
-	nmk_chip = platform_get_drvdata(dev);
-	gpiochip_remove(&nmk_chip->chip);
-	clk_disable(nmk_chip->clk);
-	clk_put(nmk_chip->clk);
-	kfree(nmk_chip);
-	release_mem_region(res->start, resource_size(res));
-	return 0;
-}
-
-
 static struct platform_driver nmk_gpio_driver = {
 	.driver = {
 		.owner = THIS_MODULE,
 		.name = "gpio",
 		},
 	.probe = nmk_gpio_probe,
-	.remove = __exit_p(nmk_gpio_remove),
 	.suspend = NULL, /* to be done */
 	.resume = NULL,
 };
-- 
1.7.0



From u.kleine-koenig at pengutronix.de  Thu Jun 10 06:00:39 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 10 Jun 2010 12:00:39 +0200
Subject: [PATCH 3/5] [ARM] Make TEXT_OFFSET a configurable option
In-Reply-To: <AANLkTilNMqC0q65GzRiyyX091390TaHFD7ffaxkWWyf8@mail.gmail.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-4-git-send-email-eric.miao@canonical.com>
	<20100610085053.GC3422@pengutronix.de>
	<AANLkTilNMqC0q65GzRiyyX091390TaHFD7ffaxkWWyf8@mail.gmail.com>
Message-ID: <20100610100039.GB31057@pengutronix.de>

On Thu, Jun 10, 2010 at 05:45:53PM +0800, Eric Miao wrote:
> 2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> > On Thu, Jun 03, 2010 at 03:36:51PM +0800, Eric Miao wrote:
> >> From: Eric Miao <eric.y.miao at gmail.com>
> >>
> >> Signed-off-by: Eric Miao <eric.miao at canonical.com>
> >> ---
> >> ?arch/arm/Kconfig ? ? ? ? | ? 13 +++++++++++++
> >> ?arch/arm/Makefile ? ? ? ?| ? 13 +------------
> >> ?arch/arm/kernel/Makefile | ? ?4 ++--
> >> ?3 files changed, 16 insertions(+), 14 deletions(-)
> >>
> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> >> index 1f254bd..e340193 100644
> >> --- a/arch/arm/Kconfig
> >> +++ b/arch/arm/Kconfig
> >> @@ -1484,6 +1484,19 @@ config ATAGS_PROC
> >> ? ? ? ? Should the atags used to boot the kernel be exported in an "atags"
> >> ? ? ? ? file in procfs. Useful with kexec.
> >>
> >> +config TEXT_OFFSET
> >> + ? ? hex "Offset of the kernel image from the start of RAM"
> > IMHO this should not be user configurable.
> >
> 
> That's true. The reason I don't want to keep this in Makefile is the
> concern about future change to Makefile (that machine-y could be
> composed of all the mach-*), and make it a kernel config option at
> least provide a way to fix that by the user interactively.
You can have both, just remove the string after "hex" above.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From kgene.kim at samsung.com  Thu Jun 10 06:01:25 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 10 Jun 2010 19:01:25 +0900
Subject: [PATCH v2] arm: s5pv210: add more banks to gpiolib
In-Reply-To: <1276088919-20730-1-git-send-email-m.szyprowski@samsung.com>
References: <1276088919-20730-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <019101cb0883$e5a07fb0$b0e17f10$%kim@samsung.com>

Marek Szyprowski wrote:
> 
> This patch adds support for MP04 and MP05 gpio banks.
> 
LGTM. Will apply.

> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> 
> ---
> 
> Changes since v1:
> - fixed style issues reported by Kukjin Kim
> 
>  arch/arm/mach-s5pv210/gpiolib.c           |   14 ++++++++++++++
>  arch/arm/mach-s5pv210/include/mach/gpio.h |   12 +++++++++---
>  2 files changed, 23 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
> index f4ac81f..0261908 100644
> --- a/arch/arm/mach-s5pv210/gpiolib.c
> +++ b/arch/arm/mach-s5pv210/gpiolib.c
> @@ -208,6 +208,20 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
>  			.label	= "MP03",
>  		},
>  	}, {
> +		.config	= &gpio_cfg_noint,
> +		.chip	= {
> +			.base	= S5PV210_MP04(0),
> +			.ngpio	= S5PV210_GPIO_MP04_NR,
> +			.label	= "MP04",
> +		},
> +	}, {
> +		.config	= &gpio_cfg_noint,
> +		.chip	= {
> +			.base	= S5PV210_MP05(0),
> +			.ngpio	= S5PV210_GPIO_MP05_NR,
> +			.label	= "MP05",
> +		},
> +	}, {
>  		.base	= (S5P_VA_GPIO + 0xC00),
>  		.config	= &gpio_cfg_noint,
>  		.chip	= {
> diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-
> s5pv210/include/mach/gpio.h
> index d6461ba..1f4b595 100644
> --- a/arch/arm/mach-s5pv210/include/mach/gpio.h
> +++ b/arch/arm/mach-s5pv210/include/mach/gpio.h
> @@ -52,6 +52,8 @@
>  #define S5PV210_GPIO_MP01_NR	(8)
>  #define S5PV210_GPIO_MP02_NR	(4)
>  #define S5PV210_GPIO_MP03_NR	(8)
> +#define S5PV210_GPIO_MP04_NR	(8)
> +#define S5PV210_GPIO_MP05_NR	(8)
> 
>  /* GPIO bank numbers */
> 
> @@ -94,6 +96,8 @@ enum s5p_gpio_number {
>  	S5PV210_GPIO_MP01_START	=
> S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
>  	S5PV210_GPIO_MP02_START	=
> S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
>  	S5PV210_GPIO_MP03_START	=
> S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
> +	S5PV210_GPIO_MP04_START	=
> S5PV210_GPIO_NEXT(S5PV210_GPIO_MP03),
> +	S5PV210_GPIO_MP05_START	=
> S5PV210_GPIO_NEXT(S5PV210_GPIO_MP04),
>  };
> 
>  /* S5PV210 GPIO number definitions */
> @@ -127,13 +131,15 @@ enum s5p_gpio_number {
>  #define S5PV210_MP01(_nr)	(S5PV210_GPIO_MP01_START + (_nr))
>  #define S5PV210_MP02(_nr)	(S5PV210_GPIO_MP02_START + (_nr))
>  #define S5PV210_MP03(_nr)	(S5PV210_GPIO_MP03_START + (_nr))
> +#define S5PV210_MP04(_nr)	(S5PV210_GPIO_MP04_START + (_nr))
> +#define S5PV210_MP05(_nr)	(S5PV210_GPIO_MP05_START + (_nr))
> 
>  /* the end of the S5PV210 specific gpios */
> -#define S5PV210_GPIO_END	(S5PV210_MP03(S5PV210_GPIO_MP03_NR) +
> 1)
> +#define S5PV210_GPIO_END	(S5PV210_MP05(S5PV210_GPIO_MP05_NR) +
> 1)
>  #define S3C_GPIO_END		S5PV210_GPIO_END
> 
> -/* define the number of gpios we need to the one after the MP03() range */
> -#define ARCH_NR_GPIOS
> 	(S5PV210_MP03(S5PV210_GPIO_MP03_NR) +	\
> +/* define the number of gpios we need to the one after the MP05() range */
> +#define ARCH_NR_GPIOS
> 	(S5PV210_MP05(S5PV210_GPIO_MP05_NR) +	\
>  				 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
> 
>  #include <asm-generic/gpio.h>
> --

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From eric.miao at canonical.com  Thu Jun 10 06:20:45 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 10 Jun 2010 18:20:45 +0800
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option for 
	exceptions
In-Reply-To: <20100610095808.GA31057@pengutronix.de>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com> 
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com> 
	<20100610090015.GD3422@pengutronix.de>
	<AANLkTin9qGAJGSgu9Y2YjI_W8UwBITd-QYyGERcLLUgP@mail.gmail.com> 
	<20100610095808.GA31057@pengutronix.de>
Message-ID: <AANLkTikulOGKEoAYptacYPgM8PAJ49JlGUO6rJWY5gqF@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> Hello Eric,
>
>> > What do you think about requiring r4 to be set to physoffset as I did in
>> > my series?
>>
>> My only concern is to impose less restrictions on the boot loaders.
> While it remains optional without runtime physoffset it's OK if you ask
> me.
>
>> And zImage is only one of the possible headers we may have:
>>
>> ?* vmlinux can actually directly booted into as long as it's placed at the
>> ? ?right place
>> ?* uImage, with zImage or vmlinux (raw or compressed) encapsulated
>> ?* zImage
>> ?* xipImage
>> ?* bootpImage
> bootpimage is still used? ?In a different thread I suggested to remove
> it.
> The others are just a wrapped vmlinux that needs to be aware anyhow.
> And the wrappers only need to pass r4 additionally to r2 and r3 through.
>
>> I'd really like to separate the guess work into two parts so they don't
>> have dependencies.
> But zreladdr is always physoffset + textoffset, isn't it?

I'm not completely sure about the u300 case.

> So you should
> use the same guess for both physoffset and zreladdr, no?

My understanding is that separating guess of phys_offset and zreladdr might
be a smoother migration path at this moment and yes it's a trade off.


> And if you do it properly, it should even be possible to reuse the same
> code for all locations.
>
> Best regards
> Uwe
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | Uwe Kleine-K?nig ? ? ? ? ? ?|
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
>


From u.kleine-koenig at pengutronix.de  Thu Jun 10 06:24:27 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 10 Jun 2010 12:24:27 +0200
Subject: [PATCH 0/10] cleanup in early boot code
In-Reply-To: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
Message-ID: <20100610102427.GC31057@pengutronix.de>

Hello,

a while ago I sent a few patches that clean up in this area, too, some
of them are orthogonal to Eric's.  I resend them in reply to this mail.

Eric, maybe we can start merging your and my work, at least the bits
that doesn't need further discussion between us?  (i.e. the patches I
acked and hopefully the first few of mine)

Do you irc?  I'm (e.g.) in #armlinux on freenode.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From u.kleine-koenig at pengutronix.de  Thu Jun 10 06:27:08 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 10 Jun 2010 12:27:08 +0200
Subject: [PATCH 02/10] arm/zImage: some comments for __armv3_mpu_cache_on
In-Reply-To: <20100610102427.GC31057@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
Message-ID: <1276165636-20150-2-git-send-email-u.kleine-koenig@pengutronix.de>

__armv3_mpu_cache_on seems broken.  As there is noone around who knows
about these machines just keep the code as is but point out the strange
things.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/boot/compressed/head.S |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 390aa92..384150b 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -396,12 +396,15 @@ __armv3_mpu_cache_on:
 
 		mov	r0, #0
 		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3
+		/* ?? ARMv3 MMU doesn not allow reading the control register, does this really work on ARMv3 MPU? */
 		mrc	p15, 0, r0, c1, c0, 0	@ read control reg
 						@ .... .... .... WC.M
 		orr	r0, r0, #0x000d		@ .... .... .... 11.1
+		/* ?? this overwrites the value constructed above? */
 		mov	r0, #0
 		mcr	p15, 0, r0, c1, c0, 0	@ write control reg
 
+		/* ?? invalidate for the second time? */
 		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3
 		mov	pc, lr
 
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 10 06:27:09 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 10 Jun 2010 12:27:09 +0200
Subject: [PATCH 03/10] arm/zImage: __armv3_mpu_cache_flush: respect
	should-be-zero specification
In-Reply-To: <20100610102427.GC31057@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
Message-ID: <1276165636-20150-3-git-send-email-u.kleine-koenig@pengutronix.de>

Probably the register content for cache operations is "don't care" in
practice, but as r1 is explicitly zeroed, use that one.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/boot/compressed/head.S |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 384150b..4058294 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -991,7 +991,7 @@ no_cache_id:
 __armv3_mmu_cache_flush:
 __armv3_mpu_cache_flush:
 		mov	r1, #0
-		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3
+		mcr	p15, 0, r1, c7, c0, 0	@ invalidate whole cache v3
 		mov	pc, lr
 
 /*
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 10 06:27:10 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 10 Jun 2010 12:27:10 +0200
Subject: [PATCH 04/10] arm/zImage: fix comments for cache_on,
	cache_off and cache_clean_flush
In-Reply-To: <20100610102427.GC31057@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
Message-ID: <1276165636-20150-4-git-send-email-u.kleine-koenig@pengutronix.de>

This adds missing registers to the list of corrupted registers and
removes a wrong comment about r9 on entry

While at it the formatting of the comment to cache_off is changed to
resemble the other two.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/boot/compressed/head.S |   11 ++++++-----
 1 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 4058294..f8a210b 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -339,9 +339,8 @@ params:		ldr	r0, =params_phys
  *  r4 = kernel execution address
  *  r7 = architecture number
  *  r8 = atags pointer
- *  r9 = run-time address of "start"  (???)
  * On exit,
- *  r1, r2, r3, r9, r10, r12 corrupted
+ *  r0, r1, r2, r3, r9, r10, r12 corrupted
  * This routine must preserve:
  *  r4, r5, r6, r7, r8
  */
@@ -774,8 +773,10 @@ proc_types:
  * Turn off the Cache and MMU.  ARMv3 does not support
  * reading the control register, but ARMv4 does.
  *
- * On exit, r0, r1, r2, r3, r9, r12 corrupted
- * This routine must preserve: r4, r6, r7
+ * On exit,
+ *  r0, r1, r2, r3, r9, r12 corrupted
+ * This routine must preserve:
+ *  r4, r6, r7
  */
 		.align	5
 cache_off:	mov	r3, #12			@ cache_off function
@@ -848,7 +849,7 @@ __armv3_mmu_cache_off:
  * Clean and flush the cache to maintain consistency.
  *
  * On exit,
- *  r1, r2, r3, r9, r11, r12 corrupted
+ *  r1, r2, r3, r9, r10, r11, r12 corrupted
  * This routine must preserve:
  *  r0, r4, r5, r6, r7
  */
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 10 06:27:07 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 10 Jun 2010 12:27:07 +0200
Subject: [PATCH 01/10] arm/zImage: don't hard code the stack size twice
In-Reply-To: <20100610102427.GC31057@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
Message-ID: <1276165636-20150-1-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/boot/compressed/head.S |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index c5191b1..390aa92 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -315,7 +315,7 @@ LC0:		.word	LC0			@ r1
 		.word	_image_size		@ r6
 		.word	_got_start		@ r11
 		.word	_got_end		@ ip
-		.word	user_stack+4096		@ sp
+		.word	user_stack_end		@ sp
 LC1:		.word	reloc_end - reloc_start
 		.size	LC0, . - LC0
 
@@ -1070,3 +1070,4 @@ reloc_end:
 		.align
 		.section ".stack", "w"
 user_stack:	.space	4096
+user_stack_end:
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 10 06:27:13 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 10 Jun 2010 12:27:13 +0200
Subject: [PATCH 07/10] arm/zImage: don't define unused symbol initrd_phys
In-Reply-To: <20100610102427.GC31057@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
Message-ID: <1276165636-20150-7-git-send-email-u.kleine-koenig@pengutronix.de>

The only user of initrd_phys is arch/arm/boot/bootp/init.S which still
gets the value passed to.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/boot/compressed/Makefile |    9 +++------
 1 files changed, 3 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 53faa90..5419448 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -79,16 +79,13 @@ endif
 EXTRA_CFLAGS  := -fpic -fno-builtin
 EXTRA_AFLAGS  := -Wa,-march=all
 
-# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
-# linker symbols.  We only define initrd_phys and params_phys if the
-# machine class defined the corresponding makefile variable.
+# Supply ZRELADDR and PARAMS_PHYS to the decompressor via linker symbols.  We
+# only define params_phys if the machine class defined the corresponding
+# makefile variable.
 LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
 ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
 endif
-ifneq ($(INITRD_PHYS),)
-LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
-endif
 ifneq ($(PARAMS_PHYS),)
 LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS)
 endif
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 10 06:27:11 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 10 Jun 2010 12:27:11 +0200
Subject: [PATCH 05/10] arm/zImage: annotate debug functions about corrupted
	registers
In-Reply-To: <20100610102427.GC31057@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
Message-ID: <1276165636-20150-5-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/boot/compressed/head.S |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index f8a210b..dbeeb56 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -1005,6 +1005,7 @@ __armv3_mpu_cache_flush:
 phexbuf:	.space	12
 		.size	phexbuf, . - phexbuf
 
+@ phex corrupts {r0, r1, r2, r3}
 phex:		adr	r3, phexbuf
 		mov	r2, #0
 		strb	r2, [r3, r1]
@@ -1019,6 +1020,7 @@ phex:		adr	r3, phexbuf
 		strb	r2, [r3, r1]
 		b	1b
 
+@ puts corrupts {r0, r1, r2, r3}
 puts:		loadsp	r3, r1
 1:		ldrb	r2, [r0], #1
 		teq	r2, #0
@@ -1033,12 +1035,14 @@ puts:		loadsp	r3, r1
 		teq	r0, #0
 		bne	1b
 		mov	pc, lr
+@ putc corrupts {r0, r1, r2, r3}
 putc:
 		mov	r2, r0
 		mov	r0, #0
 		loadsp	r3, r1
 		b	2b
 
+@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
 memdump:	mov	r12, r0
 		mov	r10, lr
 		mov	r11, #0
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 10 06:27:14 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 10 Jun 2010 12:27:14 +0200
Subject: [PATCH 08/10] arm: deprecate support for old way to pass kernel
	parameters
In-Reply-To: <20100610102427.GC31057@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
Message-ID: <1276165636-20150-8-git-send-email-u.kleine-koenig@pengutronix.de>

This was deprecated in 2001 and announced to live on for 5 years.

For now provide a kernel parameter for those who still need it.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/Kconfig         |    6 ++++++
 arch/arm/kernel/Makefile |    4 +++-
 arch/arm/kernel/compat.c |    7 -------
 arch/arm/kernel/compat.h |    2 --
 arch/arm/kernel/setup.c  |   11 +++++++++++
 5 files changed, 20 insertions(+), 10 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..a53ac65 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1374,6 +1374,12 @@ config UACCESS_WITH_MEMCPY
 	  However, if the CPU data cache is using a write-allocate mode,
 	  this option is unlikely to provide any performance gain.
 
+config DEPRECATED_PARAM_STRUCT
+	bool "Provide old way to pass kernel parameters"
+	help
+	  This was deprecated in 2001 and announced to live on for 5 years.
+	  Some old boot loaders still use this way.
+
 endmenu
 
 menu "Boot options"
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 26d302c..021f72d 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -13,10 +13,12 @@ CFLAGS_REMOVE_return_address.o = -pg
 
 # Object file lists.
 
-obj-y		:= compat.o elf.o entry-armv.o entry-common.o irq.o \
+obj-y		:= elf.o entry-armv.o entry-common.o irq.o \
 		   process.o ptrace.o return_address.o setup.o signal.o \
 		   sys_arm.o stacktrace.o time.o traps.o
 
+obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
+
 obj-$(CONFIG_LEDS)		+= leds.o
 obj-$(CONFIG_OC_ETM)		+= etm.o
 
diff --git a/arch/arm/kernel/compat.c b/arch/arm/kernel/compat.c
index 0a13854..9256523 100644
--- a/arch/arm/kernel/compat.c
+++ b/arch/arm/kernel/compat.c
@@ -217,10 +217,3 @@ void __init convert_to_tag_list(struct tag *tags)
 	struct param_struct *params = (struct param_struct *)tags;
 	build_tag_list(params, &params->u2);
 }
-
-void __init squash_mem_tags(struct tag *tag)
-{
-	for (; tag->hdr.size; tag = tag_next(tag))
-		if (tag->hdr.tag == ATAG_MEM)
-			tag->hdr.tag = ATAG_NONE;
-}
diff --git a/arch/arm/kernel/compat.h b/arch/arm/kernel/compat.h
index 27e61a6..39264ab 100644
--- a/arch/arm/kernel/compat.h
+++ b/arch/arm/kernel/compat.h
@@ -9,5 +9,3 @@
 */
 
 extern void convert_to_tag_list(struct tag *tags);
-
-extern void squash_mem_tags(struct tag *tag);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 122d999..cbc6ddb 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -44,7 +44,9 @@
 #include <asm/traps.h>
 #include <asm/unwind.h>
 
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
 #include "compat.h"
+#endif
 #include "atags.h"
 #include "tcm.h"
 
@@ -663,6 +665,13 @@ static int __init customize_machine(void)
 }
 arch_initcall(customize_machine);
 
+static void __init squash_mem_tags(struct tag *tag)
+{
+	for (; tag->hdr.size; tag = tag_next(tag))
+		if (tag->hdr.tag == ATAG_MEM)
+			tag->hdr.tag = ATAG_NONE;
+}
+
 void __init setup_arch(char **cmdline_p)
 {
 	struct tag *tags = (struct tag *)&init_tags;
@@ -683,12 +692,14 @@ void __init setup_arch(char **cmdline_p)
 	else if (mdesc->boot_params)
 		tags = phys_to_virt(mdesc->boot_params);
 
+#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
 	/*
 	 * If we have the old style parameters, convert them to
 	 * a tag list.
 	 */
 	if (tags->hdr.tag != ATAG_CORE)
 		convert_to_tag_list(tags);
+#endif
 	if (tags->hdr.tag != ATAG_CORE)
 		tags = (struct tag *)&init_tags;
 
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 10 06:27:12 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 10 Jun 2010 12:27:12 +0200
Subject: [PATCH 06/10] arm: remove bit-rotten STANDALONE_DEBUG for decompressor
In-Reply-To: <20100610102427.GC31057@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
Message-ID: <1276165636-20150-6-git-send-email-u.kleine-koenig@pengutronix.de>

I tried to get this running to debug the regression introduced by
e7db7b4 without success.  But this has several problems that make it
hard to fix:

  - lib/decompress_inflate.c includes in-kernel headers that make
    it difficult to compile for user space.
  - the binary formats changed both in kernel and user space and
    at least for the kernel side there isn't only a single
    variant.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/boot/compressed/Makefile.debug |   23 -----------------------
 arch/arm/boot/compressed/misc.c         |   20 --------------------
 2 files changed, 0 insertions(+), 43 deletions(-)
 delete mode 100644 arch/arm/boot/compressed/Makefile.debug

diff --git a/arch/arm/boot/compressed/Makefile.debug b/arch/arm/boot/compressed/Makefile.debug
deleted file mode 100644
index 491a037..0000000
--- a/arch/arm/boot/compressed/Makefile.debug
+++ /dev/null
@@ -1,23 +0,0 @@
-#
-# linux/arch/arm/boot/compressed/Makefile
-#
-# create a compressed vmlinux image from the original vmlinux
-#
-
-COMPRESSED_EXTRA=../../lib/ll_char_wr.o
-OBJECTS=misc-debug.o ll_char_wr.aout.o
-
-CFLAGS=-D__KERNEL__ -O2 -DSTDC_HEADERS -DSTANDALONE_DEBUG -Wall -I../../../../include -c
-
-test-gzip: piggy.aout.o $(OBJECTS)
-	$(CC) -o $@ $(OBJECTS) piggy.aout.o
-
-misc-debug.o: misc.c
-	$(CC) $(CFLAGS) -o $@ misc.c
-
-piggy.aout.o: piggy.o
-	arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux piggy.o piggy.aout.o
-
-ll_char_wr.aout.o: $(COMPRESSED_EXTRA)
-	arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux $(COMPRESSED_EXTRA) ll_char_wr.aout.o
-
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index d2b2ef4..e653a6d 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -28,9 +28,6 @@ unsigned int __machine_arch_type;
 
 #include <asm/unaligned.h>
 
-#ifdef STANDALONE_DEBUG
-#define putstr printf
-#else
 
 static void putstr(const char *ptr);
 extern void error(char *x);
@@ -116,7 +113,6 @@ static void putstr(const char *ptr)
 	flush();
 }
 
-#endif
 
 void *memcpy(void *__dest, __const void *__src, size_t __n)
 {
@@ -186,7 +182,6 @@ asmlinkage void __div0(void)
 
 extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
 
-#ifndef STANDALONE_DEBUG
 
 unsigned long
 decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
@@ -211,18 +206,3 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
 	putstr(" done, booting the kernel.\n");
 	return output_ptr;
 }
-#else
-
-char output_buffer[1500*1024];
-
-int main()
-{
-	output_data = output_buffer;
-
-	putstr("Uncompressing Linux...");
-	decompress(input_data, input_data_end - input_data,
-			NULL, NULL, output_data, NULL, error);
-	putstr("done.\n");
-	return 0;
-}
-#endif
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 10 06:27:15 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 10 Jun 2010 12:27:15 +0200
Subject: [PATCH 09/10] arm/uImage: require passing a LOADADDR when building
	with RUNTIME_PHYSOFFSET
In-Reply-To: <20100610102427.GC31057@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
Message-ID: <1276165636-20150-9-git-send-email-u.kleine-koenig@pengutronix.de>

the default load address (in the CONFIG_ZBOOT_ROM=n case) is ZRELADDR
which (apart from being a stupid load address for the
RUNTIME_PHYSOFFSET=n case) might not be a valid read/write memory on the
target machine at all.  So require passing a LOADADDR on the command
line.  This obiously makes the uImage more machine dependant than the
zImage.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/boot/Makefile |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index 4a590f4..264dccf 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -64,11 +64,13 @@ quiet_cmd_uimage = UIMAGE  $@
 		   -C none -a $(LOADADDR) -e $(STARTADDR) \
 		   -n 'Linux-$(KERNELRELEASE)' -d $< $@
 
+ifeq ($(CONFIG_RUNTIME_PHYS_OFFSET),)
 ifeq ($(CONFIG_ZBOOT_ROM),y)
 $(obj)/uImage: LOADADDR=$(CONFIG_ZBOOT_ROM_TEXT)
 else
 $(obj)/uImage: LOADADDR=$(ZRELADDR)
 endif
+endif
 
 ifeq ($(CONFIG_THUMB2_KERNEL),y)
 # Set bit 0 to 1 so that "mov pc, rx" switches to Thumb-2 mode
@@ -77,7 +79,9 @@ else
 $(obj)/uImage: STARTADDR=$(LOADADDR)
 endif
 
-$(obj)/uImage:	$(obj)/zImage FORCE
+$(obj)/uImage: $(obj)/zImage FORCE
+	@test -n "$(LOADADDR)" || \
+	(echo "You must specify a load address (i.e. make uImage LOADADDR=0x...)"; exit 1)
 	$(call if_changed,uimage)
 	@echo '  Image $@ is ready'
 
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 10 06:27:16 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 10 Jun 2010 12:27:16 +0200
Subject: [PATCH 10/10] arm: Allow PHYS_OFFSET to be runtime determined
In-Reply-To: <20100610102427.GC31057@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
Message-ID: <1276165636-20150-10-git-send-email-u.kleine-koenig@pengutronix.de>

This bases on work done earlier by Lennert Buytenhek and Mark A. Greer.
Compared to their approach zreladdr isn't guessed based on the pc
register but the bootloader is expected to pass PHYS_OFFSET in r3.  If
that value doesn't look right (e.g. isn't aligned) it is guessed based
on the value of sp.  This should work for CONFIG_ZBOOT_ROM, too.

To use it for your machine removing the definition of PHYS_OFFSET from
<mach/memory.h> and selecting CONFIG_RUNTIME_PHYS_OFFSET should be
enough.

Cc: Lennert Buytenhek <buytenh at wantstofly.org>
Cc: Steve Chen <schen at mvista.com>
Cc: Mark A. Greer <mgreer at mvista.com>
Cc: Kevin Hilman <khilman at deeprootsystems.com>
Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
This patch is only included as I forgot to take it out before sending the
initial mail.  But maybe it's not bad to have it in this thread, too.

Best regards
Uwe

 Documentation/arm/Booting         |    1 +
 arch/arm/Kconfig                  |    3 ++
 arch/arm/boot/compressed/Makefile |    1 +
 arch/arm/boot/compressed/head.S   |   50 +++++++++++++++++++++++++++++++++++++
 arch/arm/include/asm/memory.h     |    5 +++
 arch/arm/kernel/head.S            |   31 +++++++++++++++++------
 arch/arm/kernel/setup.c           |   10 ++++++-
 7 files changed, 92 insertions(+), 9 deletions(-)

diff --git a/Documentation/arm/Booting b/Documentation/arm/Booting
index 7685029..ec228a4 100644
--- a/Documentation/arm/Booting
+++ b/Documentation/arm/Booting
@@ -126,6 +126,7 @@ In either case, the following conditions must be met:
   r0 = 0,
   r1 = machine type number discovered in (3) above.
   r2 = physical address of tagged list in system RAM.
+  r3 = PHYS_OFFSET
 
 - CPU mode
   All forms of interrupts must be disabled (IRQs and FIQs)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a53ac65..7ac29a5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1374,6 +1374,9 @@ config UACCESS_WITH_MEMCPY
 	  However, if the CPU data cache is using a write-allocate mode,
 	  this option is unlikely to provide any performance gain.
 
+config RUNTIME_PHYS_OFFSET
+	bool
+
 config DEPRECATED_PARAM_STRUCT
 	bool "Provide old way to pass kernel parameters"
 	help
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 5419448..0660a25 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -4,6 +4,7 @@
 # create a compressed vmlinuz image from the original vmlinux
 #
 
+AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
 HEAD	= head.o
 OBJS	= misc.o decompress.o
 FONTC	= $(srctree)/drivers/video/console/font_acorn_8x8.c
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index dbeeb56..e066d26 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -120,6 +120,16 @@ wait:		mrc	p14, 0, pc, c0, c1, 0
 #endif
 		.endm
 
+		.macro	debug_passed_physoffset
+#ifdef DEBUG
+		bleq	1f
+		kputc	#'!'
+		kphex	r9, 8
+		kputc	#'\n'
+1:
+#endif
+		.endm
+
 		.section ".start", #alloc, #execinstr
 /*
  * sort out different calling conventions
@@ -137,6 +147,7 @@ start:
 		.word	_edata			@ zImage end address
 1:		mov	r7, r1			@ save architecture ID
 		mov	r8, r2			@ save atags pointer
+		mov	r9, r3			@ save phys_offset
 
 #ifndef __ARM_ARCH_2__
 		/*
@@ -234,6 +245,44 @@ not_relocated:	mov	r0, #0
 		cmp	r2, r3
 		blo	1b
 
+#ifdef CONFIG_RUNTIME_PHYS_OFFSET
+		/*
+		 * assert physoffset passed by bootloader is properly
+		 * 2MiB-aligned, ...
+		 */
+		ldr	r10, =0x001fffff
+
+		tst	r9, r10
+		debug_passed_physoffset
+		tst	r9, r10
+
+		/*
+		 * ... if not guess it based on sp.
+		 * sp & 0xf8000000 should work for most machines.  The needed
+		 * preconditions are:
+		 * - physoffset is aligned to a 128MiB boundary
+		 *   (As of Jan 2010 all but s3c2400, u300 and at91 have it.
+		 *   For the latter it depends on configuration.)
+		 * - sp < physoffset + 128MiB (which is definitely true if you
+		 *   only have 128MiB of RAM or less)
+		 */
+		andne	r9, sp, #0xf8000000
+
+#ifdef DEBUG
+		kputc	#'P'
+		kphex	r9, 8
+		kputc	#'\n'
+#endif
+
+		add	r4, r9, #TEXT_OFFSET
+#else /* ifdef CONFIG_RUNTIME_PHYS_OFFSET */
+		/* warn on r4(ZRELADDR) != r9 + TEXT_OFFSET */
+		add	r10, r9, #TEXT_OFFSET
+		cmp	r10, r4
+		debug_passed_physoffset
+
+#endif /* ifdef CONFIG_RUNTIME_PHYS_OFFSET / else */
+
 		/*
 		 * The C runtime environment should now be setup
 		 * sufficiently.  Turn the cache on, set up some
@@ -570,6 +619,7 @@ call_kernel:	bl	cache_clean_flush
 		mov	r0, #0			@ must be zero
 		mov	r1, r7			@ restore architecture number
 		mov	r2, r8			@ restore atags pointer
+		sub	r3, r4, #TEXT_OFFSET	@ physoffset
 		mov	pc, r4			@ call kernel
 
 /*
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 4312ee5..05a7a3f 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -24,6 +24,11 @@
  */
 #define UL(x) _AC(x, UL)
 
+#if defined(CONFIG_RUNTIME_PHYS_OFFSET) && !defined(__ASSEMBLY__)
+extern unsigned long phys_offset;
+#define PHYS_OFFSET	phys_offset
+#endif
+
 #ifdef CONFIG_MMU
 
 /*
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..b173bb6 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -22,12 +22,14 @@
 #include <asm/thread_info.h>
 #include <asm/system.h>
 
+#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
 #if (PHYS_OFFSET & 0x001fffff)
 #error "PHYS_OFFSET must be at an even 2MiB boundary!"
 #endif
+#define KERNEL_RAM_PADDR	(PHYS_OFFSET + TEXT_OFFSET)
+#endif
 
 #define KERNEL_RAM_VADDR	(PAGE_OFFSET + TEXT_OFFSET)
-#define KERNEL_RAM_PADDR	(PHYS_OFFSET + TEXT_OFFSET)
 
 
 /*
@@ -44,8 +46,8 @@
 	.globl	swapper_pg_dir
 	.equ	swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
 
-	.macro	pgtbl, rd
-	ldr	\rd, =(KERNEL_RAM_PADDR - 0x4000)
+	.macro	pgtbl, rd, phys_offset
+	add	\rd, \phys_offset, #(TEXT_OFFSET - 0x4000)
 	.endm
 
 #ifdef CONFIG_XIP_KERNEL
@@ -215,9 +217,25 @@ ENDPROC(__turn_mmu_on)
  * Returns:
  *  r0, r3, r6, r7 corrupted
  *  r4 = physical page table address
+ *  r5 = physical start address of (the first bank of) RAM (PHYS_OFFSET)
  */
 __create_page_tables:
-	pgtbl	r4				@ page table address
+#if defined(CONFIG_RUNTIME_PHYS_OFFSET)
+	@ stext is at PHYS_OFFSET + TEXT_OFFSET.  As PHYS_OFFSET has to be
+	@ 2MiB-aligned and assuming that TEXT_OFFSET < 2MiB
+	@ stext & 0xffe00000 yields PHYS_OFFSET
+	adr	r5, stext
+	ldr	r4, =0xffe00000
+	and	r5, r5, r4
+
+	@ save phys_offset
+	ldr	r4, =(phys_offset - PAGE_OFFSET)
+	str	r5, [r4, r5]
+#else
+	ldr	r5, =PHYS_OFFSET
+#endif
+
+	pgtbl	r4, r5				@ r4 = page table address
 
 	/*
 	 * Clear the 16K level 1 swapper page table
@@ -282,10 +300,7 @@ __create_page_tables:
 	 * Then map first 1MB of ram in case it contains our boot params.
 	 */
 	add	r0, r4, #PAGE_OFFSET >> 18
-	orr	r6, r7, #(PHYS_OFFSET & 0xff000000)
-	.if	(PHYS_OFFSET & 0x00f00000)
-	orr	r6, r6, #(PHYS_OFFSET & 0x00f00000)
-	.endif
+	orr	r6, r7, r5
 	str	r6, [r0]
 
 #ifdef CONFIG_DEBUG_LL
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index cbc6ddb..02fe334 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -69,6 +69,12 @@ __setup("fpe=", fpe_setup);
 extern void paging_init(struct machine_desc *desc);
 extern void reboot_setup(char *str);
 
+#if defined(CONFIG_RUNTIME_PHYS_OFFSET)
+/* assign a value to prevent phys_offset from ending in up bss */
+unsigned long phys_offset = 0xdeadbeef;
+EXPORT_SYMBOL(phys_offset);
+#endif
+
 unsigned int processor_id;
 EXPORT_SYMBOL(processor_id);
 unsigned int __machine_arch_type;
@@ -650,7 +656,7 @@ static struct init_tags {
 	{ tag_size(tag_core), ATAG_CORE },
 	{ 1, PAGE_SIZE, 0xff },
 	{ tag_size(tag_mem32), ATAG_MEM },
-	{ MEM_SIZE, PHYS_OFFSET },
+	{ MEM_SIZE, },
 	{ 0, ATAG_NONE }
 };
 
@@ -691,6 +697,8 @@ void __init setup_arch(char **cmdline_p)
 		tags = phys_to_virt(__atags_pointer);
 	else if (mdesc->boot_params)
 		tags = phys_to_virt(mdesc->boot_params);
+	else
+		init_tags.mem.start = PHYS_OFFSET;
 
 #if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
 	/*
-- 
1.7.1



From eric.miao at canonical.com  Thu Jun 10 06:28:44 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 10 Jun 2010 18:28:44 +0800
Subject: [PATCH 0/10] cleanup in early boot code
In-Reply-To: <20100610102427.GC31057@pengutronix.de>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com> 
	<20100610102427.GC31057@pengutronix.de>
Message-ID: <AANLkTimB-i5Pbf7DCWc8ojGIqpfoh5HE0SYYqTKqrbPc@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> Hello,
>
> a while ago I sent a few patches that clean up in this area, too, some
> of them are orthogonal to Eric's. ?I resend them in reply to this mail.
>
> Eric, maybe we can start merging your and my work, at least the bits
> that doesn't need further discussion between us? ?(i.e. the patches I
> acked and hopefully the first few of mine)
>
> Do you irc? ?I'm (e.g.) in #armlinux on freenode.

I'm normally ericm or ericm|ubuntu in #ubuntu-arm, sometime, I'll add
#armlinux into my channels to join automatically

>
> Best regards
> Uwe
>
> --
> Pengutronix e.K. ? ? ? ? ? ? ? ? ? ? ? ? ? | Uwe Kleine-K?nig ? ? ? ? ? ?|
> Industrial Linux Solutions ? ? ? ? ? ? ? ? | http://www.pengutronix.de/ ?|
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From eric.miao at canonical.com  Thu Jun 10 06:31:52 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 10 Jun 2010 18:31:52 +0800
Subject: [PATCH 01/10] arm/zImage: don't hard code the stack size twice
In-Reply-To: <1276165636-20150-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <AANLkTinvvP7GFMHDoaw3SgIetd42Yyho1r9oMuiSIlnV@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
> ?arch/arm/boot/compressed/head.S | ? ?3 ++-
> ?1 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index c5191b1..390aa92 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -315,7 +315,7 @@ LC0: ? ? ? ? ? ? ? ?.word ? LC0 ? ? ? ? ? ? ? ? ? ? @ r1
> ? ? ? ? ? ? ? ?.word ? _image_size ? ? ? ? ? ? @ r6
> ? ? ? ? ? ? ? ?.word ? _got_start ? ? ? ? ? ? ?@ r11
> ? ? ? ? ? ? ? ?.word ? _got_end ? ? ? ? ? ? ? ?@ ip
> - ? ? ? ? ? ? ? .word ? user_stack+4096 ? ? ? ? @ sp
> + ? ? ? ? ? ? ? .word ? user_stack_end ? ? ? ? ?@ sp
> ?LC1: ? ? ? ? ? .word ? reloc_end - reloc_start
> ? ? ? ? ? ? ? ?.size ? LC0, . - LC0
>
> @@ -1070,3 +1070,4 @@ reloc_end:
> ? ? ? ? ? ? ? ?.align
> ? ? ? ? ? ? ? ?.section ".stack", "w"
> ?user_stack: ? ?.space ?4096
> +user_stack_end:

This one looks OK to me.

Acked-by: Eric Miao <eric.miao at canonical.com>

From sshtylyov at mvista.com  Thu Jun 10 06:43:34 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Thu, 10 Jun 2010 14:43:34 +0400
Subject: [PATCH v3] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
References: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <4C10C1D6.8080708@ru.mvista.com>

Kukjin Kim wrote:

> From: Abhilash Kesavan <a.kesavan at samsung.com>

> Adds support for the Samsung PATA controller. This driver is based on the
> Libata subsystem and references the earlier patches sent for IDE subsystem.

> Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>

[...]

> diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
> new file mode 100644
> index 0000000..fef5515
> --- /dev/null
> +++ b/drivers/ata/pata_samsung_cf.c
> @@ -0,0 +1,608 @@
> +/* linux/drivers/ata/pata_samsung_cf.c

    File names in the heading comment are discouraged.

[...]

> +static unsigned long
> +pata_s3c_setup_timing(struct s3c_ide_info *info, struct ata_device *adev)
> +{
> +	const struct ata_timing *timing;
> +	int cycle_time;
> +	int t1;
> +	int t2;
> +	int t2i;
> +	ulong piotime;
> +
> +	cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
> +
> +	timing = ata_timing_find_mode(adev->pio_mode);
> +	t1	= (timing->setup / cycle_time) & 0xf;
> +	t2	= (timing->act8b / cycle_time) & 0xff;
> +	t2i	= (timing->rec8b / cycle_time) & 0xff;

    Why are you still not using ata_timing_compute()?

> +
> +	piotime = (t2i << 12) | (t2 << 4) | t1;
> +
> +	return piotime;
> +}
> +
> +static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
> +{
> +	int mode = adev->pio_mode - XFER_PIO_0;
> +	struct s3c_ide_info *info = ap->host->private_data;
> +	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
> +	ulong piotime;
> +
> +	/* Calculates timing parameters for PIO mode */
> +	piotime = pata_s3c_setup_timing(info, adev);

    In fact, for 8-bit (command) timing you should program the slowest mode of 
the two drives. However, with CF, you probably only have only one drive per 
channel...

> +
> +	/* Enables IORDY if mode requires it */
> +	if (ata_pio_need_iordy(adev))
> +		ata_cfg |= S3C_ATA_CFG_IORDYEN;
> +	else
> +		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
> +
> +	/* Host controller supports upto PIO4 only */
> +	if (mode >= 0 && mode <= 4) {

    No need to check -- you won't be passed a mode not specified by your pio_mask.

> +		writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
> +		writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
> +	}
> +}

[...]

> +/*
> + * pata_s3c_data_xfer - Transfer data by PIO
> + */
> +unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char *buf,
> +				unsigned int buflen, int rw)
> +{
> +	struct ata_port *ap = dev->link->ap;
> +	struct s3c_ide_info *info = ap->host->private_data;
> +	void __iomem *data_addr = ap->ioaddr.data_addr;
> +	unsigned int words = buflen >> 1, i;
> +	u16 *data_ptr = (u16 *)buf;
> +
> +	if (rw == READ)
> +		for (i = 0; i < words; i++, data_ptr++) {
> +			wait_for_host_ready(info);
> +			*data_ptr = readw(data_addr);

    Why not just ignore the result?

> +			wait_for_host_ready(info);
> +			*data_ptr = readw(info->ide_addr
> +					+ S3C_ATA_PIO_RDATA);
> +		}
> +	else
> +		for (i = 0; i < words; i++, data_ptr++) {
> +			wait_for_host_ready(info);
> +			writel(*data_ptr, data_addr);
> +		}
> +
> +	return words << 1;
> +}

[...]

> +static struct ata_port_operations pata_s3c_port_ops = {
> +	.inherits		= &ata_sff_port_ops,
> +	.sff_check_status	= pata_s3c_check_status,
> +	.sff_check_altstatus    = pata_s3c_check_altstatus,
> +	.sff_tf_load		= pata_s3c_tf_load,
> +	.sff_tf_read		= pata_s3c_tf_read,
> +	.sff_data_xfer		= pata_s3c_data_xfer,
> +	.sff_exec_command	= pata_s3c_exec_command,
> +	.sff_dev_select         = pata_s3c_dev_select,
> +	.sff_set_devctl         = pata_s3c_set_devctl,

    I forgot: you also need to override the softreset() method as it accesses 
several taskfile registers and ioread8()/iowrite8() won't suffice -- Jeff was 
too quick to ack the patch. See ata_bus_softreset(), ata_devchk(), and 
ata_sff_wait_after_reset() for the accesses I'm talking about...

[...]

> +static int __devinit pata_s3c_probe(struct platform_device *pdev)
> +{
> +	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
> +	struct device *dev = &pdev->dev;
> +	struct s3c_ide_info *info;
> +	struct resource *res;
> +	struct ata_port *ap;
> +	struct ata_host *host;
> +	enum s3c_cpu_type cpu_type;
> +	int ret;
> +
> +	cpu_type = platform_get_device_id(pdev)->driver_data;
> +
> +	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
> +	if (!info) {
> +		dev_err(dev, "failed to allocate memory for device data\n");
> +		return -ENOMEM;
> +	}
> +
> +	info->irq = platform_get_irq(pdev, 0);
> +	if (info->irq < 0) {
> +		dev_err(dev, "could not obtain irq number\n");
> +		ret = -EINVAL;
> +		goto release_device_mem;
> +	}
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (res == NULL) {
> +		dev_err(dev, "failed to get mem resource\n");
> +		ret = -EINVAL;
> +		goto release_device_mem;
> +	}
> +
> +	if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {

    Probably should call devm_request_mem_region() if you're using 
devm_ioremap()...

> +		dev_err(dev, "error requesting register region\n");
> +		return -EBUSY;
> +	}
> +
> +	info->ide_addr = devm_ioremap(dev, res->start, resource_size(res));
> +	if (!info->ide_addr) {
> +		dev_err(dev, "failed to map IO base address\n");
> +		ret = -ENOMEM;
> +		goto release_mem;
> +	}
> +
> +	info->clk = clk_get(&pdev->dev, "cfcon");
> +	if (IS_ERR(info->clk)) {
> +		dev_err(dev, "failed to get access to cf controller clock\n");
> +		ret = PTR_ERR(info->clk);
> +		info->clk = NULL;

    No 'goto' here?

[...]

> +stop_clk:
> +	clk_disable(info->clk);

    Where is clk_put() call?

> +release_mem:
> +	release_mem_region(res->start, resource_size(res));
> +release_device_mem:
> +	kfree(info);

    Doesn't using devm_kzalloc() guarantee that the memory will be freed up 
automatically?

> +return ret;

    Wrong indentation.

> +static struct platform_driver pata_s3c_driver = {
> +	.probe		= pata_s3c_probe,
> 
> 

    2 empty lines -- broken patch?

> +	.remove		= __devexit_p(pata_s3c_remove),
> +	.id_table	= pata_s3c_driver_ids,
> +	.driver		= {
> +		.name	= DRV_NAME,
> +		.owner	= THIS_MODULE,
> +#ifdef CONFIG_PM
> +		.pm	= &pata_s3c_pm_ops,
> +#endif
> +	},
> +};

[...]

MBR, Sergei


From kgene.kim at samsung.com  Thu Jun 10 06:46:13 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 10 Jun 2010 19:46:13 +0900
Subject: [PATCH 3/5] sdhci-s3c: increase the timeout value
In-Reply-To: <1276076383-24825-4-git-send-email-m.szyprowski@samsung.com>
References: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
	<1276076383-24825-4-git-send-email-m.szyprowski@samsung.com>
Message-ID: <019301cb088a$29134970$7b39dc50$%kim@samsung.com>

Marek Szyprowski wrote:
> 
> This patch increases the timeout value on sdhci-s3c controller by using
> SDHCI_QUIRK_BROKEN_TIMEOUT_VAL quirk. Without it most transfers from
> external mmc cards fails on Samsung s5pv210 SoCs based systems. Tested
> on Samsung Aquila board.
> 

Hi,

Seems to use max timeout value, 0xE.
However, should be use SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK.
Because basically, Samsung MMC used sdclock as timeout clock.

Please refer to below URL:
http://article.gmane.org/gmane.linux.kernel.mmc/304

And new patch with SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK will be submitted.

> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  drivers/mmc/host/sdhci-s3c.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index ad30f07..2b6cb44 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -331,6 +331,7 @@ static int __devinit sdhci_s3c_probe(struct
platform_device
> *pdev)
>  	 * transfers, not sure if this is a problem with this specific
>  	 * SDHCI block, or a missing configuration that needs to be set. */
>  	host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
> +	host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
> 
>  	host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
>  			 SDHCI_QUIRK_32BIT_DMA_SIZE);
> --

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From saeed at marvell.com  Thu Jun 10 06:57:16 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Thu, 10 Jun 2010 13:57:16 +0300
Subject: [PATCH] [kirkwood-otg] Leverage the Freescale OTG driver for
	Kirkwood OTG
In-Reply-To: <AANLkTikVeVBdSfeS_p0k4dRwFopELw2OIXUrS1NjEdt6@mail.gmail.com>
References: <1276094138-13497-1-git-send-email-jason.mcmullan@netronome.com>
	<1276094138-13497-2-git-send-email-jason.mcmullan@netronome.com>
	<alpine.LFD.2.00.1006091307321.30664@xanadu.home>
	<AANLkTikVeVBdSfeS_p0k4dRwFopELw2OIXUrS1NjEdt6@mail.gmail.com>
Message-ID: <FCBE654890C0334289D0AD3AF4EF009F9FAC75ABB8@IL-MB01.marvell.com>

 

>-----Original Message-----
>From: Jason McMullan [mailto:jason.mcmullan at netronome.com] 
>Sent: Wednesday, June 09, 2010 9:07 PM
>To: Nicolas Pitre
>Cc: linux-arm-kernel at lists.infradead.org; Haavard Skinnemoen; 
>Ronen Shitrit; Saeed Bishara; Rabeeh Khoury; Guennadi 
>Liakhovetski; Li Yang; Lennert Buytenhek
>Subject: Re: [PATCH] [kirkwood-otg] Leverage the Freescale OTG 
>driver for Kirkwood OTG
>
>On Wed, Jun 9, 2010 at 1:17 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
>> On Wed, 9 Jun 2010, Jason S. McMullan wrote:
>>> NOTE: Your bootloader must ensure that the Kirkwood
>>> ? ? ? USB 2.0 Bridge Window registers are set correctly,
>>> ? ? ? or the driver will stall on the first DMA.
>>
>> Could you add the code to sets that up in the kernel instead?
>
>Will do.
>
>>> ?config USB_GADGET_FSL_USB2
>>
>> Maybe the help text should be extended to mention Kirkwood?
>
>Again, good idea, will do.
Jason, the USB on kirkwood (and all orions) doesn't support OTG feature, it only support device mode when the system configured for that mode, so please repace the "otg" with udc.
Saeed


From herman_swartz at yahoo.com  Thu Jun 10 07:11:35 2010
From: herman_swartz at yahoo.com (Herman Swartz)
Date: Thu, 10 Jun 2010 04:11:35 -0700 (PDT)
Subject: Context Switching is Broken
Message-ID: <503171.97993.qm@web51806.mail.re2.yahoo.com>

Context switching is broken. The man page for context is example code that doesn't work, but should.
Does a bug report need to be submitted?

Thanks 
Herman



      


From catalin.marinas at arm.com  Thu Jun 10 07:28:36 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 10 Jun 2010 12:28:36 +0100
Subject: [PATCH v2 1/4] ARM: Remove the domain switching on ARMv6k/v7 CPUs
In-Reply-To: <alpine.LFD.2.00.1006092039000.30664@xanadu.home>
References: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
	<20100602164841.17783.94825.stgit@e102109-lin.cambridge.arm.com>
	<alpine.LFD.2.00.1006091447460.30664@xanadu.home>
	<1276122405.17056.47.camel@toshiba-laptop>
	<alpine.LFD.2.00.1006092039000.30664@xanadu.home>
Message-ID: <1276169316.24535.32.camel@e102109-lin.cambridge.arm.com>

On Thu, 2010-06-10 at 01:56 +0100, Nicolas Pitre wrote:
> On Wed, 9 Jun 2010, Catalin Marinas wrote:
> 
> > On Wed, 2010-06-09 at 20:10 +0100, Nicolas Pitre wrote:
> > > Sorry for the delay... I'm just starting to seriously look at this.
> > >
> > > On Wed, 2 Jun 2010, Catalin Marinas wrote:
> > >
> > > > This patch removes the domain switching functionality via the set_fs and
> > > > __switch_to functions on cores that have a TLS register.
> > > [...]
> > > > The user pages access rights are also modified for kernel read-only
> > > > access rather than read/write so that the copy-on-write mechanism still
> > > > works. CPU_USE_DOMAINS gets disabled only if HAS_TLS_REG is defined
> > > > since writing the TLS value to the high vectors page isn't possible.
> > >
> > > I don't like this limitation much.
> > >
> > > Since the vector page has to be accessed somehow for FIQs anyway, and
> > > the current solution for that involves accesses through the direct
> > > mapping of the vector page, then this patch could be made to work on
> > > pre-ARMv6 systems too simply by adding the necessary cache ops around
> > > the TLS and FIQ updates.
> >
> > Getting rid of domains in Linux requires that several functions no
> > longer use LDRT/STRT but LDR/STR. This implies that RO user pages should
> > also have RO permissions for the kernel. I don't have the old ARM ARM at
> > hand now but I recall there were some issues with user RO kernel RO
> > permission on pre-ARMv6 processors (there is an R bit in the CP15
> > control register which may help, I need to check the documentation).
> 
> I just checked.  It says:
> 
>    The access permission bits in section and page descriptors control
>    access to the corresponding section or page. The access permissions
>    are modified by the System (S) and ROM (R) control bits in CP15
>    register 1.
> 
> But those bits are of no use as they are effective only when the MMU
> access permission bits are all 0, otherwise they're ignored.

OK. So for read-only user pages we could set AP to 00 and R to 1 so that
pages are read-only for kernel as well. For the other cases we just use
a non-zero AP.

> What I mean, though, is for this patch to work as well on VIVT systems
> by using the domain switching _only_ when updating the TLS value or the
> FIQ handler in the vector page.

And all the other times the domain would be set to client. That would
work but we still need to change set_pte_ext() for all the pre-ARMv6
processors since we need the user RO kernel RO permission (otherwise we
break the copy-on-write mechanism which is currently handled correctly
because we use STRT).

-- 
Catalin



From kgene.kim at samsung.com  Thu Jun 10 07:39:51 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 10 Jun 2010 20:39:51 +0900
Subject: [PATCH] sdhci-s3c: Add SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK quirk for
	Samsung SoC
Message-ID: <1276169991-16396-1-git-send-email-kgene.kim@samsung.com>

From: Lee Hyuk <hyuk1.lee at samsung.com>

On Samsung's SDMMC hosts the timeout clock is derivied from the SD
Clock, which is set dynamically.
So, checked 'SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK' quirk and removed
'sdhci_s3c_get_timeout_clk' callback which doesn't need any more.

Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 drivers/mmc/host/sdhci-s3c.c |   10 +++-------
 1 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index af21792..ca09382 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -110,11 +110,6 @@ static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
 	return max;
 }
 
-static unsigned int sdhci_s3c_get_timeout_clk(struct sdhci_host *host)
-{
-	return sdhci_s3c_get_max_clk(host) / 1000000;
-}
-
 /**
  * sdhci_s3c_consider_clock - consider one the bus clocks for current setting
  * @ourhost: Our SDHCI instance.
@@ -188,7 +183,6 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
 
 		ourhost->cur_clk = best_src;
 		host->max_clk = clk_get_rate(clk);
-		host->timeout_clk = sdhci_s3c_get_timeout_clk(host);
 
 		ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
 		ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
@@ -211,7 +205,6 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
 
 static struct sdhci_ops sdhci_s3c_ops = {
 	.get_max_clock		= sdhci_s3c_get_max_clk,
-	.get_timeout_clock	= sdhci_s3c_get_timeout_clk,
 	.set_clock		= sdhci_s3c_set_clock,
 };
 
@@ -335,6 +328,9 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
 			 SDHCI_QUIRK_32BIT_DMA_SIZE);
 
+	/* HSMMC on Samsung SoCs uses SDCLK as timeout clock. */
+	host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
+
 	ret = sdhci_add_host(host);
 	if (ret) {
 		dev_err(dev, "sdhci_add_host() failed\n");
-- 
1.6.2.5



From s.hauer at pengutronix.de  Thu Jun 10 07:49:45 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 10 Jun 2010 13:49:45 +0200
Subject: [PATCH] mxc: Fix pad names for imx51
In-Reply-To: <20100609130904.GA2599@eyjafjallajokull>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100604085320.GB25357@pengutronix.de>
	<20100604105347.GA2982@matterhorn.lan>
	<20100604140959.GB2982@matterhorn.lan>
	<4C0D5996.9050906@boundarydevices.com>
	<20100607210448.GA2446@matterhorn.lan>
	<4C0D6183.1010501@boundarydevices.com>
	<20100608063036.GB20799@pengutronix.de>
	<20100609130904.GA2599@eyjafjallajokull>
Message-ID: <20100610114945.GM20799@pengutronix.de>

On Wed, Jun 09, 2010 at 03:09:04PM +0200, Amit Kucheria wrote:
> On 10 Jun 08, Sascha Hauer wrote:
> > On Mon, Jun 07, 2010 at 02:15:47PM -0700, Troy Kisky wrote:
> > > Amit Kucheria wrote:
> > > > On 10 Jun 07, Troy Kisky wrote:
> > > > 
> > > >>> On 10 Jun 04, Amit Kucheria wrote:
> > > >>>
> > > > 
> > > > <snip>
> > > > 
> > > >>> +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27		IOMUX_PAD(0x614, 0x224,  3, 0x0,   0, NO_PAD_CTRL)
> > > > 
> > > > <snip>
> > > > 
> > > >>> +#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
> > > >>> +#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
> > > >>> +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
> > > >>> +#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
> > > >>> +#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
> > > >>> +#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
> > > >>> +#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
> > > >>> +#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
> > > >>> +#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
> > > >> Why all the stuttering?
> > > >> Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
> > > >>
> > > > 
> > > > Just following the convention use in the rest of imx devices. See the
> > > > following comment at the top of the file:
> > > > 
> > > > /*
> > > >  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
> > > >  * If <padname> or <padmode> refers to a GPIO, it is named
> > > >  * GPIO_<unit>_<num> see also iomux-v3.h
> > > >  */
> > > > 
> > > > We could use the short names for pads being used in their "native mode".
> > > > But as soon as we use the pad in a different mode, such as
> > > > PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
> > > > 
> > > > Regards,
> > > > Amit
> > > > 
> > > 
> > > I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for
> > > MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to
> > > 
> > >  /*
> > >   * The naming convention for the pad modes is MX51_PAD_<padname>
> > >   * or MX51_PAD_<padname>__<padmode> if padname != padmode.
> > >   * If <padname> or <padmode> refers to a GPIO, it is named
> > >   * GPIO_<unit>_<num> see also iomux-v3.h
> > >   */
> > 
> > If anything then MX51_PAD_GPIO_<unit>_<num>. I chose to use the long
> > name to get a consistent naming and to express the fact that the pad has
> > a name and the mode has a name which can but don't has to be the same.
> > 
> 
> So will you take a modified patch to reflect this new naming convention?

Unless there are strong opinions for short names I'd like to keep the
old naming scheme as it is also used for other i.MX SoCs.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From wim at iguana.be  Thu Jun 10 07:25:20 2010
From: wim at iguana.be (Wim Van Sebroeck)
Date: Thu, 10 Jun 2010 13:25:20 +0200
Subject: [PATCH 3/3] imx2_wdt: fix section mismatch
In-Reply-To: <31360d4c97db0e754d15f27567b4592010bdd831.1276081393.git.baruch@tkos.co.il>
References: <cover.1276081393.git.baruch@tkos.co.il>
	<31360d4c97db0e754d15f27567b4592010bdd831.1276081393.git.baruch@tkos.co.il>
Message-ID: <20100610112520.GJ3788@infomag.iguana.be>

> diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
> index ea25885..2ee7dac 100644
> --- a/drivers/watchdog/imx2_wdt.c
> +++ b/drivers/watchdog/imx2_wdt.c
> @@ -330,7 +330,6 @@ static void imx2_wdt_shutdown(struct platform_device *pdev)
>  }
>  
>  static struct platform_driver imx2_wdt_driver = {
> -	.probe		= imx2_wdt_probe,
>  	.remove		= __exit_p(imx2_wdt_remove),
>  	.shutdown	= imx2_wdt_shutdown,
>  	.driver		= {

Added to linux-2.6-watchdog-next.

Kind regards,
Wim.



From m.szyprowski at samsung.com  Thu Jun 10 08:06:03 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Thu, 10 Jun 2010 14:06:03 +0200
Subject: [PATCH 5/5 fixed] sdhci-s3c: add support for new card detection
	methods
In-Reply-To: <1276076383-24825-6-git-send-email-m.szyprowski@samsung.com>
References: <1276076383-24825-6-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276171563-6612-1-git-send-email-m.szyprowski@samsung.com>

On some Samsung SoCs not all SDHCI controllers have card detect (CD)
line. For some embedded designs it is not even needed, because ususally
the device (like SDIO flash memory or wifi controller) is permanently
wired to the controller. There are also systems which have a card detect
line connected to some of the external interrupt lines or the presence
of the card depends on some other actions (like enabling a power
regulator).

This patch adds support for all these cases. The following card
detection methods are possible:

1. internal sdhci host card detect line
2. external event
3. no card detect line, controller will poll for the card
4. no card detect line, card is permanently wired to the controller
(once detected host won't poll it any more)

By default, all existing code would use method #1, what is compatible
with the previous version of the driver.

In case of external event, two callbacks must be provided in platdata:
ext_cd_init and ext_cd_cleanup. Both of them get a callback to a
function that notifies the s3c-sdhci host contoller as their argument.
That callback function should be called from the even dispatcher to let
host notice the card insertion/removal.

This patch adds changes to sdhci-s3c driver.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---

This is a quick resend, in the previous version one line was missing in the
sdhci_s3c_remove() function causing a compilation break.

 drivers/mmc/host/sdhci-s3c.c |   39 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 39 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index 615008d..f472295 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -242,6 +242,29 @@ static struct sdhci_ops sdhci_s3c_ops = {
 	.get_min_clock		= sdhci_s3c_get_min_clock,
 };
 
+static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
+{
+	struct sdhci_host *host;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	host = platform_get_drvdata(dev);
+	if (host) {
+		if (state) {
+			dev_info(&dev->dev, "card inserted.\n");
+			host->flags &= ~SDHCI_DEVICE_DEAD;
+			host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+			tasklet_schedule(&host->card_tasklet);
+		} else {
+			dev_info(&dev->dev, "card removed.\n");
+			host->flags |= SDHCI_DEVICE_DEAD;
+			host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+			tasklet_schedule(&host->card_tasklet);
+		}
+	}
+	local_irq_restore(flags);
+}
+
 static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 {
 	struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
@@ -362,6 +385,13 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
 	host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
 
+	if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
+	    pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
+		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+
+	if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
+		host->mmc->caps = MMC_CAP_NONREMOVABLE;
+
 	host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
 			 SDHCI_QUIRK_32BIT_DMA_SIZE);
 
@@ -371,6 +401,11 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 		goto err_add_host;
 	}
 
+	/* pdata->ext_cd_init might call sdhci_s3c_notify_change immediately,
+	   so it can be called only after sdhci_add_host() */
+	if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init)
+		pdata->ext_cd_init(&sdhci_s3c_notify_change);
+
 	return 0;
 
  err_add_host:
@@ -395,10 +430,14 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 
 static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
 {
+	struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
 	struct sdhci_host *host =  platform_get_drvdata(pdev);
 	struct sdhci_s3c *sc = sdhci_priv(host);
 	int ptr;
 
+	if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup)
+		pdata->ext_cd_cleanup(&sdhci_s3c_notify_change);
+
 	sdhci_remove_host(host, 1);
 
 	for (ptr = 0; ptr < 3; ptr++) {
-- 
1.7.1.240.g225c



From jason.mcmullan at netronome.com  Thu Jun 10 09:04:23 2010
From: jason.mcmullan at netronome.com (Jason McMullan)
Date: Thu, 10 Jun 2010 09:04:23 -0400
Subject: [PATCH] [kirkwood-otg] Leverage the Freescale OTG driver for 
	Kirkwood OTG
In-Reply-To: <FCBE654890C0334289D0AD3AF4EF009F9FAC75ABB8@IL-MB01.marvell.com>
References: <1276094138-13497-1-git-send-email-jason.mcmullan@netronome.com>
	<1276094138-13497-2-git-send-email-jason.mcmullan@netronome.com>
	<alpine.LFD.2.00.1006091307321.30664@xanadu.home>
	<AANLkTikVeVBdSfeS_p0k4dRwFopELw2OIXUrS1NjEdt6@mail.gmail.com>
	<FCBE654890C0334289D0AD3AF4EF009F9FAC75ABB8@IL-MB01.marvell.com>
Message-ID: <AANLkTinIkve83opXyCMWuYP-4H2lf-DF5WnlzzA1qH3s@mail.gmail.com>

On Thu, Jun 10, 2010 at 6:57 AM, Saeed Bishara <saeed at marvell.com> wrote:
> Jason, the USB on kirkwood (and all orions) doesn't support OTG feature, it only support device mode when the system configured for that mode, so please repace the "otg" with udc.

Ack! Will do!


-- 
Jason S. McMullan
Netronome Systems, Inc.


From jason77.wang at gmail.com  Thu Jun 10 09:04:50 2010
From: jason77.wang at gmail.com (jason)
Date: Thu, 10 Jun 2010 21:04:50 +0800
Subject: [PATCH] mxc: Fix pad names for imx51
In-Reply-To: <20100610114945.GM20799@pengutronix.de>
References: <1275566746-6510-1-git-send-email-jason77.wang@gmail.com>
	<1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100604085320.GB25357@pengutronix.de>
	<20100604105347.GA2982@matterhorn.lan>
	<20100604140959.GB2982@matterhorn.lan>
	<4C0D5996.9050906@boundarydevices.com>
	<20100607210448.GA2446@matterhorn.lan>
	<4C0D6183.1010501@boundarydevices.com>
	<20100608063036.GB20799@pengutronix.de>
	<20100609130904.GA2599@eyjafjallajokull>
	<20100610114945.GM20799@pengutronix.de>
Message-ID: <4C10E2F2.6080200@gmail.com>

Sascha Hauer wrote:
> On Wed, Jun 09, 2010 at 03:09:04PM +0200, Amit Kucheria wrote:
>   
>> On 10 Jun 08, Sascha Hauer wrote:
>>     
>>> On Mon, Jun 07, 2010 at 02:15:47PM -0700, Troy Kisky wrote:
>>>       
>>>> Amit Kucheria wrote:
>>>>         
>>>>> On 10 Jun 07, Troy Kisky wrote:
>>>>>
>>>>>           
>>>>>>> On 10 Jun 04, Amit Kucheria wrote:
>>>>>>>
>>>>>>>               
>>>>> <snip>
>>>>>
>>>>>           
>>>>>>> +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27		IOMUX_PAD(0x614, 0x224,  3, 0x0,   0, NO_PAD_CTRL)
>>>>>>>               
>>>>> <snip>
>>>>>
>>>>>           
>>>>>>> +#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>> +#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>> +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>> +#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>> +#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>> +#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>> +#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
>>>>>>> +#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
>>>>>>> +#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>>               
>>>>>> Why all the stuttering?
>>>>>> Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
>>>>>>
>>>>>>             
>>>>> Just following the convention use in the rest of imx devices. See the
>>>>> following comment at the top of the file:
>>>>>
>>>>> /*
>>>>>  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
>>>>>  * If <padname> or <padmode> refers to a GPIO, it is named
>>>>>  * GPIO_<unit>_<num> see also iomux-v3.h
>>>>>  */
>>>>>
>>>>> We could use the short names for pads being used in their "native mode".
>>>>> But as soon as we use the pad in a different mode, such as
>>>>> PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
>>>>>
>>>>> Regards,
>>>>> Amit
>>>>>
>>>>>           
>>>> I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for
>>>> MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to
>>>>
>>>>  /*
>>>>   * The naming convention for the pad modes is MX51_PAD_<padname>
>>>>   * or MX51_PAD_<padname>__<padmode> if padname != padmode.
>>>>   * If <padname> or <padmode> refers to a GPIO, it is named
>>>>   * GPIO_<unit>_<num> see also iomux-v3.h
>>>>   */
>>>>         
>>> If anything then MX51_PAD_GPIO_<unit>_<num>. I chose to use the long
>>> name to get a consistent naming and to express the fact that the pad has
>>> a name and the mode has a name which can but don't has to be the same.
>>>
>>>       
>> So will you take a modified patch to reflect this new naming convention?
>>     
>
> Unless there are strong opinions for short names I'd like to keep the
> old naming scheme as it is also used for other i.MX SoCs.
>
> Sascha
>
>
>   
 From the discussion, it seems that Amit's patch for iomux-mx51.h is the 
best choice,
So i will rebase my patches off that. Is it acceptable?

Thanks,
Jason.



From robert.jarzmik at free.fr  Thu Jun 10 09:14:52 2010
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Thu, 10 Jun 2010 15:14:52 +0200
Subject: usb gadget on zaurus and kexec
In-Reply-To: <201006100900.23981.marek.vasut@gmail.com> (Marek Vasut's message
	of "Thu, 10 Jun 2010 09:00:23 +0200")
References: <20100519154618.GA26381@atrey.karlin.mff.cuni.cz>
	<AANLkTim49akRJK0BN_Qk1wL6e5mrdjZioDjGNWlrjUVQ@mail.gmail.com>
	<AANLkTilCvgvf9Ch55f878nTNTue8tHYmcrLEywsjnylY@mail.gmail.com>
	<201006100900.23981.marek.vasut@gmail.com>
Message-ID: <87wru7xc4z.fsf@free.fr>

Marek Vasut <marek.vasut at gmail.com> writes:

>> > Dumping out the registers of the two situations and doing a comparison
>> > then might be a quick way.
>> 
>> Any debugging update on this?
>
> Yeah, there's a workaround. Cyril's working on a proper fix, but that might take 
> some time. Simply -- UP2OCR is misconfigured.

That's quite interesting. In the pxa27x_udc gadget driver, I seem to have a
regression on the resume from suspend to RAM path. My USB UDC is not enumerated
anymore.

The might be a correlation, as UP2OCR is lost in the suspend process. I'm very
interested by your analysis of the issue you have on kexec, as that might ease
my work :)

Besides, it's been some time I've been thinking that the pxa deserves a proper
encapsulation of the USB internal routing paths (ie. a proper way to switch from
usb host handled by ohci-pxa27x to an usb client handled by pxa2x_udc), to
reflect the setup of the Pad Unit (see TRM chapter 12.4 : tables 12.2, 12.15,
12.17, 12.18 and 12.19).

Whatever you find on the USB Port2 configuration register would help me design
the Pad block.

Cheers.

--
Robert


From pavel at ucw.cz  Thu Jun 10 09:56:10 2010
From: pavel at ucw.cz (Pavel Machek)
Date: Thu, 10 Jun 2010 15:56:10 +0200
Subject: [PATCH] sa1111: Prevent deadlock in resume path
In-Reply-To: <20100526201824.GA16418@n2100.arm.linux.org.uk>
References: <1274901104-22133-1-git-send-email-marek.vasut@gmail.com>
	<20100526191425.GD6232@n2100.arm.linux.org.uk>
	<201005262115.57282.marek.vasut@gmail.com>
	<20100526201824.GA16418@n2100.arm.linux.org.uk>
Message-ID: <20100610135609.GC4514@ucw.cz>

On Wed 2010-05-26 21:18:24, Russell King - ARM Linux wrote:
> On Wed, May 26, 2010 at 09:15:57PM +0200, Marek Vasut wrote:
> > Dne St 26. kv?tna 2010 21:14:25 Russell King - ARM Linux napsal(a):
> > > On Wed, May 26, 2010 at 09:11:44PM +0200, Marek Vasut wrote:
> > > > This patch reorganises the sa1111_resume() function in a manner the
> > > > spinlock happens after calling the sa1111_wake(). This fixes two bugs:
> > > > 
> > > > 1) This function called sa1111_wake() which tried to claim the same
> > > > spinlock
> > > > 
> > > >    the sa1111_resume() already claimed. This would result in certain
> > > >    deadlock.
> > > >    
> > > >    Original idea for this part: Russell King <linux at arm.linux.org.uk>
> > > > 
> > > > 2) The function didn't unlock the spinlock in case the chip didn't report
> > > > 
> > > >    correct ID.
> > > >    
> > > >    Original idea for this part: Julia Lawall <julia at diku.dk>
> > > > 
> > > > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> > > 
> > > Yea, good enough.
> > 
> > You want me to fight your patch tracking system or will you just merge it into 
> > your tree ?
> 
> What do you mean "fight" ?  Just send a standard git formatted patch
> to the email address with an additional KernelVersion: tag.  It's
> not at all hard.

You are linux kernel maintainer. Start acting as one. It is not at all
hard.

Alternatively, just remove KernelVersion: checking in  your
scripts.

									Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From s.hauer at pengutronix.de  Thu Jun 10 09:59:10 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 10 Jun 2010 15:59:10 +0200
Subject: [PATCH] mxc: Fix pad names for imx51
In-Reply-To: <4C10E2F2.6080200@gmail.com>
References: <20100604085320.GB25357@pengutronix.de>
	<20100604105347.GA2982@matterhorn.lan>
	<20100604140959.GB2982@matterhorn.lan>
	<4C0D5996.9050906@boundarydevices.com>
	<20100607210448.GA2446@matterhorn.lan>
	<4C0D6183.1010501@boundarydevices.com>
	<20100608063036.GB20799@pengutronix.de>
	<20100609130904.GA2599@eyjafjallajokull>
	<20100610114945.GM20799@pengutronix.de>
	<4C10E2F2.6080200@gmail.com>
Message-ID: <20100610135910.GS20799@pengutronix.de>

On Thu, Jun 10, 2010 at 09:04:50PM +0800, jason wrote:
> Sascha Hauer wrote:
>> On Wed, Jun 09, 2010 at 03:09:04PM +0200, Amit Kucheria wrote:
>>   
>>> On 10 Jun 08, Sascha Hauer wrote:
>>>     
>>>> On Mon, Jun 07, 2010 at 02:15:47PM -0700, Troy Kisky wrote:
>>>>       
>>>>> Amit Kucheria wrote:
>>>>>         
>>>>>> On 10 Jun 07, Troy Kisky wrote:
>>>>>>
>>>>>>           
>>>>>>>> On 10 Jun 04, Amit Kucheria wrote:
>>>>>>>>
>>>>>>>>               
>>>>>> <snip>
>>>>>>
>>>>>>           
>>>>>>>> +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27		IOMUX_PAD(0x614, 0x224,  3, 0x0,   0, NO_PAD_CTRL)
>>>>>>>>               
>>>>>> <snip>
>>>>>>
>>>>>>           
>>>>>>>> +#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>>> +#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>>> +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>>> +#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>>> +#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>>> +#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>>> +#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
>>>>>>>> +#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
>>>>>>>> +#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
>>>>>>>>               
>>>>>>> Why all the stuttering?
>>>>>>> Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
>>>>>>>
>>>>>>>             
>>>>>> Just following the convention use in the rest of imx devices. See the
>>>>>> following comment at the top of the file:
>>>>>>
>>>>>> /*
>>>>>>  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
>>>>>>  * If <padname> or <padmode> refers to a GPIO, it is named
>>>>>>  * GPIO_<unit>_<num> see also iomux-v3.h
>>>>>>  */
>>>>>>
>>>>>> We could use the short names for pads being used in their "native mode".
>>>>>> But as soon as we use the pad in a different mode, such as
>>>>>> PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
>>>>>>
>>>>>> Regards,
>>>>>> Amit
>>>>>>
>>>>>>           
>>>>> I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for
>>>>> MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to
>>>>>
>>>>>  /*
>>>>>   * The naming convention for the pad modes is MX51_PAD_<padname>
>>>>>   * or MX51_PAD_<padname>__<padmode> if padname != padmode.
>>>>>   * If <padname> or <padmode> refers to a GPIO, it is named
>>>>>   * GPIO_<unit>_<num> see also iomux-v3.h
>>>>>   */
>>>>>         
>>>> If anything then MX51_PAD_GPIO_<unit>_<num>. I chose to use the long
>>>> name to get a consistent naming and to express the fact that the pad has
>>>> a name and the mode has a name which can but don't has to be the same.
>>>>
>>>>       
>>> So will you take a modified patch to reflect this new naming convention?
>>>     
>>
>> Unless there are strong opinions for short names I'd like to keep the
>> old naming scheme as it is also used for other i.MX SoCs.
>>
>> Sascha
>>
>>
>>   
> From the discussion, it seems that Amit's patch for iomux-mx51.h is the  
> best choice,
> So i will rebase my patches off that. Is it acceptable?

Yes, ok.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From benjamin.zores at alcatel-lucent.com  Thu Jun 10 09:59:41 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Thu, 10 Jun 2010 15:59:41 +0200
Subject: [PATCH 2/4] arch/arm/mach-kirkwood: add support for 88F6282-A0
	revision
In-Reply-To: <20100610135936.14097.22635.stgit@localhost.localdomain>
References: <20100610135936.14097.22635.stgit@localhost.localdomain>
Message-ID: <20100610135941.14097.73238.stgit@localhost.localdomain>

Signed-off-by: Benjamin Zores <benjamin.zores at alcatel-lucent.com>
---
 arch/arm/mach-kirkwood/common.c                |   10 +++++++++-
 arch/arm/mach-kirkwood/include/mach/kirkwood.h |    5 ++++-
 arch/arm/mach-kirkwood/mpp.c                   |    2 ++
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 6072eaa..94f629d 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -402,7 +402,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
 	u32 dev, rev;
 
 	kirkwood_pcie_id(&dev, &rev);
-	if (rev == 0)  /* catch all Kirkwood Z0's */
+	if (rev == 0 && dev != MV88F6282_DEV_ID)  /* catch all Kirkwood Z0's and 6282 */
 		mvsdio_data->clock = 100000000;
 	else
 		mvsdio_data->clock = 200000000;
@@ -851,6 +851,9 @@ int __init kirkwood_find_tclk(void)
 					rev == MV88F6281_REV_A1))
 		return 200000000;
 
+	if (dev == MV88F6282_DEV_ID)
+		return 200000000;
+
 	return 166666667;
 }
 
@@ -886,6 +889,11 @@ static char * __init kirkwood_id(void)
 			return "MV88F6281-A1";
 		else
 			return "MV88F6281-Rev-Unsupported";
+	} if (dev == MV88F6282_DEV_ID) {
+		if (rev == MV88F6282_REV_A0)
+			return "MV88F6282-A0";
+		else
+			return "MV88F6282-Rev-Unsupported";
 	} else if (dev == MV88F6192_DEV_ID) {
 		if (rev == MV88F6192_REV_Z0)
 			return "MV88F6192-Z0";
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a15cf0e..a571860 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -2,7 +2,7 @@
  * arch/arm/mach-kirkwood/include/mach/kirkwood.h
  *
  * Generic definitions for Marvell Kirkwood SoC flavors:
- *  88F6180, 88F6192 and 88F6281.
+ *  88F6180, 88F6192, 88F6281 and 88F6282.
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
@@ -104,6 +104,9 @@
 #define MV88F6281_REV_A0	2
 #define MV88F6281_REV_A1	3
 
+#define MV88F6282_DEV_ID	0x6282
+#define MV88F6282_REV_A0	0
+
 #define MV88F6192_DEV_ID	0x6192
 #define MV88F6192_REV_Z0	0
 #define MV88F6192_REV_A0	2
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index a5900f6..330a5a1 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -25,6 +25,8 @@ static unsigned int __init kirkwood_variant(void)
 
 	if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
 		return MPP_F6281_MASK;
+	if (dev == MV88F6282_DEV_ID && rev >= MV88F6282_REV_A0)
+		return MPP_F6282_MASK;
 	if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
 		return MPP_F6192_MASK;
 	if (dev == MV88F6180_DEV_ID)



From benjamin.zores at alcatel-lucent.com  Thu Jun 10 09:59:36 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Thu, 10 Jun 2010 15:59:36 +0200
Subject: [PATCH 1/4] arch/arm/mach-kirkwood: update MPP definition.
Message-ID: <20100610135936.14097.22635.stgit@localhost.localdomain>

Add MPP definitions for Marvell Kirkwood 88F6282 revision.
Update some defines to reflect datasheet's MPP names.

Signed-off-by: Benjamin Zores <benjamin.zores at alcatel-lucent.com>
---
 arch/arm/mach-kirkwood/mpp.h               |  595 +++++++++++++++-------------
 arch/arm/mach-kirkwood/netspace_v2-setup.c |    4 
 arch/arm/mach-kirkwood/netxbig_v2-setup.c  |   32 +-
 arch/arm/mach-kirkwood/ts219-setup.c       |    4 
 arch/arm/mach-kirkwood/ts41x-setup.c       |   28 +
 5 files changed, 356 insertions(+), 307 deletions(-)

diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index bc74278..51a2974 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -11,7 +11,7 @@
 #ifndef __KIRKWOOD_MPP_H
 #define __KIRKWOOD_MPP_H
 
-#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
+#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \
 	/* MPP number */		((_num) & 0xff) | \
 	/* MPP select value */		(((_sel) & 0xf) << 8) | \
 	/* may be input signal */	((!!(_in)) << 12) | \
@@ -19,282 +19,331 @@
 	/* available on F6180 */	((!!(_F6180)) << 14) | \
 	/* available on F6190 */	((!!(_F6190)) << 15) | \
 	/* available on F6192 */	((!!(_F6192)) << 16) | \
-	/* available on F6281 */	((!!(_F6281)) << 17))
+	/* available on F6281 */	((!!(_F6281)) << 17) | \
+	/* available on F6282 */	((!!(_F6282)) << 18))
 
 #define MPP_NUM(x)	((x) & 0xff)
 #define MPP_SEL(x)	(((x) >> 8) & 0xf)
 
-				/*   num sel  i  o  6180 6190 6192 6281 */
-
-#define MPP_INPUT_MASK		MPP(  0, 0x0, 1, 0, 0,   0,   0,   0    )
-#define MPP_OUTPUT_MASK		MPP(  0, 0x0, 0, 1, 0,   0,   0,   0    )
-
-#define MPP_F6180_MASK		MPP(  0, 0x0, 0, 0, 1,   0,   0,   0    )
-#define MPP_F6190_MASK		MPP(  0, 0x0, 0, 0, 0,   1,   0,   0    )
-#define MPP_F6192_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   1,   0    )
-#define MPP_F6281_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   0,   1    )
-
-#define MPP0_GPIO		MPP(  0, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP0_NF_IO2		MPP(  0, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP0_SPI_SCn		MPP(  0, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP1_GPO		MPP(  1, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP1_NF_IO3		MPP(  1, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP1_SPI_MOSI		MPP(  1, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP2_GPO		MPP(  2, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP2_NF_IO4		MPP(  2, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP2_SPI_SCK		MPP(  2, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP3_GPO		MPP(  3, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP3_NF_IO5		MPP(  3, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP3_SPI_MISO		MPP(  3, 0x2, 1, 0, 1,   1,   1,   1    )
-
-#define MPP4_GPIO		MPP(  4, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP4_NF_IO6		MPP(  4, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP4_UART0_RXD		MPP(  4, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP4_SATA1_ACTn		MPP(  4, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP4_PTP_CLK		MPP(  4, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP5_GPO		MPP(  5, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP5_NF_IO7		MPP(  5, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP5_UART0_TXD		MPP(  5, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP5_PTP_TRIG_GEN	MPP(  5, 0x4, 0, 1, 1,   1,   1,   1    )
-#define MPP5_SATA0_ACTn		MPP(  5, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP6_SYSRST_OUTn	MPP(  6, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP6_SPI_MOSI		MPP(  6, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP6_PTP_TRIG_GEN	MPP(  6, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP7_GPO		MPP(  7, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PEX_RST_OUTn	MPP(  7, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP7_SPI_SCn		MPP(  7, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PTP_TRIG_GEN	MPP(  7, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP8_GPIO		MPP(  8, 0x0, 1, 1, 1,    1,  1,   1    )
-#define MPP8_TW_SDA		MPP(  8, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP8_UART0_RTS		MPP(  8, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP8_UART1_RTS		MPP(  8, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP8_MII0_RXERR		MPP(  8, 0x4, 1, 0, 0,   1,   1,   1    )
-#define MPP8_SATA1_PRESENTn	MPP(  8, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP8_PTP_CLK		MPP(  8, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP8_MII0_COL		MPP(  8, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP9_GPIO		MPP(  9, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP9_TW_SCK		MPP(  9, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP9_UART0_CTS		MPP(  9, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP9_UART1_CTS		MPP(  9, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP9_SATA0_PRESENTn	MPP(  9, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP9_PTP_EVENT_REQ	MPP(  9, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP9_MII0_CRS		MPP(  9, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP10_GPO		MPP( 10, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SPI_SCK		MPP( 10, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP10_UART0_TXD		MPP( 10, 0X3, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SATA1_ACTn	MPP( 10, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP10_PTP_TRIG_GEN	MPP( 10, 0xc, 0, 1, 1,   1,   1,   1    )
-
-#define MPP11_GPIO		MPP( 11, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP11_SPI_MISO		MPP( 11, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP11_UART0_RXD		MPP( 11, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_EVENT_REQ	MPP( 11, 0x4, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_TRIG_GEN	MPP( 11, 0xc, 0, 1, 1,   1,   1,   1    )
-#define MPP11_PTP_CLK		MPP( 11, 0xd, 1, 0, 1,   1,   1,   1    )
-#define MPP11_SATA0_ACTn	MPP( 11, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP12_GPO		MPP( 12, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP12_SD_CLK		MPP( 12, 0x1, 0, 1, 1,   1,   1,   1    )
-
-#define MPP13_GPIO		MPP( 13, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP13_SD_CMD		MPP( 13, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP13_UART1_TXD		MPP( 13, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP14_GPIO		MPP( 14, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP14_SD_D0		MPP( 14, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP14_UART1_RXD		MPP( 14, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP14_SATA1_PRESENTn	MPP( 14, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP14_MII0_COL		MPP( 14, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP15_GPIO		MPP( 15, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP15_SD_D1		MPP( 15, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP15_UART0_RTS		MPP( 15, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP15_UART1_TXD		MPP( 15, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP15_SATA0_ACTn	MPP( 15, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP16_GPIO		MPP( 16, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP16_SD_D2		MPP( 16, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP16_UART0_CTS		MPP( 16, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP16_UART1_RXD		MPP( 16, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP16_SATA1_ACTn	MPP( 16, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP16_MII0_CRS		MPP( 16, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP17_GPIO		MPP( 17, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SD_D3		MPP( 17, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SATA0_PRESENTn	MPP( 17, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP18_GPO		MPP( 18, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP18_NF_IO0		MPP( 18, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP19_GPO		MPP( 19, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP19_NF_IO1		MPP( 19, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP20_GPIO		MPP( 20, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP20_TSMP0		MPP( 20, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP20_TDM_CH0_TX_QL	MPP( 20, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP20_GE1_0		MPP( 20, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP20_AUDIO_SPDIFI	MPP( 20, 0x4, 1, 0, 0,   0,   1,   1    )
-#define MPP20_SATA1_ACTn	MPP( 20, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP21_GPIO		MPP( 21, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP21_TSMP1		MPP( 21, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP21_TDM_CH0_RX_QL	MPP( 21, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP21_GE1_1		MPP( 21, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP21_AUDIO_SPDIFO	MPP( 21, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP21_SATA0_ACTn	MPP( 21, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP22_GPIO		MPP( 22, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP22_TSMP2		MPP( 22, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP22_TDM_CH2_TX_QL	MPP( 22, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP22_GE1_2		MPP( 22, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP22_AUDIO_SPDIFRMKCLK	MPP( 22, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP22_SATA1_PRESENTn	MPP( 22, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP23_GPIO		MPP( 23, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP23_TSMP3		MPP( 23, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP23_TDM_CH2_RX_QL	MPP( 23, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP23_GE1_3		MPP( 23, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP23_AUDIO_I2SBCLK	MPP( 23, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP23_SATA0_PRESENTn	MPP( 23, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP24_GPIO		MPP( 24, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP24_TSMP4		MPP( 24, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP24_TDM_SPI_CS0	DEV( 24, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP24_GE1_4		MPP( 24, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP24_AUDIO_I2SDO	MPP( 24, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP25_GPIO		MPP( 25, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP25_TSMP5		MPP( 25, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP25_TDM_SPI_SCK	MPP( 25, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP25_GE1_5		MPP( 25, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP25_AUDIO_I2SLRCLK	MPP( 25, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP26_GPIO		MPP( 26, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP26_TSMP6		MPP( 26, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP26_TDM_SPI_MISO	MPP( 26, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP26_GE1_6		MPP( 26, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP26_AUDIO_I2SMCLK	MPP( 26, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP27_GPIO		MPP( 27, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP27_TSMP7		MPP( 27, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP27_TDM_SPI_MOSI	MPP( 27, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP27_GE1_7		MPP( 27, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP27_AUDIO_I2SDI	MPP( 27, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP28_GPIO		MPP( 28, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP28_TSMP8		MPP( 28, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP28_TDM_CODEC_INTn	MPP( 28, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP28_GE1_8		MPP( 28, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP28_AUDIO_EXTCLK	MPP( 28, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP29_GPIO		MPP( 29, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP29_TSMP9		MPP( 29, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP29_TDM_CODEC_RSTn	MPP( 29, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP29_GE1_9		MPP( 29, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP30_GPIO		MPP( 30, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP30_TSMP10		MPP( 30, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP30_TDM_PCLK		MPP( 30, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP30_GE1_10		MPP( 30, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP31_GPIO		MPP( 31, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP31_TSMP11		MPP( 31, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP31_TDM_FS		MPP( 31, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP31_GE1_11		MPP( 31, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP32_GPIO		MPP( 32, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP32_TSMP12		MPP( 32, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP32_TDM_DRX		MPP( 32, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP32_GE1_12		MPP( 32, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP33_GPIO		MPP( 33, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP33_TDM_DTX		MPP( 33, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP33_GE1_13		MPP( 33, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP34_GPIO		MPP( 34, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP34_TDM_SPI_CS1	MPP( 34, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP34_GE1_14		MPP( 34, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP35_GPIO		MPP( 35, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP35_TDM_CH0_TX_QL	MPP( 35, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP35_GE1_15		MPP( 35, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP35_SATA0_ACTn	MPP( 35, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP35_MII0_RXERR	MPP( 35, 0xc, 1, 0, 1,   1,   1,   1    )
-
-#define MPP36_GPIO		MPP( 36, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP36_TSMP0		MPP( 36, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP36_TDM_SPI_CS1	MPP( 36, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP36_AUDIO_SPDIFI	MPP( 36, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP37_GPIO		MPP( 37, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP37_TSMP1		MPP( 37, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP37_TDM_CH2_TX_QL	MPP( 37, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP37_AUDIO_SPDIFO	MPP( 37, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP38_GPIO		MPP( 38, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP38_TSMP2		MPP( 38, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP38_TDM_CH2_RX_QL	MPP( 38, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP38_AUDIO_SPDIFRMLCLK	MPP( 38, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP39_GPIO		MPP( 39, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP39_TSMP3		MPP( 39, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP39_TDM_SPI_CS0	MPP( 39, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP39_AUDIO_I2SBCLK	MPP( 39, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP40_GPIO		MPP( 40, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP40_TSMP4		MPP( 40, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP40_TDM_SPI_SCK	MPP( 40, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP40_AUDIO_I2SDO	MPP( 40, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP41_GPIO		MPP( 41, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP41_TSMP5		MPP( 41, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP41_TDM_SPI_MISO	MPP( 41, 0x2, 1, 0, 0,   0,   0,   1    )
-#define MPP41_AUDIO_I2SLRC	MPP( 41, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP42_GPIO		MPP( 42, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP42_TSMP6		MPP( 42, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP42_TDM_SPI_MOSI	MPP( 42, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP42_AUDIO_I2SMCLK	MPP( 42, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP43_GPIO		MPP( 43, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP43_TSMP7		MPP( 43, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP43_TDM_CODEC_INTn	MPP( 43, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP43_AUDIO_I2SDI	MPP( 43, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP44_GPIO		MPP( 44, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP44_TSMP8		MPP( 44, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP44_TDM_CODEC_RSTn	MPP( 44, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP44_AUDIO_EXTCLK	MPP( 44, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP45_GPIO		MPP( 45, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TSMP9		MPP( 45, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TDM_PCLK		MPP( 45, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP46_GPIO		MPP( 46, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TSMP10		MPP( 46, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TDM_FS		MPP( 46, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP47_GPIO		MPP( 47, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TSMP11		MPP( 47, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TDM_DRX		MPP( 47, 0x2, 1, 0, 0,   0,   0,   1    )
-
-#define MPP48_GPIO		MPP( 48, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TSMP12		MPP( 48, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TDM_DTX		MPP( 48, 0x2, 0, 1, 0,   0,   0,   1    )
-
-#define MPP49_GPIO		MPP( 49, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TSMP9		MPP( 49, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TDM_CH0_RX_QL	MPP( 49, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP49_PTP_CLK		MPP( 49, 0x5, 1, 0, 0,   0,   0,   1    )
+				/*   num sel  i  o  6180 6190 6192 6281 6282 */
+
+#define MPP_INPUT_MASK		MPP(  0, 0x0, 1, 0, 0,   0,   0,   0,   0 )
+#define MPP_OUTPUT_MASK		MPP(  0, 0x0, 0, 1, 0,   0,   0,   0,   0 )
+
+#define MPP_F6180_MASK		MPP(  0, 0x0, 0, 0, 1,   0,   0,   0,   0 )
+#define MPP_F6190_MASK		MPP(  0, 0x0, 0, 0, 0,   1,   0,   0,   0 )
+#define MPP_F6192_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   1,   0,   0 )
+#define MPP_F6281_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   0,   1,   0 )
+#define MPP_F6282_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP0_GPIO		MPP(  0, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP0_NF_IO2		MPP(  0, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP0_SPI_SCn		MPP(  0, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP1_GPO		MPP(  1, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP1_NF_IO3		MPP(  1, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP1_SPI_MOSI		MPP(  1, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP2_GPO		MPP(  2, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP2_NF_IO4		MPP(  2, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP2_SPI_SCK		MPP(  2, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP3_GPO		MPP(  3, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP3_NF_IO5		MPP(  3, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP3_SPI_MISO		MPP(  3, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP4_GPIO		MPP(  4, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP4_NF_IO6		MPP(  4, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP4_UART0_RXD		MPP(  4, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP4_SATA1_ACTn		MPP(  4, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP4_LCD_VGA_HSYNC	MPP(  4, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+#define MPP4_PTP_CLK		MPP(  4, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+
+#define MPP5_GPO		MPP(  5, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP5_NF_IO7		MPP(  5, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP5_UART0_TXD		MPP(  5, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP5_PTP_TRIG_GEN	MPP(  5, 0x4, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP5_SATA0_ACTn		MPP(  5, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP5_LCD_VGA_VSYNC	MPP(  5, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP6_SYSRST_OUTn	MPP(  6, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP6_SPI_MOSI		MPP(  6, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP6_PTP_TRIG_GEN	MPP(  6, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+
+#define MPP7_GPO		MPP(  7, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP7_PEX_RST_OUTn	MPP(  7, 0x1, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP7_SPI_SCn		MPP(  7, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP7_PTP_TRIG_GEN	MPP(  7, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP7_LCD_PWM		MPP(  7, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP8_GPIO		MPP(  8, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP8_TW0_SDA		MPP(  8, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP8_UART0_RTS		MPP(  8, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP8_UART1_RTS		MPP(  8, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP8_MII0_RXERR		MPP(  8, 0x4, 1, 0, 0,   1,   1,   1,   1 )
+#define MPP8_SATA1_PRESENTn	MPP(  8, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP8_PTP_CLK		MPP(  8, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP8_MII0_COL		MPP(  8, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP9_GPIO		MPP(  9, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP9_TW0_SCK		MPP(  9, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP9_UART0_CTS		MPP(  9, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_UART1_CTS		MPP(  9, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_SATA0_PRESENTn	MPP(  9, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP9_PTP_EVENT_REQ	MPP(  9, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP9_MII0_CRS		MPP(  9, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP10_GPO		MPP( 10, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_SPI_SCK		MPP( 10, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_UART0_TXD		MPP( 10, 0X3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_SATA1_ACTn	MPP( 10, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP10_PTP_TRIG_GEN	MPP( 10, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+
+#define MPP11_GPIO		MPP( 11, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP11_SPI_MISO		MPP( 11, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP11_UART0_RXD		MPP( 11, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP11_PTP_EVENT_REQ	MPP( 11, 0x4, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_TRIG_GEN	MPP( 11, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_CLK		MPP( 11, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP11_SATA0_ACTn	MPP( 11, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+
+#define MPP12_GPO		MPP( 12, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_SD_CLK		MPP( 12, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_AU_SPDIF0		MPP( 12, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP12_SPI_MOSI		MPP( 12, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP12_TW1_SDA		MPP( 12, 0xd, 1, 0, 0,   0,   0,   0,   1 )
+
+#define MPP13_GPIO		MPP( 13, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP13_SD_CMD		MPP( 13, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP13_UART1_TXD		MPP( 13, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP13_AU_SPDIFRMCLK	MPP( 13, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP13_LCDPWM		MPP( 13, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP14_GPIO		MPP( 14, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP14_SD_D0		MPP( 14, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP14_UART1_RXD		MPP( 14, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP14_SATA1_PRESENTn	MPP( 14, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP14_AU_SPDIFI		MPP( 14, 0xa, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP14_AU_I2SDI		MPP( 14, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP14_MII0_COL		MPP( 14, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP15_GPIO		MPP( 15, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP15_SD_D1		MPP( 15, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP15_UART0_RTS		MPP( 15, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP15_UART1_TXD		MPP( 15, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP15_SATA0_ACTn	MPP( 15, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP15_SPI_CSn		MPP( 15, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP16_GPIO		MPP( 16, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP16_SD_D2		MPP( 16, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP16_UART0_CTS		MPP( 16, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_UART1_RXD		MPP( 16, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_SATA1_ACTn	MPP( 16, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP16_LCD_EXT_REF_CLK	MPP( 16, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP16_MII0_CRS		MPP( 16, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP17_GPIO		MPP( 17, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP17_SD_D3		MPP( 17, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP17_SATA0_PRESENTn	MPP( 17, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP17_SATA1_ACTn	MPP( 17, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP17_TW1_SCK		MPP( 17, 0xd, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP18_GPO		MPP( 18, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP18_NF_IO0		MPP( 18, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP18_PEX0_CLKREQ	MPP( 18, 0x2, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP19_GPO		MPP( 19, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP19_NF_IO1		MPP( 19, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+
+#define MPP20_GPIO		MPP( 20, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP20_TSMP0		MPP( 20, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP20_TDM_CH0_TX_QL	MPP( 20, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP20_GE1_TXD0		MPP( 20, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP20_AU_SPDIFI		MPP( 20, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP20_SATA1_ACTn	MPP( 20, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP20_LCD_D0		MPP( 20, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP21_GPIO		MPP( 21, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP21_TSMP1		MPP( 21, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP21_TDM_CH0_RX_QL	MPP( 21, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP21_GE1_TXD1		MPP( 21, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP21_AU_SPDIFO		MPP( 21, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP21_SATA0_ACTn	MPP( 21, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP21_LCD_D1		MPP( 21, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP22_GPIO		MPP( 22, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP22_TSMP2		MPP( 22, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP22_TDM_CH2_TX_QL	MPP( 22, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_GE1_TXD2		MPP( 22, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP22_AU_SPDIFRMKCLK	MPP( 22, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_SATA1_PRESENTn	MPP( 22, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_LCD_D2		MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP23_GPIO		MPP( 23, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP23_TSMP3		MPP( 23, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP23_TDM_CH2_RX_QL	MPP( 23, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP23_GE1_TXD3		MPP( 23, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP23_AU_I2SBCLK	MPP( 23, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP23_SATA0_PRESENTn	MPP( 23, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP23_LCD_D3		MPP( 23, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP24_GPIO		MPP( 24, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP24_TSMP4		MPP( 24, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP24_TDM_SPI_CS0	MPP( 24, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP24_GE1_RXD0		MPP( 24, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP24_AU_I2SDO		MPP( 24, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP24_LCD_D4		MPP( 24, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP25_GPIO		MPP( 25, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP25_TSMP5		MPP( 25, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP25_TDM_SPI_SCK	MPP( 25, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP25_GE1_RXD1		MPP( 25, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP25_AU_I2SLRCLK	MPP( 25, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP25_LCD_D5		MPP( 25, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP26_GPIO		MPP( 26, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP26_TSMP6		MPP( 26, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP26_TDM_SPI_MISO	MPP( 26, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP26_GE1_RXD2		MPP( 26, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP26_AU_I2SMCLK	MPP( 26, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP26_LCD_D6		MPP( 26, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP27_GPIO		MPP( 27, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP27_TSMP7		MPP( 27, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP27_TDM_SPI_MOSI	MPP( 27, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP27_GE1_RXD3		MPP( 27, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP27_AU_I2SDI		MPP( 27, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP27_LCD_D7		MPP( 27, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP28_GPIO		MPP( 28, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP28_TSMP8		MPP( 28, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP28_TDM_CODEC_INTn	MPP( 28, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+#define MPP28_GE1_COL		MPP( 28, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP28_AU_EXTCLK		MPP( 28, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP28_LCD_D8		MPP( 28, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP29_GPIO		MPP( 29, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP29_TSMP9		MPP( 29, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP29_TDM_CODEC_RSTn	MPP( 29, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+#define MPP29_GE1_TCLK		MPP( 29, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP29_LCD_D9		MPP( 29, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP30_GPIO		MPP( 30, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP30_TSMP10		MPP( 30, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP30_TDM_PCLK		MPP( 30, 0x2, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP30_GE1_RXCTL		MPP( 30, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP30_LCD_D10		MPP( 30, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP31_GPIO		MPP( 31, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP31_TSMP11		MPP( 31, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP31_TDM_FS		MPP( 31, 0x2, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP31_GE1_RXCLK		MPP( 31, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP31_LCD_D11		MPP( 31, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP32_GPIO		MPP( 32, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP32_TSMP12		MPP( 32, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP32_TDM_DRX		MPP( 32, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP32_GE1_TCLKOUT	MPP( 32, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP32_LCD_D12		MPP( 32, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP33_GPO		MPP( 33, 0x0, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP33_TDM_DTX		MPP( 33, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP33_GE1_TXCTL		MPP( 33, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP33_LCD_D13		MPP( 33, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP34_GPIO		MPP( 34, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP34_TDM_SPI_CS1	MPP( 34, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP34_GE1_TXEN		MPP( 34, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP34_SATA1_ACTn	MPP( 34, 0x5, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP34_LCD_D14		MPP( 34, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP35_GPIO		MPP( 35, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP35_TDM_CH0_TX_QL	MPP( 35, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP35_GE1_RXERR		MPP( 35, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP35_SATA0_ACTn	MPP( 35, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP35_LCD_D15		MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+#define MPP35_MII0_RXERR	MPP( 35, 0xc, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP36_GPIO		MPP( 36, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP36_TSMP0		MPP( 36, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP36_TDM_SPI_CS1	MPP( 36, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP36_AU_SPDIFI		MPP( 36, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP36_TW1_SDA		MPP( 36, 0xb, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP37_GPIO		MPP( 37, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP37_TSMP1		MPP( 37, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP37_TDM_CH2_TX_QL	MPP( 37, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP37_AU_SPDIFO		MPP( 37, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP37_TW1_SCK		MPP( 37, 0xb, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP38_GPIO		MPP( 38, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP38_TSMP2		MPP( 38, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP38_TDM_CH2_RX_QL	MPP( 38, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP38_AU_SPDIFRMLCLK	MPP( 38, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP38_LCD_D18		MPP( 38, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP39_GPIO		MPP( 39, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP39_TSMP3		MPP( 39, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP39_TDM_SPI_CS0	MPP( 39, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP39_AU_I2SBCLK	MPP( 39, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP39_LCD_D19		MPP( 39, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP40_GPIO		MPP( 40, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP40_TSMP4		MPP( 40, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP40_TDM_SPI_SCK	MPP( 40, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP40_AU_I2SDO		MPP( 40, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP40_LCD_D20		MPP( 40, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP41_GPIO		MPP( 41, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP41_TSMP5		MPP( 41, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP41_TDM_SPI_MISO	MPP( 41, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+#define MPP41_AU_I2SLRCLK	MPP( 41, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP41_LCD_D21		MPP( 41, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP42_GPIO		MPP( 42, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP42_TSMP6		MPP( 42, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP42_TDM_SPI_MOSI	MPP( 42, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP42_AU_I2SMCLK	MPP( 42, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP42_LCD_D22		MPP( 42, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP43_GPIO		MPP( 43, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP43_TSMP7		MPP( 43, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP43_TDM_CODEC_INTn	MPP( 43, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+#define MPP43_AU_I2SDI		MPP( 43, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP43_LCD_D23		MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP44_GPIO		MPP( 44, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP44_TSMP8		MPP( 44, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP44_TDM_CODEC_RSTn	MPP( 44, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+#define MPP44_AU_EXTCLK		MPP( 44, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP44_LCD_CLK		MPP( 44, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP45_GPIO		MPP( 45, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP45_TSMP9		MPP( 45, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP45_TDM_PCLK		MPP( 45, 0x2, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP245_LCD_E		MPP( 45, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP46_GPIO		MPP( 46, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_TSMP10		MPP( 46, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_TDM_FS		MPP( 46, 0x2, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_LCD_HSYNC		MPP( 46, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP47_GPIO		MPP( 47, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP47_TSMP11		MPP( 47, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP47_TDM_DRX		MPP( 47, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+#define MPP47_LCD_VSYNC		MPP( 47, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP48_GPIO		MPP( 48, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP48_TSMP12		MPP( 48, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP48_TDM_DTX		MPP( 48, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP48_LCD_D16		MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP49_GPIO		MPP( 49, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP49_TSMP9		MPP( 49, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP49_TDM_CH0_RX_QL	MPP( 49, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP49_PTP_CLK		MPP( 49, 0x5, 1, 0, 0,   0,   0,   1,   0 )
+#define MPP49_PEX0_CLKREQ	MPP( 49, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP49_LCD_D17		MPP( 49, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 
 #define MPP_MAX			49
 
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 3ae158d..b96e43b 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -249,8 +249,8 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
 	MPP4_NF_IO6,
 	MPP5_NF_IO7,
 	MPP6_SYSRST_OUTn,
-	MPP8_TW_SDA,
-	MPP9_TW_SCK,
+	MPP8_TW0_SDA,
+	MPP9_TW0_SCK,
 	MPP10_UART0_TXD,
 	MPP11_UART0_RXD,
 	MPP12_GPO,		/* Red led */
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 8a2bb02..2bd14c5 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -270,8 +270,8 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
 	MPP3_SPI_MISO,
 	MPP6_SYSRST_OUTn,
 	MPP7_GPO,		/* Request power-off */
-	MPP8_TW_SDA,
-	MPP9_TW_SCK,
+	MPP8_TW0_SDA,
+	MPP9_TW0_SCK,
 	MPP10_UART0_TXD,
 	MPP11_UART0_RXD,
 	MPP13_GPIO,		/* Rear power switch (on|auto) */
@@ -306,8 +306,8 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
 	MPP3_SPI_MISO,
 	MPP6_SYSRST_OUTn,
 	MPP7_GPO,		/* Request power-off */
-	MPP8_TW_SDA,
-	MPP9_TW_SCK,
+	MPP8_TW0_SDA,
+	MPP9_TW0_SCK,
 	MPP10_UART0_TXD,
 	MPP11_UART0_RXD,
 	MPP13_GPIO,		/* Rear power switch (on|auto) */
@@ -315,20 +315,20 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
 	MPP15_GPIO,		/* Rear power switch (auto|off) */
 	MPP16_GPIO,		/* SATA HDD1 power */
 	MPP17_GPIO,		/* SATA HDD2 power */
-	MPP20_GE1_0,
-	MPP21_GE1_1,
-	MPP22_GE1_2,
-	MPP23_GE1_3,
-	MPP24_GE1_4,
-	MPP25_GE1_5,
-	MPP26_GE1_6,
-	MPP27_GE1_7,
+	MPP20_GE1_TXD0,
+	MPP21_GE1_TXD1,
+	MPP22_GE1_TXD2,
+	MPP23_GE1_TXD3,
+	MPP24_GE1_RXD0,
+	MPP25_GE1_RXD1,
+	MPP26_GE1_RXD2,
+	MPP27_GE1_RXD3,
 	MPP28_GPIO,		/* USB enable host vbus */
 	MPP29_GPIO,		/* CPLD extension ALE */
-	MPP30_GE1_10,
-	MPP31_GE1_11,
-	MPP32_GE1_12,
-	MPP33_GE1_13,
+	MPP30_GE1_RXCTL,
+	MPP31_GE1_RXCLK,
+	MPP32_GE1_TCLKOUT,
+	MPP33_GE1_TXCTL,
 	MPP34_GPIO,		/* Rear Push button */
 	MPP35_GPIO,		/* Inhibit switch power-off */
 	MPP36_GPIO,		/* SATA HDD1 presence */
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0f..d23aff9 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -74,8 +74,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
 	MPP3_SPI_MISO,
 	MPP4_SATA1_ACTn,
 	MPP5_SATA0_ACTn,
-	MPP8_TW_SDA,
-	MPP9_TW_SCK,
+	MPP8_TW0_SDA,
+	MPP9_TW0_SCK,
 	MPP10_UART0_TXD,
 	MPP11_UART0_RXD,
 	MPP13_UART1_TXD,	/* PIC controller */
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index de49c2d..ecd0d5f 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -78,26 +78,26 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
 	MPP3_SPI_MISO,
 	MPP6_SYSRST_OUTn,
 	MPP7_PEX_RST_OUTn,
-	MPP8_TW_SDA,
-	MPP9_TW_SCK,
+	MPP8_TW0_SDA,
+	MPP9_TW0_SCK,
 	MPP10_UART0_TXD,
 	MPP11_UART0_RXD,
 	MPP13_UART1_TXD,	/* PIC controller */
 	MPP14_UART1_RXD,	/* PIC controller */
 	MPP15_SATA0_ACTn,
 	MPP16_SATA1_ACTn,
-	MPP20_GE1_0,
-	MPP21_GE1_1,
-	MPP22_GE1_2,
-	MPP23_GE1_3,
-	MPP24_GE1_4,
-	MPP25_GE1_5,
-	MPP26_GE1_6,
-	MPP27_GE1_7,
-	MPP30_GE1_10,
-	MPP31_GE1_11,
-	MPP32_GE1_12,
-	MPP33_GE1_13,
+	MPP20_GE1_TXD0,
+	MPP21_GE1_TXD1,
+	MPP22_GE1_TXD2,
+	MPP23_GE1_TXD3,
+	MPP24_GE1_RXD0,
+	MPP25_GE1_RXD1,
+	MPP26_GE1_RXD2,
+	MPP27_GE1_RXD3,
+	MPP30_GE1_RXCTL,
+	MPP31_GE1_RXCLK,
+	MPP32_GE1_TCLKOUT,
+	MPP33_GE1_TXCTL,
 	MPP36_GPIO,		/* RAM: 0: 256 MB, 1: 512 MB */
 	MPP37_GPIO,		/* Reset button */
 	MPP43_GPIO,		/* USB Copy button */



From benjamin.zores at alcatel-lucent.com  Thu Jun 10 09:59:46 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Thu, 10 Jun 2010 15:59:46 +0200
Subject: [PATCH 3/4] arch/arm/mach-kirkwood: add support for 2nd PCIe port on
	88f6282.
In-Reply-To: <20100610135936.14097.22635.stgit@localhost.localdomain>
References: <20100610135936.14097.22635.stgit@localhost.localdomain>
Message-ID: <20100610135946.14097.39894.stgit@localhost.localdomain>

Signed-off-by: Benjamin Zores <benjamin.zores at alcatel-lucent.com>
---
 arch/arm/mach-kirkwood/addr-map.c                 |   21 ++
 arch/arm/mach-kirkwood/common.c                   |   28 +++
 arch/arm/mach-kirkwood/common.h                   |    5 -
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c       |    2 
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h |    3 
 arch/arm/mach-kirkwood/include/mach/irqs.h        |    1 
 arch/arm/mach-kirkwood/include/mach/kirkwood.h    |   12 +
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c    |    2 
 arch/arm/mach-kirkwood/openrd-setup.c             |    2 
 arch/arm/mach-kirkwood/pcie.c                     |  202 ++++++++++++++++-----
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c      |    2 
 arch/arm/mach-kirkwood/rd88f6281-setup.c          |    2 
 arch/arm/mach-kirkwood/ts219-setup.c              |    2 
 arch/arm/mach-kirkwood/ts41x-setup.c              |    2 
 14 files changed, 223 insertions(+), 63 deletions(-)

diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168..aa6bf38 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
 #define ATTR_DEV_CS0		0x3e
 #define ATTR_PCIE_IO		0xe0
 #define ATTR_PCIE_MEM		0xe8
+#define ATTR_PCIE1_IO		0xd0
+#define ATTR_PCIE1_MEM		0xd8
 #define ATTR_SRAM		0x01
 
 /*
@@ -84,6 +86,8 @@ void __init kirkwood_setup_cpu_mbus(void)
 	void __iomem *addr;
 	int i;
 	int cs;
+	int id = 0;
+	u32 dev, rev;
 
 	/*
 	 * First, disable and clear windows.
@@ -102,21 +106,30 @@ void __init kirkwood_setup_cpu_mbus(void)
 	/*
 	 * Setup windows for PCIe IO+MEM space.
 	 */
-	setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
+	setup_cpu_win(id++, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
 		      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
-	setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
+	setup_cpu_win(id++, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
 		      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
 
+	kirkwood_pcie_id(&dev, &rev);
+
+	if (dev == MV88F6282_DEV_ID && (rev == MV88F6282_REV_A0)) {
+	  setup_cpu_win(id++, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
+			TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
+	  setup_cpu_win(id++, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
+			TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
+	}
+
 	/*
 	 * Setup window for NAND controller.
 	 */
-	setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+	setup_cpu_win(id++, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
 		      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
 
 	/*
 	 * Setup window for SRAM.
 	 */
-	setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+	setup_cpu_win(id++, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
 		      TARGET_SRAM, ATTR_SRAM, -1);
 
 	/*
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 94f629d..473a1d0 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -44,6 +44,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
 		.length		= KIRKWOOD_PCIE_IO_SIZE,
 		.type		= MT_DEVICE,
 	}, {
+		.virtual	= KIRKWOOD_PCIE1_IO_VIRT_BASE,
+		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
+		.length		= KIRKWOOD_PCIE1_IO_SIZE,
+		.type		= MT_DEVICE,
+	}, {
 		.virtual	= KIRKWOOD_REGS_VIRT_BASE,
 		.pfn		= __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
 		.length		= KIRKWOOD_REGS_SIZE,
@@ -957,12 +962,20 @@ void __init kirkwood_init(void)
 static int __init kirkwood_clock_gate(void)
 {
 	unsigned int curr = readl(CLOCK_GATING_CTRL);
+	u32 dev, rev;
+	int flags;
 
 	printk(KERN_DEBUG "Gating clock of unused units\n");
 	printk(KERN_DEBUG "before: 0x%08x\n", curr);
 
+	kirkwood_pcie_id(&dev, &rev);
+
 	/* Make sure those units are accessible */
-	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);
+	flags = curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0;
+
+	if (dev == MV88F6282_DEV_ID && (rev == MV88F6282_REV_A0))
+		flags |= CGC_PEX1;	
+	writel(flags, CLOCK_GATING_CTRL);
 
 	/* For SATA: first shutdown the phy */
 	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
@@ -978,7 +991,7 @@ static int __init kirkwood_clock_gate(void)
 		writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
 	}
 	
-	/* For PCIe: first shutdown the phy */
+	/* For PCIe #0: first shutdown the phy */
 	if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
 		writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
 		while (1)
@@ -987,6 +1000,17 @@ static int __init kirkwood_clock_gate(void)
 		writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
 	}
 
+	/* For PCIe #1: first shutdown the phy */
+	if (dev == MV88F6282_DEV_ID && (rev == MV88F6282_REV_A0)) {
+		if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
+			writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
+			while (1)
+				if (readl(PCIE1_STATUS) & 0x1)
+					break;
+			writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
+		}
+	}
+
 	/* Now gate clock the required units */
 	writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
 	printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05e8a8a..5b2c1c1 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -18,6 +18,9 @@ struct mvsdio_platform_data;
 struct mtd_partition;
 struct mtd_info;
 
+#define KW_PCIE0	(1 << 0)
+#define KW_PCIE1	(1 << 1)
+
 /*
  * Basic Kirkwood init functions used early by machine-setup.
  */
@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);
 void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
-void kirkwood_pcie_init(void);
+void kirkwood_pcie_init(unsigned int portmask);
 void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
 void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
 void kirkwood_spi_init(void);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4b..7550c4e 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -75,7 +75,7 @@ static void __init db88f6281_init(void)
 static int __init db88f6281_pci_init(void)
 {
 	if (machine_is_db88f6281_bp())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f501..aff0e13 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,8 +59,9 @@
 #define CGC_SATA1		(1 << 15)
 #define CGC_XOR1		(1 << 16)
 #define CGC_CRYPTO		(1 << 17)
+#define CGC_PEX1		(1 << 18)
 #define CGC_GE1			(1 << 19)
 #define CGC_TDM			(1 << 20)
-#define CGC_RESERVED		((1 << 18) | (0x6 << 21))
+#define CGC_RESERVED		(0x6 << 21)
 
 #endif
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index f00a0a4..9da2eb5 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -23,6 +23,7 @@
 #define IRQ_KIRKWOOD_XOR_10	7
 #define IRQ_KIRKWOOD_XOR_11	8
 #define IRQ_KIRKWOOD_PCIE	9
+#define IRQ_KIRKWOOD_PCIE1	10
 #define IRQ_KIRKWOOD_GE00_SUM	11
 #define IRQ_KIRKWOOD_GE01_SUM	15
 #define IRQ_KIRKWOOD_USB	19
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a571860..7f0b50a 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -38,6 +38,11 @@
 #define KIRKWOOD_PCIE_IO_BUS_BASE	0x00000000
 #define KIRKWOOD_PCIE_IO_SIZE		SZ_1M
 
+#define KIRKWOOD_PCIE1_IO_PHYS_BASE	0xf5000000
+#define KIRKWOOD_PCIE1_IO_VIRT_BASE	0xfed00000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE	0x00000000
+#define KIRKWOOD_PCIE1_IO_SIZE		SZ_1M
+
 #define KIRKWOOD_REGS_PHYS_BASE		0xf1000000
 #define KIRKWOOD_REGS_VIRT_BASE		0xfee00000
 #define KIRKWOOD_REGS_SIZE		SZ_1M
@@ -46,6 +51,10 @@
 #define KIRKWOOD_PCIE_MEM_BUS_BASE	0xe0000000
 #define KIRKWOOD_PCIE_MEM_SIZE		SZ_128M
 
+#define KIRKWOOD_PCIE1_MEM_PHYS_BASE	0xd8000000
+#define KIRKWOOD_PCIE1_MEM_BUS_BASE	0xd8000000
+#define KIRKWOOD_PCIE1_MEM_SIZE		SZ_128M
+
 /*
  * Register Map
  */
@@ -72,6 +81,9 @@
 #define PCIE_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x40000)
 #define PCIE_LINK_CTRL		(PCIE_VIRT_BASE | 0x70)
 #define PCIE_STATUS		(PCIE_VIRT_BASE | 0x1a04)
+#define PCIE1_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x44000)
+#define PCIE1_LINK_CTRL		(PCIE1_VIRT_BASE | 0x70)
+#define PCIE1_STATUS		(PCIE1_VIRT_BASE | 0x1a04)
 
 #define USB_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x50000)
 
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 5e6f711..c6b92b4 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
 static int __init mv88f6281gtw_ge_pci_init(void)
 {
 	if (machine_is_mv88f6281gtw_ge())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec..2400207 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -85,7 +85,7 @@ static void __init openrd_init(void)
 static int __init openrd_pci_init(void)
 {
 	if (machine_is_openrd_base() || machine_is_openrd_client())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index dee1eff..dd1dc29 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,29 +18,51 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
+void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+{
+	*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
+	*rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+}
 
-#define PCIE_BASE	((void __iomem *)PCIE_VIRT_BASE)
+struct pcie_port {
+	int			index;
+	u8			root_bus_nr;
+	void __iomem		*base;
+	spinlock_t		conf_lock;
+	int			irq;
+	struct resource		res[2];
+};
 
-void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+static struct pcie_port pcie_port[2];
+static int num_pcie_ports;
+
+static inline struct pcie_port *bus_to_port(int bus)
 {
-	*dev = orion_pcie_dev_id(PCIE_BASE);
-	*rev = orion_pcie_rev(PCIE_BASE);
+	int i;
+
+	for (i = num_pcie_ports - 1; i >= 0; i--) {
+        	int rbus = pcie_port[i].root_bus_nr;
+		if (rbus != -1 && rbus <= bus)
+			break;
+	}
+
+	return i >= 0 ? pcie_port + i : NULL;
 }
 
-static int pcie_valid_config(int bus, int dev)
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 {
 	/*
 	 * Don't go out when trying to access --
 	 * 1. nonexisting device on local bus
 	 * 2. where there's no device connected (no link)
 	 */
-	if (bus == 0 && dev == 0)
+	if (bus == pp->root_bus_nr && dev == 0)
 		return 1;
 
-	if (!orion_pcie_link_up(PCIE_BASE))
+	if (!orion_pcie_link_up(pp->base))
 		return 0;
 
-	if (bus == 0 && dev != 1)
+	if (bus == pp->root_bus_nr && dev != 1)
 		return 0;
 
 	return 1;
@@ -52,22 +74,22 @@ static int pcie_valid_config(int bus, int dev)
  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  * transactions are atomic.
  */
-static DEFINE_SPINLOCK(kirkwood_pcie_lock);
 
 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 			int size, u32 *val)
 {
+	struct pcie_port *pp = bus_to_port(bus->number);
 	unsigned long flags;
 	int ret;
 
-	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
 		*val = 0xffffffff;
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
 
-	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
-	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+	spin_lock_irqsave(&pp->conf_lock, flags);
+	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+	spin_unlock_irqrestore(&pp->conf_lock, flags);
 
 	return ret;
 }
@@ -75,15 +97,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 			int where, int size, u32 val)
 {
+	struct pcie_port *pp = bus_to_port(bus->number);
 	unsigned long flags;
 	int ret;
 
-	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
-	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
-	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+	spin_lock_irqsave(&pp->conf_lock, flags);
+	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+	spin_unlock_irqrestore(&pp->conf_lock, flags);
 
 	return ret;
 }
@@ -93,50 +116,106 @@ static struct pci_ops pcie_ops = {
 	.write = pcie_wr_conf,
 };
 
-
-static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+static int __init pcie0_ioresouces_setup(struct pcie_port *pp)
 {
-	struct resource *res;
-	extern unsigned int kirkwood_clk_ctrl;
-
 	/*
-	 * Generic PCIe unit setup.
+	 * IORESOURCE_IO
 	 */
-	orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
+	pp->res[0].name  = "PCIe 0 I/O Space";
+	pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+	pp->res[0].end   = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+	pp->res[0].flags = IORESOURCE_IO;
+	if (request_resource(&ioport_resource, &pp->res[0]))
+		panic("Request PCIe 0 IO resource failed\n");
 
 	/*
-	 * Request resources.
+	 * IORESOURCE_MEM
 	 */
-	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-	if (!res)
-		panic("pcie_setup unable to alloc resources");
+	pp->res[1].name  = "PCIe 0 MEM";
+	pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+	pp->res[1].end   = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+	pp->res[1].flags = IORESOURCE_MEM;
+	if (request_resource(&iomem_resource, &pp->res[1]))
+		panic("Request PCIe 0 Memory resource failed\n");
+
+	return 1;
+}
 
+static int __init pcie1_ioresouces_setup(struct pcie_port *pp)
+{
 	/*
 	 * IORESOURCE_IO
 	 */
-	res[0].name = "PCIe I/O Space";
-	res[0].flags = IORESOURCE_IO;
-	res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-	res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
-	if (request_resource(&ioport_resource, &res[0]))
-		panic("Request PCIe IO resource failed\n");
-	sys->resource[0] = &res[0];
+	pp->res[0].name  = "PCIe 1 I/O Space";
+	pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
+	pp->res[0].end   = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
+	pp->res[0].flags = IORESOURCE_IO;
+	if (request_resource(&ioport_resource, &pp->res[0]))
+		panic("Request PCIe 1 IO resource failed\n");
 
 	/*
 	 * IORESOURCE_MEM
 	 */
-	res[1].name = "PCIe Memory Space";
-	res[1].flags = IORESOURCE_MEM;
-	res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
-	res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-	if (request_resource(&iomem_resource, &res[1]))
-		panic("Request PCIe Memory resource failed\n");
-	sys->resource[1] = &res[1];
+	pp->res[1].name  = "PCIe 1 MEM";
+	pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+	pp->res[1].end   = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+	pp->res[1].flags = IORESOURCE_MEM;
+	if (request_resource(&iomem_resource, &pp->res[1]))
+		panic("Request PCIe 1 Memory resource failed\n");
 
-	sys->resource[2] = NULL;
-	sys->io_offset = 0;
+	return 1;
+}
+
+static void __init kirkwood_pcie_preinit(void)
+{
+	int i;
+
+	for (i = 0; i < num_pcie_ports; i++) {
+		struct pcie_port *pp = pcie_port + i;
+		extern unsigned int kirkwood_clk_ctrl;
 
+		switch (pp->index) {
+		case 0:
+			pp->base = (void __iomem *)PCIE_VIRT_BASE;
+			pp->irq	= IRQ_KIRKWOOD_PCIE;
 	kirkwood_clk_ctrl |= CGC_PEX0;
+			pcie0_ioresouces_setup(pp);
+			break;
+		case 1:
+			pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+			pp->irq	= IRQ_KIRKWOOD_PCIE1;
+			kirkwood_clk_ctrl |= CGC_PEX1;
+			pcie1_ioresouces_setup(pp);
+			break;
+		default:
+			panic("PCIe setup: invalid controller");
+		}
+	}
+}
+
+static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+	struct pcie_port *pp;
+
+	if (nr >= num_pcie_ports)
+		return 0;
+
+	pp = &pcie_port[nr];
+	pp->root_bus_nr = sys->busnr;
+
+	printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n",
+	       sys->busnr, pp->index);
+
+	/*
+	 * Generic PCIe unit setup.
+	 */
+	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+	orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
+
+	sys->resource[0] = &pp->res[0];
+	sys->resource[1] = &pp->res[1];
+	sys->resource[2] = NULL;
+	sys->io_offset   = 0;
 
 	return 1;
 }
@@ -163,7 +242,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 {
 	struct pci_bus *bus;
 
-	if (nr == 0) {
+	if (nr < num_pcie_ports) {
 		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
 	} else {
 		bus = NULL;
@@ -175,18 +254,45 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 
 static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-	return IRQ_KIRKWOOD_PCIE;
+	struct pcie_port *pp = bus_to_port(dev->bus->number);
+
+	return pp->irq;
 }
 
 static struct hw_pci kirkwood_pci __initdata = {
-	.nr_controllers	= 1,
+	.preinit	= kirkwood_pcie_preinit,
 	.swizzle	= pci_std_swizzle,
 	.setup		= kirkwood_pcie_setup,
 	.scan		= kirkwood_pcie_scan_bus,
 	.map_irq	= kirkwood_pcie_map_irq,
 };
 
-void __init kirkwood_pcie_init(void)
+static void __init add_pcie_port(int index, unsigned long base)
+{
+	printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
+
+	if (orion_pcie_link_up((void __iomem *)base)) {
+		struct pcie_port *pp = &pcie_port[num_pcie_ports++];
+
+		printk(KERN_INFO "link up\n");
+
+		pp->index = index;
+		pp->root_bus_nr = -1;
+		pp->base = (void __iomem *)base;
+		spin_lock_init(&pp->conf_lock);
+		memset(pp->res, 0, sizeof(pp->res));
+	} else
+		printk(KERN_INFO "link down, ignoring\n");
+}
+
+void __init kirkwood_pcie_init(unsigned int portmask)
 {
+	if (portmask & KW_PCIE0)
+		add_pcie_port(0, PCIE_VIRT_BASE);
+
+	if (portmask & KW_PCIE1)
+		add_pcie_port(1, PCIE1_VIRT_BASE);
+
+	kirkwood_pci.nr_controllers = num_pcie_ports;
 	pci_common_init(&kirkwood_pci);
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 3bf6304..c34718c 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
 static int __init rd88f6192_pci_init(void)
 {
 	if (machine_is_rd88f6192_nas())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31708dd..3d14771 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
 static int __init rd88f6281_pci_init(void)
 {
 	if (machine_is_rd88f6281())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index d23aff9..5c7dd85 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -111,7 +111,7 @@ static void __init qnap_ts219_init(void)
 static int __init ts219_pci_init(void)
 {
    if (machine_is_ts219())
-           kirkwood_pcie_init();
+	kirkwood_pcie_init(KW_PCIE0);
 
    return 0;
 }
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index ecd0d5f..a2c5f70 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -136,7 +136,7 @@ static void __init qnap_ts41x_init(void)
 static int __init ts41x_pci_init(void)
 {
 	if (machine_is_ts41x())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
    return 0;
 }



From benjamin.zores at alcatel-lucent.com  Thu Jun 10 09:59:51 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Thu, 10 Jun 2010 15:59:51 +0200
Subject: [PATCH 4/4] arch/arm/mach-kirkwood: add support for 2nd TWSI
	controller on 88f6282.
In-Reply-To: <20100610135936.14097.22635.stgit@localhost.localdomain>
References: <20100610135936.14097.22635.stgit@localhost.localdomain>
Message-ID: <20100610135951.14097.48348.stgit@localhost.localdomain>

Signed-off-by: Benjamin Zores <benjamin.zores at alcatel-lucent.com>
---
 arch/arm/mach-kirkwood/common.c                |   46 +++++++++++++++++++-----
 arch/arm/mach-kirkwood/include/mach/irqs.h     |    3 +-
 arch/arm/mach-kirkwood/include/mach/kirkwood.h |    3 +-
 3 files changed, 41 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 473a1d0..93b7762 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -458,23 +458,45 @@ static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
 	.timeout	= 1000, /* Default timeout of 1 second */
 };
 
-static struct resource kirkwood_i2c_resources[] = {
+static struct resource kirkwood_i2c_0_resources[] = {
 	{
-		.start	= I2C_PHYS_BASE,
-		.end	= I2C_PHYS_BASE + 0x1f,
+		.start	= I2C_0_PHYS_BASE,
+		.end	= I2C_0_PHYS_BASE + 0x1f,
 		.flags	= IORESOURCE_MEM,
 	}, {
-		.start	= IRQ_KIRKWOOD_TWSI,
-		.end	= IRQ_KIRKWOOD_TWSI,
+		.start	= IRQ_KIRKWOOD_TWSI0,
+		.end	= IRQ_KIRKWOOD_TWSI0,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
 
-static struct platform_device kirkwood_i2c = {
+static struct resource kirkwood_i2c_1_resources[] = {
+	{
+		.start	= I2C_1_PHYS_BASE,
+		.end	= I2C_1_PHYS_BASE + 0x1f,
+		.flags	= IORESOURCE_MEM,
+	}, {
+		.start	= IRQ_KIRKWOOD_TWSI1,
+		.end	= IRQ_KIRKWOOD_TWSI1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device kirkwood_i2c_0 = {
 	.name		= MV64XXX_I2C_CTLR_NAME,
 	.id		= 0,
-	.num_resources	= ARRAY_SIZE(kirkwood_i2c_resources),
-	.resource	= kirkwood_i2c_resources,
+	.num_resources	= ARRAY_SIZE(kirkwood_i2c_0_resources),
+	.resource	= kirkwood_i2c_0_resources,
+	.dev		= {
+		.platform_data	= &kirkwood_i2c_pdata,
+	},
+};
+
+static struct platform_device kirkwood_i2c_1 = {
+	.name		= MV64XXX_I2C_CTLR_NAME,
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(kirkwood_i2c_1_resources),
+	.resource	= kirkwood_i2c_1_resources,
 	.dev		= {
 		.platform_data	= &kirkwood_i2c_pdata,
 	},
@@ -482,7 +504,13 @@ static struct platform_device kirkwood_i2c = {
 
 void __init kirkwood_i2c_init(void)
 {
-	platform_device_register(&kirkwood_i2c);
+	u32 dev, rev;
+
+	kirkwood_pcie_id(&dev, &rev);
+
+	platform_device_register(&kirkwood_i2c_0);
+	if (dev == MV88F6282_DEV_ID && (rev == MV88F6282_REV_A0))
+	  platform_device_register(&kirkwood_i2c_1);
 }
 
 
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index 9da2eb5..d82ecf0 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -33,13 +33,14 @@
 #define IRQ_KIRKWOOD_I2S	24
 #define IRQ_KIRKWOOD_TS_0	26
 #define IRQ_KIRKWOOD_SDIO	28
-#define IRQ_KIRKWOOD_TWSI	29
+#define IRQ_KIRKWOOD_TWSI0	29
 #define IRQ_KIRKWOOD_AVB	30
 #define IRQ_KIRKWOOD_TDMI	31
 
 /*
  * High Interrupt Controller
  */
+#define IRQ_KIRKWOOD_TWSI1	32
 #define IRQ_KIRKWOOD_UART_0	33
 #define IRQ_KIRKWOOD_UART_1	34
 #define IRQ_KIRKWOOD_GPIO_LOW_0_7	35
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 7f0b50a..b2f2f5d 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -68,7 +68,8 @@
 #define  DEVICE_ID		(DEV_BUS_VIRT_BASE | 0x0034)
 #define  RTC_PHYS_BASE		(DEV_BUS_PHYS_BASE | 0x0300)
 #define  SPI_PHYS_BASE		(DEV_BUS_PHYS_BASE | 0x0600)
-#define  I2C_PHYS_BASE		(DEV_BUS_PHYS_BASE | 0x1000)
+#define  I2C_0_PHYS_BASE	(DEV_BUS_PHYS_BASE | 0x1000)
+#define  I2C_1_PHYS_BASE	(DEV_BUS_PHYS_BASE | 0x1100)
 #define  UART0_PHYS_BASE	(DEV_BUS_PHYS_BASE | 0x2000)
 #define  UART0_VIRT_BASE	(DEV_BUS_VIRT_BASE | 0x2000)
 #define  UART1_PHYS_BASE	(DEV_BUS_PHYS_BASE | 0x2100)



From linux at arm.linux.org.uk  Thu Jun 10 10:01:36 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 10 Jun 2010 15:01:36 +0100
Subject: Context Switching is Broken
In-Reply-To: <503171.97993.qm@web51806.mail.re2.yahoo.com>
References: <503171.97993.qm@web51806.mail.re2.yahoo.com>
Message-ID: <20100610140136.GA32362@n2100.arm.linux.org.uk>

On Thu, Jun 10, 2010 at 04:11:35AM -0700, Herman Swartz wrote:
> Context switching is broken. The man page for context is example code
> that doesn't work, but should. Does a bug report need to be submitted?

$ man context
No manual entry for context

?


From eric at eukrea.com  Thu Jun 10 10:07:50 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Thu, 10 Jun 2010 16:07:50 +0200
Subject: [PATCH] i.MX35: add cpuimx35 support and its baseboard
Message-ID: <1276178870-10202-1-git-send-email-eric@eukrea.com>

* cpuimx35 integrates i.MX35, RAM, NAND, Ethernet, I2C RTC, USB Host,
USB OTG and I2C touchscreen controller
* mbimxsd provides access to LCD, Audio, LED, Switch button, UART ...

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/mach-mx3/Kconfig                          |   22 ++
 arch/arm/mach-mx3/Makefile                         |    2 +
 arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c       |  263 ++++++++++++++++++++
 arch/arm/mach-mx3/mach-cpuimx35.c                  |  227 +++++++++++++++++
 .../plat-mxc/include/mach/board-eukrea_cpuimx35.h  |   40 +++
 5 files changed, 554 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
 create mode 100644 arch/arm/mach-mx3/mach-cpuimx35.c
 create mode 100644 arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx35.h

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753f..b09e9a9 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -125,4 +125,26 @@ config MACH_KZM_ARM11_01
 	  Include support for KZM-ARM11-01. This includes specific
 	  configurations for the board and its peripherals.
 
+config MACH_EUKREA_CPUIMX35
+	bool "Support Eukrea CPUIMX35 Platform"
+	select ARCH_MX35
+	select MXC_ULPI if USB_ULPI
+	help
+	  Include support for Eukrea CPUIMX35 platform. This includes
+	  specific configurations for the board and its peripherals.
+
+choice
+	prompt "Baseboard"
+	depends on MACH_EUKREA_CPUIMX35
+	default MACH_EUKREA_MBIMXSD_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD_BASEBOARD
+	prompt "Eukrea MBIMXSD development board"
+	bool
+	help
+	  This adds board specific devices that can be found on Eukrea's
+	  MBIMXSD evaluation board.
+
+endchoice
+
 endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 5d650fd..ef68ff5 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -24,3 +24,5 @@ obj-$(CONFIG_MACH_PCM043)	+= mach-pcm043.o
 obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
 obj-$(CONFIG_MACH_MX35_3DS)	+= mach-mx35pdk.o
 obj-$(CONFIG_MACH_KZM_ARM11_01)	+= mach-kzm_arm11_01.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX35)	+= mach-cpuimx35.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD)	+= eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
new file mode 100644
index 0000000..6785978
--- /dev/null
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric at eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel at pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <video/platform_lcd.h>
+#include <linux/i2c.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/board-eukrea_cpuimx35.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx35.h>
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+#include <mach/audmux.h>
+#include <mach/ssi.h>
+
+#include "devices.h"
+
+static const struct fb_videomode fb_modedb[] = {
+	{
+		.name		= "CMO_QVGA",
+		.refresh	= 60,
+		.xres		= 320,
+		.yres		= 240,
+		.pixclock	= KHZ2PICOS(6500),
+		.left_margin	= 68,
+		.right_margin	= 20,
+		.upper_margin	= 15,
+		.lower_margin	= 4,
+		.hsync_len	= 30,
+		.vsync_len	= 3,
+		.sync		= 0,
+		.vmode		= FB_VMODE_NONINTERLACED,
+		.flag		= 0,
+	},
+};
+
+static struct ipu_platform_data mx3_ipu_data = {
+	.irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata = {
+	.dma_dev	= &mx3_ipu.dev,
+	.name		= "CMO_QVGA",
+	.mode		= fb_modedb,
+	.num_modes	= ARRAY_SIZE(fb_modedb),
+};
+
+static struct pad_desc eukrea_mbimxsd_pads[] = {
+	/* LCD */
+	MX35_PAD_LD0__IPU_DISPB_DAT_0,
+	MX35_PAD_LD1__IPU_DISPB_DAT_1,
+	MX35_PAD_LD2__IPU_DISPB_DAT_2,
+	MX35_PAD_LD3__IPU_DISPB_DAT_3,
+	MX35_PAD_LD4__IPU_DISPB_DAT_4,
+	MX35_PAD_LD5__IPU_DISPB_DAT_5,
+	MX35_PAD_LD6__IPU_DISPB_DAT_6,
+	MX35_PAD_LD7__IPU_DISPB_DAT_7,
+	MX35_PAD_LD8__IPU_DISPB_DAT_8,
+	MX35_PAD_LD9__IPU_DISPB_DAT_9,
+	MX35_PAD_LD10__IPU_DISPB_DAT_10,
+	MX35_PAD_LD11__IPU_DISPB_DAT_11,
+	MX35_PAD_LD12__IPU_DISPB_DAT_12,
+	MX35_PAD_LD13__IPU_DISPB_DAT_13,
+	MX35_PAD_LD14__IPU_DISPB_DAT_14,
+	MX35_PAD_LD15__IPU_DISPB_DAT_15,
+	MX35_PAD_LD16__IPU_DISPB_DAT_16,
+	MX35_PAD_LD17__IPU_DISPB_DAT_17,
+	MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+	MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+	MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+	MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+	/* Backlight */
+	MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+	/* LCD_PWR */
+	MX35_PAD_D3_CLS__GPIO1_4,
+	/* LED */
+	MX35_PAD_LD23__GPIO3_29,
+	/* SWITCH */
+	MX35_PAD_LD19__GPIO3_25,
+	/* UART2 */
+	MX35_PAD_CTS2__UART2_CTS,
+	MX35_PAD_RTS2__UART2_RTS,
+	MX35_PAD_TXD2__UART2_TXD_MUX,
+	MX35_PAD_RXD2__UART2_RXD_MUX,
+	/* I2S */
+	MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
+	MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
+	MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
+	MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+};
+
+#define GPIO_LED1	(2 * 32 + 29)
+#define GPIO_SWITCH1	(2 * 32 + 25)
+#define GPIO_LCDPWR	(4)
+
+static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
+				   unsigned int power)
+{
+	if (power)
+		gpio_direction_output(GPIO_LCDPWR, 1);
+	else
+		gpio_direction_output(GPIO_LCDPWR, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
+	.set_power		= eukrea_mbimxsd_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
+	.name			= "platform-lcd",
+	.dev.platform_data	= &eukrea_mbimxsd_lcd_power_data,
+};
+
+static struct gpio_led eukrea_mbimxsd_leds[] = {
+	{
+		.name			= "led1",
+		.default_trigger	= "heartbeat",
+		.active_low		= 1,
+		.gpio			= GPIO_LED1,
+	},
+};
+
+static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+	.leds		= eukrea_mbimxsd_leds,
+	.num_leds	= ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct platform_device eukrea_mbimxsd_leds_gpio = {
+	.name	= "leds-gpio",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &eukrea_mbimxsd_led_info,
+	},
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+	{
+		.gpio		= GPIO_SWITCH1,
+		.code		= BTN_0,
+		.desc		= "BP1",
+		.active_low	= 1,
+		.wakeup		= 1,
+	},
+};
+
+static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+	.buttons	= eukrea_mbimxsd_gpio_buttons,
+	.nbuttons	= ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static struct platform_device eukrea_mbimxsd_button_device = {
+	.name		= "gpio-keys",
+	.id		= -1,
+	.num_resources	= 0,
+	.dev		= {
+		.platform_data	= &eukrea_mbimxsd_button_data,
+	}
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+	&eukrea_mbimxsd_leds_gpio,
+	&eukrea_mbimxsd_button_device,
+	&eukrea_mbimxsd_lcd_powerdev,
+};
+
+static struct imxuart_platform_data uart_pdata = {
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("tlv320aic23", 0x1a),
+	},
+};
+
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
+	.flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx35 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd_baseboard_init(void)
+{
+	if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+			ARRAY_SIZE(eukrea_mbimxsd_pads)))
+		printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+	/* SSI unit master I2S codec connected to SSI_AUD4 */
+	mxc_audmux_v2_configure_port(0,
+			MXC_AUDMUX_V2_PTCR_SYN |
+			MXC_AUDMUX_V2_PTCR_TFSDIR |
+			MXC_AUDMUX_V2_PTCR_TFSEL(3) |
+			MXC_AUDMUX_V2_PTCR_TCLKDIR |
+			MXC_AUDMUX_V2_PTCR_TCSEL(3),
+			MXC_AUDMUX_V2_PDCR_RXDSEL(3)
+	);
+	mxc_audmux_v2_configure_port(3,
+			MXC_AUDMUX_V2_PTCR_SYN,
+			MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+	);
+#endif
+
+	mxc_register_device(&mxc_uart_device1, &uart_pdata);
+	mxc_register_device(&mx3_ipu, &mx3_ipu_data);
+	mxc_register_device(&mx3_fb, &mx3fb_pdata);
+
+	mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
+
+	gpio_request(GPIO_LED1, "LED1");
+	gpio_direction_output(GPIO_LED1, 1);
+	gpio_free(GPIO_LED1);
+
+	gpio_request(GPIO_SWITCH1, "SWITCH1");
+	gpio_direction_input(GPIO_SWITCH1);
+	gpio_free(GPIO_SWITCH1);
+
+	gpio_request(GPIO_LCDPWR, "LCDPWR");
+	gpio_direction_output(GPIO_LCDPWR, 1);
+	gpio_free(GPIO_SWITCH1);
+
+	i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+				ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
new file mode 100644
index 0000000..26fc976
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -0,0 +1,227 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric at eukrea.com
+ * Copyright (C) 2009 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/board-eukrea_cpuimx35.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/i2c.h>
+#include <mach/iomux-mx35.h>
+#include <mach/mxc_nand.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
+
+#include "devices.h"
+
+static struct imxuart_platform_data uart_pdata = {
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct imxi2c_platform_data eukrea_cpuimx35_i2c_1_data = {
+	.bitrate = 50000,
+};
+
+#define TSC2007_IRQGPIO		(2 * 32 + 2)
+static int ts_get_pendown_state(void)
+{
+	int val = 0;
+	gpio_free(TSC2007_IRQGPIO);
+	gpio_request(TSC2007_IRQGPIO, NULL);
+	gpio_direction_input(TSC2007_IRQGPIO);
+
+	val = gpio_get_value(TSC2007_IRQGPIO);
+
+	gpio_free(TSC2007_IRQGPIO);
+	gpio_request(TSC2007_IRQGPIO, NULL);
+
+	return val ? 0 : 1;
+}
+
+static int ts_init(void)
+{
+	gpio_request(TSC2007_IRQGPIO, NULL);
+	return 0;
+}
+
+static struct tsc2007_platform_data tsc2007_info = {
+	.model			= 2007,
+	.x_plate_ohms		= 180,
+	.get_pendown_state	= ts_get_pendown_state,
+	.init_platform_hw	= ts_init,
+};
+
+static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("pcf8563", 0x51),
+	}, {
+		I2C_BOARD_INFO("tsc2007", 0x48),
+		.type		= "tsc2007",
+		.platform_data	= &tsc2007_info,
+		.irq		= gpio_to_irq(TSC2007_IRQGPIO),
+	},
+};
+
+static struct platform_device *devices[] __initdata = {
+	&mxc_fec_device,
+	&imx_wdt_device0,
+};
+
+static struct pad_desc eukrea_cpuimx35_pads[] = {
+	/* UART1 */
+	MX35_PAD_CTS1__UART1_CTS,
+	MX35_PAD_RTS1__UART1_RTS,
+	MX35_PAD_TXD1__UART1_TXD_MUX,
+	MX35_PAD_RXD1__UART1_RXD_MUX,
+	/* FEC */
+	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+	MX35_PAD_FEC_COL__FEC_COL,
+	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+	MX35_PAD_FEC_MDC__FEC_MDC,
+	MX35_PAD_FEC_MDIO__FEC_MDIO,
+	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+	MX35_PAD_FEC_CRS__FEC_CRS,
+	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+	/* I2C1 */
+	MX35_PAD_I2C1_CLK__I2C1_SCL,
+	MX35_PAD_I2C1_DAT__I2C1_SDA,
+	/* TSC2007 IRQ */
+	MX35_PAD_ATA_DA2__GPIO3_2,
+};
+
+static struct mxc_nand_platform_data pcm037_nand_board_info = {
+	.width		= 1,
+	.hw_ecc		= 1,
+	.flash_bbt	= 1,
+};
+
+static struct mxc_usbh_platform_data otg_pdata = {
+	.portsc	= MXC_EHCI_MODE_UTMI,
+	.flags	= MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+static struct mxc_usbh_platform_data usbh1_pdata = {
+	.portsc	= MXC_EHCI_MODE_SERIAL,
+	.flags	= MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
+		  MXC_EHCI_IPPUE_DOWN,
+};
+
+static struct fsl_usb2_platform_data otg_device_pdata = {
+	.operating_mode	= FSL_USB2_DR_DEVICE,
+	.phy_mode	= FSL_USB2_PHY_UTMI,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx35_otg_mode(char *options)
+{
+	if (!strcmp(options, "host"))
+		otg_mode_host = 1;
+	else if (!strcmp(options, "device"))
+		otg_mode_host = 0;
+	else
+		pr_info("otg_mode neither \"host\" nor \"device\". "
+			"Defaulting to device\n");
+	return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx35_otg_mode);
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
+			ARRAY_SIZE(eukrea_cpuimx35_pads));
+
+	platform_add_devices(devices, ARRAY_SIZE(devices));
+
+	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
+
+	i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
+			ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
+	mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx35_i2c_1_data);
+
+#if defined(CONFIG_USB_ULPI)
+	if (otg_mode_host) {
+		otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+		mxc_register_device(&mxc_otg_host, &otg_pdata);
+	}
+	mxc_register_device(&mxc_usbh1, &usbh1_pdata);
+#endif
+	if (!otg_mode_host)
+		mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD
+	eukrea_mbimxsd_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx35_timer_init(void)
+{
+	mx35_clocks_init();
+}
+
+struct sys_timer eukrea_cpuimx35_timer = {
+	.init	= eukrea_cpuimx35_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
+	/* Maintainer: Eukrea Electromatique */
+	.phys_io	= MX35_AIPS1_BASE_ADDR,
+	.io_pg_offst	= ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
+	.map_io         = mx35_map_io,
+	.init_irq       = mx35_init_irq,
+	.init_machine   = mxc_board_init,
+	.timer          = &eukrea_cpuimx35_timer,
+MACHINE_END
+
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx35.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx35.h
new file mode 100644
index 0000000..116eee7
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx35.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric at eukrea.com
+ *
+ * Based on board-pcm038.h which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel at pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX35_H__
+#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX35_H__
+
+#ifndef __ASSEMBLY__
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ * TODO: Add your own baseboard init function and call it from
+ * inside eukrea_cpuimx25_init().
+ *
+ * This example here is for the development board. Refer
+ * eukrea_mbimx25-baseboard.c
+ */
+
+extern void eukrea_mbimxsd_baseboard_init(void);
+
+#endif
+
+#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX35_H__ */
-- 
1.6.3.3



From ext-phil.2.carmody at nokia.com  Thu Jun 10 10:14:02 2010
From: ext-phil.2.carmody at nokia.com (Phil Carmody)
Date: Thu, 10 Jun 2010 17:14:02 +0300
Subject: [PATCH 0/3] ARM: unwind extension
In-Reply-To: <1275567442-11370-1-git-send-email-ext-phil.2.carmody@nokia.com>
References: <1275567442-11370-1-git-send-email-ext-phil.2.carmody@nokia.com>
Message-ID: <20100610141402.GY17639@pcarmody-desktop>

On 03/06/10 14:17 +0200, Carmody Phil.2 (EXT-Ixonos/Helsinki) wrote:
> 
> The first two patches are simply preparation for the third, making it
> effectively trivial, even though it's the only one with a concrete 
> change in behaviour.
> 
> The origins of this patchset are the discovery that unwind and kmemleak
> don't always cooperate well with each other - any allocation within 
> an exit or devexit function causes kmemleak to look up symbols that 
> aren't in any unwind table. This of course means that all WARN_ONs and
> BUGs will suffer the same fate.
> 
> It could certainly be said that with a typical system the linked list
> has grown too large to be practical as a container, and some improvements
> could be made in that direction in the future.

Catalin, 

Have you had a chance to look at these yet? The linked-list efficiency
issue I mention in the final paragraph above is a no-brainer; I have a 
1-line tweak that improves the real-world efficiency so much that on 
average there are only 2 linked list operations rather than (on a 50+
module system) 70. However, that patch is orthogonal to the above set, 
so I'll not mix the two.

Phil


From will.deacon at arm.com  Thu Jun 10 10:16:49 2010
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 10 Jun 2010 15:16:49 +0100
Subject: Context Switching is Broken
In-Reply-To: <20100610140136.GA32362@n2100.arm.linux.org.uk>
References: <503171.97993.qm@web51806.mail.re2.yahoo.com>
	<20100610140136.GA32362@n2100.arm.linux.org.uk>
Message-ID: <004801cb08a7$913a9f90$b3afdeb0$@deacon@arm.com>

> On Thu, Jun 10, 2010 at 04:11:35AM -0700, Herman Swartz wrote:
> > Context switching is broken. The man page for context is example code
> > that doesn't work, but should. Does a bug report need to be submitted?
> 
> $ man context
> No manual entry for context
> 
> ?
> 

Quite. man makecontext has a fairly scary example, maybe that's
it.

Will




From linux at arm.linux.org.uk  Thu Jun 10 10:20:15 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 10 Jun 2010 15:20:15 +0100
Subject: Context Switching is Broken
In-Reply-To: <004801cb08a7$913a9f90$b3afdeb0$@deacon@arm.com>
References: <503171.97993.qm@web51806.mail.re2.yahoo.com>
	<20100610140136.GA32362@n2100.arm.linux.org.uk>
	<004801cb08a7$913a9f90$b3afdeb0$@deacon@arm.com>
Message-ID: <20100610142015.GC32362@n2100.arm.linux.org.uk>

On Thu, Jun 10, 2010 at 03:16:49PM +0100, Will Deacon wrote:
> > On Thu, Jun 10, 2010 at 04:11:35AM -0700, Herman Swartz wrote:
> > > Context switching is broken. The man page for context is example code
> > > that doesn't work, but should. Does a bug report need to be submitted?
> > 
> > $ man context
> > No manual entry for context
> > 
> > ?
> > 
> 
> Quite. man makecontext has a fairly scary example, maybe that's it.

In which case it's a question for libc people - the kernel has nothing
to do with makecontext, getcontext, setcontext and swapcontext.

I believe for glibc, these are simply unimplemented on ARM, and linking
a program which uses makecontext with glibc would result in the linker
issuing:

warning: makecontext is not implemented and will always fail

Same for the other three functions.


From catalin.marinas at arm.com  Thu Jun 10 10:42:59 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 10 Jun 2010 15:42:59 +0100
Subject: [PATCH 1/3] ARM: module - simplify code with temporaries
In-Reply-To: <1275567442-11370-2-git-send-email-ext-phil.2.carmody@nokia.com>
References: <1275567442-11370-2-git-send-email-ext-phil.2.carmody@nokia.com>
Message-ID: <1276180979.24535.45.camel@e102109-lin.cambridge.arm.com>

On Thu, 2010-06-03 at 13:17 +0100, Phil Carmody wrote:
> Less to read.
> 
> Signed-off-by: Phil Carmody <ext-phil.2.carmody at nokia.com>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>

-- 
Catalin



From catalin.marinas at arm.com  Thu Jun 10 10:43:23 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 10 Jun 2010 15:43:23 +0100
Subject: [PATCH 2/3] ARM: module - simplify unwind table handling
In-Reply-To: <1275567442-11370-3-git-send-email-ext-phil.2.carmody@nokia.com>
References: <1275567442-11370-3-git-send-email-ext-phil.2.carmody@nokia.com>
Message-ID: <1276181003.24535.46.camel@e102109-lin.cambridge.arm.com>

On Thu, 2010-06-03 at 13:17 +0100, Phil Carmody wrote:
> The various sections are all dealt with similarly, so factor out
> that common behaviour.
> 
> Signed-off-by: Phil Carmody <ext-phil.2.carmody at nokia.com>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>

-- 
Catalin



From catalin.marinas at arm.com  Thu Jun 10 10:48:16 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 10 Jun 2010 15:48:16 +0100
Subject: [PATCH 3/3] ARM: module - additional unwind tables for
	exit/devexit sections
In-Reply-To: <1275567442-11370-4-git-send-email-ext-phil.2.carmody@nokia.com>
References: <1275567442-11370-4-git-send-email-ext-phil.2.carmody@nokia.com>
Message-ID: <1276181296.24535.51.camel@e102109-lin.cambridge.arm.com>

On Thu, 2010-06-03 at 13:17 +0100, Phil Carmody wrote:
> Without these, exit functions cannot be stack-traced, so to speak.
> This implies that module unloads that perform allocations (don't
> laugh) will cause noisy warnings on the console when kmemleak is
> enabled, as it presumes that all code's call chains are traceable.
> Similarly, BUGs and WARN_ONs will give additional console spam.
> 
> Signed-off-by: Phil Carmody <ext-phil.2.carmody at nokia.com>

Acked-by: Catalin Marinas <catalin.marinas at arm.com>

-- 
Catalin



From will.deacon at arm.com  Thu Jun 10 10:59:57 2010
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 10 Jun 2010 15:59:57 +0100
Subject: [PATCH 4/4] ARM: hw-breakpoint: add HAVE_HW_BREAKPOINT to Kconfig
In-Reply-To: <1276181997-20677-4-git-send-email-will.deacon@arm.com>
References: <1276181997-20677-1-git-send-email-will.deacon@arm.com>
	<1276181997-20677-2-git-send-email-will.deacon@arm.com>
	<1276181997-20677-3-git-send-email-will.deacon@arm.com>
	<1276181997-20677-4-git-send-email-will.deacon@arm.com>
Message-ID: <1276181997-20677-5-git-send-email-will.deacon@arm.com>

If we're targetting a v6 or v7 core and have at least software perf events
available, then automatically add support for hardware breakpoints.

Cc: Frederic Weisbecker <fweisbec at gmail.com>
Cc: S. Karthikeyan <informkarthik at gmail.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/Kconfig         |    1 +
 arch/arm/kernel/Makefile |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e57cb24..7ed4d58 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -24,6 +24,7 @@ config ARM
 	select HAVE_KERNEL_LZMA
 	select HAVE_PERF_EVENTS
 	select PERF_USE_VMALLOC
+	select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V7))
 	help
 	  The ARM series is a line of low-power-consumption RISC chip designs
 	  licensed by ARM Ltd and targeted at embedded applications and
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 26d302c..e679fb0 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_ARM_THUMBEE)	+= thumbee.o
 obj-$(CONFIG_KGDB)		+= kgdb.o
 obj-$(CONFIG_ARM_UNWIND)	+= unwind.o
 obj-$(CONFIG_HAVE_TCM)		+= tcm.o
+obj-$(CONFIG_HAVE_HW_BREAKPOINT)	+= hw_breakpoint.o
 
 obj-$(CONFIG_CRUNCH)		+= crunch.o crunch-bits.o
 AFLAGS_crunch-bits.o		:= -Wa,-mcpu=ep9312
-- 
1.6.3.3



From will.deacon at arm.com  Thu Jun 10 10:59:53 2010
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 10 Jun 2010 15:59:53 +0100
Subject: [RFC PATCH 0/4] ARM: add support for hw-breakpoints [v3]
Message-ID: <1276181997-20677-1-git-send-email-will.deacon@arm.com>

This is version 3 of the RFC patches originally posted at:

v1.) http://lists.infradead.org/pipermail/linux-arm-kernel/2010-February/009084.html
v2.) http://lists.infradead.org/pipermail/linux-arm-kernel/2010-March/011170.html

Changes from v2 include:
	- Based on 2.6.35-rc2
	- Updated to use new hw-breakpoint API features
	- Addressed some comments from Frederic on LKML
	- Complete redesign of the ptrace interface so that it
	  follows the ARM ARM (v7) register structure more closely.

Unfortunately, I've only managed to compile-test this and check that the
resulting image boots. The main reasons for posting are (a) to support
current GDB development and (b) to attract comments on the code.

All comments welcome.

Cc: Frederic Weisbecker <fweisbec at gmail.com>
Cc: S. Karthikeyan <informkarthik at gmail.com>

Will Deacon (4):
  ARM: hw-breakpoint: add mechanism for hooking into prefetch aborts
  ARM: hw-breakpoint: add ARM backend for the hw-breakpoint framework
  ARM: hw-breakpoint: add new ptrace requests for hw-breakpoint
    interaction
  ARM: hw-breakpoint: add HAVE_HW_BREAKPOINT to Kconfig

 arch/arm/Kconfig                     |    1 +
 arch/arm/include/asm/hw_breakpoint.h |  117 ++++++
 arch/arm/include/asm/processor.h     |    4 +
 arch/arm/include/asm/ptrace.h        |    2 +
 arch/arm/include/asm/system.h        |    3 +
 arch/arm/kernel/Makefile             |    1 +
 arch/arm/kernel/hw_breakpoint.c      |  734 ++++++++++++++++++++++++++++++++++
 arch/arm/kernel/ptrace.c             |  196 +++++++++
 arch/arm/mm/fault.c                  |   11 +
 9 files changed, 1069 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/hw_breakpoint.h
 create mode 100644 arch/arm/kernel/hw_breakpoint.c



From will.deacon at arm.com  Thu Jun 10 10:59:54 2010
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 10 Jun 2010 15:59:54 +0100
Subject: [PATCH 1/4] ARM: hw-breakpoint: add mechanism for hooking into
	prefetch aborts
In-Reply-To: <1276181997-20677-1-git-send-email-will.deacon@arm.com>
References: <1276181997-20677-1-git-send-email-will.deacon@arm.com>
Message-ID: <1276181997-20677-2-git-send-email-will.deacon@arm.com>

On ARM processors with hardware breakpoint and watchpoint support,
triggering these events results in a debug exception. These manifest
as prefetch and data aborts respectively.

arch/arm/mm/fault.c already provides hook_fault_code for hooking
into data aborts dependent on the DFSR. This patch adds a new function,
hook_ifault_code for hooking into prefetch aborts in the same manner.

Cc: Frederic Weisbecker <fweisbec at gmail.com>
Cc: S. Karthikeyan <informkarthik at gmail.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/system.h |    3 +++
 arch/arm/mm/fault.c           |   11 +++++++++++
 2 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 5f4f480..42da2f8 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -84,6 +84,9 @@ void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
 				       struct pt_regs *),
 		     int sig, const char *name);
+void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int,
+				       struct pt_regs *),
+		     int sig, const char *name);
 
 #define xchg(ptr,x) \
 	((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 92f5801..a71b410 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -572,6 +572,17 @@ static struct fsr_info ifsr_info[] = {
 	{ do_bad,		SIGBUS,  0,		"unknown 31"			   },
 };
 
+void __init
+hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int, struct pt_regs *),
+			int sig, const char *name)
+{
+	if (nr >= 0 && nr < ARRAY_SIZE(ifsr_info)) {
+		ifsr_info[nr].fn   = fn;
+		ifsr_info[nr].sig  = sig;
+		ifsr_info[nr].name = name;
+	}
+}
+
 asmlinkage void __exception
 do_PrefetchAbort(unsigned long addr, unsigned int ifsr, struct pt_regs *regs)
 {
-- 
1.6.3.3



From will.deacon at arm.com  Thu Jun 10 10:59:56 2010
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 10 Jun 2010 15:59:56 +0100
Subject: [PATCH 3/4] ARM: hw-breakpoint: add new ptrace requests for
	hw-breakpoint interaction
In-Reply-To: <1276181997-20677-3-git-send-email-will.deacon@arm.com>
References: <1276181997-20677-1-git-send-email-will.deacon@arm.com>
	<1276181997-20677-2-git-send-email-will.deacon@arm.com>
	<1276181997-20677-3-git-send-email-will.deacon@arm.com>
Message-ID: <1276181997-20677-4-git-send-email-will.deacon@arm.com>

For debuggers to take advantage of the hw-breakpoint framework in the kernel,
it is necessary to expose the API calls via a ptrace interface.

This patch exposes the hardware breakpoints framework as a collection of
virtual registers, accesible using PTRACE_SETHBPREGS and PTRACE_GETHBPREGS
requests. The breakpoints are stored in the debug_info struct of the running
thread.

Cc: Frederic Weisbecker <fweisbec at gmail.com>
Cc: S. Karthikeyan <informkarthik at gmail.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/processor.h |    4 +
 arch/arm/include/asm/ptrace.h    |    2 +
 arch/arm/kernel/hw_breakpoint.c  |   13 +++
 arch/arm/kernel/ptrace.c         |  196 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 215 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
index 6a89567..dbd33c3 100644
--- a/arch/arm/include/asm/processor.h
+++ b/arch/arm/include/asm/processor.h
@@ -19,6 +19,7 @@
 
 #ifdef __KERNEL__
 
+#include <asm/hw_breakpoint.h>
 #include <asm/ptrace.h>
 #include <asm/types.h>
 
@@ -41,6 +42,9 @@ struct debug_entry {
 struct debug_info {
 	int			nsaved;
 	struct debug_entry	bp[2];
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+	struct perf_event	*hbp[ARM_MAX_HBP_SLOTS];
+#endif
 };
 
 struct thread_struct {
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 9dcb11e..21560e4 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -29,6 +29,8 @@
 #define PTRACE_SETCRUNCHREGS	26
 #define PTRACE_GETVFPREGS	27
 #define PTRACE_SETVFPREGS	28
+#define PTRACE_GETHBPREGS	29
+#define PTRACE_SETHBPREGS	30
 
 /*
  * PSR bits
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index b249cd7..5d5faec 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -647,6 +647,19 @@ out:
 	return ret;
 }
 
+static int hw_breakpoint_thread_notify(struct notifier_block *self,
+				       unsigned long cmd, void *t)
+{
+	if (cmd == THREAD_NOTIFY_FLUSH)
+		flush_ptrace_hw_breakpoint(current);
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block hw_breakpoint_thread_notifier_block = {
+	.notifier_call = hw_breakpoint_thread_notify,
+};
+
 /*
  * One-time initialisation.
  */
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3f562a7..51b9931 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -19,6 +19,8 @@
 #include <linux/init.h>
 #include <linux/signal.h>
 #include <linux/uaccess.h>
+#include <linux/perf_event.h>
+#include <linux/hw_breakpoint.h>
 
 #include <asm/pgtable.h>
 #include <asm/system.h>
@@ -751,6 +753,189 @@ static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
 }
 #endif
 
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+/*
+ * Handle hitting a HW-breakpoint.
+ */
+static void ptrace_hbptriggered(struct perf_event *bp, int unused,
+				     struct perf_sample_data *data,
+				     struct pt_regs *regs)
+{
+	struct arch_hw_breakpoint *bkpt = counter_arch_bp(bp);
+	siginfo_t info;
+
+	info.si_signo	= SIGTRAP;
+	info.si_errno	= bkpt->ctrl.type;
+	info.si_code	= TRAP_HWBKPT;
+	info.si_addr	= (void __user *)(bkpt->trigger);
+
+	force_sig_info(SIGTRAP, &info, current);
+}
+
+void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
+{
+	int i;
+	struct thread_struct *t = &tsk->thread;
+
+	for (i = 0; i < ARM_MAX_HBP_SLOTS; i++) {
+		unregister_hw_breakpoint(t->debug.hbp[i]);
+		t->debug.hbp[i] = NULL;
+	}
+}
+
+static u32 ptrace_get_hbp_resource_info(void)
+{
+	u8 num_brps, num_wrps, debug_arch, wp_len;
+	u32 reg = 0;
+
+	num_brps	= hw_breakpoint_slots(TYPE_INST);
+	num_wrps	= hw_breakpoint_slots(TYPE_DATA);
+	debug_arch	= arch_get_debug_arch();
+	wp_len		= arch_get_max_wp_len();
+
+	reg		|= debug_arch;
+	reg		<<= 8;
+	reg		|= wp_len;
+	reg		<<= 8;
+	reg		|= num_wrps;
+	reg		<<= 8;
+	reg		|= num_brps;
+
+	return reg;
+}
+
+/*
+ * Convert a virtual register number into an index for a thread_info
+ * breakpoint array. Breakpoints are identified using positive numbers
+ * whilst watchpoints are negative. The registers are laid out as pairs
+ * of (address, control), each pair mapping to a unique hw_breakpoint struct.
+ * Register 0 is reserved for describing resource information.
+ */
+static int ptrace_hbp_num_to_idx(long num)
+{
+	if (num < 0)
+		num = (ARM_MAX_BRP << 1) - num;
+	return (num - 1) >> 1;
+}
+
+static struct perf_event *ptrace_hbp_create(struct task_struct *tsk, int type)
+{
+	struct perf_event_attr attr;
+
+	hw_breakpoint_init(&attr);
+
+	/* Initialise fields to sane defaults. */
+	attr.bp_addr	= 0;
+	attr.bp_len	= HW_BREAKPOINT_LEN_4;
+	attr.type	= type;
+	attr.disabled	= 1;
+
+	return register_user_hw_breakpoint(&attr, ptrace_hbptriggered, tsk);
+}
+
+static int ptrace_gethbpregs(struct task_struct *tsk, long num,
+			     unsigned long  __user *data)
+{
+	u32 reg;
+	int idx, ret = 0;
+	struct perf_event *bp;
+	struct arch_hw_breakpoint *arch_bp;
+
+	if (num == 0) {
+		reg = ptrace_get_hbp_resource_info();
+	} else {
+		idx = ptrace_hbp_num_to_idx(num);
+		if (idx < 0 || idx >= ARM_MAX_HBP_SLOTS) {
+			ret = -EINVAL;
+			goto out;
+		}
+
+		bp = tsk->thread.debug.hbp[idx];
+		if (!bp) {
+			reg = 0;
+			goto put;
+		}
+
+		arch_bp = counter_arch_bp(bp);
+		if (idx & 0x1)
+			reg = encode_ctrl_reg(arch_bp->ctrl);
+		else
+			reg = arch_bp->address;
+	}
+
+put:
+	if (put_user(reg, data))
+		ret = -EFAULT;
+
+out:
+	return ret;
+}
+
+static int ptrace_sethbpregs(struct task_struct *tsk, long num,
+			     unsigned long __user *data)
+{
+	int idx, gen_len, gen_type, implied_type, ret = 0;
+	u32 user_val;
+	struct perf_event *bp;
+	struct arch_hw_breakpoint_ctrl ctrl;
+	struct perf_event_attr attr;
+
+	if (num == 0)
+		goto out;
+	else if (num < 0)
+		implied_type = HW_BREAKPOINT_RW;
+	else
+		implied_type = HW_BREAKPOINT_X;
+
+	idx = ptrace_hbp_num_to_idx(num);
+	if (idx < 0 || idx >= ARM_MAX_HBP_SLOTS) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (get_user(user_val, data)) {
+		ret = -EFAULT;
+		goto out;
+	}
+
+	bp = tsk->thread.debug.hbp[idx];
+	if (!bp) {
+		bp = ptrace_hbp_create(tsk, implied_type);
+		if (IS_ERR(bp)) {
+			ret = PTR_ERR(bp);
+			goto out;
+		}
+		tsk->thread.debug.hbp[idx] = bp;
+	}
+
+	attr = bp->attr;
+
+	if (idx & 0x1) {
+		/* Control */
+		decode_ctrl_reg(user_val, &ctrl);
+		ret = arch_bp_generic_fields(ctrl, &gen_len, &gen_type);
+		if (ret)
+			goto out;
+
+		if ((gen_type & implied_type) != gen_type) {
+				ret = -EINVAL;
+				goto out;
+		}
+
+		attr.bp_len	= gen_len;
+		attr.bp_type	= gen_type;
+		attr.disabled	= ~ctrl.enabled;
+	} else {
+		/* Address */
+		attr.bp_addr	= user_val;
+	}
+
+	ret = modify_user_hw_breakpoint(bp, &attr);
+out:
+	return ret;
+}
+#endif
+
 long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 {
 	int ret;
@@ -820,6 +1005,17 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 			break;
 #endif
 
+#ifdef CONFIG_HAVE_HW_BREAKPOINT
+		case PTRACE_GETHBPREGS:
+			ret = ptrace_gethbpregs(child, addr,
+						(unsigned long __user *)data);
+			break;
+		case PTRACE_SETHBPREGS:
+			ret = ptrace_sethbpregs(child, addr,
+						(unsigned long __user *)data);
+			break;
+#endif
+
 		default:
 			ret = ptrace_request(child, request, addr, data);
 			break;
-- 
1.6.3.3



From will.deacon at arm.com  Thu Jun 10 10:59:55 2010
From: will.deacon at arm.com (Will Deacon)
Date: Thu, 10 Jun 2010 15:59:55 +0100
Subject: [PATCH 2/4] ARM: hw-breakpoint: add ARM backend for the hw-breakpoint
	framework
In-Reply-To: <1276181997-20677-2-git-send-email-will.deacon@arm.com>
References: <1276181997-20677-1-git-send-email-will.deacon@arm.com>
	<1276181997-20677-2-git-send-email-will.deacon@arm.com>
Message-ID: <1276181997-20677-3-git-send-email-will.deacon@arm.com>

The hw-breakpoint framework in the kernel requires architecture-specific
support in order to install, remove, validate and manage hardware
breakpoints.

This patch adds preliminary support for this framework to the ARM
architecture, but restricts the number of watchpoints to a single resource
to get around the fact that the Data Fault Address Register is unpredictable
when a watchpoint debug exception is taken.

Currently, clients must handle synchronous breakpoint exceptions.
This requires the ability to single-step over the causative instruction to
avoid getting stuck in an infinite loop.

The memory-mapped extended debug interface is unsupported due to its
unreliability in real implementations.

Cc: Frederic Weisbecker <fweisbec at gmail.com>
Cc: S. Karthikeyan <informkarthik at gmail.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/hw_breakpoint.h |  117 ++++++
 arch/arm/kernel/hw_breakpoint.c      |  721 ++++++++++++++++++++++++++++++++++
 2 files changed, 838 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/hw_breakpoint.h
 create mode 100644 arch/arm/kernel/hw_breakpoint.c

diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
new file mode 100644
index 0000000..c995219
--- /dev/null
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -0,0 +1,117 @@
+#ifndef _ARM_HW_BREAKPOINT_H
+#define _ARM_HW_BREAKPOINT_H
+
+#ifdef __KERNEL__
+struct arch_hw_breakpoint_ctrl {
+		u32 __reserved	: 19,
+		len		: 8,
+		type		: 2,
+		privilege	: 2,
+		enabled		: 1;
+};
+
+struct arch_hw_breakpoint {
+	u32	address;
+	u32	trigger;
+	struct arch_hw_breakpoint_ctrl ctrl;
+};
+
+static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
+{
+	return (ctrl.len << 5) | (ctrl.type << 3) |
+		(ctrl.privilege << 1) | ctrl.enabled;
+}
+
+static inline void decode_ctrl_reg(u32 reg,
+				   struct arch_hw_breakpoint_ctrl *ctrl)
+{
+	ctrl->enabled	= reg & 0x1;
+	reg >>= 1;
+	ctrl->privilege	= reg & 0x3;
+	reg >>= 2;
+	ctrl->type	= reg & 0x3;
+	reg >>= 2;
+	ctrl->len	= reg & 0xff;
+}
+
+/* Debug architecture numbers. */
+#define ARM_DEBUG_ARCH_V6	1
+#define ARM_DEBUG_ARCH_V6_1	2
+#define ARM_DEBUG_ARCH_V7_ECP14	3
+#define ARM_DEBUG_ARCH_V7_MM	4
+
+/* Breakpoint */
+#define ARM_BREAKPOINT_EXECUTE	0
+
+/* Watchpoints */
+#define ARM_BREAKPOINT_LOAD	1
+#define ARM_BREAKPOINT_STORE	2
+
+/* Privilege Levels */
+#define ARM_BREAKPOINT_PRIV	1
+#define ARM_BREAKPOINT_USER	2
+
+/* Lengths */
+#define ARM_BREAKPOINT_LEN_1	0x1
+#define ARM_BREAKPOINT_LEN_2	0x3
+#define ARM_BREAKPOINT_LEN_4	0xf
+#define ARM_BREAKPOINT_LEN_8	0xff
+
+/* Limits */
+#define ARM_MAX_BRP		16
+#define ARM_MAX_WRP		16
+#define ARM_MAX_HBP_SLOTS	(ARM_MAX_BRP + ARM_MAX_WRP)
+
+/* DSCR method of entry bits. */
+#define ARM_DSCR_MOE(x)			((x >> 2) & 0xf)
+#define ARM_ENTRY_BREAKPOINT		0x1
+#define ARM_ENTRY_ASYNC_WATCHPOINT	0x2
+#define ARM_ENTRY_SYNC_WATCHPOINT	0xa
+
+/* DSCR monitor/halting bits. */
+#define ARM_DSCR_HDBGEN		(1 << 14)
+#define ARM_DSCR_MDBGEN		(1 << 15)
+
+/* opcode2 numbers for the co-processor instructions. */
+#define ARM_OP2_BVR		4
+#define ARM_OP2_BCR		5
+#define ARM_OP2_WVR		6
+#define ARM_OP2_WCR		7
+
+/* Base register numbers for the debug registers. */
+#define ARM_BASE_BVR		64
+#define ARM_BASE_BCR		80
+#define ARM_BASE_WVR		96
+#define ARM_BASE_WCR		112
+
+/* Accessor macros for the debug registers. */
+#define ARM_DBG_READ(M, OP2, VAL) do {\
+	asm volatile("mrc p14, 0, %0, c0," #M ", " #OP2 : "=r" (VAL));\
+} while (0)
+
+#define ARM_DBG_WRITE(M, OP2, VAL) do {\
+	asm volatile("mcr p14, 0, %0, c0," #M ", " #OP2 : : "r" (VAL));\
+} while (0)
+
+struct notifier_block;
+struct perf_event;
+struct pmu;
+struct task_struct;
+
+extern struct pmu perf_ops_bp;
+extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
+				  int *gen_len, int *gen_type);
+extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
+extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
+extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+					   unsigned long val, void *data);
+extern u8 arch_get_debug_arch(void);
+extern u8 arch_get_max_wp_len(void);
+
+int arch_install_hw_breakpoint(struct perf_event *bp);
+void arch_uninstall_hw_breakpoint(struct perf_event *bp);
+void hw_breakpoint_pmu_read(struct perf_event *bp);
+int hw_breakpoint_slots(int type);
+
+#endif	/* __KERNEL__ */
+#endif	/* _ARM_HW_BREAKPOINT_H */
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
new file mode 100644
index 0000000..b249cd7
--- /dev/null
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -0,0 +1,721 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2009, 2010 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon at arm.com>
+ */
+
+/*
+ * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
+ * using the CPU's debug registers.
+ */
+
+#define pr_fmt(fmt) "hw-breakpoint: " fmt
+
+#include <linux/errno.h>
+#include <linux/perf_event.h>
+#include <linux/hw_breakpoint.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+#include <asm/cputype.h>
+#include <asm/current.h>
+#include <asm/hw_breakpoint.h>
+#include <asm/kdebug.h>
+#include <asm/system.h>
+#include <asm/thread_notify.h>
+#include <asm/traps.h>
+
+/* Breakpoint currently in use for each BRP. */
+static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[ARM_MAX_BRP]);
+
+/* Watchpoint currently in use for each WRP. */
+static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
+
+/* Number of BRP/WRP registers on this CPU. */
+static int core_num_brps;
+static int core_num_wrps;
+
+/* Debug architecture version. */
+static u8 debug_arch;
+
+/* Maximum supported watchpoint length. */
+static u8 max_watchpoint_len;
+
+/* Determine number of BRP registers available. */
+static int get_num_brps(void)
+{
+	u32 didr;
+	ARM_DBG_READ(c0, 0, didr);
+	return ((didr >> 24) & 0xf) + 1;
+}
+
+/* Determine number of WRP registers available. */
+static int get_num_wrps(void)
+{
+	/*
+	 * FIXME: When a watchpoint fires, the only way to work out which
+	 * watchpoint it was is by disassembling the faulting instruction
+	 * and working out the address of the memory access.
+	 *
+	 * Furthermore, we can only do this if the watchpoint was precise
+	 * since imprecise watchpoints prevent us from calculating register
+	 * based addresses.
+	 *
+	 * For the time being, we only report 1 watchpoint register so we
+	 * always know which watchpoint fired. In the future we can either
+	 * add a disassembler and address generation emulator, or we can
+	 * insert a check to see if the DFAR is set on watchpoint exception
+	 * entry [the ARM ARM states that the DFAR is UNPREDICTABLE, but
+	 * experience shows that it is set on some implementations].
+	 */
+
+#if 0
+	u32 didr, wrps;
+	ARM_DBG_READ(c0, 0, didr);
+	return ((didr >> 28) & 0xf) + 1;
+#endif
+
+	return 1;
+}
+
+int hw_breakpoint_slots(int type)
+{
+	switch (type) {
+	case TYPE_INST:
+		return core_num_brps;
+	case TYPE_DATA:
+		return core_num_wrps;
+	default:
+		pr_warning("unknown slot type: %d\n", type);
+		return 0;
+	}
+}
+
+/* Determine debug architecture. */
+static u8 get_debug_arch(void)
+{
+	u32 didr;
+
+	/* Do we implement the extended CPUID interface? */
+	if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
+		pr_warning("CPUID feature registers not supported. "
+				"Assuming v6 debug is present.\n");
+		return ARM_DEBUG_ARCH_V6;
+	}
+
+	ARM_DBG_READ(c0, 0, didr);
+	return ((didr >> 16) & 0xf);
+}
+
+u8 arch_get_debug_arch(void)
+{
+	return debug_arch;
+}
+
+#define READ_WB_REG_CASE(OP2, M, VAL)		\
+	case ((OP2 << 4) + M):			\
+		ARM_DBG_READ(c ## M, OP2, VAL); \
+		break
+
+#define WRITE_WB_REG_CASE(OP2, M, VAL)		\
+	case ((OP2 << 4) + M):			\
+		ARM_DBG_WRITE(c ## M, OP2, VAL);\
+		break
+
+#define GEN_READ_WB_REG_CASES(OP2, VAL)		\
+	READ_WB_REG_CASE(OP2, 0, VAL);		\
+	READ_WB_REG_CASE(OP2, 1, VAL);		\
+	READ_WB_REG_CASE(OP2, 2, VAL);		\
+	READ_WB_REG_CASE(OP2, 3, VAL);		\
+	READ_WB_REG_CASE(OP2, 4, VAL);		\
+	READ_WB_REG_CASE(OP2, 5, VAL);		\
+	READ_WB_REG_CASE(OP2, 6, VAL);		\
+	READ_WB_REG_CASE(OP2, 7, VAL);		\
+	READ_WB_REG_CASE(OP2, 8, VAL);		\
+	READ_WB_REG_CASE(OP2, 9, VAL);		\
+	READ_WB_REG_CASE(OP2, 10, VAL);		\
+	READ_WB_REG_CASE(OP2, 11, VAL);		\
+	READ_WB_REG_CASE(OP2, 12, VAL);		\
+	READ_WB_REG_CASE(OP2, 13, VAL);		\
+	READ_WB_REG_CASE(OP2, 14, VAL);		\
+	READ_WB_REG_CASE(OP2, 15, VAL)
+
+#define GEN_WRITE_WB_REG_CASES(OP2, VAL)	\
+	WRITE_WB_REG_CASE(OP2, 0, VAL);		\
+	WRITE_WB_REG_CASE(OP2, 1, VAL);		\
+	WRITE_WB_REG_CASE(OP2, 2, VAL);		\
+	WRITE_WB_REG_CASE(OP2, 3, VAL);		\
+	WRITE_WB_REG_CASE(OP2, 4, VAL);		\
+	WRITE_WB_REG_CASE(OP2, 5, VAL);		\
+	WRITE_WB_REG_CASE(OP2, 6, VAL);		\
+	WRITE_WB_REG_CASE(OP2, 7, VAL);		\
+	WRITE_WB_REG_CASE(OP2, 8, VAL);		\
+	WRITE_WB_REG_CASE(OP2, 9, VAL);		\
+	WRITE_WB_REG_CASE(OP2, 10, VAL);	\
+	WRITE_WB_REG_CASE(OP2, 11, VAL);	\
+	WRITE_WB_REG_CASE(OP2, 12, VAL);	\
+	WRITE_WB_REG_CASE(OP2, 13, VAL);	\
+	WRITE_WB_REG_CASE(OP2, 14, VAL);	\
+	WRITE_WB_REG_CASE(OP2, 15, VAL)
+
+static u32 read_wb_reg(int n)
+{
+	u32 val = 0;
+
+	switch (n) {
+	GEN_READ_WB_REG_CASES(ARM_OP2_BVR, val);
+	GEN_READ_WB_REG_CASES(ARM_OP2_BCR, val);
+	GEN_READ_WB_REG_CASES(ARM_OP2_WVR, val);
+	GEN_READ_WB_REG_CASES(ARM_OP2_WCR, val);
+	default:
+		pr_warning("attempt to read from unknown breakpoint "
+				"register %d\n", n);
+	}
+
+	return val;
+}
+
+static void write_wb_reg(int n, u32 val)
+{
+	switch (n) {
+	GEN_WRITE_WB_REG_CASES(ARM_OP2_BVR, val);
+	GEN_WRITE_WB_REG_CASES(ARM_OP2_BCR, val);
+	GEN_WRITE_WB_REG_CASES(ARM_OP2_WVR, val);
+	GEN_WRITE_WB_REG_CASES(ARM_OP2_WCR, val);
+	default:
+		pr_warning("attempt to write to unknown breakpoint "
+				"register %d\n", n);
+	}
+}
+
+/*
+ * In order to access the breakpoint/watchpoint control registers,
+ * we must be running in debug monitor mode. Unfortunately, we can
+ * be put into halting debug mode at any time by an external debugger
+ * but there is nothing we can do to prevent that.
+ */
+static int enable_monitor_mode(void)
+{
+	u32 dscr;
+	int ret = 0;
+
+	ARM_DBG_READ(c1, 0, dscr);
+
+	/* Ensure that halting mode is disabled. */
+	if (dscr & ARM_DSCR_HDBGEN) {
+		pr_info("halting debug mode enabled. Unable to access "
+				"hardware resources.\n");
+		ret = -EPERM;
+		goto out;
+	}
+
+	/* Write to the corresponding DSCR. */
+	switch (debug_arch) {
+	case ARM_DEBUG_ARCH_V6:
+	case ARM_DEBUG_ARCH_V6_1:
+		ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
+		break;
+	case ARM_DEBUG_ARCH_V7_ECP14:
+		ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN));
+		break;
+	default:
+		ret = -ENODEV;
+		goto out;
+	}
+
+	/* Check that the write made it through. */
+	ARM_DBG_READ(c1, 0, dscr);
+	if (!(dscr & ARM_DSCR_MDBGEN)) {
+		pr_info("failed to enable monitor mode.");
+		ret = -EPERM;
+	}
+
+out:
+	return ret;
+}
+
+/*
+ * Check if 8-bit byte-address select is available.
+ * This clobbers WRP 0.
+ */
+static u8 get_max_wp_len(void)
+{
+	u32 ctrl_reg;
+	struct arch_hw_breakpoint_ctrl ctrl;
+	u8 size = 4;
+
+	if (debug_arch < ARM_DEBUG_ARCH_V7_ECP14)
+		goto out;
+
+	if (enable_monitor_mode())
+		goto out;
+
+	memset(&ctrl, 0, sizeof(ctrl));
+	ctrl.len = ARM_BREAKPOINT_LEN_8;
+	ctrl_reg = encode_ctrl_reg(ctrl);
+
+	write_wb_reg(ARM_BASE_WVR, 0);
+	write_wb_reg(ARM_BASE_WCR, ctrl_reg);
+	if ((read_wb_reg(ARM_BASE_WCR) & ctrl_reg) == ctrl_reg)
+		size = 8;
+
+out:
+	return size;
+}
+
+u8 arch_get_max_wp_len(void)
+{
+	return max_watchpoint_len;
+}
+
+/*
+ * Install a perf counter breakpoint.
+ */
+int arch_install_hw_breakpoint(struct perf_event *bp)
+{
+	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+	struct perf_event **slot, **slots;
+	int i, max_slots, ctrl_base, val_base, ret = 0;
+
+	/* Ensure that we are in monitor mode and halting mode is disabled. */
+	ret = enable_monitor_mode();
+	if (ret)
+		goto out;
+
+	if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
+		/* Breakpoint */
+		ctrl_base = ARM_BASE_BCR;
+		val_base = ARM_BASE_BVR;
+		slots = __get_cpu_var(bp_on_reg);
+		max_slots = core_num_brps;
+	} else {
+		/* Watchpoint */
+		ctrl_base = ARM_BASE_WCR;
+		val_base = ARM_BASE_WVR;
+		slots = __get_cpu_var(wp_on_reg);
+		max_slots = core_num_wrps;
+	}
+
+	for (i = 0; i < max_slots; ++i) {
+		slot = &slots[i];
+
+		if (!*slot) {
+			*slot = bp;
+			break;
+		}
+	}
+
+	if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot")) {
+		ret = -EBUSY;
+		goto out;
+	}
+
+	/* Setup the address register. */
+	write_wb_reg(val_base + i, info->address);
+
+	/* Setup the control register. */
+	write_wb_reg(ctrl_base + i, encode_ctrl_reg(info->ctrl));
+
+out:
+	return ret;
+}
+
+void arch_uninstall_hw_breakpoint(struct perf_event *bp)
+{
+	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+	struct perf_event **slot, **slots;
+	int i, max_slots, base;
+
+	if (info->ctrl.type == ARM_BREAKPOINT_EXECUTE) {
+		/* Breakpoint */
+		base = ARM_BASE_BCR;
+		slots = __get_cpu_var(bp_on_reg);
+		max_slots = core_num_brps;
+	} else {
+		/* Watchpoint */
+		base = ARM_BASE_WCR;
+		slots = __get_cpu_var(wp_on_reg);
+		max_slots = core_num_wrps;
+	}
+
+	/* Remove the breakpoint. */
+	for (i = 0; i < max_slots; ++i) {
+		slot = &slots[i];
+
+		if (*slot == bp) {
+			*slot = NULL;
+			break;
+		}
+	}
+
+	if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot"))
+		return;
+
+	/* Reset the control register. */
+	write_wb_reg(base + i, 0);
+}
+
+static int get_hbp_len(u8 hbp_len)
+{
+	unsigned int len_in_bytes = 0;
+
+	switch (hbp_len) {
+	case ARM_BREAKPOINT_LEN_1:
+		len_in_bytes = 1;
+		break;
+	case ARM_BREAKPOINT_LEN_2:
+		len_in_bytes = 2;
+		break;
+	case ARM_BREAKPOINT_LEN_4:
+		len_in_bytes = 4;
+		break;
+	case ARM_BREAKPOINT_LEN_8:
+		len_in_bytes = 8;
+		break;
+	}
+
+	return len_in_bytes;
+}
+
+/*
+ * Check whether bp virtual address is in kernel space.
+ */
+int arch_check_bp_in_kernelspace(struct perf_event *bp)
+{
+	unsigned int len;
+	unsigned long va;
+	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+	va = info->address;
+	len = get_hbp_len(info->ctrl.len);
+
+	return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
+}
+
+/*
+ * Extract generic type and length encodings from an arch_hw_breakpoint_ctrl.
+ * Hopefully this will disappear when ptrace can bypass the conversion
+ * to generic breakpoint descriptions.
+ */
+int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
+			   int *gen_len, int *gen_type)
+{
+	/* Type */
+	switch (ctrl.type) {
+	case ARM_BREAKPOINT_EXECUTE:
+		*gen_type = HW_BREAKPOINT_X;
+		break;
+	case ARM_BREAKPOINT_LOAD:
+		*gen_type = HW_BREAKPOINT_R;
+		break;
+	case ARM_BREAKPOINT_STORE:
+		*gen_type = HW_BREAKPOINT_W;
+		break;
+	case ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE:
+		*gen_type = HW_BREAKPOINT_RW;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Len */
+	switch (ctrl.len) {
+	case ARM_BREAKPOINT_LEN_1:
+		*gen_len = HW_BREAKPOINT_LEN_1;
+		break;
+	case ARM_BREAKPOINT_LEN_2:
+		*gen_len = HW_BREAKPOINT_LEN_2;
+		break;
+	case ARM_BREAKPOINT_LEN_4:
+		*gen_len = HW_BREAKPOINT_LEN_4;
+		break;
+	case ARM_BREAKPOINT_LEN_8:
+		*gen_len = HW_BREAKPOINT_LEN_8;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/*
+ * Construct an arch_hw_breakpoint from a perf_event.
+ */
+static int arch_build_bp_info(struct perf_event *bp)
+{
+	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+
+	/* Type */
+	switch (bp->attr.bp_type) {
+	case HW_BREAKPOINT_X:
+		info->ctrl.type = ARM_BREAKPOINT_EXECUTE;
+		break;
+	case HW_BREAKPOINT_R:
+		info->ctrl.type = ARM_BREAKPOINT_LOAD;
+		break;
+	case HW_BREAKPOINT_W:
+		info->ctrl.type = ARM_BREAKPOINT_STORE;
+		break;
+	case HW_BREAKPOINT_RW:
+		info->ctrl.type = ARM_BREAKPOINT_LOAD | ARM_BREAKPOINT_STORE;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Len */
+	switch (bp->attr.bp_len) {
+	case HW_BREAKPOINT_LEN_1:
+		info->ctrl.len = ARM_BREAKPOINT_LEN_1;
+		break;
+	case HW_BREAKPOINT_LEN_2:
+		info->ctrl.len = ARM_BREAKPOINT_LEN_2;
+		break;
+	case HW_BREAKPOINT_LEN_4:
+		info->ctrl.len = ARM_BREAKPOINT_LEN_4;
+		break;
+	case HW_BREAKPOINT_LEN_8:
+		info->ctrl.len = ARM_BREAKPOINT_LEN_8;
+		if ((info->ctrl.type != ARM_BREAKPOINT_EXECUTE)
+			&& max_watchpoint_len == 8)
+			break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Privilege */
+	info->ctrl.privilege = ARM_BREAKPOINT_USER | ARM_BREAKPOINT_PRIV;
+
+	/* Address */
+	info->address = bp->attr.bp_addr;
+
+	/* Enabled? */
+	info->ctrl.enabled = ~bp->attr.disabled;
+
+	return 0;
+}
+
+/*
+ * Validate the arch-specific HW Breakpoint register settings.
+ */
+int arch_validate_hwbkpt_settings(struct perf_event *bp)
+{
+	struct arch_hw_breakpoint *info = counter_arch_bp(bp);
+	int ret = 0;
+	u32 alignment_mask = 0x3;
+
+	/* Build the arch_hw_breakpoint. */
+	ret = arch_build_bp_info(bp);
+	if (ret)
+		goto out;
+
+	/* Check address alignment. */
+	if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
+		alignment_mask = 0x7;
+	if (info->address & alignment_mask) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/*
+	 * Currently we rely on an overflow handler to take
+	 * care of single-stepping the breakpoint when it fires.
+	 */
+	if (WARN_ONCE(!bp->overflow_handler,
+			"overflow handler required but none found")) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+out:
+	return ret;
+}
+
+static void watchpoint_handler(unsigned long unpredictable,
+				struct pt_regs *regs)
+{
+	int i;
+	struct perf_event **slots = __get_cpu_var(wp_on_reg);
+	struct arch_hw_breakpoint *info;
+
+	for (i = 0; i < core_num_wrps; ++i) {
+		rcu_read_lock();
+
+		if (slots[i] == NULL) {
+			rcu_read_unlock();
+			break;
+		}
+
+		/* TODO: Check if this watchpoint actually fired. */
+
+		/*
+		 * The DFAR is unpredictable. Since we only allow a
+		 * single watchpoint, we can set the trigger to the lowest
+		 * possible faulting address.
+		 */
+		info = counter_arch_bp(slots[i]);
+		info->trigger = info->address;
+		perf_bp_event(slots[i], regs);
+
+		rcu_read_unlock();
+	}
+}
+
+static void breakpoint_handler(unsigned long unpredictable,
+				struct pt_regs *regs)
+{
+	int i;
+	u32 ctrl_reg, val, addr;
+	struct perf_event **slots = __get_cpu_var(bp_on_reg);
+	struct arch_hw_breakpoint *info;
+	struct arch_hw_breakpoint_ctrl ctrl;
+
+	/* The exception entry code places the amended lr in the PC. */
+	addr = regs->ARM_pc;
+
+	for (i = 0; i < core_num_brps; ++i) {
+		rcu_read_lock();
+
+		if (slots[i] == NULL) {
+			rcu_read_unlock();
+			break;
+		}
+
+		/* Check if the breakpoint value matches. */
+		val = read_wb_reg(ARM_BASE_BVR + i);
+		if (val != (addr & ~0x3)) {
+			rcu_read_unlock();
+			continue;
+		}
+
+		/* Possible match, check the byte address select to confirm. */
+		ctrl_reg = read_wb_reg(ARM_BASE_BCR + i);
+		decode_ctrl_reg(ctrl_reg, &ctrl);
+
+		if ((1 << (addr & 0x3)) & ctrl.len) {
+			info = counter_arch_bp(slots[i]);
+			info->trigger = addr;
+			perf_bp_event(slots[i], regs);
+		}
+
+		rcu_read_unlock();
+	}
+}
+
+/*
+ * Called from either the Data Abort Handler [watchpoint] or the
+ * Prefetch Abort Handler [breakpoint].
+ */
+static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
+					struct pt_regs *regs)
+{
+	int ret = 1; /* Unhandled fault. */
+	u32 dscr;
+
+	/* We only handle watchpoints and hardware breakpoints. */
+	ARM_DBG_READ(c1, 0, dscr);
+
+	/* Perform perf callbacks. */
+	switch (ARM_DSCR_MOE(dscr)) {
+	case ARM_ENTRY_BREAKPOINT:
+		breakpoint_handler(addr, regs);
+		break;
+	case ARM_ENTRY_ASYNC_WATCHPOINT:
+	case ARM_ENTRY_SYNC_WATCHPOINT:
+		watchpoint_handler(addr, regs);
+		break;
+	default:
+		goto out;
+	}
+
+	ret = 0;
+out:
+	return ret;
+}
+
+/*
+ * One-time initialisation.
+ */
+static int __init arch_hw_breakpoint_init(void)
+{
+	int ret = 0, i;
+	u32 dscr;
+
+	debug_arch = get_debug_arch();
+
+	if (debug_arch > ARM_DEBUG_ARCH_V7_ECP14) {
+		pr_info("debug architecture 0x%x unsupported.\n", debug_arch);
+		ret = -ENODEV;
+		goto out;
+	}
+
+	/* Determine how many BRPs/WRPs are available. */
+	core_num_brps = get_num_brps();
+	core_num_wrps = get_num_wrps();
+
+	pr_info("found %d breakpoint and %d watchpoint registers.\n",
+			core_num_brps, core_num_wrps);
+
+	ARM_DBG_READ(c1, 0, dscr);
+	if (dscr & ARM_DSCR_HDBGEN) {
+		pr_warning("halting debug mode enabled. Assuming maximum "
+				"watchpoint size of 4 bytes.");
+	} else {
+		/* Work out the maximum supported watchpoint length. */
+		max_watchpoint_len = get_max_wp_len();
+		pr_info("maximum watchpoint size is %u bytes.\n",
+				max_watchpoint_len);
+
+		/*
+		 * Reset the breakpoint resources. We assume that a halting
+		 * debugger will leave the world in a nice state for us.
+		 */
+		for (i = 0; i < core_num_brps; ++i) {
+			write_wb_reg(ARM_BASE_BCR + i, 0UL);
+			write_wb_reg(ARM_BASE_BVR + i, 0UL);
+		}
+
+		for (i = 0; i < core_num_wrps; ++i) {
+			write_wb_reg(ARM_BASE_WCR + i, 0UL);
+			write_wb_reg(ARM_BASE_WVR + i, 0UL);
+		}
+	}
+
+	/* Register thread flush notifier. */
+	thread_register_notifier(&hw_breakpoint_thread_notifier_block);
+
+	/* Register debug fault handler. */
+	hook_fault_code(2, hw_breakpoint_pending, SIGTRAP, "debug exception");
+	hook_ifault_code(2, hw_breakpoint_pending, SIGTRAP, "debug exception");
+
+out:
+	return ret;
+}
+arch_initcall(arch_hw_breakpoint_init);
+
+void hw_breakpoint_pmu_read(struct perf_event *bp)
+{
+}
+
+/*
+ * Dummy function to register with die_notifier.
+ */
+int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
+					unsigned long val, void *data)
+{
+	return NOTIFY_DONE;
+}
-- 
1.6.3.3



From saeed.bishara at gmail.com  Thu Jun 10 11:07:20 2010
From: saeed.bishara at gmail.com (saeed bishara)
Date: Thu, 10 Jun 2010 18:07:20 +0300
Subject: [PATCH 4/4] arch/arm/mach-kirkwood: add support for 2nd TWSI 
	controller on 88f6282.
In-Reply-To: <20100610135951.14097.48348.stgit@localhost.localdomain>
References: <20100610135936.14097.22635.stgit@localhost.localdomain>
	<20100610135951.14097.48348.stgit@localhost.localdomain>
Message-ID: <AANLkTim9rZEXhpiY17Co3mvM1YOgtqlmRhgU3ofHJMgV@mail.gmail.com>

On Thu, Jun 10, 2010 at 4:59 PM, Benjamin Zores
<benjamin.zores at alcatel-lucent.com> wrote:
> Signed-off-by: Benjamin Zores <benjamin.zores at alcatel-lucent.com>
> ---
> ?arch/arm/mach-kirkwood/common.c ? ? ? ? ? ? ? ?| ? 46 +++++++++++++++++++-----
> ?arch/arm/mach-kirkwood/include/mach/irqs.h ? ? | ? ?3 +-
> ?arch/arm/mach-kirkwood/include/mach/kirkwood.h | ? ?3 +-
> ?3 files changed, 41 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> index 473a1d0..93b7762 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -458,23 +458,45 @@ static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
> ? ? ? ?.timeout ? ? ? ?= 1000, /* Default timeout of 1 second */
> ?};
>
> -static struct resource kirkwood_i2c_resources[] = {
> +static struct resource kirkwood_i2c_0_resources[] = {
> ? ? ? ?{
> - ? ? ? ? ? ? ? .start ?= I2C_PHYS_BASE,
> - ? ? ? ? ? ? ? .end ? ?= I2C_PHYS_BASE + 0x1f,
> + ? ? ? ? ? ? ? .start ?= I2C_0_PHYS_BASE,
> + ? ? ? ? ? ? ? .end ? ?= I2C_0_PHYS_BASE + 0x1f,
> ? ? ? ? ? ? ? ?.flags ?= IORESOURCE_MEM,
> ? ? ? ?}, {
> - ? ? ? ? ? ? ? .start ?= IRQ_KIRKWOOD_TWSI,
> - ? ? ? ? ? ? ? .end ? ?= IRQ_KIRKWOOD_TWSI,
> + ? ? ? ? ? ? ? .start ?= IRQ_KIRKWOOD_TWSI0,
> + ? ? ? ? ? ? ? .end ? ?= IRQ_KIRKWOOD_TWSI0,
> ? ? ? ? ? ? ? ?.flags ?= IORESOURCE_IRQ,
> ? ? ? ?},
> ?};
>
> -static struct platform_device kirkwood_i2c = {
> +static struct resource kirkwood_i2c_1_resources[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .start ?= I2C_1_PHYS_BASE,
> + ? ? ? ? ? ? ? .end ? ?= I2C_1_PHYS_BASE + 0x1f,
> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> + ? ? ? }, {
> + ? ? ? ? ? ? ? .start ?= IRQ_KIRKWOOD_TWSI1,
> + ? ? ? ? ? ? ? .end ? ?= IRQ_KIRKWOOD_TWSI1,
> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> + ? ? ? },
> +};
> +
> +static struct platform_device kirkwood_i2c_0 = {
> ? ? ? ?.name ? ? ? ? ? = MV64XXX_I2C_CTLR_NAME,
> ? ? ? ?.id ? ? ? ? ? ? = 0,
> - ? ? ? .num_resources ?= ARRAY_SIZE(kirkwood_i2c_resources),
> - ? ? ? .resource ? ? ? = kirkwood_i2c_resources,
> + ? ? ? .num_resources ?= ARRAY_SIZE(kirkwood_i2c_0_resources),
> + ? ? ? .resource ? ? ? = kirkwood_i2c_0_resources,
> + ? ? ? .dev ? ? ? ? ? ?= {
> + ? ? ? ? ? ? ? .platform_data ?= &kirkwood_i2c_pdata,
> + ? ? ? },
> +};
> +
> +static struct platform_device kirkwood_i2c_1 = {
> + ? ? ? .name ? ? ? ? ? = MV64XXX_I2C_CTLR_NAME,
> + ? ? ? .id ? ? ? ? ? ? = 0,
> + ? ? ? .num_resources ?= ARRAY_SIZE(kirkwood_i2c_1_resources),
> + ? ? ? .resource ? ? ? = kirkwood_i2c_1_resources,
> ? ? ? ?.dev ? ? ? ? ? ?= {
> ? ? ? ? ? ? ? ?.platform_data ?= &kirkwood_i2c_pdata,
> ? ? ? ?},
> @@ -482,7 +504,13 @@ static struct platform_device kirkwood_i2c = {
>
> ?void __init kirkwood_i2c_init(void)
> ?{
> - ? ? ? platform_device_register(&kirkwood_i2c);
> + ? ? ? u32 dev, rev;
> +
> + ? ? ? kirkwood_pcie_id(&dev, &rev);
> +
> + ? ? ? platform_device_register(&kirkwood_i2c_0);
> + ? ? ? if (dev == MV88F6282_DEV_ID && (rev == MV88F6282_REV_A0))
> + ? ? ? ? platform_device_register(&kirkwood_i2c_1);
the fact that the 6282 has 2 i2c controller doesn't mean that every
board will use both of them, I suggest to add port number to
kirkwood_i2c_init, and 6282 that wants to enable i2c 1 will call
kirkwood_i2c_init(1)
> ?}
>
>
> diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
> index 9da2eb5..d82ecf0 100644
> --- a/arch/arm/mach-kirkwood/include/mach/irqs.h
> +++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
> @@ -33,13 +33,14 @@
> ?#define IRQ_KIRKWOOD_I2S ? ? ? 24
> ?#define IRQ_KIRKWOOD_TS_0 ? ? ?26
> ?#define IRQ_KIRKWOOD_SDIO ? ? ?28
> -#define IRQ_KIRKWOOD_TWSI ? ? ?29
> +#define IRQ_KIRKWOOD_TWSI0 ? ? 29
> ?#define IRQ_KIRKWOOD_AVB ? ? ? 30
> ?#define IRQ_KIRKWOOD_TDMI ? ? ?31
>
> ?/*
> ?* High Interrupt Controller
> ?*/
> +#define IRQ_KIRKWOOD_TWSI1 ? ? 32
> ?#define IRQ_KIRKWOOD_UART_0 ? ?33
> ?#define IRQ_KIRKWOOD_UART_1 ? ?34
> ?#define IRQ_KIRKWOOD_GPIO_LOW_0_7 ? ? ?35
> diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
> index 7f0b50a..b2f2f5d 100644
> --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
> +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
> @@ -68,7 +68,8 @@
> ?#define ?DEVICE_ID ? ? ? ? ? ? (DEV_BUS_VIRT_BASE | 0x0034)
> ?#define ?RTC_PHYS_BASE ? ? ? ? (DEV_BUS_PHYS_BASE | 0x0300)
> ?#define ?SPI_PHYS_BASE ? ? ? ? (DEV_BUS_PHYS_BASE | 0x0600)
> -#define ?I2C_PHYS_BASE ? ? ? ? (DEV_BUS_PHYS_BASE | 0x1000)
> +#define ?I2C_0_PHYS_BASE ? ? ? (DEV_BUS_PHYS_BASE | 0x1000)
> +#define ?I2C_1_PHYS_BASE ? ? ? (DEV_BUS_PHYS_BASE | 0x1100)
> ?#define ?UART0_PHYS_BASE ? ? ? (DEV_BUS_PHYS_BASE | 0x2000)
> ?#define ?UART0_VIRT_BASE ? ? ? (DEV_BUS_VIRT_BASE | 0x2000)
> ?#define ?UART1_PHYS_BASE ? ? ? (DEV_BUS_PHYS_BASE | 0x2100)
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From saeed.bishara at gmail.com  Thu Jun 10 11:29:15 2010
From: saeed.bishara at gmail.com (saeed bishara)
Date: Thu, 10 Jun 2010 18:29:15 +0300
Subject: [PATCH 3/4] arch/arm/mach-kirkwood: add support for 2nd PCIe port
	on 88f6282.
In-Reply-To: <20100610135946.14097.39894.stgit@localhost.localdomain>
References: <20100610135936.14097.22635.stgit@localhost.localdomain>
	<20100610135946.14097.39894.stgit@localhost.localdomain>
Message-ID: <AANLkTikRdFDxwQskaCz6ScATh8WHUFN4XwLIyqJ_1U1k@mail.gmail.com>

On Thu, Jun 10, 2010 at 4:59 PM, Benjamin Zores
<benjamin.zores at alcatel-lucent.com> wrote:
> Signed-off-by: Benjamin Zores <benjamin.zores at alcatel-lucent.com>
> ---
> ?arch/arm/mach-kirkwood/addr-map.c ? ? ? ? ? ? ? ? | ? 21 ++
> ?arch/arm/mach-kirkwood/common.c ? ? ? ? ? ? ? ? ? | ? 28 +++
> ?arch/arm/mach-kirkwood/common.h ? ? ? ? ? ? ? ? ? | ? ?5 -
> ?arch/arm/mach-kirkwood/db88f6281-bp-setup.c ? ? ? | ? ?2
> ?arch/arm/mach-kirkwood/include/mach/bridge-regs.h | ? ?3
> ?arch/arm/mach-kirkwood/include/mach/irqs.h ? ? ? ?| ? ?1
> ?arch/arm/mach-kirkwood/include/mach/kirkwood.h ? ?| ? 12 +
> ?arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c ? ?| ? ?2
> ?arch/arm/mach-kirkwood/openrd-setup.c ? ? ? ? ? ? | ? ?2
> ?arch/arm/mach-kirkwood/pcie.c ? ? ? ? ? ? ? ? ? ? | ?202 ++++++++++++++++-----
> ?arch/arm/mach-kirkwood/rd88f6192-nas-setup.c ? ? ?| ? ?2
> ?arch/arm/mach-kirkwood/rd88f6281-setup.c ? ? ? ? ?| ? ?2
> ?arch/arm/mach-kirkwood/ts219-setup.c ? ? ? ? ? ? ?| ? ?2
> ?arch/arm/mach-kirkwood/ts41x-setup.c ? ? ? ? ? ? ?| ? ?2
> ?14 files changed, 223 insertions(+), 63 deletions(-)
>
> diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
> index 2e69168..aa6bf38 100644
> --- a/arch/arm/mach-kirkwood/addr-map.c
> +++ b/arch/arm/mach-kirkwood/addr-map.c
> @@ -31,6 +31,8 @@
> ?#define ATTR_DEV_CS0 ? ? ? ? ? 0x3e
> ?#define ATTR_PCIE_IO ? ? ? ? ? 0xe0
> ?#define ATTR_PCIE_MEM ? ? ? ? ?0xe8
> +#define ATTR_PCIE1_IO ? ? ? ? ?0xd0
> +#define ATTR_PCIE1_MEM ? ? ? ? 0xd8
> ?#define ATTR_SRAM ? ? ? ? ? ? ?0x01
>
> ?/*
> @@ -84,6 +86,8 @@ void __init kirkwood_setup_cpu_mbus(void)
> ? ? ? ?void __iomem *addr;
> ? ? ? ?int i;
> ? ? ? ?int cs;
> + ? ? ? int id = 0;
> + ? ? ? u32 dev, rev;
>
> ? ? ? ?/*
> ? ? ? ? * First, disable and clear windows.
> @@ -102,21 +106,30 @@ void __init kirkwood_setup_cpu_mbus(void)
> ? ? ? ?/*
> ? ? ? ? * Setup windows for PCIe IO+MEM space.
> ? ? ? ? */
> - ? ? ? setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
> + ? ? ? setup_cpu_win(id++, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
> ? ? ? ? ? ? ? ? ? ? ?TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
> - ? ? ? setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
> + ? ? ? setup_cpu_win(id++, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
> ? ? ? ? ? ? ? ? ? ? ?TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
>
> + ? ? ? kirkwood_pcie_id(&dev, &rev);
> +
> + ? ? ? if (dev == MV88F6282_DEV_ID && (rev == MV88F6282_REV_A0)) {
> + ? ? ? ? setup_cpu_win(id++, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
> + ? ? ? ? ? ? ? ? ? ? ? TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
> + ? ? ? ? setup_cpu_win(id++, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
> + ? ? ? ? ? ? ? ? ? ? ? TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
> + ? ? ? }
> +
> ? ? ? ?/*
> ? ? ? ? * Setup window for NAND controller.
> ? ? ? ? */
> - ? ? ? setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
> + ? ? ? setup_cpu_win(id++, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
> ? ? ? ? ? ? ? ? ? ? ?TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
>
> ? ? ? ?/*
> ? ? ? ? * Setup window for SRAM.
> ? ? ? ? */
> - ? ? ? setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
> + ? ? ? setup_cpu_win(id++, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
> ? ? ? ? ? ? ? ? ? ? ?TARGET_SRAM, ATTR_SRAM, -1);
>
> ? ? ? ?/*
> diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
> index 94f629d..473a1d0 100644
> --- a/arch/arm/mach-kirkwood/common.c
> +++ b/arch/arm/mach-kirkwood/common.c
> @@ -44,6 +44,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
> ? ? ? ? ? ? ? ?.length ? ? ? ? = KIRKWOOD_PCIE_IO_SIZE,
> ? ? ? ? ? ? ? ?.type ? ? ? ? ? = MT_DEVICE,
> ? ? ? ?}, {
> + ? ? ? ? ? ? ? .virtual ? ? ? ?= KIRKWOOD_PCIE1_IO_VIRT_BASE,
> + ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
> + ? ? ? ? ? ? ? .length ? ? ? ? = KIRKWOOD_PCIE1_IO_SIZE,
> + ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
> + ? ? ? }, {
> ? ? ? ? ? ? ? ?.virtual ? ? ? ?= KIRKWOOD_REGS_VIRT_BASE,
> ? ? ? ? ? ? ? ?.pfn ? ? ? ? ? ?= __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
> ? ? ? ? ? ? ? ?.length ? ? ? ? = KIRKWOOD_REGS_SIZE,
> @@ -957,12 +962,20 @@ void __init kirkwood_init(void)
> ?static int __init kirkwood_clock_gate(void)
> ?{
> ? ? ? ?unsigned int curr = readl(CLOCK_GATING_CTRL);
> + ? ? ? u32 dev, rev;
> + ? ? ? int flags;
>
> ? ? ? ?printk(KERN_DEBUG "Gating clock of unused units\n");
> ? ? ? ?printk(KERN_DEBUG "before: 0x%08x\n", curr);
>
> + ? ? ? kirkwood_pcie_id(&dev, &rev);
> +
> ? ? ? ?/* Make sure those units are accessible */
> - ? ? ? writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);
> + ? ? ? flags = curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0;
> +
> + ? ? ? if (dev == MV88F6282_DEV_ID && (rev == MV88F6282_REV_A0))
> + ? ? ? ? ? ? ? flags |= CGC_PEX1;
> + ? ? ? writel(flags, CLOCK_GATING_CTRL);
>
> ? ? ? ?/* For SATA: first shutdown the phy */
> ? ? ? ?if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
> @@ -978,7 +991,7 @@ static int __init kirkwood_clock_gate(void)
> ? ? ? ? ? ? ? ?writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
> ? ? ? ?}
>
> - ? ? ? /* For PCIe: first shutdown the phy */
> + ? ? ? /* For PCIe #0: first shutdown the phy */
> ? ? ? ?if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
> ? ? ? ? ? ? ? ?writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
> ? ? ? ? ? ? ? ?while (1)
> @@ -987,6 +1000,17 @@ static int __init kirkwood_clock_gate(void)
> ? ? ? ? ? ? ? ?writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
> ? ? ? ?}
>
> + ? ? ? /* For PCIe #1: first shutdown the phy */
> + ? ? ? if (dev == MV88F6282_DEV_ID && (rev == MV88F6282_REV_A0)) {
> + ? ? ? ? ? ? ? if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
> + ? ? ? ? ? ? ? ? ? ? ? writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
> + ? ? ? ? ? ? ? ? ? ? ? while (1)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? if (readl(PCIE1_STATUS) & 0x1)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? ? ? ? ? writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> ? ? ? ?/* Now gate clock the required units */
> ? ? ? ?writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
> ? ? ? ?printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
> diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
> index 05e8a8a..5b2c1c1 100644
> --- a/arch/arm/mach-kirkwood/common.h
> +++ b/arch/arm/mach-kirkwood/common.h
> @@ -18,6 +18,9 @@ struct mvsdio_platform_data;
> ?struct mtd_partition;
> ?struct mtd_info;
>
> +#define KW_PCIE0 ? ? ? (1 << 0)
> +#define KW_PCIE1 ? ? ? (1 << 1)
> +
> ?/*
> ?* Basic Kirkwood init functions used early by machine-setup.
> ?*/
> @@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);
> ?void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
> ?void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
> ?void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
> -void kirkwood_pcie_init(void);
> +void kirkwood_pcie_init(unsigned int portmask);
> ?void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
> ?void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
> ?void kirkwood_spi_init(void);
> diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
> index 39bdf4b..7550c4e 100644
> --- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
> +++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
> @@ -75,7 +75,7 @@ static void __init db88f6281_init(void)
> ?static int __init db88f6281_pci_init(void)
> ?{
> ? ? ? ?if (machine_is_db88f6281_bp())
> - ? ? ? ? ? ? ? kirkwood_pcie_init();
> + ? ? ? ? ? ? ? kirkwood_pcie_init(KW_PCIE0);
>
> ? ? ? ?return 0;
> ?}
> diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
> index 418f501..aff0e13 100644
> --- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
> +++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
> @@ -59,8 +59,9 @@
> ?#define CGC_SATA1 ? ? ? ? ? ? ?(1 << 15)
> ?#define CGC_XOR1 ? ? ? ? ? ? ? (1 << 16)
> ?#define CGC_CRYPTO ? ? ? ? ? ? (1 << 17)
> +#define CGC_PEX1 ? ? ? ? ? ? ? (1 << 18)
> ?#define CGC_GE1 ? ? ? ? ? ? ? ? ? ? ? ?(1 << 19)
> ?#define CGC_TDM ? ? ? ? ? ? ? ? ? ? ? ?(1 << 20)
> -#define CGC_RESERVED ? ? ? ? ? ((1 << 18) | (0x6 << 21))
> +#define CGC_RESERVED ? ? ? ? ? (0x6 << 21)
>
> ?#endif
> diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
> index f00a0a4..9da2eb5 100644
> --- a/arch/arm/mach-kirkwood/include/mach/irqs.h
> +++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
> @@ -23,6 +23,7 @@
> ?#define IRQ_KIRKWOOD_XOR_10 ? ?7
> ?#define IRQ_KIRKWOOD_XOR_11 ? ?8
> ?#define IRQ_KIRKWOOD_PCIE ? ? ?9
> +#define IRQ_KIRKWOOD_PCIE1 ? ? 10
> ?#define IRQ_KIRKWOOD_GE00_SUM ?11
> ?#define IRQ_KIRKWOOD_GE01_SUM ?15
> ?#define IRQ_KIRKWOOD_USB ? ? ? 19
> diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
> index a571860..7f0b50a 100644
> --- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
> +++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
> @@ -38,6 +38,11 @@
> ?#define KIRKWOOD_PCIE_IO_BUS_BASE ? ? ?0x00000000
> ?#define KIRKWOOD_PCIE_IO_SIZE ? ? ? ? ?SZ_1M
>
> +#define KIRKWOOD_PCIE1_IO_PHYS_BASE ? ?0xf5000000
> +#define KIRKWOOD_PCIE1_IO_VIRT_BASE ? ?0xfed00000
> +#define KIRKWOOD_PCIE1_IO_BUS_BASE ? ? 0x00000000
> +#define KIRKWOOD_PCIE1_IO_SIZE ? ? ? ? SZ_1M
> +
you didn't updated the comment the describes the address map.
also, I suggest you to take this part from the patch I sent, in that
patch I made sure to make the pcie1 IO physical and virtual address
consecutive to pcie0, I think without this the IO access to pcie1 will
not work. please see the __io() macro at
mach-kirkwood/include/mach/io.h
> ?#define KIRKWOOD_REGS_PHYS_BASE ? ? ? ? ? ? ? ?0xf1000000
> ?#define KIRKWOOD_REGS_VIRT_BASE ? ? ? ? ? ? ? ?0xfee00000
> ?#define KIRKWOOD_REGS_SIZE ? ? ? ? ? ? SZ_1M
> @@ -46,6 +51,10 @@
> ?#define KIRKWOOD_PCIE_MEM_BUS_BASE ? ? 0xe0000000
> ?#define KIRKWOOD_PCIE_MEM_SIZE ? ? ? ? SZ_128M
>
> +#define KIRKWOOD_PCIE1_MEM_PHYS_BASE ? 0xd8000000
> +#define KIRKWOOD_PCIE1_MEM_BUS_BASE ? ?0xd8000000
> +#define KIRKWOOD_PCIE1_MEM_SIZE ? ? ? ? ? ? ? ?SZ_128M
> +
> ?/*
> ?* Register Map
> ?*/
> @@ -72,6 +81,9 @@
> ?#define PCIE_VIRT_BASE ? ? ? ? (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
> ?#define PCIE_LINK_CTRL ? ? ? ? (PCIE_VIRT_BASE | 0x70)
> ?#define PCIE_STATUS ? ? ? ? ? ?(PCIE_VIRT_BASE | 0x1a04)
> +#define PCIE1_VIRT_BASE ? ? ? ? ? ? ? ?(KIRKWOOD_REGS_VIRT_BASE | 0x44000)
> +#define PCIE1_LINK_CTRL ? ? ? ? ? ? ? ?(PCIE1_VIRT_BASE | 0x70)
> +#define PCIE1_STATUS ? ? ? ? ? (PCIE1_VIRT_BASE | 0x1a04)
>
> ?#define USB_PHYS_BASE ? ? ? ? ?(KIRKWOOD_REGS_PHYS_BASE | 0x50000)
>
> diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
> index 5e6f711..c6b92b4 100644
> --- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
> +++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
> @@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
> ?static int __init mv88f6281gtw_ge_pci_init(void)
> ?{
> ? ? ? ?if (machine_is_mv88f6281gtw_ge())
> - ? ? ? ? ? ? ? kirkwood_pcie_init();
> + ? ? ? ? ? ? ? kirkwood_pcie_init(KW_PCIE0);
>
> ? ? ? ?return 0;
> ?}
> diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
> index ad3f1ec..2400207 100644
> --- a/arch/arm/mach-kirkwood/openrd-setup.c
> +++ b/arch/arm/mach-kirkwood/openrd-setup.c
> @@ -85,7 +85,7 @@ static void __init openrd_init(void)
> ?static int __init openrd_pci_init(void)
> ?{
> ? ? ? ?if (machine_is_openrd_base() || machine_is_openrd_client())
> - ? ? ? ? ? ? ? kirkwood_pcie_init();
> + ? ? ? ? ? ? ? kirkwood_pcie_init(KW_PCIE0);
>
> ? ? ? ?return 0;
> ?}
> diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
> index dee1eff..dd1dc29 100644
> --- a/arch/arm/mach-kirkwood/pcie.c
> +++ b/arch/arm/mach-kirkwood/pcie.c
> @@ -18,29 +18,51 @@
> ?#include <mach/bridge-regs.h>
> ?#include "common.h"
>
> +void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
> +{
> + ? ? ? *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
> + ? ? ? *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
> +}
>
> -#define PCIE_BASE ? ? ?((void __iomem *)PCIE_VIRT_BASE)
> +struct pcie_port {
> + ? ? ? int ? ? ? ? ? ? ? ? ? ? index;
> + ? ? ? u8 ? ? ? ? ? ? ? ? ? ? ?root_bus_nr;
> + ? ? ? void __iomem ? ? ? ? ? ?*base;
> + ? ? ? spinlock_t ? ? ? ? ? ? ?conf_lock;
> + ? ? ? int ? ? ? ? ? ? ? ? ? ? irq;
> + ? ? ? struct resource ? ? ? ? res[2];
> +};
>
> -void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
> +static struct pcie_port pcie_port[2];
> +static int num_pcie_ports;
> +
> +static inline struct pcie_port *bus_to_port(int bus)
> ?{
> - ? ? ? *dev = orion_pcie_dev_id(PCIE_BASE);
> - ? ? ? *rev = orion_pcie_rev(PCIE_BASE);
> + ? ? ? int i;
> +
> + ? ? ? for (i = num_pcie_ports - 1; i >= 0; i--) {
> + ? ? ? ? ? ? ? int rbus = pcie_port[i].root_bus_nr;
you're still using the pcie_port global structure. the patch I sent
removed it,  can you take this part (changes to kirkwood/pcie.c) from
my patch?
> + ? ? ? ? ? ? ? if (rbus != -1 && rbus <= bus)
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? }
> +
> + ? ? ? return i >= 0 ? pcie_port + i : NULL;
> ?}
>
> -static int pcie_valid_config(int bus, int dev)
> +static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
> ?{
> ? ? ? ?/*
> ? ? ? ? * Don't go out when trying to access --
> ? ? ? ? * 1. nonexisting device on local bus
> ? ? ? ? * 2. where there's no device connected (no link)
> ? ? ? ? */
> - ? ? ? if (bus == 0 && dev == 0)
> + ? ? ? if (bus == pp->root_bus_nr && dev == 0)
> ? ? ? ? ? ? ? ?return 1;
>
> - ? ? ? if (!orion_pcie_link_up(PCIE_BASE))
> + ? ? ? if (!orion_pcie_link_up(pp->base))
> ? ? ? ? ? ? ? ?return 0;
>
> - ? ? ? if (bus == 0 && dev != 1)
> + ? ? ? if (bus == pp->root_bus_nr && dev != 1)
> ? ? ? ? ? ? ? ?return 0;
>
> ? ? ? ?return 1;
> @@ -52,22 +74,22 @@ static int pcie_valid_config(int bus, int dev)
> ?* and then reading the PCIE_CONF_DATA register. Need to make sure these
> ?* transactions are atomic.
> ?*/
> -static DEFINE_SPINLOCK(kirkwood_pcie_lock);
>
> ?static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
> ? ? ? ? ? ? ? ? ? ? ? ?int size, u32 *val)
> ?{
> + ? ? ? struct pcie_port *pp = bus_to_port(bus->number);
> ? ? ? ?unsigned long flags;
> ? ? ? ?int ret;
>
> - ? ? ? if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
> + ? ? ? if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
> ? ? ? ? ? ? ? ?*val = 0xffffffff;
> ? ? ? ? ? ? ? ?return PCIBIOS_DEVICE_NOT_FOUND;
> ? ? ? ?}
>
> - ? ? ? spin_lock_irqsave(&kirkwood_pcie_lock, flags);
> - ? ? ? ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
> - ? ? ? spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
> + ? ? ? spin_lock_irqsave(&pp->conf_lock, flags);
> + ? ? ? ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
> + ? ? ? spin_unlock_irqrestore(&pp->conf_lock, flags);
>
> ? ? ? ?return ret;
> ?}
> @@ -75,15 +97,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
> ?static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
> ? ? ? ? ? ? ? ? ? ? ? ?int where, int size, u32 val)
> ?{
> + ? ? ? struct pcie_port *pp = bus_to_port(bus->number);
> ? ? ? ?unsigned long flags;
> ? ? ? ?int ret;
>
> - ? ? ? if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
> + ? ? ? if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
> ? ? ? ? ? ? ? ?return PCIBIOS_DEVICE_NOT_FOUND;
>
> - ? ? ? spin_lock_irqsave(&kirkwood_pcie_lock, flags);
> - ? ? ? ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
> - ? ? ? spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
> + ? ? ? spin_lock_irqsave(&pp->conf_lock, flags);
> + ? ? ? ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
> + ? ? ? spin_unlock_irqrestore(&pp->conf_lock, flags);
>
> ? ? ? ?return ret;
> ?}
> @@ -93,50 +116,106 @@ static struct pci_ops pcie_ops = {
> ? ? ? ?.write = pcie_wr_conf,
> ?};
>
> -
> -static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
> +static int __init pcie0_ioresouces_setup(struct pcie_port *pp)
> ?{
> - ? ? ? struct resource *res;
> - ? ? ? extern unsigned int kirkwood_clk_ctrl;
> -
> ? ? ? ?/*
> - ? ? ? ?* Generic PCIe unit setup.
> + ? ? ? ?* IORESOURCE_IO
> ? ? ? ? */
> - ? ? ? orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
> + ? ? ? pp->res[0].name ?= "PCIe 0 I/O Space";
> + ? ? ? pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
> + ? ? ? pp->res[0].end ? = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
> + ? ? ? pp->res[0].flags = IORESOURCE_IO;
> + ? ? ? if (request_resource(&ioport_resource, &pp->res[0]))
> + ? ? ? ? ? ? ? panic("Request PCIe 0 IO resource failed\n");
>
> ? ? ? ?/*
> - ? ? ? ?* Request resources.
> + ? ? ? ?* IORESOURCE_MEM
> ? ? ? ? */
> - ? ? ? res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
> - ? ? ? if (!res)
> - ? ? ? ? ? ? ? panic("pcie_setup unable to alloc resources");
> + ? ? ? pp->res[1].name ?= "PCIe 0 MEM";
> + ? ? ? pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
> + ? ? ? pp->res[1].end ? = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
> + ? ? ? pp->res[1].flags = IORESOURCE_MEM;
> + ? ? ? if (request_resource(&iomem_resource, &pp->res[1]))
> + ? ? ? ? ? ? ? panic("Request PCIe 0 Memory resource failed\n");
> +
> + ? ? ? return 1;
> +}
>
> +static int __init pcie1_ioresouces_setup(struct pcie_port *pp)
> +{
> ? ? ? ?/*
> ? ? ? ? * IORESOURCE_IO
> ? ? ? ? */
> - ? ? ? res[0].name = "PCIe I/O Space";
> - ? ? ? res[0].flags = IORESOURCE_IO;
> - ? ? ? res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
> - ? ? ? res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
> - ? ? ? if (request_resource(&ioport_resource, &res[0]))
> - ? ? ? ? ? ? ? panic("Request PCIe IO resource failed\n");
> - ? ? ? sys->resource[0] = &res[0];
> + ? ? ? pp->res[0].name ?= "PCIe 1 I/O Space";
> + ? ? ? pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
> + ? ? ? pp->res[0].end ? = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
> + ? ? ? pp->res[0].flags = IORESOURCE_IO;
> + ? ? ? if (request_resource(&ioport_resource, &pp->res[0]))
> + ? ? ? ? ? ? ? panic("Request PCIe 1 IO resource failed\n");
>
> ? ? ? ?/*
> ? ? ? ? * IORESOURCE_MEM
> ? ? ? ? */
> - ? ? ? res[1].name = "PCIe Memory Space";
> - ? ? ? res[1].flags = IORESOURCE_MEM;
> - ? ? ? res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
> - ? ? ? res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
> - ? ? ? if (request_resource(&iomem_resource, &res[1]))
> - ? ? ? ? ? ? ? panic("Request PCIe Memory resource failed\n");
> - ? ? ? sys->resource[1] = &res[1];
> + ? ? ? pp->res[1].name ?= "PCIe 1 MEM";
> + ? ? ? pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
> + ? ? ? pp->res[1].end ? = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
> + ? ? ? pp->res[1].flags = IORESOURCE_MEM;
> + ? ? ? if (request_resource(&iomem_resource, &pp->res[1]))
> + ? ? ? ? ? ? ? panic("Request PCIe 1 Memory resource failed\n");
>
> - ? ? ? sys->resource[2] = NULL;
> - ? ? ? sys->io_offset = 0;
> + ? ? ? return 1;
> +}
> +
> +static void __init kirkwood_pcie_preinit(void)
> +{
> + ? ? ? int i;
> +
> + ? ? ? for (i = 0; i < num_pcie_ports; i++) {
> + ? ? ? ? ? ? ? struct pcie_port *pp = pcie_port + i;
> + ? ? ? ? ? ? ? extern unsigned int kirkwood_clk_ctrl;
>
> + ? ? ? ? ? ? ? switch (pp->index) {
> + ? ? ? ? ? ? ? case 0:
> + ? ? ? ? ? ? ? ? ? ? ? pp->base = (void __iomem *)PCIE_VIRT_BASE;
> + ? ? ? ? ? ? ? ? ? ? ? pp->irq = IRQ_KIRKWOOD_PCIE;
> ? ? ? ?kirkwood_clk_ctrl |= CGC_PEX0;
> + ? ? ? ? ? ? ? ? ? ? ? pcie0_ioresouces_setup(pp);
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case 1:
> + ? ? ? ? ? ? ? ? ? ? ? pp->base = (void __iomem *)PCIE1_VIRT_BASE;
> + ? ? ? ? ? ? ? ? ? ? ? pp->irq = IRQ_KIRKWOOD_PCIE1;
> + ? ? ? ? ? ? ? ? ? ? ? kirkwood_clk_ctrl |= CGC_PEX1;
> + ? ? ? ? ? ? ? ? ? ? ? pcie1_ioresouces_setup(pp);
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? default:
> + ? ? ? ? ? ? ? ? ? ? ? panic("PCIe setup: invalid controller");
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +}
> +
> +static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
> +{
> + ? ? ? struct pcie_port *pp;
> +
> + ? ? ? if (nr >= num_pcie_ports)
> + ? ? ? ? ? ? ? return 0;
> +
> + ? ? ? pp = &pcie_port[nr];
> + ? ? ? pp->root_bus_nr = sys->busnr;
> +
> + ? ? ? printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n",
> + ? ? ? ? ? ? ?sys->busnr, pp->index);
> +
> + ? ? ? /*
> + ? ? ? ?* Generic PCIe unit setup.
> + ? ? ? ?*/
> + ? ? ? orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
> + ? ? ? orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
> +
> + ? ? ? sys->resource[0] = &pp->res[0];
> + ? ? ? sys->resource[1] = &pp->res[1];
> + ? ? ? sys->resource[2] = NULL;
> + ? ? ? sys->io_offset ? = 0;
>
> ? ? ? ?return 1;
> ?}
> @@ -163,7 +242,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
> ?{
> ? ? ? ?struct pci_bus *bus;
>
> - ? ? ? if (nr == 0) {
> + ? ? ? if (nr < num_pcie_ports) {
> ? ? ? ? ? ? ? ?bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
> ? ? ? ?} else {
> ? ? ? ? ? ? ? ?bus = NULL;
> @@ -175,18 +254,45 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
>
> ?static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
> ?{
> - ? ? ? return IRQ_KIRKWOOD_PCIE;
> + ? ? ? struct pcie_port *pp = bus_to_port(dev->bus->number);
> +
> + ? ? ? return pp->irq;
> ?}
>
> ?static struct hw_pci kirkwood_pci __initdata = {
> - ? ? ? .nr_controllers = 1,
> + ? ? ? .preinit ? ? ? ?= kirkwood_pcie_preinit,
> ? ? ? ?.swizzle ? ? ? ?= pci_std_swizzle,
> ? ? ? ?.setup ? ? ? ? ?= kirkwood_pcie_setup,
> ? ? ? ?.scan ? ? ? ? ? = kirkwood_pcie_scan_bus,
> ? ? ? ?.map_irq ? ? ? ?= kirkwood_pcie_map_irq,
> ?};
>
> -void __init kirkwood_pcie_init(void)
> +static void __init add_pcie_port(int index, unsigned long base)
> +{
> + ? ? ? printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
> +
> + ? ? ? if (orion_pcie_link_up((void __iomem *)base)) {
> + ? ? ? ? ? ? ? struct pcie_port *pp = &pcie_port[num_pcie_ports++];
> +
> + ? ? ? ? ? ? ? printk(KERN_INFO "link up\n");
> +
> + ? ? ? ? ? ? ? pp->index = index;
> + ? ? ? ? ? ? ? pp->root_bus_nr = -1;
> + ? ? ? ? ? ? ? pp->base = (void __iomem *)base;
> + ? ? ? ? ? ? ? spin_lock_init(&pp->conf_lock);
> + ? ? ? ? ? ? ? memset(pp->res, 0, sizeof(pp->res));
> + ? ? ? } else
> + ? ? ? ? ? ? ? printk(KERN_INFO "link down, ignoring\n");
> +}
> +
> +void __init kirkwood_pcie_init(unsigned int portmask)
> ?{
> + ? ? ? if (portmask & KW_PCIE0)
> + ? ? ? ? ? ? ? add_pcie_port(0, PCIE_VIRT_BASE);
> +
> + ? ? ? if (portmask & KW_PCIE1)
> + ? ? ? ? ? ? ? add_pcie_port(1, PCIE1_VIRT_BASE);
> +
> + ? ? ? kirkwood_pci.nr_controllers = num_pcie_ports;
> ? ? ? ?pci_common_init(&kirkwood_pci);
> ?}
> diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
> index 3bf6304..c34718c 100644
> --- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
> +++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
> @@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
> ?static int __init rd88f6192_pci_init(void)
> ?{
> ? ? ? ?if (machine_is_rd88f6192_nas())
> - ? ? ? ? ? ? ? kirkwood_pcie_init();
> + ? ? ? ? ? ? ? kirkwood_pcie_init(KW_PCIE0);
>
> ? ? ? ?return 0;
> ?}
> diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
> index 31708dd..3d14771 100644
> --- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
> +++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
> @@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
> ?static int __init rd88f6281_pci_init(void)
> ?{
> ? ? ? ?if (machine_is_rd88f6281())
> - ? ? ? ? ? ? ? kirkwood_pcie_init();
> + ? ? ? ? ? ? ? kirkwood_pcie_init(KW_PCIE0);
>
> ? ? ? ?return 0;
> ?}
> diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
> index d23aff9..5c7dd85 100644
> --- a/arch/arm/mach-kirkwood/ts219-setup.c
> +++ b/arch/arm/mach-kirkwood/ts219-setup.c
> @@ -111,7 +111,7 @@ static void __init qnap_ts219_init(void)
> ?static int __init ts219_pci_init(void)
> ?{
> ? ?if (machine_is_ts219())
> - ? ? ? ? ? kirkwood_pcie_init();
> + ? ? ? kirkwood_pcie_init(KW_PCIE0);
>
> ? ?return 0;
> ?}
> diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
> index ecd0d5f..a2c5f70 100644
> --- a/arch/arm/mach-kirkwood/ts41x-setup.c
> +++ b/arch/arm/mach-kirkwood/ts41x-setup.c
> @@ -136,7 +136,7 @@ static void __init qnap_ts41x_init(void)
> ?static int __init ts41x_pci_init(void)
> ?{
> ? ? ? ?if (machine_is_ts41x())
> - ? ? ? ? ? ? ? kirkwood_pcie_init();
> + ? ? ? ? ? ? ? kirkwood_pcie_init(KW_PCIE0);
>
> ? ?return 0;
> ?}
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From nico at fluxnic.net  Thu Jun 10 14:14:37 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 10 Jun 2010 14:14:37 -0400 (EDT)
Subject: [PATCH v2 1/4] ARM: Remove the domain switching on ARMv6k/v7 CPUs
In-Reply-To: <1276169316.24535.32.camel@e102109-lin.cambridge.arm.com>
References: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
	<20100602164841.17783.94825.stgit@e102109-lin.cambridge.arm.com>
	<alpine.LFD.2.00.1006091447460.30664@xanadu.home>
	<1276122405.17056.47.camel@toshiba-laptop>
	<alpine.LFD.2.00.1006092039000.30664@xanadu.home>
	<1276169316.24535.32.camel@e102109-lin.cambridge.arm.com>
Message-ID: <alpine.LFD.2.00.1006101411160.30664@xanadu.home>

On Thu, 10 Jun 2010, Catalin Marinas wrote:

> On Thu, 2010-06-10 at 01:56 +0100, Nicolas Pitre wrote:
> > On Wed, 9 Jun 2010, Catalin Marinas wrote:
> > 
> > > On Wed, 2010-06-09 at 20:10 +0100, Nicolas Pitre wrote:
> > > > Sorry for the delay... I'm just starting to seriously look at this.
> > > >
> > > > On Wed, 2 Jun 2010, Catalin Marinas wrote:
> > > >
> > > > > This patch removes the domain switching functionality via the set_fs and
> > > > > __switch_to functions on cores that have a TLS register.
> > > > [...]
> > > > > The user pages access rights are also modified for kernel read-only
> > > > > access rather than read/write so that the copy-on-write mechanism still
> > > > > works. CPU_USE_DOMAINS gets disabled only if HAS_TLS_REG is defined
> > > > > since writing the TLS value to the high vectors page isn't possible.
> > > >
> > > > I don't like this limitation much.
> > > >
> > > > Since the vector page has to be accessed somehow for FIQs anyway, and
> > > > the current solution for that involves accesses through the direct
> > > > mapping of the vector page, then this patch could be made to work on
> > > > pre-ARMv6 systems too simply by adding the necessary cache ops around
> > > > the TLS and FIQ updates.
> > >
> > > Getting rid of domains in Linux requires that several functions no
> > > longer use LDRT/STRT but LDR/STR. This implies that RO user pages should
> > > also have RO permissions for the kernel. I don't have the old ARM ARM at
> > > hand now but I recall there were some issues with user RO kernel RO
> > > permission on pre-ARMv6 processors (there is an R bit in the CP15
> > > control register which may help, I need to check the documentation).
> > 
> > I just checked.  It says:
> > 
> >    The access permission bits in section and page descriptors control
> >    access to the corresponding section or page. The access permissions
> >    are modified by the System (S) and ROM (R) control bits in CP15
> >    register 1.
> > 
> > But those bits are of no use as they are effective only when the MMU
> > access permission bits are all 0, otherwise they're ignored.
> 
> OK. So for read-only user pages we could set AP to 00 and R to 1 so that
> pages are read-only for kernel as well. For the other cases we just use
> a non-zero AP.

But what about non existing pages?  They can't go through with a read 
access from the first memory page.

> > What I mean, though, is for this patch to work as well on VIVT systems
> > by using the domain switching _only_ when updating the TLS value or the
> > FIQ handler in the vector page.
> 
> And all the other times the domain would be set to client. That would
> work but we still need to change set_pte_ext() for all the pre-ARMv6
> processors since we need the user RO kernel RO permission (otherwise we
> break the copy-on-write mechanism which is currently handled correctly
> because we use STRT).

Agreed.


Nicolas


From nico at fluxnic.net  Thu Jun 10 14:40:10 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 10 Jun 2010 14:40:10 -0400 (EDT)
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option for
	exceptions
In-Reply-To: <20100610090015.GD3422@pengutronix.de>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
	<20100610090015.GD3422@pengutronix.de>
Message-ID: <alpine.LFD.2.00.1006101429050.30664@xanadu.home>

On Thu, 10 Jun 2010, Uwe Kleine-K?nig wrote:

> >  - or the assumption of the zImage being loaded by the boot
> >    loader within 256MB from the start address is simply
> >    incorrect
> Hmmm, this makes the image depending on the bootloader.  Not that nice.
> 
> What do you think about requiring r4 to be set to physoffset as I did in
> my series?  This way zImage would already know PHYSOFFSET and so didn't
> need to guess ZRELADDR.

No.  That would make the dependency on the bootloader even _worse_.

And the fact is that most ARM targets have 256MB of RAM or less anyway, 
making this condition pretty hard to miss.  For those very few targets 
out there with more than 256MB of RAM it is rather safe to presume that 
they do load zImage/uImage in the first 256MB of RAM already, and making 
this condition effective for the future is not that bad.  And if you 
*really* can't satisfy that condition which would be really odd, then 
there is still the Kconfig option.

Compared to this, the conditions for the placement of zImage on x86 are 
far more restrictive.  So I much prefer to use generally safe 
assumptions which are compatible with existing bootloaders rather than 
having a new boot requirement for this.


Nicolas

From nico at fluxnic.net  Thu Jun 10 14:44:53 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 10 Jun 2010 14:44:53 -0400 (EDT)
Subject: [PATCH 0/5] Makefile.boot cleanup
In-Reply-To: <20100603075704.GB336@pengutronix.de>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<20100603075704.GB336@pengutronix.de>
Message-ID: <alpine.LFD.2.00.1006101442130.30664@xanadu.home>

On Thu, 3 Jun 2010, Uwe Kleine-K?nig wrote:

> Hello Eric,
> 
> On Thu, Jun 03, 2010 at 03:36:48PM +0800, Eric Miao wrote:
> > Several facts:
> > 
> > 1. ZRELADDR in most cases can be auto detected by maksing PC with
> >    0xf000_0000 if the zImage is placed within the first 256MiB from
> >    the memory start, which is a sane assumption except for:
> > 
> >    - when ARCH_MX1 or ARCH_SHARK is defined
> >    - when ARCH_U300 is defined (U300 really is strange when defining
> >      PHYS_OFFSET and ZRELADDR)
> >    - or when ZBOOT_ROM is defined
> If you guess ZRELADDR based on sp instead of pc it even should work if
> ZBOOT_ROM is defined?!

If you're using ZBOOT_ROM that means you want to execute zImage directly 
from ROM.  This is therefore a highly customized configuration.  In that 
context, having a variable phys-offset doesn't make much sense to start 
with.


Nicolas

From nico at fluxnic.net  Thu Jun 10 14:47:40 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 10 Jun 2010 14:47:40 -0400 (EDT)
Subject: [PATCH 01/10] arm/zImage: don't hard code the stack size twice
In-Reply-To: <AANLkTinvvP7GFMHDoaw3SgIetd42Yyho1r9oMuiSIlnV@mail.gmail.com>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-1-git-send-email-u.kleine-koenig@pengutronix.de>
	<AANLkTinvvP7GFMHDoaw3SgIetd42Yyho1r9oMuiSIlnV@mail.gmail.com>
Message-ID: <alpine.LFD.2.00.1006101446450.30664@xanadu.home>

On Thu, 10 Jun 2010, Eric Miao wrote:

> 2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> > Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> > ---
> > ?arch/arm/boot/compressed/head.S | ? ?3 ++-
> > ?1 files changed, 2 insertions(+), 1 deletions(-)
> >
> > diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> > index c5191b1..390aa92 100644
> > --- a/arch/arm/boot/compressed/head.S
> > +++ b/arch/arm/boot/compressed/head.S
> > @@ -315,7 +315,7 @@ LC0: ? ? ? ? ? ? ? ?.word ? LC0 ? ? ? ? ? ? ? ? ? ? @ r1
> > ? ? ? ? ? ? ? ?.word ? _image_size ? ? ? ? ? ? @ r6
> > ? ? ? ? ? ? ? ?.word ? _got_start ? ? ? ? ? ? ?@ r11
> > ? ? ? ? ? ? ? ?.word ? _got_end ? ? ? ? ? ? ? ?@ ip
> > - ? ? ? ? ? ? ? .word ? user_stack+4096 ? ? ? ? @ sp
> > + ? ? ? ? ? ? ? .word ? user_stack_end ? ? ? ? ?@ sp
> > ?LC1: ? ? ? ? ? .word ? reloc_end - reloc_start
> > ? ? ? ? ? ? ? ?.size ? LC0, . - LC0
> >
> > @@ -1070,3 +1070,4 @@ reloc_end:
> > ? ? ? ? ? ? ? ?.align
> > ? ? ? ? ? ? ? ?.section ".stack", "w"
> > ?user_stack: ? ?.space ?4096
> > +user_stack_end:
> 
> This one looks OK to me.
> 
> Acked-by: Eric Miao <eric.miao at canonical.com>

Acked-by: Nicolas Pitre <nicolas.pitre at linaro.org>


Nicolas

From milinevskyy at gmail.com  Thu Jun 10 15:12:55 2010
From: milinevskyy at gmail.com (Dmytro Milinevskyy)
Date: Thu, 10 Jun 2010 22:12:55 +0300
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
Message-ID: <4c1139ba.0d01df0a.42a6.1368@mx.google.com>

Hi!
This patch adds support for the OpenRD Ultimate machine(could be found at http://www.arm.linux.org.uk/developer/machines/list.php?id=2884)

Besides adding machine description this patch adds correction for PHY address for Ultimate version.

Differences from the previous attempt:
 - Correctly filled instances of mv643xx_eth_platform_data in case of ultimate version.
 - Do PCIE initialization for Ultimate version along with Base and Client
 - Init ge01 if (!openrd-base) to make the code cleaner

Regards,

-- Dmytro Milinevskyy

Signed-off-by: Dmytro Milinevskyy <milinevskyy at gmail.com>
---
 arch/arm/mach-kirkwood/Kconfig        |    7 +++++++
 arch/arm/mach-kirkwood/openrd-setup.c |   27 ++++++++++++++++++++++++---
 2 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 29b2163..110a3b8 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -75,6 +75,13 @@ config MACH_OPENRD_CLIENT
 	  Say 'Y' here if you want your kernel to support the
 	  Marvell OpenRD Client Board.
 
+config MACH_OPENRD_ULTIMATE
+	bool "Marvell OpenRD Ultimate Board"
+	select MACH_OPENRD
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  Marvell OpenRD Ultimate Board.
+
 config MACH_NETSPACE_V2
 	bool "LaCie Network Space v2 NAS Board"
 	help
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec..284b00f 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -1,7 +1,7 @@
 /*
  * arch/arm/mach-kirkwood/openrd-setup.c
  *
- * Marvell OpenRD (Base|Client) Board Setup
+ * Marvell OpenRD (Base|Client|Ultimate) Board Setup
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
@@ -73,9 +73,15 @@ static void __init openrd_init(void)
 
 	kirkwood_ehci_init();
 
+	if (machine_is_openrd_ultimate()) {
+		openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
+		openrd_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
+	}
+
 	kirkwood_ge00_init(&openrd_ge00_data);
-	if (machine_is_openrd_client())
+	if (!machine_is_openrd_base())
 		kirkwood_ge01_init(&openrd_ge01_data);
+
 	kirkwood_sata_init(&openrd_sata_data);
 	kirkwood_sdio_init(&openrd_mvsdio_data);
 
@@ -84,7 +90,9 @@ static void __init openrd_init(void)
 
 static int __init openrd_pci_init(void)
 {
-	if (machine_is_openrd_base() || machine_is_openrd_client())
+	if (machine_is_openrd_base() ||
+		machine_is_openrd_client() ||
+		machine_is_openrd_ultimate())
 		kirkwood_pcie_init();
 
 	return 0;
@@ -116,3 +124,16 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
 	.timer		= &kirkwood_timer,
 MACHINE_END
 #endif
+
+#ifdef CONFIG_MACH_OPENRD_ULTIMATE
+MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
+	/* Maintainer: Dhaval Vasa <dhaval.vasa at einfochips.com> */
+	.phys_io	= KIRKWOOD_REGS_PHYS_BASE,
+	.io_pg_offst	= ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+	.boot_params	= 0x00000100,
+	.init_machine	= openrd_init,
+	.map_io		= kirkwood_map_io,
+	.init_irq	= kirkwood_init_irq,
+	.timer		= &kirkwood_timer,
+MACHINE_END
+#endif
-- 
1.7.1



From nico at fluxnic.net  Thu Jun 10 15:18:14 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 10 Jun 2010 15:18:14 -0400 (EDT)
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <20100610063234.GA22533@pengutronix.de>
References: <4C083BCF.2060500@bluewatersys.com>
	<alpine.LFD.2.00.1006081655350.30664@xanadu.home>
	<4C0ED074.7050700@bluewatersys.com>
	<201006090807.20810.post@hendrik-sattler.de>
	<1276090378.2006.11.camel@m0nster>
	<20100610063234.GA22533@pengutronix.de>
Message-ID: <alpine.LFD.2.00.1006101513080.30664@xanadu.home>

On Thu, 10 Jun 2010, Uwe Kleine-K?nig wrote:

> I removed all lines from all defconfigs that don't affect the resulting
> .config basing on .35-rc1.  The diffstat is below.  As far as I checked
> there are no added lines and the 'pluses' are only context noise.  So
> the defconfigs are down to 124.4 (from 1214.4) lines on average.
> You can see the result at
> 
> 	http://git.pengutronix.de/?p=ukl/linux-2.6.git;a=commitdiff;h=arm/defconfig/reduced-v2.6.35-rc1
> 
> I'm currently reducing the defconfigs in .34 to be able to compare the
> diffstats between (.34 -> .35-rc1) and between (.34-reduced ->
> .35-reduced).  I would expect the diff is more or less the same as with
> the Kconfig idea.
> 
> Compared to the Kconfig idea I see a few advantages:
>  - Assuming that kautobuild would only use a base config + per arch
>    selections we would loose compile coverage of e.g. CONFIG_AEABI.

That is not acceptable of course.

Same thing for HIGHMEM, PREEMPT, SMP, etc.

>  - I have a script that reduces a config, so there is a bit less manual
>    work.
>  - No need to change kautobuild
> 
[...]
> 
>  177 files changed, 652 insertions(+), 194157 deletions(-)

That's really nice.


Nicolas

From amit.kucheria at canonical.com  Thu Jun 10 15:24:23 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Thu, 10 Jun 2010 21:24:23 +0200
Subject: [PATCH] mxc: Fix pad names for imx51
In-Reply-To: <20100610114945.GM20799@pengutronix.de>
References: <1275566746-6510-2-git-send-email-jason77.wang@gmail.com>
	<20100604085320.GB25357@pengutronix.de>
	<20100604105347.GA2982@matterhorn.lan>
	<20100604140959.GB2982@matterhorn.lan>
	<4C0D5996.9050906@boundarydevices.com>
	<20100607210448.GA2446@matterhorn.lan>
	<4C0D6183.1010501@boundarydevices.com>
	<20100608063036.GB20799@pengutronix.de>
	<20100609130904.GA2599@eyjafjallajokull>
	<20100610114945.GM20799@pengutronix.de>
Message-ID: <20100610192423.GE2599@eyjafjallajokull>

On 10 Jun 10, Sascha Hauer wrote:
> On Wed, Jun 09, 2010 at 03:09:04PM +0200, Amit Kucheria wrote:
> > On 10 Jun 08, Sascha Hauer wrote:
> > > On Mon, Jun 07, 2010 at 02:15:47PM -0700, Troy Kisky wrote:
> > > > Amit Kucheria wrote:
> > > > > On 10 Jun 07, Troy Kisky wrote:
> > > > > 
> > > > >>> On 10 Jun 04, Amit Kucheria wrote:
> > > > >>>
> > > > > 
> > > > > <snip>
> > > > > 
> > > > >>> +#define MX51_PAD_CSPI1_SCLK__GPIO_4_27		IOMUX_PAD(0x614, 0x224,  3, 0x0,   0, NO_PAD_CTRL)
> > > > > 
> > > > > <snip>
> > > > > 
> > > > >>> +#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
> > > > >>> +#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
> > > > >>> +#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
> > > > >>> +#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
> > > > >>> +#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
> > > > >>> +#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
> > > > >>> +#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
> > > > >>> +#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
> > > > >>> +#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
> > > > >> Why all the stuttering?
> > > > >> Isn't MX51_PAD_GPIO_1_9 or MX51_PAD_DISP2_DAT15 descriptive enough?
> > > > >>
> > > > > 
> > > > > Just following the convention use in the rest of imx devices. See the
> > > > > following comment at the top of the file:
> > > > > 
> > > > > /*
> > > > >  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
> > > > >  * If <padname> or <padmode> refers to a GPIO, it is named
> > > > >  * GPIO_<unit>_<num> see also iomux-v3.h
> > > > >  */
> > > > > 
> > > > > We could use the short names for pads being used in their "native mode".
> > > > > But as soon as we use the pad in a different mode, such as
> > > > > PAD_CSPI1_SCLK__GPIO_4_27 above, we'd need a different naming convention.
> > > > > 
> > > > > Regards,
> > > > > Amit
> > > > > 
> > > > 
> > > > I'm fine with MX51_PAD_CSPI1_SCLK__GPIO_4_27, but I don't care for
> > > > MX51_PAD_GPIO_1_9__GPIO_1_9. How about changing the comment to
> > > > 
> > > >  /*
> > > >   * The naming convention for the pad modes is MX51_PAD_<padname>
> > > >   * or MX51_PAD_<padname>__<padmode> if padname != padmode.
> > > >   * If <padname> or <padmode> refers to a GPIO, it is named
> > > >   * GPIO_<unit>_<num> see also iomux-v3.h
> > > >   */
> > > 
> > > If anything then MX51_PAD_GPIO_<unit>_<num>. I chose to use the long
> > > name to get a consistent naming and to express the fact that the pad has
> > > a name and the mode has a name which can but don't has to be the same.
> > > 
> > 
> > So will you take a modified patch to reflect this new naming convention?
> 
> Unless there are strong opinions for short names I'd like to keep the
> old naming scheme as it is also used for other i.MX SoCs.
> 

I don't have a strong opinion, but I think that the existing naming
scheme makes things a little more explicit by separating out pad name from
pad mode. I like it a little better.

Regards,
Amit
-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------


From martinwguy at gmail.com  Thu Jun 10 16:36:39 2010
From: martinwguy at gmail.com (Martin Guy)
Date: Thu, 10 Jun 2010 21:36:39 +0100
Subject: Context Switching is Broken
In-Reply-To: <20100610142015.GC32362@n2100.arm.linux.org.uk>
References: <503171.97993.qm@web51806.mail.re2.yahoo.com>
	<20100610140136.GA32362@n2100.arm.linux.org.uk>
	<20100610142015.GC32362@n2100.arm.linux.org.uk>
Message-ID: <AANLkTimeZ6xawjcYfVDohBFcMbbLlC3h2gDs91CyGcBX@mail.gmail.com>

On 6/10/10, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> On Thu, Jun 10, 2010 at 03:16:49PM +0100, Will Deacon wrote:
>  > > On Thu, Jun 10, 2010 at 04:11:35AM -0700, Herman Swartz wrote:
>  > > > Context switching is broken. The man page for context is example code
>  > > > that doesn't work, but should. Does a bug report need to be submitted?
>  > >
>  > > $ man context
>  > > No manual entry for context
>  > >
>
> > Quite. man makecontext has a fairly scary example, maybe that's it.
>
> In which case it's a question for libc people - the kernel has nothing
>  to do with makecontext, getcontext, setcontext and swapcontext.
>
>  I believe for glibc, these are simply unimplemented on ARM, and linking
>  a program which uses makecontext with glibc would result in the linker
>  issuing:
>
>  warning: makecontext is not implemented and will always fail

Indeed on ARM:

martin:~$ make makecontext
cc     makecontext.c   -o makecontext
/tmp/ccnapqW4.o: In function `main':
makecontext.c:(.text+0x110): warning: warning: getcontext is not
implemented and will always fail
makecontext.c:(.text+0x164): warning: warning: makecontext is not
implemented and will always fail
/tmp/ccnapqW4.o: In function `func1':
makecontext.c:(.text+0x24): warning: warning: swapcontext is not
implemented and will always fail
$ ./makecontext
Function not inplemented.
$

so?

    M


From akpm at linux-foundation.org  Thu Jun 10 16:43:04 2010
From: akpm at linux-foundation.org (Andrew Morton)
Date: Thu, 10 Jun 2010 13:43:04 -0700
Subject: [PATCH] s5pc110: SDHCI-s3c can override host capabilities
In-Reply-To: <20100605024053.GA23419@july>
References: <20100605024053.GA23419@july>
Message-ID: <20100610134304.c109811a.akpm@linux-foundation.org>

On Sat, 05 Jun 2010 11:40:53 +0900
Kyungmin Park <kmpark at infradead.org> wrote:

> From: Kyungmin Park <kmpark at infradead.org>
> To: linux-arm-kernel at lists.infradead.org, linux-mmc at vger.kernel.org, akpm at linux-foundation.org, ben-linux at fluff.org
> Subject: [PATCH] s5pc110: SDHCI-s3c can override host capabilities
> Date: Sat, 05 Jun 2010 11:40:53 +0900
> User-Agent: Mutt/1.5.14 (2007-02-12)
> 
> Each board can override the default sdhci host capabilities.
> Some board has broken features by hardwares and support 8-bit bandwidth.
> 
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>

The way this patch was presented, it will go into git with an Author:
address of "kmpark at infradead.org", but a Signed-off-by: address of
"kyungmin.park at samsung.com".  Which is a little odd.

The way to prevent that is to put an explicit "From:" line at the top
of the changelog.  If that line is absent, people's tools will fall
back to the From: line in the mail headers, which is what happened
here.

Please let me know if you want me to make any changes to these three
patches.



From ryan at bluewatersys.com  Thu Jun 10 16:46:29 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Fri, 11 Jun 2010 08:46:29 +1200
Subject: [PATCH 0/3] EP93xx: Add i2s audio support
In-Reply-To: <C54C83DB-A9D3-4A7A-837B-17644B257251@opensource.wolfsonmicro.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<20100609101742.GA5618@opensource.wolfsonmicro.com>
	<4C100A32.7010403@bluewatersys.com>
	(sfid-20100609_224011_305149_EE792DDC)
	<C54C83DB-A9D3-4A7A-837B-17644B257251@opensource.wolfsonmicro.com>
Message-ID: <4C114F25.5060809@bluewatersys.com>

Mark Brown wrote:
> On 9 Jun 2010, at 22:40, Ryan Mallon wrote:
> 
>> Stupid question, but where was it applied? I can't find it in any of the
>> branches at:
>> http://opensource.wolfsonmicro.com/cgi-bin/gitweb.cgi?p=linux-2.6-asoc.git;a=summary
> 
> Look in my kernel.org repository referenced in MAINTAINERS
> 
>    git://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound-2.6.git

Builds and runs fine.

Thanks,
~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From nico at fluxnic.net  Thu Jun 10 17:00:51 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 10 Jun 2010 17:00:51 -0400 (EDT)
Subject: [PATCH v2 1/4] ARM: Remove the domain switching on ARMv6k/v7 CPUs
In-Reply-To: <alpine.LFD.2.00.1006101411160.30664@xanadu.home>
References: <20100602164459.17783.9741.stgit@e102109-lin.cambridge.arm.com>
	<20100602164841.17783.94825.stgit@e102109-lin.cambridge.arm.com>
	<alpine.LFD.2.00.1006091447460.30664@xanadu.home>
	<1276122405.17056.47.camel@toshiba-laptop>
	<alpine.LFD.2.00.1006092039000.30664@xanadu.home>
	<1276169316.24535.32.camel@e102109-lin.cambridge.arm.com>
	<alpine.LFD.2.00.1006101411160.30664@xanadu.home>
Message-ID: <alpine.LFD.2.00.1006101648390.30664@xanadu.home>

On Thu, 10 Jun 2010, Nicolas Pitre wrote:

> On Thu, 10 Jun 2010, Catalin Marinas wrote:
> 
> > On Thu, 2010-06-10 at 01:56 +0100, Nicolas Pitre wrote:
> > > On Wed, 9 Jun 2010, Catalin Marinas wrote:
> > > 
> > > > On Wed, 2010-06-09 at 20:10 +0100, Nicolas Pitre wrote:
> > > > > Sorry for the delay... I'm just starting to seriously look at this.
> > > > >
> > > > > On Wed, 2 Jun 2010, Catalin Marinas wrote:
> > > > >
> > > > > > This patch removes the domain switching functionality via the set_fs and
> > > > > > __switch_to functions on cores that have a TLS register.
> > > > > [...]
> > > > > > The user pages access rights are also modified for kernel read-only
> > > > > > access rather than read/write so that the copy-on-write mechanism still
> > > > > > works. CPU_USE_DOMAINS gets disabled only if HAS_TLS_REG is defined
> > > > > > since writing the TLS value to the high vectors page isn't possible.
> > > > >
> > > > > I don't like this limitation much.
> > > > >
> > > > > Since the vector page has to be accessed somehow for FIQs anyway, and
> > > > > the current solution for that involves accesses through the direct
> > > > > mapping of the vector page, then this patch could be made to work on
> > > > > pre-ARMv6 systems too simply by adding the necessary cache ops around
> > > > > the TLS and FIQ updates.
> > > >
> > > > Getting rid of domains in Linux requires that several functions no
> > > > longer use LDRT/STRT but LDR/STR. This implies that RO user pages should
> > > > also have RO permissions for the kernel. I don't have the old ARM ARM at
> > > > hand now but I recall there were some issues with user RO kernel RO
> > > > permission on pre-ARMv6 processors (there is an R bit in the CP15
> > > > control register which may help, I need to check the documentation).
> > > 
> > > I just checked.  It says:
> > > 
> > >    The access permission bits in section and page descriptors control
> > >    access to the corresponding section or page. The access permissions
> > >    are modified by the System (S) and ROM (R) control bits in CP15
> > >    register 1.
> > > 
> > > But those bits are of no use as they are effective only when the MMU
> > > access permission bits are all 0, otherwise they're ignored.
> > 
> > OK. So for read-only user pages we could set AP to 00 and R to 1 so that
> > pages are read-only for kernel as well. For the other cases we just use
> > a non-zero AP.
> 
> But what about non existing pages?  They can't go through with a read 
> access from the first memory page.

Well... that looks like this is simply unworkable.  The R bit is global, 
so as soon as you have it on then kernel access to any memory will 
always succeed.  There is no way to have kernel RO user RO and still 
have no access on missing pages.

   Table 3-3 MMU access permissions

            Privileged    User
   AP   S R permissions   permissions

   0b00 0 0 No access     No access
   0b00 1 0 Read only     No access
   0b00 0 1 Read only     Read only
   0b00 1 1 UNPREDICTABLE UNPREDICTABLE
   0b01 x x Read/write    No access
   0b10 x x Read/write    Read only
   0b11 x x Read/write    Read/write


Nicolas


From r-woodruff2 at ti.com  Thu Jun 10 17:12:43 2010
From: r-woodruff2 at ti.com (Woodruff, Richard)
Date: Thu, 10 Jun 2010 16:12:43 -0500
Subject: facing undefined inconsistent cache issues on cortex-a9
In-Reply-To: <4C0905BC.1090301@st.com>
References: <4BF9F5FB.6020306@st.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C57001F3@dbde02.ent.ti.com>
	<4BFBBD83.5080302@st.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C57A5FC6@dbde02.ent.ti.com>
	<13B9B4C6EF24D648824FF11BE896716203BB37005A@dlee02.ent.ti.com>
	<4C0905BC.1090301@st.com>
Message-ID: <13B9B4C6EF24D648824FF11BE896716203BB762EB0@dlee02.ent.ti.com>


> From: Shiraz HASHIM [mailto:shiraz.hashim at st.com]
> Sent: Friday, June 04, 2010 8:55 AM
> To: Woodruff, Richard

> thanks for your inputs. We have some updates in this regard.
> In our architecture we have 2 ports coming out of the A9SM (multi core cortex)
> block to the interconnect matrix and the transfers are distributed between
> them.
>
> When we used the address filtering option of SCU to divide and mutually
> exclude
> the traffic between port0 and port1 of A9SM(multi core cortex) block. Like,
> assigning 1 half of the address space to port 1 and rest goes through port0.
> This solved the problem with the same set of cache and other system
> configurations.
> We are not using L2 cache and it is kept disabled. The SCU also is only used
> for
> address filtering and its synchronisation function is disabled (as we are not
> bringing up the second core)
> Now, we are not able to understand what it means. Do we need to divide the
> traffic between ports as described and it is normal. Or there is some problem
> in
> the way the transfers are handled in the system.

Off hand I'm not sure of the right answer.  The design I'm working on does not require the filtering feature so I've not looked much at it outside of some errata.  I am aware of another design which accesses a bit larger address space which does use filtering.

I'd guess you need to understand your cortex-memmap + AXI-to-memory bus adapter characteristics.

Regards,
Richard W.



From herman_swartz at yahoo.com  Thu Jun 10 17:18:58 2010
From: herman_swartz at yahoo.com (Herman Swartz)
Date: Thu, 10 Jun 2010 14:18:58 -0700 (PDT)
Subject: Context Switching is Broken
In-Reply-To: <AANLkTimeZ6xawjcYfVDohBFcMbbLlC3h2gDs91CyGcBX@mail.gmail.com>
References: <503171.97993.qm@web51806.mail.re2.yahoo.com>
	<20100610140136.GA32362@n2100.arm.linux.org.uk>
	<20100610142015.GC32362@n2100.arm.linux.org.uk>
	<AANLkTimeZ6xawjcYfVDohBFcMbbLlC3h2gDs91CyGcBX@mail.gmail.com>
Message-ID: <148780.29764.qm@web51806.mail.re2.yahoo.com>

Martin,

Looks like you took the example code out of the man page and tried to compile. This is what I get to. Look at my email sent a few minutes ago.

Thanks
HermanI



----- Original Message ----
From: Martin Guy <martinwguy at gmail.com>
To: Russell King - ARM Linux <linux at arm.linux.org.uk>
Cc: Will Deacon <will.deacon at arm.com>; Herman Swartz <herman_swartz at yahoo.com>; linux-arm-kernel at lists.infradead.org
Sent: Thu, June 10, 2010 4:36:39 PM
Subject: Re: Context Switching is Broken

On 6/10/10, Russell King - ARM Linux <linux at arm.linux.org.uk> wrote:
> On Thu, Jun 10, 2010 at 03:16:49PM +0100, Will Deacon wrote:
>? > > On Thu, Jun 10, 2010 at 04:11:35AM -0700, Herman Swartz wrote:
>? > > > Context switching is broken. The man page for context is example code
>? > > > that doesn't work, but should. Does a bug report need to be submitted?
>? > >
>? > > $ man context
>? > > No manual entry for context
>? > >
>
> > Quite. man makecontext has a fairly scary example, maybe that's it.
>
> In which case it's a question for libc people - the kernel has nothing
>? to do with makecontext, getcontext, setcontext and swapcontext.
>
>? I believe for glibc, these are simply unimplemented on ARM, and linking
>? a program which uses makecontext with glibc would result in the linker
>? issuing:
>
>? warning: makecontext is not implemented and will always fail

Indeed on ARM:

martin:~$ make makecontext
cc? ? makecontext.c? -o makecontext
/tmp/ccnapqW4.o: In function `main':
makecontext.c:(.text+0x110): warning: warning: getcontext is not
implemented and will always fail
makecontext.c:(.text+0x164): warning: warning: makecontext is not
implemented and will always fail
/tmp/ccnapqW4.o: In function `func1':
makecontext.c:(.text+0x24): warning: warning: swapcontext is not
implemented and will always fail
$ ./makecontext
Function not inplemented.
$

so?

? ? M



      


From martinwguy at gmail.com  Thu Jun 10 17:29:12 2010
From: martinwguy at gmail.com (Martin Guy)
Date: Thu, 10 Jun 2010 22:29:12 +0100
Subject: Context Switching is Broken
In-Reply-To: <148780.29764.qm@web51806.mail.re2.yahoo.com>
References: <503171.97993.qm@web51806.mail.re2.yahoo.com>
	<20100610140136.GA32362@n2100.arm.linux.org.uk>
	<20100610142015.GC32362@n2100.arm.linux.org.uk>
	<AANLkTimeZ6xawjcYfVDohBFcMbbLlC3h2gDs91CyGcBX@mail.gmail.com>
	<148780.29764.qm@web51806.mail.re2.yahoo.com>
Message-ID: <AANLkTilfwCVpr7JrLlWLIXV1DtAGZyRpvDd_8W-qfq5t@mail.gmail.com>

Hermann

While context switching works fine - any Unix system would have a hard
time working without it - these four esoteric system calls are not
implemented in the ARM port of Linux. If you'd like to modify the
linux source code to implement them, I'm sure the community would be
happy to review the patches for inclusion in the next version of the
kernel.

They seem to be implemented on x86 processors if you need them.

    M


From sshtylyov at mvista.com  Thu Jun 10 17:36:06 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 11 Jun 2010 01:36:06 +0400
Subject: [PATCH 02/10] arm/zImage: some comments for __armv3_mpu_cache_on
In-Reply-To: <1276165636-20150-2-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-2-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <4C115AC6.1040801@ru.mvista.com>

Hello.

Uwe Kleine-K?nig wrote:

> __armv3_mpu_cache_on seems broken.  As there is noone around who knows
> about these machines just keep the code as is but point out the strange
> things.

> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
>  arch/arm/boot/compressed/head.S |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index 390aa92..384150b 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -396,12 +396,15 @@ __armv3_mpu_cache_on:
>  
>  		mov	r0, #0
>  		mcr	p15, 0, r0, c7, c0, 0	@ invalidate whole cache v3
> +		/* ?? ARMv3 MMU doesn not allow reading the control register, does this really work on ARMv3 MPU? */

    Only "does not".

WBR, Sergei


From marek.vasut at gmail.com  Thu Jun 10 17:49:12 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 10 Jun 2010 23:49:12 +0200
Subject: [PATCH] sa1111: Prevent deadlock in resume path
In-Reply-To: <20100610135609.GC4514@ucw.cz>
References: <1274901104-22133-1-git-send-email-marek.vasut@gmail.com>
	<20100526201824.GA16418@n2100.arm.linux.org.uk>
	<20100610135609.GC4514@ucw.cz>
Message-ID: <201006102349.12849.marek.vasut@gmail.com>

Dne ?t 10. ?ervna 2010 15:56:10 Pavel Machek napsal(a):
> On Wed 2010-05-26 21:18:24, Russell King - ARM Linux wrote:
> > On Wed, May 26, 2010 at 09:15:57PM +0200, Marek Vasut wrote:
> > > Dne St 26. kv?tna 2010 21:14:25 Russell King - ARM Linux napsal(a):
> > > > On Wed, May 26, 2010 at 09:11:44PM +0200, Marek Vasut wrote:
> > > > > This patch reorganises the sa1111_resume() function in a manner the
> > > > > spinlock happens after calling the sa1111_wake(). This fixes two
> > > > > bugs:
> > > > > 
> > > > > 1) This function called sa1111_wake() which tried to claim the same
> > > > > spinlock
> > > > > 
> > > > >    the sa1111_resume() already claimed. This would result in
> > > > >    certain deadlock.
> > > > >    
> > > > >    Original idea for this part: Russell King
> > > > >    <linux at arm.linux.org.uk>
> > > > > 
> > > > > 2) The function didn't unlock the spinlock in case the chip didn't
> > > > > report
> > > > > 
> > > > >    correct ID.
> > > > >    
> > > > >    Original idea for this part: Julia Lawall <julia at diku.dk>
> > > > > 
> > > > > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> > > > 
> > > > Yea, good enough.
> > > 
> > > You want me to fight your patch tracking system or will you just merge
> > > it into your tree ?
> > 
> > What do you mean "fight" ?  Just send a standard git formatted patch
> > to the email address with an additional KernelVersion: tag.  It's
> > not at all hard.
> 
> You are linux kernel maintainer. Start acting as one. It is not at all
> hard.
> 
> Alternatively, just remove KernelVersion: checking in  your
> scripts.
> 
> 									Pavel

Even though my problem was fixed (yeah, sorry Russell, I didn't know the patch 
tracker was updated to support git-send-email), I have a question though.

I believe that Kernel-version is unnecessary. Isn't this information already 
encoded in the git-send-emailed patch?

btw. guys, before another burning discussion emerges, if you two plan to make 
your fights into a new sports discipline, I won't mind taking the role of a 
spectator ;-) Some possible criteria would be a length of the replying email or 
number of rough words ;-)


From linus.ml.walleij at gmail.com  Thu Jun 10 18:06:00 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Fri, 11 Jun 2010 00:06:00 +0200
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option for 
	exceptions
In-Reply-To: <AANLkTikulOGKEoAYptacYPgM8PAJ49JlGUO6rJWY5gqF@mail.gmail.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
	<20100610090015.GD3422@pengutronix.de>
	<AANLkTin9qGAJGSgu9Y2YjI_W8UwBITd-QYyGERcLLUgP@mail.gmail.com>
	<20100610095808.GA31057@pengutronix.de>
	<AANLkTikulOGKEoAYptacYPgM8PAJ49JlGUO6rJWY5gqF@mail.gmail.com>
Message-ID: <AANLkTimr0lj3Gsxw0LNf-tOX474HrSZ2-lntjrEYpu3a@mail.gmail.com>

2010/6/10 Eric Miao <eric.miao at canonical.com>:
> 2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:

>> But zreladdr is always physoffset + textoffset, isn't it?
>
> I'm not completely sure about the u300 case.

OK as you see in mach-u300/Makefile.boot we have ZRELADDR
at two different locations:

0x28E08000 or 0x48008000

(textoffset is 0x8000 IIRC)

The stuff in mach-u300/include/memory.h play with the Kconfig
options in mach-u300/Kconfig and is supposed to provide
dynamic resize of the memory for the 0x28e08000 variant,
because that variant can actually be reconfigured by the boot loader
(memory will be assigned to another CPU).

Then PHYS_OFFSET is set to the closest 2MiB boundary toward
lower addresses since this is required by ARM Linux.

As you can see in the Kconfig we currently have 13 MiB meaning
PHYS_OFFSET will be
0x28000000 + (13 - 13&1) *1024*1024 = 0x28C00000

This way we comply with the 2MiB alignment requirement,
even though in this case the actual physical memory begins
at 0x28D00000. So the first MiB does not really exist. This is
then compensated for in arch/arm/mm/mmu.c:

        /*
         * U300 - This platform family can share physical memory
         * between two ARM cpus, one running Linux and the other
         * running another OS.
         */
        if (machine_is_u300()) {
#ifdef CONFIG_MACH_U300_SINGLE_RAM
#if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) &&    \
        CONFIG_MACH_U300_2MB_ALIGNMENT_FIX
                res_size = 0x00100000;
#endif
#endif
        }

So we reserve the first MiB which is not actually memory, so
that this will not be used, and Linux will actually make use of
the memory from 0x28D00000.

If we had reserved 14MiB instead it would be:
0x28000000 + (14 - 14&1) *1024*1024 = 0x28E00000

And then it would have matched.

The ZRELADDR in Makefile.boot is actually just some
convention for the bootloader, it will work as long as we
shrink the memory used by the other CPU, if we expand it
past 14MiB everything breaks, like for 16 MiB for the other
CPU physical memory begins at 0x29000000 and trying
to have ZRELADDR at 28e08000 will just result in a
bus error.

So the relation between ZRELADDR and PHYS_OFFSET
on the U300 is:

if CONFIG_MACH_U300_SINGLE_RAM
PHYS_OFFSET = 0x28000000 +
  reserved_for_other_cpu_rounded_to_closest_2MiB_lower_addresses
ZRELADDR = 0x28e00000 + textoffset
else
PHYS_OFFSET = 0x48000000
ZRELADDR = 0x48000000 + textoffset
endif

So the assumption holds if
!CONFIG_MACH_U300_SINGLE_RAM

Else it is complicated.

Yours,
Linus Walleij


From linus.ml.walleij at gmail.com  Thu Jun 10 18:17:44 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Fri, 11 Jun 2010 00:17:44 +0200
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option for 
	exceptions
In-Reply-To: <1275550613-9553-5-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
Message-ID: <AANLkTiltifSEFdpXB0avw4ZyDzP_IrDpipafBAJbN17U@mail.gmail.com>

2010/6/3 Eric Miao <eric.miao at canonical.com>:

> +config ZRELADDR
> + ? ? ? hex "Physical address of the decompressed kernel image"
> + ? ? ? depends on !AUTO_ZRELADDR
> + ? ? ? default 0x00008000 if ARCH_BCMRING || ARCH_CNS3XXX || ARCH_DOVE ||\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARCH_EBSA110 || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR ||\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARCH_IOP13XX || ARCH_IOP33X || ARCH_IXP2000 ||\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARCH_IXP23XX || ARCH_IXP4XX || ARCH_KIRKWOOD ||\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARCH_KS8695 ?|| ARCH_LOKI || ARCH_MMP || ARCH_MV78XX0 ||\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARCH_NOMADIK || ARCH_NUC93X || ARCH_NS9XXX ||\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARCH_ORION5X || ARCH_SPEAR3XX || ARCH_SPEAR6XX ||\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARCH_UX5XX || ARCH_VERSATILE || ARCH_W90X900
> + ? ? ? default 0x08008000 if ARCH_MX1 || ARCH_SHARK
> + ? ? ? default 0x10008000 if ARCH_MSM || ARCH_OMAP1 || ARCH_RPC
> + ? ? ? default 0x20008000 if ARCH_S5P6440 || ARCH_S5P6442 ||\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARCH_S5PC100 || ARCH_S5PV210
> + ? ? ? default 0x30008000 if ARCH_S3C2410 || ARCH_S3C2400 || ARCH_S3C2412 ||\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARCH_S3C2416 || ARCH_S3C2440 || ARCH_S3C2443
> + ? ? ? default 0x40008000 if ARCH_STMP378X || ARCH_STMP37XX || ARCH_SH7372 ||\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARCH_SH7377
> + ? ? ? default 0x50008000 if ARCH_S3C64XX || ARCH_SH7367
> + ? ? ? default 0x60008000 if ARCH_VEXPRESS
> + ? ? ? default 0x80008000 if ARCH_MX25 || ARCH_MX3 || ARCH_NETX ||\
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ARCH_OMAP2 || ARCH_PNX4008
> + ? ? ? default 0x90008000 if ARCH_MX5 || ARCH_MX91231
> + ? ? ? default 0xa0008000 if ARCH_IOP32X || ARCH_PXA || MACH_MX27
> + ? ? ? default 0xc0008000 if ARCH_LH7A40X || MACH_MX21
> + ? ? ? default 0xf0008000 if ARCH_AAEC2000 || ARCH_L7200
> + ? ? ? default 0xc0028000 if ARCH_CLPS711X
> + ? ? ? default 0x70008000 if ARCH_AT91 && (ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
> + ? ? ? default 0x20008000 if ARCH_AT91 && !(ARCH_AT91CAP9 || ARCH_AT91SAM9G45)
> + ? ? ? default 0xc0008000 if ARCH_DAVINCI && ARCH_DAVINCI_DA8XX
> + ? ? ? default 0x80008000 if ARCH_DAVINCI && !ARCH_DAVINCI_DA8XX
> + ? ? ? default 0x00008000 if ARCH_EP93XX && EP93XX_SDCE3_SYNC_PHYS_OFFSET
> + ? ? ? default 0xc0008000 if ARCH_EP93XX && EP93XX_SDCE0_PHYS_OFFSET
> + ? ? ? default 0xd0008000 if ARCH_EP93XX && EP93XX_SDCE1_PHYS_OFFSET
> + ? ? ? default 0xe0008000 if ARCH_EP93XX && EP93XX_SDCE2_PHYS_OFFSET
> + ? ? ? default 0xf0008000 if ARCH_EP93XX && EP93XX_SDCE3_ASYNC_PHYS_OFFSET
> + ? ? ? default 0x00008000 if ARCH_GEMINI && GEMINI_MEM_SWAP
> + ? ? ? default 0x10008000 if ARCH_GEMINI && !GEMINI_MEM_SWAP
> + ? ? ? default 0x70008000 if ARCH_REALVIEW && REALVIEW_HIGH_PHYS_OFFSET
> + ? ? ? default 0x00008000 if ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET
> + ? ? ? default 0xc0208000 if ARCH_SA1100 && SA1111
> + ? ? ? default 0xc0008000 if ARCH_SA1100 && !SA1111
> + ? ? ? default 0x30108000 if ARCH_S3C2410 && PM_H1940
> + ? ? ? default 0x28E08000 if ARCH_U300 && MACH_U300_SINGLE_RAM
> + ? ? ? default 0x48008000 if ARCH_U300 && !MACH_U300_SINGLE_RAM

This looks correct so
Acked-by: Linus Walleij <linus.walleij at stericsson.com>

I assume it should be submitted simultaneously with a patch nuking off
all Makefile.boot files and that infrastructure then?

Yours,
Linus Walleij


From linus.ml.walleij at gmail.com  Thu Jun 10 18:23:31 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Fri, 11 Jun 2010 00:23:31 +0200
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option for 
	exceptions
In-Reply-To: <AANLkTin9qGAJGSgu9Y2YjI_W8UwBITd-QYyGERcLLUgP@mail.gmail.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
	<20100610090015.GD3422@pengutronix.de>
	<AANLkTin9qGAJGSgu9Y2YjI_W8UwBITd-QYyGERcLLUgP@mail.gmail.com>
Message-ID: <AANLkTilrG9sDFzAKaYi6k6dBGDC-Fgy6MIHyPHADTWs4@mail.gmail.com>

2010/6/10 Eric Miao <eric.miao at canonical.com>:

>>> arch/arm/mach-mx1/Makefile.boot: ? ? ? ? zreladdr-y ? := 0x08008000
>>> arch/arm/mach-shark/Makefile.boot: ? ? ? zreladdr-y ? := 0x08008000
>>> arch/arm/mach-u300/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x28E08000
>>> arch/arm/mach-u300/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x48008000
>> I care about mx1, so I would prefer using 0xf8000000.
>
> Fair enough actually. And my guess of the u300 architecture is the phys
> offset actually starts from 0x2800_0000 or 0x4800_0000 which is also
> covered by 0xf800_0000.

This is correct and incorrect. :-)

In the latter case yes, it is always at 0x48000000

In the other case the physical memory is indeed at 0x28000000 but
the range reserved for the other (ACC) CPU is locked by the boot
loader, and read/write results in a bus error. So this is compile-time
configurable.

It won't be more than a few MiB though, typically 13.

> And I think u300 can actually get rid of those
> inconsistent addresses by other means though we all know it might be
> suffering from the communication processor side of the memory allocation.

Any ideas, I'd be happy to implement them.

Any details you need, just ask.

Yours,
Linus Walleij


From linux at arm.linux.org.uk  Thu Jun 10 18:59:30 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 10 Jun 2010 23:59:30 +0100
Subject: Context Switching is Broken
In-Reply-To: <AANLkTilfwCVpr7JrLlWLIXV1DtAGZyRpvDd_8W-qfq5t@mail.gmail.com>
References: <503171.97993.qm@web51806.mail.re2.yahoo.com>
	<20100610140136.GA32362@n2100.arm.linux.org.uk>
	<20100610142015.GC32362@n2100.arm.linux.org.uk>
	<AANLkTimeZ6xawjcYfVDohBFcMbbLlC3h2gDs91CyGcBX@mail.gmail.com>
	<148780.29764.qm@web51806.mail.re2.yahoo.com>
	<AANLkTilfwCVpr7JrLlWLIXV1DtAGZyRpvDd_8W-qfq5t@mail.gmail.com>
Message-ID: <20100610225930.GD32362@n2100.arm.linux.org.uk>

On Thu, Jun 10, 2010 at 10:29:12PM +0100, Martin Guy wrote:
> While context switching works fine - any Unix system would have a hard
> time working without it - these four esoteric system calls are not
> implemented in the ARM port of Linux. If you'd like to modify the
> linux source code to implement them, I'm sure the community would be
> happy to review the patches for inclusion in the next version of the
> kernel.

If you read what I said:

"I believe for glibc, these are simply unimplemented on ARM, and linking
a program which uses makecontext with glibc would result in the linker
issuing:"

These calls are nothing to do with the kernel.  They're a subject purely
for glibc.  So there's no modification to the Linux kernel source code
which could effect their implementation.


From linux at arm.linux.org.uk  Thu Jun 10 19:05:52 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 11 Jun 2010 00:05:52 +0100
Subject: [PATCH] sa1111: Prevent deadlock in resume path
In-Reply-To: <201006102349.12849.marek.vasut@gmail.com>
References: <1274901104-22133-1-git-send-email-marek.vasut@gmail.com>
	<20100526201824.GA16418@n2100.arm.linux.org.uk>
	<20100610135609.GC4514@ucw.cz>
	<201006102349.12849.marek.vasut@gmail.com>
Message-ID: <20100610230552.GE32362@n2100.arm.linux.org.uk>

On Thu, Jun 10, 2010 at 11:49:12PM +0200, Marek Vasut wrote:
> Even though my problem was fixed (yeah, sorry Russell, I didn't know
> the patch tracker was updated to support git-send-email), I have a
> question though.
> 
> I believe that Kernel-version is unnecessary. Isn't this information already 
> encoded in the git-send-emailed patch?

It's there so that gnu patches can be accepted, and the additional
information does help when applying hard to apply patches, particularly
if either the patch has aged or was generated against an old kernel
version.

Not only that, but it was once critical when we had 2.4 and 2.5/2.6
kernel patches going via the patch system.

Last point to make - and it's in similar vain to the KernelVersion
tag - is that it would be useful if people would tag pure fixes which
should be applied to previous kernels with a "Cc: <stable at kernel.org>"
tag along-side the existing sign-offs.  That allows the stable
maintainers to automatically pick up on these patches when they're
merged into mainline.


From kmpark at infradead.org  Thu Jun 10 19:06:45 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 11 Jun 2010 08:06:45 +0900
Subject: [PATCH] s5pc110: SDHCI-s3c can override host capabilities
In-Reply-To: <20100610134304.c109811a.akpm@linux-foundation.org>
References: <20100605024053.GA23419@july>
	<20100610134304.c109811a.akpm@linux-foundation.org>
Message-ID: <AANLkTinwSxo4OqWlwQE-RxpG8WubLku2-77k2q7DPphr@mail.gmail.com>

hi,

On Fri, Jun 11, 2010 at 5:43 AM, Andrew Morton
<akpm at linux-foundation.org> wrote:
> On Sat, 05 Jun 2010 11:40:53 +0900
> Kyungmin Park <kmpark at infradead.org> wrote:
>
>> From: Kyungmin Park <kmpark at infradead.org>
>> To: linux-arm-kernel at lists.infradead.org, linux-mmc at vger.kernel.org, akpm at linux-foundation.org, ben-linux at fluff.org
>> Subject: [PATCH] s5pc110: SDHCI-s3c can override host capabilities
>> Date: Sat, 05 Jun 2010 11:40:53 +0900
>> User-Agent: Mutt/1.5.14 (2007-02-12)
>>
>> Each board can override the default sdhci host capabilities.
>> Some board has broken features by hardwares and support 8-bit bandwidth.
>>
>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>
> The way this patch was presented, it will go into git with an Author:
> address of "kmpark at infradead.org", but a Signed-off-by: address of
> "kyungmin.park at samsung.com". ?Which is a little odd.
>
> The way to prevent that is to put an explicit "From:" line at the top
> of the changelog. ?If that line is absent, people's tools will fall
> back to the From: line in the mail headers, which is what happened
> here.
>
> Please let me know if you want me to make any changes to these three
> patches.
>
No problem, please fix it freely.

Next time, I'll add the From line.
One more, mails from Marek has duplicated patches, so please ignore it.

Thank you,
Kyungmin Park


From herman_swartz at yahoo.com  Thu Jun 10 19:22:22 2010
From: herman_swartz at yahoo.com (Herman Swartz)
Date: Thu, 10 Jun 2010 16:22:22 -0700 (PDT)
Subject: Context Switching is Broken
In-Reply-To: <AANLkTilfwCVpr7JrLlWLIXV1DtAGZyRpvDd_8W-qfq5t@mail.gmail.com>
References: <503171.97993.qm@web51806.mail.re2.yahoo.com>
	<20100610140136.GA32362@n2100.arm.linux.org.uk>
	<20100610142015.GC32362@n2100.arm.linux.org.uk>
	<AANLkTimeZ6xawjcYfVDohBFcMbbLlC3h2gDs91CyGcBX@mail.gmail.com>
	<148780.29764.qm@web51806.mail.re2.yahoo.com>
	<AANLkTilfwCVpr7JrLlWLIXV1DtAGZyRpvDd_8W-qfq5t@mail.gmail.com>
Message-ID: <291734.41656.qm@web51808.mail.re2.yahoo.com>

esoteric "confined to and understandable by only an enlightened inner circle"

Sounds like there was a decision made during porting not to include these calls because they weren't considered useful enough.

What is the chance of requesting this to be included, along with other mods,?in the next release of the kernel for ARM?

The Sheeva PLUG is a neat/thrifty little box that runs 7X24. Unlike other computers laying around the house. :-)

JNOS is an Amateur Radio?packet radio communications program for TCP/IP running many?time dependent?segments.

Here is a requested?segment of the code:

/* Now do the context switch.
???? * This technique was inspired by Rob, PE1CHL, and is a bit tricky.
???? *
???? * If the old process has gone away, simply load the new process's
???? * environment. Otherwise, save the current process's state. Then if
???? * this is still the old process, load the new environment. Since the
???? * new task will "think" it's returning from the setjmp() with a return
???? * value of 1, the comparison with 0 will bypass the longjmp(), which
???? * would otherwise cause an infinite loop.
???? */
??? /* i_state isn't needed --- the signal mask is part of the context */
??? if (oldproc == NULLPROC)
??????? setcontext(&Curproc->env);
??? else
??????? swapcontext(&oldproc->env, &Curproc->env);
??? /* At this point, we're running in the newly dispatched task */
??? tmp = Curproc->retval;
??? Curproc->retval = 0;
??? /* Also restore the true interrupt state here, in case the longjmp
???? * DOES restore the interrupt state saved at the time of the setjmp().
???? * This is the case with Turbo-C's setjmp/longjmp.
???? */
??? restore(Curproc->i_state);
??? return tmp;
}




----- Original Message ----
From: Martin Guy <martinwguy at gmail.com>
To: Herman Swartz <herman_swartz at yahoo.com>
Cc: Russell King - ARM Linux <linux at arm.linux.org.uk>; Will Deacon <will.deacon at arm.com>; linux-arm-kernel at lists.infradead.org
Sent: Thu, June 10, 2010 5:29:12 PM
Subject: Re: Context Switching is Broken

Hermann

While context switching works fine - any Unix system would have a hard
time working without it - these four esoteric system calls are not
implemented in the ARM port of Linux. If you'd like to modify the
linux source code to implement them, I'm sure the community would be
happy to review the patches for inclusion in the next version of the
kernel.

They seem to be implemented on x86 processors if you need them.

? ? M



      


From herman_swartz at yahoo.com  Thu Jun 10 19:26:47 2010
From: herman_swartz at yahoo.com (Herman Swartz)
Date: Thu, 10 Jun 2010 16:26:47 -0700 (PDT)
Subject: Context Switching is Broken
In-Reply-To: <20100610225930.GD32362@n2100.arm.linux.org.uk>
References: <503171.97993.qm@web51806.mail.re2.yahoo.com>
	<20100610140136.GA32362@n2100.arm.linux.org.uk>
	<20100610142015.GC32362@n2100.arm.linux.org.uk>
	<AANLkTimeZ6xawjcYfVDohBFcMbbLlC3h2gDs91CyGcBX@mail.gmail.com>
	<148780.29764.qm@web51806.mail.re2.yahoo.com>
	<AANLkTilfwCVpr7JrLlWLIXV1DtAGZyRpvDd_8W-qfq5t@mail.gmail.com>
	<20100610225930.GD32362@n2100.arm.linux.org.uk>
Message-ID: <938111.34490.qm@web51801.mail.re2.yahoo.com>

Yes, the kernel has the functions, because the kernel uses them in it's operation. The glibc needs to implement these calls to the kernel. Do I have that right?

Herman



----- Original Message ----
From: Russell King - ARM Linux <linux at arm.linux.org.uk>
To: Martin Guy <martinwguy at gmail.com>
Cc: Herman Swartz <herman_swartz at yahoo.com>; Will Deacon <will.deacon at arm.com>; linux-arm-kernel at lists.infradead.org
Sent: Thu, June 10, 2010 6:59:30 PM
Subject: Re: Context Switching is Broken

On Thu, Jun 10, 2010 at 10:29:12PM +0100, Martin Guy wrote:
> While context switching works fine - any Unix system would have a hard
> time working without it - these four esoteric system calls are not
> implemented in the ARM port of Linux. If you'd like to modify the
> linux source code to implement them, I'm sure the community would be
> happy to review the patches for inclusion in the next version of the
> kernel.

If you read what I said:

"I believe for glibc, these are simply unimplemented on ARM, and linking
a program which uses makecontext with glibc would result in the linker
issuing:"

These calls are nothing to do with the kernel.? They're a subject purely
for glibc.? So there's no modification to the Linux kernel source code
which could effect their implementation.



      


From linux at arm.linux.org.uk  Thu Jun 10 19:36:17 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 11 Jun 2010 00:36:17 +0100
Subject: Context Switching is Broken
In-Reply-To: <938111.34490.qm@web51801.mail.re2.yahoo.com>
References: <503171.97993.qm@web51806.mail.re2.yahoo.com>
	<20100610140136.GA32362@n2100.arm.linux.org.uk>
	<20100610142015.GC32362@n2100.arm.linux.org.uk>
	<AANLkTimeZ6xawjcYfVDohBFcMbbLlC3h2gDs91CyGcBX@mail.gmail.com>
	<148780.29764.qm@web51806.mail.re2.yahoo.com>
	<AANLkTilfwCVpr7JrLlWLIXV1DtAGZyRpvDd_8W-qfq5t@mail.gmail.com>
	<20100610225930.GD32362@n2100.arm.linux.org.uk>
	<938111.34490.qm@web51801.mail.re2.yahoo.com>
Message-ID: <20100610233617.GA9865@n2100.arm.linux.org.uk>

On Thu, Jun 10, 2010 at 04:26:47PM -0700, Herman Swartz wrote:
> Yes, the kernel has the functions, because the kernel uses them in
> it's operation. The glibc needs to implement these calls to the
> kernel. Do I have that right?

No.  The kernel's context switching is entirely different to the
"context switching" that you're talking about here.

As I've said twice - and I'm not going to repeat it a third time -
this has nothing to do with the kernel and everything to do with
glibc.

You can see this from the i386 version of setcontext(), which can
be found in the glibc source code:

	sysdeps/unix/sysv/linux/i386/setcontext.S

The only call this code makes to the kernel is to set the processes
signal mask - which ARM has provided since day 1, and is used for
many things other than providing this support.  So there's nothing
to add to the kernel.

What's missing is the glibc support code.  Not the kernel code.

You need to talk to glibc people about this, not kernel people.


From kgene.kim at samsung.com  Thu Jun 10 20:29:38 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 11 Jun 2010 09:29:38 +0900
Subject: [PATCH 1/5] sdhci-s3c: depend on plat-samsung
In-Reply-To: <1276076383-24825-2-git-send-email-m.szyprowski@samsung.com>
References: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
	<1276076383-24825-2-git-send-email-m.szyprowski@samsung.com>
Message-ID: <000701cb08fd$2f8e15a0$8eaa40e0$%kim@samsung.com>

Marek Szyprowski wrote:
> 
> Most Samsung SoC have support for SDHCI block, so make the driver
> dependent on the Samsung platform instead on listing all SoCs in the
> Kconfig (and updating it again when support for the new SoC variant is
> added).
> 
Hi, Marek

Kyungmin Park already submitted same patch.

And Andrew Morton added to the -mm tree.
http://www.spinics.net/lists/mm-commits/msg79159.html

But, I think your comment is better...

> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  drivers/mmc/host/Kconfig |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index e171e77..acf5bf6 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -123,7 +123,7 @@ config MMC_SDHCI_PLTFM
> 
>  config MMC_SDHCI_S3C
>  	tristate "SDHCI support on Samsung S3C SoC"
> -	depends on MMC_SDHCI && (PLAT_S3C24XX || PLAT_S3C64XX)
> +	depends on MMC_SDHCI && PLAT_SAMSUNG
>  	help
>  	  This selects the Secure Digital Host Controller Interface (SDHCI)
>  	  often referrered to as the HSMMC block in some of the Samsung S3C
> --


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Thu Jun 10 20:56:38 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 11 Jun 2010 09:56:38 +0900
Subject: [PATCH 1/3] s3c64xx: Fix build without SDHCI controllers
In-Reply-To: <1276076345-24370-2-git-send-email-m.szyprowski@samsung.com>
References: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
	<1276076345-24370-2-git-send-email-m.szyprowski@samsung.com>
Message-ID: <000801cb0900$f64bbdc0$e2e33940$%kim@samsung.com>

Marek Szyprowski wrote:
> 
> This patch fixes the following compilation problem if only NCP machine
> is selected:
> 
> arch/arm/mach-s3c64xx/s3c6410.c: In function ?s3c6410_map_io?:
> arch/arm/mach-s3c64xx/s3c6410.c:51: error: implicit declaration of function
> ?s3c6410_default_sdhci2?
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/plat-samsung/include/plat/sdhci.h |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-
> samsung/include/plat/sdhci.h
> index 13f9fb2..c2044e5 100644
> --- a/arch/arm/plat-samsung/include/plat/sdhci.h
> +++ b/arch/arm/plat-samsung/include/plat/sdhci.h
> @@ -166,6 +166,7 @@ static inline void s3c6410_default_sdhci2(void) { }
>  #else
>  static inline void s3c6410_default_sdhci0(void) { }
>  static inline void s3c6410_default_sdhci1(void) { }
> +static inline void s3c6410_default_sdhci2(void) { }
>  static inline void s3c6400_default_sdhci0(void) { }
>  static inline void s3c6400_default_sdhci1(void) { }
> 
> --

Maybe missed in Maurus' patch 'S3C64XX: add HSMMC2 support'
commit 92b118f6968ae0788ac659af47b464acd9a754a1

Also need 'static inline s3c6400_default_sdhci2(void) { }'
Could you re-submit updated patch including s3c6400_default_sdhci2()?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From eric.miao at canonical.com  Thu Jun 10 21:23:31 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Fri, 11 Jun 2010 09:23:31 +0800
Subject: [PATCH 03/10] arm/zImage: __armv3_mpu_cache_flush: respect 
	should-be-zero specification
In-Reply-To: <1276165636-20150-3-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-3-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <AANLkTilwSqTKtyaKa53-Z_syTsdMNu5QUGkNh_IKNE11@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> Probably the register content for cache operations is "don't care" in
> practice, but as r1 is explicitly zeroed, use that one.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
> ?arch/arm/boot/compressed/head.S | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index 384150b..4058294 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -991,7 +991,7 @@ no_cache_id:
> ?__armv3_mmu_cache_flush:
> ?__armv3_mpu_cache_flush:
> ? ? ? ? ? ? ? ?mov ? ? r1, #0
> - ? ? ? ? ? ? ? mcr ? ? p15, 0, r0, c7, c0, 0 ? @ invalidate whole cache v3
> + ? ? ? ? ? ? ? mcr ? ? p15, 0, r1, c7, c0, 0 ? @ invalidate whole cache v3
> ? ? ? ? ? ? ? ?mov ? ? pc, lr

And this is at least more consistent with arch/arm/mm/cache-v3.S, so

Acked-by: Eric Miao <eric.miao at canonical.com>


From eric.miao at canonical.com  Thu Jun 10 21:34:31 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Fri, 11 Jun 2010 09:34:31 +0800
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option for 
	exceptions
In-Reply-To: <AANLkTilrG9sDFzAKaYi6k6dBGDC-Fgy6MIHyPHADTWs4@mail.gmail.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com> 
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com> 
	<20100610090015.GD3422@pengutronix.de>
	<AANLkTin9qGAJGSgu9Y2YjI_W8UwBITd-QYyGERcLLUgP@mail.gmail.com> 
	<AANLkTilrG9sDFzAKaYi6k6dBGDC-Fgy6MIHyPHADTWs4@mail.gmail.com>
Message-ID: <AANLkTin9MfkebiNoyjnJOfc4MMGHBDVqXOMRjw4YZNao@mail.gmail.com>

2010/6/11 Linus Walleij <linus.ml.walleij at gmail.com>:
> 2010/6/10 Eric Miao <eric.miao at canonical.com>:
>
>>>> arch/arm/mach-mx1/Makefile.boot: ? ? ? ? zreladdr-y ? := 0x08008000
>>>> arch/arm/mach-shark/Makefile.boot: ? ? ? zreladdr-y ? := 0x08008000
>>>> arch/arm/mach-u300/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x28E08000
>>>> arch/arm/mach-u300/Makefile.boot: ? ? ? ?zreladdr-y ? := 0x48008000
>>> I care about mx1, so I would prefer using 0xf8000000.
>>
>> Fair enough actually. And my guess of the u300 architecture is the phys
>> offset actually starts from 0x2800_0000 or 0x4800_0000 which is also
>> covered by 0xf800_0000.
>
> This is correct and incorrect. :-)
>
> In the latter case yes, it is always at 0x48000000
>
> In the other case the physical memory is indeed at 0x28000000 but
> the range reserved for the other (ACC) CPU is locked by the boot
> loader, and read/write results in a bus error. So this is compile-time
> configurable.
>
> It won't be more than a few MiB though, typically 13.
>
>> And I think u300 can actually get rid of those
>> inconsistent addresses by other means though we all know it might be
>> suffering from the communication processor side of the memory allocation.
>
> Any ideas, I'd be happy to implement them.
>

Is it possible to reserve the memory in machine_desc.fixup? though not
sure about if the memory will ever be accessed in the early stage.


From ben-linux at fluff.org  Thu Jun 10 21:57:44 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 02:57:44 +0100
Subject: [PATCH v3] libata: pata_samsung_cf: Add Samsung PATA
	controller driver
In-Reply-To: <4C10C1D6.8080708@ru.mvista.com>
References: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
	<4C10C1D6.8080708@ru.mvista.com>
Message-ID: <20100611015744.GC14272@trinity.fluff.org>

On Thu, Jun 10, 2010 at 02:43:34PM +0400, Sergei Shtylyov wrote:
> Kukjin Kim wrote:
>
>> From: Abhilash Kesavan <a.kesavan at samsung.com>
>
>> Adds support for the Samsung PATA controller. This driver is based on the
>> Libata subsystem and references the earlier patches sent for IDE subsystem.
>
>> Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
>> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
>
> [...]
>
>> diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
>> new file mode 100644
>> index 0000000..fef5515
>> --- /dev/null
>> +++ b/drivers/ata/pata_samsung_cf.c
>> @@ -0,0 +1,608 @@
>> +/* linux/drivers/ata/pata_samsung_cf.c
>
>    File names in the heading comment are discouraged.
>
> [...]

>> +static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
>> +{
>> +	int mode = adev->pio_mode - XFER_PIO_0;
>> +	struct s3c_ide_info *info = ap->host->private_data;
>> +	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
>> +	ulong piotime;
>> +
>> +	/* Calculates timing parameters for PIO mode */
>> +	piotime = pata_s3c_setup_timing(info, adev);
>
>    In fact, for 8-bit (command) timing you should program the slowest 
> mode of the two drives. However, with CF, you probably only have only one 
> drive per channel...
>
>> +
>> +	/* Enables IORDY if mode requires it */
>> +	if (ata_pio_need_iordy(adev))
>> +		ata_cfg |= S3C_ATA_CFG_IORDYEN;
>> +	else
>> +		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
>> +
>> +	/* Host controller supports upto PIO4 only */
>> +	if (mode >= 0 && mode <= 4) {
>
>    No need to check -- you won't be passed a mode not specified by your pio_mask.

probably not even worth bthering with a WARN_ON() for this.

.> +		writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
>> +		writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
>> +	}
>> +}
>
> [...]
>
>> +/*
>> + * pata_s3c_data_xfer - Transfer data by PIO
>> + */
>> +unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char *buf,
>> +				unsigned int buflen, int rw)
>> +{
>> +	struct ata_port *ap = dev->link->ap;
>> +	struct s3c_ide_info *info = ap->host->private_data;
>> +	void __iomem *data_addr = ap->ioaddr.data_addr;
>> +	unsigned int words = buflen >> 1, i;
>> +	u16 *data_ptr = (u16 *)buf;
>> +
>> +	if (rw == READ)
>> +		for (i = 0; i < words; i++, data_ptr++) {
>> +			wait_for_host_ready(info);
>> +			*data_ptr = readw(data_addr);
>
>    Why not just ignore the result?


possibly (void)readw(data_addr);

>> +			wait_for_host_ready(info);
>> +			*data_ptr = readw(info->ide_addr
>> +					+ S3C_ATA_PIO_RDATA);
>> +		}

It would be nice to have a description of why we're throwing data
away from the FIFO.

>> +	else
>> +		for (i = 0; i < words; i++, data_ptr++) {
>> +			wait_for_host_ready(info);
>> +			writel(*data_ptr, data_addr);
>> +		}

For the write case, would it be better to read the FIFO free lvel
and then then write that many words each time?

>> +	return words << 1;
>> +}
>
> [...]
>
>> +static struct ata_port_operations pata_s3c_port_ops = {
>> +	.inherits		= &ata_sff_port_ops,
>> +	.sff_check_status	= pata_s3c_check_status,
>> +	.sff_check_altstatus    = pata_s3c_check_altstatus,
>> +	.sff_tf_load		= pata_s3c_tf_load,
>> +	.sff_tf_read		= pata_s3c_tf_read,
>> +	.sff_data_xfer		= pata_s3c_data_xfer,
>> +	.sff_exec_command	= pata_s3c_exec_command,
>> +	.sff_dev_select         = pata_s3c_dev_select,
>> +	.sff_set_devctl         = pata_s3c_set_devctl,
>
>    I forgot: you also need to override the softreset() method as it 
> accesses several taskfile registers and ioread8()/iowrite8() won't 
> suffice -- Jeff was too quick to ack the patch. See ata_bus_softreset(), 
> ata_devchk(), and ata_sff_wait_after_reset() for the accesses I'm talking 
> about...
>
> [...]
>
>> +static int __devinit pata_s3c_probe(struct platform_device *pdev)
>> +{
>> +	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
>> +	struct device *dev = &pdev->dev;
>> +	struct s3c_ide_info *info;
>> +	struct resource *res;
>> +	struct ata_port *ap;
>> +	struct ata_host *host;
>> +	enum s3c_cpu_type cpu_type;
>> +	int ret;
>> +
>> +	cpu_type = platform_get_device_id(pdev)->driver_data;
>> +
>> +	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
>> +	if (!info) {
>> +		dev_err(dev, "failed to allocate memory for device data\n");
>> +		return -ENOMEM;
>> +	}
>> +
>> +	info->irq = platform_get_irq(pdev, 0);
>> +	if (info->irq < 0) {
>> +		dev_err(dev, "could not obtain irq number\n");
>> +		ret = -EINVAL;
>> +		goto release_device_mem;
>> +	}
>> +
>> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +	if (res == NULL) {
>> +		dev_err(dev, "failed to get mem resource\n");
>> +		ret = -EINVAL;
>> +		goto release_device_mem;
>> +	}
>> +
>> +	if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
>
>    Probably should call devm_request_mem_region() if you're using  
> devm_ioremap()...
>
>> +		dev_err(dev, "error requesting register region\n");
>> +		return -EBUSY;
>> +	}
>> +
>> +	info->ide_addr = devm_ioremap(dev, res->start, resource_size(res));
>> +	if (!info->ide_addr) {
>> +		dev_err(dev, "failed to map IO base address\n");
>> +		ret = -ENOMEM;
>> +		goto release_mem;
>> +	}
>> +
>> +	info->clk = clk_get(&pdev->dev, "cfcon");
>> +	if (IS_ERR(info->clk)) {
>> +		dev_err(dev, "failed to get access to cf controller clock\n");
>> +		ret = PTR_ERR(info->clk);
>> +		info->clk = NULL;

We really need to get away from passing a clock name here.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From ben-linux at fluff.org  Thu Jun 10 22:24:10 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 03:24:10 +0100
Subject: [PATCH v3] libata: pata_samsung_cf: Add Samsung PATA
	controller driver
In-Reply-To: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
References: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <20100611022410.GD14272@trinity.fluff.org>

On Thu, Jun 10, 2010 at 04:50:41PM +0900, Kukjin Kim wrote:
> From: Abhilash Kesavan <a.kesavan at samsung.com>
> 
> Adds support for the Samsung PATA controller. This driver is based on the
> Libata subsystem and references the earlier patches sent for IDE subsystem.
> 
> Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>

a few more comments, you may or may not want to fix before first
submission.

> ---
> 
> Changes since v2:
> - Changed the DRV_NAME to pata_samsung_cf
> - Used msleep instead of mdelay
> 
>  drivers/ata/Makefile          |    1 +
>  drivers/ata/pata_samsung_cf.c |  608 +++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 618 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/ata/pata_samsung_cf.c
> 
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index aa85a98..1b5facf 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -796,6 +796,15 @@ config PATA_RZ1000
>  
>  	  If unsure, say N.
>  
> +config PATA_SAMSUNG_CF
> +	tristate "Samsung SoC PATA support"
> +	depends on SAMSUNG_DEV_IDE
> +	help
> +	  This option enables basic support for Samsung's S3C/S5P board
> +	  PATA controllers via the new ATA layer
> +
> +	  If unsure, say N.
> +
>  config PATA_WINBOND_VLB
>  	tristate "Winbond W83759A VLB PATA support (Experimental)"
>  	depends on ISA && EXPERIMENTAL
> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> index 7ef89d7..9576776 100644
> --- a/drivers/ata/Makefile
> +++ b/drivers/ata/Makefile
> @@ -87,6 +87,7 @@ obj-$(CONFIG_PATA_OF_PLATFORM)	+= pata_of_platform.o
>  obj-$(CONFIG_PATA_QDI)		+= pata_qdi.o
>  obj-$(CONFIG_PATA_RB532)	+= pata_rb532_cf.o
>  obj-$(CONFIG_PATA_RZ1000)	+= pata_rz1000.o
> +obj-$(CONFIG_PATA_SAMSUNG_CF)	+= pata_samsung_cf.o
>  obj-$(CONFIG_PATA_WINBOND_VLB)	+= pata_winbond.o
>  
>  # Should be last but two libata driver
> diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
> new file mode 100644
> index 0000000..fef5515
> --- /dev/null
> +++ b/drivers/ata/pata_samsung_cf.c
> @@ -0,0 +1,608 @@
> +/* linux/drivers/ata/pata_samsung_cf.c
> + *
> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * PATA driver for Samsung SoCs.
> + * Supports CF Interface in True IDE mode. Currently only PIO mode has been
> + * implemented; UDMA support has to be added.
> + *
> + * Based on:
> + *	PATA driver for AT91SAM9260 Static Memory Controller
> + *	PATA driver for Toshiba SCC controller
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2
> + * as published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/clk.h>
> +#include <linux/libata.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include <plat/ata.h>
> +#include <plat/regs-ata.h>
> +
> +#define DRV_NAME "pata_samsung_cf"
> +#define DRV_VERSION "0.1"
> +
> +enum s3c_cpu_type {
> +	TYPE_S3C64XX,
> +	TYPE_S5PC100,
> +	TYPE_S5PV210,
> +};
> +
> +/*
> + * struct s3c_ide_info - S3C PATA instance.
> + * @clk: The clock resource for this controller.
> + * @ide_addr: The area mapped for the hardware registers.
> + * @sfr_addr: The area mapped for the special function registers.
> + * @irq: The IRQ number we are using.
> + * @cpu_type: The exact type of this controller.
> + * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
> + */
> +struct s3c_ide_info {
> +	struct clk *clk;
> +	void __iomem *ide_addr;
> +	void __iomem *sfr_addr;
> +	unsigned int irq;
> +	enum s3c_cpu_type cpu_type;
> +	unsigned int fifo_status_reg;
> +};
> +
> +static void pata_s3c_set_endian(void *s3c_ide_regbase, u8 mode)
> +{
should be void __iomem.

> +static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
> +{
> +	int mode = adev->pio_mode - XFER_PIO_0;
> +	struct s3c_ide_info *info = ap->host->private_data;
> +	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
> +	ulong piotime;
> +
> +	/* Calculates timing parameters for PIO mode */
> +	piotime = pata_s3c_setup_timing(info, adev);
> +
> +	/* Enables IORDY if mode requires it */
> +	if (ata_pio_need_iordy(adev))
> +		ata_cfg |= S3C_ATA_CFG_IORDYEN;
> +	else
> +		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
> +
> +	/* Host controller supports upto PIO4 only */
> +	if (mode >= 0 && mode <= 4) {

if this code was to stay in, it would have been better to either
WARN_ON() or print some form of error messagee instead of just silently
ignoring it... also, you should have probably set the minumum acceptable
ATA mode to ensure any further actions would not cause problems with
trying to run the b us too fast.

> +/*
> + * Waits until the IDE controller is able to perform next read/write
> + * operation to the disk. Needed for 64XX series boards only.
> + */

if it is needed only for s3c64xx series, why don't we bail if the
info->type != 64xx?

> +static int wait_for_host_ready(struct s3c_ide_info *info)
> +{
> +	ulong timeout;
> +
> +	/* wait for maximum of 20 msec */
> +	timeout = jiffies + msecs_to_jiffies(20);
> +	while (time_before(jiffies, timeout)) {
> +		if ((readl(info->ide_addr + info->fifo_status_reg) >> 28) == 0)

would be neater to have 
      void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg
      ...

      while(...) {
      		 if (readl(fifo_reg) >> 28) == 0)
	 ...

> +			return 0;
> +	}
> +	return -EBUSY;
> +}

[snip]

> +/*
> + * pata_s3c_data_xfer - Transfer data by PIO
> + */
> +unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char *buf,
> +				unsigned int buflen, int rw)
> +{
> +	struct ata_port *ap = dev->link->ap;
> +	struct s3c_ide_info *info = ap->host->private_data;
> +	void __iomem *data_addr = ap->ioaddr.data_addr;
> +	unsigned int words = buflen >> 1, i;
> +	u16 *data_ptr = (u16 *)buf;

note, is there any chance of being passed a number of bytes? if so
should we at least WARN_ON(buflen & 1) and return an error?

> +	if (rw == READ)
> +		for (i = 0; i < words; i++, data_ptr++) {
> +			wait_for_host_ready(info);
> +			*data_ptr = readw(data_addr);
> +			wait_for_host_ready(info);
> +			*data_ptr = readw(info->ide_addr
> +					+ S3C_ATA_PIO_RDATA);
> +		}
> +	else
> +		for (i = 0; i < words; i++, data_ptr++) {
> +			wait_for_host_ready(info);
> +			writel(*data_ptr, data_addr);
> +		}
> +
> +	return words << 1;
> +}
> +
> +/*
> + * pata_s3c_dev_select - Select device on ATA bus
> + */
> +static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
> +{
> +	u8 tmp;
> +
> +	if (device == 0)
> +		tmp = ATA_DEVICE_OBS;
> +	else
> +		tmp = ATA_DEVICE_OBS | ATA_DEV1;

you could have done
    u8 tmp = ATA_DEVICE_OBS;

    if (device != 0)
	tmp |= ATA_DEV1

> +	ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
> +	ata_sff_pause(ap);
> +}
> +

[snip]

> +static void pata_s3c_enable(void *s3c_ide_regbase, u8 state)
  state would be better as a bool or a natural int.
> +{
> +	u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
> +	temp = state ? (temp | 1) : (temp & ~1);
> +	writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
> +}
> +
> +static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
> +{
> +	struct ata_host *host = dev_instance;
> +	struct s3c_ide_info *info = host->private_data;
> +	u32 reg;
> +
> +	reg = readl(info->ide_addr + S3C_ATA_IRQ);
> +	writel(reg, info->ide_addr + S3C_ATA_IRQ);

no decoding of the interrupt cause?

> +	return ata_sff_interrupt(irq, dev_instance);
> +}

> +static int __devexit pata_s3c_remove(struct platform_device *pdev)
> +{
> +	struct ata_host *host = platform_get_drvdata(pdev);
> +	struct s3c_ide_info *info;
> +	struct resource *res;

> +
> +	if (!host)
> +		return 0;

don't think this check is really necessary.

> +	info = host->private_data;
> +
> +	ata_host_detach(host);
> +
> +	clk_disable(info->clk);
> +	clk_put(info->clk);
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	release_mem_region(res->start, resource_size(res));
> +	kfree(info);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int pata_s3c_suspend(struct device *dev)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct ata_host *host = platform_get_drvdata(pdev);
> +	pm_message_t state = PMSG_SUSPEND;
> +
> +	if (host)
> +		return ata_host_suspend(host, state);

again, don't think you'l lget called here if you didn't sucessfully bind.

> +	else
> +		return 0;
> +}
> +
> +static int pata_s3c_resume(struct device *dev)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct ata_host *host = platform_get_drvdata(pdev);
> +	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
> +	struct s3c_ide_info *info;
> +
> +	info = host->private_data;
> +
> +	if (host) {
> +		pata_s3c_hwinit(info, pdata);
> +		ata_host_resume(host);
> +	}
> +
> +	return 0;
> +}
> +
> +static const struct dev_pm_ops pata_s3c_pm_ops = {
> +	.suspend	= pata_s3c_suspend,
> +	.resume		= pata_s3c_resume,
> +};

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From kyungmin.park at samsung.com  Thu Jun 10 23:30:53 2010
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Fri, 11 Jun 2010 12:30:53 +0900
Subject: [PATCH 1/3] s3c64xx: Fix build without SDHCI controllers
In-Reply-To: <000801cb0900$f64bbdc0$e2e33940$%kim@samsung.com>
References: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
	<1276076345-24370-2-git-send-email-m.szyprowski@samsung.com>
	<000801cb0900$f64bbdc0$e2e33940$%kim@samsung.com>
Message-ID: <AANLkTimPp36K_SmFm053cu9f9Znb8SFHVcKAn8bjD1PI@mail.gmail.com>

On Fri, Jun 11, 2010 at 9:56 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Marek Szyprowski wrote:
>>
>> This patch fixes the following compilation problem if only NCP machine
>> is selected:
>>
>> arch/arm/mach-s3c64xx/s3c6410.c: In function ?s3c6410_map_io?:
>> arch/arm/mach-s3c64xx/s3c6410.c:51: error: implicit declaration of function
>> ?s3c6410_default_sdhci2?
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>> ---
>> ?arch/arm/plat-samsung/include/plat/sdhci.h | ? ?1 +
>> ?1 files changed, 1 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-
>> samsung/include/plat/sdhci.h
>> index 13f9fb2..c2044e5 100644
>> --- a/arch/arm/plat-samsung/include/plat/sdhci.h
>> +++ b/arch/arm/plat-samsung/include/plat/sdhci.h
>> @@ -166,6 +166,7 @@ static inline void s3c6410_default_sdhci2(void) { }
>> ?#else
>> ?static inline void s3c6410_default_sdhci0(void) { }
>> ?static inline void s3c6410_default_sdhci1(void) { }
>> +static inline void s3c6410_default_sdhci2(void) { }
>> ?static inline void s3c6400_default_sdhci0(void) { }
>> ?static inline void s3c6400_default_sdhci1(void) { }
>>
>> --
>
> Maybe missed in Maurus' patch 'S3C64XX: add HSMMC2 support'
> commit 92b118f6968ae0788ac659af47b464acd9a754a1

Which kernel tree do you use?
it's against the latest kernel.

Thank you,
Kyungmin Park

>
> Also need 'static inline s3c6400_default_sdhci2(void) { }'
> Could you re-submit updated patch including s3c6400_default_sdhci2()?
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>


From kmpark at infradead.org  Thu Jun 10 23:32:46 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 11 Jun 2010 12:32:46 +0900
Subject: [PATCH] sdhci-s3c: Add SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK quirk 
	for Samsung SoC
In-Reply-To: <1276169991-16396-1-git-send-email-kgene.kim@samsung.com>
References: <1276169991-16396-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <AANLkTim2LzIh7dadCAWCo6jltS4CYA8gLKaiQne_VzqK@mail.gmail.com>

Hi,

On Thu, Jun 10, 2010 at 8:39 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> From: Lee Hyuk <hyuk1.lee at samsung.com>
>
> On Samsung's SDMMC hosts the timeout clock is derivied from the SD
> Clock, which is set dynamically.
> So, checked 'SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK' quirk and removed
> 'sdhci_s3c_get_timeout_clk' callback which doesn't need any more.
>
> Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
> ?drivers/mmc/host/sdhci-s3c.c | ? 10 +++-------
> ?1 files changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index af21792..ca09382 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -110,11 +110,6 @@ static unsigned int sdhci_s3c_get_max_clk(struct sdhci_host *host)
> ? ? ? ?return max;
> ?}
>
> -static unsigned int sdhci_s3c_get_timeout_clk(struct sdhci_host *host)
> -{
> - ? ? ? return sdhci_s3c_get_max_clk(host) / 1000000;
> -}
> -
> ?/**
> ?* sdhci_s3c_consider_clock - consider one the bus clocks for current setting
> ?* @ourhost: Our SDHCI instance.
> @@ -188,7 +183,6 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
>
> ? ? ? ? ? ? ? ?ourhost->cur_clk = best_src;
> ? ? ? ? ? ? ? ?host->max_clk = clk_get_rate(clk);
> - ? ? ? ? ? ? ? host->timeout_clk = sdhci_s3c_get_timeout_clk(host);
>
> ? ? ? ? ? ? ? ?ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
> ? ? ? ? ? ? ? ?ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
> @@ -211,7 +205,6 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
>
> ?static struct sdhci_ops sdhci_s3c_ops = {
> ? ? ? ?.get_max_clock ? ? ? ? ?= sdhci_s3c_get_max_clk,
> - ? ? ? .get_timeout_clock ? ? ?= sdhci_s3c_get_timeout_clk,
> ? ? ? ?.set_clock ? ? ? ? ? ? ?= sdhci_s3c_set_clock,
> ?};
>
> @@ -335,6 +328,9 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
> ? ? ? ?host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
> ? ? ? ? ? ? ? ? ? ? ? ? SDHCI_QUIRK_32BIT_DMA_SIZE);
>
> + ? ? ? /* HSMMC on Samsung SoCs uses SDCLK as timeout clock. */
> + ? ? ? host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;

How do you know Samsung SoCs use SDCLK in the spec?

Is it also true at s3c64xx series?

Thank you,
Kyungmin Park

> +
> ? ? ? ?ret = sdhci_add_host(host);
> ? ? ? ?if (ret) {
> ? ? ? ? ? ? ? ?dev_err(dev, "sdhci_add_host() failed\n");
> --
> 1.6.2.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>


From kgene.kim at samsung.com  Thu Jun 10 23:58:46 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 11 Jun 2010 12:58:46 +0900
Subject: [PATCH 1/3] s3c64xx: Fix build without SDHCI controllers
In-Reply-To: <AANLkTimPp36K_SmFm053cu9f9Znb8SFHVcKAn8bjD1PI@mail.gmail.com>
References: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
	<1276076345-24370-2-git-send-email-m.szyprowski@samsung.com>
	<000801cb0900$f64bbdc0$e2e33940$%kim@samsung.com>
	<AANLkTimPp36K_SmFm053cu9f9Znb8SFHVcKAn8bjD1PI@mail.gmail.com>
Message-ID: <000c01cb091a$675b2fa0$36118ee0$%kim@samsung.com>

Kyungmin Park wrote:
> 
> On Fri, Jun 11, 2010 at 9:56 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > Marek Szyprowski wrote:
> >>
> >> This patch fixes the following compilation problem if only NCP machine
> >> is selected:
> >>
> >> arch/arm/mach-s3c64xx/s3c6410.c: In function ?s3c6410_map_io?:
> >> arch/arm/mach-s3c64xx/s3c6410.c:51: error: implicit declaration of function
> >> ?s3c6410_default_sdhci2?
> >>
> >> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> >> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> >> ---
> >>  arch/arm/plat-samsung/include/plat/sdhci.h |    1 +
> >>  1 files changed, 1 insertions(+), 0 deletions(-)
> >>
> >> diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-
> >> samsung/include/plat/sdhci.h
> >> index 13f9fb2..c2044e5 100644
> >> --- a/arch/arm/plat-samsung/include/plat/sdhci.h
> >> +++ b/arch/arm/plat-samsung/include/plat/sdhci.h
> >> @@ -166,6 +166,7 @@ static inline void s3c6410_default_sdhci2(void) { }
> >>  #else
> >>  static inline void s3c6410_default_sdhci0(void) { }
> >>  static inline void s3c6410_default_sdhci1(void) { }
> >> +static inline void s3c6410_default_sdhci2(void) { }
> >>  static inline void s3c6400_default_sdhci0(void) { }
> >>  static inline void s3c6400_default_sdhci1(void) { }
> >>
> >> --
> >
> > Maybe missed in Maurus' patch 'S3C64XX: add HSMMC2 support'
> > commit 92b118f6968ae0788ac659af47b464acd9a754a1
> 
> Which kernel tree do you use?
> it's against the latest kernel.
>
Of course, Linus' 35-rc2.
Any problem?

> >
> > Also need 'static inline s3c6400_default_sdhci2(void) { }'
> > Could you re-submit updated patch including s3c6400_default_sdhci2()?
> >


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From viresh.kumar at st.com  Fri Jun 11 00:09:53 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Fri, 11 Jun 2010 09:39:53 +0530
Subject: [PATCH resend] Watchdog: Adding support for ARM Primecell SP805
	Watchdog
In-Reply-To: <1275465783-14052-1-git-send-email-viresh.kumar@st.com>
References: <1275465783-14052-1-git-send-email-viresh.kumar@st.com>
Message-ID: <4C11B711.70907@st.com>

On 6/2/2010 1:33 PM, Viresh KUMAR wrote:
> Technical Reference Manual can be found at:
> http://infocenter.arm.com/help/topic/com.arm.doc.ddi0270b/DDI0270.pdf
> 
> Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
> ---
>  drivers/watchdog/Kconfig     |    7 +
>  drivers/watchdog/Makefile    |    1 +
>  drivers/watchdog/sp805_wdt.c |  386 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 394 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/watchdog/sp805_wdt.c
> 

Wim,

Is this patch fine or do i need to send V2?

viresh.


From kmpark at infradead.org  Fri Jun 11 00:25:18 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 11 Jun 2010 13:25:18 +0900
Subject: Pending patches for s5pc110
In-Reply-To: <AANLkTil0wWSFHpwi58enMhhG7475uUmFoZG6QhRim6Xk@mail.gmail.com>
References: <AANLkTil0wWSFHpwi58enMhhG7475uUmFoZG6QhRim6Xk@mail.gmail.com>
Message-ID: <AANLkTimjwSHLiMYFywn3vHZYCbqQCCCh9qE-n3xuYOaq@mail.gmail.com>

Hi,

No comments mean it's okay then we will prepare the patches to git pull.

Thank you,
Kyungmin Park

On Fri, Jun 4, 2010 at 8:53 AM, Kyungmin Park <kmpark at infradead.org> wrote:
> Hi ben,
>
> There's some pending patches for s5pc110.
> 1. aquila & goni support files.
> 2. keypad
> 3. s3c-fb - we have to implement FIMD and MIPI interface so please
> decide how to handle it.
> 4. etc.
>
> Do you want to re-post or any activities?
>
> Please give your plans or opinions.
>
> Thank you,
> Kyungmin Park
>


From srinidhi.kasagar at stericsson.com  Fri Jun 11 00:27:57 2010
From: srinidhi.kasagar at stericsson.com (srinidhi)
Date: Fri, 11 Jun 2010 09:57:57 +0530
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option
	for exceptions
In-Reply-To: <1275550613-9553-5-git-send-email-eric.miao@canonical.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
Message-ID: <1276230477.7920.481.camel@bnru03>

On Thu, 2010-06-03 at 09:36 +0200, Eric Miao wrote:

(...)

> +
> +config ZRELADDR
> +       hex "Physical address of the decompressed kernel image"
> +       depends on !AUTO_ZRELADDR
> +       default 0x00008000 if ARCH_BCMRING || ARCH_CNS3XXX || ARCH_DOVE ||\
> +                             ARCH_EBSA110 || ARCH_FOOTBRIDGE || ARCH_INTEGRATOR ||\
> +                             ARCH_IOP13XX || ARCH_IOP33X || ARCH_IXP2000 ||\
> +                             ARCH_IXP23XX || ARCH_IXP4XX || ARCH_KIRKWOOD ||\
> +                             ARCH_KS8695  || ARCH_LOKI || ARCH_MMP || ARCH_MV78XX0 ||\
> +                             ARCH_NOMADIK || ARCH_NUC93X || ARCH_NS9XXX ||\
> +                             ARCH_ORION5X || ARCH_SPEAR3XX || ARCH_SPEAR6XX ||\
> +                             ARCH_UX5XX || ARCH_VERSATILE || ARCH_W90X900

s/ARCH_UX5XX/ARCH_U8500

Srinidhi



From kyungmin.park at samsung.com  Fri Jun 11 00:34:52 2010
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Fri, 11 Jun 2010 13:34:52 +0900
Subject: [PATCH 1/3] s3c64xx: Fix build without SDHCI controllers
In-Reply-To: <000c01cb091a$675b2fa0$36118ee0$%kim@samsung.com>
References: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
	<1276076345-24370-2-git-send-email-m.szyprowski@samsung.com>
	<000801cb0900$f64bbdc0$e2e33940$%kim@samsung.com>
	<AANLkTimPp36K_SmFm053cu9f9Znb8SFHVcKAn8bjD1PI@mail.gmail.com>
	<000c01cb091a$675b2fa0$36118ee0$%kim@samsung.com>
Message-ID: <00a401cb091f$6f212370$4d636a50$%park@samsung.com>



> -----Original Message-----
> From: Kukjin Kim [mailto:kgene.kim at samsung.com]
> Sent: Friday, June 11, 2010 12:59 PM
> To: 'Kyungmin Park'
> Cc: 'Marek Szyprowski'; linux-arm-kernel at lists.infradead.org; linux-
> samsung-soc at vger.kernel.org; linux-mmc at vger.kernel.org; ben-
> linux at fluff.org
> Subject: RE: [PATCH 1/3] s3c64xx: Fix build without SDHCI controllers
> 
> Kyungmin Park wrote:
> >
> > On Fri, Jun 11, 2010 at 9:56 AM, Kukjin Kim <kgene.kim at samsung.com>
> wrote:
> > > Marek Szyprowski wrote:
> > >>
> > >> This patch fixes the following compilation problem if only NCP
> machine
> > >> is selected:
> > >>
> > >> arch/arm/mach-s3c64xx/s3c6410.c: In function ?s3c6410_map_io?:
> > >> arch/arm/mach-s3c64xx/s3c6410.c:51: error: implicit declaration of
> function
> > >> ?s3c6410_default_sdhci2?
> > >>
> > >> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> > >> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > >> ---
> > >>  arch/arm/plat-samsung/include/plat/sdhci.h |    1 +
> > >>  1 files changed, 1 insertions(+), 0 deletions(-)
> > >>
> > >> diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h
> b/arch/arm/plat-
> > >> samsung/include/plat/sdhci.h
> > >> index 13f9fb2..c2044e5 100644
> > >> --- a/arch/arm/plat-samsung/include/plat/sdhci.h
> > >> +++ b/arch/arm/plat-samsung/include/plat/sdhci.h
> > >> @@ -166,6 +166,7 @@ static inline void s3c6410_default_sdhci2(void)
> { }
> > >>  #else
> > >>  static inline void s3c6410_default_sdhci0(void) { }
> > >>  static inline void s3c6410_default_sdhci1(void) { }
> > >> +static inline void s3c6410_default_sdhci2(void) { }
> > >>  static inline void s3c6400_default_sdhci0(void) { }
> > >>  static inline void s3c6400_default_sdhci1(void) { }
> > >>
> > >> --
> > >
> > > Maybe missed in Maurus' patch 'S3C64XX: add HSMMC2 support'
> > > commit 92b118f6968ae0788ac659af47b464acd9a754a1
> >
> > Which kernel tree do you use?
> > it's against the latest kernel.
> >
> Of course, Linus' 35-rc2.

We used 63a07cb64ccc3ceae619d3298545d602ab5ecd38
And there's no s3c6410_default_sdhci2(void) .

Thank you,
Kyungmin Park

> Any problem?
> 
> > >
> > > Also need 'static inline s3c6400_default_sdhci2(void) { }'
> > > Could you re-submit updated patch including s3c6400_default_sdhci2()?
> > >
> 
> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.



From ben-linux at fluff.org  Fri Jun 11 00:20:46 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 05:20:46 +0100
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <1275636608.607067.417709988883.1.gpush@pororo>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<1275636608.607067.417709988883.1.gpush@pororo>
Message-ID: <20100611042046.GA31045@fluff.org.uk>

On Fri, Jun 04, 2010 at 03:30:08PM +0800, Jeremy Kerr wrote:
> We currently have 21 definitions of struct clk in the ARM architecture,
> each defined on a per-platform basis. This makes it difficult to define
> platform- (or architecture-) independent clock sources without making
> assumptions about struct clk, and impossible to compile two
> platforms with different struct clks into a single image.

Whilst I agree that this is a useful thing to do, I'd like to ensure
we get a good base for our work before we get another reason for Linus
to complain about churn.
 
> This change is an effort to unify struct clk where possible, by defining
> a common struct clk, containing a set of clock operations. Different
> clock implementations can set their own operations, and have a standard
> interface for generic code. The callback interface is exposed to the
> kernel proper, while the clock implementations only need to be seen by
> the platform internals.
> 
> This allows us to share clock code among platforms, and makes it
> possible to dynamically create clock devices in platform-independent
> code.
> 
> Platforms can enable the generic struct clock through
> CONFIG_USE_COMMON_STRUCT_CLK. In this case, the clock infrastructure
> consists of a common struct clk:

What do people think of just changing everyone who is currently using
clk support to using this new implementation?
 
> struct clk {
> 	const struct clk_ops	*ops;
> 	unsigned int		enable_count;
> 	struct mutex		mutex;

I'm a little worried about the size of struct clk if all of them
have a mutex in them. If i'm right, this is 40 bytes of data each
clock has to take on board.

Doing the following:

find arch/arm -type f -name "*.c" | xargs grep -c -E "struct.*clk.*=.*{" | grep -v ":0" | awk 'BEGIN { count=0; FS=":" }
count += $2; END { print count }'

indicates that there's approximately 2241 clocks under arch/arm at the
moment. That's about 87KiB of mutexes if all are being compiled at
once.

~> };
> 
> And a set of clock operations (defined per type of clock):
> 
> struct clk_operations {
>        int             (*enable)(struct clk *);
still think that not passing an bool as a second argument is silly.

>        void            (*disable)(struct clk *);
~>        unsigned long   (*get_rate)(struct clk *);
>        [...]
> };
> 
> To define a hardware-specific clock, machine code can "subclass" the
> struct clock into a new struct (adding any device-specific data), and
> provide a set of operations:
> 
> struct clk_foo {
> 	struct clk	clk;
> 	void __iomem	*some_register;
> };
> 
> struct clk_operations clk_foo_ops = {
> 	.get_rate = clk_foo_get_rate,
> };
> 
> The common clock definitions are based on a development patch from Ben
> Herrenschmidt <benh at kernel.crashing.org>.
> 
> Signed-off-by: Jeremy Kerr <jeremy.kerr at canonical.com>
> 
> ---
>  arch/Kconfig        |    3 
>  include/linux/clk.h |  159 ++++++++++++++++++++++++++++++++++++--------
>  2 files changed, 135 insertions(+), 27 deletions(-)
~~~~> 
> diff --git a/arch/Kconfig b/arch/Kconfig
> index acda512..2458b5e 100644
> --- a/arch/Kconfig
> +++ b/arch/Kconfig
> @@ -151,4 +151,7 @@ config HAVE_MIXED_BREAKPOINTS_REGS
>  config HAVE_USER_RETURN_NOTIFIER
>  	bool
>  
> +config USE_COMMON_STRUCT_CLK
> +	bool
> +
>  source "kernel/gcov/Kconfig"
> diff --git a/include/linux/clk.h b/include/linux/clk.h
> index 1d37f42..bb6957a 100644
> --- a/include/linux/clk.h
> +++ b/include/linux/clk.h
> @@ -3,6 +3,7 @@
>   *
>   *  Copyright (C) 2004 ARM Limited.
>   *  Written by Deep Blue Solutions Limited.
> + *  Copyright (c) 2010 Jeremy Kerr <jeremy.kerr at canonical.com>
>   *
>   * This program is free software; you can redistribute it and/or modify
>   * it under the terms of the GNU General Public License version 2 as
> @@ -11,36 +12,125 @@
>  #ifndef __LINUX_CLK_H
>  #define __LINUX_CLK_H
>  
> -struct device;
> +#include <linux/err.h>
> +#include <linux/mutex.h>
>  
> -/*
> - * The base API.
> +#ifdef CONFIG_USE_COMMON_STRUCT_CLK
> +
> +/* If we're using the common struct clk, we define the base clk object here,
> + * which will be 'subclassed' by device-specific implementations. For example:
> + *
> + *  struct clk_foo {
> + *      struct clk;
> + *      [device specific fields]
> + *  };
> + *
> + * We define the common clock API through a set of static inlines that call the
> + * corresponding clk_operations. The API is exactly the same as that documented
> + * in the !CONFIG_USE_COMMON_STRUCT_CLK case.
>   */
>  
> +struct clk {
> +	const struct clk_ops	*ops;
> +	unsigned int		enable_count;
> +	struct mutex		mutex;
> +};

how about defining a nice kerneldoc for this.

> +#define INIT_CLK(name, o) \
> +	{ .ops = &o, .enable_count = 0, \
> +		.mutex = __MUTEX_INITIALIZER(name.mutex) }

how about doing the mutex initinitialisation at registration
time, will save a pile of non-zero code in the image to mess up
the compression.

~> +struct clk_ops {
> +       int             (*enable)(struct clk *);
> +       void            (*disable)(struct clk *);
> +       unsigned long   (*get_rate)(struct clk *);
> +       void            (*put)(struct clk *);
> +       long            (*round_rate)(struct clk *, unsigned long);
> +       int             (*set_rate)(struct clk *, unsigned long);
> +       int             (*set_parent)(struct clk *, struct clk *);
> +       struct clk*     (*get_parent)(struct clk *);

should each clock carry a parent field and the this is returned by
the get parent call.~~

> +};
> +
> +static inline int clk_enable(struct clk *clk)
> +{
> +	int ret = 0;
> +
> +	if (!clk->ops->enable)
> +		return 0;
> +
> +	mutex_lock(&clk->mutex);
> +	if (!clk->enable_count)
> +		ret = clk->ops->enable(clk);
> +
> +	if (!ret)
> +		clk->enable_count++;
> +	mutex_unlock(&clk->mutex);
> +
> +	return ret;
> +}

So we're leaving the enable parent code now to each implementation?

I think this is a really bad decision, it leaves so much open to bad
code repetition, as well as something the core should really be doing
if it had a parent clock field.

~> +static inline void clk_disable(struct clk *clk)
> +{
> +	if (!clk->ops->enable)
> +		return;

so if we've no enable call we ignore disable too?

also, we don't keep an enable count if this fields are in use,
could people rely on this being correct even if the clock has
no enable/disable fields.

Would much rather see the enable_count being kept up-to-date
no matter what, given it may be watched by other parts of the
implementation, useful for debug info, and possibly useful if
later in the start sequence the clk_ops get changed to have this
field.~

> +~	mutex_lock(&clk->mutex);
> +
> +	if (!--clk->enable_count)
> +		clk->ops->disable(clk);
> +
> +	mutex_unlock(&clk->mutex);
> +}
> +
> +static inline unsigned long clk_get_rate(struct clk *clk)
> +{
> +	if (clk->ops->get_rate)
> +		return clk->ops->get_rate(clk);
> +	return 0;
> +}
> +
> +static inline void clk_put(struct clk *clk)
> +{
> +	if (clk->ops->put)
> +		clk->ops->put(clk);
> +}

I'm beginging to wonder if we don't just have a set of default ops
that get set into the clk+ops at registration time if these do
not have an implementation.
~
> +static inline long clk_round_rate(struct clk *clk, unsigned long rate)
> +{
> +	if (clk->ops->round_rate)
> +		return clk->ops->round_rate(clk, rate);
> +	return -ENOSYS;
> +}
> +
> +static inline int clk_set_rate(struct clk *clk, unsigned long rate)
>~ +{
> +	if (clk->ops->set_rate)
> +		return clk->ops->set_rate(clk, rate);
> +	return -ENOSYS;
> +}
> +
> +static inline int clk_set_parent(struct clk *clk, struct clk *parent)
> +{
> +	if (clk->ops->set_parent)
> +		return clk->ops->set_parent(clk, parent);
> +	return -ENOSYS;
> +}

We have an interesting problem here which I belive should be dealt
with, what happens when the clock's parent is changed with respect
to the enable count of the parent.

With the following instance:

	we have clocks a, b, c;
	a and b are possible parents for c;
	c starts off with a as parent

then the driver comes along:

	1) gets clocks a, b, c;
	2) clk_enable(c);
	3) clk_set_parent(c, b);
	
now we have the following:

	A) clk a now has an enable count of non-zero
	B) clk b may not be enabled
	C) even though clk a may now be unused, it is still running
	D) even though clk c was enabled, it isn't running since step3

this means that either any driver that is using a multi-parent clock
has to deal with the proper enable/disable of the parents (this is
is going to lead to code repetition, and I bet people will get it
badly wrong).

I belive the core of the clock code should deal with this, since
otherwise we end up with the situation of the same code being
repeated throughout the kernel.

> +static inline struct clk *clk_get_parent(struct clk *clk)
> +{
> +	if (clk->ops->get_parent)
> +		return clk->ops->get_parent(clk);
> +	return ERR_PTR(-ENOSYS);
> +}
>
> +#else /* !CONFIG_USE_COMMON_STRUCT_CLK */
>  
>  /*
> - * struct clk - an machine class defined object / cookie.
> + * Global clock object, actual structure is declared per-machine
>   */
>  struct clk;
>  
>  /**
> - * clk_get - lookup and obtain a reference to a clock producer.
> - * @dev: device for clock "consumer"
> - * @id: clock comsumer ID
> - *
> - * Returns a struct clk corresponding to the clock producer, or
> - * valid IS_ERR() condition containing errno.  The implementation
> - * uses @dev and @id to determine the clock consumer, and thereby
~> - * the clock producer.  (IOW, @id may be identical strings, but
> - * clk_get may return different clock producers depending on @dev.)
> - *
> - * Drivers must assume that the clock source is not enabled.
> - *
> - * clk_get should not be called from within interrupt context.
> - */
> -struct clk *clk_get(struct device *dev, const char *id);
> -
> -/**
>   * clk_enable - inform the system when the clock source should be running.
>   * @clk: clock source
>   *
> @@ -83,12 +173,6 @@ unsigned long clk_get_rate(struct clk *clk);
>   */
>  void clk_put(struct clk *clk);
>  
> -
> -/*
> - * The remaining APIs are optional for machine class support.
> - */
> -
> -
>  /**
>   * clk_round_rate - adjust a rate to the exact rate a clock can provide
>   * @clk: clock source
> @@ -125,6 +209,27 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
>   */
>  struct clk *clk_get_parent(struct clk *clk);
>  
> +#endif /* !CONFIG_USE_COMMON_STRUCT_CLK */
> +
> +struct device;
> +
> +/**
> + * clk_get - lookup and obtain a reference to a clock producer.
> + * @dev: device for clock "consumer"
> + * @id: clock comsumer ID
> + *
> + * Returns a struct clk corresponding to the clock producer, or
> + * valid IS_ERR() condition containing errno.  The implementation
> + * uses @dev and @id to determine the clock consumer, and thereby
> + * the clock producer.  (IOW, @id may be identical strings, but
> + * clk_get may return different clock producers depending on @dev.)
> + *
> + * Drivers must assume that the clock source is not enabled.
> + *
> + * clk_get should not be called from within interrupt context.
~~> + */
> +struct clk *clk_get(struct device *dev, const char *id);
> +
>  /**
>   * clk_get_sys - get a clock based upon the device name
>   * @dev_id: device name
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

-- 
Ben (ben at fluff.org, http://www.fluff.org/)

  'a smiley only costs 4 bytes'


From u.kleine-koenig at pengutronix.de  Fri Jun 11 00:55:07 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 11 Jun 2010 06:55:07 +0200
Subject: [PATCH 0/5] Makefile.boot cleanup
In-Reply-To: <alpine.LFD.2.00.1006101442130.30664@xanadu.home>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<20100603075704.GB336@pengutronix.de>
	<alpine.LFD.2.00.1006101442130.30664@xanadu.home>
Message-ID: <20100611045507.GA10894@pengutronix.de>

On Thu, Jun 10, 2010 at 02:44:53PM -0400, Nicolas Pitre wrote:
> On Thu, 3 Jun 2010, Uwe Kleine-K?nig wrote:
> 
> > Hello Eric,
> > 
> > On Thu, Jun 03, 2010 at 03:36:48PM +0800, Eric Miao wrote:
> > > Several facts:
> > > 
> > > 1. ZRELADDR in most cases can be auto detected by maksing PC with
> > >    0xf000_0000 if the zImage is placed within the first 256MiB from
> > >    the memory start, which is a sane assumption except for:
> > > 
> > >    - when ARCH_MX1 or ARCH_SHARK is defined
> > >    - when ARCH_U300 is defined (U300 really is strange when defining
> > >      PHYS_OFFSET and ZRELADDR)
> > >    - or when ZBOOT_ROM is defined
> > If you guess ZRELADDR based on sp instead of pc it even should work if
> > ZBOOT_ROM is defined?!
> 
> If you're using ZBOOT_ROM that means you want to execute zImage directly 
> from ROM.  This is therefore a highly customized configuration.  In that 
> context, having a variable phys-offset doesn't make much sense to start 
> with.
Right, but then the kernel needs to know this fixed value for
phys-offset.  In the patches presented by Eric the person configuring
the kernel needs to know that value.  When guessing based on sp she
doesn't need to read addional docs when enabling ZBOOT_ROM.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From ben-linux at fluff.org  Fri Jun 11 01:15:21 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 06:15:21 +0100
Subject: Pending patches for s5pc110
In-Reply-To: <AANLkTimjwSHLiMYFywn3vHZYCbqQCCCh9qE-n3xuYOaq@mail.gmail.com>
References: <AANLkTil0wWSFHpwi58enMhhG7475uUmFoZG6QhRim6Xk@mail.gmail.com>
	<AANLkTimjwSHLiMYFywn3vHZYCbqQCCCh9qE-n3xuYOaq@mail.gmail.com>
Message-ID: <20100611051521.GV7248@trinity.fluff.org>

On Fri, Jun 11, 2010 at 01:25:18PM +0900, Kyungmin Park wrote:
> Hi,
> 
> No comments mean it's okay then we will prepare the patches to git pull.

No. no comments means that people either haven't had time to sort
them out or in fact ON HOLIDAY.
 
> Thank you,
> Kyungmin Park
> 
> On Fri, Jun 4, 2010 at 8:53 AM, Kyungmin Park <kmpark at infradead.org> wrote:
> > Hi ben,
> >
> > There's some pending patches for s5pc110.
> > 1. aquila & goni support files.

these two should have gone in already

> > 2. keypad

I think kukjin has been looking at this, best check with him.

> > 3. s3c-fb - we have to implement FIMD and MIPI interface so please
> > decide how to handle it.

since we've not had any chance to discuss what is going on here
I can't see how we are ready to submit anything.

> > 4. etc.
> >
> > Do you want to re-post or any activities?
> >
> > Please give your plans or opinions.
> >
> > Thank you,
> > Kyungmin Park
> >
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From ben-linux at fluff.org  Fri Jun 11 01:18:25 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 06:18:25 +0100
Subject: [PATCH 3/3] s5pv210: Aquila: add definitions for sdhci devices
In-Reply-To: <1276076345-24370-4-git-send-email-m.szyprowski@samsung.com>
References: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
	<1276076345-24370-4-git-send-email-m.szyprowski@samsung.com>
Message-ID: <20100611051825.GW7248@trinity.fluff.org>

On Wed, Jun 09, 2010 at 11:39:05AM +0200, Marek Szyprowski wrote:
> This patch add support for SDHCI blocks on Samsung Aquila board. The
> following host controllers are defined:
> 1. Internal MoviNAND device (permanently wired to the controller)
> 2. Internal WiFI SDIO device (card is activated by power regualor)
> 3. External MMC/SD socket (card detection is provided by external
> gpio interrupt)
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-s5pv210/Kconfig       |    4 ++
>  arch/arm/mach-s5pv210/mach-aquila.c |   66 +++++++++++++++++++++++++++++++++++
>  2 files changed, 70 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
> index b7a2f38..dcc9d74 100644
> --- a/arch/arm/mach-s5pv210/Kconfig
> +++ b/arch/arm/mach-s5pv210/Kconfig
> @@ -57,7 +57,11 @@ config MACH_AQUILA
>  	select CPU_S5PV210
>  	select ARCH_SPARSEMEM_ENABLE
>  	select S5PV210_SETUP_FB_24BPP
> +	select S5PV210_SETUP_SDHCI
>  	select S3C_DEV_FB
> +	select S3C_DEV_HSMMC
> +	select S3C_DEV_HSMMC1
> +	select S3C_DEV_HSMMC2
>  	select S5PC110_DEV_ONENAND
>  	help
>  	  Machine support for the Samsung Aquila target based on S5PC110 SoC
> diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
> index fb9dbb2..1b7fe79 100644
> --- a/arch/arm/mach-s5pv210/mach-aquila.c
> +++ b/arch/arm/mach-s5pv210/mach-aquila.c
> @@ -13,6 +13,7 @@
>  #include <linux/init.h>
>  #include <linux/serial_core.h>
>  #include <linux/fb.h>
> +#include <linux/gpio.h>
>  
>  #include <asm/mach/arch.h>
>  #include <asm/mach/map.h>
> @@ -22,12 +23,15 @@
>  #include <mach/map.h>
>  #include <mach/regs-clock.h>
>  #include <mach/regs-fb.h>
> +#include <mach/regs-gpio.h>
>  
>  #include <plat/regs-serial.h>
>  #include <plat/s5pv210.h>
>  #include <plat/devs.h>
>  #include <plat/cpu.h>
>  #include <plat/fb.h>
> +#include <plat/gpio-cfg.h>
> +#include <plat/sdhci.h>
>  
>  /* Following are default values for UCON, ULCON and UFCON UART registers */
>  #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
> @@ -116,9 +120,66 @@ static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
>  	.setup_gpio	= s5pv210_fb_gpio_setup_24bpp,
>  };
>  
> +/* MoviNAND */
> +static struct s3c_sdhci_platdata aquila_hsmmc0_data __initdata = {
> +	.max_width		= 4,
> +	.cd_type		= S3C_SDHCI_CD_PERMANENT,
> +};
> +
> +/* Wireless LAN */
> +static struct s3c_sdhci_platdata aquila_hsmmc1_data __initdata = {
> +	.max_width		= 4,
> +	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
> +	/* ext_cd_{init,cleanup} callbacks will be added later */
> +};
> +
> +/* External Flash */
> +#define AQUILA_EXT_FLASH_IRQ	IRQ_EINT(28)	/* S5PV210_GPH3(4) */
> +#define AQUILA_EXT_FLASH_EN	S5PV210_MP05(4)
> +#define AQUILA_EXT_FLASH_CD	S5PV210_GPH3(4)
> +
> +static irqreturn_t aquila_ext_flash_card_detect_isr(int irq, void *dev_id)
> +{
> +	void (*notify_func)(struct platform_device *, int state) = dev_id;
> +	notify_func(&s3c_device_hsmmc2, !gpio_get_value(AQUILA_EXT_FLASH_CD));
> +	return IRQ_HANDLED;
> +}

hmm, not very nice this.

I'd much prefer to see a gpio-based handler in either the sdhci core or
at-least in the driver's directory since I'm sure that his is (a) something
Thomas Abrahama has already published patches for (which do need work) and
(b) probably going to be needed by other boards and/or other architectures.

> +static int aquila_ext_flash_card_detect_init(
> +		void (*notify_func)(struct platform_device *, int state))
> +{
> +	gpio_request(AQUILA_EXT_FLASH_EN, "FLASH_EN");
> +	gpio_direction_output(AQUILA_EXT_FLASH_EN, 1);
> +
> +	if (request_irq(AQUILA_EXT_FLASH_IRQ, aquila_ext_flash_card_detect_isr,
> +				IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
> +				"SDHCI card detect", notify_func))
> +		printk(KERN_ERR "Error: cannot request irq for External Flash\n");
> +	return 0;
> +}
> +
> +static int aquila_ext_flash_card_detect_cleanup(
> +		void (*notify_func)(struct platform_device *, int state))
> +{
> +	free_irq(AQUILA_EXT_FLASH_IRQ, notify_func);
> +	gpio_direction_output(AQUILA_EXT_FLASH_EN, 0);
> +	gpio_free(AQUILA_EXT_FLASH_EN);
> +	return 0;
> +}
> +
> +static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = {
> +	.max_width		= 4,
> +	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
> +	.ext_cd_init		= aquila_ext_flash_card_detect_init,
> +	.ext_cd_cleanup		= aquila_ext_flash_card_detect_cleanup,
> +};
> +
>  static struct platform_device *aquila_devices[] __initdata = {
>  	&s3c_device_fb,
>  	&s5pc110_device_onenand,
> +	&s3c_device_hsmmc0,
> +	&s3c_device_hsmmc1,
> +	&s3c_device_hsmmc2,
>  };
>  
>  static void __init aquila_map_io(void)
> @@ -130,6 +191,11 @@ static void __init aquila_map_io(void)
>  
>  static void __init aquila_machine_init(void)
>  {
> +	/* SDHCI */
> +	s3c_sdhci0_set_platdata(&aquila_hsmmc0_data);
> +	s3c_sdhci1_set_platdata(&aquila_hsmmc1_data);
> +	s3c_sdhci2_set_platdata(&aquila_hsmmc2_data);
> +
>  	/* FB */
>  	s3c_fb_set_platdata(&aquila_lcd_pdata);
>  
> -- 
> 1.7.1.240.g225c
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From ben-linux at fluff.org  Fri Jun 11 01:24:07 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 06:24:07 +0100
Subject: [PATCH 1/5] sdhci-s3c: depend on plat-samsung
In-Reply-To: <000701cb08fd$2f8e15a0$8eaa40e0$%kim@samsung.com>
References: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
	<1276076383-24825-2-git-send-email-m.szyprowski@samsung.com>
	<000701cb08fd$2f8e15a0$8eaa40e0$%kim@samsung.com>
Message-ID: <20100611052407.GX7248@trinity.fluff.org>

On Fri, Jun 11, 2010 at 09:29:38AM +0900, Kukjin Kim wrote:
> Marek Szyprowski wrote:
> > 
> > Most Samsung SoC have support for SDHCI block, so make the driver
> > dependent on the Samsung platform instead on listing all SoCs in the
> > Kconfig (and updating it again when support for the new SoC variant is
> > added).
> > 
> Hi, Marek
> 
> Kyungmin Park already submitted same patch.

Hmm, Mr Park and Co really need to learn how to handle the treatment of
patches. I'm really disapointed that these patches get submitted without
the proper authour accreditation. If this isn't sorted out then I for
one will start thinking about giving this stuff an automatic reject.

Please ensure that the original authour of a patch is accredited for
the work, and the right sign-off and any other ack data is kept with
the patch. There's documentation about most of this in the kernel
already at Documentation/SubmittingPatches.
 
> And Andrew Morton added to the -mm tree.
> http://www.spinics.net/lists/mm-commits/msg79159.html
> 
> But, I think your comment is better...
> 
> > Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> >  drivers/mmc/host/Kconfig |    2 +-
> >  1 files changed, 1 insertions(+), 1 deletions(-)
> > 
> > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> > index e171e77..acf5bf6 100644
> > --- a/drivers/mmc/host/Kconfig
> > +++ b/drivers/mmc/host/Kconfig
> > @@ -123,7 +123,7 @@ config MMC_SDHCI_PLTFM
> > 
> >  config MMC_SDHCI_S3C
> >  	tristate "SDHCI support on Samsung S3C SoC"
> > -	depends on MMC_SDHCI && (PLAT_S3C24XX || PLAT_S3C64XX)
> > +	depends on MMC_SDHCI && PLAT_SAMSUNG
> >  	help
> >  	  This selects the Secure Digital Host Controller Interface (SDHCI)
> >  	  often referrered to as the HSMMC block in some of the Samsung S3C
> > --
> 
> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From m.szyprowski at samsung.com  Fri Jun 11 01:29:27 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 11 Jun 2010 07:29:27 +0200
Subject: [PATCH 3/3] s5pv210: Aquila: add definitions for sdhci devices
In-Reply-To: <20100611051825.GW7248@trinity.fluff.org>
References: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
	<1276076345-24370-4-git-send-email-m.szyprowski@samsung.com>
	<20100611051825.GW7248@trinity.fluff.org>
Message-ID: <005a01cb0927$120e4250$362ac6f0$%szyprowski@samsung.com>

Hello,

On Friday, June 11, 2010 7:18 AM Ben Dooks wrote:

> On Wed, Jun 09, 2010 at 11:39:05AM +0200, Marek Szyprowski wrote:
> > This patch add support for SDHCI blocks on Samsung Aquila board. The
> > following host controllers are defined:
> > 1. Internal MoviNAND device (permanently wired to the controller)
> > 2. Internal WiFI SDIO device (card is activated by power regualor)
> > 3. External MMC/SD socket (card detection is provided by external
> > gpio interrupt)
> >
> > Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> >  arch/arm/mach-s5pv210/Kconfig       |    4 ++
> >  arch/arm/mach-s5pv210/mach-aquila.c |   66
> +++++++++++++++++++++++++++++++++++
> >  2 files changed, 70 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-
> s5pv210/Kconfig
> > index b7a2f38..dcc9d74 100644
> > --- a/arch/arm/mach-s5pv210/Kconfig
> > +++ b/arch/arm/mach-s5pv210/Kconfig
> > @@ -57,7 +57,11 @@ config MACH_AQUILA
> >  	select CPU_S5PV210
> >  	select ARCH_SPARSEMEM_ENABLE
> >  	select S5PV210_SETUP_FB_24BPP
> > +	select S5PV210_SETUP_SDHCI
> >  	select S3C_DEV_FB
> > +	select S3C_DEV_HSMMC
> > +	select S3C_DEV_HSMMC1
> > +	select S3C_DEV_HSMMC2
> >  	select S5PC110_DEV_ONENAND
> >  	help
> >  	  Machine support for the Samsung Aquila target based on S5PC110 SoC
> > diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-
> s5pv210/mach-aquila.c
> > index fb9dbb2..1b7fe79 100644
> > --- a/arch/arm/mach-s5pv210/mach-aquila.c
> > +++ b/arch/arm/mach-s5pv210/mach-aquila.c
> > @@ -13,6 +13,7 @@
> >  #include <linux/init.h>
> >  #include <linux/serial_core.h>
> >  #include <linux/fb.h>
> > +#include <linux/gpio.h>
> >
> >  #include <asm/mach/arch.h>
> >  #include <asm/mach/map.h>
> > @@ -22,12 +23,15 @@
> >  #include <mach/map.h>
> >  #include <mach/regs-clock.h>
> >  #include <mach/regs-fb.h>
> > +#include <mach/regs-gpio.h>
> >
> >  #include <plat/regs-serial.h>
> >  #include <plat/s5pv210.h>
> >  #include <plat/devs.h>
> >  #include <plat/cpu.h>
> >  #include <plat/fb.h>
> > +#include <plat/gpio-cfg.h>
> > +#include <plat/sdhci.h>
> >
> >  /* Following are default values for UCON, ULCON and UFCON UART registers
> */
> >  #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
> > @@ -116,9 +120,66 @@ static struct s3c_fb_platdata aquila_lcd_pdata
> __initdata = {
> >  	.setup_gpio	= s5pv210_fb_gpio_setup_24bpp,
> >  };
> >
> > +/* MoviNAND */
> > +static struct s3c_sdhci_platdata aquila_hsmmc0_data __initdata = {
> > +	.max_width		= 4,
> > +	.cd_type		= S3C_SDHCI_CD_PERMANENT,
> > +};
> > +
> > +/* Wireless LAN */
> > +static struct s3c_sdhci_platdata aquila_hsmmc1_data __initdata = {
> > +	.max_width		= 4,
> > +	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
> > +	/* ext_cd_{init,cleanup} callbacks will be added later */
> > +};
> > +
> > +/* External Flash */
> > +#define AQUILA_EXT_FLASH_IRQ	IRQ_EINT(28)	/* S5PV210_GPH3(4) */
> > +#define AQUILA_EXT_FLASH_EN	S5PV210_MP05(4)
> > +#define AQUILA_EXT_FLASH_CD	S5PV210_GPH3(4)
> > +
> > +static irqreturn_t aquila_ext_flash_card_detect_isr(int irq, void
> *dev_id)
> > +{
> > +	void (*notify_func)(struct platform_device *, int state) = dev_id;
> > +	notify_func(&s3c_device_hsmmc2, !gpio_get_value(AQUILA_EXT_FLASH_CD));
> > +	return IRQ_HANDLED;
> > +}
> 
> hmm, not very nice this.
> 
> I'd much prefer to see a gpio-based handler in either the sdhci core or
> at-least in the driver's directory since I'm sure that his is (a) something
> Thomas Abrahama has already published patches for (which do need work) and
> (b) probably going to be needed by other boards and/or other architectures.

I thought about adding the external gpio logic directly to sdhci-s3c driver,
but then I realized that it would not cover all our cases. For wifi sdio
card we need different solution - the card will be 'inserted' and 'removed'
by a power regulator glue code (called by rfkill framework). I'm really
convinced that adding support for such special case to sdhci-s3c driver is
not a good idea, that's why I came with the idea of 'external event' support
for card detect. I can move support for the gpio case to the sdhci-s3c driver
(it will be just a new CD type - SDHCI_S3C_GPIO).

I'm really open for the discussion how this can be handled in other ways.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center




From wim at iguana.be  Fri Jun 11 01:30:49 2010
From: wim at iguana.be (Wim Van Sebroeck)
Date: Fri, 11 Jun 2010 07:30:49 +0200
Subject: [PATCH resend] Watchdog: Adding support for ARM Primecell
	SP805 Watchdog
In-Reply-To: <4C11B711.70907@st.com>
References: <1275465783-14052-1-git-send-email-viresh.kumar@st.com>
	<4C11B711.70907@st.com>
Message-ID: <20100611053049.GM3788@infomag.iguana.be>

Hi Viresh,

Still need to look at it. First finishing up another project.
Probably for this weekend.

Kind regards,
Wim.

> On 6/2/2010 1:33 PM, Viresh KUMAR wrote:
> > Technical Reference Manual can be found at:
> > http://infocenter.arm.com/help/topic/com.arm.doc.ddi0270b/DDI0270.pdf
> > 
> > Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
> > ---
> >  drivers/watchdog/Kconfig     |    7 +
> >  drivers/watchdog/Makefile    |    1 +
> >  drivers/watchdog/sp805_wdt.c |  386 ++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 394 insertions(+), 0 deletions(-)
> >  create mode 100644 drivers/watchdog/sp805_wdt.c
> > 
> 
> Wim,
> 
> Is this patch fine or do i need to send V2?
> 
> viresh.


From ben-linux at fluff.org  Fri Jun 11 01:32:34 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 06:32:34 +0100
Subject: [PATCH 0/6] Various s3c-fb updates
In-Reply-To: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
Message-ID: <20100611053234.GE14272@trinity.fluff.org>

On Mon, May 31, 2010 at 11:08:49AM +0200, Pawel Osciak wrote:
> Hello,
> 
> This series is rebased onto Ben Dook's framebuffer branch available at:
> git://git.fluff.org/bjdooks/linux.git dev/s3c-fb

I'll look at updating this series once I am back in the uk, it mostly
looks good but I have yet to do any testing or give it a thorough
review.
 
> The main changes are the addition of an ability to wait for VSYNC and
> display panning.
> 
> The first patch attempts to fix some NULL pointer dereferences in case
> of a failed framebuffer memory allocation attempt. This is a quick
> fix, so please treat it more as an indication of what may be wrong
> with the code in the probe function and not as something to merge.
> 
> Patches 3-4 add "new style" device name initialization for various
> S3C/S5P devices. The 4th patch also separates S5PC100 and S5PV210 as
> their framebuffer registers sets differ.
> 
> 
> [PATCH 1/6] s3c-fb: Fix various null references on framebuffer memory alloc failure
> [PATCH 2/6] s3c-fb: Correct FRAMESEL1 bitfield defines for VIDINTCON0 register
> [PATCH 3/6] s3c-fb: Add device name initialization.
> [PATCH 4/6] s3c-fb: Separate S5PC100 and S5PV210 framebuffer driver data structures
> [PATCH 5/6] s3c-fb: Add support for display panning
> [PATCH 6/6] s3c-fb: Add wait for VSYNC ioctl
> 
> Best regards
> --
> Pawel Osciak
> Linux Platform Group
> Samsung Poland R&D Center
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From kmpark at infradead.org  Fri Jun 11 01:38:56 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 11 Jun 2010 14:38:56 +0900
Subject: Pending patches for s5pc110
In-Reply-To: <20100611051521.GV7248@trinity.fluff.org>
References: <AANLkTil0wWSFHpwi58enMhhG7475uUmFoZG6QhRim6Xk@mail.gmail.com>
	<AANLkTimjwSHLiMYFywn3vHZYCbqQCCCh9qE-n3xuYOaq@mail.gmail.com>
	<20100611051521.GV7248@trinity.fluff.org>
Message-ID: <AANLkTikJQnDEjVunmiCLGaVAnj5bR7JdsUZYJ9xAEdE5@mail.gmail.com>

On Fri, Jun 11, 2010 at 2:15 PM, Ben Dooks <ben-linux at fluff.org> wrote:
> On Fri, Jun 11, 2010 at 01:25:18PM +0900, Kyungmin Park wrote:
>> Hi,
>>
>> No comments mean it's okay then we will prepare the patches to git pull.
>
> No. no comments means that people either haven't had time to sort
> them out or in fact ON HOLIDAY.

but you usually missed our patches frequently. with this reason our
patches can't merge within proper merge window.

>
>> Thank you,
>> Kyungmin Park
>>
>> On Fri, Jun 4, 2010 at 8:53 AM, Kyungmin Park <kmpark at infradead.org> wrote:
>> > Hi ben,
>> >
>> > There's some pending patches for s5pc110.
>> > 1. aquila & goni support files.
>
> these two should have gone in already

I mean more aquila & goni patches. not basic support. e.g. OneNAND
support, FB support and so on.
>
>> > 2. keypad
>
> I think kukjin has been looking at this, best check with him.

It's already discussed. do you think it needs more comments?

>
>> > 3. s3c-fb - we have to implement FIMD and MIPI interface so please
>> > decide how to handle it.
>
> since we've not had any chance to discuss what is going on here
> I can't see how we are ready to submit anything.

It's basic functionality for s3c-fb. it's required for our target and
want to use it. even though someone don't use it.

I wonder some features are not used for other board. in this case it
should be merged if it doesn't break any previous board. Of course
with proper feedback. I think we answer your question doesn't it?

Thank you,
Kyungmin Park

>
>> > 4. etc.
>> >
>> > Do you want to re-post or any activities?
>> >
>> > Please give your plans or opinions.
>> >
>> > Thank you,
>> > Kyungmin Park
>> >
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
> --
> Ben
>
> Q: ? ? ?What's a light-year?
> A: ? ? ?One-third less calories than a regular year.
>
>


From kyungmin.park at samsung.com  Fri Jun 11 01:42:07 2010
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Fri, 11 Jun 2010 14:42:07 +0900
Subject: [PATCH 1/5] sdhci-s3c: depend on plat-samsung
In-Reply-To: <20100611052407.GX7248@trinity.fluff.org>
References: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
	<1276076383-24825-2-git-send-email-m.szyprowski@samsung.com>
	<000701cb08fd$2f8e15a0$8eaa40e0$%kim@samsung.com>
	<20100611052407.GX7248@trinity.fluff.org>
Message-ID: <AANLkTildPiWp2BZvTm8sOvaMy1gRSTH8RHqvZQRdYP6-@mail.gmail.com>

On Fri, Jun 11, 2010 at 2:24 PM, Ben Dooks <ben-linux at fluff.org> wrote:
> On Fri, Jun 11, 2010 at 09:29:38AM +0900, Kukjin Kim wrote:
>> Marek Szyprowski wrote:
>> >
>> > Most Samsung SoC have support for SDHCI block, so make the driver
>> > dependent on the Samsung platform instead on listing all SoCs in the
>> > Kconfig (and updating it again when support for the new SoC variant is
>> > added).
>> >
>> Hi, Marek
>>
>> Kyungmin Park already submitted same patch.
>
> Hmm, Mr Park and Co really need to learn how to handle the treatment of
> patches. I'm really disapointed that these patches get submitted without
> the proper authour accreditation. If this isn't sorted out then I for
> one will start thinking about giving this stuff an automatic reject.

It's just Marek missed the previous my patch, and I reply there's
duplicated patch already.

Thank you,
Kyungmin Park

>
> Please ensure that the original authour of a patch is accredited for
> the work, and the right sign-off and any other ack data is kept with
> the patch. There's documentation about most of this in the kernel
> already at Documentation/SubmittingPatches.
>
>> And Andrew Morton added to the -mm tree.
>> http://www.spinics.net/lists/mm-commits/msg79159.html
>>
>> But, I think your comment is better...
>>
>> > Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
>> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>> > ---
>> > ?drivers/mmc/host/Kconfig | ? ?2 +-
>> > ?1 files changed, 1 insertions(+), 1 deletions(-)
>> >
>> > diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> > index e171e77..acf5bf6 100644
>> > --- a/drivers/mmc/host/Kconfig
>> > +++ b/drivers/mmc/host/Kconfig
>> > @@ -123,7 +123,7 @@ config MMC_SDHCI_PLTFM
>> >
>> > ?config MMC_SDHCI_S3C
>> > ? ? tristate "SDHCI support on Samsung S3C SoC"
>> > - ? depends on MMC_SDHCI && (PLAT_S3C24XX || PLAT_S3C64XX)
>> > + ? depends on MMC_SDHCI && PLAT_SAMSUNG
>> > ? ? help
>> > ? ? ? This selects the Secure Digital Host Controller Interface (SDHCI)
>> > ? ? ? often referrered to as the HSMMC block in some of the Samsung S3C
>> > --
>>
>>
>> Thanks.
>>
>> Best regards,
>> Kgene.
>> --
>> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
>> SW Solution Development Team, Samsung Electronics Co., Ltd.
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
> --
> Ben
>
> Q: ? ? ?What's a light-year?
> A: ? ? ?One-third less calories than a regular year.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From kmpark at infradead.org  Fri Jun 11 01:52:56 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 11 Jun 2010 14:52:56 +0900
Subject: [PATCH 2/2] MAINTAINERS: add maintainer for SAMSUNG ARM 
	ARCHITECTURES
In-Reply-To: <AANLkTinpth-JO7pIOWXbnuUWXM3xQ1OnFKkfESwi0cP3@mail.gmail.com>
References: <1275647794-30634-1-git-send-email-kgene.kim@samsung.com>
	<1275647794-30634-2-git-send-email-kgene.kim@samsung.com>
	<AANLkTinpth-JO7pIOWXbnuUWXM3xQ1OnFKkfESwi0cP3@mail.gmail.com>
Message-ID: <AANLkTikygrbXPkszVvBpH217mOaY8UzJE8zcOGVTGRZo@mail.gmail.com>

Ping.

On Sat, Jun 5, 2010 at 11:24 AM, Kyungmin Park <kmpark at infradead.org> wrote:
> Hi Ben,
>
> I'm waiting your comments.
>
> Thank you,
> Kyungmin Park
>
> On Fri, Jun 4, 2010 at 7:36 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
>> ---
>> ?MAINTAINERS | ? ?2 ++
>> ?1 files changed, 2 insertions(+), 0 deletions(-)
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 1d41149..f4e4c61 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -896,11 +896,13 @@ S: ? ? ? ?Maintained
>>
>> ?ARM/SAMSUNG ARM ARCHITECTURES
>> ?M: ? ? Ben Dooks <ben-linux at fluff.org>
>> +M: ? ? Kukjin Kim <kgene.kim at samsung.com>
>> ?L: ? ? linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
>> ?W: ? ? http://www.fluff.org/ben/linux/
>> ?S: ? ? Maintained
>> ?F: ? ? arch/arm/plat-samsung/
>> ?F: ? ? arch/arm/plat-s3c24xx/
>> +F: ? ? arch/arm/plat-s5p/
>>
>> ?ARM/S3C2410 ARM ARCHITECTURE
>> ?M: ? ? Ben Dooks <ben-linux at fluff.org>
>> --
>> 1.6.2.5
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>


From m.szyprowski at samsung.com  Fri Jun 11 01:59:01 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 11 Jun 2010 07:59:01 +0200
Subject: [PATCH v2] s3c64xx: Fix build without SDHCI controllers
In-Reply-To: <000801cb0900$f64bbdc0$e2e33940$%kim@samsung.com>
References: <000801cb0900$f64bbdc0$e2e33940$%kim@samsung.com>
Message-ID: <1276235941-12114-1-git-send-email-m.szyprowski@samsung.com>

This patch fixes the following compilation problem if only NCP machine
is selected:

arch/arm/mach-s3c64xx/s3c6410.c: In function ?s3c6410_map_io?:
arch/arm/mach-s3c64xx/s3c6410.c:51: error: implicit declaration of function ?s3c6410_default_sdhci2?

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-samsung/include/plat/sdhci.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 13f9fb2..2e263a8 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -166,8 +166,10 @@ static inline void s3c6410_default_sdhci2(void) { }
 #else
 static inline void s3c6410_default_sdhci0(void) { }
 static inline void s3c6410_default_sdhci1(void) { }
+static inline void s3c6410_default_sdhci2(void) { }
 static inline void s3c6400_default_sdhci0(void) { }
 static inline void s3c6400_default_sdhci1(void) { }
+static inline void s3c6400_default_sdhci2(void) { }
 
 #endif /* CONFIG_S3C64XX_SETUP_SDHCI */
 
-- 
1.7.1.240.g225c



From kmpark at infradead.org  Fri Jun 11 02:05:32 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 11 Jun 2010 15:05:32 +0900
Subject: [PATCH 3/3] s5pv210: Aquila: add definitions for sdhci devices
In-Reply-To: <20100611051825.GW7248@trinity.fluff.org>
References: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
	<1276076345-24370-4-git-send-email-m.szyprowski@samsung.com>
	<20100611051825.GW7248@trinity.fluff.org>
Message-ID: <AANLkTil5a4B4Yk31MnEtCc80-645x09ZvCOCHcyIY-vS@mail.gmail.com>

On Fri, Jun 11, 2010 at 2:18 PM, Ben Dooks <ben-linux at fluff.org> wrote:
> On Wed, Jun 09, 2010 at 11:39:05AM +0200, Marek Szyprowski wrote:
>> This patch add support for SDHCI blocks on Samsung Aquila board. The
>> following host controllers are defined:
>> 1. Internal MoviNAND device (permanently wired to the controller)
>> 2. Internal WiFI SDIO device (card is activated by power regualor)
>> 3. External MMC/SD socket (card detection is provided by external
>> gpio interrupt)
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>> ---
>> ?arch/arm/mach-s5pv210/Kconfig ? ? ? | ? ?4 ++
>> ?arch/arm/mach-s5pv210/mach-aquila.c | ? 66 +++++++++++++++++++++++++++++++++++
>> ?2 files changed, 70 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
>> index b7a2f38..dcc9d74 100644
>> --- a/arch/arm/mach-s5pv210/Kconfig
>> +++ b/arch/arm/mach-s5pv210/Kconfig
>> @@ -57,7 +57,11 @@ config MACH_AQUILA
>> ? ? ? select CPU_S5PV210
>> ? ? ? select ARCH_SPARSEMEM_ENABLE
>> ? ? ? select S5PV210_SETUP_FB_24BPP
>> + ? ? select S5PV210_SETUP_SDHCI
>> ? ? ? select S3C_DEV_FB
>> + ? ? select S3C_DEV_HSMMC
>> + ? ? select S3C_DEV_HSMMC1
>> + ? ? select S3C_DEV_HSMMC2
>> ? ? ? select S5PC110_DEV_ONENAND
>> ? ? ? help
>> ? ? ? ? Machine support for the Samsung Aquila target based on S5PC110 SoC
>> diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
>> index fb9dbb2..1b7fe79 100644
>> --- a/arch/arm/mach-s5pv210/mach-aquila.c
>> +++ b/arch/arm/mach-s5pv210/mach-aquila.c
>> @@ -13,6 +13,7 @@
>> ?#include <linux/init.h>
>> ?#include <linux/serial_core.h>
>> ?#include <linux/fb.h>
>> +#include <linux/gpio.h>
>>
>> ?#include <asm/mach/arch.h>
>> ?#include <asm/mach/map.h>
>> @@ -22,12 +23,15 @@
>> ?#include <mach/map.h>
>> ?#include <mach/regs-clock.h>
>> ?#include <mach/regs-fb.h>
>> +#include <mach/regs-gpio.h>
>>
>> ?#include <plat/regs-serial.h>
>> ?#include <plat/s5pv210.h>
>> ?#include <plat/devs.h>
>> ?#include <plat/cpu.h>
>> ?#include <plat/fb.h>
>> +#include <plat/gpio-cfg.h>
>> +#include <plat/sdhci.h>
>>
>> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
>> ?#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | ? ? ? ?\
>> @@ -116,9 +120,66 @@ static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
>> ? ? ? .setup_gpio ? ? = s5pv210_fb_gpio_setup_24bpp,
>> ?};
>>
>> +/* MoviNAND */
>> +static struct s3c_sdhci_platdata aquila_hsmmc0_data __initdata = {
>> + ? ? .max_width ? ? ? ? ? ? ?= 4,
>> + ? ? .cd_type ? ? ? ? ? ? ? ?= S3C_SDHCI_CD_PERMANENT,
>> +};
>> +
>> +/* Wireless LAN */
>> +static struct s3c_sdhci_platdata aquila_hsmmc1_data __initdata = {
>> + ? ? .max_width ? ? ? ? ? ? ?= 4,
>> + ? ? .cd_type ? ? ? ? ? ? ? ?= S3C_SDHCI_CD_EXTERNAL,
>> + ? ? /* ext_cd_{init,cleanup} callbacks will be added later */
>> +};
>> +
>> +/* External Flash */
>> +#define AQUILA_EXT_FLASH_IRQ IRQ_EINT(28) ? ?/* S5PV210_GPH3(4) */
>> +#define AQUILA_EXT_FLASH_EN ?S5PV210_MP05(4)
>> +#define AQUILA_EXT_FLASH_CD ?S5PV210_GPH3(4)
>> +
>> +static irqreturn_t aquila_ext_flash_card_detect_isr(int irq, void *dev_id)
>> +{
>> + ? ? void (*notify_func)(struct platform_device *, int state) = dev_id;
>> + ? ? notify_func(&s3c_device_hsmmc2, !gpio_get_value(AQUILA_EXT_FLASH_CD));
>> + ? ? return IRQ_HANDLED;
>> +}
>
> hmm, not very nice this.
>
> I'd much prefer to see a gpio-based handler in either the sdhci core or
> at-least in the driver's directory since I'm sure that his is (a) something
> Thomas Abrahama has already published patches for (which do need work) and

Maybe you see the samsung internal codes. but I think the baseline is
mailing list, others are implement the same functionality with
different place. can you tell me which mail has these one?

Thank you,
Kyungmin Park

> (b) probably going to be needed by other boards and/or other architectures.


>
>> +static int aquila_ext_flash_card_detect_init(
>> + ? ? ? ? ? ? void (*notify_func)(struct platform_device *, int state))
>> +{
>> + ? ? gpio_request(AQUILA_EXT_FLASH_EN, "FLASH_EN");
>> + ? ? gpio_direction_output(AQUILA_EXT_FLASH_EN, 1);
>> +
>> + ? ? if (request_irq(AQUILA_EXT_FLASH_IRQ, aquila_ext_flash_card_detect_isr,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? "SDHCI card detect", notify_func))
>> + ? ? ? ? ? ? printk(KERN_ERR "Error: cannot request irq for External Flash\n");
>> + ? ? return 0;
>> +}
>> +
>> +static int aquila_ext_flash_card_detect_cleanup(
>> + ? ? ? ? ? ? void (*notify_func)(struct platform_device *, int state))
>> +{
>> + ? ? free_irq(AQUILA_EXT_FLASH_IRQ, notify_func);
>> + ? ? gpio_direction_output(AQUILA_EXT_FLASH_EN, 0);
>> + ? ? gpio_free(AQUILA_EXT_FLASH_EN);
>> + ? ? return 0;
>> +}
>> +
>> +static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = {
>> + ? ? .max_width ? ? ? ? ? ? ?= 4,
>> + ? ? .cd_type ? ? ? ? ? ? ? ?= S3C_SDHCI_CD_EXTERNAL,
>> + ? ? .ext_cd_init ? ? ? ? ? ?= aquila_ext_flash_card_detect_init,
>> + ? ? .ext_cd_cleanup ? ? ? ? = aquila_ext_flash_card_detect_cleanup,
>> +};
>> +
>> ?static struct platform_device *aquila_devices[] __initdata = {
>> ? ? ? &s3c_device_fb,
>> ? ? ? &s5pc110_device_onenand,
>> + ? ? &s3c_device_hsmmc0,
>> + ? ? &s3c_device_hsmmc1,
>> + ? ? &s3c_device_hsmmc2,
>> ?};
>>
>> ?static void __init aquila_map_io(void)
>> @@ -130,6 +191,11 @@ static void __init aquila_map_io(void)
>>
>> ?static void __init aquila_machine_init(void)
>> ?{
>> + ? ? /* SDHCI */
>> + ? ? s3c_sdhci0_set_platdata(&aquila_hsmmc0_data);
>> + ? ? s3c_sdhci1_set_platdata(&aquila_hsmmc1_data);
>> + ? ? s3c_sdhci2_set_platdata(&aquila_hsmmc2_data);
>> +
>> ? ? ? /* FB */
>> ? ? ? s3c_fb_set_platdata(&aquila_lcd_pdata);
>>
>> --
>> 1.7.1.240.g225c
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
> --
> Ben
>
> Q: ? ? ?What's a light-year?
> A: ? ? ?One-third less calories than a regular year.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>


From kgene.kim at samsung.com  Fri Jun 11 02:18:13 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 11 Jun 2010 15:18:13 +0900
Subject: Pending patches for s5pc110
In-Reply-To: <AANLkTikJQnDEjVunmiCLGaVAnj5bR7JdsUZYJ9xAEdE5@mail.gmail.com>
References: <AANLkTil0wWSFHpwi58enMhhG7475uUmFoZG6QhRim6Xk@mail.gmail.com>
	<AANLkTimjwSHLiMYFywn3vHZYCbqQCCCh9qE-n3xuYOaq@mail.gmail.com>
	<20100611051521.GV7248@trinity.fluff.org>
	<AANLkTikJQnDEjVunmiCLGaVAnj5bR7JdsUZYJ9xAEdE5@mail.gmail.com>
Message-ID: <002f01cb092d$e1728c30$a457a490$%kim@samsung.com>

Kyungmin Park wrote:
> 
> On Fri, Jun 11, 2010 at 2:15 PM, Ben Dooks <ben-linux at fluff.org> wrote:
> > On Fri, Jun 11, 2010 at 01:25:18PM +0900, Kyungmin Park wrote:
> >> Hi,
> >>
> >> No comments mean it's okay then we will prepare the patches to git pull.
> >
Maybe you already know no comments do not mean it's okay.

> > No. no comments means that people either haven't had time to sort
> > them out or in fact ON HOLIDAY.
> 
> but you usually missed our patches frequently. with this reason our
> patches can't merge within proper merge window.
> 
> >
> >> Thank you,
> >> Kyungmin Park
> >>
> >> On Fri, Jun 4, 2010 at 8:53 AM, Kyungmin Park <kmpark at infradead.org>
wrote:
> >> > Hi ben,
> >> >
> >> > There's some pending patches for s5pc110.
> >> > 1. aquila & goni support files.
> >
> > these two should have gone in already
> 
> I mean more aquila & goni patches. not basic support. e.g. OneNAND
> support, FB support and so on.
> >
> >> > 2. keypad
> >
> > I think kukjin has been looking at this, best check with him.
> 
> It's already discussed. do you think it needs more comments?
> 
You mean discussed to me?
Sorry, I can't remember when we discussed about that, what's my comments?

> >
> >> > 3. s3c-fb - we have to implement FIMD and MIPI interface so please
> >> > decide how to handle it.
> >
> > since we've not had any chance to discuss what is going on here
> > I can't see how we are ready to submit anything.
> 
> It's basic functionality for s3c-fb. it's required for our target and
> want to use it. even though someone don't use it.
> 
> I wonder some features are not used for other board. in this case it
> should be merged if it doesn't break any previous board. Of course
> with proper feedback. I think we answer your question doesn't it?
> 
> Thank you,
> Kyungmin Park
> 
> >
> >> > 4. etc.
> >> >
> >> > Do you want to re-post or any activities?
> >> >
> >> > Please give your plans or opinions.
> >> >
> >> > Thank you,
> >> > Kyungmin Park
> >> >
> >>


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From ben-linux at fluff.org  Fri Jun 11 02:23:00 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 07:23:00 +0100
Subject: Pending patches for s5pc110
In-Reply-To: <AANLkTikJQnDEjVunmiCLGaVAnj5bR7JdsUZYJ9xAEdE5@mail.gmail.com>
References: <AANLkTil0wWSFHpwi58enMhhG7475uUmFoZG6QhRim6Xk@mail.gmail.com>
	<AANLkTimjwSHLiMYFywn3vHZYCbqQCCCh9qE-n3xuYOaq@mail.gmail.com>
	<20100611051521.GV7248@trinity.fluff.org>
	<AANLkTikJQnDEjVunmiCLGaVAnj5bR7JdsUZYJ9xAEdE5@mail.gmail.com>
Message-ID: <20100611062300.GY7248@trinity.fluff.org>

On Fri, Jun 11, 2010 at 02:38:56PM +0900, Kyungmin Park wrote:
> On Fri, Jun 11, 2010 at 2:15 PM, Ben Dooks <ben-linux at fluff.org> wrote:
> > On Fri, Jun 11, 2010 at 01:25:18PM +0900, Kyungmin Park wrote:
> >> Hi,
> >>
> >> No comments mean it's okay then we will prepare the patches to git pull.
> >
> > No. no comments means that people either haven't had time to sort
> > them out or in fact ON HOLIDAY.
> 
> but you usually missed our patches frequently. with this reason our
> patches can't merge within proper merge window.

I belive the last set where either being posted just-before or during
the last merge window. We already had far too much queueud up then and
we where trying to ensure that the already-queued entries where processed.

The last call for updates went out on 13th May, and the two machine
patches actually turned up on the 30th of May...

It is important that we get these merges ready at least a week in
advance of the merge window, otherwise there is _no_ time time to test
the merged trees, and even worse there is little time to correct any
mistakes... there where I belive two merge problems with trying to
rebuild trees at the last minute ready to send to Linus.

Unfortunately the S5PC100 moves did get overlooked (I think I may ended
up dropping off the samsung-soc list) and the ended up producing a lot
of the work involved in generating the pull request to RMK and then
Linus. (see http://thread.gmane.org/gmane.linux.kernel.samsung-soc/1427)

If we can organise ourselves better (and Kukjin will be taking over some
of this work) then maybe we will have a much better experience for the
next time.

> >
> >> Thank you,
> >> Kyungmin Park
> >>
> >> On Fri, Jun 4, 2010 at 8:53 AM, Kyungmin Park <kmpark at infradead.org> wrote:
> >> > Hi ben,
> >> >
> >> > There's some pending patches for s5pc110.
> >> > 1. aquila & goni support files.
> >
> > these two should have gone in already
> 
> I mean more aquila & goni patches. not basic support. e.g. OneNAND
> support, FB support and so on.

As above, I belive these where rather late on the horizon to be included.

> >> > 2. keypad
> >
> > I think kukjin has been looking at this, best check with him.
> 
> It's already discussed. do you think it needs more comments?

Me, no. I think if Kukjin has no problems then it is up to Dimitry
whether he wants to merge it.
 
> >
> >> > 3. s3c-fb - we have to implement FIMD and MIPI interface so please
> >> > decide how to handle it.
> >
> > since we've not had any chance to discuss what is going on here
> > I can't see how we are ready to submit anything.
> 
> It's basic functionality for s3c-fb. it's required for our target and
> want to use it. even though someone don't use it.
> 
> I wonder some features are not used for other board. in this case it
> should be merged if it doesn't break any previous board. Of course
> with proper feedback. I think we answer your question doesn't it?

The fb system is currently without a propler maintainer and Andrew Morton
has been doing the job of applying patches. I don't know the reasons for
the last round of development not going in, but it was probably due to it
being too late.. I've so far been unable to actually subscribe to the new
fb list to try and sort it out.

This however doesn't cover the fact that there's been no movement on
dicsussing what is needed to support FIMC addition to the framebuffer
driver.

Do you have even a list of things that you think are needed for this, or
any actual patches we could look at and discuss?

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From kgene.kim at samsung.com  Fri Jun 11 02:26:32 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 11 Jun 2010 15:26:32 +0900
Subject: [PATCH 1/3] s3c64xx: Fix build without SDHCI controllers
In-Reply-To: <00a401cb091f$6f212370$4d636a50$%park@samsung.com>
References: <1276076345-24370-1-git-send-email-m.szyprowski@samsung.com>
	<1276076345-24370-2-git-send-email-m.szyprowski@samsung.com>
	<000801cb0900$f64bbdc0$e2e33940$%kim@samsung.com>
	<AANLkTimPp36K_SmFm053cu9f9Znb8SFHVcKAn8bjD1PI@mail.gmail.com>
	<000c01cb091a$675b2fa0$36118ee0$%kim@samsung.com>
	<00a401cb091f$6f212370$4d636a50$%park@samsung.com>
Message-ID: <003001cb092f$0b4b53b0$21e1fb10$%kim@samsung.com>


> -----Original Message-----
> From: Kyungmin Park [mailto:kyungmin.park at samsung.com]
> Sent: Friday, June 11, 2010 1:35 PM
> To: 'Kukjin Kim'
> Cc: 'Marek Szyprowski'; linux-arm-kernel at lists.infradead.org; linux-samsung-
> soc at vger.kernel.org; linux-mmc at vger.kernel.org; ben-linux at fluff.org
> Subject: RE: [PATCH 1/3] s3c64xx: Fix build without SDHCI controllers
> 
> 
> 
> > -----Original Message-----
> > From: Kukjin Kim [mailto:kgene.kim at samsung.com]
> > Sent: Friday, June 11, 2010 12:59 PM
> > To: 'Kyungmin Park'
> > Cc: 'Marek Szyprowski'; linux-arm-kernel at lists.infradead.org; linux-
> > samsung-soc at vger.kernel.org; linux-mmc at vger.kernel.org; ben-
> > linux at fluff.org
> > Subject: RE: [PATCH 1/3] s3c64xx: Fix build without SDHCI controllers
> >
> > Kyungmin Park wrote:
> > >
> > > On Fri, Jun 11, 2010 at 9:56 AM, Kukjin Kim <kgene.kim at samsung.com>
> > wrote:
> > > > Marek Szyprowski wrote:
> > > >>
> > > >> This patch fixes the following compilation problem if only NCP
> > machine
> > > >> is selected:
> > > >>
> > > >> arch/arm/mach-s3c64xx/s3c6410.c: In function ?s3c6410_map_io?:
> > > >> arch/arm/mach-s3c64xx/s3c6410.c:51: error: implicit declaration of
> > function
> > > >> ?s3c6410_default_sdhci2?
> > > >>
> > > >> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> > > >> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > > >> ---
> > > >>  arch/arm/plat-samsung/include/plat/sdhci.h |    1 +
> > > >>  1 files changed, 1 insertions(+), 0 deletions(-)
> > > >>
> > > >> diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h
> > b/arch/arm/plat-
> > > >> samsung/include/plat/sdhci.h
> > > >> index 13f9fb2..c2044e5 100644
> > > >> --- a/arch/arm/plat-samsung/include/plat/sdhci.h
> > > >> +++ b/arch/arm/plat-samsung/include/plat/sdhci.h
> > > >> @@ -166,6 +166,7 @@ static inline void s3c6410_default_sdhci2(void)
> > { }
> > > >>  #else
> > > >>  static inline void s3c6410_default_sdhci0(void) { }
> > > >>  static inline void s3c6410_default_sdhci1(void) { }
> > > >> +static inline void s3c6410_default_sdhci2(void) { }
> > > >>  static inline void s3c6400_default_sdhci0(void) { }
> > > >>  static inline void s3c6400_default_sdhci1(void) { }
> > > >>
> > > >> --
> > > >
> > > > Maybe missed in Maurus' patch 'S3C64XX: add HSMMC2 support'
> > > > commit 92b118f6968ae0788ac659af47b464acd9a754a1
> > >
> > > Which kernel tree do you use?
> > > it's against the latest kernel.
> > >
> > Of course, Linus' 35-rc2.
> 
> We used 63a07cb64ccc3ceae619d3298545d602ab5ecd38
> And there's no s3c6410_default_sdhci2(void) .
> 
Hmm. Maybe some misunderstanding.

I meant maybe Maurus missed when he submitted HSMMC2 support patch.
(it means Marek's patch is correct)
And need 's3c6400_default_sdhci2()' as well as 's36410_default_sdhci2()' in Marek's patch.
So requested to re-submit updated patch.

> 
> > Any problem?
> >
> > > >
> > > > Also need 'static inline s3c6400_default_sdhci2(void) { }'
> > > > Could you re-submit updated patch including s3c6400_default_sdhci2()?
> > > >
> >
> >


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From u.kleine-koenig at pengutronix.de  Fri Jun 11 02:37:33 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 11 Jun 2010 08:37:33 +0200
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option
	for exceptions
In-Reply-To: <AANLkTiltifSEFdpXB0avw4ZyDzP_IrDpipafBAJbN17U@mail.gmail.com>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
	<AANLkTiltifSEFdpXB0avw4ZyDzP_IrDpipafBAJbN17U@mail.gmail.com>
Message-ID: <20100611063733.GB10894@pengutronix.de>

Hello Linus,

On Fri, Jun 11, 2010 at 12:17:44AM +0200, Linus Walleij wrote:
> I assume it should be submitted simultaneously with a patch nuking off
> all Makefile.boot files and that infrastructure then?
Only when bootp is deleted or fixed not to use these variables.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From ext-mika.1.westerberg at nokia.com  Fri Jun 11 02:36:05 2010
From: ext-mika.1.westerberg at nokia.com (Mika Westerberg)
Date: Fri, 11 Jun 2010 09:36:05 +0300
Subject: [PATCH v2 0/8] Initial implementation of kdump for ARM
In-Reply-To: <20100525081937.GA11783@esdhcp04058.research.nokia.com>
References: <cover.1273041357.git.ext-mika.1.westerberg@nokia.com>
	<20100525081937.GA11783@esdhcp04058.research.nokia.com>
Message-ID: <20100611063605.GB11156@esdhcp04058.research.nokia.com>

On Tue, May 25, 2010 at 11:19:37AM +0300, Mika Westerberg wrote:
> On Wed, May 05, 2010 at 08:54:12AM +0200, Westerberg Mika.1 (EXT-Nixu/Helsinki) wrote:
> > 
> > This is re-send of the series. I didn't receive any comments on this but we
> > found few minor things during in-house review which are incorporated.
> > 
> > Changes to v1:
> > 	- corrected kernel-doc for crash_setup_regs()
> > 	- check return value of ioremap() in copy_oldmem_page()
> > 
> > Changes to RFC version:
> > 	- crash_setup_regs() uses Russell's suggestion for saving registers
> > 	- copy_oldmem_page() code is changed to use ioremap()
> > 	- there is no need for special 'mem=' parameters
> > 
> > I've tested this on N900 and beagleboard.
> 
> Hi Russell,
> 
> Sorry to bother you with this but I wasn't sure what is going to happen with
> these patches. Are you planning to take them or do you want me to change
> something?
> 
> I already submitted these to your patch system as I didn't receive much
> comments (not sure was this the right thing to do, however).
> 
> In addition, I tested these on ep93xx based Sim.One board and they seem to work
> there as well.

Ping..

Do you have any plans for these patches? The reason I'm asking is that there are
also userspace tools (namely makedumpfile and crash) which are needed for
post-mortem analysis, and they depend on kernel support. Without support in
mainline it makes little sense to port these to ARM.

As ARM is going to use LMB I know that patch 6116/1 "kdump: reserve memory for
crashkernel" needs to be changed to use LMB instead of bootmem but that change
should be quite simple.

So do you think I should rework these patches or may they be included in .36? It
would be nice to know if any changes are needed.

Thanks again,
MW


From marek.vasut at gmail.com  Fri Jun 11 02:45:39 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 11 Jun 2010 08:45:39 +0200
Subject: [PATCH 1/2] ARM/scoop: Add CPR register bit definitions
Message-ID: <1276238740-10640-1-git-send-email-marek.vasut@gmail.com>

Add bit definitions of the CPR register of the SCOOP chip into scoop.h

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/include/asm/hardware/scoop.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h
index 46492a6..5821f21 100644
--- a/arch/arm/include/asm/hardware/scoop.h
+++ b/arch/arm/include/asm/hardware/scoop.h
@@ -22,6 +22,11 @@
 #define SCOOP_GPWR 0x24
 #define SCOOP_GPRR 0x28
 
+#define SCOOP_CPR_OUT	( 1 << 7 )
+#define SCOOP_CPR_SD_3V	( 1 << 2 )
+#define SCOOP_CPR_CF_XV	( 1 << 1 )
+#define SCOOP_CPR_CF_3V	( 1 << 0 )
+
 #define SCOOP_GPCR_PA22	( 1 << 12 )
 #define SCOOP_GPCR_PA21	( 1 << 11 )
 #define SCOOP_GPCR_PA20	( 1 << 10 )
-- 
1.7.1



From marek.vasut at gmail.com  Fri Jun 11 02:45:40 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 11 Jun 2010 08:45:40 +0200
Subject: [PATCH 2/2] pxa/spitz: Rework spitz
In-Reply-To: <1276238740-10640-1-git-send-email-marek.vasut@gmail.com>
References: <1276238740-10640-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1276238740-10640-2-git-send-email-marek.vasut@gmail.com>

This huge patch mostly shuffles code. The spitz.c file contained terrible mess
and needed a cleanup, here it is:

1) Made every part modular, components are not built in if not selected.
2) Removed loads of preprocessor goo, mostly "#ifdef MACH_AKITA .... #endif" and
   similar code. The kernel size will grow by a few kb now, but the file is much
   more readable.
3) Reworked SD/CF power setting function and made it reentrant.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/include/mach/spitz.h |    2 -
 arch/arm/mach-pxa/spitz.c              |  748 ++++++++++++++++++--------------
 2 files changed, 420 insertions(+), 330 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index fa1998c..685749a 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
@@ -185,7 +185,5 @@
 /*
  * Shared data structures
  */
-extern struct platform_device spitzscoop_device;
-extern struct platform_device spitzscoop2_device;
 extern struct platform_device spitzssp_device;
 extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 4d2413e..bf6a7d4 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -18,12 +18,12 @@
 #include <linux/gpio_keys.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
-#include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/spi/corgi_lcd.h>
+#include <linux/mtd/physmap.h>
 #include <linux/mtd/sharpsl.h>
 #include <linux/input/matrix_keypad.h>
 
@@ -33,11 +33,9 @@
 #include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/scoop.h>
 
-
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/reset.h>
-#include <plat/i2c.h>
 #include <mach/irda.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
@@ -45,11 +43,16 @@
 #include <mach/pxa2xx_spi.h>
 #include <mach/spitz.h>
 
+#include <plat/i2c.h>
+
 #include "generic.h"
 #include "devices.h"
 #include "sharpsl.h"
 
-static unsigned long spitz_pin_config[] __initdata = {
+/******************************************************************************
+ * Pin configuration
+ ******************************************************************************/
+static unsigned long sharpslc_pin_config[] __initdata = {
 	/* Chip Selects */
 	GPIO78_nCS_2,	/* SCOOP #2 */
 	GPIO79_nCS_3,	/* NAND */
@@ -124,10 +127,13 @@ static unsigned long spitz_pin_config[] __initdata = {
 	GPIO1_GPIO | WAKEUP_ON_EDGE_FALL,	/* SPITZ_GPIO_RESET */
 };
 
-/*
- * Spitz SCOOP Device #1
- */
-static struct resource spitz_scoop_resources[] = {
+
+/******************************************************************************
+ * Scoop GPIO expander
+ ******************************************************************************/
+#if defined(CONFIG_SHARP_SCOOP) || defined(CONFIG_SHARP_SCOOP_MODULE)
+/* SCOOP Device #1 */
+static struct resource sharpslc_scoop_1_resources[] = {
 	[0] = {
 		.start		= 0x10800000,
 		.end		= 0x10800fff,
@@ -135,7 +141,7 @@ static struct resource spitz_scoop_resources[] = {
 	},
 };
 
-static struct scoop_config spitz_scoop_setup = {
+static struct scoop_config sharpslc_scoop_1_setup = {
 	.io_dir		= SPITZ_SCP_IO_DIR,
 	.io_out		= SPITZ_SCP_IO_OUT,
 	.suspend_clr	= SPITZ_SCP_SUS_CLR,
@@ -143,20 +149,18 @@ static struct scoop_config spitz_scoop_setup = {
 	.gpio_base	= SPITZ_SCP_GPIO_BASE,
 };
 
-struct platform_device spitzscoop_device = {
+struct platform_device sharpslc_scoop_1_device = {
 	.name		= "sharp-scoop",
 	.id		= 0,
 	.dev		= {
- 		.platform_data	= &spitz_scoop_setup,
+ 		.platform_data	= &sharpslc_scoop_1_setup,
 	},
-	.num_resources	= ARRAY_SIZE(spitz_scoop_resources),
-	.resource	= spitz_scoop_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_scoop_1_resources),
+	.resource	= sharpslc_scoop_1_resources,
 };
 
-/*
- * Spitz SCOOP Device #2
- */
-static struct resource spitz_scoop2_resources[] = {
+/* SCOOP Device #2 */
+static struct resource sharpslc_scoop_2_resources[] = {
 	[0] = {
 		.start		= 0x08800040,
 		.end		= 0x08800fff,
@@ -164,7 +168,7 @@ static struct resource spitz_scoop2_resources[] = {
 	},
 };
 
-static struct scoop_config spitz_scoop2_setup = {
+static struct scoop_config sharpslc_scoop_2_setup = {
 	.io_dir		= SPITZ_SCP2_IO_DIR,
 	.io_out		= SPITZ_SCP2_IO_OUT,
 	.suspend_clr	= SPITZ_SCP2_SUS_CLR,
@@ -172,82 +176,110 @@ static struct scoop_config spitz_scoop2_setup = {
 	.gpio_base	= SPITZ_SCP2_GPIO_BASE,
 };
 
-struct platform_device spitzscoop2_device = {
+struct platform_device sharpslc_scoop_2_device = {
 	.name		= "sharp-scoop",
 	.id		= 1,
 	.dev		= {
- 		.platform_data	= &spitz_scoop2_setup,
+ 		.platform_data	= &sharpslc_scoop_2_setup,
 	},
-	.num_resources	= ARRAY_SIZE(spitz_scoop2_resources),
-	.resource	= spitz_scoop2_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_scoop_2_resources),
+	.resource	= sharpslc_scoop_2_resources,
 };
 
-#define SPITZ_PWR_SD 0x01
-#define SPITZ_PWR_CF 0x02
+static void __init sharpslc_scoop_init(void)
+{
+	platform_device_register(&sharpslc_scoop_1_device);
+
+	/* Akita doesn't have the second SCOOP chip */
+	if (!machine_is_akita())
+		platform_device_register(&sharpslc_scoop_2_device);
+}
 
 /* Power control is shared with between one of the CF slots and SD */
-static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr)
+static void sharpslc_card_pwr_ctrl(int enable, unsigned short new_cpr)
 {
-	unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR);
+	unsigned short cpr;
+	unsigned long flags;
 
-	if (new_cpr & 0x0007) {
+	if (new_cpr & 0x7) {
 		gpio_set_value(SPITZ_GPIO_CF_POWER, 1);
-		if (!(cpr & 0x0002) && !(cpr & 0x0004))
-		        mdelay(5);
-		if (device == SPITZ_PWR_CF)
-		        cpr |= 0x0002;
-		if (device == SPITZ_PWR_SD)
-		        cpr |= 0x0004;
-	        write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
-	} else {
-		if (device == SPITZ_PWR_CF)
-		        cpr &= ~0x0002;
-		if (device == SPITZ_PWR_SD)
-		        cpr &= ~0x0004;
-		if (!(cpr & 0x0002) && !(cpr & 0x0004)) {
-			write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, 0x0000);
-		        mdelay(1);
-			gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
-		} else {
-		        write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
-		}
+		mdelay(5);
+	}
+		
+	local_irq_save(flags);
+
+	cpr = read_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR);
+
+	if (enable & new_cpr)
+		cpr |= new_cpr;
+	else
+		cpr &= ~enable;
+
+        write_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR, cpr);
+
+	local_irq_restore(flags);
+
+	if (!(cpr & 0x7)) {
+	        mdelay(1);
+		gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
 	}
 }
 
-static void spitz_pcmcia_pwr(struct device *scoop, unsigned short cpr, int nr)
+#else
+static inline void sharpslc_scoop_init(void) {}
+static inline void sharpslc_card_pwr_ctrl(int device, unsigned short new_cpr) {}
+#endif
+
+/******************************************************************************
+ * PCMCIA
+ ******************************************************************************/
+#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
+static void sharpslc_pcmcia_pwr(struct device *scoop, unsigned short cpr, int nr)
 {
 	/* Only need to override behaviour for slot 0 */
 	if (nr == 0)
-		spitz_card_pwr_ctrl(SPITZ_PWR_CF, cpr);
+		sharpslc_card_pwr_ctrl(
+			cpr & (SCOOP_CPR_CF_3V | SCOOP_CPR_CF_XV), cpr);
 	else
 		write_scoop_reg(scoop, SCOOP_CPR, cpr);
 }
 
-static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
-{
-	.dev        = &spitzscoop_device.dev,
-	.irq        = SPITZ_IRQ_GPIO_CF_IRQ,
-	.cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
-	.cd_irq_str = "PCMCIA0 CD",
-},{
-	.dev        = &spitzscoop2_device.dev,
-	.irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
-	.cd_irq     = -1,
-},
+static struct scoop_pcmcia_dev sharpslc_pcmcia_scoop[] = {
+	{
+		.dev        = &sharpslc_scoop_1_device.dev,
+		.irq        = SPITZ_IRQ_GPIO_CF_IRQ,
+		.cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
+		.cd_irq_str = "PCMCIA0 CD",
+	},{
+		.dev        = &sharpslc_scoop_2_device.dev,
+		.irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
+		.cd_irq     = -1,
+	},
 };
 
-static struct scoop_pcmcia_config spitz_pcmcia_config = {
-	.devs         = &spitz_pcmcia_scoop[0],
-	.num_devs     = 2,
-	.power_ctrl   = spitz_pcmcia_pwr,
+static struct scoop_pcmcia_config sharpslc_pcmcia_config = {
+	.devs		= &sharpslc_pcmcia_scoop[0],
+	.num_devs	= 2,
+	.power_ctrl	= sharpslc_pcmcia_pwr,
 };
 
-EXPORT_SYMBOL(spitzscoop_device);
-EXPORT_SYMBOL(spitzscoop2_device);
+static void __init sharpslc_pcmcia_init(void)
+{
+	/* Akita has only one PCMCIA slot used */
+	if (machine_is_akita())
+		sharpslc_pcmcia_config.num_devs = 1;
+
+	platform_scoop_config = &sharpslc_pcmcia_config;
+}
+#else
+static inline void sharpslc_pcmcia_init(void) {}
+#endif
+
+/******************************************************************************
+ * GPIO keyboard
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
 
-/*
- * Spitz Keyboard Device
- */
 #define SPITZ_KEY_CALENDAR	KEY_F1
 #define SPITZ_KEY_ADDRESS	KEY_F2
 #define SPITZ_KEY_FN		KEY_F3
@@ -263,7 +295,7 @@ EXPORT_SYMBOL(spitzscoop2_device);
 #define SPITZ_KEY_OK		KEY_F11
 #define SPITZ_KEY_MENU		KEY_F12
 
-static const uint32_t spitzkbd_keymap[] = {
+static const uint32_t sharpslc_keymap[] = {
 	KEY(0, 0, KEY_LEFTCTRL),
 	KEY(0, 1, KEY_1),
 	KEY(0, 2, KEY_3),
@@ -330,37 +362,48 @@ static const uint32_t spitzkbd_keymap[] = {
 	KEY(6, 8, KEY_RIGHT),
 };
 
-static const struct matrix_keymap_data spitzkbd_keymap_data = {
-	.keymap		= spitzkbd_keymap,
-	.keymap_size	= ARRAY_SIZE(spitzkbd_keymap),
+static const struct matrix_keymap_data sharpslc_keymap_data = {
+	.keymap		= sharpslc_keymap,
+	.keymap_size	= ARRAY_SIZE(sharpslc_keymap),
 };
 
-static const uint32_t spitzkbd_row_gpios[] =
+static const uint32_t sharpslc_row_gpios[] =
 		{ 12, 17, 91, 34, 36, 38, 39 };
-static const uint32_t spitzkbd_col_gpios[] =
+static const uint32_t sharpslc_col_gpios[] =
 		{ 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 };
 
-static struct matrix_keypad_platform_data spitzkbd_pdata = {
-	.keymap_data		= &spitzkbd_keymap_data,
-	.row_gpios		= spitzkbd_row_gpios,
-	.col_gpios		= spitzkbd_col_gpios,
-	.num_row_gpios		= ARRAY_SIZE(spitzkbd_row_gpios),
-	.num_col_gpios		= ARRAY_SIZE(spitzkbd_col_gpios),
+static struct matrix_keypad_platform_data sharpslc_mkp_pdata = {
+	.keymap_data		= &sharpslc_keymap_data,
+	.row_gpios		= sharpslc_row_gpios,
+	.col_gpios		= sharpslc_col_gpios,
+	.num_row_gpios		= ARRAY_SIZE(sharpslc_row_gpios),
+	.num_col_gpios		= ARRAY_SIZE(sharpslc_col_gpios),
 	.col_scan_delay_us	= 10,
 	.debounce_ms		= 10,
 	.wakeup			= 1,
 };
 
-static struct platform_device spitzkbd_device = {
+static struct platform_device sharpslc_mkp_device = {
 	.name		= "matrix-keypad",
 	.id		= -1,
 	.dev		= {
-		.platform_data = &spitzkbd_pdata,
+		.platform_data	= &sharpslc_mkp_pdata,
 	},
 };
 
+static void __init sharpslc_mkp_init(void)
+{
+	platform_device_register(&sharpslc_mkp_device);
+}
+#else
+static inline void sharpslc_mkp_init(void) {}
+#endif
 
-static struct gpio_keys_button spitz_gpio_keys[] = {
+/******************************************************************************
+ * GPIO keys
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button sharpslc_gpio_keys[] = {
 	{
 		.type	= EV_PWR,
 		.code	= KEY_SUSPEND,
@@ -383,27 +426,35 @@ static struct gpio_keys_button spitz_gpio_keys[] = {
 	},
 };
 
-static struct gpio_keys_platform_data spitz_gpio_keys_platform_data = {
-	.buttons	= spitz_gpio_keys,
-	.nbuttons	= ARRAY_SIZE(spitz_gpio_keys),
+static struct gpio_keys_platform_data sharpslc_gpio_keys_platform_data = {
+	.buttons	= sharpslc_gpio_keys,
+	.nbuttons	= ARRAY_SIZE(sharpslc_gpio_keys),
 };
 
-static struct platform_device spitz_gpio_keys_device = {
+static struct platform_device sharpslc_gpio_keys_device = {
 	.name	= "gpio-keys",
 	.id	= -1,
 	.dev	= {
-		.platform_data	= &spitz_gpio_keys_platform_data,
+		.platform_data	= &sharpslc_gpio_keys_platform_data,
 	},
 };
 
+static void __init sharpslc_keys_init(void)
+{
+	platform_device_register(&sharpslc_gpio_keys_device);
+}
+#else
+static inline void sharpslc_keys_init(void) {}
+#endif
 
-/*
- * Spitz LEDs
- */
-static struct gpio_led spitz_gpio_leds[] = {
+/******************************************************************************
+ * LEDs
+ ******************************************************************************/
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static struct gpio_led sharpslc_gpio_leds[] = {
 	{
 		.name			= "spitz:amber:charge",
-		.default_trigger	= "sharpsl-charge",
+		.default_trigger	= "sharpslc-charge",
 		.gpio			= SPITZ_GPIO_LED_ORANGE,
 	},
 	{
@@ -413,25 +464,32 @@ static struct gpio_led spitz_gpio_leds[] = {
 	},
 };
 
-static struct gpio_led_platform_data spitz_gpio_leds_info = {
-	.leds		= spitz_gpio_leds,
-	.num_leds	= ARRAY_SIZE(spitz_gpio_leds),
+static struct gpio_led_platform_data sharpslc_gpio_leds_info = {
+	.leds		= sharpslc_gpio_leds,
+	.num_leds	= ARRAY_SIZE(sharpslc_gpio_leds),
 };
 
-static struct platform_device spitzled_device = {
+static struct platform_device sharpslc_led_device = {
 	.name		= "leds-gpio",
 	.id		= -1,
 	.dev		= {
-		.platform_data = &spitz_gpio_leds_info,
+		.platform_data	= &sharpslc_gpio_leds_info,
 	},
 };
 
-#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_master spitz_spi_info = {
-	.num_chipselect	= 3,
-};
+static void __init sharpslc_leds_init(void)
+{
+	platform_device_register(&sharpslc_led_device);
+}
+#else
+static inline void sharpslc_leds_init(void) {}
+#endif
 
-static void spitz_wait_for_hsync(void)
+/******************************************************************************
+ * SSP Devices
+ ******************************************************************************/
+#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
+static void sharpslc_ads7846_wait_for_hsync(void)
 {
 	while (gpio_get_value(SPITZ_GPIO_HSYNC))
 		cpu_relax();
@@ -440,21 +498,21 @@ static void spitz_wait_for_hsync(void)
 		cpu_relax();
 }
 
-static struct ads7846_platform_data spitz_ads7846_info = {
+static struct ads7846_platform_data sharpslc_ads7846_info = {
 	.model			= 7846,
 	.vref_delay_usecs	= 100,
 	.x_plate_ohms		= 419,
 	.y_plate_ohms		= 486,
 	.pressure_max		= 1024,
 	.gpio_pendown		= SPITZ_GPIO_TP_INT,
-	.wait_for_sync		= spitz_wait_for_hsync,
+	.wait_for_sync		= sharpslc_ads7846_wait_for_hsync,
 };
 
-static struct pxa2xx_spi_chip spitz_ads7846_chip = {
+static struct pxa2xx_spi_chip sharpslc_ads7846_chip = {
 	.gpio_cs		= SPITZ_GPIO_ADS7846_CS,
 };
 
-static void spitz_bl_kick_battery(void)
+static void sharpslc_bl_kick_battery(void)
 {
 	void (*kick_batt)(void);
 
@@ -465,93 +523,107 @@ static void spitz_bl_kick_battery(void)
 	}
 }
 
-static struct corgi_lcd_platform_data spitz_lcdcon_info = {
+static struct corgi_lcd_platform_data sharpslc_lcdcon_info = {
 	.init_mode		= CORGI_LCD_MODE_VGA,
 	.max_intensity		= 0x2f,
 	.default_intensity	= 0x1f,
 	.limit_mask		= 0x0b,
 	.gpio_backlight_cont	= SPITZ_GPIO_BACKLIGHT_CONT,
 	.gpio_backlight_on	= SPITZ_GPIO_BACKLIGHT_ON,
-	.kick_battery		= spitz_bl_kick_battery,
+	.kick_battery		= sharpslc_bl_kick_battery,
 };
 
-static struct pxa2xx_spi_chip spitz_lcdcon_chip = {
+static struct pxa2xx_spi_chip sharpslc_lcdcon_chip = {
 	.gpio_cs	= SPITZ_GPIO_LCDCON_CS,
 };
 
-static struct pxa2xx_spi_chip spitz_max1111_chip = {
+static struct pxa2xx_spi_chip sharpslc_max1111_chip = {
 	.gpio_cs	= SPITZ_GPIO_MAX1111_CS,
 };
 
-static struct spi_board_info spitz_spi_devices[] = {
+static struct spi_board_info sharpslc_spi_devices[] = {
 	{
 		.modalias	= "ads7846",
 		.max_speed_hz	= 1200000,
 		.bus_num	= 2,
 		.chip_select	= 0,
-		.platform_data	= &spitz_ads7846_info,
-		.controller_data= &spitz_ads7846_chip,
+		.platform_data	= &sharpslc_ads7846_info,
+		.controller_data= &sharpslc_ads7846_chip,
 		.irq		= gpio_to_irq(SPITZ_GPIO_TP_INT),
 	}, {
 		.modalias	= "corgi-lcd",
 		.max_speed_hz	= 50000,
 		.bus_num	= 2,
 		.chip_select	= 1,
-		.platform_data	= &spitz_lcdcon_info,
-		.controller_data= &spitz_lcdcon_chip,
+		.platform_data	= &sharpslc_lcdcon_info,
+		.controller_data= &sharpslc_lcdcon_chip,
 	}, {
 		.modalias	= "max1111",
 		.max_speed_hz	= 450000,
 		.bus_num	= 2,
 		.chip_select	= 2,
-		.controller_data= &spitz_max1111_chip,
+		.controller_data= &sharpslc_max1111_chip,
 	},
 };
 
-static void __init spitz_init_spi(void)
+static struct pxa2xx_spi_master sharpslc_spi_info = {
+	.num_chipselect	= 3,
+};
+
+static void __init sharpslc_spi_init(void)
 {
 	if (machine_is_akita()) {
-		spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
-		spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
+		sharpslc_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
+		sharpslc_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
 	}
 
-	pxa2xx_set_spi_info(2, &spitz_spi_info);
-	spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
+	pxa2xx_set_spi_info(2, &sharpslc_spi_info);
+	spi_register_board_info(ARRAY_AND_SIZE(sharpslc_spi_devices));
 }
 #else
-static inline void spitz_init_spi(void) {}
+static inline void sharpslc_spi_init(void) {}
 #endif
 
+/******************************************************************************
+ * SD/MMC card controller
+ ******************************************************************************/
+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
 /*
- * MMC/SD Device
- *
- * The card detect interrupt isn't debounced so we delay it by 250ms
- * to give the card a chance to fully insert/eject.
+ * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
+ * give the card a chance to fully insert/eject.
  */
-static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
+static void sharpslc_mci_setpower(struct device *dev, unsigned int vdd)
 {
 	struct pxamci_platform_data* p_d = dev->platform_data;
 
-	if (( 1 << vdd) & p_d->ocr_mask)
-		spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0004);
+	if ((1 << vdd) & p_d->ocr_mask)
+		sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
 	else
-		spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0000);
+		sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
 }
 
-static struct pxamci_platform_data spitz_mci_platform_data = {
+static struct pxamci_platform_data sharpslc_mci_platform_data = {
 	.detect_delay_ms	= 250,
 	.ocr_mask		= MMC_VDD_32_33|MMC_VDD_33_34,
-	.setpower 		= spitz_mci_setpower,
+	.setpower 		= sharpslc_mci_setpower,
 	.gpio_card_detect	= SPITZ_GPIO_nSD_DETECT,
 	.gpio_card_ro		= SPITZ_GPIO_nSD_WP,
 	.gpio_power		= -1,
 };
 
+static void __init sharpslc_mmc_init(void)
+{
+	pxa_set_mci_info(&sharpslc_mci_platform_data);
+}
+#else
+static inline void sharpslc_mmc_init(void) {}
+#endif
 
-/*
- * USB Host (OHCI)
- */
-static int spitz_ohci_init(struct device *dev)
+/******************************************************************************
+ * USB Host
+ ******************************************************************************/
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static int sharpslc_ohci_init(struct device *dev)
 {
 	int err;
 
@@ -559,88 +631,114 @@ static int spitz_ohci_init(struct device *dev)
 	if (err)
 		return err;
 
-	/* Only Port 2 is connected
-	 * Setup USB Port 2 Output Control Register
-	 */
+	/* Only Port 2 is connected, setup USB Port 2 Output Control Register */
 	UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
 
 	return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1);
 }
 
-static void spitz_ohci_exit(struct device *dev)
+static void sharpslc_ohci_exit(struct device *dev)
 {
 	gpio_free(SPITZ_GPIO_USB_HOST);
 }
 
-static struct pxaohci_platform_data spitz_ohci_platform_data = {
+static struct pxaohci_platform_data sharpslc_ohci_platform_data = {
 	.port_mode	= PMM_NPS_MODE,
-	.init		= spitz_ohci_init,
-	.exit		= spitz_ohci_exit,
+	.init		= sharpslc_ohci_init,
+	.exit		= sharpslc_ohci_exit,
 	.flags		= ENABLE_PORT_ALL | NO_OC_PROTECTION,
 	.power_budget	= 150,
 };
 
+static void __init sharpslc_uhc_init(void)
+{
+	pxa_set_ohci_info(&sharpslc_ohci_platform_data);
+}
+#else
+static inline void sharpslc_uhc_init(void) {}
+#endif
 
-/*
- * Irda
- */
-
-static struct pxaficp_platform_data spitz_ficp_platform_data = {
-/* .gpio_pwdown is set in spitz_init() and akita_init() accordingly */
+/******************************************************************************
+ * IrDA
+ ******************************************************************************/
+#if defined(CONFIG_PXA_FICP) || defined(CONFIG_PXA_FICP_MODULE)
+static struct pxaficp_platform_data sharpslc_ficp_platform_data = {
 	.transceiver_cap	= IR_SIRMODE | IR_OFF,
 };
 
+static void __init sharpslc_irda_init(void)
+{
+	if (machine_is_akita())
+		sharpslc_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
+	else
+		sharpslc_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
 
-/*
- * Spitz PXA Framebuffer
- */
+	pxa_set_ficp_info(&sharpslc_ficp_platform_data);
+}
+#else
+static inline void sharpslc_irda_init(void) {}
+#endif
 
-static struct pxafb_mode_info spitz_pxafb_modes[] = {
-{
-	.pixclock       = 19231,
-	.xres           = 480,
-	.yres           = 640,
-	.bpp            = 16,
-	.hsync_len      = 40,
-	.left_margin    = 46,
-	.right_margin   = 125,
-	.vsync_len      = 3,
-	.upper_margin   = 1,
-	.lower_margin   = 0,
-	.sync           = 0,
-},{
-	.pixclock       = 134617,
-	.xres           = 240,
-	.yres           = 320,
-	.bpp            = 16,
-	.hsync_len      = 20,
-	.left_margin    = 20,
-	.right_margin   = 46,
-	.vsync_len      = 2,
-	.upper_margin   = 1,
-	.lower_margin   = 0,
-	.sync           = 0,
-},
-};
-
-static struct pxafb_mach_info spitz_pxafb_info = {
-	.modes          = &spitz_pxafb_modes[0],
-	.num_modes      = 2,
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static struct pxafb_mode_info sharpslc_pxafb_modes[] = {
+	{
+		.pixclock       = 19231,
+		.xres           = 480,
+		.yres           = 640,
+		.bpp            = 16,
+		.hsync_len      = 40,
+		.left_margin    = 46,
+		.right_margin   = 125,
+		.vsync_len      = 3,
+		.upper_margin   = 1,
+		.lower_margin   = 0,
+		.sync           = 0,
+	},{
+		.pixclock       = 134617,
+		.xres           = 240,
+		.yres           = 320,
+		.bpp            = 16,
+		.hsync_len      = 20,
+		.left_margin    = 20,
+		.right_margin   = 46,
+		.vsync_len      = 2,
+		.upper_margin   = 1,
+		.lower_margin   = 0,
+		.sync           = 0,
+	},
+};
+
+static struct pxafb_mach_info sharpslc_pxafb_info = {
+	.modes          = sharpslc_pxafb_modes,
+	.num_modes      = ARRAY_SIZE(sharpslc_pxafb_modes),
 	.fixed_modes    = 1,
 	.lcd_conn	= LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
 };
 
-static struct mtd_partition sharpsl_nand_partitions[] = {
+static void __init sharpslc_lcd_init(void)
+{
+	set_pxa_fb_info(&sharpslc_pxafb_info);
+}
+#else
+static inline void sharpslc_lcd_init(void) {}
+#endif
+
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+#if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE)
+static struct mtd_partition sharpslc_nand_partitions[] = {
 	{
 		.name = "System Area",
 		.offset = 0,
 		.size = 7 * 1024 * 1024,
-	},
-	{
+	}, {
 		.name = "Root Filesystem",
 		.offset = 7 * 1024 * 1024,
-	},
-	{
+	}, {
 		.name = "Home Filesystem",
 		.offset = MTDPART_OFS_APPEND,
 		.size = MTDPART_SIZ_FULL,
@@ -649,37 +747,72 @@ static struct mtd_partition sharpsl_nand_partitions[] = {
 
 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
 
-static struct nand_bbt_descr sharpsl_bbt = {
-	.options = 0,
-	.offs = 4,
-	.len = 2,
-	.pattern = scan_ff_pattern
+static struct nand_bbt_descr sharpslc_nand_bbt = {
+	.options	= 0,
+	.offs		= 4,
+	.len		= 2,
+	.pattern	= scan_ff_pattern
 };
 
-static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
-	.badblock_pattern	= &sharpsl_bbt,
-	.partitions		= sharpsl_nand_partitions,
-	.nr_partitions		= ARRAY_SIZE(sharpsl_nand_partitions),
+static struct nand_ecclayout sharpslc_akita_oobinfo = {
+	.oobfree	= {{0x08, 0x09}},
+	.eccbytes	= 24,
+	.eccpos		= {
+			0x05, 0x01, 0x02, 0x03, 0x06, 0x07, 0x15, 0x11,
+			0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
+			0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37,
+	},
+};
+
+static struct sharpsl_nand_platform_data sharpslc_nand_platform_data = {
+	.badblock_pattern	= &sharpslc_nand_bbt,
+	.partitions		= sharpslc_nand_partitions,
+	.nr_partitions		= ARRAY_SIZE(sharpslc_nand_partitions),
 };
 
-static struct resource sharpsl_nand_resources[] = {
+static struct resource sharpslc_nand_resources[] = {
 	{
-		.start	= 0x0C000000,
-		.end	= 0x0C000FFF,
+		.start	= PXA_CS3_PHYS,
+		.end	= PXA_CS3_PHYS + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 
-static struct platform_device sharpsl_nand_device = {
+static struct platform_device sharpslc_nand_device = {
 	.name		= "sharpsl-nand",
 	.id		= -1,
-	.resource	= sharpsl_nand_resources,
-	.num_resources	= ARRAY_SIZE(sharpsl_nand_resources),
-	.dev.platform_data	= &sharpsl_nand_platform_data,
+	.resource	= sharpslc_nand_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_nand_resources),
+	.dev		= {
+		.platform_data	= &sharpslc_nand_platform_data,
+	}
 };
 
+static void __init sharpslc_nand_init(void)
+{
+	if (machine_is_spitz()) {
+		sharpslc_nand_partitions[1].size = 5 * 1024 * 1024;
+	} else if (machine_is_akita()) {
+		sharpslc_nand_partitions[1].size = 58 * 1024 * 1024;
+		sharpslc_nand_bbt.len = 1;
+		sharpslc_nand_platform_data.ecc_layout = &sharpslc_akita_oobinfo;
+	} else if (machine_is_borzoi()) {
+		sharpslc_nand_partitions[1].size = 32 * 1024 * 1024;
+		sharpslc_nand_bbt.len = 1;
+		sharpslc_nand_platform_data.ecc_layout = &sharpslc_akita_oobinfo;
+	}
 
-static struct mtd_partition sharpsl_rom_parts[] = {
+	platform_device_register(&sharpslc_nand_device);
+}
+#else
+static inline void sharpslc_nand_init(void) {}
+#endif
+
+/******************************************************************************
+ * NOR Flash
+ ******************************************************************************/
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition sharpslc_rom_parts[] = {
 	{
 		.name	="Boot PROM Filesystem",
 		.offset	= 0x00140000,
@@ -687,158 +820,117 @@ static struct mtd_partition sharpsl_rom_parts[] = {
 	},
 };
 
-static struct physmap_flash_data sharpsl_rom_data = {
+static struct physmap_flash_data sharpslc_rom_data = {
 	.width		= 2,
-	.nr_parts	= ARRAY_SIZE(sharpsl_rom_parts),
-	.parts		= sharpsl_rom_parts,
+	.nr_parts	= ARRAY_SIZE(sharpslc_rom_parts),
+	.parts		= sharpslc_rom_parts,
 };
 
-static struct resource sharpsl_rom_resources[] = {
+static struct resource sharpslc_rom_resources[] = {
 	{
-		.start	= 0x00000000,
-		.end	= 0x007fffff,
+		.start	= PXA_CS0_PHYS,
+		.end	= PXA_CS0_PHYS + SZ_8M - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 
-static struct platform_device sharpsl_rom_device = {
-	.name	= "physmap-flash",
-	.id	= -1,
-	.resource = sharpsl_rom_resources,
-	.num_resources = ARRAY_SIZE(sharpsl_rom_resources),
-	.dev.platform_data = &sharpsl_rom_data,
+static struct platform_device sharpslc_rom_device = {
+	.name		= "physmap-flash",
+	.id		= -1,
+	.resource	= sharpslc_rom_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_rom_resources),
+	.dev		= {
+		.platform_data	= &sharpslc_rom_data,
+	},
 };
 
-static struct platform_device *devices[] __initdata = {
-	&spitzscoop_device,
-	&spitzkbd_device,
-	&spitz_gpio_keys_device,
-	&spitzled_device,
-	&sharpsl_nand_device,
-	&sharpsl_rom_device,
+static void __init sharpslc_nor_init(void)
+{
+	platform_device_register(&sharpslc_rom_device);
+}
+#else
+static inline void sharpslc_nor_init(void) {}
+#endif
+
+/******************************************************************************
+ * GPIO expander
+ ******************************************************************************/
+#if defined(CONFIG_GPIO_PCA953X) || defined(CONFIG_GPIO_PCA953X_MODULE)
+static struct pca953x_platform_data akita_pca953x_pdata = {
+	.gpio_base		= AKITA_IOEXP_GPIO_BASE,
+};
+
+static struct i2c_board_info akita_i2c_devs[] = {
+	{
+		.type		= "max7310",
+		.addr		= 0x18,
+		.platform_data	= &akita_pxa953x_pdata,
+	},
 };
 
-static void spitz_poweroff(void)
+static void __init sharpslc_i2c_init(void)
+{
+	if (machine_is_akita()) {
+		pxa_set_i2c_info(NULL);
+		i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_devs));
+	}
+}
+#else
+static inline void sharpslc_i2c_init(void) {}
+#endif
+
+
+/******************************************************************************
+ * Machine init
+ ******************************************************************************/
+static void sharpslc_poweroff(void)
 {
 	arm_machine_restart('g', NULL);
 }
 
-static void spitz_restart(char mode, const char *cmd)
+static void sharpslc_restart(char mode, const char *cmd)
 {
 	/* Bootloader magic for a reboot */
-	if((MSC0 & 0xffff0000) == 0x7ff00000)
+	if ((MSC0 & 0xffff0000) == 0x7ff00000)
 		MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
 
-	spitz_poweroff();
+	sharpslc_poweroff();
 }
 
-static void __init common_init(void)
+static void __init sharpslc_init(void)
 {
 	init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
-	pm_power_off = spitz_poweroff;
-	arm_pm_restart = spitz_restart;
-
-	if (machine_is_spitz()) {
-		sharpsl_nand_partitions[1].size = 5 * 1024 * 1024;
-	} else if (machine_is_akita()) {
-		sharpsl_nand_partitions[1].size = 58 * 1024 * 1024;
-	} else if (machine_is_borzoi()) {
-		sharpsl_nand_partitions[1].size = 32 * 1024 * 1024;
-	}
+	pm_power_off = sharpslc_poweroff;
+	arm_pm_restart = sharpslc_restart;
 
 	PMCR = 0x00;
 
 	/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
 	PCFR |= PCFR_OPDE;
 
-	pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
+	pxa2xx_mfp_config(ARRAY_AND_SIZE(sharpslc_pin_config));
 
 	pxa_set_ffuart_info(NULL);
 	pxa_set_btuart_info(NULL);
 	pxa_set_stuart_info(NULL);
-
-	spitz_init_spi();
-
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	pxa_set_mci_info(&spitz_mci_platform_data);
-	pxa_set_ohci_info(&spitz_ohci_platform_data);
-	pxa_set_ficp_info(&spitz_ficp_platform_data);
-	set_pxa_fb_info(&spitz_pxafb_info);
-	pxa_set_i2c_info(NULL);
-}
-
-#if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI)
-static struct nand_bbt_descr sharpsl_akita_bbt = {
-	.options = 0,
-	.offs = 4,
-	.len = 1,
-	.pattern = scan_ff_pattern
-};
-
-static struct nand_ecclayout akita_oobinfo = {
-	.eccbytes = 24,
-	.eccpos = {
-		   0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
-		   0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
-		   0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
-	.oobfree = {{0x08, 0x09}}
-};
-#endif
-
-#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
-static void __init spitz_init(void)
-{
-	spitz_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
-
-#ifdef CONFIG_MACH_BORZOI
-	if (machine_is_borzoi()) {
-		sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
-		sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
-	}
-#endif
-
-	platform_scoop_config = &spitz_pcmcia_config;
-
-	common_init();
-
-	platform_device_register(&spitzscoop2_device);
+	pxa27x_set_i2c_power_info(NULL);
+
+	sharpslc_spi_init();
+	sharpslc_scoop_init();
+	sharpslc_mkp_init();
+	sharpslc_keys_init();
+	sharpslc_leds_init();
+	sharpslc_mmc_init();
+	sharpslc_pcmcia_init();
+	sharpslc_irda_init();
+	sharpslc_uhc_init();
+	sharpslc_lcd_init();
+	sharpslc_nor_init();
+	sharpslc_nand_init();
+	sharpslc_i2c_init();
 }
-#endif
-
-#ifdef CONFIG_MACH_AKITA
-/*
- * Akita IO Expander
- */
-static struct pca953x_platform_data akita_ioexp = {
-	.gpio_base		= AKITA_IOEXP_GPIO_BASE,
-};
-
-static struct i2c_board_info akita_i2c_board_info[] = {
-	{
-		.type		= "max7310",
-		.addr		= 0x18,
-		.platform_data	= &akita_ioexp,
-	},
-};
-
-static void __init akita_init(void)
-{
-	spitz_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
-
-	sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
-	sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
-
-	/* We just pretend the second element of the array doesn't exist */
-	spitz_pcmcia_config.num_devs = 1;
-	platform_scoop_config = &spitz_pcmcia_config;
-
-	i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_board_info));
-
-	common_init();
-}
-#endif
 
-static void __init fixup_spitz(struct machine_desc *desc,
+static void __init sharpslc_fixup(struct machine_desc *desc,
 		struct tag *tags, char **cmdline, struct meminfo *mi)
 {
 	sharpsl_save_param();
@@ -852,10 +944,10 @@ static void __init fixup_spitz(struct machine_desc *desc,
 MACHINE_START(SPITZ, "SHARP Spitz")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= spitz_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
@@ -864,10 +956,10 @@ MACHINE_END
 MACHINE_START(BORZOI, "SHARP Borzoi")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= spitz_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
@@ -876,10 +968,10 @@ MACHINE_END
 MACHINE_START(AKITA, "SHARP Akita")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= akita_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
-- 
1.7.1



From benh at kernel.crashing.org  Fri Jun 11 02:50:18 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Fri, 11 Jun 2010 16:50:18 +1000
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100611042046.GA31045@fluff.org.uk>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<1275636608.607067.417709988883.1.gpush@pororo>
	<20100611042046.GA31045@fluff.org.uk>
Message-ID: <1276239018.1962.118.camel@pasglop>

On Fri, 2010-06-11 at 05:20 +0100, Ben Dooks wrote:
> On Fri, Jun 04, 2010 at 03:30:08PM +0800, Jeremy Kerr wrote:
> > We currently have 21 definitions of struct clk in the ARM architecture,
> > each defined on a per-platform basis. This makes it difficult to define
> > platform- (or architecture-) independent clock sources without making
> > assumptions about struct clk, and impossible to compile two
> > platforms with different struct clks into a single image.
> 
> Whilst I agree that this is a useful thing to do, I'd like to ensure
> we get a good base for our work before we get another reason for Linus
> to complain about churn.

Well, in this case the goal is to unify things, both within ARM and
between architectures, so I fail to see Linus complaining about that :-)

> What do people think of just changing everyone who is currently using
> clk support to using this new implementation?

It's risky I suppose... there isn't many users of struct clk in powerpc
land today (I think one SoC platform only uses it upstream at the
moment) so I won't mind getting moved over at once but on ARM, you have
to deal with a lot more cruft that might warrant a more progressive
migration approach... but I'll let you guys judge.
 
> > struct clk {
> > 	const struct clk_ops	*ops;
> > 	unsigned int		enable_count;
> > 	struct mutex		mutex;
> 
> I'm a little worried about the size of struct clk if all of them
> have a mutex in them. If i'm right, this is 40 bytes of data each
> clock has to take on board.
> 
> Doing the following:
> 
> find arch/arm -type f -name "*.c" | xargs grep -c -E "struct.*clk.*=.*{" | grep -v ":0" | awk 'BEGIN { count=0; FS=":" }
> count += $2; END { print count }'
> 
> indicates that there's approximately 2241 clocks under arch/arm at the
> moment. That's about 87KiB of mutexes if all are being compiled at
> once.

I'm not convince this is relevant. You assume that all 2241 of those
clocks are statically allocated -and- compiled at the same time in the
same kernel binary.

I think both assumptions are terribly unlikely, especially in ARM
land :-) And in the event where you would actually manage to achieve
such a thing, I believe 87K is going to be the very last of your
worries :-)

In case it is of interest (and I know not everybody will want to do like
that) the way I intend to use this on powerpc is to have static clk_ops,
but instanciate the struct clk (or rather subclasses of struct clk)
on demand at clk_get time.

Basically, the device-tree (or platform code as a fallback) will bind
a device clock input to a clock provider / output pair. The clock
provider is something that produces struct clk * on demand for its
outputs.

Cheers,
Ben.

> ~> };
> > 
> > And a set of clock operations (defined per type of clock):
> > 
> > struct clk_operations {
> >        int             (*enable)(struct clk *);
> still think that not passing an bool as a second argument is silly.
> 
> >        void            (*disable)(struct clk *);
> ~>        unsigned long   (*get_rate)(struct clk *);
> >        [...]
> > };
> > 
> > To define a hardware-specific clock, machine code can "subclass" the
> > struct clock into a new struct (adding any device-specific data), and
> > provide a set of operations:
> > 
> > struct clk_foo {
> > 	struct clk	clk;
> > 	void __iomem	*some_register;
> > };
> > 
> > struct clk_operations clk_foo_ops = {
> > 	.get_rate = clk_foo_get_rate,
> > };
> > 
> > The common clock definitions are based on a development patch from Ben
> > Herrenschmidt <benh at kernel.crashing.org>.
> > 
> > Signed-off-by: Jeremy Kerr <jeremy.kerr at canonical.com>
> > 
> > ---
> >  arch/Kconfig        |    3 
> >  include/linux/clk.h |  159 ++++++++++++++++++++++++++++++++++++--------
> >  2 files changed, 135 insertions(+), 27 deletions(-)
> ~~~~> 
> > diff --git a/arch/Kconfig b/arch/Kconfig
> > index acda512..2458b5e 100644
> > --- a/arch/Kconfig
> > +++ b/arch/Kconfig
> > @@ -151,4 +151,7 @@ config HAVE_MIXED_BREAKPOINTS_REGS
> >  config HAVE_USER_RETURN_NOTIFIER
> >  	bool
> >  
> > +config USE_COMMON_STRUCT_CLK
> > +	bool
> > +
> >  source "kernel/gcov/Kconfig"
> > diff --git a/include/linux/clk.h b/include/linux/clk.h
> > index 1d37f42..bb6957a 100644
> > --- a/include/linux/clk.h
> > +++ b/include/linux/clk.h
> > @@ -3,6 +3,7 @@
> >   *
> >   *  Copyright (C) 2004 ARM Limited.
> >   *  Written by Deep Blue Solutions Limited.
> > + *  Copyright (c) 2010 Jeremy Kerr <jeremy.kerr at canonical.com>
> >   *
> >   * This program is free software; you can redistribute it and/or modify
> >   * it under the terms of the GNU General Public License version 2 as
> > @@ -11,36 +12,125 @@
> >  #ifndef __LINUX_CLK_H
> >  #define __LINUX_CLK_H
> >  
> > -struct device;
> > +#include <linux/err.h>
> > +#include <linux/mutex.h>
> >  
> > -/*
> > - * The base API.
> > +#ifdef CONFIG_USE_COMMON_STRUCT_CLK
> > +
> > +/* If we're using the common struct clk, we define the base clk object here,
> > + * which will be 'subclassed' by device-specific implementations. For example:
> > + *
> > + *  struct clk_foo {
> > + *      struct clk;
> > + *      [device specific fields]
> > + *  };
> > + *
> > + * We define the common clock API through a set of static inlines that call the
> > + * corresponding clk_operations. The API is exactly the same as that documented
> > + * in the !CONFIG_USE_COMMON_STRUCT_CLK case.
> >   */
> >  
> > +struct clk {
> > +	const struct clk_ops	*ops;
> > +	unsigned int		enable_count;
> > +	struct mutex		mutex;
> > +};
> 
> how about defining a nice kerneldoc for this.
> 
> > +#define INIT_CLK(name, o) \
> > +	{ .ops = &o, .enable_count = 0, \
> > +		.mutex = __MUTEX_INITIALIZER(name.mutex) }
> 
> how about doing the mutex initinitialisation at registration
> time, will save a pile of non-zero code in the image to mess up
> the compression.
> 
> ~> +struct clk_ops {
> > +       int             (*enable)(struct clk *);
> > +       void            (*disable)(struct clk *);
> > +       unsigned long   (*get_rate)(struct clk *);
> > +       void            (*put)(struct clk *);
> > +       long            (*round_rate)(struct clk *, unsigned long);
> > +       int             (*set_rate)(struct clk *, unsigned long);
> > +       int             (*set_parent)(struct clk *, struct clk *);
> > +       struct clk*     (*get_parent)(struct clk *);
> 
> should each clock carry a parent field and the this is returned by
> the get parent call.~~
> 
> > +};
> > +
> > +static inline int clk_enable(struct clk *clk)
> > +{
> > +	int ret = 0;
> > +
> > +	if (!clk->ops->enable)
> > +		return 0;
> > +
> > +	mutex_lock(&clk->mutex);
> > +	if (!clk->enable_count)
> > +		ret = clk->ops->enable(clk);
> > +
> > +	if (!ret)
> > +		clk->enable_count++;
> > +	mutex_unlock(&clk->mutex);
> > +
> > +	return ret;
> > +}
> 
> So we're leaving the enable parent code now to each implementation?
> 
> I think this is a really bad decision, it leaves so much open to bad
> code repetition, as well as something the core should really be doing
> if it had a parent clock field.
> 
> ~> +static inline void clk_disable(struct clk *clk)
> > +{
> > +	if (!clk->ops->enable)
> > +		return;
> 
> so if we've no enable call we ignore disable too?
> 
> also, we don't keep an enable count if this fields are in use,
> could people rely on this being correct even if the clock has
> no enable/disable fields.
> 
> Would much rather see the enable_count being kept up-to-date
> no matter what, given it may be watched by other parts of the
> implementation, useful for debug info, and possibly useful if
> later in the start sequence the clk_ops get changed to have this
> field.~
> 
> > +~	mutex_lock(&clk->mutex);
> > +
> > +	if (!--clk->enable_count)
> > +		clk->ops->disable(clk);
> > +
> > +	mutex_unlock(&clk->mutex);
> > +}
> > +
> > +static inline unsigned long clk_get_rate(struct clk *clk)
> > +{
> > +	if (clk->ops->get_rate)
> > +		return clk->ops->get_rate(clk);
> > +	return 0;
> > +}
> > +
> > +static inline void clk_put(struct clk *clk)
> > +{
> > +	if (clk->ops->put)
> > +		clk->ops->put(clk);
> > +}
> 
> I'm beginging to wonder if we don't just have a set of default ops
> that get set into the clk+ops at registration time if these do
> not have an implementation.
> ~
> > +static inline long clk_round_rate(struct clk *clk, unsigned long rate)
> > +{
> > +	if (clk->ops->round_rate)
> > +		return clk->ops->round_rate(clk, rate);
> > +	return -ENOSYS;
> > +}
> > +
> > +static inline int clk_set_rate(struct clk *clk, unsigned long rate)
> >~ +{
> > +	if (clk->ops->set_rate)
> > +		return clk->ops->set_rate(clk, rate);
> > +	return -ENOSYS;
> > +}
> > +
> > +static inline int clk_set_parent(struct clk *clk, struct clk *parent)
> > +{
> > +	if (clk->ops->set_parent)
> > +		return clk->ops->set_parent(clk, parent);
> > +	return -ENOSYS;
> > +}
> 
> We have an interesting problem here which I belive should be dealt
> with, what happens when the clock's parent is changed with respect
> to the enable count of the parent.
> 
> With the following instance:
> 
> 	we have clocks a, b, c;
> 	a and b are possible parents for c;
> 	c starts off with a as parent
> 
> then the driver comes along:
> 
> 	1) gets clocks a, b, c;
> 	2) clk_enable(c);
> 	3) clk_set_parent(c, b);
> 	
> now we have the following:
> 
> 	A) clk a now has an enable count of non-zero
> 	B) clk b may not be enabled
> 	C) even though clk a may now be unused, it is still running
> 	D) even though clk c was enabled, it isn't running since step3
> 
> this means that either any driver that is using a multi-parent clock
> has to deal with the proper enable/disable of the parents (this is
> is going to lead to code repetition, and I bet people will get it
> badly wrong).
> 
> I belive the core of the clock code should deal with this, since
> otherwise we end up with the situation of the same code being
> repeated throughout the kernel.
> 
> > +static inline struct clk *clk_get_parent(struct clk *clk)
> > +{
> > +	if (clk->ops->get_parent)
> > +		return clk->ops->get_parent(clk);
> > +	return ERR_PTR(-ENOSYS);
> > +}
> >
> > +#else /* !CONFIG_USE_COMMON_STRUCT_CLK */
> >  
> >  /*
> > - * struct clk - an machine class defined object / cookie.
> > + * Global clock object, actual structure is declared per-machine
> >   */
> >  struct clk;
> >  
> >  /**
> > - * clk_get - lookup and obtain a reference to a clock producer.
> > - * @dev: device for clock "consumer"
> > - * @id: clock comsumer ID
> > - *
> > - * Returns a struct clk corresponding to the clock producer, or
> > - * valid IS_ERR() condition containing errno.  The implementation
> > - * uses @dev and @id to determine the clock consumer, and thereby
> ~> - * the clock producer.  (IOW, @id may be identical strings, but
> > - * clk_get may return different clock producers depending on @dev.)
> > - *
> > - * Drivers must assume that the clock source is not enabled.
> > - *
> > - * clk_get should not be called from within interrupt context.
> > - */
> > -struct clk *clk_get(struct device *dev, const char *id);
> > -
> > -/**
> >   * clk_enable - inform the system when the clock source should be running.
> >   * @clk: clock source
> >   *
> > @@ -83,12 +173,6 @@ unsigned long clk_get_rate(struct clk *clk);
> >   */
> >  void clk_put(struct clk *clk);
> >  
> > -
> > -/*
> > - * The remaining APIs are optional for machine class support.
> > - */
> > -
> > -
> >  /**
> >   * clk_round_rate - adjust a rate to the exact rate a clock can provide
> >   * @clk: clock source
> > @@ -125,6 +209,27 @@ int clk_set_parent(struct clk *clk, struct clk *parent);
> >   */
> >  struct clk *clk_get_parent(struct clk *clk);
> >  
> > +#endif /* !CONFIG_USE_COMMON_STRUCT_CLK */
> > +
> > +struct device;
> > +
> > +/**
> > + * clk_get - lookup and obtain a reference to a clock producer.
> > + * @dev: device for clock "consumer"
> > + * @id: clock comsumer ID
> > + *
> > + * Returns a struct clk corresponding to the clock producer, or
> > + * valid IS_ERR() condition containing errno.  The implementation
> > + * uses @dev and @id to determine the clock consumer, and thereby
> > + * the clock producer.  (IOW, @id may be identical strings, but
> > + * clk_get may return different clock producers depending on @dev.)
> > + *
> > + * Drivers must assume that the clock source is not enabled.
> > + *
> > + * clk_get should not be called from within interrupt context.
> ~~> + */
> > +struct clk *clk_get(struct device *dev, const char *id);
> > +
> >  /**
> >   * clk_get_sys - get a clock based upon the device name
> >   * @dev_id: device name
> > --
> > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> > the body of a message to majordomo at vger.kernel.org
> > More majordomo info at  http://vger.kernel.org/majordomo-info.html
> > Please read the FAQ at  http://www.tux.org/lkml/
> 




From marek.vasut at gmail.com  Fri Jun 11 02:52:45 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 11 Jun 2010 08:52:45 +0200
Subject: [PATCH 2/2] pxa/spitz: Rework spitz
In-Reply-To: <1276238740-10640-2-git-send-email-marek.vasut@gmail.com>
References: <1276238740-10640-1-git-send-email-marek.vasut@gmail.com>
	<1276238740-10640-2-git-send-email-marek.vasut@gmail.com>
Message-ID: <201006110852.45838.marek.vasut@gmail.com>

Dne P? 11. ?ervna 2010 08:45:40 Marek Vasut napsal(a):
> This huge patch mostly shuffles code. The spitz.c file contained terrible
> mess and needed a cleanup, here it is:
> 
> 1) Made every part modular, components are not built in if not selected.
> 2) Removed loads of preprocessor goo, mostly "#ifdef MACH_AKITA ....
> #endif" and similar code. The kernel size will grow by a few kb now, but
> the file is much more readable.
> 3) Reworked SD/CF power setting function and made it reentrant.
> 
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> ---
>  arch/arm/mach-pxa/include/mach/spitz.h |    2 -
>  arch/arm/mach-pxa/spitz.c              |  748
> ++++++++++++++++++-------------- 2 files changed, 420 insertions(+), 330
> deletions(-)
> 

Pavel, Eric, I tested this on metan's Z, could you give it a go ?
Thanks!


From kmpark at infradead.org  Fri Jun 11 03:07:58 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 11 Jun 2010 16:07:58 +0900
Subject: Pending patches for s5pc110
In-Reply-To: <20100611062300.GY7248@trinity.fluff.org>
References: <AANLkTil0wWSFHpwi58enMhhG7475uUmFoZG6QhRim6Xk@mail.gmail.com>
	<AANLkTimjwSHLiMYFywn3vHZYCbqQCCCh9qE-n3xuYOaq@mail.gmail.com>
	<20100611051521.GV7248@trinity.fluff.org>
	<AANLkTikJQnDEjVunmiCLGaVAnj5bR7JdsUZYJ9xAEdE5@mail.gmail.com>
	<20100611062300.GY7248@trinity.fluff.org>
Message-ID: <AANLkTimnuN9h-qka3pRlmaEsR8o6IzFgl3A2YQ5Y28HJ@mail.gmail.com>

On Fri, Jun 11, 2010 at 3:23 PM, Ben Dooks <ben-linux at fluff.org> wrote:
> On Fri, Jun 11, 2010 at 02:38:56PM +0900, Kyungmin Park wrote:
>> On Fri, Jun 11, 2010 at 2:15 PM, Ben Dooks <ben-linux at fluff.org> wrote:
>> > On Fri, Jun 11, 2010 at 01:25:18PM +0900, Kyungmin Park wrote:
>> >> Hi,
>> >>
>> >> No comments mean it's okay then we will prepare the patches to git pull.
>> >
>> > No. no comments means that people either haven't had time to sort
>> > them out or in fact ON HOLIDAY.
>>
>> but you usually missed our patches frequently. with this reason our
>> patches can't merge within proper merge window.
>
> I belive the last set where either being posted just-before or during
> the last merge window. We already had far too much queueud up then and
> we where trying to ensure that the already-queued entries where processed.

Not tell this case, please see the s5pc110 patches last year. last
year we sent the s5pc110 related patches several times. but you don't
give any opinions and can't accept without any reason.

Well it's past story,  forget it.

Last question.

I think you share the s3c maintainer-ship with Kukjin. Can you explain
the criteria?

Thank you,
Kyungmin Park

>
> The last call for updates went out on 13th May, and the two machine
> patches actually turned up on the 30th of May...
>
> It is important that we get these merges ready at least a week in
> advance of the merge window, otherwise there is _no_ time time to test
> the merged trees, and even worse there is little time to correct any
> mistakes... there where I belive two merge problems with trying to
> rebuild trees at the last minute ready to send to Linus.
>
> Unfortunately the S5PC100 moves did get overlooked (I think I may ended
> up dropping off the samsung-soc list) and the ended up producing a lot
> of the work involved in generating the pull request to RMK and then
> Linus. (see http://thread.gmane.org/gmane.linux.kernel.samsung-soc/1427)
>
> If we can organise ourselves better (and Kukjin will be taking over some
> of this work) then maybe we will have a much better experience for the
> next time.
>
>> >
>> >> Thank you,
>> >> Kyungmin Park
>> >>
>> >> On Fri, Jun 4, 2010 at 8:53 AM, Kyungmin Park <kmpark at infradead.org> wrote:
>> >> > Hi ben,
>> >> >
>> >> > There's some pending patches for s5pc110.
>> >> > 1. aquila & goni support files.
>> >
>> > these two should have gone in already
>>
>> I mean more aquila & goni patches. not basic support. e.g. OneNAND
>> support, FB support and so on.
>
> As above, I belive these where rather late on the horizon to be included.
>
>> >> > 2. keypad
>> >
>> > I think kukjin has been looking at this, best check with him.
>>
>> It's already discussed. do you think it needs more comments?
>
> Me, no. I think if Kukjin has no problems then it is up to Dimitry
> whether he wants to merge it.
>
>> >
>> >> > 3. s3c-fb - we have to implement FIMD and MIPI interface so please
>> >> > decide how to handle it.
>> >
>> > since we've not had any chance to discuss what is going on here
>> > I can't see how we are ready to submit anything.
>>
>> It's basic functionality for s3c-fb. it's required for our target and
>> want to use it. even though someone don't use it.
>>
>> I wonder some features are not used for other board. in this case it
>> should be merged if it doesn't break any previous board. Of course
>> with proper feedback. I think we answer your question doesn't it?
>
> The fb system is currently without a propler maintainer and Andrew Morton
> has been doing the job of applying patches. I don't know the reasons for
> the last round of development not going in, but it was probably due to it
> being too late.. I've so far been unable to actually subscribe to the new
> fb list to try and sort it out.
>
> This however doesn't cover the fact that there's been no movement on
> dicsussing what is needed to support FIMC addition to the framebuffer
> driver.
>
> Do you have even a list of things that you think are needed for this, or
> any actual patches we could look at and discuss?
>
> --
> Ben
>
> Q: ? ? ?What's a light-year?
> A: ? ? ?One-third less calories than a regular year.
>
>


From nicolas.ferre at atmel.com  Fri Jun 11 03:23:12 2010
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 11 Jun 2010 09:23:12 +0200
Subject: [PATCH] MAINTAINERS: some Atmel drivers change maintainer
In-Reply-To: <1275054888-13828-1-git-send-email-nicolas.ferre@atmel.com>
References: <20100528114245.3d030692@hskinnemoen-d830>
	<1275054888-13828-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <4C11E460.4010101@atmel.com>

Le 28/05/2010 15:54, Nicolas Ferre :
> I take over the maintenance of SPI, USART, Ethernet and USB gadget drivers.
> Those drivers are found in Atmel microcontrollers, both AT32/AVR32 and
> AT91/ARM.
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Ping,

With added acked-by:
Acked-by: Haavard Skinnemoen <haavard.skinnemoen at atmel.com>

> ---
> Haavard,
> I finally change the MAINTAINERS entries for all drivers that you were
> taking care of. I must admit that I was a bit frighten at the first place but
> anyway, since one year, I am getting used to it ;-)
> 
> 
>  MAINTAINERS |   10 +++++-----
>  1 files changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 33047a6..d9ce9c6 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1148,7 +1148,7 @@ F:	drivers/mmc/host/atmel-mci.c
>  F:	drivers/mmc/host/atmel-mci-regs.h
>  
>  ATMEL AT91 / AT32 SERIAL DRIVER
> -M:	Haavard Skinnemoen <hskinnemoen at atmel.com>
> +M:	Nicolas Ferre <nicolas.ferre at atmel.com>
>  S:	Supported
>  F:	drivers/serial/atmel_serial.c
>  
> @@ -1160,18 +1160,18 @@ F:	drivers/video/atmel_lcdfb.c
>  F:	include/video/atmel_lcdc.h
>  
>  ATMEL MACB ETHERNET DRIVER
> -M:	Haavard Skinnemoen <hskinnemoen at atmel.com>
> +M:	Nicolas Ferre <nicolas.ferre at atmel.com>
>  S:	Supported
>  F:	drivers/net/macb.*
>  
>  ATMEL SPI DRIVER
> -M:	Haavard Skinnemoen <hskinnemoen at atmel.com>
> +M:	Nicolas Ferre <nicolas.ferre at atmel.com>
>  S:	Supported
>  F:	drivers/spi/atmel_spi.*
>  
>  ATMEL USBA UDC DRIVER
> -M:	Haavard Skinnemoen <hskinnemoen at atmel.com>
> -L:	kernel at avr32linux.org
> +M:	Nicolas Ferre <nicolas.ferre at atmel.com>
> +L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
>  W:	http://avr32linux.org/twiki/bin/view/Main/AtmelUsbDeviceDriver
>  S:	Supported
>  F:	drivers/usb/gadget/atmel_usba_udc.*


-- 
Nicolas Ferre



From kgene.kim at samsung.com  Fri Jun 11 03:29:46 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 11 Jun 2010 16:29:46 +0900
Subject: [PATCH v3] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <4C10C1D6.8080708@ru.mvista.com>
References: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
	<4C10C1D6.8080708@ru.mvista.com>
Message-ID: <003301cb0937$e04412c0$a0cc3840$%kim@samsung.com>

Sergei Shtylyov wrote:
> 
> Kukjin Kim wrote:
> 
> > From: Abhilash Kesavan <a.kesavan at samsung.com>
> 
> > Adds support for the Samsung PATA controller. This driver is based on the
> > Libata subsystem and references the earlier patches sent for IDE
subsystem.
> 
Hi,

Thanks for your comments.

> > Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> 
> [...]
> 
> > diff --git a/drivers/ata/pata_samsung_cf.c
b/drivers/ata/pata_samsung_cf.c
> > new file mode 100644
> > index 0000000..fef5515
> > --- /dev/null
> > +++ b/drivers/ata/pata_samsung_cf.c
> > @@ -0,0 +1,608 @@
> > +/* linux/drivers/ata/pata_samsung_cf.c
> 
>     File names in the heading comment are discouraged.
> 
Hmm. I used like that in other device drivers.
Ok..will remove the file name in the heading comment.

> [...]
> 
> > +static unsigned long
> > +pata_s3c_setup_timing(struct s3c_ide_info *info, struct ata_device
*adev)
> > +{
> > +	const struct ata_timing *timing;
> > +	int cycle_time;
> > +	int t1;
> > +	int t2;
> > +	int t2i;
> > +	ulong piotime;
> > +
> > +	cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
> > +
> > +	timing = ata_timing_find_mode(adev->pio_mode);
> > +	t1	= (timing->setup / cycle_time) & 0xf;
> > +	t2	= (timing->act8b / cycle_time) & 0xff;
> > +	t2i	= (timing->rec8b / cycle_time) & 0xff;
> 
>     Why are you still not using ata_timing_compute()?
> 
Ok, will remove ata_timing_find_mode and used ata_timing_compute in
pata_s3c_set_piomode for timing parameters.

> > +
> > +	piotime = (t2i << 12) | (t2 << 4) | t1;
> > +
> > +	return piotime;
> > +}
> > +
> > +static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device
*adev)
> > +{
> > +	int mode = adev->pio_mode - XFER_PIO_0;
> > +	struct s3c_ide_info *info = ap->host->private_data;
> > +	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
> > +	ulong piotime;
> > +
> > +	/* Calculates timing parameters for PIO mode */
> > +	piotime = pata_s3c_setup_timing(info, adev);
> 
>     In fact, for 8-bit (command) timing you should program the slowest mode
of
> the two drives. However, with CF, you probably only have only one drive per
> channel...
> 
Below code looks OK ?
 
	if (ata_timing_compute(adev, adev->pio_mode, &timing, cycle_time, 0))
{
		dev_err(ap->dev, "Failed to compute ATA timing\n");
		piotime = pata_s3c_setup_timing(info, &initial_timing);
	} else {
		piotime = pata_s3c_setup_timing(info, &timing);
	}
where initial_timing is for PIO0. I have added the below struct

static const struct ata_timing initial_timing =
	{XFER_PIO_0, 70, 290, 240, 600, 165, 150, 0, 600, 0};

> > +
> > +	/* Enables IORDY if mode requires it */
> > +	if (ata_pio_need_iordy(adev))
> > +		ata_cfg |= S3C_ATA_CFG_IORDYEN;
> > +	else
> > +		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
> > +
> > +	/* Host controller supports upto PIO4 only */
> > +	if (mode >= 0 && mode <= 4) {
> 
>     No need to check -- you won't be passed a mode not specified by your
> pio_mask.
> 
Will remove the check.

> > +		writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
> > +		writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
> > +	}
> > +}
> 
> [...]
> 
> > +/*
> > + * pata_s3c_data_xfer - Transfer data by PIO
> > + */
> > +unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char
*buf,
> > +				unsigned int buflen, int rw)
> > +{
> > +	struct ata_port *ap = dev->link->ap;
> > +	struct s3c_ide_info *info = ap->host->private_data;
> > +	void __iomem *data_addr = ap->ioaddr.data_addr;
> > +	unsigned int words = buflen >> 1, i;
> > +	u16 *data_ptr = (u16 *)buf;
> > +
> > +	if (rw == READ)
> > +		for (i = 0; i < words; i++, data_ptr++) {
> > +			wait_for_host_ready(info);
> > +			*data_ptr = readw(data_addr);
> 
>     Why not just ignore the result?
> 
Will change to (void)readw(data_addr) as Ben Dooks suggested.

> > +			wait_for_host_ready(info);
> > +			*data_ptr = readw(info->ide_addr
> > +					+ S3C_ATA_PIO_RDATA);
> > +		}
> > +	else
> > +		for (i = 0; i < words; i++, data_ptr++) {
> > +			wait_for_host_ready(info);
> > +			writel(*data_ptr, data_addr);
> > +		}
> > +
> > +	return words << 1;
> > +}
> 
> [...]
> 
> > +static struct ata_port_operations pata_s3c_port_ops = {
> > +	.inherits		= &ata_sff_port_ops,
> > +	.sff_check_status	= pata_s3c_check_status,
> > +	.sff_check_altstatus    = pata_s3c_check_altstatus,
> > +	.sff_tf_load		= pata_s3c_tf_load,
> > +	.sff_tf_read		= pata_s3c_tf_read,
> > +	.sff_data_xfer		= pata_s3c_data_xfer,
> > +	.sff_exec_command	= pata_s3c_exec_command,
> > +	.sff_dev_select         = pata_s3c_dev_select,
> > +	.sff_set_devctl         = pata_s3c_set_devctl,
> 
>     I forgot: you also need to override the softreset() method as it
accesses
> several taskfile registers and ioread8()/iowrite8() won't suffice -- Jeff
was
> too quick to ack the patch. See ata_bus_softreset(), ata_devchk(), and
> ata_sff_wait_after_reset() for the accesses I'm talking about...
> 
Will add softreset method and the associated functions required.

> [...]
> 
> > +static int __devinit pata_s3c_probe(struct platform_device *pdev)
> > +{
> > +	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
> > +	struct device *dev = &pdev->dev;
> > +	struct s3c_ide_info *info;
> > +	struct resource *res;
> > +	struct ata_port *ap;
> > +	struct ata_host *host;
> > +	enum s3c_cpu_type cpu_type;
> > +	int ret;
> > +
> > +	cpu_type = platform_get_device_id(pdev)->driver_data;
> > +
> > +	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
> > +	if (!info) {
> > +		dev_err(dev, "failed to allocate memory for device data\n");
> > +		return -ENOMEM;
> > +	}
> > +
> > +	info->irq = platform_get_irq(pdev, 0);
> > +	if (info->irq < 0) {
> > +		dev_err(dev, "could not obtain irq number\n");
> > +		ret = -EINVAL;
> > +		goto release_device_mem;
> > +	}
> > +
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	if (res == NULL) {
> > +		dev_err(dev, "failed to get mem resource\n");
> > +		ret = -EINVAL;
> > +		goto release_device_mem;
> > +	}
> > +
> > +	if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
> 
>     Probably should call devm_request_mem_region() if you're using
> devm_ioremap()...
> 
Will change to devm_request_mem_region.

> > +		dev_err(dev, "error requesting register region\n");
> > +		return -EBUSY;
> > +	}
> > +
> > +	info->ide_addr = devm_ioremap(dev, res->start, resource_size(res));
> > +	if (!info->ide_addr) {
> > +		dev_err(dev, "failed to map IO base address\n");
> > +		ret = -ENOMEM;
> > +		goto release_mem;
> > +	}
> > +
> > +	info->clk = clk_get(&pdev->dev, "cfcon");
> > +	if (IS_ERR(info->clk)) {
> > +		dev_err(dev, "failed to get access to cf controller
clock\n");
> > +		ret = PTR_ERR(info->clk);
> > +		info->clk = NULL;
> 
>     No 'goto' here?
> 
Will add return ret instead of goto.

> [...]
> 
> > +stop_clk:
> > +	clk_disable(info->clk);
> 
>     Where is clk_put() call?
> 
Will add clk_put

> > +release_mem:
> > +	release_mem_region(res->start, resource_size(res));
> > +release_device_mem:
> > +	kfree(info);
> 
>     Doesn't using devm_kzalloc() guarantee that the memory will be freed up
> automatically?
> 
Will remove kfree and release_mem_region because of devm_kzalloc and
devm_request_mem_region usage

> > +return ret;
> 
>     Wrong indentation.
> 
OK.

> > +static struct platform_driver pata_s3c_driver = {
> > +	.probe		= pata_s3c_probe,
> >
> >
> 
>     2 empty lines -- broken patch?
> 
Seems OK at my end.

> > +	.remove		= __devexit_p(pata_s3c_remove),
> > +	.id_table	= pata_s3c_driver_ids,
> > +	.driver		= {
> > +		.name	= DRV_NAME,
> > +		.owner	= THIS_MODULE,
> > +#ifdef CONFIG_PM
> > +		.pm	= &pata_s3c_pm_ops,
> > +#endif
> > +	},
> > +};
> 
> [...]
> 
> MBR, Sergei

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Fri Jun 11 03:41:31 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 11 Jun 2010 16:41:31 +0900
Subject: [PATCH v3] libata: pata_samsung_cf: Add Samsung PATA	controller
	driver
In-Reply-To: <20100611022410.GD14272@trinity.fluff.org>
References: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
	<20100611022410.GD14272@trinity.fluff.org>
Message-ID: <003701cb0939$853e0050$8fba00f0$%kim@samsung.com>

Ben Dooks wrote:
> 
> On Thu, Jun 10, 2010 at 04:50:41PM +0900, Kukjin Kim wrote:
> > From: Abhilash Kesavan <a.kesavan at samsung.com>
> >
> > Adds support for the Samsung PATA controller. This driver is based on the
> > Libata subsystem and references the earlier patches sent for IDE
subsystem.
> >

Thanks for your review. :-)

> > Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> 
> a few more comments, you may or may not want to fix before first
> submission.
> 
> > ---
> >
> > Changes since v2:
> > - Changed the DRV_NAME to pata_samsung_cf
> > - Used msleep instead of mdelay
> >
> >  drivers/ata/Makefile          |    1 +
> >  drivers/ata/pata_samsung_cf.c |  608
> +++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 618 insertions(+), 0 deletions(-)
> >  create mode 100644 drivers/ata/pata_samsung_cf.c
> >
> > diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> > index aa85a98..1b5facf 100644
> > --- a/drivers/ata/Kconfig
> > +++ b/drivers/ata/Kconfig
> > @@ -796,6 +796,15 @@ config PATA_RZ1000
> >
> >  	  If unsure, say N.
> >
> > +config PATA_SAMSUNG_CF
> > +	tristate "Samsung SoC PATA support"
> > +	depends on SAMSUNG_DEV_IDE
> > +	help
> > +	  This option enables basic support for Samsung's S3C/S5P board
> > +	  PATA controllers via the new ATA layer
> > +
> > +	  If unsure, say N.
> > +
> >  config PATA_WINBOND_VLB
> >  	tristate "Winbond W83759A VLB PATA support (Experimental)"
> >  	depends on ISA && EXPERIMENTAL
> > diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> > index 7ef89d7..9576776 100644
> > --- a/drivers/ata/Makefile
> > +++ b/drivers/ata/Makefile
> > @@ -87,6 +87,7 @@ obj-$(CONFIG_PATA_OF_PLATFORM)	+=
> pata_of_platform.o
> >  obj-$(CONFIG_PATA_QDI)		+= pata_qdi.o
> >  obj-$(CONFIG_PATA_RB532)	+= pata_rb532_cf.o
> >  obj-$(CONFIG_PATA_RZ1000)	+= pata_rz1000.o
> > +obj-$(CONFIG_PATA_SAMSUNG_CF)	+= pata_samsung_cf.o
> >  obj-$(CONFIG_PATA_WINBOND_VLB)	+= pata_winbond.o
> >
> >  # Should be last but two libata driver
> > diff --git a/drivers/ata/pata_samsung_cf.c
b/drivers/ata/pata_samsung_cf.c
> > new file mode 100644
> > index 0000000..fef5515
> > --- /dev/null
> > +++ b/drivers/ata/pata_samsung_cf.c
> > @@ -0,0 +1,608 @@
> > +/* linux/drivers/ata/pata_samsung_cf.c
> > + *
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com
> > + *
> > + * PATA driver for Samsung SoCs.
> > + * Supports CF Interface in True IDE mode. Currently only PIO mode has
been
> > + * implemented; UDMA support has to be added.
> > + *
> > + * Based on:
> > + *	PATA driver for AT91SAM9260 Static Memory Controller
> > + *	PATA driver for Toshiba SCC controller
> > + *
> > + * This program is free software; you can redistribute it and/or modify
it
> > + * under the terms of the GNU General Public License version 2
> > + * as published by the Free Software Foundation.
> > +*/
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/init.h>
> > +#include <linux/clk.h>
> > +#include <linux/libata.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +
> > +#include <plat/ata.h>
> > +#include <plat/regs-ata.h>
> > +
> > +#define DRV_NAME "pata_samsung_cf"
> > +#define DRV_VERSION "0.1"
> > +
> > +enum s3c_cpu_type {
> > +	TYPE_S3C64XX,
> > +	TYPE_S5PC100,
> > +	TYPE_S5PV210,
> > +};
> > +
> > +/*
> > + * struct s3c_ide_info - S3C PATA instance.
> > + * @clk: The clock resource for this controller.
> > + * @ide_addr: The area mapped for the hardware registers.
> > + * @sfr_addr: The area mapped for the special function registers.
> > + * @irq: The IRQ number we are using.
> > + * @cpu_type: The exact type of this controller.
> > + * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
> > + */
> > +struct s3c_ide_info {
> > +	struct clk *clk;
> > +	void __iomem *ide_addr;
> > +	void __iomem *sfr_addr;
> > +	unsigned int irq;
> > +	enum s3c_cpu_type cpu_type;
> > +	unsigned int fifo_status_reg;
> > +};
> > +
> > +static void pata_s3c_set_endian(void *s3c_ide_regbase, u8 mode)
> > +{
> should be void __iomem.
> 
OK.

> > +static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device
*adev)
> > +{
> > +	int mode = adev->pio_mode - XFER_PIO_0;
> > +	struct s3c_ide_info *info = ap->host->private_data;
> > +	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
> > +	ulong piotime;
> > +
> > +	/* Calculates timing parameters for PIO mode */
> > +	piotime = pata_s3c_setup_timing(info, adev);
> > +
> > +	/* Enables IORDY if mode requires it */
> > +	if (ata_pio_need_iordy(adev))
> > +		ata_cfg |= S3C_ATA_CFG_IORDYEN;
> > +	else
> > +		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
> > +
> > +	/* Host controller supports upto PIO4 only */
> > +	if (mode >= 0 && mode <= 4) {
> 
> if this code was to stay in, it would have been better to either
> WARN_ON() or print some form of error messagee instead of just silently
> ignoring it... also, you should have probably set the minumum acceptable
> ATA mode to ensure any further actions would not cause problems with
> trying to run the b us too fast.
> 
Will remove the code..will set up the timing parameters using
ata_timing_compute and the initial timing will be for PIO0 in case of
failure.

> > +/*
> > + * Waits until the IDE controller is able to perform next read/write
> > + * operation to the disk. Needed for 64XX series boards only.
> > + */
> 
> if it is needed only for s3c64xx series, why don't we bail if the
> info->type != 64xx?
> 
This is called via pata_s3c_port_ops for 64xx else goes to pata_s5p_port_ops.

> > +static int wait_for_host_ready(struct s3c_ide_info *info)
> > +{
> > +	ulong timeout;
> > +
> > +	/* wait for maximum of 20 msec */
> > +	timeout = jiffies + msecs_to_jiffies(20);
> > +	while (time_before(jiffies, timeout)) {
> > +		if ((readl(info->ide_addr + info->fifo_status_reg) >> 28) ==
0)
> 
> would be neater to have
>       void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg
>       ...
> 
>       while(...) {
>       		 if (readl(fifo_reg) >> 28) == 0)
> 	 ...
> 
OK.

> > +			return 0;
> > +	}
> > +	return -EBUSY;
> > +}
> 
> [snip]
> 
> > +/*
> > + * pata_s3c_data_xfer - Transfer data by PIO
> > + */
> > +unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char
*buf,
> > +				unsigned int buflen, int rw)
> > +{
> > +	struct ata_port *ap = dev->link->ap;
> > +	struct s3c_ide_info *info = ap->host->private_data;
> > +	void __iomem *data_addr = ap->ioaddr.data_addr;
> > +	unsigned int words = buflen >> 1, i;
> > +	u16 *data_ptr = (u16 *)buf;
> 
> note, is there any chance of being passed a number of bytes? if so
> should we at least WARN_ON(buflen & 1) and return an error?
> 
Will add a WARN_ON.

> > +	if (rw == READ)
> > +		for (i = 0; i < words; i++, data_ptr++) {
> > +			wait_for_host_ready(info);
> > +			*data_ptr = readw(data_addr);
> > +			wait_for_host_ready(info);
> > +			*data_ptr = readw(info->ide_addr
> > +					+ S3C_ATA_PIO_RDATA);
> > +		}

Will add a description for read/write accesses.

> > +	else
> > +		for (i = 0; i < words; i++, data_ptr++) {
> > +			wait_for_host_ready(info);
> > +			writel(*data_ptr, data_addr);
> > +		}
> > +
> > +	return words << 1;
> > +}
> > +
> > +/*
> > + * pata_s3c_dev_select - Select device on ATA bus
> > + */
> > +static void pata_s3c_dev_select(struct ata_port *ap, unsigned int
device)
> > +{
> > +	u8 tmp;
> > +
> > +	if (device == 0)
> > +		tmp = ATA_DEVICE_OBS;
> > +	else
> > +		tmp = ATA_DEVICE_OBS | ATA_DEV1;
> 
> you could have done
>     u8 tmp = ATA_DEVICE_OBS;
> 
>     if (device != 0)
> 	tmp |= ATA_DEV1
> 
> > +	ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
> > +	ata_sff_pause(ap);
> > +}
> > +
> 
> [snip]
> 
> > +static void pata_s3c_enable(void *s3c_ide_regbase, u8 state)
>   state would be better as a bool or a natural int.

OK.

> > +{
> > +	u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
> > +	temp = state ? (temp | 1) : (temp & ~1);
> > +	writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
> > +}
> > +
> > +static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
> > +{
> > +	struct ata_host *host = dev_instance;
> > +	struct s3c_ide_info *info = host->private_data;
> > +	u32 reg;
> > +
> > +	reg = readl(info->ide_addr + S3C_ATA_IRQ);
> > +	writel(reg, info->ide_addr + S3C_ATA_IRQ);
> 
> no decoding of the interrupt cause?
> 
Others interrupts are for udma, mdma and EBI (we are using direct mode) and
so I let them be.

> > +	return ata_sff_interrupt(irq, dev_instance);
> > +}
> 
> > +static int __devexit pata_s3c_remove(struct platform_device *pdev)
> > +{
> > +	struct ata_host *host = platform_get_drvdata(pdev);
> > +	struct s3c_ide_info *info;
> > +	struct resource *res;
> 
> > +
> > +	if (!host)
> > +		return 0;
> 
> don't think this check is really necessary.
> 
OK.

> > +	info = host->private_data;
> > +
> > +	ata_host_detach(host);
> > +
> > +	clk_disable(info->clk);
> > +	clk_put(info->clk);
> > +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	release_mem_region(res->start, resource_size(res));
> > +	kfree(info);
> > +
> > +	return 0;
> > +}
> > +
> > +#ifdef CONFIG_PM
> > +static int pata_s3c_suspend(struct device *dev)
> > +{
> > +	struct platform_device *pdev = to_platform_device(dev);
> > +	struct ata_host *host = platform_get_drvdata(pdev);
> > +	pm_message_t state = PMSG_SUSPEND;
> > +
> > +	if (host)
> > +		return ata_host_suspend(host, state);
> 
> again, don't think you'l lget called here if you didn't sucessfully bind.
> 
OK.

> > +	else
> > +		return 0;
> > +}
> > +
> > +static int pata_s3c_resume(struct device *dev)
> > +{
> > +	struct platform_device *pdev = to_platform_device(dev);
> > +	struct ata_host *host = platform_get_drvdata(pdev);
> > +	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
> > +	struct s3c_ide_info *info;
> > +
> > +	info = host->private_data;
> > +
> > +	if (host) {
> > +		pata_s3c_hwinit(info, pdata);
> > +		ata_host_resume(host);
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> > +static const struct dev_pm_ops pata_s3c_pm_ops = {
> > +	.suspend	= pata_s3c_suspend,
> > +	.resume		= pata_s3c_resume,
> > +};
> 
> --

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From ben-linux at fluff.org  Fri Jun 11 03:54:57 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 08:54:57 +0100
Subject: Pending patches for s5pc110
In-Reply-To: <AANLkTimnuN9h-qka3pRlmaEsR8o6IzFgl3A2YQ5Y28HJ@mail.gmail.com>
References: <AANLkTil0wWSFHpwi58enMhhG7475uUmFoZG6QhRim6Xk@mail.gmail.com>
	<AANLkTimjwSHLiMYFywn3vHZYCbqQCCCh9qE-n3xuYOaq@mail.gmail.com>
	<20100611051521.GV7248@trinity.fluff.org>
	<AANLkTikJQnDEjVunmiCLGaVAnj5bR7JdsUZYJ9xAEdE5@mail.gmail.com>
	<20100611062300.GY7248@trinity.fluff.org>
	<AANLkTimnuN9h-qka3pRlmaEsR8o6IzFgl3A2YQ5Y28HJ@mail.gmail.com>
Message-ID: <20100611075457.GZ7248@trinity.fluff.org>

On Fri, Jun 11, 2010 at 04:07:58PM +0900, Kyungmin Park wrote:
> On Fri, Jun 11, 2010 at 3:23 PM, Ben Dooks <ben-linux at fluff.org> wrote:
> > On Fri, Jun 11, 2010 at 02:38:56PM +0900, Kyungmin Park wrote:
> >> On Fri, Jun 11, 2010 at 2:15 PM, Ben Dooks <ben-linux at fluff.org> wrote:
> >> > On Fri, Jun 11, 2010 at 01:25:18PM +0900, Kyungmin Park wrote:
> >> >> Hi,
> >> >>
> >> >> No comments mean it's okay then we will prepare the patches to git pull.
> >> >
> >> > No. no comments means that people either haven't had time to sort
> >> > them out or in fact ON HOLIDAY.
> >>
> >> but you usually missed our patches frequently. with this reason our
> >> patches can't merge within proper merge window.
> >
> > I belive the last set where either being posted just-before or during
> > the last merge window. We already had far too much queueud up then and
> > we where trying to ensure that the already-queued entries where processed.
> 
> Not tell this case, please see the s5pc110 patches last year. last
> year we sent the s5pc110 related patches several times. but you don't
> give any opinions and can't accept without any reason.

I gave you comments, or at least Marke should have got them for the
series sent in November, then there's nothing in my mailbox since
then.
 
> Well it's past story,  forget it.
> 
> Last question.
> 
> I think you share the s3c maintainer-ship with Kukjin. Can you explain
> the criteria?

Ok, here's the list:

1) SystemLSI are the best placed to see all the chips in development,
   since they're the ones making them. You are only dealing with a
   subset of their output (generally the S5PC100 and S5PC110) whereas
   there are many more devices in the line.

2) SystemLSI have spent time talking to me about what they need to do
   when maintaining a system and trying to acquire the necessary skills
   for managing a port.

This does not mean that you cannot be included at a later date.

As a note, that I have left myself in the maintainers entries for the
samsung series and will re-visit this once we see how well the transfer
goes in the next kernel release or two.
 
-- 
Ben




From jeremy.kerr at canonical.com  Fri Jun 11 03:57:10 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Fri, 11 Jun 2010 15:57:10 +0800
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100611042046.GA31045@fluff.org.uk>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<1275636608.607067.417709988883.1.gpush@pororo>
	<20100611042046.GA31045@fluff.org.uk>
Message-ID: <201006111557.12249.jeremy.kerr@canonical.com>

Hi Ben,

> > Platforms can enable the generic struct clock through
> > CONFIG_USE_COMMON_STRUCT_CLK. In this case, the clock infrastructure
> > consists of a common struct clk:
>
> What do people think of just changing everyone who is currently using
> clk support to using this new implementation?

I think it'd be too-big a task to take on for a single change; we'd be better 
off allowing the two implementations concurrently. Also, I'd say that there 
are many platforms that will never need the new code, so no need to change 
them over.

> > struct clk {
> > 
> > 	const struct clk_ops	*ops;
> > 	unsigned int		enable_count;
> > 	struct mutex		mutex;
> 
> I'm a little worried about the size of struct clk if all of them
> have a mutex in them. If i'm right, this is 40 bytes of data each
> clock has to take on board.

Yeah, I see your concern about adding a mutex per clock, but I do think it's 
the best solution. Of course, if there's a better way to do it, I'm happy to 
try it out.

I believe we need to ensure that clocks are enabled when clk_enable returns, 
so we'll need some mechanism for waiting on the thread doing the 
enable/disable. Since (as you say) some clocks may take 100s of microseconds 
to enable, we'll need a lock that we can hold while sleeping.

We could use a global mutex for all clocks, but that would complicate the 
interface by requiring non-locking versions of enable/disable, to allow 
recursive enable/disable of parent clocks. Also, we'd lose any parallelism 
possible in clock initialisation (we want boot to be fast, right?)

Without all the debug stuff, it looks like a mutex is 12 bytes on UP, 20 on 
SMP. That brings the maximum possible overhead to 26kB/43kB. More tolerable, 
but not great.

You know what would be awesome? if we could put platform-specific code in 
their own sections and the discard the ones we know we won't need after boot. 
But that's a discussion for another day...

> >        int             (*enable)(struct clk *);
> 
> still think that not passing an bool as a second argument is silly.

Still don't :D

> > +struct clk {
> > +	const struct clk_ops	*ops;
> > +	unsigned int		enable_count;
> > +	struct mutex		mutex;
> > +};
> 
> how about defining a nice kerneldoc for this.

Shall do. I've also decided to un-inline the base API, which means that I can 
use all of the existing prototypes in clk.h, which means the kerneldoc is 
shared too.

> > +#define INIT_CLK(name, o) \
> > +	{ .ops = &o, .enable_count = 0, \
> > +		.mutex = __MUTEX_INITIALIZER(name.mutex) }
> 
> how about doing the mutex initinitialisation at registration
> time, will save a pile of non-zero code in the image to mess up
> the compression.

I've just yesterday added the following to my tree, to allow dynamic 
initialisation:

static inline void clk_init(struct clk *clk, const struct clk_ops *ops)
{
	clk->ops = ops;
	clk->enable_count = 0;
	mutex_init(&clk->mutex);
}

So we can do this either way.

> ~> +struct clk_ops {
> 
> > +       int             (*enable)(struct clk *);
> > +       void            (*disable)(struct clk *);
> > +       unsigned long   (*get_rate)(struct clk *);
> > +       void            (*put)(struct clk *);
> > +       long            (*round_rate)(struct clk *, unsigned long);
> > +       int             (*set_rate)(struct clk *, unsigned long);
> > +       int             (*set_parent)(struct clk *, struct clk *);
> > +       struct clk*     (*get_parent)(struct clk *);
> 
> should each clock carry a parent field and the this is returned by
> the get parent call.~~

I've been debating dropping the get_parent and set_parent ops entirely, 
actually; setting a parent seems to be quite specific to hardware (you have to 
know that a particular clock can be a parent of another clock), so it seems 
like something that we shouldn't expose to drivers through this API. For the 
code that knows the hardware, it can probably access the underlying clock 
types directly.

However, I see that something in the samsung code uses clk_get_parent for what 
seems like a sane purpose, so have left them in for now. Or could this be done 
differently?

> > +static inline int clk_enable(struct clk *clk)
> > +{
> > +	int ret = 0;
> > +
> > +	if (!clk->ops->enable)
> > +		return 0;
> > +
> > +	mutex_lock(&clk->mutex);
> > +	if (!clk->enable_count)
> > +		ret = clk->ops->enable(clk);
> > +
> > +	if (!ret)
> > +		clk->enable_count++;
> > +	mutex_unlock(&clk->mutex);
> > +
> > +	return ret;
> > +}
> 
> So we're leaving the enable parent code now to each implementation?
> 
> I think this is a really bad decision, it leaves so much open to bad
> code repetition, as well as something the core should really be doing
> if it had a parent clock field.

I'm tempted to go in either direction - either no [sg]et_parent in the clk 
API, or add a parent to struct clk, but first I'd need to get up to speed on 
the external uses of the clk's parent. Want to catch me on IRC to discuss?

> ~> +static inline void clk_disable(struct clk *clk)
> 
> > +{
> > +	if (!clk->ops->enable)
> > +		return;
> 
> so if we've no enable call we ignore disable too?

Typo; this should be "if (!clk->ops->disable)". Will fix for the next 
revision.

> also, we don't keep an enable count if this fields are in use,
> could people rely on this being correct even if the clock has
> no enable/disable fields.
> 
> Would much rather see the enable_count being kept up-to-date
> no matter what, given it may be watched by other parts of the
> implementation, useful for debug info, and possibly useful if
> later in the start sequence the clk_ops get changed to have this
> field.~

Checking for the ops first allows us to skip the mutex acquire, but I'm happy 
either way.

> > +~	mutex_lock(&clk->mutex);
> > +
> > +	if (!--clk->enable_count)
> > +		clk->ops->disable(clk);
> > +
> > +	mutex_unlock(&clk->mutex);
> > +}
> > +
> > +static inline unsigned long clk_get_rate(struct clk *clk)
> > +{
> > +	if (clk->ops->get_rate)
> > +		return clk->ops->get_rate(clk);
> > +	return 0;
> > +}
> > +
> > +static inline void clk_put(struct clk *clk)
> > +{
> > +	if (clk->ops->put)
> > +		clk->ops->put(clk);
> > +}
> 
> I'm beginging to wonder if we don't just have a set of default ops
> that get set into the clk+ops at registration time if these do
> not have an implementation.

Using default ops would mean a couple of things:

1) we can no longer mark the real ops as const; and
2) we can no longer avoid the hard-to-predict indirect branch

> this means that either any driver that is using a multi-parent clock
> has to deal with the proper enable/disable of the parents (this is
> is going to lead to code repetition, and I bet people will get it
> badly wrong).
> 
> I belive the core of the clock code should deal with this, since
> otherwise we end up with the situation of the same code being
> repeated throughout the kernel.

I see the concern here, but I'll defer this one until we've decided on whether 
or not the parents should be exposed through the API.

Cheers,


Jeremy


From jy0922.shim at samsung.com  Fri Jun 11 04:08:46 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 11 Jun 2010 17:08:46 +0900
Subject: [PATCH v4 1/3] ARM: SAMSUNG: Add keypad device support
Message-ID: <1276243728-17704-1-git-send-email-jy0922.shim@samsung.com>

This patch adds samsung keypad device definition for samsung cpus.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-samsung/Kconfig                    |    5 ++
 arch/arm/plat-samsung/Makefile                   |    1 +
 arch/arm/plat-samsung/dev-keypad.c               |   58 +++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h        |    2 +
 arch/arm/plat-samsung/include/plat/keypad.h      |   59 ++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/regs-keypad.h |   49 ++++++++++++++++++
 6 files changed, 174 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-samsung/dev-keypad.c
 create mode 100644 arch/arm/plat-samsung/include/plat/keypad.h
 create mode 100644 arch/arm/plat-samsung/include/plat/regs-keypad.h

diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 2753fb3..bd007e3 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -227,6 +227,11 @@ config SAMSUNG_DEV_TS
 	help
 	    Common in platform device definitions for touchscreen device
 
+config SAMSUNG_DEV_KEYPAD
+	bool
+	help
+	  Compile in platform device definitions for keypad
+
 # DMA
 
 config S3C_DMA
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index b1d82cc..8269d80 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_S3C_DEV_RTC)	+= dev-rtc.o
 
 obj-$(CONFIG_SAMSUNG_DEV_ADC)	+= dev-adc.o
 obj-$(CONFIG_SAMSUNG_DEV_TS)	+= dev-ts.o
+obj-$(CONFIG_SAMSUNG_DEV_KEYPAD)	+= dev-keypad.o
 
 # DMA support
 
diff --git a/arch/arm/plat-samsung/dev-keypad.c b/arch/arm/plat-samsung/dev-keypad.c
new file mode 100644
index 0000000..679b444
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-keypad.c
@@ -0,0 +1,58 @@
+/*
+ * linux/arch/arm/plat-samsung/dev-keypad.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/keypad.h>
+
+static struct resource samsung_keypad_resources[] = {
+	[0] = {
+		.start	= SAMSUNG_PA_KEYPAD,
+		.end	= SAMSUNG_PA_KEYPAD + 0x20 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_KEYPAD,
+		.end	= IRQ_KEYPAD,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device samsung_device_keypad = {
+	.name		= "samsung-keypad",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(samsung_keypad_resources),
+	.resource	= samsung_keypad_resources,
+};
+
+void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
+{
+	struct samsung_keypad_platdata *npd;
+
+	if (!pd) {
+		printk(KERN_ERR "%s: no platform data\n", __func__);
+		return;
+	}
+
+	npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
+	if (!npd)
+		printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+
+	if (!npd->cfg_gpio)
+		npd->cfg_gpio = samsung_keypad_cfg_gpio;
+
+	samsung_device_keypad.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index e6144e4..6d9f01b 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -100,6 +100,8 @@ extern struct platform_device s5pc100_device_iis0;
 extern struct platform_device s5pc100_device_iis1;
 extern struct platform_device s5pc100_device_iis2;
 
+extern struct platform_device samsung_device_keypad;
+
 /* s3c2440 specific devices */
 
 #ifdef CONFIG_CPU_S3C2440
diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/plat-samsung/include/plat/keypad.h
new file mode 100644
index 0000000..6d139d6
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/keypad.h
@@ -0,0 +1,59 @@
+/*
+ * linux/arch/arm/plat-samsung/include/plat/keypad.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ * Samsung Platform - Keypad platform data definitions
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __PLAT_SAMSUNG_KEYPAD_H
+#define __PLAT_SAMSUNG_KEYPAD_H
+
+#include <linux/input/matrix_keypad.h>
+
+#define SAMSUNG_MAX_ROWS	8
+#define SAMSUNG_MAX_COLS	8
+
+/**
+ * struct samsung_keypad_platdata - Platform device data for Samsung Keypad.
+ * @keymap_data: pointer to &matrix_keymap_data.
+ * @rows: number of keypad row supported.
+ * @cols: number of keypad col supported.
+ * @no_autorepeat: disable key autorepeat.
+ * @wakeup: controls whether the device should be set up as wakeup source.
+ * @cfg_gpio: configure the GPIO.
+ *
+ * Initialisation data specific to either the machine or the platform
+ * for the device driver to use or call-back when configuring gpio.
+ */
+struct samsung_keypad_platdata {
+	const struct matrix_keymap_data	*keymap_data;
+	unsigned int		rows;
+	unsigned int		cols;
+	bool			no_autorepeat;
+	bool			wakeup;
+
+	void	(*cfg_gpio)(unsigned int rows, unsigned int cols);
+};
+
+/**
+ * samsung_keypad_set_platdata - Set platform data for Samsung Keypad device.
+ * @pd: Platform data to register to device.
+ *
+ * Register the given platform data for use with Samsung Keypad device.
+ * The call will copy the platform data, so the board definitions can
+ * make the structure itself __initdata.
+ */
+extern void samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd);
+
+/* defined by architecture to configure gpio. */
+extern void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols);
+
+#endif /* __PLAT_SAMSUNG_KEYPAD_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-keypad.h b/arch/arm/plat-samsung/include/plat/regs-keypad.h
new file mode 100644
index 0000000..e4688f0
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-keypad.h
@@ -0,0 +1,49 @@
+/*
+ * linux/arch/arm/plat-samsung/include/plat/regs-keypad.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __SAMSUNG_KEYPAD_H__
+#define __SAMSUNG_KEYPAD_H__
+
+#define SAMSUNG_KEYIFCON			0x00
+#define SAMSUNG_KEYIFSTSCLR			0x04
+#define SAMSUNG_KEYIFCOL			0x08
+#define SAMSUNG_KEYIFROW			0x0c
+#define SAMSUNG_KEYIFFC				0x10
+
+/* SAMSUNG_KEYIFCON */
+#define SAMSUNG_KEYIFCON_INT_F_EN		(1 << 0)
+#define SAMSUNG_KEYIFCON_INT_R_EN		(1 << 1)
+#define SAMSUNG_KEYIFCON_DF_EN			(1 << 2)
+#define SAMSUNG_KEYIFCON_FC_EN			(1 << 3)
+#define SAMSUNG_KEYIFCON_WAKEUPEN		(1 << 4)
+
+/* SAMSUNG_KEYIFSTSCLR */
+#define SAMSUNG_KEYIFSTSCLR_P_INT_MASK		(0xff << 0)
+#define SAMSUNG_KEYIFSTSCLR_R_INT_MASK		(0xff << 8)
+#define SAMSUNG_KEYIFSTSCLR_R_INT_OFFSET	8
+#define S5PV210_KEYIFSTSCLR_P_INT_MASK		(0x3fff << 0)
+#define S5PV210_KEYIFSTSCLR_R_INT_MASK		(0x3fff << 16)
+#define S5PV210_KEYIFSTSCLR_R_INT_OFFSET	16
+
+/* SAMSUNG_KEYIFCOL */
+#define SAMSUNG_KEYIFCOL_MASK			(0xff << 0)
+#define S5PV210_KEYIFCOLEN_MASK			(0xff << 8)
+
+/* SAMSUNG_KEYIFROW */
+#define SAMSUNG_KEYIFROW_MASK			(0xff << 0)
+#define S5PV210_KEYIFROW_MASK			(0x3fff << 0)
+
+/* SAMSUNG_KEYIFFC */
+#define SAMSUNG_KEYIFFC_MASK			(0x3ff << 0)
+
+#endif /* __SAMSUNG_KEYPAD_H__ */
-- 
1.7.0.4



From kgene.kim at samsung.com  Fri Jun 11 04:08:09 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 11 Jun 2010 17:08:09 +0900
Subject: [PATCH] sdhci-s3c: Add SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK quirk
	for Samsung SoC
In-Reply-To: <AANLkTim2LzIh7dadCAWCo6jltS4CYA8gLKaiQne_VzqK@mail.gmail.com>
References: <1276169991-16396-1-git-send-email-kgene.kim@samsung.com>
	<AANLkTim2LzIh7dadCAWCo6jltS4CYA8gLKaiQne_VzqK@mail.gmail.com>
Message-ID: <003901cb093d$3dd14110$b973c330$%kim@samsung.com>

Kyungmin Park wrote:
> 
> Hi,
> 
> On Thu, Jun 10, 2010 at 8:39 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > From: Lee Hyuk <hyuk1.lee at samsung.com>
> >
> > On Samsung's SDMMC hosts the timeout clock is derivied from the SD
> > Clock, which is set dynamically.
> > So, checked 'SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK' quirk and removed
> > 'sdhci_s3c_get_timeout_clk' callback which doesn't need any more.
> >
> > Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> > ---
> > ?drivers/mmc/host/sdhci-s3c.c | ? 10 +++-------
> > ?1 files changed, 3 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> > index af21792..ca09382 100644
> > --- a/drivers/mmc/host/sdhci-s3c.c
> > +++ b/drivers/mmc/host/sdhci-s3c.c
> > @@ -110,11 +110,6 @@ static unsigned int sdhci_s3c_get_max_clk(struct
> sdhci_host *host)
> > ? ? ? ?return max;
> > ?}
> >
> > -static unsigned int sdhci_s3c_get_timeout_clk(struct sdhci_host *host)
> > -{
> > - ? ? ? return sdhci_s3c_get_max_clk(host) / 1000000;
> > -}
> > -
> > ?/**
> > ?* sdhci_s3c_consider_clock - consider one the bus clocks for current
setting
> > ?* @ourhost: Our SDHCI instance.
> > @@ -188,7 +183,6 @@ static void sdhci_s3c_set_clock(struct sdhci_host
*host,
> unsigned int clock)
> >
> > ? ? ? ? ? ? ? ?ourhost->cur_clk = best_src;
> > ? ? ? ? ? ? ? ?host->max_clk = clk_get_rate(clk);
> > - ? ? ? ? ? ? ? host->timeout_clk = sdhci_s3c_get_timeout_clk(host);
> >
> > ? ? ? ? ? ? ? ?ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
> > ? ? ? ? ? ? ? ?ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
> > @@ -211,7 +205,6 @@ static void sdhci_s3c_set_clock(struct sdhci_host
*host,
> unsigned int clock)
> >
> > ?static struct sdhci_ops sdhci_s3c_ops = {
> > ? ? ? ?.get_max_clock ? ? ? ? ?= sdhci_s3c_get_max_clk,
> > - ? ? ? .get_timeout_clock ? ? ?= sdhci_s3c_get_timeout_clk,
> > ? ? ? ?.set_clock ? ? ? ? ? ? ?= sdhci_s3c_set_clock,
> > ?};
> >
> > @@ -335,6 +328,9 @@ static int __devinit sdhci_s3c_probe(struct
> platform_device *pdev)
> > ? ? ? ?host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
> > ? ? ? ? ? ? ? ? ? ? ? ? SDHCI_QUIRK_32BIT_DMA_SIZE);
> >
> > + ? ? ? /* HSMMC on Samsung SoCs uses SDCLK as timeout clock. */
> > + ? ? ? host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
> 
> How do you know Samsung SoCs use SDCLK in the spec?
>
Samsung SoC hardware engineer guided about that.

> Is it also true at s3c64xx series?
> 
Yes, of course.



> 
> > +
> > ? ? ? ?ret = sdhci_add_host(host);
> > ? ? ? ?if (ret) {
> > ? ? ? ? ? ? ? ?dev_err(dev, "sdhci_add_host() failed\n");
> > --
> > 1.6.2.5
> >
> > --

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From jy0922.shim at samsung.com  Fri Jun 11 04:08:47 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 11 Jun 2010 17:08:47 +0900
Subject: [PATCH v4 2/3] ARM: S5PV210: Add keypad device helpers
In-Reply-To: <1276243728-17704-1-git-send-email-jy0922.shim@samsung.com>
References: <1276243728-17704-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1276243728-17704-2-git-send-email-jy0922.shim@samsung.com>

This patch adds the keypad device platform helpers for S5PV210 cpu.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pv210/Kconfig            |    5 ++++
 arch/arm/mach-s5pv210/Makefile           |    1 +
 arch/arm/mach-s5pv210/cpu.c              |    4 +++
 arch/arm/mach-s5pv210/include/mach/map.h |    3 ++
 arch/arm/mach-s5pv210/setup-keypad.c     |   34 ++++++++++++++++++++++++++++++
 5 files changed, 47 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pv210/setup-keypad.c

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0761eac..692d01c 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -32,6 +32,11 @@ config S5PV210_SETUP_FB_24BPP
 	help
           Common setup code for S5PV210 with an 24bpp RGB display helper.
 
+config S5PV210_SETUP_KEYPAD
+	bool
+	help
+	  Common setup code for keypad.
+
 config S5PV210_SETUP_SDHCI
         bool
         select S5PV210_SETUP_SDHCI_GPIO
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 30be9a6..aae592a 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o
 obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
 obj-$(CONFIG_S5PV210_SETUP_I2C1) 	+= setup-i2c1.o
 obj-$(CONFIG_S5PV210_SETUP_I2C2) 	+= setup-i2c2.o
+obj-$(CONFIG_S5PV210_SETUP_KEYPAD)	+= setup-keypad.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 411a4a9..a3034ac 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -80,6 +80,10 @@ void __init s5pv210_map_io(void)
 	s3c_device_adc.name	= "s3c64xx-adc";
 #endif
 
+#ifdef CONFIG_SAMSUNG_DEV_KEYPAD
+	samsung_device_keypad.name = "s5pv210-keypad";
+#endif
+
 	iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
 
 	/* initialise device information early */
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 34eb168..e2f6e2a 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -32,6 +32,8 @@
 #define S5PV210_PA_SPI0		0xE1300000
 #define S5PV210_PA_SPI1		0xE1400000
 
+#define S5PV210_PA_KEYPAD	(0xE1600000)
+
 #define S5PV210_PA_IIC0		(0xE1800000)
 #define S5PV210_PA_IIC1		(0xFAB00000)
 #define S5PV210_PA_IIC2		(0xE1A00000)
@@ -104,5 +106,6 @@
 #define S3C_PA_WDT		S5PV210_PA_WATCHDOG
 
 #define SAMSUNG_PA_ADC		S5PV210_PA_ADC
+#define SAMSUNG_PA_KEYPAD	S5PV210_PA_KEYPAD
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/setup-keypad.c b/arch/arm/mach-s5pv210/setup-keypad.c
new file mode 100644
index 0000000..f51bf8d
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-keypad.c
@@ -0,0 +1,34 @@
+/*
+ * linux/arch/arm/mach-s5pv210/setup-keypad.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+
+void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
+{
+	unsigned int gpio, end;
+
+	/* Set all the necessary GPH3 pins to special-function 3 */
+	end = S5PV210_GPH3(rows);
+	for (gpio = S5PV210_GPH3(0); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* Set all the necessary GPH2 pins to special-function 3 */
+	end = S5PV210_GPH2(cols);
+	for (gpio = S5PV210_GPH2(0); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+}
-- 
1.7.0.4



From jy0922.shim at samsung.com  Fri Jun 11 04:08:44 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 11 Jun 2010 17:08:44 +0900
Subject: [PATCH v4 0/3] Add samsung keypad
Message-ID: <4C11EF0C.8060109@samsung.com>

This is patch v4 series to add Samsung keypad. I've removed board file
patchs for samsung-keypad support in the v4, They don't have any change
but i will post later because of dependence problem with other patches.

Changes since v1:
- Include linux/gpio.h instead of mach/gpio.h
- Switch to dev_pm_ops in the samsung keypad driver

Changes since v2:
- Add keypad device types to remove platform specific #ifdef
- Remove unnecessary include and checking codes.
- Rename from 'kp' to 'keypad'
- Rename keypad registers definition
- Modify 'rep' variable declaration

Changes since v3:
- Use schedule_delayed_work and remove timer
- Modify memory alloc codes
- Add MODULE_ALIAS() and missing error printk
- Change from rep to no_autorepeat and it's type to bool
- Add report EV_MSC/MSC_SCAN and wakeup control
- Remove s3c_set_platdata() call because there is not yet

Joonyoung Shim (3):
      ARM: SAMSUNG: Add keypad device support
      ARM: S5PV210: Add keypad device helpers
      input: samsung-keypad - Add samsung keypad driver

 arch/arm/mach-s5pv210/Kconfig                    |    5 +
 arch/arm/mach-s5pv210/Makefile                   |    1 +
 arch/arm/mach-s5pv210/cpu.c                      |    4 +
 arch/arm/mach-s5pv210/include/mach/map.h         |    3 +
 arch/arm/mach-s5pv210/setup-keypad.c             |   34 ++
 arch/arm/plat-samsung/Kconfig                    |    5 +
 arch/arm/plat-samsung/Makefile                   |    1 +
 arch/arm/plat-samsung/dev-keypad.c               |   58 ++++
 arch/arm/plat-samsung/include/plat/devs.h        |    2 +
 arch/arm/plat-samsung/include/plat/keypad.h      |   59 ++++
 arch/arm/plat-samsung/include/plat/regs-keypad.h |   49 +++
 drivers/input/keyboard/Kconfig                   |    9 +
 drivers/input/keyboard/Makefile                  |    1 +
 drivers/input/keyboard/samsung-keypad.c          |  400 ++++++++++++++++++++++
 14 files changed, 631 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pv210/setup-keypad.c
 create mode 100644 arch/arm/plat-samsung/dev-keypad.c
 create mode 100644 arch/arm/plat-samsung/include/plat/keypad.h
 create mode 100644 arch/arm/plat-samsung/include/plat/regs-keypad.h
 create mode 100644 drivers/input/keyboard/samsung-keypad.c


From jy0922.shim at samsung.com  Fri Jun 11 04:08:48 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 11 Jun 2010 17:08:48 +0900
Subject: [PATCH v4 3/3] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <1276243728-17704-1-git-send-email-jy0922.shim@samsung.com>
References: <1276243728-17704-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1276243728-17704-3-git-send-email-jy0922.shim@samsung.com>

This patch adds support for keypad driver running on Samsung cpus. This
driver is tested on GONI and Aquila board using S5PC110 cpu.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/input/keyboard/Kconfig          |    9 +
 drivers/input/keyboard/Makefile         |    1 +
 drivers/input/keyboard/samsung-keypad.c |  400 +++++++++++++++++++++++++++++++
 3 files changed, 410 insertions(+), 0 deletions(-)
 create mode 100644 drivers/input/keyboard/samsung-keypad.c

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index d8fa5d7..bf6a50f 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -342,6 +342,15 @@ config KEYBOARD_PXA930_ROTARY
 	  To compile this driver as a module, choose M here: the
 	  module will be called pxa930_rotary.
 
+config KEYBOARD_SAMSUNG
+	tristate "Samsung keypad support"
+	depends on SAMSUNG_DEV_KEYPAD
+	help
+	  Say Y here if you want to use the Samsung keypad.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called samsung-keypad.
+
 config KEYBOARD_STOWAWAY
 	tristate "Stowaway keyboard"
 	select SERIO
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 4596d0c..8f973ed 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_KEYBOARD_OPENCORES)	+= opencores-kbd.o
 obj-$(CONFIG_KEYBOARD_PXA27x)		+= pxa27x_keypad.o
 obj-$(CONFIG_KEYBOARD_PXA930_ROTARY)	+= pxa930_rotary.o
 obj-$(CONFIG_KEYBOARD_QT2160)		+= qt2160.o
+obj-$(CONFIG_KEYBOARD_SAMSUNG)		+= samsung-keypad.o
 obj-$(CONFIG_KEYBOARD_SH_KEYSC)		+= sh_keysc.o
 obj-$(CONFIG_KEYBOARD_STOWAWAY)		+= stowaway.o
 obj-$(CONFIG_KEYBOARD_SUNKBD)		+= sunkbd.o
diff --git a/drivers/input/keyboard/samsung-keypad.c b/drivers/input/keyboard/samsung-keypad.c
new file mode 100644
index 0000000..4b56e6f
--- /dev/null
+++ b/drivers/input/keyboard/samsung-keypad.c
@@ -0,0 +1,400 @@
+/*
+ * samsung-keypad.c  --  Samsung keypad driver
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ * Author: Donghwa Lee <dh09.lee at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <plat/keypad.h>
+#include <plat/regs-keypad.h>
+
+enum samsung_keypad_type {
+	KEYPAD_TYPE_SAMSUNG,
+	KEYPAD_TYPE_S5PV210,
+};
+
+struct samsung_keypad {
+	struct input_dev *input_dev;
+	struct clk *clk;
+	struct delayed_work work;
+	void __iomem *base;
+	unsigned short *keycodes;
+	unsigned int row_shift;
+	unsigned int rows;
+	unsigned int cols;
+	unsigned int row_state[SAMSUNG_MAX_COLS];
+	int irq;
+};
+
+static int samsung_keypad_is_s5pv210(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	enum samsung_keypad_type type;
+
+	type = platform_get_device_id(pdev)->driver_data;
+	return type == KEYPAD_TYPE_S5PV210;
+}
+
+static void samsung_keypad_scan(struct samsung_keypad *keypad,
+		unsigned int *row_state)
+{
+	struct device *dev = keypad->input_dev->dev.parent;
+	unsigned int col;
+	unsigned int val;
+
+	for (col = 0; col < keypad->cols; col++) {
+		if (samsung_keypad_is_s5pv210(dev)) {
+			val = S5PV210_KEYIFCOLEN_MASK;
+			val &= ~(1 << col) << 8;
+		} else {
+			val = SAMSUNG_KEYIFCOL_MASK;
+			val &= ~(1 << col);
+		}
+
+		writel(val, keypad->base + SAMSUNG_KEYIFCOL);
+		mdelay(1);
+
+		val = readl(keypad->base + SAMSUNG_KEYIFROW);
+		row_state[col] = ~val & ((1 << keypad->rows) - 1);
+	}
+
+	/* KEYIFCOL reg clear */
+	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+}
+
+static void samsung_keypad_worker(struct work_struct *work)
+{
+	struct samsung_keypad *keypad = container_of(work,
+			struct samsung_keypad, work.work);
+	unsigned int row_state[SAMSUNG_MAX_COLS];
+	unsigned int val;
+	unsigned int changed;
+	unsigned int pressed;
+	unsigned int key_down = 0;
+	int col, row;
+
+	clk_enable(keypad->clk);
+
+	val = readl(keypad->base + SAMSUNG_KEYIFSTSCLR);
+
+	/* interrupt clear */
+	writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR);
+
+	val = readl(keypad->base + SAMSUNG_KEYIFCON);
+	val &= ~(SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN);
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	samsung_keypad_scan(keypad, row_state);
+
+	for (col = 0; col < keypad->cols; col++) {
+		changed = row_state[col] ^ keypad->row_state[col];
+		key_down |= row_state[col];
+		if (!changed)
+			continue;
+
+		for (row = 0; row < keypad->rows; row++) {
+			if (!(changed & (1 << row)))
+				continue;
+
+			pressed = row_state[col] & (1 << row);
+
+			dev_dbg(&keypad->input_dev->dev,
+				"key %s, row: %d, col: %d\n",
+				pressed ? "pressed" : "released", row, col);
+
+			val = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
+
+			input_event(keypad->input_dev, EV_MSC, MSC_SCAN, val);
+			input_report_key(keypad->input_dev,
+					keypad->keycodes[val], pressed);
+			input_sync(keypad->input_dev);
+		}
+	}
+	memcpy(keypad->row_state, row_state, sizeof(row_state));
+
+	if (key_down)
+		schedule_delayed_work(&keypad->work, HZ / 20);
+	else {
+		/* enable interrupt bit */
+		val = readl(keypad->base + SAMSUNG_KEYIFCON);
+		val |= (SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN);
+		writel(val, keypad->base + SAMSUNG_KEYIFCON);
+		enable_irq(keypad->irq);
+	}
+	clk_disable(keypad->clk);
+}
+
+static irqreturn_t samsung_keypad_interrupt(int irq, void *dev_id)
+{
+	struct samsung_keypad *keypad = dev_id;
+
+	if (!work_pending(&keypad->work.work)) {
+		disable_irq_nosync(keypad->irq);
+		schedule_delayed_work(&keypad->work, 0);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int __devinit samsung_keypad_probe(struct platform_device *pdev)
+{
+	const struct samsung_keypad_platdata *pdata;
+	const struct matrix_keymap_data *keymap_data;
+	struct samsung_keypad *keypad;
+	struct resource *res;
+	struct input_dev *input_dev;
+	unsigned short *keycodes;
+	unsigned int row_shift;
+	unsigned int val;
+	int ret;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "no platform data defined\n");
+		return -EINVAL;
+	}
+
+	keymap_data = pdata->keymap_data;
+	if (!keymap_data) {
+		dev_err(&pdev->dev, "no keymap data defined\n");
+		return -EINVAL;
+	}
+
+	if (!pdata->rows || (pdata->rows > SAMSUNG_MAX_ROWS))
+		return -EINVAL;
+
+	if (!pdata->cols || (pdata->cols > SAMSUNG_MAX_COLS))
+		return -EINVAL;
+
+	/* initialize the gpio */
+	if (pdata->cfg_gpio)
+		pdata->cfg_gpio(pdata->rows, pdata->cols);
+
+	row_shift = get_count_order(pdata->cols);
+	/* alloc with keycodes memory */
+	keypad = kzalloc(sizeof(*keypad) + sizeof(*keycodes) *
+			(pdata->rows << row_shift), GFP_KERNEL);
+	input_dev = input_allocate_device();
+	if (!keypad || !input_dev) {
+		ret = -ENOMEM;
+		goto err_free_mem;
+	}
+	keycodes = (unsigned short *)(keypad + 1);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		ret = -ENODEV;
+		goto err_free_mem;
+	}
+
+	keypad->base = ioremap(res->start, resource_size(res));
+	if (!keypad->base) {
+		ret = -EBUSY;
+		goto err_free_mem;
+	}
+
+	keypad->clk = clk_get(&pdev->dev, "keypad");
+	if (IS_ERR(keypad->clk)) {
+		dev_err(&pdev->dev, "failed to get keypad clk\n");
+		ret = PTR_ERR(keypad->clk);
+		goto err_unmap_base;
+	}
+	clk_enable(keypad->clk);
+
+	keypad->input_dev = input_dev;
+	keypad->keycodes = keycodes;
+	keypad->row_shift = row_shift;
+	keypad->rows = pdata->rows;
+	keypad->cols = pdata->cols;
+
+	INIT_DELAYED_WORK(&keypad->work, samsung_keypad_worker);
+
+	/* enable interrupt and wakeup bit */
+	val = SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN |
+		SAMSUNG_KEYIFCON_WAKEUPEN;
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	/* KEYIFCOL reg clear */
+	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+
+	keypad->irq = platform_get_irq(pdev, 0);
+	if (keypad->irq < 0) {
+		ret = keypad->irq;
+		goto err_disable_clk;
+	}
+
+	ret = request_irq(keypad->irq, samsung_keypad_interrupt, 0,
+			dev_name(&pdev->dev), keypad);
+
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register keypad interrupt\n");
+		goto err_disable_clk;
+	}
+
+	input_dev->name = pdev->name;
+	input_dev->id.bustype = BUS_HOST;
+	input_dev->dev.parent = &pdev->dev;
+
+	input_dev->evbit[0] = BIT_MASK(EV_KEY);
+	if (!pdata->no_autorepeat)
+		input_dev->evbit[0] |= BIT_MASK(EV_REP);
+
+	input_dev->keycode = keycodes;
+	input_dev->keycodesize = sizeof(*keycodes);
+	input_dev->keycodemax = pdata->rows << row_shift;
+
+	matrix_keypad_build_keymap(keymap_data, row_shift,
+			input_dev->keycode, input_dev->keybit);
+
+	input_set_capability(input_dev, EV_MSC, MSC_SCAN);
+
+	ret = input_register_device(keypad->input_dev);
+	if (ret)
+		goto err_free_irq;
+
+	device_init_wakeup(&pdev->dev, pdata->wakeup);
+	platform_set_drvdata(pdev, keypad);
+	clk_disable(keypad->clk);
+
+	return 0;
+
+err_free_irq:
+	free_irq(keypad->irq, keypad);
+err_disable_clk:
+	clk_disable(keypad->clk);
+	clk_put(keypad->clk);
+err_unmap_base:
+	iounmap(keypad->base);
+err_free_mem:
+	input_free_device(input_dev);
+	kfree(keypad);
+
+	return ret;
+}
+
+static int __devexit samsung_keypad_remove(struct platform_device *pdev)
+{
+	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+
+	device_init_wakeup(&pdev->dev, 0);
+
+	free_irq(keypad->irq, keypad);
+	cancel_delayed_work_sync(&keypad->work);
+
+	platform_set_drvdata(pdev, NULL);
+	input_unregister_device(keypad->input_dev);
+
+	clk_disable(keypad->clk);
+	clk_put(keypad->clk);
+
+	iounmap(keypad->base);
+	kfree(keypad);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int samsung_keypad_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+
+	disable_irq(keypad->irq);
+
+	if (device_may_wakeup(&pdev->dev))
+		enable_irq_wake(keypad->irq);
+
+	return 0;
+}
+
+static int samsung_keypad_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+	unsigned int val;
+
+	if (device_may_wakeup(&pdev->dev))
+		disable_irq_wake(keypad->irq);
+
+	clk_enable(keypad->clk);
+
+	/* enable interrupt and wakeup bit */
+	val = SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN |
+		SAMSUNG_KEYIFCON_WAKEUPEN;
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	/* KEYIFCOL reg clear */
+	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+
+	clk_disable(keypad->clk);
+
+	enable_irq(keypad->irq);
+
+	return 0;
+}
+
+static const struct dev_pm_ops samsung_keypad_pm_ops = {
+	.suspend	= samsung_keypad_suspend,
+	.resume		= samsung_keypad_resume,
+};
+#endif
+
+static struct platform_device_id samsung_keypad_driver_ids[] = {
+	{
+		.name		= "samsung-keypad",
+		.driver_data	= KEYPAD_TYPE_SAMSUNG,
+	}, {
+		.name		= "s5pv210-keypad",
+		.driver_data	= KEYPAD_TYPE_S5PV210,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(platform, samsung_keypad_driver_ids);
+
+static struct platform_driver samsung_keypad_driver = {
+	.probe		= samsung_keypad_probe,
+	.remove		= __devexit_p(samsung_keypad_remove),
+	.driver		= {
+		.name	= "samsung-keypad",
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &samsung_keypad_pm_ops,
+#endif
+	},
+	.id_table	= samsung_keypad_driver_ids,
+};
+
+static int __init samsung_keypad_init(void)
+{
+	return platform_driver_register(&samsung_keypad_driver);
+}
+
+static void __exit samsung_keypad_exit(void)
+{
+	platform_driver_unregister(&samsung_keypad_driver);
+}
+
+module_init(samsung_keypad_init);
+module_exit(samsung_keypad_exit);
+
+MODULE_DESCRIPTION("Samsung keypad driver");
+MODULE_AUTHOR("Joonyoung Shim <jy0922.shim at samsung.com>");
+MODULE_AUTHOR("Donghwa Lee <dh09.lee at samsung.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:samsung-keypad");
-- 
1.7.0.4



From kmpark at infradead.org  Fri Jun 11 04:15:01 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 11 Jun 2010 17:15:01 +0900
Subject: Pending patches for s5pc110
In-Reply-To: <20100611075457.GZ7248@trinity.fluff.org>
References: <AANLkTil0wWSFHpwi58enMhhG7475uUmFoZG6QhRim6Xk@mail.gmail.com>
	<AANLkTimjwSHLiMYFywn3vHZYCbqQCCCh9qE-n3xuYOaq@mail.gmail.com>
	<20100611051521.GV7248@trinity.fluff.org>
	<AANLkTikJQnDEjVunmiCLGaVAnj5bR7JdsUZYJ9xAEdE5@mail.gmail.com>
	<20100611062300.GY7248@trinity.fluff.org>
	<AANLkTimnuN9h-qka3pRlmaEsR8o6IzFgl3A2YQ5Y28HJ@mail.gmail.com>
	<20100611075457.GZ7248@trinity.fluff.org>
Message-ID: <AANLkTinQamPv2vXHNp1Ym432zhyFf0bZnkuP9SAYzTc_@mail.gmail.com>

On Fri, Jun 11, 2010 at 4:54 PM, Ben Dooks <ben-linux at fluff.org> wrote:
> On Fri, Jun 11, 2010 at 04:07:58PM +0900, Kyungmin Park wrote:
>> On Fri, Jun 11, 2010 at 3:23 PM, Ben Dooks <ben-linux at fluff.org> wrote:
>> > On Fri, Jun 11, 2010 at 02:38:56PM +0900, Kyungmin Park wrote:
>> >> On Fri, Jun 11, 2010 at 2:15 PM, Ben Dooks <ben-linux at fluff.org> wrote:
>> >> > On Fri, Jun 11, 2010 at 01:25:18PM +0900, Kyungmin Park wrote:
>> >> >> Hi,
>> >> >>
>> >> >> No comments mean it's okay then we will prepare the patches to git pull.
>> >> >
>> >> > No. no comments means that people either haven't had time to sort
>> >> > them out or in fact ON HOLIDAY.
>> >>
>> >> but you usually missed our patches frequently. with this reason our
>> >> patches can't merge within proper merge window.
>> >
>> > I belive the last set where either being posted just-before or during
>> > the last merge window. We already had far too much queueud up then and
>> > we where trying to ensure that the already-queued entries where processed.
>>
>> Not tell this case, please see the s5pc110 patches last year. last
>> year we sent the s5pc110 related patches several times. but you don't
>> give any opinions and can't accept without any reason.
>
> I gave you comments, or at least Marke should have got them for the
> series sent in November, then there's nothing in my mailbox since
> then.
>
>> Well it's past story, ?forget it.
>>
>> Last question.
>>
>> I think you share the s3c maintainer-ship with Kukjin. Can you explain
>> the criteria?
>
> Ok, here's the list:
>
> 1) SystemLSI are the best placed to see all the chips in development,
> ? since they're the ones making them. You are only dealing with a
> ? subset of their output (generally the S5PC100 and S5PC110) whereas
> ? there are many more devices in the line.
>
> 2) SystemLSI have spent time talking to me about what they need to do
> ? when maintaining a system and trying to acquire the necessary skills
> ? for managing a port.

That's enough.

>
> This does not mean that you cannot be included at a later date.
>
> As a note, that I have left myself in the maintainers entries for the
> samsung series and will re-visit this once we see how well the transfer
> goes in the next kernel release or two.

I see.

Just opinion I hope you're more focus on difficult issues such as
reserved memory handling at used
continuous memory management at multimedia IPs and clock & power
gating to reduce the power at Samsung SoCs.

Have good holiday.

Thank you,
Kyungmin Park


From LW at KARO-electronics.de  Fri Jun 11 04:14:35 2010
From: LW at KARO-electronics.de (=?iso-8859-15?Q?Lothar_Wa=DFmann?=)
Date: Fri, 11 Jun 2010 10:14:35 +0200
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <201006111557.12249.jeremy.kerr@canonical.com>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<1275636608.607067.417709988883.1.gpush@pororo>
	<20100611042046.GA31045@fluff.org.uk>
	<201006111557.12249.jeremy.kerr@canonical.com>
Message-ID: <19473.61547.684572.647641@ipc1.ka-ro>

Hi,

> > > +static inline int clk_enable(struct clk *clk)
> > > +{
> > > +	int ret = 0;
> > > +
> > > +	if (!clk->ops->enable)
> > > +		return 0;
> > > +
> > > +	mutex_lock(&clk->mutex);
> > > +	if (!clk->enable_count)
> > > +		ret = clk->ops->enable(clk);
> > > +
> > > +	if (!ret)
> > > +		clk->enable_count++;
> > > +	mutex_unlock(&clk->mutex);
> > > +
> > > +	return ret;
> > > +}
> > 
Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
makes it impossible to call those functions in interrupt context.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From kmpark at infradead.org  Fri Jun 11 04:18:42 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 11 Jun 2010 17:18:42 +0900
Subject: [PATCH] sdhci-s3c: Add SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK quirk 
	for Samsung SoC
In-Reply-To: <003901cb093d$3dd14110$b973c330$%kim@samsung.com>
References: <1276169991-16396-1-git-send-email-kgene.kim@samsung.com>
	<AANLkTim2LzIh7dadCAWCo6jltS4CYA8gLKaiQne_VzqK@mail.gmail.com>
	<003901cb093d$3dd14110$b973c330$%kim@samsung.com>
Message-ID: <AANLkTilyfUvwRUP1M1HD5r_cx3PWxDG9SbmqZd6M1MT1@mail.gmail.com>

On Fri, Jun 11, 2010 at 5:08 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Kyungmin Park wrote:
>>
>> Hi,
>>
>> On Thu, Jun 10, 2010 at 8:39 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>> > From: Lee Hyuk <hyuk1.lee at samsung.com>
>> >
>> > On Samsung's SDMMC hosts the timeout clock is derivied from the SD
>> > Clock, which is set dynamically.
>> > So, checked 'SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK' quirk and removed
>> > 'sdhci_s3c_get_timeout_clk' callback which doesn't need any more.
>> >
>> > Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
>> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
>> > ---
>> > ?drivers/mmc/host/sdhci-s3c.c | ? 10 +++-------
>> > ?1 files changed, 3 insertions(+), 7 deletions(-)
>> >
>> > diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
>> > index af21792..ca09382 100644
>> > --- a/drivers/mmc/host/sdhci-s3c.c
>> > +++ b/drivers/mmc/host/sdhci-s3c.c
>> > @@ -110,11 +110,6 @@ static unsigned int sdhci_s3c_get_max_clk(struct
>> sdhci_host *host)
>> > ? ? ? ?return max;
>> > ?}
>> >
>> > -static unsigned int sdhci_s3c_get_timeout_clk(struct sdhci_host *host)
>> > -{
>> > - ? ? ? return sdhci_s3c_get_max_clk(host) / 1000000;
>> > -}
>> > -
>> > ?/**
>> > ?* sdhci_s3c_consider_clock - consider one the bus clocks for current
> setting
>> > ?* @ourhost: Our SDHCI instance.
>> > @@ -188,7 +183,6 @@ static void sdhci_s3c_set_clock(struct sdhci_host
> *host,
>> unsigned int clock)
>> >
>> > ? ? ? ? ? ? ? ?ourhost->cur_clk = best_src;
>> > ? ? ? ? ? ? ? ?host->max_clk = clk_get_rate(clk);
>> > - ? ? ? ? ? ? ? host->timeout_clk = sdhci_s3c_get_timeout_clk(host);
>> >
>> > ? ? ? ? ? ? ? ?ctrl = readl(host->ioaddr + S3C_SDHCI_CONTROL2);
>> > ? ? ? ? ? ? ? ?ctrl &= ~S3C_SDHCI_CTRL2_SELBASECLK_MASK;
>> > @@ -211,7 +205,6 @@ static void sdhci_s3c_set_clock(struct sdhci_host
> *host,
>> unsigned int clock)
>> >
>> > ?static struct sdhci_ops sdhci_s3c_ops = {
>> > ? ? ? ?.get_max_clock ? ? ? ? ?= sdhci_s3c_get_max_clk,
>> > - ? ? ? .get_timeout_clock ? ? ?= sdhci_s3c_get_timeout_clk,
>> > ? ? ? ?.set_clock ? ? ? ? ? ? ?= sdhci_s3c_set_clock,
>> > ?};
>> >
>> > @@ -335,6 +328,9 @@ static int __devinit sdhci_s3c_probe(struct
>> platform_device *pdev)
>> > ? ? ? ?host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
>> > ? ? ? ? ? ? ? ? ? ? ? ? SDHCI_QUIRK_32BIT_DMA_SIZE);
>> >
>> > + ? ? ? /* HSMMC on Samsung SoCs uses SDCLK as timeout clock. */
>> > + ? ? ? host->quirks |= SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK;
>>
>> How do you know Samsung SoCs use SDCLK in the spec?
>>
> Samsung SoC hardware engineer guided about that.

Of course H/W team know it. they made it. I mean how can we know it at Spec?

If MMC developer don't know the samsung socs well, then how to set it
quirk from Spec.

Thank you,
Kyungmin Park

>
>> Is it also true at s3c64xx series?
>>
> Yes, of course.
>
>
>
>>
>> > +
>> > ? ? ? ?ret = sdhci_add_host(host);
>> > ? ? ? ?if (ret) {
>> > ? ? ? ? ? ? ? ?dev_err(dev, "sdhci_add_host() failed\n");
>> > --
>> > 1.6.2.5
>> >
>> > --
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>


From ben-linux at fluff.org  Fri Jun 11 04:20:49 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 09:20:49 +0100
Subject: [PATCH 03/11] USB: s3c-hsotg: The NPTX/PTX FIFO sizes are in words,
	not bytes
In-Reply-To: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
Message-ID: <1276244457-4072-4-git-send-email-ben-linux@fluff.org>

Fix a problem where we have been underestimating the space available in
the IN PTX/NPTX FIFOs by assuming that they where simply word aligned
instead of in number-of-words. This means all length calculations need
to be multiplied-by-4.

Note, we do not change the information about fifo size or start addresses
available to userspace as we assume the user can multiply by four easily
and is already knows these values are in words.

Signed-off-by: Ben Dooks <ben-linux at fluff.org>
---
 drivers/usb/gadget/s3c-hsotg.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index ba00e6e..a018b6a 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -506,6 +506,7 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
 		}
 
 		can_write = S3C_GNPTXSTS_NPTxFSpcAvail_GET(gnptxsts);
+		can_write *= 4;	/* fifo size is in 32bit quantities. */
 	}
 
 	dev_dbg(hsotg->dev, "%s: GNPTXSTS=%08x, can=%d, to=%d, mps %d\n",
@@ -2733,7 +2734,7 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
 	 */
 
 	ptxfifo = readl(hsotg->regs + S3C_DPTXFSIZn(epnum));
-	hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo);
+	hs_ep->fifo_size = S3C_DPTXFSIZn_DPTxFSize_GET(ptxfifo) * 4;
 
 	/* if we're using dma, we need to set the next-endpoint pointer
 	 * to be something valid.
-- 
1.7.0.4



From ben-linux at fluff.org  Fri Jun 11 04:20:53 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 09:20:53 +0100
Subject: [PATCH 07/11] USB: s3c-hsotg: Only load packet per fifo write
In-Reply-To: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
Message-ID: <1276244457-4072-8-git-send-email-ben-linux@fluff.org>

Limit the IN FIFO write to a single packet per attempt at writing,
as per the specifications and ensure that we don't return fifo-full
so that we can continue writing packets if we have the space.

Signed-off-by: Ben Dooks <ben-linux at fluff.org>
---
 drivers/usb/gadget/s3c-hsotg.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 819e75a..7c35bfe 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -539,6 +539,17 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
 	if (can_write > 512)
 		can_write = 512;
 
+	/* limit the write to one max-packet size worth of data, but allow
+	 * the transfer to return that it did not run out of fifo space
+	 * doing it. */
+	if (to_write > hs_ep->ep.maxpacket) {
+		to_write = hs_ep->ep.maxpacket;
+
+		s3c_hsotg_en_gsint(hsotg,
+				   periodic ? S3C_GINTSTS_PTxFEmp :
+				   S3C_GINTSTS_NPTxFEmp);
+	}
+
 	/* see if we can write data */
 
 	if (to_write > can_write) {
-- 
1.7.0.4



From ben-linux at fluff.org  Fri Jun 11 04:20:55 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 09:20:55 +0100
Subject: [PATCH 09/11] USB: s3c-hsotg: Fix max EP0 IN request length
In-Reply-To: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
Message-ID: <1276244457-4072-10-git-send-email-ben-linux@fluff.org>

The maximum length for any EP0 IN request on EP0 is 127 bytes, not 128
as the driver currently has it.

Signed-off-by: Ben Dooks <ben-linux at fluff.org>
---
 drivers/usb/gadget/s3c-hsotg.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 2555f27..17b0779 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -613,8 +613,7 @@ static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
 		maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
 	} else {
 		if (hs_ep->dir_in) {
-			/* maxsize = S3C_DIEPTSIZ0_XferSize_LIMIT + 1; */
-			maxsize = 64+64+1;
+			maxsize = 64+64;
 			maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
 		} else {
 			maxsize = 0x3f;
-- 
1.7.0.4



From ben-linux at fluff.org  Fri Jun 11 04:20:56 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 09:20:56 +0100
Subject: [PATCH 10/11] USB: s3c-hsotg: Fix the OUT EP0 limit
In-Reply-To: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
Message-ID: <1276244457-4072-11-git-send-email-ben-linux@fluff.org>

The EP0 out limit is the same as the IN limit, so make them the same.

Signed-off-by: Ben Dooks <ben-linux at fluff.org>

tmp-fix
---
 drivers/usb/gadget/s3c-hsotg.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 17b0779..b34a05d 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -612,11 +612,10 @@ static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
 		maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
 		maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
 	} else {
+		maxsize = 64+64;
 		if (hs_ep->dir_in) {
-			maxsize = 64+64;
 			maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
 		} else {
-			maxsize = 0x3f;
 			maxpkt = 2;
 		}
 	}
-- 
1.7.0.4



From ben-linux at fluff.org  Fri Jun 11 04:20:48 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 09:20:48 +0100
Subject: [PATCH 02/11] USB: s3c-hsotg: Increase TX fifo limit
In-Reply-To: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
Message-ID: <1276244457-4072-3-git-send-email-ben-linux@fluff.org>

Up the FIFO size for the TX to 1024 entries, as this now seems to work
with all the cores. This fixes a problem when using large packets on
a core with MPS set to 512 can hang due to insufficient space for the
writes.

The hang arises due to getting the non-periodic FIFO empty IRQ but
not being able to satisfy any requests since there is never enough
space to write 512 bytes into the buffer. This means we end up with
a stream of interrupt requests.

It is easier to up the TX FIFO to fill the space we left for it
than to try and fix the positions in the code where we should have
limited the max-packet size to < TXFIFOSIZE, since the TXFIFOSIZE
depends on how the TX FIFOs have been setup.

Signed-off-by: Ben Dooks <ben-linux at fluff.org>
---
 drivers/usb/gadget/s3c-hsotg.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 6a303ce..ba00e6e 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -311,11 +311,11 @@ static void s3c_hsotg_init_fifo(struct s3c_hsotg *hsotg)
 		hsotg->regs + S3C_GNPTXFSIZ);
 	*/
 
-	/* set FIFO sizes to 2048/0x1C0 */
+	/* set FIFO sizes to 2048/1024 */
 
 	writel(2048, hsotg->regs + S3C_GRXFSIZ);
 	writel(S3C_GNPTXFSIZ_NPTxFStAddr(2048) |
-	       S3C_GNPTXFSIZ_NPTxFDep(0x1C0),
+	       S3C_GNPTXFSIZ_NPTxFDep(1024),
 	       hsotg->regs + S3C_GNPTXFSIZ);
 
 	/* arange all the rest of the TX FIFOs, as some versions of this
-- 
1.7.0.4



From ben-linux at fluff.org  Fri Jun 11 04:20:54 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 09:20:54 +0100
Subject: [PATCH 08/11] USB: s3c-hsotg: Check for new request before enqueing
	new setup
In-Reply-To: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
Message-ID: <1276244457-4072-9-git-send-email-ben-linux@fluff.org>

Before trying a new setup transaction after getting an EP0 in complete
interrupt, check that the driver did not try and send more EP0 IN data
before enqueing a new setup transaction.

This fixes a bug where we cannot send all of the IN data in one go
so split the transfer, but then fail to send all the data as we start
waiting for a new OUT transaction

Signed-off-by: Ben Dooks <ben-linux at fluff.org>
---
 drivers/usb/gadget/s3c-hsotg.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 7c35bfe..2555f27 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -1791,7 +1791,7 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
 		if (dir_in) {
 			s3c_hsotg_complete_in(hsotg, hs_ep);
 
-			if (idx == 0)
+			if (idx == 0 && !hs_ep->req)
 				s3c_hsotg_enqueue_setup(hsotg);
 		} else if (using_dma(hsotg)) {
 			/* We're using DMA, we need to fire an OutDone here
-- 
1.7.0.4



From ben-linux at fluff.org  Fri Jun 11 04:20:46 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 09:20:46 +0100
Subject: s3c-hsotg fixes
Message-ID: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>


Some further fixes for the s3c-hsotg block, as well as a repost of
the missed USB phy clock setting patch which either got missed or
passed over from last time.

As a note, this series has a patch adding support for dedicated FIFO
mode, this is in my view a fix, as when the hsotg block is compiled
with dedicated fifos then each USB IN non-periodic pipe needs to be
alloacted a unique TX FIFO. We have no actual data on how well the
block performs when all IN TX NP FIFOs are all set to the same one,
but it really should be fixed.

I am not sure if I have been subscribed to linux-usb, please CC: me
just in case.

-- 
Ben


From ben-linux at fluff.org  Fri Jun 11 04:20:51 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 09:20:51 +0100
Subject: [PATCH 05/11] USB: s3c-hsotg: Re-initialise all FIFOs on USB bus reset
In-Reply-To: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
Message-ID: <1276244457-4072-6-git-send-email-ben-linux@fluff.org>

The USB documentation suggest that the FIFOs should be reset when a
bus reset event happens. Use the s3c_hsotg_init_fifo() to ensure that
the FIFO layout is correct and that the FIFOs are flushed before
acknowledging the reset.

Signed-off-by: Ben Dooks <ben-linux at fluff.org>
---
 drivers/usb/gadget/s3c-hsotg.c |   13 ++++---------
 1 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index df3e8d1..5b61bcf 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -2083,17 +2083,12 @@ irq_retry:
 		kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
 
 		/* it seems after a reset we can end up with a situation
-		 * where the TXFIFO still has data in it... try flushing
-		 * it to remove anything that may still be in it.
+		 * where the TXFIFO still has data in it... the docs
+		 * suggest resetting all the fifos, so use the init_fifo
+		 * code to relayout and flush the fifos.
 		 */
 
-		if (1) {
-			writel(S3C_GRSTCTL_TxFNum(0) | S3C_GRSTCTL_TxFFlsh,
-			       hsotg->regs + S3C_GRSTCTL);
-
-			dev_info(hsotg->dev, "GNPTXSTS=%08x\n",
-				 readl(hsotg->regs + S3C_GNPTXSTS));
-		}
+		s3c_hsotg_init_fifo(hsotg);
 
 		s3c_hsotg_enqueue_setup(hsotg);
 
-- 
1.7.0.4



From ben-linux at fluff.org  Fri Jun 11 04:20:57 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 09:20:57 +0100
Subject: [PATCH 11/11] USB: s3c-hsotg: Fix OUT packet request retry
In-Reply-To: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
Message-ID: <1276244457-4072-12-git-send-email-ben-linux@fluff.org>

If there is more data in the request than we could fit into a single
hardware request, then check when the OutDone event is received if
we have more data, and if so, schedule the new data instead of trying
to complete the request (and in the case of EP0, sending a 0 packet
in the middle of a transfer).

Also, move the debug message about the current transfer state before
the warning about a bad transfer.

Signed-off-by: Ben Dooks <ben-linux at fluff.org>
---
 drivers/usb/gadget/s3c-hsotg.c |   18 +++++++++++-------
 1 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index b34a05d..3da45f5 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -1384,6 +1384,9 @@ static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
 	read_ptr = hs_req->req.actual;
 	max_req = hs_req->req.length - read_ptr;
 
+	dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
+		__func__, to_read, max_req, read_ptr, hs_req->req.length);
+
 	if (to_read > max_req) {
 		/* more data appeared than we where willing
 		 * to deal with in this request.
@@ -1393,9 +1396,6 @@ static void s3c_hsotg_rx_data(struct s3c_hsotg *hsotg, int ep_idx, int size)
 		WARN_ON_ONCE(1);
 	}
 
-	dev_dbg(hsotg->dev, "%s: read %d/%d, done %d/%d\n",
-		__func__, to_read, max_req, read_ptr, hs_req->req.length);
-
 	hs_ep->total_data += to_read;
 	hs_req->req.actual += to_read;
 	to_read = DIV_ROUND_UP(to_read, 4);
@@ -1464,9 +1464,11 @@ static void s3c_hsotg_send_zlp(struct s3c_hsotg *hsotg,
 static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
 				     int epnum, bool was_setup)
 {
+	u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
 	struct s3c_hsotg_ep *hs_ep = &hsotg->eps[epnum];
 	struct s3c_hsotg_req *hs_req = hs_ep->req;
 	struct usb_request *req = &hs_req->req;
+	unsigned size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
 	int result = 0;
 
 	if (!hs_req) {
@@ -1475,9 +1477,7 @@ static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
 	}
 
 	if (using_dma(hsotg)) {
-		u32 epsize = readl(hsotg->regs + S3C_DOEPTSIZ(epnum));
 		unsigned size_done;
-		unsigned size_left;
 
 		/* Calculate the size of the transfer by checking how much
 		 * is left in the endpoint size register and then working it
@@ -1487,14 +1487,18 @@ static void s3c_hsotg_handle_outdone(struct s3c_hsotg *hsotg,
 		 * so may overshoot/undershoot the transfer.
 		 */
 
-		size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
-
 		size_done = hs_ep->size_loaded - size_left;
 		size_done += hs_ep->last_load;
 
 		req->actual = size_done;
 	}
 
+	/* if there is more request to do, schedule new transfer */
+	if (req->actual < req->length && size_left == 0) {
+		s3c_hsotg_start_req(hsotg, hs_ep, hs_req, true);
+		return;
+	}
+
 	if (req->actual < req->length && req->short_not_ok) {
 		dev_dbg(hsotg->dev, "%s: got %d/%d (short not ok) => error\n",
 			__func__, req->actual, req->length);
-- 
1.7.0.4



From ben-linux at fluff.org  Fri Jun 11 04:20:52 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 09:20:52 +0100
Subject: [PATCH 06/11] USB: s3c-hsotg: Add initial detection and setup for
	dedicated FIFO mode
In-Reply-To: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
Message-ID: <1276244457-4072-7-git-send-email-ben-linux@fluff.org>

Add support for the dedicated FIFO mode on newer SoCs such as the S5PV210
partly to improve support and to fix the bug where any non-EP0 IN endpoint
requires its own FIFO allocation.

To fix this, we ensure that any non-zero IN endpoint is given a TXFIFO
using the same allocation method as the periodic case (all our current
hardware has enough FIFOs and FIFO memory for a 1:1 mapping) and ensure
that the necessary transmission done interrupt is enabled.

The default settings from reset for the core point all EPs at FIFO0,
used for the control endpoint. However, the controller documentation
states that all IN endpoints _must_ have a unique FIFO to avoid any
contention during transmission.

Note, this leaves us with a large IN FIFO for EP0 (which re-uses the
old NPTXFIFO) for an endpoint which cannot shift more than a pair of
packets at a time... this is a waste, but it looks like we cannot
re-allocate space to the individual IN FIFOs as they are already
maxed out (to be confirmed).

Signed-off-by: Ben Dooks <ben-linux at fluff.org?
---
 .../arm/plat-samsung/include/plat/regs-usb-hsotg.h |    2 +
 drivers/usb/gadget/s3c-hsotg.c                     |   40 +++++++++++++++++++-
 2 files changed, 40 insertions(+), 2 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
index 8d18d9d..dc90f5e 100644
--- a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
+++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
@@ -226,6 +226,7 @@
 
 #define S3C_DIEPMSK				S3C_HSOTG_REG(0x810)
 
+#define S3C_DIEPMSK_TxFIFOEmpty			(1 << 7)
 #define S3C_DIEPMSK_INEPNakEffMsk		(1 << 6)
 #define S3C_DIEPMSK_INTknEPMisMsk		(1 << 5)
 #define S3C_DIEPMSK_INTknTXFEmpMsk		(1 << 4)
@@ -371,6 +372,7 @@
 
 #define S3C_DIEPDMA(_a)				S3C_HSOTG_REG(0x914 + ((_a) * 0x20))
 #define S3C_DOEPDMA(_a)				S3C_HSOTG_REG(0xB14 + ((_a) * 0x20))
+#define S3C_DTXFSTS(_a)				S3C_HSOTG_REG(0x918 + ((_a) * 0x20))
 
 #define S3C_EPFIFO(_a)				S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000))
 
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 5b61bcf..819e75a 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -12,6 +12,8 @@
  * published by the Free Software Foundation.
 */
 
+#define DEBUG
+
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/spinlock.h>
@@ -131,6 +133,7 @@ struct s3c_hsotg_ep {
  * @regs: The memory area mapped for accessing registers.
  * @regs_res: The resource that was allocated when claiming register space.
  * @irq: The IRQ number we are using
+ * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
  * @debug_root: root directrory for debugfs.
  * @debug_file: main status file for debugfs.
  * @debug_fifo: FIFO status file for debugfs.
@@ -149,6 +152,8 @@ struct s3c_hsotg {
 	struct resource		*regs_res;
 	int			irq;
 
+	unsigned int		dedicated_fifos:1;
+
 	struct dentry		*debug_root;
 	struct dentry		*debug_file;
 	struct dentry		*debug_fifo;
@@ -467,7 +472,7 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
 	if (to_write == 0)
 		return 0;
 
-	if (periodic) {
+	if (periodic && !hsotg->dedicated_fifos) {
 		u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
 		int size_left;
 		int size_done;
@@ -505,6 +510,11 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
 			s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
 			return -ENOSPC;
 		}
+	} else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
+		can_write = readl(hsotg->regs + S3C_DTXFSTS(hs_ep->index));
+
+		can_write &= 0xffff;
+		can_write *= 4;
 	} else {
 		if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
 			dev_dbg(hsotg->dev,
@@ -1830,6 +1840,15 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
 				 __func__, idx);
 			clear |= S3C_DIEPMSK_INTknEPMisMsk;
 		}
+
+		/* FIFO has space or is empty (see GAHBCFG) */
+		if (hsotg->dedicated_fifos &&
+		    ints & S3C_DIEPMSK_TxFIFOEmpty) {
+			dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
+				__func__, idx);
+			s3c_hsotg_trytx(hsotg, hs_ep);
+			clear |= S3C_DIEPMSK_TxFIFOEmpty;
+		}
 	}
 
 	writel(clear, hsotg->regs + epint_reg);
@@ -2281,6 +2300,12 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
 		break;
 	}
 
+	/* if the hardware has dedicated fifos, we must give each IN EP
+	 * a unique tx-fifo even if it is non-periodic.
+	 */
+	if (dir_in && hsotg->dedicated_fifos)
+		epctrl |= S3C_DxEPCTL_TxFNum(index);
+
 	/* for non control endpoints, set PID to D0 */
 	if (index)
 		epctrl |= S3C_DxEPCTL_SetD0PID;
@@ -2570,7 +2595,8 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
 
 	writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
 	       S3C_DIEPMSK_INTknEPMisMsk |
-	       S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
+	       S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk |
+	       ((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0),
 	       hsotg->regs + S3C_DIEPMSK);
 
 	/* don't need XferCompl, we get that from RXFIFO in slave mode. In
@@ -2797,6 +2823,8 @@ static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
 
 static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
 {
+	u32 cfg4;
+
 	/* unmask subset of endpoint interrupts */
 
 	writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
@@ -2832,6 +2860,14 @@ static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
 
 	writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
 	       hsotg->regs + S3C_GAHBCFG);
+
+	/* check hardware configuration */
+
+	cfg4 = readl(hsotg->regs + 0x50);
+	hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
+
+	dev_info(hsotg->dev, "%s fifos\n",
+		 hsotg->dedicated_fifos ? "dedicated" : "shared");
 }
 
 static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)
-- 
1.7.0.4



From ben-linux at fluff.org  Fri Jun 11 04:20:47 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 09:20:47 +0100
Subject: [PATCH 01/11] USB: s3c_hsotg: Add support for external USB clock
In-Reply-To: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
Message-ID: <1276244457-4072-2-git-send-email-ben-linux@fluff.org>

From: Maurus Cuelenaere <mcuelenaere at gmail.com>

The PLL that drives the USB clock supports 3 input clocks: 12, 24 and 48Mhz.
This patch adds support to the USB driver for setting the correct register bit
according to the given clock.

This depends on the following patch:
[PATCH] ARM: S3C64XX: Add USB external clock definition

Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
Signed-off-by: Ben Dooks <ben-linux at fluff.org>
---
 drivers/usb/gadget/s3c-hsotg.c |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 26193ec..6a303ce 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -23,6 +23,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/clk.h>
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
@@ -2753,6 +2754,7 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
  */
 static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
 {
+	struct clk *xusbxti;
 	u32 osc;
 
 	writel(0, S3C_PHYPWR);
@@ -2760,6 +2762,23 @@ static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
 
 	osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
 
+	xusbxti = clk_get(hsotg->dev, "xusbxti");
+	if (xusbxti && !IS_ERR(xusbxti)) {
+		switch (clk_get_rate(xusbxti)) {
+		case 12000000:
+		    osc |= S3C_PHYCLK_CLKSEL_12M;
+		    break;
+		case 24000000:
+		    osc |= S3C_PHYCLK_CLKSEL_24M;
+		    break;
+		default:
+		case 48000000:
+		    /* default reference clock */
+		    break;
+		}
+		clk_put(xusbxti);
+	}
+
 	writel(osc | 0x10, S3C_PHYCLK);
 
 	/* issue a full set of resets to the otg and core */
-- 
1.7.0.4



From ben-linux at fluff.org  Fri Jun 11 04:20:50 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 11 Jun 2010 09:20:50 +0100
Subject: [PATCH 04/11] USB: s3c-hsotg: Avoid overwriting contents of perodic
	in 'fifo'
In-Reply-To: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
Message-ID: <1276244457-4072-5-git-send-email-ben-linux@fluff.org>

In shared fifo mode (used on older SoCs) the periodic in fifo beahves
much more like a packet buffer, discarding old data when writing new
data. Avoid this by ensuring that we do not load new transactions in
when there is data sitting already in the FIFO.

Note, this may not be an observed bug, we are fixing the case that this
may happen.

Signed-off-by: Ben Dooks <ben-linux at fluff.org>
---
 drivers/usb/gadget/s3c-hsotg.c |   12 +++++++++++-
 1 files changed, 11 insertions(+), 1 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index a018b6a..df3e8d1 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -92,7 +92,9 @@ struct s3c_hsotg_req;
  * For periodic IN endpoints, we have fifo_size and fifo_load to try
  * and keep track of the amount of data in the periodic FIFO for each
  * of these as we don't have a status register that tells us how much
- * is in each of them.
+ * is in each of them. (note, this may actually be useless information
+ * as in shared-fifo mode periodic in acts like a single-frame packet
+ * buffer than a fifo)
  */
 struct s3c_hsotg_ep {
 	struct usb_ep		ep;
@@ -475,6 +477,14 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
 
 		size_left = S3C_DxEPTSIZ_XferSize_GET(epsize);
 
+		/* if shared fifo, we cannot write anything until the
+		 * previous data has been completely sent.
+		 */
+		if (hs_ep->fifo_load != 0) {
+			s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
+			return -ENOSPC;
+		}
+
 		dev_dbg(hsotg->dev, "%s: left=%d, load=%d, fifo=%d, size %d\n",
 			__func__, size_left,
 			hs_ep->size_loaded, hs_ep->fifo_load, hs_ep->fifo_size);
-- 
1.7.0.4



From jy0922.shim at samsung.com  Fri Jun 11 04:33:14 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 11 Jun 2010 17:33:14 +0900
Subject: [PATCH v2 0/4] ARM: S5P: Support gpio interrupts
Message-ID: <4C11F4CA.10802@samsung.com>

This patch v2 set is to support gpio interrupts of samsung s5p cpus, and
the GPIOlib gpio_to_irq goes to plat-samsung gpiolib, so patch v2 set 
has four commit smaller than v1.

Changes since v1:
- Add irq_base to s3c_gpio_chip struct 
- GPIOlib gpio_to_irq() is implemented to samsung_gpiolib_to_irq() of
  plat-samsung gpiolib

Joonyoung Shim (4):
      ARM: S5PV210: Add gpio interrupt support
      ARM: S5PC100: Use S5P gpio interrupts interface
      ARM: S5PC100: Move external interrupt defines
      ARM: SAMSUNG: Add GPIOlib gpio_to_irq

 arch/arm/mach-s5pc100/Makefile                 |    2 +-
 arch/arm/mach-s5pc100/gpiolib.c                |   70 ++-----
 arch/arm/mach-s5pc100/include/mach/gpio.h      |    7 -
 arch/arm/mach-s5pc100/include/mach/irqs.h      |   18 ++-
 arch/arm/mach-s5pc100/include/mach/regs-gpio.h |    7 +
 arch/arm/mach-s5pc100/irq-gpio.c               |  266 ------------------------
 arch/arm/mach-s5pv210/gpiolib.c                |   18 ++-
 arch/arm/mach-s5pv210/include/mach/irqs.h      |   16 ++-
 arch/arm/plat-s5p/Makefile                     |    2 +-
 arch/arm/plat-s5p/irq-gpioint.c                |  208 ++++++++++++++++++
 arch/arm/plat-samsung/gpiolib.c                |    9 +
 arch/arm/plat-samsung/include/plat/gpio-core.h |    6 +
 12 files changed, 295 insertions(+), 334 deletions(-)
 delete mode 100644 arch/arm/mach-s5pc100/irq-gpio.c
 create mode 100644 arch/arm/plat-s5p/irq-gpioint.c


From jy0922.shim at samsung.com  Fri Jun 11 04:33:17 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 11 Jun 2010 17:33:17 +0900
Subject: [PATCH v2 1/4] ARM: S5PV210: Add gpio interrupt support
Message-ID: <1276245200-18052-1-git-send-email-jy0922.shim@samsung.com>

This patch is to support gpio interrupts on s5pv210.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pv210/gpiolib.c                |    8 +-
 arch/arm/mach-s5pv210/include/mach/irqs.h      |   16 ++-
 arch/arm/plat-s5p/Makefile                     |    2 +-
 arch/arm/plat-s5p/irq-gpioint.c                |  208 ++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/gpio-core.h |    2 +
 5 files changed, 233 insertions(+), 3 deletions(-)
 create mode 100644 arch/arm/plat-s5p/irq-gpioint.c

diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
index 9ea8972..16d6747 100644
--- a/arch/arm/mach-s5pv210/gpiolib.c
+++ b/arch/arm/mach-s5pv210/gpiolib.c
@@ -150,6 +150,7 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 			.label	= "GPG3",
 		},
 	}, {
+		.config	= &gpio_cfg_noint,
 		.chip	= {
 			.base	= S5PV210_GPI(0),
 			.ngpio	= S5PV210_GPIO_I_NR,
@@ -245,11 +246,16 @@ static __init int s5pv210_gpiolib_init(void)
 {
 	struct s3c_gpio_chip *chip = s5pv210_gpio_4bit;
 	int nr_chips = ARRAY_SIZE(s5pv210_gpio_4bit);
+	int gpioint_group = 0;
 	int i = 0;
 
 	for (i = 0; i < nr_chips; i++, chip++) {
-		if (chip->config == NULL)
+		if (chip->config == NULL) {
 			chip->config = &gpio_cfg;
+
+			/* gpio interrupts */
+			s5p_gpioint_add(chip, gpioint_group++);
+		}
 		if (chip->base == NULL)
 			chip->base = S5PV210_BANK_BASE(i);
 	}
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 9689537..43baacc 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -121,8 +121,22 @@
 #define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2		(IRQ_VIC_END + 1)
 
+/* GPIO interrupt */
+#define S5P_GPIOINT_GROUP_NR	22
+#define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
+#define S5P_IRQ_GPIOINT(x)	(S5P_GPIOINT_BASE + (x))
+
 /* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + 1)
+
+/*
+ * GPIO groups is 27. Each GPIO group can have max 8 GPIO interrupts.
+ *
+ * We should include gpios of all gpio groups from GPIO_A0 until GPIO_J4 to
+ * NR_IRQS because 22 gpio groups having gpio interrupts aren't in order and
+ * are mixed with no interrupt gpio groups, then it can give simple irq
+ * computation of gpio interrupts.
+ */
+#define NR_IRQS			(S5P_IRQ_GPIOINT(27 * 8) + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 39c242b..b56b4d3 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -15,6 +15,6 @@ obj-				:=
 obj-y				+= dev-uart.o
 obj-y				+= cpu.o
 obj-y				+= clock.o
-obj-y				+= irq.o
+obj-y				+= irq.o irq-gpioint.o
 obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
 
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
new file mode 100644
index 0000000..c172e37
--- /dev/null
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -0,0 +1,208 @@
+/*
+ * linux/arch/arm/plat-s5p/irq-gpioint.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Kyungmin Park <kyungmin.park at samsung.com>
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/map.h>
+#include <plat/gpio-core.h>
+#include <plat/gpio-cfg.h>
+
+#define S5P_GPIOREG(x)			(S5P_VA_GPIO + (x))
+
+#define GPIOINT_CON_OFFSET		0x700
+#define GPIOINT_MASK_OFFSET		0x900
+#define GPIOINT_PEND_OFFSET		0xA00
+
+#define GPIOINT_LEVEL_LOW		0x0
+#define GPIOINT_LEVEL_HIGH		0x1
+#define GPIOINT_EDGE_FALLING		0x2
+#define GPIOINT_EDGE_RISING		0x3
+#define GPIOINT_EDGE_BOTH		0x4
+
+static struct s3c_gpio_chip *s3c_chips[S5P_GPIOINT_GROUP_NR];
+
+static int s5p_gpioint_get_group(unsigned int irq)
+{
+	struct gpio_chip *chip = get_irq_data(irq);
+	struct s3c_gpio_chip *s3c_chip = container_of(chip,
+			struct s3c_gpio_chip, chip);
+	int group;
+
+	for (group = 0; group < S5P_GPIOINT_GROUP_NR; group++)
+		if (s3c_chip == s3c_chips[group])
+			break;
+
+	return group;
+}
+
+static int s5p_gpioint_get_offset(unsigned int irq)
+{
+	struct gpio_chip *chip = get_irq_data(irq);
+	return irq - S5P_IRQ_GPIOINT(chip->base);
+}
+
+static void s5p_gpioint_ack(unsigned int irq)
+{
+	int group, offset, pend_offset;
+	unsigned int value;
+
+	group = s5p_gpioint_get_group(irq);
+	offset = s5p_gpioint_get_offset(irq);
+	pend_offset = group << 2;
+
+	value = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
+	value |= 1 << offset;
+	__raw_writel(value, S5P_GPIOREG(GPIOINT_PEND_OFFSET) + pend_offset);
+}
+
+static void s5p_gpioint_mask(unsigned int irq)
+{
+	int group, offset, mask_offset;
+	unsigned int value;
+
+	group = s5p_gpioint_get_group(irq);
+	offset = s5p_gpioint_get_offset(irq);
+	mask_offset = group << 2;
+
+	value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+	value |= 1 << offset;
+	__raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+}
+
+static void s5p_gpioint_unmask(unsigned int irq)
+{
+	int group, offset, mask_offset;
+	unsigned int value;
+
+	group = s5p_gpioint_get_group(irq);
+	offset = s5p_gpioint_get_offset(irq);
+	mask_offset = group << 2;
+
+	value = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+	value &= ~(1 << offset);
+	__raw_writel(value, S5P_GPIOREG(GPIOINT_MASK_OFFSET) + mask_offset);
+}
+
+static void s5p_gpioint_mask_ack(unsigned int irq)
+{
+	s5p_gpioint_mask(irq);
+	s5p_gpioint_ack(irq);
+}
+
+static int s5p_gpioint_set_type(unsigned int irq, unsigned int type)
+{
+	int group, offset, con_offset;
+	unsigned int value;
+
+	group = s5p_gpioint_get_group(irq);
+	offset = s5p_gpioint_get_offset(irq);
+	con_offset = group << 2;
+
+	switch (type) {
+	case IRQ_TYPE_NONE:
+		printk(KERN_WARNING "No irq type\n");
+		return -EINVAL;
+	case IRQ_TYPE_EDGE_RISING:
+		type = GPIOINT_EDGE_RISING;
+		break;
+	case IRQ_TYPE_EDGE_FALLING:
+		type = GPIOINT_EDGE_FALLING;
+		break;
+	case IRQ_TYPE_EDGE_BOTH:
+		type = GPIOINT_EDGE_BOTH;
+		break;
+	case IRQ_TYPE_LEVEL_HIGH:
+		type = GPIOINT_LEVEL_HIGH;
+		break;
+	case IRQ_TYPE_LEVEL_LOW:
+		type = GPIOINT_LEVEL_LOW;
+		break;
+	default:
+		BUG();
+	}
+
+	value = __raw_readl(S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset);
+	value &= ~(0xf << (offset * 0x4));
+	value |= (type << (offset * 0x4));
+	__raw_writel(value, S5P_GPIOREG(GPIOINT_CON_OFFSET) + con_offset);
+
+	return 0;
+}
+
+struct irq_chip s5p_gpioint = {
+	.name		= "GPIO",
+	.ack		= s5p_gpioint_ack,
+	.mask		= s5p_gpioint_mask,
+	.mask_ack	= s5p_gpioint_mask_ack,
+	.unmask		= s5p_gpioint_unmask,
+	.set_type	= s5p_gpioint_set_type,
+};
+
+static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
+{
+	int group, offset, pend_offset, mask_offset;
+	int real_irq;
+	unsigned int pend, mask;
+
+	for (group = 0; group < S5P_GPIOINT_GROUP_NR; group++) {
+		pend_offset = group << 2;
+		pend = __raw_readl(S5P_GPIOREG(GPIOINT_PEND_OFFSET) +
+				pend_offset);
+		if (!pend)
+			continue;
+
+		mask_offset = group << 2;
+		mask = __raw_readl(S5P_GPIOREG(GPIOINT_MASK_OFFSET) +
+				mask_offset);
+		pend &= ~mask;
+
+		for (offset = 0; offset < 8; offset++) {
+			if (pend & (1 << offset)) {
+				real_irq = s3c_chips[group]->chip.base +
+					   offset;
+				generic_handle_irq(S5P_IRQ_GPIOINT(real_irq));
+			}
+		}
+	}
+}
+
+void s5p_gpioint_add(struct s3c_gpio_chip *chip, int group)
+{
+	int irq;
+	int i;
+
+	s3c_chips[group] = chip;
+
+	for (i = 0; i < chip->chip.ngpio; i++) {
+		irq = S5P_GPIOINT_BASE + chip->chip.base + i;
+		set_irq_chip(irq, &s5p_gpioint);
+		set_irq_data(irq, &chip->chip);
+		set_irq_handler(irq, handle_level_irq);
+		set_irq_flags(irq, IRQF_VALID);
+	}
+}
+
+int __init s5p_gpioint_init(void)
+{
+	/* register gpio interrupt handler */
+	set_irq_chained_handler(IRQ_GPIOINT, s5p_gpioint_handler);
+
+	return 0;
+}
+
+arch_initcall(s5p_gpioint_init);
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index e358c7d..12ec82c 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -121,6 +121,8 @@ extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
 /* exported for core SoC support to change */
 extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
 
+extern void s5p_gpioint_add(struct s3c_gpio_chip *chip, int group);
+
 #ifdef CONFIG_S3C_GPIO_TRACK
 extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END];
 
-- 
1.7.0.4



From jy0922.shim at samsung.com  Fri Jun 11 04:33:18 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 11 Jun 2010 17:33:18 +0900
Subject: [PATCH v2 2/4] ARM: S5PC100: Use S5P gpio interrupts interface
In-Reply-To: <1276245200-18052-1-git-send-email-jy0922.shim@samsung.com>
References: <1276245200-18052-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1276245200-18052-2-git-send-email-jy0922.shim@samsung.com>

The s5pc100 can use s5p gpio interrupts codes instead of s5pc100
specific gpio interrupts codes.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pc100/Makefile            |    2 +-
 arch/arm/mach-s5pc100/gpiolib.c           |   40 +----
 arch/arm/mach-s5pc100/include/mach/irqs.h |   18 ++-
 arch/arm/mach-s5pc100/irq-gpio.c          |  266 -----------------------------
 4 files changed, 25 insertions(+), 301 deletions(-)
 delete mode 100644 arch/arm/mach-s5pc100/irq-gpio.c

diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 543f3de..e9723f8 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -11,7 +11,7 @@ obj-				:=
 
 # Core support for S5PC100 system
 
-obj-$(CONFIG_CPU_S5PC100)	+= cpu.o init.o clock.o gpiolib.o irq-gpio.o
+obj-$(CONFIG_CPU_S5PC100)	+= cpu.o init.o clock.o gpiolib.o
 obj-$(CONFIG_CPU_S5PC100)	+= setup-i2c0.o
 obj-$(CONFIG_CPU_S5PC100)	+= dma.o
 
diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index 0fab7f2..40c3e56 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -63,7 +63,7 @@
 
 static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
 {
-	return S3C_IRQ_GPIO(chip->base + offset);
+	return S5P_IRQ_GPIOINT(chip->base + offset);
 }
 
 static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
@@ -380,47 +380,27 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 	},
 };
 
-/* FIXME move from irq-gpio.c */
-extern struct irq_chip s5pc100_gpioint;
-extern void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
-
-static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
-{
-	/* Interrupt */
-	if (chip->config == &gpio_cfg) {
-		int i, irq;
-
-		chip->chip.to_irq = s5pc100_gpiolib_to_irq;
-
-		for (i = 0;  i < chip->chip.ngpio; i++) {
-			irq = S3C_IRQ_GPIO_BASE + chip->chip.base + i;
-			set_irq_chip(irq, &s5pc100_gpioint);
-			set_irq_data(irq, &chip->chip);
-			set_irq_handler(irq, handle_level_irq);
-			set_irq_flags(irq, IRQF_VALID);
-		}
-	} else if (chip->config == &gpio_cfg_eint) {
-		chip->chip.to_irq = s5pc100_gpiolib_to_eint;
-	}
-}
-
 static __init int s5pc100_gpiolib_init(void)
 {
 	struct s3c_gpio_chip *chip;
 	int nr_chips;
+	int gpioint_group = 0;
 
 	chip = s5pc100_gpio_chips;
 	nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
 
-	for (; nr_chips > 0; nr_chips--, chip++)
-		s5pc100_gpiolib_link(chip);
+	for (; nr_chips > 0; nr_chips--, chip++) {
+		if (chip->config == &gpio_cfg) {
+			/* gpio interrupts */
+			chip->chip.to_irq = s5pc100_gpiolib_to_irq;
+			s5p_gpioint_add(chip, gpioint_group++);
+		} else if (chip->config == &gpio_cfg_eint)
+			chip->chip.to_irq = s5pc100_gpiolib_to_eint;
+	}
 
 	samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
 				       ARRAY_SIZE(s5pc100_gpio_chips));
 
-	/* Interrupt */
-	set_irq_chained_handler(IRQ_GPIOINT, s5pc100_irq_gpioint_handler);
-
 	return 0;
 }
 core_initcall(s5pc100_gpiolib_init);
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 28aa551..8f725bd 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -100,11 +100,21 @@
 #define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2		(IRQ_VIC_END + 1)
 
-#define S3C_IRQ_GPIO_BASE	(IRQ_EINT(31) + 1)
-#define S3C_IRQ_GPIO(x)		(S3C_IRQ_GPIO_BASE + (x))
+#define S5P_GPIOINT_GROUP_NR	21
+#define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
+#define S5P_IRQ_GPIOINT(x)	(S5P_GPIOINT_BASE + (x))
 
-/* Until MP04 Groups -> 40 (exactly 39) Groups * 8 ~= 320 GPIOs */
-#define NR_IRQS		(S3C_IRQ_GPIO(320) + 1)
+/* Set the default NR_IRQS */
+
+/*
+ * GPIO groups is 25. Each GPIO group can have max 8 GPIO interrupts.
+ *
+ * We should include gpios of all gpio groups from GPIO_A0 until GPIO_J4 to
+ * NR_IRQS because 21 gpio groups having gpio interrupts aren't in order and
+ * are mixed with no interrupt gpio groups, then it can give simple irq
+ * computation of gpio interrupts.
+ */
+#define NR_IRQS			(S5P_IRQ_GPIOINT(25 * 8) + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0
diff --git a/arch/arm/mach-s5pc100/irq-gpio.c b/arch/arm/mach-s5pc100/irq-gpio.c
deleted file mode 100644
index 2bf86c1..0000000
--- a/arch/arm/mach-s5pc100/irq-gpio.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * arch/arm/mach-s5pc100/irq-gpio.c
- *
- * Copyright (C) 2009 Samsung Electronics
- *
- * S5PC100 - Interrupt handling for IRQ_GPIO${group}(x)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-
-#include <mach/map.h>
-#include <plat/gpio-cfg.h>
-
-#define S5P_GPIOREG(x)		(S5P_VA_GPIO + (x))
-
-#define CON_OFFSET			0x700
-#define MASK_OFFSET			0x900
-#define PEND_OFFSET			0xA00
-#define CON_OFFSET_2			0xE00
-#define MASK_OFFSET_2			0xF00
-#define PEND_OFFSET_2			0xF40
-
-#define GPIOINT_LEVEL_LOW		0x0
-#define GPIOINT_LEVEL_HIGH		0x1
-#define GPIOINT_EDGE_FALLING		0x2
-#define GPIOINT_EDGE_RISING		0x3
-#define GPIOINT_EDGE_BOTH		0x4
-
-static int group_to_con_offset(int group)
-{
-	return group << 2;
-}
-
-static int group_to_mask_offset(int group)
-{
-	return group << 2;
-}
-
-static int group_to_pend_offset(int group)
-{
-	return group << 2;
-}
-
-static int s5pc100_get_start(unsigned int group)
-{
-	switch (group) {
-	case 0: return S5PC100_GPIO_A0_START;
-	case 1: return S5PC100_GPIO_A1_START;
-	case 2: return S5PC100_GPIO_B_START;
-	case 3: return S5PC100_GPIO_C_START;
-	case 4: return S5PC100_GPIO_D_START;
-	case 5: return S5PC100_GPIO_E0_START;
-	case 6: return S5PC100_GPIO_E1_START;
-	case 7: return S5PC100_GPIO_F0_START;
-	case 8: return S5PC100_GPIO_F1_START;
-	case 9: return S5PC100_GPIO_F2_START;
-	case 10: return S5PC100_GPIO_F3_START;
-	case 11: return S5PC100_GPIO_G0_START;
-	case 12: return S5PC100_GPIO_G1_START;
-	case 13: return S5PC100_GPIO_G2_START;
-	case 14: return S5PC100_GPIO_G3_START;
-	case 15: return S5PC100_GPIO_I_START;
-	case 16: return S5PC100_GPIO_J0_START;
-	case 17: return S5PC100_GPIO_J1_START;
-	case 18: return S5PC100_GPIO_J2_START;
-	case 19: return S5PC100_GPIO_J3_START;
-	case 20: return S5PC100_GPIO_J4_START;
-	default:
-		BUG();
-	}
-
-	return -EINVAL;
-}
-
-static int s5pc100_get_group(unsigned int irq)
-{
-	irq -= S3C_IRQ_GPIO(0);
-
-	switch (irq) {
-	case S5PC100_GPIO_A0_START ... S5PC100_GPIO_A1_START - 1:
-		return 0;
-	case S5PC100_GPIO_A1_START ... S5PC100_GPIO_B_START - 1:
-		return 1;
-	case S5PC100_GPIO_B_START ... S5PC100_GPIO_C_START - 1:
-		return 2;
-	case S5PC100_GPIO_C_START ... S5PC100_GPIO_D_START - 1:
-		return 3;
-	case S5PC100_GPIO_D_START ... S5PC100_GPIO_E0_START - 1:
-		return 4;
-	case S5PC100_GPIO_E0_START ... S5PC100_GPIO_E1_START - 1:
-		return 5;
-	case S5PC100_GPIO_E1_START ... S5PC100_GPIO_F0_START - 1:
-		return 6;
-	case S5PC100_GPIO_F0_START ... S5PC100_GPIO_F1_START - 1:
-		return 7;
-	case S5PC100_GPIO_F1_START ... S5PC100_GPIO_F2_START - 1:
-		return 8;
-	case S5PC100_GPIO_F2_START ... S5PC100_GPIO_F3_START - 1:
-		return 9;
-	case S5PC100_GPIO_F3_START ... S5PC100_GPIO_G0_START - 1:
-		return 10;
-	case S5PC100_GPIO_G0_START ... S5PC100_GPIO_G1_START - 1:
-		return 11;
-	case S5PC100_GPIO_G1_START ... S5PC100_GPIO_G2_START - 1:
-		return 12;
-	case S5PC100_GPIO_G2_START ... S5PC100_GPIO_G3_START - 1:
-		return 13;
-	case S5PC100_GPIO_G3_START ... S5PC100_GPIO_H0_START - 1:
-		return 14;
-	case S5PC100_GPIO_I_START ... S5PC100_GPIO_J0_START - 1:
-		return 15;
-	case S5PC100_GPIO_J0_START ... S5PC100_GPIO_J1_START - 1:
-		return 16;
-	case S5PC100_GPIO_J1_START ... S5PC100_GPIO_J2_START - 1:
-		return 17;
-	case S5PC100_GPIO_J2_START ... S5PC100_GPIO_J3_START - 1:
-		return 18;
-	case S5PC100_GPIO_J3_START ... S5PC100_GPIO_J4_START - 1:
-		return 19;
-	case S5PC100_GPIO_J4_START ... S5PC100_GPIO_K0_START - 1:
-		return 20;
-	default:
-		BUG();
-	}
-
-	return -EINVAL;
-}
-
-static int s5pc100_get_offset(unsigned int irq)
-{
-	struct gpio_chip *chip = get_irq_data(irq);
-	return irq - S3C_IRQ_GPIO(chip->base);
-}
-
-static void s5pc100_gpioint_ack(unsigned int irq)
-{
-	int group, offset, pend_offset;
-	unsigned int value;
-
-	group = s5pc100_get_group(irq);
-	offset = s5pc100_get_offset(irq);
-	pend_offset = group_to_pend_offset(group);
-
-	value = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
-	value |= 1 << offset;
-	__raw_writel(value, S5P_GPIOREG(PEND_OFFSET) + pend_offset);
-}
-
-static void s5pc100_gpioint_mask(unsigned int irq)
-{
-	int group, offset, mask_offset;
-	unsigned int value;
-
-	group = s5pc100_get_group(irq);
-	offset = s5pc100_get_offset(irq);
-	mask_offset = group_to_mask_offset(group);
-
-	value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-	value |= 1 << offset;
-	__raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-}
-
-static void s5pc100_gpioint_unmask(unsigned int irq)
-{
-	int group, offset, mask_offset;
-	unsigned int value;
-
-	group = s5pc100_get_group(irq);
-	offset = s5pc100_get_offset(irq);
-	mask_offset = group_to_mask_offset(group);
-
-	value = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-	value &= ~(1 << offset);
-	__raw_writel(value, S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-}
-
-static void s5pc100_gpioint_mask_ack(unsigned int irq)
-{
-	s5pc100_gpioint_mask(irq);
-	s5pc100_gpioint_ack(irq);
-}
-
-static int s5pc100_gpioint_set_type(unsigned int irq, unsigned int type)
-{
-	int group, offset, con_offset;
-	unsigned int value;
-
-	group = s5pc100_get_group(irq);
-	offset = s5pc100_get_offset(irq);
-	con_offset = group_to_con_offset(group);
-
-	switch (type) {
-	case IRQ_TYPE_NONE:
-		printk(KERN_WARNING "No irq type\n");
-		return -EINVAL;
-	case IRQ_TYPE_EDGE_RISING:
-		type = GPIOINT_EDGE_RISING;
-		break;
-	case IRQ_TYPE_EDGE_FALLING:
-		type = GPIOINT_EDGE_FALLING;
-		break;
-	case IRQ_TYPE_EDGE_BOTH:
-		type = GPIOINT_EDGE_BOTH;
-		break;
-	case IRQ_TYPE_LEVEL_HIGH:
-		type = GPIOINT_LEVEL_HIGH;
-		break;
-	case IRQ_TYPE_LEVEL_LOW:
-		type = GPIOINT_LEVEL_LOW;
-		break;
-	default:
-		BUG();
-	}
-
-
-	value = __raw_readl(S5P_GPIOREG(CON_OFFSET) + con_offset);
-	value &= ~(0xf << (offset * 0x4));
-	value |= (type << (offset * 0x4));
-	__raw_writel(value, S5P_GPIOREG(CON_OFFSET) + con_offset);
-
-	return 0;
-}
-
-struct irq_chip s5pc100_gpioint = {
-	.name		= "GPIO",
-	.ack		= s5pc100_gpioint_ack,
-	.mask		= s5pc100_gpioint_mask,
-	.mask_ack	= s5pc100_gpioint_mask_ack,
-	.unmask		= s5pc100_gpioint_unmask,
-	.set_type	= s5pc100_gpioint_set_type,
-};
-
-void s5pc100_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc)
-{
-	int group, offset, pend_offset, mask_offset;
-	int real_irq, group_end;
-	unsigned int pend, mask;
-
-	group_end = 21;
-
-	for (group = 0; group < group_end; group++) {
-		pend_offset = group_to_pend_offset(group);
-		pend = __raw_readl(S5P_GPIOREG(PEND_OFFSET) + pend_offset);
-		if (!pend)
-			continue;
-
-		mask_offset = group_to_mask_offset(group);
-		mask = __raw_readl(S5P_GPIOREG(MASK_OFFSET) + mask_offset);
-		pend &= ~mask;
-
-		for (offset = 0; offset < 8; offset++) {
-			if (pend & (1 << offset)) {
-				real_irq = s5pc100_get_start(group) + offset;
-				generic_handle_irq(S3C_IRQ_GPIO(real_irq));
-			}
-		}
-	}
-}
-- 
1.7.0.4



From jy0922.shim at samsung.com  Fri Jun 11 04:33:19 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 11 Jun 2010 17:33:19 +0900
Subject: [PATCH v2 3/4] ARM: S5PC100: Move external interrupt defines
In-Reply-To: <1276245200-18052-1-git-send-email-jy0922.shim@samsung.com>
References: <1276245200-18052-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1276245200-18052-3-git-send-email-jy0922.shim@samsung.com>

This patch moves external interrupt defines from gpio.h to regs-gpio.h
for consistency with s5pv210.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pc100/include/mach/gpio.h      |    7 -------
 arch/arm/mach-s5pc100/include/mach/regs-gpio.h |    7 +++++++
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
index 71ae1f5..29a8a12 100644
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -146,13 +146,6 @@ enum s5p_gpio_number {
 /* define the number of gpios we need to the one after the MP04() range */
 #define ARCH_NR_GPIOS		(S5PC100_GPIO_END + 1)
 
-#define EINT_MODE		S3C_GPIO_SFN(0x2)
-
-#define EINT_GPIO_0(x)		S5PC100_GPH0(x)
-#define EINT_GPIO_1(x)		S5PC100_GPH1(x)
-#define EINT_GPIO_2(x)		S5PC100_GPH2(x)
-#define EINT_GPIO_3(x)		S5PC100_GPH3(x)
-
 #include <asm-generic/gpio.h>
 
 #endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
index dd6295e..6abe481 100644
--- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
@@ -71,5 +71,12 @@
 #define S5P_EXTINT_RISEEDGE		(0x03)
 #define S5P_EXTINT_BOTHEDGE		(0x04)
 
+#define EINT_MODE		S3C_GPIO_SFN(0x2)
+
+#define EINT_GPIO_0(x)		S5PC100_GPH0(x)
+#define EINT_GPIO_1(x)		S5PC100_GPH1(x)
+#define EINT_GPIO_2(x)		S5PC100_GPH2(x)
+#define EINT_GPIO_3(x)		S5PC100_GPH3(x)
+
 #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
 
-- 
1.7.0.4



From jy0922.shim at samsung.com  Fri Jun 11 04:33:20 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 11 Jun 2010 17:33:20 +0900
Subject: [PATCH v2 4/4] ARM: SAMSUNG: Add GPIOlib gpio_to_irq
In-Reply-To: <1276245200-18052-1-git-send-email-jy0922.shim@samsung.com>
References: <1276245200-18052-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1276245200-18052-4-git-send-email-jy0922.shim@samsung.com>

This patch is to support gpio_to_irq() of GPIOlib for external and gpio
interrupts, then needs adding irq_base member to s3c_gpio_chip struct.
The gpio_to_irq() calls samsung_gpiolib_to_irq function.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pc100/gpiolib.c                |   38 +++++++-----------------
 arch/arm/mach-s5pv210/gpiolib.c                |   10 ++++++
 arch/arm/plat-samsung/gpiolib.c                |    9 +++++
 arch/arm/plat-samsung/include/plat/gpio-core.h |    4 ++
 4 files changed, 34 insertions(+), 27 deletions(-)

diff --git a/arch/arm/mach-s5pc100/gpiolib.c b/arch/arm/mach-s5pc100/gpiolib.c
index 40c3e56..3bcbfc1 100644
--- a/arch/arm/mach-s5pc100/gpiolib.c
+++ b/arch/arm/mach-s5pc100/gpiolib.c
@@ -61,30 +61,6 @@
  * L3	8	4Bit	None
  */
 
-static int s5pc100_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
-{
-	return S5P_IRQ_GPIOINT(chip->base + offset);
-}
-
-static int s5pc100_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
-{
-	int base;
-
-	base = chip->base - S5PC100_GPH0(0);
-	if (base == 0)
-		return IRQ_EINT(offset);
-	base = chip->base - S5PC100_GPH1(0);
-	if (base == 0)
-		return IRQ_EINT(8 + offset);
-	base = chip->base - S5PC100_GPH2(0);
-	if (base == 0)
-		return IRQ_EINT(16 + offset);
-	base = chip->base - S5PC100_GPH3(0);
-	if (base == 0)
-		return IRQ_EINT(24 + offset);
-	return -EINVAL;
-}
-
 static struct s3c_gpio_cfg gpio_cfg = {
 	.set_config	= s3c_gpio_setcfg_s3c64xx_4bit,
 	.set_pull	= s3c_gpio_setpull_updown,
@@ -228,34 +204,42 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
 	}, {
 		.base	= S5PC100_GPH0_BASE,
 		.config	= &gpio_cfg_eint,
+		.irq_base = IRQ_EINT(0),
 		.chip	= {
 			.base	= S5PC100_GPH0(0),
 			.ngpio	= S5PC100_GPIO_H0_NR,
 			.label	= "GPH0",
+			.to_irq = samsung_gpiolib_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPH1_BASE,
 		.config	= &gpio_cfg_eint,
+		.irq_base = IRQ_EINT(8),
 		.chip	= {
 			.base	= S5PC100_GPH1(0),
 			.ngpio	= S5PC100_GPIO_H1_NR,
 			.label	= "GPH1",
+			.to_irq = samsung_gpiolib_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPH2_BASE,
 		.config	= &gpio_cfg_eint,
+		.irq_base = IRQ_EINT(16),
 		.chip	= {
 			.base	= S5PC100_GPH2(0),
 			.ngpio	= S5PC100_GPIO_H2_NR,
 			.label	= "GPH2",
+			.to_irq = samsung_gpiolib_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPH3_BASE,
 		.config	= &gpio_cfg_eint,
+		.irq_base = IRQ_EINT(24),
 		.chip	= {
 			.base	= S5PC100_GPH3(0),
 			.ngpio	= S5PC100_GPIO_H3_NR,
 			.label	= "GPH3",
+			.to_irq = samsung_gpiolib_to_irq,
 		},
 	}, {
 		.base	= S5PC100_GPI_BASE,
@@ -392,10 +376,10 @@ static __init int s5pc100_gpiolib_init(void)
 	for (; nr_chips > 0; nr_chips--, chip++) {
 		if (chip->config == &gpio_cfg) {
 			/* gpio interrupts */
-			chip->chip.to_irq = s5pc100_gpiolib_to_irq;
+			chip->irq_base = S5P_IRQ_GPIOINT(chip->chip.base),
+			chip->chip.to_irq = samsung_gpiolib_to_irq;
 			s5p_gpioint_add(chip, gpioint_group++);
-		} else if (chip->config == &gpio_cfg_eint)
-			chip->chip.to_irq = s5pc100_gpiolib_to_eint;
+		}
 	}
 
 	samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
diff --git a/arch/arm/mach-s5pv210/gpiolib.c b/arch/arm/mach-s5pv210/gpiolib.c
index 16d6747..a4f28f1 100644
--- a/arch/arm/mach-s5pv210/gpiolib.c
+++ b/arch/arm/mach-s5pv210/gpiolib.c
@@ -210,34 +210,42 @@ static struct s3c_gpio_chip s5pv210_gpio_4bit[] = {
 	}, {
 		.base	= (S5P_VA_GPIO + 0xC00),
 		.config	= &gpio_cfg_noint,
+		.irq_base = IRQ_EINT(0),
 		.chip	= {
 			.base	= S5PV210_GPH0(0),
 			.ngpio	= S5PV210_GPIO_H0_NR,
 			.label	= "GPH0",
+			.to_irq = samsung_gpiolib_to_irq,
 		},
 	}, {
 		.base	= (S5P_VA_GPIO + 0xC20),
 		.config	= &gpio_cfg_noint,
+		.irq_base = IRQ_EINT(8),
 		.chip	= {
 			.base	= S5PV210_GPH1(0),
 			.ngpio	= S5PV210_GPIO_H1_NR,
 			.label	= "GPH1",
+			.to_irq = samsung_gpiolib_to_irq,
 		},
 	}, {
 		.base	= (S5P_VA_GPIO + 0xC40),
 		.config	= &gpio_cfg_noint,
+		.irq_base = IRQ_EINT(16),
 		.chip	= {
 			.base	= S5PV210_GPH2(0),
 			.ngpio	= S5PV210_GPIO_H2_NR,
 			.label	= "GPH2",
+			.to_irq = samsung_gpiolib_to_irq,
 		},
 	}, {
 		.base	= (S5P_VA_GPIO + 0xC60),
 		.config	= &gpio_cfg_noint,
+		.irq_base = IRQ_EINT(24),
 		.chip	= {
 			.base	= S5PV210_GPH3(0),
 			.ngpio	= S5PV210_GPIO_H3_NR,
 			.label	= "GPH3",
+			.to_irq = samsung_gpiolib_to_irq,
 		},
 	},
 };
@@ -254,6 +262,8 @@ static __init int s5pv210_gpiolib_init(void)
 			chip->config = &gpio_cfg;
 
 			/* gpio interrupts */
+			chip->irq_base = S5P_IRQ_GPIOINT(chip->chip.base),
+			chip->chip.to_irq = samsung_gpiolib_to_irq;
 			s5p_gpioint_add(chip, gpioint_group++);
 		}
 		if (chip->base == NULL)
diff --git a/arch/arm/plat-samsung/gpiolib.c b/arch/arm/plat-samsung/gpiolib.c
index 8a8ba8b..8cd3091 100644
--- a/arch/arm/plat-samsung/gpiolib.c
+++ b/arch/arm/plat-samsung/gpiolib.c
@@ -197,3 +197,12 @@ void __init samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
 		s3c_gpiolib_add(chip);
 	}
 }
+
+/* be called from gpio_to_irq() */
+int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
+{
+	struct s3c_gpio_chip *s3c_chip = container_of(chip,
+			struct s3c_gpio_chip, chip);
+
+	return s3c_chip->irq_base + offset;
+}
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h
index 12ec82c..920db6c 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-core.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-core.h
@@ -43,6 +43,7 @@ struct s3c_gpio_cfg;
  * struct s3c_gpio_chip - wrapper for specific implementation of gpio
  * @chip: The chip structure to be exported via gpiolib.
  * @base: The base pointer to the gpio configuration registers.
+ * @irq_base: The base irq number.
  * @config: special function and pull-resistor control information.
  * @lock: Lock for exclusive access to this gpio bank.
  * @pm_save: Save information for suspend/resume support.
@@ -63,6 +64,7 @@ struct s3c_gpio_chip {
 	struct s3c_gpio_cfg	*config;
 	struct s3c_gpio_pm	*pm;
 	void __iomem		*base;
+	int			irq_base;
 	spinlock_t		 lock;
 #ifdef CONFIG_PM
 	u32			pm_save[4];
@@ -118,6 +120,8 @@ extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip,
 extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip);
 extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip);
 
+extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset);
+
 /* exported for core SoC support to change */
 extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default;
 
-- 
1.7.0.4



From mcuelenaere at gmail.com  Fri Jun 11 04:54:27 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 10:54:27 +0200
Subject: [PATCH 06/11] USB: s3c-hsotg: Add initial detection and setup
	for dedicated FIFO mode
In-Reply-To: <1276244457-4072-7-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
	<1276244457-4072-7-git-send-email-ben-linux@fluff.org>
Message-ID: <4C11F9C3.20802@gmail.com>

Op 11-06-10 10:20, Ben Dooks schreef:
> Add support for the dedicated FIFO mode on newer SoCs such as the S5PV210
> partly to improve support and to fix the bug where any non-EP0 IN endpoint
> requires its own FIFO allocation.
> 
> To fix this, we ensure that any non-zero IN endpoint is given a TXFIFO
> using the same allocation method as the periodic case (all our current
> hardware has enough FIFOs and FIFO memory for a 1:1 mapping) and ensure
> that the necessary transmission done interrupt is enabled.
> 
> The default settings from reset for the core point all EPs at FIFO0,
> used for the control endpoint. However, the controller documentation
> states that all IN endpoints _must_ have a unique FIFO to avoid any
> contention during transmission.
> 
> Note, this leaves us with a large IN FIFO for EP0 (which re-uses the
> old NPTXFIFO) for an endpoint which cannot shift more than a pair of
> packets at a time... this is a waste, but it looks like we cannot
> re-allocate space to the individual IN FIFOs as they are already
> maxed out (to be confirmed).
> 
> Signed-off-by: Ben Dooks <ben-linux at fluff.org?

Shouldn't this be s/\?/>/ ?

> ---
>  .../arm/plat-samsung/include/plat/regs-usb-hsotg.h |    2 +
>  drivers/usb/gadget/s3c-hsotg.c                     |   40 +++++++++++++++++++-
>  2 files changed, 40 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
> index 8d18d9d..dc90f5e 100644
> --- a/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
> +++ b/arch/arm/plat-samsung/include/plat/regs-usb-hsotg.h
> @@ -226,6 +226,7 @@
>  
>  #define S3C_DIEPMSK				S3C_HSOTG_REG(0x810)
>  
> +#define S3C_DIEPMSK_TxFIFOEmpty			(1 << 7)
>  #define S3C_DIEPMSK_INEPNakEffMsk		(1 << 6)
>  #define S3C_DIEPMSK_INTknEPMisMsk		(1 << 5)
>  #define S3C_DIEPMSK_INTknTXFEmpMsk		(1 << 4)
> @@ -371,6 +372,7 @@
>  
>  #define S3C_DIEPDMA(_a)				S3C_HSOTG_REG(0x914 + ((_a) * 0x20))
>  #define S3C_DOEPDMA(_a)				S3C_HSOTG_REG(0xB14 + ((_a) * 0x20))
> +#define S3C_DTXFSTS(_a)				S3C_HSOTG_REG(0x918 + ((_a) * 0x20))
>  
>  #define S3C_EPFIFO(_a)				S3C_HSOTG_REG(0x1000 + ((_a) * 0x1000))
>  
> diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
> index 5b61bcf..819e75a 100644
> --- a/drivers/usb/gadget/s3c-hsotg.c
> +++ b/drivers/usb/gadget/s3c-hsotg.c
> @@ -12,6 +12,8 @@
>   * published by the Free Software Foundation.
>  */
>  
> +#define DEBUG

I don't think this is an intended change?

> +
>  #include <linux/kernel.h>
>  #include <linux/module.h>
>  #include <linux/spinlock.h>
> @@ -131,6 +133,7 @@ struct s3c_hsotg_ep {
>   * @regs: The memory area mapped for accessing registers.
>   * @regs_res: The resource that was allocated when claiming register space.
>   * @irq: The IRQ number we are using
> + * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
>   * @debug_root: root directrory for debugfs.
>   * @debug_file: main status file for debugfs.
>   * @debug_fifo: FIFO status file for debugfs.
> @@ -149,6 +152,8 @@ struct s3c_hsotg {
>  	struct resource		*regs_res;
>  	int			irq;
>  
> +	unsigned int		dedicated_fifos:1;
> +
>  	struct dentry		*debug_root;
>  	struct dentry		*debug_file;
>  	struct dentry		*debug_fifo;
> @@ -467,7 +472,7 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
>  	if (to_write == 0)
>  		return 0;
>  
> -	if (periodic) {
> +	if (periodic && !hsotg->dedicated_fifos) {
>  		u32 epsize = readl(hsotg->regs + S3C_DIEPTSIZ(hs_ep->index));
>  		int size_left;
>  		int size_done;
> @@ -505,6 +510,11 @@ static int s3c_hsotg_write_fifo(struct s3c_hsotg *hsotg,
>  			s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
>  			return -ENOSPC;
>  		}
> +	} else if (hsotg->dedicated_fifos && hs_ep->index != 0) {
> +		can_write = readl(hsotg->regs + S3C_DTXFSTS(hs_ep->index));
> +
> +		can_write &= 0xffff;
> +		can_write *= 4;
>  	} else {
>  		if (S3C_GNPTXSTS_NPTxQSpcAvail_GET(gnptxsts) == 0) {
>  			dev_dbg(hsotg->dev,
> @@ -1830,6 +1840,15 @@ static void s3c_hsotg_epint(struct s3c_hsotg *hsotg, unsigned int idx,
>  				 __func__, idx);
>  			clear |= S3C_DIEPMSK_INTknEPMisMsk;
>  		}
> +
> +		/* FIFO has space or is empty (see GAHBCFG) */
> +		if (hsotg->dedicated_fifos &&
> +		    ints & S3C_DIEPMSK_TxFIFOEmpty) {
> +			dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
> +				__func__, idx);
> +			s3c_hsotg_trytx(hsotg, hs_ep);
> +			clear |= S3C_DIEPMSK_TxFIFOEmpty;
> +		}
>  	}
>  
>  	writel(clear, hsotg->regs + epint_reg);
> @@ -2281,6 +2300,12 @@ static int s3c_hsotg_ep_enable(struct usb_ep *ep,
>  		break;
>  	}
>  
> +	/* if the hardware has dedicated fifos, we must give each IN EP
> +	 * a unique tx-fifo even if it is non-periodic.
> +	 */
> +	if (dir_in && hsotg->dedicated_fifos)
> +		epctrl |= S3C_DxEPCTL_TxFNum(index);
> +
>  	/* for non control endpoints, set PID to D0 */
>  	if (index)
>  		epctrl |= S3C_DxEPCTL_SetD0PID;
> @@ -2570,7 +2595,8 @@ int usb_gadget_register_driver(struct usb_gadget_driver *driver)
>  
>  	writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
>  	       S3C_DIEPMSK_INTknEPMisMsk |
> -	       S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk,
> +	       S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk |
> +	       ((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0),
>  	       hsotg->regs + S3C_DIEPMSK);
>  
>  	/* don't need XferCompl, we get that from RXFIFO in slave mode. In
> @@ -2797,6 +2823,8 @@ static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
>  
>  static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
>  {
> +	u32 cfg4;
> +
>  	/* unmask subset of endpoint interrupts */
>  
>  	writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
> @@ -2832,6 +2860,14 @@ static void s3c_hsotg_init(struct s3c_hsotg *hsotg)
>  
>  	writel(using_dma(hsotg) ? S3C_GAHBCFG_DMAEn : 0x0,
>  	       hsotg->regs + S3C_GAHBCFG);
> +
> +	/* check hardware configuration */
> +
> +	cfg4 = readl(hsotg->regs + 0x50);
> +	hsotg->dedicated_fifos = (cfg4 >> 25) & 1;
> +
> +	dev_info(hsotg->dev, "%s fifos\n",
> +		 hsotg->dedicated_fifos ? "dedicated" : "shared");
>  }
>  
>  static void s3c_hsotg_dump(struct s3c_hsotg *hsotg)




From m.szyprowski at samsung.com  Fri Jun 11 05:07:23 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 11 Jun 2010 11:07:23 +0200
Subject: [PATCH 10/11] USB: s3c-hsotg: Fix the OUT EP0 limit
In-Reply-To: <1276244457-4072-11-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
	<1276244457-4072-11-git-send-email-ben-linux@fluff.org>
Message-ID: <006901cb0945$842a9e10$8c7fda30$%szyprowski@samsung.com>

Hello,

On Friday, June 11, 2010 10:21 AM Ben Dooks wrote:

> The EP0 out limit is the same as the IN limit, so make them the same.
> 
> Signed-off-by: Ben Dooks <ben-linux at fluff.org>
> 
> tmp-fix

^ looks like this temporary fix managed to get into the final patch series
without proper cleanup.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center




From jeremy.kerr at canonical.com  Fri Jun 11 05:18:44 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Fri, 11 Jun 2010 17:18:44 +0800
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19473.61547.684572.647641@ipc1.ka-ro>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
Message-ID: <201006111718.47426.jeremy.kerr@canonical.com>

Hi Lothar,

> Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> makes it impossible to call those functions in interrupt context.

Do we do this at the moment? I know at least one implementation of clk_enable 
uses a mutex for locking.

Cheers,


Jeremy


From LW at KARO-electronics.de  Fri Jun 11 05:23:56 2010
From: LW at KARO-electronics.de (=?iso-8859-15?Q?Lothar_Wa=DFmann?=)
Date: Fri, 11 Jun 2010 11:23:56 +0200
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <201006111718.47426.jeremy.kerr@canonical.com>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
Message-ID: <19474.172.742782.972629@ipc1.ka-ro>

Hi,

> > Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> > makes it impossible to call those functions in interrupt context.
> 
> Do we do this at the moment? I know at least one implementation of clk_enable 
> uses a mutex for locking.
> 
You are probably talking about the Freescale i.MX51 kernel, that won't
even boot, if you enable CONFIG_DEBUG_KERNEL, CONFIG_DEBUG_SPINLOCK,
CONFIG_DEBUG_LOCKDEP and CONFIG_DEBUG_SPINLOCK_SLEEP.
The mutex in the clock implementation is one of the reasons.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From broonie at opensource.wolfsonmicro.com  Fri Jun 11 05:35:15 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 11 Jun 2010 10:35:15 +0100
Subject: [alsa-devel] [PATCH 0/3] EP93xx: Add i2s audio support
In-Reply-To: <4C114F25.5060809@bluewatersys.com>
References: <1275991272-30122-1-git-send-email-ryan@bluewatersys.com>
	<20100609101742.GA5618@opensource.wolfsonmicro.com>
	<4C100A32.7010403@bluewatersys.com>
	<C54C83DB-A9D3-4A7A-837B-17644B257251@opensource.wolfsonmicro.com>
	<4C114F25.5060809@bluewatersys.com>
Message-ID: <20100611093514.GA12436@sirena.org.uk>

On Fri, Jun 11, 2010 at 08:46:29AM +1200, Ryan Mallon wrote:

> Builds and runs fine.

Excellent, thanks!


From m.szyprowski at samsung.com  Fri Jun 11 05:35:20 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 11 Jun 2010 11:35:20 +0200
Subject: [PATCH 01/11] USB: s3c_hsotg: Add support for external USB clock
In-Reply-To: <1276244457-4072-2-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
	<1276244457-4072-2-git-send-email-ben-linux@fluff.org>
Message-ID: <006a01cb0949$6c7e7300$457b5900$%szyprowski@samsung.com>

Hello,

On Friday, June 11, 2010 10:21 AM Ben Dooks wrote:

> From: Maurus Cuelenaere <mcuelenaere at gmail.com>
> 
> The PLL that drives the USB clock supports 3 input clocks: 12, 24 and 48Mhz.
> This patch adds support to the USB driver for setting the correct register
> bit
> according to the given clock.
> 
> This depends on the following patch:
> [PATCH] ARM: S3C64XX: Add USB external clock definition
> 
> Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
> Signed-off-by: Ben Dooks <ben-linux at fluff.org>
> ---
>  drivers/usb/gadget/s3c-hsotg.c |   19 +++++++++++++++++++
>  1 files changed, 19 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-
> hsotg.c
> index 26193ec..6a303ce 100644
> --- a/drivers/usb/gadget/s3c-hsotg.c
> +++ b/drivers/usb/gadget/s3c-hsotg.c
> @@ -23,6 +23,7 @@
>  #include <linux/delay.h>
>  #include <linux/io.h>
>  #include <linux/slab.h>
> +#include <linux/clk.h>
> 
>  #include <linux/usb/ch9.h>
>  #include <linux/usb/gadget.h>
> @@ -2753,6 +2754,7 @@ static void __devinit s3c_hsotg_initep(struct
> s3c_hsotg *hsotg,
>   */
>  static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
>  {
> +	struct clk *xusbxti;
>  	u32 osc;
> 
>  	writel(0, S3C_PHYPWR);
> @@ -2760,6 +2762,23 @@ static void s3c_hsotg_otgreset(struct s3c_hsotg
> *hsotg)
> 
>  	osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
> 
> +	xusbxti = clk_get(hsotg->dev, "xusbxti");
> +	if (xusbxti && !IS_ERR(xusbxti)) {
> +		switch (clk_get_rate(xusbxti)) {
> +		case 12000000:
> +		    osc |= S3C_PHYCLK_CLKSEL_12M;
> +		    break;
> +		case 24000000:
> +		    osc |= S3C_PHYCLK_CLKSEL_24M;
> +		    break;
> +		default:
> +		case 48000000:
> +		    /* default reference clock */
> +		    break;

One quick style issue: there is some tabs-vs-spaces mess in the above
code.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center





From mcuelenaere at gmail.com  Fri Jun 11 05:46:59 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 11:46:59 +0200
Subject: [PATCH 01/11] USB: s3c_hsotg: Add support for external USB clock
In-Reply-To: <006a01cb0949$6c7e7300$457b5900$%szyprowski@samsung.com>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
	<1276244457-4072-2-git-send-email-ben-linux@fluff.org>
	<006a01cb0949$6c7e7300$457b5900$%szyprowski@samsung.com>
Message-ID: <4C120613.6000507@gmail.com>

The PLL that drives the USB clock supports 3 input clocks: 12, 24 and 48Mhz.
This patch adds support to the USB driver for setting the correct register bit
according to the given clock.

This depends on the following patch:
[PATCH] ARM: S3C64XX: Add USB external clock definition

Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
---

v2: - fixes space issues
    - use MHZ define

---
 drivers/usb/gadget/s3c-hsotg.c |   19 +++++++++++++++++++
 1 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 1f73b48..40ee63a 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -23,6 +23,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/clk.h>
 
 #include <linux/usb/ch9.h>
 #include <linux/usb/gadget.h>
@@ -2699,6 +2700,7 @@ static void __devinit s3c_hsotg_initep(struct s3c_hsotg *hsotg,
  */
 static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
 {
+	struct clk *xusbxti;
 	u32 osc;
 
 	writel(0, S3C_PHYPWR);
@@ -2706,6 +2708,23 @@ static void s3c_hsotg_otgreset(struct s3c_hsotg *hsotg)
 
 	osc = hsotg->plat->is_osc ? S3C_PHYCLK_EXT_OSC : 0;
 
+	xusbxti = clk_get(hsotg->dev, "xusbxti");
+	if (xusbxti && !IS_ERR(xusbxti)) {
+		switch (clk_get_rate(xusbxti)) {
+		case 12*MHZ:
+			osc |= S3C_PHYCLK_CLKSEL_12M;
+			break;
+		case 24*MHZ:
+			osc |= S3C_PHYCLK_CLKSEL_24M;
+			break;
+		default:
+		case 48*MHZ:
+			/* default reference clock */
+			break;
+		}
+		clk_put(xusbxti);
+	}
+
 	writel(osc | 0x10, S3C_PHYCLK);
 
 	/* issue a full set of resets to the otg and core */
-- 
1.7.1





From sshtylyov at mvista.com  Fri Jun 11 05:48:53 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 11 Jun 2010 13:48:53 +0400
Subject: [PATCH v3] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <003301cb0937$e04412c0$a0cc3840$%kim@samsung.com>
References: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
	<4C10C1D6.8080708@ru.mvista.com>
	<003301cb0937$e04412c0$a0cc3840$%kim@samsung.com>
Message-ID: <4C120685.8030306@mvista.com>

Hello.

Kukjin Kim wrote:

>>> From: Abhilash Kesavan <a.kesavan at samsung.com>
>>> Adds support for the Samsung PATA controller. This driver is based on the
>>> Libata subsystem and references the earlier patches sent for IDE subsystem.

> Hi,

> Thanks for your comments.

>>> Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
>>> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
>> [...]

>>> diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
>>> new file mode 100644
>>> index 0000000..fef5515
>>> --- /dev/null
>>> +++ b/drivers/ata/pata_samsung_cf.c
>>> @@ -0,0 +1,608 @@
>>> +/* linux/drivers/ata/pata_samsung_cf.c

>>     File names in the heading comment are discouraged.

> Hmm. I used like that in other device drivers.

    Nevertheless, it's quite an old rule already.

> Ok..will remove the file name in the heading comment.

>> [...]

>>> +
>>> +	piotime = (t2i << 12) | (t2 << 4) | t1;
>>> +
>>> +	return piotime;
>>> +}
>>> +
>>> +static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
>>> +{
>>> +	int mode = adev->pio_mode - XFER_PIO_0;
>>> +	struct s3c_ide_info *info = ap->host->private_data;
>>> +	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
>>> +	ulong piotime;
>>> +
>>> +	/* Calculates timing parameters for PIO mode */
>>> +	piotime = pata_s3c_setup_timing(info, adev);

>>     In fact, for 8-bit (command) timing you should program the slowest mode  of
>> the two drives. However, with CF, you probably only have only one drive per
>> channel...

> Below code looks OK ?

    No, it doesn't.

> 	if (ata_timing_compute(adev, adev->pio_mode, &timing, cycle_time, 0))
> {
> 		dev_err(ap->dev, "Failed to compute ATA timing\n");
> 		piotime = pata_s3c_setup_timing(info, &initial_timing);
> 	} else {
> 		piotime = pata_s3c_setup_timing(info, &timing);
> 	}
> where initial_timing is for PIO0. I have added the below struct

> static const struct ata_timing initial_timing =
> 	{XFER_PIO_0, 70, 290, 240, 600, 165, 150, 0, 600, 0};

    I'd call ata_timing_find_mode(XFER_PIO_0) rather than duplicating the 
ata_timing entry. But really, you shouldn't set any timing for an invalid mode 
and, as I said, you won't be passed one, so there's nor much sense in calling 
ata_timing_compute() and checking its result; anyway, you'd want to call 
ata_timing_find_mode() here instead of ata_timing_compute() because the latter 
returns already quantized timings, but initial_timing is not quantized, you'll 
have to call ata_timing_compute() in pata_s3c_setup_timing() anyway.

>>> +
>>> +	/* Enables IORDY if mode requires it */
>>> +	if (ata_pio_need_iordy(adev))
>>> +		ata_cfg |= S3C_ATA_CFG_IORDYEN;
>>> +	else
>>> +		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
>>> +
>>> +	/* Host controller supports upto PIO4 only */
>>> +	if (mode >= 0 && mode <= 4) {

>>     No need to check -- you won't be passed a mode not specified by your
>> pio_mask.

> Will remove the check.

>>> +static int __devinit pata_s3c_probe(struct platform_device *pdev)
[...]
>>> +	if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {

>>     Probably should call devm_request_mem_region() if you're using
>> devm_ioremap()...

> Will change to devm_request_mem_region.

    This function does exist, if I don't mistake...

>>> +release_mem:
>>> +	release_mem_region(res->start, resource_size(res));
>>> +release_device_mem:
>>> +	kfree(info);

>>     Doesn't using devm_kzalloc() guarantee that the memory will be freed up
>> automatically?

> Will remove kfree and release_mem_region because of devm_kzalloc and
> devm_request_mem_region usage

    I don't know devres librarry capabilities well. Tejun, am I right?

>>> +static struct platform_driver pata_s3c_driver = {
>>> +	.probe		= pata_s3c_probe,
>>>
>>>

>>     2 empty lines -- broken patch?

> Seems OK at my end.

    The sent patch had them, nevertheless.

MBR, Sergei


From u.kleine-koenig at pengutronix.de  Fri Jun 11 05:58:39 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 11 Jun 2010 11:58:39 +0200
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19474.172.742782.972629@ipc1.ka-ro>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
Message-ID: <20100611095839.GC10894@pengutronix.de>

On Fri, Jun 11, 2010 at 11:23:56AM +0200, Lothar Wa?mann wrote:
> Hi,
> 
> > > Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> > > makes it impossible to call those functions in interrupt context.
IMHO if a device generates an irq its clock should already be on.  This
way you don't need to enable or disable a clock in irq context.
 
> > Do we do this at the moment? I know at least one implementation of clk_enable 
> > uses a mutex for locking.
> > 
> You are probably talking about the Freescale i.MX51 kernel, that won't
> even boot, if you enable CONFIG_DEBUG_KERNEL, CONFIG_DEBUG_SPINLOCK,
> CONFIG_DEBUG_LOCKDEP and CONFIG_DEBUG_SPINLOCK_SLEEP.
> The mutex in the clock implementation is one of the reasons.
I will have a look into this later today.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From LW at KARO-electronics.de  Fri Jun 11 06:08:01 2010
From: LW at KARO-electronics.de (=?iso-8859-15?Q?Lothar_Wa=DFmann?=)
Date: Fri, 11 Jun 2010 12:08:01 +0200
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100611095839.GC10894@pengutronix.de>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
Message-ID: <19474.2817.333749.485028@ipc1.ka-ro>

Hi,

> > > > Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> > > > makes it impossible to call those functions in interrupt context.
> IMHO if a device generates an irq its clock should already be on.  This
> way you don't need to enable or disable a clock in irq context.
>  
You may want to disable a clock in the IRQ handler. The VPU driver in
the Freescale BSP for i.MX51 does exactly this.
Anyway I don't see any reason for using a mutex here instead of
spin_lock_irq_save() as all other implementations do.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From m.szyprowski at samsung.com  Fri Jun 11 06:25:26 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 11 Jun 2010 12:25:26 +0200
Subject: s3c-hsotg fixes
In-Reply-To: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
Message-ID: <006c01cb0950$6ced3630$46c7a290$%szyprowski@samsung.com>

Hello,

On Friday, June 11, 2010 10:21 AM Ben Dooks wrote:

> Some further fixes for the s3c-hsotg block, as well as a repost of
> the missed USB phy clock setting patch which either got missed or
> passed over from last time.
> 
> As a note, this series has a patch adding support for dedicated FIFO
> mode, this is in my view a fix, as when the hsotg block is compiled
> with dedicated fifos then each USB IN non-periodic pipe needs to be
> alloacted a unique TX FIFO. We have no actual data on how well the
> block performs when all IN TX NP FIFOs are all set to the same one,
> but it really should be fixed.

This patch series improves the driver a lot. Now it is possible to get
CDC Ethernet gadget working on S5PV210 SoC (Samsung Aquila machine).
However there are still some issues left to be resolved. I've noticed
the following things:

1. CDC Ethernet gadget: there are problems after unplugging and 
plugging the usb cable again while data is being transferred. To trigger
this it is enough to run 'ping host' command on the device and replug
the usb cable. After that no data packets are sent do the usb host
(checked with hardware usb analyser), although the ep0 control transfers
are performed correctly (device has been enumerated correctly).

2. RNDIS Ethernet gadget: after some stress tests I get an error, which
causes RNDIS session to hang (what is probably a direct result of the
otg block reinit/reset). Here is an example log:

[   69.155000] s3c-hsotg s3c-hsotg: s3c_hsotg_handle_rx: unknown status 00000000
[   69.155000] s3c-hsotg s3c-hsotg: DCFG=0x00040020, DCTL=0x00000000,
DIEPMSK=000000af
[   69.155000] s3c-hsotg s3c-hsotg: GAHBCFG=0x00000001, 0x44=0x00000000
[   69.155000] s3c-hsotg s3c-hsotg: GRXFSIZ=0x00000800, GNPTXFSIZ=0x04000800
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[1] FSize=768, StAddr=0x00000f00
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[2] FSize=768, StAddr=0x00001200
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[3] FSize=768, StAddr=0x00001500
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[4] FSize=768, StAddr=0x00001800
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[5] FSize=768, StAddr=0x00001b00
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[6] FSize=768, StAddr=0x00001e00
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[7] FSize=768, StAddr=0x00002100
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[8] FSize=768, StAddr=0x00002400
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[9] FSize=768, StAddr=0x00002700
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[10] FSize=768, StAddr=0x00002a00
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[11] FSize=768, StAddr=0x00002d00
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[12] FSize=768, StAddr=0x00003000
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[13] FSize=768, StAddr=0x00003300
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[14] FSize=768, StAddr=0x00003600
[   69.155000] s3c-hsotg s3c-hsotg: DPTx[15] FSize=768, StAddr=0x00003900
[   69.155000] s3c-hsotg s3c-hsotg: ep0-in: EPCTL=0x00028000, SIZ=0x00000000,
DMA=0x085290ed
[   69.155000] s3c-hsotg s3c-hsotg: ep0-out: EPCTL=0x80028000, SIZ=0x60000000,
DMA=0xca625c65
[   69.155000] s3c-hsotg s3c-hsotg: ep1-in: EPCTL=0x00488200, SIZ=0x20000000,
DMA=0x5f9184b4
[   69.155000] s3c-hsotg s3c-hsotg: ep1-out: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0x318b408d
[   69.155000] s3c-hsotg s3c-hsotg: ep2-in: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0x50d8cf8b
[   69.155000] s3c-hsotg s3c-hsotg: ep2-out: EPCTL=0x800b8200, SIZ=0x00180800,
DMA=0x5792d85e
[   69.155000] s3c-hsotg s3c-hsotg: ep3-in: EPCTL=0x00cc8008, SIZ=0x00000000,
DMA=0x5dee1680
[   69.155000] s3c-hsotg s3c-hsotg: ep3-out: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0xa96c912b
[   69.155000] s3c-hsotg s3c-hsotg: ep4-in: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0x5e84ae7a
[   69.155000] s3c-hsotg s3c-hsotg: ep4-out: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0xef2e9c78
[   69.155000] s3c-hsotg s3c-hsotg: ep5-in: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0x9d8f4d72
[   69.155000] s3c-hsotg s3c-hsotg: ep5-out: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0x93e82a21
[   69.155000] s3c-hsotg s3c-hsotg: ep6-in: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0x202acadf
[   69.155000] s3c-hsotg s3c-hsotg: ep6-out: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0x5520c3c9
[   69.155000] s3c-hsotg s3c-hsotg: ep7-in: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0x782200c2
[   69.155000] s3c-hsotg s3c-hsotg: ep7-out: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0xeb0b8035
[   69.155000] s3c-hsotg s3c-hsotg: ep8-in: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0x002de535
[   69.155000] s3c-hsotg s3c-hsotg: ep8-out: EPCTL=0x00000200, SIZ=0x00000000,
DMA=0x8c0b77f7
[   69.155000] s3c-hsotg s3c-hsotg: ep9-in: EPCTL=0x00000000, SIZ=0x00000000,
DMA=0xa59e32a0
[   69.155000] s3c-hsotg s3c-hsotg: ep9-out: EPCTL=0x00000000, SIZ=0x00000000,
DMA=0x07aa36a2
[   69.155000] s3c-hsotg s3c-hsotg: ep10-in: EPCTL=0x00000000, SIZ=0x00000000,
DMA=0xc6732fd5
[   69.155000] s3c-hsotg s3c-hsotg: ep10-out: EPCTL=0x00000000, SIZ=0x00000000,
DMA=0xfbf3f43d
[   69.155000] s3c-hsotg s3c-hsotg: ep11-in: EPCTL=0x00000000, SIZ=0x00000000,
DMA=0xb1d750a4
[   69.155000] s3c-hsotg s3c-hsotg: ep11-out: EPCTL=0x00000000, SIZ=0x00000000,
DMA=0x30024c06
[   69.155000] s3c-hsotg s3c-hsotg: ep12-in: EPCTL=0x00000000, SIZ=0x00000000,
DMA=0x154162af
[   69.155000] s3c-hsotg s3c-hsotg: ep12-out: EPCTL=0x00000000, SIZ=0x00000000,
DMA=0x60f9ef07
[   69.155000] s3c-hsotg s3c-hsotg: ep13-in: EPCTL=0x00000000, SIZ=0x00000000,
DMA=0xbea16bb2
[   69.155000] s3c-hsotg s3c-hsotg: ep13-out: EPCTL=0x00000000, SIZ=0x00000000,
DMA=0xd1723f0c
[   69.155000] s3c-hsotg s3c-hsotg: ep14-in: EPCTL=0x00000000, SIZ=0x00000000,
DMA=0x40d1795b
[   69.155000] s3c-hsotg s3c-hsotg: ep14-out: EPCTL=0x00000000, SIZ=0x00000000,
DMA=0xc0b155d6
[   69.155000] s3c-hsotg s3c-hsotg: DVBUSDIS=0x00000b8f, DVBUSPULSE=000002c6

I will try to investigate these issues further.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center




From broonie at opensource.wolfsonmicro.com  Fri Jun 11 06:30:48 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 11 Jun 2010 11:30:48 +0100
Subject: [PATCH 1/5] sdhci-s3c: depend on plat-samsung
In-Reply-To: <20100611052407.GX7248@trinity.fluff.org>
References: <1276076383-24825-1-git-send-email-m.szyprowski@samsung.com>
	<1276076383-24825-2-git-send-email-m.szyprowski@samsung.com>
	<000701cb08fd$2f8e15a0$8eaa40e0$%kim@samsung.com>
	<20100611052407.GX7248@trinity.fluff.org>
Message-ID: <20100611103047.GC12436@sirena.org.uk>

On Fri, Jun 11, 2010 at 06:24:07AM +0100, Ben Dooks wrote:

> Hmm, Mr Park and Co really need to learn how to handle the treatment of
> patches. I'm really disapointed that these patches get submitted without
> the proper authour accreditation. If this isn't sorted out then I for
> one will start thinking about giving this stuff an automatic reject.

For this specific patch it looks more like the patch was sufficiently
straightforward that two different people ended up coming up with
identical implementations rather than anything else?


From gores at marvell.com  Fri Jun 11 06:20:01 2010
From: gores at marvell.com (Siddarth Gore)
Date: Fri, 11 Jun 2010 15:50:01 +0530
Subject: L2 cache support for pxa16x
In-Reply-To: <AANLkTilYrgroqxaL0uGnpmTXmUznkijtFmNmkSuFL89V@mail.gmail.com>
References: <1273658181.6926.27.camel@pe-dt434>
	<AANLkTiky2tG7-n5bmMBqhKBIn7tq1tIT0KeWpkUee5YK@mail.gmail.com>
	<1274350676.6926.58.camel@pe-dt434>
	<AANLkTilYrgroqxaL0uGnpmTXmUznkijtFmNmkSuFL89V@mail.gmail.com>
Message-ID: <1276251601.29294.60.camel@pe-dt434>

On Fri, 2010-05-21 at 04:05 -0700, Haojian Zhuang wrote:
> >
> 
> I didn't meet any failure on enabling L2. What I do is in below. Which
> kernel version are you using?
> 
extremely sorry for replying _so_ late. I was using 2.6.34 vanilla
kernel. I tried your patch on latest 2.6.35-rc2 today, and it is
crashing as well (log pasted below).

<...snip...>
Uncompressing Linux... done, booting the kernel.
[    0.000000] Linux version 2.6.35-rc2-00131-g7908a9e-dirty
(gores at linux-dev.marvell.com) (gcc version 4.1.2 20070925 (Red Hat
4.1.2-33.fa1)) #40 PREEMPT Fr
i Jun 11 15:29:40 IST 2010
[    0.000000] CPU: Marvell 88SV331x [56158400] revision 0 (ARMv5TE),
cr=00053947
[    0.000000] CPU: VIVT data cache, VIVT instruction cache
[    0.000000] Machine: PXA168-based Aspenite Development Platform
[    0.000000] Memory policy: ECC disabled, Data cache writeback
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.
Total pages: 65024
[    0.000000] Kernel command line: root=mtd4 rw rootfstype=jffs2
console=ttyS0,115200
[    0.000000] PID hash table entries: 1024 (order: 0, 4096 bytes)
[    0.000000] Dentry cache hash table entries: 32768 (order: 5, 131072
bytes)
[    0.000000] Inode-cache hash table entries: 16384 (order: 4, 65536
bytes)
[    0.000000] Memory: 256MB = 256MB total
[    0.000000] Memory: 256664k/256664k available, 5480k reserved, 0K
highmem
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)
[    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
[    0.000000]     DMA     : 0xffc00000 - 0xffe00000   (   2 MB)
[    0.000000]     vmalloc : 0xd0800000 - 0xfe000000   ( 728 MB)
[    0.000000]     lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)
[    0.000000]     modules : 0xbf000000 - 0xc0000000   (  16 MB)
[    0.000000]       .init : 0xc0008000 - 0xc001d000   (  84 kB)
[    0.000000]       .text : 0xc001d000 - 0xc02d0000   (2764 kB)
[    0.000000]       .data : 0xc02e6000 - 0xc030a460   ( 146 kB)
[    0.000000] Hierarchical RCU implementation.
[    0.000000]  RCU-based detection of stalled CPUs is disabled.
[    0.000000]  Verbose stalled-CPUs detection is disabled.
[    0.000000] NR_IRQS:384
[    0.000000] Console: colour dummy device 80x30
[    0.000015] Calibrating delay loop... 796.26 BogoMIPS (lpj=3981312)
[    0.220115] pid_max: default: 32768 minimum: 301
[    0.220147] Mount-cache hash table entries: 512
[    0.220321] CPU: Testing write buffer coherency: ok
[    0.224377] NET: Registered protocol family 16
[    0.224505] Tauros2: Disabling L2 prefetch.
[    0.224554] Tauros2: Enabling L2 cache.
[    0.224567] Tauros2: L2 cache support initialised in ARMv5 mode.
[    0.231784] bio: create slab <bio-0> at 0

<...snip...>
[    4.243206] VFS: Mounted root (jffs2 filesystem) on device 31:4.
[    4.243249] Freeing init memory: 84K
[    4.370645] BUG: Bad page state in process init  pfn:00563
[    4.376669] page:c0334c60 count:0 mapcount:0 mapping:cf80aab8
index:0x4f
[    4.383411] page flags: 0x8(uptodate)
[    4.383420] [<c00235e8>] (unwind_backtrace+0x0/0xe0) from
[<c006c0d0>] (bad_page+0xc8/0xfc)
[    4.395478] [<c006c0d0>] (bad_page+0xc8/0xfc) from [<c006c16c>]
(free_pages_prepare+0x68/0xbc)
[    4.404141] [<c006c16c>] (free_pages_prepare+0x68/0xbc) from
[<c006c9c4>] (free_hot_cold_page+0x20/0x1a0)
[    4.413758] [<c006c9c4>] (free_hot_cold_page+0x20/0x1a0) from
[<c006cc10>] (__pagevec_free+0x20/0x34)
[    4.423019] [<c006cc10>] (__pagevec_free+0x20/0x34) from [<c0070798>]
(release_pages+0x274/0x28c)
[    4.423048] [<c0070798>] (release_pages+0x274/0x28c) from
[<c0070984>] (____pagevec_lru_add+0x1d4/0x1ec)
[    4.441441] [<c0070984>] (____pagevec_lru_add+0x1d4/0x1ec) from
[<c0070c28>] (lru_add_drain+0x40/0xac)
[    4.450798] [<c0070c28>] (lru_add_drain+0x40/0xac) from [<c00813c8>]
(exit_mmap+0x5c/0x1cc)
[    4.459201] [<c00813c8>] (exit_mmap+0x5c/0x1cc) from [<c0033d08>]
(mmput+0x3c/0x11c)
[    4.466988] [<c0033d08>] (mmput+0x3c/0x11c) from [<c0037f40>]
(exit_mm+0x124/0x130)
[    4.474686] [<c0037f40>] (exit_mm+0x124/0x130) from [<c00394f8>]
(do_exit+0x16c/0x654)
[    4.474712] [<c00394f8>] (do_exit+0x16c/0x654) from [<c0039a98>]
(do_group_exit+0xb8/0xec)
[    4.490928] [<c0039a98>] (do_group_exit+0xb8/0xec) from [<c0045528>]
(get_signal_to_deliver+0x3cc/0x42c)
[    4.500459] [<c0045528>] (get_signal_to_deliver+0x3cc/0x42c) from
[<c00206c4>] (do_notify_resume+0x58/0x5d8)
[    4.510337] [<c00206c4>] (do_notify_resume+0x58/0x5d8) from
[<c001df2c>] (work_pending+0x1c/0x20)
[    4.519263] Disabling lock debugging due to kernel taint
[    4.524634] kernel BUG at lib/prio_tree.c:149!
[    4.524679] Unable to handle kernel NULL pointer dereference at
virtual address 00000000
[    4.529129] pgd = c0004000
[    4.537220] [00000000] *pgd=00000000
[    4.539919] Internal error: Oops: 817 [#1] PREEMPT
[    4.543490] last sysfs file: 
[    4.548277] Modules linked in:
[    4.551238] CPU: 0    Tainted: G    B
(2.6.35-rc2-00131-g7908a9e-dirty #40)
[    4.554290] PC is at __bug+0x1c/0x28
[    4.561862] LR is at __bug+0x18/0x28
[    4.565434] pc : [<c002140c>]    lr : [<c0021408>]    psr: 60000093
[    4.569016] sp : cfc19db0  ip : c0183b34  fp : cfc19fb0
[    4.569025] r10: 00001000  r9 : c02ea1d0  r8 : 00000000
[    4.580503] r7 : cfc725c4  r6 : cfc725a0  r5 : cf80aacc  r4 :
cfc7256c
[    4.585730] r3 : 00000000  r2 : 00000003  r1 : 00002370  r0 :
00000038
[    4.592257] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
Segment user
[    4.598785] Control: 0005397f  Table: 0fd00018  DAC: 00000015
[    4.606008] Process init (pid: 1, stack limit = 0xcfc18278)
[    4.611752] Stack: (0xcfc19db0 to 0xcfc1a000)
[    4.617326] 9da0:                                     cfdc2ce0
c01571cc 00000000 c01572fc
[    4.621688] 9dc0: 00006fab 00000000 00000001 be9ba000 cfd02fa0
cf80aab8 cfc72548 cfc725a0
[    4.629879] 9de0: 00008000 c00817f0 cfc18000 c0081850 cfc18000
c007f298 cfc19e1c cfc18000
[    4.638065] 9e00: cfc18000 00000000 cfc725a0 cfd5bde0 cfc19ee8
00000001 cfc19f68 c0081480
[    4.646250] 9e20: cfc19e28 00000000 00000025 c02ea1d0 cfc15bc0
00000000 cfd5bde0 cfd5be18
[    4.654435] 9e40: cfc15bc0 c0033d08 cfd5bde0 cfc18000 cfd5bde0
c0037f40 00000000 c0044074
[    4.662623] 9e60: cfc18000 cfc18000 cfc15bc0 0000000b 000000dc
c00394f8 00000000 cfc7880c
[    4.670807] 9e80: 0000000b 0000000b cfdc3590 000000dc cfc19ee8
cfc1bd60 cfc19f68 c0039a98
[    4.678993] 9ea0: cfc18000 c0045528 00008000 cfdc35a0 00000000
cfc18000 00000000 cfc19fb0
[    4.687179] 9ec0: 00000000 00000000 cfc18000 4000cfac be9b9d64
c00206c4 cfc15bc0 00000190
[    4.695365] 9ee0: 00020001 c0024978 0000000b 00000000 00030001
00000190 00000000 00000003
[    4.703549] 9f00: 40003000 c032a1e0 4000cfac c001d30c c02f5760
cfd69ba0 cfc18000 00000000
[    4.711736] 9f20: c00cdb3c c0096b44 cfc18000 cfc19f88 cfd69ba0
00000000 cfd69ba0 c02927e8
[    4.719922] 9f40: cfc18000 00000000 00000000 cfd69ba0 c02927e8
c0097fd4 cfdc2d10 00000000
[    4.728107] 9f60: 00000000 c02927e8 c02e98e4 00000000 00001fb0
cfc19f88 00000000 cfc19fb0
[    4.736293] 9f80: cfc18000 c002124c 00000000 ffffffff be9b9f8f
40000000 00000000 00000000
[    4.744479] 9fa0: cfc18000 4000cfac be9b9d64 c001df2c ea00004b
00000190 be9b9f8f 00040000
[    4.752665] 9fc0: 00000000 be9b9f8f 40000000 00000000 00000000
00000000 4000cfac be9b9d64
[    4.760850] 9fe0: be9b9f8f be9b9d58 40003c70 40000a7c a0000010
ffffffff 76f7fd97 fdc53774
[    4.769037] [<c002140c>] (__bug+0x1c/0x28) from [<c01571cc>]
(prio_tree_replace+0x3c/0x90)
[    4.777233] [<c01571cc>] (prio_tree_replace+0x3c/0x90) from
[<c01572fc>] (prio_tree_remove+0xdc/0xf8)
[    4.785517] [<c01572fc>] (prio_tree_remove+0xdc/0xf8) from
[<c00817f0>] (__remove_shared_vm_struct+0xa4/0xd8)
[    4.794758] [<c00817f0>] (__remove_shared_vm_struct+0xa4/0xd8) from
[<c0081850>] (unlink_file_vma+0x2c/0x4c)
[    4.804694] [<c0081850>] (unlink_file_vma+0x2c/0x4c) from
[<c007f298>] (free_pgtables+0x34/0x98)
[    4.814534] [<c007f298>] (free_pgtables+0x34/0x98) from [<c0081480>]
(exit_mmap+0x114/0x1cc)
[    4.823337] [<c0081480>] (exit_mmap+0x114/0x1cc) from [<c0033d08>]
(mmput+0x3c/0x11c)
[    4.831791] [<c0033d08>] (mmput+0x3c/0x11c) from [<c0037f40>]
(exit_mm+0x124/0x130)
[    4.839639] [<c0037f40>] (exit_mm+0x124/0x130) from [<c00394f8>]
(do_exit+0x16c/0x654)
[    4.847311] [<c00394f8>] (do_exit+0x16c/0x654) from [<c0039a98>]
(do_group_exit+0xb8/0xec)
[    4.855245] [<c0039a98>] (do_group_exit+0xb8/0xec) from [<c0045528>]
(get_signal_to_deliver+0x3cc/0x42c)
[    4.863531] [<c0045528>] (get_signal_to_deliver+0x3cc/0x42c) from
[<c00206c4>] (do_notify_resume+0x58/0x5d8)
[    4.873025] [<c00206c4>] (do_notify_resume+0x58/0x5d8) from
[<c001df2c>] (work_pending+0x1c/0x20)
[    4.882874] Code: e1a01000 e59f000c eb0056ac e3a03000 (e5833000) 
[    4.897903] ---[ end trace 053bf21ade3656af ]---
[    4.897921] Fixing recursive fault but reboot is needed!
[    4.907883] BUG: scheduling while atomic: init/1/0x00000004
[    4.913488] Modules linked in:
[    4.913495] [<c00235e8>] (unwind_backtrace+0x0/0xe0) from
[<c0233970>] (schedule+0x6c/0x320)
[    4.929710] kernel BUG at fs/jffs2/readinode.c:154!
[    4.934682] Unable to handle kernel NULL pointer dereference at
virtual address 00000000
[    4.934695] pgd = c0004000
[    4.945504] [00000000] *pgd=00000000
[    4.945513] Internal error: Oops: 817 [#2] PREEMPT
[    4.949086] last sysfs file: 
[    4.953875] Modules linked in:
[    4.956836] CPU: 0    Tainted: G    B D
(2.6.35-rc2-00131-g7908a9e-dirty #40)
[    4.959887] PC is at __bug+0x1c/0x28
[    4.967458] LR is at __bug+0x18/0x28
[    4.971031] pc : [<c002140c>]    lr : [<c0021408>]    psr: 60000013
[    4.974613] sp : cfc71db0  ip : cfc71ca0  fp : cfcae600
[    4.974622] r10: cfc4df80  r9 : cfc4aef0  r8 : cfcaea00
[    4.986101] r7 : 00000000  r6 : cfc4df80  r5 : cfc71e4c  r4 :
cfc4df80
[    4.991327] r3 : 00000000  r2 : 00000000  r1 : 00000001  r0 :
0000003d
[    4.997855] Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM
Segment kernel
[    5.004383] Control: 0005397f  Table: 0fd00018  DAC: 00000017
[    5.011693] Process jffs2_gcd_mtd4 (pid: 194, stack limit =
0xcfc70278)
[    5.017437] Stack: (0xcfc71db0 to 0xcfc72000)
[    5.024051] 1da0:                                     00000002
c0122fb4 00000000 cfc71e70
[    5.028414] 1dc0: cfc68000 cfcaea00 00000110 cfc4df20 cfc4df80
cfc71e4c cfc4df80 00000000
[    5.036605] 1de0: cfcaea00 0000001a cfc4df00 c012341c cfc4df20
00000000 cfc4df80 cfc71e4c
[    5.044791] 1e00: cfc4df80 cfc4df80 000001cb 00000000 cfc71ea4
cfd5a000 00000000 c01246ac
[    5.052976] 1e20: 000007cc cfc71e70 cfd5a000 c02ea8f0 00000085
cfcae600 cfcaea00 00000000
[    5.061163] 1e40: cfc70000 00000000 00008f07 00000000 00000000
cfc4df60 0000001b 00000000
[    5.069347] 1e60: 00000000 00000000 cfd57a98 00000001 000007cc
cfc71e80 c00325ac cfcae600
[    5.077533] 1e80: cfc4b3b0 cfcaea00 00000001 00000000 00000000
00000000 00000000 c0124eb0
[    5.085719] 1ea0: 00000017 c02f4ddc cfc15bc0 c0051664 00000000
c002eb08 c002f388 cfc1801c
[    5.093906] 1ec0: 00000000 cfdc2ce0 cfc71efc cfc71ed8 c0233ba8
c002eff8 cfdc2ce0 ffff8c7e
[    5.102092] 1ee0: c0310a00 00000005 cfc70000 cfc4b3b0 cfcaea00
c012949c ffff8c7e c02343f4
[    5.110278] 1f00: 00000000 00200200 ffff8c7e c0310a00 c00413c8
cfdc2ce0 cfc71fd4 cfc70000
[    5.118462] 1f20: cfcaea00 cfcaea00 00000000 00000000 00000000
c012b070 cfdc2d10 c02ea8f0
[    5.126648] 1f40: cfc71f8c cfc71f50 c00315d0 c002dab0 cfdc2d10
c02ea8f0 cfdc2d10 cfdc2e44
[    5.134836] 1f60: 00000000 00000000 00000000 c002eb1c c02ea8f0
cfdc2d10 cfc71fa4 cfc71f88
[    5.143028] 1f80: c002ebe8 c002eb08 00000000 c02ea8b0 cfdc2ce0
cfc70000 cfc71fcc cfc71fa8
[    5.151214] 1fa0: c0233a70 c002eb70 cfc71fcc cfc71fd4 cfc19e08
cfcaea00 c012af10 cfc71fd4
[    5.159400] 1fc0: cfc19e08 cfcaea00 c012af10 c004bfa8 00000000
00000000 cfc71fd8 cfc71fd8
[    5.167586] 1fe0: 00000000 00000000 00000000 00000000 00000000
c001ef1c 76f7fd97 fdcd3774
[    5.175770] [<c002140c>] (__bug+0x1c/0x28) from [<c0122fb4>]
(check_tn_node+0x54/0x3c4)
[    5.183967] [<c0122fb4>] (check_tn_node+0x54/0x3c4) from [<c012341c>]
(jffs2_build_inode_fragtree+0xf8/0x1ec)
[    5.191993] [<c012341c>] (jffs2_build_inode_fragtree+0xf8/0x1ec) from
[<c01246ac>] (jffs2_do_read_inode_internal+0x119c/0x194c)
[    5.201921] [<c01246ac>] (jffs2_do_read_inode_internal+0x119c/0x194c)
from [<c0124eb0>] (jffs2_do_crccheck_inode+0x54/0x94)
[    5.213414] [<c0124eb0>] (jffs2_do_crccheck_inode+0x54/0x94) from
[<c012949c>] (jffs2_garbage_collect_pass+0x21c/0x974)
[    5.224561] [<c012949c>] (jffs2_garbage_collect_pass+0x21c/0x974)
from [<c012b070>] (jffs2_garbage_collect_thread+0x160/0x1b8)
[    5.235360] [<c012b070>] (jffs2_garbage_collect_thread+0x160/0x1b8)
from [<c004bfa8>] (kthread+0x78/0x80)
[    5.246766] [<c004bfa8>] (kthread+0x78/0x80) from [<c001ef1c>]
(kernel_thread_exit+0x0/0x8)
[    5.256347] Code: e1a01000 e59f000c eb0056ac e3a03000 (e5833000) 
[    5.270951] ---[ end trace 053bf21ade3656b0 ]---
[    7.022826] kernel BUG at mm/slab.c:509!
[    7.022938] Unable to handle kernel NULL pointer dereference at
virtual address 00000000
[    7.026862] pgd = c0004000
[    7.034956] [00000000] *pgd=00000000
[    7.037655] Internal error: Oops: 817 [#3] PREEMPT
[    7.041224] last sysfs file: 
[    7.046014] Modules linked in:
[    7.048973] CPU: 0    Tainted: G    B D
(2.6.35-rc2-00131-g7908a9e-dirty #40)
[    7.052024] PC is at __bug+0x1c/0x28
[    7.059598] LR is at __bug+0x18/0x28
[    7.063170] pc : [<c002140c>]    lr : [<c0021408>]    psr: 60000093
[    7.066751] sp : cfc31f40  ip : c0183b34  fp : 00000000
[    7.066761] r10: 00000001  r9 : 00000000  r8 : 00000000
[    7.078238] r7 : 00000000  r6 : cfc05130  r5 : cfc003c0  r4 :
cfc05130
[    7.083465] r3 : 00000000  r2 : 00000001  r1 : 000045ae  r0 :
00000032
[    7.089993] Flags: nZCv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
Segment kernel
[    7.096521] Control: 0005397f  Table: 0fd00018  DAC: 00000017
[    7.103917] Process events/0 (pid: 5, stack limit = 0xcfc30278)
[    7.109661] Stack: (0xcfc31f40 to 0xcfc32000)
[    7.115582] 1f40: 00000017 c008ea44 cfcab660 cfc05130 00000001
cfc05120 00000000 cfc003c0
[    7.119951] 1f60: 00000000 c008ebf8 cfc022a0 cfc003c0 00000000
c02f51c8 c008fc90 c008fccc
[    7.128135] 1f80: 00000000 cfc018e0 c02f51c8 c02f51cc cfc30000
cfc018e0 c02f51c8 c0048eb4
[    7.136322] 1fa0: c0233a70 00000000 cfc15040 c004c268 cfc31fb0
cfc31fb0 cfc31fd4 cfc19f60
[    7.144507] 1fc0: cfc018e0 c0048d84 00000000 c004bfa8 00000000
00000000 cfc31fd8 cfc31fd8
[    7.152692] 1fe0: 00000000 00000000 00000000 00000000 00000000
c001ef1c 76f7fd97 fdcd3774
[    7.160877] [<c002140c>] (__bug+0x1c/0x28) from [<c008ea44>]
(free_block+0x60/0x15c)
[    7.169073] [<c008ea44>] (free_block+0x60/0x15c) from [<c008ebf8>]
(drain_array+0xb8/0x108)
[    7.176829] [<c008ebf8>] (drain_array+0xb8/0x108) from [<c008fccc>]
(cache_reap+0x3c/0x114)
[    7.185196] [<c008fccc>] (cache_reap+0x3c/0x114) from [<c0048eb4>]
(worker_thread+0x130/0x1f8)
[    7.193570] [<c0048eb4>] (worker_thread+0x130/0x1f8) from
[<c004bfa8>] (kthread+0x78/0x80)
[    7.202205] [<c004bfa8>] (kthread+0x78/0x80) from [<c001ef1c>]
(kernel_thread_exit+0x0/0x8)
[    7.210481] Code: e1a01000 e59f000c eb0056ac e3a03000 (e5833000) 
[    7.224964] ---[ end trace 053bf21ade3656b1 ]---
[    7.224979] note: events/0[5] exited with preempt_count 1

-siddarth
> 
> diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
> index 652ae66..689e0d5 100644
> --- a/arch/arm/mach-mmp/pxa168.c
> +++ b/arch/arm/mach-mmp/pxa168.c
> @@ -15,6 +15,7 @@
>  #include <linux/io.h>
>  #include <linux/clk.h>
> 
> +#include <asm/hardware/cache-tauros2.h>
>  #include <asm/mach/time.h>
>  #include <mach/addr-map.h>
>  #include <mach/cputype.h>
> @@ -101,6 +102,7 @@ static struct clk_lookup pxa168_clkregs[] = {
>  static int __init pxa168_init(void)
>  {
>         if (cpu_is_pxa168()) {
> +               tauros2_init();
>                 mfp_init_base(MFPR_VIRT_BASE);
>                 mfp_init_addr(pxa168_mfp_addr_map);
>                 pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
> diff --git a/arch/arm/mm/cache-tauros2.c b/arch/arm/mm/cache-tauros2.c
> index 5086865..79f49f5 100644
> --- a/arch/arm/mm/cache-tauros2.c
> +++ b/arch/arm/mm/cache-tauros2.c
> @@ -120,7 +120,11 @@ static inline u32 __init read_extra_features(void)
> 
>  static inline void __init write_extra_features(u32 u)
>  {
> +       volatile u32 cp15;
>         __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
> +       __asm__("mrc p15, 0, %0, c1, c0, 0" : "=r" (cp15));
> +       cp15 |= (1 << 26);
> +       __asm__("mcr p15, 0, %0, c1, c0, 0" : : "r" (cp15));
>  }



From nicolas.ferre at atmel.com  Fri Jun 11 06:50:32 2010
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 11 Jun 2010 12:50:32 +0200
Subject: [PATCH] AT91: add new at91 chips in at91sam9g45 family
In-Reply-To: <1273509900-30278-1-git-send-email-nicolas.ferre@atmel.com>
References: <1273509900-30278-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <4C1214F8.80005@atmel.com>

Le 10/05/2010 18:45, Nicolas Ferre :
> This is the basic support for at91sam9g46, at91sam9m10 and at91sam9m11. Those
> are just very basic cpu macros and clock definition.
> 
> Signed-off-by: Patrice Vilchez <patrice.vilchez at atmel.com>
> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>

Acked-by Andrew Victor added.
Submitted as patch 6169/1
http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6169/1

Best regards,
-- 
Nicolas Ferre



From jeremy.kerr at canonical.com  Fri Jun 11 06:50:30 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Fri, 11 Jun 2010 18:50:30 +0800
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19474.2817.333749.485028@ipc1.ka-ro>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
Message-ID: <201006111850.32528.jeremy.kerr@canonical.com>

Hi Lothar,

> You may want to disable a clock in the IRQ handler. The VPU driver in
> the Freescale BSP for i.MX51 does exactly this.

Is this something we can defer to a sleepable context?

> Anyway I don't see any reason for using a mutex here instead of
> spin_lock_irq_save() as all other implementations do.

Just that enable/disable may take an arbitrarily long time to complete. Sounds 
like that hasn't been a problem in the past though.

Cheers,


Jeremy


From jamie at jamieiles.com  Fri Jun 11 08:15:45 2010
From: jamie at jamieiles.com (Jamie Iles)
Date: Fri, 11 Jun 2010 13:15:45 +0100
Subject: kmalloc/__get_free_pages and SHMLBA
Message-ID: <20100611120841.GF4403@wear.picochip.com>

I'm writing a driver at the moment that mmap()'s a buffer into userspace and
then performs DMA from the kernel buffer into the device. If I allocate with
kmalloc()/__get_free_pages() is there anything that can be done to guarantee
that the allocation is aligned to SHMLBA or do I need to try overallocating
and do this myself?

The alternative is to use vmalloc_user() and use vmalloc_to_page() to get the
direct mapping addresses to perform the DMA mapping but I'd like to be able to
DMA the whole buffer without the need for scatterlists.

Jamie


From catalin.marinas at arm.com  Fri Jun 11 08:22:16 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 11 Jun 2010 13:22:16 +0100
Subject: [PATCH] sa1111: Prevent deadlock in resume path
In-Reply-To: <20100610135609.GC4514@ucw.cz>
References: <1274901104-22133-1-git-send-email-marek.vasut@gmail.com>
	<20100526191425.GD6232@n2100.arm.linux.org.uk>
	<201005262115.57282.marek.vasut@gmail.com>
	<20100526201824.GA16418@n2100.arm.linux.org.uk>
	<20100610135609.GC4514@ucw.cz>
Message-ID: <1276258936.16663.39.camel@e102109-lin.cambridge.arm.com>

On Thu, 2010-06-10 at 14:56 +0100, Pavel Machek wrote:
> On Wed 2010-05-26 21:18:24, Russell King - ARM Linux wrote:
> > On Wed, May 26, 2010 at 09:15:57PM +0200, Marek Vasut wrote:
> > > You want me to fight your patch tracking system or will you just merge it into
> > > your tree ?
> >
> > What do you mean "fight" ?  Just send a standard git formatted patch
> > to the email address with an additional KernelVersion: tag.  It's
> > not at all hard.
> 
> You are linux kernel maintainer. Start acting as one. It is not at all
> hard.
> 
> Alternatively, just remove KernelVersion: checking in  your
> scripts.

BTW (and I'm not complaining about Russell's patch system here), how can
we get the linux-arm-kernel list subscribed to patchwork.kernel.org?
That would be useful for grabbing RFC/CFT patches.

-- 
Catalin



From marek.vasut at gmail.com  Fri Jun 11 09:17:05 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 11 Jun 2010 15:17:05 +0200
Subject: [PATCH 1/2] ARM/scoop: Add CPR register bit definitions
Message-ID: <1276262226-15015-1-git-send-email-marek.vasut@gmail.com>

Add bit definitions of the CPR register of the SCOOP chip into scoop.h

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/include/asm/hardware/scoop.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h
index 46492a6..5821f21 100644
--- a/arch/arm/include/asm/hardware/scoop.h
+++ b/arch/arm/include/asm/hardware/scoop.h
@@ -22,6 +22,11 @@
 #define SCOOP_GPWR 0x24
 #define SCOOP_GPRR 0x28
 
+#define SCOOP_CPR_OUT	( 1 << 7 )
+#define SCOOP_CPR_SD_3V	( 1 << 2 )
+#define SCOOP_CPR_CF_XV	( 1 << 1 )
+#define SCOOP_CPR_CF_3V	( 1 << 0 )
+
 #define SCOOP_GPCR_PA22	( 1 << 12 )
 #define SCOOP_GPCR_PA21	( 1 << 11 )
 #define SCOOP_GPCR_PA20	( 1 << 10 )
-- 
1.7.1



From marek.vasut at gmail.com  Fri Jun 11 09:17:06 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 11 Jun 2010 15:17:06 +0200
Subject: [PATCH 2/2] pxa/spitz: Rework spitz
In-Reply-To: <1276262226-15015-1-git-send-email-marek.vasut@gmail.com>
References: <1276262226-15015-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1276262226-15015-2-git-send-email-marek.vasut@gmail.com>

This huge patch mostly shuffles code. The spitz.c file contained terrible mess
and needed a cleanup, here it is:

1) Made every part modular, components are not built in if not selected.
2) Removed loads of preprocessor goo, mostly "#ifdef MACH_AKITA .... #endif" and
   similar code. The kernel size will grow by a few kb now, but the file is much
   more readable.
3) Reworked SD/CF power setting function and made it reentrant.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/include/mach/spitz.h |    2 -
 arch/arm/mach-pxa/spitz.c              |  748 ++++++++++++++++++--------------
 2 files changed, 420 insertions(+), 330 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index fa1998c..685749a 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
@@ -185,7 +185,5 @@
 /*
  * Shared data structures
  */
-extern struct platform_device spitzscoop_device;
-extern struct platform_device spitzscoop2_device;
 extern struct platform_device spitzssp_device;
 extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 4d2413e..bf6a7d4 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -18,12 +18,12 @@
 #include <linux/gpio_keys.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
-#include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/spi/corgi_lcd.h>
+#include <linux/mtd/physmap.h>
 #include <linux/mtd/sharpsl.h>
 #include <linux/input/matrix_keypad.h>
 
@@ -33,11 +33,9 @@
 #include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/scoop.h>
 
-
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/reset.h>
-#include <plat/i2c.h>
 #include <mach/irda.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
@@ -45,11 +43,16 @@
 #include <mach/pxa2xx_spi.h>
 #include <mach/spitz.h>
 
+#include <plat/i2c.h>
+
 #include "generic.h"
 #include "devices.h"
 #include "sharpsl.h"
 
-static unsigned long spitz_pin_config[] __initdata = {
+/******************************************************************************
+ * Pin configuration
+ ******************************************************************************/
+static unsigned long sharpslc_pin_config[] __initdata = {
 	/* Chip Selects */
 	GPIO78_nCS_2,	/* SCOOP #2 */
 	GPIO79_nCS_3,	/* NAND */
@@ -124,10 +127,13 @@ static unsigned long spitz_pin_config[] __initdata = {
 	GPIO1_GPIO | WAKEUP_ON_EDGE_FALL,	/* SPITZ_GPIO_RESET */
 };
 
-/*
- * Spitz SCOOP Device #1
- */
-static struct resource spitz_scoop_resources[] = {
+
+/******************************************************************************
+ * Scoop GPIO expander
+ ******************************************************************************/
+#if defined(CONFIG_SHARP_SCOOP) || defined(CONFIG_SHARP_SCOOP_MODULE)
+/* SCOOP Device #1 */
+static struct resource sharpslc_scoop_1_resources[] = {
 	[0] = {
 		.start		= 0x10800000,
 		.end		= 0x10800fff,
@@ -135,7 +141,7 @@ static struct resource spitz_scoop_resources[] = {
 	},
 };
 
-static struct scoop_config spitz_scoop_setup = {
+static struct scoop_config sharpslc_scoop_1_setup = {
 	.io_dir		= SPITZ_SCP_IO_DIR,
 	.io_out		= SPITZ_SCP_IO_OUT,
 	.suspend_clr	= SPITZ_SCP_SUS_CLR,
@@ -143,20 +149,18 @@ static struct scoop_config spitz_scoop_setup = {
 	.gpio_base	= SPITZ_SCP_GPIO_BASE,
 };
 
-struct platform_device spitzscoop_device = {
+struct platform_device sharpslc_scoop_1_device = {
 	.name		= "sharp-scoop",
 	.id		= 0,
 	.dev		= {
- 		.platform_data	= &spitz_scoop_setup,
+ 		.platform_data	= &sharpslc_scoop_1_setup,
 	},
-	.num_resources	= ARRAY_SIZE(spitz_scoop_resources),
-	.resource	= spitz_scoop_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_scoop_1_resources),
+	.resource	= sharpslc_scoop_1_resources,
 };
 
-/*
- * Spitz SCOOP Device #2
- */
-static struct resource spitz_scoop2_resources[] = {
+/* SCOOP Device #2 */
+static struct resource sharpslc_scoop_2_resources[] = {
 	[0] = {
 		.start		= 0x08800040,
 		.end		= 0x08800fff,
@@ -164,7 +168,7 @@ static struct resource spitz_scoop2_resources[] = {
 	},
 };
 
-static struct scoop_config spitz_scoop2_setup = {
+static struct scoop_config sharpslc_scoop_2_setup = {
 	.io_dir		= SPITZ_SCP2_IO_DIR,
 	.io_out		= SPITZ_SCP2_IO_OUT,
 	.suspend_clr	= SPITZ_SCP2_SUS_CLR,
@@ -172,82 +176,110 @@ static struct scoop_config spitz_scoop2_setup = {
 	.gpio_base	= SPITZ_SCP2_GPIO_BASE,
 };
 
-struct platform_device spitzscoop2_device = {
+struct platform_device sharpslc_scoop_2_device = {
 	.name		= "sharp-scoop",
 	.id		= 1,
 	.dev		= {
- 		.platform_data	= &spitz_scoop2_setup,
+ 		.platform_data	= &sharpslc_scoop_2_setup,
 	},
-	.num_resources	= ARRAY_SIZE(spitz_scoop2_resources),
-	.resource	= spitz_scoop2_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_scoop_2_resources),
+	.resource	= sharpslc_scoop_2_resources,
 };
 
-#define SPITZ_PWR_SD 0x01
-#define SPITZ_PWR_CF 0x02
+static void __init sharpslc_scoop_init(void)
+{
+	platform_device_register(&sharpslc_scoop_1_device);
+
+	/* Akita doesn't have the second SCOOP chip */
+	if (!machine_is_akita())
+		platform_device_register(&sharpslc_scoop_2_device);
+}
 
 /* Power control is shared with between one of the CF slots and SD */
-static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr)
+static void sharpslc_card_pwr_ctrl(int enable, unsigned short new_cpr)
 {
-	unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR);
+	unsigned short cpr;
+	unsigned long flags;
 
-	if (new_cpr & 0x0007) {
+	if (new_cpr & 0x7) {
 		gpio_set_value(SPITZ_GPIO_CF_POWER, 1);
-		if (!(cpr & 0x0002) && !(cpr & 0x0004))
-		        mdelay(5);
-		if (device == SPITZ_PWR_CF)
-		        cpr |= 0x0002;
-		if (device == SPITZ_PWR_SD)
-		        cpr |= 0x0004;
-	        write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
-	} else {
-		if (device == SPITZ_PWR_CF)
-		        cpr &= ~0x0002;
-		if (device == SPITZ_PWR_SD)
-		        cpr &= ~0x0004;
-		if (!(cpr & 0x0002) && !(cpr & 0x0004)) {
-			write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, 0x0000);
-		        mdelay(1);
-			gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
-		} else {
-		        write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
-		}
+		mdelay(5);
+	}
+		
+	local_irq_save(flags);
+
+	cpr = read_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR);
+
+	if (enable & new_cpr)
+		cpr |= new_cpr;
+	else
+		cpr &= ~enable;
+
+        write_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR, cpr);
+
+	local_irq_restore(flags);
+
+	if (!(cpr & 0x7)) {
+	        mdelay(1);
+		gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
 	}
 }
 
-static void spitz_pcmcia_pwr(struct device *scoop, unsigned short cpr, int nr)
+#else
+static inline void sharpslc_scoop_init(void) {}
+static inline void sharpslc_card_pwr_ctrl(int device, unsigned short new_cpr) {}
+#endif
+
+/******************************************************************************
+ * PCMCIA
+ ******************************************************************************/
+#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
+static void sharpslc_pcmcia_pwr(struct device *scoop, unsigned short cpr, int nr)
 {
 	/* Only need to override behaviour for slot 0 */
 	if (nr == 0)
-		spitz_card_pwr_ctrl(SPITZ_PWR_CF, cpr);
+		sharpslc_card_pwr_ctrl(
+			cpr & (SCOOP_CPR_CF_3V | SCOOP_CPR_CF_XV), cpr);
 	else
 		write_scoop_reg(scoop, SCOOP_CPR, cpr);
 }
 
-static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
-{
-	.dev        = &spitzscoop_device.dev,
-	.irq        = SPITZ_IRQ_GPIO_CF_IRQ,
-	.cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
-	.cd_irq_str = "PCMCIA0 CD",
-},{
-	.dev        = &spitzscoop2_device.dev,
-	.irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
-	.cd_irq     = -1,
-},
+static struct scoop_pcmcia_dev sharpslc_pcmcia_scoop[] = {
+	{
+		.dev        = &sharpslc_scoop_1_device.dev,
+		.irq        = SPITZ_IRQ_GPIO_CF_IRQ,
+		.cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
+		.cd_irq_str = "PCMCIA0 CD",
+	},{
+		.dev        = &sharpslc_scoop_2_device.dev,
+		.irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
+		.cd_irq     = -1,
+	},
 };
 
-static struct scoop_pcmcia_config spitz_pcmcia_config = {
-	.devs         = &spitz_pcmcia_scoop[0],
-	.num_devs     = 2,
-	.power_ctrl   = spitz_pcmcia_pwr,
+static struct scoop_pcmcia_config sharpslc_pcmcia_config = {
+	.devs		= &sharpslc_pcmcia_scoop[0],
+	.num_devs	= 2,
+	.power_ctrl	= sharpslc_pcmcia_pwr,
 };
 
-EXPORT_SYMBOL(spitzscoop_device);
-EXPORT_SYMBOL(spitzscoop2_device);
+static void __init sharpslc_pcmcia_init(void)
+{
+	/* Akita has only one PCMCIA slot used */
+	if (machine_is_akita())
+		sharpslc_pcmcia_config.num_devs = 1;
+
+	platform_scoop_config = &sharpslc_pcmcia_config;
+}
+#else
+static inline void sharpslc_pcmcia_init(void) {}
+#endif
+
+/******************************************************************************
+ * GPIO keyboard
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
 
-/*
- * Spitz Keyboard Device
- */
 #define SPITZ_KEY_CALENDAR	KEY_F1
 #define SPITZ_KEY_ADDRESS	KEY_F2
 #define SPITZ_KEY_FN		KEY_F3
@@ -263,7 +295,7 @@ EXPORT_SYMBOL(spitzscoop2_device);
 #define SPITZ_KEY_OK		KEY_F11
 #define SPITZ_KEY_MENU		KEY_F12
 
-static const uint32_t spitzkbd_keymap[] = {
+static const uint32_t sharpslc_keymap[] = {
 	KEY(0, 0, KEY_LEFTCTRL),
 	KEY(0, 1, KEY_1),
 	KEY(0, 2, KEY_3),
@@ -330,37 +362,48 @@ static const uint32_t spitzkbd_keymap[] = {
 	KEY(6, 8, KEY_RIGHT),
 };
 
-static const struct matrix_keymap_data spitzkbd_keymap_data = {
-	.keymap		= spitzkbd_keymap,
-	.keymap_size	= ARRAY_SIZE(spitzkbd_keymap),
+static const struct matrix_keymap_data sharpslc_keymap_data = {
+	.keymap		= sharpslc_keymap,
+	.keymap_size	= ARRAY_SIZE(sharpslc_keymap),
 };
 
-static const uint32_t spitzkbd_row_gpios[] =
+static const uint32_t sharpslc_row_gpios[] =
 		{ 12, 17, 91, 34, 36, 38, 39 };
-static const uint32_t spitzkbd_col_gpios[] =
+static const uint32_t sharpslc_col_gpios[] =
 		{ 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 };
 
-static struct matrix_keypad_platform_data spitzkbd_pdata = {
-	.keymap_data		= &spitzkbd_keymap_data,
-	.row_gpios		= spitzkbd_row_gpios,
-	.col_gpios		= spitzkbd_col_gpios,
-	.num_row_gpios		= ARRAY_SIZE(spitzkbd_row_gpios),
-	.num_col_gpios		= ARRAY_SIZE(spitzkbd_col_gpios),
+static struct matrix_keypad_platform_data sharpslc_mkp_pdata = {
+	.keymap_data		= &sharpslc_keymap_data,
+	.row_gpios		= sharpslc_row_gpios,
+	.col_gpios		= sharpslc_col_gpios,
+	.num_row_gpios		= ARRAY_SIZE(sharpslc_row_gpios),
+	.num_col_gpios		= ARRAY_SIZE(sharpslc_col_gpios),
 	.col_scan_delay_us	= 10,
 	.debounce_ms		= 10,
 	.wakeup			= 1,
 };
 
-static struct platform_device spitzkbd_device = {
+static struct platform_device sharpslc_mkp_device = {
 	.name		= "matrix-keypad",
 	.id		= -1,
 	.dev		= {
-		.platform_data = &spitzkbd_pdata,
+		.platform_data	= &sharpslc_mkp_pdata,
 	},
 };
 
+static void __init sharpslc_mkp_init(void)
+{
+	platform_device_register(&sharpslc_mkp_device);
+}
+#else
+static inline void sharpslc_mkp_init(void) {}
+#endif
 
-static struct gpio_keys_button spitz_gpio_keys[] = {
+/******************************************************************************
+ * GPIO keys
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button sharpslc_gpio_keys[] = {
 	{
 		.type	= EV_PWR,
 		.code	= KEY_SUSPEND,
@@ -383,27 +426,35 @@ static struct gpio_keys_button spitz_gpio_keys[] = {
 	},
 };
 
-static struct gpio_keys_platform_data spitz_gpio_keys_platform_data = {
-	.buttons	= spitz_gpio_keys,
-	.nbuttons	= ARRAY_SIZE(spitz_gpio_keys),
+static struct gpio_keys_platform_data sharpslc_gpio_keys_platform_data = {
+	.buttons	= sharpslc_gpio_keys,
+	.nbuttons	= ARRAY_SIZE(sharpslc_gpio_keys),
 };
 
-static struct platform_device spitz_gpio_keys_device = {
+static struct platform_device sharpslc_gpio_keys_device = {
 	.name	= "gpio-keys",
 	.id	= -1,
 	.dev	= {
-		.platform_data	= &spitz_gpio_keys_platform_data,
+		.platform_data	= &sharpslc_gpio_keys_platform_data,
 	},
 };
 
+static void __init sharpslc_keys_init(void)
+{
+	platform_device_register(&sharpslc_gpio_keys_device);
+}
+#else
+static inline void sharpslc_keys_init(void) {}
+#endif
 
-/*
- * Spitz LEDs
- */
-static struct gpio_led spitz_gpio_leds[] = {
+/******************************************************************************
+ * LEDs
+ ******************************************************************************/
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static struct gpio_led sharpslc_gpio_leds[] = {
 	{
 		.name			= "spitz:amber:charge",
-		.default_trigger	= "sharpsl-charge",
+		.default_trigger	= "sharpslc-charge",
 		.gpio			= SPITZ_GPIO_LED_ORANGE,
 	},
 	{
@@ -413,25 +464,32 @@ static struct gpio_led spitz_gpio_leds[] = {
 	},
 };
 
-static struct gpio_led_platform_data spitz_gpio_leds_info = {
-	.leds		= spitz_gpio_leds,
-	.num_leds	= ARRAY_SIZE(spitz_gpio_leds),
+static struct gpio_led_platform_data sharpslc_gpio_leds_info = {
+	.leds		= sharpslc_gpio_leds,
+	.num_leds	= ARRAY_SIZE(sharpslc_gpio_leds),
 };
 
-static struct platform_device spitzled_device = {
+static struct platform_device sharpslc_led_device = {
 	.name		= "leds-gpio",
 	.id		= -1,
 	.dev		= {
-		.platform_data = &spitz_gpio_leds_info,
+		.platform_data	= &sharpslc_gpio_leds_info,
 	},
 };
 
-#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_master spitz_spi_info = {
-	.num_chipselect	= 3,
-};
+static void __init sharpslc_leds_init(void)
+{
+	platform_device_register(&sharpslc_led_device);
+}
+#else
+static inline void sharpslc_leds_init(void) {}
+#endif
 
-static void spitz_wait_for_hsync(void)
+/******************************************************************************
+ * SSP Devices
+ ******************************************************************************/
+#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
+static void sharpslc_ads7846_wait_for_hsync(void)
 {
 	while (gpio_get_value(SPITZ_GPIO_HSYNC))
 		cpu_relax();
@@ -440,21 +498,21 @@ static void spitz_wait_for_hsync(void)
 		cpu_relax();
 }
 
-static struct ads7846_platform_data spitz_ads7846_info = {
+static struct ads7846_platform_data sharpslc_ads7846_info = {
 	.model			= 7846,
 	.vref_delay_usecs	= 100,
 	.x_plate_ohms		= 419,
 	.y_plate_ohms		= 486,
 	.pressure_max		= 1024,
 	.gpio_pendown		= SPITZ_GPIO_TP_INT,
-	.wait_for_sync		= spitz_wait_for_hsync,
+	.wait_for_sync		= sharpslc_ads7846_wait_for_hsync,
 };
 
-static struct pxa2xx_spi_chip spitz_ads7846_chip = {
+static struct pxa2xx_spi_chip sharpslc_ads7846_chip = {
 	.gpio_cs		= SPITZ_GPIO_ADS7846_CS,
 };
 
-static void spitz_bl_kick_battery(void)
+static void sharpslc_bl_kick_battery(void)
 {
 	void (*kick_batt)(void);
 
@@ -465,93 +523,107 @@ static void spitz_bl_kick_battery(void)
 	}
 }
 
-static struct corgi_lcd_platform_data spitz_lcdcon_info = {
+static struct corgi_lcd_platform_data sharpslc_lcdcon_info = {
 	.init_mode		= CORGI_LCD_MODE_VGA,
 	.max_intensity		= 0x2f,
 	.default_intensity	= 0x1f,
 	.limit_mask		= 0x0b,
 	.gpio_backlight_cont	= SPITZ_GPIO_BACKLIGHT_CONT,
 	.gpio_backlight_on	= SPITZ_GPIO_BACKLIGHT_ON,
-	.kick_battery		= spitz_bl_kick_battery,
+	.kick_battery		= sharpslc_bl_kick_battery,
 };
 
-static struct pxa2xx_spi_chip spitz_lcdcon_chip = {
+static struct pxa2xx_spi_chip sharpslc_lcdcon_chip = {
 	.gpio_cs	= SPITZ_GPIO_LCDCON_CS,
 };
 
-static struct pxa2xx_spi_chip spitz_max1111_chip = {
+static struct pxa2xx_spi_chip sharpslc_max1111_chip = {
 	.gpio_cs	= SPITZ_GPIO_MAX1111_CS,
 };
 
-static struct spi_board_info spitz_spi_devices[] = {
+static struct spi_board_info sharpslc_spi_devices[] = {
 	{
 		.modalias	= "ads7846",
 		.max_speed_hz	= 1200000,
 		.bus_num	= 2,
 		.chip_select	= 0,
-		.platform_data	= &spitz_ads7846_info,
-		.controller_data= &spitz_ads7846_chip,
+		.platform_data	= &sharpslc_ads7846_info,
+		.controller_data= &sharpslc_ads7846_chip,
 		.irq		= gpio_to_irq(SPITZ_GPIO_TP_INT),
 	}, {
 		.modalias	= "corgi-lcd",
 		.max_speed_hz	= 50000,
 		.bus_num	= 2,
 		.chip_select	= 1,
-		.platform_data	= &spitz_lcdcon_info,
-		.controller_data= &spitz_lcdcon_chip,
+		.platform_data	= &sharpslc_lcdcon_info,
+		.controller_data= &sharpslc_lcdcon_chip,
 	}, {
 		.modalias	= "max1111",
 		.max_speed_hz	= 450000,
 		.bus_num	= 2,
 		.chip_select	= 2,
-		.controller_data= &spitz_max1111_chip,
+		.controller_data= &sharpslc_max1111_chip,
 	},
 };
 
-static void __init spitz_init_spi(void)
+static struct pxa2xx_spi_master sharpslc_spi_info = {
+	.num_chipselect	= 3,
+};
+
+static void __init sharpslc_spi_init(void)
 {
 	if (machine_is_akita()) {
-		spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
-		spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
+		sharpslc_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
+		sharpslc_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
 	}
 
-	pxa2xx_set_spi_info(2, &spitz_spi_info);
-	spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
+	pxa2xx_set_spi_info(2, &sharpslc_spi_info);
+	spi_register_board_info(ARRAY_AND_SIZE(sharpslc_spi_devices));
 }
 #else
-static inline void spitz_init_spi(void) {}
+static inline void sharpslc_spi_init(void) {}
 #endif
 
+/******************************************************************************
+ * SD/MMC card controller
+ ******************************************************************************/
+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
 /*
- * MMC/SD Device
- *
- * The card detect interrupt isn't debounced so we delay it by 250ms
- * to give the card a chance to fully insert/eject.
+ * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
+ * give the card a chance to fully insert/eject.
  */
-static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
+static void sharpslc_mci_setpower(struct device *dev, unsigned int vdd)
 {
 	struct pxamci_platform_data* p_d = dev->platform_data;
 
-	if (( 1 << vdd) & p_d->ocr_mask)
-		spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0004);
+	if ((1 << vdd) & p_d->ocr_mask)
+		sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
 	else
-		spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0000);
+		sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
 }
 
-static struct pxamci_platform_data spitz_mci_platform_data = {
+static struct pxamci_platform_data sharpslc_mci_platform_data = {
 	.detect_delay_ms	= 250,
 	.ocr_mask		= MMC_VDD_32_33|MMC_VDD_33_34,
-	.setpower 		= spitz_mci_setpower,
+	.setpower 		= sharpslc_mci_setpower,
 	.gpio_card_detect	= SPITZ_GPIO_nSD_DETECT,
 	.gpio_card_ro		= SPITZ_GPIO_nSD_WP,
 	.gpio_power		= -1,
 };
 
+static void __init sharpslc_mmc_init(void)
+{
+	pxa_set_mci_info(&sharpslc_mci_platform_data);
+}
+#else
+static inline void sharpslc_mmc_init(void) {}
+#endif
 
-/*
- * USB Host (OHCI)
- */
-static int spitz_ohci_init(struct device *dev)
+/******************************************************************************
+ * USB Host
+ ******************************************************************************/
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static int sharpslc_ohci_init(struct device *dev)
 {
 	int err;
 
@@ -559,88 +631,114 @@ static int spitz_ohci_init(struct device *dev)
 	if (err)
 		return err;
 
-	/* Only Port 2 is connected
-	 * Setup USB Port 2 Output Control Register
-	 */
+	/* Only Port 2 is connected, setup USB Port 2 Output Control Register */
 	UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
 
 	return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1);
 }
 
-static void spitz_ohci_exit(struct device *dev)
+static void sharpslc_ohci_exit(struct device *dev)
 {
 	gpio_free(SPITZ_GPIO_USB_HOST);
 }
 
-static struct pxaohci_platform_data spitz_ohci_platform_data = {
+static struct pxaohci_platform_data sharpslc_ohci_platform_data = {
 	.port_mode	= PMM_NPS_MODE,
-	.init		= spitz_ohci_init,
-	.exit		= spitz_ohci_exit,
+	.init		= sharpslc_ohci_init,
+	.exit		= sharpslc_ohci_exit,
 	.flags		= ENABLE_PORT_ALL | NO_OC_PROTECTION,
 	.power_budget	= 150,
 };
 
+static void __init sharpslc_uhc_init(void)
+{
+	pxa_set_ohci_info(&sharpslc_ohci_platform_data);
+}
+#else
+static inline void sharpslc_uhc_init(void) {}
+#endif
 
-/*
- * Irda
- */
-
-static struct pxaficp_platform_data spitz_ficp_platform_data = {
-/* .gpio_pwdown is set in spitz_init() and akita_init() accordingly */
+/******************************************************************************
+ * IrDA
+ ******************************************************************************/
+#if defined(CONFIG_PXA_FICP) || defined(CONFIG_PXA_FICP_MODULE)
+static struct pxaficp_platform_data sharpslc_ficp_platform_data = {
 	.transceiver_cap	= IR_SIRMODE | IR_OFF,
 };
 
+static void __init sharpslc_irda_init(void)
+{
+	if (machine_is_akita())
+		sharpslc_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
+	else
+		sharpslc_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
 
-/*
- * Spitz PXA Framebuffer
- */
+	pxa_set_ficp_info(&sharpslc_ficp_platform_data);
+}
+#else
+static inline void sharpslc_irda_init(void) {}
+#endif
 
-static struct pxafb_mode_info spitz_pxafb_modes[] = {
-{
-	.pixclock       = 19231,
-	.xres           = 480,
-	.yres           = 640,
-	.bpp            = 16,
-	.hsync_len      = 40,
-	.left_margin    = 46,
-	.right_margin   = 125,
-	.vsync_len      = 3,
-	.upper_margin   = 1,
-	.lower_margin   = 0,
-	.sync           = 0,
-},{
-	.pixclock       = 134617,
-	.xres           = 240,
-	.yres           = 320,
-	.bpp            = 16,
-	.hsync_len      = 20,
-	.left_margin    = 20,
-	.right_margin   = 46,
-	.vsync_len      = 2,
-	.upper_margin   = 1,
-	.lower_margin   = 0,
-	.sync           = 0,
-},
-};
-
-static struct pxafb_mach_info spitz_pxafb_info = {
-	.modes          = &spitz_pxafb_modes[0],
-	.num_modes      = 2,
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static struct pxafb_mode_info sharpslc_pxafb_modes[] = {
+	{
+		.pixclock       = 19231,
+		.xres           = 480,
+		.yres           = 640,
+		.bpp            = 16,
+		.hsync_len      = 40,
+		.left_margin    = 46,
+		.right_margin   = 125,
+		.vsync_len      = 3,
+		.upper_margin   = 1,
+		.lower_margin   = 0,
+		.sync           = 0,
+	},{
+		.pixclock       = 134617,
+		.xres           = 240,
+		.yres           = 320,
+		.bpp            = 16,
+		.hsync_len      = 20,
+		.left_margin    = 20,
+		.right_margin   = 46,
+		.vsync_len      = 2,
+		.upper_margin   = 1,
+		.lower_margin   = 0,
+		.sync           = 0,
+	},
+};
+
+static struct pxafb_mach_info sharpslc_pxafb_info = {
+	.modes          = sharpslc_pxafb_modes,
+	.num_modes      = ARRAY_SIZE(sharpslc_pxafb_modes),
 	.fixed_modes    = 1,
 	.lcd_conn	= LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
 };
 
-static struct mtd_partition sharpsl_nand_partitions[] = {
+static void __init sharpslc_lcd_init(void)
+{
+	set_pxa_fb_info(&sharpslc_pxafb_info);
+}
+#else
+static inline void sharpslc_lcd_init(void) {}
+#endif
+
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+#if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE)
+static struct mtd_partition sharpslc_nand_partitions[] = {
 	{
 		.name = "System Area",
 		.offset = 0,
 		.size = 7 * 1024 * 1024,
-	},
-	{
+	}, {
 		.name = "Root Filesystem",
 		.offset = 7 * 1024 * 1024,
-	},
-	{
+	}, {
 		.name = "Home Filesystem",
 		.offset = MTDPART_OFS_APPEND,
 		.size = MTDPART_SIZ_FULL,
@@ -649,37 +747,72 @@ static struct mtd_partition sharpsl_nand_partitions[] = {
 
 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
 
-static struct nand_bbt_descr sharpsl_bbt = {
-	.options = 0,
-	.offs = 4,
-	.len = 2,
-	.pattern = scan_ff_pattern
+static struct nand_bbt_descr sharpslc_nand_bbt = {
+	.options	= 0,
+	.offs		= 4,
+	.len		= 2,
+	.pattern	= scan_ff_pattern
 };
 
-static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
-	.badblock_pattern	= &sharpsl_bbt,
-	.partitions		= sharpsl_nand_partitions,
-	.nr_partitions		= ARRAY_SIZE(sharpsl_nand_partitions),
+static struct nand_ecclayout sharpslc_akita_oobinfo = {
+	.oobfree	= {{0x08, 0x09}},
+	.eccbytes	= 24,
+	.eccpos		= {
+			0x05, 0x01, 0x02, 0x03, 0x06, 0x07, 0x15, 0x11,
+			0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
+			0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37,
+	},
+};
+
+static struct sharpsl_nand_platform_data sharpslc_nand_platform_data = {
+	.badblock_pattern	= &sharpslc_nand_bbt,
+	.partitions		= sharpslc_nand_partitions,
+	.nr_partitions		= ARRAY_SIZE(sharpslc_nand_partitions),
 };
 
-static struct resource sharpsl_nand_resources[] = {
+static struct resource sharpslc_nand_resources[] = {
 	{
-		.start	= 0x0C000000,
-		.end	= 0x0C000FFF,
+		.start	= PXA_CS3_PHYS,
+		.end	= PXA_CS3_PHYS + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 
-static struct platform_device sharpsl_nand_device = {
+static struct platform_device sharpslc_nand_device = {
 	.name		= "sharpsl-nand",
 	.id		= -1,
-	.resource	= sharpsl_nand_resources,
-	.num_resources	= ARRAY_SIZE(sharpsl_nand_resources),
-	.dev.platform_data	= &sharpsl_nand_platform_data,
+	.resource	= sharpslc_nand_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_nand_resources),
+	.dev		= {
+		.platform_data	= &sharpslc_nand_platform_data,
+	}
 };
 
+static void __init sharpslc_nand_init(void)
+{
+	if (machine_is_spitz()) {
+		sharpslc_nand_partitions[1].size = 5 * 1024 * 1024;
+	} else if (machine_is_akita()) {
+		sharpslc_nand_partitions[1].size = 58 * 1024 * 1024;
+		sharpslc_nand_bbt.len = 1;
+		sharpslc_nand_platform_data.ecc_layout = &sharpslc_akita_oobinfo;
+	} else if (machine_is_borzoi()) {
+		sharpslc_nand_partitions[1].size = 32 * 1024 * 1024;
+		sharpslc_nand_bbt.len = 1;
+		sharpslc_nand_platform_data.ecc_layout = &sharpslc_akita_oobinfo;
+	}
 
-static struct mtd_partition sharpsl_rom_parts[] = {
+	platform_device_register(&sharpslc_nand_device);
+}
+#else
+static inline void sharpslc_nand_init(void) {}
+#endif
+
+/******************************************************************************
+ * NOR Flash
+ ******************************************************************************/
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition sharpslc_rom_parts[] = {
 	{
 		.name	="Boot PROM Filesystem",
 		.offset	= 0x00140000,
@@ -687,158 +820,117 @@ static struct mtd_partition sharpsl_rom_parts[] = {
 	},
 };
 
-static struct physmap_flash_data sharpsl_rom_data = {
+static struct physmap_flash_data sharpslc_rom_data = {
 	.width		= 2,
-	.nr_parts	= ARRAY_SIZE(sharpsl_rom_parts),
-	.parts		= sharpsl_rom_parts,
+	.nr_parts	= ARRAY_SIZE(sharpslc_rom_parts),
+	.parts		= sharpslc_rom_parts,
 };
 
-static struct resource sharpsl_rom_resources[] = {
+static struct resource sharpslc_rom_resources[] = {
 	{
-		.start	= 0x00000000,
-		.end	= 0x007fffff,
+		.start	= PXA_CS0_PHYS,
+		.end	= PXA_CS0_PHYS + SZ_8M - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 
-static struct platform_device sharpsl_rom_device = {
-	.name	= "physmap-flash",
-	.id	= -1,
-	.resource = sharpsl_rom_resources,
-	.num_resources = ARRAY_SIZE(sharpsl_rom_resources),
-	.dev.platform_data = &sharpsl_rom_data,
+static struct platform_device sharpslc_rom_device = {
+	.name		= "physmap-flash",
+	.id		= -1,
+	.resource	= sharpslc_rom_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_rom_resources),
+	.dev		= {
+		.platform_data	= &sharpslc_rom_data,
+	},
 };
 
-static struct platform_device *devices[] __initdata = {
-	&spitzscoop_device,
-	&spitzkbd_device,
-	&spitz_gpio_keys_device,
-	&spitzled_device,
-	&sharpsl_nand_device,
-	&sharpsl_rom_device,
+static void __init sharpslc_nor_init(void)
+{
+	platform_device_register(&sharpslc_rom_device);
+}
+#else
+static inline void sharpslc_nor_init(void) {}
+#endif
+
+/******************************************************************************
+ * GPIO expander
+ ******************************************************************************/
+#if defined(CONFIG_GPIO_PCA953X) || defined(CONFIG_GPIO_PCA953X_MODULE)
+static struct pca953x_platform_data akita_pca953x_pdata = {
+	.gpio_base		= AKITA_IOEXP_GPIO_BASE,
+};
+
+static struct i2c_board_info akita_i2c_devs[] = {
+	{
+		.type		= "max7310",
+		.addr		= 0x18,
+		.platform_data	= &akita_pxa953x_pdata,
+	},
 };
 
-static void spitz_poweroff(void)
+static void __init sharpslc_i2c_init(void)
+{
+	if (machine_is_akita()) {
+		pxa_set_i2c_info(NULL);
+		i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_devs));
+	}
+}
+#else
+static inline void sharpslc_i2c_init(void) {}
+#endif
+
+
+/******************************************************************************
+ * Machine init
+ ******************************************************************************/
+static void sharpslc_poweroff(void)
 {
 	arm_machine_restart('g', NULL);
 }
 
-static void spitz_restart(char mode, const char *cmd)
+static void sharpslc_restart(char mode, const char *cmd)
 {
 	/* Bootloader magic for a reboot */
-	if((MSC0 & 0xffff0000) == 0x7ff00000)
+	if ((MSC0 & 0xffff0000) == 0x7ff00000)
 		MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
 
-	spitz_poweroff();
+	sharpslc_poweroff();
 }
 
-static void __init common_init(void)
+static void __init sharpslc_init(void)
 {
 	init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
-	pm_power_off = spitz_poweroff;
-	arm_pm_restart = spitz_restart;
-
-	if (machine_is_spitz()) {
-		sharpsl_nand_partitions[1].size = 5 * 1024 * 1024;
-	} else if (machine_is_akita()) {
-		sharpsl_nand_partitions[1].size = 58 * 1024 * 1024;
-	} else if (machine_is_borzoi()) {
-		sharpsl_nand_partitions[1].size = 32 * 1024 * 1024;
-	}
+	pm_power_off = sharpslc_poweroff;
+	arm_pm_restart = sharpslc_restart;
 
 	PMCR = 0x00;
 
 	/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
 	PCFR |= PCFR_OPDE;
 
-	pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
+	pxa2xx_mfp_config(ARRAY_AND_SIZE(sharpslc_pin_config));
 
 	pxa_set_ffuart_info(NULL);
 	pxa_set_btuart_info(NULL);
 	pxa_set_stuart_info(NULL);
-
-	spitz_init_spi();
-
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	pxa_set_mci_info(&spitz_mci_platform_data);
-	pxa_set_ohci_info(&spitz_ohci_platform_data);
-	pxa_set_ficp_info(&spitz_ficp_platform_data);
-	set_pxa_fb_info(&spitz_pxafb_info);
-	pxa_set_i2c_info(NULL);
-}
-
-#if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI)
-static struct nand_bbt_descr sharpsl_akita_bbt = {
-	.options = 0,
-	.offs = 4,
-	.len = 1,
-	.pattern = scan_ff_pattern
-};
-
-static struct nand_ecclayout akita_oobinfo = {
-	.eccbytes = 24,
-	.eccpos = {
-		   0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
-		   0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
-		   0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
-	.oobfree = {{0x08, 0x09}}
-};
-#endif
-
-#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
-static void __init spitz_init(void)
-{
-	spitz_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
-
-#ifdef CONFIG_MACH_BORZOI
-	if (machine_is_borzoi()) {
-		sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
-		sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
-	}
-#endif
-
-	platform_scoop_config = &spitz_pcmcia_config;
-
-	common_init();
-
-	platform_device_register(&spitzscoop2_device);
+	pxa27x_set_i2c_power_info(NULL);
+
+	sharpslc_spi_init();
+	sharpslc_scoop_init();
+	sharpslc_mkp_init();
+	sharpslc_keys_init();
+	sharpslc_leds_init();
+	sharpslc_mmc_init();
+	sharpslc_pcmcia_init();
+	sharpslc_irda_init();
+	sharpslc_uhc_init();
+	sharpslc_lcd_init();
+	sharpslc_nor_init();
+	sharpslc_nand_init();
+	sharpslc_i2c_init();
 }
-#endif
-
-#ifdef CONFIG_MACH_AKITA
-/*
- * Akita IO Expander
- */
-static struct pca953x_platform_data akita_ioexp = {
-	.gpio_base		= AKITA_IOEXP_GPIO_BASE,
-};
-
-static struct i2c_board_info akita_i2c_board_info[] = {
-	{
-		.type		= "max7310",
-		.addr		= 0x18,
-		.platform_data	= &akita_ioexp,
-	},
-};
-
-static void __init akita_init(void)
-{
-	spitz_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
-
-	sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
-	sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
-
-	/* We just pretend the second element of the array doesn't exist */
-	spitz_pcmcia_config.num_devs = 1;
-	platform_scoop_config = &spitz_pcmcia_config;
-
-	i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_board_info));
-
-	common_init();
-}
-#endif
 
-static void __init fixup_spitz(struct machine_desc *desc,
+static void __init sharpslc_fixup(struct machine_desc *desc,
 		struct tag *tags, char **cmdline, struct meminfo *mi)
 {
 	sharpsl_save_param();
@@ -852,10 +944,10 @@ static void __init fixup_spitz(struct machine_desc *desc,
 MACHINE_START(SPITZ, "SHARP Spitz")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= spitz_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
@@ -864,10 +956,10 @@ MACHINE_END
 MACHINE_START(BORZOI, "SHARP Borzoi")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= spitz_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
@@ -876,10 +968,10 @@ MACHINE_END
 MACHINE_START(AKITA, "SHARP Akita")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= akita_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
-- 
1.7.1



From olof at lixom.net  Fri Jun 11 09:51:29 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri, 11 Jun 2010 08:51:29 -0500
Subject: [PATCH 01/10] [ARM] tegra: initial tegra support
In-Reply-To: <AANLkTinPJuvApEVRdx5M6Oi88_-avWr_Q63atSOfTruK@mail.gmail.com>
References: <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
	<AANLkTinPJuvApEVRdx5M6Oi88_-avWr_Q63atSOfTruK@mail.gmail.com>
Message-ID: <20100611135129.GA15108@lixom.net>

Hi,

On Tue, Jun 08, 2010 at 01:34:25AM +0200, Linus Walleij wrote:
> 2010/6/4 Olof Johansson <olof at lixom.net>:
> 
> > (...)
> > diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> > index 5bd7c89..b4f6c5e 100644
> > --- a/arch/arm/mm/Kconfig
> > +++ b/arch/arm/mm/Kconfig
> > @@ -760,7 +760,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
> > ?config CACHE_L2X0
> > ? ? ? ?bool "Enable the L2x0 outer cache controller"
> > ? ? ? ?depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
> > - ? ? ? ? ? ? ? ? ?REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4
> > + ? ? ? ? ? ? ? ? ?REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK || ARCH_OMAP4 || ARCH_TEGRA
> 
> What are you actually basing your patches on? You will
> need to bring your patches to the head, there are already
> two more machines using the L2x0 for example, so this
> won't apply.

Yeah, I messed up and accidentally based it on .34 instead of current
-rc at time of posting.

Erik and Colin have rebased properly and folded in the changes from your
other comments. I'll leave it up to them but you should see an email
about it at some point.


-Olof


From eric.y.miao at gmail.com  Fri Jun 11 10:05:46 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 11 Jun 2010 22:05:46 +0800
Subject: [PATCH] pxa/z2: Fix flash layout to final version
In-Reply-To: <1275529810-589-1-git-send-email-marek.vasut@gmail.com>
References: <1275529810-589-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTinntIM_cjQLejn4gyYB34nQJYHZTyc92mk5uh59@mail.gmail.com>

On Thu, Jun 3, 2010 at 9:50 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> This patch fixes flash layout to it's final version. Also, I fixed the
> authorship information of this file as it's been totally reworked since Ken
> released his last version.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Applied to 'fix'.


From eric.y.miao at gmail.com  Fri Jun 11 10:06:21 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 11 Jun 2010 22:06:21 +0800
Subject: [PATCH] pxa/z2: Fix includes in battery driver
In-Reply-To: <1275529440-31121-1-git-send-email-marek.vasut@gmail.com>
References: <1275529440-31121-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTimp51Jn61apE_LLlk8GC_K13yCTJoJdZlNpGHn3@mail.gmail.com>

On Thu, Jun 3, 2010 at 9:44 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Remove redundant includes and add slab.h to fix problem with building.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Applied to 'fix'.


From u.kleine-koenig at pengutronix.de  Fri Jun 11 10:11:41 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 11 Jun 2010 16:11:41 +0200
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100611095839.GC10894@pengutronix.de>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
Message-ID: <20100611141141.GE10894@pengutronix.de>

Hello Lothar,

On Fri, Jun 11, 2010 at 11:58:39AM +0200, Uwe Kleine-K?nig wrote:
> > You are probably talking about the Freescale i.MX51 kernel, that won't
> > even boot, if you enable CONFIG_DEBUG_KERNEL, CONFIG_DEBUG_SPINLOCK,
> > CONFIG_DEBUG_LOCKDEP and CONFIG_DEBUG_SPINLOCK_SLEEP.
> > The mutex in the clock implementation is one of the reasons.
> I will have a look into this later today.
I take this back as this is not a mainline problem.
 
Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From pavel at ucw.cz  Fri Jun 11 10:36:00 2010
From: pavel at ucw.cz (Pavel Machek)
Date: Fri, 11 Jun 2010 16:36:00 +0200
Subject: [PATCH 2/2] pxa/spitz: Rework spitz
In-Reply-To: <201006110852.45838.marek.vasut@gmail.com>
References: <1276238740-10640-1-git-send-email-marek.vasut@gmail.com>
	<1276238740-10640-2-git-send-email-marek.vasut@gmail.com>
	<201006110852.45838.marek.vasut@gmail.com>
Message-ID: <20100611143600.GA1307@ucw.cz>

On Fri 2010-06-11 08:52:45, Marek Vasut wrote:
> Dne P? 11. ?ervna 2010 08:45:40 Marek Vasut napsal(a):
> > This huge patch mostly shuffles code. The spitz.c file contained terrible
> > mess and needed a cleanup, here it is:
> > 
> > 1) Made every part modular, components are not built in if not selected.
> > 2) Removed loads of preprocessor goo, mostly "#ifdef MACH_AKITA ....
> > #endif" and similar code. The kernel size will grow by a few kb now, but
> > the file is much more readable.
> > 3) Reworked SD/CF power setting function and made it reentrant.
> > 
> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> > ---
> >  arch/arm/mach-pxa/include/mach/spitz.h |    2 -
> >  arch/arm/mach-pxa/spitz.c              |  748
> > ++++++++++++++++++-------------- 2 files changed, 420 insertions(+), 330
> > deletions(-)
> > 
> 
> Pavel, Eric, I tested this on metan's Z, could you give it a go ?

quick test on 2.6.35-rc2 (of the 2nd version), and all seems
well. What should I look for?
								Pavel
-- 
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html


From eric.y.miao at gmail.com  Fri Jun 11 10:38:52 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 11 Jun 2010 22:38:52 +0800
Subject: [PATCH 3/3] PalmZ72: Add support for OV9640 camera sensor
In-Reply-To: <201004211411.37371.marek.vasut@gmail.com>
References: <200908220852.06689.marek.vasut@gmail.com>
	<201004211141.22791.marek.vasut@gmail.com> 
	<x2vf17812d71004210444t2083071bj4e9fa7da2f713cda@mail.gmail.com> 
	<201004211411.37371.marek.vasut@gmail.com>
Message-ID: <AANLkTimS2Il7oMsfizddQosf6_qDa0imJ3N-FPhVz8aJ@mail.gmail.com>

On Wed, Apr 21, 2010 at 8:11 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dne St 21. dubna 2010 13:44:34 Eric Miao napsal(a):
>> On Wed, Apr 21, 2010 at 5:41 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
>> > Dne So 22. srpna 2009 08:52:06 Marek Vasut napsal(a):
>> >> From 777212ce6d3bacea76281aa3d74839a3c38b32a4 Mon Sep 17 00:00:00 2001
>> >> From: Marek Vasut <marek.vasut at gmail.com>
>> >> Date: Sat, 22 Aug 2009 05:15:10 +0200
>> >> Subject: [PATCH 3/3] PalmZ72: Add support for OV9640 camera sensor
>> >
>> > Hi, was this ever merged ?
>>
>> Is the required change to ov9640 merged?
>
> Looking at this more properly, this might need a revision. The ov9640 driver is
> in though.

Marek,

How's the status of the revision?


From eric.y.miao at gmail.com  Fri Jun 11 10:44:05 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 11 Jun 2010 22:44:05 +0800
Subject: [PATCH] USB: gadget: pxa2xx: allow -1 for invalid gpio
In-Reply-To: <89D837B3-BCDC-48A4-BBF9-B292AE55D7AB@workware.net.au>
References: <89D837B3-BCDC-48A4-BBF9-B292AE55D7AB@workware.net.au>
Message-ID: <AANLkTin54H3yGMx0aaEo1jJIOo4hWDQ0kQjGpwXzDHnF@mail.gmail.com>

On Wed, Apr 21, 2010 at 2:30 PM, Steve Bennett <steveb at workware.net.au> wrote:
> gpio must be int, not u16, otherwise -1 isn't recognised
> by gpio_is_valid().
>
> Signed-off-by: Steve Bennett <steveb at workware.net.au>

This looks to have missed the last merge window, I'm picking this up
into the pxa tree.


From felipe.contreras at gmail.com  Fri Jun 11 11:17:51 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:17:51 +0300
Subject: [PATCH v3 13/14] omap: mailbox: simplify omap_mbox_register()
In-Reply-To: <20100524.174233.26958915.Hiroshi.DOYU@nokia.com>
References: <1274548465-20208-1-git-send-email-felipe.contreras@gmail.com>
	<1274548465-20208-14-git-send-email-felipe.contreras@gmail.com>
	<20100524.174233.26958915.Hiroshi.DOYU@nokia.com>
Message-ID: <AANLkTinAKOZwGSDsQv5VKXBrr1BSQw-9w5Dcq2Z_96M0@mail.gmail.com>

On Mon, May 24, 2010 at 5:42 PM, Hiroshi DOYU <Hiroshi.DOYU at nokia.com> wrote:
> From: ext Felipe Contreras <felipe.contreras at gmail.com>
> Subject: [PATCH v3 13/14] omap: mailbox: simplify omap_mbox_register()
> Date: Sat, 22 May 2010 19:14:24 +0200
>
>> No need to dynamically register mailboxes one by one.
>
> Can you squash this into [PATCH 10/14]?
>
> I think that the "struct omap_mbox **list" would make more sense
> without those reworking of modifications in this patch.

I don't know, I'm looking at the patch and I think it's much more
difficult to figure out what's happening.

See:

diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index 590ac66..3df1c28 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -142,44 +142,35 @@ struct omap_mbox mbox_dsp_info = {
 	.priv	= &omap1_mbox_dsp_priv,
 };

+struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL };
+
 static int __devinit omap1_mbox_probe(struct platform_device *pdev)
 {
 	struct resource *res;
 	int ret;
+	int i;
+	struct omap_mbox **list;

-	/* MBOX base */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (unlikely(!res)) {
-		dev_err(&pdev->dev, "invalid mem resource\n");
-		return -ENODEV;
-	}
+	list = omap1_mboxes;
+	list[0]->irq = platform_get_irq_byname(pdev, "dsp");

-	mbox_base = ioremap(res->start, resource_size(res));
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mbox_base = ioremap(res[0].start, resource_size(&res[0]));
 	if (!mbox_base)
 		return -ENOMEM;

-	/* DSP IRQ */
-	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (unlikely(!res)) {
-		dev_err(&pdev->dev, "invalid irq resource\n");
-		ret = -ENODEV;
-		goto err_out;
+	ret = omap_mbox_register(&pdev->dev, list);
+	if (ret) {
+		iounmap(mbox_base);
+		return ret;
 	}
-	mbox_dsp_info.irq = res->start;

-	ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
-	if (ret)
-		goto err_out;
 	return 0;
-
-err_out:
-	iounmap(mbox_base);
-	return ret;
 }

 static int __devexit omap1_mbox_remove(struct platform_device *pdev)
 {
-	omap_mbox_unregister(&mbox_dsp_info);
+	omap_mbox_unregister();
 	iounmap(mbox_base);
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 3ff1ad5..f336515 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -307,6 +307,8 @@ struct omap_mbox mbox_dsp_info = {
 	.priv	= &omap2_mbox_dsp_priv,
 };

+struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
+
 #if defined(CONFIG_ARCH_OMAP2420)

 /* IVA */
@@ -331,6 +333,8 @@ static struct omap_mbox mbox_iva_info = {
 	.ops	= &omap2_mbox_ops,
 	.priv	= &omap2_mbox_iva_priv,
 };
+
+struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
 #endif

 /* OMAP4 */
@@ -378,89 +382,56 @@ struct omap_mbox mbox_2_info = {
 	.priv	= &omap2_mbox_2_priv,
 };

+struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
+
 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 {
 	struct resource *res;
 	int ret;
+	struct omap_mbox **list;

-	/* MBOX base */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (unlikely(!res)) {
-		dev_err(&pdev->dev, "invalid mem resource\n");
-		return -ENODEV;
+	if (cpu_is_omap3430()) {
+		list = omap3_mboxes;
+
+		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
 	}
-	mbox_base = ioremap(res->start, resource_size(res));
-	if (!mbox_base)
-		return -ENOMEM;
+#if defined(CONFIG_ARCH_OMAP2420)
+	else if (cpu_is_omap2420()) {
+		list = omap2_mboxes;

-	/* DSP or IVA2 IRQ */
-	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
+		list[1]->irq = platform_get_irq_byname(pdev, "iva");
+	}
+#endif
+	else if (cpu_is_omap44xx()) {
+		list = omap4_mboxes;

-	if (unlikely(!res)) {
-		dev_err(&pdev->dev, "invalid irq resource\n");
-		ret = -ENODEV;
-		goto err_dsp;
+		list[0]->irq = list[1]->irq =
+			platform_get_irq_byname(pdev, "mbox");
 	}
-	if (cpu_is_omap44xx()) {
-		mbox_1_info.irq = res->start;
-		ret = omap_mbox_register(&pdev->dev, &mbox_1_info);
-	} else {
-		mbox_dsp_info.irq = res->start;
-		ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
+	else {
+		pr_err("%s: platform not supported\n", __func__);
+		return -ENODEV;
 	}
-	if (ret)
-		goto err_dsp;

-	if (cpu_is_omap44xx()) {
-		mbox_2_info.irq = res->start;
-		ret = omap_mbox_register(&pdev->dev, &mbox_2_info);
-		if (ret) {
-			omap_mbox_unregister(&mbox_1_info);
-			goto err_dsp;
-		}
-	}
-#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
-	if (cpu_is_omap2420()) {
-		/* IVA IRQ */
-		res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
-		if (unlikely(!res)) {
-			dev_err(&pdev->dev, "invalid irq resource\n");
-			ret = -ENODEV;
-			omap_mbox_unregister(&mbox_dsp_info);
-			goto err_dsp;
-		}
-		mbox_iva_info.irq = res->start;
-		ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
-		if (ret) {
-			omap_mbox_unregister(&mbox_dsp_info);
-			goto err_dsp;
-		}
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mbox_base = ioremap(res[0].start, resource_size(&res[0]));
+	if (!mbox_base)
+		return -ENOMEM;
+
+	ret = omap_mbox_register(&pdev->dev, list);
+	if (ret) {
+		iounmap(mbox_base);
+		return ret;
 	}
-#endif
 	return 0;

-#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
-err_iva1:
-	omap_mbox_unregister(&mbox_dsp_info);
-#endif
-
-err_dsp:
-	iounmap(mbox_base);
 	return ret;
 }

 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
 {
-#if defined(CONFIG_ARCH_OMAP2420)
-	if (cpu_is_omap2420())
-		omap_mbox_unregister(&mbox_iva_info);
-#endif
-
-	if (cpu_is_omap44xx()) {
-		omap_mbox_unregister(&mbox_2_info);
-		omap_mbox_unregister(&mbox_1_info);
-	} else
-		omap_mbox_unregister(&mbox_dsp_info);
+	omap_mbox_unregister();
 	iounmap(mbox_base);
 	return 0;
 }
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h
b/arch/arm/plat-omap/include/plat/mailbox.h
index aad8bf8..c44fde3 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -55,7 +55,6 @@ struct omap_mbox {
 	struct omap_mbox_queue	*txq, *rxq;
 	struct omap_mbox_ops	*ops;
 	struct device		*dev;
-	struct omap_mbox	*next;
 	void			*priv;
 };

@@ -65,8 +64,8 @@ void omap_mbox_init_seq(struct omap_mbox *);
 struct omap_mbox *omap_mbox_get(const char *);
 void omap_mbox_put(struct omap_mbox *);

-int omap_mbox_register(struct device *parent, struct omap_mbox *);
-int omap_mbox_unregister(struct omap_mbox *);
+int omap_mbox_register(struct device *parent, struct omap_mbox **);
+int omap_mbox_unregister(void);

 static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
 {
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 38a6cb1..a8e22e1 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -33,8 +33,7 @@
 #include <plat/mailbox.h>

 static struct workqueue_struct *mboxd;
-static struct omap_mbox *mboxes;
-static DEFINE_SPINLOCK(mboxes_lock);
+static struct omap_mbox **mboxes;
 static bool rq_full;

 static int mbox_configured;
@@ -307,31 +306,20 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
 	}
 }

-static struct omap_mbox **find_mboxes(const char *name)
-{
-	struct omap_mbox **p;
-
-	for (p = &mboxes; *p; p = &(*p)->next) {
-		if (strcmp((*p)->name, name) == 0)
-			break;
-	}
-
-	return p;
-}
-
 struct omap_mbox *omap_mbox_get(const char *name)
 {
 	struct omap_mbox *mbox;
 	int ret;

-	spin_lock(&mboxes_lock);
-	mbox = *(find_mboxes(name));
-	if (mbox == NULL) {
-		spin_unlock(&mboxes_lock);
-		return ERR_PTR(-ENOENT);
-	}
+	if (!mboxes)
+		return ERR_PTR(-EINVAL);

-	spin_unlock(&mboxes_lock);
+	for (mbox = *mboxes; mbox; mbox++)
+		if (!strcmp(mbox->name, name))
+			break;
+
+	if (!mbox)
+		return ERR_PTR(-ENOENT);

 	ret = omap_mbox_startup(mbox);
 	if (ret)
@@ -349,57 +337,44 @@ EXPORT_SYMBOL(omap_mbox_put);

 static struct class omap_mbox_class = { .name = "mbox", };

-int omap_mbox_register(struct device *parent, struct omap_mbox *mbox)
+int omap_mbox_register(struct device *parent, struct omap_mbox **list)
 {
-	int ret = 0;
-	struct omap_mbox **tmp;
+	int ret;
+	int i;

-	if (!mbox)
+	mboxes = list;
+	if (!mboxes)
 		return -EINVAL;
-	if (mbox->next)
-		return -EBUSY;
-
-	mbox->dev = device_create(&omap_mbox_class,
-				  parent, 0, mbox, "%s", mbox->name);
-	if (IS_ERR(mbox->dev))
-		return PTR_ERR(mbox->dev);
-
-	spin_lock(&mboxes_lock);
-	tmp = find_mboxes(mbox->name);
-	if (*tmp) {
-		ret = -EBUSY;
-		spin_unlock(&mboxes_lock);
-		goto err_find;
-	}
-	*tmp = mbox;
-	spin_unlock(&mboxes_lock);

+	for (i = 0; mboxes[i]; i++) {
+		struct omap_mbox *mbox = mboxes[i];
+		mbox->dev = device_create(&omap_mbox_class,
+				parent, 0, mbox, "%s", mbox->name);
+		if (IS_ERR(mbox->dev)) {
+			ret = PTR_ERR(mbox->dev);
+			goto err_out;
+		}
+	}
 	return 0;

-err_find:
+err_out:
+	while (i--)
+		device_unregister(mboxes[i]->dev);
 	return ret;
 }
 EXPORT_SYMBOL(omap_mbox_register);

-int omap_mbox_unregister(struct omap_mbox *mbox)
+int omap_mbox_unregister(void)
 {
-	struct omap_mbox **tmp;
-
-	spin_lock(&mboxes_lock);
-	tmp = &mboxes;
-	while (*tmp) {
-		if (mbox == *tmp) {
-			*tmp = mbox->next;
-			mbox->next = NULL;
-			spin_unlock(&mboxes_lock);
-			device_unregister(mbox->dev);
-			return 0;
-		}
-		tmp = &(*tmp)->next;
-	}
-	spin_unlock(&mboxes_lock);
+	int i;

-	return -EINVAL;
+	if (!mboxes)
+		return -EINVAL;
+
+	for (i = 0; mboxes[i]; i++)
+		device_unregister(mboxes[i]->dev);
+	mboxes = NULL;
+	return 0;
 }
 EXPORT_SYMBOL(omap_mbox_unregister);

-- 
Felipe Contreras


From felipe.contreras at gmail.com  Fri Jun 11 11:19:15 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:19:15 +0300
Subject: [PATCH v3 13/14] omap: mailbox: simplify omap_mbox_register()
In-Reply-To: <AANLkTinAKOZwGSDsQv5VKXBrr1BSQw-9w5Dcq2Z_96M0@mail.gmail.com>
References: <1274548465-20208-1-git-send-email-felipe.contreras@gmail.com>
	<1274548465-20208-14-git-send-email-felipe.contreras@gmail.com>
	<20100524.174233.26958915.Hiroshi.DOYU@nokia.com>
	<AANLkTinAKOZwGSDsQv5VKXBrr1BSQw-9w5Dcq2Z_96M0@mail.gmail.com>
Message-ID: <AANLkTiniZF39voWYAsgb5FNF8Yi59V3NCZFLOBCGFUo-@mail.gmail.com>

On Fri, Jun 11, 2010 at 6:17 PM, Felipe Contreras
<felipe.contreras at gmail.com> wrote:
> On Mon, May 24, 2010 at 5:42 PM, Hiroshi DOYU <Hiroshi.DOYU at nokia.com> wrote:
>> From: ext Felipe Contreras <felipe.contreras at gmail.com>
>> Subject: [PATCH v3 13/14] omap: mailbox: simplify omap_mbox_register()
>> Date: Sat, 22 May 2010 19:14:24 +0200
>>
>>> No need to dynamically register mailboxes one by one.
>>
>> Can you squash this into [PATCH 10/14]?
>>
>> I think that the "struct omap_mbox **list" would make more sense
>> without those reworking of modifications in this patch.
>
> I don't know, I'm looking at the patch and I think it's much more
> difficult to figure out what's happening.

I forgot to mention: what I will do is put one patch after the other.

-- 
Felipe Contreras


From linus.walleij at stericsson.com  Fri Jun 11 11:26:15 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:26:15 +0200
Subject: [PATCH 00/13] PrimeCell DMA API and drivers v6
Message-ID: <1276269975-1191-1-git-send-email-linus.walleij@stericsson.com>

This is the sixth iteration of this patch set for PrimeCell
DMA support, reposting the entire series.

Since Russell want this to run on the Versatile boards, I
have hacked around with Peter Pearse's DMA driver for PL08x
and now it is starting to look usable. Still it doesn't work
with the PB1176 (because the DMA hardware is broken) and not
with the PB11MPCore for anything but memcpy (for unknown
reason slave DMA fails, possibly my stupidity).

I need help to test and try to iron out the final problems
with the RealView+Versatile DMA. The PL08x driver is long
due, it's used in Nomadik and SPEAr as well, with more
platforms waiting in the perimeter.

This entire series should probably be considered RFC even
though everything is well tested on U300 and U8500, since
the Versatile implementation gatekeeps the others.

Yours,
Linus Walleij


From linus.walleij at stericsson.com  Fri Jun 11 11:26:29 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:26:29 +0200
Subject: [PATCH 01/13] ARM: define the PrimeCell DMA API v6
Message-ID: <1276269989-1323-1-git-send-email-linus.walleij@stericsson.com>

This patch extends the DMA engine with a PrimeCell runtime
reconfigure command to configure the DMA channel. This has been
identified as the basic extension needed to drive DMA on top of
the PL011, PL022 and PL180 PrimeCells.

Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
Acked-by: Dan Williams <dan.j.williams at intel.com>
---
 include/linux/amba/dma.h  |   44 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/dmaengine.h |    5 +++++
 2 files changed, 49 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/amba/dma.h

diff --git a/include/linux/amba/dma.h b/include/linux/amba/dma.h
new file mode 100644
index 0000000..0a5825d
--- /dev/null
+++ b/include/linux/amba/dma.h
@@ -0,0 +1,44 @@
+/*
+ *  linux/include/amba/dma.h
+ *
+ *  Copyright (C) 2010 ST-Ericsson AB
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#if !defined(AMBA_DMA_H) && defined(CONFIG_DMADEVICES)
+#define AMBA_DMA_H
+
+#include <linux/dma-mapping.h>
+
+/**
+ * struct amba_dma_channel_config - dmaengine config for PrimeCells
+ * @addr: this is the physical address where DMA data should be
+ * read (RX) or written (TX)
+ * @addr_width: this is the width of the source (RX) or target
+ * (TX) register where DMA data shall be read/written, in bytes.
+ * legal values: 1, 2, 4, 8.
+ * @direction: whether the data goes in or out on this channel,
+ * right now.
+ * @maxburst: the maximum number of words (note: words, not bytes)
+ * that can be sent in one burst to the device. Typically something
+ * like half the FIFO depth on I/O peripherals so you don't
+ * overflow it.
+ *
+ * This struct is passed in as configuration data to a DMA engine
+ * in order to set up a certain channel for PrimeCell DMA transport.
+ * Anything the DMA engine needs to know about the PrimeCell shall
+ * be passed through this struct. The DMA engine has to provide an
+ * additional command in the channel config interface, DMA_CONFIG_AMBA
+ * and this struct will then be passed in as an argument to the
+ * DMA engine device_control() function.
+ */
+struct amba_dma_channel_config {
+	dma_addr_t addr;
+	u8 addr_width:4;
+	enum dma_data_direction direction;
+	int maxburst;
+};
+
+#endif /* AMBA_DMA_H */
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index 5204f01..c309f3e 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -114,11 +114,16 @@ enum dma_ctrl_flags {
  * @DMA_TERMINATE_ALL: terminate all ongoing transfers
  * @DMA_PAUSE: pause ongoing transfers
  * @DMA_RESUME: resume paused transfer
+ * @DMA_CONFIG_AMBA: this command is only implemented by DMA controllers
+ * that need to runtime reconfigure the channel for use with ARM
+ * PrimeCell slaves. An additional argument must be passed in with this
+ * command. (See further <linux/amba/dma.h>)
  */
 enum dma_ctrl_cmd {
 	DMA_TERMINATE_ALL,
 	DMA_PAUSE,
 	DMA_RESUME,
+	DMA_CONFIG_AMBA,
 };
 
 /**
-- 
1.6.3.3



From linus.walleij at stericsson.com  Fri Jun 11 11:26:46 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:26:46 +0200
Subject: [PATCH 03/13] DMAENGINE: add generic PrimeCell interface to DMA40 v2
Message-ID: <1276270006-1431-1-git-send-email-linus.walleij@stericsson.com>

This extends the DMA engine driver for the DMA40 used in the
U8500 platform with the generic PrimeCell interface.

Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 drivers/dma/ste_dma40.c |  125 +++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 121 insertions(+), 4 deletions(-)

diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index c426829..c1b278f 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -14,6 +14,7 @@
 #include <linux/platform_device.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
+#include <linux/amba/dma.h>
 
 #include <plat/ste_dma40.h>
 
@@ -205,6 +206,9 @@ struct d40_chan {
 	struct d40_def_lcsp		 log_def;
 	struct d40_lcla_elem		 lcla;
 	struct d40_log_lli_full		*lcpa;
+	/* AMBA extensions */
+	dma_addr_t			amba_addr;
+	enum dma_data_direction		amba_direction;
 };
 
 /**
@@ -1890,7 +1894,10 @@ static int d40_prep_slave_sg_log(struct d40_desc *d40d,
 			lli_max = 1;
 
 	if (direction == DMA_FROM_DEVICE) {
-		dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
+		if (d40c->amba_addr)
+			dev_addr = d40c->amba_addr;
+		else
+			dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
 		total_size = d40_log_sg_to_dev(&d40c->lcla,
 					       sgl, sg_len,
 					       &d40d->lli_log,
@@ -1902,7 +1909,10 @@ static int d40_prep_slave_sg_log(struct d40_desc *d40d,
 					       dev_addr, lli_max,
 					       d40c->base->plat_data->llis_per_log);
 	} else if (direction == DMA_TO_DEVICE) {
-		dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
+		if (d40c->amba_addr)
+			dev_addr = d40c->amba_addr;
+		else
+			dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
 		total_size = d40_log_sg_to_dev(&d40c->lcla,
 					       sgl, sg_len,
 					       &d40d->lli_log,
@@ -1943,9 +1953,15 @@ static int d40_prep_slave_sg_phy(struct d40_desc *d40d,
 
 	if (direction == DMA_FROM_DEVICE) {
 		dst_dev_addr = 0;
-		src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
+		if (d40c->amba_addr)
+			src_dev_addr = d40c->amba_addr;
+		else
+			src_dev_addr = d40c->base->plat_data->dev_rx[d40c->dma_cfg.src_dev_type];
 	} else if (direction == DMA_TO_DEVICE) {
-		dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
+		if (d40c->amba_addr)
+			dst_dev_addr = d40c->amba_addr;
+		else
+			dst_dev_addr = d40c->base->plat_data->dev_tx[d40c->dma_cfg.dst_dev_type];
 		src_dev_addr = 0;
 	} else
 		return -EINVAL;
@@ -2065,6 +2081,103 @@ static void d40_issue_pending(struct dma_chan *chan)
 	spin_unlock_irqrestore(&d40c->lock, flags);
 }
 
+/* PrimeCell DMA extension */
+static void d40_set_ambaconfig(struct dma_chan *chan,
+			       struct amba_dma_channel_config *config)
+{
+	struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
+	struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
+	enum stedma40_periph_data_width addr_width;
+	int psize;
+
+	switch (config->addr_width) {
+	case 1:
+		addr_width = STEDMA40_BYTE_WIDTH;
+		break;
+	case 2:
+		addr_width = STEDMA40_HALFWORD_WIDTH;
+		break;
+	case 4:
+		addr_width = STEDMA40_WORD_WIDTH;
+		break;
+	case 8:
+		addr_width = STEDMA40_DOUBLEWORD_WIDTH;
+		break;
+	default:
+		dev_err(d40c->base->dev,
+			"illegal peripheral address width requested (%d)\n",
+			config->addr_width);
+		return;
+	}
+
+	if (config->maxburst >= 16)
+		psize = STEDMA40_PSIZE_LOG_16;
+	else if (config->maxburst >= 8)
+		psize = STEDMA40_PSIZE_LOG_8;
+	else if (config->maxburst >= 4)
+		psize = STEDMA40_PSIZE_LOG_4;
+	else
+		psize = STEDMA40_PSIZE_LOG_1;
+
+	if (config->direction == DMA_FROM_DEVICE) {
+		dma_addr_t dev_addr_rx =
+			d40c->base->plat_data->dev_rx[cfg->src_dev_type];
+
+		if (dev_addr_rx)
+			dev_warn(d40c->base->dev,
+				 "channel has a pre-wired RX address %08x "
+				 "overriding with %08x\n",
+				 dev_addr_rx, config->addr);
+		if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
+			dev_warn(d40c->base->dev,
+				 "channel was not configured for peripheral "
+				 "to memory transfer (%d) overriding\n",
+				 cfg->dir);
+		cfg->dir = STEDMA40_PERIPH_TO_MEM;
+	} else if (config->direction == DMA_TO_DEVICE) {
+		dma_addr_t dev_addr_tx =
+			d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
+
+		if (dev_addr_tx)
+			dev_warn(d40c->base->dev,
+				 "channel has a pre-wired TX address %08x "
+				 "overriding with %08x\n",
+				 dev_addr_tx, config->addr);
+		if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
+			dev_warn(d40c->base->dev,
+				 "channel was not configured for memory "
+				 "to peripheral transfer (%d) overriding\n",
+				 cfg->dir);
+		cfg->dir = STEDMA40_MEM_TO_PERIPH;
+	} else {
+		dev_err(d40c->base->dev,
+			"unrecognized channel direction %d\n",
+			config->direction);
+		return;
+	}
+
+	/* Set up all the endpoint configs */
+	cfg->src_info.data_width = addr_width;
+	cfg->src_info.psize = psize;
+	cfg->src_info.endianess = STEDMA40_LITTLE_ENDIAN;
+	cfg->src_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
+	cfg->dst_info.data_width = addr_width;
+	cfg->dst_info.psize = psize;
+	cfg->dst_info.endianess = STEDMA40_LITTLE_ENDIAN;
+	cfg->dst_info.flow_ctrl = STEDMA40_NO_FLOW_CTRL;
+
+	/* These settings will take precedence later */
+	d40c->amba_addr = config->addr;
+	d40c->amba_direction = config->direction;
+	dev_dbg(d40c->base->dev,
+		"configured channel %s for %s, data width %d, "
+		"maxburst %d bytes, LE, no flow control\n",
+		dma_chan_name(chan),
+		(config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
+		config->addr_width,
+		config->maxburst);
+}
+
 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		       unsigned long arg)
 {
@@ -2081,6 +2194,10 @@ static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		return d40_pause(chan);
 	case DMA_RESUME:
 		return d40_resume(chan);
+	case DMA_CONFIG_AMBA:
+		d40_set_ambaconfig(chan,
+			(struct amba_dma_channel_config *) arg);
+		return 0;
 	}
 
 	/* Other commands are unimplemented */
-- 
1.6.3.3



From linus.walleij at stericsson.com  Fri Jun 11 11:26:54 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:26:54 +0200
Subject: [PATCH 04/13] DMAENGINE: ste_dma40: config checks
Message-ID: <1276270014-1498-1-git-send-email-linus.walleij@stericsson.com>

From: Jonas Aaberg <jonas.aberg at stericsson.com>

Added various configuration checks.

Signed-off-by: Jonas Aaberg <jonas.aberg at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/plat-nomadik/include/plat/ste_dma40.h |    2 +-
 drivers/dma/ste_dma40.c                        |   29 ++++++++++++++++++++++-
 2 files changed, 28 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-nomadik/include/plat/ste_dma40.h b/arch/arm/plat-nomadik/include/plat/ste_dma40.h
index 4d12ea4..fdc1306 100644
--- a/arch/arm/plat-nomadik/include/plat/ste_dma40.h
+++ b/arch/arm/plat-nomadik/include/plat/ste_dma40.h
@@ -98,7 +98,7 @@ struct stedma40_half_channel_info {
 };
 
 enum stedma40_xfer_dir {
-	STEDMA40_MEM_TO_MEM,
+	STEDMA40_MEM_TO_MEM = 1,
 	STEDMA40_MEM_TO_PERIPH,
 	STEDMA40_PERIPH_TO_MEM,
 	STEDMA40_PERIPH_TO_PERIPH
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index c1b278f..b4ff2b1 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1000,14 +1000,39 @@ static int d40_validate_conf(struct d40_chan *d40c,
 	bool is_log = (conf->channel_type & STEDMA40_CHANNEL_IN_OPER_MODE)
 		== STEDMA40_CHANNEL_IN_LOG_MODE;
 
-	if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH &&
+	if (!conf->dir) {
+		dev_err(&d40c->chan.dev->device, "[%s] Invalid direction.\n",
+			__func__);
+		res = -EINVAL;
+	}
+
+	if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
+	    d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
+	    d40c->amba_addr == 0) {
+
+		dev_err(&d40c->chan.dev->device,
+			"[%s] Invalid TX channel address (%d)\n",
+			__func__, conf->dst_dev_type);
+		res = -EINVAL;
+	}
+
+	if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
+	    d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
+	    d40c->amba_addr == 0) {
+		dev_err(&d40c->chan.dev->device,
+			"[%s] Invalid RX channel address (%d)\n",
+			__func__, conf->src_dev_type);
+		res = -EINVAL;
+	}
+
+	if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
 	    dst_event_group == STEDMA40_DEV_DST_MEMORY) {
 		dev_err(&d40c->chan.dev->device, "[%s] Invalid dst\n",
 			__func__);
 		res = -EINVAL;
 	}
 
-	if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM &&
+	if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
 	    src_event_group == STEDMA40_DEV_SRC_MEMORY) {
 		dev_err(&d40c->chan.dev->device, "[%s] Invalid src\n",
 			__func__);
-- 
1.6.3.3



From linus.walleij at stericsson.com  Fri Jun 11 11:26:37 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:26:37 +0200
Subject: [PATCH 02/13] DMAENGINE: add generic PrimeCell interface to COH 901
	318 v7
Message-ID: <1276269997-1375-1-git-send-email-linus.walleij@stericsson.com>

This extends the DMA engine driver for the COH 901 318 used in the
U300 platform with the generic PrimeCell interface.

Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 drivers/dma/coh901318.c |  154 +++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 154 insertions(+), 0 deletions(-)

diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index a724e6b..6b21069 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -21,6 +21,7 @@
 #include <linux/uaccess.h>
 #include <linux/debugfs.h>
 #include <mach/coh901318.h>
+#include <linux/amba/dma.h>
 
 #include "coh901318_lli.h"
 
@@ -72,6 +73,9 @@ struct coh901318_chan {
 	unsigned long nbr_active_done;
 	unsigned long busy;
 
+	u32 amba_addr;
+	u32 amba_ctrl;
+
 	struct coh901318_base *base;
 };
 
@@ -190,6 +194,9 @@ static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
 static inline dma_addr_t
 cohc_dev_addr(struct coh901318_chan *cohc)
 {
+	/* PrimeCell supplied address will take precedence */
+	if (cohc->amba_addr)
+		return cohc->amba_addr;
 	return cohc->base->platform->chan_conf[cohc->id].dev_addr;
 }
 
@@ -1055,6 +1062,14 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 
 	params = cohc_chan_param(cohc);
 	config = params->config;
+	/*
+	 * Add primecell-specific control on top, make
+	 * sure the bits you set per peripheral channel are
+	 * cleared in the default config from the platform.
+	 */
+	ctrl_chained |= cohc->amba_ctrl;
+	ctrl_last |= cohc->amba_ctrl;
+	ctrl |= cohc->amba_ctrl;
 
 	if (direction == DMA_TO_DEVICE) {
 		u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
@@ -1113,6 +1128,12 @@ coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
 	if (ret)
 		goto err_lli_fill;
 
+	/*
+	 * Set the default ctrl for the channel to the one from the lli,
+	 * things may have changed due to odd buffer alignment etc.
+	 */
+	coh901318_set_ctrl(cohc, lli->control);
+
 	COH_DBG(coh901318_list_print(cohc, lli));
 
 	/* Pick a descriptor to handle this transfer */
@@ -1175,6 +1196,130 @@ coh901318_issue_pending(struct dma_chan *chan)
 	spin_unlock_irqrestore(&cohc->lock, flags);
 }
 
+/*
+ * Here we wrap in the PrimeCell dma interface
+ */
+struct burst_table {
+	int burst_8bit;
+	int burst_16bit;
+	int burst_32bit;
+	u32 reg;
+};
+
+static const struct burst_table burst_sizes[] = {
+	{
+		.burst_8bit = 64,
+		.burst_16bit = 32,
+		.burst_32bit = 16,
+		.reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
+	},
+	{
+		.burst_8bit = 48,
+		.burst_16bit = 24,
+		.burst_32bit = 12,
+		.reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
+	},
+	{
+		.burst_8bit = 32,
+		.burst_16bit = 16,
+		.burst_32bit = 8,
+		.reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
+	},
+	{
+		.burst_8bit = 16,
+		.burst_16bit = 8,
+		.burst_32bit = 4,
+		.reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
+	},
+	{
+		.burst_8bit = 8,
+		.burst_16bit = 4,
+		.burst_32bit = 2,
+		.reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
+	},
+	{
+		.burst_8bit = 4,
+		.burst_16bit = 2,
+		.burst_32bit = 1,
+		.reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
+	},
+	{
+		.burst_8bit = 2,
+		.burst_16bit = 1,
+		.burst_32bit = 0,
+		.reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
+	},
+	{
+		.burst_8bit = 1,
+		.burst_16bit = 0,
+		.burst_32bit = 0,
+		.reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
+	},
+};
+
+static void coh901318_dma_set_ambaconfig(struct dma_chan *chan,
+			struct amba_dma_channel_config *config)
+{
+	struct coh901318_chan *cohc = to_coh901318_chan(chan);
+	int maxburst = config->maxburst;
+	u32 amba_ctrl = 0;
+	int i = 0;
+
+	dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
+		config->addr_width);
+	switch (config->addr_width)  {
+	case 1:
+		amba_ctrl |=
+			COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
+			COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
+
+		while (i < ARRAY_SIZE(burst_sizes)) {
+			if (burst_sizes[i].burst_8bit <= maxburst)
+				break;
+			i++;
+		}
+
+		break;
+	case 2:
+		amba_ctrl |=
+			COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
+			COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
+
+		while (i < ARRAY_SIZE(burst_sizes)) {
+			if (burst_sizes[i].burst_16bit <= maxburst)
+				break;
+			i++;
+		}
+
+		break;
+	case 4:
+		/* Direction doesn't matter here, it's 32/32 bits */
+		amba_ctrl |=
+			COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
+			COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
+
+		while (i < ARRAY_SIZE(burst_sizes)) {
+			if (burst_sizes[i].burst_32bit <= maxburst)
+				break;
+			i++;
+		}
+
+		break;
+	default:
+		dev_err(COHC_2_DEV(cohc),
+			"bad ambaconfig: alien address width\n");
+		return;
+	}
+
+	amba_ctrl |= burst_sizes[i].reg;
+	dev_dbg(COHC_2_DEV(cohc),
+		"selected burst size %d bytes for address width %d bytes, maxburst %d\n",
+		burst_sizes[i].burst_8bit, config->addr_width, maxburst);
+
+	cohc->amba_addr = config->addr;
+	cohc->amba_ctrl = amba_ctrl;
+}
+
 static int
 coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 		  unsigned long arg)
@@ -1184,6 +1329,14 @@ coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 	struct coh901318_desc *cohd;
 	void __iomem *virtbase = cohc->base->virtbase;
 
+	if (cmd == DMA_CONFIG_AMBA) {
+		struct amba_dma_channel_config *config =
+			(struct amba_dma_channel_config *) arg;
+
+		coh901318_dma_set_ambaconfig(chan, config);
+		return 0;
+	  }
+
 	if (cmd == DMA_PAUSE) {
 		coh901318_pause(chan);
 		return 0;
@@ -1240,6 +1393,7 @@ coh901318_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
 
 	return 0;
 }
+
 void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
 			 struct coh901318_base *base)
 {
-- 
1.6.3.3



From linus.walleij at stericsson.com  Fri Jun 11 11:27:21 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:27:21 +0200
Subject: [PATCH 07/13] ARM: add PrimeCell generic DMA to PL022 v8
Message-ID: <1276270041-1662-1-git-send-email-linus.walleij@stericsson.com>

This extends the PL022 SSP/SPI driver with generic DMA engine
support using the PrimeCell DMA engine interface. Also fix up the
test code for the U300 platform.

Acked-by: Grant Likely <grant.likely at secretlab.ca>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/mach-u300/dummyspichip.c |    1 +
 drivers/spi/amba-pl022.c          |  530 ++++++++++++++++++++++++++++++-------
 include/linux/amba/pl022.h        |    6 +
 3 files changed, 446 insertions(+), 91 deletions(-)

diff --git a/arch/arm/mach-u300/dummyspichip.c b/arch/arm/mach-u300/dummyspichip.c
index 5f55012..5672189 100644
--- a/arch/arm/mach-u300/dummyspichip.c
+++ b/arch/arm/mach-u300/dummyspichip.c
@@ -268,6 +268,7 @@ static struct spi_driver pl022_dummy_driver = {
 	.driver = {
 		.name	= "spi-dummy",
 		.owner	= THIS_MODULE,
+		.bus = &spi_bus_type,
 	},
 	.probe	= pl022_dummy_probe,
 	.remove	= __devexit_p(pl022_dummy_remove),
diff --git a/drivers/spi/amba-pl022.c b/drivers/spi/amba-pl022.c
index f0a1418..109c968 100644
--- a/drivers/spi/amba-pl022.c
+++ b/drivers/spi/amba-pl022.c
@@ -27,7 +27,6 @@
 /*
  * TODO:
  * - add timeout on polled transfers
- * - add generic DMA framework support
  */
 
 #include <linux/init.h>
@@ -45,6 +44,10 @@
 #include <linux/amba/pl022.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/scatterlist.h>
+#include <linux/amba/dma.h>
 
 /*
  * This macro is used to define some register default values.
@@ -381,6 +384,14 @@ struct pl022 {
 	enum ssp_reading		read;
 	enum ssp_writing		write;
 	u32				exp_fifo_level;
+	/* DMA settings */
+#ifdef CONFIG_DMADEVICES
+	struct dma_chan			*dma_rx_channel;
+	struct dma_chan			*dma_tx_channel;
+	struct sg_table			sgt_rx;
+	struct sg_table			sgt_tx;
+	char				*dummypage;
+#endif
 };
 
 /**
@@ -406,7 +417,7 @@ struct chip_data {
 	u16 dmacr;
 	u16 cpsr;
 	u8 n_bytes;
-	u8 enable_dma:1;
+	bool enable_dma;
 	enum ssp_reading read;
 	enum ssp_writing write;
 	void (*cs_control) (u32 command);
@@ -762,6 +773,378 @@ static void *next_transfer(struct pl022 *pl022)
 	}
 	return STATE_DONE;
 }
+
+/*
+ * This DMA functionality is only compiled in if we have
+ * access to the generic DMA devices/DMA engine.
+ */
+#ifdef CONFIG_DMADEVICES
+static void unmap_free_dma_scatter(struct pl022 *pl022)
+{
+	/* Unmap and free the SG tables */
+	dma_unmap_sg(&pl022->adev->dev, pl022->sgt_tx.sgl,
+		     pl022->sgt_tx.nents, DMA_TO_DEVICE);
+	dma_unmap_sg(&pl022->adev->dev, pl022->sgt_rx.sgl,
+		     pl022->sgt_rx.nents, DMA_FROM_DEVICE);
+	sg_free_table(&pl022->sgt_rx);
+	sg_free_table(&pl022->sgt_tx);
+}
+
+static void dma_callback(void *data)
+{
+	struct pl022 *pl022 = data;
+	struct spi_message *msg = pl022->cur_msg;
+
+	/* Sync in RX buffer to CPU */
+	BUG_ON(!pl022->sgt_rx.sgl);
+	dma_sync_sg_for_cpu(&pl022->adev->dev,
+			    pl022->sgt_rx.sgl,
+			    pl022->sgt_rx.nents,
+			    DMA_FROM_DEVICE);
+
+#ifdef VERBOSE_DEBUG
+	/*
+	 * Optionally dump out buffers to inspect contents, this is
+	 * good if you want to convince yourself that the loopback
+	 * read/write contents are the same, when adopting to a new
+	 * DMA engine.
+	 */
+	{
+		struct scatterlist *sg;
+		unsigned int i;
+
+		for_each_sg(pl022->sgt_rx.sgl, sg, pl022->sgt_rx.nents, i) {
+			dev_dbg(&pl022->adev->dev, "SPI RX SG ENTRY: %d", i);
+			print_hex_dump(KERN_ERR, "SPI RX: ",
+				       DUMP_PREFIX_OFFSET,
+				       16,
+				       1,
+				       sg_virt(sg),
+				       sg_dma_len(sg),
+				       1);
+		}
+		for_each_sg(pl022->sgt_tx.sgl, sg, pl022->sgt_tx.nents, i) {
+			dev_dbg(&pl022->adev->dev, "SPI TX SG ENTRY: %d", i);
+			print_hex_dump(KERN_ERR, "SPI TX: ",
+				       DUMP_PREFIX_OFFSET,
+				       16,
+				       1,
+				       sg_virt(sg),
+				       sg_dma_len(sg),
+				       1);
+		}
+	}
+#endif
+
+	unmap_free_dma_scatter(pl022);
+
+	/* Update total bytes transfered */
+	msg->actual_length += pl022->cur_transfer->len;
+	if (pl022->cur_transfer->cs_change)
+		pl022->cur_chip->
+			cs_control(SSP_CHIP_DESELECT);
+
+	/* Move to next transfer */
+	msg->state = next_transfer(pl022);
+	tasklet_schedule(&pl022->pump_transfers);
+}
+
+static void setup_dma_scatter(struct pl022 *pl022,
+			      void *buffer,
+			      unsigned int length,
+			      struct sg_table *sgtab)
+{
+	struct scatterlist *sg;
+	int bytesleft = length;
+	void *bufp = buffer;
+	int mapbytes;
+	int i;
+
+	if (buffer) {
+		for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
+			/*
+			 * If there are less bytes left than what fits
+			 * in the current page (plus page alignment offset)
+			 * we just feed in this, else we stuff in as much
+			 * as we can.
+			 */
+			if (bytesleft < (PAGE_SIZE - offset_in_page(bufp)))
+				mapbytes = bytesleft;
+			else
+				mapbytes = PAGE_SIZE - offset_in_page(bufp);
+			sg_set_page(sg, virt_to_page(bufp),
+				    mapbytes, offset_in_page(bufp));
+			bufp += mapbytes;
+			bytesleft -= mapbytes;
+			dev_dbg(&pl022->adev->dev,
+				"set RX/TX target page @ %p, %d bytes, %d left\n",
+				bufp, mapbytes, bytesleft);
+		}
+	} else {
+		/* Map the dummy buffer on every page */
+		for_each_sg(sgtab->sgl, sg, sgtab->nents, i) {
+			if (bytesleft < PAGE_SIZE)
+				mapbytes = bytesleft;
+			else
+				mapbytes = PAGE_SIZE;
+			sg_set_page(sg, virt_to_page(pl022->dummypage),
+				    mapbytes, 0);
+			bytesleft -= mapbytes;
+			dev_dbg(&pl022->adev->dev,
+				"set RX/TX to dummy page %d bytes, %d left\n",
+				mapbytes, bytesleft);
+
+		}
+	}
+	BUG_ON(bytesleft);
+}
+
+/**
+ * configure_dma - configures the channels for the next transfer
+ * @data: SSP driver's private data structure
+ *
+ */
+static int configure_dma(struct pl022 *pl022)
+{
+	struct amba_dma_channel_config rx_conf = {
+		.addr = SSP_DR(pl022->phybase),
+		.direction = DMA_FROM_DEVICE,
+		.maxburst = pl022->vendor->fifodepth >> 1,
+	};
+	struct amba_dma_channel_config tx_conf = {
+		.addr = SSP_DR(pl022->phybase),
+		.direction = DMA_TO_DEVICE,
+		.maxburst = pl022->vendor->fifodepth >> 1,
+	};
+	unsigned int pages;
+	int ret;
+	int sglen;
+	struct dma_chan *rxchan = pl022->dma_rx_channel;
+	struct dma_chan *txchan = pl022->dma_tx_channel;
+	struct dma_async_tx_descriptor *rxdesc;
+	struct dma_async_tx_descriptor *txdesc;
+	dma_cookie_t cookie;
+
+	/* Check that the channels are available */
+	if (!rxchan || !txchan)
+		return -ENODEV;
+
+	switch (pl022->read) {
+	case READING_NULL:
+		/* Use the same as for writing */
+		rx_conf.addr_width = 0;
+		break;
+	case READING_U8:
+		rx_conf.addr_width = 1;
+		break;
+	case READING_U16:
+		rx_conf.addr_width = 2;
+		break;
+	case READING_U32:
+		rx_conf.addr_width = 4;
+		break;
+	}
+
+	switch (pl022->write) {
+	case WRITING_NULL:
+		/* Use the same as for reading */
+		tx_conf.addr_width = 0;
+		break;
+	case WRITING_U8:
+		tx_conf.addr_width = 1;
+		break;
+	case WRITING_U16:
+		tx_conf.addr_width = 2;
+		break;
+	case WRITING_U32:
+		tx_conf.addr_width = 4;
+		break;
+	}
+
+	/* SPI pecularity: we need to read and write the same width */
+	if (rx_conf.addr_width == 0)
+		rx_conf.addr_width = tx_conf.addr_width;
+	if (tx_conf.addr_width == 0)
+		tx_conf.addr_width = rx_conf.addr_width;
+	BUG_ON(rx_conf.addr_width != tx_conf.addr_width);
+
+	rxchan->device->device_control(rxchan, DMA_CONFIG_AMBA,
+				       (unsigned long) &rx_conf);
+	txchan->device->device_control(txchan, DMA_CONFIG_AMBA,
+				       (unsigned long) &tx_conf);
+
+	/* Create sglists for the transfers */
+	pages = (pl022->cur_transfer->len >> PAGE_SHIFT) + 1;
+	dev_dbg(&pl022->adev->dev, "using %d pages for transfer\n", pages);
+
+	ret = sg_alloc_table(&pl022->sgt_rx, pages, GFP_KERNEL);
+	if (ret)
+		goto err_alloc_rx_sg;
+
+	ret = sg_alloc_table(&pl022->sgt_tx, pages, GFP_KERNEL);
+	if (ret)
+		goto err_alloc_tx_sg;
+
+	/* Fill in the scatterlists for the RX+TX buffers */
+	setup_dma_scatter(pl022, pl022->rx,
+			  pl022->cur_transfer->len, &pl022->sgt_rx);
+	setup_dma_scatter(pl022, pl022->tx,
+			  pl022->cur_transfer->len, &pl022->sgt_tx);
+
+	/* Map DMA buffers */
+	sglen = dma_map_sg(&pl022->adev->dev, pl022->sgt_rx.sgl,
+			   pl022->sgt_rx.nents, DMA_FROM_DEVICE);
+	if (sglen != pages)
+		goto err_rx_sgmap;
+
+	sglen = dma_map_sg(&pl022->adev->dev, pl022->sgt_tx.sgl,
+			   pl022->sgt_tx.nents, DMA_TO_DEVICE);
+	if (sglen != pages)
+		goto err_tx_sgmap;
+
+	/* Synchronize the TX scatterlist, invalidate buffers, caches etc */
+	dma_sync_sg_for_device(&pl022->adev->dev,
+			       pl022->sgt_tx.sgl,
+			       pl022->sgt_tx.nents,
+			       DMA_TO_DEVICE);
+
+	/* Send both scatterlists */
+	rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
+				      pl022->sgt_rx.sgl,
+				      pl022->sgt_rx.nents,
+				      DMA_FROM_DEVICE,
+				      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	if (!rxdesc)
+		goto err_rxdesc;
+
+	txdesc = txchan->device->device_prep_slave_sg(txchan,
+				      pl022->sgt_tx.sgl,
+				      pl022->sgt_tx.nents,
+				      DMA_TO_DEVICE,
+				      DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	if (!txdesc)
+		goto err_txdesc;
+
+	/* Put the callback on the RX transfer only, that should finish last */
+	rxdesc->callback = dma_callback;
+	rxdesc->callback_param = pl022;
+
+	/* Submit and fire RX and TX with TX last so we're ready to read! */
+	cookie = rxdesc->tx_submit(rxdesc);
+	if (dma_submit_error(cookie))
+		goto err_submit_rx;
+	cookie = txdesc->tx_submit(txdesc);
+	if (dma_submit_error(cookie))
+		goto err_submit_tx;
+	rxchan->device->device_issue_pending(rxchan);
+	txchan->device->device_issue_pending(txchan);
+
+	return 0;
+
+err_submit_tx:
+err_submit_rx:
+err_txdesc:
+	txchan->device->device_control(txchan, DMA_TERMINATE_ALL, 0);
+err_rxdesc:
+	rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0);
+	dma_unmap_sg(&pl022->adev->dev, pl022->sgt_tx.sgl,
+		     pl022->sgt_tx.nents, DMA_TO_DEVICE);
+err_tx_sgmap:
+	dma_unmap_sg(&pl022->adev->dev, pl022->sgt_rx.sgl,
+		     pl022->sgt_tx.nents, DMA_FROM_DEVICE);
+err_rx_sgmap:
+	sg_free_table(&pl022->sgt_tx);
+err_alloc_tx_sg:
+	sg_free_table(&pl022->sgt_rx);
+err_alloc_rx_sg:
+	return -ENOMEM;
+}
+
+static int __init pl022_dma_probe(struct pl022 *pl022)
+{
+	dma_cap_mask_t mask;
+
+	/* Try to acquire a generic DMA engine slave channel */
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+	/*
+	 * We need both RX and TX channels to do DMA, else do none
+	 * of them.
+	 */
+	pl022->dma_rx_channel = dma_request_channel(mask,
+					    pl022->master_info->dma_filter,
+					    pl022->master_info->dma_rx_param);
+	if (!pl022->dma_rx_channel) {
+		dev_err(&pl022->adev->dev, "no RX DMA channel!\n");
+		goto err_no_rxchan;
+	}
+
+	pl022->dma_tx_channel = dma_request_channel(mask,
+					    pl022->master_info->dma_filter,
+					    pl022->master_info->dma_tx_param);
+	if (!pl022->dma_tx_channel) {
+		dev_err(&pl022->adev->dev, "no TX DMA channel!\n");
+		goto err_no_txchan;
+	}
+
+	pl022->dummypage = kmalloc(PAGE_SIZE, GFP_KERNEL);
+	if (!pl022->dummypage) {
+		dev_err(&pl022->adev->dev, "no DMA dummypage!\n");
+		goto err_no_dummypage;
+	}
+
+	dev_info(&pl022->adev->dev, "setup for DMA on RX %s, TX %s\n",
+		 dma_chan_name(pl022->dma_rx_channel),
+		 dma_chan_name(pl022->dma_tx_channel));
+
+	return 0;
+
+err_no_dummypage:
+	dma_release_channel(pl022->dma_tx_channel);
+err_no_txchan:
+	dma_release_channel(pl022->dma_rx_channel);
+	pl022->dma_rx_channel = NULL;
+err_no_rxchan:
+	return -ENODEV;
+}
+
+static void terminate_dma(struct pl022 *pl022)
+{
+	struct dma_chan *rxchan = pl022->dma_rx_channel;
+	struct dma_chan *txchan = pl022->dma_tx_channel;
+
+	rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0);
+	txchan->device->device_control(txchan, DMA_TERMINATE_ALL, 0);
+	unmap_free_dma_scatter(pl022);
+}
+
+static void pl022_dma_remove(struct pl022 *pl022)
+{
+	if (pl022->busy)
+		terminate_dma(pl022);
+	if (pl022->dma_tx_channel)
+		dma_release_channel(pl022->dma_tx_channel);
+	if (pl022->dma_rx_channel)
+		dma_release_channel(pl022->dma_rx_channel);
+	kfree(pl022->dummypage);
+}
+
+#else
+static inline int configure_dma(struct pl022 *pl022)
+{
+	return -ENODEV;
+}
+
+static inline int pl022_dma_probe(struct pl022 *pl022)
+{
+	return 0;
+}
+
+static inline void pl022_dma_remove(struct pl022 *pl022)
+{
+}
+#endif
+
 /**
  * pl022_interrupt_handler - Interrupt handler for SSP controller
  *
@@ -793,14 +1176,17 @@ static irqreturn_t pl022_interrupt_handler(int irq, void *dev_id)
 	if (unlikely(!irq_status))
 		return IRQ_NONE;
 
-	/* This handles the error code interrupts */
+	/*
+	 * This handles the FIFO interrupts, the timeout
+	 * interrupts are flatly ignored, they cannot be
+	 * trusted.
+	 */
 	if (unlikely(irq_status & SSP_MIS_MASK_RORMIS)) {
 		/*
 		 * Overrun interrupt - bail out since our Data has been
 		 * corrupted
 		 */
-		dev_err(&pl022->adev->dev,
-			"FIFO overrun\n");
+		dev_err(&pl022->adev->dev, "FIFO overrun\n");
 		if (readw(SSP_SR(pl022->virtbase)) & SSP_SR_MASK_RFF)
 			dev_err(&pl022->adev->dev,
 				"RXFIFO is full\n");
@@ -895,8 +1281,8 @@ static int set_up_next_transfer(struct pl022 *pl022,
 }
 
 /**
- * pump_transfers - Tasklet function which schedules next interrupt transfer
- * when running in interrupt transfer mode.
+ * pump_transfers - Tasklet function which schedules next transfer
+ * when running in interrupt or DMA transfer mode.
  * @data: SSP driver private data structure
  *
  */
@@ -953,65 +1339,23 @@ static void pump_transfers(unsigned long data)
 	}
 	/* Flush the FIFOs and let's go! */
 	flush(pl022);
-	writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
-}
 
-/**
- * NOT IMPLEMENTED
- * configure_dma - It configures the DMA pipes for DMA transfers
- * @data: SSP driver's private data structure
- *
- */
-static int configure_dma(void *data)
-{
-	struct pl022 *pl022 = data;
-	dev_dbg(&pl022->adev->dev, "configure DMA\n");
-	return -ENOTSUPP;
-}
-
-/**
- * do_dma_transfer - It handles transfers of the current message
- * if it is DMA xfer.
- * NOT FULLY IMPLEMENTED
- * @data: SSP driver's private data structure
- */
-static void do_dma_transfer(void *data)
-{
-	struct pl022 *pl022 = data;
-
-	if (configure_dma(data)) {
-		dev_dbg(&pl022->adev->dev, "configuration of DMA Failed!\n");
-		goto err_config_dma;
-	}
-
-	/* TODO: Implememt DMA setup of pipes here */
-
-	/* Enable target chip, set up transfer */
-	pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
-	if (set_up_next_transfer(pl022, pl022->cur_transfer)) {
-		/* Error path */
-		pl022->cur_msg->state = STATE_ERROR;
-		pl022->cur_msg->status = -EIO;
-		giveback(pl022);
+	if (pl022->cur_chip->enable_dma) {
+		if (configure_dma(pl022)) {
+			dev_dbg(&pl022->adev->dev,
+				"configuration of DMA failed, fall back to interrupt mode\n");
+			goto err_config_dma;
+		}
 		return;
 	}
-	/* Enable SSP */
-	writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
-	       SSP_CR1(pl022->virtbase));
-
-	/* TODO: Enable the DMA transfer here */
-	return;
 
- err_config_dma:
-	pl022->cur_msg->state = STATE_ERROR;
-	pl022->cur_msg->status = -EIO;
-	giveback(pl022);
-	return;
+err_config_dma:
+	writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
 }
 
-static void do_interrupt_transfer(void *data)
+static void do_interrupt_dma_transfer(struct pl022 *pl022)
 {
-	struct pl022 *pl022 = data;
+	u32 irqflags = ENABLE_ALL_INTERRUPTS;
 
 	/* Enable target chip */
 	pl022->cur_chip->cs_control(SSP_CHIP_SELECT);
@@ -1022,15 +1366,26 @@ static void do_interrupt_transfer(void *data)
 		giveback(pl022);
 		return;
 	}
+	/* If we're using DMA, set up DMA here */
+	if (pl022->cur_chip->enable_dma) {
+		/* Configure DMA transfer */
+		if (configure_dma(pl022)) {
+			dev_dbg(&pl022->adev->dev,
+				"configuration of DMA failed, fall back to interrupt mode\n");
+			goto err_config_dma;
+		}
+		/* Disable interrupts in DMA mode, IRQ from DMA controller */
+		irqflags = DISABLE_ALL_INTERRUPTS;
+	}
+err_config_dma:
 	/* Enable SSP, turn on interrupts */
 	writew((readw(SSP_CR1(pl022->virtbase)) | SSP_CR1_MASK_SSE),
 	       SSP_CR1(pl022->virtbase));
-	writew(ENABLE_ALL_INTERRUPTS, SSP_IMSC(pl022->virtbase));
+	writew(irqflags, SSP_IMSC(pl022->virtbase));
 }
 
-static void do_polling_transfer(void *data)
+static void do_polling_transfer(struct pl022 *pl022)
 {
-	struct pl022 *pl022 = data;
 	struct spi_message *message = NULL;
 	struct spi_transfer *transfer = NULL;
 	struct spi_transfer *previous = NULL;
@@ -1100,7 +1455,7 @@ static void do_polling_transfer(void *data)
  *
  * This function checks if there is any spi message in the queue that
  * needs processing and delegate control to appropriate function
- * do_polling_transfer()/do_interrupt_transfer()/do_dma_transfer()
+ * do_polling_transfer()/do_interrupt_dma_transfer()
  * based on the kind of the transfer
  *
  */
@@ -1148,10 +1503,8 @@ static void pump_messages(struct work_struct *work)
 
 	if (pl022->cur_chip->xfer_type == POLLING_TRANSFER)
 		do_polling_transfer(pl022);
-	else if (pl022->cur_chip->xfer_type == INTERRUPT_TRANSFER)
-		do_interrupt_transfer(pl022);
 	else
-		do_dma_transfer(pl022);
+		do_interrupt_dma_transfer(pl022);
 }
 
 
@@ -1466,23 +1819,6 @@ static int calculate_effective_freq(struct pl022 *pl022,
 }
 
 /**
- * NOT IMPLEMENTED
- * process_dma_info - Processes the DMA info provided by client drivers
- * @chip_info: chip info provided by client device
- * @chip: Runtime state maintained by the SSP controller for each spi device
- *
- * This function processes and stores DMA config provided by client driver
- * into the runtime state maintained by the SSP controller driver
- */
-static int process_dma_info(struct pl022_config_chip *chip_info,
-			    struct chip_data *chip)
-{
-	dev_err(chip_info->dev,
-		"cannot process DMA info, DMA not implemented!\n");
-	return -ENOTSUPP;
-}
-
-/**
  * pl022_setup - setup function registered to SPI master framework
  * @spi: spi device which is requesting setup
  *
@@ -1549,8 +1885,6 @@ static int pl022_setup(struct spi_device *spi)
 
 		dev_dbg(&spi->dev, "allocated memory for controller data\n");
 
-		/* Pointer back to the SPI device */
-		chip_info->dev = &spi->dev;
 		/*
 		 * Set controller data default values:
 		 * Polling is supported by default
@@ -1576,6 +1910,9 @@ static int pl022_setup(struct spi_device *spi)
 			"using user supplied controller_data settings\n");
 	}
 
+	/* Pointer back to the SPI device */
+	chip_info->dev = &spi->dev;
+
 	/*
 	 * We can override with custom divisors, else we use the board
 	 * frequency setting
@@ -1634,9 +1971,8 @@ static int pl022_setup(struct spi_device *spi)
 	chip->cpsr = 0;
 	if ((chip_info->com_mode == DMA_TRANSFER)
 	    && ((pl022->master_info)->enable_dma)) {
-		chip->enable_dma = 1;
+		chip->enable_dma = true;
 		dev_dbg(&spi->dev, "DMA mode set in controller state\n");
-		status = process_dma_info(chip_info, chip);
 		if (status < 0)
 			goto err_config_params;
 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
@@ -1644,7 +1980,7 @@ static int pl022_setup(struct spi_device *spi)
 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_ENABLED,
 			       SSP_DMACR_MASK_TXDMAE, 1);
 	} else {
-		chip->enable_dma = 0;
+		chip->enable_dma = false;
 		dev_dbg(&spi->dev, "DMA mode NOT set in controller state\n");
 		SSP_WRITE_BITS(chip->dmacr, SSP_DMA_DISABLED,
 			       SSP_DMACR_MASK_RXDMAE, 0);
@@ -1723,7 +2059,7 @@ static void pl022_cleanup(struct spi_device *spi)
 }
 
 
-static int __init
+static int __devinit
 pl022_probe(struct amba_device *adev, struct amba_id *id)
 {
 	struct device *dev = &adev->dev;
@@ -1770,6 +2106,7 @@ pl022_probe(struct amba_device *adev, struct amba_id *id)
 	if (status)
 		goto err_no_ioregion;
 
+	pl022->phybase = adev->res.start;
 	pl022->virtbase = ioremap(adev->res.start, resource_size(&adev->res));
 	if (pl022->virtbase == NULL) {
 		status = -ENOMEM;
@@ -1798,6 +2135,14 @@ pl022_probe(struct amba_device *adev, struct amba_id *id)
 		dev_err(&adev->dev, "probe - cannot get IRQ (%d)\n", status);
 		goto err_no_irq;
 	}
+
+	/* Get DMA channels */
+	if (platform_info->enable_dma) {
+		status = pl022_dma_probe(pl022);
+		if (status != 0)
+			goto err_no_dma;
+	}
+
 	/* Initialize and start queue */
 	status = init_queue(pl022);
 	if (status != 0) {
@@ -1824,6 +2169,8 @@ pl022_probe(struct amba_device *adev, struct amba_id *id)
  err_start_queue:
  err_init_queue:
 	destroy_queue(pl022);
+	pl022_dma_remove(pl022);
+ err_no_dma:
 	free_irq(adev->irq[0], pl022);
  err_no_irq:
 	clk_put(pl022->clk);
@@ -1838,7 +2185,7 @@ pl022_probe(struct amba_device *adev, struct amba_id *id)
 	return status;
 }
 
-static int __exit
+static int __devexit
 pl022_remove(struct amba_device *adev)
 {
 	struct pl022 *pl022 = amba_get_drvdata(adev);
@@ -1854,6 +2201,7 @@ pl022_remove(struct amba_device *adev)
 		return status;
 	}
 	load_ssp_default_config(pl022);
+	pl022_dma_remove(pl022);
 	free_irq(adev->irq[0], pl022);
 	clk_disable(pl022->clk);
 	clk_put(pl022->clk);
@@ -1970,7 +2318,7 @@ static struct amba_driver pl022_driver = {
 	},
 	.id_table	= pl022_ids,
 	.probe		= pl022_probe,
-	.remove		= __exit_p(pl022_remove),
+	.remove		= __devexit_p(pl022_remove),
 	.suspend        = pl022_suspend,
 	.resume         = pl022_resume,
 };
diff --git a/include/linux/amba/pl022.h b/include/linux/amba/pl022.h
index abf26cc..db6a191 100644
--- a/include/linux/amba/pl022.h
+++ b/include/linux/amba/pl022.h
@@ -228,6 +228,7 @@ enum ssp_chip_select {
 };
 
 
+struct dma_chan;
 /**
  * struct pl022_ssp_master - device.platform_data for SPI controller devices.
  * @num_chipselect: chipselects are used to distinguish individual
@@ -235,11 +236,16 @@ enum ssp_chip_select {
  *     each slave has a chipselect signal, but it's common that not
  *     every chipselect is connected to a slave.
  * @enable_dma: if true enables DMA driven transfers.
+ * @dma_rx_param: parameter to locate an RX DMA channel.
+ * @dma_tx_param: parameter to locate a TX DMA channel.
  */
 struct pl022_ssp_controller {
 	u16 bus_id;
 	u8 num_chipselect;
 	u8 enable_dma:1;
+	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+	void *dma_rx_param;
+	void *dma_tx_param;
 };
 
 /**
-- 
1.6.3.3



From linus.walleij at stericsson.com  Fri Jun 11 11:27:03 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:27:03 +0200
Subject: [PATCH 05/13] ARM: correct PL080 editor mistake
Message-ID: <1276270023-1553-1-git-send-email-linus.walleij@stericsson.com>

This PL008 among all other variables named PL080 doesn't seem
right. Fix it.

Cc: Ben Dooks <ben-linux at fluff.org>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/include/asm/hardware/pl080.h |    2 +-
 arch/arm/mach-s3c64xx/dma.c           |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
index 6a6c66b..f70e1e9 100644
--- a/arch/arm/include/asm/hardware/pl080.h
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -43,7 +43,7 @@
 
 /* Per channel configuration registers */
 
-#define PL008_Cx_STRIDE				(0x20)
+#define PL080_Cx_STRIDE				(0x20)
 #define PL080_Cx_BASE(x)			((0x100 + (x * 0x20)))
 #define PL080_Cx_SRC_ADDR(x)			((0x100 + (x * 0x20)))
 #define PL080_Cx_DST_ADDR(x)			((0x104 + (x * 0x20)))
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 5567e03..e7d03ab 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -697,7 +697,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
 		chptr->number = chno;
 		chptr->dmac = dmac;
 		chptr->regs = regptr;
-		regptr += PL008_Cx_STRIDE;
+		regptr += PL080_Cx_STRIDE;
 	}
 
 	/* for the moment, permanently enable the controller */
-- 
1.6.3.3



From linus.walleij at stericsson.com  Fri Jun 11 11:27:30 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:27:30 +0200
Subject: [PATCH 08/13] ARM: add PrimeCell generic DMA to PL011 v8
Message-ID: <1276270050-1713-1-git-send-email-linus.walleij@stericsson.com>

This extends the PL011 UART driver with generic DMA engine support
using the PrimeCell DMA engine interface.

Tested-by: Jerzy Kasenberg <jerzy.kasenberg at tieto.com>
Tested-by: Grzegorz Sygieda <grzegorz.sygieda at tieto.com>
Tested-by: Marcin Mielczarczyk <marcin.mielczarczyk at tieto.com>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 drivers/serial/amba-pl011.c |  847 ++++++++++++++++++++++++++++++++++++++++++-
 include/linux/amba/serial.h |    6 +
 2 files changed, 844 insertions(+), 9 deletions(-)

diff --git a/drivers/serial/amba-pl011.c b/drivers/serial/amba-pl011.c
index eb4cb48..8ac7015 100644
--- a/drivers/serial/amba-pl011.c
+++ b/drivers/serial/amba-pl011.c
@@ -7,6 +7,7 @@
  *
  *  Copyright 1999 ARM Limited
  *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *  Copyright (C) 2010 ST-Ericsson SA
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -48,6 +49,12 @@
 #include <linux/amba/serial.h>
 #include <linux/clk.h>
 #include <linux/slab.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/scatterlist.h>
+#include <linux/completion.h>
+#include <linux/amba/dma.h>
+#include <linux/delay.h>
 
 #include <asm/io.h>
 #include <asm/sizes.h>
@@ -63,6 +70,24 @@
 #define UART_DR_ERROR		(UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
 #define UART_DUMMY_DR_RX	(1 << 16)
 
+/* Deals with DMA transactions */
+struct pl011_dma_rx_transaction {
+	struct completion complete;
+	bool use_buffer_b;
+	struct scatterlist scatter_a;
+	struct scatterlist scatter_b;
+	char *rx_dma_buf_a;
+	char *rx_dma_buf_b;
+	dma_cookie_t cookie;
+};
+
+struct pl011_dma_tx_transaction {
+	struct completion complete;
+	struct scatterlist scatter;
+	char *tx_dma_buf;
+	dma_cookie_t cookie;
+};
+
 /*
  * We wrap our port structure around the generic uart_port.
  */
@@ -73,6 +98,16 @@ struct uart_amba_port {
 	unsigned int		old_status;
 	unsigned int		ifls;	/* vendor-specific */
 	bool			autorts;
+	unsigned int		fifosize;
+	/* DMA stuff */
+	bool			enable_dma;
+	bool			rx_dma_running;
+#ifdef CONFIG_DMADEVICES
+	struct dma_chan		*dma_rx_channel;
+	struct dma_chan		*dma_tx_channel;
+	struct pl011_dma_rx_transaction dmarx;
+	struct pl011_dma_tx_transaction dmatx;
+#endif
 };
 
 /* There is by now at least one vendor with differing details, so handle it */
@@ -91,6 +126,720 @@ static struct vendor_data vendor_st = {
 	.fifosize		= 64,
 };
 
+/*
+ * All the DMA operation mode stuff goes inside this ifdef.
+ * This assumes that you have a generic DMA device interface,
+ * no custom DMA interfaces are supported.
+ */
+#ifdef CONFIG_DMADEVICES
+
+#define PL011_DMA_BUFFER_SIZE PAGE_SIZE
+
+static void __init pl011_dma_probe_initcall(struct uart_amba_port *uap)
+{
+	/* DMA is the sole user of the platform data right now */
+	struct amba_pl011_data *plat = uap->port.dev->platform_data;
+	struct pl011_dma_rx_transaction *dmarx = &uap->dmarx;
+	struct pl011_dma_tx_transaction *dmatx = &uap->dmatx;
+	struct amba_dma_channel_config rx_conf = {
+		.addr = uap->port.mapbase + UART01x_DR,
+		.addr_width = 1,
+		.direction = DMA_FROM_DEVICE,
+		.maxburst = uap->fifosize >> 1,
+	};
+	struct amba_dma_channel_config tx_conf = {
+		.addr = uap->port.mapbase + UART01x_DR,
+		.addr_width = 1,
+		.direction = DMA_TO_DEVICE,
+		.maxburst = uap->fifosize >> 1,
+	};
+	dma_cap_mask_t mask;
+	int sglen;
+
+	/* We need platform data */
+	if (!plat) {
+		dev_err(uap->port.dev, "no DMA platform data!\n");
+		return;
+	}
+
+	/* Try to acquire a generic DMA engine slave channel */
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+
+	/*
+	 * We need both RX and TX channels to do DMA, else do none
+	 * of them.
+	 */
+	uap->dma_rx_channel = dma_request_channel(mask,
+						  plat->dma_filter,
+						  plat->dma_rx_param);
+	if (!uap->dma_rx_channel) {
+		dev_err(uap->port.dev, "no RX DMA channel!\n");
+		return;
+	}
+	uap->dma_rx_channel->device->device_control(uap->dma_rx_channel,
+						    DMA_CONFIG_AMBA,
+						    (unsigned long) &rx_conf);
+
+	uap->dma_tx_channel = dma_request_channel(mask,
+						  plat->dma_filter,
+						  plat->dma_tx_param);
+	if (!uap->dma_tx_channel) {
+		dev_err(uap->port.dev, "no TX DMA channel!\n");
+		goto err_no_txchan;
+	}
+	uap->dma_tx_channel->device->device_control(uap->dma_tx_channel,
+						    DMA_CONFIG_AMBA,
+						    (unsigned long) &tx_conf);
+
+	/* Allocate DMA RX and TX buffers */
+	dmarx->rx_dma_buf_a = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
+	if (!dmarx->rx_dma_buf_a) {
+		dev_err(uap->port.dev, "failed to allocate DMA RX buffer A\n");
+		goto err_no_rxbuf_a;
+	}
+
+	dmarx->rx_dma_buf_b = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
+	if (!dmarx->rx_dma_buf_b) {
+		dev_err(uap->port.dev, "failed to allocate DMA RX buffer B\n");
+		goto err_no_rxbuf_b;
+	}
+
+	dmatx->tx_dma_buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL);
+	if (!dmatx->tx_dma_buf) {
+		dev_err(uap->port.dev, "failed to allocate DMA TX buffer\n");
+		goto err_no_txbuf;
+	}
+
+	/* Provide single SG list with one item to the buffers */
+	sg_init_one(&dmarx->scatter_a, dmarx->rx_dma_buf_a,
+		    PL011_DMA_BUFFER_SIZE);
+	sg_init_one(&dmarx->scatter_b, dmarx->rx_dma_buf_b,
+		    PL011_DMA_BUFFER_SIZE);
+	sg_init_one(&dmatx->scatter, dmatx->tx_dma_buf, PL011_DMA_BUFFER_SIZE);
+
+	/* Map DMA buffers */
+	sglen = dma_map_sg(uap->port.dev, &dmarx->scatter_a,
+			   1, DMA_FROM_DEVICE);
+	if (sglen != 1)
+		goto err_rx_sgmap_a;
+
+	sglen = dma_map_sg(uap->port.dev, &dmarx->scatter_b,
+			   1, DMA_FROM_DEVICE);
+	if (sglen != 1)
+		goto err_rx_sgmap_b;
+
+	sglen = dma_map_sg(uap->port.dev, &dmatx->scatter,
+			   1, DMA_TO_DEVICE);
+	if (sglen != 1)
+		goto err_tx_sgmap;
+
+	/* Initially we say the transfers are incomplete */
+	init_completion(&uap->dmatx.complete);
+	complete(&uap->dmatx.complete);
+
+	/* The DMA buffer is now the FIFO the TTY subsystem can use */
+	uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
+
+	uap->enable_dma = true;
+	dev_info(uap->port.dev, "setup for DMA on RX %s, TX %s\n",
+		 dma_chan_name(uap->dma_rx_channel),
+		 dma_chan_name(uap->dma_tx_channel));
+	return;
+
+err_tx_sgmap:
+	dma_unmap_sg(uap->port.dev, &dmarx->scatter_b,
+		     1, DMA_FROM_DEVICE);
+err_rx_sgmap_b:
+	dma_unmap_sg(uap->port.dev, &dmarx->scatter_a,
+		     1, DMA_FROM_DEVICE);
+err_rx_sgmap_a:
+	kfree(dmatx->tx_dma_buf);
+err_no_txbuf:
+	kfree(dmarx->rx_dma_buf_b);
+err_no_rxbuf_b:
+	kfree(dmarx->rx_dma_buf_a);
+err_no_rxbuf_a:
+	dma_release_channel(uap->dma_tx_channel);
+	uap->dma_tx_channel = NULL;
+err_no_txchan:
+	dma_release_channel(uap->dma_rx_channel);
+	uap->dma_rx_channel = NULL;
+	return;
+}
+
+/*
+ * Stack up the UARTs and let the above initcall be done at
+ * device initcall time, because the serial driver is called as
+ * an arch initcall, and at this time the DMA subsystem is not yet
+ * registered. At this point the driver will switch over to using
+ * DMA where desired.
+ */
+
+struct dma_uap {
+	struct list_head node;
+	struct uart_amba_port *uap;
+};
+
+struct list_head __initdata pl011_dma_uarts = LIST_HEAD_INIT(pl011_dma_uarts);
+
+static int __init pl011_dma_initcall(void)
+{
+	struct list_head *node, *tmp;
+
+	list_for_each_safe(node, tmp, &pl011_dma_uarts) {
+		struct dma_uap *dmau = list_entry(node, struct dma_uap, node);
+		pl011_dma_probe_initcall(dmau->uap);
+		list_del(node);
+		kfree(dmau);
+	}
+	return 0;
+}
+
+device_initcall(pl011_dma_initcall);
+
+static void pl011_dma_probe(struct uart_amba_port *uap)
+{
+	struct dma_uap *dmau = kzalloc(sizeof(struct dma_uap), GFP_KERNEL);
+
+	if (dmau == NULL)
+		return;
+	dmau->uap = uap;
+	list_add_tail(&dmau->node, &pl011_dma_uarts);
+}
+
+static void pl011_dma_remove(struct uart_amba_port *uap)
+{
+	struct pl011_dma_rx_transaction *dmarx = &uap->dmarx;
+	struct pl011_dma_tx_transaction *dmatx = &uap->dmatx;
+
+	/* TODO: remove the initcall if it has not yet executed */
+	/* Unmap and free DMA buffers */
+	if (uap->dma_rx_channel)
+		dma_release_channel(uap->dma_rx_channel);
+	if (uap->dma_tx_channel)
+		dma_release_channel(uap->dma_tx_channel);
+	if (dmatx->tx_dma_buf) {
+		dma_unmap_sg(uap->port.dev, &dmatx->scatter,
+			     1, DMA_TO_DEVICE);
+		kfree(dmatx->tx_dma_buf);
+	}
+	if (dmarx->rx_dma_buf_b) {
+		dma_unmap_sg(uap->port.dev, &dmarx->scatter_b,
+			     1, DMA_FROM_DEVICE);
+		kfree(dmarx->rx_dma_buf_b);
+	}
+	if (dmarx->rx_dma_buf_a) {
+		dma_unmap_sg(uap->port.dev, &dmarx->scatter_a,
+			     1, DMA_FROM_DEVICE);
+		kfree(dmarx->rx_dma_buf_a);
+	}
+}
+
+/* Forward declare this for the refill routine */
+static int pl011_dma_tx_refill(struct uart_amba_port *uap);
+
+/*
+ * Move the tail when this IRQ occurs, if not empty refill and
+ * fire another transaction
+ */
+static void pl011_dma_tx_callback(void *data)
+{
+	struct uart_amba_port *uap = data;
+	struct pl011_dma_tx_transaction *dmatx = &uap->dmatx;
+	struct circ_buf *xmit = &uap->port.state->xmit;
+	u16 val;
+	int ret;
+
+	/* Temporarily disable TX DMA */
+	val = readw(uap->port.membase + UART011_DMACR);
+	val &= ~(UART011_TXDMAE);
+	writew(val, uap->port.membase + UART011_DMACR);
+
+	/* Refill the TX if the buffer is not empty */
+	if (!uart_circ_empty(xmit)) {
+		ret = pl011_dma_tx_refill(uap);
+		if (ret == -EBUSY)
+			/*
+			 * If DMA cannot be used right now, we complete this
+			 * transaction and let the TTY layer retry. If the
+			 * firs following xfer fails to set up for DMA, it
+			 * will fall through to interrupt mode.
+			 */
+			dev_dbg(uap->port.dev, "DMA busy\n");
+	} else {
+		complete(&dmatx->complete);
+	}
+}
+
+static int pl011_dma_tx_refill(struct uart_amba_port *uap)
+{
+	struct pl011_dma_tx_transaction *dmatx = &uap->dmatx;
+	struct dma_chan *chan = uap->dma_tx_channel;
+	struct dma_async_tx_descriptor *desc;
+	struct circ_buf *xmit = &uap->port.state->xmit;
+	unsigned int count;
+	unsigned long flags;
+	u16 val;
+
+	/* Don't bother about using DMA on XON/XOFF */
+	if (uap->port.x_char) {
+		/* If we can't get it into the FIFO, retry later */
+		if (readw(uap->port.membase + UART01x_FR) &
+		    UART01x_FR_TXFF) {
+			complete(&dmatx->complete);
+			return 0;
+		}
+		writew(uap->port.x_char, uap->port.membase + UART01x_DR);
+		uap->port.icount.tx++;
+		uap->port.x_char = 0;
+		complete(&dmatx->complete);
+		return 0;
+	}
+
+	/*
+	 * Try to avoid the overhead involved in using DMA if the
+	 * transaction fits in the first half of the FIFO and it's not
+	 * full. Unfortunately there is only one single bit in the
+	 * hardware to tell whether the FIFO is full or not, so
+	 * we don't know exactly how many chars we can fit in.
+	 */
+	if (uart_circ_chars_pending(xmit) < (uap->fifosize >> 1)) {
+		while (uart_circ_chars_pending(xmit)) {
+			if (readw(uap->port.membase + UART01x_FR) &
+			    UART01x_FR_TXFF) {
+				/*
+				 * Ooops TX FIFO is full, we'd better stop
+				 * this. Let's enable TX interrupt here to get
+				 * informed when there is again some space in
+				 * the TX FIFO so we can continue the transfer.
+				 * This interrupt will be cleared just before
+				 * setting up DMA, as it could interfere with
+				 * TX interrupt handling routine.
+				 */
+				uap->im |= UART011_TXIM;
+				writew(uap->im,
+				       uap->port.membase + UART011_IMSC);
+				break;
+			}
+			writew(xmit->buf[xmit->tail],
+			       uap->port.membase + UART01x_DR);
+			uap->port.icount.tx++;
+			xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+		}
+		complete(&dmatx->complete);
+		return 0;
+	}
+
+	/*
+	 * Clear TX interrupt to be sure that DMA will not interfere with
+	 * TX ISR
+	 */
+	local_irq_save(flags);
+	uap->im &= ~UART011_TXIM;
+	writew(uap->im, uap->port.membase + UART011_IMSC);
+	local_irq_restore(flags);
+
+	/* Sync the buffer for the CPU so we can write into it */
+	dma_sync_sg_for_cpu(uap->port.dev,
+			    &dmatx->scatter,
+			    1,
+			    DMA_TO_DEVICE);
+
+	/* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
+	count = uart_circ_chars_pending(xmit);
+	if (count > PL011_DMA_BUFFER_SIZE)
+		count = PL011_DMA_BUFFER_SIZE;
+
+	if (xmit->tail < xmit->head)
+		memcpy(&dmatx->tx_dma_buf[0], &xmit->buf[xmit->tail], count);
+	else {
+		size_t first = UART_XMIT_SIZE - xmit->tail;
+		size_t second = xmit->head;
+
+		memcpy(&dmatx->tx_dma_buf[0], &xmit->buf[xmit->tail], first);
+		memcpy(&dmatx->tx_dma_buf[first], &xmit->buf[0], second);
+	}
+
+	dmatx->scatter.length = count;
+
+	/* Synchronize the scatterlist, invalidate buffers, caches etc */
+	dma_sync_sg_for_device(uap->port.dev,
+			       &dmatx->scatter,
+			       1,
+			       DMA_TO_DEVICE);
+
+	/* Prepare the scatterlist */
+	desc = chan->device->device_prep_slave_sg(chan,
+						  &dmatx->scatter,
+						  1,
+						  DMA_TO_DEVICE,
+						  DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	if (!desc) {
+		/* "Complete" DMA (errorpath) */
+		complete(&dmatx->complete);
+		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
+		return -EBUSY;
+	}
+
+	/* Some data to go along to the callback */
+	desc->callback = pl011_dma_tx_callback;
+	desc->callback_param = uap;
+
+	/* Here is where overloaded DMA controllers can fail */
+	dmatx->cookie = desc->tx_submit(desc);
+	if (dma_submit_error(dmatx->cookie)) {
+		/* "Complete" DMA (errorpath) */
+		complete(&dmatx->complete);
+		chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
+		return dmatx->cookie;
+	}
+
+	/*
+	 * Now we know that DMA will fire, so advance the ring buffer
+	 * with the stuff we just dispatched
+	 */
+	xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
+	uap->port.icount.tx += count;
+	if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
+		uart_write_wakeup(&uap->port);
+
+	/* Fire the DMA transaction */
+	chan->device->device_issue_pending(chan);
+
+	val = readw(uap->port.membase + UART011_DMACR);
+	val |= UART011_TXDMAE;
+	writew(val, uap->port.membase + UART011_DMACR);
+	return 0;
+}
+
+static void pl011_dma_rx_callback(void *data);
+
+static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
+{
+	struct dma_chan *rxchan = uap->dma_rx_channel;
+	struct pl011_dma_rx_transaction *dmarx = &uap->dmarx;
+	struct dma_async_tx_descriptor *desc;
+	struct scatterlist *scatter = dmarx->use_buffer_b ?
+		&dmarx->scatter_b : &dmarx->scatter_a;
+	u16 val;
+
+	/* Start the RX DMA job */
+	desc = rxchan->device->device_prep_slave_sg(rxchan,
+						    scatter,
+						    1,
+						    DMA_FROM_DEVICE,
+						    DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	/*
+	 * If the DMA engine is busy and cannot prepare a
+	 * channel, no big deal, the driver will fall back
+	 * to interrupt mode as a result of this error code.
+	 */
+	if (!desc) {
+		uap->rx_dma_running = false;
+		rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0);
+		return -EBUSY;
+	}
+
+	/* Some data to go along to the callback */
+	desc->callback = pl011_dma_rx_callback;
+	desc->callback_param = uap;
+	/* This is another point where an overloaded engine can fail */
+	dmarx->cookie = desc->tx_submit(desc);
+	if (dma_submit_error(dmarx->cookie)) {
+		uap->rx_dma_running = false;
+		rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0);
+		return -EBUSY;
+	}
+
+	rxchan->device->device_issue_pending(rxchan);
+
+	val = readw(uap->port.membase + UART011_DMACR);
+	val |= UART011_RXDMAE;
+	writew(val, uap->port.membase + UART011_DMACR);
+	uap->rx_dma_running = true;
+
+	return 0;
+}
+
+/*
+ * This is called when either the DMA job is complete, or
+ * the FIFO timeout interrupt occurred. This must be called
+ * with the port spinlock uap->port.lock held.
+ */
+static void pl011_dma_rx_chars(struct uart_amba_port *uap,
+			       u32 pending, bool use_buffer_b,
+			       bool readfifo)
+{
+	struct pl011_dma_rx_transaction *dmarx = &uap->dmarx;
+	struct tty_struct *tty = uap->port.state->port.tty;
+	char *buf = use_buffer_b ? dmarx->rx_dma_buf_b : dmarx->rx_dma_buf_a;
+	struct scatterlist *scatter = use_buffer_b ?
+		&dmarx->scatter_b : &dmarx->scatter_a;
+	unsigned int status, ch, flag;
+	u32 count = pending;
+	u32 bufp = 0;
+	u32 fifotaken = 0; /* only used for vdbg() */
+
+	/* Sync in buffer */
+	dma_sync_sg_for_cpu(uap->port.dev,
+			    scatter,
+			    1,
+			    DMA_FROM_DEVICE);
+
+	status = readw(uap->port.membase + UART01x_FR);
+
+	/*
+	 * First take all chars in the DMA pipe, then look
+	 * in the FIFO. So loop while we have chars in the
+	 * DMA buffer or the FIFO. If we came here from a
+	 * DMA buffer full interrupt, there is already another
+	 * DMA job triggered to read the FIFO, so don't look
+	 * at it.
+	 */
+	while (count ||
+	       (readfifo && (status & UART01x_FR_RXFE) == 0)) {
+
+		flag = TTY_NORMAL;
+		uap->port.icount.rx++;
+
+		if (count) {
+			/* Take chars from the DMA buffer */
+			int inserted = tty_insert_flip_string(
+					uap->port.state->port.tty, buf, count);
+
+			/*
+			 * Check if insertion is successful to avoid
+			 * infinite loop. This can happen when TTY is full.
+			 */
+			if (unlikely(inserted == 0))
+				count = 0;
+			else {
+				count -= inserted;
+				bufp += inserted;
+			}
+			continue;
+		} else {
+			/* Take chars from the FIFO and update status */
+			ch = readw(uap->port.membase + UART01x_DR);
+			status = readw(uap->port.membase + UART01x_FR);
+			fifotaken++;
+
+			/*
+			 * Error conditions will only occur in the FIFO,
+			 * these will trigger an immediate interrupt and
+			 * stop the DMA job, so we will always find the
+			 * error in the FIFO, never in the DMA buffer.
+			 */
+			if (unlikely(ch & UART_DR_ERROR)) {
+				if (ch & UART011_DR_BE) {
+					ch &= ~(UART011_DR_FE | UART011_DR_PE);
+					uap->port.icount.brk++;
+					if (uart_handle_break(&uap->port))
+						continue;
+				} else if (ch & UART011_DR_PE)
+					uap->port.icount.parity++;
+				else if (ch & UART011_DR_FE)
+					uap->port.icount.frame++;
+				if (ch & UART011_DR_OE)
+					uap->port.icount.overrun++;
+
+				ch &= uap->port.read_status_mask;
+
+				if (ch & UART011_DR_BE)
+					flag = TTY_BREAK;
+				else if (ch & UART011_DR_PE)
+					flag = TTY_PARITY;
+				else if (ch & UART011_DR_FE)
+					flag = TTY_FRAME;
+			}
+		}
+
+		if (uart_handle_sysrq_char(&uap->port, ch & 255))
+			continue;
+
+		uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
+	}
+
+	spin_unlock(&uap->port.lock);
+	dev_vdbg(uap->port.dev,
+		 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
+		 bufp, fifotaken);
+	tty_flip_buffer_push(tty);
+	spin_lock(&uap->port.lock);
+}
+
+static void pl011_dma_rx_irq(struct uart_amba_port *uap)
+{
+	struct dma_chan *rxchan = uap->dma_rx_channel;
+	struct pl011_dma_rx_transaction *dmarx = &uap->dmarx;
+	struct scatterlist *scatter = dmarx->use_buffer_b ?
+		&dmarx->scatter_b : &dmarx->scatter_a;
+	u32 pending;
+	int ret;
+	struct dma_tx_state state;
+	enum dma_status dmastat;
+	u16 val;
+
+	/* Use PrimeCell DMA extensions to stop the transfer */
+	ret = rxchan->device->device_control(rxchan, DMA_PAUSE, 0);
+	if (ret)
+		dev_err(uap->port.dev, "unable to pause DMA transfer\n");
+	dmastat = rxchan->device->device_tx_status(rxchan,
+						   dmarx->cookie, &state);
+
+	/* Disable RX DMA temporarily */
+	val = readw(uap->port.membase + UART011_DMACR);
+	val &= ~(UART011_RXDMAE);
+	writew(val, uap->port.membase + UART011_DMACR);
+	uap->rx_dma_running = false;
+
+	if (dmastat != DMA_PAUSED)
+		dev_err(uap->port.dev, "unable to pause DMA transfer\n");
+	pending = scatter->length - state.residue;
+
+	BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
+
+	ret = rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0);
+	if (ret)
+		dev_err(uap->port.dev, "unable to terminate DMA transfer\n");
+
+	/*
+	 * This will take the chars we have so far and insert
+	 * into the framework.
+	 */
+	pl011_dma_rx_chars(uap, pending, dmarx->use_buffer_b, true);
+
+	/* Switch buffer & re-trigger DMA job */
+	dmarx->use_buffer_b = !dmarx->use_buffer_b;
+	ret = pl011_dma_rx_trigger_dma(uap);
+	if (ret) {
+		dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
+			"fall back to interrupt mode\n");
+		uap->im |= UART011_RXIM;
+		writew(uap->im, uap->port.membase + UART011_IMSC);
+	}
+}
+
+static void pl011_dma_rx_callback(void *data)
+{
+	struct uart_amba_port *uap = data;
+	struct pl011_dma_rx_transaction *dmarx = &uap->dmarx;
+	bool lastbuf = dmarx->use_buffer_b;
+	int ret;
+
+	/*
+	 * This completion interrupt occurs typically when the
+	 * RX buffer is totally stuffed but no timeout has yet
+	 * occurred. When that happens, we just want the RX
+	 * routine to flush out the secondary DMA buffer while
+	 * we immediately trigger the next DMA job.
+	 */
+	uap->rx_dma_running = false;
+	dmarx->use_buffer_b = !lastbuf;
+	ret = pl011_dma_rx_trigger_dma(uap);
+
+	spin_lock_irq(&uap->port.lock);
+	pl011_dma_rx_chars(uap, PL011_DMA_BUFFER_SIZE, lastbuf, false);
+	spin_unlock_irq(&uap->port.lock);
+	/*
+	 * Do this check after we picked the DMA chars so we don't
+	 * get some IRQ immediately from RX.
+	 */
+	if (ret) {
+		dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
+			"fall back to interrupt mode\n");
+		uap->im |= UART011_RXIM;
+		writew(uap->im, uap->port.membase + UART011_IMSC);
+	}
+}
+
+static void pl011_dma_startup(struct uart_amba_port *uap)
+{
+	u16 val;
+	int ret = 0;
+
+	if (!uap->enable_dma)
+		return;
+
+	/* Turn on DMA error (RX/TX will be enabled on demand) */
+	val = readw(uap->port.membase + UART011_DMACR);
+	val |= UART011_DMAONERR;
+	writew(val, uap->port.membase + UART011_DMACR);
+
+	ret = pl011_dma_rx_trigger_dma(uap);
+	if (ret)
+		dev_dbg(uap->port.dev, "could not trigger initial "
+			"RX DMA job, fall back to interrupt mode\n");
+}
+
+static void pl011_dma_shutdown(struct uart_amba_port *uap)
+{
+	struct dma_chan *rxchan = uap->dma_rx_channel;
+	struct dma_chan *txchan = uap->dma_tx_channel;
+	u16 val;
+
+	if (!uap->enable_dma)
+		return;
+
+	/* Disable RX and TX DMA */
+	while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
+		barrier();
+	val = readw(uap->port.membase + UART011_DMACR);
+	val &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
+	writew(val, uap->port.membase + UART011_DMACR);
+	/* Terminate any RX and TX DMA jobs */
+	rxchan->device->device_control(rxchan, DMA_TERMINATE_ALL, 0);
+	txchan->device->device_control(txchan, DMA_TERMINATE_ALL, 0);
+}
+
+static int pl011_dma_tx_chars(struct uart_amba_port *uap)
+{
+	struct pl011_dma_tx_transaction *dmatx = &uap->dmatx;
+
+	/* Try to wait for completion, return if something is in progress */
+	if (!try_wait_for_completion(&dmatx->complete))
+		return -EINPROGRESS;
+
+	/* Set up and fire the DMA job */
+	init_completion(&dmatx->complete);
+	return pl011_dma_tx_refill(uap);
+}
+
+#else
+/* Blank functions if the DMA engine is not available */
+static inline void pl011_dma_probe(struct uart_amba_port *uap)
+{
+}
+
+static inline void pl011_dma_remove(struct uart_amba_port *uap)
+{
+}
+
+static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
+{
+}
+
+static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
+{
+	return -EIO;
+}
+
+static inline void pl011_dma_startup(struct uart_amba_port *uap)
+{
+}
+
+static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
+{
+}
+
+static inline int pl011_dma_tx_chars(struct uart_amba_port *uap)
+{
+	return -EIO;
+}
+#endif
+
+
 static void pl011_stop_tx(struct uart_port *port)
 {
 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
@@ -99,10 +848,18 @@ static void pl011_stop_tx(struct uart_port *port)
 	writew(uap->im, uap->port.membase + UART011_IMSC);
 }
 
+static void pl011_tx_chars(struct uart_amba_port *uap);
+
 static void pl011_start_tx(struct uart_port *port)
 {
 	struct uart_amba_port *uap = (struct uart_amba_port *)port;
 
+	if (uap->enable_dma) {
+		/* Immediately push out chars in DMA mode */
+		pl011_tx_chars(uap);
+		return;
+	}
+	/* In interrupt mode, let the interrupt pull chars */
 	uap->im |= UART011_TXIM;
 	writew(uap->im, uap->port.membase + UART011_IMSC);
 }
@@ -128,6 +885,7 @@ static void pl011_rx_chars(struct uart_amba_port *uap)
 {
 	struct tty_struct *tty = uap->port.state->port.tty;
 	unsigned int status, ch, flag, max_count = 256;
+	int ret;
 
 	status = readw(uap->port.membase + UART01x_FR);
 	while ((status & UART01x_FR_RXFE) == 0 && max_count--) {
@@ -172,6 +930,21 @@ static void pl011_rx_chars(struct uart_amba_port *uap)
 	}
 	spin_unlock(&uap->port.lock);
 	tty_flip_buffer_push(tty);
+	/*
+	 * If we were temporarily out of DMA mode for a while,
+	 * attempt to switch back to DMA mode again.
+	 */
+	if (uap->enable_dma) {
+		uap->im &= ~UART011_RXIM;
+		writew(uap->im, uap->port.membase + UART011_IMSC);
+		ret = pl011_dma_rx_trigger_dma(uap);
+		if (ret) {
+			dev_dbg(uap->port.dev, "could not trigger RX DMA job "
+				"fall back to interrupt mode again\n");
+			uap->im |= UART011_RXIM;
+			writew(uap->im, uap->port.membase + UART011_IMSC);
+		}
+	}
 	spin_lock(&uap->port.lock);
 }
 
@@ -180,6 +953,25 @@ static void pl011_tx_chars(struct uart_amba_port *uap)
 	struct circ_buf *xmit = &uap->port.state->xmit;
 	int count;
 
+	if (uap->enable_dma) {
+		int ret;
+
+		ret = pl011_dma_tx_chars(uap);
+		if (!ret)
+			return;
+		if (ret == -EINPROGRESS)
+			return;
+
+		/*
+		 * On any other error (including -EBUSY which is emitted
+		 * in case the DMA engine is out of physical channels
+		 * for example) we fall through to interrupt mode
+		 */
+		dev_dbg(uap->port.dev, "DMA unavailable for TX\n");
+		uap->im |= UART011_TXIM;
+		writew(uap->im, uap->port.membase + UART011_IMSC);
+	}
+
 	if (uap->port.x_char) {
 		writew(uap->port.x_char, uap->port.membase + UART01x_DR);
 		uap->port.icount.tx++;
@@ -191,8 +983,10 @@ static void pl011_tx_chars(struct uart_amba_port *uap)
 		return;
 	}
 
-	count = uap->port.fifosize >> 1;
+	count = uap->fifosize >> 1;
 	do {
+		if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
+			break;
 		writew(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
 		xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 		uap->port.icount.tx++;
@@ -237,7 +1031,7 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
 	unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
 	int handled = 0;
 
-	spin_lock(&uap->port.lock);
+	spin_lock_irq(&uap->port.lock);
 
 	status = readw(uap->port.membase + UART011_MIS);
 	if (status) {
@@ -246,13 +1040,30 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
 					  UART011_RXIS),
 			       uap->port.membase + UART011_ICR);
 
-			if (status & (UART011_RTIS|UART011_RXIS))
-				pl011_rx_chars(uap);
+			if (status & (UART011_RTIS|UART011_RXIS)) {
+				if (uap->enable_dma && uap->rx_dma_running)
+					pl011_dma_rx_irq(uap);
+				else
+					pl011_rx_chars(uap);
+			}
 			if (status & (UART011_DSRMIS|UART011_DCDMIS|
 				      UART011_CTSMIS|UART011_RIMIS))
 				pl011_modem_status(uap);
-			if (status & UART011_TXIS)
+			if (status & UART011_TXIS) {
+				/*
+				 * When DMA is enabled we still use TX
+				 * interrupt to send small amounts of data,
+				 * and as a fallback when the DMA channel is
+				 * not available. This interrupt is cleared
+				 * here and will be enabled when it's needed.
+				 */
+				if (uap->enable_dma) {
+					uap->im &= ~UART011_TXIM;
+					writew(uap->im,
+					       uap->port.membase + UART011_IMSC);
+				}
 				pl011_tx_chars(uap);
+			}
 
 			if (pass_counter-- == 0)
 				break;
@@ -262,7 +1073,7 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
 		handled = 1;
 	}
 
-	spin_unlock(&uap->port.lock);
+	spin_unlock_irq(&uap->port.lock);
 
 	return IRQ_RETVAL(handled);
 }
@@ -401,16 +1212,28 @@ static int pl011_startup(struct uart_port *port)
 	cr = UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
 	writew(cr, uap->port.membase + UART011_CR);
 
+	/* Clear pending error interrupts*/
+	writew(0xFFFF & ~(UART011_TXIS | UART011_RTIS | UART011_RXIS),
+	       uap->port.membase + UART011_ICR);
+
 	/*
 	 * initialise the old status of the modem signals
 	 */
 	uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
 
+	/* Startup DMA */
+	pl011_dma_startup(uap);
+
 	/*
-	 * Finally, enable interrupts
+	 * Finally, enable interrupts, only timeouts when using DMA
+	 * if initial RX DMA job failed, start in interrupt mode
+	 * as well.
 	 */
 	spin_lock_irq(&uap->port.lock);
-	uap->im = UART011_RXIM | UART011_RTIM;
+	if (uap->enable_dma && uap->rx_dma_running)
+		uap->im = UART011_RTIM;
+	else
+		uap->im = UART011_RXIM | UART011_RTIM;
 	writew(uap->im, uap->port.membase + UART011_IMSC);
 	spin_unlock_irq(&uap->port.lock);
 
@@ -436,6 +1259,8 @@ static void pl011_shutdown(struct uart_port *port)
 	writew(0xffff, uap->port.membase + UART011_ICR);
 	spin_unlock_irq(&uap->port.lock);
 
+	pl011_dma_shutdown(uap);
+
 	/*
 	 * Free the interrupt
 	 */
@@ -496,7 +1321,7 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
 		if (!(termios->c_cflag & PARODD))
 			lcr_h |= UART01x_LCRH_EPS;
 	}
-	if (port->fifosize > 1)
+	if (uap->fifosize > 1)
 		lcr_h |= UART01x_LCRH_FEN;
 
 	spin_lock_irqsave(&port->lock, flags);
@@ -809,6 +1634,8 @@ static int pl011_probe(struct amba_device *dev, struct amba_id *id)
 	uap->port.ops = &amba_pl011_pops;
 	uap->port.flags = UPF_BOOT_AUTOCONF;
 	uap->port.line = i;
+	uap->fifosize = vendor->fifosize;
+	pl011_dma_probe(uap);
 
 	amba_ports[i] = uap;
 
@@ -817,6 +1644,7 @@ static int pl011_probe(struct amba_device *dev, struct amba_id *id)
 	if (ret) {
 		amba_set_drvdata(dev, NULL);
 		amba_ports[i] = NULL;
+		pl011_dma_remove(uap);
 		clk_put(uap->clk);
  unmap:
 		iounmap(base);
@@ -840,6 +1668,7 @@ static int pl011_remove(struct amba_device *dev)
 		if (amba_ports[i] == uap)
 			amba_ports[i] = NULL;
 
+	pl011_dma_remove(uap);
 	iounmap(uap->port.membase);
 	clk_put(uap->clk);
 	kfree(uap);
diff --git a/include/linux/amba/serial.h b/include/linux/amba/serial.h
index 5a5a7fd..2ce6a75 100644
--- a/include/linux/amba/serial.h
+++ b/include/linux/amba/serial.h
@@ -166,6 +166,12 @@ struct amba_device; /* in uncompress this is included but amba/bus.h is not */
 struct amba_pl010_data {
 	void (*set_mctrl)(struct amba_device *dev, void __iomem *base, unsigned int mctrl);
 };
+struct dma_chan;
+struct amba_pl011_data {
+	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+	void *dma_rx_param;
+	void *dma_tx_param;
+};
 #endif
 
 #endif
-- 
1.6.3.3



From linus.walleij at stericsson.com  Fri Jun 11 11:27:39 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:27:39 +0200
Subject: [PATCH 09/13] ARM: add PrimeCell generic DMA to MMCI/PL180 v7
Message-ID: <1276270059-1768-1-git-send-email-linus.walleij@stericsson.com>

This extends the MMCI/PL180 driver with generic DMA engine support
using the PrimeCell DMA engine interface.

Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 drivers/mmc/host/mmci.c   |  310 ++++++++++++++++++++++++++++++++++++++-------
 drivers/mmc/host/mmci.h   |   13 ++-
 include/linux/amba/mmci.h |   16 +++
 3 files changed, 294 insertions(+), 45 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 4917af9..42f2048 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -2,7 +2,7 @@
  *  linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
  *
  *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
- *  Copyright (C) 2010 ST-Ericsson AB.
+ *  Copyright (C) 2010 ST-Ericsson SA
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -23,8 +23,11 @@
 #include <linux/clk.h>
 #include <linux/scatterlist.h>
 #include <linux/gpio.h>
-#include <linux/amba/mmci.h>
 #include <linux/regulator/consumer.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/amba/dma.h>
+#include <linux/amba/mmci.h>
 
 #include <asm/cacheflush.h>
 #include <asm/div64.h>
@@ -98,12 +101,232 @@ static void mmci_stop_data(struct mmci_host *host)
 	host->data = NULL;
 }
 
+static void
+mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
+{
+	void __iomem *base = host->base;
+
+	dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
+		cmd->opcode, cmd->arg, cmd->flags);
+
+	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
+		writel(0, base + MMCICOMMAND);
+		udelay(1);
+	}
+
+	c |= cmd->opcode | MCI_CPSM_ENABLE;
+	if (cmd->flags & MMC_RSP_PRESENT) {
+		if (cmd->flags & MMC_RSP_136)
+			c |= MCI_CPSM_LONGRSP;
+		c |= MCI_CPSM_RESPONSE;
+	}
+	if (/*interrupt*/0)
+		c |= MCI_CPSM_INTERRUPT;
+
+	host->cmd = cmd;
+
+	writel(cmd->arg, base + MMCIARGUMENT);
+	writel(c, base + MMCICOMMAND);
+}
+
+/*
+ * All the DMA operation mode stuff goes inside this ifdef.
+ * This assumes that you have a generic DMA device interface,
+ * no custom DMA interfaces are supported.
+ */
+#ifdef CONFIG_DMADEVICES
+static void __devinit mmci_setup_dma(struct mmci_host *host)
+{
+	struct mmci_platform_data *plat = host->plat;
+	dma_cap_mask_t mask;
+
+	if (!plat || !plat->dma_filter) {
+		dev_err(mmc_dev(host->mmc), "no DMA platform data!\n");
+		return;
+	}
+
+	/* Try to acquire a generic DMA engine slave channel */
+	dma_cap_zero(mask);
+	dma_cap_set(DMA_SLAVE, mask);
+	/*
+	 * If only an RX channel is specified, the driver will
+	 * attempt to use it bidirectionally, however if it is
+	 * is specified but cannot be located, DMA will be disabled.
+	 */
+	host->dma_rx_channel = dma_request_channel(mask,
+						plat->dma_filter,
+						plat->dma_rx_param);
+	/* E.g if no DMA hardware is present */
+	if (!host->dma_rx_channel) {
+		dev_err(mmc_dev(host->mmc), "no RX DMA channel!\n");
+		return;
+	}
+	if (plat->dma_tx_param) {
+		host->dma_tx_channel = dma_request_channel(mask,
+							   plat->dma_filter,
+							   plat->dma_tx_param);
+		if (!host->dma_tx_channel) {
+			dma_release_channel(host->dma_rx_channel);
+			host->dma_rx_channel = NULL;
+		}
+	} else {
+		host->dma_tx_channel = host->dma_rx_channel;
+	}
+	host->enable_dma = true;
+	dev_info(mmc_dev(host->mmc), "use DMA channels DMA RX %s, DMA TX %s\n",
+		 dma_chan_name(host->dma_rx_channel),
+		 dma_chan_name(host->dma_tx_channel));
+}
+
+static void __devexit mmci_disable_dma(struct mmci_host *host)
+{
+	if (host->dma_rx_channel)
+		dma_release_channel(host->dma_rx_channel);
+	if (host->dma_tx_channel)
+		dma_release_channel(host->dma_tx_channel);
+	host->enable_dma = false;
+}
+
+static void mmci_dma_data_end(struct mmci_host *host)
+{
+	struct mmc_data *data = host->data;
+
+	dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+		     (data->flags & MMC_DATA_WRITE)
+		     ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+}
+
+static void mmci_dma_data_error(struct mmci_host *host)
+{
+	struct mmc_data *data = host->data;
+	struct dma_chan *chan;
+
+	dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
+	if (data->flags & MMC_DATA_READ)
+		chan = host->dma_rx_channel;
+	else
+		chan = host->dma_tx_channel;
+	dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+		     (data->flags & MMC_DATA_WRITE)
+		     ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+	chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
+}
+
+/*
+ * This one gets called repeatedly to copy data using
+ * DMA until there is no more data left to copy.
+ */
+static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
+{
+	struct amba_dma_channel_config rx_conf = {
+		.addr = host->phybase + MMCIFIFO,
+		.addr_width = 4,
+		.direction = DMA_FROM_DEVICE,
+		.maxburst = 8,
+	};
+	struct amba_dma_channel_config tx_conf = {
+		.addr = host->phybase + MMCIFIFO,
+		.addr_width = 4,
+		.direction = DMA_TO_DEVICE,
+		.maxburst = 8,
+	};
+	struct mmc_data *data = host->data;
+	enum dma_data_direction direction;
+	struct dma_chan *chan;
+	struct dma_async_tx_descriptor *desc;
+	struct scatterlist *sg;
+	unsigned int sglen;
+	dma_cookie_t cookie;
+	int i;
+
+	datactrl |= MCI_DPSM_DMAENABLE;
+	if (data->flags & MMC_DATA_READ) {
+		direction = DMA_FROM_DEVICE;
+		chan = host->dma_rx_channel;
+		chan->device->device_control(chan, DMA_CONFIG_AMBA,
+					     (unsigned long) &rx_conf);
+	} else {
+		direction = DMA_TO_DEVICE;
+		chan = host->dma_tx_channel;
+		chan->device->device_control(chan, DMA_CONFIG_AMBA,
+					     (unsigned long) &tx_conf);
+	}
+
+	/* Check for weird stuff in the sg list */
+	for_each_sg(data->sg, sg, data->sg_len, i) {
+		if (sg->offset & 3 || sg->length & 3)
+			return -EINVAL;
+	}
+
+	sglen = dma_map_sg(mmc_dev(host->mmc), data->sg,
+			   data->sg_len, direction);
+	if (sglen != data->sg_len)
+		goto unmap_exit;
+
+	desc = chan->device->device_prep_slave_sg(chan,
+					data->sg, data->sg_len, direction,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+	if (!desc)
+		goto unmap_exit;
+
+	host->dma_desc = desc;
+	dev_vdbg(mmc_dev(host->mmc), "Submit MMCI DMA job, sglen %d "
+		 "blksz %04x blks %04x flags %08x\n",
+		 sglen, data->blksz, data->blocks, data->flags);
+	cookie = desc->tx_submit(desc);
+
+	/* Here overloaded DMA controllers may fail */
+	if (dma_submit_error(cookie))
+		goto unmap_exit;
+	chan->device->device_issue_pending(chan);
+
+	/* Trigger the DMA transfer */
+	writel(datactrl, host->base + MMCIDATACTRL);
+	/*
+	 * Let the MMCI say when the data is ended and it's time
+	 * to fire next DMA request. When that happens, MMCI will
+	 * call mmci_data_end()
+	 */
+	writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
+	       host->base + MMCIMASK0);
+	return 0;
+
+unmap_exit:
+	chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
+	dma_unmap_sg(mmc_dev(host->mmc), data->sg, sglen, direction);
+	return -ENOMEM;
+}
+#else
+/* Blank functions if the DMA engine is not available */
+static inline void mmci_setup_dma(struct mmci_host *host)
+{
+}
+
+static inline void mmci_disable_dma(struct mmci_host *host)
+{
+}
+
+static inline void mmci_dma_data_end(struct mmci_host *host)
+{
+}
+
+static inline void mmci_dma_data_error(struct mmci_host *host)
+{
+}
+
+static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
+{
+	return -ENOSYS;
+}
+#endif
+
 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 {
 	unsigned int datactrl, timeout, irqmask;
 	unsigned long long clks;
 	void __iomem *base;
 	int blksz_bits;
+	int ret;
 
 	dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
 		data->blksz, data->blocks, data->flags);
@@ -112,8 +335,6 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 	host->size = data->blksz;
 	host->data_xfered = 0;
 
-	mmci_init_sg(host, data);
-
 	clks = (unsigned long long)data->timeout_ns * host->cclk;
 	do_div(clks, 1000000000UL);
 
@@ -127,13 +348,30 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 	BUG_ON(1 << blksz_bits != data->blksz);
 
 	datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
-	if (data->flags & MMC_DATA_READ) {
+
+	if (data->flags & MMC_DATA_READ)
 		datactrl |= MCI_DPSM_DIRECTION;
+
+	if (host->enable_dma) {
+		/*
+		 * Attempt to use DMA operation mode, if this
+		 * should fail, fall back to PIO mode
+		 */
+		ret = mmci_dma_start_data(host, datactrl);
+		if (!ret)
+			return;
+	}
+
+	/* IRQ mode, map the SG list for CPU reading/writing */
+	mmci_init_sg(host, data);
+
+	if (data->flags & MMC_DATA_READ) {
 		irqmask = MCI_RXFIFOHALFFULLMASK;
 
 		/*
-		 * If we have less than a FIFOSIZE of bytes to transfer,
-		 * trigger a PIO interrupt as soon as any data is available.
+		 * If we have less than a FIFOSIZE of bytes to
+		 * transfer, trigger a PIO interrupt as soon as any
+		 * data is available.
 		 */
 		if (host->size < MCI_FIFOSIZE)
 			irqmask |= MCI_RXDATAAVLBLMASK;
@@ -146,39 +384,12 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 	}
 
 	writel(datactrl, base + MMCIDATACTRL);
+	/* No interrupt when data ends */
 	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
 	writel(irqmask, base + MMCIMASK1);
 }
 
 static void
-mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
-{
-	void __iomem *base = host->base;
-
-	dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
-	    cmd->opcode, cmd->arg, cmd->flags);
-
-	if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
-		writel(0, base + MMCICOMMAND);
-		udelay(1);
-	}
-
-	c |= cmd->opcode | MCI_CPSM_ENABLE;
-	if (cmd->flags & MMC_RSP_PRESENT) {
-		if (cmd->flags & MMC_RSP_136)
-			c |= MCI_CPSM_LONGRSP;
-		c |= MCI_CPSM_RESPONSE;
-	}
-	if (/*interrupt*/0)
-		c |= MCI_CPSM_INTERRUPT;
-
-	host->cmd = cmd;
-
-	writel(cmd->arg, base + MMCIARGUMENT);
-	writel(c, base + MMCICOMMAND);
-}
-
-static void
 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
 	      unsigned int status)
 {
@@ -206,14 +417,19 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
 			data->error = -EIO;
 		status |= MCI_DATAEND;
 
-		/*
-		 * We hit an error condition.  Ensure that any data
-		 * partially written to a page is properly coherent.
-		 */
-		if (host->sg_len && data->flags & MMC_DATA_READ)
-			flush_dcache_page(sg_page(host->sg_ptr));
+		if (host->enable_dma) {
+			mmci_dma_data_error(host);
+		} else {
+			/*
+			 * We hit an error condition.  Ensure that any data
+			 * partially written to a page is properly coherent.
+			 */
+			if (host->sg_len && data->flags & MMC_DATA_READ)
+				flush_dcache_page(sg_page(host->sg_ptr));
+		}
 	}
 	if (status & MCI_DATAEND) {
+		mmci_dma_data_end(host);
 		mmci_stop_data(host);
 
 		if (!data->stop) {
@@ -623,6 +839,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 		dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
 			host->mclk);
 	}
+	host->phybase = dev->res.start;
 	host->base = ioremap(dev->res.start, resource_size(&dev->res));
 	if (!host->base) {
 		ret = -ENOMEM;
@@ -723,6 +940,8 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 			goto err_gpio_wp;
 	}
 
+	mmci_setup_dma(host);
+
 	ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
 	if (ret)
 		goto unmap;
@@ -738,9 +957,10 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 
 	mmc_add_host(mmc);
 
-	dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n",
-		mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
-		(unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
+	dev_info(&dev->dev, "%s: MMCI/PL180 manf %x rev %x cfg %02x at 0x%016llx\n",
+		 mmc_hostname(mmc), amba_manf(dev), amba_rev(dev), amba_config(dev),
+		 (unsigned long long)dev->res.start);
+	dev_info(&dev->dev, "IRQ %d, %d (pio)\n", dev->irq[0], dev->irq[1]);
 
 	init_timer(&host->timer);
 	host->timer.data = (unsigned long)host;
@@ -751,6 +971,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 	return 0;
 
  irq0_free:
+	mmci_disable_dma(host);
 	free_irq(dev->irq[0], host);
  unmap:
 	if (host->gpio_wp != -ENOSYS)
@@ -791,6 +1012,7 @@ static int __devexit mmci_remove(struct amba_device *dev)
 		writel(0, host->base + MMCICOMMAND);
 		writel(0, host->base + MMCIDATACTRL);
 
+		mmci_disable_dma(host);
 		free_irq(dev->irq[0], host);
 		free_irq(dev->irq[1], host);
 
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index d77062e..b45b286 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -139,14 +139,16 @@
  * The size of the FIFO in bytes.
  */
 #define MCI_FIFOSIZE	(16*4)
-	
 #define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
 
 #define NR_SG		16
 
 struct clk;
+struct dma_chan;
+struct dma_async_tx_descriptor;
 
 struct mmci_host {
+	phys_addr_t		phybase;
 	void __iomem		*base;
 	struct mmc_request	*mrq;
 	struct mmc_command	*cmd;
@@ -177,7 +179,16 @@ struct mmci_host {
 	struct scatterlist	*sg_ptr;
 	unsigned int		sg_off;
 	unsigned int		size;
+
 	struct regulator	*vcc;
+
+	/* DMA stuff */
+	bool			enable_dma;
+#ifdef CONFIG_DMADEVICES
+	struct dma_chan		*dma_rx_channel;
+	struct dma_chan		*dma_tx_channel;
+	struct dma_async_tx_descriptor *dma_desc;
+#endif
 };
 
 static inline void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h
index 7e466fe..f2ca60f 100644
--- a/include/linux/amba/mmci.h
+++ b/include/linux/amba/mmci.h
@@ -6,6 +6,8 @@
 
 #include <linux/mmc/host.h>
 
+/* Just some dummy forwarding */
+struct dma_chan;
 /**
  * struct mmci_platform_data - platform configuration for the MMCI
  * (also known as PL180) block.
@@ -25,6 +27,17 @@
  * @gpio_cd: read this GPIO pin to detect card insertion
  * @capabilities: the capabilities of the block as implemented in
  * this platform, signify anything MMC_CAP_* from mmc/host.h
+ * @dma_filter: function used to select an apropriate RX and TX
+ * DMA channel to be used for DMA, if and only if you're deploying the
+ * generic DMA engine
+ * @dma_rx_param: parameter passed to the DMA allocation
+ * filter in order to select an apropriate RX channel. If
+ * there is a bidirectional RX+TX channel, then just specify
+ * this and leave dma_tx_param set to NULL
+ * @dma_tx_param: parameter passed to the DMA allocation
+ * filter in order to select an apropriate TX channel. If this
+ * is NULL the driver will attempt to use the RX channel as a
+ * bidirectional channel
  */
 struct mmci_platform_data {
 	unsigned int f_max;
@@ -34,6 +47,9 @@ struct mmci_platform_data {
 	int	gpio_wp;
 	int	gpio_cd;
 	unsigned long capabilities;
+	bool (*dma_filter)(struct dma_chan *chan, void *filter_param);
+	void *dma_rx_param;
+	void *dma_tx_param;
 };
 
 #endif
-- 
1.6.3.3



From linus.walleij at stericsson.com  Fri Jun 11 11:27:47 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:27:47 +0200
Subject: [PATCH 10/13] ARM: config U300 PL180 PL011 PL022 for DMA v5
Message-ID: <1276270067-1820-1-git-send-email-linus.walleij@stericsson.com>

This will configure the platform data for the PL180, PL011 and
PL022 PrimeCells found in the U300 to use DMA with the generic
PrimeCell DMA engine.

Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/mach-u300/core.c |  173 ++++++++++++++++++++++++++++++++++++++++-----
 arch/arm/mach-u300/mmc.c  |   13 +++-
 arch/arm/mach-u300/spi.c  |   21 ++++--
 3 files changed, 181 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 5f34eb6..7f7e738 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
  * arch/arm/mach-u300/core.c
  *
  *
- * Copyright (C) 2007-2010 ST-Ericsson AB
+ * Copyright (C) 2007-2010 ST-Ericsson SA
  * License terms: GNU General Public License (GPL) version 2
  * Core platform support, IRQ handling and device definitions.
  * Author: Linus Walleij <linus.walleij at stericsson.com>
@@ -16,7 +16,9 @@
 #include <linux/device.h>
 #include <linux/mm.h>
 #include <linux/termios.h>
+#include <linux/dmaengine.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/serial.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <mach/coh901318.h>
@@ -92,10 +94,20 @@ void __init u300_map_io(void)
  * Declaration of devices found on the U300 board and
  * their respective memory locations.
  */
+
+static struct amba_pl011_data uart0_plat_data = {
+#ifdef CONFIG_COH901318
+	.dma_filter = coh901318_filter_id,
+	.dma_rx_param = (void *) U300_DMA_UART0_RX,
+	.dma_tx_param = (void *) U300_DMA_UART0_TX,
+#endif
+};
+
 static struct amba_device uart0_device = {
 	.dev = {
+		.coherent_dma_mask = ~0,
 		.init_name = "uart0", /* Slow device at 0x3000 offset */
-		.platform_data = NULL,
+		.platform_data = &uart0_plat_data,
 	},
 	.res = {
 		.start = U300_UART0_BASE,
@@ -107,10 +119,19 @@ static struct amba_device uart0_device = {
 
 /* The U335 have an additional UART1 on the APP CPU */
 #ifdef CONFIG_MACH_U300_BS335
+static struct amba_pl011_data uart1_plat_data = {
+#ifdef CONFIG_COH901318
+	.dma_filter = coh901318_filter_id,
+	.dma_rx_param = (void *) U300_DMA_UART1_RX,
+	.dma_tx_param = (void *) U300_DMA_UART1_TX,
+#endif
+};
+
 static struct amba_device uart1_device = {
 	.dev = {
+		.coherent_dma_mask = ~0,
 		.init_name = "uart1", /* Fast device at 0x7000 offset */
-		.platform_data = NULL,
+		.platform_data = &uart1_plat_data,
 	},
 	.res = {
 		.start = U300_UART1_BASE,
@@ -949,20 +970,21 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 		.priority_high = 0,
 		.dev_addr = U300_MSL_BASE + 6 * 0x40 + 0x220,
 	},
+	/*
+	 * Don't set up device address, burst count or size of src
+	 * or dst bus for this peripheral - handled by PrimeCell
+	 * DMA extension.
+	 */
 	{
 		.number = U300_DMA_MMCSD_RX_TX,
 		.name = "MMCSD RX TX",
 		.priority_high = 0,
-		.dev_addr =  U300_MMCSD_BASE + 0x080,
 		.param.config = COH901318_CX_CFG_CH_DISABLE |
 				COH901318_CX_CFG_LCR_DISABLE |
 				COH901318_CX_CFG_TC_IRQ_ENABLE |
 				COH901318_CX_CFG_BE_IRQ_ENABLE,
 		.param.ctrl_lli_chained = 0 |
 				COH901318_CX_CTRL_TC_ENABLE |
-				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 				COH901318_CX_CTRL_MASTER_MODE_M1RW |
 				COH901318_CX_CTRL_TCP_ENABLE |
 				COH901318_CX_CTRL_TC_IRQ_ENABLE |
@@ -971,9 +993,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 				COH901318_CX_CTRL_DDMA_LEGACY,
 		.param.ctrl_lli = 0 |
 				COH901318_CX_CTRL_TC_ENABLE |
-				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 				COH901318_CX_CTRL_MASTER_MODE_M1RW |
 				COH901318_CX_CTRL_TCP_ENABLE |
 				COH901318_CX_CTRL_TC_IRQ_ENABLE |
@@ -982,9 +1001,6 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 				COH901318_CX_CTRL_DDMA_LEGACY,
 		.param.ctrl_lli_last = 0 |
 				COH901318_CX_CTRL_TC_ENABLE |
-				COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
-				COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
-				COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
 				COH901318_CX_CTRL_MASTER_MODE_M1RW |
 				COH901318_CX_CTRL_TCP_DISABLE |
 				COH901318_CX_CTRL_TC_IRQ_ENABLE |
@@ -1003,15 +1019,76 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 		.name = "MSPRO RX",
 		.priority_high = 0,
 	},
+	/*
+	 * Don't set up device address, burst count or size of src
+	 * or dst bus for this peripheral - handled by PrimeCell
+	 * DMA extension.
+	 */
 	{
 		.number = U300_DMA_UART0_TX,
 		.name = "UART0 TX",
 		.priority_high = 0,
+		.param.config = COH901318_CX_CFG_CH_DISABLE |
+				COH901318_CX_CFG_LCR_DISABLE |
+				COH901318_CX_CFG_TC_IRQ_ENABLE |
+				COH901318_CX_CFG_BE_IRQ_ENABLE,
+		.param.ctrl_lli_chained = 0 |
+				COH901318_CX_CTRL_TC_ENABLE |
+				COH901318_CX_CTRL_MASTER_MODE_M1RW |
+				COH901318_CX_CTRL_TCP_ENABLE |
+				COH901318_CX_CTRL_TC_IRQ_DISABLE |
+				COH901318_CX_CTRL_HSP_ENABLE |
+				COH901318_CX_CTRL_HSS_DISABLE |
+				COH901318_CX_CTRL_DDMA_LEGACY,
+		.param.ctrl_lli = 0 |
+				COH901318_CX_CTRL_TC_ENABLE |
+				COH901318_CX_CTRL_MASTER_MODE_M1RW |
+				COH901318_CX_CTRL_TCP_ENABLE |
+				COH901318_CX_CTRL_TC_IRQ_ENABLE |
+				COH901318_CX_CTRL_HSP_ENABLE |
+				COH901318_CX_CTRL_HSS_DISABLE |
+				COH901318_CX_CTRL_DDMA_LEGACY,
+		.param.ctrl_lli_last = 0 |
+				COH901318_CX_CTRL_TC_ENABLE |
+				COH901318_CX_CTRL_MASTER_MODE_M1RW |
+				COH901318_CX_CTRL_TCP_ENABLE |
+				COH901318_CX_CTRL_TC_IRQ_ENABLE |
+				COH901318_CX_CTRL_HSP_ENABLE |
+				COH901318_CX_CTRL_HSS_DISABLE |
+				COH901318_CX_CTRL_DDMA_LEGACY,
 	},
 	{
 		.number = U300_DMA_UART0_RX,
 		.name = "UART0 RX",
 		.priority_high = 0,
+		.param.config = COH901318_CX_CFG_CH_DISABLE |
+				COH901318_CX_CFG_LCR_DISABLE |
+				COH901318_CX_CFG_TC_IRQ_ENABLE |
+				COH901318_CX_CFG_BE_IRQ_ENABLE,
+		.param.ctrl_lli_chained = 0 |
+				COH901318_CX_CTRL_TC_ENABLE |
+				COH901318_CX_CTRL_MASTER_MODE_M1RW |
+				COH901318_CX_CTRL_TCP_ENABLE |
+				COH901318_CX_CTRL_TC_IRQ_DISABLE |
+				COH901318_CX_CTRL_HSP_ENABLE |
+				COH901318_CX_CTRL_HSS_DISABLE |
+				COH901318_CX_CTRL_DDMA_LEGACY,
+		.param.ctrl_lli = 0 |
+				COH901318_CX_CTRL_TC_ENABLE |
+				COH901318_CX_CTRL_MASTER_MODE_M1RW |
+				COH901318_CX_CTRL_TCP_ENABLE |
+				COH901318_CX_CTRL_TC_IRQ_ENABLE |
+				COH901318_CX_CTRL_HSP_ENABLE |
+				COH901318_CX_CTRL_HSS_DISABLE |
+				COH901318_CX_CTRL_DDMA_LEGACY,
+		.param.ctrl_lli_last = 0 |
+				COH901318_CX_CTRL_TC_ENABLE |
+				COH901318_CX_CTRL_MASTER_MODE_M1RW |
+				COH901318_CX_CTRL_TCP_ENABLE |
+				COH901318_CX_CTRL_TC_IRQ_ENABLE |
+				COH901318_CX_CTRL_HSP_ENABLE |
+				COH901318_CX_CTRL_HSS_DISABLE |
+				COH901318_CX_CTRL_DDMA_LEGACY,
 	},
 	{
 		.number = U300_DMA_APEX_TX,
@@ -1241,15 +1318,77 @@ const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
 		.name = "XGAM PDI",
 		.priority_high = 0,
 	},
+	/*
+	 * Don't set up device address, burst count or size of src
+	 * or dst bus for this peripheral - handled by PrimeCell
+	 * DMA extension.
+	 */
 	{
 		.number = U300_DMA_SPI_TX,
 		.name = "SPI TX",
 		.priority_high = 0,
+		.param.config = COH901318_CX_CFG_CH_DISABLE |
+				COH901318_CX_CFG_LCR_DISABLE |
+				COH901318_CX_CFG_TC_IRQ_ENABLE |
+				COH901318_CX_CFG_BE_IRQ_ENABLE,
+		.param.ctrl_lli_chained = 0 |
+				COH901318_CX_CTRL_TC_ENABLE |
+				COH901318_CX_CTRL_MASTER_MODE_M1RW |
+				COH901318_CX_CTRL_TCP_DISABLE |
+				COH901318_CX_CTRL_TC_IRQ_DISABLE |
+				COH901318_CX_CTRL_HSP_ENABLE |
+				COH901318_CX_CTRL_HSS_DISABLE |
+				COH901318_CX_CTRL_DDMA_LEGACY,
+		.param.ctrl_lli = 0 |
+				COH901318_CX_CTRL_TC_ENABLE |
+				COH901318_CX_CTRL_MASTER_MODE_M1RW |
+				COH901318_CX_CTRL_TCP_DISABLE |
+				COH901318_CX_CTRL_TC_IRQ_ENABLE |
+				COH901318_CX_CTRL_HSP_ENABLE |
+				COH901318_CX_CTRL_HSS_DISABLE |
+				COH901318_CX_CTRL_DDMA_LEGACY,
+		.param.ctrl_lli_last = 0 |
+				COH901318_CX_CTRL_TC_ENABLE |
+				COH901318_CX_CTRL_MASTER_MODE_M1RW |
+				COH901318_CX_CTRL_TCP_DISABLE |
+				COH901318_CX_CTRL_TC_IRQ_ENABLE |
+				COH901318_CX_CTRL_HSP_ENABLE |
+				COH901318_CX_CTRL_HSS_DISABLE |
+				COH901318_CX_CTRL_DDMA_LEGACY,
 	},
 	{
 		.number = U300_DMA_SPI_RX,
 		.name = "SPI RX",
 		.priority_high = 0,
+		.param.config = COH901318_CX_CFG_CH_DISABLE |
+				COH901318_CX_CFG_LCR_DISABLE |
+				COH901318_CX_CFG_TC_IRQ_ENABLE |
+				COH901318_CX_CFG_BE_IRQ_ENABLE,
+		.param.ctrl_lli_chained = 0 |
+				COH901318_CX_CTRL_TC_ENABLE |
+				COH901318_CX_CTRL_MASTER_MODE_M1RW |
+				COH901318_CX_CTRL_TCP_DISABLE |
+				COH901318_CX_CTRL_TC_IRQ_DISABLE |
+				COH901318_CX_CTRL_HSP_ENABLE |
+				COH901318_CX_CTRL_HSS_DISABLE |
+				COH901318_CX_CTRL_DDMA_LEGACY,
+		.param.ctrl_lli = 0 |
+				COH901318_CX_CTRL_TC_ENABLE |
+				COH901318_CX_CTRL_MASTER_MODE_M1RW |
+				COH901318_CX_CTRL_TCP_DISABLE |
+				COH901318_CX_CTRL_TC_IRQ_ENABLE |
+				COH901318_CX_CTRL_HSP_ENABLE |
+				COH901318_CX_CTRL_HSS_DISABLE |
+				COH901318_CX_CTRL_DDMA_LEGACY,
+		.param.ctrl_lli_last = 0 |
+				COH901318_CX_CTRL_TC_ENABLE |
+				COH901318_CX_CTRL_MASTER_MODE_M1RW |
+				COH901318_CX_CTRL_TCP_DISABLE |
+				COH901318_CX_CTRL_TC_IRQ_ENABLE |
+				COH901318_CX_CTRL_HSP_ENABLE |
+				COH901318_CX_CTRL_HSS_DISABLE |
+				COH901318_CX_CTRL_DDMA_LEGACY,
+
 	},
 	{
 		.number = U300_DMA_GENERAL_PURPOSE_0,
@@ -1577,7 +1716,7 @@ static void __init u300_init_check_chip(void)
 #endif
 #ifdef CONFIG_MACH_U300_BS335
 	if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
-		printk(KERN_ERR "Platform configured for BS365 " \
+		printk(KERN_ERR "Platform configured for BS335 " \
 		       " with DB3350 but %s detected, expect problems!",
 		       chipname);
 	}
@@ -1654,12 +1793,12 @@ void __init u300_init_devices(void)
 	/* Register subdevices on the I2C buses */
 	u300_i2c_register_board_devices();
 
-	/* Register subdevices on the SPI bus */
-	u300_spi_register_board_devices();
-
 	/* Register the platform devices */
 	platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
 
+	/* Register subdevices on the SPI bus */
+	u300_spi_register_board_devices();
+
 #ifndef CONFIG_MACH_U300_SEMI_IS_SHARED
 	/*
 	 * Enable SEMI self refresh. Self-refresh of the SDRAM is entered when
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
index 88506d0..3acb710 100644
--- a/arch/arm/mach-u300/mmc.c
+++ b/arch/arm/mach-u300/mmc.c
@@ -3,11 +3,11 @@
  * arch/arm/mach-u300/mmc.c
  *
  *
- * Copyright (C) 2009 ST-Ericsson AB
+ * Copyright (C) 2009 ST-Ericsson SA
  * License terms: GNU General Public License (GPL) version 2
  *
  * Author: Linus Walleij <linus.walleij at stericsson.com>
- * Author: Johan Lundin <johan.lundin at stericsson.com>
+ * Author: Johan Lundin
  * Author: Jonas Aaberg <jonas.aberg at stericsson.com>
  */
 #include <linux/device.h>
@@ -19,8 +19,11 @@
 #include <linux/regulator/consumer.h>
 #include <linux/regulator/machine.h>
 #include <linux/gpio.h>
+#include <linux/dmaengine.h>
 #include <linux/amba/mmci.h>
 #include <linux/slab.h>
+#include <mach/coh901318.h>
+#include <mach/dma_channels.h>
 
 #include "mmc.h"
 #include "padmux.h"
@@ -108,6 +111,12 @@ int __devinit mmc_init(struct amba_device *adev)
 	mmci_card->mmc0_plat_data.gpio_cd = -1;
 	mmci_card->mmc0_plat_data.capabilities = MMC_CAP_MMC_HIGHSPEED |
 		MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
+#ifdef CONFIG_COH901318
+	mmci_card->mmc0_plat_data.dma_filter = coh901318_filter_id;
+	mmci_card->mmc0_plat_data.dma_rx_param =
+		(void *) U300_DMA_MMCSD_RX_TX;
+	/* Don't specify a TX channel, this RX channel is bidirectional */
+#endif
 
 	mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data;
 
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index f0e887b..243c999 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -11,6 +11,9 @@
 #include <linux/spi/spi.h>
 #include <linux/amba/pl022.h>
 #include <linux/err.h>
+#include <mach/coh901318.h>
+#include <mach/dma_channels.h>
+
 #include "padmux.h"
 
 /*
@@ -32,11 +35,8 @@ static void select_dummy_chip(u32 chipselect)
 struct pl022_config_chip dummy_chip_info = {
 	/* Nominally this is LOOPBACK_DISABLED, but this is our dummy chip! */
 	.lbm = LOOPBACK_ENABLED,
-	/*
-	 * available POLLING_TRANSFER and INTERRUPT_TRANSFER,
-	 * DMA_TRANSFER does not work
-	 */
-	.com_mode = INTERRUPT_TRANSFER,
+	/* available POLLING_TRANSFER, INTERRUPT_TRANSFER, DMA_TRANSFER */
+	.com_mode = DMA_TRANSFER,
 	.iface = SSP_INTERFACE_MOTOROLA_SPI,
 	/* We can only act as master but SSP_SLAVE is possible in theory */
 	.hierarchy = SSP_MASTER,
@@ -83,8 +83,6 @@ static struct spi_board_info u300_spi_devices[] = {
 static struct pl022_ssp_controller ssp_platform_data = {
 	/* If you have several SPI buses this varies, we have only bus 0 */
 	.bus_id = 0,
-	/* Set this to 1 when we think we got DMA working */
-	.enable_dma = 0,
 	/*
 	 * On the APP CPU GPIO 4, 5 and 6 are connected as generic
 	 * chip selects for SPI. (Same on U330, U335 and U365.)
@@ -92,6 +90,14 @@ static struct pl022_ssp_controller ssp_platform_data = {
 	 * and do padmuxing accordingly too.
 	 */
 	.num_chipselect = 3,
+#ifdef CONFIG_COH901318
+	.enable_dma = 1,
+	.dma_filter = coh901318_filter_id,
+	.dma_rx_param = (void *) U300_DMA_SPI_RX,
+	.dma_tx_param = (void *) U300_DMA_SPI_TX,
+#else
+	.enable_dma = 0,
+#endif
 };
 
 
@@ -117,6 +123,7 @@ void __init u300_spi_init(struct amba_device *adev)
 	}
 
 }
+
 void __init u300_spi_register_board_devices(void)
 {
 	/* Register any SPI devices */
-- 
1.6.3.3



From linus.walleij at stericsson.com  Fri Jun 11 11:27:55 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:27:55 +0200
Subject: [PATCH 11/13] ARM: config Ux500 PL011 PL022 for DMA v2
Message-ID: <1276270075-1874-1-git-send-email-linus.walleij@stericsson.com>

This will configure the platform data for the PL011 and PL022
PrimeCells found in the Ux500 to use DMA with the generic
PrimeCell DMA engine.

Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/mach-ux500/board-mop500.c   |   12 ---
 arch/arm/mach-ux500/devices-db8500.c |   92 ++++++++++++++++++++++-
 arch/arm/mach-ux500/devices.c        |  134 +++++++++++++++++++++++++++++++++-
 3 files changed, 220 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index bb8d7b7..526b2e2 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -60,16 +60,6 @@ static struct spi_board_info u8500_spi_devices[] = {
 	},
 };
 
-static struct pl022_ssp_controller ssp0_platform_data = {
-	.bus_id = 0,
-	/* pl022 not yet supports dma */
-	.enable_dma = 0,
-	/* on this platform, gpio 31,142,144,214 &
-	 * 224 are connected as chip selects
-	 */
-	.num_chipselect = 5,
-};
-
 #define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
 static struct nmk_i2c_controller u8500_i2c##id##_data = { \
 	/*				\
@@ -123,8 +113,6 @@ static void __init u8500_init_machine(void)
 	ux500_i2c2_device.dev.platform_data = &u8500_i2c2_data;
 	ux500_i2c3_device.dev.platform_data = &u8500_i2c3_data;
 
-	u8500_ssp0_device.dev.platform_data = &ssp0_platform_data;
-
 	/* Register the active AMBA devices on this board */
 	for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
 		amba_device_register(amba_devs[i], &iomem_resource);
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 8229034..a5c2aee 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -11,6 +11,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl022.h>
 
 #include <plat/ste_dma40.h>
 
@@ -55,10 +56,55 @@ struct platform_device u8500_gpio_devs[] = {
 	GPIO_DEVICE(8),
 };
 
+#ifdef CONFIG_STE_DMA40
+static struct stedma40_chan_cfg ssp0_dma_cfg_rx = {
+	.channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE|
+			 STEDMA40_LCHAN_SRC_LOG_DST_LOG|STEDMA40_NO_TIM_FOR_LINK|
+			 STEDMA40_LOW_PRIORITY_CHANNEL),
+	.dir = STEDMA40_PERIPH_TO_MEM,
+	.src_dev_type =  STEDMA40_DEV_SSP0_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg ssp0_dma_cfg_tx = {
+	.channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE|
+			 STEDMA40_LCHAN_SRC_LOG_DST_LOG|STEDMA40_NO_TIM_FOR_LINK|
+			 STEDMA40_LOW_PRIORITY_CHANNEL),
+	.dir = STEDMA40_MEM_TO_PERIPH,
+	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+	.dst_dev_type = STEDMA40_DEV_SSP0_TX,
+	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+#endif
+
+static struct pl022_ssp_controller ssp0_platform_data = {
+	.bus_id = 0,
+#ifdef CONFIG_STE_DMA40
+	.enable_dma = 1,
+	.dma_filter = stedma40_filter,
+	.dma_rx_param = &ssp0_dma_cfg_rx,
+	.dma_tx_param = &ssp0_dma_cfg_tx,
+#else
+	.enable_dma = 0,
+#endif
+	/* on this platform, gpio 31,142,144,214 &
+	 * 224 are connected as chip selects
+	 */
+	.num_chipselect = 5,
+};
+
 struct amba_device u8500_ssp0_device = {
 	.dev = {
 		.coherent_dma_mask = ~0,
 		.init_name = "ssp0",
+		.platform_data = &ssp0_platform_data,
 	},
 	.res = {
 		.start = U8500_SSP0_BASE,
@@ -171,12 +217,52 @@ struct stedma40_chan_cfg dma40_memcpy_conf_log = {
 
 /*
  * Mapping between destination event lines and physical device address.
- * The event line is tied to a device and therefor the address is constant.
+ * The event line is tied to a device and therefore the address is constant.
+ * When the address comes from a primecell it will be configured in runtime
+ * and we set the address to -1 as a placeholder.
  */
-static const dma_addr_t dma40_tx_map[STEDMA40_NR_DEV];
+static const dma_addr_t dma40_tx_map[STEDMA40_NR_DEV] = {
+	[STEDMA40_DEV_SPI0_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MMC0_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MMC1_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MMC2_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SSP0_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SSP1_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_UART2_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_UART1_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_UART0_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MM2_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MM0_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MM1_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SPI2_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SPI1_TX] = -1,  /* PrimeCell DMA */
+	[STEDMA40_DEV_SPI3_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MM3_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MM4_TX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MM5_TX] = -1, /* PrimeCell DMA */
+};
 
 /* Mapping between source event lines and physical device address */
-static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV];
+static const dma_addr_t dma40_rx_map[STEDMA40_NR_DEV] = {
+	[STEDMA40_DEV_SPI0_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MMC0_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MMC1_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MMC2_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SSP0_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SSP1_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_UART2_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_UART1_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_UART0_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MM2_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MM0_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MM1_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SPI2_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SPI1_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SPI3_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MM3_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MM4_RX] = -1, /* PrimeCell DMA */
+	[STEDMA40_DEV_SD_MM5_RX] = -1, /* PrimeCell DMA */
+};
 
 /* Reserved event lines for memcpy only */
 static int dma40_memcpy_event[] = {
diff --git a/arch/arm/mach-ux500/devices.c b/arch/arm/mach-ux500/devices.c
index 8a26889..f234461 100644
--- a/arch/arm/mach-ux500/devices.c
+++ b/arch/arm/mach-ux500/devices.c
@@ -10,10 +10,22 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/dma.h>
+#include <linux/amba/serial.h>
+
+#include <plat/ste_dma40.h>
 
 #include <mach/hardware.h>
 #include <mach/setup.h>
 
+/* Channel assignments are per-SoC */
+#ifdef CONFIG_UX500_SOC_DB8500
+#include "ste-dma40-db8500.h"
+#endif
+#if defined(CONFIG_UX500_SOC_DB5500) && defined(CONFIG_STE_DMA40)
+#error "You need to define the DMA channels for DB5500!"
+#endif
+
 #define __MEM_4K_RESOURCE(x) \
 	.res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
 
@@ -29,20 +41,136 @@ struct amba_device ux500_pl031_device = {
 	.irq = {IRQ_RTC_RTT, NO_IRQ},
 };
 
+#ifdef CONFIG_STE_DMA40
+static struct stedma40_chan_cfg uart0_dma_cfg_rx = {
+	.channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE|
+			 STEDMA40_LCHAN_SRC_LOG_DST_LOG|STEDMA40_NO_TIM_FOR_LINK|
+			 STEDMA40_LOW_PRIORITY_CHANNEL),
+	.dir = STEDMA40_PERIPH_TO_MEM,
+	.src_dev_type =  STEDMA40_DEV_UART0_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart0_dma_cfg_tx = {
+	.channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE|
+			 STEDMA40_LCHAN_SRC_LOG_DST_LOG|STEDMA40_NO_TIM_FOR_LINK|
+			 STEDMA40_LOW_PRIORITY_CHANNEL),
+	.dir = STEDMA40_MEM_TO_PERIPH,
+	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+	.dst_dev_type = STEDMA40_DEV_UART0_TX,
+	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart1_dma_cfg_rx = {
+	.channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE|
+			 STEDMA40_LCHAN_SRC_LOG_DST_LOG|STEDMA40_NO_TIM_FOR_LINK|
+			 STEDMA40_LOW_PRIORITY_CHANNEL),
+	.dir = STEDMA40_PERIPH_TO_MEM,
+	.src_dev_type =  STEDMA40_DEV_UART1_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart1_dma_cfg_tx = {
+	.channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE|
+			 STEDMA40_LCHAN_SRC_LOG_DST_LOG|STEDMA40_NO_TIM_FOR_LINK|
+			 STEDMA40_LOW_PRIORITY_CHANNEL),
+	.dir = STEDMA40_MEM_TO_PERIPH,
+	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+	.dst_dev_type = STEDMA40_DEV_UART1_TX,
+	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart2_dma_cfg_rx = {
+	.channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE|
+			 STEDMA40_LCHAN_SRC_LOG_DST_LOG|STEDMA40_NO_TIM_FOR_LINK|
+			 STEDMA40_LOW_PRIORITY_CHANNEL),
+	.dir = STEDMA40_PERIPH_TO_MEM,
+	.src_dev_type =  STEDMA40_DEV_UART2_RX,
+	.dst_dev_type = STEDMA40_DEV_DST_MEMORY,
+	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+
+static struct stedma40_chan_cfg uart2_dma_cfg_tx = {
+	.channel_type = (STEDMA40_CHANNEL_IN_LOG_MODE|
+			 STEDMA40_LCHAN_SRC_LOG_DST_LOG|STEDMA40_NO_TIM_FOR_LINK|
+			 STEDMA40_LOW_PRIORITY_CHANNEL),
+	.dir = STEDMA40_MEM_TO_PERIPH,
+	.src_dev_type = STEDMA40_DEV_SRC_MEMORY,
+	.dst_dev_type = STEDMA40_DEV_UART2_TX,
+	.src_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.src_info.data_width = STEDMA40_BYTE_WIDTH,
+	.dst_info.endianess = STEDMA40_LITTLE_ENDIAN,
+	.dst_info.data_width = STEDMA40_BYTE_WIDTH,
+};
+#endif
+
+static struct amba_pl011_data uart0_plat = {
+#ifdef CONFIG_STE_DMA40
+	.dma_filter = stedma40_filter,
+	.dma_rx_param = &uart0_dma_cfg_rx,
+	.dma_tx_param = &uart0_dma_cfg_tx,
+#endif
+};
+
+static struct amba_pl011_data uart1_plat = {
+#ifdef CONFIG_STE_DMA40
+	.dma_filter = stedma40_filter,
+	.dma_rx_param = &uart1_dma_cfg_rx,
+	.dma_tx_param = &uart1_dma_cfg_tx,
+#endif
+};
+
+static struct amba_pl011_data uart2_plat = {
+#ifdef CONFIG_STE_DMA40
+	.dma_filter = stedma40_filter,
+	.dma_rx_param = &uart2_dma_cfg_rx,
+	.dma_tx_param = &uart2_dma_cfg_tx,
+#endif
+};
+
 struct amba_device ux500_uart0_device = {
-	.dev = { .init_name = "uart0" },
+	.dev =  {
+		.coherent_dma_mask = ~0,
+		.init_name = "uart0",
+		.platform_data = &uart0_plat,
+	},
 	__MEM_4K_RESOURCE(UX500_UART0_BASE),
 	.irq = {IRQ_UART0, NO_IRQ},
 };
 
 struct amba_device ux500_uart1_device = {
-	.dev = { .init_name = "uart1" },
+	.dev =  {
+		.coherent_dma_mask = ~0,
+		.init_name = "uart1",
+		.platform_data = &uart1_plat,
+	},
 	__MEM_4K_RESOURCE(UX500_UART1_BASE),
 	.irq = {IRQ_UART1, NO_IRQ},
 };
 
 struct amba_device ux500_uart2_device = {
-	.dev = { .init_name = "uart2" },
+	.dev =  {
+		.coherent_dma_mask = ~0,
+		.init_name = "uart2",
+		.platform_data = &uart2_plat,
+	},
 	__MEM_4K_RESOURCE(UX500_UART2_BASE),
 	.irq = {IRQ_UART2, NO_IRQ},
 };
-- 
1.6.3.3



From linus.walleij at stericsson.com  Fri Jun 11 11:27:11 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:27:11 +0200
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 PrimeCells
Message-ID: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>

This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells
based on the implementation earlier submitted by Peter Pearse.
This is working like a charm for memcpy on the PB11MPCore, but
slave DMA to devices is still not working.

This DMA controller is used in mostly unmodified form in the ARM
RealView and Versatile platforms, in the ST-Ericsson Nomadik, and
in the ST SPEAr platform.

It has been converted to use the header from the Samsung PL080
derivate instead of its own defintions, and can potentially support
several controllers in the same system.

Cc: Peter Pearse <peter.pearse at arm.com>
Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Alessandro Rubini <rubini at unipv.it>
Cc: Viresh Kumar <viresh.kumar at st.com>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/include/asm/hardware/pl080.h |    2 +
 drivers/dma/Kconfig                   |    9 +
 drivers/dma/Makefile                  |    1 +
 drivers/dma/amba-pl08x.c              | 1925 +++++++++++++++++++++++++++++++++
 include/linux/amba/pl08x.h            |  173 +++
 5 files changed, 2110 insertions(+), 0 deletions(-)
 create mode 100644 drivers/dma/amba-pl08x.c
 create mode 100644 include/linux/amba/pl08x.h

diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
index f70e1e9..f35b86e 100644
--- a/arch/arm/include/asm/hardware/pl080.h
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -68,6 +68,8 @@
 #define PL080_CONTROL_TC_IRQ_EN			(1 << 31)
 #define PL080_CONTROL_PROT_MASK			(0x7 << 28)
 #define PL080_CONTROL_PROT_SHIFT		(28)
+#define PL080_CONTROL_PROT_CACHE		(1 << 30)
+#define PL080_CONTROL_PROT_BUFF			(1 << 29)
 #define PL080_CONTROL_PROT_SYS			(1 << 28)
 #define PL080_CONTROL_DST_INCR			(1 << 27)
 #define PL080_CONTROL_SRC_INCR			(1 << 26)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 8344375..f4655c2 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -36,6 +36,15 @@ comment "DMA Devices"
 config ASYNC_TX_DISABLE_CHANNEL_SWITCH
 	bool
 
+config AMBA_PL08X
+	bool "ARM PrimeCell PL080 or PL81 support"
+	depends on ARM_AMBA && EXPERIMENTAL
+	default y if ARCH_REALVIEW
+	select DMA_ENGINE
+	help
+	  Platform has a PL08x DMAC device
+	  which can provide DMA engine support
+
 config INTEL_IOATDMA
 	tristate "Intel I/OAT DMA support"
 	depends on PCI && X86
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 0fe5ebb..c51dbc8 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
 obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
 obj-$(CONFIG_PL330_DMA) += pl330.o
+obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
new file mode 100644
index 0000000..50531fa
--- /dev/null
+++ b/drivers/dma/amba-pl08x.c
@@ -0,0 +1,1925 @@
+/*
+ * Copyright (c) 2006 ARM Ltd.
+ * Copyright (c) 2010 ST-Ericsson SA
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ * The full GNU General Public License is iin this distribution in the
+ * file called COPYING.
+ *
+ * Documentation: ARM DDI 0196G == PL080
+ * Documentation: ARM DDI 0218E	== PL081
+ *
+ * PL080 & PL081 both have 16 sets of DMA signals. They differ in the number
+ * of channels which may be in use at once. Also PL080 has a dual bus master,
+ * PL081 has a single master.
+ *
+ * Memory to peripheral transfer may be visualized as
+ *	Get data from memory to DMAC
+ *	Until no data left
+ *		On burst request from peripheral
+ *			Destination burst from DMAC to peripheral
+ *			Clear burst request
+ *	Raise terminal count interrupt
+ *
+ * For peripherals with a FIFO:
+ * Source      burst size == half the depth of the peripheral FIFO
+ * Destination burst size == width of the peripheral FIFO
+ *
+ * (Bursts are irrelevant for mem to mem transfers - there are no burst
+ * signals)
+ *
+ * ASSUMES default (little) endianness for DMA transfers
+ *
+ * Only DMAC flow control is implemented
+ *
+ * Global TODO:
+ * - Break out common code from arch/arm/mach-s3c64xx and share
+ */
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/dmapool.h>
+#include <linux/amba/bus.h>
+#include <linux/dmaengine.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/dma.h>
+
+#include <asm/hardware/pl080.h>
+#include <asm/dma.h>
+#include <asm/mach/dma.h>
+#include <asm/atomic.h>
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+
+#define DRIVER_NAME	"pl08xdmac"
+
+/**
+ * struct vendor_data - vendor-specific config parameters
+ * for PL08x derivates
+ * @name: the name of this specific variant
+ * @channels: the number of channels available in this variant
+ */
+struct vendor_data {
+	char *name;
+	u8 channels;
+};
+
+/*
+ * PL08X private data structures
+ * An LLI struct - see pl08x TRM
+ * Note that next uses bit[0] as a bus bit,
+ * start & end do not - their bus bit info
+ * is in cctl
+ */
+struct lli {
+	dma_addr_t src;
+	dma_addr_t dst;
+	dma_addr_t next;
+	u32 cctl;
+};
+
+/**
+ * struct pl08x_driver_data - the local state holder for the PL08x
+ * @base: virtual memory base (remapped) for the PL08x
+ * @adev: the corresponding AMBA (PrimeCell) bus entry
+ * @vd: vendor data for this PL08x variant
+ * @pd: platform data passed in from the platform/machine
+ * @phy_chans: array of data for the physical channels
+ * @pool: a pool for the LLI descriptors
+ * @pool_ctr: counter of LLIs in the pool
+ * @max_num_llis: maximum number of LLIs, i.e. longest linked transfer
+ * length, submitted so far
+ * @lock: a spinlock for this struct
+ */
+struct pl08x_driver_data {
+	void __iomem *base;
+	struct amba_device *adev;
+	struct vendor_data *vd;
+	struct pl08x_platform_data *pd;
+	struct pl08x_phy_chan *phy_chans;
+	struct dma_pool *pool;
+	int pool_ctr;
+	int max_num_llis;
+	spinlock_t lock;
+};
+
+#ifdef MODULE
+
+# error "AMBA PL08X DMA CANNOT BE COMPILED AS A LOADABLE MODULE AT PRESENT"
+
+/*
+	a) Some devices might make use of DMA during boot
+	   (esp true for DMAENGINE implementation)
+	b) Memory allocation will need much more attention
+	   before load/unload can be supported
+ */
+#endif
+
+/*
+ * PL08X specific defines
+ */
+
+/*
+ * Memory boundaries: the manual for PL08x says that the controller
+ * cannot read past a 1KiB boundary, so these defines are used to
+ * create transfer LLIs that do not cross such boundaries.
+ */
+#define PL08X_BOUNDARY_SHIFT		(10)	/* 1KB 0x400 */
+#define PL08X_BOUNDARY_SIZE		(1 << PL08X_BOUNDARY_SHIFT)
+
+/* Minimum period between work queue runs */
+#define PL08X_WQ_PERIODMIN	20
+
+/* Size (bytes) of each LLI buffer allocated for one transfer */
+# define PL08X_LLI_TSFR_SIZE	0x2000
+
+/* Maximimum times we call dma_pool_alloc on this pool without freeing */
+#define PL08X_MAX_ALLOCS	0x40
+#define MAX_NUM_TSFR_LLIS	(PL08X_LLI_TSFR_SIZE/sizeof(struct lli))
+#define PL08X_ALIGN		8
+
+static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct pl08x_dma_chan, chan);
+}
+
+/*
+ * Physical channel handling
+ */
+
+/* Whether a certain channel is busy or not */
+static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
+{
+	unsigned int val;
+
+	val = readl(ch->base + PL080_CH_CONFIG);
+	return val & PL080_CONFIG_ACTIVE;
+}
+
+/*
+ * Set the initial DMA register values i.e. those for the first LLI
+ * The next lli pointer and the configuration interrupt bit have
+ * been set when the LLIs were constructed
+ */
+static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
+			    struct pl08x_phy_chan *ch)
+{
+	u32 val;
+
+	/* Wait for channel inactive */
+	val = readl(ch->base + PL080_CH_CONFIG);
+	while (val & PL080_CONFIG_ACTIVE)
+		val = readl(ch->base + PL080_CH_CONFIG);
+
+	dev_vdbg(&pl08x->adev->dev,
+		"WRITE channel %d: csrc=%08x, cdst=%08x, "
+		 "cctl=%08x, clli=%08x, ccfg=%08x\n",
+		ch->id,
+		ch->csrc,
+		ch->cdst,
+		ch->cctl,
+		ch->clli,
+		ch->ccfg);
+
+	writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR);
+	writel(ch->cdst, ch->base + PL080_CH_DST_ADDR);
+	writel(ch->clli, ch->base + PL080_CH_LLI);
+	writel(ch->cctl, ch->base + PL080_CH_CONTROL);
+	writel(ch->ccfg, ch->base + PL080_CH_CONFIG);
+	mb();
+}
+
+static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan)
+{
+	struct pl08x_channel_data *cd = plchan->cd;
+	struct pl08x_phy_chan *phychan = plchan->phychan;
+	struct pl08x_txd *txd = plchan->at;
+
+	/* Copy the basic control register calculated at transfer config */
+	phychan->csrc = txd->csrc;
+	phychan->cdst = txd->cdst;
+	phychan->clli = txd->clli;
+	phychan->cctl = txd->cctl;
+
+	/* Assign the signal to the proper control registers */
+	phychan->ccfg = cd->ccfg;
+	phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
+	phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
+	/* If it wasn't set from AMBA, ignore it */
+	if (txd->direction == DMA_TO_DEVICE)
+		/* Select signal as destination */
+		phychan->ccfg |=
+			(phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
+	else if (txd->direction == DMA_FROM_DEVICE)
+		/* Select signal as source */
+		phychan->ccfg |=
+			(phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
+	/* Always enable error interrupts */
+	phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
+	/* Always enable terminal interrupts */
+	phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
+}
+
+/*
+ * Enable the DMA channel
+ * Assumes all other configuration bits have been set
+ * as desired before this code is called
+ */
+static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x,
+				  struct pl08x_phy_chan *ch)
+{
+	u32 val;
+
+	/*
+	 * Do not access config register until channel shows as disabled
+	 */
+	while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id))
+		;
+
+	/*
+	 * Do not access config register until channel shows as inactive
+	 */
+	val = readl(ch->base + PL080_CH_CONFIG);
+	while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
+		val = readl(ch->base + PL080_CH_CONFIG);
+
+	writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG);
+	mb();
+}
+
+/*
+ * Overall DMAC remains enabled always.
+ *
+ * Disabling individual channels could lose data.
+ *
+ * Disable the peripheral DMA after disabling the DMAC
+ * in order to allow the DMAC FIFO to drain, and
+ * hence allow the channel to show inactive
+ *
+ */
+static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
+{
+	u32 val;
+
+	/* Set the HALT bit and wait for the FIFO to drain */
+	val = readl(ch->base + PL080_CH_CONFIG);
+	val |= PL080_CONFIG_HALT;
+	writel(val, ch->base + PL080_CH_CONFIG);
+
+	/* Wait for channel inactive */
+	val = readl(ch->base + PL080_CH_CONFIG);
+	while (val & PL080_CONFIG_ACTIVE)
+		val = readl(ch->base + PL080_CH_CONFIG);
+
+	mb();
+
+	return;
+}
+
+static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
+{
+	u32 val;
+
+	/* Clear the HALT bit */
+	val = readl(ch->base + PL080_CH_CONFIG);
+	val &= ~PL080_CONFIG_HALT;
+	writel(val, ch->base + PL080_CH_CONFIG);
+	mb();
+
+	return;
+}
+
+
+/* Stops the channel */
+static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
+{
+	u32 val;
+
+	pl08x_pause_phy_chan(ch);
+
+	/* Disable channel */
+	val = readl(ch->base + PL080_CH_CONFIG);
+	val &= ~PL080_CONFIG_ENABLE;
+	writel(val, ch->base + PL080_CH_CONFIG);
+	mb();
+
+	return;
+}
+
+static inline u32 get_bytes_in_cctl(u32 cctl)
+{
+	/* The source width defines the number of bytes */
+	u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
+
+	switch ((cctl >> 18) & 3) {
+	case PL080_WIDTH_8BIT:
+		break;
+	case PL080_WIDTH_16BIT:
+		bytes *= 2;
+		break;
+	case PL080_WIDTH_32BIT:
+		bytes *= 4;
+		break;
+	}
+	return bytes;
+}
+
+static u32 pl08x_getbytes_phy_chan(struct pl08x_phy_chan *ch)
+{
+	u32 bytes;
+
+	/* FIXME: follow all queued transactions */
+	bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
+	/* TODO: follow the LLI to see the sum summarum */
+	return bytes;
+}
+
+/*
+ * Allocate a physical channel for a virtual channel
+ */
+static struct pl08x_phy_chan *
+pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
+		      struct pl08x_dma_chan *virt_chan)
+{
+	struct pl08x_phy_chan *ch = NULL;
+	unsigned long flags;
+	int i;
+
+	/*
+	 * Try to locate a physical channel to be used for
+	 * this transfer. If all are taken return NULL and
+	 * the requester will have to cope by using some fallback
+	 * PIO mode or retrying later.
+	 */
+	for (i = 0; i < pl08x->vd->channels; i++) {
+		ch = &pl08x->phy_chans[i];
+
+		spin_lock_irqsave(&ch->lock, flags);
+
+		if (!ch->serving) {
+			ch->serving = virt_chan;
+			ch->signal = -1;
+			spin_unlock_irqrestore(&ch->lock, flags);
+			break;
+		}
+
+		spin_unlock_irqrestore(&ch->lock, flags);
+	}
+
+	if (i == pl08x->vd->channels) {
+		/* No physical channel available, cope with it */
+		return NULL;
+	}
+
+	return ch;
+}
+
+static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
+					 struct pl08x_phy_chan *ch)
+{
+	unsigned long flags;
+
+	/* Stop the channel and clear its interrupts */
+	pl08x_stop_phy_chan(ch);
+	writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
+	writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
+
+	/* Mark it as free */
+	spin_lock_irqsave(&ch->lock, flags);
+	ch->serving = NULL;
+	ch->signal = -1;
+	spin_unlock_irqrestore(&ch->lock, flags);
+}
+
+/*
+ * LLI handling
+ */
+
+static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
+{
+	switch (coded) {
+	case PL080_WIDTH_8BIT:
+		return 1;
+	case PL080_WIDTH_16BIT:
+		return 2;
+	case PL080_WIDTH_32BIT:
+		return 4;
+	default:
+		break;
+	}
+	BUG();
+	return 0;
+}
+
+static inline u32 pl08x_cctl_bits(u32 cctl,
+				  u8 srcwidth,
+				  u8 dstwidth,
+				  u32 tsize)
+{
+	u32 retbits = cctl;
+
+	/* Remove all src, dst and transfersize bits */
+	retbits &= ~PL080_CONTROL_DWIDTH_MASK;
+	retbits &= ~PL080_CONTROL_SWIDTH_MASK;
+	retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
+
+	/* Then set the bits according to the parameters */
+	switch(srcwidth) {
+	case 1:
+		retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
+		break;
+	case 2:
+		retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
+		break;
+	case 4:
+		retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	switch(dstwidth) {
+	case 1:
+		retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
+		break;
+	case 2:
+		retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
+		break;
+	case 4:
+		retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
+	return retbits;
+}
+
+/*
+ * Autoselect a master bus to use for the transfer
+ * this prefers the destination bus if both available
+ * if fixed address on one bus the other will be chosen
+ */
+void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
+	struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
+	struct pl08x_bus_data **sbus, u32 cctl)
+{
+	if (!cctl & PL080_CONTROL_DST_INCR) {
+		*mbus = src_bus;
+		*sbus = dst_bus;
+	} else if (!cctl & PL080_CONTROL_SRC_INCR) {
+		*mbus = dst_bus;
+		*sbus = src_bus;
+	} else {
+		if (dst_bus->buswidth == 4) {
+			*mbus = dst_bus;
+			*sbus = src_bus;
+		} else if (src_bus->buswidth == 4) {
+			*mbus = src_bus;
+			*sbus = dst_bus;
+		} else if (dst_bus->buswidth == 2) {
+			*mbus = dst_bus;
+			*sbus = src_bus;
+		} else if (src_bus->buswidth == 2) {
+			*mbus = src_bus;
+			*sbus = dst_bus;
+		} else {
+			/* src_bus->buswidth == 1 */
+			*mbus = dst_bus;
+			*sbus = src_bus;
+		}
+	}
+}
+
+/*
+ * Fills in one LLI for a certain transfer descriptor
+ * and advance the counter
+ */
+int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
+			    struct pl08x_txd *txd, int num_llis, int len,
+			    u32 cctl, u32 *remainder)
+{
+	struct lli *llis_va = (struct lli *)(txd->llis_va);
+	struct lli *llis_bus = (struct lli *)(txd->llis_bus);
+
+	BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
+
+	llis_va[num_llis].cctl		= cctl;
+	llis_va[num_llis].src		= txd->srcbus.addr;
+	llis_va[num_llis].dst		= txd->dstbus.addr;
+	/*
+	 * The bus bit is added to the next lli's address
+	 */
+	llis_va[num_llis].next =
+		(dma_addr_t)((u32) &(llis_bus[num_llis + 1])
+			     | pl08x->pd->bus_bit_lli);
+
+	if (cctl & PL080_CONTROL_SRC_INCR)
+		txd->srcbus.addr += len;
+	if (cctl & PL080_CONTROL_DST_INCR)
+		txd->dstbus.addr += len;
+
+	*remainder -= len;
+
+	return num_llis + 1;
+}
+
+/*
+ * Return number of bytes to fill to boundary, or len
+ */
+static inline u32 pl08x_pre_boundary(u32 addr, u32 len)
+{
+	u32 boundary;
+
+	boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
+		<< PL08X_BOUNDARY_SHIFT;
+
+	if (boundary < addr + len)
+		return boundary - addr;
+	else
+		return len;
+}
+
+/*
+ * This fills in the table of LLIs for the transfer descriptor
+ * Note that we assume we never have to change the burst sizes
+ * Return 0 for error
+ */
+static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
+			      struct pl08x_txd *txd)
+{
+	struct pl08x_channel_data *cd = txd->cd;
+	struct pl08x_bus_data *mbus, *sbus;
+	u32 remainder;
+	int num_llis = 0;
+	u32 cctl;
+	int max_bytes_per_lli;
+	int total_bytes = 0;
+	struct lli *llis_va;
+	struct lli *llis_bus;
+
+	if (!txd) {
+		dev_err(&pl08x->adev->dev, "%s no descriptor\n", __func__);
+		return 0;
+	}
+
+	txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_KERNEL,
+				      &txd->llis_bus);
+	if (!txd->llis_va) {
+		dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
+		return 0;
+	}
+
+	pl08x->pool_ctr++;
+
+	/*
+	 * Initialize bus values for this transfer
+	 * from the passed optimal values
+	 */
+	if (!cd) {
+		dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
+		return 0;
+	}
+
+	/* Get the default CCTL from the platform data */
+	cctl = cd->cctl;
+
+	/* Find maximum width of the source bus */
+	txd->srcbus.maxwidth =
+		pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
+				       PL080_CONTROL_SWIDTH_SHIFT);
+
+	/* Find maximum width of the destination bus */
+	txd->dstbus.maxwidth =
+		pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
+				       PL080_CONTROL_DWIDTH_SHIFT);
+
+	/* Set up the bus widths to the maximum */
+	txd->srcbus.buswidth = txd->srcbus.maxwidth;
+	txd->dstbus.buswidth = txd->dstbus.maxwidth;
+	dev_vdbg(&pl08x->adev->dev,
+		 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
+		 __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
+
+
+	/*
+	 * bytes transferred == tsize * MIN(buswidths), not max(buswidths)
+	 */
+	max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
+		PL080_CONTROL_TRANSFER_SIZE_MASK;
+	dev_vdbg(&pl08x->adev->dev,
+		 "%s max bytes per lli = %d\n",
+		 __func__, max_bytes_per_lli);
+
+	/* We need to count this down to zero */
+	remainder = txd->len;
+	dev_vdbg(&pl08x->adev->dev,
+		 "%s remainder = %d\n",
+		 __func__, remainder);
+
+	/*
+	 * Choose bus to align to
+	 * - prefers destination bus if both available
+	 * - if fixed address on one bus chooses other
+	 */
+	pl08x_choose_master_bus(&txd->srcbus,
+		&txd->dstbus, &mbus, &sbus, cctl);
+
+	if (txd->len < mbus->buswidth) {
+		/*
+		 * Less than a bus width available
+		 * - send as single bytes
+		 */
+		while (remainder) {
+			dev_vdbg(&pl08x->adev->dev,
+				 "%s single byte LLIs for a transfer of less than a bus width (remain %08x)\n",
+				 __func__, remainder);
+			cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
+			num_llis =
+				pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
+					cctl, &remainder);
+			total_bytes++;
+		}
+	} else {
+		/*
+		 *  Make one byte LLIs until master bus is aligned
+		 *  - slave will then be aligned also
+		 */
+		while ((mbus->addr) % (mbus->buswidth)) {
+			dev_vdbg(&pl08x->adev->dev,
+				"%s adjustment lli for less than bus width (remain %08x)\n",
+				 __func__, remainder);
+			cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
+			num_llis = pl08x_fill_lli_for_desc
+				(pl08x, txd, num_llis, 1, cctl, &remainder);
+			total_bytes++;
+		}
+
+		/*
+		 *  Master now aligned
+		 * - if slave is not then we must set its width down
+		 */
+		if (sbus->addr % sbus->buswidth) {
+			dev_dbg(&pl08x->adev->dev,
+				"%s set down bus width to one byte\n",
+				 __func__);
+
+			sbus->buswidth = 1;
+		}
+
+		/*
+		 * Make largest possible LLIs until less than one bus width left
+		 */
+		while (remainder > (mbus->buswidth - 1)) {
+			int lli_len, target_len;
+			int tsize;
+			int odd_bytes;
+
+			/*
+			 * If enough left try to send max possible,
+			 * otherwise try to send the remainder
+			 */
+			target_len = remainder;
+			if (remainder > max_bytes_per_lli)
+				target_len = max_bytes_per_lli;
+
+			/*
+			 * Set bus lengths for incrementing busses
+			 * to number of bytes which fill to next memory
+			 * boundary
+			 */
+			if (cctl & PL080_CONTROL_SRC_INCR)
+				txd->srcbus.fill_bytes =
+					pl08x_pre_boundary(
+						txd->srcbus.addr,
+						remainder);
+			else
+				txd->srcbus.fill_bytes =
+					max_bytes_per_lli;
+
+			if (cctl & PL080_CONTROL_DST_INCR)
+				txd->dstbus.fill_bytes =
+					pl08x_pre_boundary(
+						txd->dstbus.addr,
+						remainder);
+			else
+				txd->dstbus.fill_bytes =
+						max_bytes_per_lli;
+
+			/*
+			 *  Find the nearest
+			 */
+			lli_len	= min(txd->srcbus.fill_bytes,
+				txd->dstbus.fill_bytes);
+
+			BUG_ON(lli_len > remainder);
+
+			if (lli_len <= 0) {
+				dev_err(&pl08x->adev->dev,
+					"%s lli_len is %d, <= 0\n",
+						__func__, lli_len);
+				return 0;
+			}
+
+			if (lli_len == target_len) {
+				/*
+				 * Can send what we wanted
+				 */
+				/*
+				 *  Maintain alignment
+				 */
+				lli_len	= (lli_len/mbus->buswidth) *
+							mbus->buswidth;
+				odd_bytes = 0;
+			} else {
+				/*
+				 * So now we know how many bytes to transfer
+				 * to get to the nearest boundary
+				 * The next lli will past the boundary
+				 * - however we may be working to a boundary
+				 *   on the slave bus
+				 *   We need to ensure the master stays aligned
+				 */
+				odd_bytes = lli_len % mbus->buswidth;
+				/*
+				 * - and that we are working in multiples
+				 *   of the bus widths
+				 */
+				lli_len -= odd_bytes;
+
+			}
+
+			if (lli_len) {
+				/*
+				 * Check against minimum bus alignment:
+				 * Calculate actual transfer size in relation to bus
+				 * width an get a maximum remainder of the smallest
+				 * bus width - 1
+				 */
+				/* FIXME: use round_down()? */
+				tsize = lli_len / min(mbus->buswidth, sbus->buswidth);
+				lli_len	= tsize * min(mbus->buswidth, sbus->buswidth);
+
+				if (target_len != lli_len) {
+					dev_vdbg(&pl08x->adev->dev,
+					"%s can't send what we want. Desired %08x, lli of %08x bytes in txd of %08x\n",
+					__func__, target_len, lli_len, txd->len);
+				}
+
+				cctl = pl08x_cctl_bits(cctl,
+						       txd->srcbus.buswidth,
+						       txd->dstbus.buswidth,
+						       tsize);
+
+				dev_vdbg(&pl08x->adev->dev,
+					"%s fill lli with single lli chunk of size %08x (remainder %08x)\n",
+					__func__, lli_len, remainder);
+				num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
+						num_llis, lli_len, cctl,
+						&remainder);
+				total_bytes += lli_len;
+			}
+
+
+			if (odd_bytes) {
+				/*
+				 * Creep past the boundary,
+				 * maintaining master alignment
+				 */
+				int j;
+				for (j = 0; (j < mbus->buswidth)
+						&& (remainder); j++) {
+					cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
+					dev_vdbg(&pl08x->adev->dev,
+						"%s align with boundardy, single byte (remain %08x)\n",
+						__func__, remainder);
+					num_llis =
+						pl08x_fill_lli_for_desc(pl08x,
+							txd, num_llis, 1,
+							cctl, &remainder);
+					total_bytes++;
+				}
+			}
+		}
+
+		/*
+		 * Send any odd bytes
+		 */
+		if (remainder < 0) {
+			dev_err(&pl08x->adev->dev, "%s remainder not fitted 0x%08x bytes\n",
+					__func__, remainder);
+			return 0;
+		}
+
+		while (remainder) {
+			cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
+			dev_vdbg(&pl08x->adev->dev,
+				"%s align with boundardy, single odd byte (remain %d)\n",
+				__func__, remainder);
+			num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
+					1, cctl, &remainder);
+			total_bytes++;
+		}
+	}
+	if (total_bytes != txd->len) {
+		dev_err(&pl08x->adev->dev,
+			"%s size of encoded lli:s don't match total txd, transferred 0x%08x from size 0x%08x\n",
+			__func__, total_bytes, txd->len);
+		return 0;
+	}
+
+	if (num_llis >= MAX_NUM_TSFR_LLIS) {
+		dev_err(&pl08x->adev->dev,
+			"%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
+			__func__, (u32) MAX_NUM_TSFR_LLIS);
+		return 0;
+	}
+	/*
+	 * Decide whether this is a loop or a terminated transfer
+	 */
+	llis_va = ((struct lli *)txd->llis_va);
+	llis_bus = ((struct lli *)txd->llis_bus);
+
+	if (cd->circular_buffer) {
+		/*
+		 * Loop the circular buffer so that the next element
+		 * points back to the beginning of the LLI.
+		 */
+		llis_va[num_llis - 1].next =
+			(dma_addr_t)((unsigned int)&(llis_bus[0]) +
+						pl08x->pd->bus_bit_lli);
+	} else {
+		/*
+		 * On non-circular buffers, the final LLI terminates
+		 * the LLI.
+		 */
+		llis_va[num_llis - 1].next = 0;
+		/*
+		 * The final LLI element shall also fire an interrupt
+		 */
+		llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
+	}
+
+	/* Now store the channel register values */
+	txd->csrc = llis_va[0].src;
+	txd->cdst = llis_va[0].dst;
+	if (num_llis > 1)
+		txd->clli = llis_va[0].next;
+	else
+		txd->clli = 0;
+
+	txd->cctl = llis_va[0].cctl;
+	/* ccfg will be set at physical channel allocation time */
+
+	{
+		int i;
+
+		for (i = 0; i < num_llis; i++) {
+				dev_vdbg(&pl08x->adev->dev,
+					"lli %d @%p: csrc=%08x, cdst=%08x, cctl=%08x, clli=%08x\n",
+					i,
+					&llis_va[i],
+					llis_va[i].src,
+					llis_va[i].dst,
+					llis_va[i].cctl,
+					llis_va[i].next
+					);
+		}
+	}
+
+	/*
+	 * Reflects the longest lli submitted so far
+	 * TODO: Change to use /proc data
+	 */
+	if (pl08x->max_num_llis < num_llis)
+		pl08x->max_num_llis = num_llis;
+
+	return num_llis;
+}
+
+/* You should call this with the struct pl08x lock held */
+static void pl08x_free_txd(struct pl08x_driver_data *pl08x, struct pl08x_txd *txd)
+{
+	if (!txd)
+		dev_err(&pl08x->adev->dev,
+			"%s no descriptor to free\n",
+			__func__);
+
+	/* Free the LLI */
+	dma_pool_free(pl08x->pool, txd->llis_va,
+		      txd->llis_bus);
+
+	pl08x->pool_ctr--;
+
+	kfree(txd);
+}
+
+static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, struct list_head *txdlist)
+{
+	struct pl08x_txd *txdi = NULL;
+	struct pl08x_txd *next;
+
+	if (!list_empty(txdlist)) {
+		list_for_each_entry_safe(txdi,
+					 next, txdlist, node) {
+			list_del(&txdi->node);
+			pl08x_free_txd(pl08x, txdi);
+		}
+
+	}
+}
+
+static void pl08x_tasklet(unsigned long data)
+{
+	struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
+	struct pl08x_phy_chan *phychan = plchan->phychan;
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_txd *txdi = NULL;
+	struct pl08x_txd *next;
+	unsigned long flags;
+
+	if (!plchan)
+		BUG();
+
+	spin_lock_irqsave(&plchan->lock, flags);
+
+	if (plchan->at) {
+		dma_async_tx_callback callback =
+			plchan->at->tx.callback;
+		void *callback_param =
+			plchan->at->tx.callback_param;
+
+		/*
+		 * Update last completed
+		 */
+		plchan->lc =
+			(plchan->at->tx.cookie);
+
+		/*
+		 * Callback peripheral driver for p/m
+		 * to signal completion
+		 */
+		if (callback)
+			callback(callback_param);
+
+		/*
+		 * Device callbacks should NOT clear
+		 * the current transaction on the channel
+		 * Linus: sometimes they should?
+		 */
+		if (!plchan->at)
+			BUG();
+
+		/*
+		 * Free the descriptor if it's not for a device
+		 * using a circular buffer
+		 */
+		if (!plchan->at->cd->circular_buffer) {
+			pl08x_free_txd(pl08x, plchan->at);
+			plchan->at = NULL;
+		}
+		/*
+		 * else descriptor for circular
+		 * buffers only freed when
+		 * client has disabled dma
+		 */
+	}
+	/*
+	 * If a new descriptor is queued, set it up
+	 */
+	if (!list_empty(&plchan->desc_list)) {
+		list_for_each_entry_safe(txdi,
+					 next, &plchan->desc_list, node) {
+			list_del_init(&txdi->node);
+		}
+	} else {
+		/*
+		 * No more jobs, so free up the physical channel
+		 * Free any allocated signal on slave transfers too
+		 */
+		if ((phychan->signal >= 0) && pl08x->pd->put_signal)
+			pl08x->pd->put_signal(plchan);
+		pl08x_put_phy_channel(pl08x, phychan);
+		plchan->phychan = NULL;
+	}
+
+	spin_unlock_irqrestore(&plchan->lock, flags);
+}
+
+static irqreturn_t pl08x_irq(int irq, void *dev)
+{
+	struct pl08x_driver_data *pl08x = dev;
+	u32 mask = 0;
+	u32 val;
+	int i;
+
+	val = readl(pl08x->base + PL080_ERR_STATUS);
+	mb();
+	if (val) {
+		/*
+		 * An error interrupt (on one or more channels)
+		 */
+		dev_err(&pl08x->adev->dev,
+			"%s error interrupt, register value 0x%08x\n",
+				__func__, val);
+		/*
+		 * Simply clear ALL PL08X error interrupts,
+		 * regardless of channel and cause
+		 * FIXME: should be 0x00000003 on PL081 really.
+		 */
+		writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
+	}
+	val = readl(pl08x->base + PL080_INT_STATUS);
+	mb();
+	for (i = 0; i < pl08x->vd->channels; i++) {
+		if ((1 << i) & val) {
+			/* Locate physical channel */
+			struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
+			struct pl08x_dma_chan *plchan = phychan->serving;
+
+			/* Schedule tasklet on this channel */
+			tasklet_schedule(&plchan->tasklet);
+
+			mask |= (1 << i);
+		}
+	}
+	/*
+	 * Clear only the terminal interrupts on channels we processed
+	 */
+	writel(mask, pl08x->base + PL080_TC_CLEAR);
+	mb();
+
+	return mask ? IRQ_HANDLED : IRQ_NONE;
+}
+
+
+/*
+ * The DMA ENGINE API
+ */
+static int pl08x_alloc_chan_resources(struct dma_chan *chan)
+{
+	return 0;
+}
+
+static void pl08x_free_chan_resources(struct dma_chan *chan)
+{
+}
+
+/*
+ * This should be called with the channel plchan->lock held
+ */
+static int prep_phy_channel(struct pl08x_dma_chan *plchan,
+			    struct pl08x_txd *txd)
+{
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_phy_chan *ch;
+	int ret;
+
+	/* Check if we already have a channel */
+	if (plchan->phychan)
+		return 0;
+
+	ch = pl08x_get_phy_channel(pl08x, plchan);
+	if (!ch) {
+		/* No physical channel available, cope with it */
+		dev_info(&pl08x->adev->dev, "no physical channel "
+			"available for xfer on %s\n", plchan->name);
+		return -EBUSY;
+	}
+
+	/*
+	 * OK we have a physical channel: for memcpy() this is all we
+	 * need, but for slaves the physical siglals may be muxed!
+	 * Can the platform allow us to use this channel?
+	 */
+	if ((txd->direction == DMA_FROM_DEVICE || txd->direction == DMA_TO_DEVICE) &&
+	    pl08x->pd->get_signal) {
+		ret = pl08x->pd->get_signal(plchan);
+		if (ret < 0) {
+			dev_info(&pl08x->adev->dev,
+				"unable to use physical channel "
+				"%d for transfer on %s due to "
+				"platform restrictions\n",
+				ch->id, plchan->name);
+			/* Release physical channel & return */
+			pl08x_put_phy_channel(pl08x, ch);
+			return -EBUSY;
+		}
+		ch->signal = ret;
+	}
+
+	dev_dbg(&pl08x->adev->dev, "allocated physical "
+		 "channel %d and signal %d for xfer on %s\n",
+		 ch->id,
+		 ch->signal,
+		 plchan->name);
+
+	plchan->phychan = ch;
+
+	return 0;
+}
+
+/*
+ * First make the LLIs (could/should we do this earlier??)
+ * slave (m/p) - no queued transactions allowed at present
+ *	TODO allow queued transactions for non circular buffers
+ * Set up the channel active txd as inactive
+ * m2m	- transactions may be queued
+ * If no active txd on channel
+ *	set it up as inactive
+ *	- issue_pending() will set active & start
+ * else
+ *	queue it
+ * Lock channel since there may be (at least for m2m) multiple calls
+ *
+ * Return < 0 for error
+ */
+
+static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	int num_llis;
+	unsigned long flags;
+	struct pl08x_txd *txd = container_of(tx, struct pl08x_txd, tx);
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	int ret;
+
+	num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
+
+	if (num_llis) {
+		spin_lock_irqsave(&plchan->lock, flags);
+		atomic_inc(&plchan->last_issued);
+		tx->cookie = atomic_read(&plchan->last_issued);
+
+		if (plchan->at) {
+
+			/*
+			 * If this device not using a circular buffer then
+			 * queue this new descriptor for transfer.
+			 * The descriptor for a circular buffer continues
+			 * to be used until the channel is freed.
+			 */
+			if (txd->cd->circular_buffer)
+				dev_err(&pl08x->adev->dev,
+					"%s attempting to queue a circular buffer\n",
+						__func__);
+			else
+				list_add_tail(&txd->node,
+					&plchan->desc_list);
+
+		} else {
+			plchan->at = txd;
+			txd->active = false;
+		}
+
+		/*
+		 * See if we already have a physical channel allocated,
+		 * else this is the time to try to get one.
+		 */
+		ret = prep_phy_channel(plchan, txd);
+		if (ret) {
+			/* No physical channel available, cope with it */
+			spin_unlock_irqrestore(&plchan->lock, flags);
+			return -EBUSY;
+		}
+
+		spin_unlock_irqrestore(&plchan->lock, flags);
+
+		return tx->cookie;
+	} else
+		return -EINVAL;
+}
+
+static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
+		struct dma_chan *chan, unsigned long flags)
+{
+	struct dma_async_tx_descriptor *retval = NULL;
+
+	return retval;
+}
+
+/*
+ * Code accessing dma_async_is_complete() in a tight loop
+ * may give problems - could schedule where indicated.
+ * If slaves are relying on interrupts to signal completion this
+ * function must not be called with interrupts disabled
+ */
+static enum dma_status
+pl08x_dma_tx_status(struct dma_chan *chan,
+		    dma_cookie_t cookie,
+		    struct dma_tx_state *txstate)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	dma_cookie_t last_used;
+	dma_cookie_t last_complete;
+	enum dma_status ret;
+	u32 bytesleft = 0;
+
+	last_used = atomic_read(&plchan->last_issued);
+	last_complete = plchan->lc;
+
+	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	if (ret == DMA_SUCCESS) {
+		dma_set_tx_state(txstate, last_complete, last_used, 0);
+		return ret;
+	}
+
+	/*
+	 * schedule(); could be inserted here
+	 */
+
+	/*
+	 * This cookie not complete yet
+	 */
+	last_used = atomic_read(&plchan->last_issued);
+	last_complete = plchan->lc;
+
+	/* Get number of bytes left in the active transaction */
+	if (plchan->phychan)
+		bytesleft = pl08x_getbytes_phy_chan(plchan->phychan);
+
+	dma_set_tx_state(txstate, last_complete, last_used,
+			 bytesleft);
+
+	return DMA_IN_PROGRESS;
+	/* FIXME: make possible to return DMA_IN_PROGRESS */
+}
+
+/* PrimeCell DMA extension */
+struct burst_table {
+	int burstwords;
+	u32 reg;
+};
+
+static const struct burst_table burst_sizes[] = {
+	{
+		.burstwords = 256,
+		.reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 128,
+		.reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 64,
+		.reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 32,
+		.reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 16,
+		.reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 8,
+		.reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 4,
+		.reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 1,
+		.reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+};
+
+static void dma_set_ambaconfig(struct dma_chan *chan,
+			       struct amba_dma_channel_config *config)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_channel_data *cd = plchan->cd;
+	int maxburst = config->maxburst;
+	u32 cctl = 0;
+	/* Mask out all except src and dst channel */
+	u32 ccfg = cd->ccfg & 0x000003DEU;
+	int i = 0;
+
+	plchan->amba_addr = config->addr;
+	plchan->amba_direction = config->direction;
+
+	switch (config->addr_width) {
+	case 1:
+		cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
+			(PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
+		break;
+	case 2:
+		cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
+			(PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
+		break;
+	case 4:
+		cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
+			(PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
+		break;
+	default:
+		dev_err(&pl08x->adev->dev,
+			"bad ambaconfig: alien address width\n");
+		return;
+	}
+
+	/* Now decide on a maxburst */
+	while (i < ARRAY_SIZE(burst_sizes)) {
+		if (burst_sizes[i].burstwords <= maxburst)
+			break;
+		i++;
+	}
+	cctl |= burst_sizes[i].reg;
+
+	/* Transfer direction */
+	if (config->direction == DMA_TO_DEVICE) {
+		cctl |= PL080_CONTROL_SRC_INCR;
+		ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
+	} else if (config->direction == DMA_FROM_DEVICE) {
+		cctl |= PL080_CONTROL_DST_INCR;
+		ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
+	} else {
+		dev_err(&pl08x->adev->dev,
+			"bad ambaconfig: alien transfer direction\n");
+	}
+
+	/* Access the cell in privileged mode, non-bufferable, non-cacheable */
+	cctl &= ~PL080_CONTROL_PROT_MASK;
+	cctl |= PL080_CONTROL_PROT_SYS;
+
+	/* Modify the default channel data to fit PrimeCell request */
+	cd->cctl = cctl;
+	cd->ccfg = ccfg;
+
+	dev_info(&pl08x->adev->dev,
+		 "configured channel %s (%s) for %s, data width %d, "
+		 "maxburst %d words, LE, CCTL=%08x, CCFG=%08x\n",
+		 dma_chan_name(chan), plchan->name,
+		 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
+		 config->addr_width,
+		 config->maxburst,
+		 cctl, ccfg);
+}
+
+/*
+ * Slave transactions callback to the slave device to allow
+ * synchronization of slave DMA signals with the DMAC enable
+ */
+static void pl08x_issue_pending(struct dma_chan *chan)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	unsigned long flags;
+
+	spin_lock_irqsave(&plchan->lock, flags);
+	if (plchan->at) {
+		if (!plchan->at->active) {
+			/* Configure the physical channel for the active txd */
+			pl08x_config_phychan_for_txd(plchan);
+			pl08x_set_cregs(pl08x, plchan->phychan);
+			pl08x_enable_phy_chan(pl08x, plchan->phychan);
+			plchan->at->active = true;
+		}
+		/*
+		 * else skip active transfer
+		 * Calls with active txd occur for NET_DMA
+		 * - there can be queued descriptors
+		 */
+	}
+	spin_unlock_irqrestore(&plchan->lock, flags);
+	/*
+	 * else - calls with no active descriptor occur for NET_DMA
+	 */
+}
+
+/*
+ * Initialize a descriptor to be used by memcpy submit
+ */
+static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
+		struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
+		size_t len, unsigned long flags)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_txd *txd;
+
+	txd = kzalloc(sizeof(struct pl08x_txd), GFP_KERNEL);
+	if (!txd) {
+		dev_err(&pl08x->adev->dev,
+			"%s no memory for descriptor\n", __func__);
+		return NULL;
+	}
+
+	dma_async_tx_descriptor_init(&txd->tx, chan);
+	txd->direction = DMA_NONE;
+	txd->srcbus.addr = src;
+	txd->dstbus.addr = dest;
+
+	/* Set platform data for m2m */
+	txd->cd = &pl08x->pd->memcpy_channel;
+	/* Both to be incremented or the code will break */
+	txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
+	txd->tx.tx_submit = pl08x_tx_submit;
+	txd->tx.callback = NULL;
+	txd->tx.callback_param = NULL;
+	txd->len = len;
+
+	INIT_LIST_HEAD(&txd->node);
+
+	return &txd->tx;
+}
+
+struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
+		struct dma_chan *chan, struct scatterlist *sgl,
+		unsigned int sg_len, enum dma_data_direction direction,
+		unsigned long flags)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_txd *txd;
+
+	/*
+	 * Current implementation ASSUMES only one sg
+	 */
+	if (sg_len != 1) {
+		dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
+			__func__);
+		BUG();
+	}
+
+	dev_info(&pl08x->adev->dev, "%s prepare transaction from %s\n",
+		 __func__, plchan->name);
+
+	txd = kmalloc(sizeof(struct pl08x_txd), GFP_KERNEL);
+	if (!txd) {
+		dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
+		return NULL;
+	}
+
+	dma_async_tx_descriptor_init(&txd->tx, chan);
+
+	if (direction != plchan->amba_direction)
+		dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
+			"the direction configured for the PrimeCell\n",
+			__func__);
+
+	txd->direction = direction;
+	if (direction == DMA_TO_DEVICE) {
+		txd->srcbus.addr	= sgl->dma_address;
+		txd->dstbus.addr	= plchan->amba_addr;
+	} else if (direction == DMA_FROM_DEVICE) {
+		txd->srcbus.addr	= plchan->amba_addr;
+		txd->dstbus.addr	= sgl->dma_address;
+	} else {
+		dev_err(&pl08x->adev->dev,
+			"%s direction unsupported\n", __func__);
+		return NULL;
+	}
+	txd->cd = plchan->cd;
+	txd->tx.tx_submit = pl08x_tx_submit;
+	txd->tx.callback = NULL;
+	txd->tx.callback_param = NULL;
+	txd->len = sgl->length;
+
+	INIT_LIST_HEAD(&txd->node);
+
+	return &txd->tx;
+}
+
+static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+			 unsigned long arg)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	unsigned long flags;
+
+	/* Controls applicable to inactive channels */
+	if (cmd == DMA_CONFIG_AMBA) {
+		dma_set_ambaconfig(chan,
+				   (struct amba_dma_channel_config *)
+				   arg);
+		return 0;
+	}
+
+	/* Anything succeeds on non-existing transfers */
+	spin_lock_irqsave(&plchan->lock, flags);
+	if (!plchan->at || !plchan->phychan) {
+		spin_unlock_irqrestore(&plchan->lock, flags);
+		return 0;
+	}
+
+	switch (cmd) {
+	case DMA_TERMINATE_ALL:
+		pl08x_stop_phy_chan(plchan->phychan);
+
+		/* Mark physical channel as free and free any slave signal */
+		if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal)
+			pl08x->pd->put_signal(plchan);
+		pl08x_put_phy_channel(pl08x, plchan->phychan);
+		plchan->phychan = NULL;
+
+		/* Dequeue jobs and free LLIs */
+		pl08x_free_txd(pl08x, plchan->at);
+		pl08x_free_txd_list(pl08x, &plchan->desc_list);
+
+		spin_unlock_irqrestore(&plchan->lock, flags);
+
+		return 0;
+	case DMA_PAUSE:
+		pl08x_pause_phy_chan(plchan->phychan);
+		spin_unlock_irqrestore(&plchan->lock, flags);
+		return 0;
+	case DMA_RESUME:
+		pl08x_resume_phy_chan(plchan->phychan);
+		spin_unlock_irqrestore(&plchan->lock, flags);
+		return 0;
+	default:
+		break;
+	}
+	spin_unlock_irqrestore(&plchan->lock, flags);
+
+	/* Unknown command */
+	return -ENXIO;
+}
+
+bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	char *name = chan_id;
+
+	/* Check that the channel is not taken! */
+	if (!strcmp(plchan->name, name))
+		return true;
+
+	return false;
+}
+
+struct dma_device dmac_memcpy = {
+	.device_alloc_chan_resources	= pl08x_alloc_chan_resources,
+	.device_free_chan_resources	= pl08x_free_chan_resources,
+	.device_prep_dma_memcpy		= pl08x_prep_dma_memcpy,
+	.device_prep_dma_xor		= NULL,
+	.device_prep_dma_memset		= NULL,
+	.device_prep_dma_interrupt	= pl08x_prep_dma_interrupt,
+	.device_tx_status		= pl08x_dma_tx_status,
+	.device_issue_pending		= pl08x_issue_pending,
+	.device_control			= pl08x_control,
+	/*
+	 * Align to 4-byte boundary
+	 * This makes the DMAtests fail with grace on PB1176
+	 * broken DMA hardware instead of locking everything
+	 * up.
+	 */
+	/* .copy_align			= 2, */
+};
+
+struct dma_device dmac_slave = {
+	.device_alloc_chan_resources	= pl08x_alloc_chan_resources,
+	.device_free_chan_resources	= pl08x_free_chan_resources,
+	.device_prep_dma_xor		= NULL,
+	.device_prep_dma_memset		= NULL,
+	.device_prep_dma_interrupt	= pl08x_prep_dma_interrupt,
+	.device_tx_status		= pl08x_dma_tx_status,
+	.device_issue_pending		= pl08x_issue_pending,
+	.device_prep_slave_sg		= pl08x_prep_slave_sg,
+	.device_control			= pl08x_control,
+};
+
+
+/*
+ * Just check that the device is there and active
+ * TODO: turn this bit on/off depending on the number of
+ * physical channels actually used, if it is zero... well
+ * shut it off.
+ */
+static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
+{
+	u32 val;
+
+	val = readl(pl08x->base + PL080_CONFIG);
+	val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
+	/* We implictly clear bit 1 and that means little-endian mode */
+	val |= PL080_CONFIG_ENABLE;
+	mb();
+	writel(val, pl08x->base + PL080_CONFIG);
+	mb();
+}
+
+/*
+ * Initialise the DMAC memcpy channels.
+ * Make a local wrapper to hold required data
+ */
+static int pl08x_dma_init_memcpy_channels(struct pl08x_driver_data *pl08x,
+						 struct dma_device *memdev)
+{
+	struct pl08x_dma_chan *chan;
+	int i;
+
+	INIT_LIST_HEAD(&memdev->channels);
+	/*
+	 * Register as many many memcpy as we have physical channels,
+	 * we won't always be able to use all but the code will have
+	 * to cope with that situation.
+	 */
+	for (i = 0; i < pl08x->vd->channels; i++) {
+		chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
+		if (!chan) {
+			dev_err(&pl08x->adev->dev,
+				"%s no memory for channel\n", __func__);
+			return -ENOMEM;
+		}
+
+		chan->host = pl08x;
+		chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
+		if (!chan->name) {
+			kfree(chan);
+			return -ENOMEM;
+		}
+		chan->cd = &pl08x->pd->memcpy_channel;
+		dev_info(&pl08x->adev->dev,
+			"initialize virtual memcpy channel \"%s\"\n",
+			chan->name);
+
+		chan->chan.device = memdev;
+		atomic_set(&chan->last_issued, 0);
+		chan->lc = atomic_read(&chan->last_issued);
+
+		spin_lock_init(&chan->lock);
+		INIT_LIST_HEAD(&chan->desc_list);
+		tasklet_init(&chan->tasklet, pl08x_tasklet,
+			     (unsigned long) chan);
+
+		list_add_tail(&chan->chan.device_node, &memdev->channels);
+	}
+	dev_info(&pl08x->adev->dev, "initialized %d virtual memcpy channels\n", i);
+	return i;
+}
+
+/*
+ * Initialise the DMAC slave channels.
+ * Make a local wrapper to hold required data
+ */
+static int pl08x_dma_init_slave_channels(struct pl08x_driver_data *pl08x,
+						struct dma_device *slave)
+{
+	struct pl08x_dma_chan *chan;
+	int i;
+
+	INIT_LIST_HEAD(&slave->channels);
+	for (i = 0; i < pl08x->pd->num_slave_channels; i++) {
+		chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
+		if (!chan) {
+			dev_err(&pl08x->adev->dev,
+				"%s no memory for channel\n", __func__);
+			return -ENOMEM;
+		}
+
+		chan->host = pl08x;
+		chan->name = pl08x->pd->slave_channels[i].bus_id;
+		chan->cd = &pl08x->pd->slave_channels[i];
+		dev_info(&pl08x->adev->dev,
+			"initialize virtual channel \"%s\"\n",
+			chan->name);
+
+		chan->chan.device = slave;
+		atomic_set(&chan->last_issued, 0);
+		chan->lc = atomic_read(&chan->last_issued);
+
+		spin_lock_init(&chan->lock);
+		INIT_LIST_HEAD(&chan->desc_list);
+		tasklet_init(&chan->tasklet, pl08x_tasklet,
+			     (unsigned long) chan);
+
+		list_add_tail(&chan->chan.device_node, &slave->channels);
+	}
+	dev_info(&pl08x->adev->dev, "initialized %d virtual slave channels\n", i);
+	return i;
+}
+
+static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
+{
+	struct pl08x_driver_data *pl08x;
+	struct vendor_data *vd = id->data;
+	int ret = 0;
+	int i;
+
+	ret = amba_request_regions(adev, NULL);
+	if (ret)
+		return ret;
+
+	/* Create the driver state holder */
+	pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
+	if (!pl08x) {
+		ret = -ENOMEM;
+		goto out_no_pl08x;
+	}
+
+	/* Assign useful pointers to the driver state */
+	pl08x->adev = adev;
+	pl08x->vd = vd;
+
+	/* A DMA memory pool for LLIs, align on 1-byte boundary */
+	pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
+			PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
+	if (!pl08x->pool) {
+		ret = -ENOMEM;
+		goto out_no_lli_pool;
+	}
+	pl08x->pool_ctr = 0;
+	pl08x->max_num_llis = 0;
+
+	spin_lock_init(&pl08x->lock);
+
+	pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
+	if (!pl08x->base) {
+		ret = -ENOMEM;
+		goto out_no_ioremap;
+	}
+
+	/* Turn on the PL08x */
+	pl08x_ensure_on(pl08x);
+
+	/*
+	 * Attach the interrupt handler
+	 */
+	writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
+	writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
+	mb();
+
+	ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
+			  vd->name, pl08x);
+	if (ret) {
+		dev_err(&adev->dev, "%s failed to request "
+			"interrupt %d\n",
+			__func__, adev->irq[0]);
+		goto out_no_irq;
+	}
+
+	/* Initialize physical channels */
+	pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
+			GFP_KERNEL);
+	if (!pl08x->phy_chans) {
+		dev_err(&adev->dev, "%s failed to allocate "
+			"physical channel holders\n",
+			__func__);
+		goto out_no_phychans;
+	}
+
+	for (i = 0; i < vd->channels; i++) {
+		struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
+
+		ch->id = i;
+		ch->base = pl08x->base + PL080_Cx_BASE(i);
+		spin_lock_init(&ch->lock);
+		ch->serving = NULL;
+		ch->signal = -1;
+		dev_info(&adev->dev,
+			 "physical channel %d is %s\n", i,
+			 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
+	}
+
+	/* Get the platform data */
+	pl08x->pd = (struct pl08x_platform_data *)(adev->dev.platform_data);
+
+	/* Set caps */
+	dma_cap_set(DMA_MEMCPY, dmac_memcpy.cap_mask);
+	dma_cap_set(DMA_SLAVE, dmac_slave.cap_mask);
+	dmac_memcpy.dev = &adev->dev;
+	dmac_slave.dev = &adev->dev;
+
+	/* Register memcpy channels */
+	ret = pl08x_dma_init_memcpy_channels(pl08x, &dmac_memcpy);
+	if (ret <= 0) {
+		dev_warn(&pl08x->adev->dev,
+			 "%s failed to enumerate memcpy channels - %d\n",
+			 __func__, ret);
+		goto out_no_memcpy;
+	}
+	dmac_memcpy.chancnt = ret;
+
+	/* Register slave channels */
+	ret = pl08x_dma_init_slave_channels(pl08x, &dmac_slave);
+	if (ret <= 0) {
+		dev_warn(&pl08x->adev->dev,
+			"%s failed to enumerate slave channels - %d\n",
+				__func__, ret);
+		goto out_no_slave;
+	}
+	dmac_slave.chancnt = ret;
+
+	ret = dma_async_device_register(&dmac_memcpy);
+	if (ret) {
+		dev_warn(&pl08x->adev->dev,
+			"%s failed to register memcpy as an async device - %d\n",
+			__func__, ret);
+		goto out_no_memcpy_reg;
+	}
+
+	ret = dma_async_device_register(&dmac_slave);
+	if (ret) {
+		dev_warn(&pl08x->adev->dev,
+			"%s failed to register slave as an async device - %d\n",
+			__func__, ret);
+		goto out_no_slave_reg;
+	}
+
+	amba_set_drvdata(adev, pl08x);
+	dev_info(&pl08x->adev->dev, "ARM(R) %s DMA block initialized @%08x\n",
+		vd->name, adev->res.start);
+	return 0;
+
+out_no_slave_reg:
+	dma_async_device_unregister(&dmac_memcpy);
+out_no_memcpy_reg:
+	/* FIXME: free slave channels */
+out_no_slave:
+	/* FIXME: free memcpy channels */
+out_no_memcpy:
+	kfree(pl08x->phy_chans);
+out_no_phychans:
+	free_irq(adev->irq[0], pl08x);
+out_no_irq:
+	iounmap(pl08x->base);
+out_no_ioremap:
+	dma_pool_destroy(pl08x->pool);
+out_no_lli_pool:
+	kfree(pl08x);
+out_no_pl08x:
+	amba_release_regions(adev);
+	return ret;
+}
+
+/* PL080 has 8 channels and the PL080 have just 2 */
+static struct vendor_data vendor_pl080 = {
+	.name = "PL080",
+	.channels = 8,
+};
+
+static struct vendor_data vendor_pl081 = {
+	.name = "PL081",
+	.channels = 2,
+};
+
+static struct amba_id pl08x_ids[] = {
+	/* PL080 */
+	{
+		.id	= 0x00041080,
+		.mask	= 0x000fffff,
+		.data	= &vendor_pl080,
+	},
+	/* PL081 */
+	{
+		.id	= 0x00041081,
+		.mask	= 0x000fffff,
+		.data	= &vendor_pl081,
+	},
+	/* Nomadik 8815 PL080 variant */
+	{
+		.id	= 0x00280880,
+		.mask	= 0x00ffffff,
+		.data	= &vendor_pl080,
+	},
+	{ 0, 0 },
+};
+
+static struct amba_driver pl08x_amba_driver = {
+	.drv.name	= DRIVER_NAME,
+	.id_table	= pl08x_ids,
+	.probe		= pl08x_probe,
+};
+
+static int __init pl08x_init(void)
+{
+	int retval;
+	retval = amba_driver_register(&pl08x_amba_driver);
+	if (retval)
+		printk(KERN_WARNING
+			"PL08X::pl08x_init() - failed to register as an amba device - %d\n",
+			retval);
+	return retval;
+}
+subsys_initcall(pl08x_init);
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
new file mode 100644
index 0000000..5f9b16f
--- /dev/null
+++ b/include/linux/amba/pl08x.h
@@ -0,0 +1,173 @@
+/*
+ *	linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
+ *
+ *	Copyright (C) 2005 ARM Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * pl08x information required by platform code
+ *
+ * Please credit ARM.com
+ * Documentation: ARM DDI 0196D
+ *
+ */
+
+#ifndef AMBA_PL08X_H
+#define AMBA_PL08X_H
+
+/* We need sizes of structs from this header */
+#include <linux/dmaengine.h>
+
+/**
+ * struct pl08x_channel_data - data structure to pass info between
+ * platform and PL08x driver regarding channel configuration
+ * @bus_id: name of this device channel, not just a device name since
+ * devices may have more than one channel e.g. "foo_tx"
+ * @min_signal: the minimum DMA signal number to be muxed in for this
+ * channel (for platforms supporting muxed signals). If you have
+ * static assignments, make sure this is set to the assigned signal
+ * number, PL08x have 16 possible signals in number 0 thru 15 so
+ * when these are not enough they often get muxed (in hardware)
+ * disabling simultaneous use of the same channel for two devices.
+ * @max_signal: the maximum DMA signal number to be muxed in for
+ * the channel. Set to the same as min_signal for
+ * devices with static assignments
+ * @muxval: a number usually used to poke into some mux regiser to
+ * mux in the signal to this channel
+ * @cctl_opt: default options for the channel control register
+ * @circular_buffer: whether the buffer passed in is circular and
+ * shall simply be looped round round (like a record baby round
+ * round round round)
+ */
+struct pl08x_channel_data {
+	char *bus_id;
+	int min_signal;
+	int max_signal;
+	u32 muxval;
+	unsigned int cctl; /* Turn me into u32? */
+	u32 ccfg;
+	bool circular_buffer;
+};
+
+/**
+ * struct pl08x_bus_data - information of source or destination
+ * busses for a transfer
+ * @addr: current address
+ * @maxwidth: the maximum width of a transfer on this bus
+ * @buswidth: the width of this bus in bytes: 1, 2 or 4
+ * @fill_bytes: bytes required to fill to the next bus memory
+ * boundary
+ */
+struct pl08x_bus_data {
+	dma_addr_t addr;
+	u8 maxwidth;
+	u8 buswidth;
+	u32 fill_bytes;
+};
+
+/**
+ * struct pl08x_phy_chan - holder for the physical channels
+ * @id: physical index to this channel
+ * @lock: a lock to use when altering an instance of this struct
+ * @signal: the physical signal (aka channel) serving this
+ * physical channel right now
+ * @serving: the virtual channel currently being served by this
+ * physical channel
+ */
+struct pl08x_phy_chan {
+	unsigned int id;
+	void __iomem *base;
+	spinlock_t lock;
+	int signal;
+	struct pl08x_dma_chan *serving;
+	u32 csrc;
+	u32 cdst;
+	u32 clli;
+	u32 cctl;
+	u32 ccfg;
+};
+
+/**
+ * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
+ * @llis_bus: DMA memory address (physical) start for the LLIs
+ * @llis_va: virtual memory address start for the LLIs
+ */
+struct pl08x_txd {
+	struct dma_async_tx_descriptor tx;
+	enum dma_data_direction	direction;
+	struct pl08x_bus_data srcbus;
+	struct pl08x_bus_data dstbus;
+	int len;
+	dma_addr_t llis_bus;
+	void *llis_va;
+	struct list_head node;
+	struct pl08x_channel_data *cd;
+	bool active;
+	/* Settings to be put into the physical channel when we submit this txd */
+	u32 csrc;
+	u32 cdst;
+	u32 clli;
+	u32 cctl;
+};
+
+/**
+ * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
+ * @chan: wrappped abstract channel
+ * @phychan: the physical channel utilized by this channel, if there is one
+ * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
+ * @name: name of channel
+ * @cd: channel platform data
+ * @amba_addr: address for RX/TX according to the PrimeCell config
+ * @amba_direction: current direction of this channel according to
+ * @lc: last completed transaction on this channel
+ * @desc_list: queued transactions pending on this channel
+ * @at: active transaction on this channel
+ * @lock: a lock for this channel data
+ * @host: a pointer to the host (internal use)
+ */
+struct pl08x_dma_chan {
+	struct dma_chan chan;
+	struct pl08x_phy_chan *phychan;
+	struct tasklet_struct tasklet;
+	char *name;
+	struct pl08x_channel_data *cd;
+	dma_addr_t amba_addr;
+	enum dma_data_direction	amba_direction;
+	atomic_t last_issued;
+	dma_cookie_t lc;
+	struct list_head desc_list;
+	struct pl08x_txd *at;
+	spinlock_t lock;
+	void *host;
+};
+
+/**
+ * struct pl08x_platform_data - the platform configuration for the
+ * PL08x PrimeCells.
+ * @slave_channels: the channels defined for the different devices on the
+ * platform, all inclusive, including multiplexed channels. The available
+ * physical channels will be multiplexed around these signals as they
+ * are requested, just enumerate all possible channels.
+ * @get_signal: request a physical signal to be used for a DMA
+ * transfer immediately: if there is some multiplexing or similar blocking
+ * the use of the channel the transfer can be denied by returning
+ * less than zero, else it returns the allocated signal number
+ * @put_signal: indicate to the platform that this physical signal is not
+ * running any DMA transfer and multiplexing can be recycled
+ * @bus_bit_lli: Bit[0] of the address indicated which AHB bus master the
+ * LLI addresses are on 0/1 Master 1/2.
+ */
+struct pl08x_platform_data {
+	struct pl08x_channel_data *slave_channels;
+	unsigned int num_slave_channels;
+	struct pl08x_channel_data memcpy_channel;
+	int (*get_signal)(struct pl08x_dma_chan *);
+	void (*put_signal)(struct pl08x_dma_chan *);
+	unsigned int bus_bit_lli:1;
+};
+
+bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
+
+#endif	/* AMBA_PL08X_H */
-- 
1.6.3.3



From linus.walleij at stericsson.com  Fri Jun 11 11:28:03 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:28:03 +0200
Subject: [PATCH 12/13] ARM: RFC: PL08x platform data for the ARM RealView
	platforms
Message-ID: <1276270083-1927-1-git-send-email-linus.walleij@stericsson.com>

This adds platform data for the RealViews, something here is
likely prohibiting the RealViews from doing proper DMA so I
need help to find out what.

Note that this will even activate DMA in the broken DMA controller
on the PB1176, so this will not be the final version. Sadly the
PB1176 is usually all I have available for testing.

Cc: Peter Pearse <peter.pearse at arm.com>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/mach-realview/core.c                      |  375 +++++++++++++++++++-
 arch/arm/mach-realview/core.h                      |    2 +
 arch/arm/mach-realview/include/mach/board-pb1176.h |    1 +
 arch/arm/mach-realview/include/mach/platform.h     |    2 +
 arch/arm/mach-realview/realview_eb.c               |    2 +-
 arch/arm/mach-realview/realview_pb1176.c           |    7 +-
 arch/arm/mach-realview/realview_pb11mp.c           |   33 ++-
 arch/arm/mach-realview/realview_pba8.c             |    2 +-
 arch/arm/mach-realview/realview_pbx.c              |    2 +-
 9 files changed, 418 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 595be19..41ceb9e 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -25,6 +25,8 @@
 #include <linux/interrupt.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/serial.h>
 #include <linux/io.h>
 #include <linux/smsc911x.h>
 #include <linux/ata_platform.h>
@@ -46,6 +48,7 @@
 #include <asm/mach/map.h>
 
 #include <asm/hardware/gic.h>
+#include <asm/hardware/pl080.h>
 
 #include <mach/clkdev.h>
 #include <mach/platform.h>
@@ -232,6 +235,19 @@ static unsigned int realview_mmc_status(struct device *dev)
 	struct amba_device *adev = container_of(dev, struct amba_device, dev);
 	u32 mask;
 
+	if (machine_is_realview_pb1176()) {
+		bool inserted = false;
+
+		/*
+		 * The PB1176 does not have the status register,
+		 * assume it is inserted at startup, then invert
+		 * for each call, assuming the call is done whenever
+		 * the card status changes.
+		 */
+		inserted = !inserted;
+		return inserted ? 0 : 1;
+	}
+
 	if (adev->res.start == REALVIEW_MMCI0_BASE)
 		mask = 1;
 	else
@@ -242,9 +258,14 @@ static unsigned int realview_mmc_status(struct device *dev)
 
 struct mmci_platform_data realview_mmc0_plat_data = {
 	.ocr_mask	= MMC_VDD_32_33|MMC_VDD_33_34,
-	.status		= realview_mmc_status,
+	.status		= realview_mmc_status, /* Not on the PB1176! */
 	.gpio_wp	= 17,
 	.gpio_cd	= 16,
+#ifdef CONFIG_AMBA_PL08X
+	.dma_filter = pl08x_filter_id,
+	.dma_rx_param = (void *) "mci0",
+	/* Don't specify a TX channel, this RX channel is bidirectional */
+#endif
 };
 
 struct mmci_platform_data realview_mmc1_plat_data = {
@@ -252,6 +273,11 @@ struct mmci_platform_data realview_mmc1_plat_data = {
 	.status		= realview_mmc_status,
 	.gpio_wp	= 19,
 	.gpio_cd	= 18,
+#ifdef CONFIG_AMBA_PL08X
+	.dma_filter = pl08x_filter_id,
+	.dma_rx_param = (void *) "mci1",
+	/* Don't specify a TX channel, this RX channel is bidirectional */
+#endif
 };
 
 /*
@@ -589,6 +615,352 @@ struct clcd_board clcd_plat_data = {
 	.remove		= realview_clcd_remove,
 };
 
+
+/*
+ * DMA config
+ */
+#ifdef CONFIG_AMBA_PL08X
+
+
+/* State of the big DMA mux */
+static u32 current_mux = 0x00;
+static u32 mux_users = 0x00;
+static spinlock_t current_mux_lock = SPIN_LOCK_UNLOCKED;
+
+static int pl081_get_signal(struct pl08x_dma_chan *ch)
+{
+	struct pl08x_channel_data *cd = ch->cd;
+	unsigned long flags;
+	u32 val;
+
+	printk(KERN_INFO "requesting DMA signal on channel %s\n", ch->name);
+
+	/* This one has statically assigned channels */
+	if (machine_is_realview_pb1176())
+		return cd->min_signal;
+
+	spin_lock_irqsave(&current_mux_lock, flags);
+	/*
+	 * We're on the same mux so fine, go ahead!
+	 */
+	if (cd->muxval == current_mux) {
+		mux_users ++;
+		spin_unlock_irqrestore(&current_mux_lock, flags);
+		/* We still have to write it since it's OFF  by default */
+		val = readl(__io_address(REALVIEW_SYS_DMAPSR));
+		val &= 0xFFFFFFC0U;
+		val |= current_mux;
+		val |= 0x80; /* That's how they do it on the Versatile */
+		writel(val, __io_address(REALVIEW_SYS_DMAPSR));
+		return cd->min_signal;
+	}
+	/*
+	 * If we're not on the same mux and there are already
+	 * users on the other mux setting, tough luck, the client
+	 * can come back and retry or give up and fall back to
+	 * PIO mode.
+	 */
+	if (mux_users) {
+		spin_unlock_irqrestore(&current_mux_lock, flags);
+		return -EBUSY;
+	}
+
+	/* Switch mux setting */
+	current_mux = cd->muxval;
+
+	val = readl(__io_address(REALVIEW_SYS_DMAPSR));
+	val &= 0xFFFFFFC0U;
+	val |= cd->muxval;
+	val |= 0x80; /* That's how they do it on the Versatile */
+	writel(val, __io_address(REALVIEW_SYS_DMAPSR));
+
+	printk(KERN_INFO "%s: muxing in %s in bank %d writing value "
+	       "%08x to register %08x\n",
+	       __func__, ch->name, cd->muxval,
+	       val, REALVIEW_SYS_DMAPSR);
+
+	spin_unlock_irqrestore(&current_mux_lock, flags);
+
+	return cd->min_signal;
+}
+
+static void pl081_put_signal(struct pl08x_dma_chan *ch)
+{
+	unsigned long flags;
+
+	printk(KERN_INFO "release DMA signal on channel %s\n", ch->name);
+
+	/* This one has statically assigned channels */
+	if (machine_is_realview_pb1176())
+		return;
+
+	spin_lock_irqsave(&current_mux_lock, flags);
+	mux_users--;
+	spin_unlock_irqrestore(&current_mux_lock, flags);
+}
+
+#define PRIMECELL_DEFAULT_CCTL (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT | \
+				PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT | \
+				PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+				PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+				PL080_CONTROL_PROT_SYS)
+
+/* The PB1176 has static channel assignments */
+struct pl08x_channel_data pb1176_chan_data[] = {
+	/* Muxed on signal bank 0 */
+	[0] = {
+		.bus_id = "aacirx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[1] = {
+		.bus_id = "aacitx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[2] = {
+		.bus_id = "mci0",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[3] = {
+		.bus_id = "uart4rx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[4] = {
+		.bus_id = "uart4tx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[5] = {
+		.bus_id = "scirx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[6] = {
+		.bus_id = "scitx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[7] = {
+		.bus_id = "usbdc",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[8] = {
+		.bus_id = "usbhc",
+		.min_signal = 8,
+		.max_signal = 8,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[9] = {
+		.bus_id = "pismo",
+		.min_signal = 9,
+		.max_signal = 9,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+};
+
+/* Muxed channels as found in most RealViews */
+struct pl08x_channel_data realview_chan_data[] = {
+	/* Muxed on signal bank 0 */
+	[0] = {
+		.bus_id = "usb0",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[1] = {
+		.bus_id = "usb1",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[2] = {
+		.bus_id = "t1dmac0",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[3] = {
+		.bus_id = "mci0",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[4] = {
+		.bus_id = "aacitx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[5] = {
+		.bus_id = "aacirx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[6] = {
+		.bus_id = "scirx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[7] = {
+		.bus_id = "scitx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	/* Muxed on signal bank 1 */
+	[8] = {
+		.bus_id = "ssprx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.muxval = 0x01,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[9] = {
+		.bus_id = "ssptx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.muxval = 0x01,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[10] = {
+		.bus_id = "uart2rx",
+		.min_signal = 2,
+		.max_signal = 2,
+		.muxval = 0x01,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[11] = {
+		.bus_id = "uart2tx",
+		.min_signal = 3,
+		.max_signal = 3,
+		.muxval = 0x01,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[12] = {
+		.bus_id = "uart1rx",
+		.min_signal = 4,
+		.max_signal = 4,
+		.muxval = 0x01,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[13] = {
+		.bus_id = "uart1tx",
+		.min_signal = 5,
+		.max_signal = 5,
+		.muxval = 0x01,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[14] = {
+		.bus_id = "uart0rx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.muxval = 0x01,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[15] = {
+		.bus_id = "uart0tx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.muxval = 0x01,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+};
+
+struct pl08x_platform_data pl081_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		/*
+		 * We pass in some optimal memcpy config, the
+		 * driver will augment it if need be. 256 byte
+		 * bursts and 32bit bus width.
+		 */
+		.cctl =
+		(PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT |	\
+		 PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT |	\
+		 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |	\
+		 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT |	\
+		 PL080_CONTROL_PROT_BUFF |				\
+		 PL080_CONTROL_PROT_CACHE |				\
+		 PL080_CONTROL_PROT_SYS),
+		/* Flow control: DMAC controls this */
+		.ccfg = PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	.get_signal = pl081_get_signal,
+	.put_signal = pl081_put_signal,
+	.bus_bit_lli = 0,
+};
+
+void __init pl081_fixup(void)
+{
+	if (machine_is_realview_pb1176()) {
+		pl081_plat_data.slave_channels = pb1176_chan_data;
+		pl081_plat_data.num_slave_channels = ARRAY_SIZE(pb1176_chan_data);
+	} else {
+		pl081_plat_data.slave_channels = realview_chan_data;
+		pl081_plat_data.num_slave_channels = ARRAY_SIZE(realview_chan_data);
+	}
+}
+
+#else
+struct pl08x_platform_data pl081_plat_data = {
+};
+
+void __init pl081_fixup(void)
+{
+}
+#endif
+
+
 #ifdef CONFIG_LEDS
 #define VA_LEDS_BASE (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
 
@@ -685,4 +1057,5 @@ void realview_fixup(struct machine_desc *mdesc, struct tag *tags, char **from,
 	meminfo->bank[0].size = SZ_256M;
 	meminfo->nr_banks = 1;
 #endif
+	pl081_fixup();
 }
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 781bca6..af8427f 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -53,12 +53,14 @@ extern struct platform_device realview_i2c_device;
 extern struct mmci_platform_data realview_mmc0_plat_data;
 extern struct mmci_platform_data realview_mmc1_plat_data;
 extern struct clcd_board clcd_plat_data;
+extern struct pl08x_platform_data pl081_plat_data;
 extern void __iomem *gic_cpu_base_addr;
 extern void __iomem *timer0_va_base;
 extern void __iomem *timer1_va_base;
 extern void __iomem *timer2_va_base;
 extern void __iomem *timer3_va_base;
 
+extern void pl081_fixup(void);
 extern void realview_leds_event(led_event_t ledevt);
 extern void realview_timer_init(unsigned int timer_irq);
 extern int realview_flash_register(struct resource *res, u32 num);
diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h
index 2f5ccb2..73f37b9 100644
--- a/arch/arm/mach-realview/include/mach/board-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/board-pb1176.h
@@ -26,6 +26,7 @@
 /*
  * Peripheral addresses
  */
+#define REALVIEW_PB1176_DMAC_BASE		0x10030000 /* DMAC */
 #define REALVIEW_PB1176_SCTL_BASE		0x10100000 /* System controller */
 #define REALVIEW_PB1176_SMC_BASE		0x10111000 /* SMC */
 #define REALVIEW_PB1176_DMC_BASE		0x10109000 /* DMC configuration */
diff --git a/arch/arm/mach-realview/include/mach/platform.h b/arch/arm/mach-realview/include/mach/platform.h
index 1b77a27..934c5c2 100644
--- a/arch/arm/mach-realview/include/mach/platform.h
+++ b/arch/arm/mach-realview/include/mach/platform.h
@@ -77,6 +77,7 @@
 #define REALVIEW_SYS_BOOTCS_OFFSET           0x58
 #define REALVIEW_SYS_24MHz_OFFSET            0x5C
 #define REALVIEW_SYS_MISC_OFFSET             0x60
+#define REALVIEW_SYS_DMAPSR_OFFSET           0x64
 #define REALVIEW_SYS_IOSEL_OFFSET            0x70
 #define REALVIEW_SYS_PROCID_OFFSET           0x84
 #define REALVIEW_SYS_TEST_OSC0_OFFSET        0xC0
@@ -111,6 +112,7 @@
 #define REALVIEW_SYS_BOOTCS                  (REALVIEW_SYS_BASE + REALVIEW_SYS_BOOTCS_OFFSET)
 #define REALVIEW_SYS_24MHz                   (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
 #define REALVIEW_SYS_MISC                    (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
+#define REALVIEW_SYS_DMAPSR                  (REALVIEW_SYS_BASE + REALVIEW_SYS_DMAPSR_OFFSET)
 #define REALVIEW_SYS_IOSEL                   (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
 #define REALVIEW_SYS_PROCID                  (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
 #define REALVIEW_SYS_TEST_OSC0               (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 422ccd7..87d43cb 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -201,7 +201,7 @@ AMBA_DEVICE(uart3, "fpga:uart3", EB_UART3, NULL);
 /* DevChip Primecells */
 AMBA_DEVICE(smc,   "dev:smc",   EB_SMC,   NULL);
 AMBA_DEVICE(clcd,  "dev:clcd",  EB_CLCD,  &clcd_plat_data);
-AMBA_DEVICE(dmac,  "dev:dmac",  DMAC,     NULL);
+AMBA_DEVICE(dmac,  "dev:dmac",  DMAC,     &pl081_plat_data);
 AMBA_DEVICE(sctl,  "dev:sctl",  SCTL,     NULL);
 AMBA_DEVICE(wdog,  "dev:wdog",  EB_WATCHDOG, NULL);
 AMBA_DEVICE(gpio0, "dev:gpio0", EB_GPIO0, &gpio0_plat_data);
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 96568eb..d190f1e 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -143,7 +143,7 @@ static struct pl061_platform_data gpio2_plat_data = {
 #define MPMC_DMA	{ 0, 0 }
 #define PB1176_CLCD_IRQ	{ IRQ_DC1176_CLCD, NO_IRQ }
 #define PB1176_CLCD_DMA	{ 0, 0 }
-#define DMAC_IRQ	{ IRQ_PB1176_DMAC, NO_IRQ }
+#define PB1176_DMAC_IRQ	{ IRQ_PB1176_DMAC, NO_IRQ }
 #define DMAC_DMA	{ 0, 0 }
 #define SCTL_IRQ	{ NO_IRQ, NO_IRQ }
 #define SCTL_DMA	{ 0, 0 }
@@ -191,10 +191,10 @@ AMBA_DEVICE(ssp0,	"dev:ssp0",	PB1176_SSP,	NULL);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,	"issp:clcd",	PB1176_CLCD,	&clcd_plat_data);
-//AMBA_DEVICE(dmac,	"issp:dmac",	PB1176_DMAC,	NULL);
+AMBA_DEVICE(dmac,	"issp:dmac",	PB1176_DMAC,	&pl081_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
-//	&dmac_device,
+	&dmac_device,
 	&uart0_device,
 	&uart1_device,
 	&uart2_device,
@@ -320,6 +320,7 @@ static void realview_pb1176_fixup(struct machine_desc *mdesc,
 	meminfo->bank[0].start = 0;
 	meminfo->bank[0].size = SZ_128M;
 	meminfo->nr_banks = 1;
+	pl081_fixup();
 }
 
 static void __init realview_pb1176_init(void)
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 7fbefbb..813026a 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -25,6 +25,8 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/serial.h>
+#include <linux/amba/pl08x.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -123,6 +125,30 @@ static struct pl061_platform_data gpio2_plat_data = {
 	.irq_base	= -1,
 };
 
+static struct amba_pl011_data uart0_plat_data = {
+#ifdef CONFIG_AMBA_PL08X
+	.dma_filter = pl08x_filter_id,
+	.dma_rx_param = (void *) "uart0rx",
+	.dma_tx_param = (void *) "uart0tx",
+#endif
+};
+
+static struct amba_pl011_data uart1_plat_data = {
+#ifdef CONFIG_AMBA_PL08X
+	.dma_filter = pl08x_filter_id,
+	.dma_rx_param = (void *) "uart1rx",
+	.dma_tx_param = (void *) "uart1tx",
+#endif
+};
+
+static struct amba_pl011_data uart2_plat_data = {
+#ifdef CONFIG_AMBA_PL08X
+	.dma_filter = pl08x_filter_id,
+	.dma_rx_param = (void *) "uart2rx",
+	.dma_tx_param = (void *) "uart2tx",
+#endif
+};
+
 /*
  * RealView PB11MPCore AMBA devices
  */
@@ -189,11 +215,16 @@ AMBA_DEVICE(sci0,	"dev:sci0",	SCI,		NULL);
 AMBA_DEVICE(uart0,	"dev:uart0",	PB11MP_UART0,	NULL);
 AMBA_DEVICE(uart1,	"dev:uart1",	PB11MP_UART1,	NULL);
 AMBA_DEVICE(uart2,	"dev:uart2",	PB11MP_UART2,	NULL);
+#if 0
+AMBA_DEVICE(uart0,	"dev:uart0",	PB11MP_UART0,	&uart0_plat_data);
+AMBA_DEVICE(uart1,	"dev:uart1",	PB11MP_UART1,	&uart1_plat_data);
+AMBA_DEVICE(uart2,	"dev:uart2",	PB11MP_UART2,	&uart2_plat_data);
+#endif
 AMBA_DEVICE(ssp0,	"dev:ssp0",	PB11MP_SSP,	NULL);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,	"issp:clcd",	PB11MP_CLCD,	&clcd_plat_data);
-AMBA_DEVICE(dmac,	"issp:dmac",	DMAC,		NULL);
+AMBA_DEVICE(dmac,	"issp:dmac",	DMAC,		&pl081_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
 	&dmac_device,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index d3c113b..366969f 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -183,7 +183,7 @@ AMBA_DEVICE(ssp0,	"dev:ssp0",	PBA8_SSP,	NULL);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,	"issp:clcd",	PBA8_CLCD,	&clcd_plat_data);
-AMBA_DEVICE(dmac,	"issp:dmac",	DMAC,		NULL);
+AMBA_DEVICE(dmac,	"issp:dmac",	DMAC,		&pl081_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
 	&dmac_device,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index a235ba3..ca16948 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -205,7 +205,7 @@ AMBA_DEVICE(ssp0,	"dev:ssp0",	PBX_SSP,	NULL);
 
 /* Primecells on the NEC ISSP chip */
 AMBA_DEVICE(clcd,	"issp:clcd",	PBX_CLCD,	&clcd_plat_data);
-AMBA_DEVICE(dmac,	"issp:dmac",	DMAC,		NULL);
+AMBA_DEVICE(dmac,	"issp:dmac",	DMAC,		&pl081_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
 	&dmac_device,
-- 
1.6.3.3



From linus.walleij at stericsson.com  Fri Jun 11 11:28:11 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Fri, 11 Jun 2010 17:28:11 +0200
Subject: [PATCH 13/13] ARM: RFC: PL08x platform data for the ARM Versatile
	platforms
Message-ID: <1276270091-1982-1-git-send-email-linus.walleij@stericsson.com>

This adds platform data for the Versatile. I have no such hardware
to test on but I'm implementing in the blue according to spec in
the hopes that someone will help me out in debugging and testing
it.

Cc: Peter Pearse <peter.pearse at arm.com>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/mach-versatile/core.c                  |  525 ++++++++++++++++++++++-
 arch/arm/mach-versatile/include/mach/platform.h |    6 +
 arch/arm/mach-versatile/versatile_pb.c          |   17 +-
 3 files changed, 543 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 3dff864..bc90434 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -28,6 +28,8 @@
 #include <linux/amba/clcd.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/serial.h>
+#include <linux/amba/pl08x.h>
 #include <linux/io.h>
 #include <linux/gfp.h>
 
@@ -38,6 +40,7 @@
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/icst.h>
 #include <asm/hardware/vic.h>
+#include <asm/hardware/pl080.h>
 #include <asm/mach-types.h>
 
 #include <asm/mach/arch.h>
@@ -352,6 +355,11 @@ static struct mmci_platform_data mmc0_plat_data = {
 	.status		= mmc_status,
 	.gpio_wp	= -1,
 	.gpio_cd	= -1,
+#ifdef CONFIG_AMBA_PL08X
+	.dma_filter = pl08x_filter_id,
+	.dma_rx_param = (void *) "mci0",
+	/* Don't specify a TX channel, this RX channel is bidirectional */
+#endif
 };
 
 /*
@@ -693,6 +701,490 @@ static struct clcd_board clcd_plat_data = {
 	.remove		= versatile_clcd_remove,
 };
 
+/*
+ * DMA config
+ * The DMA channel routing is static on the PA926EJ-S
+ * and dynamic on the PB926EJ-S using SYS_DMAPSR0..SYS_DMAPSR2
+ */
+#ifdef CONFIG_AMBA_PL08X
+
+struct pb926ejs_dma_signal {
+	unsigned int id;
+	struct pl08x_dma_chan *user;
+	u32 ctrlreg;
+};
+
+/*
+ * The three first channels on ARM926EJ-S are muxed,
+ * but to make things simple we enable all channels
+ * to be muxed, however most of the channels will just
+ * me muxed on top of themselves.
+ */
+static struct pb926ejs_dma_signal pl080_muxtab[] = {
+	[0] = {
+		.id = 0,
+		.ctrlreg = VERSATILE_SYS_DMAPSR0,
+	},
+	[1] = {
+		.id = 1,
+		.ctrlreg = VERSATILE_SYS_DMAPSR1,
+	},
+	[2] = {
+		.id = 2,
+		.ctrlreg = VERSATILE_SYS_DMAPSR2,
+	},
+	[3] = {
+		.id = 3,
+	},
+	[4] = {
+		.id = 4,
+	},
+	[5] = {
+		.id = 5,
+	},
+	[6] = {
+		.id = 6,
+	},
+	[7] = {
+		.id = 7,
+	},
+	[8] = {
+		.id = 8,
+	},
+	[9] = {
+		.id = 9,
+	},
+	[10] = {
+		.id = 10,
+	},
+	[11] = {
+		.id = 11,
+	},
+	[12] = {
+		.id = 12,
+	},
+	[13] = {
+		.id = 13,
+	},
+	[14] = {
+		.id = 14,
+	},
+	[15] = {
+		.id = 15,
+	},
+};
+
+/* This is a lock for the above muxing array */
+static spinlock_t muxlock = SPIN_LOCK_UNLOCKED;
+
+static int pl080_get_signal(struct pl08x_dma_chan *ch)
+{
+	struct pl08x_channel_data *cd = ch->cd;
+
+	printk(KERN_INFO "requesting DMA signal on channel %s\n", ch->name);
+
+	/*
+	 * The AB926EJ-S is simple - only static assignments
+	 * so the channel is already muxed in and ready to go.
+	 */
+	if (machine_is_versatile_ab())
+		return cd->min_signal;
+
+	/* The PB926EJ-S is hairier */
+	if (machine_is_versatile_pb()) {
+		unsigned long flags;
+		int i;
+
+		if (cd->min_signal > ARRAY_SIZE(pl080_muxtab) ||
+		    cd->max_signal > ARRAY_SIZE(pl080_muxtab) ||
+		    (cd->max_signal < cd->min_signal)) {
+			printk(KERN_ERR "%s: illegal muxing constraints for %s\n",
+			       __func__, ch->name);
+			return -EINVAL;
+		}
+		/* Try to find a signal to use */
+		spin_lock_irqsave(&muxlock, flags);
+		for (i = cd->min_signal; i <= cd->max_signal; i++) {
+			if (!pl080_muxtab[i].user) {
+				u32 val;
+
+				pl080_muxtab[i].user = ch;
+				/* If the channels need to be muxed in, mux them! */
+				if (pl080_muxtab[i].ctrlreg) {
+					val = readl(__io_address(pl080_muxtab[i].ctrlreg));
+					val &= 0xFFFFFF70U;
+					val |= 0x80; /* Turn on muxing */
+					val |= cd->muxval; /* Mux in the right peripheral */
+					writel(val, __io_address(pl080_muxtab[i].ctrlreg));
+					printk(KERN_INFO "%s: muxing in %s at channel %d writing value "
+					       "%08x to register %08x\n",
+					       __func__, ch->name, i,
+					       val, pl080_muxtab[i].ctrlreg);
+				}
+				spin_unlock_irqrestore(&muxlock, flags);
+				return pl080_muxtab[i].id;
+			}
+		}
+		spin_unlock_irqrestore(&muxlock, flags);
+	}
+
+	return -EBUSY;
+}
+
+static void pl080_put_signal(struct pl08x_dma_chan *ch)
+{
+	struct pl08x_channel_data *cd = ch->cd;
+	unsigned long flags;
+	int i;
+
+	printk(KERN_INFO "releasing DMA signal on channel %s\n", ch->name);
+	if (cd->min_signal > ARRAY_SIZE(pl080_muxtab) ||
+	    cd->max_signal > ARRAY_SIZE(pl080_muxtab) ||
+	    (cd->max_signal < cd->min_signal)) {
+		printk(KERN_INFO "%s: illegal muxing constraints for %s\n",
+		       __func__, ch->name);
+		return;
+	}
+	spin_lock_irqsave(&muxlock, flags);
+	for (i = cd->min_signal; i <= cd->max_signal; i++) {
+		if (pl080_muxtab[i].user == ch) {
+			pl080_muxtab[i].user = NULL;
+			if (pl080_muxtab[i].ctrlreg) {
+				u32 val;
+
+				val = readl(__io_address(pl080_muxtab[i].ctrlreg));
+				val &= 0xFFFFFF70U; /* Disable, select no channel */
+				writel(val, __io_address(pl080_muxtab[i].ctrlreg));
+				printk(KERN_INFO "%s: muxing out %s at channel %d writing value "
+				       "%08x to register %08x\n",
+				       __func__, ch->name, i,
+				       val, pl080_muxtab[i].ctrlreg);
+			}
+			spin_unlock_irqrestore(&muxlock, flags);
+			return;
+		}
+	}
+	spin_unlock_irqrestore(&muxlock, flags);
+	printk(KERN_INFO "%s: unable to release muxing on channel %s\n",
+	       __func__, ch->name);
+}
+
+struct pl08x_platform_data pl080_plat_data = {
+	.memcpy_channel = {
+		.bus_id = "memcpy",
+		/*
+		 * We pass in some optimal memcpy config, the
+		 * driver will augment it if need be. 256 byte
+		 * bursts and 32bit bus width.
+		 */
+		.cctl =
+		(PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT |	\
+		 PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT |	\
+		 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |	\
+		 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT |	\
+		 PL080_CONTROL_PROT_BUFF |				\
+		 PL080_CONTROL_PROT_CACHE |				\
+		 PL080_CONTROL_PROT_SYS),
+		/* Flow control: DMAC controls this */
+		.ccfg = PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	.get_signal = pl080_get_signal,
+	.put_signal = pl080_put_signal,
+	.bus_bit_lli = 0,
+};
+
+#define PRIMECELL_DEFAULT_CCTL (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT | \
+				PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT | \
+				PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
+				PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
+				PL080_CONTROL_PROT_SYS)
+
+static struct pl08x_channel_data ab926ejs_chan_data[] = {
+	[0] = {
+		.bus_id = "aacirx",
+		.min_signal = 0,
+		.max_signal = 0,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[1] = {
+		.bus_id = "aacitx",
+		.min_signal = 1,
+		.max_signal = 1,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[2] = {
+		.bus_id = "mci0",
+		.min_signal = 2,
+		.max_signal = 2,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[3] = {
+		.bus_id = "reserved",
+		.min_signal = 3,
+		.max_signal = 3,
+	},
+	[4] = {
+		.bus_id = "reserved",
+		.min_signal = 4,
+		.max_signal = 4,
+	},
+	[5] = {
+		.bus_id = "reserved",
+		.min_signal = 5,
+		.max_signal = 5,
+	},
+	[6] = {
+		.bus_id = "scirx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[7] = {
+		.bus_id = "scitx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[8] = {
+		.bus_id = "ssprx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[9] = {
+		.bus_id = "ssptx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[10] = {
+		.bus_id = "uart2rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[11] = {
+		.bus_id = "uart2tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[12] = {
+		.bus_id = "uart1rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[13] = {
+		.bus_id = "uart1tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[14] = {
+		.bus_id = "uart0rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[15] = {
+		.bus_id = "uart0tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+};
+
+/* For the PB926EJ-S we define some extra virtual channels */
+static struct pl08x_channel_data pb926ejs_chan_data[] = {
+	[0] = {
+		/* Muxed on channel 0-3 */
+		.bus_id = "aacitx",
+		.min_signal = 0,
+		.max_signal = 2,
+		.muxval = 0x00,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[1] = {
+		/* Muxed on channel 0-3 */
+		.bus_id = "aacirx",
+		.min_signal = 0,
+		.max_signal = 2,
+		.muxval = 0x01,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[2] = {
+		/* Muxed on channel 0-3 */
+		.bus_id = "usba",
+		.min_signal = 0,
+		.max_signal = 2,
+		.muxval = 0x02,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[3] = {
+		/* Muxed on channel 0-3 */
+		.bus_id = "usbb",
+		.min_signal = 0,
+		.max_signal = 2,
+		.muxval = 0x03,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[4] = {
+		/* Muxed on channel 0-3 */
+		.bus_id = "mci0",
+		.min_signal = 0,
+		.max_signal = 2,
+		.muxval = 0x04,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[5] = {
+		/* Muxed on channel 0-3 */
+		.bus_id = "mci1",
+		.min_signal = 0,
+		.max_signal = 2,
+		.muxval = 0x05,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[6] = {
+		/* Muxed on channel 0-3 */
+		.bus_id = "uart3tx",
+		.min_signal = 0,
+		.max_signal = 2,
+		.muxval = 0x06,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[7] = {
+		/* Muxed on channel 0-3 */
+		.bus_id = "uart3rx",
+		.min_signal = 0,
+		.max_signal = 2,
+		.muxval = 0x07,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[8] = {
+		/* Muxed on channel 0-3 */
+		.bus_id = "sciinta",
+		.min_signal = 0,
+		.max_signal = 2,
+		.muxval = 0x08,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[9] = {
+		/* Muxed on channel 0-3 */
+		.bus_id = "sciintb",
+		.min_signal = 0,
+		.max_signal = 2,
+		.muxval = 0x09,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+	},
+	[10] = {
+		.bus_id = "scirx",
+		.min_signal = 6,
+		.max_signal = 6,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[11] = {
+		.bus_id = "scitx",
+		.min_signal = 7,
+		.max_signal = 7,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[12] = {
+		.bus_id = "ssprx",
+		.min_signal = 8,
+		.max_signal = 8,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[13] = {
+		.bus_id = "ssptx",
+		.min_signal = 9,
+		.max_signal = 9,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[14] = {
+		.bus_id = "uart2rx",
+		.min_signal = 10,
+		.max_signal = 10,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[15] = {
+		.bus_id = "uart2tx",
+		.min_signal = 11,
+		.max_signal = 11,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[16] = {
+		.bus_id = "uart1rx",
+		.min_signal = 12,
+		.max_signal = 12,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[17] = {
+		.bus_id = "uart1tx",
+		.min_signal = 13,
+		.max_signal = 13,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[18] = {
+		.bus_id = "uart0rx",
+		.min_signal = 14,
+		.max_signal = 14,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+	[19] = {
+		.bus_id = "uart0tx",
+		.min_signal = 15,
+		.max_signal = 15,
+		.cctl = PRIMECELL_DEFAULT_CCTL,
+		.ccfg = PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT,
+	},
+};
+
+static void __init pl080_fixup(void)
+{
+	if (machine_is_versatile_ab()) {
+		pl080_plat_data.slave_channels = ab926ejs_chan_data;
+		pl080_plat_data.num_slave_channels = ARRAY_SIZE(ab926ejs_chan_data);
+	}
+	if (machine_is_versatile_pb()) {
+		pl080_plat_data.slave_channels = pb926ejs_chan_data;
+		pl080_plat_data.num_slave_channels = ARRAY_SIZE(pb926ejs_chan_data);
+	}
+}
+#else
+static struct pl08x_platform_data pl080_plat_data = {
+};
+
+static void __init pl080_fixup(void)
+{
+}
+#endif
+
 static struct pl061_platform_data gpio0_plat_data = {
 	.gpio_base	= 0,
 	.irq_base	= IRQ_GPIO0_START,
@@ -703,6 +1195,30 @@ static struct pl061_platform_data gpio1_plat_data = {
 	.irq_base	= IRQ_GPIO1_START,
 };
 
+static struct amba_pl011_data uart0_plat_data = {
+#ifdef CONFIG_AMBA_PL08X
+	.dma_filter = pl08x_filter_id,
+	.dma_rx_param = (void *) "uart0rx",
+	.dma_tx_param = (void *) "uart0tx",
+#endif
+};
+
+static struct amba_pl011_data uart1_plat_data = {
+#ifdef CONFIG_AMBA_PL08X
+	.dma_filter = pl08x_filter_id,
+	.dma_rx_param = (void *) "uart1rx",
+	.dma_tx_param = (void *) "uart1tx",
+#endif
+};
+
+static struct amba_pl011_data uart2_plat_data = {
+#ifdef CONFIG_AMBA_PL08X
+	.dma_filter = pl08x_filter_id,
+	.dma_rx_param = (void *) "uart2rx",
+	.dma_tx_param = (void *) "uart2tx",
+#endif
+};
+
 #define AACI_IRQ	{ IRQ_AACI, NO_IRQ }
 #define AACI_DMA	{ 0x80, 0x81 }
 #define MMCI0_IRQ	{ IRQ_MMCI0A,IRQ_SIC_MMCI0B }
@@ -762,16 +1278,16 @@ AMBA_DEVICE(kmi1,  "fpga:07", KMI1,     NULL);
 AMBA_DEVICE(smc,   "dev:00",  SMC,      NULL);
 AMBA_DEVICE(mpmc,  "dev:10",  MPMC,     NULL);
 AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
-AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
+AMBA_DEVICE(dmac,  "dev:30",  DMAC,     &pl080_plat_data);
 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
 AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
 AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
-AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
-AMBA_DEVICE(uart1, "dev:f2",  UART1,    NULL);
-AMBA_DEVICE(uart2, "dev:f3",  UART2,    NULL);
+AMBA_DEVICE(uart0, "dev:f1",  UART0,    &uart0_plat_data);
+AMBA_DEVICE(uart1, "dev:f2",  UART1,    &uart1_plat_data);
+AMBA_DEVICE(uart2, "dev:f3",  UART2,    &uart2_plat_data);
 AMBA_DEVICE(ssp0,  "dev:f4",  SSP,      NULL);
 
 static struct amba_device *amba_devs[] __initdata = {
@@ -843,6 +1359,7 @@ void __init versatile_init(void)
 	platform_device_register(&versatile_flash_device);
 	platform_device_register(&versatile_i2c_device);
 	platform_device_register(&smc91x_device);
+	pl080_fixup();
 
 	for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 		struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-versatile/include/mach/platform.h b/arch/arm/mach-versatile/include/mach/platform.h
index ec08740..fa0907c 100644
--- a/arch/arm/mach-versatile/include/mach/platform.h
+++ b/arch/arm/mach-versatile/include/mach/platform.h
@@ -86,6 +86,9 @@
 #define VERSATILE_SYS_BOOTCS_OFFSET           0x58
 #define VERSATILE_SYS_24MHz_OFFSET            0x5C
 #define VERSATILE_SYS_MISC_OFFSET             0x60
+#define VERSATILE_SYS_DMAPSR0_OFFSET          0x64 /* Only on PB926EJ-S */
+#define VERSATILE_SYS_DMAPSR1_OFFSET          0x68 /* Only on PB926EJ-S */
+#define VERSATILE_SYS_DMAPSR2_OFFSET          0x6C /* Only on PB926EJ-S */
 #define VERSATILE_SYS_TEST_OSC0_OFFSET        0x80
 #define VERSATILE_SYS_TEST_OSC1_OFFSET        0x84
 #define VERSATILE_SYS_TEST_OSC2_OFFSET        0x88
@@ -124,6 +127,9 @@
 #define VERSATILE_SYS_BOOTCS                  (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET)
 #define VERSATILE_SYS_24MHz                   (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET)
 #define VERSATILE_SYS_MISC                    (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET)
+#define VERSATILE_SYS_DMAPSR0                 (VERSATILE_SYS_BASE + VERSATILE_SYS_DMAPSR0_OFFSET) /* Only on PB926EJ-S */
+#define VERSATILE_SYS_DMAPSR1                 (VERSATILE_SYS_BASE + VERSATILE_SYS_DMAPSR1_OFFSET) /* Only on PB926EJ-S */
+#define VERSATILE_SYS_DMAPSR2                 (VERSATILE_SYS_BASE + VERSATILE_SYS_DMAPSR2_OFFSET) /* Only on PB926EJ-S */
 #define VERSATILE_SYS_TEST_OSC0               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET)
 #define VERSATILE_SYS_TEST_OSC1               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET)
 #define VERSATILE_SYS_TEST_OSC2               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET)
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 239cd30..ecb6bf6 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -25,6 +25,8 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl061.h>
 #include <linux/amba/mmci.h>
+#include <linux/amba/serial.h>
+#include <linux/amba/pl08x.h>
 #include <linux/io.h>
 
 #include <mach/hardware.h>
@@ -46,6 +48,11 @@ static struct mmci_platform_data mmc1_plat_data = {
 	.status		= mmc_status,
 	.gpio_wp	= -1,
 	.gpio_cd	= -1,
+#ifdef CONFIG_AMBA_PL08X
+	.dma_filter = pl08x_filter_id,
+	.dma_rx_param = (void *) "mci1",
+	/* Don't specify a TX channel, this RX channel is bidirectional */
+#endif
 };
 
 static struct pl061_platform_data gpio2_plat_data = {
@@ -58,6 +65,14 @@ static struct pl061_platform_data gpio3_plat_data = {
 	.irq_base	= IRQ_GPIO3_START,
 };
 
+static struct amba_pl011_data uart3_plat_data = {
+#ifdef CONFIG_AMBA_PL08X
+	.dma_filter = pl08x_filter_id,
+	.dma_rx_param = (void *) "uart3rx",
+	.dma_tx_param = (void *) "uart3tx",
+#endif
+};
+
 #define UART3_IRQ	{ IRQ_SIC_UART3, NO_IRQ }
 #define UART3_DMA	{ 0x86, 0x87 }
 #define SCI1_IRQ	{ IRQ_SIC_SCI3, NO_IRQ }
@@ -78,7 +93,7 @@ static struct pl061_platform_data gpio3_plat_data = {
  */
 
 /* FPGA Primecells */
-AMBA_DEVICE(uart3, "fpga:09", UART3,    NULL);
+AMBA_DEVICE(uart3, "fpga:09", UART3,    &uart3_plat_data);
 AMBA_DEVICE(sci1,  "fpga:0a", SCI1,     NULL);
 AMBA_DEVICE(mmc1,  "fpga:0b", MMCI1,    &mmc1_plat_data);
 
-- 
1.6.3.3



From felipe.contreras at gmail.com  Fri Jun 11 11:51:35 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:35 +0300
Subject: [PATCH v4 00/14] omap: mailbox: bunch of cleanups
Message-ID: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>

From: Felipe Contreras <--global>

Hi,

These are hopefully non-functional changes. Just shuffling code around, and
removing unecessary stuff.

This v4 includes minor changes suggested by Felipe Balbi, Hiroshi, and Russell.

Comments from Felipe Balbi, Tony Lindgren, Hiroshi DOYU, and Russell King.

Felipe Contreras (14):
  omap: mailbox: trivial whitespace cleanups
  omap: mailbox: trivial cleanups
  omap: mailbox: reorganize structures
  omap: mailbox: 2420 should be detected at run-time
  omap: mailbox: use correct config for omap1
  omap: mailbox: update omap1 probing
  omap: mailbox: don't export unecessary symbols
  omap: mailbox: remove unecessary fields
  omap: mailbox: add IRQ names
  omap: mailbox: reorganize registering
  omap: mailbox: simplify omap_mbox_register()
  omap: mailbox: only compile for configured archs
  omap: mailbox: standarize on 'omap-mailbox'
  omap: mailbox: reorganize headers

 arch/arm/mach-omap1/devices.c             |   11 +-
 arch/arm/mach-omap1/mailbox.c             |   55 ++++------
 arch/arm/mach-omap2/devices.c             |    6 +-
 arch/arm/mach-omap2/mailbox.c             |  179 +++++++++++++----------------
 arch/arm/plat-omap/include/plat/mailbox.h |   16 +--
 arch/arm/plat-omap/mailbox.c              |  136 +++++++++-------------
 6 files changed, 170 insertions(+), 233 deletions(-)

Here's the interdiff with v3:

diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index fdd6cc9..1a85a42 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -143,17 +143,16 @@ struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL };
 
 static int __devinit omap1_mbox_probe(struct platform_device *pdev)
 {
-       struct resource *res;
+       struct resource *mem;
        int ret;
        int i;
        struct omap_mbox **list;
 
-       res = pdev->resource;
-
        list = omap1_mboxes;
        list[0]->irq = platform_get_irq_byname(pdev, "dsp");
 
-       mbox_base = ioremap(res[0].start, resource_size(&res[0]));
+       mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       mbox_base = ioremap(mem->start, resource_size(mem));
        if (!mbox_base)
                return -ENOMEM;
 
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index d46e439..42dbfa4 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -388,13 +388,12 @@ struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
 
 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 {
-       struct resource *res;
+       struct resource *mem;
        int ret;
        struct omap_mbox **list;
 
-       res = pdev->resource;
-
-       if (false);
+       if (false)
+               ;
 #if defined(CONFIG_ARCH_OMAP3430)
        else if (cpu_is_omap3430()) {
                list = omap3_mboxes;
@@ -423,7 +422,8 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
                return -ENODEV;
        }
 
-       mbox_base = ioremap(res[0].start, resource_size(&res[0]));
+       mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       mbox_base = ioremap(mem->start, resource_size(mem));
        if (!mbox_base)
                return -ENOMEM;
 



From felipe.contreras at gmail.com  Fri Jun 11 11:51:36 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:36 +0300
Subject: [PATCH v4 01/14] omap: mailbox: trivial whitespace cleanups
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-2-git-send-email-felipe.contreras@gmail.com>

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/plat-omap/mailbox.c |   44 +++++++++++++++++++++---------------------
 1 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 36b3aa2..38a6cb1 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -142,14 +142,14 @@ static void mbox_rx_work(struct work_struct *work)
 	struct omap_mbox_queue *mq =
 			container_of(work, struct omap_mbox_queue, work);
 	mbox_msg_t msg;
- 	int len;
-  
- 	while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
- 		len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
- 		WARN_ON(len != sizeof(msg));
-
- 		if (mq->callback)
- 			mq->callback((void *)msg);
+	int len;
+
+	while (kfifo_len(&mq->fifo) >= sizeof(msg)) {
+		len = kfifo_out(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
+		WARN_ON(len != sizeof(msg));
+
+		if (mq->callback)
+			mq->callback((void *)msg);
 	}
 }
 
@@ -165,12 +165,12 @@ static void __mbox_tx_interrupt(struct omap_mbox *mbox)
 
 static void __mbox_rx_interrupt(struct omap_mbox *mbox)
 {
- 	struct omap_mbox_queue *mq = mbox->rxq;
+	struct omap_mbox_queue *mq = mbox->rxq;
 	mbox_msg_t msg;
- 	int len;
+	int len;
 
 	while (!mbox_fifo_empty(mbox)) {
- 		if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
+		if (unlikely(kfifo_avail(&mq->fifo) < sizeof(msg))) {
 			omap_mbox_disable_irq(mbox, IRQ_RX);
 			rq_full = true;
 			goto nomem;
@@ -178,8 +178,8 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
 
 		msg = mbox_fifo_read(mbox);
 
- 		len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
- 		WARN_ON(len != sizeof(msg));
+		len = kfifo_in(&mq->fifo, (unsigned char *)&msg, sizeof(msg));
+		WARN_ON(len != sizeof(msg));
 
 		if (mbox->ops->type == OMAP_MBOX_TYPE1)
 			break;
@@ -278,11 +278,11 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
 
 	return 0;
 
- fail_alloc_rxq:
+fail_alloc_rxq:
 	mbox_queue_free(mbox->txq);
- fail_alloc_txq:
+fail_alloc_txq:
 	free_irq(mbox->irq, mbox);
- fail_request_irq:
+fail_request_irq:
 	if (mbox->ops->shutdown)
 		mbox->ops->shutdown(mbox);
 
@@ -359,10 +359,10 @@ int omap_mbox_register(struct device *parent, struct omap_mbox *mbox)
 	if (mbox->next)
 		return -EBUSY;
 
- 	mbox->dev = device_create(&omap_mbox_class,
- 				  parent, 0, mbox, "%s", mbox->name);
- 	if (IS_ERR(mbox->dev))
- 		return PTR_ERR(mbox->dev);
+	mbox->dev = device_create(&omap_mbox_class,
+				  parent, 0, mbox, "%s", mbox->name);
+	if (IS_ERR(mbox->dev))
+		return PTR_ERR(mbox->dev);
 
 	spin_lock(&mboxes_lock);
 	tmp = find_mboxes(mbox->name);
@@ -405,7 +405,7 @@ EXPORT_SYMBOL(omap_mbox_unregister);
 
 static int __init omap_mbox_init(void)
 {
- 	int err;
+	int err;
 
 	err = class_register(&omap_mbox_class);
 	if (err)
@@ -426,7 +426,7 @@ subsys_initcall(omap_mbox_init);
 static void __exit omap_mbox_exit(void)
 {
 	destroy_workqueue(mboxd);
- 	class_unregister(&omap_mbox_class);
+	class_unregister(&omap_mbox_class);
 }
 module_exit(omap_mbox_exit);
 
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:37 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:37 +0300
Subject: [PATCH v4 02/14] omap: mailbox: trivial cleanups
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-3-git-send-email-felipe.contreras@gmail.com>

And fix a few compilation warnings.

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/mach-omap1/devices.c |    6 ++----
 arch/arm/mach-omap1/mailbox.c |    2 +-
 arch/arm/mach-omap2/mailbox.c |   10 ++++++----
 3 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 379100c..462b59c 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -73,12 +73,10 @@ static inline void omap_init_rtc(void) {}
 #  define INT_DSP_MAILBOX1	INT_1610_DSP_MAILBOX1
 #endif
 
-#define OMAP1_MBOX_BASE		OMAP16XX_MAILBOX_BASE
-
 static struct resource mbox_resources[] = {
 	{
-		.start		= OMAP1_MBOX_BASE,
-		.end		= OMAP1_MBOX_BASE + OMAP1_MBOX_SIZE,
+		.start		= OMAP16XX_MAILBOX_BASE,
+		.end		= OMAP16XX_MAILBOX_BASE + OMAP1_MBOX_SIZE,
 		.flags		= IORESOURCE_MEM,
 	},
 	{
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index 4f5b3da..15bf2a2 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -83,7 +83,7 @@ static int omap1_mbox_fifo_full(struct omap_mbox *mbox)
 	struct omap_mbox1_fifo *fifo =
 		&((struct omap_mbox1_priv *)mbox->priv)->rx_fifo;
 
-	return (mbox_read_reg(fifo->flag));
+	return mbox_read_reg(fifo->flag);
 }
 
 /* irq */
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 763272c..8c1070c 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -131,7 +131,7 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
 	}
 
 	l = mbox_read_reg(MAILBOX_REVISION);
-	pr_info("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
+	pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
 
 	if (cpu_is_omap44xx())
 		l = OMAP4_SMARTIDLE;
@@ -300,8 +300,6 @@ static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
 	.irqdisable	= MAILBOX_IRQENABLE(0),
 };
 
-
-
 /* OMAP4 specific data structure. Use the cpu_is_omap4xxx()
 to use this*/
 static struct omap_mbox2_priv omap2_mbox_1_priv = {
@@ -357,7 +355,6 @@ struct omap_mbox mbox_2_info = {
 };
 EXPORT_SYMBOL(mbox_2_info);
 
-
 #if defined(CONFIG_ARCH_OMAP2420) /* IVA */
 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
 	.tx_fifo = {
@@ -443,6 +440,11 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 #endif
 	return 0;
 
+#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
+err_iva1:
+	omap_mbox_unregister(&mbox_dsp_info);
+#endif
+
 err_dsp:
 	iounmap(mbox_base);
 	return ret;
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:38 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:38 +0300
Subject: [PATCH v4 03/14] omap: mailbox: reorganize structures
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-4-git-send-email-felipe.contreras@gmail.com>

OMAP4 ones messed up the organization.

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/mach-omap2/mailbox.c |   68 +++++++++++++++++++++--------------------
 1 files changed, 35 insertions(+), 33 deletions(-)

diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 8c1070c..edcfec6 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -283,6 +283,7 @@ static struct omap_mbox_ops omap2_mbox_ops = {
  */
 
 /* FIXME: the following structs should be filled automatically by the user id */
+
 /* DSP */
 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
 	.tx_fifo = {
@@ -300,8 +301,40 @@ static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
 	.irqdisable	= MAILBOX_IRQENABLE(0),
 };
 
-/* OMAP4 specific data structure. Use the cpu_is_omap4xxx()
-to use this*/
+struct omap_mbox mbox_dsp_info = {
+	.name	= "dsp",
+	.ops	= &omap2_mbox_ops,
+	.priv	= &omap2_mbox_dsp_priv,
+};
+EXPORT_SYMBOL(mbox_dsp_info);
+
+#if defined(CONFIG_ARCH_OMAP2420)
+
+/* IVA */
+static struct omap_mbox2_priv omap2_mbox_iva_priv = {
+	.tx_fifo = {
+		.msg		= MAILBOX_MESSAGE(2),
+		.fifo_stat	= MAILBOX_FIFOSTATUS(2),
+	},
+	.rx_fifo = {
+		.msg		= MAILBOX_MESSAGE(3),
+		.msg_stat	= MAILBOX_MSGSTATUS(3),
+	},
+	.irqenable	= MAILBOX_IRQENABLE(3),
+	.irqstatus	= MAILBOX_IRQSTATUS(3),
+	.notfull_bit	= MAILBOX_IRQ_NOTFULL(2),
+	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(3),
+	.irqdisable	= MAILBOX_IRQENABLE(3),
+};
+
+static struct omap_mbox mbox_iva_info = {
+	.name	= "iva",
+	.ops	= &omap2_mbox_ops,
+	.priv	= &omap2_mbox_iva_priv,
+};
+#endif
+
+/* OMAP4 */
 static struct omap_mbox2_priv omap2_mbox_1_priv = {
 	.tx_fifo = {
 		.msg		= MAILBOX_MESSAGE(0),
@@ -325,13 +358,6 @@ struct omap_mbox mbox_1_info = {
 };
 EXPORT_SYMBOL(mbox_1_info);
 
-struct omap_mbox mbox_dsp_info = {
-	.name	= "dsp",
-	.ops	= &omap2_mbox_ops,
-	.priv	= &omap2_mbox_dsp_priv,
-};
-EXPORT_SYMBOL(mbox_dsp_info);
-
 static struct omap_mbox2_priv omap2_mbox_2_priv = {
 	.tx_fifo = {
 		.msg		= MAILBOX_MESSAGE(3),
@@ -355,30 +381,6 @@ struct omap_mbox mbox_2_info = {
 };
 EXPORT_SYMBOL(mbox_2_info);
 
-#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
-static struct omap_mbox2_priv omap2_mbox_iva_priv = {
-	.tx_fifo = {
-		.msg		= MAILBOX_MESSAGE(2),
-		.fifo_stat	= MAILBOX_FIFOSTATUS(2),
-	},
-	.rx_fifo = {
-		.msg		= MAILBOX_MESSAGE(3),
-		.msg_stat	= MAILBOX_MSGSTATUS(3),
-	},
-	.irqenable	= MAILBOX_IRQENABLE(3),
-	.irqstatus	= MAILBOX_IRQSTATUS(3),
-	.notfull_bit	= MAILBOX_IRQ_NOTFULL(2),
-	.newmsg_bit	= MAILBOX_IRQ_NEWMSG(3),
-	.irqdisable	= MAILBOX_IRQENABLE(3),
-};
-
-static struct omap_mbox mbox_iva_info = {
-	.name	= "iva",
-	.ops	= &omap2_mbox_ops,
-	.priv	= &omap2_mbox_iva_priv,
-};
-#endif
-
 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 {
 	struct resource *res;
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:39 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:39 +0300
Subject: [PATCH v4 04/14] omap: mailbox: 2420 should be detected at run-time
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-5-git-send-email-felipe.contreras@gmail.com>

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/mach-omap2/mailbox.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index edcfec6..f67cb2c 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -455,7 +455,8 @@ err_dsp:
 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
 {
 #if defined(CONFIG_ARCH_OMAP2420)
-	omap_mbox_unregister(&mbox_iva_info);
+	if (cpu_is_omap2420())
+		omap_mbox_unregister(&mbox_iva_info);
 #endif
 
 	if (cpu_is_omap44xx()) {
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:40 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:40 +0300
Subject: [PATCH v4 05/14] omap: mailbox: use correct config for omap1
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-6-git-send-email-felipe.contreras@gmail.com>

CONFIG_OMAP_DSP is not in mainline, CONFIG_OMAP_MBOX_FWK is.

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/mach-omap1/devices.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 462b59c..da796f2 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -63,7 +63,7 @@ static void omap_init_rtc(void)
 static inline void omap_init_rtc(void) {}
 #endif
 
-#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
+#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
 
 #if defined(CONFIG_ARCH_OMAP15XX)
 #  define OMAP1_MBOX_SIZE	0x23
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:41 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:41 +0300
Subject: [PATCH v4 06/14] omap: mailbox: update omap1 probing
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-7-git-send-email-felipe.contreras@gmail.com>

Based on omap2 code.

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/mach-omap1/mailbox.c |   28 ++++++++++++++--------------
 1 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index 15bf2a2..211b9fc 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -146,12 +146,7 @@ EXPORT_SYMBOL(mbox_dsp_info);
 static int __devinit omap1_mbox_probe(struct platform_device *pdev)
 {
 	struct resource *res;
-
-	if (pdev->num_resources != 2) {
-		dev_err(&pdev->dev, "invalid number of resources: %d\n",
-			pdev->num_resources);
-		return -ENODEV;
-	}
+	int ret;
 
 	/* MBOX base */
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -161,27 +156,32 @@ static int __devinit omap1_mbox_probe(struct platform_device *pdev)
 	}
 
 	mbox_base = ioremap(res->start, resource_size(res));
-	if (!mbox_base) {
-		dev_err(&pdev->dev, "ioremap failed\n");
-		return -ENODEV;
-	}
+	if (!mbox_base)
+		return -ENOMEM;
 
 	/* DSP IRQ */
 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 	if (unlikely(!res)) {
 		dev_err(&pdev->dev, "invalid irq resource\n");
-		iounmap(mbox_base);
-		return -ENODEV;
+		ret = -ENODEV;
+		goto err_out;
 	}
 	mbox_dsp_info.irq = res->start;
 
-	return omap_mbox_register(&pdev->dev, &mbox_dsp_info);
+	ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
+	if (ret)
+		goto err_out;
+	return 0;
+
+err_out:
+	iounmap(mbox_base);
+	return ret;
 }
 
 static int __devexit omap1_mbox_remove(struct platform_device *pdev)
 {
 	omap_mbox_unregister(&mbox_dsp_info);
-
+	iounmap(mbox_base);
 	return 0;
 }
 
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:42 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:42 +0300
Subject: [PATCH v4 07/14] omap: mailbox: don't export unecessary symbols
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-8-git-send-email-felipe.contreras@gmail.com>

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/mach-omap1/mailbox.c |    1 -
 arch/arm/mach-omap2/mailbox.c |    3 ---
 2 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index 211b9fc..590ac66 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -141,7 +141,6 @@ struct omap_mbox mbox_dsp_info = {
 	.ops	= &omap1_mbox_ops,
 	.priv	= &omap1_mbox_dsp_priv,
 };
-EXPORT_SYMBOL(mbox_dsp_info);
 
 static int __devinit omap1_mbox_probe(struct platform_device *pdev)
 {
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index f67cb2c..3ff1ad5 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -306,7 +306,6 @@ struct omap_mbox mbox_dsp_info = {
 	.ops	= &omap2_mbox_ops,
 	.priv	= &omap2_mbox_dsp_priv,
 };
-EXPORT_SYMBOL(mbox_dsp_info);
 
 #if defined(CONFIG_ARCH_OMAP2420)
 
@@ -356,7 +355,6 @@ struct omap_mbox mbox_1_info = {
 	.ops	= &omap2_mbox_ops,
 	.priv	= &omap2_mbox_1_priv,
 };
-EXPORT_SYMBOL(mbox_1_info);
 
 static struct omap_mbox2_priv omap2_mbox_2_priv = {
 	.tx_fifo = {
@@ -379,7 +377,6 @@ struct omap_mbox mbox_2_info = {
 	.ops	= &omap2_mbox_ops,
 	.priv	= &omap2_mbox_2_priv,
 };
-EXPORT_SYMBOL(mbox_2_info);
 
 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 {
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:43 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:43 +0300
Subject: [PATCH v4 08/14] omap: mailbox: remove unecessary fields
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-9-git-send-email-felipe.contreras@gmail.com>

Nobody is using them.

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/plat-omap/include/plat/mailbox.h |    8 --------
 1 files changed, 0 insertions(+), 8 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index 0c3c4a5..aad8bf8 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -52,19 +52,11 @@ struct omap_mbox_queue {
 struct omap_mbox {
 	char			*name;
 	unsigned int		irq;
-
 	struct omap_mbox_queue	*txq, *rxq;
-
 	struct omap_mbox_ops	*ops;
-
-	mbox_msg_t		seq_snd, seq_rcv;
-
 	struct device		*dev;
-
 	struct omap_mbox	*next;
 	void			*priv;
-
-	void			(*err_notify)(void);
 };
 
 int omap_mbox_msg_send(struct omap_mbox *, mbox_msg_t msg);
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:45 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:45 +0300
Subject: [PATCH v4 10/14] omap: mailbox: reorganize registering
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-11-git-send-email-felipe.contreras@gmail.com>

It's more extensible this way.

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/mach-omap1/mailbox.c |   42 ++++++++--------
 arch/arm/mach-omap2/mailbox.c |  107 +++++++++++++++++------------------------
 2 files changed, 66 insertions(+), 83 deletions(-)

diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index 590ac66..0318754 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -29,6 +29,8 @@
 
 static void __iomem *mbox_base;
 
+static struct omap_mbox **list;
+
 struct omap_mbox1_fifo {
 	unsigned long cmd;
 	unsigned long data;
@@ -142,44 +144,44 @@ struct omap_mbox mbox_dsp_info = {
 	.priv	= &omap1_mbox_dsp_priv,
 };
 
+struct omap_mbox *omap1_mboxes[] = { &mbox_dsp_info, NULL };
+
 static int __devinit omap1_mbox_probe(struct platform_device *pdev)
 {
-	struct resource *res;
+	struct resource *mem;
 	int ret;
+	int i;
 
-	/* MBOX base */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (unlikely(!res)) {
-		dev_err(&pdev->dev, "invalid mem resource\n");
-		return -ENODEV;
-	}
+	list = omap1_mboxes;
+
+	list[0]->irq = platform_get_irq_byname(pdev, "dsp");
 
-	mbox_base = ioremap(res->start, resource_size(res));
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mbox_base = ioremap(mem->start, resource_size(mem));
 	if (!mbox_base)
 		return -ENOMEM;
 
-	/* DSP IRQ */
-	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-	if (unlikely(!res)) {
-		dev_err(&pdev->dev, "invalid irq resource\n");
-		ret = -ENODEV;
-		goto err_out;
+	for (i = 0; list[i]; i++) {
+		ret = omap_mbox_register(&pdev->dev, list[i]);
+		if (ret)
+			goto err_out;
 	}
-	mbox_dsp_info.irq = res->start;
-
-	ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
-	if (ret)
-		goto err_out;
 	return 0;
 
 err_out:
+	while (i--)
+		omap_mbox_unregister(list[i]);
 	iounmap(mbox_base);
 	return ret;
 }
 
 static int __devexit omap1_mbox_remove(struct platform_device *pdev)
 {
-	omap_mbox_unregister(&mbox_dsp_info);
+	int i;
+
+	for (i = 0; list[i]; i++)
+		omap_mbox_unregister(list[i]);
+
 	iounmap(mbox_base);
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 3ff1ad5..e5abc8e 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -56,6 +56,8 @@
 
 static void __iomem *mbox_base;
 
+static struct omap_mbox **list;
+
 struct omap_mbox2_fifo {
 	unsigned long msg;
 	unsigned long fifo_stat;
@@ -307,6 +309,8 @@ struct omap_mbox mbox_dsp_info = {
 	.priv	= &omap2_mbox_dsp_priv,
 };
 
+struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
+
 #if defined(CONFIG_ARCH_OMAP2420)
 
 /* IVA */
@@ -331,6 +335,8 @@ static struct omap_mbox mbox_iva_info = {
 	.ops	= &omap2_mbox_ops,
 	.priv	= &omap2_mbox_iva_priv,
 };
+
+struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
 #endif
 
 /* OMAP4 */
@@ -378,89 +384,64 @@ struct omap_mbox mbox_2_info = {
 	.priv	= &omap2_mbox_2_priv,
 };
 
+struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
+
 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 {
-	struct resource *res;
+	struct resource *mem;
 	int ret;
+	int i;
 
-	/* MBOX base */
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	if (unlikely(!res)) {
-		dev_err(&pdev->dev, "invalid mem resource\n");
-		return -ENODEV;
+	if (cpu_is_omap3430()) {
+		list = omap3_mboxes;
+
+		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
 	}
-	mbox_base = ioremap(res->start, resource_size(res));
-	if (!mbox_base)
-		return -ENOMEM;
+#if defined(CONFIG_ARCH_OMAP2420)
+	else if (cpu_is_omap2420()) {
+		list = omap2_mboxes;
 
-	/* DSP or IVA2 IRQ */
-	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
+		list[1]->irq = platform_get_irq_byname(pdev, "iva");
+	}
+#endif
+	else if (cpu_is_omap44xx()) {
+		list = omap4_mboxes;
 
-	if (unlikely(!res)) {
-		dev_err(&pdev->dev, "invalid irq resource\n");
-		ret = -ENODEV;
-		goto err_dsp;
+		list[0]->irq = list[1]->irq =
+			platform_get_irq_byname(pdev, "mbox");
 	}
-	if (cpu_is_omap44xx()) {
-		mbox_1_info.irq = res->start;
-		ret = omap_mbox_register(&pdev->dev, &mbox_1_info);
-	} else {
-		mbox_dsp_info.irq = res->start;
-		ret = omap_mbox_register(&pdev->dev, &mbox_dsp_info);
+	else {
+		pr_err("%s: platform not supported\n", __func__);
+		return -ENODEV;
 	}
-	if (ret)
-		goto err_dsp;
 
-	if (cpu_is_omap44xx()) {
-		mbox_2_info.irq = res->start;
-		ret = omap_mbox_register(&pdev->dev, &mbox_2_info);
-		if (ret) {
-			omap_mbox_unregister(&mbox_1_info);
-			goto err_dsp;
-		}
-	}
-#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
-	if (cpu_is_omap2420()) {
-		/* IVA IRQ */
-		res = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
-		if (unlikely(!res)) {
-			dev_err(&pdev->dev, "invalid irq resource\n");
-			ret = -ENODEV;
-			omap_mbox_unregister(&mbox_dsp_info);
-			goto err_dsp;
-		}
-		mbox_iva_info.irq = res->start;
-		ret = omap_mbox_register(&pdev->dev, &mbox_iva_info);
-		if (ret) {
-			omap_mbox_unregister(&mbox_dsp_info);
-			goto err_dsp;
-		}
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	mbox_base = ioremap(mem->start, resource_size(mem));
+	if (!mbox_base)
+		return -ENOMEM;
+
+	for (i = 0; list[i]; i++) {
+		ret = omap_mbox_register(&pdev->dev, list[i]);
+		if (ret)
+			goto err_out;
 	}
-#endif
 	return 0;
 
-#if defined(CONFIG_ARCH_OMAP2420) /* IVA */
-err_iva1:
-	omap_mbox_unregister(&mbox_dsp_info);
-#endif
-
-err_dsp:
+err_out:
+	while (i--)
+		omap_mbox_unregister(list[i]);
 	iounmap(mbox_base);
 	return ret;
 }
 
 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
 {
-#if defined(CONFIG_ARCH_OMAP2420)
-	if (cpu_is_omap2420())
-		omap_mbox_unregister(&mbox_iva_info);
-#endif
+	int i;
+
+	for (i = 0; list[i]; i++)
+		omap_mbox_unregister(list[i]);
 
-	if (cpu_is_omap44xx()) {
-		omap_mbox_unregister(&mbox_2_info);
-		omap_mbox_unregister(&mbox_1_info);
-	} else
-		omap_mbox_unregister(&mbox_dsp_info);
 	iounmap(mbox_base);
 	return 0;
 }
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:44 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:44 +0300
Subject: [PATCH v4 09/14] omap: mailbox: add IRQ names
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-10-git-send-email-felipe.contreras@gmail.com>

Will be useful to identify them later.

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/mach-omap1/devices.c |    1 +
 arch/arm/mach-omap2/devices.c |    4 ++++
 2 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index da796f2..314fea3 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -82,6 +82,7 @@ static struct resource mbox_resources[] = {
 	{
 		.start		= INT_DSP_MAILBOX1,
 		.flags		= IORESOURCE_IRQ,
+		.name		= "dsp",
 	},
 };
 
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 2271b9b..b621476 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -150,10 +150,12 @@ static struct resource omap2_mbox_resources[] = {
 	{
 		.start		= INT_24XX_MAIL_U0_MPU,
 		.flags		= IORESOURCE_IRQ,
+		.name		= "dsp",
 	},
 	{
 		.start		= INT_24XX_MAIL_U3_MPU,
 		.flags		= IORESOURCE_IRQ,
+		.name		= "iva",
 	},
 };
 static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
@@ -172,6 +174,7 @@ static struct resource omap3_mbox_resources[] = {
 	{
 		.start		= INT_24XX_MAIL_U0_MPU,
 		.flags		= IORESOURCE_IRQ,
+		.name		= "dsp",
 	},
 };
 static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
@@ -193,6 +196,7 @@ static struct resource omap4_mbox_resources[] = {
 	{
 		.start          = OMAP44XX_IRQ_MAIL_U0,
 		.flags          = IORESOURCE_IRQ,
+		.name		= "mbox",
 	},
 };
 static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:46 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:46 +0300
Subject: [PATCH v4 11/14] omap: mailbox: simplify omap_mbox_register()
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-12-git-send-email-felipe.contreras@gmail.com>

No need to dynamically register mailboxes one by one.

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/mach-omap1/mailbox.c             |   25 ++------
 arch/arm/mach-omap2/mailbox.c             |   22 ++-----
 arch/arm/plat-omap/include/plat/mailbox.h |    5 +-
 arch/arm/plat-omap/mailbox.c              |   95 +++++++++++------------------
 4 files changed, 50 insertions(+), 97 deletions(-)

diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index 0318754..9ca0d58 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -29,8 +29,6 @@
 
 static void __iomem *mbox_base;
 
-static struct omap_mbox **list;
-
 struct omap_mbox1_fifo {
 	unsigned long cmd;
 	unsigned long data;
@@ -151,9 +149,9 @@ static int __devinit omap1_mbox_probe(struct platform_device *pdev)
 	struct resource *mem;
 	int ret;
 	int i;
+	struct omap_mbox **list;
 
 	list = omap1_mboxes;
-
 	list[0]->irq = platform_get_irq_byname(pdev, "dsp");
 
 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -161,27 +159,18 @@ static int __devinit omap1_mbox_probe(struct platform_device *pdev)
 	if (!mbox_base)
 		return -ENOMEM;
 
-	for (i = 0; list[i]; i++) {
-		ret = omap_mbox_register(&pdev->dev, list[i]);
-		if (ret)
-			goto err_out;
+	ret = omap_mbox_register(&pdev->dev, list);
+	if (ret) {
+		iounmap(mbox_base);
+		return ret;
 	}
-	return 0;
 
-err_out:
-	while (i--)
-		omap_mbox_unregister(list[i]);
-	iounmap(mbox_base);
-	return ret;
+	return 0;
 }
 
 static int __devexit omap1_mbox_remove(struct platform_device *pdev)
 {
-	int i;
-
-	for (i = 0; list[i]; i++)
-		omap_mbox_unregister(list[i]);
-
+	omap_mbox_unregister();
 	iounmap(mbox_base);
 	return 0;
 }
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index e5abc8e..55d8b77 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -56,8 +56,6 @@
 
 static void __iomem *mbox_base;
 
-static struct omap_mbox **list;
-
 struct omap_mbox2_fifo {
 	unsigned long msg;
 	unsigned long fifo_stat;
@@ -390,7 +388,7 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 {
 	struct resource *mem;
 	int ret;
-	int i;
+	struct omap_mbox **list;
 
 	if (cpu_is_omap3430()) {
 		list = omap3_mboxes;
@@ -421,27 +419,19 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 	if (!mbox_base)
 		return -ENOMEM;
 
-	for (i = 0; list[i]; i++) {
-		ret = omap_mbox_register(&pdev->dev, list[i]);
-		if (ret)
-			goto err_out;
+	ret = omap_mbox_register(&pdev->dev, list);
+	if (ret) {
+		iounmap(mbox_base);
+		return ret;
 	}
 	return 0;
 
-err_out:
-	while (i--)
-		omap_mbox_unregister(list[i]);
-	iounmap(mbox_base);
 	return ret;
 }
 
 static int __devexit omap2_mbox_remove(struct platform_device *pdev)
 {
-	int i;
-
-	for (i = 0; list[i]; i++)
-		omap_mbox_unregister(list[i]);
-
+	omap_mbox_unregister();
 	iounmap(mbox_base);
 	return 0;
 }
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index aad8bf8..c44fde3 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -55,7 +55,6 @@ struct omap_mbox {
 	struct omap_mbox_queue	*txq, *rxq;
 	struct omap_mbox_ops	*ops;
 	struct device		*dev;
-	struct omap_mbox	*next;
 	void			*priv;
 };
 
@@ -65,8 +64,8 @@ void omap_mbox_init_seq(struct omap_mbox *);
 struct omap_mbox *omap_mbox_get(const char *);
 void omap_mbox_put(struct omap_mbox *);
 
-int omap_mbox_register(struct device *parent, struct omap_mbox *);
-int omap_mbox_unregister(struct omap_mbox *);
+int omap_mbox_register(struct device *parent, struct omap_mbox **);
+int omap_mbox_unregister(void);
 
 static inline void omap_mbox_save_ctx(struct omap_mbox *mbox)
 {
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 38a6cb1..a8e22e1 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -33,8 +33,7 @@
 #include <plat/mailbox.h>
 
 static struct workqueue_struct *mboxd;
-static struct omap_mbox *mboxes;
-static DEFINE_SPINLOCK(mboxes_lock);
+static struct omap_mbox **mboxes;
 static bool rq_full;
 
 static int mbox_configured;
@@ -307,31 +306,20 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
 	}
 }
 
-static struct omap_mbox **find_mboxes(const char *name)
-{
-	struct omap_mbox **p;
-
-	for (p = &mboxes; *p; p = &(*p)->next) {
-		if (strcmp((*p)->name, name) == 0)
-			break;
-	}
-
-	return p;
-}
-
 struct omap_mbox *omap_mbox_get(const char *name)
 {
 	struct omap_mbox *mbox;
 	int ret;
 
-	spin_lock(&mboxes_lock);
-	mbox = *(find_mboxes(name));
-	if (mbox == NULL) {
-		spin_unlock(&mboxes_lock);
-		return ERR_PTR(-ENOENT);
-	}
+	if (!mboxes)
+		return ERR_PTR(-EINVAL);
 
-	spin_unlock(&mboxes_lock);
+	for (mbox = *mboxes; mbox; mbox++)
+		if (!strcmp(mbox->name, name))
+			break;
+
+	if (!mbox)
+		return ERR_PTR(-ENOENT);
 
 	ret = omap_mbox_startup(mbox);
 	if (ret)
@@ -349,57 +337,44 @@ EXPORT_SYMBOL(omap_mbox_put);
 
 static struct class omap_mbox_class = { .name = "mbox", };
 
-int omap_mbox_register(struct device *parent, struct omap_mbox *mbox)
+int omap_mbox_register(struct device *parent, struct omap_mbox **list)
 {
-	int ret = 0;
-	struct omap_mbox **tmp;
+	int ret;
+	int i;
 
-	if (!mbox)
+	mboxes = list;
+	if (!mboxes)
 		return -EINVAL;
-	if (mbox->next)
-		return -EBUSY;
-
-	mbox->dev = device_create(&omap_mbox_class,
-				  parent, 0, mbox, "%s", mbox->name);
-	if (IS_ERR(mbox->dev))
-		return PTR_ERR(mbox->dev);
-
-	spin_lock(&mboxes_lock);
-	tmp = find_mboxes(mbox->name);
-	if (*tmp) {
-		ret = -EBUSY;
-		spin_unlock(&mboxes_lock);
-		goto err_find;
-	}
-	*tmp = mbox;
-	spin_unlock(&mboxes_lock);
 
+	for (i = 0; mboxes[i]; i++) {
+		struct omap_mbox *mbox = mboxes[i];
+		mbox->dev = device_create(&omap_mbox_class,
+				parent, 0, mbox, "%s", mbox->name);
+		if (IS_ERR(mbox->dev)) {
+			ret = PTR_ERR(mbox->dev);
+			goto err_out;
+		}
+	}
 	return 0;
 
-err_find:
+err_out:
+	while (i--)
+		device_unregister(mboxes[i]->dev);
 	return ret;
 }
 EXPORT_SYMBOL(omap_mbox_register);
 
-int omap_mbox_unregister(struct omap_mbox *mbox)
+int omap_mbox_unregister(void)
 {
-	struct omap_mbox **tmp;
-
-	spin_lock(&mboxes_lock);
-	tmp = &mboxes;
-	while (*tmp) {
-		if (mbox == *tmp) {
-			*tmp = mbox->next;
-			mbox->next = NULL;
-			spin_unlock(&mboxes_lock);
-			device_unregister(mbox->dev);
-			return 0;
-		}
-		tmp = &(*tmp)->next;
-	}
-	spin_unlock(&mboxes_lock);
+	int i;
 
-	return -EINVAL;
+	if (!mboxes)
+		return -EINVAL;
+
+	for (i = 0; mboxes[i]; i++)
+		device_unregister(mboxes[i]->dev);
+	mboxes = NULL;
+	return 0;
 }
 EXPORT_SYMBOL(omap_mbox_unregister);
 
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:47 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:47 +0300
Subject: [PATCH v4 12/14] omap: mailbox: only compile for configured archs
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-13-git-send-email-felipe.contreras@gmail.com>

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/mach-omap2/mailbox.c |   15 +++++++++++++--
 1 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 55d8b77..4c0c112 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -284,6 +284,7 @@ static struct omap_mbox_ops omap2_mbox_ops = {
 
 /* FIXME: the following structs should be filled automatically by the user id */
 
+#if defined(CONFIG_ARCH_OMAP3430) || defined(CONFIG_ARCH_OMAP2420)
 /* DSP */
 static struct omap_mbox2_priv omap2_mbox_dsp_priv = {
 	.tx_fifo = {
@@ -306,11 +307,13 @@ struct omap_mbox mbox_dsp_info = {
 	.ops	= &omap2_mbox_ops,
 	.priv	= &omap2_mbox_dsp_priv,
 };
+#endif
 
+#if defined(CONFIG_ARCH_OMAP3430)
 struct omap_mbox *omap3_mboxes[] = { &mbox_dsp_info, NULL };
+#endif
 
 #if defined(CONFIG_ARCH_OMAP2420)
-
 /* IVA */
 static struct omap_mbox2_priv omap2_mbox_iva_priv = {
 	.tx_fifo = {
@@ -337,6 +340,7 @@ static struct omap_mbox mbox_iva_info = {
 struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
 #endif
 
+#if defined(CONFIG_ARCH_OMAP4)
 /* OMAP4 */
 static struct omap_mbox2_priv omap2_mbox_1_priv = {
 	.tx_fifo = {
@@ -383,6 +387,7 @@ struct omap_mbox mbox_2_info = {
 };
 
 struct omap_mbox *omap4_mboxes[] = { &mbox_1_info, &mbox_2_info, NULL };
+#endif
 
 static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 {
@@ -390,11 +395,15 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 	int ret;
 	struct omap_mbox **list;
 
-	if (cpu_is_omap3430()) {
+	if (false)
+		;
+#if defined(CONFIG_ARCH_OMAP3430)
+	else if (cpu_is_omap3430()) {
 		list = omap3_mboxes;
 
 		list[0]->irq = platform_get_irq_byname(pdev, "dsp");
 	}
+#endif
 #if defined(CONFIG_ARCH_OMAP2420)
 	else if (cpu_is_omap2420()) {
 		list = omap2_mboxes;
@@ -403,12 +412,14 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
 		list[1]->irq = platform_get_irq_byname(pdev, "iva");
 	}
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
 	else if (cpu_is_omap44xx()) {
 		list = omap4_mboxes;
 
 		list[0]->irq = list[1]->irq =
 			platform_get_irq_byname(pdev, "mbox");
 	}
+#endif
 	else {
 		pr_err("%s: platform not supported\n", __func__);
 		return -ENODEV;
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:48 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:48 +0300
Subject: [PATCH v4 13/14] omap: mailbox: standarize on 'omap-mailbox'
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-14-git-send-email-felipe.contreras@gmail.com>

omap{1,2}-mailbox are modules that provide the 'omap-mailbox' driver.

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/mach-omap1/devices.c |    2 +-
 arch/arm/mach-omap1/mailbox.c |    4 ++--
 arch/arm/mach-omap2/devices.c |    2 +-
 arch/arm/mach-omap2/mailbox.c |    6 ++----
 4 files changed, 6 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 314fea3..16e43e5 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -87,7 +87,7 @@ static struct resource mbox_resources[] = {
 };
 
 static struct platform_device mbox_device = {
-	.name		= "omap1-mailbox",
+	.name		= "omap-mailbox",
 	.id		= -1,
 	.num_resources	= ARRAY_SIZE(mbox_resources),
 	.resource	= mbox_resources,
diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index 9ca0d58..afc3963 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -1,5 +1,5 @@
 /*
- * Mailbox reservation modules for DSP
+ * Mailbox reservation modules for OMAP1
  *
  * Copyright (C) 2006-2009 Nokia Corporation
  * Written by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
@@ -179,7 +179,7 @@ static struct platform_driver omap1_mbox_driver = {
 	.probe	= omap1_mbox_probe,
 	.remove	= __devexit_p(omap1_mbox_remove),
 	.driver	= {
-		.name	= "omap1-mailbox",
+		.name	= "omap-mailbox",
 	},
 };
 
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index b621476..d9ac853 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -206,7 +206,7 @@ static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
 #endif
 
 static struct platform_device mbox_device = {
-	.name		= "omap2-mailbox",
+	.name		= "omap-mailbox",
 	.id		= -1,
 };
 
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 4c0c112..62d5ffe 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -18,8 +18,6 @@
 #include <plat/mailbox.h>
 #include <mach/irqs.h>
 
-#define DRV_NAME "omap2-mailbox"
-
 #define MAILBOX_REVISION		0x000
 #define MAILBOX_SYSCONFIG		0x010
 #define MAILBOX_SYSSTATUS		0x014
@@ -451,7 +449,7 @@ static struct platform_driver omap2_mbox_driver = {
 	.probe = omap2_mbox_probe,
 	.remove = __devexit_p(omap2_mbox_remove),
 	.driver = {
-		.name = DRV_NAME,
+		.name = "omap-mailbox",
 	},
 };
 
@@ -472,4 +470,4 @@ MODULE_LICENSE("GPL v2");
 MODULE_DESCRIPTION("omap mailbox: omap2/3/4 architecture specific functions");
 MODULE_AUTHOR("Hiroshi DOYU <Hiroshi.DOYU at nokia.com>");
 MODULE_AUTHOR("Paul Mundt");
-MODULE_ALIAS("platform:"DRV_NAME);
+MODULE_ALIAS("platform:omap2-mailbox");
-- 
1.7.1



From felipe.contreras at gmail.com  Fri Jun 11 11:51:49 2010
From: felipe.contreras at gmail.com (Felipe Contreras)
Date: Fri, 11 Jun 2010 18:51:49 +0300
Subject: [PATCH v4 14/14] omap: mailbox: reorganize headers
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <1276271509-11983-15-git-send-email-felipe.contreras@gmail.com>

Remove kernel.h and module.h since they are not used correctly anyway.

Also, remove device.h since it comes along with platform_device.h
(always will I guess).

Signed-off-by: Felipe Contreras <felipe.contreras at gmail.com>
---
 arch/arm/mach-omap1/mailbox.c             |    3 ---
 arch/arm/mach-omap2/mailbox.c             |    1 -
 arch/arm/plat-omap/include/plat/mailbox.h |    3 ++-
 arch/arm/plat-omap/mailbox.c              |    5 ++---
 4 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-omap1/mailbox.c b/arch/arm/mach-omap1/mailbox.c
index afc3963..1a85a42 100644
--- a/arch/arm/mach-omap1/mailbox.c
+++ b/arch/arm/mach-omap1/mailbox.c
@@ -9,13 +9,10 @@
  * for more details.
  */
 
-#include <linux/kernel.h>
-#include <linux/resource.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <plat/mailbox.h>
-#include <mach/irqs.h>
 
 #define MAILBOX_ARM2DSP1		0x00
 #define MAILBOX_ARM2DSP1b		0x04
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 62d5ffe..42dbfa4 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -10,7 +10,6 @@
  * for more details.
  */
 
-#include <linux/kernel.h>
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index c44fde3..9976565 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -3,9 +3,10 @@
 #ifndef MAILBOX_H
 #define MAILBOX_H
 
-#include <linux/wait.h>
+#include <linux/spinlock.h>
 #include <linux/workqueue.h>
 #include <linux/interrupt.h>
+#include <linux/device.h>
 #include <linux/kfifo.h>
 
 typedef u32 mbox_msg_t;
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index a8e22e1..8d4c7be 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -21,10 +21,9 @@
  *
  */
 
-#include <linux/kernel.h>
-#include <linux/module.h>
 #include <linux/interrupt.h>
-#include <linux/device.h>
+#include <linux/spinlock.h>
+#include <linux/mutex.h>
 #include <linux/delay.h>
 #include <linux/slab.h>
 #include <linux/kfifo.h>
-- 
1.7.1



From marek.vasut at gmail.com  Fri Jun 11 11:52:08 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 11 Jun 2010 17:52:08 +0200
Subject: [PATCH 2/2] pxa/spitz: Rework spitz
In-Reply-To: <20100611143600.GA1307@ucw.cz>
References: <1276238740-10640-1-git-send-email-marek.vasut@gmail.com>
	<201006110852.45838.marek.vasut@gmail.com>
	<20100611143600.GA1307@ucw.cz>
Message-ID: <201006111752.08130.marek.vasut@gmail.com>

Dne P? 11. ?ervna 2010 16:36:00 Pavel Machek napsal(a):
> On Fri 2010-06-11 08:52:45, Marek Vasut wrote:
> > Dne P? 11. ?ervna 2010 08:45:40 Marek Vasut napsal(a):
> > > This huge patch mostly shuffles code. The spitz.c file contained
> > > terrible mess and needed a cleanup, here it is:
> > > 
> > > 1) Made every part modular, components are not built in if not
> > > selected. 2) Removed loads of preprocessor goo, mostly "#ifdef
> > > MACH_AKITA .... #endif" and similar code. The kernel size will grow by
> > > a few kb now, but the file is much more readable.
> > > 3) Reworked SD/CF power setting function and made it reentrant.
> > > 
> > > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> > > ---
> > > 
> > >  arch/arm/mach-pxa/include/mach/spitz.h |    2 -
> > >  arch/arm/mach-pxa/spitz.c              |  748
> > > 
> > > ++++++++++++++++++-------------- 2 files changed, 420 insertions(+),
> > > 330 deletions(-)
> > 
> > Pavel, Eric, I tested this on metan's Z, could you give it a go ?
> 
> quick test on 2.6.35-rc2 (of the 2nd version), and all seems
> well. What should I look for?
> 								Pavel

Nothing, the functionality should be the same ... I just felt like it needs 
rework, it was frustrating digging in it in the state it is in now. The way it 
is now it's much easier to hack on it. There are still open issues:

1) CPUfreq on Zaurus is still broken. (doesn't work on other devices - causes 
freezes)
2) PCMCIA driver looses interrupts. (pcmcia-sharpsl needs rework)
3) We need driver for the CPU PMIC. (I already wrote it)
4) Weird mess on the LCD when using DMA (also happens on other devices)

So we'll have at least another four following patches sometimes later.

Pavel, can we get this in? Can I get your Ack and get this one applied? Thanks


From marek.vasut at gmail.com  Fri Jun 11 11:55:27 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 11 Jun 2010 17:55:27 +0200
Subject: [PATCH 3/3] PalmZ72: Add support for OV9640 camera sensor
In-Reply-To: <AANLkTimS2Il7oMsfizddQosf6_qDa0imJ3N-FPhVz8aJ@mail.gmail.com>
References: <200908220852.06689.marek.vasut@gmail.com>
	<201004211411.37371.marek.vasut@gmail.com>
	<AANLkTimS2Il7oMsfizddQosf6_qDa0imJ3N-FPhVz8aJ@mail.gmail.com>
Message-ID: <201006111755.27382.marek.vasut@gmail.com>

Dne P? 11. ?ervna 2010 16:38:52 Eric Miao napsal(a):
> On Wed, Apr 21, 2010 at 8:11 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > Dne St 21. dubna 2010 13:44:34 Eric Miao napsal(a):
> >> On Wed, Apr 21, 2010 at 5:41 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> >> > Dne So 22. srpna 2009 08:52:06 Marek Vasut napsal(a):
> >> >> From 777212ce6d3bacea76281aa3d74839a3c38b32a4 Mon Sep 17 00:00:00
> >> >> 2001 From: Marek Vasut <marek.vasut at gmail.com>
> >> >> Date: Sat, 22 Aug 2009 05:15:10 +0200
> >> >> Subject: [PATCH 3/3] PalmZ72: Add support for OV9640 camera sensor
> >> > 
> >> > Hi, was this ever merged ?
> >> 
> >> Is the required change to ov9640 merged?
> > 
> > Looking at this more properly, this might need a revision. The ov9640
> > driver is in though.
> 
> Marek,
> 
> How's the status of the revision?

Ewwww ... I totally forgot about this one ... could you send me the original 
patch please?

Thanks!


From olof at lixom.net  Fri Jun 11 12:03:31 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri, 11 Jun 2010 11:03:31 -0500
Subject: [PATCH] ARM: Add ARCH_HAS_L2X0 and make CACHE_L2X0 config depend on
	that
In-Reply-To: <6fqujhaev78923q90va>
References: <6fqujhaev78923q90va>
Message-ID: <1276272211-13065-1-git-send-email-olof@lixom.net>

It normally scales better if each platform that has <foo> selects the
ARCH_HAS_<foo> option, instead of having to add every single one to the
depends line.

Signed-off-by: Olof Johansson <olof at lixom.net>
---
 arch/arm/Kconfig               |    2 ++
 arch/arm/mach-mx3/Kconfig      |    2 ++
 arch/arm/mach-realview/Kconfig |    5 +++++
 arch/arm/mach-vexpress/Kconfig |    1 +
 arch/arm/mm/Kconfig            |    8 +++++---
 arch/arm/plat-omap/Kconfig     |    1 +
 6 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..6800b4b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -748,6 +748,7 @@ config ARCH_U8500
 	select GENERIC_CLOCKEVENTS
 	select COMMON_CLKDEV
 	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_HAS_L2X0
 	help
 	  Support for ST-Ericsson's Ux500 architecture
 
@@ -759,6 +760,7 @@ config ARCH_NOMADIK
 	select COMMON_CLKDEV
 	select GENERIC_CLOCKEVENTS
 	select ARCH_REQUIRE_GPIOLIB
+	select ARCH_HAS_L2X0
 	help
 	  Support for the Nomadik platform by ST-Ericsson
 
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753f..a4cd462 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -3,12 +3,14 @@ if ARCH_MX3
 config ARCH_MX31
 	select ARCH_HAS_RNGA
 	select ARCH_MXC_AUDMUX_V2
+	select ARCH_HAS_L2X0
 	bool
 
 config ARCH_MX35
 	bool
 	select ARCH_MXC_IOMUX_V3
 	select ARCH_MXC_AUDMUX_V2
+	select ARCH_HAS_L2X0
 
 comment "MX3 platforms:"
 
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index ee5e392..24077e8 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -11,6 +11,7 @@ config REALVIEW_EB_A9MP
 	bool "Support Multicore Cortex-A9"
 	depends on MACH_REALVIEW_EB
 	select CPU_V7
+	select ARCH_HAS_L2X0
 	help
 	  Enable support for the Cortex-A9MPCore tile on the Realview platform.
 
@@ -18,6 +19,7 @@ config REALVIEW_EB_ARM11MP
 	bool "Support ARM11MPCore tile"
 	depends on MACH_REALVIEW_EB
 	select CPU_V6
+	select ARCH_HAS_L2X0
 	help
 	  Enable support for the ARM11MPCore tile on the Realview platform.
 
@@ -35,6 +37,7 @@ config MACH_REALVIEW_PB11MP
 	select CPU_V6
 	select ARM_GIC
 	select HAVE_PATA_PLATFORM
+	select ARCH_HAS_L2X0
 	help
 	  Include support for the ARM(R) RealView MPCore Platform Baseboard.
 	  PB11MPCore is a platform with an on-board ARM11MPCore and has
@@ -44,6 +47,7 @@ config MACH_REALVIEW_PB1176
 	bool "Support RealView/PB1176 platform"
 	select CPU_V6
 	select ARM_GIC
+	select ARCH_HAS_L2X0
 	help
 	  Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
 
@@ -72,6 +76,7 @@ config MACH_REALVIEW_PBX
 	select HAVE_PATA_PLATFORM
 	select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
 	select ZONE_DMA if SPARSEMEM
+	select ARCH_HAS_L2X0
 	help
 	  Include support for the ARM(R) RealView PBX platform.
 
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 3f19b66..8cc4281 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -5,5 +5,6 @@ config ARCH_VEXPRESS_CA9X4
 	bool "Versatile Express Cortex-A9x4 tile"
 	select CPU_V7
 	select ARM_GIC
+	select ARCH_HAS_L2X0
 
 endmenu
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..419b957 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -759,11 +759,13 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 	  Say Y here to use the Feroceon L2 cache in writethrough mode.
 	  Unless you specifically require this, say N for writeback mode.
 
+config ARCH_HAS_L2X0
+	bool
+	default n
+
 config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
-	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
-		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
+	depends on ARCH_HAS_L2X0
 	default y
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 78b49a6..2e42717 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -38,6 +38,7 @@ config ARCH_OMAP4
 	depends on ARCH_OMAP2PLUS
 	select CPU_V7
 	select ARM_GIC
+	select ARCH_HAS_L2X0
 
 endchoice
 
-- 
1.5.6.5



From dwalker at codeaurora.org  Fri Jun 11 13:58:07 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Fri, 11 Jun 2010 10:58:07 -0700
Subject: [PATCH] ARM: Add ARCH_HAS_L2X0 and make CACHE_L2X0 config
	depend on that
In-Reply-To: <1276272211-13065-1-git-send-email-olof@lixom.net>
References: <6fqujhaev78923q90va>
	<1276272211-13065-1-git-send-email-olof@lixom.net>
Message-ID: <1276279087.31800.6.camel@c-dwalke-linux.qualcomm.com>

On Fri, 2010-06-11 at 11:03 -0500, Olof Johansson wrote:

> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> index 346ae14..419b957 100644
> --- a/arch/arm/mm/Kconfig
> +++ b/arch/arm/mm/Kconfig
> @@ -759,11 +759,13 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
>  	  Say Y here to use the Feroceon L2 cache in writethrough mode.
>  	  Unless you specifically require this, say N for writeback mode.
>  
> +config ARCH_HAS_L2X0
> +	bool
> +	default n
> +

I made a similar change not too long ago, but Russell wanted the define
to be HAVE_CACHE_L2X0 ..

Daniel






From ccross at android.com  Fri Jun 11 14:54:29 2010
From: ccross at android.com (Colin Cross)
Date: Fri, 11 Jun 2010 11:54:29 -0700
Subject: [PATCH 05/10] [ARM] tegra: Add timer support
In-Reply-To: <AANLkTilitoPKhSCk1gxwyzOdu8LZD-9xA3EesFKkDsLy@mail.gmail.com>
References: <1275635441-17378-1-git-send-email-olof@lixom.net>
	<1275635441-17378-2-git-send-email-olof@lixom.net>
	<1275635441-17378-3-git-send-email-olof@lixom.net>
	<1275635441-17378-4-git-send-email-olof@lixom.net>
	<1275635441-17378-5-git-send-email-olof@lixom.net>
	<1275635441-17378-6-git-send-email-olof@lixom.net>
	<AANLkTilitoPKhSCk1gxwyzOdu8LZD-9xA3EesFKkDsLy@mail.gmail.com>
Message-ID: <AANLkTiketaVq4PBc9FTr6RgVO038twXXF7BMU0W8GsH5@mail.gmail.com>

On Mon, Jun 7, 2010 at 4:43 PM, Linus Walleij
<linus.ml.walleij at gmail.com> wrote:
> 2010/6/4 Olof Johansson <olof at lixom.net>:
>
>> (....)
>> +static struct clock_event_device tegra_clockevent = {
>> + ? ? ? .name ? ? ? ? ? = "timer0",
>> + ? ? ? .rating ? ? ? ? = 300,
>> + ? ? ? .features ? ? ? = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
>> + ? ? ? .mult ? ? ? ? ? = 16777,
>> + ? ? ? .shift ? ? ? ? ?= 24,
>> + ? ? ? .set_next_event = tegra_timer_set_next_event,
>> + ? ? ? .set_mode ? ? ? = tegra_timer_set_mode,
>> +};
>> +
>> +static struct clocksource tegra_clocksource = {
>> + ? ? ? .name ? = "timer_us",
>> + ? ? ? .rating = 300,
>> + ? ? ? .read ? = tegra_clocksource_read,
>> + ? ? ? .mask ? = 0xFFFFFFFFUL,
>> + ? ? ? .mult ? = 1000,
>> + ? ? ? .shift ?= 0,
>> + ? ? ? .flags ?= CLOCK_SOURCE_IS_CONTINUOUS,
>> +};
>
> How did you calculate the magic mult/shift numbers 16777/24 and
> 1000/0 above? Especially the latter intuitively seem very inappropriate,
> and I guess there will be revisions of this platform with new frequencies
> for the timer as well, making these hard-coded values a bug source.

Thanks, fixed.  The numbers are correct, as Tegra timers all run at
1MHz regardless of input clock frequency, but removing the magic
numbers is clearer.

For the clocksource, I replaced it with clocksource_register_hz, which
hides the minsec number as well. Clockevents I replaced iwth
clockevents_calc_mult_shift.

> I would consider using the
> clocksource_calc_mult_shift() and
> clockevents_calc_mult_shift()
> functions based on the frequency of the timer counter and a minimum wakeup
> range if you don't know exactly why you want these mult+shifts.
>
> I posted some patches to encourage the use of these recently.
>
> Yours,
> Linus Walleij
>


From mcuelenaere at gmail.com  Fri Jun 11 15:48:37 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 21:48:37 +0200
Subject: [RFC/PATCH 0/9] Samsung crypto engine
Message-ID: <4C129315.4030404@gmail.com>

Hi all,

this patchset introduces crypto acceleration support for the crypto engine
available in S3C64XX and S5PC100 SoC's. I only have access to a S3C6410 board so
it would be nice if people could test these patches on S5PC100.

The driver currently only supports AES and (T)DES in PIO mode, but even then it
doesn't always succeed the DES self-tests so the driver part of this patch is
more an RFC than an actual patch.

AES seems to work better than (T)DES, but it hangs on 64-bytes transfers (DES
hangs on a 24-byte transfer).

There is support for DMA in the driver, but that has its own set of problems (it
can't even finish a single transfer).

I've tagged the patches I think are worthy for upstreaming with [PATCH], the
others are tagged with [RFC] (reviews are welcome!).

I'm not completely sure about my approach of handling the subsystems' register
offsets currently as this limits the driver to S3C64XX- or S5PC100-only.

Mapping these to virtual space could solve this and would have the benefit of
reducing the ~11MB IO space on S3C64XX SoC's.

Maurus Cuelenaere (9):
  ARM: S3C64XX: Add SDMA clocks
  ARM: S3C64XX: Add SDMA support to DMA core
  ARM: S3C64XX: Stop and flush requests on freeing
  ARM: S3C64XX: Add support for secur clock
  ARM: S3C64XX: Add crypto engine register definitions
  ARM: S5PC100: Add crypto engine register definitions
  ARM: SAMSUNG: Add crypto engine platform definition
  ARM: SAMSUNG: Add crypto engine register definitions
  crypto: Add Samsung crypto engine driver

 arch/arm/Kconfig                              |    2 +
 arch/arm/mach-s3c64xx/clock.c                 |   21 +
 arch/arm/mach-s3c64xx/dma.c                   |   54 +-
 arch/arm/mach-s3c64xx/include/mach/map.h      |    3 +
 arch/arm/mach-s3c64xx/include/mach/regs-sss.h |   27 +
 arch/arm/mach-s5pc100/include/mach/map.h      |    4 +
 arch/arm/mach-s5pc100/include/mach/regs-sss.h |   29 +
 arch/arm/plat-samsung/Kconfig                 |    5 +
 arch/arm/plat-samsung/Makefile                |    1 +
 arch/arm/plat-samsung/dev-sss.c               |   46 +
 arch/arm/plat-samsung/include/plat/devs.h     |    2 +
 arch/arm/plat-samsung/include/plat/regs-sss.h |  153 +++
 drivers/crypto/Kconfig                        |   11 +
 drivers/crypto/Makefile                       |    1 +
 drivers/crypto/s3c-sss.c                      | 1320 +++++++++++++++++++++++++
 15 files changed, 1668 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/mach-s3c64xx/include/mach/regs-sss.h
 create mode 100644 arch/arm/mach-s5pc100/include/mach/regs-sss.h
 create mode 100644 arch/arm/plat-samsung/dev-sss.c
 create mode 100644 arch/arm/plat-samsung/include/plat/regs-sss.h
 create mode 100644 drivers/crypto/s3c-sss.c



From mcuelenaere at gmail.com  Fri Jun 11 15:48:42 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 21:48:42 +0200
Subject: [PATCH 1/9] ARM: S3C64XX: Add SDMA clocks
In-Reply-To: <cover.1276284559.git.mcuelenaere@gmail.com>
References: <cover.1276284559.git.mcuelenaere@gmail.com>
Message-ID: <4C12931A.7010500@gmail.com>

This adds the clock definition bits for SDMA.

Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
---
 arch/arm/mach-s3c64xx/clock.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 7a4138b..d3e11a1 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -218,6 +218,18 @@ static struct clk init_clocks_disable[] = {
 		.parent		= &clk_h,
 		.enable		= s3c64xx_hclk_ctrl,
 		.ctrlbit	= S3C_CLKCON_HCLK_DMA1,
+	}, {
+		.name		= "sdma0",
+		.id		= -1,
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_SDMA0,
+	}, {
+		.name		= "sdma1",
+		.id		= -1,
+		.parent		= &clk_h,
+		.enable		= s3c64xx_hclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_HCLK_SDMA1,
 	},
 };
 
-- 
1.7.1




From mcuelenaere at gmail.com  Fri Jun 11 15:48:47 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 21:48:47 +0200
Subject: [PATCH 2/9] ARM: S3C64XX: Add SDMA support to DMA core
In-Reply-To: <cover.1276284559.git.mcuelenaere@gmail.com>
References: <cover.1276284559.git.mcuelenaere@gmail.com>
Message-ID: <4C12931F.7020105@gmail.com>

The crypto engine uses the DMACH_SECURITY_[RT]X channels, who seem to be
hardcoded to SDMA-only in hardware, so add support for SDMA to the S3C64XX
DMA core.

Only DMACH_SECURITY_[RT]X are using SDMA, other channels are unaffected and
will continue to use standard DMA.

Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
---
 arch/arm/mach-s3c64xx/dma.c |   51 ++++++++++++++++++++++++++++++++++--------
 1 files changed, 41 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 5567e03..be043db 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -45,6 +45,15 @@ struct s3c64xx_dmac {
 /* pool to provide LLI buffers */
 static struct dma_pool *dma_pool;
 
+/* SDMA channel state information */
+static struct s3c2410_dma_chan sdma_chans[S3C_DMA_CHANNELS];
+
+/* Currently hardcodes SECURITY_[RT]X SDMA-only as dictated by HW */
+static inline bool channel_needs_sdma(unsigned int chan)
+{
+	return chan == DMACH_SECURITY_RX || chan == DMACH_SECURITY_TX;
+}
+
 /* Debug configuration and code */
 
 static unsigned char debug_show_buffs = 0;
@@ -92,16 +101,20 @@ static void dbg_showbuffs(struct s3c2410_dma_chan *chan)
 
 static struct s3c2410_dma_chan *s3c64xx_dma_map_channel(unsigned int channel)
 {
+	struct s3c2410_dma_chan *chans = s3c2410_chans;
 	struct s3c2410_dma_chan *chan;
 	unsigned int start, offs;
 
+	if (channel_needs_sdma(channel))
+		chans = sdma_chans;
+
 	start = 0;
 
 	if (channel >= DMACH_PCM1_TX)
 		start = 8;
 
 	for (offs = 0; offs < 8; offs++) {
-		chan = &s3c2410_chans[start + offs];
+		chan = &chans[start + offs];
 		if (!chan->in_use)
 			goto found;
 	}
@@ -634,8 +647,12 @@ static struct sysdev_class dma_sysclass = {
 	.name		= "s3c64xx-dma",
 };
 
+static struct sysdev_class sdma_sysclass = {
+	.name		= "s3c64xx-sdma",
+};
+
 static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
-			     int irq, unsigned int base)
+			     int irq, unsigned int base, bool sdma)
 {
 	struct s3c2410_dma_chan *chptr = &s3c2410_chans[chno];
 	struct s3c64xx_dmac *dmac;
@@ -651,7 +668,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
 	}
 
 	dmac->sysdev.id = chno / 8;
-	dmac->sysdev.cls = &dma_sysclass;
+	dmac->sysdev.cls = sdma ? &sdma_sysclass : &dma_sysclass;
 
 	err = sysdev_register(&dmac->sysdev);
 	if (err) {
@@ -666,7 +683,11 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
 		goto err_dev;
 	}
 
-	snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id);
+	if (sdma) {
+		snprintf(clkname, sizeof(clkname), "sdma%d", dmac->sysdev.id);
+		chptr = &sdma_chans[chno];
+	} else
+		snprintf(clkname, sizeof(clkname), "dma%d", dmac->sysdev.id);
 
 	dmac->clk = clk_get(NULL, clkname);
 	if (IS_ERR(dmac->clk)) {
@@ -690,8 +711,8 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
 	regptr = regs + PL080_Cx_BASE(0);
 
 	for (ch = 0; ch < 8; ch++, chno++, chptr++) {
-		printk(KERN_INFO "%s: registering DMA %d (%p)\n",
-		       __func__, chno, regptr);
+		printk(KERN_INFO "%s: registering %sDMA %d (%p)\n",
+		       __func__, sdma ? "S" : "", chno, regptr);
 
 		chptr->bit = 1 << ch;
 		chptr->number = chno;
@@ -737,12 +758,22 @@ static int __init s3c64xx_dma_init(void)
 		return -ENOMEM;
 	}
 
-	/* Set all DMA configuration to be DMA, not SDMA */
-	writel(0xffffff, S3C_SYSREG(0x110));
+	ret = sysdev_class_register(&sdma_sysclass);
+	if (ret) {
+		printk(KERN_ERR "%s: failed to create sysclass\n", __func__);
+		return -ENOMEM;
+	}
+
+	/* Set all DMA configuration to be DMA, except SECURITY_[RT]X */
+	writel(0x3fffffff, S3C_SYSREG(0x110));
 
 	/* Register standard DMA controlers */
-	s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000);
-	s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000);
+	s3c64xx_dma_init1(0, DMACH_UART0, IRQ_DMA0, 0x75000000, false);
+	s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_DMA1, 0x75100000, false);
+
+	/* Register SDMA controllers */
+	s3c64xx_dma_init1(0, DMACH_UART0, IRQ_SDMA0, 0x7DB00000, true);
+	s3c64xx_dma_init1(8, DMACH_PCM1_TX, IRQ_SDMA1, 0x7DC00000, true);
 
 	return 0;
 }
-- 
1.7.1




From mcuelenaere at gmail.com  Fri Jun 11 15:48:51 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 21:48:51 +0200
Subject: [PATCH 3/9] ARM: S3C64XX: Stop and flush requests on freeing
In-Reply-To: <cover.1276284559.git.mcuelenaere@gmail.com>
References: <cover.1276284559.git.mcuelenaere@gmail.com>
Message-ID: <4C129323.2030101@gmail.com>

When a DMA channel is freed, its pending requests should be flushed and the
channel should be halted. This patch ensures that happens.

Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
---
 arch/arm/mach-s3c64xx/dma.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index be043db..48cbfbc 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -560,7 +560,8 @@ int s3c2410_dma_free(unsigned int channel, struct s3c2410_dma_client *client)
 		       channel, chan->client, client);
 	}
 
-	/* sort out stopping and freeing the channel */
+	s3c64xx_dma_flush(chan);
+	s3c64xx_dma_stop(chan);
 
 
 	chan->client = NULL;
-- 
1.7.1




From mcuelenaere at gmail.com  Fri Jun 11 15:48:56 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 21:48:56 +0200
Subject: [PATCH 4/9] ARM: S3C64XX: Add support for secur clock
In-Reply-To: <cover.1276284559.git.mcuelenaere@gmail.com>
References: <cover.1276284559.git.mcuelenaere@gmail.com>
Message-ID: <4C129328.7090400@gmail.com>

This patch adds correct register definitions for the secur clock, used by the
Samsung crypto engine.

Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
---
 arch/arm/mach-s3c64xx/clock.c |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index d3e11a1..8cbe949 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -716,6 +716,15 @@ static struct clksrc_clk clksrcs[] = {
 		.reg_div	= { .reg = S3C_CLK_DIV0, .shift = 20, .size = 4  },
 		.reg_src	= { .reg = NULL, .shift = 0, .size = 0  },
 		.sources	= &clkset_camif,
+	},  {
+		.clk	= {
+			.name		= "secur",
+			.id		= -1,
+			.ctrlbit	= S3C_CLKCON_SCLK_SECUR,
+			.enable		= s3c64xx_sclk_ctrl,
+			.parent		= &clk_h2,
+		},
+		.reg_div	= { .reg = S3C_CLK_DIV0, .shift = 18, .size = 2 },
 	},
 };
 
-- 
1.7.1




From mcuelenaere at gmail.com  Fri Jun 11 15:49:05 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 21:49:05 +0200
Subject: [PATCH 6/9] ARM: S5PC100: Add crypto engine register definitions
In-Reply-To: <cover.1276284559.git.mcuelenaere@gmail.com>
References: <cover.1276284559.git.mcuelenaere@gmail.com>
Message-ID: <4C129331.7000001@gmail.com>

This patch adds the physical address and size which corresponds to the crypto
engine on the S5PC100. It also adds the offsets for the crypto subsystems.

Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
---
 arch/arm/mach-s5pc100/include/mach/map.h      |    4 +++
 arch/arm/mach-s5pc100/include/mach/regs-sss.h |   29 +++++++++++++++++++++++++
 2 files changed, 33 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc100/include/mach/regs-sss.h

diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 4681ebe..1d842b5 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -116,6 +116,10 @@
 #define S5PC100_PA_SDRAM	(0x20000000)
 #define S5PC1XX_PA_SDRAM	S5PC100_PA_SDRAM
 
+/* Crypto Engine */
+#define SAMSUNG_PA_SSS		(0xF4000000)
+#define SAMSUNG_SZ_SSS		(SZ_1M * 3 + SZ_64K)
+
 /* compatibility defines. */
 #define S3C_PA_RTC		S5PC100_PA_RTC
 #define S3C_PA_UART		S5PC100_PA_UART
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-sss.h b/arch/arm/mach-s5pc100/include/mach/regs-sss.h
new file mode 100644
index 0000000..41b3e6b
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/regs-sss.h
@@ -0,0 +1,29 @@
+/*
+ * linux/arch/arm/mach-s5pc100/include/mach/regs-sss.h
+ *
+ * Copyright (C) 2010 Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __MACH_S5PC100_REGS_SSS_H
+#define __MACH_S5PC100_REGS_SSS_H __FILE__
+
+#define SSS_OFF_CFG				(0x000000)
+#define SSS_OFF_FIFO_RX				(0x010000)
+#define SSS_OFF_AES_RX				(0x040000)
+#define SSS_OFF_TDES_RX				(0x050000)
+#define SSS_OFF_HASH_RX				(0x060000)
+
+#define SSS_OFF_FIFO_TX				(0x110000)
+#define SSS_OFF_AES_TX				(0x140000)
+#define SSS_OFF_TDES_TX				(0x150000)
+#define SSS_OFF_HASH_TX				(0x160000)
+
+#define SSS_OFF_SDMA_RX				(0x200000)
+#define SSS_OFF_SDMA_TX				(0x300000)
+
+#endif /* __MACH_S5PC100_REGS_SSS_H */
-- 
1.7.1




From mcuelenaere at gmail.com  Fri Jun 11 15:49:00 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 21:49:00 +0200
Subject: [PATCH 5/9] ARM: S3C64XX: Add crypto engine register definitions
In-Reply-To: <cover.1276284559.git.mcuelenaere@gmail.com>
References: <cover.1276284559.git.mcuelenaere@gmail.com>
Message-ID: <4C12932C.8060803@gmail.com>

This patch adds the physical address and size which corresponds to the crypto
engine on the S3C64XX. It also adds the offsets for the crypto subsystems.

Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
---
 arch/arm/mach-s3c64xx/include/mach/map.h      |    3 ++
 arch/arm/mach-s3c64xx/include/mach/regs-sss.h |   27 +++++++++++++++++++++++++
 2 files changed, 30 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s3c64xx/include/mach/regs-sss.h

diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 9fdd50c..fa80afc 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -87,6 +87,9 @@
 #define S3C64XX_PA_USB_HSPHY	(0x7C100000)
 #define S3C64XX_VA_USB_HSPHY	S3C_ADDR_CPU(0x00200000)
 
+#define SAMSUNG_PA_SSS		(0x7D000000)
+#define SAMSUNG_SZ_SSS		(SZ_1M * 10 + SZ_256)
+
 /* place VICs close together */
 #define VA_VIC0			(S3C_VA_IRQ + 0x00)
 #define VA_VIC1			(S3C_VA_IRQ + 0x10000)
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-sss.h b/arch/arm/mach-s3c64xx/include/mach/regs-sss.h
new file mode 100644
index 0000000..3a0769f
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/regs-sss.h
@@ -0,0 +1,27 @@
+/*
+ * linux/arch/arm/mach-s3c64xx/include/mach/regs-sss.h
+ *
+ * Copyright (C) 2010 Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __MACH_S3C64XX_REGS_SSS_H
+#define __MACH_S3C64XX_REGS_SSS_H __FILE__
+
+#define SSS_OFF_CFG				(0x000000)
+#define SSS_OFF_AES_RX				(0x100000)
+#define SSS_OFF_TDES_RX				(0x200000)
+#define SSS_OFF_HASH_RX				(0x300000)
+#define SSS_OFF_FIFO_RX				(0x400000)
+#define SSS_OFF_AES_TX				(0x500000)
+#define SSS_OFF_TDES_TX				(0x600000)
+#define SSS_OFF_HASH_TX				(0x700000)
+#define SSS_OFF_FIFO_TX				(0x800000)
+#define SSS_OFF_SDMA_RX				(0x900000)
+#define SSS_OFF_SDMA_TX				(0xA00000)
+
+#endif /* __MACH_S3C64XX_REGS_SSS_H */
-- 
1.7.1




From mcuelenaere at gmail.com  Fri Jun 11 15:49:10 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 21:49:10 +0200
Subject: [PATCH 7/9] ARM: SAMSUNG: Add crypto engine platform definition
In-Reply-To: <cover.1276284559.git.mcuelenaere@gmail.com>
References: <cover.1276284559.git.mcuelenaere@gmail.com>
Message-ID: <4C129336.4000703@gmail.com>

This patch adds the platform device used by the crypto engine driver.

Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
---
 arch/arm/Kconfig                          |    2 +
 arch/arm/plat-samsung/Kconfig             |    5 +++
 arch/arm/plat-samsung/Makefile            |    1 +
 arch/arm/plat-samsung/dev-sss.c           |   46 +++++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h |    2 +
 5 files changed, 56 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-samsung/dev-sss.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3f8718f..3e80510 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -680,6 +680,7 @@ config ARCH_S3C64XX
 	select S3C_DEV_NAND
 	select USB_ARCH_HAS_OHCI
 	select SAMSUNG_GPIOLIB_4BIT
+	select SAMSUNG_DEV_SSS
 	help
 	  Samsung S3C64XX series based systems
 
@@ -705,6 +706,7 @@ config ARCH_S5PC1XX
 	select HAVE_CLK
 	select CPU_V7
 	select ARM_L1_CACHE_SHIFT_6
+	select SAMSUNG_DEV_SSS
 	help
 	  Samsung S5PC1XX series based systems
 
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 229919e..c001d54 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -211,6 +211,11 @@ config SAMSUNG_DEV_TS
 	help
 	    Common in platform device definitions for touchscreen device
 
+config SAMSUNG_DEV_SSS
+	bool
+	help
+	    Compile in platform device definitions for Security Sub-Systems
+
 # DMA
 
 config S3C_DMA
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 4828849..43a3c64 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_S3C_DEV_RTC)	+= dev-rtc.o
 
 obj-$(CONFIG_SAMSUNG_DEV_ADC)	+= dev-adc.o
 obj-$(CONFIG_SAMSUNG_DEV_TS)	+= dev-ts.o
+obj-$(CONFIG_SAMSUNG_DEV_SSS)	+= dev-sss.o
 
 # DMA support
 
diff --git a/arch/arm/plat-samsung/dev-sss.c b/arch/arm/plat-samsung/dev-sss.c
new file mode 100644
index 0000000..6c662a1
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-sss.c
@@ -0,0 +1,46 @@
+/* linux/arch/arm/plat-samsung/dev-sss.c
+ *
+ * Copyright (c) 2010 Maurus Cuelenaere
+ *
+ * Based on arch/arm/plat-samsung/dev-hsmmc1.c
+ * original file Copyright (c) 2008 Simtec Electronics
+ *
+ * Samsung series device definition for security sub-system
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/devs.h>
+
+static struct resource s3c_sss_resource[] = {
+	{
+		.start = SAMSUNG_PA_SSS,
+		.end   = SAMSUNG_PA_SSS + SAMSUNG_SZ_SSS - 1,
+		.flags = IORESOURCE_MEM,
+	}, {
+		.start = IRQ_SEC,
+		.end   = IRQ_SEC,
+		.flags = IORESOURCE_IRQ,
+	}
+};
+
+static u64 s3c_device_sss_dmamask = 0xffffffffUL;
+
+struct platform_device s3c_device_sss = {
+	.name		= "s3c-sss",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(s3c_sss_resource),
+	.resource	= s3c_sss_resource,
+	.dev		= {
+		.dma_mask		= &s3c_device_sss_dmamask,
+		.coherent_dma_mask	= 0xffffffffUL,
+	},
+};
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index ef69e56..c689fae 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -64,6 +64,8 @@ extern struct platform_device s3c_device_nand;
 extern struct platform_device s3c_device_usbgadget;
 extern struct platform_device s3c_device_usb_hsotg;
 
+extern struct platform_device s3c_device_sss;
+
 extern struct platform_device s5pv210_device_ac97;
 extern struct platform_device s5pv210_device_pcm0;
 extern struct platform_device s5pv210_device_pcm1;
-- 
1.7.1




From hartleys at visionengravers.com  Fri Jun 11 20:09:41 2010
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Fri, 11 Jun 2010 19:09:41 -0500
Subject: [PATCH] ep93xx: clear devcfg bits before setting them
Message-ID: <0D753D10438DA54287A00B027084269763711321BA@AUSP01VMBX24.collaborationhost.net>

The ep93xx core helper function ep93xx_devcfg_set_clear should mask the
clear_bits before setting the new set_bits in case the clear_bits are a
mask value that also includes the set_bits.

Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
Cc: Ryan Mallon <ryan at bluewatersys.com>

---

diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 9092677..92f2ebb 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -215,8 +215,8 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
 	spin_lock_irqsave(&syscon_swlock, flags);
 
 	val = __raw_readl(EP93XX_SYSCON_DEVCFG);
-	val |= set_bits;
 	val &= ~clear_bits;
+	val |= set_bits;
 	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
 	__raw_writel(val, EP93XX_SYSCON_DEVCFG);
 

From ben-linux at fluff.org  Fri Jun 11 23:34:29 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Sat, 12 Jun 2010 04:34:29 +0100
Subject: s3c-hsotg fixes
In-Reply-To: <006c01cb0950$6ced3630$46c7a290$%szyprowski@samsung.com>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
	<006c01cb0950$6ced3630$46c7a290$%szyprowski@samsung.com>
Message-ID: <20100612033429.GJ3498@trinity.fluff.org>

On Fri, Jun 11, 2010 at 12:25:26PM +0200, Marek Szyprowski wrote:
> Hello,
> 
> On Friday, June 11, 2010 10:21 AM Ben Dooks wrote:
> 
> > Some further fixes for the s3c-hsotg block, as well as a repost of
> > the missed USB phy clock setting patch which either got missed or
> > passed over from last time.
> > 
> > As a note, this series has a patch adding support for dedicated FIFO
> > mode, this is in my view a fix, as when the hsotg block is compiled
> > with dedicated fifos then each USB IN non-periodic pipe needs to be
> > alloacted a unique TX FIFO. We have no actual data on how well the
> > block performs when all IN TX NP FIFOs are all set to the same one,
> > but it really should be fixed.
> 
> This patch series improves the driver a lot. Now it is possible to get
> CDC Ethernet gadget working on S5PV210 SoC (Samsung Aquila machine).
> However there are still some issues left to be resolved. I've noticed
> the following things:
> 
> 1. CDC Ethernet gadget: there are problems after unplugging and 
> plugging the usb cable again while data is being transferred. To trigger
> this it is enough to run 'ping host' command on the device and replug
> the usb cable. After that no data packets are sent do the usb host
> (checked with hardware usb analyser), although the ep0 control transfers
> are performed correctly (device has been enumerated correctly).

Hmm, that is intereting. Maybe we broke non-ep0 fifos somehow
 
> 2. RNDIS Ethernet gadget: after some stress tests I get an error, which
> causes RNDIS session to hang (what is probably a direct result of the
> otg block reinit/reset). Here is an example log:

any particular kind of stress tests, or are you just telling it nasty
things to upset it? will try and look into this too.

 
> [   69.155000] s3c-hsotg s3c-hsotg: s3c_hsotg_handle_rx: unknown status 00000000
> [   69.155000] s3c-hsotg s3c-hsotg: DCFG=0x00040020, DCTL=0x00000000,
> DIEPMSK=000000af
> [   69.155000] s3c-hsotg s3c-hsotg: GAHBCFG=0x00000001, 0x44=0x00000000
> [   69.155000] s3c-hsotg s3c-hsotg: GRXFSIZ=0x00000800, GNPTXFSIZ=0x04000800
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[1] FSize=768, StAddr=0x00000f00
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[2] FSize=768, StAddr=0x00001200
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[3] FSize=768, StAddr=0x00001500
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[4] FSize=768, StAddr=0x00001800
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[5] FSize=768, StAddr=0x00001b00
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[6] FSize=768, StAddr=0x00001e00
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[7] FSize=768, StAddr=0x00002100
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[8] FSize=768, StAddr=0x00002400
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[9] FSize=768, StAddr=0x00002700
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[10] FSize=768, StAddr=0x00002a00
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[11] FSize=768, StAddr=0x00002d00
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[12] FSize=768, StAddr=0x00003000
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[13] FSize=768, StAddr=0x00003300
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[14] FSize=768, StAddr=0x00003600
> [   69.155000] s3c-hsotg s3c-hsotg: DPTx[15] FSize=768, StAddr=0x00003900
> [   69.155000] s3c-hsotg s3c-hsotg: ep0-in: EPCTL=0x00028000, SIZ=0x00000000,
> DMA=0x085290ed
> [   69.155000] s3c-hsotg s3c-hsotg: ep0-out: EPCTL=0x80028000, SIZ=0x60000000,
> DMA=0xca625c65
> [   69.155000] s3c-hsotg s3c-hsotg: ep1-in: EPCTL=0x00488200, SIZ=0x20000000,
> DMA=0x5f9184b4
> [   69.155000] s3c-hsotg s3c-hsotg: ep1-out: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0x318b408d
> [   69.155000] s3c-hsotg s3c-hsotg: ep2-in: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0x50d8cf8b
> [   69.155000] s3c-hsotg s3c-hsotg: ep2-out: EPCTL=0x800b8200, SIZ=0x00180800,
> DMA=0x5792d85e
> [   69.155000] s3c-hsotg s3c-hsotg: ep3-in: EPCTL=0x00cc8008, SIZ=0x00000000,
> DMA=0x5dee1680
> [   69.155000] s3c-hsotg s3c-hsotg: ep3-out: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0xa96c912b
> [   69.155000] s3c-hsotg s3c-hsotg: ep4-in: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0x5e84ae7a
> [   69.155000] s3c-hsotg s3c-hsotg: ep4-out: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0xef2e9c78
> [   69.155000] s3c-hsotg s3c-hsotg: ep5-in: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0x9d8f4d72
> [   69.155000] s3c-hsotg s3c-hsotg: ep5-out: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0x93e82a21
> [   69.155000] s3c-hsotg s3c-hsotg: ep6-in: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0x202acadf
> [   69.155000] s3c-hsotg s3c-hsotg: ep6-out: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0x5520c3c9
> [   69.155000] s3c-hsotg s3c-hsotg: ep7-in: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0x782200c2
> [   69.155000] s3c-hsotg s3c-hsotg: ep7-out: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0xeb0b8035
> [   69.155000] s3c-hsotg s3c-hsotg: ep8-in: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0x002de535
> [   69.155000] s3c-hsotg s3c-hsotg: ep8-out: EPCTL=0x00000200, SIZ=0x00000000,
> DMA=0x8c0b77f7
> [   69.155000] s3c-hsotg s3c-hsotg: ep9-in: EPCTL=0x00000000, SIZ=0x00000000,
> DMA=0xa59e32a0
> [   69.155000] s3c-hsotg s3c-hsotg: ep9-out: EPCTL=0x00000000, SIZ=0x00000000,
> DMA=0x07aa36a2
> [   69.155000] s3c-hsotg s3c-hsotg: ep10-in: EPCTL=0x00000000, SIZ=0x00000000,
> DMA=0xc6732fd5
> [   69.155000] s3c-hsotg s3c-hsotg: ep10-out: EPCTL=0x00000000, SIZ=0x00000000,
> DMA=0xfbf3f43d
> [   69.155000] s3c-hsotg s3c-hsotg: ep11-in: EPCTL=0x00000000, SIZ=0x00000000,
> DMA=0xb1d750a4
> [   69.155000] s3c-hsotg s3c-hsotg: ep11-out: EPCTL=0x00000000, SIZ=0x00000000,
> DMA=0x30024c06
> [   69.155000] s3c-hsotg s3c-hsotg: ep12-in: EPCTL=0x00000000, SIZ=0x00000000,
> DMA=0x154162af
> [   69.155000] s3c-hsotg s3c-hsotg: ep12-out: EPCTL=0x00000000, SIZ=0x00000000,
> DMA=0x60f9ef07
> [   69.155000] s3c-hsotg s3c-hsotg: ep13-in: EPCTL=0x00000000, SIZ=0x00000000,
> DMA=0xbea16bb2
> [   69.155000] s3c-hsotg s3c-hsotg: ep13-out: EPCTL=0x00000000, SIZ=0x00000000,
> DMA=0xd1723f0c
> [   69.155000] s3c-hsotg s3c-hsotg: ep14-in: EPCTL=0x00000000, SIZ=0x00000000,
> DMA=0x40d1795b
> [   69.155000] s3c-hsotg s3c-hsotg: ep14-out: EPCTL=0x00000000, SIZ=0x00000000,
> DMA=0xc0b155d6
> [   69.155000] s3c-hsotg s3c-hsotg: DVBUSDIS=0x00000b8f, DVBUSPULSE=000002c6
> 
> I will try to investigate these issues further.
> 
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
> 
> 

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From olof at lixom.net  Sat Jun 12 00:13:17 2010
From: olof at lixom.net (Olof Johansson)
Date: Fri, 11 Jun 2010 23:13:17 -0500
Subject: [PATCH v2] ARM: Add HAVE_CACHE_L2X0
In-Reply-To: <1276279087.31800.6.camel@c-dwalke-linux.qualcomm.com>
References: <1276272211-13065-1-git-send-email-olof@lixom.net>
	<1276279087.31800.6.camel@c-dwalke-linux.qualcomm.com>
Message-ID: <20100612041317.GA23571@lixom.net>

It normally scales better if each platform that has <foo> selects the
HAVE_<foo> option, instead of having to add every single one to the
depends line for CONFIG_<foo>.

Signed-off-by: Olof Johansson <olof at lixom.net>

---

On Fri, Jun 11, 2010 at 10:58:07AM -0700, Daniel Walker wrote:

> I made a similar change not too long ago, but Russell wanted the define
> to be HAVE_CACHE_L2X0 ..

Ah, I missed it. I'm not attached to the option name so since I didn't
see you repost, here's my version... :)


-Olof

---

 arch/arm/Kconfig               |    2 ++
 arch/arm/mach-mx3/Kconfig      |    2 ++
 arch/arm/mach-realview/Kconfig |    5 +++++
 arch/arm/mach-vexpress/Kconfig |    1 +
 arch/arm/mm/Kconfig            |    8 +++++---
 arch/arm/plat-omap/Kconfig     |    1 +
 6 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..fee073d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -748,6 +748,7 @@ config ARCH_U8500
 	select GENERIC_CLOCKEVENTS
 	select COMMON_CLKDEV
 	select ARCH_REQUIRE_GPIOLIB
+	select HAVE_CACHE_L2X0
 	help
 	  Support for ST-Ericsson's Ux500 architecture
 
@@ -759,6 +760,7 @@ config ARCH_NOMADIK
 	select COMMON_CLKDEV
 	select GENERIC_CLOCKEVENTS
 	select ARCH_REQUIRE_GPIOLIB
+	select HAVE_CACHE_L2X0
 	help
 	  Support for the Nomadik platform by ST-Ericsson
 
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753f..103cad3 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -3,12 +3,14 @@ if ARCH_MX3
 config ARCH_MX31
 	select ARCH_HAS_RNGA
 	select ARCH_MXC_AUDMUX_V2
+	select HAVE_CACHE_L2X0
 	bool
 
 config ARCH_MX35
 	bool
 	select ARCH_MXC_IOMUX_V3
 	select ARCH_MXC_AUDMUX_V2
+	select HAVE_CACHE_L2X0
 
 comment "MX3 platforms:"
 
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index ee5e392..f188ea3 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -11,6 +11,7 @@ config REALVIEW_EB_A9MP
 	bool "Support Multicore Cortex-A9"
 	depends on MACH_REALVIEW_EB
 	select CPU_V7
+	select HAVE_CACHE_L2X0
 	help
 	  Enable support for the Cortex-A9MPCore tile on the Realview platform.
 
@@ -18,6 +19,7 @@ config REALVIEW_EB_ARM11MP
 	bool "Support ARM11MPCore tile"
 	depends on MACH_REALVIEW_EB
 	select CPU_V6
+	select HAVE_CACHE_L2X0
 	help
 	  Enable support for the ARM11MPCore tile on the Realview platform.
 
@@ -35,6 +37,7 @@ config MACH_REALVIEW_PB11MP
 	select CPU_V6
 	select ARM_GIC
 	select HAVE_PATA_PLATFORM
+	select HAVE_CACHE_L2X0
 	help
 	  Include support for the ARM(R) RealView MPCore Platform Baseboard.
 	  PB11MPCore is a platform with an on-board ARM11MPCore and has
@@ -44,6 +47,7 @@ config MACH_REALVIEW_PB1176
 	bool "Support RealView/PB1176 platform"
 	select CPU_V6
 	select ARM_GIC
+	select HAVE_CACHE_L2X0
 	help
 	  Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
 
@@ -72,6 +76,7 @@ config MACH_REALVIEW_PBX
 	select HAVE_PATA_PLATFORM
 	select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
 	select ZONE_DMA if SPARSEMEM
+	select HAVE_CACHE_L2X0
 	help
 	  Include support for the ARM(R) RealView PBX platform.
 
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 3f19b66..97d8592 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -5,5 +5,6 @@ config ARCH_VEXPRESS_CA9X4
 	bool "Versatile Express Cortex-A9x4 tile"
 	select CPU_V7
 	select ARM_GIC
+	select HAVE_CACHE_L2X0
 
 endmenu
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..14d25f3 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -759,11 +759,13 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 	  Say Y here to use the Feroceon L2 cache in writethrough mode.
 	  Unless you specifically require this, say N for writeback mode.
 
+config HAVE_CACHE_L2X0
+	bool
+	default n
+
 config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
-	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
-		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
+	depends on HAVE_CACHE_L2X0
 	default y
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 78b49a6..e7972d9 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -38,6 +38,7 @@ config ARCH_OMAP4
 	depends on ARCH_OMAP2PLUS
 	select CPU_V7
 	select ARM_GIC
+	select HAVE_CACHE_L2X0
 
 endchoice
 
-- 
1.5.6.5



From benh at kernel.crashing.org  Sat Jun 12 01:10:49 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Sat, 12 Jun 2010 15:10:49 +1000
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19473.61547.684572.647641@ipc1.ka-ro>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<1275636608.607067.417709988883.1.gpush@pororo>
	<20100611042046.GA31045@fluff.org.uk>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
Message-ID: <1276319449.1962.178.camel@pasglop>


> Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> makes it impossible to call those functions in interrupt context.

And doing clk_enable/clk_disable from interrupt context is a bad idea as
well :-)

Cheers,
Ben.




From benh at kernel.crashing.org  Sat Jun 12 01:12:53 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Sat, 12 Jun 2010 15:12:53 +1000
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19474.172.742782.972629@ipc1.ka-ro>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
Message-ID: <1276319573.1962.180.camel@pasglop>

On Fri, 2010-06-11 at 11:23 +0200, Lothar Wa?mann wrote:
> Hi,
> 
> > > Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> > > makes it impossible to call those functions in interrupt context.
> > 
> > Do we do this at the moment? I know at least one implementation of clk_enable 
> > uses a mutex for locking.
> > 
> You are probably talking about the Freescale i.MX51 kernel, that won't
> even boot, if you enable CONFIG_DEBUG_KERNEL, CONFIG_DEBUG_SPINLOCK,
> CONFIG_DEBUG_LOCKDEP and CONFIG_DEBUG_SPINLOCK_SLEEP.
> The mutex in the clock implementation is one of the reasons.

Regardless. Clocks generally take time to enable. I don't believe doing
clock enable/disable at hard irq context is a great idea.

If you really want to do something like that, you can always use either
threaded interrupts, or if you know your clock is off, mask & defer your
handling to a work queue yourself.

Unless we have enough case of very fast switching clocks that would
really benefit for that but from my experience, when a device can issue
interrupts, it should have its clocks on, unless it's some kind of
"wakeup" interrupt in which case it can safely be delayed.

Cheers,
Ben.



From benh at kernel.crashing.org  Sat Jun 12 01:14:03 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Sat, 12 Jun 2010 15:14:03 +1000
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19474.2817.333749.485028@ipc1.ka-ro>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
Message-ID: <1276319643.1962.181.camel@pasglop>

On Fri, 2010-06-11 at 12:08 +0200, Lothar Wa?mann wrote:
> Hi,
> 
> > > > > Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> > > > > makes it impossible to call those functions in interrupt context.
> > IMHO if a device generates an irq its clock should already be on.  This
> > way you don't need to enable or disable a clock in irq context.
> >  
> You may want to disable a clock in the IRQ handler. The VPU driver in
> the Freescale BSP for i.MX51 does exactly this.
> Anyway I don't see any reason for using a mutex here instead of
> spin_lock_irq_save() as all other implementations do.

Because you suddenly make it impossible to sleep inside enable/disable
unless I'm mistaken about the implementation details. Some PLLs can need
milliseconds to stabilize (especially if they need to be powered up
first). Doing that with a lock held is a BAD IDEA.

Cheers,
Ben.




From eric.y.miao at gmail.com  Sat Jun 12 01:23:34 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 12 Jun 2010 13:23:34 +0800
Subject: [PATCH 3/3] PalmZ72: Add support for OV9640 camera sensor
In-Reply-To: <201006111755.27382.marek.vasut@gmail.com>
References: <200908220852.06689.marek.vasut@gmail.com>
	<201004211411.37371.marek.vasut@gmail.com> 
	<AANLkTimS2Il7oMsfizddQosf6_qDa0imJ3N-FPhVz8aJ@mail.gmail.com> 
	<201006111755.27382.marek.vasut@gmail.com>
Message-ID: <AANLkTimjT8xgYIKp9QBttzD9fRnxvGJPecv4zj8Sgeev@mail.gmail.com>

On Fri, Jun 11, 2010 at 11:55 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dne P? 11. ?ervna 2010 16:38:52 Eric Miao napsal(a):
>> On Wed, Apr 21, 2010 at 8:11 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
>> > Dne St 21. dubna 2010 13:44:34 Eric Miao napsal(a):
>> >> On Wed, Apr 21, 2010 at 5:41 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
>> >> > Dne So 22. srpna 2009 08:52:06 Marek Vasut napsal(a):
>> >> >> From 777212ce6d3bacea76281aa3d74839a3c38b32a4 Mon Sep 17 00:00:00
>> >> >> 2001 From: Marek Vasut <marek.vasut at gmail.com>
>> >> >> Date: Sat, 22 Aug 2009 05:15:10 +0200
>> >> >> Subject: [PATCH 3/3] PalmZ72: Add support for OV9640 camera sensor
>> >> >
>> >> > Hi, was this ever merged ?
>> >>
>> >> Is the required change to ov9640 merged?
>> >
>> > Looking at this more properly, this might need a revision. The ov9640
>> > driver is in though.
>>
>> Marek,
>>
>> How's the status of the revision?
>
> Ewwww ... I totally forgot about this one ... could you send me the original
> patch please?
>

Forwarded.


From eric.y.miao at gmail.com  Sat Jun 12 01:36:32 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 12 Jun 2010 13:36:32 +0800
Subject: [PATCH] sa1111: Prevent deadlock in resume path
In-Reply-To: <1276258936.16663.39.camel@e102109-lin.cambridge.arm.com>
References: <1274901104-22133-1-git-send-email-marek.vasut@gmail.com> 
	<20100526191425.GD6232@n2100.arm.linux.org.uk>
	<201005262115.57282.marek.vasut@gmail.com> 
	<20100526201824.GA16418@n2100.arm.linux.org.uk>
	<20100610135609.GC4514@ucw.cz> 
	<1276258936.16663.39.camel@e102109-lin.cambridge.arm.com>
Message-ID: <AANLkTin5QDIZGJ_SvNxrK5C3ewT3DcMJNqrryYgMlEmy@mail.gmail.com>

On Fri, Jun 11, 2010 at 8:22 PM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
> On Thu, 2010-06-10 at 14:56 +0100, Pavel Machek wrote:
>> On Wed 2010-05-26 21:18:24, Russell King - ARM Linux wrote:
>> > On Wed, May 26, 2010 at 09:15:57PM +0200, Marek Vasut wrote:
>> > > You want me to fight your patch tracking system or will you just merge it into
>> > > your tree ?
>> >
>> > What do you mean "fight" ? ?Just send a standard git formatted patch
>> > to the email address with an additional KernelVersion: tag. ?It's
>> > not at all hard.
>>
>> You are linux kernel maintainer. Start acting as one. It is not at all
>> hard.
>>
>> Alternatively, just remove KernelVersion: checking in ?your
>> scripts.
>
> BTW (and I'm not complaining about Russell's patch system here), how can
> we get the linux-arm-kernel list subscribed to patchwork.kernel.org?
> That would be useful for grabbing RFC/CFT patches.
>

CC'ed Jeremy Kerr.

Jeremy,

Is it OK to add linux-arm-kernel?


From buytenh at wantstofly.org  Sat Jun 12 04:29:19 2010
From: buytenh at wantstofly.org (Lennert Buytenhek)
Date: Sat, 12 Jun 2010 10:29:19 +0200
Subject: [PATCH] Marvell OpenRD-Ultimate machine support
In-Reply-To: <4c1139ba.0d01df0a.42a6.1368@mx.google.com>
References: <4c1139ba.0d01df0a.42a6.1368@mx.google.com>
Message-ID: <20100612082919.GN1743@mail.wantstofly.org>

On Thu, Jun 10, 2010 at 10:12:55PM +0300, Dmytro Milinevskyy wrote:

> This patch adds support for the OpenRD Ultimate machine(could be found at http://www.arm.linux.org.uk/developer/machines/list.php?id=2884)

Acked-by: Lennert Buytenhek <buytenh at wantstofly.org>


> +MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
> +	/* Maintainer: Dhaval Vasa <dhaval.vasa at einfochips.com> */

I wonder whether this is correct, though.


From buytenh at wantstofly.org  Sat Jun 12 04:31:37 2010
From: buytenh at wantstofly.org (Lennert Buytenhek)
Date: Sat, 12 Jun 2010 10:31:37 +0200
Subject: [PATCH 1/2 v2] mv643xx_eth: use sw csum for big packets
In-Reply-To: <FCBE654890C0334289D0AD3AF4EF009F9FAC75AA96@IL-MB01.marvell.com>
References: <FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>
	<1276073483-17208-1-git-send-email-saeed@marvell.com>
	<20100610064330.GK1743@mail.wantstofly.org>
	<FCBE654890C0334289D0AD3AF4EF009F9FAC75AA96@IL-MB01.marvell.com>
Message-ID: <20100612083137.GO1743@mail.wantstofly.org>

On Thu, Jun 10, 2010 at 10:38:05AM +0300, Saeed Bishara wrote:

> >> diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
> >> index e345ec8..2d0e06b 100644
> >> --- a/drivers/net/mv643xx_eth.c
> >> +++ b/drivers/net/mv643xx_eth.c
> >> @@ -289,6 +289,7 @@ struct mv643xx_eth_shared_private {
> >>  	unsigned int t_clk;
> >>  	int extended_rx_coal_limit;
> >>  	int tx_bw_control;
> >> +	int tx_csum_limit;
> >>  };
> >>  
> >>  #define TX_BW_CONTROL_ABSENT		0
> >> @@ -782,7 +783,8 @@ static int txq_submit_skb(struct 
> >tx_queue *txq, struct sk_buff *skb)
> >>  		       skb->protocol != htons(ETH_P_8021Q));
> >>  
> >>  		tag_bytes = (void *)ip_hdr(skb) - (void 
> >*)skb->data - ETH_HLEN;
> >> -		if (unlikely(tag_bytes & ~12)) {
> >> +		if (unlikely(tag_bytes & ~12) ||
> >> +			skb->len > mp->shared->tx_csum_limit) {
> >
> >Please line up skb->len with unlikely() on the line above it.
> >
> >
> >> @@ -2666,6 +2668,9 @@ static int 
> >mv643xx_eth_shared_probe(struct platform_device *pdev)
> >>  	 * Detect hardware parameters.
> >>  	 */
> >>  	msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk 
> >: 133000000;
> >> +	msp->tx_csum_limit = pd->tx_csum_limit ? 
> >pd->tx_csum_limit : 9 * 1024;
> >> +	/* add header count so we can compare against skb->len */
> >> +	msp->tx_csum_limit += ETH_HLEN;
> >>  	infer_hw_params(msp);
> >
> >Is the limit 9 * 1024 + 14 for the whole packet, or 9 * 1024 for the IP
> >part?
>
> the limit is for the IP part, but I thought that adding the header length, then comparing agains skb->len will be the same. What do you suggest?

Right, but for the header length you take 14, while if to include VLAN
tags or DSA tags the header might actually be longer -- how does that
affect the ability of the hardware to compute the checksum?

I.e. is the restriction "total packet length must be < N + 14 bytes"
or is it "the IP part must be < N bytes and it doesn't matter whether
there are VLAN tags or not"?

I.e.:

> >I.e. what happens if skb->len is 9 * 1024 + 15, but there is one VLAN
> >tag present -- will the hardware be able to do the checksum offload or
> >not?


From eric.y.miao at gmail.com  Sat Jun 12 05:15:09 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 12 Jun 2010 17:15:09 +0800
Subject: [PATCH 2/3] pxa: Fix all devices using wm97xx_batt.h
In-Reply-To: <20100607091743.GB23093@rakim.wolfsonmicro.main>
References: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com> 
	<1275613654-23918-2-git-send-email-marek.vasut@gmail.com> 
	<20100607091743.GB23093@rakim.wolfsonmicro.main>
Message-ID: <AANLkTilkdPTchodUTXgpc2-7PcuJTPzX2vSqpHu4jjXt@mail.gmail.com>

On Mon, Jun 7, 2010 at 5:17 PM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Fri, Jun 04, 2010 at 03:07:33AM +0200, Marek Vasut wrote:
>> This file is scheduled for removal, therefore fix all devices that use this
>> file to use the suggested wm97xx.h and pass platform data properly.
>>
>> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
>
> Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
>

Applied.


From eric.y.miao at gmail.com  Sat Jun 12 05:16:58 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 12 Jun 2010 17:16:58 +0800
Subject: [PATCH 3/3] wm97xx_batt: Remove redundant header file
In-Reply-To: <1275613654-23918-3-git-send-email-marek.vasut@gmail.com>
References: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com> 
	<1275613654-23918-3-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTimb6TqQLLHDLI_qInwScZUQpYIDxNymE8SUh_9J@mail.gmail.com>

On Fri, Jun 4, 2010 at 9:07 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> ---
> ?include/linux/wm97xx_batt.h | ? 16 ----------------
> ?1 files changed, 0 insertions(+), 16 deletions(-)
> ?delete mode 100644 include/linux/wm97xx_batt.h
>
> diff --git a/include/linux/wm97xx_batt.h b/include/linux/wm97xx_batt.h
> deleted file mode 100644
> index a1d6419..0000000
> --- a/include/linux/wm97xx_batt.h
> +++ /dev/null
> @@ -1,16 +0,0 @@
> -#ifndef _LINUX_WM97XX_BAT_H
> -#define _LINUX_WM97XX_BAT_H
> -
> -#include <linux/wm97xx.h>
> -
> -#warning This file will be removed soon, use wm97xx.h instead!
> -
> -#define wm97xx_batt_info wm97xx_batt_pdata
> -
> -#ifdef CONFIG_BATTERY_WM97XX
> -void wm97xx_bat_set_pdata(struct wm97xx_batt_info *data);
> -#else
> -static inline void wm97xx_bat_set_pdata(struct wm97xx_batt_info *data) {}
> -#endif
> -
> -#endif

A git grep of wm97xx_batt.h shows:

drivers/power/wm97xx_battery.c:/* The interface is deprecated, as well
as linux/wm97xx_batt.h */

So you may want to remove that part as well. Otherwise looks good to me.


From eric.y.miao at gmail.com  Sat Jun 12 05:24:52 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 12 Jun 2010 17:24:52 +0800
Subject: [RFC PATCH] stargate2 and imote2 board file merge
In-Reply-To: <20100607095436.GF2702@excalibur.local>
References: <1275832502-28552-1-git-send-email-jic23@cam.ac.uk> 
	<20100607070724.GB2702@excalibur.local> <4C0CB700.8080300@cam.ac.uk> 
	<20100607092458.GE2702@excalibur.local>
	<20100607095436.GF2702@excalibur.local>
Message-ID: <AANLkTimGhZ0Q8roMB6Sh95J_abENichdO7Nk2uHDEkth@mail.gmail.com>

On Mon, Jun 7, 2010 at 5:54 PM, Stefan Schmidt
<stefan at datenfreihafen.org> wrote:
> Hello.
>
> On Mon, 2010-06-07 at 11:24, Stefan Schmidt wrote:
>> On Mon, 2010-06-07 at 10:08, Jonathan Cameron wrote:
>>
>> > :) I'll admit I haven't tested it myself yet. ?Didn't have the debug board to hand
>> > to be able to flash it to an imote2 and my sg2's were all in use testing the radio
>> > driver (that is dependent on mac802154 mainlining). ?One day we will have these devices
>> > fully supported in mainline.
>>
>> I should be able to flash it onto the imote2 today or tomorrow. Will let you
>> know my results.
>
> I can confirm that it boots fine on my imote2.
>
> Acked-by: Stefan Schmidt <stefan at datenfreihafen.org>
>
> I guess its Eric's call if he would like to see them merged.
>

Patches reducing duplication are always welcome, and this looks good to me.
Thanks for the testing.

Applied to 'devel'.


From eric.y.miao at gmail.com  Sat Jun 12 05:35:24 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 12 Jun 2010 17:35:24 +0800
Subject: [PATCH 1/5] usb/otg/ulpi: extend the generic ulpi driver.
In-Reply-To: <1275464450-23003-2-git-send-email-grinberg@compulab.co.il>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il> 
	<1275464450-23003-2-git-send-email-grinberg@compulab.co.il>
Message-ID: <AANLkTimHDBI0grgNrcvZ-BWS9kd0z4lFqEgVoyM4ysVJ@mail.gmail.com>

> +/* ULPI Function Control Register bits */
> +#define ULPI_FC_HS ? ? 0 ? ? ? ? ? ? ? /* Enable HS tcvr */
> +#define ULPI_FC_FS ? ? (0x1 << 0) ? ? ?/* Enable FS tcvr */
> +#define ULPI_FC_LS ? ? (0x2 << 0) ? ? ?/* Enable LS tcvr */
> +#define ULPI_FC_FS_LS ?(0x3 << 0) ? ? ?/* Enable FS tcvr for LS packets */
> +#define ULPI_FC_TRM_SEL ? ? ? ?(0x1 << 2) ? ? ?/* Internal pullup and HS termination */
> +#define ULPI_FC_NODRV ?(0x1 << 3) ? ? ?/* Non-Driving Operation */
> +#define ULPI_FC_NONRZI (0x1 << 4) ? ? ?/* Disable bit-stuff and NRZI encode */
> +#define ULPI_FC_RESET ?(0x1 << 5) ? ? ?/* Reset the UTMI core */
> +#define ULPI_FC_DEFAULT ? ? ? ?0x41 ? ? ? ? ? ?/* Function Control Register Default */
> +
> +
> +/* ULPI Interface Register bits */
> +#define ULPI_IC_6PIN ? (1 << 0) ? ? ? ?/* XCVR 6 serial pin mode */
> +#define ULPI_IC_3PIN ? (1 << 1) ? ? ? ?/* XCVR 3 serial pin mode */
> +#define ULPI_IC_CARKIT (1 << 2) ? ? ? ?/* Carkit mode */
> +#define ULPI_IC_CLKSPND ? ? ? ?(1 << 3) ? ? ? ?/* Active low clock suspend */
> +#define ULPI_IC_AUTORES ? ? ? ?(1 << 4) ? ? ? ?/* PHY auto transmit resume signal */
> +#define ULPI_IC_VBUSINV ? ? ? ?(1 << 5) ? ? ? ?/* Invert the external VBUS indicator */
> +#define ULPI_IC_INDPT ?(1 << 6) ? ? ? ?/* Indicator Pass Through */
> +#define ULPI_IC_DISPRT (1 << 7) ? ? ? ?/* Interface Protect Disable */
> +#define ULPI_IC_DEFAULT ? ? ? ?0x0 ? ? ? ? ? ? /* Interface Control Register Default */
> +
> ?struct otg_transceiver *otg_ulpi_create(struct otg_io_access_ops *ops,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned int flags);
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? u8 fc_flags, u8 ic_flags, u8 otg_flags);
>

Just one comment about the API, I might not know all the detail of these two
FC/IC registers, but maybe it can be even better:

1. separate flags definition from the FC/IC register bits, i.e. sometimes not
all the register bits will be used, and some times a meaningful flag name is
better (though the flag definition can be encoded properly to simplify the
algorithm to map into the actual register bits)

2. extend the original 'flags' variable and bits for the above definitions, so
we can keep the API unchanged.


From eric.y.miao at gmail.com  Sat Jun 12 07:48:25 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sat, 12 Jun 2010 19:48:25 +0800
Subject: [PATCH 4/5] [ARM] usb/host/ohci-pxa27x: make PXA310 USB OTG port 
	work in host mode.
In-Reply-To: <1275464450-23003-5-git-send-email-grinberg@compulab.co.il>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il> 
	<1275464450-23003-2-git-send-email-grinberg@compulab.co.il> 
	<1275464450-23003-3-git-send-email-grinberg@compulab.co.il> 
	<1275464450-23003-4-git-send-email-grinberg@compulab.co.il> 
	<1275464450-23003-5-git-send-email-grinberg@compulab.co.il>
Message-ID: <AANLkTilUt8D7B3UF_j1wOvsnXTVQyioofwMEikScdLOn@mail.gmail.com>

On Wed, Jun 2, 2010 at 3:40 PM, Igor Grinberg <grinberg at compulab.co.il> wrote:
>
> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
> Signed-off-by: Mike Rapoport <mike at compulab.co.il>
> ---
> ?arch/arm/mach-pxa/include/mach/ohci.h ? ? | ? ?3 +
> ?arch/arm/mach-pxa/include/mach/regs-u2d.h | ? ?2 +
> ?drivers/usb/host/ohci-pxa27x.c ? ? ? ? ? ?| ?183 +++++++++++++++++++++++++++++

My feeling is on pxa310, the OTG/ULPI is actually closer to the UDC, so
generally, I'd really like to see minimum change to ohci.


From marek.vasut at gmail.com  Sat Jun 12 08:44:38 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat, 12 Jun 2010 14:44:38 +0200
Subject: [PATCH 2/3] ARM/scoop: Add CPR register bit definitions
In-Reply-To: <1276346679-2893-1-git-send-email-marek.vasut@gmail.com>
References: <1276346679-2893-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1276346679-2893-2-git-send-email-marek.vasut@gmail.com>

Add bit definitions of the CPR register of the SCOOP chip into scoop.h. Also,
cleanup the GPCR definitions to match coding style.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/include/asm/hardware/scoop.h |   29 +++++++++++++++++------------
 1 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h
index 46492a6..ebb3cea 100644
--- a/arch/arm/include/asm/hardware/scoop.h
+++ b/arch/arm/include/asm/hardware/scoop.h
@@ -22,18 +22,23 @@
 #define SCOOP_GPWR 0x24
 #define SCOOP_GPRR 0x28
 
-#define SCOOP_GPCR_PA22	( 1 << 12 )
-#define SCOOP_GPCR_PA21	( 1 << 11 )
-#define SCOOP_GPCR_PA20	( 1 << 10 )
-#define SCOOP_GPCR_PA19	( 1 << 9 )
-#define SCOOP_GPCR_PA18	( 1 << 8 )
-#define SCOOP_GPCR_PA17	( 1 << 7 )
-#define SCOOP_GPCR_PA16	( 1 << 6 )
-#define SCOOP_GPCR_PA15	( 1 << 5 )
-#define SCOOP_GPCR_PA14	( 1 << 4 )
-#define SCOOP_GPCR_PA13	( 1 << 3 )
-#define SCOOP_GPCR_PA12	( 1 << 2 )
-#define SCOOP_GPCR_PA11	( 1 << 1 )
+#define SCOOP_CPR_OUT	(1 << 7)
+#define SCOOP_CPR_SD_3V	(1 << 2)
+#define SCOOP_CPR_CF_XV	(1 << 1)
+#define SCOOP_CPR_CF_3V	(1 << 0)
+
+#define SCOOP_GPCR_PA22	(1 << 12)
+#define SCOOP_GPCR_PA21	(1 << 11)
+#define SCOOP_GPCR_PA20	(1 << 10)
+#define SCOOP_GPCR_PA19	(1 << 9)
+#define SCOOP_GPCR_PA18	(1 << 8)
+#define SCOOP_GPCR_PA17	(1 << 7)
+#define SCOOP_GPCR_PA16	(1 << 6)
+#define SCOOP_GPCR_PA15	(1 << 5)
+#define SCOOP_GPCR_PA14	(1 << 4)
+#define SCOOP_GPCR_PA13	(1 << 3)
+#define SCOOP_GPCR_PA12	(1 << 2)
+#define SCOOP_GPCR_PA11	(1 << 1)
 
 struct scoop_config {
 	unsigned short io_out;
-- 
1.7.1



From marek.vasut at gmail.com  Sat Jun 12 08:44:37 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat, 12 Jun 2010 14:44:37 +0200
Subject: [PATCH 1/3] ISL6271A voltage regulator support.
Message-ID: <1276346679-2893-1-git-send-email-marek.vasut@gmail.com>

This device is very simple, it supports only one LDO. This single LDO is
programmed over I2C to 16 possible voltages.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/regulator/Kconfig              |    6 +
 drivers/regulator/Makefile             |    1 +
 drivers/regulator/isl6271a-regulator.c |  199 ++++++++++++++++++++++++++++++++
 3 files changed, 206 insertions(+), 0 deletions(-)
 create mode 100644 drivers/regulator/isl6271a-regulator.c

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 04f2e08..6772ca7 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -201,5 +201,11 @@ config REGULATOR_88PM8607
 	help
 	  This driver supports 88PM8607 voltage regulator chips.
 
+config REGULATOR_ISL6271A
+	tristate "Intersil ISL6271A Power regulator"
+	depends on I2C
+	help
+	  This driver supports ISL6271A voltage regulator chip.
+
 endif
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 4e7feec..e2191bf 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
 obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o
 obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
 obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
+obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/isl6271a-regulator.c b/drivers/regulator/isl6271a-regulator.c
new file mode 100644
index 0000000..41cddc7
--- /dev/null
+++ b/drivers/regulator/isl6271a-regulator.c
@@ -0,0 +1,199 @@
+/*
+ * isl6271a-regulator.c
+ *
+ * Support for Intersil ISL6271A voltage regulator
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+/* Supported voltage values for regulators */
+static const u32 core_buck_table[] = {
+	 850000,  900000,  950000, 1000000,
+	1050000, 1100000, 1150000, 1200000,
+	1250000, 1300000, 1350000, 1400000,
+	1450000, 1500000, 1550000, 1600000,
+};
+
+/* PMIC details */
+struct isl_pmic {
+	struct regulator_desc	desc;
+	struct i2c_client	*client;
+	struct regulator_dev	*rdev;
+	struct mutex		mtx;
+};
+
+static int isl6271a_get_voltage(struct regulator_dev *dev)
+{
+	struct isl_pmic *pmic = rdev_get_drvdata(dev);
+	int idx, data;
+
+	mutex_lock(&pmic->mtx);
+
+	idx = i2c_smbus_read_byte(pmic->client);
+	if (idx < 0) {
+		dev_err(&pmic->client->dev, "Error getting voltage\n");
+		data = idx;
+		goto out;
+	}
+
+	data = core_buck_table[idx & 0xf];
+
+out:
+	mutex_unlock(&pmic->mtx);
+	return data;
+}
+
+static int isl6271a_set_voltage(struct regulator_dev *dev, int minuV, int maxuV)
+{
+	struct isl_pmic *pmic = rdev_get_drvdata(dev);
+	int vsel, err;
+	int pmic_minuV = core_buck_table[0];
+	int pmic_maxuV = core_buck_table[ARRAY_SIZE(core_buck_table) - 1];
+
+	if (minuV < pmic_minuV || minuV > pmic_maxuV)
+		return -EINVAL;
+	if (maxuV < pmic_minuV || maxuV > pmic_maxuV)
+		return -EINVAL;
+
+	for (vsel = 0; vsel < ARRAY_SIZE(core_buck_table); vsel++) {
+		int uV = core_buck_table[vsel];
+
+		if (minuV <= uV && uV <= maxuV)
+			break;
+	}
+
+	if (vsel == ARRAY_SIZE(core_buck_table))
+		return -EINVAL;
+
+	mutex_lock(&pmic->mtx);
+
+	err = i2c_smbus_write_byte(pmic->client, vsel);
+	if (err < 0)
+		dev_err(&pmic->client->dev, "Error setting voltage\n");
+
+	mutex_unlock(&pmic->mtx);
+	return err;
+}
+
+static int isl6271a_list_voltage(struct regulator_dev *dev, unsigned selector)
+{
+	return core_buck_table[selector];
+}
+
+static struct regulator_ops isl_core_ops = {
+	.get_voltage	= isl6271a_get_voltage,
+	.set_voltage	= isl6271a_set_voltage,
+	.list_voltage	= isl6271a_list_voltage,
+};
+
+static int __devinit isl6271a_probe(struct i2c_client *client,
+				     const struct i2c_device_id *id)
+{
+	struct regulator_init_data *init_data	= client->dev.platform_data;
+	struct isl_pmic *pmic;
+	int err;
+
+	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+		return -EIO;
+
+	if (!init_data)
+		return -EIO;
+
+	pmic = kzalloc(sizeof(struct isl_pmic), GFP_KERNEL);
+	if (!pmic)
+		return -ENOMEM;
+
+	pmic->client = client;
+
+	mutex_init(&pmic->mtx);
+
+	pmic->desc.name	= "Core Buck";
+	pmic->desc.id	= 0;
+	pmic->desc.n_voltages = ARRAY_SIZE(core_buck_table);
+	pmic->desc.ops	= &isl_core_ops;
+	pmic->desc.type	= REGULATOR_VOLTAGE;
+	pmic->desc.owner = THIS_MODULE;
+
+	pmic->rdev = regulator_register(&pmic->desc, &client->dev,
+					init_data, pmic);
+	if (IS_ERR(pmic->rdev)) {
+		dev_err(&client->dev, "failed to register %s\n",
+			id->name);
+		err = PTR_ERR(pmic->rdev);
+		goto error;
+	}
+
+	i2c_set_clientdata(client, pmic);
+
+	return 0;
+
+error:
+	kfree(pmic);
+	return err;
+}
+
+static int __devexit isl6271a_remove(struct i2c_client *client)
+{
+	struct isl_pmic *pmic = i2c_get_clientdata(client);
+
+	i2c_set_clientdata(client, NULL);
+
+	regulator_unregister(pmic->rdev);
+
+	kfree(pmic);
+
+	return 0;
+}
+
+static const struct i2c_device_id isl6271a_id[] = {
+	{.name = "isl6271a", 0 },
+	{ },
+};
+
+MODULE_DEVICE_TABLE(i2c, isl6271a_id);
+
+static struct i2c_driver isl6271a_i2c_driver = {
+	.driver = {
+		.name = "isl6271a",
+		.owner = THIS_MODULE,
+	},
+	.probe = isl6271a_probe,
+	.remove = __devexit_p(isl6271a_remove),
+	.id_table = isl6271a_id,
+};
+
+static int __init isl6271a_init(void)
+{
+	return i2c_add_driver(&isl6271a_i2c_driver);
+}
+
+static void __exit isl6271a_cleanup(void)
+{
+	i2c_del_driver(&isl6271a_i2c_driver);
+}
+
+subsys_initcall(isl6271a_init);
+module_exit(isl6271a_cleanup);
+
+MODULE_AUTHOR("Marek Vasut <marek.vasut at gmail.com>");
+MODULE_DESCRIPTION("Intersil ISL6271A voltage regulator driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.1



From marek.vasut at gmail.com  Sat Jun 12 08:44:39 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat, 12 Jun 2010 14:44:39 +0200
Subject: [PATCH 3/3] pxa/spitz: Rework spitz
In-Reply-To: <1276346679-2893-1-git-send-email-marek.vasut@gmail.com>
References: <1276346679-2893-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1276346679-2893-3-git-send-email-marek.vasut@gmail.com>

This huge patch mostly shuffles code. The spitz.c file contained terrible mess
and needed a cleanup, here it is:

1) Made every part modular, components are not built in if not selected.
2) Removed loads of preprocessor goo, mostly "#ifdef MACH_AKITA .... #endif" and
   similar code. The kernel size will grow by a few kb now, but the file is much
   more readable.
3) Reworked SD/CF power setting function and made it reentrant.
4) Add ISL6271A regulator support
5) Correctly register WM8750

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/include/mach/spitz.h |    2 -
 arch/arm/mach-pxa/spitz.c              |  810 ++++++++++++++++++-------------
 2 files changed, 470 insertions(+), 342 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index fa1998c..685749a 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
@@ -185,7 +185,5 @@
 /*
  * Shared data structures
  */
-extern struct platform_device spitzscoop_device;
-extern struct platform_device spitzscoop2_device;
 extern struct platform_device spitzssp_device;
 extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 4d2413e..fa31980 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -18,14 +18,15 @@
 #include <linux/gpio_keys.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
-#include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/spi/corgi_lcd.h>
+#include <linux/mtd/physmap.h>
 #include <linux/mtd/sharpsl.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -33,11 +34,9 @@
 #include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/scoop.h>
 
-
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/reset.h>
-#include <plat/i2c.h>
 #include <mach/irda.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
@@ -45,11 +44,16 @@
 #include <mach/pxa2xx_spi.h>
 #include <mach/spitz.h>
 
+#include <plat/i2c.h>
+
 #include "generic.h"
 #include "devices.h"
 #include "sharpsl.h"
 
-static unsigned long spitz_pin_config[] __initdata = {
+/******************************************************************************
+ * Pin configuration
+ ******************************************************************************/
+static unsigned long sharpslc_pin_config[] __initdata = {
 	/* Chip Selects */
 	GPIO78_nCS_2,	/* SCOOP #2 */
 	GPIO79_nCS_3,	/* NAND */
@@ -124,10 +128,13 @@ static unsigned long spitz_pin_config[] __initdata = {
 	GPIO1_GPIO | WAKEUP_ON_EDGE_FALL,	/* SPITZ_GPIO_RESET */
 };
 
-/*
- * Spitz SCOOP Device #1
- */
-static struct resource spitz_scoop_resources[] = {
+
+/******************************************************************************
+ * Scoop GPIO expander
+ ******************************************************************************/
+#if defined(CONFIG_SHARP_SCOOP) || defined(CONFIG_SHARP_SCOOP_MODULE)
+/* SCOOP Device #1 */
+static struct resource sharpslc_scoop_1_resources[] = {
 	[0] = {
 		.start		= 0x10800000,
 		.end		= 0x10800fff,
@@ -135,7 +142,7 @@ static struct resource spitz_scoop_resources[] = {
 	},
 };
 
-static struct scoop_config spitz_scoop_setup = {
+static struct scoop_config sharpslc_scoop_1_setup = {
 	.io_dir		= SPITZ_SCP_IO_DIR,
 	.io_out		= SPITZ_SCP_IO_OUT,
 	.suspend_clr	= SPITZ_SCP_SUS_CLR,
@@ -143,20 +150,18 @@ static struct scoop_config spitz_scoop_setup = {
 	.gpio_base	= SPITZ_SCP_GPIO_BASE,
 };
 
-struct platform_device spitzscoop_device = {
+struct platform_device sharpslc_scoop_1_device = {
 	.name		= "sharp-scoop",
 	.id		= 0,
 	.dev		= {
- 		.platform_data	= &spitz_scoop_setup,
+		.platform_data	= &sharpslc_scoop_1_setup,
 	},
-	.num_resources	= ARRAY_SIZE(spitz_scoop_resources),
-	.resource	= spitz_scoop_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_scoop_1_resources),
+	.resource	= sharpslc_scoop_1_resources,
 };
 
-/*
- * Spitz SCOOP Device #2
- */
-static struct resource spitz_scoop2_resources[] = {
+/* SCOOP Device #2 */
+static struct resource sharpslc_scoop_2_resources[] = {
 	[0] = {
 		.start		= 0x08800040,
 		.end		= 0x08800fff,
@@ -164,7 +169,7 @@ static struct resource spitz_scoop2_resources[] = {
 	},
 };
 
-static struct scoop_config spitz_scoop2_setup = {
+static struct scoop_config sharpslc_scoop_2_setup = {
 	.io_dir		= SPITZ_SCP2_IO_DIR,
 	.io_out		= SPITZ_SCP2_IO_OUT,
 	.suspend_clr	= SPITZ_SCP2_SUS_CLR,
@@ -172,82 +177,110 @@ static struct scoop_config spitz_scoop2_setup = {
 	.gpio_base	= SPITZ_SCP2_GPIO_BASE,
 };
 
-struct platform_device spitzscoop2_device = {
+struct platform_device sharpslc_scoop_2_device = {
 	.name		= "sharp-scoop",
 	.id		= 1,
 	.dev		= {
- 		.platform_data	= &spitz_scoop2_setup,
+		.platform_data	= &sharpslc_scoop_2_setup,
 	},
-	.num_resources	= ARRAY_SIZE(spitz_scoop2_resources),
-	.resource	= spitz_scoop2_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_scoop_2_resources),
+	.resource	= sharpslc_scoop_2_resources,
 };
 
-#define SPITZ_PWR_SD 0x01
-#define SPITZ_PWR_CF 0x02
+static void __init sharpslc_scoop_init(void)
+{
+	platform_device_register(&sharpslc_scoop_1_device);
+
+	/* Akita doesn't have the second SCOOP chip */
+	if (!machine_is_akita())
+		platform_device_register(&sharpslc_scoop_2_device);
+}
 
 /* Power control is shared with between one of the CF slots and SD */
-static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr)
+static void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr)
 {
-	unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR);
+	unsigned short cpr;
+	unsigned long flags;
 
-	if (new_cpr & 0x0007) {
+	if (new_cpr & 0x7) {
 		gpio_set_value(SPITZ_GPIO_CF_POWER, 1);
-		if (!(cpr & 0x0002) && !(cpr & 0x0004))
-		        mdelay(5);
-		if (device == SPITZ_PWR_CF)
-		        cpr |= 0x0002;
-		if (device == SPITZ_PWR_SD)
-		        cpr |= 0x0004;
-	        write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
-	} else {
-		if (device == SPITZ_PWR_CF)
-		        cpr &= ~0x0002;
-		if (device == SPITZ_PWR_SD)
-		        cpr &= ~0x0004;
-		if (!(cpr & 0x0002) && !(cpr & 0x0004)) {
-			write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, 0x0000);
-		        mdelay(1);
-			gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
-		} else {
-		        write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
-		}
+		mdelay(5);
+	}
+
+	local_irq_save(flags);
+
+	cpr = read_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR);
+
+	if (enable & new_cpr)
+		cpr |= new_cpr;
+	else
+		cpr &= ~enable;
+
+	write_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR, cpr);
+
+	local_irq_restore(flags);
+
+	if (!(cpr & 0x7)) {
+		mdelay(1);
+		gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
 	}
 }
 
-static void spitz_pcmcia_pwr(struct device *scoop, unsigned short cpr, int nr)
+#else
+static inline void sharpslc_scoop_init(void) {}
+static inline void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr) {}
+#endif
+
+/******************************************************************************
+ * PCMCIA
+ ******************************************************************************/
+#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
+static void sharpslc_pcmcia_pwr(struct device *scoop, uint16_t cpr, int nr)
 {
 	/* Only need to override behaviour for slot 0 */
 	if (nr == 0)
-		spitz_card_pwr_ctrl(SPITZ_PWR_CF, cpr);
+		sharpslc_card_pwr_ctrl(
+			cpr & (SCOOP_CPR_CF_3V | SCOOP_CPR_CF_XV), cpr);
 	else
 		write_scoop_reg(scoop, SCOOP_CPR, cpr);
 }
 
-static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
-{
-	.dev        = &spitzscoop_device.dev,
-	.irq        = SPITZ_IRQ_GPIO_CF_IRQ,
-	.cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
-	.cd_irq_str = "PCMCIA0 CD",
-},{
-	.dev        = &spitzscoop2_device.dev,
-	.irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
-	.cd_irq     = -1,
-},
+static struct scoop_pcmcia_dev sharpslc_pcmcia_scoop[] = {
+	{
+		.dev        = &sharpslc_scoop_1_device.dev,
+		.irq        = SPITZ_IRQ_GPIO_CF_IRQ,
+		.cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
+		.cd_irq_str = "PCMCIA0 CD",
+	}, {
+		.dev        = &sharpslc_scoop_2_device.dev,
+		.irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
+		.cd_irq     = -1,
+	},
 };
 
-static struct scoop_pcmcia_config spitz_pcmcia_config = {
-	.devs         = &spitz_pcmcia_scoop[0],
-	.num_devs     = 2,
-	.power_ctrl   = spitz_pcmcia_pwr,
+static struct scoop_pcmcia_config sharpslc_pcmcia_config = {
+	.devs		= &sharpslc_pcmcia_scoop[0],
+	.num_devs	= 2,
+	.power_ctrl	= sharpslc_pcmcia_pwr,
 };
 
-EXPORT_SYMBOL(spitzscoop_device);
-EXPORT_SYMBOL(spitzscoop2_device);
+static void __init sharpslc_pcmcia_init(void)
+{
+	/* Akita has only one PCMCIA slot used */
+	if (machine_is_akita())
+		sharpslc_pcmcia_config.num_devs = 1;
+
+	platform_scoop_config = &sharpslc_pcmcia_config;
+}
+#else
+static inline void sharpslc_pcmcia_init(void) {}
+#endif
+
+/******************************************************************************
+ * GPIO keyboard
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
 
-/*
- * Spitz Keyboard Device
- */
 #define SPITZ_KEY_CALENDAR	KEY_F1
 #define SPITZ_KEY_ADDRESS	KEY_F2
 #define SPITZ_KEY_FN		KEY_F3
@@ -263,7 +296,7 @@ EXPORT_SYMBOL(spitzscoop2_device);
 #define SPITZ_KEY_OK		KEY_F11
 #define SPITZ_KEY_MENU		KEY_F12
 
-static const uint32_t spitzkbd_keymap[] = {
+static const uint32_t sharpslc_keymap[] = {
 	KEY(0, 0, KEY_LEFTCTRL),
 	KEY(0, 1, KEY_1),
 	KEY(0, 2, KEY_3),
@@ -330,37 +363,48 @@ static const uint32_t spitzkbd_keymap[] = {
 	KEY(6, 8, KEY_RIGHT),
 };
 
-static const struct matrix_keymap_data spitzkbd_keymap_data = {
-	.keymap		= spitzkbd_keymap,
-	.keymap_size	= ARRAY_SIZE(spitzkbd_keymap),
+static const struct matrix_keymap_data sharpslc_keymap_data = {
+	.keymap		= sharpslc_keymap,
+	.keymap_size	= ARRAY_SIZE(sharpslc_keymap),
 };
 
-static const uint32_t spitzkbd_row_gpios[] =
+static const uint32_t sharpslc_row_gpios[] =
 		{ 12, 17, 91, 34, 36, 38, 39 };
-static const uint32_t spitzkbd_col_gpios[] =
+static const uint32_t sharpslc_col_gpios[] =
 		{ 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 };
 
-static struct matrix_keypad_platform_data spitzkbd_pdata = {
-	.keymap_data		= &spitzkbd_keymap_data,
-	.row_gpios		= spitzkbd_row_gpios,
-	.col_gpios		= spitzkbd_col_gpios,
-	.num_row_gpios		= ARRAY_SIZE(spitzkbd_row_gpios),
-	.num_col_gpios		= ARRAY_SIZE(spitzkbd_col_gpios),
+static struct matrix_keypad_platform_data sharpslc_mkp_pdata = {
+	.keymap_data		= &sharpslc_keymap_data,
+	.row_gpios		= sharpslc_row_gpios,
+	.col_gpios		= sharpslc_col_gpios,
+	.num_row_gpios		= ARRAY_SIZE(sharpslc_row_gpios),
+	.num_col_gpios		= ARRAY_SIZE(sharpslc_col_gpios),
 	.col_scan_delay_us	= 10,
 	.debounce_ms		= 10,
 	.wakeup			= 1,
 };
 
-static struct platform_device spitzkbd_device = {
+static struct platform_device sharpslc_mkp_device = {
 	.name		= "matrix-keypad",
 	.id		= -1,
 	.dev		= {
-		.platform_data = &spitzkbd_pdata,
+		.platform_data	= &sharpslc_mkp_pdata,
 	},
 };
 
+static void __init sharpslc_mkp_init(void)
+{
+	platform_device_register(&sharpslc_mkp_device);
+}
+#else
+static inline void sharpslc_mkp_init(void) {}
+#endif
 
-static struct gpio_keys_button spitz_gpio_keys[] = {
+/******************************************************************************
+ * GPIO keys
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button sharpslc_gpio_keys[] = {
 	{
 		.type	= EV_PWR,
 		.code	= KEY_SUSPEND,
@@ -383,27 +427,35 @@ static struct gpio_keys_button spitz_gpio_keys[] = {
 	},
 };
 
-static struct gpio_keys_platform_data spitz_gpio_keys_platform_data = {
-	.buttons	= spitz_gpio_keys,
-	.nbuttons	= ARRAY_SIZE(spitz_gpio_keys),
+static struct gpio_keys_platform_data sharpslc_gpio_keys_platform_data = {
+	.buttons	= sharpslc_gpio_keys,
+	.nbuttons	= ARRAY_SIZE(sharpslc_gpio_keys),
 };
 
-static struct platform_device spitz_gpio_keys_device = {
+static struct platform_device sharpslc_gpio_keys_device = {
 	.name	= "gpio-keys",
 	.id	= -1,
 	.dev	= {
-		.platform_data	= &spitz_gpio_keys_platform_data,
+		.platform_data	= &sharpslc_gpio_keys_platform_data,
 	},
 };
 
+static void __init sharpslc_keys_init(void)
+{
+	platform_device_register(&sharpslc_gpio_keys_device);
+}
+#else
+static inline void sharpslc_keys_init(void) {}
+#endif
 
-/*
- * Spitz LEDs
- */
-static struct gpio_led spitz_gpio_leds[] = {
+/******************************************************************************
+ * LEDs
+ ******************************************************************************/
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static struct gpio_led sharpslc_gpio_leds[] = {
 	{
 		.name			= "spitz:amber:charge",
-		.default_trigger	= "sharpsl-charge",
+		.default_trigger	= "sharpslc-charge",
 		.gpio			= SPITZ_GPIO_LED_ORANGE,
 	},
 	{
@@ -413,25 +465,32 @@ static struct gpio_led spitz_gpio_leds[] = {
 	},
 };
 
-static struct gpio_led_platform_data spitz_gpio_leds_info = {
-	.leds		= spitz_gpio_leds,
-	.num_leds	= ARRAY_SIZE(spitz_gpio_leds),
+static struct gpio_led_platform_data sharpslc_gpio_leds_info = {
+	.leds		= sharpslc_gpio_leds,
+	.num_leds	= ARRAY_SIZE(sharpslc_gpio_leds),
 };
 
-static struct platform_device spitzled_device = {
+static struct platform_device sharpslc_led_device = {
 	.name		= "leds-gpio",
 	.id		= -1,
 	.dev		= {
-		.platform_data = &spitz_gpio_leds_info,
+		.platform_data	= &sharpslc_gpio_leds_info,
 	},
 };
 
-#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_master spitz_spi_info = {
-	.num_chipselect	= 3,
-};
+static void __init sharpslc_leds_init(void)
+{
+	platform_device_register(&sharpslc_led_device);
+}
+#else
+static inline void sharpslc_leds_init(void) {}
+#endif
 
-static void spitz_wait_for_hsync(void)
+/******************************************************************************
+ * SSP Devices
+ ******************************************************************************/
+#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
+static void sharpslc_ads7846_wait_for_hsync(void)
 {
 	while (gpio_get_value(SPITZ_GPIO_HSYNC))
 		cpu_relax();
@@ -440,21 +499,21 @@ static void spitz_wait_for_hsync(void)
 		cpu_relax();
 }
 
-static struct ads7846_platform_data spitz_ads7846_info = {
+static struct ads7846_platform_data sharpslc_ads7846_info = {
 	.model			= 7846,
 	.vref_delay_usecs	= 100,
 	.x_plate_ohms		= 419,
 	.y_plate_ohms		= 486,
 	.pressure_max		= 1024,
 	.gpio_pendown		= SPITZ_GPIO_TP_INT,
-	.wait_for_sync		= spitz_wait_for_hsync,
+	.wait_for_sync		= sharpslc_ads7846_wait_for_hsync,
 };
 
-static struct pxa2xx_spi_chip spitz_ads7846_chip = {
+static struct pxa2xx_spi_chip sharpslc_ads7846_chip = {
 	.gpio_cs		= SPITZ_GPIO_ADS7846_CS,
 };
 
-static void spitz_bl_kick_battery(void)
+static void sharpslc_bl_kick_battery(void)
 {
 	void (*kick_batt)(void);
 
@@ -465,93 +524,109 @@ static void spitz_bl_kick_battery(void)
 	}
 }
 
-static struct corgi_lcd_platform_data spitz_lcdcon_info = {
+static struct corgi_lcd_platform_data sharpslc_lcdcon_info = {
 	.init_mode		= CORGI_LCD_MODE_VGA,
 	.max_intensity		= 0x2f,
 	.default_intensity	= 0x1f,
 	.limit_mask		= 0x0b,
 	.gpio_backlight_cont	= SPITZ_GPIO_BACKLIGHT_CONT,
 	.gpio_backlight_on	= SPITZ_GPIO_BACKLIGHT_ON,
-	.kick_battery		= spitz_bl_kick_battery,
+	.kick_battery		= sharpslc_bl_kick_battery,
 };
 
-static struct pxa2xx_spi_chip spitz_lcdcon_chip = {
+static struct pxa2xx_spi_chip sharpslc_lcdcon_chip = {
 	.gpio_cs	= SPITZ_GPIO_LCDCON_CS,
 };
 
-static struct pxa2xx_spi_chip spitz_max1111_chip = {
+static struct pxa2xx_spi_chip sharpslc_max1111_chip = {
 	.gpio_cs	= SPITZ_GPIO_MAX1111_CS,
 };
 
-static struct spi_board_info spitz_spi_devices[] = {
+static struct spi_board_info sharpslc_spi_devices[] = {
 	{
-		.modalias	= "ads7846",
-		.max_speed_hz	= 1200000,
-		.bus_num	= 2,
-		.chip_select	= 0,
-		.platform_data	= &spitz_ads7846_info,
-		.controller_data= &spitz_ads7846_chip,
-		.irq		= gpio_to_irq(SPITZ_GPIO_TP_INT),
+		.modalias		= "ads7846",
+		.max_speed_hz		= 1200000,
+		.bus_num		= 2,
+		.chip_select		= 0,
+		.platform_data		= &sharpslc_ads7846_info,
+		.controller_data	= &sharpslc_ads7846_chip,
+		.irq			= gpio_to_irq(SPITZ_GPIO_TP_INT),
 	}, {
-		.modalias	= "corgi-lcd",
-		.max_speed_hz	= 50000,
-		.bus_num	= 2,
-		.chip_select	= 1,
-		.platform_data	= &spitz_lcdcon_info,
-		.controller_data= &spitz_lcdcon_chip,
+		.modalias		= "corgi-lcd",
+		.max_speed_hz		= 50000,
+		.bus_num		= 2,
+		.chip_select		= 1,
+		.platform_data		= &sharpslc_lcdcon_info,
+		.controller_data	= &sharpslc_lcdcon_chip,
 	}, {
-		.modalias	= "max1111",
-		.max_speed_hz	= 450000,
-		.bus_num	= 2,
-		.chip_select	= 2,
-		.controller_data= &spitz_max1111_chip,
+		.modalias		= "max1111",
+		.max_speed_hz		= 450000,
+		.bus_num		= 2,
+		.chip_select		= 2,
+		.controller_data	= &sharpslc_max1111_chip,
 	},
 };
 
-static void __init spitz_init_spi(void)
+static struct pxa2xx_spi_master sharpslc_spi_info = {
+	.num_chipselect	= 3,
+};
+
+static void __init sharpslc_spi_init(void)
 {
+	struct corgi_lcd_platform_data *lcd_data = &sharpslc_lcdcon_info;
+
 	if (machine_is_akita()) {
-		spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
-		spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
+		lcd_data->gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
+		lcd_data->gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
 	}
 
-	pxa2xx_set_spi_info(2, &spitz_spi_info);
-	spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
+	pxa2xx_set_spi_info(2, &sharpslc_spi_info);
+	spi_register_board_info(ARRAY_AND_SIZE(sharpslc_spi_devices));
 }
 #else
-static inline void spitz_init_spi(void) {}
+static inline void sharpslc_spi_init(void) {}
 #endif
 
+/******************************************************************************
+ * SD/MMC card controller
+ ******************************************************************************/
+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
 /*
- * MMC/SD Device
- *
- * The card detect interrupt isn't debounced so we delay it by 250ms
- * to give the card a chance to fully insert/eject.
+ * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
+ * give the card a chance to fully insert/eject.
  */
-static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
+static void sharpslc_mci_setpower(struct device *dev, unsigned int vdd)
 {
 	struct pxamci_platform_data* p_d = dev->platform_data;
 
-	if (( 1 << vdd) & p_d->ocr_mask)
-		spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0004);
+	if ((1 << vdd) & p_d->ocr_mask)
+		sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
 	else
-		spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0000);
+		sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
 }
 
-static struct pxamci_platform_data spitz_mci_platform_data = {
+static struct pxamci_platform_data sharpslc_mci_platform_data = {
 	.detect_delay_ms	= 250,
 	.ocr_mask		= MMC_VDD_32_33|MMC_VDD_33_34,
-	.setpower 		= spitz_mci_setpower,
+	.setpower		= sharpslc_mci_setpower,
 	.gpio_card_detect	= SPITZ_GPIO_nSD_DETECT,
 	.gpio_card_ro		= SPITZ_GPIO_nSD_WP,
 	.gpio_power		= -1,
 };
 
+static void __init sharpslc_mmc_init(void)
+{
+	pxa_set_mci_info(&sharpslc_mci_platform_data);
+}
+#else
+static inline void sharpslc_mmc_init(void) {}
+#endif
 
-/*
- * USB Host (OHCI)
- */
-static int spitz_ohci_init(struct device *dev)
+/******************************************************************************
+ * USB Host
+ ******************************************************************************/
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static int sharpslc_ohci_init(struct device *dev)
 {
 	int err;
 
@@ -559,88 +634,114 @@ static int spitz_ohci_init(struct device *dev)
 	if (err)
 		return err;
 
-	/* Only Port 2 is connected
-	 * Setup USB Port 2 Output Control Register
-	 */
+	/* Only Port 2 is connected, setup USB Port 2 Output Control Register */
 	UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
 
 	return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1);
 }
 
-static void spitz_ohci_exit(struct device *dev)
+static void sharpslc_ohci_exit(struct device *dev)
 {
 	gpio_free(SPITZ_GPIO_USB_HOST);
 }
 
-static struct pxaohci_platform_data spitz_ohci_platform_data = {
+static struct pxaohci_platform_data sharpslc_ohci_platform_data = {
 	.port_mode	= PMM_NPS_MODE,
-	.init		= spitz_ohci_init,
-	.exit		= spitz_ohci_exit,
+	.init		= sharpslc_ohci_init,
+	.exit		= sharpslc_ohci_exit,
 	.flags		= ENABLE_PORT_ALL | NO_OC_PROTECTION,
 	.power_budget	= 150,
 };
 
+static void __init sharpslc_uhc_init(void)
+{
+	pxa_set_ohci_info(&sharpslc_ohci_platform_data);
+}
+#else
+static inline void sharpslc_uhc_init(void) {}
+#endif
 
-/*
- * Irda
- */
-
-static struct pxaficp_platform_data spitz_ficp_platform_data = {
-/* .gpio_pwdown is set in spitz_init() and akita_init() accordingly */
+/******************************************************************************
+ * IrDA
+ ******************************************************************************/
+#if defined(CONFIG_PXA_FICP) || defined(CONFIG_PXA_FICP_MODULE)
+static struct pxaficp_platform_data sharpslc_ficp_platform_data = {
 	.transceiver_cap	= IR_SIRMODE | IR_OFF,
 };
 
+static void __init sharpslc_irda_init(void)
+{
+	if (machine_is_akita())
+		sharpslc_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
+	else
+		sharpslc_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
 
-/*
- * Spitz PXA Framebuffer
- */
+	pxa_set_ficp_info(&sharpslc_ficp_platform_data);
+}
+#else
+static inline void sharpslc_irda_init(void) {}
+#endif
 
-static struct pxafb_mode_info spitz_pxafb_modes[] = {
-{
-	.pixclock       = 19231,
-	.xres           = 480,
-	.yres           = 640,
-	.bpp            = 16,
-	.hsync_len      = 40,
-	.left_margin    = 46,
-	.right_margin   = 125,
-	.vsync_len      = 3,
-	.upper_margin   = 1,
-	.lower_margin   = 0,
-	.sync           = 0,
-},{
-	.pixclock       = 134617,
-	.xres           = 240,
-	.yres           = 320,
-	.bpp            = 16,
-	.hsync_len      = 20,
-	.left_margin    = 20,
-	.right_margin   = 46,
-	.vsync_len      = 2,
-	.upper_margin   = 1,
-	.lower_margin   = 0,
-	.sync           = 0,
-},
-};
-
-static struct pxafb_mach_info spitz_pxafb_info = {
-	.modes          = &spitz_pxafb_modes[0],
-	.num_modes      = 2,
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static struct pxafb_mode_info sharpslc_pxafb_modes[] = {
+	{
+		.pixclock       = 19231,
+		.xres           = 480,
+		.yres           = 640,
+		.bpp            = 16,
+		.hsync_len      = 40,
+		.left_margin    = 46,
+		.right_margin   = 125,
+		.vsync_len      = 3,
+		.upper_margin   = 1,
+		.lower_margin   = 0,
+		.sync           = 0,
+	}, {
+		.pixclock       = 134617,
+		.xres           = 240,
+		.yres           = 320,
+		.bpp            = 16,
+		.hsync_len      = 20,
+		.left_margin    = 20,
+		.right_margin   = 46,
+		.vsync_len      = 2,
+		.upper_margin   = 1,
+		.lower_margin   = 0,
+		.sync           = 0,
+	},
+};
+
+static struct pxafb_mach_info sharpslc_pxafb_info = {
+	.modes          = sharpslc_pxafb_modes,
+	.num_modes      = ARRAY_SIZE(sharpslc_pxafb_modes),
 	.fixed_modes    = 1,
 	.lcd_conn	= LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
 };
 
-static struct mtd_partition sharpsl_nand_partitions[] = {
+static void __init sharpslc_lcd_init(void)
+{
+	set_pxa_fb_info(&sharpslc_pxafb_info);
+}
+#else
+static inline void sharpslc_lcd_init(void) {}
+#endif
+
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+#if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE)
+static struct mtd_partition sharpslc_nand_partitions[] = {
 	{
 		.name = "System Area",
 		.offset = 0,
 		.size = 7 * 1024 * 1024,
-	},
-	{
+	}, {
 		.name = "Root Filesystem",
 		.offset = 7 * 1024 * 1024,
-	},
-	{
+	}, {
 		.name = "Home Filesystem",
 		.offset = MTDPART_OFS_APPEND,
 		.size = MTDPART_SIZ_FULL,
@@ -649,37 +750,72 @@ static struct mtd_partition sharpsl_nand_partitions[] = {
 
 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
 
-static struct nand_bbt_descr sharpsl_bbt = {
-	.options = 0,
-	.offs = 4,
-	.len = 2,
-	.pattern = scan_ff_pattern
+static struct nand_bbt_descr sharpslc_nand_bbt = {
+	.options	= 0,
+	.offs		= 4,
+	.len		= 2,
+	.pattern	= scan_ff_pattern
+};
+
+static struct nand_ecclayout sharpslc_akita_oobinfo = {
+	.oobfree	= { {0x08, 0x09} },
+	.eccbytes	= 24,
+	.eccpos		= {
+			0x05, 0x01, 0x02, 0x03, 0x06, 0x07, 0x15, 0x11,
+			0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
+			0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37,
+	},
 };
 
-static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
-	.badblock_pattern	= &sharpsl_bbt,
-	.partitions		= sharpsl_nand_partitions,
-	.nr_partitions		= ARRAY_SIZE(sharpsl_nand_partitions),
+static struct sharpsl_nand_platform_data sharpslc_nand_pdata = {
+	.badblock_pattern	= &sharpslc_nand_bbt,
+	.partitions		= sharpslc_nand_partitions,
+	.nr_partitions		= ARRAY_SIZE(sharpslc_nand_partitions),
 };
 
-static struct resource sharpsl_nand_resources[] = {
+static struct resource sharpslc_nand_resources[] = {
 	{
-		.start	= 0x0C000000,
-		.end	= 0x0C000FFF,
+		.start	= PXA_CS3_PHYS,
+		.end	= PXA_CS3_PHYS + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 
-static struct platform_device sharpsl_nand_device = {
+static struct platform_device sharpslc_nand_device = {
 	.name		= "sharpsl-nand",
 	.id		= -1,
-	.resource	= sharpsl_nand_resources,
-	.num_resources	= ARRAY_SIZE(sharpsl_nand_resources),
-	.dev.platform_data	= &sharpsl_nand_platform_data,
+	.resource	= sharpslc_nand_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_nand_resources),
+	.dev		= {
+		.platform_data	= &sharpslc_nand_pdata,
+	}
 };
 
+static void __init sharpslc_nand_init(void)
+{
+	if (machine_is_spitz()) {
+		sharpslc_nand_partitions[1].size = 5 * 1024 * 1024;
+	} else if (machine_is_akita()) {
+		sharpslc_nand_partitions[1].size = 58 * 1024 * 1024;
+		sharpslc_nand_bbt.len = 1;
+		sharpslc_nand_pdata.ecc_layout = &sharpslc_akita_oobinfo;
+	} else if (machine_is_borzoi()) {
+		sharpslc_nand_partitions[1].size = 32 * 1024 * 1024;
+		sharpslc_nand_bbt.len = 1;
+		sharpslc_nand_pdata.ecc_layout = &sharpslc_akita_oobinfo;
+	}
+
+	platform_device_register(&sharpslc_nand_device);
+}
+#else
+static inline void sharpslc_nand_init(void) {}
+#endif
 
-static struct mtd_partition sharpsl_rom_parts[] = {
+/******************************************************************************
+ * NOR Flash
+ ******************************************************************************/
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition sharpslc_rom_parts[] = {
 	{
 		.name	="Boot PROM Filesystem",
 		.offset	= 0x00140000,
@@ -687,158 +823,152 @@ static struct mtd_partition sharpsl_rom_parts[] = {
 	},
 };
 
-static struct physmap_flash_data sharpsl_rom_data = {
+static struct physmap_flash_data sharpslc_rom_data = {
 	.width		= 2,
-	.nr_parts	= ARRAY_SIZE(sharpsl_rom_parts),
-	.parts		= sharpsl_rom_parts,
+	.nr_parts	= ARRAY_SIZE(sharpslc_rom_parts),
+	.parts		= sharpslc_rom_parts,
 };
 
-static struct resource sharpsl_rom_resources[] = {
+static struct resource sharpslc_rom_resources[] = {
 	{
-		.start	= 0x00000000,
-		.end	= 0x007fffff,
+		.start	= PXA_CS0_PHYS,
+		.end	= PXA_CS0_PHYS + SZ_8M - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 
-static struct platform_device sharpsl_rom_device = {
-	.name	= "physmap-flash",
-	.id	= -1,
-	.resource = sharpsl_rom_resources,
-	.num_resources = ARRAY_SIZE(sharpsl_rom_resources),
-	.dev.platform_data = &sharpsl_rom_data,
-};
-
-static struct platform_device *devices[] __initdata = {
-	&spitzscoop_device,
-	&spitzkbd_device,
-	&spitz_gpio_keys_device,
-	&spitzled_device,
-	&sharpsl_nand_device,
-	&sharpsl_rom_device,
+static struct platform_device sharpslc_rom_device = {
+	.name		= "physmap-flash",
+	.id		= -1,
+	.resource	= sharpslc_rom_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_rom_resources),
+	.dev		= {
+		.platform_data	= &sharpslc_rom_data,
+	},
 };
 
-static void spitz_poweroff(void)
+static void __init sharpslc_nor_init(void)
 {
-	arm_machine_restart('g', NULL);
+	platform_device_register(&sharpslc_rom_device);
 }
+#else
+static inline void sharpslc_nor_init(void) {}
+#endif
 
-static void spitz_restart(char mode, const char *cmd)
-{
-	/* Bootloader magic for a reboot */
-	if((MSC0 & 0xffff0000) == 0x7ff00000)
-		MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
-
-	spitz_poweroff();
-}
+/******************************************************************************
+ * GPIO expander
+ ******************************************************************************/
+#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
+static struct pca953x_platform_data akita_pca953x_pdata = {
+	.gpio_base		= AKITA_IOEXP_GPIO_BASE,
+};
 
-static void __init common_init(void)
-{
-	init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
-	pm_power_off = spitz_poweroff;
-	arm_pm_restart = spitz_restart;
+static struct i2c_board_info sharpslc_i2c_devs[] = {
+	{
+		.type		= "wm8750",
+		.addr		= 0x1b,
+	}, {
+		.type		= "max7310",
+		.addr		= 0x18,
+		.platform_data	= &akita_pca953x_pdata,
+	},
+};
 
-	if (machine_is_spitz()) {
-		sharpsl_nand_partitions[1].size = 5 * 1024 * 1024;
-	} else if (machine_is_akita()) {
-		sharpsl_nand_partitions[1].size = 58 * 1024 * 1024;
-	} else if (machine_is_borzoi()) {
-		sharpsl_nand_partitions[1].size = 32 * 1024 * 1024;
+static struct regulator_consumer_supply isl6271a_consumers[] = {
+	{
+		.supply	= "vcc_core",
 	}
+};
 
-	PMCR = 0x00;
-
-	/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
-	PCFR |= PCFR_OPDE;
+static struct regulator_init_data isl6271a_info[] = {
+	{
+		.constraints = {
+			.name		= "vcc_core range",
+			.min_uV		= 850000,
+			.max_uV		= 1600000,
+			.always_on	= 1,
+			.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		},
+	.consumer_supplies	= isl6271a_consumers,
+	.num_consumer_supplies	= ARRAY_SIZE(isl6271a_consumers),
+	}
+};
 
-	pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
+static struct i2c_board_info sharpslc_pi2c_devs[] = {
+	{
+		.type		= "isl6271a",
+		.addr		= 0x0c,
+		.platform_data	= &isl6271a_info,
+	},
+};
 
-	pxa_set_ffuart_info(NULL);
-	pxa_set_btuart_info(NULL);
-	pxa_set_stuart_info(NULL);
+static void __init sharpslc_i2c_init(void)
+{
+	int size = ARRAY_SIZE(sharpslc_i2c_devs);
 
-	spitz_init_spi();
+	/* Only Akita has the max7310 chip */
+	if (!machine_is_akita())
+		size--;
 
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	pxa_set_mci_info(&spitz_mci_platform_data);
-	pxa_set_ohci_info(&spitz_ohci_platform_data);
-	pxa_set_ficp_info(&spitz_ficp_platform_data);
-	set_pxa_fb_info(&spitz_pxafb_info);
 	pxa_set_i2c_info(NULL);
+	pxa27x_set_i2c_power_info(NULL);
+	i2c_register_board_info(0, sharpslc_i2c_devs, size);
+	i2c_register_board_info(1, ARRAY_AND_SIZE(sharpslc_pi2c_devs));
 }
-
-#if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI)
-static struct nand_bbt_descr sharpsl_akita_bbt = {
-	.options = 0,
-	.offs = 4,
-	.len = 1,
-	.pattern = scan_ff_pattern
-};
-
-static struct nand_ecclayout akita_oobinfo = {
-	.eccbytes = 24,
-	.eccpos = {
-		   0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
-		   0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
-		   0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
-	.oobfree = {{0x08, 0x09}}
-};
+#else
+static inline void sharpslc_i2c_init(void) {}
 #endif
 
-#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
-static void __init spitz_init(void)
+/******************************************************************************
+ * Machine init
+ ******************************************************************************/
+static void sharpslc_poweroff(void)
 {
-	spitz_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
-
-#ifdef CONFIG_MACH_BORZOI
-	if (machine_is_borzoi()) {
-		sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
-		sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
-	}
-#endif
-
-	platform_scoop_config = &spitz_pcmcia_config;
-
-	common_init();
-
-	platform_device_register(&spitzscoop2_device);
+	arm_machine_restart('g', NULL);
 }
-#endif
 
-#ifdef CONFIG_MACH_AKITA
-/*
- * Akita IO Expander
- */
-static struct pca953x_platform_data akita_ioexp = {
-	.gpio_base		= AKITA_IOEXP_GPIO_BASE,
-};
+static void sharpslc_restart(char mode, const char *cmd)
+{
+	/* Bootloader magic for a reboot */
+	if ((MSC0 & 0xffff0000) == 0x7ff00000)
+		MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
 
-static struct i2c_board_info akita_i2c_board_info[] = {
-	{
-		.type		= "max7310",
-		.addr		= 0x18,
-		.platform_data	= &akita_ioexp,
-	},
-};
+	sharpslc_poweroff();
+}
 
-static void __init akita_init(void)
+static void __init sharpslc_init(void)
 {
-	spitz_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
+	init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
+	pm_power_off = sharpslc_poweroff;
+	arm_pm_restart = sharpslc_restart;
 
-	sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
-	sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
+	PMCR = 0x00;
 
-	/* We just pretend the second element of the array doesn't exist */
-	spitz_pcmcia_config.num_devs = 1;
-	platform_scoop_config = &spitz_pcmcia_config;
+	/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
+	PCFR |= PCFR_OPDE;
 
-	i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_board_info));
+	pxa2xx_mfp_config(ARRAY_AND_SIZE(sharpslc_pin_config));
 
-	common_init();
+	pxa_set_ffuart_info(NULL);
+	pxa_set_btuart_info(NULL);
+	pxa_set_stuart_info(NULL);
+
+	sharpslc_spi_init();
+	sharpslc_scoop_init();
+	sharpslc_mkp_init();
+	sharpslc_keys_init();
+	sharpslc_leds_init();
+	sharpslc_mmc_init();
+	sharpslc_pcmcia_init();
+	sharpslc_irda_init();
+	sharpslc_uhc_init();
+	sharpslc_lcd_init();
+	sharpslc_nor_init();
+	sharpslc_nand_init();
+	sharpslc_i2c_init();
 }
-#endif
 
-static void __init fixup_spitz(struct machine_desc *desc,
+static void __init sharpslc_fixup(struct machine_desc *desc,
 		struct tag *tags, char **cmdline, struct meminfo *mi)
 {
 	sharpsl_save_param();
@@ -852,10 +982,10 @@ static void __init fixup_spitz(struct machine_desc *desc,
 MACHINE_START(SPITZ, "SHARP Spitz")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= spitz_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
@@ -864,10 +994,10 @@ MACHINE_END
 MACHINE_START(BORZOI, "SHARP Borzoi")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= spitz_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
@@ -876,10 +1006,10 @@ MACHINE_END
 MACHINE_START(AKITA, "SHARP Akita")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= akita_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
-- 
1.7.1



From anarsoul at gmail.com  Sat Jun 12 08:46:03 2010
From: anarsoul at gmail.com (Vasily Khoruzhick)
Date: Sat, 12 Jun 2010 15:46:03 +0300
Subject: [PATCH] h1940: implement mmc_power function
Message-ID: <1276346763-29309-1-git-send-email-anarsoul@gmail.com>

Signed-off-by: Vasily Khoruzhick <anarsoul at gmail.com>
---
 arch/arm/mach-s3c2410/include/mach/h1940-latch.h |    7 +++----
 arch/arm/mach-s3c2410/mach-h1940.c               |   17 ++++++++++++++++-
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h
index d8a8327..a29bc1c 100644
--- a/arch/arm/mach-s3c2410/include/mach/h1940-latch.h
+++ b/arch/arm/mach-s3c2410/include/mach/h1940-latch.h
@@ -39,8 +39,8 @@
 #define H1940_LATCH_UDA_POWER		(1<<24)
 #define H1940_LATCH_AUDIO_POWER		(1<<25)
 #define H1940_LATCH_SM803_ENABLE	(1<<26)
-#define H1940_LATCH_LCD_P4		(1<<27)
-#define H1940_LATCH_CPUQ5		(1<<28)		/* untraced */
+#define H1940_LATCH_LCD_P4			(1<<27)
+#define H1940_LATCH_SD_POWER		(1<<28)
 #define H1940_LATCH_BLUETOOTH_POWER	(1<<29)		/* active high */
 #define H1940_LATCH_LED_GREEN		(1<<30)
 #define H1940_LATCH_LED_FLASH		(1<<31)
@@ -54,8 +54,7 @@
 	H1940_LATCH_LCD_P1		| \
 	H1940_LATCH_LCD_P2		| \
 	H1940_LATCH_LCD_P3		| \
-	H1940_LATCH_MAX1698_nSHUTDOWN   | \
-	H1940_LATCH_CPUQ5
+	H1940_LATCH_MAX1698_nSHUTDOWN
 
 /* control functions */
 
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 779b45b..ddeedad 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -198,10 +198,25 @@ static struct platform_device h1940_device_bluetooth = {
 	.id               = -1,
 };
 
+static void h1940_set_mmc_power(unsigned char power_mode, unsigned short vdd)
+{
+	switch (power_mode) {
+	case MMC_POWER_OFF:
+		h1940_latch_control(H1940_LATCH_SD_POWER, 0);
+		break;
+	case MMC_POWER_UP:
+	case MMC_POWER_ON:
+		h1940_latch_control(0, H1940_LATCH_SD_POWER);
+		break;
+	default:
+		break;
+	}
+}
+
 static struct s3c24xx_mci_pdata h1940_mmc_cfg __initdata = {
 	.gpio_detect   = S3C2410_GPF(5),
 	.gpio_wprotect = S3C2410_GPH(8),
-	.set_power     = NULL,
+	.set_power     = h1940_set_mmc_power,
 	.ocr_avail     = MMC_VDD_32_33,
 };
 
-- 
1.7.1



From marek.vasut at gmail.com  Sat Jun 12 08:47:33 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat, 12 Jun 2010 14:47:33 +0200
Subject: [PATCH 3/3] wm97xx_batt: Remove redundant header file
In-Reply-To: <AANLkTimb6TqQLLHDLI_qInwScZUQpYIDxNymE8SUh_9J@mail.gmail.com>
References: <1275613654-23918-1-git-send-email-marek.vasut@gmail.com>
	<1275613654-23918-3-git-send-email-marek.vasut@gmail.com>
	<AANLkTimb6TqQLLHDLI_qInwScZUQpYIDxNymE8SUh_9J@mail.gmail.com>
Message-ID: <201006121447.33221.marek.vasut@gmail.com>

Dne So 12. ?ervna 2010 11:16:58 Eric Miao napsal(a):
> On Fri, Jun 4, 2010 at 9:07 AM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> > ---
> >  include/linux/wm97xx_batt.h |   16 ----------------
> >  1 files changed, 0 insertions(+), 16 deletions(-)
> >  delete mode 100644 include/linux/wm97xx_batt.h
> > 
> > diff --git a/include/linux/wm97xx_batt.h b/include/linux/wm97xx_batt.h
> > deleted file mode 100644
> > index a1d6419..0000000
> > --- a/include/linux/wm97xx_batt.h
> > +++ /dev/null
> > @@ -1,16 +0,0 @@
> > -#ifndef _LINUX_WM97XX_BAT_H
> > -#define _LINUX_WM97XX_BAT_H
> > -
> > -#include <linux/wm97xx.h>
> > -
> > -#warning This file will be removed soon, use wm97xx.h instead!
> > -
> > -#define wm97xx_batt_info wm97xx_batt_pdata
> > -
> > -#ifdef CONFIG_BATTERY_WM97XX
> > -void wm97xx_bat_set_pdata(struct wm97xx_batt_info *data);
> > -#else
> > -static inline void wm97xx_bat_set_pdata(struct wm97xx_batt_info *data)
> > {} -#endif
> > -
> > -#endif
> 
> A git grep of wm97xx_batt.h shows:
> 
> drivers/power/wm97xx_battery.c:/* The interface is deprecated, as well
> as linux/wm97xx_batt.h */
> 
> So you may want to remove that part as well. Otherwise looks good to me.

Thanks, good catch. But let's push this through a separate patch, shall we?


From marek.vasut at gmail.com  Sat Jun 12 08:51:13 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sat, 12 Jun 2010 14:51:13 +0200
Subject: [PATCH] wm97xx_batt: Remove deprecated method to set pdata
Message-ID: <1276347073-3055-1-git-send-email-marek.vasut@gmail.com>

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/power/wm97xx_battery.c |   16 ----------------
 1 files changed, 0 insertions(+), 16 deletions(-)

diff --git a/drivers/power/wm97xx_battery.c b/drivers/power/wm97xx_battery.c
index 4e8afce..5071d85 100644
--- a/drivers/power/wm97xx_battery.c
+++ b/drivers/power/wm97xx_battery.c
@@ -29,7 +29,6 @@ static DEFINE_MUTEX(bat_lock);
 static struct work_struct bat_work;
 static struct mutex work_lock;
 static int bat_status = POWER_SUPPLY_STATUS_UNKNOWN;
-static struct wm97xx_batt_info *gpdata;
 static enum power_supply_property *prop;
 
 static unsigned long wm97xx_read_bat(struct power_supply *bat_ps)
@@ -172,12 +171,6 @@ static int __devinit wm97xx_bat_probe(struct platform_device *dev)
 	struct wm97xx_pdata *wmdata = dev->dev.platform_data;
 	struct wm97xx_batt_pdata *pdata;
 
-	if (gpdata) {
-		dev_err(&dev->dev, "Do not pass platform_data through "
-			"wm97xx_bat_set_pdata!\n");
-		return -EINVAL;
-	}
-
 	if (!wmdata) {
 		dev_err(&dev->dev, "No platform data supplied\n");
 		return -EINVAL;
@@ -308,15 +301,6 @@ static void __exit wm97xx_bat_exit(void)
 	platform_driver_unregister(&wm97xx_bat_driver);
 }
 
-/* The interface is deprecated, as well as linux/wm97xx_batt.h */
-void wm97xx_bat_set_pdata(struct wm97xx_batt_info *data);
-
-void wm97xx_bat_set_pdata(struct wm97xx_batt_info *data)
-{
-	gpdata = data;
-}
-EXPORT_SYMBOL_GPL(wm97xx_bat_set_pdata);
-
 module_init(wm97xx_bat_init);
 module_exit(wm97xx_bat_exit);
 
-- 
1.7.1



From jason77.wang at gmail.com  Sat Jun 12 10:22:35 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Sat, 12 Jun 2010 22:22:35 +0800
Subject: [PATCH 0/4]Refine iomux files for i.MX51
Message-ID: <1276352559-8105-1-git-send-email-jason77.wang@gmail.com>

Through the discussion, I divide my patches to 3 parts.
part1: mx51 iomux related part, the first patch in this part is from
       Amit, other patches are based off this patch and they are some
       fix or adding definitions for imx51_3ds board.
part2: mxc common cpld debugboard patches. In this part, include a
       reverting mx31_3ds patch. I have made built and bootup test
       for mx31_3ds platform.
part3: adding mx51_3ds platform patches.

Because part3 depends on part1 and part2, while part1 and part2 are
independent mutually, i will send part1 and part2 first, if these
two parts are passed review, then i will send part3.

part1:
 [PATCH 1/4] mxc: Fix pad names for imx51
 [PATCH 2/4] mx51/iomux: Fix mux mode and input path for two pads
 [PATCH 3/4] mx51/iomux: add UART and GPIO pad definitions for imx51_3ds board
 [PATCH 4/4] mxc/iomux: add GPIO bank offset for iomux v3 platforms

part2:
 [PATCH 1/2] mxc: add common debug board for 3-stack platforms
 [PATCH 2/2] mx31_3ds: revert cpld debug board relate code




From jason77.wang at gmail.com  Sat Jun 12 10:22:36 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Sat, 12 Jun 2010 22:22:36 +0800
Subject: [PATCH 1/4] mxc: Fix pad names for imx51
In-Reply-To: <1276352559-8105-1-git-send-email-jason77.wang@gmail.com>
References: <1276352559-8105-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <1276352559-8105-2-git-send-email-jason77.wang@gmail.com>

From: Amit Kucheria <amit.kucheria at canonical.com>

The pads capable of being used as GPIOs had their pad-name and mode-name
switched. Also fix the following:

- Whitespace fixes
- Replace IOMUX_CONFIG_ALTn with 'n'

Signed-off-by: Amit Kucheria <amit.kucheria at canonical.com>
---
 arch/arm/mach-mx5/board-mx51_babbage.c      |    2 +-
 arch/arm/plat-mxc/include/mach/iomux-mx51.h |  533 +++++++++++++--------------
 2 files changed, 252 insertions(+), 283 deletions(-)

diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index ed885f9..4f96d9c 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -78,7 +78,7 @@ static struct pad_desc mx51babbage_pads[] = {
 	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 
 	/* USB HUB reset line*/
-	MX51_PAD_GPIO_1_7__GPIO1_7,
+	MX51_PAD_GPIO_1_7__GPIO_1_7,
 };
 
 /* Serial ports */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index ab0f95d..e8648bc 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -27,8 +27,8 @@ typedef enum iomux_config {
 	IOMUX_CONFIG_ALT5,
 	IOMUX_CONFIG_ALT6,
 	IOMUX_CONFIG_ALT7,
-	IOMUX_CONFIG_GPIO,	/* added to help user use GPIO mode */
-	IOMUX_CONFIG_SION = 0x1 << 4,	/* LOOPBACK:MUX SION bit */
+	IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
+	IOMUX_CONFIG_SION = 0x1 << 4,   /* LOOPBACK:MUX SION bit */
 } iomux_pin_cfg_t;
 
 /* Pad control groupings */
@@ -50,285 +50,254 @@ typedef enum iomux_config {
  * GPIO_<unit>_<num> see also iomux-v3.h
  */
 
-/*
- * FIXME: This was converted using scripts from existing Freescale code to
- * this form used upstream. Need to verify the name format.
- */
-
-/*						PAD      MUX   ALT INPSE PATH PADCTRL */
-
-#define MX51_PAD_GPIO_2_0__EIM_D16	IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_1__EIM_D17	IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_2__EIM_D18	IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_3__EIM_D19	IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_4__EIM_D20	IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_5__EIM_D21	IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO_2_5	IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_6__EIM_D22	IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_7__EIM_D23	IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
-
-/* Babbage UART3 */
-#define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
-
-#define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30	IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31	IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_10__EIM_A16	IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_11__EIM_A17	IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_12__EIM_A18	IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_13__EIM_A19	IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_14__EIM_A20	IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_15__EIM_A21	IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_16__EIM_A22	IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_17__EIM_A23	IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_18__EIM_A24	IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_19__EIM_A25	IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_20__EIM_A26	IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_21__EIM_A27	IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0	IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1	IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_22__EIM_EB2	IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_23__EIM_EB3	IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_24__EIM_OE	IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_25__EIM_CS0	IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_26__EIM_CS1	IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_27__EIM_CS2	IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_28__EIM_CS3	IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_29__EIM_CS4	IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_30__EIM_CS5	IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_31__EIM_DTACK	IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_3_1__EIM_LBA	IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__EIM_CRE	IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1	IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__NANDF_WE_B	IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__NANDF_RE_B	IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__NANDF_ALE	IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__NANDF_CLE	IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__NANDF_WP_B	IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__NANDF_RB0	IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_9__NANDF_RB1	IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_10__NANDF_RB2	IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_11__NANDF_RB3	IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__GPIO_NAND	IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
-/* REVISIT: Not sure of these values
-
-  #define MX51_PAD_GPIO_1___NANDF_RB4	IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_13__NANDF_RB5	IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_15__NANDF_RB7	IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-*/
-#define MX51_PAD_GPIO_3_14__NANDF_RB6	IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_16__NANDF_CS0	IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_17__NANDF_CS1	IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_18__NANDF_CS2	IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_19__NANDF_CS3	IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_20__NANDF_CS4	IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_21__NANDF_CS5	IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_22__NANDF_CS6	IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_23__NANDF_CS7	IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT	IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_25__NANDF_D15	IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_26__NANDF_D14	IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_27__NANDF_D13	IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_28__NANDF_D12	IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_29__NANDF_D11	IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_30__NANDF_D10	IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_31__NANDF_D9	IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_0__NANDF_D8	IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_1__NANDF_D7	IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_2__NANDF_D6	IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_3__NANDF_D5	IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_4__NANDF_D4	IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_5__NANDF_D3	IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_6__NANDF_D2	IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_7__NANDF_D1	IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_8__NANDF_D0	IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__CSI1_D8	IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_13__CSI1_D9	IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10	IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11	IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12	IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13	IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14	IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15	IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16	IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17	IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18	IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19	IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC	IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC	IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK	IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK	IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PKE0__CSI1_PKE0	IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_9__CSI2_D12	IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_10__CSI2_D13	IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D14	IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D15	IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D16	IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D17	IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D18	IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D19	IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_13__CSI2_VSYNC	IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_14__CSI2_HSYNC	IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK	IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PKE0__CSI2_PKE0	IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_16__I2C1_CLK	IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_17__I2C1_DAT	IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD	IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD	IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_20__AUD3_BB_CK	IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_21__AUD3_BB_FS	IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_22__CSPI1_MOSI	IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_23__CSPI1_MISO	IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_24__CSPI1_SS0	IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_25__CSPI1_SS1	IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_26__CSPI1_RDY	IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_27__CSPI1_SCLK	IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
-
-/* Babbage UART1 */
-#define MX51_PAD_UART1_RXD__UART1_RXD	IOMUX_PAD(0x618, 0x228,	IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_TXD__UART1_TXD	IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_RTS__UART1_RTS	IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS	IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
-
-/* Babbage UART2 */
-#define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
-
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_24__OWIRE_LINE	IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0	IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1	IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2	IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3	IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0	IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1	IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2	IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3	IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__KEY_COL4	IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__KEY_COL5	IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK	IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR	IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO_1_27	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT	IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_GPIO_3_0__DI1_PIN11	IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_1__DI1_PIN12	IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__DI1_PIN13	IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__DI1_D0_CS	IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__DI1_D1_CS	IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN	IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO	IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK	IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS	IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0	IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1	IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2	IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3	IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4	IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5	IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6	IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7	IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8	IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9	IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3	IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2	IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP1__DI_GP1	IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DI_GP2	IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DI_GP3	IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4	IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2	IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3	IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI_GP4	IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0	IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1	IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2	IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3	IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4	IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5	IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_19__DISP2_DAT6	IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_29__DISP2_DAT7	IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_30__DISP2_DAT8	IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_31__DISP2_DAT9	IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD	IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK	IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0	IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1	IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2	IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3	IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_0__GPIO1_0	IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_1__GPIO1_1	IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD	IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK	IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0	IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1	IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2	IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3	IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_2__GPIO1_2	IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_3__GPIO1_3	IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_4__GPIO1_4	IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_5__GPIO1_5	IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_7__GPIO1_7	IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_8__GPIO1_8	IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
-						(PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
-#define MX51_PAD_GPIO_1_9__GPIO1_9	IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
-
-/* EIM */
-#define MX51_PAD_EIM_DA0__EIM_DA0	IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1	IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2	IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3	IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4	IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5	IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6	IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7	IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_DA8__EIM_DA8	IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9	IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10	IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11	IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12	IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13	IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14	IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15	IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+/*							  PAD    MUX   ALT INPSE PATH PADCTRL */
+#define MX51_PAD_EIM_DA0__EIM_DA0		IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA1__EIM_DA1		IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA2__EIM_DA2		IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA3__EIM_DA3		IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA4__EIM_DA4		IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA5__EIM_DA5		IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA6__EIM_DA6		IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA7__EIM_DA7		IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA8__EIM_DA8		IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA9__EIM_DA9		IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA10__EIM_DA10		IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA11__EIM_DA11		IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA12__EIM_DA12		IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA13__EIM_DA13		IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA14__EIM_DA14		IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA15__EIM_DA15		IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__GPIO_2_0              IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D17__GPIO_2_1              IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__GPIO_2_2              IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__GPIO_2_3              IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D20__GPIO_2_4              IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO_2_5		IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__GPIO_2_6              IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__GPIO_2_7              IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__GPIO_2_10             IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__GPIO_2_11             IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__GPIO_2_12             IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__GPIO_2_13             IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO_2_14             IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__GPIO_2_15             IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__GPIO_2_16             IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__GPIO_2_17             IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__GPIO_2_18             IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__GPIO_2_19             IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__GPIO_2_20             IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__GPIO_2_21             IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__GPIO_2_22             IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPIO_2_23             IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__GPIO_2_24              IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__GPIO_2_25             IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__GPIO_2_26             IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__GPIO_2_27             IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__GPIO_2_28             IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__GPIO_2_29             IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__GPIO_2_30             IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__GPIO_2_31           IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__GPIO_3_1              IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__GPIO_3_2              IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4D0, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__GPIO_3_3           IOMUX_PAD(0x4E4, 0x108, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__GPIO_3_4           IOMUX_PAD(0x4E8, 0x10C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__GPIO_3_5            IOMUX_PAD(0x4EC, 0x110, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__GPIO_3_6            IOMUX_PAD(0x4F0, 0x114, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__GPIO_3_7           IOMUX_PAD(0x4F4, 0x118, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__GPIO_3_12           IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__GPIO_3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__GPIO_3_17           IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__GPIO_3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__GPIO_3_19           IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__GPIO_3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__GPIO_3_21           IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__GPIO_3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__GPIO_3_23           IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__GPIO_3_29           IOMUX_PAD(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__GPIO_3_30           IOMUX_PAD(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__GPIO_3_31            IOMUX_PAD(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__GPIO_4_0             IOMUX_PAD(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__GPIO_4_1             IOMUX_PAD(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__GPIO_4_2             IOMUX_PAD(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__GPIO_4_3             IOMUX_PAD(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__GPIO_4_4             IOMUX_PAD(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__GPIO_4_5             IOMUX_PAD(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__GPIO_4_6             IOMUX_PAD(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__GPIO_4_7             IOMUX_PAD(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__GPIO_4_8             IOMUX_PAD(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__GPIO_3_12             IOMUX_PAD(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__GPIO_3_13             IOMUX_PAD(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5B4, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5B8, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PKE0__CSI1_PKE0           IOMUX_PAD(0x860, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__GPIO_4_9             IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__GPIO_4_10            IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__GPIO_4_11            IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__GPIO_4_12            IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__GPIO_4_11            IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__GPIO_4_12            IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__GPIO_4_11            IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__GPIO_4_12            IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__GPIO_4_13          IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__GPIO_4_14          IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15         IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__GPIO_4_16            IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__GPIO_4_17            IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18         IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19         IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__GPIO_4_20          IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__GPIO_4_21          IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__GPIO_4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__GPIO_4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__GPIO_4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__GPIO_4_25           IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__GPIO_4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO_1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO_1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__GPIO_1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO_1_27           IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__GPIO_3_0            IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP1__DI_GP1                 IOMUX_PAD(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DI_GP2                 IOMUX_PAD(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DI_GP3                 IOMUX_PAD(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI_GP4                 IOMUX_PAD(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__GPIO_1_19          IOMUX_PAD(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__GPIO_1_29          IOMUX_PAD(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__GPIO_1_30          IOMUX_PAD(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__GPIO_1_31          IOMUX_PAD(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_0__GPIO_1_0		IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_1__GPIO_1_1		IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
 
 #endif /* __MACH_IOMUX_MX51_H__ */
-- 
1.5.6.5



From jason77.wang at gmail.com  Sat Jun 12 10:22:37 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Sat, 12 Jun 2010 22:22:37 +0800
Subject: [PATCH 2/4] mx51/iomux: Fix mux mode and input path for two pads
In-Reply-To: <1276352559-8105-2-git-send-email-jason77.wang@gmail.com>
References: <1276352559-8105-1-git-send-email-jason77.wang@gmail.com>
	<1276352559-8105-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <1276352559-8105-3-git-send-email-jason77.wang@gmail.com>

For pad EIM_D27 to work in UART3_RTS mode, the input path should be
3 instead of 0; for pad USBH1_STP to work in GPIO_1_27 mode, the mux
value should be 2 instead of 8.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/include/mach/iomux-mx51.h |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index e8648bc..7433369 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -78,7 +78,7 @@ typedef enum iomux_config {
 #define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
@@ -207,7 +207,7 @@ typedef enum iomux_config {
 #define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
 #define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
 #define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO_1_27           IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO_1_27           IOMUX_PAD(0x680, 0x280, 2, 0x0,   0, MX51_USBH1_PAD_CTRL)
 #define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
 #define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
 #define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
-- 
1.5.6.5



From jason77.wang at gmail.com  Sat Jun 12 10:22:38 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Sat, 12 Jun 2010 22:22:38 +0800
Subject: [PATCH 3/4] mx51/iomux: add UART and GPIO pad definitions for
	imx51_3ds board
In-Reply-To: <1276352559-8105-3-git-send-email-jason77.wang@gmail.com>
References: <1276352559-8105-1-git-send-email-jason77.wang@gmail.com>
	<1276352559-8105-2-git-send-email-jason77.wang@gmail.com>
	<1276352559-8105-3-git-send-email-jason77.wang@gmail.com>
Message-ID: <1276352559-8105-4-git-send-email-jason77.wang@gmail.com>

Add UART2 CTS/RTS and UART3 RXD/TXD pad definitons for imx51_3ds board,
add GPIO_1_6 definiton because this pin is used as a CPLD parent irq
request pin on imx51_3ds board.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/include/mach/iomux-mx51.h |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 7433369..2fc6559 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -77,7 +77,9 @@ typedef enum iomux_config {
 #define MX51_PAD_EIM_D23__GPIO_2_7              IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART2_CTS		IOMUX_PAD(0x414, 0x080, 4, 0x0,   0, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART2_RTS		IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
@@ -191,7 +193,9 @@ typedef enum iomux_config {
 #define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
 #define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
 #define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__UART3_RXD		IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_UART3_RXD__GPIO_1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__UART3_TXD		IOMUX_PAD(0x634, 0x244, 1, 0x0,   0, MX51_UART3_PAD_CTRL)
 #define MX51_PAD_UART3_TXD__GPIO_1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_OWIRE_LINE__GPIO_1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
@@ -295,7 +299,7 @@ typedef enum iomux_config {
 #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
-- 
1.5.6.5



From jason77.wang at gmail.com  Sat Jun 12 10:22:39 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Sat, 12 Jun 2010 22:22:39 +0800
Subject: [PATCH 4/4] mxc/iomux: add GPIO bank offset for iomux v3 platforms
In-Reply-To: <1276352559-8105-4-git-send-email-jason77.wang@gmail.com>
References: <1276352559-8105-1-git-send-email-jason77.wang@gmail.com>
	<1276352559-8105-2-git-send-email-jason77.wang@gmail.com>
	<1276352559-8105-3-git-send-email-jason77.wang@gmail.com>
	<1276352559-8105-4-git-send-email-jason77.wang@gmail.com>
Message-ID: <1276352559-8105-5-git-send-email-jason77.wang@gmail.com>

These GPIO bank offsets are useful when define a gpio number.
E.G. when GPIO PORTC pin 6 is used for irq request pin of external
expanding device, we can define it like:
  #define EXP_PARENT_IRQ_PIN (GPIO_PORTC + 6)

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/include/mach/iomux-v3.h |   15 +++++++++++++++
 1 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index f2f73d3..0880a4a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -89,6 +89,21 @@ struct pad_desc {
 #define PAD_CTL_SRE_FAST		(1 << 0)
 #define PAD_CTL_SRE_SLOW		(0 << 0)
 
+
+#define MX51_NUM_GPIO_PORT	4
+
+#define GPIO_PIN_MASK 0x1f
+
+#define GPIO_PORT_SHIFT 5
+#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
+
+#define GPIO_PORTA	(0 << GPIO_PORT_SHIFT)
+#define GPIO_PORTB	(1 << GPIO_PORT_SHIFT)
+#define GPIO_PORTC	(2 << GPIO_PORT_SHIFT)
+#define GPIO_PORTD	(3 << GPIO_PORT_SHIFT)
+#define GPIO_PORTE	(4 << GPIO_PORT_SHIFT)
+#define GPIO_PORTF	(5 << GPIO_PORT_SHIFT)
+
 /*
  * setups a single pad in the iomuxer
  */
-- 
1.5.6.5



From david-b at pacbell.net  Sat Jun 12 10:24:30 2010
From: david-b at pacbell.net (David Brownell)
Date: Sat, 12 Jun 2010 07:24:30 -0700 (PDT)
Subject: [PATCH 4/5] [ARM] usb/host/ohci-pxa27x: make PXA310 USB OTG port
	work in host mode.
In-Reply-To: <AANLkTilUt8D7B3UF_j1wOvsnXTVQyioofwMEikScdLOn@mail.gmail.com>
Message-ID: <614940.91741.qm@web180314.mail.gq1.yahoo.com>



--- On Sat, 6/12/10, Eric Miao <eric.y.miao at gmail.com> wrote:

> > ?arch/arm/mach-pxa/include/mach/ohci.h ? ? | ? ?3
> +
> > ?arch/arm/mach-pxa/include/mach/regs-u2d.h | ? ?2
> +
> > ?drivers/usb/host/ohci-pxa27x.c ? ? ? ? ? ?|
> ?183 +++++++++++++++++++++++++++++

Doesn't touch generic OHCI code, so it looks
OK to me... ack.
> 
> My feeling is on pxa310, the OTG/ULPI is actually closer to
> the UDC, so
> generally, I'd really like to see minimum change to ohci.
> 



From jason77.wang at gmail.com  Sat Jun 12 10:25:05 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Sat, 12 Jun 2010 22:25:05 +0800
Subject: [PATCH 0/2]Add mxc common CPLD debugboard support
Message-ID: <1276352707-8199-1-git-send-email-jason77.wang@gmail.com>

part2:
 [PATCH 1/2] mxc: add common debug board for 3-stack platforms
 [PATCH 2/2] mx31_3ds: revert cpld debug board relate code




From jason77.wang at gmail.com  Sat Jun 12 10:25:06 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Sat, 12 Jun 2010 22:25:06 +0800
Subject: [PATCH 1/2] mxc: add common debug board for 3-stack platforms
In-Reply-To: <1276352707-8199-1-git-send-email-jason77.wang@gmail.com>
References: <1276352707-8199-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <1276352707-8199-2-git-send-email-jason77.wang@gmail.com>

The debug board is little different for all mxc 3-stack(PDK)
platforms, it is possible here to add a common implementation to
support this board.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/Kconfig                        |   11 ++
 arch/arm/plat-mxc/Makefile                       |    1 +
 arch/arm/plat-mxc/cpld_debugboard.c              |  161 ++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/cpld_debugboard.h |   60 ++++++++
 4 files changed, 233 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-mxc/cpld_debugboard.c
 create mode 100644 arch/arm/plat-mxc/include/mach/cpld_debugboard.h

diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 7f7ad6f..8bf917e 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -81,6 +81,17 @@ config MXC_PWM
 	help
 	  Enable support for the i.MX PWM controller(s).
 
+config MXC_DEBUG_BOARD
+	bool "Enable MXC debug board(for 3-stack)"
+	help
+	  The debug board is an integral part of the MXC 3-stack(PDK)
+	  platforms, it can be attached or removed from the peripheral
+	  board. On debug board, several debug devices(ethernet, UART,
+	  buttons, LEDs and JTAG) are implemented. Between the MCU and
+	  these devices, a CPLD is added as a bridge which performs
+	  data/address de-multiplexing and decode, signal level shift,
+	  interrupt control and various board functions.
+
 config MXC_ULPI
 	bool
 
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 895bc3c..b9e8c6f 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
+obj-$(CONFIG_MXC_DEBUG_BOARD) += cpld_debugboard.o
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
diff --git a/arch/arm/plat-mxc/cpld_debugboard.c b/arch/arm/plat-mxc/cpld_debugboard.c
new file mode 100644
index 0000000..0554fa0
--- /dev/null
+++ b/arch/arm/plat-mxc/cpld_debugboard.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <mach/hardware.h>
+#include <mach/cpld_debugboard.h>
+
+static void __iomem *brd_io;
+static void expio_ack_irq(u32 irq);
+
+static struct resource smsc911x_resources[] = {
+	{
+		.flags = IORESOURCE_MEM,
+	} , {
+		.start = EXPIO_INT_ENET,
+		.end = EXPIO_INT_ENET,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+struct smsc911x_platform_config smsc911x_config = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+};
+
+struct platform_device smsc_lan9217_device = {
+	.name = "smsc911x",
+	.id = 0,
+	.dev = {
+		.platform_data = &smsc911x_config,
+	},
+	.num_resources = ARRAY_SIZE(smsc911x_resources),
+	.resource = smsc911x_resources,
+};
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+	u32 imr_val;
+	u32 int_valid;
+	u32 expio_irq;
+
+	desc->chip->mask(irq);	/* irq = gpio irq number */
+
+	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
+	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
+
+	expio_irq = MXC_BOARD_IRQ_START;
+	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+		struct irq_desc *d;
+		if ((int_valid & 1) == 0)
+			continue;
+		d = irq_desc + expio_irq;
+		if (unlikely(!(d->handle_irq)))
+			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
+		else
+			d->handle_irq(expio_irq, d);
+	}
+
+	desc->chip->ack(irq);
+	desc->chip->unmask(irq);
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * Irq is an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg |= (1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static void expio_ack_irq(u32 irq)
+{
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	expio_mask_irq(irq);
+}
+
+static void expio_unmask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg &= ~(1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+	.ack = expio_ack_irq,
+	.mask = expio_mask_irq,
+	.unmask = expio_unmask_irq,
+};
+
+int __init mxc_expio_init(u32 base, u32 p_irq)
+{
+	int i;
+
+	brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
+	if (brd_io == NULL)
+		return -ENOMEM;
+
+	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
+		pr_info("3-Stack Debug board not detected\n");
+		iounmap(brd_io);
+		brd_io = NULL;
+		return -ENODEV;
+	}
+
+	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
+		readw(brd_io + CPLD_CODE_VER_REG));
+
+	smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
+	smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
+
+	/*
+	 * Configure INT line as GPIO input
+	 */
+	gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
+	gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
+
+	/* disable the interrupt and clear the status */
+	__raw_writew(0, brd_io + INTR_MASK_REG);
+	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
+	for (i = MXC_EXP_IO_BASE;
+	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
+		set_irq_chip(i, &expio_irq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+	set_irq_type(p_irq, IRQF_TRIGGER_LOW);
+	set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
+
+	return 0;
+}
diff --git a/arch/arm/plat-mxc/include/mach/cpld_debugboard.h b/arch/arm/plat-mxc/include/mach/cpld_debugboard.h
new file mode 100644
index 0000000..a1422d2
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/cpld_debugboard.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_CPLD_DB_H__
+#define __ASM_ARCH_MXC_CPLD_DB_H__
+
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR(n)	(n + 0x0)
+/* External UART */
+#define UARTA_BASE_ADDR(n)	(n + 0x8000)
+#define UARTB_BASE_ADDR(n)	(n + 0x10000)
+
+#define BOARD_IO_ADDR(n)	(n + 0x20000)
+/* LED switchs */
+#define LED_SWITCH_REG		0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG	0x08
+/* status, interrupt */
+#define INTR_STATUS_REG	0x10
+#define INTR_MASK_REG		0x38
+#define INTR_RESET_REG		0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG	0x40
+#define MAGIC_NUMBER2_REG	0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG	0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG	0x58
+/* module reset register*/
+#define MODULE_RESET_REG	0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG	0x68
+
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_GPIO(irq)	((irq) - MXC_INTERNAL_IRQS)
+
+#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
+#define MXC_MAX_EXP_IO_LINES	16
+
+/* interrupts like external uart , external ethernet etc*/
+#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
+#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
+#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
+#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
+#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
+
+extern struct platform_device smsc_lan9217_device;
+
+int __init mxc_expio_init(u32 base, u32 p_irq);
+
+#endif /* __ASM_ARCH_MXC_CPLD_DB_H__ */
-- 
1.5.6.5



From jason77.wang at gmail.com  Sat Jun 12 10:25:07 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Sat, 12 Jun 2010 22:25:07 +0800
Subject: [PATCH 2/2] mx31_3ds: revert cpld debug board relate code
In-Reply-To: <1276352707-8199-2-git-send-email-jason77.wang@gmail.com>
References: <1276352707-8199-1-git-send-email-jason77.wang@gmail.com>
	<1276352707-8199-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <1276352707-8199-3-git-send-email-jason77.wang@gmail.com>

Because we add a cpld debug board support in mxc level, we remove
those redudent codes from board level.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx3/Kconfig                       |    1 +
 arch/arm/mach-mx3/mach-mx31_3ds.c               |  168 +----------------------
 arch/arm/plat-mxc/include/mach/board-mx31_3ds.h |   42 ------
 3 files changed, 4 insertions(+), 207 deletions(-)

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753f..fd422cf 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -58,6 +58,7 @@ config MACH_MX31LITE
 config MACH_MX31_3DS
 	bool "Support MX31PDK (3DS)"
 	select ARCH_MX31
+	select MXC_DEBUG_BOARD
 	help
 	  Include support for MX31PDK (3DS) platform. This includes specific
 	  configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 58e5729..d8af726 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -22,7 +22,6 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/smsc911x.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
@@ -38,6 +37,7 @@
 #include <asm/mach/map.h>
 #include <mach/common.h>
 #include <mach/board-mx31_3ds.h>
+#include <mach/cpld_debugboard.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/mxc_nand.h>
@@ -213,173 +213,11 @@ static struct imxuart_platform_data uart_pdata = {
 };
 
 /*
- * Support for the SMSC9217 on the Debug board.
- */
-
-static struct smsc911x_platform_config smsc911x_config = {
-	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
-	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-	.phy_interface	= PHY_INTERFACE_MODE_MII,
-};
-
-static struct resource smsc911x_resources[] = {
-	{
-		.start		= LAN9217_BASE_ADDR,
-		.end		= LAN9217_BASE_ADDR + 0xff,
-		.flags		= IORESOURCE_MEM,
-	}, {
-		.start		= EXPIO_INT_ENET,
-		.end		= EXPIO_INT_ENET,
-		.flags		= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device smsc911x_device = {
-	.name		= "smsc911x",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(smsc911x_resources),
-	.resource	= smsc911x_resources,
-	.dev		= {
-		.platform_data = &smsc911x_config,
-	},
-};
-
-/*
- * Routines for the CPLD on the debug board. It contains a CPLD handling
- * LEDs, switches, interrupts for Ethernet.
- */
-
-static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
-{
-	uint32_t imr_val;
-	uint32_t int_valid;
-	uint32_t expio_irq;
-
-	imr_val = __raw_readw(CPLD_INT_MASK_REG);
-	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
-
-	expio_irq = MXC_EXP_IO_BASE;
-	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
-		if ((int_valid & 1) == 0)
-			continue;
-		generic_handle_irq(expio_irq);
-	}
-}
-
-/*
- * Disable an expio pin's interrupt by setting the bit in the imr.
- * @param irq           an expio virtual irq number
- */
-static void expio_mask_irq(uint32_t irq)
-{
-	uint16_t reg;
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* mask the interrupt */
-	reg = __raw_readw(CPLD_INT_MASK_REG);
-	reg |= 1 << expio;
-	__raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-/*
- * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
- * @param irq           an expanded io virtual irq number
- */
-static void expio_ack_irq(uint32_t irq)
-{
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* clear the interrupt status */
-	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
-	__raw_writew(0, CPLD_INT_RESET_REG);
-	/* mask the interrupt */
-	expio_mask_irq(irq);
-}
-
-/*
- * Enable a expio pin's interrupt by clearing the bit in the imr.
- * @param irq           a expio virtual irq number
- */
-static void expio_unmask_irq(uint32_t irq)
-{
-	uint16_t reg;
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* unmask the interrupt */
-	reg = __raw_readw(CPLD_INT_MASK_REG);
-	reg &= ~(1 << expio);
-	__raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-static struct irq_chip expio_irq_chip = {
-	.ack = expio_ack_irq,
-	.mask = expio_mask_irq,
-	.unmask = expio_unmask_irq,
-};
-
-static int __init mx31_3ds_init_expio(void)
-{
-	int i;
-	int ret;
-
-	/* Check if there's a debug board connected */
-	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
-	    (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
-	    (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
-		/* No Debug board found */
-		return -ENODEV;
-	}
-
-	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
-		__raw_readw(CPLD_CODE_VER_REG));
-
-	/*
-	 * Configure INT line as GPIO input
-	 */
-	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
-	if (ret)
-		pr_warning("could not get LAN irq gpio\n");
-	else
-		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-
-	/* Disable the interrupts and clear the status */
-	__raw_writew(0, CPLD_INT_MASK_REG);
-	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
-	__raw_writew(0, CPLD_INT_RESET_REG);
-	__raw_writew(0x1F, CPLD_INT_MASK_REG);
-	for (i = MXC_EXP_IO_BASE;
-	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
-	     i++) {
-		set_irq_chip(i, &expio_irq_chip);
-		set_irq_handler(i, handle_level_irq);
-		set_irq_flags(i, IRQF_VALID);
-	}
-	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
-	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
-
-	return 0;
-}
-
-/*
- * This structure defines the MX31 memory map.
- */
-static struct map_desc mx31_3ds_io_desc[] __initdata = {
-	{
-		.virtual = MX31_CS5_BASE_ADDR_VIRT,
-		.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
-		.length = MX31_CS5_SIZE,
-		.type = MT_DEVICE,
-	},
-};
-
-/*
  * Set up static virtual mappings.
  */
 static void __init mx31_3ds_map_io(void)
 {
 	mx31_map_io();
-	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
 }
 
 /*!
@@ -402,8 +240,8 @@ static void __init mxc_board_init(void)
 	mx31_3ds_usbotg_init();
 	mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
 
-	if (!mx31_3ds_init_expio())
-		platform_device_register(&smsc911x_device);
+	if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
+		platform_device_register(&smsc_lan9217_device);
 }
 
 static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
index da92933..c26d88d 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
@@ -12,48 +12,6 @@
 #define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
 
 /* Definitions for components on the Debug board */
-
-/* Base address of CPLD controller on the Debug board */
-#define DEBUG_BASE_ADDRESS		CS5_IO_ADDRESS(CS5_BASE_ADDR)
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR		CS5_BASE_ADDR
-
-/* CPLD config and interrupt base address */
-#define CPLD_ADDR			(DEBUG_BASE_ADDRESS + 0x20000)
-
-/* LED switchs */
-#define CPLD_LED_REG			(CPLD_ADDR + 0x00)
-/* buttons */
-#define CPLD_SWITCH_BUTTONS_REG	(EXPIO_ADDR + 0x08)
-/* status, interrupt */
-#define CPLD_INT_STATUS_REG		(CPLD_ADDR + 0x10)
-#define CPLD_INT_MASK_REG		(CPLD_ADDR + 0x38)
-#define CPLD_INT_RESET_REG		(CPLD_ADDR + 0x20)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER1_REG		(CPLD_ADDR + 0x40)
-#define CPLD_MAGIC_NUMBER2_REG		(CPLD_ADDR + 0x48)
-/* CPLD code version */
-#define CPLD_CODE_VER_REG		(CPLD_ADDR + 0x50)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER3_REG		(CPLD_ADDR + 0x58)
-/* module reset register */
-#define CPLD_MODULE_RESET_REG		(CPLD_ADDR + 0x60)
-/* CPU ID and Personality ID */
-#define CPLD_MCU_BOARD_ID_REG		(CPLD_ADDR + 0x68)
-
-/* CPLD IRQ line for external uart, external ethernet etc */
 #define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
 
-#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_ENET		(MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_XUART_A	(MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_XUART_B	(MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_BUTTON_A	(MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_BUTTON_B	(MXC_EXP_IO_BASE + 4)
-
-#define MXC_MAX_EXP_IO_LINES	16
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
-- 
1.5.6.5



From broonie at opensource.wolfsonmicro.com  Sat Jun 12 13:21:14 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 12 Jun 2010 18:21:14 +0100
Subject: [PATCH 1/3] ISL6271A voltage regulator support.
In-Reply-To: <1276346679-2893-1-git-send-email-marek.vasut@gmail.com>
References: <1276346679-2893-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <20100612172114.GA20610@opensource.wolfsonmicro.com>

On Sat, Jun 12, 2010 at 02:44:37PM +0200, Marek Vasut wrote:
> This device is very simple, it supports only one LDO. This single LDO is
> programmed over I2C to 16 possible voltages.

Google tells me that the device has three regulators on it - two LDOs
and one DCDC buck convertor:

   http://www.intersil.com/products/deviceinfo.asp?pn=ISL6271A

While the LDOs look like they have no software control it'd be best to
provide hookup for them, even if that's just a case of instantiating the
appropriate fixed voltage regulators.

> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

> +/* Supported voltage values for regulators */
> +static const u32 core_buck_table[] = {
> +	 850000,  900000,  950000, 1000000,
> +	1050000, 1100000, 1150000, 1200000,
> +	1250000, 1300000, 1350000, 1400000,
> +	1450000, 1500000, 1550000, 1600000,
> +};

This looks like it could be replaced with a simple function rather than
a lookup table which would simplify the code.

Also, are you sure this is a buck?  That's a specific technical term
usually only applied to DCDC regulators - LDOs are a different type of
regulator 

> +static int __devinit isl6271a_probe(struct i2c_client *client,
> +				     const struct i2c_device_id *id)
> +{
> +	struct regulator_init_data *init_data	= client->dev.platform_data;
> +	struct isl_pmic *pmic;
> +	int err;
> +
> +	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
> +		return -EIO;
> +
> +	if (!init_data)
> +		return -EIO;

It'd be better to print an error message here so users know what's going
on when the device fails to appear.


From broonie at opensource.wolfsonmicro.com  Sat Jun 12 13:21:40 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 12 Jun 2010 18:21:40 +0100
Subject: [PATCH] wm97xx_batt: Remove deprecated method to set pdata
In-Reply-To: <1276347073-3055-1-git-send-email-marek.vasut@gmail.com>
References: <1276347073-3055-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <20100612172140.GB20610@opensource.wolfsonmicro.com>

On Sat, Jun 12, 2010 at 02:51:13PM +0200, Marek Vasut wrote:
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>


From david-b at pacbell.net  Sat Jun 12 13:34:37 2010
From: david-b at pacbell.net (David Brownell)
Date: Sat, 12 Jun 2010 10:34:37 -0700 (PDT)
Subject: [PATCH 1/5] usb/otg/ulpi: extend the generic ulpi driver.
In-Reply-To: <AANLkTimHDBI0grgNrcvZ-BWS9kd0z4lFqEgVoyM4ysVJ@mail.gmail.com>
Message-ID: <73954.66622.qm@web180307.mail.gq1.yahoo.com>



--- On Sat, 6/12/10, Eric Miao <eric.y.miao at gmail.com> wrote:

> From: Eric Miao <eric.y.miao at gmail.com>
> Subject: Re: [PATCH 1/5] usb/otg/ulpi: extend the generic ulpi driver.
> To: "Igor Grinberg" <grinberg at compulab.co.il>


Isn't this patch From: Igor?

It arrived in my mailbox a bit mangled.

A quick scan suggests its OK, but I can't test
or evanulate it just now, e.g. to see if it
breaks anything else, builds, etc.  Plus, I've
not looked at this driver.

Felipe, got any comments?  Is this driver generic
enough that MUSB could use it for ULPI access?



From khc at pm.waw.pl  Sat Jun 12 19:11:07 2010
From: khc at pm.waw.pl (Krzysztof Halasa)
Date: Sun, 13 Jun 2010 01:11:07 +0200
Subject: [PATCH 0/3] Support for three IXP425 based boards
In-Reply-To: <cover.1275415521.git.richard.cochran@omicron.at> (Richard
	Cochran's message of "Wed, 2 Jun 2010 11:55:58 +0200")
References: <cover.1275415521.git.richard.cochran@omicron.at>
Message-ID: <m3y6ej9790.fsf@intrepid.localdomain>

Hi,

Richard Cochran <richardcochran at gmail.com> writes:

> This patch series adds support for three IXP425 based boards from
> OMICRON electronics GmbH. The code has been adapted from the IXDP425
> and the NSLU boards.

Sorry I'm unable to look at the patches at this time. Will do. The other
thing is Linus apparently hasn't pulled the previous portion. It has to
wait for another week+, too.
-- 
Krzysztof Halasa


From benh at kernel.crashing.org  Sat Jun 12 21:10:23 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Sun, 13 Jun 2010 11:10:23 +1000
Subject: [PATCH 1/4] net/phy/marvell: Expose IDs and flags in a .h and add
	dns323 LEDs setup flag
Message-ID: <1276391423.1962.263.camel@pasglop>

This moves the various known Marvell PHY IDs to include/linux/marvell_phy.h
along with dev_flags definitions for use by the driver.

I then added a flag that changes the PHY init code to setup the LEDs
config to the values needed to operate a dns323 rev C1 NAS.

I moved the existing "resistance" flag to the .h as well, though I've
been unable to find whoever sets this to convert it to use that constant.

Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
---
 drivers/net/phy/marvell.c   |   38 ++++++++++++++++++++------------------
 include/linux/marvell_phy.h |   20 ++++++++++++++++++++
 2 files changed, 40 insertions(+), 18 deletions(-)
 create mode 100644 include/linux/marvell_phy.h

diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 78b74e8..5a1bd5d 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -29,6 +29,7 @@
 #include <linux/mii.h>
 #include <linux/ethtool.h>
 #include <linux/phy.h>
+#include <linux/marvell_phy.h>
 
 #include <asm/io.h>
 #include <asm/irq.h>
@@ -48,8 +49,6 @@
 #define MII_M1145_RGMII_RX_DELAY	0x0080
 #define MII_M1145_RGMII_TX_DELAY	0x0002
 
-#define M1145_DEV_FLAGS_RESISTANCE	0x00000001
-
 #define MII_M1111_PHY_LED_CONTROL	0x18
 #define MII_M1111_PHY_LED_DIRECT	0x4100
 #define MII_M1111_PHY_LED_COMBINE	0x411c
@@ -350,7 +349,10 @@ static int m88e1118_config_init(struct phy_device *phydev)
 		return err;
 
 	/* Adjust LED Control */
-	err = phy_write(phydev, 0x10, 0x021e);
+	if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS)
+		err = phy_write(phydev, 0x10, 0x1100);
+	else
+		err = phy_write(phydev, 0x10, 0x021e);
 	if (err < 0)
 		return err;
 
@@ -398,7 +400,7 @@ static int m88e1145_config_init(struct phy_device *phydev)
 		if (err < 0)
 			return err;
 
-		if (phydev->dev_flags & M1145_DEV_FLAGS_RESISTANCE) {
+		if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) {
 			err = phy_write(phydev, 0x1d, 0x0012);
 			if (err < 0)
 				return err;
@@ -529,8 +531,8 @@ static int m88e1121_did_interrupt(struct phy_device *phydev)
 
 static struct phy_driver marvell_drivers[] = {
 	{
-		.phy_id = 0x01410c60,
-		.phy_id_mask = 0xfffffff0,
+		.phy_id = MARVELL_PHY_ID_88E1101,
+		.phy_id_mask = MARVELL_PHY_ID_MASK,
 		.name = "Marvell 88E1101",
 		.features = PHY_GBIT_FEATURES,
 		.flags = PHY_HAS_INTERRUPT,
@@ -541,8 +543,8 @@ static struct phy_driver marvell_drivers[] = {
 		.driver = { .owner = THIS_MODULE },
 	},
 	{
-		.phy_id = 0x01410c90,
-		.phy_id_mask = 0xfffffff0,
+		.phy_id = MARVELL_PHY_ID_88E1112,
+		.phy_id_mask = MARVELL_PHY_ID_MASK,
 		.name = "Marvell 88E1112",
 		.features = PHY_GBIT_FEATURES,
 		.flags = PHY_HAS_INTERRUPT,
@@ -554,8 +556,8 @@ static struct phy_driver marvell_drivers[] = {
 		.driver = { .owner = THIS_MODULE },
 	},
 	{
-		.phy_id = 0x01410cc0,
-		.phy_id_mask = 0xfffffff0,
+		.phy_id = MARVELL_PHY_ID_88E1111,
+		.phy_id_mask = MARVELL_PHY_ID_MASK,
 		.name = "Marvell 88E1111",
 		.features = PHY_GBIT_FEATURES,
 		.flags = PHY_HAS_INTERRUPT,
@@ -567,8 +569,8 @@ static struct phy_driver marvell_drivers[] = {
 		.driver = { .owner = THIS_MODULE },
 	},
 	{
-		.phy_id = 0x01410e10,
-		.phy_id_mask = 0xfffffff0,
+		.phy_id = MARVELL_PHY_ID_88E1118,
+		.phy_id_mask = MARVELL_PHY_ID_MASK,
 		.name = "Marvell 88E1118",
 		.features = PHY_GBIT_FEATURES,
 		.flags = PHY_HAS_INTERRUPT,
@@ -580,8 +582,8 @@ static struct phy_driver marvell_drivers[] = {
 		.driver = {.owner = THIS_MODULE,},
 	},
 	{
-		.phy_id = 0x01410cb0,
-		.phy_id_mask = 0xfffffff0,
+		.phy_id = MARVELL_PHY_ID_88E1121R,
+		.phy_id_mask = MARVELL_PHY_ID_MASK,
 		.name = "Marvell 88E1121R",
 		.features = PHY_GBIT_FEATURES,
 		.flags = PHY_HAS_INTERRUPT,
@@ -593,8 +595,8 @@ static struct phy_driver marvell_drivers[] = {
 		.driver = { .owner = THIS_MODULE },
 	},
 	{
-		.phy_id = 0x01410cd0,
-		.phy_id_mask = 0xfffffff0,
+		.phy_id = MARVELL_PHY_ID_88E1145,
+		.phy_id_mask = MARVELL_PHY_ID_MASK,
 		.name = "Marvell 88E1145",
 		.features = PHY_GBIT_FEATURES,
 		.flags = PHY_HAS_INTERRUPT,
@@ -606,8 +608,8 @@ static struct phy_driver marvell_drivers[] = {
 		.driver = { .owner = THIS_MODULE },
 	},
 	{
-		.phy_id = 0x01410e30,
-		.phy_id_mask = 0xfffffff0,
+		.phy_id = MARVELL_PHY_ID_88E1240,
+		.phy_id_mask = MARVELL_PHY_ID_MASK,
 		.name = "Marvell 88E1240",
 		.features = PHY_GBIT_FEATURES,
 		.flags = PHY_HAS_INTERRUPT,
diff --git a/include/linux/marvell_phy.h b/include/linux/marvell_phy.h
new file mode 100644
index 0000000..2ed4fb8
--- /dev/null
+++ b/include/linux/marvell_phy.h
@@ -0,0 +1,20 @@
+#ifndef _MARVELL_PHY_H
+#define _MARVELL_PHY_H
+
+/* Mask used for ID comparisons */
+#define MARVELL_PHY_ID_MASK		0xfffffff0
+
+/* Known PHY IDs */
+#define MARVELL_PHY_ID_88E1101		0x01410c60
+#define MARVELL_PHY_ID_88E1112		0x01410c90
+#define MARVELL_PHY_ID_88E1111		0x01410cc0
+#define MARVELL_PHY_ID_88E1118		0x01410e10
+#define MARVELL_PHY_ID_88E1121R		0x01410cb0
+#define MARVELL_PHY_ID_88E1145		0x01410cd0
+#define MARVELL_PHY_ID_88E1240		0x01410e30
+
+/* struct phy_device dev_flags definitions */
+#define MARVELL_PHY_M1145_FLAGS_RESISTANCE	0x00000001
+#define MARVELL_PHY_M1118_DNS323_LEDS		0x00000002
+
+#endif /* _MARVELL_PHY_H */




From benh at kernel.crashing.org  Sat Jun 12 21:10:39 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Sun, 13 Jun 2010 11:10:39 +1000
Subject: [PATCH 3/4] arm/orion5x: Fix soft-reset for some platforms
Message-ID: <1276391439.1962.265.camel@pasglop>

Some platforms, such as the DNS-323 rev C requires the soft reset line
to be toggled on and back off for the reset to work.

Note: The choice of 200ms delay comes from the 2.6.12 based vendor kernel.
It seems to be a -lot- though and I had my device working fine with much
smaller delays but better safe...

Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
---
 arch/arm/mach-orion5x/include/mach/system.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-orion5x/include/mach/system.h b/arch/arm/mach-orion5x/include/mach/system.h
index 60e734c..a1d6e46 100644
--- a/arch/arm/mach-orion5x/include/mach/system.h
+++ b/arch/arm/mach-orion5x/include/mach/system.h
@@ -25,6 +25,8 @@ static inline void arch_reset(char mode, const char *cmd)
 	 */
 	orion5x_setbits(RSTOUTn_MASK, (1 << 2));
 	orion5x_setbits(CPU_SOFT_RESET, 1);
+	mdelay(200);
+	orion5x_clrbits(CPU_SOFT_RESET, 1);
 }
 
 




From benh at kernel.crashing.org  Sat Jun 12 21:10:32 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Sun, 13 Jun 2010 11:10:32 +1000
Subject: [PATCH 2/4] arm/orion5x: Base support for DNS-323 rev C1
Message-ID: <1276391432.1962.264.camel@pasglop>

This patch adds the base support for this new HW revision to the existing
dns323-setup.c file. The SoC seems to be the same as rev B1, the GPIOs
are all wired differently though and the fan control isn't i2c based
anymore.

Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
---
 arch/arm/mach-orion5x/dns323-setup.c |  367 ++++++++++++++++++++++++++++------
 1 files changed, 305 insertions(+), 62 deletions(-)

diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index fe0de16..7a2bb94 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -3,6 +3,10 @@
  *
  * Copyright (C) 2007 Herbert Valerio Riedel <hvr at gnu.org>
  *
+ * Support for HW Rev C1:
+ *
+ * Copyright (C) 2010 Benjamin Herrenschmidt <benh at kernel.crashing.org>
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU Lesser General Public License as
  * published by the Free Software Foundation; either version 2 of the
@@ -23,6 +27,8 @@
 #include <linux/input.h>
 #include <linux/i2c.h>
 #include <linux/ata_platform.h>
+#include <linux/phy.h>
+#include <linux/marvell_phy.h>
 #include <asm/mach-types.h>
 #include <asm/gpio.h>
 #include <asm/mach/arch.h>
@@ -31,6 +37,7 @@
 #include "common.h"
 #include "mpp.h"
 
+/* Rev A1 and B1 */
 #define DNS323_GPIO_LED_RIGHT_AMBER	1
 #define DNS323_GPIO_LED_LEFT_AMBER	2
 #define DNS323_GPIO_SYSTEM_UP		3
@@ -42,6 +49,23 @@
 #define DNS323_GPIO_KEY_POWER		9
 #define DNS323_GPIO_KEY_RESET		10
 
+/* Rev C1 */
+#define DNS323C_GPIO_KEY_POWER		1
+#define DNS323C_GPIO_POWER_OFF		2
+#define DNS323C_GPIO_LED_RIGHT_AMBER	8
+#define DNS323C_GPIO_LED_LEFT_AMBER	9
+#define DNS323C_GPIO_LED_POWER		17
+#define DNS323C_GPIO_FAN_BIT1		18
+#define DNS323C_GPIO_FAN_BIT0		19
+
+/* Exposed to userspace, do not change */
+enum {
+	DNS323_REV_A1,	/* 0 */
+	DNS323_REV_B1,	/* 1 */
+	DNS323_REV_C1,	/* 2 */
+};
+
+
 /****************************************************************************
  * PCI setup
  */
@@ -68,21 +92,12 @@ static struct hw_pci dns323_pci __initdata = {
 	.map_irq	= dns323_pci_map_irq,
 };
 
-static int __init dns323_dev_id(void)
-{
-	u32 dev, rev;
-
-	orion5x_pcie_id(&dev, &rev);
-
-	return dev;
-}
-
 static int __init dns323_pci_init(void)
 {
-	/* The 5182 doesn't really use its PCI bus, and initialising PCI
+	/* Rev B1 and C1 doesn't really use its PCI bus, and initialising PCI
 	 * gets in the way of initialising the SATA controller.
 	 */
-	if (machine_is_dns323() && dns323_dev_id() != MV88F5182_DEV_ID)
+	if (machine_is_dns323() && system_rev == DNS323_REV_A1)
 		pci_common_init(&dns323_pci);
 
 	return 0;
@@ -221,7 +236,7 @@ static int __init dns323_read_mac_addr(void)
 	}
 
 	iounmap(mac_page);
-	printk("DNS323: Found ethernet MAC address: ");
+	printk("DNS-323: Found ethernet MAC address: ");
 	for (i = 0; i < 6; i++)
 		printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
 
@@ -259,7 +274,7 @@ static int dns323_gpio_blink_set(unsigned gpio, int state,
 	return 0;
 }
 
-static struct gpio_led dns323_leds[] = {
+static struct gpio_led dns323ab_leds[] = {
 	{
 		.name = "power:blue",
 		.gpio = DNS323_GPIO_LED_POWER2,
@@ -276,9 +291,34 @@ static struct gpio_led dns323_leds[] = {
 	},
 };
 
-static struct gpio_led_platform_data dns323_led_data = {
-	.num_leds	= ARRAY_SIZE(dns323_leds),
-	.leds		= dns323_leds,
+
+static struct gpio_led dns323c_leds[] = {
+	{
+		.name = "power:blue",
+		.gpio = DNS323C_GPIO_LED_POWER,
+		.default_trigger = "timer",
+		.active_low = 1,
+	}, {
+		.name = "right:amber",
+		.gpio = DNS323C_GPIO_LED_RIGHT_AMBER,
+		.active_low = 1,
+	}, {
+		.name = "left:amber",
+		.gpio = DNS323C_GPIO_LED_LEFT_AMBER,
+		.active_low = 1,
+	},
+};
+
+
+static struct gpio_led_platform_data dns323ab_led_data = {
+	.num_leds	= ARRAY_SIZE(dns323ab_leds),
+	.leds		= dns323ab_leds,
+	.gpio_blink_set = dns323_gpio_blink_set,
+};
+
+static struct gpio_led_platform_data dns323c_led_data = {
+	.num_leds	= ARRAY_SIZE(dns323c_leds),
+	.leds		= dns323c_leds,
 	.gpio_blink_set = dns323_gpio_blink_set,
 };
 
@@ -286,7 +326,7 @@ static struct platform_device dns323_gpio_leds = {
 	.name		= "leds-gpio",
 	.id		= -1,
 	.dev		= {
-		.platform_data	= &dns323_led_data,
+		.platform_data	= &dns323ab_led_data,
 	},
 };
 
@@ -294,7 +334,7 @@ static struct platform_device dns323_gpio_leds = {
  * GPIO Attached Keys
  */
 
-static struct gpio_keys_button dns323_buttons[] = {
+static struct gpio_keys_button dns323ab_buttons[] = {
 	{
 		.code		= KEY_RESTART,
 		.gpio		= DNS323_GPIO_KEY_RESET,
@@ -308,9 +348,23 @@ static struct gpio_keys_button dns323_buttons[] = {
 	},
 };
 
-static struct gpio_keys_platform_data dns323_button_data = {
-	.buttons	= dns323_buttons,
-	.nbuttons	= ARRAY_SIZE(dns323_buttons),
+static struct gpio_keys_platform_data dns323ab_button_data = {
+	.buttons	= dns323ab_buttons,
+	.nbuttons	= ARRAY_SIZE(dns323ab_buttons),
+};
+
+static struct gpio_keys_button dns323c_buttons[] = {
+	{
+		.code		= KEY_POWER,
+		.gpio		= DNS323C_GPIO_KEY_POWER,
+		.desc		= "Power Button",
+		.active_low	= 1,
+	},
+};
+
+static struct gpio_keys_platform_data dns323c_button_data = {
+	.buttons	= dns323c_buttons,
+	.nbuttons	= ARRAY_SIZE(dns323c_buttons),
 };
 
 static struct platform_device dns323_button_device = {
@@ -318,7 +372,7 @@ static struct platform_device dns323_button_device = {
 	.id		= -1,
 	.num_resources	= 0,
 	.dev		= {
-		.platform_data	= &dns323_button_data,
+		.platform_data	= &dns323ab_button_data,
 	},
 };
 
@@ -332,7 +386,7 @@ static struct mv_sata_platform_data dns323_sata_data = {
 /****************************************************************************
  * General Setup
  */
-static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
+static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = {
 	{  0, MPP_PCIE_RST_OUTn },
 	{  1, MPP_GPIO },		/* right amber LED (sata ch0) */
 	{  2, MPP_GPIO },		/* left amber LED (sata ch1) */
@@ -356,7 +410,7 @@ static struct orion5x_mpp_mode dns323_mv88f5181_mpp_modes[] __initdata = {
 	{ -1 },
 };
 
-static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
+static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = {
 	{  0, MPP_UNUSED },
 	{  1, MPP_GPIO },		/* right amber LED (sata ch0) */
 	{  2, MPP_GPIO },		/* left amber LED (sata ch1) */
@@ -380,15 +434,57 @@ static struct orion5x_mpp_mode dns323_mv88f5182_mpp_modes[] __initdata = {
 	{ -1 },
 };
 
+static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = {
+	{  0, MPP_GPIO },		/* ? input */
+	{  1, MPP_GPIO },		/* input power switch (0 = pressed) */
+	{  2, MPP_GPIO },		/* output power off */
+	{  3, MPP_UNUSED },		/* ? output */
+	{  4, MPP_UNUSED },		/* ? output */
+	{  5, MPP_UNUSED },		/* ? output */
+	{  6, MPP_UNUSED },		/* ? output */
+	{  7, MPP_UNUSED },		/* ? output */
+	{  8, MPP_GPIO },		/* i/o right amber LED */
+	{  9, MPP_GPIO },		/* i/o left amber LED */
+	{ 10, MPP_GPIO },		/* input */
+	{ 11, MPP_UNUSED },
+	{ 12, MPP_SATA_LED },
+	{ 13, MPP_SATA_LED },
+	{ 14, MPP_SATA_LED },
+	{ 15, MPP_SATA_LED },
+	{ 16, MPP_UNUSED },
+	{ 17, MPP_GPIO },		/* power button LED */
+	{ 18, MPP_GPIO },		/* fan speed bit 0 */
+	{ 19, MPP_GPIO },		/* fan speed bit 1 */
+	{ -1 },
+};
+
+/* Rev C1 Fan speed notes:
+ *
+ * The fan is controlled by 2 GPIOs on this board. The settings
+ * of the bits is as follow:
+ *
+ *  GPIO 18    GPIO 19    Fan
+ *
+ *    0          0        stopped
+ *    0          1        low speed
+ *    1          0        high speed
+ *    1          1        don't do that (*)
+ *
+ * (*) I think the two bits control two feed-in resistors into a fixed
+ *     PWN circuit, setting both bits will basically go a 'bit' faster
+ *     than high speed, but d-link doesn't do it and you may get out of
+ *     HW spec so don't do it.
+ */
+
 /*
- * On the DNS-323 the following devices are attached via I2C:
+ * On the DNS-323 A1 and B1 the following devices are attached via I2C:
  *
  *  i2c addr | chip        | description
  *  0x3e     | GMT G760Af  | fan speed PWM controller
  *  0x48     | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
  *  0x68     | ST M41T80   | RTC w/ alarm
  */
-static struct i2c_board_info __initdata dns323_i2c_devices[] = {
+static struct i2c_board_info __initdata dns323ab_i2c_devices[] = {
 	{
 		I2C_BOARD_INFO("g760a", 0x3e),
 	}, {
@@ -398,36 +494,140 @@ static struct i2c_board_info __initdata dns323_i2c_devices[] = {
 	},
 };
 
+/*
+ * On the DNS-323 C1 the following devices are attached via I2C:
+ *
+ *  i2c addr | chip        | description
+ *  0x48     | GMT G751-2f | temp. sensor and therm. watchdog (LM75 compatible)
+ *  0x68     | ST M41T80   | RTC w/ alarm
+ */
+static struct i2c_board_info __initdata dns323c_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("lm75", 0x48),
+	}, {
+		I2C_BOARD_INFO("m41t80", 0x68),
+	},
+};
+
 /* DNS-323 rev. A specific power off method */
 static void dns323a_power_off(void)
 {
-	pr_info("%s: triggering power-off...\n", __func__);
+	pr_info("DNS-323: Triggering power-off...\n");
 	gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
 }
 
 /* DNS-323 rev B specific power off method */
 static void dns323b_power_off(void)
 {
-	pr_info("%s: triggering power-off...\n", __func__);
+	pr_info("DNS-323: Triggering power-off...\n");
 	/* Pin has to be changed to 1 and back to 0 to do actual power off. */
 	gpio_set_value(DNS323_GPIO_POWER_OFF, 1);
 	mdelay(100);
 	gpio_set_value(DNS323_GPIO_POWER_OFF, 0);
 }
 
+/* DNS-323 rev. C specific power off method */
+static void dns323c_power_off(void)
+{
+	pr_info("DNS-323: Triggering power-off...\n");
+	gpio_set_value(DNS323C_GPIO_POWER_OFF, 1);
+}
+
+static int dns323c_phy_fixup(struct phy_device *phy)
+{
+	phy->dev_flags |= MARVELL_PHY_M1118_DNS323_LEDS;
+
+	return 0;
+}
+
+static int __init dns323_identify_rev(void)
+{
+	u32 dev, rev, i, reg;
+
+	pr_debug("DNS-323: Identifying board ... \n");
+
+	/* Rev A1 has a 5181 */
+	orion5x_pcie_id(&dev, &rev);
+	if (dev == MV88F5181_DEV_ID) {
+		pr_debug("DNS-323: 5181 found, board is A1\n");
+		return DNS323_REV_A1;
+	}
+	pr_debug("DNS-323: 5182 found, board is B1 or C1, checking PHY...\n");
+
+	/* Rev B1 and C1 both have 5182, let's poke at the eth PHY. This is
+	 * a bit gross but we want to do that without links into the eth
+	 * driver so let's poke at it directly. We default to rev B1 in
+	 * case the accesses fail
+	 */
+
+#define ETH_SMI_REG		(ORION5X_ETH_VIRT_BASE + 0x2000 + 0x004)
+#define  SMI_BUSY		0x10000000
+#define  SMI_READ_VALID		0x08000000
+#define  SMI_OPCODE_READ	0x04000000
+#define  SMI_OPCODE_WRITE	0x00000000
+
+	for (i = 0; i < 1000; i++) {
+		reg = readl(ETH_SMI_REG);
+		if (!(reg & SMI_BUSY))
+			break;
+	}
+	if (i >= 1000) {
+		pr_warning("DNS-323: Timeout accessing PHY, assuming rev B1\n");
+		return DNS323_REV_B1;
+	}
+	writel((3 << 21)	/* phy ID reg */ |
+	       (8 << 16)	/* phy addr */ |
+	       SMI_OPCODE_READ, ETH_SMI_REG);
+	for (i = 0; i < 1000; i++) {
+		reg = readl(ETH_SMI_REG);
+		if (reg & SMI_READ_VALID)
+			break;
+	}
+	if (i >= 1000) {
+		pr_warning("DNS-323: Timeout reading PHY, assuming rev B1\n");
+		return DNS323_REV_B1;
+	}
+	pr_debug("DNS-323: Ethernet PHY ID 0x%x\n", reg & 0xffff);
+
+	/* Note: the Marvell tools mask the ID with 0x3f0 before comparison
+	 * but I don't see that making a difference here, at least with
+	 * any known Marvell PHY ID
+	 */
+	switch(reg & 0xfff0) {
+	case 0x0cc0: /* MV88E1111 */
+		return DNS323_REV_B1;
+	case 0x0e10: /* MV88E1118 */
+		return DNS323_REV_C1;
+	default:
+		pr_warning("DNS-323: Unknown PHY ID 0x%04x, assuming rev B1\n",
+			   reg & 0xffff);
+	}
+	return DNS323_REV_B1;
+}
+
 static void __init dns323_init(void)
 {
 	/* Setup basic Orion functions. Need to be called early. */
 	orion5x_init();
 
+	/* Identify revision */
+	system_rev = dns323_identify_rev();
+	pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev);
+
 	/* Just to be tricky, the 5182 has a completely different
 	 * set of MPP modes to the 5181.
 	 */
-	if (dns323_dev_id() == MV88F5182_DEV_ID)
-		orion5x_mpp_conf(dns323_mv88f5182_mpp_modes);
-	else {
-		orion5x_mpp_conf(dns323_mv88f5181_mpp_modes);
+	switch(system_rev) {
+	case DNS323_REV_A1:
+		orion5x_mpp_conf(dns323a_mpp_modes);
 		writel(0, MPP_DEV_CTRL);		/* DEV_D[31:16] */
+		break;
+	case DNS323_REV_B1:
+		orion5x_mpp_conf(dns323b_mpp_modes);
+		break;
+	case DNS323_REV_C1:
+		orion5x_mpp_conf(dns323c_mpp_modes);
+		break;
 	}
 
 	/* setup flash mapping
@@ -436,53 +636,96 @@ static void __init dns323_init(void)
 	orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
 	platform_device_register(&dns323_nor_flash);
 
-	/* The 5181 power LED is active low and requires
-	 * DNS323_GPIO_LED_POWER1 to also be low.
-	 */
-	if (dns323_dev_id() == MV88F5181_DEV_ID) {
-		dns323_leds[0].active_low = 1;
-		gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
-		gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
+	/* Sort out LEDs, Buttons and i2c devices */
+	switch(system_rev) {
+	case DNS323_REV_A1:
+		/* The 5181 power LED is active low and requires
+		 * DNS323_GPIO_LED_POWER1 to also be low.
+		 */
+		 dns323ab_leds[0].active_low = 1;
+		 gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
+		 gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
+		/* Fall through */
+	case DNS323_REV_B1:
+		i2c_register_board_info(0, dns323ab_i2c_devices,
+				ARRAY_SIZE(dns323ab_i2c_devices));
+		break;
+	case DNS323_REV_C1:
+		/* Hookup LEDs & Buttons */
+		dns323_gpio_leds.dev.platform_data = &dns323c_led_data;
+		dns323_button_device.dev.platform_data = &dns323c_button_data;
+
+		/* Hookup i2c devices and fan driver */
+		i2c_register_board_info(0, dns323c_i2c_devices,
+				ARRAY_SIZE(dns323c_i2c_devices));
+		platform_device_register_simple("dns323c-fan", 0, NULL, 0);
+
+		/* Register fixup for the PHY LEDs */
+		phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
+					   MARVELL_PHY_ID_MASK,
+					   dns323c_phy_fixup);
 	}
 
 	platform_device_register(&dns323_gpio_leds);
-
 	platform_device_register(&dns323_button_device);
 
-	i2c_register_board_info(0, dns323_i2c_devices,
-				ARRAY_SIZE(dns323_i2c_devices));
-
 	/*
 	 * Configure peripherals.
 	 */
 	if (dns323_read_mac_addr() < 0)
-		printk("DNS323: Failed to read MAC address\n");
-
+		printk("DNS-323: Failed to read MAC address\n");
 	orion5x_ehci0_init();
 	orion5x_eth_init(&dns323_eth_data);
 	orion5x_i2c_init();
 	orion5x_uart0_init();
 
-	/* The 5182 has its SATA controller on-chip, and needs its own little
-	 * init routine.
-	 */
-	if (dns323_dev_id() == MV88F5182_DEV_ID)
+	/* Remaining GPIOs */
+	switch(system_rev) {
+	case DNS323_REV_A1:
+		/* Poweroff GPIO */
+		if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+		    gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
+			pr_err("DNS-323: failed to setup power-off GPIO\n");
+		pm_power_off = dns323a_power_off;
+		break;
+	case DNS323_REV_B1:
+		/* 5182 built-in SATA init */
 		orion5x_sata_init(&dns323_sata_data);
 
-	/* The 5182 has flag to indicate the system is up. Without this flag
-	 * set, power LED will flash and cannot be controlled via leds-gpio.
-	 */
-	if (dns323_dev_id() == MV88F5182_DEV_ID)
-		gpio_set_value(DNS323_GPIO_SYSTEM_UP, 1);
-
-	/* Register dns323 specific power-off method */
-	if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
-	    gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
-		pr_err("DNS323: failed to setup power-off GPIO\n");
-	if (dns323_dev_id() == MV88F5182_DEV_ID)
+		/* The DNS323 rev B1 has flag to indicate the system is up.
+		 * Without this flag set, power LED will flash and cannot be
+		 * controlled via leds-gpio.
+		 */
+		if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0)
+			gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1);
+
+		/* Poweroff GPIO */
+		if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+		    gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
+			pr_err("DNS-323: failed to setup power-off GPIO\n");
 		pm_power_off = dns323b_power_off;
-	else
-		pm_power_off = dns323a_power_off;
+		break;
+	case DNS323_REV_C1:
+		/* 5182 built-in SATA init */
+		orion5x_sata_init(&dns323_sata_data);
+
+		/* Poweroff GPIO */
+		if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 ||
+		    gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0)
+			pr_err("DNS-323: failed to setup power-off GPIO\n");
+		pm_power_off = dns323c_power_off;
+
+		/* Now, -this- should theorically be done by the sata_mv driver
+		 * once I figure out what's going on there. Maybe the behaviour
+		 * of the LEDs should be somewhat passed via the platform_data.
+		 * for now, just whack the register and make the LEDs happy
+		 *
+		 * Note: AFAIK, rev B1 needs the same treatement but I'll let
+		 * somebody else test it.
+		 */
+		writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
+		break;
+	}
 }
 
 /* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */




From benh at kernel.crashing.org  Sat Jun 12 21:10:43 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Sun, 13 Jun 2010 11:10:43 +1000
Subject: [PATCH 4/4] hwmon: DNS323 rev C1 fan support
Message-ID: <1276391443.1962.268.camel@pasglop>

The hardware only supports 3 settings: off, slow and fast.

In order to have a chance to work with existing fan control systems,
we emulate a PWM device with the following mapping:

   0.. 15  off		0 RPM input
  16..127  slow	      400 RPM input
 128..255  fast      2000 RPM input

This provides something more/less working with fancontrol, though
it does have a tendency to work by doing short bursts of "slow"
speed every half a minute as it settles around my min temp. Not
a big deal a specialized script could probably do better, or even
tweaks to fancontrol config. At leats it should be safe, and appears
to work well enough for me with fancontrol.

Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
CC: lm-sensors at lm-sensors.org
---
 drivers/hwmon/Kconfig       |   12 ++
 drivers/hwmon/Makefile      |    1 +
 drivers/hwmon/dns323c-fan.c |  271 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 284 insertions(+), 0 deletions(-)
 create mode 100644 drivers/hwmon/dns323c-fan.c

diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index e19cf8e..953608a 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1118,6 +1118,18 @@ config SENSORS_MC13783_ADC
         help
           Support for the A/D converter on MC13783 PMIC.
 
+config SENSORS_DNS323C_FAN
+       tristate "D-Link DNS323 rev C1 Fan"
+       depends on MACH_DNS323
+       help
+         Support for the GPIO based fan control on the D-Link DNS323
+	 HW revision C1. This exposes a pseudo pwm device with the
+	 following values supported:
+
+	 	    0..15	: Fan off
+		   16..127	: Fan on low speed
+		  128..255	: Fan on high speed
+	 
 if ACPI
 
 comment "ACPI drivers"
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 2138ceb..98a1fcd 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -103,6 +103,7 @@ obj-$(CONFIG_SENSORS_W83L785TS)	+= w83l785ts.o
 obj-$(CONFIG_SENSORS_W83L786NG)	+= w83l786ng.o
 obj-$(CONFIG_SENSORS_WM831X)	+= wm831x-hwmon.o
 obj-$(CONFIG_SENSORS_WM8350)	+= wm8350-hwmon.o
+obj-$(CONFIG_SENSORS_DNS323C_FAN)+= dns323c-fan.o
 
 ifeq ($(CONFIG_HWMON_DEBUG_CHIP),y)
 EXTRA_CFLAGS += -DDEBUG
diff --git a/drivers/hwmon/dns323c-fan.c b/drivers/hwmon/dns323c-fan.c
new file mode 100644
index 0000000..4ae18d0
--- /dev/null
+++ b/drivers/hwmon/dns323c-fan.c
@@ -0,0 +1,271 @@
+/*
+ *  dns323c_fan - Driver for the D-LINK DNS-323 rev C1 fan control
+ *
+ *  Copyright 2010 Benjamin Herrenschmidt
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/hwmon.h>
+
+#include <linux/hwmon-sysfs.h>
+#include <linux/gfp.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/sysfs.h>
+#include <linux/platform_device.h>
+
+enum fan_speed {
+	FAN_OFF,
+	FAN_LOW	,
+	FAN_FAST,
+	FAN_FAST_LOCK,
+};
+
+#define DNS323C_GPIO_FAN_BIT1		18
+#define DNS323C_GPIO_FAN_BIT0		19
+
+struct dns323c_fan {
+	struct device	*hwmon;
+	struct mutex	lock;
+	enum fan_speed	speed;
+};
+
+static void __set_fan_speed(struct dns323c_fan *fan, enum fan_speed speed)
+{
+	if (speed == fan->speed)
+		return;
+
+	switch(speed) {
+	case FAN_OFF:
+		gpio_set_value(DNS323C_GPIO_FAN_BIT1, 0);
+		gpio_set_value(DNS323C_GPIO_FAN_BIT0, 0);
+		break;
+	case FAN_LOW:
+		gpio_set_value(DNS323C_GPIO_FAN_BIT1, 0);
+		gpio_set_value(DNS323C_GPIO_FAN_BIT0, 1);
+		break;
+	default:
+		gpio_set_value(DNS323C_GPIO_FAN_BIT0, 0);
+		gpio_set_value(DNS323C_GPIO_FAN_BIT1, 1);
+	};
+	fan->speed = speed;
+}
+
+static ssize_t show_name(struct device *dev, struct device_attribute *da,
+			   char *buf)
+{
+	return sprintf(buf, "dns323c-fan\n");
+}
+
+static ssize_t show_pwm(struct device *dev, struct device_attribute *da,
+			char *buf)
+{
+	struct dns323c_fan *fan = dev_get_drvdata(dev);
+	int pseudo_pwm;
+
+	switch(fan->speed) {
+	case FAN_OFF:
+		pseudo_pwm = 0;
+		break;
+	case FAN_LOW:
+		pseudo_pwm = 63;
+		break;
+	default:
+		pseudo_pwm = 255;
+	}
+	return sprintf(buf, "%d\n", pseudo_pwm);
+}
+
+static ssize_t set_pwm(struct device *dev, struct device_attribute *da,
+		       const char *buf, size_t count)
+{
+	struct dns323c_fan *fan = dev_get_drvdata(dev);
+	enum fan_speed speed;
+	unsigned long val;
+
+	if (strict_strtoul(buf, 10, &val))
+		return -EINVAL;
+	if (fan->speed == FAN_FAST_LOCK)
+		return count;
+
+	mutex_lock(&fan->lock);
+	if (val < 16)
+		speed = FAN_OFF;
+	else if (val < 128)
+		speed = FAN_LOW;
+	else
+		speed = FAN_FAST;
+	__set_fan_speed(fan, speed);
+	mutex_unlock(&fan->lock);
+
+	return count;
+}
+
+static ssize_t show_pwm_en(struct device *dev, struct device_attribute *da,
+			   char *buf)
+{
+	struct dns323c_fan *fan = dev_get_drvdata(dev);
+
+	if (fan->speed == FAN_FAST_LOCK)
+		return sprintf(buf, "0\n");
+	else
+		return sprintf(buf, "1\n");
+}
+
+static ssize_t set_pwm_en(struct device *dev, struct device_attribute *da,
+			  const char *buf, size_t count)
+{
+	struct dns323c_fan *fan = dev_get_drvdata(dev);
+	enum fan_speed speed;
+	unsigned long val;
+
+	if (strict_strtoul(buf, 10, &val))
+		return -EINVAL;
+	if (val != 0 && val != 1)
+		return -EINVAL;
+
+	mutex_lock(&fan->lock);
+	if (val == 0 && fan->speed != FAN_FAST_LOCK)
+		speed = FAN_FAST_LOCK;
+	else if (val != 0 && fan->speed == FAN_FAST_LOCK)
+		speed = FAN_FAST;
+	else
+		speed = fan->speed;
+	__set_fan_speed(fan, speed);
+	mutex_unlock(&fan->lock);
+
+	return count;
+}
+
+static ssize_t show_fake_rpm(struct device *dev, struct device_attribute *da,
+			     char *buf)
+{
+	struct dns323c_fan *fan = dev_get_drvdata(dev);
+	int pseudo_rpm;
+
+	switch(fan->speed) {
+	case FAN_OFF:
+		pseudo_rpm = 0;
+		break;
+	case FAN_LOW:
+		pseudo_rpm = 400;
+		break;
+	default:
+		pseudo_rpm = 2000;
+	}
+	return sprintf(buf, "%d\n", pseudo_rpm);
+}
+
+static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
+static DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm);
+static DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, show_pwm_en, set_pwm_en);
+static DEVICE_ATTR(fan1_input, S_IRUGO, show_fake_rpm, NULL);
+
+static int dns323c_fan_probe(struct platform_device *pdev)
+{
+	struct dns323c_fan *fan = NULL;
+	int ret = -ENXIO;
+
+	/* Get the GPIOs */
+	if (gpio_request(DNS323C_GPIO_FAN_BIT0, "FAN0") != 0) {
+		pr_err("dns323c_fan: Failed to request fan GPIO 0 !\n");
+		return -ENXIO;
+	}
+	if (gpio_request(DNS323C_GPIO_FAN_BIT1, "FAN1") != 0) {
+		pr_err("dns323c_fan: Failed to request fan GPIO 1 !\n");
+		goto err_gpio;
+	}
+
+	/* Set directions to output and medium speed. We write bit 1 first
+	 * since it contains 0 to avoid having a transitory 11 state which
+	 * isn't supported
+	 */
+	gpio_direction_output(DNS323C_GPIO_FAN_BIT1, 0);
+	gpio_direction_output(DNS323C_GPIO_FAN_BIT0, 1);
+
+	/* Grab some memory for our state */
+	fan = kzalloc(sizeof(struct dns323c_fan), GFP_KERNEL);
+	if (!fan) {
+		ret = -ENOMEM;
+		goto err_alloc;
+	}
+	fan->speed = FAN_LOW;
+	mutex_init(&fan->lock);
+	platform_set_drvdata(pdev, fan);
+
+	ret = device_create_file(&pdev->dev, &dev_attr_name);
+	ret |= device_create_file(&pdev->dev, &dev_attr_pwm1);
+	ret |= device_create_file(&pdev->dev, &dev_attr_pwm1_enable);
+	ret |= device_create_file(&pdev->dev, &dev_attr_fan1_input);
+	if (ret)
+		goto err_file;
+
+	fan->hwmon = hwmon_device_register(&pdev->dev);
+	if (IS_ERR(fan->hwmon)) {
+		ret = PTR_ERR(fan->hwmon);
+		goto err_dev;
+	}
+	return 0;
+
+ err_dev:
+	device_remove_file(&pdev->dev, &dev_attr_name);
+	device_remove_file(&pdev->dev, &dev_attr_pwm1);
+	device_remove_file(&pdev->dev, &dev_attr_pwm1_enable);
+	device_remove_file(&pdev->dev, &dev_attr_fan1_input);
+ err_file:
+	kfree(fan);
+ err_alloc:
+	gpio_free(DNS323C_GPIO_FAN_BIT1);
+ err_gpio:
+	gpio_free(DNS323C_GPIO_FAN_BIT0);
+	return ret;
+}
+
+static int __devexit dns323c_fan_remove(struct platform_device *pdev)
+{
+	struct dns323c_fan *fan = platform_get_drvdata(pdev);
+
+	hwmon_device_unregister(fan->hwmon);
+	device_remove_file(&pdev->dev, &dev_attr_name);
+	device_remove_file(&pdev->dev, &dev_attr_pwm1);
+	device_remove_file(&pdev->dev, &dev_attr_pwm1_enable);
+	device_remove_file(&pdev->dev, &dev_attr_fan1_input);
+	kfree(fan);
+	gpio_free(DNS323C_GPIO_FAN_BIT1);
+	gpio_free(DNS323C_GPIO_FAN_BIT0);
+	return 0;
+}
+
+static struct platform_driver dns323c_fan_driver = {
+	.probe = dns323c_fan_probe,
+	.remove = __devexit_p(dns323c_fan_remove),
+	.driver = {
+		.name = "dns323c-fan",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init dns323c_fan_init(void)
+{
+	return platform_driver_register(&dns323c_fan_driver);
+}
+
+static void __exit dns323c_fan_exit(void)
+{
+	platform_driver_unregister(&dns323c_fan_driver);
+}
+
+MODULE_AUTHOR("Benjamin Herrenschmidt <benh at kernel.crashing.org>");
+MODULE_DESCRIPTION("DNS323 RevC1 Fan control");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:dns323c-fan");
+
+module_init(dns323c_fan_init);
+module_exit(dns323c_fan_exit);




From eric.y.miao at gmail.com  Sat Jun 12 22:33:11 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sun, 13 Jun 2010 10:33:11 +0800
Subject: [PATCH] wm97xx_batt: Remove deprecated method to set pdata
In-Reply-To: <20100612172140.GB20610@opensource.wolfsonmicro.com>
References: <1276347073-3055-1-git-send-email-marek.vasut@gmail.com> 
	<20100612172140.GB20610@opensource.wolfsonmicro.com>
Message-ID: <AANLkTikhclymsEo5jyS3Zi3bzRimgoYU1GWNNErtFVEi@mail.gmail.com>

On Sun, Jun 13, 2010 at 1:21 AM, Mark Brown
<broonie at opensource.wolfsonmicro.com> wrote:
> On Sat, Jun 12, 2010 at 02:51:13PM +0200, Marek Vasut wrote:
>> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
>
> Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
>

Thanks. Applied.


From ben-linux at fluff.org  Sun Jun 13 01:16:26 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Sun, 13 Jun 2010 06:16:26 +0100
Subject: [PATCH] ARM: Add ARCH_HAS_L2X0 and make CACHE_L2X0 config
	depend on that
In-Reply-To: <1276279087.31800.6.camel@c-dwalke-linux.qualcomm.com>
References: <1276272211-13065-1-git-send-email-olof@lixom.net>
	<1276279087.31800.6.camel@c-dwalke-linux.qualcomm.com>
Message-ID: <20100613051625.GA7248@trinity.fluff.org>

On Fri, Jun 11, 2010 at 10:58:07AM -0700, Daniel Walker wrote:
> On Fri, 2010-06-11 at 11:03 -0500, Olof Johansson wrote:
> 
> > diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> > index 346ae14..419b957 100644
> > --- a/arch/arm/mm/Kconfig
> > +++ b/arch/arm/mm/Kconfig
> > @@ -759,11 +759,13 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
> >  	  Say Y here to use the Feroceon L2 cache in writethrough mode.
> >  	  Unless you specifically require this, say N for writeback mode.
> >  
> > +config ARCH_HAS_L2X0
> > +	bool
> > +	default n
> > +
> 
> I made a similar change not too long ago, but Russell wanted the define
> to be HAVE_CACHE_L2X0 ..

possibly, I was thinking ARM_L2X0 would also be an option, since if I
remeber correctly it is selecting the driver not the availability of
it.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From w.sang at pengutronix.de  Sun Jun 13 01:28:31 2010
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Sun, 13 Jun 2010 07:28:31 +0200
Subject: [PATCH 1/4] net/phy/marvell: Expose IDs and flags in a .h and
	add dns323 LEDs setup flag
In-Reply-To: <1276391423.1962.263.camel@pasglop>
References: <1276391423.1962.263.camel@pasglop>
Message-ID: <20100613052831.GA17012@pengutronix.de>

On Sun, Jun 13, 2010 at 11:10:23AM +1000, Benjamin Herrenschmidt wrote:
> This moves the various known Marvell PHY IDs to include/linux/marvell_phy.h
> along with dev_flags definitions for use by the driver.
> 
> I then added a flag that changes the PHY init code to setup the LEDs
> config to the values needed to operate a dns323 rev C1 NAS.
> 
> I moved the existing "resistance" flag to the .h as well, though I've
> been unable to find whoever sets this to convert it to use that constant.
> 
> Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>

That should do for now.

Reviewed-by: Wolfram Sang <w.sang at pengutronix.de>

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From benh at kernel.crashing.org  Sun Jun 13 02:02:35 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Sun, 13 Jun 2010 16:02:35 +1000
Subject: [PATCH 1/4] net/phy/marvell: Expose IDs and flags in a .h and
	add dns323 LEDs setup flag
In-Reply-To: <20100613052831.GA17012@pengutronix.de>
References: <1276391423.1962.263.camel@pasglop>
	<20100613052831.GA17012@pengutronix.de>
Message-ID: <1276408955.1962.578.camel@pasglop>

On Sun, 2010-06-13 at 07:28 +0200, Wolfram Sang wrote:
> On Sun, Jun 13, 2010 at 11:10:23AM +1000, Benjamin Herrenschmidt wrote:
> > This moves the various known Marvell PHY IDs to include/linux/marvell_phy.h
> > along with dev_flags definitions for use by the driver.
> > 
> > I then added a flag that changes the PHY init code to setup the LEDs
> > config to the values needed to operate a dns323 rev C1 NAS.
> > 
> > I moved the existing "resistance" flag to the .h as well, though I've
> > been unable to find whoever sets this to convert it to use that constant.
> > 
> > Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
> 
> That should do for now.
> 
> Reviewed-by: Wolfram Sang <w.sang at pengutronix.de>

Thanks.

Dave, any objection to having that go via the arm tree along with the
rest of my patches to support the dns323 since they depend on this one ?

Cheers,
Ben.




From marek.vasut at gmail.com  Sun Jun 13 02:50:31 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sun, 13 Jun 2010 08:50:31 +0200
Subject: [PATCH] wm97xx_batt: Remove deprecated method to set pdata
In-Reply-To: <AANLkTikhclymsEo5jyS3Zi3bzRimgoYU1GWNNErtFVEi@mail.gmail.com>
References: <1276347073-3055-1-git-send-email-marek.vasut@gmail.com>
	<20100612172140.GB20610@opensource.wolfsonmicro.com>
	<AANLkTikhclymsEo5jyS3Zi3bzRimgoYU1GWNNErtFVEi@mail.gmail.com>
Message-ID: <201006130850.31627.marek.vasut@gmail.com>

Dne Ne 13. ?ervna 2010 04:33:11 Eric Miao napsal(a):
> On Sun, Jun 13, 2010 at 1:21 AM, Mark Brown
> 
> <broonie at opensource.wolfsonmicro.com> wrote:
> > On Sat, Jun 12, 2010 at 02:51:13PM +0200, Marek Vasut wrote:
> >> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> > 
> > Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> 
> Thanks. Applied.

Please also apply the other one (the one removing linux/wm97xx_batt.h)

Thanks!


From mike at compulab.co.il  Sun Jun 13 02:57:38 2010
From: mike at compulab.co.il (Mike Rapoport)
Date: Sun, 13 Jun 2010 09:57:38 +0300
Subject: [PATCH 4/5] [ARM] usb/host/ohci-pxa27x: make PXA310 USB OTG port
	work in host mode.
In-Reply-To: <AANLkTilUt8D7B3UF_j1wOvsnXTVQyioofwMEikScdLOn@mail.gmail.com>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-2-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-3-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-4-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-5-git-send-email-grinberg@compulab.co.il>
	<AANLkTilUt8D7B3UF_j1wOvsnXTVQyioofwMEikScdLOn@mail.gmail.com>
Message-ID: <4C148162.2020507@compulab.co.il>

Eric Miao wrote:
> On Wed, Jun 2, 2010 at 3:40 PM, Igor Grinberg <grinberg at compulab.co.il> wrote:
>> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
>> Signed-off-by: Mike Rapoport <mike at compulab.co.il>
>> ---
>>  arch/arm/mach-pxa/include/mach/ohci.h     |    3 +
>>  arch/arm/mach-pxa/include/mach/regs-u2d.h |    2 +
>>  drivers/usb/host/ohci-pxa27x.c            |  183 +++++++++++++++++++++++++++++
> 
> My feeling is on pxa310, the OTG/ULPI is actually closer to the UDC, so
> generally, I'd really like to see minimum change to ohci.

There are certain registers set up that should be done in order to 
enable the pxa310 otg port in the host mode. I agree that most of them 
should be done in the UDC driver, but since there's no UDC driver at all 
for pxa310, the most logical place for those register set ups would be 
pxa ohci glue driver.

-- 
Sincerely yours,
Mike.


From eric.y.miao at gmail.com  Sun Jun 13 03:01:32 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sun, 13 Jun 2010 15:01:32 +0800
Subject: [PATCH] wm97xx_batt: Remove deprecated method to set pdata
In-Reply-To: <201006130850.31627.marek.vasut@gmail.com>
References: <1276347073-3055-1-git-send-email-marek.vasut@gmail.com> 
	<20100612172140.GB20610@opensource.wolfsonmicro.com>
	<AANLkTikhclymsEo5jyS3Zi3bzRimgoYU1GWNNErtFVEi@mail.gmail.com> 
	<201006130850.31627.marek.vasut@gmail.com>
Message-ID: <AANLkTinjFxv0WsfkifvCfNH5XoZGvg1YfVe_HTBkBtNM@mail.gmail.com>

On Sun, Jun 13, 2010 at 2:50 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dne Ne 13. ?ervna 2010 04:33:11 Eric Miao napsal(a):
>> On Sun, Jun 13, 2010 at 1:21 AM, Mark Brown
>>
>> <broonie at opensource.wolfsonmicro.com> wrote:
>> > On Sat, Jun 12, 2010 at 02:51:13PM +0200, Marek Vasut wrote:
>> >> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
>> >
>> > Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
>>
>> Thanks. Applied.
>
> Please also apply the other one (the one removing linux/wm97xx_batt.h)
>

They are merged.


From eric.y.miao at gmail.com  Sun Jun 13 03:04:28 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sun, 13 Jun 2010 15:04:28 +0800
Subject: [PATCH 4/5] [ARM] usb/host/ohci-pxa27x: make PXA310 USB OTG port 
	work in host mode.
In-Reply-To: <4C148162.2020507@compulab.co.il>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il> 
	<1275464450-23003-2-git-send-email-grinberg@compulab.co.il> 
	<1275464450-23003-3-git-send-email-grinberg@compulab.co.il> 
	<1275464450-23003-4-git-send-email-grinberg@compulab.co.il> 
	<1275464450-23003-5-git-send-email-grinberg@compulab.co.il> 
	<AANLkTilUt8D7B3UF_j1wOvsnXTVQyioofwMEikScdLOn@mail.gmail.com> 
	<4C148162.2020507@compulab.co.il>
Message-ID: <AANLkTin2RmVoFhF7-2iWIx_7hRr473KZnyq9FOqZhcWi@mail.gmail.com>

On Sun, Jun 13, 2010 at 2:57 PM, Mike Rapoport <mike at compulab.co.il> wrote:
> Eric Miao wrote:
>>
>> On Wed, Jun 2, 2010 at 3:40 PM, Igor Grinberg <grinberg at compulab.co.il>
>> wrote:
>>>
>>> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
>>> Signed-off-by: Mike Rapoport <mike at compulab.co.il>
>>> ---
>>> ?arch/arm/mach-pxa/include/mach/ohci.h ? ? | ? ?3 +
>>> ?arch/arm/mach-pxa/include/mach/regs-u2d.h | ? ?2 +
>>> ?drivers/usb/host/ohci-pxa27x.c ? ? ? ? ? ?| ?183
>>> +++++++++++++++++++++++++++++
>>
>> My feeling is on pxa310, the OTG/ULPI is actually closer to the UDC, so
>> generally, I'd really like to see minimum change to ohci.
>
> There are certain registers set up that should be done in order to enable
> the pxa310 otg port in the host mode. I agree that most of them should be
> done in the UDC driver, but since there's no UDC driver at all for pxa310,

Wow, that's a big problem.

> the most logical place for those register set ups would be pxa ohci glue
> driver.
>

So, is there a simple way to setup the ULPI for the host within mach-pxa/*?
We need really really simple code for that, so it has minimum impact when
we move that part into pxa310-udc.c? I still want ohci-pxa27x to remain
minimum impacted.


From mike at compulab.co.il  Sun Jun 13 03:06:50 2010
From: mike at compulab.co.il (Mike Rapoport)
Date: Sun, 13 Jun 2010 10:06:50 +0300
Subject: [PATCH 4/5] [ARM] usb/host/ohci-pxa27x: make PXA310 USB OTG port
	work in host mode.
In-Reply-To: <AANLkTin2RmVoFhF7-2iWIx_7hRr473KZnyq9FOqZhcWi@mail.gmail.com>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-2-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-3-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-4-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-5-git-send-email-grinberg@compulab.co.il>
	<AANLkTilUt8D7B3UF_j1wOvsnXTVQyioofwMEikScdLOn@mail.gmail.com>
	<4C148162.2020507@compulab.co.il>
	<AANLkTin2RmVoFhF7-2iWIx_7hRr473KZnyq9FOqZhcWi@mail.gmail.com>
Message-ID: <4C14838A.7060509@compulab.co.il>

Eric Miao wrote:
> On Sun, Jun 13, 2010 at 2:57 PM, Mike Rapoport <mike at compulab.co.il> wrote:
>> Eric Miao wrote:
>>> On Wed, Jun 2, 2010 at 3:40 PM, Igor Grinberg <grinberg at compulab.co.il>
>>> wrote:
>>>> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
>>>> Signed-off-by: Mike Rapoport <mike at compulab.co.il>
>>>> ---
>>>>  arch/arm/mach-pxa/include/mach/ohci.h     |    3 +
>>>>  arch/arm/mach-pxa/include/mach/regs-u2d.h |    2 +
>>>>  drivers/usb/host/ohci-pxa27x.c            |  183
>>>> +++++++++++++++++++++++++++++
>>> My feeling is on pxa310, the OTG/ULPI is actually closer to the UDC, so
>>> generally, I'd really like to see minimum change to ohci.
>> There are certain registers set up that should be done in order to enable
>> the pxa310 otg port in the host mode. I agree that most of them should be
>> done in the UDC driver, but since there's no UDC driver at all for pxa310,
> 
> Wow, that's a big problem.
 >
>> the most logical place for those register set ups would be pxa ohci glue
>> driver.
>>
> 
> So, is there a simple way to setup the ULPI for the host within mach-pxa/*?
> We need really really simple code for that, so it has minimum impact when
> we move that part into pxa310-udc.c? I still want ohci-pxa27x to remain
> minimum impacted.

we can put most of the code in, say, arch/arm/mach-pxa/pxa3xx-u2d.c and 
add hooks in ohci-pxa27x.

-- 
Sincerely yours,
Mike.


From saeed at marvell.com  Sun Jun 13 03:38:10 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Sun, 13 Jun 2010 10:38:10 +0300
Subject: [PATCH 1/2 v2] mv643xx_eth: use sw csum for big packets
In-Reply-To: <20100612083137.GO1743@mail.wantstofly.org>
References: <FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>
	<1276073483-17208-1-git-send-email-saeed@marvell.com>
	<20100610064330.GK1743@mail.wantstofly.org>
	<FCBE654890C0334289D0AD3AF4EF009F9FAC75AA96@IL-MB01.marvell.com>
	<20100612083137.GO1743@mail.wantstofly.org>
Message-ID: <FCBE654890C0334289D0AD3AF4EF009F9FAC7B6E2B@IL-MB01.marvell.com>

 

>-----Original Message-----
>From: Lennert Buytenhek [mailto:buytenh at wantstofly.org] 
>Sent: Saturday, June 12, 2010 11:32 AM
>To: Saeed Bishara
>Cc: linux-net at vger.kernel.org; linux-arm-kernel at lists.infradead.org
>Subject: Re: [PATCH 1/2 v2] mv643xx_eth: use sw csum for big packets
>
>On Thu, Jun 10, 2010 at 10:38:05AM +0300, Saeed Bishara wrote:
>
>> >> diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
>> >> index e345ec8..2d0e06b 100644
>> >> --- a/drivers/net/mv643xx_eth.c
>> >> +++ b/drivers/net/mv643xx_eth.c
>> >> @@ -289,6 +289,7 @@ struct mv643xx_eth_shared_private {
>> >>  	unsigned int t_clk;
>> >>  	int extended_rx_coal_limit;
>> >>  	int tx_bw_control;
>> >> +	int tx_csum_limit;
>> >>  };
>> >>  
>> >>  #define TX_BW_CONTROL_ABSENT		0
>> >> @@ -782,7 +783,8 @@ static int txq_submit_skb(struct 
>> >tx_queue *txq, struct sk_buff *skb)
>> >>  		       skb->protocol != htons(ETH_P_8021Q));
>> >>  
>> >>  		tag_bytes = (void *)ip_hdr(skb) - (void 
>> >*)skb->data - ETH_HLEN;
>> >> -		if (unlikely(tag_bytes & ~12)) {
>> >> +		if (unlikely(tag_bytes & ~12) ||
>> >> +			skb->len > mp->shared->tx_csum_limit) {
>> >
>> >Please line up skb->len with unlikely() on the line above it.
>> >
>> >
>> >> @@ -2666,6 +2668,9 @@ static int 
>> >mv643xx_eth_shared_probe(struct platform_device *pdev)
>> >>  	 * Detect hardware parameters.
>> >>  	 */
>> >>  	msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk 
>> >: 133000000;
>> >> +	msp->tx_csum_limit = pd->tx_csum_limit ? 
>> >pd->tx_csum_limit : 9 * 1024;
>> >> +	/* add header count so we can compare against skb->len */
>> >> +	msp->tx_csum_limit += ETH_HLEN;
>> >>  	infer_hw_params(msp);
>> >
>> >Is the limit 9 * 1024 + 14 for the whole packet, or 9 * 
>1024 for the IP
>> >part?
>>
>> the limit is for the IP part, but I thought that adding the 
>header length, then comparing agains skb->len will be the 
>same. What do you suggest?
>
>Right, but for the header length you take 14, while if to include VLAN
>tags or DSA tags the header might actually be longer -- how does that
>affect the ability of the hardware to compute the checksum?
>
>I.e. is the restriction "total packet length must be < N + 14 bytes"
>or is it "the IP part must be < N bytes and it doesn't matter whether
>there are VLAN tags or not"?
It's the second option: "the IP part must be < N" regardless to the L2 header.
saeed
>
>I.e.:
>
>> >I.e. what happens if skb->len is 9 * 1024 + 15, but there 
>is one VLAN
>> >tag present -- will the hardware be able to do the checksum 
>offload or
>> >not?
>

From grinberg at compulab.co.il  Sun Jun 13 04:31:49 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Sun, 13 Jun 2010 11:31:49 +0300
Subject: [PATCH 2/2] [ARM] pxa/cm-x300: enable the IRQ_WAKEUP0 as wakeup
	source.
In-Reply-To: <1276417909-22980-2-git-send-email-grinberg@compulab.co.il>
References: <1276417909-22980-1-git-send-email-grinberg@compulab.co.il>
	<1276417909-22980-2-git-send-email-grinberg@compulab.co.il>
Message-ID: <1276417909-22980-3-git-send-email-grinberg@compulab.co.il>


Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
Signed-off-by: Mike Rapoport <mike at compulab.co.il>
---
 arch/arm/mach-pxa/cm-x300.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index fdda6be..8d227b4 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -689,6 +689,7 @@ static void __init cm_x300_init_da9030(void)
 {
 	pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info);
 	i2c_register_board_info(1, &cm_x300_pmic_info, 1);
+	set_irq_wake(IRQ_WAKEUP0, 1);
 }
 
 static void __init cm_x300_init_wi2wi(void)
-- 
1.6.4.4



From grinberg at compulab.co.il  Sun Jun 13 04:31:47 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Sun, 13 Jun 2010 11:31:47 +0300
Subject: [PATCH 0/2] [ARM] pxa3xx: enable the IRQ_WAKEUPx to be a wakeup
	source.
Message-ID: <1276417909-22980-1-git-send-email-grinberg@compulab.co.il>

Hardware specific setup should be done to enable
the IRQ_WAKEUPx as a wakeup source on pxa3xx cpu.
This patch series enables the IRQ_WAKEUPx to be
a wakeup source and makes use of it on cm-x300.

Igor Grinberg (2):
  [ARM] pxa3xx: add set_type to the ext_wakeup irq chip.
  [ARM] pxa/cm-x300: enable the IRQ_WAKEUP0 as wakeup source.

 arch/arm/mach-pxa/cm-x300.c |    1 +
 arch/arm/mach-pxa/pxa3xx.c  |   12 ++++++++++++
 2 files changed, 13 insertions(+), 0 deletions(-)



From grinberg at compulab.co.il  Sun Jun 13 04:31:48 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Sun, 13 Jun 2010 11:31:48 +0300
Subject: [PATCH 1/2] [ARM] pxa3xx: add set_type to the ext_wakeup irq chip.
In-Reply-To: <1276417909-22980-1-git-send-email-grinberg@compulab.co.il>
References: <1276417909-22980-1-git-send-email-grinberg@compulab.co.il>
Message-ID: <1276417909-22980-2-git-send-email-grinberg@compulab.co.il>

pxa3xx cpu needs the irq type setup to be able to
wakeup from low power mode on IRQ_WAKEUPx events.

Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
Signed-off-by: Mike Rapoport <mike at compulab.co.il>
---
 arch/arm/mach-pxa/pxa3xx.c |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index f2f4127..2d54812 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -566,11 +566,23 @@ static void pxa_unmask_ext_wakeup(unsigned int irq)
 	PECR |= PECR_IE(irq - IRQ_WAKEUP0);
 }
 
+static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type)
+{
+	if (flow_type & IRQ_TYPE_EDGE_RISING)
+		PWER |= 1 << (irq - IRQ_WAKEUP0);
+
+	if (flow_type & IRQ_TYPE_EDGE_FALLING)
+		PWER |= 1 << (irq - IRQ_WAKEUP0 + 2);
+
+	return 0;
+}
+
 static struct irq_chip pxa_ext_wakeup_chip = {
 	.name		= "WAKEUP",
 	.ack		= pxa_ack_ext_wakeup,
 	.mask		= pxa_mask_ext_wakeup,
 	.unmask		= pxa_unmask_ext_wakeup,
+	.set_type	= pxa_set_ext_wakeup_type,
 };
 
 static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
-- 
1.6.4.4



From dedekind1 at gmail.com  Sun Jun 13 05:16:06 2010
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Sun, 13 Jun 2010 12:16:06 +0300
Subject: [PATCH] ixp4xx: add support for static flash partitions
In-Reply-To: <20100531162434.GA4599@riccoc20.at.omicron.at>
References: <20100531162434.GA4599@riccoc20.at.omicron.at>
Message-ID: <1276420566.19028.184.camel@localhost>

On Mon, 2010-05-31 at 18:24 +0200, Richard Cochran wrote:
> This patch adds support for static flash partitioning from a platform
> device. Also, we clean up some weirdness where statements were separated
> by commas instead of semicolons. While we are at it, fix some minor bad
> white space, too.
> 
> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
> ---
>  drivers/mtd/maps/ixp4xx.c |   37 ++++++++++++++++++++++++++++---------
>  1 files changed, 28 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/mtd/maps/ixp4xx.c b/drivers/mtd/maps/ixp4xx.c
> index 7b05152..5345d11 100644
> --- a/drivers/mtd/maps/ixp4xx.c
> +++ b/drivers/mtd/maps/ixp4xx.c
> @@ -108,7 +108,7 @@ static void ixp4xx_copy_from(struct map_info *map, void *to,
>  
>  	if (from & 1) {
>  		*dest++ = BYTE1(flash_read16(src));
> -                src++;
> +		src++;
>  		--len;
>  	}

Your patch mostly applies, except of this chunk, which was modified
before by

commit 53f2b1c86a1fa1414be93571062ac4c263fa9fbc
Author: Jon Ringle <jon at ringle.org>
Date:   Wed Jan 13 09:36:10 2010 -0500

    mtd: ixp4xx: fix reading from half-word boundary
    
    Fix handling of reads that don't start on a half-word boundary.
    
    Signed-off-by: Jon Ringle <jon at ringle.org>
    Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy at nokia.com>
    Signed-off-by: David Woodhouse <David.Woodhouse at intel.com>

I could fix your patch up myself, but I do not know the code, so please,
re-send a patch against the latest mtd-2.6 tree.
-- 
Best Regards,
Artem Bityutskiy (????? ????????)



From marek.vasut at gmail.com  Sun Jun 13 06:30:08 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sun, 13 Jun 2010 12:30:08 +0200
Subject: [PATCH 1/3] ISL6271A voltage regulator support.
In-Reply-To: <20100612172114.GA20610@opensource.wolfsonmicro.com>
References: <1276346679-2893-1-git-send-email-marek.vasut@gmail.com>
	<20100612172114.GA20610@opensource.wolfsonmicro.com>
Message-ID: <201006131230.08408.marek.vasut@gmail.com>

Dne So 12. ?ervna 2010 19:21:14 Mark Brown napsal(a):
> On Sat, Jun 12, 2010 at 02:44:37PM +0200, Marek Vasut wrote:
> > This device is very simple, it supports only one LDO. This single LDO is
> > programmed over I2C to 16 possible voltages.
> 
> Google tells me that the device has three regulators on it - two LDOs
> and one DCDC buck convertor:
> 
>    http://www.intersil.com/products/deviceinfo.asp?pn=ISL6271A
> 
> While the LDOs look like they have no software control it'd be best to
> provide hookup for them, even if that's just a case of instantiating the
> appropriate fixed voltage regulators.

Is this necessary? I'd only increase the kernel size without any gain ... or am 
I wrong ?
> 
> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> > 
> > +/* Supported voltage values for regulators */
> > +static const u32 core_buck_table[] = {
> > +	 850000,  900000,  950000, 1000000,
> > +	1050000, 1100000, 1150000, 1200000,
> > +	1250000, 1300000, 1350000, 1400000,
> > +	1450000, 1500000, 1550000, 1600000,
> > +};
> 
> This looks like it could be replaced with a simple function rather than
> a lookup table which would simplify the code.

Will do.
> 
> Also, are you sure this is a buck?  That's a specific technical term
> usually only applied to DCDC regulators - LDOs are a different type of
> regulator

That's what's written in the ISL6271a TRM. On the first page, under the 
"Features" section.
> 
> > +static int __devinit isl6271a_probe(struct i2c_client *client,
> > +				     const struct i2c_device_id *id)
> > +{
> > +	struct regulator_init_data *init_data	= client->dev.platform_data;
> > +	struct isl_pmic *pmic;
> > +	int err;
> > +
> > +	if (!i2c_check_functionality(client->adapter,
> > I2C_FUNC_SMBUS_BYTE_DATA)) +		return -EIO;
> > +
> > +	if (!init_data)
> > +		return -EIO;
> 
> It'd be better to print an error message here so users know what's going
> on when the device fails to appear.

Ok.

Thanks!


From eric.y.miao at gmail.com  Sun Jun 13 06:47:54 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sun, 13 Jun 2010 18:47:54 +0800
Subject: [PATCH] mioa701: fix camera regression
In-Reply-To: <87pr01mnw1.fsf@free.fr>
References: <1275514190-32006-1-git-send-email-robert.jarzmik@free.fr> 
	<Pine.LNX.4.64.1006032058380.19573@axis700.grange>
	<87pr01mnw1.fsf@free.fr>
Message-ID: <AANLkTikvIN3bnxEQrz9ZtTB4vhg3nygx8JJ5aqwQlfbD@mail.gmail.com>

On Wed, Jun 9, 2010 at 1:31 AM, Robert Jarzmik <robert.jarzmik at free.fr> wrote:
>> On Wed, 2 Jun 2010, Robert Jarzmik wrote:
>>
>>> Since commit a48c24a696f0d93c49f913b7818e9819612b1f4e, the
>>> camera is not working anymore.
>>>
>>> After the v4l2 migration, the mt9m111 camera board
>>> information was not passed to the i2c layer anymore, but
>>> stored for future use of v4l2 (through soc_camera).
>>>
>>> Because mioa701_i2c_devices[] was tagged as "__initdata",
>>> and because after the v4l2 migration, the new structure
>>> "iclink" references it, the mt9m111 driver is not probed
>>> anymore, as part of "iclink" is not valid (discarded after
>>> kernel init).
>>>
>>> Although there is not compilation error, nor runtime oops,
>>> this patch restores a working camera on the mioa701 board.
>>>
>>> Signed-off-by: Robert Jarzmik <robert.jarzmik at free.fr>
>>
>> Acked-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>
>>
>>>
>>> --
>>> Eric, could you schedule that into your fix branch please ?
>
> Ping.
>

Sorry. Now merged.


From eric.y.miao at gmail.com  Sun Jun 13 06:53:38 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Sun, 13 Jun 2010 18:53:38 +0800
Subject: [PATCH 1/2] ISL6271A voltage regulator support.
In-Reply-To: <201006071654.51324.marek.vasut@gmail.com>
References: <1275887908-22285-1-git-send-email-marek.vasut@gmail.com> 
	<20100607114856.GD5993@sirena.org.uk>
	<201006071654.51324.marek.vasut@gmail.com>
Message-ID: <AANLkTilhU0XW7fo4yOT7v6AXc0UNmlGGiMs7ilGXQJii@mail.gmail.com>

On Mon, Jun 7, 2010 at 10:54 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dne Po 7. ?ervna 2010 13:48:56 Mark Brown napsal(a):
>> On Mon, Jun 07, 2010 at 07:18:27AM +0200, Marek Vasut wrote:
>> > This device is very simple, it supports only one LDO. This single LDO is
>> > programmed over I2C to 16 possible voltages.
>>
>> Marek, you really should know to CC patches to maintainers by now. ?This
>> is not CCed to myself, Liam or lkml.
>

Indeed Marek, please Cc Liam and Mark Brown for any sound/regulator stuffs.

And I am a bit confused about this as well, since PATCH 1/2 and PATCH 2/2
doesn't seem to be related. Next time, I'd suggest such two be
individual patches.


From marek.vasut at gmail.com  Sun Jun 13 07:28:41 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sun, 13 Jun 2010 13:28:41 +0200
Subject: [PATCH v2] ISL6271A voltage regulator support.
Message-ID: <1276428521-6926-1-git-send-email-marek.vasut@gmail.com>

This device is very simple, it supports only one LDO. This single LDO is
programmed over I2C to 16 possible voltages.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/regulator/Kconfig              |    6 +
 drivers/regulator/Makefile             |    1 +
 drivers/regulator/isl6271a-regulator.c |  195 ++++++++++++++++++++++++++++++++
 3 files changed, 202 insertions(+), 0 deletions(-)
 create mode 100644 drivers/regulator/isl6271a-regulator.c

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 04f2e08..6772ca7 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -201,5 +201,11 @@ config REGULATOR_88PM8607
 	help
 	  This driver supports 88PM8607 voltage regulator chips.
 
+config REGULATOR_ISL6271A
+	tristate "Intersil ISL6271A Power regulator"
+	depends on I2C
+	help
+	  This driver supports ISL6271A voltage regulator chip.
+
 endif
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 4e7feec..e2191bf 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
 obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o
 obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
 obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
+obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/isl6271a-regulator.c b/drivers/regulator/isl6271a-regulator.c
new file mode 100644
index 0000000..e5068d5
--- /dev/null
+++ b/drivers/regulator/isl6271a-regulator.c
@@ -0,0 +1,195 @@
+/*
+ * isl6271a-regulator.c
+ *
+ * Support for Intersil ISL6271A voltage regulator
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#define	ISL6271A_VOLTAGE_MIN	850000
+#define	ISL6271A_VOLTAGE_MAX	1600000
+#define	ISL6271A_VOLTAGE_STEP	50000
+
+/* PMIC details */
+struct isl_pmic {
+	struct regulator_desc	desc;
+	struct i2c_client	*client;
+	struct regulator_dev	*rdev;
+	struct mutex		mtx;
+};
+
+static int isl6271a_get_voltage(struct regulator_dev *dev)
+{
+	struct isl_pmic *pmic = rdev_get_drvdata(dev);
+	int idx, data;
+
+	mutex_lock(&pmic->mtx);
+
+	idx = i2c_smbus_read_byte(pmic->client);
+	if (idx < 0) {
+		dev_err(&pmic->client->dev, "Error getting voltage\n");
+		data = idx;
+		goto out;
+	}
+
+	/* Convert the data from chip to microvolts */
+	data = ISL6271A_VOLTAGE_MIN + (ISL6271A_VOLTAGE_STEP * (idx & 0xf));
+
+out:
+	mutex_unlock(&pmic->mtx);
+	return data;
+}
+
+static int isl6271a_set_voltage(struct regulator_dev *dev, int minuV, int maxuV)
+{
+	struct isl_pmic *pmic = rdev_get_drvdata(dev);
+	int vsel, err, data;
+
+	if (minuV < ISL6271A_VOLTAGE_MIN || minuV > ISL6271A_VOLTAGE_MAX)
+		return -EINVAL;
+	if (maxuV < ISL6271A_VOLTAGE_MIN || maxuV > ISL6271A_VOLTAGE_MAX)
+		return -EINVAL;
+
+	/* Align to 50000 mV */
+	vsel = minuV - (minuV % ISL6271A_VOLTAGE_STEP);
+
+	/* If the result fell out of [minuV,maxuV] range, put it back */
+	if (vsel < minuV)
+		vsel += ISL6271A_VOLTAGE_STEP;
+
+	/* Convert the microvolts to data for the chip */
+	data = (vsel - ISL6271A_VOLTAGE_MIN) / ISL6271A_VOLTAGE_STEP;
+
+	mutex_lock(&pmic->mtx);
+
+	err = i2c_smbus_write_byte(pmic->client, data);
+	if (err < 0)
+		dev_err(&pmic->client->dev, "Error setting voltage\n");
+
+	mutex_unlock(&pmic->mtx);
+	return err;
+}
+
+static int isl6271a_list_voltage(struct regulator_dev *dev, unsigned selector)
+{
+	return ISL6271A_VOLTAGE_MIN + (ISL6271A_VOLTAGE_STEP * selector);
+}
+
+static struct regulator_ops isl_core_ops = {
+	.get_voltage	= isl6271a_get_voltage,
+	.set_voltage	= isl6271a_set_voltage,
+	.list_voltage	= isl6271a_list_voltage,
+};
+
+static int __devinit isl6271a_probe(struct i2c_client *i2c,
+				     const struct i2c_device_id *id)
+{
+	struct regulator_init_data *init_data	= i2c->dev.platform_data;
+	struct isl_pmic *pmic;
+	int err;
+
+	if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+		return -EIO;
+
+	if (!init_data) {
+		dev_err(&i2c->dev, "no platform data supplied\n");
+		return -EIO;
+	}
+
+	pmic = kzalloc(sizeof(struct isl_pmic), GFP_KERNEL);
+	if (!pmic)
+		return -ENOMEM;
+
+	pmic->client = i2c;
+
+	mutex_init(&pmic->mtx);
+
+	pmic->desc.name	= "Core Buck";
+	pmic->desc.id	= 0;
+	pmic->desc.n_voltages = 16;
+	pmic->desc.ops	= &isl_core_ops;
+	pmic->desc.type	= REGULATOR_VOLTAGE;
+	pmic->desc.owner = THIS_MODULE;
+
+	pmic->rdev = regulator_register(&pmic->desc, &i2c->dev,
+					init_data, pmic);
+	if (IS_ERR(pmic->rdev)) {
+		dev_err(&i2c->dev, "failed to register %s\n", id->name);
+		err = PTR_ERR(pmic->rdev);
+		goto error;
+	}
+
+	i2c_set_clientdata(i2c, pmic);
+
+	return 0;
+
+error:
+	kfree(pmic);
+	return err;
+}
+
+static int __devexit isl6271a_remove(struct i2c_client *i2c)
+{
+	struct isl_pmic *pmic = i2c_get_clientdata(i2c);
+
+	i2c_set_clientdata(i2c, NULL);
+
+	regulator_unregister(pmic->rdev);
+
+	kfree(pmic);
+
+	return 0;
+}
+
+static const struct i2c_device_id isl6271a_id[] = {
+	{.name = "isl6271a", 0 },
+	{ },
+};
+
+MODULE_DEVICE_TABLE(i2c, isl6271a_id);
+
+static struct i2c_driver isl6271a_i2c_driver = {
+	.driver = {
+		.name = "isl6271a",
+		.owner = THIS_MODULE,
+	},
+	.probe = isl6271a_probe,
+	.remove = __devexit_p(isl6271a_remove),
+	.id_table = isl6271a_id,
+};
+
+static int __init isl6271a_init(void)
+{
+	return i2c_add_driver(&isl6271a_i2c_driver);
+}
+
+static void __exit isl6271a_cleanup(void)
+{
+	i2c_del_driver(&isl6271a_i2c_driver);
+}
+
+subsys_initcall(isl6271a_init);
+module_exit(isl6271a_cleanup);
+
+MODULE_AUTHOR("Marek Vasut <marek.vasut at gmail.com>");
+MODULE_DESCRIPTION("Intersil ISL6271A voltage regulator driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.1



From marek.vasut at gmail.com  Sun Jun 13 07:44:20 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sun, 13 Jun 2010 13:44:20 +0200
Subject: [PATCH 1/2] ARM/scoop: Add CPR register bit definitions
Message-ID: <1276429461-10402-1-git-send-email-marek.vasut@gmail.com>

Add bit definitions of the CPR register of the SCOOP chip into scoop.h. Also,
cleanup the GPCR definitions to match coding style.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/include/asm/hardware/scoop.h |   29 +++++++++++++++++------------
 1 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h
index 46492a6..ebb3cea 100644
--- a/arch/arm/include/asm/hardware/scoop.h
+++ b/arch/arm/include/asm/hardware/scoop.h
@@ -22,18 +22,23 @@
 #define SCOOP_GPWR 0x24
 #define SCOOP_GPRR 0x28
 
-#define SCOOP_GPCR_PA22	( 1 << 12 )
-#define SCOOP_GPCR_PA21	( 1 << 11 )
-#define SCOOP_GPCR_PA20	( 1 << 10 )
-#define SCOOP_GPCR_PA19	( 1 << 9 )
-#define SCOOP_GPCR_PA18	( 1 << 8 )
-#define SCOOP_GPCR_PA17	( 1 << 7 )
-#define SCOOP_GPCR_PA16	( 1 << 6 )
-#define SCOOP_GPCR_PA15	( 1 << 5 )
-#define SCOOP_GPCR_PA14	( 1 << 4 )
-#define SCOOP_GPCR_PA13	( 1 << 3 )
-#define SCOOP_GPCR_PA12	( 1 << 2 )
-#define SCOOP_GPCR_PA11	( 1 << 1 )
+#define SCOOP_CPR_OUT	(1 << 7)
+#define SCOOP_CPR_SD_3V	(1 << 2)
+#define SCOOP_CPR_CF_XV	(1 << 1)
+#define SCOOP_CPR_CF_3V	(1 << 0)
+
+#define SCOOP_GPCR_PA22	(1 << 12)
+#define SCOOP_GPCR_PA21	(1 << 11)
+#define SCOOP_GPCR_PA20	(1 << 10)
+#define SCOOP_GPCR_PA19	(1 << 9)
+#define SCOOP_GPCR_PA18	(1 << 8)
+#define SCOOP_GPCR_PA17	(1 << 7)
+#define SCOOP_GPCR_PA16	(1 << 6)
+#define SCOOP_GPCR_PA15	(1 << 5)
+#define SCOOP_GPCR_PA14	(1 << 4)
+#define SCOOP_GPCR_PA13	(1 << 3)
+#define SCOOP_GPCR_PA12	(1 << 2)
+#define SCOOP_GPCR_PA11	(1 << 1)
 
 struct scoop_config {
 	unsigned short io_out;
-- 
1.7.1



From marek.vasut at gmail.com  Sun Jun 13 07:44:21 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sun, 13 Jun 2010 13:44:21 +0200
Subject: [PATCH 2/2] pxa/spitz: Rework spitz
In-Reply-To: <1276429461-10402-1-git-send-email-marek.vasut@gmail.com>
References: <1276429461-10402-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1276429461-10402-2-git-send-email-marek.vasut@gmail.com>

This huge patch mostly shuffles code. The spitz.c file contained terrible mess
and needed a cleanup, here it is:

1) Made every part modular, components are not built in if not selected.
2) Removed loads of preprocessor goo, mostly "#ifdef MACH_AKITA .... #endif" and
   similar code. The kernel size will grow by a few kb now, but the file is much
   more readable.
3) Reworked SD/CF power setting function and made it reentrant.
4) Add ISL6271A regulator support
5) Correctly register WM8750

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/include/mach/spitz.h |    2 -
 arch/arm/mach-pxa/spitz.c              |  810 ++++++++++++++++++-------------
 2 files changed, 470 insertions(+), 342 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index fa1998c..685749a 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
@@ -185,7 +185,5 @@
 /*
  * Shared data structures
  */
-extern struct platform_device spitzscoop_device;
-extern struct platform_device spitzscoop2_device;
 extern struct platform_device spitzssp_device;
 extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 4d2413e..fa31980 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -18,14 +18,15 @@
 #include <linux/gpio_keys.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
-#include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/spi/corgi_lcd.h>
+#include <linux/mtd/physmap.h>
 #include <linux/mtd/sharpsl.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -33,11 +34,9 @@
 #include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/scoop.h>
 
-
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/reset.h>
-#include <plat/i2c.h>
 #include <mach/irda.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
@@ -45,11 +44,16 @@
 #include <mach/pxa2xx_spi.h>
 #include <mach/spitz.h>
 
+#include <plat/i2c.h>
+
 #include "generic.h"
 #include "devices.h"
 #include "sharpsl.h"
 
-static unsigned long spitz_pin_config[] __initdata = {
+/******************************************************************************
+ * Pin configuration
+ ******************************************************************************/
+static unsigned long sharpslc_pin_config[] __initdata = {
 	/* Chip Selects */
 	GPIO78_nCS_2,	/* SCOOP #2 */
 	GPIO79_nCS_3,	/* NAND */
@@ -124,10 +128,13 @@ static unsigned long spitz_pin_config[] __initdata = {
 	GPIO1_GPIO | WAKEUP_ON_EDGE_FALL,	/* SPITZ_GPIO_RESET */
 };
 
-/*
- * Spitz SCOOP Device #1
- */
-static struct resource spitz_scoop_resources[] = {
+
+/******************************************************************************
+ * Scoop GPIO expander
+ ******************************************************************************/
+#if defined(CONFIG_SHARP_SCOOP) || defined(CONFIG_SHARP_SCOOP_MODULE)
+/* SCOOP Device #1 */
+static struct resource sharpslc_scoop_1_resources[] = {
 	[0] = {
 		.start		= 0x10800000,
 		.end		= 0x10800fff,
@@ -135,7 +142,7 @@ static struct resource spitz_scoop_resources[] = {
 	},
 };
 
-static struct scoop_config spitz_scoop_setup = {
+static struct scoop_config sharpslc_scoop_1_setup = {
 	.io_dir		= SPITZ_SCP_IO_DIR,
 	.io_out		= SPITZ_SCP_IO_OUT,
 	.suspend_clr	= SPITZ_SCP_SUS_CLR,
@@ -143,20 +150,18 @@ static struct scoop_config spitz_scoop_setup = {
 	.gpio_base	= SPITZ_SCP_GPIO_BASE,
 };
 
-struct platform_device spitzscoop_device = {
+struct platform_device sharpslc_scoop_1_device = {
 	.name		= "sharp-scoop",
 	.id		= 0,
 	.dev		= {
- 		.platform_data	= &spitz_scoop_setup,
+		.platform_data	= &sharpslc_scoop_1_setup,
 	},
-	.num_resources	= ARRAY_SIZE(spitz_scoop_resources),
-	.resource	= spitz_scoop_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_scoop_1_resources),
+	.resource	= sharpslc_scoop_1_resources,
 };
 
-/*
- * Spitz SCOOP Device #2
- */
-static struct resource spitz_scoop2_resources[] = {
+/* SCOOP Device #2 */
+static struct resource sharpslc_scoop_2_resources[] = {
 	[0] = {
 		.start		= 0x08800040,
 		.end		= 0x08800fff,
@@ -164,7 +169,7 @@ static struct resource spitz_scoop2_resources[] = {
 	},
 };
 
-static struct scoop_config spitz_scoop2_setup = {
+static struct scoop_config sharpslc_scoop_2_setup = {
 	.io_dir		= SPITZ_SCP2_IO_DIR,
 	.io_out		= SPITZ_SCP2_IO_OUT,
 	.suspend_clr	= SPITZ_SCP2_SUS_CLR,
@@ -172,82 +177,110 @@ static struct scoop_config spitz_scoop2_setup = {
 	.gpio_base	= SPITZ_SCP2_GPIO_BASE,
 };
 
-struct platform_device spitzscoop2_device = {
+struct platform_device sharpslc_scoop_2_device = {
 	.name		= "sharp-scoop",
 	.id		= 1,
 	.dev		= {
- 		.platform_data	= &spitz_scoop2_setup,
+		.platform_data	= &sharpslc_scoop_2_setup,
 	},
-	.num_resources	= ARRAY_SIZE(spitz_scoop2_resources),
-	.resource	= spitz_scoop2_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_scoop_2_resources),
+	.resource	= sharpslc_scoop_2_resources,
 };
 
-#define SPITZ_PWR_SD 0x01
-#define SPITZ_PWR_CF 0x02
+static void __init sharpslc_scoop_init(void)
+{
+	platform_device_register(&sharpslc_scoop_1_device);
+
+	/* Akita doesn't have the second SCOOP chip */
+	if (!machine_is_akita())
+		platform_device_register(&sharpslc_scoop_2_device);
+}
 
 /* Power control is shared with between one of the CF slots and SD */
-static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr)
+static void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr)
 {
-	unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR);
+	unsigned short cpr;
+	unsigned long flags;
 
-	if (new_cpr & 0x0007) {
+	if (new_cpr & 0x7) {
 		gpio_set_value(SPITZ_GPIO_CF_POWER, 1);
-		if (!(cpr & 0x0002) && !(cpr & 0x0004))
-		        mdelay(5);
-		if (device == SPITZ_PWR_CF)
-		        cpr |= 0x0002;
-		if (device == SPITZ_PWR_SD)
-		        cpr |= 0x0004;
-	        write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
-	} else {
-		if (device == SPITZ_PWR_CF)
-		        cpr &= ~0x0002;
-		if (device == SPITZ_PWR_SD)
-		        cpr &= ~0x0004;
-		if (!(cpr & 0x0002) && !(cpr & 0x0004)) {
-			write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, 0x0000);
-		        mdelay(1);
-			gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
-		} else {
-		        write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
-		}
+		mdelay(5);
+	}
+
+	local_irq_save(flags);
+
+	cpr = read_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR);
+
+	if (enable & new_cpr)
+		cpr |= new_cpr;
+	else
+		cpr &= ~enable;
+
+	write_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR, cpr);
+
+	local_irq_restore(flags);
+
+	if (!(cpr & 0x7)) {
+		mdelay(1);
+		gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
 	}
 }
 
-static void spitz_pcmcia_pwr(struct device *scoop, unsigned short cpr, int nr)
+#else
+static inline void sharpslc_scoop_init(void) {}
+static inline void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr) {}
+#endif
+
+/******************************************************************************
+ * PCMCIA
+ ******************************************************************************/
+#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
+static void sharpslc_pcmcia_pwr(struct device *scoop, uint16_t cpr, int nr)
 {
 	/* Only need to override behaviour for slot 0 */
 	if (nr == 0)
-		spitz_card_pwr_ctrl(SPITZ_PWR_CF, cpr);
+		sharpslc_card_pwr_ctrl(
+			cpr & (SCOOP_CPR_CF_3V | SCOOP_CPR_CF_XV), cpr);
 	else
 		write_scoop_reg(scoop, SCOOP_CPR, cpr);
 }
 
-static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
-{
-	.dev        = &spitzscoop_device.dev,
-	.irq        = SPITZ_IRQ_GPIO_CF_IRQ,
-	.cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
-	.cd_irq_str = "PCMCIA0 CD",
-},{
-	.dev        = &spitzscoop2_device.dev,
-	.irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
-	.cd_irq     = -1,
-},
+static struct scoop_pcmcia_dev sharpslc_pcmcia_scoop[] = {
+	{
+		.dev        = &sharpslc_scoop_1_device.dev,
+		.irq        = SPITZ_IRQ_GPIO_CF_IRQ,
+		.cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
+		.cd_irq_str = "PCMCIA0 CD",
+	}, {
+		.dev        = &sharpslc_scoop_2_device.dev,
+		.irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
+		.cd_irq     = -1,
+	},
 };
 
-static struct scoop_pcmcia_config spitz_pcmcia_config = {
-	.devs         = &spitz_pcmcia_scoop[0],
-	.num_devs     = 2,
-	.power_ctrl   = spitz_pcmcia_pwr,
+static struct scoop_pcmcia_config sharpslc_pcmcia_config = {
+	.devs		= &sharpslc_pcmcia_scoop[0],
+	.num_devs	= 2,
+	.power_ctrl	= sharpslc_pcmcia_pwr,
 };
 
-EXPORT_SYMBOL(spitzscoop_device);
-EXPORT_SYMBOL(spitzscoop2_device);
+static void __init sharpslc_pcmcia_init(void)
+{
+	/* Akita has only one PCMCIA slot used */
+	if (machine_is_akita())
+		sharpslc_pcmcia_config.num_devs = 1;
+
+	platform_scoop_config = &sharpslc_pcmcia_config;
+}
+#else
+static inline void sharpslc_pcmcia_init(void) {}
+#endif
+
+/******************************************************************************
+ * GPIO keyboard
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
 
-/*
- * Spitz Keyboard Device
- */
 #define SPITZ_KEY_CALENDAR	KEY_F1
 #define SPITZ_KEY_ADDRESS	KEY_F2
 #define SPITZ_KEY_FN		KEY_F3
@@ -263,7 +296,7 @@ EXPORT_SYMBOL(spitzscoop2_device);
 #define SPITZ_KEY_OK		KEY_F11
 #define SPITZ_KEY_MENU		KEY_F12
 
-static const uint32_t spitzkbd_keymap[] = {
+static const uint32_t sharpslc_keymap[] = {
 	KEY(0, 0, KEY_LEFTCTRL),
 	KEY(0, 1, KEY_1),
 	KEY(0, 2, KEY_3),
@@ -330,37 +363,48 @@ static const uint32_t spitzkbd_keymap[] = {
 	KEY(6, 8, KEY_RIGHT),
 };
 
-static const struct matrix_keymap_data spitzkbd_keymap_data = {
-	.keymap		= spitzkbd_keymap,
-	.keymap_size	= ARRAY_SIZE(spitzkbd_keymap),
+static const struct matrix_keymap_data sharpslc_keymap_data = {
+	.keymap		= sharpslc_keymap,
+	.keymap_size	= ARRAY_SIZE(sharpslc_keymap),
 };
 
-static const uint32_t spitzkbd_row_gpios[] =
+static const uint32_t sharpslc_row_gpios[] =
 		{ 12, 17, 91, 34, 36, 38, 39 };
-static const uint32_t spitzkbd_col_gpios[] =
+static const uint32_t sharpslc_col_gpios[] =
 		{ 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 };
 
-static struct matrix_keypad_platform_data spitzkbd_pdata = {
-	.keymap_data		= &spitzkbd_keymap_data,
-	.row_gpios		= spitzkbd_row_gpios,
-	.col_gpios		= spitzkbd_col_gpios,
-	.num_row_gpios		= ARRAY_SIZE(spitzkbd_row_gpios),
-	.num_col_gpios		= ARRAY_SIZE(spitzkbd_col_gpios),
+static struct matrix_keypad_platform_data sharpslc_mkp_pdata = {
+	.keymap_data		= &sharpslc_keymap_data,
+	.row_gpios		= sharpslc_row_gpios,
+	.col_gpios		= sharpslc_col_gpios,
+	.num_row_gpios		= ARRAY_SIZE(sharpslc_row_gpios),
+	.num_col_gpios		= ARRAY_SIZE(sharpslc_col_gpios),
 	.col_scan_delay_us	= 10,
 	.debounce_ms		= 10,
 	.wakeup			= 1,
 };
 
-static struct platform_device spitzkbd_device = {
+static struct platform_device sharpslc_mkp_device = {
 	.name		= "matrix-keypad",
 	.id		= -1,
 	.dev		= {
-		.platform_data = &spitzkbd_pdata,
+		.platform_data	= &sharpslc_mkp_pdata,
 	},
 };
 
+static void __init sharpslc_mkp_init(void)
+{
+	platform_device_register(&sharpslc_mkp_device);
+}
+#else
+static inline void sharpslc_mkp_init(void) {}
+#endif
 
-static struct gpio_keys_button spitz_gpio_keys[] = {
+/******************************************************************************
+ * GPIO keys
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button sharpslc_gpio_keys[] = {
 	{
 		.type	= EV_PWR,
 		.code	= KEY_SUSPEND,
@@ -383,27 +427,35 @@ static struct gpio_keys_button spitz_gpio_keys[] = {
 	},
 };
 
-static struct gpio_keys_platform_data spitz_gpio_keys_platform_data = {
-	.buttons	= spitz_gpio_keys,
-	.nbuttons	= ARRAY_SIZE(spitz_gpio_keys),
+static struct gpio_keys_platform_data sharpslc_gpio_keys_platform_data = {
+	.buttons	= sharpslc_gpio_keys,
+	.nbuttons	= ARRAY_SIZE(sharpslc_gpio_keys),
 };
 
-static struct platform_device spitz_gpio_keys_device = {
+static struct platform_device sharpslc_gpio_keys_device = {
 	.name	= "gpio-keys",
 	.id	= -1,
 	.dev	= {
-		.platform_data	= &spitz_gpio_keys_platform_data,
+		.platform_data	= &sharpslc_gpio_keys_platform_data,
 	},
 };
 
+static void __init sharpslc_keys_init(void)
+{
+	platform_device_register(&sharpslc_gpio_keys_device);
+}
+#else
+static inline void sharpslc_keys_init(void) {}
+#endif
 
-/*
- * Spitz LEDs
- */
-static struct gpio_led spitz_gpio_leds[] = {
+/******************************************************************************
+ * LEDs
+ ******************************************************************************/
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static struct gpio_led sharpslc_gpio_leds[] = {
 	{
 		.name			= "spitz:amber:charge",
-		.default_trigger	= "sharpsl-charge",
+		.default_trigger	= "sharpslc-charge",
 		.gpio			= SPITZ_GPIO_LED_ORANGE,
 	},
 	{
@@ -413,25 +465,32 @@ static struct gpio_led spitz_gpio_leds[] = {
 	},
 };
 
-static struct gpio_led_platform_data spitz_gpio_leds_info = {
-	.leds		= spitz_gpio_leds,
-	.num_leds	= ARRAY_SIZE(spitz_gpio_leds),
+static struct gpio_led_platform_data sharpslc_gpio_leds_info = {
+	.leds		= sharpslc_gpio_leds,
+	.num_leds	= ARRAY_SIZE(sharpslc_gpio_leds),
 };
 
-static struct platform_device spitzled_device = {
+static struct platform_device sharpslc_led_device = {
 	.name		= "leds-gpio",
 	.id		= -1,
 	.dev		= {
-		.platform_data = &spitz_gpio_leds_info,
+		.platform_data	= &sharpslc_gpio_leds_info,
 	},
 };
 
-#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_master spitz_spi_info = {
-	.num_chipselect	= 3,
-};
+static void __init sharpslc_leds_init(void)
+{
+	platform_device_register(&sharpslc_led_device);
+}
+#else
+static inline void sharpslc_leds_init(void) {}
+#endif
 
-static void spitz_wait_for_hsync(void)
+/******************************************************************************
+ * SSP Devices
+ ******************************************************************************/
+#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
+static void sharpslc_ads7846_wait_for_hsync(void)
 {
 	while (gpio_get_value(SPITZ_GPIO_HSYNC))
 		cpu_relax();
@@ -440,21 +499,21 @@ static void spitz_wait_for_hsync(void)
 		cpu_relax();
 }
 
-static struct ads7846_platform_data spitz_ads7846_info = {
+static struct ads7846_platform_data sharpslc_ads7846_info = {
 	.model			= 7846,
 	.vref_delay_usecs	= 100,
 	.x_plate_ohms		= 419,
 	.y_plate_ohms		= 486,
 	.pressure_max		= 1024,
 	.gpio_pendown		= SPITZ_GPIO_TP_INT,
-	.wait_for_sync		= spitz_wait_for_hsync,
+	.wait_for_sync		= sharpslc_ads7846_wait_for_hsync,
 };
 
-static struct pxa2xx_spi_chip spitz_ads7846_chip = {
+static struct pxa2xx_spi_chip sharpslc_ads7846_chip = {
 	.gpio_cs		= SPITZ_GPIO_ADS7846_CS,
 };
 
-static void spitz_bl_kick_battery(void)
+static void sharpslc_bl_kick_battery(void)
 {
 	void (*kick_batt)(void);
 
@@ -465,93 +524,109 @@ static void spitz_bl_kick_battery(void)
 	}
 }
 
-static struct corgi_lcd_platform_data spitz_lcdcon_info = {
+static struct corgi_lcd_platform_data sharpslc_lcdcon_info = {
 	.init_mode		= CORGI_LCD_MODE_VGA,
 	.max_intensity		= 0x2f,
 	.default_intensity	= 0x1f,
 	.limit_mask		= 0x0b,
 	.gpio_backlight_cont	= SPITZ_GPIO_BACKLIGHT_CONT,
 	.gpio_backlight_on	= SPITZ_GPIO_BACKLIGHT_ON,
-	.kick_battery		= spitz_bl_kick_battery,
+	.kick_battery		= sharpslc_bl_kick_battery,
 };
 
-static struct pxa2xx_spi_chip spitz_lcdcon_chip = {
+static struct pxa2xx_spi_chip sharpslc_lcdcon_chip = {
 	.gpio_cs	= SPITZ_GPIO_LCDCON_CS,
 };
 
-static struct pxa2xx_spi_chip spitz_max1111_chip = {
+static struct pxa2xx_spi_chip sharpslc_max1111_chip = {
 	.gpio_cs	= SPITZ_GPIO_MAX1111_CS,
 };
 
-static struct spi_board_info spitz_spi_devices[] = {
+static struct spi_board_info sharpslc_spi_devices[] = {
 	{
-		.modalias	= "ads7846",
-		.max_speed_hz	= 1200000,
-		.bus_num	= 2,
-		.chip_select	= 0,
-		.platform_data	= &spitz_ads7846_info,
-		.controller_data= &spitz_ads7846_chip,
-		.irq		= gpio_to_irq(SPITZ_GPIO_TP_INT),
+		.modalias		= "ads7846",
+		.max_speed_hz		= 1200000,
+		.bus_num		= 2,
+		.chip_select		= 0,
+		.platform_data		= &sharpslc_ads7846_info,
+		.controller_data	= &sharpslc_ads7846_chip,
+		.irq			= gpio_to_irq(SPITZ_GPIO_TP_INT),
 	}, {
-		.modalias	= "corgi-lcd",
-		.max_speed_hz	= 50000,
-		.bus_num	= 2,
-		.chip_select	= 1,
-		.platform_data	= &spitz_lcdcon_info,
-		.controller_data= &spitz_lcdcon_chip,
+		.modalias		= "corgi-lcd",
+		.max_speed_hz		= 50000,
+		.bus_num		= 2,
+		.chip_select		= 1,
+		.platform_data		= &sharpslc_lcdcon_info,
+		.controller_data	= &sharpslc_lcdcon_chip,
 	}, {
-		.modalias	= "max1111",
-		.max_speed_hz	= 450000,
-		.bus_num	= 2,
-		.chip_select	= 2,
-		.controller_data= &spitz_max1111_chip,
+		.modalias		= "max1111",
+		.max_speed_hz		= 450000,
+		.bus_num		= 2,
+		.chip_select		= 2,
+		.controller_data	= &sharpslc_max1111_chip,
 	},
 };
 
-static void __init spitz_init_spi(void)
+static struct pxa2xx_spi_master sharpslc_spi_info = {
+	.num_chipselect	= 3,
+};
+
+static void __init sharpslc_spi_init(void)
 {
+	struct corgi_lcd_platform_data *lcd_data = &sharpslc_lcdcon_info;
+
 	if (machine_is_akita()) {
-		spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
-		spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
+		lcd_data->gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
+		lcd_data->gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
 	}
 
-	pxa2xx_set_spi_info(2, &spitz_spi_info);
-	spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
+	pxa2xx_set_spi_info(2, &sharpslc_spi_info);
+	spi_register_board_info(ARRAY_AND_SIZE(sharpslc_spi_devices));
 }
 #else
-static inline void spitz_init_spi(void) {}
+static inline void sharpslc_spi_init(void) {}
 #endif
 
+/******************************************************************************
+ * SD/MMC card controller
+ ******************************************************************************/
+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
 /*
- * MMC/SD Device
- *
- * The card detect interrupt isn't debounced so we delay it by 250ms
- * to give the card a chance to fully insert/eject.
+ * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
+ * give the card a chance to fully insert/eject.
  */
-static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
+static void sharpslc_mci_setpower(struct device *dev, unsigned int vdd)
 {
 	struct pxamci_platform_data* p_d = dev->platform_data;
 
-	if (( 1 << vdd) & p_d->ocr_mask)
-		spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0004);
+	if ((1 << vdd) & p_d->ocr_mask)
+		sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
 	else
-		spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0000);
+		sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
 }
 
-static struct pxamci_platform_data spitz_mci_platform_data = {
+static struct pxamci_platform_data sharpslc_mci_platform_data = {
 	.detect_delay_ms	= 250,
 	.ocr_mask		= MMC_VDD_32_33|MMC_VDD_33_34,
-	.setpower 		= spitz_mci_setpower,
+	.setpower		= sharpslc_mci_setpower,
 	.gpio_card_detect	= SPITZ_GPIO_nSD_DETECT,
 	.gpio_card_ro		= SPITZ_GPIO_nSD_WP,
 	.gpio_power		= -1,
 };
 
+static void __init sharpslc_mmc_init(void)
+{
+	pxa_set_mci_info(&sharpslc_mci_platform_data);
+}
+#else
+static inline void sharpslc_mmc_init(void) {}
+#endif
 
-/*
- * USB Host (OHCI)
- */
-static int spitz_ohci_init(struct device *dev)
+/******************************************************************************
+ * USB Host
+ ******************************************************************************/
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static int sharpslc_ohci_init(struct device *dev)
 {
 	int err;
 
@@ -559,88 +634,114 @@ static int spitz_ohci_init(struct device *dev)
 	if (err)
 		return err;
 
-	/* Only Port 2 is connected
-	 * Setup USB Port 2 Output Control Register
-	 */
+	/* Only Port 2 is connected, setup USB Port 2 Output Control Register */
 	UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
 
 	return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1);
 }
 
-static void spitz_ohci_exit(struct device *dev)
+static void sharpslc_ohci_exit(struct device *dev)
 {
 	gpio_free(SPITZ_GPIO_USB_HOST);
 }
 
-static struct pxaohci_platform_data spitz_ohci_platform_data = {
+static struct pxaohci_platform_data sharpslc_ohci_platform_data = {
 	.port_mode	= PMM_NPS_MODE,
-	.init		= spitz_ohci_init,
-	.exit		= spitz_ohci_exit,
+	.init		= sharpslc_ohci_init,
+	.exit		= sharpslc_ohci_exit,
 	.flags		= ENABLE_PORT_ALL | NO_OC_PROTECTION,
 	.power_budget	= 150,
 };
 
+static void __init sharpslc_uhc_init(void)
+{
+	pxa_set_ohci_info(&sharpslc_ohci_platform_data);
+}
+#else
+static inline void sharpslc_uhc_init(void) {}
+#endif
 
-/*
- * Irda
- */
-
-static struct pxaficp_platform_data spitz_ficp_platform_data = {
-/* .gpio_pwdown is set in spitz_init() and akita_init() accordingly */
+/******************************************************************************
+ * IrDA
+ ******************************************************************************/
+#if defined(CONFIG_PXA_FICP) || defined(CONFIG_PXA_FICP_MODULE)
+static struct pxaficp_platform_data sharpslc_ficp_platform_data = {
 	.transceiver_cap	= IR_SIRMODE | IR_OFF,
 };
 
+static void __init sharpslc_irda_init(void)
+{
+	if (machine_is_akita())
+		sharpslc_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
+	else
+		sharpslc_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
 
-/*
- * Spitz PXA Framebuffer
- */
+	pxa_set_ficp_info(&sharpslc_ficp_platform_data);
+}
+#else
+static inline void sharpslc_irda_init(void) {}
+#endif
 
-static struct pxafb_mode_info spitz_pxafb_modes[] = {
-{
-	.pixclock       = 19231,
-	.xres           = 480,
-	.yres           = 640,
-	.bpp            = 16,
-	.hsync_len      = 40,
-	.left_margin    = 46,
-	.right_margin   = 125,
-	.vsync_len      = 3,
-	.upper_margin   = 1,
-	.lower_margin   = 0,
-	.sync           = 0,
-},{
-	.pixclock       = 134617,
-	.xres           = 240,
-	.yres           = 320,
-	.bpp            = 16,
-	.hsync_len      = 20,
-	.left_margin    = 20,
-	.right_margin   = 46,
-	.vsync_len      = 2,
-	.upper_margin   = 1,
-	.lower_margin   = 0,
-	.sync           = 0,
-},
-};
-
-static struct pxafb_mach_info spitz_pxafb_info = {
-	.modes          = &spitz_pxafb_modes[0],
-	.num_modes      = 2,
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static struct pxafb_mode_info sharpslc_pxafb_modes[] = {
+	{
+		.pixclock       = 19231,
+		.xres           = 480,
+		.yres           = 640,
+		.bpp            = 16,
+		.hsync_len      = 40,
+		.left_margin    = 46,
+		.right_margin   = 125,
+		.vsync_len      = 3,
+		.upper_margin   = 1,
+		.lower_margin   = 0,
+		.sync           = 0,
+	}, {
+		.pixclock       = 134617,
+		.xres           = 240,
+		.yres           = 320,
+		.bpp            = 16,
+		.hsync_len      = 20,
+		.left_margin    = 20,
+		.right_margin   = 46,
+		.vsync_len      = 2,
+		.upper_margin   = 1,
+		.lower_margin   = 0,
+		.sync           = 0,
+	},
+};
+
+static struct pxafb_mach_info sharpslc_pxafb_info = {
+	.modes          = sharpslc_pxafb_modes,
+	.num_modes      = ARRAY_SIZE(sharpslc_pxafb_modes),
 	.fixed_modes    = 1,
 	.lcd_conn	= LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
 };
 
-static struct mtd_partition sharpsl_nand_partitions[] = {
+static void __init sharpslc_lcd_init(void)
+{
+	set_pxa_fb_info(&sharpslc_pxafb_info);
+}
+#else
+static inline void sharpslc_lcd_init(void) {}
+#endif
+
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+#if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE)
+static struct mtd_partition sharpslc_nand_partitions[] = {
 	{
 		.name = "System Area",
 		.offset = 0,
 		.size = 7 * 1024 * 1024,
-	},
-	{
+	}, {
 		.name = "Root Filesystem",
 		.offset = 7 * 1024 * 1024,
-	},
-	{
+	}, {
 		.name = "Home Filesystem",
 		.offset = MTDPART_OFS_APPEND,
 		.size = MTDPART_SIZ_FULL,
@@ -649,37 +750,72 @@ static struct mtd_partition sharpsl_nand_partitions[] = {
 
 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
 
-static struct nand_bbt_descr sharpsl_bbt = {
-	.options = 0,
-	.offs = 4,
-	.len = 2,
-	.pattern = scan_ff_pattern
+static struct nand_bbt_descr sharpslc_nand_bbt = {
+	.options	= 0,
+	.offs		= 4,
+	.len		= 2,
+	.pattern	= scan_ff_pattern
+};
+
+static struct nand_ecclayout sharpslc_akita_oobinfo = {
+	.oobfree	= { {0x08, 0x09} },
+	.eccbytes	= 24,
+	.eccpos		= {
+			0x05, 0x01, 0x02, 0x03, 0x06, 0x07, 0x15, 0x11,
+			0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
+			0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37,
+	},
 };
 
-static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
-	.badblock_pattern	= &sharpsl_bbt,
-	.partitions		= sharpsl_nand_partitions,
-	.nr_partitions		= ARRAY_SIZE(sharpsl_nand_partitions),
+static struct sharpsl_nand_platform_data sharpslc_nand_pdata = {
+	.badblock_pattern	= &sharpslc_nand_bbt,
+	.partitions		= sharpslc_nand_partitions,
+	.nr_partitions		= ARRAY_SIZE(sharpslc_nand_partitions),
 };
 
-static struct resource sharpsl_nand_resources[] = {
+static struct resource sharpslc_nand_resources[] = {
 	{
-		.start	= 0x0C000000,
-		.end	= 0x0C000FFF,
+		.start	= PXA_CS3_PHYS,
+		.end	= PXA_CS3_PHYS + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 
-static struct platform_device sharpsl_nand_device = {
+static struct platform_device sharpslc_nand_device = {
 	.name		= "sharpsl-nand",
 	.id		= -1,
-	.resource	= sharpsl_nand_resources,
-	.num_resources	= ARRAY_SIZE(sharpsl_nand_resources),
-	.dev.platform_data	= &sharpsl_nand_platform_data,
+	.resource	= sharpslc_nand_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_nand_resources),
+	.dev		= {
+		.platform_data	= &sharpslc_nand_pdata,
+	}
 };
 
+static void __init sharpslc_nand_init(void)
+{
+	if (machine_is_spitz()) {
+		sharpslc_nand_partitions[1].size = 5 * 1024 * 1024;
+	} else if (machine_is_akita()) {
+		sharpslc_nand_partitions[1].size = 58 * 1024 * 1024;
+		sharpslc_nand_bbt.len = 1;
+		sharpslc_nand_pdata.ecc_layout = &sharpslc_akita_oobinfo;
+	} else if (machine_is_borzoi()) {
+		sharpslc_nand_partitions[1].size = 32 * 1024 * 1024;
+		sharpslc_nand_bbt.len = 1;
+		sharpslc_nand_pdata.ecc_layout = &sharpslc_akita_oobinfo;
+	}
+
+	platform_device_register(&sharpslc_nand_device);
+}
+#else
+static inline void sharpslc_nand_init(void) {}
+#endif
 
-static struct mtd_partition sharpsl_rom_parts[] = {
+/******************************************************************************
+ * NOR Flash
+ ******************************************************************************/
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition sharpslc_rom_parts[] = {
 	{
 		.name	="Boot PROM Filesystem",
 		.offset	= 0x00140000,
@@ -687,158 +823,152 @@ static struct mtd_partition sharpsl_rom_parts[] = {
 	},
 };
 
-static struct physmap_flash_data sharpsl_rom_data = {
+static struct physmap_flash_data sharpslc_rom_data = {
 	.width		= 2,
-	.nr_parts	= ARRAY_SIZE(sharpsl_rom_parts),
-	.parts		= sharpsl_rom_parts,
+	.nr_parts	= ARRAY_SIZE(sharpslc_rom_parts),
+	.parts		= sharpslc_rom_parts,
 };
 
-static struct resource sharpsl_rom_resources[] = {
+static struct resource sharpslc_rom_resources[] = {
 	{
-		.start	= 0x00000000,
-		.end	= 0x007fffff,
+		.start	= PXA_CS0_PHYS,
+		.end	= PXA_CS0_PHYS + SZ_8M - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 
-static struct platform_device sharpsl_rom_device = {
-	.name	= "physmap-flash",
-	.id	= -1,
-	.resource = sharpsl_rom_resources,
-	.num_resources = ARRAY_SIZE(sharpsl_rom_resources),
-	.dev.platform_data = &sharpsl_rom_data,
-};
-
-static struct platform_device *devices[] __initdata = {
-	&spitzscoop_device,
-	&spitzkbd_device,
-	&spitz_gpio_keys_device,
-	&spitzled_device,
-	&sharpsl_nand_device,
-	&sharpsl_rom_device,
+static struct platform_device sharpslc_rom_device = {
+	.name		= "physmap-flash",
+	.id		= -1,
+	.resource	= sharpslc_rom_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_rom_resources),
+	.dev		= {
+		.platform_data	= &sharpslc_rom_data,
+	},
 };
 
-static void spitz_poweroff(void)
+static void __init sharpslc_nor_init(void)
 {
-	arm_machine_restart('g', NULL);
+	platform_device_register(&sharpslc_rom_device);
 }
+#else
+static inline void sharpslc_nor_init(void) {}
+#endif
 
-static void spitz_restart(char mode, const char *cmd)
-{
-	/* Bootloader magic for a reboot */
-	if((MSC0 & 0xffff0000) == 0x7ff00000)
-		MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
-
-	spitz_poweroff();
-}
+/******************************************************************************
+ * GPIO expander
+ ******************************************************************************/
+#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
+static struct pca953x_platform_data akita_pca953x_pdata = {
+	.gpio_base		= AKITA_IOEXP_GPIO_BASE,
+};
 
-static void __init common_init(void)
-{
-	init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
-	pm_power_off = spitz_poweroff;
-	arm_pm_restart = spitz_restart;
+static struct i2c_board_info sharpslc_i2c_devs[] = {
+	{
+		.type		= "wm8750",
+		.addr		= 0x1b,
+	}, {
+		.type		= "max7310",
+		.addr		= 0x18,
+		.platform_data	= &akita_pca953x_pdata,
+	},
+};
 
-	if (machine_is_spitz()) {
-		sharpsl_nand_partitions[1].size = 5 * 1024 * 1024;
-	} else if (machine_is_akita()) {
-		sharpsl_nand_partitions[1].size = 58 * 1024 * 1024;
-	} else if (machine_is_borzoi()) {
-		sharpsl_nand_partitions[1].size = 32 * 1024 * 1024;
+static struct regulator_consumer_supply isl6271a_consumers[] = {
+	{
+		.supply	= "vcc_core",
 	}
+};
 
-	PMCR = 0x00;
-
-	/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
-	PCFR |= PCFR_OPDE;
+static struct regulator_init_data isl6271a_info[] = {
+	{
+		.constraints = {
+			.name		= "vcc_core range",
+			.min_uV		= 850000,
+			.max_uV		= 1600000,
+			.always_on	= 1,
+			.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		},
+	.consumer_supplies	= isl6271a_consumers,
+	.num_consumer_supplies	= ARRAY_SIZE(isl6271a_consumers),
+	}
+};
 
-	pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
+static struct i2c_board_info sharpslc_pi2c_devs[] = {
+	{
+		.type		= "isl6271a",
+		.addr		= 0x0c,
+		.platform_data	= &isl6271a_info,
+	},
+};
 
-	pxa_set_ffuart_info(NULL);
-	pxa_set_btuart_info(NULL);
-	pxa_set_stuart_info(NULL);
+static void __init sharpslc_i2c_init(void)
+{
+	int size = ARRAY_SIZE(sharpslc_i2c_devs);
 
-	spitz_init_spi();
+	/* Only Akita has the max7310 chip */
+	if (!machine_is_akita())
+		size--;
 
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	pxa_set_mci_info(&spitz_mci_platform_data);
-	pxa_set_ohci_info(&spitz_ohci_platform_data);
-	pxa_set_ficp_info(&spitz_ficp_platform_data);
-	set_pxa_fb_info(&spitz_pxafb_info);
 	pxa_set_i2c_info(NULL);
+	pxa27x_set_i2c_power_info(NULL);
+	i2c_register_board_info(0, sharpslc_i2c_devs, size);
+	i2c_register_board_info(1, ARRAY_AND_SIZE(sharpslc_pi2c_devs));
 }
-
-#if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI)
-static struct nand_bbt_descr sharpsl_akita_bbt = {
-	.options = 0,
-	.offs = 4,
-	.len = 1,
-	.pattern = scan_ff_pattern
-};
-
-static struct nand_ecclayout akita_oobinfo = {
-	.eccbytes = 24,
-	.eccpos = {
-		   0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
-		   0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
-		   0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
-	.oobfree = {{0x08, 0x09}}
-};
+#else
+static inline void sharpslc_i2c_init(void) {}
 #endif
 
-#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
-static void __init spitz_init(void)
+/******************************************************************************
+ * Machine init
+ ******************************************************************************/
+static void sharpslc_poweroff(void)
 {
-	spitz_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
-
-#ifdef CONFIG_MACH_BORZOI
-	if (machine_is_borzoi()) {
-		sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
-		sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
-	}
-#endif
-
-	platform_scoop_config = &spitz_pcmcia_config;
-
-	common_init();
-
-	platform_device_register(&spitzscoop2_device);
+	arm_machine_restart('g', NULL);
 }
-#endif
 
-#ifdef CONFIG_MACH_AKITA
-/*
- * Akita IO Expander
- */
-static struct pca953x_platform_data akita_ioexp = {
-	.gpio_base		= AKITA_IOEXP_GPIO_BASE,
-};
+static void sharpslc_restart(char mode, const char *cmd)
+{
+	/* Bootloader magic for a reboot */
+	if ((MSC0 & 0xffff0000) == 0x7ff00000)
+		MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
 
-static struct i2c_board_info akita_i2c_board_info[] = {
-	{
-		.type		= "max7310",
-		.addr		= 0x18,
-		.platform_data	= &akita_ioexp,
-	},
-};
+	sharpslc_poweroff();
+}
 
-static void __init akita_init(void)
+static void __init sharpslc_init(void)
 {
-	spitz_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
+	init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
+	pm_power_off = sharpslc_poweroff;
+	arm_pm_restart = sharpslc_restart;
 
-	sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
-	sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
+	PMCR = 0x00;
 
-	/* We just pretend the second element of the array doesn't exist */
-	spitz_pcmcia_config.num_devs = 1;
-	platform_scoop_config = &spitz_pcmcia_config;
+	/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
+	PCFR |= PCFR_OPDE;
 
-	i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_board_info));
+	pxa2xx_mfp_config(ARRAY_AND_SIZE(sharpslc_pin_config));
 
-	common_init();
+	pxa_set_ffuart_info(NULL);
+	pxa_set_btuart_info(NULL);
+	pxa_set_stuart_info(NULL);
+
+	sharpslc_spi_init();
+	sharpslc_scoop_init();
+	sharpslc_mkp_init();
+	sharpslc_keys_init();
+	sharpslc_leds_init();
+	sharpslc_mmc_init();
+	sharpslc_pcmcia_init();
+	sharpslc_irda_init();
+	sharpslc_uhc_init();
+	sharpslc_lcd_init();
+	sharpslc_nor_init();
+	sharpslc_nand_init();
+	sharpslc_i2c_init();
 }
-#endif
 
-static void __init fixup_spitz(struct machine_desc *desc,
+static void __init sharpslc_fixup(struct machine_desc *desc,
 		struct tag *tags, char **cmdline, struct meminfo *mi)
 {
 	sharpsl_save_param();
@@ -852,10 +982,10 @@ static void __init fixup_spitz(struct machine_desc *desc,
 MACHINE_START(SPITZ, "SHARP Spitz")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= spitz_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
@@ -864,10 +994,10 @@ MACHINE_END
 MACHINE_START(BORZOI, "SHARP Borzoi")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= spitz_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
@@ -876,10 +1006,10 @@ MACHINE_END
 MACHINE_START(AKITA, "SHARP Akita")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= akita_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
-- 
1.7.1



From herman_swartz at yahoo.com  Thu Jun 10 17:13:57 2010
From: herman_swartz at yahoo.com (Herman Swartz)
Date: Thu, 10 Jun 2010 14:13:57 -0700 (PDT)
Subject: Fw: Context Switching is Broken
In-Reply-To: <4C114200.6030307@fifthhorseman.net>
References: <121634.13810.qm@web51801.mail.re2.yahoo.com>
	<4C110181.6000109@fifthhorseman.net>
	<4C110600.4050808@telefonica.net>
	<4C114200.6030307@fifthhorseman.net>
Message-ID: <468524.82182.qm@web51805.mail.re2.yahoo.com>





----- Forwarded Message ----
From: Herman Swartz <herman_swartz at yahoo.com>
To: debian-arm at lists.debian.org
Sent: Thu, June 10, 2010 5:12:35 PM
Subject: Re: Context Switching is Broken

Hi,

I was having trouble getting to the list so did not immediately put in details until now.

------------- From dmesg to show my cpu.

[??? 0.000000] Initializing cgroup subsys cpuset
[??? 0.000000] Initializing cgroup subsys cpu
[??? 0.000000] Linux version 2.6.32-trunk-kirkwood (Debian 2.6.32-5) (ben at decadent.org.uk) (gcc version 4.3.4 (Debian 4.3.4-6) ) #1 Mon Jan 11 10:57:12 UTC 2010
[??? 0.000000] CPU: Feroceon 88FR131 [56251311] revision 1 (ARMv5TE), cr=00053977
[??? 0.000000] CPU: VIVT data cache, VIVT instruction cache
[??? 0.000000] Machine: Marvell SheevaPlug Reference Board
[??? 0.000000] Memory policy: ECC disabled, Data cache writeback
[??? 0.000000] On node 0 totalpages: 131072
[??? 0.000000] free_area_init_node: node 0, pgdat c03d0904, node_mem_map c0dbc000
[??? 0.000000]?? Normal zone: 1024 pages used for memmap
[??? 0.000000]?? Normal zone: 0 pages reserved
[??? 0.000000]?? Normal zone: 130048 pages, LIFO batch:31
[??? 0.000000] Built 1 zonelists in Zone order, mobility grouping on.? Total pages: 130048

---------- Tail end of make output

/home/gpetrov/jnos2/ksubr.c:31: warning: warning: getcontext is not implemented and will always fail
net.a(kernel.o): In function `pwait':
/home/gpetrov/jnos2/kernel.c:346: warning: warning: setcontext is not implemented and will always fail
net.a(ksubr.o): In function `psetup':
/home/gpetrov/jnos2/ksubr.c:166: warning: warning: makecontext is not implemented and will always fail
net.a(kernel.o): In function `pwait':
/home/gpetrov/jnos2/kernel.c:348: warning: warning: swapcontext is not implemented and will always fail

----------- directories where library files are located

debian:/home/gpetrov/Ctest# find / -name "ucontext.h"
/usr/include/asm-generic/ucontext.h
/usr/include/ucontext.h
/usr/include/sys/ucontext.h
debian:/home/gpetrov/Ctest#

------- from one of the ucontext.h library files above...

debian:/usr/include# ls ucontext.h
ucontext.h
debian:/usr/include# less ucontext.h
/* Get user context and store it in variable pointed to by UCP.? */
extern int getcontext (ucontext_t *__ucp) __THROW;
/* Set user context from information of variable pointed to by UCP.? */
extern int setcontext (__const ucontext_t *__ucp) __THROW;
/* Save current context in context variable pointed to by OUCP and set
?? context from variable pointed to by UCP.? */
extern int swapcontext (ucontext_t *__restrict __oucp,
??????????????????????? __const ucontext_t *__restrict __ucp) __THROW;
/* Manipulate user context UCP to continue with calling functions FUNC
?? and the ARGC-1 parameters following ARGC when the context is used
?? the next time in `setcontext' or `swapcontext'.
?? We cannot say anything about the parameters FUNC takes; `void'
?? is as good as any other choice.? */
extern void makecontext (ucontext_t *__ucp, void (*__func) (void),
???????????????????????? int __argc, ...) __THROW;
__END_DECLS
#endif /* ucontext.h */


Does the CPU support context switching, from looking around I think it does since there is an addon for improving context switching performance of this model of ARM processor.

JNOS application developer believes there is no support for context switching. Seems to be a kernel issue to me but maybe the make is not finding the library files??

What do you think?

Thanks
Herman



----- Original Message ----
From: Daniel Kahn Gillmor <dkg at fifthhorseman.net>
To: Xan <dxpublica at telefonica.net>
Cc: debian-arm at lists.debian.org; Herman Swartz <herman_swartz at yahoo.com>
Sent: Thu, June 10, 2010 3:50:24 PM
Subject: Re: Context Switching is Broken

On 06/10/2010 11:34 AM, Xan wrote:
> Maybe you refer to texexec. Try "man texexec". Does it work?

I also do not have a texexec manual page.? Is this related to ARM on debian?

Could you try being more explicit about exactly what you're doing, what
you expect to happen, and what is actually happening?

??? --dkg


      


From mcuelenaere at gmail.com  Fri Jun 11 05:01:18 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 11:01:18 +0200
Subject: [PATCH 10/11] USB: s3c-hsotg: Fix the OUT EP0 limit
In-Reply-To: <1276244457-4072-11-git-send-email-ben-linux@fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
	<1276244457-4072-11-git-send-email-ben-linux@fluff.org>
Message-ID: <4C11FB5E.8060106@gmail.com>




Op 11-06-10 10:20, Ben Dooks schreef:
> The EP0 out limit is the same as the IN limit, so make them the same.
> 
> Signed-off-by: Ben Dooks <ben-linux-elnMNo+KYs3YtjvyW6yDsg at public.gmane.org>
> 
> tmp-fix

Shouldn't this line be removed?

> ---
>  drivers/usb/gadget/s3c-hsotg.c |    3 +--
>  1 files changed, 1 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
> index 17b0779..b34a05d 100644
> --- a/drivers/usb/gadget/s3c-hsotg.c
> +++ b/drivers/usb/gadget/s3c-hsotg.c
> @@ -612,11 +612,10 @@ static unsigned get_ep_limit(struct s3c_hsotg_ep *hs_ep)
>  		maxsize = S3C_DxEPTSIZ_XferSize_LIMIT + 1;
>  		maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
>  	} else {
> +		maxsize = 64+64;
>  		if (hs_ep->dir_in) {
> -			maxsize = 64+64;
>  			maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
>  		} else {
> -			maxsize = 0x3f;
>  			maxpkt = 2;
>  		}
>  	}





From mcuelenaere at gmail.com  Fri Jun 11 15:49:21 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 21:49:21 +0200
Subject: [RFC 9/9] crypto: Add Samsung crypto engine driver
In-Reply-To: <cover.1276284559.git.mcuelenaere@gmail.com>
References: <cover.1276284559.git.mcuelenaere@gmail.com>
Message-ID: <4C129341.2060407@gmail.com>

This patch adds support for the Samsung crypto engine driver available in the
S3C64XX and S5PC100 SoCs. Currently this supports AES and (T)DES with ECB and
CBC block ciphers (also CTR for AES). Support for (HMAC)-SHA1 acceleration is
also available in this engine, but isn't used in the driver yet.

Support for DMA has been added in the code but is currently disabled due to
issues with data transfers.

Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
---
 drivers/crypto/Kconfig   |   11 +
 drivers/crypto/Makefile  |    1 +
 drivers/crypto/s3c-sss.c | 1320 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 1332 insertions(+), 0 deletions(-)
 create mode 100644 drivers/crypto/s3c-sss.c

diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index b08403d..597a151 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -222,4 +222,15 @@ config CRYPTO_DEV_PPC4XX
 	help
 	  This option allows you to have support for AMCC crypto acceleration.
 
+config CRYPTO_DEV_SSS
+	tristate "Samsung Security Sub-Systems"
+	depends on SAMSUNG_DEV_SSS
+	select CRYPTO_ALGAPI
+	select CRYPTO_BLKCIPHER
+	select CRYPTO_DES
+	select CRYPTO_HASH
+	help
+	    This driver utilizes the cryptographic engine in Samsung S3C64XX
+	    and S5PC100 SoCs.
+
 endif # CRYPTO_HW
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 6ffcb3f..ef14b4d 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_CRYPTO_DEV_MV_CESA) += mv_cesa.o
 obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
 obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
 obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
+obj-$(CONFIG_CRYPTO_DEV_SSS) += s3c-sss.o
diff --git a/drivers/crypto/s3c-sss.c b/drivers/crypto/s3c-sss.c
new file mode 100644
index 0000000..9fd5288
--- /dev/null
+++ b/drivers/crypto/s3c-sss.c
@@ -0,0 +1,1320 @@
+/*
+ * linux/drivers/crypto/s3c-sss.c
+ *
+ * Copyright (C) 2010 Maurus Cuelenaere
+ *
+ * Support for S3C64XX Security Sub-Systems
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/*#define DEBUG*/
+
+#include <linux/clk.h>
+#include <linux/crypto.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/timer.h>
+
+#include <crypto/internal/hash.h>
+#include <crypto/algapi.h>
+#include <crypto/aes.h>
+#include <crypto/ctr.h>
+#include <crypto/des.h>
+#include <crypto/sha.h>
+#include <crypto/scatterwalk.h>
+
+#include <mach/dma.h>
+
+#include <plat/regs-sss.h>
+
+#define SSS_CRA_PRIORITY	300
+#define SSS_MAX_KEY_SIZE	AES_MAX_KEY_SIZE
+#define SSS_FIFO_SIZE		0x40U
+#define SSS_TIMEOUT		(3*HZ)
+
+/**
+ * struct s3c_sss - driver state.
+ * @dev: pointer to the device struct
+ * @clock: clock associated with peripheral
+ * @irq: irq associated with peripheral
+ * @regs: pointer to mapped registers
+ * @regs_phys: pointer to physical address of registers
+ * @regs_res: pointer to struct resource representing registers
+ * @cur_req: pointer to pending request (NULL indicates no current request)
+ * @dma_client: struct used for passing to DMA core
+ * @lock: lock used for synchronizing queue accesses
+ * @tasklet: tasklet doing the main work
+ * @timer: timer used for timing out faulty requests
+ * @queue: queue containing requests
+ */
+struct s3c_sss {
+	struct device			*dev;
+
+	struct clk			*clock;
+	int				irq;
+	void __iomem			*regs;
+	void __iomem			*regs_phys;
+	struct resource			*regs_res;
+
+	struct ablkcipher_request	*cur_req;
+	struct s3c2410_dma_client	dma_client;
+	spinlock_t			lock;
+	struct tasklet_struct		tasklet;
+	struct timer_list		timer;
+	struct crypto_queue		queue;
+};
+
+/**
+ * struct sss_context - cipher/hash key state
+ * @key: storage for the key
+ * @key_len: length of the key
+ * @dev: pointer to struct containing the driver state
+ */
+struct sss_context {
+	u8				key[SSS_MAX_KEY_SIZE];
+	unsigned int			key_len;
+
+	struct s3c_sss			*dev;
+};
+
+/**
+ * struct sss_fifo_channel - FIFO handling state
+ *
+ * @cur_sg: scatterlist used in current transfer
+ * @offset: offset within current scatterlist
+ * @dir: FIFO direction
+ * @sg: pointer to scatter-gather lists
+ * @sg_count: amount of scatter-gather lists
+ * @req_size: size of current request
+ * @bytes_done: amount of data transferred
+ * @dev: pointer to struct containing the driver state
+ */
+struct sss_fifo_channel {
+	/* DMA */
+	struct scatterlist		*cur_sg;
+	int				offset;
+	int				sg_count;
+
+	/* generic */
+	enum {
+		FIFO_RX,
+		FIFO_TX
+	}				dir;
+	struct scatterlist		*sg;
+	size_t				req_size;
+	size_t				bytes_done;
+	struct s3c_sss			*dev;
+};
+
+/**
+ * struct sss_req_context - driver-specific data associated with a request
+ * @algorithm: algorithm used in request
+ * @blk_cipher: block cipher used in request
+ * @direction: whether to encrypt or decrypt
+ * @rx: RX FIFO channel, see struct sss_fifo_channel
+ * @tx: TX FIFO channel, see struct sss_fifo_channel
+ * @setup_done: whether hardware has been set up
+ * @err: indicates any occured error during request
+ */
+struct sss_req_context {
+	enum sss_algorithm {
+		ALGO_AES,
+		ALGO_DES,
+		ALGO_TDES,
+		ALGO_SHA1,
+		ALGO_HMAC_SHA1,
+	}				algorithm;
+	enum sss_block_cipher {
+		CIPH_ECB,
+		CIPH_CBC,
+		CIPH_CTR,
+	}				blk_cipher;
+	enum sss_direction {
+		ENCRYPT,
+		DECRYPT,
+	}				direction;
+
+	struct sss_fifo_channel		rx;
+	struct sss_fifo_channel		tx;
+	bool				setup_done;
+	int				err;
+};
+
+/**
+ * struct sss_crypto_wrapper - simple wrapper for easy access to the driver data
+ * @alg: wrapped crypto algorithm
+ * @dev: pointer to the driver state
+ */
+struct sss_crypto_wrapper {
+	struct crypto_alg		 alg;
+	struct s3c_sss			*dev;
+};
+
+/*** Helper functions ***/
+
+#define fifo_to_req_ctx(fifo, dir) container_of((fifo), \
+						struct sss_req_context, dir)
+
+static inline struct sss_req_context *sss_to_req_ctx(struct s3c_sss *sss)
+{
+	struct ablkcipher_request *req = sss->cur_req;
+	return req ? ablkcipher_request_ctx(req) : NULL;
+}
+
+static inline unsigned int fifo_to_dma_channel(struct sss_fifo_channel *chan)
+{
+	return chan->dir == FIFO_TX ? DMACH_SECURITY_TX : DMACH_SECURITY_RX;
+}
+
+static inline bool sss_dma_enabled(void)
+{
+	/* DMA is disabled till someone figures out why it's not transmitting
+	   all data to the crypto engine. */
+	return false;
+}
+
+static int count_sgs(struct scatterlist *sg)
+{
+	int i;
+
+	for (i = 0; sg; i++)
+		sg = sg_next(sg);
+
+	return i;
+}
+
+static inline void orrl(u32 val, void __iomem *reg)
+{
+	writel(readl(reg) | val, reg);
+}
+
+#ifdef DEBUG
+static void sss_dump_regs(struct s3c_sss *sss)
+{
+	dev_dbg(sss->dev, "DnI_CFG: %x\n", readl(sss->regs + DnI_CFG));
+
+	dev_dbg(sss->dev, "FRx_Ctrl: %x\n", readl(sss->regs + FRx_Ctrl));
+	dev_dbg(sss->dev, "FRx_MLen: %x\n", readl(sss->regs + FRx_MLen));
+	dev_dbg(sss->dev, "FRx_BlkSz: %x\n", readl(sss->regs + FRx_BlkSz));
+	dev_dbg(sss->dev, "FRx_Addr: %x\n", readl(sss->regs + FRx_Addr));
+	dev_dbg(sss->dev, "FRx_MLenCnt: %x\n", readl(sss->regs + FRx_MLenCnt));
+
+	dev_dbg(sss->dev, "FTx_Ctrl: %x\n", readl(sss->regs + FTx_Ctrl));
+	dev_dbg(sss->dev, "FTx_MLen: %x\n", readl(sss->regs + FTx_MLen));
+	dev_dbg(sss->dev, "FTx_BlkSz: %x\n", readl(sss->regs + FTx_BlkSz));
+	dev_dbg(sss->dev, "FTx_Addr: %x\n", readl(sss->regs + FTx_Addr));
+	dev_dbg(sss->dev, "FTx_MLenCnt: %x\n", readl(sss->regs + FTx_MLenCnt));
+
+	dev_dbg(sss->dev, "AES_CTRL: %x\n", readl(sss->regs + AES_CTRL));
+	dev_dbg(sss->dev, "TDES_CTRL: %x\n", readl(sss->regs + TDES_CTRL));
+	dev_dbg(sss->dev, "HASH_CTRL: %x\n", readl(sss->regs + HASH_CTRL));
+	dev_dbg(sss->dev, "HASH_STATUS: %x\n", readl(sss->regs + HASH_STATUS));
+}
+#else
+#define sss_dump_regs(...)
+#endif
+
+#ifdef DEBUG
+static void sss_dump_channel(struct sss_fifo_channel *chan)
+{
+	struct s3c_sss *sss = chan->dev;
+	bool tx = (chan->dir == FIFO_TX);
+	u32 val;
+
+	val = readl(sss->regs + (tx ? FTx_Ctrl : FRx_Ctrl));
+
+	dev_dbg(sss->dev, "FIFO_%cX: %c%c%c%c%c\n", tx ? 'T' : 'R',
+		val & FXx_Ctrl_Full ? 'F' : ' ',
+		val & FXx_Ctrl_Empty ? 'E' : ' ',
+		val & FXx_Ctrl_Done ? 'D' : ' ',
+		val & FXx_Ctrl_Running ? 'R' : ' ',
+		val & FXx_Ctrl_Start ? 'S' : ' ');
+
+	if (sss_dma_enabled()) {
+		dev_dbg(sss->dev, "      cur_sg: %p\n", chan->cur_sg);
+		dev_dbg(sss->dev, "      offset: %d\n", chan->offset);
+		dev_dbg(sss->dev, "    sg_count: %d\n", chan->sg_count);
+	}
+
+	dev_dbg(sss->dev, "    req_size: %d\n", chan->req_size);
+	dev_dbg(sss->dev, "  bytes_done: %d\n", chan->bytes_done);
+	dev_dbg(sss->dev, "     mlencnt: %d\n",
+		readl(sss->regs + (tx ? FTx_MLenCnt : FRx_MLenCnt)) * 4);
+	dev_dbg(sss->dev, "    wd2write: %d\n", (val >> tx ? 8 : 16) & 0xFF);
+	dev_dbg(sss->dev, "     wd2read: %d\n", (val >> tx ? 16 : 8) & 0xFF);
+}
+#else
+#define sss_dump_channel(...)
+#endif
+
+static void sss_reset_fifo(struct s3c_sss *sss, int reg)
+{
+	int timeout = 1000;
+	u32 val;
+
+	writel(FXx_Ctrl_Reset, sss->regs + reg);
+
+	while (timeout-- > 0) {
+		val = readl(sss->regs + reg);
+		if (!(val & FXx_Ctrl_Reset))
+			break;
+	}
+
+	if (timeout <= 0)
+		dev_warn(sss->dev, "Failed to reset FIFO_%cX!\n",
+			 reg == FRx_Ctrl ? 'R' : 'T');
+}
+
+static void sss_reset_hw(struct s3c_sss *sss)
+{
+	u32 val = 0;
+
+	if (sss_dma_enabled())
+		val |= (DnI_CFG_RxDmaEnb | DnI_CFG_TxDmaEnb |
+			DnI_CFG_RxTrgLevel(16) | DnI_CFG_TxTrgLevel(16));
+
+	writel(val, sss->regs + DnI_CFG);
+
+	/* Reset FIFOs */
+	sss_reset_fifo(sss, FRx_Ctrl);
+	sss_reset_fifo(sss, FTx_Ctrl);
+
+	/* Ensure all subsystems are disabled */
+	writel(0, sss->regs + AES_CTRL);
+	writel(0, sss->regs + TDES_CTRL);
+	writel(0, sss->regs + HASH_CTRL);
+}
+
+#ifdef DEBUG
+static void check_priv_mismatch(struct s3c_sss *sss, const char* name, int reg)
+{
+	u32 val = readl(sss->regs + reg);
+
+	if (val & RdPrivMismatch)
+		dev_warn(sss->dev, "%s read privilege mismatch! (0x%x)\n", name,
+			 val);
+
+	if (val & WrPrivMismatch)
+		dev_warn(sss->dev, "%s write privilege mismatch! (0x%x)\n",
+			 name, val);
+}
+#else
+#define check_priv_mismatch(...)
+#endif
+
+static irqreturn_t sss_irq(int irq, void *priv)
+{
+	struct s3c_sss *sss = priv;
+	u32 cfg = readl(sss->regs + DnI_CFG);
+
+	check_priv_mismatch(sss, "CONFIG", DnI_CFG);
+
+	if (cfg & DnI_CFG_FRx_Intr_Status) {
+		dev_dbg(sss->dev, "%s: FIFO_RX IRQ\n", __func__);
+		check_priv_mismatch(sss, "FIFO RX", FRx_Ctrl);
+
+		if (sss->cur_req && !sss_dma_enabled()) {
+			struct sss_fifo_channel *ch = &sss_to_req_ctx(sss)->rx;
+			if (ch->req_size) {
+				dev_dbg(sss->dev, "Increasing consumption with "
+						  "%d bytes\n", ch->req_size);
+				ch->bytes_done += ch->req_size;
+				ch->req_size = 0;
+				tasklet_schedule(&sss->tasklet);
+			}
+		}
+	}
+
+	if (cfg & DnI_CFG_FTx_Intr_Status) {
+		dev_dbg(sss->dev, "%s: FIFO_TX IRQ\n", __func__);
+		check_priv_mismatch(sss, "FIFO TX", FTx_Ctrl);
+
+		if (sss->cur_req && !sss_dma_enabled())
+			tasklet_schedule(&sss->tasklet);
+	}
+
+	if (cfg & DnI_CFG_SHA_Intr_Status)
+		dev_dbg(sss->dev, "%s: HASH IRQ\n", __func__);
+
+	if (cfg & DnI_CFG_DES_Intr_Status) {
+		dev_dbg(sss->dev, "%s: TDES IRQ\n", __func__);
+		check_priv_mismatch(sss, "TDES", TDES_CTRL);
+	}
+
+	if (cfg & DnI_CFG_AES_Intr_Status) {
+		dev_dbg(sss->dev, "%s: AES IRQ\n", __func__);
+		check_priv_mismatch(sss, "AES", AES_CTRL);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static void sss_dma_cb(struct s3c2410_dma_chan *chan, void *pw, int size,
+		       enum s3c2410_dma_buffresult res)
+{
+	struct sss_fifo_channel *fifo_chan = pw;
+	struct s3c_sss *sss = fifo_chan->dev;
+	struct sss_req_context *req_ctx;
+
+	dev_dbg(sss->dev, "%s: FIFO_%cX\n", __func__,
+		fifo_chan->dir == FIFO_RX ? 'R' : 'T');
+
+	if (fifo_chan->dir == FIFO_RX)
+		req_ctx = fifo_to_req_ctx(fifo_chan, rx);
+	else
+		req_ctx = fifo_to_req_ctx(fifo_chan, tx);
+
+	switch (res) {
+	case S3C2410_RES_OK:
+		fifo_chan->bytes_done += fifo_chan->req_size;
+		fifo_chan->offset += fifo_chan->req_size;
+		fifo_chan->req_size = 0;
+		break;
+	case S3C2410_RES_ERR:
+	case S3C2410_RES_ABORT:
+	default:
+		dev_err(sss->dev, "Error occured during DMA transfer!\n");
+		if (!req_ctx->err)
+			req_ctx->err = -EIO;
+	}
+
+	tasklet_schedule(&sss->tasklet);
+}
+
+static int sss_setup_dma(struct s3c_sss *sss, unsigned int channel)
+{
+	enum s3c2410_dmasrc source;
+	unsigned long reg;
+	int ret;
+
+	ret = s3c2410_dma_request(channel, &sss->dma_client, sss);
+	if (ret < 0)
+		return ret;
+
+	if (channel == DMACH_SECURITY_RX) {
+		reg = (unsigned long)(sss->regs_phys + SDMA_FRx_Buf);
+		source = S3C2410_DMASRC_MEM;
+	} else { /* DMACH_SECURITY_TX */
+		reg = (unsigned long)(sss->regs_phys + SDMA_FTx_Buf);
+		source = S3C2410_DMASRC_HW;
+	}
+
+	s3c2410_dma_config(channel, 4);
+	s3c2410_dma_devconfig(channel, source, reg);
+	s3c2410_dma_set_buffdone_fn(channel, sss_dma_cb);
+
+	return 0;
+}
+
+static void sss_setup_hw(struct s3c_sss *sss)
+{
+	struct ablkcipher_request *req = sss->cur_req;
+	struct sss_context *ctx = crypto_tfm_ctx(req->base.tfm);
+	struct sss_req_context *req_ctx = ablkcipher_request_ctx(req);
+	u32 val, cfg, fifo_rx, fifo_tx;
+
+	dev_dbg(sss->dev, "%s: setting up hw\n", __func__);
+
+	sss_reset_hw(sss);
+
+	cfg = readl(sss->regs + DnI_CFG);
+	cfg |= (DnI_CFG_FTx_Intr_En | DnI_CFG_FRx_Intr_En);
+
+	fifo_rx = (FXx_Ctrl_Host_Rd_En | FXx_Ctrl_Host_Wr_En |
+		   FRx_Ctrl_Sync_Tx);
+	fifo_tx = (FXx_Ctrl_Host_Rd_En | FXx_Ctrl_Host_Wr_En);
+
+	switch (req_ctx->algorithm) {
+	case ALGO_AES:
+		cfg |= DnI_CFG_AES_Intr_En;
+		fifo_rx |= FXx_Ctrl_Module_AES;
+		fifo_tx |= FXx_Ctrl_Module_AES;
+
+		switch (req_ctx->blk_cipher) {
+		case CIPH_ECB:
+			val = AES_CTRL_OpMode_ECB;
+			break;
+		case CIPH_CBC:
+			val = AES_CTRL_OpMode_CBC;
+			memcpy(sss->regs + AES_IV, req->info, 16);
+			break;
+		case CIPH_CTR:
+			val = AES_CTRL_OpMode_CTR;
+			memcpy(sss->regs + AES_CTR, req->info, 16); /* ??? */
+			break;
+		}
+
+		if (req_ctx->direction == DECRYPT &&
+		    req_ctx->blk_cipher != CIPH_CTR)
+			val |= AES_CTRL_OpDirection_Dec;
+
+		switch (ctx->key_len) {
+		case AES_KEYSIZE_128:
+			val |= AES_CTRL_KeyMode_128bits;
+			break;
+		case AES_KEYSIZE_192:
+			val |= AES_CTRL_KeyMode_192bits;
+			break;
+		case AES_KEYSIZE_256:
+			val |= AES_CTRL_KeyMode_256bits;
+			break;
+		}
+		memcpy(sss->regs + AES_KEY, ctx->key, ctx->key_len);
+
+		writel(val, sss->regs + AES_CTRL);
+
+		writel(AES_BLOCK_SIZE / 4, sss->regs + FRx_BlkSz);
+		writel(AES_BLOCK_SIZE / 4, sss->regs + FTx_BlkSz);
+		writel(sss->regs_phys + AES_DIN, sss->regs + FRx_Addr);
+		writel(sss->regs_phys + AES_DOUT, sss->regs + FTx_Addr);
+
+		break;
+	case ALGO_DES:
+	case ALGO_TDES:
+		cfg |= DnI_CFG_DES_Intr_En;
+		fifo_rx |= FXx_Ctrl_Module_DES;
+		fifo_tx |= FXx_Ctrl_Module_DES;
+
+		switch (req_ctx->blk_cipher) {
+		case CIPH_ECB:
+			val = TDES_CTRL_Mode_ECB;
+			break;
+		case CIPH_CBC:
+			val = TDES_CTRL_Mode_CBC;
+			memcpy(sss->regs + TDES_IV, req->info, 16);
+			break;
+		case CIPH_CTR:
+			/* NOP */
+			break;
+		}
+
+		if (req_ctx->direction == DECRYPT)
+			val |= TDES_CTRL_OpDirection_Dec;
+
+		if (req_ctx->algorithm == ALGO_TDES)
+			val |= TDES_CTRL_Mode_Tdes;
+
+		val |= TDES_CTRL_IntMode;
+
+		memcpy(sss->regs + TDES_KEY, ctx->key, ctx->key_len);
+
+		writel(val, sss->regs + TDES_CTRL);
+
+		writel(DES_BLOCK_SIZE / 4, sss->regs + FRx_BlkSz);
+		writel(DES_BLOCK_SIZE / 4, sss->regs + FTx_BlkSz);
+		writel(sss->regs_phys + TDES_INPUT, sss->regs + FRx_Addr);
+		writel(sss->regs_phys + TDES_OUTPUT, sss->regs + FTx_Addr);
+
+		break;
+	case ALGO_SHA1:
+	case ALGO_HMAC_SHA1:
+		cfg |= DnI_CFG_SHA_Intr_En;
+		fifo_rx |= FXx_Ctrl_Module_SHA;
+		fifo_tx |= FXx_Ctrl_Module_SHA;
+
+		/*TODO*/
+
+		break;
+	}
+
+	writel(cfg, sss->regs + DnI_CFG);
+	writel(fifo_rx, sss->regs + FRx_Ctrl);
+	writel(fifo_tx, sss->regs + FTx_Ctrl);
+}
+
+static void sss_setup_hw_mlen(struct sss_fifo_channel *chan, size_t len)
+{
+	struct s3c_sss *sss = chan->dev;
+
+	if (chan->dir == FIFO_RX) {
+		writel(len / 4, sss->regs + FRx_MLen);
+		orrl(FXx_Ctrl_Start, sss->regs + FRx_Ctrl);
+	} else {
+		writel(len / 4, sss->regs + FTx_MLen);
+		orrl(FXx_Ctrl_Start, sss->regs + FTx_Ctrl);
+	}
+}
+
+static int sss_setup_dma_channel(struct sss_fifo_channel *chan)
+{
+	struct s3c_sss *sss = chan->dev;
+	unsigned int channel = fifo_to_dma_channel(chan);
+	int ret;
+
+	if (chan->offset >= sg_dma_len(chan->cur_sg)) {
+		chan->cur_sg = sg_next(chan->cur_sg);
+		chan->offset = 0;
+	}
+
+	chan->req_size = min(sg_dma_len(chan->cur_sg) - chan->offset,
+			     SSS_FIFO_SIZE);
+
+	sss_setup_hw_mlen(chan, chan->req_size);
+
+	dev_dbg(sss->dev, "Enqueue'ing for FIFO_%cX: %x (%d)\n",
+		channel == DMACH_SECURITY_TX ? 'T' : 'R',
+		sg_dma_address(chan->cur_sg) + chan->offset, chan->req_size);
+
+	ret = s3c2410_dma_enqueue(channel, chan,
+				  sg_dma_address(chan->cur_sg) + chan->offset,
+				  chan->req_size);
+	if (ret)
+		return ret;
+
+	return s3c2410_dma_ctrl(fifo_to_dma_channel(chan), S3C2410_DMAOP_START);
+}
+
+static void sss_setup_fifo(struct sss_fifo_channel *chan)
+{
+	struct s3c_sss *sss = chan->dev;
+	struct ablkcipher_request *req = sss->cur_req;
+	enum dma_data_direction dir;
+	unsigned int sg_flags;
+
+	if (chan->dir == FIFO_RX) {
+		sg_flags = SG_MITER_FROM_SG;
+		chan->sg = req->src;
+		dir = DMA_TO_DEVICE;
+	} else {
+		sg_flags = SG_MITER_TO_SG;
+		chan->sg = req->dst;
+		dir = DMA_FROM_DEVICE;
+	}
+
+	if (sss_dma_enabled()) {
+		int sg_count = count_sgs(chan->sg);
+		chan->sg_count = dma_map_sg(sss->dev, chan->sg, sg_count, dir);
+		chan->cur_sg = chan->sg;
+
+		s3c2410_dma_ctrl(fifo_to_dma_channel(chan),
+				 S3C2410_DMAOP_FLUSH);
+	}
+}
+
+static int sss_handle_fifo(struct sss_fifo_channel *chan)
+{
+	struct s3c_sss *sss = chan->dev;
+	struct ablkcipher_request *req = sss->cur_req;
+	void __iomem *fifo;
+
+	if (chan->req_size)
+		/* FIFO is still transferring data */
+		return -EINPROGRESS;
+
+	if (sss_dma_enabled())
+		return sss_setup_dma_channel(chan);
+
+	/* PIO */
+	if (chan->dir == FIFO_RX)
+		fifo = sss->regs + FRx_Buf;
+	else
+		fifo = sss->regs + FTx_Buf;
+
+	chan->req_size = min(req->nbytes - chan->bytes_done, SSS_FIFO_SIZE);
+
+	sss_setup_hw_mlen(chan, chan->req_size);
+
+	dev_dbg(sss->dev, "Transferring %d bytes to FIFO_%s\n", chan->req_size,
+		chan->dir == FIFO_TX ? "TX" : "RX");
+
+	scatterwalk_map_and_copy(fifo, chan->sg, chan->bytes_done,
+				 chan->req_size, (chan->dir == FIFO_TX));
+
+	if (chan->dir == FIFO_TX) {
+		chan->bytes_done += chan->req_size;
+		chan->req_size = 0;
+	}
+
+	return 0;
+}
+
+static void sss_cleanup_fifo(struct sss_fifo_channel *chan)
+{
+	struct s3c_sss *sss = chan->dev;
+	enum dma_data_direction dir;
+
+	if (sss_dma_enabled()) {
+		if (chan->dir == FIFO_RX)
+			dir = DMA_TO_DEVICE;
+		else
+			dir = DMA_FROM_DEVICE;
+
+		dma_unmap_sg(sss->dev, chan->sg, chan->sg_count, dir);
+
+		s3c2410_dma_ctrl(fifo_to_dma_channel(chan), S3C2410_DMAOP_STOP);
+	}
+}
+
+static void sss_timer_callback(unsigned long priv)
+{
+	struct s3c_sss *sss = (struct s3c_sss *)priv;
+	struct sss_req_context *req_ctx = sss_to_req_ctx(sss);
+
+	dev_err(sss->dev, "Request timed out!\n");
+	req_ctx->err = -ETIMEDOUT;
+
+	tasklet_schedule(&sss->tasklet);
+}
+
+static void sss_tasklet_callback(unsigned long priv)
+{
+	struct s3c_sss *sss = (struct s3c_sss *)priv;
+	struct sss_req_context *req_ctx;
+	struct ablkcipher_request *req;
+	unsigned long flags;
+
+	if (!sss->cur_req) {
+		spin_lock_irqsave(&sss->lock, flags);
+		sss->cur_req = ablkcipher_dequeue_request(&sss->queue);
+		spin_unlock_irqrestore(&sss->lock, flags);
+
+		if (!sss->cur_req) {
+			dev_warn(sss->dev, "Tasklet was called without any "
+					   "pending request!\n");
+			return;
+		}
+	}
+
+	/*TODO: backlog*/
+
+	req = sss->cur_req;
+	req_ctx = ablkcipher_request_ctx(req);
+
+	dev_dbg(sss->dev, "Current request: %p (%d)\n", req, req->nbytes);
+
+	if (!req_ctx->setup_done) {
+		clk_enable(sss->clock);
+
+		sss_setup_hw(sss);
+		sss_setup_fifo(&req_ctx->rx);
+		sss_setup_fifo(&req_ctx->tx);
+
+		req_ctx->setup_done = true;
+	}
+
+	/* Ensure timeout handler is killed */
+	if (timer_pending(&sss->timer))
+		del_timer(&sss->timer);
+
+	if (!req_ctx->err && (req_ctx->rx.bytes_done < req->nbytes ||
+			      req_ctx->tx.bytes_done < req->nbytes)) {
+		int ret;
+
+		if (req_ctx->tx.bytes_done < req_ctx->rx.bytes_done)
+			/* Keep TX in sync with RX */
+			ret = sss_handle_fifo(&req_ctx->tx);
+		else
+			/* Transmit some more data to RX */
+			ret = sss_handle_fifo(&req_ctx->rx);
+
+		sss_dump_channel(&req_ctx->tx);
+		sss_dump_channel(&req_ctx->rx);
+
+		if (ret && ret != -EINPROGRESS) {
+			req_ctx->err = ret;
+			goto cleanup;
+		}
+
+		mod_timer(&sss->timer, jiffies + SSS_TIMEOUT);
+		return;
+	}
+
+cleanup:
+	sss_cleanup_fifo(&req_ctx->rx);
+	sss_cleanup_fifo(&req_ctx->tx);
+
+	clk_disable(sss->clock);
+
+	/* Inform client of completion */
+	req->base.complete(&req->base, req_ctx->err);
+
+	spin_lock_irqsave(&sss->lock, flags);
+	sss->cur_req = NULL;
+	/* Check whether there's still work to do */
+	if (sss->queue.qlen || crypto_get_backlog(&sss->queue))
+		tasklet_schedule(&sss->tasklet);
+	spin_unlock_irqrestore(&sss->lock, flags);
+}
+
+/*** SW handling ***/
+
+static int sss_crypto_generic(struct ablkcipher_request *req,
+			      enum sss_algorithm alg,
+			      enum sss_block_cipher blk_ciph,
+			      enum sss_direction dir)
+{
+	struct sss_context *ctx = crypto_tfm_ctx(req->base.tfm);
+	struct sss_req_context *req_ctx = ablkcipher_request_ctx(req);
+	struct s3c_sss *sss = ctx->dev;
+	unsigned long flags;
+	int ret;
+
+	/* Fill the request */
+	*req_ctx = (struct sss_req_context){
+		.algorithm	= alg,
+		.blk_cipher	= blk_ciph,
+		.direction	= dir,
+		.rx		= {
+				.dev = sss,
+				.dir = FIFO_RX,
+		},
+		.tx		= {
+				.dev = sss,
+				.dir = FIFO_TX,
+		},
+	};
+
+	/* Enqueue the request */
+	spin_lock_irqsave(&sss->lock, flags);
+	ret = ablkcipher_enqueue_request(&sss->queue, req);
+	if (ret == -EINPROGRESS && !sss->cur_req)
+		tasklet_schedule(&sss->tasklet);
+	spin_unlock_irqrestore(&sss->lock, flags);
+
+	if (ret != -EINPROGRESS)
+		dev_err(sss->dev, "Couldn't enqueue request!\n");
+
+	return ret;
+}
+
+static int sss_aes_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
+			  unsigned int len)
+{
+	struct crypto_tfm *tfm	= crypto_ablkcipher_tfm(cipher);
+	struct sss_context *ctx	= crypto_tfm_ctx(tfm);
+
+	switch (len) {
+	case AES_KEYSIZE_128:
+	case AES_KEYSIZE_192:
+	case AES_KEYSIZE_256:
+		break;
+	default:
+		crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
+		return -EINVAL;
+	}
+
+	memcpy(ctx->key, key, len);
+	ctx->key_len = len;
+
+	return 0;
+}
+
+static int sss_des_setkey(struct crypto_ablkcipher *cipher, const u8 *key,
+			  unsigned int len)
+{
+	struct crypto_tfm *tfm	= crypto_ablkcipher_tfm(cipher);
+	struct sss_context *ctx	= crypto_tfm_ctx(tfm);
+
+	if (len > SSS_MAX_KEY_SIZE) {
+		crypto_ablkcipher_set_flags(cipher, CRYPTO_TFM_RES_BAD_KEY_LEN);
+		return -EINVAL;
+	}
+
+	/* RFC2451: weak key checks SHOULD be performed */
+	if (len == DES_KEY_SIZE) {
+		u32 tmp[DES_EXPKEY_WORDS];
+		int ret = des_ekey(tmp, key);
+
+		if (unlikely(ret == 0) &&
+		    (crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_WEAK_KEY)) {
+			crypto_tfm_set_flags(tfm, CRYPTO_TFM_RES_WEAK_KEY);
+			return -EINVAL;
+		}
+	}
+
+	memcpy(ctx->key, key, len);
+	ctx->key_len = len;
+
+	return 0;
+}
+
+static int sss_cra_init(struct crypto_tfm *tfm)
+{
+	struct sss_crypto_wrapper *wrapper = container_of(tfm->__crt_alg,
+						struct sss_crypto_wrapper, alg);
+	struct s3c_sss *sss = wrapper->dev;
+	struct sss_context *ctx = crypto_tfm_ctx(tfm);
+
+	ctx->dev = sss;
+	tfm->crt_ablkcipher.reqsize = sizeof(struct sss_req_context);
+
+	return 0;
+}
+
+static int sss_aes_cbc_encrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_AES, CIPH_CBC, ENCRYPT);
+}
+
+static int sss_aes_cbc_decrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_AES, CIPH_CBC, DECRYPT);
+}
+
+static int sss_aes_ecb_encrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_AES, CIPH_ECB, ENCRYPT);
+}
+
+static int sss_aes_ecb_decrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_AES, CIPH_ECB, DECRYPT);
+}
+
+static int sss_aes_ctr_encrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_AES, CIPH_CTR, ENCRYPT);
+}
+
+static int sss_aes_ctr_decrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_AES, CIPH_CTR, DECRYPT);
+}
+
+static int sss_des_ecb_encrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_DES, CIPH_ECB, ENCRYPT);
+}
+
+static int sss_des_ecb_decrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_DES, CIPH_ECB, DECRYPT);
+}
+
+static int sss_des_cbc_encrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_DES, CIPH_CBC, ENCRYPT);
+}
+
+static int sss_des_cbc_decrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_DES, CIPH_CBC, DECRYPT);
+}
+
+static int sss_tdes_ecb_encrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_TDES, CIPH_ECB, ENCRYPT);
+}
+
+static int sss_tdes_ecb_decrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_TDES, CIPH_ECB, DECRYPT);
+}
+
+static int sss_tdes_cbc_encrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_TDES, CIPH_CBC, ENCRYPT);
+}
+
+static int sss_tdes_cbc_decrypt(struct ablkcipher_request *req)
+{
+	return sss_crypto_generic(req, ALGO_TDES, CIPH_CBC, DECRYPT);
+}
+
+static struct sss_algo_template {
+	char				*alg_name;
+	char				*blk_ciph_name;
+	int				 blk_size;
+	struct ablkcipher_alg		 ablkcipher;
+
+	struct sss_crypto_wrapper	*alg;
+} sss_crypto_algos[] = {
+	/* AES ECB/CBC/CTR */
+	{
+		.alg_name = "aes",
+		.blk_ciph_name = "ecb",
+		.blk_size = AES_BLOCK_SIZE,
+		.ablkcipher = {
+			.min_keysize	=	AES_MIN_KEY_SIZE,
+			.max_keysize	=	AES_MAX_KEY_SIZE,
+			.setkey		=	sss_aes_setkey,
+			.encrypt	=	sss_aes_ecb_encrypt,
+			.decrypt	=	sss_aes_ecb_decrypt,
+		},
+	},
+	{
+		.alg_name = "aes",
+		.blk_ciph_name = "cbc",
+		.blk_size = AES_BLOCK_SIZE,
+		.ablkcipher = {
+			.ivsize		=	AES_BLOCK_SIZE,
+			.min_keysize	=	AES_MIN_KEY_SIZE,
+			.max_keysize	=	AES_MAX_KEY_SIZE,
+			.setkey		=	sss_aes_setkey,
+			.encrypt	=	sss_aes_cbc_encrypt,
+			.decrypt	=	sss_aes_cbc_decrypt,
+		},
+	},
+	{
+		.alg_name = "aes",
+		.blk_ciph_name = "ctr",
+		.blk_size = AES_BLOCK_SIZE,
+		.ablkcipher = {
+			.ivsize		=	CTR_RFC3686_IV_SIZE,
+			.min_keysize	=	AES_MIN_KEY_SIZE,
+			.max_keysize	=	AES_MAX_KEY_SIZE,
+			.setkey		=	sss_aes_setkey,
+			.encrypt	=	sss_aes_ctr_encrypt,
+			.decrypt	=	sss_aes_ctr_decrypt,
+		},
+	},
+	/* DES CBC/ECB */
+	{
+		.alg_name = "des",
+		.blk_ciph_name = "cbc",
+		.blk_size = DES_BLOCK_SIZE,
+		.ablkcipher = {
+			.ivsize		=	DES_BLOCK_SIZE,
+			.min_keysize	=	DES_KEY_SIZE,
+			.max_keysize	=	DES_KEY_SIZE,
+			.setkey		=	sss_des_setkey,
+			.encrypt	=	sss_des_cbc_encrypt,
+			.decrypt	=	sss_des_cbc_decrypt,
+		},
+	},
+	{
+		.alg_name = "des",
+		.blk_ciph_name = "ecb",
+		.blk_size = DES_BLOCK_SIZE,
+		.ablkcipher = {
+			.min_keysize	=	DES_KEY_SIZE,
+			.max_keysize	=	DES_KEY_SIZE,
+			.setkey		=	sss_des_setkey,
+			.encrypt	=	sss_des_ecb_encrypt,
+			.decrypt	=	sss_des_ecb_decrypt,
+		},
+	},
+	/* TDES CBC/ECB */
+	{
+		.alg_name = "des3_ede",
+		.blk_ciph_name = "cbc",
+		.blk_size = DES3_EDE_BLOCK_SIZE,
+		.ablkcipher = {
+			.ivsize		=	DES3_EDE_BLOCK_SIZE,
+			.min_keysize	=	DES3_EDE_KEY_SIZE,
+			.max_keysize	=	DES3_EDE_KEY_SIZE,
+			.setkey		=	sss_des_setkey,
+			.encrypt	=	sss_tdes_cbc_encrypt,
+			.decrypt	=	sss_tdes_cbc_decrypt,
+		},
+	},
+	{
+		.alg_name = "des3_ede",
+		.blk_ciph_name = "ecb",
+		.blk_size = DES3_EDE_BLOCK_SIZE,
+		.ablkcipher = {
+			.min_keysize	=	DES3_EDE_KEY_SIZE,
+			.max_keysize	=	DES3_EDE_KEY_SIZE,
+			.setkey		=	sss_des_setkey,
+			.encrypt	=	sss_tdes_ecb_encrypt,
+			.decrypt	=	sss_tdes_ecb_decrypt,
+		},
+	},
+};
+
+static int sss_init_template(struct platform_device *pdev,
+			     struct sss_algo_template *templ)
+{
+	struct s3c_sss *sss = platform_get_drvdata(pdev);
+	struct sss_crypto_wrapper *alg;
+
+	alg = kzalloc(sizeof(struct sss_crypto_wrapper), GFP_KERNEL);
+	if (!alg)
+		return -ENOMEM;
+
+	alg->dev = sss;
+	alg->alg = (struct crypto_alg){
+			.cra_ablkcipher	= templ->ablkcipher,
+			.cra_blocksize	= templ->blk_size,
+			.cra_ctxsize	= sizeof(struct sss_context),
+			.cra_flags	= CRYPTO_ALG_TYPE_ABLKCIPHER |
+					  CRYPTO_ALG_ASYNC,
+			.cra_init	= sss_cra_init,
+			.cra_module	= THIS_MODULE,
+			.cra_priority	= SSS_CRA_PRIORITY,
+			.cra_type	= &crypto_ablkcipher_type,
+	};
+
+	snprintf(alg->alg.cra_name, CRYPTO_MAX_ALG_NAME, "%s(%s)",
+		 templ->blk_ciph_name, templ->alg_name);
+	snprintf(alg->alg.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-%s-%s",
+		 pdev->name, templ->alg_name, templ->blk_ciph_name);
+
+	/* Save pointer for removal */
+	templ->alg = alg;
+
+	dev_info(sss->dev, "crypto acceleration for %s", alg->alg.cra_name);
+
+	return 0;
+}
+
+static struct ahash_alg sss_hash_algos[] = {
+#if 0
+	{
+		.init		=	sss_sha_init,
+		.update		=	sss_sha_update,
+		.final		=	sss_sha1_final,
+		.digest		=	sss_sha1_digest,
+		.halg		=	{
+			.digestsize		=	SHA1_DIGEST_SIZE,
+			.statesize		=	sizeof(struct sha1_state),
+			.base			=	{
+				.cra_name		=	"sha1",
+				.cra_driver_name	=	"s3c-sss-sha1",
+				.cra_priority		=	SSS_CRA_PRIORITY,
+				.cra_flags		=	CRYPTO_ALG_TYPE_AHASH |
+								CRYPTO_ALG_ASYNC,
+				.cra_blocksize		=	SHA1_BLOCK_SIZE,
+				.cra_ctxsize		=	sizeof(struct sss_context),
+				.cra_type		=	&crypto_ahash_type,
+				.cra_module		=	THIS_MODULE,
+				.cra_init		=	sss_cra_init,
+			}
+		},
+	},
+	{
+		.init		=	sss_sha_init,
+		.update		=	sss_sha_update,
+		.final		=	sss_sha1_final,
+		.digest		=	sss_sha1_digest,
+		.setkey		=	sss_sha1_setkey,
+		.halg		=	{
+			.digestsize		=	SHA1_DIGEST_SIZE,
+			.statesize		=	sizeof(struct sha1_state),
+			.base			=	{
+				.cra_name		=	"hmac(sha1)",
+				.cra_driver_name	=	"s3c-sss-hmac-sha1",
+				.cra_priority		=	SSS_CRA_PRIORITY,
+				.cra_flags		=	CRYPTO_ALG_TYPE_AHASH |
+								CRYPTO_ALG_ASYNC,
+				.cra_blocksize		=	SHA1_BLOCK_SIZE,
+				.cra_ctxsize		=	sizeof(struct sss_context),
+				.cra_type		=	&crypto_ahash_type,
+				.cra_module		=	THIS_MODULE,
+				.cra_init		=	sss_cra_init,
+			}
+		},
+	},
+#endif
+};
+
+static void sss_unregister_algos(void)
+{
+	struct sss_crypto_wrapper *alg;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(sss_crypto_algos); i++) {
+		alg = sss_crypto_algos[i].alg;
+
+		if (alg) {
+			crypto_unregister_alg(&alg->alg);
+			kfree(alg);
+
+			sss_crypto_algos[i].alg = NULL;
+		}
+	}
+
+	/* Unregistering algorithms that weren't registered in the first place
+	   doesn't do any harm, so just do it for all. */
+	for (i = 0; i < ARRAY_SIZE(sss_hash_algos); i++)
+		crypto_unregister_ahash(&sss_hash_algos[i]);
+}
+
+static int sss_register_algos(struct platform_device *pdev)
+{
+	int i, ret;
+
+	for (i = 0; i < ARRAY_SIZE(sss_crypto_algos); i++) {
+		ret = sss_init_template(pdev, &sss_crypto_algos[i]);
+		if (ret)
+			goto exit;
+
+		ret = crypto_register_alg(&sss_crypto_algos[i].alg->alg);
+		if (ret)
+			goto exit;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(sss_hash_algos); i++) {
+		ret = crypto_register_ahash(&sss_hash_algos[i]);
+		if (ret)
+			goto exit;
+	}
+
+	return 0;
+
+exit:
+	sss_unregister_algos();
+	return ret;
+}
+
+static int __devinit sss_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct s3c_sss *sss;
+	int ret;
+
+	sss = kzalloc(sizeof(struct s3c_sss), GFP_KERNEL);
+	if (!sss) {
+		dev_err(dev, "cannot allocate memory\n");
+		return -ENOMEM;
+	}
+
+	spin_lock_init(&sss->lock);
+	crypto_init_queue(&sss->queue, 50);
+	tasklet_init(&sss->tasklet, sss_tasklet_callback, (unsigned long) sss);
+	setup_timer(&sss->timer, sss_timer_callback, (unsigned long) sss);
+
+	sss->dev = dev;
+	sss->dma_client.name = (char *) pdev->name;
+	platform_set_drvdata(pdev, sss);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(dev, "cannot find register resource\n");
+		ret = -EINVAL;
+		goto exit_dev;
+	}
+
+	sss->regs_res = request_mem_region(res->start, resource_size(res),
+					   dev_name(dev));
+	if (!sss->regs_res) {
+		dev_err(dev, "cannot request register resource\n");
+		ret = -ENOENT;
+		goto exit_dev;
+	}
+
+	sss->regs_phys = (void __iomem *) res->start;
+
+	sss->regs = ioremap(res->start, resource_size(res));
+	if (!sss->regs) {
+		dev_err(dev, "cannot map registers\n");
+		ret = -ENXIO;
+		goto exit_resource;
+	}
+
+	ret = platform_get_irq(pdev, 0);
+	if (ret < 0 || ret == NO_IRQ) {
+		dev_err(dev, "cannot find IRQ\n");
+		goto exit_regs_remap;
+	}
+
+	sss->irq = ret;
+
+	ret = request_irq(sss->irq, sss_irq, 0, dev_name(dev), sss);
+	if (ret < 0) {
+		dev_err(dev, "cannot claim IRQ\n");
+		goto exit_regs_remap;
+	}
+
+	sss->clock = clk_get(dev, "secur");
+	if (!sss->clock) {
+		dev_err(dev, "cannot find clock\n");
+		ret = -ENXIO;
+		goto exit_irq;
+	}
+
+	WARN_ON(clk_set_rate(sss->clock, 66*1000000)); /*REMOVEME*/
+
+	if (sss_dma_enabled()) {
+		ret = sss_setup_dma(sss, DMACH_SECURITY_RX);
+		if (ret < 0) {
+			dev_err(dev, "cannot setup SECURITY_RX DMA channel\n");
+			goto exit_clock;
+		}
+
+		ret = sss_setup_dma(sss, DMACH_SECURITY_TX);
+		if (ret < 0) {
+			dev_err(dev, "cannot setup SECURITY_TX DMA channel\n");
+			goto exit_dma_rx;
+		}
+	}
+
+	ret = sss_register_algos(pdev);
+	if (ret) {
+		dev_err(dev, "cannot register algos\n");
+		goto exit_dma_tx;
+	}
+
+	return 0;
+
+exit_dma_tx:
+	if (sss_dma_enabled())
+		s3c2410_dma_free(DMACH_SECURITY_TX, &sss->dma_client);
+exit_dma_rx:
+	if (sss_dma_enabled())
+		s3c2410_dma_free(DMACH_SECURITY_RX, &sss->dma_client);
+exit_clock:
+	clk_put(sss->clock);
+exit_irq:
+	free_irq(sss->irq, sss);
+exit_regs_remap:
+	iounmap(sss->regs);
+exit_resource:
+	release_resource(sss->regs_res);
+	kfree(sss->regs_res);
+exit_dev:
+	tasklet_kill(&sss->tasklet);
+	kfree(sss);
+
+	return ret;
+}
+
+static int __devexit sss_remove(struct platform_device *pdev)
+{
+	struct s3c_sss *sss = platform_get_drvdata(pdev);
+
+	if (timer_pending(&sss->timer))
+		del_timer(&sss->timer);
+
+	if (sss_dma_enabled()) {
+		s3c2410_dma_free(DMACH_SECURITY_TX, &sss->dma_client);
+		s3c2410_dma_free(DMACH_SECURITY_RX, &sss->dma_client);
+	}
+
+	sss_unregister_algos();
+	clk_put(sss->clock);
+	free_irq(sss->irq, sss);
+	iounmap(sss->regs);
+	release_resource(sss->regs_res);
+	kfree(sss->regs_res);
+	tasklet_kill(&sss->tasklet);
+	kfree(sss);
+
+	return 0;
+}
+
+static struct platform_driver sss_crypto = {
+	.driver		= {
+		.name	= "s3c-sss",
+		.owner	= THIS_MODULE,
+	},
+	.probe		= sss_probe,
+	.remove		= __devexit_p(sss_remove),
+};
+
+static int __init sss_crypto_init(void)
+{
+	return platform_driver_register(&sss_crypto);
+}
+module_init(sss_crypto_init);
+
+static void __exit sss_crypto_exit(void)
+{
+	platform_driver_unregister(&sss_crypto);
+}
+module_exit(sss_crypto_exit);
+
+MODULE_AUTHOR("Maurus Cuelenaere <mcuelenaere at gmail.com>");
+MODULE_DESCRIPTION("Support for Samsung's Security Sub-Systems");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:sss_crypto");
-- 
1.7.1



From mcuelenaere at gmail.com  Fri Jun 11 15:49:16 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Fri, 11 Jun 2010 21:49:16 +0200
Subject: [RFC 8/9] ARM: SAMSUNG: Add crypto engine register definitions
In-Reply-To: <cover.1276284559.git.mcuelenaere@gmail.com>
References: <cover.1276284559.git.mcuelenaere@gmail.com>
Message-ID: <4C12933C.9080506@gmail.com>

This patch adds the header file containing the register offsets used by the
crypto engine.

Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
---
 arch/arm/plat-samsung/include/plat/regs-sss.h |  153 +++++++++++++++++++++++++
 1 files changed, 153 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-samsung/include/plat/regs-sss.h

diff --git a/arch/arm/plat-samsung/include/plat/regs-sss.h b/arch/arm/plat-samsung/include/plat/regs-sss.h
new file mode 100644
index 0000000..f54cd3b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-sss.h
@@ -0,0 +1,153 @@
+/*
+ * linux/arch/arm/plat-samsung/include/plat/regs-sss.h
+ *
+ * Copyright (C) 2010 Maurus Cuelenaere
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __PLAT_SAMSUNG_REGS_SSS_H
+#define __PLAT_SAMSUNG_REGS_SSS_H __FILE__
+
+#include <mach/regs-sss.h>
+
+/* Config */
+#define DnI_CFG				(SSS_OFF_CFG + 0x00)
+
+#define DnI_CFG_WrPrivMismatch		(1 << 31)
+#define DnI_CFG_RdPrivMismatch		(1 << 30)
+#define DnI_CFG_SHA_Intr_Status		(1 << 22)
+#define DnI_CFG_DES_Intr_Status		(1 << 21)
+#define DnI_CFG_AES_Intr_Status		(1 << 20)
+#define DnI_CFG_FTx_Intr_Status		(1 << 17)
+#define DnI_CFG_FRx_Intr_Status		(1 << 16)
+#define DnI_CFG_SHA_Intr_En		(1 << 14)
+#define DnI_CFG_DES_Intr_En		(1 << 13)
+#define DnI_CFG_AES_Intr_En		(1 << 12)
+#define DnI_CFG_FTx_Intr_En		(1 << 9)
+#define DnI_CFG_FRx_Intr_En		(1 << 8)
+#define DnI_CFG_TxTrgLevel(n)		(((n / 4) & 7) << 5)
+#define DnI_CFG_TxDmaEnb		(1 << 4)
+#define DnI_CFG_RxTrgLevel(n)		(((n / 4) & 7) << 1)
+#define DnI_CFG_RxDmaEnb		(1 << 0)
+
+/* FIFO */
+#define FRx_Ctrl			(SSS_OFF_FIFO_RX + 0x00)
+#define FRx_MLen			(SSS_OFF_FIFO_RX + 0x04)
+#define FRx_BlkSz			(SSS_OFF_FIFO_RX + 0x08)
+#define FRx_Addr			(SSS_OFF_FIFO_RX + 0x0C)
+#define FRx_MLenCnt			(SSS_OFF_FIFO_RX + 0x10)
+#define FRx_Buf				(SSS_OFF_FIFO_RX + 0x40)
+
+#define FTx_Ctrl			(SSS_OFF_FIFO_TX + 0x00)
+#define FTx_MLen			(SSS_OFF_FIFO_TX + 0x04)
+#define FTx_BlkSz			(SSS_OFF_FIFO_TX + 0x08)
+#define FTx_Addr			(SSS_OFF_FIFO_TX + 0x0C)
+#define FTx_MLenCnt			(SSS_OFF_FIFO_TX + 0x10)
+#define FTx_Buf				(SSS_OFF_FIFO_TX + 0x40)
+
+#define FXx_Ctrl_WrPrivError		(1 << 31)
+#define FXx_Ctrl_RdPrivError		(1 << 30)
+#define FXx_Ctrl_Full			(1 << 27)
+#define FXx_Ctrl_Empty			(1 << 26)
+#define FXx_Ctrl_Done			(1 << 25)
+#define FXx_Ctrl_Running		(1 << 24)
+#define FRx_Ctrl_Wd2Write(n)		((n & 0xFF) << 16)
+#define FRx_Ctrl_Wd2Read(n)		((n & 0xFF) << 8)
+#define FTx_Ctrl_Wd2Read(n)		((n & 0xFF) << 16)
+#define FTx_Ctrl_Wd2Write(n)		((n & 0xFF) << 8)
+#define FXx_Ctrl_Module_AES		(0 << 6)
+#define FXx_Ctrl_Module_DES		(1 << 6)
+#define FXx_Ctrl_Module_SHA		(2 << 6)
+#define FXx_Ctrl_Host_Rd_En		(1 << 5)
+#define FXx_Ctrl_Host_Wr_En		(1 << 4)
+#define FRx_Ctrl_Sync_Tx		(1 << 3)
+#define FXx_Ctrl_Reset			(1 << 2)
+#define FXx_Ctrl_ERROR_En		(1 << 1)
+#define FXx_Ctrl_Start			(1 << 0)
+
+#define FXx_BlkSz_LastValidByte(n)	((n & 3) << 16)
+
+/* AES */
+#define AES_CTRL			(SSS_OFF_AES_RX + 0x00)
+#define AES_DIN				(SSS_OFF_AES_RX + 0x10)
+#define AES_DOUT			(SSS_OFF_AES_TX + 0x20)
+#define AES_KEY				(SSS_OFF_AES_RX + 0x80)
+#define AES_IV				(SSS_OFF_AES_RX + 0xA0)
+#define AES_CTR				(SSS_OFF_AES_RX + 0xB0)
+
+#define AES_CTRL_WrPrivMismatch		(1 << 31)
+#define AES_CTRL_RdPrivMismatch		(1 << 30)
+#define AES_CTRL_OutReady		(1 << 10)
+#define AES_CTRL_InReady		(1 << 9)
+#define AES_CTRL_ContDecOn		(1 << 8)
+#define AES_CTRL_CtrWidth_16bits	(0 << 6)
+#define AES_CTRL_CtrWidth_32bits	(1 << 6)
+#define AES_CTRL_CtrWidth_64bits	(2 << 6)
+#define AES_CTRL_OpMode_ECB		(1 << 4)
+#define AES_CTRL_OpMode_CBC		(2 << 4)
+#define AES_CTRL_OpMode_CTR		(3 << 4)
+#define AES_CTRL_OpDirection_Enc	(0 << 3)
+#define AES_CTRL_OpDirection_Dec	(1 << 3)
+#define AES_CTRL_KeyMode_128bits	(0 << 1)
+#define AES_CTRL_KeyMode_192bits	(1 << 1)
+#define AES_CTRL_KeyMode_256bits	(2 << 1)
+#define AES_CTRL_OpEnable		(1 << 0)
+
+/* TDES */
+#define TDES_CTRL			(SSS_OFF_TDES_RX + 0x00)
+#define TDES_KEY			(SSS_OFF_TDES_RX + 0x10)
+#define TDES_INPUT			(SSS_OFF_TDES_RX + 0x40)
+#define TDES_OUTPUT			(SSS_OFF_TDES_TX + 0x48)
+#define TDES_IV				(SSS_OFF_TDES_RX + 0x50)
+
+#define TDES_CTRL_WrPrivMismatch	(1 << 31)
+#define TDES_CTRL_RdPrivMismatch	(1 << 30)
+#define TDES_CTRL_OutReady		(1 << 7)
+#define TDES_CTRL_InReady		(1 << 6)
+#define TDES_CTRL_Mode_Des		(0 << 5)
+#define TDES_CTRL_Mode_Tdes		(1 << 5)
+#define TDES_CTRL_Mode_ECB		(1 << 3)
+#define TDES_CTRL_Mode_CBC		(2 << 3)
+#define TDES_CTRL_OpDirection_Enc	(0 << 2)
+#define TDES_CTRL_OpDirection_Dec	(1 << 2)
+#define TDES_CTRL_IntMode		(1 << 1)
+#define TDES_CTRL_OpEnable		(1 << 0)
+
+/* SHA1/PRNG */
+#define HASH_CTRL			(SSS_OFF_HASH_RX + 0x00)
+#define HASH_DATA			(SSS_OFF_HASH_RX + 0x04)
+#define HASH_STATUS			(SSS_OFF_HASH_RX + 0x30)
+#define HASH_OUTPUT			(SSS_OFF_HASH_TX + 0x34)
+#define HASH_MIDOUT			(SSS_OFF_HASH_RX + 0x5C)
+#define HASH_IV				(SSS_OFF_HASH_RX + 0x70)
+#define PRE_MSG_LENGTH			(SSS_OFF_HASH_RX + 0x84)
+
+#define HASH_CTRL_USE_IV		(1 << 8)
+#define HASH_CTRL_End_of_Hash_byte(n)	((n & 3) << 6)
+#define HASH_CTRL_SEED_SETTING_ENB	(1 << 5)
+#define HASH_CTRL_Hash_Input_Finished	(1 << 4)
+#define HASH_CTRL_Hash_Start		(1 << 3)
+#define HASH_CTRL_Data_Selection	(1 << 2)
+#define HASH_CTRL_Engine_HMAC		(0 << 0)
+#define HASH_CTRL_Engine_SHA1		(1 << 0)
+#define HASH_CTRL_Engine_PRNG		(2 << 0)
+
+#define HASH_STATUS_BUFFER_IN_ENB	(1 << 4)
+#define HASH_STATUS_Engine_Ready	(1 << 3)
+#define HASH_STATUS_RNG_Ready		(1 << 2)
+#define HASH_STATUS_32bit_Ready		(1 << 1)
+#define HASH_STATUS_Output_Ready	(1 << 0)
+
+/* SDMA */
+#define SDMA_FRx_Buf			(SSS_OFF_SDMA_RX + 0x40)
+#define SDMA_FTx_Buf			(SSS_OFF_SDMA_TX + 0x40)
+
+/* Generic */
+#define WrPrivMismatch			(1 << 31)
+#define RdPrivMismatch			(1 << 30)
+
+#endif /* __PLAT_SAMSUNG_REGS_SSS_H */
-- 
1.7.1




From broonie at opensource.wolfsonmicro.com  Sun Jun 13 10:00:59 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sun, 13 Jun 2010 15:00:59 +0100
Subject: [PATCH 1/3] ISL6271A voltage regulator support.
In-Reply-To: <201006131230.08408.marek.vasut@gmail.com>
	(sfid-20100613_113213_110193_0C520859)
References: <1276346679-2893-1-git-send-email-marek.vasut@gmail.com>
	<20100612172114.GA20610@opensource.wolfsonmicro.com>
	<201006131230.08408.marek.vasut@gmail.com>
	(sfid-20100613_113213_110193_0C520859)
Message-ID: <40F790AF-4BAF-4AA2-8438-C3365FBABB57@opensource.wolfsonmicro.com>


On 13 Jun 2010, at 11:30, Marek Vasut wrote:

> Dne So 12. ?ervna 2010 19:21:14 Mark Brown napsal(a):
>> On Sat, Jun 12, 2010 at 02:44:37PM +0200, Marek Vasut wrote:
>>> This device is very simple, it supports only one LDO. This single LDO is
>>> programmed over I2C to 16 possible voltages.
>> 
>> Google tells me that the device has three regulators on it - two LDOs
>> and one DCDC buck convertor:
>> 
>>   http://www.intersil.com/products/deviceinfo.asp?pn=ISL6271A
>> 
>> While the LDOs look like they have no software control it'd be best to
>> provide hookup for them, even if that's just a case of instantiating the
>> appropriate fixed voltage regulators.

> Is this necessary? I'd only increase the kernel size without any gain ... or am 
> I wrong ?

If devices are connected to the fixed supplies they still need to be told about
the connection so they can interact well with the regulator API.

There's also the fact that your description of the device in the changelog is
rather inaccurate - the device has three regulators, not just a single LDO, and
the regulator that is software controllable is a DCDC buck convertor not a LDO.

>> Also, are you sure this is a buck?  That's a specific technical term
>> usually only applied to DCDC regulators - LDOs are a different type of
>> regulator

> That's what's written in the ISL6271a TRM. On the first page, under the 
> "Features" section.

That says there is one buck and 2 LDOs and it rather looks like the software
controllable regulator is the buck.



From marek.vasut at gmail.com  Sun Jun 13 11:25:51 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Sun, 13 Jun 2010 17:25:51 +0200
Subject: [PATCH v3] ISL6271A voltage regulator support.
Message-ID: <1276442751-3562-1-git-send-email-marek.vasut@gmail.com>

This device is very simple, it supports one buck and two LDOs. The LDOs are
fixed-voltage. Only the buck is programable over the I2C bus to 16 possible
voltages.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/regulator/Kconfig              |    6 +
 drivers/regulator/Makefile             |    1 +
 drivers/regulator/isl6271a-regulator.c |  236 ++++++++++++++++++++++++++++++++
 3 files changed, 243 insertions(+), 0 deletions(-)
 create mode 100644 drivers/regulator/isl6271a-regulator.c

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 04f2e08..6772ca7 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -201,5 +201,11 @@ config REGULATOR_88PM8607
 	help
 	  This driver supports 88PM8607 voltage regulator chips.
 
+config REGULATOR_ISL6271A
+	tristate "Intersil ISL6271A Power regulator"
+	depends on I2C
+	help
+	  This driver supports ISL6271A voltage regulator chip.
+
 endif
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 4e7feec..e2191bf 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_REGULATOR_AB3100) += ab3100.o
 obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o
 obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
 obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
+obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/isl6271a-regulator.c b/drivers/regulator/isl6271a-regulator.c
new file mode 100644
index 0000000..e49d2bd
--- /dev/null
+++ b/drivers/regulator/isl6271a-regulator.c
@@ -0,0 +1,236 @@
+/*
+ * isl6271a-regulator.c
+ *
+ * Support for Intersil ISL6271A voltage regulator
+ *
+ * Copyright (C) 2010 Marek Vasut <marek.vasut at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
+ * whether express or implied; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/driver.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#define	ISL6271A_VOLTAGE_MIN	850000
+#define	ISL6271A_VOLTAGE_MAX	1600000
+#define	ISL6271A_VOLTAGE_STEP	50000
+
+/* PMIC details */
+struct isl_pmic {
+	struct i2c_client	*client;
+	struct regulator_dev	*rdev[3];
+	struct mutex		mtx;
+};
+
+static int isl6271a_get_voltage(struct regulator_dev *dev)
+{
+	struct isl_pmic *pmic = rdev_get_drvdata(dev);
+	int idx, data;
+
+	mutex_lock(&pmic->mtx);
+
+	idx = i2c_smbus_read_byte(pmic->client);
+	if (idx < 0) {
+		dev_err(&pmic->client->dev, "Error getting voltage\n");
+		data = idx;
+		goto out;
+	}
+
+	/* Convert the data from chip to microvolts */
+	data = ISL6271A_VOLTAGE_MIN + (ISL6271A_VOLTAGE_STEP * (idx & 0xf));
+
+out:
+	mutex_unlock(&pmic->mtx);
+	return data;
+}
+
+static int isl6271a_set_voltage(struct regulator_dev *dev, int minuV, int maxuV)
+{
+	struct isl_pmic *pmic = rdev_get_drvdata(dev);
+	int vsel, err, data;
+
+	if (minuV < ISL6271A_VOLTAGE_MIN || minuV > ISL6271A_VOLTAGE_MAX)
+		return -EINVAL;
+	if (maxuV < ISL6271A_VOLTAGE_MIN || maxuV > ISL6271A_VOLTAGE_MAX)
+		return -EINVAL;
+
+	/* Align to 50000 mV */
+	vsel = minuV - (minuV % ISL6271A_VOLTAGE_STEP);
+
+	/* If the result fell out of [minuV,maxuV] range, put it back */
+	if (vsel < minuV)
+		vsel += ISL6271A_VOLTAGE_STEP;
+
+	/* Convert the microvolts to data for the chip */
+	data = (vsel - ISL6271A_VOLTAGE_MIN) / ISL6271A_VOLTAGE_STEP;
+
+	mutex_lock(&pmic->mtx);
+
+	err = i2c_smbus_write_byte(pmic->client, data);
+	if (err < 0)
+		dev_err(&pmic->client->dev, "Error setting voltage\n");
+
+	mutex_unlock(&pmic->mtx);
+	return err;
+}
+
+static int isl6271a_list_voltage(struct regulator_dev *dev, unsigned selector)
+{
+	return ISL6271A_VOLTAGE_MIN + (ISL6271A_VOLTAGE_STEP * selector);
+}
+
+static struct regulator_ops isl_core_ops = {
+	.get_voltage	= isl6271a_get_voltage,
+	.set_voltage	= isl6271a_set_voltage,
+	.list_voltage	= isl6271a_list_voltage,
+};
+
+static int isl6271a_get_fixed_voltage(struct regulator_dev *dev)
+{
+	int id = rdev_get_id(dev);
+	return (id == 1) ? 1100000 : 1300000;
+}
+
+static int isl6271a_list_fixed_voltage(struct regulator_dev *dev, unsigned selector)
+{
+	int id = rdev_get_id(dev);
+	return (id == 1) ? 1100000 : 1300000;
+}
+
+static struct regulator_ops isl_fixed_ops = {
+	.get_voltage	= isl6271a_get_fixed_voltage,
+	.list_voltage	= isl6271a_list_fixed_voltage,
+};
+
+static struct regulator_desc isl_rd[] = {
+	{
+		.name		= "Core Buck",
+		.id		= 0,
+		.n_voltages	= 16,
+		.ops		= &isl_core_ops,
+		.type		= REGULATOR_VOLTAGE,
+		.owner		= THIS_MODULE,
+	}, {
+		.name		= "LDO1",
+		.id		= 1,
+		.n_voltages	= 1,
+		.ops		= &isl_fixed_ops,
+		.type		= REGULATOR_VOLTAGE,
+		.owner		= THIS_MODULE,
+	}, {
+		.name		= "LDO2",
+		.id		= 2,
+		.n_voltages	= 1,
+		.ops		= &isl_fixed_ops,
+		.type		= REGULATOR_VOLTAGE,
+		.owner		= THIS_MODULE,
+	},
+};
+
+static int __devinit isl6271a_probe(struct i2c_client *i2c,
+				     const struct i2c_device_id *id)
+{
+	struct regulator_init_data *init_data	= i2c->dev.platform_data;
+	struct isl_pmic *pmic;
+	int err, i;
+
+	if (!i2c_check_functionality(i2c->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+		return -EIO;
+
+	if (!init_data) {
+		dev_err(&i2c->dev, "no platform data supplied\n");
+		return -EIO;
+	}
+
+	pmic = kzalloc(sizeof(struct isl_pmic), GFP_KERNEL);
+	if (!pmic)
+		return -ENOMEM;
+
+	pmic->client = i2c;
+
+	mutex_init(&pmic->mtx);
+
+	for (i = 0; i < 3; i++) {
+		pmic->rdev[i] = regulator_register(&isl_rd[0], &i2c->dev,
+						init_data, pmic);
+		if (IS_ERR(pmic->rdev[i])) {
+			dev_err(&i2c->dev, "failed to register %s\n", id->name);
+			err = PTR_ERR(pmic->rdev);
+			goto error;
+		}
+	}
+
+	i2c_set_clientdata(i2c, pmic);
+
+	return 0;
+
+error:
+	while (--i >= 0)
+		regulator_unregister(pmic->rdev[i]);
+
+	kfree(pmic);
+	return err;
+}
+
+static int __devexit isl6271a_remove(struct i2c_client *i2c)
+{
+	struct isl_pmic *pmic = i2c_get_clientdata(i2c);
+	int i;
+
+	i2c_set_clientdata(i2c, NULL);
+
+	for (i = 0; i < 3; i++)
+		regulator_unregister(pmic->rdev[i]);
+
+	kfree(pmic);
+
+	return 0;
+}
+
+static const struct i2c_device_id isl6271a_id[] = {
+	{.name = "isl6271a", 0 },
+	{ },
+};
+
+MODULE_DEVICE_TABLE(i2c, isl6271a_id);
+
+static struct i2c_driver isl6271a_i2c_driver = {
+	.driver = {
+		.name = "isl6271a",
+		.owner = THIS_MODULE,
+	},
+	.probe = isl6271a_probe,
+	.remove = __devexit_p(isl6271a_remove),
+	.id_table = isl6271a_id,
+};
+
+static int __init isl6271a_init(void)
+{
+	return i2c_add_driver(&isl6271a_i2c_driver);
+}
+
+static void __exit isl6271a_cleanup(void)
+{
+	i2c_del_driver(&isl6271a_i2c_driver);
+}
+
+subsys_initcall(isl6271a_init);
+module_exit(isl6271a_cleanup);
+
+MODULE_AUTHOR("Marek Vasut <marek.vasut at gmail.com>");
+MODULE_DESCRIPTION("Intersil ISL6271A voltage regulator driver");
+MODULE_LICENSE("GPL v2");
-- 
1.7.1



From eric.y.miao at gmail.com  Sun Jun 13 12:00:11 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 14 Jun 2010 00:00:11 +0800
Subject: [PATCH 1/2] [ARM] pxa3xx: add set_type to the ext_wakeup irq 
	chip.
In-Reply-To: <1276417909-22980-2-git-send-email-grinberg@compulab.co.il>
References: <1276417909-22980-1-git-send-email-grinberg@compulab.co.il> 
	<1276417909-22980-2-git-send-email-grinberg@compulab.co.il>
Message-ID: <AANLkTik9BRty_akndFUlsnllvNX9m375eVUzT9I8XjA8@mail.gmail.com>

On Sun, Jun 13, 2010 at 4:31 PM, Igor Grinberg <grinberg at compulab.co.il> wrote:
> pxa3xx cpu needs the irq type setup to be able to
> wakeup from low power mode on IRQ_WAKEUPx events.
>
> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
> Signed-off-by: Mike Rapoport <mike at compulab.co.il>

OK, applied.

> ---
> ?arch/arm/mach-pxa/pxa3xx.c | ? 12 ++++++++++++
> ?1 files changed, 12 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
> index f2f4127..2d54812 100644
> --- a/arch/arm/mach-pxa/pxa3xx.c
> +++ b/arch/arm/mach-pxa/pxa3xx.c
> @@ -566,11 +566,23 @@ static void pxa_unmask_ext_wakeup(unsigned int irq)
> ? ? ? ?PECR |= PECR_IE(irq - IRQ_WAKEUP0);
> ?}
>
> +static int pxa_set_ext_wakeup_type(unsigned int irq, unsigned int flow_type)
> +{
> + ? ? ? if (flow_type & IRQ_TYPE_EDGE_RISING)
> + ? ? ? ? ? ? ? PWER |= 1 << (irq - IRQ_WAKEUP0);
> +
> + ? ? ? if (flow_type & IRQ_TYPE_EDGE_FALLING)
> + ? ? ? ? ? ? ? PWER |= 1 << (irq - IRQ_WAKEUP0 + 2);
> +
> + ? ? ? return 0;
> +}
> +
> ?static struct irq_chip pxa_ext_wakeup_chip = {
> ? ? ? ?.name ? ? ? ? ? = "WAKEUP",
> ? ? ? ?.ack ? ? ? ? ? ?= pxa_ack_ext_wakeup,
> ? ? ? ?.mask ? ? ? ? ? = pxa_mask_ext_wakeup,
> ? ? ? ?.unmask ? ? ? ? = pxa_unmask_ext_wakeup,
> + ? ? ? .set_type ? ? ? = pxa_set_ext_wakeup_type,
> ?};
>
> ?static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
> --
> 1.6.4.4
>
>


From eric.y.miao at gmail.com  Sun Jun 13 12:02:22 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 14 Jun 2010 00:02:22 +0800
Subject: [PATCH 2/2] [ARM] pxa/cm-x300: enable the IRQ_WAKEUP0 as wakeup 
	source.
In-Reply-To: <1276417909-22980-3-git-send-email-grinberg@compulab.co.il>
References: <1276417909-22980-1-git-send-email-grinberg@compulab.co.il> 
	<1276417909-22980-2-git-send-email-grinberg@compulab.co.il> 
	<1276417909-22980-3-git-send-email-grinberg@compulab.co.il>
Message-ID: <AANLkTilhqoMa3qsPEYyVWKJrPHl5NnKWUhzexhPjEZaZ@mail.gmail.com>

On Sun, Jun 13, 2010 at 4:31 PM, Igor Grinberg <grinberg at compulab.co.il> wrote:
>
> Signed-off-by: Igor Grinberg <grinberg at compulab.co.il>
> Signed-off-by: Mike Rapoport <mike at compulab.co.il>

OK, applied.

> ---
> ?arch/arm/mach-pxa/cm-x300.c | ? ?1 +
> ?1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
> index fdda6be..8d227b4 100644
> --- a/arch/arm/mach-pxa/cm-x300.c
> +++ b/arch/arm/mach-pxa/cm-x300.c
> @@ -689,6 +689,7 @@ static void __init cm_x300_init_da9030(void)
> ?{
> ? ? ? ?pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info);
> ? ? ? ?i2c_register_board_info(1, &cm_x300_pmic_info, 1);
> + ? ? ? set_irq_wake(IRQ_WAKEUP0, 1);
> ?}
>
> ?static void __init cm_x300_init_wi2wi(void)
> --
> 1.6.4.4
>
>


From eric.y.miao at gmail.com  Sun Jun 13 12:42:45 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 14 Jun 2010 00:42:45 +0800
Subject: [PATCH] pxa168 and pxa930 build fix - plat-pxa/pmu.c dependent on
	ARCH_PXA for IRQ_PMU
In-Reply-To: <3623778261485640027@unknownmsgid>
References: <1275932959-474-1-git-send-email-jic23@cam.ac.uk> 
	<AANLkTilXErDZHWf71e7pwUbt1i66MVrfP_lPisgoBZ0G@mail.gmail.com> 
	<AANLkTinm5ZU1tLR8CYwU4K8FPbCdLTdAyrfXq54nYkl_@mail.gmail.com> 
	<3623778261485640027@unknownmsgid>
Message-ID: <AANLkTik2JD4y1-4Dt5999adu4mtNAAS9DLu9sG77l56u@mail.gmail.com>

On Tue, Jun 8, 2010 at 4:52 PM, Will Deacon <will.deacon at arm.com> wrote:
> Hi Eric,
>
>> We have different ways to handle this:
>>
>> 1. register different platform devices with different IRQs for pxa[23]xx, pxa168
>> 2. modify the IRQ at run-time to a correct one
>> 3. move the platform device registration back into arch/arm/mach-pxa/<soc>.c
>> (or arch/arm/mach-pxa/common.c) and arch/arm/mach-mmp/<soc>.c
>
> For the RealView boards, we take approach number (1). This is largely for two
> reasons:
>
> 1.) The PMU IRQ doesn't have a consistent naming scheme
> 2.) SMP RealView platforms need to have an extra resource in the
> ? ?platform_device for each CPU.
>
> However, looking at the PXA168 description and the perf-events code,
> I don't think we support the PMU anyway [see init_hw_perf_events in
> arch/arm/kernel/perf_event.c]. If the PMU present is accessible in the
> same way as one of the other supported PMUs, then it would be easy to
> add it to the perf-events code. Otherwise, a new PMU driver will need
> to be written if people want to use it.
>
> Without access to a TRM, I can't tell whether or not supporting the PMU
> is trivial, so I guess we go with option (3) for the time being.
>
>> We need to figure out if there are some other differences between these
>> PMUs (or in the future), which will make solution 3) stand out.
>
> In the future I reckon PMU devices will be memory-mapped and live inside
> components other than the CPU. PMU registration will then be highly SoC-specific.
> Perf events doesn't yet support any of this, so it depends how future-proof you
> want to be!
>

For a quick solution of the build error, I decided to pick Jonathan's
patch first. At least PMU is not tested and ever used on pxa168/910/mmp2
series at this moment. I'll work on a proper fix later, possibly a patch
merged through -devel branch instead of -fix.

>
>> >> ?arch/arm/plat-pxa/Makefile | ? ?3 ++-
>> >> ?1 files changed, 2 insertions(+), 1 deletions(-)
>> >>
>> >> diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
>> >> index 6187edf..a17cc0c 100644
>> >> --- a/arch/arm/plat-pxa/Makefile
>> >> +++ b/arch/arm/plat-pxa/Makefile
>> >> @@ -2,8 +2,9 @@
>> >> ?# Makefile for code common across different PXA processor families
>> >> ?#
>> >>
>> >> -obj-y ?:= dma.o pmu.o
>> >> +obj-y ?:= dma.o
>> >>
>> >> +obj-$(CONFIG_ARCH_PXA) ? ? ? ? += pmu.o
>> >> ?obj-$(CONFIG_GENERIC_GPIO) ? ? += gpio.o
>> >> ?obj-$(CONFIG_PXA3xx) ? ? ? ? ? += mfp.o
>> >> ?obj-$(CONFIG_ARCH_MMP) ? ? ? ? += mfp.o
>> >> --
>> >> 1.6.4.4
>
>
>


From mcuos.com at gmail.com  Sun Jun 13 12:51:32 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Mon, 14 Jun 2010 00:51:32 +0800
Subject: [PATCH] pxa168 and pxa930 build fix - plat-pxa/pmu.c dependent on
	ARCH_PXA for IRQ_PMU
In-Reply-To: <AANLkTik2JD4y1-4Dt5999adu4mtNAAS9DLu9sG77l56u@mail.gmail.com>
References: <1275932959-474-1-git-send-email-jic23@cam.ac.uk>
	<AANLkTilXErDZHWf71e7pwUbt1i66MVrfP_lPisgoBZ0G@mail.gmail.com>
	<AANLkTinm5ZU1tLR8CYwU4K8FPbCdLTdAyrfXq54nYkl_@mail.gmail.com>
	<3623778261485640027@unknownmsgid>
	<AANLkTik2JD4y1-4Dt5999adu4mtNAAS9DLu9sG77l56u@mail.gmail.com>
Message-ID: <AANLkTinHL6q_Nbed237cuoCNy1DUCGTGXQG6np-tZtS-@mail.gmail.com>

2010/6/14 Eric Miao <eric.y.miao at gmail.com>:
> On Tue, Jun 8, 2010 at 4:52 PM, Will Deacon <will.deacon at arm.com> wrote:
>> Hi Eric,
>>
>>> We have different ways to handle this:
>>>
>>> 1. register different platform devices with different IRQs for pxa[23]xx, pxa168
>>> 2. modify the IRQ at run-time to a correct one
>>> 3. move the platform device registration back into arch/arm/mach-pxa/<soc>.c
>>> (or arch/arm/mach-pxa/common.c) and arch/arm/mach-mmp/<soc>.c
>>
>> For the RealView boards, we take approach number (1). This is largely for two
>> reasons:
>>
>> 1.) The PMU IRQ doesn't have a consistent naming scheme
>> 2.) SMP RealView platforms need to have an extra resource in the
>> ? ?platform_device for each CPU.
>>
>> However, looking at the PXA168 description and the perf-events code,
>> I don't think we support the PMU anyway [see init_hw_perf_events in
>> arch/arm/kernel/perf_event.c]. If the PMU present is accessible in the
>> same way as one of the other supported PMUs, then it would be easy to
>> add it to the perf-events code. Otherwise, a new PMU driver will need
>> to be written if people want to use it.
>>
>> Without access to a TRM, I can't tell whether or not supporting the PMU
>> is trivial, so I guess we go with option (3) for the time being.
>>
>>> We need to figure out if there are some other differences between these
>>> PMUs (or in the future), which will make solution 3) stand out.
>>
>> In the future I reckon PMU devices will be memory-mapped and live inside
>> components other than the CPU. PMU registration will then be highly SoC-specific.
>> Perf events doesn't yet support any of this, so it depends how future-proof you
>> want to be!
>>
>
> For a quick solution of the build error, I decided to pick Jonathan's
> patch first. At least PMU is not tested and ever used on pxa168/910/mmp2
> series at this moment. I'll work on a proper fix later, possibly a patch
> merged through -devel branch instead of -fix.
>

Good idea. thanks!

>>
>>> >> ?arch/arm/plat-pxa/Makefile | ? ?3 ++-
>>> >> ?1 files changed, 2 insertions(+), 1 deletions(-)
>>> >>
>>> >> diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
>>> >> index 6187edf..a17cc0c 100644
>>> >> --- a/arch/arm/plat-pxa/Makefile
>>> >> +++ b/arch/arm/plat-pxa/Makefile
>>> >> @@ -2,8 +2,9 @@
>>> >> ?# Makefile for code common across different PXA processor families
>>> >> ?#
>>> >>
>>> >> -obj-y ?:= dma.o pmu.o
>>> >> +obj-y ?:= dma.o
>>> >>
>>> >> +obj-$(CONFIG_ARCH_PXA) ? ? ? ? += pmu.o
>>> >> ?obj-$(CONFIG_GENERIC_GPIO) ? ? += gpio.o
>>> >> ?obj-$(CONFIG_PXA3xx) ? ? ? ? ? += mfp.o
>>> >> ?obj-$(CONFIG_ARCH_MMP) ? ? ? ? += mfp.o
>>> >> --
>>> >> 1.6.4.4
>>
>>
>>
>



-- 
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mail addr:linux-arm-kernel at lists.infradead.org
you can subscribe by:
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

* linux-arm-NUC900 mailing list
mail addr:NUC900 at googlegroups.com
main web: https://groups.google.com/group/NUC900
you can subscribe it by sending me mail:
mcuos.com at gmail.com


From mcuos.com at gmail.com  Sun Jun 13 13:24:12 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Mon, 14 Jun 2010 01:24:12 +0800
Subject: [PATCH 1/2] NUC900:  Add i2c0 driver support for NUC900
Message-ID: <4C15143C.1020603@gmail.com>

This patch is to add i2c0 driver support for NUC900.

Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>

---
 arch/arm/mach-w90x900/include/mach/i2c.h |   11 +
 drivers/i2c/busses/Kconfig               |    7 +
 drivers/i2c/busses/Makefile              |    1 +
 drivers/i2c/busses/i2c-nuc900.c          |  699 ++++++++++++++++++++++++++++++
 4 files changed, 718 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-w90x900/include/mach/i2c.h
 create mode 100644 drivers/i2c/busses/i2c-nuc900.c

diff --git a/arch/arm/mach-w90x900/include/mach/i2c.h b/arch/arm/mach-w90x900/include/mach/i2c.h
new file mode 100644
index 0000000..292f3f9
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/i2c.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_ARCH_NUC900_I2C_H
+#define __ASM_ARCH_NUC900_I2C_H
+
+struct nuc900_platform_i2c {
+	int		bus_num;
+	unsigned long   bus_freq;
+	void	(*get_clock)(unsigned int *cpuclk_khz,
+			unsigned int *ahbclk_khz, unsigned int *apbclk_khz);
+};
+
+#endif /* __ASM_ARCH_NUC900_I2C_H */
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index bceafbf..ee284d2 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -448,6 +448,13 @@ config I2C_NOMADIK
 	  If you say yes to this option, support will be included for the
 	  I2C interface from ST-Ericsson's Nomadik and Ux500 architectures.

+config I2C_NUC900
+	tristate "NUC900 I2C Driver"
+	depends on ARCH_W90X900
+	help
+	  Say Y here to include support for I2C controller in the
+	  Winbond/Nuvoton NUC900 based System-on-Chip devices.
+
 config I2C_OCORES
 	tristate "OpenCores I2C Controller"
 	depends on EXPERIMENTAL
diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
index 936880b..c3ef492 100644
--- a/drivers/i2c/busses/Makefile
+++ b/drivers/i2c/busses/Makefile
@@ -43,6 +43,7 @@ obj-$(CONFIG_I2C_IXP2000)	+= i2c-ixp2000.o
 obj-$(CONFIG_I2C_MPC)		+= i2c-mpc.o
 obj-$(CONFIG_I2C_MV64XXX)	+= i2c-mv64xxx.o
 obj-$(CONFIG_I2C_NOMADIK)	+= i2c-nomadik.o
+obj-$(CONFIG_I2C_NUC900)	+= i2c-nuc900.o
 obj-$(CONFIG_I2C_OCORES)	+= i2c-ocores.o
 obj-$(CONFIG_I2C_OMAP)		+= i2c-omap.o
 obj-$(CONFIG_I2C_PASEMI)	+= i2c-pasemi.o
diff --git a/drivers/i2c/busses/i2c-nuc900.c b/drivers/i2c/busses/i2c-nuc900.c
new file mode 100644
index 0000000..c8e043a
--- /dev/null
+++ b/drivers/i2c/busses/i2c-nuc900.c
@@ -0,0 +1,699 @@
+/*
+ * linux/drivers/i2c/busses/i2c-nuc900.c
+ *
+ * Copyright (c) 2010 Nuvoton technology corporation.
+ *
+ * This driver based on S3C2410 I2C Controller of Ben Dooks <ben at simtec.co.uk>.
+ * Written by Wan ZongShun <mcuos.com at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c-id.h>
+#include <linux/init.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+#include <mach/mfp.h>
+#include <mach/i2c.h>
+
+#define CSR		0x00
+#define DIVIDER		0x04
+#define CMDR		0x08
+#define SWR		0x0C
+#define RXR		0x10
+#define TXR		0x14
+
+#define IRQEN		0x003
+#define I2CBUSY		0x400
+#define I2CSTART	0x018
+
+#define I2C_CMD_START	0x10
+#define I2C_CMD_STOP	0x08
+#define I2C_CMD_READ	0x04
+#define I2C_CMD_WRITE	0x02
+#define I2C_CMD_NACK	0x01
+
+#define IRQFLAG		0x004
+#define ARBIT_LOST	0x200
+#define SLAVE_ACK	0x800
+
+/* i2c controller state */
+
+enum nuc900_i2c_state {
+	STATE_IDLE,
+	STATE_START,
+	STATE_READ,
+	STATE_WRITE,
+	STATE_STOP
+};
+
+struct nuc900_i2c {
+	spinlock_t		lock;
+	wait_queue_head_t	wait;
+
+	struct i2c_msg		*msg;
+	unsigned int		msg_num;
+	unsigned int		msg_idx;
+	unsigned int		msg_ptr;
+	unsigned int		irq;
+
+	enum nuc900_i2c_state	state;
+
+	void __iomem		*regs;
+	struct clk		*clk;
+	struct device		*dev;
+	struct resource		*ioarea;
+	struct i2c_adapter	adap;
+};
+
+/* nuc900_i2c_master_complete
+ *
+ * complete the message and wake up the caller, using the given return code,
+ * or zero to mean ok.
+*/
+
+static inline void nuc900_i2c_master_complete(struct nuc900_i2c *i2c, int ret)
+{
+	dev_dbg(i2c->dev, "master_complete %d\n", ret);
+
+	i2c->msg_ptr = 0;
+	i2c->msg = NULL;
+	i2c->msg_idx++;
+	i2c->msg_num = 0;
+	if (ret)
+		i2c->msg_idx = ret;
+
+	wake_up(&i2c->wait);
+}
+
+/* irq enable/disable functions */
+
+static inline void nuc900_i2c_disable_irq(struct nuc900_i2c *i2c)
+{
+	unsigned long tmp;
+
+	tmp = readl(i2c->regs + CSR);
+	writel(tmp & ~IRQEN, i2c->regs + CSR);
+}
+
+static inline void nuc900_i2c_enable_irq(struct nuc900_i2c *i2c)
+{
+	unsigned long tmp;
+
+	tmp = readl(i2c->regs + CSR);
+	writel(tmp | IRQEN, i2c->regs + CSR);
+}
+
+
+/* nuc900_i2c_message_start
+ *
+ * put the start of a message onto the bus
+*/
+
+static void nuc900_i2c_message_start(struct nuc900_i2c *i2c,
+				      struct i2c_msg *msg)
+{
+	unsigned int addr = (msg->addr & 0x7f) << 1;
+
+	if (msg->flags & I2C_M_RD)
+		addr |= 0x1;
+	writel(addr & 0xff, i2c->regs + TXR);
+	writel(I2C_CMD_START | I2C_CMD_WRITE, i2c->regs + CMDR);
+}
+
+static inline void nuc900_i2c_stop(struct nuc900_i2c *i2c, int ret)
+{
+
+	dev_dbg(i2c->dev, "STOP\n");
+
+	/* stop the transfer */
+	i2c->state = STATE_STOP;
+	writel(I2C_CMD_STOP, i2c->regs + CMDR);
+
+	nuc900_i2c_master_complete(i2c, ret);
+	nuc900_i2c_disable_irq(i2c);
+}
+
+/* helper functions to determine the current state in the set of
+ * messages we are sending */
+
+/* is_lastmsg()
+ *
+ * returns TRUE if the current message is the last in the set
+*/
+
+static inline int is_lastmsg(struct nuc900_i2c *i2c)
+{
+	return i2c->msg_idx >= (i2c->msg_num - 1);
+}
+
+/* is_msglast
+ *
+ * returns TRUE if we this is the last byte in the current message
+*/
+
+static inline int is_msglast(struct nuc900_i2c *i2c)
+{
+	return i2c->msg_ptr == i2c->msg->len-1;
+}
+
+/* is_msgend
+ *
+ * returns TRUE if we reached the end of the current message
+*/
+
+static inline int is_msgend(struct nuc900_i2c *i2c)
+{
+	return i2c->msg_ptr >= i2c->msg->len;
+}
+
+/* i2s_s3c_irq_nextbyte
+ *
+ * process an interrupt and work out what to do
+ */
+
+static int i2s_nuc900_irq_nextbyte(struct nuc900_i2c *i2c,
+							unsigned long iicstat)
+{
+	unsigned char byte;
+	int ret = 0;
+
+	switch (i2c->state) {
+
+	case STATE_IDLE:
+		dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
+		break;
+
+	case STATE_STOP:
+		dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
+		nuc900_i2c_disable_irq(i2c);
+		break;
+
+	case STATE_START:
+		/* last thing we did was send a start condition on the
+		 * bus, or started a new i2c message
+		 */
+
+		if (iicstat & SLAVE_ACK &&
+		    !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
+			/* ack was not received... */
+
+			dev_dbg(i2c->dev, "ack was not received\n");
+			nuc900_i2c_stop(i2c, -ENXIO);
+			goto out;
+		}
+
+		if (i2c->msg->flags & I2C_M_RD)
+			i2c->state = STATE_READ;
+		else
+			i2c->state = STATE_WRITE;
+
+		/* terminate the transfer if there is nothing to do
+		 * as this is used by the i2c probe to find devices. */
+
+		if (is_lastmsg(i2c) && i2c->msg->len == 0) {
+			nuc900_i2c_stop(i2c, 0);
+			goto out;
+		}
+
+		if (i2c->state == STATE_READ)
+			goto prepare_read;
+
+		/* fall through to the write state, as we will need to
+		 * send a byte as well */
+
+	case STATE_WRITE:
+		/* we are writing data to the device... check for the
+		 * end of the message, and if so, work out what to do
+		 */
+
+		if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
+			if (iicstat & SLAVE_ACK) {
+				dev_dbg(i2c->dev, "WRITE: No Ack\n");
+
+				nuc900_i2c_stop(i2c, -ECONNREFUSED);
+				goto out;
+			}
+		}
+
+retry_write:
+
+		if (!is_msgend(i2c)) {
+			byte = i2c->msg->buf[i2c->msg_ptr++];
+			writeb(byte, i2c->regs + TXR);
+			writel(I2C_CMD_WRITE, i2c->regs + CMDR);
+
+		} else if (!is_lastmsg(i2c)) {
+			/* we need to go to the next i2c message */
+
+			dev_dbg(i2c->dev, "WRITE: Next Message\n");
+
+			i2c->msg_ptr = 0;
+			i2c->msg_idx++;
+			i2c->msg++;
+
+			/* check to see if we need to do another message */
+			if (i2c->msg->flags & I2C_M_NOSTART) {
+
+				if (i2c->msg->flags & I2C_M_RD) {
+					/* cannot do this, the controller
+					 * forces us to send a new START
+					 * when we change direction */
+
+					nuc900_i2c_stop(i2c, -EINVAL);
+				}
+
+				goto retry_write;
+			} else {
+				/* send the new start */
+				nuc900_i2c_message_start(i2c, i2c->msg);
+				i2c->state = STATE_START;
+			}
+
+		} else {
+			/* send stop */
+
+			nuc900_i2c_stop(i2c, 0);
+		}
+		break;
+
+	case STATE_READ:
+		/* we have a byte of data in the data register, do
+		 * something with it, and then work out wether we are
+		 * going to do any more read/write
+		 */
+
+		byte = readb(i2c->regs + RXR);
+		i2c->msg->buf[i2c->msg_ptr++] = byte;
+
+prepare_read:
+		if (is_msglast(i2c)) {
+			/* last byte of buffer */
+
+			if (is_lastmsg(i2c))
+				writel(I2C_CMD_READ | I2C_CMD_NACK,
+							i2c->regs + CMDR);
+
+		} else if (is_msgend(i2c)) {
+			/* ok, we've read the entire buffer, see if there
+			 * is anything else we need to do */
+
+			if (is_lastmsg(i2c)) {
+				/* last message, send stop and complete */
+				dev_dbg(i2c->dev, "READ: Send Stop\n");
+
+				nuc900_i2c_stop(i2c, 0);
+			} else {
+				/* go to the next transfer */
+				dev_dbg(i2c->dev, "READ: Next Transfer\n");
+
+				i2c->msg_ptr = 0;
+				i2c->msg_idx++;
+				i2c->msg++;
+
+				writel(I2C_CMD_READ, i2c->regs + CMDR);
+			}
+
+		} else {
+			writel(I2C_CMD_READ, i2c->regs + CMDR);
+		}
+
+		break;
+	}
+
+ out:
+	return ret;
+}
+
+/* nuc900_i2c_irq
+ *
+ * top level IRQ servicing routine
+*/
+
+static irqreturn_t nuc900_i2c_irq(int irqno, void *dev_id)
+{
+	struct nuc900_i2c *i2c = dev_id;
+	unsigned long status;
+
+	status = readl(i2c->regs + CSR);
+	writel(status | IRQFLAG, i2c->regs + CSR);
+
+	if (status & ARBIT_LOST) {
+		/* deal with arbitration loss */
+		dev_err(i2c->dev, "deal with arbitration loss\n");
+		goto out;
+	}
+
+	if (i2c->state == STATE_IDLE) {
+		dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
+		goto out;
+	}
+
+	/* pretty much this leaves us with the fact that we've
+	 * transmitted or received whatever byte we last sent */
+
+	i2s_nuc900_irq_nextbyte(i2c, status);
+
+ out:
+	return IRQ_HANDLED;
+}
+
+
+/* nuc900_i2c_set_master
+ *
+ * get the i2c bus for a master transaction
+*/
+
+static int nuc900_i2c_set_master(struct nuc900_i2c *i2c)
+{
+	int timeout = 400;
+
+	while (timeout-- > 0) {
+		if (((readl(i2c->regs + SWR) & I2CSTART) == I2CSTART) &&
+				((readl(i2c->regs + CSR) & I2CBUSY) == 0)) {
+			return 0;
+		}
+
+		msleep(1);
+	}
+
+	return -ETIMEDOUT;
+}
+
+/* nuc900_i2c_doxfer
+ *
+ * this starts an i2c transfer
+*/
+
+static int nuc900_i2c_doxfer(struct nuc900_i2c *i2c,
+			      struct i2c_msg *msgs, int num)
+{
+	unsigned long iicstat, timeout;
+	int spins = 20;
+	int ret;
+
+	ret = nuc900_i2c_set_master(i2c);
+	if (ret != 0) {
+		dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
+		ret = -EAGAIN;
+		goto out;
+	}
+
+	spin_lock_irq(&i2c->lock);
+
+	i2c->msg     = msgs;
+	i2c->msg_num = num;
+	i2c->msg_ptr = 0;
+	i2c->msg_idx = 0;
+	i2c->state   = STATE_START;
+
+	nuc900_i2c_enable_irq(i2c);
+	nuc900_i2c_message_start(i2c, msgs);
+	spin_unlock_irq(&i2c->lock);
+
+	timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
+
+	ret = i2c->msg_idx;
+
+	/* having these next two as dev_err() makes life very
+	 * noisy when doing an i2cdetect */
+
+	if (timeout == 0)
+		dev_dbg(i2c->dev, "timeout\n");
+	else if (ret != num)
+		dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
+
+	/* ensure the stop has been through the bus */
+
+	dev_dbg(i2c->dev, "waiting for bus idle\n");
+
+	/* first, try busy waiting briefly */
+	do {
+		iicstat = readl(i2c->regs + CSR);
+	} while ((iicstat & I2CBUSY) && --spins);
+
+	/* if that timed out sleep */
+	if (!spins) {
+		msleep(1);
+		iicstat = readl(i2c->regs + CSR);
+	}
+
+	if (iicstat & I2CBUSY)
+		dev_warn(i2c->dev, "timeout waiting for bus idle\n");
+
+ out:
+	return ret;
+}
+
+/* nuc900_i2c_xfer
+ *
+ * first port of call from the i2c bus code when an message needs
+ * transferring across the i2c bus.
+*/
+
+static int nuc900_i2c_xfer(struct i2c_adapter *adap,
+			struct i2c_msg *msgs, int num)
+{
+	struct nuc900_i2c *i2c = (struct nuc900_i2c *)adap->algo_data;
+	int retry;
+	int ret;
+
+	for (retry = 0; retry < adap->retries; retry++) {
+
+		ret = nuc900_i2c_doxfer(i2c, msgs, num);
+
+		if (ret != -EAGAIN)
+			return ret;
+
+		dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
+
+		udelay(100);
+	}
+
+	return -EREMOTEIO;
+}
+
+/* declare our i2c functionality */
+static u32 nuc900_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
+}
+
+/* i2c bus registration info */
+
+static const struct i2c_algorithm nuc900_i2c_algorithm = {
+	.master_xfer		= nuc900_i2c_xfer,
+	.functionality		= nuc900_i2c_func,
+};
+
+/* nuc900_i2c_probe
+ *
+ * called by the bus driver when a suitable device is found
+*/
+
+static int __devinit nuc900_i2c_probe(struct platform_device *pdev)
+{
+	struct nuc900_i2c *i2c;
+	struct nuc900_platform_i2c *pdata;
+	struct resource *res;
+	unsigned int apbclk_khz;
+	int ret;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "no platform data\n");
+		return -EINVAL;
+	}
+
+	i2c = kzalloc(sizeof(struct nuc900_i2c), GFP_KERNEL);
+	if (!i2c) {
+		dev_err(&pdev->dev, "no memory for state\n");
+		return -ENOMEM;
+	}
+
+	strlcpy(i2c->adap.name, "nuc900-i2c0", sizeof(i2c->adap.name));
+	i2c->adap.owner   = THIS_MODULE;
+	i2c->adap.algo    = &nuc900_i2c_algorithm;
+	i2c->adap.retries = 2;
+	i2c->adap.class   = I2C_CLASS_HWMON | I2C_CLASS_SPD;
+
+	spin_lock_init(&i2c->lock);
+	init_waitqueue_head(&i2c->wait);
+
+	/* find the clock and enable it */
+
+	i2c->dev = &pdev->dev;
+	i2c->clk = clk_get(&pdev->dev, "nuc900-i2c0");
+	if (IS_ERR(i2c->clk)) {
+		dev_err(&pdev->dev, "cannot get clock\n");
+		ret = -ENOENT;
+		goto err_noclk;
+	}
+
+	dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
+
+	clk_enable(i2c->clk);
+
+	/* map the registers */
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(&pdev->dev, "cannot find IO resource\n");
+		ret = -ENOENT;
+		goto err_clk;
+	}
+
+	i2c->ioarea = request_mem_region(res->start, resource_size(res),
+					 pdev->name);
+
+	if (i2c->ioarea == NULL) {
+		dev_err(&pdev->dev, "cannot request IO\n");
+		ret = -ENXIO;
+		goto err_clk;
+	}
+
+	i2c->regs = ioremap(res->start, resource_size(res));
+
+	if (i2c->regs == NULL) {
+		dev_err(&pdev->dev, "cannot map IO\n");
+		ret = -ENXIO;
+		goto err_ioarea;
+	}
+
+	dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
+		i2c->regs, i2c->ioarea, res);
+
+	/* setup info block for the i2c core */
+
+	i2c->adap.algo_data = i2c;
+	i2c->adap.dev.parent = &pdev->dev;
+
+	mfp_set_groupg(&pdev->dev);
+
+	pdata->get_clock(NULL, NULL, &apbclk_khz);
+
+	ret = apbclk_khz/(pdata->bus_freq * 5) - 1;
+	writel(ret & 0xffff, i2c->regs + DIVIDER);
+
+	/* find the IRQ for this unit (note, this relies on the init call to
+	 * ensure no current IRQs pending
+	 */
+
+	i2c->irq = ret = platform_get_irq(pdev, 0);
+	if (ret <= 0) {
+		dev_err(&pdev->dev, "cannot find IRQ\n");
+		goto err_iomap;
+	}
+
+	ret = request_irq(i2c->irq, nuc900_i2c_irq, IRQF_DISABLED,
+			  dev_name(&pdev->dev), i2c);
+
+	if (ret != 0) {
+		dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
+		goto err_iomap;
+	}
+
+	/* Note, previous versions of the driver used i2c_add_adapter()
+	 * to add the bus at any number. We now pass the bus number via
+	 * the platform data, so if unset it will now default to always
+	 * being bus 0.
+	 */
+
+	i2c->adap.nr = pdata->bus_num;
+
+	ret = i2c_add_numbered_adapter(&i2c->adap);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to add bus to i2c core\n");
+		goto err_irq;
+	}
+
+	platform_set_drvdata(pdev, i2c);
+
+	dev_info(&pdev->dev, "%s: NUC900 I2C adapter\n",
+						dev_name(&i2c->adap.dev));
+	return 0;
+
+ err_irq:
+	free_irq(i2c->irq, i2c);
+
+ err_iomap:
+	iounmap(i2c->regs);
+
+ err_ioarea:
+	release_resource(i2c->ioarea);
+	kfree(i2c->ioarea);
+
+ err_clk:
+	clk_disable(i2c->clk);
+	clk_put(i2c->clk);
+
+ err_noclk:
+	kfree(i2c);
+	return ret;
+}
+
+/* nuc900_i2c_remove
+ *
+ * called when device is removed from the bus
+*/
+
+static int __devexit nuc900_i2c_remove(struct platform_device *pdev)
+{
+	struct nuc900_i2c *i2c = platform_get_drvdata(pdev);
+
+	i2c_del_adapter(&i2c->adap);
+	free_irq(i2c->irq, i2c);
+
+	clk_disable(i2c->clk);
+	clk_put(i2c->clk);
+
+	iounmap(i2c->regs);
+
+	release_resource(i2c->ioarea);
+	kfree(i2c->ioarea);
+	kfree(i2c);
+
+	return 0;
+}
+
+static struct platform_driver nuc900_i2c_driver = {
+	.probe		= nuc900_i2c_probe,
+	.remove		= __devexit_p(nuc900_i2c_remove),
+	.driver		= {
+		.owner	= THIS_MODULE,
+		.name	= "nuc900-i2c0",
+	},
+};
+
+static int __init i2c_adap_nuc900_init(void)
+{
+	return platform_driver_register(&nuc900_i2c_driver);
+}
+
+static void __exit i2c_adap_nuc900_exit(void)
+{
+	platform_driver_unregister(&nuc900_i2c_driver);
+}
+subsys_initcall(i2c_adap_nuc900_init);
+module_exit(i2c_adap_nuc900_exit);
+
+MODULE_DESCRIPTION("NUC900 I2C Bus driver");
+MODULE_AUTHOR("Wan ZongShun, <mcuos.com at gmail.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:nuc900-i2c0");
-- 
1.6.3.3


From mcuos.com at gmail.com  Sun Jun 13 13:28:34 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Mon, 14 Jun 2010 01:28:34 +0800
Subject: [PATCH 2/2] NUC900: Add platform support for nuc900 i2c driver
Message-ID: <4C151542.5000609@gmail.com>

This patch is to add platform support for i2c driver.
For get i2c work clock, I implemented the 'nuc900_get_cpuclock'
api for getting cpu,apb,ahb clock.

Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
---
 arch/arm/mach-w90x900/cpu.c |   43 +++++++++++++++++++++++++++++++++
 arch/arm/mach-w90x900/cpu.h |    3 +-
 arch/arm/mach-w90x900/dev.c |   56 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 101 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 642207e..2396548 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -195,6 +195,49 @@ static int __init nuc900_set_cpufreq(char *str)

 __setup("cpufreq=", nuc900_set_cpufreq);

+void nuc900_get_cpuclock(unsigned int *cpuclk_khz,
+			unsigned int *ahbclk_khz, unsigned int *apbclk_khz) {
+
+	int ahbspeed = 0, apbspeed = 0, cpuspeed = 0;
+
+	if (cpuclk_khz) {
+		cpuspeed = __raw_readl(REG_PLLCON0);
+		if (cpuspeed == PLL_200MHZ)
+			cpuspeed = 200 * 1000;
+		else if (cpuspeed == PLL_166MHZ)
+			cpuspeed = 166 * 1000;
+		else if (cpuspeed == PLL_120MHZ)
+			cpuspeed = 120 * 1000;
+		else if (cpuspeed == PLL_100MHZ)
+			cpuspeed = 100 * 1000;
+		else if (cpuspeed == PLL_66MHZ)
+			cpuspeed = 66 * 1000;
+		else
+			printk(KERN_ERR "Can not read true cpuspeed!\n");
+		*cpuclk_khz = cpuspeed;
+	}
+
+	if (ahbclk_khz) {
+		ahbspeed = (__raw_readl(REG_CLKDIV) >> 24) & 0x03;
+		if (ahbspeed == AHB_CPUCLK_1_1)
+			ahbspeed = cpuspeed;
+		else if (ahbspeed == AHB_CPUCLK_1_2)
+			ahbspeed = cpuspeed / 2;
+		else
+			printk(KERN_ERR "Can not read true ahbspeed!\n");
+		*ahbclk_khz = ahbspeed;
+	}
+
+	if (apbclk_khz) {
+		apbspeed = (__raw_readl(REG_CLKDIV) >> 26) & 0x03;
+		if (apbspeed == APB_AHB_1_2)
+			apbspeed = ahbspeed / 2;
+		else
+			printk(KERN_ERR "Can not read true apbspeed!\n");
+		*apbclk_khz = apbspeed;
+	}
+}
+
 /*Init NUC900 evb io*/

 void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size)
diff --git a/arch/arm/mach-w90x900/cpu.h b/arch/arm/mach-w90x900/cpu.h
index f8730b6..00217ad 100644
--- a/arch/arm/mach-w90x900/cpu.h
+++ b/arch/arm/mach-w90x900/cpu.h
@@ -49,7 +49,8 @@ extern void nuc900_clock_source(struct device *dev, unsigned char *src);
 extern void nuc900_init_clocks(void);
 extern void nuc900_map_io(struct map_desc *mach_desc, int mach_size);
 extern void nuc900_board_init(struct platform_device **device, int size);
-
+extern void nuc900_get_cpuclock(unsigned int *cpuclk_khz,
+			unsigned int *ahbclk_khz, unsigned int *apbclk_khz);
 /* for either public between 910 and 920, or between 920 and 950 */

 extern struct platform_device nuc900_serial_device;
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
index b2eda4d..7287002 100644
--- a/arch/arm/mach-w90x900/dev.c
+++ b/arch/arm/mach-w90x900/dev.c
@@ -36,6 +36,7 @@
 #include <mach/nuc900_spi.h>
 #include <mach/map.h>
 #include <mach/fb.h>
+#include <mach/i2c.h>

 #include "cpu.h"

@@ -45,6 +46,7 @@
 #define NUC900_FLASH_SIZE	0x400000
 #define SPIOFFSET		0x200
 #define SPIOREG_SIZE		0x100
+#define I2C_SIZE		0x100

 static struct mtd_partition nuc900_flash_partitions[] = {
 	{
@@ -450,6 +452,59 @@ struct platform_device nuc900_device_audio = {
 	}
 };

+/* I2C0, I2C1 controller */
+
+static struct nuc900_platform_i2c nuc900_i2c0_data = {
+	.bus_num	=	0,
+	.bus_freq	=	100,
+	.get_clock	=	nuc900_get_cpuclock,
+};
+
+static struct resource nuc900_i2c0_resource[] = {
+	[0] = {
+		.start = W90X900_PA_I2C,
+		.end   = W90X900_PA_I2C + I2C_SIZE - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_I2CGROUP,
+		.end   = IRQ_I2CGROUP,
+		.flags = IORESOURCE_IRQ,
+	}
+
+};
+
+struct platform_device nuc900_device_i2c0 = {
+	.name		  = "nuc900-i2c0",
+	.id		  = -1,
+	.num_resources	  = ARRAY_SIZE(nuc900_i2c0_resource),
+	.resource	  = nuc900_i2c0_resource,
+	.dev		= {
+				.platform_data = &nuc900_i2c0_data,
+			}
+};
+
+static struct resource nuc900_i2c1_resource[] = {
+	[0] = {
+		.start = W90X900_PA_I2C,
+		.end   = W90X900_PA_I2C + 2*I2C_SIZE - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_I2CGROUP,
+		.end   = IRQ_I2CGROUP,
+		.flags = IORESOURCE_IRQ,
+	}
+
+};
+
+struct platform_device nuc900_device_i2c1 = {
+	.name		  = "nuc900-i2c1",
+	.id		  = -1,
+	.num_resources	  = ARRAY_SIZE(nuc900_i2c1_resource),
+	.resource	  = nuc900_i2c1_resource,
+};
+
 /*Here should be your evb resourse,such as LCD*/

 static struct platform_device *nuc900_public_dev[] __initdata = {
@@ -462,6 +517,7 @@ static struct platform_device *nuc900_public_dev[] __initdata = {
 	&nuc900_device_spi,
 	&nuc900_device_wdt,
 	&nuc900_device_audio,
+	&nuc900_device_i2c0,
 };

 /* Provide adding specific CPU platform devices API */
-- 
1.6.3.3


From tbm at cyrius.com  Sun Jun 13 14:37:18 2010
From: tbm at cyrius.com (Martin Michlmayr)
Date: Sun, 13 Jun 2010 19:37:18 +0100
Subject: [PATCH] Kirkwood: Add MPP44 (board ID) on TS-219
Message-ID: <20100613183718.GA6929@jirafa.cyrius.com>

MPP44 can be used to differentiate between one-bay (TS-11x) and
two-bay (TS-21x) devices.

According to an engineer from QNAP, the setting of MPP44 depends
on the firmware rather than hardware.  Presumably, this means
that you could fake the MPP44 value by changing the boot loader.

Signed-off-by: Martin Michlmayr <tbm at cyrius.com>

diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0f..40ed723 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -83,6 +83,7 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
 	MPP15_GPIO,		/* USB Copy button */
 	MPP16_GPIO,		/* Reset button */
 	MPP36_GPIO,		/* RAM: 0: 256 MB, 1: 512 MB */
+	MPP44_GPIO,		/* Board ID: 0: TS-11x, 1: TS-21x */
 	0
 };
 

-- 
Martin Michlmayr
http://www.cyrius.com/


From tbm at cyrius.com  Sun Jun 13 15:00:16 2010
From: tbm at cyrius.com (Martin Michlmayr)
Date: Sun, 13 Jun 2010 20:00:16 +0100
Subject: [PATCH] Kirkwood: Add support for HP t5325 Thin Client
Message-ID: <20100613190016.GA7604@jirafa.cyrius.com>

Add support for the HP t5325 Thin Client.  This thin client is based
on a Marvell Kirkwood chip at 1.2 GHz and features 512 MB RAM, 512 MB
SATA-attached flash and an XGI Volari Z11 GPU.

Signed-off-by: Martin Michlmayr <tbm at cyrius.com>

---
This patch doesn't take Saeed's PCI changes into account; also, it
requires a mach-types update to build.

--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -99,6 +99,12 @@ config MACH_NET5BIG_V2
 	  Say 'Y' here if you want your kernel to support the
 	  LaCie 5Big Network v2 NAS.
 
+config MACH_T5325
+	bool "HP t5325 Thin Client"
+	help
+	  Say 'Y' here if you want your kernel to support the
+	  HP t5325 Thin Client.
+
 endmenu
 
 endif
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -14,5 +14,6 @@ obj-$(CONFIG_MACH_NETSPACE_V2)		+= netspace_v2-setup.o
 obj-$(CONFIG_MACH_INETSPACE_V2)		+= netspace_v2-setup.o
 obj-$(CONFIG_MACH_NET2BIG_V2)		+= netxbig_v2-setup.o
 obj-$(CONFIG_MACH_NET5BIG_V2)		+= netxbig_v2-setup.o
+obj-$(CONFIG_MACH_T5325)		+= t5325-setup.o
 
 obj-$(CONFIG_CPU_IDLE)			+= cpuidle.o
--- /dev/null	2010-05-25 13:42:08.579681378 +0000
+++ b/arch/arm/mach-kirkwood/t5325-setup.c	2010-05-24 14:48:44.000000000 +0000
@@ -0,0 +1,194 @@
+/*
+ *
+ * HP t5325 Thin Client setup
+ *
+ * Copyright (C) 2010  Martin Michlmayr <tbm at cyrius.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/flash.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/orion_spi.h>
+#include <linux/i2c.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+struct mtd_partition hp_t5325_partitions[] = {
+	{
+		.name		= "u-boot env",
+		.size		= SZ_64K,
+		.offset		= SZ_512K + SZ_256K,
+	},
+	{
+		.name		= "permanent u-boot env",
+		.size		= SZ_64K,
+		.offset		= MTDPART_OFS_APPEND,
+		.mask_flags	= MTD_WRITEABLE,
+	},
+	{
+		.name		= "HP env",
+		.size		= SZ_64K,
+		.offset		= MTDPART_OFS_APPEND,
+	},
+	{
+		.name		= "u-boot",
+		.size		= SZ_512K,
+		.offset		= 0,
+		.mask_flags	= MTD_WRITEABLE,
+	},
+	{
+		.name		= "SSD firmware",
+		.size		= SZ_256K,
+		.offset		= SZ_512K,
+	},
+};
+
+const struct flash_platform_data hp_t5325_flash = {
+	.type		= "mx25l8005",
+	.name		= "spi_flash",
+	.parts		= hp_t5325_partitions,
+	.nr_parts	= ARRAY_SIZE(hp_t5325_partitions),
+};
+
+struct spi_board_info __initdata hp_t5325_spi_slave_info[] = {
+	{
+		.modalias	= "m25p80",
+		.platform_data	= &hp_t5325_flash,
+		.irq		= -1,
+	},
+};
+
+static struct mv643xx_eth_platform_data hp_t5325_ge00_data = {
+	.phy_addr	= MV643XX_ETH_PHY_ADDR(8),
+};
+
+static struct mv_sata_platform_data hp_t5325_sata_data = {
+	.n_ports	= 2,
+};
+
+static struct gpio_keys_button hp_t5325_buttons[] = {
+	{
+		.code		= KEY_POWER,
+		.gpio		= 45,
+		.desc		= "Power",
+		.active_low	= 1,
+	},
+};
+
+static struct gpio_keys_platform_data hp_t5325_button_data = {
+	.buttons	= hp_t5325_buttons,
+	.nbuttons	= ARRAY_SIZE(hp_t5325_buttons),
+};
+
+static struct platform_device hp_t5325_button_device = {
+	.name		= "gpio-keys",
+	.id		= -1,
+	.num_resources	= 0,
+	.dev		= {
+		.platform_data	= &hp_t5325_button_data,
+	}
+};
+
+static unsigned int hp_t5325_mpp_config[] __initdata = {
+	MPP0_NF_IO2,
+	MPP1_SPI_MOSI,
+	MPP2_SPI_SCK,
+	MPP3_SPI_MISO,
+	MPP4_NF_IO6,
+	MPP5_NF_IO7,
+	MPP6_SYSRST_OUTn,
+	MPP7_SPI_SCn,
+	MPP8_TW_SDA,
+	MPP9_TW_SCK,
+	MPP10_UART0_TXD,
+	MPP11_UART0_RXD,
+	MPP12_SD_CLK,
+	MPP13_GPIO,
+	MPP14_GPIO,
+	MPP15_GPIO,
+	MPP16_GPIO,
+	MPP17_GPIO,
+	MPP18_NF_IO0,
+	MPP19_NF_IO1,
+	MPP20_GPIO,
+	MPP21_GPIO,
+	MPP22_GPIO,
+	MPP23_GPIO,
+	MPP32_GPIO,
+	MPP33_GE1_13,
+	MPP39_AUDIO_I2SBCLK,
+	MPP40_AUDIO_I2SDO,
+	MPP41_AUDIO_I2SLRC,
+	MPP42_AUDIO_I2SMCLK,
+	MPP45_GPIO,		/* Power button */
+	MPP48_GPIO,		/* Board power off */
+	0
+};
+
+#define HP_T5325_GPIO_POWER_OFF		48
+
+static void hp_t5325_power_off(void)
+{
+	gpio_set_value(HP_T5325_GPIO_POWER_OFF, 1);
+}
+
+static void __init hp_t5325_init(void)
+{
+	/*
+	 * Basic setup. Needs to be called early.
+	 */
+	kirkwood_init();
+	kirkwood_mpp_conf(hp_t5325_mpp_config);
+
+	kirkwood_uart0_init();
+	spi_register_board_info(hp_t5325_spi_slave_info,
+				ARRAY_SIZE(hp_t5325_spi_slave_info));
+	kirkwood_spi_init();
+	kirkwood_i2c_init();
+	kirkwood_ge00_init(&hp_t5325_ge00_data);
+	kirkwood_sata_init(&hp_t5325_sata_data);
+	kirkwood_ehci_init();
+	platform_device_register(&hp_t5325_button_device);
+
+	if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
+	    gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
+		pm_power_off = hp_t5325_power_off;
+	else
+		pr_err("t5325: failed to configure power-off GPIO\n");
+}
+
+static int __init hp_t5325_pci_init(void)
+{
+	if (machine_is_t5325())
+		kirkwood_pcie_init();
+
+	return 0;
+}
+subsys_initcall(hp_t5325_pci_init);
+
+MACHINE_START(T5325, "HP t5325 Thin Client")
+	/* Maintainer: Martin Michlmayr <tbm at cyrius.com> */
+	.phys_io	= KIRKWOOD_REGS_PHYS_BASE,
+	.io_pg_offst	= ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+	.boot_params	= 0x00000100,
+	.init_machine	= hp_t5325_init,
+	.map_io		= kirkwood_map_io,
+	.init_irq	= kirkwood_init_irq,
+	.timer		= &kirkwood_timer,
+MACHINE_END

-- 
Martin Michlmayr
http://www.cyrius.com/


From ben-linux at fluff.org  Sun Jun 13 18:23:49 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Sun, 13 Jun 2010 23:23:49 +0100
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <201006111557.12249.jeremy.kerr@canonical.com>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<1275636608.607067.417709988883.1.gpush@pororo>
	<20100611042046.GA31045@fluff.org.uk>
	<201006111557.12249.jeremy.kerr@canonical.com>
Message-ID: <20100613222349.GD31045@fluff.org.uk>

On Fri, Jun 11, 2010 at 03:57:10PM +0800, Jeremy Kerr wrote:
> Hi Ben,
> 
> > > Platforms can enable the generic struct clock through
> > > CONFIG_USE_COMMON_STRUCT_CLK. In this case, the clock infrastructure
> > > consists of a common struct clk:
> >
> > What do people think of just changing everyone who is currently using
> > clk support to using this new implementation?
> 
> I think it'd be too-big a task to take on for a single change; we'd be better 
> off allowing the two implementations concurrently. Also, I'd say that there 
> are many platforms that will never need the new code, so no need to change 
> them over.
~
Ok, agreed on that.
 
> > > struct clk {
> > > 
> > > 	const struct clk_ops	*ops;
> > > 	unsigned int		enable_count;
> > > 	struct mutex		mutex;
> > 
> > I'm a little worried about the size of struct clk if all of them
> > have a mutex in them. If i'm right, this is 40 bytes of data each
> > clock has to take on board.
> 
> Yeah, I see your concern about adding a mutex per clock, but I do think it's 
> the best solution. Of course, if there's a better way to do it, I'm happy to 
> try it out.

You also need a warning that even if it protects the clock, it may not
protect any access to the hardware implementing it.
 
> I believe we need to ensure that clocks are enabled when clk_enable returns, 
> so we'll need some mechanism for waiting on the thread doing the 
> enable/disable. Since (as you say) some clocks may take 100s of microseconds 
> to enable, we'll need a lock that we can hold while sleeping.

Well, mutexes give us that, whilst enabling we hold the mutex.
 
> We could use a global mutex for all clocks, but that would complicate the 
> interface by requiring non-locking versions of enable/disable, to allow 
> recursive enable/disable of parent clocks. Also, we'd lose any parallelism 
> possible in clock initialisation (we want boot to be fast, right?)

More to the point, we need it to _work_ fast. It isn't just boot time.
 
> Without all the debug stuff, it looks like a mutex is 12 bytes on UP, 20 on 
> SMP. That brings the maximum possible overhead to 26kB/43kB. More tolerable, 
> but not great.
>
> You know what would be awesome? if we could put platform-specific code in 
> their own sections and the discard the ones we know we won't need after boot. 
> But that's a discussion for another day...
> 
> > >        int             (*enable)(struct clk *);
> > 
> > still think that not passing an bool as a second argument is silly.
> 
> Still don't :D

Pfft.

> > > +struct clk {
> > > +	const struct clk_ops	*ops;
> > > +	unsigned int		enable_count;
> > > +	struct mutex		mutex;
> > > +};
> > 
> > how about defining a nice kerneldoc for this.
> 
> Shall do. I've also decided to un-inline the base API, which means that I can 
> use all of the existing prototypes in clk.h, which means the kerneldoc is 
> shared too.

Ok, I was going to suggest that anyway.

> 
> > > +#define INIT_CLK(name, o) \
> > > +	{ .ops = &o, .enable_count = 0, \
> > > +		.mutex = __MUTEX_INITIALIZER(name.mutex) }
> > 
> > how about doing the mutex initinitialisation at registration
> > time, will save a pile of non-zero code in the image to mess up
> > the compression.
> 
> I've just yesterday added the following to my tree, to allow dynamic 
> initialisation:
> 
> static inline void clk_init(struct clk *clk, const struct clk_ops *ops)
> {
> 	clk->ops = ops;
> 	clk->enable_count = 0;
> 	mutex_init(&clk->mutex);
> }
> 
> So we can do this either way.

the above is in my view better.
 
> > ~> +struct clk_ops {
> > 
> > > +       int             (*enable)(struct clk *);
> > > +       void            (*disable)(struct clk *);
> > > +       unsigned long   (*get_rate)(struct clk *);
> > > +       void            (*put)(struct clk *);
> > > +       long            (*round_rate)(struct clk *, unsigned long);
> > > +       int             (*set_rate)(struct clk *, unsigned long);
> > > +       int             (*set_parent)(struct clk *, struct clk *);
> > > +       struct clk*     (*get_parent)(struct clk *);
> > 
> > should each clock carry a parent field and the this is returned by
> > the get parent call.~~
> 
> I've been debating dropping the get_parent and set_parent ops entirely, 
> actually; setting a parent seems to be quite specific to hardware (you have to 
> know that a particular clock can be a parent of another clock), so it seems 
> like something that we shouldn't expose to drivers through this API. For the 
> code that knows the hardware, it can probably access the underlying clock 
> types directly.
>

Not really, and it is in use with extant drivers, so not easily
removable either.

> However, I see that something in the samsung code uses clk_get_parent for what 
> seems like a sane purpose, so have left them in for now. Or could this be done 
> differently?

nope, and I really like this method.
 
> > > +static inline int clk_enable(struct clk *clk)
> > > +{
> > > +	int ret = 0;
> > > +
> > > +	if (!clk->ops->enable)
> > > +		return 0;
> > > +
> > > +	mutex_lock(&clk->mutex);
> > > +	if (!clk->enable_count)
> > > +		ret = clk->ops->enable(clk);
> > > +
> > > +	if (!ret)
> > > +		clk->enable_count++;
> > > +	mutex_unlock(&clk->mutex);
> > > +
> > > +	return ret;
> > > +}
> > 
> > So we're leaving the enable parent code now to each implementation?
> > 
> > I think this is a really bad decision, it leaves so much open to bad
> > code repetition, as well as something the core should really be doing
> > if it had a parent clock field.
> 
> I'm tempted to go in either direction - either no [sg]et_parent in the clk 
> API, or add a parent to struct clk, but first I'd need to get up to speed on 
> the external uses of the clk's parent. Want to catch me on IRC to discuss?

Possibly, still screwed on timezone.
 
> > ~> +static inline void clk_disable(struct clk *clk)
> > 
> > > +{
> > > +	if (!clk->ops->enable)
> > > +		return;
> > 
> > so if we've no enable call we ignore disable too?
> 
> Typo; this should be "if (!clk->ops->disable)". Will fix for the next 
> revision.

yes, pointing that out.
 
> > also, we don't keep an enable count if this fields are in use,
> > could people rely on this being correct even if the clock has
> > no enable/disable fields.
> > 
> > Would much rather see the enable_count being kept up-to-date
> > no matter what, given it may be watched by other parts of the
> > implementation, useful for debug info, and possibly useful if
> > later in the start sequence the clk_ops get changed to have this
> > field.~
> 
> Checking for the ops first allows us to skip the mutex acquire, but I'm happy 
> either way.

erm, sorry, yes, you can check for them before mutex. any chages
should be done with mutex held.
 
> > > +~	mutex_lock(&clk->mutex);
> > > +
> > > +	if (!--clk->enable_count)
> > > +		clk->ops->disable(clk);
> > > +
> > > +	mutex_unlock(&clk->mutex);
> > > +}
> > > +
> > > +static inline unsigned long clk_get_rate(struct clk *clk)
> > > +{
> > > +	if (clk->ops->get_rate)
> > > +		return clk->ops->get_rate(clk);
> > > +	return 0;
> > > +}
> > > +
> > > +static inline void clk_put(struct clk *clk)
> > > +{
> > > +	if (clk->ops->put)
> > > +		clk->ops->put(clk);
> > > +}
> > 
> > I'm beginging to wonder if we don't just have a set of default ops
> > that get set into the clk+ops at registration time if these do
> > not have an implementation.
> 
> Using default ops would mean a couple of things:
> 
> 1) we can no longer mark the real ops as const; and
> 2) we can no longer avoid the hard-to-predict indirect branch

ok, how about people have to mark these as a default non op in their
clock structure, and then error if they try and register a clock with
null ops. anyone changing these to NULL later deserves all the pain and agony
they get.
 
> > this means that either any driver that is using a multi-parent clock
> > has to deal with the proper enable/disable of the parents (this is
> > is going to lead to code repetition, and I bet people will get it
> > badly wrong).
> > 
> > I belive the core of the clock code should deal with this, since
> > otherwise we end up with the situation of the same code being
> > repeated throughout the kernel.
> 
> I see the concern here, but I'll defer this one until we've decided on whether 
> or not the parents should be exposed through the API.

Ok, let's find out what other people think too. I'm not the only user.

BTW, we do need to do some cleanups to the samsung code, we've a few
places where we explicitly name clocks. Discussion for seperate
thread.

-- 
Ben (ben at fluff.org, http://www.fluff.org/)

  'a smiley only costs 4 bytes'


From ben-linux at fluff.org  Sun Jun 13 18:25:12 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Sun, 13 Jun 2010 23:25:12 +0100
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19473.61547.684572.647641@ipc1.ka-ro>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<1275636608.607067.417709988883.1.gpush@pororo>
	<20100611042046.GA31045@fluff.org.uk>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
Message-ID: <20100613222512.GE31045@fluff.org.uk>

On Fri, Jun 11, 2010 at 10:14:35AM +0200, Lothar Wa?mann wrote:
> Hi,
> 
> > > > +static inline int clk_enable(struct clk *clk)
> > > > +{
> > > > +	int ret = 0;
> > > > +
> > > > +	if (!clk->ops->enable)
> > > > +		return 0;
> > > > +
> > > > +	mutex_lock(&clk->mutex);
> > > > +	if (!clk->enable_count)
> > > > +		ret = clk->ops->enable(clk);
> > > > +
> > > > +	if (!ret)
> > > > +		clk->enable_count++;
> > > > +	mutex_unlock(&clk->mutex);
> > > > +
> > > > +	return ret;
> > > > +}
> > > 
> Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> makes it impossible to call those functions in interrupt context.

I think that is a bad idea, unless you can provide otherwise. These
calls can sleep depending on implementation, and thus I would like to
ensure that they are marked as might-sleep.

Is there any specific reason? If so, we need to add some form of ops
where we have _nosleep specificially for this case.

-- 
Ben (ben at fluff.org, http://www.fluff.org/)

  'a smiley only costs 4 bytes'


From ben-linux at fluff.org  Sun Jun 13 18:27:15 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Sun, 13 Jun 2010 23:27:15 +0100
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19474.2817.333749.485028@ipc1.ka-ro>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
Message-ID: <20100613222715.GF31045@fluff.org.uk>

On Fri, Jun 11, 2010 at 12:08:01PM +0200, Lothar Wa?mann wrote:
> Hi,
> 
> > > > > Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> > > > > makes it impossible to call those functions in interrupt context.
> > IMHO if a device generates an irq its clock should already be on.  This
> > way you don't need to enable or disable a clock in irq context.
> >  
> You may want to disable a clock in the IRQ handler. The VPU driver in
> the Freescale BSP for i.MX51 does exactly this.
> Anyway I don't see any reason for using a mutex here instead of
> spin_lock_irq_save() as all other implementations do.

Hmm, then again the VPU driver may just be a bit wrong here.

We could protect each clock with a spinlock, but that would end up
with a problem of spinning where we have clocks that takes 100s of
usec or so to init. See all PLLs on S3C devices, where it can take
100-300uS to get a stable clock out of the device.

-- 
Ben (ben at fluff.org, http://www.fluff.org/)

  'a smiley only costs 4 bytes'


From ryan at bluewatersys.com  Sun Jun 13 18:46:21 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Mon, 14 Jun 2010 10:46:21 +1200
Subject: [PATCH] ep93xx: clear devcfg bits before setting them
In-Reply-To: <0D753D10438DA54287A00B027084269763711321BA@AUSP01VMBX24.collaborationhost.net>
References: <0D753D10438DA54287A00B027084269763711321BA@AUSP01VMBX24.collaborationhost.net>
Message-ID: <4C155FBD.4020106@bluewatersys.com>

H Hartley Sweeten wrote:
> The ep93xx core helper function ep93xx_devcfg_set_clear should mask the
> clear_bits before setting the new set_bits in case the clear_bits are a
> mask value that also includes the set_bits.
> 
> Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: Ryan Mallon <ryan at bluewatersys.com>

Acked-by: Ryan Mallon <ryan at bluewatersys.com>

> ---
> 
> diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
> index 9092677..92f2ebb 100644
> --- a/arch/arm/mach-ep93xx/core.c
> +++ b/arch/arm/mach-ep93xx/core.c
> @@ -215,8 +215,8 @@ void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
>  	spin_lock_irqsave(&syscon_swlock, flags);
>  
>  	val = __raw_readl(EP93XX_SYSCON_DEVCFG);
> -	val |= set_bits;
>  	val &= ~clear_bits;
> +	val |= set_bits;
>  	__raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
>  	__raw_writel(val, EP93XX_SYSCON_DEVCFG);
>  


-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From ryan at bluewatersys.com  Sun Jun 13 18:51:06 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Mon, 14 Jun 2010 10:51:06 +1200
Subject: [PATCH 0/5] SPEAr3xx: Unify build of SPEAr3xx platforms
In-Reply-To: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <4C1560DA.5040803@bluewatersys.com>

Ryan Mallon wrote:
> Rework the SPEAr3xx code to allow all three SPEAr3xx platforms to be
> built into a single kernel.
> 
> I do not have access to any SPEAr3xx hardware, so the patch series is
> build tested only.

Any interest in this patch series, or anybody with hardware that is able
to test it?

Patch 1/5 is a simple cleanup patch which makes a bunch of local
structures static, so it doesn't change functionality. Patch 5/5 can be
dropped until the path forward for cleaning up the defconfigs has been
decided. The other patches should not change the functionality if only
one of the platforms is compiled in, but should also allow all three
SPEAr3xx platforms to be built and run in a single kernel.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From eric.y.miao at gmail.com  Sun Jun 13 23:09:49 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 14 Jun 2010 11:09:49 +0800
Subject: [GIT PULL] pxa: fixes for v2.6.35-rc3
Message-ID: <AANLkTikVogt4MaYbOxOIr1DXjX29pYWYw5pbmCkC36Lv@mail.gmail.com>

The following changes since commit 7e27d6e778cd87b6f2415515d7127eba53fe5d02:

  Linux 2.6.35-rc3 (2010-06-11 19:14:04 -0700)

are available in the git repository at:
  git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git fix

Jonathan Cameron (1):
      [ARM] mmp: fix build failure due to IRQ_PMU depends on ARCH_PXA

Marek Vasut (2):
      [ARM] pxa/z2: fix missing include in battery driver
      [ARM] pxa/z2: fix flash layout to final version

Robert Jarzmik (1):
      [ARM] pxa/mioa701: fix camera regression

Steve Bennett (1):
      [ARM] pxa: fix incorrect gpio type in udc_pxa2xx.h


From jeremy.kerr at canonical.com  Sun Jun 13 23:10:25 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Mon, 14 Jun 2010 11:10:25 +0800
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100613222349.GD31045@fluff.org.uk>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<20100613222349.GD31045@fluff.org.uk>
Message-ID: <201006141110.26440.jeremy.kerr@canonical.com>

Hi Ben,

> You also need a warning that even if it protects the clock, it may not
> protect any access to the hardware implementing it.

Yep, agreed. HW clock implementations are free to acquire the mutex in their 
ops.

> > I believe we need to ensure that clocks are enabled when clk_enable
> > returns, so we'll need some mechanism for waiting on the thread doing
> > the enable/disable. Since (as you say) some clocks may take 100s of
> > microseconds to enable, we'll need a lock that we can hold while
> > sleeping.
> 
> Well, mutexes give us that, whilst enabling we hold the mutex.

Exactly, that's why I think the mutex option is the best way to go.

> > I've just yesterday added the following to my tree, to allow dynamic
> > initialisation:
> > 
> > static inline void clk_init(struct clk *clk, const struct clk_ops *ops)
> > {
> > 
> > 	clk->ops = ops;
> > 	clk->enable_count = 0;
> > 	mutex_init(&clk->mutex);
> > 
> > }
> > 
> > So we can do this either way.
> 
> the above is in my view better.

By 'the above' do you mean doing the mutex init at registration time, or the 
clk_init code above?

Either way should be fine; delaying the mutex_init until registration will has 
the nice property of not requiring the clock name to be passed to INIT_CLK.

> > I've been debating dropping the get_parent and set_parent ops entirely,
> > actually; setting a parent seems to be quite specific to hardware (you
> > have to know that a particular clock can be a parent of another clock),
> > so it seems like something that we shouldn't expose to drivers through
> > this API. For the code that knows the hardware, it can probably access
> > the underlying clock types directly.
> 
> Not really, and it is in use with extant drivers, so not easily
> removable either.

OK, is set_parent used much? I can see the use of get_parent, but calls 
set_parent need to know specifics of the clock hardware.

> > Checking for the ops first allows us to skip the mutex acquire, but I'm
> > happy either way.
> 
> erm, sorry, yes, you can check for them before mutex. any chages
> should be done with mutex held.

Yep.

> > Using default ops would mean a couple of things:
> > 
> > 1) we can no longer mark the real ops as const; and
> > 2) we can no longer avoid the hard-to-predict indirect branch
> 
> ok, how about people have to mark these as a default non op in their
> clock structure, and then error if they try and register a clock with
> null ops. anyone changing these to NULL later deserves all the pain and
> agony they get.

That addresses the first point, but still means we have an unnecessary 
indirect branch to a function that does nothing. Since I've unlined the code 
where this happens, the checks for null ops are pretty unobtrusive. If we 
require all ops to be not-null, then we'll need much larger chunks of code 
where the ops are defined. I like that you can just set the ops callbacks that 
you need, and the rest "just works".

Cheers,


Jeremy


From grant.likely at secretlab.ca  Mon Jun 14 01:02:15 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sun, 13 Jun 2010 23:02:15 -0600
Subject: Request review of device tree documentation
In-Reply-To: <4C146F18.9030008@firmworks.com>
References: <AANLkTilK4YkRMJqlcRDOAlGBzpdlZuSo9NF5NrRNocHT@mail.gmail.com> 
	<33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com>
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com> 
	<4C13430B.5000907@firmworks.com> <1276339529.1962.184.camel@pasglop> 
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com> 
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com> 
	<4C146F18.9030008@firmworks.com>
Message-ID: <AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>

[cc'ing linux-arm-kernel because we're discussing ARM issues]

On Sat, Jun 12, 2010 at 11:39 PM, Mitch Bradley <wmb at firmworks.com> wrote:
> Grant Likely wrote:
>>
>> On Sat, Jun 12, 2010 at 4:52 PM, Benjamin Herrenschmidt
>> <benh at kernel.crashing.org> wrote:
>>
>>>
>>> On Sat, 2010-06-12 at 06:30 -1000, Mitch Bradley wrote:
>>>
>>>
>>>>
>>>> I'm certainly going to try keeping OFW alive. ?On the x86 OLPC machines,
>>>> the ability to
>>>> dive into OFW via a SysRq key combo was very helpful for debugging some
>>>> difficult
>>>> problems. ?The team has asked me to support the feature on ARM.
>>>>
>>>
>>> Oh well, if you can and can convince the ARM kernel folks to do the
>>> necessary changes ... :-)
>>>
>>
>> What is needed to keep OFW alive? ?I've got no problem with doing so
>> if it isn't invasive, and as long as the same boot entry interface can
>> be used.
>>
>
> Minimally, OFW needs to own some memory that the kernel won't steal. ?OFW on
> ARM
> is position-independent, so it can be tucked up at the top of memory fairly
> easily.
>
> To call back into OFW, the virtual mapping for that memory needs to be
> reestablished.
> Or perhaps the MMU and caches can be turned off for the duration of the
> callback.
> I don't have the details of ARM MMUs and caches reloaded into my head yet.
> ?Maybe next week...

Remapping the MMU could be hairy, but I see no issue with marking
OFW's memory as reserved.  How does OFW currently tell the OS what
memory it should not touch because OFW is using it?  Is it device tree
data or another mechanism?

> Also, for debugging, OFW typically needs access to a UART. ?If the OS is
> using the UART,
> it's often possible for OFW to use it just by turning off interrupts and
> polling the UART.

This doesn't sound onerous.

>> What is the use-case for having a dynamic device tree?
>
> The use case for a dynamic device tree is not compelling.
>
> In SPARC / Solaris land, Open Boot managed the non-volatile configuration
> variables, which the OS could access and modify dynamically as properties in
> /options. ?The OS didn't have to know the storage layout nor the hardware
> details of the storage device. ?Convenient, but not hugely important.

I think the assumption can be made that this will not be a use case on ARM.

>> ?I can see
>> keeping OFW alive being useful for some debug facilities, but once the
>> kernel has started, I'm really not interested in relying on firmware
>> to manage the hardware.
>
> That's sort of a self-fulfilling prophecy. ?If the OS doesn't trust the
> firmware, there is no pressure for the firmware to "get it right".

Firmware will not get it right.  Period.  There will always be
something wrong.  It is never right on PCs.  It will never be right on
the other architectures.  That goes for OSes too, but upgrading an OS
isn't as risky as upgrading firmware.  That isn't to say that it can't
be close, but every firmware feature that the OS depends on is a
feature that could force a risky firmware upgrade when the bug in it
is discovered.

I'm also convinced that the economics are all wrong for "getting it
right" when talking about firmware.  Manufactures don't care about
firmware; they care about selling boxes.  Customers don't care about
firmware, they care about the operating system (well, that's not true
either, they care about applications).  For manufactures, once it can
boot the real operating system, there is little to no incentive to
spend any more money on firmware when the money can be better spent on
either the next product or the adding features to the operating system
of the existing product.  In fact, spending money on firmware is
actually *more risky* one a product ships, because if a firmware
upgrade goes bad, then that means product returned for repair at the
factory.

For me, this leads to two conclusions;
- That the OS should have little to no dependencies on the firmware
after it is booted so that bug fixes remain entirely in the realm of
the operating system.
- That the description of the hardware (ie Device Tree or ACPI) should
be decoupled enough from firmware that bugs in the data do not force a
firmware upgrade.  The data must always be updatabie.  Even if
configuration or data is completely corrupt, it must still be simple
to recover.

Note: I'm not critiquing OFW on either of these points.  These are
just some of my base requirements when I approach system design.

> In PC land, the current status quo is that Windows depends on ACPI so
> heavily that BIOS vendors pretty much have to get that part of the puzzle
> right. ?Microsoft did a thorough job of creating certification tests and
> enforcing their use. ?I'm not praising ACPI, just pointing out the dynamics
> that result from assignment of responsibility.

Yet how many boards are shipped with broken ACPI tables?  Just
bringing up ACPI in the presence of a kernel developer seems to bring
about the onset of Tourette's.  Bios provides enough data to be able
to boot the operating system, but in my experience it still requires
extra drivers to be added after installation for everything to work
right.

OTOH, I'm not had to deal with ACPI personally, so I may also be
talking out of my backside on this point.  :-)

> That said, I'm not interested in pushing the issue. ?It's okay with me if
> the device tree is static as far as the kernel is concerned, and callbacks
> to OFW are only used for debugging purposes.

The current intent is to only accept the flat tree representation when
booting the kernel.  So we'll need to encode the callback pointer into
the tree somewhere.

Cheers,
g.


From grant.likely at secretlab.ca  Mon Jun 14 01:13:50 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sun, 13 Jun 2010 23:13:50 -0600
Subject: Request review of device tree documentation
In-Reply-To: <1276408087.1962.552.camel@pasglop>
References: <AANLkTilK4YkRMJqlcRDOAlGBzpdlZuSo9NF5NrRNocHT@mail.gmail.com> 
	<33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com>
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com> 
	<4C13430B.5000907@firmworks.com> <1276339529.1962.184.camel@pasglop> 
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com> 
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com> 
	<1276408087.1962.552.camel@pasglop>
Message-ID: <AANLkTikBjwuVvij8I91XaQgLfn8r_lZDrAsIBfJrHDBF@mail.gmail.com>

On Sat, Jun 12, 2010 at 11:48 PM, Benjamin Herrenschmidt
<benh at kernel.crashing.org> wrote:
> On Sat, 2010-06-12 at 23:07 -0600, Grant Likely wrote:
>>
>> What is needed to keep OFW alive? ?I've got no problem with doing so
>> if it isn't invasive, and as long as the same boot entry interface can
>> be used.
>
> Well, no. OF has a well defined "client interface" which is what gets us
> in prom_init.c on powerpc when r5 is non NULL. You can use it to do
> things like access devices or the device-tree.
>
> We use that to suck the device-tree, which we flatten, and then re-enter
> the kernel with the "common" entry interface.

I don't think I want to do the same on ARM.  I'd rather have the
prom_init stuff in a boot wrapper, or have OFW itself generate the
flat representation before booting the kernel.  I'm trying to
constrain the number of things that could go wrong by defining only
one way for getting the device tree data into the kernel.

> If you want to keep OF alive, you -can- probably do that too, but it's
> more tricky. You need to keep the memory where OF resides reserved, OF
> might need special MMU translations, you maybe need to install hooks in
> OF itself for it to be able to manipulate some of those, etc...
>
>> What is the use-case for having a dynamic device tree? ?I can see
>> keeping OFW alive being useful for some debug facilities, but once the
>> kernel has started, I'm really not interested in relying on firmware
>> to manage the hardware. ?(but then again it's no secret that I'm
>> suspicious of anything that depends on runtime interaction with
>> firmware).
>
> As we all are :-)

:-)

> I see one genuine use of dynamic device-tree though, which is in a
> virtualized environment (where the host can be Linux itself). Hotplug
> can then be a matter of getting new nodes & properties fed down to the
> OS by the hypervisor/firmware.
>
> pSeries somewhat works like that, but using weirdo rtas calls. We could
> do something saner for kvm or whatever other hypervisors we have some
> amount of control onto, where bits of compiled dtb can be handed down
> representing a sub-hierarchy of the tree.

Right.  We don't need to use OFW/RTAS to handle this use case.

g.


From viresh.kumar at st.com  Mon Jun 14 01:16:18 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Mon, 14 Jun 2010 10:46:18 +0530
Subject: [PATCH 1/5] SPEAr3xx: Make local structres static
In-Reply-To: <1275717955-14545-2-git-send-email-ryan@bluewatersys.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
	<1275717955-14545-2-git-send-email-ryan@bluewatersys.com>
Message-ID: <4C15BB22.9010309@st.com>

On 6/5/2010 11:35 AM, Ryan Mallon wrote:
> Several structures in arch/arm/mach-spear3xx are not marked static
> like they should be. Fix this.
> 
> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
> ---
>  arch/arm/mach-spear3xx/spear300.c |   33 ++++++++++----------
>  arch/arm/mach-spear3xx/spear310.c |   16 +++++-----
>  arch/arm/mach-spear3xx/spear320.c |   56 +++++++++++++++++-----------------
>  arch/arm/mach-spear3xx/spear3xx.c |   60 ++++++++++++++++++------------------
>  4 files changed, 83 insertions(+), 82 deletions(-)
> 
> diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
> index 3560f8c..b71f996 100644
> --- a/arch/arm/mach-spear3xx/spear300.c
> +++ b/arch/arm/mach-spear3xx/spear300.c
> @@ -119,7 +119,7 @@ struct pmx_mode caml_lcd_mode = {
>  };
>  
>  /* devices */
> -struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
> +static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
>  	{
>  		.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
>  			ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
> @@ -134,7 +134,7 @@ struct pmx_dev pmx_fsmc_2_chips = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
> +static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
>  	{
>  		.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
>  			ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
> @@ -149,7 +149,7 @@ struct pmx_dev pmx_fsmc_4_chips = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_keyboard_modes[] = {
> +static struct pmx_dev_mode pmx_keyboard_modes[] = {
>  	{
>  		.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
>  			LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
> @@ -166,7 +166,7 @@ struct pmx_dev pmx_keyboard = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_clcd_modes[] = {
> +static struct pmx_dev_mode pmx_clcd_modes[] = {
>  	{
>  		.ids = PHOTO_FRAME_MODE,
>  		.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
> @@ -184,7 +184,7 @@ struct pmx_dev pmx_clcd = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
> +static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
>  	{
>  		.ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
>  		.mask = PMX_MII_MASK,
> @@ -211,7 +211,7 @@ struct pmx_dev pmx_telecom_gpio = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
> +static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
>  	{
>  		.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
>  			HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
> @@ -229,7 +229,7 @@ struct pmx_dev pmx_telecom_tdm = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
> +static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
>  	{
>  		.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
>  			LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
> @@ -246,7 +246,7 @@ struct pmx_dev pmx_telecom_spi_cs_i2c_clk = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_telecom_camera_modes[] = {
> +static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
>  	{
>  		.ids = CAML_LCDW_MODE | CAML_LCD_MODE,
>  		.mask = PMX_MII_MASK,
> @@ -263,7 +263,7 @@ struct pmx_dev pmx_telecom_camera = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_telecom_dac_modes[] = {
> +static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
>  	{
>  		.ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
>  			| CAMU_WLCD_MODE | CAML_LCD_MODE,
> @@ -278,7 +278,7 @@ struct pmx_dev pmx_telecom_dac = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
> +static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
>  	{
>  		.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
>  			| LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
> @@ -295,7 +295,7 @@ struct pmx_dev pmx_telecom_i2s = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
> +static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
>  	{
>  		.ids = NAND_MODE | NOR_MODE,
>  		.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
> @@ -310,7 +310,7 @@ struct pmx_dev pmx_telecom_boot_pins = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
> +static struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
>  	{
>  		.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
>  			HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
> @@ -330,7 +330,7 @@ struct pmx_dev pmx_telecom_sdio_4bit = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
> +static struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
>  	{
>  		.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
>  			HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
> @@ -349,7 +349,7 @@ struct pmx_dev pmx_telecom_sdio_8bit = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_gpio1_modes[] = {
> +static struct pmx_dev_mode pmx_gpio1_modes[] = {
>  	{
>  		.ids = PHOTO_FRAME_MODE,
>  		.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
> @@ -391,7 +391,7 @@ struct amba_device gpio1_device = {
>  };
>  
>  /* spear3xx shared irq */
> -struct shirq_dev_config shirq_ras1_config[] = {
> +static struct shirq_dev_config shirq_ras1_config[] = {
>  	{
>  		.virq = VIRQ_IT_PERS_S,
>  		.enb_mask = IT_PERS_S_IRQ_MASK,
> @@ -431,7 +431,8 @@ struct shirq_dev_config shirq_ras1_config[] = {
>  	},
>  };
>  
> -struct spear_shirq shirq_ras1 = {
> +
> +static struct spear_shirq shirq_ras1 = {
>  	.irq = IRQ_GEN_RAS_1,
>  	.dev_config = shirq_ras1_config,
>  	.dev_count = ARRAY_SIZE(shirq_ras1_config),
> diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
> index 96a1ab8..14698b8 100644
> --- a/arch/arm/mach-spear3xx/spear310.c
> +++ b/arch/arm/mach-spear3xx/spear310.c
> @@ -142,7 +142,7 @@ struct pmx_driver pmx_driver = {
>  /* Add spear310 specific devices here */
>  
>  /* spear3xx shared irq */
> -struct shirq_dev_config shirq_ras1_config[] = {
> +static struct shirq_dev_config shirq_ras1_config[] = {
>  	{
>  		.virq = VIRQ_SMII0,
>  		.status_mask = SMII0_IRQ_MASK,
> @@ -170,7 +170,7 @@ struct shirq_dev_config shirq_ras1_config[] = {
>  	},
>  };
>  
> -struct spear_shirq shirq_ras1 = {
> +static struct spear_shirq shirq_ras1 = {
>  	.irq = IRQ_GEN_RAS_1,
>  	.dev_config = shirq_ras1_config,
>  	.dev_count = ARRAY_SIZE(shirq_ras1_config),
> @@ -182,7 +182,7 @@ struct spear_shirq shirq_ras1 = {
>  	},
>  };
>  
> -struct shirq_dev_config shirq_ras2_config[] = {
> +static struct shirq_dev_config shirq_ras2_config[] = {
>  	{
>  		.virq = VIRQ_UART1,
>  		.status_mask = UART1_IRQ_MASK,
> @@ -201,7 +201,7 @@ struct shirq_dev_config shirq_ras2_config[] = {
>  	},
>  };
>  
> -struct spear_shirq shirq_ras2 = {
> +static struct spear_shirq shirq_ras2 = {
>  	.irq = IRQ_GEN_RAS_2,
>  	.dev_config = shirq_ras2_config,
>  	.dev_count = ARRAY_SIZE(shirq_ras2_config),
> @@ -213,14 +213,14 @@ struct spear_shirq shirq_ras2 = {
>  	},
>  };
>  
> -struct shirq_dev_config shirq_ras3_config[] = {
> +static struct shirq_dev_config shirq_ras3_config[] = {
>  	{
>  		.virq = VIRQ_EMI,
>  		.status_mask = EMI_IRQ_MASK,
>  	},
>  };
>  
> -struct spear_shirq shirq_ras3 = {
> +static struct spear_shirq shirq_ras3 = {
>  	.irq = IRQ_GEN_RAS_3,
>  	.dev_config = shirq_ras3_config,
>  	.dev_count = ARRAY_SIZE(shirq_ras3_config),
> @@ -232,7 +232,7 @@ struct spear_shirq shirq_ras3 = {
>  	},
>  };
>  
> -struct shirq_dev_config shirq_intrcomm_ras_config[] = {
> +static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
>  	{
>  		.virq = VIRQ_TDM_HDLC,
>  		.status_mask = TDM_HDLC_IRQ_MASK,
> @@ -245,7 +245,7 @@ struct shirq_dev_config shirq_intrcomm_ras_config[] = {
>  	},
>  };
>  
> -struct spear_shirq shirq_intrcomm_ras = {
> +static struct spear_shirq shirq_intrcomm_ras = {
>  	.irq = IRQ_INTRCOMM_RAS_ARM,
>  	.dev_config = shirq_intrcomm_ras_config,
>  	.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
> diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
> index 6a12195..958e52d 100644
> --- a/arch/arm/mach-spear3xx/spear320.c
> +++ b/arch/arm/mach-spear3xx/spear320.c
> @@ -54,7 +54,7 @@ struct pmx_mode small_printers_mode = {
>  };
>  
>  /* devices */
> -struct pmx_dev_mode pmx_clcd_modes[] = {
> +static struct pmx_dev_mode pmx_clcd_modes[] = {
>  	{
>  		.ids = AUTO_NET_SMII_MODE,
>  		.mask = 0x0,
> @@ -68,7 +68,7 @@ struct pmx_dev pmx_clcd = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_emi_modes[] = {
> +static struct pmx_dev_mode pmx_emi_modes[] = {
>  	{
>  		.ids = AUTO_EXP_MODE,
>  		.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
> @@ -82,7 +82,7 @@ struct pmx_dev pmx_emi = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_fsmc_modes[] = {
> +static struct pmx_dev_mode pmx_fsmc_modes[] = {
>  	{
>  		.ids = ALL_MODES,
>  		.mask = 0x0,
> @@ -96,7 +96,7 @@ struct pmx_dev pmx_fsmc = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_spp_modes[] = {
> +static struct pmx_dev_mode pmx_spp_modes[] = {
>  	{
>  		.ids = SMALL_PRINTERS_MODE,
>  		.mask = 0x0,
> @@ -110,7 +110,7 @@ struct pmx_dev pmx_spp = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_sdio_modes[] = {
> +static struct pmx_dev_mode pmx_sdio_modes[] = {
>  	{
>  		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
>  			SMALL_PRINTERS_MODE,
> @@ -125,7 +125,7 @@ struct pmx_dev pmx_sdio = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_i2s_modes[] = {
> +static struct pmx_dev_mode pmx_i2s_modes[] = {
>  	{
>  		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
>  		.mask = PMX_UART0_MODEM_MASK,
> @@ -139,7 +139,7 @@ struct pmx_dev pmx_i2s = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_uart1_modes[] = {
> +static struct pmx_dev_mode pmx_uart1_modes[] = {
>  	{
>  		.ids = ALL_MODES,
>  		.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
> @@ -153,7 +153,7 @@ struct pmx_dev pmx_uart1 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_uart1_modem_modes[] = {
> +static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
>  	{
>  		.ids = AUTO_EXP_MODE,
>  		.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
> @@ -172,7 +172,7 @@ struct pmx_dev pmx_uart1_modem = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_uart2_modes[] = {
> +static struct pmx_dev_mode pmx_uart2_modes[] = {
>  	{
>  		.ids = ALL_MODES,
>  		.mask = PMX_FIRDA_MASK,
> @@ -186,7 +186,7 @@ struct pmx_dev pmx_uart2 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_touchscreen_modes[] = {
> +static struct pmx_dev_mode pmx_touchscreen_modes[] = {
>  	{
>  		.ids = AUTO_NET_SMII_MODE,
>  		.mask = PMX_SSP_CS_MASK,
> @@ -200,7 +200,7 @@ struct pmx_dev pmx_touchscreen = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_can_modes[] = {
> +static struct pmx_dev_mode pmx_can_modes[] = {
>  	{
>  		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
>  		.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
> @@ -215,7 +215,7 @@ struct pmx_dev pmx_can = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_sdio_led_modes[] = {
> +static struct pmx_dev_mode pmx_sdio_led_modes[] = {
>  	{
>  		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
>  		.mask = PMX_SSP_CS_MASK,
> @@ -229,7 +229,7 @@ struct pmx_dev pmx_sdio_led = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_pwm0_modes[] = {
> +static struct pmx_dev_mode pmx_pwm0_modes[] = {
>  	{
>  		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
>  		.mask = PMX_UART0_MODEM_MASK,
> @@ -246,7 +246,7 @@ struct pmx_dev pmx_pwm0 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_pwm1_modes[] = {
> +static struct pmx_dev_mode pmx_pwm1_modes[] = {
>  	{
>  		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
>  		.mask = PMX_UART0_MODEM_MASK,
> @@ -263,7 +263,7 @@ struct pmx_dev pmx_pwm1 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_pwm2_modes[] = {
> +static struct pmx_dev_mode pmx_pwm2_modes[] = {
>  	{
>  		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
>  		.mask = PMX_SSP_CS_MASK,
> @@ -280,7 +280,7 @@ struct pmx_dev pmx_pwm2 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_pwm3_modes[] = {
> +static struct pmx_dev_mode pmx_pwm3_modes[] = {
>  	{
>  		.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
>  		.mask = PMX_MII_MASK,
> @@ -294,7 +294,7 @@ struct pmx_dev pmx_pwm3 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_ssp1_modes[] = {
> +static struct pmx_dev_mode pmx_ssp1_modes[] = {
>  	{
>  		.ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
>  		.mask = PMX_MII_MASK,
> @@ -308,7 +308,7 @@ struct pmx_dev pmx_ssp1 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_ssp2_modes[] = {
> +static struct pmx_dev_mode pmx_ssp2_modes[] = {
>  	{
>  		.ids = AUTO_NET_SMII_MODE,
>  		.mask = PMX_MII_MASK,
> @@ -322,7 +322,7 @@ struct pmx_dev pmx_ssp2 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_mii1_modes[] = {
> +static struct pmx_dev_mode pmx_mii1_modes[] = {
>  	{
>  		.ids = AUTO_NET_MII_MODE,
>  		.mask = 0x0,
> @@ -336,7 +336,7 @@ struct pmx_dev pmx_mii1 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_smii0_modes[] = {
> +static struct pmx_dev_mode pmx_smii0_modes[] = {
>  	{
>  		.ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
>  		.mask = PMX_MII_MASK,
> @@ -350,7 +350,7 @@ struct pmx_dev pmx_smii0 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_smii1_modes[] = {
> +static struct pmx_dev_mode pmx_smii1_modes[] = {
>  	{
>  		.ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
>  		.mask = PMX_MII_MASK,
> @@ -364,7 +364,7 @@ struct pmx_dev pmx_smii1 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_i2c1_modes[] = {
> +static struct pmx_dev_mode pmx_i2c1_modes[] = {
>  	{
>  		.ids = AUTO_EXP_MODE,
>  		.mask = 0x0,
> @@ -387,7 +387,7 @@ struct pmx_driver pmx_driver = {
>  /* Add spear320 specific devices here */
>  
>  /* spear3xx shared irq */
> -struct shirq_dev_config shirq_ras1_config[] = {
> +static struct shirq_dev_config shirq_ras1_config[] = {
>  	{
>  		.virq = VIRQ_EMI,
>  		.status_mask = EMI_IRQ_MASK,
> @@ -403,7 +403,7 @@ struct shirq_dev_config shirq_ras1_config[] = {
>  	},
>  };
>  
> -struct spear_shirq shirq_ras1 = {
> +static struct spear_shirq shirq_ras1 = {
>  	.irq = IRQ_GEN_RAS_1,
>  	.dev_config = shirq_ras1_config,
>  	.dev_count = ARRAY_SIZE(shirq_ras1_config),
> @@ -416,7 +416,7 @@ struct spear_shirq shirq_ras1 = {
>  	},
>  };
>  
> -struct shirq_dev_config shirq_ras3_config[] = {
> +static struct shirq_dev_config shirq_ras3_config[] = {
>  	{
>  		.virq = VIRQ_PLGPIO,
>  		.enb_mask = GPIO_IRQ_MASK,
> @@ -435,7 +435,7 @@ struct shirq_dev_config shirq_ras3_config[] = {
>  	},
>  };
>  
> -struct spear_shirq shirq_ras3 = {
> +static struct spear_shirq shirq_ras3 = {
>  	.irq = IRQ_GEN_RAS_3,
>  	.dev_config = shirq_ras3_config,
>  	.dev_count = ARRAY_SIZE(shirq_ras3_config),
> @@ -449,7 +449,7 @@ struct spear_shirq shirq_ras3 = {
>  	},
>  };
>  
> -struct shirq_dev_config shirq_intrcomm_ras_config[] = {
> +static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
>  	{
>  		.virq = VIRQ_CANU,
>  		.status_mask = CAN_U_IRQ_MASK,
> @@ -497,7 +497,7 @@ struct shirq_dev_config shirq_intrcomm_ras_config[] = {
>  	},
>  };
>  
> -struct spear_shirq shirq_intrcomm_ras = {
> +static struct spear_shirq shirq_intrcomm_ras = {
>  	.irq = IRQ_INTRCOMM_RAS_ARM,
>  	.dev_config = shirq_intrcomm_ras_config,
>  	.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
> diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
> index e87313a..5f2cddc 100644
> --- a/arch/arm/mach-spear3xx/spear3xx.c
> +++ b/arch/arm/mach-spear3xx/spear3xx.c
> @@ -102,7 +102,7 @@ void __init spear3xx_map_io(void)
>  
>  /* pad multiplexing support */
>  /* devices */
> -struct pmx_dev_mode pmx_firda_modes[] = {
> +static struct pmx_dev_mode pmx_firda_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_FIRDA_MASK,
> @@ -116,7 +116,7 @@ struct pmx_dev pmx_firda = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_i2c_modes[] = {
> +static struct pmx_dev_mode pmx_i2c_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_I2C_MASK,
> @@ -130,7 +130,7 @@ struct pmx_dev pmx_i2c = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_ssp_cs_modes[] = {
> +static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_SSP_CS_MASK,
> @@ -144,7 +144,7 @@ struct pmx_dev pmx_ssp_cs = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_ssp_modes[] = {
> +static struct pmx_dev_mode pmx_ssp_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_SSP_MASK,
> @@ -158,7 +158,7 @@ struct pmx_dev pmx_ssp = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_mii_modes[] = {
> +static struct pmx_dev_mode pmx_mii_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_MII_MASK,
> @@ -172,7 +172,7 @@ struct pmx_dev pmx_mii = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
> +static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_GPIO_PIN0_MASK,
> @@ -186,7 +186,7 @@ struct pmx_dev pmx_gpio_pin0 = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
> +static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_GPIO_PIN1_MASK,
> @@ -200,7 +200,7 @@ struct pmx_dev pmx_gpio_pin1 = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
> +static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_GPIO_PIN2_MASK,
> @@ -214,7 +214,7 @@ struct pmx_dev pmx_gpio_pin2 = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
> +static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_GPIO_PIN3_MASK,
> @@ -228,7 +228,7 @@ struct pmx_dev pmx_gpio_pin3 = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
> +static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_GPIO_PIN4_MASK,
> @@ -242,7 +242,7 @@ struct pmx_dev pmx_gpio_pin4 = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
> +static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_GPIO_PIN5_MASK,
> @@ -256,7 +256,7 @@ struct pmx_dev pmx_gpio_pin5 = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_uart0_modem_modes[] = {
> +static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_UART0_MODEM_MASK,
> @@ -270,7 +270,7 @@ struct pmx_dev pmx_uart0_modem = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_uart0_modes[] = {
> +static struct pmx_dev_mode pmx_uart0_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_UART0_MASK,
> @@ -284,7 +284,7 @@ struct pmx_dev pmx_uart0 = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_timer_3_4_modes[] = {
> +static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_TIMER_3_4_MASK,
> @@ -298,7 +298,7 @@ struct pmx_dev pmx_timer_3_4 = {
>  	.enb_on_reset = 0,
>  };
>  
> -struct pmx_dev_mode pmx_timer_1_2_modes[] = {
> +static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
>  	{
>  		.ids = 0xffffffff,
>  		.mask = PMX_TIMER_1_2_MASK,
> @@ -314,7 +314,7 @@ struct pmx_dev pmx_timer_1_2 = {
>  
>  #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
>  /* plgpios devices */
> -struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_FIRDA_MASK,
> @@ -328,7 +328,7 @@ struct pmx_dev pmx_plgpio_0_1 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_UART0_MASK,
> @@ -342,7 +342,7 @@ struct pmx_dev pmx_plgpio_2_3 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_I2C_MASK,
> @@ -356,7 +356,7 @@ struct pmx_dev pmx_plgpio_4_5 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_SSP_MASK,
> @@ -370,7 +370,7 @@ struct pmx_dev pmx_plgpio_6_9 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_MII_MASK,
> @@ -384,7 +384,7 @@ struct pmx_dev pmx_plgpio_10_27 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_28_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_GPIO_PIN0_MASK,
> @@ -398,7 +398,7 @@ struct pmx_dev pmx_plgpio_28 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_29_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_GPIO_PIN1_MASK,
> @@ -412,7 +412,7 @@ struct pmx_dev pmx_plgpio_29 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_30_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_GPIO_PIN2_MASK,
> @@ -426,7 +426,7 @@ struct pmx_dev pmx_plgpio_30 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_31_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_GPIO_PIN3_MASK,
> @@ -440,7 +440,7 @@ struct pmx_dev pmx_plgpio_31 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_32_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_GPIO_PIN4_MASK,
> @@ -454,7 +454,7 @@ struct pmx_dev pmx_plgpio_32 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_33_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_GPIO_PIN5_MASK,
> @@ -468,7 +468,7 @@ struct pmx_dev pmx_plgpio_33 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_SSP_CS_MASK,
> @@ -482,7 +482,7 @@ struct pmx_dev pmx_plgpio_34_36 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_UART0_MODEM_MASK,
> @@ -496,7 +496,7 @@ struct pmx_dev pmx_plgpio_37_42 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_TIMER_1_2_MASK,
> @@ -510,7 +510,7 @@ struct pmx_dev pmx_plgpio_43_44_47_48 = {
>  	.enb_on_reset = 1,
>  };
>  
> -struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
> +static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
>  	{
>  		.ids = 0x00,
>  		.mask = PMX_TIMER_3_4_MASK,

These structures are not local, they are used in spear3**_evb.c files,
and hence can't be static.


From viresh.kumar at st.com  Mon Jun 14 01:18:17 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Mon, 14 Jun 2010 10:48:17 +0530
Subject: [PATCH 2/5] SPEAR3xx: Rename register/irq defines to remove naming
	conflicts
In-Reply-To: <1275717955-14545-3-git-send-email-ryan@bluewatersys.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
	<1275717955-14545-3-git-send-email-ryan@bluewatersys.com>
Message-ID: <4C15BB99.4060108@st.com>

On 6/5/2010 11:35 AM, Ryan Mallon wrote:
> Prefix register and irq defintions to remove naming conflicts between
> the three SPEAr3xx platforms.
> 
> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
> ---
>  arch/arm/mach-spear3xx/include/mach/generic.h  |    4 +-
>  arch/arm/mach-spear3xx/include/mach/irqs.h     |  195 ++++++++++++------------
>  arch/arm/mach-spear3xx/include/mach/spear300.h |   26 ++--
>  arch/arm/mach-spear3xx/include/mach/spear310.h |   44 +++---
>  arch/arm/mach-spear3xx/include/mach/spear320.h |   50 +++---
>  arch/arm/mach-spear3xx/spear300.c              |   65 ++++----
>  arch/arm/mach-spear3xx/spear310.c              |   92 ++++++------
>  arch/arm/mach-spear3xx/spear320.c              |  134 ++++++++--------
>  arch/arm/mach-spear3xx/spear3xx.c              |    4 +-
>  9 files changed, 308 insertions(+), 306 deletions(-)
> 
> diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
> index af7e02c..48dfb9c 100644
> --- a/arch/arm/mach-spear3xx/include/mach/generic.h
> +++ b/arch/arm/mach-spear3xx/include/mach/generic.h
> @@ -27,8 +27,8 @@
>   * Following GPT channels will be used as clock source and clockevent
>   */
>  #define SPEAR_GPT0_BASE		SPEAR3XX_ML1_TMR_BASE
> -#define SPEAR_GPT0_CHAN0_IRQ	IRQ_CPU_GPT1_1
> -#define SPEAR_GPT0_CHAN1_IRQ	IRQ_CPU_GPT1_2
> +#define SPEAR_GPT0_CHAN0_IRQ	SPEAR3XX_IRQ_CPU_GPT1_1
> +#define SPEAR_GPT0_CHAN1_IRQ	SPEAR3XX_IRQ_CPU_GPT1_2
>  
>  /* Add spear3xx family device structure declarations here */
>  extern struct amba_device gpio_device;
> diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
> index 7f940b8..668bf72 100644
> --- a/arch/arm/mach-spear3xx/include/mach/irqs.h
> +++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
> @@ -15,138 +15,141 @@
>  #define __MACH_IRQS_H
>  
>  /* SPEAr3xx IRQ definitions */
> -#define IRQ_HW_ACCEL_MOD_0			0
> -#define IRQ_INTRCOMM_RAS_ARM			1
> -#define IRQ_CPU_GPT1_1				2
> -#define IRQ_CPU_GPT1_2				3
> -#define IRQ_BASIC_GPT1_1			4
> -#define IRQ_BASIC_GPT1_2			5
> -#define IRQ_BASIC_GPT2_1			6
> -#define IRQ_BASIC_GPT2_2			7
> -#define IRQ_BASIC_DMA				8
> -#define IRQ_BASIC_SMI				9
> -#define IRQ_BASIC_RTC				10
> -#define IRQ_BASIC_GPIO				11
> -#define IRQ_BASIC_WDT				12
> -#define IRQ_DDR_CONTROLLER			13
> -#define IRQ_SYS_ERROR				14
> -#define IRQ_WAKEUP_RCV				15
> -#define IRQ_JPEG				16
> -#define IRQ_IRDA				17
> -#define IRQ_ADC					18
> -#define IRQ_UART				19
> -#define IRQ_SSP					20
> -#define IRQ_I2C					21
> -#define IRQ_MAC_1				22
> -#define IRQ_MAC_2				23
> -#define IRQ_USB_DEV				24
> -#define IRQ_USB_H_OHCI_0			25
> -#define IRQ_USB_H_EHCI_0			26
> -#define IRQ_USB_H_EHCI_1			IRQ_USB_H_EHCI_0
> -#define IRQ_USB_H_OHCI_1			27
> -#define IRQ_GEN_RAS_1				28
> -#define IRQ_GEN_RAS_2				29
> -#define IRQ_GEN_RAS_3				30
> -#define IRQ_HW_ACCEL_MOD_1			31
> -#define IRQ_VIC_END				32
> -
> -#define VIRQ_START				IRQ_VIC_END
> +#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0		0
> +#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM		1
> +#define SPEAR3XX_IRQ_CPU_GPT1_1			2
> +#define SPEAR3XX_IRQ_CPU_GPT1_2			3
> +#define SPEAR3XX_IRQ_BASIC_GPT1_1		4
> +#define SPEAR3XX_IRQ_BASIC_GPT1_2		5
> +#define SPEAR3XX_IRQ_BASIC_GPT2_1		6
> +#define SPEAR3XX_IRQ_BASIC_GPT2_2		7
> +#define SPEAR3XX_IRQ_BASIC_DMA			8
> +#define SPEAR3XX_IRQ_BASIC_SMI			9
> +#define SPEAR3XX_IRQ_BASIC_RTC			10
> +#define SPEAR3XX_IRQ_BASIC_GPIO			11
> +#define SPEAR3XX_IRQ_BASIC_WDT			12
> +#define SPEAR3XX_IRQ_DDR_CONTROLLER		13
> +#define SPEAR3XX_IRQ_SYS_ERROR			14
> +#define SPEAR3XX_IRQ_WAKEUP_RCV			15
> +#define SPEAR3XX_IRQ_JPEG			16
> +#define SPEAR3XX_IRQ_IRDA			17
> +#define SPEAR3XX_IRQ_ADC			18
> +#define SPEAR3XX_IRQ_UART			19
> +#define SPEAR3XX_IRQ_SSP			20
> +#define SPEAR3XX_IRQ_I2C			21
> +#define SPEAR3XX_IRQ_MAC_1			22
> +#define SPEAR3XX_IRQ_MAC_2			23
> +#define SPEAR3XX_IRQ_USB_DEV			24
> +#define SPEAR3XX_IRQ_USB_H_OHCI_0		25
> +#define SPEAR3XX_IRQ_USB_H_EHCI_0		26
> +#define SPEAR3XX_IRQ_USB_H_EHCI_1		SPEAR3XX_IRQ_USB_H_EHCI_0
> +#define SPEAR3XX_IRQ_USB_H_OHCI_1		27
> +#define SPEAR3XX_IRQ_GEN_RAS_1			28
> +#define SPEAR3XX_IRQ_GEN_RAS_2			29
> +#define SPEAR3XX_IRQ_GEN_RAS_3			30
> +#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1		31
> +#define SPEAR3XX_IRQ_VIC_END			32
> +

We have kept it, the way it was intentionally. I don't understand why any
conflicts will occur.


From kgene.kim at samsung.com  Mon Jun 14 01:18:53 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 14 Jun 2010 14:18:53 +0900
Subject: [PATCH v4 2/3] ARM: S5PV210: Add keypad device helpers
In-Reply-To: <1276243728-17704-2-git-send-email-jy0922.shim@samsung.com>
References: <1276243728-17704-1-git-send-email-jy0922.shim@samsung.com>
	<1276243728-17704-2-git-send-email-jy0922.shim@samsung.com>
Message-ID: <007801cb0b81$16cc0ff0$44642fd0$%kim@samsung.com>

Joonyoung Shim wrote:
> 
> This patch adds the keypad device platform helpers for S5PV210 cpu.
> 
> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-s5pv210/Kconfig            |    5 ++++
>  arch/arm/mach-s5pv210/Makefile           |    1 +
>  arch/arm/mach-s5pv210/cpu.c              |    4 +++
>  arch/arm/mach-s5pv210/include/mach/map.h |    3 ++
>  arch/arm/mach-s5pv210/setup-keypad.c     |   34
> ++++++++++++++++++++++++++++++
>  5 files changed, 47 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-s5pv210/setup-keypad.c
> 
> diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
> index 0761eac..692d01c 100644
> --- a/arch/arm/mach-s5pv210/Kconfig
> +++ b/arch/arm/mach-s5pv210/Kconfig
> @@ -32,6 +32,11 @@ config S5PV210_SETUP_FB_24BPP
>  	help
>            Common setup code for S5PV210 with an 24bpp RGB display helper.
> 
> +config S5PV210_SETUP_KEYPAD
> +	bool
> +	help
> +	  Common setup code for keypad.
> +
>  config S5PV210_SETUP_SDHCI
>          bool
>          select S5PV210_SETUP_SDHCI_GPIO
> diff --git a/arch/arm/mach-s5pv210/Makefile
b/arch/arm/mach-s5pv210/Makefile
> index 30be9a6..aae592a 100644
> --- a/arch/arm/mach-s5pv210/Makefile
> +++ b/arch/arm/mach-s5pv210/Makefile
> @@ -31,5 +31,6 @@ obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o
>  obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
>  obj-$(CONFIG_S5PV210_SETUP_I2C1) 	+= setup-i2c1.o
>  obj-$(CONFIG_S5PV210_SETUP_I2C2) 	+= setup-i2c2.o
> +obj-$(CONFIG_S5PV210_SETUP_KEYPAD)	+= setup-keypad.o
>  obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
>  obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
> diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
> index 411a4a9..a3034ac 100644
> --- a/arch/arm/mach-s5pv210/cpu.c
> +++ b/arch/arm/mach-s5pv210/cpu.c
> @@ -80,6 +80,10 @@ void __init s5pv210_map_io(void)
>  	s3c_device_adc.name	= "s3c64xx-adc";
>  #endif
> 
> +#ifdef CONFIG_SAMSUNG_DEV_KEYPAD
> +	samsung_device_keypad.name = "s5pv210-keypad";
> +#endif
> +

Please use one method. See Kyungmin Park's prev. comments on the subject.

>  	iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
> 
>  	/* initialise device information early */
> diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-
> s5pv210/include/mach/map.h
> index 34eb168..e2f6e2a 100644
> --- a/arch/arm/mach-s5pv210/include/mach/map.h
> +++ b/arch/arm/mach-s5pv210/include/mach/map.h
> @@ -32,6 +32,8 @@
>  #define S5PV210_PA_SPI0		0xE1300000
>  #define S5PV210_PA_SPI1		0xE1400000
> 
> +#define S5PV210_PA_KEYPAD	(0xE1600000)
> +
>  #define S5PV210_PA_IIC0		(0xE1800000)
>  #define S5PV210_PA_IIC1		(0xFAB00000)
>  #define S5PV210_PA_IIC2		(0xE1A00000)
> @@ -104,5 +106,6 @@
>  #define S3C_PA_WDT		S5PV210_PA_WATCHDOG
> 
>  #define SAMSUNG_PA_ADC		S5PV210_PA_ADC
> +#define SAMSUNG_PA_KEYPAD	S5PV210_PA_KEYPAD
> 
>  #endif /* __ASM_ARCH_MAP_H */
> diff --git a/arch/arm/mach-s5pv210/setup-keypad.c
b/arch/arm/mach-s5pv210/setup-
> keypad.c
> new file mode 100644
> index 0000000..f51bf8d
> --- /dev/null
> +++ b/arch/arm/mach-s5pv210/setup-keypad.c
> @@ -0,0 +1,34 @@
> +/*
> + * linux/arch/arm/mach-s5pv210/setup-keypad.c
> + *
> + * Copyright (C) 2010 Samsung Electronics Co.Ltd
> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
> + *
> + *  This program is free software; you can redistribute  it and/or modify
it
> + *  under  the terms of  the GNU General  Public License as published by
the
> + *  Free Software Foundation;  either version 2 of the  License, or (at
your
> + *  option) any later version.
> + *
> + */
> +
> +#include <linux/gpio.h>
> +#include <plat/gpio-cfg.h>
> +
> +void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
> +{
> +	unsigned int gpio, end;
> +
> +	/* Set all the necessary GPH3 pins to special-function 3 */

What's the special-function 3?
How about 'special function KP_ROWs'?

> +	end = S5PV210_GPH3(rows);
> +	for (gpio = S5PV210_GPH3(0); gpio < end; gpio++) {
> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> +	}
> +
> +	/* Set all the necessary GPH2 pins to special-function 3 */

How about 'special function KP_COLs'?

> +	end = S5PV210_GPH2(cols);
> +	for (gpio = S5PV210_GPH2(0); gpio < end; gpio++) {
> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> +	}
> +}
> --


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From viresh.kumar at st.com  Mon Jun 14 01:21:13 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Mon, 14 Jun 2010 10:51:13 +0530
Subject: [PATCH 3/5] SPEAr3xx: Rework pmx_dev code to remove conflicts
In-Reply-To: <1275717955-14545-4-git-send-email-ryan@bluewatersys.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
	<1275717955-14545-4-git-send-email-ryan@bluewatersys.com>
Message-ID: <4C15BC49.5040105@st.com>

On 6/5/2010 11:35 AM, Ryan Mallon wrote:
> Prefix the pmx_devs to remove naming conflicts between the three
> SPEAr3xx platforms. Also make pmx_driver static to each platform and
> rework the init code to pass the devices rather than export the
> pmx_driver structure.
> 
> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
> ---
>  arch/arm/mach-spear3xx/include/mach/generic.h |  135 ++++++++++++-------------
>  arch/arm/mach-spear3xx/spear300.c             |   39 ++++----
>  arch/arm/mach-spear3xx/spear300_evb.c         |   26 ++---
>  arch/arm/mach-spear3xx/spear310.c             |   29 +++---
>  arch/arm/mach-spear3xx/spear310_evb.c         |   42 ++++-----
>  arch/arm/mach-spear3xx/spear320.c             |   57 ++++++-----
>  arch/arm/mach-spear3xx/spear320_evb.c         |   36 +++----
>  arch/arm/mach-spear3xx/spear3xx.c             |   60 ++++++------
>  8 files changed, 202 insertions(+), 222 deletions(-)
> 
> diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
> index 48dfb9c..408d39f 100644
> --- a/arch/arm/mach-spear3xx/include/mach/generic.h
> +++ b/arch/arm/mach-spear3xx/include/mach/generic.h
> @@ -60,21 +60,21 @@ void spear_pmx_init(struct pmx_driver *pmx_driver, uint base, uint size);
>  #define PMX_TIMER_1_2_MASK	(1 << 0)
>  
>  /* pad mux devices */
> -extern struct pmx_dev pmx_firda;
> -extern struct pmx_dev pmx_i2c;
> -extern struct pmx_dev pmx_ssp_cs;
> -extern struct pmx_dev pmx_ssp;
> -extern struct pmx_dev pmx_mii;
> -extern struct pmx_dev pmx_gpio_pin0;
> -extern struct pmx_dev pmx_gpio_pin1;
> -extern struct pmx_dev pmx_gpio_pin2;
> -extern struct pmx_dev pmx_gpio_pin3;
> -extern struct pmx_dev pmx_gpio_pin4;
> -extern struct pmx_dev pmx_gpio_pin5;
> -extern struct pmx_dev pmx_uart0_modem;
> -extern struct pmx_dev pmx_uart0;
> -extern struct pmx_dev pmx_timer_3_4;
> -extern struct pmx_dev pmx_timer_1_2;
> +extern struct pmx_dev spear3xx_pmx_firda;
> +extern struct pmx_dev spear3xx_pmx_i2c;
> +extern struct pmx_dev spear3xx_pmx_ssp_cs;
> +extern struct pmx_dev spear3xx_pmx_ssp;
> +extern struct pmx_dev spear3xx_pmx_mii;
> +extern struct pmx_dev spear3xx_pmx_gpio_pin0;
> +extern struct pmx_dev spear3xx_pmx_gpio_pin1;
> +extern struct pmx_dev spear3xx_pmx_gpio_pin2;
> +extern struct pmx_dev spear3xx_pmx_gpio_pin3;
> +extern struct pmx_dev spear3xx_pmx_gpio_pin4;
> +extern struct pmx_dev spear3xx_pmx_gpio_pin5;
> +extern struct pmx_dev spear3xx_pmx_uart0_modem;
> +extern struct pmx_dev spear3xx_pmx_uart0;
> +extern struct pmx_dev spear3xx_pmx_timer_3_4;
> +extern struct pmx_dev spear3xx_pmx_timer_1_2;
>  

same here. I don't understand why any conflicts will be there.

[snip...]

>  
>  /* pmx driver structure */
> -struct pmx_driver pmx_driver = {
> +static struct pmx_driver pmx_driver = {
>  	.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
>  	.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
>  };
> @@ -511,7 +511,8 @@ static struct spear_shirq shirq_intrcomm_ras = {
>  };
>  
>  /* spear320 routines */
> -void __init spear320_init(void)
> +void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
> +			  u8 pmx_dev_count)
>  {
>  	void __iomem *base;
>  	int ret = 0;
> @@ -540,10 +541,10 @@ void __init spear320_init(void)
>  		if (ret)
>  			printk(KERN_ERR "Error registering Shared IRQ 4\n");
>  	}
> -}
>  
> -void spear320_pmx_init(void)
> -{
> +	pmx_driver.mode = pmx_mode;
> +	pmx_driver.devs = pmx_devs;
> +	pmx_driver.devs_count = pmx_dev_count;
>  	spear_pmx_init(&pmx_driver, SPEAR320_SOC_CONFIG_BASE,
> -			SPEAR320_SOC_CONFIG_SIZE);
> +		       SPEAR320_SOC_CONFIG_SIZE);
>  }

This part looks fine.

> diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
> index 62ac685..4969fa9 100644
> --- a/arch/arm/mach-spear3xx/spear320_evb.c
> +++ b/arch/arm/mach-spear3xx/spear320_evb.c
> @@ -19,22 +19,22 @@
>  
>  static struct amba_device *amba_devs[] __initdata = {
> @@ -56,13 +56,7 @@ static void __init spear320_evb_init(void)
>  	unsigned int i;
>  
>  	/* call spear320 machine init function */
> -	spear320_init();
> -
> -	/* padmux initialization */
> -	pmx_driver.mode = &auto_net_mii_mode;
> -	pmx_driver.devs = pmx_devs;
> -	pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
> -	spear320_pmx_init();
> +	spear320_init(&auto_net_mii_mode, pmx_devs, ARRAY_SIZE(pmx_devs));

this is also fine.


From grant.likely at secretlab.ca  Mon Jun 14 01:23:45 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sun, 13 Jun 2010 23:23:45 -0600
Subject: Request review of device tree documentation
In-Reply-To: <1276408773.1962.574.camel@pasglop>
References: <AANLkTilK4YkRMJqlcRDOAlGBzpdlZuSo9NF5NrRNocHT@mail.gmail.com> 
	<33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com>
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com> 
	<4C13430B.5000907@firmworks.com> <1276339529.1962.184.camel@pasglop> 
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com> 
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com> 
	<4C146F18.9030008@firmworks.com> <1276408773.1962.574.camel@pasglop>
Message-ID: <AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com>

[cc'ing linux-arm-kernel]

On Sat, Jun 12, 2010 at 11:59 PM, Benjamin Herrenschmidt
<benh at kernel.crashing.org> wrote:
> On Sat, 2010-06-12 at 19:39 -1000, Mitch Bradley wrote:
>
>> Minimally, OFW needs to own some memory that the kernel won't steal.
>> OFW on ARM is position-independent, so it can be tucked up at the top of memory
>> fairly easily.
>
> Amen :-)
>
>> To call back into OFW, the virtual mapping for that memory needs to be
>> reestablished.
>
> That's a nasty part unless ARM provides a usable "real mode" which
> allows MMIO accesses, which I -think- it does. I don't remember the
> details that much.
>
> Maybe we could define a binding tho where we could somewhat standardize
> the portion of the virtual address space used by OF. IE. from the top of
> the address space down to the max size it requires. It might require
> some games to play with the fixmap on ARM side tho...
>
> Another option would be something more RTAS-like where a specific call
> can be done by the OS itself to 'relocate' (not physically but virtually
> in this case) OF into the OS preferred location. Be prepared to have
> multiple of these called though as kernels kexec into one another.

This sounds reasonable to me.

>> Or perhaps the MMU and caches can be turned off for the duration of the
>> callback.
>> I don't have the details of ARM MMUs and caches reloaded into my head
>> yet. ?Maybe next week...
>
> Forgot most of it too. Looks like it's about time I read the ARM
> architecture again, this sounds like fun :-)
>
> BTW. I notice no ARM list is CCed on this discussion ... maybe we should
> fix that ?

cc'ing linux-arm-kernel in all my replies

>> Also, for debugging, OFW typically needs access to a UART. ?If the OS is
>> using the UART, it's often possible for OFW to use it just by turning off interrupts and
>> polling the UART.
>
> That might not be a big deal unless the OS plays with the clocks which
> it -does- tend to do. It might be worth defining some kind of property
> OF puts in the UART node to inform the OS not to play games and keep
> that one enabled, though that could affect power management, so might
> need to be conditional on some nvram option (debug-enabled?)
>
>> The use case for a dynamic device tree is not compelling.
>
> Right, generally not, except in virtualized environments (see my other
> response).
>
> Now, the -one- thing that WILL happen if we have something like OF that
> remains alive is of course vendors will try to use it as a HAL. You know
> as well as I do that it -will- happen :-)
>
> There's two reasons that typically happen. The misguided "good" one
> which is to think it helps keeping a single/more maintainable kernel
> image by stuffing the horrible details of nvram, rtc, etc.. access,
> poweron/off GPIOs, clock control, etc... in there. The "bad" one which
> is to stash code you don't want to show the source code for (codec
> control, etc...).
>
> This is bad for so many reasons that I don't think I need to even start
> listing them :-) So that's something that will have to be strongly kept
> in check and fought I suspect.

With a stout 2x4 if needed.  I'm going to try very hard to dissuade
this.  Yet another reason why I only what one method for passing the
device tree into the kernel.

> To some extent, in fact, doing that sort of stuff in OF or even in RTAS
> like we do on power is even worse than ACPI-like tables. At least with
> those tables, the interpreter is in the operating system, thus can run
> with interrupts on, scheduling on, etc... With RTAS, or client interface
> calls, you'll end up with potentially huge slumps of CPU time "lost"
> into the bowels of the firmware.

Unfortunately, on the newer ARM SoCs, binary blobs are all over the
place anyway.  :-(

g.


From ryan at bluewatersys.com  Mon Jun 14 01:31:30 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Mon, 14 Jun 2010 17:31:30 +1200
Subject: [PATCH 1/5] SPEAr3xx: Make local structres static
In-Reply-To: <4C15BB22.9010309@st.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
	<1275717955-14545-2-git-send-email-ryan@bluewatersys.com>
	<4C15BB22.9010309@st.com>
Message-ID: <4C15BEB2.1030004@bluewatersys.com>

Viresh KUMAR wrote:
> On 6/5/2010 11:35 AM, Ryan Mallon wrote:
>> Several structures in arch/arm/mach-spear3xx are not marked static
>> like they should be. Fix this.
>>
>> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
>> ---
>>  arch/arm/mach-spear3xx/spear300.c |   33 ++++++++++----------
>>  arch/arm/mach-spear3xx/spear310.c |   16 +++++-----
>>  arch/arm/mach-spear3xx/spear320.c |   56 +++++++++++++++++-----------------
>>  arch/arm/mach-spear3xx/spear3xx.c |   60 ++++++++++++++++++------------------
>>  4 files changed, 83 insertions(+), 82 deletions(-)
>>

<snip>

>> -struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
>> +static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
>>  	{
>>  		.ids = 0x00,
>>  		.mask = PMX_TIMER_3_4_MASK,
> 
> These structures are not local, they are used in spear3**_evb.c files,
> and hence can't be static.

The pmx_dev structures are used by the spear3**_evb.c files, but the
pmx_dev_mode structures are local. This patch is only making the latter
static. I have done a build test which includes all three spear3**_evb
board files and got no compilation warnings/errors.

~Ryan



From richardcochran at gmail.com  Mon Jun 14 01:36:23 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Mon, 14 Jun 2010 07:36:23 +0200
Subject: [PATCH 0/3] Support for three IXP425 based boards
In-Reply-To: <m3y6ej9790.fsf@intrepid.localdomain>
References: <cover.1275415521.git.richard.cochran@omicron.at>
	<m3y6ej9790.fsf@intrepid.localdomain>
Message-ID: <20100614053623.GA2753@riccoc20.at.omicron.at>

On Sun, Jun 13, 2010 at 01:11:07AM +0200, Krzysztof Halasa wrote:
> Sorry I'm unable to look at the patches at this time. Will do. The other
> thing is Linus apparently hasn't pulled the previous portion. It has to
> wait for another week+, too.

There is no rush. Also, after following the discussion about all the
"arch/arm/mach" noise and churning, I think it might be better to
combine these there boards into one file. They are quite similar to
each other. Maybe I will resubmit before too long...

Thanks in advance for your review,

Richard


From ryan at bluewatersys.com  Mon Jun 14 01:36:28 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Mon, 14 Jun 2010 17:36:28 +1200
Subject: [PATCH 2/5] SPEAR3xx: Rename register/irq defines to remove naming
	conflicts
In-Reply-To: <4C15BB99.4060108@st.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
	<1275717955-14545-3-git-send-email-ryan@bluewatersys.com>
	<4C15BB99.4060108@st.com>
Message-ID: <4C15BFDC.70809@bluewatersys.com>

Viresh KUMAR wrote:
> On 6/5/2010 11:35 AM, Ryan Mallon wrote:
>> Prefix register and irq defintions to remove naming conflicts between
>> the three SPEAr3xx platforms.
>>
>> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
>> ---
>>  arch/arm/mach-spear3xx/include/mach/generic.h  |    4 +-
>>  arch/arm/mach-spear3xx/include/mach/irqs.h     |  195 ++++++++++++------------
>>  arch/arm/mach-spear3xx/include/mach/spear300.h |   26 ++--
>>  arch/arm/mach-spear3xx/include/mach/spear310.h |   44 +++---
>>  arch/arm/mach-spear3xx/include/mach/spear320.h |   50 +++---
>>  arch/arm/mach-spear3xx/spear300.c              |   65 ++++----
>>  arch/arm/mach-spear3xx/spear310.c              |   92 ++++++------
>>  arch/arm/mach-spear3xx/spear320.c              |  134 ++++++++--------
>>  arch/arm/mach-spear3xx/spear3xx.c              |    4 +-
>>  9 files changed, 308 insertions(+), 306 deletions(-)
>>
>> diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
>> index af7e02c..48dfb9c 100644
>> --- a/arch/arm/mach-spear3xx/include/mach/generic.h
>> +++ b/arch/arm/mach-spear3xx/include/mach/generic.h
>> @@ -27,8 +27,8 @@
>>   * Following GPT channels will be used as clock source and clockevent
>>   */
>>  #define SPEAR_GPT0_BASE		SPEAR3XX_ML1_TMR_BASE
>> -#define SPEAR_GPT0_CHAN0_IRQ	IRQ_CPU_GPT1_1
>> -#define SPEAR_GPT0_CHAN1_IRQ	IRQ_CPU_GPT1_2
>> +#define SPEAR_GPT0_CHAN0_IRQ	SPEAR3XX_IRQ_CPU_GPT1_1
>> +#define SPEAR_GPT0_CHAN1_IRQ	SPEAR3XX_IRQ_CPU_GPT1_2
>>  

<snip>

> 
> We have kept it, the way it was intentionally. I don't understand why any
> conflicts will occur.

The goal of the patch series is to allow all a single kernel to have
support for all of the spear platforms, ie CONFIG_MACH_SPEAR300,
CONFIG_MACH_SPEAR310 and CONFIG_MACH_SPEAR320 can all be set.

The current code has duplicate defines in
arch/arm/mach-spear3xx/include/mach/spear3[012]0.h which means that
these three files cannot be included at once (they are included from
arch/arm/mach-spear3xx/include/mach/spear.h).

~Ryan



From grant.likely at secretlab.ca  Mon Jun 14 01:36:57 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sun, 13 Jun 2010 23:36:57 -0600
Subject: Request review of device tree documentation
In-Reply-To: <1276417792.1962.731.camel@pasglop>
References: <AANLkTilK4YkRMJqlcRDOAlGBzpdlZuSo9NF5NrRNocHT@mail.gmail.com> 
	<33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com>
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com> 
	<4C13430B.5000907@firmworks.com> <1276339529.1962.184.camel@pasglop> 
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com> 
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com> 
	<4C146F18.9030008@firmworks.com> <1276408773.1962.574.camel@pasglop> 
	<4C147EA5.3060500@firmworks.com> <1276417792.1962.731.camel@pasglop>
Message-ID: <AANLkTimc12G-YYTd4yQiviY-ijvJ9TzVEmxxaoF43xVR@mail.gmail.com>

On Sun, Jun 13, 2010 at 2:29 AM, Benjamin Herrenschmidt
<benh at kernel.crashing.org> wrote:
> On Sat, 2010-06-12 at 20:45 -1000, Mitch Bradley wrote:
>
>> Either fought or embraced. ?To the extent that it is possible to focus
>> solely on Linux and ARM, one could image doing a good HAL.
>
> That will come with a huge amount of comunity resistance sadly, but I
> can imagine distros liking it.
>
> In general, I much prefer having all the necessary native drivers in the
> kernel, and the device-tree to provide the right representation, and
> avoid trying to abstract "methods" via a HAL. It's the Linux philosophy
> as much as possible (even when defeated by ACPI).
>
> But if we're going to be forced by vendors into HALs, we can also make
> sure that whatever they come up with is half reasonable :-)

I think there is more to be concerned about regarding binary blobs
than HALs.  Many of the new SoCs require closed binaries to use all
the hardware right now (graphics cores in particular).

Board vendors seem to be taking the plunge and modifying the kernel
rather than trying to create a HAL for driving board specific
features.

>> (The reason I say ARM-only is ?because the
>> only other non-x86 architecture that has any "legs" left is PowerPC, and
>> PPC already has a coherent story.)
>
> Well, ppc story isn't that coherent as far as this goes :-) We don't
> keep OF alive, we have RTAS which is a pile of poo... etc...
>
> But yeah, we are fine without a HAL, so if we stick to OF as a
> bootloader and provider of the device-tree, we are fine.
>
>> > To some extent, in fact, doing that sort of stuff in OF or even in RTAS
>> > like we do on power is even worse than ACPI-like tables. At least with
>> > those tables, the interpreter is in the operating system, thus can run
>> > with interrupts on, scheduling on, etc...
>>
>> I have an FCode interpreter that can live inside the OS. ?It's
>> considerably simpler than the ACPI interpreter.
>
> That's the one thing I purposefully avoided mentioning :-)
>
> It's an interesting idea, I've though about it. If course, there's all
> sort of things to be careful about, such as who provides the f-code with
> virtual->physical mappings to devices, how they are represented, how
> much of the OF "forth" environment is accessible to such f-code, locking
> between f-code and kernel use of shared resources (especially true when
> dealing with things like i2c devices, plls, etc...).
>
> IE. THe base idea is simple. The implementation can be a huge can of
> worms.
>
> Cheers,
> Ben.
>
>> > ?With RTAS, or client interface
>> > calls, you'll end up with potentially huge slumps of CPU time "lost"
>> > into the bowels of the firmware.
>> >
>> >
>> > Cheers,
>> > Ben.
>> >
>> >
>> >
>
>
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From m.szyprowski at samsung.com  Mon Jun 14 01:40:11 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 14 Jun 2010 07:40:11 +0200
Subject: s3c-hsotg fixes
In-Reply-To: <20100612033429.GJ3498@trinity.fluff.org>
References: <1276244457-4072-1-git-send-email-ben-linux@fluff.org>
	<006c01cb0950$6ced3630$46c7a290$%szyprowski@samsung.com>
	<20100612033429.GJ3498@trinity.fluff.org>
Message-ID: <008f01cb0b84$10f8a3b0$32e9eb10$%szyprowski@samsung.com>

Hello,

On Saturday, June 12, 2010 5:34 AM Ben Dooks wrote:

> On Fri, Jun 11, 2010 at 12:25:26PM +0200, Marek Szyprowski wrote:
> > Hello,
> >
> > On Friday, June 11, 2010 10:21 AM Ben Dooks wrote:
> >
> > > Some further fixes for the s3c-hsotg block, as well as a repost of
> > > the missed USB phy clock setting patch which either got missed or
> > > passed over from last time.
> > >
> > > As a note, this series has a patch adding support for dedicated FIFO
> > > mode, this is in my view a fix, as when the hsotg block is compiled
> > > with dedicated fifos then each USB IN non-periodic pipe needs to be
> > > alloacted a unique TX FIFO. We have no actual data on how well the
> > > block performs when all IN TX NP FIFOs are all set to the same one,
> > > but it really should be fixed.
> >
> > This patch series improves the driver a lot. Now it is possible to get
> > CDC Ethernet gadget working on S5PV210 SoC (Samsung Aquila machine).
> > However there are still some issues left to be resolved. I've noticed
> > the following things:
> >
> > 1. CDC Ethernet gadget: there are problems after unplugging and
> > plugging the usb cable again while data is being transferred. To trigger
> > this it is enough to run 'ping host' command on the device and replug
> > the usb cable. After that no data packets are sent do the usb host
> > (checked with hardware usb analyser), although the ep0 control transfers
> > are performed correctly (device has been enumerated correctly).
> 
> Hmm, that is intereting. Maybe we broke non-ep0 fifos somehow
> 
> > 2. RNDIS Ethernet gadget: after some stress tests I get an error, which
> > causes RNDIS session to hang (what is probably a direct result of the
> > otg block reinit/reset). Here is an example log:
> 
> any particular kind of stress tests, or are you just telling it nasty
> things to upset it? will try and look into this too.

I've tested it with Windows XP SP3 host (Pentium4 2.8GHz, VIA USB 2.0 EHCI
controller) and the following script:

--->8--[killer.bat]---
:foo
ping 192.168.129.3
goto foo
--->8-----------------

192.168.129.3 is an IP address of the client system (Linux on S5PV210).

Four instances of this script was running simultaneously and a Task Manager
with Network Status tab was opened. Each time when Windows runs ping command
the RNDIS transaction is performed. So this test basically checked how the
driver would act on a flood of RNDIS transactions. Each NDIS transactions
consists of the following transfers: RNDIS Command (ep0-control in), RNDIS
notification (ep3-interrupt in) and RNDIS Response (ep0-control out). All 3
parts of RNDIS transaction must be performed correctly, otherwise Windows
host locks (it is quite easy to notice this, Network Status graph stops
scrolling). The test took about 5 minutes to trigger the issue.

The flood of RNDIS transactions happens also during normal usage, some
firewalls or anti-virus scanning tools also can cause it, so it shouldn't
be considered something really unusual.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center




From viresh.kumar at st.com  Mon Jun 14 01:41:34 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Mon, 14 Jun 2010 11:11:34 +0530
Subject: [PATCH 1/5] SPEAr3xx: Make local structres static
In-Reply-To: <4C15BEB2.1030004@bluewatersys.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
	<1275717955-14545-2-git-send-email-ryan@bluewatersys.com>
	<4C15BB22.9010309@st.com> <4C15BEB2.1030004@bluewatersys.com>
Message-ID: <4C15C10E.9010404@st.com>

On 6/14/2010 11:01 AM, Ryan Mallon wrote:
>>> -struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
>>> >> +static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
>>> >>  	{
>>> >>  		.ids = 0x00,
>>> >>  		.mask = PMX_TIMER_3_4_MASK,
>> > 
>> > These structures are not local, they are used in spear3**_evb.c files,
>> > and hence can't be static.
> The pmx_dev structures are used by the spear3**_evb.c files, but the
> pmx_dev_mode structures are local. This patch is only making the latter
> static. I have done a build test which includes all three spear3**_evb
> board files and got no compilation warnings/errors.

sorry!! You were correct.


From viresh.kumar at st.com  Mon Jun 14 01:46:18 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Mon, 14 Jun 2010 11:16:18 +0530
Subject: [PATCH 2/5] SPEAR3xx: Rename register/irq defines to remove naming
	conflicts
In-Reply-To: <4C15BFDC.70809@bluewatersys.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
	<1275717955-14545-3-git-send-email-ryan@bluewatersys.com>
	<4C15BB99.4060108@st.com> <4C15BFDC.70809@bluewatersys.com>
Message-ID: <4C15C22A.7070408@st.com>

On 6/14/2010 11:06 AM, Ryan Mallon wrote:
> The goal of the patch series is to allow all a single kernel to have
> support for all of the spear platforms, ie CONFIG_MACH_SPEAR300,
> CONFIG_MACH_SPEAR310 and CONFIG_MACH_SPEAR320 can all be set.
> 
> The current code has duplicate defines in
> arch/arm/mach-spear3xx/include/mach/spear3[012]0.h which means that
> these three files cannot be included at once (they are included from
> arch/arm/mach-spear3xx/include/mach/spear.h).

I understood what you did, but i am not sure how will it actually work.
I tried to look into kernel source but couldn't find much.

Suppose all three machines/boards are selected and we got one kernel.
Then how should we tell the kernel which machines init routine to be called.
I suppose through uboot only, but not sure how it internally works.

Can you please help me understand that?

viresh.


From viresh.kumar at st.com  Mon Jun 14 02:02:54 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Mon, 14 Jun 2010 11:32:54 +0530
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 PrimeCells
In-Reply-To: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <4C15C60E.6080404@st.com>

Linus,

I haven't reviewed it completely. Will do it in some time.


On 6/11/2010 8:57 PM, Linus WALLEIJ wrote:

[snip...]

> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
> new file mode 100644
> index 0000000..50531fa
> --- /dev/null
> +++ b/drivers/dma/amba-pl08x.c
> @@ -0,0 +1,1925 @@
> +/*
> + * Copyright (c) 2006 ARM Ltd.
> + * Copyright (c) 2010 ST-Ericsson SA
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the Free
> + * Software Foundation; either version 2 of the License, or (at your option)
> + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program; if not, write to the Free Software Foundation, Inc., 59
> + * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
> + *
> + * The full GNU General Public License is iin this distribution in the
> + * file called COPYING.
> + *
> + * Documentation: ARM DDI 0196G == PL080
> + * Documentation: ARM DDI 0218E	== PL081
> + *
> + * PL080 & PL081 both have 16 sets of DMA signals. They differ in the number
> + * of channels which may be in use at once. Also PL080 has a dual bus master,
> + * PL081 has a single master.
> + *
> + * Memory to peripheral transfer may be visualized as
> + *	Get data from memory to DMAC
> + *	Until no data left
> + *		On burst request from peripheral
> + *			Destination burst from DMAC to peripheral
> + *			Clear burst request
> + *	Raise terminal count interrupt
> + *
> + * For peripherals with a FIFO:
> + * Source      burst size == half the depth of the peripheral FIFO
> + * Destination burst size == width of the peripheral FIFO
> + *

I didn't get it completely, why burst depends upon width of peripheral FIFO.

> + * (Bursts are irrelevant for mem to mem transfers - there are no burst
> + * signals)

I agree that there are no request lines from memories but still we can program
them with burst in order to faster the transfer. This burst feature is
automatically handled by DMA.

> + *
> + * ASSUMES default (little) endianness for DMA transfers
> + *
> + * Only DMAC flow control is implemented
> + *
> + * Global TODO:
> + * - Break out common code from arch/arm/mach-s3c64xx and share
> + */
> +#include <linux/device.h>
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/pci.h>
> +#include <linux/interrupt.h>
> +#include <linux/slab.h>
> +#include <linux/dmapool.h>
> +#include <linux/amba/bus.h>
> +#include <linux/dmaengine.h>
> +#include <linux/amba/pl08x.h>
> +#include <linux/amba/dma.h>
> +
> +#include <asm/hardware/pl080.h>
> +#include <asm/dma.h>
> +#include <asm/mach/dma.h>
> +#include <asm/atomic.h>
> +#include <asm/processor.h>
> +#include <asm/cacheflush.h>
> +
> +#define DRIVER_NAME	"pl08xdmac"
> +
> +/**
> + * struct vendor_data - vendor-specific config parameters
> + * for PL08x derivates
> + * @name: the name of this specific variant
> + * @channels: the number of channels available in this variant
> + */
> +struct vendor_data {
> +	char *name;
> +	u8 channels;
> +};
> +
> +/*
> + * PL08X private data structures
> + * An LLI struct - see pl08x TRM
> + * Note that next uses bit[0] as a bus bit,
> + * start & end do not - their bus bit info
> + * is in cctl
> + */
> +struct lli {
> +	dma_addr_t src;
> +	dma_addr_t dst;
> +	dma_addr_t next;
> +	u32 cctl;
> +};
> +
> +/**
> + * struct pl08x_driver_data - the local state holder for the PL08x
> + * @base: virtual memory base (remapped) for the PL08x
> + * @adev: the corresponding AMBA (PrimeCell) bus entry
> + * @vd: vendor data for this PL08x variant
> + * @pd: platform data passed in from the platform/machine
> + * @phy_chans: array of data for the physical channels
> + * @pool: a pool for the LLI descriptors
> + * @pool_ctr: counter of LLIs in the pool
> + * @max_num_llis: maximum number of LLIs, i.e. longest linked transfer
> + * length, submitted so far

What is the significance of this field? What it is used for?

> + * @lock: a spinlock for this struct
> + */
> +struct pl08x_driver_data {
> +	void __iomem *base;
> +	struct amba_device *adev;
> +	struct vendor_data *vd;
> +	struct pl08x_platform_data *pd;
> +	struct pl08x_phy_chan *phy_chans;
> +	struct dma_pool *pool;
> +	int pool_ctr;
> +	int max_num_llis;
> +	spinlock_t lock;
> +};
> +
> +#ifdef MODULE
> +
> +# error "AMBA PL08X DMA CANNOT BE COMPILED AS A LOADABLE MODULE AT PRESENT"
> +
> +/*
> +	a) Some devices might make use of DMA during boot
> +	   (esp true for DMAENGINE implementation)
> +	b) Memory allocation will need much more attention
> +	   before load/unload can be supported
> + */
> +#endif
> +
> +/*
> + * PL08X specific defines
> + */
> +
> +/*
> + * Memory boundaries: the manual for PL08x says that the controller
> + * cannot read past a 1KiB boundary, so these defines are used to
> + * create transfer LLIs that do not cross such boundaries.
> + */
> +#define PL08X_BOUNDARY_SHIFT		(10)	/* 1KB 0x400 */
> +#define PL08X_BOUNDARY_SIZE		(1 << PL08X_BOUNDARY_SHIFT)
> +
> +/* Minimum period between work queue runs */
> +#define PL08X_WQ_PERIODMIN	20
> +
> +/* Size (bytes) of each LLI buffer allocated for one transfer */
> +# define PL08X_LLI_TSFR_SIZE	0x2000
> +
> +/* Maximimum times we call dma_pool_alloc on this pool without freeing */
> +#define PL08X_MAX_ALLOCS	0x40
> +#define MAX_NUM_TSFR_LLIS	(PL08X_LLI_TSFR_SIZE/sizeof(struct lli))
> +#define PL08X_ALIGN		8
> +
> +static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
> +{
> +	return container_of(chan, struct pl08x_dma_chan, chan);
> +}
> +
> +/*
> + * Physical channel handling
> + */
> +
> +/* Whether a certain channel is busy or not */
> +static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
> +{
> +	unsigned int val;
> +
> +	val = readl(ch->base + PL080_CH_CONFIG);
> +	return val & PL080_CONFIG_ACTIVE;
> +}
> +
> +/*
> + * Set the initial DMA register values i.e. those for the first LLI
> + * The next lli pointer and the configuration interrupt bit have
> + * been set when the LLIs were constructed
> + */
> +static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
> +			    struct pl08x_phy_chan *ch)
> +{
> +	u32 val;
> +
> +	/* Wait for channel inactive */
> +	val = readl(ch->base + PL080_CH_CONFIG);
> +	while (val & PL080_CONFIG_ACTIVE)
> +		val = readl(ch->base + PL080_CH_CONFIG);

can we use pl08x_phy_channel_busy() instead of above code?

> +
> +	dev_vdbg(&pl08x->adev->dev,
> +		"WRITE channel %d: csrc=%08x, cdst=%08x, "
> +		 "cctl=%08x, clli=%08x, ccfg=%08x\n",
> +		ch->id,
> +		ch->csrc,
> +		ch->cdst,
> +		ch->cctl,
> +		ch->clli,
> +		ch->ccfg);
> +
> +	writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR);
> +	writel(ch->cdst, ch->base + PL080_CH_DST_ADDR);
> +	writel(ch->clli, ch->base + PL080_CH_LLI);
> +	writel(ch->cctl, ch->base + PL080_CH_CONTROL);
> +	writel(ch->ccfg, ch->base + PL080_CH_CONFIG);
> +	mb();
> +}
> +
> +static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan)
> +{
> +	struct pl08x_channel_data *cd = plchan->cd;
> +	struct pl08x_phy_chan *phychan = plchan->phychan;
> +	struct pl08x_txd *txd = plchan->at;
> +
> +	/* Copy the basic control register calculated at transfer config */
> +	phychan->csrc = txd->csrc;
> +	phychan->cdst = txd->cdst;
> +	phychan->clli = txd->clli;
> +	phychan->cctl = txd->cctl;
> +
> +	/* Assign the signal to the proper control registers */
> +	phychan->ccfg = cd->ccfg;
> +	phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
> +	phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
> +	/* If it wasn't set from AMBA, ignore it */
> +	if (txd->direction == DMA_TO_DEVICE)
> +		/* Select signal as destination */
> +		phychan->ccfg |=
> +			(phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
> +	else if (txd->direction == DMA_FROM_DEVICE)
> +		/* Select signal as source */
> +		phychan->ccfg |=
> +			(phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
> +	/* Always enable error interrupts */
> +	phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
> +	/* Always enable terminal interrupts */
> +	phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
> +}
> +
> +/*
> + * Enable the DMA channel
> + * Assumes all other configuration bits have been set
> + * as desired before this code is called
> + */
> +static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x,
> +				  struct pl08x_phy_chan *ch)
> +{
> +	u32 val;
> +
> +	/*
> +	 * Do not access config register until channel shows as disabled
> +	 */
> +	while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id))
> +		;
> +
> +	/*
> +	 * Do not access config register until channel shows as inactive
> +	 */
> +	val = readl(ch->base + PL080_CH_CONFIG);
> +	while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
> +		val = readl(ch->base + PL080_CH_CONFIG);

above 3 fns are always called in order, i.e. pl08x_enable_phy_chan will
be called after pl08x_set_cregs, so we may not require these checks
here. Is my understanding correct??

> +
> +	writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG);
> +	mb();
> +}
> +
> +/*
> + * Overall DMAC remains enabled always.
> + *
> + * Disabling individual channels could lose data.
> + *
> + * Disable the peripheral DMA after disabling the DMAC
> + * in order to allow the DMAC FIFO to drain, and
> + * hence allow the channel to show inactive
> + *
> + */
> +static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
> +{
> +	u32 val;
> +
> +	/* Set the HALT bit and wait for the FIFO to drain */
> +	val = readl(ch->base + PL080_CH_CONFIG);
> +	val |= PL080_CONFIG_HALT;
> +	writel(val, ch->base + PL080_CH_CONFIG);
> +
> +	/* Wait for channel inactive */
> +	val = readl(ch->base + PL080_CH_CONFIG);
> +	while (val & PL080_CONFIG_ACTIVE)
> +		val = readl(ch->base + PL080_CH_CONFIG);

can we use pl08x_phy_channel_busy() instead of above code?
Please check everywhere.

> +
> +	mb();
> +
> +	return;

return not required!!

> +}
> +
> +static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)

can these small fns be made inline???

> +{
> +	u32 val;
> +
> +	/* Clear the HALT bit */
> +	val = readl(ch->base + PL080_CH_CONFIG);
> +	val &= ~PL080_CONFIG_HALT;
> +	writel(val, ch->base + PL080_CH_CONFIG);
> +	mb();
> +
> +	return;
> +}
> +
> +
> +/* Stops the channel */
> +static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
> +{
> +	u32 val;
> +
> +	pl08x_pause_phy_chan(ch);
> +
> +	/* Disable channel */
> +	val = readl(ch->base + PL080_CH_CONFIG);
> +	val &= ~PL080_CONFIG_ENABLE;
> +	writel(val, ch->base + PL080_CH_CONFIG);
> +	mb();
> +
> +	return;

same here. return not required.

> +}
> +
> +static inline u32 get_bytes_in_cctl(u32 cctl)
> +{
> +	/* The source width defines the number of bytes */
> +	u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
> +
> +	switch ((cctl >> 18) & 3) {

better to use Macros instead of magic numbers here!!!

> +	case PL080_WIDTH_8BIT:
> +		break;
> +	case PL080_WIDTH_16BIT:
> +		bytes *= 2;
> +		break;
> +	case PL080_WIDTH_32BIT:
> +		bytes *= 4;
> +		break;
> +	}
> +	return bytes;
> +}
> +
> +static u32 pl08x_getbytes_phy_chan(struct pl08x_phy_chan *ch)
> +{
> +	u32 bytes;
> +
> +	/* FIXME: follow all queued transactions */
> +	bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
> +	/* TODO: follow the LLI to see the sum summarum */
> +	return bytes;
> +}
> +
> +/*
> + * Allocate a physical channel for a virtual channel
> + */
> +static struct pl08x_phy_chan *
> +pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
> +		      struct pl08x_dma_chan *virt_chan)
> +{
> +	struct pl08x_phy_chan *ch = NULL;
> +	unsigned long flags;
> +	int i;
> +
> +	/*
> +	 * Try to locate a physical channel to be used for
> +	 * this transfer. If all are taken return NULL and
> +	 * the requester will have to cope by using some fallback
> +	 * PIO mode or retrying later.
> +	 */
> +	for (i = 0; i < pl08x->vd->channels; i++) {
> +		ch = &pl08x->phy_chans[i];
> +
> +		spin_lock_irqsave(&ch->lock, flags);
> +
> +		if (!ch->serving) {
> +			ch->serving = virt_chan;
> +			ch->signal = -1;
> +			spin_unlock_irqrestore(&ch->lock, flags);
> +			break;
> +		}
> +
> +		spin_unlock_irqrestore(&ch->lock, flags);
> +	}
> +
> +	if (i == pl08x->vd->channels) {
> +		/* No physical channel available, cope with it */
> +		return NULL;
> +	}
> +
> +	return ch;
> +}
> +
> +static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
> +					 struct pl08x_phy_chan *ch)
> +{
> +	unsigned long flags;
> +
> +	/* Stop the channel and clear its interrupts */
> +	pl08x_stop_phy_chan(ch);
> +	writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
> +	writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
> +
> +	/* Mark it as free */
> +	spin_lock_irqsave(&ch->lock, flags);
> +	ch->serving = NULL;
> +	ch->signal = -1;
> +	spin_unlock_irqrestore(&ch->lock, flags);
> +}
> +
> +/*
> + * LLI handling
> + */
> +
> +static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
> +{
> +	switch (coded) {
> +	case PL080_WIDTH_8BIT:
> +		return 1;
> +	case PL080_WIDTH_16BIT:
> +		return 2;
> +	case PL080_WIDTH_32BIT:
> +		return 4;
> +	default:
> +		break;
> +	}
> +	BUG();
> +	return 0;
> +}
> +
> +static inline u32 pl08x_cctl_bits(u32 cctl,
> +				  u8 srcwidth,
> +				  u8 dstwidth,
> +				  u32 tsize)

Not sure, if we should write above function prototype in just 2 lines,
or is it okay to write it the way it is written.

> +{
> +	u32 retbits = cctl;
> +
> +	/* Remove all src, dst and transfersize bits */
> +	retbits &= ~PL080_CONTROL_DWIDTH_MASK;
> +	retbits &= ~PL080_CONTROL_SWIDTH_MASK;
> +	retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
> +
> +	/* Then set the bits according to the parameters */
> +	switch(srcwidth) {
> +	case 1:
> +		retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
> +		break;
> +	case 2:
> +		retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
> +		break;
> +	case 4:
> +		retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
> +		break;
> +	default:
> +		BUG();
> +		break;
> +	}
> +
> +	switch(dstwidth) {
> +	case 1:
> +		retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
> +		break;
> +	case 2:
> +		retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
> +		break;
> +	case 4:
> +		retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
> +		break;
> +	default:
> +		BUG();
> +		break;
> +	}
> +
> +	retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
> +	return retbits;
> +}
> +
> +/*
> + * Autoselect a master bus to use for the transfer
> + * this prefers the destination bus if both available
> + * if fixed address on one bus the other will be chosen
> + */
> +void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
> +	struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
> +	struct pl08x_bus_data **sbus, u32 cctl)
> +{
> +	if (!cctl & PL080_CONTROL_DST_INCR) {
> +		*mbus = src_bus;
> +		*sbus = dst_bus;
> +	} else if (!cctl & PL080_CONTROL_SRC_INCR) {
> +		*mbus = dst_bus;
> +		*sbus = src_bus;
> +	} else {
> +		if (dst_bus->buswidth == 4) {
> +			*mbus = dst_bus;
> +			*sbus = src_bus;
> +		} else if (src_bus->buswidth == 4) {
> +			*mbus = src_bus;
> +			*sbus = dst_bus;
> +		} else if (dst_bus->buswidth == 2) {
> +			*mbus = dst_bus;
> +			*sbus = src_bus;
> +		} else if (src_bus->buswidth == 2) {
> +			*mbus = src_bus;
> +			*sbus = dst_bus;
> +		} else {
> +			/* src_bus->buswidth == 1 */
> +			*mbus = dst_bus;
> +			*sbus = src_bus;
> +		}
> +	}
> +}
> +
> +/*
> + * Fills in one LLI for a certain transfer descriptor
> + * and advance the counter
> + */
> +int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
> +			    struct pl08x_txd *txd, int num_llis, int len,
> +			    u32 cctl, u32 *remainder)
> +{
> +	struct lli *llis_va = (struct lli *)(txd->llis_va);
> +	struct lli *llis_bus = (struct lli *)(txd->llis_bus);
> +
> +	BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
> +
> +	llis_va[num_llis].cctl		= cctl;
> +	llis_va[num_llis].src		= txd->srcbus.addr;
> +	llis_va[num_llis].dst		= txd->dstbus.addr;
> +	/*
> +	 * The bus bit is added to the next lli's address
> +	 */
> +	llis_va[num_llis].next =
> +		(dma_addr_t)((u32) &(llis_bus[num_llis + 1])
> +			     | pl08x->pd->bus_bit_lli);
> +
> +	if (cctl & PL080_CONTROL_SRC_INCR)
> +		txd->srcbus.addr += len;
> +	if (cctl & PL080_CONTROL_DST_INCR)
> +		txd->dstbus.addr += len;
> +
> +	*remainder -= len;
> +
> +	return num_llis + 1;
> +}
> +
> +/*
> + * Return number of bytes to fill to boundary, or len
> + */
> +static inline u32 pl08x_pre_boundary(u32 addr, u32 len)
> +{
> +	u32 boundary;
> +
> +	boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
> +		<< PL08X_BOUNDARY_SHIFT;
> +
> +	if (boundary < addr + len)
> +		return boundary - addr;
> +	else
> +		return len;
> +}
> +
> +/*
> + * This fills in the table of LLIs for the transfer descriptor
> + * Note that we assume we never have to change the burst sizes
> + * Return 0 for error
> + */
> +static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
> +			      struct pl08x_txd *txd)
> +{
> +	struct pl08x_channel_data *cd = txd->cd;
> +	struct pl08x_bus_data *mbus, *sbus;
> +	u32 remainder;
> +	int num_llis = 0;
> +	u32 cctl;
> +	int max_bytes_per_lli;
> +	int total_bytes = 0;
> +	struct lli *llis_va;
> +	struct lli *llis_bus;
> +
> +	if (!txd) {
> +		dev_err(&pl08x->adev->dev, "%s no descriptor\n", __func__);
> +		return 0;
> +	}
> +
> +	txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_KERNEL,
> +				      &txd->llis_bus);
> +	if (!txd->llis_va) {
> +		dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
> +		return 0;
> +	}
> +
> +	pl08x->pool_ctr++;
> +
> +	/*
> +	 * Initialize bus values for this transfer
> +	 * from the passed optimal values
> +	 */
> +	if (!cd) {
> +		dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
> +		return 0;
> +	}
> +
> +	/* Get the default CCTL from the platform data */
> +	cctl = cd->cctl;
> +
> +	/* Find maximum width of the source bus */
> +	txd->srcbus.maxwidth =
> +		pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
> +				       PL080_CONTROL_SWIDTH_SHIFT);
> +
> +	/* Find maximum width of the destination bus */
> +	txd->dstbus.maxwidth =
> +		pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
> +				       PL080_CONTROL_DWIDTH_SHIFT);
> +
> +	/* Set up the bus widths to the maximum */
> +	txd->srcbus.buswidth = txd->srcbus.maxwidth;
> +	txd->dstbus.buswidth = txd->dstbus.maxwidth;
> +	dev_vdbg(&pl08x->adev->dev,
> +		 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
> +		 __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
> +
> +
> +	/*
> +	 * bytes transferred == tsize * MIN(buswidths), not max(buswidths)
> +	 */
> +	max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
> +		PL080_CONTROL_TRANSFER_SIZE_MASK;
> +	dev_vdbg(&pl08x->adev->dev,
> +		 "%s max bytes per lli = %d\n",
> +		 __func__, max_bytes_per_lli);
> +
> +	/* We need to count this down to zero */
> +	remainder = txd->len;
> +	dev_vdbg(&pl08x->adev->dev,
> +		 "%s remainder = %d\n",
> +		 __func__, remainder);
> +
> +	/*
> +	 * Choose bus to align to
> +	 * - prefers destination bus if both available
> +	 * - if fixed address on one bus chooses other
> +	 */
> +	pl08x_choose_master_bus(&txd->srcbus,
> +		&txd->dstbus, &mbus, &sbus, cctl);
> +
> +	if (txd->len < mbus->buswidth) {
> +		/*
> +		 * Less than a bus width available
> +		 * - send as single bytes
> +		 */
> +		while (remainder) {
> +			dev_vdbg(&pl08x->adev->dev,
> +				 "%s single byte LLIs for a transfer of less than a bus width (remain %08x)\n",
> +				 __func__, remainder);
> +			cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
> +			num_llis =
> +				pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
> +					cctl, &remainder);
> +			total_bytes++;
> +		}
> +	} else {
> +		/*
> +		 *  Make one byte LLIs until master bus is aligned
> +		 *  - slave will then be aligned also
> +		 */
> +		while ((mbus->addr) % (mbus->buswidth)) {
> +			dev_vdbg(&pl08x->adev->dev,
> +				"%s adjustment lli for less than bus width (remain %08x)\n",
> +				 __func__, remainder);
> +			cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
> +			num_llis = pl08x_fill_lli_for_desc
> +				(pl08x, txd, num_llis, 1, cctl, &remainder);
> +			total_bytes++;
> +		}
> +
> +		/*
> +		 *  Master now aligned
> +		 * - if slave is not then we must set its width down
> +		 */
> +		if (sbus->addr % sbus->buswidth) {
> +			dev_dbg(&pl08x->adev->dev,
> +				"%s set down bus width to one byte\n",
> +				 __func__);
> +
> +			sbus->buswidth = 1;
> +		}
> +
> +		/*
> +		 * Make largest possible LLIs until less than one bus width left
> +		 */
> +		while (remainder > (mbus->buswidth - 1)) {
> +			int lli_len, target_len;
> +			int tsize;
> +			int odd_bytes;
> +
> +			/*
> +			 * If enough left try to send max possible,
> +			 * otherwise try to send the remainder
> +			 */
> +			target_len = remainder;
> +			if (remainder > max_bytes_per_lli)
> +				target_len = max_bytes_per_lli;
> +
> +			/*
> +			 * Set bus lengths for incrementing busses
> +			 * to number of bytes which fill to next memory
> +			 * boundary
> +			 */
> +			if (cctl & PL080_CONTROL_SRC_INCR)
> +				txd->srcbus.fill_bytes =
> +					pl08x_pre_boundary(
> +						txd->srcbus.addr,
> +						remainder);
> +			else
> +				txd->srcbus.fill_bytes =
> +					max_bytes_per_lli;
> +
> +			if (cctl & PL080_CONTROL_DST_INCR)
> +				txd->dstbus.fill_bytes =
> +					pl08x_pre_boundary(
> +						txd->dstbus.addr,
> +						remainder);
> +			else
> +				txd->dstbus.fill_bytes =
> +						max_bytes_per_lli;
> +
> +			/*
> +			 *  Find the nearest
> +			 */
> +			lli_len	= min(txd->srcbus.fill_bytes,
> +				txd->dstbus.fill_bytes);
> +
> +			BUG_ON(lli_len > remainder);
> +
> +			if (lli_len <= 0) {
> +				dev_err(&pl08x->adev->dev,
> +					"%s lli_len is %d, <= 0\n",
> +						__func__, lli_len);
> +				return 0;
> +			}
> +
> +			if (lli_len == target_len) {
> +				/*
> +				 * Can send what we wanted
> +				 */
> +				/*
> +				 *  Maintain alignment
> +				 */
> +				lli_len	= (lli_len/mbus->buswidth) *
> +							mbus->buswidth;
> +				odd_bytes = 0;
> +			} else {
> +				/*
> +				 * So now we know how many bytes to transfer
> +				 * to get to the nearest boundary
> +				 * The next lli will past the boundary
> +				 * - however we may be working to a boundary
> +				 *   on the slave bus
> +				 *   We need to ensure the master stays aligned
> +				 */
> +				odd_bytes = lli_len % mbus->buswidth;
> +				/*
> +				 * - and that we are working in multiples
> +				 *   of the bus widths
> +				 */
> +				lli_len -= odd_bytes;
> +
> +			}
> +
> +			if (lli_len) {
> +				/*
> +				 * Check against minimum bus alignment:
> +				 * Calculate actual transfer size in relation to bus
> +				 * width an get a maximum remainder of the smallest
> +				 * bus width - 1
> +				 */
> +				/* FIXME: use round_down()? */
> +				tsize = lli_len / min(mbus->buswidth, sbus->buswidth);
> +				lli_len	= tsize * min(mbus->buswidth, sbus->buswidth);
> +
> +				if (target_len != lli_len) {
> +					dev_vdbg(&pl08x->adev->dev,
> +					"%s can't send what we want. Desired %08x, lli of %08x bytes in txd of %08x\n",
> +					__func__, target_len, lli_len, txd->len);
> +				}
> +
> +				cctl = pl08x_cctl_bits(cctl,
> +						       txd->srcbus.buswidth,
> +						       txd->dstbus.buswidth,
> +						       tsize);
> +
> +				dev_vdbg(&pl08x->adev->dev,
> +					"%s fill lli with single lli chunk of size %08x (remainder %08x)\n",
> +					__func__, lli_len, remainder);
> +				num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
> +						num_llis, lli_len, cctl,
> +						&remainder);
> +				total_bytes += lli_len;
> +			}
> +
> +
> +			if (odd_bytes) {
> +				/*
> +				 * Creep past the boundary,
> +				 * maintaining master alignment
> +				 */
> +				int j;
> +				for (j = 0; (j < mbus->buswidth)
> +						&& (remainder); j++) {
> +					cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
> +					dev_vdbg(&pl08x->adev->dev,
> +						"%s align with boundardy, single byte (remain %08x)\n",
> +						__func__, remainder);
> +					num_llis =
> +						pl08x_fill_lli_for_desc(pl08x,
> +							txd, num_llis, 1,
> +							cctl, &remainder);
> +					total_bytes++;
> +				}
> +			}
> +		}
> +
> +		/*
> +		 * Send any odd bytes
> +		 */
> +		if (remainder < 0) {
> +			dev_err(&pl08x->adev->dev, "%s remainder not fitted 0x%08x bytes\n",
> +					__func__, remainder);
> +			return 0;
> +		}
> +
> +		while (remainder) {
> +			cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
> +			dev_vdbg(&pl08x->adev->dev,
> +				"%s align with boundardy, single odd byte (remain %d)\n",
> +				__func__, remainder);
> +			num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
> +					1, cctl, &remainder);
> +			total_bytes++;
> +		}
> +	}
> +	if (total_bytes != txd->len) {
> +		dev_err(&pl08x->adev->dev,
> +			"%s size of encoded lli:s don't match total txd, transferred 0x%08x from size 0x%08x\n",
> +			__func__, total_bytes, txd->len);
> +		return 0;
> +	}
> +
> +	if (num_llis >= MAX_NUM_TSFR_LLIS) {
> +		dev_err(&pl08x->adev->dev,
> +			"%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
> +			__func__, (u32) MAX_NUM_TSFR_LLIS);
> +		return 0;
> +	}
> +	/*
> +	 * Decide whether this is a loop or a terminated transfer
> +	 */
> +	llis_va = ((struct lli *)txd->llis_va);
> +	llis_bus = ((struct lli *)txd->llis_bus);
> +
> +	if (cd->circular_buffer) {
> +		/*
> +		 * Loop the circular buffer so that the next element
> +		 * points back to the beginning of the LLI.
> +		 */
> +		llis_va[num_llis - 1].next =
> +			(dma_addr_t)((unsigned int)&(llis_bus[0]) +
> +						pl08x->pd->bus_bit_lli);
> +	} else {
> +		/*
> +		 * On non-circular buffers, the final LLI terminates
> +		 * the LLI.
> +		 */
> +		llis_va[num_llis - 1].next = 0;
> +		/*
> +		 * The final LLI element shall also fire an interrupt
> +		 */
> +		llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
> +	}
> +
> +	/* Now store the channel register values */
> +	txd->csrc = llis_va[0].src;
> +	txd->cdst = llis_va[0].dst;
> +	if (num_llis > 1)
> +		txd->clli = llis_va[0].next;
> +	else
> +		txd->clli = 0;
> +
> +	txd->cctl = llis_va[0].cctl;
> +	/* ccfg will be set at physical channel allocation time */
> +
> +	{
> +		int i;
> +
> +		for (i = 0; i < num_llis; i++) {
> +				dev_vdbg(&pl08x->adev->dev,
> +					"lli %d @%p: csrc=%08x, cdst=%08x, cctl=%08x, clli=%08x\n",
> +					i,
> +					&llis_va[i],
> +					llis_va[i].src,
> +					llis_va[i].dst,
> +					llis_va[i].cctl,
> +					llis_va[i].next
> +					);
> +		}
> +	}
> +
> +	/*
> +	 * Reflects the longest lli submitted so far
> +	 * TODO: Change to use /proc data
> +	 */
> +	if (pl08x->max_num_llis < num_llis)
> +		pl08x->max_num_llis = num_llis;
> +
> +	return num_llis;
> +}
> +
> +/* You should call this with the struct pl08x lock held */
> +static void pl08x_free_txd(struct pl08x_driver_data *pl08x, struct pl08x_txd *txd)
> +{
> +	if (!txd)
> +		dev_err(&pl08x->adev->dev,
> +			"%s no descriptor to free\n",
> +			__func__);
> +
> +	/* Free the LLI */
> +	dma_pool_free(pl08x->pool, txd->llis_va,
> +		      txd->llis_bus);
> +
> +	pl08x->pool_ctr--;
> +
> +	kfree(txd);
> +}
> +
> +static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x, struct list_head *txdlist)
> +{
> +	struct pl08x_txd *txdi = NULL;
> +	struct pl08x_txd *next;
> +
> +	if (!list_empty(txdlist)) {
> +		list_for_each_entry_safe(txdi,
> +					 next, txdlist, node) {
> +			list_del(&txdi->node);
> +			pl08x_free_txd(pl08x, txdi);
> +		}
> +
> +	}
> +}
> +
> +static void pl08x_tasklet(unsigned long data)
> +{
> +	struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
> +	struct pl08x_phy_chan *phychan = plchan->phychan;
> +	struct pl08x_driver_data *pl08x = plchan->host;
> +	struct pl08x_txd *txdi = NULL;
> +	struct pl08x_txd *next;
> +	unsigned long flags;
> +
> +	if (!plchan)
> +		BUG();
> +
> +	spin_lock_irqsave(&plchan->lock, flags);
> +
> +	if (plchan->at) {
> +		dma_async_tx_callback callback =
> +			plchan->at->tx.callback;
> +		void *callback_param =
> +			plchan->at->tx.callback_param;
> +
> +		/*
> +		 * Update last completed
> +		 */
> +		plchan->lc =
> +			(plchan->at->tx.cookie);
> +
> +		/*
> +		 * Callback peripheral driver for p/m
> +		 * to signal completion
> +		 */
> +		if (callback)
> +			callback(callback_param);
> +
> +		/*
> +		 * Device callbacks should NOT clear
> +		 * the current transaction on the channel
> +		 * Linus: sometimes they should?
> +		 */
> +		if (!plchan->at)
> +			BUG();
> +
> +		/*
> +		 * Free the descriptor if it's not for a device
> +		 * using a circular buffer
> +		 */
> +		if (!plchan->at->cd->circular_buffer) {
> +			pl08x_free_txd(pl08x, plchan->at);
> +			plchan->at = NULL;
> +		}
> +		/*
> +		 * else descriptor for circular
> +		 * buffers only freed when
> +		 * client has disabled dma
> +		 */
> +	}
> +	/*
> +	 * If a new descriptor is queued, set it up
> +	 */
> +	if (!list_empty(&plchan->desc_list)) {
> +		list_for_each_entry_safe(txdi,
> +					 next, &plchan->desc_list, node) {
> +			list_del_init(&txdi->node);
> +		}
> +	} else {
> +		/*
> +		 * No more jobs, so free up the physical channel
> +		 * Free any allocated signal on slave transfers too
> +		 */
> +		if ((phychan->signal >= 0) && pl08x->pd->put_signal)
> +			pl08x->pd->put_signal(plchan);
> +		pl08x_put_phy_channel(pl08x, phychan);
> +		plchan->phychan = NULL;
> +	}
> +
> +	spin_unlock_irqrestore(&plchan->lock, flags);
> +}
> +
> +static irqreturn_t pl08x_irq(int irq, void *dev)
> +{
> +	struct pl08x_driver_data *pl08x = dev;
> +	u32 mask = 0;
> +	u32 val;
> +	int i;
> +
> +	val = readl(pl08x->base + PL080_ERR_STATUS);
> +	mb();
> +	if (val) {
> +		/*
> +		 * An error interrupt (on one or more channels)
> +		 */
> +		dev_err(&pl08x->adev->dev,
> +			"%s error interrupt, register value 0x%08x\n",
> +				__func__, val);
> +		/*
> +		 * Simply clear ALL PL08X error interrupts,
> +		 * regardless of channel and cause
> +		 * FIXME: should be 0x00000003 on PL081 really.
> +		 */
> +		writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
> +	}
> +	val = readl(pl08x->base + PL080_INT_STATUS);
> +	mb();
> +	for (i = 0; i < pl08x->vd->channels; i++) {
> +		if ((1 << i) & val) {
> +			/* Locate physical channel */
> +			struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
> +			struct pl08x_dma_chan *plchan = phychan->serving;
> +
> +			/* Schedule tasklet on this channel */
> +			tasklet_schedule(&plchan->tasklet);
> +
> +			mask |= (1 << i);
> +		}
> +	}
> +	/*
> +	 * Clear only the terminal interrupts on channels we processed
> +	 */
> +	writel(mask, pl08x->base + PL080_TC_CLEAR);
> +	mb();
> +
> +	return mask ? IRQ_HANDLED : IRQ_NONE;
> +}
> +
> +
> +/*
> + * The DMA ENGINE API
> + */
> +static int pl08x_alloc_chan_resources(struct dma_chan *chan)
> +{
> +	return 0;
> +}
> +
> +static void pl08x_free_chan_resources(struct dma_chan *chan)
> +{
> +}
> +
> +/*
> + * This should be called with the channel plchan->lock held
> + */
> +static int prep_phy_channel(struct pl08x_dma_chan *plchan,
> +			    struct pl08x_txd *txd)
> +{
> +	struct pl08x_driver_data *pl08x = plchan->host;
> +	struct pl08x_phy_chan *ch;
> +	int ret;
> +
> +	/* Check if we already have a channel */
> +	if (plchan->phychan)
> +		return 0;
> +
> +	ch = pl08x_get_phy_channel(pl08x, plchan);
> +	if (!ch) {
> +		/* No physical channel available, cope with it */
> +		dev_info(&pl08x->adev->dev, "no physical channel "
> +			"available for xfer on %s\n", plchan->name);
> +		return -EBUSY;
> +	}
> +
> +	/*
> +	 * OK we have a physical channel: for memcpy() this is all we
> +	 * need, but for slaves the physical siglals may be muxed!
> +	 * Can the platform allow us to use this channel?
> +	 */
> +	if ((txd->direction == DMA_FROM_DEVICE || txd->direction == DMA_TO_DEVICE) &&
> +	    pl08x->pd->get_signal) {
> +		ret = pl08x->pd->get_signal(plchan);
> +		if (ret < 0) {
> +			dev_info(&pl08x->adev->dev,
> +				"unable to use physical channel "
> +				"%d for transfer on %s due to "
> +				"platform restrictions\n",
> +				ch->id, plchan->name);
> +			/* Release physical channel & return */
> +			pl08x_put_phy_channel(pl08x, ch);
> +			return -EBUSY;
> +		}
> +		ch->signal = ret;
> +	}
> +
> +	dev_dbg(&pl08x->adev->dev, "allocated physical "
> +		 "channel %d and signal %d for xfer on %s\n",
> +		 ch->id,
> +		 ch->signal,
> +		 plchan->name);
> +
> +	plchan->phychan = ch;
> +
> +	return 0;
> +}
> +
> +/*
> + * First make the LLIs (could/should we do this earlier??)
> + * slave (m/p) - no queued transactions allowed at present
> + *	TODO allow queued transactions for non circular buffers
> + * Set up the channel active txd as inactive
> + * m2m	- transactions may be queued
> + * If no active txd on channel
> + *	set it up as inactive
> + *	- issue_pending() will set active & start
> + * else
> + *	queue it
> + * Lock channel since there may be (at least for m2m) multiple calls
> + *
> + * Return < 0 for error
> + */
> +
> +static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
> +{
> +	int num_llis;
> +	unsigned long flags;
> +	struct pl08x_txd *txd = container_of(tx, struct pl08x_txd, tx);
> +	struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
> +	struct pl08x_driver_data *pl08x = plchan->host;
> +	int ret;
> +
> +	num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
> +
> +	if (num_llis) {
> +		spin_lock_irqsave(&plchan->lock, flags);
> +		atomic_inc(&plchan->last_issued);
> +		tx->cookie = atomic_read(&plchan->last_issued);
> +
> +		if (plchan->at) {
> +
> +			/*
> +			 * If this device not using a circular buffer then
> +			 * queue this new descriptor for transfer.
> +			 * The descriptor for a circular buffer continues
> +			 * to be used until the channel is freed.
> +			 */
> +			if (txd->cd->circular_buffer)
> +				dev_err(&pl08x->adev->dev,
> +					"%s attempting to queue a circular buffer\n",
> +						__func__);
> +			else
> +				list_add_tail(&txd->node,
> +					&plchan->desc_list);
> +
> +		} else {
> +			plchan->at = txd;
> +			txd->active = false;
> +		}
> +
> +		/*
> +		 * See if we already have a physical channel allocated,
> +		 * else this is the time to try to get one.
> +		 */
> +		ret = prep_phy_channel(plchan, txd);
> +		if (ret) {
> +			/* No physical channel available, cope with it */
> +			spin_unlock_irqrestore(&plchan->lock, flags);
> +			return -EBUSY;
> +		}
> +
> +		spin_unlock_irqrestore(&plchan->lock, flags);
> +
> +		return tx->cookie;
> +	} else
> +		return -EINVAL;
> +}
> +
> +static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
> +		struct dma_chan *chan, unsigned long flags)
> +{
> +	struct dma_async_tx_descriptor *retval = NULL;
> +
> +	return retval;
> +}
> +
> +/*
> + * Code accessing dma_async_is_complete() in a tight loop
> + * may give problems - could schedule where indicated.
> + * If slaves are relying on interrupts to signal completion this
> + * function must not be called with interrupts disabled
> + */
> +static enum dma_status
> +pl08x_dma_tx_status(struct dma_chan *chan,
> +		    dma_cookie_t cookie,
> +		    struct dma_tx_state *txstate)
> +{
> +	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
> +	dma_cookie_t last_used;
> +	dma_cookie_t last_complete;
> +	enum dma_status ret;
> +	u32 bytesleft = 0;
> +
> +	last_used = atomic_read(&plchan->last_issued);
> +	last_complete = plchan->lc;
> +
> +	ret = dma_async_is_complete(cookie, last_complete, last_used);
> +	if (ret == DMA_SUCCESS) {
> +		dma_set_tx_state(txstate, last_complete, last_used, 0);
> +		return ret;
> +	}
> +
> +	/*
> +	 * schedule(); could be inserted here
> +	 */
> +
> +	/*
> +	 * This cookie not complete yet
> +	 */
> +	last_used = atomic_read(&plchan->last_issued);
> +	last_complete = plchan->lc;
> +
> +	/* Get number of bytes left in the active transaction */
> +	if (plchan->phychan)
> +		bytesleft = pl08x_getbytes_phy_chan(plchan->phychan);
> +
> +	dma_set_tx_state(txstate, last_complete, last_used,
> +			 bytesleft);
> +
> +	return DMA_IN_PROGRESS;
> +	/* FIXME: make possible to return DMA_IN_PROGRESS */
> +}
> +
> +/* PrimeCell DMA extension */
> +struct burst_table {
> +	int burstwords;
> +	u32 reg;
> +};
> +
> +static const struct burst_table burst_sizes[] = {
> +	{
> +		.burstwords = 256,
> +		.reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
> +			(PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
> +	},
> +	{
> +		.burstwords = 128,
> +		.reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
> +			(PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
> +	},
> +	{
> +		.burstwords = 64,
> +		.reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
> +			(PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
> +	},
> +	{
> +		.burstwords = 32,
> +		.reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
> +			(PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
> +	},
> +	{
> +		.burstwords = 16,
> +		.reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
> +			(PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
> +	},
> +	{
> +		.burstwords = 8,
> +		.reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
> +			(PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
> +	},
> +	{
> +		.burstwords = 4,
> +		.reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
> +			(PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
> +	},
> +	{
> +		.burstwords = 1,
> +		.reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
> +			(PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
> +	},
> +};
> +
> +static void dma_set_ambaconfig(struct dma_chan *chan,
> +			       struct amba_dma_channel_config *config)
> +{
> +	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
> +	struct pl08x_driver_data *pl08x = plchan->host;
> +	struct pl08x_channel_data *cd = plchan->cd;
> +	int maxburst = config->maxburst;
> +	u32 cctl = 0;
> +	/* Mask out all except src and dst channel */
> +	u32 ccfg = cd->ccfg & 0x000003DEU;
> +	int i = 0;
> +
> +	plchan->amba_addr = config->addr;
> +	plchan->amba_direction = config->direction;
> +
> +	switch (config->addr_width) {
> +	case 1:
> +		cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
> +			(PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
> +		break;
> +	case 2:
> +		cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
> +			(PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
> +		break;
> +	case 4:
> +		cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
> +			(PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
> +		break;
> +	default:
> +		dev_err(&pl08x->adev->dev,
> +			"bad ambaconfig: alien address width\n");
> +		return;
> +	}
> +
> +	/* Now decide on a maxburst */
> +	while (i < ARRAY_SIZE(burst_sizes)) {
> +		if (burst_sizes[i].burstwords <= maxburst)
> +			break;
> +		i++;
> +	}
> +	cctl |= burst_sizes[i].reg;
> +
> +	/* Transfer direction */
> +	if (config->direction == DMA_TO_DEVICE) {
> +		cctl |= PL080_CONTROL_SRC_INCR;
> +		ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
> +	} else if (config->direction == DMA_FROM_DEVICE) {
> +		cctl |= PL080_CONTROL_DST_INCR;
> +		ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
> +	} else {
> +		dev_err(&pl08x->adev->dev,
> +			"bad ambaconfig: alien transfer direction\n");
> +	}
> +
> +	/* Access the cell in privileged mode, non-bufferable, non-cacheable */
> +	cctl &= ~PL080_CONTROL_PROT_MASK;
> +	cctl |= PL080_CONTROL_PROT_SYS;
> +
> +	/* Modify the default channel data to fit PrimeCell request */
> +	cd->cctl = cctl;
> +	cd->ccfg = ccfg;
> +
> +	dev_info(&pl08x->adev->dev,
> +		 "configured channel %s (%s) for %s, data width %d, "
> +		 "maxburst %d words, LE, CCTL=%08x, CCFG=%08x\n",
> +		 dma_chan_name(chan), plchan->name,
> +		 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
> +		 config->addr_width,
> +		 config->maxburst,
> +		 cctl, ccfg);
> +}
> +
> +/*
> + * Slave transactions callback to the slave device to allow
> + * synchronization of slave DMA signals with the DMAC enable
> + */
> +static void pl08x_issue_pending(struct dma_chan *chan)
> +{
> +	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
> +	struct pl08x_driver_data *pl08x = plchan->host;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&plchan->lock, flags);
> +	if (plchan->at) {
> +		if (!plchan->at->active) {
> +			/* Configure the physical channel for the active txd */
> +			pl08x_config_phychan_for_txd(plchan);
> +			pl08x_set_cregs(pl08x, plchan->phychan);
> +			pl08x_enable_phy_chan(pl08x, plchan->phychan);
> +			plchan->at->active = true;
> +		}
> +		/*
> +		 * else skip active transfer
> +		 * Calls with active txd occur for NET_DMA
> +		 * - there can be queued descriptors
> +		 */
> +	}
> +	spin_unlock_irqrestore(&plchan->lock, flags);
> +	/*
> +	 * else - calls with no active descriptor occur for NET_DMA
> +	 */
> +}
> +
> +/*
> + * Initialize a descriptor to be used by memcpy submit
> + */
> +static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
> +		struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
> +		size_t len, unsigned long flags)
> +{
> +	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
> +	struct pl08x_driver_data *pl08x = plchan->host;
> +	struct pl08x_txd *txd;
> +
> +	txd = kzalloc(sizeof(struct pl08x_txd), GFP_KERNEL);
> +	if (!txd) {
> +		dev_err(&pl08x->adev->dev,
> +			"%s no memory for descriptor\n", __func__);
> +		return NULL;
> +	}
> +
> +	dma_async_tx_descriptor_init(&txd->tx, chan);
> +	txd->direction = DMA_NONE;
> +	txd->srcbus.addr = src;
> +	txd->dstbus.addr = dest;
> +
> +	/* Set platform data for m2m */
> +	txd->cd = &pl08x->pd->memcpy_channel;
> +	/* Both to be incremented or the code will break */
> +	txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
> +	txd->tx.tx_submit = pl08x_tx_submit;
> +	txd->tx.callback = NULL;
> +	txd->tx.callback_param = NULL;
> +	txd->len = len;
> +
> +	INIT_LIST_HEAD(&txd->node);
> +
> +	return &txd->tx;
> +}
> +
> +struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
> +		struct dma_chan *chan, struct scatterlist *sgl,
> +		unsigned int sg_len, enum dma_data_direction direction,
> +		unsigned long flags)
> +{
> +	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
> +	struct pl08x_driver_data *pl08x = plchan->host;
> +	struct pl08x_txd *txd;
> +
> +	/*
> +	 * Current implementation ASSUMES only one sg
> +	 */
> +	if (sg_len != 1) {
> +		dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
> +			__func__);
> +		BUG();
> +	}
> +
> +	dev_info(&pl08x->adev->dev, "%s prepare transaction from %s\n",
> +		 __func__, plchan->name);
> +
> +	txd = kmalloc(sizeof(struct pl08x_txd), GFP_KERNEL);
> +	if (!txd) {
> +		dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
> +		return NULL;
> +	}
> +
> +	dma_async_tx_descriptor_init(&txd->tx, chan);
> +
> +	if (direction != plchan->amba_direction)
> +		dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
> +			"the direction configured for the PrimeCell\n",
> +			__func__);
> +
> +	txd->direction = direction;
> +	if (direction == DMA_TO_DEVICE) {
> +		txd->srcbus.addr	= sgl->dma_address;
> +		txd->dstbus.addr	= plchan->amba_addr;
> +	} else if (direction == DMA_FROM_DEVICE) {
> +		txd->srcbus.addr	= plchan->amba_addr;
> +		txd->dstbus.addr	= sgl->dma_address;
> +	} else {
> +		dev_err(&pl08x->adev->dev,
> +			"%s direction unsupported\n", __func__);
> +		return NULL;
> +	}
> +	txd->cd = plchan->cd;
> +	txd->tx.tx_submit = pl08x_tx_submit;
> +	txd->tx.callback = NULL;
> +	txd->tx.callback_param = NULL;
> +	txd->len = sgl->length;
> +
> +	INIT_LIST_HEAD(&txd->node);
> +
> +	return &txd->tx;
> +}
> +
> +static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
> +			 unsigned long arg)
> +{
> +	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
> +	struct pl08x_driver_data *pl08x = plchan->host;
> +	unsigned long flags;
> +
> +	/* Controls applicable to inactive channels */
> +	if (cmd == DMA_CONFIG_AMBA) {
> +		dma_set_ambaconfig(chan,
> +				   (struct amba_dma_channel_config *)
> +				   arg);
> +		return 0;
> +	}
> +
> +	/* Anything succeeds on non-existing transfers */
> +	spin_lock_irqsave(&plchan->lock, flags);
> +	if (!plchan->at || !plchan->phychan) {
> +		spin_unlock_irqrestore(&plchan->lock, flags);
> +		return 0;
> +	}
> +
> +	switch (cmd) {
> +	case DMA_TERMINATE_ALL:
> +		pl08x_stop_phy_chan(plchan->phychan);
> +
> +		/* Mark physical channel as free and free any slave signal */
> +		if ((plchan->phychan->signal >= 0) && pl08x->pd->put_signal)
> +			pl08x->pd->put_signal(plchan);
> +		pl08x_put_phy_channel(pl08x, plchan->phychan);
> +		plchan->phychan = NULL;
> +
> +		/* Dequeue jobs and free LLIs */
> +		pl08x_free_txd(pl08x, plchan->at);
> +		pl08x_free_txd_list(pl08x, &plchan->desc_list);
> +
> +		spin_unlock_irqrestore(&plchan->lock, flags);
> +
> +		return 0;
> +	case DMA_PAUSE:
> +		pl08x_pause_phy_chan(plchan->phychan);
> +		spin_unlock_irqrestore(&plchan->lock, flags);
> +		return 0;
> +	case DMA_RESUME:
> +		pl08x_resume_phy_chan(plchan->phychan);
> +		spin_unlock_irqrestore(&plchan->lock, flags);
> +		return 0;
> +	default:
> +		break;
> +	}
> +	spin_unlock_irqrestore(&plchan->lock, flags);
> +
> +	/* Unknown command */
> +	return -ENXIO;
> +}
> +
> +bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
> +{
> +	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
> +	char *name = chan_id;
> +
> +	/* Check that the channel is not taken! */
> +	if (!strcmp(plchan->name, name))
> +		return true;
> +
> +	return false;
> +}
> +
> +struct dma_device dmac_memcpy = {
> +	.device_alloc_chan_resources	= pl08x_alloc_chan_resources,
> +	.device_free_chan_resources	= pl08x_free_chan_resources,
> +	.device_prep_dma_memcpy		= pl08x_prep_dma_memcpy,
> +	.device_prep_dma_xor		= NULL,
> +	.device_prep_dma_memset		= NULL,
> +	.device_prep_dma_interrupt	= pl08x_prep_dma_interrupt,
> +	.device_tx_status		= pl08x_dma_tx_status,
> +	.device_issue_pending		= pl08x_issue_pending,
> +	.device_control			= pl08x_control,
> +	/*
> +	 * Align to 4-byte boundary
> +	 * This makes the DMAtests fail with grace on PB1176
> +	 * broken DMA hardware instead of locking everything
> +	 * up.
> +	 */
> +	/* .copy_align			= 2, */
> +};
> +
> +struct dma_device dmac_slave = {

they must be marked static.

> +	.device_alloc_chan_resources	= pl08x_alloc_chan_resources,
> +	.device_free_chan_resources	= pl08x_free_chan_resources,
> +	.device_prep_dma_xor		= NULL,
> +	.device_prep_dma_memset		= NULL,
> +	.device_prep_dma_interrupt	= pl08x_prep_dma_interrupt,
> +	.device_tx_status		= pl08x_dma_tx_status,
> +	.device_issue_pending		= pl08x_issue_pending,
> +	.device_prep_slave_sg		= pl08x_prep_slave_sg,
> +	.device_control			= pl08x_control,
> +};
> +

One more thing linus, why do we need to create this separation between
channels. i.e. few are for memcpy and few for slave_sg. Why don't all
channels support everything and this is resolved at runtime.

> +
> +/*
> + * Just check that the device is there and active
> + * TODO: turn this bit on/off depending on the number of
> + * physical channels actually used, if it is zero... well
> + * shut it off.
> + */
> +static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
> +{
> +	u32 val;
> +
> +	val = readl(pl08x->base + PL080_CONFIG);
> +	val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
> +	/* We implictly clear bit 1 and that means little-endian mode */
> +	val |= PL080_CONFIG_ENABLE;
> +	mb();
> +	writel(val, pl08x->base + PL080_CONFIG);
> +	mb();
> +}
> +
> +/*
> + * Initialise the DMAC memcpy channels.
> + * Make a local wrapper to hold required data
> + */
> +static int pl08x_dma_init_memcpy_channels(struct pl08x_driver_data *pl08x,
> +						 struct dma_device *memdev)
> +{
> +	struct pl08x_dma_chan *chan;
> +	int i;
> +
> +	INIT_LIST_HEAD(&memdev->channels);
> +	/*
> +	 * Register as many many memcpy as we have physical channels,
> +	 * we won't always be able to use all but the code will have
> +	 * to cope with that situation.
> +	 */
> +	for (i = 0; i < pl08x->vd->channels; i++) {
> +		chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
> +		if (!chan) {
> +			dev_err(&pl08x->adev->dev,
> +				"%s no memory for channel\n", __func__);
> +			return -ENOMEM;
> +		}
> +
> +		chan->host = pl08x;
> +		chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
> +		if (!chan->name) {
> +			kfree(chan);
> +			return -ENOMEM;
> +		}
> +		chan->cd = &pl08x->pd->memcpy_channel;
> +		dev_info(&pl08x->adev->dev,
> +			"initialize virtual memcpy channel \"%s\"\n",
> +			chan->name);
> +
> +		chan->chan.device = memdev;
> +		atomic_set(&chan->last_issued, 0);
> +		chan->lc = atomic_read(&chan->last_issued);
> +
> +		spin_lock_init(&chan->lock);
> +		INIT_LIST_HEAD(&chan->desc_list);
> +		tasklet_init(&chan->tasklet, pl08x_tasklet,
> +			     (unsigned long) chan);
> +
> +		list_add_tail(&chan->chan.device_node, &memdev->channels);
> +	}
> +	dev_info(&pl08x->adev->dev, "initialized %d virtual memcpy channels\n", i);
> +	return i;
> +}
> +
> +/*
> + * Initialise the DMAC slave channels.
> + * Make a local wrapper to hold required data
> + */
> +static int pl08x_dma_init_slave_channels(struct pl08x_driver_data *pl08x,
> +						struct dma_device *slave)

above 2 functions are almost exactly same, can we have single function
instead of two.

> +{
> +	struct pl08x_dma_chan *chan;
> +	int i;
> +
> +	INIT_LIST_HEAD(&slave->channels);
> +	for (i = 0; i < pl08x->pd->num_slave_channels; i++) {
> +		chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
> +		if (!chan) {
> +			dev_err(&pl08x->adev->dev,
> +				"%s no memory for channel\n", __func__);
> +			return -ENOMEM;
> +		}
> +
> +		chan->host = pl08x;
> +		chan->name = pl08x->pd->slave_channels[i].bus_id;
> +		chan->cd = &pl08x->pd->slave_channels[i];
> +		dev_info(&pl08x->adev->dev,
> +			"initialize virtual channel \"%s\"\n",
> +			chan->name);
> +
> +		chan->chan.device = slave;
> +		atomic_set(&chan->last_issued, 0);
> +		chan->lc = atomic_read(&chan->last_issued);
> +
> +		spin_lock_init(&chan->lock);
> +		INIT_LIST_HEAD(&chan->desc_list);
> +		tasklet_init(&chan->tasklet, pl08x_tasklet,
> +			     (unsigned long) chan);
> +
> +		list_add_tail(&chan->chan.device_node, &slave->channels);
> +	}
> +	dev_info(&pl08x->adev->dev, "initialized %d virtual slave channels\n", i);
> +	return i;
> +}
> +
> +static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
> +{
> +	struct pl08x_driver_data *pl08x;
> +	struct vendor_data *vd = id->data;
> +	int ret = 0;
> +	int i;
> +
> +	ret = amba_request_regions(adev, NULL);
> +	if (ret)
> +		return ret;
> +
> +	/* Create the driver state holder */
> +	pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
> +	if (!pl08x) {
> +		ret = -ENOMEM;
> +		goto out_no_pl08x;
> +	}
> +
> +	/* Assign useful pointers to the driver state */
> +	pl08x->adev = adev;
> +	pl08x->vd = vd;
> +
> +	/* A DMA memory pool for LLIs, align on 1-byte boundary */
> +	pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
> +			PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
> +	if (!pl08x->pool) {
> +		ret = -ENOMEM;
> +		goto out_no_lli_pool;
> +	}
> +	pl08x->pool_ctr = 0;
> +	pl08x->max_num_llis = 0;

they are already 0.

> +
> +	spin_lock_init(&pl08x->lock);
> +
> +	pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
> +	if (!pl08x->base) {
> +		ret = -ENOMEM;
> +		goto out_no_ioremap;
> +	}
> +
> +	/* Turn on the PL08x */
> +	pl08x_ensure_on(pl08x);
> +
> +	/*
> +	 * Attach the interrupt handler
> +	 */
> +	writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
> +	writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
> +	mb();
> +
> +	ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
> +			  vd->name, pl08x);
> +	if (ret) {
> +		dev_err(&adev->dev, "%s failed to request "
> +			"interrupt %d\n",
> +			__func__, adev->irq[0]);

can be written in 2 lines only.

> +		goto out_no_irq;
> +	}
> +
> +	/* Initialize physical channels */
> +	pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
> +			GFP_KERNEL);
> +	if (!pl08x->phy_chans) {
> +		dev_err(&adev->dev, "%s failed to allocate "
> +			"physical channel holders\n",
> +			__func__);
> +		goto out_no_phychans;
> +	}
> +
> +	for (i = 0; i < vd->channels; i++) {
> +		struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
> +
> +		ch->id = i;
> +		ch->base = pl08x->base + PL080_Cx_BASE(i);
> +		spin_lock_init(&ch->lock);
> +		ch->serving = NULL;
> +		ch->signal = -1;
> +		dev_info(&adev->dev,
> +			 "physical channel %d is %s\n", i,
> +			 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
> +	}
> +
> +	/* Get the platform data */
> +	pl08x->pd = (struct pl08x_platform_data *)(adev->dev.platform_data);

better to use dev_get_platdata, also no need of typecasting as
platform_data is of type void*.

> +
> +	/* Set caps */
> +	dma_cap_set(DMA_MEMCPY, dmac_memcpy.cap_mask);
> +	dma_cap_set(DMA_SLAVE, dmac_slave.cap_mask);
> +	dmac_memcpy.dev = &adev->dev;
> +	dmac_slave.dev = &adev->dev;
> +
> +	/* Register memcpy channels */
> +	ret = pl08x_dma_init_memcpy_channels(pl08x, &dmac_memcpy);
> +	if (ret <= 0) {
> +		dev_warn(&pl08x->adev->dev,
> +			 "%s failed to enumerate memcpy channels - %d\n",
> +			 __func__, ret);
> +		goto out_no_memcpy;
> +	}
> +	dmac_memcpy.chancnt = ret;
> +
> +	/* Register slave channels */
> +	ret = pl08x_dma_init_slave_channels(pl08x, &dmac_slave);
> +	if (ret <= 0) {
> +		dev_warn(&pl08x->adev->dev,
> +			"%s failed to enumerate slave channels - %d\n",
> +				__func__, ret);
> +		goto out_no_slave;
> +	}
> +	dmac_slave.chancnt = ret;
> +
> +	ret = dma_async_device_register(&dmac_memcpy);
> +	if (ret) {
> +		dev_warn(&pl08x->adev->dev,
> +			"%s failed to register memcpy as an async device - %d\n",
> +			__func__, ret);
> +		goto out_no_memcpy_reg;
> +	}
> +
> +	ret = dma_async_device_register(&dmac_slave);
> +	if (ret) {
> +		dev_warn(&pl08x->adev->dev,
> +			"%s failed to register slave as an async device - %d\n",
> +			__func__, ret);
> +		goto out_no_slave_reg;
> +	}
> +
> +	amba_set_drvdata(adev, pl08x);
> +	dev_info(&pl08x->adev->dev, "ARM(R) %s DMA block initialized @%08x\n",
> +		vd->name, adev->res.start);
> +	return 0;
> +
> +out_no_slave_reg:
> +	dma_async_device_unregister(&dmac_memcpy);
> +out_no_memcpy_reg:
> +	/* FIXME: free slave channels */
> +out_no_slave:
> +	/* FIXME: free memcpy channels */
> +out_no_memcpy:
> +	kfree(pl08x->phy_chans);
> +out_no_phychans:
> +	free_irq(adev->irq[0], pl08x);
> +out_no_irq:
> +	iounmap(pl08x->base);
> +out_no_ioremap:
> +	dma_pool_destroy(pl08x->pool);
> +out_no_lli_pool:
> +	kfree(pl08x);
> +out_no_pl08x:
> +	amba_release_regions(adev);
> +	return ret;
> +}
> +
> +/* PL080 has 8 channels and the PL080 have just 2 */

"PL080 or PL081 have just 2"?? You mentioned at the beginning of this
file, that PL081 has 16 channels. Am i missing something??

> +static struct vendor_data vendor_pl080 = {
> +	.name = "PL080",
> +	.channels = 8,
> +};
> +
> +static struct vendor_data vendor_pl081 = {
> +	.name = "PL081",
> +	.channels = 2,
> +};
> +
> +static struct amba_id pl08x_ids[] = {
> +	/* PL080 */
> +	{
> +		.id	= 0x00041080,
> +		.mask	= 0x000fffff,
> +		.data	= &vendor_pl080,
> +	},
> +	/* PL081 */
> +	{
> +		.id	= 0x00041081,
> +		.mask	= 0x000fffff,
> +		.data	= &vendor_pl081,
> +	},
> +	/* Nomadik 8815 PL080 variant */
> +	{
> +		.id	= 0x00280880,
> +		.mask	= 0x00ffffff,
> +		.data	= &vendor_pl080,
> +	},
> +	{ 0, 0 },
> +};
> +
> +static struct amba_driver pl08x_amba_driver = {
> +	.drv.name	= DRIVER_NAME,
> +	.id_table	= pl08x_ids,
> +	.probe		= pl08x_probe,
> +};
> +
> +static int __init pl08x_init(void)
> +{
> +	int retval;
> +	retval = amba_driver_register(&pl08x_amba_driver);
> +	if (retval)
> +		printk(KERN_WARNING
> +			"PL08X::pl08x_init() - failed to register as an amba device - %d\n",
> +			retval);
> +	return retval;
> +}
> +subsys_initcall(pl08x_init);
> diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
> new file mode 100644
> index 0000000..5f9b16f
> --- /dev/null
> +++ b/include/linux/amba/pl08x.h
> @@ -0,0 +1,173 @@
> +/*
> + *	linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
> + *
> + *	Copyright (C) 2005 ARM Ltd
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * pl08x information required by platform code
> + *
> + * Please credit ARM.com
> + * Documentation: ARM DDI 0196D
> + *
> + */
> +
> +#ifndef AMBA_PL08X_H
> +#define AMBA_PL08X_H
> +
> +/* We need sizes of structs from this header */
> +#include <linux/dmaengine.h>
> +
> +/**
> + * struct pl08x_channel_data - data structure to pass info between
> + * platform and PL08x driver regarding channel configuration
> + * @bus_id: name of this device channel, not just a device name since
> + * devices may have more than one channel e.g. "foo_tx"
> + * @min_signal: the minimum DMA signal number to be muxed in for this
> + * channel (for platforms supporting muxed signals). If you have
> + * static assignments, make sure this is set to the assigned signal
> + * number, PL08x have 16 possible signals in number 0 thru 15 so
> + * when these are not enough they often get muxed (in hardware)
> + * disabling simultaneous use of the same channel for two devices.
> + * @max_signal: the maximum DMA signal number to be muxed in for
> + * the channel. Set to the same as min_signal for
> + * devices with static assignments
> + * @muxval: a number usually used to poke into some mux regiser to
> + * mux in the signal to this channel
> + * @cctl_opt: default options for the channel control register
> + * @circular_buffer: whether the buffer passed in is circular and
> + * shall simply be looped round round (like a record baby round
> + * round round round)
> + */
> +struct pl08x_channel_data {
> +	char *bus_id;
> +	int min_signal;
> +	int max_signal;
> +	u32 muxval;
> +	unsigned int cctl; /* Turn me into u32? */
> +	u32 ccfg;
> +	bool circular_buffer;
> +};
> +
> +/**
> + * struct pl08x_bus_data - information of source or destination
> + * busses for a transfer
> + * @addr: current address
> + * @maxwidth: the maximum width of a transfer on this bus
> + * @buswidth: the width of this bus in bytes: 1, 2 or 4
> + * @fill_bytes: bytes required to fill to the next bus memory
> + * boundary
> + */
> +struct pl08x_bus_data {
> +	dma_addr_t addr;
> +	u8 maxwidth;
> +	u8 buswidth;
> +	u32 fill_bytes;
> +};
> +
> +/**
> + * struct pl08x_phy_chan - holder for the physical channels
> + * @id: physical index to this channel
> + * @lock: a lock to use when altering an instance of this struct
> + * @signal: the physical signal (aka channel) serving this
> + * physical channel right now
> + * @serving: the virtual channel currently being served by this
> + * physical channel
> + */
> +struct pl08x_phy_chan {
> +	unsigned int id;
> +	void __iomem *base;
> +	spinlock_t lock;
> +	int signal;
> +	struct pl08x_dma_chan *serving;
> +	u32 csrc;
> +	u32 cdst;
> +	u32 clli;
> +	u32 cctl;
> +	u32 ccfg;
> +};
> +
> +/**
> + * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
> + * @llis_bus: DMA memory address (physical) start for the LLIs
> + * @llis_va: virtual memory address start for the LLIs
> + */
> +struct pl08x_txd {
> +	struct dma_async_tx_descriptor tx;
> +	enum dma_data_direction	direction;
> +	struct pl08x_bus_data srcbus;
> +	struct pl08x_bus_data dstbus;
> +	int len;
> +	dma_addr_t llis_bus;
> +	void *llis_va;
> +	struct list_head node;
> +	struct pl08x_channel_data *cd;
> +	bool active;
> +	/* Settings to be put into the physical channel when we submit this txd */
> +	u32 csrc;
> +	u32 cdst;
> +	u32 clli;
> +	u32 cctl;
> +};
> +
> +/**
> + * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
> + * @chan: wrappped abstract channel
> + * @phychan: the physical channel utilized by this channel, if there is one
> + * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
> + * @name: name of channel
> + * @cd: channel platform data
> + * @amba_addr: address for RX/TX according to the PrimeCell config
> + * @amba_direction: current direction of this channel according to
> + * @lc: last completed transaction on this channel
> + * @desc_list: queued transactions pending on this channel
> + * @at: active transaction on this channel
> + * @lock: a lock for this channel data
> + * @host: a pointer to the host (internal use)
> + */
> +struct pl08x_dma_chan {
> +	struct dma_chan chan;
> +	struct pl08x_phy_chan *phychan;
> +	struct tasklet_struct tasklet;
> +	char *name;
> +	struct pl08x_channel_data *cd;
> +	dma_addr_t amba_addr;
> +	enum dma_data_direction	amba_direction;
> +	atomic_t last_issued;
> +	dma_cookie_t lc;
> +	struct list_head desc_list;
> +	struct pl08x_txd *at;
> +	spinlock_t lock;
> +	void *host;
> +};
> +
> +/**
> + * struct pl08x_platform_data - the platform configuration for the
> + * PL08x PrimeCells.
> + * @slave_channels: the channels defined for the different devices on the
> + * platform, all inclusive, including multiplexed channels. The available
> + * physical channels will be multiplexed around these signals as they
> + * are requested, just enumerate all possible channels.
> + * @get_signal: request a physical signal to be used for a DMA
> + * transfer immediately: if there is some multiplexing or similar blocking
> + * the use of the channel the transfer can be denied by returning
> + * less than zero, else it returns the allocated signal number
> + * @put_signal: indicate to the platform that this physical signal is not
> + * running any DMA transfer and multiplexing can be recycled
> + * @bus_bit_lli: Bit[0] of the address indicated which AHB bus master the
> + * LLI addresses are on 0/1 Master 1/2.
> + */
> +struct pl08x_platform_data {
> +	struct pl08x_channel_data *slave_channels;
> +	unsigned int num_slave_channels;
> +	struct pl08x_channel_data memcpy_channel;
> +	int (*get_signal)(struct pl08x_dma_chan *);
> +	void (*put_signal)(struct pl08x_dma_chan *);
> +	unsigned int bus_bit_lli:1;
> +};
> +
> +bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
> +
> +#endif	/* AMBA_PL08X_H */



From anarsoul at gmail.com  Mon Jun 14 02:04:11 2010
From: anarsoul at gmail.com (Vasily Khoruzhick)
Date: Mon, 14 Jun 2010 09:04:11 +0300
Subject: [PATCH v2] rtc-s3c: Fix rtc-s3c driver initialization
In-Reply-To: <1274975846-14006-1-git-send-email-anarsoul@gmail.com>
References: <1274975846-14006-1-git-send-email-anarsoul@gmail.com>
Message-ID: <201006140904.17950.anarsoul@gmail.com>

? ????????? ?? 27 ??? 2010 18:57:26 ????? Vasily Khoruzhick ???????:
> setfreq should be called only after rtc device registration,
> as it uses rtc device; s3c_rtc_cpu_type should be checked
> only once it was set.
> 
> Signed-off-by: Vasily Khoruzhick <anarsoul at gmail.com>

Hi, Ben.

What about this patch? I've seen similar series on linux-samsung-soc maillist, 
but neither their series nor my patch is applied to your tree. Why? :)

Regards
Vasily
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From benh at kernel.crashing.org  Mon Jun 14 02:09:32 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Mon, 14 Jun 2010 16:09:32 +1000
Subject: Request review of device tree documentation
In-Reply-To: <AANLkTikBjwuVvij8I91XaQgLfn8r_lZDrAsIBfJrHDBF@mail.gmail.com>
References: <AANLkTilK4YkRMJqlcRDOAlGBzpdlZuSo9NF5NrRNocHT@mail.gmail.com>
	<33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com>
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com>
	<4C13430B.5000907@firmworks.com> <1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<1276408087.1962.552.camel@pasglop>
	<AANLkTikBjwuVvij8I91XaQgLfn8r_lZDrAsIBfJrHDBF@mail.gmail.com>
Message-ID: <1276495772.2552.22.camel@pasglop>

On Sun, 2010-06-13 at 23:13 -0600, Grant Likely wrote:
> > We use that to suck the device-tree, which we flatten, and then
> re-enter
> > the kernel with the "common" entry interface.
> 
> I don't think I want to do the same on ARM.  I'd rather have the
> prom_init stuff in a boot wrapper, or have OFW itself generate the
> flat representation before booting the kernel.

But then it's no longer OF. IE. A compliant OF implementation provides a
client interface API :-)

This is going to be especially important if Mitch wants to keep OF
alive.

I suppose it could be done via a wrapper like prom_init, which flattens
the tree, and sticks somewhere in a property the address of the OF
client interface callback though it's a tad awkward. If well defined, I
suppose Mitch might even be able to make his OF natively boot kernels
that way but that's of course up to him.

> I'm trying to constrain the number of things that could go wrong by
> defining only one way for getting the device tree data into the
> kernel.

I understand, and the flattened method is the most versatile, I'm just
pointing out the situation here :-)

> Right.  We don't need to use OFW/RTAS to handle this use case.

Definitely not. It will depend on whatever hypervisor interface is
implemented in a given environment. Though I do like the idea of passing
precompiled bits of .dtb around for hotplug :-) We could make that a
standard way of KVM to do things in embedded space.

Cheers,
Ben.




From wmb at firmworks.com  Mon Jun 14 02:17:13 2010
From: wmb at firmworks.com (Mitch Bradley)
Date: Sun, 13 Jun 2010 20:17:13 -1000
Subject: Request review of device tree documentation
In-Reply-To: <1276495772.2552.22.camel@pasglop>
References: <AANLkTilK4YkRMJqlcRDOAlGBzpdlZuSo9NF5NrRNocHT@mail.gmail.com>	
	<33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com>	
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com>	
	<4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop>	
	<1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com>	
	<1276383132.1962.195.camel@pasglop>	
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>	
	<1276408087.1962.552.camel@pasglop>	
	<AANLkTikBjwuVvij8I91XaQgLfn8r_lZDrAsIBfJrHDBF@mail.gmail.com>
	<1276495772.2552.22.camel@pasglop>
Message-ID: <4C15C969.7020108@firmworks.com>

Benjamin Herrenschmidt wrote:
> On Sun, 2010-06-13 at 23:13 -0600, Grant Likely wrote:
>   
>>> We use that to suck the device-tree, which we flatten, and then
>>>       
>> re-enter
>>     
>>> the kernel with the "common" entry interface.
>>>       
>> I don't think I want to do the same on ARM.  I'd rather have the
>> prom_init stuff in a boot wrapper, or have OFW itself generate the
>> flat representation before booting the kernel.
>>     
>
> But then it's no longer OF. IE. A compliant OF implementation provides a
> client interface API :-)
>
> This is going to be especially important if Mitch wants to keep OF
> alive.
>
> I suppose it could be done via a wrapper like prom_init, which flattens
> the tree, and sticks somewhere in a property the address of the OF
> client interface callback though it's a tad awkward. If well defined, I
> suppose Mitch might even be able to make his OF natively boot kernels
> that way but that's of course up to him.
>   

I'm willing to create a flattened tree.  I can provide both a client 
interface and a flattened tree.  The kernel probably won't use the 
client interface to any significant extent.

Way back in the misty annals of history, I dreamed of having a common 
interface between firmware and OSs.  That didn't happen.  Every OS 
insisted on defining its own interface and creating a custom bootloader, 
or in some cases a half dozen of them.
>   
>> I'm trying to constrain the number of things that could go wrong by
>> defining only one way for getting the device tree data into the
>> kernel.
>>     
>
> I understand, and the flattened method is the most versatile, I'm just
> pointing out the situation here :-)
>
>   
>> Right.  We don't need to use OFW/RTAS to handle this use case.
>>     
>
> Definitely not. It will depend on whatever hypervisor interface is
> implemented in a given environment. Though I do like the idea of passing
> precompiled bits of .dtb around for hotplug :-) We could make that a
> standard way of KVM to do things in embedded space.
>
> Cheers,
> Ben.
>
>
>   


From LW at KARO-electronics.de  Mon Jun 14 02:39:21 2010
From: LW at KARO-electronics.de (=?iso-8859-15?Q?Lothar_Wa=DFmann?=)
Date: Mon, 14 Jun 2010 08:39:21 +0200
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <1276319643.1962.181.camel@pasglop>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
	<1276319643.1962.181.camel@pasglop>
Message-ID: <19477.52889.982995.407051@ipc1.ka-ro>

Hi,

Benjamin Herrenschmidt writes:
> On Fri, 2010-06-11 at 12:08 +0200, Lothar Wa?mann wrote:
> > Hi,
> > 
> > > > > > Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> > > > > > makes it impossible to call those functions in interrupt context.
> > > IMHO if a device generates an irq its clock should already be on.  This
> > > way you don't need to enable or disable a clock in irq context.
> > >  
> > You may want to disable a clock in the IRQ handler. The VPU driver in
> > the Freescale BSP for i.MX51 does exactly this.
> > Anyway I don't see any reason for using a mutex here instead of
> > spin_lock_irq_save() as all other implementations do.
> 
> Because you suddenly make it impossible to sleep inside enable/disable
              ^^^^^^^^^^^^^^^^^^^^^^^^^^^
???
All implementations so far use spin_lock_irq_save()!

How would you be able to sleep with a mutex held?
If you hold a lock you must not sleep, no matter what sort of lock it
is.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From u.kleine-koenig at pengutronix.de  Mon Jun 14 02:40:28 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 14 Jun 2010 08:40:28 +0200
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19477.52889.982995.407051@ipc1.ka-ro>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
	<1276319643.1962.181.camel@pasglop>
	<19477.52889.982995.407051@ipc1.ka-ro>
Message-ID: <20100614064028.GA12159@pengutronix.de>

Hello Lothar,

On Mon, Jun 14, 2010 at 08:39:21AM +0200, Lothar Wa?mann wrote:
> Hi,
> 
> Benjamin Herrenschmidt writes:
> > On Fri, 2010-06-11 at 12:08 +0200, Lothar Wa?mann wrote:
> > > Hi,
> > > 
> > > > > > > Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> > > > > > > makes it impossible to call those functions in interrupt context.
> > > > IMHO if a device generates an irq its clock should already be on.  This
> > > > way you don't need to enable or disable a clock in irq context.
> > > >  
> > > You may want to disable a clock in the IRQ handler. The VPU driver in
> > > the Freescale BSP for i.MX51 does exactly this.
> > > Anyway I don't see any reason for using a mutex here instead of
> > > spin_lock_irq_save() as all other implementations do.
> > 
> > Because you suddenly make it impossible to sleep inside enable/disable
>               ^^^^^^^^^^^^^^^^^^^^^^^^^^^
> ???
> All implementations so far use spin_lock_irq_save()!
> 
> How would you be able to sleep with a mutex held?
> If you hold a lock you must not sleep, no matter what sort of lock it
> is.
That's wrong.  With a mutex hold you may sleep.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From LW at KARO-electronics.de  Mon Jun 14 02:52:25 2010
From: LW at KARO-electronics.de (=?iso-8859-15?Q?Lothar_Wa=DFmann?=)
Date: Mon, 14 Jun 2010 08:52:25 +0200
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100614064028.GA12159@pengutronix.de>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
	<1276319643.1962.181.camel@pasglop>
	<19477.52889.982995.407051@ipc1.ka-ro>
	<20100614064028.GA12159@pengutronix.de>
Message-ID: <19477.53673.644128.558827@ipc1.ka-ro>

Hi,

Uwe Kleine-K?nig writes:
> Hello Lothar,
> 
> On Mon, Jun 14, 2010 at 08:39:21AM +0200, Lothar Wa?mann wrote:
> > Hi,
> > 
> > Benjamin Herrenschmidt writes:
> > > On Fri, 2010-06-11 at 12:08 +0200, Lothar Wa?mann wrote:
> > > > Hi,
> > > > 
> > > > > > > > Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> > > > > > > > makes it impossible to call those functions in interrupt context.
> > > > > IMHO if a device generates an irq its clock should already be on.  This
> > > > > way you don't need to enable or disable a clock in irq context.
> > > > >  
> > > > You may want to disable a clock in the IRQ handler. The VPU driver in
> > > > the Freescale BSP for i.MX51 does exactly this.
> > > > Anyway I don't see any reason for using a mutex here instead of
> > > > spin_lock_irq_save() as all other implementations do.
> > > 
> > > Because you suddenly make it impossible to sleep inside enable/disable
> >               ^^^^^^^^^^^^^^^^^^^^^^^^^^^
> > ???
> > All implementations so far use spin_lock_irq_save()!
> > 
> > How would you be able to sleep with a mutex held?
> > If you hold a lock you must not sleep, no matter what sort of lock it
> > is.
> That's wrong.  With a mutex hold you may sleep.
> 
OK, you're right. But still all other implementations (omap, mxc,
davinci,...) use spin_lock_irqsave() to protect the enable/disable
functions and don't seem to have any problem with this.
Is there any reason to change this, or make it inconsistent
for one arch?

And arch/arm/plat-s3c/clock.c has the following comment:
|/* We originally used an mutex here, but some contexts (see resume)
| * are calling functions such as clk_set_parent() with IRQs disabled
| * causing an BUG to be triggered.
| */
|DEFINE_SPINLOCK(clocks_lock);


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From kgene.kim at samsung.com  Mon Jun 14 02:57:48 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 14 Jun 2010 15:57:48 +0900
Subject: [PATCH v3] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <4C120685.8030306@mvista.com>
References: <1276156241-28804-1-git-send-email-kgene.kim@samsung.com>
	<4C10C1D6.8080708@ru.mvista.com>
	<003301cb0937$e04412c0$a0cc3840$%kim@samsung.com>
	<4C120685.8030306@mvista.com>
Message-ID: <008801cb0b8e$e89a50c0$b9cef240$%kim@samsung.com>

Sergei Shtylyov wrote:
> 
> Hello.
> 
> Kukjin Kim wrote:
> 
> >>> From: Abhilash Kesavan <a.kesavan at samsung.com>
> >>> Adds support for the Samsung PATA controller. This driver is based on
the
> >>> Libata subsystem and references the earlier patches sent for IDE
subsystem.
> 
> > Hi,
> 
> > Thanks for your comments.
> 
> >>> Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> >>> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> >> [...]
> 
> >>> diff --git a/drivers/ata/pata_samsung_cf.c
b/drivers/ata/pata_samsung_cf.c
> >>> new file mode 100644
> >>> index 0000000..fef5515
> >>> --- /dev/null
> >>> +++ b/drivers/ata/pata_samsung_cf.c
> >>> @@ -0,0 +1,608 @@
> >>> +/* linux/drivers/ata/pata_samsung_cf.c
> 
> >>     File names in the heading comment are discouraged.
> 
> > Hmm. I used like that in other device drivers.
> 
>     Nevertheless, it's quite an old rule already.
> 
> > Ok..will remove the file name in the heading comment.
> 
> >> [...]
> 
> >>> +
> >>> +	piotime = (t2i << 12) | (t2 << 4) | t1;
> >>> +
> >>> +	return piotime;
> >>> +}
> >>> +
> >>> +static void pata_s3c_set_piomode(struct ata_port *ap, struct
ata_device
> *adev)
> >>> +{
> >>> +	int mode = adev->pio_mode - XFER_PIO_0;
> >>> +	struct s3c_ide_info *info = ap->host->private_data;
> >>> +	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
> >>> +	ulong piotime;
> >>> +
> >>> +	/* Calculates timing parameters for PIO mode */
> >>> +	piotime = pata_s3c_setup_timing(info, adev);
> 
> >>     In fact, for 8-bit (command) timing you should program the slowest
mode
> of
> >> the two drives. However, with CF, you probably only have only one drive
per
> >> channel...
> 
> > Below code looks OK ?
> 
>     No, it doesn't.
> 
> > 	if (ata_timing_compute(adev, adev->pio_mode, &timing, cycle_time, 0))
> > {
> > 		dev_err(ap->dev, "Failed to compute ATA timing\n");
> > 		piotime = pata_s3c_setup_timing(info, &initial_timing);
> > 	} else {
> > 		piotime = pata_s3c_setup_timing(info, &timing);
> > 	}
> > where initial_timing is for PIO0. I have added the below struct
> 
> > static const struct ata_timing initial_timing =
> > 	{XFER_PIO_0, 70, 290, 240, 600, 165, 150, 0, 600, 0};
> 
>     I'd call ata_timing_find_mode(XFER_PIO_0) rather than duplicating the
> ata_timing entry. But really, you shouldn't set any timing for an invalid
mode
> and, as I said, you won't be passed one, so there's nor much sense in
calling
> ata_timing_compute() and checking its result; anyway, you'd want to call
> ata_timing_find_mode() here instead of ata_timing_compute() because the
latter
> returns already quantized timings, but initial_timing is not quantized,
you'll
> have to call ata_timing_compute() in pata_s3c_setup_timing() anyway.
> 
OK, no check for invalid mode then. Now using 'ata_timing_compute' to get the
quantized timings t1, t2 and t2i and then writing them to PIO_TIME registers.
PIO_TIME [0:3]  t1      [4:11] t2      [12:19] t2i.

> >>> +
> >>> +	/* Enables IORDY if mode requires it */
> >>> +	if (ata_pio_need_iordy(adev))
> >>> +		ata_cfg |= S3C_ATA_CFG_IORDYEN;
> >>> +	else
> >>> +		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
> >>> +
> >>> +	/* Host controller supports upto PIO4 only */
> >>> +	if (mode >= 0 && mode <= 4) {
> 
> >>     No need to check -- you won't be passed a mode not specified by your
> >> pio_mask.
> 
> > Will remove the check.
> 
> >>> +static int __devinit pata_s3c_probe(struct platform_device *pdev)
> [...]
> >>> +	if (!request_mem_region(res->start, resource_size(res), DRV_NAME)) {
> 
> >>     Probably should call devm_request_mem_region() if you're using
> >> devm_ioremap()...
> 
> > Will change to devm_request_mem_region.
> 
>     This function does exist, if I don't mistake...
> 
> >>> +release_mem:
> >>> +	release_mem_region(res->start, resource_size(res));
> >>> +release_device_mem:
> >>> +	kfree(info);
> 
> >>     Doesn't using devm_kzalloc() guarantee that the memory will be freed
up
> >> automatically?
> 
> > Will remove kfree and release_mem_region because of devm_kzalloc and
> > devm_request_mem_region usage
> 
>     I don't know devres librarry capabilities well. Tejun, am I right?
> 
> >>> +static struct platform_driver pata_s3c_driver = {
> >>> +	.probe		= pata_s3c_probe,
> >>>
> >>>
> 
> >>     2 empty lines -- broken patch?
> 
> > Seems OK at my end.
> 
>     The sent patch had them, nevertheless.
> 
> MBR, Sergei


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From eric at eukrea.com  Mon Jun 14 03:07:46 2010
From: eric at eukrea.com (=?UTF-8?B?RXJpYyBCw6luYXJk?=)
Date: Mon, 14 Jun 2010 09:07:46 +0200
Subject: [PATCH] mxc_nand: fix PM
In-Reply-To: <1274982919-13251-1-git-send-email-eric@eukrea.com>
References: <1274942000-3580-2-git-send-email-eric@eukrea.com>
	<1274982919-13251-1-git-send-email-eric@eukrea.com>
Message-ID: <4C15D542.2060102@eukrea.com>

Hi Sascha,

Le 27/05/2010 19:55, Eric B?nard a ?crit :
> * when resuming, we get the following log :
> nand_resume called for a chip which is not in suspended state
> * this happens because mtd->suspend and mtd->resume are already
> called from the mtd layer, thus they were called a second time
> in mxc_nand so mtd complains when trying to resume for the
> second time
> * the fix is to remove these call and thus remove the supend and
> resume functions of mxc_nand
>
any news concerning this patch ?

Eric

> Signed-off-by: Eric B?nard<eric at eukrea.com>
> Cc: s.hauer at pengutronix.de
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: linux-mtd at lists.infradead.org
> ---
>   drivers/mtd/nand/mxc_nand.c |   44 +------------------------------------------
>   1 files changed, 1 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
> index 314e2bf..217b247 100644
> --- a/drivers/mtd/nand/mxc_nand.c
> +++ b/drivers/mtd/nand/mxc_nand.c
> @@ -892,53 +892,11 @@ static int __devexit mxcnd_remove(struct platform_device *pdev)
>   	return 0;
>   }
>
> -#ifdef CONFIG_PM
> -static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
> -{
> -	struct mtd_info *mtd = platform_get_drvdata(pdev);
> -	struct nand_chip *nand_chip = mtd->priv;
> -	struct mxc_nand_host *host = nand_chip->priv;
> -	int ret = 0;
> -
> -	DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
> -
> -	ret = mtd->suspend(mtd);
> -
> -	/*
> -	 * nand_suspend locks the device for exclusive access, so
> -	 * the clock must already be off.
> -	 */
> -	BUG_ON(!ret&&  host->clk_act);
> -
> -	return ret;
> -}
> -
> -static int mxcnd_resume(struct platform_device *pdev)
> -{
> -	struct mtd_info *mtd = platform_get_drvdata(pdev);
> -	struct nand_chip *nand_chip = mtd->priv;
> -	struct mxc_nand_host *host = nand_chip->priv;
> -	int ret = 0;
> -
> -	DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
> -
> -	mtd->resume(mtd);
> -
> -	return ret;
> -}
> -
> -#else
> -# define mxcnd_suspend   NULL
> -# define mxcnd_resume    NULL
> -#endif				/* CONFIG_PM */
> -
>   static struct platform_driver mxcnd_driver = {
>   	.driver = {
>   		   .name = DRIVER_NAME,
> -		   },
> +	},
>   	.remove = __devexit_p(mxcnd_remove),
> -	.suspend = mxcnd_suspend,
> -	.resume = mxcnd_resume,
>   };
>
>   static int __init mxc_nd_init(void)



From kgene.kim at samsung.com  Mon Jun 14 03:07:43 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 14 Jun 2010 16:07:43 +0900
Subject: [PATCH v4] libata: pata_samsung_cf: Add Samsung PATA controller driver
Message-ID: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>

From: Abhilash Kesavan <a.kesavan at samsung.com>

Adds support for the Samsung PATA controller. This driver is based on the
Libata subsystem and references the earlier patches sent for IDE subsystem.

Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---

Changes since v3:

Addressed comments from 

Sergei Shtylyov:
	- Removed filename in header
	- Used ata_timing_compute for obtaining timing parameters
	- Removed valid PIO mode check
	- Added softreset method and associated functions
	- Used devm_request_mem_region function as had used devm_ioremap
	  earlier
	- Removed kree and release_mem_region calls because of managed
	  kzalloc and request_mem_region fns being used
	- Added return in clk_get function
	- Added missing clk_put
	- Corrected indentation issue

Ben Dooks:
	- Added missing 'void __iomem' parameters
	- Added check for trailing bytes in data_xfer function
	- Removed assignment in data_xfer function
	- Coding changes - e.g. in pata_s3c_enable, pata_s3c_dev_select,
	  wait_for_host_ready
	- Removed host checks in suspend/resume functions

 drivers/ata/Kconfig           |    9 +
 drivers/ata/Makefile          |    1 +
 drivers/ata/pata_samsung_cf.c |  735 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 745 insertions(+), 0 deletions(-)
 create mode 100644 drivers/ata/pata_samsung_cf.c

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index aa85a98..1b5facf 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -796,6 +796,15 @@ config PATA_RZ1000
 
 	  If unsure, say N.
 
+config PATA_SAMSUNG_CF
+	tristate "Samsung SoC PATA support"
+	depends on SAMSUNG_DEV_IDE
+	help
+	  This option enables basic support for Samsung's S3C/S5P board
+	  PATA controllers via the new ATA layer
+
+	  If unsure, say N.
+
 config PATA_WINBOND_VLB
 	tristate "Winbond W83759A VLB PATA support (Experimental)"
 	depends on ISA && EXPERIMENTAL
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 7ef89d7..9576776 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_PATA_OF_PLATFORM)	+= pata_of_platform.o
 obj-$(CONFIG_PATA_QDI)		+= pata_qdi.o
 obj-$(CONFIG_PATA_RB532)	+= pata_rb532_cf.o
 obj-$(CONFIG_PATA_RZ1000)	+= pata_rz1000.o
+obj-$(CONFIG_PATA_SAMSUNG_CF)	+= pata_samsung_cf.o
 obj-$(CONFIG_PATA_WINBOND_VLB)	+= pata_winbond.o
 
 # Should be last but two libata driver
diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
new file mode 100644
index 0000000..aeb2825
--- /dev/null
+++ b/drivers/ata/pata_samsung_cf.c
@@ -0,0 +1,735 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * PATA driver for Samsung SoCs.
+ * Supports CF Interface in True IDE mode. Currently only PIO mode has been
+ * implemented; UDMA support has to be added.
+ *
+ * Based on:
+ *	PATA driver for AT91SAM9260 Static Memory Controller
+ *	PATA driver for Toshiba SCC controller
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/libata.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <plat/ata.h>
+#include <plat/regs-ata.h>
+
+#define DRV_NAME "pata_samsung_cf"
+#define DRV_VERSION "0.1"
+
+enum s3c_cpu_type {
+	TYPE_S3C64XX,
+	TYPE_S5PC100,
+	TYPE_S5PV210,
+};
+
+/*
+ * struct s3c_ide_info - S3C PATA instance.
+ * @clk: The clock resource for this controller.
+ * @ide_addr: The area mapped for the hardware registers.
+ * @sfr_addr: The area mapped for the special function registers.
+ * @irq: The IRQ number we are using.
+ * @cpu_type: The exact type of this controller.
+ * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
+ */
+struct s3c_ide_info {
+	struct clk *clk;
+	void __iomem *ide_addr;
+	void __iomem *sfr_addr;
+	unsigned int irq;
+	enum s3c_cpu_type cpu_type;
+	unsigned int fifo_status_reg;
+};
+
+static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
+{
+	u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
+	reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
+	writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
+}
+
+static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
+{
+	/* Select true-ide as the internal operating mode */
+	writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
+		s3c_ide_sfrbase + S3C_CFATA_MUX);
+}
+
+static unsigned long
+pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
+{
+	int t1;
+	int t2;
+	int t2i;
+	ulong piotime;
+
+	t1 = ata->setup;
+	t2 = ata->act8b;
+	t2i = ata->rec8b;
+
+	piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
+
+	return piotime;
+}
+
+static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+	struct s3c_ide_info *info = ap->host->private_data;
+	struct ata_timing timing;
+	int cycle_time;
+	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
+	ulong piotime;
+
+	/* Enables IORDY if mode requires it */
+	if (ata_pio_need_iordy(adev))
+		ata_cfg |= S3C_ATA_CFG_IORDYEN;
+	else
+		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
+
+	cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
+
+	ata_timing_compute(adev, adev->pio_mode, &timing,
+					cycle_time * 1000, 0);
+
+	piotime = pata_s3c_setup_timing(info, &timing);
+
+	writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
+	writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
+}
+
+/*
+ * Waits until the IDE controller is able to perform next read/write
+ * operation to the disk. Needed for 64XX series boards only.
+ */
+static int wait_for_host_ready(struct s3c_ide_info *info)
+{
+	ulong timeout;
+	void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
+
+	/* wait for maximum of 20 msec */
+	timeout = jiffies + msecs_to_jiffies(20);
+	while (time_before(jiffies, timeout)) {
+		if ((readl(fifo_reg) >> 28) == 0)
+			return 0;
+	}
+	return -EBUSY;
+}
+
+/*
+ * Writes to one of the task file registers.
+ */
+static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
+{
+	struct s3c_ide_info *info = host->private_data;
+
+	wait_for_host_ready(info);
+	writeb(addr, reg);
+}
+
+/*
+ * Reads from one of the task file registers.
+ */
+static u8 ata_inb(struct ata_host *host, void __iomem *reg)
+{
+	struct s3c_ide_info *info = host->private_data;
+	u8 temp;
+
+	wait_for_host_ready(info);
+	(void) readb(reg);
+	wait_for_host_ready(info);
+	temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
+	return temp;
+}
+
+/*
+ * pata_s3c_tf_load - send taskfile registers to host controller
+ */
+static void pata_s3c_tf_load(struct ata_port *ap,
+				const struct ata_taskfile *tf)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
+
+	if (tf->ctl != ap->last_ctl) {
+		ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
+		ap->last_ctl = tf->ctl;
+		ata_wait_idle(ap);
+	}
+
+	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
+		ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
+		ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
+		ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
+		ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
+		ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
+	}
+
+	if (is_addr) {
+		ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
+		ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
+		ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
+		ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
+		ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
+	}
+
+	if (tf->flags & ATA_TFLAG_DEVICE)
+		ata_outb(ap->host, tf->device, ioaddr->device_addr);
+
+	ata_wait_idle(ap);
+}
+
+/*
+ * pata_s3c_tf_read - input device's ATA taskfile shadow registers
+ */
+static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+
+	tf->feature = ata_inb(ap->host, ioaddr->error_addr);
+	tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+	tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+	tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
+	tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
+	tf->device = ata_inb(ap->host, ioaddr->device_addr);
+
+	if (tf->flags & ATA_TFLAG_LBA48) {
+		iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
+		tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
+		tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+		tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+		tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
+		tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
+		iowrite8(tf->ctl, ioaddr->ctl_addr);
+		ap->last_ctl = tf->ctl;
+	}
+}
+
+/*
+ * pata_s3c_exec_command - issue ATA command to host controller
+ */
+static void pata_s3c_exec_command(struct ata_port *ap,
+				const struct ata_taskfile *tf)
+{
+	ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
+	ata_sff_pause(ap);
+}
+
+/*
+ * pata_s3c_check_status - Read device status register
+ */
+static u8 pata_s3c_check_status(struct ata_port *ap)
+{
+	return ata_inb(ap->host, ap->ioaddr.status_addr);
+}
+
+/*
+ * pata_s3c_check_altstatus - Read alternate device status register
+ */
+static u8 pata_s3c_check_altstatus(struct ata_port *ap)
+{
+	return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
+}
+
+/*
+ * pata_s3c_data_xfer - Transfer data by PIO
+ */
+unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char *buf,
+				unsigned int buflen, int rw)
+{
+	struct ata_port *ap = dev->link->ap;
+	struct s3c_ide_info *info = ap->host->private_data;
+	void __iomem *data_addr = ap->ioaddr.data_addr;
+	unsigned int words = buflen >> 1, i;
+	u16 *data_ptr = (u16 *)buf;
+
+	/* Requires wait same as in ata_inb/ata_outb */
+	if (rw == READ)
+		for (i = 0; i < words; i++, data_ptr++) {
+			wait_for_host_ready(info);
+			(void) readw(data_addr);
+			wait_for_host_ready(info);
+			*data_ptr = readw(info->ide_addr
+					+ S3C_ATA_PIO_RDATA);
+		}
+	else
+		for (i = 0; i < words; i++, data_ptr++) {
+			wait_for_host_ready(info);
+			writew(*data_ptr, data_addr);
+		}
+
+	if (buflen & 0x01) {
+		dev_err(ap->dev, "unexpected trailing data\n");
+		return -EINVAL;
+	}
+
+	return words << 1;
+}
+
+/*
+ * pata_s3c_dev_select - Select device on ATA bus
+ */
+static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
+{
+	u8 tmp = ATA_DEVICE_OBS;
+
+	if (device != 0)
+		tmp |= ATA_DEV1;
+
+	ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
+	ata_sff_pause(ap);
+}
+
+/*
+ * pata_s3c_devchk - PATA device presence detection
+ */
+static unsigned int pata_s3c_devchk(struct ata_port *ap,
+				unsigned int device)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+	u8 nsect, lbal;
+
+	ap->ops->sff_dev_select(ap, device);
+
+	ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
+	ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
+
+	ata_outb(ap->host, 0xaa, ioaddr->nsect_addr);
+	ata_outb(ap->host, 0x55, ioaddr->lbal_addr);
+
+	ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
+	ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
+
+	nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+	lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+
+	if ((nsect == 0x55) && (lbal == 0xaa))
+		return 1;	/* we found a device */
+
+	return 0;		/* nothing found */
+}
+
+/*
+ * pata_s3c_wait_after_reset - wait for devices to become ready after reset
+ */
+static int pata_s3c_wait_after_reset(struct ata_link *link,
+		unsigned int devmask, unsigned long deadline)
+{
+	struct ata_port *ap = link->ap;
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+	unsigned int dev0 = devmask & (1 << 0);
+	unsigned int dev1 = devmask & (1 << 1);
+	int rc, ret = 0;
+
+	msleep(ATA_WAIT_AFTER_RESET);
+
+	/* always check readiness of the master device */
+	rc = ata_sff_wait_ready(link, deadline);
+	if (rc)
+		return rc;
+
+	/* if device 1 was found in ata_devchk, wait for register
+	 * access briefly, then wait for BSY to clear.
+	 */
+	if (dev1) {
+		int i;
+
+		ap->ops->sff_dev_select(ap, 1);
+
+		for (i = 0; i < 2; i++) {
+			u8 nsect, lbal;
+
+			nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+			lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+			if ((nsect == 1) && (lbal == 1))
+				break;
+			msleep(50);	/* give drive a breather */
+		}
+
+		rc = ata_sff_wait_ready(link, deadline);
+		if (rc) {
+			if (rc != -ENODEV)
+				return rc;
+			ret = rc;
+		}
+	}
+
+	ap->ops->sff_dev_select(ap, 0);
+	if (dev1)
+		ap->ops->sff_dev_select(ap, 1);
+	if (dev0)
+		ap->ops->sff_dev_select(ap, 0);
+
+	return ret;
+}
+
+/*
+ * pata_s3c_bus_softreset - PATA device software reset
+ */
+static unsigned int pata_s3c_bus_softreset(struct ata_port *ap,
+		unsigned int devmask, unsigned long deadline)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+
+	/* software reset.  causes dev0 to be selected */
+	ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
+	udelay(20);
+	ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr);
+	udelay(20);
+	ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
+	ap->last_ctl = ap->ctl;
+
+	return pata_s3c_wait_after_reset(&ap->link, devmask, deadline);
+}
+
+/*
+ * pata_s3c_softreset - reset host port via ATA SRST
+ */
+static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
+			 unsigned long deadline)
+{
+	struct ata_port *ap = link->ap;
+	unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
+	unsigned int devmask = 0;
+	int rc;
+	u8 err;
+
+	/* determine if device 0/1 are present */
+	if (pata_s3c_devchk(ap, 0))
+		devmask |= (1 << 0);
+	if (slave_possible && pata_s3c_devchk(ap, 1))
+		devmask |= (1 << 1);
+
+	/* select device 0 again */
+	ap->ops->sff_dev_select(ap, 0);
+
+	/* issue bus reset */
+	rc = pata_s3c_bus_softreset(ap, devmask, deadline);
+	/* if link is occupied, -ENODEV too is an error */
+	if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
+		ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
+		return rc;
+	}
+
+	/* determine by signature whether we have ATA or ATAPI devices */
+	classes[0] = ata_sff_dev_classify(&ap->link.device[0],
+					  devmask & (1 << 0), &err);
+	if (slave_possible && err != 0x81)
+		classes[1] = ata_sff_dev_classify(&ap->link.device[1],
+						  devmask & (1 << 1), &err);
+
+	return 0;
+}
+
+/*
+ * pata_s3c_set_devctl - Write device control register
+ */
+static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
+{
+	ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
+}
+
+static struct scsi_host_template pata_s3c_sht = {
+	ATA_PIO_SHT(DRV_NAME),
+};
+
+static struct ata_port_operations pata_s3c_port_ops = {
+	.inherits		= &ata_sff_port_ops,
+	.sff_check_status	= pata_s3c_check_status,
+	.sff_check_altstatus    = pata_s3c_check_altstatus,
+	.sff_tf_load		= pata_s3c_tf_load,
+	.sff_tf_read		= pata_s3c_tf_read,
+	.sff_data_xfer		= pata_s3c_data_xfer,
+	.sff_exec_command	= pata_s3c_exec_command,
+	.sff_dev_select         = pata_s3c_dev_select,
+	.sff_set_devctl         = pata_s3c_set_devctl,
+	.softreset		= pata_s3c_softreset,
+	.set_piomode		= pata_s3c_set_piomode,
+};
+
+static struct ata_port_operations pata_s5p_port_ops = {
+	.inherits		= &ata_sff_port_ops,
+	.set_piomode		= pata_s3c_set_piomode,
+};
+
+static void pata_s3c_enable(void *s3c_ide_regbase, bool state)
+{
+	u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
+	temp = state ? (temp | 1) : (temp & ~1);
+	writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
+}
+
+static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
+{
+	struct ata_host *host = dev_instance;
+	struct s3c_ide_info *info = host->private_data;
+	u32 reg;
+
+	reg = readl(info->ide_addr + S3C_ATA_IRQ);
+	writel(reg, info->ide_addr + S3C_ATA_IRQ);
+
+	return ata_sff_interrupt(irq, dev_instance);
+}
+
+static void pata_s3c_hwinit(struct s3c_ide_info *info,
+				struct s3c_ide_platdata *pdata)
+{
+	switch (info->cpu_type) {
+	case TYPE_S3C64XX:
+		/* Configure as big endian */
+		pata_s3c_cfg_mode(info->sfr_addr);
+		pata_s3c_set_endian(info->ide_addr, 1);
+		pata_s3c_enable(info->ide_addr, true);
+		msleep(100);
+
+		/* Remove IRQ Status */
+		writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
+		writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
+	break;
+
+	case TYPE_S5PC100:
+		pata_s3c_cfg_mode(info->sfr_addr);
+
+	case TYPE_S5PV210:
+		/* Configure as little endian */
+		pata_s3c_set_endian(info->ide_addr, 0);
+		pata_s3c_enable(info->ide_addr, true);
+		msleep(100);
+
+		/* Remove IRQ Status */
+		writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
+		writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
+	break;
+
+	default:
+		BUG();
+	}
+}
+
+static int __devinit pata_s3c_probe(struct platform_device *pdev)
+{
+	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
+	struct device *dev = &pdev->dev;
+	struct s3c_ide_info *info;
+	struct resource *res;
+	struct ata_port *ap;
+	struct ata_host *host;
+	enum s3c_cpu_type cpu_type;
+	int ret;
+
+	cpu_type = platform_get_device_id(pdev)->driver_data;
+
+	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
+	if (!info) {
+		dev_err(dev, "failed to allocate memory for device data\n");
+		return -ENOMEM;
+	}
+
+	info->irq = platform_get_irq(pdev, 0);
+	if (info->irq < 0) {
+		dev_err(dev, "could not obtain irq number\n");
+		return -EINVAL;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(dev, "failed to get mem resource\n");
+		return -EINVAL;
+	}
+
+	if (!devm_request_mem_region(dev, res->start,
+				resource_size(res), DRV_NAME)) {
+		dev_err(dev, "error requesting register region\n");
+		return -EBUSY;
+	}
+
+	info->ide_addr = devm_ioremap(dev, res->start, resource_size(res));
+	if (!info->ide_addr) {
+		dev_err(dev, "failed to map IO base address\n");
+		return -ENOMEM;
+	}
+
+	info->clk = clk_get(&pdev->dev, "cfcon");
+	if (IS_ERR(info->clk)) {
+		dev_err(dev, "failed to get access to cf controller clock\n");
+		ret = PTR_ERR(info->clk);
+		info->clk = NULL;
+		return ret;
+	}
+
+	clk_enable(info->clk);
+
+	/* init ata host */
+	host = ata_host_alloc(dev, 1);
+	if (!host) {
+		dev_err(dev, "failed to allocate ide host\n");
+		ret = -ENOMEM;
+		goto stop_clk;
+	}
+
+	ap = host->ports[0];
+	ap->flags |= ATA_FLAG_MMIO;
+	ap->pio_mask = ATA_PIO4;
+
+	if (cpu_type == TYPE_S3C64XX) {
+		ap->ops = &pata_s3c_port_ops;
+		info->sfr_addr = info->ide_addr + 0x1800;
+		info->ide_addr += 0x1900;
+		info->fifo_status_reg = 0x94;
+	} else if (cpu_type == TYPE_S5PC100) {
+		ap->ops = &pata_s5p_port_ops;
+		info->sfr_addr = info->ide_addr + 0x1800;
+		info->ide_addr += 0x1900;
+		info->fifo_status_reg = 0x84;
+	} else {
+		ap->ops = &pata_s5p_port_ops;
+		info->fifo_status_reg = 0x84;
+	}
+
+	info->cpu_type = cpu_type;
+
+	if (!info->irq) {
+		ap->flags |= ATA_FLAG_PIO_POLLING;
+		ata_port_desc(ap, "no IRQ, using PIO polling\n");
+	}
+
+	ap->ioaddr.cmd_addr =  info->ide_addr + S3C_ATA_CMD;
+	ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
+	ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
+	ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
+	ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
+	ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
+	ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
+	ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
+	ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
+	ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
+	ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
+	ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
+	ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
+
+	ata_port_desc(ap, "mmio cmd 0x%llx ",
+			(unsigned long long)res->start);
+
+	host->private_data = info;
+
+	if (pdata && pdata->setup_gpio)
+		pdata->setup_gpio();
+
+	/* Set endianness and enable the interface */
+	pata_s3c_hwinit(info, pdata);
+
+	platform_set_drvdata(pdev, host);
+
+	return ata_host_activate(host, info->irq,
+			info->irq ? pata_s3c_irq : NULL,
+			0, &pata_s3c_sht);
+
+stop_clk:
+	clk_disable(info->clk);
+	clk_put(info->clk);
+	return ret;
+}
+
+static int __devexit pata_s3c_remove(struct platform_device *pdev)
+{
+	struct ata_host *host = platform_get_drvdata(pdev);
+	struct s3c_ide_info *info;
+
+	info = host->private_data;
+	ata_host_detach(host);
+
+	clk_disable(info->clk);
+	clk_put(info->clk);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int pata_s3c_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ata_host *host = platform_get_drvdata(pdev);
+	pm_message_t state = PMSG_SUSPEND;
+
+	return ata_host_suspend(host, state);
+}
+
+static int pata_s3c_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ata_host *host = platform_get_drvdata(pdev);
+	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
+	struct s3c_ide_info *info;
+
+	info = host->private_data;
+
+	pata_s3c_hwinit(info, pdata);
+	ata_host_resume(host);
+
+	return 0;
+}
+
+static const struct dev_pm_ops pata_s3c_pm_ops = {
+	.suspend	= pata_s3c_suspend,
+	.resume		= pata_s3c_resume,
+};
+#endif
+
+/* driver device registration */
+static struct platform_device_id pata_s3c_driver_ids[] = {
+	{
+		.name		= "s3c64xx-pata",
+		.driver_data	= TYPE_S3C64XX,
+	}, {
+		.name		= "s5pc100-pata",
+		.driver_data	= TYPE_S5PC100,
+	}, {
+		.name		= "s5pv210-pata",
+		.driver_data	= TYPE_S5PV210,
+	},
+	{ }
+};
+
+MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
+
+static struct platform_driver pata_s3c_driver = {
+	.probe		= pata_s3c_probe,
+	.remove		= __devexit_p(pata_s3c_remove),
+	.id_table	= pata_s3c_driver_ids,
+	.driver		= {
+		.name	= DRV_NAME,
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &pata_s3c_pm_ops,
+#endif
+	},
+};
+
+static int __init pata_s3c_init(void)
+{
+	return platform_driver_register(&pata_s3c_driver);
+}
+
+static void __exit pata_s3c_exit(void)
+{
+	platform_driver_unregister(&pata_s3c_driver);
+}
+
+module_init(pata_s3c_init);
+module_exit(pata_s3c_exit);
+
+MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan at samsung.com>");
+MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
-- 
1.6.6.1



From kgene.kim at samsung.com  Mon Jun 14 03:19:43 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 14 Jun 2010 16:19:43 +0900
Subject: [PATCH 2/2 RE-SEND] ARM: S5PV210: Add support HSMMC on Samsung
	SMDKV210
Message-ID: <1276499983-19463-1-git-send-email-kgene.kim@samsung.com>

From: Lee Hyuk <hyuk1.lee at samsung.com>

This patch adds support HSMMC on Samsung SMDKV210, and gpio configuration for
S5PV210 hsmmc3.

Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---

Changes since previous patch:

- Adding missed call s5pv210_default_sdhci3() in s5pv210_map_io()

 arch/arm/mach-s5pv210/Kconfig            |    5 +++++
 arch/arm/mach-s5pv210/cpu.c              |    1 +
 arch/arm/mach-s5pv210/include/mach/map.h |    1 +
 arch/arm/mach-s5pv210/mach-smdkv210.c    |    4 ++++
 arch/arm/mach-s5pv210/setup-sdhci-gpio.c |   20 ++++++++++++++++++++
 5 files changed, 31 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0761eac..6aee967 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -72,9 +72,14 @@ config MACH_SMDKV210
 	select CPU_S5PV210
 	select ARCH_SPARSEMEM_ENABLE
 	select SAMSUNG_DEV_ADC
+	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC1
+	select S3C_DEV_HSMMC2
+	select S3C_DEV_HSMMC3
 	select SAMSUNG_DEV_TS
 	select S3C_DEV_WDT
 	select HAVE_S3C2410_WATCHDOG
+	select S5PV210_SETUP_SDHCI
 	help
 	  Machine support for Samsung SMDKV210
 
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 411a4a9..765034e 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -86,6 +86,7 @@ void __init s5pv210_map_io(void)
 	s5pv210_default_sdhci0();
 	s5pv210_default_sdhci1();
 	s5pv210_default_sdhci2();
+	s5pv210_default_sdhci3();
 
 	/* the i2c devices are directly compatible with s3c2440 */
 	s3c_i2c0_setname("s3c2440-i2c");
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 34eb168..fa9d7c2 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -97,6 +97,7 @@
 #define S3C_PA_HSMMC0		S5PV210_PA_HSMMC(0)
 #define S3C_PA_HSMMC1		S5PV210_PA_HSMMC(1)
 #define S3C_PA_HSMMC2		S5PV210_PA_HSMMC(2)
+#define S3C_PA_HSMMC3		S5PV210_PA_HSMMC(3)
 #define S3C_PA_IIC		S5PV210_PA_IIC0
 #define S3C_PA_IIC1		S5PV210_PA_IIC1
 #define S3C_PA_IIC2		S5PV210_PA_IIC2
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 0d46279..b08f376 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -77,6 +77,10 @@ static struct platform_device *smdkv210_devices[] __initdata = {
 	&s5pv210_device_iis0,
 	&s5pv210_device_ac97,
 	&s3c_device_adc,
+	&s3c_device_hsmmc0,
+	&s3c_device_hsmmc1,
+	&s3c_device_hsmmc2,
+	&s3c_device_hsmmc3,
 	&s3c_device_ts,
 	&s3c_device_wdt,
 };
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
index fe7d86d..415f62c 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
@@ -102,3 +102,23 @@ void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 	s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
 	s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
 }
+
+void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+
+	/* Set all the necessary GPG1[0:2] pins to special-function 2 */
+	for (gpio = S5PV210_GPG3(0); gpio < S5PV210_GPG3(2); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* Data pin GPG1[3:6] to special-function 2 */
+	for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP);
+	s3c_gpio_cfgpin(S5PV210_GPG3(2), S3C_GPIO_SFN(2));
+}
-- 
1.6.2.5



From s.hauer at pengutronix.de  Mon Jun 14 03:35:21 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 14 Jun 2010 09:35:21 +0200
Subject: [GIT PULL] mxc patches
Message-ID: <20100614073521.GY20799@pengutronix.de>

This is basically the same pull request as the last time minus the
defconfig changes.

Sascha

The following changes since commit 7e27d6e778cd87b6f2415515d7127eba53fe5d02:

  Linux 2.6.35-rc3 (2010-06-11 19:14:04 -0700)

are available in the git repository at:
  git://git.pengutronix.de/git/imx/linux-2.6 for-rmk

Amit Kucheria (1):
      arm: mxc: utilise usecount field in clock operations

Baruch Siach (3):
      mxc_nand: add support for platform defined partitions
      mx25: add platform code for imx-keypad
      mx25pdk: add keypad support

Daniel Mack (3):
      ARM: mx3: pcm037: remove unused variable
      ARM: mx3: mx31lilly: fix build error for !CONFIG_USB_ULPI
      ARM: mx3: mx31lilly: pass mc13783 SPI IRQ pin

Dinh Nguyen (2):
      mx5: Add i2c to Freescale MX51 Babbage HW
      mx5: Register i2c on Freescale MX51 Babbage HW

Eric B?nard (14):
      eukrea_mbimx27-baseboard: fix typo in display name
      eukrea_mbimx27-baseboard: add generic-bl and platform-lcd controls
      eukrea_mbimx27-baseboard: add timings for DVI output
      cpuimx27 and mbimx27: allow fine control of UART4 and SDHC2 usage
      mach-cpuimx27: fix QuadUART's IRQ typo in pins'setup
      eukrea_mbimx27: fix ADS7846 support
      mach-cpuimx27: add USB Host2 and OTG support
      mach-cpuimx27: register wdt and w1_master resources
      mxcmmc: add card detect through DAT3 possibility
      eukrea_mbimx27: use card detect through DAT3 for SDHC1
      MX2X: Add Keypad device definition for MX2X arch
      eukrea_mbimx27: add support for the keyboard
      eukrea_mbimx27: add audio codec
      i.MX35: return IPU clock's value for mx3fb

Sascha Hauer (1):
      mxc_nand: Fix OOB handling

Wolfram Sang (1):
      pcm037/pcm043/pca100: fix ULPI-related build warnings

 arch/arm/mach-mx2/Kconfig                    |   10 ++-
 arch/arm/mach-mx2/devices.c                  |   18 +++
 arch/arm/mach-mx2/devices.h                  |    1 +
 arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c |  181 +++++++++++++++++++++++---
 arch/arm/mach-mx2/mach-cpuimx27.c            |   93 +++++++++++++-
 arch/arm/mach-mx2/mach-pca100.c              |    2 +
 arch/arm/mach-mx25/clock.c                   |    2 +-
 arch/arm/mach-mx25/devices.c                 |   20 +++
 arch/arm/mach-mx25/devices.h                 |    1 +
 arch/arm/mach-mx25/mach-mx25pdk.c            |   36 +++++
 arch/arm/mach-mx3/clock-imx35.c              |    2 +-
 arch/arm/mach-mx3/mach-mx31lilly.c           |   34 ++++--
 arch/arm/mach-mx3/mach-pcm037.c              |    3 +-
 arch/arm/mach-mx3/mach-pcm043.c              |    2 +
 arch/arm/mach-mx5/board-mx51_babbage.c       |   26 ++++
 arch/arm/mach-mx5/clock-mx51.c               |   11 ++
 arch/arm/mach-mx5/devices.c                  |   58 ++++++++
 arch/arm/mach-mx5/devices.h                  |    3 +
 arch/arm/plat-mxc/clock.c                    |   37 ++++--
 arch/arm/plat-mxc/include/mach/iomux-mx25.h  |   19 ++-
 arch/arm/plat-mxc/include/mach/iomux-mx51.h  |   18 ++-
 arch/arm/plat-mxc/include/mach/mmc.h         |    3 +
 arch/arm/plat-mxc/include/mach/mx25.h        |    2 +
 arch/arm/plat-mxc/include/mach/mxc_nand.h    |    4 +
 drivers/mmc/host/mxcmmc.c                    |   16 ++-
 drivers/mtd/nand/mxc_nand.c                  |   33 +----
 26 files changed, 545 insertions(+), 90 deletions(-)
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From linux at arm.linux.org.uk  Mon Jun 14 03:38:28 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 14 Jun 2010 08:38:28 +0100
Subject: Request review of device tree documentation
In-Reply-To: <AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com>
References: <AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com>
	<4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<1276408773.1962.574.camel@pasglop>
	<AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com>
Message-ID: <20100614073828.GA6095@n2100.arm.linux.org.uk>

On Sun, Jun 13, 2010 at 11:23:45PM -0600, Grant Likely wrote:
> >> Or perhaps the MMU and caches can be turned off for the duration of the
> >> callback.
> >> I don't have the details of ARM MMUs and caches reloaded into my head
> >> yet. ?Maybe next week...

We've had these kinds of questions in the past.  Doing what you're asking
above is not really an option - it requires:

1. disable all IRQs
2. setup 1:1 MMU mappings for code to turn off MMU
   (requires new page table)
3. disable imprecise exceptions
4. flush caches and TLBS
5. jump to 1:1 mapping area for code to disable MMU
6. disable caches and mmu
7. call function
8. flush caches and TLBs
9. re-enable caches and mmu
10. re-enable imprecise exceptions
11. switch back to original MMU mappings
12. re-enable all IRQs

This is fine if you don't care at all about interrupt latency.
Unfortunately, most people do care about interrupt latency because
that directly affects interactivity and system performance.  The
called function could not enable interrupts or exceptions - as the
CPU vectors are in virtual space, disabling the MMU effectively
makes them disappear.

Moreover, with the MMU and caches disabled, the CPU performance is
extremely poor, so the called function will run slowly.

So, disabling the MMU isn't really viable.

Now, if the external code was fully PIC, we could then run it with
the MMU enabled.  However, this wouldn't really help - the external
code could not access any devices without knowledge of how the kernel
setup the V:P translations.

So you'd need to pass some kind of data structure giving locations of
devices to the called code - but then what if the kernel doesn't have
the device mapped?


From kmpark at infradead.org  Mon Jun 14 03:41:12 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Mon, 14 Jun 2010 16:41:12 +0900
Subject: [PATCH 2/2 RE-SEND] ARM: S5PV210: Add support HSMMC on Samsung 
	SMDKV210
In-Reply-To: <1276499983-19463-1-git-send-email-kgene.kim@samsung.com>
References: <1276499983-19463-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <AANLkTin-IvzeY3QDMskm-G6QWFqddppdYrrkEBldGGsN@mail.gmail.com>

Hi

On Mon, Jun 14, 2010 at 4:19 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> From: Lee Hyuk <hyuk1.lee at samsung.com>
>
> This patch adds support HSMMC on Samsung SMDKV210, and gpio configuration for
> S5PV210 hsmmc3.
>
> Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
>
> Changes since previous patch:
>
> - Adding missed call s5pv210_default_sdhci3() in s5pv210_map_io()
>
>  arch/arm/mach-s5pv210/Kconfig            |    5 +++++
>  arch/arm/mach-s5pv210/cpu.c              |    1 +
>  arch/arm/mach-s5pv210/include/mach/map.h |    1 +
>  arch/arm/mach-s5pv210/mach-smdkv210.c    |    4 ++++
>  arch/arm/mach-s5pv210/setup-sdhci-gpio.c |   20 ++++++++++++++++++++
>  5 files changed, 31 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
> index 0761eac..6aee967 100644
> --- a/arch/arm/mach-s5pv210/Kconfig
> +++ b/arch/arm/mach-s5pv210/Kconfig
> @@ -72,9 +72,14 @@ config MACH_SMDKV210
>        select CPU_S5PV210
>        select ARCH_SPARSEMEM_ENABLE
>        select SAMSUNG_DEV_ADC
> +       select S3C_DEV_HSMMC
> +       select S3C_DEV_HSMMC1
> +       select S3C_DEV_HSMMC2
> +       select S3C_DEV_HSMMC3
>        select SAMSUNG_DEV_TS
>        select S3C_DEV_WDT
>        select HAVE_S3C2410_WATCHDOG
> +       select S5PV210_SETUP_SDHCI
>        help
>          Machine support for Samsung SMDKV210
>
> diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
> index 411a4a9..765034e 100644
> --- a/arch/arm/mach-s5pv210/cpu.c
> +++ b/arch/arm/mach-s5pv210/cpu.c
> @@ -86,6 +86,7 @@ void __init s5pv210_map_io(void)
>        s5pv210_default_sdhci0();
>        s5pv210_default_sdhci1();
>        s5pv210_default_sdhci2();
> +       s5pv210_default_sdhci3();
>
>        /* the i2c devices are directly compatible with s3c2440 */
>        s3c_i2c0_setname("s3c2440-i2c");
> diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
> index 34eb168..fa9d7c2 100644
> --- a/arch/arm/mach-s5pv210/include/mach/map.h
> +++ b/arch/arm/mach-s5pv210/include/mach/map.h
> @@ -97,6 +97,7 @@
>  #define S3C_PA_HSMMC0          S5PV210_PA_HSMMC(0)
>  #define S3C_PA_HSMMC1          S5PV210_PA_HSMMC(1)
>  #define S3C_PA_HSMMC2          S5PV210_PA_HSMMC(2)
> +#define S3C_PA_HSMMC3          S5PV210_PA_HSMMC(3)
>  #define S3C_PA_IIC             S5PV210_PA_IIC0
>  #define S3C_PA_IIC1            S5PV210_PA_IIC1
>  #define S3C_PA_IIC2            S5PV210_PA_IIC2
> diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
> index 0d46279..b08f376 100644
> --- a/arch/arm/mach-s5pv210/mach-smdkv210.c
> +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
> @@ -77,6 +77,10 @@ static struct platform_device *smdkv210_devices[] __initdata = {
>        &s5pv210_device_iis0,
>        &s5pv210_device_ac97,
>        &s3c_device_adc,
> +       &s3c_device_hsmmc0,
> +       &s3c_device_hsmmc1,
> +       &s3c_device_hsmmc2,
> +       &s3c_device_hsmmc3,
>        &s3c_device_ts,
>        &s3c_device_wdt,
>  };
> diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
> index fe7d86d..415f62c 100644
> --- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
> +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
> @@ -102,3 +102,23 @@ void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
>        s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
>        s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
>  }
> +
> +void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
> +{
> +       unsigned int gpio;
> +
> +       /* Set all the necessary GPG1[0:2] pins to special-function 2 */

Wrong pin name, GPG3?

> +       for (gpio = S5PV210_GPG3(0); gpio < S5PV210_GPG3(2); gpio++) {
> +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> +       }
> +
> +       /* Data pin GPG1[3:6] to special-function 2 */
ditto
> +       for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) {
> +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> +       }
> +
> +       s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP);
> +       s3c_gpio_cfgpin(S5PV210_GPG3(2), S3C_GPIO_SFN(2));

In case of this, how about to use one loop like this.

for (gpio = GPG3(0); gpio <= GPG3(7); gpio++)
    s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));

since all pins use special function 2.

or others methods are welcome.

To Ben,
When do you apply previous gpio helper functions?

Thank you,
Kyungmin Park


> +}
> --
> 1.6.2.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>


From wmb at firmworks.com  Mon Jun 14 03:45:50 2010
From: wmb at firmworks.com (Mitch Bradley)
Date: Sun, 13 Jun 2010 21:45:50 -1000
Subject: Request review of device tree documentation
In-Reply-To: <20100614073828.GA6095@n2100.arm.linux.org.uk>
References: <AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com>
	<4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<1276408773.1962.574.camel@pasglop>
	<AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com>
	<20100614073828.GA6095@n2100.arm.linux.org.uk>
Message-ID: <4C15DE2E.1050905@firmworks.com>

Russell King - ARM Linux wrote:
> On Sun, Jun 13, 2010 at 11:23:45PM -0600, Grant Likely wrote:
>   
>>>> Or perhaps the MMU and caches can be turned off for the duration of the
>>>> callback.
>>>> I don't have the details of ARM MMUs and caches reloaded into my head
>>>> yet.  Maybe next week...
>>>>         
>
> We've had these kinds of questions in the past.  Doing what you're asking
> above is not really an option - it requires:
>
> 1. disable all IRQs
> 2. setup 1:1 MMU mappings for code to turn off MMU
>    (requires new page table)
> 3. disable imprecise exceptions
> 4. flush caches and TLBS
> 5. jump to 1:1 mapping area for code to disable MMU
> 6. disable caches and mmu
> 7. call function
> 8. flush caches and TLBs
> 9. re-enable caches and mmu
> 10. re-enable imprecise exceptions
> 11. switch back to original MMU mappings
> 12. re-enable all IRQs
>
> This is fine if you don't care at all about interrupt latency.
> Unfortunately, most people do care about interrupt latency because
> that directly affects interactivity and system performance.  The
> called function could not enable interrupts or exceptions - as the
> CPU vectors are in virtual space, disabling the MMU effectively
> makes them disappear.
>
> Moreover, with the MMU and caches disabled, the CPU performance is
> extremely poor, so the called function will run slowly.
>
> So, disabling the MMU isn't really viable.
>   

None of this is a deal-breaker for the kind of debugging tasks that are 
the primary use case for the callback.

> Now, if the external code was fully PIC, we could then run it with
> the MMU enabled.  However, this wouldn't really help - the external
> code could not access any devices without knowledge of how the kernel
> setup the V:P translations.
>
> So you'd need to pass some kind of data structure giving locations of
> devices to the called code - but then what if the kernel doesn't have
> the device mapped?
>
>   


From kgene.kim at samsung.com  Mon Jun 14 03:58:51 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Mon, 14 Jun 2010 16:58:51 +0900
Subject: [PATCH 2/2 RE-SEND] ARM: S5PV210: Add support HSMMC on Samsung
	SMDKV210
In-Reply-To: <AANLkTin-IvzeY3QDMskm-G6QWFqddppdYrrkEBldGGsN@mail.gmail.com>
References: <1276499983-19463-1-git-send-email-kgene.kim@samsung.com>
	<AANLkTin-IvzeY3QDMskm-G6QWFqddppdYrrkEBldGGsN@mail.gmail.com>
Message-ID: <009c01cb0b97$7265ea00$5731be00$%kim@samsung.com>

Kyungmin Park wrote:
> 
> Hi
> 
Hi, :-)

> On Mon, Jun 14, 2010 at 4:19 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > From: Lee Hyuk <hyuk1.lee at samsung.com>
> >
> > This patch adds support HSMMC on Samsung SMDKV210, and gpio
> configuration for
> > S5PV210 hsmmc3.
> >
> > Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> > ---
> >
> > Changes since previous patch:
> >
> > - Adding missed call s5pv210_default_sdhci3() in s5pv210_map_io()
> >
> >  arch/arm/mach-s5pv210/Kconfig            |    5 +++++
> >  arch/arm/mach-s5pv210/cpu.c              |    1 +
> >  arch/arm/mach-s5pv210/include/mach/map.h |    1 +
> >  arch/arm/mach-s5pv210/mach-smdkv210.c    |    4 ++++
> >  arch/arm/mach-s5pv210/setup-sdhci-gpio.c |   20 ++++++++++++++++++++
> >  5 files changed, 31 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-s5pv210/Kconfig
b/arch/arm/mach-s5pv210/Kconfig
> > index 0761eac..6aee967 100644
> > --- a/arch/arm/mach-s5pv210/Kconfig
> > +++ b/arch/arm/mach-s5pv210/Kconfig
> > @@ -72,9 +72,14 @@ config MACH_SMDKV210
> >        select CPU_S5PV210
> >        select ARCH_SPARSEMEM_ENABLE
> >        select SAMSUNG_DEV_ADC
> > +       select S3C_DEV_HSMMC
> > +       select S3C_DEV_HSMMC1
> > +       select S3C_DEV_HSMMC2
> > +       select S3C_DEV_HSMMC3
> >        select SAMSUNG_DEV_TS
> >        select S3C_DEV_WDT
> >        select HAVE_S3C2410_WATCHDOG
> > +       select S5PV210_SETUP_SDHCI
> >        help
> >          Machine support for Samsung SMDKV210
> >
> > diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
> > index 411a4a9..765034e 100644
> > --- a/arch/arm/mach-s5pv210/cpu.c
> > +++ b/arch/arm/mach-s5pv210/cpu.c
> > @@ -86,6 +86,7 @@ void __init s5pv210_map_io(void)
> >        s5pv210_default_sdhci0();
> >        s5pv210_default_sdhci1();
> >        s5pv210_default_sdhci2();
> > +       s5pv210_default_sdhci3();
> >
> >        /* the i2c devices are directly compatible with s3c2440 */
> >        s3c_i2c0_setname("s3c2440-i2c");
> > diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-
> s5pv210/include/mach/map.h
> > index 34eb168..fa9d7c2 100644
> > --- a/arch/arm/mach-s5pv210/include/mach/map.h
> > +++ b/arch/arm/mach-s5pv210/include/mach/map.h
> > @@ -97,6 +97,7 @@
> >  #define S3C_PA_HSMMC0          S5PV210_PA_HSMMC(0)
> >  #define S3C_PA_HSMMC1          S5PV210_PA_HSMMC(1)
> >  #define S3C_PA_HSMMC2          S5PV210_PA_HSMMC(2)
> > +#define S3C_PA_HSMMC3          S5PV210_PA_HSMMC(3)
> >  #define S3C_PA_IIC             S5PV210_PA_IIC0
> >  #define S3C_PA_IIC1            S5PV210_PA_IIC1
> >  #define S3C_PA_IIC2            S5PV210_PA_IIC2
> > diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-
> s5pv210/mach-smdkv210.c
> > index 0d46279..b08f376 100644
> > --- a/arch/arm/mach-s5pv210/mach-smdkv210.c
> > +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
> > @@ -77,6 +77,10 @@ static struct platform_device *smdkv210_devices[]
> __initdata = {
> >        &s5pv210_device_iis0,
> >        &s5pv210_device_ac97,
> >        &s3c_device_adc,
> > +       &s3c_device_hsmmc0,
> > +       &s3c_device_hsmmc1,
> > +       &s3c_device_hsmmc2,
> > +       &s3c_device_hsmmc3,
> >        &s3c_device_ts,
> >        &s3c_device_wdt,
> >  };
> > diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-
> s5pv210/setup-sdhci-gpio.c
> > index fe7d86d..415f62c 100644
> > --- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
> > +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
> > @@ -102,3 +102,23 @@ void s5pv210_setup_sdhci2_cfg_gpio(struct
> platform_device *dev, int width)
> >        s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
> >        s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
> >  }
> > +
> > +void s5pv210_setup_sdhci3_cfg_gpio(struct platform_device *dev, int
width)
> > +{
> > +       unsigned int gpio;
> > +
> > +       /* Set all the necessary GPG1[0:2] pins to special-function 2 */
> 
> Wrong pin name, GPG3?
> 
OK.

> > +       for (gpio = S5PV210_GPG3(0); gpio < S5PV210_GPG3(2); gpio++) {
> > +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> > +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> > +       }
> > +
> > +       /* Data pin GPG1[3:6] to special-function 2 */
> ditto

OK.

> > +       for (gpio = S5PV210_GPG3(3); gpio <= S5PV210_GPG3(6); gpio++) {
> > +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> > +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> > +       }
> > +
> > +       s3c_gpio_setpull(S5PV210_GPG3(2), S3C_GPIO_PULL_UP);
> > +       s3c_gpio_cfgpin(S5PV210_GPG3(2), S3C_GPIO_SFN(2));
> 
> In case of this, how about to use one loop like this.
> 
> for (gpio = GPG3(0); gpio <= GPG3(7); gpio++)
>     s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> 
> since all pins use special function 2.
> 
> or others methods are welcome.
> 

Yeah, you're right.
But used same method of s5pv210_sdhci0_cfg_gpio(), sdhci1_xxx(), and
sdhci2_xxx() from Marek.

If necessary, will modify later with others.

> To Ben,
> When do you apply previous gpio helper functions?
> 
What's the previous gpio helper functions for?


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From u.kleine-koenig at pengutronix.de  Mon Jun 14 04:32:14 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 14 Jun 2010 10:32:14 +0200
Subject: ARM defconfig files
In-Reply-To: <alpine.LFD.2.00.1006031119440.8175@i5.linux-foundation.org>
References: <20100603074548.GA12104@flint.arm.linux.org.uk>
	<alpine.LFD.2.00.1006030725420.8175@i5.linux-foundation.org>
	<20100603181010.GA25779@flint.arm.linux.org.uk>
	<1275589230.23384.19.camel@c-dwalke-linux.qualcomm.com>
	<alpine.LFD.2.00.1006031119440.8175@i5.linux-foundation.org>
Message-ID: <20100614083214.GA2104@pengutronix.de>

Hello,

[Added linux-arm-kernel ML to Cc, note that it's moderated for
non-subscribers.]

On Thu, Jun 03, 2010 at 11:21:59AM -0700, Linus Torvalds wrote:
> 
> 
> On Thu, 3 Jun 2010, Daniel Walker wrote:
> > 
> > I don't see how we can do without defconfigs altogether tho. I mean , if
> > you want to run a Beagle board or a Nexus one we can't just give the
> > users a slim ARM config and let them troll through 1000's of drivers
> > trying to find just those ones that work on their given board.
> 
> Well, you also don't need the full defconfig's with the kernel.
> 
> Right now they are just noise. They actually _hide_ things, because 
> diffstat (and dirstat) information becomes pointless, and the diffs become 
> totally unreadable by any human (trust me - when the choice is between 
> "search for next relevant diff" or "blast it, I can't be bothered with 
> walking through this crap", quite often the choice is the latter).
I wrote a script that throws out all unneeded lines in all arm
defconfigs that don't influence the resulting .config for .34 and
.35-rc1 and compared .34<->.35-rc with .34-reduced<->.35-rc1-reduced.

Here are the results:

	$ git diff --dirstat v2.6.34 v2.6.35-rc1 arch/arm
	  11.8% arch/arm/configs/
	  10.0% arch/arm/mach-msm/
	  10.8% arch/arm/mach-omap2/
	   4.8% arch/arm/mach-pxa/
	   4.5% arch/arm/mach-s5pc100/
	   3.3% arch/arm/mach-s5pv210/
	   4.4% arch/arm/mach-spear3xx/
	   3.1% arch/arm/mach-ux500/
	   5.1% arch/arm/plat-s5pc1xx/
	   3.1% arch/arm/plat-samsung/
	  38.2% arch/arm/

	$ git diff --dirstat arm/defconfig/reduced-v2.6.34 arm/defconfig/reduced-v2.6.35-rc1 arch/arm
	   3.1% arch/arm/mach-davinci/
	  11.3% arch/arm/mach-msm/
	  12.2% arch/arm/mach-omap2/
	   5.4% arch/arm/mach-pxa/
	   5.1% arch/arm/mach-s5pc100/
	   3.7% arch/arm/mach-s5pv210/
	   5.0% arch/arm/mach-spear3xx/
	   3.5% arch/arm/mach-ux500/
	   5.8% arch/arm/plat-s5pc1xx/
	   3.5% arch/arm/plat-samsung/
	  40.9% arch/arm/

	$ git diff --dirstat=0 arm/defconfig/reduced-v2.6.34 arm/defconfig/reduced-v2.6.35-rc1 arch/arm | grep config
	   1.1% arch/arm/configs/

	$ git diff --shortstat v2.6.35-rc1 arm/defconfig/reduced-v2.6.35-rc1
	 177 files changed, 652 insertions(+), 194157 deletions(-)

(The insertions above are only moved lines I think, I didn't check them
all.)

The branches arm/defconfig/reduced-v2.6.34 and
arm/defconfig/reduced-v2.6.35-rc1 are available at my repo at
git://git.pengutronix.de/git/ukl/linux-2.6.git .  (There is a gitweb at
http://git.pengutronix.de/?p=ukl/linux-2.6.git)

So maintaining these minimal defconfigs would have reduced the defconfig
noise from 11.8% down to 1.1%.  And probably it could be considerably
reduced further with constructs like:

	config HAVE_MTD_NAND_MXC
		bool

	config MTD_NAND_MXC
		tristate "MXC NAND support"
		...
		default m if HAVE_MTD_NAND_MXC
		help
		  ...

	...
	config MACH_MX27ADS
		...
		select HAVE_MTD_NAND_MXC

.  Compared with selecting everything in Kconfig files this approach
allows further tweaking of a config.  (E.g. "I have a mx27ads machine,
but I don't need nand support.")  Compared with the SAT-Solver it's an
idea that works today.

One downside of this approach (when done with my script only) is that
too much is removed.  E.g. in mx3_defconfig CONFIG_ARCH_MX3 is removed.
This is OK from a logical POV but then changing the default of the
corresponding choice (and I intend to do that in the near future) would
break this defconfig.

I can share my script and I'm willing to support maintaining the
minimality of the defconfig files if they are an acceptable (maybe
intermediate) step for Linus.

Together with the efforts to reduce the number of defconfigs as thought
about in other mails of this thread the situation should become quite
better for Linus.  (I'm currently working on merging support for all
Freescale SoCs into a single mach- directory and so merge mx1_defconfig,
mx21_defconfig, mx27_defconfig, mx31pdk_defconfig, mx3_defconfig and
mx51_defconfig.)

Linus: I would really appreciate if you wouldn't remove all (or nearly
all) defconfig files.  I think you would force a quicker solution to
this problem, but during that time the ARM community would loose compile
coverage.

Thoughts on this?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From myungjoo.ham at samsung.com  Mon Jun 14 04:39:09 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Mon, 14 Jun 2010 17:39:09 +0900
Subject: [PATCH 0/6] S5PV210 PM Support (suspend-to-mem)
Message-ID: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>

This patch set supports S5PV210/S5PC110 PM (suspend-to-mem).

MyungJoo Ham (8):
  S5PV210 Add IRQ/EINT register information for the CPU.
  S5PV210 add clock registers for the CPU.
  S5PV210 added register mappings
  S5PV210 GPIO relataed registers are added.
  S5PV210 added EINT-GPIO register mappings
  S5PV210 PM Support (suspend-to-mem)

 arch/arm/mach-s5pv210/Makefile                  |    4 +
 arch/arm/mach-s5pv210/include/mach/irqs.h       |    9 +
 arch/arm/mach-s5pv210/include/mach/map.h        |   45 +++
 arch/arm/mach-s5pv210/include/mach/regs-clock.h |  467 ++++++++++++++++++++++-
 arch/arm/mach-s5pv210/include/mach/regs-gpio.h  |  121 ++++++
 arch/arm/mach-s5pv210/include/mach/regs-irq.h   |    6 +
 arch/arm/plat-s5p/Makefile                      |    3 +
 arch/arm/plat-s5p/include/plat/gpio-ext.h       |   44 +++
 arch/arm/plat-s5p/include/plat/map-s5p.h        |    1 +
 arch/arm/plat-s5p/sleep.S                       |  248 ++++++++++++
 arch/arm/plat-samsung/include/plat/pm-core.h    |   53 +++
 arch/arm/plat-samsung/include/plat/pm.h         |   13 +
 arch/arm/plat-samsung/pm-gpio.c                 |    4 +-
 arch/arm/plat-samsung/pm.c                      |   75 ++++-
 14 files changed, 1082 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/plat-s5p/include/plat/gpio-ext.h
 create mode 100644 arch/arm/plat-s5p/sleep.S
 create mode 100644 arch/arm/plat-samsung/include/plat/pm-core.h



From myungjoo.ham at samsung.com  Mon Jun 14 04:39:14 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Mon, 14 Jun 2010 17:39:14 +0900
Subject: [PATCH 5/6] S5PV210 added EINT-GPIO register mappings
In-Reply-To: <1276504755-24741-5-git-send-email-MyungJoo.Ham@samsung.com>
References: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-2-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-3-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-4-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-5-git-send-email-MyungJoo.Ham@samsung.com>
Message-ID: <1276504755-24741-6-git-send-email-MyungJoo.Ham@samsung.com>


Signed-off-by: MyungJoo Ham <MyungJoo.Ham at samsung.com>
---
 arch/arm/plat-s5p/include/plat/gpio-ext.h |   44 +++++++++++++++++++++++++++++
 1 files changed, 44 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-s5p/include/plat/gpio-ext.h

diff --git a/arch/arm/plat-s5p/include/plat/gpio-ext.h b/arch/arm/plat-s5p/include/plat/gpio-ext.h
new file mode 100644
index 0000000..b298335
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/gpio-ext.h
@@ -0,0 +1,44 @@
+/* linux/arch/arm/plat-s5p/include/plat/gpio-eint.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *
+ * External Interrupt (GPH0 ~ GPH3) control register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#define S5P_WKUP_INT_CON0_7		(S5P_EINT_BASE + 0x0)
+#define S5P_WKUP_INT_CON8_15		(S5P_EINT_BASE + 0x4)
+#define S5P_WKUP_INT_CON16_23		(S5P_EINT_BASE + 0x8)
+#define S5P_WKUP_INT_CON24_31		(S5P_EINT_BASE + 0xC)
+#define S5P_WKUP_INT_CON(x)		(S5P_WKUP_INT_CON0_7 + (x * 0x4))
+
+#define S5P_WKUP_INT_FLTCON0_3		(S5P_EINT_BASE + 0x80)
+#define S5P_WKUP_INT_FLTCON4_7		(S5P_EINT_BASE + 0x84)
+#define S5P_WKUP_INT_FLTCON8_11		(S5P_EINT_BASE + 0x88)
+#define S5P_WKUP_INT_FLTCON12_15	(S5P_EINT_BASE + 0x8C)
+#define S5P_WKUP_INT_FLTCON16_19	(S5P_EINT_BASE + 0x90)
+#define S5P_WKUP_INT_FLTCON20_23	(S5P_EINT_BASE + 0x94)
+#define S5P_WKUP_INT_FLTCON24_27	(S5P_EINT_BASE + 0x98)
+#define S5P_WKUP_INT_FLTCON28_31	(S5P_EINT_BASE + 0x9C)
+#define S5P_WKUP_INT_FLTCON(x)		(S5P_WKUP_INT_FLTCON0_3 + (x * 0x4))
+
+#define S5P_WKUP_INT_MASK0_7		(S5P_EINT_BASE + 0x100)
+#define S5P_WKUP_INT_MASK8_15		(S5P_EINT_BASE + 0x104)
+#define S5P_WKUP_INT_MASK16_23		(S5P_EINT_BASE + 0x108)
+#define S5P_WKUP_INT_MASK24_31		(S5P_EINT_BASE + 0x10C)
+#define S5P_WKUP_INT_MASK(x)		(S5P_WKUP_INT_MASK0_7 + (x * 0x4))
+
+#define S5P_WKUP_INT_PEND0_7		(S5P_EINT_BASE + 0x140)
+#define S5P_WKUP_INT_PEND8_15		(S5P_EINT_BASE + 0x144)
+#define S5P_WKUP_INT_PEND16_23		(S5P_EINT_BASE + 0x148)
+#define S5P_WKUP_INT_PEND24_31		(S5P_EINT_BASE + 0x14C)
+#define S5P_WKUP_INT_PEND(x)		(S5P_WKUP_INT_PEND0_7 + (x * 0x4))
+
+#define S5P_WKUP_INT_LOWLEV		(0x00)
+#define S5P_WKUP_INT_HILEV		(0x01)
+#define S5P_WKUP_INT_FALLEDGE		(0x02)
+#define S5P_WKUP_INT_RISEEDGE		(0x03)
+#define S5P_WKUP_INT_BOTHEDGE		(0x04)
-- 
1.6.3.3



From myungjoo.ham at samsung.com  Mon Jun 14 04:39:10 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Mon, 14 Jun 2010 17:39:10 +0900
Subject: [PATCH 1/6] S5PV210 Add IRQ/EINT register information for the CPU.
In-Reply-To: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>
References: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>
Message-ID: <1276504755-24741-2-git-send-email-MyungJoo.Ham@samsung.com>


Signed-off-by: MyungJoo Ham <MyungJoo.Ham at samsung.com>
---
 arch/arm/mach-s5pv210/include/mach/irqs.h     |    9 +++++++++
 arch/arm/mach-s5pv210/include/mach/regs-irq.h |    6 ++++++
 2 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 9689537..6c5f491 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -118,9 +118,18 @@
 #define IRQ_MDNIE3		S5P_IRQ_VIC3(8)
 #define IRQ_VIC_END		S5P_IRQ_VIC3(31)
 
+/* External interrupt */
+
 #define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))
 #define S5P_EINT_BASE2		(IRQ_VIC_END + 1)
 
+#define S5P_EINT(x)             (S5P_EINT_BASE2 + ((x) - 16))
+#define IRQ_EINT_BIT(x) ((x) < IRQ_EINT16_31 ? (x) - S5P_VIC0_BASE : (x) - S5P_EINT(0))
+
+/* GPIO interrupt */
+#define S5P_IRQ_GPIO_BASE       (IRQ_EINT(31) + 1)
+#define S5P_IRQ_GPIO(x)         (S5P_IRQ_GPIO_BASE + (x))
+
 /* Set the default NR_IRQS */
 #define NR_IRQS			(IRQ_EINT(31) + 1)
 
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach-s5pv210/include/mach/regs-irq.h
index 5c3b104..139604f 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-irq.h
@@ -16,4 +16,10 @@
 #include <asm/hardware/vic.h>
 #include <mach/map.h>
 
+/* interrupt controller */
+#define S5PV210_VIC0REG(x)                      ((x) + VA_VIC0)
+#define S5PV210_VIC1REG(x)                      ((x) + VA_VIC1)
+#define S5PV210_VIC2REG(x)                      ((x) + VA_VIC2)
+#define S5PV210_VIC3REG(x)                      ((x) + VA_VIC3)
+
 #endif /* __ASM_ARCH_REGS_IRQ_H */
-- 
1.6.3.3



From myungjoo.ham at samsung.com  Mon Jun 14 04:39:11 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Mon, 14 Jun 2010 17:39:11 +0900
Subject: [PATCH 2/6] S5PV210 add clock registers for the CPU.
In-Reply-To: <1276504755-24741-2-git-send-email-MyungJoo.Ham@samsung.com>
References: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-2-git-send-email-MyungJoo.Ham@samsung.com>
Message-ID: <1276504755-24741-3-git-send-email-MyungJoo.Ham@samsung.com>

	Besides, renamed a register name "BUS0" into "IP5" as EVT1 uses
"IP5" instead of BUS0 (of EVT0)

Signed-off-by: MyungJoo Ham <MyungJoo.Ham at samsung.com>
---
 arch/arm/mach-s5pv210/include/mach/regs-clock.h |  467 ++++++++++++++++++++++-
 1 files changed, 465 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
index 2a25ab4..9652338 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -25,6 +25,8 @@
 #define S5P_APLL_CON		S5P_CLKREG(0x100)
 #define S5P_MPLL_CON		S5P_CLKREG(0x108)
 #define S5P_EPLL_CON		S5P_CLKREG(0x110)
+#define S5P_EPLL_CON1		S5P_CLKREG(0x114)
+#define S5P_EPLL_CON1_MASK	(0xFFFF << 0)
 #define S5P_VPLL_CON		S5P_CLKREG(0x120)
 
 #define S5P_CLK_SRC0		S5P_CLKREG(0x200)
@@ -63,14 +65,139 @@
 #define S5P_CLKGATE_IP4		S5P_CLKREG(0x470)
 
 #define S5P_CLKGATE_BLOCK	S5P_CLKREG(0x480)
-#define S5P_CLKGATE_BUS0	S5P_CLKREG(0x484)
+#define S5P_CLKGATE_IP5		S5P_CLKREG(0x484)
 #define S5P_CLKGATE_BUS1	S5P_CLKREG(0x488)
 #define S5P_CLK_OUT		S5P_CLKREG(0x500)
+#define S5P_CLK_DIV_STAT0   S5P_CLKREG(0x1000)
+#define S5P_CLK_DIV_STAT1   S5P_CLKREG(0x1004)
+#define S5P_CLK_MUX_STAT0   S5P_CLKREG(0x1100)
+#define S5P_CLK_MUX_STAT1   S5P_CLKREG(0x1104)
+#define S5P_MIXER_OUT_SEL	S5P_CLKREG(0x7004)
+#define S5P_MDNIE_SEL		S5P_CLKREG(0x7008)
+#define S5P_MIPI_PHY_CON0	S5P_CLKREG(0x7200)
+#define S5P_MIPI_PHY_CON1	S5P_CLKREG(0x7204)
+
+#define S5P_DCGIDX_MAP0		S5P_CLKREG(0x3000)
+#define S5P_DCGIDX_MAP1		S5P_CLKREG(0x3004)
+#define S5P_DCGIDX_MAP2		S5P_CLKREG(0x3008)
+#define S5P_DCGPERF_MAP0	S5P_CLKREG(0x3020)
+#define S5P_DCGPERF_MAP1	S5P_CLKREG(0x3024)
+#define S5P_DVCIDX_MAP		S5P_CLKREG(0x3040)
+#define S5P_FREQ_CPU		S5P_CLKREG(0x3060)
+#define S5P_FREQ_DPM		S5P_CLKREG(0x3064)
+#define S5P_DVSEMCLK_EN		S5P_CLKREG(0x3080)
+#define S5P_MAXPERF		S5P_CLKREG(0x3084)
+
+#define S5P_EPLL_EN     (1<<31)
+#define S5P_EPLL_MASK   0xffffffff
+#define S5P_EPLLVAL(_v,_m,_p,_s)   ((_v) << 27 | (_m) << 16 | ((_p) << 8) | ((_s)))
 
 /* CLKSRC0 */
+#define S5P_CLKSRC0_APLL_MASK		(0x1<<0)
+#define S5P_CLKSRC0_APLL_SHIFT		(0)
+#define S5P_CLKSRC0_MPLL_MASK		(0x1<<4)
+#define S5P_CLKSRC0_MPLL_SHIFT		(4)
+#define S5P_CLKSRC0_EPLL_MASK		(0x1<<8)
+#define S5P_CLKSRC0_EPLL_SHIFT		(8)
+#define S5P_CLKSRC0_VPLL_MASK		(0x1<<12)
+#define S5P_CLKSRC0_VPLL_SHIFT		(12)
 #define S5P_CLKSRC0_MUX200_MASK		(0x1<<16)
+#define S5P_CLKSRC0_MUX200_SHIFT	(16)
 #define S5P_CLKSRC0_MUX166_MASK		(0x1<<20)
+#define S5P_CLKSRC0_MUX166_SHIFT	(20)
 #define S5P_CLKSRC0_MUX133_MASK		(0x1<<24)
+#define S5P_CLKSRC0_MUX133_SHIFT	(24)
+#define S5P_CLKSRC0_ONENAND_MASK	(0x1<<28)
+#define S5P_CLKSRC0_ONENAND_SHIFT	(28)
+
+/* CLKSRC1 */
+#define S5P_CLKSRC1_HDMI_MASK		(0x1<<0)
+#define S5P_CLKSRC1_HDMI_SHIFT		(0)
+#define S5P_CLKSRC1_MIXER_MASK		(0x1<<4)
+#define S5P_CLKSRC1_MIXER_SHIFT		(4)
+#define S5P_CLKSRC1_DAC_MASK		(0x1<<8)
+#define S5P_CLKSRC1_DAC_SHIFT		(8)
+#define S5P_CLKSRC1_CAM0_MASK		(0xF<<12)
+#define S5P_CLKSRC1_CAM0_SHIFT		(12)
+#define S5P_CLKSRC1_CAM1_MASK		(0xF<<16)
+#define S5P_CLKSRC1_CAM1_SHIFT		(16)
+#define S5P_CLKSRC1_FIMD_MASK		(0xF<<20)
+#define S5P_CLKSRC1_FIMD_SHIFT		(20)
+#define S5P_CLKSRC1_CSIS_MASK		(0xF<<24)
+#define S5P_CLKSRC1_CSIS_SHIFT		(24)
+#define S5P_CLKSRC1_VPLLSRC_MASK	(0x1<<28)
+#define S5P_CLKSRC1_VPLLSRC_SHIFT	(28)
+
+/* CLKSRC2 */
+#define S5P_CLKSRC2_G3D_MASK		(0x3<<0)
+#define S5P_CLKSRC2_G3D_SHIFT		(0)
+#define S5P_CLKSRC2_MFC_MASK		(0x3<<4)
+#define S5P_CLKSRC2_MFC_SHIFT		(4)
+#define S5P_CLKSRC2_G2D_MASK		(0x3<<8)
+#define S5P_CLKSRC2_G2D_SHIFT		(8)
+
+/* CLKSRC3 */
+#define S5P_CLKSRC3_MDNIE_MASK		(0xF<<0)
+#define S5P_CLKSRC3_MDNIE_SHIFT		(0)
+#define S5P_CLKSRC3_MDNIE_PWMCLK_MASK	(0xF<<4)
+#define S5P_CLKSRC3_MDNIE_PWMCLK_SHIFT	(4)
+#define S5P_CLKSRC3_FIMC0_LCLK_MASK	(0xF<<12)
+#define S5P_CLKSRC3_FIMC0_LCLK_SHIFT	(12)
+#define S5P_CLKSRC3_FIMC1_LCLK_MASK	(0xF<<16)
+#define S5P_CLKSRC3_FIMC1_LCLK_SHIFT	(16)
+#define S5P_CLKSRC3_FIMC2_LCLK_MASK	(0xF<<20)
+#define S5P_CLKSRC3_FIMC2_LCLK_SHIFT	(20)
+
+/* CLKSRC4 */
+#define S5P_CLKSRC4_MMC0_MASK		(0xF<<0)
+#define S5P_CLKSRC4_MMC0_SHIFT		(0)
+#define S5P_CLKSRC4_MMC1_MASK		(0xF<<4)
+#define S5P_CLKSRC4_MMC1_SHIFT		(4)
+#define S5P_CLKSRC4_MMC2_MASK		(0xF<<8)
+#define S5P_CLKSRC4_MMC2_SHIFT		(8)
+#define S5P_CLKSRC4_MMC3_MASK		(0xF<<12)
+#define S5P_CLKSRC4_MMC3_SHIFT		(12)
+#define S5P_CLKSRC4_UART0_MASK		(0xF<<16)
+#define S5P_CLKSRC4_UART0_SHIFT		(16)
+#define S5P_CLKSRC4_UART1_MASK		(0xF<<20)
+#define S5P_CLKSRC4_UART1_SHIFT		(20)
+#define S5P_CLKSRC4_UART2_MASK		(0xF<<24)
+#define S5P_CLKSRC4_UART2_SHIFT		(24)
+#define S5P_CLKSRC4_UART3_MASK		(0xF<<28)
+#define S5P_CLKSRC4_UART3_SHIFT		(28)
+
+/* CLKSRC5 */
+#define S5P_CLKSRC5_SPI0_MASK		(0xF<<0)
+#define S5P_CLKSRC5_SPI0_SHIFT		(0)
+#define S5P_CLKSRC5_SPI1_MASK		(0xF<<4)
+#define S5P_CLKSRC5_SPI1_SHIFT		(4)
+#define S5P_CLKSRC5_SPI2_MASK		(0xF<<8)
+#define S5P_CLKSRC5_SPI2_SHIFT		(8)
+#define S5P_CLKSRC5_PWM_MASK		(0xF<<12)
+#define S5P_CLKSRC5_PWM_SHIFT		(12)
+
+/* CLKSRC6 */
+#define S5P_CLKSRC6_AUDIO0_MASK		(0xF<<0)
+#define S5P_CLKSRC6_AUDIO0_SHIFT	(0)
+#define S5P_CLKSRC6_AUDIO1_MASK		(0xF<<4)
+#define S5P_CLKSRC6_AUDIO1_SHIFT	(4)
+#define S5P_CLKSRC6_AUDIO2_MASK		(0xF<<8)
+#define S5P_CLKSRC6_AUDIO2_SHIFT	(8)
+#define S5P_CLKSRC6_SPDIF_MASK		(0x3<<12)
+#define S5P_CLKSRC6_SPDIF_SHIFT		(12)
+#define S5P_CLKSRC6_HPM_MASK		(0x1<<16)
+#define S5P_CLKSRC6_HPM_SHIFT		(16)
+#define S5P_CLKSRC6_PWI_MASK		(0xF<<20)
+#define S5P_CLKSRC6_PWI_SHIFT		(20)
+#define S5P_CLKSRC6_ONEDRAM_MASK	(0x3<<24)
+#define S5P_CLKSRC6_ONEDRAM_SHIFT	(24)
+
+/* CLKSRC_MASK0 - To be defined */
+#define S5P_CLKSRC_MASK0_HDMI		(1<<0)
+#define S5P_CLKSRC_MASK0_MIXER		(1<<1)
+
+/* CLKSRC_MASK1 - To be defined */
+
 
 /* CLKDIV0 */
 #define S5P_CLKDIV0_APLL_SHIFT		(0)
@@ -90,7 +217,325 @@
 #define S5P_CLKDIV0_PCLK66_SHIFT	(28)
 #define S5P_CLKDIV0_PCLK66_MASK		(0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
 
+/* CLKDIV1 */
+#define S5P_CLKDIV1_TBLK_MASK		(0xF<<0)
+#define S5P_CLKDIV1_TBLK_SHIFT		(0)
+#define S5P_CLKDIV1_FIMC_MASK		(0xF<<8)
+#define S5P_CLKDIV1_FIMC_SHIFT		(8)
+#define S5P_CLKDIV1_CAM0_MASK		(0xF<<12)
+#define S5P_CLKDIV1_CAM0_SHIFT		(12)
+#define S5P_CLKDIV1_CAM1_MASK		(0xF<<16)
+#define S5P_CLKDIV1_CAM1_SHIFT		(16)
+#define S5P_CLKDIV1_FIMD_MASK		(0xF<<20)
+#define S5P_CLKDIV1_FIMD_SHIFT		(20)
+#define S5P_CLKDIV1_CSIS_MASK		(0xF<<28)
+#define S5P_CLKDIV1_CSIS_SHIFT		(28)
+
+/* CLKDIV2 */
+#define S5P_CLKDIV2_G3D_MASK		(0xF<<0)
+#define S5P_CLKDIV2_G3D_SHIFT		(0)
+#define S5P_CLKDIV2_MFC_MASK		(0xF<<4)
+#define S5P_CLKDIV2_MFC_SHIFT		(4)
+#define S5P_CLKDIV2_G2D_MASK		(0xF<<8)
+#define S5P_CLKDIV2_G2D_SHIFT		(8)
+
+/* CLKDIV3 */
+#define S5P_CLKDIV3_MDNIE_MASK		(0xf<<0)
+#define S5P_CLKDIV3_MDNIE_SHIFT		(0)
+#define S5P_CLKDIV3_MDNIE_PWM_MASK	(0x3f<<4)
+#define S5P_CLKDIV3_MDNIE_PWM_SHIFT	(4)
+#define S5P_CLKDIV3_FIMC0_LCLK_MASK	(0xf<<12)
+#define S5P_CLKDIV3_FIMC0_LCLK_SHIFT	(12)
+#define S5P_CLKDIV3_FIMC1_LCLK_MASK	(0xf<<16)
+#define S5P_CLKDIV3_FIMC1_LCLK_SHIFT	(16)
+#define S5P_CLKDIV3_FIMC2_LCLK_MASK	(0xf<<20)
+#define S5P_CLKDIV3_FIMC2_LCLK_SHIFT	(20)
+
+/* CLKDIV4 */
+#define S5P_CLKDIV4_MMC0_MASK		(0xF<<0)
+#define S5P_CLKDIV4_MMC0_SHIFT		(0)
+#define S5P_CLKDIV4_MMC1_MASK		(0xF<<4)
+#define S5P_CLKDIV4_MMC1_SHIFT		(4)
+#define S5P_CLKDIV4_MMC2_MASK		(0xF<<8)
+#define S5P_CLKDIV4_MMC2_SHIFT		(8)
+#define S5P_CLKDIV4_MMC3_MASK		(0xF<<12)
+#define S5P_CLKDIV4_MMC3_SHIFT		(12)
+#define S5P_CLKDIV4_UART0_MASK		(0xF<<16)
+#define S5P_CLKDIV4_UART0_SHIFT		(16)
+#define S5P_CLKDIV4_UART1_MASK		(0xf<<20)
+#define S5P_CLKDIV4_UART1_SHIFT		(20)
+#define S5P_CLKDIV4_UART2_MASK		(0xf<<24)
+#define S5P_CLKDIV4_UART2_SHIFT		(24)
+#define S5P_CLKDIV4_UART3_MASK		(0xf<<28)
+#define S5P_CLKDIV4_UART3_SHIFT		(28)
+
+/* CLKDIV5 */
+#define S5P_CLKDIV5_SPI0_MASK		(0xF<<0)
+#define S5P_CLKDIV5_SPI0_SHIFT		(0)
+#define S5P_CLKDIV5_SPI1_MASK		(0xF<<4)
+#define S5P_CLKDIV5_SPI1_SHIFT		(4)
+#define S5P_CLKDIV5_SPI2_MASK		(0xF<<8)
+#define S5P_CLKDIV5_SPI2_SHIFT		(8)
+#define S5P_CLKDIV5_PWM_MASK		(0xF<<12)
+#define S5P_CLKDIV5_PWM_SHIFT		(12)
+
+/* CLKDIV6 */
+#define S5P_CLKDIV6_AUDIO0_MASK		(0xF<<0)
+#define S5P_CLKDIV6_AUDIO0_SHIFT	(0)
+#define S5P_CLKDIV6_AUDIO1_MASK		(0xF<<4)
+#define S5P_CLKDIV6_AUDIO1_SHIFT	(4)
+#define S5P_CLKDIV6_AUDIO2_MASK		(0xF<<8)
+#define S5P_CLKDIV6_AUDIO2_SHIFT	(8)
+#define S5P_CLKDIV6_ONENAND_MASK	(0x7<<12)
+#define S5P_CLKDIV6_ONENAND_SHIFT	(12)
+#define S5P_CLKDIV6_COPY_MASK		(0x7<<16)
+#define S5P_CLKDIV6_COPY_SHIFT		(16)
+#define S5P_CLKDIV6_HPM_MASK		(0x7<<20)
+#define S5P_CLKDIV6_HPM_SHIFT		(20)
+#define S5P_CLKDIV6_PWI_MASK		(0xf<<24)
+#define S5P_CLKDIV6_PWI_SHIFT		(24)
+#define S5P_CLKDIV6_ONEDRAM_MASK	(0xf<<28)
+#define S5P_CLKDIV6_ONEDRAM_SHIFT	(28)
+
+/* IP Clock Gate 0 Registers */
+#define S5P_CLKGATE_IP0_CSIS		(1<<31)
+#define S5P_CLKGATE_IP0_IPC		(1<<30)
+#define S5P_CLKGATE_IP0_ROTATOR		(1<<29)
+#define S5P_CLKGATE_IP0_JPEG		(1<<28)
+#define S5P_CLKGATE_IP0_FIMC2		(1<<26)
+#define S5P_CLKGATE_IP0_FIMC1		(1<<25)
+#define S5P_CLKGATE_IP0_FIMC0		(1<<24)
+#define S5P_CLKGATE_IP0_MFC		(1<<16)
+#define S5P_CLKGATE_IP0_G2D		(1<<12)
+#define S5P_CLKGATE_IP0_G3D		(1<<8)
+#define S5P_CLKGATE_IP0_IMEM		(1<<5)
+#define S5P_CLKGATE_IP0_PDMA1		(1<<4)
+#define S5P_CLKGATE_IP0_PDMA0		(1<<3)
+#define S5P_CLKGATE_IP0_MDMA		(1<<2)
+#define S5P_CLKGATE_IP0_DMC1		(1<<1)
+#define S5P_CLKGATE_IP0_DMC0		(1<<0)
+#define S5P_CLKGATE_IP0_RESERVED	(0x08feeec0)
+#define S5P_CLKGATE_IP0_ALWAYS_ON	( S5P_CLKGATE_IP0_DMC1 |\
+					S5P_CLKGATE_IP0_DMC0 |\
+					S5P_CLKGATE_IP0_IMEM )
+#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING
+#define S5P_CLKGATE_IP0_BOOT_ON		( S5P_CLKGATE_IP0_PDMA0 |\
+					S5P_CLKGATE_IP0_PDMA1)
+#else
+#define S5P_CLKGATE_IP0_BOOT_ON		( S5P_CLKGATE_IP0_PDMA0 |\
+					S5P_CLKGATE_IP0_PDMA1 |\
+					S5P_CLKGATE_IP0_G2D)
+#endif
+
+/* IP Clock Gate 1 Registers */
+#define S5P_CLKGATE_IP1_NFCON		(1<<28)
+#define S5P_CLKGATE_IP1_SROMC		(1<<26)
+#define S5P_CLKGATE_IP1_CFCON		(1<<25)
+#define S5P_CLKGATE_IP1_NANDXL		(1<<24)
+#define S5P_CLKGATE_IP1_USBHOST		(1<<17)
+#define S5P_CLKGATE_IP1_USBOTG		(1<<16)
+#define S5P_CLKGATE_IP1_HDMI		(1<<11)
+#define S5P_CLKGATE_IP1_TVENC		(1<<10)
+#define S5P_CLKGATE_IP1_MIXER		(1<<9)
+#define S5P_CLKGATE_IP1_VP		(1<<8)
+#define S5P_CLKGATE_IP1_DSIM		(1<<2)
+#define S5P_CLKGATE_IP1_MIE		(1<<1)
+#define S5P_CLKGATE_IP1_FIMD		(1<<0)
+#define S5P_CLKGATE_IP1_RESERVED	(0xe8fcf0f8)
+#define S5P_CLKGATE_IP1_ALWAYS_ON	( 0 )
+#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING
+#define S5P_CLKGATE_IP1_BOOT_ON		( S5P_CLKGATE_IP1_FIMD |\
+					S5P_CLKGATE_IP1_NANDXL)
+#else
+#define S5P_CLKGATE_IP1_BOOT_ON		( S5P_CLKGATE_IP1_FIMD |\
+					S5P_CLKGATE_IP1_NANDXL |\
+					S5P_CLKGATE_IP1_USBOTG)
+#endif
+
+
+/* IP Clock Gate 2 Registers */
+#define S5P_CLKGATE_IP2_TZIC3		(1<<31)
+#define S5P_CLKGATE_IP2_TZIC2		(1<<30)
+#define S5P_CLKGATE_IP2_TZIC1		(1<<29)
+#define S5P_CLKGATE_IP2_TZIC0		(1<<28)
+#define S5P_CLKGATE_IP2_VIC3		(1<<27)
+#define S5P_CLKGATE_IP2_VIC2		(1<<26)
+#define S5P_CLKGATE_IP2_VIC1		(1<<25)
+#define S5P_CLKGATE_IP2_VIC0		(1<<24)
+#define S5P_CLKGATE_IP2_TSI		(1<<20)
+#define S5P_CLKGATE_IP2_HSMMC3		(1<<19)
+#define S5P_CLKGATE_IP2_HSMMC2		(1<<18)
+#define S5P_CLKGATE_IP2_HSMMC1		(1<<17)
+#define S5P_CLKGATE_IP2_HSMMC0		(1<<16)
+#define S5P_CLKGATE_IP2_SECJTAG		(1<<11)
+#define S5P_CLKGATE_IP2_HOSTIF		(1<<10)
+#define S5P_CLKGATE_IP2_MODEM		(1<<9)
+#define S5P_CLKGATE_IP2_CORESIGHT	(1<<8)
+#define S5P_CLKGATE_IP2_SDM		(1<<1)
+#define S5P_CLKGATE_IP2_SECSS		(1<<0)
+#define S5P_CLKGATE_IP2_RESERVED	(0xe0f0fc)
+#define S5P_CLKGATE_IP2_ALWAYS_ON	( S5P_CLKGATE_IP2_TZIC3 | S5P_CLKGATE_IP2_TZIC2 |\
+					S5P_CLKGATE_IP2_TZIC1 | S5P_CLKGATE_IP2_TZIC0 |\
+					S5P_CLKGATE_IP2_VIC3 | S5P_CLKGATE_IP2_VIC2 |\
+					S5P_CLKGATE_IP2_VIC1 | S5P_CLKGATE_IP2_VIC0 |\
+					S5P_CLKGATE_IP2_SECJTAG | S5P_CLKGATE_IP2_CORESIGHT |\
+					S5P_CLKGATE_IP2_SDM | S5P_CLKGATE_IP2_SECSS )
+#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING
+#define S5P_CLKGATE_IP2_BOOT_ON		( 0 )
+#else
+#define S5P_CLKGATE_IP2_BOOT_ON		( S5P_CLKGATE_IP2_TSI |\
+					S5P_CLKGATE_IP2_HSMMC2 |\
+					S5P_CLKGATE_IP2_HSMMC0 |\
+					S5P_CLKGATE_IP2_HOSTIF |\
+					S5P_CLKGATE_IP2_MODEM)
+#endif
+
+
+/* IP Clock Gate 3 Registers */
+#define S5P_CLKGATE_IP3_PCM2		(1<<30)
+#define S5P_CLKGATE_IP3_PCM1		(1<<29)
+#define S5P_CLKGATE_IP3_PCM0		(1<<28)
+#define S5P_CLKGATE_IP3_SYSCON		(1<<27)
+#define S5P_CLKGATE_IP3_GPIO		(1<<26)
+#define S5P_CLKGATE_IP3_TSADC		(1<<24)
+#define S5P_CLKGATE_IP3_PWM		(1<<23)
+#define S5P_CLKGATE_IP3_WDT		(1<<22)
+#define S5P_CLKGATE_IP3_KEYIF		(1<<21)
+#define S5P_CLKGATE_IP3_UART3		(1<<20)
+#define S5P_CLKGATE_IP3_UART2		(1<<19)
+#define S5P_CLKGATE_IP3_UART1		(1<<18)
+#define S5P_CLKGATE_IP3_UART0		(1<<17)
+#define S5P_CLKGATE_IP3_SYSTIMER	(1<<16)
+#define S5P_CLKGATE_IP3_RTC		(1<<15)
+#define S5P_CLKGATE_IP3_SPI2		(1<<14)
+#define S5P_CLKGATE_IP3_SPI1		(1<<13)
+#define S5P_CLKGATE_IP3_SPI0		(1<<12)
+#define S5P_CLKGATE_IP3_I2C_HDMI_PHY	(1<<11)
+#define S5P_CLKGATE_IP3_I2C_HDMI_DDC	(1<<10)
+#define S5P_CLKGATE_IP3_I2C2		(1<<9)
+#define S5P_CLKGATE_IP3_I2C1		(1<<8)
+#define S5P_CLKGATE_IP3_I2C0		(1<<7)
+#define S5P_CLKGATE_IP3_I2S2		(1<<6)
+#define S5P_CLKGATE_IP3_I2S1		(1<<5)
+#define S5P_CLKGATE_IP3_I2S0		(1<<4)
+#define S5P_CLKGATE_IP3_AC97		(1<<1)
+#define S5P_CLKGATE_IP3_SPDIF		(1<<0)
+#define S5P_CLKGATE_IP3_RESERVED	(0x8200000c)
+#define S5P_CLKGATE_IP3_ALWAYS_ON	( S5P_CLKGATE_IP3_SYSCON |\
+					S5P_CLKGATE_IP3_GPIO |\
+					S5P_CLKGATE_IP3_PWM |\
+					S5P_CLKGATE_IP3_UART0 |\
+					S5P_CLKGATE_IP3_UART1 |\
+					S5P_CLKGATE_IP3_UART2 |\
+					S5P_CLKGATE_IP3_UART3 |\
+					S5P_CLKGATE_IP3_SYSTIMER |\
+					S5P_CLKGATE_IP3_I2C0 |\
+					S5P_CLKGATE_IP3_I2C1 |\
+					S5P_CLKGATE_IP3_I2C2 |\
+					S5P_CLKGATE_IP3_RTC )
+#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING
+#define S5P_CLKGATE_IP3_BOOT_ON		( 0 )
+#else
+#define S5P_CLKGATE_IP3_BOOT_ON		( S5P_CLKGATE_IP3_WDT |\
+					S5P_CLKGATE_IP3_KEYIF |\
+					S5P_CLKGATE_IP3_I2C_HDMI_PHY )
+#endif
+
+
+/* IP Clock Gate 4 Registers */
+#define S5P_CLKGATE_IP4_TZPC3		(1<<8)
+#define S5P_CLKGATE_IP4_TZPC2		(1<<7)
+#define S5P_CLKGATE_IP4_TZPC1		(1<<6)
+#define S5P_CLKGATE_IP4_TZPC0		(1<<5)
+#define S5P_CLKGATE_IP4_SECKEY		(1<<3)
+#define S5P_CLKGATE_IP4_IEM_APC		(1<<2)
+#define S5P_CLKGATE_IP4_IEM_IEC		(1<<1)
+#define S5P_CLKGATE_IP4_CHIP_ID		(1<<0)
+#define S5P_CLKGATE_IP4_RESERVED	(0xfffffe10)
+#define S5P_CLKGATE_IP4_ALWAYS_ON	( S5P_CLKGATE_IP4_TZPC3 |\
+					S5P_CLKGATE_IP4_TZPC2 |\
+					S5P_CLKGATE_IP4_TZPC1 |\
+					S5P_CLKGATE_IP4_TZPC0 )
+#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING
+#define S5P_CLKGATE_IP4_BOOT_ON		( 0 )
+#else
+#define S5P_CLKGATE_IP4_BOOT_ON		( S5P_CLKGATE_IP4_CHIP_ID )
+#endif
+
+
+/* Block Clock Gate Registers */
+#define S5P_CLKGATE_BLOCK_INTC		(1<<10)
+#define S5P_CLKGATE_BLOCK_HSMMC		(1<<9)
+#define S5P_CLKGATE_BLOCK_DEBUG		(1<<8)
+#define S5P_CLKGATE_BLOCK_SECURITY	(1<<7)
+#define S5P_CLKGATE_BLOCK_MEMORY	(1<<6)
+#define S5P_CLKGATE_BLOCK_USB		(1<<5)
+#define S5P_CLKGATE_BLOCK_TV		(1<<4)
+#define S5P_CLKGATE_BLOCK_LCD		(1<<3)
+#define S5P_CLKGATE_BLOCK_IMG		(1<<2)
+#define S5P_CLKGATE_BLOCK_MFC		(1<<1)
+#define S5P_CLKGATE_BLOCK_G3D		(1<<0)
+
+/* IP Clock Gate 5 Registers */
+#define S5P_CLKGATE_IP5_JPEG		(1<<29)
+#define S5P_CLKGATE_IP5_RESERVED	(0xdfffffff)
+#define S5P_CLKGATE_IP5_ALWAYS_ON	(0)
+#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING
+#define S5P_CLKGATE_IP5_BOOT_ON		(0)
+#else
+#define S5P_CLKGATE_IP5_BOOT_ON		( S5P_CLKGATE_IP5_JPEG )
+#endif
+
+/* Bus Clock Gate Registers (hidden) */
+
+
+/* CLK_OUT Registers */
+#define S5P_CLKOUT_DIV_SHIFT		(20)
+#define S5P_CLKOUT_DIV_MASK		(0xf << S5P_CLKOUT_DIV_SHIFT)
+#define S5P_CLKOUT_CLKSEL_SHIFT		(12)
+#define S5P_CLKOUT_CLKSEL_MASK		(0x1f << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_APLL		(0 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_MPLL		(1 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_EPLL		(2 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_VPLL		(3 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_SCLK_USBPHY0	(4 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_SCLK_USBPHY1	(5 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_SCLK_HDMIPHY	(6 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_RTC		(7 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_TICK		(8 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_HCLK200	(9 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_PCLK100	(10 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_HCLK166	(11 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_PCLK83	(12 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_HCLK133	(13 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_PCLK66	(14 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_ARMCLK	(15 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_SCLK_HPM	(16 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_XXTI		(17 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_XUSBXTI	(18 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_CLKSEL_DOUT		(19 << S5P_CLKOUT_CLKSEL_SHIFT)
+#define S5P_CLKOUT_DCLKCMP_SHIFT	(8)
+#define S5P_CLKOUT_DCLKCMP_MASK		(0xf << S5P_CLKOUT_DCLKCMP_SHIFT)
+#define S5P_CLKOUT_DCLKDIV_SHIFT	(4)
+#define S5P_CLKOUT_DCLKDIV_MASK		(0xf << S5P_CLKOUT_DCLKDIV_SHIFT)
+#define S5P_CLKOUT_DCLKSEL_SHIFT	(1)
+#define S5P_CLKOUT_DCLKSEL_MASK		(0x7 << S5P_CLKOUT_DCLKSEL_SHIFT)
+#define S5P_CLKOUT_DCLKSEL_XXTI		(0 << S5P_CLKOUT_DCLKSEL_SHIFT)
+#define S5P_CLKOUT_DCLKSEL_XUSBXTI	(1 << S5P_CLKOUT_DCLKSEL_SHIFT)
+#define S5P_CLKOUT_DCLKSEL_HDMI27M	(2 << S5P_CLKOUT_DCLKSEL_SHIFT)
+#define S5P_CLKOUT_DCLKSEL_USBPHY0	(3 << S5P_CLKOUT_DCLKSEL_SHIFT)
+#define S5P_CLKOUT_DCLKSEL_USBPHY1	(4 << S5P_CLKOUT_DCLKSEL_SHIFT)
+#define S5P_CLKOUT_DCLKSEL_HDMIPHY	(5 << S5P_CLKOUT_DCLKSEL_SHIFT)
+#define S5P_CLKOUT_DCLKSEL_FOUTEPLL	(6 << S5P_CLKOUT_DCLKSEL_SHIFT)
+#define S5P_CLKOUT_DCLKSEL_SCLKEPLL	(7 << S5P_CLKOUT_DCLKSEL_SHIFT)
+#define S5P_CLKOUT_DCLKEN_SHIFT		(0)
+#define S5P_CLKOUT_DCLKEN_MASK		(0x1 << S5P_CLKOUT_DCLKEN_SHIFT)
+#define S5P_CLKOUT_DCLKEN_ENABLE	(1 << S5P_CLKOUT_DCLKEN_SHIFT)
+#define S5P_CLKOUT_DCLKEN_DISABLE	(0 << S5P_CLKOUT_DCLKEN_SHIFT)
+
 /* Registers related to power management */
+#define S5P_SWRESET		S5P_CLKREG(0x2000)
+
 #define S5P_PWR_CFG		S5P_CLKREG(0xC000)
 #define S5P_EINT_WAKEUP_MASK	S5P_CLKREG(0xC004)
 #define S5P_WAKEUP_MASK 	S5P_CLKREG(0xC008)
@@ -112,8 +557,13 @@
 
 #define S5P_OTHERS		S5P_CLKREG(0xE000)
 #define S5P_OM_STAT		S5P_CLKREG(0xE100)
+#define S5P_MIE_CONTROL		S5P_CLKREG(0xE800)
+#define S5P_HDMI_PHY_CONTROL	S5P_CLKREG(0xE804)
 #define S5P_USB_PHY_CONTROL	S5P_CLKREG(0xE80C)
 #define S5P_DAC_CONTROL		S5P_CLKREG(0xE810)
+#define S5P_MIPI_DPHY_CONTROL		S5P_CLKREG(0xE814)
+#define S5P_ADC_CONTROL		S5P_CLKREG(0xE818)
+#define S5P_PS_HOLD_CONTROL	S5P_CLKREG(0xE81C)
 
 #define S5P_INFORM0		S5P_CLKREG(0xF000)
 #define S5P_INFORM1		S5P_CLKREG(0xF004)
@@ -159,12 +609,25 @@
 /* OTHERS Resgister */
 #define S5P_OTHERS_USB_SIG_MASK		(1 << 16)
 #define S5P_OTHERS_MIPI_DPHY_EN		(1 << 28)
+#define S5P_OTHERS_CLKOUT_SHIFT		(8)
+#define S5P_OTHERS_CLKOUT_MASK		(0x3 << S5P_OTHERS_CLKOUT_SHIFT)
+#define S5P_OTHERS_CLKOUT_SYSCON	(0 << S5P_OTHERS_CLKOUT_SHIFT)
+#define S5P_OTHERS_CLKOUT_RESERVED	(1 << S5P_OTHERS_CLKOUT_SHIFT)
+#define S5P_OTHERS_CLKOUT_XXTI		(2 << S5P_OTHERS_CLKOUT_SHIFT)
+#define S5P_OTHERS_CLKOUT_XUSBXTI	(3 << S5P_OTHERS_CLKOUT_SHIFT)
 
 /* MIPI */
-#define S5P_MIPI_DPHY_EN		(3)
+#define S5P_MIPI_DPHY_EN		(3 << 0)
+
+/* S5P_MIPI_PHY_CON0 */
+#define S5P_MIPI_M_RESETN		(1 << 1)
 
 /* S5P_DAC_CONTROL */
 #define S5P_DAC_ENABLE			(1)
 #define S5P_DAC_DISABLE			(0)
 
+#define S5PC110_USB_PHY_CON	S5P_CLKREG(0xE80c)
+#define S5PC110_USB_PHY0_EN	(1 << 0)
+#define S5PC110_USB_PHY1_EN	(1 << 1)
+
 #endif /* __ASM_ARCH_REGS_CLOCK_H */
-- 
1.6.3.3



From myungjoo.ham at samsung.com  Mon Jun 14 04:39:12 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Mon, 14 Jun 2010 17:39:12 +0900
Subject: [PATCH 3/6] S5PV210 added register mappings
In-Reply-To: <1276504755-24741-3-git-send-email-MyungJoo.Ham@samsung.com>
References: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-2-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-3-git-send-email-MyungJoo.Ham@samsung.com>
Message-ID: <1276504755-24741-4-git-send-email-MyungJoo.Ham@samsung.com>


Signed-off-by: MyungJoo Ham <MyungJoo.Ham at samsung.com>
---
 arch/arm/mach-s5pv210/include/mach/map.h |   45 ++++++++++++++++++++++++++++++
 1 files changed, 45 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 34eb168..e1a6ff8 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -54,6 +54,9 @@
 
 #define S5PV210_PA_SROMC	(0xE8000000)
 
+/* DMA */
+#define S5PV210_PA_DMA          (0xFA200000)
+#define S5PV210_PA_PDMA         (0xE0900000)
 #define S5PV210_PA_MDMA		0xFA200000
 #define S5PV210_PA_PDMA0	0xE0900000
 #define S5PV210_PA_PDMA1	0xE0A00000
@@ -77,6 +80,25 @@
 #define S5PV210_PA_SDRAM	(0x20000000)
 #define S5P_PA_SDRAM		S5PV210_PA_SDRAM
 
+#define S5PV210_PA_RTC          (0xE2800000)
+
+#define S5PV210_PA_PWR          (0xE010C000)
+#define S5P_PA_PWR              S5PV210_PA_PWR
+#define S5P_PA_INFORM0          (S5P_PA_PWR + 0x3000)
+
+/* USB HS OTG */
+#define S5PV210_PA_USB_HSOTG    (0xEC000000)
+#define S5PV210_PA_USB_HSPHY    (0xEC100000)
+
+/* FIMC */
+#define S5PV210_PA_FIMC0        (0xFB200000)
+#define S5PV210_PA_FIMC1        (0xFB300000)
+#define S5PV210_PA_FIMC2        (0xFB400000)
+
+/* MFC */
+#define S5PV210_PA_MFC          (0xF1700000)
+#define S5PV210_SZ_MFC          (0x0000FFFF)
+
 /* I2S */
 #define S5PV210_PA_IIS0		0xEEE30000
 #define S5PV210_PA_IIS1		0xE2100000
@@ -87,6 +109,17 @@
 #define S5PV210_PA_PCM1		0xE1200000
 #define S5PV210_PA_PCM2		0xE2B00000
 
+/* Audio SubSystem */
+#define S5PV210_PA_AUDSS        (0xEEE10000)
+
+/* TZPC */
+#define S5PV210_PA_TZPC0        (0xF1500000)
+#define S5PV210_PA_TZPC1        (0xFAD00000)
+#define S5PV210_PA_TZPC2        (0xE0600000)
+#define S5PV210_PA_TZPC3        (0xE1C00000)
+
+#define S5PV210_VA_TZPC(x)      (S3C_ADDR(0x01700000) + ((x) * 0x10000))
+
 /* AC97 */
 #define S5PV210_PA_AC97		0xE2200000
 
@@ -101,6 +134,18 @@
 #define S3C_PA_IIC1		S5PV210_PA_IIC1
 #define S3C_PA_IIC2		S5PV210_PA_IIC2
 #define S3C_PA_FB		S5PV210_PA_FB
+#define S3C_PA_USB_HSOTG        S5PV210_PA_USB_HSOTG
+#define S3C_PA_USB_HSPHY        S5PV210_PA_USB_HSPHY
+#define S3C_PA_RTC              S5PV210_PA_RTC
+#define S5P_PA_FIMC0            S5PV210_PA_FIMC0
+#define S5P_PA_FIMC1            S5PV210_PA_FIMC1
+#define S5P_PA_FIMC2            S5PV210_PA_FIMC2
+#define S3C_PA_DMA              S5PV210_PA_DMA
+#define S3C_PA_PDMA             S5PV210_PA_PDMA
+#define S3C_PA_IIS_V50          S5PV210_PA_IIS0
+#define S3C_PA_ADC              S5PV210_PA_ADC(0)
+#define S3C_PA_ADC0             S5PV210_PA_ADC(0)
+#define S3C_PA_ADC1             S5PV210_PA_ADC(1)
 #define S3C_PA_WDT		S5PV210_PA_WATCHDOG
 
 #define SAMSUNG_PA_ADC		S5PV210_PA_ADC
-- 
1.6.3.3



From myungjoo.ham at samsung.com  Mon Jun 14 04:39:13 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Mon, 14 Jun 2010 17:39:13 +0900
Subject: [PATCH 4/6] S5PV210 GPIO relataed registers are added.
In-Reply-To: <1276504755-24741-4-git-send-email-MyungJoo.Ham@samsung.com>
References: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-2-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-3-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-4-git-send-email-MyungJoo.Ham@samsung.com>
Message-ID: <1276504755-24741-5-git-send-email-MyungJoo.Ham@samsung.com>


Signed-off-by: MyungJoo Ham <MyungJoo.Ham at samsung.com>
---
 arch/arm/mach-s5pv210/include/mach/regs-gpio.h |  121 ++++++++++++++++++++++++
 1 files changed, 121 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
index 49e029b..d0dc78f 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-gpio.h
@@ -45,4 +45,125 @@
 #define EINT_GPIO_2(x)		S5PV210_GPH2(x)
 #define EINT_GPIO_3(x)		S5PV210_GPH3(x)
 
+#define S5PV210_GPIO_BASE	S5P_VA_GPIO
+
+#define S5PV210_ETC0PUD         (S5PV210_GPIO_BASE + 0x0608)
+#define S5PV210_ETC0DRV         (S5PV210_GPIO_BASE + 0x060C)
+#define S5PV210_ETC1PUD         (S5PV210_GPIO_BASE + 0x0628)
+#define S5PV210_ETC1DRV         (S5PV210_GPIO_BASE + 0x062C)
+#define S5PV210_ETC2PUD         (S5PV210_GPIO_BASE + 0x0648)
+#define S5PV210_ETC2DRV         (S5PV210_GPIO_BASE + 0x064C)
+
+#define S5PV210_GPA0_INT_CON    (S5PV210_GPIO_BASE + 0x0700)
+#define S5PV210_GPA1_INT_CON    (S5PV210_GPIO_BASE + 0x0704)
+#define S5PV210_GPB_INT_CON     (S5PV210_GPIO_BASE + 0x0708)
+#define S5PV210_GPC0_INT_CON    (S5PV210_GPIO_BASE + 0x070C)
+#define S5PV210_GPC1_INT_CON    (S5PV210_GPIO_BASE + 0x0710)
+#define S5PV210_GPD0_INT_CON    (S5PV210_GPIO_BASE + 0x0714)
+#define S5PV210_GPD1_INT_CON    (S5PV210_GPIO_BASE + 0x0718)
+#define S5PV210_GPE0_INT_CON    (S5PV210_GPIO_BASE + 0x071C)
+#define S5PV210_GPE1_INT_CON    (S5PV210_GPIO_BASE + 0x0720)
+#define S5PV210_GPF0_INT_CON    (S5PV210_GPIO_BASE + 0x0724)
+#define S5PV210_GPF1_INT_CON    (S5PV210_GPIO_BASE + 0x0728)
+#define S5PV210_GPF2_INT_CON    (S5PV210_GPIO_BASE + 0x072C)
+#define S5PV210_GPF3_INT_CON    (S5PV210_GPIO_BASE + 0x0730)
+#define S5PV210_GPG0_INT_CON    (S5PV210_GPIO_BASE + 0x0734)
+#define S5PV210_GPG1_INT_CON    (S5PV210_GPIO_BASE + 0x0738)
+#define S5PV210_GPG2_INT_CON    (S5PV210_GPIO_BASE + 0x073C)
+#define S5PV210_GPG3_INT_CON    (S5PV210_GPIO_BASE + 0x0740)
+#define S5PV210_GPJ0_INT_CON    (S5PV210_GPIO_BASE + 0x0744)
+#define S5PV210_GPJ1_INT_CON    (S5PV210_GPIO_BASE + 0x0748)
+#define S5PV210_GPJ2_INT_CON    (S5PV210_GPIO_BASE + 0x074C)
+#define S5PV210_GPJ3_INT_CON    (S5PV210_GPIO_BASE + 0x0750)
+#define S5PV210_GPJ4_INT_CON    (S5PV210_GPIO_BASE + 0x0754)
+
+#define S5PV210_GPA0_INT_MASK   (S5PV210_GPIO_BASE + 0x0900)
+#define S5PV210_GPA1_INT_MASK   (S5PV210_GPIO_BASE + 0x0904)
+#define S5PV210_GPB_INT_MASK    (S5PV210_GPIO_BASE + 0x0908)
+#define S5PV210_GPC0_INT_MASK   (S5PV210_GPIO_BASE + 0x090C)
+#define S5PV210_GPC1_INT_MASK   (S5PV210_GPIO_BASE + 0x0910)
+#define S5PV210_GPD0_INT_MASK   (S5PV210_GPIO_BASE + 0x0914)
+#define S5PV210_GPD1_INT_MASK   (S5PV210_GPIO_BASE + 0x0918)
+#define S5PV210_GPE0_INT_MASK   (S5PV210_GPIO_BASE + 0x091C)
+#define S5PV210_GPE1_INT_MASK   (S5PV210_GPIO_BASE + 0x0920)
+#define S5PV210_GPF0_INT_MASK   (S5PV210_GPIO_BASE + 0x0924)
+#define S5PV210_GPF1_INT_MASK   (S5PV210_GPIO_BASE + 0x0928)
+#define S5PV210_GPF2_INT_MASK   (S5PV210_GPIO_BASE + 0x092C)
+#define S5PV210_GPF3_INT_MASK   (S5PV210_GPIO_BASE + 0x0930)
+#define S5PV210_GPG0_INT_MASK   (S5PV210_GPIO_BASE + 0x0934)
+#define S5PV210_GPG1_INT_MASK   (S5PV210_GPIO_BASE + 0x0938)
+#define S5PV210_GPG2_INT_MASK   (S5PV210_GPIO_BASE + 0x093C)
+#define S5PV210_GPG3_INT_MASK   (S5PV210_GPIO_BASE + 0x0940)
+#define S5PV210_GPJ0_INT_MASK   (S5PV210_GPIO_BASE + 0x0944)
+#define S5PV210_GPJ1_INT_MASK   (S5PV210_GPIO_BASE + 0x0948)
+#define S5PV210_GPJ2_INT_MASK   (S5PV210_GPIO_BASE + 0x094C)
+#define S5PV210_GPJ3_INT_MASK   (S5PV210_GPIO_BASE + 0x0950)
+#define S5PV210_GPJ4_INT_MASK   (S5PV210_GPIO_BASE + 0x0954)
+
+#define S5PV210_GPA0_INT_PEND   (S5PV210_GPIO_BASE + 0x0a00)
+#define S5PV210_GPA1_INT_PEND   (S5PV210_GPIO_BASE + 0x0a04)
+#define S5PV210_GPB_INT_PEND    (S5PV210_GPIO_BASE + 0x0a08)
+#define S5PV210_GPC0_INT_PEND   (S5PV210_GPIO_BASE + 0x0a0C)
+#define S5PV210_GPC1_INT_PEND   (S5PV210_GPIO_BASE + 0x0a10)
+#define S5PV210_GPD0_INT_PEND   (S5PV210_GPIO_BASE + 0x0a14)
+#define S5PV210_GPD1_INT_PEND   (S5PV210_GPIO_BASE + 0x0a18)
+#define S5PV210_GPE0_INT_PEND   (S5PV210_GPIO_BASE + 0x0a1C)
+#define S5PV210_GPE1_INT_PEND   (S5PV210_GPIO_BASE + 0x0a20)
+#define S5PV210_GPF0_INT_PEND   (S5PV210_GPIO_BASE + 0x0a24)
+#define S5PV210_GPF1_INT_PEND   (S5PV210_GPIO_BASE + 0x0a28)
+#define S5PV210_GPF2_INT_PEND   (S5PV210_GPIO_BASE + 0x0a2C)
+#define S5PV210_GPF3_INT_PEND   (S5PV210_GPIO_BASE + 0x0a30)
+#define S5PV210_GPG0_INT_PEND   (S5PV210_GPIO_BASE + 0x0a34)
+#define S5PV210_GPG1_INT_PEND   (S5PV210_GPIO_BASE + 0x0a38)
+#define S5PV210_GPG2_INT_PEND   (S5PV210_GPIO_BASE + 0x0a3C)
+#define S5PV210_GPG3_INT_PEND   (S5PV210_GPIO_BASE + 0x0a40)
+#define S5PV210_GPJ0_INT_PEND   (S5PV210_GPIO_BASE + 0x0a44)
+#define S5PV210_GPJ1_INT_PEND   (S5PV210_GPIO_BASE + 0x0a48)
+#define S5PV210_GPJ2_INT_PEND   (S5PV210_GPIO_BASE + 0x0a4C)
+#define S5PV210_GPJ3_INT_PEND   (S5PV210_GPIO_BASE + 0x0a50)
+#define S5PV210_GPJ4_INT_PEND   (S5PV210_GPIO_BASE + 0x0a54)
+
+#define S5PV210_GPIO_INT_GRPPRI (S5PV210_GPIO_BASE + 0x0b00)
+#define S5PV210_GPIO_INT_PRIORITY       (S5PV210_GPIO_BASE + 0x0b04)
+#define S5PV210_GPIO_INT_SERVICE        (S5PV210_GPIO_BASE + 0x0b08)
+#define S5PV210_GPIO_INT_SERVICE_PEND   (S5PV210_GPIO_BASE + 0x0b0c)
+#define S5PV210_GPIO_INT_GRPFIXPRI      (S5PV210_GPIO_BASE + 0x0b10)
+
+#define S5PV210_GPA0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b14)
+#define S5PV210_GPA1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b18)
+#define S5PV210_GPB_INT_FIXPRI  (S5PV210_GPIO_BASE + 0x0b1c)
+#define S5PV210_GPC0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b20)
+#define S5PV210_GPC1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b24)
+#define S5PV210_GPD0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b28)
+#define S5PV210_GPD1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b2c)
+#define S5PV210_GPE0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b30)
+#define S5PV210_GPE1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b34)
+#define S5PV210_GPF0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b38)
+#define S5PV210_GPF1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b3c)
+#define S5PV210_GPF2_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b40)
+#define S5PV210_GPF3_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b44)
+#define S5PV210_GPG0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b48)
+#define S5PV210_GPG1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b4c)
+#define S5PV210_GPG2_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b50)
+#define S5PV210_GPG3_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b54)
+#define S5PV210_GPJ0_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b58)
+#define S5PV210_GPJ1_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b5c)
+#define S5PV210_GPJ2_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b60)
+#define S5PV210_GPJ3_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b64)
+#define S5PV210_GPJ4_INT_FIXPRI (S5PV210_GPIO_BASE + 0x0b68)
+
+
+#define S5PV210_EXT_INT_BASE	(S5PV210_GPIO_BASE + 0x0E00)
+#define S5PV210_PDNEN		(S5PV210_GPIO_BASE + 0x0F80)
+#define S5PC100_PDNEN_NORMAL	(0 << 0)
+
+#define S5PV210_PDNEN_CFG_PDNEN	(1 << 1)
+#define S5PV210_PDNEN_CFG_AUTO	(0 << 1)
+#define S5PV210_PDNEN_POWERDOWN	(1 << 0)
+#define S5PV210_PDNEN_NORMAL	(0 << 0)
+
+/* Common part */
+#define S5P_EINT_BASE			(S5PV210_EXT_INT_BASE)
+
+
 #endif /* __ASM_ARCH_REGS_GPIO_H */
-- 
1.6.3.3



From myungjoo.ham at samsung.com  Mon Jun 14 04:39:15 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Mon, 14 Jun 2010 17:39:15 +0900
Subject: [PATCH 6/6] S5PV210 PM Support Main (suspend-to-mem)
In-Reply-To: <1276504755-24741-6-git-send-email-MyungJoo.Ham@samsung.com>
References: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-2-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-3-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-4-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-5-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-6-git-send-email-MyungJoo.Ham@samsung.com>
Message-ID: <1276504755-24741-7-git-send-email-MyungJoo.Ham@samsung.com>


Signed-off-by: MyungJoo Ham <MyungJoo.Ham at samsung.com>
---
 arch/arm/mach-s5pv210/Makefile               |    4 +
 arch/arm/plat-s5p/Makefile                   |    3 +
 arch/arm/plat-s5p/include/plat/map-s5p.h     |    1 +
 arch/arm/plat-s5p/sleep.S                    |  248 ++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/pm-core.h |   53 ++++++
 arch/arm/plat-samsung/include/plat/pm.h      |   13 ++
 arch/arm/plat-samsung/pm-gpio.c              |    4 +-
 arch/arm/plat-samsung/pm.c                   |   75 +++++++-
 8 files changed, 392 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/plat-s5p/sleep.S
 create mode 100644 arch/arm/plat-samsung/include/plat/pm-core.h

diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 30be9a6..16ca1e9 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -33,3 +33,7 @@ obj-$(CONFIG_S5PV210_SETUP_I2C1) 	+= setup-i2c1.o
 obj-$(CONFIG_S5PV210_SETUP_I2C2) 	+= setup-i2c2.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
+
+# power management support
+
+obj-$(CONFIG_PM)		+= pm.o
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 39c242b..578a4e5 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -18,3 +18,6 @@ obj-y				+= clock.o
 obj-y				+= irq.o
 obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
 
+# CPU support
+
+obj-$(CONFIG_PM)		+= sleep.o
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index 1482852..20b8524 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -24,6 +24,7 @@
 #define S5P_VA_UART3		(S3C_VA_UART + 0xC00)
 
 #define S3C_UART_OFFSET		(0x400)
+#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
 #define VA_VIC(x)		(S3C_VA_IRQ + ((x) * 0x10000))
 #define VA_VIC0			VA_VIC(0)
diff --git a/arch/arm/plat-s5p/sleep.S b/arch/arm/plat-s5p/sleep.S
new file mode 100644
index 0000000..a1e038b
--- /dev/null
+++ b/arch/arm/plat-s5p/sleep.S
@@ -0,0 +1,248 @@
+/* linux/arch/arm/plat-s5pc1xx/sleep.S
+ *
+ * S5PC1XX Power Manager (Suspend-To-RAM) support
+ *
+ * Based on plat-s3c64xx sleep code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <plat/regs-serial.h>
+#include <asm/memory.h>
+
+	.text
+
+	/* s3c_cpu_save
+	 *
+	 * save enough of the CPU state to allow us to re-start
+	 * pm.c code. as we store items like the sp/lr, we will
+	 * end up returning from this function when the cpu resumes
+	 * so the return value is set to mark this.
+	 *
+	 * This arangement means we avoid having to flush the cache
+	 * from this code.
+	 *
+	 * entry:
+	 *	r0 = pointer to save block
+	 *
+	*/
+
+ENTRY(s3c_cpu_save)
+	stmfd	sp!, { r3 - r12, lr }
+
+	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
+	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
+	mrc	p15, 0, r6, c2, c0, 0	@ Translation Table BASE0
+	mrc	p15, 0, r7, c2, c0, 1	@ Translation Table BASE1
+	mrc	p15, 0, r8, c2, c0, 2	@ Translation Table Control
+	mrc	p15, 0, r9, c1, c0, 0	@ Control register
+	mrc	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
+	mrc	p15, 0, r11, c1, c0, 2	@ Co-processor access controls
+	mrc	p15, 0, r12, c10, c2, 0	@ Read PRRR
+	mrc	p15, 0, r3, c10, c2, 1	@ READ NMRR
+
+ ARM(	stmia	r0, { r3 - r13 } )	@ Save CP registers and SP
+ THUMB(	stmia	r0, { r3 - r12 } )	@ Save CP registers and SP
+ THUMB(	str	sp, [ r0, #40 ]	 )
+
+
+	/* save our state to ram  */
+	bl	s3c_pm_cb_flushcache
+
+	/* call final suspend code  */
+	ldr	r0, =pm_cpu_sleep
+	@@ldr	pc, [r0]
+	ldr	r0, [r0]
+	mov	pc, r0
+
+	@@ return to the caller, after having the MMU
+	@@ turned on, this restores the last bits from the
+	@@ stack
+
+	.global resume_with_mmu
+resume_with_mmu:
+
+	/* delete added mmu table list */
+	ldr	r9 , =(PAGE_OFFSET - PHYS_OFFSET)
+	add	r4, r4, r9
+	str	r12, [r4]
+
+	ldmfd	sp!, { r3 - r12, pc }	@ return, from sp from s3c_cpu_save
+
+	.ltorg
+
+	@@ the next bits sit in the .data segment, even though they
+	@@ happen to be code... the s3c_sleep_save_phys needs to be
+	@@ accessed by the resume code before it can restore the MMU.
+	@@ This means that the variable has to be close enough for the
+	@@ code to read it... since the .text segment needs to be RO,
+	@@ the data segment can be the only place to put this code.
+
+	.data
+
+	.global	s3c_sleep_save_phys
+s3c_sleep_save_phys:
+	.word	0
+
+	/* sleep magic, to allow the bootloader to check for an valid
+	 * image to resume to. Must be the first word before the
+	 * s3c_cpu_resume entry.
+	*/
+
+	.word	0x2bedf00d
+
+	/* s3c_cpu_resume
+	 *
+	 * resume code entry for bootloader to call
+	 *
+	 * we must put this code here in the data segment as we have no
+	 * other way of restoring the stack pointer after sleep, and we
+	 * must not write to the code segment (code is read-only)
+	*/
+
+ENTRY(s3c_cpu_resume)
+	mov	r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
+	msr	cpsr_c, r0
+
+	/* Debug
+	*
+	* Serial port configuration code
+	* Use when low-level debug functionality is needed before UARTs
+	* configuratio is restored
+	* It utilizes low-level kernel debug functions (printch,printhex),
+	* so please enable them at kernel config
+	* This code was used with S5PC110 !!!
+	*/
+#ifdef CONFIG_SAMSUNG_PM_DEBUG
+	ldr	r0, =S5P_PA_GPIO
+	ldr     r1, =0x22222222
+	str     r1, [r0, #0x0]                  @S5PC1XX_GPIO_A0_OFFSET
+	ldr     r1, =0x00002222
+	str     r1, [r0, #0x20]                 @S5PC1XX_GPIO_A1_OFFSET
+
+	/* UART_SEL MP0_5[7] at S5PC110 */
+	add     r0, r0, #0x360                  @S5PC1XX_GPIO_MP0_5_OFFSET
+	ldr     r1, [r0, #0x0]                  @S5PC1XX_GPIO_CON_OFFSET
+	bic     r1, r1, #(0xf << 28)            @ 28 = 7 * 4-bit
+	orr     r1, r1, #(0x1 << 28)            @ Output
+	str     r1, [r0, #0x0]                  @S5PC1XX_GPIO_CON_OFFSET
+
+	ldr     r1, [r0, #0x8]                  @S5PC1XX_GPIO_PULL_OFFSET
+	bic     r1, r1, #(0x3 << 14)            @ 14 = 7 * 2-bit
+	orr     r1, r1, #(0x2 << 14)            @ Pull-up enabled
+	str     r1, [r0, #0x8]                  @S5PC1XX_GPIO_PULL_OFFSET
+
+	ldr     r1, [r0, #0x4]                  @S5PC1XX_GPIO_DAT_OFFSET
+	orr     r1, r1, #(1 << 7)               @ 7 = 7 * 1-bit
+	str     r1, [r0, #0x4]                  @S5PC1XX_GPIO_DAT_OFFSET
+
+	ldr     r0, =S3C_PA_UART                 @ S5PC110_PA_UART
+	add	r0, r0, #(0x400 * CONFIG_DEBUG_S3C_UART) @
+	mov     r1, #0x3
+	str     r1, [r0, #0x000]                @ ULCON
+	ldr     r1, =0x245
+	str     r1, [r0, #0x004]                @ UCON
+	mov     r1, #0x23
+	str     r1, [r0, #0x028]                @ UBRDIV
+	mov     r1, #0x3
+	str     r1, [r0, #0x02C]                @ UDIVSLOT
+
+	mov r0, #'_'
+	bl printch
+
+	mov r0, #'_'
+	bl printch
+
+	mov r0, #'W'
+	bl printch
+
+	mov r0, #'_'
+	bl printch
+
+	mov r0, #'_'
+	bl printch
+
+	mov r0, #'\n'
+	bl printch
+
+#endif
+	mov	r1, #0
+	mcr	p15, 0, r1, c8, c7, 0	@ Invalidate TLBs
+	mcr	p15, 0, r1, c7, c5, 0	@ Invalidate I Cache
+
+ ARM(	ldr	r0, s3c_sleep_save_phys		)
+ THUMB( adr.w	r0, s3c_sleep_save_phys		)
+ THUMB(	ldr	r0, [r0]			)
+
+ ARM(	ldmia	r0, { r3 - r13 } )	@ reload regs and SPI
+ THUMB(	ldmia	r0, { r3 - r12 } )	@ reload regs and SPI
+ THUMB(	ldr	sp, [ r0, #40 ]	 )
+
+	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
+	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
+	mcr	p15, 0, r8, c2, c0, 2	@ Translation Table Control
+	mcr	p15, 0, r7, c2, c0, 1	@ Translation Table BASE1
+	mcr	p15, 0, r6, c2, c0, 0	@ Translation Table BASE0
+	mcr	p15, 0, r10, c1, c0, 1	@ Auxiliary control register
+
+	mov	r0, #0
+	mcr	p15, 0, r0, c8, c7, 0	@ Invalidate I & D TLB
+
+	mov	r0, #0
+	mcr	p15, 0, r11, c1, c0, 2	@ Co-processor access controls
+	mcr	p15, 0, r0, c7, c5, 4
+
+	mcr	p15, 0, r12, c10, c2, 0	@ write PRRR
+	mcr	p15, 0, r3, c10, c2, 1	@ write NMRR
+
+
+	/* calculate first section address into r8 */
+	mov	r4, r6
+	ldr	r5, =0x3fff
+	bic	r4, r4, r5
+	/* read data from INFORM0 */
+	ldr	r11, =S5P_PA_INFORM0
+
+	ldr	r10, [r11, #0]
+	mov	r10, r10 ,LSR #18
+	bic	r10, r10, #0x3
+	orr	r4, r4, r10
+
+	/* calculate mmu list value into r9 */
+	mov	r10, r10, LSL #18
+	ldr	r5, =0x40e
+	orr	r10, r10, r5
+
+	/* back up originally data */
+
+	ldr	r12, [r4]
+
+	/* Added list about mmu */
+	str	r10, [r4]
+
+	ldr	r2, =resume_with_mmu
+	mcr	p15, 0, r9, c1, c0, 0		@ turn on MMU, etc
+
+	isb
+	mov	pc, r2				@ go back to virtual address
+
+	.ltorg
diff --git a/arch/arm/plat-samsung/include/plat/pm-core.h b/arch/arm/plat-samsung/include/plat/pm-core.h
new file mode 100644
index 0000000..df282c5
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pm-core.h
@@ -0,0 +1,53 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/pm-core.h
+ *
+ * S5PC1XX - PM core support for arch/arm/plat-s3c/pm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+#include <plat/cpu.h>
+
+#define s3c_irqwake_eintallow	(ULONG_MAX)
+#define s3c_irqwake_intallow	(0)
+
+static inline void s3c_pm_debug_init_uart(void)
+{
+	u32 tmp = __raw_readl(S5P_CLKGATE_IP3);
+
+	/* As a note, since the S5PC1XX UARTs generally have multiple
+	 * clock sources, we simply enable PCLK at the moment and hope
+	 * that the resume settings for the UART are suitable for the
+	 * use with PCLK.
+	 */
+
+	tmp |= S5P_CLKGATE_IP3_UART0;
+	tmp |= S5P_CLKGATE_IP3_UART1;
+	tmp |= S5P_CLKGATE_IP3_UART2;
+	tmp |= S5P_CLKGATE_IP3_UART3;
+
+	__raw_writel(tmp, S5P_CLKGATE_IP3);
+	udelay(10);
+}
+
+static inline void s3c_pm_arch_prepare_irqs(void)
+{
+}
+
+static inline void s3c_pm_arch_stop_clocks(void)
+{
+}
+
+static inline void s3c_pm_arch_show_resume_irqs(void)
+{
+	S3C_PMDBG("sleep: wakeup source (WAKEUP_STAT): %8.8xh\n",
+		__raw_readl(S5P_WAKEUP_STAT));
+}
+
+static inline void s3c_pm_arch_update_uart(void __iomem *regs,
+					   struct pm_uart_save *save)
+{
+}
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h
index 245836d..ac0bc65 100644
--- a/arch/arm/plat-samsung/include/plat/pm.h
+++ b/arch/arm/plat-samsung/include/plat/pm.h
@@ -39,6 +39,7 @@ extern unsigned long s3c_irqwake_eintallow;
 
 extern void (*pm_cpu_prep)(void);
 extern void (*pm_cpu_sleep)(void);
+extern void (*pm_cpu_finish)(void);
 
 /* Flags for PM Control */
 
@@ -73,6 +74,12 @@ struct sleep_save {
 #define SAVE_ITEM(x) \
 	{ .reg = (x) }
 
+#define SAVE_GPIO_INT(x)                \
+	SAVE_ITEM((x)),                 \
+	SAVE_ITEM((x) + 0x100),         \
+	SAVE_ITEM((x) + 0x200),         \
+	SAVE_ITEM((x) + 0x300)
+
 /**
  * struct pm_uart_save - save block for core UART
  * @ulcon: Save value for S3C2410_ULCON
@@ -161,6 +168,9 @@ extern void s3c_pm_check_store(void);
  */
 extern void s3c_pm_configure_extint(void);
 
+extern void s3c_pm_configure_int(void);
+
+
 /**
  * s3c_pm_restore_gpios() - restore the state of the gpios after sleep.
  *
@@ -187,3 +197,6 @@ extern void s3c_pm_cb_flushcache(void);
 
 extern void s3c_pm_save_core(void);
 extern void s3c_pm_restore_core(void);
+
+extern void s3c_pm_wakeup_source(unsigned int *internal,
+		unsigned int *external);
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c
index 7df03f8..1b9529a 100644
--- a/arch/arm/plat-samsung/pm-gpio.c
+++ b/arch/arm/plat-samsung/pm-gpio.c
@@ -192,7 +192,7 @@ struct s3c_gpio_pm s3c_gpio_pm_2bit = {
 	.resume = s3c_gpio_pm_2bit_resume,
 };
 
-#ifdef CONFIG_ARCH_S3C64XX
+#if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_ARCH_S5PV210)
 static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip)
 {
 	chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON);
@@ -302,7 +302,7 @@ struct s3c_gpio_pm s3c_gpio_pm_4bit = {
 	.save	= s3c_gpio_pm_4bit_save,
 	.resume = s3c_gpio_pm_4bit_resume,
 };
-#endif /* CONFIG_ARCH_S3C64XX */
+#endif /* CONFIG_ARCH_S3C64XX || CONFIG_ARCH_S5PV210 */
 
 /**
  * s3c_pm_save_gpio() - save gpio chip data for suspend
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 27cfca5..503e3bd 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -26,10 +26,16 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-irq.h>
+#include <mach/irqs.h>
 #include <asm/irq.h>
 
 #include <plat/pm.h>
+#ifdef CONFIG_CPU_S5PV210
+#include <plat/pm-core.h>
+#else
 #include <mach/pm-core.h>
+#endif
+#include <plat/gpio-ext.h>
 
 /* for external use */
 
@@ -231,6 +237,27 @@ static void s3c_pm_show_resume_irqs(int start, unsigned long which,
 
 void (*pm_cpu_prep)(void);
 void (*pm_cpu_sleep)(void);
+void (*pm_cpu_finish)(void);
+
+unsigned int s3c_pm_wakeup_source_save_int;
+unsigned int s3c_pm_wakeup_source_save_ext;
+static void s3c_pm_wakeup_source_set(unsigned int internal,
+		unsigned int external)
+{
+	s3c_pm_wakeup_source_save_int = internal & ~s3c_irqwake_intmask;
+	if (internal & 0x01)
+		s3c_pm_wakeup_source_save_ext = external &
+			~s3c_irqwake_eintmask;
+	else
+		s3c_pm_wakeup_source_save_ext = 0;
+}
+
+void s3c_pm_wakeup_source(unsigned int *internal,
+		unsigned int *external)
+{
+	*internal = s3c_pm_wakeup_source_save_int;
+	*external = s3c_pm_wakeup_source_save_ext;
+}
 
 #define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
 
@@ -259,6 +286,11 @@ static int s3c_pm_enter(suspend_state_t state)
 	 * require a full power-cycle)
 	*/
 
+	/* set the irq configuration for wake */
+	s3c_irqwake_intmask = 0xFFDD;
+	s3c_pm_configure_int();
+	s3c_pm_configure_extint();
+
 	if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
 	    !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
 		printk(KERN_ERR "%s: No wake-up sources!\n", __func__);
@@ -270,19 +302,20 @@ static int s3c_pm_enter(suspend_state_t state)
 
 	s3c_sleep_save_phys = virt_to_phys(regs_save);
 
-	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
-
 	/* save all necessary core registers not covered by the drivers */
 
 	s3c_pm_save_gpios();
 	s3c_pm_save_uarts();
 	s3c_pm_save_core();
 
-	/* set the irq configuration for wake */
 
-	s3c_pm_configure_extint();
+	/* For the future use with deep idle */
+	__raw_writel(virt_to_phys(regs_save), S5P_INFORM2);
+	__raw_writel(0, S5P_INFORM1);
+
+	S3C_PMDBG("s3c_sleep_save_phys=0x%08lx\n", s3c_sleep_save_phys);
 
-	S3C_PMDBG("sleep: irq wakeup masks: %08lx,%08lx\n",
+	S3C_PMDBG("sleep: IRQ wakeup masks: %08lx,%08lx\n",
 	    s3c_irqwake_intmask, s3c_irqwake_eintmask);
 
 	s3c_pm_arch_prepare_irqs();
@@ -312,11 +345,11 @@ static int s3c_pm_enter(suspend_state_t state)
 	cpu_init();
 
 	/* restore the system state */
-
 	s3c_pm_restore_core();
 	s3c_pm_restore_uarts();
 	s3c_pm_restore_gpios();
 
+
 	s3c_pm_debug_init();
 
 	/* check what irq (if any) restored the system */
@@ -325,11 +358,36 @@ static int s3c_pm_enter(suspend_state_t state)
 
 	S3C_PMDBG("%s: post sleep, preparing to return\n", __func__);
 
+	__raw_writel(__raw_readl(S5P_OTHERS) | (1<<31) | (1<<30) | (1<<29) |
+		(1<<28), S5P_OTHERS);
+
+	/* WAKEUP STAT */
+	printk(KERN_INFO "Wakeup Stat: %8.8xh\n", __raw_readl(S5P_WAKEUP_STAT));
+
 	/* LEDs should now be 1110 */
 	s3c_pm_debug_smdkled(1 << 1, 0);
 
 	s3c_pm_check_restore();
 
+	/* If ext int is the wakeup source... */
+	if (__raw_readl(S5P_WAKEUP_STAT) & 0x01) { /* EXTINT */
+		/* If HOME or HOLD key pressed, trigger an event manually */
+
+		S3C_PMDBG("EXT INT SOURCE = %2.2x %2.2x %2.2x %2.2x\n",
+				__raw_readl(S5P_WKUP_INT_PEND24_31),
+				__raw_readl(S5P_WKUP_INT_PEND16_23),
+				__raw_readl(S5P_WKUP_INT_PEND8_15),
+				__raw_readl(S5P_WKUP_INT_PEND0_7));
+
+		s3c_pm_wakeup_source_set(__raw_readl(S5P_WAKEUP_STAT),
+				__raw_readl(S5P_WKUP_INT_PEND24_31)<<24 |
+				__raw_readl(S5P_WKUP_INT_PEND16_23)<<16 |
+				__raw_readl(S5P_WKUP_INT_PEND8_15)<<8 |
+				__raw_readl(S5P_WKUP_INT_PEND0_7)<<0);
+	}
+	else
+		s3c_pm_wakeup_source_set(__raw_readl(S5P_WAKEUP_STAT), 0);
+
 	/* ok, let's return from sleep */
 
 	S3C_PMDBG("S3C PM Resume (post-restore)\n");
@@ -353,11 +411,14 @@ static int s3c_pm_prepare(void)
 static void s3c_pm_finish(void)
 {
 	s3c_pm_check_cleanup();
+
+	if (pm_cpu_finish)
+		pm_cpu_finish();
 }
 
 static struct platform_suspend_ops s3c_pm_ops = {
-	.enter		= s3c_pm_enter,
 	.prepare	= s3c_pm_prepare,
+	.enter		= s3c_pm_enter,
 	.finish		= s3c_pm_finish,
 	.valid		= suspend_valid_only_mem,
 };
-- 
1.6.3.3



From u.kleine-koenig at pengutronix.de  Mon Jun 14 04:43:51 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 14 Jun 2010 10:43:51 +0200
Subject: [PATCH] mxc_nand: fix PM
In-Reply-To: <1274982919-13251-1-git-send-email-eric@eukrea.com>
References: <1274942000-3580-2-git-send-email-eric@eukrea.com>
	<1274982919-13251-1-git-send-email-eric@eukrea.com>
Message-ID: <20100614084351.GC12159@pengutronix.de>

Hello Eric,

On Thu, May 27, 2010 at 07:55:19PM +0200, Eric B?nard wrote:
> * when resuming, we get the following log :
> nand_resume called for a chip which is not in suspended state
> * this happens because mtd->suspend and mtd->resume are already
> called from the mtd layer, thus they were called a second time
> in mxc_nand so mtd complains when trying to resume for the
> second time
> * the fix is to remove these call and thus remove the supend and
> resume functions of mxc_nand
the commit log looks IMHO ugly.  Better make it (including Subject):

mtd/mxc_nand: don't call mtd->{suspend,resume} explicitly

The mtd layer is responsible to call mtd->{suspend,resume}.  Doing it
again in the driver is wrong and results in a warning:

	nand_resume called for a chip which is not in suspended state

at resume time.  Removing the calls from the resume and suspend
functions makes them empty allowing them to be deleted completely.

Signed-off-by: Eric B?nard <eric at eukrea.com>
Acked-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-mtd at lists.infradead.org

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From benh at kernel.crashing.org  Mon Jun 14 05:22:58 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Mon, 14 Jun 2010 19:22:58 +1000
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19477.52889.982995.407051@ipc1.ka-ro>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
	<1276319643.1962.181.camel@pasglop>
	<19477.52889.982995.407051@ipc1.ka-ro>
Message-ID: <1276507378.2552.39.camel@pasglop>

On Mon, 2010-06-14 at 08:39 +0200, Lothar Wa?mann wrote:
> All implementations so far use spin_lock_irq_save()!

Nothing prevents your implementation to be a tad smarter.

> How would you be able to sleep with a mutex held?
> If you hold a lock you must not sleep, no matter what sort of lock it
> is. 

You can perfectly sleep with a mutex held. You -do- have to be careful
of course to ensure you aren't going to do silly thing like re-enter and
try to take it twice, or A->B B->A deadlocks, but in the typical case of
wanting to use a msleep rather than udelay, it works very well :-)

Cheers,
Ben.




From linux at arm.linux.org.uk  Mon Jun 14 05:25:59 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 14 Jun 2010 10:25:59 +0100
Subject: Request review of device tree documentation
In-Reply-To: <4C15DE2E.1050905@firmworks.com>
References: <1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<1276408773.1962.574.camel@pasglop>
	<AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com>
	<20100614073828.GA6095@n2100.arm.linux.org.uk>
	<4C15DE2E.1050905@firmworks.com>
Message-ID: <20100614092559.GA7881@n2100.arm.linux.org.uk>

On Sun, Jun 13, 2010 at 09:45:50PM -1000, Mitch Bradley wrote:
> None of this is a deal-breaker for the kind of debugging tasks that are  
> the primary use case for the callback.

Would you mind explaining what kind of tasks these callbacks will
be used for?


From LW at KARO-electronics.de  Mon Jun 14 05:30:08 2010
From: LW at KARO-electronics.de (=?iso-8859-15?Q?Lothar_Wa=DFmann?=)
Date: Mon, 14 Jun 2010 11:30:08 +0200
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <1276507378.2552.39.camel@pasglop>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
	<1276319643.1962.181.camel@pasglop>
	<19477.52889.982995.407051@ipc1.ka-ro>
	<1276507378.2552.39.camel@pasglop>
Message-ID: <19477.63136.664249.167207@ipc1.ka-ro>

Benjamin Herrenschmidt writes:
> On Mon, 2010-06-14 at 08:39 +0200, Lothar Wa?mann wrote:
> > All implementations so far use spin_lock_irq_save()!
> 
> Nothing prevents your implementation to be a tad smarter.
> 
I vote for consistency, so that device drivers can be kept arch
independent instead of having to care about implentation details of
each arch.


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From buytenh at wantstofly.org  Mon Jun 14 05:32:37 2010
From: buytenh at wantstofly.org (Lennert Buytenhek)
Date: Mon, 14 Jun 2010 11:32:37 +0200
Subject: [PATCH 1/2 v2] mv643xx_eth: use sw csum for big packets
In-Reply-To: <FCBE654890C0334289D0AD3AF4EF009F9FAC7B6E2B@IL-MB01.marvell.com>
References: <FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>
	<1276073483-17208-1-git-send-email-saeed@marvell.com>
	<20100610064330.GK1743@mail.wantstofly.org>
	<FCBE654890C0334289D0AD3AF4EF009F9FAC75AA96@IL-MB01.marvell.com>
	<20100612083137.GO1743@mail.wantstofly.org>
	<FCBE654890C0334289D0AD3AF4EF009F9FAC7B6E2B@IL-MB01.marvell.com>
Message-ID: <20100614093237.GG14513@mail.wantstofly.org>

On Sun, Jun 13, 2010 at 10:38:10AM +0300, Saeed Bishara wrote:

> >> >> @@ -2666,6 +2668,9 @@ static int 
> >> >mv643xx_eth_shared_probe(struct platform_device *pdev)
> >> >>  	 * Detect hardware parameters.
> >> >>  	 */
> >> >>  	msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk 
> >> >: 133000000;
> >> >> +	msp->tx_csum_limit = pd->tx_csum_limit ? 
> >> >pd->tx_csum_limit : 9 * 1024;
> >> >> +	/* add header count so we can compare against skb->len */
> >> >> +	msp->tx_csum_limit += ETH_HLEN;
> >> >>  	infer_hw_params(msp);
> >> >
> >> >Is the limit 9 * 1024 + 14 for the whole packet, or 9 * 
> >1024 for the IP
> >> >part?
> >>
> >> the limit is for the IP part, but I thought that adding the 
> >header length, then comparing agains skb->len will be the 
> >same. What do you suggest?
> >
> >Right, but for the header length you take 14, while if to include VLAN
> >tags or DSA tags the header might actually be longer -- how does that
> >affect the ability of the hardware to compute the checksum?
> >
> >I.e. is the restriction "total packet length must be < N + 14 bytes"
> >or is it "the IP part must be < N bytes and it doesn't matter whether
> >there are VLAN tags or not"?
>
> It's the second option: "the IP part must be < N" regardless to the L2 header.

Then I suppose you want to do something like:

	int hdr_len;
	int tag_bytes;

	hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
	tag_bytes = hdr_len - 4;
	if (skb->len - hdr_len > the limit || unlikely(tag_bytes & ~12)) {

(And then keep the limit as maximum number of bytes in the packet
starting from the IP header part.)


From u.kleine-koenig at pengutronix.de  Mon Jun 14 05:34:59 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 14 Jun 2010 11:34:59 +0200
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19477.53673.644128.558827@ipc1.ka-ro>
References: <201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
	<1276319643.1962.181.camel@pasglop>
	<19477.52889.982995.407051@ipc1.ka-ro>
	<20100614064028.GA12159@pengutronix.de>
	<19477.53673.644128.558827@ipc1.ka-ro>
Message-ID: <20100614093459.GD12159@pengutronix.de>

Hello,

> And arch/arm/plat-s3c/clock.c has the following comment:
> |/* We originally used an mutex here, but some contexts (see resume)
> | * are calling functions such as clk_set_parent() with IRQs disabled
> | * causing an BUG to be triggered.
> | */
> |DEFINE_SPINLOCK(clocks_lock);
I wonder why it's needed to reparent clocks during resume.  And where
exactly IRQs are disabled.  Hmm, this comment was initially introduced
by v2.6.28-rc7-180-gc3391e3, its commit log talks about cpufreq, not
resume.

Ben (Dooks): Is this still relevant?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From benh at kernel.crashing.org  Mon Jun 14 05:36:10 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Mon, 14 Jun 2010 19:36:10 +1000
Subject: Request review of device tree documentation
In-Reply-To: <20100614092559.GA7881@n2100.arm.linux.org.uk>
References: <1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com> <1276408773.1962.574.camel@pasglop>
	<AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com>
	<20100614073828.GA6095@n2100.arm.linux.org.uk>
	<4C15DE2E.1050905@firmworks.com>
	<20100614092559.GA7881@n2100.arm.linux.org.uk>
Message-ID: <1276508170.2552.43.camel@pasglop>

On Mon, 2010-06-14 at 10:25 +0100, Russell King - ARM Linux wrote:
> On Sun, Jun 13, 2010 at 09:45:50PM -1000, Mitch Bradley wrote:
> > None of this is a deal-breaker for the kind of debugging tasks that are  
> > the primary use case for the callback.
> 
> Would you mind explaining what kind of tasks these callbacks will
> be used for?

That's one of the thing I'm "touching" on in my previous reply...

(For those who didn't quite follow, the discussion here is about
allowing a real Open Firmware implementation on ARM with the feature of
leaving OF alive while the OS is up, which is something sparc does but
we never supported on ppc).

Ideally, if you keep open firmware alive, you can drop into it when the
kernel crashes for example, or in some other circumstances.

However, there's a lot of room for abuse here and I'm worried that if it
becomes widespread, we'll start seeing vendors use that as a way to do
some kind of HAL and hide various platform methods in there (clock
control, nvram, etc...).

Another option Mitch mentioned is to have the f-code interpreter (f-code
is OF tokenized forth format) in the kernel, but that doesn't completely
solve the problem of providing it with appropriate virtual mappings,
arbitrating access to HW resources, etc etc etc

OF as a FW/bootloader is great. OF alive along with the OS can be a nice
debugging tool under some circumstances but I am a bit more dubious as
to whether that's going to work out in practice. But I'd like to -not-
see it abused as some kind of HAL.

Cheers,
Ben.




From u.kleine-koenig at pengutronix.de  Mon Jun 14 05:43:10 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 14 Jun 2010 11:43:10 +0200
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19477.63136.664249.167207@ipc1.ka-ro>
References: <201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
	<1276319643.1962.181.camel@pasglop>
	<19477.52889.982995.407051@ipc1.ka-ro>
	<1276507378.2552.39.camel@pasglop>
	<19477.63136.664249.167207@ipc1.ka-ro>
Message-ID: <20100614094310.GE12159@pengutronix.de>

On Mon, Jun 14, 2010 at 11:30:08AM +0200, Lothar Wa?mann wrote:
> Benjamin Herrenschmidt writes:
> > On Mon, 2010-06-14 at 08:39 +0200, Lothar Wa?mann wrote:
> > > All implementations so far use spin_lock_irq_save()!
> > 
> > Nothing prevents your implementation to be a tad smarter.
> > 
> I vote for consistency, so that device drivers can be kept arch
> independent instead of having to care about implentation details of
> each arch.
Back when I implemented clock support for ns9xxx (unfortunately not in
mainline) I tried with a spinlock first and later switched to a mutex.
IIRC the reason was that on ns9215 enabling the rtc clock took long
(don't remember a number) and successfull enabling was signaled by an
irq.  So I would have had to implement irq polling in the clock code.

I think you can find different examples that make both possiblities bad.
All in all I think that a sleeping clock implementation is preferable as
it improves (general) latencies.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From linux at arm.linux.org.uk  Mon Jun 14 05:47:40 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 14 Jun 2010 10:47:40 +0100
Subject: Request review of device tree documentation
In-Reply-To: <1276508170.2552.43.camel@pasglop>
References: <4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<1276408773.1962.574.camel@pasglop>
	<AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com>
	<20100614073828.GA6095@n2100.arm.linux.org.uk>
	<4C15DE2E.1050905@firmworks.com>
	<20100614092559.GA7881@n2100.arm.linux.org.uk>
	<1276508170.2552.43.camel@pasglop>
Message-ID: <20100614094740.GB7881@n2100.arm.linux.org.uk>

On Mon, Jun 14, 2010 at 07:36:10PM +1000, Benjamin Herrenschmidt wrote:
> However, there's a lot of room for abuse here and I'm worried that if it
> becomes widespread, we'll start seeing vendors use that as a way to do
> some kind of HAL and hide various platform methods in there (clock
> control, nvram, etc...).

This is what I'm worried about too.

As I said in my first reply in this thread, calling out from the kernel
will kill performance due to the time taken to shut down the caches and
MMU, which can only be done safely with all exceptions turned off.

The only time that it can be seriously considered is if you're calling
out to reboot, shutdown or kexec.


From ryan at bluewatersys.com  Mon Jun 14 06:17:59 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Mon, 14 Jun 2010 22:17:59 +1200
Subject: [PATCH 2/5] SPEAR3xx: Rename register/irq defines to remove naming
	conflicts
In-Reply-To: <4C15C22A.7070408@st.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
	<1275717955-14545-3-git-send-email-ryan@bluewatersys.com>
	<4C15BB99.4060108@st.com> <4C15BFDC.70809@bluewatersys.com>
	<4C15C22A.7070408@st.com>
Message-ID: <4C1601D7.1080404@bluewatersys.com>

Viresh KUMAR wrote:
> On 6/14/2010 11:06 AM, Ryan Mallon wrote:
>> The goal of the patch series is to allow all a single kernel to have
>> support for all of the spear platforms, ie CONFIG_MACH_SPEAR300,
>> CONFIG_MACH_SPEAR310 and CONFIG_MACH_SPEAR320 can all be set.
>>
>> The current code has duplicate defines in
>> arch/arm/mach-spear3xx/include/mach/spear3[012]0.h which means that
>> these three files cannot be included at once (they are included from
>> arch/arm/mach-spear3xx/include/mach/spear.h).
> 
> I understood what you did, but i am not sure how will it actually work.
> I tried to look into kernel source but couldn't find much.
> 
> Suppose all three machines/boards are selected and we got one kernel.
> Then how should we tell the kernel which machines init routine to be called.
> I suppose through uboot only, but not sure how it internally works.
> 
> Can you please help me understand that?

The machine id is passed in register r1 by the boot loader, which
matches the id in the MACHINE_START descriptors in the board files. Many
of the other arm sub-architectures already allow multiple
boards/implementations to be compiled into a single kernel and selected
at runtime.

~Ryan



From mcuelenaere at gmail.com  Mon Jun 14 06:18:24 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Mon, 14 Jun 2010 12:18:24 +0200
Subject: [PATCH v2] rtc-s3c: Fix rtc-s3c driver initialization
In-Reply-To: <201006140904.17950.anarsoul@gmail.com>
References: <1274975846-14006-1-git-send-email-anarsoul@gmail.com>
	<201006140904.17950.anarsoul@gmail.com>
Message-ID: <4C1601F0.1060209@gmail.com>

Op 14-06-10 08:04, Vasily Khoruzhick schreef:
> ? ????????? ?? 27 ??? 2010 18:57:26 ????? Vasily Khoruzhick ???????:
>> setfreq should be called only after rtc device registration,
>> as it uses rtc device; s3c_rtc_cpu_type should be checked
>> only once it was set.
>>
>> Signed-off-by: Vasily Khoruzhick <anarsoul at gmail.com>
> 
> Hi, Ben.
> 
> What about this patch? I've seen similar series on linux-samsung-soc maillist, 
> but neither their series nor my patch is applied to your tree. Why? :)
> 
> Regards
> Vasily

A similar patch is already in Linus' tree, see e893de59a4982791368b3ce412bc67dd601a88a0.


From jeremy.kerr at canonical.com  Mon Jun 14 06:18:24 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Mon, 14 Jun 2010 18:18:24 +0800
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100611042046.GA31045@fluff.org.uk>
References: <1275636608.606606.450179637764.0.gpush@pororo>
	<1275636608.607067.417709988883.1.gpush@pororo>
	<20100611042046.GA31045@fluff.org.uk>
Message-ID: <201006141818.26954.jeremy.kerr@canonical.com>

Hi Ben,

I've just pushed to my clk-common branch, mostly involving the changes we've 
discussed so far.

http://kernel.ubuntu.com/git?p=jk/dt/linux-2.6.git;a=commitdiff;h=f2c5141c88aa4c5ba82aee1b5b8abe5e9ff09146

The clk-common-mx51 and clk-common-versatile branches both contain basic ports 
of the mx51 and versatile platforms to the new clock infrastructure.

Cheers,


Jeremy


From mcuelenaere at gmail.com  Mon Jun 14 06:18:24 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Mon, 14 Jun 2010 12:18:24 +0200
Subject: [PATCH v2] rtc-s3c: Fix rtc-s3c driver initialization
In-Reply-To: <201006140904.17950.anarsoul@gmail.com>
References: <1274975846-14006-1-git-send-email-anarsoul@gmail.com>
	<201006140904.17950.anarsoul@gmail.com>
Message-ID: <4C1601F0.1060209@gmail.com>

Op 14-06-10 08:04, Vasily Khoruzhick schreef:
> ? ????????? ?? 27 ??? 2010 18:57:26 ????? Vasily Khoruzhick ???????:
>> setfreq should be called only after rtc device registration,
>> as it uses rtc device; s3c_rtc_cpu_type should be checked
>> only once it was set.
>>
>> Signed-off-by: Vasily Khoruzhick <anarsoul at gmail.com>
> 
> Hi, Ben.
> 
> What about this patch? I've seen similar series on linux-samsung-soc maillist, 
> but neither their series nor my patch is applied to your tree. Why? :)
> 
> Regards
> Vasily

A similar patch is already in Linus' tree, see e893de59a4982791368b3ce412bc67dd601a88a0.



From eric.y.miao at gmail.com  Mon Jun 14 06:19:30 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 14 Jun 2010 18:19:30 +0800
Subject: [PATCH] [ARM] pxa/corgi: fix MMC/SD card detection failure
Message-ID: <1276510770-27748-1-git-send-email-eric.y.miao@gmail.com>

Reported-by: Andrea Adami <andrea.adami at gmail.com>
Signed-off-by: Eric Miao <eric.y.miao at gmail.com>
---
 arch/arm/mach-pxa/corgi.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 3d1dcb9..51ffa6a 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -446,7 +446,7 @@ static struct platform_device corgiled_device = {
 static struct pxamci_platform_data corgi_mci_platform_data = {
 	.detect_delay_ms	= 250,
 	.ocr_mask		= MMC_VDD_32_33|MMC_VDD_33_34,
-	.gpio_card_detect	= -1,
+	.gpio_card_detect	= CORGI_GPIO_nSD_DETECT,
 	.gpio_card_ro		= CORGI_GPIO_nSD_WP,
 	.gpio_power		= CORGI_GPIO_SD_PWR,
 };
-- 
1.7.1.251.g92a7



From anarsoul at gmail.com  Mon Jun 14 06:38:40 2010
From: anarsoul at gmail.com (Vasily Khoruzhick)
Date: Mon, 14 Jun 2010 13:38:40 +0300
Subject: [PATCH v2] rtc-s3c: Fix rtc-s3c driver initialization
In-Reply-To: <4C1601F0.1060209@gmail.com>
References: <1274975846-14006-1-git-send-email-anarsoul@gmail.com>
	<201006140904.17950.anarsoul@gmail.com>
	<4C1601F0.1060209@gmail.com>
Message-ID: <201006141338.47947.anarsoul@gmail.com>

? ????????? ?? 14 ???? 2010 13:18:24 ????? Maurus Cuelenaere ???????:
> A similar patch is already in Linus' tree, see
> e893de59a4982791368b3ce412bc67dd601a88a0.

Thanks for pointing that.
Sad that this change is not in Ben's next-samsung yet :(

Regards
Vasily
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From mcuelenaere at gmail.com  Mon Jun 14 06:44:43 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Mon, 14 Jun 2010 12:44:43 +0200
Subject: [PATCH v2] rtc-s3c: Fix rtc-s3c driver initialization
In-Reply-To: <201006141338.47947.anarsoul@gmail.com>
References: <1274975846-14006-1-git-send-email-anarsoul@gmail.com>
	<201006140904.17950.anarsoul@gmail.com>
	<4C1601F0.1060209@gmail.com>
	<201006141338.47947.anarsoul@gmail.com>
Message-ID: <4C16081B.3030907@gmail.com>

Op 14-06-10 12:38, Vasily Khoruzhick schreef:
> ? ????????? ?? 14 ???? 2010 13:18:24 ????? Maurus Cuelenaere ???????:
>   
>> A similar patch is already in Linus' tree, see
>> e893de59a4982791368b3ce412bc67dd601a88a0.
>>     
> Thanks for pointing that.
> Sad that this change is not in Ben's next-samsung yet :(
>   

It's just a matter of rebasing. And AFAICS current Ben's next-samsung ==
Linus' 2.6.35-rc1 tag.

-- 
Maurus Cuelenaere



From mcuelenaere at gmail.com  Mon Jun 14 07:31:16 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Mon, 14 Jun 2010 13:31:16 +0200
Subject: S3C FB pixclock calculation
Message-ID: <4C161304.70903@gmail.com>

Hi,

one thing that has bothered me for some time is the fb pixclock value: this
seems rather arbitrary and undocumented (couldn't find it in the datasheets).

Though I did find an "algorithm", which I've used in the SmartQ machs for the
calculation of this value (I can't remember where I found it, I think it was in
the original SmartQ kernels).

So I made this small patch which does the calculation in the s3c fb driver
itself when the pixclock pdata hasn't been set (see below).

I've checked this against the SMDK6410 value (and ANW6410 and HMT, which are
identical) and it seems to match so I *think* this is correct, but as it's
undocumented I'm not sure.

Is anyone able to tell me whether I'm correct? (if so, I'll clean up this patch
and send it for inclusion)

--
Maurus Cuelenaere

diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 9682ecc..17d882f 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -235,6 +235,22 @@ static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
 	return result;
 }

+static void s3c_fb_missing_pixclock(struct fb_videomode *mode)
+{
+	u64 pixclk = 1000000000000ULL;
+	u32 div;
+
+	div  = mode->left_margin + mode->hsync_len + mode->right_margin +
+	       mode->xres;
+	div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +
+	       mode->yres;
+	div *= mode->refresh ? : 80;
+
+	do_div(pixclk, div);
+
+	mode->pixclock = pixclk;
+}
+
 /**
  * s3c_fb_align_word() - align pixel count to word boundary
  * @bpp: The number of bits per pixel
@@ -925,6 +941,9 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev)
 		if (!pd->win[win])
 			continue;

+		if (!pd->win[win]->win_mode.pixclock)
+			s3c_fb_missing_pixclock(&pd->win[win]->win_mode);
+
 		ret = s3c_fb_probe_win(sfb, win, &sfb->windows[win]);
 		if (ret < 0) {
 			dev_err(dev, "failed to create window %d\n", win);




From david at gibson.dropbear.id.au  Mon Jun 14 08:44:38 2010
From: david at gibson.dropbear.id.au (David Gibson)
Date: Mon, 14 Jun 2010 22:44:38 +1000
Subject: Request review of device tree documentation
In-Reply-To: <AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
References: <33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com>
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com>
	<4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
Message-ID: <20100614124438.GF9323@yookeroo>

On Sun, Jun 13, 2010 at 11:02:15PM -0600, Grant Likely wrote:
[sni]
> > That's sort of a self-fulfilling prophecy. ?If the OS doesn't trust the
> > firmware, there is no pressure for the firmware to "get it right".
> 
> Firmware will not get it right.  Period.  There will always be
> something wrong.  It is never right on PCs.  It will never be right on
> the other architectures.

Yes, yes, yes.  And there is a great deal of empirical evidence to
back that assertion.

>  That goes for OSes too, but upgrading an OS
> isn't as risky as upgrading firmware.  That isn't to say that it can't
> be close, but every firmware feature that the OS depends on is a
> feature that could force a risky firmware upgrade when the bug in it
> is discovered.

Indeed.  In fact, the general rule of thumb is really "put as much as
possible into the most easily replaced layer of the stack".  This is,
incidentally, why I've always been dubious about simple firmwares
supplying a flattened device tree rather than including the device
tree template in the kernel, cuboot style.

> I'm also convinced that the economics are all wrong for "getting it
> right" when talking about firmware.  Manufactures don't care about
> firmware; they care about selling boxes.  Customers don't care about
> firmware, they care about the operating system (well, that's not true
> either, they care about applications).  For manufactures, once it can
> boot the real operating system, there is little to no incentive to
> spend any more money on firmware when the money can be better spent on
> either the next product or the adding features to the operating system
> of the existing product.  In fact, spending money on firmware is
> actually *more risky* one a product ships, because if a firmware
> upgrade goes bad, then that means product returned for repair at the
> factory.

A good analysis.  The other side of this, is that for an OS, if you
rely on the firmware to do X, it will work when the firmware gets it
right.  If you do X yourself, it will work whether or not the firmware
gets it right.  This means that if there's even one firmware you have
to deal with out there that gets X wrong, you have to do it yourself
and then there is little to no incentive to rely on firmware even in
the cases where it does get it right.  In fact there's a disincentive,
because then you have two different code paths to test and maintain.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson


From broonie at opensource.wolfsonmicro.com  Mon Jun 14 08:48:31 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 14 Jun 2010 13:48:31 +0100
Subject: [PATCH v3] ISL6271A voltage regulator support.
In-Reply-To: <1276442751-3562-1-git-send-email-marek.vasut@gmail.com>
References: <1276442751-3562-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <20100614124831.GE14604@rakim.wolfsonmicro.main>

On Sun, Jun 13, 2010 at 05:25:51PM +0200, Marek Vasut wrote:
> This device is very simple, it supports one buck and two LDOs. The LDOs are
> fixed-voltage. Only the buck is programable over the I2C bus to 16 possible
> voltages.
> 
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>

For future reference...

> +	/* Convert the data from chip to microvolts */
> +	data = ISL6271A_VOLTAGE_MIN + (ISL6271A_VOLTAGE_STEP * (idx & 0xf));

...note that this is just list_voltage() (if you're going to fix this
please only do so with an incremental patch).


From linus.ml.walleij at gmail.com  Mon Jun 14 09:39:33 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Mon, 14 Jun 2010 15:39:33 +0200
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 
	PrimeCells
In-Reply-To: <4C15C60E.6080404@st.com>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>
	<4C15C60E.6080404@st.com>
Message-ID: <AANLkTim9n-p-Pw6FWvzQMBiAuB3h9ILq1Ya6XWk_0l-c@mail.gmail.com>

Hi Viresh, thanks a lot for reviewing this and I'd be *very* happy if
you could give it a spin on
the SPEAr as well!

2010/6/14 Viresh KUMAR <viresh.kumar at st.com>:
>> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
>> (...)
>> + * For peripherals with a FIFO:
>> + * Source ? ? ?burst size == half the depth of the peripheral FIFO
>> + * Destination burst size == width of the peripheral FIFO
>> + *
>
> I didn't get it completely, why burst depends upon width of peripheral FIFO.

I think this is just the wrong word, it should be "depth".

>> + * (Bursts are irrelevant for mem to mem transfers - there are no burst
>> + * signals)
>
> I agree that there are no request lines from memories but still we can program
> them with burst in order to faster the transfer. This burst feature is
> automatically handled by DMA.

Actually in the example platform data I set this to the maxburst size
256 Bytes, however if I read the manual correctly this is simply ignored
when you do mem2mem transfers.

It will simply AHB master the bus until the transaction is finished. That
is why the manual states:

"You must program memory-to-memory transfers with a low channel
priority, otherwise:
?    other DMA channels cannot access the bus until the
memory-to-memory transfer
     has finished
?    other AHB masters cannot perform any transaction."

>> + * @max_num_llis: maximum number of LLIs, i.e. longest linked transfer
>> + * length, submitted so far
>
> What is the significance of this field? What it is used for?

Statistics in Peters original implementation. I'll remove it.

>> +static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
>> + ? ? ? ? ? ? ? ? ? ? ? ? struct pl08x_phy_chan *ch)
>> +{
>> + ? ? u32 val;
>> +
>> + ? ? /* Wait for channel inactive */
>> + ? ? val = readl(ch->base + PL080_CH_CONFIG);
>> + ? ? while (val & PL080_CONFIG_ACTIVE)
>> + ? ? ? ? ? ? val = readl(ch->base + PL080_CH_CONFIG);
>
> can we use pl08x_phy_channel_busy() instead of above code?

Fixed.

>> + ? ? /*
>> + ? ? ?* Do not access config register until channel shows as inactive
>> + ? ? ?*/
>> + ? ? val = readl(ch->base + PL080_CH_CONFIG);
>> + ? ? while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
>> + ? ? ? ? ? ? val = readl(ch->base + PL080_CH_CONFIG);
>
> above 3 fns are always called in order, i.e. pl08x_enable_phy_chan will
> be called after pl08x_set_cregs, so we may not require these checks
> here. Is my understanding correct??

The previous check if the channel is active before proceeding, this check also
checks the enable bit, this behaviour comes straight from the manual and is
required to avoid hardware races, so I don't dare to touch it really...

>> + ? ? /* Wait for channel inactive */
>> + ? ? val = readl(ch->base + PL080_CH_CONFIG);
>> + ? ? while (val & PL080_CONFIG_ACTIVE)
>> + ? ? ? ? ? ? val = readl(ch->base + PL080_CH_CONFIG);
>
> can we use pl08x_phy_channel_busy() instead of above code?
> Please check everywhere.

It's just these two places. Fixed this one as well.

>> +
>> + ? ? mb();
>> +
>> + ? ? return;
>
> return not required!!

Fixed.

>> +static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
>
> can these small fns be made inline???

Probably but the compiler will do that anyway if there some
point. I'm afraid of violating chapter 15 of CodingStyle...

>> +/* Stops the channel */
>> +static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
>> +{
>> + ? ? u32 val;
>> +
>> + ? ? pl08x_pause_phy_chan(ch);
>> +
>> + ? ? /* Disable channel */
>> + ? ? val = readl(ch->base + PL080_CH_CONFIG);
>> + ? ? val &= ~PL080_CONFIG_ENABLE;
>> + ? ? writel(val, ch->base + PL080_CH_CONFIG);
>> + ? ? mb();
>> +
>> + ? ? return;
>
> same here. return not required.

Fixed all these.

>> +static inline u32 get_bytes_in_cctl(u32 cctl)
>> +{
>> + ? ? /* The source width defines the number of bytes */
>> + ? ? u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
>> +
>> + ? ? switch ((cctl >> 18) & 3) {
>
> better to use Macros instead of magic numbers here!!!

Fixed.

>> +static inline u32 pl08x_cctl_bits(u32 cctl,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? u8 srcwidth,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? u8 dstwidth,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? u32 tsize)
>
> Not sure, if we should write above function prototype in just 2 lines,
> or is it okay to write it the way it is written.

Whatever, I made it two lines instead.

>> +struct dma_device dmac_slave = {
>
> they must be marked static.

Fixed.

>> + ? ? .device_alloc_chan_resources ? ?= pl08x_alloc_chan_resources,
>> + ? ? .device_free_chan_resources ? ? = pl08x_free_chan_resources,
>> + ? ? .device_prep_dma_xor ? ? ? ? ? ?= NULL,
>> + ? ? .device_prep_dma_memset ? ? ? ? = NULL,
>> + ? ? .device_prep_dma_interrupt ? ? ?= pl08x_prep_dma_interrupt,
>> + ? ? .device_tx_status ? ? ? ? ? ? ? = pl08x_dma_tx_status,
>> + ? ? .device_issue_pending ? ? ? ? ? = pl08x_issue_pending,
>> + ? ? .device_prep_slave_sg ? ? ? ? ? = pl08x_prep_slave_sg,
>> + ? ? .device_control ? ? ? ? ? ? ? ? = pl08x_control,
>> +};
>> +
>
> One more thing linus, why do we need to create this separation between
> channels. i.e. few are for memcpy and few for slave_sg. Why don't all
> channels support everything and this is resolved at runtime.

This is done in all in-tree drivers, the reason is (I think) that for example
the dmatest.c test client will look for:

	if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
		cnt = dmatest_add_threads(dtc, DMA_MEMCPY);
		thread_count += cnt > 0 ? cnt : 0;

So if you want to partition some channels for device I/O (typically some
which are hard-coded to some devices) and others for memcpy() you create
a slave instance for the former and a memcpy() instance for the latter.

In this case we multiplex the memcpy and slave transfers on the few
physical channels we have, but I haven't finally decided how to handle this:
perhaps we should always set on physical channel aside for memcpy
so this won't ever fail, and then this special memcpy device entry will help.

Ideas? Use cases?

>> +/*
>> + * Initialise the DMAC slave channels.
>> + * Make a local wrapper to hold required data
>> + */
>> +static int pl08x_dma_init_slave_channels(struct pl08x_driver_data *pl08x,
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct dma_device *slave)
>
> above 2 functions are almost exactly same, can we have single function
> instead of two.

OK Fixed.

>> + ? ? /* A DMA memory pool for LLIs, align on 1-byte boundary */
>> + ? ? pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
>> + ? ? ? ? ? ? ? ? ? ? PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
>> + ? ? if (!pl08x->pool) {
>> + ? ? ? ? ? ? ret = -ENOMEM;
>> + ? ? ? ? ? ? goto out_no_lli_pool;
>> + ? ? }
>> + ? ? pl08x->pool_ctr = 0;
>> + ? ? pl08x->max_num_llis = 0;
>
> they are already 0.

OK deleted.

>> + ? ? ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
>> + ? ? ? ? ? ? ? ? ? ? ? vd->name, pl08x);
>> + ? ? if (ret) {
>> + ? ? ? ? ? ? dev_err(&adev->dev, "%s failed to request "
>> + ? ? ? ? ? ? ? ? ? ? "interrupt %d\n",
>> + ? ? ? ? ? ? ? ? ? ? __func__, adev->irq[0]);
>
> can be written in 2 lines only.

Fixed.

>> + ? ? /* Get the platform data */
>> + ? ? pl08x->pd = (struct pl08x_platform_data *)(adev->dev.platform_data);
>
> better to use dev_get_platdata, also no need of typecasting as
> platform_data is of type void*.

Fixed.

>> +/* PL080 has 8 channels and the PL080 have just 2 */
>
> "PL080 or PL081 have just 2"?? You mentioned at the beginning of this
> file, that PL081 has 16 channels. Am i missing something??

Wrong words again, this is one of the most confusing things about PL080/PL081,
it has 2 or 8 *channels* but always 16 *signals*.

Almost all other interrupt controllers have a 1-to-1 correspondence between the
number of incoming signals and the number of available slave channels.
Not the PL08x... it has less channels than signals.

I will underscore it again... if it confuses both me and you it will invariably
confuse everybody else too.

Thanks!

Yours,
Linus Walleij


From nico at fluxnic.net  Mon Jun 14 09:51:50 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 14 Jun 2010 09:51:50 -0400 (EDT)
Subject: Request review of device tree documentation
In-Reply-To: <AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com>
References: <AANLkTilK4YkRMJqlcRDOAlGBzpdlZuSo9NF5NrRNocHT@mail.gmail.com>
	<33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com>
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com>
	<4C13430B.5000907@firmworks.com> <1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com> <1276408773.1962.574.camel@pasglop>
	<AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com>
Message-ID: <alpine.LFD.2.00.1006140943350.13427@xanadu.home>

On Sun, 13 Jun 2010, Grant Likely wrote:

> [cc'ing linux-arm-kernel]
> 
> On Sat, Jun 12, 2010 at 11:59 PM, Benjamin Herrenschmidt
> > BTW. I notice no ARM list is CCed on this discussion ... maybe we should
> > fix that ?
> 
> cc'ing linux-arm-kernel in all my replies

I'm afraid this won't be enough.

I'm seeing a stream of frightening crazy talk involving ARM and some 
other stuff I still can't make head and tail of.  So, before you get a 
wholesale NAK on everything from me, please I'd suggest you guys rewind 
a bit now that the ARM list is in CC and just explain what this is all 
about and why we should feel concerned.  Then maybe the ARM savvy people 
amongst us could suggest more appropriate approaches?

Thank you.


Nicolas


From jamie at shareable.org  Mon Jun 14 10:29:58 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Mon, 14 Jun 2010 15:29:58 +0100
Subject: Request review of device tree documentation
In-Reply-To: <20100614094740.GB7881@n2100.arm.linux.org.uk>
References: <1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<1276408773.1962.574.camel@pasglop>
	<AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com>
	<20100614073828.GA6095@n2100.arm.linux.org.uk>
	<4C15DE2E.1050905@firmworks.com>
	<20100614092559.GA7881@n2100.arm.linux.org.uk>
	<1276508170.2552.43.camel@pasglop>
	<20100614094740.GB7881@n2100.arm.linux.org.uk>
Message-ID: <20100614142958.GA9550@shareable.org>

Russell King - ARM Linux wrote:
> On Mon, Jun 14, 2010 at 07:36:10PM +1000, Benjamin Herrenschmidt wrote:
> > However, there's a lot of room for abuse here and I'm worried that if it
> > becomes widespread, we'll start seeing vendors use that as a way to do
> > some kind of HAL and hide various platform methods in there (clock
> > control, nvram, etc...).
> 
> This is what I'm worried about too.
> 
> As I said in my first reply in this thread, calling out from the kernel
> will kill performance due to the time taken to shut down the caches and
> MMU, which can only be done safely with all exceptions turned off.

Some applications use ARM (or other "embedded"-ish CPU) as opposed to
x86 PCs, to get predictable and reasonable interrupt latency.

x86 PCs sometimes have unpredictable interrupt latency due to those
mystery interrupts that the BIOS handles and the OS can't see or
block.  It's a different cause, but let's not duplicate the symptom
where it isn't wanted.

Even if opaque firmware callouts were fast, it would be an issue with
real-time kernels if they couldn't depend on that as an auditable fact.

-- Jamie


From nico at fluxnic.net  Mon Jun 14 10:59:20 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 14 Jun 2010 10:59:20 -0400 (EDT)
Subject: Request review of device tree documentation
In-Reply-To: <20100614124438.GF9323@yookeroo>
References: <33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com>
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com>
	<4C13430B.5000907@firmworks.com> <1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
	<20100614124438.GF9323@yookeroo>
Message-ID: <alpine.LFD.2.00.1006141044510.13427@xanadu.home>

On Mon, 14 Jun 2010, David Gibson wrote:

> On Sun, Jun 13, 2010 at 11:02:15PM -0600, Grant Likely wrote:
> [sni]
> > > That's sort of a self-fulfilling prophecy. ?If the OS doesn't trust the
> > > firmware, there is no pressure for the firmware to "get it right".
> > 
> > Firmware will not get it right.  Period.  There will always be
> > something wrong.  It is never right on PCs.  It will never be right on
> > the other architectures.
> 
> Yes, yes, yes.  And there is a great deal of empirical evidence to
> back that assertion.
> 
> >  That goes for OSes too, but upgrading an OS
> > isn't as risky as upgrading firmware.  That isn't to say that it can't
> > be close, but every firmware feature that the OS depends on is a
> > feature that could force a risky firmware upgrade when the bug in it
> > is discovered.
> 
> Indeed.  In fact, the general rule of thumb is really "put as much as
> possible into the most easily replaced layer of the stack".  This is,
> incidentally, why I've always been dubious about simple firmwares
> supplying a flattened device tree rather than including the device
> tree template in the kernel, cuboot style.

The biggest advantage, IMHO, for adding DT to ARM, is actually to 
decouple the hardware config information and the kernel.  If in the end 
the DT has to be shipped in the kernel then we're losing all this 
advantage over the current state of things on ARM which still works 
pretty well otherwise.

In the best case, the simple firmware simply has to retrieve the 
flattened device tree from flash, and pass it to the kernel just like 
some anonymous blob.  And the simple firmware only needs to provide a 
way for that DT blob to be updatable, like through an upload of a 
replacement blob that was prepared offline.  Just like a ramdisk image 
or the like.

That doesn't need to be fancier than that, and the goal of having the DT 
data tied to the hardware instead of the kernel is achieved.

> > I'm also convinced that the economics are all wrong for "getting it
> > right" when talking about firmware.  Manufactures don't care about
> > firmware; they care about selling boxes.  Customers don't care about
> > firmware, they care about the operating system (well, that's not true
> > either, they care about applications).  For manufactures, once it can
> > boot the real operating system, there is little to no incentive to
> > spend any more money on firmware when the money can be better spent on
> > either the next product or the adding features to the operating system
> > of the existing product.  In fact, spending money on firmware is
> > actually *more risky* one a product ships, because if a firmware
> > upgrade goes bad, then that means product returned for repair at the
> > factory.
> 
> A good analysis.  The other side of this, is that for an OS, if you
> rely on the firmware to do X, it will work when the firmware gets it
> right.  If you do X yourself, it will work whether or not the firmware
> gets it right.  This means that if there's even one firmware you have
> to deal with out there that gets X wrong, you have to do it yourself
> and then there is little to no incentive to rely on firmware even in
> the cases where it does get it right.  In fact there's a disincentive,
> because then you have two different code paths to test and maintain.

Amen.


Nicolas

From olof at lixom.net  Mon Jun 14 10:59:56 2010
From: olof at lixom.net (Olof Johansson)
Date: Mon, 14 Jun 2010 09:59:56 -0500
Subject: [PATCH] ARM: Add ARCH_HAS_L2X0 and make CACHE_L2X0 config
	depend on that
In-Reply-To: <20100613051625.GA7248@trinity.fluff.org>
References: <1276272211-13065-1-git-send-email-olof@lixom.net>
	<1276279087.31800.6.camel@c-dwalke-linux.qualcomm.com>
	<20100613051625.GA7248@trinity.fluff.org>
Message-ID: <20100614145956.GA29355@lixom.net>

On Sun, Jun 13, 2010 at 06:16:26AM +0100, Ben Dooks wrote:
> On Fri, Jun 11, 2010 at 10:58:07AM -0700, Daniel Walker wrote:
> >
> > I made a similar change not too long ago, but Russell wanted the define
> > to be HAVE_CACHE_L2X0 ..
> 
> possibly, I was thinking ARM_L2X0 would also be an option, since if I
> remeber correctly it is selecting the driver not the availability of
> it.

Yeah, there are lots of different possible names. :)

Let's just go with the one Russell preferred and not worry too much
about it. There's some presendence to using HAVE_.* already.


-Olof


From grant.likely at secretlab.ca  Mon Jun 14 11:08:16 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 14 Jun 2010 09:08:16 -0600
Subject: Request review of device tree documentation
In-Reply-To: <alpine.LFD.2.00.1006141044510.13427@xanadu.home>
References: <33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com> 
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com> 
	<4C13430B.5000907@firmworks.com> <1276339529.1962.184.camel@pasglop> 
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com> 
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com> 
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com> 
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>
Message-ID: <AANLkTikH6AHQZse6YX6EzT3H3MKQzob_J04my5mLWW0V@mail.gmail.com>

On Mon, Jun 14, 2010 at 8:59 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Mon, 14 Jun 2010, David Gibson wrote:
>
>> On Sun, Jun 13, 2010 at 11:02:15PM -0600, Grant Likely wrote:
>> Indeed. ?In fact, the general rule of thumb is really "put as much as
>> possible into the most easily replaced layer of the stack". ?This is,
>> incidentally, why I've always been dubious about simple firmwares
>> supplying a flattened device tree rather than including the device
>> tree template in the kernel, cuboot style.
>
> The biggest advantage, IMHO, for adding DT to ARM, is actually to
> decouple the hardware config information and the kernel. ?If in the end
> the DT has to be shipped in the kernel then we're losing all this
> advantage over the current state of things on ARM which still works
> pretty well otherwise.
>
> In the best case, the simple firmware simply has to retrieve the
> flattened device tree from flash, and pass it to the kernel just like
> some anonymous blob. ?And the simple firmware only needs to provide a
> way for that DT blob to be updatable, like through an upload of a
> replacement blob that was prepared offline. ?Just like a ramdisk image
> or the like.
>
> That doesn't need to be fancier than that, and the goal of having the DT
> data tied to the hardware instead of the kernel is achieved.

exactly right.

g.


From grant.likely at secretlab.ca  Mon Jun 14 11:35:23 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 14 Jun 2010 09:35:23 -0600
Subject: Request review of device tree documentation
In-Reply-To: <alpine.LFD.2.00.1006140943350.13427@xanadu.home>
References: <AANLkTilK4YkRMJqlcRDOAlGBzpdlZuSo9NF5NrRNocHT@mail.gmail.com> 
	<33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com>
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com> 
	<4C13430B.5000907@firmworks.com> <1276339529.1962.184.camel@pasglop> 
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com> 
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com> 
	<4C146F18.9030008@firmworks.com> <1276408773.1962.574.camel@pasglop> 
	<AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com> 
	<alpine.LFD.2.00.1006140943350.13427@xanadu.home>
Message-ID: <AANLkTim1mYpaxe-_OGbOF3AaZ6m5_SVUXLbeyKnAyvjs@mail.gmail.com>

On Mon, Jun 14, 2010 at 7:51 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Sun, 13 Jun 2010, Grant Likely wrote:
>
>> [cc'ing linux-arm-kernel]
>>
>> On Sat, Jun 12, 2010 at 11:59 PM, Benjamin Herrenschmidt
>> > BTW. I notice no ARM list is CCed on this discussion ... maybe we should
>> > fix that ?
>>
>> cc'ing linux-arm-kernel in all my replies
>
> I'm afraid this won't be enough.
>
> I'm seeing a stream of frightening crazy talk involving ARM and some
> other stuff I still can't make head and tail of. ?So, before you get a
> wholesale NAK on everything from me, please I'd suggest you guys rewind
> a bit now that the ARM list is in CC and just explain what this is all
> about and why we should feel concerned. ?Then maybe the ARM savvy people
> amongst us could suggest more appropriate approaches?

The discussion *started* with a request to review this document:

http://devicetree.org/Device_Tree_Usage

Which is in early draft form (which is why the arm list wasn't
initially cc'd. I was soliciting feedback from the current device tree
users.  A second request for review will go out after rework is done
to the document).

In one of the reply threads Mitch stated that he is working on an ARM
project that will use Open Firmware as the bootloader, and that he'd
like the ability to keep OFW available after the kernel is booted
which is something currently done on both Sparc and OLPC x86.  Mitch
will correct me if I'm made any misrepresentations here.

Conceptually I'm not opposed to allowing OFW to stay resident
providing that it does not impose new requirements on the boot
interface (the kernel would still need to be handed the flattened
representation of the device tree) and that the code to do so is well
contained in the kernel.  The devil is of course in the details on how
feasible it is to accomplish.  ARM machines with Open Firmware are
going to be the minority, so I'm not interested in doing anything
special or out of the ordinary specifically to support it.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From nico at fluxnic.net  Mon Jun 14 11:58:54 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 14 Jun 2010 11:58:54 -0400 (EDT)
Subject: Request review of device tree documentation
In-Reply-To: <AANLkTim1mYpaxe-_OGbOF3AaZ6m5_SVUXLbeyKnAyvjs@mail.gmail.com>
References: <AANLkTilK4YkRMJqlcRDOAlGBzpdlZuSo9NF5NrRNocHT@mail.gmail.com>
	<33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com>
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com>
	<4C13430B.5000907@firmworks.com> <1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com> <1276408773.1962.574.camel@pasglop>
	<AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com>
	<alpine.LFD.2.00.1006140943350.13427@xanadu.home>
	<AANLkTim1mYpaxe-_OGbOF3AaZ6m5_SVUXLbeyKnAyvjs@mail.gmail.com>
Message-ID: <alpine.LFD.2.00.1006141143480.13427@xanadu.home>

On Mon, 14 Jun 2010, Grant Likely wrote:

> The discussion *started* with a request to review this document:
> 
> http://devicetree.org/Device_Tree_Usage
> 
> Which is in early draft form (which is why the arm list wasn't
> initially cc'd. I was soliciting feedback from the current device tree
> users.  A second request for review will go out after rework is done
> to the document).

I'm therefore assuming I can safely ignore it for now then.

> In one of the reply threads Mitch stated that he is working on an ARM
> project that will use Open Firmware as the bootloader, and that he'd
> like the ability to keep OFW available after the kernel is booted
> which is something currently done on both Sparc and OLPC x86.  Mitch
> will correct me if I'm made any misrepresentations here.

OK... but what does "keep OFW available" mean? And what for?

> Conceptually I'm not opposed to allowing OFW to stay resident
> providing that it does not impose new requirements on the boot
> interface (the kernel would still need to be handed the flattened
> representation of the device tree) and that the code to do so is well
> contained in the kernel.  The devil is of course in the details on how
> feasible it is to accomplish.

Well, you'd need to tell the kernel about what memory area not to touch 
(given that memory is not in some area the kernel will touch anyway when 
it is in its early boot stage and still not smart enough to avoid it).

Then you'll need special code to perform those steps RMK already 
mentioned.  This is a bit like the low-level code for suspend/resume 
support is doing.  This is of course if I'm still guessing right about 
the whole purpose of this.

> ARM machines with Open Firmware are
> going to be the minority, so I'm not interested in doing anything
> special or out of the ordinary specifically to support it.

This certainly doesn't have to involve the core kernel.  A special 
module may even be sufficient to keep the complexity localized.  Just 
like low-level suspend/resume code is per SOC already anyway.

But again, what for?


Nicolas


From jamie at shareable.org  Mon Jun 14 12:02:01 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Mon, 14 Jun 2010 17:02:01 +0100
Subject: Request review of device tree documentation
In-Reply-To: <alpine.LFD.2.00.1006141044510.13427@xanadu.home>
References: <4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>
Message-ID: <20100614160201.GD9550@shareable.org>

Nicolas Pitre wrote:
> On Mon, 14 Jun 2010, David Gibson wrote:
> 
> > On Sun, Jun 13, 2010 at 11:02:15PM -0600, Grant Likely wrote:
> > [sni]
> > > > That's sort of a self-fulfilling prophecy. ?If the OS doesn't trust the
> > > > firmware, there is no pressure for the firmware to "get it right".
> > > 
> > > Firmware will not get it right.  Period.  There will always be
> > > something wrong.  It is never right on PCs.  It will never be right on
> > > the other architectures.
> > 
> > Yes, yes, yes.  And there is a great deal of empirical evidence to
> > back that assertion.
> > 
> > >  That goes for OSes too, but upgrading an OS
> > > isn't as risky as upgrading firmware.  That isn't to say that it can't
> > > be close, but every firmware feature that the OS depends on is a
> > > feature that could force a risky firmware upgrade when the bug in it
> > > is discovered.
> > 
> > Indeed.  In fact, the general rule of thumb is really "put as much as
> > possible into the most easily replaced layer of the stack".  This is,
> > incidentally, why I've always been dubious about simple firmwares
> > supplying a flattened device tree rather than including the device
> > tree template in the kernel, cuboot style.
> 
> The biggest advantage, IMHO, for adding DT to ARM, is actually to 
> decouple the hardware config information and the kernel.  If in the end 
> the DT has to be shipped in the kernel then we're losing all this 
> advantage over the current state of things on ARM which still works 
> pretty well otherwise.
> 
> In the best case, the simple firmware simply has to retrieve the 
> flattened device tree from flash, and pass it to the kernel just like 
> some anonymous blob.  And the simple firmware only needs to provide a 
> way for that DT blob to be updatable, like through an upload of a 
> replacement blob that was prepared offline.  Just like a ramdisk image 
> or the like.
> 
> That doesn't need to be fancier than that, and the goal of having the DT 
> data tied to the hardware instead of the kernel is achieved.

Imho that puts the DT in a similar category as initrd/initramfs, from
the bootloader's point of view.  It's another blob whose address is
passed to the kernel, just like initrd.

Some bootloaders can't update blobs independently for technical
reasons, or to be minimal.

A device I'm using does kernel updates by updating the whole romfs
boot image, which contains the kernel and other auxiliary blobs used
for booting (splash screen, early irq handlers etc.) as well as the
root filesystem.

It is done that way to pack everything together in the small flash,
and because the NOR flash eraseblocks are too large relative to the
whole flash size to use separate partitions for kernel, boot
filesystem and other blobs for booting.

Dedicating a 64kiB eraseblock out of 2MB just for a small DT would be
quite wasteful.  Dedicating two to make it powerfail-safe would be
even worse.

So requiring that a bootloader can update the DT _independently_ of
everything else is a bit much for some devices.

But requiring that it's generally treated like other separate blob,
i.e. in a similar way to initrd, and the kernel image itself, seems
not unreasonable.

Like initrd, some people will find they need to compile it in to the
kernel image to fit some bootloader they can't change, or daren't risk
changing in already rolled out devices that they want to update to a
DT-using kernel.

I won't be surprised if I see some vendor SDK containing a kernel
patch to early-parse the bootloader-supplied ROMFS image to extract
"devicetree.bin.gz" at some point :-)

We can discourage that sort of thing (but not prevent it) by ensuring
the open source bootloaders support a DT blob as easily as possible.

-- Jamie


From imp at bsdimp.com  Mon Jun 14 11:51:08 2010
From: imp at bsdimp.com (M. Warner Losh)
Date: Mon, 14 Jun 2010 09:51:08 -0600 (MDT)
Subject: Request review of device tree documentation
In-Reply-To: <20100614124438.GF9323@yookeroo>
References: <4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
	<20100614124438.GF9323@yookeroo>
Message-ID: <20100614.095108.295937982770216377.imp@bsdimp.com>

In message: <20100614124438.GF9323 at yookeroo>
            David Gibson <david at gibson.dropbear.id.au> writes:
: On Sun, Jun 13, 2010 at 11:02:15PM -0600, Grant Likely wrote:
: [sni]
: > > That's sort of a self-fulfilling prophecy. ?If the OS doesn't trust the
: > > firmware, there is no pressure for the firmware to "get it right".
: > 
: > Firmware will not get it right.  Period.  There will always be
: > something wrong.  It is never right on PCs.  It will never be right on
: > the other architectures.
: 
: Yes, yes, yes.  And there is a great deal of empirical evidence to
: back that assertion.

While I'll be the first to agree with that, there's also a great deal
of empirical evidence to suggest that they get it right enough often
enough.  Otherwise nothing would boot and everything would be broken.

: >  That goes for OSes too, but upgrading an OS
: > isn't as risky as upgrading firmware.  That isn't to say that it can't
: > be close, but every firmware feature that the OS depends on is a
: > feature that could force a risky firmware upgrade when the bug in it
: > is discovered.
: 
: Indeed.  In fact, the general rule of thumb is really "put as much as
: possible into the most easily replaced layer of the stack".  This is,
: incidentally, why I've always been dubious about simple firmwares
: supplying a flattened device tree rather than including the device
: tree template in the kernel, cuboot style.

The down side of cuboot style is that your kernel will boot on fewer
boards.  The firmware enables more generic kernels.

: > I'm also convinced that the economics are all wrong for "getting it
: > right" when talking about firmware.  Manufactures don't care about
: > firmware; they care about selling boxes.  Customers don't care about
: > firmware, they care about the operating system (well, that's not true
: > either, they care about applications).  For manufactures, once it can
: > boot the real operating system, there is little to no incentive to
: > spend any more money on firmware when the money can be better spent on
: > either the next product or the adding features to the operating system
: > of the existing product.  In fact, spending money on firmware is
: > actually *more risky* one a product ships, because if a firmware
: > upgrade goes bad, then that means product returned for repair at the
: > factory.
: 
: A good analysis.  The other side of this, is that for an OS, if you
: rely on the firmware to do X, it will work when the firmware gets it
: right.  If you do X yourself, it will work whether or not the firmware
: gets it right.  This means that if there's even one firmware you have
: to deal with out there that gets X wrong, you have to do it yourself
: and then there is little to no incentive to rely on firmware even in
: the cases where it does get it right.  In fact there's a disincentive,
: because then you have two different code paths to test and maintain.

Two comments: (1) You are assuming that you are in a position to do
'X' right which isn't always possible (in this case, it is impossible
to do generically, but can be done specifically for a given board if
you know enough about the board) and (2) In this case, the wrapped fdt
path uses the same path as the get the fdt from the firmware.

Warner


From davem at davemloft.net  Mon Jun 14 12:13:20 2010
From: davem at davemloft.net (David Miller)
Date: Mon, 14 Jun 2010 09:13:20 -0700 (PDT)
Subject: [PATCH 1/4] net/phy/marvell: Expose IDs and flags in a .h and
	add dns323 LEDs setup flag
In-Reply-To: <1276408955.1962.578.camel@pasglop>
References: <1276391423.1962.263.camel@pasglop>
	<20100613052831.GA17012@pengutronix.de>
	<1276408955.1962.578.camel@pasglop>
Message-ID: <20100614.091320.59687255.davem@davemloft.net>

From: Benjamin Herrenschmidt <benh at kernel.crashing.org>
Date: Sun, 13 Jun 2010 16:02:35 +1000

> On Sun, 2010-06-13 at 07:28 +0200, Wolfram Sang wrote:
>> On Sun, Jun 13, 2010 at 11:10:23AM +1000, Benjamin Herrenschmidt wrote:
>> > This moves the various known Marvell PHY IDs to include/linux/marvell_phy.h
>> > along with dev_flags definitions for use by the driver.
>> > 
>> > I then added a flag that changes the PHY init code to setup the LEDs
>> > config to the values needed to operate a dns323 rev C1 NAS.
>> > 
>> > I moved the existing "resistance" flag to the .h as well, though I've
>> > been unable to find whoever sets this to convert it to use that constant.
>> > 
>> > Signed-off-by: Benjamin Herrenschmidt <benh at kernel.crashing.org>
>> 
>> That should do for now.
>> 
>> Reviewed-by: Wolfram Sang <w.sang at pengutronix.de>
> 
> Thanks.
> 
> Dave, any objection to having that go via the arm tree along with the
> rest of my patches to support the dns323 since they depend on this one ?

No problem:

Acked-by: David S. Miller <davem at davemloft.net>


From richardcochran at gmail.com  Mon Jun 14 12:15:19 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Mon, 14 Jun 2010 18:15:19 +0200
Subject: [PATCH] ixp4xx: add support for static flash partitions
In-Reply-To: <1276420566.19028.184.camel@localhost>
References: <20100531162434.GA4599@riccoc20.at.omicron.at>
	<1276420566.19028.184.camel@localhost>
Message-ID: <20100614161519.GB24877@riccoc20.at.omicron.at>

On Sun, Jun 13, 2010 at 12:16:06PM +0300, Artem Bityutskiy wrote:
> I could fix your patch up myself, but I do not know the code, so please,
> re-send a patch against the latest mtd-2.6 tree.

Okay, here it is again, this time against today's master branch of 
git://git.infradead.org/mtd-2.6.git

Thanks,
Richard


This patch adds support for static flash partitioning from a platform
device. Also, we clean up some weirdness where statements were separated
by commas instead of semicolons. While we are at it, fix some minor bad
white space, too.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 drivers/mtd/maps/ixp4xx.c |   35 +++++++++++++++++++++++++++--------
 1 files changed, 27 insertions(+), 8 deletions(-)

diff --git a/drivers/mtd/maps/ixp4xx.c b/drivers/mtd/maps/ixp4xx.c
index e0a5e04..1f9fde0 100644
--- a/drivers/mtd/maps/ixp4xx.c
+++ b/drivers/mtd/maps/ixp4xx.c
@@ -118,7 +118,7 @@ static void ixp4xx_copy_from(struct map_info *map, void *to,
 		*dest++ = BYTE1(data);
 		src += 2;
 		len -= 2;
-        }
+	}
 
 	if (len > 0)
 		*dest++ = BYTE0(flash_read16(src));
@@ -185,6 +185,8 @@ static int ixp4xx_flash_probe(struct platform_device *dev)
 {
 	struct flash_platform_data *plat = dev->dev.platform_data;
 	struct ixp4xx_flash_info *info;
+	const char *part_type = NULL;
+	int nr_parts = 0;
 	int err = -1;
 
 	if (!plat)
@@ -218,9 +220,9 @@ static int ixp4xx_flash_probe(struct platform_device *dev)
 	 */
 	info->map.bankwidth = 2;
 	info->map.name = dev_name(&dev->dev);
-	info->map.read = ixp4xx_read16,
-	info->map.write = ixp4xx_probe_write16,
-	info->map.copy_from = ixp4xx_copy_from,
+	info->map.read = ixp4xx_read16;
+	info->map.write = ixp4xx_probe_write16;
+	info->map.copy_from = ixp4xx_copy_from;
 
 	info->res = request_mem_region(dev->resource->start,
 			resource_size(dev->resource),
@@ -248,11 +250,28 @@ static int ixp4xx_flash_probe(struct platform_device *dev)
 	info->mtd->owner = THIS_MODULE;
 
 	/* Use the fast version */
-	info->map.write = ixp4xx_write16,
+	info->map.write = ixp4xx_write16;
+
+#ifdef CONFIG_MTD_PARTITIONS
+	nr_parts = parse_mtd_partitions(info->mtd, probes, &info->partitions,
+					dev->resource->start);
+#endif
+	if (nr_parts > 0) {
+		part_type = "dynamic";
+	} else {
+		info->partitions = plat->parts;
+		nr_parts = plat->nr_parts;
+		part_type = "static";
+	}
+	if (nr_parts == 0) {
+		printk(KERN_NOTICE "IXP4xx flash: no partition info "
+			"available, registering whole flash\n");
+		err = add_mtd_device(info->mtd);
+	} else {
+		printk(KERN_NOTICE "IXP4xx flash: using %s partition "
+			"definition\n", part_type);
+		err = add_mtd_partitions(info->mtd, info->partitions, nr_parts);
 
-	err = parse_mtd_partitions(info->mtd, probes, &info->partitions, dev->resource->start);
-	if (err > 0) {
-		err = add_mtd_partitions(info->mtd, info->partitions, err);
 		if(err)
 			printk(KERN_ERR "Could not parse partitions\n");
 	}
-- 
1.6.3.3




From grant.likely at secretlab.ca  Mon Jun 14 12:16:03 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 14 Jun 2010 10:16:03 -0600
Subject: Request review of device tree documentation
In-Reply-To: <alpine.LFD.2.00.1006141143480.13427@xanadu.home>
References: <AANLkTilK4YkRMJqlcRDOAlGBzpdlZuSo9NF5NrRNocHT@mail.gmail.com> 
	<33BD8E86-9397-432A-97BF-F154812C157B@digitaldans.com>
	<AANLkTilv6TtPZs0DAwd8JlSV_J3VvMsvtVVOOeQauOIn@mail.gmail.com> 
	<4C13430B.5000907@firmworks.com> <1276339529.1962.184.camel@pasglop> 
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com> 
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com> 
	<4C146F18.9030008@firmworks.com> <1276408773.1962.574.camel@pasglop> 
	<AANLkTinwL0XtMNG13inr_1UliOlqZkyr4dlvG-ZGL9JT@mail.gmail.com> 
	<alpine.LFD.2.00.1006140943350.13427@xanadu.home>
	<AANLkTim1mYpaxe-_OGbOF3AaZ6m5_SVUXLbeyKnAyvjs@mail.gmail.com> 
	<alpine.LFD.2.00.1006141143480.13427@xanadu.home>
Message-ID: <AANLkTikOC5lRVOTf__UKxcF_KMnvAXi23lK6BoCzMUNC@mail.gmail.com>

On Mon, Jun 14, 2010 at 9:58 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Mon, 14 Jun 2010, Grant Likely wrote:
>
>> The discussion *started* with a request to review this document:
>>
>> http://devicetree.org/Device_Tree_Usage
>>
>> Which is in early draft form (which is why the arm list wasn't
>> initially cc'd. I was soliciting feedback from the current device tree
>> users. ?A second request for review will go out after rework is done
>> to the document).
>
> I'm therefore assuming I can safely ignore it for now then.

Correct.

I'll let Mitch answer the rest of your questions.

g.


From nico at fluxnic.net  Mon Jun 14 12:23:38 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 14 Jun 2010 12:23:38 -0400 (EDT)
Subject: Request review of device tree documentation
In-Reply-To: <20100614160201.GD9550@shareable.org>
References: <4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop> <1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com> <1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>
	<20100614160201.GD9550@shareable.org>
Message-ID: <alpine.LFD.2.00.1006141206110.13427@xanadu.home>

On Mon, 14 Jun 2010, Jamie Lokier wrote:

> Nicolas Pitre wrote:
> > On Mon, 14 Jun 2010, David Gibson wrote:
> > 
> > > On Sun, Jun 13, 2010 at 11:02:15PM -0600, Grant Likely wrote:
> > > [sni]
> > > > > That's sort of a self-fulfilling prophecy. ?If the OS doesn't trust the
> > > > > firmware, there is no pressure for the firmware to "get it right".
> > > > 
> > > > Firmware will not get it right.  Period.  There will always be
> > > > something wrong.  It is never right on PCs.  It will never be right on
> > > > the other architectures.
> > > 
> > > Yes, yes, yes.  And there is a great deal of empirical evidence to
> > > back that assertion.
> > > 
> > > >  That goes for OSes too, but upgrading an OS
> > > > isn't as risky as upgrading firmware.  That isn't to say that it can't
> > > > be close, but every firmware feature that the OS depends on is a
> > > > feature that could force a risky firmware upgrade when the bug in it
> > > > is discovered.
> > > 
> > > Indeed.  In fact, the general rule of thumb is really "put as much as
> > > possible into the most easily replaced layer of the stack".  This is,
> > > incidentally, why I've always been dubious about simple firmwares
> > > supplying a flattened device tree rather than including the device
> > > tree template in the kernel, cuboot style.
> > 
> > The biggest advantage, IMHO, for adding DT to ARM, is actually to 
> > decouple the hardware config information and the kernel.  If in the end 
> > the DT has to be shipped in the kernel then we're losing all this 
> > advantage over the current state of things on ARM which still works 
> > pretty well otherwise.
> > 
> > In the best case, the simple firmware simply has to retrieve the 
> > flattened device tree from flash, and pass it to the kernel just like 
> > some anonymous blob.  And the simple firmware only needs to provide a 
> > way for that DT blob to be updatable, like through an upload of a 
> > replacement blob that was prepared offline.  Just like a ramdisk image 
> > or the like.
> > 
> > That doesn't need to be fancier than that, and the goal of having the DT 
> > data tied to the hardware instead of the kernel is achieved.
> 
> Imho that puts the DT in a similar category as initrd/initramfs, from
> the bootloader's point of view.  It's another blob whose address is
> passed to the kernel, just like initrd.

Exact.

> Some bootloaders can't update blobs independently for technical
> reasons, or to be minimal.
> 
> A device I'm using does kernel updates by updating the whole romfs
> boot image, which contains the kernel and other auxiliary blobs used
> for booting (splash screen, early irq handlers etc.) as well as the
> root filesystem.
> 
> It is done that way to pack everything together in the small flash,
> and because the NOR flash eraseblocks are too large relative to the
> whole flash size to use separate partitions for kernel, boot
> filesystem and other blobs for booting.

If you already have to update everything at once already anyway, then 
the DT blob just has to be in that update.  No need to do otherwise if 
you can't do better than that for the kernel alone.

> Dedicating a 64kiB eraseblock out of 2MB just for a small DT would be
> quite wasteful.  Dedicating two to make it powerfail-safe would be
> even worse.

I hardly see how you can be power fail safe with your 
update-everything-at-once condition above anyway.

Furthermore, if the DT is updated by the bootloader, then that means 
you're not running a live system at that point.  If power fails during 
the DT update, then you simply have to re-update it when power is back 
to allow a successful boot of the kernel afterwards.

> So requiring that a bootloader can update the DT _independently_ of
> everything else is a bit much for some devices.

In my opinion, this use case you're illustrating above simply could 
continue to _not_ use DT at all.  If your NOR flash is so small that you 
cannot spare some extra erase blocks, then this is a deeply embedded 
profile the current DT-on-ARM push is not really meant for.  You would 
be much better with a minimally configured kernel with all the hardware 
info statically compiled into the kernel and get away without all the DT 
parsing code altogether, like you're already doing today.

While I think DT for ARM has advantages, I don't see us dropping the 
legacy ARM methods anytime soon, especially for existing or extremely 
constrained targets.


Nicolas

From grant.likely at secretlab.ca  Mon Jun 14 12:28:09 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 14 Jun 2010 10:28:09 -0600
Subject: Request review of device tree documentation
In-Reply-To: <20100614160201.GD9550@shareable.org>
References: <4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop> 
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com> 
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com> 
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com> 
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home> 
	<20100614160201.GD9550@shareable.org>
Message-ID: <AANLkTilZuMKzFN1hD1k4Q067jSkryPuWA2bhW0Y3GJTg@mail.gmail.com>

On Mon, Jun 14, 2010 at 10:02 AM, Jamie Lokier <jamie at shareable.org> wrote:
> Nicolas Pitre wrote:
>> On Mon, 14 Jun 2010, David Gibson wrote:
>>
>> > On Sun, Jun 13, 2010 at 11:02:15PM -0600, Grant Likely wrote:
>> > [sni]
>> > > > That's sort of a self-fulfilling prophecy. ?If the OS doesn't trust the
>> > > > firmware, there is no pressure for the firmware to "get it right".
>> > >
>> > > Firmware will not get it right. ?Period. ?There will always be
>> > > something wrong. ?It is never right on PCs. ?It will never be right on
>> > > the other architectures.
>> >
>> > Yes, yes, yes. ?And there is a great deal of empirical evidence to
>> > back that assertion.
>> >
>> > > ?That goes for OSes too, but upgrading an OS
>> > > isn't as risky as upgrading firmware. ?That isn't to say that it can't
>> > > be close, but every firmware feature that the OS depends on is a
>> > > feature that could force a risky firmware upgrade when the bug in it
>> > > is discovered.
>> >
>> > Indeed. ?In fact, the general rule of thumb is really "put as much as
>> > possible into the most easily replaced layer of the stack". ?This is,
>> > incidentally, why I've always been dubious about simple firmwares
>> > supplying a flattened device tree rather than including the device
>> > tree template in the kernel, cuboot style.
>>
>> The biggest advantage, IMHO, for adding DT to ARM, is actually to
>> decouple the hardware config information and the kernel. ?If in the end
>> the DT has to be shipped in the kernel then we're losing all this
>> advantage over the current state of things on ARM which still works
>> pretty well otherwise.
>>
>> In the best case, the simple firmware simply has to retrieve the
>> flattened device tree from flash, and pass it to the kernel just like
>> some anonymous blob. ?And the simple firmware only needs to provide a
>> way for that DT blob to be updatable, like through an upload of a
>> replacement blob that was prepared offline. ?Just like a ramdisk image
>> or the like.
>>
>> That doesn't need to be fancier than that, and the goal of having the DT
>> data tied to the hardware instead of the kernel is achieved.
>
> Imho that puts the DT in a similar category as initrd/initramfs, from
> the bootloader's point of view. ?It's another blob whose address is
> passed to the kernel, just like initrd.
>
> Some bootloaders can't update blobs independently for technical
> reasons, or to be minimal.
>
> A device I'm using does kernel updates by updating the whole romfs
> boot image, which contains the kernel and other auxiliary blobs used
> for booting (splash screen, early irq handlers etc.) as well as the
> root filesystem.
>
> It is done that way to pack everything together in the small flash,
> and because the NOR flash eraseblocks are too large relative to the
> whole flash size to use separate partitions for kernel, boot
> filesystem and other blobs for booting.

This is totally fine.  I've got no problem with a specific firmware
requiring everything (kernel,dt,rootfs) packed into a single image
file.  Packing the image can be done at OS install time (instead of
prebuilding it) if the system builder want to retain the independent
hardware configuration aspects of using the device tree.

> Dedicating a 64kiB eraseblock out of 2MB just for a small DT would be
> quite wasteful. ?Dedicating two to make it powerfail-safe would be
> even worse.
>
> So requiring that a bootloader can update the DT _independently_ of
> everything else is a bit much for some devices.

Independent update of the DT is a useful feature, but it is certainly
not a hard requirement.  It's a far more likely use-case if the kernel
and DT is stored on a filesystem instead of bare NOR flash.

> But requiring that it's generally treated like other separate blob,
> i.e. in a similar way to initrd, and the kernel image itself, seems
> not unreasonable.
>
> Like initrd, some people will find they need to compile it in to the
> kernel image to fit some bootloader they can't change, or daren't risk
> changing in already rolled out devices that they want to update to a
> DT-using kernel.

Yes, I fully expect that.  Fortunately the situation is better than it
was with powerpc.  Since the machine id is being retained, a
DT-enabled kernel can continue to support non-DT systems.  There will
not be a flag day to cut everything over to a new boot interface.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From grant.likely at secretlab.ca  Mon Jun 14 12:29:51 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 14 Jun 2010 10:29:51 -0600
Subject: Request review of device tree documentation
In-Reply-To: <alpine.LFD.2.00.1006141206110.13427@xanadu.home>
References: <4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop> 
	<1276339684.1962.186.camel@pasglop> <4C13B618.1030006@firmworks.com> 
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com> 
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com> 
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home> 
	<20100614160201.GD9550@shareable.org>
	<alpine.LFD.2.00.1006141206110.13427@xanadu.home>
Message-ID: <AANLkTimY8IvWh92kyiJOTZKfb9ddCMeqcTo86cTOytWg@mail.gmail.com>

On Mon, Jun 14, 2010 at 10:23 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Mon, 14 Jun 2010, Jamie Lokier wrote:
>> So requiring that a bootloader can update the DT _independently_ of
>> everything else is a bit much for some devices.
>
> In my opinion, this use case you're illustrating above simply could
> continue to _not_ use DT at all. ?If your NOR flash is so small that you
> cannot spare some extra erase blocks, then this is a deeply embedded
> profile the current DT-on-ARM push is not really meant for. ?You would
> be much better with a minimally configured kernel with all the hardware
> info statically compiled into the kernel and get away without all the DT
> parsing code altogether, like you're already doing today.
>
> While I think DT for ARM has advantages, I don't see us dropping the
> legacy ARM methods anytime soon, especially for existing or extremely
> constrained targets.

I completely agree.

g.


From jamie at shareable.org  Mon Jun 14 12:33:24 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Mon, 14 Jun 2010 17:33:24 +0100
Subject: Request review of device tree documentation
In-Reply-To: <AANLkTilZuMKzFN1hD1k4Q067jSkryPuWA2bhW0Y3GJTg@mail.gmail.com>
References: <1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>
	<20100614160201.GD9550@shareable.org>
	<AANLkTilZuMKzFN1hD1k4Q067jSkryPuWA2bhW0Y3GJTg@mail.gmail.com>
Message-ID: <20100614163324.GG9550@shareable.org>

Grant Likely wrote:
> > Like initrd, some people will find they need to compile it in to the
> > kernel image to fit some bootloader they can't change, or daren't risk
> > changing in already rolled out devices that they want to update to a
> > DT-using kernel.
> 
> Yes, I fully expect that.  Fortunately the situation is better than it
> was with powerpc.  Since the machine id is being retained, a
> DT-enabled kernel can continue to support non-DT systems.  There will
> not be a flag day to cut everything over to a new boot interface.

That's excellent, thank you.  I was a bit unsure about how that was going.

-- Jamie


From x0095840 at ti.com  Mon Jun 14 12:51:09 2010
From: x0095840 at ti.com (Fernando Guzman Lugo)
Date: Mon, 14 Jun 2010 11:51:09 -0500
Subject: [PATCH] mailbox: change full flag per mailbox queue instead of global
Message-ID: <1276534269-19179-1-git-send-email-x0095840@ti.com>

As pointed by Ben Ohand, the variable rq_full flag is a global
variable, so if there are multiple mailbox users there will be
conflics. Now there is a full flag per mailbox queue.

Reported-by: Ohad Ben-Cohen <ohad at wizery.com>
Signed-off-by: Fernando Guzman Lugo <x0095840 at ti.com>
---
 arch/arm/plat-omap/include/plat/mailbox.h |    1 +
 arch/arm/plat-omap/mailbox.c              |    7 +++----
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
index 729166b..a6144b8 100644
--- a/arch/arm/plat-omap/include/plat/mailbox.h
+++ b/arch/arm/plat-omap/include/plat/mailbox.h
@@ -47,6 +47,7 @@ struct omap_mbox_queue {
 	struct tasklet_struct	tasklet;
 	int	(*callback)(void *);
 	struct omap_mbox	*mbox;
+	bool	full;
 };
 
 struct omap_mbox {
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 8d86b0b..a1e274e 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -30,7 +30,6 @@
 
 static struct omap_mbox *mboxes;
 static DEFINE_RWLOCK(mboxes_lock);
-static bool rq_full;
 
 static int mbox_configured;
 static DEFINE_MUTEX(mbox_configured_lock);
@@ -140,9 +139,9 @@ static void mbox_rx_work(struct work_struct *work)
 	while (1) {
 		spin_lock_irqsave(q->queue_lock, flags);
 		rq = blk_fetch_request(q);
-		if (rq_full) {
+		if (mbox->rxq->full) {
 			omap_mbox_enable_irq(mbox, IRQ_RX);
-			rq_full = false;
+			mbox->rxq->full = false;
 		}
 		spin_unlock_irqrestore(q->queue_lock, flags);
 		if (!rq)
@@ -183,7 +182,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
 		rq = blk_get_request(q, WRITE, GFP_ATOMIC);
 		if (unlikely(!rq)) {
 			omap_mbox_disable_irq(mbox, IRQ_RX);
-			rq_full = true;
+			mbox->rxq->full = true;
 			goto nomem;
 		}
 
-- 
1.6.3.3



From hartleys at visionengravers.com  Mon Jun 14 12:57:54 2010
From: hartleys at visionengravers.com (H Hartley Sweeten)
Date: Mon, 14 Jun 2010 11:57:54 -0500
Subject: [PATCH] mtd: physmap.c: use resource_size()
Message-ID: <0D753D10438DA54287A00B02708426976371223143@AUSP01VMBX24.collaborationhost.net>

Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
Cc: David Woodhouse <David.Woodhouse at intel.com>

---

diff --git a/drivers/mtd/maps/physmap.c b/drivers/mtd/maps/physmap.c
index 426461a..829aa4b 100644
--- a/drivers/mtd/maps/physmap.c
+++ b/drivers/mtd/maps/physmap.c
@@ -106,12 +106,12 @@ static int physmap_flash_probe(struct platform_device *dev)
 
 	for (i = 0; i < dev->num_resources; i++) {
 		printk(KERN_NOTICE "physmap platform flash device: %.8llx at %.8llx\n",
-		       (unsigned long long)(dev->resource[i].end - dev->resource[i].start + 1),
+		       (unsigned long long)resource_size(&dev->resource[i]),
 		       (unsigned long long)dev->resource[i].start);
 
 		if (!devm_request_mem_region(&dev->dev,
 			dev->resource[i].start,
-			dev->resource[i].end - dev->resource[i].start + 1,
+			resource_size(&dev->resource[i]),
 			dev_name(&dev->dev))) {
 			dev_err(&dev->dev, "Could not reserve memory region\n");
 			err = -ENOMEM;
@@ -120,7 +120,7 @@ static int physmap_flash_probe(struct platform_device *dev)
 
 		info->map[i].name = dev_name(&dev->dev);
 		info->map[i].phys = dev->resource[i].start;
-		info->map[i].size = dev->resource[i].end - dev->resource[i].start + 1;
+		info->map[i].size = resource_size(&dev->resource[i]);
 		info->map[i].bankwidth = physmap_data->width;
 		info->map[i].set_vpp = physmap_data->set_vpp;
 		info->map[i].pfow_base = physmap_data->pfow_base;


From wmb at firmworks.com  Mon Jun 14 12:58:57 2010
From: wmb at firmworks.com (Mitch Bradley)
Date: Mon, 14 Jun 2010 06:58:57 -1000
Subject: Request review of device tree documentation
In-Reply-To: <20100614160201.GD9550@shareable.org>
References: <4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>
	<20100614160201.GD9550@shareable.org>
Message-ID: <4C165FD1.6080505@firmworks.com>

I shall try to clarify this discussion.

There are actually two different things being discussed.  The first is, 
I hope, not too controversial.  The second is so controversial as to be 
a hopeless cause.

First, the primary use case for "keeping OFW alive" is for debugging 
purposes.  OFW remains resident in memory so that, if the OS is set to 
allow it (not the default), a hot-key freezes the OS and enters OFW, 
where a human can inspect the state of devices and OS data structures. A 
high skill level is required, so it's okay if some fiddling is necessary 
to find or establish virtual addresses or do similar magic .  In my 
career of working closely with hardware manufacturers, I and others have 
found this feature to be extremely helpful.  Often it has resulted in 
the resolution of difficult problems that were blocking the ability to 
ship the product - problems that resisted other kernel debugging techniques.

The second topic is the hypothetical use of OFW as a HAL. That will not 
happen for several reasons.  The opposition to the idea is widespread 
and deeply held, and there are good arguments to support that 
opposition.   Furthermore, the economic conditions necessary for the 
creation of such a HAL do not exist in the ARM world, nor indeed in the 
Linux world in general.  (The necessary condition is the ability for one 
company to impose a substantial change by fiat - essentially a monopoly 
position.)

Shall we agree, then, that any further discussion of the HAL issue is 
"just for fun", and that nobody needs to feel threatened that it would 
actually happen?

The potential for "vendors breaking out of the debugging use case and 
turning it into a HAL" is miniscule, because

a) The callback is disabled by default
b) The technical challenges of the callback interface limit its 
applicability to specific "wizard user" scenarios
c) OFW is unlikely to achieve sufficient market penetration for the HAL 
thing to be worth doing



From nico at fluxnic.net  Mon Jun 14 13:26:13 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 14 Jun 2010 13:26:13 -0400 (EDT)
Subject: Request review of device tree documentation
In-Reply-To: <4C165FD1.6080505@firmworks.com>
References: <4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop> <1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com> <1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>
	<20100614160201.GD9550@shareable.org> <4C165FD1.6080505@firmworks.com>
Message-ID: <alpine.LFD.2.00.1006141311580.13427@xanadu.home>

On Mon, 14 Jun 2010, Mitch Bradley wrote:

> First, the primary use case for "keeping OFW alive" is for debugging purposes.
> OFW remains resident in memory so that, if the OS is set to allow it (not the
> default), a hot-key freezes the OS and enters OFW, where a human can inspect
> the state of devices and OS data structures. A high skill level is required,
> so it's okay if some fiddling is necessary to find or establish virtual
> addresses or do similar magic .  

Why would you impose such pain on yourself in order to try to make OFW a 
viable debugging tool on ARM for live kernels, while you can achieve the 
same and more much less intrusively and so much more safely with a JTAG 
based debugger?

If the cost of a JTAG solution is a concern, you can order USB based 
JTAG dongles on the net for less than $30 and use them with OpenOCD[1].

Otherwise, what's wrong with already supported kgdb, or even kdb?

[1] http://openocd.berlios.de/web/


Nicolas


From grant.likely at secretlab.ca  Mon Jun 14 13:32:22 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 14 Jun 2010 11:32:22 -0600
Subject: Platform data with function pointers
In-Reply-To: <-71663801230973480@unknownmsgid>
References: <-71663801230973480@unknownmsgid>
Message-ID: <AANLkTikqONUs722_ev6hqfpJiehUq2qAGWGhmxg6WkTs@mail.gmail.com>

[cc'ing devicetree-discuss - this conversation should be kept on-list]

Hi Lorenzo,

On Mon, Jun 14, 2010 at 4:42 AM, Lorenzo Pieralisi
<Lorenzo.Pieralisi at arm.com> wrote:
> Hi Grant,
>
> Sorry to bother you, we had a chat about this at UDS, but I wanted to make sure I am doing it the PPC way.

Well, I wouldn't call it the PPC way.  PPC doesn't have a great
solution either.  A new approach is needed.  See below...

> When a platform_data pointer is initialized statically to a struct like e.g. the following:
> struct flash_platform_data {
> ? ? ? ?const char ? ? ?*map_name;
> ? ? ? ?const char ? ? ?*name;
> ? ? ? ?unsigned int ? ?width;
> ? ? ? ?int ? ? ? ? ? ? (*init)(void);
> ? ? ? ?void ? ? ? ? ? ?(*exit)(void);
> ? ? ? ?void ? ? ? ? ? ?(*set_vpp)(int on);
> ? ? ? ?void ? ? ? ? ? ?(*mmcontrol)(struct mtd_info *mtd, int sync_read);
> ? ? ? ?struct mtd_partition *parts;
> ? ? ? ?unsigned int ? ?nr_parts;
> };
>
> static struct flash_platform_data v2m_flash_data = {
> ? ? ? ?.map_name ? ? ? = "cfi_probe",
> ? ? ? ?.width ? ? ? ? ?= 4,
> ? ? ? ?.init ? ? ? ? ? = v2m_flash_init,
> ? ? ? ?.exit ? ? ? ? ? = v2m_flash_exit,
> ? ? ? ?.set_vpp ? ? ? ?= v2m_flash_set_vpp,
> };
>
> I think that the driver depending on a compatible property should initialize the platform_data pointer from FDT accordingly
> (dynamically, but there are function pointers in there, so they are not _really_ data). But how ? Do we compile in all existing
> static struct and pick off one depending on the compatible string ? Is there an example I can check in the PPC tree to port drivers
> the _proper_ way ?

There isn't a full example, partially because powerpc has mostly
avoided anonymous function pointers up to this point, and partially
because we don't have a good mechanism for handling it.

To start with, I must state that I really dislike platform data
because it is an anonymous pointer passed from mach code to the device
driver.  There is absolutely no type checking, and lots of opportunity
for a mismatch between the provided structure and what the driver
things it is provided.  I'm far more interested in passing parseable
data to the driver.

That being said, I completely understand the need to pass
mach-specific function pointers to a driver, and there are situations
where it must be done.

There is no single _proper_ way, but there are a number of options
depending on the situation.

One option is to build the mach specific functions into the
of_match_table for the driver.  Almost exactly like your suggestion of
compiling them in and choosing the correct one based on the matched
compatible value.  This works best if the mach code is well contained
and doesn't have to interact with other parts of mach code..  It also
works well if a lot of machines share the same hooks.  It keeps all
the driver code together, but it can get very unwieldy if a lot of
platforms need to add their custom code to a driver.  An example of
this can be seen in drivers/char/xilinx_hwicap/xilinx_hwicap.c.  Look
for the hwicap_of_match table.

If the function pointer truly is a one-off that isn't going to be
shared by other mach code, then I see two options (in both cases, I'm
assuming that the normal OF mechanisms are used to register the
devices).

1) Create a global function pointer to be populated by mach code.
Drivers would call the function at .probe() time and pass in a pointer
to the data structure.  Machine-specific code can then populate it
with the correct driver data including the function pointers.  This
works, and it preserves type safety, but it also lacks taste.  It
feels like an ugly hack to me.

2) In mach code, register a bus notifier before calling
of_platform_bus_probe().  Doing so ensures that the mach callback gets
called before a driver gets bound to the device.  Then mach code can
allocate and attach the correct platform data.  (See device_add() in
driver/base/core.c.  The bus notifiers get called before the driver is
probed with bus_probe_device()).  This solution is more elegant to me,
but it still has the problem of no type safety on the platform_data
pointer.

I'm open to other ideas on this if anyone else has a suggestion.

g.


From wmb at firmworks.com  Mon Jun 14 14:20:47 2010
From: wmb at firmworks.com (Mitch Bradley)
Date: Mon, 14 Jun 2010 08:20:47 -1000
Subject: Request review of device tree documentation
In-Reply-To: <alpine.LFD.2.00.1006141311580.13427@xanadu.home>
References: <4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>
	<20100614160201.GD9550@shareable.org>
	<4C165FD1.6080505@firmworks.com>
	<alpine.LFD.2.00.1006141311580.13427@xanadu.home>
Message-ID: <4C1672FF.3060407@firmworks.com>

Nicolas Pitre wrote:
> On Mon, 14 Jun 2010, Mitch Bradley wrote:
>
>   
>> First, the primary use case for "keeping OFW alive" is for debugging purposes.
>> OFW remains resident in memory so that, if the OS is set to allow it (not the
>> default), a hot-key freezes the OS and enters OFW, where a human can inspect
>> the state of devices and OS data structures. A high skill level is required,
>> so it's okay if some fiddling is necessary to find or establish virtual
>> addresses or do similar magic .  
>>     
>
> Why would you impose such pain on yourself in order to try to make OFW a 
> viable debugging tool on ARM for live kernels, while you can achieve the 
> same and more much less intrusively and so much more safely with a JTAG 
> based debugger?
>
> If the cost of a JTAG solution is a concern, you can order USB based 
> JTAG dongles on the net for less than $30 and use them with OpenOCD[1].
>   

If OFW is present on the machine, when a customer reports a problem I 
can tell them
to do x and y and z and tell me what they see.  In this manner, I have 
often solved
difficult problems in minutes or hours.

Arranging for a JTAG dongle to appear at the customer site, then getting 
it set up and
the necessary software installed and configured on a suitable host 
system, typically
requires several days at best, plus potentially a lot of fiddling 
depending on what
sort of host system the customer happens to have.

The phrase "impose such pain on yourself" presupposes that the technical 
challenges
are much harder than they actually are.  In fact, most of the pain comes 
from dealing
with the "yuck, why would you ever want to do that" argument.  I first 
experienced
that argument in 1982, when Tom Lyon - Sun's Unix driver expert at the 
time - threatened
to "scratch my disk" if I ported Forth to the Sun 1 machine.  Tom later 
recanted and
said that he was very glad that I had done so, after I used it to solve 
several stop-ship
problems that came close to killing the company.

> Otherwise, what's wrong with already supported kgdb, or even kdb?
>
> [1] http://openocd.berlios.de/web/
>   

Requires setup.  The power of "it's just there, flip a switch to turn it 
on" has to be
experienced in the heat of battle to be appreciated.

The other difference is that conventional debuggers focus on the problem of
inspecting and controlling the execution of preexisting programs, instead of
on the problem of constructing quick tests to test hypotheses.  While it is
possible to use them to "poke around", it quickly becomes cumbersome if you
need to do anything more complicated than just looking.  OFW's built-in
programming language is particularly well suited for making little test 
loops
on-the-fly.   Also, OFW has drivers for most of all of the system's 
hardware, and
those drivers are independently developed from the Linux drivers.  That 
often
serves as a valuable "second opinion" to help discover the root cause of 
hardware
misbehavior.
>
> Nicolas
>
>   


From bahadir at l4dev.org  Mon Jun 14 15:00:43 2010
From: bahadir at l4dev.org (Bahadir Balban)
Date: Mon, 14 Jun 2010 22:00:43 +0300
Subject: map_vm_area() correct dcache cleaning on ARMv7?
Message-ID: <4C167C5B.9070605@l4dev.org>

I am looking at the path map_vm_area() takes with regard to cache
maintenance on ARMv7. It is not how I anticipated. map_vm_area() calls
vmap_pte_range() which has:

1. pte_alloc_one_kernel(), __get_free_page(): allocate pages for 2nd
level table.

2. clean_dcache_area(): clean data cache for pages allocated in (1)
conditionally if tlb cannot fetch from 1st level dcache.

3. __pmd_populate(): Set 1st level entries to point at 2nd level.

4. flush_pmd_entry(): Clean the dcache for 1st to 2nd
level pointer set in (3), conditionally if TLB needs it.

5. set_pte_ext(): Set each 2nd level entry to pages.

6. set_pte_ext(): Unconditionally clean the dcache for 2nd level to
page pointer set up in (5).

My remarks:
I would expect (2) to not exist at all, since we don't know if there is
any page table data in those newly allocated pages. How is this useful?

I would expect (6) to be doing what (2) and (4) is doing, e.g. only
conditionally clean the dcache in case tlb cannot fetch from L1. Am I
missing something?

-- 
Bahadir





From linux at arm.linux.org.uk  Mon Jun 14 15:30:03 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 14 Jun 2010 20:30:03 +0100
Subject: map_vm_area() correct dcache cleaning on ARMv7?
In-Reply-To: <4C167C5B.9070605@l4dev.org>
References: <4C167C5B.9070605@l4dev.org>
Message-ID: <20100614193003.GA17539@n2100.arm.linux.org.uk>

On Mon, Jun 14, 2010 at 10:00:43PM +0300, Bahadir Balban wrote:
> I am looking at the path map_vm_area() takes with regard to cache
> maintenance on ARMv7. It is not how I anticipated. map_vm_area() calls
> vmap_pte_range() which has:
> 
> 1. pte_alloc_one_kernel(), __get_free_page(): allocate pages for 2nd
> level table.
> 
> 2. clean_dcache_area(): clean data cache for pages allocated in (1)
> conditionally if tlb cannot fetch from 1st level dcache.

This is absolutely correct.  We allocate a new page.  This new page can
contain any random garbage, from old PTE entries to invalid PTE entries.
It could even be code.  We do not want the MMU to read that old data.

So, we zero the page, and then call clean_dcache_area() to ensure that
the MMU will see an _initialized_ kernel, not the crappy data that was
in the page before.

> 3. __pmd_populate(): Set 1st level entries to point at 2nd level.
> 
> 4. flush_pmd_entry(): Clean the dcache for 1st to 2nd
> level pointer set in (3), conditionally if TLB needs it.

This pushes the cache line for the L1 table out to memory so that the
MMU can see it.  Without this, the MMU could still see 'zero', in
which case the MMU will fault on the first access to any page covered
by this L2 page table.

> 5. set_pte_ext(): Set each 2nd level entry to pages.
> 
> 6. set_pte_ext(): Unconditionally clean the dcache for 2nd level to
> page pointer set up in (5).

Again, this is to ensure that the MMU can see the data written to the
page tables.



From nico at fluxnic.net  Mon Jun 14 15:40:19 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 14 Jun 2010 15:40:19 -0400 (EDT)
Subject: Request review of device tree documentation
In-Reply-To: <4C1672FF.3060407@firmworks.com>
References: <4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop> <1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com> <1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>
	<20100614160201.GD9550@shareable.org> <4C165FD1.6080505@firmworks.com>
	<alpine.LFD.2.00.1006141311580.13427@xanadu.home>
	<4C1672FF.3060407@firmworks.com>
Message-ID: <alpine.LFD.2.00.1006141432530.13427@xanadu.home>

On Mon, 14 Jun 2010, Mitch Bradley wrote:

> Nicolas Pitre wrote:
> > On Mon, 14 Jun 2010, Mitch Bradley wrote:
> > 
> >   
> > > First, the primary use case for "keeping OFW alive" is for debugging
> > > purposes.
> > > OFW remains resident in memory so that, if the OS is set to allow it (not
> > > the
> > > default), a hot-key freezes the OS and enters OFW, where a human can
> > > inspect
> > > the state of devices and OS data structures. A high skill level is
> > > required,
> > > so it's okay if some fiddling is necessary to find or establish virtual
> > > addresses or do similar magic .      
> > 
> > Why would you impose such pain on yourself in order to try to make OFW a
> > viable debugging tool on ARM for live kernels, while you can achieve the
> > same and more much less intrusively and so much more safely with a JTAG
> > based debugger?
> > 
> > If the cost of a JTAG solution is a concern, you can order USB based JTAG
> > dongles on the net for less than $30 and use them with OpenOCD[1].
> >   
> 
> If OFW is present on the machine, when a customer reports a problem I 
> can tell them to do x and y and z and tell me what they see.  In this 
> manner, I have often solved difficult problems in minutes or hours.

That's assuming OFW is still intact somewhere and unaffected by said 
problem.

> Arranging for a JTAG dongle to appear at the customer site, then 
> getting it set up and the necessary software installed and configured 
> on a suitable host system, typically requires several days at best, 
> plus potentially a lot of fiddling depending on what sort of host 
> system the customer happens to have.

Well, if I may use the SheevaPlug as an example, the actual FT2232 chip 
currently used in most of those USB-JTAG dongle was provided directly on 
the board.  So you have this standard mini-B type USB connector on the 
side of the device from which you get both a serial console and a JTAG 
interface.  All you need is a standard USB cable, just like the one you 
get with a MP3 player or a digital camera, so there are plenty of those 
around.

Software wise, people have provided self contained packages containing 
OpenOCD, the necessary recovery binary images, and a script to bind it 
all into a nice debricking utility for when you blow your flash content 
away.

Oh and OpenOCD runs on Linux, Mac OS as well as Windows.

So there are ways to customize things and make this really straight 
forward to users.  But in the SheevaPlug case this ease of use was also 
planned further by integrating easy JTAG access into the hardware 
design.  And a couple other ARM boards out there are doing the same 
thing too.

> The phrase "impose such pain on yourself" presupposes that the 
> technical challenges are much harder than they actually are.  In fact, 
> most of the pain comes from dealing with the "yuck, why would you ever 
> want to do that" argument.  I first experienced that argument in 1982, 
> when Tom Lyon - Sun's Unix driver expert at the time - threatened to 
> "scratch my disk" if I ported Forth to the Sun 1 machine.  Tom later 
> recanted and said that he was very glad that I had done so, after I 
> used it to solve several stop-ship problems that came close to killing 
> the company.

Sure. Pioneering solutions to save your life is always worth the pain.  
But in this case some solutions were already developed and in use today.  
So all you'll be doing here is sort of reinventing the wheel with the 
only major benefit that it is a wheel that you're familiar with, while 
the rest of the crowd is using another one already.

> > Otherwise, what's wrong with already supported kgdb, or even kdb?
> > 
> > [1] http://openocd.berlios.de/web/
> >   
> 
> Requires setup.  The power of "it's just there, flip a switch to turn 
> it on" has to be experienced in the heat of battle to be appreciated.

Sure... when 1) the switch does still work even after damage was 
incurred, and 2) you have someone on-site with the appropriate knowledge 
for it.

> The other difference is that conventional debuggers focus on the problem of
> inspecting and controlling the execution of preexisting programs, instead of
> on the problem of constructing quick tests to test hypotheses.  While it is
> possible to use them to "poke around", it quickly becomes cumbersome if you
> need to do anything more complicated than just looking.  OFW's built-in
> programming language is particularly well suited for making little test loops
> on-the-fly.   

Just for completeness, OpenOCD is not itself a debugger.  It is a mean 
to provide a GDB remote debugging interface amongst other things.  It 
has its own interface that can be used autonomously, and if I'm not 
mistaken there is even a web interface to it.  And OpenOCD can be 
scripted (it contains a TCL interpreter).  So you can do all sorts of 
things with it.  The most popular usage is to reflash a hosed system.

I even saw someone use a modified OpenOCD version to wait until the CPU 
entered a particular function, have it single-stepped, and get 
statistics on cache hits and misses on a per assembly instruction 
granularity.  You just can't get that sort of info with software 
solutions running on the target as that screws up the results, nor with 
an emulator as it is usually too slow to emulate some real life 
situations.

> Also, OFW has drivers for most of all of the system's hardware, and 
> those drivers are independently developed from the Linux drivers.  
> That often serves as a valuable "second opinion" to help discover the 
> root cause of hardware misbehavior.

Sure.  I think this is a valid case, although it is quite a stretch to 
have a duplicate set of drivers there "just in case" and expect them to 
take over _live_ without skewed results.  You usually want to reboot 
into that other environment to perform your validation test, not to 
hijack the hardware from under the running OS, fiddle with it, and give 
it back to the OS hoping that everything will continue to go well.

Furthermore, those independently developed drivers are not the best 
utilization of resources.  You will hardly find people willing to 
re-implement something that already exists out there.  And if they have 
to do it once, they'll do it for Linux directly.  That's why ideas such 
as using Linux as a bootloader to boot Linux are becoming more popular.  
Even U-Boot is leveraging Linux for a lot of driver code.  Otherwise 
those duplicated drivers are simple versions for bootloader purposes 
with no similar concerns about concurrency and performance you typically 
find in a full fledged OS.

There is even a trend amongst hardware vendors to converge around 
"standardized" hardware interfaces for many class of devices, so they 
even don't have any, or very little, driver development to do.

So yes, in theory, this "second opinion" from independently developed 
drivers would be quite useful.  But in practice this is rarely 
affordable.


Nicolas


From ben-linux at fluff.org  Mon Jun 14 16:00:00 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Mon, 14 Jun 2010 21:00:00 +0100
Subject: Request review of device tree documentation
In-Reply-To: <AANLkTimc12G-YYTd4yQiviY-ijvJ9TzVEmxxaoF43xVR@mail.gmail.com>
References: <1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<1276408773.1962.574.camel@pasglop>
	<4C147EA5.3060500@firmworks.com>
	<1276417792.1962.731.camel@pasglop>
	<AANLkTimc12G-YYTd4yQiviY-ijvJ9TzVEmxxaoF43xVR@mail.gmail.com>
Message-ID: <20100614200000.GB7248@trinity.fluff.org>

On Sun, Jun 13, 2010 at 11:36:57PM -0600, Grant Likely wrote:
> On Sun, Jun 13, 2010 at 2:29 AM, Benjamin Herrenschmidt
> <benh at kernel.crashing.org> wrote:
> > On Sat, 2010-06-12 at 20:45 -1000, Mitch Bradley wrote:
> >
> >> Either fought or embraced. ?To the extent that it is possible to focus
> >> solely on Linux and ARM, one could image doing a good HAL.
> >
> > That will come with a huge amount of comunity resistance sadly, but I
> > can imagine distros liking it.
> >
> > In general, I much prefer having all the necessary native drivers in the
> > kernel, and the device-tree to provide the right representation, and
> > avoid trying to abstract "methods" via a HAL. It's the Linux philosophy
> > as much as possible (even when defeated by ACPI).
> >
> > But if we're going to be forced by vendors into HALs, we can also make
> > sure that whatever they come up with is half reasonable :-)
> 
> I think there is more to be concerned about regarding binary blobs
> than HALs.  Many of the new SoCs require closed binaries to use all
> the hardware right now (graphics cores in particular).
> 
> Board vendors seem to be taking the plunge and modifying the kernel
> rather than trying to create a HAL for driving board specific
> features.

In my view HALs are a bad idea, they constrain you to one calling method
and make it difficult to evolve support in the kernel. I belive it is
part of the reason that we've always tried to avoid a standardised
kernel driver interface.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From broonie at opensource.wolfsonmicro.com  Mon Jun 14 16:08:01 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 14 Jun 2010 21:08:01 +0100
Subject: Request review of device tree documentation
In-Reply-To: <alpine.LFD.2.00.1006141432530.13427@xanadu.home>
References: <AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>
	<20100614160201.GD9550@shareable.org>
	<4C165FD1.6080505@firmworks.com>
	<alpine.LFD.2.00.1006141311580.13427@xanadu.home>
	<4C1672FF.3060407@firmworks.com>
	<alpine.LFD.2.00.1006141432530.13427@xanadu.home>
Message-ID: <20100614200800.GF10776@sirena.org.uk>

On Mon, Jun 14, 2010 at 03:40:19PM -0400, Nicolas Pitre wrote:
> On Mon, 14 Jun 2010, Mitch Bradley wrote:

> > Arranging for a JTAG dongle to appear at the customer site, then 
> > getting it set up and the necessary software installed and configured 
> > on a suitable host system, typically requires several days at best, 
> > plus potentially a lot of fiddling depending on what sort of host 
> > system the customer happens to have.

> Well, if I may use the SheevaPlug as an example, the actual FT2232 chip 
> currently used in most of those USB-JTAG dongle was provided directly on 
> the board.  So you have this standard mini-B type USB connector on the 
> side of the device from which you get both a serial console and a JTAG 
> interface.  All you need is a standard USB cable, just like the one you 
> get with a MP3 player or a digital camera, so there are plenty of those 
> around.

The other thing here is of course that if JTAG is a problem serial or
other console access is likely to also be a problem - it's likely to not
be physically present and at least as painful to set up as JTAG.


From konkers at android.com  Mon Jun 14 17:10:16 2010
From: konkers at android.com (Erik Gilling)
Date: Mon, 14 Jun 2010 14:10:16 -0700
Subject: [PATCH v3 00/11] [ARM] tegra: tegra support
In-Reply-To: <1271198563-10424-1-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
Message-ID: <1276549827-2688-1-git-send-email-konkers@android.com>

This is the 3rd and hopefully final version of initial support for the Tegra
sub architecture.  Assuming no major issues come up, I'll be submitting
these patches (possibly minus the fb support) to linux-next later this week.
Thanks to all who have given feedback on the previous versions.

git://android.git.kernel.org/kernel/tegra.git  for-next

Cheers,
    Erik



From konkers at android.com  Mon Jun 14 17:10:17 2010
From: konkers at android.com (Erik Gilling)
Date: Mon, 14 Jun 2010 14:10:17 -0700
Subject: [PATCH v3 01/11] [ARM] tegra: initial tegra support
In-Reply-To: <1276549827-2688-1-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
Message-ID: <1276549827-2688-2-git-send-email-konkers@android.com>

v2: Fixes from Mike Rapoport
	- remove unused header files (mach/dma.h and mach/nand.h)
	- remove tegra 1 references from Makefile.boot

v2: fixes from Russell King
	- remove mach/io.h include from mach/iomap.h
	- fix whitespace in Kconfig

v2: from Colin Cross
	- fix invalid immediate in debug-macro.S

v3:
	- allow selection of multiple boards

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Erik Gilling <konkers at android.com>
---
 arch/arm/Kconfig                               |   13 ++
 arch/arm/Makefile                              |    1 +
 arch/arm/mach-tegra/Kconfig                    |   49 ++++++
 arch/arm/mach-tegra/Makefile                   |    2 +
 arch/arm/mach-tegra/Makefile.boot              |    3 +
 arch/arm/mach-tegra/board.h                    |   32 ++++
 arch/arm/mach-tegra/common.c                   |   44 +++++
 arch/arm/mach-tegra/include/mach/barriers.h    |   30 ++++
 arch/arm/mach-tegra/include/mach/debug-macro.S |   46 ++++++
 arch/arm/mach-tegra/include/mach/entry-macro.S |  118 ++++++++++++++
 arch/arm/mach-tegra/include/mach/hardware.h    |   24 +++
 arch/arm/mach-tegra/include/mach/io.h          |   79 +++++++++
 arch/arm/mach-tegra/include/mach/iomap.h       |  203 ++++++++++++++++++++++++
 arch/arm/mach-tegra/include/mach/memory.h      |   28 ++++
 arch/arm/mach-tegra/include/mach/system.h      |   39 +++++
 arch/arm/mach-tegra/include/mach/timex.h       |   26 +++
 arch/arm/mach-tegra/include/mach/uncompress.h  |   78 +++++++++
 arch/arm/mach-tegra/include/mach/vmalloc.h     |   28 ++++
 arch/arm/mach-tegra/io.c                       |   78 +++++++++
 arch/arm/mm/Kconfig                            |    3 +-
 20 files changed, 923 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-tegra/Kconfig
 create mode 100644 arch/arm/mach-tegra/Makefile
 create mode 100644 arch/arm/mach-tegra/Makefile.boot
 create mode 100644 arch/arm/mach-tegra/board.h
 create mode 100644 arch/arm/mach-tegra/common.c
 create mode 100644 arch/arm/mach-tegra/include/mach/barriers.h
 create mode 100644 arch/arm/mach-tegra/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-tegra/include/mach/entry-macro.S
 create mode 100644 arch/arm/mach-tegra/include/mach/hardware.h
 create mode 100644 arch/arm/mach-tegra/include/mach/io.h
 create mode 100644 arch/arm/mach-tegra/include/mach/iomap.h
 create mode 100644 arch/arm/mach-tegra/include/mach/memory.h
 create mode 100644 arch/arm/mach-tegra/include/mach/system.h
 create mode 100644 arch/arm/mach-tegra/include/mach/timex.h
 create mode 100644 arch/arm/mach-tegra/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-tegra/include/mach/vmalloc.h
 create mode 100644 arch/arm/mach-tegra/io.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..626a3cb 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -561,6 +561,17 @@ config ARCH_NUC93X
 	  Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
 	  low-power and high performance MPEG-4/JPEG multimedia controller chip.
 
+config ARCH_TEGRA
+	bool "NVIDIA Tegra"
+	select GENERIC_TIME
+	select GENERIC_CLOCKEVENTS
+	select GENERIC_GPIO
+	select HAVE_CLK
+	select ARCH_HAS_BARRIERS if CACHE_L2X0
+	help
+	  This enables support for NVIDIA Tegra based systems (Tegra APX,
+	  Tegra 6xx and Tegra 2 series).
+
 config ARCH_PNX4008
 	bool "Philips Nexperia PNX4008 Mobile"
 	select CPU_ARM926T
@@ -908,6 +919,8 @@ source "arch/arm/mach-shmobile/Kconfig"
 
 source "arch/arm/plat-stmp3xxx/Kconfig"
 
+source "arch/arm/mach-tegra/Kconfig"
+
 source "arch/arm/mach-u300/Kconfig"
 
 source "arch/arm/mach-ux500/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 64ba313..24c437a 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -175,6 +175,7 @@ machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile
 machine-$(CONFIG_ARCH_STMP378X)		:= stmp378x
 machine-$(CONFIG_ARCH_STMP37XX)		:= stmp37xx
+machine-$(CONFIG_ARCH_TEGRA)		:= tegra
 machine-$(CONFIG_ARCH_U300)		:= u300
 machine-$(CONFIG_ARCH_U8500)		:= ux500
 machine-$(CONFIG_ARCH_VERSATILE)	:= versatile
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
new file mode 100644
index 0000000..bcbda96
--- /dev/null
+++ b/arch/arm/mach-tegra/Kconfig
@@ -0,0 +1,49 @@
+if ARCH_TEGRA
+
+comment "NVIDIA Tegra options"
+
+choice
+	prompt "Select Tegra processor family for target system"
+
+config ARCH_TEGRA_2x_SOC
+	bool "Tegra 2 family"
+	select CPU_V7
+	select ARM_GIC
+	help
+	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
+	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
+
+endchoice
+
+comment "Tegra board type"
+
+config MACH_HARMONY
+       bool "Harmony board"
+       help
+         Support for nVidia Harmony development platform
+
+choice
+        prompt "Low-level debug console UART"
+        default TEGRA_DEBUG_UART_NONE
+
+config TEGRA_DEBUG_UART_NONE
+        bool "None"
+
+config TEGRA_DEBUG_UARTA
+        bool "UART-A"
+
+config TEGRA_DEBUG_UARTB
+        bool "UART-B"
+
+config TEGRA_DEBUG_UARTC
+        bool "UART-C"
+
+config TEGRA_DEBUG_UARTD
+        bool "UART-D"
+
+config TEGRA_DEBUG_UARTE
+        bool "UART-E"
+
+endchoice
+
+endif
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
new file mode 100644
index 0000000..81f003d
--- /dev/null
+++ b/arch/arm/mach-tegra/Makefile
@@ -0,0 +1,2 @@
+obj-y                                   += common.o
+obj-y                                   += io.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
new file mode 100644
index 0000000..db52d61
--- /dev/null
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00008000
+params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00000100
+initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC)	:= 0x00800000
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
new file mode 100644
index 0000000..3d06354
--- /dev/null
+++ b/arch/arm/mach-tegra/board.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-tegra/board.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_BOARD_H
+#define __MACH_TEGRA_BOARD_H
+
+#include <linux/types.h>
+
+void __init tegra_common_init(void);
+void __init tegra_map_common_io(void);
+void __init tegra_init_irq(void);
+void __init tegra_init_clock(void);
+
+extern struct sys_timer tegra_timer;
+#endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
new file mode 100644
index 0000000..20875ee
--- /dev/null
+++ b/arch/arm/mach-tegra/common.c
@@ -0,0 +1,44 @@
+/*
+ * arch/arm/mach-tegra/board-harmony.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/iomap.h>
+
+#include "board.h"
+
+void __init tegra_init_cache(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+	void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
+
+	writel(0x331, p + L2X0_TAG_LATENCY_CTRL);
+	writel(0x441, p + L2X0_DATA_LATENCY_CTRL);
+
+	l2x0_init(p, 0x6C080001, 0x8200c3fe);
+#endif
+}
+
+void __init tegra_common_init(void)
+{
+	tegra_init_cache();
+}
diff --git a/arch/arm/mach-tegra/include/mach/barriers.h b/arch/arm/mach-tegra/include/mach/barriers.h
new file mode 100644
index 0000000..cc11517
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/barriers.h
@@ -0,0 +1,30 @@
+/*
+ * arch/arm/mach-realview/include/mach/barriers.h
+ *
+ * Copyright (C) 2010 ARM Ltd.
+ * Written by Catalin Marinas <catalin.marinas at arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __MACH_BARRIERS_H
+#define __MACH_BARRIERS_H
+
+#include <asm/outercache.h>
+
+#define rmb()		dmb()
+#define wmb()		do { dsb(); outer_sync(); } while (0)
+#define mb()		wmb()
+
+#endif	/* __MACH_BARRIERS_H */
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
new file mode 100644
index 0000000..55a3956
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -0,0 +1,46 @@
+/*
+ * arch/arm/mach-tegra/include/mach/debug-macro.S
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <mach/io.h>
+
+	.macro  addruart,rx, tmp
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                 @ MMU enabled?
+        ldreq   \rx, =IO_APB_PHYS       @ physical
+        ldrne   \rx, =IO_APB_VIRT        @ virtual
+#if defined(CONFIG_TEGRA_DEBUG_UART_NONE)
+#error "A debug UART must be selected in the kernel config to use DEBUG_LL"
+#elif defined(CONFIG_TEGRA_DEBUG_UARTA)
+        orr     \rx, \rx, #0x6000
+#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
+	ldr	\tmp, =0x6040
+        orr     \rx, \rx, \tmp
+#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
+        orr     \rx, \rx, #0x6200
+#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
+        orr     \rx, \rx, #0x6300
+#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
+        orr     \rx, \rx, #0x6400
+#endif
+	.endm
+
+#define UART_SHIFT	2
+#include <asm/hardware/debug-8250.S>
+
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
new file mode 100644
index 0000000..2ba9e5c
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -0,0 +1,118 @@
+/* arch/arm/mach-tegra/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2009 Palm, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <mach/iomap.h>
+#include <mach/io.h>
+
+#if defined(CONFIG_ARM_GIC)
+
+#include <asm/hardware/gic.h>
+
+	/* Uses the GIC interrupt controller built into the cpu */
+#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
+
+	.macro	disable_fiq
+	.endm
+
+	.macro	get_irqnr_preamble, base, tmp
+	movw \base, #(ICTRL_BASE & 0x0000ffff)
+	movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
+	.endm
+
+	.macro  arch_ret_to_user, tmp1, tmp2
+	.endm
+
+	/*
+	 * The interrupt numbering scheme is defined in the
+	 * interrupt controller spec.  To wit:
+	 *
+	 * Interrupts 0-15 are IPI
+	 * 16-28 are reserved
+	 * 29-31 are local.  We allow 30 to be used for the watchdog.
+	 * 32-1020 are global
+	 * 1021-1022 are reserved
+	 * 1023 is "spurious" (no interrupt)
+	 *
+	 * For now, we ignore all local interrupts so only return an interrupt
+	 * if it's between 30 and 1020.  The test_for_ipi routine below will
+	 * pick up on IPIs.
+	 *
+	 * A simple read from the controller will tell us the number of the
+	 * highest priority enabled interrupt.  We then just need to check
+	 * whether it is in the valid range for an IRQ (30-1020 inclusive).
+	 */
+
+	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+	/* bits 12-10 = src CPU, 9-0 = int # */
+	ldr     \irqstat, [\base, #GIC_CPU_INTACK]
+
+	ldr		\tmp, =1021
+
+	bic     \irqnr, \irqstat, #0x1c00
+
+	cmp     \irqnr, #29
+	cmpcc	\irqnr, \irqnr
+	cmpne	\irqnr, \tmp
+	cmpcs	\irqnr, \irqnr
+
+	.endm
+
+	/* We assume that irqstat (the raw value of the IRQ acknowledge
+	 * register) is preserved from the macro above.
+	 * If there is an IPI, we immediately signal end of interrupt on the
+	 * controller, since this requires the original irqstat value which
+	 * we won't easily be able to recreate later.
+	 */
+
+	.macro test_for_ipi, irqnr, irqstat, base, tmp
+	bic	\irqnr, \irqstat, #0x1c00
+	cmp	\irqnr, #16
+	strcc	\irqstat, [\base, #GIC_CPU_EOI]
+	cmpcs	\irqnr, \irqnr
+	.endm
+
+	/* As above, this assumes that irqstat and base are preserved.. */
+
+	.macro test_for_ltirq, irqnr, irqstat, base, tmp
+	bic	\irqnr, \irqstat, #0x1c00
+	mov 	\tmp, #0
+	cmp	\irqnr, #29
+	moveq	\tmp, #1
+	streq	\irqstat, [\base, #GIC_CPU_EOI]
+	cmp	\tmp, #0
+	.endm
+
+#else
+	/* legacy interrupt controller for AP16 */
+	.macro	disable_fiq
+	.endm
+
+	.macro	get_irqnr_preamble, base, tmp
+	@ enable imprecise aborts
+	cpsie	a
+	@ EVP base at 0xf010f000
+	mov \base, #0xf0000000
+	orr \base, #0x00100000
+	orr \base, #0x0000f000
+	.endm
+
+	.macro	arch_ret_to_user, tmp1, tmp2
+	.endm
+
+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+	ldr \irqnr, [\base, #0x20]	@ EVT_IRQ_STS
+	cmp \irqnr, #0x80
+	.endm
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/hardware.h b/arch/arm/mach-tegra/include/mach/hardware.h
new file mode 100644
index 0000000..6014edf
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/hardware.h
@@ -0,0 +1,24 @@
+/*
+ * arch/arm/mach-tegra/include/mach/hardware.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_HARDWARE_H
+#define __MACH_TEGRA_HARDWARE_H
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
new file mode 100644
index 0000000..35edfc3
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/io.h
@@ -0,0 +1,79 @@
+/*
+ * arch/arm/mach-tegra/include/mach/io.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IO_H
+#define __MACH_TEGRA_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/* On TEGRA, many peripherals are very closely packed in
+ * two 256MB io windows (that actually only use about 64KB
+ * at the start of each).
+ *
+ * We will just map the first 1MB of each window (to minimize
+ * pt entries needed) and provide a macro to transform physical
+ * io addresses to an appropriate void __iomem *.
+ *
+ */
+
+#define IO_CPU_PHYS     0x50040000
+#define IO_CPU_VIRT     0xFE000000
+#define IO_CPU_SIZE	SZ_16K
+
+#define IO_PPSB_PHYS	0x60000000
+#define IO_PPSB_VIRT	0xFE200000
+#define IO_PPSB_SIZE	SZ_1M
+
+#define IO_APB_PHYS	0x70000000
+#define IO_APB_VIRT	0xFE300000
+#define IO_APB_SIZE	SZ_1M
+
+#define IO_TO_VIRT_BETWEEN(p, st, sz)	((p) >= (st) && (p) < ((st) + (sz)))
+#define IO_TO_VIRT_XLATE(p, pst, vst)	(((p) - (pst) + (vst)))
+
+#define IO_TO_VIRT(n) ( \
+	IO_TO_VIRT_BETWEEN((n), IO_PPSB_PHYS, IO_PPSB_SIZE) ?		\
+		IO_TO_VIRT_XLATE((n), IO_PPSB_PHYS, IO_PPSB_VIRT) :	\
+	IO_TO_VIRT_BETWEEN((n), IO_APB_PHYS, IO_APB_SIZE) ?		\
+		IO_TO_VIRT_XLATE((n), IO_APB_PHYS, IO_APB_VIRT) :	\
+	IO_TO_VIRT_BETWEEN((n), IO_CPU_PHYS, IO_CPU_SIZE) ?		\
+		IO_TO_VIRT_XLATE((n), IO_CPU_PHYS, IO_CPU_VIRT) :	\
+	0)
+
+#ifndef __ASSEMBLER__
+
+#define __arch_ioremap(p, s, t)	tegra_ioremap(p, s, t)
+#define __arch_iounmap(v)	tegra_iounmap(v)
+
+void __iomem *tegra_ioremap(unsigned long phys, size_t size, unsigned int type);
+void tegra_iounmap(volatile void __iomem *addr);
+
+#define IO_ADDRESS(n) ((void __iomem *) IO_TO_VIRT(n))
+
+static inline void __iomem *__io(unsigned long addr)
+{
+	return (void __iomem *)addr;
+}
+#define __io(a)         __io(a)
+#define __mem_pci(a)    (a)
+
+#endif
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
new file mode 100644
index 0000000..1741f7d
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -0,0 +1,203 @@
+/*
+ * arch/arm/mach-tegra/include/mach/iomap.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IOMAP_H
+#define __MACH_TEGRA_IOMAP_H
+
+#include <asm/sizes.h>
+
+#define TEGRA_ARM_PERIF_BASE		0x50040000
+#define TEGRA_ARM_PERIF_SIZE		SZ_8K
+
+#define TEGRA_ARM_INT_DIST_BASE		0x50041000
+#define TEGRA_ARM_INT_DIST_SIZE		SZ_4K
+
+#define TEGRA_DISPLAY_BASE		0x54200000
+#define TEGRA_DISPLAY_SIZE		SZ_256K
+
+#define TEGRA_DISPLAY2_BASE		0x54240000
+#define TEGRA_DISPLAY2_SIZE		SZ_256K
+
+#define TEGRA_PRIMARY_ICTLR_BASE	0x60004000
+#define TEGRA_PRIMARY_ICTLR_SIZE	SZ_64
+
+#define TEGRA_SECONDARY_ICTLR_BASE	0x60004100
+#define TEGRA_SECONDARY_ICTLR_SIZE	SZ_64
+
+#define TEGRA_TERTIARY_ICTLR_BASE	0x60004200
+#define TEGRA_TERTIARY_ICTLR_SIZE	SZ_64
+
+#define TEGRA_QUATERNARY_ICTLR_BASE	0x60004300
+#define TEGRA_QUATERNARY_ICTLR_SIZE	SZ_64
+
+#define TEGRA_TMR1_BASE			0x60005000
+#define TEGRA_TMR1_SIZE			SZ_8
+
+#define TEGRA_TMR2_BASE			0x60005008
+#define TEGRA_TMR2_SIZE			SZ_8
+
+#define TEGRA_TMRUS_BASE		0x60005010
+#define TEGRA_TMRUS_SIZE		SZ_64
+
+#define TEGRA_TMR3_BASE			0x60005050
+#define TEGRA_TMR3_SIZE			SZ_8
+
+#define TEGRA_TMR4_BASE			0x60005058
+#define TEGRA_TMR4_SIZE			SZ_8
+
+#define TEGRA_CLK_RESET_BASE		0x60006000
+#define TEGRA_CLK_RESET_SIZE		SZ_4K
+
+#define TEGRA_FLOW_CTRL_BASE		0x60007000
+#define TEGRA_FLOW_CTRL_SIZE		20
+
+#define TEGRA_STATMON_BASE		0x6000C4000
+#define TEGRA_STATMON_SIZE		SZ_1K
+
+#define TEGRA_GPIO_BASE			0x6000D000
+#define TEGRA_GPIO_SIZE			SZ_4K
+
+#define TEGRA_EXCEPTION_VECTORS_BASE    0x6000F000
+#define TEGRA_EXCEPTION_VECTORS_SIZE    SZ_4K
+
+#define TEGRA_APB_MISC_BASE		0x70000000
+#define TEGRA_APB_MISC_SIZE		SZ_4K
+
+#define TEGRA_AC97_BASE			0x70002000
+#define TEGRA_AC97_SIZE			SZ_512
+
+#define TEGRA_SPDIF_BASE		0x70002400
+#define TEGRA_SPDIF_SIZE		SZ_512
+
+#define TEGRA_I2S1_BASE			0x70002800
+#define TEGRA_I2S1_SIZE			SZ_256
+
+#define TEGRA_I2S2_BASE			0x70002A00
+#define TEGRA_I2S2_SIZE			SZ_256
+
+#define TEGRA_UARTA_BASE		0x70006000
+#define TEGRA_UARTA_SIZE		SZ_64
+
+#define TEGRA_UARTB_BASE		0x70006040
+#define TEGRA_UARTB_SIZE		SZ_64
+
+#define TEGRA_UARTC_BASE		0x70006200
+#define TEGRA_UARTC_SIZE		SZ_256
+
+#define TEGRA_UARTD_BASE		0x70006300
+#define TEGRA_UARTD_SIZE		SZ_256
+
+#define TEGRA_UARTE_BASE		0x70006400
+#define TEGRA_UARTE_SIZE		SZ_256
+
+#define TEGRA_NAND_BASE			0x70008000
+#define TEGRA_NAND_SIZE			SZ_256
+
+#define TEGRA_HSMMC_BASE		0x70008500
+#define TEGRA_HSMMC_SIZE		SZ_256
+
+#define TEGRA_SNOR_BASE			0x70009000
+#define TEGRA_SNOR_SIZE			SZ_4K
+
+#define TEGRA_PWFM_BASE			0x7000A000
+#define TEGRA_PWFM_SIZE			SZ_256
+
+#define TEGRA_MIPI_BASE			0x7000B000
+#define TEGRA_MIPI_SIZE			SZ_256
+
+#define TEGRA_I2C_BASE			0x7000C000
+#define TEGRA_I2C_SIZE			SZ_256
+
+#define TEGRA_TWC_BASE			0x7000C100
+#define TEGRA_TWC_SIZE			SZ_256
+
+#define TEGRA_SPI_BASE			0x7000C380
+#define TEGRA_SPI_SIZE			48
+
+#define TEGRA_I2C2_BASE			0x7000C400
+#define TEGRA_I2C2_SIZE			SZ_256
+
+#define TEGRA_I2C3_BASE			0x7000C500
+#define TEGRA_I2C3_SIZE			SZ_256
+
+#define TEGRA_OWR_BASE			0x7000D000
+#define TEGRA_OWR_SIZE			80
+
+#define TEGRA_DVC_BASE			0x7000D000
+#define TEGRA_DVC_SIZE			SZ_512
+
+#define TEGRA_SPI1_BASE			0x7000D400
+#define TEGRA_SPI1_SIZE			SZ_512
+
+#define TEGRA_SPI2_BASE			0x7000D600
+#define TEGRA_SPI2_SIZE			SZ_512
+
+#define TEGRA_SPI3_BASE			0x7000D800
+#define TEGRA_SPI3_SIZE			SZ_512
+
+#define TEGRA_SPI4_BASE			0x7000DA00
+#define TEGRA_SPI4_SIZE			SZ_512
+
+#define TEGRA_RTC_BASE			0x7000E000
+#define TEGRA_RTC_SIZE			SZ_256
+
+#define TEGRA_KBC_BASE			0x7000E200
+#define TEGRA_KBC_SIZE			SZ_256
+
+#define TEGRA_PMC_BASE			0x7000E400
+#define TEGRA_PMC_SIZE			SZ_256
+
+#define TEGRA_MC_BASE			0x7000F000
+#define TEGRA_MC_SIZE			SZ_1K
+
+#define TEGRA_EMC_BASE			0x7000F400
+#define TEGRA_EMC_SIZE			SZ_1K
+
+#define TEGRA_FUSE_BASE			0x7000F800
+#define TEGRA_FUSE_SIZE			SZ_1K
+
+#define TEGRA_KFUSE_BASE		0x7000FC00
+#define TEGRA_KFUSE_SIZE		SZ_1K
+
+#define TEGRA_CSITE_BASE		0x70040000
+#define TEGRA_CSITE_SIZE		SZ_256K
+
+#define TEGRA_USB_BASE			0xC5000000
+#define TEGRA_USB_SIZE			SZ_16K
+
+#define TEGRA_USB1_BASE			0xC5004000
+#define TEGRA_USB1_SIZE			SZ_16K
+
+#define TEGRA_USB2_BASE			0xC5008000
+#define TEGRA_USB2_SIZE			SZ_16K
+
+#define TEGRA_SDMMC1_BASE		0xC8000000
+#define TEGRA_SDMMC1_SIZE		SZ_512
+
+#define TEGRA_SDMMC2_BASE		0xC8000200
+#define TEGRA_SDMMC2_SIZE		SZ_512
+
+#define TEGRA_SDMMC3_BASE		0xC8000400
+#define TEGRA_SDMMC3_SIZE		SZ_512
+
+#define TEGRA_SDMMC4_BASE		0xC8000600
+#define TEGRA_SDMMC4_SIZE		SZ_512
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h
new file mode 100644
index 0000000..6151bab
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/memory.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-tegra/include/mach/memory.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_MEMORY_H
+#define __MACH_TEGRA_MEMORY_H
+
+/* physical offset of RAM */
+#define PHYS_OFFSET		UL(0)
+
+#endif
+
diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/include/mach/system.h
new file mode 100644
index 0000000..84d5d46
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/system.h
@@ -0,0 +1,39 @@
+/*
+ * arch/arm/mach-tegra/include/mach/system.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_SYSTEM_H
+#define __MACH_TEGRA_SYSTEM_H
+
+#include <mach/hardware.h>
+#include <mach/iomap.h>
+
+static inline void arch_idle(void)
+{
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+	void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04);
+	u32 reg = readl(reset);
+	reg |= 0x04;
+	writel(reg, reset);
+}
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/timex.h b/arch/arm/mach-tegra/include/mach/timex.h
new file mode 100644
index 0000000..a44ccbd
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/timex.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-tegra/include/mach/timex.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_TIMEX_H
+#define __MACH_TEGRA_TIMEX_H
+
+#define CLOCK_TICK_RATE		1000000
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/uncompress.h b/arch/arm/mach-tegra/include/mach/uncompress.h
new file mode 100644
index 0000000..6c4dd81
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/uncompress.h
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/mach-tegra/include/mach/uncompress.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_UNCOMPRESS_H
+#define __MACH_TEGRA_UNCOMPRESS_H
+
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+
+#include <mach/iomap.h>
+
+#if defined(CONFIG_TEGRA_DEBUG_UARTA)
+#define DEBUG_UART_BASE TEGRA_UARTA_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTB)
+#define DEBUG_UART_BASE TEGRA_UARTB_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTC)
+#define DEBUG_UART_BASE TEGRA_UARTC_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTD)
+#define DEBUG_UART_BASE TEGRA_UARTD_BASE
+#elif defined(CONFIG_TEGRA_DEBUG_UARTE)
+#define DEBUG_UART_BASE TEGRA_UARTE_BASE
+#else
+#define DEBUG_UART_BASE NULL
+#endif
+
+static void putc(int c)
+{
+	volatile u8 *uart = (volatile u8 *)DEBUG_UART_BASE;
+	int shift = 2;
+
+	if (uart == NULL)
+		return;
+
+	while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
+		barrier();
+	uart[UART_TX << shift] = c;
+}
+
+static inline void flush(void)
+{
+}
+
+static inline void arch_decomp_setup(void)
+{
+	volatile u8 *uart = (volatile u8 *)DEBUG_UART_BASE;
+	int shift = 2;
+
+	if (uart == NULL)
+		return;
+
+	uart[UART_LCR << shift] |= UART_LCR_DLAB;
+	uart[UART_DLL << shift] = 0x75;
+	uart[UART_DLM << shift] = 0x0;
+	uart[UART_LCR << shift] = 3;
+}
+
+static inline void arch_decomp_wdog(void)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/vmalloc.h b/arch/arm/mach-tegra/include/mach/vmalloc.h
new file mode 100644
index 0000000..267a141
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/vmalloc.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-tegra/include/mach/vmalloc.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_VMALLOC_H
+#define __MACH_TEGRA_VMALLOC_H
+
+#include <asm/sizes.h>
+
+#define VMALLOC_END        0xFE000000
+
+#endif
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
new file mode 100644
index 0000000..9fe2c5c
--- /dev/null
+++ b/arch/arm/mach-tegra/io.c
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/mach-tegra/io.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+
+#include "board.h"
+
+static struct map_desc tegra_io_desc[] __initdata = {
+	{
+		.virtual = IO_PPSB_VIRT,
+		.pfn = __phys_to_pfn(IO_PPSB_PHYS),
+		.length = IO_PPSB_SIZE,
+		.type = MT_DEVICE,
+	},
+	{
+		.virtual = IO_APB_VIRT,
+		.pfn = __phys_to_pfn(IO_APB_PHYS),
+		.length = IO_APB_SIZE,
+		.type = MT_DEVICE,
+	},
+	{
+		.virtual = IO_CPU_VIRT,
+		.pfn = __phys_to_pfn(IO_CPU_PHYS),
+		.length = IO_CPU_SIZE,
+		.type = MT_DEVICE,
+	},
+};
+
+void __init tegra_map_common_io(void)
+{
+	iotable_init(tegra_io_desc, ARRAY_SIZE(tegra_io_desc));
+}
+
+/*
+ * Intercept ioremap() requests for addresses in our fixed mapping regions.
+ */
+void __iomem *tegra_ioremap(unsigned long p, size_t size, unsigned int type)
+{
+	void __iomem *v = IO_ADDRESS(p);
+	if (v == NULL)
+		v = __arm_ioremap(p, size, type);
+	return v;
+}
+EXPORT_SYMBOL(tegra_ioremap);
+
+void tegra_iounmap(volatile void __iomem *addr)
+{
+	unsigned long virt = (unsigned long)addr;
+
+	if (virt >= VMALLOC_START && virt < VMALLOC_END)
+		__iounmap(addr);
+}
+EXPORT_SYMBOL(tegra_iounmap);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..0b6172f 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -763,7 +763,8 @@ config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
 	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
 		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
-		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
+		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
+		   ARCH_TEGRA
 	default y
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC
-- 
1.6.5.6



From konkers at android.com  Mon Jun 14 17:10:23 2010
From: konkers at android.com (Erik Gilling)
Date: Mon, 14 Jun 2010 14:10:23 -0700
Subject: [PATCH v3 07/11] [ARM] tegra: add pinmux support
In-Reply-To: <1276549827-2688-7-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
	<1276549827-2688-3-git-send-email-konkers@android.com>
	<1276549827-2688-4-git-send-email-konkers@android.com>
	<1276549827-2688-5-git-send-email-konkers@android.com>
	<1276549827-2688-6-git-send-email-konkers@android.com>
	<1276549827-2688-7-git-send-email-konkers@android.com>
Message-ID: <1276549827-2688-8-git-send-email-konkers@android.com>

v2: fixes from Russell King
	- include linux/io.h instead of asm/io.h
v3:
	- Add drive strength controls
	- Replace typedef enums with plain enums

Signed-off-by: Erik Gilling <konkers at android.com>
Signed-off-by: Colin Cross <ccross at android.com>
---
 arch/arm/mach-tegra/Makefile              |    2 +
 arch/arm/mach-tegra/include/mach/pinmux.h |  348 +++++++++++
 arch/arm/mach-tegra/pinmux.c              |  945 +++++++++++++++++++++++++++++
 3 files changed, 1295 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/pinmux.h
 create mode 100644 arch/arm/mach-tegra/pinmux.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 122f7dc..5e47a71 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -4,6 +4,8 @@ obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
 obj-y                                   += gpio.o
+obj-y                                   += pinmux.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/include/mach/pinmux.h b/arch/arm/mach-tegra/include/mach/pinmux.h
new file mode 100644
index 0000000..41c8ce5
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/pinmux.h
@@ -0,0 +1,348 @@
+/*
+ * linux/arch/arm/mach-tegra/include/mach/pinmux.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_PINMUX_H
+#define __MACH_TEGRA_PINMUX_H
+
+enum tegra_pingroup {
+	TEGRA_PINGROUP_ATA = 0,
+	TEGRA_PINGROUP_ATB,
+	TEGRA_PINGROUP_ATC,
+	TEGRA_PINGROUP_ATD,
+	TEGRA_PINGROUP_ATE,
+	TEGRA_PINGROUP_CDEV1,
+	TEGRA_PINGROUP_CDEV2,
+	TEGRA_PINGROUP_CRTP,
+	TEGRA_PINGROUP_CSUS,
+	TEGRA_PINGROUP_DAP1,
+	TEGRA_PINGROUP_DAP2,
+	TEGRA_PINGROUP_DAP3,
+	TEGRA_PINGROUP_DAP4,
+	TEGRA_PINGROUP_DDC,
+	TEGRA_PINGROUP_DTA,
+	TEGRA_PINGROUP_DTB,
+	TEGRA_PINGROUP_DTC,
+	TEGRA_PINGROUP_DTD,
+	TEGRA_PINGROUP_DTE,
+	TEGRA_PINGROUP_DTF,
+	TEGRA_PINGROUP_GMA,
+	TEGRA_PINGROUP_GMB,
+	TEGRA_PINGROUP_GMC,
+	TEGRA_PINGROUP_GMD,
+	TEGRA_PINGROUP_GME,
+	TEGRA_PINGROUP_GPU,
+	TEGRA_PINGROUP_GPU7,
+	TEGRA_PINGROUP_GPV,
+	TEGRA_PINGROUP_HDINT,
+	TEGRA_PINGROUP_I2CP,
+	TEGRA_PINGROUP_IRRX,
+	TEGRA_PINGROUP_IRTX,
+	TEGRA_PINGROUP_KBCA,
+	TEGRA_PINGROUP_KBCB,
+	TEGRA_PINGROUP_KBCC,
+	TEGRA_PINGROUP_KBCD,
+	TEGRA_PINGROUP_KBCE,
+	TEGRA_PINGROUP_KBCF,
+	TEGRA_PINGROUP_LCSN,
+	TEGRA_PINGROUP_LD0,
+	TEGRA_PINGROUP_LD1,
+	TEGRA_PINGROUP_LD10,
+	TEGRA_PINGROUP_LD11,
+	TEGRA_PINGROUP_LD12,
+	TEGRA_PINGROUP_LD13,
+	TEGRA_PINGROUP_LD14,
+	TEGRA_PINGROUP_LD15,
+	TEGRA_PINGROUP_LD16,
+	TEGRA_PINGROUP_LD17,
+	TEGRA_PINGROUP_LD2,
+	TEGRA_PINGROUP_LD3,
+	TEGRA_PINGROUP_LD4,
+	TEGRA_PINGROUP_LD5,
+	TEGRA_PINGROUP_LD6,
+	TEGRA_PINGROUP_LD7,
+	TEGRA_PINGROUP_LD8,
+	TEGRA_PINGROUP_LD9,
+	TEGRA_PINGROUP_LDC,
+	TEGRA_PINGROUP_LDI,
+	TEGRA_PINGROUP_LHP0,
+	TEGRA_PINGROUP_LHP1,
+	TEGRA_PINGROUP_LHP2,
+	TEGRA_PINGROUP_LHS,
+	TEGRA_PINGROUP_LM0,
+	TEGRA_PINGROUP_LM1,
+	TEGRA_PINGROUP_LPP,
+	TEGRA_PINGROUP_LPW0,
+	TEGRA_PINGROUP_LPW1,
+	TEGRA_PINGROUP_LPW2,
+	TEGRA_PINGROUP_LSC0,
+	TEGRA_PINGROUP_LSC1,
+	TEGRA_PINGROUP_LSCK,
+	TEGRA_PINGROUP_LSDA,
+	TEGRA_PINGROUP_LSDI,
+	TEGRA_PINGROUP_LSPI,
+	TEGRA_PINGROUP_LVP0,
+	TEGRA_PINGROUP_LVP1,
+	TEGRA_PINGROUP_LVS,
+	TEGRA_PINGROUP_OWC,
+	TEGRA_PINGROUP_PMC,
+	TEGRA_PINGROUP_PTA,
+	TEGRA_PINGROUP_RM,
+	TEGRA_PINGROUP_SDB,
+	TEGRA_PINGROUP_SDC,
+	TEGRA_PINGROUP_SDD,
+	TEGRA_PINGROUP_SDIO1,
+	TEGRA_PINGROUP_SLXA,
+	TEGRA_PINGROUP_SLXC,
+	TEGRA_PINGROUP_SLXD,
+	TEGRA_PINGROUP_SLXK,
+	TEGRA_PINGROUP_SPDI,
+	TEGRA_PINGROUP_SPDO,
+	TEGRA_PINGROUP_SPIA,
+	TEGRA_PINGROUP_SPIB,
+	TEGRA_PINGROUP_SPIC,
+	TEGRA_PINGROUP_SPID,
+	TEGRA_PINGROUP_SPIE,
+	TEGRA_PINGROUP_SPIF,
+	TEGRA_PINGROUP_SPIG,
+	TEGRA_PINGROUP_SPIH,
+	TEGRA_PINGROUP_UAA,
+	TEGRA_PINGROUP_UAB,
+	TEGRA_PINGROUP_UAC,
+	TEGRA_PINGROUP_UAD,
+	TEGRA_PINGROUP_UCA,
+	TEGRA_PINGROUP_UCB,
+	TEGRA_PINGROUP_UDA,
+	/* these pin groups only have pullup and pull down control */
+	TEGRA_PINGROUP_CK32,
+	TEGRA_PINGROUP_DDRC,
+	TEGRA_PINGROUP_PMCA,
+	TEGRA_PINGROUP_PMCB,
+	TEGRA_PINGROUP_PMCC,
+	TEGRA_PINGROUP_PMCD,
+	TEGRA_PINGROUP_PMCE,
+	TEGRA_PINGROUP_XM2C,
+	TEGRA_PINGROUP_XM2D,
+	TEGRA_MAX_PINGROUP,
+};
+
+enum tegra_mux_func {
+	TEGRA_MUX_RSVD = 0x8000,
+	TEGRA_MUX_RSVD1 = 0x8000,
+	TEGRA_MUX_RSVD2 = 0x8001,
+	TEGRA_MUX_RSVD3 = 0x8002,
+	TEGRA_MUX_RSVD4 = 0x8003,
+	TEGRA_MUX_NONE = -1,
+	TEGRA_MUX_AHB_CLK,
+	TEGRA_MUX_APB_CLK,
+	TEGRA_MUX_AUDIO_SYNC,
+	TEGRA_MUX_CRT,
+	TEGRA_MUX_DAP1,
+	TEGRA_MUX_DAP2,
+	TEGRA_MUX_DAP3,
+	TEGRA_MUX_DAP4,
+	TEGRA_MUX_DAP5,
+	TEGRA_MUX_DISPLAYA,
+	TEGRA_MUX_DISPLAYB,
+	TEGRA_MUX_EMC_TEST0_DLL,
+	TEGRA_MUX_EMC_TEST1_DLL,
+	TEGRA_MUX_GMI,
+	TEGRA_MUX_GMI_INT,
+	TEGRA_MUX_HDMI,
+	TEGRA_MUX_I2C,
+	TEGRA_MUX_I2C2,
+	TEGRA_MUX_I2C3,
+	TEGRA_MUX_IDE,
+	TEGRA_MUX_IRDA,
+	TEGRA_MUX_KBC,
+	TEGRA_MUX_MIO,
+	TEGRA_MUX_MIPI_HS,
+	TEGRA_MUX_NAND,
+	TEGRA_MUX_OSC,
+	TEGRA_MUX_OWR,
+	TEGRA_MUX_PCIE,
+	TEGRA_MUX_PLLA_OUT,
+	TEGRA_MUX_PLLC_OUT1,
+	TEGRA_MUX_PLLM_OUT1,
+	TEGRA_MUX_PLLP_OUT2,
+	TEGRA_MUX_PLLP_OUT3,
+	TEGRA_MUX_PLLP_OUT4,
+	TEGRA_MUX_PWM,
+	TEGRA_MUX_PWR_INTR,
+	TEGRA_MUX_PWR_ON,
+	TEGRA_MUX_RTCK,
+	TEGRA_MUX_SDIO1,
+	TEGRA_MUX_SDIO2,
+	TEGRA_MUX_SDIO3,
+	TEGRA_MUX_SDIO4,
+	TEGRA_MUX_SFLASH,
+	TEGRA_MUX_SPDIF,
+	TEGRA_MUX_SPI1,
+	TEGRA_MUX_SPI2,
+	TEGRA_MUX_SPI2_ALT,
+	TEGRA_MUX_SPI3,
+	TEGRA_MUX_SPI4,
+	TEGRA_MUX_TRACE,
+	TEGRA_MUX_TWC,
+	TEGRA_MUX_UARTA,
+	TEGRA_MUX_UARTB,
+	TEGRA_MUX_UARTC,
+	TEGRA_MUX_UARTD,
+	TEGRA_MUX_UARTE,
+	TEGRA_MUX_ULPI,
+	TEGRA_MUX_VI,
+	TEGRA_MUX_VI_SENSOR_CLK,
+	TEGRA_MUX_XIO,
+	TEGRA_MAX_MUX,
+};
+
+enum tegra_pullupdown {
+	TEGRA_PUPD_NORMAL = 0,
+	TEGRA_PUPD_PULL_DOWN,
+	TEGRA_PUPD_PULL_UP,
+};
+
+enum tegra_tristate {
+	TEGRA_TRI_NORMAL = 0,
+	TEGRA_TRI_TRISTATE = 1,
+};
+
+struct tegra_pingroup_config {
+	enum tegra_pingroup	pingroup;
+	enum tegra_mux_func	func;
+	enum tegra_pullupdown	pupd;
+	enum tegra_tristate	tristate;
+};
+
+enum tegra_slew {
+	TEGRA_SLEW_FASTEST = 0,
+	TEGRA_SLEW_FAST,
+	TEGRA_SLEW_SLOW,
+	TEGRA_SLEW_SLOWEST,
+	TEGRA_MAX_SLEW,
+};
+
+enum tegra_pull_strength {
+	TEGRA_PULL_0 = 0,
+	TEGRA_PULL_1,
+	TEGRA_PULL_2,
+	TEGRA_PULL_3,
+	TEGRA_PULL_4,
+	TEGRA_PULL_5,
+	TEGRA_PULL_6,
+	TEGRA_PULL_7,
+	TEGRA_PULL_8,
+	TEGRA_PULL_9,
+	TEGRA_PULL_10,
+	TEGRA_PULL_11,
+	TEGRA_PULL_12,
+	TEGRA_PULL_13,
+	TEGRA_PULL_14,
+	TEGRA_PULL_15,
+	TEGRA_PULL_16,
+	TEGRA_PULL_17,
+	TEGRA_PULL_18,
+	TEGRA_PULL_19,
+	TEGRA_PULL_20,
+	TEGRA_PULL_21,
+	TEGRA_PULL_22,
+	TEGRA_PULL_23,
+	TEGRA_PULL_24,
+	TEGRA_PULL_25,
+	TEGRA_PULL_26,
+	TEGRA_PULL_27,
+	TEGRA_PULL_28,
+	TEGRA_PULL_29,
+	TEGRA_PULL_30,
+	TEGRA_PULL_31,
+	TEGRA_MAX_PULL,
+};
+
+enum tegra_drive_pingroup {
+	TEGRA_DRIVE_PINGROUP_AO1 = 0,
+	TEGRA_DRIVE_PINGROUP_AO2,
+	TEGRA_DRIVE_PINGROUP_AT1,
+	TEGRA_DRIVE_PINGROUP_AT2,
+	TEGRA_DRIVE_PINGROUP_CDEV1,
+	TEGRA_DRIVE_PINGROUP_CDEV2,
+	TEGRA_DRIVE_PINGROUP_CSUS,
+	TEGRA_DRIVE_PINGROUP_DAP1,
+	TEGRA_DRIVE_PINGROUP_DAP2,
+	TEGRA_DRIVE_PINGROUP_DAP3,
+	TEGRA_DRIVE_PINGROUP_DAP4,
+	TEGRA_DRIVE_PINGROUP_DBG,
+	TEGRA_DRIVE_PINGROUP_LCD1,
+	TEGRA_DRIVE_PINGROUP_LCD2,
+	TEGRA_DRIVE_PINGROUP_SDMMC2,
+	TEGRA_DRIVE_PINGROUP_SDMMC3,
+	TEGRA_DRIVE_PINGROUP_SPI,
+	TEGRA_DRIVE_PINGROUP_UAA,
+	TEGRA_DRIVE_PINGROUP_UAB,
+	TEGRA_DRIVE_PINGROUP_UART2,
+	TEGRA_DRIVE_PINGROUP_UART3,
+	TEGRA_DRIVE_PINGROUP_VI1,
+	TEGRA_DRIVE_PINGROUP_VI2,
+	TEGRA_DRIVE_PINGROUP_XM2A,
+	TEGRA_DRIVE_PINGROUP_XM2C,
+	TEGRA_DRIVE_PINGROUP_XM2D,
+	TEGRA_DRIVE_PINGROUP_XM2CLK,
+	TEGRA_DRIVE_PINGROUP_MEMCOMP,
+	TEGRA_MAX_DRIVE_PINGROUP,
+};
+
+enum tegra_drive {
+	TEGRA_DRIVE_DIV_8 = 0,
+	TEGRA_DRIVE_DIV_4,
+	TEGRA_DRIVE_DIV_2,
+	TEGRA_DRIVE_DIV_1,
+	TEGRA_MAX_DRIVE,
+};
+
+enum tegra_hsm {
+	TEGRA_HSM_DISABLE = 0,
+	TEGRA_HSM_ENABLE,
+};
+
+enum tegra_schmitt {
+	TEGRA_SCHMITT_DISABLE = 0,
+	TEGRA_SCHMITT_ENABLE,
+};
+
+struct tegra_drive_pingroup_config {
+	enum tegra_drive_pingroup pingroup;
+	enum tegra_hsm hsm;
+	enum tegra_schmitt schmitt;
+	enum tegra_drive drive;
+	enum tegra_pull_strength pull_down;
+	enum tegra_pull_strength pull_up;
+	enum tegra_slew slew_rising;
+	enum tegra_slew slew_falling;
+};
+
+int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func);
+int tegra_pinmux_set_tristate(enum tegra_pingroup pg, enum tegra_tristate tristate);
+int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg, enum tegra_pullupdown pupd);
+
+void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup,
+	enum tegra_mux_func func, enum tegra_pullupdown pupd,
+	enum tegra_tristate tristate);
+
+void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len);
+
+void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
+	int len);
+
+#endif
+
diff --git a/arch/arm/mach-tegra/pinmux.c b/arch/arm/mach-tegra/pinmux.c
new file mode 100644
index 0000000..13ae102
--- /dev/null
+++ b/arch/arm/mach-tegra/pinmux.c
@@ -0,0 +1,945 @@
+/*
+ * linux/arch/arm/mach-tegra/pinmux.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+
+#include <mach/iomap.h>
+#include <mach/pinmux.h>
+
+
+#define TEGRA_TRI_STATE(x)	(0x14 + (4 * (x)))
+#define TEGRA_PP_MUX_CTL(x)	(0x80 + (4 * (x)))
+#define TEGRA_PP_PU_PD(x)	(0xa0 + (4 * (x)))
+
+#define REG_A 0
+#define REG_B 1
+#define REG_C 2
+#define REG_D 3
+#define REG_E 4
+#define REG_F 5
+#define REG_G 6
+
+#define REG_N -1
+
+#define HSM_EN(reg)	(((reg) >> 2) & 0x1)
+#define SCHMT_EN(reg)	(((reg) >> 3) & 0x1)
+#define LPMD(reg)	(((reg) >> 4) & 0x3)
+#define DRVDN(reg)	(((reg) >> 12) & 0x1f)
+#define DRVUP(reg)	(((reg) >> 20) & 0x1f)
+#define SLWR(reg)	(((reg) >> 28) & 0x3)
+#define SLWF(reg)	(((reg) >> 30) & 0x3)
+
+struct tegra_pingroup_desc {
+	const char *name;
+	int funcs[4];
+	s8 tri_reg; 	/* offset into the TRISTATE_REG_* register bank */
+	s8 tri_bit; 	/* offset into the TRISTATE_REG_* register bit */
+	s8 mux_reg;	/* offset into the PIN_MUX_CTL_* register bank */
+	s8 mux_bit;	/* offset into the PIN_MUX_CTL_* register bit */
+	s8 pupd_reg;	/* offset into the PULL_UPDOWN_REG_* register bank */
+	s8 pupd_bit;	/* offset into the PULL_UPDOWN_REG_* register bit */
+};
+
+#define PINGROUP(pg_name, f0, f1, f2, f3,			\
+		 tri_r, tri_b, mux_r, mux_b, pupd_r, pupd_b)	\
+	[TEGRA_PINGROUP_ ## pg_name] = {			\
+		.name = #pg_name,				\
+		.funcs = {					\
+			TEGRA_MUX_ ## f0,			\
+			TEGRA_MUX_ ## f1,			\
+			TEGRA_MUX_ ## f2,			\
+			TEGRA_MUX_ ## f3,			\
+		},						\
+		.tri_reg = REG_ ## tri_r,			\
+		.tri_bit = tri_b,				\
+		.mux_reg = REG_ ## mux_r,			\
+		.mux_bit = mux_b,				\
+		.pupd_reg = REG_ ## pupd_r,			\
+		.pupd_bit = pupd_b,				\
+	}
+
+static const struct tegra_pingroup_desc pingroups[TEGRA_MAX_PINGROUP] = {
+	PINGROUP(ATA,   IDE,       NAND,      GMI,       RSVD,          A, 0,  A, 24, A, 0),
+	PINGROUP(ATB,   IDE,       NAND,      GMI,       SDIO4,         A, 1,  A, 16, A, 2),
+	PINGROUP(ATC,   IDE,       NAND,      GMI,       SDIO4,         A, 2,  A, 22, A, 4),
+	PINGROUP(ATD,   IDE,       NAND,      GMI,       SDIO4,         A, 3,  A, 20, A, 6),
+	PINGROUP(ATE,   IDE,       NAND,      GMI,       RSVD,          B, 25, A, 12, A, 8),
+	PINGROUP(CDEV1, OSC,       PLLA_OUT,  PLLM_OUT1, AUDIO_SYNC,    A, 4,  C, 2,  C, 0),
+	PINGROUP(CDEV2, OSC,       AHB_CLK,   APB_CLK,   PLLP_OUT4,     A, 5,  C, 4,  C, 2),
+	PINGROUP(CRTP,  CRT,       RSVD,      RSVD,      RSVD,          D, 14, G, 20, B, 24),
+	PINGROUP(CSUS,  PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK, A, 6,  C, 6,  D, 24),
+	PINGROUP(DAP1,  DAP1,      RSVD,      GMI,       SDIO2,         A, 7,  C, 20, A, 10),
+	PINGROUP(DAP2,  DAP2,      TWC,       RSVD,      GMI,           A, 8,  C, 22, A, 12),
+	PINGROUP(DAP3,  DAP3,      RSVD,      RSVD,      RSVD,          A, 9,  C, 24, A, 14),
+	PINGROUP(DAP4,  DAP4,      RSVD,      GMI,       RSVD,          A, 10, C, 26, A, 16),
+	PINGROUP(DDC,   I2C2,      RSVD,      RSVD,      RSVD,          B, 31, C, 0,  E, 28),
+	PINGROUP(DTA,   RSVD,      SDIO2,     VI,        RSVD,          A, 11, B, 20, A, 18),
+	PINGROUP(DTB,   RSVD,      RSVD,      VI,        SPI1,          A, 12, B, 22, A, 20),
+	PINGROUP(DTC,   RSVD,      RSVD,      VI,        RSVD,          A, 13, B, 26, A, 22),
+	PINGROUP(DTD,   RSVD,      SDIO2,     VI,        RSVD,          A, 14, B, 28, A, 24),
+	PINGROUP(DTE,   RSVD,      RSVD,      VI,        SPI1,          A, 15, B, 30, A, 26),
+	PINGROUP(DTF,   I2C3,      RSVD,      VI,        RSVD,          D, 12, G, 30, A, 28),
+	PINGROUP(GMA,   UARTE,     SPI3,      GMI,       SDIO4,         A, 28, B, 0,  E, 20),
+	PINGROUP(GMB,   IDE,       NAND,      GMI,       GMI_INT,       B, 29, C, 28, E, 22),
+	PINGROUP(GMC,   UARTD,     SPI4,      GMI,       SFLASH,        A, 29, B, 2,  E, 24),
+	PINGROUP(GMD,   RSVD,      NAND,      GMI,       SFLASH,        B, 30, C, 30, E, 26),
+	PINGROUP(GME,   RSVD,      DAP5,      GMI,       SDIO4,         B, 0,  D, 0,  C, 24),
+	PINGROUP(GPU,   PWM,       UARTA,     GMI,       RSVD,          A, 16, D, 4,  B, 20),
+	PINGROUP(GPU7,  RTCK,      RSVD,      RSVD,      RSVD,          D, 11, G, 28, B, 6),
+	PINGROUP(GPV,   PCIE,      RSVD,      RSVD,      RSVD,          A, 17, D, 2,  A, 30),
+	PINGROUP(HDINT, HDMI,      RSVD,      RSVD,      RSVD,          C, 23, B, 4,  D, 22),
+	PINGROUP(I2CP,  I2C,       RSVD,      RSVD,      RSVD,          A, 18, C, 8,  B, 2),
+	PINGROUP(IRRX,  UARTA,     UARTB,     GMI,       SPI4,          A, 20, C, 18, C, 22),
+	PINGROUP(IRTX,  UARTA,     UARTB,     GMI,       SPI4,          A, 19, C, 16, C, 20),
+	PINGROUP(KBCA,  KBC,       NAND,      SDIO2,     EMC_TEST0_DLL, A, 22, C, 10, B, 8),
+	PINGROUP(KBCB,  KBC,       NAND,      SDIO2,     MIO,           A, 21, C, 12, B, 10),
+	PINGROUP(KBCC,  KBC,       NAND,      TRACE,     EMC_TEST1_DLL, B, 26, C, 14, B, 12),
+	PINGROUP(KBCD,  KBC,       NAND,      SDIO2,     MIO,           D, 10, G, 26, B, 14),
+	PINGROUP(KBCE,  KBC,       NAND,      OWR,       RSVD,          A, 26, A, 28, E, 2),
+	PINGROUP(KBCF,  KBC,       NAND,      TRACE,     MIO,           A, 27, A, 26, E, 0),
+	PINGROUP(LCSN,  DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          C, 31, E, 12, D, 20),
+	PINGROUP(LD0,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 0,  F, 0,  D, 12),
+	PINGROUP(LD1,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 1,  F, 2,  D, 12),
+	PINGROUP(LD10,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 10, F, 20, D, 12),
+	PINGROUP(LD11,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 11, F, 22, D, 12),
+	PINGROUP(LD12,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 12, F, 24, D, 12),
+	PINGROUP(LD13,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 13, F, 26, D, 12),
+	PINGROUP(LD14,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 14, F, 28, D, 12),
+	PINGROUP(LD15,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 15, F, 30, D, 12),
+	PINGROUP(LD16,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 16, G, 0,  D, 12),
+	PINGROUP(LD17,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 17, G, 2,  D, 12),
+	PINGROUP(LD2,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 2,  F, 4,  D, 12),
+	PINGROUP(LD3,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 3,  F, 6,  D, 12),
+	PINGROUP(LD4,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 4,  F, 8,  D, 12),
+	PINGROUP(LD5,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 5,  F, 10, D, 12),
+	PINGROUP(LD6,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 6,  F, 12, D, 12),
+	PINGROUP(LD7,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 7,  F, 14, D, 12),
+	PINGROUP(LD8,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 8,  F, 16, D, 12),
+	PINGROUP(LD9,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 9,  F, 18, D, 12),
+	PINGROUP(LDC,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 30, E, 14, D, 20),
+	PINGROUP(LDI,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          D, 6,  G, 16, D, 18),
+	PINGROUP(LHP0,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 18, G, 10, D, 16),
+	PINGROUP(LHP1,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 19, G, 4,  D, 14),
+	PINGROUP(LHP2,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 20, G, 6,  D, 14),
+	PINGROUP(LHS,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          D, 7,  E, 22, D, 22),
+	PINGROUP(LM0,   DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          C, 24, E, 26, D, 22),
+	PINGROUP(LM1,   DISPLAYA,  DISPLAYB,  RSVD,      CRT,           C, 25, E, 28, D, 22),
+	PINGROUP(LPP,   DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          D, 8,  G, 14, D, 18),
+	PINGROUP(LPW0,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          D, 3,  E, 0,  D, 20),
+	PINGROUP(LPW1,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          D, 4,  E, 2,  D, 20),
+	PINGROUP(LPW2,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          D, 5,  E, 4,  D, 20),
+	PINGROUP(LSC0,  DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 27, E, 18, D, 22),
+	PINGROUP(LSC1,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          C, 28, E, 20, D, 20),
+	PINGROUP(LSCK,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          C, 29, E, 16, D, 20),
+	PINGROUP(LSDA,  DISPLAYA,  DISPLAYB,  SPI3,      HDMI,          D, 1,  E, 8,  D, 20),
+	PINGROUP(LSDI,  DISPLAYA,  DISPLAYB,  SPI3,      RSVD,          D, 2,  E, 6,  D, 20),
+	PINGROUP(LSPI,  DISPLAYA,  DISPLAYB,  XIO,       HDMI,          D, 0,  E, 10, D, 22),
+	PINGROUP(LVP0,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 21, E, 30, D, 22),
+	PINGROUP(LVP1,  DISPLAYA,  DISPLAYB,  RSVD,      RSVD,          C, 22, G, 8,  D, 16),
+	PINGROUP(LVS,   DISPLAYA,  DISPLAYB,  XIO,       RSVD,          C, 26, E, 24, D, 22),
+	PINGROUP(OWC,   OWR,       RSVD,      RSVD,      RSVD,          A, 31, B, 8,  E, 30),
+	PINGROUP(PMC,   PWR_ON,    PWR_INTR,  RSVD,      RSVD,          A, 23, G, 18, N, -1),
+	PINGROUP(PTA,   I2C2,      HDMI,      GMI,       RSVD,          A, 24, G, 22, B, 4),
+	PINGROUP(RM,    I2C,       RSVD,      RSVD,      RSVD,          A, 25, A, 14, B, 0),
+	PINGROUP(SDB,   UARTA,     PWM,       SDIO3,     SPI2,          D, 15, D, 10, N, -1),
+	PINGROUP(SDC,   PWM,       TWC,       SDIO3,     SPI3,          B, 1,  D, 12, D, 28),
+	PINGROUP(SDD,   UARTA,     PWM,       SDIO3,     SPI3,          B, 2,  D, 14, D, 30),
+	PINGROUP(SDIO1, SDIO1,     RSVD,      UARTE,     UARTA,         A, 30, A, 30, E, 18),
+	PINGROUP(SLXA,  PCIE,      SPI4,      SDIO3,     SPI2,          B, 3,  B, 6,  B, 22),
+	PINGROUP(SLXC,  SPDIF,     SPI4,      SDIO3,     SPI2,          B, 5,  B, 10, B, 26),
+	PINGROUP(SLXD,  SPDIF,     SPI4,      SDIO3,     SPI2,          B, 6,  B, 12, B, 28),
+	PINGROUP(SLXK,  PCIE,      SPI4,      SDIO3,     SPI2,          B, 7,  B, 14, B, 30),
+	PINGROUP(SPDI,  SPDIF,     RSVD,      I2C,       SDIO2,         B, 8,  D, 8,  B, 16),
+	PINGROUP(SPDO,  SPDIF,     RSVD,      I2C,       SDIO2,         B, 9,  D, 6,  B, 18),
+	PINGROUP(SPIA,  SPI1,      SPI2,      SPI3,      GMI,           B, 10, D, 30, C, 4),
+	PINGROUP(SPIB,  SPI1,      SPI2,      SPI3,      GMI,           B, 11, D, 28, C, 6),
+	PINGROUP(SPIC,  SPI1,      SPI2,      SPI3,      GMI,           B, 12, D, 26, C, 8),
+	PINGROUP(SPID,  SPI2,      SPI1,      SPI2_ALT,  GMI,           B, 13, D, 24, C, 10),
+	PINGROUP(SPIE,  SPI2,      SPI1,      SPI2_ALT,  GMI,           B, 14, D, 22, C, 12),
+	PINGROUP(SPIF,  SPI3,      SPI1,      SPI2,      RSVD,          B, 15, D, 20, C, 14),
+	PINGROUP(SPIG,  SPI3,      SPI2,      SPI2_ALT,  I2C,           B, 16, D, 18, C, 16),
+	PINGROUP(SPIH,  SPI3,      SPI2,      SPI2_ALT,  I2C,           B, 17, D, 16, C, 18),
+	PINGROUP(UAA,   SPI3,      MIPI_HS,   UARTA,     ULPI,          B, 18, A, 0,  D, 0),
+	PINGROUP(UAB,   SPI2,      MIPI_HS,   UARTA,     ULPI,          B, 19, A, 2,  D, 2),
+	PINGROUP(UAC,   OWR,       RSVD,      RSVD,      RSVD,          B, 20, A, 4,  D, 4),
+	PINGROUP(UAD,   IRDA,      SPDIF,     UARTA,     SPI4,          B, 21, A, 6,  D, 6),
+	PINGROUP(UCA,   UARTC,     RSVD,      GMI,       RSVD,          B, 22, B, 16, D, 8),
+	PINGROUP(UCB,   UARTC,     PWM,       GMI,       RSVD,          B, 23, B, 18, D, 10),
+	PINGROUP(UDA,   SPI1,      RSVD,      UARTD,     ULPI,          D, 13, A, 8,  E, 16),
+	/* these pin groups only have pullup and pull down control */
+	PINGROUP(CK32,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 14),
+	PINGROUP(DDRC,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  D, 26),
+	PINGROUP(PMCA,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 4),
+	PINGROUP(PMCB,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 6),
+	PINGROUP(PMCC,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 8),
+	PINGROUP(PMCD,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 10),
+	PINGROUP(PMCE,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  E, 12),
+	PINGROUP(XM2C,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  C, 30),
+	PINGROUP(XM2D,  RSVD,      RSVD,      RSVD,      RSVD,          N, -1,  N, -1,  C, 28),
+};
+
+static char *tegra_mux_names[TEGRA_MAX_MUX] = {
+	[TEGRA_MUX_AHB_CLK] = "AHB_CLK",
+	[TEGRA_MUX_APB_CLK] = "APB_CLK",
+	[TEGRA_MUX_AUDIO_SYNC] = "AUDIO_SYNC",
+	[TEGRA_MUX_CRT] = "CRT",
+	[TEGRA_MUX_DAP1] = "DAP1",
+	[TEGRA_MUX_DAP2] = "DAP2",
+	[TEGRA_MUX_DAP3] = "DAP3",
+	[TEGRA_MUX_DAP4] = "DAP4",
+	[TEGRA_MUX_DAP5] = "DAP5",
+	[TEGRA_MUX_DISPLAYA] = "DISPLAYA",
+	[TEGRA_MUX_DISPLAYB] = "DISPLAYB",
+	[TEGRA_MUX_EMC_TEST0_DLL] = "EMC_TEST0_DLL",
+	[TEGRA_MUX_EMC_TEST1_DLL] = "EMC_TEST1_DLL",
+	[TEGRA_MUX_GMI] = "GMI",
+	[TEGRA_MUX_GMI_INT] = "GMI_INT",
+	[TEGRA_MUX_HDMI] = "HDMI",
+	[TEGRA_MUX_I2C] = "I2C",
+	[TEGRA_MUX_I2C2] = "I2C2",
+	[TEGRA_MUX_I2C3] = "I2C3",
+	[TEGRA_MUX_IDE] = "IDE",
+	[TEGRA_MUX_IRDA] = "IRDA",
+	[TEGRA_MUX_KBC] = "KBC",
+	[TEGRA_MUX_MIO] = "MIO",
+	[TEGRA_MUX_MIPI_HS] = "MIPI_HS",
+	[TEGRA_MUX_NAND] = "NAND",
+	[TEGRA_MUX_OSC] = "OSC",
+	[TEGRA_MUX_OWR] = "OWR",
+	[TEGRA_MUX_PCIE] = "PCIE",
+	[TEGRA_MUX_PLLA_OUT] = "PLLA_OUT",
+	[TEGRA_MUX_PLLC_OUT1] = "PLLC_OUT1",
+	[TEGRA_MUX_PLLM_OUT1] = "PLLM_OUT1",
+	[TEGRA_MUX_PLLP_OUT2] = "PLLP_OUT2",
+	[TEGRA_MUX_PLLP_OUT3] = "PLLP_OUT3",
+	[TEGRA_MUX_PLLP_OUT4] = "PLLP_OUT4",
+	[TEGRA_MUX_PWM] = "PWM",
+	[TEGRA_MUX_PWR_INTR] = "PWR_INTR",
+	[TEGRA_MUX_PWR_ON] = "PWR_ON",
+	[TEGRA_MUX_RTCK] = "RTCK",
+	[TEGRA_MUX_SDIO1] = "SDIO1",
+	[TEGRA_MUX_SDIO2] = "SDIO2",
+	[TEGRA_MUX_SDIO3] = "SDIO3",
+	[TEGRA_MUX_SDIO4] = "SDIO4",
+	[TEGRA_MUX_SFLASH] = "SFLASH",
+	[TEGRA_MUX_SPDIF] = "SPDIF",
+	[TEGRA_MUX_SPI1] = "SPI1",
+	[TEGRA_MUX_SPI2] = "SPI2",
+	[TEGRA_MUX_SPI2_ALT] = "SPI2_ALT",
+	[TEGRA_MUX_SPI3] = "SPI3",
+	[TEGRA_MUX_SPI4] = "SPI4",
+	[TEGRA_MUX_TRACE] = "TRACE",
+	[TEGRA_MUX_TWC] = "TWC",
+	[TEGRA_MUX_UARTA] = "UARTA",
+	[TEGRA_MUX_UARTB] = "UARTB",
+	[TEGRA_MUX_UARTC] = "UARTC",
+	[TEGRA_MUX_UARTD] = "UARTD",
+	[TEGRA_MUX_UARTE] = "UARTE",
+	[TEGRA_MUX_ULPI] = "ULPI",
+	[TEGRA_MUX_VI] = "VI",
+	[TEGRA_MUX_VI_SENSOR_CLK] = "VI_SENSOR_CLK",
+	[TEGRA_MUX_XIO] = "XIO",
+};
+
+struct tegra_drive_pingroup_desc {
+	const char *name;
+	s16 reg;
+};
+
+#define DRIVE_PINGROUP(pg_name, r)				\
+	[TEGRA_DRIVE_PINGROUP_ ## pg_name] = {			\
+		.name = #pg_name,				\
+		.reg = r					\
+	}
+
+static const struct tegra_drive_pingroup_desc drive_pingroups[TEGRA_MAX_PINGROUP] = {
+	DRIVE_PINGROUP(AO1,		0x868),
+	DRIVE_PINGROUP(AO2,		0x86c),
+	DRIVE_PINGROUP(AT1,		0x870),
+	DRIVE_PINGROUP(AT2,		0x874),
+	DRIVE_PINGROUP(CDEV1,		0x878),
+	DRIVE_PINGROUP(CDEV2,		0x87c),
+	DRIVE_PINGROUP(CSUS,		0x880),
+	DRIVE_PINGROUP(DAP1,		0x884),
+	DRIVE_PINGROUP(DAP2,		0x888),
+	DRIVE_PINGROUP(DAP3,		0x88c),
+	DRIVE_PINGROUP(DAP4,		0x890),
+	DRIVE_PINGROUP(DBG,		0x894),
+	DRIVE_PINGROUP(LCD1,		0x898),
+	DRIVE_PINGROUP(LCD2,		0x89c),
+	DRIVE_PINGROUP(SDMMC2,	0x8a0),
+	DRIVE_PINGROUP(SDMMC3,	0x8a4),
+	DRIVE_PINGROUP(SPI,		0x8a8),
+	DRIVE_PINGROUP(UAA,		0x8ac),
+	DRIVE_PINGROUP(UAB,		0x8b0),
+	DRIVE_PINGROUP(UART2,		0x8b4),
+	DRIVE_PINGROUP(UART3,		0x8b8),
+	DRIVE_PINGROUP(VI1,		0x8bc),
+	DRIVE_PINGROUP(VI2,		0x8c0),
+	DRIVE_PINGROUP(XM2A,		0x8c4),
+	DRIVE_PINGROUP(XM2C,		0x8c8),
+	DRIVE_PINGROUP(XM2D,		0x8cc),
+	DRIVE_PINGROUP(XM2CLK,	0x8d0),
+	DRIVE_PINGROUP(MEMCOMP,	0x8d4),
+};
+
+static const char *tegra_drive_names[TEGRA_MAX_DRIVE] = {
+	[TEGRA_DRIVE_DIV_8] = "DIV_8",
+	[TEGRA_DRIVE_DIV_4] = "DIV_4",
+	[TEGRA_DRIVE_DIV_2] = "DIV_2",
+	[TEGRA_DRIVE_DIV_1] = "DIV_1",
+};
+
+static const char *tegra_slew_names[TEGRA_MAX_SLEW] = {
+	[TEGRA_SLEW_FASTEST] = "FASTEST",
+	[TEGRA_SLEW_FAST] = "FAST",
+	[TEGRA_SLEW_SLOW] = "SLOW",
+	[TEGRA_SLEW_SLOWEST] = "SLOWEST",
+};
+
+static DEFINE_SPINLOCK(mux_lock);
+
+static const char *pingroup_name(enum tegra_pingroup pg)
+{
+	if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+		return "<UNKNOWN>";
+
+	return pingroups[pg].name;
+}
+
+static const char *func_name(enum tegra_mux_func func)
+{
+	if (func == TEGRA_MUX_RSVD1)
+		return "RSVD1";
+
+	if (func == TEGRA_MUX_RSVD2)
+		return "RSVD2";
+
+	if (func == TEGRA_MUX_RSVD3)
+		return "RSVD3";
+
+	if (func == TEGRA_MUX_RSVD4)
+		return "RSVD4";
+
+	if (func == TEGRA_MUX_NONE)
+		return "NONE";
+
+	if (func < 0 || func >=  TEGRA_MAX_MUX)
+		return "<UNKNOWN>";
+
+	return tegra_mux_names[func];
+}
+
+
+static const char *tri_name(unsigned long val)
+{
+	return val ? "TRISTATE" : "NORMAL";
+}
+
+static const char *pupd_name(unsigned long val)
+{
+	switch (val) {
+	case 0:
+		return "NORMAL";
+
+	case 1:
+		return "PULL_DOWN";
+
+	case 2:
+		return "PULL_UP";
+
+	default:
+		return "RSVD";
+	}
+}
+
+
+static inline unsigned long pg_readl(unsigned long offset)
+{
+	return readl(IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
+}
+
+static inline void pg_writel(unsigned long value, unsigned long offset)
+{
+	writel(value, IO_TO_VIRT(TEGRA_APB_MISC_BASE + offset));
+}
+
+int tegra_pinmux_set_func(enum tegra_pingroup pg, enum tegra_mux_func func)
+{
+	int mux = -1;
+	int i;
+	unsigned long reg;
+	unsigned long flags;
+
+	if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+		return -ERANGE;
+
+	if (pingroups[pg].mux_reg == REG_N)
+		return -EINVAL;
+
+	if (func < 0)
+		return -ERANGE;
+
+	if (func & TEGRA_MUX_RSVD) {
+		mux = func & 0x3;
+	} else {
+		for (i = 0; i < 4; i++) {
+			if (pingroups[pg].funcs[i] == func) {
+				mux = i;
+				break;
+			}
+		}
+	}
+
+	if (mux < 0)
+		return -EINVAL;
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg));
+	reg &= ~(0x3 << pingroups[pg].mux_bit);
+	reg |= mux << pingroups[pg].mux_bit;
+	pg_writel(reg, TEGRA_PP_MUX_CTL(pingroups[pg].mux_reg));
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+int tegra_pinmux_set_tristate(enum tegra_pingroup pg,
+	enum tegra_tristate tristate)
+{
+	unsigned long reg;
+	unsigned long flags;
+
+	if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+		return -ERANGE;
+
+	if (pingroups[pg].tri_reg == REG_N)
+		return -EINVAL;
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(TEGRA_TRI_STATE(pingroups[pg].tri_reg));
+	reg &= ~(0x1 << pingroups[pg].tri_bit);
+	if (tristate)
+		reg |= 1 << pingroups[pg].tri_bit;
+	pg_writel(reg, TEGRA_TRI_STATE(pingroups[pg].tri_reg));
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+int tegra_pinmux_set_pullupdown(enum tegra_pingroup pg,
+	enum tegra_pullupdown pupd)
+{
+	unsigned long reg;
+	unsigned long flags;
+
+	if (pg < 0 || pg >=  TEGRA_MAX_PINGROUP)
+		return -ERANGE;
+
+	if (pingroups[pg].pupd_reg == REG_N)
+		return -EINVAL;
+
+	if (pupd != TEGRA_PUPD_NORMAL &&
+	    pupd != TEGRA_PUPD_PULL_DOWN &&
+	    pupd != TEGRA_PUPD_PULL_UP)
+		return -EINVAL;
+
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(TEGRA_PP_PU_PD(pingroups[pg].pupd_reg));
+	reg &= ~(0x3 << pingroups[pg].pupd_bit);
+	reg |= pupd << pingroups[pg].pupd_bit;
+	pg_writel(reg, TEGRA_PP_PU_PD(pingroups[pg].pupd_reg));
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+void tegra_pinmux_config_pingroup(enum tegra_pingroup pingroup,
+				 enum tegra_mux_func func,
+				 enum tegra_pullupdown pupd,
+				 enum tegra_tristate tristate)
+{
+	int err;
+
+	if (pingroups[pingroup].mux_reg != REG_N) {
+		err = tegra_pinmux_set_func(pingroup, func);
+		if (err < 0)
+			pr_err("pinmux: can't set pingroup %s func to %s: %d\n",
+			       pingroup_name(pingroup), func_name(func), err);
+	}
+
+	if (pingroups[pingroup].pupd_reg != REG_N) {
+		err = tegra_pinmux_set_pullupdown(pingroup, pupd);
+		if (err < 0)
+			pr_err("pinmux: can't set pingroup %s pullupdown to %s: %d\n",
+			       pingroup_name(pingroup), pupd_name(pupd), err);
+	}
+
+	if (pingroups[pingroup].tri_reg != REG_N) {
+		err = tegra_pinmux_set_tristate(pingroup, tristate);
+		if (err < 0)
+			pr_err("pinmux: can't set pingroup %s tristate to %s: %d\n",
+			       pingroup_name(pingroup), tri_name(func), err);
+	}
+}
+
+
+
+void tegra_pinmux_config_table(struct tegra_pingroup_config *config, int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		tegra_pinmux_config_pingroup(config[i].pingroup,
+					     config[i].func,
+					     config[i].pupd,
+					     config[i].tristate);
+}
+
+static const char *drive_pinmux_name(enum tegra_drive_pingroup pg)
+{
+	if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+		return "<UNKNOWN>";
+
+	return drive_pingroups[pg].name;
+}
+
+static const char *enable_name(unsigned long val)
+{
+	return val ? "ENABLE" : "DISABLE";
+}
+
+static const char *drive_name(unsigned long val)
+{
+	if (val >= TEGRA_MAX_DRIVE)
+		return "<UNKNOWN>";
+
+	return tegra_drive_names[val];
+}
+
+static const char *slew_name(unsigned long val)
+{
+	if (val >= TEGRA_MAX_SLEW)
+		return "<UNKNOWN>";
+
+	return tegra_slew_names[val];
+}
+
+static int tegra_drive_pinmux_set_hsm(enum tegra_drive_pingroup pg,
+	enum tegra_hsm hsm)
+{
+	unsigned long flags;
+	u32 reg;
+	if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+		return -ERANGE;
+
+	if (hsm != TEGRA_HSM_ENABLE && hsm != TEGRA_HSM_DISABLE)
+		return -EINVAL;
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(drive_pingroups[pg].reg);
+	if (hsm == TEGRA_HSM_ENABLE)
+		reg |= (1 << 2);
+	else
+		reg &= ~(1 << 2);
+	pg_writel(reg, drive_pingroups[pg].reg);
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+static int tegra_drive_pinmux_set_schmitt(enum tegra_drive_pingroup pg,
+	enum tegra_schmitt schmitt)
+{
+	unsigned long flags;
+	u32 reg;
+	if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+		return -ERANGE;
+
+	if (schmitt != TEGRA_SCHMITT_ENABLE && schmitt != TEGRA_SCHMITT_DISABLE)
+		return -EINVAL;
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(drive_pingroups[pg].reg);
+	if (schmitt == TEGRA_SCHMITT_ENABLE)
+		reg |= (1 << 3);
+	else
+		reg &= ~(1 << 3);
+	pg_writel(reg, drive_pingroups[pg].reg);
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+static int tegra_drive_pinmux_set_drive(enum tegra_drive_pingroup pg,
+	enum tegra_drive drive)
+{
+	unsigned long flags;
+	u32 reg;
+	if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+		return -ERANGE;
+
+	if (drive < 0 || drive >= TEGRA_MAX_DRIVE)
+		return -EINVAL;
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(drive_pingroups[pg].reg);
+	reg &= ~(0x3 << 4);
+	reg |= drive << 4;
+	pg_writel(reg, drive_pingroups[pg].reg);
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+static int tegra_drive_pinmux_set_pull_down(enum tegra_drive_pingroup pg,
+	enum tegra_pull_strength pull_down)
+{
+	unsigned long flags;
+	u32 reg;
+	if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+		return -ERANGE;
+
+	if (pull_down < 0 || pull_down >= TEGRA_MAX_PULL)
+		return -EINVAL;
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(drive_pingroups[pg].reg);
+	reg &= ~(0x1f << 12);
+	reg |= pull_down << 12;
+	pg_writel(reg, drive_pingroups[pg].reg);
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+static int tegra_drive_pinmux_set_pull_up(enum tegra_drive_pingroup pg,
+	enum tegra_pull_strength pull_up)
+{
+	unsigned long flags;
+	u32 reg;
+	if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+		return -ERANGE;
+
+	if (pull_up < 0 || pull_up >= TEGRA_MAX_PULL)
+		return -EINVAL;
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(drive_pingroups[pg].reg);
+	reg &= ~(0x1f << 12);
+	reg |= pull_up << 12;
+	pg_writel(reg, drive_pingroups[pg].reg);
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+static int tegra_drive_pinmux_set_slew_rising(enum tegra_drive_pingroup pg,
+	enum tegra_slew slew_rising)
+{
+	unsigned long flags;
+	u32 reg;
+	if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+		return -ERANGE;
+
+	if (slew_rising < 0 || slew_rising >= TEGRA_MAX_SLEW)
+		return -EINVAL;
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(drive_pingroups[pg].reg);
+	reg &= ~(0x3 << 28);
+	reg |= slew_rising << 28;
+	pg_writel(reg, drive_pingroups[pg].reg);
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+static int tegra_drive_pinmux_set_slew_falling(enum tegra_drive_pingroup pg,
+	enum tegra_slew slew_falling)
+{
+	unsigned long flags;
+	u32 reg;
+	if (pg < 0 || pg >=  TEGRA_MAX_DRIVE_PINGROUP)
+		return -ERANGE;
+
+	if (slew_falling < 0 || slew_falling >= TEGRA_MAX_SLEW)
+		return -EINVAL;
+
+	spin_lock_irqsave(&mux_lock, flags);
+
+	reg = pg_readl(drive_pingroups[pg].reg);
+	reg &= ~(0x3 << 30);
+	reg |= slew_falling << 30;
+	pg_writel(reg, drive_pingroups[pg].reg);
+
+	spin_unlock_irqrestore(&mux_lock, flags);
+
+	return 0;
+}
+
+static void tegra_drive_pinmux_config_pingroup(enum tegra_drive_pingroup pingroup,
+					  enum tegra_hsm hsm,
+					  enum tegra_schmitt schmitt,
+					  enum tegra_drive drive,
+					  enum tegra_pull_strength pull_down,
+					  enum tegra_pull_strength pull_up,
+					  enum tegra_slew slew_rising,
+					  enum tegra_slew slew_falling)
+{
+	int err;
+
+	err = tegra_drive_pinmux_set_hsm(pingroup, hsm);
+	if (err < 0)
+		pr_err("pinmux: can't set pingroup %s hsm to %s: %d\n",
+			drive_pinmux_name(pingroup),
+			enable_name(hsm), err);
+
+	err = tegra_drive_pinmux_set_schmitt(pingroup, schmitt);
+	if (err < 0)
+		pr_err("pinmux: can't set pingroup %s schmitt to %s: %d\n",
+			drive_pinmux_name(pingroup),
+			enable_name(schmitt), err);
+
+	err = tegra_drive_pinmux_set_drive(pingroup, drive);
+	if (err < 0)
+		pr_err("pinmux: can't set pingroup %s drive to %s: %d\n",
+			drive_pinmux_name(pingroup),
+			drive_name(drive), err);
+
+	err = tegra_drive_pinmux_set_pull_down(pingroup, pull_down);
+	if (err < 0)
+		pr_err("pinmux: can't set pingroup %s pull down to %d: %d\n",
+			drive_pinmux_name(pingroup),
+			pull_down, err);
+
+	err = tegra_drive_pinmux_set_pull_up(pingroup, pull_up);
+	if (err < 0)
+		pr_err("pinmux: can't set pingroup %s pull up to %d: %d\n",
+			drive_pinmux_name(pingroup),
+			pull_up, err);
+
+	err = tegra_drive_pinmux_set_slew_rising(pingroup, slew_rising);
+	if (err < 0)
+		pr_err("pinmux: can't set pingroup %s rising slew to %s: %d\n",
+			drive_pinmux_name(pingroup),
+			slew_name(slew_rising), err);
+
+	err = tegra_drive_pinmux_set_slew_falling(pingroup, slew_falling);
+	if (err < 0)
+		pr_err("pinmux: can't set pingroup %s falling slew to %s: %d\n",
+			drive_pinmux_name(pingroup),
+			slew_name(slew_falling), err);
+}
+
+void tegra_drive_pinmux_config_table(struct tegra_drive_pingroup_config *config,
+	int len)
+{
+	int i;
+
+	for (i = 0; i < len; i++)
+		tegra_drive_pinmux_config_pingroup(config[i].pingroup,
+						     config[i].hsm,
+						     config[i].schmitt,
+						     config[i].drive,
+						     config[i].pull_down,
+						     config[i].pull_up,
+						     config[i].slew_rising,
+						     config[i].slew_falling);
+}
+
+
+#ifdef	CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static void dbg_pad_field(struct seq_file *s, int len)
+{
+	seq_putc(s, ',');
+
+	while (len-- > -1)
+		seq_putc(s, ' ');
+}
+
+static int dbg_pinmux_show(struct seq_file *s, void *unused)
+{
+	int i;
+	int len;
+
+	for (i = 0; i < TEGRA_MAX_PINGROUP; i++) {
+		unsigned long tri;
+		unsigned long mux;
+		unsigned long pupd;
+
+		seq_printf(s, "\t{TEGRA_PINGROUP_%s", pingroups[i].name);
+		len = strlen(pingroups[i].name);
+		dbg_pad_field(s, 5 - len);
+
+		if (pingroups[i].mux_reg == REG_N) {
+			seq_printf(s, "TEGRA_MUX_NONE");
+			len = strlen("NONE");
+		} else {
+			mux = (pg_readl(TEGRA_PP_MUX_CTL(pingroups[i].mux_reg)) >>
+			       pingroups[i].mux_bit) & 0x3;
+			if (pingroups[i].funcs[mux] == TEGRA_MUX_RSVD) {
+				seq_printf(s, "TEGRA_MUX_RSVD%1lu", mux+1);
+				len = 5;
+			} else {
+				seq_printf(s, "TEGRA_MUX_%s",
+					   tegra_mux_names[pingroups[i].funcs[mux]]);
+				len = strlen(tegra_mux_names[pingroups[i].funcs[mux]]);
+			}
+		}
+		dbg_pad_field(s, 13-len);
+
+		if (pingroups[i].mux_reg == REG_N) {
+			seq_printf(s, "TEGRA_PUPD_NORMAL");
+			len = strlen("NORMAL");
+		} else {
+			pupd = (pg_readl(TEGRA_PP_PU_PD(pingroups[i].pupd_reg)) >>
+				pingroups[i].pupd_bit) & 0x3;
+			seq_printf(s, "TEGRA_PUPD_%s", pupd_name(pupd));
+			len = strlen(pupd_name(pupd));
+		}
+		dbg_pad_field(s, 9 - len);
+
+		if (pingroups[i].tri_reg == REG_N) {
+			seq_printf(s, "TEGRA_TRI_NORMAL");
+		} else {
+			tri = (pg_readl(TEGRA_TRI_STATE(pingroups[i].tri_reg)) >>
+			       pingroups[i].tri_bit) & 0x1;
+
+			seq_printf(s, "TEGRA_TRI_%s", tri_name(tri));
+		}
+		seq_printf(s, "},\n");
+	}
+	return 0;
+}
+
+static int dbg_pinmux_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, dbg_pinmux_show, &inode->i_private);
+}
+
+static const struct file_operations debug_fops = {
+	.open		= dbg_pinmux_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int dbg_drive_pinmux_show(struct seq_file *s, void *unused)
+{
+	int i;
+	int len;
+
+	for (i = 0; i < TEGRA_MAX_DRIVE_PINGROUP; i++) {
+		u32 reg;
+
+		seq_printf(s, "\t{TEGRA_DRIVE_PINGROUP_%s",
+			drive_pingroups[i].name);
+		len = strlen(drive_pingroups[i].name);
+		dbg_pad_field(s, 7 - len);
+
+
+		reg = pg_readl(drive_pingroups[i].reg);
+		if (HSM_EN(reg)) {
+			seq_printf(s, "TEGRA_HSM_ENABLE");
+			len = 16;
+		} else {
+			seq_printf(s, "TEGRA_HSM_DISABLE");
+			len = 17;
+		}
+		dbg_pad_field(s, 17 - len);
+
+		if (SCHMT_EN(reg)) {
+			seq_printf(s, "TEGRA_SCHMITT_ENABLE");
+			len = 21;
+		} else {
+			seq_printf(s, "TEGRA_SCHMITT_DISABLE");
+			len = 22;
+		}
+		dbg_pad_field(s, 22 - len);
+
+		seq_printf(s, "TEGRA_DRIVE_%s", drive_name(LPMD(reg)));
+		len = strlen(drive_name(LPMD(reg)));
+		dbg_pad_field(s, 5 - len);
+
+		seq_printf(s, "TEGRA_PULL_%d", DRVDN(reg));
+		len = DRVDN(reg) < 10 ? 1 : 2;
+		dbg_pad_field(s, 2 - len);
+
+		seq_printf(s, "TEGRA_PULL_%d", DRVUP(reg));
+		len = DRVUP(reg) < 10 ? 1 : 2;
+		dbg_pad_field(s, 2 - len);
+
+		seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWR(reg)));
+		len = strlen(slew_name(SLWR(reg)));
+		dbg_pad_field(s, 7 - len);
+
+		seq_printf(s, "TEGRA_SLEW_%s", slew_name(SLWF(reg)));
+
+		seq_printf(s, "},\n");
+	}
+	return 0;
+}
+
+static int dbg_drive_pinmux_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, dbg_drive_pinmux_show, &inode->i_private);
+}
+
+static const struct file_operations debug_drive_fops = {
+	.open		= dbg_drive_pinmux_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int __init tegra_pinmux_debuginit(void)
+{
+	(void) debugfs_create_file("tegra_pinmux", S_IRUGO,
+					NULL, NULL, &debug_fops);
+	(void) debugfs_create_file("tegra_pinmux_drive", S_IRUGO,
+					NULL, NULL, &debug_drive_fops);
+	return 0;
+}
+late_initcall(tegra_pinmux_debuginit);
+#endif
-- 
1.6.5.6



From konkers at android.com  Mon Jun 14 17:10:27 2010
From: konkers at android.com (Erik Gilling)
Date: Mon, 14 Jun 2010 14:10:27 -0700
Subject: [PATCH v3 11/11] [ARM] tegra: add panel support to harmony board files
In-Reply-To: <1276549827-2688-11-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
	<1276549827-2688-3-git-send-email-konkers@android.com>
	<1276549827-2688-4-git-send-email-konkers@android.com>
	<1276549827-2688-5-git-send-email-konkers@android.com>
	<1276549827-2688-6-git-send-email-konkers@android.com>
	<1276549827-2688-7-git-send-email-konkers@android.com>
	<1276549827-2688-8-git-send-email-konkers@android.com>
	<1276549827-2688-9-git-send-email-konkers@android.com>
	<1276549827-2688-10-git-send-email-konkers@android.com>
	<1276549827-2688-11-git-send-email-konkers@android.com>
Message-ID: <1276549827-2688-12-git-send-email-konkers@android.com>

Signed-off-by: Erik Gilling <konkers at android.com>
---
 arch/arm/mach-tegra/Makefile              |    1 +
 arch/arm/mach-tegra/board-harmony-panel.c |   65 +++++++++++++++++++++++++++++
 arch/arm/mach-tegra/board-harmony.c       |    1 +
 arch/arm/mach-tegra/board-harmony.h       |    1 +
 4 files changed, 68 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/board-harmony-panel.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 51e9370..c832aa8 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 
 obj-${CONFIG_MACH_HARMONY}              += board-harmony.o
 obj-${CONFIG_MACH_HARMONY}              += board-harmony-pinmux.o
+obj-${CONFIG_MACH_HARMONY}              += board-harmony-panel.o
diff --git a/arch/arm/mach-tegra/board-harmony-panel.c b/arch/arm/mach-tegra/board-harmony-panel.c
new file mode 100644
index 0000000..79b83f1
--- /dev/null
+++ b/arch/arm/mach-tegra/board-harmony-panel.c
@@ -0,0 +1,65 @@
+/*
+ * arch/arm/mach-tegra/board-harmony-panel.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/resource.h>
+#include <linux/platform_device.h>
+#include <asm/mach-types.h>
+#include <mach/irqs.h>
+#include <mach/iomap.h>
+#include <mach/tegra_fb.h>
+
+/* Framebuffer */
+static struct resource fb_resource[] = {
+	[0] = {
+		.start  = INT_DISPLAY_GENERAL,
+		.end    = INT_DISPLAY_GENERAL,
+		.flags  = IORESOURCE_IRQ,
+	},
+	[1] = {
+		.start	= TEGRA_DISPLAY_BASE,
+		.end	= TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[2] = {
+		.start	= 0x1c012000,
+		.end	= 0x1c012000 + 0x500000 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+};
+
+static struct tegra_fb_lcd_data tegra_fb_lcd_platform_data = {
+	.lcd_xres	= 1024,
+	.lcd_yres	= 600,
+	.fb_xres	= 1024,
+	.fb_yres	= 600,
+	.bits_per_pixel	= 16,
+};
+
+static struct platform_device tegra_fb_device = {
+	.name		= "tegrafb",
+	.id		= 0,
+	.resource	= fb_resource,
+	.num_resources	= ARRAY_SIZE(fb_resource),
+	.dev = {
+		.platform_data = &tegra_fb_lcd_platform_data,
+	},
+};
+
+void __init harmony_panel_init(void)
+{
+	platform_device_register(&tegra_fb_device);
+}
+
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 05e78dd..5887311 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -111,6 +111,7 @@ static void __init tegra_harmony_init(void)
 	tegra_clk_init_from_table(harmony_clk_init_table);
 
 	harmony_pinmux_init();
+	harmony_panel_init();
 
 	platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
 }
diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h
index 09ca775..94053c9 100644
--- a/arch/arm/mach-tegra/board-harmony.h
+++ b/arch/arm/mach-tegra/board-harmony.h
@@ -18,5 +18,6 @@
 #define _MACH_TEGRA_BOARD_HARMONY_H
 
 void harmony_pinmux_init(void);
+void harmony_panel_init(void);
 
 #endif
-- 
1.6.5.6



From konkers at android.com  Mon Jun 14 17:10:21 2010
From: konkers at android.com (Erik Gilling)
Date: Mon, 14 Jun 2010 14:10:21 -0700
Subject: [PATCH v3 05/11] [ARM] tegra: Add timer support
In-Reply-To: <1276549827-2688-5-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
	<1276549827-2688-3-git-send-email-konkers@android.com>
	<1276549827-2688-4-git-send-email-konkers@android.com>
	<1276549827-2688-5-git-send-email-konkers@android.com>
Message-ID: <1276549827-2688-6-git-send-email-konkers@android.com>

From: Colin Cross <ccross at android.com>

v2: fixes from Russell King:
	- include linux/io.h instead of asm/io.h
    fixes from Gary King:
	- remove extra (and incorrect) irq definitions
	- use timer 3 instead of timer 1 for compatibility with other drivers
	- fix typo that disabled oneshot mode
v3:
	- Implement sched_clock
	- Fix checkpatch issues
    fixes from Gary King:
    	- Fix incorrect cycles calculation
	- Fix min_delta_ns assignment
    fixes from Linus Walleij:
	- use calc_mult_shift() instead of hard coding values

Signed-off-by: Colin Cross <ccross at android.com>
---
 arch/arm/mach-tegra/Makefile |    1 +
 arch/arm/mach-tegra/timer.c  |  187 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 188 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/timer.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index f339559..01f47fd 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -2,6 +2,7 @@ obj-y                                   += common.o
 obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
+obj-y                                   += timer.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
new file mode 100644
index 0000000..2f42021
--- /dev/null
+++ b/arch/arm/mach-tegra/timer.c
@@ -0,0 +1,187 @@
+/*
+ * arch/arch/mach-tegra/timer.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/cnt32_to_63.h>
+
+#include <asm/mach/time.h>
+#include <asm/mach/time.h>
+#include <asm/localtimer.h>
+
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+
+#include "board.h"
+#include "clock.h"
+
+#define TIMERUS_CNTR_1US 0x10
+#define TIMERUS_USEC_CFG 0x14
+#define TIMERUS_CNTR_FREEZE 0x4c
+
+#define TIMER1_BASE 0x0
+#define TIMER2_BASE 0x8
+#define TIMER3_BASE 0x50
+#define TIMER4_BASE 0x58
+
+#define TIMER_PTV 0x0
+#define TIMER_PCR 0x4
+
+struct tegra_timer;
+
+static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
+
+#define timer_writel(value, reg) \
+	__raw_writel(value, (u32)timer_reg_base + (reg))
+#define timer_readl(reg) \
+	__raw_readl((u32)timer_reg_base + (reg))
+
+static int tegra_timer_set_next_event(unsigned long cycles,
+					 struct clock_event_device *evt)
+{
+	u32 reg;
+
+	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
+	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
+
+	return 0;
+}
+
+static void tegra_timer_set_mode(enum clock_event_mode mode,
+				    struct clock_event_device *evt)
+{
+	u32 reg;
+
+	timer_writel(0, TIMER3_BASE + TIMER_PTV);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		reg = 0xC0000000 | ((1000000/HZ)-1);
+		timer_writel(reg, TIMER3_BASE + TIMER_PTV);
+		break;
+	case CLOCK_EVT_MODE_ONESHOT:
+		break;
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	case CLOCK_EVT_MODE_RESUME:
+		break;
+	}
+}
+
+static cycle_t tegra_clocksource_read(struct clocksource *cs)
+{
+	return cnt32_to_63(timer_readl(TIMERUS_CNTR_1US));
+}
+
+static struct clock_event_device tegra_clockevent = {
+	.name		= "timer0",
+	.rating		= 300,
+	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+	.set_next_event	= tegra_timer_set_next_event,
+	.set_mode	= tegra_timer_set_mode,
+};
+
+static struct clocksource tegra_clocksource = {
+	.name	= "timer_us",
+	.rating	= 300,
+	.read	= tegra_clocksource_read,
+	.mask	= 0x7FFFFFFFFFFFFFFFULL,
+	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+unsigned long long sched_clock(void)
+{
+	return clocksource_cyc2ns(tegra_clocksource.read(&tegra_clocksource),
+		tegra_clocksource.mult, tegra_clocksource.shift);
+}
+
+static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
+	evt->event_handler(evt);
+	return IRQ_HANDLED;
+}
+
+static struct irqaction tegra_timer_irq = {
+	.name		= "timer0",
+	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
+	.handler	= tegra_timer_interrupt,
+	.dev_id		= &tegra_clockevent,
+	.irq		= INT_TMR3,
+};
+
+static void __init tegra_init_timer(void)
+{
+	unsigned long rate = clk_measure_input_freq();
+	int ret;
+
+#ifdef CONFIG_HAVE_ARM_TWD
+	twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
+#endif
+
+	switch (rate) {
+	case 12000000:
+		timer_writel(0x000b, TIMERUS_USEC_CFG);
+		break;
+	case 13000000:
+		timer_writel(0x000c, TIMERUS_USEC_CFG);
+		break;
+	case 19200000:
+		timer_writel(0x045f, TIMERUS_USEC_CFG);
+		break;
+	case 26000000:
+		timer_writel(0x0019, TIMERUS_USEC_CFG);
+		break;
+	default:
+		WARN(1, "Unknown clock rate");
+	}
+
+	if (clocksource_register_hz(&tegra_clocksource, 1000000)) {
+		printk(KERN_ERR "Failed to register clocksource\n");
+		BUG();
+	}
+
+	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
+	if (ret) {
+		printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
+		BUG();
+	}
+
+	clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
+	tegra_clockevent.max_delta_ns =
+		clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
+	tegra_clockevent.min_delta_ns =
+		clockevent_delta2ns(0x1, &tegra_clockevent);
+	tegra_clockevent.cpumask = cpu_all_mask;
+	tegra_clockevent.irq = tegra_timer_irq.irq;
+	clockevents_register_device(&tegra_clockevent);
+
+	return;
+}
+
+struct sys_timer tegra_timer = {
+	.init = tegra_init_timer,
+};
-- 
1.6.5.6



From konkers at android.com  Mon Jun 14 17:10:18 2010
From: konkers at android.com (Erik Gilling)
Date: Mon, 14 Jun 2010 14:10:18 -0700
Subject: [PATCH v3 02/11] [ARM] tegra: Add IRQ support
In-Reply-To: <1276549827-2688-2-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
Message-ID: <1276549827-2688-3-git-send-email-konkers@android.com>

v2: fixes from Russell King
	- include linux/io.h instead of asm/io.h and mach/io.h

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Erik Gilling <konkers at android.com>
---
 arch/arm/mach-tegra/Makefile            |    1 +
 arch/arm/mach-tegra/include/mach/irqs.h |  173 +++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/irq.c               |   34 ++++++
 3 files changed, 208 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/irqs.h
 create mode 100644 arch/arm/mach-tegra/irq.c

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 81f003d..a0d2c5b 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,2 +1,3 @@
 obj-y                                   += common.o
 obj-y                                   += io.o
+obj-y                                   += irq.o
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
new file mode 100644
index 0000000..20f640e
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -0,0 +1,173 @@
+/*
+ * arch/arm/mach-tegra/include/mach/irqs.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_IRQS_H
+#define __MACH_TEGRA_IRQS_H
+
+#define INT_GIC_BASE			0
+
+#define IRQ_LOCALTIMER                  29
+
+/* Primary Interrupt Controller */
+#define INT_PRI_BASE			(INT_GIC_BASE + 32)
+#define INT_TMR1			(INT_PRI_BASE + 0)
+#define INT_TMR2			(INT_PRI_BASE + 1)
+#define INT_RTC				(INT_PRI_BASE + 2)
+#define INT_I2S2			(INT_PRI_BASE + 3)
+#define INT_SHR_SEM_INBOX_IBF		(INT_PRI_BASE + 4)
+#define INT_SHR_SEM_INBOX_IBE		(INT_PRI_BASE + 5)
+#define INT_SHR_SEM_OUTBOX_IBF		(INT_PRI_BASE + 6)
+#define INT_SHR_SEM_OUTBOX_IBE		(INT_PRI_BASE + 7)
+#define INT_VDE_UCQ_ERROR		(INT_PRI_BASE + 8)
+#define INT_VDE_SYNC_TOKEN		(INT_PRI_BASE + 9)
+#define INT_VDE_BSE_V			(INT_PRI_BASE + 10)
+#define INT_VDE_BSE_A			(INT_PRI_BASE + 11)
+#define INT_VDE_SXE			(INT_PRI_BASE + 12)
+#define INT_I2S1			(INT_PRI_BASE + 13)
+#define INT_SDMMC1			(INT_PRI_BASE + 14)
+#define INT_SDMMC2			(INT_PRI_BASE + 15)
+#define INT_XIO				(INT_PRI_BASE + 16)
+#define INT_VDE				(INT_PRI_BASE + 17)
+#define INT_AVP_UCQ			(INT_PRI_BASE + 18)
+#define INT_SDMMC3			(INT_PRI_BASE + 19)
+#define INT_USB				(INT_PRI_BASE + 20)
+#define INT_USB2			(INT_PRI_BASE + 21)
+#define INT_PRI_RES_22			(INT_PRI_BASE + 22)
+#define INT_EIDE			(INT_PRI_BASE + 23)
+#define INT_NANDFLASH			(INT_PRI_BASE + 24)
+#define INT_VCP				(INT_PRI_BASE + 25)
+#define INT_APB_DMA			(INT_PRI_BASE + 26)
+#define INT_AHB_DMA			(INT_PRI_BASE + 27)
+#define INT_GNT_0			(INT_PRI_BASE + 28)
+#define INT_GNT_1			(INT_PRI_BASE + 29)
+#define INT_OWR				(INT_PRI_BASE + 30)
+#define INT_SDMMC4			(INT_PRI_BASE + 31)
+
+/* Secondary Interrupt Controller */
+#define INT_SEC_BASE			(INT_PRI_BASE + 32)
+#define INT_GPIO1			(INT_SEC_BASE + 0)
+#define INT_GPIO2			(INT_SEC_BASE + 1)
+#define INT_GPIO3			(INT_SEC_BASE + 2)
+#define INT_GPIO4			(INT_SEC_BASE + 3)
+#define INT_UARTA			(INT_SEC_BASE + 4)
+#define INT_UARTB			(INT_SEC_BASE + 5)
+#define INT_I2C				(INT_SEC_BASE + 6)
+#define INT_SPI				(INT_SEC_BASE + 7)
+#define INT_TWC				(INT_SEC_BASE + 8)
+#define INT_TMR3			(INT_SEC_BASE + 9)
+#define INT_TMR4			(INT_SEC_BASE + 10)
+#define INT_FLOW_RSM0			(INT_SEC_BASE + 11)
+#define INT_FLOW_RSM1			(INT_SEC_BASE + 12)
+#define INT_SPDIF			(INT_SEC_BASE + 13)
+#define INT_UARTC			(INT_SEC_BASE + 14)
+#define INT_MIPI			(INT_SEC_BASE + 15)
+#define INT_EVENTA			(INT_SEC_BASE + 16)
+#define INT_EVENTB			(INT_SEC_BASE + 17)
+#define INT_EVENTC			(INT_SEC_BASE + 18)
+#define INT_EVENTD			(INT_SEC_BASE + 19)
+#define INT_VFIR			(INT_SEC_BASE + 20)
+#define INT_DVC				(INT_SEC_BASE + 21)
+#define INT_SYS_STATS_MON		(INT_SEC_BASE + 22)
+#define INT_GPIO5			(INT_SEC_BASE + 23)
+#define INT_CPU0_PMU_INTR		(INT_SEC_BASE + 24)
+#define INT_CPU2_PMU_INTR		(INT_SEC_BASE + 25)
+#define INT_SEC_RES_26			(INT_SEC_BASE + 26)
+#define INT_S_LINK1			(INT_SEC_BASE + 27)
+#define INT_APB_DMA_COP			(INT_SEC_BASE + 28)
+#define INT_AHB_DMA_COP			(INT_SEC_BASE + 29)
+#define INT_DMA_TX			(INT_SEC_BASE + 30)
+#define INT_DMA_RX			(INT_SEC_BASE + 31)
+
+/* Tertiary Interrupt Controller */
+#define INT_TRI_BASE			(INT_SEC_BASE + 32)
+#define INT_HOST1X_COP_SYNCPT		(INT_TRI_BASE + 0)
+#define INT_HOST1X_MPCORE_SYNCPT	(INT_TRI_BASE + 1)
+#define INT_HOST1X_COP_GENERAL		(INT_TRI_BASE + 2)
+#define INT_HOST1X_MPCORE_GENERAL	(INT_TRI_BASE + 3)
+#define INT_MPE_GENERAL			(INT_TRI_BASE + 4)
+#define INT_VI_GENERAL			(INT_TRI_BASE + 5)
+#define INT_EPP_GENERAL			(INT_TRI_BASE + 6)
+#define INT_ISP_GENERAL			(INT_TRI_BASE + 7)
+#define INT_2D_GENERAL			(INT_TRI_BASE + 8)
+#define INT_DISPLAY_GENERAL		(INT_TRI_BASE + 9)
+#define INT_DISPLAY_B_GENERAL		(INT_TRI_BASE + 10)
+#define INT_HDMI			(INT_TRI_BASE + 11)
+#define INT_TVO_GENERAL			(INT_TRI_BASE + 12)
+#define INT_MC_GENERAL			(INT_TRI_BASE + 13)
+#define INT_EMC_GENERAL			(INT_TRI_BASE + 14)
+#define INT_TRI_RES_15			(INT_TRI_BASE + 15)
+#define INT_TRI_RES_16			(INT_TRI_BASE + 16)
+#define INT_AC97			(INT_TRI_BASE + 17)
+#define INT_SPI_2			(INT_TRI_BASE + 18)
+#define INT_SPI_3			(INT_TRI_BASE + 19)
+#define INT_I2C2			(INT_TRI_BASE + 20)
+#define INT_KBC				(INT_TRI_BASE + 21)
+#define INT_EXTERNAL_PMU		(INT_TRI_BASE + 22)
+#define INT_GPIO6			(INT_TRI_BASE + 23)
+#define INT_TVDAC			(INT_TRI_BASE + 24)
+#define INT_GPIO7			(INT_TRI_BASE + 25)
+#define INT_UARTD			(INT_TRI_BASE + 26)
+#define INT_UARTE			(INT_TRI_BASE + 27)
+#define INT_I2C3			(INT_TRI_BASE + 28)
+#define INT_SPI_4			(INT_TRI_BASE + 29)
+#define INT_TRI_RES_30			(INT_TRI_BASE + 30)
+#define INT_SW_RESERVED			(INT_TRI_BASE + 31)
+
+/* Quaternary Interrupt Controller */
+#define INT_QUAD_BASE			(INT_TRI_BASE + 32)
+#define INT_SNOR			(INT_QUAD_BASE + 0)
+#define INT_USB3			(INT_QUAD_BASE + 1)
+#define INT_PCIE_INTR			(INT_QUAD_BASE + 2)
+#define INT_PCIE_MSI			(INT_QUAD_BASE + 3)
+#define INT_QUAD_RES_4			(INT_QUAD_BASE + 4)
+#define INT_QUAD_RES_5			(INT_QUAD_BASE + 5)
+#define INT_QUAD_RES_6			(INT_QUAD_BASE + 6)
+#define INT_QUAD_RES_7			(INT_QUAD_BASE + 7)
+#define INT_APB_DMA_CH0			(INT_QUAD_BASE + 8)
+#define INT_APB_DMA_CH1			(INT_QUAD_BASE + 9)
+#define INT_APB_DMA_CH2			(INT_QUAD_BASE + 10)
+#define INT_APB_DMA_CH3			(INT_QUAD_BASE + 11)
+#define INT_APB_DMA_CH4			(INT_QUAD_BASE + 12)
+#define INT_APB_DMA_CH5			(INT_QUAD_BASE + 13)
+#define INT_APB_DMA_CH6			(INT_QUAD_BASE + 14)
+#define INT_APB_DMA_CH7			(INT_QUAD_BASE + 15)
+#define INT_APB_DMA_CH8			(INT_QUAD_BASE + 16)
+#define INT_APB_DMA_CH9			(INT_QUAD_BASE + 17)
+#define INT_APB_DMA_CH10		(INT_QUAD_BASE + 18)
+#define INT_APB_DMA_CH11		(INT_QUAD_BASE + 19)
+#define INT_APB_DMA_CH12		(INT_QUAD_BASE + 20)
+#define INT_APB_DMA_CH13		(INT_QUAD_BASE + 21)
+#define INT_APB_DMA_CH14		(INT_QUAD_BASE + 22)
+#define INT_APB_DMA_CH15		(INT_QUAD_BASE + 23)
+#define INT_QUAD_RES_24			(INT_QUAD_BASE + 24)
+#define INT_QUAD_RES_25			(INT_QUAD_BASE + 25)
+#define INT_QUAD_RES_26			(INT_QUAD_BASE + 26)
+#define INT_QUAD_RES_27			(INT_QUAD_BASE + 27)
+#define INT_QUAD_RES_28			(INT_QUAD_BASE + 28)
+#define INT_QUAD_RES_29			(INT_QUAD_BASE + 29)
+#define INT_QUAD_RES_30			(INT_QUAD_BASE + 30)
+#define INT_QUAD_RES_31			(INT_QUAD_BASE + 31)
+
+#define INT_GPIO_BASE			(INT_QUAD_BASE + 32)
+#define INT_GPIO_NR			(28 * 8)
+
+#define NR_IRQS				(INT_GPIO_BASE + INT_GPIO_NR)
+
+#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
new file mode 100644
index 0000000..1fdbe70
--- /dev/null
+++ b/arch/arm/mach-tegra/irq.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <asm/hardware/gic.h>
+
+#include <mach/iomap.h>
+
+#include "board.h"
+
+void __init tegra_init_irq(void)
+{
+	gic_dist_init(0, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), 29);
+	gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
+}
-- 
1.6.5.6



From konkers at android.com  Mon Jun 14 17:10:20 2010
From: konkers at android.com (Erik Gilling)
Date: Mon, 14 Jun 2010 14:10:20 -0700
Subject: [PATCH v3 04/11] [ARM] tegra: SMP support
In-Reply-To: <1276549827-2688-4-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
	<1276549827-2688-3-git-send-email-konkers@android.com>
	<1276549827-2688-4-git-send-email-konkers@android.com>
Message-ID: <1276549827-2688-5-git-send-email-konkers@android.com>

From: Colin Cross <ccross at android.com>

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Erik Gilling <konkers at android.com>
---
 arch/arm/Kconfig                       |   11 ++-
 arch/arm/mach-tegra/Makefile           |    2 +
 arch/arm/mach-tegra/headsmp.S          |   61 +++++++++++++
 arch/arm/mach-tegra/hotplug.c          |  140 ++++++++++++++++++++++++++++
 arch/arm/mach-tegra/include/mach/smp.h |   30 ++++++
 arch/arm/mach-tegra/localtimer.c       |   25 +++++
 arch/arm/mach-tegra/platsmp.c          |  156 ++++++++++++++++++++++++++++++++
 7 files changed, 421 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-tegra/headsmp.S
 create mode 100644 arch/arm/mach-tegra/hotplug.c
 create mode 100644 arch/arm/mach-tegra/include/mach/smp.h
 create mode 100644 arch/arm/mach-tegra/localtimer.c
 create mode 100644 arch/arm/mach-tegra/platsmp.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 98e41e1..c8f28f8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1113,10 +1113,11 @@ config SMP
 	bool "Symmetric Multi-Processing (EXPERIMENTAL)"
 	depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
 		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
-		 ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
+		 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_TEGRA)
 	depends on GENERIC_CLOCKEVENTS
 	select USE_GENERIC_SMP_HELPERS
-	select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
+	select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || \
+		 ARCH_VEXPRESS_CA9X4 || ARCH_TEGRA)
 	help
 	  This enables support for systems with more than one CPU. If you have
 	  a system with only one CPU, like most personal computers, say N. If
@@ -1185,9 +1186,11 @@ config HOTPLUG_CPU
 config LOCAL_TIMERS
 	bool "Use local timer interrupts"
 	depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
-		REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
+		REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+		ARCH_U8500 || ARCH_TEGRA)
 	default y
-	select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
+	select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || \
+		ARCH_TEGRA)
 	help
 	  Enable support for local timers on SMP platforms, rather then the
 	  legacy IPI broadcast method.  Local timers allows the system
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index e20546a..f339559 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -3,3 +3,5 @@ obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
+obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
+obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
new file mode 100644
index 0000000..b5349b2
--- /dev/null
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -0,0 +1,61 @@
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        .section ".text.head", "ax"
+	__CPUINIT
+
+/*
+ * Tegra specific entry point for secondary CPUs.
+ *   The secondary kernel init calls v7_flush_dcache_all before it enables
+ *   the L1; however, the L1 comes out of reset in an undefined state, so
+ *   the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ *   of cache lines with uninitialized data and uninitialized tags to get
+ *   written out to memory, which does really unpleasant things to the main
+ *   processor.  We fix this by performing an invalidate, rather than a
+ *   clean + invalidate, before jumping into the kernel.
+ */
+ENTRY(v7_invalidate_l1)
+        mov     r0, #0
+        mcr     p15, 2, r0, c0, c0, 0
+        mrc     p15, 1, r0, c0, c0, 0
+
+        ldr     r1, =0x7fff
+        and     r2, r1, r0, lsr #13
+
+        ldr     r1, =0x3ff
+
+        and     r3, r1, r0, lsr #3  @ NumWays - 1
+        add     r2, r2, #1          @ NumSets
+
+        and     r0, r0, #0x7
+        add     r0, r0, #4          @ SetShift
+
+        clz     r1, r3              @ WayShift
+        add     r4, r3, #1          @ NumWays
+1:      sub     r2, r2, #1          @ NumSets--
+        mov     r3, r4              @ Temp = NumWays
+2:      subs    r3, r3, #1          @ Temp--
+        mov     r5, r3, lsl r1
+        mov     r6, r2, lsl r0
+        orr     r5, r5, r6          @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+        mcr     p15, 0, r5, c7, c6, 2
+        bgt     2b
+        cmp     r2, #0
+        bgt     1b
+        dsb
+        isb
+        mov     pc, lr
+ENDPROC(v7_invalidate_l1)
+
+ENTRY(tegra_secondary_startup)
+	msr	cpsr_fsxc, #0xd3
+        bl      v7_invalidate_l1
+	mrc	p15, 0, r0, c0, c0, 5
+        and	r0, r0, #15
+        ldr     r1, =0x6000f100
+        str     r0, [r1]
+1:      ldr     r2, [r1]
+        cmp     r0, r2
+        beq     1b
+        b       secondary_startup
+ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
new file mode 100644
index 0000000..8e7f115
--- /dev/null
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -0,0 +1,140 @@
+/*
+ *  linux/arch/arm/mach-realview/hotplug.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/smp.h>
+#include <linux/completion.h>
+
+#include <asm/cacheflush.h>
+
+static DECLARE_COMPLETION(cpu_killed);
+
+static inline void cpu_enter_lowpower(void)
+{
+	unsigned int v;
+
+	flush_cache_all();
+	asm volatile(
+	"	mcr	p15, 0, %1, c7, c5, 0\n"
+	"	mcr	p15, 0, %1, c7, c10, 4\n"
+	/*
+	 * Turn off coherency
+	 */
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	bic	%0, %0, #0x20\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	"	mrc	p15, 0, %0, c1, c0, 0\n"
+	"	bic	%0, %0, #0x04\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	  : "=&r" (v)
+	  : "r" (0)
+	  : "cc");
+}
+
+static inline void cpu_leave_lowpower(void)
+{
+	unsigned int v;
+
+	asm volatile(
+	"mrc	p15, 0, %0, c1, c0, 0\n"
+	"	orr	%0, %0, #0x04\n"
+	"	mcr	p15, 0, %0, c1, c0, 0\n"
+	"	mrc	p15, 0, %0, c1, c0, 1\n"
+	"	orr	%0, %0, #0x20\n"
+	"	mcr	p15, 0, %0, c1, c0, 1\n"
+	  : "=&r" (v)
+	  :
+	  : "cc");
+}
+
+static inline void platform_do_lowpower(unsigned int cpu)
+{
+	/*
+	 * there is no power-control hardware on this platform, so all
+	 * we can do is put the core into WFI; this is safe as the calling
+	 * code will have already disabled interrupts
+	 */
+	for (;;) {
+		/*
+		 * here's the WFI
+		 */
+		asm(".word	0xe320f003\n"
+		    :
+		    :
+		    : "memory", "cc");
+
+		/*if (pen_release == cpu) {*/
+			/*
+			 * OK, proper wakeup, we're done
+			 */
+			break;
+		/*}*/
+
+		/*
+		 * getting here, means that we have come out of WFI without
+		 * having been woken up - this shouldn't happen
+		 *
+		 * The trouble is, letting people know about this is not really
+		 * possible, since we are currently running incoherently, and
+		 * therefore cannot safely call printk() or anything else
+		 */
+#ifdef DEBUG
+		printk(KERN_WARN "CPU%u: spurious wakeup call\n", cpu);
+#endif
+	}
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+	return wait_for_completion_timeout(&cpu_killed, 5000);
+}
+
+/*
+ * platform-specific code to shutdown a CPU
+ *
+ * Called with IRQs disabled
+ */
+void platform_cpu_die(unsigned int cpu)
+{
+#ifdef DEBUG
+	unsigned int this_cpu = hard_smp_processor_id();
+
+	if (cpu != this_cpu) {
+		printk(KERN_CRIT "Eek! platform_cpu_die running on %u, should be %u\n",
+			   this_cpu, cpu);
+		BUG();
+	}
+#endif
+
+	printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
+	complete(&cpu_killed);
+
+	/*
+	 * we're ready for shutdown now, so do it
+	 */
+	cpu_enter_lowpower();
+	platform_do_lowpower(cpu);
+
+	/*
+	 * bring this CPU back into the world of cache
+	 * coherency, and then restore interrupts
+	 */
+	cpu_leave_lowpower();
+}
+
+int platform_cpu_disable(unsigned int cpu)
+{
+	/*
+	 * we don't allow CPU 0 to be shutdown (it is still too special
+	 * e.g. clock tick interrupts)
+	 */
+	return cpu == 0 ? -EPERM : 0;
+}
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
new file mode 100644
index 0000000..8b42dab
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/smp.h
@@ -0,0 +1,30 @@
+#ifndef ASMARM_ARCH_SMP_H
+#define ASMARM_ARCH_SMP_H
+
+
+#include <asm/hardware/gic.h>
+
+#define hard_smp_processor_id()			\
+	({						\
+		unsigned int cpunum;			\
+		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
+			: "=r" (cpunum));		\
+		cpunum &= 0x0F;				\
+	})
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(const struct cpumask *mask)
+{
+	gic_raise_softirq(mask, 1);
+}
+
+/*
+ * Do nothing on MPcore.
+ */
+static inline void smp_cross_call_done(cpumask_t callmap)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-tegra/localtimer.c b/arch/arm/mach-tegra/localtimer.c
new file mode 100644
index 0000000..f81ca7c
--- /dev/null
+++ b/arch/arm/mach-tegra/localtimer.c
@@ -0,0 +1,25 @@
+/*
+ *  arch/arm/mach-tegra/localtimer.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/clockchips.h>
+#include <asm/irq.h>
+#include <asm/smp_twd.h>
+#include <asm/localtimer.h>
+
+/*
+ * Setup the local clock events for a CPU.
+ */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+	evt->irq = IRQ_LOCALTIMER;
+	twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
new file mode 100644
index 0000000..1c0fd92
--- /dev/null
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -0,0 +1,156 @@
+/*
+ *  linux/arch/arm/mach-tegra/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ *  Copyright (C) 2009 Palm
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/localtimer.h>
+#include <asm/smp_scu.h>
+
+#include <mach/iomap.h>
+
+extern void tegra_secondary_startup(void);
+
+static DEFINE_SPINLOCK(boot_lock);
+static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
+
+#define EVP_CPU_RESET_VECTOR \
+	(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
+#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
+	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
+#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
+	(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+	trace_hardirqs_off();
+
+	/*
+	 * if any interrupts are already enabled for the primary
+	 * core (e.g. timer irq), then they will not have been enabled
+	 * for us: do so
+	 */
+	gic_cpu_init(0, IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x100);
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long old_boot_vector;
+	unsigned long boot_vector;
+	unsigned long timeout;
+	u32 reg;
+
+	/*
+	 * set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+
+	/* set the reset vector to point to the secondary_startup routine */
+
+	boot_vector = virt_to_phys(tegra_secondary_startup);
+	old_boot_vector = readl(EVP_CPU_RESET_VECTOR);
+	writel(boot_vector, EVP_CPU_RESET_VECTOR);
+
+	/* enable cpu clock on cpu1 */
+	reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+	writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+
+	reg = (1<<13) | (1<<9) | (1<<5) | (1<<1);
+	writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+
+	smp_wmb();
+	flush_cache_all();
+
+	/* unhalt the cpu */
+	writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14);
+
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
+			break;
+		udelay(10);
+	}
+
+	/* put the old boot vector back */
+	writel(old_boot_vector, EVP_CPU_RESET_VECTOR);
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+	unsigned int i, ncores = scu_get_core_count(scu_base);
+
+	for (i = 0; i < ncores; i++)
+		cpu_set(i, cpu_possible_map);
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+	unsigned int ncores = scu_get_core_count(scu_base);
+	unsigned int cpu = smp_processor_id();
+	int i;
+
+	smp_store_cpu_info(cpu);
+
+	/*
+	 * are we trying to boot more cores than exist?
+	 */
+	if (max_cpus > ncores)
+		max_cpus = ncores;
+
+	/*
+	 * Initialise the present map, which describes the set of CPUs
+	 * actually populated at the present time.
+	 */
+	for (i = 0; i < max_cpus; i++)
+		set_cpu_present(i, true);
+
+	/*
+	 * Initialise the SCU if there are more than one CPU and let
+	 * them know where to start. Note that, on modern versions of
+	 * MILO, the "poke" doesn't actually do anything until each
+	 * individual core is sent a soft interrupt to get it out of
+	 * WFI
+	 */
+	if (max_cpus > 1) {
+		percpu_timer_setup();
+		scu_enable(scu_base);
+	}
+}
-- 
1.6.5.6



From konkers at android.com  Mon Jun 14 17:10:24 2010
From: konkers at android.com (Erik Gilling)
Date: Mon, 14 Jun 2010 14:10:24 -0700
Subject: [PATCH v3 08/11] [ARM] tegra: harmony: Add harmony board file
In-Reply-To: <1276549827-2688-8-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
	<1276549827-2688-3-git-send-email-konkers@android.com>
	<1276549827-2688-4-git-send-email-konkers@android.com>
	<1276549827-2688-5-git-send-email-konkers@android.com>
	<1276549827-2688-6-git-send-email-konkers@android.com>
	<1276549827-2688-7-git-send-email-konkers@android.com>
	<1276549827-2688-8-git-send-email-konkers@android.com>
Message-ID: <1276549827-2688-9-git-send-email-konkers@android.com>

From: Colin Cross <ccross at android.com>

v2: fixes from Russell King
	- include linux/io.h instead of mach/io.h

v3: fixes from Linus Walleij
	- remove /16 * 16 from UART clock

v3:
	- Fix checkpatch issues
	- make board init calls explicit
	- use clock init table to set clocks
	- remove panel

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Erik Gilling <konkers at android.com>
---
 arch/arm/mach-tegra/Makefile               |    3 +
 arch/arm/mach-tegra/board-harmony-pinmux.c |  144 ++++++++++++++++++++++++++++
 arch/arm/mach-tegra/board-harmony.c        |  127 ++++++++++++++++++++++++
 arch/arm/mach-tegra/board-harmony.h        |   22 ++++
 4 files changed, 296 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/board-harmony-pinmux.c
 create mode 100644 arch/arm/mach-tegra/board-harmony.c
 create mode 100644 arch/arm/mach-tegra/board-harmony.h

diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 5e47a71..51e9370 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -9,3 +9,6 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += clock.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
+
+obj-${CONFIG_MACH_HARMONY}              += board-harmony.o
+obj-${CONFIG_MACH_HARMONY}              += board-harmony-pinmux.o
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
new file mode 100644
index 0000000..50b15d5
--- /dev/null
+++ b/arch/arm/mach-tegra/board-harmony-pinmux.c
@@ -0,0 +1,144 @@
+/*
+ * arch/arm/mach-tegra/board-harmony-pinmux.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <mach/pinmux.h>
+
+#include "board-harmony.h"
+
+static struct tegra_pingroup_config harmony_pinmux[] = {
+	{TEGRA_PINGROUP_ATA,   TEGRA_MUX_IDE,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_ATB,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_ATC,   TEGRA_MUX_NAND,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_ATD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_ATE,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4,     TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CRTP,  TEGRA_MUX_CRT,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CSUS,  TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DAP1,  TEGRA_MUX_DAP1,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DAP2,  TEGRA_MUX_DAP2,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DAP3,  TEGRA_MUX_DAP3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DAP4,  TEGRA_MUX_DAP4,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DDC,   TEGRA_MUX_I2C2,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_DTA,   TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DTB,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DTC,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DTD,   TEGRA_MUX_SDIO2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DTE,   TEGRA_MUX_RSVD1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_DTF,   TEGRA_MUX_I2C3,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_GMA,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GMB,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GMC,   TEGRA_MUX_UARTD,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GMD,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GME,   TEGRA_MUX_SDIO4,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GPU,   TEGRA_MUX_GMI,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_GPU7,  TEGRA_MUX_RTCK,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_GPV,   TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_I2CP,  TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_IRRX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_IRTX,  TEGRA_MUX_UARTA,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_KBCA,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCB,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCC,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCD,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCE,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_KBCF,  TEGRA_MUX_KBC,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LCSN,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LD0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD10,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD11,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD12,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD13,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD14,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD15,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD16,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD17,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD2,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD3,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD4,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD5,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD6,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD7,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD8,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LD9,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LDC,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LDI,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LHP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LHP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LHP2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LHS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LM0,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LM1,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LPP,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LPW0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LPW1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LPW2,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LSC0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LSC1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSCK,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSDA,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSDI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LSPI,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LVP0,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_LVP1,  TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_LVS,   TEGRA_MUX_DISPLAYA,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_OWC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_PMC,   TEGRA_MUX_PWR_ON,        TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PTA,   TEGRA_MUX_HDMI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_RM,    TEGRA_MUX_I2C,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SDB,   TEGRA_MUX_PWM,           TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SDC,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SDD,   TEGRA_MUX_PWM,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SDIO1, TEGRA_MUX_SDIO1,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXA,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXC,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXD,  TEGRA_MUX_SPDIF,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SLXK,  TEGRA_MUX_PCIE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPDI,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPDO,  TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIA,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIB,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIC,  TEGRA_MUX_GMI,           TEGRA_PUPD_PULL_UP,   TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_SPID,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIE,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIF,  TEGRA_MUX_SPI1,          TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIG,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_SPIH,  TEGRA_MUX_SPI2_ALT,      TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UAA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UAB,   TEGRA_MUX_ULPI,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UAC,   TEGRA_MUX_RSVD2,         TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UAD,   TEGRA_MUX_IRDA,          TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UCA,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UCB,   TEGRA_MUX_UARTC,         TEGRA_PUPD_PULL_UP,   TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_UDA,   TEGRA_MUX_ULPI,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_TRISTATE},
+	{TEGRA_PINGROUP_CK32,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_DDRC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCA,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCB,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCC,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCD,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_PMCE,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_XM2C,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+	{TEGRA_PINGROUP_XM2D,  TEGRA_MUX_NONE,          TEGRA_PUPD_NORMAL,    TEGRA_TRI_NORMAL},
+};
+
+void harmony_pinmux_init(void)
+{
+	tegra_pinmux_config_table(harmony_pinmux, ARRAY_SIZE(harmony_pinmux));
+}
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
new file mode 100644
index 0000000..05e78dd
--- /dev/null
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -0,0 +1,127 @@
+/*
+ * arch/arm/mach-tegra/board-harmony.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/pda_power.h>
+#include <linux/io.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/setup.h>
+
+#include <mach/iomap.h>
+#include <mach/irqs.h>
+
+#include "board.h"
+#include "board-harmony.h"
+#include "clock.h"
+
+/* NVidia bootloader tags */
+#define ATAG_NVIDIA		0x41000801
+
+#define ATAG_NVIDIA_RM			0x1
+#define ATAG_NVIDIA_DISPLAY		0x2
+#define ATAG_NVIDIA_FRAMEBUFFER		0x3
+#define ATAG_NVIDIA_CHIPSHMOO		0x4
+#define ATAG_NVIDIA_CHIPSHMOOPHYS	0x5
+#define ATAG_NVIDIA_PRESERVED_MEM_0	0x10000
+#define ATAG_NVIDIA_PRESERVED_MEM_N	2
+#define ATAG_NVIDIA_FORCE_32		0x7fffffff
+
+struct tag_tegra {
+	__u32 bootarg_key;
+	__u32 bootarg_len;
+	char bootarg[1];
+};
+
+static int __init parse_tag_nvidia(const struct tag *tag)
+{
+
+	return 0;
+}
+__tagtable(ATAG_NVIDIA, parse_tag_nvidia);
+
+static struct plat_serial8250_port debug_uart_platform_data[] = {
+	{
+		.membase	= IO_ADDRESS(TEGRA_UARTD_BASE),
+		.mapbase	= TEGRA_UARTD_BASE,
+		.irq		= INT_UARTD,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.iotype		= UPIO_MEM,
+		.regshift	= 2,
+		.uartclk	= 216000000,
+	}, {
+		.flags		= 0
+	}
+};
+
+static struct platform_device debug_uart = {
+	.name = "serial8250",
+	.id = PLAT8250_DEV_PLATFORM,
+	.dev = {
+		.platform_data = debug_uart_platform_data,
+	},
+};
+
+static struct platform_device *harmony_devices[] __initdata = {
+	&debug_uart,
+};
+
+static void __init tegra_harmony_fixup(struct machine_desc *desc,
+	struct tag *tags, char **cmdline, struct meminfo *mi)
+{
+	mi->nr_banks = 2;
+	mi->bank[0].start = PHYS_OFFSET;
+	mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
+	mi->bank[0].size = 448 * SZ_1M;
+	mi->bank[1].start = SZ_512M;
+	mi->bank[1].node = PHYS_TO_NID(SZ_512M);
+	mi->bank[1].size = SZ_512M;
+}
+
+static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = {
+	/* name		parent		rate		enabled */
+	{ "uartd",	"pll_p",	216000000,	true },
+	{ NULL,		NULL,		0,		0},
+};
+
+static void __init tegra_harmony_init(void)
+{
+	tegra_common_init();
+
+	tegra_clk_init_from_table(harmony_clk_init_table);
+
+	harmony_pinmux_init();
+
+	platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
+}
+
+MACHINE_START(HARMONY, "harmony")
+	.boot_params  = 0x00000100,
+	.phys_io        = IO_APB_PHYS,
+	.io_pg_offst    = ((IO_APB_VIRT) >> 18) & 0xfffc,
+	.fixup		= tegra_harmony_fixup,
+	.init_irq       = tegra_init_irq,
+	.init_machine   = tegra_harmony_init,
+	.map_io         = tegra_map_common_io,
+	.timer          = &tegra_timer,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h
new file mode 100644
index 0000000..09ca775
--- /dev/null
+++ b/arch/arm/mach-tegra/board-harmony.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-tegra/board-harmony.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _MACH_TEGRA_BOARD_HARMONY_H
+#define _MACH_TEGRA_BOARD_HARMONY_H
+
+void harmony_pinmux_init(void);
+
+#endif
-- 
1.6.5.6



From konkers at android.com  Mon Jun 14 17:10:25 2010
From: konkers at android.com (Erik Gilling)
Date: Mon, 14 Jun 2010 14:10:25 -0700
Subject: [PATCH v3 09/11] [ARM] tegra: add MAINTAINERS entry
In-Reply-To: <1276549827-2688-9-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
	<1276549827-2688-3-git-send-email-konkers@android.com>
	<1276549827-2688-4-git-send-email-konkers@android.com>
	<1276549827-2688-5-git-send-email-konkers@android.com>
	<1276549827-2688-6-git-send-email-konkers@android.com>
	<1276549827-2688-7-git-send-email-konkers@android.com>
	<1276549827-2688-8-git-send-email-konkers@android.com>
	<1276549827-2688-9-git-send-email-konkers@android.com>
Message-ID: <1276549827-2688-10-git-send-email-konkers@android.com>

Signed-off-by: Erik Gilling <konkers at android.com>
Signed-off-by: Colin Cross <ccross at android.com>
Acked-by: Olof Johansson <olof at lixom.net>
---
 MAINTAINERS |    9 +++++++++
 1 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 67accd7..7cc831a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5520,6 +5520,15 @@ W:	http://tcp-lp-mod.sourceforge.net/
 S:	Maintained
 F:	net/ipv4/tcp_lp.c
 
+TEGRA SUPPORT
+M:	Colin Cross <ccross at android.com>
+M:	Erik Gilling <konkers at android.com>
+M:	Olof Johansson <olof at lixom.net>
+L:	linux-tegra at vger.kernel.org
+T:	git git://android.git.kernel.org/kernel/tegra.git
+S:	Supported
+F:	arch/arm/mach-tegra
+
 TEHUTI ETHERNET DRIVER
 M:	Alexander Indenbaum <baum at tehutinetworks.net>
 M:	Andy Gospodarek <andy at greyhouse.net>
-- 
1.6.5.6



From konkers at android.com  Mon Jun 14 17:10:22 2010
From: konkers at android.com (Erik Gilling)
Date: Mon, 14 Jun 2010 14:10:22 -0700
Subject: [PATCH v3 06/11] [ARM] tegra: add GPIO support
In-Reply-To: <1276549827-2688-6-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
	<1276549827-2688-3-git-send-email-konkers@android.com>
	<1276549827-2688-4-git-send-email-konkers@android.com>
	<1276549827-2688-5-git-send-email-konkers@android.com>
	<1276549827-2688-6-git-send-email-konkers@android.com>
Message-ID: <1276549827-2688-7-git-send-email-konkers@android.com>

v2: fixes from Mike Rapoport:
	- move gpio-names.h to arch/arm/mach-tegra
    fixes from Russell King
	- include linux/io.h and linux/gpio.h instead of asm/io.h
	  and asm/gpio.h
    additional changes:
    	- add macros to convert between irq and gpio numbers for platform data
	- change for_each_bit to for_each_set_bit in gpio.c
v3:
	- minor bugfixes

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Erik Gilling <konkers at android.com>
---
 arch/arm/mach-tegra/Kconfig             |    1 +
 arch/arm/mach-tegra/Makefile            |    1 +
 arch/arm/mach-tegra/gpio-names.h        |  247 ++++++++++++++++++++++
 arch/arm/mach-tegra/gpio.c              |  348 +++++++++++++++++++++++++++++++
 arch/arm/mach-tegra/include/mach/gpio.h |   53 +++++
 5 files changed, 650 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/gpio-names.h
 create mode 100644 arch/arm/mach-tegra/gpio.c
 create mode 100644 arch/arm/mach-tegra/include/mach/gpio.h

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index bcbda96..a57713c 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -9,6 +9,7 @@ config ARCH_TEGRA_2x_SOC
 	bool "Tegra 2 family"
 	select CPU_V7
 	select ARM_GIC
+	select ARCH_REQUIRE_GPIOLIB
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 01f47fd..122f7dc 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -3,6 +3,7 @@ obj-y                                   += io.o
 obj-y                                   += irq.o
 obj-y                                   += clock.o
 obj-y                                   += timer.o
+obj-y                                   += gpio.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o localtimer.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
diff --git a/arch/arm/mach-tegra/gpio-names.h b/arch/arm/mach-tegra/gpio-names.h
new file mode 100644
index 0000000..f28220a
--- /dev/null
+++ b/arch/arm/mach-tegra/gpio-names.h
@@ -0,0 +1,247 @@
+/*
+ * arch/arm/mach-tegra/include/mach/gpio-names.h
+ *
+ * Copyright (c) 2010 Google, Inc
+ *
+ * Author:
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_TEGRA_GPIO_NAMES_H
+#define __MACH_TEGRA_GPIO_NAMES_H
+
+#define TEGRA_GPIO_PA0		0
+#define TEGRA_GPIO_PA1		1
+#define TEGRA_GPIO_PA2		2
+#define TEGRA_GPIO_PA3		3
+#define TEGRA_GPIO_PA4		4
+#define TEGRA_GPIO_PA5		5
+#define TEGRA_GPIO_PA6		6
+#define TEGRA_GPIO_PA7		7
+#define TEGRA_GPIO_PB0		8
+#define TEGRA_GPIO_PB1		9
+#define TEGRA_GPIO_PB2		10
+#define TEGRA_GPIO_PB3		11
+#define TEGRA_GPIO_PB4		12
+#define TEGRA_GPIO_PB5		13
+#define TEGRA_GPIO_PB6		14
+#define TEGRA_GPIO_PB7		15
+#define TEGRA_GPIO_PC0		16
+#define TEGRA_GPIO_PC1		17
+#define TEGRA_GPIO_PC2		18
+#define TEGRA_GPIO_PC3		19
+#define TEGRA_GPIO_PC4		20
+#define TEGRA_GPIO_PC5		21
+#define TEGRA_GPIO_PC6		22
+#define TEGRA_GPIO_PC7		23
+#define TEGRA_GPIO_PD0		24
+#define TEGRA_GPIO_PD1		25
+#define TEGRA_GPIO_PD2		26
+#define TEGRA_GPIO_PD3		27
+#define TEGRA_GPIO_PD4		28
+#define TEGRA_GPIO_PD5		29
+#define TEGRA_GPIO_PD6		30
+#define TEGRA_GPIO_PD7		31
+#define TEGRA_GPIO_PE0		32
+#define TEGRA_GPIO_PE1		33
+#define TEGRA_GPIO_PE2		34
+#define TEGRA_GPIO_PE3		35
+#define TEGRA_GPIO_PE4		36
+#define TEGRA_GPIO_PE5		37
+#define TEGRA_GPIO_PE6		38
+#define TEGRA_GPIO_PE7		39
+#define TEGRA_GPIO_PF0		40
+#define TEGRA_GPIO_PF1		41
+#define TEGRA_GPIO_PF2		42
+#define TEGRA_GPIO_PF3		43
+#define TEGRA_GPIO_PF4		44
+#define TEGRA_GPIO_PF5		45
+#define TEGRA_GPIO_PF6		46
+#define TEGRA_GPIO_PF7		47
+#define TEGRA_GPIO_PG0		48
+#define TEGRA_GPIO_PG1		49
+#define TEGRA_GPIO_PG2		50
+#define TEGRA_GPIO_PG3		51
+#define TEGRA_GPIO_PG4		52
+#define TEGRA_GPIO_PG5		53
+#define TEGRA_GPIO_PG6		54
+#define TEGRA_GPIO_PG7		55
+#define TEGRA_GPIO_PH0		56
+#define TEGRA_GPIO_PH1		57
+#define TEGRA_GPIO_PH2		58
+#define TEGRA_GPIO_PH3		59
+#define TEGRA_GPIO_PH4		60
+#define TEGRA_GPIO_PH5		61
+#define TEGRA_GPIO_PH6		62
+#define TEGRA_GPIO_PH7		63
+#define TEGRA_GPIO_PI0		64
+#define TEGRA_GPIO_PI1		65
+#define TEGRA_GPIO_PI2		66
+#define TEGRA_GPIO_PI3		67
+#define TEGRA_GPIO_PI4		68
+#define TEGRA_GPIO_PI5		69
+#define TEGRA_GPIO_PI6		70
+#define TEGRA_GPIO_PI7		71
+#define TEGRA_GPIO_PJ0		72
+#define TEGRA_GPIO_PJ1		73
+#define TEGRA_GPIO_PJ2		74
+#define TEGRA_GPIO_PJ3		75
+#define TEGRA_GPIO_PJ4		76
+#define TEGRA_GPIO_PJ5		77
+#define TEGRA_GPIO_PJ6		78
+#define TEGRA_GPIO_PJ7		79
+#define TEGRA_GPIO_PK0		80
+#define TEGRA_GPIO_PK1		81
+#define TEGRA_GPIO_PK2		82
+#define TEGRA_GPIO_PK3		83
+#define TEGRA_GPIO_PK4		84
+#define TEGRA_GPIO_PK5		85
+#define TEGRA_GPIO_PK6		86
+#define TEGRA_GPIO_PK7		87
+#define TEGRA_GPIO_PL0		88
+#define TEGRA_GPIO_PL1		89
+#define TEGRA_GPIO_PL2		90
+#define TEGRA_GPIO_PL3		91
+#define TEGRA_GPIO_PL4		92
+#define TEGRA_GPIO_PL5		93
+#define TEGRA_GPIO_PL6		94
+#define TEGRA_GPIO_PL7		95
+#define TEGRA_GPIO_PM0		96
+#define TEGRA_GPIO_PM1		97
+#define TEGRA_GPIO_PM2		98
+#define TEGRA_GPIO_PM3		99
+#define TEGRA_GPIO_PM4		100
+#define TEGRA_GPIO_PM5		101
+#define TEGRA_GPIO_PM6		102
+#define TEGRA_GPIO_PM7		103
+#define TEGRA_GPIO_PN0		104
+#define TEGRA_GPIO_PN1		105
+#define TEGRA_GPIO_PN2		106
+#define TEGRA_GPIO_PN3		107
+#define TEGRA_GPIO_PN4		108
+#define TEGRA_GPIO_PN5		109
+#define TEGRA_GPIO_PN6		110
+#define TEGRA_GPIO_PN7		111
+#define TEGRA_GPIO_PO0		112
+#define TEGRA_GPIO_PO1		113
+#define TEGRA_GPIO_PO2		114
+#define TEGRA_GPIO_PO3		115
+#define TEGRA_GPIO_PO4		116
+#define TEGRA_GPIO_PO5		117
+#define TEGRA_GPIO_PO6		118
+#define TEGRA_GPIO_PO7		119
+#define TEGRA_GPIO_PP0		120
+#define TEGRA_GPIO_PP1		121
+#define TEGRA_GPIO_PP2		122
+#define TEGRA_GPIO_PP3		123
+#define TEGRA_GPIO_PP4		124
+#define TEGRA_GPIO_PP5		125
+#define TEGRA_GPIO_PP6		126
+#define TEGRA_GPIO_PP7		127
+#define TEGRA_GPIO_PQ0		128
+#define TEGRA_GPIO_PQ1		129
+#define TEGRA_GPIO_PQ2		130
+#define TEGRA_GPIO_PQ3		131
+#define TEGRA_GPIO_PQ4		132
+#define TEGRA_GPIO_PQ5		133
+#define TEGRA_GPIO_PQ6		134
+#define TEGRA_GPIO_PQ7		135
+#define TEGRA_GPIO_PR0		136
+#define TEGRA_GPIO_PR1		137
+#define TEGRA_GPIO_PR2		138
+#define TEGRA_GPIO_PR3		139
+#define TEGRA_GPIO_PR4		140
+#define TEGRA_GPIO_PR5		141
+#define TEGRA_GPIO_PR6		142
+#define TEGRA_GPIO_PR7		143
+#define TEGRA_GPIO_PS0		144
+#define TEGRA_GPIO_PS1		145
+#define TEGRA_GPIO_PS2		146
+#define TEGRA_GPIO_PS3		147
+#define TEGRA_GPIO_PS4		148
+#define TEGRA_GPIO_PS5		149
+#define TEGRA_GPIO_PS6		150
+#define TEGRA_GPIO_PS7		151
+#define TEGRA_GPIO_PT0		152
+#define TEGRA_GPIO_PT1		153
+#define TEGRA_GPIO_PT2		154
+#define TEGRA_GPIO_PT3		155
+#define TEGRA_GPIO_PT4		156
+#define TEGRA_GPIO_PT5		157
+#define TEGRA_GPIO_PT6		158
+#define TEGRA_GPIO_PT7		159
+#define TEGRA_GPIO_PU0		160
+#define TEGRA_GPIO_PU1		161
+#define TEGRA_GPIO_PU2		162
+#define TEGRA_GPIO_PU3		163
+#define TEGRA_GPIO_PU4		164
+#define TEGRA_GPIO_PU5		165
+#define TEGRA_GPIO_PU6		166
+#define TEGRA_GPIO_PU7		167
+#define TEGRA_GPIO_PV0		168
+#define TEGRA_GPIO_PV1		169
+#define TEGRA_GPIO_PV2		170
+#define TEGRA_GPIO_PV3		171
+#define TEGRA_GPIO_PV4		172
+#define TEGRA_GPIO_PV5		173
+#define TEGRA_GPIO_PV6		174
+#define TEGRA_GPIO_PV7		175
+#define TEGRA_GPIO_PW0		176
+#define TEGRA_GPIO_PW1		177
+#define TEGRA_GPIO_PW2		178
+#define TEGRA_GPIO_PW3		179
+#define TEGRA_GPIO_PW4		180
+#define TEGRA_GPIO_PW5		181
+#define TEGRA_GPIO_PW6		182
+#define TEGRA_GPIO_PW7		183
+#define TEGRA_GPIO_PX0		184
+#define TEGRA_GPIO_PX1		185
+#define TEGRA_GPIO_PX2		186
+#define TEGRA_GPIO_PX3		187
+#define TEGRA_GPIO_PX4		188
+#define TEGRA_GPIO_PX5		189
+#define TEGRA_GPIO_PX6		190
+#define TEGRA_GPIO_PX7		191
+#define TEGRA_GPIO_PY0		192
+#define TEGRA_GPIO_PY1		193
+#define TEGRA_GPIO_PY2		194
+#define TEGRA_GPIO_PY3		195
+#define TEGRA_GPIO_PY4		196
+#define TEGRA_GPIO_PY5		197
+#define TEGRA_GPIO_PY6		198
+#define TEGRA_GPIO_PY7		199
+#define TEGRA_GPIO_PZ0		200
+#define TEGRA_GPIO_PZ1		201
+#define TEGRA_GPIO_PZ2		202
+#define TEGRA_GPIO_PZ3		203
+#define TEGRA_GPIO_PZ4		204
+#define TEGRA_GPIO_PZ5		205
+#define TEGRA_GPIO_PZ6		206
+#define TEGRA_GPIO_PZ7		207
+#define TEGRA_GPIO_PAA0		208
+#define TEGRA_GPIO_PAA1		209
+#define TEGRA_GPIO_PAA2		210
+#define TEGRA_GPIO_PAA3		211
+#define TEGRA_GPIO_PAA4		212
+#define TEGRA_GPIO_PAA5		213
+#define TEGRA_GPIO_PAA6		214
+#define TEGRA_GPIO_PAA7		215
+#define TEGRA_GPIO_PBB0		216
+#define TEGRA_GPIO_PBB1		217
+#define TEGRA_GPIO_PBB2		218
+#define TEGRA_GPIO_PBB3		219
+#define TEGRA_GPIO_PBB4		220
+#define TEGRA_GPIO_PBB5		221
+#define TEGRA_GPIO_PBB6		222
+#define TEGRA_GPIO_PBB7		223
+
+#endif
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
new file mode 100644
index 0000000..fe78fba
--- /dev/null
+++ b/arch/arm/mach-tegra/gpio.c
@@ -0,0 +1,348 @@
+/*
+ * arch/arm/mach-tegra/gpio.c
+ *
+ * Copyright (c) 2010 Google, Inc
+ *
+ * Author:
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/irq.h>
+
+#include <linux/io.h>
+#include <linux/gpio.h>
+
+#include <mach/iomap.h>
+
+#define GPIO_BANK(x)		((x) >> 5)
+#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
+#define GPIO_BIT(x)		((x) & 0x7)
+
+#define GPIO_REG(x)		(IO_TO_VIRT(TEGRA_GPIO_BASE) +	\
+				 GPIO_BANK(x) * 0x80 +		\
+				 GPIO_PORT(x) * 4)
+
+#define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
+#define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
+#define GPIO_OUT(x)		(GPIO_REG(x) + 0X20)
+#define GPIO_IN(x)		(GPIO_REG(x) + 0x30)
+#define GPIO_INT_STA(x)		(GPIO_REG(x) + 0x40)
+#define GPIO_INT_ENB(x)		(GPIO_REG(x) + 0x50)
+#define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
+#define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)
+
+#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + 0x800)
+#define GPIO_MSK_OE(x)		(GPIO_REG(x) + 0x810)
+#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + 0X820)
+#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + 0x840)
+#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + 0x850)
+#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + 0x860)
+
+#define GPIO_INT_LVL_MASK		0x010101
+#define GPIO_INT_LVL_EDGE_RISING	0x000101
+#define GPIO_INT_LVL_EDGE_FALLING	0x000100
+#define GPIO_INT_LVL_EDGE_BOTH		0x010100
+#define GPIO_INT_LVL_LEVEL_HIGH		0x000001
+#define GPIO_INT_LVL_LEVEL_LOW		0x000000
+
+struct tegra_gpio_bank {
+	int bank;
+	int irq;
+	spinlock_t lvl_lock[4];
+};
+
+
+static struct tegra_gpio_bank tegra_gpio_banks[] = {
+	{.bank = 0, .irq = INT_GPIO1},
+	{.bank = 1, .irq = INT_GPIO2},
+	{.bank = 2, .irq = INT_GPIO3},
+	{.bank = 3, .irq = INT_GPIO4},
+	{.bank = 4, .irq = INT_GPIO5},
+	{.bank = 5, .irq = INT_GPIO6},
+	{.bank = 6, .irq = INT_GPIO7},
+};
+
+static int tegra_gpio_compose(int bank, int port, int bit)
+{
+	return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
+}
+
+static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
+{
+	u32 val;
+
+	val = 0x100 << GPIO_BIT(gpio);
+	if (value)
+		val |= 1 << GPIO_BIT(gpio);
+	__raw_writel(val, reg);
+}
+
+void tegra_gpio_enable(int gpio)
+{
+	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
+}
+
+void tegra_gpio_disable(int gpio)
+{
+	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
+}
+
+static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
+{
+	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
+}
+
+static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+	return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
+}
+
+static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
+	return 0;
+}
+
+static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
+					int value)
+{
+	tegra_gpio_set(chip, offset, value);
+	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
+	return 0;
+}
+
+
+
+static struct gpio_chip tegra_gpio_chip = {
+	.label			= "tegra-gpio",
+	.direction_input	= tegra_gpio_direction_input,
+	.get			= tegra_gpio_get,
+	.direction_output	= tegra_gpio_direction_output,
+	.set			= tegra_gpio_set,
+	.base			= 0,
+	.ngpio			= ARCH_NR_GPIOS,
+};
+
+static void tegra_gpio_irq_ack(unsigned int irq)
+{
+	int gpio = irq - INT_GPIO_BASE;
+
+	__raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
+}
+
+static void tegra_gpio_irq_mask(unsigned int irq)
+{
+	int gpio = irq - INT_GPIO_BASE;
+
+	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
+}
+
+static void tegra_gpio_irq_unmask(unsigned int irq)
+{
+	int gpio = irq - INT_GPIO_BASE;
+
+	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
+}
+
+static int tegra_gpio_irq_set_type(unsigned int irq, unsigned int type)
+{
+	int gpio = irq - INT_GPIO_BASE;
+	struct tegra_gpio_bank *bank = get_irq_chip_data(irq);
+	int port = GPIO_PORT(gpio);
+	int lvl_type;
+	int val;
+	unsigned long flags;
+
+	switch (type & IRQ_TYPE_SENSE_MASK) {
+	case IRQ_TYPE_EDGE_RISING:
+		lvl_type = GPIO_INT_LVL_EDGE_RISING;
+		break;
+
+	case IRQ_TYPE_EDGE_FALLING:
+		lvl_type = GPIO_INT_LVL_EDGE_FALLING;
+		break;
+
+	case IRQ_TYPE_EDGE_BOTH:
+		lvl_type = GPIO_INT_LVL_EDGE_BOTH;
+		break;
+
+	case IRQ_TYPE_LEVEL_HIGH:
+		lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
+		break;
+
+	case IRQ_TYPE_LEVEL_LOW:
+		lvl_type = GPIO_INT_LVL_LEVEL_LOW;
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	spin_lock_irqsave(&bank->lvl_lock[port], flags);
+
+	val = __raw_readl(GPIO_INT_LVL(gpio));
+	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
+	val |= lvl_type << GPIO_BIT(gpio);
+	__raw_writel(val, GPIO_INT_LVL(gpio));
+
+	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
+
+	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
+		__set_irq_handler_unlocked(irq, handle_level_irq);
+	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
+		__set_irq_handler_unlocked(irq, handle_edge_irq);
+
+	return 0;
+}
+
+static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+	struct tegra_gpio_bank *bank;
+	int port;
+	int pin;
+	int unmasked = 0;
+
+	desc->chip->ack(irq);
+
+	bank = get_irq_data(irq);
+
+	for (port = 0; port < 4; port++) {
+		int gpio = tegra_gpio_compose(bank->bank, port, 0);
+		unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) &
+			__raw_readl(GPIO_INT_ENB(gpio));
+		u32 lvl = __raw_readl(GPIO_INT_LVL(gpio));
+
+		for_each_set_bit(pin, &sta, 8) {
+			__raw_writel(1 << pin, GPIO_INT_CLR(gpio));
+
+			/* if gpio is edge triggered, clear condition
+			 * before executing the hander so that we don't
+			 * miss edges
+			 */
+			if (lvl & (0x100 << pin)) {
+				unmasked = 1;
+				desc->chip->unmask(irq);
+			}
+
+			generic_handle_irq(gpio_to_irq(gpio + pin));
+		}
+	}
+
+	if (!unmasked)
+		desc->chip->unmask(irq);
+
+}
+
+
+static struct irq_chip tegra_gpio_irq_chip = {
+	.name		= "GPIO",
+	.ack		= tegra_gpio_irq_ack,
+	.mask		= tegra_gpio_irq_mask,
+	.unmask		= tegra_gpio_irq_unmask,
+	.set_type	= tegra_gpio_irq_set_type,
+};
+
+
+/* This lock class tells lockdep that GPIO irqs are in a different
+ * category than their parents, so it won't report false recursion.
+ */
+static struct lock_class_key gpio_lock_class;
+
+static int __init tegra_gpio_init(void)
+{
+	struct tegra_gpio_bank *bank;
+	int i;
+	int j;
+
+	for (i = 0; i < 7; i++) {
+		for (j = 0; j < 4; j++) {
+			int gpio = tegra_gpio_compose(i, j, 0);
+			__raw_writel(0x00, GPIO_INT_ENB(gpio));
+		}
+	}
+
+	gpiochip_add(&tegra_gpio_chip);
+
+	for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + ARCH_NR_GPIOS); i++) {
+		bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
+
+		lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class);
+		set_irq_chip_data(i, bank);
+		set_irq_chip(i, &tegra_gpio_irq_chip);
+		set_irq_handler(i, handle_simple_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
+		bank = &tegra_gpio_banks[i];
+
+		set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler);
+		set_irq_data(bank->irq, bank);
+
+		for (j = 0; j < 4; j++)
+			spin_lock_init(&bank->lvl_lock[j]);
+	}
+
+	return 0;
+}
+
+postcore_initcall(tegra_gpio_init);
+
+#ifdef	CONFIG_DEBUG_FS
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
+static int dbg_gpio_show(struct seq_file *s, void *unused)
+{
+	int i;
+	int j;
+
+	for (i = 0; i < 7; i++) {
+		for (j = 0; j < 4; j++) {
+			int gpio = tegra_gpio_compose(i, j, 0);
+			seq_printf(s, "%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
+			       i, j,
+			       __raw_readl(GPIO_CNF(gpio)),
+			       __raw_readl(GPIO_OE(gpio)),
+			       __raw_readl(GPIO_OUT(gpio)),
+			       __raw_readl(GPIO_IN(gpio)),
+			       __raw_readl(GPIO_INT_STA(gpio)),
+			       __raw_readl(GPIO_INT_ENB(gpio)),
+			       __raw_readl(GPIO_INT_LVL(gpio)));
+		}
+	}
+	return 0;
+}
+
+static int dbg_gpio_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, dbg_gpio_show, &inode->i_private);
+}
+
+static const struct file_operations debug_fops = {
+	.open		= dbg_gpio_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int __init tegra_gpio_debuginit(void)
+{
+	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
+					NULL, NULL, &debug_fops);
+	return 0;
+}
+late_initcall(tegra_gpio_debuginit);
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/gpio.h b/arch/arm/mach-tegra/include/mach/gpio.h
new file mode 100644
index 0000000..540e822
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/gpio.h
@@ -0,0 +1,53 @@
+/*
+ * arch/arm/mach-tegra/include/mach/gpio.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_GPIO_H
+#define __MACH_TEGRA_GPIO_H
+
+#include <mach/irqs.h>
+
+#define ARCH_NR_GPIOS		INT_GPIO_NR
+
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value		__gpio_get_value
+#define gpio_set_value		__gpio_set_value
+#define gpio_cansleep		__gpio_cansleep
+
+#define TEGRA_GPIO_TO_IRQ(gpio) (INT_GPIO_BASE + (gpio))
+#define TEGRA_IRQ_TO_GPIO(irq) ((gpio) - INT_GPIO_BASE)
+
+static inline int gpio_to_irq(unsigned int gpio)
+{
+	if (gpio < ARCH_NR_GPIOS)
+		return INT_GPIO_BASE + gpio;
+	return -EINVAL;
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+	if ((irq >= INT_GPIO_BASE) && (irq < INT_GPIO_BASE + INT_GPIO_NR))
+		return irq - INT_GPIO_BASE;
+	return -EINVAL;
+}
+
+void tegra_gpio_enable(int gpio);
+void tegra_gpio_disable(int gpio);
+
+#endif
-- 
1.6.5.6



From konkers at android.com  Mon Jun 14 17:10:26 2010
From: konkers at android.com (Erik Gilling)
Date: Mon, 14 Jun 2010 14:10:26 -0700
Subject: [PATCH v3 10/11] [ARM] tegra: Add framebuffer driver
In-Reply-To: <1276549827-2688-10-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
	<1276549827-2688-3-git-send-email-konkers@android.com>
	<1276549827-2688-4-git-send-email-konkers@android.com>
	<1276549827-2688-5-git-send-email-konkers@android.com>
	<1276549827-2688-6-git-send-email-konkers@android.com>
	<1276549827-2688-7-git-send-email-konkers@android.com>
	<1276549827-2688-8-git-send-email-konkers@android.com>
	<1276549827-2688-9-git-send-email-konkers@android.com>
	<1276549827-2688-10-git-send-email-konkers@android.com>
Message-ID: <1276549827-2688-11-git-send-email-konkers@android.com>

From: Colin Cross <ccross at android.com>

v2: Fixes from review by Russell King
    - Use proper return values

v2: Fixes from review by Jaya Kumar
    - Comments on lcd resolution
    - Remove stub functions
    - Change DUMP_REG to pr_debug
    - Add unregister_framebuffer to tegra_plat_remove

v2: from Colin Cross
    - adjust debugging

v3: Fixes from review by Jaya Kumar
        - Free irq in probe error case and remove function
	- Fix checkpatch issues

Signed-off-by: Colin Cross <ccross at android.com>
Signed-off-by: Erik Gilling <konkers at android.com>
CC: Jaya Kumar <jayakumar.lkml at gmail.com>
CC: linux-fbdev <linux-fbdev at vger.kernel.org>
---
 arch/arm/mach-tegra/include/mach/tegra_fb.h |   27 ++
 drivers/video/Kconfig                       |   10 +
 drivers/video/Makefile                      |    1 +
 drivers/video/tegrafb.c                     |  624 +++++++++++++++++++++++++++
 4 files changed, 662 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/include/mach/tegra_fb.h
 create mode 100644 drivers/video/tegrafb.c

diff --git a/arch/arm/mach-tegra/include/mach/tegra_fb.h b/arch/arm/mach-tegra/include/mach/tegra_fb.h
new file mode 100644
index 0000000..84ae886
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/tegra_fb.h
@@ -0,0 +1,27 @@
+/*
+ * arch/arm/mach-tegra/include/mach/tegra_fb.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Colin Cross <ccross at android.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+/* Platform data structure to be passed to the driver */
+struct tegra_fb_lcd_data {
+	int	fb_xres;
+	int	fb_yres;
+	/* Resolution of the output to the LCD.  If different from the
+	   framebuffer resolution, the Tegra display block will scale it */
+	int	lcd_xres;
+	int	lcd_yres;
+	int	bits_per_pixel;
+};
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 3d94a14..e047002 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1089,6 +1089,16 @@ config FB_RIVA_BACKLIGHT
 	help
 	  Say Y here if you want to control the backlight of your display.
 
+config FB_TEGRA
+	tristate "NVIDIA Tegra SoC display support"
+	depends on ARCH_TEGRA && FB = y
+	select FB_CFB_FILLRECT
+	select FB_CFB_COPYAREA
+	select FB_CFB_IMAGEBLIT
+	default FB
+	help
+	  This driver supports the NVIDIA Tegra systems-on-a-chip.
+
 config FB_I810
 	tristate "Intel 810/815 support (EXPERIMENTAL)"
 	depends on EXPERIMENTAL && FB && PCI && X86_32 && AGP_INTEL
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index ddc2af2..d9098d6 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -131,6 +131,7 @@ obj-$(CONFIG_FB_CARMINE)          += carminefb.o
 obj-$(CONFIG_FB_MB862XX)	  += mb862xx/
 obj-$(CONFIG_FB_MSM)              += msm/
 obj-$(CONFIG_FB_NUC900)           += nuc900fb.o
+obj-$(CONFIG_FB_TEGRA)            += tegrafb.o
 
 # Platform or fallback drivers go here
 obj-$(CONFIG_FB_UVESA)            += uvesafb.o
diff --git a/drivers/video/tegrafb.c b/drivers/video/tegrafb.c
new file mode 100644
index 0000000..47b2d42
--- /dev/null
+++ b/drivers/video/tegrafb.c
@@ -0,0 +1,624 @@
+/*
+ * drivers/video/tegrafb.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Author: Colin Cross <ccross at android.com>
+ *         Travis Geiselbrecht <travis at palm.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/fb.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/clk.h>
+#include <linux/wait.h>
+#include <asm/cacheflush.h>
+#include <mach/tegra_fb.h>
+
+#define DC_CMD_GENERAL_INCR_SYNCPT		0x000
+#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL	0x001
+#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR	0x002
+#define DC_CMD_WIN_A_INCR_SYNCPT		0x008
+#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL		0x009
+#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR		0x00a
+#define DC_CMD_WIN_B_INCR_SYNCPT		0x010
+#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL		0x011
+#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR		0x012
+#define DC_CMD_WIN_C_INCR_SYNCPT		0x018
+#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL		0x019
+#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR		0x01a
+#define DC_CMD_CONT_SYNCPT_VSYNC		0x028
+#define DC_CMD_DISPLAY_COMMAND_OPTION0		0x031
+#define DC_CMD_DISPLAY_COMMAND			0x032
+#define DC_CMD_SIGNAL_RAISE			0x033
+#define DC_CMD_INT_STATUS			0x037
+#define DC_CMD_INT_MASK				0x038
+#define DC_CMD_INT_ENABLE			0x039
+#define DC_CMD_INT_TYPE				0x03a
+#define DC_CMD_INT_POLARITY			0x03b
+#define DC_CMD_SIGNAL_RAISE1			0x03c
+#define DC_CMD_SIGNAL_RAISE2			0x03d
+#define DC_CMD_SIGNAL_RAISE3			0x03e
+#define DC_CMD_STATE_ACCESS			0x040
+#define DC_CMD_STATE_CONTROL			0x041
+#define DC_CMD_DISPLAY_WINDOW_HEADER		0x042
+#define DC_CMD_REG_ACT_CONTROL			0x043
+#define DC_WINC_A_COLOR_PALETTE			0x500
+#define DC_WINC_A_PALETTE_COLOR_EXT		0x600
+#define DC_WIN_A_WIN_OPTIONS			0x700
+#define DC_WIN_A_BYTE_SWAP			0x701
+#define DC_WIN_A_BUFFER_CONTROL			0x702
+#define DC_WIN_A_COLOR_DEPTH			0x703
+#define DC_WIN_A_POSITION			0x704
+#define DC_WIN_A_SIZE				0x705
+#define DC_WIN_A_PRESCALED_SIZE			0x706
+#define DC_WIN_A_H_INITIAL_DDA			0x707
+#define DC_WIN_A_V_INITIAL_DDA			0x708
+#define DC_WIN_A_DDA_INCREMENT			0x709
+#define DC_WIN_A_LINE_STRIDE			0x70a
+#define DC_WIN_A_BUF_STRIDE			0x70b
+#define DC_WINBUF_A_START_ADDR			0x800
+#define DC_WINBUF_A_ADDR_H_OFFSET		0x806
+#define DC_WINBUF_A_ADDR_V_OFFSET		0x808
+
+
+#define DC_INT_CTXSW				(1<<0)
+#define DC_INT_FRAME_END			(1<<1)
+#define DC_INT_V_BLANK				(1<<2)
+#define DC_INT_H_BLANK				(1<<3)
+#define DC_INT_V_PULSE3				(1<<4)
+
+#define DC_COLOR_DEPTH_P1			0
+#define DC_COLOR_DEPTH_P2			1
+#define DC_COLOR_DEPTH_P4			2
+#define DC_COLOR_DEPTH_P8			3
+#define DC_COLOR_DEPTH_B4G4R4A4			4
+#define DC_COLOR_DEPTH_B5G5R5A			5
+#define DC_COLOR_DEPTH_B5G6R5			6
+#define DC_COLOR_DEPTH_AB5G5R5			7
+#define DC_COLOR_DEPTH_B8G8R8A8			12
+#define DC_COLOR_DEPTH_R8G8B8A8			13
+#define DC_COLOR_DEPTH_B6x2G6x2R6x2A8		14
+#define DC_COLOR_DEPTH_R6x2G6x2B6x2A8		15
+#define DC_COLOR_DEPTH_YCbCr422			16
+#define DC_COLOR_DEPTH_YUV422			17
+#define DC_COLOR_DEPTH_YCbCr420P		18
+#define DC_COLOR_DEPTH_YUV420P			19
+#define DC_COLOR_DEPTH_YCbCr422P		20
+#define DC_COLOR_DEPTH_YUV422P			21
+#define DC_COLOR_DEPTH_YCbCr422R		22
+#define DC_COLOR_DEPTH_YUV422R			23
+#define DC_COLOR_DEPTH_YCbCr422RA		24
+#define DC_COLOR_DEPTH_YUV422RA			25
+
+struct tegra_fb_info {
+	struct clk *clk;
+	struct resource *reg_mem;
+	struct resource *fb_mem;
+	void __iomem *reg_base;
+	wait_queue_head_t event_wq;
+	unsigned int wait_condition;
+	/* Resolution of the output to the LCD.  If different from the
+	   framebuffer resolution, the Tegra display block will scale it */
+	int lcd_xres;
+	int lcd_yres;
+	int irq;
+};
+
+static void tegra_fb_writel(struct tegra_fb_info *tegra_fb, u32 val,
+	unsigned long reg)
+{
+	writel(val, tegra_fb->reg_base + reg*sizeof(u32));
+}
+
+static u32 tegra_fb_readl(struct tegra_fb_info *tegra_fb, unsigned long reg)
+{
+	return readl(tegra_fb->reg_base + reg*sizeof(u32));
+}
+
+/* palette attary used by the fbcon */
+u32 pseudo_palette[16];
+
+irqreturn_t tegra_fb_irq(int irq, void *ptr)
+{
+	struct fb_info *info = ptr;
+	struct tegra_fb_info *tegra_fb = info->par;
+
+	u32 reg = tegra_fb_readl(tegra_fb, DC_CMD_INT_STATUS);
+	tegra_fb_writel(tegra_fb, reg, DC_CMD_INT_STATUS);
+
+	tegra_fb->wait_condition = 1;
+	wake_up(&tegra_fb->event_wq);
+	return IRQ_HANDLED;
+}
+
+static int tegra_fb_wait_for_event(struct tegra_fb_info *tegra_fb,
+	unsigned long timeout, u32 irq_mask)
+{
+	u32 reg;
+
+	tegra_fb->wait_condition = 0;
+
+	reg = tegra_fb_readl(tegra_fb, DC_CMD_INT_MASK);
+	reg |= irq_mask;
+	tegra_fb_writel(tegra_fb, reg, DC_CMD_INT_MASK);
+
+	/* Clear any pending interrupt */
+	tegra_fb_writel(tegra_fb, irq_mask, DC_CMD_INT_STATUS);
+
+	tegra_fb_writel(tegra_fb, irq_mask, DC_CMD_INT_ENABLE);
+
+	/* Wait for the irq to fire */
+	wait_event_interruptible_timeout(tegra_fb->event_wq,
+		tegra_fb->wait_condition, timeout);
+
+	tegra_fb_writel(tegra_fb, 0, DC_CMD_INT_ENABLE);
+
+	if (!tegra_fb->wait_condition) {
+		pr_warning("%s: wait for vsync timed out\n", __func__);
+		return -ETIMEDOUT;
+	}
+	return 0;
+}
+
+/* Writes to many registers in the display block are buffered.
+ * tegra_fb_activate requests an update of the main registers from their
+ * double-buffered registers, which takes effect at the end of the next frame,
+ * and then waits for the frame_end IRQ.
+ */
+static void tegra_fb_activate(struct tegra_fb_info *tegra_fb)
+{
+	int vsync_count = 0;
+
+	if (unlikely(tegra_fb_readl(tegra_fb, DC_CMD_STATE_CONTROL) & 3)) {
+		pr_warning("%s: update already activated!\n", __func__);
+		return;
+	}
+
+	tegra_fb_writel(tegra_fb, (1 << 8) | (1 << 9), DC_CMD_STATE_CONTROL);
+	tegra_fb_writel(tegra_fb, (1 << 0) | (1 << 1), DC_CMD_STATE_CONTROL);
+	while (tegra_fb_readl(tegra_fb, DC_CMD_STATE_CONTROL) & 3) {
+		vsync_count++;
+		if (tegra_fb_wait_for_event(tegra_fb, HZ/10, DC_INT_FRAME_END))
+			break;
+	}
+	if (unlikely(vsync_count > 1))
+		pr_warning("%s: waited for %d vsyncs\n", __func__, vsync_count);
+}
+
+
+static int tegra_fb_open(struct fb_info *info, int user)
+{
+	return 0;
+}
+
+static int tegra_fb_release(struct fb_info *info, int user)
+{
+	return 0;
+}
+
+static int tegra_fb_check_var(struct fb_var_screeninfo *var,
+	struct fb_info *info)
+{
+	if ((var->xres != info->var.xres) ||
+	    (var->yres != info->var.yres) ||
+	    (var->xres_virtual != info->var.xres_virtual) ||
+	    (var->yres_virtual != info->var.yres_virtual) ||
+	    (var->grayscale != info->var.grayscale))
+		return -EINVAL;
+	return 0;
+}
+
+static int tegra_fb_set_par(struct fb_info *info)
+{
+	struct tegra_fb_info *tegra_fb = info->par;
+	struct fb_var_screeninfo *var = &info->var;
+	struct fb_fix_screeninfo *fix = &info->fix;
+	u32 color_depth;
+	unsigned int h_dda;
+	unsigned int v_dda;
+
+	/* we only support RGB ordering for now */
+	switch (var->bits_per_pixel) {
+	case 32:
+	case 24:
+		var->red.offset = 0;
+		var->red.length = 8;
+		var->green.offset = 8;
+		var->green.length = 8;
+		var->blue.offset = 16;
+		var->blue.length = 8;
+		color_depth = DC_COLOR_DEPTH_B8G8R8A8;
+		break;
+	case 16:
+		var->red.offset = 11;
+		var->red.length = 5;
+		var->green.offset = 5;
+		var->green.length = 6;
+		var->blue.offset = 0;
+		var->blue.length = 5;
+		color_depth = DC_COLOR_DEPTH_B5G6R5;
+		break;
+	default:
+		return -EINVAL;
+	}
+	fix->line_length = var->xres * var->bits_per_pixel / 8;
+
+	h_dda = (var->xres * 0x1000) / (tegra_fb->lcd_xres - 1);
+	v_dda = (var->yres * 0x1000) / (tegra_fb->lcd_yres - 1);
+
+	tegra_fb_writel(tegra_fb, tegra_fb->lcd_yres<<16 | tegra_fb->lcd_xres,
+		DC_WIN_A_SIZE);
+	tegra_fb_writel(tegra_fb, var->yres<<16 | fix->line_length,
+		DC_WIN_A_PRESCALED_SIZE);
+	tegra_fb_writel(tegra_fb, 0, DC_WIN_A_H_INITIAL_DDA);
+	tegra_fb_writel(tegra_fb, 0, DC_WIN_A_V_INITIAL_DDA);
+	tegra_fb_writel(tegra_fb, v_dda << 16 | h_dda, DC_WIN_A_DDA_INCREMENT);
+	tegra_fb_writel(tegra_fb, color_depth, DC_WIN_A_COLOR_DEPTH);
+	tegra_fb_writel(tegra_fb, fix->line_length, DC_WIN_A_LINE_STRIDE);
+	return 0;
+}
+
+static int tegra_fb_setcolreg(unsigned regno, unsigned red, unsigned green,
+	unsigned blue, unsigned transp, struct fb_info *info)
+{
+	struct fb_var_screeninfo *var = &info->var;
+
+	if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
+	    info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
+		u32 v;
+
+		if (regno >= 16)
+			return -EINVAL;
+
+		v = (red << var->red.offset) |
+			(green << var->green.offset) |
+			(blue << var->blue.offset);
+
+		((u32 *)info->pseudo_palette)[regno] = v;
+	}
+
+	return 0;
+}
+
+static int tegra_fb_pan_display(struct fb_var_screeninfo *var,
+	struct fb_info *info)
+{
+	struct tegra_fb_info *tegra_fb = info->par;
+	char __iomem *flush_start;
+	char __iomem *flush_end;
+	u32 addr;
+
+	flush_start = info->screen_base + (var->yoffset * info->fix.line_length);
+	flush_end = flush_start + (var->yres * info->fix.line_length);
+
+	info->var.xoffset = var->xoffset;
+	info->var.yoffset = var->yoffset;
+
+	addr = info->fix.smem_start + (var->yoffset * info->fix.line_length) +
+		(var->xoffset * (var->bits_per_pixel/8));
+
+	tegra_fb_writel(tegra_fb, addr, DC_WINBUF_A_START_ADDR);
+	tegra_fb_activate(tegra_fb);
+	return 0;
+}
+
+static void tegra_fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
+{
+	cfb_fillrect(info, rect);
+}
+
+static void tegra_fb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
+{
+	cfb_copyarea(info, region);
+}
+
+static void tegra_fb_imageblit(struct fb_info *info, const struct fb_image *image)
+{
+	cfb_imageblit(info, image);
+}
+
+#ifdef DEBUG
+#define DUMP_REG(a) dev_dbg(info->dev, "%-32s\t%03x\t%08x\n", #a, a, tegra_fb_readl(tegra_fb, a));
+static void dump_regs(struct fb_info *info)
+{
+	struct tegra_fb_info *tegra_fb = info->par;
+
+	DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
+	DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
+	DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
+	DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
+	DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
+	DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
+	DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
+	DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
+	DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
+	DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
+	DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
+	DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
+	DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
+	DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
+	DUMP_REG(DC_CMD_DISPLAY_COMMAND);
+	DUMP_REG(DC_CMD_SIGNAL_RAISE);
+	DUMP_REG(DC_CMD_INT_STATUS);
+	DUMP_REG(DC_CMD_INT_MASK);
+	DUMP_REG(DC_CMD_INT_ENABLE);
+	DUMP_REG(DC_CMD_INT_TYPE);
+	DUMP_REG(DC_CMD_INT_POLARITY);
+	DUMP_REG(DC_CMD_SIGNAL_RAISE1);
+	DUMP_REG(DC_CMD_SIGNAL_RAISE2);
+	DUMP_REG(DC_CMD_SIGNAL_RAISE3);
+	DUMP_REG(DC_CMD_STATE_ACCESS);
+	DUMP_REG(DC_CMD_STATE_CONTROL);
+	DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
+	DUMP_REG(DC_CMD_REG_ACT_CONTROL);
+	tegra_fb_writel(tegra_fb, 1<<4, DC_CMD_DISPLAY_WINDOW_HEADER);
+	DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
+	DUMP_REG(DC_WINC_A_COLOR_PALETTE);
+	DUMP_REG(DC_WINC_A_PALETTE_COLOR_EXT);
+	DUMP_REG(DC_WIN_A_WIN_OPTIONS);
+	DUMP_REG(DC_WIN_A_BYTE_SWAP);
+	DUMP_REG(DC_WIN_A_BUFFER_CONTROL);
+	DUMP_REG(DC_WIN_A_COLOR_DEPTH);
+	DUMP_REG(DC_WIN_A_POSITION);
+	DUMP_REG(DC_WIN_A_SIZE);
+	DUMP_REG(DC_WIN_A_PRESCALED_SIZE);
+	DUMP_REG(DC_WIN_A_H_INITIAL_DDA);
+	DUMP_REG(DC_WIN_A_V_INITIAL_DDA);
+	DUMP_REG(DC_WIN_A_DDA_INCREMENT);
+	DUMP_REG(DC_WIN_A_LINE_STRIDE);
+	DUMP_REG(DC_WIN_A_BUF_STRIDE);
+	DUMP_REG(DC_WINBUF_A_START_ADDR);
+	DUMP_REG(DC_WINBUF_A_ADDR_H_OFFSET);
+	DUMP_REG(DC_WINBUF_A_ADDR_V_OFFSET);
+}
+#endif
+
+static struct fb_ops tegra_fb_ops = {
+	.owner = THIS_MODULE,
+	.fb_open = tegra_fb_open,
+	.fb_release = tegra_fb_release,
+	.fb_check_var = tegra_fb_check_var,
+	.fb_set_par = tegra_fb_set_par,
+	.fb_setcolreg = tegra_fb_setcolreg,
+	.fb_pan_display = tegra_fb_pan_display,
+	.fb_fillrect = tegra_fb_fillrect,
+	.fb_copyarea = tegra_fb_copyarea,
+	.fb_imageblit = tegra_fb_imageblit,
+};
+
+static int tegra_plat_probe(struct platform_device *pdev)
+{
+	struct fb_info *info;
+	struct tegra_fb_info *tegra_fb;
+	struct clk *clk;
+	struct resource	*res;
+	struct resource *reg_mem;
+	struct resource *fb_mem;
+	int ret = 0;
+	void __iomem *reg_base;
+	void __iomem *fb_base;
+	unsigned long fb_size;
+	unsigned long fb_phys;
+	int irq;
+	const struct tegra_fb_lcd_data *lcd_data = pdev->dev.platform_data;
+
+	info = framebuffer_alloc(sizeof(struct tegra_fb_info), &pdev->dev);
+	if (!info) {
+		ret = -ENOMEM;
+		goto err;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq <= 0) {
+		dev_err(&pdev->dev, "%s: no irq\n", pdev->name);
+		ret = -ENOENT;
+		goto err_free;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "%s: no mem resource\n", pdev->name);
+		ret = -ENOENT;
+		goto err_free;
+	}
+
+	reg_mem = request_mem_region(res->start, resource_size(res), pdev->name);
+	if (!reg_mem) {
+		dev_err(&pdev->dev, "%s: request_mem_region failed\n", pdev->name);
+		ret = -EBUSY;
+		goto err_free;
+	}
+
+	reg_base = ioremap(res->start, resource_size(res));
+	if (!reg_base) {
+		dev_err(&pdev->dev, "%s: registers can't be mapped\n", pdev->name);
+		ret = -EBUSY;
+		goto err_release_resource_reg;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+	if (!res) {
+		dev_err(&pdev->dev, "%s: no mem resource\n", pdev->name);
+		ret = -ENOENT;
+		goto err_iounmap_reg;
+	}
+
+	fb_mem = request_mem_region(res->start, resource_size(res), pdev->name);
+	if (!fb_mem) {
+		dev_err(&pdev->dev, "%s: request_mem_region failed\n", pdev->name);
+		ret = -EBUSY;
+		goto err_iounmap_reg;
+	}
+
+	fb_size = resource_size(res);
+	fb_phys = res->start;
+	fb_base = ioremap_nocache(fb_phys, fb_size);
+	if (!fb_base) {
+		dev_err(&pdev->dev, "%s: fb can't be mapped\n", pdev->name);
+		ret = -EBUSY;
+		goto err_release_resource_fb;
+	}
+
+	clk = clk_get(&pdev->dev, NULL);
+	if (!clk) {
+		dev_err(&pdev->dev, "%s: can't get clock\n", pdev->name);
+		ret = -ENOENT;
+		goto err_iounmap_fb;
+	}
+	clk_enable(clk);
+
+	tegra_fb = info->par;
+	tegra_fb->clk = clk;
+	tegra_fb->fb_mem = fb_mem;
+	tegra_fb->reg_mem = reg_mem;
+	tegra_fb->reg_base = reg_base;
+	tegra_fb->irq = irq;
+	tegra_fb->lcd_xres = lcd_data->lcd_xres;
+	tegra_fb->lcd_yres = lcd_data->lcd_yres;
+
+	info->fbops = &tegra_fb_ops;
+	info->pseudo_palette = pseudo_palette;
+	info->screen_base = fb_base;
+	info->screen_size = fb_size;
+
+	strlcpy(info->fix.id, "tegra_fb", sizeof(info->fix.id));
+	info->fix.type = FB_TYPE_PACKED_PIXELS;
+	info->fix.visual = FB_VISUAL_TRUECOLOR;
+	info->fix.xpanstep   = 1;
+	info->fix.ypanstep   = 1;
+	info->fix.accel	  = FB_ACCEL_NONE;
+	info->fix.smem_start = fb_phys;
+	info->fix.smem_len = fb_size;
+
+	info->var.xres			= lcd_data->fb_xres;
+	info->var.yres			= lcd_data->fb_yres;
+	info->var.xres_virtual		= lcd_data->fb_xres;
+	info->var.yres_virtual		= lcd_data->fb_yres*2;
+	info->var.bits_per_pixel	= lcd_data->bits_per_pixel;
+	info->var.activate		= FB_ACTIVATE_NOW;
+	info->var.height		= -1;
+	info->var.width			= -1;
+	info->var.pixclock		= 24500;
+	info->var.left_margin		= 0;
+	info->var.right_margin		= 0;
+	info->var.upper_margin		= 0;
+	info->var.lower_margin		= 0;
+	info->var.hsync_len		= 0;
+	info->var.vsync_len		= 0;
+	info->var.vmode			= FB_VMODE_NONINTERLACED;
+
+	if (request_irq(irq, tegra_fb_irq, IRQF_DISABLED,
+			dev_name(&pdev->dev), info)) {
+		pr_debug("%s: request_irq %d failed\n",
+			pdev->name, irq);
+		ret = -EBUSY;
+		goto err_clk_disable;
+	}
+
+	init_waitqueue_head(&tegra_fb->event_wq);
+
+	/* Enable writes to Window A */
+	tegra_fb_writel(tegra_fb, 1<<4, DC_CMD_DISPLAY_WINDOW_HEADER);
+
+#ifdef DEBUG
+	info->dev = &pdev->dev;
+	dev_dbg(info->dev, "Framebuffer registers before init:\n");
+	dump_regs(info);
+#endif
+
+	tegra_fb_set_par(info);
+
+#ifdef DEBUG
+	dev_dbg(info->dev, "Framebuffer registers after init:\n");
+	dump_regs(info);
+#endif
+
+	dev_info(&pdev->dev, "base address: %08x (%08x)\n",
+			(unsigned int)info->fix.smem_start,
+			(unsigned int)info->screen_base);
+
+	if (register_framebuffer(info)) {
+		dev_err(&pdev->dev, "failed to register framebuffer\n");
+		ret = -ENODEV;
+		goto err_free_irq;
+	}
+	platform_set_drvdata(pdev, info);
+	return 0;
+
+err_free_irq:
+	free_irq(irq, info);
+err_clk_disable:
+	clk_disable(clk);
+err_iounmap_fb:
+	iounmap(fb_base);
+err_release_resource_fb:
+	release_resource(fb_mem);
+err_iounmap_reg:
+	iounmap(reg_base);
+err_release_resource_reg:
+	release_resource(reg_mem);
+err_free:
+	framebuffer_release(info);
+err:
+	return ret;
+}
+
+static int tegra_plat_remove(struct platform_device *pdev)
+{
+	struct fb_info *info = platform_get_drvdata(pdev);
+	struct tegra_fb_info *tegra_fb = info->par;
+	unregister_framebuffer(info);
+	free_irq(tegra_fb->irq, info);
+	clk_disable(tegra_fb->clk);
+	iounmap(info->screen_base);
+	release_resource(tegra_fb->fb_mem);
+	iounmap(tegra_fb->reg_base);
+	release_resource(tegra_fb->reg_mem);
+	framebuffer_release(info);
+	return 0;
+}
+
+struct platform_driver tegra_platform_driver = {
+	.probe = tegra_plat_probe,
+	.remove = tegra_plat_remove,
+	.driver = {
+		.name = "tegrafb",
+		.owner = THIS_MODULE,
+	},
+};
+
+static int __init tegra_fb_init(void)
+{
+	int e;
+	e = platform_driver_register(&tegra_platform_driver);
+	if (e) {
+		pr_info("tegrafb: platform_driver_register failed\n");
+		return e;
+	}
+	return e;
+}
+
+static void __exit tegra_exit(void)
+{
+	platform_driver_unregister(&tegra_platform_driver);
+}
+
+module_exit(tegra_exit);
+module_init(tegra_fb_init);
-- 
1.6.5.6



From konkers at android.com  Mon Jun 14 17:10:19 2010
From: konkers at android.com (Erik Gilling)
Date: Mon, 14 Jun 2010 14:10:19 -0700
Subject: [PATCH v3 03/11] [ARM] tegra: Add clock support
In-Reply-To: <1276549827-2688-3-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
	<1276549827-2688-3-git-send-email-konkers@android.com>
Message-ID: <1276549827-2688-4-git-send-email-konkers@android.com>

From: Colin Cross <ccross at android.com>

v2: fixes from Russell King:
	- include linux/io.h instead of asm/io.h
	- fix whitespace in Kconfig
	- Use spin_lock_init to initialize lock
	- Return -ENOSYS instead of BUG for unimplemented clock ops
	- Use proper return values in tegra2 clock ops
    additional changes:
	- Rename some clocks to match dev_ids
	- add rate propagation
	- add debugfs entries
	- add support for clock listed in clk_lookup under multiple dev_ids
v3:
	- Replace per-clock locking with global clock lock
	- Autodetect clock state on init
	- Let clock dividers pick next lower possible frequency
	- Add support for clock init tables
	- Minor bug fixes
	- Fix checkpatch issues

Signed-off-by: Colin Cross <ccross at android.com>
---
 arch/arm/Kconfig                          |    1 +
 arch/arm/mach-tegra/Makefile              |    2 +
 arch/arm/mach-tegra/clock.c               |  488 +++++++++++
 arch/arm/mach-tegra/clock.h               |  147 ++++
 arch/arm/mach-tegra/common.c              |   17 +
 arch/arm/mach-tegra/include/mach/clk.h    |   26 +
 arch/arm/mach-tegra/include/mach/clkdev.h |   32 +
 arch/arm/mach-tegra/tegra2_clocks.c       | 1359 +++++++++++++++++++++++++++++
 8 files changed, 2072 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-tegra/clock.c
 create mode 100644 arch/arm/mach-tegra/clock.h
 create mode 100644 arch/arm/mach-tegra/include/mach/clk.h
 create mode 100644 arch/arm/mach-tegra/include/mach/clkdev.h
 create mode 100644 arch/arm/mach-tegra/tegra2_clocks.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 626a3cb..98e41e1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -567,6 +567,7 @@ config ARCH_TEGRA
 	select GENERIC_CLOCKEVENTS
 	select GENERIC_GPIO
 	select HAVE_CLK
+	select COMMON_CLKDEV
 	select ARCH_HAS_BARRIERS if CACHE_L2X0
 	help
 	  This enables support for NVIDIA Tegra based systems (Tegra APX,
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index a0d2c5b..e20546a 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,3 +1,5 @@
 obj-y                                   += common.o
 obj-y                                   += io.o
 obj-y                                   += irq.o
+obj-y                                   += clock.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
new file mode 100644
index 0000000..03ad578
--- /dev/null
+++ b/arch/arm/mach-tegra/clock.c
@@ -0,0 +1,488 @@
+/*
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/list.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/slab.h>
+#include <linux/seq_file.h>
+#include <asm/clkdev.h>
+
+#include "clock.h"
+
+static LIST_HEAD(clocks);
+
+static DEFINE_SPINLOCK(clock_lock);
+
+struct clk *tegra_get_clock_by_name(const char *name)
+{
+	struct clk *c;
+	struct clk *ret = NULL;
+	unsigned long flags;
+	spin_lock_irqsave(&clock_lock, flags);
+	list_for_each_entry(c, &clocks, node) {
+		if (strcmp(c->name, name) == 0) {
+			ret = c;
+			break;
+		}
+	}
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return ret;
+}
+
+int clk_reparent(struct clk *c, struct clk *parent)
+{
+	pr_debug("%s: %s\n", __func__, c->name);
+	if (c->refcnt && c->parent)
+		clk_disable_locked(c->parent);
+	c->parent = parent;
+	if (c->refcnt && c->parent)
+		clk_enable_locked(c->parent);
+	list_del(&c->sibling);
+	list_add_tail(&c->sibling, &parent->children);
+	return 0;
+}
+
+static void propagate_rate(struct clk *c)
+{
+	struct clk *clkp;
+	pr_debug("%s: %s\n", __func__, c->name);
+	list_for_each_entry(clkp, &c->children, sibling) {
+		pr_debug("   %s\n", clkp->name);
+		if (clkp->ops->recalculate_rate)
+			clkp->ops->recalculate_rate(clkp);
+		propagate_rate(clkp);
+	}
+}
+
+void clk_init(struct clk *c)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&clock_lock, flags);
+
+	INIT_LIST_HEAD(&c->children);
+	INIT_LIST_HEAD(&c->sibling);
+
+	if (c->ops && c->ops->init)
+		c->ops->init(c);
+
+	list_add(&c->node, &clocks);
+
+	if (c->parent)
+		list_add_tail(&c->sibling, &c->parent->children);
+
+	spin_unlock_irqrestore(&clock_lock, flags);
+}
+
+int clk_enable_locked(struct clk *c)
+{
+	int ret;
+	pr_debug("%s: %s\n", __func__, c->name);
+	if (c->refcnt == 0) {
+		if (c->parent) {
+			ret = clk_enable_locked(c->parent);
+			if (ret)
+				return ret;
+		}
+
+		if (c->ops && c->ops->enable) {
+			ret = c->ops->enable(c);
+			if (ret) {
+				if (c->parent)
+					clk_disable_locked(c->parent);
+				return ret;
+			}
+			c->state = ON;
+#ifdef CONFIG_DEBUG_FS
+			c->set = 1;
+#endif
+		}
+	}
+	c->refcnt++;
+
+	return 0;
+}
+
+int clk_enable(struct clk *c)
+{
+	int ret;
+	unsigned long flags;
+	spin_lock_irqsave(&clock_lock, flags);
+	ret = clk_enable_locked(c);
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable_locked(struct clk *c)
+{
+	pr_debug("%s: %s\n", __func__, c->name);
+	if (c->refcnt == 0) {
+		WARN(1, "Attempting to disable clock %s with refcnt 0", c->name);
+		return;
+	}
+	if (c->refcnt == 1) {
+		if (c->ops && c->ops->disable)
+			c->ops->disable(c);
+
+		if (c->parent)
+			clk_disable_locked(c->parent);
+
+		c->state = OFF;
+	}
+	c->refcnt--;
+}
+
+void clk_disable(struct clk *c)
+{
+	unsigned long flags;
+	spin_lock_irqsave(&clock_lock, flags);
+	clk_disable_locked(c);
+	spin_unlock_irqrestore(&clock_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+
+int clk_set_parent_locked(struct clk *c, struct clk *parent)
+{
+	int ret;
+
+	pr_debug("%s: %s\n", __func__, c->name);
+
+	if (!c->ops || !c->ops->set_parent)
+		return -ENOSYS;
+
+	ret = c->ops->set_parent(c, parent);
+
+	if (ret)
+		return ret;
+
+	propagate_rate(c);
+
+	return 0;
+}
+
+int clk_set_parent(struct clk *c, struct clk *parent)
+{
+	int ret;
+	unsigned long flags;
+	spin_lock_irqsave(&clock_lock, flags);
+	ret = clk_set_parent_locked(c, parent);
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *c)
+{
+	return c->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+int clk_set_rate(struct clk *c, unsigned long rate)
+{
+	int ret = 0;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clock_lock, flags);
+
+	pr_debug("%s: %s\n", __func__, c->name);
+
+	if (c->ops && c->ops->set_rate)
+		ret = c->ops->set_rate(c, rate);
+	else
+		ret = -ENOSYS;
+
+	propagate_rate(c);
+
+	spin_unlock_irqrestore(&clock_lock, flags);
+
+	return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+unsigned long clk_get_rate(struct clk *c)
+{
+	unsigned long flags;
+	unsigned long ret;
+
+	spin_lock_irqsave(&clock_lock, flags);
+
+	pr_debug("%s: %s\n", __func__, c->name);
+
+	ret = c->rate;
+
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return ret;
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
+{
+	struct clk *c;
+	struct clk *p;
+
+	int ret = 0;
+
+	c = tegra_get_clock_by_name(table->name);
+
+	if (!c) {
+		pr_warning("Unable to initialize clock %s\n",
+			table->name);
+		return -ENODEV;
+	}
+
+	if (table->parent) {
+		p = tegra_get_clock_by_name(table->parent);
+		if (!p) {
+			pr_warning("Unable to find parent %s of clock %s\n",
+				table->parent, table->name);
+			return -ENODEV;
+		}
+
+		if (c->parent != p) {
+			ret = clk_set_parent(c, p);
+			if (ret) {
+				pr_warning("Unable to set parent %s of clock %s: %d\n",
+					table->parent, table->name, ret);
+				return -EINVAL;
+			}
+		}
+	}
+
+	if (table->rate && table->rate != clk_get_rate(c)) {
+		ret = clk_set_rate(c, table->rate);
+		if (ret) {
+			pr_warning("Unable to set clock %s to rate %lu: %d\n",
+				table->name, table->rate, ret);
+			return -EINVAL;
+		}
+	}
+
+	if (table->enabled) {
+		ret = clk_enable(c);
+		if (ret) {
+			pr_warning("Unable to enable clock %s: %d\n",
+				table->name, ret);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+void tegra_clk_init_from_table(struct tegra_clk_init_table *table)
+{
+	for (; table->name; table++)
+		tegra_clk_init_one_from_table(table);
+}
+EXPORT_SYMBOL(tegra_clk_init_from_table);
+
+void tegra_periph_reset_deassert(struct clk *c)
+{
+	tegra2_periph_reset_deassert(c);
+}
+EXPORT_SYMBOL(tegra_periph_reset_deassert);
+
+void tegra_periph_reset_assert(struct clk *c)
+{
+	tegra2_periph_reset_assert(c);
+}
+EXPORT_SYMBOL(tegra_periph_reset_assert);
+
+int __init tegra_init_clock(void)
+{
+	tegra2_init_clocks();
+
+	return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+static struct dentry *clk_debugfs_root;
+
+
+static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
+{
+	struct clk *child;
+	struct clk *safe;
+	const char *state = "uninit";
+	char div[5] = {0};
+
+	if (c->state == ON)
+		state = "on";
+	else if (c->state == OFF)
+		state = "off";
+
+	if (c->mul != 0 && c->div != 0) {
+		BUG_ON(c->mul > 2);
+		if (c->mul > c->div)
+			snprintf(div, sizeof(div), "x%d", c->mul / c->div);
+		else
+			snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
+				(c->div % c->mul) ? ".5" : "");
+	}
+
+	seq_printf(s, "%*s%-*s %-6s %-3d %-5s %-10lu\n",
+		level * 3 + 1, c->set ? "" : "*",
+		30 - level * 3, c->name,
+		state, c->refcnt, div, c->rate);
+	list_for_each_entry_safe(child, safe, &c->children, sibling) {
+		clock_tree_show_one(s, child, level + 1);
+	}
+}
+
+static int clock_tree_show(struct seq_file *s, void *data)
+{
+	struct clk *c;
+	unsigned long flags;
+	seq_printf(s, " clock                          state  ref div   rate      \n");
+	seq_printf(s, "-----------------------------------------------------------\n");
+	spin_lock_irqsave(&clock_lock, flags);
+	list_for_each_entry(c, &clocks, node)
+		if (c->parent == NULL)
+			clock_tree_show_one(s, c, 0);
+	spin_unlock_irqrestore(&clock_lock, flags);
+	return 0;
+}
+
+static int clock_tree_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, clock_tree_show, inode->i_private);
+}
+
+static const struct file_operations clock_tree_fops = {
+	.open		= clock_tree_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int possible_parents_show(struct seq_file *s, void *data)
+{
+	struct clk *c = s->private;
+	int i;
+
+	for (i = 0; c->inputs[i].input; i++) {
+		char *first = (i == 0) ? "" : " ";
+		seq_printf(s, "%s%s", first, c->inputs[i].input->name);
+	}
+	seq_printf(s, "\n");
+	return 0;
+}
+
+static int possible_parents_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, possible_parents_show, inode->i_private);
+}
+
+static const struct file_operations possible_parents_fops = {
+	.open		= possible_parents_open,
+	.read		= seq_read,
+	.llseek		= seq_lseek,
+	.release	= single_release,
+};
+
+static int clk_debugfs_register_one(struct clk *c)
+{
+	struct dentry *d, *child, *child_tmp;
+
+	d = debugfs_create_dir(c->name, clk_debugfs_root);
+	if (!d)
+		return -ENOMEM;
+	c->dent = d;
+
+	d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+	if (!d)
+		goto err_out;
+
+	d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
+	if (!d)
+		goto err_out;
+
+	if (c->inputs) {
+		d = debugfs_create_file("possible_parents", S_IRUGO, c->dent,
+			c, &possible_parents_fops);
+		if (!d)
+			goto err_out;
+	}
+
+	return 0;
+
+err_out:
+	d = c->dent;
+	list_for_each_entry_safe(child, child_tmp, &d->d_subdirs, d_u.d_child)
+		debugfs_remove(child);
+	debugfs_remove(c->dent);
+	return -ENOMEM;
+}
+
+static int clk_debugfs_register(struct clk *c)
+{
+	int err;
+	struct clk *pa = c->parent;
+
+	if (pa && !pa->dent) {
+		err = clk_debugfs_register(pa);
+		if (err)
+			return err;
+	}
+
+	if (!c->dent) {
+		err = clk_debugfs_register_one(c);
+		if (err)
+			return err;
+	}
+	return 0;
+}
+
+static int __init clk_debugfs_init(void)
+{
+	struct clk *c;
+	struct dentry *d;
+	int err = -ENOMEM;
+
+	d = debugfs_create_dir("clock", NULL);
+	if (!d)
+		return -ENOMEM;
+	clk_debugfs_root = d;
+
+	d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
+		&clock_tree_fops);
+	if (!d)
+		goto err_out;
+
+	list_for_each_entry(c, &clocks, node) {
+		err = clk_debugfs_register(c);
+		if (err)
+			goto err_out;
+	}
+	return 0;
+err_out:
+	debugfs_remove_recursive(clk_debugfs_root);
+	return err;
+}
+
+late_initcall(clk_debugfs_init);
+#endif
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
new file mode 100644
index 0000000..af7c70e
--- /dev/null
+++ b/arch/arm/mach-tegra/clock.h
@@ -0,0 +1,147 @@
+/*
+ * arch/arm/mach-tegra/include/mach/clock.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_TEGRA_CLOCK_H
+#define __MACH_TEGRA_CLOCK_H
+
+#include <linux/list.h>
+#include <asm/clkdev.h>
+
+#define DIV_BUS			(1 << 0)
+#define DIV_U71			(1 << 1)
+#define DIV_U71_FIXED		(1 << 2)
+#define DIV_2			(1 << 3)
+#define PLL_FIXED		(1 << 4)
+#define PLL_HAS_CPCON		(1 << 5)
+#define MUX			(1 << 6)
+#define PLLD			(1 << 7)
+#define PERIPH_NO_RESET		(1 << 8)
+#define PERIPH_NO_ENB		(1 << 9)
+#define PERIPH_EMC_ENB		(1 << 10)
+#define PERIPH_MANUAL_RESET	(1 << 11)
+#define PLL_ALT_MISC_REG	(1 << 12)
+#define ENABLE_ON_INIT		(1 << 28)
+
+struct clk;
+
+struct clk_mux_sel {
+	struct clk	*input;
+	u32		value;
+};
+
+struct clk_pll_table {
+	unsigned long	input_rate;
+	unsigned long	output_rate;
+	u16		n;
+	u16		m;
+	u8		p;
+	u8		cpcon;
+};
+
+struct clk_ops {
+	void		(*init)(struct clk *);
+	int		(*enable)(struct clk *);
+	void		(*disable)(struct clk *);
+	void		(*recalc)(struct clk *);
+	int		(*set_parent)(struct clk *, struct clk *);
+	int		(*set_rate)(struct clk *, unsigned long);
+	unsigned long	(*get_rate)(struct clk *);
+	long		(*round_rate)(struct clk *, unsigned long);
+	unsigned long	(*recalculate_rate)(struct clk *);
+};
+
+enum clk_state {
+	UNINITIALIZED = 0,
+	ON,
+	OFF,
+};
+
+struct clk {
+	/* node for master clocks list */
+	struct list_head		node;
+	struct list_head		children;	/* list of children */
+	struct list_head		sibling;	/* node for children */
+#ifdef CONFIG_DEBUG_FS
+	struct dentry			*dent;
+	struct dentry			*parent_dent;
+#endif
+	struct clk_ops			*ops;
+	struct clk			*parent;
+	struct clk_lookup		lookup;
+	unsigned long			rate;
+	u32				flags;
+	u32				refcnt;
+	const char			*name;
+	u32				reg;
+	u32				reg_shift;
+	unsigned int			clk_num;
+	enum clk_state			state;
+#ifdef CONFIG_DEBUG_FS
+	bool				set;
+#endif
+
+	/* PLL */
+	unsigned long			input_min;
+	unsigned long			input_max;
+	unsigned long			cf_min;
+	unsigned long			cf_max;
+	unsigned long			vco_min;
+	unsigned long			vco_max;
+	u32				m;
+	u32				n;
+	u32				p;
+	u32				cpcon;
+	const struct clk_pll_table	*pll_table;
+
+	/* DIV */
+	u32				div;
+	u32				mul;
+
+	/* MUX */
+	const struct clk_mux_sel	*inputs;
+	u32				sel;
+	u32				reg_mask;
+};
+
+
+struct clk_duplicate {
+	const char *name;
+	struct clk_lookup lookup;
+};
+
+struct tegra_clk_init_table {
+	const char *name;
+	const char *parent;
+	unsigned long rate;
+	bool enabled;
+};
+
+void tegra2_init_clocks(void);
+void tegra2_periph_reset_deassert(struct clk *c);
+void tegra2_periph_reset_assert(struct clk *c);
+void clk_init(struct clk *clk);
+struct clk *tegra_get_clock_by_name(const char *name);
+unsigned long clk_measure_input_freq(void);
+void clk_disable_locked(struct clk *c);
+int clk_enable_locked(struct clk *c);
+int clk_set_parent_locked(struct clk *c, struct clk *parent);
+int clk_reparent(struct clk *c, struct clk *parent);
+void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
+
+#endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 20875ee..039a514 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -25,6 +25,21 @@
 #include <mach/iomap.h>
 
 #include "board.h"
+#include "clock.h"
+
+static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
+	/* name		parent		rate		enabled */
+	{ "clk_m",	NULL,		0,		true },
+	{ "pll_p",	"clk_m",	216000000,	true },
+	{ "pll_p_out1",	"pll_p",	28800000,	true },
+	{ "pll_p_out2",	"pll_p",	48000000,	true },
+	{ "pll_p_out3",	"pll_p",	72000000,	true },
+	{ "pll_p_out4",	"pll_p",	108000000,	true },
+	{ "sys",	"pll_p_out4",	108000000,	true },
+	{ "hclk",	"sys",		108000000,	true },
+	{ "pclk",	"hclk",		54000000,	true },
+	{ NULL,		NULL,		0,		0},
+};
 
 void __init tegra_init_cache(void)
 {
@@ -40,5 +55,7 @@ void __init tegra_init_cache(void)
 
 void __init tegra_common_init(void)
 {
+	tegra_init_clock();
+	tegra_clk_init_from_table(common_clk_init_table);
 	tegra_init_cache();
 }
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
new file mode 100644
index 0000000..2896f25
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -0,0 +1,26 @@
+/*
+ * arch/arm/mach-tegra/include/mach/clk.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Erik Gilling <konkers at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_CLK_H
+#define __MACH_CLK_H
+
+void tegra_periph_reset_deassert(struct clk *c);
+void tegra_periph_reset_assert(struct clk *c);
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/clkdev.h b/arch/arm/mach-tegra/include/mach/clkdev.h
new file mode 100644
index 0000000..412f5c6
--- /dev/null
+++ b/arch/arm/mach-tegra/include/mach/clkdev.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-tegra/include/mach/clkdev.h
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+static inline int __clk_get(struct clk *clk)
+{
+	return 1;
+}
+
+static inline void __clk_put(struct clk *clk)
+{
+}
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
new file mode 100644
index 0000000..4261632
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -0,0 +1,1359 @@
+/*
+ * arch/arm/mach-tegra/tegra2_clocks.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ *
+ * Author:
+ *	Colin Cross <ccross at google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/hrtimer.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/iomap.h>
+
+#include "clock.h"
+
+#define RST_DEVICES			0x004
+#define RST_DEVICES_SET			0x300
+#define RST_DEVICES_CLR			0x304
+
+#define CLK_OUT_ENB			0x010
+#define CLK_OUT_ENB_SET			0x320
+#define CLK_OUT_ENB_CLR			0x324
+
+#define OSC_CTRL			0x50
+#define OSC_CTRL_OSC_FREQ_MASK		(3<<30)
+#define OSC_CTRL_OSC_FREQ_13MHZ		(0<<30)
+#define OSC_CTRL_OSC_FREQ_19_2MHZ	(1<<30)
+#define OSC_CTRL_OSC_FREQ_12MHZ		(2<<30)
+#define OSC_CTRL_OSC_FREQ_26MHZ		(3<<30)
+
+#define OSC_FREQ_DET			0x58
+#define OSC_FREQ_DET_TRIG		(1<<31)
+
+#define OSC_FREQ_DET_STATUS		0x5C
+#define OSC_FREQ_DET_BUSY		(1<<31)
+#define OSC_FREQ_DET_CNT_MASK		0xFFFF
+
+#define PERIPH_CLK_SOURCE_MASK		(3<<30)
+#define PERIPH_CLK_SOURCE_SHIFT		30
+#define PERIPH_CLK_SOURCE_ENABLE	(1<<28)
+#define PERIPH_CLK_SOURCE_DIV_MASK	0xFF
+#define PERIPH_CLK_SOURCE_DIV_SHIFT	0
+
+#define PLL_BASE			0x0
+#define PLL_BASE_BYPASS			(1<<31)
+#define PLL_BASE_ENABLE			(1<<30)
+#define PLL_BASE_REF_ENABLE		(1<<29)
+#define PLL_BASE_OVERRIDE		(1<<28)
+#define PLL_BASE_LOCK			(1<<27)
+#define PLL_BASE_DIVP_MASK		(0x7<<20)
+#define PLL_BASE_DIVP_SHIFT		20
+#define PLL_BASE_DIVN_MASK		(0x3FF<<8)
+#define PLL_BASE_DIVN_SHIFT		8
+#define PLL_BASE_DIVM_MASK		(0x1F)
+#define PLL_BASE_DIVM_SHIFT		0
+
+#define PLL_OUT_RATIO_MASK		(0xFF<<8)
+#define PLL_OUT_RATIO_SHIFT		8
+#define PLL_OUT_OVERRIDE		(1<<2)
+#define PLL_OUT_CLKEN			(1<<1)
+#define PLL_OUT_RESET_DISABLE		(1<<0)
+
+#define PLL_MISC(c)			(((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
+#define PLL_MISC_DCCON_SHIFT		20
+#define PLL_MISC_LOCK_ENABLE		(1<<18)
+#define PLL_MISC_CPCON_SHIFT		8
+#define PLL_MISC_CPCON_MASK		(0xF<<PLL_MISC_CPCON_SHIFT)
+#define PLL_MISC_LFCON_SHIFT		4
+#define PLL_MISC_LFCON_MASK		(0xF<<PLL_MISC_LFCON_SHIFT)
+#define PLL_MISC_VCOCON_SHIFT		0
+#define PLL_MISC_VCOCON_MASK		(0xF<<PLL_MISC_VCOCON_SHIFT)
+
+#define PLLD_MISC_CLKENABLE		(1<<30)
+#define PLLD_MISC_DIV_RST		(1<<23)
+#define PLLD_MISC_DCCON_SHIFT		12
+
+#define PERIPH_CLK_TO_ENB_REG(c)	((c->clk_num / 32) * 4)
+#define PERIPH_CLK_TO_ENB_SET_REG(c)	((c->clk_num / 32) * 8)
+#define PERIPH_CLK_TO_ENB_BIT(c)	(1 << (c->clk_num % 32))
+
+#define SUPER_CLK_MUX			0x00
+#define SUPER_STATE_SHIFT		28
+#define SUPER_STATE_MASK		(0xF << SUPER_STATE_SHIFT)
+#define SUPER_STATE_STANDBY		(0x0 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IDLE		(0x1 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_RUN			(0x2 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IRQ			(0x3 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_FIQ			(0x4 << SUPER_STATE_SHIFT)
+#define SUPER_SOURCE_MASK		0xF
+#define	SUPER_FIQ_SOURCE_SHIFT		12
+#define	SUPER_IRQ_SOURCE_SHIFT		8
+#define	SUPER_RUN_SOURCE_SHIFT		4
+#define	SUPER_IDLE_SOURCE_SHIFT		0
+
+#define SUPER_CLK_DIVIDER		0x04
+
+#define BUS_CLK_DISABLE			(1<<3)
+#define BUS_CLK_DIV_MASK		0x3
+
+static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+
+#define clk_writel(value, reg) \
+	__raw_writel(value, (u32)reg_clk_base + (reg))
+#define clk_readl(reg) \
+	__raw_readl((u32)reg_clk_base + (reg))
+
+unsigned long clk_measure_input_freq(void)
+{
+	u32 clock_autodetect;
+	clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
+	do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
+	clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
+	if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
+		return 12000000;
+	} else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
+		return 13000000;
+	} else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
+		return 19200000;
+	} else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
+		return 26000000;
+	} else {
+		pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
+		BUG();
+		return 0;
+	}
+}
+
+static int clk_div71_get_divider(struct clk *c, unsigned long rate)
+{
+	unsigned long divider_u71;
+
+	divider_u71 = DIV_ROUND_UP(c->rate * 2, rate);
+
+	if (divider_u71 - 2 > 255 || divider_u71 - 2 < 0)
+		return -EINVAL;
+
+	return divider_u71 - 2;
+}
+
+static unsigned long tegra2_clk_recalculate_rate(struct clk *c)
+{
+	unsigned long rate;
+	rate = c->parent->rate;
+
+	if (c->mul != 0 && c->div != 0)
+		c->rate = rate * c->mul / c->div;
+	else
+		c->rate = rate;
+	return c->rate;
+}
+
+
+/* clk_m functions */
+static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
+{
+	u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
+
+	c->rate = clk_measure_input_freq();
+	switch (c->rate) {
+	case 12000000:
+		auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
+		break;
+	case 13000000:
+		auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
+		break;
+	case 19200000:
+		auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
+		break;
+	case 26000000:
+		auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
+		break;
+	default:
+		pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
+		BUG();
+	}
+	clk_writel(auto_clock_control, OSC_CTRL);
+	return c->rate;
+}
+
+static void tegra2_clk_m_init(struct clk *c)
+{
+	pr_debug("%s on clock %s\n", __func__, c->name);
+	tegra2_clk_m_autodetect_rate(c);
+}
+
+static int tegra2_clk_m_enable(struct clk *c)
+{
+	pr_debug("%s on clock %s\n", __func__, c->name);
+	return 0;
+}
+
+static void tegra2_clk_m_disable(struct clk *c)
+{
+	pr_debug("%s on clock %s\n", __func__, c->name);
+	BUG();
+}
+
+static struct clk_ops tegra_clk_m_ops = {
+	.init		= tegra2_clk_m_init,
+	.enable		= tegra2_clk_m_enable,
+	.disable	= tegra2_clk_m_disable,
+};
+
+/* super clock functions */
+/* "super clocks" on tegra have two-stage muxes and a clock skipping
+ * super divider.  We will ignore the clock skipping divider, since we
+ * can't lower the voltage when using the clock skip, but we can if we
+ * lower the PLL frequency.
+ */
+static void tegra2_super_clk_init(struct clk *c)
+{
+	u32 val;
+	int source;
+	int shift;
+	const struct clk_mux_sel *sel;
+	val = clk_readl(c->reg + SUPER_CLK_MUX);
+	c->state = ON;
+	BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+		((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+	shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+		SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+	source = (val >> shift) & SUPER_SOURCE_MASK;
+	for (sel = c->inputs; sel->input != NULL; sel++) {
+		if (sel->value == source)
+			break;
+	}
+	BUG_ON(sel->input == NULL);
+	c->parent = sel->input;
+	tegra2_clk_recalculate_rate(c);
+}
+
+static int tegra2_super_clk_enable(struct clk *c)
+{
+	clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
+	return 0;
+}
+
+static void tegra2_super_clk_disable(struct clk *c)
+{
+	pr_debug("%s on clock %s\n", __func__, c->name);
+
+	/* oops - don't disable the CPU clock! */
+	BUG();
+}
+
+static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
+{
+	u32 val;
+	const struct clk_mux_sel *sel;
+	int shift;
+	val = clk_readl(c->reg + SUPER_CLK_MUX);;
+	BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+		((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+	shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+		SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+	for (sel = c->inputs; sel->input != NULL; sel++) {
+		if (sel->input == p) {
+			clk_reparent(c, p);
+			val &= ~(SUPER_SOURCE_MASK << shift);
+			val |= sel->value << shift;
+			clk_writel(val, c->reg);
+			c->rate = c->parent->rate;
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+static struct clk_ops tegra_super_ops = {
+	.init			= tegra2_super_clk_init,
+	.enable			= tegra2_super_clk_enable,
+	.disable		= tegra2_super_clk_disable,
+	.set_parent		= tegra2_super_clk_set_parent,
+	.recalculate_rate	= tegra2_clk_recalculate_rate,
+};
+
+/* bus clock functions */
+static void tegra2_bus_clk_init(struct clk *c)
+{
+	u32 val = clk_readl(c->reg);
+	c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
+	c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
+	c->mul = 1;
+	tegra2_clk_recalculate_rate(c);
+}
+
+static int tegra2_bus_clk_enable(struct clk *c)
+{
+	u32 val = clk_readl(c->reg);
+	val &= ~(BUS_CLK_DISABLE << c->reg_shift);
+	clk_writel(val, c->reg);
+	return 0;
+}
+
+static void tegra2_bus_clk_disable(struct clk *c)
+{
+	u32 val = clk_readl(c->reg);
+	val |= BUS_CLK_DISABLE << c->reg_shift;
+	clk_writel(val, c->reg);
+}
+
+static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	u32 val = clk_readl(c->reg);
+	unsigned long parent_rate = c->parent->rate;
+	int i;
+	for (i = 1; i <= 4; i++) {
+		if (rate == parent_rate / i) {
+			val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
+			val |= (i - 1) << c->reg_shift;
+			clk_writel(val, c->reg);
+			c->div = i;
+			c->mul = 1;
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+static struct clk_ops tegra_bus_ops = {
+	.init			= tegra2_bus_clk_init,
+	.enable			= tegra2_bus_clk_enable,
+	.disable		= tegra2_bus_clk_disable,
+	.set_rate		= tegra2_bus_clk_set_rate,
+	.recalculate_rate	= tegra2_clk_recalculate_rate,
+};
+
+/* PLL Functions */
+static unsigned long tegra2_pll_clk_recalculate_rate(struct clk *c)
+{
+	u64 rate;
+	rate = c->parent->rate;
+	rate *= c->n;
+	do_div(rate, c->m);
+	if (c->p == 2)
+		rate >>= 1;
+	c->rate = rate;
+	return c->rate;
+}
+
+static int tegra2_pll_clk_wait_for_lock(struct clk *c)
+{
+	ktime_t before;
+
+	before = ktime_get();
+	while (!(clk_readl(c->reg + PLL_BASE) & PLL_BASE_LOCK)) {
+		if (ktime_us_delta(ktime_get(), before) > 5000) {
+			pr_err("Timed out waiting for lock bit on pll %s",
+				c->name);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static void tegra2_pll_clk_init(struct clk *c)
+{
+	u32 val = clk_readl(c->reg + PLL_BASE);
+
+	c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+
+	if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+		pr_warning("Clock %s has unknown fixed frequency\n", c->name);
+		c->n = 1;
+		c->m = 0;
+		c->p = 1;
+	} else if (val & PLL_BASE_BYPASS) {
+		c->n = 1;
+		c->m = 1;
+		c->p = 1;
+	} else {
+		c->n = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+		c->m = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+		c->p = (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
+	}
+
+	val = clk_readl(c->reg + PLL_MISC(c));
+	if (c->flags & PLL_HAS_CPCON)
+		c->cpcon = (val & PLL_MISC_CPCON_MASK) >> PLL_MISC_CPCON_SHIFT;
+
+	tegra2_pll_clk_recalculate_rate(c);
+}
+
+static int tegra2_pll_clk_enable(struct clk *c)
+{
+	u32 val;
+	pr_debug("%s on clock %s\n", __func__, c->name);
+
+	val = clk_readl(c->reg + PLL_BASE);
+	val &= ~PLL_BASE_BYPASS;
+	val |= PLL_BASE_ENABLE;
+	clk_writel(val, c->reg + PLL_BASE);
+
+	val = clk_readl(c->reg + PLL_MISC(c));
+	val |= PLL_MISC_LOCK_ENABLE;
+	clk_writel(val, c->reg + PLL_MISC(c));
+
+	tegra2_pll_clk_wait_for_lock(c);
+
+	return 0;
+}
+
+static void tegra2_pll_clk_disable(struct clk *c)
+{
+	u32 val;
+	pr_debug("%s on clock %s\n", __func__, c->name);
+
+	val = clk_readl(c->reg);
+	val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+	clk_writel(val, c->reg);
+}
+
+static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	u32 val;
+	unsigned long input_rate;
+	const struct clk_pll_table *sel;
+
+	pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+	BUG_ON(c->refcnt != 0);
+
+	input_rate = c->parent->rate;
+	for (sel = c->pll_table; sel->input_rate != 0; sel++) {
+		if (sel->input_rate == input_rate && sel->output_rate == rate) {
+			c->n = sel->n;
+			c->m = sel->m;
+			c->p = sel->p;
+			c->cpcon = sel->cpcon;
+
+			val = clk_readl(c->reg + PLL_BASE);
+			if (c->flags & PLL_FIXED)
+				val |= PLL_BASE_OVERRIDE;
+			val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
+				 PLL_BASE_DIVM_MASK);
+			val |= (c->m << PLL_BASE_DIVM_SHIFT) |
+				(c->n << PLL_BASE_DIVN_SHIFT);
+			BUG_ON(c->p > 2);
+			if (c->p == 2)
+				val |= 1 << PLL_BASE_DIVP_SHIFT;
+			clk_writel(val, c->reg + PLL_BASE);
+
+			if (c->flags & PLL_HAS_CPCON) {
+				val = c->cpcon << PLL_MISC_CPCON_SHIFT;
+				val |= PLL_MISC_LOCK_ENABLE;
+				clk_writel(val, c->reg + PLL_MISC(c));
+			}
+
+			if (c->state == ON)
+				tegra2_pll_clk_enable(c);
+
+			c->rate = rate;
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+static struct clk_ops tegra_pll_ops = {
+	.init			= tegra2_pll_clk_init,
+	.enable			= tegra2_pll_clk_enable,
+	.disable		= tegra2_pll_clk_disable,
+	.set_rate		= tegra2_pll_clk_set_rate,
+	.recalculate_rate	= tegra2_pll_clk_recalculate_rate,
+};
+
+/* Clock divider ops */
+static void tegra2_pll_div_clk_init(struct clk *c)
+{
+	u32 val = clk_readl(c->reg);
+	u32 divu71;
+	val >>= c->reg_shift;
+	c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
+	if (!(val & PLL_OUT_RESET_DISABLE))
+		c->state = OFF;
+
+	if (c->flags & DIV_U71) {
+		divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+		c->div = (divu71 + 2);
+		c->mul = 2;
+	} else if (c->flags & DIV_2) {
+		c->div = 2;
+		c->mul = 1;
+	} else {
+		c->div = 1;
+		c->mul = 1;
+	}
+
+	tegra2_clk_recalculate_rate(c);
+}
+
+static int tegra2_pll_div_clk_enable(struct clk *c)
+{
+	u32 val;
+	u32 new_val;
+
+	pr_debug("%s: %s\n", __func__, c->name);
+	if (c->flags & DIV_U71) {
+		val = clk_readl(c->reg);
+		new_val = val >> c->reg_shift;
+		new_val &= 0xFFFF;
+
+		new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
+
+		val &= ~(0xFFFF << c->reg_shift);
+		val |= new_val << c->reg_shift;
+		clk_writel(val, c->reg);
+		return 0;
+	} else if (c->flags & DIV_2) {
+		BUG_ON(!(c->flags & PLLD));
+		val = clk_readl(c->reg);
+		val &= ~PLLD_MISC_DIV_RST;
+		clk_writel(val, c->reg);
+		return 0;
+	}
+	return -EINVAL;
+}
+
+static void tegra2_pll_div_clk_disable(struct clk *c)
+{
+	u32 val;
+	u32 new_val;
+
+	pr_debug("%s: %s\n", __func__, c->name);
+	if (c->flags & DIV_U71) {
+		val = clk_readl(c->reg);
+		new_val = val >> c->reg_shift;
+		new_val &= 0xFFFF;
+
+		new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
+
+		val &= ~(0xFFFF << c->reg_shift);
+		val |= new_val << c->reg_shift;
+		clk_writel(val, c->reg);
+	} else if (c->flags & DIV_2) {
+		BUG_ON(!(c->flags & PLLD));
+		val = clk_readl(c->reg);
+		val |= PLLD_MISC_DIV_RST;
+		clk_writel(val, c->reg);
+	}
+}
+
+static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	u32 val;
+	u32 new_val;
+	int divider_u71;
+	pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+	if (c->flags & DIV_U71) {
+		divider_u71 = clk_div71_get_divider(c->parent, rate);
+		if (divider_u71 >= 0) {
+			val = clk_readl(c->reg);
+			new_val = val >> c->reg_shift;
+			new_val &= 0xFFFF;
+			if (c->flags & DIV_U71_FIXED)
+				new_val |= PLL_OUT_OVERRIDE;
+			new_val &= ~PLL_OUT_RATIO_MASK;
+			new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
+
+			val &= ~(0xFFFF << c->reg_shift);
+			val |= new_val << c->reg_shift;
+			clk_writel(val, c->reg);
+			c->div = divider_u71 + 2;
+			c->mul = 2;
+			tegra2_clk_recalculate_rate(c);
+			return 0;
+		}
+	} else if (c->flags & DIV_2) {
+		if (c->parent->rate == rate * 2) {
+			c->rate = rate;
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+
+static struct clk_ops tegra_pll_div_ops = {
+	.init			= tegra2_pll_div_clk_init,
+	.enable			= tegra2_pll_div_clk_enable,
+	.disable		= tegra2_pll_div_clk_disable,
+	.set_rate		= tegra2_pll_div_clk_set_rate,
+	.recalculate_rate	= tegra2_clk_recalculate_rate,
+};
+
+/* Periph clk ops */
+
+static void tegra2_periph_clk_init(struct clk *c)
+{
+	u32 val = clk_readl(c->reg);
+	const struct clk_mux_sel *mux = 0;
+	const struct clk_mux_sel *sel;
+	if (c->flags & MUX) {
+		for (sel = c->inputs; sel->input != NULL; sel++) {
+			if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value)
+				mux = sel;
+		}
+		BUG_ON(!mux);
+
+		c->parent = mux->input;
+	} else {
+		c->parent = c->inputs[0].input;
+	}
+
+	if (c->flags & DIV_U71) {
+		u32 divu71 = val & PERIPH_CLK_SOURCE_DIV_MASK;
+		c->div = divu71 + 2;
+		c->mul = 2;
+	} else {
+		c->div = 1;
+		c->mul = 1;
+	}
+
+	c->state = ON;
+	if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+			PERIPH_CLK_TO_ENB_BIT(c)))
+		c->state = OFF;
+	if (!(c->flags & PERIPH_NO_RESET))
+		if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
+				PERIPH_CLK_TO_ENB_BIT(c))
+			c->state = OFF;
+	tegra2_clk_recalculate_rate(c);
+}
+
+static int tegra2_periph_clk_enable(struct clk *c)
+{
+	u32 val;
+	pr_debug("%s on clock %s\n", __func__, c->name);
+
+	clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+		CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
+	if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
+		clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+			RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+	if (c->flags & PERIPH_EMC_ENB) {
+		/* The EMC peripheral clock has 2 extra enable bits */
+		/* FIXME: Do they need to be disabled? */
+		val = clk_readl(c->reg);
+		val |= 0x3 << 24;
+		clk_writel(val, c->reg);
+	}
+	return 0;
+}
+
+static void tegra2_periph_clk_disable(struct clk *c)
+{
+	pr_debug("%s on clock %s\n", __func__, c->name);
+
+	clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+		CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+}
+
+void tegra2_periph_reset_deassert(struct clk *c)
+{
+	pr_debug("%s on clock %s\n", __func__, c->name);
+	if (!(c->flags & PERIPH_NO_RESET))
+		clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+			RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+}
+
+void tegra2_periph_reset_assert(struct clk *c)
+{
+	pr_debug("%s on clock %s\n", __func__, c->name);
+	if (!(c->flags & PERIPH_NO_RESET))
+		clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+			RST_DEVICES_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
+}
+
+
+static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
+{
+	u32 val;
+	const struct clk_mux_sel *sel;
+	pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+	for (sel = c->inputs; sel->input != NULL; sel++) {
+		if (sel->input == p) {
+			clk_reparent(c, p);
+			val = clk_readl(c->reg);
+			val &= ~PERIPH_CLK_SOURCE_MASK;
+			val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT;
+			clk_writel(val, c->reg);
+			c->rate = c->parent->rate;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	u32 val;
+	int divider_u71;
+	pr_debug("%s: %lu\n", __func__, rate);
+	if (c->flags & DIV_U71) {
+		divider_u71 = clk_div71_get_divider(c->parent, rate);
+		if (divider_u71 >= 0) {
+			val = clk_readl(c->reg);
+			val &= ~PERIPH_CLK_SOURCE_DIV_MASK;
+			val |= divider_u71;
+			clk_writel(val, c->reg);
+			c->div = divider_u71 + 2;
+			c->mul = 2;
+			tegra2_clk_recalculate_rate(c);
+			return 0;
+		}
+	}
+	return -EINVAL;
+}
+
+static struct clk_ops tegra_periph_clk_ops = {
+	.init			= &tegra2_periph_clk_init,
+	.enable			= &tegra2_periph_clk_enable,
+	.disable		= &tegra2_periph_clk_disable,
+	.set_parent		= &tegra2_periph_clk_set_parent,
+	.set_rate		= &tegra2_periph_clk_set_rate,
+	.recalculate_rate	= &tegra2_clk_recalculate_rate,
+};
+
+/* Clock doubler ops */
+static void tegra2_clk_double_init(struct clk *c)
+{
+	c->mul = 2;
+	c->div = 1;
+	c->state = ON;
+	if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+			PERIPH_CLK_TO_ENB_BIT(c)))
+		c->state = OFF;
+	tegra2_clk_recalculate_rate(c);
+};
+
+static struct clk_ops tegra_clk_double_ops = {
+	.init			= &tegra2_clk_double_init,
+	.enable			= &tegra2_periph_clk_enable,
+	.disable		= &tegra2_periph_clk_disable,
+	.recalculate_rate	= &tegra2_clk_recalculate_rate,
+};
+
+/* Clock definitions */
+static struct clk tegra_clk_32k = {
+	.name = "clk_32k",
+	.rate = 32678,
+	.ops  = NULL,
+};
+
+static struct clk_pll_table tegra_pll_s_table[] = {
+	{32768, 12000000, 366, 1, 1, 0},
+	{32768, 13000000, 397, 1, 1, 0},
+	{32768, 19200000, 586, 1, 1, 0},
+	{32768, 26000000, 793, 1, 1, 0},
+	{0, 0, 0, 0, 0, 0},
+};
+
+static struct clk tegra_pll_s = {
+	.name      = "pll_s",
+	.flags     = PLL_ALT_MISC_REG,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xf0,
+	.input_min = 32768,
+	.input_max = 32768,
+	.parent    = &tegra_clk_32k,
+	.cf_min    = 0, /* FIXME */
+	.cf_max    = 0, /* FIXME */
+	.vco_min   = 12000000,
+	.vco_max   = 26000000,
+	.pll_table = tegra_pll_s_table,
+};
+
+static struct clk_mux_sel tegra_clk_m_sel[] = {
+	{ .input = &tegra_clk_32k, .value = 0},
+	{ .input = &tegra_pll_s,  .value = 1},
+	{ 0, 0},
+};
+static struct clk tegra_clk_m = {
+	.name      = "clk_m",
+	.flags     = ENABLE_ON_INIT,
+	.ops       = &tegra_clk_m_ops,
+	.inputs    = tegra_clk_m_sel,
+	.reg       = 0x1fc,
+	.reg_mask  = (1<<28),
+	.reg_shift = 28,
+};
+
+static struct clk_pll_table tegra_pll_c_table[] = {
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_c = {
+	.name      = "pll_c",
+	.flags	   = PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0x80,
+	.input_min = 2000000,
+	.input_max = 31000000,
+	.parent    = &tegra_clk_m,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 20000000,
+	.vco_max   = 1400000000,
+	.pll_table = tegra_pll_c_table,
+};
+
+static struct clk tegra_pll_c_out1 = {
+	.name      = "pll_c_out1",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = DIV_U71,
+	.parent    = &tegra_pll_c,
+	.reg       = 0x84,
+	.reg_shift = 0,
+};
+
+static struct clk_pll_table tegra_pll_m_table[] = {
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_m = {
+	.name      = "pll_m",
+	.flags     = PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0x90,
+	.input_min = 2000000,
+	.input_max = 31000000,
+	.parent    = &tegra_clk_m,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 20000000,
+	.vco_max   = 1200000000,
+	.pll_table = tegra_pll_m_table,
+};
+
+static struct clk tegra_pll_m_out1 = {
+	.name      = "pll_m_out1",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = DIV_U71,
+	.parent    = &tegra_pll_m,
+	.reg       = 0x94,
+	.reg_shift = 0,
+};
+
+static struct clk_pll_table tegra_pll_p_table[] = {
+	{ 12000000, 216000000, 432, 12, 2, 8},
+	{ 13000000, 216000000, 432, 13, 2, 8},
+	{ 19200000, 216000000, 90,   4, 2, 1},
+	{ 26000000, 216000000, 432, 26, 2, 8},
+	{ 12000000, 432000000, 432, 12, 1, 8},
+	{ 13000000, 432000000, 432, 13, 1, 8},
+	{ 19200000, 432000000, 90,   4, 1, 1},
+	{ 26000000, 432000000, 432, 26, 1, 8},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_p = {
+	.name      = "pll_p",
+	.flags     = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xa0,
+	.input_min = 2000000,
+	.input_max = 31000000,
+	.parent    = &tegra_clk_m,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 20000000,
+	.vco_max   = 1400000000,
+	.pll_table = tegra_pll_p_table,
+};
+
+static struct clk tegra_pll_p_out1 = {
+	.name      = "pll_p_out1",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa4,
+	.reg_shift = 0,
+};
+
+static struct clk tegra_pll_p_out2 = {
+	.name      = "pll_p_out2",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa4,
+	.reg_shift = 16,
+};
+
+static struct clk tegra_pll_p_out3 = {
+	.name      = "pll_p_out3",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa8,
+	.reg_shift = 0,
+};
+
+static struct clk tegra_pll_p_out4 = {
+	.name      = "pll_p_out4",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
+	.parent    = &tegra_pll_p,
+	.reg       = 0xa8,
+	.reg_shift = 16,
+};
+
+static struct clk_pll_table tegra_pll_a_table[] = {
+	{ 28800000, 56448000, 49, 25, 1, 1},
+	{ 28800000, 73728000, 64, 25, 1, 1},
+	{ 28800000, 11289600, 49, 25, 1, 1},
+	{ 28800000, 12288000, 64, 25, 1, 1},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_a = {
+	.name      = "pll_a",
+	.flags     = PLL_HAS_CPCON,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xb0,
+	.input_min = 2000000,
+	.input_max = 31000000,
+	.parent    = &tegra_pll_p_out1,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 20000000,
+	.vco_max   = 1400000000,
+	.pll_table = tegra_pll_a_table,
+};
+
+static struct clk tegra_pll_a_out0 = {
+	.name      = "pll_a_out0",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = DIV_U71,
+	.parent    = &tegra_pll_a,
+	.reg       = 0xb4,
+	.reg_shift = 0,
+};
+
+static struct clk_pll_table tegra_pll_d_table[] = {
+	{ 12000000, 1000000000, 1000, 12, 1, 12},
+	{ 13000000, 1000000000, 1000, 13, 1, 12},
+	{ 19200000, 1000000000, 625,  12, 1, 8},
+	{ 26000000, 1000000000, 1000, 26, 1, 12},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_d = {
+	.name      = "pll_d",
+	.flags     = PLL_HAS_CPCON | PLLD,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xd0,
+	.input_min = 2000000,
+	.input_max = 40000000,
+	.parent    = &tegra_clk_m,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 40000000,
+	.vco_max   = 1000000000,
+	.pll_table = tegra_pll_d_table,
+};
+
+static struct clk tegra_pll_d_out0 = {
+	.name      = "pll_d_out0",
+	.ops       = &tegra_pll_div_ops,
+	.flags     = DIV_2 | PLLD,
+	.parent    = &tegra_pll_d,
+};
+
+static struct clk_pll_table tegra_pll_u_table[] = {
+	{ 12000000, 480000000, 960, 12, 1, 0},
+	{ 13000000, 480000000, 960, 13, 1, 0},
+	{ 19200000, 480000000, 200, 4,  1, 0},
+	{ 26000000, 480000000, 960, 26, 1, 0},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_u = {
+	.name      = "pll_u",
+	.flags     = 0,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xc0,
+	.input_min = 2000000,
+	.input_max = 40000000,
+	.parent    = &tegra_clk_m,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 480000000,
+	.vco_max   = 960000000,
+	.pll_table = tegra_pll_u_table,
+};
+
+static struct clk_pll_table tegra_pll_x_table[] = {
+	{ 12000000, 1000000000, 1000, 12, 1, 12},
+	{ 13000000, 1000000000, 1000, 13, 1, 12},
+	{ 19200000, 1000000000, 625,  12, 1, 8},
+	{ 26000000, 1000000000, 1000, 26, 1, 12},
+	{ 12000000, 750000000,  750,  12, 1, 12},
+	{ 13000000, 750000000,  750,  13, 1, 12},
+	{ 19200000, 750000000,  625,  16, 1, 8},
+	{ 26000000, 750000000,  750,  26, 1, 12},
+	{ 0, 0, 0, 0, 0, 0 },
+};
+
+static struct clk tegra_pll_x = {
+	.name      = "pll_x",
+	.flags     = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
+	.ops       = &tegra_pll_ops,
+	.reg       = 0xe0,
+	.input_min = 2000000,
+	.input_max = 31000000,
+	.parent    = &tegra_clk_m,
+	.cf_min    = 1000000,
+	.cf_max    = 6000000,
+	.vco_min   = 20000000,
+	.vco_max   = 1200000000,
+	.pll_table = tegra_pll_x_table,
+};
+
+static struct clk tegra_clk_d = {
+	.name      = "clk_d",
+	.flags     = PERIPH_NO_RESET,
+	.ops       = &tegra_clk_double_ops,
+	.clk_num   = 90,
+	.reg       = 0x34,
+	.reg_shift = 12,
+	.parent    = &tegra_clk_m,
+};
+
+/* FIXME: need tegra_audio
+static struct clk tegra_clk_audio_2x = {
+	.name      = "clk_d",
+	.flags     = PERIPH_NO_RESET,
+	.ops       = &tegra_clk_double_ops,
+	.clk_num   = 89,
+	.reg       = 0x34,
+	.reg_shift = 8,
+	.parent    = &tegra_audio,
+}
+*/
+
+static struct clk_mux_sel mux_cclk[] = {
+	{ .input = &tegra_clk_m,	.value = 0},
+	{ .input = &tegra_pll_c,	.value = 1},
+	{ .input = &tegra_clk_32k,	.value = 2},
+	{ .input = &tegra_pll_m,	.value = 3},
+	{ .input = &tegra_pll_p,	.value = 4},
+	{ .input = &tegra_pll_p_out4,	.value = 5},
+	{ .input = &tegra_pll_p_out3,	.value = 6},
+	{ .input = &tegra_clk_d,	.value = 7},
+	{ .input = &tegra_pll_x,	.value = 8},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_sclk[] = {
+	{ .input = &tegra_clk_m,	.value = 0},
+	{ .input = &tegra_pll_c_out1,	.value = 1},
+	{ .input = &tegra_pll_p_out4,	.value = 2},
+	{ .input = &tegra_pll_p_out3,	.value = 3},
+	{ .input = &tegra_pll_p_out2,	.value = 4},
+	{ .input = &tegra_clk_d,	.value = 5},
+	{ .input = &tegra_clk_32k,	.value = 6},
+	{ .input = &tegra_pll_m_out1,	.value = 7},
+	{ 0, 0},
+};
+
+static struct clk tegra_clk_cpu = {
+	.name	= "cpu",
+	.inputs	= mux_cclk,
+	.reg	= 0x20,
+	.ops	= &tegra_super_ops,
+};
+
+static struct clk tegra_clk_sys = {
+	.name	= "sys",
+	.inputs	= mux_sclk,
+	.reg	= 0x28,
+	.ops	= &tegra_super_ops,
+};
+
+static struct clk tegra_clk_hclk = {
+	.name		= "hclk",
+	.flags		= DIV_BUS,
+	.parent		= &tegra_clk_sys,
+	.reg		= 0x30,
+	.reg_shift	= 4,
+	.ops		= &tegra_bus_ops,
+};
+
+static struct clk tegra_clk_pclk = {
+	.name		= "pclk",
+	.flags		= DIV_BUS,
+	.parent		= &tegra_clk_hclk,
+	.reg		= 0x30,
+	.reg_shift	= 0,
+	.ops		= &tegra_bus_ops,
+};
+
+static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
+	{ .input = &tegra_pll_m, .value = 0},
+	{ .input = &tegra_pll_c, .value = 1},
+	{ .input = &tegra_pll_p, .value = 2},
+	{ .input = &tegra_pll_a_out0, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
+	{ .input = &tegra_pll_m, .value = 0},
+	{ .input = &tegra_pll_c, .value = 1},
+	{ .input = &tegra_pll_p, .value = 2},
+	{ .input = &tegra_clk_m, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
+	{ .input = &tegra_pll_p, .value = 0},
+	{ .input = &tegra_pll_c, .value = 1},
+	{ .input = &tegra_pll_m, .value = 2},
+	{ .input = &tegra_clk_m, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_plla_audio_pllp_clkm[] = {
+	{.input = &tegra_pll_a, .value = 0},
+	/* FIXME: no mux defined for tegra_audio
+	{.input = &tegra_audio, .value = 1},*/
+	{.input = &tegra_pll_p, .value = 2},
+	{.input = &tegra_clk_m, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
+	{.input = &tegra_pll_p, .value = 0},
+	{.input = &tegra_pll_d_out0, .value = 1},
+	{.input = &tegra_pll_c, .value = 2},
+	{.input = &tegra_clk_m, .value = 3},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
+	{.input = &tegra_pll_p,     .value = 0},
+	{.input = &tegra_pll_c,     .value = 1},
+	/* FIXME: no mux defined for tegra_audio
+	{.input = &tegra_audio,     .value = 2},*/
+	{.input = &tegra_clk_m,     .value = 3},
+	{.input = &tegra_clk_32k,   .value = 4},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
+	{.input = &tegra_pll_p,     .value = 0},
+	{.input = &tegra_pll_c,     .value = 1},
+	{.input = &tegra_pll_m,     .value = 2},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_clk_m[] = {
+	{ .input = &tegra_clk_m, .value = 0},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_pllp_out3[] = {
+	{ .input = &tegra_pll_p_out3, .value = 0},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_plld[] = {
+	{ .input = &tegra_pll_d, .value = 0},
+	{ 0, 0},
+};
+
+static struct clk_mux_sel mux_clk_32k[] = {
+	{ .input = &tegra_clk_32k, .value = 0},
+	{ 0, 0},
+};
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _inputs, _flags) \
+	{						\
+		.name      = _name,			\
+		.lookup    = {				\
+			.dev_id    = _dev,		\
+			.con_id	   = _con,		\
+		},					\
+		.ops       = &tegra_periph_clk_ops,	\
+		.clk_num   = _clk_num,			\
+		.reg       = _reg,			\
+		.inputs    = _inputs,			\
+		.flags     = _flags,			\
+	}
+
+struct clk tegra_periph_clks[] = {
+	PERIPH_CLK("rtc",	"rtc-tegra",		NULL,	4,	0,	mux_clk_32k,			PERIPH_NO_RESET),
+	PERIPH_CLK("timer",	"timer",		NULL,	5,	0,	mux_clk_m,			0),
+	PERIPH_CLK("i2s1",	"i2s.0",		NULL,	11,	0x100,	mux_plla_audio_pllp_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("i2s2",	"i2s.1",		NULL,	18,	0x104,	mux_plla_audio_pllp_clkm,	MUX | DIV_U71),
+	/* FIXME: spdif has 2 clocks but 1 enable */
+	PERIPH_CLK("spdif_out",	"spdif_out",		NULL,	10,	0x108,	mux_plla_audio_pllp_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("spdif_in",	"spdif_in",		NULL,	10,	0x10c,	mux_pllp_pllc_pllm,		MUX | DIV_U71),
+	PERIPH_CLK("pwm",	"pwm",			NULL,	17,	0x110,	mux_pllp_pllc_audio_clkm_clk32,	MUX | DIV_U71),
+	PERIPH_CLK("spi",	"spi",			NULL,	43,	0x114,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("xio",	"xio",			NULL,	45,	0x120,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("twc",	"twc",			NULL,	16,	0x12c,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sbc1",	"spi_tegra.0",		NULL,	41,	0x134,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sbc2",	"spi_tegra.1",		NULL,	44,	0x118,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sbc3",	"spi_tegra.2",		NULL,	46,	0x11c,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sbc4",	"spi_tegra.3",		NULL,	68,	0x1b4,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("ide",	"ide",			NULL,	25,	0x144,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("ndflash",	"tegra_nand",		NULL,	13,	0x160,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	/* FIXME: vfir shares an enable with uartb */
+	PERIPH_CLK("vfir",	"vfir",			NULL,	7,	0x168,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sdmmc1",	"sdhci-tegra.0",	NULL,	14,	0x150,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sdmmc2",	"sdhci-tegra.1",	NULL,	9,	0x154,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sdmmc3",	"sdhci-tegra.2",	NULL,	69,	0x1bc,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("sdmmc4",	"sdhci-tegra.3",	NULL,	15,	0x160,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("vde",	"vde",			NULL,	61,	0x1c8,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("csite",	"csite",		NULL,	73,	0x1d4,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	/* FIXME: what is la? */
+	PERIPH_CLK("la",	"la",			NULL,	76,	0x1f8,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("owr",	"owr",			NULL,	71,	0x1cc,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("nor",	"nor",			NULL,	42,	0x1d0,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("mipi",	"mipi",			NULL,	50,	0x174,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("i2c1",	"tegra-i2c.0",		NULL,	12,	0x124,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("i2c2",	"tegra-i2c.1",		NULL,	54,	0x198,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("i2c3",	"tegra-i2c.2",		NULL,	67,	0x1b8,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("dvc",	"tegra-i2c.3",		NULL,	47,	0x128,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("i2c1_i2c",	"tegra-i2c.0",		"i2c",	0,	0,	mux_pllp_out3,			0),
+	PERIPH_CLK("i2c2_i2c",	"tegra-i2c.1",		"i2c",	0,	0,	mux_pllp_out3,			0),
+	PERIPH_CLK("i2c3_i2c",	"tegra-i2c.2",		"i2c",	0,	0,	mux_pllp_out3,			0),
+	PERIPH_CLK("dvc_i2c",	"tegra-i2c.3",		"i2c",	0,	0,	mux_pllp_out3,			0),
+	PERIPH_CLK("uarta",	"uart.0",		NULL,	6,	0x178,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("uartb",	"uart.1",		NULL,	7,	0x17c,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("uartc",	"uart.2",		NULL,	55,	0x1a0,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("uartd",	"uart.3",		NULL,	65,	0x1c0,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("uarte",	"uart.4",		NULL,	66,	0x1c4,	mux_pllp_pllc_pllm_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("3d",	"3d",			NULL,	24,	0x158,	mux_pllm_pllc_pllp_plla,	MUX | DIV_U71 | PERIPH_MANUAL_RESET),
+	PERIPH_CLK("2d",	"2d",			NULL,	21,	0x15c,	mux_pllm_pllc_pllp_plla,	MUX | DIV_U71),
+	/* FIXME: vi and vi_sensor share an enable */
+	PERIPH_CLK("vi",	"vi",			NULL,	20,	0x148,	mux_pllm_pllc_pllp_plla,	MUX | DIV_U71),
+	PERIPH_CLK("vi_sensor",	"vi_sensor",		NULL,	20,	0x1a8,	mux_pllm_pllc_pllp_plla,	MUX | DIV_U71),
+	PERIPH_CLK("epp",	"epp",			NULL,	19,	0x16c,	mux_pllm_pllc_pllp_plla,	MUX | DIV_U71),
+	PERIPH_CLK("mpe",	"mpe",			NULL,	60,	0x170,	mux_pllm_pllc_pllp_plla,	MUX | DIV_U71),
+	PERIPH_CLK("host1x",	"host1x",		NULL,	28,	0x180,	mux_pllm_pllc_pllp_plla,	MUX | DIV_U71),
+	/* FIXME: cve and tvo share an enable	*/
+	PERIPH_CLK("cve",	"cve",			NULL,	49,	0x140,	mux_pllp_plld_pllc_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("tvo",	"tvo",			NULL,	49,	0x188,	mux_pllp_plld_pllc_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("hdmi",	"hdmi",			NULL,	51,	0x18c,	mux_pllp_plld_pllc_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("tvdac",	"tvdac",		NULL,	53,	0x194,	mux_pllp_plld_pllc_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("disp1",	"tegrafb.0",		NULL,	27,	0x138,	mux_pllp_plld_pllc_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("disp2",	"tegrafb.1",		NULL,	26,	0x13c,	mux_pllp_plld_pllc_clkm,	MUX | DIV_U71),
+	PERIPH_CLK("usbd",	"fsl-tegra-udc",	NULL,	22,	0,	mux_clk_m,			0),
+	PERIPH_CLK("usb2",	"usb.1",		NULL,	58,	0,	mux_clk_m,			0),
+	PERIPH_CLK("usb3",	"usb.2",		NULL,	59,	0,	mux_clk_m,			0),
+	PERIPH_CLK("emc",	"emc",			NULL,	57,	0x19c,	mux_pllm_pllc_pllp_clkm,	MUX | DIV_U71 | PERIPH_EMC_ENB),
+	PERIPH_CLK("dsi",	"dsi",			NULL,	48,	0,	mux_plld,			0),
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con)		\
+	{						\
+		.name	= _name,			\
+		.lookup	= {				\
+			.dev_id	= _dev,			\
+			.con_id		= _con,		\
+		},					\
+	}
+
+/* Some clocks may be used by different drivers depending on the board
+ * configuration.  List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+struct clk_duplicate tegra_clk_duplicates[] = {
+	CLK_DUPLICATE("uarta",	"tegra_uart.0",	NULL),
+	CLK_DUPLICATE("uartb",	"tegra_uart.1",	NULL),
+	CLK_DUPLICATE("uartc",	"tegra_uart.2",	NULL),
+	CLK_DUPLICATE("uartd",	"tegra_uart.3",	NULL),
+	CLK_DUPLICATE("uarte",	"tegra_uart.4",	NULL),
+};
+
+#define CLK(dev, con, ck)	\
+	{			\
+		.dev_id = dev,	\
+		.con_id = con,	\
+		.clk = ck,	\
+	}
+
+struct clk_lookup tegra_clk_lookups[] = {
+	/* external root sources */
+	CLK(NULL,	"32k_clk",	&tegra_clk_32k),
+	CLK(NULL,	"pll_s",	&tegra_pll_s),
+	CLK(NULL,	"clk_m",	&tegra_clk_m),
+	CLK(NULL,	"pll_m",	&tegra_pll_m),
+	CLK(NULL,	"pll_m_out1",	&tegra_pll_m_out1),
+	CLK(NULL,	"pll_c",	&tegra_pll_c),
+	CLK(NULL,	"pll_c_out1",	&tegra_pll_c_out1),
+	CLK(NULL,	"pll_p",	&tegra_pll_p),
+	CLK(NULL,	"pll_p_out1",	&tegra_pll_p_out1),
+	CLK(NULL,	"pll_p_out2",	&tegra_pll_p_out2),
+	CLK(NULL,	"pll_p_out3",	&tegra_pll_p_out3),
+	CLK(NULL,	"pll_p_out4",	&tegra_pll_p_out4),
+	CLK(NULL,	"pll_a",	&tegra_pll_a),
+	CLK(NULL,	"pll_a_out0",	&tegra_pll_a_out0),
+	CLK(NULL,	"pll_d",	&tegra_pll_d),
+	CLK(NULL,	"pll_d_out0",	&tegra_pll_d_out0),
+	CLK(NULL,	"pll_u",	&tegra_pll_u),
+	CLK(NULL,	"pll_x",	&tegra_pll_x),
+	CLK(NULL,	"cpu",		&tegra_clk_cpu),
+	CLK(NULL,	"sys",		&tegra_clk_sys),
+	CLK(NULL,	"hclk",		&tegra_clk_hclk),
+	CLK(NULL,	"pclk",		&tegra_clk_pclk),
+	CLK(NULL,	"clk_d",	&tegra_clk_d),
+};
+
+void __init tegra2_init_clocks(void)
+{
+	int i;
+	struct clk_lookup *cl;
+	struct clk *c;
+	struct clk_duplicate *cd;
+
+	for (i = 0; i < ARRAY_SIZE(tegra_clk_lookups); i++) {
+		cl = &tegra_clk_lookups[i];
+		clk_init(cl->clk);
+		clkdev_add(cl);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(tegra_periph_clks); i++) {
+		c = &tegra_periph_clks[i];
+		cl = &c->lookup;
+		cl->clk = c;
+
+		clk_init(cl->clk);
+		clkdev_add(cl);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+		cd = &tegra_clk_duplicates[i];
+		c = tegra_get_clock_by_name(cd->name);
+		if (c) {
+			cl = &cd->lookup;
+			cl->clk = c;
+			clkdev_add(cl);
+		} else {
+			pr_err("%s: Unknown duplicate clock %s\n", __func__,
+				cd->name);
+		}
+	}
+}
-- 
1.6.5.6



From bahadir at l4dev.org  Mon Jun 14 17:52:02 2010
From: bahadir at l4dev.org (Bahadir Balban)
Date: Tue, 15 Jun 2010 00:52:02 +0300
Subject: map_vm_area() correct dcache cleaning on ARMv7?
In-Reply-To: <20100614193003.GA17539@n2100.arm.linux.org.uk>
References: <4C167C5B.9070605@l4dev.org>
	<20100614193003.GA17539@n2100.arm.linux.org.uk>
Message-ID: <4C16A482.4020106@l4dev.org>

Russell King - ARM Linux wrote:
> On Mon, Jun 14, 2010 at 10:00:43PM +0300, Bahadir Balban wrote:
>> 2. clean_dcache_area(): clean data cache for pages allocated in (1)
>> conditionally if tlb cannot fetch from 1st level dcache.
> 
> This is absolutely correct.  We allocate a new page.  This new page can
> contain any random garbage, from old PTE entries to invalid PTE entries.
> It could even be code.  We do not want the MMU to read that old data.
> 
> So, we zero the page, and then call clean_dcache_area() to ensure that
> the MMU will see an _initialized_ kernel, not the crappy data that was
> in the page before.
> 

You are correct. The zero-initialized page must be seen by MMU.

>> 4. flush_pmd_entry(): Clean the dcache for 1st to 2nd
>> level pointer set in (3), conditionally if TLB needs it.
> 
> This pushes the cache line for the L1 table out to memory so that the
> MMU can see it.  Without this, the MMU could still see 'zero', in
> which case the MMU will fault on the first access to any page covered
> by this L2 page table.
> 
>> 5. set_pte_ext(): Set each 2nd level entry to pages.
>>
>> 6. set_pte_ext(): Unconditionally clean the dcache for 2nd level to
>> page pointer set up in (5).
> 
> Again, this is to ensure that the MMU can see the data written to the
> page tables.
> 

In ARMv7 you might not need to clean the dcache if TLB supports L1
fetches. My point is it seems to be an unconditional clean here. (2) and
(4) in my example does check for this. How about a patch like this one:

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a..6eef696 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -163,8 +163,10 @@ ENTRY(cpu_v7_set_pte_ext)
        moveq   r3, #0

        str     r3, [r0]
+#ifndef TLB_CAN_READ_FROM_L1_CACHE
        mcr     p15, 0, r0, c7, c10, 1          @ flush_pte
 #endif
+#endif
        mov     pc, lr
 ENDPROC(cpu_v7_set_pte_ext)



From jayakumar.lkml at gmail.com  Mon Jun 14 19:59:54 2010
From: jayakumar.lkml at gmail.com (Jaya Kumar)
Date: Tue, 15 Jun 2010 07:59:54 +0800
Subject: [PATCH v3 10/11] [ARM] tegra: Add framebuffer driver
In-Reply-To: <1276549827-2688-11-git-send-email-konkers@android.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
	<1276549827-2688-3-git-send-email-konkers@android.com>
	<1276549827-2688-4-git-send-email-konkers@android.com>
	<1276549827-2688-5-git-send-email-konkers@android.com>
	<1276549827-2688-6-git-send-email-konkers@android.com>
	<1276549827-2688-7-git-send-email-konkers@android.com>
	<1276549827-2688-8-git-send-email-konkers@android.com>
	<1276549827-2688-9-git-send-email-konkers@android.com>
	<1276549827-2688-10-git-send-email-konkers@android.com>
	<1276549827-2688-11-git-send-email-konkers@android.com>
Message-ID: <AANLkTikqOrciEnESCC1yGm0UvcxdK942ddrZF4K49TVb@mail.gmail.com>

On Tue, Jun 15, 2010 at 5:10 AM, Erik Gilling <konkers at android.com> wrote:
> diff --git a/drivers/video/tegrafb.c b/drivers/video/tegrafb.c
> new file mode 100644
> index 0000000..47b2d42
> --- /dev/null
> +++ b/drivers/video/tegrafb.c

> +/* palette attary used by the fbcon */
> +u32 pseudo_palette[16];

attary

> +
> +irqreturn_t tegra_fb_irq(int irq, void *ptr)
> +{
> + ? ? ? struct fb_info *info = ptr;
> + ? ? ? struct tegra_fb_info *tegra_fb = info->par;
> +
> + ? ? ? u32 reg = tegra_fb_readl(tegra_fb, DC_CMD_INT_STATUS);
> + ? ? ? tegra_fb_writel(tegra_fb, reg, DC_CMD_INT_STATUS);
> +
> + ? ? ? tegra_fb->wait_condition = 1;
> + ? ? ? wake_up(&tegra_fb->event_wq);
> + ? ? ? return IRQ_HANDLED;
> +}
> +
> +static int tegra_fb_wait_for_event(struct tegra_fb_info *tegra_fb,
> + ? ? ? unsigned long timeout, u32 irq_mask)
> +{
> + ? ? ? u32 reg;
> +
> + ? ? ? tegra_fb->wait_condition = 0;
> +
> + ? ? ? reg = tegra_fb_readl(tegra_fb, DC_CMD_INT_MASK);
> + ? ? ? reg |= irq_mask;
> + ? ? ? tegra_fb_writel(tegra_fb, reg, DC_CMD_INT_MASK);
> +
> + ? ? ? /* Clear any pending interrupt */
> + ? ? ? tegra_fb_writel(tegra_fb, irq_mask, DC_CMD_INT_STATUS);
> +
> + ? ? ? tegra_fb_writel(tegra_fb, irq_mask, DC_CMD_INT_ENABLE);
> +
> + ? ? ? /* Wait for the irq to fire */
> + ? ? ? wait_event_interruptible_timeout(tegra_fb->event_wq,
> + ? ? ? ? ? ? ? tegra_fb->wait_condition, timeout);
> +
> + ? ? ? tegra_fb_writel(tegra_fb, 0, DC_CMD_INT_ENABLE);
> +
> + ? ? ? if (!tegra_fb->wait_condition) {
> + ? ? ? ? ? ? ? pr_warning("%s: wait for vsync timed out\n", __func__);
> + ? ? ? ? ? ? ? return -ETIMEDOUT;
> + ? ? ? }
> + ? ? ? return 0;
> +}

Apologies for the incremental review. The wait_condition code above
looks odd to me. Typically, we just test the return value of
wait_event_interruptible_timeout to see whether it timed out (returns
0 if so). But I guess the above approach works as well.

> +               if (tegra_fb_wait_for_event(tegra_fb, HZ/10, DC_INT_FRAME_END))

I still didn't follow how tegra_fb_activate is using the -ETIMEDOUT
return value from the wait, it seems like it is just ignored. You are
also doing stuff like HZ/10 and you might prefer to use
msecs_to_jiffies.

Thanks,
jaya


From jayakumar.lkml at gmail.com  Mon Jun 14 20:16:25 2010
From: jayakumar.lkml at gmail.com (Jaya Kumar)
Date: Tue, 15 Jun 2010 08:16:25 +0800
Subject: [PATCH v3 10/11] [ARM] tegra: Add framebuffer driver
In-Reply-To: <AANLkTikqOrciEnESCC1yGm0UvcxdK942ddrZF4K49TVb@mail.gmail.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
	<1276549827-2688-3-git-send-email-konkers@android.com>
	<1276549827-2688-4-git-send-email-konkers@android.com>
	<1276549827-2688-5-git-send-email-konkers@android.com>
	<1276549827-2688-6-git-send-email-konkers@android.com>
	<1276549827-2688-7-git-send-email-konkers@android.com>
	<1276549827-2688-8-git-send-email-konkers@android.com>
	<1276549827-2688-9-git-send-email-konkers@android.com>
	<1276549827-2688-10-git-send-email-konkers@android.com>
	<1276549827-2688-11-git-send-email-konkers@android.com>
	<AANLkTikqOrciEnESCC1yGm0UvcxdK942ddrZF4K49TVb@mail.gmail.com>
Message-ID: <AANLkTilppHVz2XpLfin9wxrt9kHE1PIbct5XYvd_4iiX@mail.gmail.com>

On Tue, Jun 15, 2010 at 7:59 AM, Jaya Kumar <jayakumar.lkml at gmail.com> wrote:
> On Tue, Jun 15, 2010 at 5:10 AM, Erik Gilling <konkers at android.com> wrote:
>
>> + ? ? ? ? ? ? ? if (tegra_fb_wait_for_event(tegra_fb, HZ/10, DC_INT_FRAME_END))
>
> I still didn't follow how tegra_fb_activate is using the -ETIMEDOUT
> return value from the wait, it seems like it is just ignored. You are
> also doing stuff like HZ/10 and you might prefer to use
> msecs_to_jiffies.
>

I was unclear above. I mean the following code:

+	while (tegra_fb_readl(tegra_fb, DC_CMD_STATE_CONTROL) & 3) {
+		vsync_count++;
+		if (tegra_fb_wait_for_event(tegra_fb, HZ/10, DC_INT_FRAME_END))
+			break;
+	}
+	if (unlikely(vsync_count > 1))
+		pr_warning("%s: waited for %d vsyncs\n", __func__, vsync_count);

It seems to me like the timeout from wait_for_event isn't propagated
back upwards. Maybe it isn't needed but the way the code handles this
seems confusing to me.

Thanks,
jaya


From ccross at android.com  Mon Jun 14 20:43:34 2010
From: ccross at android.com (Colin Cross)
Date: Mon, 14 Jun 2010 17:43:34 -0700
Subject: [PATCH v3 10/11] [ARM] tegra: Add framebuffer driver
In-Reply-To: <AANLkTilppHVz2XpLfin9wxrt9kHE1PIbct5XYvd_4iiX@mail.gmail.com>
References: <1271198563-10424-1-git-send-email-konkers@android.com>
	<1276549827-2688-1-git-send-email-konkers@android.com>
	<1276549827-2688-2-git-send-email-konkers@android.com>
	<1276549827-2688-3-git-send-email-konkers@android.com>
	<1276549827-2688-4-git-send-email-konkers@android.com>
	<1276549827-2688-5-git-send-email-konkers@android.com>
	<1276549827-2688-6-git-send-email-konkers@android.com>
	<1276549827-2688-7-git-send-email-konkers@android.com>
	<1276549827-2688-8-git-send-email-konkers@android.com>
	<1276549827-2688-9-git-send-email-konkers@android.com>
	<1276549827-2688-10-git-send-email-konkers@android.com>
	<1276549827-2688-11-git-send-email-konkers@android.com>
	<AANLkTikqOrciEnESCC1yGm0UvcxdK942ddrZF4K49TVb@mail.gmail.com>
	<AANLkTilppHVz2XpLfin9wxrt9kHE1PIbct5XYvd_4iiX@mail.gmail.com>
Message-ID: <AANLkTikOYNoOGH5-6hYJ5dVZ-qlHE88xGb3G64e_eUH8@mail.gmail.com>

On Mon, Jun 14, 2010 at 5:16 PM, Jaya Kumar <jayakumar.lkml at gmail.com> wrote:
> On Tue, Jun 15, 2010 at 7:59 AM, Jaya Kumar <jayakumar.lkml at gmail.com> wrote:
>> On Tue, Jun 15, 2010 at 5:10 AM, Erik Gilling <konkers at android.com> wrote:
>>
>>> + ? ? ? ? ? ? ? if (tegra_fb_wait_for_event(tegra_fb, HZ/10, DC_INT_FRAME_END))
>>
>> I still didn't follow how tegra_fb_activate is using the -ETIMEDOUT
>> return value from the wait, it seems like it is just ignored. You are
>> also doing stuff like HZ/10 and you might prefer to use
>> msecs_to_jiffies.
>>
>
> I was unclear above. I mean the following code:
>
> + ? ? ? while (tegra_fb_readl(tegra_fb, DC_CMD_STATE_CONTROL) & 3) {
> + ? ? ? ? ? ? ? vsync_count++;
> + ? ? ? ? ? ? ? if (tegra_fb_wait_for_event(tegra_fb, HZ/10, DC_INT_FRAME_END))
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? }
> + ? ? ? if (unlikely(vsync_count > 1))
> + ? ? ? ? ? ? ? pr_warning("%s: waited for %d vsyncs\n", __func__, vsync_count);
>
> It seems to me like the timeout from wait_for_event isn't propagated
> back upwards. Maybe it isn't needed but the way the code handles this
> seems confusing to me.

ETIMEDOUT in tegra_fb_wait_for_event is detecting waiting on an
interrupt that is not firing, and the loop in tegra_fb_activate is
checking for the double-buffering bits to clear in a reasonable amount
of time.  The if check in the loop makes sure that if the frame
interrupt is not occuring, the driver doesn't loop forever on the
double-buffering bits.

I'll modify tegra_fb_activate to propagate the error code and use
msecs_to_jiffies.

Thanks,
Colin


From marek.vasut at gmail.com  Mon Jun 14 21:25:16 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Tue, 15 Jun 2010 03:25:16 +0200
Subject: [PATCH] pxa/colibri320: Add UDC support
Message-ID: <1276565116-17646-1-git-send-email-marek.vasut@gmail.com>

Add support for PXA UDC.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/colibri-pxa320.c |   40 ++++++++++++++++++++++++++++++++++++
 1 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index ae835fa..99e850d 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
+#include <linux/usb/gpio_vbus.h>
 
 #include <asm/mach-types.h>
 #include <asm/sizes.h>
@@ -28,6 +29,8 @@
 #include <mach/pxafb.h>
 #include <mach/ohci.h>
 #include <mach/audio.h>
+#include <mach/pxa27x-udc.h>
+#include <mach/udc.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -101,6 +104,42 @@ void __init colibri_pxa320_init_ohci(void)
 static inline void colibri_pxa320_init_ohci(void) {}
 #endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
 
+#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE)
+static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = {
+	.gpio_vbus		= mfp_to_gpio(MFP_PIN_GPIO96),
+	.gpio_pullup		= -1,
+};
+
+static struct platform_device colibri_pxa320_gpio_vbus = {
+	.name	= "gpio-vbus",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &colibri_pxa320_gpio_vbus_info,
+	},
+};
+
+static void colibri_pxa320_udc_command(int cmd)
+{
+	if (cmd == PXA2XX_UDC_CMD_CONNECT)
+		UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
+	else if (cmd == PXA2XX_UDC_CMD_DISCONNECT)
+		UP2OCR = UP2OCR_HXOE;
+}
+
+static struct pxa2xx_udc_mach_info colibri_pxa320_udc_info __initdata = {
+	.udc_command		= colibri_pxa320_udc_command,
+	.gpio_pullup		= -1,
+};
+
+static void __init colibri_pxa320_init_udc(void)
+{
+	pxa_set_udc_info(&colibri_pxa320_udc_info);
+	platform_device_register(&colibri_pxa320_gpio_vbus);
+}
+#else
+static inline void colibri_pxa320_init_udc(void) {}
+#endif
+
 static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = {
 	GPIO22_MMC1_CLK,
 	GPIO23_MMC1_CMD,
@@ -212,6 +251,7 @@ void __init colibri_pxa320_init(void)
 	colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config),
 				mfp_to_gpio(MFP_PIN_GPIO28));
 	colibri_pxa320_init_uart();
+	colibri_pxa320_init_udc();
 }
 
 MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
-- 
1.7.1



From david at gibson.dropbear.id.au  Mon Jun 14 22:02:24 2010
From: david at gibson.dropbear.id.au (David Gibson)
Date: Tue, 15 Jun 2010 12:02:24 +1000
Subject: Request review of device tree documentation
In-Reply-To: <alpine.LFD.2.00.1006141044510.13427@xanadu.home>
References: <4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>
Message-ID: <20100615020224.GK9323@yookeroo>

On Mon, Jun 14, 2010 at 10:59:20AM -0400, Nicolas Pitre wrote:
> On Mon, 14 Jun 2010, David Gibson wrote:
> 
> > On Sun, Jun 13, 2010 at 11:02:15PM -0600, Grant Likely wrote:
> > [sni]
> > > > That's sort of a self-fulfilling prophecy. ?If the OS doesn't trust the
> > > > firmware, there is no pressure for the firmware to "get it right".
> > > 
> > > Firmware will not get it right.  Period.  There will always be
> > > something wrong.  It is never right on PCs.  It will never be right on
> > > the other architectures.
> > 
> > Yes, yes, yes.  And there is a great deal of empirical evidence to
> > back that assertion.
> > 
> > >  That goes for OSes too, but upgrading an OS
> > > isn't as risky as upgrading firmware.  That isn't to say that it can't
> > > be close, but every firmware feature that the OS depends on is a
> > > feature that could force a risky firmware upgrade when the bug in it
> > > is discovered.
> > 
> > Indeed.  In fact, the general rule of thumb is really "put as much as
> > possible into the most easily replaced layer of the stack".  This is,
> > incidentally, why I've always been dubious about simple firmwares
> > supplying a flattened device tree rather than including the device
> > tree template in the kernel, cuboot style.
> 
> The biggest advantage, IMHO, for adding DT to ARM, is actually to 
> decouple the hardware config information and the kernel.  If in the end 
> the DT has to be shipped in the kernel then we're losing all this 
> advantage over the current state of things on ARM which still works 
> pretty well otherwise.

Right, which is why I'm just dubious, not dead against it.  If
firmware supplies a device tree that's so awful you have to replace
most of it, then you haven't won much over having a kernel wrapper
which uses ad-hoc logic to detect the board type from whatever random
clues the firmware leaves and selects a device tree from it's library
of them based on that.  On ARM this sort of approach is probably more
effective than powerpc, even, since you could use the machine number
to select from a bag of canned device trees and still have a
multi-board kernel.

> In the best case, the simple firmware simply has to retrieve the 
> flattened device tree from flash, and pass it to the kernel just like 
> some anonymous blob.  And the simple firmware only needs to provide a 
> way for that DT blob to be updatable, like through an upload of a 
> replacement blob that was prepared offline.  Just like a ramdisk image 
> or the like.

Yes, having the firmware DT independently updateable makes most of my
concerns about it go away.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson


From mhowe at cwlinux.com  Mon Jun 14 23:29:36 2010
From: mhowe at cwlinux.com (Morgan Howe)
Date: Tue, 15 Jun 2010 11:29:36 +0800
Subject: mxcmmc driver hangs on sync
Message-ID: <20100615112936.5d03ce92@morgan>

Greetings,

I'm using a freescale i.mx27 board with 2 class 2 sdhc cards.
Originally we were working with the 2.6.22 kernel from freescale, but
found that after an extended period of writing to the SD card (around
2k-3k writes of a 1mb file), the driver would hang when we called the
sync command. It appeared to be an issue related to dma interrupts.

Since we have been wanting to move to the newer kernel anyway, I
decided to try a similar test using the current mainline kernel from
Linus' tree.  Basically, my test is a simple bash script which does
this:

while(true) {
cp 1mb_test_file SD1
cp SD1/1mb_test_file SD2
sync
}

With the older kernel this would hang on sync after a few thousand
loops, and much sooner if you ran 2 or 3 of these processes at a time.
I tried last night with the newer kernel and kicking off 3 processes
and after ~100-150 loops per process I get this:

mxc-mmc mxc-mmc.0: mxcmci_finish_data: No CRC -ETIMEDOUT
mmcblk0: error -110 transferring data, sector 24765007, nr 512, card
status 0x0 mmcblk0: error -110 sending stop command, response 0x0, card
status 0x0 end_request: I/O error, dev mmcblk0, sector 24765021
end_request: I/O error, dev mmcblk0, sector 24765023
end_request: I/O error, dev mmcblk0, sector 24765031
end_request: I/O error, dev mmcblk0, sector 24765039
...
<snip>

It then continues for ~20 more loops per process, and then again I get
that same error. Continues for a while longer and then finally this:

mxc-mmc mxc-mmc.1: mxcmci_finish_data: No CRC -ETIMEDOUT
mmcblk1: error -110 transferring data, sector 8859727, nr 144, card
status 0xc00 FEC: MDIO read timeout

And I can see in the output from ps:

  535 0         2808 S    /bin/sh ./test.sh 
  673 0         2808 S    /bin/sh ./test.sh 
  747 0         2808 S    /bin/sh ./test.sh 
 2097 0         2672 D    sync 
 2098 0         2672 D    sync 
 2099 0         2672 D    sync 
 2261 0            0 SW   [flush-179:8]
 2262 0         3052 R    ps

Has anyone seen this or have any suggestions how I may be able to go
about fixing it?

Regards,
Morgan


From kgene.kim at samsung.com  Mon Jun 14 23:45:36 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 15 Jun 2010 12:45:36 +0900
Subject: [PATCH 0/6] S5PV210 PM Support (suspend-to-mem)
In-Reply-To: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>
References: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>
Message-ID: <007601cb0c3d$3aa91910$affb4b30$%kim@samsung.com>

Myungjoo Ham wrote:
> 
> This patch set supports S5PV210/S5PC110 PM (suspend-to-mem).
> 

Please include Ben Dooks for Samsung SoC patch - his address is in
MAINTAINERS.

And If this patch set is for S5PV210/S5PC110 PM, please make sure that
includes for PM code.
Seems to be added unnecessary codes.

> MyungJoo Ham (8):
>   S5PV210 Add IRQ/EINT register information for the CPU.
>   S5PV210 add clock registers for the CPU.
>   S5PV210 added register mappings
>   S5PV210 GPIO relataed registers are added.
>   S5PV210 added EINT-GPIO register mappings
>   S5PV210 PM Support (suspend-to-mem)
> 
>  arch/arm/mach-s5pv210/Makefile                  |    4 +
>  arch/arm/mach-s5pv210/include/mach/irqs.h       |    9 +
>  arch/arm/mach-s5pv210/include/mach/map.h        |   45 +++
>  arch/arm/mach-s5pv210/include/mach/regs-clock.h |  467
> ++++++++++++++++++++++-
>  arch/arm/mach-s5pv210/include/mach/regs-gpio.h  |  121 ++++++
>  arch/arm/mach-s5pv210/include/mach/regs-irq.h   |    6 +
>  arch/arm/plat-s5p/Makefile                      |    3 +
>  arch/arm/plat-s5p/include/plat/gpio-ext.h       |   44 +++
>  arch/arm/plat-s5p/include/plat/map-s5p.h        |    1 +
>  arch/arm/plat-s5p/sleep.S                       |  248 ++++++++++++
>  arch/arm/plat-samsung/include/plat/pm-core.h    |   53 +++
>  arch/arm/plat-samsung/include/plat/pm.h         |   13 +
>  arch/arm/plat-samsung/pm-gpio.c                 |    4 +-
>  arch/arm/plat-samsung/pm.c                      |   75 ++++-
>  14 files changed, 1082 insertions(+), 11 deletions(-)
>  create mode 100644 arch/arm/plat-s5p/include/plat/gpio-ext.h
>  create mode 100644 arch/arm/plat-s5p/sleep.S
>  create mode 100644 arch/arm/plat-samsung/include/plat/pm-core.h
> 
> 

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Tue Jun 15 00:20:47 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 15 Jun 2010 13:20:47 +0900
Subject: [PATCH 2/6] S5PV210 add clock registers for the CPU.
In-Reply-To: <1276504755-24741-3-git-send-email-MyungJoo.Ham@samsung.com>
References: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-2-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-3-git-send-email-MyungJoo.Ham@samsung.com>
Message-ID: <008601cb0c42$23789130$6a69b390$%kim@samsung.com>

MyungJoo Ham wrote:
> 
> 	Besides, renamed a register name "BUS0" into "IP5" as EVT1 uses
> "IP5" instead of BUS0 (of EVT0)

Please make sure that your patch has no problem by using
scripts/checkpatch.pl before submitting.
Following is from script/checkpatch.pl:
'total: 33 errors, 6 warnings, 513 lines checked' :-(

And could you specify a reason for adding these register definitions if they
are not being used.

> 
> Signed-off-by: MyungJoo Ham <MyungJoo.Ham at samsung.com>
> ---
>  arch/arm/mach-s5pv210/include/mach/regs-clock.h |  467
> ++++++++++++++++++++++-
>  1 files changed, 465 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
b/arch/arm/mach-
> s5pv210/include/mach/regs-clock.h
> index 2a25ab4..9652338 100644
> --- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
> +++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
> @@ -25,6 +25,8 @@
>  #define S5P_APLL_CON		S5P_CLKREG(0x100)
>  #define S5P_MPLL_CON		S5P_CLKREG(0x108)
>  #define S5P_EPLL_CON		S5P_CLKREG(0x110)
> +#define S5P_EPLL_CON1		S5P_CLKREG(0x114)
> +#define S5P_EPLL_CON1_MASK	(0xFFFF << 0)
>  #define S5P_VPLL_CON		S5P_CLKREG(0x120)
> 
>  #define S5P_CLK_SRC0		S5P_CLKREG(0x200)
> @@ -63,14 +65,139 @@
>  #define S5P_CLKGATE_IP4		S5P_CLKREG(0x470)
> 
>  #define S5P_CLKGATE_BLOCK	S5P_CLKREG(0x480)
> -#define S5P_CLKGATE_BUS0	S5P_CLKREG(0x484)
> +#define S5P_CLKGATE_IP5		S5P_CLKREG(0x484)
>  #define S5P_CLKGATE_BUS1	S5P_CLKREG(0x488)
>  #define S5P_CLK_OUT		S5P_CLKREG(0x500)
> +#define S5P_CLK_DIV_STAT0   S5P_CLKREG(0x1000)
> +#define S5P_CLK_DIV_STAT1   S5P_CLKREG(0x1004)
> +#define S5P_CLK_MUX_STAT0   S5P_CLKREG(0x1100)
> +#define S5P_CLK_MUX_STAT1   S5P_CLKREG(0x1104)
> +#define S5P_MIXER_OUT_SEL	S5P_CLKREG(0x7004)
> +#define S5P_MDNIE_SEL		S5P_CLKREG(0x7008)
> +#define S5P_MIPI_PHY_CON0	S5P_CLKREG(0x7200)
> +#define S5P_MIPI_PHY_CON1	S5P_CLKREG(0x7204)
> +
> +#define S5P_DCGIDX_MAP0		S5P_CLKREG(0x3000)
> +#define S5P_DCGIDX_MAP1		S5P_CLKREG(0x3004)
> +#define S5P_DCGIDX_MAP2		S5P_CLKREG(0x3008)
> +#define S5P_DCGPERF_MAP0	S5P_CLKREG(0x3020)
> +#define S5P_DCGPERF_MAP1	S5P_CLKREG(0x3024)
> +#define S5P_DVCIDX_MAP		S5P_CLKREG(0x3040)
> +#define S5P_FREQ_CPU		S5P_CLKREG(0x3060)
> +#define S5P_FREQ_DPM		S5P_CLKREG(0x3064)
> +#define S5P_DVSEMCLK_EN		S5P_CLKREG(0x3080)
> +#define S5P_MAXPERF		S5P_CLKREG(0x3084)
> +
> +#define S5P_EPLL_EN     (1<<31)
> +#define S5P_EPLL_MASK   0xffffffff
> +#define S5P_EPLLVAL(_v,_m,_p,_s)   ((_v) << 27 | (_m) << 16 | ((_p) << 8)
| ((_s)))
> 
>  /* CLKSRC0 */
> +#define S5P_CLKSRC0_APLL_MASK		(0x1<<0)
> +#define S5P_CLKSRC0_APLL_SHIFT		(0)
> +#define S5P_CLKSRC0_MPLL_MASK		(0x1<<4)
> +#define S5P_CLKSRC0_MPLL_SHIFT		(4)
> +#define S5P_CLKSRC0_EPLL_MASK		(0x1<<8)
> +#define S5P_CLKSRC0_EPLL_SHIFT		(8)
> +#define S5P_CLKSRC0_VPLL_MASK		(0x1<<12)
> +#define S5P_CLKSRC0_VPLL_SHIFT		(12)
>  #define S5P_CLKSRC0_MUX200_MASK		(0x1<<16)
> +#define S5P_CLKSRC0_MUX200_SHIFT	(16)
>  #define S5P_CLKSRC0_MUX166_MASK		(0x1<<20)
> +#define S5P_CLKSRC0_MUX166_SHIFT	(20)
>  #define S5P_CLKSRC0_MUX133_MASK		(0x1<<24)
> +#define S5P_CLKSRC0_MUX133_SHIFT	(24)
> +#define S5P_CLKSRC0_ONENAND_MASK	(0x1<<28)
> +#define S5P_CLKSRC0_ONENAND_SHIFT	(28)
> +
> +/* CLKSRC1 */
> +#define S5P_CLKSRC1_HDMI_MASK		(0x1<<0)
> +#define S5P_CLKSRC1_HDMI_SHIFT		(0)
> +#define S5P_CLKSRC1_MIXER_MASK		(0x1<<4)
> +#define S5P_CLKSRC1_MIXER_SHIFT		(4)
> +#define S5P_CLKSRC1_DAC_MASK		(0x1<<8)
> +#define S5P_CLKSRC1_DAC_SHIFT		(8)
> +#define S5P_CLKSRC1_CAM0_MASK		(0xF<<12)
> +#define S5P_CLKSRC1_CAM0_SHIFT		(12)
> +#define S5P_CLKSRC1_CAM1_MASK		(0xF<<16)
> +#define S5P_CLKSRC1_CAM1_SHIFT		(16)
> +#define S5P_CLKSRC1_FIMD_MASK		(0xF<<20)
> +#define S5P_CLKSRC1_FIMD_SHIFT		(20)
> +#define S5P_CLKSRC1_CSIS_MASK		(0xF<<24)
> +#define S5P_CLKSRC1_CSIS_SHIFT		(24)
> +#define S5P_CLKSRC1_VPLLSRC_MASK	(0x1<<28)
> +#define S5P_CLKSRC1_VPLLSRC_SHIFT	(28)
> +
> +/* CLKSRC2 */
> +#define S5P_CLKSRC2_G3D_MASK		(0x3<<0)
> +#define S5P_CLKSRC2_G3D_SHIFT		(0)
> +#define S5P_CLKSRC2_MFC_MASK		(0x3<<4)
> +#define S5P_CLKSRC2_MFC_SHIFT		(4)
> +#define S5P_CLKSRC2_G2D_MASK		(0x3<<8)
> +#define S5P_CLKSRC2_G2D_SHIFT		(8)
> +
> +/* CLKSRC3 */
> +#define S5P_CLKSRC3_MDNIE_MASK		(0xF<<0)
> +#define S5P_CLKSRC3_MDNIE_SHIFT		(0)
> +#define S5P_CLKSRC3_MDNIE_PWMCLK_MASK	(0xF<<4)
> +#define S5P_CLKSRC3_MDNIE_PWMCLK_SHIFT	(4)
> +#define S5P_CLKSRC3_FIMC0_LCLK_MASK	(0xF<<12)
> +#define S5P_CLKSRC3_FIMC0_LCLK_SHIFT	(12)
> +#define S5P_CLKSRC3_FIMC1_LCLK_MASK	(0xF<<16)
> +#define S5P_CLKSRC3_FIMC1_LCLK_SHIFT	(16)
> +#define S5P_CLKSRC3_FIMC2_LCLK_MASK	(0xF<<20)
> +#define S5P_CLKSRC3_FIMC2_LCLK_SHIFT	(20)
> +
> +/* CLKSRC4 */
> +#define S5P_CLKSRC4_MMC0_MASK		(0xF<<0)
> +#define S5P_CLKSRC4_MMC0_SHIFT		(0)
> +#define S5P_CLKSRC4_MMC1_MASK		(0xF<<4)
> +#define S5P_CLKSRC4_MMC1_SHIFT		(4)
> +#define S5P_CLKSRC4_MMC2_MASK		(0xF<<8)
> +#define S5P_CLKSRC4_MMC2_SHIFT		(8)
> +#define S5P_CLKSRC4_MMC3_MASK		(0xF<<12)
> +#define S5P_CLKSRC4_MMC3_SHIFT		(12)
> +#define S5P_CLKSRC4_UART0_MASK		(0xF<<16)
> +#define S5P_CLKSRC4_UART0_SHIFT		(16)
> +#define S5P_CLKSRC4_UART1_MASK		(0xF<<20)
> +#define S5P_CLKSRC4_UART1_SHIFT		(20)
> +#define S5P_CLKSRC4_UART2_MASK		(0xF<<24)
> +#define S5P_CLKSRC4_UART2_SHIFT		(24)
> +#define S5P_CLKSRC4_UART3_MASK		(0xF<<28)
> +#define S5P_CLKSRC4_UART3_SHIFT		(28)
> +
> +/* CLKSRC5 */
> +#define S5P_CLKSRC5_SPI0_MASK		(0xF<<0)
> +#define S5P_CLKSRC5_SPI0_SHIFT		(0)
> +#define S5P_CLKSRC5_SPI1_MASK		(0xF<<4)
> +#define S5P_CLKSRC5_SPI1_SHIFT		(4)
> +#define S5P_CLKSRC5_SPI2_MASK		(0xF<<8)
> +#define S5P_CLKSRC5_SPI2_SHIFT		(8)
> +#define S5P_CLKSRC5_PWM_MASK		(0xF<<12)
> +#define S5P_CLKSRC5_PWM_SHIFT		(12)
> +
> +/* CLKSRC6 */
> +#define S5P_CLKSRC6_AUDIO0_MASK		(0xF<<0)
> +#define S5P_CLKSRC6_AUDIO0_SHIFT	(0)
> +#define S5P_CLKSRC6_AUDIO1_MASK		(0xF<<4)
> +#define S5P_CLKSRC6_AUDIO1_SHIFT	(4)
> +#define S5P_CLKSRC6_AUDIO2_MASK		(0xF<<8)
> +#define S5P_CLKSRC6_AUDIO2_SHIFT	(8)
> +#define S5P_CLKSRC6_SPDIF_MASK		(0x3<<12)
> +#define S5P_CLKSRC6_SPDIF_SHIFT		(12)
> +#define S5P_CLKSRC6_HPM_MASK		(0x1<<16)
> +#define S5P_CLKSRC6_HPM_SHIFT		(16)
> +#define S5P_CLKSRC6_PWI_MASK		(0xF<<20)
> +#define S5P_CLKSRC6_PWI_SHIFT		(20)
> +#define S5P_CLKSRC6_ONEDRAM_MASK	(0x3<<24)
> +#define S5P_CLKSRC6_ONEDRAM_SHIFT	(24)
> +
> +/* CLKSRC_MASK0 - To be defined */
> +#define S5P_CLKSRC_MASK0_HDMI		(1<<0)
> +#define S5P_CLKSRC_MASK0_MIXER		(1<<1)
> +
> +/* CLKSRC_MASK1 - To be defined */
> +
> 
>  /* CLKDIV0 */
>  #define S5P_CLKDIV0_APLL_SHIFT		(0)
> @@ -90,7 +217,325 @@
>  #define S5P_CLKDIV0_PCLK66_SHIFT	(28)
>  #define S5P_CLKDIV0_PCLK66_MASK		(0x7 <<
> S5P_CLKDIV0_PCLK66_SHIFT)
> 
> +/* CLKDIV1 */
> +#define S5P_CLKDIV1_TBLK_MASK		(0xF<<0)
> +#define S5P_CLKDIV1_TBLK_SHIFT		(0)
> +#define S5P_CLKDIV1_FIMC_MASK		(0xF<<8)
> +#define S5P_CLKDIV1_FIMC_SHIFT		(8)
> +#define S5P_CLKDIV1_CAM0_MASK		(0xF<<12)
> +#define S5P_CLKDIV1_CAM0_SHIFT		(12)
> +#define S5P_CLKDIV1_CAM1_MASK		(0xF<<16)
> +#define S5P_CLKDIV1_CAM1_SHIFT		(16)
> +#define S5P_CLKDIV1_FIMD_MASK		(0xF<<20)
> +#define S5P_CLKDIV1_FIMD_SHIFT		(20)
> +#define S5P_CLKDIV1_CSIS_MASK		(0xF<<28)
> +#define S5P_CLKDIV1_CSIS_SHIFT		(28)
> +
> +/* CLKDIV2 */
> +#define S5P_CLKDIV2_G3D_MASK		(0xF<<0)
> +#define S5P_CLKDIV2_G3D_SHIFT		(0)
> +#define S5P_CLKDIV2_MFC_MASK		(0xF<<4)
> +#define S5P_CLKDIV2_MFC_SHIFT		(4)
> +#define S5P_CLKDIV2_G2D_MASK		(0xF<<8)
> +#define S5P_CLKDIV2_G2D_SHIFT		(8)
> +
> +/* CLKDIV3 */
> +#define S5P_CLKDIV3_MDNIE_MASK		(0xf<<0)
> +#define S5P_CLKDIV3_MDNIE_SHIFT		(0)
> +#define S5P_CLKDIV3_MDNIE_PWM_MASK	(0x3f<<4)
> +#define S5P_CLKDIV3_MDNIE_PWM_SHIFT	(4)
> +#define S5P_CLKDIV3_FIMC0_LCLK_MASK	(0xf<<12)
> +#define S5P_CLKDIV3_FIMC0_LCLK_SHIFT	(12)
> +#define S5P_CLKDIV3_FIMC1_LCLK_MASK	(0xf<<16)
> +#define S5P_CLKDIV3_FIMC1_LCLK_SHIFT	(16)
> +#define S5P_CLKDIV3_FIMC2_LCLK_MASK	(0xf<<20)
> +#define S5P_CLKDIV3_FIMC2_LCLK_SHIFT	(20)
> +
> +/* CLKDIV4 */
> +#define S5P_CLKDIV4_MMC0_MASK		(0xF<<0)
> +#define S5P_CLKDIV4_MMC0_SHIFT		(0)
> +#define S5P_CLKDIV4_MMC1_MASK		(0xF<<4)
> +#define S5P_CLKDIV4_MMC1_SHIFT		(4)
> +#define S5P_CLKDIV4_MMC2_MASK		(0xF<<8)
> +#define S5P_CLKDIV4_MMC2_SHIFT		(8)
> +#define S5P_CLKDIV4_MMC3_MASK		(0xF<<12)
> +#define S5P_CLKDIV4_MMC3_SHIFT		(12)
> +#define S5P_CLKDIV4_UART0_MASK		(0xF<<16)
> +#define S5P_CLKDIV4_UART0_SHIFT		(16)
> +#define S5P_CLKDIV4_UART1_MASK		(0xf<<20)
> +#define S5P_CLKDIV4_UART1_SHIFT		(20)
> +#define S5P_CLKDIV4_UART2_MASK		(0xf<<24)
> +#define S5P_CLKDIV4_UART2_SHIFT		(24)
> +#define S5P_CLKDIV4_UART3_MASK		(0xf<<28)
> +#define S5P_CLKDIV4_UART3_SHIFT		(28)
> +
> +/* CLKDIV5 */
> +#define S5P_CLKDIV5_SPI0_MASK		(0xF<<0)
> +#define S5P_CLKDIV5_SPI0_SHIFT		(0)
> +#define S5P_CLKDIV5_SPI1_MASK		(0xF<<4)
> +#define S5P_CLKDIV5_SPI1_SHIFT		(4)
> +#define S5P_CLKDIV5_SPI2_MASK		(0xF<<8)
> +#define S5P_CLKDIV5_SPI2_SHIFT		(8)
> +#define S5P_CLKDIV5_PWM_MASK		(0xF<<12)
> +#define S5P_CLKDIV5_PWM_SHIFT		(12)
> +
> +/* CLKDIV6 */
> +#define S5P_CLKDIV6_AUDIO0_MASK		(0xF<<0)
> +#define S5P_CLKDIV6_AUDIO0_SHIFT	(0)
> +#define S5P_CLKDIV6_AUDIO1_MASK		(0xF<<4)
> +#define S5P_CLKDIV6_AUDIO1_SHIFT	(4)
> +#define S5P_CLKDIV6_AUDIO2_MASK		(0xF<<8)
> +#define S5P_CLKDIV6_AUDIO2_SHIFT	(8)
> +#define S5P_CLKDIV6_ONENAND_MASK	(0x7<<12)
> +#define S5P_CLKDIV6_ONENAND_SHIFT	(12)
> +#define S5P_CLKDIV6_COPY_MASK		(0x7<<16)
> +#define S5P_CLKDIV6_COPY_SHIFT		(16)
> +#define S5P_CLKDIV6_HPM_MASK		(0x7<<20)
> +#define S5P_CLKDIV6_HPM_SHIFT		(20)
> +#define S5P_CLKDIV6_PWI_MASK		(0xf<<24)
> +#define S5P_CLKDIV6_PWI_SHIFT		(24)
> +#define S5P_CLKDIV6_ONEDRAM_MASK	(0xf<<28)
> +#define S5P_CLKDIV6_ONEDRAM_SHIFT	(28)
> +
> +/* IP Clock Gate 0 Registers */
> +#define S5P_CLKGATE_IP0_CSIS		(1<<31)
> +#define S5P_CLKGATE_IP0_IPC		(1<<30)
> +#define S5P_CLKGATE_IP0_ROTATOR		(1<<29)
> +#define S5P_CLKGATE_IP0_JPEG		(1<<28)
> +#define S5P_CLKGATE_IP0_FIMC2		(1<<26)
> +#define S5P_CLKGATE_IP0_FIMC1		(1<<25)
> +#define S5P_CLKGATE_IP0_FIMC0		(1<<24)
> +#define S5P_CLKGATE_IP0_MFC		(1<<16)
> +#define S5P_CLKGATE_IP0_G2D		(1<<12)
> +#define S5P_CLKGATE_IP0_G3D		(1<<8)
> +#define S5P_CLKGATE_IP0_IMEM		(1<<5)
> +#define S5P_CLKGATE_IP0_PDMA1		(1<<4)
> +#define S5P_CLKGATE_IP0_PDMA0		(1<<3)
> +#define S5P_CLKGATE_IP0_MDMA		(1<<2)
> +#define S5P_CLKGATE_IP0_DMC1		(1<<1)
> +#define S5P_CLKGATE_IP0_DMC0		(1<<0)
> +#define S5P_CLKGATE_IP0_RESERVED	(0x08feeec0)
> +#define S5P_CLKGATE_IP0_ALWAYS_ON	( S5P_CLKGATE_IP0_DMC1 |\
> +					S5P_CLKGATE_IP0_DMC0 |\
> +					S5P_CLKGATE_IP0_IMEM )
> +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING
> +#define S5P_CLKGATE_IP0_BOOT_ON		( S5P_CLKGATE_IP0_PDMA0
> |\
> +					S5P_CLKGATE_IP0_PDMA1)
> +#else
> +#define S5P_CLKGATE_IP0_BOOT_ON		( S5P_CLKGATE_IP0_PDMA0
> |\
> +					S5P_CLKGATE_IP0_PDMA1 |\
> +					S5P_CLKGATE_IP0_G2D)
> +#endif
> +
> +/* IP Clock Gate 1 Registers */
> +#define S5P_CLKGATE_IP1_NFCON		(1<<28)
> +#define S5P_CLKGATE_IP1_SROMC		(1<<26)
> +#define S5P_CLKGATE_IP1_CFCON		(1<<25)
> +#define S5P_CLKGATE_IP1_NANDXL		(1<<24)
> +#define S5P_CLKGATE_IP1_USBHOST		(1<<17)
> +#define S5P_CLKGATE_IP1_USBOTG		(1<<16)
> +#define S5P_CLKGATE_IP1_HDMI		(1<<11)
> +#define S5P_CLKGATE_IP1_TVENC		(1<<10)
> +#define S5P_CLKGATE_IP1_MIXER		(1<<9)
> +#define S5P_CLKGATE_IP1_VP		(1<<8)
> +#define S5P_CLKGATE_IP1_DSIM		(1<<2)
> +#define S5P_CLKGATE_IP1_MIE		(1<<1)
> +#define S5P_CLKGATE_IP1_FIMD		(1<<0)
> +#define S5P_CLKGATE_IP1_RESERVED	(0xe8fcf0f8)
> +#define S5P_CLKGATE_IP1_ALWAYS_ON	( 0 )
> +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING
> +#define S5P_CLKGATE_IP1_BOOT_ON		( S5P_CLKGATE_IP1_FIMD |\
> +					S5P_CLKGATE_IP1_NANDXL)
> +#else
> +#define S5P_CLKGATE_IP1_BOOT_ON		( S5P_CLKGATE_IP1_FIMD |\
> +					S5P_CLKGATE_IP1_NANDXL |\
> +					S5P_CLKGATE_IP1_USBOTG)
> +#endif
> +
> +
> +/* IP Clock Gate 2 Registers */
> +#define S5P_CLKGATE_IP2_TZIC3		(1<<31)
> +#define S5P_CLKGATE_IP2_TZIC2		(1<<30)
> +#define S5P_CLKGATE_IP2_TZIC1		(1<<29)
> +#define S5P_CLKGATE_IP2_TZIC0		(1<<28)
> +#define S5P_CLKGATE_IP2_VIC3		(1<<27)
> +#define S5P_CLKGATE_IP2_VIC2		(1<<26)
> +#define S5P_CLKGATE_IP2_VIC1		(1<<25)
> +#define S5P_CLKGATE_IP2_VIC0		(1<<24)
> +#define S5P_CLKGATE_IP2_TSI		(1<<20)
> +#define S5P_CLKGATE_IP2_HSMMC3		(1<<19)
> +#define S5P_CLKGATE_IP2_HSMMC2		(1<<18)
> +#define S5P_CLKGATE_IP2_HSMMC1		(1<<17)
> +#define S5P_CLKGATE_IP2_HSMMC0		(1<<16)
> +#define S5P_CLKGATE_IP2_SECJTAG		(1<<11)
> +#define S5P_CLKGATE_IP2_HOSTIF		(1<<10)
> +#define S5P_CLKGATE_IP2_MODEM		(1<<9)
> +#define S5P_CLKGATE_IP2_CORESIGHT	(1<<8)
> +#define S5P_CLKGATE_IP2_SDM		(1<<1)
> +#define S5P_CLKGATE_IP2_SECSS		(1<<0)
> +#define S5P_CLKGATE_IP2_RESERVED	(0xe0f0fc)
> +#define S5P_CLKGATE_IP2_ALWAYS_ON	( S5P_CLKGATE_IP2_TZIC3 |
> S5P_CLKGATE_IP2_TZIC2 |\
> +					S5P_CLKGATE_IP2_TZIC1 |
> S5P_CLKGATE_IP2_TZIC0 |\
> +					S5P_CLKGATE_IP2_VIC3 |
> S5P_CLKGATE_IP2_VIC2 |\
> +					S5P_CLKGATE_IP2_VIC1 |
> S5P_CLKGATE_IP2_VIC0 |\
> +					S5P_CLKGATE_IP2_SECJTAG |
> S5P_CLKGATE_IP2_CORESIGHT |\
> +					S5P_CLKGATE_IP2_SDM |
> S5P_CLKGATE_IP2_SECSS )
> +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING
> +#define S5P_CLKGATE_IP2_BOOT_ON		( 0 )
> +#else
> +#define S5P_CLKGATE_IP2_BOOT_ON		( S5P_CLKGATE_IP2_TSI |\
> +					S5P_CLKGATE_IP2_HSMMC2 |\
> +					S5P_CLKGATE_IP2_HSMMC0 |\
> +					S5P_CLKGATE_IP2_HOSTIF |\
> +					S5P_CLKGATE_IP2_MODEM)
> +#endif
> +
> +
> +/* IP Clock Gate 3 Registers */
> +#define S5P_CLKGATE_IP3_PCM2		(1<<30)
> +#define S5P_CLKGATE_IP3_PCM1		(1<<29)
> +#define S5P_CLKGATE_IP3_PCM0		(1<<28)
> +#define S5P_CLKGATE_IP3_SYSCON		(1<<27)
> +#define S5P_CLKGATE_IP3_GPIO		(1<<26)
> +#define S5P_CLKGATE_IP3_TSADC		(1<<24)
> +#define S5P_CLKGATE_IP3_PWM		(1<<23)
> +#define S5P_CLKGATE_IP3_WDT		(1<<22)
> +#define S5P_CLKGATE_IP3_KEYIF		(1<<21)
> +#define S5P_CLKGATE_IP3_UART3		(1<<20)
> +#define S5P_CLKGATE_IP3_UART2		(1<<19)
> +#define S5P_CLKGATE_IP3_UART1		(1<<18)
> +#define S5P_CLKGATE_IP3_UART0		(1<<17)
> +#define S5P_CLKGATE_IP3_SYSTIMER	(1<<16)
> +#define S5P_CLKGATE_IP3_RTC		(1<<15)
> +#define S5P_CLKGATE_IP3_SPI2		(1<<14)
> +#define S5P_CLKGATE_IP3_SPI1		(1<<13)
> +#define S5P_CLKGATE_IP3_SPI0		(1<<12)
> +#define S5P_CLKGATE_IP3_I2C_HDMI_PHY	(1<<11)
> +#define S5P_CLKGATE_IP3_I2C_HDMI_DDC	(1<<10)
> +#define S5P_CLKGATE_IP3_I2C2		(1<<9)
> +#define S5P_CLKGATE_IP3_I2C1		(1<<8)
> +#define S5P_CLKGATE_IP3_I2C0		(1<<7)
> +#define S5P_CLKGATE_IP3_I2S2		(1<<6)
> +#define S5P_CLKGATE_IP3_I2S1		(1<<5)
> +#define S5P_CLKGATE_IP3_I2S0		(1<<4)
> +#define S5P_CLKGATE_IP3_AC97		(1<<1)
> +#define S5P_CLKGATE_IP3_SPDIF		(1<<0)
> +#define S5P_CLKGATE_IP3_RESERVED	(0x8200000c)
> +#define S5P_CLKGATE_IP3_ALWAYS_ON	( S5P_CLKGATE_IP3_SYSCON |\
> +					S5P_CLKGATE_IP3_GPIO |\
> +					S5P_CLKGATE_IP3_PWM |\
> +					S5P_CLKGATE_IP3_UART0 |\
> +					S5P_CLKGATE_IP3_UART1 |\
> +					S5P_CLKGATE_IP3_UART2 |\
> +					S5P_CLKGATE_IP3_UART3 |\
> +					S5P_CLKGATE_IP3_SYSTIMER |\
> +					S5P_CLKGATE_IP3_I2C0 |\
> +					S5P_CLKGATE_IP3_I2C1 |\
> +					S5P_CLKGATE_IP3_I2C2 |\
> +					S5P_CLKGATE_IP3_RTC )
> +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING
> +#define S5P_CLKGATE_IP3_BOOT_ON		( 0 )
> +#else
> +#define S5P_CLKGATE_IP3_BOOT_ON		( S5P_CLKGATE_IP3_WDT |\
> +					S5P_CLKGATE_IP3_KEYIF |\
> +					S5P_CLKGATE_IP3_I2C_HDMI_PHY )
> +#endif
> +
> +
> +/* IP Clock Gate 4 Registers */
> +#define S5P_CLKGATE_IP4_TZPC3		(1<<8)
> +#define S5P_CLKGATE_IP4_TZPC2		(1<<7)
> +#define S5P_CLKGATE_IP4_TZPC1		(1<<6)
> +#define S5P_CLKGATE_IP4_TZPC0		(1<<5)
> +#define S5P_CLKGATE_IP4_SECKEY		(1<<3)
> +#define S5P_CLKGATE_IP4_IEM_APC		(1<<2)
> +#define S5P_CLKGATE_IP4_IEM_IEC		(1<<1)
> +#define S5P_CLKGATE_IP4_CHIP_ID		(1<<0)
> +#define S5P_CLKGATE_IP4_RESERVED	(0xfffffe10)
> +#define S5P_CLKGATE_IP4_ALWAYS_ON	( S5P_CLKGATE_IP4_TZPC3 |\
> +					S5P_CLKGATE_IP4_TZPC2 |\
> +					S5P_CLKGATE_IP4_TZPC1 |\
> +					S5P_CLKGATE_IP4_TZPC0 )
> +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING
> +#define S5P_CLKGATE_IP4_BOOT_ON		( 0 )
> +#else
> +#define S5P_CLKGATE_IP4_BOOT_ON
> 	( S5P_CLKGATE_IP4_CHIP_ID )
> +#endif
> +
> +
> +/* Block Clock Gate Registers */
> +#define S5P_CLKGATE_BLOCK_INTC		(1<<10)
> +#define S5P_CLKGATE_BLOCK_HSMMC		(1<<9)
> +#define S5P_CLKGATE_BLOCK_DEBUG		(1<<8)
> +#define S5P_CLKGATE_BLOCK_SECURITY	(1<<7)
> +#define S5P_CLKGATE_BLOCK_MEMORY	(1<<6)
> +#define S5P_CLKGATE_BLOCK_USB		(1<<5)
> +#define S5P_CLKGATE_BLOCK_TV		(1<<4)
> +#define S5P_CLKGATE_BLOCK_LCD		(1<<3)
> +#define S5P_CLKGATE_BLOCK_IMG		(1<<2)
> +#define S5P_CLKGATE_BLOCK_MFC		(1<<1)
> +#define S5P_CLKGATE_BLOCK_G3D		(1<<0)
> +
> +/* IP Clock Gate 5 Registers */
> +#define S5P_CLKGATE_IP5_JPEG		(1<<29)
> +#define S5P_CLKGATE_IP5_RESERVED	(0xdfffffff)
> +#define S5P_CLKGATE_IP5_ALWAYS_ON	(0)
> +#ifdef CONFIG_S5PV210_AGGRESSIVE_GATING
> +#define S5P_CLKGATE_IP5_BOOT_ON		(0)
> +#else
> +#define S5P_CLKGATE_IP5_BOOT_ON		( S5P_CLKGATE_IP5_JPEG )
> +#endif
> +
> +/* Bus Clock Gate Registers (hidden) */
> +
> +
> +/* CLK_OUT Registers */
> +#define S5P_CLKOUT_DIV_SHIFT		(20)
> +#define S5P_CLKOUT_DIV_MASK		(0xf <<
> S5P_CLKOUT_DIV_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_SHIFT		(12)
> +#define S5P_CLKOUT_CLKSEL_MASK		(0x1f <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_APLL		(0 <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_MPLL		(1 <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_EPLL		(2 <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_VPLL		(3 <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_SCLK_USBPHY0	(4 <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_SCLK_USBPHY1	(5 <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_SCLK_HDMIPHY	(6 <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_RTC		(7 <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_TICK		(8 <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_HCLK200	(9 << S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_PCLK100	(10 << S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_HCLK166	(11 << S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_PCLK83	(12 << S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_HCLK133	(13 << S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_PCLK66	(14 << S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_ARMCLK	(15 << S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_SCLK_HPM	(16 <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_XXTI		(17 <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_XUSBXTI	(18 << S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_CLKSEL_DOUT		(19 <<
> S5P_CLKOUT_CLKSEL_SHIFT)
> +#define S5P_CLKOUT_DCLKCMP_SHIFT	(8)
> +#define S5P_CLKOUT_DCLKCMP_MASK		(0xf <<
> S5P_CLKOUT_DCLKCMP_SHIFT)
> +#define S5P_CLKOUT_DCLKDIV_SHIFT	(4)
> +#define S5P_CLKOUT_DCLKDIV_MASK		(0xf <<
> S5P_CLKOUT_DCLKDIV_SHIFT)
> +#define S5P_CLKOUT_DCLKSEL_SHIFT	(1)
> +#define S5P_CLKOUT_DCLKSEL_MASK		(0x7 <<
> S5P_CLKOUT_DCLKSEL_SHIFT)
> +#define S5P_CLKOUT_DCLKSEL_XXTI		(0 <<
> S5P_CLKOUT_DCLKSEL_SHIFT)
> +#define S5P_CLKOUT_DCLKSEL_XUSBXTI	(1 <<
> S5P_CLKOUT_DCLKSEL_SHIFT)
> +#define S5P_CLKOUT_DCLKSEL_HDMI27M	(2 <<
> S5P_CLKOUT_DCLKSEL_SHIFT)
> +#define S5P_CLKOUT_DCLKSEL_USBPHY0	(3 <<
> S5P_CLKOUT_DCLKSEL_SHIFT)
> +#define S5P_CLKOUT_DCLKSEL_USBPHY1	(4 <<
> S5P_CLKOUT_DCLKSEL_SHIFT)
> +#define S5P_CLKOUT_DCLKSEL_HDMIPHY	(5 <<
> S5P_CLKOUT_DCLKSEL_SHIFT)
> +#define S5P_CLKOUT_DCLKSEL_FOUTEPLL	(6 <<
> S5P_CLKOUT_DCLKSEL_SHIFT)
> +#define S5P_CLKOUT_DCLKSEL_SCLKEPLL	(7 <<
> S5P_CLKOUT_DCLKSEL_SHIFT)
> +#define S5P_CLKOUT_DCLKEN_SHIFT		(0)
> +#define S5P_CLKOUT_DCLKEN_MASK		(0x1 <<
> S5P_CLKOUT_DCLKEN_SHIFT)
> +#define S5P_CLKOUT_DCLKEN_ENABLE	(1 << S5P_CLKOUT_DCLKEN_SHIFT)
> +#define S5P_CLKOUT_DCLKEN_DISABLE	(0 << S5P_CLKOUT_DCLKEN_SHIFT)
> +
>  /* Registers related to power management */
> +#define S5P_SWRESET		S5P_CLKREG(0x2000)
> +
>  #define S5P_PWR_CFG		S5P_CLKREG(0xC000)
>  #define S5P_EINT_WAKEUP_MASK	S5P_CLKREG(0xC004)
>  #define S5P_WAKEUP_MASK 	S5P_CLKREG(0xC008)
> @@ -112,8 +557,13 @@
> 
>  #define S5P_OTHERS		S5P_CLKREG(0xE000)
>  #define S5P_OM_STAT		S5P_CLKREG(0xE100)
> +#define S5P_MIE_CONTROL		S5P_CLKREG(0xE800)
> +#define S5P_HDMI_PHY_CONTROL	S5P_CLKREG(0xE804)
>  #define S5P_USB_PHY_CONTROL	S5P_CLKREG(0xE80C)
>  #define S5P_DAC_CONTROL		S5P_CLKREG(0xE810)
> +#define S5P_MIPI_DPHY_CONTROL		S5P_CLKREG(0xE814)
> +#define S5P_ADC_CONTROL		S5P_CLKREG(0xE818)
> +#define S5P_PS_HOLD_CONTROL	S5P_CLKREG(0xE81C)
> 
>  #define S5P_INFORM0		S5P_CLKREG(0xF000)
>  #define S5P_INFORM1		S5P_CLKREG(0xF004)
> @@ -159,12 +609,25 @@
>  /* OTHERS Resgister */
>  #define S5P_OTHERS_USB_SIG_MASK		(1 << 16)
>  #define S5P_OTHERS_MIPI_DPHY_EN		(1 << 28)
> +#define S5P_OTHERS_CLKOUT_SHIFT		(8)
> +#define S5P_OTHERS_CLKOUT_MASK		(0x3 <<
> S5P_OTHERS_CLKOUT_SHIFT)
> +#define S5P_OTHERS_CLKOUT_SYSCON	(0 << S5P_OTHERS_CLKOUT_SHIFT)
> +#define S5P_OTHERS_CLKOUT_RESERVED	(1 <<
> S5P_OTHERS_CLKOUT_SHIFT)
> +#define S5P_OTHERS_CLKOUT_XXTI		(2 <<
> S5P_OTHERS_CLKOUT_SHIFT)
> +#define S5P_OTHERS_CLKOUT_XUSBXTI	(3 << S5P_OTHERS_CLKOUT_SHIFT)
> 
>  /* MIPI */
> -#define S5P_MIPI_DPHY_EN		(3)
> +#define S5P_MIPI_DPHY_EN		(3 << 0)
> +
> +/* S5P_MIPI_PHY_CON0 */
> +#define S5P_MIPI_M_RESETN		(1 << 1)
> 
>  /* S5P_DAC_CONTROL */
>  #define S5P_DAC_ENABLE			(1)
>  #define S5P_DAC_DISABLE			(0)
> 
> +#define S5PC110_USB_PHY_CON	S5P_CLKREG(0xE80c)
> +#define S5PC110_USB_PHY0_EN	(1 << 0)
> +#define S5PC110_USB_PHY1_EN	(1 << 1)
> +
>  #endif /* __ASM_ARCH_REGS_CLOCK_H */
> --


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From baruch at tkos.co.il  Tue Jun 15 01:19:05 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Tue, 15 Jun 2010 08:19:05 +0300
Subject: [PATCH 1/2] NUC900:  Add i2c0 driver support for NUC900
In-Reply-To: <4C15143C.1020603@gmail.com>
References: <4C15143C.1020603@gmail.com>
Message-ID: <20100615051905.GD3233@jasper.tkos.co.il>

Hi Wan,

On Mon, Jun 14, 2010 at 01:24:12AM +0800, Wan ZongShun wrote:
> This patch is to add i2c0 driver support for NUC900.
> 
> Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
> 
> ---

[snip]

> +	pdata->get_clock(NULL, NULL, &apbclk_khz);

Why not use clk_get_rate() for this?

baruch

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From viresh.kumar at st.com  Tue Jun 15 01:25:54 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Tue, 15 Jun 2010 10:55:54 +0530
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 PrimeCells
In-Reply-To: <AANLkTim9n-p-Pw6FWvzQMBiAuB3h9ILq1Ya6XWk_0l-c@mail.gmail.com>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>	<4C15C60E.6080404@st.com>
	<AANLkTim9n-p-Pw6FWvzQMBiAuB3h9ILq1Ya6XWk_0l-c@mail.gmail.com>
Message-ID: <4C170EE2.4010706@st.com>

On 6/14/2010 7:09 PM, Linus Walleij wrote:
> Hi Viresh, thanks a lot for reviewing this and I'd be *very* happy if
> you could give it a spin on
> the SPEAr as well!

I would be happy too linus, will do it in few weeks, right now we are running
short of time.

> 
> 2010/6/14 Viresh KUMAR <viresh.kumar at st.com>:
>>> diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
>>> (...)
>>> + * (Bursts are irrelevant for mem to mem transfers - there are no burst
>>> + * signals)
>>
>> I agree that there are no request lines from memories but still we can program
>> them with burst in order to faster the transfer. This burst feature is
>> automatically handled by DMA.
> 
> Actually in the example platform data I set this to the maxburst size
> 256 Bytes, however if I read the manual correctly this is simply ignored
> when you do mem2mem transfers.
> 
> It will simply AHB master the bus until the transaction is finished. That
> is why the manual states:
> 
> "You must program memory-to-memory transfers with a low channel
> priority, otherwise:
> ?    other DMA channels cannot access the bus until the
> memory-to-memory transfer
>      has finished
> ?    other AHB masters cannot perform any transaction."

Yes i have seen them. One more thing i have found related to mem to mem
transfers is:
"You must set this value to the burst size of the destination peripheral,
or if the destination is memory, to the memory boundary size."

>>> +static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
>>> +                         struct pl08x_phy_chan *ch)
>>> +{
>>> +     u32 val;
>>> +
>>> +     /* Wait for channel inactive */
>>> +     val = readl(ch->base + PL080_CH_CONFIG);
>>> +     while (val & PL080_CONFIG_ACTIVE)
>>> +             val = readl(ch->base + PL080_CH_CONFIG);
>>
>> can we use pl08x_phy_channel_busy() instead of above code?
> 
> Fixed.
> 
>>> +     /*
>>> +      * Do not access config register until channel shows as inactive
>>> +      */
>>> +     val = readl(ch->base + PL080_CH_CONFIG);
>>> +     while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
>>> +             val = readl(ch->base + PL080_CH_CONFIG);
>>
>> above 3 fns are always called in order, i.e. pl08x_enable_phy_chan will
>> be called after pl08x_set_cregs, so we may not require these checks
>> here. Is my understanding correct??
> 
> The previous check if the channel is active before proceeding, this check also
> checks the enable bit, this behaviour comes straight from the manual and is
> required to avoid hardware races, so I don't dare to touch it really...
> 

I was talking about the similar check present in pl08x_set_cregs, which will
be called before this routine. pl08x_set_cregs has already checked if channel
is active or not. so checking active in this routine is not required.


>>> +     .device_alloc_chan_resources    = pl08x_alloc_chan_resources,
>>> +     .device_free_chan_resources     = pl08x_free_chan_resources,
>>> +     .device_prep_dma_xor            = NULL,
>>> +     .device_prep_dma_memset         = NULL,
>>> +     .device_prep_dma_interrupt      = pl08x_prep_dma_interrupt,
>>> +     .device_tx_status               = pl08x_dma_tx_status,
>>> +     .device_issue_pending           = pl08x_issue_pending,
>>> +     .device_prep_slave_sg           = pl08x_prep_slave_sg,
>>> +     .device_control                 = pl08x_control,
>>> +};
>>> +
>>
>> One more thing linus, why do we need to create this separation between
>> channels. i.e. few are for memcpy and few for slave_sg. Why don't all
>> channels support everything and this is resolved at runtime.
> 
> This is done in all in-tree drivers, the reason is (I think) that for example
> the dmatest.c test client will look for:
> 
> 	if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
> 		cnt = dmatest_add_threads(dtc, DMA_MEMCPY);
> 		thread_count += cnt > 0 ? cnt : 0;
> 
> So if you want to partition some channels for device I/O (typically some
> which are hard-coded to some devices) and others for memcpy() you create
> a slave instance for the former and a memcpy() instance for the latter.
> 
> In this case we multiplex the memcpy and slave transfers on the few
> physical channels we have, but I haven't finally decided how to handle this:
> perhaps we should always set on physical channel aside for memcpy
> so this won't ever fail, and then this special memcpy device entry will help.
> 
> Ideas? Use cases?

Hmmm. I am not sure, but i think we can't hard code a channel for some device.
All channels should be available with both capabilities. If still there are
some conditions (that you might know), where we need to hard code channels
for devices, then this should come from plat data in some way.



I have few more doubts that i wanted to ask. Are following supported in your
driver, we need them in SPEAr:
 - Configure burst size of source or destination.
 - Configure DMA Master for src or dest.
 - Transfer from Peripheral to Peripheral.
 - Configure Width of src or dest peripheral.
 - Configure Flow controller of transfer.
 - Some callback for fixing Request line multiplexing just before
	initiating transfer.
 - Multiple sg elements in slave_sg transfer. I think it is not supported.
 - Control for autoincrement of addresses, both in case of memory and
	peripherals.


viresh.


From viresh.kumar at st.com  Tue Jun 15 01:32:23 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Tue, 15 Jun 2010 11:02:23 +0530
Subject: [PATCH 0/5] SPEAr3xx: Unify build of SPEAr3xx platforms
In-Reply-To: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <4C171067.1060102@st.com>

On 6/5/2010 11:35 AM, Ryan Mallon wrote:
> Rework the SPEAr3xx code to allow all three SPEAr3xx platforms to be
> built into a single kernel.
> 
> I do not have access to any SPEAr3xx hardware, so the patch series is
> build tested only.
> 
> Ryan Mallon (5):
>   SPEAr3xx: Make local structres static
>   SPEAR3xx: Rename register/irq defines to remove naming conflicts
>   SPEAr3xx: Rework pmx_dev code to remove conflicts
>   SPEAr3xx: Rework KConfig to allow all boards to be compiled in
>   SPEAr3xx: Replace defconfigs with single unfied defconfig
> 
>  arch/arm/configs/spear300_defconfig            |  773 -----------------------
>  arch/arm/configs/spear310_defconfig            |  775 ------------------------
>  arch/arm/configs/spear320_defconfig            |  775 ------------------------
>  arch/arm/configs/spear3xx_defconfig            |  775 ++++++++++++++++++++++++
>  arch/arm/mach-spear3xx/Kconfig                 |   30 +-
>  arch/arm/mach-spear3xx/Kconfig300              |   17 -
>  arch/arm/mach-spear3xx/Kconfig310              |   17 -
>  arch/arm/mach-spear3xx/Kconfig320              |   17 -
>  arch/arm/mach-spear3xx/include/mach/generic.h  |  139 ++---
>  arch/arm/mach-spear3xx/include/mach/irqs.h     |  195 +++---
>  arch/arm/mach-spear3xx/include/mach/spear300.h |   26 +-
>  arch/arm/mach-spear3xx/include/mach/spear310.h |   44 +-
>  arch/arm/mach-spear3xx/include/mach/spear320.h |   50 +-
>  arch/arm/mach-spear3xx/spear300.c              |  135 ++--
>  arch/arm/mach-spear3xx/spear300_evb.c          |   26 +-
>  arch/arm/mach-spear3xx/spear310.c              |  137 +++--
>  arch/arm/mach-spear3xx/spear310_evb.c          |   42 +-
>  arch/arm/mach-spear3xx/spear320.c              |  247 ++++----
>  arch/arm/mach-spear3xx/spear320_evb.c          |   36 +-
>  arch/arm/mach-spear3xx/spear3xx.c              |  124 ++--
>  20 files changed, 1387 insertions(+), 2993 deletions(-)
>  delete mode 100644 arch/arm/configs/spear300_defconfig
>  delete mode 100644 arch/arm/configs/spear310_defconfig
>  delete mode 100644 arch/arm/configs/spear320_defconfig
>  create mode 100644 arch/arm/configs/spear3xx_defconfig
>  delete mode 100644 arch/arm/mach-spear3xx/Kconfig300
>  delete mode 100644 arch/arm/mach-spear3xx/Kconfig310
>  delete mode 100644 arch/arm/mach-spear3xx/Kconfig320
> 
> 

Ryan,

Patches looks fine to me, but i need to test them before i Ack them.
Please give me some time to do that, currently i am very busy in some other
activities.

viresh.


From kgene.kim at samsung.com  Tue Jun 15 01:59:51 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 15 Jun 2010 14:59:51 +0900
Subject: [PATCH 3/6] S5PV210 added register mappings
In-Reply-To: <1276504755-24741-4-git-send-email-MyungJoo.Ham@samsung.com>
References: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-2-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-3-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-4-git-send-email-MyungJoo.Ham@samsung.com>
Message-ID: <009501cb0c50$079fc7e0$16df57a0$%kim@samsung.com>

MyungJoo Ham wrote:
> 

Where is commit message?
Needs comment why this patch needs.

> Signed-off-by: MyungJoo Ham <MyungJoo.Ham at samsung.com>
> ---
>  arch/arm/mach-s5pv210/include/mach/map.h |   45
> ++++++++++++++++++++++++++++++
>  1 files changed, 45 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-
> s5pv210/include/mach/map.h
> index 34eb168..e1a6ff8 100644
> --- a/arch/arm/mach-s5pv210/include/mach/map.h
> +++ b/arch/arm/mach-s5pv210/include/mach/map.h
> @@ -54,6 +54,9 @@
> 
>  #define S5PV210_PA_SROMC	(0xE8000000)
> 
> +/* DMA */

No need above comment.
We know _PA_DMA means physical address of DMA.

> +#define S5PV210_PA_DMA          (0xFA200000)
> +#define S5PV210_PA_PDMA         (0xE0900000)
>  #define S5PV210_PA_MDMA		0xFA200000
>  #define S5PV210_PA_PDMA0	0xE0900000
>  #define S5PV210_PA_PDMA1	0xE0A00000
> @@ -77,6 +80,25 @@
>  #define S5PV210_PA_SDRAM	(0x20000000)
>  #define S5P_PA_SDRAM		S5PV210_PA_SDRAM
> 
> +#define S5PV210_PA_RTC          (0xE2800000)
> +
> +#define S5PV210_PA_PWR          (0xE010C000)
> +#define S5P_PA_PWR              S5PV210_PA_PWR
> +#define S5P_PA_INFORM0          (S5P_PA_PWR + 0x3000)
> +
> +/* USB HS OTG */
> +#define S5PV210_PA_USB_HSOTG    (0xEC000000)
> +#define S5PV210_PA_USB_HSPHY    (0xEC100000)
> +
> +/* FIMC */
> +#define S5PV210_PA_FIMC0        (0xFB200000)
> +#define S5PV210_PA_FIMC1        (0xFB300000)
> +#define S5PV210_PA_FIMC2        (0xFB400000)
> +
> +/* MFC */
> +#define S5PV210_PA_MFC          (0xF1700000)
> +#define S5PV210_SZ_MFC          (0x0000FFFF)
> +
>  /* I2S */
>  #define S5PV210_PA_IIS0		0xEEE30000
>  #define S5PV210_PA_IIS1		0xE2100000
> @@ -87,6 +109,17 @@
>  #define S5PV210_PA_PCM1		0xE1200000
>  #define S5PV210_PA_PCM2		0xE2B00000
> 
> +/* Audio SubSystem */
> +#define S5PV210_PA_AUDSS        (0xEEE10000)
> +
> +/* TZPC */
> +#define S5PV210_PA_TZPC0        (0xF1500000)
> +#define S5PV210_PA_TZPC1        (0xFAD00000)
> +#define S5PV210_PA_TZPC2        (0xE0600000)
> +#define S5PV210_PA_TZPC3        (0xE1C00000)
> +
> +#define S5PV210_VA_TZPC(x)      (S3C_ADDR(0x01700000) + ((x) * 0x10000))
> +
>  /* AC97 */
>  #define S5PV210_PA_AC97		0xE2200000
> 
> @@ -101,6 +134,18 @@
>  #define S3C_PA_IIC1		S5PV210_PA_IIC1
>  #define S3C_PA_IIC2		S5PV210_PA_IIC2
>  #define S3C_PA_FB		S5PV210_PA_FB
> +#define S3C_PA_USB_HSOTG        S5PV210_PA_USB_HSOTG
> +#define S3C_PA_USB_HSPHY        S5PV210_PA_USB_HSPHY
> +#define S3C_PA_RTC              S5PV210_PA_RTC
> +#define S5P_PA_FIMC0            S5PV210_PA_FIMC0
> +#define S5P_PA_FIMC1            S5PV210_PA_FIMC1
> +#define S5P_PA_FIMC2            S5PV210_PA_FIMC2
> +#define S3C_PA_DMA              S5PV210_PA_DMA
> +#define S3C_PA_PDMA             S5PV210_PA_PDMA
> +#define S3C_PA_IIS_V50          S5PV210_PA_IIS0
> +#define S3C_PA_ADC              S5PV210_PA_ADC(0)
> +#define S3C_PA_ADC0             S5PV210_PA_ADC(0)
> +#define S3C_PA_ADC1             S5PV210_PA_ADC(1)
>  #define S3C_PA_WDT		S5PV210_PA_WATCHDOG
> 
>  #define SAMSUNG_PA_ADC		S5PV210_PA_ADC
> --

I don't know why above mappings need now.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Tue Jun 15 02:05:13 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 15 Jun 2010 15:05:13 +0900
Subject: [PATCH 1/6] S5PV210 Add IRQ/EINT register information for the CPU.
In-Reply-To: <1276504755-24741-2-git-send-email-MyungJoo.Ham@samsung.com>
References: <1276504755-24741-1-git-send-email-MyungJoo.Ham@samsung.com>
	<1276504755-24741-2-git-send-email-MyungJoo.Ham@samsung.com>
Message-ID: <009601cb0c50$c04e3920$40eaab60$%kim@samsung.com>

MyungJoo Ham wrote:
> 
> Signed-off-by: MyungJoo Ham <MyungJoo.Ham at samsung.com>

Is above your e-mail right? myungjoo.ham or MyungJoo.Ham?

> ---
>  arch/arm/mach-s5pv210/include/mach/irqs.h     |    9 +++++++++
>  arch/arm/mach-s5pv210/include/mach/regs-irq.h |    6 ++++++
>  2 files changed, 15 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-
> s5pv210/include/mach/irqs.h
> index 9689537..6c5f491 100644
> --- a/arch/arm/mach-s5pv210/include/mach/irqs.h
> +++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
> @@ -118,9 +118,18 @@
>  #define IRQ_MDNIE3		S5P_IRQ_VIC3(8)
>  #define IRQ_VIC_END		S5P_IRQ_VIC3(31)
> 
> +/* External interrupt */
> +

No need above comment.
Because xxx_EINT_xxx means External Interrupt blah...

>  #define S5P_EINT_BASE1		(S5P_IRQ_VIC0(0))
>  #define S5P_EINT_BASE2		(IRQ_VIC_END + 1)
> 
> +#define S5P_EINT(x)             (S5P_EINT_BASE2 + ((x) - 16))
> +#define IRQ_EINT_BIT(x) ((x) < IRQ_EINT16_31 ? (x) - S5P_VIC0_BASE : (x) -
> S5P_EINT(0))
> +

IRQ_EINT_BIT is same as EINT_OFFSET.
In your patch set, could not find where you has used IRQ_EINT_BIT!!

> +/* GPIO interrupt */
> +#define S5P_IRQ_GPIO_BASE       (IRQ_EINT(31) + 1)
> +#define S5P_IRQ_GPIO(x)         (S5P_IRQ_GPIO_BASE + (x))
> +
>  /* Set the default NR_IRQS */
>  #define NR_IRQS			(IRQ_EINT(31) + 1)
> 
> diff --git a/arch/arm/mach-s5pv210/include/mach/regs-irq.h b/arch/arm/mach-
> s5pv210/include/mach/regs-irq.h
> index 5c3b104..139604f 100644
> --- a/arch/arm/mach-s5pv210/include/mach/regs-irq.h
> +++ b/arch/arm/mach-s5pv210/include/mach/regs-irq.h
> @@ -16,4 +16,10 @@
>  #include <asm/hardware/vic.h>
>  #include <mach/map.h>
> 
> +/* interrupt controller */
> +#define S5PV210_VIC0REG(x)                      ((x) + VA_VIC0)
> +#define S5PV210_VIC1REG(x)                      ((x) + VA_VIC1)
> +#define S5PV210_VIC2REG(x)                      ((x) + VA_VIC2)
> +#define S5PV210_VIC3REG(x)                      ((x) + VA_VIC3)
> +

Also not used anywhere in your patch set...

>  #endif /* __ASM_ARCH_REGS_IRQ_H */
> --
> 1.6.3.3
> 
> 

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From daniel at caiaq.de  Tue Jun 15 02:31:43 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Tue, 15 Jun 2010 08:31:43 +0200
Subject: mxcmmc driver hangs on sync
In-Reply-To: <20100615112936.5d03ce92@morgan>
References: <20100615112936.5d03ce92@morgan>
Message-ID: <20100615063142.GU17833@buzzloop.caiaq.de>

Hi,

On Tue, Jun 15, 2010 at 11:29:36AM +0800, Morgan Howe wrote:
> With the older kernel this would hang on sync after a few thousand
> loops, and much sooner if you ran 2 or 3 of these processes at a time.
> I tried last night with the newer kernel and kicking off 3 processes
> and after ~100-150 loops per process I get this:

Which 'newer kernel' did you try?

Daniel


From ryan at bluewatersys.com  Tue Jun 15 02:49:00 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Tue, 15 Jun 2010 18:49:00 +1200
Subject: [PATCH 0/5] SPEAr3xx: Unify build of SPEAr3xx platforms
In-Reply-To: <4C171067.1060102@st.com>
References: <1275717955-14545-1-git-send-email-ryan@bluewatersys.com>
	<4C171067.1060102@st.com>
Message-ID: <4C17225C.8030201@bluewatersys.com>

Viresh KUMAR wrote:
> On 6/5/2010 11:35 AM, Ryan Mallon wrote:
>> Rework the SPEAr3xx code to allow all three SPEAr3xx platforms to be
>> built into a single kernel.
>>
>> I do not have access to any SPEAr3xx hardware, so the patch series is
>> build tested only.
>>
>> Ryan Mallon (5):
>>   SPEAr3xx: Make local structres static
>>   SPEAR3xx: Rename register/irq defines to remove naming conflicts
>>   SPEAr3xx: Rework pmx_dev code to remove conflicts
>>   SPEAr3xx: Rework KConfig to allow all boards to be compiled in
>>   SPEAr3xx: Replace defconfigs with single unfied defconfig
> 
> Ryan,
> 
> Patches looks fine to me, but i need to test them before i Ack them.
> Please give me some time to do that, currently i am very busy in some other
> activities.
> 
> viresh.

Thanks, let me know if you need help with the code at all.

~Ryan




From mhowe at cwlinux.com  Tue Jun 15 03:20:51 2010
From: mhowe at cwlinux.com (Morgan Howe)
Date: Tue, 15 Jun 2010 15:20:51 +0800
Subject: mxcmmc driver hangs on sync
In-Reply-To: <20100615063142.GU17833@buzzloop.caiaq.de>
References: <20100615112936.5d03ce92@morgan>
	<20100615063142.GU17833@buzzloop.caiaq.de>
Message-ID: <20100615152051.26e4589c@morgan>

On Tue, 15 Jun 2010 08:31:43 +0200
Daniel Mack <daniel at caiaq.de> wrote:

> Hi,
> 
> On Tue, Jun 15, 2010 at 11:29:36AM +0800, Morgan Howe wrote:
> > With the older kernel this would hang on sync after a few thousand
> > loops, and much sooner if you ran 2 or 3 of these processes at a
> > time. I tried last night with the newer kernel and kicking off 3
> > processes and after ~100-150 loops per process I get this:
> 
> Which 'newer kernel' did you try?

Hey Daniel,

Sorry, I said current mainline, but actually it's 2.6.35-rc1.

Regards,
Morgan


From daniel at caiaq.de  Tue Jun 15 03:22:37 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Tue, 15 Jun 2010 09:22:37 +0200
Subject: mxcmmc driver hangs on sync
In-Reply-To: <20100615152051.26e4589c@morgan>
References: <20100615112936.5d03ce92@morgan>
	<20100615063142.GU17833@buzzloop.caiaq.de>
	<20100615152051.26e4589c@morgan>
Message-ID: <20100615072237.GW17833@buzzloop.caiaq.de>

On Tue, Jun 15, 2010 at 03:20:51PM +0800, Morgan Howe wrote:
> On Tue, 15 Jun 2010 08:31:43 +0200
> Daniel Mack <daniel at caiaq.de> wrote:
> > On Tue, Jun 15, 2010 at 11:29:36AM +0800, Morgan Howe wrote:
> > > With the older kernel this would hang on sync after a few thousand
> > > loops, and much sooner if you ran 2 or 3 of these processes at a
> > > time. I tried last night with the newer kernel and kicking off 3
> > > processes and after ~100-150 loops per process I get this:
> > 
> > Which 'newer kernel' did you try?
> 
> Hey Daniel,
> 
> Sorry, I said current mainline, but actually it's 2.6.35-rc1.

Could you try two things:

a) build a kernel without MX2 DMA support
b) try 2.6.34, as there were some updates to the mxcmmc driver after
   2.6.34 which could be related

Daniel


From langabe at gmail.com  Tue Jun 15 03:58:26 2010
From: langabe at gmail.com (Alex Gonzalez)
Date: Tue, 15 Jun 2010 09:58:26 +0200
Subject: Hung kernel on SD writeback while suspending to RAM
Message-ID: <AANLkTikHHcnJygPWKAlDk4NWGBE_fxexeLt3WO0xea0M@mail.gmail.com>

Hi,

I am looking into suspend to RAM on a Freescale MX51 running a 2.6.31
kernel. The
system suspends and resumes OK except when an SD card is mounted.

What happens then is that it finds a page which is being written to disk
(writeback flag is set), so it waits forever in uninterruptible state for
the write to finish, which never happens.

I was expecting the filesystem sync previous to the tasks freezing to have
written all page caches to disk.

Any suggestion as to how to debug this forward?

Thanks in advance,
Alex

INFO: task sh:595 blocked for more than 120 seconds.
"echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
sh D c02be320 0 595 1 0x00000000
[<c02be320>] (schedule+0x300/0x344) from [<c02be388>]
(io_schedule+0x24/0x40)
[<c02be388>] (io_schedule+0x24/0x40) from [<c006fe18>]
(sync_page+0x38/0x40)
[<c006fe18>] (sync_page+0x38/0x40) from [<c02be68c>]
(__wait_on_bit+0x54/0x9c)
[<c02be68c>] (__wait_on_bit+0x54/0x9c) from [<c0070070>]
(wait_on_page_bit+0xb4/0xcc)
[<c0070070>] (wait_on_page_bit+0xb4/0xcc) from
[<c0075fc8>] (write_cache_pages+0x1fc/0x37c)
[<c0075fc8>] (write_cache_pages+0x1fc/0x37c) from
[<c00761ac>] (do_writepages+0x3c/0x54)
[<c00761ac>] (do_writepages+0x3c/0x54) from
[<c0070a80>] (__filemap_fdatawrite_range+0x64/0x6c)
[<c0070a80>] (__filemap_fdatawrite_range+0x64/0x6c) from
[<c00714c4>] (filemap_fdatawrite+0x28/0x30)
[<c00714c4>] (filemap_fdatawrite+0x28/0x30) from
[<c00714e4>] (filemap_write_and_wait+0x18/0x3c)
[<c00714e4>] (filemap_write_and_wait+0x18/0x3c) from
[<c00b2e68>] (fsync_bdev+0x18/0x38)
[<c00b2e68>] (fsync_bdev+0x18/0x38) from [<c013d3bc>]
(invalidate_partition+0x18/0x34)
[<c013d3bc>] (invalidate_partition+0x18/0x34) from [<c00ca6e0>]
(del_gendisk+0x28/0xc8)
[<c00ca6e0>] (del_gendisk+0x28/0xc8) from [<c01e4c88>]
(mmc_blk_remove+0x20/0x3c)
[<c01e4c88>] (mmc_blk_remove+0x20/0x3c) from [<c01e0688>]
(mmc_bus_remove+0x18/0x20)
[<c01e0688>] (mmc_bus_remove+0x18/0x20) from
[<c01872f8>] (__device_release_driver+0x64/0xa4)
[<c01872f8>] (__device_release_driver+0x64/0xa4) from
[<c01873dc>] (device_release_driver+0x1c/0x28)
[<c01873dc>] (device_release_driver+0x1c/0x28) from
[<c01869f8>] (bus_remove_device+0x9c/0xac)
[<c01869f8>] (bus_remove_device+0x9c/0xac) from [<c01852d0>]
(device_del+0x110/0x16c)
[<c01852d0>] (device_del+0x110/0x16c) from [<c01e073c>]
(mmc_remove_card+0x4c/0x60)
[<c01e073c>] (mmc_remove_card+0x4c/0x60) from [<c01e1b70>]
(mmc_sd_remove+0x24/0x30)
[<c01e1b70>] (mmc_sd_remove+0x24/0x30) from [<c01e001c>]
(mmc_suspend_host+0xc4/0x188)
[<c01e001c>] (mmc_suspend_host+0xc4/0x188) from [<c01e6860>]
(sdhci_suspend+0x58/0x120)
[<c01e6860>] (sdhci_suspend+0x58/0x120) from
[<c0188378>] (platform_pm_suspend+0x48/0x54)
[<c0188378>] (platform_pm_suspend+0x48/0x54) from [<c018a098>]
(pm_op+0x30/0x7c)
[<c018a098>] (pm_op+0x30/0x7c) from [<c018a86c>]
(dpm_suspend_start+0x3ac/0x50c)
[<c018a86c>] (dpm_suspend_start+0x3ac/0x50c) from
[<c006b560>] (suspend_devices_and_enter+0x3c/0x1c4)
[<c006b560>] (suspend_devices_and_enter+0x3c/0x1c4) from
[<c006b7a0>] (enter_state+0xb8/0x118)
[<c006b7a0>] (enter_state+0xb8/0x118) from [<c006afbc>]
(state_store+0xa0/0xbc)  [<c006afbc>] (state_store+0xa0/0xbc) from
[<c0146cd4>] (kobj_attr_store+0x18/0x1c)
[<c0146cd4>] (kobj_attr_store+0x18/0x1c) from
[<c00cbd24>] (sysfs_write_file+0x108/0x13c)
[<c00cbd24>] (sysfs_write_file+0x108/0x13c) from [<c008f7cc>]
(vfs_write+0xac/0x128)  [<c008f7cc>] (vfs_write+0xac/0x128) from
[<c008f8f4>] (sys_write+0x3c/0x68)
[<c008f8f4>] (sys_write+0x3c/0x68) from [<c0025e80>] (ret_fast_
-------------- next part --------------
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From kgene.kim at samsung.com  Tue Jun 15 06:25:08 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 15 Jun 2010 19:25:08 +0900
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 PrimeCells
In-Reply-To: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <002001cb0c75$0a54fd00$1efef700$%kim@samsung.com>

Linus Walleij wrote:
> 
> This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells
> based on the implementation earlier submitted by Peter Pearse.
> This is working like a charm for memcpy on the PB11MPCore, but
> slave DMA to devices is still not working.
> 
> This DMA controller is used in mostly unmodified form in the ARM
> RealView and Versatile platforms, in the ST-Ericsson Nomadik, and
> in the ST SPEAr platform.
> 
> It has been converted to use the header from the Samsung PL080
> derivate instead of its own defintions, and can potentially support
> several controllers in the same system.
> 
> Cc: Peter Pearse <peter.pearse at arm.com>
> Cc: Ben Dooks <ben-linux at fluff.org>
> Cc: Kukjin Kim <kgene.kim at samsung.com>

Looks good, but please give me some time to test on the board(SMDK6410).
If any problem, let you know. Of course no problem, will ack.

> Cc: Alessandro Rubini <rubini at unipv.it>
> Cc: Viresh Kumar <viresh.kumar at st.com>
> Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
> ---
>  arch/arm/include/asm/hardware/pl080.h |    2 +
>  drivers/dma/Kconfig                   |    9 +
>  drivers/dma/Makefile                  |    1 +
>  drivers/dma/amba-pl08x.c              | 1925
> +++++++++++++++++++++++++++++++++
>  include/linux/amba/pl08x.h            |  173 +++
>  5 files changed, 2110 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/dma/amba-pl08x.c
>  create mode 100644 include/linux/amba/pl08x.h
> 
(snip)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From mhowe at cwlinux.com  Tue Jun 15 06:32:00 2010
From: mhowe at cwlinux.com (Morgan Howe)
Date: Tue, 15 Jun 2010 18:32:00 +0800
Subject: mxcmmc driver hangs on sync
In-Reply-To: <20100615072237.GW17833@buzzloop.caiaq.de>
References: <20100615112936.5d03ce92@morgan>
	<20100615063142.GU17833@buzzloop.caiaq.de>
	<20100615152051.26e4589c@morgan>
	<20100615072237.GW17833@buzzloop.caiaq.de>
Message-ID: <20100615183200.45164c20@morgan>

Hey Daniel,


On Tue, 15 Jun 2010 09:22:37 +0200
Daniel Mack <daniel at caiaq.de> wrote:
> Could you try two things:
> 
> a) build a kernel without MX2 DMA support

I did this and ran the test again several times and the behavior seemed
basically the same.

Around 100 times, write the file to each SD and sync.
Then finally:

mxc-mmc mxc-mmc.0: mxcmci_finish_data: No CRC -ETIMEDOUT
mmcblk0: error -110 transferring data, sector 29692583, nr 512, card
status 0xc00 end_request: I/O error, dev mmcblk0, sector 29692863
... <snip ~20 similar I/O errors for other sectors>

After this it continues to write without problems and eventually:

Loop: 159
Loop: 162
Loop: 164
Loop: 187
mxc-mmc mxc-mmc.0: mxcmci_finish_data: No CRC -ETIMEDOUT
mmcblk0: error -110 transferring data, sector 29517031, nr 96, card
status 0xc00 end_request: I/O error, dev mmcblk0, sector 29517125

Loop # represents the number of times each of the four processes has
copied to SD1, copied from SD1 to SD2, and then called sync.  It
continues after this error again and then:

Loop: 228
Loop: 233
Loop: 231
Loop: 257
mxc-mmc mxc-mmc.1: mxcmci_finish_data: No CRC -ETIMEDOUT
mmcblk1: error -110 transferring data, sector 22419455, nr 56, card
status 0xc00

At this point I can see that all four of the test scripts are stuck
at calling sync.

> b) try 2.6.34, as there were some updates to the mxcmmc driver after
>    2.6.34 which could be related

I will try this, but may need a bit more time.

Regards,
Morgan


From w.sang at pengutronix.de  Tue Jun 15 06:34:22 2010
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Tue, 15 Jun 2010 12:34:22 +0200
Subject: [PATCH 1/2] otg/ulpi: bail out on read errors
Message-ID: <1276598063-3956-1-git-send-email-w.sang@pengutronix.de>

otg_read may return errnos, so bail out correctly to prevent bogus
ID-numbers.

Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Daniel Mack <daniel at caiaq.de>
Cc: Greg KH <gregkh at suse.de>
---
 drivers/usb/otg/ulpi.c |   15 ++++++++++-----
 1 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/drivers/usb/otg/ulpi.c b/drivers/usb/otg/ulpi.c
index b1b3469..d331b22 100644
--- a/drivers/usb/otg/ulpi.c
+++ b/drivers/usb/otg/ulpi.c
@@ -59,12 +59,17 @@ static int ulpi_set_flags(struct otg_transceiver *otg)
 
 static int ulpi_init(struct otg_transceiver *otg)
 {
-	int i, vid, pid;
-
-	vid = (otg_io_read(otg, ULPI_VENDOR_ID_HIGH) << 8) |
-	       otg_io_read(otg, ULPI_VENDOR_ID_LOW);
-	pid = (otg_io_read(otg, ULPI_PRODUCT_ID_HIGH) << 8) |
-	       otg_io_read(otg, ULPI_PRODUCT_ID_LOW);
+	int i, vid, pid, ret;
+	u32 ulpi_id = 0;
+
+	for (i = 0; i < 4; i++) {
+		ret = otg_io_read(otg, ULPI_PRODUCT_ID_HIGH - i);
+		if (ret < 0)
+			return ret;
+		ulpi_id = (ulpi_id << 8) | ret;
+	}
+	vid = ulpi_id & 0xffff;
+	pid = ulpi_id >> 16;
 
 	pr_info("ULPI transceiver vendor/product ID 0x%04x/0x%04x\n", vid, pid);
 
-- 
1.7.1



From w.sang at pengutronix.de  Tue Jun 15 06:34:23 2010
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Tue, 15 Jun 2010 12:34:23 +0200
Subject: [PATCH 2/2] ehci-mxc: bail out on transceiver problems
In-Reply-To: <1276598063-3956-1-git-send-email-w.sang@pengutronix.de>
References: <1276598063-3956-1-git-send-email-w.sang@pengutronix.de>
Message-ID: <1276598063-3956-2-git-send-email-w.sang@pengutronix.de>

The old code registered the hcd even if there were no transceivers
detected, leading to oopses like this if we try to probe a non-existant
ULPI:

[    2.730000] mxc-ehci mxc-ehci.0: unable to init transceiver
[    2.740000] timeout polling for ULPI device
[    2.740000] timeout polling for ULPI device
[    2.750000] mxc-ehci mxc-ehci.0: unable to enable vbus on transceiver
[    2.750000] mxc-ehci mxc-ehci.0: Freescale On-Chip EHCI Host Controller
[    2.760000] mxc-ehci mxc-ehci.0: new USB bus registered, assigned bus number 2
[    2.770000] Unhandled fault: external abort on non-linefetch (0x808) at 0xc4876184
[    2.770000] Internal error: : 808 [#1] PREEMPT
[    2.770000] last sysfs file:
[    2.770000] Modules linked in:
[    2.770000] CPU: 0    Not tainted  (2.6.33.5 #5)
[    2.770000] PC is at ehci_hub_control+0x4d4/0x8f8
[    2.770000] LR is at ehci_mxc_setup+0xbc/0xdc
[    2.770000] pc : [<c0196dfc>]    lr : [<c019bc8c>]    psr: 00000093
[    2.770000] sp : c3815e40  ip : 00000001  fp : 60000013
[    2.770000] r10: c4876184  r9 : 00000000  r8 : c3814000
[    2.770000] r7 : c391d2cc  r6 : 00000001  r5 : 00000001  r4 : 00000000
[    2.770000] r3 : 80000000  r2 : 00000007  r1 : 80000000  r0 : c4876184
[    2.770000] Flags: nzcv  IRQs off  FIQs on  Mode SVC_32  ISA ARM Segment kernel
[    2.770000] Control: 0005317f  Table: a0004000  DAC: 00000017
[    2.770000] Process swapper (pid: 1, stack limit = 0xc3814270)
...

Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: Daniel Mack <daniel at caiaq.de>
Cc: Greg KH <gregkh at suse.de>
Cc: stable at kernel.org
---
 drivers/usb/host/ehci-mxc.c |   13 ++++++++++---
 1 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index 544ccfd..bd40277 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -207,10 +207,17 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
 	/* Initialize the transceiver */
 	if (pdata->otg) {
 		pdata->otg->io_priv = hcd->regs + ULPI_VIEWPORT_OFFSET;
-		if (otg_init(pdata->otg) != 0)
-			dev_err(dev, "unable to init transceiver\n");
-		else if (otg_set_vbus(pdata->otg, 1) != 0)
+		ret = otg_init(pdata->otg);
+		if (ret) {
+			dev_err(dev, "unable to init transceiver, probably missing\n");
+			ret = -ENODEV;
+			goto err_add;
+		}
+		ret = otg_set_vbus(pdata->otg, 1);
+		if (ret) {
 			dev_err(dev, "unable to enable vbus on transceiver\n");
+			goto err_add;
+		}
 	}
 
 	priv->hcd = hcd;
-- 
1.7.1



From daniel at caiaq.de  Tue Jun 15 06:39:45 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Tue, 15 Jun 2010 12:39:45 +0200
Subject: [PATCH 1/2] otg/ulpi: bail out on read errors
In-Reply-To: <1276598063-3956-1-git-send-email-w.sang@pengutronix.de>
References: <1276598063-3956-1-git-send-email-w.sang@pengutronix.de>
Message-ID: <20100615103945.GD17833@buzzloop.caiaq.de>

On Tue, Jun 15, 2010 at 12:34:22PM +0200, Wolfram Sang wrote:
> otg_read may return errnos, so bail out correctly to prevent bogus
> ID-numbers.
> 
> Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>

Acked-by: Daniel Mack <daniel at caiaq.de>

> Cc: Greg KH <gregkh at suse.de>
> ---
>  drivers/usb/otg/ulpi.c |   15 ++++++++++-----
>  1 files changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/usb/otg/ulpi.c b/drivers/usb/otg/ulpi.c
> index b1b3469..d331b22 100644
> --- a/drivers/usb/otg/ulpi.c
> +++ b/drivers/usb/otg/ulpi.c
> @@ -59,12 +59,17 @@ static int ulpi_set_flags(struct otg_transceiver *otg)
>  
>  static int ulpi_init(struct otg_transceiver *otg)
>  {
> -	int i, vid, pid;
> -
> -	vid = (otg_io_read(otg, ULPI_VENDOR_ID_HIGH) << 8) |
> -	       otg_io_read(otg, ULPI_VENDOR_ID_LOW);
> -	pid = (otg_io_read(otg, ULPI_PRODUCT_ID_HIGH) << 8) |
> -	       otg_io_read(otg, ULPI_PRODUCT_ID_LOW);
> +	int i, vid, pid, ret;
> +	u32 ulpi_id = 0;
> +
> +	for (i = 0; i < 4; i++) {
> +		ret = otg_io_read(otg, ULPI_PRODUCT_ID_HIGH - i);
> +		if (ret < 0)
> +			return ret;
> +		ulpi_id = (ulpi_id << 8) | ret;
> +	}
> +	vid = ulpi_id & 0xffff;
> +	pid = ulpi_id >> 16;
>  
>  	pr_info("ULPI transceiver vendor/product ID 0x%04x/0x%04x\n", vid, pid);
>  
> -- 
> 1.7.1
> 


From daniel at caiaq.de  Tue Jun 15 06:43:42 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Tue, 15 Jun 2010 12:43:42 +0200
Subject: [PATCH 2/2] ehci-mxc: bail out on transceiver problems
In-Reply-To: <1276598063-3956-2-git-send-email-w.sang@pengutronix.de>
References: <1276598063-3956-1-git-send-email-w.sang@pengutronix.de>
	<1276598063-3956-2-git-send-email-w.sang@pengutronix.de>
Message-ID: <20100615104342.GE17833@buzzloop.caiaq.de>

On Tue, Jun 15, 2010 at 12:34:23PM +0200, Wolfram Sang wrote:
> The old code registered the hcd even if there were no transceivers
> detected, leading to oopses like this if we try to probe a non-existant
> ULPI:

Hmm. I'm aware that there was a missing bail in this function, but
actually, I had hardware which didn't properly detect the ULPI chip but
still worked fine. There has been quite some discussion here about that,
and eventually I decided to not make this a hard error as it didn't
really harm.

> [    2.730000] mxc-ehci mxc-ehci.0: unable to init transceiver
> [    2.740000] timeout polling for ULPI device
> [    2.740000] timeout polling for ULPI device
> [    2.750000] mxc-ehci mxc-ehci.0: unable to enable vbus on transceiver
> [    2.750000] mxc-ehci mxc-ehci.0: Freescale On-Chip EHCI Host Controller
> [    2.760000] mxc-ehci mxc-ehci.0: new USB bus registered, assigned bus number 2
> [    2.770000] Unhandled fault: external abort on non-linefetch (0x808) at 0xc4876184
> [    2.770000] Internal error: : 808 [#1] PREEMPT
> [    2.770000] last sysfs file:
> [    2.770000] Modules linked in:
> [    2.770000] CPU: 0    Not tainted  (2.6.33.5 #5)
> [    2.770000] PC is at ehci_hub_control+0x4d4/0x8f8
> [    2.770000] LR is at ehci_mxc_setup+0xbc/0xdc
> [    2.770000] pc : [<c0196dfc>]    lr : [<c019bc8c>]    psr: 00000093
> [    2.770000] sp : c3815e40  ip : 00000001  fp : 60000013
> [    2.770000] r10: c4876184  r9 : 00000000  r8 : c3814000
> [    2.770000] r7 : c391d2cc  r6 : 00000001  r5 : 00000001  r4 : 00000000
> [    2.770000] r3 : 80000000  r2 : 00000007  r1 : 80000000  r0 : c4876184
> [    2.770000] Flags: nzcv  IRQs off  FIQs on  Mode SVC_32  ISA ARM Segment kernel
> [    2.770000] Control: 0005317f  Table: a0004000  DAC: 00000017
> [    2.770000] Process swapper (pid: 1, stack limit = 0xc3814270)

But that, of course, changes everthing. If you happen to see such
Ooopses, your patch should go in, and I will check the boards again and
see if they still fail to probe the ULPI. Eventually, we might need some
kind of quirks field in the platform data :(

Thanks,
Daniel

> Signed-off-by: Wolfram Sang <w.sang at pengutronix.de>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>

Acked-by: Daniel Mack <daniel at caiaq.de>

> Cc: Greg KH <gregkh at suse.de>
> Cc: stable at kernel.org
> ---
>  drivers/usb/host/ehci-mxc.c |   13 ++++++++++---
>  1 files changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
> index 544ccfd..bd40277 100644
> --- a/drivers/usb/host/ehci-mxc.c
> +++ b/drivers/usb/host/ehci-mxc.c
> @@ -207,10 +207,17 @@ static int ehci_mxc_drv_probe(struct platform_device *pdev)
>  	/* Initialize the transceiver */
>  	if (pdata->otg) {
>  		pdata->otg->io_priv = hcd->regs + ULPI_VIEWPORT_OFFSET;
> -		if (otg_init(pdata->otg) != 0)
> -			dev_err(dev, "unable to init transceiver\n");
> -		else if (otg_set_vbus(pdata->otg, 1) != 0)
> +		ret = otg_init(pdata->otg);
> +		if (ret) {
> +			dev_err(dev, "unable to init transceiver, probably missing\n");
> +			ret = -ENODEV;
> +			goto err_add;
> +		}
> +		ret = otg_set_vbus(pdata->otg, 1);
> +		if (ret) {
>  			dev_err(dev, "unable to enable vbus on transceiver\n");
> +			goto err_add;
> +		}
>  	}
>  
>  	priv->hcd = hcd;
> -- 
> 1.7.1
> 


From jassisinghbrar at gmail.com  Tue Jun 15 06:45:45 2010
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Tue, 15 Jun 2010 19:45:45 +0900
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 
	PrimeCells
In-Reply-To: <002001cb0c75$0a54fd00$1efef700$%kim@samsung.com>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>
	<002001cb0c75$0a54fd00$1efef700$%kim@samsung.com>
Message-ID: <AANLkTil7gb7SjrYPrHPfSomwxLlHpowXOZd_Qr125jvr@mail.gmail.com>

On Tue, Jun 15, 2010 at 7:25 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Linus Walleij wrote:
>>
>> This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells
>> based on the implementation earlier submitted by Peter Pearse.
>> This is working like a charm for memcpy on the PB11MPCore, but
>> slave DMA to devices is still not working.
>>
>> This DMA controller is used in mostly unmodified form in the ARM
>> RealView and Versatile platforms, in the ST-Ericsson Nomadik, and
>> in the ST SPEAr platform.
>>
>> It has been converted to use the header from the Samsung PL080
>> derivate instead of its own defintions, and can potentially support
>> several controllers in the same system.
>>
>> Cc: Peter Pearse <peter.pearse at arm.com>
>> Cc: Ben Dooks <ben-linux at fluff.org>
>> Cc: Kukjin Kim <kgene.kim at samsung.com>
>
> Looks good, but please give me some time to test on the board(SMDK6410).
> If any problem, let you know. Of course no problem, will ack.
Samsung doesn't use the DMA API, so this driver is unlikely to work.


From lrg at slimlogic.co.uk  Tue Jun 15 06:47:57 2010
From: lrg at slimlogic.co.uk (Liam Girdwood)
Date: Tue, 15 Jun 2010 11:47:57 +0100
Subject: [PATCH v3] ISL6271A voltage regulator support.
In-Reply-To: <20100614124831.GE14604@rakim.wolfsonmicro.main>
References: <1276442751-3562-1-git-send-email-marek.vasut@gmail.com>
	<20100614124831.GE14604@rakim.wolfsonmicro.main>
Message-ID: <1276598877.3003.36.camel@odin>

On Mon, 2010-06-14 at 13:48 +0100, Mark Brown wrote:
> On Sun, Jun 13, 2010 at 05:25:51PM +0200, Marek Vasut wrote:
> > This device is very simple, it supports one buck and two LDOs. The LDOs are
> > fixed-voltage. Only the buck is programable over the I2C bus to 16 possible
> > voltages.
> > 
> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> 
> Acked-by: Mark Brown <broonie at opensource.wolfsonmicro.com>
> 

Applied, although had to manually fix some conflicts with Kconfig.

Thanks

Liam
-- 
Freelance Developer, SlimLogic Ltd
ASoC and Voltage Regulator Maintainer.
http://www.slimlogic.co.uk



From w.sang at pengutronix.de  Tue Jun 15 07:03:33 2010
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Tue, 15 Jun 2010 13:03:33 +0200
Subject: [PATCH 2/2] ehci-mxc: bail out on transceiver problems
In-Reply-To: <20100615104342.GE17833@buzzloop.caiaq.de>
References: <1276598063-3956-1-git-send-email-w.sang@pengutronix.de>
	<1276598063-3956-2-git-send-email-w.sang@pengutronix.de>
	<20100615104342.GE17833@buzzloop.caiaq.de>
Message-ID: <20100615110333.GC2478@pengutronix.de>

On Tue, Jun 15, 2010 at 12:43:42PM +0200, Daniel Mack wrote:
> On Tue, Jun 15, 2010 at 12:34:23PM +0200, Wolfram Sang wrote:
> > The old code registered the hcd even if there were no transceivers
> > detected, leading to oopses like this if we try to probe a non-existant
> > ULPI:
> 
> Hmm. I'm aware that there was a missing bail in this function, but
> actually, I had hardware which didn't properly detect the ULPI chip but
> still worked fine. There has been quite some discussion here about that,
> and eventually I decided to not make this a hard error as it didn't
> really harm.

My use case is that we have two very similar boards, one uses just the second
host controller, the other one uses also OTG. Of course, we'd like to have just
one kernel, so we wanted to check if probing for OTG fails gracefully enough,
if the ULPI is not present. It did not, so this is what my patch intends to
fix. I think, checking why your boards fail to do the init, is the cleaner way
to go in the long run.

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From mcuos.com at gmail.com  Tue Jun 15 07:07:00 2010
From: mcuos.com at gmail.com (Wan ZongShun)
Date: Tue, 15 Jun 2010 19:07:00 +0800
Subject: [PATCH] NUC900: patch for implement clk_get_rate
Message-ID: <4C175ED4.8080303@gmail.com>

According to Baruch's advice, I re-orgnize previous patch named
'Add platform support for nuc900 i2c driver'.

This patch is for implementing clk_get_rate, there are four clk
rates were needed to get, cpufreq,ahb,apb and external crystal.
clk_get_rate return value is for external crystal.

---
 arch/arm/mach-w90x900/clock.c |    9 +++++++
 arch/arm/mach-w90x900/clock.h |    5 ++++
 arch/arm/mach-w90x900/cpu.c   |   50 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 64 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-w90x900/clock.c b/arch/arm/mach-w90x900/clock.c
index 2c371ff..6325642 100644
--- a/arch/arm/mach-w90x900/clock.c
+++ b/arch/arm/mach-w90x900/clock.c
@@ -57,6 +57,15 @@ EXPORT_SYMBOL(clk_disable);

 unsigned long clk_get_rate(struct clk *clk)
 {
+	unsigned long flags, ret;
+
+	if (clk == NULL || IS_ERR(clk))
+		return -EPERM;
+	spin_lock_irqsave(&clocks_lock, flags);
+	ret = nuc900_get_cpuclock(&clk->cpufreq, &clk->ahbfreq, &clk->apbfreq);
+	spin_unlock_irqrestore(&clocks_lock, flags);
+	if (ret)
+		return ret;
 	return 15000000;
 }
 EXPORT_SYMBOL(clk_get_rate);
diff --git a/arch/arm/mach-w90x900/clock.h b/arch/arm/mach-w90x900/clock.h
index c56ddab..af8e04c 100644
--- a/arch/arm/mach-w90x900/clock.h
+++ b/arch/arm/mach-w90x900/clock.h
@@ -14,10 +14,15 @@

 void nuc900_clk_enable(struct clk *clk, int enable);
 void nuc900_subclk_enable(struct clk *clk, int enable);
+int nuc900_get_cpuclock(unsigned int *cpuclk_khz,
+			unsigned int *ahbclk_khz, unsigned int *apbclk_khz);

 struct clk {
 	unsigned long		cken;
 	unsigned int		enabled;
+	unsigned int		cpufreq;
+	unsigned int		ahbfreq;
+	unsigned int		apbfreq;
 	void			(*enable)(struct clk *, int enable);
 };

diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
index 642207e..c4cce24 100644
--- a/arch/arm/mach-w90x900/cpu.c
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -195,6 +195,56 @@ static int __init nuc900_set_cpufreq(char *str)

 __setup("cpufreq=", nuc900_set_cpufreq);

+int nuc900_get_cpuclock(unsigned int *cpuclk_khz,
+			unsigned int *ahbclk_khz, unsigned int *apbclk_khz) {
+
+	int ahbspeed = 0, apbspeed = 0, cpuspeed = 0;
+
+	if (cpuclk_khz) {
+		cpuspeed = __raw_readl(REG_PLLCON0);
+		if (cpuspeed == PLL_200MHZ)
+			cpuspeed = 200 * 1000;
+		else if (cpuspeed == PLL_166MHZ)
+			cpuspeed = 166 * 1000;
+		else if (cpuspeed == PLL_120MHZ)
+			cpuspeed = 120 * 1000;
+		else if (cpuspeed == PLL_100MHZ)
+			cpuspeed = 100 * 1000;
+		else if (cpuspeed == PLL_66MHZ)
+			cpuspeed = 66 * 1000;
+		else {
+			printk(KERN_ERR "Can not read true cpuspeed!\n");
+			return -EPERM;
+		}
+		*cpuclk_khz = cpuspeed;
+	}
+
+	if (ahbclk_khz) {
+		ahbspeed = (__raw_readl(REG_CLKDIV) >> 24) & 0x03;
+		if (ahbspeed == AHB_CPUCLK_1_1)
+			ahbspeed = cpuspeed;
+		else if (ahbspeed == AHB_CPUCLK_1_2)
+			ahbspeed = cpuspeed / 2;
+		else {
+			printk(KERN_ERR "Can not read true ahbspeed!\n");
+			return -EPERM;
+		}
+		*ahbclk_khz = ahbspeed;
+	}
+
+	if (apbclk_khz) {
+		apbspeed = (__raw_readl(REG_CLKDIV) >> 26) & 0x03;
+		if (apbspeed == APB_AHB_1_2)
+			apbspeed = ahbspeed / 2;
+		else {
+			printk(KERN_ERR "Can not read true apbspeed!\n");
+			return -EPERM;
+		}
+		*apbclk_khz = apbspeed;
+	}
+	return 0;
+}
+
 /*Init NUC900 evb io*/

 void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size)
-- 
1.6.3.3


From daniel at caiaq.de  Tue Jun 15 07:12:55 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Tue, 15 Jun 2010 13:12:55 +0200
Subject: [PATCH 2/2] ehci-mxc: bail out on transceiver problems
In-Reply-To: <20100615110333.GC2478@pengutronix.de>
References: <1276598063-3956-1-git-send-email-w.sang@pengutronix.de>
	<1276598063-3956-2-git-send-email-w.sang@pengutronix.de>
	<20100615104342.GE17833@buzzloop.caiaq.de>
	<20100615110333.GC2478@pengutronix.de>
Message-ID: <20100615111255.GG17833@buzzloop.caiaq.de>

On Tue, Jun 15, 2010 at 01:03:33PM +0200, Wolfram Sang wrote:
> On Tue, Jun 15, 2010 at 12:43:42PM +0200, Daniel Mack wrote:
> > On Tue, Jun 15, 2010 at 12:34:23PM +0200, Wolfram Sang wrote:
> > > The old code registered the hcd even if there were no transceivers
> > > detected, leading to oopses like this if we try to probe a non-existant
> > > ULPI:
> > 
> > Hmm. I'm aware that there was a missing bail in this function, but
> > actually, I had hardware which didn't properly detect the ULPI chip but
> > still worked fine. There has been quite some discussion here about that,
> > and eventually I decided to not make this a hard error as it didn't
> > really harm.
> 
> My use case is that we have two very similar boards, one uses just the second
> host controller, the other one uses also OTG. Of course, we'd like to have just
> one kernel, so we wanted to check if probing for OTG fails gracefully enough,
> if the ULPI is not present. It did not, so this is what my patch intends to
> fix. I think, checking why your boards fail to do the init, is the cleaner way
> to go in the long run.

There's a design flaw in Freescale's MX31 reference designs which lets
the nCS pin float. And many board designers blindly copied that flaw
over to their own designs.

See

  http://marc.info/?l=linux-usb&m=125985151110906&w=4

So we might need quirks handling here.


Daniel



From mcuelenaere at gmail.com  Tue Jun 15 07:17:28 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Tue, 15 Jun 2010 13:17:28 +0200
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 PrimeCells
In-Reply-To: <AANLkTil7gb7SjrYPrHPfSomwxLlHpowXOZd_Qr125jvr@mail.gmail.com>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>	<002001cb0c75$0a54fd00$1efef700$%kim@samsung.com>
	<AANLkTil7gb7SjrYPrHPfSomwxLlHpowXOZd_Qr125jvr@mail.gmail.com>
Message-ID: <4C176148.4020507@gmail.com>

Op 15-06-10 12:45, Jassi Brar schreef:
> On Tue, Jun 15, 2010 at 7:25 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>> Linus Walleij wrote:
>>>
>>> This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells
>>> based on the implementation earlier submitted by Peter Pearse.
>>> This is working like a charm for memcpy on the PB11MPCore, but
>>> slave DMA to devices is still not working.
>>>
>>> This DMA controller is used in mostly unmodified form in the ARM
>>> RealView and Versatile platforms, in the ST-Ericsson Nomadik, and
>>> in the ST SPEAr platform.
>>>
>>> It has been converted to use the header from the Samsung PL080
>>> derivate instead of its own defintions, and can potentially support
>>> several controllers in the same system.
>>>
>>> Cc: Peter Pearse <peter.pearse at arm.com>
>>> Cc: Ben Dooks <ben-linux at fluff.org>
>>> Cc: Kukjin Kim <kgene.kim at samsung.com>
>>
>> Looks good, but please give me some time to test on the board(SMDK6410).
>> If any problem, let you know. Of course no problem, will ack.
> Samsung doesn't use the DMA API, so this driver is unlikely to work.

It doesn't indeed, but it could be adapted to be a wrapper around the DMA engine API.
Or even better, the drivers could be adapted to use that API.


From mcuelenaere at gmail.com  Tue Jun 15 07:17:28 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Tue, 15 Jun 2010 13:17:28 +0200
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 PrimeCells
In-Reply-To: <AANLkTil7gb7SjrYPrHPfSomwxLlHpowXOZd_Qr125jvr@mail.gmail.com>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>	<002001cb0c75$0a54fd00$1efef700$%kim@samsung.com>
	<AANLkTil7gb7SjrYPrHPfSomwxLlHpowXOZd_Qr125jvr@mail.gmail.com>
Message-ID: <4C176148.4020507@gmail.com>

Op 15-06-10 12:45, Jassi Brar schreef:
> On Tue, Jun 15, 2010 at 7:25 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>> Linus Walleij wrote:
>>>
>>> This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells
>>> based on the implementation earlier submitted by Peter Pearse.
>>> This is working like a charm for memcpy on the PB11MPCore, but
>>> slave DMA to devices is still not working.
>>>
>>> This DMA controller is used in mostly unmodified form in the ARM
>>> RealView and Versatile platforms, in the ST-Ericsson Nomadik, and
>>> in the ST SPEAr platform.
>>>
>>> It has been converted to use the header from the Samsung PL080
>>> derivate instead of its own defintions, and can potentially support
>>> several controllers in the same system.
>>>
>>> Cc: Peter Pearse <peter.pearse at arm.com>
>>> Cc: Ben Dooks <ben-linux at fluff.org>
>>> Cc: Kukjin Kim <kgene.kim at samsung.com>
>>
>> Looks good, but please give me some time to test on the board(SMDK6410).
>> If any problem, let you know. Of course no problem, will ack.
> Samsung doesn't use the DMA API, so this driver is unlikely to work.

It doesn't indeed, but it could be adapted to be a wrapper around the DMA engine API.
Or even better, the drivers could be adapted to use that API.



From kgene.kim at samsung.com  Tue Jun 15 07:27:48 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 15 Jun 2010 20:27:48 +0900
Subject: [PATCH 3/3] sdhci-s3c: Add SDHCI_QUIRK_NO_WP_BIT for Samsung SoC
In-Reply-To: <1276601268-7226-1-git-send-email-kgene.kim@samsung.com>
References: <1276601268-7226-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1276601268-7226-4-git-send-email-kgene.kim@samsung.com>

From: Lee Hyuk <hyuk1.lee at samsung.com>

S5PV210 HSMMC host controller doesn't have the WP pin which should be
connnected with SDMMC card WP pin. So if there are the cfg_wp and get_ro
in pdata, configure the WP pin and replace get_ro function in sdhci with
get_ro function in pdata.

Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 drivers/mmc/host/sdhci-s3c.c |   12 ++++++++++++
 drivers/mmc/host/sdhci.c     |    3 +++
 drivers/mmc/host/sdhci.h     |    3 +++
 3 files changed, 18 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index af21792..857cbed 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -311,6 +311,9 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	if (pdata->cfg_gpio)
 		pdata->cfg_gpio(pdev, pdata->max_width);
 
+	if (pdata->get_ro)
+		sdhci_s3c_ops.get_ro = pdata->get_ro;
+
 	host->hw_name = "samsung-hsmmc";
 	host->ops = &sdhci_s3c_ops;
 	host->quirks = 0;
@@ -335,6 +338,15 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
 			 SDHCI_QUIRK_32BIT_DMA_SIZE);
 
+	/* Controller's WP pin donsn't connected with SD card. So we allocate
+	 * a GPIO for getting WP data form SD card  and use that data as
+	 * the return value of the get_ro function */
+	host->quirks |= SDHCI_QUIRK_NO_WP_BIT;
+
+	/* to configure gpio pin as a card write protection signal */
+	if (pdata->cfg_wp)
+		pdata->cfg_wp(pdev->id);
+
 	ret = sdhci_add_host(host);
 	if (ret) {
 		dev_err(dev, "sdhci_add_host() failed\n");
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index c6d1bd8..2f8dfbc 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1192,6 +1192,9 @@ static int sdhci_get_ro(struct mmc_host *mmc)
 
 	host = mmc_priv(mmc);
 
+	if ((host->quirks & SDHCI_QUIRK_NO_WP_BIT) && host->ops->get_ro)
+		return host->ops->get_ro(mmc);
+
 	spin_lock_irqsave(&host->lock, flags);
 
 	if (host->flags & SDHCI_DEVICE_DEAD)
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c846813..f479e22 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -240,6 +240,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN		(1<<25)
 /* Controller cannot support End Attribute in NOP ADMA descriptor */
 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC		(1<<26)
+/* Controller has no write-protect pin connected with SD card */
+#define SDHCI_QUIRK_NO_WP_BIT                          (1<<27)
 
 	int			irq;		/* Device IRQ */
 	void __iomem *		ioaddr;		/* Mapped address */
@@ -312,6 +314,7 @@ struct sdhci_ops {
 	unsigned int	(*get_max_clock)(struct sdhci_host *host);
 	unsigned int	(*get_min_clock)(struct sdhci_host *host);
 	unsigned int	(*get_timeout_clock)(struct sdhci_host *host);
+	int		(*get_ro)(struct mmc_host *mmc);
 };
 
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
-- 
1.6.2.5



From kgene.kim at samsung.com  Tue Jun 15 07:27:45 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 15 Jun 2010 20:27:45 +0900
Subject: ARM: S5PV210: Add support SDMMC Write Protection on SMDKV210
Message-ID: <1276601268-7226-1-git-send-email-kgene.kim@samsung.com>

This patch adds support SDMMC write protection pin on SMDKV210.

Note: Depends on following patch set

[PATCH 1/2] ARM: SAMSUNG: Add device definition for HSMMC3
[PATCH 2/2 RE-SEND] ARM: S5PV210: Add support HSMMC on Samsung SMDKV210

And this patch set includes the following patches:

[PATCH 1/3] ARM: SAMSUNG: Add the member of platdata to implement SDMMC Write Protection
[PATCH 2/3] ARM: S5PV210: Add support SDMMC WP through EXT_INT on SMDKV210
[PATCH 3/3] sdhci-s3c: Add SDHCI_QUIRK_NO_WP_BIT for Samsung SoC


From kgene.kim at samsung.com  Tue Jun 15 07:27:46 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 15 Jun 2010 20:27:46 +0900
Subject: [PATCH 1/3] ARM: SAMSUNG: Add the member of platdata to implement
	SDMMC Write Protection
In-Reply-To: <1276601268-7226-1-git-send-email-kgene.kim@samsung.com>
References: <1276601268-7226-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1276601268-7226-2-git-send-email-kgene.kim@samsung.com>

From: Lee Hyuk <hyuk1.lee at samsung.com>

This patch adds the members of platdata which are cfg_wp and get_ro.
The cfg_wp is the function for setting the specific GPIO for WP pin
and get_ro is the function for getting data from the assigned GPIO.

Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/plat-samsung/dev-hsmmc.c          |    4 ++++
 arch/arm/plat-samsung/dev-hsmmc1.c         |    4 ++++
 arch/arm/plat-samsung/dev-hsmmc2.c         |    4 ++++
 arch/arm/plat-samsung/dev-hsmmc3.c         |    4 ++++
 arch/arm/plat-samsung/include/plat/sdhci.h |    6 ++++++
 5 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index 4c05b39..f2bae6f 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -65,4 +65,8 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
 		set->cfg_gpio = pd->cfg_gpio;
 	if (pd->cfg_card)
 		set->cfg_card = pd->cfg_card;
+	if (pd->cfg_wp)
+		set->cfg_wp = pd->cfg_wp;
+	if (pd->get_ro)
+		set->get_ro = pd->get_ro;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index e49bc4c..b326e0d 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -65,4 +65,8 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
 		set->cfg_gpio = pd->cfg_gpio;
 	if (pd->cfg_card)
 		set->cfg_card = pd->cfg_card;
+	if (pd->cfg_wp)
+		set->cfg_wp = pd->cfg_wp;
+	if (pd->get_ro)
+		set->get_ro = pd->get_ro;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index 824580b..3474ef2 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -66,4 +66,8 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
 		set->cfg_gpio = pd->cfg_gpio;
 	if (pd->cfg_card)
 		set->cfg_card = pd->cfg_card;
+	if (pd->cfg_wp)
+		set->cfg_wp = pd->cfg_wp;
+	if (pd->get_ro)
+		set->get_ro = pd->get_ro;
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c
index 05d5ea4..1da8ea7 100644
--- a/arch/arm/plat-samsung/dev-hsmmc3.c
+++ b/arch/arm/plat-samsung/dev-hsmmc3.c
@@ -69,4 +69,8 @@ void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
 		set->cfg_gpio = pd->cfg_gpio;
 	if (pd->cfg_card)
 		set->cfg_card = pd->cfg_card;
+	if (pd->cfg_wp)
+		set->cfg_wp = pd->cfg_wp;
+	if (pd->get_ro)
+		set->get_ro = pd->get_ro;
 }
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 1314ffa..da198d8 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -29,6 +29,8 @@ struct mmc_ios;
  *            is necessary the controllers and/or GPIO blocks require the
  *	      changing of driver-strength and other controls dependant on
  *	      the card and speed of operation.
+ * @cfg_wp: Configure the GPIO in order to allocate WP pin.
+ * @get_ro: Call back function for getting data from the allocated GPIO.
  *
  * Initialisation data specific to either the machine or the platform
  * for the device driver to use or call-back when configuring gpio or
@@ -45,6 +47,8 @@ struct s3c_sdhci_platdata {
 			    void __iomem *regbase,
 			    struct mmc_ios *ios,
 			    struct mmc_card *card);
+	void	(*cfg_wp)(int dev_id);
+	int	(*get_ro)(struct mmc_host *mmc);
 };
 
 /**
@@ -234,6 +238,8 @@ extern void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
 					   struct mmc_ios *ios,
 					   struct mmc_card *card);
 
+extern void s3c_sdhci_set_platdata(void);
+
 #ifdef CONFIG_S3C_DEV_HSMMC
 static inline void s5pv210_default_sdhci0(void)
 {
-- 
1.6.2.5



From kgene.kim at samsung.com  Tue Jun 15 07:27:47 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 15 Jun 2010 20:27:47 +0900
Subject: [PATCH 2/3] ARM: S5PV210: Add support SDMMC WP through EXT_INT on
	SMDKV210
In-Reply-To: <1276601268-7226-1-git-send-email-kgene.kim@samsung.com>
References: <1276601268-7226-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1276601268-7226-3-git-send-email-kgene.kim@samsung.com>

From: Lee Hyuk <hyuk1.lee at samsung.com>

S5PV210 HSMMC host controller doesn't have the Write Protection pin which
should be connnected with SDMMC card WP pin. So allocated a GPIO in order to
get the data from SDMMC card WP pin with EXT_INT and implement get_ro and
cfg_wp function.

Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pv210/mach-smdkv210.c |    2 +
 arch/arm/mach-s5pv210/setup-sdhci.c   |   72 +++++++++++++++++++++++++++++++++
 2 files changed, 74 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index b08f376..18cdb8c 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -27,6 +27,7 @@
 #include <plat/cpu.h>
 #include <plat/adc.h>
 #include <plat/ts.h>
+#include <plat/sdhci.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
@@ -101,6 +102,7 @@ static void __init smdkv210_map_io(void)
 static void __init smdkv210_machine_init(void)
 {
 	s3c24xx_ts_set_platdata(&s3c_ts_platform);
+	s3c_sdhci_set_platdata();
 	platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
 }
 
diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
index 51815ec..b553b36 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci.c
@@ -15,13 +15,17 @@
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 
 #include <linux/mmc/card.h>
 #include <linux/mmc/host.h>
 
+#include <plat/gpio-cfg.h>
 #include <plat/regs-sdhci.h>
 #include <plat/sdhci.h>
 
+#include <mach/map.h>
+
 /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
 
 char *s5pv210_hsmmc_clksrcs[4] = {
@@ -61,3 +65,71 @@ void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
 	writel(ctrl2, r + S3C_SDHCI_CONTROL2);
 	writel(ctrl3, r + S3C_SDHCI_CONTROL3);
 }
+
+static int s5pv210_sdhci_get_ro(struct mmc_host *mmc)
+{
+	int gpio_dat;
+
+	if ((mmc->index == 0 && s3c_hsmmc0_def_platdata.cfg_wp != NULL) ||
+		(mmc->index == 1 && s3c_hsmmc1_def_platdata.cfg_wp != NULL)) {
+		gpio_dat = __raw_readl((S5P_VA_GPIO + 0xC00) + 0x04);
+		return !!(gpio_dat & 0x80);
+	} else if (mmc->index == 2 && s3c_hsmmc2_def_platdata.cfg_wp != NULL) {
+		gpio_dat = __raw_readl((S5P_VA_GPIO + 0xC00) + 0x64);
+		return !!(gpio_dat & 0x2);
+	} else if (mmc->index == 3 && s3c_hsmmc3_def_platdata.cfg_wp != NULL) {
+		gpio_dat = __raw_readl((S5P_VA_GPIO + 0xC00) + 0x24);
+		return !!(gpio_dat & 0x1);
+	} else
+		return 0;
+}
+
+static void s5pv210_setup_sdhci_gpio_wp(int dev_id)
+{
+	switch (dev_id) {
+	case 0:
+	case 1:
+		s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_INPUT);
+		s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP);
+		break;
+	case 2:
+		s3c_gpio_cfgpin(S5PV210_GPH3(1), S3C_GPIO_INPUT);
+		s3c_gpio_setpull(S5PV210_GPH3(1), S3C_GPIO_PULL_UP);
+		break;
+	case 3:
+		s3c_gpio_cfgpin(S5PV210_GPH1(0), S3C_GPIO_INPUT);
+		s3c_gpio_setpull(S5PV210_GPH1(0), S3C_GPIO_PULL_UP);
+		break;
+	default:
+		break;
+	}
+}
+
+static struct s3c_sdhci_platdata hsmmc0_platdata = {
+	.cfg_wp         = s5pv210_setup_sdhci_gpio_wp,
+	.get_ro         = s5pv210_sdhci_get_ro,
+};
+
+static struct s3c_sdhci_platdata hsmmc1_platdata = {
+	.cfg_wp         = s5pv210_setup_sdhci_gpio_wp,
+	.get_ro         = s5pv210_sdhci_get_ro,
+};
+
+static struct s3c_sdhci_platdata hsmmc2_platdata = {
+	.cfg_wp         = s5pv210_setup_sdhci_gpio_wp,
+	.get_ro         = s5pv210_sdhci_get_ro,
+};
+
+static struct s3c_sdhci_platdata hsmmc3_platdata = {
+	.cfg_wp         = s5pv210_setup_sdhci_gpio_wp,
+	.get_ro         = s5pv210_sdhci_get_ro,
+};
+
+void s3c_sdhci_set_platdata(void)
+{
+	s3c_sdhci0_set_platdata(&hsmmc0_platdata);
+	s3c_sdhci1_set_platdata(&hsmmc1_platdata);
+	s3c_sdhci2_set_platdata(&hsmmc2_platdata);
+	s3c_sdhci3_set_platdata(&hsmmc3_platdata);
+}
+EXPORT_SYMBOL(s3c_sdhci_set_platdata);
-- 
1.6.2.5



From jassisinghbrar at gmail.com  Tue Jun 15 07:39:43 2010
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Tue, 15 Jun 2010 20:39:43 +0900
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 
	PrimeCells
In-Reply-To: <4C176148.4020507@gmail.com>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>
	<002001cb0c75$0a54fd00$1efef700$%kim@samsung.com>
	<AANLkTil7gb7SjrYPrHPfSomwxLlHpowXOZd_Qr125jvr@mail.gmail.com>
	<4C176148.4020507@gmail.com>
Message-ID: <AANLkTil7b5Pg5q18eGvGY_cFH75rdpSuZhigH4vcjrnu@mail.gmail.com>

On Tue, Jun 15, 2010 at 8:17 PM, Maurus Cuelenaere
<mcuelenaere at gmail.com> wrote:
> Op 15-06-10 12:45, Jassi Brar schreef:
>> On Tue, Jun 15, 2010 at 7:25 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>>> Linus Walleij wrote:
>>>>
>>>> This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells
>>>> based on the implementation earlier submitted by Peter Pearse.
>>>> This is working like a charm for memcpy on the PB11MPCore, but
>>>> slave DMA to devices is still not working.
>>>>
>>>> This DMA controller is used in mostly unmodified form in the ARM
>>>> RealView and Versatile platforms, in the ST-Ericsson Nomadik, and
>>>> in the ST SPEAr platform.
>>>>
>>>> It has been converted to use the header from the Samsung PL080
>>>> derivate instead of its own defintions, and can potentially support
>>>> several controllers in the same system.
>>>>
>>>> Cc: Peter Pearse <peter.pearse at arm.com>
>>>> Cc: Ben Dooks <ben-linux at fluff.org>
>>>> Cc: Kukjin Kim <kgene.kim at samsung.com>
>>>
>>> Looks good, but please give me some time to test on the board(SMDK6410).
>>> If any problem, let you know. Of course no problem, will ack.
>> Samsung doesn't use the DMA API, so this driver is unlikely to work.
>
> It doesn't indeed, but it could be adapted to be a wrapper around the DMA engine API.
> Or even better, the drivers could be adapted to use that API.
I don't particularly like the idea of making Samsung's drivers use the DMA API.
IMHO the S3C dma api is better atm.


From philippe.retornaz at epfl.ch  Tue Jun 15 07:47:50 2010
From: philippe.retornaz at epfl.ch (Philippe =?iso-8859-1?q?R=E9tornaz?=)
Date: Tue, 15 Jun 2010 13:47:50 +0200
Subject: [PATCH 2/2] ehci-mxc: bail out on transceiver problems
In-Reply-To: <20100615104342.GE17833@buzzloop.caiaq.de>
References: <1276598063-3956-1-git-send-email-w.sang@pengutronix.de>
	<1276598063-3956-2-git-send-email-w.sang@pengutronix.de>
	<20100615104342.GE17833@buzzloop.caiaq.de>
Message-ID: <201006151347.51085.philippe.retornaz@epfl.ch>

Le mardi, 15 juin 2010 12.43:42, Daniel Mack a ?crit :
> On Tue, Jun 15, 2010 at 12:34:23PM +0200, Wolfram Sang wrote:
> > The old code registered the hcd even if there were no transceivers
> > detected, leading to oopses like this if we try to probe a non-existant
> > ULPI:
> 
> Hmm. I'm aware that there was a missing bail in this function, but
> actually, I had hardware which didn't properly detect the ULPI chip but
> still worked fine. There has been quite some discussion here about that,
> and eventually I decided to not make this a hard error as it didn't
> really harm.
> 
> > [    2.730000] mxc-ehci mxc-ehci.0: unable to init transceiver
> > [    2.740000] timeout polling for ULPI device
> > [    2.740000] timeout polling for ULPI device
> > [    2.750000] mxc-ehci mxc-ehci.0: unable to enable vbus on transceiver
> > [    2.750000] mxc-ehci mxc-ehci.0: Freescale On-Chip EHCI Host
> > Controller [    2.760000] mxc-ehci mxc-ehci.0: new USB bus registered,
> > assigned bus number 2 [    2.770000] Unhandled fault: external abort on
> > non-linefetch (0x808) at 0xc4876184 [    2.770000] Internal error: : 808
> > [#1] PREEMPT
> > [    2.770000] last sysfs file:
> > [    2.770000] Modules linked in:
> > [    2.770000] CPU: 0    Not tainted  (2.6.33.5 #5)
> > [    2.770000] PC is at ehci_hub_control+0x4d4/0x8f8
> > [    2.770000] LR is at ehci_mxc_setup+0xbc/0xdc
> > [    2.770000] pc : [<c0196dfc>]    lr : [<c019bc8c>]    psr: 00000093
> > [    2.770000] sp : c3815e40  ip : 00000001  fp : 60000013
> > [    2.770000] r10: c4876184  r9 : 00000000  r8 : c3814000
> > [    2.770000] r7 : c391d2cc  r6 : 00000001  r5 : 00000001  r4 : 00000000
> > [    2.770000] r3 : 80000000  r2 : 00000007  r1 : 80000000  r0 : c4876184
> > [    2.770000] Flags: nzcv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
> > Segment kernel [    2.770000] Control: 0005317f  Table: a0004000  DAC:
> > 00000017 [    2.770000] Process swapper (pid: 1, stack limit =
> > 0xc3814270)
> 
> But that, of course, changes everthing. If you happen to see such
> Ooopses, your patch should go in, and I will check the boards again and
> see if they still fail to probe the ULPI. Eventually, we might need some
> kind of quirks field in the platform data :(
> 

Have you tried my imx31 EHCI controller init patch applied ? 
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/014729.html

Btw, it has still not be applied, anybody knows why ? 

Regards,

Philippe


From kmpark at infradead.org  Tue Jun 15 07:52:45 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Tue, 15 Jun 2010 20:52:45 +0900
Subject: [PATCH 2/3] ARM: S5PV210: Add support SDMMC WP through EXT_INT on
	SMDKV210
In-Reply-To: <1276601268-7226-3-git-send-email-kgene.kim@samsung.com>
References: <1276601268-7226-1-git-send-email-kgene.kim@samsung.com>
	<1276601268-7226-3-git-send-email-kgene.kim@samsung.com>
Message-ID: <AANLkTimQwmFGwRgXASba1ECwYDJaay_D1q4_L6tvIo9y@mail.gmail.com>

On Tue, Jun 15, 2010 at 8:27 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> From: Lee Hyuk <hyuk1.lee at samsung.com>
>
> S5PV210 HSMMC host controller doesn't have the Write Protection pin which
> should be connnected with SDMMC card WP pin. So allocated a GPIO in order to
> get the data from SDMMC card WP pin with EXT_INT and implement get_ro and
> cfg_wp function.
>
> Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
> ?arch/arm/mach-s5pv210/mach-smdkv210.c | ? ?2 +
> ?arch/arm/mach-s5pv210/setup-sdhci.c ? | ? 72 +++++++++++++++++++++++++++++++++
> ?2 files changed, 74 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
> index b08f376..18cdb8c 100644
> --- a/arch/arm/mach-s5pv210/mach-smdkv210.c
> +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
> @@ -27,6 +27,7 @@
> ?#include <plat/cpu.h>
> ?#include <plat/adc.h>
> ?#include <plat/ts.h>
> +#include <plat/sdhci.h>
>
> ?/* Following are default values for UCON, ULCON and UFCON UART registers */
> ?#define S5PV210_UCON_DEFAULT ? (S3C2410_UCON_TXILEVEL | ? ? ? ?\
> @@ -101,6 +102,7 @@ static void __init smdkv210_map_io(void)
> ?static void __init smdkv210_machine_init(void)
> ?{
> ? ? ? ?s3c24xx_ts_set_platdata(&s3c_ts_platform);
> + ? ? ? s3c_sdhci_set_platdata();
> ? ? ? ?platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
> ?}
>
> diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
> index 51815ec..b553b36 100644
> --- a/arch/arm/mach-s5pv210/setup-sdhci.c
> +++ b/arch/arm/mach-s5pv210/setup-sdhci.c
> @@ -15,13 +15,17 @@
> ?#include <linux/interrupt.h>
> ?#include <linux/platform_device.h>
> ?#include <linux/io.h>
> +#include <linux/gpio.h>
>
> ?#include <linux/mmc/card.h>
> ?#include <linux/mmc/host.h>
>
> +#include <plat/gpio-cfg.h>
> ?#include <plat/regs-sdhci.h>
> ?#include <plat/sdhci.h>
>
> +#include <mach/map.h>
> +
> ?/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
>
> ?char *s5pv210_hsmmc_clksrcs[4] = {
> @@ -61,3 +65,71 @@ void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
> ? ? ? ?writel(ctrl2, r + S3C_SDHCI_CONTROL2);
> ? ? ? ?writel(ctrl3, r + S3C_SDHCI_CONTROL3);
> ?}
> +
> +static int s5pv210_sdhci_get_ro(struct mmc_host *mmc)
> +{
> + ? ? ? int gpio_dat;
> +
> + ? ? ? if ((mmc->index == 0 && s3c_hsmmc0_def_platdata.cfg_wp != NULL) ||
> + ? ? ? ? ? ? ? (mmc->index == 1 && s3c_hsmmc1_def_platdata.cfg_wp != NULL)) {
> + ? ? ? ? ? ? ? gpio_dat = __raw_readl((S5P_VA_GPIO + 0xC00) + 0x04);
> + ? ? ? ? ? ? ? return !!(gpio_dat & 0x80);

It's GPIO values, and it's smdk specific values. So it should go smdk
board files instead of platform common one.

> + ? ? ? } else if (mmc->index == 2 && s3c_hsmmc2_def_platdata.cfg_wp != NULL) {
> + ? ? ? ? ? ? ? gpio_dat = __raw_readl((S5P_VA_GPIO + 0xC00) + 0x64);
> + ? ? ? ? ? ? ? return !!(gpio_dat & 0x2);
> + ? ? ? } else if (mmc->index == 3 && s3c_hsmmc3_def_platdata.cfg_wp != NULL) {
> + ? ? ? ? ? ? ? gpio_dat = __raw_readl((S5P_VA_GPIO + 0xC00) + 0x24);
> + ? ? ? ? ? ? ? return !!(gpio_dat & 0x1);
> + ? ? ? } else
> + ? ? ? ? ? ? ? return 0;
> +}
> +
> +static void s5pv210_setup_sdhci_gpio_wp(int dev_id)
> +{
> + ? ? ? switch (dev_id) {
> + ? ? ? case 0:
> + ? ? ? case 1:
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_INPUT);
> + ? ? ? ? ? ? ? s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP);
> + ? ? ? ? ? ? ? break;
> + ? ? ? case 2:
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(S5PV210_GPH3(1), S3C_GPIO_INPUT);
> + ? ? ? ? ? ? ? s3c_gpio_setpull(S5PV210_GPH3(1), S3C_GPIO_PULL_UP);
> + ? ? ? ? ? ? ? break;
> + ? ? ? case 3:
> + ? ? ? ? ? ? ? s3c_gpio_cfgpin(S5PV210_GPH1(0), S3C_GPIO_INPUT);
> + ? ? ? ? ? ? ? s3c_gpio_setpull(S5PV210_GPH1(0), S3C_GPIO_PULL_UP);

Ditto. board specific configurations. should go smdk board file.

> + ? ? ? ? ? ? ? break;
> + ? ? ? default:
> + ? ? ? ? ? ? ? break;
> + ? ? ? }
> +}
> +
> +static struct s3c_sdhci_platdata hsmmc0_platdata = {
> + ? ? ? .cfg_wp ? ? ? ? = s5pv210_setup_sdhci_gpio_wp,
> + ? ? ? .get_ro ? ? ? ? = s5pv210_sdhci_get_ro,
> +};
> +
> +static struct s3c_sdhci_platdata hsmmc1_platdata = {
> + ? ? ? .cfg_wp ? ? ? ? = s5pv210_setup_sdhci_gpio_wp,
> + ? ? ? .get_ro ? ? ? ? = s5pv210_sdhci_get_ro,
> +};
> +
> +static struct s3c_sdhci_platdata hsmmc2_platdata = {
> + ? ? ? .cfg_wp ? ? ? ? = s5pv210_setup_sdhci_gpio_wp,
> + ? ? ? .get_ro ? ? ? ? = s5pv210_sdhci_get_ro,
> +};
> +
> +static struct s3c_sdhci_platdata hsmmc3_platdata = {
> + ? ? ? .cfg_wp ? ? ? ? = s5pv210_setup_sdhci_gpio_wp,
> + ? ? ? .get_ro ? ? ? ? = s5pv210_sdhci_get_ro,
> +};
> +
> +void s3c_sdhci_set_platdata(void)
> +{
> + ? ? ? s3c_sdhci0_set_platdata(&hsmmc0_platdata);
> + ? ? ? s3c_sdhci1_set_platdata(&hsmmc1_platdata);
> + ? ? ? s3c_sdhci2_set_platdata(&hsmmc2_platdata);
> + ? ? ? s3c_sdhci3_set_platdata(&hsmmc3_platdata);
> +}
> +EXPORT_SYMBOL(s3c_sdhci_set_platdata);

I think all added lines should go smdk totally.

Thank you,
Kyungmin Park

> --
> 1.6.2.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-mmc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>


From daniel at caiaq.de  Tue Jun 15 07:53:01 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Tue, 15 Jun 2010 13:53:01 +0200
Subject: [PATCH 2/2] ehci-mxc: bail out on transceiver problems
In-Reply-To: <201006151347.51085.philippe.retornaz@epfl.ch>
References: <1276598063-3956-1-git-send-email-w.sang@pengutronix.de>
	<1276598063-3956-2-git-send-email-w.sang@pengutronix.de>
	<20100615104342.GE17833@buzzloop.caiaq.de>
	<201006151347.51085.philippe.retornaz@epfl.ch>
Message-ID: <20100615115301.GJ17833@buzzloop.caiaq.de>

On Tue, Jun 15, 2010 at 01:47:50PM +0200, Philippe R?tornaz wrote:
> Le mardi, 15 juin 2010 12.43:42, Daniel Mack a ?crit :
> > On Tue, Jun 15, 2010 at 12:34:23PM +0200, Wolfram Sang wrote:
> > > The old code registered the hcd even if there were no transceivers
> > > detected, leading to oopses like this if we try to probe a non-existant
> > > ULPI:
> > 
> > Hmm. I'm aware that there was a missing bail in this function, but
> > actually, I had hardware which didn't properly detect the ULPI chip but
> > still worked fine. There has been quite some discussion here about that,
> > and eventually I decided to not make this a hard error as it didn't
> > really harm.
> > 
> > > [    2.730000] mxc-ehci mxc-ehci.0: unable to init transceiver
> > > [    2.740000] timeout polling for ULPI device
> > > [    2.740000] timeout polling for ULPI device
> > > [    2.750000] mxc-ehci mxc-ehci.0: unable to enable vbus on transceiver
> > > [    2.750000] mxc-ehci mxc-ehci.0: Freescale On-Chip EHCI Host
> > > Controller [    2.760000] mxc-ehci mxc-ehci.0: new USB bus registered,
> > > assigned bus number 2 [    2.770000] Unhandled fault: external abort on
> > > non-linefetch (0x808) at 0xc4876184 [    2.770000] Internal error: : 808
> > > [#1] PREEMPT
> > > [    2.770000] last sysfs file:
> > > [    2.770000] Modules linked in:
> > > [    2.770000] CPU: 0    Not tainted  (2.6.33.5 #5)
> > > [    2.770000] PC is at ehci_hub_control+0x4d4/0x8f8
> > > [    2.770000] LR is at ehci_mxc_setup+0xbc/0xdc
> > > [    2.770000] pc : [<c0196dfc>]    lr : [<c019bc8c>]    psr: 00000093
> > > [    2.770000] sp : c3815e40  ip : 00000001  fp : 60000013
> > > [    2.770000] r10: c4876184  r9 : 00000000  r8 : c3814000
> > > [    2.770000] r7 : c391d2cc  r6 : 00000001  r5 : 00000001  r4 : 00000000
> > > [    2.770000] r3 : 80000000  r2 : 00000007  r1 : 80000000  r0 : c4876184
> > > [    2.770000] Flags: nzcv  IRQs off  FIQs on  Mode SVC_32  ISA ARM
> > > Segment kernel [    2.770000] Control: 0005317f  Table: a0004000  DAC:
> > > 00000017 [    2.770000] Process swapper (pid: 1, stack limit =
> > > 0xc3814270)
> > 
> > But that, of course, changes everthing. If you happen to see such
> > Ooopses, your patch should go in, and I will check the boards again and
> > see if they still fail to probe the ULPI. Eventually, we might need some
> > kind of quirks field in the platform data :(
> > 
> 
> Have you tried my imx31 EHCI controller init patch applied ? 
> http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/014729.html

No, I haven't yet, as I'm not currently working on such a board. But I
will once I get back to that issue. Thanks for the reminder :)

Daniel


From mcuelenaere at gmail.com  Tue Jun 15 07:53:52 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Tue, 15 Jun 2010 13:53:52 +0200
Subject: [PATCH 2/3] ARM: S5PV210: Add support SDMMC WP through EXT_INT
	on SMDKV210
In-Reply-To: <1276601268-7226-3-git-send-email-kgene.kim@samsung.com>
References: <1276601268-7226-1-git-send-email-kgene.kim@samsung.com>
	<1276601268-7226-3-git-send-email-kgene.kim@samsung.com>
Message-ID: <4C1769D0.7040904@gmail.com>

Op 15-06-10 13:27, Kukjin Kim schreef:
> From: Lee Hyuk <hyuk1.lee at samsung.com>
>
> S5PV210 HSMMC host controller doesn't have the Write Protection pin which
> should be connnected with SDMMC card WP pin. So allocated a GPIO in order to
> get the data from SDMMC card WP pin with EXT_INT and implement get_ro and
> cfg_wp function.
>
> Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
>  arch/arm/mach-s5pv210/mach-smdkv210.c |    2 +
>  arch/arm/mach-s5pv210/setup-sdhci.c   |   72 +++++++++++++++++++++++++++++++++
>  2 files changed, 74 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
> index b08f376..18cdb8c 100644
> --- a/arch/arm/mach-s5pv210/mach-smdkv210.c
> +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
> @@ -27,6 +27,7 @@
>  #include <plat/cpu.h>
>  #include <plat/adc.h>
>  #include <plat/ts.h>
> +#include <plat/sdhci.h>
>  
>  /* Following are default values for UCON, ULCON and UFCON UART registers */
>  #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
> @@ -101,6 +102,7 @@ static void __init smdkv210_map_io(void)
>  static void __init smdkv210_machine_init(void)
>  {
>  	s3c24xx_ts_set_platdata(&s3c_ts_platform);
> +	s3c_sdhci_set_platdata();
>   

Wouldn't it be better to name this s5pv210_sdhci_set_platdata() ?
Also, see below.

>  	platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
>  }
>  
> diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
> index 51815ec..b553b36 100644
> --- a/arch/arm/mach-s5pv210/setup-sdhci.c
> +++ b/arch/arm/mach-s5pv210/setup-sdhci.c
> @@ -15,13 +15,17 @@
>  #include <linux/interrupt.h>
>  #include <linux/platform_device.h>
>  #include <linux/io.h>
> +#include <linux/gpio.h>
>  
>  #include <linux/mmc/card.h>
>  #include <linux/mmc/host.h>
>  
> +#include <plat/gpio-cfg.h>
>  #include <plat/regs-sdhci.h>
>  #include <plat/sdhci.h>
>  
> +#include <mach/map.h>
> +
>  /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
>  
>  char *s5pv210_hsmmc_clksrcs[4] = {
> @@ -61,3 +65,71 @@ void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
>  	writel(ctrl2, r + S3C_SDHCI_CONTROL2);
>  	writel(ctrl3, r + S3C_SDHCI_CONTROL3);
>  }
> +
> +static int s5pv210_sdhci_get_ro(struct mmc_host *mmc)
> +{
> +	int gpio_dat;
> +
> +	if ((mmc->index == 0 && s3c_hsmmc0_def_platdata.cfg_wp != NULL) ||
> +		(mmc->index == 1 && s3c_hsmmc1_def_platdata.cfg_wp != NULL)) {
> +		gpio_dat = __raw_readl((S5P_VA_GPIO + 0xC00) + 0x04);
> +		return !!(gpio_dat & 0x80);
> +	} else if (mmc->index == 2 && s3c_hsmmc2_def_platdata.cfg_wp != NULL) {
> +		gpio_dat = __raw_readl((S5P_VA_GPIO + 0xC00) + 0x64);
> +		return !!(gpio_dat & 0x2);
> +	} else if (mmc->index == 3 && s3c_hsmmc3_def_platdata.cfg_wp != NULL) {
> +		gpio_dat = __raw_readl((S5P_VA_GPIO + 0xC00) + 0x24);
> +		return !!(gpio_dat & 0x1);
> +	} else
> +		return 0;
> +}
> +
> +static void s5pv210_setup_sdhci_gpio_wp(int dev_id)
> +{
> +	switch (dev_id) {
> +	case 0:
> +	case 1:
> +		s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_INPUT);
> +		s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP);
> +		break;
> +	case 2:
> +		s3c_gpio_cfgpin(S5PV210_GPH3(1), S3C_GPIO_INPUT);
> +		s3c_gpio_setpull(S5PV210_GPH3(1), S3C_GPIO_PULL_UP);
> +		break;
> +	case 3:
> +		s3c_gpio_cfgpin(S5PV210_GPH1(0), S3C_GPIO_INPUT);
> +		s3c_gpio_setpull(S5PV210_GPH1(0), S3C_GPIO_PULL_UP);
> +		break;
> +	default:
> +		break;
> +	}
> +}
> +
> +static struct s3c_sdhci_platdata hsmmc0_platdata = {
> +	.cfg_wp         = s5pv210_setup_sdhci_gpio_wp,
> +	.get_ro         = s5pv210_sdhci_get_ro,
> +};
> +
> +static struct s3c_sdhci_platdata hsmmc1_platdata = {
> +	.cfg_wp         = s5pv210_setup_sdhci_gpio_wp,
> +	.get_ro         = s5pv210_sdhci_get_ro,
> +};
> +
> +static struct s3c_sdhci_platdata hsmmc2_platdata = {
> +	.cfg_wp         = s5pv210_setup_sdhci_gpio_wp,
> +	.get_ro         = s5pv210_sdhci_get_ro,
> +};
> +
> +static struct s3c_sdhci_platdata hsmmc3_platdata = {
> +	.cfg_wp         = s5pv210_setup_sdhci_gpio_wp,
> +	.get_ro         = s5pv210_sdhci_get_ro,
> +};
> +
> +void s3c_sdhci_set_platdata(void)
> +{
> +	s3c_sdhci0_set_platdata(&hsmmc0_platdata);
> +	s3c_sdhci1_set_platdata(&hsmmc1_platdata);
> +	s3c_sdhci2_set_platdata(&hsmmc2_platdata);
> +	s3c_sdhci3_set_platdata(&hsmmc3_platdata);
> +}
> +EXPORT_SYMBOL(s3c_sdhci_set_platdata);
>   

Why do you export this function? I don't see this being used anywhere
except in mach-s5pv210.

-- 
Maurus Cuelenaere



From ben-linux at fluff.org  Tue Jun 15 07:59:47 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Tue, 15 Jun 2010 12:59:47 +0100
Subject: [PATCH 2/3] ARM: S5PV210: Add support SDMMC WP through EXT_INT
	on SMDKV210
In-Reply-To: <1276601268-7226-3-git-send-email-kgene.kim@samsung.com>
References: <1276601268-7226-1-git-send-email-kgene.kim@samsung.com>
	<1276601268-7226-3-git-send-email-kgene.kim@samsung.com>
Message-ID: <20100615115947.GC7248@trinity.fluff.org>

On Tue, Jun 15, 2010 at 08:27:47PM +0900, Kukjin Kim wrote:
> From: Lee Hyuk <hyuk1.lee at samsung.com>
> 
> S5PV210 HSMMC host controller doesn't have the Write Protection pin which
> should be connnected with SDMMC card WP pin. So allocated a GPIO in order to
> get the data from SDMMC card WP pin with EXT_INT and implement get_ro and
> cfg_wp function.
> 
> Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
>  arch/arm/mach-s5pv210/mach-smdkv210.c |    2 +
>  arch/arm/mach-s5pv210/setup-sdhci.c   |   72 +++++++++++++++++++++++++++++++++
>  2 files changed, 74 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
> index b08f376..18cdb8c 100644
> --- a/arch/arm/mach-s5pv210/mach-smdkv210.c
> +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
> @@ -27,6 +27,7 @@
>  #include <plat/cpu.h>
>  #include <plat/adc.h>
>  #include <plat/ts.h>
> +#include <plat/sdhci.h>
>  
>  /* Following are default values for UCON, ULCON and UFCON UART registers */
>  #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
> @@ -101,6 +102,7 @@ static void __init smdkv210_map_io(void)
>  static void __init smdkv210_machine_init(void)
>  {
>  	s3c24xx_ts_set_platdata(&s3c_ts_platform);
> +	s3c_sdhci_set_platdata();

hmm, did you really want to call it this? also, no argument specified.

>  	platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
>  }
>  
> diff --git a/arch/arm/mach-s5pv210/setup-sdhci.c b/arch/arm/mach-s5pv210/setup-sdhci.c
> index 51815ec..b553b36 100644
> --- a/arch/arm/mach-s5pv210/setup-sdhci.c
> +++ b/arch/arm/mach-s5pv210/setup-sdhci.c
> @@ -15,13 +15,17 @@
>  #include <linux/interrupt.h>
>  #include <linux/platform_device.h>
>  #include <linux/io.h>
> +#include <linux/gpio.h>
>  
>  #include <linux/mmc/card.h>
>  #include <linux/mmc/host.h>
>  
> +#include <plat/gpio-cfg.h>
>  #include <plat/regs-sdhci.h>
>  #include <plat/sdhci.h>
>  
> +#include <mach/map.h>
> +
>  /* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
>  
>  char *s5pv210_hsmmc_clksrcs[4] = {
> @@ -61,3 +65,71 @@ void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
>  	writel(ctrl2, r + S3C_SDHCI_CONTROL2);
>  	writel(ctrl3, r + S3C_SDHCI_CONTROL3);
>  }
> +
> +static int s5pv210_sdhci_get_ro(struct mmc_host *mmc)
> +{
> +	int gpio_dat;
> +
> +	if ((mmc->index == 0 && s3c_hsmmc0_def_platdata.cfg_wp != NULL) ||
> +		(mmc->index == 1 && s3c_hsmmc1_def_platdata.cfg_wp != NULL)) {
> +		gpio_dat = __raw_readl((S5P_VA_GPIO + 0xC00) + 0x04);
> +		return !!(gpio_dat & 0x80);
> +	} else if (mmc->index == 2 && s3c_hsmmc2_def_platdata.cfg_wp != NULL) {
> +		gpio_dat = __raw_readl((S5P_VA_GPIO + 0xC00) + 0x64);
> +		return !!(gpio_dat & 0x2);
> +	} else if (mmc->index == 3 && s3c_hsmmc3_def_platdata.cfg_wp != NULL) {
> +		gpio_dat = __raw_readl((S5P_VA_GPIO + 0xC00) + 0x24);
> +		return !!(gpio_dat & 0x1);
> +	} else
> +		return 0;

Why not use the gpio layer? really, this sort of thing is what it is
there for.

> +}
> +
> +static void s5pv210_setup_sdhci_gpio_wp(int dev_id)
> +{
> +	switch (dev_id) {
> +	case 0:
> +	case 1:
> +		s3c_gpio_cfgpin(S5PV210_GPH0(7), S3C_GPIO_INPUT);
> +		s3c_gpio_setpull(S5PV210_GPH0(7), S3C_GPIO_PULL_UP);
> +		break;
> +	case 2:
> +		s3c_gpio_cfgpin(S5PV210_GPH3(1), S3C_GPIO_INPUT);
> +		s3c_gpio_setpull(S5PV210_GPH3(1), S3C_GPIO_PULL_UP);
> +		break;
> +	case 3:
> +		s3c_gpio_cfgpin(S5PV210_GPH1(0), S3C_GPIO_INPUT);
> +		s3c_gpio_setpull(S5PV210_GPH1(0), S3C_GPIO_PULL_UP);
> +		break;
> +	default:
> +		break;

again, if you'd use the gpio layer, at-lesat the cfgpin() wouldn't
have been necessary.

> +	}
> +}
> +
> +static struct s3c_sdhci_platdata hsmmc0_platdata = {
> +	.cfg_wp         = s5pv210_setup_sdhci_gpio_wp,
> +	.get_ro         = s5pv210_sdhci_get_ro,
> +};
> +
> +static struct s3c_sdhci_platdata hsmmc1_platdata = {
> +	.cfg_wp         = s5pv210_setup_sdhci_gpio_wp,
> +	.get_ro         = s5pv210_sdhci_get_ro,
> +};
> +
> +static struct s3c_sdhci_platdata hsmmc2_platdata = {
> +	.cfg_wp         = s5pv210_setup_sdhci_gpio_wp,
> +	.get_ro         = s5pv210_sdhci_get_ro,
> +};
> +
> +static struct s3c_sdhci_platdata hsmmc3_platdata = {
> +	.cfg_wp         = s5pv210_setup_sdhci_gpio_wp,
> +	.get_ro         = s5pv210_sdhci_get_ro,
> +};
> +
> +void s3c_sdhci_set_platdata(void)
> +{
> +	s3c_sdhci0_set_platdata(&hsmmc0_platdata);
> +	s3c_sdhci1_set_platdata(&hsmmc1_platdata);
> +	s3c_sdhci2_set_platdata(&hsmmc2_platdata);
> +	s3c_sdhci3_set_platdata(&hsmmc3_platdata);
> +}
> +EXPORT_SYMBOL(s3c_sdhci_set_platdata);

There is _NO NEED_ to export these, they really should not be used outside
of the machine initialisation.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From ben-linux at fluff.org  Tue Jun 15 08:02:45 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Tue, 15 Jun 2010 13:02:45 +0100
Subject: [PATCH 1/3] ARM: SAMSUNG: Add the member of platdata to
	implement SDMMC Write Protection
In-Reply-To: <1276601268-7226-2-git-send-email-kgene.kim@samsung.com>
References: <1276601268-7226-1-git-send-email-kgene.kim@samsung.com>
	<1276601268-7226-2-git-send-email-kgene.kim@samsung.com>
Message-ID: <20100615120245.GD7248@trinity.fluff.org>

On Tue, Jun 15, 2010 at 08:27:46PM +0900, Kukjin Kim wrote:
> From: Lee Hyuk <hyuk1.lee at samsung.com>
> 
> This patch adds the members of platdata which are cfg_wp and get_ro.
> The cfg_wp is the function for setting the specific GPIO for WP pin
> and get_ro is the function for getting data from the assigned GPIO.

Why not just pass gpio numbers, and have the sdhci-s3c driver claim them
if they are valid?
 
> Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
>  arch/arm/plat-samsung/dev-hsmmc.c          |    4 ++++
>  arch/arm/plat-samsung/dev-hsmmc1.c         |    4 ++++
>  arch/arm/plat-samsung/dev-hsmmc2.c         |    4 ++++
>  arch/arm/plat-samsung/dev-hsmmc3.c         |    4 ++++
>  arch/arm/plat-samsung/include/plat/sdhci.h |    6 ++++++
>  5 files changed, 22 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
> index 4c05b39..f2bae6f 100644
> --- a/arch/arm/plat-samsung/dev-hsmmc.c
> +++ b/arch/arm/plat-samsung/dev-hsmmc.c
> @@ -65,4 +65,8 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
>  		set->cfg_gpio = pd->cfg_gpio;
>  	if (pd->cfg_card)
>  		set->cfg_card = pd->cfg_card;
> +	if (pd->cfg_wp)
> +		set->cfg_wp = pd->cfg_wp;
> +	if (pd->get_ro)
> +		set->get_ro = pd->get_ro;
>  }
> diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
> index e49bc4c..b326e0d 100644
> --- a/arch/arm/plat-samsung/dev-hsmmc1.c
> +++ b/arch/arm/plat-samsung/dev-hsmmc1.c
> @@ -65,4 +65,8 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
>  		set->cfg_gpio = pd->cfg_gpio;
>  	if (pd->cfg_card)
>  		set->cfg_card = pd->cfg_card;
> +	if (pd->cfg_wp)
> +		set->cfg_wp = pd->cfg_wp;
> +	if (pd->get_ro)
> +		set->get_ro = pd->get_ro;
>  }
> diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
> index 824580b..3474ef2 100644
> --- a/arch/arm/plat-samsung/dev-hsmmc2.c
> +++ b/arch/arm/plat-samsung/dev-hsmmc2.c
> @@ -66,4 +66,8 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
>  		set->cfg_gpio = pd->cfg_gpio;
>  	if (pd->cfg_card)
>  		set->cfg_card = pd->cfg_card;
> +	if (pd->cfg_wp)
> +		set->cfg_wp = pd->cfg_wp;
> +	if (pd->get_ro)
> +		set->get_ro = pd->get_ro;
>  }
> diff --git a/arch/arm/plat-samsung/dev-hsmmc3.c b/arch/arm/plat-samsung/dev-hsmmc3.c
> index 05d5ea4..1da8ea7 100644
> --- a/arch/arm/plat-samsung/dev-hsmmc3.c
> +++ b/arch/arm/plat-samsung/dev-hsmmc3.c
> @@ -69,4 +69,8 @@ void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
>  		set->cfg_gpio = pd->cfg_gpio;
>  	if (pd->cfg_card)
>  		set->cfg_card = pd->cfg_card;
> +	if (pd->cfg_wp)
> +		set->cfg_wp = pd->cfg_wp;
> +	if (pd->get_ro)
> +		set->get_ro = pd->get_ro;
>  }
> diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
> index 1314ffa..da198d8 100644
> --- a/arch/arm/plat-samsung/include/plat/sdhci.h
> +++ b/arch/arm/plat-samsung/include/plat/sdhci.h
> @@ -29,6 +29,8 @@ struct mmc_ios;
>   *            is necessary the controllers and/or GPIO blocks require the
>   *	      changing of driver-strength and other controls dependant on
>   *	      the card and speed of operation.
> + * @cfg_wp: Configure the GPIO in order to allocate WP pin.
> + * @get_ro: Call back function for getting data from the allocated GPIO.

if you just used gpio calls and passed a gpio number here,
you'd not need cfg_wp.

>   *
>   * Initialisation data specific to either the machine or the platform
>   * for the device driver to use or call-back when configuring gpio or
> @@ -45,6 +47,8 @@ struct s3c_sdhci_platdata {
>  			    void __iomem *regbase,
>  			    struct mmc_ios *ios,
>  			    struct mmc_card *card);
> +	void	(*cfg_wp)(int dev_id);
> +	int	(*get_ro)(struct mmc_host *mmc);
>  };
>  
>  /**
> @@ -234,6 +238,8 @@ extern void s5pv210_setup_sdhci_cfg_card(struct platform_device *dev,
>  					   struct mmc_ios *ios,
>  					   struct mmc_card *card);
>  
> +extern void s3c_sdhci_set_platdata(void);
> +
>  #ifdef CONFIG_S3C_DEV_HSMMC
>  static inline void s5pv210_default_sdhci0(void)
>  {
> -- 
> 1.6.2.5
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From ben-linux at fluff.org  Tue Jun 15 08:04:06 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Tue, 15 Jun 2010 13:04:06 +0100
Subject: [PATCH 3/3] sdhci-s3c: Add SDHCI_QUIRK_NO_WP_BIT for Samsung SoC
In-Reply-To: <1276601268-7226-4-git-send-email-kgene.kim@samsung.com>
References: <1276601268-7226-1-git-send-email-kgene.kim@samsung.com>
	<1276601268-7226-4-git-send-email-kgene.kim@samsung.com>
Message-ID: <20100615120406.GE7248@trinity.fluff.org>

On Tue, Jun 15, 2010 at 08:27:48PM +0900, Kukjin Kim wrote:
> From: Lee Hyuk <hyuk1.lee at samsung.com>
> 
> S5PV210 HSMMC host controller doesn't have the WP pin which should be
> connnected with SDMMC card WP pin. So if there are the cfg_wp and get_ro
> in pdata, configure the WP pin and replace get_ro function in sdhci with
> get_ro function in pdata.
> 
> Signed-off-by: Hyuk Lee <hyuk1.lee at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
>  drivers/mmc/host/sdhci-s3c.c |   12 ++++++++++++
>  drivers/mmc/host/sdhci.c     |    3 +++
>  drivers/mmc/host/sdhci.h     |    3 +++
>  3 files changed, 18 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
> index af21792..857cbed 100644
> --- a/drivers/mmc/host/sdhci-s3c.c
> +++ b/drivers/mmc/host/sdhci-s3c.c
> @@ -311,6 +311,9 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>  	if (pdata->cfg_gpio)
>  		pdata->cfg_gpio(pdev, pdata->max_width);
>  
> +	if (pdata->get_ro)
> +		sdhci_s3c_ops.get_ro = pdata->get_ro;
> +
>  	host->hw_name = "samsung-hsmmc";
>  	host->ops = &sdhci_s3c_ops;
>  	host->quirks = 0;
> @@ -335,6 +338,15 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
>  	host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
>  			 SDHCI_QUIRK_32BIT_DMA_SIZE);
>  
> +	/* Controller's WP pin donsn't connected with SD card. So we allocate
> +	 * a GPIO for getting WP data form SD card  and use that data as
> +	 * the return value of the get_ro function */
> +	host->quirks |= SDHCI_QUIRK_NO_WP_BIT;

I really think this should be a custom-wp quirk, not a we-don-have-wp
quirk.

> +
> +	/* to configure gpio pin as a card write protection signal */
> +	if (pdata->cfg_wp)
> +		pdata->cfg_wp(pdev->id);
> +
>  	ret = sdhci_add_host(host);
>  	if (ret) {
>  		dev_err(dev, "sdhci_add_host() failed\n");
> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> index c6d1bd8..2f8dfbc 100644
> --- a/drivers/mmc/host/sdhci.c
> +++ b/drivers/mmc/host/sdhci.c
> @@ -1192,6 +1192,9 @@ static int sdhci_get_ro(struct mmc_host *mmc)
>  
>  	host = mmc_priv(mmc);
>  
> +	if ((host->quirks & SDHCI_QUIRK_NO_WP_BIT) && host->ops->get_ro)
> +		return host->ops->get_ro(mmc);
> +
>  	spin_lock_irqsave(&host->lock, flags);
>  
>  	if (host->flags & SDHCI_DEVICE_DEAD)
> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
> index c846813..f479e22 100644
> --- a/drivers/mmc/host/sdhci.h
> +++ b/drivers/mmc/host/sdhci.h
> @@ -240,6 +240,8 @@ struct sdhci_host {
>  #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN		(1<<25)
>  /* Controller cannot support End Attribute in NOP ADMA descriptor */
>  #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC		(1<<26)
> +/* Controller has no write-protect pin connected with SD card */
> +#define SDHCI_QUIRK_NO_WP_BIT                          (1<<27)
>  
>  	int			irq;		/* Device IRQ */
>  	void __iomem *		ioaddr;		/* Mapped address */
> @@ -312,6 +314,7 @@ struct sdhci_ops {
>  	unsigned int	(*get_max_clock)(struct sdhci_host *host);
>  	unsigned int	(*get_min_clock)(struct sdhci_host *host);
>  	unsigned int	(*get_timeout_clock)(struct sdhci_host *host);
> +	int		(*get_ro)(struct mmc_host *mmc);
>  };
>  
>  #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
> -- 
> 1.6.2.5
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From mcuelenaere at gmail.com  Tue Jun 15 08:04:54 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Tue, 15 Jun 2010 14:04:54 +0200
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 PrimeCells
In-Reply-To: <AANLkTil7b5Pg5q18eGvGY_cFH75rdpSuZhigH4vcjrnu@mail.gmail.com>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>	<002001cb0c75$0a54fd00$1efef700$%kim@samsung.com>	<AANLkTil7gb7SjrYPrHPfSomwxLlHpowXOZd_Qr125jvr@mail.gmail.com>	<4C176148.4020507@gmail.com>
	<AANLkTil7b5Pg5q18eGvGY_cFH75rdpSuZhigH4vcjrnu@mail.gmail.com>
Message-ID: <4C176C66.20008@gmail.com>

Op 15-06-10 13:39, Jassi Brar schreef:
> On Tue, Jun 15, 2010 at 8:17 PM, Maurus Cuelenaere
> <mcuelenaere at gmail.com> wrote:
>   
>> Op 15-06-10 12:45, Jassi Brar schreef:
>>     
>>> On Tue, Jun 15, 2010 at 7:25 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>>>       
>>>> Linus Walleij wrote:
>>>>         
>>>>> This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells
>>>>> based on the implementation earlier submitted by Peter Pearse.
>>>>> This is working like a charm for memcpy on the PB11MPCore, but
>>>>> slave DMA to devices is still not working.
>>>>>
>>>>> This DMA controller is used in mostly unmodified form in the ARM
>>>>> RealView and Versatile platforms, in the ST-Ericsson Nomadik, and
>>>>> in the ST SPEAr platform.
>>>>>
>>>>> It has been converted to use the header from the Samsung PL080
>>>>> derivate instead of its own defintions, and can potentially support
>>>>> several controllers in the same system.
>>>>>
>>>>> Cc: Peter Pearse <peter.pearse at arm.com>
>>>>> Cc: Ben Dooks <ben-linux at fluff.org>
>>>>> Cc: Kukjin Kim <kgene.kim at samsung.com>
>>>>>           
>>>> Looks good, but please give me some time to test on the board(SMDK6410).
>>>> If any problem, let you know. Of course no problem, will ack.
>>>>         
>>> Samsung doesn't use the DMA API, so this driver is unlikely to work.
>>>       
>> It doesn't indeed, but it could be adapted to be a wrapper around the DMA engine API.
>> Or even better, the drivers could be adapted to use that API.
>>     
> I don't particularly like the idea of making Samsung's drivers use the DMA API.
> IMHO the S3C dma api is better atm.
>   

At the moment it is better, true. But I do think it'd be better to use a
generic API than an arch-specific one.
I'm not familiar enough with both of them to know what functionality is
currently missing but I do think that once the DMA engine API is up to
speed, it should replace the s3c one.

-- 
Maurus Cuelenaere



From ext-phil.2.carmody at nokia.com  Tue Jun 15 08:46:38 2010
From: ext-phil.2.carmody at nokia.com (Phil Carmody)
Date: Tue, 15 Jun 2010 15:46:38 +0300
Subject: [PATCH 1/1] ARM: unwind - optimise linked-list searches for modules
Message-ID: <1276605998-19275-1-git-send-email-ext-phil.2.carmody@nokia.com>

With several sections per module, and dozens of modules, the
searches down the linked list would dominate the lookup time,
dwarfing any savings from the binary search within the section.

A simple move-to-front optimisation exploits the commonality
of the code paths taken, and in simple real-world tests reduces
the number of steps in the search to barely more than 1.

Signed-off-by: Phil Carmody <ext-phil.2.carmody at nokia.com>
---
 arch/arm/kernel/unwind.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index dd81a91..2e88abf 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -146,6 +146,8 @@ static struct unwind_idx *unwind_find_idx(unsigned long addr)
 			    addr < table->end_addr) {
 				idx = search_index(addr, table->start,
 						   table->stop - 1);
+				/* MTF with 50 modules: 80 steps becomes ~1 */
+				list_move(&table->list, &unwind_tables);
 				break;
 			}
 		}
-- 
1.6.0.4



From grinberg at compulab.co.il  Tue Jun 15 10:47:41 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Tue, 15 Jun 2010 17:47:41 +0300
Subject: [PATCH 1/5] usb/otg/ulpi: extend the generic ulpi driver.
In-Reply-To: <AANLkTimHDBI0grgNrcvZ-BWS9kd0z4lFqEgVoyM4ysVJ@mail.gmail.com>
References: <1275464450-23003-1-git-send-email-grinberg@compulab.co.il>
	<1275464450-23003-2-git-send-email-grinberg@compulab.co.il>
	<AANLkTimHDBI0grgNrcvZ-BWS9kd0z4lFqEgVoyM4ysVJ@mail.gmail.com>
Message-ID: <4C17928D.6020402@compulab.co.il>



On 06/12/10 12:35, Eric Miao wrote:
>> +/* ULPI Function Control Register bits */
>> +#define ULPI_FC_HS     0               /* Enable HS tcvr */
>> +#define ULPI_FC_FS     (0x1 << 0)      /* Enable FS tcvr */
>> +#define ULPI_FC_LS     (0x2 << 0)      /* Enable LS tcvr */
>> +#define ULPI_FC_FS_LS  (0x3 << 0)      /* Enable FS tcvr for LS packets */
>> +#define ULPI_FC_TRM_SEL        (0x1 << 2)      /* Internal pullup and HS termination */
>> +#define ULPI_FC_NODRV  (0x1 << 3)      /* Non-Driving Operation */
>> +#define ULPI_FC_NONRZI (0x1 << 4)      /* Disable bit-stuff and NRZI encode */
>> +#define ULPI_FC_RESET  (0x1 << 5)      /* Reset the UTMI core */
>> +#define ULPI_FC_DEFAULT        0x41            /* Function Control Register Default */
>> +
>> +
>> +/* ULPI Interface Register bits */
>> +#define ULPI_IC_6PIN   (1 << 0)        /* XCVR 6 serial pin mode */
>> +#define ULPI_IC_3PIN   (1 << 1)        /* XCVR 3 serial pin mode */
>> +#define ULPI_IC_CARKIT (1 << 2)        /* Carkit mode */
>> +#define ULPI_IC_CLKSPND        (1 << 3)        /* Active low clock suspend */
>> +#define ULPI_IC_AUTORES        (1 << 4)        /* PHY auto transmit resume signal */
>> +#define ULPI_IC_VBUSINV        (1 << 5)        /* Invert the external VBUS indicator */
>> +#define ULPI_IC_INDPT  (1 << 6)        /* Indicator Pass Through */
>> +#define ULPI_IC_DISPRT (1 << 7)        /* Interface Protect Disable */
>> +#define ULPI_IC_DEFAULT        0x0             /* Interface Control Register Default */
>> +
>>  struct otg_transceiver *otg_ulpi_create(struct otg_io_access_ops *ops,
>> -                                       unsigned int flags);
>> +                                       u8 fc_flags, u8 ic_flags, u8 otg_flags);
>>
>>     
> Just one comment about the API, I might not know all the detail of these two
> FC/IC registers, but maybe it can be even better:
>
> 1. separate flags definition from the FC/IC register bits, i.e. sometimes not
> all the register bits will be used, and some times a meaningful flag name is
> better (though the flag definition can be encoded properly to simplify the
> algorithm to map into the actual register bits)
>
>   

I understand what you mean and I think it is indeed better to keep the
bits and registers private
to the ulpi driver and export only some usable flags.
Meanwhile, there is new ulpi.h, merged between 2.6.34 and 2.6.35-rc1 and
it violates already
the concept of keeping the bits/regs private.
For now there are too many combinations of those bits and it is
impossible to summarize them
in some way usable flags.
pxa310 uses only a reletively small subset of the ulpi register bits, so
we could define
flags specific to pxa310 in the new pxa310-u2d.c or pxa310-u2d.h, so
board will only pass those flags
to the pxa310-u2d.c driver which in turn will translate them to the ulpi
register settings.

> 2. extend the original 'flags' variable and bits for the above definitions, so
> we can keep the API unchanged.
>   

Well, I think that the current API is still fresh and it does only
support current implementation
in which the flags are stored in otg_transceiver and there is no any
private data to the ulpi driver.

> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>   

-- 
Regards,
Igor.



From richardcochran at gmail.com  Tue Jun 15 12:06:48 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:06:48 +0200
Subject: [PATCH v4 00/12] ptp: IEEE 1588 clock support
Message-ID: <cover.1276615626.git.richard.cochran@omicron.at>

Now and again there has been talk on the netdev list of adding PTP
support into Linux. One part of the picture is already in place, the
SO_TIMESTAMPING API for hardware time stamping. This patch set offers
the missing second part needed for complete IEEE 1588 support.

The only feature still to be implemented is the hook into the PPS
subsystem, to synchronize the Linux clock to the PTP clock.

The first seven patches concern phylib. A new generation of PHYs with
timestamping capabilities is appearing on the market. In order to
support hardware timestamping on these devices in Linux, a number of
adjustments will have to be made in the PHY subsystem. The reasons for
the changes are explained inline at the top of the patches.

The last five patches provide the PTP subsystem itself.

* Why all the CCs?

  1. The patches probably should go through netdev.
  2. One driver is for PowerPC, and adds device tree stuff.
  3. One driver is for the ARM Xscale IXP465

* Open Issues:

** DP83640
   In order to make this work, three lines must be added into the MAC
   driver. Since this PHY can be connected to almost any MAC, I did
   not do anything about that. If you have the DP83640 and want to try
   the driver, you need to add three lines to your MAC driver.

   1. Before mdio_register, add
		bus->locktype = MDIOBUS_ATOMIC_RW;
   2. In the .ndo_start_xmit function, add
		skb_tx_timestamp()
   3. In the NAPI poll function, add
		skb_rx_timestamp()

** IXP465
   I do not know how to correctly choose the timestamp "channel" based
   on the port identifier:

	#define PORT2CHANNEL(p)		1
	/*
	 * PHYSICAL_ID(p->id) ?
	 * TODO - Figure out correct mapping.
	 */

* Patch ChangeLog

** v4
*** general
   - Added a clock driver for the National Semiconductor PHYTER.
   - Added a clock driver for the Intel IXP465.
   - Made more stylish according to checkstyle.pl.
*** gianfar
   - Replace device_type and model with compatible string ("fsl,etsec-ptp")
   - Register only one interrupt, since others are superfluous.
   - Combine ptp clock instance with private variable structure.
   - ISR now returns NONE or HANDLED properly.
   - Print error message if something is missing from the device nodes.

** v3
*** general
   - Added documentation on writing clock drivers.
   - Added the ioctls for the ancillary clock features.
   - Changed wrong subsys_initcall() to module_init() in clock drivers.
   - Removed the (too coarse) character device mutex.
   - Setting the clock now requires CAP_SYS_TIME.
*** gianfar
   - Added alarm feature.
   - Added device tree node binding description.
   - Added fine grain locking of the clock registers.
   - Added the external time stamp feature.
   - Added white space for better style.
   - Coverted base+offset to structure pointers for register access.
   - When removing the driver, we now disable all PTP functions.

** v2
   - Changed clock list from a static array into a dynamic list. Also,
     use a bitmap to manage the clock's minor numbers.
   - Replaced character device semaphore with a mutex.
   - Drop .ko from module names in Kbuild help.
   - Replace deprecated unifdef-y with header-y for user space header file.
   - Added links to both of the ptpd patches on sourceforge.
   - Gianfar driver now gets parameters from device tree.
   - Added API documentation to Documentation/ptp/ptp.txt

Looking forward to your feedback,
Richard


Richard Cochran (12):
  phylib: preserve ifreq parameter when calling generic phy_mii_ioctl()
  phylib: do not filter phy_mii_ioctl()
  phylib: add a driver method for the SIOCSHWTSTAMP ioctl.
  phylib: add a way to make PHY time stamps possible.
  phylib: Allow reading and writing a mii bus from atomic context.
  ptp: add a BPF to help drivers detect PTP packets.
  phylib: support the National Semiconductor DP83640 PHY.
  ptp: Added a brand new class driver for ptp clocks.
  ptp: Added a clock that uses the Linux system time.
  ptp: Added a clock that uses the eTSEC found on the MPC85xx.
  ptp: Added a clock driver for the IXP46x.
  ptp: Added a clock driver for the National Semiconductor PHYTER.

 Documentation/powerpc/dts-bindings/fsl/tsec.txt |   54 ++
 Documentation/ptp/ptp.txt                       |   95 ++++
 Documentation/ptp/testptp.c                     |  269 ++++++++++
 Documentation/ptp/testptp.mk                    |   33 ++
 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h   |   67 +++
 arch/powerpc/boot/dts/mpc8313erdb.dts           |   13 +
 arch/powerpc/boot/dts/p2020ds.dts               |   13 +
 arch/powerpc/boot/dts/p2020rdb.dts              |   13 +
 drivers/Kconfig                                 |    2 +
 drivers/Makefile                                |    1 +
 drivers/net/Makefile                            |    1 +
 drivers/net/arm/ixp4xx_eth.c                    |  197 ++++++++-
 drivers/net/au1000_eth.c                        |    2 +-
 drivers/net/bcm63xx_enet.c                      |    2 +-
 drivers/net/cpmac.c                             |    5 +-
 drivers/net/dnet.c                              |    2 +-
 drivers/net/ethoc.c                             |    2 +-
 drivers/net/fec.c                               |    2 +-
 drivers/net/fec_mpc52xx.c                       |    2 +-
 drivers/net/fs_enet/fs_enet-main.c              |    3 +-
 drivers/net/gianfar.c                           |    2 +-
 drivers/net/gianfar_ptp.c                       |  518 ++++++++++++++++++++
 drivers/net/gianfar_ptp_reg.h                   |  113 +++++
 drivers/net/macb.c                              |    2 +-
 drivers/net/mv643xx_eth.c                       |    2 +-
 drivers/net/octeon/octeon_mgmt.c                |    2 +-
 drivers/net/phy/Kconfig                         |   16 +
 drivers/net/phy/Makefile                        |    1 +
 drivers/net/phy/dp83640.c                       |  595 +++++++++++++++++++++++
 drivers/net/phy/dp83640_reg.h                   |  237 +++++++++
 drivers/net/phy/mdio_bus.c                      |   35 ++-
 drivers/net/phy/phy.c                           |    8 +-
 drivers/net/sb1250-mac.c                        |    2 +-
 drivers/net/sh_eth.c                            |    2 +-
 drivers/net/smsc911x.c                          |    2 +-
 drivers/net/smsc9420.c                          |    2 +-
 drivers/net/stmmac/stmmac_main.c                |   22 +-
 drivers/net/tc35815.c                           |    2 +-
 drivers/net/tg3.c                               |    2 +-
 drivers/ptp/Kconfig                             |   64 +++
 drivers/ptp/Makefile                            |    7 +
 drivers/ptp/ptp_clock.c                         |  514 ++++++++++++++++++++
 drivers/ptp/ptp_ixp46x.c                        |  231 +++++++++
 drivers/ptp/ptp_linux.c                         |  136 ++++++
 drivers/staging/octeon/ethernet-mdio.c          |    2 +-
 include/linux/Kbuild                            |    1 +
 include/linux/phy.h                             |   22 +-
 include/linux/ptp_classify.h                    |  118 +++++
 include/linux/ptp_clock.h                       |   79 +++
 include/linux/ptp_clock_kernel.h                |  137 ++++++
 include/linux/skbuff.h                          |   32 ++
 kernel/time/ntp.c                               |    2 +
 net/Kconfig                                     |   11 +
 net/dsa/slave.c                                 |    3 +-
 54 files changed, 3651 insertions(+), 51 deletions(-)
 create mode 100644 Documentation/ptp/ptp.txt
 create mode 100644 Documentation/ptp/testptp.c
 create mode 100644 Documentation/ptp/testptp.mk
 create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
 create mode 100644 drivers/net/gianfar_ptp.c
 create mode 100644 drivers/net/gianfar_ptp_reg.h
 create mode 100644 drivers/net/phy/dp83640.c
 create mode 100644 drivers/net/phy/dp83640_reg.h
 create mode 100644 drivers/ptp/Kconfig
 create mode 100644 drivers/ptp/Makefile
 create mode 100644 drivers/ptp/ptp_clock.c
 create mode 100644 drivers/ptp/ptp_ixp46x.c
 create mode 100644 drivers/ptp/ptp_linux.c
 create mode 100644 include/linux/ptp_classify.h
 create mode 100644 include/linux/ptp_clock.h
 create mode 100644 include/linux/ptp_clock_kernel.h



From richardcochran at gmail.com  Tue Jun 15 12:07:26 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:07:26 +0200
Subject: [PATCH 01/12] phylib: preserve ifreq parameter when calling
	generic phy_mii_ioctl()
In-Reply-To: <cover.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
Message-ID: <cd8ba64792e4ee94f42a5ef765a65e02c1446b0c.1276615626.git.richard.cochran@omicron.at>

The phy_mii_ioctl() function unnecessarily throws away the original ifreq.
We need access to the ifreq in order to support PHYs that can perform
hardware time stamping.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 drivers/net/arm/ixp4xx_eth.c           |    3 ++-
 drivers/net/au1000_eth.c               |    2 +-
 drivers/net/bcm63xx_enet.c             |    2 +-
 drivers/net/cpmac.c                    |    2 +-
 drivers/net/dnet.c                     |    2 +-
 drivers/net/ethoc.c                    |    2 +-
 drivers/net/fec.c                      |    2 +-
 drivers/net/fec_mpc52xx.c              |    2 +-
 drivers/net/fs_enet/fs_enet-main.c     |    3 +--
 drivers/net/gianfar.c                  |    2 +-
 drivers/net/macb.c                     |    2 +-
 drivers/net/mv643xx_eth.c              |    2 +-
 drivers/net/octeon/octeon_mgmt.c       |    2 +-
 drivers/net/phy/phy.c                  |    3 ++-
 drivers/net/sb1250-mac.c               |    2 +-
 drivers/net/sh_eth.c                   |    2 +-
 drivers/net/smsc911x.c                 |    2 +-
 drivers/net/smsc9420.c                 |    2 +-
 drivers/net/stmmac/stmmac_main.c       |    2 +-
 drivers/net/tc35815.c                  |    2 +-
 drivers/net/tg3.c                      |    2 +-
 drivers/staging/octeon/ethernet-mdio.c |    2 +-
 include/linux/phy.h                    |    2 +-
 net/dsa/slave.c                        |    3 +--
 24 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index ee2f842..4f1cc71 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -782,7 +782,8 @@ static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
 
 	if (!netif_running(dev))
 		return -EINVAL;
-	return phy_mii_ioctl(port->phydev, if_mii(req), cmd);
+
+	return phy_mii_ioctl(port->phydev, req, cmd);
 }
 
 /* ethtool support */
diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c
index ece6128..386d4fe 100644
--- a/drivers/net/au1000_eth.c
+++ b/drivers/net/au1000_eth.c
@@ -978,7 +978,7 @@ static int au1000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	if (!aup->phy_dev)
 		return -EINVAL; /* PHY not controllable */
 
-	return phy_mii_ioctl(aup->phy_dev, if_mii(rq), cmd);
+	return phy_mii_ioctl(aup->phy_dev, rq, cmd);
 }
 
 static const struct net_device_ops au1000_netdev_ops = {
diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c
index faf5add..0d2c5da 100644
--- a/drivers/net/bcm63xx_enet.c
+++ b/drivers/net/bcm63xx_enet.c
@@ -1496,7 +1496,7 @@ static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	if (priv->has_phy) {
 		if (!priv->phydev)
 			return -ENODEV;
-		return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
+		return phy_mii_ioctl(priv->phydev, rq, cmd);
 	} else {
 		struct mii_if_info mii;
 
diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c
index 3c58db5..d4c5ca4 100644
--- a/drivers/net/cpmac.c
+++ b/drivers/net/cpmac.c
@@ -848,7 +848,7 @@ static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 		return -EINVAL;
 	if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
 	    (cmd == SIOCSMIIREG))
-		return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
+		return phy_mii_ioctl(priv->phy, ifr, cmd);
 
 	return -EOPNOTSUPP;
 }
diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c
index 8b0f50b..4ea7141 100644
--- a/drivers/net/dnet.c
+++ b/drivers/net/dnet.c
@@ -797,7 +797,7 @@ static int dnet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	if (!phydev)
 		return -ENODEV;
 
-	return phy_mii_ioctl(phydev, if_mii(rq), cmd);
+	return phy_mii_ioctl(phydev, rq, cmd);
 }
 
 static void dnet_get_drvinfo(struct net_device *dev,
diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c
index 6ed2df1..8102f01 100644
--- a/drivers/net/ethoc.c
+++ b/drivers/net/ethoc.c
@@ -734,7 +734,7 @@ static int ethoc_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 		phy = priv->phy;
 	}
 
-	return phy_mii_ioctl(phy, mdio, cmd);
+	return phy_mii_ioctl(phy, ifr, cmd);
 }
 
 static int ethoc_config(struct net_device *dev, struct ifmap *map)
diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index a3cae4e..f24f49e 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -828,7 +828,7 @@ static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	if (!phydev)
 		return -ENODEV;
 
-	return phy_mii_ioctl(phydev, if_mii(rq), cmd);
+	return phy_mii_ioctl(phydev, rq, cmd);
 }
 
 static void fec_enet_free_buffers(struct net_device *dev)
diff --git a/drivers/net/fec_mpc52xx.c b/drivers/net/fec_mpc52xx.c
index 25e6cc6..fdbf148 100644
--- a/drivers/net/fec_mpc52xx.c
+++ b/drivers/net/fec_mpc52xx.c
@@ -826,7 +826,7 @@ static int mpc52xx_fec_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	if (!priv->phydev)
 		return -ENOTSUPP;
 
-	return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
+	return phy_mii_ioctl(priv->phydev, rq, cmd);
 }
 
 static const struct net_device_ops mpc52xx_fec_netdev_ops = {
diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c
index 309a0ea..f08cff9 100644
--- a/drivers/net/fs_enet/fs_enet-main.c
+++ b/drivers/net/fs_enet/fs_enet-main.c
@@ -963,12 +963,11 @@ static const struct ethtool_ops fs_ethtool_ops = {
 static int fs_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 {
 	struct fs_enet_private *fep = netdev_priv(dev);
-	struct mii_ioctl_data *mii = (struct mii_ioctl_data *)&rq->ifr_data;
 
 	if (!netif_running(dev))
 		return -EINVAL;
 
-	return phy_mii_ioctl(fep->phydev, mii, cmd);
+	return phy_mii_ioctl(fep->phydev, rq, cmd);
 }
 
 extern int fs_mii_connect(struct net_device *dev);
diff --git a/drivers/net/gianfar.c b/drivers/net/gianfar.c
index ab54821..9d88e20 100644
--- a/drivers/net/gianfar.c
+++ b/drivers/net/gianfar.c
@@ -834,7 +834,7 @@ static int gfar_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	if (!priv->phydev)
 		return -ENODEV;
 
-	return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
+	return phy_mii_ioctl(priv->phydev, rq, cmd);
 }
 
 static unsigned int reverse_bitmap(unsigned int bit_map, unsigned int max_qs)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index 40797fb..ff2f158 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -1082,7 +1082,7 @@ static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	if (!phydev)
 		return -ENODEV;
 
-	return phy_mii_ioctl(phydev, if_mii(rq), cmd);
+	return phy_mii_ioctl(phydev, rq, cmd);
 }
 
 static const struct net_device_ops macb_netdev_ops = {
diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index e345ec8..e3ab182 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -2452,7 +2452,7 @@ static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 	struct mv643xx_eth_private *mp = netdev_priv(dev);
 
 	if (mp->phy != NULL)
-		return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
+		return phy_mii_ioctl(mp->phy, ifr, cmd);
 
 	return -EOPNOTSUPP;
 }
diff --git a/drivers/net/octeon/octeon_mgmt.c b/drivers/net/octeon/octeon_mgmt.c
index 000e792..73a2671 100644
--- a/drivers/net/octeon/octeon_mgmt.c
+++ b/drivers/net/octeon/octeon_mgmt.c
@@ -620,7 +620,7 @@ static int octeon_mgmt_ioctl(struct net_device *netdev,
 	if (!p->phydev)
 		return -EINVAL;
 
-	return phy_mii_ioctl(p->phydev, if_mii(rq), cmd);
+	return phy_mii_ioctl(p->phydev, rq, cmd);
 }
 
 static void octeon_mgmt_adjust_link(struct net_device *netdev)
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 64be466..bd88d81 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -309,8 +309,9 @@ EXPORT_SYMBOL(phy_ethtool_gset);
  * current state.  Use at own risk.
  */
 int phy_mii_ioctl(struct phy_device *phydev,
-		struct mii_ioctl_data *mii_data, int cmd)
+		struct ifreq *ifr, int cmd)
 {
+	struct mii_ioctl_data *mii_data = if_mii(ifr);
 	u16 val = mii_data->val_in;
 
 	switch (cmd) {
diff --git a/drivers/net/sb1250-mac.c b/drivers/net/sb1250-mac.c
index 1f3acc3..e585c3f 100644
--- a/drivers/net/sb1250-mac.c
+++ b/drivers/net/sb1250-mac.c
@@ -2532,7 +2532,7 @@ static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	if (!netif_running(dev) || !sc->phy_dev)
 		return -EINVAL;
 
-	return phy_mii_ioctl(sc->phy_dev, if_mii(rq), cmd);
+	return phy_mii_ioctl(sc->phy_dev, rq, cmd);
 }
 
 static int sbmac_close(struct net_device *dev)
diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c
index 501a55f..8279f8e 100644
--- a/drivers/net/sh_eth.c
+++ b/drivers/net/sh_eth.c
@@ -1233,7 +1233,7 @@ static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
 	if (!phydev)
 		return -ENODEV;
 
-	return phy_mii_ioctl(phydev, if_mii(rq), cmd);
+	return phy_mii_ioctl(phydev, rq, cmd);
 }
 
 #if defined(SH_ETH_HAS_TSU)
diff --git a/drivers/net/smsc911x.c b/drivers/net/smsc911x.c
index cc55974..56dc2ff 100644
--- a/drivers/net/smsc911x.c
+++ b/drivers/net/smsc911x.c
@@ -1538,7 +1538,7 @@ static int smsc911x_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 	if (!netif_running(dev) || !pdata->phy_dev)
 		return -EINVAL;
 
-	return phy_mii_ioctl(pdata->phy_dev, if_mii(ifr), cmd);
+	return phy_mii_ioctl(pdata->phy_dev, ifr, cmd);
 }
 
 static int
diff --git a/drivers/net/smsc9420.c b/drivers/net/smsc9420.c
index 6cdee6a..b09ee1c 100644
--- a/drivers/net/smsc9420.c
+++ b/drivers/net/smsc9420.c
@@ -245,7 +245,7 @@ static int smsc9420_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 	if (!netif_running(dev) || !pd->phy_dev)
 		return -EINVAL;
 
-	return phy_mii_ioctl(pd->phy_dev, if_mii(ifr), cmd);
+	return phy_mii_ioctl(pd->phy_dev, ifr, cmd);
 }
 
 static int smsc9420_ethtool_get_settings(struct net_device *dev,
diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c
index a31d580..6af7471 100644
--- a/drivers/net/stmmac/stmmac_main.c
+++ b/drivers/net/stmmac/stmmac_main.c
@@ -1450,7 +1450,7 @@ static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 			return -EINVAL;
 
 		spin_lock(&priv->lock);
-		ret = phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
+		ret = phy_mii_ioctl(priv->phydev, rq, cmd);
 		spin_unlock(&priv->lock);
 	default:
 		break;
diff --git a/drivers/net/tc35815.c b/drivers/net/tc35815.c
index be08b75..99e423a 100644
--- a/drivers/net/tc35815.c
+++ b/drivers/net/tc35815.c
@@ -2066,7 +2066,7 @@ static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 		return -EINVAL;
 	if (!lp->phy_dev)
 		return -ENODEV;
-	return phy_mii_ioctl(lp->phy_dev, if_mii(rq), cmd);
+	return phy_mii_ioctl(lp->phy_dev, rq, cmd);
 }
 
 static void tc35815_chip_reset(struct net_device *dev)
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 289cdc5..d4163f2 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -10954,7 +10954,7 @@ static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 		if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
 			return -EAGAIN;
 		phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
-		return phy_mii_ioctl(phydev, data, cmd);
+		return phy_mii_ioctl(phydev, ifr, cmd);
 	}
 
 	switch (cmd) {
diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c
index 7e0be8d..10a82ef 100644
--- a/drivers/staging/octeon/ethernet-mdio.c
+++ b/drivers/staging/octeon/ethernet-mdio.c
@@ -113,7 +113,7 @@ int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 	if (!priv->phydev)
 		return -EINVAL;
 
-	return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd);
+	return phy_mii_ioctl(priv->phydev, rq, cmd);
 }
 
 static void cvm_oct_adjust_link(struct net_device *dev)
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 987e111..d63736a 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -498,7 +498,7 @@ void phy_stop_machine(struct phy_device *phydev);
 int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd);
 int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd);
 int phy_mii_ioctl(struct phy_device *phydev,
-		struct mii_ioctl_data *mii_data, int cmd);
+		struct ifreq *ifr, int cmd);
 int phy_start_interrupts(struct phy_device *phydev);
 void phy_print_status(struct phy_device *phydev);
 struct phy_device* phy_device_create(struct mii_bus *bus, int addr, int phy_id);
diff --git a/net/dsa/slave.c b/net/dsa/slave.c
index 8fdca56..64ca2a6 100644
--- a/net/dsa/slave.c
+++ b/net/dsa/slave.c
@@ -164,10 +164,9 @@ out:
 static int dsa_slave_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 {
 	struct dsa_slave_priv *p = netdev_priv(dev);
-	struct mii_ioctl_data *mii_data = if_mii(ifr);
 
 	if (p->phy != NULL)
-		return phy_mii_ioctl(p->phy, mii_data, cmd);
+		return phy_mii_ioctl(p->phy, ifr, cmd);
 
 	return -EOPNOTSUPP;
 }
-- 
1.6.3.3



From richardcochran at gmail.com  Tue Jun 15 12:07:46 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:07:46 +0200
Subject: [PATCH 02/12] phylib: do not filter phy_mii_ioctl()
In-Reply-To: <cover.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
Message-ID: <4cd127a2aa2c40a1b573e079e0624f10d1d94867.1276615626.git.richard.cochran@omicron.at>

Two maverick drivers filter the ioctl commands passed to phy_mii_ioctl().
This is unnecessary since phylib will check the command in any case.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 drivers/net/cpmac.c              |    5 +----
 drivers/net/stmmac/stmmac_main.c |   22 ++++++++--------------
 2 files changed, 9 insertions(+), 18 deletions(-)

diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c
index d4c5ca4..0e47ca1 100644
--- a/drivers/net/cpmac.c
+++ b/drivers/net/cpmac.c
@@ -846,11 +846,8 @@ static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 		return -EINVAL;
 	if (!priv->phy)
 		return -EINVAL;
-	if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
-	    (cmd == SIOCSMIIREG))
-		return phy_mii_ioctl(priv->phy, ifr, cmd);
 
-	return -EOPNOTSUPP;
+	return phy_mii_ioctl(priv->phy, ifr, cmd);
 }
 
 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c
index 6af7471..acf0616 100644
--- a/drivers/net/stmmac/stmmac_main.c
+++ b/drivers/net/stmmac/stmmac_main.c
@@ -1437,24 +1437,18 @@ static void stmmac_poll_controller(struct net_device *dev)
 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 {
 	struct stmmac_priv *priv = netdev_priv(dev);
-	int ret = -EOPNOTSUPP;
+	int ret;
 
 	if (!netif_running(dev))
 		return -EINVAL;
 
-	switch (cmd) {
-	case SIOCGMIIPHY:
-	case SIOCGMIIREG:
-	case SIOCSMIIREG:
-		if (!priv->phydev)
-			return -EINVAL;
-
-		spin_lock(&priv->lock);
-		ret = phy_mii_ioctl(priv->phydev, rq, cmd);
-		spin_unlock(&priv->lock);
-	default:
-		break;
-	}
+	if (!priv->phydev)
+		return -EINVAL;
+
+	spin_lock(&priv->lock);
+	ret = phy_mii_ioctl(priv->phydev, rq, cmd);
+	spin_unlock(&priv->lock);
+
 	return ret;
 }
 
-- 
1.6.3.3



From richardcochran at gmail.com  Tue Jun 15 12:08:06 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:08:06 +0200
Subject: [PATCH 03/12] phylib: add a driver method for the SIOCSHWTSTAMP ioctl.
In-Reply-To: <cover.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
Message-ID: <77fe18d640e35dcbfad1e117a4321f935500d5ac.1276615626.git.richard.cochran@omicron.at>

This patch adds a phy driver method for configuring hardware time stamping.
Drivers may optionally implement this function.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 drivers/net/phy/phy.c |    5 +++++
 include/linux/phy.h   |    3 +++
 2 files changed, 8 insertions(+), 0 deletions(-)

diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index bd88d81..5130db8 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -361,6 +361,11 @@ int phy_mii_ioctl(struct phy_device *phydev,
 		}
 		break;
 
+	case SIOCSHWTSTAMP:
+		if (phydev->drv->hwtstamp)
+			return phydev->drv->hwtstamp(phydev, ifr);
+		/* fall through */
+
 	default:
 		return -EOPNOTSUPP;
 	}
diff --git a/include/linux/phy.h b/include/linux/phy.h
index d63736a..a5e9df1 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -402,6 +402,9 @@ struct phy_driver {
 	/* Clears up any memory if needed */
 	void (*remove)(struct phy_device *phydev);
 
+	/* Handles SIOCSHWTSTAMP ioctl for hardware time stamping. */
+	int (*hwtstamp)(struct phy_device *phydev, struct ifreq *ifr);
+
 	struct device_driver driver;
 };
 #define to_phy_driver(d) container_of(d, struct phy_driver, driver)
-- 
1.6.3.3



From richardcochran at gmail.com  Tue Jun 15 12:08:20 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:08:20 +0200
Subject: [PATCH 04/12] phylib: add a way to make PHY time stamps possible.
In-Reply-To: <cover.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
Message-ID: <27c0ad283f025c2bb71e7ceb71be07f969939429.1276615626.git.richard.cochran@omicron.at>

This patch adds a new networking option to allow hardware time stamps
from PHY devices. Using PHY time stamps will still require adding two
inline function calls to each MAC driver. The CONFIG option makes these
calls safe to add, since the calls become NOOPs when the option is
disabled.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 include/linux/phy.h    |    4 ++++
 include/linux/skbuff.h |   32 ++++++++++++++++++++++++++++++++
 net/Kconfig            |   11 +++++++++++
 3 files changed, 47 insertions(+), 0 deletions(-)

diff --git a/include/linux/phy.h b/include/linux/phy.h
index a5e9df1..7a8caac 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -234,6 +234,8 @@ enum phy_state {
 	PHY_RESUMING
 };
 
+struct sk_buff;
+
 /* phy_device: An instance of a PHY
  *
  * drv: Pointer to the driver for this PHY instance
@@ -404,6 +406,8 @@ struct phy_driver {
 
 	/* Handles SIOCSHWTSTAMP ioctl for hardware time stamping. */
 	int (*hwtstamp)(struct phy_device *phydev, struct ifreq *ifr);
+	int (*rxtstamp)(struct phy_device *phydev, struct sk_buff *skb);
+	int (*txtstamp)(struct phy_device *phydev, struct sk_buff *skb);
 
 	struct device_driver driver;
 };
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 645e78d..7b650d4 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -29,6 +29,7 @@
 #include <linux/rcupdate.h>
 #include <linux/dmaengine.h>
 #include <linux/hrtimer.h>
+#include <linux/phy.h>
 
 /* Don't change this without changing skb_csum_unnecessary! */
 #define CHECKSUM_NONE 0
@@ -1942,6 +1943,37 @@ static inline ktime_t net_invalid_timestamp(void)
 extern void skb_tstamp_tx(struct sk_buff *orig_skb,
 			struct skb_shared_hwtstamps *hwtstamps);
 
+#ifdef CONFIG_NETWORK_PHY_TIMESTAMPING
+
+static inline void skb_tx_timetamp(struct phy_device *phy, struct sk_buff *skb)
+{
+	union skb_shared_tx *shtx = skb_tx(skb);
+
+	if (shtx->hardware && phy && phy->drv->txtstamp)
+		phy->drv->txtstamp(phy, skb);
+
+	if (shtx->software && !shtx->in_progress)
+		skb_tstamp_tx(skb, NULL);
+}
+
+static inline void skb_rx_timetamp(struct phy_device *phy, struct sk_buff *skb)
+{
+	if (phy && phy->drv->rxtstamp)
+		phy->drv->rxtstamp(phy, skb);
+}
+
+#else /* CONFIG_NETWORK_PHY_TIMESTAMPING */
+
+static inline void skb_tx_timetamp(struct phy_device *phy, struct sk_buff *skb)
+{
+}
+
+static inline void skb_rx_timetamp(struct phy_device *phy, struct sk_buff *skb)
+{
+}
+
+#endif /* !CONFIG_NETWORK_PHY_TIMESTAMPING */
+
 extern __sum16 __skb_checksum_complete_head(struct sk_buff *skb, int len);
 extern __sum16 __skb_checksum_complete(struct sk_buff *skb);
 
diff --git a/net/Kconfig b/net/Kconfig
index 0d68b40..3fa7ae3 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -86,6 +86,17 @@ config NETWORK_SECMARK
 	  to nfmark, but designated for security purposes.
 	  If you are unsure how to answer this question, answer N.
 
+config NETWORK_PHY_TIMESTAMPING
+	bool "Timestamping in PHY devices"
+	depends on EXPERIMENTAL
+	help
+	  This allows timestamping of network packets by PHYs with
+	  hardware timestamping capabilities. This option adds some
+	  overhead in the transmit and receive paths. Note that this
+	  option also requires support in the MAC driver.
+
+	  If you are unsure how to answer this question, answer N.
+
 menuconfig NETFILTER
 	bool "Network packet filtering framework (Netfilter)"
 	---help---
-- 
1.6.3.3



From richardcochran at gmail.com  Tue Jun 15 12:08:46 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:08:46 +0200
Subject: [PATCH 05/12] phylib: Allow reading and writing a mii bus from
	atomic context.
In-Reply-To: <cover.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
Message-ID: <1b8219e7d7993d0e8204b94e959477e3007534ce.1276615626.git.richard.cochran@omicron.at>

In order to support hardware time stamping from a PHY, it is necessary to
read from the PHY while running in_interrupt(). This patch allows a mii
bus to operate in an atomic context. An mii_bus driver may declare itself
capable for this mode. Drivers which do not do this will remain with the
default that bus operations may sleep.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 drivers/net/phy/mdio_bus.c |   35 ++++++++++++++++++++++++++++-------
 include/linux/phy.h        |   13 +++++++++++--
 2 files changed, 39 insertions(+), 9 deletions(-)

diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index 6a6b819..441be7d 100644
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -36,6 +36,22 @@
 #include <asm/irq.h>
 #include <asm/uaccess.h>
 
+static inline void mdiobus_lock(struct mii_bus *bus)
+{
+	if (MDIOBUS_SLEEPS_RW == bus->locktype)
+		mutex_lock(&bus->mdio_lock.m);
+	else
+		spin_lock(&bus->mdio_lock.s);
+}
+
+static inline void mdiobus_unlock(struct mii_bus *bus)
+{
+	if (MDIOBUS_SLEEPS_RW == bus->locktype)
+		mutex_unlock(&bus->mdio_lock.m);
+	else
+		spin_unlock(&bus->mdio_lock.s);
+}
+
 /**
  * mdiobus_alloc - allocate a mii_bus structure
  *
@@ -107,7 +123,10 @@ int mdiobus_register(struct mii_bus *bus)
 		return -EINVAL;
 	}
 
-	mutex_init(&bus->mdio_lock);
+	if (MDIOBUS_SLEEPS_RW == bus->locktype)
+		mutex_init(&bus->mdio_lock.m);
+	else
+		spin_lock_init(&bus->mdio_lock.s);
 
 	if (bus->reset)
 		bus->reset(bus);
@@ -212,11 +231,12 @@ int mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
 {
 	int retval;
 
-	BUG_ON(in_interrupt());
+	if (MDIOBUS_SLEEPS_RW == bus->locktype)
+		BUG_ON(in_interrupt());
 
-	mutex_lock(&bus->mdio_lock);
+	mdiobus_lock(bus);
 	retval = bus->read(bus, addr, regnum);
-	mutex_unlock(&bus->mdio_lock);
+	mdiobus_unlock(bus);
 
 	return retval;
 }
@@ -237,11 +257,12 @@ int mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val)
 {
 	int err;
 
-	BUG_ON(in_interrupt());
+	if (MDIOBUS_SLEEPS_RW == bus->locktype)
+		BUG_ON(in_interrupt());
 
-	mutex_lock(&bus->mdio_lock);
+	mdiobus_lock(bus);
 	err = bus->write(bus, addr, regnum, val);
-	mutex_unlock(&bus->mdio_lock);
+	mdiobus_unlock(bus);
 
 	return err;
 }
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 7a8caac..352b030 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -98,11 +98,20 @@ struct mii_bus {
 	int (*write)(struct mii_bus *bus, int phy_id, int regnum, u16 val);
 	int (*reset)(struct mii_bus *bus);
 
+	/* Indicates whether bus may be used from an atomic context. */
+	enum {
+		MDIOBUS_SLEEPS_RW,
+		MDIOBUS_ATOMIC_RW
+	} locktype;
+
 	/*
-	 * A lock to ensure that only one thing can read/write
+	 * A lock or mutex to ensure that only one thing can read/write
 	 * the MDIO bus at a time
 	 */
-	struct mutex mdio_lock;
+	union {
+		struct mutex m;
+		spinlock_t s;
+	} mdio_lock;
 
 	struct device *parent;
 	enum {
-- 
1.6.3.3



From richardcochran at gmail.com  Tue Jun 15 12:09:00 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:09:00 +0200
Subject: [PATCH 06/12] ptp: add a BPF to help drivers detect PTP packets.
In-Reply-To: <cover.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
Message-ID: <ff2f84e46a207813113e2d5b422ecb28848c9c8c.1276615626.git.richard.cochran@omicron.at>

Certain kinds of hardware time stamping units in both MACs and PHYs have
the limitation that they can only time stamp PTP packets. Drivers for such
hardware are left with the task of correctly matching skbs to time stamps.
This patch adds a BPF that drivers can use to classify PTP packets when
needed.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 include/linux/ptp_classify.h |  118 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 118 insertions(+), 0 deletions(-)
 create mode 100644 include/linux/ptp_classify.h

diff --git a/include/linux/ptp_classify.h b/include/linux/ptp_classify.h
new file mode 100644
index 0000000..e68efc3
--- /dev/null
+++ b/include/linux/ptp_classify.h
@@ -0,0 +1,118 @@
+/*
+ * PTP 1588 support
+ *
+ * This file implements a BPF that recognizes PTP event messages.
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _PTP_CLASSIFY_H_
+#define _PTP_CLASSIFY_H_
+
+#include <linux/if_ether.h>
+#include <linux/if_vlan.h>
+#include <linux/filter.h>
+#ifdef __KERNEL__
+#include <linux/in.h>
+#else
+#include <netinet/in.h>
+#endif
+
+#define PTP_CLASS_NONE  0x00 /* not a PTP event message */
+#define PTP_CLASS_V1    0x01 /* protocol version 1 */
+#define PTP_CLASS_V2    0x02 /* protocol version 2 */
+#define PTP_CLASS_VMASK 0x0f /* max protocol version is 15 */
+#define PTP_CLASS_IPV4  0x10 /* event in an IPV4 UDP packet */
+#define PTP_CLASS_IPV6  0x20 /* event in an IPV6 UDP packet */
+#define PTP_CLASS_L2    0x30 /* event in a L2 packet */
+#define PTP_CLASS_VLAN  0x40 /* event in a VLAN tagged L2 packet */
+#define PTP_CLASS_PMASK 0xf0 /* mask for the packet type field */
+
+#define PTP_CLASS_V1_IPV4 (PTP_CLASS_V1 | PTP_CLASS_IPV4)
+#define PTP_CLASS_V1_IPV6 (PTP_CLASS_V1 | PTP_CLASS_IPV6) /*probably DNE*/
+#define PTP_CLASS_V2_IPV4 (PTP_CLASS_V2 | PTP_CLASS_IPV4)
+#define PTP_CLASS_V2_IPV6 (PTP_CLASS_V2 | PTP_CLASS_IPV6)
+#define PTP_CLASS_V2_L2   (PTP_CLASS_V2 | PTP_CLASS_L2)
+#define PTP_CLASS_V2_VLAN (PTP_CLASS_V2 | PTP_CLASS_VLAN)
+
+#define PTP_EV_PORT 319
+
+#define OFF_ETYPE	12
+#define OFF_IHL		14
+#define OFF_FRAG	20
+#define OFF_PROTO4	23
+#define OFF_NEXT	6
+#define OFF_UDP_DST	2
+
+#define IP6_HLEN	40
+#define UDP_HLEN	8
+
+#define RELOFF_DST4	(ETH_HLEN + OFF_UDP_DST)
+#define OFF_DST6	(ETH_HLEN + IP6_HLEN + OFF_UDP_DST)
+#define OFF_PTP6	(ETH_HLEN + IP6_HLEN + UDP_HLEN)
+
+#define OP_AND	(BPF_ALU | BPF_AND  | BPF_K)
+#define OP_JEQ	(BPF_JMP | BPF_JEQ  | BPF_K)
+#define OP_JSET	(BPF_JMP | BPF_JSET | BPF_K)
+#define OP_LDB	(BPF_LD  | BPF_B    | BPF_ABS)
+#define OP_LDH	(BPF_LD  | BPF_H    | BPF_ABS)
+#define OP_LDHI	(BPF_LD  | BPF_H    | BPF_IND)
+#define OP_LDX	(BPF_LDX | BPF_B    | BPF_MSH)
+#define OP_OR	(BPF_ALU | BPF_OR   | BPF_K)
+#define OP_RETA	(BPF_RET | BPF_A)
+#define OP_RETK	(BPF_RET | BPF_K)
+
+#define PTP_FILTER \
+	{OP_LDH,	0,   0, OFF_ETYPE		}, /*              */ \
+	{OP_JEQ,	0,  12, ETH_P_IP		}, /* f goto L20   */ \
+	{OP_LDB,	0,   0, OFF_PROTO4		}, /*              */ \
+	{OP_JEQ,	0,   9, IPPROTO_UDP		}, /* f goto L10   */ \
+	{OP_LDH,	0,   0, OFF_FRAG		}, /*              */ \
+	{OP_JSET,	7,   0, 0x1fff			}, /* t goto L11   */ \
+	{OP_LDX,	0,   0, OFF_IHL			}, /*              */ \
+	{OP_LDHI,	0,   0, RELOFF_DST4		}, /*              */ \
+	{OP_JEQ,	0,   4, PTP_EV_PORT		}, /* f goto L12   */ \
+	{OP_LDHI,	0,   0, ETH_HLEN + UDP_HLEN	}, /*              */ \
+	{OP_AND,	0,   0, PTP_CLASS_VMASK		}, /*              */ \
+	{OP_OR,		0,   0, PTP_CLASS_IPV4		}, /*              */ \
+	{OP_RETA,	0,   0, 0			}, /*              */ \
+/*L1x*/	{OP_RETK,	0,   0, PTP_CLASS_NONE		}, /*              */ \
+/*L20*/	{OP_JEQ,	0,   9, ETH_P_IPV6		}, /* f goto L40   */ \
+	{OP_LDB,	0,   0, ETH_HLEN + OFF_NEXT	}, /*              */ \
+	{OP_JEQ,	0,   6, IPPROTO_UDP		}, /* f goto L30   */ \
+	{OP_LDH,	0,   0, OFF_DST6		}, /*              */ \
+	{OP_JEQ,	0,   4, PTP_EV_PORT		}, /* f goto L31   */ \
+	{OP_LDH,	0,   0, OFF_PTP6		}, /*              */ \
+	{OP_AND,	0,   0, PTP_CLASS_VMASK		}, /*              */ \
+	{OP_OR,		0,   0, PTP_CLASS_IPV6		}, /*              */ \
+	{OP_RETA,	0,   0, 0			}, /*              */ \
+/*L3x*/	{OP_RETK,	0,   0, PTP_CLASS_NONE		}, /*              */ \
+/*L40*/	{OP_JEQ,	0,   6, ETH_P_8021Q		}, /* f goto L50   */ \
+	{OP_LDH,	0,   0, OFF_ETYPE + 4		}, /*              */ \
+	{OP_JEQ,	0,   9, ETH_P_1588		}, /* f goto L60   */ \
+	{OP_LDH,	0,   0, ETH_HLEN + VLAN_HLEN	}, /*              */ \
+	{OP_AND,	0,   0, PTP_CLASS_VMASK		}, /*              */ \
+	{OP_OR,		0,   0, PTP_CLASS_VLAN		}, /*              */ \
+	{OP_RETA,	0,   0, 0			}, /*              */ \
+/*L50*/	{OP_JEQ,	0,   4, ETH_P_1588		}, /* f goto L61   */ \
+	{OP_LDH,	0,   0, ETH_HLEN		}, /*              */ \
+	{OP_AND,	0,   0, PTP_CLASS_VMASK		}, /*              */ \
+	{OP_OR,		0,   0, PTP_CLASS_L2		}, /*              */ \
+	{OP_RETA,	0,   0, 0			}, /*              */ \
+/*L6x*/	{OP_RETK,	0,   0, PTP_CLASS_NONE		},
+
+#endif
-- 
1.6.3.3



From richardcochran at gmail.com  Tue Jun 15 12:09:15 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:09:15 +0200
Subject: [PATCH 07/12] phylib: support the National Semiconductor DP83640 PHY.
In-Reply-To: <cover.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
Message-ID: <d51c259ce9de54e17953d49acb92a39f92ba13a1.1276615626.git.richard.cochran@omicron.at>

This patch adds a driver for the DP83640. This device is one of a new
generation of PHYs able to time stamp PTP packets.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 drivers/net/phy/Kconfig       |    5 +
 drivers/net/phy/Makefile      |    1 +
 drivers/net/phy/dp83640.c     |  439 +++++++++++++++++++++++++++++++++++++++++
 drivers/net/phy/dp83640_reg.h |  237 ++++++++++++++++++++++
 4 files changed, 682 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/phy/dp83640.c
 create mode 100644 drivers/net/phy/dp83640_reg.h

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index a527e37..430cab1 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -77,6 +77,11 @@ config NATIONAL_PHY
 	---help---
 	  Currently supports the DP83865 PHY.
 
+config DP83640_PHY
+	tristate "Driver for the National Semiconductor DP83640 PHYTER"
+	---help---
+	  Supports the DP83640 PHYTER with IEEE 1588 features.
+
 config STE10XP
 	depends on PHYLIB
 	tristate "Driver for STMicroelectronics STe10Xp PHYs"
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 13bebab..2333215 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_FIXED_PHY)		+= fixed.o
 obj-$(CONFIG_MDIO_BITBANG)	+= mdio-bitbang.o
 obj-$(CONFIG_MDIO_GPIO)		+= mdio-gpio.o
 obj-$(CONFIG_NATIONAL_PHY)	+= national.o
+obj-$(CONFIG_DP83640_PHY)	+= dp83640.o
 obj-$(CONFIG_STE10XP)		+= ste10Xp.o
 obj-$(CONFIG_MICREL_PHY)	+= micrel.o
 obj-$(CONFIG_MDIO_OCTEON)	+= mdio-octeon.o
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
new file mode 100644
index 0000000..a3217ea
--- /dev/null
+++ b/drivers/net/phy/dp83640.c
@@ -0,0 +1,439 @@
+/*
+ * Driver for the National Semiconductor DP83640 PHYTER
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/ethtool.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/mii.h>
+#include <linux/module.h>
+#include <linux/net_tstamp.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+#include <linux/ptp_classify.h>
+
+#include "dp83640_reg.h"
+
+#define DP83640_PHY_ID	0x20005ce1
+#define PAGESEL		0x13
+#define LAYER4		0x02
+#define LAYER2		0x01
+#define MAX_RXTS	8
+
+struct rxts {
+	struct list_head list;
+	u64 ns;
+	unsigned long tmo;
+	u16 seqid;
+	u8  msgtype;
+	u16 hash;
+};
+
+struct dp83640_private {
+	int hwts_tx_en;
+	int hwts_rx_en;
+	int layer;
+	int version;
+	/* protects extended registers from concurrent access */
+	spinlock_t extreg_lock;
+	int page;
+	/* list of rx timestamps */
+	struct list_head rxts;
+	struct list_head pool;
+	struct rxts pool_data[MAX_RXTS];
+};
+
+/* globals */
+
+static struct sock_filter ptp_filter[] = {
+	PTP_FILTER
+};
+
+/* extended register access functions */
+
+static int ext_read(struct phy_device *phydev, int page, u32 regnum)
+{
+	struct dp83640_private *dp83640 = phydev->priv;
+	int val;
+
+	spin_lock(&dp83640->extreg_lock);
+
+	if (dp83640->page != page) {
+		phy_write(phydev, PAGESEL, page);
+		dp83640->page = page;
+	}
+	val = phy_read(phydev, regnum);
+
+	spin_unlock(&dp83640->extreg_lock);
+
+	return val;
+}
+
+static void ext_write(struct phy_device *phydev, int page, u32 regnum, u16 val)
+{
+	struct dp83640_private *dp83640 = phydev->priv;
+
+	spin_lock(&dp83640->extreg_lock);
+
+	if (dp83640->page != page) {
+		phy_write(phydev, PAGESEL, page);
+		dp83640->page = page;
+	}
+	phy_write(phydev, regnum, val);
+
+	spin_unlock(&dp83640->extreg_lock);
+}
+
+static int expired(struct rxts *rxts)
+{
+	return time_after(jiffies, rxts->tmo);
+}
+
+static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
+{
+	u16 *seqid;
+	u8 *msgtype, *data = skb->data;
+
+	switch (type) {
+	case PTP_CLASS_V1_IPV4:
+		msgtype = data + 42 + 32;
+		seqid = (u16 *)(data + 42 + 30);
+		break;
+	case PTP_CLASS_V1_IPV6:
+		msgtype = data + 62 + 32;
+		seqid = (u16 *)(data + 62 + 30);
+		break;
+	case PTP_CLASS_V2_IPV4:
+		msgtype = data + 42 + 0;
+		seqid = (u16 *)(data + 42 + 30);
+		break;
+	case PTP_CLASS_V2_IPV6:
+		msgtype = data + 62 + 0;
+		seqid = (u16 *)(data + 62 + 30);
+		break;
+	case PTP_CLASS_V2_L2:
+		msgtype = data + 14 + 0;
+		seqid = (u16 *)(data + 14 + 30);
+		break;
+	case PTP_CLASS_V2_VLAN:
+		msgtype = data + 18 + 0;
+		seqid = (u16 *)(data + 18 + 30);
+		break;
+	default:
+		return 0;
+	}
+
+	return ((*msgtype & 0xf) == rxts->msgtype && *seqid == rxts->seqid);
+}
+
+static int dp83640_probe(struct phy_device *phydev)
+{
+	struct dp83640_private *dp83640;
+	int i;
+
+	if (sk_chk_filter(ptp_filter, ARRAY_SIZE(ptp_filter))) {
+		pr_err("dp83640: bad ptp filter\n");
+		return -EINVAL;
+	}
+
+	dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
+	if (!dp83640)
+		return -ENOMEM;
+
+	spin_lock_init(&dp83640->extreg_lock);
+
+	INIT_LIST_HEAD(&dp83640->rxts);
+	INIT_LIST_HEAD(&dp83640->pool);
+
+	for (i = 0; i < MAX_RXTS; i++)
+		list_add(&dp83640->pool_data[i].list, &dp83640->pool);
+
+	phydev->priv = dp83640;
+
+	return 0;
+}
+
+static void dp83640_remove(struct phy_device *phydev)
+{
+	struct dp83640_private *dp83640 = phydev->priv;
+	kfree(dp83640);
+}
+
+static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
+{
+	struct dp83640_private *dp83640 = phydev->priv;
+	struct hwtstamp_config cfg;
+	u16 txcfg0, rxcfg0;
+
+	if (phydev->bus->locktype != MDIOBUS_ATOMIC_RW)
+		return -EOPNOTSUPP;
+
+	if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
+		return -EFAULT;
+
+	if (cfg.flags) /* reserved for future extensions */
+		return -EINVAL;
+
+	switch (cfg.tx_type) {
+	case HWTSTAMP_TX_OFF:
+		dp83640->hwts_tx_en = 0;
+		break;
+	case HWTSTAMP_TX_ON:
+		dp83640->hwts_tx_en = 1;
+		break;
+	default:
+		return -ERANGE;
+	}
+
+	switch (cfg.rx_filter) {
+	case HWTSTAMP_FILTER_NONE:
+		dp83640->hwts_rx_en = 0;
+		dp83640->layer = 0;
+		dp83640->version = 0;
+		break;
+	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
+	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
+	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
+		dp83640->hwts_rx_en = 1;
+		dp83640->layer = LAYER4;
+		dp83640->version = 1;
+		break;
+	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
+	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
+	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
+		dp83640->hwts_rx_en = 1;
+		dp83640->layer = LAYER4;
+		dp83640->version = 2;
+		break;
+	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
+	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
+	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
+		dp83640->hwts_rx_en = 1;
+		dp83640->layer = LAYER2;
+		dp83640->version = 2;
+		break;
+	case HWTSTAMP_FILTER_PTP_V2_EVENT:
+	case HWTSTAMP_FILTER_PTP_V2_SYNC:
+	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
+		dp83640->hwts_rx_en = 1;
+		dp83640->layer = LAYER4|LAYER2;
+		dp83640->version = 2;
+		break;
+	default:
+		return -ERANGE;
+	}
+
+	txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
+	rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
+
+	if (dp83640->layer & LAYER2) {
+		txcfg0 |= TX_L2_EN;
+		rxcfg0 |= RX_L2_EN;
+	}
+	if (dp83640->layer & LAYER4) {
+		txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
+		rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
+	}
+
+	if (dp83640->hwts_tx_en)
+		txcfg0 |= TX_TS_EN;
+
+	if (dp83640->hwts_rx_en)
+		rxcfg0 |= RX_TS_EN;
+
+	if (dp83640->hwts_tx_en || dp83640->hwts_rx_en)
+		ext_write(phydev, PAGE4, PTP_CTL, PTP_ENABLE);
+
+	ext_write(phydev, PAGE5, PTP_TXCFG0, txcfg0);
+	ext_write(phydev, PAGE5, PTP_RXCFG0, rxcfg0);
+
+	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
+}
+
+static void read_rxts(struct phy_device *phydev, struct rxts *rxts)
+{
+	u64 ns;
+	int overflow, sec, val;
+	u16 hash, seq;
+	u8 msgtype;
+
+	val = ext_read(phydev, PAGE4, PTP_RXTS); /* ns[15:0] */
+	ns = val;
+
+	val = ext_read(phydev, PAGE4, PTP_RXTS); /* overflow[1:0], ns[29:16] */
+	overflow = val >> 14;
+	ns |= (val & 0x3fff) << 16;
+
+	val = ext_read(phydev, PAGE4, PTP_RXTS); /* sec[15:0] */
+	sec = val;
+
+	val = ext_read(phydev, PAGE4, PTP_RXTS); /* sec[31:16] */
+	sec |= val << 16;
+
+	seq = ext_read(phydev, PAGE4, PTP_RXTS); /* sequenceId[15:0] */
+	val = ext_read(phydev, PAGE4, PTP_RXTS); /* messageType[3:0], hash[11:0] */
+	msgtype = (val >> 12) & 0xf;
+	hash = val & 0x0fff;
+	ns += ((u64)sec) * 1000000000ULL;
+
+	rxts->ns = ns;
+	rxts->tmo = jiffies + HZ;
+	rxts->seqid = seq;
+	rxts->msgtype = msgtype;
+	rxts->hash = hash;
+}
+
+static int dp83640_rxtstamp(struct phy_device *phydev, struct sk_buff *skb)
+{
+	struct dp83640_private *dp83640 = phydev->priv;
+	struct skb_shared_hwtstamps *shhwtstamps;
+	struct list_head *this, *next;
+	struct rxts *rxts;
+	unsigned int type;
+	int val;
+
+	if (!dp83640->hwts_rx_en)
+		return -1;
+
+	for (;;) {
+		val = ext_read(phydev, PAGE4, PTP_STS);
+		if (!(val & RXTS_RDY))
+			break;
+
+		if (list_empty(&dp83640->pool)) {
+			pr_warning("dp83640: rx timestamp pool is empty\n");
+			break;
+		}
+
+		rxts = list_first_entry(&dp83640->pool, struct rxts, list);
+		list_del_init(&rxts->list);
+		read_rxts(phydev, rxts);
+		list_add_tail(&rxts->list, &dp83640->rxts);
+	}
+
+	type = sk_run_filter(skb, ptp_filter, ARRAY_SIZE(ptp_filter));
+
+	list_for_each_safe(this, next, &dp83640->rxts) {
+
+		rxts = list_entry(this, struct rxts, list);
+
+		/* check sequenceID, messageType, 12 bit hash of offset 20-29 */
+
+		if (match(skb, type, rxts)) {
+			shhwtstamps = skb_hwtstamps(skb);
+			memset(shhwtstamps, 0, sizeof(*shhwtstamps));
+			shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
+			list_del_init(&rxts->list);
+			list_add(&rxts->list, &dp83640->pool);
+			return 0;
+		}
+		if (expired(rxts)) {
+			list_del_init(&rxts->list);
+			list_add(&rxts->list, &dp83640->pool);
+		}
+	}
+
+	return -1;
+}
+
+static int dp83640_txtstamp(struct phy_device *phydev, struct sk_buff *skb)
+{
+	struct dp83640_private *dp83640 = phydev->priv;
+	struct skb_shared_hwtstamps shhwtstamps;
+	union skb_shared_tx *shtx;
+	u64 ns;
+	int cnt, overflow, sec, val;
+
+	if (!dp83640->hwts_tx_en)
+		return -1;
+
+	/*
+	 * This really stinks, but we have to poll for the Tx time stamp.
+	 */
+	for (cnt = 0; cnt < 100; cnt++) {
+		val = ext_read(phydev, PAGE4, PTP_STS);
+		if (val & TXTS_RDY)
+			break;
+		udelay(1);
+	}
+	if (!(val & TXTS_RDY))
+		return -1;
+
+	val = ext_read(phydev, PAGE4, PTP_TXTS); /* ns[15:0] */
+	ns = val;
+
+	val = ext_read(phydev, PAGE4, PTP_TXTS); /* overflow[1:0], ns[29:16] */
+	overflow = val >> 14;
+	ns |= (val & 0x3fff) << 16;
+
+	val = ext_read(phydev, PAGE4, PTP_TXTS); /* sec[15:0] */
+	sec = val;
+
+	val = ext_read(phydev, PAGE4, PTP_TXTS); /* sec[31:16] */
+	sec |= val << 16;
+
+	ns += ((u64)sec) * 1000000000ULL;
+
+	shtx = skb_tx(skb);
+	shtx->in_progress = 1;
+	memset(&shhwtstamps, 0, sizeof(shhwtstamps));
+	shhwtstamps.hwtstamp = ns_to_ktime(ns);
+	skb_tstamp_tx(skb, &shhwtstamps);
+
+	return 0;
+}
+
+static struct phy_driver dp83640_driver = {
+	.phy_id		= DP83640_PHY_ID,
+	.phy_id_mask	= 0xfffffff0,
+	.name		= "NatSemi DP83640",
+	.features	= PHY_BASIC_FEATURES,
+	.flags		= 0,
+	.probe		= dp83640_probe,
+	.remove		= dp83640_remove,
+	.config_aneg	= genphy_config_aneg,
+	.read_status	= genphy_read_status,
+	.hwtstamp	= dp83640_hwtstamp,
+	.rxtstamp	= dp83640_rxtstamp,
+	.txtstamp	= dp83640_txtstamp,
+	.driver		= {.owner = THIS_MODULE,}
+};
+
+static int __init dp83640_init(void)
+{
+	return phy_driver_register(&dp83640_driver);
+}
+
+static void __exit dp83640_exit(void)
+{
+	phy_driver_unregister(&dp83640_driver);
+}
+
+MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
+MODULE_AUTHOR("Richard Cochran <richard.cochran at omicron.at>");
+MODULE_LICENSE("GPL");
+
+module_init(dp83640_init);
+module_exit(dp83640_exit);
+
+static struct mdio_device_id dp83640_tbl[] = {
+	{ DP83640_PHY_ID, 0xfffffff0 },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
diff --git a/drivers/net/phy/dp83640_reg.h b/drivers/net/phy/dp83640_reg.h
new file mode 100644
index 0000000..349fdbc
--- /dev/null
+++ b/drivers/net/phy/dp83640_reg.h
@@ -0,0 +1,237 @@
+/* dp83640_reg.h
+ * Generated by regen.tcl on Wed Jun 02 07:11:36 AM CEST 2010
+ */
+#ifndef HAVE_DP83640_REGISTERS
+#define HAVE_DP83640_REGISTERS
+
+#define PAGE4                     0x0004
+#define PTP_CTL                   0x0014 /* PTP Control Register */
+#define PTP_TDR                   0x0015 /* PTP Time Data Register */
+#define PTP_STS                   0x0016 /* PTP Status Register */
+#define PTP_TSTS                  0x0017 /* PTP Trigger Status Register */
+#define PTP_RATEL                 0x0018 /* PTP Rate Low Register */
+#define PTP_RATEH                 0x0019 /* PTP Rate High Register */
+#define PTP_RDCKSUM               0x001a /* PTP Read Checksum */
+#define PTP_WRCKSUM               0x001b /* PTP Write Checksum */
+#define PTP_TXTS                  0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
+#define PTP_RXTS                  0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
+#define PTP_ESTS                  0x001e /* PTP Event Status Register */
+#define PTP_EDATA                 0x001f /* PTP Event Data Register */
+
+#define PAGE5                     0x0005
+#define PTP_TRIG                  0x0014 /* PTP Trigger Configuration Register */
+#define PTP_EVNT                  0x0015 /* PTP Event Configuration Register */
+#define PTP_TXCFG0                0x0016 /* PTP Transmit Configuration Register 0 */
+#define PTP_TXCFG1                0x0017 /* PTP Transmit Configuration Register 1 */
+#define PSF_CFG0                  0x0018 /* PHY Status Frame Configuration Register 0 */
+#define PTP_RXCFG0                0x0019 /* PTP Receive Configuration Register 0 */
+#define PTP_RXCFG1                0x001a /* PTP Receive Configuration Register 1 */
+#define PTP_RXCFG2                0x001b /* PTP Receive Configuration Register 2 */
+#define PTP_RXCFG3                0x001c /* PTP Receive Configuration Register 3 */
+#define PTP_RXCFG4                0x001d /* PTP Receive Configuration Register 4 */
+#define PTP_TRDL                  0x001e /* PTP Temporary Rate Duration Low Register */
+#define PTP_TRDH                  0x001f /* PTP Temporary Rate Duration High Register */
+
+#define PAGE6                     0x0006
+#define PTP_COC                   0x0014 /* PTP Clock Output Control Register */
+#define PSF_CFG1                  0x0015 /* PHY Status Frame Configuration Register 1 */
+#define PSF_CFG2                  0x0016 /* PHY Status Frame Configuration Register 2 */
+#define PSF_CFG3                  0x0017 /* PHY Status Frame Configuration Register 3 */
+#define PSF_CFG4                  0x0018 /* PHY Status Frame Configuration Register 4 */
+#define PTP_SFDCFG                0x0019 /* PTP SFD Configuration Register */
+#define PTP_INTCTL                0x001a /* PTP Interrupt Control Register */
+#define PTP_CLKSRC                0x001b /* PTP Clock Source Register */
+#define PTP_ETR                   0x001c /* PTP Ethernet Type Register */
+#define PTP_OFF                   0x001d /* PTP Offset Register */
+#define PTP_GPIOMON               0x001e /* PTP GPIO Monitor Register */
+#define PTP_RXHASH                0x001f /* PTP Receive Hash Register */
+
+/* Bit definitions for the PTP_CTL register */
+#define TRIG_SEL_SHIFT            (10) /* PTP Trigger Select */
+#define TRIG_SEL_MASK             (0x7)
+#define TRIG_DIS                  (1<<9) /* Disable PTP Trigger */
+#define TRIG_EN                   (1<<8) /* Enable PTP Trigger */
+#define TRIG_READ                 (1<<7) /* Read PTP Trigger */
+#define TRIG_LOAD                 (1<<6) /* Load PTP Trigger */
+#define PTP_RD_CLK                (1<<5) /* Read PTP Clock */
+#define PTP_LOAD_CLK              (1<<4) /* Load PTP Clock */
+#define PTP_STEP_CLK              (1<<3) /* Step PTP Clock */
+#define PTP_ENABLE                (1<<2) /* Enable PTP Clock */
+#define PTP_DISABLE               (1<<1) /* Disable PTP Clock */
+#define PTP_RESET                 (1<<0) /* Reset PTP Clock */
+
+/* Bit definitions for the PTP_STS register */
+#define TXTS_RDY                  (1<<11) /* Transmit Timestamp Ready */
+#define RXTS_RDY                  (1<<10) /* Receive Timestamp Ready */
+#define TRIG_DONE                 (1<<9) /* PTP Trigger Done */
+#define EVENT_RDY                 (1<<8) /* PTP Event Timestamp Ready */
+#define TXTS_IE                   (1<<3) /* Transmit Timestamp Interrupt Enable */
+#define RXTS_IE                   (1<<2) /* Receive Timestamp Interrupt Enable */
+#define TRIG_IE                   (1<<1) /* Trigger Interrupt Enable */
+#define EVENT_IE                  (1<<0) /* Event Interrupt Enable */
+
+/* Bit definitions for the PTP_TSTS register */
+#define TRIG7_ERROR               (1<<15) /* Trigger 7 Error */
+#define TRIG7_ACTIVE              (1<<14) /* Trigger 7 Active */
+#define TRIG6_ERROR               (1<<13) /* Trigger 6 Error */
+#define TRIG6_ACTIVE              (1<<12) /* Trigger 6 Active */
+#define TRIG5_ERROR               (1<<11) /* Trigger 5 Error */
+#define TRIG5_ACTIVE              (1<<10) /* Trigger 5 Active */
+#define TRIG4_ERROR               (1<<9) /* Trigger 4 Error */
+#define TRIG4_ACTIVE              (1<<8) /* Trigger 4 Active */
+#define TRIG3_ERROR               (1<<7) /* Trigger 3 Error */
+#define TRIG3_ACTIVE              (1<<6) /* Trigger 3 Active */
+#define TRIG2_ERROR               (1<<5) /* Trigger 2 Error */
+#define TRIG2_ACTIVE              (1<<4) /* Trigger 2 Active */
+#define TRIG1_ERROR               (1<<3) /* Trigger 1 Error */
+#define TRIG1_ACTIVE              (1<<2) /* Trigger 1 Active */
+#define TRIG0_ERROR               (1<<1) /* Trigger 0 Error */
+#define TRIG0_ACTIVE              (1<<0) /* Trigger 0 Active */
+
+/* Bit definitions for the PTP_RATEH register */
+#define PTP_RATE_DIR              (1<<15) /* PTP Rate Direction */
+#define PTP_TMP_RATE              (1<<14) /* PTP Temporary Rate */
+#define PTP_RATE_HI_SHIFT         (0) /* PTP Rate High 10-bits */
+#define PTP_RATE_HI_MASK          (0x3ff)
+
+/* Bit definitions for the PTP_ESTS register */
+#define EVNTS_MISSED_SHIFT        (8) /* Indicates number of events missed */
+#define EVNTS_MISSED_MASK         (0x7)
+#define EVNT_TS_LEN_SHIFT         (6) /* Indicates length of the Timestamp field in 16-bit words minus 1 */
+#define EVNT_TS_LEN_MASK          (0x3)
+#define EVNT_RF                   (1<<5) /* Indicates whether the event is a rise or falling event */
+#define EVNT_NUM_SHIFT            (2) /* Indicates Event Timestamp Unit which detected an event */
+#define EVNT_NUM_MASK             (0x7)
+#define MULT_EVNT                 (1<<1) /* Indicates multiple events were detected at the same time */
+#define EVENT_DET                 (1<<0) /* PTP Event Detected */
+
+/* Bit definitions for the PTP_EDATA register */
+#define E7_RISE                   (1<<15) /* Indicates direction of Event 7 */
+#define E7_DET                    (1<<14) /* Indicates Event 7 detected */
+#define E6_RISE                   (1<<13) /* Indicates direction of Event 6 */
+#define E6_DET                    (1<<12) /* Indicates Event 6 detected */
+#define E5_RISE                   (1<<11) /* Indicates direction of Event 5 */
+#define E5_DET                    (1<<10) /* Indicates Event 5 detected */
+#define E4_RISE                   (1<<9) /* Indicates direction of Event 4 */
+#define E4_DET                    (1<<8) /* Indicates Event 4 detected */
+#define E3_RISE                   (1<<7) /* Indicates direction of Event 3 */
+#define E3_DET                    (1<<6) /* Indicates Event 3 detected */
+#define E2_RISE                   (1<<5) /* Indicates direction of Event 2 */
+#define E2_DET                    (1<<4) /* Indicates Event 2 detected */
+#define E1_RISE                   (1<<3) /* Indicates direction of Event 1 */
+#define E1_DET                    (1<<2) /* Indicates Event 1 detected */
+#define E0_RISE                   (1<<1) /* Indicates direction of Event 0 */
+#define E0_DET                    (1<<0) /* Indicates Event 0 detected */
+
+/* Bit definitions for the PTP_TRIG register */
+#define TRIG_PULSE                (1<<15) /* generate a Pulse rather than a single edge */
+#define TRIG_PER                  (1<<14) /* generate a periodic signal */
+#define TRIG_IF_LATE              (1<<13) /* trigger immediately if already past */
+#define TRIG_NOTIFY               (1<<12) /* Trigger Notification Enable */
+#define TRIG_GPIO_SHIFT           (8) /* Trigger GPIO Connection, value 1-12 */
+#define TRIG_GPIO_MASK            (0xf)
+#define TRIG_TOGGLE               (1<<7) /* Trigger Toggle Mode Enable */
+#define TRIG_CSEL_SHIFT           (1) /* Trigger Configuration Select */
+#define TRIG_CSEL_MASK            (0x7)
+#define TRIG_WR                   (1<<0) /* Trigger Configuration Write */
+
+/* Bit definitions for the PTP_EVNT register */
+#define EVNT_RISE                 (1<<14) /* Event Rise Detect Enable */
+#define EVNT_FALL                 (1<<13) /* Event Fall Detect Enable */
+#define EVNT_SINGLE               (1<<12) /* enable single event capture operation */
+#define EVNT_GPIO_SHIFT           (8) /* Event GPIO Connection, value 1-12 */
+#define EVNT_GPIO_MASK            (0xf)
+#define EVNT_SEL_SHIFT            (1) /* Event Select */
+#define EVNT_SEL_MASK             (0x7)
+#define EVNT_WR                   (1<<0) /* Event Configuration Write */
+
+/* Bit definitions for the PTP_TXCFG0 register */
+#define SYNC_1STEP                (1<<15) /* insert timestamp into transmit Sync Messages */
+#define DR_INSERT                 (1<<13) /* Insert Delay_Req Timestamp in Delay_Resp (dangerous) */
+#define NTP_TS_EN                 (1<<12) /* Enable Timestamping of NTP Packets */
+#define IGNORE_2STEP              (1<<11) /* Ignore Two_Step flag for One-Step operation */
+#define CRC_1STEP                 (1<<10) /* Disable checking of CRC for One-Step operation */
+#define CHK_1STEP                 (1<<9) /* Enable UDP Checksum correction for One-Step Operation */
+#define IP1588_EN                 (1<<8) /* Enable IEEE 1588 defined IP address filter */
+#define TX_L2_EN                  (1<<7) /* Layer2 Timestamp Enable */
+#define TX_IPV6_EN                (1<<6) /* IPv6 Timestamp Enable */
+#define TX_IPV4_EN                (1<<5) /* IPv4 Timestamp Enable */
+#define TX_PTP_VER_SHIFT          (1) /* Enable Timestamp capture for IEEE 1588 version X */
+#define TX_PTP_VER_MASK           (0xf)
+#define TX_TS_EN                  (1<<0) /* Transmit Timestamp Enable */
+
+/* Bit definitions for the PTP_TXCFG1 register */
+#define BYTE0_MASK_SHIFT          (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
+#define BYTE0_MASK_MASK           (0xff)
+#define BYTE0_DATA_SHIFT          (0) /* Data to be used for matching Byte0 of the PTP Message */
+#define BYTE0_DATA_MASK           (0xff)
+
+/* Bit definitions for the PTP_RXCFG0 register */
+#define DOMAIN_EN                 (1<<15) /* Domain Match Enable */
+#define ALT_MAST_DIS              (1<<14) /* Alternate Master Timestamp Disable */
+#define USER_IP_SEL               (1<<13) /* Selects portion of IP address accessible thru PTP_RXCFG2 */
+#define USER_IP_EN                (1<<12) /* Enable User-programmed IP address filter */
+#define RX_SLAVE                  (1<<11) /* Receive Slave Only */
+#define IP1588_EN_SHIFT           (8) /* Enable IEEE 1588 defined IP address filters */
+#define IP1588_EN_MASK            (0xf)
+#define RX_L2_EN                  (1<<7) /* Layer2 Timestamp Enable */
+#define RX_IPV6_EN                (1<<6) /* IPv6 Timestamp Enable */
+#define RX_IPV4_EN                (1<<5) /* IPv4 Timestamp Enable */
+#define RX_PTP_VER_SHIFT          (1) /* Enable Timestamp capture for IEEE 1588 version X */
+#define RX_PTP_VER_MASK           (0xf)
+#define RX_TS_EN                  (1<<0) /* Receive Timestamp Enable */
+
+/* Bit definitions for the PTP_RXCFG1 register */
+#define BYTE0_MASK_SHIFT          (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
+#define BYTE0_MASK_MASK           (0xff)
+#define BYTE0_DATA_SHIFT          (0) /* Data to be used for matching Byte0 of the PTP Message */
+#define BYTE0_DATA_MASK           (0xff)
+
+/* Bit definitions for the PTP_RXCFG3 register */
+#define TS_MIN_IFG_SHIFT          (12) /* Minimum Inter-frame Gap */
+#define TS_MIN_IFG_MASK           (0xf)
+#define ACC_UDP                   (1<<11) /* Record Timestamp if UDP Checksum Error */
+#define ACC_CRC                   (1<<10) /* Record Timestamp if CRC Error */
+#define TS_APPEND                 (1<<9) /* Append Timestamp for L2 */
+#define TS_INSERT                 (1<<8) /* Enable Timestamp Insertion */
+#define PTP_DOMAIN_SHIFT          (0) /* PTP Message domainNumber field */
+#define PTP_DOMAIN_MASK           (0xff)
+
+/* Bit definitions for the PTP_RXCFG4 register */
+#define IPV4_UDP_MOD              (1<<15) /* Enable IPV4 UDP Modification */
+#define TS_SEC_EN                 (1<<14) /* Enable Timestamp Seconds */
+#define TS_SEC_LEN_SHIFT          (12) /* Inserted Timestamp Seconds Length */
+#define TS_SEC_LEN_MASK           (0x3)
+#define RXTS_NS_OFF_SHIFT         (6) /* Receive Timestamp Nanoseconds offset */
+#define RXTS_NS_OFF_MASK          (0x3f)
+#define RXTS_SEC_OFF_SHIFT        (0) /* Receive Timestamp Seconds offset */
+#define RXTS_SEC_OFF_MASK         (0x3f)
+
+/* Bit definitions for the PTP_COC register */
+#define PTP_CLKOUT_EN             (1<<15) /* PTP Clock Output Enable */
+#define PTP_CLKOUT_SEL            (1<<14) /* PTP Clock Output Source Select */
+#define PTP_CLKOUT_SPEEDSEL       (1<<13) /* PTP Clock Output I/O Speed Select */
+#define PTP_CLKDIV_SHIFT          (0) /* PTP Clock Divide-by Value */
+#define PTP_CLKDIV_MASK           (0xff)
+
+/* Bit definitions for the PTP_SFDCFG register */
+#define TX_SFD_GPIO_SHIFT         (4) /* TX SFD GPIO Select, value 1-12 */
+#define TX_SFD_GPIO_MASK          (0xf)
+#define RX_SFD_GPIO_SHIFT         (0) /* RX SFD GPIO Select, value 1-12 */
+#define RX_SFD_GPIO_MASK          (0xf)
+
+/* Bit definitions for the PTP_INTCTL register */
+#define PTP_INT_GPIO_SHIFT        (0) /* PTP Interrupt GPIO Select */
+#define PTP_INT_GPIO_MASK         (0xf)
+
+/* Bit definitions for the PTP_CLKSRC register */
+#define CLK_SRC_SHIFT             (14) /* PTP Clock Source Select */
+#define CLK_SRC_MASK              (0x3)
+#define CLK_SRC_PER_SHIFT         (0) /* PTP Clock Source Period */
+#define CLK_SRC_PER_MASK          (0x7f)
+
+/* Bit definitions for the PTP_OFF register */
+#define PTP_OFFSET_SHIFT          (0) /* PTP Message offset from preceding header */
+#define PTP_OFFSET_MASK           (0xff)
+
+#endif
-- 
1.6.3.3



From richardcochran at gmail.com  Tue Jun 15 12:09:32 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:09:32 +0200
Subject: [PATCH 08/12] ptp: Added a brand new class driver for ptp clocks.
In-Reply-To: <cover.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
Message-ID: <4a030d2bace90f089f2f3f61496b918c6f1dfb52.1276615626.git.richard.cochran@omicron.at>

This patch adds an infrastructure for hardware clocks that implement
IEEE 1588, the Precision Time Protocol (PTP). A class driver offers a
registration method to particular hardware clock drivers. Each clock is
exposed to user space as a character device with ioctls that allow tuning
of the PTP clock.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 Documentation/ptp/ptp.txt        |   95 +++++++
 Documentation/ptp/testptp.c      |  269 ++++++++++++++++++++
 Documentation/ptp/testptp.mk     |   33 +++
 drivers/Kconfig                  |    2 +
 drivers/Makefile                 |    1 +
 drivers/ptp/Kconfig              |   26 ++
 drivers/ptp/Makefile             |    5 +
 drivers/ptp/ptp_clock.c          |  514 ++++++++++++++++++++++++++++++++++++++
 include/linux/Kbuild             |    1 +
 include/linux/ptp_clock.h        |   79 ++++++
 include/linux/ptp_clock_kernel.h |  137 ++++++++++
 11 files changed, 1162 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/ptp/ptp.txt
 create mode 100644 Documentation/ptp/testptp.c
 create mode 100644 Documentation/ptp/testptp.mk
 create mode 100644 drivers/ptp/Kconfig
 create mode 100644 drivers/ptp/Makefile
 create mode 100644 drivers/ptp/ptp_clock.c
 create mode 100644 include/linux/ptp_clock.h
 create mode 100644 include/linux/ptp_clock_kernel.h

diff --git a/Documentation/ptp/ptp.txt b/Documentation/ptp/ptp.txt
new file mode 100644
index 0000000..46858b3
--- /dev/null
+++ b/Documentation/ptp/ptp.txt
@@ -0,0 +1,95 @@
+
+* PTP infrastructure for Linux
+
+  This patch set introduces support for IEEE 1588 PTP clocks in
+  Linux. Together with the SO_TIMESTAMPING socket options, this
+  presents a standardized method for developing PTP user space
+  programs, synchronizing Linux with external clocks, and using the
+  ancillary features of PTP hardware clocks.
+
+  A new class driver exports a kernel interface for specific clock
+  drivers and a user space interface. The infrastructure supports a
+  complete set of PTP functionality.
+
+  + Basic clock operations
+    - Set time
+    - Get time
+    - Shift the clock by a given offset atomically
+    - Adjust clock frequency
+
+  + Ancillary clock features
+    - One short or periodic alarms, with signal delivery to user program
+    - Time stamp external events
+    - Period output signals configurable from user space
+    - Synchronization of the Linux system time via the PPS subsystem
+
+** PTP kernel API
+
+   A PTP clock driver registers itself with the class driver. The
+   class driver handles all of the dealings with user space. The
+   author of a clock driver need only implement the details of
+   programming the clock hardware. The clock driver notifies the class
+   driver of asynchronous events (alarms and external time stamps) via
+   a simple message passing interface.
+
+   The class driver supports multiple PTP clock drivers. In normal use
+   cases, only one PTP clock is needed. However, for testing and
+   development, it can be useful to have more than one clock in a
+   single system, in order to allow performance comparisons.
+
+** PTP user space API
+
+   The class driver creates a character device for each registered PTP
+   clock. User space programs may control the clock using standardized
+   ioctls. A program may query, enable, configure, and disable the
+   ancillary clock features. User space can receive time stamped
+   events via blocking read() and poll(). One shot and periodic
+   signals may be configured via an ioctl API with semantics similar
+   to the POSIX timer_settime() system call.
+
+   As an real life example, the following two patches for ptpd version
+   1.0.0 demonstrate how the API works.
+
+   https://sourceforge.net/tracker/?func=detail&aid=2992845&group_id=139814&atid=744634
+
+   https://sourceforge.net/tracker/?func=detail&aid=2992847&group_id=139814&atid=744634
+
+** Writing clock drivers
+
+   Clock drivers include include/linux/ptp_clock_kernel.h and register
+   themselves by presenting a 'struct ptp_clock_info' to the
+   registration method. Clock drivers must implement all of the
+   functions in the interface. If a clock does not offer a particular
+   ancillary feature, then the driver should just return -EOPNOTSUPP
+   from those functions.
+
+   Drivers must ensure that all of the methods in interface are
+   reentrant. Since most hardware implementations treat the time value
+   as a 64 bit integer accessed as two 32 bit registers, drivers
+   should use spin_lock_irqsave/spin_unlock_irqrestore to protect
+   against concurrent access. This locking cannot be accomplished in
+   class driver, since the lock may also be needed by the clock
+   driver's interrupt service routine.
+
+** Supported hardware
+
+   + Standard Linux system timer
+     - No special PTP features
+     - For use with software time stamping
+
+   + Freescale eTSEC gianfar
+     - 2 Time stamp external triggers, programmable polarity (opt. interrupt)
+     - 2 Alarm registers (optional interrupt)
+     - 3 Periodic signals (optional interrupt)
+
+   + National DP83640
+     - 6 GPIOs programmable as inputs or outputs
+     - 6 GPIOs with dedicated functions (LED/JTAG/clock) can also be
+       used as general inputs or outputs
+     - GPIO inputs can time stamp external triggers
+     - GPIO outputs can produce periodic signals
+     - 1 interrupt pin
+
+   + Intel IXP465
+     - Auxiliary Slave/Master Mode Snapshot (optional interrupt)
+     - Target Time (optional interrupt)
diff --git a/Documentation/ptp/testptp.c b/Documentation/ptp/testptp.c
new file mode 100644
index 0000000..e30f758
--- /dev/null
+++ b/Documentation/ptp/testptp.c
@@ -0,0 +1,269 @@
+/*
+ * PTP 1588 clock support - User space test program
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <errno.h>
+#include <fcntl.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <time.h>
+#include <unistd.h>
+
+#include <linux/ptp_clock.h>
+
+static void handle_alarm(int s)
+{
+	printf("received signal %d\n", s);
+}
+
+static int install_handler(int signum, void (*handler)(int))
+{
+	struct sigaction action;
+	sigset_t mask;
+
+	/* Unblock the signal. */
+	sigemptyset(&mask);
+	sigaddset(&mask, signum);
+	sigprocmask(SIG_UNBLOCK, &mask, NULL);
+
+	/* Install the signal handler. */
+	action.sa_handler = handler;
+	action.sa_flags = 0;
+	sigemptyset(&action.sa_mask);
+	sigaction(signum, &action, NULL);
+
+	return 0;
+}
+
+static void usage(char *progname)
+{
+	fprintf(stderr,
+		"usage: %s [options]\n"
+		" -a val     request a one-shot alarm after 'val' seconds\n"
+		" -A val     request a periodic alarm every 'val' seconds\n"
+		" -c         query the ptp clock's capabilities\n"
+		" -d name    device to open\n"
+		" -e val     read 'val' external time stamp events\n"
+		" -f val     adjust the ptp clock frequency by 'val' PPB\n"
+		" -g         get the ptp clock time\n"
+		" -h         prints this message\n"
+		" -s         set the ptp clock time from the system time\n"
+		" -t val     shift the ptp clock time by 'val' seconds\n"
+		" -v         query the ptp clock api version\n",
+		progname);
+}
+
+int main(int argc, char *argv[])
+{
+	struct ptp_clock_caps caps;
+	struct ptp_clock_timer timer;
+	struct ptp_extts_event event;
+	struct ptp_clock_request request;
+	struct timespec ts;
+	char *progname;
+	int c, cnt, fd, val = 0;
+
+	char *device = "/dev/ptp_clock_0";
+	int adjfreq = 0x7fffffff;
+	int adjtime = 0;
+	int capabilities = 0;
+	int extts = 0;
+	int gettime = 0;
+	int oneshot = 0;
+	int periodic = 0;
+	int settime = 0;
+	int version = 0;
+
+	progname = strrchr(argv[0], '/');
+	progname = progname ? 1+progname : argv[0];
+	while (EOF != (c = getopt(argc, argv, "a:A:cd:e:f:ghst:v"))) {
+		switch (c) {
+		case 'a':
+			oneshot = atoi(optarg);
+			break;
+		case 'A':
+			periodic = atoi(optarg);
+			break;
+		case 'c':
+			capabilities = 1;
+			break;
+		case 'd':
+			device = optarg;
+			break;
+		case 'e':
+			extts = atoi(optarg);
+			break;
+		case 'f':
+			adjfreq = atoi(optarg);
+			break;
+		case 'g':
+			gettime = 1;
+			break;
+		case 's':
+			settime = 1;
+			break;
+		case 't':
+			adjtime = atoi(optarg);
+			break;
+		case 'v':
+			version = 1;
+			break;
+		case 'h':
+			usage(progname);
+			return 0;
+		case '?':
+		default:
+			usage(progname);
+			return -1;
+		}
+	}
+
+	fd = open(device, O_RDWR);
+	if (fd < 0) {
+		fprintf(stderr, "cannot open %s: %s", device, strerror(errno));
+		return -1;
+	}
+
+	if (version) {
+		if (ioctl(fd, PTP_CLOCK_APIVERS, &val)) {
+			perror("PTP_CLOCK_APIVERS");
+		} else {
+			printf("version = 0x%08x\n", val);
+		}
+	}
+
+	if (capabilities) {
+		if (ioctl(fd, PTP_CLOCK_GETCAPS, &caps)) {
+			perror("PTP_CLOCK_GETCAPS");
+		} else {
+			printf("capabilities:\n"
+			       "  %d maximum frequency adjustment (PPB)\n"
+			       "  %d programmable alarms\n"
+			       "  %d external time stamp channels\n"
+			       "  %d programmable periodic signals\n"
+			       "  %d pulse per second\n",
+			       caps.max_adj,
+			       caps.n_alarm,
+			       caps.n_ext_ts,
+			       caps.n_per_out,
+			       caps.pps);
+		}
+	}
+
+	if (0x7fffffff != adjfreq) {
+		if (ioctl(fd, PTP_CLOCK_ADJFREQ, adjfreq)) {
+			perror("PTP_CLOCK_ADJFREQ");
+		} else {
+			puts("frequency adjustment okay");
+		}
+	}
+
+	if (adjtime) {
+		ts.tv_sec = adjtime;
+		ts.tv_nsec = 0;
+		if (ioctl(fd, PTP_CLOCK_ADJTIME, &ts)) {
+			perror("PTP_CLOCK_ADJTIME");
+		} else {
+			puts("time shift okay");
+		}
+	}
+
+	if (gettime) {
+		if (ioctl(fd, PTP_CLOCK_GETTIME, &ts)) {
+			perror("PTP_CLOCK_GETTIME");
+		} else {
+			printf("clock time: %ld.%09ld or %s",
+			       ts.tv_sec, ts.tv_nsec, ctime(&ts.tv_sec));
+		}
+	}
+
+	if (settime) {
+		clock_gettime(CLOCK_REALTIME, &ts);
+		if (ioctl(fd, PTP_CLOCK_SETTIME, &ts)) {
+			perror("PTP_CLOCK_SETTIME");
+		} else {
+			puts("set time okay");
+		}
+	}
+
+	if (extts) {
+		memset(&request, 0, sizeof(request));
+		request.type = PTP_REQUEST_EXTTS;
+		request.index = 0;
+		request.flags = PTP_ENABLE_FEATURE;
+		if (ioctl(fd, PTP_FEATURE_REQUEST, &request)) {
+			perror("PTP_FEATURE_REQUEST");
+			extts = 0;
+		} else {
+			puts("set timer okay");
+		}
+		for (; extts; extts--) {
+			cnt = read(fd, &event, sizeof(event));
+			if (cnt != sizeof(event)) {
+				perror("read");
+				break;
+			}
+			printf("event index %d at %ld.%09ld\n", event.index,
+			       event.ts.tv_sec, event.ts.tv_nsec);
+		}
+		/* Disable the feature again. */
+		request.flags = 0;
+		if (ioctl(fd, PTP_FEATURE_REQUEST, &request)) {
+			perror("PTP_FEATURE_REQUEST");
+		}
+	}
+
+	if (oneshot) {
+		install_handler(SIGALRM, handle_alarm);
+		memset(&timer, 0, sizeof(timer));
+		timer.signum = SIGALRM;
+		timer.tsp.it_value.tv_sec = oneshot;
+		if (ioctl(fd, PTP_CLOCK_SETTIMER, &timer)) {
+			perror("PTP_CLOCK_SETTIMER");
+		} else {
+			puts("set timer okay");
+		}
+		pause();
+	}
+
+	if (periodic) {
+		install_handler(SIGALRM, handle_alarm);
+		memset(&timer, 0, sizeof(timer));
+		timer.signum = SIGALRM;
+		timer.tsp.it_value.tv_sec = periodic;
+		timer.tsp.it_interval.tv_sec = periodic;
+		if (ioctl(fd, PTP_CLOCK_SETTIMER, &timer)) {
+			perror("PTP_CLOCK_SETTIMER");
+		} else {
+			puts("set timer okay");
+		}
+		while (1) {
+			pause();
+		}
+	}
+
+	close(fd);
+	return 0;
+}
diff --git a/Documentation/ptp/testptp.mk b/Documentation/ptp/testptp.mk
new file mode 100644
index 0000000..4ef2d97
--- /dev/null
+++ b/Documentation/ptp/testptp.mk
@@ -0,0 +1,33 @@
+# PTP 1588 clock support - User space test program
+#
+# Copyright (C) 2010 OMICRON electronics GmbH
+#
+#  This program is free software; you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation; either version 2 of the License, or
+#  (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program; if not, write to the Free Software
+#  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+CC        = $(CROSS_COMPILE)gcc
+INC       = -I$(KBUILD_OUTPUT)/usr/include
+CFLAGS    = -Wall $(INC)
+LDLIBS    = -lrt
+PROGS     = testptp
+
+all: $(PROGS)
+
+testptp: testptp.o
+
+clean:
+	rm -f testptp.o
+
+distclean: clean
+	rm -f $(PROGS)
diff --git a/drivers/Kconfig b/drivers/Kconfig
index a2b902f..774fbd7 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -52,6 +52,8 @@ source "drivers/spi/Kconfig"
 
 source "drivers/pps/Kconfig"
 
+source "drivers/ptp/Kconfig"
+
 source "drivers/gpio/Kconfig"
 
 source "drivers/w1/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 91874e0..6d12b48 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -76,6 +76,7 @@ obj-$(CONFIG_I2O)		+= message/
 obj-$(CONFIG_RTC_LIB)		+= rtc/
 obj-y				+= i2c/ media/
 obj-$(CONFIG_PPS)		+= pps/
+obj-$(CONFIG_PTP_1588_CLOCK)	+= ptp/
 obj-$(CONFIG_W1)		+= w1/
 obj-$(CONFIG_POWER_SUPPLY)	+= power/
 obj-$(CONFIG_HWMON)		+= hwmon/
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
new file mode 100644
index 0000000..c80a25b
--- /dev/null
+++ b/drivers/ptp/Kconfig
@@ -0,0 +1,26 @@
+#
+# PTP clock support configuration
+#
+
+menu "PTP clock support"
+
+config PTP_1588_CLOCK
+	tristate "PTP clock support"
+	depends on EXPERIMENTAL
+	help
+	  The IEEE 1588 standard defines a method to precisely
+	  synchronize distributed clocks over Ethernet networks. The
+	  standard defines a Precision Time Protocol (PTP), which can
+	  be used to achieve synchronization within a few dozen
+	  microseconds. In addition, with the help of special hardware
+	  time stamping units, it can be possible to achieve
+	  synchronization to within a few hundred nanoseconds.
+
+	  This driver adds support for PTP clocks as character
+	  devices. If you want to use a PTP clock, then you should
+	  also enable at least one clock driver as well.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called ptp_clock.
+
+endmenu
diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
new file mode 100644
index 0000000..b86695c
--- /dev/null
+++ b/drivers/ptp/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for PTP 1588 clock support.
+#
+
+obj-$(CONFIG_PTP_1588_CLOCK)		+= ptp_clock.o
diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c
new file mode 100644
index 0000000..4753bf3
--- /dev/null
+++ b/drivers/ptp/ptp_clock.c
@@ -0,0 +1,514 @@
+/*
+ * PTP 1588 clock support
+ *
+ * Partially adapted from the Linux PPS driver.
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/bitops.h>
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/poll.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/uaccess.h>
+
+#include <linux/ptp_clock_kernel.h>
+#include <linux/ptp_clock.h>
+
+#define PTP_MAX_ALARMS 4
+#define PTP_MAX_CLOCKS BITS_PER_LONG
+#define PTP_MAX_TIMESTAMPS 128
+
+struct alarm {
+	struct pid *pid;
+	int sig;
+};
+
+struct timestamp_event_queue {
+	struct ptp_extts_event buf[PTP_MAX_TIMESTAMPS];
+	int head;
+	int tail;
+	int overflow;
+};
+
+struct ptp_clock {
+	struct list_head list;
+	struct cdev cdev;
+	struct device *dev;
+	struct ptp_clock_info *info;
+	dev_t devid;
+	int index; /* index into clocks.map, also the minor number */
+
+	struct alarm alarm[PTP_MAX_ALARMS];
+	struct mutex alarm_mux; /* one process at a time setting an alarm */
+
+	struct timestamp_event_queue tsevq; /* simple fifo for time stamps */
+	struct mutex tsevq_mux; /* one process at a time reading the fifo */
+	wait_queue_head_t tsev_wq;
+};
+
+/* private globals */
+
+static const struct file_operations ptp_fops;
+static dev_t ptp_devt;
+static struct class *ptp_class;
+
+static struct {
+	struct list_head list;
+	DECLARE_BITMAP(map, PTP_MAX_CLOCKS);
+} clocks;
+static DEFINE_SPINLOCK(clocks_lock); /* protects 'clocks' */
+
+/* time stamp event queue operations */
+
+static inline int queue_cnt(struct timestamp_event_queue *q)
+{
+	int cnt = q->tail - q->head;
+	return cnt < 0 ? PTP_MAX_TIMESTAMPS + cnt : cnt;
+}
+
+static inline int queue_free(struct timestamp_event_queue *q)
+{
+	return PTP_MAX_TIMESTAMPS - queue_cnt(q) - 1;
+}
+
+static void enqueue_external_timestamp(struct timestamp_event_queue *queue,
+				       struct ptp_clock_event *src)
+{
+	struct ptp_extts_event *dst;
+	u32 remainder;
+
+	dst = &queue->buf[queue->tail];
+
+	dst->index = src->index;
+	dst->ts.tv_sec = div_u64_rem(src->timestamp, 1000000000, &remainder);
+	dst->ts.tv_nsec = remainder;
+
+	if (!queue_free(queue))
+		queue->overflow++;
+
+	queue->tail = (queue->tail + 1) % PTP_MAX_TIMESTAMPS;
+}
+
+/* public interface */
+
+struct ptp_clock *ptp_clock_register(struct ptp_clock_info *info)
+{
+	struct ptp_clock *ptp;
+	int err = 0, index, major = MAJOR(ptp_devt);
+	unsigned long flags;
+
+	if (info->n_alarm > PTP_MAX_ALARMS)
+		return ERR_PTR(-EINVAL);
+
+	/* Find a free clock slot and reserve it. */
+	err = -EBUSY;
+	spin_lock_irqsave(&clocks_lock, flags);
+	index = find_first_zero_bit(clocks.map, PTP_MAX_CLOCKS);
+	if (index < PTP_MAX_CLOCKS) {
+		set_bit(index, clocks.map);
+		spin_unlock_irqrestore(&clocks_lock, flags);
+	} else {
+		spin_unlock_irqrestore(&clocks_lock, flags);
+		goto no_clock;
+	}
+
+	/* Initialize a clock structure. */
+	err = -ENOMEM;
+	ptp = kzalloc(sizeof(struct ptp_clock), GFP_KERNEL);
+	if (ptp == NULL)
+		goto no_memory;
+
+	ptp->info = info;
+	ptp->devid = MKDEV(major, index);
+	ptp->index = index;
+	mutex_init(&ptp->alarm_mux);
+	mutex_init(&ptp->tsevq_mux);
+	init_waitqueue_head(&ptp->tsev_wq);
+
+	/* Create a new device in our class. */
+	ptp->dev = device_create(ptp_class, NULL, ptp->devid, ptp,
+				 "ptp_clock_%d", ptp->index);
+	if (IS_ERR(ptp->dev))
+		goto no_device;
+
+	dev_set_drvdata(ptp->dev, ptp);
+
+	/* Register a character device. */
+	cdev_init(&ptp->cdev, &ptp_fops);
+	ptp->cdev.owner = info->owner;
+	err = cdev_add(&ptp->cdev, ptp->devid, 1);
+	if (err)
+		goto no_cdev;
+
+	/* Clock is ready, add it into the list. */
+	spin_lock_irqsave(&clocks_lock, flags);
+	list_add(&ptp->list, &clocks.list);
+	spin_unlock_irqrestore(&clocks_lock, flags);
+
+	return ptp;
+
+no_cdev:
+	device_destroy(ptp_class, ptp->devid);
+no_device:
+	mutex_destroy(&ptp->alarm_mux);
+	mutex_destroy(&ptp->tsevq_mux);
+	kfree(ptp);
+no_memory:
+	spin_lock_irqsave(&clocks_lock, flags);
+	clear_bit(index, clocks.map);
+	spin_unlock_irqrestore(&clocks_lock, flags);
+no_clock:
+	return ERR_PTR(err);
+}
+EXPORT_SYMBOL(ptp_clock_register);
+
+int ptp_clock_unregister(struct ptp_clock *ptp)
+{
+	unsigned long flags;
+
+	/* Release the clock's resources. */
+	cdev_del(&ptp->cdev);
+	device_destroy(ptp_class, ptp->devid);
+	mutex_destroy(&ptp->alarm_mux);
+	mutex_destroy(&ptp->tsevq_mux);
+
+	/* Remove the clock from the list. */
+	spin_lock_irqsave(&clocks_lock, flags);
+	list_del(&ptp->list);
+	clear_bit(ptp->index, clocks.map);
+	spin_unlock_irqrestore(&clocks_lock, flags);
+
+	kfree(ptp);
+
+	return 0;
+}
+EXPORT_SYMBOL(ptp_clock_unregister);
+
+void ptp_clock_event(struct ptp_clock *ptp, struct ptp_clock_event *event)
+{
+	switch (event->type) {
+
+	case PTP_CLOCK_ALARM:
+		kill_pid(ptp->alarm[event->index].pid,
+			 ptp->alarm[event->index].sig, 1);
+		break;
+
+	case PTP_CLOCK_EXTTS:
+		enqueue_external_timestamp(&ptp->tsevq, event);
+		wake_up_interruptible(&ptp->tsev_wq);
+		break;
+
+	case PTP_CLOCK_PPS:
+		break;
+	}
+}
+EXPORT_SYMBOL(ptp_clock_event);
+
+/* character device operations */
+
+static int ptp_ioctl(struct inode *node, struct file *fp,
+		      unsigned int cmd, unsigned long arg)
+{
+	struct ptp_clock_caps caps;
+	struct ptp_clock_request req;
+	struct ptp_clock_timer timer;
+	struct ptp_clock *ptp = fp->private_data;
+	struct ptp_clock_info *ops = ptp->info;
+	void *priv = ops->priv;
+	struct timespec ts;
+	int flags, index;
+	int err = 0;
+
+	switch (cmd) {
+
+	case PTP_CLOCK_APIVERS:
+		err = put_user(PTP_CLOCK_VERSION, (u32 __user *)arg);
+		break;
+
+	case PTP_CLOCK_ADJFREQ:
+		if (!capable(CAP_SYS_TIME))
+			return -EPERM;
+		err = ops->adjfreq(priv, arg);
+		break;
+
+	case PTP_CLOCK_ADJTIME:
+		if (!capable(CAP_SYS_TIME))
+			return -EPERM;
+		if (copy_from_user(&ts, (void __user *)arg, sizeof(ts)))
+			err = -EFAULT;
+		else
+			err = ops->adjtime(priv, &ts);
+		break;
+
+	case PTP_CLOCK_GETTIME:
+		err = ops->gettime(priv, &ts);
+		if (err)
+			break;
+		err = copy_to_user((void __user *)arg, &ts, sizeof(ts));
+		break;
+
+	case PTP_CLOCK_SETTIME:
+		if (!capable(CAP_SYS_TIME))
+			return -EPERM;
+		if (copy_from_user(&ts, (void __user *)arg, sizeof(ts)))
+			err = -EFAULT;
+		else
+			err = ops->settime(priv, &ts);
+		break;
+
+	case PTP_CLOCK_GETCAPS:
+		memset(&caps, 0, sizeof(caps));
+		caps.max_adj = ptp->info->max_adj;
+		caps.n_alarm = ptp->info->n_alarm;
+		caps.n_ext_ts = ptp->info->n_ext_ts;
+		caps.n_per_out = ptp->info->n_per_out;
+		caps.pps = ptp->info->pps;
+		err = copy_to_user((void __user *)arg, &caps, sizeof(caps));
+		break;
+
+	case PTP_CLOCK_GETTIMER:
+		if (copy_from_user(&timer, (void __user *)arg, sizeof(timer))) {
+			err = -EFAULT;
+			break;
+		}
+		index = timer.alarm_index;
+		if (index < 0 || index >= ptp->info->n_alarm) {
+			err = -EINVAL;
+			break;
+		}
+		err = ops->gettimer(priv, index, &timer.tsp);
+		if (err)
+			break;
+		err = copy_to_user((void __user *)arg, &timer, sizeof(timer));
+		break;
+
+	case PTP_CLOCK_SETTIMER:
+		if (copy_from_user(&timer, (void __user *)arg, sizeof(timer))) {
+			err = -EFAULT;
+			break;
+		}
+		index = timer.alarm_index;
+		if (index < 0 || index >= ptp->info->n_alarm) {
+			err = -EINVAL;
+			break;
+		}
+		if (!valid_signal(timer.signum))
+			return -EINVAL;
+		flags = timer.flags;
+		if (flags & (flags != TIMER_ABSTIME)) {
+			err = -EINVAL;
+			break;
+		}
+		if (mutex_lock_interruptible(&ptp->alarm_mux))
+			return -ERESTARTSYS;
+
+		if (ptp->alarm[index].pid)
+			put_pid(ptp->alarm[index].pid);
+
+		ptp->alarm[index].pid = get_pid(task_pid(current));
+		ptp->alarm[index].sig = timer.signum;
+		err = ops->settimer(priv, index, flags, &timer.tsp);
+
+		mutex_unlock(&ptp->alarm_mux);
+		break;
+
+	case PTP_FEATURE_REQUEST:
+		if (copy_from_user(&req, (void __user *)arg, sizeof(req))) {
+			err = -EFAULT;
+			break;
+		}
+		switch (req.type) {
+		case PTP_REQUEST_EXTTS:
+		case PTP_REQUEST_PEROUT:
+			break;
+		case PTP_REQUEST_PPS:
+			if (!capable(CAP_SYS_TIME))
+				return -EPERM;
+			break;
+		default:
+			err = -EINVAL;
+			break;
+		}
+		if (err)
+			break;
+		err = ops->enable(priv, &req,
+				  req.flags & PTP_ENABLE_FEATURE ? 1 : 0);
+		break;
+
+	default:
+		err = -ENOTTY;
+		break;
+	}
+	return err;
+}
+
+static int ptp_open(struct inode *inode, struct file *fp)
+{
+	struct ptp_clock *ptp;
+	ptp = container_of(inode->i_cdev, struct ptp_clock, cdev);
+
+	fp->private_data = ptp;
+
+	return 0;
+}
+
+static unsigned int ptp_poll(struct file *fp, poll_table *wait)
+{
+	struct ptp_clock *ptp = fp->private_data;
+
+	poll_wait(fp, &ptp->tsev_wq, wait);
+
+	return queue_cnt(&ptp->tsevq) ? POLLIN : 0;
+}
+
+static ssize_t ptp_read(struct file *fp, char __user *buf,
+			size_t cnt, loff_t *off)
+{
+	struct ptp_clock *ptp = fp->private_data;
+	struct timestamp_event_queue *queue = &ptp->tsevq;
+	struct ptp_extts_event *event;
+	size_t qcnt;
+
+	if (mutex_lock_interruptible(&ptp->tsevq_mux))
+		return -ERESTARTSYS;
+
+	cnt = cnt / sizeof(struct ptp_extts_event);
+
+	if (wait_event_interruptible(ptp->tsev_wq,
+				     (qcnt = queue_cnt(&ptp->tsevq)))) {
+		mutex_unlock(&ptp->tsevq_mux);
+		return -ERESTARTSYS;
+	}
+
+	if (cnt > qcnt)
+		cnt = qcnt;
+
+	event = &queue->buf[queue->head];
+
+	if (copy_to_user(buf, event, cnt * sizeof(struct ptp_extts_event))) {
+		mutex_unlock(&ptp->tsevq_mux);
+		return -EFAULT;
+	}
+	queue->head = (queue->head + cnt) % PTP_MAX_TIMESTAMPS;
+
+	mutex_unlock(&ptp->tsevq_mux);
+
+	return cnt * sizeof(struct ptp_extts_event);
+}
+
+static int ptp_release(struct inode *inode, struct file *fp)
+{
+	struct ptp_clock *ptp;
+	struct itimerspec ts = {
+		{0, 0}, {0, 0}
+	};
+	int i;
+
+	ptp = container_of(inode->i_cdev, struct ptp_clock, cdev);
+
+	for (i = 0; i < ptp->info->n_alarm; i++) {
+		if (ptp->alarm[i].pid) {
+			ptp->info->settimer(ptp->info->priv, i, 0, &ts);
+			put_pid(ptp->alarm[i].pid);
+			ptp->alarm[i].pid = NULL;
+		}
+	}
+	return 0;
+}
+
+static const struct file_operations ptp_fops = {
+	.owner		= THIS_MODULE,
+	.ioctl		= ptp_ioctl,
+	.open		= ptp_open,
+	.poll		= ptp_poll,
+	.read		= ptp_read,
+	.release	= ptp_release,
+};
+
+/* sysfs */
+
+static ssize_t ptp_show_status(struct device *dev,
+			       struct device_attribute *attr, char *buf)
+{
+	struct ptp_clock *ptp = dev_get_drvdata(dev);
+	return sprintf(buf,
+		       "maximum adjustment:  %d\n"
+		       "programmable alarms: %d\n"
+		       "external timestamps: %d\n"
+		       "periodic outputs:    %d\n"
+		       "has pps:             %d\n"
+		       "device index:        %d\n",
+		       ptp->info->max_adj,
+		       ptp->info->n_alarm,
+		       ptp->info->n_ext_ts,
+		       ptp->info->n_per_out,
+		       ptp->info->pps,
+		       ptp->index);
+}
+
+struct device_attribute ptp_attrs[] = {
+	__ATTR(capabilities, S_IRUGO, ptp_show_status, NULL),
+	__ATTR_NULL,
+};
+
+/* module operations */
+
+static void __exit ptp_exit(void)
+{
+	class_destroy(ptp_class);
+	unregister_chrdev_region(ptp_devt, PTP_MAX_CLOCKS);
+}
+
+static int __init ptp_init(void)
+{
+	int err;
+
+	INIT_LIST_HEAD(&clocks.list);
+
+	ptp_class = class_create(THIS_MODULE, "ptp");
+	if (!ptp_class) {
+		printk(KERN_ERR "ptp: failed to allocate class\n");
+		return -ENOMEM;
+	}
+	ptp_class->dev_attrs = ptp_attrs;
+
+	err = alloc_chrdev_region(&ptp_devt, 0, PTP_MAX_CLOCKS, "ptp");
+	if (err < 0) {
+		printk(KERN_ERR "ptp: failed to allocate char device region\n");
+		goto no_region;
+	}
+
+	pr_info("PTP clock support registered\n");
+	return 0;
+
+no_region:
+	class_destroy(ptp_class);
+	return err;
+}
+
+subsys_initcall(ptp_init);
+module_exit(ptp_exit);
+
+MODULE_AUTHOR("Richard Cochran <richard.cochran at omicron.at>");
+MODULE_DESCRIPTION("PTP clocks support");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 2fc8e14..9959fe4 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -140,6 +140,7 @@ header-y += pkt_sched.h
 header-y += posix_types.h
 header-y += ppdev.h
 header-y += prctl.h
+header-y += ptp_clock.h
 header-y += qnxtypes.h
 header-y += qnx4_fs.h
 header-y += radeonfb.h
diff --git a/include/linux/ptp_clock.h b/include/linux/ptp_clock.h
new file mode 100644
index 0000000..5a509c5
--- /dev/null
+++ b/include/linux/ptp_clock.h
@@ -0,0 +1,79 @@
+/*
+ * PTP 1588 clock support - user space interface
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _PTP_CLOCK_H_
+#define _PTP_CLOCK_H_
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+#define PTP_ENABLE_FEATURE (1<<0)
+#define PTP_RISING_EDGE    (1<<1)
+#define PTP_FALLING_EDGE   (1<<2)
+
+enum ptp_request_types {
+	PTP_REQUEST_EXTTS,
+	PTP_REQUEST_PEROUT,
+	PTP_REQUEST_PPS,
+};
+
+struct ptp_clock_caps {
+	__s32 max_adj; /* Maximum frequency adjustment, parts per billon. */
+	int n_alarm;   /* Number of programmable alarms. */
+	int n_ext_ts;  /* Number of external time stamp channels. */
+	int n_per_out; /* Number of programmable periodic signals. */
+	int pps;       /* Whether the clock supports a PPS callback. */
+};
+
+struct ptp_clock_timer {
+	int alarm_index;       /* Which alarm to query or configure. */
+	int signum;            /* Requested signal. */
+	int flags;             /* Zero or TIMER_ABSTIME, see TIMER_SETTIME(2) */
+	struct itimerspec tsp; /* See TIMER_SETTIME(2) */
+};
+
+struct ptp_clock_request {
+	int type;  /* One of the ptp_request_types enumeration values. */
+	int index; /* Which channel to configure. */
+	struct timespec ts; /* For period signals, the desired period. */
+	int flags; /* Bit field for PTP_ENABLE_FEATURE or other flags. */
+};
+
+struct ptp_extts_event {
+	int index;
+	struct timespec ts;
+};
+
+#define PTP_CLOCK_VERSION 0x00000001
+
+#define PTP_CLK_MAGIC '='
+
+#define PTP_CLOCK_APIVERS _IOR (PTP_CLK_MAGIC, 1, __u32)
+#define PTP_CLOCK_ADJFREQ _IO  (PTP_CLK_MAGIC, 2)
+#define PTP_CLOCK_ADJTIME _IOW (PTP_CLK_MAGIC, 3, struct timespec)
+#define PTP_CLOCK_GETTIME _IOR (PTP_CLK_MAGIC, 4, struct timespec)
+#define PTP_CLOCK_SETTIME _IOW (PTP_CLK_MAGIC, 5, struct timespec)
+
+#define PTP_CLOCK_GETCAPS   _IOR  (PTP_CLK_MAGIC, 6, struct ptp_clock_caps)
+#define PTP_CLOCK_GETTIMER  _IOWR (PTP_CLK_MAGIC, 7, struct ptp_clock_timer)
+#define PTP_CLOCK_SETTIMER  _IOW  (PTP_CLK_MAGIC, 8, struct ptp_clock_timer)
+#define PTP_FEATURE_REQUEST _IOW  (PTP_CLK_MAGIC, 9, struct ptp_clock_request)
+
+#endif
diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h
new file mode 100644
index 0000000..d6cc158
--- /dev/null
+++ b/include/linux/ptp_clock_kernel.h
@@ -0,0 +1,137 @@
+/*
+ * PTP 1588 clock support
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _PTP_CLOCK_KERNEL_H_
+#define _PTP_CLOCK_KERNEL_H_
+
+#include <linux/ptp_clock.h>
+
+/**
+ * struct ptp_clock_info - decribes a PTP hardware clock
+ *
+ * @owner:     The clock driver should set to THIS_MODULE.
+ * @name:      A short name to identify the clock.
+ * @max_adj:   The maximum possible frequency adjustment, in parts per billon.
+ * @n_alarm:   The number of programmable alarms.
+ * @n_ext_ts:  The number of external time stamp channels.
+ * @n_per_out: The number of programmable periodic signals.
+ * @pps:       Indicates whether the clock supports a PPS callback.
+ * @priv:      Passed to the clock operations, for the driver's private use.
+ *
+ * clock operations
+ *
+ * @adjfreq:  Adjusts the frequency of the hardware clock.
+ *            parameter delta: Desired period change in parts per billion.
+ *
+ * @adjtime:  Shifts the time of the hardware clock.
+ *            parameter ts: Desired change in seconds and nanoseconds.
+ *
+ * @gettime:  Reads the current time from the hardware clock.
+ *            parameter ts: Holds the result.
+ *
+ * @settime:  Set the current time on the hardware clock.
+ *            parameter ts: Time value to set.
+ *
+ * @gettimer: Reads the time remaining from the given timer.
+ *            parameter index: Which alarm to query.
+ *            parameter ts: Holds the result.
+ *
+ * @settimer: Arms the given timer for periodic or one shot operation.
+ *            parameter index: Which alarm to set.
+ *            parameter abs: TIMER_ABSTIME, or zero for relative timer.
+ *            parameter ts: Alarm time and period to set.
+ *
+ * @enable:   Request driver to enable or disable an ancillary feature.
+ *            parameter request: Desired resource to enable or disable.
+ *            parameter on: Caller passes one to enable or zero to disable.
+ *
+ * The callbacks must all return zero on success, non-zero otherwise.
+ */
+
+struct ptp_clock_info {
+	struct module *owner;
+	char name[16];
+	s32 max_adj;
+	int n_alarm;
+	int n_ext_ts;
+	int n_per_out;
+	int pps;
+	void *priv;
+	int (*adjfreq)(void *priv, s32 delta);
+	int (*adjtime)(void *priv, struct timespec *ts);
+	int (*gettime)(void *priv, struct timespec *ts);
+	int (*settime)(void *priv, struct timespec *ts);
+	int (*gettimer)(void *priv, int index, struct itimerspec *ts);
+	int (*settimer)(void *priv, int index, int abs, struct itimerspec *ts);
+	int (*enable)(void *priv, struct ptp_clock_request *request, int on);
+};
+
+struct ptp_clock;
+
+/**
+ * ptp_clock_register() - register a PTP hardware clock driver
+ *
+ * @info:  Structure describing the new clock.
+ */
+
+extern struct ptp_clock *ptp_clock_register(struct ptp_clock_info *info);
+
+/**
+ * ptp_clock_unregister() - unregister a PTP hardware clock driver
+ *
+ * @ptp:  The clock to remove from service.
+ */
+
+extern int ptp_clock_unregister(struct ptp_clock *ptp);
+
+
+enum ptp_clock_events {
+	PTP_CLOCK_ALARM,
+	PTP_CLOCK_EXTTS,
+	PTP_CLOCK_PPS,
+};
+
+/**
+ * struct ptp_clock_event - decribes a PTP hardware clock event
+ *
+ * @type:  One of the ptp_clock_events enumeration values.
+ * @index: Identifies the source of the event.
+ * @timestamp: When the event occured.
+ */
+
+struct ptp_clock_event {
+	int type;
+	int index;
+	u64 timestamp;
+};
+
+/**
+ * ptp_clock_event() - notify the PTP layer about an event
+ *
+ * This function should only be called from interrupt context.
+ *
+ * @ptp:    The clock obtained from ptp_clock_register().
+ * @event:  Message structure describing the event.
+ */
+
+extern void ptp_clock_event(struct ptp_clock *ptp,
+			    struct ptp_clock_event *event);
+
+#endif
-- 
1.6.3.3



From richardcochran at gmail.com  Tue Jun 15 12:09:46 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:09:46 +0200
Subject: [PATCH 09/12] ptp: Added a clock that uses the Linux system time.
In-Reply-To: <cover.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
Message-ID: <2a9d504ab573d8b83137bd16a318940aaac15d7f.1276615626.git.richard.cochran@omicron.at>

This PTP clock simply uses the NTP time adjustment system calls. The
driver can be used in systems that lack a special hardware PTP clock.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 drivers/ptp/Kconfig     |   12 ++++
 drivers/ptp/Makefile    |    1 +
 drivers/ptp/ptp_linux.c |  136 +++++++++++++++++++++++++++++++++++++++++++++++
 kernel/time/ntp.c       |    2 +
 4 files changed, 151 insertions(+), 0 deletions(-)
 create mode 100644 drivers/ptp/ptp_linux.c

diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index c80a25b..9390d44 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -23,4 +23,16 @@ config PTP_1588_CLOCK
 	  To compile this driver as a module, choose M here: the module
 	  will be called ptp_clock.
 
+config PTP_1588_CLOCK_LINUX
+	tristate "Linux system timer as PTP clock"
+	depends on PTP_1588_CLOCK
+	help
+	  This driver adds support for using the standard Linux time
+	  source as a PTP clock. This clock is only useful if your PTP
+	  programs are using software time stamps for the PTP Ethernet
+	  packets.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called ptp_linux.
+
 endmenu
diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
index b86695c..1651d52 100644
--- a/drivers/ptp/Makefile
+++ b/drivers/ptp/Makefile
@@ -3,3 +3,4 @@
 #
 
 obj-$(CONFIG_PTP_1588_CLOCK)		+= ptp_clock.o
+obj-$(CONFIG_PTP_1588_CLOCK_LINUX)	+= ptp_linux.o
diff --git a/drivers/ptp/ptp_linux.c b/drivers/ptp/ptp_linux.c
new file mode 100644
index 0000000..f93ae0c
--- /dev/null
+++ b/drivers/ptp/ptp_linux.c
@@ -0,0 +1,136 @@
+/*
+ * PTP 1588 clock using the Linux system clock
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/hrtimer.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/timex.h>
+
+#include <linux/ptp_clock_kernel.h>
+
+static struct ptp_clock *linux_clock;
+
+DEFINE_SPINLOCK(adjtime_lock);
+
+static int ptp_linux_adjfreq(void *priv, s32 delta)
+{
+	struct timex txc;
+	s64 tmp = delta;
+	int err;
+	txc.freq = div_s64(tmp<<16, 1000);
+	txc.modes = ADJ_FREQUENCY;
+	err = do_adjtimex(&txc);
+	return err < 0 ? err : 0;
+}
+
+static int ptp_linux_adjtime(void *priv, struct timespec *ts)
+{
+	s64 delta;
+	ktime_t now;
+	struct timespec t2;
+	unsigned long flags;
+	int err;
+
+	delta = 1000000000LL * ts->tv_sec + ts->tv_nsec;
+
+	spin_lock_irqsave(&adjtime_lock, flags);
+
+	now = ktime_get_real();
+
+	now = delta < 0 ? ktime_sub_ns(now, -delta) : ktime_add_ns(now, delta);
+
+	t2 = ktime_to_timespec(now);
+
+	err = do_settimeofday(&t2);
+
+	spin_unlock_irqrestore(&adjtime_lock, flags);
+
+	return err;
+}
+
+static int ptp_linux_gettime(void *priv, struct timespec *ts)
+{
+	getnstimeofday(ts);
+	return 0;
+}
+
+static int ptp_linux_settime(void *priv, struct timespec *ts)
+{
+	return do_settimeofday(ts);
+}
+
+static int ptp_linux_gettimer(void *priv, int index, struct itimerspec *ts)
+{
+	/* We do not offer any ancillary features at all. */
+	return -EOPNOTSUPP;
+}
+
+static int ptp_linux_settimer(void *p, int i, int abs, struct itimerspec *ts)
+{
+	/* We do not offer any ancillary features at all. */
+	return -EOPNOTSUPP;
+}
+
+static int ptp_linux_enable(void *priv, struct ptp_clock_request *rq, int on)
+{
+	/* We do not offer any ancillary features at all. */
+	return -EOPNOTSUPP;
+}
+
+static struct ptp_clock_info ptp_linux_caps = {
+	.owner		= THIS_MODULE,
+	.name		= "Linux timer",
+	.max_adj	= 512000,
+	.n_alarm	= 0,
+	.n_ext_ts	= 0,
+	.n_per_out	= 0,
+	.pps		= 0,
+	.priv		= NULL,
+	.adjfreq	= ptp_linux_adjfreq,
+	.adjtime	= ptp_linux_adjtime,
+	.gettime	= ptp_linux_gettime,
+	.settime	= ptp_linux_settime,
+	.gettimer	= ptp_linux_gettimer,
+	.settimer	= ptp_linux_settimer,
+	.enable		= ptp_linux_enable,
+};
+
+/* module operations */
+
+static void __exit ptp_linux_exit(void)
+{
+	ptp_clock_unregister(linux_clock);
+}
+
+static int __init ptp_linux_init(void)
+{
+	linux_clock = ptp_clock_register(&ptp_linux_caps);
+
+	return IS_ERR(linux_clock) ? PTR_ERR(linux_clock) : 0;
+}
+
+module_init(ptp_linux_init);
+module_exit(ptp_linux_exit);
+
+MODULE_AUTHOR("Richard Cochran <richard.cochran at omicron.at>");
+MODULE_DESCRIPTION("PTP clock using the Linux system timer");
+MODULE_LICENSE("GPL");
diff --git a/kernel/time/ntp.c b/kernel/time/ntp.c
index c631168..eba3bcf 100644
--- a/kernel/time/ntp.c
+++ b/kernel/time/ntp.c
@@ -14,6 +14,7 @@
 #include <linux/timex.h>
 #include <linux/time.h>
 #include <linux/mm.h>
+#include <linux/module.h>
 
 /*
  * NTP timekeeping variables:
@@ -535,6 +536,7 @@ int do_adjtimex(struct timex *txc)
 
 	return result;
 }
+EXPORT_SYMBOL(do_adjtimex);
 
 static int __init ntp_tick_adj_setup(char *str)
 {
-- 
1.6.3.3



From richardcochran at gmail.com  Tue Jun 15 12:10:04 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:10:04 +0200
Subject: [PATCH 10/12] ptp: Added a clock that uses the eTSEC found on the
	MPC85xx.
In-Reply-To: <cover.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
Message-ID: <041faf3cb6ecbedf8f3ff2104914f91d2a24fc4d.1276615626.git.richard.cochran@omicron.at>

The eTSEC includes a PTP clock with quite a few features. This patch adds
support for the basic clock adjustment functions, plus two external time
stamps and one alarm.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 Documentation/powerpc/dts-bindings/fsl/tsec.txt |   54 +++
 arch/powerpc/boot/dts/mpc8313erdb.dts           |   13 +
 arch/powerpc/boot/dts/p2020ds.dts               |   13 +
 arch/powerpc/boot/dts/p2020rdb.dts              |   13 +
 drivers/net/Makefile                            |    1 +
 drivers/net/gianfar_ptp.c                       |  518 +++++++++++++++++++++++
 drivers/net/gianfar_ptp_reg.h                   |  113 +++++
 drivers/ptp/Kconfig                             |   13 +
 8 files changed, 738 insertions(+), 0 deletions(-)
 create mode 100644 drivers/net/gianfar_ptp.c
 create mode 100644 drivers/net/gianfar_ptp_reg.h

diff --git a/Documentation/powerpc/dts-bindings/fsl/tsec.txt b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
index edb7ae1..14577e9 100644
--- a/Documentation/powerpc/dts-bindings/fsl/tsec.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
@@ -74,3 +74,57 @@ Example:
 		interrupt-parent = <&mpic>;
 		phy-handle = <&phy0>
 	};
+
+* Gianfar PTP clock nodes
+
+General Properties:
+
+  - compatible   Should be "fsl,etsec-ptp"
+  - reg          Offset and length of the register set for the device
+  - interrupts   There should be at least two interrupts. Some devices
+                 have as many as four PTP related interrupts.
+
+Clock Properties:
+
+  - tclk_period  Timer reference clock period in nanoseconds.
+  - tmr_prsc     Prescaler, divides the output clock.
+  - tmr_add      Frequency compensation value.
+  - cksel        0= external clock, 1= eTSEC system clock, 3= RTC clock input.
+                 Currently the driver only supports choice "1".
+  - tmr_fiper1   Fixed interval period pulse generator.
+  - tmr_fiper2   Fixed interval period pulse generator.
+
+  These properties set the operational parameters for the PTP
+  clock. You must choose these carefully for the clock to work right.
+  Here is how to figure good values:
+
+  TimerOsc     = system clock               MHz
+  tclk_period  = desired clock period       nanoseconds
+  NominalFreq  = 1000 / tclk_period         MHz
+  FreqDivRatio = TimerOsc / NominalFreq     (must be greater that 1.0)
+  tmr_add      = ceil(2^32 / FreqDivRatio)
+  OutputClock  = NominalFreq / tmr_prsc     MHz
+  PulseWidth   = 1 / OutputClock            microseconds
+  FiperFreq1   = desired frequency in Hz
+  FiperDiv1    = 1000000 * OutputClock / FiperFreq1
+  tmr_fiper1   = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+
+  The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+  driver expects that tmr_fiper1 will be correctly set to produce a 1
+  Pulse Per Second (PPS) signal, since this will be offered to the PPS
+  subsystem to synchronize the Linux clock.
+
+Example:
+
+	ptp_clock at 24E00 {
+		compatible = "fsl,etsec-ptp";
+		reg = <0x24E00 0xB0>;
+		interrupts = <12 0x8 13 0x8>;
+		interrupt-parent = < &ipic >;
+		tclk_period = <10>;
+		tmr_prsc    = <100>;
+		tmr_add     = <0x999999A4>;
+		cksel       = <0x1>;
+		tmr_fiper1  = <0x3B9AC9F6>;
+		tmr_fiper2  = <0x00018696>;
+	};
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 183f2aa..0526384 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -208,6 +208,19 @@
 			sleep = <&pmc 0x00300000>;
 		};
 
+		ptp_clock at 24E00 {
+			compatible = "fsl,etsec-ptp";
+			reg = <0x24E00 0xB0>;
+			interrupts = <12 0x8 13 0x8>;
+			interrupt-parent = < &ipic >;
+			tclk_period = <10>;
+			tmr_prsc    = <100>;
+			tmr_add     = <0x999999A4>;
+			cksel       = <0x1>;
+			tmr_fiper1  = <0x3B9AC9F6>;
+			tmr_fiper2  = <0x00018696>;
+		};
+
 		enet0: ethernet at 24000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 1101914..ae5dc4d 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -336,6 +336,19 @@
 			phy_type = "ulpi";
 		};
 
+		ptp_clock at 24E00 {
+			compatible = "fsl,etsec-ptp";
+			reg = <0x24E00 0xB0>;
+			interrupts = <68 2 69 2 70 2>;
+			interrupt-parent = < &mpic >;
+			tclk_period = <5>;
+			tmr_prsc = <200>;
+			tmr_add = <0xCCCCCCCD>;
+			cksel = <1>;
+			tmr_fiper1 = <0x3B9AC9FB>;
+			tmr_fiper2 = <0x0001869B>;
+		};
+
 		enet0: ethernet at 24000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index da4cb0d..133945c 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -396,6 +396,19 @@
 			phy_type = "ulpi";
 		};
 
+		ptp_clock at 24E00 {
+			compatible = "fsl,etsec-ptp";
+			reg = <0x24E00 0xB0>;
+			interrupts = <68 2 69 2 70 2>;
+			interrupt-parent = < &mpic >;
+			tclk_period = <5>;
+			tmr_prsc = <200>;
+			tmr_add = <0xCCCCCCCD>;
+			cksel = <1>;
+			tmr_fiper1 = <0x3B9AC9FB>;
+			tmr_fiper2 = <0x0001869B>;
+		};
+
 		enet0: ethernet at 24000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 0a0512a..389c0d9 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -28,6 +28,7 @@ obj-$(CONFIG_ATL2) += atlx/
 obj-$(CONFIG_ATL1E) += atl1e/
 obj-$(CONFIG_ATL1C) += atl1c/
 obj-$(CONFIG_GIANFAR) += gianfar_driver.o
+obj-$(CONFIG_PTP_1588_CLOCK_GIANFAR) += gianfar_ptp.o
 obj-$(CONFIG_TEHUTI) += tehuti.o
 obj-$(CONFIG_ENIC) += enic/
 obj-$(CONFIG_JME) += jme.o
diff --git a/drivers/net/gianfar_ptp.c b/drivers/net/gianfar_ptp.c
new file mode 100644
index 0000000..0991652
--- /dev/null
+++ b/drivers/net/gianfar_ptp.c
@@ -0,0 +1,518 @@
+/*
+ * PTP 1588 clock using the eTSEC
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/device.h>
+#include <linux/hrtimer.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/timex.h>
+#include <linux/io.h>
+
+#include <linux/ptp_clock_kernel.h>
+
+#include "gianfar_ptp_reg.h"
+#include "gianfar.h"
+
+#define DRIVER		"gianfar_ptp"
+#define N_ALARM		1 /* first alarm is used internally to reset fipers */
+#define N_EXT_TS	2
+#define REG_SIZE	sizeof(struct gianfar_ptp_registers)
+
+struct etsects {
+	struct gianfar_ptp_registers *regs;
+	struct ptp_clock *clock;
+	int irq;
+	u64 alarm_interval; /* for periodic alarm */
+	u64 alarm_value;
+	u32 tclk_period;  /* nanoseconds */
+	u32 tmr_prsc;
+	u32 tmr_add;
+	u32 cksel;
+	u32 tmr_fiper1;
+	u32 tmr_fiper2;
+};
+
+/* Private globals */
+static struct etsects the_clock;
+DEFINE_SPINLOCK(register_lock);
+
+/*
+ * Register access functions
+ */
+
+static u64 tmr_cnt_read(struct etsects *etsects)
+{
+	u64 ns;
+	u32 lo, hi;
+
+	lo = gfar_read(&etsects->regs->tmr_cnt_l);
+	hi = gfar_read(&etsects->regs->tmr_cnt_h);
+	ns = ((u64) hi) << 32;
+	ns |= lo;
+	return ns;
+}
+
+static void tmr_cnt_write(struct etsects *etsects, u64 ns)
+{
+	u32 hi = ns >> 32;
+	u32 lo = ns & 0xffffffff;
+
+	gfar_write(&etsects->regs->tmr_cnt_l, lo);
+	gfar_write(&etsects->regs->tmr_cnt_h, hi);
+}
+
+static void set_alarm(struct etsects *etsects)
+{
+	u64 ns;
+	u32 lo, hi;
+
+	ns = tmr_cnt_read(etsects) + 1500000000ULL;
+	ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
+	ns -= etsects->tclk_period;
+	hi = ns >> 32;
+	lo = ns & 0xffffffff;
+	gfar_write(&etsects->regs->tmr_alarm1_l, lo);
+	gfar_write(&etsects->regs->tmr_alarm1_h, hi);
+}
+
+static void set_fipers(struct etsects *etsects)
+{
+	u32 tmr_ctrl = gfar_read(&etsects->regs->tmr_ctrl);
+
+	gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl & (~TE));
+	gfar_write(&etsects->regs->tmr_prsc,   etsects->tmr_prsc);
+	gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
+	gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
+	set_alarm(etsects);
+	gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl|TE);
+}
+
+/*
+ * Interrupt service routine
+ */
+
+static irqreturn_t isr(int irq, void *priv)
+{
+	struct etsects *etsects = priv;
+	struct ptp_clock_event event;
+	u64 ns;
+	u32 ack = 0, lo, hi, mask, val;
+
+	val = gfar_read(&etsects->regs->tmr_tevent);
+
+	if (val & ETS1) {
+		ack |= ETS1;
+		hi = gfar_read(&etsects->regs->tmr_etts1_h);
+		lo = gfar_read(&etsects->regs->tmr_etts1_l);
+		event.type = PTP_CLOCK_EXTTS;
+		event.index = 0;
+		event.timestamp = ((u64) hi) << 32;
+		event.timestamp |= lo;
+		ptp_clock_event(etsects->clock, &event);
+	}
+
+	if (val & ETS2) {
+		ack |= ETS2;
+		hi = gfar_read(&etsects->regs->tmr_etts2_h);
+		lo = gfar_read(&etsects->regs->tmr_etts2_l);
+		event.type = PTP_CLOCK_EXTTS;
+		event.index = 1;
+		event.timestamp = ((u64) hi) << 32;
+		event.timestamp |= lo;
+		ptp_clock_event(etsects->clock, &event);
+	}
+
+	if (val & ALM2) {
+		ack |= ALM2;
+		if (etsects->alarm_value) {
+			event.type = PTP_CLOCK_ALARM;
+			event.index = 0;
+			event.timestamp = etsects->alarm_value;
+			ptp_clock_event(etsects->clock, &event);
+		}
+		if (etsects->alarm_interval) {
+			ns = etsects->alarm_value + etsects->alarm_interval;
+			hi = ns >> 32;
+			lo = ns & 0xffffffff;
+			spin_lock(&register_lock);
+			gfar_write(&etsects->regs->tmr_alarm2_l, lo);
+			gfar_write(&etsects->regs->tmr_alarm2_h, hi);
+			spin_unlock(&register_lock);
+			etsects->alarm_value = ns;
+		} else {
+			gfar_write(&etsects->regs->tmr_tevent, ALM2);
+			spin_lock(&register_lock);
+			mask = gfar_read(&etsects->regs->tmr_temask);
+			mask &= ~ALM2EN;
+			gfar_write(&etsects->regs->tmr_temask, mask);
+			spin_unlock(&register_lock);
+			etsects->alarm_value = 0;
+			etsects->alarm_interval = 0;
+		}
+	}
+
+	if (ack) {
+		gfar_write(&etsects->regs->tmr_tevent, ack);
+		return IRQ_HANDLED;
+	} else
+		return IRQ_NONE;
+}
+
+/*
+ * PTP clock operations
+ */
+
+static int ptp_gianfar_adjfreq(void *priv, s32 ppb)
+{
+	u64 adj;
+	u32 diff, tmr_add;
+	int neg_adj = 0;
+	struct etsects *etsects = priv;
+
+	if (!ppb)
+		return 0;
+
+	if (ppb < 0) {
+		neg_adj = 1;
+		ppb = -ppb;
+	}
+	tmr_add = etsects->tmr_add;
+	adj = tmr_add;
+	adj *= ppb;
+	diff = div_u64(adj, 1000000000ULL);
+
+	tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
+
+	gfar_write(&etsects->regs->tmr_add, tmr_add);
+
+	return 0;
+}
+
+static int ptp_gianfar_adjtime(void *priv, struct timespec *ts)
+{
+	s64 delta, now;
+	unsigned long flags;
+	struct etsects *etsects = priv;
+
+	delta = 1000000000LL * ts->tv_sec;
+	delta += ts->tv_nsec;
+
+	spin_lock_irqsave(&register_lock, flags);
+
+	now = tmr_cnt_read(etsects);
+	now += delta;
+	tmr_cnt_write(etsects, now);
+
+	spin_unlock_irqrestore(&register_lock, flags);
+
+	set_fipers(etsects);
+
+	return 0;
+}
+
+static int ptp_gianfar_gettime(void *priv, struct timespec *ts)
+{
+	u64 ns;
+	u32 remainder;
+	unsigned long flags;
+	struct etsects *etsects = priv;
+
+	spin_lock_irqsave(&register_lock, flags);
+
+	ns = tmr_cnt_read(etsects);
+
+	spin_unlock_irqrestore(&register_lock, flags);
+
+	ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
+	ts->tv_nsec = remainder;
+	return 0;
+}
+
+static int ptp_gianfar_settime(void *priv, struct timespec *ts)
+{
+	u64 ns;
+	unsigned long flags;
+	struct etsects *etsects = priv;
+
+	ns = ts->tv_sec * 1000000000ULL;
+	ns += ts->tv_nsec;
+
+	spin_lock_irqsave(&register_lock, flags);
+
+	tmr_cnt_write(etsects, ns);
+	set_fipers(etsects);
+
+	spin_unlock_irqrestore(&register_lock, flags);
+
+	return 0;
+}
+
+static int ptp_gianfar_gettimer(void *priv, int index, struct itimerspec *ts)
+{
+	u64 now, ns;
+	u32 remainder;
+	unsigned long flags;
+	struct etsects *etsects = priv;
+
+	ns = etsects->alarm_interval;
+
+	ts->it_interval.tv_sec = div_u64_rem(ns, 1000000000, &remainder);
+	ts->it_interval.tv_nsec = remainder;
+
+	spin_lock_irqsave(&register_lock, flags);
+	now = tmr_cnt_read(etsects);
+	spin_unlock_irqrestore(&register_lock, flags);
+
+	ns = etsects->alarm_value - now;
+
+	ts->it_value.tv_sec = div_u64_rem(ns, 1000000000, &remainder);
+	ts->it_value.tv_nsec = remainder;
+
+	return 0;
+}
+
+static int ptp_gianfar_settimer(void *p, int i, int abs, struct itimerspec *ts)
+{
+	u64 ns;
+	u32 lo, hi, mask;
+	unsigned long flags;
+	struct etsects *etsects = p;
+
+	ns = ts->it_interval.tv_sec * 1000000000ULL;
+	ns += ts->it_interval.tv_nsec;
+
+	etsects->alarm_interval = ns;
+
+	ns = ts->it_value.tv_sec * 1000000000ULL;
+	ns += ts->it_value.tv_nsec;
+
+	if (!ns) {
+		/* Cancel the timer. */
+		etsects->alarm_value = 0;
+		etsects->alarm_interval = 0;
+		return 0;
+	}
+
+	if (!abs) {
+		spin_lock_irqsave(&register_lock, flags);
+		ns += tmr_cnt_read(etsects);
+		spin_unlock_irqrestore(&register_lock, flags);
+	}
+
+	etsects->alarm_value = ns;
+
+	hi = ns >> 32;
+	lo = ns & 0xffffffff;
+
+	spin_lock_irqsave(&register_lock, flags);
+
+	gfar_write(&etsects->regs->tmr_alarm2_l, lo);
+	gfar_write(&etsects->regs->tmr_alarm2_h, hi);
+
+	mask = gfar_read(&etsects->regs->tmr_temask);
+	mask |= ALM2EN;
+	gfar_write(&etsects->regs->tmr_temask, mask);
+
+	spin_unlock_irqrestore(&register_lock, flags);
+
+	return 0;
+}
+
+static int ptp_gianfar_enable(void *priv, struct ptp_clock_request *rq, int on)
+{
+	struct etsects *etsects = priv;
+	unsigned long flags;
+	u32 bit, mask;
+
+	switch (rq->type) {
+	case PTP_REQUEST_EXTTS:
+		switch (rq->index) {
+		case 0:
+			bit = ETS1EN;
+			break;
+		case 1:
+			bit = ETS2EN;
+			break;
+		default:
+			return -EINVAL;
+		}
+		spin_lock_irqsave(&register_lock, flags);
+		if (on) {
+			mask = gfar_read(&etsects->regs->tmr_temask);
+			mask |= bit;
+			gfar_write(&etsects->regs->tmr_temask, mask);
+		} else {
+			mask = gfar_read(&etsects->regs->tmr_temask);
+			mask &= ~bit;
+			gfar_write(&etsects->regs->tmr_temask, mask);
+		}
+		spin_unlock_irqrestore(&register_lock, flags);
+		return 0;
+	}
+
+	return -EOPNOTSUPP;
+}
+
+static struct ptp_clock_info ptp_gianfar_caps = {
+	.owner		= THIS_MODULE,
+	.name		= "gianfar clock",
+	.max_adj	= 512000,
+	.n_alarm	= N_ALARM,
+	.n_ext_ts	= N_EXT_TS,
+	.n_per_out	= 0,
+	.pps		= 0,
+	.priv		= &the_clock,
+	.adjfreq	= ptp_gianfar_adjfreq,
+	.adjtime	= ptp_gianfar_adjtime,
+	.gettime	= ptp_gianfar_gettime,
+	.settime	= ptp_gianfar_settime,
+	.gettimer	= ptp_gianfar_gettimer,
+	.settimer	= ptp_gianfar_settimer,
+	.enable		= ptp_gianfar_enable,
+};
+
+/* OF device tree */
+
+static int get_of_u32(struct device_node *node, char *str, u32 *val)
+{
+	int plen;
+	const u32 *prop = of_get_property(node, str, &plen);
+
+	if (!prop || plen != sizeof(*prop))
+		return -1;
+	*val = *prop;
+	return 0;
+}
+
+static int gianfar_ptp_probe(struct of_device *dev,
+			     const struct of_device_id *match)
+{
+	u64 addr, size;
+	struct device_node *node = dev->dev.of_node;
+	struct etsects *etsects = &the_clock;
+	struct timespec now;
+	phys_addr_t reg_addr;
+	unsigned long reg_size;
+	u32 tmr_ctrl;
+
+	if (get_of_u32(node, "tclk_period", &etsects->tclk_period) ||
+	    get_of_u32(node, "tmr_prsc", &etsects->tmr_prsc) ||
+	    get_of_u32(node, "tmr_add", &etsects->tmr_add) ||
+	    get_of_u32(node, "cksel", &etsects->cksel) ||
+	    get_of_u32(node, "tmr_fiper1", &etsects->tmr_fiper1) ||
+	    get_of_u32(node, "tmr_fiper2", &etsects->tmr_fiper2)) {
+		pr_err("device tree node missing required elements\n");
+		return -ENODEV;
+	}
+
+	etsects->irq = irq_of_parse_and_map(node, 0);
+
+	if (etsects->irq == NO_IRQ) {
+		pr_err("irq not in device tree\n");
+		return -ENODEV;
+	}
+	if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
+		pr_err("request_irq failed\n");
+		return -ENODEV;
+	}
+
+	addr = of_translate_address(node, of_get_address(node, 0, &size, NULL));
+	reg_addr = addr;
+	reg_size = size;
+	if (reg_size < REG_SIZE) {
+		pr_warning("device tree reg range %lu too small\n", reg_size);
+		reg_size = REG_SIZE;
+	}
+	etsects->regs = ioremap(reg_addr, reg_size);
+	if (!etsects->regs) {
+		pr_err("ioremap ptp registers failed\n");
+		return -EINVAL;
+	}
+
+	tmr_ctrl =
+	  (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
+	  (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
+
+	getnstimeofday(&now);
+	ptp_gianfar_settime(etsects, &now);
+
+	gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl);
+	gfar_write(&etsects->regs->tmr_add,    etsects->tmr_add);
+	gfar_write(&etsects->regs->tmr_prsc,   etsects->tmr_prsc);
+	gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
+	gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
+	set_alarm(etsects);
+	gfar_write(&etsects->regs->tmr_ctrl,   tmr_ctrl|FS|RTPE|TE);
+
+	etsects->clock = ptp_clock_register(&ptp_gianfar_caps);
+
+	return IS_ERR(etsects->clock) ? PTR_ERR(etsects->clock) : 0;
+}
+
+static int gianfar_ptp_remove(struct of_device *dev)
+{
+	gfar_write(&the_clock.regs->tmr_temask, 0);
+	gfar_write(&the_clock.regs->tmr_ctrl,   0);
+
+	ptp_clock_unregister(the_clock.clock);
+
+	free_irq(the_clock.irq, &the_clock);
+
+	iounmap(the_clock.regs);
+
+	return 0;
+}
+
+static struct of_device_id match_table[] = {
+	{ .compatible = "fsl,etsec-ptp" },
+	{},
+};
+
+static struct of_platform_driver gianfar_ptp_driver = {
+	.driver = {
+		.name		= "gianfar_ptp",
+		.of_match_table	= match_table,
+		.owner		= THIS_MODULE,
+	},
+	.probe       = gianfar_ptp_probe,
+	.remove      = gianfar_ptp_remove,
+};
+
+/* module operations */
+
+static void __exit ptp_gianfar_exit(void)
+{
+	of_unregister_platform_driver(&gianfar_ptp_driver);
+}
+
+static int __init ptp_gianfar_init(void)
+{
+	return of_register_platform_driver(&gianfar_ptp_driver);
+}
+
+module_init(ptp_gianfar_init);
+module_exit(ptp_gianfar_exit);
+
+MODULE_AUTHOR("Richard Cochran <richard.cochran at omicron.at>");
+MODULE_DESCRIPTION("PTP clock using the eTSEC");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/gianfar_ptp_reg.h b/drivers/net/gianfar_ptp_reg.h
new file mode 100644
index 0000000..95e171f
--- /dev/null
+++ b/drivers/net/gianfar_ptp_reg.h
@@ -0,0 +1,113 @@
+/* gianfar_ptp_reg.h
+ * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
+ *
+ * PTP 1588 clock using the gianfar eTSEC
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _GIANFAR_PTP_REG_H_
+#define _GIANFAR_PTP_REG_H_
+
+struct gianfar_ptp_registers {
+	u32 tmr_ctrl;     /* Timer control register */
+	u32 tmr_tevent;   /* Timestamp event register */
+	u32 tmr_temask;   /* Timer event mask register */
+	u32 tmr_pevent;   /* Timestamp event register */
+	u32 tmr_pemask;   /* Timer event mask register */
+	u32 tmr_stat;     /* Timestamp status register */
+	u32 tmr_cnt_h;    /* Timer counter high register */
+	u32 tmr_cnt_l;    /* Timer counter low register */
+	u32 tmr_add;      /* Timer drift compensation addend register */
+	u32 tmr_acc;      /* Timer accumulator register */
+	u32 tmr_prsc;     /* Timer prescale */
+	u8  res1[4];
+	u32 tmroff_h;     /* Timer offset high */
+	u32 tmroff_l;     /* Timer offset low */
+	u8  res2[8];
+	u32 tmr_alarm1_h; /* Timer alarm 1 high register */
+	u32 tmr_alarm1_l; /* Timer alarm 1 high register */
+	u32 tmr_alarm2_h; /* Timer alarm 2 high register */
+	u32 tmr_alarm2_l; /* Timer alarm 2 high register */
+	u8  res3[48];
+	u32 tmr_fiper1;   /* Timer fixed period interval */
+	u32 tmr_fiper2;   /* Timer fixed period interval */
+	u32 tmr_fiper3;   /* Timer fixed period interval */
+	u8  res4[20];
+	u32 tmr_etts1_h;  /* Timestamp of general purpose external trigger */
+	u32 tmr_etts1_l;  /* Timestamp of general purpose external trigger */
+	u32 tmr_etts2_h;  /* Timestamp of general purpose external trigger */
+	u32 tmr_etts2_l;  /* Timestamp of general purpose external trigger */
+};
+
+/* Bit definitions for the TMR_CTRL register */
+#define ALM1P                 (1<<31) /* Alarm1 output polarity */
+#define ALM2P                 (1<<30) /* Alarm2 output polarity */
+#define FS                    (1<<28) /* FIPER start indication */
+#define PP1L                  (1<<27) /* Fiper1 pulse loopback mode enabled. */
+#define PP2L                  (1<<26) /* Fiper2 pulse loopback mode enabled. */
+#define TCLK_PERIOD_SHIFT     (16) /* 1588 timer reference clock period. */
+#define TCLK_PERIOD_MASK      (0x3ff)
+#define RTPE                  (1<<15) /* Record Tx Timestamp to PAL Enable. */
+#define FRD                   (1<<14) /* FIPER Realignment Disable */
+#define ESFDP                 (1<<11) /* External Tx/Rx SFD Polarity. */
+#define ESFDE                 (1<<10) /* External Tx/Rx SFD Enable. */
+#define ETEP2                 (1<<9) /* External trigger 2 edge polarity */
+#define ETEP1                 (1<<8) /* External trigger 1 edge polarity */
+#define COPH                  (1<<7) /* Generated clock (TSEC_1588_GCLK) output phase. */
+#define CIPH                  (1<<6) /* External oscillator input clock phase. */
+#define TMSR                  (1<<5) /* Timer soft reset. When enabled, it resets all the timer registers and state machines. */
+#define BYP                   (1<<3) /* Bypass drift compensated clock */
+#define TE                    (1<<2) /* 1588 timer enable. If not enabled, all the timer registers and state machines are disabled. */
+#define CKSEL_SHIFT           (0) /* 1588 Timer reference clock source select. */
+#define CKSEL_MASK            (0x3)
+
+/* Bit definitions for the TMR_TEVENT register */
+#define ETS2                  (1<<25) /* External trigger 2 timestamp sampled */
+#define ETS1                  (1<<24) /* External trigger 1 timestamp sampled */
+#define ALM2                  (1<<17) /* Current time equaled alarm time register 2 */
+#define ALM1                  (1<<16) /* Current time equaled alarm time register 1 */
+#define PP1                   (1<<7) /* Indicates that a periodic pulse has been generated based on FIPER1 register */
+#define PP2                   (1<<6) /* Indicates that a periodic pulse has been generated based on FIPER2 register */
+#define PP3                   (1<<5) /* Indicates that a periodic pulse has been generated based on FIPER3 register */
+
+/* Bit definitions for the TMR_TEMASK register */
+#define ETS2EN                (1<<25) /* External trigger 2 timestamp sample event enable */
+#define ETS1EN                (1<<24) /* External trigger 1 timestamp sample event enable */
+#define ALM2EN                (1<<17) /* Timer ALM2 event enable */
+#define ALM1EN                (1<<16) /* Timer ALM1 event enable */
+#define PP1EN                 (1<<7) /* Periodic pulse event 1 enable */
+#define PP2EN                 (1<<6) /* Periodic pulse event 2 enable */
+
+/* Bit definitions for the TMR_PEVENT register */
+#define TXP2                  (1<<9) /* Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS2 register */
+#define TXP1                  (1<<8) /* Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS1 register */
+#define RXP                   (1<<0) /* Indicates that a PTP frame has been received */
+
+/* Bit definitions for the TMR_PEMASK register */
+#define TXP2EN                (1<<9) /* Transmit PTP packet event 2 enable */
+#define TXP1EN                (1<<8) /* Transmit PTP packet event 1 enable */
+#define RXPEN                 (1<<0) /* Receive PTP packet event enable */
+
+/* Bit definitions for the TMR_STAT register */
+#define STAT_VEC_SHIFT        (0) /* Timer general purpose status vector */
+#define STAT_VEC_MASK         (0x3f)
+
+/* Bit definitions for the TMR_PRSC register */
+#define PRSC_OCK_SHIFT        (0) /* Output clock division/prescale factor. */
+#define PRSC_OCK_MASK         (0xffff)
+
+#endif
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index 9390d44..3b7bd73 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -35,4 +35,17 @@ config PTP_1588_CLOCK_LINUX
 	  To compile this driver as a module, choose M here: the module
 	  will be called ptp_linux.
 
+config PTP_1588_CLOCK_GIANFAR
+	tristate "Freescale eTSEC as PTP clock"
+	depends on PTP_1588_CLOCK
+	depends on GIANFAR
+	help
+	  This driver adds support for using the eTSEC as a PTP
+	  clock. This clock is only useful if your PTP programs are
+	  getting hardware time stamps on the PTP Ethernet packets
+	  using the SO_TIMESTAMPING API.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called gianfar_ptp.
+
 endmenu
-- 
1.6.3.3



From richardcochran at gmail.com  Tue Jun 15 12:10:27 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:10:27 +0200
Subject: [PATCH 11/12] ptp: Added a clock driver for the IXP46x.
In-Reply-To: <cover.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
Message-ID: <0c03ef3e283c6b3ef58feaf1f77ccb0fd605010b.1276615626.git.richard.cochran@omicron.at>

This patch adds a driver for the hardware time stamping unit found on the
IXP465. Only the basic clock operations are implemented.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h |   67 +++++++
 drivers/net/arm/ixp4xx_eth.c                  |  194 +++++++++++++++++++++
 drivers/ptp/Kconfig                           |   13 ++
 drivers/ptp/Makefile                          |    1 +
 drivers/ptp/ptp_ixp46x.c                      |  231 +++++++++++++++++++++++++
 5 files changed, 506 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
 create mode 100644 drivers/ptp/ptp_ixp46x.c

diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644
index 0000000..7fb02b6
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -0,0 +1,67 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _IXP46X_TS_H_
+#define _IXP46X_TS_H_
+
+#define DEFAULT_ADDEND 0xF0000029
+#define TICKS_NS_SHIFT 4
+
+struct ixp46x_channel_ctl {
+	u32 Ch_Control; /* 0x40 Time Synchronization Channel Control */
+	u32 Ch_Event;   /* 0x44 Time Synchronization Channel Event */
+	u32 TxSnapLo;   /* 0x48 Transmit Snapshot Low Register */
+	u32 TxSnapHi;   /* 0x4C Transmit Snapshot High Register */
+	u32 RxSnapLo;   /* 0x50 Receive Snapshot Low Register */
+	u32 RxSnapHi;   /* 0x54 Receive Snapshot High Register */
+	u32 SrcUUIDLo;  /* 0x58 Source UUID0 Low Register */
+	u32 SrcUUIDHi;  /* 0x5C Sequence Identifier/Source UUID0 High */
+};
+
+struct ixp46x_ts_regs {
+	u32 Control;     /* 0x00 Time Sync Control Register */
+	u32 Event;       /* 0x04 Time Sync Event Register */
+	u32 Addend;      /* 0x08 Time Sync Addend Register */
+	u32 Accum;       /* 0x0C Time Sync Accumulator Register */
+	u32 Test;        /* 0x10 Time Sync Test Register */
+	u32 Unused;      /* 0x14 */
+	u32 RSysTime_Lo; /* 0x18 RawSystemTime_Low Register */
+	u32 RSysTimeHi;  /* 0x1C RawSystemTime_High Register */
+	u32 SysTimeLo;   /* 0x20 SystemTime_Low Register */
+	u32 SysTimeHi;   /* 0x24 SystemTime_High Register */
+	u32 TrgtLo;      /* 0x28 TargetTime_Low Register */
+	u32 TrgtHi;      /* 0x2C TargetTime_High Register */
+	u32 ASMSLo;      /* 0x30 Auxiliary Slave Mode Snapshot Low  */
+	u32 ASMSHi;      /* 0x34 Auxiliary Slave Mode Snapshot High */
+	u32 AMMSLo;      /* 0x38 Auxiliary Master Mode Snapshot Low */
+	u32 AMMSHi;      /* 0x3C Auxiliary Master Mode Snapshot High */
+
+	struct ixp46x_channel_ctl channel[3];
+};
+
+/* 0x40 Time Synchronization Channel Control Register Bits */
+#define MASTER_MODE   (1<<0)
+#define TIMESTAMP_ALL (1<<1)
+
+/* 0x44 Time Synchronization Channel Event Register Bits */
+#define TX_SNAPSHOT_LOCKED (1<<0)
+#define RX_SNAPSHOT_LOCKED (1<<1)
+
+#endif
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index 4f1cc71..2201960 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -30,9 +30,12 @@
 #include <linux/etherdevice.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/net_tstamp.h>
 #include <linux/phy.h>
 #include <linux/platform_device.h>
+#include <linux/ptp_classify.h>
 #include <linux/slab.h>
+#include <mach/ixp46x_ts.h>
 #include <mach/npe.h>
 #include <mach/qmgr.h>
 
@@ -67,6 +70,14 @@
 #define RXFREE_QUEUE(port_id)	(NPE_ID(port_id) + 26)
 #define TXDONE_QUEUE		31
 
+#define PTP_SLAVE_MODE		1
+#define PTP_MASTER_MODE		2
+#define PORT2CHANNEL(p)		1
+/*
+ * PHYSICAL_ID(p->id) ?
+ * TODO - Figure out correct mapping.
+ */
+
 /* TX Control Registers */
 #define TX_CNTRL0_TX_EN		0x01
 #define TX_CNTRL0_HALFDUPLEX	0x02
@@ -171,6 +182,8 @@ struct port {
 	int id;			/* logical port ID */
 	int speed, duplex;
 	u8 firmware[4];
+	int hwts_tx_en;
+	int hwts_rx_en;
 };
 
 /* NPE message structure */
@@ -246,6 +259,170 @@ static int ports_open;
 static struct port *npe_port_tab[MAX_NPES];
 static struct dma_pool *dma_pool;
 
+static struct sock_filter ptp_filter[] = {
+	PTP_FILTER
+};
+
+static int match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seq)
+{
+	unsigned int type;
+	u16 *hi, *id;
+	u8 *lo, *data = skb->data;
+
+	type = sk_run_filter(skb, ptp_filter, ARRAY_SIZE(ptp_filter));
+
+	if (PTP_CLASS_V1_IPV4 == type) {
+
+		id = (u16 *)(data + 42 + 30);
+		hi = (u16 *)(data + 42 + 22);
+		lo = data + 42 + 24;
+
+		return (uid_hi == *hi &&
+			0 == memcmp(&uid_lo, lo, sizeof(uid_lo)) &&
+			seq == *id);
+	}
+
+	return 0;
+}
+
+static void do_rx_timestamp(struct port *port, struct sk_buff *skb)
+{
+	struct skb_shared_hwtstamps *shhwtstamps;
+	struct ixp46x_ts_regs *regs;
+	u64 ns;
+	u32 ch, hi, lo, val;
+	u16 uid, seq;
+
+	if (!port->hwts_rx_en)
+		return;
+
+	ch = PORT2CHANNEL(port);
+
+	regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
+
+	val = __raw_readl(&regs->channel[ch].Ch_Event);
+
+	if (!(val & RX_SNAPSHOT_LOCKED))
+		return;
+
+	lo = __raw_readl(&regs->channel[ch].SrcUUIDLo);
+	hi = __raw_readl(&regs->channel[ch].SrcUUIDHi);
+
+	uid = hi & 0xffff;
+	seq = (hi >> 16) & 0xffff;
+
+	if (!match(skb, htons(uid), htonl(lo), htons(seq)))
+		goto out;
+
+	lo = __raw_readl(&regs->channel[ch].RxSnapLo);
+	hi = __raw_readl(&regs->channel[ch].RxSnapHi);
+	ns = ((u64) hi) << 32;
+	ns |= lo;
+	ns <<= TICKS_NS_SHIFT;
+
+	shhwtstamps = skb_hwtstamps(skb);
+	memset(shhwtstamps, 0, sizeof(*shhwtstamps));
+	shhwtstamps->hwtstamp = ns_to_ktime(ns);
+out:
+	__raw_writel(RX_SNAPSHOT_LOCKED, &regs->channel[ch].Ch_Event);
+}
+
+static void do_tx_timestamp(struct port *port, struct sk_buff *skb)
+{
+#ifdef __ARMEB__
+	struct skb_shared_hwtstamps shhwtstamps;
+	struct ixp46x_ts_regs *regs;
+	union skb_shared_tx *shtx;
+	u64 ns;
+	u32 ch, cnt, hi, lo, val;
+
+	shtx = skb_tx(skb);
+
+	if (!shtx->in_progress)
+		return;
+
+	ch = PORT2CHANNEL(port);
+
+	regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
+
+	/*
+	 * This really stinks, but we have to poll for the Tx time stamp.
+	 * Usually, the time stamp is ready after 4 to 6 microseconds.
+	 */
+	for (cnt = 0; cnt < 100; cnt++) {
+		val = __raw_readl(&regs->channel[ch].Ch_Event);
+		if (val & TX_SNAPSHOT_LOCKED)
+			break;
+		udelay(1);
+	}
+	if (!(val & TX_SNAPSHOT_LOCKED)) {
+		shtx->in_progress = 0;
+		return;
+	}
+
+	lo = __raw_readl(&regs->channel[ch].TxSnapLo);
+	hi = __raw_readl(&regs->channel[ch].TxSnapHi);
+	ns = ((u64) hi) << 32;
+	ns |= lo;
+	ns <<= TICKS_NS_SHIFT;
+
+	memset(&shhwtstamps, 0, sizeof(shhwtstamps));
+	shhwtstamps.hwtstamp = ns_to_ktime(ns);
+	skb_tstamp_tx(skb, &shhwtstamps);
+
+	__raw_writel(TX_SNAPSHOT_LOCKED, &regs->channel[ch].Ch_Event);
+#endif
+}
+
+static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
+{
+	struct hwtstamp_config cfg;
+	struct ixp46x_ts_regs *regs;
+	struct port *port = netdev_priv(netdev);
+	int ch;
+
+	if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
+		return -EFAULT;
+
+	if (cfg.flags) /* reserved for future extensions */
+		return -EINVAL;
+
+	ch = PORT2CHANNEL(port);
+	regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
+
+	switch (cfg.tx_type) {
+	case HWTSTAMP_TX_OFF:
+		port->hwts_tx_en = 0;
+		break;
+	case HWTSTAMP_TX_ON:
+		port->hwts_tx_en = 1;
+		break;
+	default:
+		return -ERANGE;
+	}
+
+	switch (cfg.rx_filter) {
+	case HWTSTAMP_FILTER_NONE:
+		port->hwts_rx_en = 0;
+		break;
+	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
+		port->hwts_rx_en = PTP_SLAVE_MODE;
+		__raw_writel(0, &regs->channel[ch].Ch_Control);
+		break;
+	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
+		port->hwts_rx_en = PTP_MASTER_MODE;
+		__raw_writel(MASTER_MODE, &regs->channel[ch].Ch_Control);
+		break;
+	default:
+		return -ERANGE;
+	}
+
+	/* Clear out any old time stamps. */
+	__raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
+		     &regs->channel[ch].Ch_Event);
+
+	return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
+}
 
 static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
 			   int write, u16 cmd)
@@ -573,6 +750,7 @@ static int eth_poll(struct napi_struct *napi, int budget)
 
 		debug_pkt(dev, "eth_poll", skb->data, skb->len);
 
+		do_rx_timestamp(port, skb);
 		skb->protocol = eth_type_trans(skb, dev);
 		dev->stats.rx_packets++;
 		dev->stats.rx_bytes += skb->len;
@@ -652,6 +830,7 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
 	void *mem;
 	u32 phys;
 	struct desc *desc;
+	union skb_shared_tx *shtx;
 
 #if DEBUG_TX
 	printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
@@ -665,6 +844,10 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
 
 	debug_pkt(dev, "eth_xmit", skb->data, skb->len);
 
+	shtx = skb_tx(skb);
+	if (unlikely(shtx->hardware && port->hwts_tx_en))
+		shtx->in_progress = 1;
+
 	len = skb->len;
 #ifdef __ARMEB__
 	offset = 0; /* no need to keep alignment */
@@ -728,6 +911,9 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
 #if DEBUG_TX
 	printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
 #endif
+
+	do_tx_timestamp(port, skb);
+
 	return NETDEV_TX_OK;
 }
 
@@ -783,6 +969,9 @@ static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
 	if (!netif_running(dev))
 		return -EINVAL;
 
+	if (cpu_is_ixp46x() && cmd == SIOCSHWTSTAMP)
+		return hwtstamp_ioctl(dev, req, cmd);
+
 	return phy_mii_ioctl(port->phydev, req, cmd);
 }
 
@@ -1171,6 +1360,11 @@ static int __devinit eth_init_one(struct platform_device *pdev)
 	char phy_id[MII_BUS_ID_SIZE + 3];
 	int err;
 
+	if (sk_chk_filter(ptp_filter, ARRAY_SIZE(ptp_filter))) {
+		pr_err("ixp4xx_eth: bad ptp filter\n");
+		return -EINVAL;
+	}
+
 	if (!(dev = alloc_etherdev(sizeof(struct port))))
 		return -ENOMEM;
 
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index 3b7bd73..9fb35f6 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -48,4 +48,17 @@ config PTP_1588_CLOCK_GIANFAR
 	  To compile this driver as a module, choose M here: the module
 	  will be called gianfar_ptp.
 
+config PTP_1588_CLOCK_IXP46X
+	tristate "Intel IXP46x as PTP clock"
+	depends on PTP_1588_CLOCK
+	depends on IXP4XX_ETH
+	help
+	  This driver adds support for using the IXP46X as a PTP
+	  clock. This clock is only useful if your PTP programs are
+	  getting hardware time stamps on the PTP Ethernet packets
+	  using the SO_TIMESTAMPING API.
+
+	  To compile this driver as a module, choose M here: the module
+	  will be called ptp_ixp46x.
+
 endmenu
diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
index 1651d52..5018f58 100644
--- a/drivers/ptp/Makefile
+++ b/drivers/ptp/Makefile
@@ -4,3 +4,4 @@
 
 obj-$(CONFIG_PTP_1588_CLOCK)		+= ptp_clock.o
 obj-$(CONFIG_PTP_1588_CLOCK_LINUX)	+= ptp_linux.o
+obj-$(CONFIG_PTP_1588_CLOCK_IXP46X)	+= ptp_ixp46x.o
diff --git a/drivers/ptp/ptp_ixp46x.c b/drivers/ptp/ptp_ixp46x.c
new file mode 100644
index 0000000..22c5bc3
--- /dev/null
+++ b/drivers/ptp/ptp_ixp46x.c
@@ -0,0 +1,231 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <linux/ptp_clock_kernel.h>
+#include <mach/ixp46x_ts.h>
+
+DEFINE_SPINLOCK(register_lock);
+
+/*
+ * Register access functions
+ */
+
+static inline u32 ixp_read(volatile unsigned __iomem *addr)
+{
+	u32 val;
+	val = __raw_readl(addr);
+	return val;
+}
+
+static inline void ixp_write(volatile unsigned __iomem *addr, u32 val)
+{
+	__raw_writel(val, addr);
+}
+
+static u64 sys_time_read(struct ixp46x_ts_regs *regs)
+{
+	u64 ns;
+	u32 lo, hi;
+
+	lo = ixp_read(&regs->SysTimeLo);
+	hi = ixp_read(&regs->SysTimeHi);
+
+	ns = ((u64) hi) << 32;
+	ns |= lo;
+	ns <<= TICKS_NS_SHIFT;
+
+	return ns;
+}
+
+static void sys_time_write(struct ixp46x_ts_regs *regs, u64 ns)
+{
+	u32 hi, lo;
+
+	ns >>= TICKS_NS_SHIFT;
+	hi = ns >> 32;
+	lo = ns & 0xffffffff;
+
+	ixp_write(&regs->SysTimeLo, lo);
+	ixp_write(&regs->SysTimeHi, hi);
+}
+
+/*
+ * PTP clock operations
+ */
+
+static int ptp_ixp_adjfreq(void *priv, s32 ppb)
+{
+	u64 adj;
+	u32 diff, addend;
+	int neg_adj = 0;
+	struct ixp46x_ts_regs *regs = priv;
+
+	if (!ppb)
+		return 0;
+
+	if (ppb < 0) {
+		neg_adj = 1;
+		ppb = -ppb;
+	}
+	addend = DEFAULT_ADDEND;
+	adj = addend;
+	adj *= ppb;
+	diff = div_u64(adj, 1000000000ULL);
+
+	addend = neg_adj ? addend - diff : addend + diff;
+
+	ixp_write(&regs->Addend, addend);
+
+	return 0;
+}
+
+static int ptp_ixp_adjtime(void *priv, struct timespec *ts)
+{
+	s64 delta, now;
+	unsigned long flags;
+	struct ixp46x_ts_regs *regs = priv;
+
+	delta = 1000000000LL * ts->tv_sec;
+	delta += ts->tv_nsec;
+
+	spin_lock_irqsave(&register_lock, flags);
+
+	now = sys_time_read(regs);
+	now += delta;
+	sys_time_write(regs, now);
+
+	spin_unlock_irqrestore(&register_lock, flags);
+
+	return 0;
+}
+
+static int ptp_ixp_gettime(void *priv, struct timespec *ts)
+{
+	u64 ns;
+	u32 remainder;
+	unsigned long flags;
+	struct ixp46x_ts_regs *regs = priv;
+
+	spin_lock_irqsave(&register_lock, flags);
+
+	ns = sys_time_read(regs);
+
+	spin_unlock_irqrestore(&register_lock, flags);
+
+	ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
+	ts->tv_nsec = remainder;
+	return 0;
+}
+
+static int ptp_ixp_settime(void *priv, struct timespec *ts)
+{
+	u64 ns;
+	unsigned long flags;
+	struct ixp46x_ts_regs *regs = priv;
+
+	ns = ts->tv_sec * 1000000000ULL;
+	ns += ts->tv_nsec;
+
+	spin_lock_irqsave(&register_lock, flags);
+
+	sys_time_write(regs, ns);
+
+	spin_unlock_irqrestore(&register_lock, flags);
+
+	return 0;
+}
+
+static int ptp_ixp_gettimer(void *priv, int index, struct itimerspec *ts)
+{
+	/* We do not offer any ancillary features at all. */
+	return -EOPNOTSUPP;
+}
+
+static int ptp_ixp_settimer(void *p, int i, int abs, struct itimerspec *ts)
+{
+	/* We do not offer any ancillary features at all. */
+	return -EOPNOTSUPP;
+}
+
+static int ptp_ixp_enable(void *priv, struct ptp_clock_request *rq, int on)
+{
+	/* We do not offer any ancillary features at all. */
+	return -EOPNOTSUPP;
+}
+
+static struct ptp_clock_info ptp_ixp_caps = {
+	.owner		= THIS_MODULE,
+	.name		= "IXP46X timer",
+	.max_adj	= 512000,
+	.n_alarm	= 0,
+	.n_ext_ts	= 0,
+	.n_per_out	= 0,
+	.pps		= 0,
+	.priv		= NULL,
+	.adjfreq	= ptp_ixp_adjfreq,
+	.adjtime	= ptp_ixp_adjtime,
+	.gettime	= ptp_ixp_gettime,
+	.settime	= ptp_ixp_settime,
+	.gettimer	= ptp_ixp_gettimer,
+	.settimer	= ptp_ixp_settimer,
+	.enable		= ptp_ixp_enable,
+};
+
+/* module operations */
+
+static struct {
+	struct ixp46x_ts_regs *regs;
+	struct ptp_clock *ptp_clock;
+} ixp_clock;
+
+static void __exit ptp_ixp_exit(void)
+{
+	ptp_clock_unregister(ixp_clock.ptp_clock);
+}
+
+static int __init ptp_ixp_init(void)
+{
+	ixp_clock.regs = 
+		(struct ixp46x_ts_regs __iomem *)IXP4XX_TIMESYNC_BASE_VIRT;
+
+	ptp_ixp_caps.priv = ixp_clock.regs;
+
+	ixp_clock.ptp_clock = ptp_clock_register(&ptp_ixp_caps);
+
+	if (IS_ERR(ixp_clock.ptp_clock))
+		return PTR_ERR(ixp_clock.ptp_clock);
+
+	ixp_write(&ixp_clock.regs->Addend, DEFAULT_ADDEND);
+
+	return 0;
+}
+
+module_init(ptp_ixp_init);
+module_exit(ptp_ixp_exit);
+
+MODULE_AUTHOR("Richard Cochran <richard.cochran at omicron.at>");
+MODULE_DESCRIPTION("PTP clock using the IXP46X timer");
+MODULE_LICENSE("GPL");
-- 
1.6.3.3



From richardcochran at gmail.com  Tue Jun 15 12:10:45 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:10:45 +0200
Subject: [PATCH 12/12] ptp: Added a clock driver for the National
	Semiconductor PHYTER.
In-Reply-To: <cover.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
Message-ID: <37f5015b186bdd51f8451ade042f90c8b39a5cc8.1276615626.git.richard.cochran@omicron.at>

This patch adds support for the PTP clock found on the DP83640. Only the
basic clock operations have been implemented.

Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
---
 drivers/net/phy/Kconfig   |   11 +++
 drivers/net/phy/dp83640.c |  158 ++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 168 insertions(+), 1 deletions(-)

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 430cab1..507c68a 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -79,9 +79,20 @@ config NATIONAL_PHY
 
 config DP83640_PHY
 	tristate "Driver for the National Semiconductor DP83640 PHYTER"
+	depends on PTP_1588_CLOCK
+	depends on NETWORK_PHY_TIMESTAMPING
 	---help---
 	  Supports the DP83640 PHYTER with IEEE 1588 features.
 
+	  This driver adds support for using the DP83640 as a PTP
+	  clock. This clock is only useful if your PTP programs are
+	  getting hardware time stamps on the PTP Ethernet packets
+	  using the SO_TIMESTAMPING API.
+
+	  In order for this to work, your MAC driver must also
+	  implement the the skb_tx_timetamp() and skb_rx_timetamp()
+	  functions.
+
 config STE10XP
 	depends on PHYLIB
 	tristate "Driver for STMicroelectronics STe10Xp PHYs"
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
index a3217ea..21eadc3 100644
--- a/drivers/net/phy/dp83640.c
+++ b/drivers/net/phy/dp83640.c
@@ -26,6 +26,7 @@
 #include <linux/netdevice.h>
 #include <linux/phy.h>
 #include <linux/ptp_classify.h>
+#include <linux/ptp_clock_kernel.h>
 
 #include "dp83640_reg.h"
 
@@ -45,10 +46,13 @@ struct rxts {
 };
 
 struct dp83640_private {
+	struct phy_device *phydev;
 	int hwts_tx_en;
 	int hwts_rx_en;
 	int layer;
 	int version;
+	/* protects PTP_TDR register from concurrent access */
+	spinlock_t ptp_tdr_lock;
 	/* protects extended registers from concurrent access */
 	spinlock_t extreg_lock;
 	int page;
@@ -60,6 +64,9 @@ struct dp83640_private {
 
 /* globals */
 
+static struct ptp_clock *dp83640_clock;
+DEFINE_SPINLOCK(clock_lock); /* protects the one and only dp83640_clock */
+
 static struct sock_filter ptp_filter[] = {
 	PTP_FILTER
 };
@@ -99,6 +106,129 @@ static void ext_write(struct phy_device *phydev, int page, u32 regnum, u16 val)
 	spin_unlock(&dp83640->extreg_lock);
 }
 
+static int tdr_write(struct dp83640_private *dp83640,
+		     struct timespec *ts, u16 cmd)
+{
+	struct phy_device *phydev = dp83640->phydev;
+
+	spin_lock(&dp83640->ptp_tdr_lock);
+
+	ext_write(phydev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
+	ext_write(phydev, PAGE4, PTP_TDR, ts->tv_nsec >> 16);   /* ns[31:16] */
+	ext_write(phydev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
+	ext_write(phydev, PAGE4, PTP_TDR, ts->tv_sec >> 16);    /* sec[31:16] */
+
+	ext_write(phydev, PAGE4, PTP_CTL, cmd);
+
+	spin_unlock(&dp83640->ptp_tdr_lock);
+
+	return 0;
+}
+
+/* ptp clock methods */
+
+static int ptp_dp83640_adjfreq(void *priv, s32 ppb)
+{
+	struct dp83640_private *dp83640 = priv;
+	struct phy_device *phydev = dp83640->phydev;
+	u64 rate;
+	int neg_adj = 0;
+	u16 hi, lo;
+
+	if (!ppb)
+		return 0;
+
+	if (ppb < 0) {
+		neg_adj = 1;
+		ppb = -ppb;
+	}
+	rate = ppb;
+	rate <<= 26;
+	rate = div_u64(rate, 1953125);
+
+	hi = (rate >> 16) & PTP_RATE_HI_MASK;
+	if (neg_adj)
+		hi |= PTP_RATE_DIR;
+
+	lo = rate & 0xffff;
+
+	ext_write(phydev, PAGE4, PTP_RATEH, hi);
+	ext_write(phydev, PAGE4, PTP_RATEL, lo);
+
+	return 0;
+}
+
+static int ptp_dp83640_adjtime(void *priv, struct timespec *ts)
+{
+	return tdr_write(priv, ts, PTP_STEP_CLK);
+}
+
+static int ptp_dp83640_gettime(void *priv, struct timespec *ts)
+{
+	struct dp83640_private *dp83640 = priv;
+	struct phy_device *phydev = dp83640->phydev;
+	unsigned int val[4];
+
+	spin_lock(&dp83640->ptp_tdr_lock);
+
+	ext_write(phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
+
+	val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
+	val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
+	val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
+	val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
+
+	spin_unlock(&dp83640->ptp_tdr_lock);
+
+	ts->tv_nsec = val[0] | (val[1] << 16);
+	ts->tv_sec  = val[2] | (val[3] << 16);
+
+	return 0;
+}
+
+static int ptp_dp83640_settime(void *priv, struct timespec *ts)
+{
+	return tdr_write(priv, ts, PTP_LOAD_CLK);
+}
+
+static int ptp_dp83640_gettimer(void *priv, int index, struct itimerspec *ts)
+{
+	/* We do not (yet) offer any ancillary features. */
+	return -EOPNOTSUPP;
+}
+
+static int ptp_dp83640_settimer(void *p, int i, int abs, struct itimerspec *ts)
+{
+	/* We do not (yet) offer any ancillary features. */
+	return -EOPNOTSUPP;
+}
+
+static int ptp_dp83640_enable(void *priv, struct ptp_clock_request *rq, int on)
+{
+	/* We do not (yet) offer any ancillary features. */
+	return -EOPNOTSUPP;
+}
+
+static struct ptp_clock_info ptp_dp83640_caps = {
+	.owner		= THIS_MODULE,
+	.name		= "dp83640 timer",
+	.max_adj	= 1953124,
+	.n_alarm	= 0,
+	.n_ext_ts	= 0,
+	.n_per_out	= 0,
+	.pps		= 0,
+	.priv		= NULL,
+	.adjfreq	= ptp_dp83640_adjfreq,
+	.adjtime	= ptp_dp83640_adjtime,
+	.gettime	= ptp_dp83640_gettime,
+	.settime	= ptp_dp83640_settime,
+	.gettimer	= ptp_dp83640_gettimer,
+	.settimer	= ptp_dp83640_settimer,
+	.enable		= ptp_dp83640_enable,
+};
+
+/* time stamping methods */
+
 static int expired(struct rxts *rxts)
 {
 	return time_after(jiffies, rxts->tmo);
@@ -144,6 +274,7 @@ static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
 static int dp83640_probe(struct phy_device *phydev)
 {
 	struct dp83640_private *dp83640;
+	unsigned long flags;
 	int i;
 
 	if (sk_chk_filter(ptp_filter, ARRAY_SIZE(ptp_filter))) {
@@ -155,8 +286,9 @@ static int dp83640_probe(struct phy_device *phydev)
 	if (!dp83640)
 		return -ENOMEM;
 
+	dp83640->phydev = phydev;
+	spin_lock_init(&dp83640->ptp_tdr_lock);
 	spin_lock_init(&dp83640->extreg_lock);
-
 	INIT_LIST_HEAD(&dp83640->rxts);
 	INIT_LIST_HEAD(&dp83640->pool);
 
@@ -165,12 +297,36 @@ static int dp83640_probe(struct phy_device *phydev)
 
 	phydev->priv = dp83640;
 
+	spin_lock_irqsave(&clock_lock, flags);
+
+	if (!dp83640_clock) {
+		ptp_dp83640_caps.priv = dp83640;
+		dp83640_clock = ptp_clock_register(&ptp_dp83640_caps);
+		if (IS_ERR(dp83640_clock)) {
+			spin_unlock_irqrestore(&clock_lock, flags);
+			kfree(dp83640);
+			return PTR_ERR(dp83640_clock);
+		}
+	}
+	spin_unlock_irqrestore(&clock_lock, flags);
+
 	return 0;
 }
 
 static void dp83640_remove(struct phy_device *phydev)
 {
 	struct dp83640_private *dp83640 = phydev->priv;
+	unsigned long flags;
+
+	spin_lock_irqsave(&clock_lock, flags);
+
+	if (ptp_dp83640_caps.priv == dp83640) {
+		ptp_clock_unregister(dp83640_clock);
+		dp83640_clock = NULL;
+		ptp_dp83640_caps.priv = NULL;
+	}
+	spin_unlock_irqrestore(&clock_lock, flags);
+
 	kfree(dp83640);
 }
 
-- 
1.6.3.3



From grant.likely at secretlab.ca  Tue Jun 15 12:26:54 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 15 Jun 2010 10:26:54 -0600
Subject: [PATCH 02/12] phylib: do not filter phy_mii_ioctl()
In-Reply-To: <4cd127a2aa2c40a1b573e079e0624f10d1d94867.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<4cd127a2aa2c40a1b573e079e0624f10d1d94867.1276615626.git.richard.cochran@omicron.at>
Message-ID: <AANLkTiliSFzs0dowKbMW-dqcmwEncHT98vGyEmXE3O3Q@mail.gmail.com>

On Tue, Jun 15, 2010 at 10:07 AM, Richard Cochran
<richardcochran at gmail.com> wrote:
> Two maverick drivers filter the ioctl commands passed to phy_mii_ioctl().
> This is unnecessary since phylib will check the command in any case.
>
> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>

At a glance, looks okay to me.

> ---
> ?drivers/net/cpmac.c ? ? ? ? ? ? ?| ? ?5 +----
> ?drivers/net/stmmac/stmmac_main.c | ? 22 ++++++++--------------
> ?2 files changed, 9 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c
> index d4c5ca4..0e47ca1 100644
> --- a/drivers/net/cpmac.c
> +++ b/drivers/net/cpmac.c
> @@ -846,11 +846,8 @@ static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
> ? ? ? ? ? ? ? ?return -EINVAL;
> ? ? ? ?if (!priv->phy)
> ? ? ? ? ? ? ? ?return -EINVAL;
> - ? ? ? if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
> - ? ? ? ? ? (cmd == SIOCSMIIREG))
> - ? ? ? ? ? ? ? return phy_mii_ioctl(priv->phy, ifr, cmd);
>
> - ? ? ? return -EOPNOTSUPP;
> + ? ? ? return phy_mii_ioctl(priv->phy, ifr, cmd);
> ?}
>
> ?static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
> diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c
> index 6af7471..acf0616 100644
> --- a/drivers/net/stmmac/stmmac_main.c
> +++ b/drivers/net/stmmac/stmmac_main.c
> @@ -1437,24 +1437,18 @@ static void stmmac_poll_controller(struct net_device *dev)
> ?static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
> ?{
> ? ? ? ?struct stmmac_priv *priv = netdev_priv(dev);
> - ? ? ? int ret = -EOPNOTSUPP;
> + ? ? ? int ret;
>
> ? ? ? ?if (!netif_running(dev))
> ? ? ? ? ? ? ? ?return -EINVAL;
>
> - ? ? ? switch (cmd) {
> - ? ? ? case SIOCGMIIPHY:
> - ? ? ? case SIOCGMIIREG:
> - ? ? ? case SIOCSMIIREG:
> - ? ? ? ? ? ? ? if (!priv->phydev)
> - ? ? ? ? ? ? ? ? ? ? ? return -EINVAL;
> -
> - ? ? ? ? ? ? ? spin_lock(&priv->lock);
> - ? ? ? ? ? ? ? ret = phy_mii_ioctl(priv->phydev, rq, cmd);
> - ? ? ? ? ? ? ? spin_unlock(&priv->lock);
> - ? ? ? default:
> - ? ? ? ? ? ? ? break;
> - ? ? ? }
> + ? ? ? if (!priv->phydev)
> + ? ? ? ? ? ? ? return -EINVAL;
> +
> + ? ? ? spin_lock(&priv->lock);
> + ? ? ? ret = phy_mii_ioctl(priv->phydev, rq, cmd);
> + ? ? ? spin_unlock(&priv->lock);
> +
> ? ? ? ?return ret;
> ?}
>
> --
> 1.6.3.3
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From grant.likely at secretlab.ca  Tue Jun 15 12:27:59 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 15 Jun 2010 10:27:59 -0600
Subject: [PATCH 03/12] phylib: add a driver method for the SIOCSHWTSTAMP 
	ioctl.
In-Reply-To: <77fe18d640e35dcbfad1e117a4321f935500d5ac.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<77fe18d640e35dcbfad1e117a4321f935500d5ac.1276615626.git.richard.cochran@omicron.at>
Message-ID: <AANLkTiml5FyHstY-0ZPHxFDvA349BZv3TeX9gXtURFFN@mail.gmail.com>

On Tue, Jun 15, 2010 at 10:08 AM, Richard Cochran
<richardcochran at gmail.com> wrote:
> This patch adds a phy driver method for configuring hardware time stamping.
> Drivers may optionally implement this function.
>
> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>

Adding an ioctl to the userspace ABI.  Make sure you cc: linux-kernel
on the next spin of this series.

g.

> ---
> ?drivers/net/phy/phy.c | ? ?5 +++++
> ?include/linux/phy.h ? | ? ?3 +++
> ?2 files changed, 8 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
> index bd88d81..5130db8 100644
> --- a/drivers/net/phy/phy.c
> +++ b/drivers/net/phy/phy.c
> @@ -361,6 +361,11 @@ int phy_mii_ioctl(struct phy_device *phydev,
> ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ?break;
>
> + ? ? ? case SIOCSHWTSTAMP:
> + ? ? ? ? ? ? ? if (phydev->drv->hwtstamp)
> + ? ? ? ? ? ? ? ? ? ? ? return phydev->drv->hwtstamp(phydev, ifr);
> + ? ? ? ? ? ? ? /* fall through */
> +
> ? ? ? ?default:
> ? ? ? ? ? ? ? ?return -EOPNOTSUPP;
> ? ? ? ?}
> diff --git a/include/linux/phy.h b/include/linux/phy.h
> index d63736a..a5e9df1 100644
> --- a/include/linux/phy.h
> +++ b/include/linux/phy.h
> @@ -402,6 +402,9 @@ struct phy_driver {
> ? ? ? ?/* Clears up any memory if needed */
> ? ? ? ?void (*remove)(struct phy_device *phydev);
>
> + ? ? ? /* Handles SIOCSHWTSTAMP ioctl for hardware time stamping. */
> + ? ? ? int (*hwtstamp)(struct phy_device *phydev, struct ifreq *ifr);
> +
> ? ? ? ?struct device_driver driver;
> ?};
> ?#define to_phy_driver(d) container_of(d, struct phy_driver, driver)
> --
> 1.6.3.3
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From richardcochran at gmail.com  Tue Jun 15 12:34:09 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 18:34:09 +0200
Subject: [PATCH 03/12] phylib: add a driver method for the
	SIOCSHWTSTAMP ioctl.
In-Reply-To: <AANLkTiml5FyHstY-0ZPHxFDvA349BZv3TeX9gXtURFFN@mail.gmail.com>
References: <cover.1276615626.git.richard.cochran@omicron.at>
	<77fe18d640e35dcbfad1e117a4321f935500d5ac.1276615626.git.richard.cochran@omicron.at>
	<AANLkTiml5FyHstY-0ZPHxFDvA349BZv3TeX9gXtURFFN@mail.gmail.com>
Message-ID: <20100615163409.GA10668@riccoc20.at.omicron.at>

On Tue, Jun 15, 2010 at 10:27:59AM -0600, Grant Likely wrote:
> On Tue, Jun 15, 2010 at 10:08 AM, Richard Cochran
> <richardcochran at gmail.com> wrote:
> > This patch adds a phy driver method for configuring hardware time stamping.
> > Drivers may optionally implement this function.
> >
> > Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
> 
> Adding an ioctl to the userspace ABI.  Make sure you cc: linux-kernel
> on the next spin of this series.

Not sure what you mean. SIOCSHWTSTAMP is a standard socket option as
of 2.6.30. The patch just makes it possible for PHY drivers to
implement this option.

Richard



From grant.likely at secretlab.ca  Tue Jun 15 12:33:51 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 15 Jun 2010 10:33:51 -0600
Subject: [PATCH 04/12] phylib: add a way to make PHY time stamps possible.
In-Reply-To: <27c0ad283f025c2bb71e7ceb71be07f969939429.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<27c0ad283f025c2bb71e7ceb71be07f969939429.1276615626.git.richard.cochran@omicron.at>
Message-ID: <AANLkTimhAvu0_WuMCwnCrw9Rbcy6dKxvTlzepJm7ZDdR@mail.gmail.com>

On Tue, Jun 15, 2010 at 10:08 AM, Richard Cochran
<richardcochran at gmail.com> wrote:
> This patch adds a new networking option to allow hardware time stamps
> from PHY devices. Using PHY time stamps will still require adding two
> inline function calls to each MAC driver. The CONFIG option makes these
> calls safe to add, since the calls become NOOPs when the option is
> disabled.
>
> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
> ---
> ?include/linux/phy.h ? ?| ? ?4 ++++
> ?include/linux/skbuff.h | ? 32 ++++++++++++++++++++++++++++++++
> ?net/Kconfig ? ? ? ? ? ?| ? 11 +++++++++++
> ?3 files changed, 47 insertions(+), 0 deletions(-)
>
[...]
> diff --git a/net/Kconfig b/net/Kconfig
> index 0d68b40..3fa7ae3 100644
> --- a/net/Kconfig
> +++ b/net/Kconfig
> @@ -86,6 +86,17 @@ config NETWORK_SECMARK
> ? ? ? ? ?to nfmark, but designated for security purposes.
> ? ? ? ? ?If you are unsure how to answer this question, answer N.
>
> +config NETWORK_PHY_TIMESTAMPING
> + ? ? ? bool "Timestamping in PHY devices"
> + ? ? ? depends on EXPERIMENTAL
> + ? ? ? help
> + ? ? ? ? This allows timestamping of network packets by PHYs with
> + ? ? ? ? hardware timestamping capabilities. This option adds some
> + ? ? ? ? overhead in the transmit and receive paths. Note that this
> + ? ? ? ? option also requires support in the MAC driver.

Some overhead?  At a brief glance of the series it looks like it could
add a lot of overhead, but I'm not fully clear on what the full
process is.  Can you describe how the hardware timestamping works?  I
could use an overview of what the kernel has to do.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From grant.likely at secretlab.ca  Tue Jun 15 12:43:08 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 15 Jun 2010 10:43:08 -0600
Subject: [PATCH 05/12] phylib: Allow reading and writing a mii bus from 
	atomic context.
In-Reply-To: <1b8219e7d7993d0e8204b94e959477e3007534ce.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<1b8219e7d7993d0e8204b94e959477e3007534ce.1276615626.git.richard.cochran@omicron.at>
Message-ID: <AANLkTikeae2t4KmnawOCo2LqfSI57BKjNnUayY09DfEC@mail.gmail.com>

On Tue, Jun 15, 2010 at 10:08 AM, Richard Cochran
<richardcochran at gmail.com> wrote:
> In order to support hardware time stamping from a PHY, it is necessary to
> read from the PHY while running in_interrupt(). This patch allows a mii
> bus to operate in an atomic context. An mii_bus driver may declare itself
> capable for this mode. Drivers which do not do this will remain with the
> default that bus operations may sleep.
>
> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>

Last I checked, the MDIO bus is very slow.  Is this really a good
idea?  How much latency does MDIO access have on the hardware you are
working with?

I also don't like the idea of taking a spin lock during MDIO
operations, and the dual locking mode in the core code.

I'd rather see separate atomic context hooks that doesn't obtain the
mutex under the assumption that the caller has already done so.  If
the bus doesn't support atomic access, then it won't implement the
hooks and the core code should return an error.

I've cc'd Thomas Gleixner.  He might have a better idea about how to
implement what you're trying to do.

g.

> ---
> ?drivers/net/phy/mdio_bus.c | ? 35 ++++++++++++++++++++++++++++-------
> ?include/linux/phy.h ? ? ? ?| ? 13 +++++++++++--
> ?2 files changed, 39 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
> index 6a6b819..441be7d 100644
> --- a/drivers/net/phy/mdio_bus.c
> +++ b/drivers/net/phy/mdio_bus.c
> @@ -36,6 +36,22 @@
> ?#include <asm/irq.h>
> ?#include <asm/uaccess.h>
>
> +static inline void mdiobus_lock(struct mii_bus *bus)
> +{
> + ? ? ? if (MDIOBUS_SLEEPS_RW == bus->locktype)
> + ? ? ? ? ? ? ? mutex_lock(&bus->mdio_lock.m);
> + ? ? ? else
> + ? ? ? ? ? ? ? spin_lock(&bus->mdio_lock.s);
> +}
> +
> +static inline void mdiobus_unlock(struct mii_bus *bus)
> +{
> + ? ? ? if (MDIOBUS_SLEEPS_RW == bus->locktype)
> + ? ? ? ? ? ? ? mutex_unlock(&bus->mdio_lock.m);
> + ? ? ? else
> + ? ? ? ? ? ? ? spin_unlock(&bus->mdio_lock.s);
> +}
> +
> ?/**
> ?* mdiobus_alloc - allocate a mii_bus structure
> ?*
> @@ -107,7 +123,10 @@ int mdiobus_register(struct mii_bus *bus)
> ? ? ? ? ? ? ? ?return -EINVAL;
> ? ? ? ?}
>
> - ? ? ? mutex_init(&bus->mdio_lock);
> + ? ? ? if (MDIOBUS_SLEEPS_RW == bus->locktype)
> + ? ? ? ? ? ? ? mutex_init(&bus->mdio_lock.m);
> + ? ? ? else
> + ? ? ? ? ? ? ? spin_lock_init(&bus->mdio_lock.s);
>
> ? ? ? ?if (bus->reset)
> ? ? ? ? ? ? ? ?bus->reset(bus);
> @@ -212,11 +231,12 @@ int mdiobus_read(struct mii_bus *bus, int addr, u32 regnum)
> ?{
> ? ? ? ?int retval;
>
> - ? ? ? BUG_ON(in_interrupt());
> + ? ? ? if (MDIOBUS_SLEEPS_RW == bus->locktype)
> + ? ? ? ? ? ? ? BUG_ON(in_interrupt());
>
> - ? ? ? mutex_lock(&bus->mdio_lock);
> + ? ? ? mdiobus_lock(bus);
> ? ? ? ?retval = bus->read(bus, addr, regnum);
> - ? ? ? mutex_unlock(&bus->mdio_lock);
> + ? ? ? mdiobus_unlock(bus);
>
> ? ? ? ?return retval;
> ?}
> @@ -237,11 +257,12 @@ int mdiobus_write(struct mii_bus *bus, int addr, u32 regnum, u16 val)
> ?{
> ? ? ? ?int err;
>
> - ? ? ? BUG_ON(in_interrupt());
> + ? ? ? if (MDIOBUS_SLEEPS_RW == bus->locktype)
> + ? ? ? ? ? ? ? BUG_ON(in_interrupt());
>
> - ? ? ? mutex_lock(&bus->mdio_lock);
> + ? ? ? mdiobus_lock(bus);
> ? ? ? ?err = bus->write(bus, addr, regnum, val);
> - ? ? ? mutex_unlock(&bus->mdio_lock);
> + ? ? ? mdiobus_unlock(bus);
>
> ? ? ? ?return err;
> ?}
> diff --git a/include/linux/phy.h b/include/linux/phy.h
> index 7a8caac..352b030 100644
> --- a/include/linux/phy.h
> +++ b/include/linux/phy.h
> @@ -98,11 +98,20 @@ struct mii_bus {
> ? ? ? ?int (*write)(struct mii_bus *bus, int phy_id, int regnum, u16 val);
> ? ? ? ?int (*reset)(struct mii_bus *bus);
>
> + ? ? ? /* Indicates whether bus may be used from an atomic context. */
> + ? ? ? enum {
> + ? ? ? ? ? ? ? MDIOBUS_SLEEPS_RW,
> + ? ? ? ? ? ? ? MDIOBUS_ATOMIC_RW
> + ? ? ? } locktype;
> +
> ? ? ? ?/*
> - ? ? ? ?* A lock to ensure that only one thing can read/write
> + ? ? ? ?* A lock or mutex to ensure that only one thing can read/write
> ? ? ? ? * the MDIO bus at a time
> ? ? ? ? */
> - ? ? ? struct mutex mdio_lock;
> + ? ? ? union {
> + ? ? ? ? ? ? ? struct mutex m;
> + ? ? ? ? ? ? ? spinlock_t s;
> + ? ? ? } mdio_lock;
>
> ? ? ? ?struct device *parent;
> ? ? ? ?enum {
> --
> 1.6.3.3
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From grant.likely at secretlab.ca  Tue Jun 15 12:49:56 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 15 Jun 2010 10:49:56 -0600
Subject: [PATCH 03/12] phylib: add a driver method for the SIOCSHWTSTAMP 
	ioctl.
In-Reply-To: <20100615163409.GA10668@riccoc20.at.omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<77fe18d640e35dcbfad1e117a4321f935500d5ac.1276615626.git.richard.cochran@omicron.at>
	<AANLkTiml5FyHstY-0ZPHxFDvA349BZv3TeX9gXtURFFN@mail.gmail.com> 
	<20100615163409.GA10668@riccoc20.at.omicron.at>
Message-ID: <AANLkTilYe-TKxSnIweNt4laXLlhP6pCe9Hr4szqv_7TY@mail.gmail.com>

On Tue, Jun 15, 2010 at 10:34 AM, Richard Cochran
<richardcochran at gmail.com> wrote:
> On Tue, Jun 15, 2010 at 10:27:59AM -0600, Grant Likely wrote:
>> On Tue, Jun 15, 2010 at 10:08 AM, Richard Cochran
>> <richardcochran at gmail.com> wrote:
>> > This patch adds a phy driver method for configuring hardware time stamping.
>> > Drivers may optionally implement this function.
>> >
>> > Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
>>
>> Adding an ioctl to the userspace ABI. ?Make sure you cc: linux-kernel
>> on the next spin of this series.
>
> Not sure what you mean. SIOCSHWTSTAMP is a standard socket option as
> of 2.6.30. The patch just makes it possible for PHY drivers to
> implement this option.

Ah, sorry.  I didn't go check that first.

g.


From grant.likely at secretlab.ca  Tue Jun 15 12:53:21 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 15 Jun 2010 10:53:21 -0600
Subject: [PATCH 03/12] phylib: add a driver method for the SIOCSHWTSTAMP 
	ioctl.
In-Reply-To: <AANLkTilYe-TKxSnIweNt4laXLlhP6pCe9Hr4szqv_7TY@mail.gmail.com>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<77fe18d640e35dcbfad1e117a4321f935500d5ac.1276615626.git.richard.cochran@omicron.at>
	<AANLkTiml5FyHstY-0ZPHxFDvA349BZv3TeX9gXtURFFN@mail.gmail.com> 
	<20100615163409.GA10668@riccoc20.at.omicron.at>
	<AANLkTilYe-TKxSnIweNt4laXLlhP6pCe9Hr4szqv_7TY@mail.gmail.com>
Message-ID: <AANLkTinFWxzfl3swUIho5q9dpfkzwq9v76HLAQYnzPQ7@mail.gmail.com>

On Tue, Jun 15, 2010 at 10:49 AM, Grant Likely
<grant.likely at secretlab.ca> wrote:
> On Tue, Jun 15, 2010 at 10:34 AM, Richard Cochran
> <richardcochran at gmail.com> wrote:
>> On Tue, Jun 15, 2010 at 10:27:59AM -0600, Grant Likely wrote:
>>> On Tue, Jun 15, 2010 at 10:08 AM, Richard Cochran
>>> <richardcochran at gmail.com> wrote:
>>> > This patch adds a phy driver method for configuring hardware time stamping.
>>> > Drivers may optionally implement this function.
>>> >
>>> > Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
>>>
>>> Adding an ioctl to the userspace ABI. ?Make sure you cc: linux-kernel
>>> on the next spin of this series.
>>
>> Not sure what you mean. SIOCSHWTSTAMP is a standard socket option as
>> of 2.6.30. The patch just makes it possible for PHY drivers to
>> implement this option.
>
> Ah, sorry. ?I didn't go check that first.

Although, now that I'm looking through the PTP patches, you
*definitely* should post this series to the lkml.  It has implications
beyond ppc and arm.

g.


From grant.likely at secretlab.ca  Tue Jun 15 13:00:10 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 15 Jun 2010 11:00:10 -0600
Subject: [PATCH 08/12] ptp: Added a brand new class driver for ptp clocks.
In-Reply-To: <4a030d2bace90f089f2f3f61496b918c6f1dfb52.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<4a030d2bace90f089f2f3f61496b918c6f1dfb52.1276615626.git.richard.cochran@omicron.at>
Message-ID: <AANLkTin4lYghEWhjzEyARvYDgHaXdniwLbfyZ4jY0rwm@mail.gmail.com>

On Tue, Jun 15, 2010 at 10:09 AM, Richard Cochran
<richardcochran at gmail.com> wrote:
> This patch adds an infrastructure for hardware clocks that implement
> IEEE 1588, the Precision Time Protocol (PTP). A class driver offers a
> registration method to particular hardware clock drivers. Each clock is
> exposed to user space as a character device with ioctls that allow tuning
> of the PTP clock.
>
> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
> ---
> ?Documentation/ptp/ptp.txt ? ? ? ?| ? 95 +++++++
> ?Documentation/ptp/testptp.c ? ? ?| ?269 ++++++++++++++++++++
> ?Documentation/ptp/testptp.mk ? ? | ? 33 +++
> ?drivers/Kconfig ? ? ? ? ? ? ? ? ?| ? ?2 +
> ?drivers/Makefile ? ? ? ? ? ? ? ? | ? ?1 +
> ?drivers/ptp/Kconfig ? ? ? ? ? ? ?| ? 26 ++
> ?drivers/ptp/Makefile ? ? ? ? ? ? | ? ?5 +
> ?drivers/ptp/ptp_clock.c ? ? ? ? ?| ?514 ++++++++++++++++++++++++++++++++++++++
> ?include/linux/Kbuild ? ? ? ? ? ? | ? ?1 +
> ?include/linux/ptp_clock.h ? ? ? ?| ? 79 ++++++
> ?include/linux/ptp_clock_kernel.h | ?137 ++++++++++
> ?11 files changed, 1162 insertions(+), 0 deletions(-)
> ?create mode 100644 Documentation/ptp/ptp.txt
> ?create mode 100644 Documentation/ptp/testptp.c
> ?create mode 100644 Documentation/ptp/testptp.mk
> ?create mode 100644 drivers/ptp/Kconfig
> ?create mode 100644 drivers/ptp/Makefile
> ?create mode 100644 drivers/ptp/ptp_clock.c
> ?create mode 100644 include/linux/ptp_clock.h
> ?create mode 100644 include/linux/ptp_clock_kernel.h
>
> diff --git a/Documentation/ptp/ptp.txt b/Documentation/ptp/ptp.txt
> new file mode 100644
> index 0000000..46858b3
> --- /dev/null
> +++ b/Documentation/ptp/ptp.txt
> @@ -0,0 +1,95 @@
> +
> +* PTP infrastructure for Linux
> +
> + ?This patch set introduces support for IEEE 1588 PTP clocks in
> + ?Linux. Together with the SO_TIMESTAMPING socket options, this
> + ?presents a standardized method for developing PTP user space
> + ?programs, synchronizing Linux with external clocks, and using the
> + ?ancillary features of PTP hardware clocks.
> +
> + ?A new class driver exports a kernel interface for specific clock
> + ?drivers and a user space interface. The infrastructure supports a
> + ?complete set of PTP functionality.
> +
> + ?+ Basic clock operations
> + ? ?- Set time
> + ? ?- Get time
> + ? ?- Shift the clock by a given offset atomically
> + ? ?- Adjust clock frequency
> +
> + ?+ Ancillary clock features
> + ? ?- One short or periodic alarms, with signal delivery to user program
> + ? ?- Time stamp external events
> + ? ?- Period output signals configurable from user space
> + ? ?- Synchronization of the Linux system time via the PPS subsystem
> +
> +** PTP kernel API
> +
> + ? A PTP clock driver registers itself with the class driver. The
> + ? class driver handles all of the dealings with user space. The
> + ? author of a clock driver need only implement the details of
> + ? programming the clock hardware. The clock driver notifies the class
> + ? driver of asynchronous events (alarms and external time stamps) via
> + ? a simple message passing interface.
> +
> + ? The class driver supports multiple PTP clock drivers. In normal use
> + ? cases, only one PTP clock is needed. However, for testing and
> + ? development, it can be useful to have more than one clock in a
> + ? single system, in order to allow performance comparisons.
> +
> +** PTP user space API
> +
> + ? The class driver creates a character device for each registered PTP
> + ? clock. User space programs may control the clock using standardized
> + ? ioctls. A program may query, enable, configure, and disable the
> + ? ancillary clock features. User space can receive time stamped
> + ? events via blocking read() and poll(). One shot and periodic
> + ? signals may be configured via an ioctl API with semantics similar
> + ? to the POSIX timer_settime() system call.
> +
> + ? As an real life example, the following two patches for ptpd version
> + ? 1.0.0 demonstrate how the API works.
> +
> + ? https://sourceforge.net/tracker/?func=detail&aid=2992845&group_id=139814&atid=744634
> +
> + ? https://sourceforge.net/tracker/?func=detail&aid=2992847&group_id=139814&atid=744634

Question from an ignorant reviewer:  Why a new interface instead of
working with the existing high resolution timers infrastructure?

g.

> +
> +** Writing clock drivers
> +
> + ? Clock drivers include include/linux/ptp_clock_kernel.h and register
> + ? themselves by presenting a 'struct ptp_clock_info' to the
> + ? registration method. Clock drivers must implement all of the
> + ? functions in the interface. If a clock does not offer a particular
> + ? ancillary feature, then the driver should just return -EOPNOTSUPP
> + ? from those functions.
> +
> + ? Drivers must ensure that all of the methods in interface are
> + ? reentrant. Since most hardware implementations treat the time value
> + ? as a 64 bit integer accessed as two 32 bit registers, drivers
> + ? should use spin_lock_irqsave/spin_unlock_irqrestore to protect
> + ? against concurrent access. This locking cannot be accomplished in
> + ? class driver, since the lock may also be needed by the clock
> + ? driver's interrupt service routine.
> +
> +** Supported hardware
> +
> + ? + Standard Linux system timer
> + ? ? - No special PTP features
> + ? ? - For use with software time stamping
> +
> + ? + Freescale eTSEC gianfar
> + ? ? - 2 Time stamp external triggers, programmable polarity (opt. interrupt)
> + ? ? - 2 Alarm registers (optional interrupt)
> + ? ? - 3 Periodic signals (optional interrupt)
> +
> + ? + National DP83640
> + ? ? - 6 GPIOs programmable as inputs or outputs
> + ? ? - 6 GPIOs with dedicated functions (LED/JTAG/clock) can also be
> + ? ? ? used as general inputs or outputs
> + ? ? - GPIO inputs can time stamp external triggers
> + ? ? - GPIO outputs can produce periodic signals
> + ? ? - 1 interrupt pin
> +
> + ? + Intel IXP465
> + ? ? - Auxiliary Slave/Master Mode Snapshot (optional interrupt)
> + ? ? - Target Time (optional interrupt)
> diff --git a/Documentation/ptp/testptp.c b/Documentation/ptp/testptp.c
> new file mode 100644
> index 0000000..e30f758
> --- /dev/null
> +++ b/Documentation/ptp/testptp.c
> @@ -0,0 +1,269 @@
> +/*
> + * PTP 1588 clock support - User space test program
> + *
> + * Copyright (C) 2010 OMICRON electronics GmbH
> + *
> + * ?This program is free software; you can redistribute it and/or modify
> + * ?it under the terms of the GNU General Public License as published by
> + * ?the Free Software Foundation; either version 2 of the License, or
> + * ?(at your option) any later version.
> + *
> + * ?This program is distributed in the hope that it will be useful,
> + * ?but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * ?GNU General Public License for more details.
> + *
> + * ?You should have received a copy of the GNU General Public License
> + * ?along with this program; if not, write to the Free Software
> + * ?Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +#include <errno.h>
> +#include <fcntl.h>
> +#include <signal.h>
> +#include <stdio.h>
> +#include <stdlib.h>
> +#include <string.h>
> +#include <sys/ioctl.h>
> +#include <sys/mman.h>
> +#include <sys/stat.h>
> +#include <sys/time.h>
> +#include <sys/types.h>
> +#include <time.h>
> +#include <unistd.h>
> +
> +#include <linux/ptp_clock.h>
> +
> +static void handle_alarm(int s)
> +{
> + ? ? ? printf("received signal %d\n", s);
> +}
> +
> +static int install_handler(int signum, void (*handler)(int))
> +{
> + ? ? ? struct sigaction action;
> + ? ? ? sigset_t mask;
> +
> + ? ? ? /* Unblock the signal. */
> + ? ? ? sigemptyset(&mask);
> + ? ? ? sigaddset(&mask, signum);
> + ? ? ? sigprocmask(SIG_UNBLOCK, &mask, NULL);
> +
> + ? ? ? /* Install the signal handler. */
> + ? ? ? action.sa_handler = handler;
> + ? ? ? action.sa_flags = 0;
> + ? ? ? sigemptyset(&action.sa_mask);
> + ? ? ? sigaction(signum, &action, NULL);
> +
> + ? ? ? return 0;
> +}
> +
> +static void usage(char *progname)
> +{
> + ? ? ? fprintf(stderr,
> + ? ? ? ? ? ? ? "usage: %s [options]\n"
> + ? ? ? ? ? ? ? " -a val ? ? request a one-shot alarm after 'val' seconds\n"
> + ? ? ? ? ? ? ? " -A val ? ? request a periodic alarm every 'val' seconds\n"
> + ? ? ? ? ? ? ? " -c ? ? ? ? query the ptp clock's capabilities\n"
> + ? ? ? ? ? ? ? " -d name ? ?device to open\n"
> + ? ? ? ? ? ? ? " -e val ? ? read 'val' external time stamp events\n"
> + ? ? ? ? ? ? ? " -f val ? ? adjust the ptp clock frequency by 'val' PPB\n"
> + ? ? ? ? ? ? ? " -g ? ? ? ? get the ptp clock time\n"
> + ? ? ? ? ? ? ? " -h ? ? ? ? prints this message\n"
> + ? ? ? ? ? ? ? " -s ? ? ? ? set the ptp clock time from the system time\n"
> + ? ? ? ? ? ? ? " -t val ? ? shift the ptp clock time by 'val' seconds\n"
> + ? ? ? ? ? ? ? " -v ? ? ? ? query the ptp clock api version\n",
> + ? ? ? ? ? ? ? progname);
> +}
> +
> +int main(int argc, char *argv[])
> +{
> + ? ? ? struct ptp_clock_caps caps;
> + ? ? ? struct ptp_clock_timer timer;
> + ? ? ? struct ptp_extts_event event;
> + ? ? ? struct ptp_clock_request request;
> + ? ? ? struct timespec ts;
> + ? ? ? char *progname;
> + ? ? ? int c, cnt, fd, val = 0;
> +
> + ? ? ? char *device = "/dev/ptp_clock_0";
> + ? ? ? int adjfreq = 0x7fffffff;
> + ? ? ? int adjtime = 0;
> + ? ? ? int capabilities = 0;
> + ? ? ? int extts = 0;
> + ? ? ? int gettime = 0;
> + ? ? ? int oneshot = 0;
> + ? ? ? int periodic = 0;
> + ? ? ? int settime = 0;
> + ? ? ? int version = 0;
> +
> + ? ? ? progname = strrchr(argv[0], '/');
> + ? ? ? progname = progname ? 1+progname : argv[0];
> + ? ? ? while (EOF != (c = getopt(argc, argv, "a:A:cd:e:f:ghst:v"))) {
> + ? ? ? ? ? ? ? switch (c) {
> + ? ? ? ? ? ? ? case 'a':
> + ? ? ? ? ? ? ? ? ? ? ? oneshot = atoi(optarg);
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case 'A':
> + ? ? ? ? ? ? ? ? ? ? ? periodic = atoi(optarg);
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case 'c':
> + ? ? ? ? ? ? ? ? ? ? ? capabilities = 1;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case 'd':
> + ? ? ? ? ? ? ? ? ? ? ? device = optarg;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case 'e':
> + ? ? ? ? ? ? ? ? ? ? ? extts = atoi(optarg);
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case 'f':
> + ? ? ? ? ? ? ? ? ? ? ? adjfreq = atoi(optarg);
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case 'g':
> + ? ? ? ? ? ? ? ? ? ? ? gettime = 1;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case 's':
> + ? ? ? ? ? ? ? ? ? ? ? settime = 1;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case 't':
> + ? ? ? ? ? ? ? ? ? ? ? adjtime = atoi(optarg);
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case 'v':
> + ? ? ? ? ? ? ? ? ? ? ? version = 1;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case 'h':
> + ? ? ? ? ? ? ? ? ? ? ? usage(progname);
> + ? ? ? ? ? ? ? ? ? ? ? return 0;
> + ? ? ? ? ? ? ? case '?':
> + ? ? ? ? ? ? ? default:
> + ? ? ? ? ? ? ? ? ? ? ? usage(progname);
> + ? ? ? ? ? ? ? ? ? ? ? return -1;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? fd = open(device, O_RDWR);
> + ? ? ? if (fd < 0) {
> + ? ? ? ? ? ? ? fprintf(stderr, "cannot open %s: %s", device, strerror(errno));
> + ? ? ? ? ? ? ? return -1;
> + ? ? ? }
> +
> + ? ? ? if (version) {
> + ? ? ? ? ? ? ? if (ioctl(fd, PTP_CLOCK_APIVERS, &val)) {
> + ? ? ? ? ? ? ? ? ? ? ? perror("PTP_CLOCK_APIVERS");
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? printf("version = 0x%08x\n", val);
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (capabilities) {
> + ? ? ? ? ? ? ? if (ioctl(fd, PTP_CLOCK_GETCAPS, &caps)) {
> + ? ? ? ? ? ? ? ? ? ? ? perror("PTP_CLOCK_GETCAPS");
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? printf("capabilities:\n"
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?" ?%d maximum frequency adjustment (PPB)\n"
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?" ?%d programmable alarms\n"
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?" ?%d external time stamp channels\n"
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?" ?%d programmable periodic signals\n"
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?" ?%d pulse per second\n",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?caps.max_adj,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?caps.n_alarm,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?caps.n_ext_ts,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?caps.n_per_out,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?caps.pps);
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (0x7fffffff != adjfreq) {
> + ? ? ? ? ? ? ? if (ioctl(fd, PTP_CLOCK_ADJFREQ, adjfreq)) {
> + ? ? ? ? ? ? ? ? ? ? ? perror("PTP_CLOCK_ADJFREQ");
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? puts("frequency adjustment okay");
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (adjtime) {
> + ? ? ? ? ? ? ? ts.tv_sec = adjtime;
> + ? ? ? ? ? ? ? ts.tv_nsec = 0;
> + ? ? ? ? ? ? ? if (ioctl(fd, PTP_CLOCK_ADJTIME, &ts)) {
> + ? ? ? ? ? ? ? ? ? ? ? perror("PTP_CLOCK_ADJTIME");
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? puts("time shift okay");
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (gettime) {
> + ? ? ? ? ? ? ? if (ioctl(fd, PTP_CLOCK_GETTIME, &ts)) {
> + ? ? ? ? ? ? ? ? ? ? ? perror("PTP_CLOCK_GETTIME");
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? printf("clock time: %ld.%09ld or %s",
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ts.tv_sec, ts.tv_nsec, ctime(&ts.tv_sec));
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (settime) {
> + ? ? ? ? ? ? ? clock_gettime(CLOCK_REALTIME, &ts);
> + ? ? ? ? ? ? ? if (ioctl(fd, PTP_CLOCK_SETTIME, &ts)) {
> + ? ? ? ? ? ? ? ? ? ? ? perror("PTP_CLOCK_SETTIME");
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? puts("set time okay");
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (extts) {
> + ? ? ? ? ? ? ? memset(&request, 0, sizeof(request));
> + ? ? ? ? ? ? ? request.type = PTP_REQUEST_EXTTS;
> + ? ? ? ? ? ? ? request.index = 0;
> + ? ? ? ? ? ? ? request.flags = PTP_ENABLE_FEATURE;
> + ? ? ? ? ? ? ? if (ioctl(fd, PTP_FEATURE_REQUEST, &request)) {
> + ? ? ? ? ? ? ? ? ? ? ? perror("PTP_FEATURE_REQUEST");
> + ? ? ? ? ? ? ? ? ? ? ? extts = 0;
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? puts("set timer okay");
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? for (; extts; extts--) {
> + ? ? ? ? ? ? ? ? ? ? ? cnt = read(fd, &event, sizeof(event));
> + ? ? ? ? ? ? ? ? ? ? ? if (cnt != sizeof(event)) {
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? perror("read");
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? ? ? ? ? printf("event index %d at %ld.%09ld\n", event.index,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?event.ts.tv_sec, event.ts.tv_nsec);
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? /* Disable the feature again. */
> + ? ? ? ? ? ? ? request.flags = 0;
> + ? ? ? ? ? ? ? if (ioctl(fd, PTP_FEATURE_REQUEST, &request)) {
> + ? ? ? ? ? ? ? ? ? ? ? perror("PTP_FEATURE_REQUEST");
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (oneshot) {
> + ? ? ? ? ? ? ? install_handler(SIGALRM, handle_alarm);
> + ? ? ? ? ? ? ? memset(&timer, 0, sizeof(timer));
> + ? ? ? ? ? ? ? timer.signum = SIGALRM;
> + ? ? ? ? ? ? ? timer.tsp.it_value.tv_sec = oneshot;
> + ? ? ? ? ? ? ? if (ioctl(fd, PTP_CLOCK_SETTIMER, &timer)) {
> + ? ? ? ? ? ? ? ? ? ? ? perror("PTP_CLOCK_SETTIMER");
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? puts("set timer okay");
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? pause();
> + ? ? ? }
> +
> + ? ? ? if (periodic) {
> + ? ? ? ? ? ? ? install_handler(SIGALRM, handle_alarm);
> + ? ? ? ? ? ? ? memset(&timer, 0, sizeof(timer));
> + ? ? ? ? ? ? ? timer.signum = SIGALRM;
> + ? ? ? ? ? ? ? timer.tsp.it_value.tv_sec = periodic;
> + ? ? ? ? ? ? ? timer.tsp.it_interval.tv_sec = periodic;
> + ? ? ? ? ? ? ? if (ioctl(fd, PTP_CLOCK_SETTIMER, &timer)) {
> + ? ? ? ? ? ? ? ? ? ? ? perror("PTP_CLOCK_SETTIMER");
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? puts("set timer okay");
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? while (1) {
> + ? ? ? ? ? ? ? ? ? ? ? pause();
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? close(fd);
> + ? ? ? return 0;
> +}
> diff --git a/Documentation/ptp/testptp.mk b/Documentation/ptp/testptp.mk
> new file mode 100644
> index 0000000..4ef2d97
> --- /dev/null
> +++ b/Documentation/ptp/testptp.mk
> @@ -0,0 +1,33 @@
> +# PTP 1588 clock support - User space test program
> +#
> +# Copyright (C) 2010 OMICRON electronics GmbH
> +#
> +# ?This program is free software; you can redistribute it and/or modify
> +# ?it under the terms of the GNU General Public License as published by
> +# ?the Free Software Foundation; either version 2 of the License, or
> +# ?(at your option) any later version.
> +#
> +# ?This program is distributed in the hope that it will be useful,
> +# ?but WITHOUT ANY WARRANTY; without even the implied warranty of
> +# ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> +# ?GNU General Public License for more details.
> +#
> +# ?You should have received a copy of the GNU General Public License
> +# ?along with this program; if not, write to the Free Software
> +# ?Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> +
> +CC ? ? ? ?= $(CROSS_COMPILE)gcc
> +INC ? ? ? = -I$(KBUILD_OUTPUT)/usr/include
> +CFLAGS ? ?= -Wall $(INC)
> +LDLIBS ? ?= -lrt
> +PROGS ? ? = testptp
> +
> +all: $(PROGS)
> +
> +testptp: testptp.o
> +
> +clean:
> + ? ? ? rm -f testptp.o
> +
> +distclean: clean
> + ? ? ? rm -f $(PROGS)
> diff --git a/drivers/Kconfig b/drivers/Kconfig
> index a2b902f..774fbd7 100644
> --- a/drivers/Kconfig
> +++ b/drivers/Kconfig
> @@ -52,6 +52,8 @@ source "drivers/spi/Kconfig"
>
> ?source "drivers/pps/Kconfig"
>
> +source "drivers/ptp/Kconfig"
> +
> ?source "drivers/gpio/Kconfig"
>
> ?source "drivers/w1/Kconfig"
> diff --git a/drivers/Makefile b/drivers/Makefile
> index 91874e0..6d12b48 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -76,6 +76,7 @@ obj-$(CONFIG_I2O) ? ? ? ? ? ? += message/
> ?obj-$(CONFIG_RTC_LIB) ? ? ? ? ?+= rtc/
> ?obj-y ? ? ? ? ? ? ? ? ? ? ? ? ?+= i2c/ media/
> ?obj-$(CONFIG_PPS) ? ? ? ? ? ? ?+= pps/
> +obj-$(CONFIG_PTP_1588_CLOCK) ? += ptp/
> ?obj-$(CONFIG_W1) ? ? ? ? ? ? ? += w1/
> ?obj-$(CONFIG_POWER_SUPPLY) ? ? += power/
> ?obj-$(CONFIG_HWMON) ? ? ? ? ? ?+= hwmon/
> diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
> new file mode 100644
> index 0000000..c80a25b
> --- /dev/null
> +++ b/drivers/ptp/Kconfig
> @@ -0,0 +1,26 @@
> +#
> +# PTP clock support configuration
> +#
> +
> +menu "PTP clock support"
> +
> +config PTP_1588_CLOCK
> + ? ? ? tristate "PTP clock support"
> + ? ? ? depends on EXPERIMENTAL
> + ? ? ? help
> + ? ? ? ? The IEEE 1588 standard defines a method to precisely
> + ? ? ? ? synchronize distributed clocks over Ethernet networks. The
> + ? ? ? ? standard defines a Precision Time Protocol (PTP), which can
> + ? ? ? ? be used to achieve synchronization within a few dozen
> + ? ? ? ? microseconds. In addition, with the help of special hardware
> + ? ? ? ? time stamping units, it can be possible to achieve
> + ? ? ? ? synchronization to within a few hundred nanoseconds.
> +
> + ? ? ? ? This driver adds support for PTP clocks as character
> + ? ? ? ? devices. If you want to use a PTP clock, then you should
> + ? ? ? ? also enable at least one clock driver as well.
> +
> + ? ? ? ? To compile this driver as a module, choose M here: the module
> + ? ? ? ? will be called ptp_clock.
> +
> +endmenu
> diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
> new file mode 100644
> index 0000000..b86695c
> --- /dev/null
> +++ b/drivers/ptp/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# Makefile for PTP 1588 clock support.
> +#
> +
> +obj-$(CONFIG_PTP_1588_CLOCK) ? ? ? ? ? += ptp_clock.o
> diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c
> new file mode 100644
> index 0000000..4753bf3
> --- /dev/null
> +++ b/drivers/ptp/ptp_clock.c
> @@ -0,0 +1,514 @@
> +/*
> + * PTP 1588 clock support
> + *
> + * Partially adapted from the Linux PPS driver.
> + *
> + * Copyright (C) 2010 OMICRON electronics GmbH
> + *
> + * ?This program is free software; you can redistribute it and/or modify
> + * ?it under the terms of the GNU General Public License as published by
> + * ?the Free Software Foundation; either version 2 of the License, or
> + * ?(at your option) any later version.
> + *
> + * ?This program is distributed in the hope that it will be useful,
> + * ?but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * ?GNU General Public License for more details.
> + *
> + * ?You should have received a copy of the GNU General Public License
> + * ?along with this program; if not, write to the Free Software
> + * ?Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +#include <linux/bitops.h>
> +#include <linux/cdev.h>
> +#include <linux/device.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/module.h>
> +#include <linux/poll.h>
> +#include <linux/sched.h>
> +#include <linux/slab.h>
> +#include <linux/uaccess.h>
> +
> +#include <linux/ptp_clock_kernel.h>
> +#include <linux/ptp_clock.h>
> +
> +#define PTP_MAX_ALARMS 4
> +#define PTP_MAX_CLOCKS BITS_PER_LONG
> +#define PTP_MAX_TIMESTAMPS 128
> +
> +struct alarm {
> + ? ? ? struct pid *pid;
> + ? ? ? int sig;
> +};
> +
> +struct timestamp_event_queue {
> + ? ? ? struct ptp_extts_event buf[PTP_MAX_TIMESTAMPS];
> + ? ? ? int head;
> + ? ? ? int tail;
> + ? ? ? int overflow;
> +};
> +
> +struct ptp_clock {
> + ? ? ? struct list_head list;
> + ? ? ? struct cdev cdev;
> + ? ? ? struct device *dev;
> + ? ? ? struct ptp_clock_info *info;
> + ? ? ? dev_t devid;
> + ? ? ? int index; /* index into clocks.map, also the minor number */
> +
> + ? ? ? struct alarm alarm[PTP_MAX_ALARMS];
> + ? ? ? struct mutex alarm_mux; /* one process at a time setting an alarm */
> +
> + ? ? ? struct timestamp_event_queue tsevq; /* simple fifo for time stamps */
> + ? ? ? struct mutex tsevq_mux; /* one process at a time reading the fifo */
> + ? ? ? wait_queue_head_t tsev_wq;
> +};
> +
> +/* private globals */
> +
> +static const struct file_operations ptp_fops;
> +static dev_t ptp_devt;
> +static struct class *ptp_class;
> +
> +static struct {
> + ? ? ? struct list_head list;
> + ? ? ? DECLARE_BITMAP(map, PTP_MAX_CLOCKS);
> +} clocks;
> +static DEFINE_SPINLOCK(clocks_lock); /* protects 'clocks' */
> +
> +/* time stamp event queue operations */
> +
> +static inline int queue_cnt(struct timestamp_event_queue *q)
> +{
> + ? ? ? int cnt = q->tail - q->head;
> + ? ? ? return cnt < 0 ? PTP_MAX_TIMESTAMPS + cnt : cnt;
> +}
> +
> +static inline int queue_free(struct timestamp_event_queue *q)
> +{
> + ? ? ? return PTP_MAX_TIMESTAMPS - queue_cnt(q) - 1;
> +}
> +
> +static void enqueue_external_timestamp(struct timestamp_event_queue *queue,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct ptp_clock_event *src)
> +{
> + ? ? ? struct ptp_extts_event *dst;
> + ? ? ? u32 remainder;
> +
> + ? ? ? dst = &queue->buf[queue->tail];
> +
> + ? ? ? dst->index = src->index;
> + ? ? ? dst->ts.tv_sec = div_u64_rem(src->timestamp, 1000000000, &remainder);
> + ? ? ? dst->ts.tv_nsec = remainder;
> +
> + ? ? ? if (!queue_free(queue))
> + ? ? ? ? ? ? ? queue->overflow++;
> +
> + ? ? ? queue->tail = (queue->tail + 1) % PTP_MAX_TIMESTAMPS;
> +}
> +
> +/* public interface */
> +
> +struct ptp_clock *ptp_clock_register(struct ptp_clock_info *info)
> +{
> + ? ? ? struct ptp_clock *ptp;
> + ? ? ? int err = 0, index, major = MAJOR(ptp_devt);
> + ? ? ? unsigned long flags;
> +
> + ? ? ? if (info->n_alarm > PTP_MAX_ALARMS)
> + ? ? ? ? ? ? ? return ERR_PTR(-EINVAL);
> +
> + ? ? ? /* Find a free clock slot and reserve it. */
> + ? ? ? err = -EBUSY;
> + ? ? ? spin_lock_irqsave(&clocks_lock, flags);
> + ? ? ? index = find_first_zero_bit(clocks.map, PTP_MAX_CLOCKS);
> + ? ? ? if (index < PTP_MAX_CLOCKS) {
> + ? ? ? ? ? ? ? set_bit(index, clocks.map);
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> + ? ? ? } else {
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> + ? ? ? ? ? ? ? goto no_clock;
> + ? ? ? }
> +
> + ? ? ? /* Initialize a clock structure. */
> + ? ? ? err = -ENOMEM;
> + ? ? ? ptp = kzalloc(sizeof(struct ptp_clock), GFP_KERNEL);
> + ? ? ? if (ptp == NULL)
> + ? ? ? ? ? ? ? goto no_memory;
> +
> + ? ? ? ptp->info = info;
> + ? ? ? ptp->devid = MKDEV(major, index);
> + ? ? ? ptp->index = index;
> + ? ? ? mutex_init(&ptp->alarm_mux);
> + ? ? ? mutex_init(&ptp->tsevq_mux);
> + ? ? ? init_waitqueue_head(&ptp->tsev_wq);
> +
> + ? ? ? /* Create a new device in our class. */
> + ? ? ? ptp->dev = device_create(ptp_class, NULL, ptp->devid, ptp,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"ptp_clock_%d", ptp->index);
> + ? ? ? if (IS_ERR(ptp->dev))
> + ? ? ? ? ? ? ? goto no_device;
> +
> + ? ? ? dev_set_drvdata(ptp->dev, ptp);
> +
> + ? ? ? /* Register a character device. */
> + ? ? ? cdev_init(&ptp->cdev, &ptp_fops);
> + ? ? ? ptp->cdev.owner = info->owner;
> + ? ? ? err = cdev_add(&ptp->cdev, ptp->devid, 1);
> + ? ? ? if (err)
> + ? ? ? ? ? ? ? goto no_cdev;
> +
> + ? ? ? /* Clock is ready, add it into the list. */
> + ? ? ? spin_lock_irqsave(&clocks_lock, flags);
> + ? ? ? list_add(&ptp->list, &clocks.list);
> + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> +
> + ? ? ? return ptp;
> +
> +no_cdev:
> + ? ? ? device_destroy(ptp_class, ptp->devid);
> +no_device:
> + ? ? ? mutex_destroy(&ptp->alarm_mux);
> + ? ? ? mutex_destroy(&ptp->tsevq_mux);
> + ? ? ? kfree(ptp);
> +no_memory:
> + ? ? ? spin_lock_irqsave(&clocks_lock, flags);
> + ? ? ? clear_bit(index, clocks.map);
> + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> +no_clock:
> + ? ? ? return ERR_PTR(err);
> +}
> +EXPORT_SYMBOL(ptp_clock_register);
> +
> +int ptp_clock_unregister(struct ptp_clock *ptp)
> +{
> + ? ? ? unsigned long flags;
> +
> + ? ? ? /* Release the clock's resources. */
> + ? ? ? cdev_del(&ptp->cdev);
> + ? ? ? device_destroy(ptp_class, ptp->devid);
> + ? ? ? mutex_destroy(&ptp->alarm_mux);
> + ? ? ? mutex_destroy(&ptp->tsevq_mux);
> +
> + ? ? ? /* Remove the clock from the list. */
> + ? ? ? spin_lock_irqsave(&clocks_lock, flags);
> + ? ? ? list_del(&ptp->list);
> + ? ? ? clear_bit(ptp->index, clocks.map);
> + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> +
> + ? ? ? kfree(ptp);
> +
> + ? ? ? return 0;
> +}
> +EXPORT_SYMBOL(ptp_clock_unregister);
> +
> +void ptp_clock_event(struct ptp_clock *ptp, struct ptp_clock_event *event)
> +{
> + ? ? ? switch (event->type) {
> +
> + ? ? ? case PTP_CLOCK_ALARM:
> + ? ? ? ? ? ? ? kill_pid(ptp->alarm[event->index].pid,
> + ? ? ? ? ? ? ? ? ? ? ? ?ptp->alarm[event->index].sig, 1);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_EXTTS:
> + ? ? ? ? ? ? ? enqueue_external_timestamp(&ptp->tsevq, event);
> + ? ? ? ? ? ? ? wake_up_interruptible(&ptp->tsev_wq);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_PPS:
> + ? ? ? ? ? ? ? break;
> + ? ? ? }
> +}
> +EXPORT_SYMBOL(ptp_clock_event);
> +
> +/* character device operations */
> +
> +static int ptp_ioctl(struct inode *node, struct file *fp,
> + ? ? ? ? ? ? ? ? ? ? unsigned int cmd, unsigned long arg)
> +{
> + ? ? ? struct ptp_clock_caps caps;
> + ? ? ? struct ptp_clock_request req;
> + ? ? ? struct ptp_clock_timer timer;
> + ? ? ? struct ptp_clock *ptp = fp->private_data;
> + ? ? ? struct ptp_clock_info *ops = ptp->info;
> + ? ? ? void *priv = ops->priv;
> + ? ? ? struct timespec ts;
> + ? ? ? int flags, index;
> + ? ? ? int err = 0;
> +
> + ? ? ? switch (cmd) {
> +
> + ? ? ? case PTP_CLOCK_APIVERS:
> + ? ? ? ? ? ? ? err = put_user(PTP_CLOCK_VERSION, (u32 __user *)arg);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_ADJFREQ:
> + ? ? ? ? ? ? ? if (!capable(CAP_SYS_TIME))
> + ? ? ? ? ? ? ? ? ? ? ? return -EPERM;
> + ? ? ? ? ? ? ? err = ops->adjfreq(priv, arg);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_ADJTIME:
> + ? ? ? ? ? ? ? if (!capable(CAP_SYS_TIME))
> + ? ? ? ? ? ? ? ? ? ? ? return -EPERM;
> + ? ? ? ? ? ? ? if (copy_from_user(&ts, (void __user *)arg, sizeof(ts)))
> + ? ? ? ? ? ? ? ? ? ? ? err = -EFAULT;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? err = ops->adjtime(priv, &ts);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_GETTIME:
> + ? ? ? ? ? ? ? err = ops->gettime(priv, &ts);
> + ? ? ? ? ? ? ? if (err)
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? err = copy_to_user((void __user *)arg, &ts, sizeof(ts));
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_SETTIME:
> + ? ? ? ? ? ? ? if (!capable(CAP_SYS_TIME))
> + ? ? ? ? ? ? ? ? ? ? ? return -EPERM;
> + ? ? ? ? ? ? ? if (copy_from_user(&ts, (void __user *)arg, sizeof(ts)))
> + ? ? ? ? ? ? ? ? ? ? ? err = -EFAULT;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? err = ops->settime(priv, &ts);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_GETCAPS:
> + ? ? ? ? ? ? ? memset(&caps, 0, sizeof(caps));
> + ? ? ? ? ? ? ? caps.max_adj = ptp->info->max_adj;
> + ? ? ? ? ? ? ? caps.n_alarm = ptp->info->n_alarm;
> + ? ? ? ? ? ? ? caps.n_ext_ts = ptp->info->n_ext_ts;
> + ? ? ? ? ? ? ? caps.n_per_out = ptp->info->n_per_out;
> + ? ? ? ? ? ? ? caps.pps = ptp->info->pps;
> + ? ? ? ? ? ? ? err = copy_to_user((void __user *)arg, &caps, sizeof(caps));
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_GETTIMER:
> + ? ? ? ? ? ? ? if (copy_from_user(&timer, (void __user *)arg, sizeof(timer))) {
> + ? ? ? ? ? ? ? ? ? ? ? err = -EFAULT;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? index = timer.alarm_index;
> + ? ? ? ? ? ? ? if (index < 0 || index >= ptp->info->n_alarm) {
> + ? ? ? ? ? ? ? ? ? ? ? err = -EINVAL;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? err = ops->gettimer(priv, index, &timer.tsp);
> + ? ? ? ? ? ? ? if (err)
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? err = copy_to_user((void __user *)arg, &timer, sizeof(timer));
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_SETTIMER:
> + ? ? ? ? ? ? ? if (copy_from_user(&timer, (void __user *)arg, sizeof(timer))) {
> + ? ? ? ? ? ? ? ? ? ? ? err = -EFAULT;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? index = timer.alarm_index;
> + ? ? ? ? ? ? ? if (index < 0 || index >= ptp->info->n_alarm) {
> + ? ? ? ? ? ? ? ? ? ? ? err = -EINVAL;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? if (!valid_signal(timer.signum))
> + ? ? ? ? ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? ? ? ? ? flags = timer.flags;
> + ? ? ? ? ? ? ? if (flags & (flags != TIMER_ABSTIME)) {
> + ? ? ? ? ? ? ? ? ? ? ? err = -EINVAL;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? if (mutex_lock_interruptible(&ptp->alarm_mux))
> + ? ? ? ? ? ? ? ? ? ? ? return -ERESTARTSYS;
> +
> + ? ? ? ? ? ? ? if (ptp->alarm[index].pid)
> + ? ? ? ? ? ? ? ? ? ? ? put_pid(ptp->alarm[index].pid);
> +
> + ? ? ? ? ? ? ? ptp->alarm[index].pid = get_pid(task_pid(current));
> + ? ? ? ? ? ? ? ptp->alarm[index].sig = timer.signum;
> + ? ? ? ? ? ? ? err = ops->settimer(priv, index, flags, &timer.tsp);
> +
> + ? ? ? ? ? ? ? mutex_unlock(&ptp->alarm_mux);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_FEATURE_REQUEST:
> + ? ? ? ? ? ? ? if (copy_from_user(&req, (void __user *)arg, sizeof(req))) {
> + ? ? ? ? ? ? ? ? ? ? ? err = -EFAULT;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? switch (req.type) {
> + ? ? ? ? ? ? ? case PTP_REQUEST_EXTTS:
> + ? ? ? ? ? ? ? case PTP_REQUEST_PEROUT:
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case PTP_REQUEST_PPS:
> + ? ? ? ? ? ? ? ? ? ? ? if (!capable(CAP_SYS_TIME))
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? return -EPERM;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? default:
> + ? ? ? ? ? ? ? ? ? ? ? err = -EINVAL;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? if (err)
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? err = ops->enable(priv, &req,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? req.flags & PTP_ENABLE_FEATURE ? 1 : 0);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? default:
> + ? ? ? ? ? ? ? err = -ENOTTY;
> + ? ? ? ? ? ? ? break;
> + ? ? ? }
> + ? ? ? return err;
> +}
> +
> +static int ptp_open(struct inode *inode, struct file *fp)
> +{
> + ? ? ? struct ptp_clock *ptp;
> + ? ? ? ptp = container_of(inode->i_cdev, struct ptp_clock, cdev);
> +
> + ? ? ? fp->private_data = ptp;
> +
> + ? ? ? return 0;
> +}
> +
> +static unsigned int ptp_poll(struct file *fp, poll_table *wait)
> +{
> + ? ? ? struct ptp_clock *ptp = fp->private_data;
> +
> + ? ? ? poll_wait(fp, &ptp->tsev_wq, wait);
> +
> + ? ? ? return queue_cnt(&ptp->tsevq) ? POLLIN : 0;
> +}
> +
> +static ssize_t ptp_read(struct file *fp, char __user *buf,
> + ? ? ? ? ? ? ? ? ? ? ? size_t cnt, loff_t *off)
> +{
> + ? ? ? struct ptp_clock *ptp = fp->private_data;
> + ? ? ? struct timestamp_event_queue *queue = &ptp->tsevq;
> + ? ? ? struct ptp_extts_event *event;
> + ? ? ? size_t qcnt;
> +
> + ? ? ? if (mutex_lock_interruptible(&ptp->tsevq_mux))
> + ? ? ? ? ? ? ? return -ERESTARTSYS;
> +
> + ? ? ? cnt = cnt / sizeof(struct ptp_extts_event);
> +
> + ? ? ? if (wait_event_interruptible(ptp->tsev_wq,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(qcnt = queue_cnt(&ptp->tsevq)))) {
> + ? ? ? ? ? ? ? mutex_unlock(&ptp->tsevq_mux);
> + ? ? ? ? ? ? ? return -ERESTARTSYS;
> + ? ? ? }
> +
> + ? ? ? if (cnt > qcnt)
> + ? ? ? ? ? ? ? cnt = qcnt;
> +
> + ? ? ? event = &queue->buf[queue->head];
> +
> + ? ? ? if (copy_to_user(buf, event, cnt * sizeof(struct ptp_extts_event))) {
> + ? ? ? ? ? ? ? mutex_unlock(&ptp->tsevq_mux);
> + ? ? ? ? ? ? ? return -EFAULT;
> + ? ? ? }
> + ? ? ? queue->head = (queue->head + cnt) % PTP_MAX_TIMESTAMPS;
> +
> + ? ? ? mutex_unlock(&ptp->tsevq_mux);
> +
> + ? ? ? return cnt * sizeof(struct ptp_extts_event);
> +}
> +
> +static int ptp_release(struct inode *inode, struct file *fp)
> +{
> + ? ? ? struct ptp_clock *ptp;
> + ? ? ? struct itimerspec ts = {
> + ? ? ? ? ? ? ? {0, 0}, {0, 0}
> + ? ? ? };
> + ? ? ? int i;
> +
> + ? ? ? ptp = container_of(inode->i_cdev, struct ptp_clock, cdev);
> +
> + ? ? ? for (i = 0; i < ptp->info->n_alarm; i++) {
> + ? ? ? ? ? ? ? if (ptp->alarm[i].pid) {
> + ? ? ? ? ? ? ? ? ? ? ? ptp->info->settimer(ptp->info->priv, i, 0, &ts);
> + ? ? ? ? ? ? ? ? ? ? ? put_pid(ptp->alarm[i].pid);
> + ? ? ? ? ? ? ? ? ? ? ? ptp->alarm[i].pid = NULL;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> + ? ? ? return 0;
> +}
> +
> +static const struct file_operations ptp_fops = {
> + ? ? ? .owner ? ? ? ? ?= THIS_MODULE,
> + ? ? ? .ioctl ? ? ? ? ?= ptp_ioctl,
> + ? ? ? .open ? ? ? ? ? = ptp_open,
> + ? ? ? .poll ? ? ? ? ? = ptp_poll,
> + ? ? ? .read ? ? ? ? ? = ptp_read,
> + ? ? ? .release ? ? ? ?= ptp_release,
> +};
> +
> +/* sysfs */
> +
> +static ssize_t ptp_show_status(struct device *dev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct device_attribute *attr, char *buf)
> +{
> + ? ? ? struct ptp_clock *ptp = dev_get_drvdata(dev);
> + ? ? ? return sprintf(buf,
> + ? ? ? ? ? ? ? ? ? ? ?"maximum adjustment: ?%d\n"
> + ? ? ? ? ? ? ? ? ? ? ?"programmable alarms: %d\n"
> + ? ? ? ? ? ? ? ? ? ? ?"external timestamps: %d\n"
> + ? ? ? ? ? ? ? ? ? ? ?"periodic outputs: ? ?%d\n"
> + ? ? ? ? ? ? ? ? ? ? ?"has pps: ? ? ? ? ? ? %d\n"
> + ? ? ? ? ? ? ? ? ? ? ?"device index: ? ? ? ?%d\n",
> + ? ? ? ? ? ? ? ? ? ? ?ptp->info->max_adj,
> + ? ? ? ? ? ? ? ? ? ? ?ptp->info->n_alarm,
> + ? ? ? ? ? ? ? ? ? ? ?ptp->info->n_ext_ts,
> + ? ? ? ? ? ? ? ? ? ? ?ptp->info->n_per_out,
> + ? ? ? ? ? ? ? ? ? ? ?ptp->info->pps,
> + ? ? ? ? ? ? ? ? ? ? ?ptp->index);
> +}
> +
> +struct device_attribute ptp_attrs[] = {
> + ? ? ? __ATTR(capabilities, S_IRUGO, ptp_show_status, NULL),
> + ? ? ? __ATTR_NULL,
> +};
> +
> +/* module operations */
> +
> +static void __exit ptp_exit(void)
> +{
> + ? ? ? class_destroy(ptp_class);
> + ? ? ? unregister_chrdev_region(ptp_devt, PTP_MAX_CLOCKS);
> +}
> +
> +static int __init ptp_init(void)
> +{
> + ? ? ? int err;
> +
> + ? ? ? INIT_LIST_HEAD(&clocks.list);
> +
> + ? ? ? ptp_class = class_create(THIS_MODULE, "ptp");
> + ? ? ? if (!ptp_class) {
> + ? ? ? ? ? ? ? printk(KERN_ERR "ptp: failed to allocate class\n");
> + ? ? ? ? ? ? ? return -ENOMEM;
> + ? ? ? }
> + ? ? ? ptp_class->dev_attrs = ptp_attrs;
> +
> + ? ? ? err = alloc_chrdev_region(&ptp_devt, 0, PTP_MAX_CLOCKS, "ptp");
> + ? ? ? if (err < 0) {
> + ? ? ? ? ? ? ? printk(KERN_ERR "ptp: failed to allocate char device region\n");
> + ? ? ? ? ? ? ? goto no_region;
> + ? ? ? }
> +
> + ? ? ? pr_info("PTP clock support registered\n");
> + ? ? ? return 0;
> +
> +no_region:
> + ? ? ? class_destroy(ptp_class);
> + ? ? ? return err;
> +}
> +
> +subsys_initcall(ptp_init);
> +module_exit(ptp_exit);
> +
> +MODULE_AUTHOR("Richard Cochran <richard.cochran at omicron.at>");
> +MODULE_DESCRIPTION("PTP clocks support");
> +MODULE_LICENSE("GPL");
> diff --git a/include/linux/Kbuild b/include/linux/Kbuild
> index 2fc8e14..9959fe4 100644
> --- a/include/linux/Kbuild
> +++ b/include/linux/Kbuild
> @@ -140,6 +140,7 @@ header-y += pkt_sched.h
> ?header-y += posix_types.h
> ?header-y += ppdev.h
> ?header-y += prctl.h
> +header-y += ptp_clock.h
> ?header-y += qnxtypes.h
> ?header-y += qnx4_fs.h
> ?header-y += radeonfb.h
> diff --git a/include/linux/ptp_clock.h b/include/linux/ptp_clock.h
> new file mode 100644
> index 0000000..5a509c5
> --- /dev/null
> +++ b/include/linux/ptp_clock.h
> @@ -0,0 +1,79 @@
> +/*
> + * PTP 1588 clock support - user space interface
> + *
> + * Copyright (C) 2010 OMICRON electronics GmbH
> + *
> + * ?This program is free software; you can redistribute it and/or modify
> + * ?it under the terms of the GNU General Public License as published by
> + * ?the Free Software Foundation; either version 2 of the License, or
> + * ?(at your option) any later version.
> + *
> + * ?This program is distributed in the hope that it will be useful,
> + * ?but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * ?GNU General Public License for more details.
> + *
> + * ?You should have received a copy of the GNU General Public License
> + * ?along with this program; if not, write to the Free Software
> + * ?Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#ifndef _PTP_CLOCK_H_
> +#define _PTP_CLOCK_H_
> +
> +#include <linux/ioctl.h>
> +#include <linux/types.h>
> +
> +#define PTP_ENABLE_FEATURE (1<<0)
> +#define PTP_RISING_EDGE ? ?(1<<1)
> +#define PTP_FALLING_EDGE ? (1<<2)
> +
> +enum ptp_request_types {
> + ? ? ? PTP_REQUEST_EXTTS,
> + ? ? ? PTP_REQUEST_PEROUT,
> + ? ? ? PTP_REQUEST_PPS,
> +};
> +
> +struct ptp_clock_caps {
> + ? ? ? __s32 max_adj; /* Maximum frequency adjustment, parts per billon. */
> + ? ? ? int n_alarm; ? /* Number of programmable alarms. */
> + ? ? ? int n_ext_ts; ?/* Number of external time stamp channels. */
> + ? ? ? int n_per_out; /* Number of programmable periodic signals. */
> + ? ? ? int pps; ? ? ? /* Whether the clock supports a PPS callback. */
> +};
> +
> +struct ptp_clock_timer {
> + ? ? ? int alarm_index; ? ? ? /* Which alarm to query or configure. */
> + ? ? ? int signum; ? ? ? ? ? ?/* Requested signal. */
> + ? ? ? int flags; ? ? ? ? ? ? /* Zero or TIMER_ABSTIME, see TIMER_SETTIME(2) */
> + ? ? ? struct itimerspec tsp; /* See TIMER_SETTIME(2) */
> +};
> +
> +struct ptp_clock_request {
> + ? ? ? int type; ?/* One of the ptp_request_types enumeration values. */
> + ? ? ? int index; /* Which channel to configure. */
> + ? ? ? struct timespec ts; /* For period signals, the desired period. */
> + ? ? ? int flags; /* Bit field for PTP_ENABLE_FEATURE or other flags. */
> +};
> +
> +struct ptp_extts_event {
> + ? ? ? int index;
> + ? ? ? struct timespec ts;
> +};
> +
> +#define PTP_CLOCK_VERSION 0x00000001
> +
> +#define PTP_CLK_MAGIC '='
> +
> +#define PTP_CLOCK_APIVERS _IOR (PTP_CLK_MAGIC, 1, __u32)
> +#define PTP_CLOCK_ADJFREQ _IO ?(PTP_CLK_MAGIC, 2)
> +#define PTP_CLOCK_ADJTIME _IOW (PTP_CLK_MAGIC, 3, struct timespec)
> +#define PTP_CLOCK_GETTIME _IOR (PTP_CLK_MAGIC, 4, struct timespec)
> +#define PTP_CLOCK_SETTIME _IOW (PTP_CLK_MAGIC, 5, struct timespec)
> +
> +#define PTP_CLOCK_GETCAPS ? _IOR ?(PTP_CLK_MAGIC, 6, struct ptp_clock_caps)
> +#define PTP_CLOCK_GETTIMER ?_IOWR (PTP_CLK_MAGIC, 7, struct ptp_clock_timer)
> +#define PTP_CLOCK_SETTIMER ?_IOW ?(PTP_CLK_MAGIC, 8, struct ptp_clock_timer)
> +#define PTP_FEATURE_REQUEST _IOW ?(PTP_CLK_MAGIC, 9, struct ptp_clock_request)
> +
> +#endif
> diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h
> new file mode 100644
> index 0000000..d6cc158
> --- /dev/null
> +++ b/include/linux/ptp_clock_kernel.h
> @@ -0,0 +1,137 @@
> +/*
> + * PTP 1588 clock support
> + *
> + * Copyright (C) 2010 OMICRON electronics GmbH
> + *
> + * ?This program is free software; you can redistribute it and/or modify
> + * ?it under the terms of the GNU General Public License as published by
> + * ?the Free Software Foundation; either version 2 of the License, or
> + * ?(at your option) any later version.
> + *
> + * ?This program is distributed in the hope that it will be useful,
> + * ?but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * ?GNU General Public License for more details.
> + *
> + * ?You should have received a copy of the GNU General Public License
> + * ?along with this program; if not, write to the Free Software
> + * ?Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#ifndef _PTP_CLOCK_KERNEL_H_
> +#define _PTP_CLOCK_KERNEL_H_
> +
> +#include <linux/ptp_clock.h>
> +
> +/**
> + * struct ptp_clock_info - decribes a PTP hardware clock
> + *
> + * @owner: ? ? The clock driver should set to THIS_MODULE.
> + * @name: ? ? ?A short name to identify the clock.
> + * @max_adj: ? The maximum possible frequency adjustment, in parts per billon.
> + * @n_alarm: ? The number of programmable alarms.
> + * @n_ext_ts: ?The number of external time stamp channels.
> + * @n_per_out: The number of programmable periodic signals.
> + * @pps: ? ? ? Indicates whether the clock supports a PPS callback.
> + * @priv: ? ? ?Passed to the clock operations, for the driver's private use.
> + *
> + * clock operations
> + *
> + * @adjfreq: ?Adjusts the frequency of the hardware clock.
> + * ? ? ? ? ? ?parameter delta: Desired period change in parts per billion.
> + *
> + * @adjtime: ?Shifts the time of the hardware clock.
> + * ? ? ? ? ? ?parameter ts: Desired change in seconds and nanoseconds.
> + *
> + * @gettime: ?Reads the current time from the hardware clock.
> + * ? ? ? ? ? ?parameter ts: Holds the result.
> + *
> + * @settime: ?Set the current time on the hardware clock.
> + * ? ? ? ? ? ?parameter ts: Time value to set.
> + *
> + * @gettimer: Reads the time remaining from the given timer.
> + * ? ? ? ? ? ?parameter index: Which alarm to query.
> + * ? ? ? ? ? ?parameter ts: Holds the result.
> + *
> + * @settimer: Arms the given timer for periodic or one shot operation.
> + * ? ? ? ? ? ?parameter index: Which alarm to set.
> + * ? ? ? ? ? ?parameter abs: TIMER_ABSTIME, or zero for relative timer.
> + * ? ? ? ? ? ?parameter ts: Alarm time and period to set.
> + *
> + * @enable: ? Request driver to enable or disable an ancillary feature.
> + * ? ? ? ? ? ?parameter request: Desired resource to enable or disable.
> + * ? ? ? ? ? ?parameter on: Caller passes one to enable or zero to disable.
> + *
> + * The callbacks must all return zero on success, non-zero otherwise.
> + */
> +
> +struct ptp_clock_info {
> + ? ? ? struct module *owner;
> + ? ? ? char name[16];
> + ? ? ? s32 max_adj;
> + ? ? ? int n_alarm;
> + ? ? ? int n_ext_ts;
> + ? ? ? int n_per_out;
> + ? ? ? int pps;
> + ? ? ? void *priv;
> + ? ? ? int (*adjfreq)(void *priv, s32 delta);
> + ? ? ? int (*adjtime)(void *priv, struct timespec *ts);
> + ? ? ? int (*gettime)(void *priv, struct timespec *ts);
> + ? ? ? int (*settime)(void *priv, struct timespec *ts);
> + ? ? ? int (*gettimer)(void *priv, int index, struct itimerspec *ts);
> + ? ? ? int (*settimer)(void *priv, int index, int abs, struct itimerspec *ts);
> + ? ? ? int (*enable)(void *priv, struct ptp_clock_request *request, int on);
> +};
> +
> +struct ptp_clock;
> +
> +/**
> + * ptp_clock_register() - register a PTP hardware clock driver
> + *
> + * @info: ?Structure describing the new clock.
> + */
> +
> +extern struct ptp_clock *ptp_clock_register(struct ptp_clock_info *info);
> +
> +/**
> + * ptp_clock_unregister() - unregister a PTP hardware clock driver
> + *
> + * @ptp: ?The clock to remove from service.
> + */
> +
> +extern int ptp_clock_unregister(struct ptp_clock *ptp);
> +
> +
> +enum ptp_clock_events {
> + ? ? ? PTP_CLOCK_ALARM,
> + ? ? ? PTP_CLOCK_EXTTS,
> + ? ? ? PTP_CLOCK_PPS,
> +};
> +
> +/**
> + * struct ptp_clock_event - decribes a PTP hardware clock event
> + *
> + * @type: ?One of the ptp_clock_events enumeration values.
> + * @index: Identifies the source of the event.
> + * @timestamp: When the event occured.
> + */
> +
> +struct ptp_clock_event {
> + ? ? ? int type;
> + ? ? ? int index;
> + ? ? ? u64 timestamp;
> +};
> +
> +/**
> + * ptp_clock_event() - notify the PTP layer about an event
> + *
> + * This function should only be called from interrupt context.
> + *
> + * @ptp: ? ?The clock obtained from ptp_clock_register().
> + * @event: ?Message structure describing the event.
> + */
> +
> +extern void ptp_clock_event(struct ptp_clock *ptp,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? struct ptp_clock_event *event);
> +
> +#endif
> --
> 1.6.3.3
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From richardcochran at gmail.com  Tue Jun 15 13:08:06 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Tue, 15 Jun 2010 19:08:06 +0200
Subject: [PATCH 05/12] phylib: Allow reading and writing a mii bus from
	atomic context.
In-Reply-To: <AANLkTikeae2t4KmnawOCo2LqfSI57BKjNnUayY09DfEC@mail.gmail.com>
References: <cover.1276615626.git.richard.cochran@omicron.at>
	<1b8219e7d7993d0e8204b94e959477e3007534ce.1276615626.git.richard.cochran@omicron.at>
	<AANLkTikeae2t4KmnawOCo2LqfSI57BKjNnUayY09DfEC@mail.gmail.com>
Message-ID: <20100615170806.GB10668@riccoc20.at.omicron.at>

On Tue, Jun 15, 2010 at 10:43:08AM -0600, Grant Likely wrote:
> On Tue, Jun 15, 2010 at 10:08 AM, Richard Cochran
> <richardcochran at gmail.com> wrote:
> > In order to support hardware time stamping from a PHY, it is necessary to
> > read from the PHY while running in_interrupt(). This patch allows a mii
> > bus to operate in an atomic context. An mii_bus driver may declare itself
> > capable for this mode. Drivers which do not do this will remain with the
> > default that bus operations may sleep.
> >
> > Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
> 
> Last I checked, the MDIO bus is very slow.  Is this really a good
> idea?  How much latency does MDIO access have on the hardware you are
> working with?

Yes, MDIO access is slow, and it can vary (eg bit banging
implementations). It clear that getting PHY timestamps is costly, but
for applications that want PTP synchronization, one is willing to pay
the price.

> I also don't like the idea of taking a spin lock during MDIO
> operations, and the dual locking mode in the core code.

Originally, the phylib used a spinlock for this. It was replaced with
a mutex in 35b5f6b1a82b5c586e0b24c711dc6ba944e88ef1 in order to
accommodate mdio busses that may need to sleep. So, keeping the option
to use a spinlock is similar to the previous implementation.

> I'd rather see separate atomic context hooks that doesn't obtain the
> mutex under the assumption that the caller has already done so.  If
> the bus doesn't support atomic access, then it won't implement the
> hooks and the core code should return an error.
> 
> I've cc'd Thomas Gleixner.  He might have a better idea about how to
> implement what you're trying to do.

Okay, I'm open to suggestions...

Thanks,

Richard


From grant.likely at secretlab.ca  Tue Jun 15 13:20:41 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 15 Jun 2010 11:20:41 -0600
Subject: [PATCH 10/12] ptp: Added a clock that uses the eTSEC found on the
	MPC85xx.
In-Reply-To: <041faf3cb6ecbedf8f3ff2104914f91d2a24fc4d.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<041faf3cb6ecbedf8f3ff2104914f91d2a24fc4d.1276615626.git.richard.cochran@omicron.at>
Message-ID: <AANLkTikFc15j-Qhw9M2CnKLKq58Wi1xD7E2dtVNsVgeA@mail.gmail.com>

On Tue, Jun 15, 2010 at 10:10 AM, Richard Cochran
<richardcochran at gmail.com> wrote:
> The eTSEC includes a PTP clock with quite a few features. This patch adds
> support for the basic clock adjustment functions, plus two external time
> stamps and one alarm.
>
> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>

Hi Richard,

comments below...

> ---
> ?Documentation/powerpc/dts-bindings/fsl/tsec.txt | ? 54 +++
> ?arch/powerpc/boot/dts/mpc8313erdb.dts ? ? ? ? ? | ? 13 +
> ?arch/powerpc/boot/dts/p2020ds.dts ? ? ? ? ? ? ? | ? 13 +
> ?arch/powerpc/boot/dts/p2020rdb.dts ? ? ? ? ? ? ?| ? 13 +
> ?drivers/net/Makefile ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?1 +
> ?drivers/net/gianfar_ptp.c ? ? ? ? ? ? ? ? ? ? ? | ?518 +++++++++++++++++++++++
> ?drivers/net/gianfar_ptp_reg.h ? ? ? ? ? ? ? ? ? | ?113 +++++

Is this header file used by anything other than gianfar_ptp.c?  If
not, then roll the two files together.

> ?drivers/ptp/Kconfig ? ? ? ? ? ? ? ? ? ? ? ? ? ? | ? 13 +
> ?8 files changed, 738 insertions(+), 0 deletions(-)
> ?create mode 100644 drivers/net/gianfar_ptp.c
> ?create mode 100644 drivers/net/gianfar_ptp_reg.h
>
> diff --git a/Documentation/powerpc/dts-bindings/fsl/tsec.txt b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
> index edb7ae1..14577e9 100644
> --- a/Documentation/powerpc/dts-bindings/fsl/tsec.txt
> +++ b/Documentation/powerpc/dts-bindings/fsl/tsec.txt
> @@ -74,3 +74,57 @@ Example:
> ? ? ? ? ? ? ? ?interrupt-parent = <&mpic>;
> ? ? ? ? ? ? ? ?phy-handle = <&phy0>
> ? ? ? ?};
> +
> +* Gianfar PTP clock nodes
> +
> +General Properties:
> +
> + ?- compatible ? Should be "fsl,etsec-ptp"
> + ?- reg ? ? ? ? ?Offset and length of the register set for the device
> + ?- interrupts ? There should be at least two interrupts. Some devices
> + ? ? ? ? ? ? ? ? have as many as four PTP related interrupts.
> +
> +Clock Properties:
> +
> + ?- tclk_period ?Timer reference clock period in nanoseconds.
> + ?- tmr_prsc ? ? Prescaler, divides the output clock.
> + ?- tmr_add ? ? ?Frequency compensation value.

Use dash ('-') not underscore ('_') in property names.

> + ?- cksel ? ? ? ?0= external clock, 1= eTSEC system clock, 3= RTC clock input.
> + ? ? ? ? ? ? ? ? Currently the driver only supports choice "1".

If you encode this value as a string, then it will be friendly for humans too.

> + ?- tmr_fiper1 ? Fixed interval period pulse generator.
> + ?- tmr_fiper2 ? Fixed interval period pulse generator.

I could use more explication here.  Is this a divider value?
Computers are good at making calculations, and the driver can obtain
the clock frequency supplied to the device.  It may be more useful to
specify here the desired frequency rather than the divider.  Certainly
more human-friendly too.

> +
> + ?These properties set the operational parameters for the PTP
> + ?clock. You must choose these carefully for the clock to work right.
> + ?Here is how to figure good values:
> +
> + ?TimerOsc ? ? = system clock ? ? ? ? ? ? ? MHz
> + ?tclk_period ?= desired clock period ? ? ? nanoseconds
> + ?NominalFreq ?= 1000 / tclk_period ? ? ? ? MHz
> + ?FreqDivRatio = TimerOsc / NominalFreq ? ? (must be greater that 1.0)
> + ?tmr_add ? ? ?= ceil(2^32 / FreqDivRatio)
> + ?OutputClock ?= NominalFreq / tmr_prsc ? ? MHz
> + ?PulseWidth ? = 1 / OutputClock ? ? ? ? ? ?microseconds
> + ?FiperFreq1 ? = desired frequency in Hz
> + ?FiperDiv1 ? ?= 1000000 * OutputClock / FiperFreq1
> + ?tmr_fiper1 ? = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
> +
> + ?The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
> + ?driver expects that tmr_fiper1 will be correctly set to produce a 1
> + ?Pulse Per Second (PPS) signal, since this will be offered to the PPS
> + ?subsystem to synchronize the Linux clock.
> +
> +Example:
> +
> + ? ? ? ptp_clock at 24E00 {
> + ? ? ? ? ? ? ? compatible = "fsl,etsec-ptp";
> + ? ? ? ? ? ? ? reg = <0x24E00 0xB0>;
> + ? ? ? ? ? ? ? interrupts = <12 0x8 13 0x8>;
> + ? ? ? ? ? ? ? interrupt-parent = < &ipic >;
> + ? ? ? ? ? ? ? tclk_period = <10>;
> + ? ? ? ? ? ? ? tmr_prsc ? ?= <100>;
> + ? ? ? ? ? ? ? tmr_add ? ? = <0x999999A4>;
> + ? ? ? ? ? ? ? cksel ? ? ? = <0x1>;
> + ? ? ? ? ? ? ? tmr_fiper1 ?= <0x3B9AC9F6>;
> + ? ? ? ? ? ? ? tmr_fiper2 ?= <0x00018696>;
> + ? ? ? };
> diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
> index 183f2aa..0526384 100644
> --- a/arch/powerpc/boot/dts/mpc8313erdb.dts
> +++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
> @@ -208,6 +208,19 @@
> ? ? ? ? ? ? ? ? ? ? ? ?sleep = <&pmc 0x00300000>;
> ? ? ? ? ? ? ? ?};
>
> + ? ? ? ? ? ? ? ptp_clock at 24E00 {
> + ? ? ? ? ? ? ? ? ? ? ? compatible = "fsl,etsec-ptp";
> + ? ? ? ? ? ? ? ? ? ? ? reg = <0x24E00 0xB0>;
> + ? ? ? ? ? ? ? ? ? ? ? interrupts = <12 0x8 13 0x8>;
> + ? ? ? ? ? ? ? ? ? ? ? interrupt-parent = < &ipic >;
> + ? ? ? ? ? ? ? ? ? ? ? tclk_period = <10>;
> + ? ? ? ? ? ? ? ? ? ? ? tmr_prsc ? ?= <100>;
> + ? ? ? ? ? ? ? ? ? ? ? tmr_add ? ? = <0x999999A4>;
> + ? ? ? ? ? ? ? ? ? ? ? cksel ? ? ? = <0x1>;
> + ? ? ? ? ? ? ? ? ? ? ? tmr_fiper1 ?= <0x3B9AC9F6>;
> + ? ? ? ? ? ? ? ? ? ? ? tmr_fiper2 ?= <0x00018696>;
> + ? ? ? ? ? ? ? };
> +
> ? ? ? ? ? ? ? ?enet0: ethernet at 24000 {
> ? ? ? ? ? ? ? ? ? ? ? ?#address-cells = <1>;
> ? ? ? ? ? ? ? ? ? ? ? ?#size-cells = <1>;
> diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
> index 1101914..ae5dc4d 100644
> --- a/arch/powerpc/boot/dts/p2020ds.dts
> +++ b/arch/powerpc/boot/dts/p2020ds.dts
> @@ -336,6 +336,19 @@
> ? ? ? ? ? ? ? ? ? ? ? ?phy_type = "ulpi";
> ? ? ? ? ? ? ? ?};
>
> + ? ? ? ? ? ? ? ptp_clock at 24E00 {
> + ? ? ? ? ? ? ? ? ? ? ? compatible = "fsl,etsec-ptp";
> + ? ? ? ? ? ? ? ? ? ? ? reg = <0x24E00 0xB0>;
> + ? ? ? ? ? ? ? ? ? ? ? interrupts = <68 2 69 2 70 2>;
> + ? ? ? ? ? ? ? ? ? ? ? interrupt-parent = < &mpic >;
> + ? ? ? ? ? ? ? ? ? ? ? tclk_period = <5>;
> + ? ? ? ? ? ? ? ? ? ? ? tmr_prsc = <200>;
> + ? ? ? ? ? ? ? ? ? ? ? tmr_add = <0xCCCCCCCD>;
> + ? ? ? ? ? ? ? ? ? ? ? cksel = <1>;
> + ? ? ? ? ? ? ? ? ? ? ? tmr_fiper1 = <0x3B9AC9FB>;
> + ? ? ? ? ? ? ? ? ? ? ? tmr_fiper2 = <0x0001869B>;
> + ? ? ? ? ? ? ? };
> +
> ? ? ? ? ? ? ? ?enet0: ethernet at 24000 {
> ? ? ? ? ? ? ? ? ? ? ? ?#address-cells = <1>;
> ? ? ? ? ? ? ? ? ? ? ? ?#size-cells = <1>;
> diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
> index da4cb0d..133945c 100644
> --- a/arch/powerpc/boot/dts/p2020rdb.dts
> +++ b/arch/powerpc/boot/dts/p2020rdb.dts
> @@ -396,6 +396,19 @@
> ? ? ? ? ? ? ? ? ? ? ? ?phy_type = "ulpi";
> ? ? ? ? ? ? ? ?};
>
> + ? ? ? ? ? ? ? ptp_clock at 24E00 {
> + ? ? ? ? ? ? ? ? ? ? ? compatible = "fsl,etsec-ptp";
> + ? ? ? ? ? ? ? ? ? ? ? reg = <0x24E00 0xB0>;
> + ? ? ? ? ? ? ? ? ? ? ? interrupts = <68 2 69 2 70 2>;
> + ? ? ? ? ? ? ? ? ? ? ? interrupt-parent = < &mpic >;
> + ? ? ? ? ? ? ? ? ? ? ? tclk_period = <5>;
> + ? ? ? ? ? ? ? ? ? ? ? tmr_prsc = <200>;
> + ? ? ? ? ? ? ? ? ? ? ? tmr_add = <0xCCCCCCCD>;
> + ? ? ? ? ? ? ? ? ? ? ? cksel = <1>;
> + ? ? ? ? ? ? ? ? ? ? ? tmr_fiper1 = <0x3B9AC9FB>;
> + ? ? ? ? ? ? ? ? ? ? ? tmr_fiper2 = <0x0001869B>;
> + ? ? ? ? ? ? ? };
> +
> ? ? ? ? ? ? ? ?enet0: ethernet at 24000 {
> ? ? ? ? ? ? ? ? ? ? ? ?#address-cells = <1>;
> ? ? ? ? ? ? ? ? ? ? ? ?#size-cells = <1>;
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 0a0512a..389c0d9 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -28,6 +28,7 @@ obj-$(CONFIG_ATL2) += atlx/
> ?obj-$(CONFIG_ATL1E) += atl1e/
> ?obj-$(CONFIG_ATL1C) += atl1c/
> ?obj-$(CONFIG_GIANFAR) += gianfar_driver.o
> +obj-$(CONFIG_PTP_1588_CLOCK_GIANFAR) += gianfar_ptp.o
> ?obj-$(CONFIG_TEHUTI) += tehuti.o
> ?obj-$(CONFIG_ENIC) += enic/
> ?obj-$(CONFIG_JME) += jme.o
> diff --git a/drivers/net/gianfar_ptp.c b/drivers/net/gianfar_ptp.c
> new file mode 100644
> index 0000000..0991652
> --- /dev/null
> +++ b/drivers/net/gianfar_ptp.c
> @@ -0,0 +1,518 @@
> +/*
> + * PTP 1588 clock using the eTSEC
> + *
> + * Copyright (C) 2010 OMICRON electronics GmbH
> + *
> + * ?This program is free software; you can redistribute it and/or modify
> + * ?it under the terms of the GNU General Public License as published by
> + * ?the Free Software Foundation; either version 2 of the License, or
> + * ?(at your option) any later version.
> + *
> + * ?This program is distributed in the hope that it will be useful,
> + * ?but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * ?GNU General Public License for more details.
> + *
> + * ?You should have received a copy of the GNU General Public License
> + * ?along with this program; if not, write to the Free Software
> + * ?Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +#include <linux/device.h>
> +#include <linux/hrtimer.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_platform.h>
> +#include <linux/timex.h>
> +#include <linux/io.h>
> +
> +#include <linux/ptp_clock_kernel.h>
> +
> +#include "gianfar_ptp_reg.h"
> +#include "gianfar.h"
> +
> +#define DRIVER ? ? ? ? "gianfar_ptp"
> +#define N_ALARM ? ? ? ? ? ? ? ?1 /* first alarm is used internally to reset fipers */
> +#define N_EXT_TS ? ? ? 2
> +#define REG_SIZE ? ? ? sizeof(struct gianfar_ptp_registers)
> +
> +struct etsects {
> + ? ? ? struct gianfar_ptp_registers *regs;
> + ? ? ? struct ptp_clock *clock;
> + ? ? ? int irq;
> + ? ? ? u64 alarm_interval; /* for periodic alarm */
> + ? ? ? u64 alarm_value;
> + ? ? ? u32 tclk_period; ?/* nanoseconds */
> + ? ? ? u32 tmr_prsc;
> + ? ? ? u32 tmr_add;
> + ? ? ? u32 cksel;
> + ? ? ? u32 tmr_fiper1;
> + ? ? ? u32 tmr_fiper2;
> +};
> +
> +/* Private globals */
> +static struct etsects the_clock;

Will there ever be multiple instances of this device?

> +DEFINE_SPINLOCK(register_lock);
> +
> +/*
> + * Register access functions
> + */
> +
> +static u64 tmr_cnt_read(struct etsects *etsects)
> +{
> + ? ? ? u64 ns;
> + ? ? ? u32 lo, hi;
> +
> + ? ? ? lo = gfar_read(&etsects->regs->tmr_cnt_l);
> + ? ? ? hi = gfar_read(&etsects->regs->tmr_cnt_h);
> + ? ? ? ns = ((u64) hi) << 32;
> + ? ? ? ns |= lo;
> + ? ? ? return ns;
> +}
> +
> +static void tmr_cnt_write(struct etsects *etsects, u64 ns)
> +{
> + ? ? ? u32 hi = ns >> 32;
> + ? ? ? u32 lo = ns & 0xffffffff;
> +
> + ? ? ? gfar_write(&etsects->regs->tmr_cnt_l, lo);
> + ? ? ? gfar_write(&etsects->regs->tmr_cnt_h, hi);
> +}
> +
> +static void set_alarm(struct etsects *etsects)
> +{
> + ? ? ? u64 ns;
> + ? ? ? u32 lo, hi;
> +
> + ? ? ? ns = tmr_cnt_read(etsects) + 1500000000ULL;
> + ? ? ? ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
> + ? ? ? ns -= etsects->tclk_period;
> + ? ? ? hi = ns >> 32;
> + ? ? ? lo = ns & 0xffffffff;
> + ? ? ? gfar_write(&etsects->regs->tmr_alarm1_l, lo);
> + ? ? ? gfar_write(&etsects->regs->tmr_alarm1_h, hi);
> +}
> +
> +static void set_fipers(struct etsects *etsects)
> +{
> + ? ? ? u32 tmr_ctrl = gfar_read(&etsects->regs->tmr_ctrl);
> +
> + ? ? ? gfar_write(&etsects->regs->tmr_ctrl, ? tmr_ctrl & (~TE));
> + ? ? ? gfar_write(&etsects->regs->tmr_prsc, ? etsects->tmr_prsc);
> + ? ? ? gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
> + ? ? ? gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
> + ? ? ? set_alarm(etsects);
> + ? ? ? gfar_write(&etsects->regs->tmr_ctrl, ? tmr_ctrl|TE);
> +}
> +
> +/*
> + * Interrupt service routine
> + */
> +
> +static irqreturn_t isr(int irq, void *priv)
> +{
> + ? ? ? struct etsects *etsects = priv;
> + ? ? ? struct ptp_clock_event event;
> + ? ? ? u64 ns;
> + ? ? ? u32 ack = 0, lo, hi, mask, val;
> +
> + ? ? ? val = gfar_read(&etsects->regs->tmr_tevent);
> +
> + ? ? ? if (val & ETS1) {
> + ? ? ? ? ? ? ? ack |= ETS1;
> + ? ? ? ? ? ? ? hi = gfar_read(&etsects->regs->tmr_etts1_h);
> + ? ? ? ? ? ? ? lo = gfar_read(&etsects->regs->tmr_etts1_l);
> + ? ? ? ? ? ? ? event.type = PTP_CLOCK_EXTTS;
> + ? ? ? ? ? ? ? event.index = 0;
> + ? ? ? ? ? ? ? event.timestamp = ((u64) hi) << 32;
> + ? ? ? ? ? ? ? event.timestamp |= lo;
> + ? ? ? ? ? ? ? ptp_clock_event(etsects->clock, &event);
> + ? ? ? }
> +
> + ? ? ? if (val & ETS2) {
> + ? ? ? ? ? ? ? ack |= ETS2;
> + ? ? ? ? ? ? ? hi = gfar_read(&etsects->regs->tmr_etts2_h);
> + ? ? ? ? ? ? ? lo = gfar_read(&etsects->regs->tmr_etts2_l);
> + ? ? ? ? ? ? ? event.type = PTP_CLOCK_EXTTS;
> + ? ? ? ? ? ? ? event.index = 1;
> + ? ? ? ? ? ? ? event.timestamp = ((u64) hi) << 32;
> + ? ? ? ? ? ? ? event.timestamp |= lo;
> + ? ? ? ? ? ? ? ptp_clock_event(etsects->clock, &event);
> + ? ? ? }
> +
> + ? ? ? if (val & ALM2) {
> + ? ? ? ? ? ? ? ack |= ALM2;
> + ? ? ? ? ? ? ? if (etsects->alarm_value) {
> + ? ? ? ? ? ? ? ? ? ? ? event.type = PTP_CLOCK_ALARM;
> + ? ? ? ? ? ? ? ? ? ? ? event.index = 0;
> + ? ? ? ? ? ? ? ? ? ? ? event.timestamp = etsects->alarm_value;
> + ? ? ? ? ? ? ? ? ? ? ? ptp_clock_event(etsects->clock, &event);
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? if (etsects->alarm_interval) {
> + ? ? ? ? ? ? ? ? ? ? ? ns = etsects->alarm_value + etsects->alarm_interval;
> + ? ? ? ? ? ? ? ? ? ? ? hi = ns >> 32;
> + ? ? ? ? ? ? ? ? ? ? ? lo = ns & 0xffffffff;
> + ? ? ? ? ? ? ? ? ? ? ? spin_lock(&register_lock);
> + ? ? ? ? ? ? ? ? ? ? ? gfar_write(&etsects->regs->tmr_alarm2_l, lo);
> + ? ? ? ? ? ? ? ? ? ? ? gfar_write(&etsects->regs->tmr_alarm2_h, hi);
> + ? ? ? ? ? ? ? ? ? ? ? spin_unlock(&register_lock);
> + ? ? ? ? ? ? ? ? ? ? ? etsects->alarm_value = ns;
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? gfar_write(&etsects->regs->tmr_tevent, ALM2);
> + ? ? ? ? ? ? ? ? ? ? ? spin_lock(&register_lock);
> + ? ? ? ? ? ? ? ? ? ? ? mask = gfar_read(&etsects->regs->tmr_temask);
> + ? ? ? ? ? ? ? ? ? ? ? mask &= ~ALM2EN;
> + ? ? ? ? ? ? ? ? ? ? ? gfar_write(&etsects->regs->tmr_temask, mask);
> + ? ? ? ? ? ? ? ? ? ? ? spin_unlock(&register_lock);
> + ? ? ? ? ? ? ? ? ? ? ? etsects->alarm_value = 0;
> + ? ? ? ? ? ? ? ? ? ? ? etsects->alarm_interval = 0;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (ack) {
> + ? ? ? ? ? ? ? gfar_write(&etsects->regs->tmr_tevent, ack);
> + ? ? ? ? ? ? ? return IRQ_HANDLED;
> + ? ? ? } else
> + ? ? ? ? ? ? ? return IRQ_NONE;
> +}
> +
> +/*
> + * PTP clock operations
> + */
> +
> +static int ptp_gianfar_adjfreq(void *priv, s32 ppb)
> +{
> + ? ? ? u64 adj;
> + ? ? ? u32 diff, tmr_add;
> + ? ? ? int neg_adj = 0;
> + ? ? ? struct etsects *etsects = priv;
> +
> + ? ? ? if (!ppb)
> + ? ? ? ? ? ? ? return 0;
> +
> + ? ? ? if (ppb < 0) {
> + ? ? ? ? ? ? ? neg_adj = 1;
> + ? ? ? ? ? ? ? ppb = -ppb;
> + ? ? ? }
> + ? ? ? tmr_add = etsects->tmr_add;
> + ? ? ? adj = tmr_add;
> + ? ? ? adj *= ppb;
> + ? ? ? diff = div_u64(adj, 1000000000ULL);
> +
> + ? ? ? tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
> +
> + ? ? ? gfar_write(&etsects->regs->tmr_add, tmr_add);
> +
> + ? ? ? return 0;
> +}
> +
> +static int ptp_gianfar_adjtime(void *priv, struct timespec *ts)
> +{
> + ? ? ? s64 delta, now;
> + ? ? ? unsigned long flags;
> + ? ? ? struct etsects *etsects = priv;
> +
> + ? ? ? delta = 1000000000LL * ts->tv_sec;
> + ? ? ? delta += ts->tv_nsec;
> +
> + ? ? ? spin_lock_irqsave(&register_lock, flags);
> +
> + ? ? ? now = tmr_cnt_read(etsects);
> + ? ? ? now += delta;
> + ? ? ? tmr_cnt_write(etsects, now);
> +
> + ? ? ? spin_unlock_irqrestore(&register_lock, flags);
> +
> + ? ? ? set_fipers(etsects);
> +
> + ? ? ? return 0;
> +}
> +
> +static int ptp_gianfar_gettime(void *priv, struct timespec *ts)
> +{
> + ? ? ? u64 ns;
> + ? ? ? u32 remainder;
> + ? ? ? unsigned long flags;
> + ? ? ? struct etsects *etsects = priv;
> +
> + ? ? ? spin_lock_irqsave(&register_lock, flags);
> +
> + ? ? ? ns = tmr_cnt_read(etsects);
> +
> + ? ? ? spin_unlock_irqrestore(&register_lock, flags);
> +
> + ? ? ? ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
> + ? ? ? ts->tv_nsec = remainder;
> + ? ? ? return 0;
> +}
> +
> +static int ptp_gianfar_settime(void *priv, struct timespec *ts)
> +{
> + ? ? ? u64 ns;
> + ? ? ? unsigned long flags;
> + ? ? ? struct etsects *etsects = priv;
> +
> + ? ? ? ns = ts->tv_sec * 1000000000ULL;
> + ? ? ? ns += ts->tv_nsec;
> +
> + ? ? ? spin_lock_irqsave(&register_lock, flags);
> +
> + ? ? ? tmr_cnt_write(etsects, ns);
> + ? ? ? set_fipers(etsects);
> +
> + ? ? ? spin_unlock_irqrestore(&register_lock, flags);
> +
> + ? ? ? return 0;
> +}
> +
> +static int ptp_gianfar_gettimer(void *priv, int index, struct itimerspec *ts)
> +{
> + ? ? ? u64 now, ns;
> + ? ? ? u32 remainder;
> + ? ? ? unsigned long flags;
> + ? ? ? struct etsects *etsects = priv;
> +
> + ? ? ? ns = etsects->alarm_interval;
> +
> + ? ? ? ts->it_interval.tv_sec = div_u64_rem(ns, 1000000000, &remainder);
> + ? ? ? ts->it_interval.tv_nsec = remainder;
> +
> + ? ? ? spin_lock_irqsave(&register_lock, flags);
> + ? ? ? now = tmr_cnt_read(etsects);
> + ? ? ? spin_unlock_irqrestore(&register_lock, flags);
> +
> + ? ? ? ns = etsects->alarm_value - now;
> +
> + ? ? ? ts->it_value.tv_sec = div_u64_rem(ns, 1000000000, &remainder);
> + ? ? ? ts->it_value.tv_nsec = remainder;
> +
> + ? ? ? return 0;
> +}
> +
> +static int ptp_gianfar_settimer(void *p, int i, int abs, struct itimerspec *ts)
> +{
> + ? ? ? u64 ns;
> + ? ? ? u32 lo, hi, mask;
> + ? ? ? unsigned long flags;
> + ? ? ? struct etsects *etsects = p;
> +
> + ? ? ? ns = ts->it_interval.tv_sec * 1000000000ULL;
> + ? ? ? ns += ts->it_interval.tv_nsec;
> +
> + ? ? ? etsects->alarm_interval = ns;
> +
> + ? ? ? ns = ts->it_value.tv_sec * 1000000000ULL;
> + ? ? ? ns += ts->it_value.tv_nsec;
> +
> + ? ? ? if (!ns) {
> + ? ? ? ? ? ? ? /* Cancel the timer. */
> + ? ? ? ? ? ? ? etsects->alarm_value = 0;
> + ? ? ? ? ? ? ? etsects->alarm_interval = 0;
> + ? ? ? ? ? ? ? return 0;
> + ? ? ? }
> +
> + ? ? ? if (!abs) {
> + ? ? ? ? ? ? ? spin_lock_irqsave(&register_lock, flags);
> + ? ? ? ? ? ? ? ns += tmr_cnt_read(etsects);
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(&register_lock, flags);
> + ? ? ? }
> +
> + ? ? ? etsects->alarm_value = ns;
> +
> + ? ? ? hi = ns >> 32;
> + ? ? ? lo = ns & 0xffffffff;
> +
> + ? ? ? spin_lock_irqsave(&register_lock, flags);
> +
> + ? ? ? gfar_write(&etsects->regs->tmr_alarm2_l, lo);
> + ? ? ? gfar_write(&etsects->regs->tmr_alarm2_h, hi);
> +
> + ? ? ? mask = gfar_read(&etsects->regs->tmr_temask);
> + ? ? ? mask |= ALM2EN;
> + ? ? ? gfar_write(&etsects->regs->tmr_temask, mask);
> +
> + ? ? ? spin_unlock_irqrestore(&register_lock, flags);
> +
> + ? ? ? return 0;
> +}
> +
> +static int ptp_gianfar_enable(void *priv, struct ptp_clock_request *rq, int on)
> +{
> + ? ? ? struct etsects *etsects = priv;
> + ? ? ? unsigned long flags;
> + ? ? ? u32 bit, mask;
> +
> + ? ? ? switch (rq->type) {
> + ? ? ? case PTP_REQUEST_EXTTS:
> + ? ? ? ? ? ? ? switch (rq->index) {
> + ? ? ? ? ? ? ? case 0:
> + ? ? ? ? ? ? ? ? ? ? ? bit = ETS1EN;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case 1:
> + ? ? ? ? ? ? ? ? ? ? ? bit = ETS2EN;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? default:
> + ? ? ? ? ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? spin_lock_irqsave(&register_lock, flags);
> + ? ? ? ? ? ? ? if (on) {
> + ? ? ? ? ? ? ? ? ? ? ? mask = gfar_read(&etsects->regs->tmr_temask);
> + ? ? ? ? ? ? ? ? ? ? ? mask |= bit;
> + ? ? ? ? ? ? ? ? ? ? ? gfar_write(&etsects->regs->tmr_temask, mask);
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? mask = gfar_read(&etsects->regs->tmr_temask);
> + ? ? ? ? ? ? ? ? ? ? ? mask &= ~bit;
> + ? ? ? ? ? ? ? ? ? ? ? gfar_write(&etsects->regs->tmr_temask, mask);
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(&register_lock, flags);
> + ? ? ? ? ? ? ? return 0;
> + ? ? ? }
> +
> + ? ? ? return -EOPNOTSUPP;
> +}
> +
> +static struct ptp_clock_info ptp_gianfar_caps = {
> + ? ? ? .owner ? ? ? ? ?= THIS_MODULE,
> + ? ? ? .name ? ? ? ? ? = "gianfar clock",
> + ? ? ? .max_adj ? ? ? ?= 512000,
> + ? ? ? .n_alarm ? ? ? ?= N_ALARM,
> + ? ? ? .n_ext_ts ? ? ? = N_EXT_TS,
> + ? ? ? .n_per_out ? ? ?= 0,
> + ? ? ? .pps ? ? ? ? ? ?= 0,
> + ? ? ? .priv ? ? ? ? ? = &the_clock,
> + ? ? ? .adjfreq ? ? ? ?= ptp_gianfar_adjfreq,
> + ? ? ? .adjtime ? ? ? ?= ptp_gianfar_adjtime,
> + ? ? ? .gettime ? ? ? ?= ptp_gianfar_gettime,
> + ? ? ? .settime ? ? ? ?= ptp_gianfar_settime,
> + ? ? ? .gettimer ? ? ? = ptp_gianfar_gettimer,
> + ? ? ? .settimer ? ? ? = ptp_gianfar_settimer,
> + ? ? ? .enable ? ? ? ? = ptp_gianfar_enable,
> +};
> +
> +/* OF device tree */
> +
> +static int get_of_u32(struct device_node *node, char *str, u32 *val)
> +{
> + ? ? ? int plen;
> + ? ? ? const u32 *prop = of_get_property(node, str, &plen);
> +
> + ? ? ? if (!prop || plen != sizeof(*prop))
> + ? ? ? ? ? ? ? return -1;
> + ? ? ? *val = *prop;
> + ? ? ? return 0;
> +}
> +
> +static int gianfar_ptp_probe(struct of_device *dev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ?const struct of_device_id *match)
> +{
> + ? ? ? u64 addr, size;
> + ? ? ? struct device_node *node = dev->dev.of_node;
> + ? ? ? struct etsects *etsects = &the_clock;
> + ? ? ? struct timespec now;
> + ? ? ? phys_addr_t reg_addr;
> + ? ? ? unsigned long reg_size;
> + ? ? ? u32 tmr_ctrl;
> +
> + ? ? ? if (get_of_u32(node, "tclk_period", &etsects->tclk_period) ||
> + ? ? ? ? ? get_of_u32(node, "tmr_prsc", &etsects->tmr_prsc) ||
> + ? ? ? ? ? get_of_u32(node, "tmr_add", &etsects->tmr_add) ||
> + ? ? ? ? ? get_of_u32(node, "cksel", &etsects->cksel) ||
> + ? ? ? ? ? get_of_u32(node, "tmr_fiper1", &etsects->tmr_fiper1) ||
> + ? ? ? ? ? get_of_u32(node, "tmr_fiper2", &etsects->tmr_fiper2)) {
> + ? ? ? ? ? ? ? pr_err("device tree node missing required elements\n");
> + ? ? ? ? ? ? ? return -ENODEV;
> + ? ? ? }
> +
> + ? ? ? etsects->irq = irq_of_parse_and_map(node, 0);
> +
> + ? ? ? if (etsects->irq == NO_IRQ) {
> + ? ? ? ? ? ? ? pr_err("irq not in device tree\n");
> + ? ? ? ? ? ? ? return -ENODEV;
> + ? ? ? }
> + ? ? ? if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
> + ? ? ? ? ? ? ? pr_err("request_irq failed\n");
> + ? ? ? ? ? ? ? return -ENODEV;
> + ? ? ? }
> +
> + ? ? ? addr = of_translate_address(node, of_get_address(node, 0, &size, NULL));
> + ? ? ? reg_addr = addr;
> + ? ? ? reg_size = size;
> + ? ? ? if (reg_size < REG_SIZE) {
> + ? ? ? ? ? ? ? pr_warning("device tree reg range %lu too small\n", reg_size);
> + ? ? ? ? ? ? ? reg_size = REG_SIZE;
> + ? ? ? }
> + ? ? ? etsects->regs = ioremap(reg_addr, reg_size);
> + ? ? ? if (!etsects->regs) {
> + ? ? ? ? ? ? ? pr_err("ioremap ptp registers failed\n");
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }

Consider of_iomap(), it will simplify the code a bit.

> +
> + ? ? ? tmr_ctrl =
> + ? ? ? ? (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
> + ? ? ? ? (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
> +
> + ? ? ? getnstimeofday(&now);
> + ? ? ? ptp_gianfar_settime(etsects, &now);
> +
> + ? ? ? gfar_write(&etsects->regs->tmr_ctrl, ? tmr_ctrl);
> + ? ? ? gfar_write(&etsects->regs->tmr_add, ? ?etsects->tmr_add);
> + ? ? ? gfar_write(&etsects->regs->tmr_prsc, ? etsects->tmr_prsc);
> + ? ? ? gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
> + ? ? ? gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
> + ? ? ? set_alarm(etsects);
> + ? ? ? gfar_write(&etsects->regs->tmr_ctrl, ? tmr_ctrl|FS|RTPE|TE);
> +
> + ? ? ? etsects->clock = ptp_clock_register(&ptp_gianfar_caps);
> +
> + ? ? ? return IS_ERR(etsects->clock) ? PTR_ERR(etsects->clock) : 0;
> +}
> +
> +static int gianfar_ptp_remove(struct of_device *dev)
> +{
> + ? ? ? gfar_write(&the_clock.regs->tmr_temask, 0);
> + ? ? ? gfar_write(&the_clock.regs->tmr_ctrl, ? 0);
> +
> + ? ? ? ptp_clock_unregister(the_clock.clock);
> +
> + ? ? ? free_irq(the_clock.irq, &the_clock);
> +
> + ? ? ? iounmap(the_clock.regs);
> +
> + ? ? ? return 0;
> +}
> +
> +static struct of_device_id match_table[] = {
> + ? ? ? { .compatible = "fsl,etsec-ptp" },
> + ? ? ? {},
> +};
> +
> +static struct of_platform_driver gianfar_ptp_driver = {
> + ? ? ? .driver = {
> + ? ? ? ? ? ? ? .name ? ? ? ? ? = "gianfar_ptp",
> + ? ? ? ? ? ? ? .of_match_table = match_table,
> + ? ? ? ? ? ? ? .owner ? ? ? ? ?= THIS_MODULE,
> + ? ? ? },
> + ? ? ? .probe ? ? ? = gianfar_ptp_probe,
> + ? ? ? .remove ? ? ?= gianfar_ptp_remove,
> +};
> +
> +/* module operations */
> +
> +static void __exit ptp_gianfar_exit(void)
> +{
> + ? ? ? of_unregister_platform_driver(&gianfar_ptp_driver);
> +}
> +
> +static int __init ptp_gianfar_init(void)
> +{
> + ? ? ? return of_register_platform_driver(&gianfar_ptp_driver);
> +}
> +
> +module_init(ptp_gianfar_init);

Move ptp_gianfar_exit() definition here so it is immediately before
the module_exit() line.

> +module_exit(ptp_gianfar_exit);
> +
> +MODULE_AUTHOR("Richard Cochran <richard.cochran at omicron.at>");
> +MODULE_DESCRIPTION("PTP clock using the eTSEC");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/net/gianfar_ptp_reg.h b/drivers/net/gianfar_ptp_reg.h
> new file mode 100644
> index 0000000..95e171f
> --- /dev/null
> +++ b/drivers/net/gianfar_ptp_reg.h
> @@ -0,0 +1,113 @@
> +/* gianfar_ptp_reg.h
> + * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
> + *
> + * PTP 1588 clock using the gianfar eTSEC
> + *
> + * Copyright (C) 2010 OMICRON electronics GmbH
> + *
> + * ?This program is free software; you can redistribute it and/or modify
> + * ?it under the terms of the GNU General Public License as published by
> + * ?the Free Software Foundation; either version 2 of the License, or
> + * ?(at your option) any later version.
> + *
> + * ?This program is distributed in the hope that it will be useful,
> + * ?but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * ?GNU General Public License for more details.
> + *
> + * ?You should have received a copy of the GNU General Public License
> + * ?along with this program; if not, write to the Free Software
> + * ?Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +#ifndef _GIANFAR_PTP_REG_H_
> +#define _GIANFAR_PTP_REG_H_
> +
> +struct gianfar_ptp_registers {
> + ? ? ? u32 tmr_ctrl; ? ? /* Timer control register */
> + ? ? ? u32 tmr_tevent; ? /* Timestamp event register */
> + ? ? ? u32 tmr_temask; ? /* Timer event mask register */
> + ? ? ? u32 tmr_pevent; ? /* Timestamp event register */
> + ? ? ? u32 tmr_pemask; ? /* Timer event mask register */
> + ? ? ? u32 tmr_stat; ? ? /* Timestamp status register */
> + ? ? ? u32 tmr_cnt_h; ? ?/* Timer counter high register */
> + ? ? ? u32 tmr_cnt_l; ? ?/* Timer counter low register */
> + ? ? ? u32 tmr_add; ? ? ?/* Timer drift compensation addend register */
> + ? ? ? u32 tmr_acc; ? ? ?/* Timer accumulator register */
> + ? ? ? u32 tmr_prsc; ? ? /* Timer prescale */
> + ? ? ? u8 ?res1[4];
> + ? ? ? u32 tmroff_h; ? ? /* Timer offset high */
> + ? ? ? u32 tmroff_l; ? ? /* Timer offset low */
> + ? ? ? u8 ?res2[8];
> + ? ? ? u32 tmr_alarm1_h; /* Timer alarm 1 high register */
> + ? ? ? u32 tmr_alarm1_l; /* Timer alarm 1 high register */
> + ? ? ? u32 tmr_alarm2_h; /* Timer alarm 2 high register */
> + ? ? ? u32 tmr_alarm2_l; /* Timer alarm 2 high register */
> + ? ? ? u8 ?res3[48];
> + ? ? ? u32 tmr_fiper1; ? /* Timer fixed period interval */
> + ? ? ? u32 tmr_fiper2; ? /* Timer fixed period interval */
> + ? ? ? u32 tmr_fiper3; ? /* Timer fixed period interval */
> + ? ? ? u8 ?res4[20];
> + ? ? ? u32 tmr_etts1_h; ?/* Timestamp of general purpose external trigger */
> + ? ? ? u32 tmr_etts1_l; ?/* Timestamp of general purpose external trigger */
> + ? ? ? u32 tmr_etts2_h; ?/* Timestamp of general purpose external trigger */
> + ? ? ? u32 tmr_etts2_l; ?/* Timestamp of general purpose external trigger */
> +};
> +
> +/* Bit definitions for the TMR_CTRL register */
> +#define ALM1P ? ? ? ? ? ? ? ? (1<<31) /* Alarm1 output polarity */
> +#define ALM2P ? ? ? ? ? ? ? ? (1<<30) /* Alarm2 output polarity */
> +#define FS ? ? ? ? ? ? ? ? ? ?(1<<28) /* FIPER start indication */
> +#define PP1L ? ? ? ? ? ? ? ? ?(1<<27) /* Fiper1 pulse loopback mode enabled. */
> +#define PP2L ? ? ? ? ? ? ? ? ?(1<<26) /* Fiper2 pulse loopback mode enabled. */
> +#define TCLK_PERIOD_SHIFT ? ? (16) /* 1588 timer reference clock period. */
> +#define TCLK_PERIOD_MASK ? ? ?(0x3ff)
> +#define RTPE ? ? ? ? ? ? ? ? ?(1<<15) /* Record Tx Timestamp to PAL Enable. */
> +#define FRD ? ? ? ? ? ? ? ? ? (1<<14) /* FIPER Realignment Disable */
> +#define ESFDP ? ? ? ? ? ? ? ? (1<<11) /* External Tx/Rx SFD Polarity. */
> +#define ESFDE ? ? ? ? ? ? ? ? (1<<10) /* External Tx/Rx SFD Enable. */
> +#define ETEP2 ? ? ? ? ? ? ? ? (1<<9) /* External trigger 2 edge polarity */
> +#define ETEP1 ? ? ? ? ? ? ? ? (1<<8) /* External trigger 1 edge polarity */
> +#define COPH ? ? ? ? ? ? ? ? ?(1<<7) /* Generated clock (TSEC_1588_GCLK) output phase. */
> +#define CIPH ? ? ? ? ? ? ? ? ?(1<<6) /* External oscillator input clock phase. */
> +#define TMSR ? ? ? ? ? ? ? ? ?(1<<5) /* Timer soft reset. When enabled, it resets all the timer registers and state machines. */
> +#define BYP ? ? ? ? ? ? ? ? ? (1<<3) /* Bypass drift compensated clock */
> +#define TE ? ? ? ? ? ? ? ? ? ?(1<<2) /* 1588 timer enable. If not enabled, all the timer registers and state machines are disabled. */
> +#define CKSEL_SHIFT ? ? ? ? ? (0) /* 1588 Timer reference clock source select. */
> +#define CKSEL_MASK ? ? ? ? ? ?(0x3)
> +
> +/* Bit definitions for the TMR_TEVENT register */
> +#define ETS2 ? ? ? ? ? ? ? ? ?(1<<25) /* External trigger 2 timestamp sampled */
> +#define ETS1 ? ? ? ? ? ? ? ? ?(1<<24) /* External trigger 1 timestamp sampled */
> +#define ALM2 ? ? ? ? ? ? ? ? ?(1<<17) /* Current time equaled alarm time register 2 */
> +#define ALM1 ? ? ? ? ? ? ? ? ?(1<<16) /* Current time equaled alarm time register 1 */
> +#define PP1 ? ? ? ? ? ? ? ? ? (1<<7) /* Indicates that a periodic pulse has been generated based on FIPER1 register */
> +#define PP2 ? ? ? ? ? ? ? ? ? (1<<6) /* Indicates that a periodic pulse has been generated based on FIPER2 register */
> +#define PP3 ? ? ? ? ? ? ? ? ? (1<<5) /* Indicates that a periodic pulse has been generated based on FIPER3 register */
> +
> +/* Bit definitions for the TMR_TEMASK register */
> +#define ETS2EN ? ? ? ? ? ? ? ?(1<<25) /* External trigger 2 timestamp sample event enable */
> +#define ETS1EN ? ? ? ? ? ? ? ?(1<<24) /* External trigger 1 timestamp sample event enable */
> +#define ALM2EN ? ? ? ? ? ? ? ?(1<<17) /* Timer ALM2 event enable */
> +#define ALM1EN ? ? ? ? ? ? ? ?(1<<16) /* Timer ALM1 event enable */
> +#define PP1EN ? ? ? ? ? ? ? ? (1<<7) /* Periodic pulse event 1 enable */
> +#define PP2EN ? ? ? ? ? ? ? ? (1<<6) /* Periodic pulse event 2 enable */
> +
> +/* Bit definitions for the TMR_PEVENT register */
> +#define TXP2 ? ? ? ? ? ? ? ? ?(1<<9) /* Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS2 register */
> +#define TXP1 ? ? ? ? ? ? ? ? ?(1<<8) /* Indicates that a PTP frame has been transmitted and its timestamp is stored in TXTS1 register */
> +#define RXP ? ? ? ? ? ? ? ? ? (1<<0) /* Indicates that a PTP frame has been received */
> +
> +/* Bit definitions for the TMR_PEMASK register */
> +#define TXP2EN ? ? ? ? ? ? ? ?(1<<9) /* Transmit PTP packet event 2 enable */
> +#define TXP1EN ? ? ? ? ? ? ? ?(1<<8) /* Transmit PTP packet event 1 enable */
> +#define RXPEN ? ? ? ? ? ? ? ? (1<<0) /* Receive PTP packet event enable */
> +
> +/* Bit definitions for the TMR_STAT register */
> +#define STAT_VEC_SHIFT ? ? ? ?(0) /* Timer general purpose status vector */
> +#define STAT_VEC_MASK ? ? ? ? (0x3f)
> +
> +/* Bit definitions for the TMR_PRSC register */
> +#define PRSC_OCK_SHIFT ? ? ? ?(0) /* Output clock division/prescale factor. */
> +#define PRSC_OCK_MASK ? ? ? ? (0xffff)
> +
> +#endif
> diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
> index 9390d44..3b7bd73 100644
> --- a/drivers/ptp/Kconfig
> +++ b/drivers/ptp/Kconfig
> @@ -35,4 +35,17 @@ config PTP_1588_CLOCK_LINUX
> ? ? ? ? ?To compile this driver as a module, choose M here: the module
> ? ? ? ? ?will be called ptp_linux.
>
> +config PTP_1588_CLOCK_GIANFAR
> + ? ? ? tristate "Freescale eTSEC as PTP clock"
> + ? ? ? depends on PTP_1588_CLOCK
> + ? ? ? depends on GIANFAR
> + ? ? ? help
> + ? ? ? ? This driver adds support for using the eTSEC as a PTP
> + ? ? ? ? clock. This clock is only useful if your PTP programs are
> + ? ? ? ? getting hardware time stamps on the PTP Ethernet packets
> + ? ? ? ? using the SO_TIMESTAMPING API.
> +
> + ? ? ? ? To compile this driver as a module, choose M here: the module
> + ? ? ? ? will be called gianfar_ptp.
> +
> ?endmenu
> --
> 1.6.3.3
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From clagix at gmail.com  Tue Jun 15 14:26:24 2010
From: clagix at gmail.com (Guido Classen)
Date: Tue, 15 Jun 2010 20:26:24 +0200
Subject: [PATCH] at91rm9200 static memory controller initialization
Message-ID: <AANLkTinIPD1tceqoONbpfDmvnJI7Q1F765kQQvMaqgPO@mail.gmail.com>

Hello mailing list,

This patch adds AT91RM9200 static memory controller initialization based
on a structure 'at91rm9200_smc_config'. It is simlar to a patch provided
by Andrew Victor for the AT91SAM9 family (sam9_smc.[ch]).

The code can be used like this:

        /*
         * Setup static memory controller chip select for external quad UART
         *
         */
        static const struct __initdata at91rm9200_smc_config
                quad_uart_cs_config = {
                .wait_states          = 16,
                .data_float_time      = 0,
                .byte_access_type     = AT91RM9200_BAT_8_BIT,
                .data_bus_width       = AT91RM9200_DATA_BUS_WIDTH_8,
                .data_read_protocol   = AT91RM9200_DRP_STANDARD,
                .address_to_cs_setup  = AT91RM9200_ACSS_STANDARD,
                .rw_setup             = 2,
                .rw_hold              = 2
        };

        if (at91rm9200_smc_configure(CCM2200_QUAD_UART_CS,
                                     &quad_uart_cs_config ) != 0 ) {
                printk( KERN_ERR
                        "Unable to configure static memory controller\n" );
                return -EIO;
	}


I am new at ARM linux and not familiar with the naming conventions.
Please review the patch and give comments.

Best regards

  Guido Classen

Signed-off-by: Guido Classen <clagix at gmail.com>

diff -Nrub '--exclude=*~'
linux-2.6.35-ccm2200/arch/arm/mach-at91/at91rm9200_smc.c
linux-2.6.35-rm9200_smc//arch/arm/mach-at91/at91rm9200_smc.c
--- linux-2.6.35-ccm2200/arch/arm/mach-at91/at91rm9200_smc.c	1970-01-01
01:00:00.000000000 +0100
+++ linux-2.6.35-rm9200_smc//arch/arm/mach-at91/at91rm9200_smc.c	2010-06-14
19:58:48.000000000 +0200
@@ -0,0 +1,88 @@
+/*
+ * linux/arch/arm/mach-at91/at91rm9200_smc.c
+ *
+ * Copyright (C) 2010 Guido Classen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/io.h>
+
+#include <mach/at91rm9200_mc.h>
+#include <mach/at91_pio.h>
+
+#include "at91rm9200_smc.h"
+
+int __init at91rm9200_smc_configure(int chip_select,
+				    struct at91rm9200_smc_config *config)
+{
+	unsigned int mask;
+
+	/* check parameters */
+	if (chip_select < 0 || chip_select > 7
+	    || config->wait_states > 128
+	    || config->data_float_time > 15
+	    || (config->byte_access_type != AT91RM9200_BAT_TWO_8_BIT
+		&& config->byte_access_type != AT91RM9200_BAT_16_BIT)
+	    || (config->data_read_protocol != AT91RM9200_DRP_STANDARD
+		&& config->data_read_protocol != AT91RM9200_DRP_EARLY)
+	    || config->address_to_cs_setup < AT91RM9200_ACSS_STANDARD
+	    || config->address_to_cs_setup > AT91RM9200_ACSS_3_CYCLES
+	    || config->rw_setup > 7
+	    || config->rw_hold > 7)
+		return -EINVAL;
+
+
+	// configure gpios, if necessary
+	if (chip_select > 3)
+	{
+#define AT91C_PC10_NCS4_CFCS  (1<<10)
+#define AT91C_PC11_NCS5_CFCE1 (1<<11)
+#define AT91C_PC12_NCS6_CFCE2 (1<<12)
+#define AT91C_PC13_NCS7	      (1<<13)
+		switch (chip_select)
+		{
+		case 4:	mask = AT91C_PC10_NCS4_CFCS;	break;
+		case 5:	mask = AT91C_PC11_NCS5_CFCE1;	break;
+		case 6:	mask = AT91C_PC12_NCS6_CFCE2;	break;
+		case 7:	mask = AT91C_PC13_NCS7;		break;
+		default: mask = 0;
+		}
+		/* select peripheral a function */
+		at91_sys_write(AT91_PIOC + PIO_ASR, mask);
+
+		/* disable pio controller and enable peripheral */
+		at91_sys_write(AT91_PIOC + PIO_PDR, mask);
+	}
+
+	/* write the new configuration to SMC chip select register */
+	at91_sys_write(AT91_SMC_CSR(chip_select),
+		       (config->wait_states > 0
+			? (AT91_SMC_NWS & (config->wait_states-1))
+			| AT91_SMC_WSEN
+			: 0)
+		       | AT91_SMC_TDF_(config->data_float_time)
+		       | (config->byte_access_type == AT91RM9200_BAT_16_BIT
+			  ? AT91_SMC_BAT : 0)
+		       | ((int)config->data_bus_width << 13)
+		       | (config->data_read_protocol == AT91RM9200_DRP_EARLY
+			  ? AT91_SMC_DPR : 0)
+		       | ((int)config->address_to_cs_setup << 16)
+		       | AT91_SMC_RWSETUP_(config->rw_setup)
+		       | AT91_SMC_RWHOLD_(config->rw_hold) );
+	return 0;
+}
diff -Nrub '--exclude=*~'
linux-2.6.35-ccm2200/arch/arm/mach-at91/at91rm9200_smc.h
linux-2.6.35-rm9200_smc//arch/arm/mach-at91/at91rm9200_smc.h
--- linux-2.6.35-ccm2200/arch/arm/mach-at91/at91rm9200_smc.h	1970-01-01
01:00:00.000000000 +0100
+++ linux-2.6.35-rm9200_smc//arch/arm/mach-at91/at91rm9200_smc.h	2010-06-14
19:51:15.000000000 +0200
@@ -0,0 +1,66 @@
+/*
+ * linux/arch/arm/mach-at91/at91rm9200_smc.h
+ *
+ * Copyright (C) 2010 Guido Classen
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307	 USA
+ *
+ */
+
+struct at91rm9200_smc_config {
+	/* wait states 0...128 (0 = no wait states) */
+	u8 wait_states;
+	/* 0...15 wait states after memory read cycle */
+	u8 data_float_time;
+
+	/* only valid for data_bus_width=AT91RM9200_DATA_BUS_WIDTH_16 */
+	enum byte_access_type {
+		/* dummy value for 8 bit device (ignored) */
+		AT91RM9200_BAT_8_BIT = 0,
+		/* chip select is connected to two/four 8-bit
+		 * devices */
+		AT91RM9200_BAT_TWO_8_BIT = 0,
+		/* chip select is connected too a 16 bit device */
+		AT91RM9200_BAT_16_BIT = 1
+	} byte_access_type;
+
+	enum data_bus_width {
+		AT91RM9200_DATA_BUS_WIDTH_8 = 2,  /* 8 bit data bus */
+		AT91RM9200_DATA_BUS_WIDTH_16 = 1, /* 16 bit data bus */
+	} data_bus_width;
+	enum data_read_protocol {
+		AT91RM9200_DRP_STANDARD = 0, /* standard data read protocol */
+		AT91RM9200_DRP_EARLY	= 1  /* early data read protocol */
+	} data_read_protocol;
+
+	enum address_to_cs_setup {
+		/* standard: address asserted at the beginning of the
+		 * access and deasserted at the end */
+		AT91RM9200_ACSS_STANDARD   = 0,
+		/* one cycle less at the beginning and end */
+		AT91RM9200_ACSS_1_CYCLE	   = 1,
+		/* two cycles less at the beginning and end */
+		AT91RM9200_ACSS_2_CYCLES   = 2,
+		/* three cycles less at the beginning and end */
+		AT91RM9200_ACSS_3_CYCLES   = 3
+	} address_to_cs_setup;
+	/* 0...7 number of read/write setup cycles */
+	u8 rw_setup;
+	/* 0...7 number of read/write hold cycles */
+	u8 rw_hold;
+};
+
+extern int __init at91rm9200_smc_configure(int chip_select,
+					   struct at91rm9200_smc_config *config);
diff -Nrub '--exclude=*~'
linux-2.6.35-ccm2200/arch/arm/mach-at91/Makefile
linux-2.6.35-rm9200_smc//arch/arm/mach-at91/Makefile
--- linux-2.6.35-ccm2200/arch/arm/mach-at91/Makefile	2010-06-14
16:31:35.000000000 +0200
+++ linux-2.6.35-rm9200_smc//arch/arm/mach-at91/Makefile	2010-06-14
19:45:24.000000000 +0200
@@ -10,7 +10,7 @@
 obj-$(CONFIG_AT91_PMC_UNIT)	+= clock.o

 # CPU-specific support
-obj-$(CONFIG_ARCH_AT91RM9200)	+= at91rm9200.o at91rm9200_time.o
at91rm9200_devices.o
+obj-$(CONFIG_ARCH_AT91RM9200)	+= at91rm9200.o at91rm9200_time.o
at91rm9200_devices.o at91rm9200_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9260)	+= at91sam9260.o at91sam926x_time.o
at91sam9260_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9261)	+= at91sam9261.o at91sam926x_time.o
at91sam9261_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G10)	+= at91sam9261.o at91sam926x_time.o
at91sam9261_devices.o sam9_smc.o


From dwalker at codeaurora.org  Tue Jun 15 14:27:23 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Tue, 15 Jun 2010 11:27:23 -0700
Subject: [GIT PULL] ARM MSM for 2.6.36
Message-ID: <1276626445-20316-1-git-send-email-dwalker@codeaurora.org>

Russell,

Here are some patch that's have been submitted here a few times for review,
and recently have seen any comments. One fixes a memory defect seen on
our MSM7x30 platform, and the other enabled gpiolib for MSM and trout
specifically.

Anyway, Please pull and let me know if there's any issues.

Daniel

The following changes since commit 7e27d6e778cd87b6f2415515d7127eba53fe5d02:

  Linux 2.6.35-rc3 (2010-06-11 19:14:04 -0700)

are available in the git repository at:
  git://codeaurora.org/quic/kernel/dwalker/linux-msm.git for-russell

Michael Bohan (1):
      arm: mm: Don't free prohibited memmap entries

Pavel Machek (1):
      Add GPIO support for HTC Dream.

 arch/arm/Kconfig                      |    1 +
 arch/arm/mach-msm/Makefile            |    2 +-
 arch/arm/mach-msm/board-trout-gpio.c  |  112 +++++++++++++++++++++++
 arch/arm/mach-msm/board-trout.h       |  157 +++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/gpio.h |    7 ++
 arch/arm/mm/init.c                    |   19 ++--
 6 files changed, 287 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/mach-msm/board-trout-gpio.c


From dwalker at codeaurora.org  Tue Jun 15 14:27:25 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Tue, 15 Jun 2010 11:27:25 -0700
Subject: [PATCH 2/2] arm: mm: Don't free prohibited memmap entries
In-Reply-To: <1276626445-20316-1-git-send-email-dwalker@codeaurora.org>
References: <1276626445-20316-1-git-send-email-dwalker@codeaurora.org>
Message-ID: <1276626445-20316-3-git-send-email-dwalker@codeaurora.org>

From: Michael Bohan <mbohan at codeaurora.org>

The VM subsystem assumes that there are valid memmap entries to
the bank end aligned to MAX_ORDER_NR_PAGES. It will try and read
these page structs, and so we cannot free any memmap entries that
it may inspect.

Signed-off-by: Michael Bohan <mbohan at codeaurora.org>
Signed-off-by: Daniel Walker <dwalker at codeaurora.org>
---
 arch/arm/mm/init.c |   19 +++++++++----------
 1 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index f6a9994..e18c7ce 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -495,28 +495,27 @@ static void __init free_unused_memmap_node(int node, struct meminfo *mi)
 	unsigned int i;
 
 	/*
-	 * [FIXME] This relies on each bank being in address order.  This
-	 * may not be the case, especially if the user has provided the
-	 * information on the command line.
+	 * This relies on each bank being in address order.
+	 * The banks are sorted previously in bootmem_init().
 	 */
 	for_each_nodebank(i, mi, node) {
 		struct membank *bank = &mi->bank[i];
 
 		bank_start = bank_pfn_start(bank);
-		if (bank_start < prev_bank_end) {
-			printk(KERN_ERR "MEM: unordered memory banks.  "
-				"Not freeing memmap.\n");
-			break;
-		}
 
 		/*
 		 * If we had a previous bank, and there is a space
 		 * between the current bank and the previous, free it.
 		 */
-		if (prev_bank_end && prev_bank_end != bank_start)
+		if (prev_bank_end && prev_bank_end < bank_start)
 			free_memmap(node, prev_bank_end, bank_start);
 
-		prev_bank_end = bank_pfn_end(bank);
+		/*
+		 * Align up here since the VM subsystem insists that the
+		 * memmap entries are valid from the bank end aligned to
+		 * MAX_ORDER_NR_PAGES.
+		 */
+		prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES);
 	}
 }
 
-- 
1.7.1



From dwalker at codeaurora.org  Tue Jun 15 14:27:24 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Tue, 15 Jun 2010 11:27:24 -0700
Subject: [PATCH 1/2] Add GPIO support for HTC Dream.
In-Reply-To: <1276626445-20316-1-git-send-email-dwalker@codeaurora.org>
References: <1276626445-20316-1-git-send-email-dwalker@codeaurora.org>
Message-ID: <1276626445-20316-2-git-send-email-dwalker@codeaurora.org>

From: Pavel Machek <pavel at ucw.cz>

Signed-off-by: Pavel Machek <pavel at ucw.cz>
[dwalker at codeaurora.org: renamed to trout]
Signed-off-by: Daniel Walker <dwalker at codeaurora.org>
---
 arch/arm/Kconfig                      |    1 +
 arch/arm/mach-msm/Makefile            |    2 +-
 arch/arm/mach-msm/board-trout-gpio.c  |  112 +++++++++++++++++++++++
 arch/arm/mach-msm/board-trout.h       |  157 +++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/gpio.h |    7 ++
 5 files changed, 278 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-msm/board-trout-gpio.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..c171f35 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -586,6 +586,7 @@ config ARCH_MSM
 	bool "Qualcomm MSM"
 	select HAVE_CLK
 	select GENERIC_CLOCKEVENTS
+	select ARCH_REQUIRE_GPIOLIB
 	help
 	  Support for Qualcomm MSM/QSD based systems.  This runs on the
 	  apps processor of the MSM/QSD and depends on a shared memory
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 66677f0..7ff8020 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -15,7 +15,7 @@ obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
 obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
 obj-$(CONFIG_MSM_SMD) += last_radio_log.o
 
-obj-$(CONFIG_MACH_TROUT) += board-trout.o devices-msm7x00.o
+obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o devices-msm7x00.o
 obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
 obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
 obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
new file mode 100644
index 0000000..6e6bc76
--- /dev/null
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -0,0 +1,112 @@
+/*
+ * linux/arch/arm/mach-msm/gpio.c
+ *
+ * Copyright (C) 2005 HP Labs
+ * Copyright (C) 2008 Google, Inc.
+ * Copyright (C) 2009 Pavel Machek <pavel at ucw.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+
+#include "board-trout.h"
+
+struct msm_gpio_chip {
+	struct gpio_chip	chip;
+	void __iomem		*reg;	/* Base of register bank */
+	u8			shadow;
+};
+
+#define to_msm_gpio_chip(c) container_of(c, struct msm_gpio_chip, chip)
+
+static int msm_gpiolib_get(struct gpio_chip *chip, unsigned offset)
+{
+	struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
+	unsigned mask = 1 << offset;
+
+	return !! (readb(msm_gpio->reg) & mask);
+}
+
+static void msm_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+	struct msm_gpio_chip *msm_gpio = to_msm_gpio_chip(chip);
+	unsigned mask = 1 << offset;
+
+	if (val)
+		msm_gpio->shadow |= mask;
+	else
+		msm_gpio->shadow &= ~mask;
+
+	writeb(msm_gpio->shadow, msm_gpio->reg);
+}
+
+static int msm_gpiolib_direction_input(struct gpio_chip *chip,
+					unsigned offset)
+{
+	msm_gpiolib_set(chip, offset, 0);
+	return 0;
+}
+
+static int msm_gpiolib_direction_output(struct gpio_chip *chip,
+					 unsigned offset, int val)
+{
+	msm_gpiolib_set(chip, offset, val);
+	return 0;
+}
+
+#define TROUT_GPIO_BANK(name, reg_num, base_gpio, shadow_val)		\
+	{								\
+		.chip = {						\
+			.label		  = name,			\
+			.direction_input  = msm_gpiolib_direction_input,\
+			.direction_output = msm_gpiolib_direction_output, \
+			.get		  = msm_gpiolib_get,		\
+			.set		  = msm_gpiolib_set,		\
+			.base		  = base_gpio,			\
+			.ngpio		  = 8,				\
+		},							\
+		.reg = (void *) reg_num + TROUT_CPLD_BASE,		\
+		.shadow = shadow_val,					\
+	}
+
+static struct msm_gpio_chip msm_gpio_banks[] = {
+#if defined(CONFIG_MSM_DEBUG_UART1)
+        /* H2W pins <-> UART1 */
+        TROUT_GPIO_BANK("MISC2", 0x00,   TROUT_GPIO_MISC2_BASE, 0x40),
+#else
+	/* H2W pins <-> UART3, Bluetooth <-> UART1 */
+        TROUT_GPIO_BANK("MISC2", 0x00,   TROUT_GPIO_MISC2_BASE, 0x80),
+#endif
+	/* I2C pull */
+        TROUT_GPIO_BANK("MISC3", 0x02,   TROUT_GPIO_MISC3_BASE, 0x04),
+        TROUT_GPIO_BANK("MISC4", 0x04,   TROUT_GPIO_MISC4_BASE, 0),
+	/* mmdi 32k en */
+        TROUT_GPIO_BANK("MISC5", 0x06,   TROUT_GPIO_MISC5_BASE, 0x04),
+        TROUT_GPIO_BANK("INT2", 0x08,    TROUT_GPIO_INT2_BASE,  0),
+        TROUT_GPIO_BANK("MISC1", 0x0a,   TROUT_GPIO_MISC1_BASE, 0),
+        TROUT_GPIO_BANK("VIRTUAL", 0x12, TROUT_GPIO_VIRTUAL_BASE, 0),
+};
+
+/*
+ * Called from the processor-specific init to enable GPIO pin support.
+ */
+int __init trout_init_gpio(void)
+{
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
+                gpiochip_add(&msm_gpio_banks[i].chip);
+
+	return 0;
+}
+
+postcore_initcall(trout_init_gpio);
+
diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h
index 4f345a5..308c4df 100644
--- a/arch/arm/mach-msm/board-trout.h
+++ b/arch/arm/mach-msm/board-trout.h
@@ -1,5 +1,162 @@
+/* linux/arch/arm/mach-msm/board-trout.h
+** Author: Brian Swetland <swetland at google.com>
+*/
+#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
+#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
+
+#include <mach/board.h>
+
+#define MSM_SMI_BASE		0x00000000
+#define MSM_SMI_SIZE		0x00800000
+
+#define MSM_EBI_BASE		0x10000000
+#define MSM_EBI_SIZE		0x06e00000
+
+#define MSM_PMEM_GPU0_BASE	0x00000000
+#define MSM_PMEM_GPU0_SIZE	0x00700000
+
+#define MSM_PMEM_MDP_BASE	0x02000000
+#define MSM_PMEM_MDP_SIZE	0x00800000
+
+#define MSM_PMEM_ADSP_BASE      0x02800000
+#define MSM_PMEM_ADSP_SIZE	0x00800000
+
+#define MSM_PMEM_CAMERA_BASE	0x03000000
+#define MSM_PMEM_CAMERA_SIZE	0x00800000
+
+#define MSM_FB_BASE		0x03800000
+#define MSM_FB_SIZE		0x00100000
+
+#define MSM_LINUX_BASE		MSM_EBI_BASE
+#define MSM_LINUX_SIZE		0x06500000
+
+#define MSM_PMEM_GPU1_SIZE	0x800000
+#define MSM_PMEM_GPU1_BASE	MSM_RAM_CONSOLE_BASE - MSM_PMEM_GPU1_SIZE
+
+#define MSM_RAM_CONSOLE_BASE	MSM_EBI_BASE + 0x6d00000
+#define MSM_RAM_CONSOLE_SIZE	128 * SZ_1K
+
+#if (MSM_FB_BASE + MSM_FB_SIZE) >= (MSM_PMEM_GPU1_BASE)
+#error invalid memory map
+#endif
+
+#define DECLARE_MSM_IOMAP
+#include <mach/msm_iomap.h>
+
+#define TROUT_4_BALL_UP_0     1
+#define TROUT_4_BALL_LEFT_0   18
+#define TROUT_4_BALL_DOWN_0   57
+#define TROUT_4_BALL_RIGHT_0  91
+
+#define TROUT_5_BALL_UP_0     94
+#define TROUT_5_BALL_LEFT_0   18
+#define TROUT_5_BALL_DOWN_0   90
+#define TROUT_5_BALL_RIGHT_0  19
+
+#define TROUT_POWER_KEY     20
+
+#define TROUT_4_TP_LS_EN    19
+#define TROUT_5_TP_LS_EN    1
 
 #define TROUT_CPLD_BASE   0xE8100000
 #define TROUT_CPLD_START  0x98000000
 #define TROUT_CPLD_SIZE   SZ_4K
 
+#define TROUT_GPIO_CABLE_IN1		(83)
+#define TROUT_GPIO_CABLE_IN2		(49)
+
+#define TROUT_GPIO_START (128)
+
+#define TROUT_GPIO_INT_MASK0_REG            (0x0c)
+#define TROUT_GPIO_INT_STAT0_REG            (0x0e)
+#define TROUT_GPIO_INT_MASK1_REG            (0x14)
+#define TROUT_GPIO_INT_STAT1_REG            (0x10)
+
+#define TROUT_GPIO_HAPTIC_PWM               (28)
+#define TROUT_GPIO_PS_HOLD                  (25)
+
+#define TROUT_GPIO_MISC2_BASE               (TROUT_GPIO_START + 0x00)
+#define TROUT_GPIO_MISC3_BASE               (TROUT_GPIO_START + 0x08)
+#define TROUT_GPIO_MISC4_BASE               (TROUT_GPIO_START + 0x10)
+#define TROUT_GPIO_MISC5_BASE               (TROUT_GPIO_START + 0x18)
+#define TROUT_GPIO_INT2_BASE                (TROUT_GPIO_START + 0x20)
+#define TROUT_GPIO_MISC1_BASE               (TROUT_GPIO_START + 0x28)
+#define TROUT_GPIO_VIRTUAL_BASE             (TROUT_GPIO_START + 0x30)
+#define TROUT_GPIO_INT5_BASE                (TROUT_GPIO_START + 0x48)
+
+#define TROUT_GPIO_CHARGER_EN               (TROUT_GPIO_MISC2_BASE + 0)
+#define TROUT_GPIO_ISET                     (TROUT_GPIO_MISC2_BASE + 1)
+#define TROUT_GPIO_H2W_DAT_DIR              (TROUT_GPIO_MISC2_BASE + 2)
+#define TROUT_GPIO_H2W_CLK_DIR              (TROUT_GPIO_MISC2_BASE + 3)
+#define TROUT_GPIO_H2W_DAT_GPO              (TROUT_GPIO_MISC2_BASE + 4)
+#define TROUT_GPIO_H2W_CLK_GPO              (TROUT_GPIO_MISC2_BASE + 5)
+#define TROUT_GPIO_H2W_SEL0                 (TROUT_GPIO_MISC2_BASE + 6)
+#define TROUT_GPIO_H2W_SEL1                 (TROUT_GPIO_MISC2_BASE + 7)
+
+#define TROUT_GPIO_SPOTLIGHT_EN             (TROUT_GPIO_MISC3_BASE + 0)
+#define TROUT_GPIO_FLASH_EN                 (TROUT_GPIO_MISC3_BASE + 1)
+#define TROUT_GPIO_I2C_PULL                 (TROUT_GPIO_MISC3_BASE + 2)
+#define TROUT_GPIO_TP_I2C_PULL              (TROUT_GPIO_MISC3_BASE + 3)
+#define TROUT_GPIO_TP_EN                    (TROUT_GPIO_MISC3_BASE + 4)
+#define TROUT_GPIO_JOG_EN                   (TROUT_GPIO_MISC3_BASE + 5)
+#define TROUT_GPIO_UI_LED_EN                (TROUT_GPIO_MISC3_BASE + 6)
+#define TROUT_GPIO_QTKEY_LED_EN             (TROUT_GPIO_MISC3_BASE + 7)
+
+#define TROUT_GPIO_VCM_PWDN                 (TROUT_GPIO_MISC4_BASE + 0)
+#define TROUT_GPIO_USB_H2W_SW               (TROUT_GPIO_MISC4_BASE + 1)
+#define TROUT_GPIO_COMPASS_RST_N            (TROUT_GPIO_MISC4_BASE + 2)
+#define TROUT_GPIO_HAPTIC_EN_UP             (TROUT_GPIO_MISC4_BASE + 3)
+#define TROUT_GPIO_HAPTIC_EN_MAIN           (TROUT_GPIO_MISC4_BASE + 4)
+#define TROUT_GPIO_USB_PHY_RST_N            (TROUT_GPIO_MISC4_BASE + 5)
+#define TROUT_GPIO_WIFI_PA_RESETX           (TROUT_GPIO_MISC4_BASE + 6)
+#define TROUT_GPIO_WIFI_EN                  (TROUT_GPIO_MISC4_BASE + 7)
+
+#define TROUT_GPIO_BT_32K_EN                (TROUT_GPIO_MISC5_BASE + 0)
+#define TROUT_GPIO_MAC_32K_EN               (TROUT_GPIO_MISC5_BASE + 1)
+#define TROUT_GPIO_MDDI_32K_EN              (TROUT_GPIO_MISC5_BASE + 2)
+#define TROUT_GPIO_COMPASS_32K_EN           (TROUT_GPIO_MISC5_BASE + 3)
+
+#define TROUT_GPIO_NAVI_ACT_N               (TROUT_GPIO_INT2_BASE + 0)
+#define TROUT_GPIO_COMPASS_IRQ              (TROUT_GPIO_INT2_BASE + 1)
+#define TROUT_GPIO_SLIDING_DET              (TROUT_GPIO_INT2_BASE + 2)
+#define TROUT_GPIO_AUD_HSMIC_DET_N          (TROUT_GPIO_INT2_BASE + 3)
+#define TROUT_GPIO_SD_DOOR_N                (TROUT_GPIO_INT2_BASE + 4)
+#define TROUT_GPIO_CAM_BTN_STEP1_N          (TROUT_GPIO_INT2_BASE + 5)
+#define TROUT_GPIO_CAM_BTN_STEP2_N          (TROUT_GPIO_INT2_BASE + 6)
+#define TROUT_GPIO_TP_ATT_N                 (TROUT_GPIO_INT2_BASE + 7)
+#define TROUT_GPIO_BANK0_FIRST_INT_SOURCE   (TROUT_GPIO_NAVI_ACT_N)
+#define TROUT_GPIO_BANK0_LAST_INT_SOURCE    (TROUT_GPIO_TP_ATT_N)
+
+#define TROUT_GPIO_H2W_DAT_GPI              (TROUT_GPIO_MISC1_BASE + 0)
+#define TROUT_GPIO_H2W_CLK_GPI              (TROUT_GPIO_MISC1_BASE + 1)
+#define TROUT_GPIO_CPLD128_VER_0            (TROUT_GPIO_MISC1_BASE + 4)
+#define TROUT_GPIO_CPLD128_VER_1            (TROUT_GPIO_MISC1_BASE + 5)
+#define TROUT_GPIO_CPLD128_VER_2            (TROUT_GPIO_MISC1_BASE + 6)
+#define TROUT_GPIO_CPLD128_VER_3            (TROUT_GPIO_MISC1_BASE + 7)
+
+#define TROUT_GPIO_SDMC_CD_N                (TROUT_GPIO_VIRTUAL_BASE + 0)
+#define TROUT_GPIO_END                      (TROUT_GPIO_SDMC_CD_N)
+#define TROUT_GPIO_BANK1_FIRST_INT_SOURCE   (TROUT_GPIO_SDMC_CD_N)
+#define TROUT_GPIO_BANK1_LAST_INT_SOURCE    (TROUT_GPIO_SDMC_CD_N)
+
+#define TROUT_GPIO_VIRTUAL_TO_REAL_OFFSET \
+	(TROUT_GPIO_INT5_BASE - TROUT_GPIO_VIRTUAL_BASE)
+
+#define TROUT_INT_START (NR_MSM_IRQS + NR_GPIO_IRQS)
+#define TROUT_INT_BANK0_COUNT (8)
+#define TROUT_INT_BANK1_START (TROUT_INT_START + TROUT_INT_BANK0_COUNT)
+#define TROUT_INT_BANK1_COUNT (1)
+#define TROUT_INT_END (TROUT_INT_START + TROUT_INT_BANK0_COUNT + \
+			TROUT_INT_BANK1_COUNT - 1)
+#define TROUT_GPIO_TO_INT(n) (((n) <= TROUT_GPIO_BANK0_LAST_INT_SOURCE) ? \
+	(TROUT_INT_START - TROUT_GPIO_BANK0_FIRST_INT_SOURCE + (n)) : \
+	(TROUT_INT_BANK1_START - TROUT_GPIO_BANK1_FIRST_INT_SOURCE + (n)))
+
+#define TROUT_INT_TO_BANK(n) ((n - TROUT_INT_START) / TROUT_INT_BANK0_COUNT)
+#define TROUT_INT_TO_MASK(n) (1U << ((n - TROUT_INT_START) & 7))
+#define TROUT_BANK_TO_MASK_REG(bank) \
+	(bank ? TROUT_GPIO_INT_MASK1_REG : TROUT_GPIO_INT_MASK0_REG)
+#define TROUT_BANK_TO_STAT_REG(bank) \
+	(bank ? TROUT_GPIO_INT_STAT1_REG : TROUT_GPIO_INT_STAT0_REG)
+
+#endif /* GUARD */
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
index 262b441..83e47c0 100644
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -16,6 +16,13 @@
 #ifndef __ASM_ARCH_MSM_GPIO_H
 #define __ASM_ARCH_MSM_GPIO_H
 
+#include <asm-generic/gpio.h>
+
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+
 /**
  * struct msm_gpio - GPIO pin description
  * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
-- 
1.7.1



From dwalker at codeaurora.org  Tue Jun 15 14:28:43 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Tue, 15 Jun 2010 11:28:43 -0700
Subject: [GIT PULL] ARM MSM for 2.6.36
In-Reply-To: <1276626445-20316-1-git-send-email-dwalker@codeaurora.org>
References: <1276626445-20316-1-git-send-email-dwalker@codeaurora.org>
Message-ID: <1276626523.6432.4.camel@c-dwalke-linux.qualcomm.com>

On Tue, 2010-06-15 at 11:27 -0700, Daniel Walker wrote:
> Russell,
> 
> Here are some patch that's have been submitted here a few times for review,
> and recently have seen any comments. One fixes a memory defect seen on
> our MSM7x30 platform, and the other enabled gpiolib for MSM and trout
> specifically.

Sorry, this paragraph is horrible ..

They haven't seen any comments, and they have been submitted a few times
in the past..

Daniel



From mathieu.desnoyers at efficios.com  Tue Jun 15 14:29:19 2010
From: mathieu.desnoyers at efficios.com (Mathieu Desnoyers)
Date: Tue, 15 Jun 2010 14:29:19 -0400
Subject: Userspace helpers at static addresses on ARM [was: Re: [PATCH] fix
	the "unknown" case]
In-Reply-To: <OFC507BE7B.F11411B7-ONC1257743.005F924F-C1257743.00605E5E@de.ibm.com>
References: <20100614220600.GA15130@linux.vnet.ibm.com>
	<OF014FB97C.3968191D-ONC1257743.0043E356-C1257743.004525C9@de.ibm.com>
	<20100615150727.GC2304@linux.vnet.ibm.com>
	<OFCD1BC564.0035E292-ONC1257743.0057CB53-C1257743.0058903F@de.ibm.com>
	<20100615170001.GG2304@linux.vnet.ibm.com>
	<20100615170315.GA7835@Krystal>
	<OFC507BE7B.F11411B7-ONC1257743.005F924F-C1257743.00605E5E@de.ibm.com>
Message-ID: <20100615182919.GB11394@Krystal>

* Ulrich Weigand (Ulrich.Weigand at de.ibm.com) wrote:
> Mathieu Desnoyers <mathieu.desnoyers at efficios.com> wrote on 06/15/2010
> 07:03:15 PM:
> 
> > I wonder starting with which Linux kernel version __kernel_dmb appeared.
> > Tying ourself directly to a Linux kernel ABI might complicate things.
> >
> > Is this ABI presented in a vDSO or userland have to go through a system
> call ?
> > Is there any way to probe for its availability ?
> 
> This looks sort-of like a vDSO, except without the DSO part :-)
> 
> The kernel simply makes the code available at a fixed address that is
> directly callable by user space.  See the comments in
> linux/arch/arm/kernel/entry-armv.S:
> 

Hrm, statically addressed shared objects. The security guys should be freaking
out here. This can sadly make stack overflow exploitation much, much, easier
because of lack of randomization of addresses where the code is located. :-/

About the original topic of our discussion:
Thanks for the explanation below. I think making urcu test for the kernel
feature at library load seems like the best portable solution so far. We can
directly use the specific memory barriers when armv7+ is specified, and check
at runtime if the kernel feature is there for "generic" arm build. For generic
ARM build where we discover that the kernel lacks the proper features, we could
rely on Paul's double-fake-mutex scheme (assuming we audit glibc pthreads to
ensure the proper memory barriers are there). If we find out that even pthreads
mutexes got the barriers wrong there, then we should refuse to load the library
altogether.

Thanks,

Mathieu

> /*
>  * User helpers.
>  *
>  * These are segment of kernel provided user code reachable from user space
>  * at a fixed address in kernel memory.  This is used to provide user space
>  * with some operations which require kernel help because of unimplemented
>  * native feature and/or instructions in many ARM CPUs. The idea is for
>  * this code to be executed directly in user mode for best efficiency but
>  * which is too intimate with the kernel counter part to be left to user
>  * libraries.  In fact this code might even differ from one CPU to another
>  * depending on the available  instruction set and restrictions like on
>  * SMP systems.  In other words, the kernel reserves the right to change
>  * this code as needed without warning. Only the entry points and their
>  * results are guaranteed to be stable.
>  *
>  * Each segment is 32-byte aligned and will be moved to the top of the high
>  * vector page.  New segments (if ever needed) must be added in front of
>  * existing ones.  This mechanism should be used only for things that are
>  * really small and justified, and not be abused freely.
>  *
>  * User space is expected to implement those things inline when optimizing
>  * for a processor that has the necessary native support, but only if such
>  * resulting binaries are already to be incompatible with earlier ARM
>  * processors due to the use of unsupported instructions other than what
>  * is provided here.  In other words don't make binaries unable to run on
>  * earlier processors just for the sake of not using these kernel helpers
>  * if your compiled code is not going to use the new instructions for other
>  * purpose.
>  */
> 
> 
> /*
>  * Reference prototype:
>  *
>  *           void __kernel_memory_barrier(void)
>  *
>  * Input:
>  *
>  *           lr = return address
>  *
>  * Output:
>  *
>  *           none
>  *
>  * Clobbered:
>  *
>  *           none
>  *
>  * Definition and user space usage example:
>  *
>  *           typedef void (__kernel_dmb_t)(void);
>  *           #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
>  *
>  * Apply any needed memory barrier to preserve consistency with data
> modified
>  * manually and __kuser_cmpxchg usage.
>  *
>  * This could be used as follows:
>  *
>  * #define __kernel_dmb() \
>  *         asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0,
> #95" \
>  *		         : : : "r0", "lr","cc" )
>  */
> 
> 
> As far as I can see, the only provision to check whether a feature is
> available
> is this one:
> 
> /*
>  * Reference declaration:
>  *
>  *           extern unsigned int __kernel_helper_version;
>  *
>  * Definition and user space usage example:
>  *
>  *           #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
>  *
>  * User space may read this to determine the curent number of helpers
>  * available.
>  */
> 
> However, note that libgcc code does not perform this check, it simply
> assumes
> the above routine to be present.
> 
> The __kernel_dmb (which is the most recently added helper available in
> current
> mainline) seems to have been available since kernel 2.6.15, so presumably
> code
> using any of the GCC sync primitives would simply fail on any older kernel,
> unless I'm missing something here ...
> 
> 
> Mit freundlichen Gruessen / Best Regards
> 
> Ulrich Weigand
> 
> --
>   Dr. Ulrich Weigand | Phone: +49-7031/16-3727
>   STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
>   IBM Deutschland Research & Development GmbH
>   Vorsitzender des Aufsichtsrats: Martin Jetter | Gesch?ftsf?hrung: Dirk
> Wittkopp
>   Sitz der Gesellschaft: B?blingen | Registergericht: Amtsgericht
> Stuttgart, HRB 243294
> 

-- 
Mathieu Desnoyers
Operating System Efficiency R&D Consultant
EfficiOS Inc.
http://www.efficios.com


From grant.likely at secretlab.ca  Tue Jun 15 14:29:15 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 15 Jun 2010 12:29:15 -0600
Subject: [PATCH 05/12] phylib: Allow reading and writing a mii bus from 
	atomic context.
In-Reply-To: <20100615170806.GB10668@riccoc20.at.omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<1b8219e7d7993d0e8204b94e959477e3007534ce.1276615626.git.richard.cochran@omicron.at>
	<AANLkTikeae2t4KmnawOCo2LqfSI57BKjNnUayY09DfEC@mail.gmail.com> 
	<20100615170806.GB10668@riccoc20.at.omicron.at>
Message-ID: <AANLkTin8RI4UKzA58k_qER_urdwnD037u5GZrVQS8IoS@mail.gmail.com>

On Tue, Jun 15, 2010 at 11:08 AM, Richard Cochran
<richardcochran at gmail.com> wrote:
> On Tue, Jun 15, 2010 at 10:43:08AM -0600, Grant Likely wrote:
>> On Tue, Jun 15, 2010 at 10:08 AM, Richard Cochran
>> <richardcochran at gmail.com> wrote:
>> > In order to support hardware time stamping from a PHY, it is necessary to
>> > read from the PHY while running in_interrupt(). This patch allows a mii
>> > bus to operate in an atomic context. An mii_bus driver may declare itself
>> > capable for this mode. Drivers which do not do this will remain with the
>> > default that bus operations may sleep.
>> >
>> > Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
>>
>> Last I checked, the MDIO bus is very slow. ?Is this really a good
>> idea? ?How much latency does MDIO access have on the hardware you are
>> working with?
>
> Yes, MDIO access is slow, and it can vary (eg bit banging
> implementations). It clear that getting PHY timestamps is costly, but
> for applications that want PTP synchronization, one is willing to pay
> the price.
>
>> I also don't like the idea of taking a spin lock during MDIO
>> operations, and the dual locking mode in the core code.
>
> Originally, the phylib used a spinlock for this. It was replaced with
> a mutex in 35b5f6b1a82b5c586e0b24c711dc6ba944e88ef1 in order to
> accommodate mdio busses that may need to sleep. So, keeping the option
> to use a spinlock is similar to the previous implementation.

That's right, and I fully agree with that change.  To me, going back
to allowing spin locks is a regression because it adds a new source of
scheduling latency.  Using a mutex forces users to take into account
the slow nature of MDIO access.  For existing callers, this isn't a
problem because they already are designed for this characteristic.  A
new user which depends on atomic access should use a different API
which doesn't take the lock with the understanding that it is may
return a failure if it doesn't support it or if it cannot perform the
operation atomically.

That still leaves the troubling MDIO induced latency issue.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From clagix at gmail.com  Tue Jun 15 14:36:47 2010
From: clagix at gmail.com (Guido Classen)
Date: Tue, 15 Jun 2010 20:36:47 +0200
Subject: [PATCH] Resend: at91rm9200 static memory controller initialization
Message-ID: <AANLkTinmuxJ9GhzZVOb51THgYe7208y7fQAzoyg2tcgM@mail.gmail.com>

Hello mailing list,

I resend the last patch becase it seams to be garbaged by google mail.

This patch adds AT91RM9200 static memory controller initialization based
on a structure 'at91rm9200_smc_config'. It is simlar to a patch provided
by Andrew Victor for the AT91SAM9 family (sam9_smc.[ch]).

The code can be used like this:

        /*
         * Setup static memory controller chip select for external quad UART
         *
         */
        static const struct __initdata at91rm9200_smc_config
                quad_uart_cs_config = {
                .wait_states          = 16,
                .data_float_time      = 0,
                .byte_access_type     = AT91RM9200_BAT_8_BIT,
                .data_bus_width       = AT91RM9200_DATA_BUS_WIDTH_8,
                .data_read_protocol   = AT91RM9200_DRP_STANDARD,
                .address_to_cs_setup  = AT91RM9200_ACSS_STANDARD,
                .rw_setup             = 2,
                .rw_hold              = 2
        };

        if (at91rm9200_smc_configure(CCM2200_QUAD_UART_CS,
                                     &quad_uart_cs_config ) != 0 ) {
                printk( KERN_ERR
                        "Unable to configure static memory controller\n" );
                return -EIO;
	}


I am new at ARM linux and not familiar with the naming conventions.
Please review the patch and give comments.

Best regards

  Guido Classen

Signed-off-by: Guido Classen <clagix at gmail.com>
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From grant.likely at secretlab.ca  Tue Jun 15 14:41:56 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 15 Jun 2010 12:41:56 -0600
Subject: [PATCH 11/12] ptp: Added a clock driver for the IXP46x.
In-Reply-To: <0c03ef3e283c6b3ef58feaf1f77ccb0fd605010b.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<0c03ef3e283c6b3ef58feaf1f77ccb0fd605010b.1276615626.git.richard.cochran@omicron.at>
Message-ID: <AANLkTinPDaWNvUG8q8RdvRUga-qrPlSV2H5TkzVVMaFn@mail.gmail.com>

On Tue, Jun 15, 2010 at 10:10 AM, Richard Cochran
<richardcochran at gmail.com> wrote:
> This patch adds a driver for the hardware time stamping unit found on the
> IXP465. Only the basic clock operations are implemented.
>
> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>

Hi Richard,

Comments below...

> ---
> ?arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h | ? 67 +++++++
> ?drivers/net/arm/ixp4xx_eth.c ? ? ? ? ? ? ? ? ?| ?194 +++++++++++++++++++++
> ?drivers/ptp/Kconfig ? ? ? ? ? ? ? ? ? ? ? ? ? | ? 13 ++
> ?drivers/ptp/Makefile ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?1 +
> ?drivers/ptp/ptp_ixp46x.c ? ? ? ? ? ? ? ? ? ? ?| ?231 +++++++++++++++++++++++++
> ?5 files changed, 506 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
> ?create mode 100644 drivers/ptp/ptp_ixp46x.c
>
> diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
> new file mode 100644
> index 0000000..7fb02b6
> --- /dev/null
> +++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
> @@ -0,0 +1,67 @@
> +/*
> + * PTP 1588 clock using the IXP46X
> + *
> + * Copyright (C) 2010 OMICRON electronics GmbH
> + *
> + * ?This program is free software; you can redistribute it and/or modify
> + * ?it under the terms of the GNU General Public License as published by
> + * ?the Free Software Foundation; either version 2 of the License, or
> + * ?(at your option) any later version.
> + *
> + * ?This program is distributed in the hope that it will be useful,
> + * ?but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * ?GNU General Public License for more details.
> + *
> + * ?You should have received a copy of the GNU General Public License
> + * ?along with this program; if not, write to the Free Software
> + * ?Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#ifndef _IXP46X_TS_H_
> +#define _IXP46X_TS_H_
> +
> +#define DEFAULT_ADDEND 0xF0000029
> +#define TICKS_NS_SHIFT 4
> +
> +struct ixp46x_channel_ctl {
> + ? ? ? u32 Ch_Control; /* 0x40 Time Synchronization Channel Control */
> + ? ? ? u32 Ch_Event; ? /* 0x44 Time Synchronization Channel Event */
> + ? ? ? u32 TxSnapLo; ? /* 0x48 Transmit Snapshot Low Register */
> + ? ? ? u32 TxSnapHi; ? /* 0x4C Transmit Snapshot High Register */
> + ? ? ? u32 RxSnapLo; ? /* 0x50 Receive Snapshot Low Register */
> + ? ? ? u32 RxSnapHi; ? /* 0x54 Receive Snapshot High Register */
> + ? ? ? u32 SrcUUIDLo; ?/* 0x58 Source UUID0 Low Register */
> + ? ? ? u32 SrcUUIDHi; ?/* 0x5C Sequence Identifier/Source UUID0 High */
> +};

Nitpick.  We use all lower case names for structures in Linux.

> +
> +struct ixp46x_ts_regs {
> + ? ? ? u32 Control; ? ? /* 0x00 Time Sync Control Register */
> + ? ? ? u32 Event; ? ? ? /* 0x04 Time Sync Event Register */
> + ? ? ? u32 Addend; ? ? ?/* 0x08 Time Sync Addend Register */
> + ? ? ? u32 Accum; ? ? ? /* 0x0C Time Sync Accumulator Register */
> + ? ? ? u32 Test; ? ? ? ?/* 0x10 Time Sync Test Register */
> + ? ? ? u32 Unused; ? ? ?/* 0x14 */
> + ? ? ? u32 RSysTime_Lo; /* 0x18 RawSystemTime_Low Register */
> + ? ? ? u32 RSysTimeHi; ?/* 0x1C RawSystemTime_High Register */
> + ? ? ? u32 SysTimeLo; ? /* 0x20 SystemTime_Low Register */
> + ? ? ? u32 SysTimeHi; ? /* 0x24 SystemTime_High Register */
> + ? ? ? u32 TrgtLo; ? ? ?/* 0x28 TargetTime_Low Register */
> + ? ? ? u32 TrgtHi; ? ? ?/* 0x2C TargetTime_High Register */
> + ? ? ? u32 ASMSLo; ? ? ?/* 0x30 Auxiliary Slave Mode Snapshot Low ?*/
> + ? ? ? u32 ASMSHi; ? ? ?/* 0x34 Auxiliary Slave Mode Snapshot High */
> + ? ? ? u32 AMMSLo; ? ? ?/* 0x38 Auxiliary Master Mode Snapshot Low */
> + ? ? ? u32 AMMSHi; ? ? ?/* 0x3C Auxiliary Master Mode Snapshot High */
> +
> + ? ? ? struct ixp46x_channel_ctl channel[3];
> +};
> +
> +/* 0x40 Time Synchronization Channel Control Register Bits */
> +#define MASTER_MODE ? (1<<0)
> +#define TIMESTAMP_ALL (1<<1)
> +
> +/* 0x44 Time Synchronization Channel Event Register Bits */
> +#define TX_SNAPSHOT_LOCKED (1<<0)
> +#define RX_SNAPSHOT_LOCKED (1<<1)
> +
> +#endif
> diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
> index 4f1cc71..2201960 100644
> --- a/drivers/net/arm/ixp4xx_eth.c
> +++ b/drivers/net/arm/ixp4xx_eth.c
> @@ -30,9 +30,12 @@
> ?#include <linux/etherdevice.h>
> ?#include <linux/io.h>
> ?#include <linux/kernel.h>
> +#include <linux/net_tstamp.h>
> ?#include <linux/phy.h>
> ?#include <linux/platform_device.h>
> +#include <linux/ptp_classify.h>
> ?#include <linux/slab.h>
> +#include <mach/ixp46x_ts.h>
> ?#include <mach/npe.h>
> ?#include <mach/qmgr.h>
>
> @@ -67,6 +70,14 @@
> ?#define RXFREE_QUEUE(port_id) ?(NPE_ID(port_id) + 26)
> ?#define TXDONE_QUEUE ? ? ? ? ? 31
>
> +#define PTP_SLAVE_MODE ? ? ? ? 1
> +#define PTP_MASTER_MODE ? ? ? ? ? ? ? ?2
> +#define PORT2CHANNEL(p) ? ? ? ? ? ? ? ?1
> +/*
> + * PHYSICAL_ID(p->id) ?
> + * TODO - Figure out correct mapping.
> + */
> +
> ?/* TX Control Registers */
> ?#define TX_CNTRL0_TX_EN ? ? ? ? ? ? ? ?0x01
> ?#define TX_CNTRL0_HALFDUPLEX ? 0x02
> @@ -171,6 +182,8 @@ struct port {
> ? ? ? ?int id; ? ? ? ? ? ? ? ? /* logical port ID */
> ? ? ? ?int speed, duplex;
> ? ? ? ?u8 firmware[4];
> + ? ? ? int hwts_tx_en;
> + ? ? ? int hwts_rx_en;
> ?};
>
> ?/* NPE message structure */
> @@ -246,6 +259,170 @@ static int ports_open;
> ?static struct port *npe_port_tab[MAX_NPES];
> ?static struct dma_pool *dma_pool;
>
> +static struct sock_filter ptp_filter[] = {
> + ? ? ? PTP_FILTER
> +};
> +
> +static int match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seq)
> +{
> + ? ? ? unsigned int type;
> + ? ? ? u16 *hi, *id;
> + ? ? ? u8 *lo, *data = skb->data;
> +
> + ? ? ? type = sk_run_filter(skb, ptp_filter, ARRAY_SIZE(ptp_filter));
> +
> + ? ? ? if (PTP_CLASS_V1_IPV4 == type) {
> +
> + ? ? ? ? ? ? ? id = (u16 *)(data + 42 + 30);
> + ? ? ? ? ? ? ? hi = (u16 *)(data + 42 + 22);
> + ? ? ? ? ? ? ? lo = data + 42 + 24;
> +
> + ? ? ? ? ? ? ? return (uid_hi == *hi &&
> + ? ? ? ? ? ? ? ? ? ? ? 0 == memcmp(&uid_lo, lo, sizeof(uid_lo)) &&
> + ? ? ? ? ? ? ? ? ? ? ? seq == *id);
> + ? ? ? }
> +
> + ? ? ? return 0;
> +}
> +
> +static void do_rx_timestamp(struct port *port, struct sk_buff *skb)
> +{
> + ? ? ? struct skb_shared_hwtstamps *shhwtstamps;
> + ? ? ? struct ixp46x_ts_regs *regs;
> + ? ? ? u64 ns;
> + ? ? ? u32 ch, hi, lo, val;
> + ? ? ? u16 uid, seq;
> +
> + ? ? ? if (!port->hwts_rx_en)
> + ? ? ? ? ? ? ? return;
> +
> + ? ? ? ch = PORT2CHANNEL(port);
> +
> + ? ? ? regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
> +
> + ? ? ? val = __raw_readl(&regs->channel[ch].Ch_Event);
> +
> + ? ? ? if (!(val & RX_SNAPSHOT_LOCKED))
> + ? ? ? ? ? ? ? return;
> +
> + ? ? ? lo = __raw_readl(&regs->channel[ch].SrcUUIDLo);
> + ? ? ? hi = __raw_readl(&regs->channel[ch].SrcUUIDHi);
> +
> + ? ? ? uid = hi & 0xffff;
> + ? ? ? seq = (hi >> 16) & 0xffff;
> +
> + ? ? ? if (!match(skb, htons(uid), htonl(lo), htons(seq)))
> + ? ? ? ? ? ? ? goto out;
> +
> + ? ? ? lo = __raw_readl(&regs->channel[ch].RxSnapLo);
> + ? ? ? hi = __raw_readl(&regs->channel[ch].RxSnapHi);
> + ? ? ? ns = ((u64) hi) << 32;
> + ? ? ? ns |= lo;
> + ? ? ? ns <<= TICKS_NS_SHIFT;
> +
> + ? ? ? shhwtstamps = skb_hwtstamps(skb);
> + ? ? ? memset(shhwtstamps, 0, sizeof(*shhwtstamps));
> + ? ? ? shhwtstamps->hwtstamp = ns_to_ktime(ns);
> +out:
> + ? ? ? __raw_writel(RX_SNAPSHOT_LOCKED, &regs->channel[ch].Ch_Event);
> +}
> +
> +static void do_tx_timestamp(struct port *port, struct sk_buff *skb)
> +{
> +#ifdef __ARMEB__
> + ? ? ? struct skb_shared_hwtstamps shhwtstamps;
> + ? ? ? struct ixp46x_ts_regs *regs;
> + ? ? ? union skb_shared_tx *shtx;
> + ? ? ? u64 ns;
> + ? ? ? u32 ch, cnt, hi, lo, val;
> +
> + ? ? ? shtx = skb_tx(skb);
> +
> + ? ? ? if (!shtx->in_progress)
> + ? ? ? ? ? ? ? return;
> +
> + ? ? ? ch = PORT2CHANNEL(port);
> +
> + ? ? ? regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
> +
> + ? ? ? /*
> + ? ? ? ?* This really stinks, but we have to poll for the Tx time stamp.
> + ? ? ? ?* Usually, the time stamp is ready after 4 to 6 microseconds.
> + ? ? ? ?*/
> + ? ? ? for (cnt = 0; cnt < 100; cnt++) {
> + ? ? ? ? ? ? ? val = __raw_readl(&regs->channel[ch].Ch_Event);
> + ? ? ? ? ? ? ? if (val & TX_SNAPSHOT_LOCKED)
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? udelay(1);

You want to get stuff as fast as possible, but there is a udelay()
that just chews up CPU time.  Would cpu_relax() be sufficient with a
time-based exit condition in the loop?

> + ? ? ? }
> + ? ? ? if (!(val & TX_SNAPSHOT_LOCKED)) {
> + ? ? ? ? ? ? ? shtx->in_progress = 0;
> + ? ? ? ? ? ? ? return;
> + ? ? ? }
> +
> + ? ? ? lo = __raw_readl(&regs->channel[ch].TxSnapLo);
> + ? ? ? hi = __raw_readl(&regs->channel[ch].TxSnapHi);
> + ? ? ? ns = ((u64) hi) << 32;
> + ? ? ? ns |= lo;
> + ? ? ? ns <<= TICKS_NS_SHIFT;
> +
> + ? ? ? memset(&shhwtstamps, 0, sizeof(shhwtstamps));
> + ? ? ? shhwtstamps.hwtstamp = ns_to_ktime(ns);
> + ? ? ? skb_tstamp_tx(skb, &shhwtstamps);
> +
> + ? ? ? __raw_writel(TX_SNAPSHOT_LOCKED, &regs->channel[ch].Ch_Event);
> +#endif
> +}
> +
> +static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
> +{
> + ? ? ? struct hwtstamp_config cfg;
> + ? ? ? struct ixp46x_ts_regs *regs;
> + ? ? ? struct port *port = netdev_priv(netdev);
> + ? ? ? int ch;
> +
> + ? ? ? if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
> + ? ? ? ? ? ? ? return -EFAULT;
> +
> + ? ? ? if (cfg.flags) /* reserved for future extensions */
> + ? ? ? ? ? ? ? return -EINVAL;
> +
> + ? ? ? ch = PORT2CHANNEL(port);
> + ? ? ? regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
> +
> + ? ? ? switch (cfg.tx_type) {
> + ? ? ? case HWTSTAMP_TX_OFF:
> + ? ? ? ? ? ? ? port->hwts_tx_en = 0;
> + ? ? ? ? ? ? ? break;
> + ? ? ? case HWTSTAMP_TX_ON:
> + ? ? ? ? ? ? ? port->hwts_tx_en = 1;
> + ? ? ? ? ? ? ? break;
> + ? ? ? default:
> + ? ? ? ? ? ? ? return -ERANGE;
> + ? ? ? }
> +
> + ? ? ? switch (cfg.rx_filter) {
> + ? ? ? case HWTSTAMP_FILTER_NONE:
> + ? ? ? ? ? ? ? port->hwts_rx_en = 0;
> + ? ? ? ? ? ? ? break;
> + ? ? ? case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
> + ? ? ? ? ? ? ? port->hwts_rx_en = PTP_SLAVE_MODE;
> + ? ? ? ? ? ? ? __raw_writel(0, &regs->channel[ch].Ch_Control);
> + ? ? ? ? ? ? ? break;
> + ? ? ? case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
> + ? ? ? ? ? ? ? port->hwts_rx_en = PTP_MASTER_MODE;
> + ? ? ? ? ? ? ? __raw_writel(MASTER_MODE, &regs->channel[ch].Ch_Control);
> + ? ? ? ? ? ? ? break;
> + ? ? ? default:
> + ? ? ? ? ? ? ? return -ERANGE;
> + ? ? ? }
> +
> + ? ? ? /* Clear out any old time stamps. */
> + ? ? ? __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
> + ? ? ? ? ? ? ? ? ? ?&regs->channel[ch].Ch_Event);
> +
> + ? ? ? return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
> +}
>
> ?static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
> ? ? ? ? ? ? ? ? ? ? ? ? ? int write, u16 cmd)
> @@ -573,6 +750,7 @@ static int eth_poll(struct napi_struct *napi, int budget)
>
> ? ? ? ? ? ? ? ?debug_pkt(dev, "eth_poll", skb->data, skb->len);
>
> + ? ? ? ? ? ? ? do_rx_timestamp(port, skb);
> ? ? ? ? ? ? ? ?skb->protocol = eth_type_trans(skb, dev);
> ? ? ? ? ? ? ? ?dev->stats.rx_packets++;
> ? ? ? ? ? ? ? ?dev->stats.rx_bytes += skb->len;
> @@ -652,6 +830,7 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
> ? ? ? ?void *mem;
> ? ? ? ?u32 phys;
> ? ? ? ?struct desc *desc;
> + ? ? ? union skb_shared_tx *shtx;
>
> ?#if DEBUG_TX
> ? ? ? ?printk(KERN_DEBUG "%s: eth_xmit\n", dev->name);
> @@ -665,6 +844,10 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
>
> ? ? ? ?debug_pkt(dev, "eth_xmit", skb->data, skb->len);
>
> + ? ? ? shtx = skb_tx(skb);
> + ? ? ? if (unlikely(shtx->hardware && port->hwts_tx_en))
> + ? ? ? ? ? ? ? shtx->in_progress = 1;
> +
> ? ? ? ?len = skb->len;
> ?#ifdef __ARMEB__
> ? ? ? ?offset = 0; /* no need to keep alignment */
> @@ -728,6 +911,9 @@ static int eth_xmit(struct sk_buff *skb, struct net_device *dev)
> ?#if DEBUG_TX
> ? ? ? ?printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
> ?#endif
> +
> + ? ? ? do_tx_timestamp(port, skb);
> +
> ? ? ? ?return NETDEV_TX_OK;
> ?}
>
> @@ -783,6 +969,9 @@ static int eth_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
> ? ? ? ?if (!netif_running(dev))
> ? ? ? ? ? ? ? ?return -EINVAL;
>
> + ? ? ? if (cpu_is_ixp46x() && cmd == SIOCSHWTSTAMP)
> + ? ? ? ? ? ? ? return hwtstamp_ioctl(dev, req, cmd);
> +
> ? ? ? ?return phy_mii_ioctl(port->phydev, req, cmd);
> ?}
>
> @@ -1171,6 +1360,11 @@ static int __devinit eth_init_one(struct platform_device *pdev)
> ? ? ? ?char phy_id[MII_BUS_ID_SIZE + 3];
> ? ? ? ?int err;
>
> + ? ? ? if (sk_chk_filter(ptp_filter, ARRAY_SIZE(ptp_filter))) {
> + ? ? ? ? ? ? ? pr_err("ixp4xx_eth: bad ptp filter\n");
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> ? ? ? ?if (!(dev = alloc_etherdev(sizeof(struct port))))
> ? ? ? ? ? ? ? ?return -ENOMEM;
>
> diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
> index 3b7bd73..9fb35f6 100644
> --- a/drivers/ptp/Kconfig
> +++ b/drivers/ptp/Kconfig
> @@ -48,4 +48,17 @@ config PTP_1588_CLOCK_GIANFAR
> ? ? ? ? ?To compile this driver as a module, choose M here: the module
> ? ? ? ? ?will be called gianfar_ptp.
>
> +config PTP_1588_CLOCK_IXP46X
> + ? ? ? tristate "Intel IXP46x as PTP clock"
> + ? ? ? depends on PTP_1588_CLOCK
> + ? ? ? depends on IXP4XX_ETH
> + ? ? ? help
> + ? ? ? ? This driver adds support for using the IXP46X as a PTP
> + ? ? ? ? clock. This clock is only useful if your PTP programs are
> + ? ? ? ? getting hardware time stamps on the PTP Ethernet packets
> + ? ? ? ? using the SO_TIMESTAMPING API.
> +
> + ? ? ? ? To compile this driver as a module, choose M here: the module
> + ? ? ? ? will be called ptp_ixp46x.
> +
> ?endmenu
> diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
> index 1651d52..5018f58 100644
> --- a/drivers/ptp/Makefile
> +++ b/drivers/ptp/Makefile
> @@ -4,3 +4,4 @@
>
> ?obj-$(CONFIG_PTP_1588_CLOCK) ? ? ? ? ? += ptp_clock.o
> ?obj-$(CONFIG_PTP_1588_CLOCK_LINUX) ? ? += ptp_linux.o
> +obj-$(CONFIG_PTP_1588_CLOCK_IXP46X) ? ?+= ptp_ixp46x.o
> diff --git a/drivers/ptp/ptp_ixp46x.c b/drivers/ptp/ptp_ixp46x.c
> new file mode 100644
> index 0000000..22c5bc3
> --- /dev/null
> +++ b/drivers/ptp/ptp_ixp46x.c
> @@ -0,0 +1,231 @@
> +/*
> + * PTP 1588 clock using the IXP46X
> + *
> + * Copyright (C) 2010 OMICRON electronics GmbH
> + *
> + * ?This program is free software; you can redistribute it and/or modify
> + * ?it under the terms of the GNU General Public License as published by
> + * ?the Free Software Foundation; either version 2 of the License, or
> + * ?(at your option) any later version.
> + *
> + * ?This program is distributed in the hope that it will be useful,
> + * ?but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * ?GNU General Public License for more details.
> + *
> + * ?You should have received a copy of the GNU General Public License
> + * ?along with this program; if not, write to the Free Software
> + * ?Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +
> +#include <linux/ptp_clock_kernel.h>
> +#include <mach/ixp46x_ts.h>
> +
> +DEFINE_SPINLOCK(register_lock);
> +
> +/*
> + * Register access functions
> + */
> +
> +static inline u32 ixp_read(volatile unsigned __iomem *addr)
> +{
> + ? ? ? u32 val;
> + ? ? ? val = __raw_readl(addr);
> + ? ? ? return val;
> +}

return __raw_readl(addr) perhaps?

> +
> +static inline void ixp_write(volatile unsigned __iomem *addr, u32 val)
> +{
> + ? ? ? __raw_writel(val, addr);
> +}
> +
> +static u64 sys_time_read(struct ixp46x_ts_regs *regs)
> +{
> + ? ? ? u64 ns;
> + ? ? ? u32 lo, hi;
> +
> + ? ? ? lo = ixp_read(&regs->SysTimeLo);
> + ? ? ? hi = ixp_read(&regs->SysTimeHi);
> +
> + ? ? ? ns = ((u64) hi) << 32;
> + ? ? ? ns |= lo;
> + ? ? ? ns <<= TICKS_NS_SHIFT;
> +
> + ? ? ? return ns;
> +}
> +
> +static void sys_time_write(struct ixp46x_ts_regs *regs, u64 ns)

Should use the ptp_ixp_ prefix on these functions too.

> +{
> + ? ? ? u32 hi, lo;
> +
> + ? ? ? ns >>= TICKS_NS_SHIFT;
> + ? ? ? hi = ns >> 32;
> + ? ? ? lo = ns & 0xffffffff;
> +
> + ? ? ? ixp_write(&regs->SysTimeLo, lo);
> + ? ? ? ixp_write(&regs->SysTimeHi, hi);
> +}
> +
> +/*
> + * PTP clock operations
> + */
> +
> +static int ptp_ixp_adjfreq(void *priv, s32 ppb)
> +{
> + ? ? ? u64 adj;
> + ? ? ? u32 diff, addend;
> + ? ? ? int neg_adj = 0;
> + ? ? ? struct ixp46x_ts_regs *regs = priv;
> +
> + ? ? ? if (!ppb)
> + ? ? ? ? ? ? ? return 0;
> +
> + ? ? ? if (ppb < 0) {
> + ? ? ? ? ? ? ? neg_adj = 1;
> + ? ? ? ? ? ? ? ppb = -ppb;
> + ? ? ? }
> + ? ? ? addend = DEFAULT_ADDEND;
> + ? ? ? adj = addend;
> + ? ? ? adj *= ppb;
> + ? ? ? diff = div_u64(adj, 1000000000ULL);
> +
> + ? ? ? addend = neg_adj ? addend - diff : addend + diff;
> +
> + ? ? ? ixp_write(&regs->Addend, addend);
> +
> + ? ? ? return 0;
> +}
> +
> +static int ptp_ixp_adjtime(void *priv, struct timespec *ts)
> +{
> + ? ? ? s64 delta, now;
> + ? ? ? unsigned long flags;
> + ? ? ? struct ixp46x_ts_regs *regs = priv;
> +
> + ? ? ? delta = 1000000000LL * ts->tv_sec;
> + ? ? ? delta += ts->tv_nsec;
> +
> + ? ? ? spin_lock_irqsave(&register_lock, flags);
> +
> + ? ? ? now = sys_time_read(regs);
> + ? ? ? now += delta;
> + ? ? ? sys_time_write(regs, now);
> +
> + ? ? ? spin_unlock_irqrestore(&register_lock, flags);
> +
> + ? ? ? return 0;
> +}
> +
> +static int ptp_ixp_gettime(void *priv, struct timespec *ts)
> +{
> + ? ? ? u64 ns;
> + ? ? ? u32 remainder;
> + ? ? ? unsigned long flags;
> + ? ? ? struct ixp46x_ts_regs *regs = priv;
> +
> + ? ? ? spin_lock_irqsave(&register_lock, flags);
> +
> + ? ? ? ns = sys_time_read(regs);
> +
> + ? ? ? spin_unlock_irqrestore(&register_lock, flags);
> +
> + ? ? ? ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
> + ? ? ? ts->tv_nsec = remainder;
> + ? ? ? return 0;
> +}
> +
> +static int ptp_ixp_settime(void *priv, struct timespec *ts)
> +{
> + ? ? ? u64 ns;
> + ? ? ? unsigned long flags;
> + ? ? ? struct ixp46x_ts_regs *regs = priv;
> +
> + ? ? ? ns = ts->tv_sec * 1000000000ULL;
> + ? ? ? ns += ts->tv_nsec;
> +
> + ? ? ? spin_lock_irqsave(&register_lock, flags);
> +
> + ? ? ? sys_time_write(regs, ns);
> +
> + ? ? ? spin_unlock_irqrestore(&register_lock, flags);
> +
> + ? ? ? return 0;
> +}
> +
> +static int ptp_ixp_gettimer(void *priv, int index, struct itimerspec *ts)
> +{
> + ? ? ? /* We do not offer any ancillary features at all. */
> + ? ? ? return -EOPNOTSUPP;
> +}
> +
> +static int ptp_ixp_settimer(void *p, int i, int abs, struct itimerspec *ts)
> +{
> + ? ? ? /* We do not offer any ancillary features at all. */
> + ? ? ? return -EOPNOTSUPP;
> +}
> +
> +static int ptp_ixp_enable(void *priv, struct ptp_clock_request *rq, int on)
> +{
> + ? ? ? /* We do not offer any ancillary features at all. */
> + ? ? ? return -EOPNOTSUPP;
> +}
> +
> +static struct ptp_clock_info ptp_ixp_caps = {
> + ? ? ? .owner ? ? ? ? ?= THIS_MODULE,
> + ? ? ? .name ? ? ? ? ? = "IXP46X timer",
> + ? ? ? .max_adj ? ? ? ?= 512000,
> + ? ? ? .n_alarm ? ? ? ?= 0,
> + ? ? ? .n_ext_ts ? ? ? = 0,
> + ? ? ? .n_per_out ? ? ?= 0,
> + ? ? ? .pps ? ? ? ? ? ?= 0,
> + ? ? ? .priv ? ? ? ? ? = NULL,

If the value is '0' or NULL, just leave them out of the structure initializer.

> + ? ? ? .adjfreq ? ? ? ?= ptp_ixp_adjfreq,
> + ? ? ? .adjtime ? ? ? ?= ptp_ixp_adjtime,
> + ? ? ? .gettime ? ? ? ?= ptp_ixp_gettime,
> + ? ? ? .settime ? ? ? ?= ptp_ixp_settime,
> + ? ? ? .gettimer ? ? ? = ptp_ixp_gettimer,
> + ? ? ? .settimer ? ? ? = ptp_ixp_settimer,
> + ? ? ? .enable ? ? ? ? = ptp_ixp_enable,
> +};
> +
> +/* module operations */
> +
> +static struct {
> + ? ? ? struct ixp46x_ts_regs *regs;
> + ? ? ? struct ptp_clock *ptp_clock;
> +} ixp_clock;
> +
> +static void __exit ptp_ixp_exit(void)
> +{
> + ? ? ? ptp_clock_unregister(ixp_clock.ptp_clock);
> +}
> +
> +static int __init ptp_ixp_init(void)
> +{
> + ? ? ? ixp_clock.regs =
> + ? ? ? ? ? ? ? (struct ixp46x_ts_regs __iomem *)IXP4XX_TIMESYNC_BASE_VIRT;
> +
> + ? ? ? ptp_ixp_caps.priv = ixp_clock.regs;
> +
> + ? ? ? ixp_clock.ptp_clock = ptp_clock_register(&ptp_ixp_caps);
> +
> + ? ? ? if (IS_ERR(ixp_clock.ptp_clock))
> + ? ? ? ? ? ? ? return PTR_ERR(ixp_clock.ptp_clock);
> +
> + ? ? ? ixp_write(&ixp_clock.regs->Addend, DEFAULT_ADDEND);
> +
> + ? ? ? return 0;
> +}
> +
> +module_init(ptp_ixp_init);
> +module_exit(ptp_ixp_exit);

Keep module_init and module_exit with their respective function declarations.

g.


From grant.likely at secretlab.ca  Tue Jun 15 14:49:13 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 15 Jun 2010 12:49:13 -0600
Subject: [PATCH 12/12] ptp: Added a clock driver for the National 
	Semiconductor PHYTER.
In-Reply-To: <37f5015b186bdd51f8451ade042f90c8b39a5cc8.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<37f5015b186bdd51f8451ade042f90c8b39a5cc8.1276615626.git.richard.cochran@omicron.at>
Message-ID: <AANLkTilqd-wxqMWDxssC-XMDJqZ8iIiSrvp2t8xARAQV@mail.gmail.com>

On Tue, Jun 15, 2010 at 10:10 AM, Richard Cochran
<richardcochran at gmail.com> wrote:
> This patch adds support for the PTP clock found on the DP83640. Only the
> basic clock operations have been implemented.
>
> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
> ---
> ?drivers/net/phy/Kconfig ? | ? 11 +++
> ?drivers/net/phy/dp83640.c | ?158 ++++++++++++++++++++++++++++++++++++++++++++-
> ?2 files changed, 168 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index 430cab1..507c68a 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -79,9 +79,20 @@ config NATIONAL_PHY
>
> ?config DP83640_PHY
> ? ? ? ?tristate "Driver for the National Semiconductor DP83640 PHYTER"
> + ? ? ? depends on PTP_1588_CLOCK
> + ? ? ? depends on NETWORK_PHY_TIMESTAMPING

Won't this break things for existing DP83640 users?

> ? ? ? ?---help---
> ? ? ? ? ?Supports the DP83640 PHYTER with IEEE 1588 features.
>
> + ? ? ? ? This driver adds support for using the DP83640 as a PTP
> + ? ? ? ? clock. This clock is only useful if your PTP programs are
> + ? ? ? ? getting hardware time stamps on the PTP Ethernet packets
> + ? ? ? ? using the SO_TIMESTAMPING API.
> +
> + ? ? ? ? In order for this to work, your MAC driver must also
> + ? ? ? ? implement the the skb_tx_timetamp() and skb_rx_timetamp()
> + ? ? ? ? functions.
> +
> ?config STE10XP
> ? ? ? ?depends on PHYLIB
> ? ? ? ?tristate "Driver for STMicroelectronics STe10Xp PHYs"
> diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
> index a3217ea..21eadc3 100644
> --- a/drivers/net/phy/dp83640.c
> +++ b/drivers/net/phy/dp83640.c
> @@ -26,6 +26,7 @@
> ?#include <linux/netdevice.h>
> ?#include <linux/phy.h>
> ?#include <linux/ptp_classify.h>
> +#include <linux/ptp_clock_kernel.h>
>
> ?#include "dp83640_reg.h"
>
> @@ -45,10 +46,13 @@ struct rxts {
> ?};
>
> ?struct dp83640_private {
> + ? ? ? struct phy_device *phydev;
> ? ? ? ?int hwts_tx_en;
> ? ? ? ?int hwts_rx_en;
> ? ? ? ?int layer;
> ? ? ? ?int version;
> + ? ? ? /* protects PTP_TDR register from concurrent access */
> + ? ? ? spinlock_t ptp_tdr_lock;
> ? ? ? ?/* protects extended registers from concurrent access */
> ? ? ? ?spinlock_t extreg_lock;
> ? ? ? ?int page;
> @@ -60,6 +64,9 @@ struct dp83640_private {
>
> ?/* globals */
>
> +static struct ptp_clock *dp83640_clock;
> +DEFINE_SPINLOCK(clock_lock); /* protects the one and only dp83640_clock */

Why only one?  Is it not possible to have 2 of these PHYs in a system?

> +
> ?static struct sock_filter ptp_filter[] = {
> ? ? ? ?PTP_FILTER
> ?};
> @@ -99,6 +106,129 @@ static void ext_write(struct phy_device *phydev, int page, u32 regnum, u16 val)
> ? ? ? ?spin_unlock(&dp83640->extreg_lock);
> ?}
>
> +static int tdr_write(struct dp83640_private *dp83640,
> + ? ? ? ? ? ? ? ? ? ?struct timespec *ts, u16 cmd)
> +{
> + ? ? ? struct phy_device *phydev = dp83640->phydev;
> +
> + ? ? ? spin_lock(&dp83640->ptp_tdr_lock);
> +
> + ? ? ? ext_write(phydev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
> + ? ? ? ext_write(phydev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); ? /* ns[31:16] */
> + ? ? ? ext_write(phydev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
> + ? ? ? ext_write(phydev, PAGE4, PTP_TDR, ts->tv_sec >> 16); ? ?/* sec[31:16] */
> +
> + ? ? ? ext_write(phydev, PAGE4, PTP_CTL, cmd);
> +
> + ? ? ? spin_unlock(&dp83640->ptp_tdr_lock);
> +
> + ? ? ? return 0;
> +}
> +
> +/* ptp clock methods */
> +
> +static int ptp_dp83640_adjfreq(void *priv, s32 ppb)
> +{
> + ? ? ? struct dp83640_private *dp83640 = priv;
> + ? ? ? struct phy_device *phydev = dp83640->phydev;
> + ? ? ? u64 rate;
> + ? ? ? int neg_adj = 0;
> + ? ? ? u16 hi, lo;
> +
> + ? ? ? if (!ppb)
> + ? ? ? ? ? ? ? return 0;
> +
> + ? ? ? if (ppb < 0) {
> + ? ? ? ? ? ? ? neg_adj = 1;
> + ? ? ? ? ? ? ? ppb = -ppb;
> + ? ? ? }
> + ? ? ? rate = ppb;
> + ? ? ? rate <<= 26;
> + ? ? ? rate = div_u64(rate, 1953125);
> +
> + ? ? ? hi = (rate >> 16) & PTP_RATE_HI_MASK;
> + ? ? ? if (neg_adj)
> + ? ? ? ? ? ? ? hi |= PTP_RATE_DIR;
> +
> + ? ? ? lo = rate & 0xffff;
> +
> + ? ? ? ext_write(phydev, PAGE4, PTP_RATEH, hi);
> + ? ? ? ext_write(phydev, PAGE4, PTP_RATEL, lo);
> +
> + ? ? ? return 0;
> +}
> +
> +static int ptp_dp83640_adjtime(void *priv, struct timespec *ts)
> +{
> + ? ? ? return tdr_write(priv, ts, PTP_STEP_CLK);
> +}
> +
> +static int ptp_dp83640_gettime(void *priv, struct timespec *ts)
> +{
> + ? ? ? struct dp83640_private *dp83640 = priv;
> + ? ? ? struct phy_device *phydev = dp83640->phydev;
> + ? ? ? unsigned int val[4];
> +
> + ? ? ? spin_lock(&dp83640->ptp_tdr_lock);
> +
> + ? ? ? ext_write(phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
> +
> + ? ? ? val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
> + ? ? ? val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
> + ? ? ? val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
> + ? ? ? val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
> +
> + ? ? ? spin_unlock(&dp83640->ptp_tdr_lock);
> +
> + ? ? ? ts->tv_nsec = val[0] | (val[1] << 16);
> + ? ? ? ts->tv_sec ?= val[2] | (val[3] << 16);
> +
> + ? ? ? return 0;
> +}
> +
> +static int ptp_dp83640_settime(void *priv, struct timespec *ts)
> +{
> + ? ? ? return tdr_write(priv, ts, PTP_LOAD_CLK);
> +}
> +
> +static int ptp_dp83640_gettimer(void *priv, int index, struct itimerspec *ts)
> +{
> + ? ? ? /* We do not (yet) offer any ancillary features. */
> + ? ? ? return -EOPNOTSUPP;
> +}
> +
> +static int ptp_dp83640_settimer(void *p, int i, int abs, struct itimerspec *ts)
> +{
> + ? ? ? /* We do not (yet) offer any ancillary features. */
> + ? ? ? return -EOPNOTSUPP;
> +}
> +
> +static int ptp_dp83640_enable(void *priv, struct ptp_clock_request *rq, int on)
> +{
> + ? ? ? /* We do not (yet) offer any ancillary features. */
> + ? ? ? return -EOPNOTSUPP;
> +}
> +
> +static struct ptp_clock_info ptp_dp83640_caps = {
> + ? ? ? .owner ? ? ? ? ?= THIS_MODULE,
> + ? ? ? .name ? ? ? ? ? = "dp83640 timer",
> + ? ? ? .max_adj ? ? ? ?= 1953124,
> + ? ? ? .n_alarm ? ? ? ?= 0,
> + ? ? ? .n_ext_ts ? ? ? = 0,
> + ? ? ? .n_per_out ? ? ?= 0,
> + ? ? ? .pps ? ? ? ? ? ?= 0,
> + ? ? ? .priv ? ? ? ? ? = NULL,

ditto here, can leave the 0s and nulls out.

> + ? ? ? .adjfreq ? ? ? ?= ptp_dp83640_adjfreq,
> + ? ? ? .adjtime ? ? ? ?= ptp_dp83640_adjtime,
> + ? ? ? .gettime ? ? ? ?= ptp_dp83640_gettime,
> + ? ? ? .settime ? ? ? ?= ptp_dp83640_settime,
> + ? ? ? .gettimer ? ? ? = ptp_dp83640_gettimer,
> + ? ? ? .settimer ? ? ? = ptp_dp83640_settimer,
> + ? ? ? .enable ? ? ? ? = ptp_dp83640_enable,
> +};
> +
> +/* time stamping methods */
> +
> ?static int expired(struct rxts *rxts)
> ?{
> ? ? ? ?return time_after(jiffies, rxts->tmo);
> @@ -144,6 +274,7 @@ static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
> ?static int dp83640_probe(struct phy_device *phydev)
> ?{
> ? ? ? ?struct dp83640_private *dp83640;
> + ? ? ? unsigned long flags;
> ? ? ? ?int i;
>
> ? ? ? ?if (sk_chk_filter(ptp_filter, ARRAY_SIZE(ptp_filter))) {
> @@ -155,8 +286,9 @@ static int dp83640_probe(struct phy_device *phydev)
> ? ? ? ?if (!dp83640)
> ? ? ? ? ? ? ? ?return -ENOMEM;
>
> + ? ? ? dp83640->phydev = phydev;
> + ? ? ? spin_lock_init(&dp83640->ptp_tdr_lock);
> ? ? ? ?spin_lock_init(&dp83640->extreg_lock);
> -
> ? ? ? ?INIT_LIST_HEAD(&dp83640->rxts);
> ? ? ? ?INIT_LIST_HEAD(&dp83640->pool);
>
> @@ -165,12 +297,36 @@ static int dp83640_probe(struct phy_device *phydev)
>
> ? ? ? ?phydev->priv = dp83640;
>
> + ? ? ? spin_lock_irqsave(&clock_lock, flags);
> +
> + ? ? ? if (!dp83640_clock) {
> + ? ? ? ? ? ? ? ptp_dp83640_caps.priv = dp83640;
> + ? ? ? ? ? ? ? dp83640_clock = ptp_clock_register(&ptp_dp83640_caps);
> + ? ? ? ? ? ? ? if (IS_ERR(dp83640_clock)) {
> + ? ? ? ? ? ? ? ? ? ? ? spin_unlock_irqrestore(&clock_lock, flags);
> + ? ? ? ? ? ? ? ? ? ? ? kfree(dp83640);
> + ? ? ? ? ? ? ? ? ? ? ? return PTR_ERR(dp83640_clock);
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> + ? ? ? spin_unlock_irqrestore(&clock_lock, flags);
> +
> ? ? ? ?return 0;
> ?}
>
> ?static void dp83640_remove(struct phy_device *phydev)
> ?{
> ? ? ? ?struct dp83640_private *dp83640 = phydev->priv;
> + ? ? ? unsigned long flags;
> +
> + ? ? ? spin_lock_irqsave(&clock_lock, flags);
> +
> + ? ? ? if (ptp_dp83640_caps.priv == dp83640) {
> + ? ? ? ? ? ? ? ptp_clock_unregister(dp83640_clock);
> + ? ? ? ? ? ? ? dp83640_clock = NULL;
> + ? ? ? ? ? ? ? ptp_dp83640_caps.priv = NULL;
> + ? ? ? }
> + ? ? ? spin_unlock_irqrestore(&clock_lock, flags);
> +
> ? ? ? ?kfree(dp83640);
> ?}
>
> --
> 1.6.3.3
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From paulmck at linux.vnet.ibm.com  Tue Jun 15 15:02:54 2010
From: paulmck at linux.vnet.ibm.com (Paul E. McKenney)
Date: Tue, 15 Jun 2010 12:02:54 -0700
Subject: Userspace helpers at static addresses on ARM [was: Re: [PATCH]
	fix the "unknown" case]
In-Reply-To: <20100615182919.GB11394@Krystal>
References: <20100614220600.GA15130@linux.vnet.ibm.com>
	<OF014FB97C.3968191D-ONC1257743.0043E356-C1257743.004525C9@de.ibm.com>
	<20100615150727.GC2304@linux.vnet.ibm.com>
	<OFCD1BC564.0035E292-ONC1257743.0057CB53-C1257743.0058903F@de.ibm.com>
	<20100615170001.GG2304@linux.vnet.ibm.com>
	<20100615170315.GA7835@Krystal>
	<OFC507BE7B.F11411B7-ONC1257743.005F924F-C1257743.00605E5E@de.ibm.com>
	<20100615182919.GB11394@Krystal>
Message-ID: <20100615190254.GH2304@linux.vnet.ibm.com>

On Tue, Jun 15, 2010 at 02:29:19PM -0400, Mathieu Desnoyers wrote:
> * Ulrich Weigand (Ulrich.Weigand at de.ibm.com) wrote:
> > Mathieu Desnoyers <mathieu.desnoyers at efficios.com> wrote on 06/15/2010
> > 07:03:15 PM:
> > 
> > > I wonder starting with which Linux kernel version __kernel_dmb appeared.
> > > Tying ourself directly to a Linux kernel ABI might complicate things.
> > >
> > > Is this ABI presented in a vDSO or userland have to go through a system
> > call ?
> > > Is there any way to probe for its availability ?
> > 
> > This looks sort-of like a vDSO, except without the DSO part :-)
> > 
> > The kernel simply makes the code available at a fixed address that is
> > directly callable by user space.  See the comments in
> > linux/arch/arm/kernel/entry-armv.S:
> > 
> 
> Hrm, statically addressed shared objects. The security guys should be freaking
> out here. This can sadly make stack overflow exploitation much, much, easier
> because of lack of randomization of addresses where the code is located. :-/
> 
> About the original topic of our discussion:
> Thanks for the explanation below. I think making urcu test for the kernel
> feature at library load seems like the best portable solution so far. We can
> directly use the specific memory barriers when armv7+ is specified, and check
> at runtime if the kernel feature is there for "generic" arm build. For generic
> ARM build where we discover that the kernel lacks the proper features, we could
> rely on Paul's double-fake-mutex scheme (assuming we audit glibc pthreads to
> ensure the proper memory barriers are there). If we find out that even pthreads
> mutexes got the barriers wrong there, then we should refuse to load the library
> altogether.

OK.  The gcc patches were for __sync_sychronize(), which I have replaced
with a "dmb" asm, and for __sync_lock_release(), which I do not use.
If I understand Paolo and Uli correctly (a dubious assumption, to be
sure), then the memory barriers and atomicity should be supplied by
the libraries and/or kernel for the other __sync_ primitives.

So for ARMv7, my prior patch should suffice.  (Or am I still missing
something?)

Additional patches are no doubt required for other ARM flavors, and
perhaps also for older compilers and kernels.

							Thanx, Paul

> Thanks,
> 
> Mathieu
> 
> > /*
> >  * User helpers.
> >  *
> >  * These are segment of kernel provided user code reachable from user space
> >  * at a fixed address in kernel memory.  This is used to provide user space
> >  * with some operations which require kernel help because of unimplemented
> >  * native feature and/or instructions in many ARM CPUs. The idea is for
> >  * this code to be executed directly in user mode for best efficiency but
> >  * which is too intimate with the kernel counter part to be left to user
> >  * libraries.  In fact this code might even differ from one CPU to another
> >  * depending on the available  instruction set and restrictions like on
> >  * SMP systems.  In other words, the kernel reserves the right to change
> >  * this code as needed without warning. Only the entry points and their
> >  * results are guaranteed to be stable.
> >  *
> >  * Each segment is 32-byte aligned and will be moved to the top of the high
> >  * vector page.  New segments (if ever needed) must be added in front of
> >  * existing ones.  This mechanism should be used only for things that are
> >  * really small and justified, and not be abused freely.
> >  *
> >  * User space is expected to implement those things inline when optimizing
> >  * for a processor that has the necessary native support, but only if such
> >  * resulting binaries are already to be incompatible with earlier ARM
> >  * processors due to the use of unsupported instructions other than what
> >  * is provided here.  In other words don't make binaries unable to run on
> >  * earlier processors just for the sake of not using these kernel helpers
> >  * if your compiled code is not going to use the new instructions for other
> >  * purpose.
> >  */
> > 
> > 
> > /*
> >  * Reference prototype:
> >  *
> >  *           void __kernel_memory_barrier(void)
> >  *
> >  * Input:
> >  *
> >  *           lr = return address
> >  *
> >  * Output:
> >  *
> >  *           none
> >  *
> >  * Clobbered:
> >  *
> >  *           none
> >  *
> >  * Definition and user space usage example:
> >  *
> >  *           typedef void (__kernel_dmb_t)(void);
> >  *           #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
> >  *
> >  * Apply any needed memory barrier to preserve consistency with data
> > modified
> >  * manually and __kuser_cmpxchg usage.
> >  *
> >  * This could be used as follows:
> >  *
> >  * #define __kernel_dmb() \
> >  *         asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0,
> > #95" \
> >  *		         : : : "r0", "lr","cc" )
> >  */
> > 
> > 
> > As far as I can see, the only provision to check whether a feature is
> > available
> > is this one:
> > 
> > /*
> >  * Reference declaration:
> >  *
> >  *           extern unsigned int __kernel_helper_version;
> >  *
> >  * Definition and user space usage example:
> >  *
> >  *           #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
> >  *
> >  * User space may read this to determine the curent number of helpers
> >  * available.
> >  */
> > 
> > However, note that libgcc code does not perform this check, it simply
> > assumes
> > the above routine to be present.
> > 
> > The __kernel_dmb (which is the most recently added helper available in
> > current
> > mainline) seems to have been available since kernel 2.6.15, so presumably
> > code
> > using any of the GCC sync primitives would simply fail on any older kernel,
> > unless I'm missing something here ...
> > 
> > 
> > Mit freundlichen Gruessen / Best Regards
> > 
> > Ulrich Weigand
> > 
> > --
> >   Dr. Ulrich Weigand | Phone: +49-7031/16-3727
> >   STSM, GNU compiler and toolchain for Linux on System z and Cell/B.E.
> >   IBM Deutschland Research & Development GmbH
> >   Vorsitzender des Aufsichtsrats: Martin Jetter | Gesch?ftsf?hrung: Dirk
> > Wittkopp
> >   Sitz der Gesellschaft: B?blingen | Registergericht: Amtsgericht
> > Stuttgart, HRB 243294
> > 
> 
> -- 
> Mathieu Desnoyers
> Operating System Efficiency R&D Consultant
> EfficiOS Inc.
> http://www.efficios.com


From grant.likely at secretlab.ca  Tue Jun 15 15:11:30 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Tue, 15 Jun 2010 13:11:30 -0600
Subject: [PATCH 08/12] ptp: Added a brand new class driver for ptp clocks.
In-Reply-To: <4a030d2bace90f089f2f3f61496b918c6f1dfb52.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<4a030d2bace90f089f2f3f61496b918c6f1dfb52.1276615626.git.richard.cochran@omicron.at>
Message-ID: <AANLkTinYjzfChsN0AB5W6kOh6xJYPJtoEq941pG8WbmS@mail.gmail.com>

On Tue, Jun 15, 2010 at 10:09 AM, Richard Cochran
<richardcochran at gmail.com> wrote:
> This patch adds an infrastructure for hardware clocks that implement
> IEEE 1588, the Precision Time Protocol (PTP). A class driver offers a
> registration method to particular hardware clock drivers. Each clock is
> exposed to user space as a character device with ioctls that allow tuning
> of the PTP clock.
>
> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>

Hi Richard,

Some more comments on this patch...

> ---
> ?Documentation/ptp/ptp.txt ? ? ? ?| ? 95 +++++++
> ?Documentation/ptp/testptp.c ? ? ?| ?269 ++++++++++++++++++++
> ?Documentation/ptp/testptp.mk ? ? | ? 33 +++
> ?drivers/Kconfig ? ? ? ? ? ? ? ? ?| ? ?2 +
> ?drivers/Makefile ? ? ? ? ? ? ? ? | ? ?1 +
> ?drivers/ptp/Kconfig ? ? ? ? ? ? ?| ? 26 ++
> ?drivers/ptp/Makefile ? ? ? ? ? ? | ? ?5 +
> ?drivers/ptp/ptp_clock.c ? ? ? ? ?| ?514 ++++++++++++++++++++++++++++++++++++++
> ?include/linux/Kbuild ? ? ? ? ? ? | ? ?1 +
> ?include/linux/ptp_clock.h ? ? ? ?| ? 79 ++++++
> ?include/linux/ptp_clock_kernel.h | ?137 ++++++++++
> ?11 files changed, 1162 insertions(+), 0 deletions(-)
> ?create mode 100644 Documentation/ptp/ptp.txt
> ?create mode 100644 Documentation/ptp/testptp.c
> ?create mode 100644 Documentation/ptp/testptp.mk
> ?create mode 100644 drivers/ptp/Kconfig
> ?create mode 100644 drivers/ptp/Makefile
> ?create mode 100644 drivers/ptp/ptp_clock.c
> ?create mode 100644 include/linux/ptp_clock.h
> ?create mode 100644 include/linux/ptp_clock_kernel.h
>
> diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
> new file mode 100644
> index 0000000..b86695c
> --- /dev/null
> +++ b/drivers/ptp/Makefile
> @@ -0,0 +1,5 @@
> +#
> +# Makefile for PTP 1588 clock support.
> +#
> +
> +obj-$(CONFIG_PTP_1588_CLOCK) ? ? ? ? ? += ptp_clock.o
> diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c
> new file mode 100644
> index 0000000..4753bf3
> --- /dev/null
> +++ b/drivers/ptp/ptp_clock.c
> @@ -0,0 +1,514 @@
> +/*
> + * PTP 1588 clock support
> + *
> + * Partially adapted from the Linux PPS driver.
> + *
> + * Copyright (C) 2010 OMICRON electronics GmbH
> + *
> + * ?This program is free software; you can redistribute it and/or modify
> + * ?it under the terms of the GNU General Public License as published by
> + * ?the Free Software Foundation; either version 2 of the License, or
> + * ?(at your option) any later version.
> + *
> + * ?This program is distributed in the hope that it will be useful,
> + * ?but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * ?GNU General Public License for more details.
> + *
> + * ?You should have received a copy of the GNU General Public License
> + * ?along with this program; if not, write to the Free Software
> + * ?Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +#include <linux/bitops.h>
> +#include <linux/cdev.h>
> +#include <linux/device.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/list.h>
> +#include <linux/module.h>
> +#include <linux/poll.h>
> +#include <linux/sched.h>
> +#include <linux/slab.h>
> +#include <linux/uaccess.h>
> +
> +#include <linux/ptp_clock_kernel.h>
> +#include <linux/ptp_clock.h>
> +
> +#define PTP_MAX_ALARMS 4
> +#define PTP_MAX_CLOCKS BITS_PER_LONG
> +#define PTP_MAX_TIMESTAMPS 128
> +
> +struct alarm {
> + ? ? ? struct pid *pid;
> + ? ? ? int sig;
> +};
> +
> +struct timestamp_event_queue {
> + ? ? ? struct ptp_extts_event buf[PTP_MAX_TIMESTAMPS];
> + ? ? ? int head;
> + ? ? ? int tail;
> + ? ? ? int overflow;
> +};
> +
> +struct ptp_clock {
> + ? ? ? struct list_head list;
> + ? ? ? struct cdev cdev;
> + ? ? ? struct device *dev;
> + ? ? ? struct ptp_clock_info *info;
> + ? ? ? dev_t devid;
> + ? ? ? int index; /* index into clocks.map, also the minor number */
> +
> + ? ? ? struct alarm alarm[PTP_MAX_ALARMS];
> + ? ? ? struct mutex alarm_mux; /* one process at a time setting an alarm */
> +
> + ? ? ? struct timestamp_event_queue tsevq; /* simple fifo for time stamps */
> + ? ? ? struct mutex tsevq_mux; /* one process at a time reading the fifo */
> + ? ? ? wait_queue_head_t tsev_wq;
> +};
> +
> +/* private globals */
> +
> +static const struct file_operations ptp_fops;
> +static dev_t ptp_devt;
> +static struct class *ptp_class;
> +
> +static struct {
> + ? ? ? struct list_head list;
> + ? ? ? DECLARE_BITMAP(map, PTP_MAX_CLOCKS);
> +} clocks;
> +static DEFINE_SPINLOCK(clocks_lock); /* protects 'clocks' */

Doesn't appear that clocks is manipulated at atomic context.  Mutex instead?

> +
> +/* time stamp event queue operations */
> +
> +static inline int queue_cnt(struct timestamp_event_queue *q)
> +{
> + ? ? ? int cnt = q->tail - q->head;
> + ? ? ? return cnt < 0 ? PTP_MAX_TIMESTAMPS + cnt : cnt;
> +}
> +
> +static inline int queue_free(struct timestamp_event_queue *q)
> +{
> + ? ? ? return PTP_MAX_TIMESTAMPS - queue_cnt(q) - 1;
> +}
> +
> +static void enqueue_external_timestamp(struct timestamp_event_queue *queue,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct ptp_clock_event *src)
> +{
> + ? ? ? struct ptp_extts_event *dst;
> + ? ? ? u32 remainder;
> +
> + ? ? ? dst = &queue->buf[queue->tail];
> +
> + ? ? ? dst->index = src->index;
> + ? ? ? dst->ts.tv_sec = div_u64_rem(src->timestamp, 1000000000, &remainder);
> + ? ? ? dst->ts.tv_nsec = remainder;
> +
> + ? ? ? if (!queue_free(queue))
> + ? ? ? ? ? ? ? queue->overflow++;
> +
> + ? ? ? queue->tail = (queue->tail + 1) % PTP_MAX_TIMESTAMPS;
> +}
> +
> +/* public interface */
> +
> +struct ptp_clock *ptp_clock_register(struct ptp_clock_info *info)
> +{
> + ? ? ? struct ptp_clock *ptp;
> + ? ? ? int err = 0, index, major = MAJOR(ptp_devt);
> + ? ? ? unsigned long flags;
> +
> + ? ? ? if (info->n_alarm > PTP_MAX_ALARMS)
> + ? ? ? ? ? ? ? return ERR_PTR(-EINVAL);

Okay, this is my opinion here, and other maintainers may disagree with
me, but the ERR_PTR() pattern is a horrible idea.  It is non-obvious
when reading code when the pattern is used, and the compiler will not
catch misinterpretation of the return value for you.  Please don't add
new instances of using it.  Just return NULL on error and log it with
printk() or pr_error().  Very seldom do I find the actual error code
to be actually useful anyway.  Generally callers only care about
whether or not the operation succeeded.

> +
> + ? ? ? /* Find a free clock slot and reserve it. */
> + ? ? ? err = -EBUSY;
> + ? ? ? spin_lock_irqsave(&clocks_lock, flags);
> + ? ? ? index = find_first_zero_bit(clocks.map, PTP_MAX_CLOCKS);
> + ? ? ? if (index < PTP_MAX_CLOCKS) {
> + ? ? ? ? ? ? ? set_bit(index, clocks.map);
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> + ? ? ? } else {
> + ? ? ? ? ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> + ? ? ? ? ? ? ? goto no_clock;
> + ? ? ? }

If the spinlock is changed to a mutex that is held for the entire
function call, then the logic here can be simpler.

> +
> + ? ? ? /* Initialize a clock structure. */
> + ? ? ? err = -ENOMEM;
> + ? ? ? ptp = kzalloc(sizeof(struct ptp_clock), GFP_KERNEL);
> + ? ? ? if (ptp == NULL)
> + ? ? ? ? ? ? ? goto no_memory;
> +
> + ? ? ? ptp->info = info;
> + ? ? ? ptp->devid = MKDEV(major, index);
> + ? ? ? ptp->index = index;
> + ? ? ? mutex_init(&ptp->alarm_mux);
> + ? ? ? mutex_init(&ptp->tsevq_mux);
> + ? ? ? init_waitqueue_head(&ptp->tsev_wq);
> +
> + ? ? ? /* Create a new device in our class. */
> + ? ? ? ptp->dev = device_create(ptp_class, NULL, ptp->devid, ptp,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?"ptp_clock_%d", ptp->index);
> + ? ? ? if (IS_ERR(ptp->dev))
> + ? ? ? ? ? ? ? goto no_device;
> +
> + ? ? ? dev_set_drvdata(ptp->dev, ptp);
> +
> + ? ? ? /* Register a character device. */
> + ? ? ? cdev_init(&ptp->cdev, &ptp_fops);
> + ? ? ? ptp->cdev.owner = info->owner;
> + ? ? ? err = cdev_add(&ptp->cdev, ptp->devid, 1);
> + ? ? ? if (err)
> + ? ? ? ? ? ? ? goto no_cdev;
> +
> + ? ? ? /* Clock is ready, add it into the list. */
> + ? ? ? spin_lock_irqsave(&clocks_lock, flags);
> + ? ? ? list_add(&ptp->list, &clocks.list);
> + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> +
> + ? ? ? return ptp;
> +
> +no_cdev:
> + ? ? ? device_destroy(ptp_class, ptp->devid);
> +no_device:
> + ? ? ? mutex_destroy(&ptp->alarm_mux);
> + ? ? ? mutex_destroy(&ptp->tsevq_mux);
> + ? ? ? kfree(ptp);
> +no_memory:
> + ? ? ? spin_lock_irqsave(&clocks_lock, flags);
> + ? ? ? clear_bit(index, clocks.map);
> + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> +no_clock:
> + ? ? ? return ERR_PTR(err);
> +}
> +EXPORT_SYMBOL(ptp_clock_register);
> +
> +int ptp_clock_unregister(struct ptp_clock *ptp)
> +{
> + ? ? ? unsigned long flags;
> +
> + ? ? ? /* Release the clock's resources. */
> + ? ? ? cdev_del(&ptp->cdev);
> + ? ? ? device_destroy(ptp_class, ptp->devid);
> + ? ? ? mutex_destroy(&ptp->alarm_mux);
> + ? ? ? mutex_destroy(&ptp->tsevq_mux);
> +
> + ? ? ? /* Remove the clock from the list. */
> + ? ? ? spin_lock_irqsave(&clocks_lock, flags);
> + ? ? ? list_del(&ptp->list);
> + ? ? ? clear_bit(ptp->index, clocks.map);
> + ? ? ? spin_unlock_irqrestore(&clocks_lock, flags);
> +
> + ? ? ? kfree(ptp);
> +
> + ? ? ? return 0;
> +}
> +EXPORT_SYMBOL(ptp_clock_unregister);
> +
> +void ptp_clock_event(struct ptp_clock *ptp, struct ptp_clock_event *event)
> +{
> + ? ? ? switch (event->type) {
> +
> + ? ? ? case PTP_CLOCK_ALARM:
> + ? ? ? ? ? ? ? kill_pid(ptp->alarm[event->index].pid,
> + ? ? ? ? ? ? ? ? ? ? ? ?ptp->alarm[event->index].sig, 1);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_EXTTS:
> + ? ? ? ? ? ? ? enqueue_external_timestamp(&ptp->tsevq, event);
> + ? ? ? ? ? ? ? wake_up_interruptible(&ptp->tsev_wq);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_PPS:
> + ? ? ? ? ? ? ? break;
> + ? ? ? }
> +}
> +EXPORT_SYMBOL(ptp_clock_event);
> +
> +/* character device operations */
> +
> +static int ptp_ioctl(struct inode *node, struct file *fp,
> + ? ? ? ? ? ? ? ? ? ? unsigned int cmd, unsigned long arg)
> +{
> + ? ? ? struct ptp_clock_caps caps;
> + ? ? ? struct ptp_clock_request req;
> + ? ? ? struct ptp_clock_timer timer;
> + ? ? ? struct ptp_clock *ptp = fp->private_data;
> + ? ? ? struct ptp_clock_info *ops = ptp->info;
> + ? ? ? void *priv = ops->priv;
> + ? ? ? struct timespec ts;
> + ? ? ? int flags, index;
> + ? ? ? int err = 0;
> +
> + ? ? ? switch (cmd) {
> +
> + ? ? ? case PTP_CLOCK_APIVERS:
> + ? ? ? ? ? ? ? err = put_user(PTP_CLOCK_VERSION, (u32 __user *)arg);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_ADJFREQ:
> + ? ? ? ? ? ? ? if (!capable(CAP_SYS_TIME))
> + ? ? ? ? ? ? ? ? ? ? ? return -EPERM;
> + ? ? ? ? ? ? ? err = ops->adjfreq(priv, arg);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_ADJTIME:
> + ? ? ? ? ? ? ? if (!capable(CAP_SYS_TIME))
> + ? ? ? ? ? ? ? ? ? ? ? return -EPERM;
> + ? ? ? ? ? ? ? if (copy_from_user(&ts, (void __user *)arg, sizeof(ts)))
> + ? ? ? ? ? ? ? ? ? ? ? err = -EFAULT;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? err = ops->adjtime(priv, &ts);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_GETTIME:
> + ? ? ? ? ? ? ? err = ops->gettime(priv, &ts);
> + ? ? ? ? ? ? ? if (err)
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? err = copy_to_user((void __user *)arg, &ts, sizeof(ts));
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_SETTIME:
> + ? ? ? ? ? ? ? if (!capable(CAP_SYS_TIME))
> + ? ? ? ? ? ? ? ? ? ? ? return -EPERM;
> + ? ? ? ? ? ? ? if (copy_from_user(&ts, (void __user *)arg, sizeof(ts)))
> + ? ? ? ? ? ? ? ? ? ? ? err = -EFAULT;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? err = ops->settime(priv, &ts);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_GETCAPS:
> + ? ? ? ? ? ? ? memset(&caps, 0, sizeof(caps));
> + ? ? ? ? ? ? ? caps.max_adj = ptp->info->max_adj;
> + ? ? ? ? ? ? ? caps.n_alarm = ptp->info->n_alarm;
> + ? ? ? ? ? ? ? caps.n_ext_ts = ptp->info->n_ext_ts;
> + ? ? ? ? ? ? ? caps.n_per_out = ptp->info->n_per_out;
> + ? ? ? ? ? ? ? caps.pps = ptp->info->pps;
> + ? ? ? ? ? ? ? err = copy_to_user((void __user *)arg, &caps, sizeof(caps));
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_GETTIMER:
> + ? ? ? ? ? ? ? if (copy_from_user(&timer, (void __user *)arg, sizeof(timer))) {
> + ? ? ? ? ? ? ? ? ? ? ? err = -EFAULT;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? index = timer.alarm_index;
> + ? ? ? ? ? ? ? if (index < 0 || index >= ptp->info->n_alarm) {
> + ? ? ? ? ? ? ? ? ? ? ? err = -EINVAL;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? err = ops->gettimer(priv, index, &timer.tsp);
> + ? ? ? ? ? ? ? if (err)
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? err = copy_to_user((void __user *)arg, &timer, sizeof(timer));
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_CLOCK_SETTIMER:
> + ? ? ? ? ? ? ? if (copy_from_user(&timer, (void __user *)arg, sizeof(timer))) {
> + ? ? ? ? ? ? ? ? ? ? ? err = -EFAULT;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? index = timer.alarm_index;
> + ? ? ? ? ? ? ? if (index < 0 || index >= ptp->info->n_alarm) {
> + ? ? ? ? ? ? ? ? ? ? ? err = -EINVAL;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? if (!valid_signal(timer.signum))
> + ? ? ? ? ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? ? ? ? ? flags = timer.flags;
> + ? ? ? ? ? ? ? if (flags & (flags != TIMER_ABSTIME)) {
> + ? ? ? ? ? ? ? ? ? ? ? err = -EINVAL;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? if (mutex_lock_interruptible(&ptp->alarm_mux))
> + ? ? ? ? ? ? ? ? ? ? ? return -ERESTARTSYS;
> +
> + ? ? ? ? ? ? ? if (ptp->alarm[index].pid)
> + ? ? ? ? ? ? ? ? ? ? ? put_pid(ptp->alarm[index].pid);
> +
> + ? ? ? ? ? ? ? ptp->alarm[index].pid = get_pid(task_pid(current));
> + ? ? ? ? ? ? ? ptp->alarm[index].sig = timer.signum;
> + ? ? ? ? ? ? ? err = ops->settimer(priv, index, flags, &timer.tsp);
> +
> + ? ? ? ? ? ? ? mutex_unlock(&ptp->alarm_mux);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case PTP_FEATURE_REQUEST:
> + ? ? ? ? ? ? ? if (copy_from_user(&req, (void __user *)arg, sizeof(req))) {
> + ? ? ? ? ? ? ? ? ? ? ? err = -EFAULT;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? switch (req.type) {
> + ? ? ? ? ? ? ? case PTP_REQUEST_EXTTS:
> + ? ? ? ? ? ? ? case PTP_REQUEST_PEROUT:
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? case PTP_REQUEST_PPS:
> + ? ? ? ? ? ? ? ? ? ? ? if (!capable(CAP_SYS_TIME))
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? return -EPERM;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? default:
> + ? ? ? ? ? ? ? ? ? ? ? err = -EINVAL;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? if (err)
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? err = ops->enable(priv, &req,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? req.flags & PTP_ENABLE_FEATURE ? 1 : 0);
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? default:
> + ? ? ? ? ? ? ? err = -ENOTTY;
> + ? ? ? ? ? ? ? break;
> + ? ? ? }
> + ? ? ? return err;
> +}
> +
> +static int ptp_open(struct inode *inode, struct file *fp)
> +{
> + ? ? ? struct ptp_clock *ptp;
> + ? ? ? ptp = container_of(inode->i_cdev, struct ptp_clock, cdev);
> +
> + ? ? ? fp->private_data = ptp;
> +
> + ? ? ? return 0;
> +}
> +
> +static unsigned int ptp_poll(struct file *fp, poll_table *wait)
> +{
> + ? ? ? struct ptp_clock *ptp = fp->private_data;
> +
> + ? ? ? poll_wait(fp, &ptp->tsev_wq, wait);
> +
> + ? ? ? return queue_cnt(&ptp->tsevq) ? POLLIN : 0;
> +}
> +
> +static ssize_t ptp_read(struct file *fp, char __user *buf,
> + ? ? ? ? ? ? ? ? ? ? ? size_t cnt, loff_t *off)
> +{
> + ? ? ? struct ptp_clock *ptp = fp->private_data;
> + ? ? ? struct timestamp_event_queue *queue = &ptp->tsevq;
> + ? ? ? struct ptp_extts_event *event;
> + ? ? ? size_t qcnt;
> +
> + ? ? ? if (mutex_lock_interruptible(&ptp->tsevq_mux))
> + ? ? ? ? ? ? ? return -ERESTARTSYS;
> +
> + ? ? ? cnt = cnt / sizeof(struct ptp_extts_event);
> +
> + ? ? ? if (wait_event_interruptible(ptp->tsev_wq,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(qcnt = queue_cnt(&ptp->tsevq)))) {
> + ? ? ? ? ? ? ? mutex_unlock(&ptp->tsevq_mux);
> + ? ? ? ? ? ? ? return -ERESTARTSYS;
> + ? ? ? }
> +
> + ? ? ? if (cnt > qcnt)
> + ? ? ? ? ? ? ? cnt = qcnt;
> +
> + ? ? ? event = &queue->buf[queue->head];
> +
> + ? ? ? if (copy_to_user(buf, event, cnt * sizeof(struct ptp_extts_event))) {
> + ? ? ? ? ? ? ? mutex_unlock(&ptp->tsevq_mux);
> + ? ? ? ? ? ? ? return -EFAULT;
> + ? ? ? }
> + ? ? ? queue->head = (queue->head + cnt) % PTP_MAX_TIMESTAMPS;
> +
> + ? ? ? mutex_unlock(&ptp->tsevq_mux);
> +
> + ? ? ? return cnt * sizeof(struct ptp_extts_event);
> +}
> +
> +static int ptp_release(struct inode *inode, struct file *fp)
> +{
> + ? ? ? struct ptp_clock *ptp;
> + ? ? ? struct itimerspec ts = {
> + ? ? ? ? ? ? ? {0, 0}, {0, 0}
> + ? ? ? };
> + ? ? ? int i;
> +
> + ? ? ? ptp = container_of(inode->i_cdev, struct ptp_clock, cdev);
> +
> + ? ? ? for (i = 0; i < ptp->info->n_alarm; i++) {
> + ? ? ? ? ? ? ? if (ptp->alarm[i].pid) {
> + ? ? ? ? ? ? ? ? ? ? ? ptp->info->settimer(ptp->info->priv, i, 0, &ts);
> + ? ? ? ? ? ? ? ? ? ? ? put_pid(ptp->alarm[i].pid);
> + ? ? ? ? ? ? ? ? ? ? ? ptp->alarm[i].pid = NULL;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> + ? ? ? return 0;
> +}
> +
> +static const struct file_operations ptp_fops = {
> + ? ? ? .owner ? ? ? ? ?= THIS_MODULE,
> + ? ? ? .ioctl ? ? ? ? ?= ptp_ioctl,
> + ? ? ? .open ? ? ? ? ? = ptp_open,
> + ? ? ? .poll ? ? ? ? ? = ptp_poll,
> + ? ? ? .read ? ? ? ? ? = ptp_read,
> + ? ? ? .release ? ? ? ?= ptp_release,
> +};
> +
> +/* sysfs */
> +
> +static ssize_t ptp_show_status(struct device *dev,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct device_attribute *attr, char *buf)
> +{
> + ? ? ? struct ptp_clock *ptp = dev_get_drvdata(dev);
> + ? ? ? return sprintf(buf,
> + ? ? ? ? ? ? ? ? ? ? ?"maximum adjustment: ?%d\n"
> + ? ? ? ? ? ? ? ? ? ? ?"programmable alarms: %d\n"
> + ? ? ? ? ? ? ? ? ? ? ?"external timestamps: %d\n"
> + ? ? ? ? ? ? ? ? ? ? ?"periodic outputs: ? ?%d\n"
> + ? ? ? ? ? ? ? ? ? ? ?"has pps: ? ? ? ? ? ? %d\n"
> + ? ? ? ? ? ? ? ? ? ? ?"device index: ? ? ? ?%d\n",
> + ? ? ? ? ? ? ? ? ? ? ?ptp->info->max_adj,
> + ? ? ? ? ? ? ? ? ? ? ?ptp->info->n_alarm,
> + ? ? ? ? ? ? ? ? ? ? ?ptp->info->n_ext_ts,
> + ? ? ? ? ? ? ? ? ? ? ?ptp->info->n_per_out,
> + ? ? ? ? ? ? ? ? ? ? ?ptp->info->pps,
> + ? ? ? ? ? ? ? ? ? ? ?ptp->index);
> +}

Don't do this in a sysfs file.  Use a debugfs file if you want to
export freeform data like this.  sysfs files should contain either
only one value, or a simple list-of-same-type values.  Formatted data
is completely out.

> +
> +struct device_attribute ptp_attrs[] = {
> + ? ? ? __ATTR(capabilities, S_IRUGO, ptp_show_status, NULL),
> + ? ? ? __ATTR_NULL,
> +};
> +
> +/* module operations */
> +
> +static void __exit ptp_exit(void)
> +{
> + ? ? ? class_destroy(ptp_class);
> + ? ? ? unregister_chrdev_region(ptp_devt, PTP_MAX_CLOCKS);
> +}
> +
> +static int __init ptp_init(void)
> +{
> + ? ? ? int err;
> +
> + ? ? ? INIT_LIST_HEAD(&clocks.list);
> +
> + ? ? ? ptp_class = class_create(THIS_MODULE, "ptp");
> + ? ? ? if (!ptp_class) {
> + ? ? ? ? ? ? ? printk(KERN_ERR "ptp: failed to allocate class\n");
> + ? ? ? ? ? ? ? return -ENOMEM;
> + ? ? ? }
> + ? ? ? ptp_class->dev_attrs = ptp_attrs;
> +
> + ? ? ? err = alloc_chrdev_region(&ptp_devt, 0, PTP_MAX_CLOCKS, "ptp");
> + ? ? ? if (err < 0) {
> + ? ? ? ? ? ? ? printk(KERN_ERR "ptp: failed to allocate char device region\n");
> + ? ? ? ? ? ? ? goto no_region;
> + ? ? ? }
> +
> + ? ? ? pr_info("PTP clock support registered\n");
> + ? ? ? return 0;
> +
> +no_region:
> + ? ? ? class_destroy(ptp_class);
> + ? ? ? return err;
> +}
> +
> +subsys_initcall(ptp_init);
> +module_exit(ptp_exit);
> +
> +MODULE_AUTHOR("Richard Cochran <richard.cochran at omicron.at>");
> +MODULE_DESCRIPTION("PTP clocks support");
> +MODULE_LICENSE("GPL");
> diff --git a/include/linux/Kbuild b/include/linux/Kbuild
> index 2fc8e14..9959fe4 100644
> --- a/include/linux/Kbuild
> +++ b/include/linux/Kbuild
> @@ -140,6 +140,7 @@ header-y += pkt_sched.h
> ?header-y += posix_types.h
> ?header-y += ppdev.h
> ?header-y += prctl.h
> +header-y += ptp_clock.h
> ?header-y += qnxtypes.h
> ?header-y += qnx4_fs.h
> ?header-y += radeonfb.h
> diff --git a/include/linux/ptp_clock.h b/include/linux/ptp_clock.h
> new file mode 100644
> index 0000000..5a509c5
> --- /dev/null
> +++ b/include/linux/ptp_clock.h
> @@ -0,0 +1,79 @@
> +/*
> + * PTP 1588 clock support - user space interface
> + *
> + * Copyright (C) 2010 OMICRON electronics GmbH
> + *
> + * ?This program is free software; you can redistribute it and/or modify
> + * ?it under the terms of the GNU General Public License as published by
> + * ?the Free Software Foundation; either version 2 of the License, or
> + * ?(at your option) any later version.
> + *
> + * ?This program is distributed in the hope that it will be useful,
> + * ?but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * ?GNU General Public License for more details.
> + *
> + * ?You should have received a copy of the GNU General Public License
> + * ?along with this program; if not, write to the Free Software
> + * ?Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#ifndef _PTP_CLOCK_H_
> +#define _PTP_CLOCK_H_
> +
> +#include <linux/ioctl.h>
> +#include <linux/types.h>
> +
> +#define PTP_ENABLE_FEATURE (1<<0)
> +#define PTP_RISING_EDGE ? ?(1<<1)
> +#define PTP_FALLING_EDGE ? (1<<2)
> +
> +enum ptp_request_types {
> + ? ? ? PTP_REQUEST_EXTTS,
> + ? ? ? PTP_REQUEST_PEROUT,
> + ? ? ? PTP_REQUEST_PPS,
> +};
> +
> +struct ptp_clock_caps {
> + ? ? ? __s32 max_adj; /* Maximum frequency adjustment, parts per billon. */
> + ? ? ? int n_alarm; ? /* Number of programmable alarms. */
> + ? ? ? int n_ext_ts; ?/* Number of external time stamp channels. */
> + ? ? ? int n_per_out; /* Number of programmable periodic signals. */
> + ? ? ? int pps; ? ? ? /* Whether the clock supports a PPS callback. */
> +};
> +
> +struct ptp_clock_timer {
> + ? ? ? int alarm_index; ? ? ? /* Which alarm to query or configure. */
> + ? ? ? int signum; ? ? ? ? ? ?/* Requested signal. */
> + ? ? ? int flags; ? ? ? ? ? ? /* Zero or TIMER_ABSTIME, see TIMER_SETTIME(2) */
> + ? ? ? struct itimerspec tsp; /* See TIMER_SETTIME(2) */
> +};
> +
> +struct ptp_clock_request {
> + ? ? ? int type; ?/* One of the ptp_request_types enumeration values. */
> + ? ? ? int index; /* Which channel to configure. */
> + ? ? ? struct timespec ts; /* For period signals, the desired period. */
> + ? ? ? int flags; /* Bit field for PTP_ENABLE_FEATURE or other flags. */
> +};
> +
> +struct ptp_extts_event {
> + ? ? ? int index;
> + ? ? ? struct timespec ts;
> +};
> +
> +#define PTP_CLOCK_VERSION 0x00000001
> +
> +#define PTP_CLK_MAGIC '='
> +
> +#define PTP_CLOCK_APIVERS _IOR (PTP_CLK_MAGIC, 1, __u32)
> +#define PTP_CLOCK_ADJFREQ _IO ?(PTP_CLK_MAGIC, 2)
> +#define PTP_CLOCK_ADJTIME _IOW (PTP_CLK_MAGIC, 3, struct timespec)
> +#define PTP_CLOCK_GETTIME _IOR (PTP_CLK_MAGIC, 4, struct timespec)
> +#define PTP_CLOCK_SETTIME _IOW (PTP_CLK_MAGIC, 5, struct timespec)
> +
> +#define PTP_CLOCK_GETCAPS ? _IOR ?(PTP_CLK_MAGIC, 6, struct ptp_clock_caps)
> +#define PTP_CLOCK_GETTIMER ?_IOWR (PTP_CLK_MAGIC, 7, struct ptp_clock_timer)
> +#define PTP_CLOCK_SETTIMER ?_IOW ?(PTP_CLK_MAGIC, 8, struct ptp_clock_timer)
> +#define PTP_FEATURE_REQUEST _IOW ?(PTP_CLK_MAGIC, 9, struct ptp_clock_request)
> +
> +#endif
> diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h
> new file mode 100644
> index 0000000..d6cc158
> --- /dev/null
> +++ b/include/linux/ptp_clock_kernel.h
> @@ -0,0 +1,137 @@
> +/*
> + * PTP 1588 clock support
> + *
> + * Copyright (C) 2010 OMICRON electronics GmbH
> + *
> + * ?This program is free software; you can redistribute it and/or modify
> + * ?it under the terms of the GNU General Public License as published by
> + * ?the Free Software Foundation; either version 2 of the License, or
> + * ?(at your option) any later version.
> + *
> + * ?This program is distributed in the hope that it will be useful,
> + * ?but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * ?MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
> + * ?GNU General Public License for more details.
> + *
> + * ?You should have received a copy of the GNU General Public License
> + * ?along with this program; if not, write to the Free Software
> + * ?Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
> + */
> +
> +#ifndef _PTP_CLOCK_KERNEL_H_
> +#define _PTP_CLOCK_KERNEL_H_
> +
> +#include <linux/ptp_clock.h>
> +
> +/**
> + * struct ptp_clock_info - decribes a PTP hardware clock
> + *
> + * @owner: ? ? The clock driver should set to THIS_MODULE.
> + * @name: ? ? ?A short name to identify the clock.
> + * @max_adj: ? The maximum possible frequency adjustment, in parts per billon.
> + * @n_alarm: ? The number of programmable alarms.
> + * @n_ext_ts: ?The number of external time stamp channels.
> + * @n_per_out: The number of programmable periodic signals.
> + * @pps: ? ? ? Indicates whether the clock supports a PPS callback.
> + * @priv: ? ? ?Passed to the clock operations, for the driver's private use.
> + *
> + * clock operations
> + *
> + * @adjfreq: ?Adjusts the frequency of the hardware clock.
> + * ? ? ? ? ? ?parameter delta: Desired period change in parts per billion.
> + *
> + * @adjtime: ?Shifts the time of the hardware clock.
> + * ? ? ? ? ? ?parameter ts: Desired change in seconds and nanoseconds.
> + *
> + * @gettime: ?Reads the current time from the hardware clock.
> + * ? ? ? ? ? ?parameter ts: Holds the result.
> + *
> + * @settime: ?Set the current time on the hardware clock.
> + * ? ? ? ? ? ?parameter ts: Time value to set.
> + *
> + * @gettimer: Reads the time remaining from the given timer.
> + * ? ? ? ? ? ?parameter index: Which alarm to query.
> + * ? ? ? ? ? ?parameter ts: Holds the result.
> + *
> + * @settimer: Arms the given timer for periodic or one shot operation.
> + * ? ? ? ? ? ?parameter index: Which alarm to set.
> + * ? ? ? ? ? ?parameter abs: TIMER_ABSTIME, or zero for relative timer.
> + * ? ? ? ? ? ?parameter ts: Alarm time and period to set.
> + *
> + * @enable: ? Request driver to enable or disable an ancillary feature.
> + * ? ? ? ? ? ?parameter request: Desired resource to enable or disable.
> + * ? ? ? ? ? ?parameter on: Caller passes one to enable or zero to disable.
> + *
> + * The callbacks must all return zero on success, non-zero otherwise.
> + */
> +
> +struct ptp_clock_info {
> + ? ? ? struct module *owner;
> + ? ? ? char name[16];
> + ? ? ? s32 max_adj;
> + ? ? ? int n_alarm;
> + ? ? ? int n_ext_ts;
> + ? ? ? int n_per_out;
> + ? ? ? int pps;
> + ? ? ? void *priv;
> + ? ? ? int (*adjfreq)(void *priv, s32 delta);
> + ? ? ? int (*adjtime)(void *priv, struct timespec *ts);
> + ? ? ? int (*gettime)(void *priv, struct timespec *ts);
> + ? ? ? int (*settime)(void *priv, struct timespec *ts);
> + ? ? ? int (*gettimer)(void *priv, int index, struct itimerspec *ts);
> + ? ? ? int (*settimer)(void *priv, int index, int abs, struct itimerspec *ts);
> + ? ? ? int (*enable)(void *priv, struct ptp_clock_request *request, int on);
> +};
> +
> +struct ptp_clock;
> +
> +/**
> + * ptp_clock_register() - register a PTP hardware clock driver
> + *
> + * @info: ?Structure describing the new clock.
> + */
> +
> +extern struct ptp_clock *ptp_clock_register(struct ptp_clock_info *info);
> +
> +/**
> + * ptp_clock_unregister() - unregister a PTP hardware clock driver
> + *
> + * @ptp: ?The clock to remove from service.
> + */
> +
> +extern int ptp_clock_unregister(struct ptp_clock *ptp);
> +
> +
> +enum ptp_clock_events {
> + ? ? ? PTP_CLOCK_ALARM,
> + ? ? ? PTP_CLOCK_EXTTS,
> + ? ? ? PTP_CLOCK_PPS,
> +};
> +
> +/**
> + * struct ptp_clock_event - decribes a PTP hardware clock event
> + *
> + * @type: ?One of the ptp_clock_events enumeration values.
> + * @index: Identifies the source of the event.
> + * @timestamp: When the event occured.
> + */
> +
> +struct ptp_clock_event {
> + ? ? ? int type;
> + ? ? ? int index;
> + ? ? ? u64 timestamp;
> +};
> +
> +/**
> + * ptp_clock_event() - notify the PTP layer about an event
> + *
> + * This function should only be called from interrupt context.
> + *
> + * @ptp: ? ?The clock obtained from ptp_clock_register().
> + * @event: ?Message structure describing the event.
> + */
> +
> +extern void ptp_clock_event(struct ptp_clock *ptp,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? struct ptp_clock_event *event);
> +
> +#endif
> --
> 1.6.3.3
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From linus.walleij at stericsson.com  Tue Jun 15 16:14:59 2010
From: linus.walleij at stericsson.com (Linus WALLEIJ)
Date: Tue, 15 Jun 2010 22:14:59 +0200
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 PrimeCells
In-Reply-To: <4C170EE2.4010706@st.com>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>
	<4C15C60E.6080404@st.com>
	<AANLkTim9n-p-Pw6FWvzQMBiAuB3h9ILq1Ya6XWk_0l-c@mail.gmail.com>
	<4C170EE2.4010706@st.com>
Message-ID: <CEE6BB42CAD6E947908279175AF8470A025E5AE1ED@EXDCVYMBSTM006.EQ1STM.local>

[Viresh]

> On 6/14/2010 7:09 PM, Linus Walleij wrote:
> > Hi Viresh, thanks a lot for reviewing this and I'd be *very* happy if
> > you could give it a spin on
> > the SPEAr as well!
> 
> I would be happy too linus, will do it in few weeks, right now we are
> running short of time.

Yeah I know that feeling ... anyway I will probably publish a few
more rounds of this before then.

> > In this case we multiplex the memcpy and slave transfers on the few
> > physical channels we have, but I haven't finally decided how to
> handle this:
> > perhaps we should always set on physical channel aside for memcpy
> > so this won't ever fail, and then this special memcpy device entry
> will help.
> >
> > Ideas? Use cases?
> 
> Hmmm. I am not sure, but i think we can't hard code a channel for some
> device.
> All channels should be available with both capabilities. If still there
> are
> some conditions (that you might know), where we need to hard code
> channels
> for devices, then this should come from plat data in some way.

Currently I don't hardcode anything, the physical channels
(on the PL081 only two!) will be multiplexed on a first-come
First-served basis. This is a bit problematic since if I start
a DMAengine memcpy test there is a real battle about the channels...
The memcpy test assumes it will always get a channel, see.

I could queue the transfers waiting for a physical channel to
become available but perhaps that's not so good either.

> I have few more doubts that i wanted to ask. Are following supported in
> your
> driver, we need them in SPEAr:
>  - Configure burst size of source or destination.

The PrimeCell extension supports this, do you need that in things
that are not PrimeCells? In that case we need to make them generic.

>  - Configure DMA Master for src or dest.

Right now I have an algorithm that will (on the PL080, the PL081
has only one master) try to select AHB1 for the memory and AHB2
for the device by checking if one address is fixed. If both or
none addresses are fixed it will simply select AHB1 for source
and AHB2 for destination.

Please elaborate on what algorithm you need for this!

>  - Transfer from Peripheral to Peripheral.

Not supported by DMAengine, but would be easy enough to add.

>  - Configure Width of src or dest peripheral.

Part of PrimeCell DMA API.

>  - Configure Flow controller of transfer.

Currently only done dynamically with DMA as the master for
Mem2mem, mem2per and per2mem. Mastering from the peripherals
is not supported. Do you have advanced features like that?

Anyway it can be passed in from platform data easily.

>  - Some callback for fixing Request line multiplexing just before
> 	initiating transfer.

This is part of this driver. RealView & versatile have exactly
this problem too.

>  - Multiple sg elements in slave_sg transfer. I think it is not
> supported.

No, but can be fixed quite easily.

>  - Control for autoincrement of addresses, both in case of memory and
> 	peripherals.

Right now the engine autoincrements the memory pointers if memory
is source/destination and both on mem2mem.

If you actually have peripherals that need increasing pointers it can
Probably be added.

Yours,
Linus Walleij


From jdzheng at broadcom.com  Tue Jun 15 16:42:26 2010
From: jdzheng at broadcom.com (JD (Jiandong) Zheng)
Date: Tue, 15 Jun 2010 13:42:26 -0700
Subject: [PATCH] MAINTAINERS: Change BCMRING maintainer
Message-ID: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E3F7@SJEXCHCCR02.corp.ad.broadcom.com>

Hello,

I am Jiandong Zheng working on BCMRING in Broadcom Canada Ltd. I am replacing Leo Chen (leochen at broadcom.com) as " ARM/BCMRING ARM ARCHITECTURE" and "ARM/BCMRING MTD NAND DRIVER" maintainer.

Here is the patch to MAINTAINERS file in linux 2.6.34 about this change.

Signed-off-by: Jiandong Zheng <jdzheng at broadcom.com>

diff -urN linux-2.6.34/MAINTAINERS.orig linux-2.6.34/MAINTAINERS
--- linux-2.6.34/MAINTAINERS.orig	2010-06-15 11:59:53.202128994 -0700
+++ linux-2.6.34/MAINTAINERS	2010-06-15 12:01:59.862277620 -0700
@@ -570,14 +570,14 @@
 S:	Maintained
 
 ARM/BCMRING ARM ARCHITECTURE
-M:	Leo Chen <leochen at broadcom.com>
+M:	Jiandong Zheng <jdzheng at broadcom.com>
 M:	Scott Branden <sbranden at broadcom.com>
 L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 S:	Maintained
 F:	arch/arm/mach-bcmring
 
 ARM/BCMRING MTD NAND DRIVER
-M:	Leo Chen <leochen at broadcom.com>
+M:	Jiandong Zheng <jdzheng at broadcom.com>
 M:	Scott Branden <sbranden at broadcom.com>
 L:	linux-mtd at lists.infradead.org
 S:	Maintained


Thanks,

Jiandong Zheng
Senior Staff Software Engineer
Broadcom Canada Ltd.



From linus.walleij at stericsson.com  Tue Jun 15 16:55:07 2010
From: linus.walleij at stericsson.com (Linus WALLEIJ)
Date: Tue, 15 Jun 2010 22:55:07 +0200
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 PrimeCells
In-Reply-To: <AANLkTil7gb7SjrYPrHPfSomwxLlHpowXOZd_Qr125jvr@mail.gmail.com>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>
	<002001cb0c75$0a54fd00$1efef700$%kim@samsung.com>
	<AANLkTil7gb7SjrYPrHPfSomwxLlHpowXOZd_Qr125jvr@mail.gmail.com>
Message-ID: <CEE6BB42CAD6E947908279175AF8470A025E5AE204@EXDCVYMBSTM006.EQ1STM.local>

[Jassi]
> [Kukjin]
> >> It has been converted to use the header from the Samsung PL080
> >> derivate instead of its own defintions, and can potentially support
> >> several controllers in the same system.
> > Looks good, but please give me some time to test on the
> board(SMDK6410).
> > If any problem, let you know. Of course no problem, will ack.
> Samsung doesn't use the DMA API, so this driver is unlikely to work.

Yeah that was never the intention, the Samsung derivate has one extra
Register and other funny stuff.

I was more hoping on breaking out a subset in the same elegant way
with a generic part and a separate DMAengine as was done with the
PL330... But I need to get it fully working first.

Atleast I used the same include file.

But I have functional UART DMA on the RealView PB11MPCore now!

Yours,
Linus Walleij

From kgene.kim at samsung.com  Tue Jun 15 19:42:24 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 16 Jun 2010 08:42:24 +0900
Subject: [PATCH] ARM: s5pv210_defconfig: Update for removing s5pc110_defconfig
Message-ID: <1276645344-16623-1-git-send-email-kgene.kim@samsung.com>

Now that S5PC110 machines and S5PV210 machines can be built into
one kernel, update mach-s5pv210/Kconfig and s5pv210_defconfig.

Tested on SMDKC110(S5PC110) and SMDKV210(S5PV210).
Note that GONI machine ID is not included in the kernel.

Created and tested against linux-2.6.35-rc3.

Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/configs/s5pc110_defconfig |  924 ------------------------------------
 arch/arm/configs/s5pv210_defconfig |   30 +-
 arch/arm/mach-s5pv210/Kconfig      |   28 +-
 3 files changed, 39 insertions(+), 943 deletions(-)
 delete mode 100644 arch/arm/configs/s5pc110_defconfig

diff --git a/arch/arm/configs/s5pc110_defconfig b/arch/arm/configs/s5pc110_defconfig
deleted file mode 100644
index c4de360..0000000
--- a/arch/arm/configs/s5pc110_defconfig
+++ /dev/null
@@ -1,924 +0,0 @@
-#
-# Automatically generated make config: don't edit
-# Linux kernel version: 2.6.34
-# Wed May 26 19:04:37 2010
-#
-CONFIG_ARM=y
-CONFIG_SYS_SUPPORTS_APM_EMULATION=y
-CONFIG_GENERIC_GPIO=y
-CONFIG_GENERIC_TIME=y
-CONFIG_ARCH_USES_GETTIMEOFFSET=y
-CONFIG_HAVE_PROC_CPU=y
-CONFIG_NO_IOPORT=y
-CONFIG_GENERIC_HARDIRQS=y
-CONFIG_STACKTRACE_SUPPORT=y
-CONFIG_HAVE_LATENCYTOP_SUPPORT=y
-CONFIG_LOCKDEP_SUPPORT=y
-CONFIG_TRACE_IRQFLAGS_SUPPORT=y
-CONFIG_HARDIRQS_SW_RESEND=y
-CONFIG_GENERIC_IRQ_PROBE=y
-CONFIG_RWSEM_GENERIC_SPINLOCK=y
-CONFIG_GENERIC_HWEIGHT=y
-CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_NEED_DMA_MAP_STATE=y
-CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
-CONFIG_ARM_L1_CACHE_SHIFT_6=y
-CONFIG_VECTORS_BASE=0xffff0000
-CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
-CONFIG_CONSTRUCTORS=y
-
-#
-# General setup
-#
-CONFIG_EXPERIMENTAL=y
-CONFIG_BROKEN_ON_SMP=y
-CONFIG_LOCK_KERNEL=y
-CONFIG_INIT_ENV_ARG_LIMIT=32
-CONFIG_LOCALVERSION=""
-CONFIG_LOCALVERSION_AUTO=y
-CONFIG_HAVE_KERNEL_GZIP=y
-CONFIG_HAVE_KERNEL_LZMA=y
-CONFIG_HAVE_KERNEL_LZO=y
-CONFIG_KERNEL_GZIP=y
-# CONFIG_KERNEL_BZIP2 is not set
-# CONFIG_KERNEL_LZMA is not set
-# CONFIG_KERNEL_LZO is not set
-CONFIG_SWAP=y
-# CONFIG_SYSVIPC is not set
-# CONFIG_BSD_PROCESS_ACCT is not set
-
-#
-# RCU Subsystem
-#
-CONFIG_TREE_RCU=y
-# CONFIG_TREE_PREEMPT_RCU is not set
-# CONFIG_TINY_RCU is not set
-# CONFIG_RCU_TRACE is not set
-CONFIG_RCU_FANOUT=32
-# CONFIG_RCU_FANOUT_EXACT is not set
-# CONFIG_TREE_RCU_TRACE is not set
-# CONFIG_IKCONFIG is not set
-CONFIG_LOG_BUF_SHIFT=17
-# CONFIG_CGROUPS is not set
-CONFIG_SYSFS_DEPRECATED=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-# CONFIG_RELAY is not set
-CONFIG_NAMESPACES=y
-# CONFIG_UTS_NS is not set
-# CONFIG_USER_NS is not set
-# CONFIG_PID_NS is not set
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE=""
-CONFIG_RD_GZIP=y
-CONFIG_RD_BZIP2=y
-CONFIG_RD_LZMA=y
-CONFIG_RD_LZO=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_SYSCTL=y
-CONFIG_ANON_INODES=y
-# CONFIG_EMBEDDED is not set
-CONFIG_UID16=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS=y
-CONFIG_KALLSYMS_ALL=y
-# CONFIG_KALLSYMS_EXTRA_PASS is not set
-CONFIG_HOTPLUG=y
-CONFIG_PRINTK=y
-CONFIG_BUG=y
-CONFIG_ELF_CORE=y
-CONFIG_BASE_FULL=y
-CONFIG_FUTEX=y
-CONFIG_EPOLL=y
-CONFIG_SIGNALFD=y
-CONFIG_TIMERFD=y
-CONFIG_EVENTFD=y
-CONFIG_SHMEM=y
-CONFIG_AIO=y
-CONFIG_HAVE_PERF_EVENTS=y
-CONFIG_PERF_USE_VMALLOC=y
-
-#
-# Kernel Performance Events And Counters
-#
-# CONFIG_PERF_EVENTS is not set
-# CONFIG_PERF_COUNTERS is not set
-CONFIG_VM_EVENT_COUNTERS=y
-CONFIG_SLUB_DEBUG=y
-CONFIG_COMPAT_BRK=y
-# CONFIG_SLAB is not set
-CONFIG_SLUB=y
-# CONFIG_SLOB is not set
-# CONFIG_PROFILING is not set
-CONFIG_HAVE_OPROFILE=y
-# CONFIG_KPROBES is not set
-CONFIG_HAVE_KPROBES=y
-CONFIG_HAVE_KRETPROBES=y
-CONFIG_HAVE_CLK=y
-
-#
-# GCOV-based kernel profiling
-#
-# CONFIG_SLOW_WORK is not set
-CONFIG_HAVE_GENERIC_DMA_COHERENT=y
-CONFIG_SLABINFO=y
-CONFIG_RT_MUTEXES=y
-CONFIG_BASE_SMALL=0
-CONFIG_MODULES=y
-# CONFIG_MODULE_FORCE_LOAD is not set
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_MODULE_FORCE_UNLOAD is not set
-# CONFIG_MODVERSIONS is not set
-# CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_BLOCK=y
-CONFIG_LBDAF=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_BLK_DEV_INTEGRITY is not set
-
-#
-# IO Schedulers
-#
-CONFIG_IOSCHED_NOOP=y
-CONFIG_IOSCHED_DEADLINE=y
-CONFIG_IOSCHED_CFQ=y
-# CONFIG_DEFAULT_DEADLINE is not set
-CONFIG_DEFAULT_CFQ=y
-# CONFIG_DEFAULT_NOOP is not set
-CONFIG_DEFAULT_IOSCHED="cfq"
-# CONFIG_INLINE_SPIN_TRYLOCK is not set
-# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK is not set
-# CONFIG_INLINE_SPIN_LOCK_BH is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_SPIN_UNLOCK is not set
-# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
-# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
-# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_READ_TRYLOCK is not set
-# CONFIG_INLINE_READ_LOCK is not set
-# CONFIG_INLINE_READ_LOCK_BH is not set
-# CONFIG_INLINE_READ_LOCK_IRQ is not set
-# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_READ_UNLOCK is not set
-# CONFIG_INLINE_READ_UNLOCK_BH is not set
-# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
-# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
-# CONFIG_INLINE_WRITE_TRYLOCK is not set
-# CONFIG_INLINE_WRITE_LOCK is not set
-# CONFIG_INLINE_WRITE_LOCK_BH is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
-# CONFIG_INLINE_WRITE_UNLOCK is not set
-# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
-# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
-# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
-# CONFIG_MUTEX_SPIN_ON_OWNER is not set
-# CONFIG_FREEZER is not set
-
-#
-# System Type
-#
-CONFIG_MMU=y
-# CONFIG_ARCH_AAEC2000 is not set
-# CONFIG_ARCH_INTEGRATOR is not set
-# CONFIG_ARCH_REALVIEW is not set
-# CONFIG_ARCH_VERSATILE is not set
-# CONFIG_ARCH_VEXPRESS is not set
-# CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_BCMRING is not set
-# CONFIG_ARCH_CLPS711X is not set
-# CONFIG_ARCH_CNS3XXX is not set
-# CONFIG_ARCH_GEMINI is not set
-# CONFIG_ARCH_EBSA110 is not set
-# CONFIG_ARCH_EP93XX is not set
-# CONFIG_ARCH_FOOTBRIDGE is not set
-# CONFIG_ARCH_MXC is not set
-# CONFIG_ARCH_STMP3XXX is not set
-# CONFIG_ARCH_NETX is not set
-# CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IOP13XX is not set
-# CONFIG_ARCH_IOP32X is not set
-# CONFIG_ARCH_IOP33X is not set
-# CONFIG_ARCH_IXP23XX is not set
-# CONFIG_ARCH_IXP2000 is not set
-# CONFIG_ARCH_IXP4XX is not set
-# CONFIG_ARCH_L7200 is not set
-# CONFIG_ARCH_DOVE is not set
-# CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_LOKI is not set
-# CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_ORION5X is not set
-# CONFIG_ARCH_MMP is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
-# CONFIG_ARCH_W90X900 is not set
-# CONFIG_ARCH_NUC93X is not set
-# CONFIG_ARCH_PNX4008 is not set
-# CONFIG_ARCH_PXA is not set
-# CONFIG_ARCH_MSM is not set
-# CONFIG_ARCH_SHMOBILE is not set
-# CONFIG_ARCH_RPC is not set
-# CONFIG_ARCH_SA1100 is not set
-# CONFIG_ARCH_S3C2410 is not set
-# CONFIG_ARCH_S3C64XX is not set
-# CONFIG_ARCH_S5P6440 is not set
-# CONFIG_ARCH_S5P6442 is not set
-# CONFIG_ARCH_S5PC100 is not set
-CONFIG_ARCH_S5PV210=y
-# CONFIG_ARCH_SHARK is not set
-# CONFIG_ARCH_LH7A40X is not set
-# CONFIG_ARCH_U300 is not set
-# CONFIG_ARCH_U8500 is not set
-# CONFIG_ARCH_NOMADIK is not set
-# CONFIG_ARCH_DAVINCI is not set
-# CONFIG_ARCH_OMAP is not set
-# CONFIG_PLAT_SPEAR is not set
-CONFIG_PLAT_SAMSUNG=y
-
-#
-# Boot options
-#
-# CONFIG_S3C_BOOT_ERROR_RESET is not set
-CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
-CONFIG_S3C_LOWLEVEL_UART_PORT=1
-CONFIG_SAMSUNG_CLKSRC=y
-CONFIG_SAMSUNG_IRQ_VIC_TIMER=y
-CONFIG_SAMSUNG_IRQ_UART=y
-CONFIG_SAMSUNG_GPIOLIB_4BIT=y
-CONFIG_S3C_GPIO_CFG_S3C24XX=y
-CONFIG_S3C_GPIO_CFG_S3C64XX=y
-CONFIG_S3C_GPIO_PULL_UPDOWN=y
-CONFIG_S5P_GPIO_DRVSTR=y
-CONFIG_SAMSUNG_GPIO_EXTRA=0
-CONFIG_S3C_GPIO_SPACE=0
-CONFIG_S3C_GPIO_TRACK=y
-# CONFIG_S3C_ADC is not set
-CONFIG_S3C_DEV_WDT=y
-CONFIG_S3C_PL330_DMA=y
-
-#
-# Power management
-#
-CONFIG_PLAT_S5P=y
-CONFIG_S5P_EXT_INT=y
-CONFIG_CPU_S5PV210=y
-# CONFIG_MACH_AQUILA is not set
-# CONFIG_MACH_GONI is not set
-# CONFIG_MACH_SMDKV210 is not set
-CONFIG_MACH_SMDKC110=y
-
-#
-# Processor Type
-#
-CONFIG_CPU_32v6K=y
-CONFIG_CPU_V7=y
-CONFIG_CPU_32v7=y
-CONFIG_CPU_ABRT_EV7=y
-CONFIG_CPU_PABRT_V7=y
-CONFIG_CPU_CACHE_V7=y
-CONFIG_CPU_CACHE_VIPT=y
-CONFIG_CPU_COPY_V6=y
-CONFIG_CPU_TLB_V7=y
-CONFIG_CPU_HAS_ASID=y
-CONFIG_CPU_CP15=y
-CONFIG_CPU_CP15_MMU=y
-
-#
-# Processor Features
-#
-CONFIG_ARM_THUMB=y
-# CONFIG_ARM_THUMBEE is not set
-# CONFIG_CPU_ICACHE_DISABLE is not set
-# CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_CPU_BPREDICT_DISABLE is not set
-CONFIG_HAS_TLS_REG=y
-CONFIG_ARM_L1_CACHE_SHIFT=6
-CONFIG_ARM_DMA_MEM_BUFFERABLE=y
-CONFIG_CPU_HAS_PMU=y
-# CONFIG_ARM_ERRATA_430973 is not set
-# CONFIG_ARM_ERRATA_458693 is not set
-# CONFIG_ARM_ERRATA_460075 is not set
-CONFIG_ARM_VIC=y
-CONFIG_ARM_VIC_NR=2
-CONFIG_PL330=y
-
-#
-# Bus support
-#
-# CONFIG_PCI_SYSCALL is not set
-# CONFIG_ARCH_SUPPORTS_MSI is not set
-# CONFIG_PCCARD is not set
-
-#
-# Kernel Features
-#
-# CONFIG_VMSPLIT_3G is not set
-CONFIG_VMSPLIT_2G=y
-# CONFIG_VMSPLIT_1G is not set
-CONFIG_PAGE_OFFSET=0x80000000
-# CONFIG_PREEMPT_NONE is not set
-# CONFIG_PREEMPT_VOLUNTARY is not set
-CONFIG_PREEMPT=y
-CONFIG_HZ=200
-# CONFIG_THUMB2_KERNEL is not set
-CONFIG_AEABI=y
-CONFIG_OABI_COMPAT=y
-CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
-# CONFIG_HIGHMEM is not set
-CONFIG_SELECT_MEMORY_MODEL=y
-# CONFIG_FLATMEM_MANUAL is not set
-# CONFIG_DISCONTIGMEM_MANUAL is not set
-CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_SPARSEMEM=y
-CONFIG_HAVE_MEMORY_PRESENT=y
-CONFIG_SPARSEMEM_EXTREME=y
-CONFIG_SPLIT_PTLOCK_CPUS=999999
-# CONFIG_PHYS_ADDR_T_64BIT is not set
-CONFIG_ZONE_DMA_FLAG=0
-CONFIG_VIRT_TO_BUS=y
-# CONFIG_KSM is not set
-CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
-CONFIG_ALIGNMENT_TRAP=y
-# CONFIG_UACCESS_WITH_MEMCPY is not set
-
-#
-# Boot options
-#
-CONFIG_ZBOOT_ROM_TEXT=0
-CONFIG_ZBOOT_ROM_BSS=0
-CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
-# CONFIG_CMDLINE_FORCE is not set
-# CONFIG_XIP_KERNEL is not set
-# CONFIG_KEXEC is not set
-
-#
-# CPU Power Management
-#
-# CONFIG_CPU_IDLE is not set
-
-#
-# Floating point emulation
-#
-
-#
-# At least one emulation must be selected
-#
-# CONFIG_FPE_NWFPE is not set
-# CONFIG_FPE_FASTFPE is not set
-CONFIG_VFP=y
-CONFIG_VFPv3=y
-CONFIG_NEON=y
-
-#
-# Userspace binary formats
-#
-CONFIG_BINFMT_ELF=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_HAVE_AOUT=y
-# CONFIG_BINFMT_AOUT is not set
-# CONFIG_BINFMT_MISC is not set
-
-#
-# Power management options
-#
-# CONFIG_PM is not set
-CONFIG_ARCH_SUSPEND_POSSIBLE=y
-# CONFIG_NET is not set
-
-#
-# Device Drivers
-#
-
-#
-# Generic Driver Options
-#
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_DEVTMPFS is not set
-CONFIG_STANDALONE=y
-CONFIG_PREVENT_FIRMWARE_BUILD=y
-CONFIG_FW_LOADER=y
-CONFIG_FIRMWARE_IN_KERNEL=y
-CONFIG_EXTRA_FIRMWARE=""
-# CONFIG_DEBUG_DRIVER is not set
-# CONFIG_DEBUG_DEVRES is not set
-# CONFIG_SYS_HYPERVISOR is not set
-# CONFIG_MTD is not set
-# CONFIG_PARPORT is not set
-CONFIG_BLK_DEV=y
-# CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_BLK_DEV_CRYPTOLOOP is not set
-
-#
-# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
-#
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=16
-CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_BLK_DEV_XIP is not set
-# CONFIG_CDROM_PKTCDVD is not set
-# CONFIG_MG_DISK is not set
-# CONFIG_MISC_DEVICES is not set
-CONFIG_HAVE_IDE=y
-# CONFIG_IDE is not set
-
-#
-# SCSI device support
-#
-CONFIG_SCSI_MOD=y
-# CONFIG_RAID_ATTRS is not set
-CONFIG_SCSI=y
-CONFIG_SCSI_DMA=y
-# CONFIG_SCSI_TGT is not set
-# CONFIG_SCSI_NETLINK is not set
-CONFIG_SCSI_PROC_FS=y
-
-#
-# SCSI support type (disk, tape, CD-ROM)
-#
-CONFIG_BLK_DEV_SD=y
-# CONFIG_CHR_DEV_ST is not set
-# CONFIG_CHR_DEV_OSST is not set
-# CONFIG_BLK_DEV_SR is not set
-CONFIG_CHR_DEV_SG=y
-# CONFIG_CHR_DEV_SCH is not set
-# CONFIG_SCSI_MULTI_LUN is not set
-# CONFIG_SCSI_CONSTANTS is not set
-# CONFIG_SCSI_LOGGING is not set
-# CONFIG_SCSI_SCAN_ASYNC is not set
-CONFIG_SCSI_WAIT_SCAN=m
-
-#
-# SCSI Transports
-#
-# CONFIG_SCSI_SPI_ATTRS is not set
-# CONFIG_SCSI_FC_ATTRS is not set
-# CONFIG_SCSI_SAS_LIBSAS is not set
-# CONFIG_SCSI_SRP_ATTRS is not set
-CONFIG_SCSI_LOWLEVEL=y
-# CONFIG_LIBFC is not set
-# CONFIG_LIBFCOE is not set
-# CONFIG_SCSI_DEBUG is not set
-# CONFIG_SCSI_DH is not set
-# CONFIG_SCSI_OSD_INITIATOR is not set
-# CONFIG_ATA is not set
-# CONFIG_MD is not set
-# CONFIG_PHONE is not set
-
-#
-# Input device support
-#
-CONFIG_INPUT=y
-# CONFIG_INPUT_FF_MEMLESS is not set
-# CONFIG_INPUT_POLLDEV is not set
-# CONFIG_INPUT_SPARSEKMAP is not set
-
-#
-# Userland interfaces
-#
-CONFIG_INPUT_MOUSEDEV=y
-CONFIG_INPUT_MOUSEDEV_PSAUX=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
-# CONFIG_INPUT_JOYDEV is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_INPUT_EVBUG is not set
-
-#
-# Input Device Drivers
-#
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_INPUT_JOYSTICK is not set
-# CONFIG_INPUT_TABLET is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-# CONFIG_TOUCHSCREEN_AD7879 is not set
-# CONFIG_TOUCHSCREEN_DYNAPRO is not set
-# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
-# CONFIG_TOUCHSCREEN_FUJITSU is not set
-# CONFIG_TOUCHSCREEN_GUNZE is not set
-# CONFIG_TOUCHSCREEN_ELO is not set
-# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
-# CONFIG_TOUCHSCREEN_MTOUCH is not set
-# CONFIG_TOUCHSCREEN_INEXIO is not set
-# CONFIG_TOUCHSCREEN_MK712 is not set
-# CONFIG_TOUCHSCREEN_PENMOUNT is not set
-# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
-# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
-# CONFIG_TOUCHSCREEN_W90X900 is not set
-# CONFIG_INPUT_MISC is not set
-
-#
-# Hardware I/O ports
-#
-CONFIG_SERIO=y
-CONFIG_SERIO_SERPORT=y
-# CONFIG_SERIO_RAW is not set
-# CONFIG_SERIO_ALTERA_PS2 is not set
-# CONFIG_GAMEPORT is not set
-
-#
-# Character devices
-#
-CONFIG_VT=y
-CONFIG_CONSOLE_TRANSLATIONS=y
-CONFIG_VT_CONSOLE=y
-CONFIG_HW_CONSOLE=y
-# CONFIG_VT_HW_CONSOLE_BINDING is not set
-CONFIG_DEVKMEM=y
-# CONFIG_SERIAL_NONSTANDARD is not set
-
-#
-# Serial drivers
-#
-CONFIG_SERIAL_8250=y
-# CONFIG_SERIAL_8250_CONSOLE is not set
-CONFIG_SERIAL_8250_NR_UARTS=4
-CONFIG_SERIAL_8250_RUNTIME_UARTS=4
-# CONFIG_SERIAL_8250_EXTENDED is not set
-
-#
-# Non-8250 serial port support
-#
-CONFIG_SERIAL_SAMSUNG=y
-CONFIG_SERIAL_SAMSUNG_UARTS_4=y
-CONFIG_SERIAL_SAMSUNG_UARTS=4
-# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
-CONFIG_SERIAL_SAMSUNG_CONSOLE=y
-CONFIG_SERIAL_S5PV210=y
-CONFIG_SERIAL_CORE=y
-CONFIG_SERIAL_CORE_CONSOLE=y
-# CONFIG_SERIAL_TIMBERDALE is not set
-# CONFIG_SERIAL_ALTERA_JTAGUART is not set
-# CONFIG_SERIAL_ALTERA_UART is not set
-CONFIG_UNIX98_PTYS=y
-# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
-CONFIG_LEGACY_PTYS=y
-CONFIG_LEGACY_PTY_COUNT=256
-# CONFIG_IPMI_HANDLER is not set
-CONFIG_HW_RANDOM=y
-# CONFIG_HW_RANDOM_TIMERIOMEM is not set
-# CONFIG_R3964 is not set
-# CONFIG_RAW_DRIVER is not set
-# CONFIG_TCG_TPM is not set
-# CONFIG_I2C is not set
-# CONFIG_SPI is not set
-
-#
-# PPS support
-#
-# CONFIG_PPS is not set
-CONFIG_ARCH_REQUIRE_GPIOLIB=y
-CONFIG_GPIOLIB=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_GPIO_SYSFS is not set
-
-#
-# Memory mapped GPIO expanders:
-#
-# CONFIG_GPIO_IT8761E is not set
-
-#
-# I2C GPIO expanders:
-#
-
-#
-# PCI GPIO expanders:
-#
-
-#
-# SPI GPIO expanders:
-#
-
-#
-# AC97 GPIO expanders:
-#
-# CONFIG_W1 is not set
-# CONFIG_POWER_SUPPLY is not set
-# CONFIG_HWMON is not set
-# CONFIG_THERMAL is not set
-# CONFIG_WATCHDOG is not set
-CONFIG_HAVE_S3C2410_WATCHDOG=y
-CONFIG_SSB_POSSIBLE=y
-
-#
-# Sonics Silicon Backplane
-#
-# CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
-# CONFIG_MFD_CORE is not set
-# CONFIG_MFD_SM501 is not set
-# CONFIG_MFD_ASIC3 is not set
-# CONFIG_HTC_EGPIO is not set
-# CONFIG_HTC_PASIC3 is not set
-# CONFIG_MFD_TMIO is not set
-# CONFIG_MFD_T7L66XB is not set
-# CONFIG_MFD_TC6387XB is not set
-# CONFIG_MFD_TC6393XB is not set
-# CONFIG_REGULATOR is not set
-# CONFIG_MEDIA_SUPPORT is not set
-
-#
-# Graphics support
-#
-# CONFIG_VGASTATE is not set
-# CONFIG_VIDEO_OUTPUT_CONTROL is not set
-# CONFIG_FB is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
-
-#
-# Display device support
-#
-# CONFIG_DISPLAY_SUPPORT is not set
-
-#
-# Console display driver support
-#
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_DUMMY_CONSOLE=y
-# CONFIG_SOUND is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_MMC is not set
-# CONFIG_MEMSTICK is not set
-# CONFIG_NEW_LEDS is not set
-# CONFIG_ACCESSIBILITY is not set
-CONFIG_RTC_LIB=y
-# CONFIG_RTC_CLASS is not set
-# CONFIG_DMADEVICES is not set
-# CONFIG_AUXDISPLAY is not set
-# CONFIG_UIO is not set
-# CONFIG_STAGING is not set
-
-#
-# File systems
-#
-CONFIG_EXT2_FS=y
-# CONFIG_EXT2_FS_XATTR is not set
-# CONFIG_EXT2_FS_XIP is not set
-# CONFIG_EXT3_FS is not set
-# CONFIG_EXT4_FS is not set
-# CONFIG_REISERFS_FS is not set
-# CONFIG_JFS_FS is not set
-CONFIG_FS_POSIX_ACL=y
-# CONFIG_XFS_FS is not set
-# CONFIG_GFS2_FS is not set
-# CONFIG_BTRFS_FS is not set
-# CONFIG_NILFS2_FS is not set
-CONFIG_FILE_LOCKING=y
-CONFIG_FSNOTIFY=y
-CONFIG_DNOTIFY=y
-CONFIG_INOTIFY=y
-CONFIG_INOTIFY_USER=y
-# CONFIG_QUOTA is not set
-# CONFIG_AUTOFS_FS is not set
-# CONFIG_AUTOFS4_FS is not set
-# CONFIG_FUSE_FS is not set
-CONFIG_GENERIC_ACL=y
-
-#
-# Caches
-#
-# CONFIG_FSCACHE is not set
-
-#
-# CD-ROM/DVD Filesystems
-#
-# CONFIG_ISO9660_FS is not set
-# CONFIG_UDF_FS is not set
-
-#
-# DOS/FAT/NT Filesystems
-#
-CONFIG_FAT_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_CODEPAGE=437
-CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
-# CONFIG_NTFS_FS is not set
-
-#
-# Pseudo filesystems
-#
-CONFIG_PROC_FS=y
-CONFIG_PROC_SYSCTL=y
-CONFIG_PROC_PAGE_MONITOR=y
-CONFIG_SYSFS=y
-CONFIG_TMPFS=y
-CONFIG_TMPFS_POSIX_ACL=y
-# CONFIG_HUGETLB_PAGE is not set
-# CONFIG_CONFIGFS_FS is not set
-CONFIG_MISC_FILESYSTEMS=y
-# CONFIG_ADFS_FS is not set
-# CONFIG_AFFS_FS is not set
-# CONFIG_HFS_FS is not set
-# CONFIG_HFSPLUS_FS is not set
-# CONFIG_BEFS_FS is not set
-# CONFIG_BFS_FS is not set
-# CONFIG_EFS_FS is not set
-# CONFIG_LOGFS is not set
-CONFIG_CRAMFS=y
-# CONFIG_SQUASHFS is not set
-# CONFIG_VXFS_FS is not set
-# CONFIG_MINIX_FS is not set
-# CONFIG_OMFS_FS is not set
-# CONFIG_HPFS_FS is not set
-# CONFIG_QNX4FS_FS is not set
-CONFIG_ROMFS_FS=y
-CONFIG_ROMFS_BACKED_BY_BLOCK=y
-# CONFIG_ROMFS_BACKED_BY_MTD is not set
-# CONFIG_ROMFS_BACKED_BY_BOTH is not set
-CONFIG_ROMFS_ON_BLOCK=y
-# CONFIG_SYSV_FS is not set
-# CONFIG_UFS_FS is not set
-
-#
-# Partition Types
-#
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_ACORN_PARTITION is not set
-# CONFIG_OSF_PARTITION is not set
-# CONFIG_AMIGA_PARTITION is not set
-# CONFIG_ATARI_PARTITION is not set
-# CONFIG_MAC_PARTITION is not set
-CONFIG_MSDOS_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-# CONFIG_MINIX_SUBPARTITION is not set
-CONFIG_SOLARIS_X86_PARTITION=y
-# CONFIG_UNIXWARE_DISKLABEL is not set
-# CONFIG_LDM_PARTITION is not set
-# CONFIG_SGI_PARTITION is not set
-# CONFIG_ULTRIX_PARTITION is not set
-# CONFIG_SUN_PARTITION is not set
-# CONFIG_KARMA_PARTITION is not set
-# CONFIG_EFI_PARTITION is not set
-# CONFIG_SYSV68_PARTITION is not set
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="iso8859-1"
-CONFIG_NLS_CODEPAGE_437=y
-# CONFIG_NLS_CODEPAGE_737 is not set
-# CONFIG_NLS_CODEPAGE_775 is not set
-# CONFIG_NLS_CODEPAGE_850 is not set
-# CONFIG_NLS_CODEPAGE_852 is not set
-# CONFIG_NLS_CODEPAGE_855 is not set
-# CONFIG_NLS_CODEPAGE_857 is not set
-# CONFIG_NLS_CODEPAGE_860 is not set
-# CONFIG_NLS_CODEPAGE_861 is not set
-# CONFIG_NLS_CODEPAGE_862 is not set
-# CONFIG_NLS_CODEPAGE_863 is not set
-# CONFIG_NLS_CODEPAGE_864 is not set
-# CONFIG_NLS_CODEPAGE_865 is not set
-# CONFIG_NLS_CODEPAGE_866 is not set
-# CONFIG_NLS_CODEPAGE_869 is not set
-# CONFIG_NLS_CODEPAGE_936 is not set
-# CONFIG_NLS_CODEPAGE_950 is not set
-# CONFIG_NLS_CODEPAGE_932 is not set
-# CONFIG_NLS_CODEPAGE_949 is not set
-# CONFIG_NLS_CODEPAGE_874 is not set
-# CONFIG_NLS_ISO8859_8 is not set
-# CONFIG_NLS_CODEPAGE_1250 is not set
-# CONFIG_NLS_CODEPAGE_1251 is not set
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-# CONFIG_NLS_ISO8859_2 is not set
-# CONFIG_NLS_ISO8859_3 is not set
-# CONFIG_NLS_ISO8859_4 is not set
-# CONFIG_NLS_ISO8859_5 is not set
-# CONFIG_NLS_ISO8859_6 is not set
-# CONFIG_NLS_ISO8859_7 is not set
-# CONFIG_NLS_ISO8859_9 is not set
-# CONFIG_NLS_ISO8859_13 is not set
-# CONFIG_NLS_ISO8859_14 is not set
-# CONFIG_NLS_ISO8859_15 is not set
-# CONFIG_NLS_KOI8_R is not set
-# CONFIG_NLS_KOI8_U is not set
-# CONFIG_NLS_UTF8 is not set
-
-#
-# Kernel hacking
-#
-# CONFIG_PRINTK_TIME is not set
-CONFIG_ENABLE_WARN_DEPRECATED=y
-CONFIG_ENABLE_MUST_CHECK=y
-CONFIG_FRAME_WARN=1024
-CONFIG_MAGIC_SYSRQ=y
-# CONFIG_STRIP_ASM_SYMS is not set
-# CONFIG_UNUSED_SYMBOLS is not set
-# CONFIG_DEBUG_FS is not set
-# CONFIG_HEADERS_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_SHIRQ is not set
-CONFIG_DETECT_SOFTLOCKUP=y
-# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
-CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
-CONFIG_DETECT_HUNG_TASK=y
-# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
-CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
-CONFIG_SCHED_DEBUG=y
-# CONFIG_SCHEDSTATS is not set
-# CONFIG_TIMER_STATS is not set
-# CONFIG_DEBUG_OBJECTS is not set
-# CONFIG_SLUB_DEBUG_ON is not set
-# CONFIG_SLUB_STATS is not set
-# CONFIG_DEBUG_KMEMLEAK is not set
-# CONFIG_DEBUG_PREEMPT is not set
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_DEBUG_PI_LIST=y
-# CONFIG_RT_MUTEX_TESTER is not set
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_LOCK_ALLOC is not set
-# CONFIG_PROVE_LOCKING is not set
-# CONFIG_LOCK_STAT is not set
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
-# CONFIG_DEBUG_KOBJECT is not set
-CONFIG_DEBUG_BUGVERBOSE=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_DEBUG_VM is not set
-# CONFIG_DEBUG_WRITECOUNT is not set
-CONFIG_DEBUG_MEMORY_INIT=y
-# CONFIG_DEBUG_LIST is not set
-# CONFIG_DEBUG_SG is not set
-# CONFIG_DEBUG_NOTIFIERS is not set
-# CONFIG_DEBUG_CREDENTIALS is not set
-# CONFIG_BOOT_PRINTK_DELAY is not set
-# CONFIG_RCU_TORTURE_TEST is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-# CONFIG_BACKTRACE_SELF_TEST is not set
-# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
-# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
-# CONFIG_FAULT_INJECTION is not set
-# CONFIG_LATENCYTOP is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_FUNCTION_TRACER=y
-CONFIG_TRACING_SUPPORT=y
-CONFIG_FTRACE=y
-# CONFIG_FUNCTION_TRACER is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_PREEMPT_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_ENABLE_DEFAULT_TRACERS is not set
-# CONFIG_BOOT_TRACER is not set
-CONFIG_BRANCH_PROFILE_NONE=y
-# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
-# CONFIG_PROFILE_ALL_BRANCHES is not set
-# CONFIG_STACK_TRACER is not set
-# CONFIG_KMEMTRACE is not set
-# CONFIG_WORKQUEUE_TRACER is not set
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_ATOMIC64_SELFTEST is not set
-# CONFIG_SAMPLES is not set
-CONFIG_HAVE_ARCH_KGDB=y
-# CONFIG_KGDB is not set
-CONFIG_ARM_UNWIND=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
-# CONFIG_DEBUG_STACK_USAGE is not set
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
-# CONFIG_DEBUG_ICEDCC is not set
-# CONFIG_OC_ETM is not set
-CONFIG_DEBUG_S3C_UART=1
-
-#
-# Security options
-#
-# CONFIG_KEYS is not set
-# CONFIG_SECURITY is not set
-# CONFIG_SECURITYFS is not set
-# CONFIG_DEFAULT_SECURITY_SELINUX is not set
-# CONFIG_DEFAULT_SECURITY_SMACK is not set
-# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
-CONFIG_DEFAULT_SECURITY_DAC=y
-CONFIG_DEFAULT_SECURITY=""
-# CONFIG_CRYPTO is not set
-# CONFIG_BINARY_PRINTF is not set
-
-#
-# Library routines
-#
-CONFIG_BITREVERSE=y
-CONFIG_GENERIC_FIND_LAST_BIT=y
-CONFIG_CRC_CCITT=y
-# CONFIG_CRC16 is not set
-# CONFIG_CRC_T10DIF is not set
-# CONFIG_CRC_ITU_T is not set
-CONFIG_CRC32=y
-# CONFIG_CRC7 is not set
-# CONFIG_LIBCRC32C is not set
-CONFIG_ZLIB_INFLATE=y
-CONFIG_LZO_DECOMPRESS=y
-CONFIG_DECOMPRESS_GZIP=y
-CONFIG_DECOMPRESS_BZIP2=y
-CONFIG_DECOMPRESS_LZMA=y
-CONFIG_DECOMPRESS_LZO=y
-CONFIG_HAS_IOMEM=y
-CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig
index e2f5bce..5d447c1 100644
--- a/arch/arm/configs/s5pv210_defconfig
+++ b/arch/arm/configs/s5pv210_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.34
-# Wed May 26 19:04:39 2010
+# Linux kernel version: 2.6.35-rc3
+# Wed Jun 16 08:03:01 2010
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -34,6 +34,7 @@ CONFIG_EXPERIMENTAL=y
 CONFIG_BROKEN_ON_SMP=y
 CONFIG_LOCK_KERNEL=y
 CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
 CONFIG_LOCALVERSION=""
 CONFIG_LOCALVERSION_AUTO=y
 CONFIG_HAVE_KERNEL_GZIP=y
@@ -253,6 +254,7 @@ CONFIG_SAMSUNG_GPIO_EXTRA=0
 CONFIG_S3C_GPIO_SPACE=0
 CONFIG_S3C_GPIO_TRACK=y
 # CONFIG_S3C_ADC is not set
+CONFIG_S3C_DEV_FB=y
 CONFIG_S3C_DEV_WDT=y
 CONFIG_SAMSUNG_DEV_ADC=y
 CONFIG_SAMSUNG_DEV_TS=y
@@ -264,10 +266,19 @@ CONFIG_S3C_PL330_DMA=y
 CONFIG_PLAT_S5P=y
 CONFIG_S5P_EXT_INT=y
 CONFIG_CPU_S5PV210=y
-# CONFIG_MACH_AQUILA is not set
+CONFIG_S5PV210_SETUP_FB_24BPP=y
+
+#
+# S5PC110 Machines
+#
+CONFIG_MACH_AQUILA=y
 # CONFIG_MACH_GONI is not set
+CONFIG_MACH_SMDKC110=y
+
+#
+# S5PV210 Machines
+#
 CONFIG_MACH_SMDKV210=y
-# CONFIG_MACH_SMDKC110 is not set
 
 #
 # Processor Type
@@ -567,6 +578,7 @@ CONFIG_HW_RANDOM=y
 # CONFIG_R3964 is not set
 # CONFIG_RAW_DRIVER is not set
 # CONFIG_TCG_TPM is not set
+# CONFIG_RAMOOPS is not set
 # CONFIG_I2C is not set
 # CONFIG_SPI is not set
 
@@ -599,6 +611,10 @@ CONFIG_GPIOLIB=y
 #
 # AC97 GPIO expanders:
 #
+
+#
+# MODULbus GPIO expanders:
+#
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
@@ -611,10 +627,7 @@ CONFIG_SSB_POSSIBLE=y
 # Sonics Silicon Backplane
 #
 # CONFIG_SSB is not set
-
-#
-# Multifunction device drivers
-#
+CONFIG_MFD_SUPPORT=y
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
 # CONFIG_MFD_ASIC3 is not set
@@ -624,6 +637,7 @@ CONFIG_SSB_POSSIBLE=y
 # CONFIG_MFD_T7L66XB is not set
 # CONFIG_MFD_TC6387XB is not set
 # CONFIG_MFD_TC6393XB is not set
+# CONFIG_ABX500_CORE is not set
 # CONFIG_REGULATOR is not set
 # CONFIG_MEDIA_SUPPORT is not set
 
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0761eac..8150480 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -43,10 +43,10 @@ config S5PV210_SETUP_SDHCI_GPIO
 	help
 	  Common setup code for SDHCI gpio.
 
-# machine support
+menu "S5PC110 Machines"
 
 config MACH_AQUILA
-	bool "Samsung Aquila"
+	bool "Aquila"
 	select CPU_S5PV210
 	select ARCH_SPARSEMEM_ENABLE
 	select S5PV210_SETUP_FB_24BPP
@@ -62,11 +62,25 @@ config MACH_GONI
 	  Machine support for Samsung GONI board
 	  S5PC110(MCP) is one of package option of S5PV210
 
+config MACH_SMDKC110
+	bool "SMDKC110"
+	select CPU_S5PV210
+	select ARCH_SPARSEMEM_ENABLE
+	select S3C_DEV_WDT
+	select HAVE_S3C2410_WATCHDOG
+	help
+	  Machine support for Samsung SMDKC110
+	  S5PC110(MCP) is one of package option of S5PV210
+
+endmenu
+
 config S5PC110_DEV_ONENAND
 	bool
 	help
 	  Compile in platform device definition for OneNAND1 controller
 
+menu "S5PV210 Machines"
+
 config MACH_SMDKV210
 	bool "SMDKV210"
 	select CPU_S5PV210
@@ -78,14 +92,6 @@ config MACH_SMDKV210
 	help
 	  Machine support for Samsung SMDKV210
 
-config MACH_SMDKC110
-	bool "SMDKC110"
-	select CPU_S5PV210
-	select ARCH_SPARSEMEM_ENABLE
-	select S3C_DEV_WDT
-	select HAVE_S3C2410_WATCHDOG
-	help
-	  Machine support for Samsung SMDKC110
-	  S5PC110(MCP) is one of package option of S5PV210
+endmenu
 
 endif
-- 
1.6.2.5



From marek.vasut at gmail.com  Tue Jun 15 19:59:08 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 16 Jun 2010 01:59:08 +0200
Subject: [PATCH] ixp4xx: add support for static flash partitions
In-Reply-To: <20100614161519.GB24877@riccoc20.at.omicron.at>
References: <20100531162434.GA4599@riccoc20.at.omicron.at>
	<1276420566.19028.184.camel@localhost>
	<20100614161519.GB24877@riccoc20.at.omicron.at>
Message-ID: <201006160159.08491.marek.vasut@gmail.com>

Dne Po 14. ?ervna 2010 18:15:19 Richard Cochran napsal(a):
> On Sun, Jun 13, 2010 at 12:16:06PM +0300, Artem Bityutskiy wrote:
> > I could fix your patch up myself, but I do not know the code, so please,
> > re-send a patch against the latest mtd-2.6 tree.
> 
> Okay, here it is again, this time against today's master branch of
> git://git.infradead.org/mtd-2.6.git
> 
> Thanks,
> Richard
> 
> 
> This patch adds support for static flash partitioning from a platform
> device. Also, we clean up some weirdness where statements were separated
> by commas instead of semicolons. While we are at it, fix some minor bad
> white space, too.
> 
> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>
> ---
>  drivers/mtd/maps/ixp4xx.c |   35 +++++++++++++++++++++++++++--------
>  1 files changed, 27 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/mtd/maps/ixp4xx.c b/drivers/mtd/maps/ixp4xx.c
> index e0a5e04..1f9fde0 100644
> --- a/drivers/mtd/maps/ixp4xx.c
> +++ b/drivers/mtd/maps/ixp4xx.c
> @@ -118,7 +118,7 @@ static void ixp4xx_copy_from(struct map_info *map, void
> *to, *dest++ = BYTE1(data);
>  		src += 2;
>  		len -= 2;
> -        }
> +	}
> 
>  	if (len > 0)
>  		*dest++ = BYTE0(flash_read16(src));
> @@ -185,6 +185,8 @@ static int ixp4xx_flash_probe(struct platform_device
> *dev) {
>  	struct flash_platform_data *plat = dev->dev.platform_data;
>  	struct ixp4xx_flash_info *info;
> +	const char *part_type = NULL;
> +	int nr_parts = 0;
>  	int err = -1;
> 
>  	if (!plat)
> @@ -218,9 +220,9 @@ static int ixp4xx_flash_probe(struct platform_device
> *dev) */
>  	info->map.bankwidth = 2;
>  	info->map.name = dev_name(&dev->dev);
> -	info->map.read = ixp4xx_read16,
> -	info->map.write = ixp4xx_probe_write16,
> -	info->map.copy_from = ixp4xx_copy_from,
> +	info->map.read = ixp4xx_read16;
> +	info->map.write = ixp4xx_probe_write16;
> +	info->map.copy_from = ixp4xx_copy_from;
> 
>  	info->res = request_mem_region(dev->resource->start,
>  			resource_size(dev->resource),
> @@ -248,11 +250,28 @@ static int ixp4xx_flash_probe(struct platform_device
> *dev) info->mtd->owner = THIS_MODULE;
> 
>  	/* Use the fast version */
> -	info->map.write = ixp4xx_write16,
> +	info->map.write = ixp4xx_write16;
> +
> +#ifdef CONFIG_MTD_PARTITIONS
> +	nr_parts = parse_mtd_partitions(info->mtd, probes, &info->partitions,
> +					dev->resource->start);
> +#endif
> +	if (nr_parts > 0) {
> +		part_type = "dynamic";
> +	} else {
> +		info->partitions = plat->parts;
> +		nr_parts = plat->nr_parts;
> +		part_type = "static";
> +	}
> +	if (nr_parts == 0) {
> +		printk(KERN_NOTICE "IXP4xx flash: no partition info "
> +			"available, registering whole flash\n");
> +		err = add_mtd_device(info->mtd);
> +	} else {
> +		printk(KERN_NOTICE "IXP4xx flash: using %s partition "
> +			"definition\n", part_type);
> +		err = add_mtd_partitions(info->mtd, info->partitions, nr_parts);
> 
> -	err = parse_mtd_partitions(info->mtd, probes, &info->partitions,
> dev->resource->start); -	if (err > 0) {
> -		err = add_mtd_partitions(info->mtd, info->partitions, err);
>  		if(err)
>  			printk(KERN_ERR "Could not parse partitions\n");
>  	}


Maybe send the formating fixes in a separate patch. Thanks


From marek.vasut at gmail.com  Tue Jun 15 20:05:03 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 16 Jun 2010 02:05:03 +0200
Subject: [PATCH 1/2] NUC900:  Add i2c0 driver support for NUC900
In-Reply-To: <20100615051905.GD3233@jasper.tkos.co.il>
References: <4C15143C.1020603@gmail.com>
	<20100615051905.GD3233@jasper.tkos.co.il>
Message-ID: <201006160205.04009.marek.vasut@gmail.com>

Dne ?t 15. ?ervna 2010 07:19:05 Baruch Siach napsal(a):
> Hi Wan,
> 
> On Mon, Jun 14, 2010 at 01:24:12AM +0800, Wan ZongShun wrote:
> > This patch is to add i2c0 driver support for NUC900.
> > 
> > Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
> > 
> > ---
> 
> [snip]
> 
> > +	pdata->get_clock(NULL, NULL, &apbclk_khz);
> 
> Why not use clk_get_rate() for this?
> 
> baruch

Other but what you already pointed out I can't find.

Reviewed-by: Marek Vasut <marek.vasut at gmail.com>


From kmpark at infradead.org  Tue Jun 15 20:07:25 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Wed, 16 Jun 2010 09:07:25 +0900
Subject: [PATCH] ARM: s5pv210_defconfig: Update for removing 
	s5pc110_defconfig
In-Reply-To: <1276645344-16623-1-git-send-email-kgene.kim@samsung.com>
References: <1276645344-16623-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <AANLkTilROdCkyX1Q0rMYYhhNxzdj5Mf3F4PWRGxG0DXO@mail.gmail.com>

Acked-by: Kyungmin Park <kyungmin.park at samsung.com>

P.s. How about the define C110_COMMON select to reduce Kconfig lines?
in case of c110 has almost same features. sparemem, 24 fb, rtc, and so
on.

On Wed, Jun 16, 2010 at 8:42 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Now that S5PC110 machines and S5PV210 machines can be built into
> one kernel, update mach-s5pv210/Kconfig and s5pv210_defconfig.
>
> Tested on SMDKC110(S5PC110) and SMDKV210(S5PV210).
> Note that GONI machine ID is not included in the kernel.
>
> Created and tested against linux-2.6.35-rc3.
>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
> ?arch/arm/configs/s5pc110_defconfig | ?924 ------------------------------------
> ?arch/arm/configs/s5pv210_defconfig | ? 30 +-
> ?arch/arm/mach-s5pv210/Kconfig ? ? ?| ? 28 +-
> ?3 files changed, 39 insertions(+), 943 deletions(-)
> ?delete mode 100644 arch/arm/configs/s5pc110_defconfig
>
> diff --git a/arch/arm/configs/s5pc110_defconfig b/arch/arm/configs/s5pc110_defconfig
> deleted file mode 100644
> index c4de360..0000000
> --- a/arch/arm/configs/s5pc110_defconfig
> +++ /dev/null
> @@ -1,924 +0,0 @@
> -#
> -# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.34
> -# Wed May 26 19:04:37 2010
> -#
> -CONFIG_ARM=y
> -CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> -CONFIG_GENERIC_GPIO=y
> -CONFIG_GENERIC_TIME=y
> -CONFIG_ARCH_USES_GETTIMEOFFSET=y
> -CONFIG_HAVE_PROC_CPU=y
> -CONFIG_NO_IOPORT=y
> -CONFIG_GENERIC_HARDIRQS=y
> -CONFIG_STACKTRACE_SUPPORT=y
> -CONFIG_HAVE_LATENCYTOP_SUPPORT=y
> -CONFIG_LOCKDEP_SUPPORT=y
> -CONFIG_TRACE_IRQFLAGS_SUPPORT=y
> -CONFIG_HARDIRQS_SW_RESEND=y
> -CONFIG_GENERIC_IRQ_PROBE=y
> -CONFIG_RWSEM_GENERIC_SPINLOCK=y
> -CONFIG_GENERIC_HWEIGHT=y
> -CONFIG_GENERIC_CALIBRATE_DELAY=y
> -CONFIG_NEED_DMA_MAP_STATE=y
> -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
> -CONFIG_ARM_L1_CACHE_SHIFT_6=y
> -CONFIG_VECTORS_BASE=0xffff0000
> -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
> -CONFIG_CONSTRUCTORS=y
> -
> -#
> -# General setup
> -#
> -CONFIG_EXPERIMENTAL=y
> -CONFIG_BROKEN_ON_SMP=y
> -CONFIG_LOCK_KERNEL=y
> -CONFIG_INIT_ENV_ARG_LIMIT=32
> -CONFIG_LOCALVERSION=""
> -CONFIG_LOCALVERSION_AUTO=y
> -CONFIG_HAVE_KERNEL_GZIP=y
> -CONFIG_HAVE_KERNEL_LZMA=y
> -CONFIG_HAVE_KERNEL_LZO=y
> -CONFIG_KERNEL_GZIP=y
> -# CONFIG_KERNEL_BZIP2 is not set
> -# CONFIG_KERNEL_LZMA is not set
> -# CONFIG_KERNEL_LZO is not set
> -CONFIG_SWAP=y
> -# CONFIG_SYSVIPC is not set
> -# CONFIG_BSD_PROCESS_ACCT is not set
> -
> -#
> -# RCU Subsystem
> -#
> -CONFIG_TREE_RCU=y
> -# CONFIG_TREE_PREEMPT_RCU is not set
> -# CONFIG_TINY_RCU is not set
> -# CONFIG_RCU_TRACE is not set
> -CONFIG_RCU_FANOUT=32
> -# CONFIG_RCU_FANOUT_EXACT is not set
> -# CONFIG_TREE_RCU_TRACE is not set
> -# CONFIG_IKCONFIG is not set
> -CONFIG_LOG_BUF_SHIFT=17
> -# CONFIG_CGROUPS is not set
> -CONFIG_SYSFS_DEPRECATED=y
> -CONFIG_SYSFS_DEPRECATED_V2=y
> -# CONFIG_RELAY is not set
> -CONFIG_NAMESPACES=y
> -# CONFIG_UTS_NS is not set
> -# CONFIG_USER_NS is not set
> -# CONFIG_PID_NS is not set
> -CONFIG_BLK_DEV_INITRD=y
> -CONFIG_INITRAMFS_SOURCE=""
> -CONFIG_RD_GZIP=y
> -CONFIG_RD_BZIP2=y
> -CONFIG_RD_LZMA=y
> -CONFIG_RD_LZO=y
> -CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> -CONFIG_SYSCTL=y
> -CONFIG_ANON_INODES=y
> -# CONFIG_EMBEDDED is not set
> -CONFIG_UID16=y
> -CONFIG_SYSCTL_SYSCALL=y
> -CONFIG_KALLSYMS=y
> -CONFIG_KALLSYMS_ALL=y
> -# CONFIG_KALLSYMS_EXTRA_PASS is not set
> -CONFIG_HOTPLUG=y
> -CONFIG_PRINTK=y
> -CONFIG_BUG=y
> -CONFIG_ELF_CORE=y
> -CONFIG_BASE_FULL=y
> -CONFIG_FUTEX=y
> -CONFIG_EPOLL=y
> -CONFIG_SIGNALFD=y
> -CONFIG_TIMERFD=y
> -CONFIG_EVENTFD=y
> -CONFIG_SHMEM=y
> -CONFIG_AIO=y
> -CONFIG_HAVE_PERF_EVENTS=y
> -CONFIG_PERF_USE_VMALLOC=y
> -
> -#
> -# Kernel Performance Events And Counters
> -#
> -# CONFIG_PERF_EVENTS is not set
> -# CONFIG_PERF_COUNTERS is not set
> -CONFIG_VM_EVENT_COUNTERS=y
> -CONFIG_SLUB_DEBUG=y
> -CONFIG_COMPAT_BRK=y
> -# CONFIG_SLAB is not set
> -CONFIG_SLUB=y
> -# CONFIG_SLOB is not set
> -# CONFIG_PROFILING is not set
> -CONFIG_HAVE_OPROFILE=y
> -# CONFIG_KPROBES is not set
> -CONFIG_HAVE_KPROBES=y
> -CONFIG_HAVE_KRETPROBES=y
> -CONFIG_HAVE_CLK=y
> -
> -#
> -# GCOV-based kernel profiling
> -#
> -# CONFIG_SLOW_WORK is not set
> -CONFIG_HAVE_GENERIC_DMA_COHERENT=y
> -CONFIG_SLABINFO=y
> -CONFIG_RT_MUTEXES=y
> -CONFIG_BASE_SMALL=0
> -CONFIG_MODULES=y
> -# CONFIG_MODULE_FORCE_LOAD is not set
> -CONFIG_MODULE_UNLOAD=y
> -# CONFIG_MODULE_FORCE_UNLOAD is not set
> -# CONFIG_MODVERSIONS is not set
> -# CONFIG_MODULE_SRCVERSION_ALL is not set
> -CONFIG_BLOCK=y
> -CONFIG_LBDAF=y
> -# CONFIG_BLK_DEV_BSG is not set
> -# CONFIG_BLK_DEV_INTEGRITY is not set
> -
> -#
> -# IO Schedulers
> -#
> -CONFIG_IOSCHED_NOOP=y
> -CONFIG_IOSCHED_DEADLINE=y
> -CONFIG_IOSCHED_CFQ=y
> -# CONFIG_DEFAULT_DEADLINE is not set
> -CONFIG_DEFAULT_CFQ=y
> -# CONFIG_DEFAULT_NOOP is not set
> -CONFIG_DEFAULT_IOSCHED="cfq"
> -# CONFIG_INLINE_SPIN_TRYLOCK is not set
> -# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
> -# CONFIG_INLINE_SPIN_LOCK is not set
> -# CONFIG_INLINE_SPIN_LOCK_BH is not set
> -# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
> -# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
> -# CONFIG_INLINE_SPIN_UNLOCK is not set
> -# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
> -# CONFIG_INLINE_SPIN_UNLOCK_IRQ is not set
> -# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
> -# CONFIG_INLINE_READ_TRYLOCK is not set
> -# CONFIG_INLINE_READ_LOCK is not set
> -# CONFIG_INLINE_READ_LOCK_BH is not set
> -# CONFIG_INLINE_READ_LOCK_IRQ is not set
> -# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
> -# CONFIG_INLINE_READ_UNLOCK is not set
> -# CONFIG_INLINE_READ_UNLOCK_BH is not set
> -# CONFIG_INLINE_READ_UNLOCK_IRQ is not set
> -# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
> -# CONFIG_INLINE_WRITE_TRYLOCK is not set
> -# CONFIG_INLINE_WRITE_LOCK is not set
> -# CONFIG_INLINE_WRITE_LOCK_BH is not set
> -# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
> -# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
> -# CONFIG_INLINE_WRITE_UNLOCK is not set
> -# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
> -# CONFIG_INLINE_WRITE_UNLOCK_IRQ is not set
> -# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
> -# CONFIG_MUTEX_SPIN_ON_OWNER is not set
> -# CONFIG_FREEZER is not set
> -
> -#
> -# System Type
> -#
> -CONFIG_MMU=y
> -# CONFIG_ARCH_AAEC2000 is not set
> -# CONFIG_ARCH_INTEGRATOR is not set
> -# CONFIG_ARCH_REALVIEW is not set
> -# CONFIG_ARCH_VERSATILE is not set
> -# CONFIG_ARCH_VEXPRESS is not set
> -# CONFIG_ARCH_AT91 is not set
> -# CONFIG_ARCH_BCMRING is not set
> -# CONFIG_ARCH_CLPS711X is not set
> -# CONFIG_ARCH_CNS3XXX is not set
> -# CONFIG_ARCH_GEMINI is not set
> -# CONFIG_ARCH_EBSA110 is not set
> -# CONFIG_ARCH_EP93XX is not set
> -# CONFIG_ARCH_FOOTBRIDGE is not set
> -# CONFIG_ARCH_MXC is not set
> -# CONFIG_ARCH_STMP3XXX is not set
> -# CONFIG_ARCH_NETX is not set
> -# CONFIG_ARCH_H720X is not set
> -# CONFIG_ARCH_IOP13XX is not set
> -# CONFIG_ARCH_IOP32X is not set
> -# CONFIG_ARCH_IOP33X is not set
> -# CONFIG_ARCH_IXP23XX is not set
> -# CONFIG_ARCH_IXP2000 is not set
> -# CONFIG_ARCH_IXP4XX is not set
> -# CONFIG_ARCH_L7200 is not set
> -# CONFIG_ARCH_DOVE is not set
> -# CONFIG_ARCH_KIRKWOOD is not set
> -# CONFIG_ARCH_LOKI is not set
> -# CONFIG_ARCH_MV78XX0 is not set
> -# CONFIG_ARCH_ORION5X is not set
> -# CONFIG_ARCH_MMP is not set
> -# CONFIG_ARCH_KS8695 is not set
> -# CONFIG_ARCH_NS9XXX is not set
> -# CONFIG_ARCH_W90X900 is not set
> -# CONFIG_ARCH_NUC93X is not set
> -# CONFIG_ARCH_PNX4008 is not set
> -# CONFIG_ARCH_PXA is not set
> -# CONFIG_ARCH_MSM is not set
> -# CONFIG_ARCH_SHMOBILE is not set
> -# CONFIG_ARCH_RPC is not set
> -# CONFIG_ARCH_SA1100 is not set
> -# CONFIG_ARCH_S3C2410 is not set
> -# CONFIG_ARCH_S3C64XX is not set
> -# CONFIG_ARCH_S5P6440 is not set
> -# CONFIG_ARCH_S5P6442 is not set
> -# CONFIG_ARCH_S5PC100 is not set
> -CONFIG_ARCH_S5PV210=y
> -# CONFIG_ARCH_SHARK is not set
> -# CONFIG_ARCH_LH7A40X is not set
> -# CONFIG_ARCH_U300 is not set
> -# CONFIG_ARCH_U8500 is not set
> -# CONFIG_ARCH_NOMADIK is not set
> -# CONFIG_ARCH_DAVINCI is not set
> -# CONFIG_ARCH_OMAP is not set
> -# CONFIG_PLAT_SPEAR is not set
> -CONFIG_PLAT_SAMSUNG=y
> -
> -#
> -# Boot options
> -#
> -# CONFIG_S3C_BOOT_ERROR_RESET is not set
> -CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
> -CONFIG_S3C_LOWLEVEL_UART_PORT=1
> -CONFIG_SAMSUNG_CLKSRC=y
> -CONFIG_SAMSUNG_IRQ_VIC_TIMER=y
> -CONFIG_SAMSUNG_IRQ_UART=y
> -CONFIG_SAMSUNG_GPIOLIB_4BIT=y
> -CONFIG_S3C_GPIO_CFG_S3C24XX=y
> -CONFIG_S3C_GPIO_CFG_S3C64XX=y
> -CONFIG_S3C_GPIO_PULL_UPDOWN=y
> -CONFIG_S5P_GPIO_DRVSTR=y
> -CONFIG_SAMSUNG_GPIO_EXTRA=0
> -CONFIG_S3C_GPIO_SPACE=0
> -CONFIG_S3C_GPIO_TRACK=y
> -# CONFIG_S3C_ADC is not set
> -CONFIG_S3C_DEV_WDT=y
> -CONFIG_S3C_PL330_DMA=y
> -
> -#
> -# Power management
> -#
> -CONFIG_PLAT_S5P=y
> -CONFIG_S5P_EXT_INT=y
> -CONFIG_CPU_S5PV210=y
> -# CONFIG_MACH_AQUILA is not set
> -# CONFIG_MACH_GONI is not set
> -# CONFIG_MACH_SMDKV210 is not set
> -CONFIG_MACH_SMDKC110=y
> -
> -#
> -# Processor Type
> -#
> -CONFIG_CPU_32v6K=y
> -CONFIG_CPU_V7=y
> -CONFIG_CPU_32v7=y
> -CONFIG_CPU_ABRT_EV7=y
> -CONFIG_CPU_PABRT_V7=y
> -CONFIG_CPU_CACHE_V7=y
> -CONFIG_CPU_CACHE_VIPT=y
> -CONFIG_CPU_COPY_V6=y
> -CONFIG_CPU_TLB_V7=y
> -CONFIG_CPU_HAS_ASID=y
> -CONFIG_CPU_CP15=y
> -CONFIG_CPU_CP15_MMU=y
> -
> -#
> -# Processor Features
> -#
> -CONFIG_ARM_THUMB=y
> -# CONFIG_ARM_THUMBEE is not set
> -# CONFIG_CPU_ICACHE_DISABLE is not set
> -# CONFIG_CPU_DCACHE_DISABLE is not set
> -# CONFIG_CPU_BPREDICT_DISABLE is not set
> -CONFIG_HAS_TLS_REG=y
> -CONFIG_ARM_L1_CACHE_SHIFT=6
> -CONFIG_ARM_DMA_MEM_BUFFERABLE=y
> -CONFIG_CPU_HAS_PMU=y
> -# CONFIG_ARM_ERRATA_430973 is not set
> -# CONFIG_ARM_ERRATA_458693 is not set
> -# CONFIG_ARM_ERRATA_460075 is not set
> -CONFIG_ARM_VIC=y
> -CONFIG_ARM_VIC_NR=2
> -CONFIG_PL330=y
> -
> -#
> -# Bus support
> -#
> -# CONFIG_PCI_SYSCALL is not set
> -# CONFIG_ARCH_SUPPORTS_MSI is not set
> -# CONFIG_PCCARD is not set
> -
> -#
> -# Kernel Features
> -#
> -# CONFIG_VMSPLIT_3G is not set
> -CONFIG_VMSPLIT_2G=y
> -# CONFIG_VMSPLIT_1G is not set
> -CONFIG_PAGE_OFFSET=0x80000000
> -# CONFIG_PREEMPT_NONE is not set
> -# CONFIG_PREEMPT_VOLUNTARY is not set
> -CONFIG_PREEMPT=y
> -CONFIG_HZ=200
> -# CONFIG_THUMB2_KERNEL is not set
> -CONFIG_AEABI=y
> -CONFIG_OABI_COMPAT=y
> -CONFIG_ARCH_SPARSEMEM_ENABLE=y
> -CONFIG_ARCH_SPARSEMEM_DEFAULT=y
> -# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
> -# CONFIG_HIGHMEM is not set
> -CONFIG_SELECT_MEMORY_MODEL=y
> -# CONFIG_FLATMEM_MANUAL is not set
> -# CONFIG_DISCONTIGMEM_MANUAL is not set
> -CONFIG_SPARSEMEM_MANUAL=y
> -CONFIG_SPARSEMEM=y
> -CONFIG_HAVE_MEMORY_PRESENT=y
> -CONFIG_SPARSEMEM_EXTREME=y
> -CONFIG_SPLIT_PTLOCK_CPUS=999999
> -# CONFIG_PHYS_ADDR_T_64BIT is not set
> -CONFIG_ZONE_DMA_FLAG=0
> -CONFIG_VIRT_TO_BUS=y
> -# CONFIG_KSM is not set
> -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
> -CONFIG_ALIGNMENT_TRAP=y
> -# CONFIG_UACCESS_WITH_MEMCPY is not set
> -
> -#
> -# Boot options
> -#
> -CONFIG_ZBOOT_ROM_TEXT=0
> -CONFIG_ZBOOT_ROM_BSS=0
> -CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
> -# CONFIG_CMDLINE_FORCE is not set
> -# CONFIG_XIP_KERNEL is not set
> -# CONFIG_KEXEC is not set
> -
> -#
> -# CPU Power Management
> -#
> -# CONFIG_CPU_IDLE is not set
> -
> -#
> -# Floating point emulation
> -#
> -
> -#
> -# At least one emulation must be selected
> -#
> -# CONFIG_FPE_NWFPE is not set
> -# CONFIG_FPE_FASTFPE is not set
> -CONFIG_VFP=y
> -CONFIG_VFPv3=y
> -CONFIG_NEON=y
> -
> -#
> -# Userspace binary formats
> -#
> -CONFIG_BINFMT_ELF=y
> -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> -CONFIG_HAVE_AOUT=y
> -# CONFIG_BINFMT_AOUT is not set
> -# CONFIG_BINFMT_MISC is not set
> -
> -#
> -# Power management options
> -#
> -# CONFIG_PM is not set
> -CONFIG_ARCH_SUSPEND_POSSIBLE=y
> -# CONFIG_NET is not set
> -
> -#
> -# Device Drivers
> -#
> -
> -#
> -# Generic Driver Options
> -#
> -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> -# CONFIG_DEVTMPFS is not set
> -CONFIG_STANDALONE=y
> -CONFIG_PREVENT_FIRMWARE_BUILD=y
> -CONFIG_FW_LOADER=y
> -CONFIG_FIRMWARE_IN_KERNEL=y
> -CONFIG_EXTRA_FIRMWARE=""
> -# CONFIG_DEBUG_DRIVER is not set
> -# CONFIG_DEBUG_DEVRES is not set
> -# CONFIG_SYS_HYPERVISOR is not set
> -# CONFIG_MTD is not set
> -# CONFIG_PARPORT is not set
> -CONFIG_BLK_DEV=y
> -# CONFIG_BLK_DEV_COW_COMMON is not set
> -CONFIG_BLK_DEV_LOOP=y
> -# CONFIG_BLK_DEV_CRYPTOLOOP is not set
> -
> -#
> -# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
> -#
> -CONFIG_BLK_DEV_RAM=y
> -CONFIG_BLK_DEV_RAM_COUNT=16
> -CONFIG_BLK_DEV_RAM_SIZE=8192
> -# CONFIG_BLK_DEV_XIP is not set
> -# CONFIG_CDROM_PKTCDVD is not set
> -# CONFIG_MG_DISK is not set
> -# CONFIG_MISC_DEVICES is not set
> -CONFIG_HAVE_IDE=y
> -# CONFIG_IDE is not set
> -
> -#
> -# SCSI device support
> -#
> -CONFIG_SCSI_MOD=y
> -# CONFIG_RAID_ATTRS is not set
> -CONFIG_SCSI=y
> -CONFIG_SCSI_DMA=y
> -# CONFIG_SCSI_TGT is not set
> -# CONFIG_SCSI_NETLINK is not set
> -CONFIG_SCSI_PROC_FS=y
> -
> -#
> -# SCSI support type (disk, tape, CD-ROM)
> -#
> -CONFIG_BLK_DEV_SD=y
> -# CONFIG_CHR_DEV_ST is not set
> -# CONFIG_CHR_DEV_OSST is not set
> -# CONFIG_BLK_DEV_SR is not set
> -CONFIG_CHR_DEV_SG=y
> -# CONFIG_CHR_DEV_SCH is not set
> -# CONFIG_SCSI_MULTI_LUN is not set
> -# CONFIG_SCSI_CONSTANTS is not set
> -# CONFIG_SCSI_LOGGING is not set
> -# CONFIG_SCSI_SCAN_ASYNC is not set
> -CONFIG_SCSI_WAIT_SCAN=m
> -
> -#
> -# SCSI Transports
> -#
> -# CONFIG_SCSI_SPI_ATTRS is not set
> -# CONFIG_SCSI_FC_ATTRS is not set
> -# CONFIG_SCSI_SAS_LIBSAS is not set
> -# CONFIG_SCSI_SRP_ATTRS is not set
> -CONFIG_SCSI_LOWLEVEL=y
> -# CONFIG_LIBFC is not set
> -# CONFIG_LIBFCOE is not set
> -# CONFIG_SCSI_DEBUG is not set
> -# CONFIG_SCSI_DH is not set
> -# CONFIG_SCSI_OSD_INITIATOR is not set
> -# CONFIG_ATA is not set
> -# CONFIG_MD is not set
> -# CONFIG_PHONE is not set
> -
> -#
> -# Input device support
> -#
> -CONFIG_INPUT=y
> -# CONFIG_INPUT_FF_MEMLESS is not set
> -# CONFIG_INPUT_POLLDEV is not set
> -# CONFIG_INPUT_SPARSEKMAP is not set
> -
> -#
> -# Userland interfaces
> -#
> -CONFIG_INPUT_MOUSEDEV=y
> -CONFIG_INPUT_MOUSEDEV_PSAUX=y
> -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
> -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
> -# CONFIG_INPUT_JOYDEV is not set
> -CONFIG_INPUT_EVDEV=y
> -# CONFIG_INPUT_EVBUG is not set
> -
> -#
> -# Input Device Drivers
> -#
> -# CONFIG_INPUT_KEYBOARD is not set
> -# CONFIG_INPUT_MOUSE is not set
> -# CONFIG_INPUT_JOYSTICK is not set
> -# CONFIG_INPUT_TABLET is not set
> -CONFIG_INPUT_TOUCHSCREEN=y
> -# CONFIG_TOUCHSCREEN_AD7879 is not set
> -# CONFIG_TOUCHSCREEN_DYNAPRO is not set
> -# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
> -# CONFIG_TOUCHSCREEN_FUJITSU is not set
> -# CONFIG_TOUCHSCREEN_GUNZE is not set
> -# CONFIG_TOUCHSCREEN_ELO is not set
> -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
> -# CONFIG_TOUCHSCREEN_MTOUCH is not set
> -# CONFIG_TOUCHSCREEN_INEXIO is not set
> -# CONFIG_TOUCHSCREEN_MK712 is not set
> -# CONFIG_TOUCHSCREEN_PENMOUNT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
> -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
> -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
> -# CONFIG_TOUCHSCREEN_W90X900 is not set
> -# CONFIG_INPUT_MISC is not set
> -
> -#
> -# Hardware I/O ports
> -#
> -CONFIG_SERIO=y
> -CONFIG_SERIO_SERPORT=y
> -# CONFIG_SERIO_RAW is not set
> -# CONFIG_SERIO_ALTERA_PS2 is not set
> -# CONFIG_GAMEPORT is not set
> -
> -#
> -# Character devices
> -#
> -CONFIG_VT=y
> -CONFIG_CONSOLE_TRANSLATIONS=y
> -CONFIG_VT_CONSOLE=y
> -CONFIG_HW_CONSOLE=y
> -# CONFIG_VT_HW_CONSOLE_BINDING is not set
> -CONFIG_DEVKMEM=y
> -# CONFIG_SERIAL_NONSTANDARD is not set
> -
> -#
> -# Serial drivers
> -#
> -CONFIG_SERIAL_8250=y
> -# CONFIG_SERIAL_8250_CONSOLE is not set
> -CONFIG_SERIAL_8250_NR_UARTS=4
> -CONFIG_SERIAL_8250_RUNTIME_UARTS=4
> -# CONFIG_SERIAL_8250_EXTENDED is not set
> -
> -#
> -# Non-8250 serial port support
> -#
> -CONFIG_SERIAL_SAMSUNG=y
> -CONFIG_SERIAL_SAMSUNG_UARTS_4=y
> -CONFIG_SERIAL_SAMSUNG_UARTS=4
> -# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
> -CONFIG_SERIAL_SAMSUNG_CONSOLE=y
> -CONFIG_SERIAL_S5PV210=y
> -CONFIG_SERIAL_CORE=y
> -CONFIG_SERIAL_CORE_CONSOLE=y
> -# CONFIG_SERIAL_TIMBERDALE is not set
> -# CONFIG_SERIAL_ALTERA_JTAGUART is not set
> -# CONFIG_SERIAL_ALTERA_UART is not set
> -CONFIG_UNIX98_PTYS=y
> -# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
> -CONFIG_LEGACY_PTYS=y
> -CONFIG_LEGACY_PTY_COUNT=256
> -# CONFIG_IPMI_HANDLER is not set
> -CONFIG_HW_RANDOM=y
> -# CONFIG_HW_RANDOM_TIMERIOMEM is not set
> -# CONFIG_R3964 is not set
> -# CONFIG_RAW_DRIVER is not set
> -# CONFIG_TCG_TPM is not set
> -# CONFIG_I2C is not set
> -# CONFIG_SPI is not set
> -
> -#
> -# PPS support
> -#
> -# CONFIG_PPS is not set
> -CONFIG_ARCH_REQUIRE_GPIOLIB=y
> -CONFIG_GPIOLIB=y
> -# CONFIG_DEBUG_GPIO is not set
> -# CONFIG_GPIO_SYSFS is not set
> -
> -#
> -# Memory mapped GPIO expanders:
> -#
> -# CONFIG_GPIO_IT8761E is not set
> -
> -#
> -# I2C GPIO expanders:
> -#
> -
> -#
> -# PCI GPIO expanders:
> -#
> -
> -#
> -# SPI GPIO expanders:
> -#
> -
> -#
> -# AC97 GPIO expanders:
> -#
> -# CONFIG_W1 is not set
> -# CONFIG_POWER_SUPPLY is not set
> -# CONFIG_HWMON is not set
> -# CONFIG_THERMAL is not set
> -# CONFIG_WATCHDOG is not set
> -CONFIG_HAVE_S3C2410_WATCHDOG=y
> -CONFIG_SSB_POSSIBLE=y
> -
> -#
> -# Sonics Silicon Backplane
> -#
> -# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> -# CONFIG_MFD_CORE is not set
> -# CONFIG_MFD_SM501 is not set
> -# CONFIG_MFD_ASIC3 is not set
> -# CONFIG_HTC_EGPIO is not set
> -# CONFIG_HTC_PASIC3 is not set
> -# CONFIG_MFD_TMIO is not set
> -# CONFIG_MFD_T7L66XB is not set
> -# CONFIG_MFD_TC6387XB is not set
> -# CONFIG_MFD_TC6393XB is not set
> -# CONFIG_REGULATOR is not set
> -# CONFIG_MEDIA_SUPPORT is not set
> -
> -#
> -# Graphics support
> -#
> -# CONFIG_VGASTATE is not set
> -# CONFIG_VIDEO_OUTPUT_CONTROL is not set
> -# CONFIG_FB is not set
> -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
> -
> -#
> -# Display device support
> -#
> -# CONFIG_DISPLAY_SUPPORT is not set
> -
> -#
> -# Console display driver support
> -#
> -# CONFIG_VGA_CONSOLE is not set
> -CONFIG_DUMMY_CONSOLE=y
> -# CONFIG_SOUND is not set
> -# CONFIG_HID_SUPPORT is not set
> -# CONFIG_USB_SUPPORT is not set
> -# CONFIG_MMC is not set
> -# CONFIG_MEMSTICK is not set
> -# CONFIG_NEW_LEDS is not set
> -# CONFIG_ACCESSIBILITY is not set
> -CONFIG_RTC_LIB=y
> -# CONFIG_RTC_CLASS is not set
> -# CONFIG_DMADEVICES is not set
> -# CONFIG_AUXDISPLAY is not set
> -# CONFIG_UIO is not set
> -# CONFIG_STAGING is not set
> -
> -#
> -# File systems
> -#
> -CONFIG_EXT2_FS=y
> -# CONFIG_EXT2_FS_XATTR is not set
> -# CONFIG_EXT2_FS_XIP is not set
> -# CONFIG_EXT3_FS is not set
> -# CONFIG_EXT4_FS is not set
> -# CONFIG_REISERFS_FS is not set
> -# CONFIG_JFS_FS is not set
> -CONFIG_FS_POSIX_ACL=y
> -# CONFIG_XFS_FS is not set
> -# CONFIG_GFS2_FS is not set
> -# CONFIG_BTRFS_FS is not set
> -# CONFIG_NILFS2_FS is not set
> -CONFIG_FILE_LOCKING=y
> -CONFIG_FSNOTIFY=y
> -CONFIG_DNOTIFY=y
> -CONFIG_INOTIFY=y
> -CONFIG_INOTIFY_USER=y
> -# CONFIG_QUOTA is not set
> -# CONFIG_AUTOFS_FS is not set
> -# CONFIG_AUTOFS4_FS is not set
> -# CONFIG_FUSE_FS is not set
> -CONFIG_GENERIC_ACL=y
> -
> -#
> -# Caches
> -#
> -# CONFIG_FSCACHE is not set
> -
> -#
> -# CD-ROM/DVD Filesystems
> -#
> -# CONFIG_ISO9660_FS is not set
> -# CONFIG_UDF_FS is not set
> -
> -#
> -# DOS/FAT/NT Filesystems
> -#
> -CONFIG_FAT_FS=y
> -CONFIG_MSDOS_FS=y
> -CONFIG_VFAT_FS=y
> -CONFIG_FAT_DEFAULT_CODEPAGE=437
> -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
> -# CONFIG_NTFS_FS is not set
> -
> -#
> -# Pseudo filesystems
> -#
> -CONFIG_PROC_FS=y
> -CONFIG_PROC_SYSCTL=y
> -CONFIG_PROC_PAGE_MONITOR=y
> -CONFIG_SYSFS=y
> -CONFIG_TMPFS=y
> -CONFIG_TMPFS_POSIX_ACL=y
> -# CONFIG_HUGETLB_PAGE is not set
> -# CONFIG_CONFIGFS_FS is not set
> -CONFIG_MISC_FILESYSTEMS=y
> -# CONFIG_ADFS_FS is not set
> -# CONFIG_AFFS_FS is not set
> -# CONFIG_HFS_FS is not set
> -# CONFIG_HFSPLUS_FS is not set
> -# CONFIG_BEFS_FS is not set
> -# CONFIG_BFS_FS is not set
> -# CONFIG_EFS_FS is not set
> -# CONFIG_LOGFS is not set
> -CONFIG_CRAMFS=y
> -# CONFIG_SQUASHFS is not set
> -# CONFIG_VXFS_FS is not set
> -# CONFIG_MINIX_FS is not set
> -# CONFIG_OMFS_FS is not set
> -# CONFIG_HPFS_FS is not set
> -# CONFIG_QNX4FS_FS is not set
> -CONFIG_ROMFS_FS=y
> -CONFIG_ROMFS_BACKED_BY_BLOCK=y
> -# CONFIG_ROMFS_BACKED_BY_MTD is not set
> -# CONFIG_ROMFS_BACKED_BY_BOTH is not set
> -CONFIG_ROMFS_ON_BLOCK=y
> -# CONFIG_SYSV_FS is not set
> -# CONFIG_UFS_FS is not set
> -
> -#
> -# Partition Types
> -#
> -CONFIG_PARTITION_ADVANCED=y
> -# CONFIG_ACORN_PARTITION is not set
> -# CONFIG_OSF_PARTITION is not set
> -# CONFIG_AMIGA_PARTITION is not set
> -# CONFIG_ATARI_PARTITION is not set
> -# CONFIG_MAC_PARTITION is not set
> -CONFIG_MSDOS_PARTITION=y
> -CONFIG_BSD_DISKLABEL=y
> -# CONFIG_MINIX_SUBPARTITION is not set
> -CONFIG_SOLARIS_X86_PARTITION=y
> -# CONFIG_UNIXWARE_DISKLABEL is not set
> -# CONFIG_LDM_PARTITION is not set
> -# CONFIG_SGI_PARTITION is not set
> -# CONFIG_ULTRIX_PARTITION is not set
> -# CONFIG_SUN_PARTITION is not set
> -# CONFIG_KARMA_PARTITION is not set
> -# CONFIG_EFI_PARTITION is not set
> -# CONFIG_SYSV68_PARTITION is not set
> -CONFIG_NLS=y
> -CONFIG_NLS_DEFAULT="iso8859-1"
> -CONFIG_NLS_CODEPAGE_437=y
> -# CONFIG_NLS_CODEPAGE_737 is not set
> -# CONFIG_NLS_CODEPAGE_775 is not set
> -# CONFIG_NLS_CODEPAGE_850 is not set
> -# CONFIG_NLS_CODEPAGE_852 is not set
> -# CONFIG_NLS_CODEPAGE_855 is not set
> -# CONFIG_NLS_CODEPAGE_857 is not set
> -# CONFIG_NLS_CODEPAGE_860 is not set
> -# CONFIG_NLS_CODEPAGE_861 is not set
> -# CONFIG_NLS_CODEPAGE_862 is not set
> -# CONFIG_NLS_CODEPAGE_863 is not set
> -# CONFIG_NLS_CODEPAGE_864 is not set
> -# CONFIG_NLS_CODEPAGE_865 is not set
> -# CONFIG_NLS_CODEPAGE_866 is not set
> -# CONFIG_NLS_CODEPAGE_869 is not set
> -# CONFIG_NLS_CODEPAGE_936 is not set
> -# CONFIG_NLS_CODEPAGE_950 is not set
> -# CONFIG_NLS_CODEPAGE_932 is not set
> -# CONFIG_NLS_CODEPAGE_949 is not set
> -# CONFIG_NLS_CODEPAGE_874 is not set
> -# CONFIG_NLS_ISO8859_8 is not set
> -# CONFIG_NLS_CODEPAGE_1250 is not set
> -# CONFIG_NLS_CODEPAGE_1251 is not set
> -CONFIG_NLS_ASCII=y
> -CONFIG_NLS_ISO8859_1=y
> -# CONFIG_NLS_ISO8859_2 is not set
> -# CONFIG_NLS_ISO8859_3 is not set
> -# CONFIG_NLS_ISO8859_4 is not set
> -# CONFIG_NLS_ISO8859_5 is not set
> -# CONFIG_NLS_ISO8859_6 is not set
> -# CONFIG_NLS_ISO8859_7 is not set
> -# CONFIG_NLS_ISO8859_9 is not set
> -# CONFIG_NLS_ISO8859_13 is not set
> -# CONFIG_NLS_ISO8859_14 is not set
> -# CONFIG_NLS_ISO8859_15 is not set
> -# CONFIG_NLS_KOI8_R is not set
> -# CONFIG_NLS_KOI8_U is not set
> -# CONFIG_NLS_UTF8 is not set
> -
> -#
> -# Kernel hacking
> -#
> -# CONFIG_PRINTK_TIME is not set
> -CONFIG_ENABLE_WARN_DEPRECATED=y
> -CONFIG_ENABLE_MUST_CHECK=y
> -CONFIG_FRAME_WARN=1024
> -CONFIG_MAGIC_SYSRQ=y
> -# CONFIG_STRIP_ASM_SYMS is not set
> -# CONFIG_UNUSED_SYMBOLS is not set
> -# CONFIG_DEBUG_FS is not set
> -# CONFIG_HEADERS_CHECK is not set
> -CONFIG_DEBUG_KERNEL=y
> -# CONFIG_DEBUG_SHIRQ is not set
> -CONFIG_DETECT_SOFTLOCKUP=y
> -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
> -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
> -CONFIG_DETECT_HUNG_TASK=y
> -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
> -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
> -CONFIG_SCHED_DEBUG=y
> -# CONFIG_SCHEDSTATS is not set
> -# CONFIG_TIMER_STATS is not set
> -# CONFIG_DEBUG_OBJECTS is not set
> -# CONFIG_SLUB_DEBUG_ON is not set
> -# CONFIG_SLUB_STATS is not set
> -# CONFIG_DEBUG_KMEMLEAK is not set
> -# CONFIG_DEBUG_PREEMPT is not set
> -CONFIG_DEBUG_RT_MUTEXES=y
> -CONFIG_DEBUG_PI_LIST=y
> -# CONFIG_RT_MUTEX_TESTER is not set
> -CONFIG_DEBUG_SPINLOCK=y
> -CONFIG_DEBUG_MUTEXES=y
> -# CONFIG_DEBUG_LOCK_ALLOC is not set
> -# CONFIG_PROVE_LOCKING is not set
> -# CONFIG_LOCK_STAT is not set
> -CONFIG_DEBUG_SPINLOCK_SLEEP=y
> -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
> -# CONFIG_DEBUG_KOBJECT is not set
> -CONFIG_DEBUG_BUGVERBOSE=y
> -CONFIG_DEBUG_INFO=y
> -# CONFIG_DEBUG_VM is not set
> -# CONFIG_DEBUG_WRITECOUNT is not set
> -CONFIG_DEBUG_MEMORY_INIT=y
> -# CONFIG_DEBUG_LIST is not set
> -# CONFIG_DEBUG_SG is not set
> -# CONFIG_DEBUG_NOTIFIERS is not set
> -# CONFIG_DEBUG_CREDENTIALS is not set
> -# CONFIG_BOOT_PRINTK_DELAY is not set
> -# CONFIG_RCU_TORTURE_TEST is not set
> -# CONFIG_RCU_CPU_STALL_DETECTOR is not set
> -# CONFIG_BACKTRACE_SELF_TEST is not set
> -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
> -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
> -# CONFIG_FAULT_INJECTION is not set
> -# CONFIG_LATENCYTOP is not set
> -CONFIG_SYSCTL_SYSCALL_CHECK=y
> -# CONFIG_PAGE_POISONING is not set
> -CONFIG_HAVE_FUNCTION_TRACER=y
> -CONFIG_TRACING_SUPPORT=y
> -CONFIG_FTRACE=y
> -# CONFIG_FUNCTION_TRACER is not set
> -# CONFIG_IRQSOFF_TRACER is not set
> -# CONFIG_PREEMPT_TRACER is not set
> -# CONFIG_SCHED_TRACER is not set
> -# CONFIG_ENABLE_DEFAULT_TRACERS is not set
> -# CONFIG_BOOT_TRACER is not set
> -CONFIG_BRANCH_PROFILE_NONE=y
> -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
> -# CONFIG_PROFILE_ALL_BRANCHES is not set
> -# CONFIG_STACK_TRACER is not set
> -# CONFIG_KMEMTRACE is not set
> -# CONFIG_WORKQUEUE_TRACER is not set
> -# CONFIG_BLK_DEV_IO_TRACE is not set
> -# CONFIG_ATOMIC64_SELFTEST is not set
> -# CONFIG_SAMPLES is not set
> -CONFIG_HAVE_ARCH_KGDB=y
> -# CONFIG_KGDB is not set
> -CONFIG_ARM_UNWIND=y
> -CONFIG_DEBUG_USER=y
> -CONFIG_DEBUG_ERRORS=y
> -# CONFIG_DEBUG_STACK_USAGE is not set
> -CONFIG_DEBUG_LL=y
> -CONFIG_EARLY_PRINTK=y
> -# CONFIG_DEBUG_ICEDCC is not set
> -# CONFIG_OC_ETM is not set
> -CONFIG_DEBUG_S3C_UART=1
> -
> -#
> -# Security options
> -#
> -# CONFIG_KEYS is not set
> -# CONFIG_SECURITY is not set
> -# CONFIG_SECURITYFS is not set
> -# CONFIG_DEFAULT_SECURITY_SELINUX is not set
> -# CONFIG_DEFAULT_SECURITY_SMACK is not set
> -# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
> -CONFIG_DEFAULT_SECURITY_DAC=y
> -CONFIG_DEFAULT_SECURITY=""
> -# CONFIG_CRYPTO is not set
> -# CONFIG_BINARY_PRINTF is not set
> -
> -#
> -# Library routines
> -#
> -CONFIG_BITREVERSE=y
> -CONFIG_GENERIC_FIND_LAST_BIT=y
> -CONFIG_CRC_CCITT=y
> -# CONFIG_CRC16 is not set
> -# CONFIG_CRC_T10DIF is not set
> -# CONFIG_CRC_ITU_T is not set
> -CONFIG_CRC32=y
> -# CONFIG_CRC7 is not set
> -# CONFIG_LIBCRC32C is not set
> -CONFIG_ZLIB_INFLATE=y
> -CONFIG_LZO_DECOMPRESS=y
> -CONFIG_DECOMPRESS_GZIP=y
> -CONFIG_DECOMPRESS_BZIP2=y
> -CONFIG_DECOMPRESS_LZMA=y
> -CONFIG_DECOMPRESS_LZO=y
> -CONFIG_HAS_IOMEM=y
> -CONFIG_HAS_DMA=y
> diff --git a/arch/arm/configs/s5pv210_defconfig b/arch/arm/configs/s5pv210_defconfig
> index e2f5bce..5d447c1 100644
> --- a/arch/arm/configs/s5pv210_defconfig
> +++ b/arch/arm/configs/s5pv210_defconfig
> @@ -1,7 +1,7 @@
> ?#
> ?# Automatically generated make config: don't edit
> -# Linux kernel version: 2.6.34
> -# Wed May 26 19:04:39 2010
> +# Linux kernel version: 2.6.35-rc3
> +# Wed Jun 16 08:03:01 2010
> ?#
> ?CONFIG_ARM=y
> ?CONFIG_SYS_SUPPORTS_APM_EMULATION=y
> @@ -34,6 +34,7 @@ CONFIG_EXPERIMENTAL=y
> ?CONFIG_BROKEN_ON_SMP=y
> ?CONFIG_LOCK_KERNEL=y
> ?CONFIG_INIT_ENV_ARG_LIMIT=32
> +CONFIG_CROSS_COMPILE=""
> ?CONFIG_LOCALVERSION=""
> ?CONFIG_LOCALVERSION_AUTO=y
> ?CONFIG_HAVE_KERNEL_GZIP=y
> @@ -253,6 +254,7 @@ CONFIG_SAMSUNG_GPIO_EXTRA=0
> ?CONFIG_S3C_GPIO_SPACE=0
> ?CONFIG_S3C_GPIO_TRACK=y
> ?# CONFIG_S3C_ADC is not set
> +CONFIG_S3C_DEV_FB=y
> ?CONFIG_S3C_DEV_WDT=y
> ?CONFIG_SAMSUNG_DEV_ADC=y
> ?CONFIG_SAMSUNG_DEV_TS=y
> @@ -264,10 +266,19 @@ CONFIG_S3C_PL330_DMA=y
> ?CONFIG_PLAT_S5P=y
> ?CONFIG_S5P_EXT_INT=y
> ?CONFIG_CPU_S5PV210=y
> -# CONFIG_MACH_AQUILA is not set
> +CONFIG_S5PV210_SETUP_FB_24BPP=y
> +
> +#
> +# S5PC110 Machines
> +#
> +CONFIG_MACH_AQUILA=y
> ?# CONFIG_MACH_GONI is not set
> +CONFIG_MACH_SMDKC110=y
> +
> +#
> +# S5PV210 Machines
> +#
> ?CONFIG_MACH_SMDKV210=y
> -# CONFIG_MACH_SMDKC110 is not set
>
> ?#
> ?# Processor Type
> @@ -567,6 +578,7 @@ CONFIG_HW_RANDOM=y
> ?# CONFIG_R3964 is not set
> ?# CONFIG_RAW_DRIVER is not set
> ?# CONFIG_TCG_TPM is not set
> +# CONFIG_RAMOOPS is not set
> ?# CONFIG_I2C is not set
> ?# CONFIG_SPI is not set
>
> @@ -599,6 +611,10 @@ CONFIG_GPIOLIB=y
> ?#
> ?# AC97 GPIO expanders:
> ?#
> +
> +#
> +# MODULbus GPIO expanders:
> +#
> ?# CONFIG_W1 is not set
> ?# CONFIG_POWER_SUPPLY is not set
> ?# CONFIG_HWMON is not set
> @@ -611,10 +627,7 @@ CONFIG_SSB_POSSIBLE=y
> ?# Sonics Silicon Backplane
> ?#
> ?# CONFIG_SSB is not set
> -
> -#
> -# Multifunction device drivers
> -#
> +CONFIG_MFD_SUPPORT=y
> ?# CONFIG_MFD_CORE is not set
> ?# CONFIG_MFD_SM501 is not set
> ?# CONFIG_MFD_ASIC3 is not set
> @@ -624,6 +637,7 @@ CONFIG_SSB_POSSIBLE=y
> ?# CONFIG_MFD_T7L66XB is not set
> ?# CONFIG_MFD_TC6387XB is not set
> ?# CONFIG_MFD_TC6393XB is not set
> +# CONFIG_ABX500_CORE is not set
> ?# CONFIG_REGULATOR is not set
> ?# CONFIG_MEDIA_SUPPORT is not set
>
> diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
> index 0761eac..8150480 100644
> --- a/arch/arm/mach-s5pv210/Kconfig
> +++ b/arch/arm/mach-s5pv210/Kconfig
> @@ -43,10 +43,10 @@ config S5PV210_SETUP_SDHCI_GPIO
> ? ? ? ?help
> ? ? ? ? ?Common setup code for SDHCI gpio.
>
> -# machine support
> +menu "S5PC110 Machines"
>
> ?config MACH_AQUILA
> - ? ? ? bool "Samsung Aquila"
> + ? ? ? bool "Aquila"
> ? ? ? ?select CPU_S5PV210
> ? ? ? ?select ARCH_SPARSEMEM_ENABLE
> ? ? ? ?select S5PV210_SETUP_FB_24BPP
> @@ -62,11 +62,25 @@ config MACH_GONI
> ? ? ? ? ?Machine support for Samsung GONI board
> ? ? ? ? ?S5PC110(MCP) is one of package option of S5PV210
>
> +config MACH_SMDKC110
> + ? ? ? bool "SMDKC110"
> + ? ? ? select CPU_S5PV210
> + ? ? ? select ARCH_SPARSEMEM_ENABLE
> + ? ? ? select S3C_DEV_WDT
> + ? ? ? select HAVE_S3C2410_WATCHDOG
> + ? ? ? help
> + ? ? ? ? Machine support for Samsung SMDKC110
> + ? ? ? ? S5PC110(MCP) is one of package option of S5PV210
> +
> +endmenu
> +
> ?config S5PC110_DEV_ONENAND
> ? ? ? ?bool
> ? ? ? ?help
> ? ? ? ? ?Compile in platform device definition for OneNAND1 controller
>
> +menu "S5PV210 Machines"
> +
> ?config MACH_SMDKV210
> ? ? ? ?bool "SMDKV210"
> ? ? ? ?select CPU_S5PV210
> @@ -78,14 +92,6 @@ config MACH_SMDKV210
> ? ? ? ?help
> ? ? ? ? ?Machine support for Samsung SMDKV210
>
> -config MACH_SMDKC110
> - ? ? ? bool "SMDKC110"
> - ? ? ? select CPU_S5PV210
> - ? ? ? select ARCH_SPARSEMEM_ENABLE
> - ? ? ? select S3C_DEV_WDT
> - ? ? ? select HAVE_S3C2410_WATCHDOG
> - ? ? ? help
> - ? ? ? ? Machine support for Samsung SMDKC110
> - ? ? ? ? S5PC110(MCP) is one of package option of S5PV210
> +endmenu
>
> ?endif
> --
> 1.6.2.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>


From w.sang at pengutronix.de  Tue Jun 15 21:44:58 2010
From: w.sang at pengutronix.de (Wolfram Sang)
Date: Wed, 16 Jun 2010 03:44:58 +0200
Subject: [PATCH 2/2] ehci-mxc: bail out on transceiver problems
In-Reply-To: <20100615104342.GE17833@buzzloop.caiaq.de>
References: <1276598063-3956-1-git-send-email-w.sang@pengutronix.de>
	<1276598063-3956-2-git-send-email-w.sang@pengutronix.de>
	<20100615104342.GE17833@buzzloop.caiaq.de>
Message-ID: <20100616014458.GA30484@pengutronix.de>

On Tue, Jun 15, 2010 at 12:43:42PM +0200, Daniel Mack wrote:
> On Tue, Jun 15, 2010 at 12:34:23PM +0200, Wolfram Sang wrote:
> > The old code registered the hcd even if there were no transceivers
> > detected, leading to oopses like this if we try to probe a non-existant
> > ULPI:
> 
> Hmm. I'm aware that there was a missing bail in this function, but
> actually, I had hardware which didn't properly detect the ULPI chip but
> still worked fine. There has been quite some discussion here about that,
> and eventually I decided to not make this a hard error as it didn't
> really harm.

Hmm, so, do you think this patch is stable-material after all?

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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From eric.y.miao at gmail.com  Tue Jun 15 22:17:07 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 16 Jun 2010 10:17:07 +0800
Subject: [PATCH] MAINTAINERS: Change BCMRING maintainer
In-Reply-To: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E3F7@SJEXCHCCR02.corp.ad.broadcom.com>
References: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E3F7@SJEXCHCCR02.corp.ad.broadcom.com>
Message-ID: <AANLkTil6o6tHQdDM0YQRgxme3VLVuk8HUOzqscxsBQBi@mail.gmail.com>

On Wed, Jun 16, 2010 at 4:42 AM, JD (Jiandong) Zheng
<jdzheng at broadcom.com> wrote:
> Hello,
>
> I am Jiandong Zheng working on BCMRING in Broadcom Canada Ltd. I am replacing Leo Chen (leochen at broadcom.com) as " ARM/BCMRING ARM ARCHITECTURE" and "ARM/BCMRING MTD NAND DRIVER" maintainer.
>
> Here is the patch to MAINTAINERS file in linux 2.6.34 about this change.
>
> Signed-off-by: Jiandong Zheng <jdzheng at broadcom.com>

Search your email address in linux-2.6 tree, no result found. This is
community, not a company. Maintainer is not assigned. Show us some
credits please?

>
> diff -urN linux-2.6.34/MAINTAINERS.orig linux-2.6.34/MAINTAINERS
> --- linux-2.6.34/MAINTAINERS.orig ? ? ? 2010-06-15 11:59:53.202128994 -0700
> +++ linux-2.6.34/MAINTAINERS ? ?2010-06-15 12:01:59.862277620 -0700
> @@ -570,14 +570,14 @@
> ?S: ? ? Maintained
>
> ?ARM/BCMRING ARM ARCHITECTURE
> -M: ? ? Leo Chen <leochen at broadcom.com>
> +M: ? ? Jiandong Zheng <jdzheng at broadcom.com>
> ?M: ? ? Scott Branden <sbranden at broadcom.com>
> ?L: ? ? linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
> ?S: ? ? Maintained
> ?F: ? ? arch/arm/mach-bcmring
>
> ?ARM/BCMRING MTD NAND DRIVER
> -M: ? ? Leo Chen <leochen at broadcom.com>
> +M: ? ? Jiandong Zheng <jdzheng at broadcom.com>
> ?M: ? ? Scott Branden <sbranden at broadcom.com>
> ?L: ? ? linux-mtd at lists.infradead.org
> ?S: ? ? Maintained
>
>
> Thanks,
>
> Jiandong Zheng
> Senior Staff Software Engineer
> Broadcom Canada Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From jy0922.shim at samsung.com  Tue Jun 15 22:21:18 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Wed, 16 Jun 2010 11:21:18 +0900
Subject: [PATCH v4 2/3] ARM: S5PV210: Add keypad device helpers
In-Reply-To: <007801cb0b81$16cc0ff0$44642fd0$%kim@samsung.com>
References: <1276243728-17704-1-git-send-email-jy0922.shim@samsung.com>
	<1276243728-17704-2-git-send-email-jy0922.shim@samsung.com>
	<007801cb0b81$16cc0ff0$44642fd0$%kim@samsung.com>
Message-ID: <4C18351E.2080805@samsung.com>

On 6/14/2010 2:18 PM, Kukjin Kim wrote:
> Joonyoung Shim wrote:
>> This patch adds the keypad device platform helpers for S5PV210 cpu.
>>
>> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>> ---
>>  arch/arm/mach-s5pv210/Kconfig            |    5 ++++
>>  arch/arm/mach-s5pv210/Makefile           |    1 +
>>  arch/arm/mach-s5pv210/cpu.c              |    4 +++
>>  arch/arm/mach-s5pv210/include/mach/map.h |    3 ++
>>  arch/arm/mach-s5pv210/setup-keypad.c     |   34
>> ++++++++++++++++++++++++++++++
>>  5 files changed, 47 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/mach-s5pv210/setup-keypad.c
>>
>> diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
>> index 0761eac..692d01c 100644
>> --- a/arch/arm/mach-s5pv210/Kconfig
>> +++ b/arch/arm/mach-s5pv210/Kconfig
>> @@ -32,6 +32,11 @@ config S5PV210_SETUP_FB_24BPP
>>  	help
>>            Common setup code for S5PV210 with an 24bpp RGB display helper.
>>
>> +config S5PV210_SETUP_KEYPAD
>> +	bool
>> +	help
>> +	  Common setup code for keypad.
>> +
>>  config S5PV210_SETUP_SDHCI
>>          bool
>>          select S5PV210_SETUP_SDHCI_GPIO
>> diff --git a/arch/arm/mach-s5pv210/Makefile
> b/arch/arm/mach-s5pv210/Makefile
>> index 30be9a6..aae592a 100644
>> --- a/arch/arm/mach-s5pv210/Makefile
>> +++ b/arch/arm/mach-s5pv210/Makefile
>> @@ -31,5 +31,6 @@ obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o
>>  obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
>>  obj-$(CONFIG_S5PV210_SETUP_I2C1) 	+= setup-i2c1.o
>>  obj-$(CONFIG_S5PV210_SETUP_I2C2) 	+= setup-i2c2.o
>> +obj-$(CONFIG_S5PV210_SETUP_KEYPAD)	+= setup-keypad.o
>>  obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
>>  obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
>> diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
>> index 411a4a9..a3034ac 100644
>> --- a/arch/arm/mach-s5pv210/cpu.c
>> +++ b/arch/arm/mach-s5pv210/cpu.c
>> @@ -80,6 +80,10 @@ void __init s5pv210_map_io(void)
>>  	s3c_device_adc.name	= "s3c64xx-adc";
>>  #endif
>>
>> +#ifdef CONFIG_SAMSUNG_DEV_KEYPAD
>> +	samsung_device_keypad.name = "s5pv210-keypad";
>> +#endif
>> +
> 
> Please use one method. See Kyungmin Park's prev. comments on the subject.
> 

I cannot understand this comment meaning and where is Kyungmin's
comments? Please let me know detailed thing.

>>  	iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
>>
>>  	/* initialise device information early */
>> diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-
>> s5pv210/include/mach/map.h
>> index 34eb168..e2f6e2a 100644
>> --- a/arch/arm/mach-s5pv210/include/mach/map.h
>> +++ b/arch/arm/mach-s5pv210/include/mach/map.h
>> @@ -32,6 +32,8 @@
>>  #define S5PV210_PA_SPI0		0xE1300000
>>  #define S5PV210_PA_SPI1		0xE1400000
>>
>> +#define S5PV210_PA_KEYPAD	(0xE1600000)
>> +
>>  #define S5PV210_PA_IIC0		(0xE1800000)
>>  #define S5PV210_PA_IIC1		(0xFAB00000)
>>  #define S5PV210_PA_IIC2		(0xE1A00000)
>> @@ -104,5 +106,6 @@
>>  #define S3C_PA_WDT		S5PV210_PA_WATCHDOG
>>
>>  #define SAMSUNG_PA_ADC		S5PV210_PA_ADC
>> +#define SAMSUNG_PA_KEYPAD	S5PV210_PA_KEYPAD
>>
>>  #endif /* __ASM_ARCH_MAP_H */
>> diff --git a/arch/arm/mach-s5pv210/setup-keypad.c
> b/arch/arm/mach-s5pv210/setup-
>> keypad.c
>> new file mode 100644
>> index 0000000..f51bf8d
>> --- /dev/null
>> +++ b/arch/arm/mach-s5pv210/setup-keypad.c
>> @@ -0,0 +1,34 @@
>> +/*
>> + * linux/arch/arm/mach-s5pv210/setup-keypad.c
>> + *
>> + * Copyright (C) 2010 Samsung Electronics Co.Ltd
>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>> + *
>> + *  This program is free software; you can redistribute  it and/or modify
> it
>> + *  under  the terms of  the GNU General  Public License as published by
> the
>> + *  Free Software Foundation;  either version 2 of the  License, or (at
> your
>> + *  option) any later version.
>> + *
>> + */
>> +
>> +#include <linux/gpio.h>
>> +#include <plat/gpio-cfg.h>
>> +
>> +void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
>> +{
>> +	unsigned int gpio, end;
>> +
>> +	/* Set all the necessary GPH3 pins to special-function 3 */
> 
> What's the special-function 3?

I refered s3c_gpio_cfgpin() comments of
arch/arm/plat-samsung/include/plat/gpio-cfg.h

I think this is enough comments but if you want more specific comments
still, i can add it.

Thanks.

> How about 'special function KP_ROWs'?
> 
>> +	end = S5PV210_GPH3(rows);
>> +	for (gpio = S5PV210_GPH3(0); gpio < end; gpio++) {
>> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
>> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
>> +	}
>> +
>> +	/* Set all the necessary GPH2 pins to special-function 3 */
> 
> How about 'special function KP_COLs'?
> 
>> +	end = S5PV210_GPH2(cols);
>> +	for (gpio = S5PV210_GPH2(0); gpio < end; gpio++) {
>> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
>> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
>> +	}
>> +}
>> --
> 
> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> 
> 



From joe at perches.com  Tue Jun 15 22:39:41 2010
From: joe at perches.com (Joe Perches)
Date: Tue, 15 Jun 2010 19:39:41 -0700
Subject: [PATCH] MAINTAINERS: Change BCMRING maintainer
In-Reply-To: <AANLkTil6o6tHQdDM0YQRgxme3VLVuk8HUOzqscxsBQBi@mail.gmail.com>
References: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E3F7@SJEXCHCCR02.corp.ad.broadcom.com>
	<AANLkTil6o6tHQdDM0YQRgxme3VLVuk8HUOzqscxsBQBi@mail.gmail.com>
Message-ID: <1276655981.1586.172.camel@Joe-Laptop.home>

On Wed, 2010-06-16 at 10:17 +0800, Eric Miao wrote:
> On Wed, Jun 16, 2010 at 4:42 AM, JD (Jiandong) Zheng
> <jdzheng at broadcom.com> wrote:
> > I am Jiandong Zheng working on BCMRING in Broadcom Canada Ltd.
> > I am replacing Leo Chen (leochen at broadcom.com) as
> > "ARM/BCMRING ARM ARCHITECTURE" and "ARM/BCMRING MTD NAND DRIVER"
> >  maintainer.
> > Signed-off-by: Jiandong Zheng <jdzheng at broadcom.com>
> Search your email address in linux-2.6 tree, no result found. This is
> community, not a company. Maintainer is not assigned. Show us some
> credits please?

I think you're going overboard Eric.
You'll find several company addresses, some with names, in MAINTAINERS.

for instance:
$ grep M:.*support MAINTAINERS 
M:	support at lsi.com
M:	Vincent Sanders <support at simtec.co.uk>
M:	Vincent Sanders <support at simtec.co.uk>
M:	Matthias Bruestle and Harald Welte <support at reiner-sct.com>
M:	Support Department <support at connecttech.com>

Some others:
M:	STEricsson <STEricsson_nomadik_linux at list.st.com>
M:	"Digi International, Inc" <Eng.Linux at digi.com>
M:	HighPoint Linux Team <linux at highpoint-tech.com>
M:	Intel Linux Wireless <ilw at linux.intel.com>
M:	linux-wimax at intel.com
M:	linux390 at de.ibm.com
M:	linux-driver at qlogic.com
M:	Solarflare linux maintainers <linux-net-drivers at solarflare.com>
M:	davinci-linux-open-source at linux.davincidsp.com

Would you prefer that broadcom go the way of intel with the
ipw2x00 or just have a faceless "linux-support at broadcom.com"?

Not me.

Welcome JD.




From eric.y.miao at gmail.com  Tue Jun 15 22:58:23 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 16 Jun 2010 10:58:23 +0800
Subject: [PATCH] MAINTAINERS: Change BCMRING maintainer
In-Reply-To: <1276655981.1586.172.camel@Joe-Laptop.home>
References: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E3F7@SJEXCHCCR02.corp.ad.broadcom.com>
	<AANLkTil6o6tHQdDM0YQRgxme3VLVuk8HUOzqscxsBQBi@mail.gmail.com> 
	<1276655981.1586.172.camel@Joe-Laptop.home>
Message-ID: <AANLkTilI2toj42vZcHzPC4ru82CDMf2UWsTasPyOD3Nh@mail.gmail.com>

On Wed, Jun 16, 2010 at 10:39 AM, Joe Perches <joe at perches.com> wrote:
> On Wed, 2010-06-16 at 10:17 +0800, Eric Miao wrote:
>> On Wed, Jun 16, 2010 at 4:42 AM, JD (Jiandong) Zheng
>> <jdzheng at broadcom.com> wrote:
>> > I am Jiandong Zheng working on BCMRING in Broadcom Canada Ltd.
>> > I am replacing Leo Chen (leochen at broadcom.com) as
>> > "ARM/BCMRING ARM ARCHITECTURE" and "ARM/BCMRING MTD NAND DRIVER"
>> > ?maintainer.
>> > Signed-off-by: Jiandong Zheng <jdzheng at broadcom.com>
>> Search your email address in linux-2.6 tree, no result found. This is
>> community, not a company. Maintainer is not assigned. Show us some
>> credits please?
>
> I think you're going overboard Eric.
> You'll find several company addresses, some with names, in MAINTAINERS.

Well, I'm not against a company address at all, I myself am employed and
use company address very often. And I really welcome some one to come up
and take the responsibility of some orphaned code. But the first impression
of this, to me, it's more like a Broadcom internal policy to assign someone
or not (maybe some work transition of Leo Chen). And I haven't seen much
contribution from JD so far, honestly, (but doesn't mean I don't believe
he's going to contribute a lot).

Sorry, JD, I was a bit rude on this and this is not personal at all. Nice to
know you actually, bcmring was not actively maintained since last year.
I hope we can know more about you.

>
> for instance:
> $ grep M:.*support MAINTAINERS
> M: ? ? ?support at lsi.com
> M: ? ? ?Vincent Sanders <support at simtec.co.uk>
> M: ? ? ?Vincent Sanders <support at simtec.co.uk>
> M: ? ? ?Matthias Bruestle and Harald Welte <support at reiner-sct.com>
> M: ? ? ?Support Department <support at connecttech.com>
>
> Some others:
> M: ? ? ?STEricsson <STEricsson_nomadik_linux at list.st.com>
> M: ? ? ?"Digi International, Inc" <Eng.Linux at digi.com>
> M: ? ? ?HighPoint Linux Team <linux at highpoint-tech.com>
> M: ? ? ?Intel Linux Wireless <ilw at linux.intel.com>
> M: ? ? ?linux-wimax at intel.com
> M: ? ? ?linux390 at de.ibm.com
> M: ? ? ?linux-driver at qlogic.com
> M: ? ? ?Solarflare linux maintainers <linux-net-drivers at solarflare.com>
> M: ? ? ?davinci-linux-open-source at linux.davincidsp.com
>
> Would you prefer that broadcom go the way of intel with the
> ipw2x00 or just have a faceless "linux-support at broadcom.com"?
>
> Not me.
>
> Welcome JD.
>
>
>


From eric.miao at canonical.com  Tue Jun 15 23:16:43 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Wed, 16 Jun 2010 11:16:43 +0800
Subject: [PATCH 02/10] arm/zImage: some comments for __armv3_mpu_cache_on
In-Reply-To: <1276165636-20150-2-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-2-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <AANLkTiluJns87Cc7Xk4VA-_9nXMNuhfcR2Kwu0A0IevK@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> __armv3_mpu_cache_on seems broken. ?As there is noone around who knows
> about these machines just keep the code as is but point out the strange
> things.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
> ?arch/arm/boot/compressed/head.S | ? ?3 +++
> ?1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index 390aa92..384150b 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -396,12 +396,15 @@ __armv3_mpu_cache_on:
>
> ? ? ? ? ? ? ? ?mov ? ? r0, #0
> ? ? ? ? ? ? ? ?mcr ? ? p15, 0, r0, c7, c0, 0 ? @ invalidate whole cache v3
> + ? ? ? ? ? ? ? /* ?? ARMv3 MMU doesn not allow reading the control register, does this really work on ARMv3 MPU? */


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.1.1276658227.27306.linux-arm-kernel@lists.infradead.org>

http://en.wikipedia.org/wiki/ARM_architecture

ARM740T is actually V4T, and reading of control register should be OK.
Although I guess due to historic reason, it's using armv3_* prefix for
the functions?

> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mrc =C2=A0 =C2=A0 =
p15, 0, r0, c1, c0, 0 =C2=A0 @ read control reg
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0@ .... .... .... WC.M
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0orr =C2=A0 =C2=A0 =
r0, r0, #0x000d =C2=A0 =C2=A0 =C2=A0 =C2=A0 @ .... .... .... 11.1
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* ?? this overwrites =
the value constructed above? */
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mov =C2=A0 =C2=A0 =
r0, #0

This does seem to be an error.

> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mcr =C2=A0 =C2=A0 =
p15, 0, r0, c1, c0, 0 =C2=A0 @ write control reg
>
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* ?? invalidate for t=
he second time? */
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mcr =C2=A0 =C2=A0 =
p15, 0, r0, c7, c0, 0 =C2=A0 @ invalidate whole cache v3
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mov =C2=A0 =C2=A0 =
pc, lr
>
> --
> 1.7.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From eric.y.miao at gmail.com  Tue Jun 15 23:43:29 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 16 Jun 2010 11:43:29 +0800
Subject: [PATCH] ARM: Add ARCH_HAS_L2X0 and make CACHE_L2X0 config depend 
	on that
In-Reply-To: <20100614145956.GA29355@lixom.net>
References: <1276272211-13065-1-git-send-email-olof@lixom.net> 
	<1276279087.31800.6.camel@c-dwalke-linux.qualcomm.com>
	<20100613051625.GA7248@trinity.fluff.org> 
	<20100614145956.GA29355@lixom.net>
Message-ID: <AANLkTimH979ASCut4dEE0FGJ-3PA3jzfHg_SzVM6eor_@mail.gmail.com>

On Mon, Jun 14, 2010 at 10:59 PM, Olof Johansson <olof at lixom.net> wrote:
> On Sun, Jun 13, 2010 at 06:16:26AM +0100, Ben Dooks wrote:
>> On Fri, Jun 11, 2010 at 10:58:07AM -0700, Daniel Walker wrote:
>> >
>> > I made a similar change not too long ago, but Russell wanted the define
>> > to be HAVE_CACHE_L2X0 ..
>>
>> possibly, I was thinking ARM_L2X0 would also be an option, since if I
>> remeber correctly it is selecting the driver not the availability of
>> it.
>
> Yeah, there are lots of different possible names. :)
>
> Let's just go with the one Russell preferred and not worry too much
> about it. There's some presendence to using HAVE_.* already.
>

Sometimes I am thinking that maybe ARCH_HAS_* has some benefits:

HAVE_* for those kernel-wide and general capabilities
ARCH_HAS_* for those ARM machine-class specific capabilities?

So to make things a bit more clear? If ARCH_HAS_* is widely adopted
on architectures other than ARM, maybe we can then switch that name
to HAVE_*?


From viresh.kumar at st.com  Tue Jun 15 23:59:24 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Wed, 16 Jun 2010 09:29:24 +0530
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 PrimeCells
In-Reply-To: <CEE6BB42CAD6E947908279175AF8470A025E5AE1ED@EXDCVYMBSTM006.EQ1STM.local>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>	<4C15C60E.6080404@st.com>
	<AANLkTim9n-p-Pw6FWvzQMBiAuB3h9ILq1Ya6XWk_0l-c@mail.gmail.com>
	<4C170EE2.4010706@st.com>
	<CEE6BB42CAD6E947908279175AF8470A025E5AE1ED@EXDCVYMBSTM006.EQ1STM.local>
Message-ID: <4C184C1C.4000204@st.com>

On 6/16/2010 1:44 AM, Linus WALLEIJ wrote:
> [Viresh]
> 
>> On 6/14/2010 7:09 PM, Linus Walleij wrote:
>> I have few more doubts that i wanted to ask. Are following supported in
>> your
>> driver, we need them in SPEAr:
>>  - Configure burst size of source or destination.
> 
> The PrimeCell extension supports this, do you need that in things
> that are not PrimeCells? In that case we need to make them generic.
> 
>>  - Configure DMA Master for src or dest.
> 
> Right now I have an algorithm that will (on the PL080, the PL081
> has only one master) try to select AHB1 for the memory and AHB2

PL080 have 2 Masters.

> for the device by checking if one address is fixed. If both or
> none addresses are fixed it will simply select AHB1 for source
> and AHB2 for destination.
> 
> Please elaborate on what algorithm you need for this!

In the same way, how other peripheral related data is passed to DMA driver,
(like request lines), we can also pass configuration and control information.
This will provide us with all features requested by me, as most of the
control will be from user only. In SPEAr6xx, Memory is accessible from Master1
only but in SPEAr3xx only from Master 2, similar is the pattern with few 
peripherals also and so i need control over DMA channel configuration.

>>  - Configure Flow controller of transfer.
> 
> Currently only done dynamically with DMA as the master for
> Mem2mem, mem2per and per2mem. Mastering from the peripherals
> is not supported. Do you have advanced features like that?

We have JPEG controller, which acts as a flow controller for JPEG to
mem transfer. (Synopsys JPEG Controller).

> 
> Anyway it can be passed in from platform data easily.
> 

But platform data will be passed one time only and we will not be able to
do it while transferring data at run time.


From kgene.kim at samsung.com  Wed Jun 16 00:04:04 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 16 Jun 2010 13:04:04 +0900
Subject: [PATCH v4 2/3] ARM: S5PV210: Add keypad device helpers
In-Reply-To: <4C18351E.2080805@samsung.com>
References: <1276243728-17704-1-git-send-email-jy0922.shim@samsung.com>
	<1276243728-17704-2-git-send-email-jy0922.shim@samsung.com>
	<007801cb0b81$16cc0ff0$44642fd0$%kim@samsung.com>
	<4C18351E.2080805@samsung.com>
Message-ID: <009801cb0d08$f883fc90$e98bf5b0$%kim@samsung.com>

Joonyoung Shim wrote:
> 
> On 6/14/2010 2:18 PM, Kukjin Kim wrote:
> > Joonyoung Shim wrote:
> >> This patch adds the keypad device platform helpers for S5PV210 cpu.
> >>
> >> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> >> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> >> ---
> >>  arch/arm/mach-s5pv210/Kconfig            |    5 ++++
> >>  arch/arm/mach-s5pv210/Makefile           |    1 +
> >>  arch/arm/mach-s5pv210/cpu.c              |    4 +++
> >>  arch/arm/mach-s5pv210/include/mach/map.h |    3 ++
> >>  arch/arm/mach-s5pv210/setup-keypad.c     |   34
> >> ++++++++++++++++++++++++++++++
> >>  5 files changed, 47 insertions(+), 0 deletions(-)
> >>  create mode 100644 arch/arm/mach-s5pv210/setup-keypad.c
> >>
> >> diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
> >> index 0761eac..692d01c 100644
> >> --- a/arch/arm/mach-s5pv210/Kconfig
> >> +++ b/arch/arm/mach-s5pv210/Kconfig
> >> @@ -32,6 +32,11 @@ config S5PV210_SETUP_FB_24BPP
> >>  	help
> >>            Common setup code for S5PV210 with an 24bpp RGB display
> helper.
> >>
> >> +config S5PV210_SETUP_KEYPAD
> >> +	bool
> >> +	help
> >> +	  Common setup code for keypad.
> >> +
> >>  config S5PV210_SETUP_SDHCI
> >>          bool
> >>          select S5PV210_SETUP_SDHCI_GPIO
> >> diff --git a/arch/arm/mach-s5pv210/Makefile
> > b/arch/arm/mach-s5pv210/Makefile
> >> index 30be9a6..aae592a 100644
> >> --- a/arch/arm/mach-s5pv210/Makefile
> >> +++ b/arch/arm/mach-s5pv210/Makefile
> >> @@ -31,5 +31,6 @@ obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-
> onenand.o
> >>  obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
> >>  obj-$(CONFIG_S5PV210_SETUP_I2C1) 	+= setup-i2c1.o
> >>  obj-$(CONFIG_S5PV210_SETUP_I2C2) 	+= setup-i2c2.o
> >> +obj-$(CONFIG_S5PV210_SETUP_KEYPAD)	+= setup-keypad.o
> >>  obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
> >>  obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
> >> diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
> >> index 411a4a9..a3034ac 100644
> >> --- a/arch/arm/mach-s5pv210/cpu.c
> >> +++ b/arch/arm/mach-s5pv210/cpu.c
> >> @@ -80,6 +80,10 @@ void __init s5pv210_map_io(void)
> >>  	s3c_device_adc.name	= "s3c64xx-adc";
> >>  #endif
> >>
> >> +#ifdef CONFIG_SAMSUNG_DEV_KEYPAD
> >> +	samsung_device_keypad.name = "s5pv210-keypad";
> >> +#endif
> >> +
> >
> > Please use one method. See Kyungmin Park's prev. comments on the subject.
> >
> 
> I cannot understand this comment meaning and where is Kyungmin's
> comments? Please let me know detailed thing.
> 
Please refer to below URLs.

Kyungmin Park's comment:
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/015634.html

Ben Dooks' comment:
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/016519.html

And you can find similar case in the CFCON and TSADC patches for Samsung SoCs.

> >>  	iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
> >>
> >>  	/* initialise device information early */
> >> diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-
> >> s5pv210/include/mach/map.h
> >> index 34eb168..e2f6e2a 100644
> >> --- a/arch/arm/mach-s5pv210/include/mach/map.h
> >> +++ b/arch/arm/mach-s5pv210/include/mach/map.h
> >> @@ -32,6 +32,8 @@
> >>  #define S5PV210_PA_SPI0		0xE1300000
> >>  #define S5PV210_PA_SPI1		0xE1400000
> >>
> >> +#define S5PV210_PA_KEYPAD	(0xE1600000)
> >> +
> >>  #define S5PV210_PA_IIC0		(0xE1800000)
> >>  #define S5PV210_PA_IIC1		(0xFAB00000)
> >>  #define S5PV210_PA_IIC2		(0xE1A00000)
> >> @@ -104,5 +106,6 @@
> >>  #define S3C_PA_WDT		S5PV210_PA_WATCHDOG
> >>
> >>  #define SAMSUNG_PA_ADC		S5PV210_PA_ADC
> >> +#define SAMSUNG_PA_KEYPAD	S5PV210_PA_KEYPAD
> >>
> >>  #endif /* __ASM_ARCH_MAP_H */
> >> diff --git a/arch/arm/mach-s5pv210/setup-keypad.c
> > b/arch/arm/mach-s5pv210/setup-
> >> keypad.c
> >> new file mode 100644
> >> index 0000000..f51bf8d
> >> --- /dev/null
> >> +++ b/arch/arm/mach-s5pv210/setup-keypad.c
> >> @@ -0,0 +1,34 @@
> >> +/*
> >> + * linux/arch/arm/mach-s5pv210/setup-keypad.c
> >> + *
> >> + * Copyright (C) 2010 Samsung Electronics Co.Ltd
> >> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
> >> + *
> >> + *  This program is free software; you can redistribute  it and/or modify
> > it
> >> + *  under  the terms of  the GNU General  Public License as published by
> > the
> >> + *  Free Software Foundation;  either version 2 of the  License, or (at
> > your
> >> + *  option) any later version.
> >> + *
> >> + */
> >> +
> >> +#include <linux/gpio.h>
> >> +#include <plat/gpio-cfg.h>
> >> +
> >> +void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
> >> +{
> >> +	unsigned int gpio, end;
> >> +
> >> +	/* Set all the necessary GPH3 pins to special-function 3 */
> >
> > What's the special-function 3?
> 
> I refered s3c_gpio_cfgpin() comments of
> arch/arm/plat-samsung/include/plat/gpio-cfg.h
> 
> I think this is enough comments but if you want more specific comments
> still, i can add it.
> 
Hmm..just minor comment to easily reading.

> Thanks.
> 
> > How about 'special function KP_ROWs'?
> >
> >> +	end = S5PV210_GPH3(rows);
> >> +	for (gpio = S5PV210_GPH3(0); gpio < end; gpio++) {
> >> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
> >> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> >> +	}
> >> +
> >> +	/* Set all the necessary GPH2 pins to special-function 3 */
> >
> > How about 'special function KP_COLs'?
> >
> >> +	end = S5PV210_GPH2(cols);
> >> +	for (gpio = S5PV210_GPH2(0); gpio < end; gpio++) {
> >> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
> >> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> >> +	}
> >> +}
> >> --
> >
> >
> > Thanks.
> >

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From jy0922.shim at samsung.com  Wed Jun 16 00:26:14 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Wed, 16 Jun 2010 13:26:14 +0900
Subject: [PATCH v4 2/3] ARM: S5PV210: Add keypad device helpers
In-Reply-To: <009801cb0d08$f883fc90$e98bf5b0$%kim@samsung.com>
References: <1276243728-17704-1-git-send-email-jy0922.shim@samsung.com>
	<1276243728-17704-2-git-send-email-jy0922.shim@samsung.com>
	<007801cb0b81$16cc0ff0$44642fd0$%kim@samsung.com>
	<4C18351E.2080805@samsung.com>
	<009801cb0d08$f883fc90$e98bf5b0$%kim@samsung.com>
Message-ID: <4C185266.9060204@samsung.com>

On 6/16/2010 1:04 PM, Kukjin Kim wrote:
> Joonyoung Shim wrote:
>> On 6/14/2010 2:18 PM, Kukjin Kim wrote:
>>> Joonyoung Shim wrote:
>>>> This patch adds the keypad device platform helpers for S5PV210 cpu.
>>>>
>>>> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
>>>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>>>> ---
>>>>  arch/arm/mach-s5pv210/Kconfig            |    5 ++++
>>>>  arch/arm/mach-s5pv210/Makefile           |    1 +
>>>>  arch/arm/mach-s5pv210/cpu.c              |    4 +++
>>>>  arch/arm/mach-s5pv210/include/mach/map.h |    3 ++
>>>>  arch/arm/mach-s5pv210/setup-keypad.c     |   34
>>>> ++++++++++++++++++++++++++++++
>>>>  5 files changed, 47 insertions(+), 0 deletions(-)
>>>>  create mode 100644 arch/arm/mach-s5pv210/setup-keypad.c
>>>>
>>>> diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
>>>> index 0761eac..692d01c 100644
>>>> --- a/arch/arm/mach-s5pv210/Kconfig
>>>> +++ b/arch/arm/mach-s5pv210/Kconfig
>>>> @@ -32,6 +32,11 @@ config S5PV210_SETUP_FB_24BPP
>>>>  	help
>>>>            Common setup code for S5PV210 with an 24bpp RGB display
>> helper.
>>>> +config S5PV210_SETUP_KEYPAD
>>>> +	bool
>>>> +	help
>>>> +	  Common setup code for keypad.
>>>> +
>>>>  config S5PV210_SETUP_SDHCI
>>>>          bool
>>>>          select S5PV210_SETUP_SDHCI_GPIO
>>>> diff --git a/arch/arm/mach-s5pv210/Makefile
>>> b/arch/arm/mach-s5pv210/Makefile
>>>> index 30be9a6..aae592a 100644
>>>> --- a/arch/arm/mach-s5pv210/Makefile
>>>> +++ b/arch/arm/mach-s5pv210/Makefile
>>>> @@ -31,5 +31,6 @@ obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-
>> onenand.o
>>>>  obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
>>>>  obj-$(CONFIG_S5PV210_SETUP_I2C1) 	+= setup-i2c1.o
>>>>  obj-$(CONFIG_S5PV210_SETUP_I2C2) 	+= setup-i2c2.o
>>>> +obj-$(CONFIG_S5PV210_SETUP_KEYPAD)	+= setup-keypad.o
>>>>  obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
>>>>  obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
>>>> diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
>>>> index 411a4a9..a3034ac 100644
>>>> --- a/arch/arm/mach-s5pv210/cpu.c
>>>> +++ b/arch/arm/mach-s5pv210/cpu.c
>>>> @@ -80,6 +80,10 @@ void __init s5pv210_map_io(void)
>>>>  	s3c_device_adc.name	= "s3c64xx-adc";
>>>>  #endif
>>>>
>>>> +#ifdef CONFIG_SAMSUNG_DEV_KEYPAD
>>>> +	samsung_device_keypad.name = "s5pv210-keypad";
>>>> +#endif
>>>> +
>>> Please use one method. See Kyungmin Park's prev. comments on the subject.
>>>
>> I cannot understand this comment meaning and where is Kyungmin's
>> comments? Please let me know detailed thing.
>>
> Please refer to below URLs.
> 
> Kyungmin Park's comment:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/015634.html
> 
> Ben Dooks' comment:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/016519.html
> 
> And you can find similar case in the CFCON and TSADC patches for Samsung SoCs.
> 

OK. I see and will use wrapper function.

>>>>  	iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
>>>>
>>>>  	/* initialise device information early */
>>>> diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-
>>>> s5pv210/include/mach/map.h
>>>> index 34eb168..e2f6e2a 100644
>>>> --- a/arch/arm/mach-s5pv210/include/mach/map.h
>>>> +++ b/arch/arm/mach-s5pv210/include/mach/map.h
>>>> @@ -32,6 +32,8 @@
>>>>  #define S5PV210_PA_SPI0		0xE1300000
>>>>  #define S5PV210_PA_SPI1		0xE1400000
>>>>
>>>> +#define S5PV210_PA_KEYPAD	(0xE1600000)
>>>> +
>>>>  #define S5PV210_PA_IIC0		(0xE1800000)
>>>>  #define S5PV210_PA_IIC1		(0xFAB00000)
>>>>  #define S5PV210_PA_IIC2		(0xE1A00000)
>>>> @@ -104,5 +106,6 @@
>>>>  #define S3C_PA_WDT		S5PV210_PA_WATCHDOG
>>>>
>>>>  #define SAMSUNG_PA_ADC		S5PV210_PA_ADC
>>>> +#define SAMSUNG_PA_KEYPAD	S5PV210_PA_KEYPAD
>>>>
>>>>  #endif /* __ASM_ARCH_MAP_H */
>>>> diff --git a/arch/arm/mach-s5pv210/setup-keypad.c
>>> b/arch/arm/mach-s5pv210/setup-
>>>> keypad.c
>>>> new file mode 100644
>>>> index 0000000..f51bf8d
>>>> --- /dev/null
>>>> +++ b/arch/arm/mach-s5pv210/setup-keypad.c
>>>> @@ -0,0 +1,34 @@
>>>> +/*
>>>> + * linux/arch/arm/mach-s5pv210/setup-keypad.c
>>>> + *
>>>> + * Copyright (C) 2010 Samsung Electronics Co.Ltd
>>>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>>>> + *
>>>> + *  This program is free software; you can redistribute  it and/or modify
>>> it
>>>> + *  under  the terms of  the GNU General  Public License as published by
>>> the
>>>> + *  Free Software Foundation;  either version 2 of the  License, or (at
>>> your
>>>> + *  option) any later version.
>>>> + *
>>>> + */
>>>> +
>>>> +#include <linux/gpio.h>
>>>> +#include <plat/gpio-cfg.h>
>>>> +
>>>> +void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
>>>> +{
>>>> +	unsigned int gpio, end;
>>>> +
>>>> +	/* Set all the necessary GPH3 pins to special-function 3 */
>>> What's the special-function 3?
>> I refered s3c_gpio_cfgpin() comments of
>> arch/arm/plat-samsung/include/plat/gpio-cfg.h
>>
>> I think this is enough comments but if you want more specific comments
>> still, i can add it.
>>
> Hmm..just minor comment to easily reading.
> 

OK. I will add it.

>> Thanks.
>>
>>> How about 'special function KP_ROWs'?
>>>
>>>> +	end = S5PV210_GPH3(rows);
>>>> +	for (gpio = S5PV210_GPH3(0); gpio < end; gpio++) {
>>>> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
>>>> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
>>>> +	}
>>>> +
>>>> +	/* Set all the necessary GPH2 pins to special-function 3 */
>>> How about 'special function KP_COLs'?
>>>
>>>> +	end = S5PV210_GPH2(cols);
>>>> +	for (gpio = S5PV210_GPH2(0); gpio < end; gpio++) {
>>>> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
>>>> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
>>>> +	}
>>>> +}
>>>> --
>>>
>>> Thanks.
>>>
> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> 
> 



From daniel at caiaq.de  Wed Jun 16 01:35:19 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Wed, 16 Jun 2010 07:35:19 +0200
Subject: [PATCH 2/2] ehci-mxc: bail out on transceiver problems
In-Reply-To: <20100616014458.GA30484@pengutronix.de>
References: <1276598063-3956-1-git-send-email-w.sang@pengutronix.de>
	<1276598063-3956-2-git-send-email-w.sang@pengutronix.de>
	<20100615104342.GE17833@buzzloop.caiaq.de>
	<20100616014458.GA30484@pengutronix.de>
Message-ID: <20100616053519.GT17833@buzzloop.caiaq.de>

On Wed, Jun 16, 2010 at 03:44:58AM +0200, Wolfram Sang wrote:
> On Tue, Jun 15, 2010 at 12:43:42PM +0200, Daniel Mack wrote:
> > On Tue, Jun 15, 2010 at 12:34:23PM +0200, Wolfram Sang wrote:
> > > The old code registered the hcd even if there were no transceivers
> > > detected, leading to oopses like this if we try to probe a non-existant
> > > ULPI:
> > 
> > Hmm. I'm aware that there was a missing bail in this function, but
> > actually, I had hardware which didn't properly detect the ULPI chip but
> > still worked fine. There has been quite some discussion here about that,
> > and eventually I decided to not make this a hard error as it didn't
> > really harm.
> 
> Hmm, so, do you think this patch is stable-material after all?

Hard to say. It might break existing board support, which would be a
regression. OTOH, it fixes an Oops. Don't know really ...

Daniel


From richardcochran at gmail.com  Wed Jun 16 01:40:47 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Wed, 16 Jun 2010 07:40:47 +0200
Subject: [PATCH 04/12] phylib: add a way to make PHY time stamps possible.
In-Reply-To: <AANLkTimhAvu0_WuMCwnCrw9Rbcy6dKxvTlzepJm7ZDdR@mail.gmail.com>
References: <cover.1276615626.git.richard.cochran@omicron.at>
	<27c0ad283f025c2bb71e7ceb71be07f969939429.1276615626.git.richard.cochran@omicron.at>
	<AANLkTimhAvu0_WuMCwnCrw9Rbcy6dKxvTlzepJm7ZDdR@mail.gmail.com>
Message-ID: <20100616054047.GA2887@riccoc20.at.omicron.at>

On Tue, Jun 15, 2010 at 10:33:51AM -0600, Grant Likely wrote:
> > +config NETWORK_PHY_TIMESTAMPING
> Some overhead?  At a brief glance of the series it looks like it could
> add a lot of overhead, but I'm not fully clear on what the full
> process is.  Can you describe how the hardware timestamping works?  I
> could use an overview of what the kernel has to do.

First of all, I want to emphasize that this network stack option is
purely voluntary. Only those people who know that they have a PTP
capable PHY and really want the timestamps will (or should) enable
this option. When it is not enabled, it has no effect at all.

Hardware timestamping is described in

   Documentation/networking/timestamping.txt
   Documentation/networking/timestamping/timestamping.c

The PTP subsystem is described in

   Documentation/ptp/ptp.txt

There really is more to say about the issue than appears in those
documents, but they are a good starting place for discussion.

BTW I am submitting a conference paper on the design on the PTP
subsystem. If you would like to have it, just ask me off-list.

Richard


From mike at compulab.co.il  Wed Jun 16 02:09:44 2010
From: mike at compulab.co.il (Mike Rapoport)
Date: Wed, 16 Jun 2010 09:09:44 +0300
Subject: Request review of device tree documentation
In-Reply-To: <4C165FD1.6080505@firmworks.com>
References: <4C13430B.5000907@firmworks.com>	<1276339529.1962.184.camel@pasglop>	<1276339684.1962.186.camel@pasglop>	<4C13B618.1030006@firmworks.com>	<1276383132.1962.195.camel@pasglop>	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>	<4C146F18.9030008@firmworks.com>	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>	<20100614124438.GF9323@yookeroo>	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>	<20100614160201.GD9550@shareable.org>
	<4C165FD1.6080505@firmworks.com>
Message-ID: <4C186AA8.4040709@compulab.co.il>

Mitch Bradley wrote:

> The second topic is the hypothetical use of OFW as a HAL. That will not 
> happen for several reasons.  The opposition to the idea is widespread 
> and deeply held, and there are good arguments to support that 
> opposition.   Furthermore, the economic conditions necessary for the 
> creation of such a HAL do not exist in the ARM world, nor indeed in the 
> Linux world in general.  (The necessary condition is the ability for one 
> company to impose a substantial change by fiat - essentially a monopoly 
> position.)
> 
> Shall we agree, then, that any further discussion of the HAL issue is 
> "just for fun", and that nobody needs to feel threatened that it would 
> actually happen?

I've recently worked with vendor versions of U-Boot for advanced ARM 
SoCs. There is already *huge* chunk of HAL code in those versions. And 
if there would be possibility to have callbacks into the firmware these 
chunks would only grow, IMHO.


> The potential for "vendors breaking out of the debugging use case and 
> turning it into a HAL" is miniscule, because
> 
> a) The callback is disabled by default
> b) The technical challenges of the callback interface limit its 
> applicability to specific "wizard user" scenarios
> c) OFW is unlikely to achieve sufficient market penetration for the HAL 
> thing to be worth doing
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


-- 
Sincerely yours,
Mike.


From wmb at firmworks.com  Wed Jun 16 02:13:15 2010
From: wmb at firmworks.com (Mitch Bradley)
Date: Tue, 15 Jun 2010 20:13:15 -1000
Subject: Request review of device tree documentation
In-Reply-To: <4C186AA8.4040709@compulab.co.il>
References: <4C13430B.5000907@firmworks.com>	<1276339529.1962.184.camel@pasglop>	<1276339684.1962.186.camel@pasglop>	<4C13B618.1030006@firmworks.com>	<1276383132.1962.195.camel@pasglop>	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>	<4C146F18.9030008@firmworks.com>	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>	<20100614124438.GF9323@yookeroo>	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>	<20100614160201.GD9550@shareable.org>
	<4C165FD1.6080505@firmworks.com> <4C186AA8.4040709@compulab.co.il>
Message-ID: <4C186B7B.1060308@firmworks.com>

Mike Rapoport wrote:
> Mitch Bradley wrote:
>
>> The second topic is the hypothetical use of OFW as a HAL. That will 
>> not happen for several reasons.  The opposition to the idea is 
>> widespread and deeply held, and there are good arguments to support 
>> that opposition.   Furthermore, the economic conditions necessary for 
>> the creation of such a HAL do not exist in the ARM world, nor indeed 
>> in the Linux world in general.  (The necessary condition is the 
>> ability for one company to impose a substantial change by fiat - 
>> essentially a monopoly position.)
>>
>> Shall we agree, then, that any further discussion of the HAL issue is 
>> "just for fun", and that nobody needs to feel threatened that it 
>> would actually happen?
>
> I've recently worked with vendor versions of U-Boot for advanced ARM 
> SoCs. There is already *huge* chunk of HAL code in those versions. And 
> if there would be possibility to have callbacks into the firmware 
> these chunks would only grow, IMHO.

How can there be HAL code in U-Boot unless there is already the 
possibility to have callbacks into the firmware?

It is not HAL if it can't be called.

>
>
>> The potential for "vendors breaking out of the debugging use case and 
>> turning it into a HAL" is miniscule, because
>>
>> a) The callback is disabled by default
>> b) The technical challenges of the callback interface limit its 
>> applicability to specific "wizard user" scenarios
>> c) OFW is unlikely to achieve sufficient market penetration for the 
>> HAL thing to be worth doing
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>


From mike at compulab.co.il  Wed Jun 16 02:17:22 2010
From: mike at compulab.co.il (Mike Rapoport)
Date: Wed, 16 Jun 2010 09:17:22 +0300
Subject: Request review of device tree documentation
In-Reply-To: <4C186B7B.1060308@firmworks.com>
References: <4C13430B.5000907@firmworks.com>	<1276339529.1962.184.camel@pasglop>	<1276339684.1962.186.camel@pasglop>	<4C13B618.1030006@firmworks.com>	<1276383132.1962.195.camel@pasglop>	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>	<4C146F18.9030008@firmworks.com>	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>	<20100614124438.GF9323@yookeroo>	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>	<20100614160201.GD9550@shareable.org>
	<4C165FD1.6080505@firmworks.com> <4C186AA8.4040709@compulab.co.il>
	<4C186B7B.1060308@firmworks.com>
Message-ID: <4C186C72.2020506@compulab.co.il>

Mitch Bradley wrote:
> Mike Rapoport wrote:
>> Mitch Bradley wrote:
>>
>>> The second topic is the hypothetical use of OFW as a HAL. That will 
>>> not happen for several reasons.  The opposition to the idea is 
>>> widespread and deeply held, and there are good arguments to support 
>>> that opposition.   Furthermore, the economic conditions necessary for 
>>> the creation of such a HAL do not exist in the ARM world, nor indeed 
>>> in the Linux world in general.  (The necessary condition is the 
>>> ability for one company to impose a substantial change by fiat - 
>>> essentially a monopoly position.)
>>>
>>> Shall we agree, then, that any further discussion of the HAL issue is 
>>> "just for fun", and that nobody needs to feel threatened that it 
>>> would actually happen?
>>
>> I've recently worked with vendor versions of U-Boot for advanced ARM 
>> SoCs. There is already *huge* chunk of HAL code in those versions. And 
>> if there would be possibility to have callbacks into the firmware 
>> these chunks would only grow, IMHO.
> 
> How can there be HAL code in U-Boot unless there is already the 
> possibility to have callbacks into the firmware?

Currently it aims to abstract hardware from U-Boot and reuse the same HW 
access code across operating systems and bootloaders. If this code would 
have callbacks I afraid the things would became worse.

> It is not HAL if it can't be called.
> 
>>
>>
>>> The potential for "vendors breaking out of the debugging use case and 
>>> turning it into a HAL" is miniscule, because
>>>
>>> a) The callback is disabled by default
>>> b) The technical challenges of the callback interface limit its 
>>> applicability to specific "wizard user" scenarios
>>> c) OFW is unlikely to achieve sufficient market penetration for the 
>>> HAL thing to be worth doing
>>>
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>>


-- 
Sincerely yours,
Mike.


From richardcochran at gmail.com  Wed Jun 16 02:20:19 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Wed, 16 Jun 2010 08:20:19 +0200
Subject: [PATCH 05/12] phylib: Allow reading and writing a mii bus from
	atomic context.
In-Reply-To: <AANLkTin8RI4UKzA58k_qER_urdwnD037u5GZrVQS8IoS@mail.gmail.com>
References: <cover.1276615626.git.richard.cochran@omicron.at>
	<1b8219e7d7993d0e8204b94e959477e3007534ce.1276615626.git.richard.cochran@omicron.at>
	<AANLkTikeae2t4KmnawOCo2LqfSI57BKjNnUayY09DfEC@mail.gmail.com>
	<20100615170806.GB10668@riccoc20.at.omicron.at>
	<AANLkTin8RI4UKzA58k_qER_urdwnD037u5GZrVQS8IoS@mail.gmail.com>
Message-ID: <20100616062019.GB2887@riccoc20.at.omicron.at>

> That's right, and I fully agree with that change.  To me, going back
> to allowing spin locks is a regression because it adds a new source of
> scheduling latency.

I think that the change was not about reducing scheduling
latency. Rather, the idea was simply to allow mdio bus drivers that
sleep. Here is the change log message:

    commit 35b5f6b1a82b5c586e0b24c711dc6ba944e88ef1

    PHYLIB: Locking fixes for PHY I/O potentially sleeping
    
    PHY read/write functions can potentially sleep (e.g., a PHY accessed
    via I2C).  The following changes were made to account for this:
    
        * Change spin locks to mutex locks
        * Add a BUG_ON() to phy_read() phy_write() to warn against
          calling them from an interrupt context.
        * Use work queue for PHY state machine handling since
          it can potentially sleep
        * Change phydev lock from spinlock to mutex

The fundamental issue is this: Fro the SO_TIMESTAMPING API, receive
timestamps must appear in a control message along with the packet
data. Only the MAC driver (or the PHY driver) knows how to get the
timestamp. The stack calls the MAC driver via its napi poll
function. During the call, the driver must provide the skb with Rx
timestamp.

The only reasonable way to do this is to have the driver fetch the
timestamp durng the napi poll function. For MAC drivers with fast
register access, the performance penalty is small. For PHY drivers
with must go via the MDIO bus, the performance penalty is obviously
larger, and the user must be willing to live with it.

You might suggest the alternate that the driver would defer the
netif_receive_skb() callback until a work queue completes, providing
the Rx timestamp. The driver would then call netif_receive_skb() at
some later time.

However, there are a number of problems with this idea:

1. It is really icky for the drivers to be creating new skb queues for
   this purpose. MAC drivers would have to maintain such queues on
   behalf of the PHY drivers, but only when the PHYs support
   timestamping. Yuck.

2. There is a (soft) real time constraint on the delivery of the PTP
   packets to the user space application. Basicly, delays and jitter
   in the time to receive the packet negatively affect the clock servo
   loop.

3. It cannot work for many kinds of PTP timestamping hardware. Some of
   hardware only timestamps PTP packets. That means that not every
   received packet will have a timestamp. Such hardware provides some
   key data from the packet (like PTP UUID and sequence number) with
   the timestamp. Software must match this information to a particular
   packet. In order to defer a skb, the driver must first obtain the
   timestamp information. This is a catch-22.

Having said all that, I am still open to suggestions...

Richard


From richardcochran at gmail.com  Wed Jun 16 02:29:40 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Wed, 16 Jun 2010 08:29:40 +0200
Subject: [PATCH 04/12] phylib: add a way to make PHY time stamps possible.
In-Reply-To: <27c0ad283f025c2bb71e7ceb71be07f969939429.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
	<27c0ad283f025c2bb71e7ceb71be07f969939429.1276615626.git.richard.cochran@omicron.at>
Message-ID: <20100616062940.GC2887@riccoc20.at.omicron.at>

On Tue, Jun 15, 2010 at 06:08:20PM +0200, Richard Cochran wrote:

> +static inline void skb_tx_timetamp(struct phy_device *phy, struct sk_buff *skb)
> +{
> +	union skb_shared_tx *shtx = skb_tx(skb);
> +
> +	if (shtx->hardware && phy && phy->drv->txtstamp)
> +		phy->drv->txtstamp(phy, skb);
> +
> +	if (shtx->software && !shtx->in_progress)
> +		skb_tstamp_tx(skb, NULL);
> +}

I forgot to mention this patch also provides a way to fix the broken
software timestamp fallback mode of the SO_TIMESTAMPING API.

We would have to add this inline call to every MAC driver in an
appropriate spot within the hard_xmit function. It is not too pretty,
but providing this as a compile time option will promote
standardization of the SO_TIMESTAMPING API for applications.

Richard


From wmb at firmworks.com  Wed Jun 16 02:32:51 2010
From: wmb at firmworks.com (Mitch Bradley)
Date: Tue, 15 Jun 2010 20:32:51 -1000
Subject: Request review of device tree documentation
In-Reply-To: <4C186C72.2020506@compulab.co.il>
References: <4C13430B.5000907@firmworks.com>	<1276339529.1962.184.camel@pasglop>	<1276339684.1962.186.camel@pasglop>	<4C13B618.1030006@firmworks.com>	<1276383132.1962.195.camel@pasglop>	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>	<4C146F18.9030008@firmworks.com>	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>	<20100614124438.GF9323@yookeroo>	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>	<20100614160201.GD9550@shareable.org>
	<4C165FD1.6080505@firmworks.com> <4C186AA8.4040709@compulab.co.il>
	<4C186B7B.1060308@firmworks.com> <4C186C72.2020506@compulab.co.il>
Message-ID: <4C187013.5000400@firmworks.com>

Mike Rapoport wrote:
> Mitch Bradley wrote:
>> Mike Rapoport wrote:
>>> Mitch Bradley wrote:
>>>
>>>> The second topic is the hypothetical use of OFW as a HAL. That will 
>>>> not happen for several reasons.  The opposition to the idea is 
>>>> widespread and deeply held, and there are good arguments to support 
>>>> that opposition.   Furthermore, the economic conditions necessary 
>>>> for the creation of such a HAL do not exist in the ARM world, nor 
>>>> indeed in the Linux world in general.  (The necessary condition is 
>>>> the ability for one company to impose a substantial change by fiat 
>>>> - essentially a monopoly position.)
>>>>
>>>> Shall we agree, then, that any further discussion of the HAL issue 
>>>> is "just for fun", and that nobody needs to feel threatened that it 
>>>> would actually happen?
>>>
>>> I've recently worked with vendor versions of U-Boot for advanced ARM 
>>> SoCs. There is already *huge* chunk of HAL code in those versions. 
>>> And if there would be possibility to have callbacks into the 
>>> firmware these chunks would only grow, IMHO.
>>
>> How can there be HAL code in U-Boot unless there is already the 
>> possibility to have callbacks into the firmware?
>
> Currently it aims to abstract hardware from U-Boot and reuse the same 
> HW access code across operating systems and bootloaders. If this code 
> would have callbacks I afraid the things would became worse.

The only way I can understand what you said is if I assume that by 
"callback", you mean the following sequence:

a) U-boot loads and executes the OS, providing to the OS the address of 
some HW access routines that it can use
b) The OS calls one of those HW access routines
c) During the execution of that HW access routine, that routine calls 
"back" into the OS, before returning.  So a call into the OS is nested 
inside a call into U-boot resident code.

If that is what you are worried about, it is not what we were 
discussing.  We were discussing - and many people were against - step (b).

Are you saying that step (b) - the OS calling into routines provided by 
U-Boot - is already the status quo?

>
>> It is not HAL if it can't be called.
>>
>>>
>>>
>>>> The potential for "vendors breaking out of the debugging use case 
>>>> and turning it into a HAL" is miniscule, because
>>>>
>>>> a) The callback is disabled by default
>>>> b) The technical challenges of the callback interface limit its 
>>>> applicability to specific "wizard user" scenarios
>>>> c) OFW is unlikely to achieve sufficient market penetration for the 
>>>> HAL thing to be worth doing
>>>>
>>>>
>>>> _______________________________________________
>>>> linux-arm-kernel mailing list
>>>> linux-arm-kernel at lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>
>>>
>
>


From linus.ml.walleij at gmail.com  Wed Jun 16 02:38:38 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Wed, 16 Jun 2010 08:38:38 +0200
Subject: [PATCH 06/13] DMAENGINE: driver for the ARM PL080/PL081 
	PrimeCells
In-Reply-To: <4C184C1C.4000204@st.com>
References: <1276270031-1607-1-git-send-email-linus.walleij@stericsson.com>
	<4C15C60E.6080404@st.com>
	<AANLkTim9n-p-Pw6FWvzQMBiAuB3h9ILq1Ya6XWk_0l-c@mail.gmail.com>
	<4C170EE2.4010706@st.com>
	<CEE6BB42CAD6E947908279175AF8470A025E5AE1ED@EXDCVYMBSTM006.EQ1STM.local>
	<4C184C1C.4000204@st.com>
Message-ID: <AANLkTinZgUzXy9wH760foYDqbr5gvHO07LkiCco_q8Wj@mail.gmail.com>

[Viresh]

> In the same way, how other peripheral related data is passed to DMA driver,
> (like request lines), we can also pass configuration and control information.

Yep.

> In SPEAr6xx, Memory is accessible from Master1
> only but in SPEAr3xx only from Master 2, similar is the pattern with few
> peripherals also and so i need control over DMA channel configuration.

Oh I had no clue that you could set up your masters like that!
Anyway, I'll attempt to hack in some platform config for how
the AHB masters are assigned, but you'll likely have to patch it
to work with SPEAr in the end.

>> Currently only done dynamically with DMA as the master for
>> Mem2mem, mem2per and per2mem. Mastering from the peripherals
>> is not supported. Do you have advanced features like that?
>
> We have JPEG controller, which acts as a flow controller for JPEG to
> mem transfer. (Synopsys JPEG Controller).

OK that's special..

>> Anyway it can be passed in from platform data easily.
>
> But platform data will be passed one time only and we will not be able to
> do it while transferring data at run time.

Usually there is a very fixed use for each virtual DMA channel (which
have a platform config each), i.e. usually there is only one or two
flow controls per virtual channel. So in this case I guess that
Synopsys JPEG has a virtual channel that always is JPEG->mem with
JPEG as master, so it can actually be in fix platform data?

Anyway, we can probably extended either the way we did for PrimeCells
or in some generic way by adding config commands to the DMAengine,
so I see no road blocker.

Yours,
Linus Walleij


From richardcochran at gmail.com  Wed Jun 16 02:45:41 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Wed, 16 Jun 2010 08:45:41 +0200
Subject: [PATCH 10/12] ptp: Added a clock that uses the eTSEC found on
	the MPC85xx.
In-Reply-To: <AANLkTikFc15j-Qhw9M2CnKLKq58Wi1xD7E2dtVNsVgeA@mail.gmail.com>
References: <cover.1276615626.git.richard.cochran@omicron.at>
	<041faf3cb6ecbedf8f3ff2104914f91d2a24fc4d.1276615626.git.richard.cochran@omicron.at>
	<AANLkTikFc15j-Qhw9M2CnKLKq58Wi1xD7E2dtVNsVgeA@mail.gmail.com>
Message-ID: <20100616064541.GD2887@riccoc20.at.omicron.at>

On Tue, Jun 15, 2010 at 11:20:41AM -0600, Grant Likely wrote:
> 
> Is this header file used by anything other than gianfar_ptp.c?  If
> not, then roll the two files together.

I anticipate that it might be necessary to share the header's contents
with gianfar.c one day.

> Use dash ('-') not underscore ('_') in property names.

Okay, can do.

> If you encode this value as a string, then it will be friendly for humans too.

Okay.

> I could use more explication here.  Is this a divider value?
> Computers are good at making calculations, and the driver can obtain
> the clock frequency supplied to the device.  It may be more useful to
> specify here the desired frequency rather than the divider.  Certainly
> more human-friendly too.

It is not that simple. The basic algorithm is described in the text,
and anyone wanting to use the eTSEC for PTP will have to consider the
issue themselves, since it is a design issue with a few tradeoffs
related to the board layout. It is really too thorny to do in the
driver automatically.

I can post a tcltk calculator script for finding appropriate values,
in anyone would like to see it.

> > +static struct etsects the_clock;
> 
> Will there ever be multiple instances of this device?

No, never. If you consider how PTP works, there can only be one clock
per system.

> Consider of_iomap(), it will simplify the code a bit.

> Move ptp_gianfar_exit() definition here so it is immediately before
> the module_exit() line.

Okay.


Thanks for the review,

Richard




From s.hauer at pengutronix.de  Wed Jun 16 02:47:23 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 16 Jun 2010 08:47:23 +0200
Subject: [PATCH 0/4]Refine iomux files for i.MX51
In-Reply-To: <1276352559-8105-1-git-send-email-jason77.wang@gmail.com>
References: <1276352559-8105-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <20100616064723.GH20799@pengutronix.de>

On Sat, Jun 12, 2010 at 10:22:35PM +0800, Jason Wang wrote:
> Through the discussion, I divide my patches to 3 parts.
> part1: mx51 iomux related part, the first patch in this part is from
>        Amit, other patches are based off this patch and they are some
>        fix or adding definitions for imx51_3ds board.

This is ok now. Can you please rebase onto
git://git.pengutronix.de/git/imx/linux-2.6.git imx-for-2.6.36

The first patch conflicts with another of your patches:

e5ceef78 mx5: Add i2c to Freescale MX51 Babbage HW



-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From mike at compulab.co.il  Wed Jun 16 02:47:40 2010
From: mike at compulab.co.il (Mike Rapoport)
Date: Wed, 16 Jun 2010 09:47:40 +0300
Subject: Request review of device tree documentation
In-Reply-To: <4C187013.5000400@firmworks.com>
References: <4C13430B.5000907@firmworks.com>	<1276339529.1962.184.camel@pasglop>	<1276339684.1962.186.camel@pasglop>	<4C13B618.1030006@firmworks.com>	<1276383132.1962.195.camel@pasglop>	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>	<4C146F18.9030008@firmworks.com>	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>	<20100614124438.GF9323@yookeroo>	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>	<20100614160201.GD9550@shareable.org>
	<4C165FD1.6080505@firmworks.com> <4C186AA8.4040709@compulab.co.il>
	<4C186B7B.1060308@firmworks.com> <4C186C72.2020506@compulab.co.il>
	<4C187013.5000400@firmworks.com>
Message-ID: <4C18738C.4090809@compulab.co.il>

Mitch Bradley wrote:
> Mike Rapoport wrote:
>> Mitch Bradley wrote:
>>> Mike Rapoport wrote:
>>>> Mitch Bradley wrote:
>>>>
>>>>> The second topic is the hypothetical use of OFW as a HAL. That will 
>>>>> not happen for several reasons.  The opposition to the idea is 
>>>>> widespread and deeply held, and there are good arguments to support 
>>>>> that opposition.   Furthermore, the economic conditions necessary 
>>>>> for the creation of such a HAL do not exist in the ARM world, nor 
>>>>> indeed in the Linux world in general.  (The necessary condition is 
>>>>> the ability for one company to impose a substantial change by fiat 
>>>>> - essentially a monopoly position.)
>>>>>
>>>>> Shall we agree, then, that any further discussion of the HAL issue 
>>>>> is "just for fun", and that nobody needs to feel threatened that it 
>>>>> would actually happen?
>>>>
>>>> I've recently worked with vendor versions of U-Boot for advanced ARM 
>>>> SoCs. There is already *huge* chunk of HAL code in those versions. 
>>>> And if there would be possibility to have callbacks into the 
>>>> firmware these chunks would only grow, IMHO.
>>>
>>> How can there be HAL code in U-Boot unless there is already the 
>>> possibility to have callbacks into the firmware?
>>
>> Currently it aims to abstract hardware from U-Boot and reuse the same 
>> HW access code across operating systems and bootloaders. If this code 
>> would have callbacks I afraid the things would became worse.
> 
> The only way I can understand what you said is if I assume that by 
> "callback", you mean the following sequence:
> 
> a) U-boot loads and executes the OS, providing to the OS the address of 
> some HW access routines that it can use
> b) The OS calls one of those HW access routines
> c) During the execution of that HW access routine, that routine calls 
> "back" into the OS, before returning.  So a call into the OS is nested 
> inside a call into U-boot resident code.
> 
> If that is what you are worried about, it is not what we were 
> discussing.  We were discussing - and many people were against - step (b).
> 
> Are you saying that step (b) - the OS calling into routines provided by 
> U-Boot - is already the status quo?

I'm also objecting the step (b) and, fortunately, it's not yet the 
status quo.
Current U-Boot/kernel implementations I've encountered still do not have 
OS calls to resident HW access routines. But if such calls would be 
allowed, my impression is that SoC vendors would make extensive use of them.

>>
>>> It is not HAL if it can't be called.
>>>
>>>>
>>>>
>>>>> The potential for "vendors breaking out of the debugging use case 
>>>>> and turning it into a HAL" is miniscule, because
>>>>>
>>>>> a) The callback is disabled by default
>>>>> b) The technical challenges of the callback interface limit its 
>>>>> applicability to specific "wizard user" scenarios
>>>>> c) OFW is unlikely to achieve sufficient market penetration for the 
>>>>> HAL thing to be worth doing
>>>>>
>>>>>
>>>>> _______________________________________________
>>>>> linux-arm-kernel mailing list
>>>>> linux-arm-kernel at lists.infradead.org
>>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>>
>>>>
>>
>>


-- 
Sincerely yours,
Mike.


From m.szyprowski at samsung.com  Wed Jun 16 02:49:12 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 08:49:12 +0200
Subject: [PATCH v2] SDHCI-S3C fixes and enhancements (platform specific code)
Message-ID: <1276670954-17652-1-git-send-email-m.szyprowski@samsung.com>

Hello,

This series includes various fixes to sdhci-s3c driver as well as a
major feature enhancement. This patch series is prepared to get complete
sdhci support on Samsung Aquila board.

A quick overview on the patches:

#1 - add support for various methods of notifying the host driver about
     the card insertion/removal (should be compatible with existing code)
#2 - add sdhci driver platform data for all hsmmc controllers on Samsung
     Aquila board

Changes to the sdhci-s3c driver itself will be posted in a separate
patch series for easier merging, please refer to the "[PATCH] SDHCI-S3C
fixes and enhancements (driver specific code)" thread.

Changes since V1:
- added support for external gpio interrupt based card detect method
  directly to sdhci-s3c driver
- removed s3c64xx compilation fix patch from the series

A complete list of patches:

[PATCH 1/2] Samsung: sdhci-s3c: add support for new card detection methods
[PATCH 2/2] s5pv210: Aquila: add definitions for sdhci devices

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center



From m.szyprowski at samsung.com  Wed Jun 16 02:49:14 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 08:49:14 +0200
Subject: [PATCH 2/2] s5pv210: Aquila: add definitions for sdhci devices
In-Reply-To: <1276670954-17652-1-git-send-email-m.szyprowski@samsung.com>
References: <1276670954-17652-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276670954-17652-3-git-send-email-m.szyprowski@samsung.com>

This patch add support for SDHCI blocks on Samsung Aquila board. The
following host controllers are defined:
1. Internal MoviNAND device (permanently wired to the controller)
2. Internal WiFI SDIO device (card is activated by power regualor)
3. External MMC/SD socket (card detection is provided by external
gpio interrupt)

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pv210/Kconfig       |    4 +++
 arch/arm/mach-s5pv210/mach-aquila.c |   43 +++++++++++++++++++++++++++++++++++
 2 files changed, 47 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0761eac..f48d70a 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -50,7 +50,11 @@ config MACH_AQUILA
 	select CPU_S5PV210
 	select ARCH_SPARSEMEM_ENABLE
 	select S5PV210_SETUP_FB_24BPP
+	select S5PV210_SETUP_SDHCI
 	select S3C_DEV_FB
+	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC1
+	select S3C_DEV_HSMMC2
 	help
 	  Machine support for the Samsung Aquila target based on S5PC110 SoC
 
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 10bc76e..a616498 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/fb.h>
+#include <linux/gpio.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -22,12 +23,15 @@
 #include <mach/map.h>
 #include <mach/regs-clock.h>
 #include <mach/regs-fb.h>
+#include <mach/regs-gpio.h>
 
 #include <plat/regs-serial.h>
 #include <plat/s5pv210.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb.h>
+#include <plat/gpio-cfg.h>
+#include <plat/sdhci.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
@@ -116,8 +120,44 @@ static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
 	.setup_gpio	= s5pv210_fb_gpio_setup_24bpp,
 };
 
+/* MoviNAND */
+static struct s3c_sdhci_platdata aquila_hsmmc0_data __initdata = {
+	.max_width		= 4,
+	.cd_type		= S3C_SDHCI_CD_PERMANENT,
+};
+
+/* Wireless LAN */
+static struct s3c_sdhci_platdata aquila_hsmmc1_data __initdata = {
+	.max_width		= 4,
+	.cd_type		= S3C_SDHCI_CD_EXTERNAL,
+	/* ext_cd_{init,cleanup} callbacks will be added later */
+};
+
+/* External Flash */
+#define AQUILA_EXT_FLASH_EN	S5PV210_MP05(4)
+#define AQUILA_EXT_FLASH_CD	S5PV210_GPH3(4)
+static struct s3c_sdhci_platdata aquila_hsmmc2_data __initdata = {
+	.max_width		= 4,
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= AQUILA_EXT_FLASH_CD,
+	.ext_cd_gpio_invert	= 1,
+};
+
+static void aquila_setup_sdhci()
+{
+	gpio_request(AQUILA_EXT_FLASH_EN, "FLASH_EN");
+	gpio_direction_output(AQUILA_EXT_FLASH_EN, 1);
+
+	s3c_sdhci0_set_platdata(&aquila_hsmmc0_data);
+	s3c_sdhci1_set_platdata(&aquila_hsmmc1_data);
+	s3c_sdhci2_set_platdata(&aquila_hsmmc2_data);
+};
+
 static struct platform_device *aquila_devices[] __initdata = {
 	&s3c_device_fb,
+	&s3c_device_hsmmc0,
+	&s3c_device_hsmmc1,
+	&s3c_device_hsmmc2,
 };
 
 static void __init aquila_map_io(void)
@@ -129,6 +169,9 @@ static void __init aquila_map_io(void)
 
 static void __init aquila_machine_init(void)
 {
+	/* SDHCI */
+	aquila_setup_sdhci();
+
 	/* FB */
 	s3c_fb_set_platdata(&aquila_lcd_pdata);
 
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun 16 02:49:13 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 08:49:13 +0200
Subject: [PATCH 1/2] Samsung: sdhci-s3c: add support for new card detection
	methods
In-Reply-To: <1276670954-17652-1-git-send-email-m.szyprowski@samsung.com>
References: <1276670954-17652-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276670954-17652-2-git-send-email-m.szyprowski@samsung.com>

On some Samsung SoCs not all SDHCI controllers have card detect (CD)
line. For some embedded designs it is not even needed, because ususally
the device (like SDIO flash memory or wifi controller) is permanently
wired to the controller. There are also systems which have a card detect
line connected to some of the external interrupt lines or the presence
of the card depends on some other actions (like enabling a power
regulator).

This patch adds support for all these cases. The following card
detection methods are possible:

1. internal sdhci host card detect line
2. external event
3. external gpio interrupt
4. no card detect line, controller will poll for the card
5. no card detect line, card is permanently wired to the controller
(once detected host won't poll it any more)

By default, all existing code would use method #1, what is compatible
with the previous version of the driver.

In case of external event, two callbacks must be provided in platdata:
ext_cd_init and ext_cd_cleanup. Both of them get a callback to a
function that notifies the s3c-sdhci host contoller as their argument.
That callback function should be called from the even dispatcher to let
host notice the card insertion/removal.

In case of external gpio interrupt, a gpio pin number must be provided
in platdata (ext_cd_gpio parameter), as well as the information about
the polarity of that gpio pin (ext_cd_gpio_invert). By default
(ext_cd_gpio_invert == 0) gpio value 0 means 'card has been removed',
but this can be changed to 'card has been removed' when
ext_cd_gpio_invert == 1.

This patch adds all required changes to platform support code.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s3c64xx/setup-sdhci-gpio.c   |   14 +++++++++---
 arch/arm/mach-s5pc100/setup-sdhci-gpio.c   |   21 ++++++++++++++-----
 arch/arm/mach-s5pv210/setup-sdhci-gpio.c   |   22 +++++++++++++++-----
 arch/arm/plat-samsung/dev-hsmmc.c          |    5 ++++
 arch/arm/plat-samsung/dev-hsmmc1.c         |    5 ++++
 arch/arm/plat-samsung/dev-hsmmc2.c         |    5 ++++
 arch/arm/plat-samsung/include/plat/sdhci.h |   29 ++++++++++++++++++++++++++++
 7 files changed, 85 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
index a58c0cc..54c311c 100644
--- a/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s3c64xx/setup-sdhci-gpio.c
@@ -22,6 +22,7 @@
 
 void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 	unsigned int end;
 
@@ -33,12 +34,15 @@ void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
 	}
 
-	s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
+	}
 }
 
 void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 	unsigned int end;
 
@@ -50,8 +54,10 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
 	}
 
-	s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
+	}
 }
 
 void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
index 7769c76..e4b6739 100644
--- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
@@ -23,6 +23,7 @@
 
 void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 	unsigned int end;
 	unsigned int num;
@@ -47,12 +48,15 @@ void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 		}
 	}
 
-	s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
+	}
 }
 
 void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 	unsigned int end;
 
@@ -64,12 +68,15 @@ void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
 	}
 
-	s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
+	}
 }
 
 void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 	unsigned int end;
 
@@ -81,6 +88,8 @@ void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
 	}
 
-	s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
+	}
 }
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
index fe7d86d..b3ad243 100644
--- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
+++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c
@@ -21,9 +21,11 @@
 #include <mach/gpio.h>
 #include <plat/gpio-cfg.h>
 #include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
 
 void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 
 	/* Set all the necessary GPG0/GPG1 pins to special-function 2 */
@@ -48,12 +50,15 @@ void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
 		break;
 	}
 
-	s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S5PV210_GPG0(2), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S5PV210_GPG0(2), S3C_GPIO_SFN(2));
+	}
 }
 
 void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 
 	/* Set all the necessary GPG1[0:1] pins to special-function 2 */
@@ -68,12 +73,15 @@ void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
 		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
 	}
 
-	s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S5PV210_GPG1(2), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S5PV210_GPG1(2), S3C_GPIO_SFN(2));
+	}
 }
 
 void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 {
+	struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
 	unsigned int gpio;
 
 	/* Set all the necessary GPG2[0:1] pins to special-function 2 */
@@ -99,6 +107,8 @@ void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
 		break;
 	}
 
-	s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
-	s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
+	if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
+		s3c_gpio_setpull(S5PV210_GPG2(2), S3C_GPIO_PULL_UP);
+		s3c_gpio_cfgpin(S5PV210_GPG2(2), S3C_GPIO_SFN(2));
+	}
 }
diff --git a/arch/arm/plat-samsung/dev-hsmmc.c b/arch/arm/plat-samsung/dev-hsmmc.c
index 4c05b39..b0f93f1 100644
--- a/arch/arm/plat-samsung/dev-hsmmc.c
+++ b/arch/arm/plat-samsung/dev-hsmmc.c
@@ -60,6 +60,11 @@ void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
 	struct s3c_sdhci_platdata *set = &s3c_hsmmc0_def_platdata;
 
 	set->max_width = pd->max_width;
+	set->cd_type = pd->cd_type;
+	set->ext_cd_init = pd->ext_cd_init;
+	set->ext_cd_cleanup = pd->ext_cd_cleanup;
+	set->ext_cd_gpio = pd->ext_cd_gpio;
+	set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
 
 	if (pd->cfg_gpio)
 		set->cfg_gpio = pd->cfg_gpio;
diff --git a/arch/arm/plat-samsung/dev-hsmmc1.c b/arch/arm/plat-samsung/dev-hsmmc1.c
index e49bc4c..1504fd8 100644
--- a/arch/arm/plat-samsung/dev-hsmmc1.c
+++ b/arch/arm/plat-samsung/dev-hsmmc1.c
@@ -60,6 +60,11 @@ void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
 	struct s3c_sdhci_platdata *set = &s3c_hsmmc1_def_platdata;
 
 	set->max_width = pd->max_width;
+	set->cd_type = pd->cd_type;
+	set->ext_cd_init = pd->ext_cd_init;
+	set->ext_cd_cleanup = pd->ext_cd_cleanup;
+	set->ext_cd_gpio = pd->ext_cd_gpio;
+	set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
 
 	if (pd->cfg_gpio)
 		set->cfg_gpio = pd->cfg_gpio;
diff --git a/arch/arm/plat-samsung/dev-hsmmc2.c b/arch/arm/plat-samsung/dev-hsmmc2.c
index 824580b..b28ef17 100644
--- a/arch/arm/plat-samsung/dev-hsmmc2.c
+++ b/arch/arm/plat-samsung/dev-hsmmc2.c
@@ -61,6 +61,11 @@ void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
 	struct s3c_sdhci_platdata *set = &s3c_hsmmc2_def_platdata;
 
 	set->max_width = pd->max_width;
+	set->cd_type = pd->cd_type;
+	set->ext_cd_init = pd->ext_cd_init;
+	set->ext_cd_cleanup = pd->ext_cd_cleanup;
+	set->ext_cd_gpio = pd->ext_cd_gpio;
+	set->ext_cd_gpio_invert = pd->ext_cd_gpio_invert;
 
 	if (pd->cfg_gpio)
 		set->cfg_gpio = pd->cfg_gpio;
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 13f9fb2..5eb261f 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -20,10 +20,31 @@ struct mmc_host;
 struct mmc_card;
 struct mmc_ios;
 
+enum cd_types {
+	S3C_SDHCI_CD_INTERNAL,	/* use mmc internal CD line */
+	S3C_SDHCI_CD_EXTERNAL,	/* use external callback */
+	S3C_SDHCI_CD_GPIO,	/* use external gpio pin for CD line */
+	S3C_SDHCI_CD_NONE,	/* no CD line, use polling to detect card */
+	S3C_SDHCI_CD_PERMANENT,	/* no CD line, card permanently wired to host */
+};
+
 /**
  * struct s3c_sdhci_platdata() - Platform device data for Samsung SDHCI
  * @max_width: The maximum number of data bits supported.
  * @host_caps: Standard MMC host capabilities bit field.
+ * @cd_type: Type of Card Detection method (see cd_types enum above)
+ * @ext_cd_init: Initialize external card detect subsystem. Called on
+ *		 sdhci-s3c driver probe when cd_type == S3C_SDHCI_CD_EXTERNAL.
+ *		 notify_func argument is a callback to the sdhci-s3c driver
+ *		 that triggers the card detection event. Callback arguments:
+ *		 dev is pointer to platform device of the host controller,
+ *		 state is new state of the card (0 - removed, 1 - inserted).
+ * @ext_cd_cleanup: Cleanup external card detect subsystem. Called on
+ *		 sdhci-s3c driver remove when cd_type == S3C_SDHCI_CD_EXTERNAL.
+ *		 notify_func argument is the same callback as for ext_cd_init.
+ * @ext_cd_gpio: gpio pin used for external CD line, valid only if
+ *		 cd_type == S3C_SDHCI_CD_GPIO
+ * @ext_cd_gpio_invert: invert values for external CD gpio line
  * @cfg_gpio: Configure the GPIO for a specific card bit-width
  * @cfg_card: Configure the interface for a specific card and speed. This
  *            is necessary the controllers and/or GPIO blocks require the
@@ -37,9 +58,17 @@ struct mmc_ios;
 struct s3c_sdhci_platdata {
 	unsigned int	max_width;
 	unsigned int	host_caps;
+	enum cd_types	cd_type;
 
 	char		**clocks;	/* set of clock sources */
 
+	int		ext_cd_gpio;
+	bool		ext_cd_gpio_invert;
+	int 	(*ext_cd_init)(void (*notify_func)(struct platform_device *,
+						   int state));
+	int 	(*ext_cd_cleanup)(void (*notify_func)(struct platform_device *,
+						      int state));
+
 	void	(*cfg_gpio)(struct platform_device *dev, int width);
 	void	(*cfg_card)(struct platform_device *dev,
 			    void __iomem *regbase,
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun 16 02:49:53 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 08:49:53 +0200
Subject: [PATCH v2] SDHCI-S3C fixes and enhancements (driver specific code)
Message-ID: <1276670996-17729-1-git-send-email-m.szyprowski@samsung.com>

Hello,

This series includes various fixes to sdhci-s3c driver as well as a
major feature enhancement. This patch series is prepared to get complete
sdhci support on Samsung Aquila board.

A quick overview on the patches:

#1 - add missing sdhci_s3c_driver_remove() function
#2 - introduce new sdhci quirk to get rid of anoying runtime warning and
     possible problems with slow mmc/sd cards
#3 - add support for various methods of notifying the host driver about
     the card insertion/removal (should be compatible with existing code)

Last patch requires changes to the Samsung platform setup code, which
has been posted in a separate patch series for easier merging, please
refer to the "[PATCH v2] SDHCI-S3C fixes and enhancements (platform
specific code)" thread.

Changes since V1:
- added support for gpio external interrupt card based detect method
  directly to sdhci-s3c driver
- removed duplicate Kconfig patch
- removed timeout patch (not really needed)

A complete list of patches:

[PATCH 1/3] sdhci-s3c: add missing remove function
[PATCH 2/3] sdhci-s3c: add support for the non standard minimal clock value
[PATCH 3/3] sdhci-s3c: add support for new card detection methods

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center


From m.szyprowski at samsung.com  Wed Jun 16 02:49:56 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 08:49:56 +0200
Subject: [PATCH 3/3] sdhci-s3c: add support for new card detection methods
In-Reply-To: <1276670996-17729-1-git-send-email-m.szyprowski@samsung.com>
References: <1276670996-17729-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276670996-17729-4-git-send-email-m.szyprowski@samsung.com>

On some Samsung SoCs not all SDHCI controllers have card detect (CD)
line. For some embedded designs it is not even needed, because ususally
the device (like SDIO flash memory or wifi controller) is permanently
wired to the controller. There are also systems which have a card detect
line connected to some of the external interrupt lines or the presence
of the card depends on some other actions (like enabling a power
regulator).

This patch adds support for all these cases. The following card
detection methods are possible:

1. internal sdhci host card detect line
2. external event
3. external gpio interrupt
4. no card detect line, controller will poll for the card
5. no card detect line, card is permanently wired to the controller
(once detected host won't poll it any more)

By default, all existing code would use method #1, what is compatible
with the previous version of the driver.

In case of external event, two callbacks must be provided in platdata:
ext_cd_init and ext_cd_cleanup. Both of them get a callback to a
function that notifies the s3c-sdhci host contoller as their argument.
That callback function should be called from the even dispatcher to let
host notice the card insertion/removal.

In case of external gpio interrupt, a gpio pin number must be provided
in platdata (ext_cd_gpio parameter), as well as the information about
the polarity of that gpio pin (ext_cd_gpio_invert). By default
(ext_cd_gpio_invert == 0) gpio value 0 means 'card has been removed',
but this can be changed to 'card has been removed' when
ext_cd_gpio_invert == 1.

This patch adds changes to sdhci-s3c driver.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/mmc/host/sdhci-s3c.c |   75 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 75 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index b67414f..bb04b35 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -18,6 +18,7 @@
 #include <linux/slab.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
 
 #include <linux/mmc/host.h>
 
@@ -44,6 +45,8 @@ struct sdhci_s3c {
 	struct resource		*ioarea;
 	struct s3c_sdhci_platdata *pdata;
 	unsigned int		cur_clk;
+	int			ext_cd_irq;
+	int			ext_cd_gpio;
 
 	struct clk		*clk_io;
 	struct clk		*clk_bus[MAX_BUS_CLK];
@@ -242,6 +245,39 @@ static struct sdhci_ops sdhci_s3c_ops = {
 	.get_min_clock		= sdhci_s3c_get_min_clock,
 };
 
+static void sdhci_s3c_notify_change(struct platform_device *dev, int state)
+{
+	struct sdhci_host *host;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	host = platform_get_drvdata(dev);
+	if (host) {
+		if (state) {
+			dev_dbg(&dev->dev, "card inserted.\n");
+			host->flags &= ~SDHCI_DEVICE_DEAD;
+			host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+			tasklet_schedule(&host->card_tasklet);
+		} else {
+			dev_dbg(&dev->dev, "card removed.\n");
+			host->flags |= SDHCI_DEVICE_DEAD;
+			host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+			tasklet_schedule(&host->card_tasklet);
+		}
+	}
+	local_irq_restore(flags);
+}
+
+static irqreturn_t sdhci_s3c_gpio_card_detect_isr(int irq, void *dev_id)
+{
+	struct sdhci_s3c *sc = dev_id;
+	int status = gpio_get_value(sc->ext_cd_gpio);
+	if (sc->pdata->ext_cd_gpio_invert)
+		status = !status;
+	sdhci_s3c_notify_change(sc->pdev, status);
+	return IRQ_HANDLED;
+}
+
 static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 {
 	struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
@@ -279,6 +315,7 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	sc->host = host;
 	sc->pdev = pdev;
 	sc->pdata = pdata;
+	sc->ext_cd_gpio = -1;
 
 	platform_set_drvdata(pdev, host);
 
@@ -361,6 +398,13 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	 * SDHCI block, or a missing configuration that needs to be set. */
 	host->quirks |= SDHCI_QUIRK_NO_BUSY_IRQ;
 
+	if (pdata->cd_type == S3C_SDHCI_CD_NONE ||
+	    pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
+		host->quirks |= SDHCI_QUIRK_BROKEN_CARD_DETECTION;
+
+	if (pdata->cd_type == S3C_SDHCI_CD_PERMANENT)
+		host->mmc->caps = MMC_CAP_NONREMOVABLE;
+
 	host->quirks |= (SDHCI_QUIRK_32BIT_DMA_ADDR |
 			 SDHCI_QUIRK_32BIT_DMA_SIZE);
 
@@ -370,6 +414,27 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 		goto err_add_host;
 	}
 
+	/* pdata->ext_cd_init might call sdhci_s3c_notify_change immediately,
+	   so it can be called only after sdhci_add_host() */
+	if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_init)
+		pdata->ext_cd_init(&sdhci_s3c_notify_change);
+
+	if (pdata->cd_type == S3C_SDHCI_CD_GPIO &&
+	    gpio_is_valid(pdata->ext_cd_gpio)) {
+
+		gpio_request(pdata->ext_cd_gpio, "SDHCI EXT CD");
+		sc->ext_cd_gpio = pdata->ext_cd_gpio;
+
+		sc->ext_cd_irq = gpio_to_irq(pdata->ext_cd_gpio);
+		if (sc->ext_cd_irq &&
+		    request_irq(sc->ext_cd_irq, sdhci_s3c_gpio_card_detect_isr,
+				IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+				dev_name(&pdev->dev), sc)) {
+			dev_err(&pdev->dev, "cannot request irq for card detect\n");
+			sc->ext_cd_irq = 0;
+		}
+	}
+
 	return 0;
 
  err_add_host:
@@ -394,10 +459,20 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 
 static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
 {
+	struct s3c_sdhci_platdata *pdata = pdev->dev.platform_data;
 	struct sdhci_host *host =  platform_get_drvdata(pdev);
 	struct sdhci_s3c *sc = sdhci_priv(host);
 	int ptr;
 
+	if (pdata->cd_type == S3C_SDHCI_CD_EXTERNAL && pdata->ext_cd_cleanup)
+		pdata->ext_cd_cleanup(&sdhci_s3c_notify_change);
+
+	if (sc->ext_cd_irq)
+		free_irq(sc->ext_cd_irq, sdhci_s3c_gpio_card_detect_isr);
+
+	if (sc->ext_cd_gpio != -1)
+		gpio_free(sc->ext_cd_gpio);
+
 	sdhci_remove_host(host, 1);
 
 	for (ptr = 0; ptr < 3; ptr++) {
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun 16 02:49:54 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 08:49:54 +0200
Subject: [PATCH 1/3] sdhci-s3c: add missing remove function
In-Reply-To: <1276670996-17729-1-git-send-email-m.szyprowski@samsung.com>
References: <1276670996-17729-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276670996-17729-2-git-send-email-m.szyprowski@samsung.com>

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/mmc/host/sdhci-s3c.c |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index af21792..ad30f07 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -365,6 +365,26 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 
 static int __devexit sdhci_s3c_remove(struct platform_device *pdev)
 {
+	struct sdhci_host *host =  platform_get_drvdata(pdev);
+	struct sdhci_s3c *sc = sdhci_priv(host);
+	int ptr;
+
+	sdhci_remove_host(host, 1);
+
+	for (ptr = 0; ptr < 3; ptr++) {
+		clk_disable(sc->clk_bus[ptr]);
+		clk_put(sc->clk_bus[ptr]);
+	}
+	clk_disable(sc->clk_io);
+	clk_put(sc->clk_io);
+
+	iounmap(host->ioaddr);
+	release_resource(sc->ioarea);
+	kfree(sc->ioarea);
+
+	sdhci_free_host(host);
+	platform_set_drvdata(pdev, NULL);
+
 	return 0;
 }
 
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun 16 02:49:55 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 08:49:55 +0200
Subject: [PATCH 2/3] sdhci-s3c: add support for the non standard minimal clock
	value
In-Reply-To: <1276670996-17729-1-git-send-email-m.szyprowski@samsung.com>
References: <1276670996-17729-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1276670996-17729-3-git-send-email-m.szyprowski@samsung.com>

S3C SDHCI host controller can change the source for generating mmc clock.
By default host bus clock is used, what causes some problems on machines
with 133MHz bus, because the SDHCI divider cannot be as high get proper
clock value for identification mode. This is not a problem for the
controller, because it can generate lower frequencies from other clock
sources. This patch adds a new quirk to SDHCI driver to calculate the
minimal supported clock frequency.

This fixes the flood of the following warnings on Samsung S5PV210 SoCs:
mmc0: Minimum clock frequency too high for identification mode

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/mmc/host/sdhci-of-esdhc.c |    1 +
 drivers/mmc/host/sdhci-s3c.c      |   29 +++++++++++++++++++++++++++++
 drivers/mmc/host/sdhci.c          |    2 +-
 drivers/mmc/host/sdhci.h          |    2 ++
 4 files changed, 33 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index c8623de..64b3f79 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -124,6 +124,7 @@ struct sdhci_of_data sdhci_esdhc = {
 		  SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 		  SDHCI_QUIRK_NO_BUSY_IRQ |
 		  SDHCI_QUIRK_NONSTANDARD_CLOCK |
+		  SDHCI_QUIRK_NONSTANDARD_MINCLOCK |
 		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 		  SDHCI_QUIRK_PIO_NEEDS_DELAY |
 		  SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET |
diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c
index ad30f07..b67414f 100644
--- a/drivers/mmc/host/sdhci-s3c.c
+++ b/drivers/mmc/host/sdhci-s3c.c
@@ -209,10 +209,37 @@ static void sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock)
 	}
 }
 
+/**
+ * sdhci_s3c_get_min_clock - callback to get minimal supported clock value
+ * @host: The SDHCI host being queried
+ *
+ * To init mmc host properly a minimal clock value is needed. For high system
+ * bus clock's values the standard formula gives values out of allowed range.
+ * The clock still can be set to lower values, if clock source other then
+ * system bus is selected.
+*/
+static unsigned int sdhci_s3c_get_min_clock(struct sdhci_host *host)
+{
+	struct sdhci_s3c *ourhost = to_s3c(host);
+	unsigned int delta, min = UINT_MAX;
+	int src;
+
+	for (src = 0; src < MAX_BUS_CLK; src++) {
+		delta = sdhci_s3c_consider_clock(ourhost, src, 0);
+		if (delta == UINT_MAX)
+			continue;
+		/* delta is a negative value in this case */
+		if (-delta < min)
+			min = -delta;
+	}
+	return min;
+}
+
 static struct sdhci_ops sdhci_s3c_ops = {
 	.get_max_clock		= sdhci_s3c_get_max_clk,
 	.get_timeout_clock	= sdhci_s3c_get_timeout_clk,
 	.set_clock		= sdhci_s3c_set_clock,
+	.get_min_clock		= sdhci_s3c_get_min_clock,
 };
 
 static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
@@ -316,6 +343,8 @@ static int __devinit sdhci_s3c_probe(struct platform_device *pdev)
 	host->quirks = 0;
 	host->irq = irq;
 
+	host->quirks |= SDHCI_QUIRK_NONSTANDARD_MINCLOCK;
+
 	/* Setup quirks for the controller */
 	host->quirks |= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
 
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index c6d1bd8..8b3ee53 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -1785,7 +1785,7 @@ int sdhci_add_host(struct sdhci_host *host)
 	 * Set host parameters.
 	 */
 	mmc->ops = &sdhci_ops;
-	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK &&
+	if (host->quirks & SDHCI_QUIRK_NONSTANDARD_MINCLOCK &&
 			host->ops->set_clock && host->ops->get_min_clock)
 		mmc->f_min = host->ops->get_min_clock(host);
 	else
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index c846813..3fd87c2 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -240,6 +240,8 @@ struct sdhci_host {
 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN		(1<<25)
 /* Controller cannot support End Attribute in NOP ADMA descriptor */
 #define SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC		(1<<26)
+/* Controller has nonstandard clock management */
+#define SDHCI_QUIRK_NONSTANDARD_MINCLOCK		(1<<27)
 
 	int			irq;		/* Device IRQ */
 	void __iomem *		ioaddr;		/* Mapped address */
-- 
1.7.1.240.g225c



From richardcochran at gmail.com  Wed Jun 16 02:54:35 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Wed, 16 Jun 2010 08:54:35 +0200
Subject: [PATCH 11/12] ptp: Added a clock driver for the IXP46x.
In-Reply-To: <AANLkTinPDaWNvUG8q8RdvRUga-qrPlSV2H5TkzVVMaFn@mail.gmail.com>
References: <cover.1276615626.git.richard.cochran@omicron.at>
	<0c03ef3e283c6b3ef58feaf1f77ccb0fd605010b.1276615626.git.richard.cochran@omicron.at>
	<AANLkTinPDaWNvUG8q8RdvRUga-qrPlSV2H5TkzVVMaFn@mail.gmail.com>
Message-ID: <20100616065435.GE2887@riccoc20.at.omicron.at>

On Tue, Jun 15, 2010 at 12:41:56PM -0600, Grant Likely wrote:
> Nitpick.  We use all lower case names for structures in Linux.

Yes, I know, but in this case an exception makes sense.

I prefer to use the exact same register mnemonics as in the hardware
documentation, whenever possible. That way, anyone later working on
the driver with hardware manual in hand (and they should be doing that
way) will immediately see the connection.

> You want to get stuff as fast as possible, but there is a udelay()
> that just chews up CPU time.  Would cpu_relax() be sufficient with a
> time-based exit condition in the loop?

I am not sure. What does cpu_relax() do exactly, and when is it safe
to call?

Thanks,
Richard


From s.hauer at pengutronix.de  Wed Jun 16 02:55:40 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 16 Jun 2010 08:55:40 +0200
Subject: [PATCH 1/2] mxc: add common debug board for 3-stack platforms
In-Reply-To: <1276352707-8199-2-git-send-email-jason77.wang@gmail.com>
References: <1276352707-8199-1-git-send-email-jason77.wang@gmail.com>
	<1276352707-8199-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <20100616065540.GI20799@pengutronix.de>

On Sat, Jun 12, 2010 at 10:25:06PM +0800, Jason Wang wrote:
> The debug board is little different for all mxc 3-stack(PDK)
> platforms, it is possible here to add a common implementation to
> support this board.

Two small things left:

Could you change the name cpld_debugboard.c to something like
3ds_debugboard.c? That we are talking about the 3ds is much more
interesting than that there's a cpld on the board.

Also, I really prefer having no extra header file for the debug board.
All information in this header file is only interesting in this single C
file.

Sascha


> 
> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
> ---
>  arch/arm/plat-mxc/Kconfig                        |   11 ++
>  arch/arm/plat-mxc/Makefile                       |    1 +
>  arch/arm/plat-mxc/cpld_debugboard.c              |  161 ++++++++++++++++++++++
>  arch/arm/plat-mxc/include/mach/cpld_debugboard.h |   60 ++++++++
>  4 files changed, 233 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/plat-mxc/cpld_debugboard.c
>  create mode 100644 arch/arm/plat-mxc/include/mach/cpld_debugboard.h
> 
> diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
> index 7f7ad6f..8bf917e 100644
> --- a/arch/arm/plat-mxc/Kconfig
> +++ b/arch/arm/plat-mxc/Kconfig
> @@ -81,6 +81,17 @@ config MXC_PWM
>  	help
>  	  Enable support for the i.MX PWM controller(s).
>  
> +config MXC_DEBUG_BOARD
> +	bool "Enable MXC debug board(for 3-stack)"
> +	help
> +	  The debug board is an integral part of the MXC 3-stack(PDK)
> +	  platforms, it can be attached or removed from the peripheral
> +	  board. On debug board, several debug devices(ethernet, UART,
> +	  buttons, LEDs and JTAG) are implemented. Between the MCU and
> +	  these devices, a CPLD is added as a bridge which performs
> +	  data/address de-multiplexing and decode, signal level shift,
> +	  interrupt control and various board functions.
> +
>  config MXC_ULPI
>  	bool
>  
> diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
> index 895bc3c..b9e8c6f 100644
> --- a/arch/arm/plat-mxc/Makefile
> +++ b/arch/arm/plat-mxc/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
>  obj-$(CONFIG_MXC_ULPI) += ulpi.o
>  obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
>  obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
> +obj-$(CONFIG_MXC_DEBUG_BOARD) += cpld_debugboard.o
>  ifdef CONFIG_SND_IMX_SOC
>  obj-y += ssi-fiq.o
>  obj-y += ssi-fiq-ksym.o
> diff --git a/arch/arm/plat-mxc/cpld_debugboard.c b/arch/arm/plat-mxc/cpld_debugboard.c
> new file mode 100644
> index 0000000..0554fa0
> --- /dev/null
> +++ b/arch/arm/plat-mxc/cpld_debugboard.c
> @@ -0,0 +1,161 @@
> +/*
> + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/io.h>
> +#include <linux/platform_device.h>
> +#include <linux/gpio.h>
> +#include <linux/smsc911x.h>
> +
> +#include <mach/hardware.h>
> +#include <mach/cpld_debugboard.h>
> +
> +static void __iomem *brd_io;
> +static void expio_ack_irq(u32 irq);
> +
> +static struct resource smsc911x_resources[] = {
> +	{
> +		.flags = IORESOURCE_MEM,
> +	} , {
> +		.start = EXPIO_INT_ENET,
> +		.end = EXPIO_INT_ENET,
> +		.flags = IORESOURCE_IRQ,
> +	},
> +};
> +
> +struct smsc911x_platform_config smsc911x_config = {
> +	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
> +	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
> +};
> +
> +struct platform_device smsc_lan9217_device = {
> +	.name = "smsc911x",
> +	.id = 0,
> +	.dev = {
> +		.platform_data = &smsc911x_config,
> +	},
> +	.num_resources = ARRAY_SIZE(smsc911x_resources),
> +	.resource = smsc911x_resources,
> +};
> +
> +static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
> +{
> +	u32 imr_val;
> +	u32 int_valid;
> +	u32 expio_irq;
> +
> +	desc->chip->mask(irq);	/* irq = gpio irq number */
> +
> +	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
> +	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
> +
> +	expio_irq = MXC_BOARD_IRQ_START;
> +	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
> +		struct irq_desc *d;
> +		if ((int_valid & 1) == 0)
> +			continue;
> +		d = irq_desc + expio_irq;
> +		if (unlikely(!(d->handle_irq)))
> +			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
> +		else
> +			d->handle_irq(expio_irq, d);
> +	}
> +
> +	desc->chip->ack(irq);
> +	desc->chip->unmask(irq);
> +}
> +
> +/*
> + * Disable an expio pin's interrupt by setting the bit in the imr.
> + * Irq is an expio virtual irq number
> + */
> +static void expio_mask_irq(u32 irq)
> +{
> +	u16 reg;
> +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> +
> +	reg = __raw_readw(brd_io + INTR_MASK_REG);
> +	reg |= (1 << expio);
> +	__raw_writew(reg, brd_io + INTR_MASK_REG);
> +}
> +
> +static void expio_ack_irq(u32 irq)
> +{
> +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> +
> +	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
> +	__raw_writew(0, brd_io + INTR_RESET_REG);
> +	expio_mask_irq(irq);
> +}
> +
> +static void expio_unmask_irq(u32 irq)
> +{
> +	u16 reg;
> +	u32 expio = MXC_IRQ_TO_EXPIO(irq);
> +
> +	reg = __raw_readw(brd_io + INTR_MASK_REG);
> +	reg &= ~(1 << expio);
> +	__raw_writew(reg, brd_io + INTR_MASK_REG);
> +}
> +
> +static struct irq_chip expio_irq_chip = {
> +	.ack = expio_ack_irq,
> +	.mask = expio_mask_irq,
> +	.unmask = expio_unmask_irq,
> +};
> +
> +int __init mxc_expio_init(u32 base, u32 p_irq)
> +{
> +	int i;
> +
> +	brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
> +	if (brd_io == NULL)
> +		return -ENOMEM;
> +
> +	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
> +	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
> +	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
> +		pr_info("3-Stack Debug board not detected\n");
> +		iounmap(brd_io);
> +		brd_io = NULL;
> +		return -ENODEV;
> +	}
> +
> +	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
> +		readw(brd_io + CPLD_CODE_VER_REG));
> +
> +	smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
> +	smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
> +
> +	/*
> +	 * Configure INT line as GPIO input
> +	 */
> +	gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
> +	gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
> +
> +	/* disable the interrupt and clear the status */
> +	__raw_writew(0, brd_io + INTR_MASK_REG);
> +	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
> +	__raw_writew(0, brd_io + INTR_RESET_REG);
> +	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
> +	for (i = MXC_EXP_IO_BASE;
> +	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
> +		set_irq_chip(i, &expio_irq_chip);
> +		set_irq_handler(i, handle_level_irq);
> +		set_irq_flags(i, IRQF_VALID);
> +	}
> +	set_irq_type(p_irq, IRQF_TRIGGER_LOW);
> +	set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
> +
> +	return 0;
> +}
> diff --git a/arch/arm/plat-mxc/include/mach/cpld_debugboard.h b/arch/arm/plat-mxc/include/mach/cpld_debugboard.h
> new file mode 100644
> index 0000000..a1422d2
> --- /dev/null
> +++ b/arch/arm/plat-mxc/include/mach/cpld_debugboard.h
> @@ -0,0 +1,60 @@
> +/*
> + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
> + *
> + *
> + * The code contained herein is licensed under the GNU General Public
> + * License. You may obtain a copy of the GNU General Public License
> + * Version 2 or later at the following locations:
> + *
> + * http://www.opensource.org/licenses/gpl-license.html
> + * http://www.gnu.org/copyleft/gpl.html
> + */
> +
> +#ifndef __ASM_ARCH_MXC_CPLD_DB_H__
> +#define __ASM_ARCH_MXC_CPLD_DB_H__
> +
> +/* LAN9217 ethernet base address */
> +#define LAN9217_BASE_ADDR(n)	(n + 0x0)
> +/* External UART */
> +#define UARTA_BASE_ADDR(n)	(n + 0x8000)
> +#define UARTB_BASE_ADDR(n)	(n + 0x10000)
> +
> +#define BOARD_IO_ADDR(n)	(n + 0x20000)
> +/* LED switchs */
> +#define LED_SWITCH_REG		0x00
> +/* buttons */
> +#define SWITCH_BUTTONS_REG	0x08
> +/* status, interrupt */
> +#define INTR_STATUS_REG	0x10
> +#define INTR_MASK_REG		0x38
> +#define INTR_RESET_REG		0x20
> +/* magic word for debug CPLD */
> +#define MAGIC_NUMBER1_REG	0x40
> +#define MAGIC_NUMBER2_REG	0x48
> +/* CPLD code version */
> +#define CPLD_CODE_VER_REG	0x50
> +/* magic word for debug CPLD */
> +#define MAGIC_NUMBER3_REG	0x58
> +/* module reset register*/
> +#define MODULE_RESET_REG	0x60
> +/* CPU ID and Personality ID */
> +#define MCU_BOARD_ID_REG	0x68
> +
> +#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
> +#define MXC_IRQ_TO_GPIO(irq)	((irq) - MXC_INTERNAL_IRQS)
> +
> +#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
> +#define MXC_MAX_EXP_IO_LINES	16
> +
> +/* interrupts like external uart , external ethernet etc*/
> +#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
> +#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
> +#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
> +#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
> +#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
> +
> +extern struct platform_device smsc_lan9217_device;
> +
> +int __init mxc_expio_init(u32 base, u32 p_irq);
> +
> +#endif /* __ASM_ARCH_MXC_CPLD_DB_H__ */
> -- 
> 1.5.6.5
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Jun 16 02:57:08 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 16 Jun 2010 08:57:08 +0200
Subject: [PATCH 2/2] mx31_3ds: revert cpld debug board relate code
In-Reply-To: <1276352707-8199-3-git-send-email-jason77.wang@gmail.com>
References: <1276352707-8199-1-git-send-email-jason77.wang@gmail.com>
	<1276352707-8199-2-git-send-email-jason77.wang@gmail.com>
	<1276352707-8199-3-git-send-email-jason77.wang@gmail.com>
Message-ID: <20100616065708.GJ20799@pengutronix.de>


[Added Magnus to Cc]

Magnus,

As you are the original author of the removed code, can I have you
Acked-by or Tested-by here?

Sascha

On Sat, Jun 12, 2010 at 10:25:07PM +0800, Jason Wang wrote:
> Because we add a cpld debug board support in mxc level, we remove
> those redudent codes from board level.
> 
> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
> ---
>  arch/arm/mach-mx3/Kconfig                       |    1 +
>  arch/arm/mach-mx3/mach-mx31_3ds.c               |  168 +----------------------
>  arch/arm/plat-mxc/include/mach/board-mx31_3ds.h |   42 ------
>  3 files changed, 4 insertions(+), 207 deletions(-)
> 
> diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
> index 344753f..fd422cf 100644
> --- a/arch/arm/mach-mx3/Kconfig
> +++ b/arch/arm/mach-mx3/Kconfig
> @@ -58,6 +58,7 @@ config MACH_MX31LITE
>  config MACH_MX31_3DS
>  	bool "Support MX31PDK (3DS)"
>  	select ARCH_MX31
> +	select MXC_DEBUG_BOARD
>  	help
>  	  Include support for MX31PDK (3DS) platform. This includes specific
>  	  configurations for the board and its peripherals.
> diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
> index 58e5729..d8af726 100644
> --- a/arch/arm/mach-mx3/mach-mx31_3ds.c
> +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
> @@ -22,7 +22,6 @@
>  #include <linux/clk.h>
>  #include <linux/irq.h>
>  #include <linux/gpio.h>
> -#include <linux/smsc911x.h>
>  #include <linux/platform_device.h>
>  #include <linux/mfd/mc13783.h>
>  #include <linux/spi/spi.h>
> @@ -38,6 +37,7 @@
>  #include <asm/mach/map.h>
>  #include <mach/common.h>
>  #include <mach/board-mx31_3ds.h>
> +#include <mach/cpld_debugboard.h>
>  #include <mach/imx-uart.h>
>  #include <mach/iomux-mx3.h>
>  #include <mach/mxc_nand.h>
> @@ -213,173 +213,11 @@ static struct imxuart_platform_data uart_pdata = {
>  };
>  
>  /*
> - * Support for the SMSC9217 on the Debug board.
> - */
> -
> -static struct smsc911x_platform_config smsc911x_config = {
> -	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
> -	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
> -	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
> -	.phy_interface	= PHY_INTERFACE_MODE_MII,
> -};
> -
> -static struct resource smsc911x_resources[] = {
> -	{
> -		.start		= LAN9217_BASE_ADDR,
> -		.end		= LAN9217_BASE_ADDR + 0xff,
> -		.flags		= IORESOURCE_MEM,
> -	}, {
> -		.start		= EXPIO_INT_ENET,
> -		.end		= EXPIO_INT_ENET,
> -		.flags		= IORESOURCE_IRQ,
> -	},
> -};
> -
> -static struct platform_device smsc911x_device = {
> -	.name		= "smsc911x",
> -	.id		= -1,
> -	.num_resources	= ARRAY_SIZE(smsc911x_resources),
> -	.resource	= smsc911x_resources,
> -	.dev		= {
> -		.platform_data = &smsc911x_config,
> -	},
> -};
> -
> -/*
> - * Routines for the CPLD on the debug board. It contains a CPLD handling
> - * LEDs, switches, interrupts for Ethernet.
> - */
> -
> -static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
> -{
> -	uint32_t imr_val;
> -	uint32_t int_valid;
> -	uint32_t expio_irq;
> -
> -	imr_val = __raw_readw(CPLD_INT_MASK_REG);
> -	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
> -
> -	expio_irq = MXC_EXP_IO_BASE;
> -	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
> -		if ((int_valid & 1) == 0)
> -			continue;
> -		generic_handle_irq(expio_irq);
> -	}
> -}
> -
> -/*
> - * Disable an expio pin's interrupt by setting the bit in the imr.
> - * @param irq           an expio virtual irq number
> - */
> -static void expio_mask_irq(uint32_t irq)
> -{
> -	uint16_t reg;
> -	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
> -
> -	/* mask the interrupt */
> -	reg = __raw_readw(CPLD_INT_MASK_REG);
> -	reg |= 1 << expio;
> -	__raw_writew(reg, CPLD_INT_MASK_REG);
> -}
> -
> -/*
> - * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
> - * @param irq           an expanded io virtual irq number
> - */
> -static void expio_ack_irq(uint32_t irq)
> -{
> -	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
> -
> -	/* clear the interrupt status */
> -	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
> -	__raw_writew(0, CPLD_INT_RESET_REG);
> -	/* mask the interrupt */
> -	expio_mask_irq(irq);
> -}
> -
> -/*
> - * Enable a expio pin's interrupt by clearing the bit in the imr.
> - * @param irq           a expio virtual irq number
> - */
> -static void expio_unmask_irq(uint32_t irq)
> -{
> -	uint16_t reg;
> -	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
> -
> -	/* unmask the interrupt */
> -	reg = __raw_readw(CPLD_INT_MASK_REG);
> -	reg &= ~(1 << expio);
> -	__raw_writew(reg, CPLD_INT_MASK_REG);
> -}
> -
> -static struct irq_chip expio_irq_chip = {
> -	.ack = expio_ack_irq,
> -	.mask = expio_mask_irq,
> -	.unmask = expio_unmask_irq,
> -};
> -
> -static int __init mx31_3ds_init_expio(void)
> -{
> -	int i;
> -	int ret;
> -
> -	/* Check if there's a debug board connected */
> -	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
> -	    (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
> -	    (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
> -		/* No Debug board found */
> -		return -ENODEV;
> -	}
> -
> -	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
> -		__raw_readw(CPLD_CODE_VER_REG));
> -
> -	/*
> -	 * Configure INT line as GPIO input
> -	 */
> -	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
> -	if (ret)
> -		pr_warning("could not get LAN irq gpio\n");
> -	else
> -		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
> -
> -	/* Disable the interrupts and clear the status */
> -	__raw_writew(0, CPLD_INT_MASK_REG);
> -	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
> -	__raw_writew(0, CPLD_INT_RESET_REG);
> -	__raw_writew(0x1F, CPLD_INT_MASK_REG);
> -	for (i = MXC_EXP_IO_BASE;
> -	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
> -	     i++) {
> -		set_irq_chip(i, &expio_irq_chip);
> -		set_irq_handler(i, handle_level_irq);
> -		set_irq_flags(i, IRQF_VALID);
> -	}
> -	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
> -	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
> -
> -	return 0;
> -}
> -
> -/*
> - * This structure defines the MX31 memory map.
> - */
> -static struct map_desc mx31_3ds_io_desc[] __initdata = {
> -	{
> -		.virtual = MX31_CS5_BASE_ADDR_VIRT,
> -		.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
> -		.length = MX31_CS5_SIZE,
> -		.type = MT_DEVICE,
> -	},
> -};
> -
> -/*
>   * Set up static virtual mappings.
>   */
>  static void __init mx31_3ds_map_io(void)
>  {
>  	mx31_map_io();
> -	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
>  }
>  
>  /*!
> @@ -402,8 +240,8 @@ static void __init mxc_board_init(void)
>  	mx31_3ds_usbotg_init();
>  	mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
>  
> -	if (!mx31_3ds_init_expio())
> -		platform_device_register(&smsc911x_device);
> +	if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
> +		platform_device_register(&smsc_lan9217_device);
>  }
>  
>  static void __init mx31_3ds_timer_init(void)
> diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
> index da92933..c26d88d 100644
> --- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
> +++ b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
> @@ -12,48 +12,6 @@
>  #define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
>  
>  /* Definitions for components on the Debug board */
> -
> -/* Base address of CPLD controller on the Debug board */
> -#define DEBUG_BASE_ADDRESS		CS5_IO_ADDRESS(CS5_BASE_ADDR)
> -
> -/* LAN9217 ethernet base address */
> -#define LAN9217_BASE_ADDR		CS5_BASE_ADDR
> -
> -/* CPLD config and interrupt base address */
> -#define CPLD_ADDR			(DEBUG_BASE_ADDRESS + 0x20000)
> -
> -/* LED switchs */
> -#define CPLD_LED_REG			(CPLD_ADDR + 0x00)
> -/* buttons */
> -#define CPLD_SWITCH_BUTTONS_REG	(EXPIO_ADDR + 0x08)
> -/* status, interrupt */
> -#define CPLD_INT_STATUS_REG		(CPLD_ADDR + 0x10)
> -#define CPLD_INT_MASK_REG		(CPLD_ADDR + 0x38)
> -#define CPLD_INT_RESET_REG		(CPLD_ADDR + 0x20)
> -/* magic word for debug CPLD */
> -#define CPLD_MAGIC_NUMBER1_REG		(CPLD_ADDR + 0x40)
> -#define CPLD_MAGIC_NUMBER2_REG		(CPLD_ADDR + 0x48)
> -/* CPLD code version */
> -#define CPLD_CODE_VER_REG		(CPLD_ADDR + 0x50)
> -/* magic word for debug CPLD */
> -#define CPLD_MAGIC_NUMBER3_REG		(CPLD_ADDR + 0x58)
> -/* module reset register */
> -#define CPLD_MODULE_RESET_REG		(CPLD_ADDR + 0x60)
> -/* CPU ID and Personality ID */
> -#define CPLD_MCU_BOARD_ID_REG		(CPLD_ADDR + 0x68)
> -
> -/* CPLD IRQ line for external uart, external ethernet etc */
>  #define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
>  
> -#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
> -#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)
> -
> -#define EXPIO_INT_ENET		(MXC_EXP_IO_BASE + 0)
> -#define EXPIO_INT_XUART_A	(MXC_EXP_IO_BASE + 1)
> -#define EXPIO_INT_XUART_B	(MXC_EXP_IO_BASE + 2)
> -#define EXPIO_INT_BUTTON_A	(MXC_EXP_IO_BASE + 3)
> -#define EXPIO_INT_BUTTON_B	(MXC_EXP_IO_BASE + 4)
> -
> -#define MXC_MAX_EXP_IO_LINES	16
> -
>  #endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
> -- 
> 1.5.6.5
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From imp at bsdimp.com  Wed Jun 16 02:52:37 2010
From: imp at bsdimp.com (M. Warner Losh)
Date: Wed, 16 Jun 2010 00:52:37 -0600 (MDT)
Subject: Request review of device tree documentation
In-Reply-To: <4C187013.5000400@firmworks.com>
References: <4C186B7B.1060308@firmworks.com> <4C186C72.2020506@compulab.co.il>
	<4C187013.5000400@firmworks.com>
Message-ID: <20100616.005237.338122493954307067.imp@bsdimp.com>

In message: <4C187013.5000400 at firmworks.com>
            Mitch Bradley <wmb at firmworks.com> writes:
: Mike Rapoport wrote:
: > Mitch Bradley wrote:
: >> Mike Rapoport wrote:
: >>> Mitch Bradley wrote:
: >>>
: >>>> The second topic is the hypothetical use of OFW as a HAL. That will
: >>>> not happen for several reasons.  The opposition to the idea is
: >>>> widespread and deeply held, and there are good arguments to support
: >>>> that opposition.  Furthermore, the economic conditions necessary for
: >>>> the creation of such a HAL do not exist in the ARM world, nor indeed
: >>>> in the Linux world in general.  (The necessary condition is the
: >>>> ability for one company to impose a substantial change by fiat -
: >>>> essentially a monopoly position.)
: >>>>
: >>>> Shall we agree, then, that any further discussion of the HAL issue is
: >>>> "just for fun", and that nobody needs to feel threatened that it would
: >>>> actually happen?
: >>>
: >>> I've recently worked with vendor versions of U-Boot for advanced ARM
: >>> SoCs. There is already *huge* chunk of HAL code in those versions. And
: >>> if there would be possibility to have callbacks into the firmware
: >>> these chunks would only grow, IMHO.
: >>
: >> How can there be HAL code in U-Boot unless there is already the
: >> possibility to have callbacks into the firmware?
: >
: > Currently it aims to abstract hardware from U-Boot and reuse the same
: > HW access code across operating systems and bootloaders. If this code
: > would have callbacks I afraid the things would became worse.
: 
: The only way I can understand what you said is if I assume that by
: "callback", you mean the following sequence:
: 
: a) U-boot loads and executes the OS, providing to the OS the address
: of some HW access routines that it can use
: b) The OS calls one of those HW access routines
: c) During the execution of that HW access routine, that routine calls
: "back" into the OS, before returning.  So a call into the OS is nested
: inside a call into U-boot resident code.
: 
: If that is what you are worried about, it is not what we were
: discussing.  We were discussing - and many people were against - step
: (b).
: 
: Are you saying that step (b) - the OS calling into routines provided
: by U-Boot - is already the status quo?

I don't know about status quo, but it certainly is supported.  There's
an option to allow for a secondary boot loader, such as FreeBSD's
/boot/loader, to call back into uboot to read things from
flash/disk/whatever, do network access, etc.  Not so much a HAL, but
more of an echo of the functionality provided by PC BIOS functions.
/boot/loader can be viewed as a mini OS that calls back into uboot to
have it do things.  Once /boot/loader loads FreeBSD, btw, it and uboot
disappear from the scene, so this isn't exactly a HAL situation...

Warner


: >
: >> It is not HAL if it can't be called.
: >>
: >>>
: >>>
: >>>> The potential for "vendors breaking out of the debugging use case and
: >>>> turning it into a HAL" is miniscule, because
: >>>>
: >>>> a) The callback is disabled by default
: >>>> b) The technical challenges of the callback interface limit its
: >>>> applicability to specific "wizard user" scenarios
: >>>> c) OFW is unlikely to achieve sufficient market penetration for the
: >>>> HAL thing to be worth doing
: >>>>
: >>>>
: >>>> _______________________________________________
: >>>> linux-arm-kernel mailing list
: >>>> linux-arm-kernel at lists.infradead.org
: >>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
: >>>
: >>>
: >
: >
: _______________________________________________
: devicetree-discuss mailing list
: devicetree-discuss at lists.ozlabs.org
: https://lists.ozlabs.org/listinfo/devicetree-discuss
: 
: 


From brl at pcpool00.mathematik.uni-freiburg.de  Wed Jun 16 03:29:55 2010
From: brl at pcpool00.mathematik.uni-freiburg.de (Bernhard R. Link)
Date: Wed, 16 Jun 2010 09:29:55 +0200
Subject: [PATCH] orion/kirkwood: reset PCIe unit on boot
In-Reply-To: <1276029158-22159-1-git-send-email-razzor@kopf-tisch.de>
References: <1276029158-22159-1-git-send-email-razzor@kopf-tisch.de>
Message-ID: <20100616072955.GA12905@pcpool00.mathematik.uni-freiburg.de>

* Olaf Rempel <razzor at kopf-tisch.de> [100615 16:52]:
> Patch found in QNAPs vendor source package, with some cleanups
> (proper defines, shortened max. timeout from 1s to 200ms).
> 
> Without this patch the PCIe SATA controller (Marvell 88sx7042/sata_mv)
> in my QNAP TS-419P (Marvell 88f6281/Kirkwood) stops working after a
> few minutes.
> The symptomes are described in this thread:
> http://marc.info/?l=linux-ide&m=124822863706181&w=2

As far as I can tell, that patch fixes those hangs for me, too.

	Bernhard R. Link


From wmb at firmworks.com  Wed Jun 16 03:40:32 2010
From: wmb at firmworks.com (Mitch Bradley)
Date: Tue, 15 Jun 2010 21:40:32 -1000
Subject: Request review of device tree documentation
In-Reply-To: <4C18738C.4090809@compulab.co.il>
References: <4C13430B.5000907@firmworks.com>	<1276339529.1962.184.camel@pasglop>	<1276339684.1962.186.camel@pasglop>	<4C13B618.1030006@firmworks.com>	<1276383132.1962.195.camel@pasglop>	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>	<4C146F18.9030008@firmworks.com>	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>	<20100614124438.GF9323@yookeroo>	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>	<20100614160201.GD9550@shareable.org>
	<4C165FD1.6080505@firmworks.com> <4C186AA8.4040709@compulab.co.il>
	<4C186B7B.1060308@firmworks.com> <4C186C72.2020506@compulab.co.il>
	<4C187013.5000400@firmworks.com> <4C18738C.4090809@compulab.co.il>
Message-ID: <4C187FF0.5020806@firmworks.com>

Mike Rapoport wrote:
> Mitch Bradley wrote:
>> Mike Rapoport wrote:
>>> Mitch Bradley wrote:
>>>> Mike Rapoport wrote:
>>>>> Mitch Bradley wrote:
>>>>>
>>>>>> The second topic is the hypothetical use of OFW as a HAL. That 
>>>>>> will not happen for several reasons.  The opposition to the idea 
>>>>>> is widespread and deeply held, and there are good arguments to 
>>>>>> support that opposition.   Furthermore, the economic conditions 
>>>>>> necessary for the creation of such a HAL do not exist in the ARM 
>>>>>> world, nor indeed in the Linux world in general.  (The necessary 
>>>>>> condition is the ability for one company to impose a substantial 
>>>>>> change by fiat - essentially a monopoly position.)
>>>>>>
>>>>>> Shall we agree, then, that any further discussion of the HAL 
>>>>>> issue is "just for fun", and that nobody needs to feel threatened 
>>>>>> that it would actually happen?
>>>>>
>>>>> I've recently worked with vendor versions of U-Boot for advanced 
>>>>> ARM SoCs. There is already *huge* chunk of HAL code in those 
>>>>> versions. And if there would be possibility to have callbacks into 
>>>>> the firmware these chunks would only grow, IMHO.
>>>>
>>>> How can there be HAL code in U-Boot unless there is already the 
>>>> possibility to have callbacks into the firmware?
>>>
>>> Currently it aims to abstract hardware from U-Boot and reuse the 
>>> same HW access code across operating systems and bootloaders. If 
>>> this code would have callbacks I afraid the things would became worse.
>>
>> The only way I can understand what you said is if I assume that by 
>> "callback", you mean the following sequence:
>>
>> a) U-boot loads and executes the OS, providing to the OS the address 
>> of some HW access routines that it can use
>> b) The OS calls one of those HW access routines
>> c) During the execution of that HW access routine, that routine calls 
>> "back" into the OS, before returning.  So a call into the OS is 
>> nested inside a call into U-boot resident code.
>>
>> If that is what you are worried about, it is not what we were 
>> discussing.  We were discussing - and many people were against - step 
>> (b).
>>
>> Are you saying that step (b) - the OS calling into routines provided 
>> by U-Boot - is already the status quo?
>
> I'm also objecting the step (b) and, fortunately, it's not yet the 
> status quo.
> Current U-Boot/kernel implementations I've encountered still do not 
> have OS calls to resident HW access routines. But if such calls would 
> be allowed, my impression is that SoC vendors would make extensive use 
> of them.

One could argue that a feature that vendors would use extensively is one 
that is sorely needed from their point of view.

One counterargument, of course, is that "there is a better way".  But it 
is only "better" under a cost function that values things differently 
than the vendors value them.  Were that not so, the vendors would gladly 
use the "better" way and not be tempted to use the objectionable 
feature. (Unless, of course, the vendors are just ignorant or unskilled 
- but I generally find that different cost functions cause more 
disconnects than lack of ability.)

Which of course raises the question:  How does the Linux community view 
such SoC vendors?  Are they embraced and eagerly supported, or (either 
openly or secretly) viewed as a nuisance?  How does the widespread 
objection to something that such vendors "would make extensive use of" 
mesh with that view?

>
>>>
>>>> It is not HAL if it can't be called.
>>>>
>>>>>
>>>>>
>>>>>> The potential for "vendors breaking out of the debugging use case 
>>>>>> and turning it into a HAL" is miniscule, because
>>>>>>
>>>>>> a) The callback is disabled by default
>>>>>> b) The technical challenges of the callback interface limit its 
>>>>>> applicability to specific "wizard user" scenarios
>>>>>> c) OFW is unlikely to achieve sufficient market penetration for 
>>>>>> the HAL thing to be worth doing
>>>>>>
>>>>>>
>>>>>> _______________________________________________
>>>>>> linux-arm-kernel mailing list
>>>>>> linux-arm-kernel at lists.infradead.org
>>>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>>>
>>>>>
>>>
>>>
>
>


From jy0922.shim at samsung.com  Wed Jun 16 04:17:32 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Wed, 16 Jun 2010 17:17:32 +0900
Subject: [PATCH v4 3/3] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <1276243728-17704-3-git-send-email-jy0922.shim@samsung.com>
References: <1276243728-17704-1-git-send-email-jy0922.shim@samsung.com>
	<1276243728-17704-3-git-send-email-jy0922.shim@samsung.com>
Message-ID: <4C18889C.2030501@samsung.com>

On 6/11/2010 5:08 PM, Joonyoung Shim wrote:
> This patch adds support for keypad driver running on Samsung cpus. This
> driver is tested on GONI and Aquila board using S5PC110 cpu.
> 
> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  drivers/input/keyboard/Kconfig          |    9 +
>  drivers/input/keyboard/Makefile         |    1 +
>  drivers/input/keyboard/samsung-keypad.c |  400 +++++++++++++++++++++++++++++++
>  3 files changed, 410 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/input/keyboard/samsung-keypad.c
> 

Hi,

Dmitry and Kukjin, any feedback on this?





From jpihet at mvista.com  Wed Jun 16 04:29:35 2010
From: jpihet at mvista.com (Jean Pihet)
Date: Wed, 16 Jun 2010 10:29:35 +0200
Subject: [PATCH] OMAP3: pmu: make CPU_HAS_PMU dependent on OMAP3_EMU
In-Reply-To: <1274972448-10721-1-git-send-email-will.deacon@arm.com>
References: <1274972448-10721-1-git-send-email-will.deacon@arm.com>
Message-ID: <AANLkTikIiLybBr-wV_SRWFNLkZn892gwsWHCxsIYenFJ@mail.gmail.com>

Hi Will,

Sorry for the late reply. Here below are the test results.
Re-sending in plain text only, sorry for the inconvenience.

On Thu, May 27, 2010 at 17:00, Will Deacon <will.deacon at arm.com> wrote:
> CPU performance event counters on v7 cores will only operate
> if either the NIDEN or DBGEN signals are driven high.
>
> For the OMAP3 platform, these signals are driven low by default [i.e.
> when a JTAG debugger is not connected] but DBGEN can be asserted in
> software by selecting the OMAP3_EMU Kconfig option, which enables the
> virtual clock for hardware debugging peripherals.
>
> This patch makes CPU_HAS_PMU depend on OMAP3_EMU for OMAP3 platforms.
>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Jean Pihet <jpihet at mvista.com>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ---
>
> Since I don't have an OMAP3 board to test this on I would appreciate
> it if somebody with some hardware could (a) confirm that this problem
> exists and (b) validate that this patch solves the issue. Thanks!
>
>  arch/arm/Kconfig |    3 ++-
>  1 files changed, 2 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 1f254bd..98922f7 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -955,7 +955,8 @@ config XSCALE_PMU
>        default y
>
>  config CPU_HAS_PMU
> -       depends on CPU_V6 || CPU_V7 || XSCALE_PMU
> +       depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
> +                  (!ARCH_OMAP3 || OMAP3_EMU)
>        default y
>        bool
>
> --
> 1.6.3.3
>
>

The patch nicely fixes the issue. Tested with Oprofile on OMAP3530
EVM. RETention and OFF power modes succesfully tested.

Acked-by: Jean Pihet <jpihet at mvista.com>

Regards,
Jean


From will.deacon at arm.com  Wed Jun 16 05:12:34 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 16 Jun 2010 10:12:34 +0100
Subject: [RFC PATCH 0/4] ARM: add support for hw-breakpoints [v3]
In-Reply-To: <1276181997-20677-1-git-send-email-will.deacon@arm.com>
References: <1276181997-20677-1-git-send-email-will.deacon@arm.com>
Message-ID: <000b01cb0d34$0f09ebc0$2d1dc340$@deacon@arm.com>

Hello,

> This is version 3 of the RFC patches originally posted at:
> 
> v1.) http://lists.infradead.org/pipermail/linux-arm-kernel/2010-February/009084.html
> v2.) http://lists.infradead.org/pipermail/linux-arm-kernel/2010-March/011170.html
> 
> Changes from v2 include:
> 	- Based on 2.6.35-rc2
> 	- Updated to use new hw-breakpoint API features
> 	- Addressed some comments from Frederic on LKML
> 	- Complete redesign of the ptrace interface so that it
> 	  follows the ARM ARM (v7) register structure more closely.
> 
> Unfortunately, I've only managed to compile-test this and check that the
> resulting image boots. The main reasons for posting are (a) to support
> current GDB development and (b) to attract comments on the code.

I've managed to do some preliminary testing using the GDB work
in progress and found a few coding howlers. Rather than submit
a new patchset, I'll keep an up-to-date patch series, rebased
against the latest mainline tag here:

http://www.linux-arm.org/git?p=linux-2.6-wd.git;a=shortlog;h=refs/heads/hw-breakpoint

Once the GDB work is complete, I'll submit v4 to this list.

Cheers,

Will





From linux at arm.linux.org.uk  Wed Jun 16 05:19:31 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 16 Jun 2010 10:19:31 +0100
Subject: [PATCH 02/10] arm/zImage: some comments for __armv3_mpu_cache_on
In-Reply-To: <AANLkTiluJns87Cc7Xk4VA-_9nXMNuhfcR2Kwu0A0IevK@mail.gmail.com>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-2-git-send-email-u.kleine-koenig@pengutronix.de>
	<AANLkTiluJns87Cc7Xk4VA-_9nXMNuhfcR2Kwu0A0IevK@mail.gmail.com>
Message-ID: <20100616091931.GA16149@n2100.arm.linux.org.uk>

On Wed, Jun 16, 2010 at 11:16:43AM +0800, Eric Miao wrote:
> > ? ? ? ? ? ? ? ?mrc ? ? p15, 0, r0, c1, c0, 0 ? @ read control reg
> > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?@ .... .... .... WC.M
> > ? ? ? ? ? ? ? ?orr ? ? r0, r0, #0x000d ? ? ? ? @ .... .... .... 11.1
> > + ? ? ? ? ? ? ? /* ?? this overwrites the value constructed above? */
> > ? ? ? ? ? ? ? ?mov ? ? r0, #0
> 
> This does seem to be an error.

If we can't test the removal of that line, we have to assume that the
existing code was tested, and did work.  (It certainly will work, but
slower because the caches would not be on.)  We don't know if removing
this line would cause problems.

I think it's better just to add a comment about it, and leave the code
as-is.

However, if someone has an ARM740T system and can test the removal of
this, then we can remove it.  I suspect that ARM740T systems are rarely
worked on now though - esp. as the whole nommu stuff doesn't seem to
get much attention.


From Hiroshi.DOYU at nokia.com  Wed Jun 16 05:21:41 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Wed, 16 Jun 2010 12:21:41 +0300 (EEST)
Subject: [PATCH v4 00/14] omap: mailbox: bunch of cleanups
In-Reply-To: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
References: <1276271509-11983-1-git-send-email-felipe.contreras@gmail.com>
Message-ID: <20100616.122141.245405863.Hiroshi.DOYU@nokia.com>

From: ext Felipe Contreras <felipe.contreras at gmail.com>
Subject: [PATCH v4 00/14] omap: mailbox: bunch of cleanups
Date: Fri, 11 Jun 2010 17:51:35 +0200

> From: Felipe Contreras <--global>
> 
> Hi,
> 
> These are hopefully non-functional changes. Just shuffling code around, and
> removing unecessary stuff.
> 
> This v4 includes minor changes suggested by Felipe Balbi, Hiroshi, and Russell.
> 
> Comments from Felipe Balbi, Tony Lindgren, Hiroshi DOYU, and Russell King.

Applied against:
  git://gitorious.org/~doyu/lk/mainline.git v2.6.35-rc3-mailbox

Only [PATCH 1/14] isn't used since the original patch is correct but
messed up at applying just in my branch.



From m.szyprowski at samsung.com  Wed Jun 16 05:34:43 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 11:34:43 +0200
Subject: [PATCH v2] Various s3c-fb updates
In-Reply-To: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1276680892-14760-1-git-send-email-m.szyprowski@samsung.com>

Hello,

Im sending a new version of the s3c-fb patch series on behalf of Pawel
Osciak.

This series is rebased onto Ben Dook's framebuffer branch available at:
git://git.fluff.org/bjdooks/linux.git dev/s3c-fb

The main changes are the addition of an ability to wait for VSYNC and
display panning and better support for S5PV210 SoCs. A lot of various
bugs has been also fixed.

The first patch attempts to fix some NULL pointer dereferences in case
of a failed framebuffer memory allocation attempt. This is a quick fix,
so please treat it more as an indication of what may be wrong with the
code in the probe function and not as something to merge.

Patches 3-4 add "new style" device name initialization for various
S3C/S5P devices. The 4th patch also separates S5PC100 and S5PV210 as
their framebuffer registers sets differ.

Patch 7 nd 9 are pure bugfixes.

Patch 8 adds support for the new feature available on S5PV210.

The complete list of patches:
[PATCH 1/9] s3c-fb: Fix various null references on framebuffer memory alloc failure
[PATCH 2/9] s3c-fb: Correct FRAMESEL1 bitfield defines for VIDINTCON0 register
[PATCH 3/9] s3c-fb: Add device name initialization.
[PATCH 4/9] s3c-fb: Separate S5PC100 and S5PV210 framebuffer driver data structures
[PATCH 5/9] s3c-fb: Add support for display panning
[PATCH 6/9] s3c-fb: Add wait for VSYNC ioctl
[PATCH 7/9] s3c-fb: window 3 of 64xx+ does not have an osd_d register
[PATCH 8/9] s3c-fb: Add SHADOWCON shadow register locking support for S5PV210
[PATCH 9/9] s3c-fb: Correct window osd size and alpha register handling

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center


From m.szyprowski at samsung.com  Wed Jun 16 05:34:45 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 11:34:45 +0200
Subject: [PATCH 2/9] s3c-fb: Correct FRAMESEL1 bitfield defines for VIDINTCON0
	register
In-Reply-To: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1276680892-14760-3-git-send-email-m.szyprowski@samsung.com>

From: Pawel Osciak <p.osciak at samsung.com>

FRAMESEL1 bitfield starts on 13th bit, not on 14th.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/plat-samsung/include/plat/regs-fb.h |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index f4259e5..ac10013 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -292,11 +292,11 @@
 #define VIDINTCON0_FRAMESEL0_ACTIVE		(0x2 << 15)
 #define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)
 
-#define VIDINTCON0_FRAMESEL1			(1 << 14)
-#define VIDINTCON0_FRAMESEL1_NONE		(0x0 << 14)
-#define VIDINTCON0_FRAMESEL1_BACKPORCH		(0x1 << 14)
-#define VIDINTCON0_FRAMESEL1_VSYNC		(0x2 << 14)
-#define VIDINTCON0_FRAMESEL1_FRONTPORCH		(0x3 << 14)
+#define VIDINTCON0_FRAMESEL1			(1 << 13)
+#define VIDINTCON0_FRAMESEL1_NONE		(0x0 << 13)
+#define VIDINTCON0_FRAMESEL1_BACKPORCH		(0x1 << 13)
+#define VIDINTCON0_FRAMESEL1_VSYNC		(0x2 << 13)
+#define VIDINTCON0_FRAMESEL1_FRONTPORCH		(0x3 << 13)
 
 #define VIDINTCON0_INT_FRAME			(1 << 12)
 #define VIDINTCON0_FIFIOSEL_MASK		(0x7f << 5)
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun 16 05:34:47 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 11:34:47 +0200
Subject: [PATCH 4/9] s3c-fb: Separate S5PC100 and S5PV210 framebuffer driver
	data structures
In-Reply-To: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1276680892-14760-5-git-send-email-m.szyprowski@samsung.com>

From: Pawel Osciak <p.osciak at samsung.com>

S5PC100 and S5PV210 framebuffer devices differ slightly in terms of
available registers and their driver data structures have to be separate.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 drivers/video/s3c-fb.c |   37 ++++++++++++++++++++++++++++++++++---
 1 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index d998324..59ac76a 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -1251,7 +1251,35 @@ static struct s3c_fb_driverdata s3c_fb_data_64xx __devinitdata = {
 	.win[4]	= &s3c_fb_data_64xx_wins[4],
 };
 
-static struct s3c_fb_driverdata s3c_fb_data_s5p __devinitdata = {
+static struct s3c_fb_driverdata s3c_fb_data_s5pc100 __devinitdata = {
+	.variant = {
+		.nr_windows	= 5,
+		.vidtcon	= VIDTCON0,
+		.wincon		= WINCON(0),
+		.winmap		= WINxMAP(0),
+		.keycon		= WKEYCON,
+		.osd		= VIDOSD_BASE,
+		.osd_stride	= 16,
+		.buf_start	= VIDW_BUF_START(0),
+		.buf_size	= VIDW_BUF_SIZE(0),
+		.buf_end	= VIDW_BUF_END(0),
+
+		.palette = {
+			[0] = 0x2400,
+			[1] = 0x2800,
+			[2] = 0x2c00,
+			[3] = 0x3000,
+			[4] = 0x3400,
+		},
+	},
+	.win[0]	= &s3c_fb_data_64xx_wins[0],
+	.win[1]	= &s3c_fb_data_64xx_wins[1],
+	.win[2]	= &s3c_fb_data_64xx_wins[2],
+	.win[3]	= &s3c_fb_data_64xx_wins[3],
+	.win[4]	= &s3c_fb_data_64xx_wins[4],
+};
+
+static struct s3c_fb_driverdata s3c_fb_data_s5pv210 __devinitdata = {
 	.variant = {
 		.nr_windows	= 5,
 		.vidtcon	= VIDTCON0,
@@ -1319,8 +1347,11 @@ static struct platform_device_id s3c_fb_driver_ids[] = {
 		.name		= "s3c-fb",
 		.driver_data	= (unsigned long)&s3c_fb_data_64xx,
 	}, {
-		.name		= "s5p-fb",
-		.driver_data	= (unsigned long)&s3c_fb_data_s5p,
+		.name		= "s5pc100-fb",
+		.driver_data	= (unsigned long)&s3c_fb_data_s5pc100,
+	}, {
+		.name		= "s5pv210-fb",
+		.driver_data	= (unsigned long)&s3c_fb_data_s5pv210,
 	}, {
 		.name		= "s3c2443-fb",
 		.driver_data	= (unsigned long)&s3c_fb_data_s3c2443,
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun 16 05:34:44 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 11:34:44 +0200
Subject: [PATCH 1/9] s3c-fb: Fix various null references on framebuffer memory
	alloc failure
In-Reply-To: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1276680892-14760-2-git-send-email-m.szyprowski@samsung.com>

From: Pawel Osciak <p.osciak at samsung.com>

The following problems were found in the above situation:

sfb->windows[win] was being assigned at the end of s3c_fb_probe_win only.
This resulted in passing a NULL to s3c_fb_release_win if probe_win returned
early and a memory leak.

dma_free_writecombine does not allow its third argument to be NULL.

fb_dealloc_cmap does not verify whether its argument is not NULL.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 drivers/video/s3c-fb.c |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index b00c064..d998324 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -804,7 +804,8 @@ static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
 {
 	struct fb_info *fbi = win->fbinfo;
 
-	dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
+	if (fbi->screen_base)
+		dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
 			      fbi->screen_base, fbi->fix.smem_start);
 }
 
@@ -819,7 +820,8 @@ static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
 {
 	if (win->fbinfo) {
 		unregister_framebuffer(win->fbinfo);
-		fb_dealloc_cmap(&win->fbinfo->cmap);
+		if (&win->fbinfo->cmap)
+			fb_dealloc_cmap(&win->fbinfo->cmap);
 		s3c_fb_free_memory(sfb, win);
 		framebuffer_release(win->fbinfo);
 	}
@@ -865,6 +867,7 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 	WARN_ON(windata->win_mode.yres == 0);
 
 	win = fbinfo->par;
+	*res = win;
 	var = &fbinfo->var;
 	win->variant = *variant;
 	win->fbinfo = fbinfo;
@@ -939,7 +942,6 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 		return ret;
 	}
 
-	*res = win;
 	dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
 
 	return 0;
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun 16 05:34:46 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 11:34:46 +0200
Subject: [PATCH 3/9] s3c-fb: Add device name initialization.
In-Reply-To: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1276680892-14760-4-git-send-email-m.szyprowski@samsung.com>

From: Pawel Osciak <p.osciak at samsung.com>

Add framebuffer device name initialization calls for S3C2443, S3C64xx
and S5P machines.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/mach-s3c2443/s3c2443.c              |    2 +
 arch/arm/mach-s3c64xx/s3c6400.c              |    3 ++
 arch/arm/mach-s3c64xx/s3c6410.c              |    3 ++
 arch/arm/mach-s5pc100/cpu.c                  |    3 ++
 arch/arm/mach-s5pv210/cpu.c                  |    3 ++
 arch/arm/plat-samsung/include/plat/fb-core.h |   29 ++++++++++++++++++++++++++
 6 files changed, 43 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-samsung/include/plat/fb-core.h

diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index ce2ec32..839b6b2 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -35,6 +35,7 @@
 #include <plat/s3c2443.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/fb-core.h>
 
 static struct map_desc s3c2443_iodesc[] __initdata = {
 	IODESC_ENT(WATCHDOG),
@@ -62,6 +63,7 @@ int __init s3c2443_init(void)
 	s3c24xx_reset_hook = s3c2443_hard_reset;
 
 	s3c_device_nand.name = "s3c2412-nand";
+	s3c_fb_setname("s3c2443-fb");
 
 	/* change WDT IRQ number */
 	s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
diff --git a/arch/arm/mach-s3c64xx/s3c6400.c b/arch/arm/mach-s3c64xx/s3c6400.c
index 5e93fe3..f4a9e07 100644
--- a/arch/arm/mach-s3c64xx/s3c6400.c
+++ b/arch/arm/mach-s3c64xx/s3c6400.c
@@ -38,6 +38,7 @@
 #include <plat/sdhci.h>
 #include <plat/iic-core.h>
 #include <plat/onenand-core.h>
+#include <plat/fb-core.h>
 #include <mach/s3c6400.h>
 
 void __init s3c6400_map_io(void)
@@ -55,6 +56,8 @@ void __init s3c6400_map_io(void)
 
 	s3c_onenand_setname("s3c6400-onenand");
 	s3c64xx_onenand1_setname("s3c6400-onenand");
+
+	s3c_fb_setname("s3c-fb");
 }
 
 void __init s3c6400_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 014401c..b2acb60 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -40,6 +40,7 @@
 #include <plat/iic-core.h>
 #include <plat/adc.h>
 #include <plat/onenand-core.h>
+#include <plat/fb-core.h>
 #include <mach/s3c6400.h>
 #include <mach/s3c6410.h>
 
@@ -58,6 +59,8 @@ void __init s3c6410_map_io(void)
 	s3c_device_nand.name = "s3c6400-nand";
 	s3c_onenand_setname("s3c6410-onenand");
 	s3c64xx_onenand1_setname("s3c6410-onenand");
+
+	s3c_fb_setname("s3c-fb");
 }
 
 void __init s3c6410_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 7b5bdbc..d10276a 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -41,6 +41,7 @@
 #include <plat/iic-core.h>
 #include <plat/sdhci.h>
 #include <plat/onenand-core.h>
+#include <plat/fb-core.h>
 
 #include <plat/s5pc100.h>
 
@@ -92,6 +93,8 @@ void __init s5pc100_map_io(void)
 	s3c_i2c1_setname("s3c2440-i2c");
 
 	s3c_onenand_setname("s5pc100-onenand");
+
+	s3c_fb_setname("s5pc100-fb");
 }
 
 void __init s5pc100_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 411a4a9..4d3580a 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -34,6 +34,7 @@
 #include <plat/s5pv210.h>
 #include <plat/iic-core.h>
 #include <plat/sdhci.h>
+#include <plat/fb-core.h>
 
 /* Initial IO mappings */
 
@@ -91,6 +92,8 @@ void __init s5pv210_map_io(void)
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
 	s3c_i2c2_setname("s3c2440-i2c");
+
+	s3c_fb_setname("s5pv210-fb");
 }
 
 void __init s5pv210_init_clocks(int xtal)
diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/plat-samsung/include/plat/fb-core.h
new file mode 100644
index 0000000..bca383e
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/fb-core.h
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/plat-samsung/include/plat/fb-core.h
+ *
+ * Copyright 2010 Samsung Electronics Co., Ltd.
+ *	Pawel Osciak <p.osciak at samsung.com>
+ *
+ * Samsung framebuffer driver core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PLAT_FB_CORE_H
+#define __ASM_PLAT_FB_CORE_H __FILE__
+
+/*
+ * These functions are only for use with the core support code, such as
+ * the CPU-specific initialization code.
+ */
+
+/* Re-define device name depending on support. */
+static inline void s3c_fb_setname(char *name)
+{
+#ifdef CONFIG_S3C_DEV_FB
+	s3c_device_fb.name = name;
+#endif
+}
+
+#endif /* __ASM_PLAT_FB_CORE_H */
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun 16 05:34:49 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 11:34:49 +0200
Subject: [PATCH 6/9] s3c-fb: Add wait for VSYNC ioctl
In-Reply-To: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1276680892-14760-7-git-send-email-m.szyprowski@samsung.com>

From: Pawel Osciak <p.osciak at samsung.com>

Add VSYNC interrupt support and an ioctl that allows waiting for it.
Interrupts are turned on only when needed.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/plat-samsung/include/plat/regs-fb.h |    1 +
 drivers/video/s3c-fb.c                       |  167 +++++++++++++++++++++++++-
 2 files changed, 167 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index f454e32..5bcdd09 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -298,6 +298,7 @@
 #define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)
 
 #define VIDINTCON0_FRAMESEL1			(1 << 13)
+#define VIDINTCON0_FRAMESEL1_MASK		(0x3 << 13)
 #define VIDINTCON0_FRAMESEL1_NONE		(0x0 << 13)
 #define VIDINTCON0_FRAMESEL1_BACKPORCH		(0x1 << 13)
 #define VIDINTCON0_FRAMESEL1_VSYNC		(0x2 << 13)
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 4f3680d..6131ebb 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -21,6 +21,8 @@
 #include <linux/clk.h>
 #include <linux/fb.h>
 #include <linux/io.h>
+#include <linux/uaccess.h>
+#include <linux/interrupt.h>
 
 #include <mach/map.h>
 #include <plat/regs-fb-v4.h>
@@ -48,6 +50,11 @@
 	__raw_writel(v, r); } while(0)
 #endif /* FB_S3C_DEBUG_REGWRITE */
 
+/* irq_flags bits */
+#define S3C_FB_VSYNC_IRQ_EN	0
+
+#define VSYNC_TIMEOUT_MSEC 50
+
 struct s3c_fb;
 
 #define VALID_BPP(x) (1 << ((x) - 1))
@@ -156,6 +163,16 @@ struct s3c_fb_win {
 };
 
 /**
+ * struct s3c_fb_vsync - vsync information
+ * @wait:	a queue for processes waiting for vsync
+ * @count:	vsync interrupt count
+ */
+struct s3c_fb_vsync {
+	wait_queue_head_t	wait;
+	unsigned int		count;
+};
+
+/**
  * struct s3c_fb - overall hardware state of the hardware
  * @dev: The device that we bound to, for printing, etc.
  * @regs_res: The resource we claimed for the IO registers.
@@ -165,6 +182,9 @@ struct s3c_fb_win {
  * @enabled: A bitmask of enabled hardware windows.
  * @pdata: The platform configuration data passed with the device.
  * @windows: The hardware windows that have been claimed.
+ * @irq_no: IRQ line number
+ * @irq_flags: irq flags
+ * @vsync_info: VSYNC-related information (count, queues...)
  */
 struct s3c_fb {
 	struct device		*dev;
@@ -177,6 +197,10 @@ struct s3c_fb {
 
 	struct s3c_fb_platdata	*pdata;
 	struct s3c_fb_win	*windows[S3C_FB_MAX_WIN];
+
+	int			 irq_no;
+	unsigned long		 irq_flags;
+	struct s3c_fb_vsync	 vsync_info;
 };
 
 /**
@@ -801,6 +825,124 @@ static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
 	return 0;
 }
 
+/**
+ * s3c_fb_enable_irq() - enable framebuffer interrupts
+ * @sfb: main hardware state
+ */
+static void s3c_fb_enable_irq(struct s3c_fb *sfb)
+{
+	void __iomem *regs = sfb->regs;
+	u32 irq_ctrl_reg;
+
+	if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
+		/* IRQ disabled, enable it */
+		irq_ctrl_reg = readl(regs + VIDINTCON0);
+
+		irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
+		irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
+
+		irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
+		irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
+		irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
+		irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
+
+		writel(irq_ctrl_reg, regs + VIDINTCON0);
+	}
+}
+
+/**
+ * s3c_fb_disable_irq() - disable framebuffer interrupts
+ * @sfb: main hardware state
+ */
+static void s3c_fb_disable_irq(struct s3c_fb *sfb)
+{
+	void __iomem *regs = sfb->regs;
+	u32 irq_ctrl_reg;
+
+	if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
+		/* IRQ enabled, disable it */
+		irq_ctrl_reg = readl(regs + VIDINTCON0);
+
+		irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
+		irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
+
+		writel(irq_ctrl_reg, regs + VIDINTCON0);
+	}
+}
+
+static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
+{
+	struct s3c_fb *sfb = dev_id;
+	void __iomem  *regs = sfb->regs;
+	u32 irq_sts_reg;
+
+	irq_sts_reg = readl(regs + VIDINTCON1);
+
+	if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
+
+		/* VSYNC interrupt, accept it */
+		writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
+
+		sfb->vsync_info.count++;
+		wake_up_interruptible(&sfb->vsync_info.wait);
+	}
+
+	/* We only support waiting for VSYNC for now, so it's safe
+	 * to always disable irqs here.
+	 */
+	s3c_fb_disable_irq(sfb);
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
+ * @sfb: main hardware state
+ * @crtc: head index.
+ */
+static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
+{
+	unsigned long count;
+	int ret;
+
+	if (crtc != 0)
+		return -ENODEV;
+
+	s3c_fb_enable_irq(sfb);
+	count = sfb->vsync_info.count;
+	ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
+				       count != sfb->vsync_info.count,
+				       msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));
+	if (ret == 0)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
+			unsigned long arg)
+{
+	struct s3c_fb_win *win = info->par;
+	struct s3c_fb *sfb = win->parent;
+	int ret;
+	u32 crtc;
+
+	switch (cmd) {
+	case FBIO_WAITFORVSYNC:
+		if (get_user(crtc, (u32 __user *)arg)) {
+			ret = -EFAULT;
+			break;
+		}
+
+		ret = s3c_fb_wait_for_vsync(sfb, crtc);
+		break;
+	default:
+		ret = -ENOTTY;
+	}
+
+	return ret;
+}
+
 static struct fb_ops s3c_fb_ops = {
 	.owner		= THIS_MODULE,
 	.fb_check_var	= s3c_fb_check_var,
@@ -811,6 +953,7 @@ static struct fb_ops s3c_fb_ops = {
 	.fb_copyarea	= cfb_copyarea,
 	.fb_imageblit	= cfb_imageblit,
 	.fb_pan_display	= s3c_fb_pan_display,
+	.fb_ioctl	= s3c_fb_ioctl,
 };
 
 /**
@@ -917,6 +1060,8 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 
 	dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
 
+	init_waitqueue_head(&sfb->vsync_info.wait);
+
 	palette_size = variant->palette_sz * 4;
 
 	fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
@@ -1096,6 +1241,20 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev)
 		goto err_req_region;
 	}
 
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(dev, "failed to acquire irq resource\n");
+		ret = -ENOENT;
+		goto err_ioremap;
+	}
+	sfb->irq_no = res->start;
+	ret = request_irq(sfb->irq_no, s3c_fb_irq,
+			  0, "s3c_fb", sfb);
+	if (ret) {
+		dev_err(dev, "irq request failed\n");
+		goto err_ioremap;
+	}
+
 	dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
 
 	/* setup gpio and output polarity controls */
@@ -1130,7 +1289,7 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev)
 			dev_err(dev, "failed to create window %d\n", win);
 			for (; win >= 0; win--)
 				s3c_fb_release_win(sfb, sfb->windows[win]);
-			goto err_ioremap;
+			goto err_irq;
 		}
 	}
 
@@ -1138,6 +1297,9 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev)
 
 	return 0;
 
+err_irq:
+	free_irq(sfb->irq_no, sfb);
+
 err_ioremap:
 	iounmap(sfb->regs);
 
@@ -1170,6 +1332,8 @@ static int __devexit s3c_fb_remove(struct platform_device *pdev)
 		if (sfb->windows[win])
 			s3c_fb_release_win(sfb, sfb->windows[win]);
 
+	free_irq(sfb->irq_no, sfb);
+
 	iounmap(sfb->regs);
 
 	clk_disable(sfb->bus_clk);
@@ -1370,6 +1534,7 @@ static struct s3c_fb_driverdata s3c_fb_data_s5pv210 __devinitdata = {
 			[3] = 0x3000,
 			[4] = 0x3400,
 		},
+
 	},
 	.win[0]	= &s3c_fb_data_64xx_wins[0],
 	.win[1]	= &s3c_fb_data_64xx_wins[1],
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun 16 05:34:48 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 11:34:48 +0200
Subject: [PATCH 5/9] s3c-fb: Add support for display panning
In-Reply-To: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1276680892-14760-6-git-send-email-m.szyprowski@samsung.com>

From: Pawel Osciak <p.osciak at samsung.com>

Supports all bpp modes.

The PRTCON register is used to disable in-hardware updates of registers
that store start and end addresses of framebuffer memory. This prevents
display corruption in case we do not make it before VSYNC with updating
them atomically. With this feature there is no need to wait for a VSYNC
interrupt before each such update.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/plat-samsung/include/plat/regs-fb.h |    5 ++
 drivers/video/s3c-fb.c                       |   71 ++++++++++++++++++++++++++
 2 files changed, 76 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index ac10013..f454e32 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -112,6 +112,11 @@
 #define VIDCON2_ORGYCbCr			(1 << 8)
 #define VIDCON2_YUVORDCrCb			(1 << 7)
 
+/* PRTCON (S3C6410, S5PC100) */
+
+#define PRTCON					(0x0c)
+#define PRTCON_PROTECT				(1 << 11)
+
 /* VIDTCON0 */
 
 #define VIDTCON0_VBPDE_MASK			(0xff << 24)
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 59ac76a..4f3680d 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -71,6 +71,7 @@ struct s3c_fb;
  * @buf_end: Offset of buffer end registers.
  * @osd: The base for the OSD registers.
  * @palette: Address of palette memory, or 0 if none.
+ * @has_prtcon: Set if has PRTCON register.
  */
 struct s3c_fb_variant {
 	unsigned int	is_2443:1;
@@ -85,6 +86,8 @@ struct s3c_fb_variant {
 	unsigned short	osd;
 	unsigned short	osd_stride;
 	unsigned short	palette[S3C_FB_MAX_WIN];
+
+	unsigned int	has_prtcon:1;
 };
 
 /**
@@ -379,6 +382,9 @@ static int s3c_fb_set_par(struct fb_info *info)
 
 	info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
 
+	info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
+	info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
+
 	/* disable the window whilst we update it */
 	writel(0, regs + WINCON(win_no));
 
@@ -735,6 +741,66 @@ static int s3c_fb_blank(int blank_mode, struct fb_info *info)
 	return 0;
 }
 
+/**
+ * s3c_fb_pan_display() - Pan the display.
+ *
+ * Note that the offsets can be written to the device at any time, as their
+ * values are latched at each vsync automatically. This also means that only
+ * the last call to this function will have any effect on next vsync, but
+ * there is no need to sleep waiting for it to prevent tearing.
+ *
+ * @var: The screen information to verify.
+ * @info: The framebuffer device.
+ */
+static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
+			      struct fb_info *info)
+{
+	struct s3c_fb_win *win	= info->par;
+	struct s3c_fb *sfb	= win->parent;
+	void __iomem *buf	= sfb->regs + win->index * 8;
+	unsigned int start_byte_offset, end_byte_offset;
+
+	/* Offset in bytes to the start of the displayed area */
+	start_byte_offset = var->yoffset * info->fix.line_length;
+	/* X offset depends on the current bpp */
+	if (info->var.bits_per_pixel >= 8) {
+		start_byte_offset +=
+			var->xoffset * (info->var.bits_per_pixel >> 3);
+	} else {
+		switch (info->var.bits_per_pixel) {
+		case 4:
+			start_byte_offset += var->xoffset >> 1;
+			break;
+		case 2:
+			start_byte_offset += var->xoffset >> 2;
+			break;
+		case 1:
+			start_byte_offset += var->xoffset >> 3;
+			break;
+		default:
+			dev_err(sfb->dev, "invalid bpp\n");
+			return -EINVAL;
+		}
+	}
+	/* Offset in bytes to the end of the displayed area */
+	end_byte_offset = start_byte_offset + var->yres * info->fix.line_length;
+
+	/* Temporarily turn off per-vsync update from shadow registers until
+	 * both start and end addresses are updated to prevent corruption */
+	if (sfb->variant.has_prtcon)
+		writel(PRTCON_PROTECT, sfb->regs + PRTCON);
+
+	writel(info->fix.smem_start + start_byte_offset,
+		buf + sfb->variant.buf_start);
+	writel(info->fix.smem_start + end_byte_offset,
+		buf + sfb->variant.buf_end);
+
+	if (sfb->variant.has_prtcon)
+		writel(0, sfb->regs + PRTCON);
+
+	return 0;
+}
+
 static struct fb_ops s3c_fb_ops = {
 	.owner		= THIS_MODULE,
 	.fb_check_var	= s3c_fb_check_var,
@@ -744,6 +810,7 @@ static struct fb_ops s3c_fb_ops = {
 	.fb_fillrect	= cfb_fillrect,
 	.fb_copyarea	= cfb_copyarea,
 	.fb_imageblit	= cfb_imageblit,
+	.fb_pan_display	= s3c_fb_pan_display,
 };
 
 /**
@@ -1243,6 +1310,8 @@ static struct s3c_fb_driverdata s3c_fb_data_64xx __devinitdata = {
 			[3] = 0x320,
 			[4] = 0x340,
 		},
+
+		.has_prtcon	= 1,
 	},
 	.win[0]	= &s3c_fb_data_64xx_wins[0],
 	.win[1]	= &s3c_fb_data_64xx_wins[1],
@@ -1271,6 +1340,8 @@ static struct s3c_fb_driverdata s3c_fb_data_s5pc100 __devinitdata = {
 			[3] = 0x3000,
 			[4] = 0x3400,
 		},
+
+		.has_prtcon	= 1,
 	},
 	.win[0]	= &s3c_fb_data_64xx_wins[0],
 	.win[1]	= &s3c_fb_data_64xx_wins[1],
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun 16 05:34:52 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 11:34:52 +0200
Subject: [PATCH 9/9] s3c-fb: Correct window osd size and alpha register
	handling
In-Reply-To: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1276680892-14760-10-git-send-email-m.szyprowski@samsung.com>

From: Pawel Osciak <p.osciak at samsung.com>

S3C64xx and S5P OSD registers for OSD size and alpha are as follows:
VIDOSDC: win 0 - size, win 1-4: alpha
VIDOSDD: win 1-2 - size; not present for windows 0, 3 and 4

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 drivers/video/s3c-fb.c |   58 ++++++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 51 insertions(+), 7 deletions(-)

diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 5e14f0a..f098bd1 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -64,6 +64,9 @@ struct s3c_fb;
 #define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
 #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
 #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
+#define VIDOSD_SIZE(win, variant, win_variant) \
+	(OSD_BASE(win, variant) + (win_variant).osd_size_off)
+#define VIDOSD_ALPHA(win, variant, win_variant) VIDOSD_C(win, variant)
 
 /**
  * struct s3c_fb_variant - fb variant information
@@ -112,7 +115,10 @@ struct s3c_fb_variant {
 struct s3c_fb_win_variant {
 	unsigned int	has_osd_c:1;
 	unsigned int	has_osd_d:1;
+	unsigned int	has_osd_size:1;
+	unsigned int	has_osd_alpha:1;
 	unsigned int	palette_16bpp:1;
+	unsigned short	osd_size_off;
 	unsigned short	palette_sz;
 	u32		valid_bpp;
 };
@@ -365,6 +371,36 @@ static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
 }
 
 /**
+ * vidosd_set_size() - set OSD size for a window
+ *
+ * @win: the window to set OSD size for
+ * @size: OSD size register value
+ */
+static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
+{
+	struct s3c_fb *sfb = win->parent;
+
+	if (win->variant.has_osd_size)
+		writel(size, sfb->regs + VIDOSD_SIZE(win->index, sfb->variant,
+							win->variant));
+}
+
+/**
+ * vidosd_set_alpha() - set alpha transparency for a window
+ *
+ * @win: the window to set OSD size for
+ * @alpha: alpha register value
+ */
+static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
+{
+	struct s3c_fb *sfb = win->parent;
+
+	if (win->variant.has_osd_alpha)
+		writel(alpha, sfb->regs + VIDOSD_ALPHA(win->index,
+						sfb->variant, win->variant));
+}
+
+/**
  * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
  * @info: The framebuffer to change.
  *
@@ -378,7 +414,7 @@ static int s3c_fb_set_par(struct fb_info *info)
 	void __iomem *regs = sfb->regs;
 	void __iomem *buf = regs;
 	int win_no = win->index;
-	u32 osdc_data = 0;
+	u32 alpha = 0;
 	u32 data;
 	u32 pagewidth;
 	int clkdiv;
@@ -481,15 +517,12 @@ static int s3c_fb_set_par(struct fb_info *info)
 
 	data = var->xres * var->yres;
 
-	osdc_data = VIDISD14C_ALPHA1_R(0xf) |
+	alpha = VIDISD14C_ALPHA1_R(0xf) |
 		VIDISD14C_ALPHA1_G(0xf) |
 		VIDISD14C_ALPHA1_B(0xf);
 
-	if (win->variant.has_osd_d) {
-		writel(data, regs + VIDOSD_D(win_no, sfb->variant));
-		writel(osdc_data, regs + VIDOSD_C(win_no, sfb->variant));
-	} else
-		writel(data, regs + VIDOSD_C(win_no, sfb->variant));
+	vidosd_set_alpha(win, alpha);
+	vidosd_set_size(win, data);
 
 	data = WINCONx_ENWIN;
 
@@ -1452,12 +1485,17 @@ static int s3c_fb_resume(struct platform_device *pdev)
 static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] __devinitdata = {
 	[0] = {
 		.has_osd_c	= 1,
+		.has_osd_size	= 1,
+		.osd_size_off	= 0x8,
 		.palette_sz	= 256,
 		.valid_bpp	= VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
 	},
 	[1] = {
 		.has_osd_c	= 1,
 		.has_osd_d	= 1,
+		.has_osd_size	= 1,
+		.osd_size_off	= 0x12,
+		.has_osd_alpha	= 1,
 		.palette_sz	= 256,
 		.valid_bpp	= (VALID_BPP1248 | VALID_BPP(16) |
 				   VALID_BPP(18) | VALID_BPP(19) |
@@ -1466,6 +1504,9 @@ static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] __devinitdata = {
 	[2] = {
 		.has_osd_c	= 1,
 		.has_osd_d	= 1,
+		.has_osd_size	= 1,
+		.osd_size_off	= 0x12,
+		.has_osd_alpha	= 1,
 		.palette_sz	= 16,
 		.palette_16bpp	= 1,
 		.valid_bpp	= (VALID_BPP1248 | VALID_BPP(16) |
@@ -1474,6 +1515,7 @@ static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] __devinitdata = {
 	},
 	[3] = {
 		.has_osd_c	= 1,
+		.has_osd_alpha	= 1,
 		.palette_sz	= 16,
 		.palette_16bpp	= 1,
 		.valid_bpp	= (VALID_BPP124  | VALID_BPP(16) |
@@ -1482,6 +1524,7 @@ static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] __devinitdata = {
 	},
 	[4] = {
 		.has_osd_c	= 1,
+		.has_osd_alpha	= 1,
 		.palette_sz	= 4,
 		.palette_16bpp	= 1,
 		.valid_bpp	= (VALID_BPP(1) | VALID_BPP(2) |
@@ -1607,6 +1650,7 @@ static struct s3c_fb_driverdata s3c_fb_data_s3c2443 __devinitdata = {
 	},
 	.win[1] = &(struct s3c_fb_win_variant) {
 		.has_osd_c	= 1,
+		.has_osd_alpha	= 1,
 		.palette_sz	= 256,
 		.valid_bpp	= (VALID_BPP1248 | VALID_BPP(16) |
 				   VALID_BPP(18) | VALID_BPP(19) |
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun 16 05:34:50 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 11:34:50 +0200
Subject: [PATCH 7/9] s3c-fb: window 3 of 64xx+ does not have an osd_d register
In-Reply-To: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1276680892-14760-8-git-send-email-m.szyprowski@samsung.com>

From: Pawel Osciak <p.osciak at samsung.com>

Fix incorrectly defined OSD_D register for S3C64xx SoCs.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 drivers/video/s3c-fb.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 6131ebb..0a93fca 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -1437,7 +1437,6 @@ static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] __devinitdata = {
 	},
 	[3] = {
 		.has_osd_c	= 1,
-		.has_osd_d	= 1,
 		.palette_sz	= 16,
 		.palette_16bpp	= 1,
 		.valid_bpp	= (VALID_BPP124  | VALID_BPP(16) |
-- 
1.7.1.240.g225c



From m.szyprowski at samsung.com  Wed Jun 16 05:34:51 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 16 Jun 2010 11:34:51 +0200
Subject: [PATCH 8/9] s3c-fb: Add SHADOWCON shadow register locking support for
	S5PV210
In-Reply-To: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
References: <1275296935-2693-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1276680892-14760-9-git-send-email-m.szyprowski@samsung.com>

From: Pawel Osciak <p.osciak at samsung.com>

S5PV210 allows per-window locking of register value updates from shadow
registers.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/plat-samsung/include/plat/regs-fb.h |    3 ++
 drivers/video/s3c-fb.c                       |   46 +++++++++++++++++++++++--
 2 files changed, 45 insertions(+), 4 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index 5bcdd09..da54b64 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -218,6 +218,9 @@
 #define WINCON1_BPPMODE_25BPP_A1888		(0xd << 2)
 #define WINCON1_BPPMODE_28BPP_A4888		(0xd << 2)
 
+/* S5PV210 */
+#define SHADOWCON				(0x34)
+#define SHADOWCON_WINx_PROTECT(_win)		(1 << (10 + _win))
 
 #define VIDOSDxA_TOPLEFT_X_MASK			(0x7ff << 11)
 #define VIDOSDxA_TOPLEFT_X_SHIFT		(11)
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 0a93fca..5e14f0a 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -79,6 +79,7 @@ struct s3c_fb;
  * @osd: The base for the OSD registers.
  * @palette: Address of palette memory, or 0 if none.
  * @has_prtcon: Set if has PRTCON register.
+ * @has_shadowcon: Set if has SHADOWCON register.
  */
 struct s3c_fb_variant {
 	unsigned int	is_2443:1;
@@ -95,6 +96,7 @@ struct s3c_fb_variant {
 	unsigned short	palette[S3C_FB_MAX_WIN];
 
 	unsigned int	has_prtcon:1;
+	unsigned int	has_shadowcon:1;
 };
 
 /**
@@ -620,6 +622,43 @@ static inline unsigned int chan_to_field(unsigned int chan,
 }
 
 /**
+ * shadow_protect() - disable updating values from shadow registers at vsync
+ *
+ * @sfb: The hardware information
+ * @win_no: Window number to protect registers for
+ */
+static void shadow_protect(struct s3c_fb_win *win)
+{
+	struct s3c_fb *sfb = win->parent;
+
+	if (sfb->variant.has_prtcon)
+		writel(PRTCON_PROTECT, sfb->regs + PRTCON);
+	else if (sfb->variant.has_shadowcon)
+		writel(SHADOWCON_WINx_PROTECT(win->index),
+			sfb->regs + SHADOWCON);
+}
+
+/**
+ * shadow_noprotect() - re-enable updating values from shadow registers at vsync
+ *
+ * @sfb: The hardware information
+ * @win_no: Window number to re-enable updates from shadow registers
+ */
+static void shadow_noprotect(struct s3c_fb_win *win)
+{
+	struct s3c_fb *sfb = win->parent;
+	u32 reg;
+
+	if (sfb->variant.has_prtcon) {
+		writel(0, sfb->regs + PRTCON);
+	} else if (sfb->variant.has_shadowcon) {
+		reg = readl(sfb->regs + SHADOWCON);
+		writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
+			sfb->regs + SHADOWCON);
+	}
+}
+
+/**
  * s3c_fb_setcolreg() - framebuffer layer request to change palette.
  * @regno: The palette index to change.
  * @red: The red field for the palette data.
@@ -811,16 +850,14 @@ static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
 
 	/* Temporarily turn off per-vsync update from shadow registers until
 	 * both start and end addresses are updated to prevent corruption */
-	if (sfb->variant.has_prtcon)
-		writel(PRTCON_PROTECT, sfb->regs + PRTCON);
+	shadow_protect(win);
 
 	writel(info->fix.smem_start + start_byte_offset,
 		buf + sfb->variant.buf_start);
 	writel(info->fix.smem_start + end_byte_offset,
 		buf + sfb->variant.buf_end);
 
-	if (sfb->variant.has_prtcon)
-		writel(0, sfb->regs + PRTCON);
+	shadow_noprotect(win);
 
 	return 0;
 }
@@ -1534,6 +1571,7 @@ static struct s3c_fb_driverdata s3c_fb_data_s5pv210 __devinitdata = {
 			[4] = 0x3400,
 		},
 
+		.has_shadowcon	= 1,
 	},
 	.win[0]	= &s3c_fb_data_64xx_wins[0],
 	.win[1]	= &s3c_fb_data_64xx_wins[1],
-- 
1.7.1.240.g225c



From pan at nt.tu-darmstadt.de  Wed Jun 16 05:45:00 2010
From: pan at nt.tu-darmstadt.de (Vladimir Pantelic)
Date: Wed, 16 Jun 2010 11:45:00 +0200
Subject: Request review of device tree documentation
In-Reply-To: <4C187FF0.5020806@firmworks.com>
References: <4C13430B.5000907@firmworks.com>	<1276339529.1962.184.camel@pasglop>	<1276339684.1962.186.camel@pasglop>	<4C13B618.1030006@firmworks.com>	<1276383132.1962.195.camel@pasglop>	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>	<4C146F18.9030008@firmworks.com>	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>	<20100614124438.GF9323@yookeroo>	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>	<20100614160201.GD9550@shareable.org>	<4C165FD1.6080505@firmworks.com>
	<4C186AA8.4040709@compulab.co.il>	<4C186B7B.1060308@firmworks.com>
	<4C186C72.2020506@compulab.co.il>	<4C187013.5000400@firmworks.com>
	<4C18738C.4090809@compulab.co.il> <4C187FF0.5020806@firmworks.com>
Message-ID: <4C189D1C.6050304@nt.tu-darmstadt.de>

Mitch Bradley wrote:

>>  I'm also objecting the step (b) and, fortunately, it's not yet the
>>  status quo.
>>  Current U-Boot/kernel implementations I've encountered still do not
>>  have OS calls to resident HW access routines. But if such calls would
>>  be allowed, my impression is that SoC vendors would make extensive use
>>  of them.
>
> One could argue that a feature that vendors would use extensively is one
> that is sorely needed from their point of view.

yes, it would free them from writing these pesky linux drivers and getting
them into mainline :)



From richardcochran at gmail.com  Wed Jun 16 06:05:39 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Wed, 16 Jun 2010 12:05:39 +0200
Subject: [PATCH 12/12] ptp: Added a clock driver for the National
	Semiconductor PHYTER.
In-Reply-To: <AANLkTilqd-wxqMWDxssC-XMDJqZ8iIiSrvp2t8xARAQV@mail.gmail.com>
References: <cover.1276615626.git.richard.cochran@omicron.at>
	<37f5015b186bdd51f8451ade042f90c8b39a5cc8.1276615626.git.richard.cochran@omicron.at>
	<AANLkTilqd-wxqMWDxssC-XMDJqZ8iIiSrvp2t8xARAQV@mail.gmail.com>
Message-ID: <20100616100539.GA3569@riccoc20.at.omicron.at>

On Tue, Jun 15, 2010 at 12:49:13PM -0600, Grant Likely wrote:
> Won't this break things for existing DP83640 users?

Nope, the driver was only added five patches ago, and it only offers
the timestamping stuff. The standard PHY functions just call the
generic functions, so the PHY works fine even without this driver.

> > +static struct ptp_clock *dp83640_clock;
> > +DEFINE_SPINLOCK(clock_lock); /* protects the one and only dp83640_clock */
> 
> Why only one?  Is it not possible to have 2 of these PHYs in a system?

Yes, you can have multiple PHYs, but only one PTP clock.

If you do use multiple PHYs, then you must wire their clocks together
and adjust the PTP clock on only one of the PHYs.


Thanks for your other comments,

Richard


From s.nawrocki at samsung.com  Wed Jun 16 06:12:01 2010
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Wed, 16 Jun 2010 12:12:01 +0200
Subject: [PATCH 5/7] ARM: S5PV210: Add fifo link definitions for fimc and
	framebuffer
In-Reply-To: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
References: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
Message-ID: <1276683123-30224-6-git-send-email-s.nawrocki@samsung.com>

From: Marek Szyprowski <m.szyprowski at samsung.com>

Add definition of local paths that are available on Sasmung S5PV210
SoCs.

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com>
---
 arch/arm/mach-s5pv210/setup-fimc0.c       |   23 +++++++++++++++++++++++
 arch/arm/mach-s5pv210/setup-fimc1.c       |   23 +++++++++++++++++++++++
 arch/arm/mach-s5pv210/setup-fimc2.c       |   23 +++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/fimc.h |    4 ++++
 4 files changed, 73 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/setup-fimc0.c b/arch/arm/mach-s5pv210/setup-fimc0.c
index 94205f5..fab6e52 100644
--- a/arch/arm/mach-s5pv210/setup-fimc0.c
+++ b/arch/arm/mach-s5pv210/setup-fimc0.c
@@ -10,6 +10,10 @@
  */
 
 #include <plat/fimc.h>
+#include <plat/fifo.h>
+#include <linux/fb.h>
+#include <plat/fb.h>
+#include <plat/devs.h>
 
 struct samsung_plat_fimc s5p_fimc0_default_data __initdata = {
 	.capability	= S5P_FIMC_IN_ROT | S5P_FIMC_OUT_ROT,
@@ -23,3 +27,22 @@ struct samsung_plat_fimc s5p_fimc0_default_data __initdata = {
 	.out_rot_en_w	= 1920,
 	.out_rot_dis_w	= 4224
 };
+
+static struct s3c_fifo_link s5pv210_fimc0_win0_link = {
+	.master_dev	= &s5p_device_fimc0.dev,
+	.slave_dev	= &s3c_device_fb.dev,
+};
+
+void __init s5pv210_setup_fimc0_fb_link(void)
+{
+	struct s3c_fb_platdata *fb_pd;
+	struct samsung_plat_fimc *fimc_pd;
+
+	fimc_pd = s5p_device_fimc0.dev.platform_data;
+	fb_pd = s3c_device_fb.dev.platform_data;
+
+	if (fimc_pd && fb_pd && fb_pd->win[0]) {
+		fb_pd->win[0]->fifo_sources[0] = &s5pv210_fimc0_win0_link;
+		fimc_pd->fifo_targets[0] = &s5pv210_fimc0_win0_link;
+	}
+}
diff --git a/arch/arm/mach-s5pv210/setup-fimc1.c b/arch/arm/mach-s5pv210/setup-fimc1.c
index bfaffe9..2a6e930 100644
--- a/arch/arm/mach-s5pv210/setup-fimc1.c
+++ b/arch/arm/mach-s5pv210/setup-fimc1.c
@@ -10,6 +10,10 @@
  */
 
 #include <plat/fimc.h>
+#include <plat/fifo.h>
+#include <linux/fb.h>
+#include <plat/fb.h>
+#include <plat/devs.h>
 
 struct samsung_plat_fimc s5p_fimc1_default_data __initdata = {
 	.capability	= S5P_FIMC_IN_ROT | S5P_FIMC_OUT_ROT,
@@ -23,3 +27,22 @@ struct samsung_plat_fimc s5p_fimc1_default_data __initdata = {
 	.out_rot_en_w	= 1920,
 	.out_rot_dis_w	= 4224
 };
+
+static struct s3c_fifo_link s5pv210_fimc1_win1_link = {
+	.master_dev	= &s5p_device_fimc1.dev,
+	.slave_dev	= &s3c_device_fb.dev,
+};
+
+void __init s5pv210_setup_fimc1_fb_link(void)
+{
+	struct s3c_fb_platdata *fb_pd;
+	struct samsung_plat_fimc *fimc_pd;
+
+	fimc_pd = s5p_device_fimc1.dev.platform_data;
+	fb_pd = s3c_device_fb.dev.platform_data;
+
+	if (fimc_pd && fb_pd && fb_pd->win[1]) {
+		fb_pd->win[1]->fifo_sources[0] = &s5pv210_fimc1_win1_link;
+		fimc_pd->fifo_targets[0] = &s5pv210_fimc1_win1_link;
+	}
+}
diff --git a/arch/arm/mach-s5pv210/setup-fimc2.c b/arch/arm/mach-s5pv210/setup-fimc2.c
index a53a382..79b61b0 100644
--- a/arch/arm/mach-s5pv210/setup-fimc2.c
+++ b/arch/arm/mach-s5pv210/setup-fimc2.c
@@ -10,6 +10,10 @@
  */
 
 #include <plat/fimc.h>
+#include <plat/fifo.h>
+#include <linux/fb.h>
+#include <plat/fb.h>
+#include <plat/devs.h>
 
 struct samsung_plat_fimc s5p_fimc2_default_data __initdata = {
 	.capability	= S5P_FIMC_IN_ROT | S5P_FIMC_OUT_ROT,
@@ -23,3 +27,22 @@ struct samsung_plat_fimc s5p_fimc2_default_data __initdata = {
 	.out_rot_en_w	= 1280,
 	.out_rot_dis_w	= 1920
 };
+
+static struct s3c_fifo_link s5pv210_fimc2_win2_link = {
+	.master_dev	= &s5p_device_fimc2.dev,
+	.slave_dev	= &s3c_device_fb.dev,
+};
+
+void __init s5pv210_setup_fimc2_fb_link(void)
+{
+	struct s3c_fb_platdata *fb_pd;
+	struct samsung_plat_fimc *fimc_pd;
+
+	fimc_pd = s5p_device_fimc2.dev.platform_data;
+	fb_pd = s3c_device_fb.dev.platform_data;
+
+	if (fimc_pd && fb_pd && fb_pd->win[2]) {
+		fb_pd->win[2]->fifo_sources[0] = &s5pv210_fimc2_win2_link;
+		fimc_pd->fifo_targets[0] = &s5pv210_fimc2_win2_link;
+	}
+}
diff --git a/arch/arm/plat-samsung/include/plat/fimc.h b/arch/arm/plat-samsung/include/plat/fimc.h
index bc6799e..8f95fc0 100644
--- a/arch/arm/plat-samsung/include/plat/fimc.h
+++ b/arch/arm/plat-samsung/include/plat/fimc.h
@@ -54,5 +54,9 @@ extern void s5p_fimc0_set_platdata(struct samsung_plat_fimc *fimc);
 extern void s5p_fimc1_set_platdata(struct samsung_plat_fimc *fimc);
 extern void s5p_fimc2_set_platdata(struct samsung_plat_fimc *fimc);
 
+extern void __init s5pv210_setup_fimc0_fb_link(void);
+extern void __init s5pv210_setup_fimc1_fb_link(void);
+extern void __init s5pv210_setup_fimc2_fb_link(void);
+
 #endif /* FIMC_H_ */
 
-- 
1.7.0.4



From s.nawrocki at samsung.com  Wed Jun 16 06:11:56 2010
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Wed, 16 Jun 2010 12:11:56 +0200
Subject: [PATCH/RFC] Samsung multimedia (FIMC and FB) drivers proposal
Message-ID: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>


Hello, 

This RFC concerns Samsung's S3C/S5P SoC series and the proposal 
of a general solution for managing direct data pipelines between 
numerous graphics IPs present in these chips.

Background
-----------------

Selected multimedia devices in Samsung S3C/S5P SoCs are capable of 
transferring data directly between each other over so called fifo 
channels, bypassing the main memory system bus. The fifo links, for 
instance exist between tv scaler and framebuffer (S3C64xx), camera 
interface and framebuffer (S3C64xx, S5PC1xx and others) or framebuffer 
and video postprocessor (S3C64xx). Usually a framebuffer (display 
controller) is the data receiver in a different configurations. 
The framebuffer is divided into logic windows which represent 
data transfer destination objects in each fifo configurations. 

Implementation
-----------------

To enable the fifo link both ends need to be switched in a synchronized 
way to so called "local fifo mode". Depending on the SoC it mostly needs 
to be done shortly after an interrupt invocation and excess latencies 
are not acceptable. 

The proposed solution supports the following kinds of fifo links between
source and target devices:
 - "one to one", e.g. fimc-0 -> framebuffer window-0 (s5pv210 like)
 - "one to many" e.g. fimc-1 or TV scaler -> framebufer window-1
   (s3c64xx like)
 - "many to one", e.g. camera interface -> framebuffer window-0 or
   window-1 (s3c64xx like)

Implementing support for the local fifo mode requires partial control of 
one (slave) device from within other (master) device. The v4l2_subdev 
API seem to seem to be a concise solution for this problem. 

The following patches are a preliminary implementation of the V4L2 
driver of the camera interface/video postprocessor, which is found in 
S3C/S5P SoCs and required logic in s3c-fb driver. 

We decided to create a v4l2 subdevice instance at framebuffer per its each 
possible data source, depending on SoC architecture, as shown below:

                  -------------------          ---------------
                 |                   |        |               |
                 |   fb window-0     |  ....  |  fb window-N  |<---
                  -------------------         |               |    |
       ----------|  v4l2_subdev-0.1  |        |               |    |
      |           -------------------          ---------------     |
      |          |  v4l2_subdev-0.2  |        | v4l2_subdev-N |    |
      |           -------------------          ---------------     |
      |                 |                        |   ^             |
      |                 |    -------------------     |          slave_dev
      |                 |   |                     sub_dev          |
 --------------     ----------------                 |             |
|  v4l2_device |   |  v4l2_device   |       [ s3c_fifo_link ]------
 --------------     ----------------           | 
|              |   |                |      master_dev
|  tv scaler   |   | video postproc.|          |
|              |   |   (fimc-0)     |<---------
 --------------     ---------------- 


The s3c_fifo_link data structure allows to define possible device driver's 
connections, depending on the physical hardware architecture.

struct s3c_fifo_link {
	struct device	*master_dev;
	struct device	*slave_dev;
	struct v4l2_subdev *sub_dev;
};


Driver initialization sequence
-------------------------------

At slave (fb window) side:

- during probe() call fb driver initializes each window's subdevice 
  and s3c_fifo_link data structure 
  

At master (fimc-X) side:

- in video device open() fimc iterates through its list of pointers 
  to target subdevices earlier setup by the platform code 
  and initialized by fb probe() and calls v4l2_device_register_subdev() 


Driver module release sequence
-------------------------------

When the video postprocessor acquires one of the framebuffer subdevices 
the framebuffer module is marked as "in use" so it cannot be removed 
until the postprocessor has completed its perations on fb v4l2-subdev.

On slave module removal (unless any subdevice is in use):

- slave device driver deletes its all subdevices and sets to null
  corresponding sub_dev field in s3c_fifo_link instance

On master removal/close:

-  master device driver calls v4l2_device_register_subdev() on sub_dev; 
   after that subdevice/fifo interface may be used by any 
   other master device


I would like to ask for any comments on such a v4l2-subdev API usage
and on any possible drawbacks it might have.

Kernel tree
-----------------

This patch series has been prepared in assumption that the following
patches for s3c-fb driver has been applied:
1. S3C Frame Buffer patches prepared by Ben Dooks:
   git://git.fluff.org/bjdooks/linux for-2635/s3c-fb
2. S3C Frame Buffer patches prepared by Pawel Osciak:
   http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg01527.html
   
For easier code review all the patches will be also available in
few hours on:
http://git.infradead.org/users/kmpark/linux-2.6-samsung/ 
branch s5pv210-fimc-fb

Patches
-----------------

The following patch series contains:

[PATCH 1/7] ARM: Samsung: Add FIMC driver register definition and platform helpers
[PATCH 2/7] ARM: Samsung: Add platform definitions for local FIMC/FIMD fifo path
[PATCH 3/7] s3c-fb: Add v4l2 subdevice to support framebuffer local fifo input path
[PATCH 4/7] v4l: Add Samsung FIMC (video postprocessor) driver
[PATCH 5/7] ARM: S5PV210: Add fifo link definitions for fimc and framebuffer
[PATCH 6/7] ARM: S5PV210: enable FIMC on Aquila
[PATCH 7/7] ARM: S5PC100: enable FIMC on SMDKC100

Best regards,
--
Sylwester Nawrocki
Samsung Poland R&D Center




From s.nawrocki at samsung.com  Wed Jun 16 06:11:58 2010
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Wed, 16 Jun 2010 12:11:58 +0200
Subject: [PATCH 2/7] ARM: Samsung: Add platform definitions for local FIMC/FIMD
	fifo path
In-Reply-To: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
References: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
Message-ID: <1276683123-30224-3-git-send-email-s.nawrocki@samsung.com>

From: Marek Szyprowski <m.szyprowski at samsung.com>

Add a common s3c_fifo_link structure that describes a local path link
between 2 multimedia devices (like FIMC and FrameBuffer).

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com>
---
 arch/arm/plat-samsung/include/plat/fifo.h |   37 +++++++++++++++++++++++++++++
 1 files changed, 37 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-samsung/include/plat/fifo.h

diff --git a/arch/arm/plat-samsung/include/plat/fifo.h b/arch/arm/plat-samsung/include/plat/fifo.h
new file mode 100644
index 0000000..84d242b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/fifo.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIFO_H_
+#define FIFO_H_
+
+#include <linux/device.h>
+#include <media/v4l2-subdev.h>
+
+/*
+ * The multimedia devices contained in Samsung S3C/S5P SoC series
+ * like framebuffer, camera interface or tv scaler can transfer data
+ * directly between each other through hardware fifo channels.
+ * s3c_fifo_link data structure is an abstraction for such links,
+ * it allows to define V4L2 device drivers hierarchy according to
+ * the hardware structure. Fifo links are mostly unidirectional, exclusive
+ * data buses. To control data transfer in fifo mode synchronization is
+ * is required between drivers at both ends of the fifo channel
+ * (master_dev, slave_dev). s3c_fifo_link:sub_dev is intended  to export
+ * in a consistent way all the functionality of the slave device required
+ * at master device driver to enable transfer through fifo channel.
+ * master_dev and slave_dev is to be setup by the platform code whilst
+ * sub_dev entry will mostly be initlized during slave_dev probe().
+ */
+struct s3c_fifo_link {
+	struct device		*master_dev;
+	struct device		*slave_dev;
+	struct v4l2_subdev	*sub_dev;
+};
+
+#endif /* FIFO_H_ */
+
-- 
1.7.0.4



From s.nawrocki at samsung.com  Wed Jun 16 06:12:03 2010
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Wed, 16 Jun 2010 12:12:03 +0200
Subject: [PATCH 7/7] ARM: S5PC100: enable FIMC on SMDKC100
In-Reply-To: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
References: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
Message-ID: <1276683123-30224-8-git-send-email-s.nawrocki@samsung.com>

Add support for FIMC on Samsung SMDKC100 board.

Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/mach-s5pc100/Kconfig         |    6 ++++++
 arch/arm/mach-s5pc100/mach-smdkc100.c |    9 +++++++++
 2 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 81a06a3..2ead495 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -62,6 +62,12 @@ config MACH_SMDKC100
 	select S5PC100_SETUP_FB_24BPP
 	select S5PC100_SETUP_I2C1
 	select S5PC100_SETUP_SDHCI
+	select S5P_DEV_FIMC0
+	select S5PC100_SETUP_FIMC0
+	select S5P_DEV_FIMC1
+	select S5PC100_SETUP_FIMC1
+	select S5P_DEV_FIMC2
+	select S5PC100_SETUP_FIMC2
 	help
 	  Machine support for the Samsung SMDKC100
 
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index af22f82..425b1c5 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -42,6 +42,7 @@
 #include <plat/s5pc100.h>
 #include <plat/fb.h>
 #include <plat/iic.h>
+#include <plat/fimc.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define S5PC100_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
@@ -159,6 +160,9 @@ static struct platform_device *smdkc100_devices[] __initdata = {
 	&smdkc100_lcd_powerdev,
 	&s5pc100_device_iis0,
 	&s5pc100_device_ac97,
+	&s5p_device_fimc0,
+	&s5p_device_fimc1,
+	&s5p_device_fimc2,
 };
 
 static void __init smdkc100_map_io(void)
@@ -178,6 +182,11 @@ static void __init smdkc100_machine_init(void)
 
 	s3c_fb_set_platdata(&smdkc100_lcd_pdata);
 
+	/* FIMC */
+	s5p_fimc0_set_platdata(NULL);
+	s5p_fimc1_set_platdata(NULL);
+	s5p_fimc2_set_platdata(NULL);
+
 	/* LCD init */
 	gpio_request(S5PC100_GPD(0), "GPD");
 	gpio_request(S5PC100_GPH0(6), "GPH0");
-- 
1.7.0.4



From s.nawrocki at samsung.com  Wed Jun 16 06:11:59 2010
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Wed, 16 Jun 2010 12:11:59 +0200
Subject: [PATCH 3/7] s3c-fb: Add v4l2 subdevice to support framebuffer local
	fifo input path
In-Reply-To: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
References: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
Message-ID: <1276683123-30224-4-git-send-email-s.nawrocki@samsung.com>

Selected multimedia devices in Samsung S3C/S5P SoC series are capable of
transferring data directly between each other, bypassing the main system
bus. Such a datapath exists between the camera interface/video
postprocessor and the lcd controller. To control the data flow from the
fimc driver level v4l2-subdevice driver is added to the framebuffer.
Among others it enables to switch the lcd controller from DMA input to
local fifo path.

Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/plat-samsung/include/plat/fb.h |    6 +
 drivers/video/s3c-fb.c                  |  454 ++++++++++++++++++++++++++++++-
 2 files changed, 452 insertions(+), 8 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index cb3ca3a..7dc6110 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -22,6 +22,10 @@
  */
 #define S3C_FB_MAX_WIN	(5)
 
+#define S3C_FB_MAX_WIN_SOURCES	(2)
+
+struct s3c_fifo_link;
+
 /**
  * struct s3c_fb_pd_win - per window setup data
  * @win_mode: The display parameters to initialise (not for window 0)
@@ -35,6 +39,8 @@ struct s3c_fb_pd_win {
 	unsigned short		max_bpp;
 	unsigned short		virtual_x;
 	unsigned short		virtual_y;
+
+	struct s3c_fifo_link	*fifo_sources[S3C_FB_MAX_WIN_SOURCES];
 };
 
 /**
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index f098bd1..d36ca88 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -24,9 +24,14 @@
 #include <linux/uaccess.h>
 #include <linux/interrupt.h>
 
+#include <linux/videodev2.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+
 #include <mach/map.h>
 #include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
+#include <plat/fifo.h>
 
 /* This driver will export a number of framebuffer interfaces depending
  * on the configuration passed in via the platform data. Each fb instance
@@ -56,6 +61,18 @@
 #define VSYNC_TIMEOUT_MSEC 50
 
 struct s3c_fb;
+struct s3c_fb_win;
+
+struct s3c_fb_win_sd {
+	struct v4l2_subdev	sd;
+	unsigned int		index;
+	struct s3c_fb_win	*win;
+	struct s3c_fifo_link	*link;
+	struct v4l2_format	fmt;
+	int			streaming;
+	struct v4l2_crop	default_rect;
+	struct v4l2_crop	osd_rect;
+};
 
 #define VALID_BPP(x) (1 << ((x) - 1))
 
@@ -157,6 +174,9 @@ struct s3c_fb_palette {
  * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
  * @index: The window number of this window.
  * @palette: The bitfields for changing r/g/b into a hardware palette entry.
+ * @sources:
+ * @local_path: flag indicating the lcd controller input mode:
+ *		0 - local path from other SoC subsystem, 1 - DMA
  */
 struct s3c_fb_win {
 	struct s3c_fb_pd_win	*windata;
@@ -168,6 +188,8 @@ struct s3c_fb_win {
 	u32			*palette_buffer;
 	u32			 pseudo_palette[16];
 	unsigned int		 index;
+	struct s3c_fb_win_sd	*sources[S3C_FB_MAX_WIN_SOURCES];
+	unsigned int		local_path;
 };
 
 /**
@@ -361,13 +383,10 @@ static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
  */
 static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
 {
-	int pix_per_word;
-
 	if (bpp > 16)
 		return pix;
 
-	pix_per_word = (8 * 32) / bpp;
-	return ALIGN(pix, pix_per_word);
+	return  round_down(pix, (bpp > 8) ? 2 : 4);
 }
 
 /**
@@ -419,6 +438,9 @@ static int s3c_fb_set_par(struct fb_info *info)
 	u32 pagewidth;
 	int clkdiv;
 
+	if (win->local_path)
+		return -EBUSY;
+
 	dev_dbg(sfb->dev, "setting framebuffer parameters\n");
 
 	switch (var->bits_per_pixel) {
@@ -486,7 +508,7 @@ static int s3c_fb_set_par(struct fb_info *info)
 
 		data = VIDTCON2_LINEVAL(var->yres - 1) |
 		       VIDTCON2_HOZVAL(var->xres - 1);
-		writel(data, regs +sfb->variant.vidtcon + 8 );
+		writel(data, regs + sfb->variant.vidtcon + 8);
 	}
 
 	/* write the buffer address */
@@ -711,6 +733,9 @@ static int s3c_fb_setcolreg(unsigned regno,
 	dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
 		__func__, win->index, regno, red, green, blue);
 
+	if (win->local_path)
+		return -EBUSY;
+
 	switch (info->fix.visual) {
 	case FB_VISUAL_TRUECOLOR:
 		/* true-colour, use pseudo-palette */
@@ -786,6 +811,9 @@ static int s3c_fb_blank(int blank_mode, struct fb_info *info)
 
 	dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
 
+	if (win->local_path)
+		return -EBUSY;
+
 	wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
 
 	switch (blank_mode) {
@@ -896,6 +924,168 @@ static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
 }
 
 /**
+ * s3c_fb_set_osd() - set position and size of the framebuffer window
+ *
+ * @win: framebuffer window to get data for
+ * @cr: pixel cropping reactangle
+ *
+ * Set framebuffer window position and size. cr rectangle will be modified
+ * if it does not meet the hardware alignment requirements.
+ */
+int s3c_fb_set_osd(struct s3c_fb_win *win, struct v4l2_rect *cr, int bpp)
+{
+	u32 data, width;
+	struct s3c_fb *sfb = win->parent;
+	void __iomem *regs = sfb->regs;
+
+	if (win->index >= S3C_FB_MAX_WIN)
+		return -EINVAL;
+
+	shadow_protect(win);
+
+	cr->left = s3c_fb_align_word(bpp, cr->left);
+	data = VIDOSDxA_TOPLEFT_X(cr->left) | VIDOSDxA_TOPLEFT_Y(cr->top);
+	writel(data, regs + VIDOSD_A(win->index, sfb->variant));
+
+	width = s3c_fb_align_word(bpp, cr->width - 1);
+
+	data = VIDOSDxB_BOTRIGHT_X(cr->left + width)
+	     | VIDOSDxB_BOTRIGHT_Y(cr->top + cr->height - 1);
+
+	writel(data, regs + VIDOSD_B(win->index, sfb->variant));
+
+	data = (width + 1) * cr->height;
+	vidosd_set_size(win, data);
+
+	shadow_noprotect(win);
+
+	dev_dbg(sfb->dev, "%s(): l:%d t:%d w:%d h:%d", __func__,
+		cr->left, cr->top, cr->width, cr->height);
+
+	return 0;
+}
+
+/**
+ * s3c_fb_get_osd() - get position and size of the frame buffer window
+ *
+ * @win: framebuffer window to get data for
+ * @cr: current cropping rectangle
+ */
+int s3c_fb_get_osd(struct s3c_fb_win *win, struct v4l2_rect *cr)
+{
+	u32 reg, ltx, lty;
+	struct s3c_fb *sfb = win->parent;
+	void __iomem *regs = sfb->regs;
+
+	if (!cr || win->index >= S3C_FB_MAX_WIN)
+		return -EINVAL;
+
+	reg = readl(regs + VIDOSD_A(win->index, sfb->variant));
+
+	ltx = (reg >> VIDOSDxA_TOPLEFT_X_SHIFT) & VIDOSDxA_TOPLEFT_X_LIMIT;
+	lty = (reg >> VIDOSDxA_TOPLEFT_Y_SHIFT) & VIDOSDxA_TOPLEFT_Y_LIMIT;
+
+	reg = readl(regs + VIDOSD_B(win->index, sfb->variant));
+
+	cr->width = ((reg >> VIDOSDxB_BOTRIGHT_X_SHIFT)
+		  & VIDOSDxB_BOTRIGHT_X_LIMIT) - ltx + 1;
+
+	cr->height = ((reg >> VIDOSDxB_BOTRIGHT_Y_SHIFT)
+			& VIDOSDxB_BOTRIGHT_Y_LIMIT) - lty + 1;
+	cr->left = ltx;
+	cr->top = lty;
+
+	dev_dbg(sfb->dev, "%s(): l:%d t:%d w:%d h:%d", __func__,
+		cr->left, cr->top, cr->width, cr->height);
+
+	return 0;
+}
+
+/**
+ * s3c_fb_enable_local() - switch window between input DMA and fifo modes
+ *
+ * @en: nonzero - switch from input DMA to fifo mode and apply
+ *		  window size and position set by the window's subdevice
+ *      0 - restore from fifo to DMA mode
+ * @fb_sd: window subdevice for fifo input
+ */
+static int s3c_fb_enable_local_in(struct s3c_fb_win_sd *fb_sd, int en)
+{
+	struct s3c_fb_win *win = fb_sd->win;
+	struct s3c_fb *sfb = win->parent;
+	static u32 wincon;
+	u32 reg;
+	int ret = 0, bpp = 32;
+
+	/* disable video output and the window logic before altering
+	   window setup */
+	reg = readl(sfb->regs + WINCON(win->index));
+	reg &= ~WINCONx_ENWIN;
+	writel(reg, sfb->regs + WINCON(win->index));
+
+	shadow_protect(win);
+
+	reg = readl(sfb->regs + WINCON(win->index));
+
+	if (en) {
+		if (fb_sd->streaming)
+			return 0;
+
+		wincon = reg;
+
+		switch (fb_sd->fmt.fmt.pix.pixelformat) {
+		case V4L2_PIX_FMT_YUYV: /* YCbCr 4:4:4 */
+			reg |= WINCONx_YCbCr | WINCONx_ENLOCAL;
+			bpp = 16;
+			break;
+
+		case V4L2_PIX_FMT_RGB24:
+		default:
+			reg &= ~(WINCONx_YCbCr | WINCONx_WSWP | WINCONx_HAWSWP |
+				 WINCONx_BYTSWP | WINCONx_BITSWP |
+				 WINCON0_BPPMODE_MASK | WINCONx_BURSTLEN_MASK);
+
+			reg |=	WINCON0_BPPMODE_24BPP_888 |
+				WINCONx_BURSTLEN_4WORD |
+				WINCONx_ENLOCAL;
+			bpp = 24;
+			break;
+		}
+		ret = s3c_fb_set_osd(fb_sd->win, &fb_sd->osd_rect.c, bpp);
+		if (!ret) {
+			fb_sd->streaming = 1;
+			writel(reg, sfb->regs + WINCON(win->index));
+		}
+	} else {
+		/* here we need to be aligned with VSYNC interrupt */
+		if (!fb_sd->streaming)
+			return 0;
+
+		reg = wincon & ~WINCONx_ENLOCAL;
+		fb_sd->streaming = 0;
+		/* restore OSD values from before we enabled local mode */
+		bpp = win->fbinfo->var.bits_per_pixel;
+		s3c_fb_set_osd(fb_sd->win, &fb_sd->default_rect.c, bpp);
+		writel(reg, sfb->regs + WINCON(win->index));
+	}
+
+	shadow_noprotect(win);
+
+	reg = readl(sfb->regs + WINCON(win->index));
+	reg |= WINCONx_ENWIN;
+	writel(reg, sfb->regs + WINCON(win->index));
+
+	return ret;
+}
+
+/* Returns current horizontal line number. It will be 0 during VSYNC. */
+inline u32 s3c_fb_get_line_count(struct s3c_fb *sfb)
+{
+	u32 reg = readl(sfb->regs + VIDCON1);
+	return VIDCON1_LINECNT_GET(reg);
+}
+
+/**
  * s3c_fb_enable_irq() - enable framebuffer interrupts
  * @sfb: main hardware state
  */
@@ -912,7 +1102,7 @@ static void s3c_fb_enable_irq(struct s3c_fb *sfb)
 		irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
 
 		irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
-		irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
+		irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
 		irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
 		irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
 
@@ -1089,6 +1279,247 @@ static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
 			      fbi->screen_base, fbi->fix.smem_start);
 }
 
+/* V4L2 frambuffer subdevice  */
+
+static struct s3c_fb_win_sd *to_fb_win_sd(struct v4l2_subdev *s)
+{
+	return container_of(s, struct s3c_fb_win_sd, sd);
+}
+
+/**
+ * v4l2_sd_fb_s_stream() - switch between DMA on local path mode
+ *
+ * @win: window to change operation mode for.
+ * @sd:
+ * @en: if nonzero - apply cropping rectangle and switch to local path,
+ *	otherwise - restore cropping rectangle and switch to input DMA mode.
+ */
+static int v4l2_sd_fb_s_stream(struct v4l2_subdev *sd, int en)
+{
+	unsigned long flags;
+	struct s3c_fb_win_sd *w_sd = to_fb_win_sd(sd);
+	struct s3c_fb_win *win = w_sd->win;
+	struct s3c_fb *sfb = win->parent;
+	int retr = 100;
+	int ret = 0;
+
+	if (win->index > 2)
+		return -EINVAL;
+
+	mutex_lock(&win->fbinfo->lock);
+
+	if (en) {
+		ret = s3c_fb_enable_local_in(w_sd, en);
+		win->local_path = 1;
+	} else {
+		/* fimc-frambuffer fifo need to be stopped shortly after VSYNC,
+		   for this reason horizontal line count is additionally
+		   examined after waking up by an interrupt. If it is 0 we are
+		   still at VSYNC and therefore are save to disable fifo.
+		   Waiting for VSYNC is repeated unless it is the right time
+		   to proceed. */
+		while (retr--) {
+			ret = s3c_fb_wait_for_vsync(sfb, 0);
+			if (ret)
+				continue;
+			local_irq_save(flags);
+			if (s3c_fb_get_line_count(sfb) == 0) {
+
+				s3c_fb_enable_local_in(w_sd, 0);
+				/* Notify FIMC driver */
+				v4l2_subdev_notify(&w_sd->sd, 0, NULL);
+				local_irq_restore(flags);
+				break;
+			}
+			local_irq_restore(flags);
+		}
+		if (!retr)
+			ret = -ETIMEDOUT;
+		win->local_path = 0;
+	}
+	mutex_unlock(&win->fbinfo->lock);
+
+	return ret;
+}
+
+/**
+ * v4l2_sd_fb_s_fmt() - set format for local input path mode
+ *
+ * @sd: pointer to v4l2 subdevice
+ * @fmt: pixel format to set
+ */
+static int v4l2_sd_fb_s_fmt(struct v4l2_subdev *sd, struct v4l2_format *fmt)
+{
+	struct s3c_fb_win_sd *fb_sd = to_fb_win_sd(sd);
+	int fourcc = fmt->fmt.pix.pixelformat;
+
+	if (!fmt || (fourcc != V4L2_PIX_FMT_YUYV
+		&& fourcc != V4L2_PIX_FMT_RGB24))
+		return -EINVAL;
+	fb_sd->fmt.fmt.pix.pixelformat = fmt->fmt.pix.pixelformat;
+	return 0;
+}
+
+/**
+ * v4l2_sd_fb_cropcap() - get cropping capabilities for local fifo input mode
+ *
+ * @sd: pointer to v4l2 subdevice
+ * @cc:
+ */
+static int v4l2_sd_fb_cropcap(struct v4l2_subdev *sd, struct v4l2_cropcap *cc)
+{
+	struct s3c_fb_win *win = to_fb_win_sd(sd)->win;
+	struct s3c_fb_pd_win *windata = win->windata;
+
+	if (!windata)
+		return -ENODEV;
+
+	mutex_lock(&win->fbinfo->lock);
+
+	cc->defrect.width = windata->win_mode.xres;
+	cc->defrect.height = windata->win_mode.yres;
+	cc->defrect.left = 0;
+	cc->defrect.top = 0;
+	cc->bounds = cc->defrect;
+
+	mutex_unlock(&win->fbinfo->lock);
+
+	return 0;
+}
+
+/**
+ * v4l2_sd_fb_s_crop() - set window position and size
+ *
+ * @sd: pointer to v4l2 subdevice
+ * @cr: cropping rectangle to set for local path mode
+ */
+static int v4l2_sd_fb_s_crop(struct v4l2_subdev *sd, struct v4l2_crop *cr)
+{
+	struct s3c_fb_win_sd *fb_sd = to_fb_win_sd(sd);
+	u32 fourcc = fb_sd->fmt.fmt.pix.pixelformat;
+	struct v4l2_rect *r;
+
+	fb_sd->osd_rect = *cr;
+
+	if (fourcc == V4L2_PIX_FMT_YUYV) {
+		r = &cr->c;
+		r->left = round_down(r->left, 8);
+		r->top = round_down(r->top, 8);
+		r->width = round_down(r->width, 8);
+		r->height = round_down(r->height, 8);
+	}
+
+	return 0;
+}
+
+/**
+ * v4l2_sd_fb_g_crop() - set window position and size
+ *
+ * @sd: pointer to v4l2 subdevice
+ * @cr: rectangle to return current cropping parameters to
+ *
+ * Implements g_crop operation for camera interface driver.
+ */
+static int v4l2_sd_fb_g_crop(struct v4l2_subdev *sd, struct v4l2_crop *cr)
+{
+	struct s3c_fb_win_sd *fb_sd = to_fb_win_sd(sd);
+
+	*cr = fb_sd->osd_rect;
+
+	return 0;
+}
+
+
+static struct v4l2_subdev_core_ops v4l2_sd_core_fb_ops = { NULL };
+
+static struct v4l2_subdev_video_ops v4l2_sd_video_fb_ops = {
+	.s_stream = v4l2_sd_fb_s_stream,
+	.s_fmt = v4l2_sd_fb_s_fmt,
+	.cropcap = v4l2_sd_fb_cropcap,
+	.s_crop = v4l2_sd_fb_s_crop,
+	.g_crop = v4l2_sd_fb_g_crop,
+};
+
+static struct v4l2_subdev_ops v4l2_sd_fb_ops = {
+	.core = &v4l2_sd_core_fb_ops,
+	.video = &v4l2_sd_video_fb_ops,
+};
+
+static int s3c_fb_unregister_subdevices(struct s3c_fb_win *win)
+{
+	int i;
+	struct s3c_fb *sfb = win->parent;
+
+	if (win->index >= S3C_FB_MAX_WIN)
+		return -ENODEV;
+
+	for (i = 0; i < S3C_FB_MAX_WIN_SOURCES; i++) {
+		if (win->sources[i]) {
+			/* remove sub_dev pointer from link */
+			win->sources[i]->link->sub_dev = NULL;
+			kfree(win->sources[i]);
+			dev_dbg(sfb->dev,
+				"s3c-fb subdevice %d removed from window %d\n",
+				i, win->index);
+		}
+	}
+
+	return 0;
+}
+
+/* Create the subdevice per each data source of the framebuffer window.
+   Locking: The caller holds win->parent->dev->mutex. */
+static int s3c_fb_register_subdevices(struct s3c_fb_win *win)
+{
+	int i;
+	struct s3c_fb *sfb = win->parent;
+	struct s3c_fb_pd_win *windata = win->windata;
+	struct s3c_fb_win_sd *win_sd;
+	struct v4l2_rect *r;
+
+
+	if (win->index >= S3C_FB_MAX_WIN)
+		return -ENODEV;
+
+	for (i = 0; i < S3C_FB_MAX_WIN_SOURCES; i++) {
+		if (!windata->fifo_sources[i])
+			continue;
+		win_sd = kzalloc(sizeof(struct s3c_fb_win_sd), GFP_KERNEL);
+		if (win_sd == NULL)
+			return -ENOMEM;
+		win_sd->index = i;
+		win_sd->win = win;
+		win_sd->link = windata->fifo_sources[i];
+		win_sd->streaming = 0;
+		v4l2_subdev_init(&win_sd->sd, &v4l2_sd_fb_ops);
+		snprintf(win_sd->sd.name, sizeof(win_sd->sd.name),
+			 "s3cfb-local");
+
+		/* hook up pointer to slave device */
+		win_sd->link->sub_dev = &win_sd->sd;
+		win->sources[i] = win_sd;
+
+		/* set default rectangle to current window */
+		s3c_fb_get_osd(win, &win_sd->default_rect.c);
+
+		/* set fimc fifo output rectangle to current window */
+		r = &win_sd->osd_rect.c;
+		r->width = windata->win_mode.xres;
+		r->height = windata->win_mode.yres;
+		r->left = 0;
+		r->top = 0;
+
+		win_sd->fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_RGB24;
+
+		dev_dbg(sfb->dev, "%s(): l:%d t:%d w:%d h:%d",
+			__func__, r->left, r->top, r->width, r->height);
+
+		dev_dbg(sfb->dev, "subdevice %d registered at window %d\n",
+			i, win->index);
+	}
+	return 0;
+}
+
 /**
  * s3c_fb_release_win() - release resources for a framebuffer window.
  * @win: The window to cleanup the resources for.
@@ -1099,6 +1530,7 @@ static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
 static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
 {
 	if (win->fbinfo) {
+		s3c_fb_unregister_subdevices(win);
 		unregister_framebuffer(win->fbinfo);
 		if (&win->fbinfo->cmap)
 			fb_dealloc_cmap(&win->fbinfo->cmap);
@@ -1157,6 +1589,7 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 	win->windata = windata;
 	win->index = win_no;
 	win->palette_buffer = (u32 *)(win + 1);
+	win->local_path = 0;
 
 	ret = s3c_fb_alloc_memory(sfb, win);
 	if (ret) {
@@ -1212,11 +1645,16 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 	else
 		dev_err(sfb->dev, "failed to allocate fb cmap\n");
 
+	/* run the check_var and set_par on our configuration. */
 	s3c_fb_set_par(fbinfo);
 
-	dev_dbg(sfb->dev, "about to register framebuffer\n");
+	ret =  s3c_fb_register_subdevices(win);
+	if (ret < 0) {
+		dev_err(sfb->dev, "failed to register s3c-fb subdevices\n");
+		return ret;
+	}
 
-	/* run the check_var and set_par on our configuration. */
+	dev_dbg(sfb->dev, "about to register framebuffer\n");
 
 	ret = register_framebuffer(fbinfo);
 	if (ret < 0) {
-- 
1.7.0.4



From s.nawrocki at samsung.com  Wed Jun 16 06:12:00 2010
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Wed, 16 Jun 2010 12:12:00 +0200
Subject: [PATCH 4/7] v4l: Add Samsung FIMC (video postprocessor) driver
In-Reply-To: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
References: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
Message-ID: <1276683123-30224-5-git-send-email-s.nawrocki@samsung.com>

This driver implements memory to memory (DMA-DMA) operations in v4l2-mem2mem
framework, including color conversion, image resizing, flipping and rotation.

For direct local fifo path to lcd controller, i.e. to enable interworking
between framebuffer and fimc driver v4l2-subdev API is used.
Framebuffer registers its fifo path subdevice per each window and initializes
corresponding s3c_fifo_link:sub_dev entry in the platform so fimc driver
is able acquire corresponding framebuffer subdevice, when its video device
is opened. This enables mapping fifo source and target device drivers according
to existing data paths in hardware.

Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Reviewed-by: Pawel Osciak <p.osciak at samsung.com>
Reviewed-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 drivers/media/video/Kconfig                  |   18 +
 drivers/media/video/Makefile                 |    1 +
 drivers/media/video/samsung-fimc/Makefile    |    3 +
 drivers/media/video/samsung-fimc/fimc-core.c | 1612 ++++++++++++++++++++++++++
 drivers/media/video/samsung-fimc/fimc-core.h |  509 ++++++++
 drivers/media/video/samsung-fimc/fimc-fifo.c |  822 +++++++++++++
 drivers/media/video/samsung-fimc/fimc-reg.c  |  572 +++++++++
 include/linux/videodev2.h                    |    1 +
 8 files changed, 3538 insertions(+), 0 deletions(-)
 create mode 100644 drivers/media/video/samsung-fimc/Makefile
 create mode 100644 drivers/media/video/samsung-fimc/fimc-core.c
 create mode 100644 drivers/media/video/samsung-fimc/fimc-core.h
 create mode 100644 drivers/media/video/samsung-fimc/fimc-fifo.c
 create mode 100644 drivers/media/video/samsung-fimc/fimc-reg.c

diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index bdbc9d3..5cf2534 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -969,6 +969,15 @@ config VIDEO_OMAP2
 	---help---
 	  This is a v4l2 driver for the TI OMAP2 camera capture interface
 
+config  VIDEO_SAMSUNG_FIMC
+	tristate "Samsung S5P Camera Interface (video postprocessor) driver"
+	depends on VIDEO_DEV && VIDEO_V4L2
+	select VIDEOBUF_DMA_CONTIG
+	select V4L2_MEM2MEM_DEV
+	default n
+	help
+	  This is a v4l2 driver the Samsung S5P camera capture interface
+
 #
 # USB Multimedia device configuration
 #
@@ -1150,4 +1159,13 @@ config VIDEO_MEM2MEM_TESTDEV
 	  This is a virtual test device for the memory-to-memory driver
 	  framework.
 
+config  VIDEO_SAMSUNG_FIMC
+	tristate "Samsung S5PV210 Camera Interface (video postprocessor) driver"
+	depends on VIDEO_DEV && VIDEO_V4L2
+	select VIDEOBUF_DMA_CONTIG
+	select V4L2_MEM2MEM_DEV
+	default n
+	help
+		Samsung S5PV210 camera interface (video postprocessor) driver.
+
 endif # V4L_MEM2MEM_DRIVERS
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index cc93859..522d037 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -165,6 +165,7 @@ obj-$(CONFIG_VIDEO_MX1)			+= mx1_camera.o
 obj-$(CONFIG_VIDEO_MX3)			+= mx3_camera.o
 obj-$(CONFIG_VIDEO_PXA27x)		+= pxa_camera.o
 obj-$(CONFIG_VIDEO_SH_MOBILE_CEU)	+= sh_mobile_ceu_camera.o
+obj-$(CONFIG_VIDEO_SAMSUNG_FIMC) 	+= samsung-fimc/
 
 obj-$(CONFIG_ARCH_DAVINCI)		+= davinci/
 
diff --git a/drivers/media/video/samsung-fimc/Makefile b/drivers/media/video/samsung-fimc/Makefile
new file mode 100644
index 0000000..c5c40c1
--- /dev/null
+++ b/drivers/media/video/samsung-fimc/Makefile
@@ -0,0 +1,3 @@
+
+obj-$(CONFIG_VIDEO_SAMSUNG_FIMC) := samsung-fimc.o
+samsung-fimc-y := fimc-core.o fimc-reg.o fimc-fifo.o
diff --git a/drivers/media/video/samsung-fimc/fimc-core.c b/drivers/media/video/samsung-fimc/fimc-core.c
new file mode 100644
index 0000000..23b95a8
--- /dev/null
+++ b/drivers/media/video/samsung-fimc/fimc-core.c
@@ -0,0 +1,1612 @@
+/*
+ * S5P camera interface (video postprocessor) driver
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Sylwester Nawrocki, s.nawrocki at samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/bug.h>
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+
+#include <linux/videodev2.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/videobuf-core.h>
+#include <media/videobuf-dma-contig.h>
+
+#include "fimc-core.h"
+
+
+struct fimc_fmt fimc_formats[] = {
+	{
+		.name	= "RGB565",
+		.fourcc	= V4L2_PIX_FMT_RGB565X,
+		.depth	= 16,
+		.color	= S5P_FIMC_RGB565,
+		.buff_cnt = 1,
+		.planes_cnt = 1
+	}, {
+		.name	= "RGB666",
+		.fourcc	= V4L2_PIX_FMT_RGB666,
+		.depth	= 32,
+		.color	= S5P_FIMC_RGB666,
+		.buff_cnt = 1,
+		.planes_cnt = 1
+	}, {
+		.name = "XRGB-8-8-8-8, 24 bpp",
+		.fourcc	= V4L2_PIX_FMT_RGB24,
+		.depth = 32,
+		.color	= S5P_FIMC_RGB888,
+		.buff_cnt = 1,
+		.planes_cnt = 1
+	}, {
+		.name	= "YUV 4:2:2 packed, YCbYCr",
+		.fourcc	= V4L2_PIX_FMT_YUYV,
+		.depth	= 16,
+		.color	= S5P_FIMC_YCBYCR422,
+		.buff_cnt = 1,
+		.planes_cnt = 1
+		}, {
+		.name	= "YUV 4:2:2 packed, CbYCrY",
+		.fourcc	= V4L2_PIX_FMT_UYVY,
+		.depth	= 16,
+		.color	= S5P_FIMC_CBYCRY422,
+		.buff_cnt = 1,
+		.planes_cnt = 1
+	}, {
+		.name	= "YUV 4:2:2 packed, CrYCbY",
+		.fourcc	= V4L2_PIX_FMT_VYUY,
+		.depth	= 16,
+		.color	= S5P_FIMC_CRYCBY422,
+		.buff_cnt = 1,
+		.planes_cnt = 1
+	}, {
+		.name	= "YUV 4:2:2 packed, YCrYCb",
+		.fourcc	= V4L2_PIX_FMT_YVYU,
+		.depth	= 16,
+		.color	= S5P_FIMC_YCRYCB422,
+		.buff_cnt = 1,
+		.planes_cnt = 1
+	}, {
+		.name	= "YUV 4:2:2 planar, Y/Cb/Cr",
+		.fourcc	= V4L2_PIX_FMT_YUV422P,
+		.depth	= 12,
+		.color	= S5P_FIMC_YCBCR422,
+		.buff_cnt = 1,
+		.planes_cnt = 3
+	}, {
+		.name	= "YUV 4:2:2 planar, Y/CbCr",
+		.fourcc	= V4L2_PIX_FMT_NV16,
+		.depth	= 16,
+		.color	= S5P_FIMC_YCBCR422,
+		.buff_cnt = 1,
+		.planes_cnt = 2
+	}, {
+		.name	= "YUV 4:2:2 planar, Y/CrCb",
+		.fourcc	= V4L2_PIX_FMT_NV61,
+		.depth	= 16,
+		.color	= S5P_FIMC_RGB565,
+		.buff_cnt = 1,
+		.planes_cnt = 2
+	}, {
+		.name	= "YUV 4:2:0 planar, YCbCr",
+		.fourcc	= V4L2_PIX_FMT_YUV420,
+		.depth	= 12,
+		.color	= S5P_FIMC_YCBCR420,
+		.buff_cnt = 1,
+		.planes_cnt = 3
+	}, {
+		.name	= "YUV 4:2:0 planar, Y/CbCr",
+		.fourcc	= V4L2_PIX_FMT_NV12,
+		.depth	= 12,
+		.color	= S5P_FIMC_YCBCR420,
+		.buff_cnt = 1,
+		.planes_cnt = 2
+	}
+ };
+
+static struct v4l2_queryctrl s5p_fimc_ctrls[] = {
+	{
+		.id		= V4L2_CID_HFLIP,
+		.type		= V4L2_CTRL_TYPE_BOOLEAN,
+		.name		= "Horizontal flip",
+		.minimum	= 0,
+		.maximum	= 1,
+		.default_value	= 0,
+	},
+	{
+		.id		= V4L2_CID_VFLIP,
+		.type		= V4L2_CTRL_TYPE_BOOLEAN,
+		.name		= "Vertical flip",
+		.minimum	= 0,
+		.maximum	= 1,
+		.default_value	= 0,
+	},
+	{
+		.id		= V4L2_CID_ROTATE,
+		.type		= V4L2_CTRL_TYPE_INTEGER,
+		.name		= "Rotation (CCW)",
+		.minimum	= 0,
+		.maximum	= 270,
+		.step		= 90,
+		.default_value	= 0,
+	},
+};
+
+
+static struct v4l2_queryctrl *get_ctrl(int id)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(s5p_fimc_ctrls); ++i)
+		if (id == s5p_fimc_ctrls[i].id)
+			return &s5p_fimc_ctrls[i];
+	return NULL;
+}
+
+int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f)
+{
+	int ret = 0;
+	if (r->width > f->width) {
+		if (f->width > (r->width * SCALER_MAX_HRATIO))
+			ret = 1;
+	} else {
+		if ((f->width * SCALER_MAX_HRATIO) < r->width)
+			ret = 1;
+	}
+
+	if (r->height > f->height) {
+		if (f->height > (r->height * SCALER_MAX_VRATIO))
+			ret = 1;
+	} else {
+		if ((f->height * SCALER_MAX_VRATIO) < r->height)
+			ret = 1;
+	}
+
+	return ret;
+}
+
+static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
+{
+	if (src >= tar * 64) {
+		return -EINVAL;
+	} else if (src >= tar * 32) {
+		*ratio = 32;
+		*shift = 5;
+	} else if (src >= tar * 16) {
+		*ratio = 16;
+		*shift = 4;
+	} else if (src >= tar * 8) {
+		*ratio = 8;
+		*shift = 3;
+	} else if (src >= tar * 4) {
+		*ratio = 4;
+		*shift = 2;
+	} else if (src >= tar * 2) {
+		*ratio = 2;
+		*shift = 1;
+	} else {
+		*ratio = 1;
+		*shift = 0;
+	}
+
+	return 0;
+}
+
+int fimc_set_scaler_info(struct fimc_ctx *ctx)
+{
+	struct fimc_scaler *sc = &ctx->scaler;
+	struct fimc_dma_offset *d_ofs = &ctx->s_frame.dma_offset;
+	int tx, ty, sx, sy;
+	int width, height, h_ofs, v_ofs;
+	int ret;
+	struct fimc_frame *src_frame = &ctx->s_frame;
+	struct fimc_frame *dst_frame = &ctx->d_frame;
+
+	if (ctx->in_path == FIMC_DMA) {
+		if ((ctx->rotation == 90 || ctx->rotation == 270)
+			&& FIMC_LCDFIFO == ctx->out_path) {
+			/* here we are using only the input rotator */
+			width = src_frame->height;
+			height = src_frame->width;
+			h_ofs = d_ofs->y_v;
+			v_ofs = d_ofs->y_h;
+		} else {
+			width = src_frame->width;
+			height = src_frame->height;
+			h_ofs = d_ofs->y_h;
+			v_ofs = d_ofs->y_v;
+		}
+	} else {
+		width = src_frame->width;
+		height = src_frame->height;
+		h_ofs = d_ofs->y_h;
+		v_ofs = d_ofs->y_v;
+	}
+
+	tx = dst_frame->width;
+	ty = dst_frame->height;
+
+	if (tx <= 0 || ty <= 0) {
+		v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
+			"invalid target size: %d %d", tx, ty);
+		return -EINVAL;
+	}
+
+	sx = width;
+	sy = height;
+
+	sc->real_width = width;
+	sc->real_height = height;
+
+	if (sx <= 0 || sy <= 0) {
+		err("invalid source size: s: %d %d, t: %d %d", sx, sy, tx, ty);
+		return -EINVAL;
+	}
+
+	dbg("sx= %d, sy= %d, tx= %d, ty= %d", sx, sy, tx, ty);
+
+	ret = fimc_get_scaler_factor(sx, tx,
+			  &sc->pre_hratio, &sc->hfactor);
+	if (ret)
+		return ret;
+
+	ret = fimc_get_scaler_factor(sy, ty,
+			  &sc->pre_vratio, &sc->vfactor);
+	if (ret)
+		return ret;
+
+	sc->pre_dst_width = sx/sc->pre_hratio;
+	sc->pre_dst_height = sy/sc->pre_vratio;
+
+	sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
+	sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
+
+	dbg("sc->main_hratio= %d, sc->main_vratio= %d",
+		sc->main_hratio, sc->main_vratio);
+	dbg("sc->hfactor= %d, sc->vfactor= %d", sc->hfactor, sc->vfactor);
+
+	sc->scaleup_h = (tx >= sx) ? 1 : 0;
+	sc->scaleup_v = (ty >= sy) ? 1 : 0;
+
+	/* check to see if input and output size/format differ */
+	if (src_frame->fmt->color == dst_frame->fmt->color
+		&& src_frame->width == dst_frame->width
+		&& src_frame->height == dst_frame->height)
+		sc->copy_mode = 1;
+	else
+		sc->copy_mode = 0;
+
+	return 0;
+}
+
+
+static irqreturn_t fimc_isr(int irq, void *priv)
+{
+	struct fimc_ctx *ctx;
+	struct fimc_vid_buffer *src_buf, *dst_buf;
+	struct fimc_dev *dev = (struct fimc_dev *)priv;
+	struct v4l2_fimc_outp_dev *outp = &dev->outp;
+
+	BUG_ON(!dev);
+	fimc_hw_clear_irq(dev);
+
+	spin_lock(&dev->slock);
+
+	/* v4l2-mem2mem */
+	if (test_and_clear_bit(ST_M2M_PEND, &dev->state)) {
+		ctx = v4l2_m2m_get_curr_priv(dev->m2m.m2m_dev);
+		if (!ctx || !ctx->m2m_ctx)
+			goto isr_unlock;
+		src_buf = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
+		dst_buf = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
+		if (src_buf && dst_buf) {
+			spin_lock(&dev->irqlock);
+			src_buf->vb.state = dst_buf->vb.state =  VIDEOBUF_DONE;
+			wake_up(&src_buf->vb.done);
+			wake_up(&dst_buf->vb.done);
+			spin_unlock(&dev->irqlock);
+			v4l2_m2m_job_finish(dev->m2m.m2m_dev, ctx->m2m_ctx);
+		}
+		goto isr_unlock;
+	}
+
+	/* local fifo mode */
+	fimc_hw_reset_fifo_ov(dev);
+
+	if (test_bit(ST_LCDFIFO_RUN, &dev->state)) {
+
+		/* schedule next buffer in hw if there is any available */
+		if (!list_empty(&outp->buf_q)) {
+			ctx = outp->ctx;
+
+			spin_lock(&dev->irqlock);
+			outp->curr_buf->vb.state = VIDEOBUF_DONE;
+			spin_unlock(&dev->irqlock);
+			wake_up(&outp->curr_buf->vb.done);
+
+			outp->curr_buf = list_entry(outp->buf_q.next,
+				struct fimc_vid_buffer, vb.queue);
+			outp->curr_buf->vb.state = VIDEOBUF_ACTIVE;
+			list_del(&outp->curr_buf->vb.queue);
+
+			spin_lock(&ctx->slock);
+			fimc_prepare_addr(ctx, outp->curr_buf,
+					  V4L2_BUF_TYPE_VIDEO_OUTPUT);
+			/* set source buffer address in hw */
+			fimc_hw_set_input_addr(dev, &ctx->s_frame.paddr);
+			spin_unlock(&ctx->slock);
+		}
+
+	} else if (test_and_clear_bit(ST_LCDFIFO_PEND, &dev->state)) {
+
+		set_bit(ST_LCDFIFO_RUN, &dev->state);
+		wake_up(&dev->irq_queue);
+	}
+
+isr_unlock:
+	spin_unlock(&dev->slock);
+	return IRQ_HANDLED;
+}
+
+
+static void fimc_dma_run(void *priv)
+{
+	struct fimc_ctx *ctx = priv;
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct fimc_frame *frame;
+	u32	ret;
+
+	if (!ctx || ctx->out_path != FIMC_DMA)
+		return;
+
+	set_bit(ST_M2M_PEND, &dev->state);
+
+	ctx->flags |= (FIMC_SRC_ADDR | FIMC_DST_ADDR);
+	ret = fimc_prepare_config(ctx, ctx->flags);
+	if (ret) {
+		err("Wrong configuration");
+		return;
+	}
+
+	if (dev->m2m.ctx != ctx)
+		ctx->flags |= FIMC_PARAMS;
+
+	frame = &ctx->s_frame;
+	dbg("SRC: width= %d, height= %d, f_width= %d, f_height= %d "
+		"offs_h= %d, offs_v= %d",
+		frame->width, frame->height,
+		frame->f_width, frame->f_height,
+		frame->offs_h, frame->offs_v);
+
+	frame = &ctx->d_frame;
+	dbg("DST: width= %d, height= %d, f_width= %d, f_height= %d "
+		"offs_h= %d, offs_v= %d",
+		frame->width, frame->height,
+		frame->f_width, frame->f_height,
+		frame->offs_h, frame->offs_v);
+
+	fimc_hw_set_input_addr(dev, &ctx->s_frame.paddr);
+
+	if (ctx->flags & FIMC_PARAMS) {
+		fimc_hw_set_input_path(ctx);
+		fimc_hw_set_in_dma(ctx);
+		if (fimc_set_scaler_info(ctx)) {
+			err("scaler configuration error");
+			return;
+		}
+		fimc_hw_set_prescaler(ctx);
+		fimc_hw_set_scaler(ctx);
+		fimc_hw_set_target_format(ctx);
+		fimc_hw_set_rotation(ctx);
+		fimc_hw_set_effect(ctx);
+	}
+
+	fimc_hw_set_output_path(ctx);
+	if (ctx->flags & (FIMC_DST_ADDR | FIMC_PARAMS))
+		fimc_hw_set_output_addr(dev, &ctx->d_frame.paddr);
+
+	if (ctx->flags & FIMC_PARAMS)
+		fimc_hw_set_out_dma(ctx);
+
+	if (ctx->scaler.enabled)
+		fimc_hw_start_scaler(dev);
+	fimc_hw_en_capture(ctx);
+
+	ctx->flags = 0;
+
+	if (ctx->in_path == FIMC_DMA)
+		fimc_hw_start_in_dma(dev);
+
+	dev->m2m.ctx = ctx;
+}
+
+static void fimc_job_abort(void *priv)
+{
+
+}
+
+/* set order for 1 and 2 plane YCBCR 4:2:2 formats */
+static void fimc_set_yuv_order(struct fimc_ctx *ctx)
+{
+	/* the one only mode supported in SoC */
+	ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
+	ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
+
+	/* set order for 1 plane input formats */
+	switch (ctx->s_frame.fmt->color) {
+	case S5P_FIMC_YCRYCB422:
+		ctx->in_order_1p = S5P_FIMC_IN_YCRYCB;
+		break;
+	case S5P_FIMC_CBYCRY422:
+		ctx->in_order_1p = S5P_FIMC_IN_CBYCRY;
+		break;
+	case S5P_FIMC_CRYCBY422:
+		ctx->in_order_1p = S5P_FIMC_IN_CRYCBY;
+		break;
+	case S5P_FIMC_YCBYCR422:
+	default:
+		ctx->in_order_1p = S5P_FIMC_IN_YCBYCR;
+		break;
+	}
+	dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
+
+	switch (ctx->d_frame.fmt->color) {
+	case S5P_FIMC_YCRYCB422:
+		ctx->out_order_1p = S5P_FIMC_OUT_YCRYCB;
+		break;
+	case S5P_FIMC_CBYCRY422:
+		ctx->out_order_1p = S5P_FIMC_OUT_CBYCRY;
+		break;
+	case S5P_FIMC_CRYCBY422:
+		ctx->out_order_1p = S5P_FIMC_OUT_CRYCBY;
+		break;
+	case S5P_FIMC_YCBYCR422:
+	default:
+		ctx->out_order_1p = S5P_FIMC_OUT_YCBYCR;
+		break;
+	}
+	dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
+}
+
+/*
+ * This function check dimensions, operation and color mode and
+ * pre-calculates offset and scaling coefficients.
+ * Returns 0 if dimensions are valid, non zero otherwise.
+ * Does not alter any FIMC registers.
+ */
+int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags)
+{
+	struct fimc_frame *src_frame, *dst_frame;
+	struct fimc_vid_buffer *buf = NULL;
+	int ret = 0;
+
+	dbg("flags= 0x%X", flags);
+
+	src_frame = &ctx->s_frame;
+	dst_frame = &ctx->d_frame;
+
+	if (flags & FIMC_PARAMS) {
+		if ((FIMC_DMA == ctx->out_path) &&
+			(ctx->rotation == 90 || ctx->rotation == 270)) {
+			swap(dst_frame->f_width, dst_frame->f_height);
+			swap(dst_frame->width, dst_frame->height);
+		}
+
+		/* prepare the output offset related attributes for scaler */
+		dst_frame->dma_offset.y_h = dst_frame->offs_h
+			 * (dst_frame->fmt->depth >> 3);
+		dst_frame->dma_offset.y_v = dst_frame->offs_v;
+
+		dst_frame->dma_offset.cb_h = dst_frame->offs_h;
+		dst_frame->dma_offset.cb_v = dst_frame->offs_v;
+
+		dst_frame->dma_offset.cr_h = dst_frame->offs_h;
+		dst_frame->dma_offset.cr_v = dst_frame->offs_v;
+
+		if (3 == dst_frame->fmt->planes_cnt) {
+			dst_frame->dma_offset.cb_h >>= 1;
+			dst_frame->dma_offset.cb_v >>= 1;
+			dst_frame->dma_offset.cr_h >>= 1;
+			dst_frame->dma_offset.cr_v >>= 1;
+		}
+
+		dbg("OUT OFFSET: color= %d, y_h= %d, y_v= %d",
+			dst_frame->fmt->color,
+			dst_frame->dma_offset.y_h, dst_frame->dma_offset.y_v);
+
+		/* prepare the input offset related attributes for scaler */
+		src_frame->dma_offset.y_h = src_frame->offs_h
+			* (src_frame->fmt->depth >> 3);
+		src_frame->dma_offset.y_v = src_frame->offs_v;
+
+		src_frame->dma_offset.cb_h = src_frame->offs_h;
+		src_frame->dma_offset.cb_v = src_frame->offs_v;
+
+		src_frame->dma_offset.cr_h = src_frame->offs_h;
+		src_frame->dma_offset.cr_v = src_frame->offs_v;
+
+		if (3 == src_frame->fmt->planes_cnt) {
+			src_frame->dma_offset.cb_h >>= 1;
+			src_frame->dma_offset.cb_v >>= 1;
+			src_frame->dma_offset.cr_h >>= 1;
+			src_frame->dma_offset.cr_v >>= 1;
+		}
+
+		dbg("IN OFFSET: color= %d, y_h= %d, y_v= %d",
+			src_frame->fmt->color, src_frame->dma_offset.y_h,
+			src_frame->dma_offset.y_v);
+
+		fimc_set_yuv_order(ctx);
+
+		/* Check against the scaler ratio */
+		if (src_frame->height > SCALER_MAX_VRATIO*dst_frame->height ||
+			src_frame->width > SCALER_MAX_HRATIO*dst_frame->width) {
+				err("Out of the scaler range");
+				return -EINVAL;
+		}
+	} /* if (flags & FIMC_PARAMS) */
+
+	/* input DMA mode is not allowed when the scaler is disabled */
+	ctx->scaler.enabled = 1;
+
+	if (flags & FIMC_SRC_ADDR) {
+		buf = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
+		ret = fimc_prepare_addr(ctx, buf,
+			V4L2_BUF_TYPE_VIDEO_OUTPUT);
+		if (ret)
+			return ret;
+	}
+
+	if (flags & FIMC_DST_ADDR) {
+		buf = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
+		ret = fimc_prepare_addr(ctx, buf,
+			V4L2_BUF_TYPE_VIDEO_CAPTURE);
+	}
+
+	return ret;
+}
+
+/* the color format (planes_cnt, buff_cnt) must be already configured */
+int fimc_prepare_addr(struct fimc_ctx *ctx,
+		struct fimc_vid_buffer *buf, enum v4l2_buf_type type)
+{
+	int ret = 0;
+	struct fimc_frame *frame;
+	struct fimc_addr *paddr;
+	u32 pix_size;
+
+	ctx_m2m_get_frame(frame, ctx, type);
+	paddr = &frame->paddr;
+
+	if (!buf)
+		return -EINVAL;
+
+	pix_size = frame->width * frame->height;
+
+	dbg("%d buff_cnt, planes_cnt= %d, frame->size= %d, pix_size= %d",
+		frame->fmt->buff_cnt, frame->fmt->planes_cnt,
+		frame->size, pix_size);
+
+	if (frame->fmt->buff_cnt == 1) {
+		paddr->y = videobuf_to_dma_contig(&buf->vb);
+		switch (frame->fmt->planes_cnt) {
+		case 1:
+			paddr->cb = 0;
+			paddr->cr = 0;
+			break;
+		case 2:
+			/* decompose Y into Y/Cb */
+			paddr->cb = (u32)(paddr->y + pix_size);
+			paddr->cr = 0;
+			break;
+		case 3:
+			paddr->cb = (u32)(paddr->y + pix_size);
+			/* decompose Y into Y/Cb/Cr */
+			if (S5P_FIMC_YCBCR420 == frame->fmt->color)
+				paddr->cr = (u32)(paddr->cb
+						+ (pix_size >> 2));
+			else /* 422 */
+				paddr->cr = (u32)(paddr->cb
+						+ (pix_size >> 1));
+			break;
+		default:
+			return -EINVAL;
+		}
+	}
+
+	dbg("PHYS_ADDR: type= %d, y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
+	type, paddr->y, paddr->cb, paddr->cr, ret);
+
+	return ret;
+}
+
+static unsigned int get_plane_size(struct fimc_frame *frame, unsigned int plane)
+{
+	unsigned long size = 0;
+
+	if (frame == NULL)
+		return -EINVAL;
+
+	if (plane >= frame->fmt->planes_cnt)
+		return 0;
+
+	if (1 == frame->fmt->planes_cnt) {
+		size = (frame->width * frame->height * frame->fmt->depth) >> 3;
+	} else if (frame->fmt->planes_cnt <= 3) {
+		switch (plane) {
+		case 0:
+			size = frame->width * frame->height;
+			break;
+		case 1:	/* fall through */
+		case 2:
+			if (S5P_FIMC_YCBCR420 == frame->fmt->color
+				&& 2 != frame->fmt->planes_cnt)
+				size = (frame->width * frame->height) >> 2;
+			else /* 422 */
+				size = (frame->width * frame->height) >> 1;
+			break;
+		}
+	} else {
+		size = 0;
+	}
+
+	return size;
+}
+
+static void fimc_buf_release(struct videobuf_queue *vq,
+				    struct videobuf_buffer *vb)
+{
+	videobuf_dma_contig_free(vq, vb);
+	vb->state = VIDEOBUF_NEEDS_INIT;
+}
+
+static int fimc_buf_setup(struct videobuf_queue *vq, unsigned int *count,
+				unsigned int *size)
+{
+	struct fimc_ctx *ctx = vq->priv_data;
+	struct fimc_frame *frame;
+
+	ctx_m2m_get_frame(frame, ctx, vq->type);
+
+	*size = (frame->width * frame->height * frame->fmt->depth) >> 3;
+	if (0 == *count)
+		*count = 1;
+	return 0;
+}
+
+static int fimc_buf_prepare(struct videobuf_queue *vq,
+		struct videobuf_buffer *vb, enum v4l2_field field)
+{
+	struct fimc_ctx *ctx = vq->priv_data;
+	struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
+	struct fimc_frame *frame;
+	int ret;
+
+	ctx_m2m_get_frame(frame, ctx, vq->type);
+
+	if (vb->baddr) {
+		if (vb->bsize < frame->size) {
+			v4l2_err(v4l2_dev,
+				"User-provided buffer too small (%d < %d)\n",
+				 vb->bsize, frame->size);
+			WARN_ON(1);
+			return -EINVAL;
+		}
+	} else if (vb->state != VIDEOBUF_NEEDS_INIT
+		   && vb->bsize < frame->size) {
+		return -EINVAL;
+	}
+
+	vb->width       = frame->width;
+	vb->height      = frame->height;
+	vb->bytesperline = (frame->width * frame->fmt->depth) >> 3;
+	vb->size        = frame->size;
+	vb->field       = field;
+
+	if (VIDEOBUF_NEEDS_INIT == vb->state) {
+		ret = videobuf_iolock(vq, vb, NULL);
+		if (ret) {
+			v4l2_err(v4l2_dev, "Iolock failed\n");
+			fimc_buf_release(vq, vb);
+			return ret;
+		}
+	}
+	vb->state = VIDEOBUF_PREPARED;
+
+	return 0;
+}
+
+static void fimc_buf_queue(struct videobuf_queue *vq,
+				  struct videobuf_buffer *vb)
+{
+	unsigned long flags;
+	struct fimc_ctx *ctx = vq->priv_data;
+	struct fimc_dev *dev = ctx->fimc_dev;
+
+
+	if (ctx->out_path != FIMC_LCDFIFO) {
+		v4l2_m2m_buf_queue(ctx->m2m_ctx, vq, vb);
+	} else {
+		/* queue the buffer and start transaction if required */
+		spin_lock_irqsave(&ctx->slock, flags);
+		list_add_tail(&vb->queue, &dev->outp.buf_q);
+		vb->state = VIDEOBUF_QUEUED;
+		spin_unlock_irqrestore(&ctx->slock, flags);
+
+		spin_lock_irqsave(&dev->slock, flags);
+		if (!test_bit(ST_LCDFIFO_RUN, &dev->state)) {
+			set_bit(ST_LCDFIFO_PEND, &dev->state);
+			queue_work(dev->work_queue, &dev->outp.work);
+		}
+		spin_unlock_irqrestore(&dev->slock, flags);
+	}
+}
+
+struct videobuf_queue_ops fimc_qops = {
+	.buf_setup	= fimc_buf_setup,
+	.buf_prepare	= fimc_buf_prepare,
+	.buf_queue	= fimc_buf_queue,
+	.buf_release	= fimc_buf_release,
+};
+
+static int fimc_m2m_querycap(struct file *file, void *priv,
+			   struct v4l2_capability *cap)
+{
+	struct fimc_ctx *ctx = file->private_data;
+	struct fimc_dev *dev = ctx->fimc_dev;
+
+	strncpy(cap->driver, dev->pdev->name, sizeof(cap->driver) - 1);
+	strncpy(cap->card, dev->pdev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->version = KERNEL_VERSION(1, 0, 0);
+	cap->capabilities = V4L2_CAP_STREAMING |
+		V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_VIDEO_OUTPUT;
+
+	return 0;
+}
+
+int fimc_m2m_enum_fmt(struct file *file, void *priv, struct v4l2_fmtdesc *f)
+{
+	struct fimc_fmt *fmt;
+
+	if (f->index >= ARRAY_SIZE(fimc_formats))
+		return -EINVAL;
+
+	fmt = &fimc_formats[f->index];
+	strncpy(f->description, fmt->name, sizeof(f->description) - 1);
+	f->pixelformat = fmt->fourcc;
+	return 0;
+}
+
+static int fimc_m2m_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
+{
+	struct fimc_ctx *ctx = priv;
+	struct fimc_frame *frame;
+
+	ctx_m2m_get_frame(frame, ctx, f->type);
+
+	f->fmt.pix.width	= frame->width;
+	f->fmt.pix.height	= frame->height;
+	f->fmt.pix.field	= V4L2_FIELD_NONE;
+	f->fmt.pix.pixelformat	= frame->fmt->fourcc;
+
+	return 0;
+}
+
+struct fimc_fmt *find_format(struct v4l2_format *f)
+{
+	struct fimc_fmt *fmt;
+	unsigned int i;
+
+	for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
+		fmt = &fimc_formats[i];
+		if (fmt->fourcc == f->fmt.pix.pixelformat)
+			break;
+	}
+	if (i == ARRAY_SIZE(fimc_formats))
+		return NULL;
+
+	return fmt;
+}
+
+static int fimc_m2m_try_fmt(struct file *file, void *priv,
+			     struct v4l2_format *f)
+{
+	u32 max_width, max_height;
+	struct fimc_fmt *fmt;
+	struct fimc_ctx *ctx = priv;
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct v4l2_pix_format *pix = &f->fmt.pix;
+	u32 mod_x, mod_y;
+
+	fmt = find_format(f);
+	if (!fmt) {
+		v4l2_err(&dev->m2m.v4l2_dev,
+		"Fourcc format (0x%08x) invalid.\n",
+			 pix->pixelformat);
+		return -EINVAL;
+	}
+
+	if (pix->field == V4L2_FIELD_ANY)
+		pix->field = V4L2_FIELD_NONE;
+	else if (V4L2_FIELD_NONE != pix->field)
+		return -EINVAL;
+
+	if (V4L2_BUF_TYPE_VIDEO_OUTPUT == f->type) {
+		max_width = dev->pldata->scaler_dis_w;
+		max_height = dev->pldata->scaler_dis_w;
+	} else if (V4L2_BUF_TYPE_VIDEO_CAPTURE == f->type) {
+		max_width = dev->pldata->out_rot_dis_w;
+		max_height = dev->pldata->out_rot_dis_w;
+	} else {
+		err("Wrong stream type (%d)", f->type);
+		return -EINVAL;
+	}
+
+	dbg("max_w= %d, max_h= %d", max_width, max_height);
+
+	if (pix->height > max_height)
+		pix->height = max_height;
+	if (pix->width > max_width)
+		pix->width = max_width;
+
+	if (tiled_fmt(fmt)) {
+		mod_x = 64; /* 64x32 tile */
+		mod_y = 32;
+	} else {
+		mod_x = DMA_MIN_SIZE;
+		mod_y = DMA_MIN_SIZE;
+	}
+
+	dbg("mod_x= 0x%X, mod_y= 0x%X", mod_x, mod_y);
+
+	pix->width = (pix->width == 0) ? mod_x : ALIGN(pix->width, mod_x);
+	pix->height = (pix->height == 0) ? mod_y : ALIGN(pix->height, mod_y);
+
+	if (!pix->bytesperline) {
+		pix->bytesperline = (pix->width * fmt->depth) >> 3;
+	} else {
+		u32 f_width = pix->bytesperline*8/fmt->depth;
+		if (f_width > max_width)
+			pix->bytesperline = (max_width * fmt->depth) >> 3;
+	}
+
+	if (!pix->sizeimage)
+		pix->sizeimage = pix->height * pix->bytesperline;
+
+	dbg("pix->bytesperline= %d, fmt->depth= %d",
+	    pix->bytesperline, fmt->depth);
+
+	return 0;
+}
+
+
+static int fimc_m2m_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
+{
+	struct fimc_frame *frame;
+	struct v4l2_pix_format *pix;
+	struct videobuf_queue	*src_vq = NULL,
+				*dst_vq = NULL;
+	struct fimc_ctx *ctx = priv;
+	struct v4l2_device *v4l2_dev = &ctx->fimc_dev->m2m.v4l2_dev;
+	int ret = 0;
+
+	BUG_ON(!ctx);
+
+	ret = fimc_m2m_try_fmt(file, priv, f);
+	if (ret)
+		return ret;
+
+	mutex_lock(&ctx->fimc_dev->lock);
+
+	src_vq = v4l2_m2m_get_src_vq(ctx->m2m_ctx);
+	dst_vq = v4l2_m2m_get_dst_vq(ctx->m2m_ctx);
+
+	mutex_lock(&src_vq->vb_lock);
+	mutex_lock(&dst_vq->vb_lock);
+
+	if (videobuf_queue_is_busy(src_vq)) {
+		v4l2_err(v4l2_dev, "%s queue busy\n", __func__);
+		ret = -EBUSY;
+		goto s_fmt_out;
+	}
+
+	if (videobuf_queue_is_busy(dst_vq)) {
+		v4l2_err(v4l2_dev, "%s queue busy\n", __func__);
+		ret = -EBUSY;
+		goto s_fmt_out;
+	}
+
+	if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		frame = &ctx->s_frame;
+		ctx->flags |= FIMC_SRC_FMT;
+	} else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
+		frame = &(ctx)->d_frame;
+		ctx->flags |= FIMC_DST_FMT;
+	} else {
+		v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
+			 "Wrong buffer/video queue type (%d)\n", f->type);
+		return -EINVAL;
+	}
+
+	pix = &f->fmt.pix;
+	frame->fmt = find_format(f);
+	if (!frame->fmt) {
+		ret = -EINVAL;
+		goto s_fmt_out;
+	}
+
+	frame->f_width = pix->bytesperline*8/frame->fmt->depth;
+	frame->f_height = pix->sizeimage/pix->bytesperline;
+	frame->width = pix->width;
+	frame->height = pix->height;
+	frame->o_width = pix->width;
+	frame->o_height = pix->height;
+	frame->offs_h = 0;
+	frame->offs_v = 0;
+	frame->size = (pix->width * pix->height * frame->fmt->depth) >> 3;
+	ctx->flags |= FIMC_PARAMS;
+	src_vq->field = dst_vq->field = pix->field;
+
+	dbg("f_width= %d, f_height= %d", frame->f_width, frame->f_height);
+
+s_fmt_out:
+	mutex_unlock(&dst_vq->vb_lock);
+	mutex_unlock(&src_vq->vb_lock);
+	mutex_unlock(&ctx->fimc_dev->lock);
+	return ret;
+}
+
+static int fimc_m2m_reqbufs(struct file *file, void *priv,
+			  struct v4l2_requestbuffers *reqbufs)
+{
+	struct fimc_ctx *ctx = priv;
+	return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
+}
+
+static int fimc_m2m_querybuf(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct fimc_ctx *ctx = priv;
+	return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
+}
+
+static int fimc_m2m_qbuf(struct file *file, void *priv,
+			  struct v4l2_buffer *buf)
+{
+	struct fimc_ctx *ctx = priv;
+
+	if (!fimc_fifo_active(ctx->fimc_dev))
+		return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
+	else
+		return -EBUSY;
+}
+
+static int fimc_m2m_dqbuf(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct fimc_ctx *ctx = priv;
+	return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
+}
+
+static int fimc_m2m_streamon(struct file *file, void *priv,
+			   enum v4l2_buf_type type)
+{
+	struct fimc_ctx *ctx = priv;
+
+	if (!fimc_fifo_active(ctx->fimc_dev))
+		return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
+	else
+		return -EBUSY;
+}
+
+static int fimc_m2m_streamoff(struct file *file, void *priv,
+			    enum v4l2_buf_type type)
+{
+	struct fimc_ctx *ctx = priv;
+	return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
+}
+
+int fimc_m2m_queryctrl(struct file *file, void *priv,
+			    struct v4l2_queryctrl *qc)
+{
+	struct v4l2_queryctrl *c;
+	c = get_ctrl(qc->id);
+	if (!c)
+		return -EINVAL;
+	*qc = *c;
+	return 0;
+}
+
+int fimc_m2m_g_ctrl(struct file *file, void *priv,
+			 struct v4l2_control *ctrl)
+{
+	struct fimc_ctx *ctx = priv;
+
+	switch (ctrl->id) {
+	case V4L2_CID_HFLIP:
+		ctrl->value = (FLIP_X_AXIS & ctx->flip) ? 1 : 0;
+		break;
+	case V4L2_CID_VFLIP:
+		ctrl->value = (FLIP_Y_AXIS & ctx->flip) ? 1 : 0;
+		break;
+	case V4L2_CID_ROTATE:
+		ctrl->value = ctx->rotation;
+		break;
+	default:
+		v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev, "Invalid control\n");
+		return -EINVAL;
+	}
+	dbg("ctrl->value= %d", ctrl->value);
+	return 0;
+}
+
+static int check_ctrl_val(struct fimc_ctx *ctx,
+			  struct v4l2_control *ctrl)
+{
+	struct v4l2_queryctrl *c;
+	c = get_ctrl(ctrl->id);
+	if (!c)
+		return -EINVAL;
+
+	if (ctrl->value < c->minimum || ctrl->value > c->maximum
+		|| (c->step != 0 && ctrl->value % c->step != 0)) {
+		v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev,
+		"Invalid control value\n");
+		return -ERANGE;
+	}
+
+	return 0;
+}
+
+int fimc_m2m_s_ctrl(struct file *file, void *priv,
+			 struct v4l2_control *ctrl)
+{
+	struct fimc_ctx *ctx = priv;
+	struct samsung_plat_fimc *pldata = ctx->fimc_dev->pldata;
+	int ret = 0;
+
+	ret = check_ctrl_val(ctx, ctrl);
+	if (ret != 0)
+		return ret;
+
+	switch (ctrl->id) {
+	case V4L2_CID_HFLIP:
+		if (ctrl->value)
+			ctx->flip |= FLIP_X_AXIS;
+		else
+			ctx->flip &= ~FLIP_X_AXIS;
+		break;
+
+	case V4L2_CID_VFLIP:
+		if (ctrl->value)
+			ctx->flip |= FLIP_Y_AXIS;
+		else
+			ctx->flip &= ~FLIP_Y_AXIS;
+		break;
+
+	case V4L2_CID_ROTATE:
+		if (ctrl->value == 90 || ctrl->value == 270) {
+			/* use input rotator in LCDFIFO output mode only */
+			if (ctx->out_path == FIMC_LCDFIFO) {
+				if (!(pldata->capability & S5P_FIMC_IN_ROT))
+					return -EINVAL;
+			} else if (ctx->in_path == FIMC_DMA &&
+				   !(pldata->capability & S5P_FIMC_OUT_ROT)) {
+				return -EINVAL;
+			}
+		}
+		ctx->rotation = ctrl->value;
+		if (ctrl->value == 180)
+			ctx->flip = FLIP_XY_AXIS;
+		break;
+
+	default:
+		v4l2_err(&ctx->fimc_dev->m2m.v4l2_dev, "Invalid control\n");
+		return -EINVAL;
+	}
+
+	ctx->flags |= FIMC_PARAMS;
+	return 0;
+}
+
+
+static int fimc_m2m_cropcap(struct file *file, void *fh,
+			     struct v4l2_cropcap *cr)
+{
+	struct fimc_frame *frame;
+	struct fimc_ctx *ctx = fh;
+	if (!ctx) {
+		WARN_ON(1);
+		return -ENOENT;
+	}
+
+	ctx_m2m_get_frame(frame, ctx, cr->type);
+
+	cr->bounds.left = 0;
+	cr->bounds.top = 0;
+	cr->bounds.width = frame->f_width;
+	cr->bounds.height = frame->f_height;
+	cr->defrect.left = frame->offs_h;
+	cr->defrect.top = frame->offs_v;
+	cr->defrect.width = frame->o_width;
+	cr->defrect.height = frame->o_height;
+	return 0;
+}
+
+static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
+{
+	struct fimc_frame *frame;
+	struct fimc_ctx *ctx = file->private_data;
+
+	BUG_ON(!ctx);
+
+	ctx_m2m_get_frame(frame, ctx, cr->type);
+
+	cr->c.left = frame->offs_h;
+	cr->c.top = frame->offs_v;
+	cr->c.width = frame->width;
+	cr->c.height = frame->height;
+
+	return 0;
+}
+
+static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
+{
+	struct fimc_frame *f;
+	struct fimc_ctx *ctx = file->private_data;
+	struct fimc_dev *dev = ctx->fimc_dev;
+	int ret = 0;
+
+	if (cr->c.top < 0 || cr->c.left < 0) {
+		v4l2_err(&dev->m2m.v4l2_dev,
+			"doesn't support negative values for top & left\n");
+		return -EINVAL;
+	}
+
+	if (cr->c.width  <= 0 || cr->c.height <= 0) {
+		v4l2_err(&dev->m2m.v4l2_dev,
+			"crop width and height must be greater than 0\n");
+		return -EINVAL;
+	}
+
+	ctx_m2m_get_frame(f, ctx, cr->type);
+
+	dbg("%d %d %d %d f_w= %d, f_h= %d",
+		cr->c.left, cr->c.top, cr->c.width, cr->c.height,
+		f->f_width, f->f_height);
+
+	/* adjust to DMA_MIN_SIZE pixels boundary */
+	cr->c.width = ALIGN(cr->c.width, DMA_MIN_SIZE);
+	cr->c.height = ALIGN(cr->c.height, DMA_MIN_SIZE);
+	cr->c.left = ALIGN(cr->c.left, DMA_MIN_SIZE);
+	cr->c.top = ALIGN(cr->c.top, DMA_MIN_SIZE);
+
+	if ((cr->c.left + cr->c.width > f->o_width)
+		|| (cr->c.top + cr->c.height > f->o_height)) {
+		v4l2_err(&dev->m2m.v4l2_dev, "Error in S_CROP params\n");
+		dbg("%d %d %d %d. %d %d",
+			cr->c.left, cr->c.top, cr->c.width, cr->c.height,
+			f->o_width, f->o_height);
+		return -EINVAL;
+	}
+
+	if ((ctx->flags & FIMC_SRC_FMT) && (ctx->flags & FIMC_DST_FMT)) {
+		/* check for the pixel scaling ratio when cropping input img */
+		if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
+			ret = fimc_check_scaler_ratio(&cr->c, &ctx->d_frame);
+		else if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
+			ret = fimc_check_scaler_ratio(&cr->c, &ctx->s_frame);
+
+		if (ret) {
+			v4l2_err(&dev->m2m.v4l2_dev,  "Out of scaler range");
+			return -EINVAL;
+		}
+	}
+
+	f->offs_h = cr->c.left;
+	f->offs_v = cr->c.top;
+	f->width = cr->c.width;
+	f->height = cr->c.height;
+	ctx->flags |= FIMC_PARAMS;
+	return 0;
+}
+
+static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
+	.vidioc_querycap		= fimc_m2m_querycap,
+
+	.vidioc_enum_fmt_vid_cap	= fimc_m2m_enum_fmt,
+	.vidioc_enum_fmt_vid_out	= fimc_m2m_enum_fmt,
+
+	.vidioc_g_fmt_vid_cap		= fimc_m2m_g_fmt,
+	.vidioc_g_fmt_vid_out		= fimc_m2m_g_fmt,
+
+	.vidioc_try_fmt_vid_cap		= fimc_m2m_try_fmt,
+	.vidioc_try_fmt_vid_out		= fimc_m2m_try_fmt,
+
+	.vidioc_s_fmt_vid_cap		= fimc_m2m_s_fmt,
+	.vidioc_s_fmt_vid_out		= fimc_m2m_s_fmt,
+
+	.vidioc_reqbufs			= fimc_m2m_reqbufs,
+	.vidioc_querybuf		= fimc_m2m_querybuf,
+
+	.vidioc_qbuf			= fimc_m2m_qbuf,
+	.vidioc_dqbuf			= fimc_m2m_dqbuf,
+
+	.vidioc_streamon		= fimc_m2m_streamon,
+	.vidioc_streamoff		= fimc_m2m_streamoff,
+
+	.vidioc_queryctrl		= fimc_m2m_queryctrl,
+	.vidioc_g_ctrl			= fimc_m2m_g_ctrl,
+	.vidioc_s_ctrl			= fimc_m2m_s_ctrl,
+
+	.vidioc_g_crop			= fimc_m2m_g_crop,
+	.vidioc_s_crop			= fimc_m2m_s_crop,
+	.vidioc_cropcap			= fimc_m2m_cropcap
+
+};
+
+static void queue_init(void *priv, struct videobuf_queue *vq,
+		       enum v4l2_buf_type type)
+{
+	struct fimc_ctx *ctx = priv;
+	struct fimc_dev *dev = ctx->fimc_dev;
+
+	videobuf_queue_dma_contig_init(vq, &fimc_qops,
+		dev->m2m.v4l2_dev.dev,
+		&dev->irqlock, type, V4L2_FIELD_NONE,
+		sizeof(struct fimc_vid_buffer), priv);
+}
+
+static int fimc_m2m_open(struct file *file)
+{
+	struct fimc_dev *dev = video_drvdata(file);
+	struct fimc_ctx *ctx = NULL;
+	int err = 0;
+
+	mutex_lock(&dev->lock);
+	dev->m2m.refcnt++;
+	set_bit(ST_OUTDMA_RUN, &dev->state);
+	mutex_unlock(&dev->lock);
+
+
+	ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+
+	file->private_data = ctx;
+	ctx->fimc_dev = dev;
+	/* default format */
+	ctx->s_frame.fmt = &fimc_formats[0];
+	ctx->d_frame.fmt = &fimc_formats[0];
+	/* per user process device context initialization */
+	ctx->flags = 0;
+	ctx->effect.type = S5P_FIMC_EFFECT_ORIGINAL;
+	ctx->in_path = FIMC_DMA;
+	ctx->out_path = FIMC_DMA;
+
+	ctx->m2m_ctx = v4l2_m2m_ctx_init(ctx, dev->m2m.m2m_dev, queue_init);
+
+	if (IS_ERR(ctx->m2m_ctx)) {
+		err = PTR_ERR(ctx->m2m_ctx);
+		kfree(ctx);
+		return err;
+	}
+
+	return 0;
+}
+
+static int fimc_m2m_release(struct file *file)
+{
+	struct fimc_ctx *ctx = file->private_data;
+	struct fimc_dev *dev = ctx->fimc_dev;
+
+	v4l2_m2m_ctx_release(ctx->m2m_ctx);
+	kfree(ctx);
+	mutex_lock(&dev->lock);
+	if (--dev->m2m.refcnt <= 0)
+		clear_bit(ST_OUTDMA_RUN, &dev->state);
+	mutex_unlock(&dev->lock);
+	return 0;
+}
+
+static unsigned int fimc_m2m_poll(struct file *file,
+				     struct poll_table_struct *wait)
+{
+	struct fimc_ctx *ctx = file->private_data;
+	return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
+}
+
+
+static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct fimc_ctx *ctx = file->private_data;
+	return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
+}
+
+static const struct v4l2_file_operations fimc_m2m_fops = {
+	.owner		= THIS_MODULE,
+	.open		= fimc_m2m_open,
+	.release	= fimc_m2m_release,
+	.poll		= fimc_m2m_poll,
+	.ioctl		= video_ioctl2,
+	.mmap		= fimc_m2m_mmap,
+};
+
+static struct v4l2_m2m_ops m2m_ops = {
+	.device_run	= fimc_dma_run,
+	.job_abort	= fimc_job_abort,
+};
+
+
+static int fimc_register_m2m_device(struct fimc_dev *dev)
+{
+	struct video_device *vfd;
+	struct platform_device *pdev;
+	struct v4l2_device *v4l2_dev;
+	int ret = 0;
+
+	if (!dev)
+		return -ENODEV;
+
+	pdev = dev->pdev;
+	v4l2_dev = &dev->m2m.v4l2_dev;
+
+	/* set name if it is empty */
+	if (!v4l2_dev->name[0])
+		snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
+			 "%s.%d.v4l2_m2m", MODULE_NAME, dev->id);
+
+	ret = v4l2_device_register(&pdev->dev, v4l2_dev);
+	if (ret)
+		return ret;;
+
+	vfd = video_device_alloc();
+	if (!vfd) {
+		v4l2_err(v4l2_dev, "Failed to allocate video device\n");
+		goto err_m2m_r1;
+	}
+
+	vfd->fops	= &fimc_m2m_fops;
+	vfd->ioctl_ops	= &fimc_m2m_ioctl_ops;
+	vfd->minor	= -1;
+	vfd->release	= video_device_release;
+
+	snprintf(vfd->name, sizeof(vfd->name), "%s.%d:v4l2_m2m",
+		 MODULE_NAME, dev->id);
+
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
+	if (ret) {
+		v4l2_err(v4l2_dev,
+			 "%s(): failed to register video device\n", __func__);
+		goto err_m2m_r2;
+	}
+	video_set_drvdata(vfd, dev);
+	dev->m2m.vfd = vfd;
+	v4l2_info(v4l2_dev, "%s(): registered as /dev/video%d\n",
+		  __func__, vfd->num);
+
+	platform_set_drvdata(pdev, dev);
+
+	dev->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
+
+	if (IS_ERR(dev->m2m.m2m_dev)) {
+		v4l2_err(v4l2_dev,
+			 "%s(): failed to initialize v4l2-m2m device\n",
+			 __func__);
+		ret = PTR_ERR(dev->m2m.m2m_dev);
+		goto err_m2m_r3;
+	}
+	return 0;
+
+err_m2m_r1:
+	v4l2_device_unregister(&dev->m2m.v4l2_dev);
+err_m2m_r2:
+	video_device_release(dev->m2m.vfd);
+err_m2m_r3:
+	video_unregister_device(dev->m2m.vfd);
+
+	return ret;
+}
+
+static void fimc_unregister_m2m_device(struct fimc_dev *dev)
+{
+	if (dev) {
+		v4l2_m2m_release(dev->m2m.m2m_dev);
+		video_unregister_device(dev->m2m.vfd);
+		video_device_release(dev->m2m.vfd);
+		v4l2_device_unregister(&dev->m2m.v4l2_dev);
+	}
+}
+
+static int fimc_probe(struct platform_device *pdev)
+{
+	struct fimc_dev *dev;
+	struct resource *res;
+	int ret = 0;
+
+	dev_dbg(&pdev->dev, "%s():\n", __func__);
+
+	if (!pdev->dev.platform_data) {
+		dev_err(&pdev->dev, "platform_data is not set\n");
+		return -ENOENT;
+	}
+
+	dev = kzalloc(sizeof(struct fimc_dev), GFP_KERNEL);
+	if (!dev)
+		return -ENOMEM;
+
+	dev->id = pdev->id;
+	dev->pdev = pdev;
+	dev->pldata = pdev->dev.platform_data;
+	dev->state = ST_IDLE;
+
+	spin_lock_init(&dev->irqlock);
+	init_waitqueue_head(&dev->irq_queue);
+	spin_lock_init(&dev->slock);
+
+	mutex_init(&dev->lock);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to find the registers\n");
+		ret = -ENOENT;
+		goto err_info;
+	}
+
+	dev->regs_res = request_mem_region(res->start, resource_size(res),
+			dev_name(&pdev->dev));
+	if (!dev->regs_res) {
+		dev_err(&pdev->dev, "failed to obtain register region\n");
+		ret = -ENOENT;
+		goto err_info;
+	}
+
+	dev->regs = ioremap(res->start, resource_size(res));
+	if (!dev->regs) {
+		dev_err(&pdev->dev, "failed to map registers\n");
+		ret = -ENXIO;
+		goto err_req_region;
+	}
+
+	/* FIMC clock */
+	dev->clock = clk_get(&pdev->dev, "sclk_fimc");
+	if (IS_ERR(dev->clock)) {
+		ret = -ENXIO;
+		dev_err(&pdev->dev, "failed to get fimc clock source\n");
+		goto err_regs_unmap;
+	}
+	clk_enable(dev->clock);
+
+	/* IRQ */
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to get IRQ resource\n");
+		ret = -ENXIO;
+		goto err_clk;
+	}
+	dev->irq = res->start;
+
+	fimc_hw_reset(dev);
+
+	ret = request_irq(dev->irq, fimc_isr, 0, pdev->name, dev);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
+		goto err_clk;
+	}
+
+	dev->work_queue = create_workqueue(dev_name(&dev->pdev->dev));
+	if (!dev->work_queue)
+		goto err_irq;
+
+	ret = fimc_register_m2m_device(dev);
+	if (ret)
+		goto err_wq;
+
+	ret = fimc_register_fifo_device(dev);
+	if (ret)
+		goto err_m2m;
+
+	fimc_hw_en_lastirq(dev, 1);
+
+	dev_dbg(&pdev->dev, "%s(): fimc-%d registered successfully\n",
+		__func__, dev->id);
+
+	return 0;
+
+err_m2m:
+	fimc_unregister_m2m_device(dev);
+err_wq:
+	destroy_workqueue(dev->work_queue);
+err_irq:
+	free_irq(dev->irq, dev);
+err_clk:
+	clk_disable(dev->clock);
+	clk_put(dev->clock);
+err_regs_unmap:
+	iounmap(dev->regs);
+err_req_region:
+	release_resource(dev->regs_res);
+	kfree(dev->regs_res);
+err_info:
+	dev_err(&pdev->dev, "failed to install\n");
+	return ret;
+}
+
+static int __devexit fimc_remove(struct platform_device *pdev)
+{
+	struct fimc_dev *dev =
+		(struct fimc_dev *)platform_get_drvdata(pdev);
+
+	v4l2_info(&dev->m2m.v4l2_dev, "Removing %s\n", pdev->name);
+
+	free_irq(dev->irq, dev);
+
+	fimc_hw_reset(dev);
+
+	fimc_unregister_m2m_device(dev);
+	fimc_unregister_fifo_device(dev);
+
+	iounmap(dev->regs);
+	release_resource(dev->regs_res);
+	kfree(dev->regs_res);
+	kfree(dev);
+	return 0;
+}
+
+static struct platform_driver fimc_driver = {
+	.probe = fimc_probe,
+	.remove = __devexit_p(fimc_remove),
+	.driver = {
+		.name = "s5p-fimc",
+		.owner = THIS_MODULE,
+	}
+};
+
+static char banner[] __initdata = KERN_INFO \
+	"S5PC Camera Interface V4L2 Driver, (c) 2010 Samsung Electronics\n";
+
+static int __init fimc_init(void)
+{
+	u32 ret;
+	printk(banner);
+
+	ret = platform_driver_register(&fimc_driver);
+	if (ret != 0) {
+		printk(KERN_ERR "FIMC platform driver register failed\n");
+		return -1;
+	}
+	return 0;
+}
+
+static void __exit fimc_exit(void)
+{
+	platform_driver_unregister(&fimc_driver);
+}
+
+module_init(fimc_init);
+module_exit(fimc_exit);
+
+MODULE_AUTHOR("Sylwester Nawrocki, s.nawrocki at samsung.com");
+MODULE_DESCRIPTION("S5PV210 FIMC (video postprocessor) driver");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/media/video/samsung-fimc/fimc-core.h b/drivers/media/video/samsung-fimc/fimc-core.h
new file mode 100644
index 0000000..ba5020a
--- /dev/null
+++ b/drivers/media/video/samsung-fimc/fimc-core.h
@@ -0,0 +1,509 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Sylwester Nawrocki, s.nawrocki at samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_CORE_H_
+#define FIMC_CORE_H_
+
+#include <linux/types.h>
+#include <plat/fimc.h>
+#include <plat/regs-fimc.h>
+#include <media/videobuf-core.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-mem2mem.h>
+#include <linux/videodev2.h>
+
+
+#define err(fmt, args...) \
+	printk(KERN_ERR "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
+
+#ifdef DEBUG
+#define dbg(fmt, args...) \
+	printk(KERN_DEBUG "%s:%d: " fmt "\n", __func__, __LINE__, ##args)
+#else
+#define dbg(fmt, args...)
+#endif
+
+#define ctx_m2m_get_frame(frame, ctx, type) do { \
+	if (V4L2_BUF_TYPE_VIDEO_OUTPUT == (type)) { \
+		frame = &(ctx)->s_frame; \
+	} else if (V4L2_BUF_TYPE_VIDEO_CAPTURE == (type)) { \
+		frame = &(ctx)->d_frame; \
+	} else { \
+		v4l2_err(&(ctx)->fimc_dev->m2m.v4l2_dev,\
+			"Wrong buffer/video queue type (%d)\n", type); \
+		return -EINVAL; \
+	} \
+} while (0)
+
+#define ctx_lcl_get_frame(frame, ctx, type) do { \
+	if (V4L2_BUF_TYPE_VIDEO_OUTPUT == (type)) { \
+		frame = &(ctx)->s_frame; \
+	} else if (V4L2_BUF_TYPE_VIDEO_OVERLAY == (type)) { \
+		frame = &(ctx)->d_frame; \
+	} else { \
+		v4l2_err(&(ctx)->fimc_dev->outp.v4l2_dev,\
+			"Wrong buffer/video queue type (%d)\n", type); \
+		return -EINVAL; \
+	} \
+} while (0)
+
+/* Time to wait for an interrupt whilst shutting down the lcdfifo mode. */
+#define FIMC_FIFO_SHDWN_TIMEOUT	((100*HZ)/1000)
+
+#define MODULE_NAME		"s5p-fimc"
+#define MAX_FIMC_DEVICES	3
+#define S5P_FIMC_MAX_FRAMES	4
+#define DMA_MIN_SIZE		16
+#define SCALER_MAX_HRATIO	64
+#define SCALER_MAX_VRATIO	64
+
+#define	FIMC_CHANGED_NONE	0
+#define	FIMC_PARAMS		(1 << 0)
+#define	FIMC_SRC_ADDR		(1 << 1)
+#define	FIMC_DST_ADDR		(1 << 2)
+#define	FIMC_SRC_FMT		(1 << 3)
+#define	FIMC_DST_FMT		(1 << 4)
+
+
+enum fimc_dev_flags {
+	ST_IDLE,
+	ST_OUTDMA_RUN,
+	ST_M2M_PEND,
+
+	ST_LCDFIFO_PEND,
+	ST_LCDFIFO_RUN
+};
+
+#define fimc_m2m_active(dev) test_bit(ST_OUTDMA_RUN, &(dev)->state)
+#define fimc_m2m_pending(dev) test_bit(ST_M2M_PEND, &(dev)->state)
+
+#define fimc_fifo_active(dev) test_bit(ST_LCDFIFO_RUN, &(dev)->state)
+#define fimc_fifo_pending(dev) test_bit(ST_LCDFIFO_PEND, &(dev)->state)
+
+enum fimc_datapath {
+	FIMC_ITU_CAM_A,
+	FIMC_ITU_CAM_B,
+	FIMC_MIPI_CAM,
+	FIMC_DMA,
+	FIMC_LCDFIFO,
+	FIMC_WRITEBACK
+};
+
+enum fimc_color_fmt {
+	S5P_FIMC_RGB565,
+	S5P_FIMC_RGB666,
+	S5P_FIMC_RGB888,
+	S5P_FIMC_YCBCR420,
+	S5P_FIMC_YCBCR422,
+	S5P_FIMC_YCBYCR422,
+	S5P_FIMC_YCRYCB422,
+	S5P_FIMC_CBYCRY422,
+	S5P_FIMC_CRYCBY422,
+	S5P_FIMC_RGB30_LOCAL,
+	S5P_FIMC_YCBCR444_LOCAL,
+	S5P_FIMC_MAX_COLOR = S5P_FIMC_YCBCR444_LOCAL,
+	S5P_FIMC_COLOR_MASK = 0x0F,
+};
+
+/* Y/Cb/Cr components order at DMA output for 1 plane YCbCr 4:2:2 formats */
+#define	S5P_FIMC_OUT_CRYCBY	S5P_CIOCTRL_ORDER422_CRYCBY
+#define	S5P_FIMC_OUT_CBYCRY	S5P_CIOCTRL_ORDER422_YCRYCB
+#define	S5P_FIMC_OUT_YCRYCB	S5P_CIOCTRL_ORDER422_CBYCRY
+#define	S5P_FIMC_OUT_YCBYCR	S5P_CIOCTRL_ORDER422_YCBYCR
+
+/* Input Y/Cb/Cr components order for 1 plane YCbCr 4:2:2 color formats */
+#define	S5P_FIMC_IN_CRYCBY	S5P_MSCTRL_ORDER422_CRYCBY
+#define	S5P_FIMC_IN_CBYCRY	S5P_MSCTRL_ORDER422_YCRYCB
+#define	S5P_FIMC_IN_YCRYCB	S5P_MSCTRL_ORDER422_CBYCRY
+#define	S5P_FIMC_IN_YCBYCR	S5P_MSCTRL_ORDER422_YCBYCR
+
+/* Cb/Cr chrominance components order for 2 plane Y/CbCr 4:2:2 formats */
+#define	S5P_FIMC_LSB_CRCB	S5P_CIOCTRL_ORDER422_2P_LSB_CRCB
+
+/* The embedded image effect selection */
+#define	S5P_FIMC_EFFECT_ORIGINAL	S5P_CIIMGEFF_FIN_BYPASS
+#define	S5P_FIMC_EFFECT_ARBITRARY	S5P_CIIMGEFF_FIN_ARBITRARY
+#define	S5P_FIMC_EFFECT_NEGATIVE	S5P_CIIMGEFF_FIN_NEGATIVE
+#define	S5P_FIMC_EFFECT_ARTFREEZE	S5P_CIIMGEFF_FIN_ARTFREEZE
+#define	S5P_FIMC_EFFECT_EMBOSSING	S5P_CIIMGEFF_FIN_EMBOSSING
+#define	S5P_FIMC_EFFECT_SIKHOUETTE	S5P_CIIMGEFF_FIN_SILHOUETTE
+
+
+/* Definitions for flags field in struct fimc_ctx */
+#define	IN_DMA_ACCESS_LINEAR		0	/* default */
+#define	IN_DMA_ACCESS_TILED		(1 << 0)
+#define	OUT_DMA_ACCESS_LINEAR		(0 << 1)
+#define	OUT_DMA_ACCESS_TILED		(1 << 1)
+#define	SCAN_MODE_PROGRESSIVE		(0 << 2)
+#define	SCAN_MODE_INTERLACED		(1 << 2)
+/* YCbCr data dynamic range selection for the RGB <-> YCBCR color space
+ * conversion. Y/Cb/Cr (0 ~ 255) : Wide default */
+#define	S5P_FIMC_COLOR_RANGE_WIDE	(0 << 3)
+/* Y (16 ~ 235), Cb/Cr (16 ~ 240) : Narrow */
+#define	S5P_FIMC_COLOR_RANGE_NARROW	(1 << 3)
+
+#define	FLIP_NONE	0
+#define	FLIP_X_AXIS	0x01
+#define	FLIP_Y_AXIS	0x02
+#define	FLIP_XY_AXIS	(FLIP_X_AXIS | FLIP_Y_AXIS)
+
+
+struct fimc_fmt {
+	char	*name;
+	u32	fourcc;
+	u32	color;
+	u32	depth;
+	/* number of plane video buffers used */
+	u16	buff_cnt;
+	/* number of planes for contiguous formats */
+	u16	planes_cnt;
+};
+
+/**
+ * struct fimc_dma_offset
+ * @y_h:	y value horizontal offset
+ * @y_v:	y value vertical offset
+ * @cb_h:	cb value horizontal offset
+ * @cb_v:	cb value vertical offset
+ * @cr_h:	cr value horizontal offset
+ * @cr_v:	cr value vertical offset
+ */
+struct fimc_dma_offset {
+	int	y_h;
+	int	y_v;
+	int	cb_h;
+	int	cb_v;
+	int	cr_h;
+	int	cr_v;
+};
+
+/**
+ * struct s5pc_fimc_fb_osd
+ * @x: OSD rectangle top left x coordinate
+ * @y: OSD rectangle top left y coordinate
+ * @width: OSD rectangle width
+ * @height: OSD rectangle height
+ * @saved: the flag indicating whether this data structure is initialized
+ */
+struct fimc_fb_osd {
+	u32	x;
+	u32	y;
+	u32	width;
+	u32	height;
+	int	saved;
+};
+
+/**
+ * struct s5p_fimc_effect
+ * @type:	effect type
+ * @pat_cb:	cr value when type is "arbitrary"
+ * @pat_cr:	cr value when type is "arbitrary"
+ */
+struct fimc_effect {
+	u32	type;
+	u8	pat_cb;
+	u8	pat_cr;
+};
+
+/**
+ * struct fimc_scaler
+ * @enabled:		flag indicating whether the scaler is used or not
+ * @hfactor:		horizontal shift factor
+ * @vfactor:		vertical shift factor
+ * @pre_hratio:		prescaler horizontal ratio
+ * @pre_vratio:		prescaler vertical ratio
+ * @pre_dst_width:	prescaler destination width
+ * @pre_dst_height:	pre-scaler destination height
+ * @scaleup_h:		flag indicating scaling up horizontally
+ * @scaleup_v:		flag indicating scaling up vertically
+ * @main_hratio:	main scaler horizontal ratio
+ * @main_vratio:	main scaler vertical ratio
+ * @real_width:		src_width - offset
+ * @real_height:	src_height - offset
+ * @copy_mode:		flag indicating one to one mode, i.e. no scaling
+ *			and color format conversion
+ */
+struct fimc_scaler {
+	u32	enabled;
+	u32	hfactor;
+	u32	vfactor;
+	u32	pre_hratio;
+	u32	pre_vratio;
+	u32	pre_dst_width;
+	u32	pre_dst_height;
+	u32	scaleup_h;
+	u32	scaleup_v;
+	u32	main_hratio;
+	u32	main_vratio;
+	u32	real_width;
+	u32	real_height;
+	u32	copy_mode;
+};
+
+/**
+ * struct fimc_addr
+ * @y:	 Y (luminance) plane physical address
+ * @cb:	 Cb plane physical address
+ * @cr:	 Cr plane physical address
+ */
+struct fimc_addr {
+	u32	y;
+	u32	cb;
+	u32	cr;
+};
+
+/**
+ * struct fimc_vid_buffer
+ * @vb:
+ * @paddr:
+ * @index:
+ */
+struct fimc_vid_buffer {
+	struct videobuf_buffer	vb;
+	struct fimc_addr	paddr;
+	int			index;
+};
+
+/**
+ * struct fimc_frame - input/output frame format properties
+ * @f_width:	image full width (virtual screen size)
+ * @f_height:	image full height (virtual screen size)
+ * @o_width:	original image width as set by S_FMT
+ * @o_height:	original image height as set by S_FMT
+ * @offs_h:	image horizontal pixel offset
+ * @offs_v:	image vertical pixel offset
+ * @width:	image pixel width
+ * @height:	image pixel weight
+ * @paddr:	image frame buffer physical addresses
+ * @buf_cnt:	number of buffers depending on a color format
+ * @size:	image size in bytes
+ * @color:	color format
+ * @dma_offset:	DMA offset in bytes
+ */
+struct fimc_frame {
+	u32	f_width;
+	u32	f_height;
+	u32	o_width;
+	u32	o_height;
+	u32	offs_h;
+	u32	offs_v;
+	u32	width;
+	u32	height;
+	u32	size;
+	struct fimc_addr	paddr;
+	struct fimc_dma_offset	dma_offset;
+	struct fimc_fmt		*fmt;
+};
+
+
+/* v4l2 memory to memory device abstraction */
+struct fimc_v4l_m2m_dev {
+	struct video_device	*vfd;
+	struct v4l2_device	v4l2_dev;
+	struct v4l2_m2m_dev	*m2m_dev;
+	struct fimc_ctx		*ctx;
+	int			refcnt;
+};
+
+/* v4l2 output device */
+struct v4l2_fimc_outp_dev {
+	struct video_device		*vfd;
+	struct v4l2_device		v4l2_dev;
+	struct v4l2_subdev		*sd[FIMC_MAX_FIFO_TARGETS];
+	struct work_struct		work;
+	/* fimc_video_buffer queue head */
+	struct list_head		buf_q;
+	/* pointer to currently processed video buffer */
+	struct fimc_vid_buffer		*curr_buf;
+	/* video buffer queue for OUTPUT stream */
+	struct videobuf_queue		vbq;
+	struct v4l2_format		fmt;
+	struct fimc_ctx			*ctx;
+	int				refcnt;
+};
+
+
+struct fimc_ctx;
+
+/**
+ * struct fimc_subdev: abstraction for a FIMC entity
+ * @slock:
+ * @pdev:	pointer to the FIMC platform device
+ * @pldata:	pointer to the device platform data
+ * @id:		FIMC device index (0..2)
+ * @clock:
+ * @regs:
+ * @regs_res:
+ * @mem_res:
+ * @irq:	interrupt number of the FIMC subdevice
+ * @irqlock:	spinlock protecting videbuffer queue
+ * @lock:
+ * @irq_queue:
+ * @work_queue:
+ * @m2m:
+ * @outp:
+ * @state:
+ */
+struct fimc_dev {
+	spinlock_t			slock;
+	struct platform_device		*pdev;
+	struct samsung_plat_fimc	*pldata;
+	int				id;
+	struct clk			*clock;
+	void __iomem			*regs;
+	struct resource			*regs_res;
+	struct resource			*mem_res;
+	int				irq;
+	spinlock_t			irqlock;
+	struct mutex			lock;
+	wait_queue_head_t		irq_queue;
+	struct workqueue_struct		*work_queue;
+	struct fimc_v4l_m2m_dev		m2m;
+	struct v4l2_fimc_outp_dev	outp;
+	volatile unsigned long		state;
+};
+
+
+/**
+ * fimc_ctx - the device context data structure
+ * @lock:		mutex protecting the context data
+ * @s_frame:		source frame properties
+ * @d_frame:		destination frame properties
+ * @osd:		osd (output) window parameters
+ * @out_order_1p:	output 1-plane YCBCR order
+ * @out_order_2p:	output 2-plane YCBCR order
+ * @in_order_1p		input 1-plane YCBCR order
+ * @in_order_2p:	input 2-plane YCBCR order
+ * @in_path:		input mode
+ * @out_path:		output mode
+ * @scaler:		image scaler properties
+ * @effect:		image effect
+ * @rotation:		image clockwise rotation in degrees
+ * @flip:		image flip mode
+ * @updated:		flags variable to keep track of user configurable
+ *			parameters (ioctl)
+ * @fimc_dev:		fimc device related to the context
+ * @m2m_ctx:		memory-to-memory device context
+ */
+struct fimc_ctx {
+	spinlock_t		slock;
+	struct fimc_frame	s_frame;
+	struct fimc_frame	d_frame;
+	u32			out_order_1p;
+	u32			out_order_2p;
+	u32			in_order_1p;
+	u32			in_order_2p;
+	enum fimc_datapath	in_path;
+	enum fimc_datapath	out_path;
+	struct fimc_scaler	scaler;
+	struct fimc_effect	effect;
+	int			rotation;
+	u32			flip;
+	u32			flags;
+	struct fimc_dev		*fimc_dev;
+	struct v4l2_m2m_ctx	*m2m_ctx;
+};
+
+
+extern struct fimc_fmt fimc_formats[];
+extern struct videobuf_queue_ops fimc_qops;
+
+static inline int tiled_fmt(struct fimc_fmt *fmt)
+{
+	return 0;
+}
+
+static inline void fimc_hw_clear_irq(struct fimc_dev *dev)
+{
+	u32 cfg = readl(dev->regs + S5P_CIGCTRL);
+	cfg |= S5P_CIGCTRL_IRQ_CLR;
+	writel(cfg, dev->regs + S5P_CIGCTRL);
+}
+
+static inline void fimc_hw_start_scaler(struct fimc_dev *dev)
+{
+	u32 cfg = readl(dev->regs + S5P_CISCCTRL);
+	cfg |= S5P_CISCCTRL_SCALERSTART;
+	writel(cfg, dev->regs + S5P_CISCCTRL);
+}
+
+static inline void fimc_hw_stop_scaler(struct fimc_dev *dev)
+{
+	u32 cfg = readl(dev->regs + S5P_CISCCTRL);
+	cfg &= ~S5P_CISCCTRL_SCALERSTART;
+	writel(cfg, dev->regs + S5P_CISCCTRL);
+}
+
+static inline void fimc_hw_dis_capture(struct fimc_dev *dev)
+{
+	u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
+	cfg &= ~(S5P_CIIMGCPT_IMGCPTEN | S5P_CIIMGCPT_IMGCPTEN_SC);
+	writel(cfg, dev->regs + S5P_CIIMGCPT);
+}
+
+static inline void fimc_hw_start_in_dma(struct fimc_dev *dev)
+{
+	u32 cfg = readl(dev->regs + S5P_MSCTRL);
+	cfg |= S5P_MSCTRL_ENVID;
+	writel(cfg, dev->regs + S5P_MSCTRL);
+}
+
+static inline void fimc_hw_stop_in_dma(struct fimc_dev *dev)
+{
+	u32 cfg = readl(dev->regs + S5P_MSCTRL);
+	cfg &= ~S5P_MSCTRL_ENVID;
+	writel(cfg, dev->regs + S5P_MSCTRL);
+}
+
+
+/* -----------------------------------------------------*/
+/* fimc-core.c */
+int fimc_set_scaler_info(struct fimc_ctx *ctx);
+struct fimc_fmt *find_format(struct v4l2_format *f);
+int fimc_m2m_enum_fmt(struct file *file, void *priv,
+		      struct v4l2_fmtdesc *f);
+int fimc_m2m_queryctrl(struct file *file, void *priv,
+		       struct v4l2_queryctrl *qc);
+int fimc_m2m_g_ctrl(struct file *file, void *priv,
+		    struct v4l2_control *ctrl);
+int fimc_m2m_s_ctrl(struct file *file, void *priv,
+		    struct v4l2_control *ctrl);
+int fimc_check_scaler_ratio(struct v4l2_rect *r, struct fimc_frame *f);
+int fimc_prepare_addr(struct fimc_ctx *ctx,
+	struct fimc_vid_buffer *buf, enum v4l2_buf_type type);
+int fimc_prepare_config(struct fimc_ctx *ctx, u32 flags);
+
+/* -----------------------------------------------------*/
+/* fimc-fifo.c						*/
+int fimc_register_fifo_device(struct fimc_dev *dev);
+void fimc_unregister_fifo_device(struct fimc_dev *dev);
+
+/* -----------------------------------------------------*/
+/* fimc-reg.c						*/
+int fimc_hw_reset_fifo_ov(struct fimc_dev *dev);
+void fimc_hw_reset(struct fimc_dev *dev);
+void fimc_hw_set_rotation(struct fimc_ctx *ctx);
+void fimc_hw_set_target_format(struct fimc_ctx *ctx);
+void fimc_hw_set_out_dma(struct fimc_ctx *ctx);
+void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable);
+void fimc_hw_en_irq(struct fimc_dev *dev, int enable);
+void fimc_hw_en_autoload(struct fimc_dev *dev, int enable);
+void fimc_hw_set_prescaler(struct fimc_ctx *ctx);
+void fimc_hw_set_scaler(struct fimc_ctx *ctx);
+void fimc_hw_en_capture(struct fimc_ctx *ctx);
+void fimc_hw_set_effect(struct fimc_ctx *ctx);
+void fimc_hw_set_in_dma(struct fimc_ctx *ctx);
+void fimc_hw_set_input_path(struct fimc_ctx *ctx);
+void fimc_hw_set_output_path(struct fimc_ctx *ctx);
+void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr);
+void fimc_hw_set_output_addr(struct fimc_dev *dev, struct fimc_addr *paddr);
+void fimc_hw_shadow_dis(struct fimc_dev *ctx, int off);
+
+#endif /* FIMC_CORE_H_ */
diff --git a/drivers/media/video/samsung-fimc/fimc-fifo.c b/drivers/media/video/samsung-fimc/fimc-fifo.c
new file mode 100644
index 0000000..9c11d13
--- /dev/null
+++ b/drivers/media/video/samsung-fimc/fimc-fifo.c
@@ -0,0 +1,822 @@
+/*
+ * S5P camera interface (video postprocessor) driver
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Sylwester Nawrocki, s.nawrocki at samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published
+ * by the Free Software Foundiation. either version 2 of the License,
+ * or (at your option) any later version
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/bug.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+
+#include <linux/fb.h>
+#include <mach/regs-fb.h>
+#include <plat/fb.h>
+#include <plat/fimc.h>
+#include <plat/fifo.h>
+
+#include <linux/videodev2.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/videobuf-core.h>
+#include <media/videobuf-dma-contig.h>
+
+#include "fimc-core.h"
+
+
+static int fimc_stop_lcdfifo(struct fimc_dev *dev)
+{
+	unsigned long flags;
+	struct v4l2_fimc_outp_dev *outp;
+
+	outp = &dev->outp;
+
+	if (fimc_fifo_active(dev) || fimc_fifo_pending(dev)) {
+
+		flush_workqueue(dev->work_queue);
+
+		/* disable fifo at frambuffer and fimc side */
+		v4l2_subdev_call(dev->outp.sd[FIMC_LCD_FIFO_TARGET],
+				 video, s_stream, 0);
+	}
+
+	spin_lock_irqsave(&dev->slock, flags);
+
+	/* Processing of the last buffer in the videobuf queue is never finished
+	   within the interrupt routine, so it needs to be done here.*/
+	if (outp->curr_buf) {
+		spin_lock(&dev->irqlock);
+		outp->curr_buf->vb.state = VIDEOBUF_DONE;
+		spin_unlock(&dev->irqlock);
+
+		wake_up(&outp->curr_buf->vb.done);
+		outp->curr_buf = NULL;
+	}
+	clear_bit(ST_LCDFIFO_RUN, &dev->state);
+
+	spin_unlock_irqrestore(&dev->slock, flags);
+	return 0;
+}
+
+void fimc_v4l2_dev_notify(struct v4l2_subdev *sd,
+			  unsigned int notification, void *arg)
+{
+	struct fimc_dev *dev = v4l2_get_subdevdata(sd);
+
+	BUG_ON(!dev);
+
+	switch (notification) {
+	case 0:
+		spin_lock(&dev->slock);
+		fimc_hw_en_autoload(dev, false);
+		fimc_hw_dis_capture(dev);
+		fimc_hw_stop_in_dma(dev);
+		fimc_hw_stop_scaler(dev);
+		clear_bit(ST_LCDFIFO_RUN, &dev->state);
+		spin_unlock(&dev->slock);
+		break;
+	default:
+		break;
+	}
+}
+
+static void lcdfifo_try_run(void *priv)
+{
+	struct fimc_ctx *ctx = priv;
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct fimc_frame *frame;
+	unsigned long flags;
+
+	BUG_ON(dev->outp.sd[FIMC_LCD_FIFO_TARGET] == NULL);
+
+	frame = &ctx->s_frame;
+	dbg("SRC: width= %d, height= %d, f_width= %d, f_height= %d " \
+		"offs_h= %d, offs_v= %d",
+		frame->width, frame->height,
+		frame->f_width, frame->f_height,
+		frame->offs_h, frame->offs_v);
+
+	frame = &ctx->d_frame;
+	dbg("DST: width= %d, height= %d, f_width= %d, f_height= %d " \
+		"offs_h= %d, offs_v= %d",
+		frame->width, frame->height,
+		frame->f_width, frame->f_height,
+		frame->offs_h, frame->offs_v);
+
+	spin_lock_irqsave(&dev->slock, flags);
+	fimc_hw_set_input_addr(dev, &ctx->s_frame.paddr);
+	spin_unlock_irqrestore(&dev->slock, flags);
+
+	if (ctx->flags & FIMC_PARAMS) {
+		fimc_hw_set_input_path(ctx);
+		fimc_hw_set_in_dma(ctx);
+
+		if (fimc_set_scaler_info(ctx)) {
+			err("scaler configuration error");
+			return;
+		}
+
+		spin_lock_irqsave(&dev->slock, flags);
+		fimc_hw_set_prescaler(ctx);
+		fimc_hw_set_scaler(ctx);
+		fimc_hw_set_target_format(ctx);
+		fimc_hw_set_rotation(ctx);
+		fimc_hw_set_effect(ctx);
+		spin_unlock_irqrestore(&dev->slock, flags);
+	}
+
+	v4l2_subdev_call(dev->outp.sd[FIMC_LCD_FIFO_TARGET], video,
+			 s_stream, 1);
+
+	spin_lock_irqsave(&dev->slock, flags);
+
+	fimc_hw_set_output_path(ctx);
+	if (ctx->scaler.enabled)
+		fimc_hw_start_scaler(dev);
+
+	fimc_hw_en_capture(ctx);
+	fimc_hw_start_in_dma(dev);
+
+	ctx->flags = 0;
+
+
+	spin_unlock_irqrestore(&dev->slock, flags);
+}
+
+static void fimc_worker(struct work_struct *work)
+{
+	int ret;
+	unsigned long flags;
+	struct v4l2_fimc_outp_dev *outp =
+		container_of(work, struct v4l2_fimc_outp_dev, work);
+	struct fimc_ctx *ctx = outp->ctx;
+	struct fimc_frame *f = &ctx->d_frame;
+	struct fimc_dev *dev;
+	struct v4l2_crop cr;
+
+	BUG_ON(!ctx || !ctx->fimc_dev);
+	dev = ctx->fimc_dev;
+
+	mutex_lock(&dev->lock);
+
+	if (fimc_fifo_active(dev) || list_empty(&outp->buf_q))
+		goto w_unlock;
+
+	/* Get the window parameters from framebuffer to apply its any
+	   aligment requirements. */
+	cr.type = V4L2_BUF_TYPE_VIDEO_OVERLAY;
+	v4l2_subdev_call(outp->sd[FIMC_LCD_FIFO_TARGET],
+			video, g_crop, &cr);
+
+	f->offs_h = cr.c.left;
+	f->offs_v = cr.c.top;
+	f->width = cr.c.width;
+	f->height = cr.c.height;
+
+	ctx->flags &= ~(FIMC_SRC_ADDR | FIMC_DST_ADDR);
+	ret = fimc_prepare_config(ctx, ctx->flags);
+	if (ret)
+		goto w_unlock;
+
+	spin_lock_irqsave(&dev->slock, flags);
+	outp->curr_buf = list_entry(outp->buf_q.next,
+		struct fimc_vid_buffer, vb.queue);
+
+	spin_lock(&dev->irqlock);
+	outp->curr_buf->vb.state = VIDEOBUF_ACTIVE;
+	spin_unlock(&dev->irqlock);
+
+	list_del(&outp->curr_buf->vb.queue);
+	fimc_prepare_addr(ctx, outp->curr_buf,
+				V4L2_BUF_TYPE_VIDEO_OUTPUT);
+	spin_unlock_irqrestore(&dev->slock, flags);
+
+	lcdfifo_try_run(ctx);
+
+w_unlock:
+	mutex_unlock(&dev->lock);
+}
+
+
+static int fimc_target_osd_sync(struct fimc_ctx *ctx)
+{
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct v4l2_cropcap osd;
+	struct v4l2_rect *r;
+	struct fimc_frame *frame;
+	u32 mod_x = DMA_MIN_SIZE - 1;
+	u32 mod_y = DMA_MIN_SIZE - 1;
+	int ret;
+
+	if (!dev || !dev->outp.sd[FIMC_LCD_FIFO_TARGET])
+		return -EINVAL;
+
+	ret = v4l2_subdev_call(dev->outp.sd[FIMC_LCD_FIFO_TARGET],
+				video, cropcap, &osd);
+	if (ret)
+		return ret;
+
+	r = &osd.defrect;
+	r->left &= ~mod_x;
+	r->top &= ~mod_y;
+	r->width &= ~mod_x;
+	r->height &= ~mod_y;
+
+	frame = &ctx->d_frame;
+	frame->f_width = r->width;
+	frame->f_height = r->height;
+	frame->width = r->width;
+	frame->height = r->height;
+	frame->o_width = r->width;
+	frame->o_height = r->height;
+	return 0;
+}
+
+/* Register any framebuffer fifo subdevices if not already registered. */
+static int fimc_register_fb_subdevices(struct fimc_dev *dev)
+{
+	struct s3c_fifo_link *link;
+	int i, ret = 0;
+
+	for (i = 0; i < FIMC_MAX_FIFO_TARGETS; i++) {
+		link = dev->pldata->fifo_targets[i];
+		if (!link)
+			continue;
+		mutex_lock(&link->slave_dev->mutex);
+		if (link->sub_dev) {
+			if (link->sub_dev->v4l2_dev) {
+				mutex_unlock(&link->slave_dev->mutex);
+				continue;
+			}
+			if (!v4l2_device_register_subdev(&dev->outp.v4l2_dev,
+							link->sub_dev)) {
+				v4l2_set_subdevdata(link->sub_dev, dev);
+				dev->outp.sd[i] = link->sub_dev;
+			} else {
+				dev->outp.sd[i] = NULL;
+				mutex_unlock(&link->slave_dev->mutex);
+				v4l2_err(&dev->outp.v4l2_dev,
+					 "Failed to register fb subdevice\n");
+				return -ENODEV;
+			}
+		}
+		mutex_unlock(&link->slave_dev->mutex);
+	}
+	return ret;
+}
+
+/* Unregister fifo target subdevices. */
+static void fimc_unregister_fb_subdevices(struct fimc_dev *dev)
+{
+	int i;
+	struct s3c_fifo_link *link;
+
+	for (i = 0; i < FIMC_MAX_FIFO_TARGETS; i++) {
+		link = dev->pldata->fifo_targets[i];
+		if (!link)
+			continue;
+		mutex_lock(&link->slave_dev->mutex);
+		if (dev->outp.sd[i]) {
+			v4l2_device_unregister_subdev(dev->outp.sd[i]);
+			dev->outp.sd[i] = NULL;
+		}
+		mutex_unlock(&link->slave_dev->mutex);
+	}
+}
+
+static int fimc_open(struct file *file)
+{
+	struct fimc_dev *dev = video_drvdata(file);
+	int ret;
+
+	mutex_lock(&dev->lock);
+
+	dbg("pid: %d, state: 0x%lx, refcnt= %d",
+		task_pid_nr(current), dev->state, dev->outp.refcnt);
+
+	if (dev->outp.refcnt++ == 0) {
+		ret = fimc_register_fb_subdevices(dev);
+		if (ret)
+			goto op_err;
+
+		if (!dev->outp.sd[FIMC_LCD_FIFO_TARGET]) {
+			v4l2_err(&dev->outp.v4l2_dev,
+				 "Lcd fifo subdevice not found\n");
+			ret = -ENODEV;
+			goto op_err;
+		}
+	}
+
+	file->private_data = dev->outp.ctx;
+
+op_err:
+	mutex_unlock(&dev->lock);
+	return ret;
+}
+
+static int fimc_close(struct file *file)
+{
+	struct fimc_dev *dev = video_drvdata(file);
+
+	mutex_lock(&dev->lock);
+
+	dbg("pid: %d, state: 0x%lx, refcnt= %d",
+		task_pid_nr(current), dev->state, dev->outp.refcnt);
+
+	if (--dev->outp.refcnt <= 0) {
+		fimc_stop_lcdfifo(dev);
+		videobuf_stop(&dev->outp.vbq);
+		fimc_unregister_fb_subdevices(dev);
+	}
+	dbg("pid: %d, state: 0x%lx, refcnt= %d",
+		task_pid_nr(current), dev->state, dev->outp.refcnt);
+
+	mutex_unlock(&dev->lock);
+	return 0;
+}
+
+static unsigned int fimc_poll(struct file *file,
+				     struct poll_table_struct *wait)
+{
+	return POLLERR;
+}
+
+static int fimc_mmap(struct file *file, struct vm_area_struct *vma)
+{
+	struct fimc_ctx *ctx = file->private_data;
+	struct v4l2_fimc_outp_dev *outp = &ctx->fimc_dev->outp;
+
+	return videobuf_mmap_mapper(&outp->vbq, vma);
+}
+
+/* video device file operations */
+static const struct v4l2_file_operations fimc_fops = {
+	.owner		= THIS_MODULE,
+	.open		= fimc_open,
+	.release	= fimc_close,
+	.poll		= fimc_poll,
+	.ioctl		= video_ioctl2,
+	.mmap		= fimc_mmap,
+};
+
+static int fimc_querycap_output(struct file *file, void *priv,
+			   struct v4l2_capability *cap)
+{
+	struct fimc_ctx *ctx = file->private_data;
+	struct fimc_dev *dev = ctx->fimc_dev;
+
+	strncpy(cap->driver, dev->pdev->name, sizeof(cap->driver) - 1);
+	strncpy(cap->card, dev->pdev->name, sizeof(cap->card) - 1);
+	cap->bus_info[0] = 0;
+	cap->version = KERNEL_VERSION(1, 0, 0);
+	cap->capabilities = V4L2_CAP_STREAMING |
+		V4L2_CAP_VIDEO_OVERLAY | V4L2_CAP_VIDEO_OUTPUT;
+
+	return 0;
+}
+
+static int fimc_g_fmt_output(struct file *file, void *priv,
+			     struct v4l2_format *f)
+{
+	struct fimc_ctx *ctx = priv;
+	struct fimc_frame *frame = &ctx->s_frame;
+
+	f->fmt.pix.width	= frame->width;
+	f->fmt.pix.height	= frame->height;
+	f->fmt.pix.field	= V4L2_FIELD_NONE;
+	f->fmt.pix.pixelformat	= frame->fmt->fourcc;
+
+	return 0;
+}
+
+static int fimc_try_fmt_output(struct file *file, void *priv,
+			     struct v4l2_format *f)
+{
+	struct fimc_fmt *fmt;
+	struct fimc_ctx *ctx = priv;
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct v4l2_pix_format *pix = &f->fmt.pix;
+	u32 max_width, max_height;
+	u32 mod_x = DMA_MIN_SIZE - 1;
+	u32 mod_y = DMA_MIN_SIZE - 1;
+
+	fmt = find_format(f);
+	if (!fmt) {
+		v4l2_err(&dev->outp.v4l2_dev,
+			 "Fourcc format (0x%08x) invalid.\n",
+			 pix->pixelformat);
+		return -EINVAL;
+	}
+
+	if (pix->field == V4L2_FIELD_ANY)
+		pix->field = V4L2_FIELD_NONE;
+	else if (V4L2_FIELD_NONE != pix->field)
+		return -EINVAL;
+
+	max_width = dev->pldata->scaler_dis_w;
+	max_height = dev->pldata->scaler_dis_w;
+
+	dbg("max_w= %d, max_h= %d", max_width, max_height);
+
+	if (pix->height > max_height)
+		pix->height = max_height;
+	if (pix->width > max_width)
+		pix->width = max_width;
+
+	if (tiled_fmt(fmt)) {
+		mod_x = (64 - 1); /* 64x32 tile */
+		mod_y = (32 - 1);
+	}
+
+	pix->width &= ~mod_x;
+	pix->height &= ~mod_y;
+	if (0 == pix->width)
+		pix->width = mod_x + 1;
+	if (0 == pix->height)
+		pix->height = mod_y + 1;
+
+	if (0 == pix->bytesperline) {
+		pix->bytesperline = (pix->width * fmt->depth) >> 3;
+	} else {
+		u32 f_width = pix->bytesperline*8/fmt->depth;
+		if (f_width > max_width)
+			pix->bytesperline = (max_width * fmt->depth) >> 3;
+	}
+
+	if (0 == pix->sizeimage)
+		pix->sizeimage = pix->height * pix->bytesperline;
+
+	dbg("pix->bytesperline= %d, fmt->depth= %d",
+	    pix->bytesperline, fmt->depth);
+
+	return 0;
+}
+
+
+static int fimc_s_fmt_output(struct file *file, void *priv,
+			     struct v4l2_format *f)
+{
+	struct fimc_frame *frame;
+	struct v4l2_pix_format *pix;
+	struct v4l2_format fmt;
+	struct fimc_ctx *ctx = priv;
+	struct fimc_dev *dev = ctx->fimc_dev;
+	int ret;
+
+	BUG_ON(!ctx);
+
+	if (fimc_fifo_active(dev))
+		return -EBUSY;
+
+	ret = fimc_try_fmt_output(file, priv, f);
+	if (ret)
+		return ret;
+
+	mutex_lock(&dev->lock);
+
+	frame = &ctx->s_frame;
+	pix = &f->fmt.pix;
+	frame->fmt = find_format(f);
+	if (!frame->fmt) {
+		mutex_unlock(&dev->lock);
+		return -EINVAL;
+	}
+
+	/* source frame format */
+	frame->f_width = pix->bytesperline*8/frame->fmt->depth;
+	frame->f_height = pix->sizeimage/pix->bytesperline;
+	frame->width = pix->width;
+	frame->height = pix->height;
+	frame->o_width = pix->width;
+	frame->o_height = pix->height;
+	frame->offs_h = 0;
+	frame->offs_v = 0;
+	frame->size = (pix->width * pix->height * frame->fmt->depth) >> 3;
+
+	/* destination frame format */
+	fimc_target_osd_sync(ctx);
+
+	fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_RGB24;
+	ret = v4l2_subdev_call(dev->outp.sd[FIMC_LCD_FIFO_TARGET],
+			       video, s_fmt, &fmt);
+
+	ctx->flags |= FIMC_PARAMS | FIMC_SRC_FMT;
+	mutex_unlock(&dev->lock);
+	return ret;
+}
+
+static int fimc_streamon_output(struct file *file, void *priv,
+			   enum v4l2_buf_type type)
+{
+	struct fimc_ctx *ctx = priv;
+	struct v4l2_fimc_outp_dev *outp = &ctx->fimc_dev->outp;
+
+	if (fimc_fifo_active(ctx->fimc_dev))
+		return -EBUSY;
+
+	return videobuf_streamon(&outp->vbq);
+}
+
+static int fimc_streamoff_output(struct file *file, void *priv,
+			    enum v4l2_buf_type type)
+{
+	unsigned long flags;
+	struct fimc_ctx *ctx = priv;
+	struct fimc_dev *dev = ctx->fimc_dev;
+	int ret = 0;
+
+	spin_lock_irqsave(&dev->slock, flags);
+
+	if (!fimc_fifo_active(dev)) {
+		spin_unlock_irqrestore(&dev->slock, flags);
+	} else {
+		spin_unlock_irqrestore(&dev->slock, flags);
+		fimc_stop_lcdfifo(dev);
+		ret = videobuf_streamoff(&dev->outp.vbq);
+	}
+	return ret;
+}
+
+static int fimc_reqbufs_output(struct file *file, void *priv,
+			  struct v4l2_requestbuffers *reqbufs)
+{
+	struct fimc_ctx *ctx = priv;
+	struct v4l2_fimc_outp_dev *outp = &ctx->fimc_dev->outp;
+
+	if (fimc_fifo_active(ctx->fimc_dev))
+		return -EBUSY;
+
+	return videobuf_reqbufs(&outp->vbq, reqbufs);
+}
+
+static int fimc_querybuf_output(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct fimc_ctx *ctx = priv;
+	struct v4l2_fimc_outp_dev *outp = &ctx->fimc_dev->outp;
+
+	if (fimc_fifo_active(ctx->fimc_dev))
+		return -EBUSY;
+
+	return videobuf_querybuf(&outp->vbq, buf);
+}
+
+static int fimc_qbuf_output(struct file *file, void *priv,
+			  struct v4l2_buffer *buf)
+{
+	struct fimc_ctx *ctx = priv;
+	struct v4l2_fimc_outp_dev *outp = &ctx->fimc_dev->outp;
+
+	return videobuf_qbuf(&outp->vbq, buf);
+}
+
+static int fimc_dqbuf_output(struct file *file, void *priv,
+			   struct v4l2_buffer *buf)
+{
+	struct fimc_ctx *ctx = priv;
+
+	return videobuf_dqbuf(&ctx->fimc_dev->outp.vbq, buf,
+		file->f_flags & O_NONBLOCK);
+}
+
+static int fimc_cropcap_output(struct file *file, void *fh,
+			     struct v4l2_cropcap *cr)
+{
+	struct fimc_ctx *ctx = fh;
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct fimc_frame *f = &ctx->s_frame;
+
+	if (cr->type == V4L2_BUF_TYPE_VIDEO_OVERLAY) {
+		return v4l2_subdev_call(dev->outp.sd[FIMC_LCD_FIFO_TARGET],
+					video, cropcap, cr);
+	} else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		cr->bounds.left = 0;
+		cr->bounds.top = 0;
+		cr->bounds.width = f->f_width;
+		cr->bounds.height = f->f_height;
+		cr->defrect.left = f->offs_h;
+		cr->defrect.top = f->offs_v;
+		cr->defrect.width = f->o_width;
+		cr->defrect.height = f->o_height;
+	} else {
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int fimc_g_crop_output(struct file *file, void *fh, struct v4l2_crop *cr)
+{
+	struct fimc_ctx *ctx = file->private_data;
+	struct fimc_frame *f = &ctx->s_frame;
+	struct fimc_dev *dev = ctx->fimc_dev;
+
+	if (cr->type == V4L2_BUF_TYPE_VIDEO_OVERLAY) {
+		return v4l2_subdev_call(dev->outp.sd[FIMC_LCD_FIFO_TARGET],
+					video, g_crop, cr);
+	} else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
+		cr->c.left = f->offs_h;
+		cr->c.top = f->offs_v;
+		cr->c.width = f->width;
+		cr->c.height = f->height;
+	} else {
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int fimc_s_crop_output(struct file *file, void *fh, struct v4l2_crop *cr)
+{
+	struct fimc_frame *f;
+	struct fimc_ctx *ctx = file->private_data;
+	struct fimc_dev *dev = ctx->fimc_dev;
+	int ret = 0;
+
+	if (fimc_fifo_active(dev))
+		return -EBUSY;
+
+	if (cr->c.top < 0 || cr->c.left < 0) {
+		v4l2_err(&dev->outp.v4l2_dev,
+			"doesn't support negative values for top & left\n");
+		return -EINVAL;
+	}
+
+	ctx_lcl_get_frame(f, ctx, cr->type);
+
+	/* adjust to DMA_MIN_SIZE pixel boundary */
+	cr->c.width = ALIGN(cr->c.width, DMA_MIN_SIZE);
+	cr->c.height = ALIGN(cr->c.height, DMA_MIN_SIZE);
+	cr->c.left = ALIGN(cr->c.left, DMA_MIN_SIZE);
+	cr->c.top = ALIGN(cr->c.top, DMA_MIN_SIZE);
+
+	dbg("%d %d %d %d f_w= %d, f_h= %d",
+		cr->c.left, cr->c.top, cr->c.width, cr->c.height,
+		f->f_width, f->f_height);
+
+	if ((cr->c.left + cr->c.width > f->o_width)
+		|| (cr->c.top + cr->c.height > f->o_height)) {
+		v4l2_err(&dev->outp.v4l2_dev, "Error in S_CROP params\n");
+		return -EINVAL;
+	}
+
+	if ((ctx->flags & FIMC_SRC_FMT) && (ctx->flags & FIMC_DST_FMT)) {
+		if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
+			ret = fimc_check_scaler_ratio(&cr->c, &ctx->d_frame);
+		else if (cr->type == V4L2_BUF_TYPE_VIDEO_OVERLAY)
+			ret = fimc_check_scaler_ratio(&cr->c, &ctx->s_frame);
+
+		if (ret) {
+			v4l2_err(&dev->outp.v4l2_dev,  "Out of scaler range");
+			return -EINVAL;
+		}
+	}
+
+	f->offs_h = cr->c.left;
+	f->offs_v = cr->c.top;
+	f->width = cr->c.width;
+	f->height = cr->c.height;
+
+	if (cr->type == V4L2_BUF_TYPE_VIDEO_OVERLAY)
+		return v4l2_subdev_call(dev->outp.sd[FIMC_LCD_FIFO_TARGET],
+					video, s_crop, cr);
+	return 0;
+}
+
+
+static const struct v4l2_ioctl_ops fimc_ioctl_ops = {
+	.vidioc_querycap		= fimc_querycap_output,
+
+	.vidioc_enum_fmt_vid_out	= fimc_m2m_enum_fmt,
+	.vidioc_try_fmt_vid_out		= fimc_try_fmt_output,
+	.vidioc_s_fmt_vid_out		= fimc_s_fmt_output,
+	.vidioc_g_fmt_vid_out		= fimc_g_fmt_output,
+
+	.vidioc_reqbufs			= fimc_reqbufs_output,
+	.vidioc_querybuf		= fimc_querybuf_output,
+
+	.vidioc_qbuf			= fimc_qbuf_output,
+	.vidioc_dqbuf			= fimc_dqbuf_output,
+
+	.vidioc_streamon		= fimc_streamon_output,
+	.vidioc_streamoff		= fimc_streamoff_output,
+
+	.vidioc_queryctrl		= fimc_m2m_queryctrl,
+	.vidioc_g_ctrl			= fimc_m2m_g_ctrl,
+	.vidioc_s_ctrl			= fimc_m2m_s_ctrl,
+
+	.vidioc_g_crop			= fimc_g_crop_output,
+	.vidioc_s_crop			= fimc_s_crop_output,
+	.vidioc_cropcap			= fimc_cropcap_output
+};
+
+/* Register FIMC video device for local fifo path mode. */
+int fimc_register_fifo_device(struct fimc_dev *dev)
+{
+	int ret = 0;
+	struct video_device *vfd;
+	struct fimc_ctx *ctx;
+	struct v4l2_device *v4l2_dev = &dev->outp.v4l2_dev;
+
+	/* set name if it is empty */
+	if (!v4l2_dev->name[0])
+		snprintf(v4l2_dev->name, sizeof(v4l2_dev->name),
+			 "%s.%d.v4l2_output", MODULE_NAME, dev->id);
+
+	ret = v4l2_device_register(NULL, v4l2_dev);
+	if (ret)
+		goto err_info;
+
+	vfd = video_device_alloc();
+	if (!vfd) {
+		v4l2_err(v4l2_dev, "Failed to allocate video device\n");
+		ret = -ENOMEM;
+		goto err_v4l2_reg;
+	}
+
+	vfd->fops	= &fimc_fops;
+	vfd->ioctl_ops	= &fimc_ioctl_ops;
+	vfd->minor	= -1;
+	vfd->release	= video_device_release;
+	snprintf(vfd->name, sizeof(vfd->name), "%s%d", MODULE_NAME, dev->id);
+
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
+	if (ret) {
+		v4l2_err(v4l2_dev, "Failed to register video device\n");
+		goto err_vd_reg;
+	}
+	video_set_drvdata(vfd, dev);
+
+	INIT_WORK(&dev->outp.work, fimc_worker);
+
+	dev->outp.vfd = vfd;
+	v4l2_dev->notify = fimc_v4l2_dev_notify;
+
+	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+	if (!ctx) {
+		ret = -ENOMEM;
+		goto err_ctx;
+	}
+	ctx->fimc_dev = dev;
+	/* default format RGB888 */
+	ctx->s_frame.fmt = &fimc_formats[2];
+	ctx->d_frame.fmt = &fimc_formats[2];
+
+	ctx->in_path = FIMC_DMA;
+	ctx->out_path = FIMC_LCDFIFO;
+	ctx->effect.type = S5P_FIMC_EFFECT_ORIGINAL;
+	ctx->flags |= FIMC_DST_FMT;
+	fimc_target_osd_sync(ctx);
+
+	dev->outp.ctx = ctx;
+
+	spin_lock_init(&ctx->slock);
+	INIT_LIST_HEAD(&dev->outp.buf_q);
+
+	/* source video bufer queue for output device in FIMC FIFO mode */
+	videobuf_queue_dma_contig_init(&dev->outp.vbq, &fimc_qops,
+		dev->outp.v4l2_dev.dev, &dev->irqlock,
+		V4L2_BUF_TYPE_VIDEO_OUTPUT, V4L2_FIELD_NONE,
+		sizeof(struct fimc_vid_buffer), (void *)ctx);
+
+	dev->outp.fmt.fmt.pix.pixelformat = V4L2_PIX_FMT_RGB24;
+	dev->outp.refcnt = 0;
+
+	v4l2_info(v4l2_dev, "FIMC fifo driver registered as /dev/video%d\n",
+		  vfd->num);
+	return 0;
+
+err_ctx:
+	video_unregister_device(dev->outp.vfd);
+err_vd_reg:
+	video_device_release(vfd);
+err_v4l2_reg:
+	v4l2_device_unregister(v4l2_dev);
+err_info:
+	dev_err(&dev->pdev->dev, "failed to install\n");
+	return ret;
+}
+
+void fimc_unregister_fifo_device(struct fimc_dev *dev)
+{
+	if (dev && dev->outp.vfd) {
+		video_unregister_device(dev->outp.vfd);
+		video_device_release(dev->outp.vfd);
+		v4l2_device_unregister(&dev->outp.v4l2_dev);
+		kfree(dev->outp.ctx);
+	}
+}
diff --git a/drivers/media/video/samsung-fimc/fimc-reg.c b/drivers/media/video/samsung-fimc/fimc-reg.c
new file mode 100644
index 0000000..93857f8
--- /dev/null
+++ b/drivers/media/video/samsung-fimc/fimc-reg.c
@@ -0,0 +1,572 @@
+/*
+ * Register interface file for Samsung Camera Interface (FIMC) driver
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Sylwester Nawrocki, s.nawrocki at samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <mach/map.h>
+#include <plat/regs-fimc.h>
+#include <plat/fimc.h>
+#include <linux/delay.h>
+
+#include "fimc-core.h"
+
+
+int fimc_hw_reset_fifo_ov(struct fimc_dev *dev)
+{
+	u32 cfg, status;
+
+	status = readl(dev->regs + S5P_CISTATUS);
+
+	if ((S5P_CISTATUS_OVFIY | S5P_CISTATUS_OVFICB | S5P_CISTATUS_OVFICR)
+		& status) {
+		cfg = readl(dev->regs + S5P_CIWDOFST);
+		cfg |= (S5P_CIWDOFST_CLROVFIY | S5P_CIWDOFST_CLROVFICB
+			| S5P_CIWDOFST_CLROVFICR);
+		writel(cfg, dev->regs + S5P_CIWDOFST);
+
+		cfg = readl(dev->regs + S5P_CIWDOFST);
+		cfg &= ~(S5P_CIWDOFST_CLROVFIY | S5P_CIWDOFST_CLROVFICB
+			| S5P_CIWDOFST_CLROVFICR);
+		writel(cfg, dev->regs + S5P_CIWDOFST);
+	}
+
+	return 0;
+}
+
+void fimc_hw_reset(struct fimc_dev *dev)
+{
+	u32 cfg;
+
+	cfg = readl(dev->regs + S5P_CISRCFMT);
+	cfg |= S5P_CISRCFMT_ITU601_8BIT;
+	writel(cfg, dev->regs + S5P_CISRCFMT);
+
+	/* sw reset */
+	cfg = readl(dev->regs + S5P_CIGCTRL);
+	cfg |= (S5P_CIGCTRL_SWRST | S5P_CIGCTRL_IRQ_LEVEL);
+	writel(cfg, dev->regs + S5P_CIGCTRL);
+	msleep(1);
+
+	cfg = readl(dev->regs + S5P_CIGCTRL);
+	cfg &= ~S5P_CIGCTRL_SWRST;
+	writel(cfg, dev->regs + S5P_CIGCTRL);
+
+}
+
+void fimc_hw_set_rotation(struct fimc_ctx *ctx)
+{
+	u32 cfg, flip;
+	struct fimc_dev *dev = ctx->fimc_dev;
+
+	cfg = readl(dev->regs + S5P_CITRGFMT);
+	cfg &= ~(S5P_CITRGFMT_INROT90 | S5P_CITRGFMT_OUTROT90);
+
+	flip = readl(dev->regs + S5P_MSCTRL);
+	flip &= ~S5P_MSCTRL_FLIP_MASK;
+
+	/* The input and output rotator cannot work simultaneously,
+	in input DMA mode only the output rotator shall be used. */
+	if (ctx->rotation == 90 || ctx->rotation == 270) {
+		if (ctx->out_path == FIMC_LCDFIFO) {
+			cfg |= S5P_CITRGFMT_INROT90;
+			if (ctx->rotation == 270)
+				flip |= S5P_MSCTRL_FLIP_180;
+		} else {
+			cfg |= S5P_CITRGFMT_OUTROT90;
+			if (ctx->rotation == 270)
+				cfg |= S5P_CITRGFMT_FLIP_180;
+		}
+	} else if (ctx->rotation == 180) {
+		if (ctx->out_path == FIMC_LCDFIFO)
+			flip |= S5P_MSCTRL_FLIP_180;
+		else
+			cfg |= S5P_CITRGFMT_FLIP_180;
+	}
+	if (ctx->rotation == 180 || ctx->rotation == 270)
+		writel(flip, dev->regs + S5P_MSCTRL);
+	writel(cfg, dev->regs + S5P_CITRGFMT);
+}
+
+static u32 fimc_hw_get_in_flip(u32 ctx_flip)
+{
+	u32 flip = S5P_MSCTRL_FLIP_NORMAL;
+
+	switch (ctx_flip) {
+	case FLIP_X_AXIS:
+		flip = S5P_MSCTRL_FLIP_X_MIRROR;
+		break;
+	case FLIP_Y_AXIS:
+		flip = S5P_MSCTRL_FLIP_Y_MIRROR;
+		break;
+	case FLIP_XY_AXIS:
+		flip = S5P_MSCTRL_FLIP_180;
+		break;
+	}
+
+	return flip;
+}
+
+static u32 fimc_hw_get_target_flip(u32 ctx_flip)
+{
+	u32 flip = S5P_CITRGFMT_FLIP_NORMAL;
+
+	switch (ctx_flip) {
+	case FLIP_X_AXIS:
+		flip = S5P_CITRGFMT_FLIP_X_MIRROR;
+		break;
+	case FLIP_Y_AXIS:
+		flip = S5P_CITRGFMT_FLIP_Y_MIRROR;
+		break;
+	case FLIP_XY_AXIS:
+		flip = S5P_CITRGFMT_FLIP_180;
+		break;
+	case FLIP_NONE:
+		break;
+
+	}
+	return flip;
+}
+
+void fimc_hw_set_target_format(struct fimc_ctx *ctx)
+{
+	u32 cfg;
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct fimc_frame *frame = &ctx->d_frame;
+
+	dbg("w= %d, h= %d color: %d", frame->width,
+		frame->height, frame->fmt->color);
+
+	cfg = readl(dev->regs + S5P_CITRGFMT);
+	cfg &= ~(S5P_CITRGFMT_OUT_FMT_MASK |
+		  S5P_CITRGFMT_HSIZE_MASK |
+		  S5P_CITRGFMT_VSIZE_MASK);
+
+	switch (frame->fmt->color) {
+	case S5P_FIMC_RGB565:
+	case S5P_FIMC_RGB666:
+	case S5P_FIMC_RGB888:
+		cfg |= S5P_CITRGFMT_OUTFORMAT_RGB;
+		break;
+	case S5P_FIMC_YCBCR420:
+		cfg |= S5P_CITRGFMT_OUTFORMAT_YCBCR420;
+		break;
+	case S5P_FIMC_YCBYCR422:
+	case S5P_FIMC_YCRYCB422:
+	case S5P_FIMC_CBYCRY422:
+	case S5P_FIMC_CRYCBY422:
+		if (frame->fmt->planes_cnt == 1)
+			cfg |= S5P_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
+		else
+			cfg |= S5P_CITRGFMT_OUTFORMAT_YCBCR422;
+		break;
+	default:
+		break;
+	}
+
+	cfg |= S5P_CITRGFMT_TARGETHSIZE(frame->width);
+	cfg |= S5P_CITRGFMT_TARGETVSIZE(frame->height);
+
+	if (!ctx->rotation) {
+		cfg &= ~S5P_CITRGFMT_FLIP_MASK;
+		cfg |= fimc_hw_get_target_flip(ctx->flip);
+	}
+	writel(cfg, dev->regs + S5P_CITRGFMT);
+
+	cfg = S5P_CITAREA_TARGET_AREA(frame->width * frame->height);
+	writel(cfg, dev->regs + S5P_CITAREA);
+}
+
+static void fimc_hw_set_out_dma_size(struct fimc_ctx *ctx)
+{
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct fimc_frame *frame = &ctx->d_frame;
+	u32 cfg = 0;
+
+	dbg("h= 0x%X  w= 0x%X", frame->f_width, frame->f_height);
+
+	if (ctx->rotation == 90 || ctx->rotation == 270) {
+		cfg |= S5P_ORGOSIZE_HORIZONTAL(frame->f_height);
+		cfg |= S5P_ORGOSIZE_VERTICAL(frame->f_width);
+	} else {
+		cfg |= S5P_ORGOSIZE_HORIZONTAL(frame->f_width);
+		cfg |= S5P_ORGOSIZE_VERTICAL(frame->f_height);
+	}
+	dbg("ORGOSIZE: 0x%X", cfg);
+	writel(cfg, dev->regs + S5P_ORGOSIZE);
+}
+
+void fimc_hw_set_out_dma(struct fimc_ctx *ctx)
+{
+	u32 cfg;
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct fimc_frame *frame = &ctx->d_frame;
+	struct fimc_dma_offset *offset = &frame->dma_offset;
+
+	/* input dma offsets */
+	cfg = 0;
+	cfg |= S5P_CIOYOFF_HORIZONTAL(offset->y_h);
+	cfg |= S5P_CIOYOFF_VERTICAL(offset->y_v);
+	writel(cfg, dev->regs + S5P_CIOYOFF);
+
+	cfg = 0;
+	cfg |= S5P_CIOCBOFF_HORIZONTAL(offset->cb_h);
+	cfg |= S5P_CIOCBOFF_VERTICAL(offset->cb_v);
+	writel(cfg, dev->regs + S5P_CIOCBOFF);
+
+	cfg = 0;
+	cfg |= S5P_CIOCROFF_HORIZONTAL(offset->cr_h);
+	cfg |= S5P_CIOCROFF_VERTICAL(offset->cr_v);
+	writel(cfg, dev->regs + S5P_CIOCROFF);
+
+	fimc_hw_set_out_dma_size(ctx);
+
+	/* configure chroma components order */
+	cfg = readl(dev->regs + S5P_CIOCTRL);
+
+	cfg &= ~(S5P_CIOCTRL_ORDER2P_MASK | S5P_CIOCTRL_ORDER422_MASK |
+		 S5P_CIOCTRL_YCBCR_PLANE_MASK);
+
+	if (frame->fmt->planes_cnt == 1)
+		cfg |= ctx->out_order_1p;
+	else if (frame->fmt->planes_cnt == 2)
+		cfg |= ctx->out_order_2p | S5P_CIOCTRL_YCBCR_2PLANE;
+	else if (frame->fmt->planes_cnt == 3)
+		cfg |= S5P_CIOCTRL_YCBCR_3PLANE;
+
+	writel(cfg, dev->regs + S5P_CIOCTRL);
+}
+
+void fimc_hw_en_autoload(struct fimc_dev *dev, int enable)
+{
+	u32 cfg = readl(dev->regs + S5P_ORGISIZE);
+	if (enable)
+		cfg |= S5P_CIREAL_ISIZE_AUTOLOAD_ENABLE;
+	else
+		cfg &= ~S5P_CIREAL_ISIZE_AUTOLOAD_ENABLE;
+	writel(cfg, dev->regs + S5P_ORGISIZE);
+}
+
+void fimc_hw_en_lastirq(struct fimc_dev *dev, int enable)
+{
+	unsigned long flags;
+	u32 cfg;
+
+	spin_lock_irqsave(&dev->slock, flags);
+
+	cfg = readl(dev->regs + S5P_CIOCTRL);
+	if (enable)
+		cfg |= S5P_CIOCTRL_LASTIRQ_ENABLE;
+	else
+		cfg &= ~S5P_CIOCTRL_LASTIRQ_ENABLE;
+	writel(cfg, dev->regs + S5P_CIOCTRL);
+
+	spin_unlock_irqrestore(&dev->slock, flags);
+}
+
+void fimc_hw_set_prescaler(struct fimc_ctx *ctx)
+{
+	struct fimc_dev *dev =  ctx->fimc_dev;
+	struct fimc_scaler *sc = &ctx->scaler;
+	u32 cfg = 0, shfactor;
+
+	shfactor = 10 - (sc->hfactor + sc->vfactor);
+
+	cfg |= S5P_CISCPRERATIO_SHFACTOR(shfactor);
+	cfg |= S5P_CISCPRERATIO_PREHORRATIO(sc->pre_hratio);
+	cfg |= S5P_CISCPRERATIO_PREVERRATIO(sc->pre_vratio);
+
+	writel(cfg, dev->regs + S5P_CISCPRERATIO);
+
+	cfg = 0;
+	cfg |= S5P_CISCPREDST_PREDSTWIDTH(sc->pre_dst_width);
+	cfg |= S5P_CISCPREDST_PREDSTHEIGHT(sc->pre_dst_height);
+
+	writel(cfg, dev->regs + S5P_CISCPREDST);
+}
+
+void fimc_hw_set_scaler(struct fimc_ctx *ctx)
+{
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct fimc_scaler *sc = &ctx->scaler;
+	struct fimc_frame *src_frame = &ctx->s_frame;
+	struct fimc_frame *dst_frame = &ctx->d_frame;
+	u32 cfg;
+
+	if (ctx->flags & S5P_FIMC_COLOR_RANGE_NARROW)
+		cfg = (S5P_CISCCTRL_CSCR2Y_NARROW|S5P_CISCCTRL_CSCY2R_NARROW);
+	else
+		cfg = (S5P_CISCCTRL_CSCR2Y_WIDE|S5P_CISCCTRL_CSCY2R_WIDE);
+
+	if (!sc->enabled)
+		cfg |= S5P_CISCCTRL_SCALERBYPASS;
+
+	if (sc->scaleup_h)
+		cfg |= S5P_CISCCTRL_SCALEUP_H;
+
+	if (sc->scaleup_v)
+		cfg |= S5P_CISCCTRL_SCALEUP_V;
+
+	if (sc->copy_mode)
+		cfg |= S5P_CISCCTRL_ONE2ONE;
+
+
+	if (ctx->in_path == FIMC_DMA) {
+		if (src_frame->fmt->color == S5P_FIMC_RGB565)
+			cfg |= S5P_CISCCTRL_INRGB_FMT_RGB565;
+		else if (src_frame->fmt->color == S5P_FIMC_RGB666)
+			cfg |= S5P_CISCCTRL_INRGB_FMT_RGB666;
+		else if (src_frame->fmt->color == S5P_FIMC_RGB888)
+			cfg |= S5P_CISCCTRL_INRGB_FMT_RGB888;
+	}
+
+	if (ctx->out_path == FIMC_DMA) {
+		if (dst_frame->fmt->color == S5P_FIMC_RGB565)
+			cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB565;
+		else if (dst_frame->fmt->color == S5P_FIMC_RGB666)
+			cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB666;
+		else if (dst_frame->fmt->color == S5P_FIMC_RGB888)
+			cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
+	} else {
+		cfg |= S5P_CISCCTRL_OUTRGB_FMT_RGB888;
+
+		if (ctx->flags&SCAN_MODE_INTERLACED)
+			cfg |= S5P_CISCCTRL_INTERLACE;
+		else
+			cfg |= S5P_CISCCTRL_PROGRESSIVE;
+	}
+
+	dbg("main_hratio= 0x%X  main_vratio= 0x%X",
+		sc->main_hratio, sc->main_vratio);
+
+	cfg |= S5P_CISCCTRL_MAINHORRATIO(sc->main_hratio);
+	cfg |= S5P_CISCCTRL_MAINVERRATIO(sc->main_vratio);
+
+	writel(cfg, dev->regs + S5P_CISCCTRL);
+}
+
+
+void fimc_hw_en_capture(struct fimc_ctx *ctx)
+{
+	struct fimc_dev *dev = ctx->fimc_dev;
+	u32 cfg = readl(dev->regs + S5P_CIIMGCPT);
+
+	if (FIMC_DMA == ctx->out_path) {
+		/* one shot mode */
+		cfg |= S5P_CIIMGCPT_CPT_FREN_ENABLE | S5P_CIIMGCPT_IMGCPTEN
+			| S5P_CIIMGCPT_CPT_FRMOD_EN;
+	} else {
+		/* freerun */
+		cfg &= ~(S5P_CIIMGCPT_CPT_FREN_ENABLE |
+			 S5P_CIIMGCPT_CPT_FRMOD_EN);
+		cfg |= S5P_CIIMGCPT_IMGCPTEN;
+	}
+
+	if (ctx->scaler.enabled)
+		cfg |= S5P_CIIMGCPT_IMGCPTEN_SC;
+
+	writel(cfg, dev->regs + S5P_CIIMGCPT);
+}
+
+void fimc_hw_shadow_dis(struct fimc_dev *dev, int off)
+{
+	u32 cfg = readl(dev->regs + S5P_CIGCTRL);
+	if (off)
+		cfg |= S5P_CIGCTRL_SHDW_DISABLE;
+	else
+		cfg &= ~S5P_CIGCTRL_SHDW_DISABLE;
+	writel(cfg, dev->regs + S5P_CIGCTRL);
+}
+
+
+void fimc_hw_set_effect(struct fimc_ctx *ctx)
+{
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct fimc_effect *effect = &ctx->effect;
+	u32 cfg = (S5P_CIIMGEFF_IE_ENABLE | S5P_CIIMGEFF_IE_SC_AFTER);
+
+	cfg |= effect->type;
+
+	if (effect->type == S5P_FIMC_EFFECT_ARBITRARY) {
+		cfg |= S5P_CIIMGEFF_PAT_CB(effect->pat_cb);
+		cfg |= S5P_CIIMGEFF_PAT_CR(effect->pat_cr);
+	}
+
+	writel(cfg, dev->regs + S5P_CIIMGEFF);
+}
+
+static void fimc_hw_set_in_dma_size(struct fimc_ctx *ctx)
+{
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct fimc_frame *frame = &ctx->s_frame;
+	u32 cfg_o = 0;
+	u32 cfg_r = 0;
+
+	if (FIMC_LCDFIFO == ctx->out_path)
+		cfg_r |=  S5P_CIREAL_ISIZE_AUTOLOAD_ENABLE;
+
+	cfg_o |= S5P_ORGISIZE_HORIZONTAL(frame->f_width);
+	cfg_o |= S5P_ORGISIZE_VERTICAL(frame->f_height);
+	cfg_r |= S5P_CIREAL_ISIZE_WIDTH(frame->width);
+	cfg_r |= S5P_CIREAL_ISIZE_HEIGHT(frame->height);
+
+	writel(cfg_o, dev->regs + S5P_ORGISIZE);
+	writel(cfg_r, dev->regs + S5P_CIREAL_ISIZE);
+}
+
+void fimc_hw_set_in_dma(struct fimc_ctx *ctx)
+{
+	struct fimc_dev *dev = ctx->fimc_dev;
+	struct fimc_frame *frame = &ctx->s_frame;
+	struct fimc_dma_offset *offset = &frame->dma_offset;
+	u32 cfg = 0;
+
+	/* offsets */
+	cfg |= S5P_CIIYOFF_HORIZONTAL(offset->y_h);
+	cfg |= S5P_CIIYOFF_VERTICAL(offset->y_v);
+	writel(cfg, dev->regs + S5P_CIIYOFF);
+
+	cfg = 0;
+	cfg |= S5P_CIICBOFF_HORIZONTAL(offset->cb_h);
+	cfg |= S5P_CIICBOFF_VERTICAL(offset->cb_v);
+	writel(cfg, dev->regs + S5P_CIICBOFF);
+
+	cfg = 0;
+	cfg |= S5P_CIICROFF_HORIZONTAL(offset->cr_h);
+	cfg |= S5P_CIICROFF_VERTICAL(offset->cr_v);
+	writel(cfg, dev->regs + S5P_CIICROFF);
+
+	/* original & real size */
+	fimc_hw_set_in_dma_size(ctx);
+
+	/* autoload is used currently only in FIFO mode */
+	fimc_hw_en_autoload(dev, ctx->out_path == FIMC_LCDFIFO);
+
+	/* input dma set to process single frame only */
+	cfg = readl(dev->regs + S5P_MSCTRL);
+	cfg &= ~(S5P_MSCTRL_FLIP_MASK
+		| S5P_MSCTRL_INFORMAT_MASK
+		| S5P_MSCTRL_IN_BURST_COUNT_MASK
+		| S5P_MSCTRL_INPUT_MASK
+		| S5P_MSCTRL_C_INT_IN_MASK
+		| S5P_MSCTRL_2P_IN_ORDER_MASK);
+
+	cfg |= (S5P_MSCTRL_SUCCESSIVE_COUNT(1) | S5P_MSCTRL_INPUT_MEMORY);
+
+	switch (frame->fmt->color) {
+	case S5P_FIMC_RGB565:
+	case S5P_FIMC_RGB666:
+	case S5P_FIMC_RGB888:
+		cfg |= S5P_MSCTRL_INFORMAT_RGB;
+		break;
+	case S5P_FIMC_YCBCR420:
+		cfg |= S5P_MSCTRL_INFORMAT_YCBCR420;
+
+		if (frame->fmt->planes_cnt == 2)
+			cfg |= ctx->in_order_2p | S5P_MSCTRL_C_INT_IN_2PLANE;
+		else
+			cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
+
+		break;
+	case S5P_FIMC_YCBYCR422:
+	case S5P_FIMC_YCRYCB422:
+	case S5P_FIMC_CBYCRY422:
+	case S5P_FIMC_CRYCBY422:
+		if (frame->fmt->planes_cnt == 1) {
+			cfg |= ctx->in_order_1p
+				| S5P_MSCTRL_INFORMAT_YCBCR422_1PLANE;
+		} else {
+			cfg |= S5P_MSCTRL_INFORMAT_YCBCR422;
+
+			if (frame->fmt->planes_cnt == 2)
+				cfg |= ctx->in_order_2p
+					| S5P_MSCTRL_C_INT_IN_2PLANE;
+			else
+				cfg |= S5P_MSCTRL_C_INT_IN_3PLANE;
+		}
+		break;
+	default:
+		break;
+	}
+
+	/* Input DMA flip mode (and rotation). Do not allow simultaneous
+	   rotation and flipping */
+	if (!ctx->rotation && ctx->out_path == FIMC_LCDFIFO)
+		cfg |= fimc_hw_get_in_flip(ctx->flip);
+
+	writel(cfg, dev->regs + S5P_MSCTRL);
+
+	/* in/out DMA linear/tiled mode */
+	cfg = readl(dev->regs + S5P_CIDMAPARAM);
+	cfg &= ~(S5P_CIDMAPARAM_R_MODE_64X32 | S5P_CIDMAPARAM_W_MODE_64X32);
+
+	if (tiled_fmt(ctx->s_frame.fmt))
+		cfg |= S5P_CIDMAPARAM_R_MODE_64X32;
+
+	if (tiled_fmt(ctx->d_frame.fmt))
+		cfg |= S5P_CIDMAPARAM_W_MODE_64X32;
+
+	writel(cfg, dev->regs + S5P_CIDMAPARAM);
+}
+
+
+void fimc_hw_set_input_path(struct fimc_ctx *ctx)
+{
+	struct fimc_dev *dev = ctx->fimc_dev;
+
+	u32 cfg = readl(dev->regs + S5P_MSCTRL);
+	cfg &= ~S5P_MSCTRL_INPUT_MASK;
+
+	if (ctx->in_path == FIMC_DMA)
+		cfg |= S5P_MSCTRL_INPUT_MEMORY;
+	else
+		cfg |= S5P_MSCTRL_INPUT_EXTCAM;
+
+	writel(cfg, dev->regs + S5P_MSCTRL);
+}
+
+void fimc_hw_set_output_path(struct fimc_ctx *ctx)
+{
+	struct fimc_dev *dev = ctx->fimc_dev;
+
+	u32 cfg = readl(dev->regs + S5P_CISCCTRL);
+	cfg &= ~S5P_CISCCTRL_LCDPATHEN_FIFO;
+	if (ctx->out_path == FIMC_LCDFIFO)
+		cfg |= S5P_CISCCTRL_LCDPATHEN_FIFO;
+	writel(cfg, dev->regs + S5P_CISCCTRL);
+}
+
+void fimc_hw_set_input_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
+{
+	u32 cfg = 0;
+
+	cfg = readl(dev->regs + S5P_CIREAL_ISIZE);
+	cfg |= S5P_CIREAL_ISIZE_ADDR_CH_DISABLE;
+	writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
+
+	writel(paddr->y, dev->regs + S5P_CIIYSA0);
+	writel(paddr->cb, dev->regs + S5P_CIICBSA0);
+	writel(paddr->cr, dev->regs + S5P_CIICRSA0);
+
+	cfg &= ~S5P_CIREAL_ISIZE_ADDR_CH_DISABLE;
+	writel(cfg, dev->regs + S5P_CIREAL_ISIZE);
+}
+
+void fimc_hw_set_output_addr(struct fimc_dev *dev, struct fimc_addr *paddr)
+{
+	int i = 0;
+	/* each of the four output register sets points to the same buffer */
+	for (i = 0; i < S5P_FIMC_MAX_FRAMES; i++) {
+		writel(paddr->y, dev->regs + S5P_CIOYSA(i));
+		writel(paddr->cb, dev->regs + S5P_CIOCBSA(i));
+		writel(paddr->cr, dev->regs + S5P_CIOCRSA(i));
+	}
+}
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index 047f7e6..974dc51 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -277,6 +277,7 @@ struct v4l2_pix_format {
 #define V4L2_PIX_FMT_RGB565  v4l2_fourcc('R', 'G', 'B', 'P') /* 16  RGB-5-6-5     */
 #define V4L2_PIX_FMT_RGB555X v4l2_fourcc('R', 'G', 'B', 'Q') /* 16  RGB-5-5-5 BE  */
 #define V4L2_PIX_FMT_RGB565X v4l2_fourcc('R', 'G', 'B', 'R') /* 16  RGB-5-6-5 BE  */
+#define V4L2_PIX_FMT_RGB666  v4l2_fourcc('R', 'G', 'B', 'H') /* 18  RGB-6-6-6	  */
 #define V4L2_PIX_FMT_BGR24   v4l2_fourcc('B', 'G', 'R', '3') /* 24  BGR-8-8-8     */
 #define V4L2_PIX_FMT_RGB24   v4l2_fourcc('R', 'G', 'B', '3') /* 24  RGB-8-8-8     */
 #define V4L2_PIX_FMT_BGR32   v4l2_fourcc('B', 'G', 'R', '4') /* 32  BGR-8-8-8-8   */
-- 
1.7.0.4



From s.nawrocki at samsung.com  Wed Jun 16 06:11:57 2010
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Wed, 16 Jun 2010 12:11:57 +0200
Subject: [PATCH 1/7] ARM: Samsung: Add FIMC driver register definition and
	platform helpers
In-Reply-To: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
References: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
Message-ID: <1276683123-30224-2-git-send-email-s.nawrocki@samsung.com>

FIMC device is a camera interface embedded in S5P Samsung SOC series. It
supports ITU-R BT.601/656 and MIPI-CSI standards, memory to memory
operations, color conversion, resizing and rotation.

Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/mach-s5pc100/Kconfig              |   15 ++
 arch/arm/mach-s5pc100/Makefile             |    3 +
 arch/arm/mach-s5pc100/include/mach/map.h   |    8 +
 arch/arm/mach-s5pc100/setup-fimc0.c        |   25 ++
 arch/arm/mach-s5pc100/setup-fimc1.c        |   25 ++
 arch/arm/mach-s5pc100/setup-fimc2.c        |   25 ++
 arch/arm/mach-s5pv210/Kconfig              |   15 ++
 arch/arm/mach-s5pv210/Makefile             |    3 +
 arch/arm/mach-s5pv210/include/mach/map.h   |    8 +
 arch/arm/mach-s5pv210/setup-fimc0.c        |   25 ++
 arch/arm/mach-s5pv210/setup-fimc1.c        |   25 ++
 arch/arm/mach-s5pv210/setup-fimc2.c        |   25 ++
 arch/arm/plat-s5p/Kconfig                  |   16 ++
 arch/arm/plat-s5p/Makefile                 |    3 +
 arch/arm/plat-s5p/dev-fimc0.c              |   58 +++++
 arch/arm/plat-s5p/dev-fimc1.c              |   56 +++++
 arch/arm/plat-s5p/dev-fimc2.c              |   56 +++++
 arch/arm/plat-s5p/include/plat/regs-fimc.h |  355 ++++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/fimc.h  |   58 +++++
 19 files changed, 804 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pc100/setup-fimc0.c
 create mode 100644 arch/arm/mach-s5pc100/setup-fimc1.c
 create mode 100644 arch/arm/mach-s5pc100/setup-fimc2.c
 create mode 100644 arch/arm/mach-s5pv210/setup-fimc0.c
 create mode 100644 arch/arm/mach-s5pv210/setup-fimc1.c
 create mode 100644 arch/arm/mach-s5pv210/setup-fimc2.c
 create mode 100644 arch/arm/plat-s5p/dev-fimc0.c
 create mode 100644 arch/arm/plat-s5p/dev-fimc1.c
 create mode 100644 arch/arm/plat-s5p/dev-fimc2.c
 create mode 100644 arch/arm/plat-s5p/include/plat/regs-fimc.h
 create mode 100644 arch/arm/plat-samsung/include/plat/fimc.h

diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b2a11df..81a06a3 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -36,6 +36,21 @@ config S5PC100_SETUP_SDHCI_GPIO
 	help
 	  Common setup code for SDHCI gpio.
 
+config S5PC100_SETUP_FIMC0
+	bool
+	help
+	  Setup code for FIMC controller 0
+
+config S5PC100_SETUP_FIMC1
+	bool
+	help
+	  Setup code for FIMC controller 1
+
+config S5PC100_SETUP_FIMC2
+	bool
+	help
+	  Setup code for FIMC controller 2
+
 config MACH_SMDKC100
 	bool "SMDKC100"
 	select CPU_S5PC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 543f3de..2984e8b 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -25,6 +25,9 @@ obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
 # device support
 obj-y				+= dev-audio.o
 obj-$(CONFIG_S3C64XX_DEV_SPI)	+= dev-spi.o
+obj-$(CONFIG_S5PC100_SETUP_FIMC0)	+= setup-fimc0.o
+obj-$(CONFIG_S5PC100_SETUP_FIMC1)	+= setup-fimc1.o
+obj-$(CONFIG_S5PC100_SETUP_FIMC2)	+= setup-fimc2.o
 
 # machine support
 
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index cadae43..aecfb24 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -112,6 +112,11 @@
 #define S5PC100_PA_SDRAM	(0x20000000)
 #define S5P_PA_SDRAM		S5PC100_PA_SDRAM
 
+/* FIMC */
+#define S5PC100_PA_FIMC0	(0xEE200000)
+#define S5PC100_PA_FIMC1	(0xEE300000)
+#define S5PC100_PA_FIMC2	(0xEE400000)
+
 /* compatibiltiy defines. */
 #define S3C_PA_UART		S5PC100_PA_UART
 #define S3C_PA_IIC		S5PC100_PA_IIC0
@@ -134,5 +139,8 @@
 #define S3C_PA_ONENAND		S5PC100_PA_ONENAND
 #define S3C_PA_ONENAND_BUF	S5PC100_PA_ONENAND_BUF
 #define S3C_SZ_ONENAND_BUF	S5PC100_SZ_ONENAND_BUF
+#define S5P_PA_FIMC0		S5PC100_PA_FIMC0
+#define S5P_PA_FIMC1		S5PC100_PA_FIMC1
+#define S5P_PA_FIMC2		S5PC100_PA_FIMC2
 
 #endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/setup-fimc0.c b/arch/arm/mach-s5pc100/setup-fimc0.c
new file mode 100644
index 0000000..decb27a
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-fimc0.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5pc100/setup-fimc0.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * S5PC100 - setup and capabilities definitions for S5P FIMC device 0
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/fimc.h>
+
+struct samsung_plat_fimc s5p_fimc0_default_data __initdata = {
+	.capability	= S5P_FIMC_IN_ROT | S5P_FIMC_OUT_ROT,
+	/* scaler input pixel size constraints */
+	.scaler_en_w	= 3264,
+	.scaler_dis_w	= 8192,
+	/* input rotator limits for (input) image pixel size */
+	.in_rot_en_h	= 1280,
+	.in_rot_dis_w	= 8192,
+	/* output rotator limits for (output) image pixel size */
+	.out_rot_en_w	= 1280,
+	.out_rot_dis_w	= 3264
+};
diff --git a/arch/arm/mach-s5pc100/setup-fimc1.c b/arch/arm/mach-s5pc100/setup-fimc1.c
new file mode 100644
index 0000000..a74a231
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-fimc1.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5pc100/setup-fimc1.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * S5PC100 - setup and capabilities definitions for S5P FIMC device 1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/fimc.h>
+
+struct samsung_plat_fimc s5p_fimc1_default_data __initdata = {
+	.capability	= S5P_FIMC_IN_ROT | S5P_FIMC_OUT_ROT,
+	/* scaler input pixel size constraints */
+	.scaler_en_w	= 1280,
+	.scaler_dis_w	= 8192,
+	/* input rotator limits for (input) image pixel size */
+	.in_rot_en_h	= 768,
+	.in_rot_dis_w	= 8192,
+	/* output rotator limits for (output) image pixel size */
+	.out_rot_en_w	= 768,
+	.out_rot_dis_w	= 1280
+};
diff --git a/arch/arm/mach-s5pc100/setup-fimc2.c b/arch/arm/mach-s5pc100/setup-fimc2.c
new file mode 100644
index 0000000..c707e6a
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-fimc2.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5pc100/setup-fimc2.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * S5PC100 - setup and capabilities definitions for S5P FIMC device 2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/fimc.h>
+
+struct samsung_plat_fimc s5p_fimc2_default_data __initdata = {
+	.capability	= 0,
+	/* scaler input pixel size constraints */
+	.scaler_en_w	= 1440,
+	.scaler_dis_w	= 8192,
+	/* input rotator limits for (input) image pixel size */
+	.in_rot_en_h	= 0,
+	.in_rot_dis_w	= 1440,
+	/* output rotator limits for (output) image pixel size */
+	.out_rot_en_w	= 0,
+	.out_rot_dis_w	= 1440
+};
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0761eac..7cbba86 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -32,6 +32,21 @@ config S5PV210_SETUP_FB_24BPP
 	help
           Common setup code for S5PV210 with an 24bpp RGB display helper.
 
+config S5PV210_SETUP_FIMC0
+	bool
+	help
+	  Setup code for FIMC controller 0
+
+config S5PV210_SETUP_FIMC1
+	bool
+	help
+	  Setup code for FIMC controller 1
+
+config S5PV210_SETUP_FIMC2
+	bool
+	help
+	  Setup code for FIMC controller 2
+
 config S5PV210_SETUP_SDHCI
         bool
         select S5PV210_SETUP_SDHCI_GPIO
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 30be9a6..dbadbab 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -33,3 +33,6 @@ obj-$(CONFIG_S5PV210_SETUP_I2C1) 	+= setup-i2c1.o
 obj-$(CONFIG_S5PV210_SETUP_I2C2) 	+= setup-i2c2.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
+obj-$(CONFIG_S5PV210_SETUP_FIMC0)	+= setup-fimc0.o
+obj-$(CONFIG_S5PV210_SETUP_FIMC1)	+= setup-fimc1.o
+obj-$(CONFIG_S5PV210_SETUP_FIMC2)	+= setup-fimc2.o
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 34eb168..6dd7b10 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -92,6 +92,11 @@
 
 #define S5PV210_PA_ADC		(0xE1700000)
 
+/* FIMC */
+#define S5PV210_PA_FIMC0	(0xFB200000)
+#define S5PV210_PA_FIMC1	(0xFB300000)
+#define S5PV210_PA_FIMC2	(0xFB400000)
+
 /* compatibiltiy defines. */
 #define S3C_PA_UART		S5PV210_PA_UART
 #define S3C_PA_HSMMC0		S5PV210_PA_HSMMC(0)
@@ -104,5 +109,8 @@
 #define S3C_PA_WDT		S5PV210_PA_WATCHDOG
 
 #define SAMSUNG_PA_ADC		S5PV210_PA_ADC
+#define S5P_PA_FIMC0		S5PV210_PA_FIMC0
+#define S5P_PA_FIMC1		S5PV210_PA_FIMC1
+#define S5P_PA_FIMC2		S5PV210_PA_FIMC2
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/setup-fimc0.c b/arch/arm/mach-s5pv210/setup-fimc0.c
new file mode 100644
index 0000000..94205f5
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-fimc0.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5pv210/setup-fimc0.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * S5PV210 - setup and capabilities definitions for S5P FIMC device 0
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/fimc.h>
+
+struct samsung_plat_fimc s5p_fimc0_default_data __initdata = {
+	.capability	= S5P_FIMC_IN_ROT | S5P_FIMC_OUT_ROT,
+	/* scaler input pixel size constraints */
+	.scaler_en_w	= 4224,
+	.scaler_dis_w	= 8192,
+	/* input rotator limits for (input) image pixel size */
+	.in_rot_en_h	= 1920,
+	.in_rot_dis_w	= 8192,
+	/* output rotator limits for (output) image pixel size */
+	.out_rot_en_w	= 1920,
+	.out_rot_dis_w	= 4224
+};
diff --git a/arch/arm/mach-s5pv210/setup-fimc1.c b/arch/arm/mach-s5pv210/setup-fimc1.c
new file mode 100644
index 0000000..bfaffe9
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-fimc1.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5pv210/setup-fimc1.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * S5PV210 - setup and capabilities definitions for S5P FIMC device 1
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/fimc.h>
+
+struct samsung_plat_fimc s5p_fimc1_default_data __initdata = {
+	.capability	= S5P_FIMC_IN_ROT | S5P_FIMC_OUT_ROT,
+	/* scaler input pixel size constraints */
+	.scaler_en_w	= 4224,
+	.scaler_dis_w	= 8192,
+	/* input rotator limits for (input) image pixel size */
+	.in_rot_en_h	= 1920,
+	.in_rot_dis_w	= 8192,
+	/* output rotator limits for (output) image pixel size */
+	.out_rot_en_w	= 1920,
+	.out_rot_dis_w	= 4224
+};
diff --git a/arch/arm/mach-s5pv210/setup-fimc2.c b/arch/arm/mach-s5pv210/setup-fimc2.c
new file mode 100644
index 0000000..a53a382
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-fimc2.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5pv210/setup-fimc2.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * S5PV210 - setup and capabilities definitions for S5P FIMC device 2
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <plat/fimc.h>
+
+struct samsung_plat_fimc s5p_fimc2_default_data __initdata = {
+	.capability	= S5P_FIMC_IN_ROT | S5P_FIMC_OUT_ROT,
+	/* scaler input pixel size constraints */
+	.scaler_en_w	= 1920,
+	.scaler_dis_w	= 8192,
+	/* input rotator limits for (input) image pixel size */
+	.in_rot_en_h	= 1280,
+	.in_rot_dis_w	= 8192,
+	/* output rotator limits for (output) image pixel size */
+	.out_rot_en_w	= 1280,
+	.out_rot_dis_w	= 1920
+};
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 11d6a1b..38b60c7 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -5,6 +5,22 @@
 #
 # Licensed under GPLv2
 
+config S5P_DEV_FIMC0
+	bool
+	help
+	  Compile in platform device definitions for FIMC controller 0
+
+config S5P_DEV_FIMC1
+	bool
+	help
+	  Compile in platform device definitions for FIMC controller 1
+
+config S5P_DEV_FIMC2
+	bool
+	help
+	  Compile in platform device definitions for FIMC controller 2
+
+
 config PLAT_S5P
 	bool
 	depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210)
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 39c242b..9776a76 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -18,3 +18,6 @@ obj-y				+= clock.o
 obj-y				+= irq.o
 obj-$(CONFIG_S5P_EXT_INT)	+= irq-eint.o
 
+obj-$(CONFIG_S5P_DEV_FIMC0)	+= dev-fimc0.o
+obj-$(CONFIG_S5P_DEV_FIMC1)	+= dev-fimc1.o
+obj-$(CONFIG_S5P_DEV_FIMC2)	+= dev-fimc2.o
diff --git a/arch/arm/plat-s5p/dev-fimc0.c b/arch/arm/plat-s5p/dev-fimc0.c
new file mode 100644
index 0000000..ceb729d
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimc0.c
@@ -0,0 +1,58 @@
+/* linux/arch/arm/plat-s5p/dev-fimc0.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Base S5P FIMC0 resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <plat/fimc.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+
+
+static struct resource s5p_fimc_resource[] = {
+	[0] = {
+		.start	= S5P_PA_FIMC0,
+		.end	= S5P_PA_FIMC0 + SZ_1M - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_FIMC0,
+		.end	= IRQ_FIMC0,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device s5p_device_fimc0 = {
+	.name		= "s5p-fimc",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(s5p_fimc_resource),
+	.resource	= s5p_fimc_resource,
+};
+
+
+void __init s5p_fimc0_set_platdata(struct samsung_plat_fimc *pd)
+{
+	struct samsung_plat_fimc *npd;
+
+	if (!pd)
+		pd = &s5p_fimc0_default_data;
+
+	npd = kmemdup(pd, sizeof(*npd), GFP_KERNEL);
+	if (!npd)
+		printk(KERN_ERR "%s: platform_data allocation failed\n",
+			__func__);
+
+	s5p_device_fimc0.dev.platform_data = npd;
+}
+
diff --git a/arch/arm/plat-s5p/dev-fimc1.c b/arch/arm/plat-s5p/dev-fimc1.c
new file mode 100644
index 0000000..af49852
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimc1.c
@@ -0,0 +1,56 @@
+/* linux/arch/arm/plat-s5p/dev-fimc1.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Base S5P FIMC1 resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <plat/fimc.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+
+static struct resource s5p_fimc_resource[] = {
+	[0] = {
+		.start	= S5P_PA_FIMC1,
+		.end	= S5P_PA_FIMC1 + SZ_1M - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_FIMC1,
+		.end	= IRQ_FIMC1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device s5p_device_fimc1 = {
+	.name		= "s5p-fimc",
+	.id		= 1,
+	.num_resources	= ARRAY_SIZE(s5p_fimc_resource),
+	.resource	= s5p_fimc_resource,
+};
+
+void __init s5p_fimc1_set_platdata(struct samsung_plat_fimc *pd)
+{
+	struct samsung_plat_fimc *npd;
+
+	if (!pd)
+		pd = &s5p_fimc1_default_data;
+
+	npd = kmemdup(pd, sizeof(*npd), GFP_KERNEL);
+	if (!npd)
+		printk(KERN_ERR "%s: platform_data allocation failed\n",
+			__func__);
+
+	s5p_device_fimc1.dev.platform_data = npd;
+}
+
diff --git a/arch/arm/plat-s5p/dev-fimc2.c b/arch/arm/plat-s5p/dev-fimc2.c
new file mode 100644
index 0000000..4082e76
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimc2.c
@@ -0,0 +1,56 @@
+/* linux/arch/arm/plat-s5p/dev-fimc2.c
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Base S5P FIMC2 resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+#include <mach/irqs.h>
+#include <plat/fimc.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+
+static struct resource s5p_fimc_resource[] = {
+	[0] = {
+		.start	= S5P_PA_FIMC2,
+		.end	= S5P_PA_FIMC2 + SZ_1M - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_FIMC2,
+		.end	= IRQ_FIMC2,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device s5p_device_fimc2 = {
+	.name		= "s5p-fimc",
+	.id		= 2,
+	.num_resources	= ARRAY_SIZE(s5p_fimc_resource),
+	.resource	= s5p_fimc_resource,
+};
+
+void __init s5p_fimc2_set_platdata(struct samsung_plat_fimc *pd)
+{
+	struct samsung_plat_fimc *npd;
+
+	if (!pd)
+		pd = &s5p_fimc2_default_data;
+
+	npd = kmemdup(pd, sizeof(*npd), GFP_KERNEL);
+	if (!npd)
+		printk(KERN_ERR "%s: platform_data allocation failed\n",
+			__func__);
+
+	s5p_device_fimc2.dev.platform_data = npd;
+}
+
diff --git a/arch/arm/plat-s5p/include/plat/regs-fimc.h b/arch/arm/plat-s5p/include/plat/regs-fimc.h
new file mode 100644
index 0000000..84a221a
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/regs-fimc.h
@@ -0,0 +1,355 @@
+/* arch/arm/plat-s5p/include/plat/regs-fimc.h
+ *
+ * Register definition file for Samsung Camera Interface (FIMC) driver
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef REGS_FIMC_H_
+#define REGS_FIMC_H_
+
+#define S5P_CIOYSA(__x)				(0x18 + (__x) * 4)
+#define S5P_CIOCBSA(__x)			(0x28 + (__x) * 4)
+#define S5P_CIOCRSA(__x)			(0x38 + (__x) * 4)
+
+/* Input source format */
+#define S5P_CISRCFMT				0x00
+/* Window offset */
+#define S5P_CIWDOFST				0x04
+/* Global control */
+#define S5P_CIGCTRL				0x08
+/* Window offset 2 */
+#define S5P_CIWDOFST2				0x14
+/* Output DMA Y 1st frame start address */
+#define S5P_CIOYSA1				0x18
+/* Output DMA Y 2nd frame start address */
+#define S5P_CIOYSA2				0x1c
+/* Output DMA Y 3rd frame start address */
+#define S5P_CIOYSA3				0x20
+/* Output DMA Y 4th frame start address */
+#define S5P_CIOYSA4				0x24
+/* Output DMA Cb 1st frame start address */
+#define S5P_CIOCBSA1				0x28
+/* Output DMA Cb 2nd frame start address */
+#define S5P_CIOCBSA2				0x2c
+/* Output DMA Cb 3rd frame start address */
+#define S5P_CIOCBSA3				0x30
+/* Output DMA Cb 4th frame start address */
+#define S5P_CIOCBSA4				0x34
+/* Output DMA Cr 1st frame start address */
+#define S5P_CIOCRSA1				0x38
+/* Output DMA Cr 2nd frame start address */
+#define S5P_CIOCRSA2				0x3c
+/* Output DMA Cr 3rd frame start address */
+#define S5P_CIOCRSA3				0x40
+/* Output DMA Cr 4th frame start address */
+#define S5P_CIOCRSA4				0x44
+/* Target image format */
+#define S5P_CITRGFMT				0x48
+/* Output DMA control */
+#define S5P_CIOCTRL				0x4c
+/* Pre-scaler control 1 */
+#define S5P_CISCPRERATIO			0x50
+/* Pre-scaler control 2 */
+#define S5P_CISCPREDST				0x54
+/* Main scaler control */
+#define S5P_CISCCTRL				0x58
+/* Target area */
+#define S5P_CITAREA				0x5c
+/* Status */
+#define S5P_CISTATUS				0x64
+/* Image capture enable command */
+#define S5P_CIIMGCPT				0xc0
+/* Capture sequence */
+#define S5P_CICPTSEQ				0xc4
+/* Image effects */
+#define S5P_CIIMGEFF				0xd0
+/* Y frame start address for input DMA */
+#define S5P_CIIYSA0				0xd4
+/* Cb frame start address for input DMA */
+#define S5P_CIICBSA0				0xd8
+/* Cr frame start address for input DMA */
+#define S5P_CIICRSA0				0xdc
+/* Real input DMA image size */
+#define S5P_CIREAL_ISIZE			0xf8
+/* Input DMA control */
+#define S5P_MSCTRL				0xfc
+/* Output DMA Y offset */
+#define S5P_CIOYOFF				0x168
+/* Output DMA CB offset */
+#define S5P_CIOCBOFF				0x16c
+/* Output DMA CR offset */
+#define S5P_CIOCROFF				0x170
+/* Input DMA Y offset */
+#define S5P_CIIYOFF				0x174
+/* Input DMA CB offset */
+#define S5P_CIICBOFF				0x178
+/* Input DMA CR offset */
+#define S5P_CIICROFF				0x17c
+/* Input DMA original image size */
+#define S5P_ORGISIZE				0x180
+/* Output DMA original image size */
+#define S5P_ORGOSIZE				0x184
+/* Real output DMA image size */
+#define S5P_CIEXTEN				0x188
+/* DMA parameter */
+#define S5P_CIDMAPARAM				0x18c
+/* MIPI CSI image format */
+#define S5P_CSIIMGFMT				0x194
+
+
+#define S5P_CISRCFMT_SOURCEHSIZE(x)		((x) << 16)
+#define S5P_CISRCFMT_SOURCEVSIZE(x)		((x) << 0)
+
+#define S5P_CIWDOFST_WINHOROFST(x)		((x) << 16)
+#define S5P_CIWDOFST_WINVEROFST(x)		((x) << 0)
+
+#define S5P_CIWDOFST2_WINHOROFST2(x)		((x) << 16)
+#define S5P_CIWDOFST2_WINVEROFST2(x)		((x) << 0)
+
+#define S5P_CITRGFMT_TARGETHSIZE(x)		((x) << 16)
+#define S5P_CITRGFMT_TARGETVSIZE(x)		((x) << 0)
+
+#define S5P_CISCPRERATIO_SHFACTOR(x)		((x) << 28)
+#define S5P_CISCPRERATIO_PREHORRATIO(x)		((x) << 16)
+#define S5P_CISCPRERATIO_PREVERRATIO(x)		((x) << 0)
+
+#define S5P_CISCPREDST_PREDSTWIDTH(x)		((x) << 16)
+#define S5P_CISCPREDST_PREDSTHEIGHT(x)		((x) << 0)
+
+#define S5P_CISCCTRL_MAINHORRATIO(x)		((x) << 16)
+#define S5P_CISCCTRL_MAINVERRATIO(x)		((x) << 0)
+
+#define S5P_CITAREA_TARGET_AREA(x)		((x) << 0)
+
+#define S5P_CIIMGEFF_PAT_CB(x)			((x) << 13)
+#define S5P_CIIMGEFF_PAT_CR(x)			((x) << 0)
+
+#define S5P_CIREAL_ISIZE_HEIGHT(x)		((x) << 16)
+#define S5P_CIREAL_ISIZE_WIDTH(x)		((x) << 0)
+
+#define S5P_MSCTRL_SUCCESSIVE_COUNT(x)		((x) << 24)
+
+#define S5P_CIOYOFF_VERTICAL(x)			((x) << 16)
+#define S5P_CIOYOFF_HORIZONTAL(x)		((x) << 0)
+
+#define S5P_CIOCBOFF_VERTICAL(x)		((x) << 16)
+#define S5P_CIOCBOFF_HORIZONTAL(x)		((x) << 0)
+
+#define S5P_CIOCROFF_VERTICAL(x)		((x) << 16)
+#define S5P_CIOCROFF_HORIZONTAL(x)		((x) << 0)
+
+#define S5P_CIIYOFF_VERTICAL(x)			((x) << 16)
+#define S5P_CIIYOFF_HORIZONTAL(x)		((x) << 0)
+
+#define S5P_CIICBOFF_VERTICAL(x)		((x) << 16)
+#define S5P_CIICBOFF_HORIZONTAL(x)		((x) << 0)
+
+#define S5P_CIICROFF_VERTICAL(x)		((x) << 16)
+#define S5P_CIICROFF_HORIZONTAL(x)		((x) << 0)
+
+#define S5P_ORGISIZE_VERTICAL(x)		((x) << 16)
+#define S5P_ORGISIZE_HORIZONTAL(x)		((x) << 0)
+
+#define S5P_ORGOSIZE_VERTICAL(x)		((x) << 16)
+#define S5P_ORGOSIZE_HORIZONTAL(x)		((x) << 0)
+
+
+/* Register's bit definitions */
+
+/* Source format register */
+#define S5P_CISRCFMT_ITU601_8BIT		(1 << 31)
+#define S5P_CISRCFMT_ITU656_8BIT		(0 << 31)
+#define S5P_CISRCFMT_ITU601_16BIT		(1 << 29)
+#define S5P_CISRCFMT_ORDER422_YCBYCR		(0 << 14)
+#define S5P_CISRCFMT_ORDER422_YCRYCB		(1 << 14)
+#define S5P_CISRCFMT_ORDER422_CBYCRY		(2 << 14)
+#define S5P_CISRCFMT_ORDER422_CRYCBY		(3 << 14)
+/* ITU601 16bit only */
+#define S5P_CISRCFMT_ORDER422_Y4CBCRCBCR	(0 << 14)
+/* ITU601 16bit only */
+#define S5P_CISRCFMT_ORDER422_Y4CRCBCRCB	(1 << 14)
+
+/* Window offset register */
+#define S5P_CIWDOFST_WINOFSEN			(1 << 31)
+#define S5P_CIWDOFST_CLROVFIY			(1 << 30)
+#define S5P_CIWDOFST_CLROVRLB			(1 << 29)
+#define S5P_CIWDOFST_WINHOROFST_MASK		(0x7ff << 16)
+#define S5P_CIWDOFST_CLROVFICB			(1 << 15)
+#define S5P_CIWDOFST_CLROVFICR			(1 << 14)
+#define S5P_CIWDOFST_WINVEROFST_MASK		(0xfff << 0)
+
+/* Global control register */
+#define S5P_CIGCTRL_SWRST			(1 << 31)
+#define S5P_CIGCTRL_CAMRST_A			(1 << 30)
+#define S5P_CIGCTRL_SELCAM_ITU_B		(0 << 29)
+#define S5P_CIGCTRL_SELCAM_ITU_A		(1 << 29)
+#define S5P_CIGCTRL_SELCAM_ITU_MASK		(1 << 29)
+#define S5P_CIGCTRL_TESTPAT_NORMAL		(0 << 27)
+#define S5P_CIGCTRL_TESTPAT_COLOR_BAR		(1 << 27)
+#define S5P_CIGCTRL_TESTPAT_HOR_INC		(2 << 27)
+#define S5P_CIGCTRL_TESTPAT_VER_INC		(3 << 27)
+#define S5P_CIGCTRL_TESTPAT_MASK		(3 << 27)
+#define S5P_CIGCTRL_TESTPAT_SHIFT		(27)
+#define S5P_CIGCTRL_INVPOLPCLK			(1 << 26)
+#define S5P_CIGCTRL_INVPOLVSYNC			(1 << 25)
+#define S5P_CIGCTRL_INVPOLHREF			(1 << 24)
+#define S5P_CIGCTRL_IRQ_OVFEN			(1 << 22)
+#define S5P_CIGCTRL_HREF_MASK			(1 << 21)
+#define S5P_CIGCTRL_IRQ_EDGE			(0 << 20)
+#define S5P_CIGCTRL_IRQ_LEVEL			(1 << 20)
+#define S5P_CIGCTRL_IRQ_CLR			(1 << 19)
+#define S5P_CIGCTRL_IRQ_DISABLE			(0 << 16)
+#define S5P_CIGCTRL_IRQ_ENABLE			(1 << 16)
+#define S5P_CIGCTRL_SHDW_DISABLE		(1 << 12)
+#define S5P_CIGCTRL_SELCAM_MIPI_B		(0 << 7)
+#define S5P_CIGCTRL_SELCAM_MIPI_A		(1 << 7)
+#define S5P_CIGCTRL_SELCAM_MIPI_MASK		(1 << 7)
+#define S5P_CIGCTRL_CAMIF_SELWB			(1 << 6)
+#define S5P_CIGCTRL_INVPOLHSYNC			(1 << 4)
+#define S5P_CIGCTRL_SELCAM_ITU			(0 << 3)
+#define S5P_CIGCTRL_SELCAM_MIPI			(1 << 3)
+#define S5P_CIGCTRL_PROGRESSIVE			(0 << 0)
+#define S5P_CIGCTRL_INTERLACE			(1 << 0)
+
+/* Window offset2 register */
+#define S5P_CIWDOFST_WINHOROFST2_MASK		(0xfff << 16)
+#define S5P_CIWDOFST_WINVEROFST2_MASK		(0xfff << 16)
+
+/* Target format register */
+#define S5P_CITRGFMT_INROT90			(1 << 31)
+#define S5P_CITRGFMT_OUTFORMAT_YCBCR420		(0 << 29)
+#define S5P_CITRGFMT_OUTFORMAT_YCBCR422		(1 << 29)
+#define S5P_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE	(2 << 29)
+#define S5P_CITRGFMT_OUTFORMAT_RGB		(3 << 29)
+#define S5P_CITRGFMT_OUT_FMT_MASK		(3 << 29)
+#define S5P_CITRGFMT_HSIZE_MASK			(0xfff << 16)
+#define S5P_CITRGFMT_FLIP_SHIFT			(14)
+#define S5P_CITRGFMT_FLIP_NORMAL		(0 << 14)
+#define S5P_CITRGFMT_FLIP_X_MIRROR		(1 << 14)
+#define S5P_CITRGFMT_FLIP_Y_MIRROR		(2 << 14)
+#define S5P_CITRGFMT_FLIP_180			(3 << 14)
+#define S5P_CITRGFMT_FLIP_MASK			(3 << 14)
+#define S5P_CITRGFMT_OUTROT90			(1 << 13)
+#define S5P_CITRGFMT_VSIZE_MASK			(0xfff << 0)
+
+/* Output DMA control register */
+#define S5P_CIOCTRL_ORDER422_MASK		(3 << 0)
+#define S5P_CIOCTRL_ORDER422_CRYCBY		(0 << 0)
+#define S5P_CIOCTRL_ORDER422_YCRYCB		(1 << 0)
+#define S5P_CIOCTRL_ORDER422_CBYCRY		(2 << 0)
+#define S5P_CIOCTRL_ORDER422_YCBYCR		(3 << 0)
+#define S5P_CIOCTRL_LASTIRQ_ENABLE		(1 << 2)
+#define S5P_CIOCTRL_YCBCR_3PLANE		(0 << 3)
+#define S5P_CIOCTRL_YCBCR_2PLANE		(1 << 3)
+#define S5P_CIOCTRL_YCBCR_PLANE_MASK		(1 << 3)
+#define S5P_CIOCTRL_ORDER2P_SHIFT		(24)
+#define S5P_CIOCTRL_ORDER2P_MASK		(3 << 24)
+#define S5P_CIOCTRL_ORDER422_2P_LSB_CRCB	(0 << 24)
+
+
+/* Main scaler control register */
+#define S5P_CISCCTRL_SCALERBYPASS		(1 << 31)
+#define S5P_CISCCTRL_SCALEUP_H			(1 << 30)
+#define S5P_CISCCTRL_SCALEUP_V			(1 << 29)
+#define S5P_CISCCTRL_CSCR2Y_NARROW		(0 << 28)
+#define S5P_CISCCTRL_CSCR2Y_WIDE		(1 << 28)
+#define S5P_CISCCTRL_CSCY2R_NARROW		(0 << 27)
+#define S5P_CISCCTRL_CSCY2R_WIDE		(1 << 27)
+#define S5P_CISCCTRL_LCDPATHEN_FIFO		(1 << 26)
+#define S5P_CISCCTRL_PROGRESSIVE		(0 << 25)
+#define S5P_CISCCTRL_INTERLACE			(1 << 25)
+#define S5P_CISCCTRL_SCALERSTART		(1 << 15)
+#define S5P_CISCCTRL_INRGB_FMT_RGB565		(0 << 13)
+#define S5P_CISCCTRL_INRGB_FMT_RGB666		(1 << 13)
+#define S5P_CISCCTRL_INRGB_FMT_RGB888		(2 << 13)
+#define S5P_CISCCTRL_INRGB_FMT_MASK		(3 << 13)
+#define S5P_CISCCTRL_OUTRGB_FMT_RGB565		(0 << 11)
+#define S5P_CISCCTRL_OUTRGB_FMT_RGB666		(1 << 11)
+#define S5P_CISCCTRL_OUTRGB_FMT_RGB888		(2 << 11)
+#define S5P_CISCCTRL_OUTRGB_FMT_MASK		(3 << 11)
+#define S5P_CISCCTRL_EXTRGB_NORMAL		(0 << 10)
+#define S5P_CISCCTRL_EXTRGB_EXTENSION		(1 << 10)
+#define S5P_CISCCTRL_ONE2ONE			(1 << 9)
+
+/* Status register */
+#define S5P_CISTATUS_OVFIY			(1 << 31)
+#define S5P_CISTATUS_OVFICB			(1 << 30)
+#define S5P_CISTATUS_OVFICR			(1 << 29)
+#define S5P_CISTATUS_VSYNC			(1 << 28)
+#define S5P_CISTATUS_WINOFSTEN			(1 << 25)
+#define S5P_CISTATUS_IMGCPTEN			(1 << 22)
+#define S5P_CISTATUS_IMGCPTENSC			(1 << 21)
+#define S5P_CISTATUS_VSYNC_A			(1 << 20)
+#define S5P_CISTATUS_VSYNC_B			(1 << 19)
+#define S5P_CISTATUS_OVRLB			(1 << 18)
+#define S5P_CISTATUS_FRAMEEND			(1 << 17)
+#define S5P_CISTATUS_LASTCAPTUREEND		(1 << 16)
+#define S5P_CISTATUS_VVALID_A			(1 << 15)
+#define S5P_CISTATUS_VVALID_B			(1 << 14)
+
+/* Image capture enable register */
+#define S5P_CIIMGCPT_IMGCPTEN			(1 << 31)
+#define S5P_CIIMGCPT_IMGCPTEN_SC		(1 << 30)
+#define S5P_CIIMGCPT_CPT_FREN_ENABLE		(1 << 25)
+#define S5P_CIIMGCPT_CPT_FRMOD_EN		(0 << 18)
+#define S5P_CIIMGCPT_CPT_FRMOD_CNT		(1 << 18)
+
+/* Image effects register */
+#define S5P_CIIMGEFF_IE_DISABLE			(0 << 30)
+#define S5P_CIIMGEFF_IE_ENABLE			(1 << 30)
+#define S5P_CIIMGEFF_IE_SC_BEFORE		(0 << 29)
+#define S5P_CIIMGEFF_IE_SC_AFTER		(1 << 29)
+#define S5P_CIIMGEFF_FIN_BYPASS			(0 << 26)
+#define S5P_CIIMGEFF_FIN_ARBITRARY		(1 << 26)
+#define S5P_CIIMGEFF_FIN_NEGATIVE		(2 << 26)
+#define S5P_CIIMGEFF_FIN_ARTFREEZE		(3 << 26)
+#define S5P_CIIMGEFF_FIN_EMBOSSING		(4 << 26)
+#define S5P_CIIMGEFF_FIN_SILHOUETTE		(5 << 26)
+#define S5P_CIIMGEFF_FIN_MASK			(7 << 26)
+#define S5P_CIIMGEFF_PAT_CBCR_MASK		((0xff < 13) | (0xff < 0))
+
+/* Real input DMA size register */
+#define S5P_CIREAL_ISIZE_AUTOLOAD_ENABLE	(1 << 31)
+#define S5P_CIREAL_ISIZE_ADDR_CH_DISABLE	(1 << 30)
+
+/* Input DMA control register */
+#define S5P_MSCTRL_IN_BURST_COUNT_MASK		(3 << 24)
+#define S5P_MSCTRL_2P_IN_ORDER_MASK		(3 << 16)
+#define S5P_MSCTRL_2P_IN_ORDER_SHIFT		(16)
+#define S5P_MSCTRL_C_INT_IN_3PLANE		(0 << 15)
+#define S5P_MSCTRL_C_INT_IN_2PLANE		(1 << 15)
+#define S5P_MSCTRL_C_INT_IN_MASK		(1 << 15)
+#define S5P_MSCTRL_FLIP_SHIFT			(13)
+#define S5P_MSCTRL_FLIP_MASK			(3 << 13)
+#define S5P_MSCTRL_FLIP_NORMAL			(0 << 13)
+#define S5P_MSCTRL_FLIP_X_MIRROR		(1 << 13)
+#define S5P_MSCTRL_FLIP_Y_MIRROR		(2 << 13)
+#define S5P_MSCTRL_FLIP_180			(3 << 13)
+#define S5P_MSCTRL_ORDER422_SHIFT		(4)
+#define S5P_MSCTRL_ORDER422_CRYCBY		(0 << 4)
+#define S5P_MSCTRL_ORDER422_YCRYCB		(1 << 4)
+#define S5P_MSCTRL_ORDER422_CBYCRY		(2 << 4)
+#define S5P_MSCTRL_ORDER422_YCBYCR		(3 << 4)
+#define S5P_MSCTRL_ORDER422_MASK		(3 << 4)
+#define S5P_MSCTRL_INPUT_EXTCAM			(0 << 3)
+#define S5P_MSCTRL_INPUT_MEMORY			(1 << 3)
+#define S5P_MSCTRL_INPUT_MASK			(1 << 3)
+#define S5P_MSCTRL_INFORMAT_YCBCR420		(0 << 1)
+#define S5P_MSCTRL_INFORMAT_YCBCR422		(1 << 1)
+#define S5P_MSCTRL_INFORMAT_YCBCR422_1PLANE	(2 << 1)
+#define S5P_MSCTRL_INFORMAT_RGB			(3 << 1)
+#define S5P_MSCTRL_INFORMAT_MASK		(3 << 1)
+#define S5P_MSCTRL_ENVID			(1 << 0)
+
+/* DMA parameter register */
+#define S5P_CIDMAPARAM_R_MODE_64X32		(3 << 29)
+#define S5P_CIDMAPARAM_W_MODE_LINEAR		(0 << 13)
+#define S5P_CIDMAPARAM_W_MODE_CONFTILE		(1 << 13)
+#define S5P_CIDMAPARAM_W_MODE_64X32		(3 << 13)
+
+#endif /* REGS_FIMC_H_ */
diff --git a/arch/arm/plat-samsung/include/plat/fimc.h b/arch/arm/plat-samsung/include/plat/fimc.h
new file mode 100644
index 0000000..bc6799e
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/fimc.h
@@ -0,0 +1,58 @@
+/* linux/arch/arm/plat-samsung/include/plat/fimc.h
+ *
+ * Platform header file for FIMC driver
+ *
+ * Copyright (c) 2010 Samsung Electronics
+ *
+ * Sylwester Nawrocki, <s.nawrocki at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef FIMC_H_
+#define FIMC_H_
+
+#include <linux/device.h>
+#include <linux/platform_device.h>
+
+#include <media/v4l2-subdev.h>
+
+struct s3c_fifo_link;
+
+extern struct platform_device s5p_device_fimc0;
+extern struct platform_device s5p_device_fimc1;
+extern struct platform_device s5p_device_fimc2;
+
+struct samsung_plat_fimc {
+/* Input and output rotator availability */
+#define S5P_FIMC_IN_ROT    (1 << 0)
+#define S5P_FIMC_OUT_ROT   (1 << 1)
+	u32             capability;
+	/* scaler input pixel size constraints */
+	u16		scaler_en_w;
+	u16		scaler_dis_w;
+	/* input rotator limits for (input) image pixel size */
+	u16		in_rot_en_h;
+	u16		in_rot_dis_w;
+	/* output rotator limits for (output) image pixel size */
+	u16		out_rot_en_w;
+	u16		out_rot_dis_w;
+	/* transfer of data in fifo mode is possible only to one framebuffer
+	   window from each fimc entity */
+#define FIMC_MAX_FIFO_TARGETS	1
+#define FIMC_LCD_FIFO_TARGET	0
+	struct s3c_fifo_link	*fifo_targets[FIMC_MAX_FIFO_TARGETS];
+};
+
+extern struct samsung_plat_fimc s5p_fimc0_default_data;
+extern struct samsung_plat_fimc s5p_fimc1_default_data;
+extern struct samsung_plat_fimc s5p_fimc2_default_data;
+
+extern void s5p_fimc0_set_platdata(struct samsung_plat_fimc *fimc);
+extern void s5p_fimc1_set_platdata(struct samsung_plat_fimc *fimc);
+extern void s5p_fimc2_set_platdata(struct samsung_plat_fimc *fimc);
+
+#endif /* FIMC_H_ */
+
-- 
1.7.0.4



From s.nawrocki at samsung.com  Wed Jun 16 06:12:02 2010
From: s.nawrocki at samsung.com (Sylwester Nawrocki)
Date: Wed, 16 Jun 2010 12:12:02 +0200
Subject: [PATCH 6/7] ARM: S5PV210: enable FIMC on Aquila
In-Reply-To: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
References: <1276683123-30224-1-git-send-email-s.nawrocki@samsung.com>
Message-ID: <1276683123-30224-7-git-send-email-s.nawrocki@samsung.com>

Add support for FIMC on Samsung Aquila board. Enable support for local
path mode between fimc and frame buffer.

Signed-off-by: Sylwester Nawrocki <s.nawrocki at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/mach-s5pv210/Kconfig       |    6 ++++
 arch/arm/mach-s5pv210/mach-aquila.c |   51 +++++++++++++++++++++++++++++++++++
 2 files changed, 57 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 7cbba86..65635ef 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -66,6 +66,12 @@ config MACH_AQUILA
 	select ARCH_SPARSEMEM_ENABLE
 	select S5PV210_SETUP_FB_24BPP
 	select S3C_DEV_FB
+	select S5P_DEV_FIMC0
+	select S5PV210_SETUP_FIMC0
+	select S5P_DEV_FIMC1
+	select S5PV210_SETUP_FIMC1
+	select S5P_DEV_FIMC2
+	select S5PV210_SETUP_FIMC2
 	help
 	  Machine support for the Samsung Aquila target based on S5PC110 SoC
 
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 10bc76e..8af0db8 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/serial_core.h>
 #include <linux/fb.h>
+#include <linux/clk.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -28,6 +29,8 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb.h>
+#include <plat/fimc.h>
+#include <plat/fifo.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
@@ -116,8 +119,44 @@ static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
 	.setup_gpio	= s5pv210_fb_gpio_setup_24bpp,
 };
 
+static void __init aquila_fimc_clk_init(void)
+{
+	int i;
+	struct clk *clk_fimc, *parent;
+	struct s5p_platform_fimc *pldata;
+
+	struct device *fimc_devs[] = {
+		&s5p_device_fimc0.dev,
+		&s5p_device_fimc1.dev,
+		&s5p_device_fimc2.dev
+	};
+
+	parent = clk_get(NULL, "mout_epll");
+	if (IS_ERR(parent))
+		return;
+
+	for (i = 0; i < ARRAY_SIZE(fimc_devs); i++) {
+		if (fimc_devs[i]) {
+			clk_fimc = clk_get(fimc_devs[i], "sclk_fimc");
+
+			if (IS_ERR(clk_fimc))
+				continue;
+
+			clk_set_parent(clk_fimc, parent);
+			pldata = fimc_devs[i]->platform_data;
+			if (pldata)
+				clk_set_rate(clk_fimc, 133000000);
+			clk_enable(clk_fimc);
+		}
+	}
+	clk_put(parent);
+}
+
 static struct platform_device *aquila_devices[] __initdata = {
 	&s3c_device_fb,
+	&s5p_device_fimc0,
+	&s5p_device_fimc1,
+	&s5p_device_fimc2,
 };
 
 static void __init aquila_map_io(void)
@@ -129,10 +168,22 @@ static void __init aquila_map_io(void)
 
 static void __init aquila_machine_init(void)
 {
+	/* FIMC */
+	s5p_fimc0_set_platdata(NULL);
+	s5p_fimc1_set_platdata(NULL);
+	s5p_fimc2_set_platdata(NULL);
+
 	/* FB */
 	s3c_fb_set_platdata(&aquila_lcd_pdata);
 
+	/* FIMC->FB fifo links */
+	s5pv210_setup_fimc0_fb_link();
+	s5pv210_setup_fimc1_fb_link();
+	s5pv210_setup_fimc2_fb_link();
+
 	platform_add_devices(aquila_devices, ARRAY_SIZE(aquila_devices));
+
+	aquila_fimc_clk_init();
 }
 
 MACHINE_START(AQUILA, "Aquila")
-- 
1.7.0.4



From mike at compulab.co.il  Wed Jun 16 06:39:03 2010
From: mike at compulab.co.il (Mike Rapoport)
Date: Wed, 16 Jun 2010 13:39:03 +0300
Subject: Request review of device tree documentation
In-Reply-To: <4C187FF0.5020806@firmworks.com>
References: <4C13430B.5000907@firmworks.com>	<1276339529.1962.184.camel@pasglop>	<1276339684.1962.186.camel@pasglop>	<4C13B618.1030006@firmworks.com>	<1276383132.1962.195.camel@pasglop>	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>	<4C146F18.9030008@firmworks.com>	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>	<20100614124438.GF9323@yookeroo>	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>	<20100614160201.GD9550@shareable.org>
	<4C165FD1.6080505@firmworks.com> <4C186AA8.4040709@compulab.co.il>
	<4C186B7B.1060308@firmworks.com> <4C186C72.2020506@compulab.co.il>
	<4C187013.5000400@firmworks.com> <4C18738C.4090809@compulab.co.il>
	<4C187FF0.5020806@firmworks.com>
Message-ID: <4C18A9C7.5070800@compulab.co.il>

Mitch Bradley wrote:
> Mike Rapoport wrote:
>> Mitch Bradley wrote:
>>> Mike Rapoport wrote:
>>>> Mitch Bradley wrote:
>>>>> Mike Rapoport wrote:
>>>>>> Mitch Bradley wrote:
>>>>>>
>>>>>>> The second topic is the hypothetical use of OFW as a HAL. That 
>>>>>>> will not happen for several reasons.  The opposition to the idea 
>>>>>>> is widespread and deeply held, and there are good arguments to 
>>>>>>> support that opposition.   Furthermore, the economic conditions 
>>>>>>> necessary for the creation of such a HAL do not exist in the ARM 
>>>>>>> world, nor indeed in the Linux world in general.  (The necessary 
>>>>>>> condition is the ability for one company to impose a substantial 
>>>>>>> change by fiat - essentially a monopoly position.)
>>>>>>>
>>>>>>> Shall we agree, then, that any further discussion of the HAL 
>>>>>>> issue is "just for fun", and that nobody needs to feel threatened 
>>>>>>> that it would actually happen?
>>>>>>
>>>>>> I've recently worked with vendor versions of U-Boot for advanced 
>>>>>> ARM SoCs. There is already *huge* chunk of HAL code in those 
>>>>>> versions. And if there would be possibility to have callbacks into 
>>>>>> the firmware these chunks would only grow, IMHO.
>>>>>
>>>>> How can there be HAL code in U-Boot unless there is already the 
>>>>> possibility to have callbacks into the firmware?
>>>>
>>>> Currently it aims to abstract hardware from U-Boot and reuse the 
>>>> same HW access code across operating systems and bootloaders. If 
>>>> this code would have callbacks I afraid the things would became worse.
>>>
>>> The only way I can understand what you said is if I assume that by 
>>> "callback", you mean the following sequence:
>>>
>>> a) U-boot loads and executes the OS, providing to the OS the address 
>>> of some HW access routines that it can use
>>> b) The OS calls one of those HW access routines
>>> c) During the execution of that HW access routine, that routine calls 
>>> "back" into the OS, before returning.  So a call into the OS is 
>>> nested inside a call into U-boot resident code.
>>>
>>> If that is what you are worried about, it is not what we were 
>>> discussing.  We were discussing - and many people were against - step 
>>> (b).
>>>
>>> Are you saying that step (b) - the OS calling into routines provided 
>>> by U-Boot - is already the status quo?
>>
>> I'm also objecting the step (b) and, fortunately, it's not yet the 
>> status quo.
>> Current U-Boot/kernel implementations I've encountered still do not 
>> have OS calls to resident HW access routines. But if such calls would 
>> be allowed, my impression is that SoC vendors would make extensive use 
>> of them.
> 
> One could argue that a feature that vendors would use extensively is one 
> that is sorely needed from their point of view.
> 
> One counterargument, of course, is that "there is a better way".  But it 
> is only "better" under a cost function that values things differently 
> than the vendors value them.  Were that not so, the vendors would gladly 
> use the "better" way and not be tempted to use the objectionable 
> feature. (Unless, of course, the vendors are just ignorant or unskilled 
> - but I generally find that different cost functions cause more 
> disconnects than lack of ability.)

It's hardly arguable that Linux community and decision makers at chip 
vendor companies use different cost functions. But it's not that obvious 
that vendors cost functions based on well established _technical_ analysis.
Many vendors try to use the same code base for several operating 
systems. From the high level perspective it sounds logical: use the same 
core functionality and thin adaptation layers to fit the core 
functionality into several OSes. But in reality, developing the OS 
abstraction layer and "thin" adaptation layers may become more expensive 
than developing each OS support from scratch. Besides, such code becomes 
a real mess after a while, and it's maintainability is very questionable.

> Which of course raises the question:  How does the Linux community view 
> such SoC vendors?  Are they embraced and eagerly supported, or (either 
> openly or secretly) viewed as a nuisance?  How does the widespread 
> objection to something that such vendors "would make extensive use of" 
> mesh with that view?

I cannot tell for the entire Linux community, but from what I know, such 
vendors are not much welcomed in the community.

>>
>>>>
>>>>> It is not HAL if it can't be called.
>>>>>
>>>>>>
>>>>>>
>>>>>>> The potential for "vendors breaking out of the debugging use case 
>>>>>>> and turning it into a HAL" is miniscule, because
>>>>>>>
>>>>>>> a) The callback is disabled by default
>>>>>>> b) The technical challenges of the callback interface limit its 
>>>>>>> applicability to specific "wizard user" scenarios
>>>>>>> c) OFW is unlikely to achieve sufficient market penetration for 
>>>>>>> the HAL thing to be worth doing
>>>>>>>
>>>>>>>
>>>>>>> _______________________________________________
>>>>>>> linux-arm-kernel mailing list
>>>>>>> linux-arm-kernel at lists.infradead.org
>>>>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>>>>
>>>>>>
>>>>
>>>>
>>
>>


-- 
Sincerely yours,
Mike.


From amit.kucheria at canonical.com  Wed Jun 16 07:08:44 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Wed, 16 Jun 2010 14:08:44 +0300
Subject: [PATCH 0/4]Refine iomux files for i.MX51
In-Reply-To: <20100616064723.GH20799@pengutronix.de>
References: <1276352559-8105-1-git-send-email-jason77.wang@gmail.com>
	<20100616064723.GH20799@pengutronix.de>
Message-ID: <20100616110844.GC3210@matterhorn.lan>

On 10 Jun 16, Sascha Hauer wrote:
> On Sat, Jun 12, 2010 at 10:22:35PM +0800, Jason Wang wrote:
> > Through the discussion, I divide my patches to 3 parts.
> > part1: mx51 iomux related part, the first patch in this part is from
> >        Amit, other patches are based off this patch and they are some
> >        fix or adding definitions for imx51_3ds board.
> 
> This is ok now. Can you please rebase onto
> git://git.pengutronix.de/git/imx/linux-2.6.git imx-for-2.6.36
> 
> The first patch conflicts with another of your patches:
> 
> e5ceef78 mx5: Add i2c to Freescale MX51 Babbage HW
> 

Please find rebased patch below.

It is only compile-tested (broken board getting updated)

Cheers,
Amit
-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria at canonical.com
----------------------------------------------------------------------



From amit.kucheria at canonical.com  Wed Jun 16 07:00:15 2010
From: amit.kucheria at canonical.com (Amit Kucheria)
Date: Wed, 16 Jun 2010 14:00:15 +0300
Subject: [PATCH] mxc: Fix pad names for imx51
Message-ID: <6af7cc9714a595111d750e097259e5c98e6512be.1276686329.git.amit.kucheria@canonical.com>

The pads capable of being used as GPIOs had their pad-name and mode-name
switched. Also, fix the following:

- Whitespace fixes
- Replace IOMUX_CONFIG_ALTn with 'n'

Signed-off-by: Amit Kucheria <amit.kucheria at canonical.com>
---
 arch/arm/mach-mx5/board-mx51_babbage.c      |    2 +-
 arch/arm/plat-mxc/include/mach/iomux-mx51.h |  553 +++++++++++++--------------
 2 files changed, 265 insertions(+), 290 deletions(-)

diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 19cde68..6e384d9 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -92,7 +92,7 @@ static struct pad_desc mx51babbage_pads[] = {
 	MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 
 	/* USB HUB reset line*/
-	MX51_PAD_GPIO_1_7__GPIO1_7,
+	MX51_PAD_GPIO_1_7__GPIO_1_7,
 };
 
 /* Serial ports */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 38961c6..a52d37e 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -27,8 +27,8 @@ typedef enum iomux_config {
 	IOMUX_CONFIG_ALT5,
 	IOMUX_CONFIG_ALT6,
 	IOMUX_CONFIG_ALT7,
-	IOMUX_CONFIG_GPIO,	/* added to help user use GPIO mode */
-	IOMUX_CONFIG_SION = 0x1 << 4,	/* LOOPBACK:MUX SION bit */
+	IOMUX_CONFIG_GPIO,      /* added to help user use GPIO mode */
+	IOMUX_CONFIG_SION = 0x1 << 4,   /* LOOPBACK:MUX SION bit */
 } iomux_pin_cfg_t;
 
 /* Pad control groupings */
@@ -38,7 +38,7 @@ typedef enum iomux_config {
 				PAD_CTL_SRE_FAST)
 #define MX51_UART3_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
 				PAD_CTL_SRE_FAST)
-#define MX51_I2C_PAD_CTRL		(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
+#define MX51_I2C_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
 				PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
 #define MX51_USBH1_PAD_CTRL	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 				PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
@@ -48,293 +48,268 @@ typedef enum iomux_config {
 
 /*
  * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named
- * GPIO_<unit>_<num> see also iomux-v3.h
+ * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
+ * See also iomux-v3.h
  */
 
-/*
- * FIXME: This was converted using scripts from existing Freescale code to
- * this form used upstream. Need to verify the name format.
- */
-
-/*						PAD      MUX   ALT INPSE PATH PADCTRL */
-
-#define MX51_PAD_EIM_D16__I2C1_SDA	IOMUX_PAD(0x3f0, 0x05c, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION, \
-					0x09b4, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO_2_1__EIM_D17	IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_2__EIM_D18	IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D19__I2C1_SCL	IOMUX_PAD(0x3fc, 0x068, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION, \
-					0x09b0, 0, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_GPIO_2_4__EIM_D20	IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_5__EIM_D21	IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D21__GPIO_2_5	IOMUX_PAD(0x404, 0x070, IOMUX_CONFIG_ALT1, 0x0,   0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_6__EIM_D22	IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_7__EIM_D23	IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
-
-/* Babbage UART3 */
-#define MX51_PAD_EIM_D24__UART3_CTS	IOMUX_PAD(0x410, 0x07c, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D25__UART3_RXD	IOMUX_PAD(0x414, 0x080, IOMUX_CONFIG_ALT3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D26__UART3_TXD	IOMUX_PAD(0x418, 0x084, IOMUX_CONFIG_ALT3, 0x0, 0, MX51_UART3_PAD_CTRL)
-#define MX51_PAD_EIM_D27__UART3_RTS	IOMUX_PAD(0x41c, 0x088, IOMUX_CONFIG_ALT3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
-
-#define MX51_PAD_EIM_D28__EIM_D28	IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D29__EIM_D29	IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D30__EIM_D30	IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_D31__EIM_D31	IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_10__EIM_A16	IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_11__EIM_A17	IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_12__EIM_A18	IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_13__EIM_A19	IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_14__EIM_A20	IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_15__EIM_A21	IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_16__EIM_A22	IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_17__EIM_A23	IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_18__EIM_A24	IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_19__EIM_A25	IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_20__EIM_A26	IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_21__EIM_A27	IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB0__EIM_EB0	IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_EB1__EIM_EB1	IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_22__EIM_EB2	IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_23__EIM_EB3	IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_2_24__EIM_OE	IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_25__EIM_CS0	IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_26__EIM_CS1	IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_27__EIM_CS2	IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_28__EIM_CS3	IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_29__EIM_CS4	IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_30__EIM_CS5	IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_2_31__EIM_DTACK	IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_GPIO_3_1__EIM_LBA	IOMUX_PAD(0x494, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__EIM_CRE	IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DRAM_CS1__DRAM_CS1	IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__NANDF_WE_B	IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__NANDF_RE_B	IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__NANDF_ALE	IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__NANDF_CLE	IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__NANDF_WP_B	IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__NANDF_RB0	IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_9__NANDF_RB1	IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_10__NANDF_RB2	IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_11__NANDF_RB3	IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__GPIO_NAND	IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL)
-/* REVISIT: Not sure of these values
-
-  #define MX51_PAD_GPIO_1___NANDF_RB4	IOMUX_PAD(, , , 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_13__NANDF_RB5	IOMUX_PAD(0x5D8, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-  #define MX51_PAD_GPIO_3_15__NANDF_RB7	IOMUX_PAD(0x5E0, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-*/
-#define MX51_PAD_GPIO_3_14__NANDF_RB6	IOMUX_PAD(0x5DC, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_16__NANDF_CS0	IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_17__NANDF_CS1	IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_18__NANDF_CS2	IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_19__NANDF_CS3	IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_20__NANDF_CS4	IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_21__NANDF_CS5	IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_22__NANDF_CS6	IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_23__NANDF_CS7	IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_24__NANDF_RDY_INT	IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_25__NANDF_D15	IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_26__NANDF_D14	IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_27__NANDF_D13	IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_28__NANDF_D12	IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_29__NANDF_D11	IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_30__NANDF_D10	IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_31__NANDF_D9	IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_0__NANDF_D8	IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_1__NANDF_D7	IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_2__NANDF_D6	IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_3__NANDF_D5	IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_4__NANDF_D4	IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_5__NANDF_D3	IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_6__NANDF_D2	IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_7__NANDF_D1	IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_8__NANDF_D0	IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_12__CSI1_D8	IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_13__CSI1_D9	IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D10__CSI1_D10	IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D11__CSI1_D11	IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D12__CSI1_D12	IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D13__CSI1_D13	IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D14__CSI1_D14	IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D15__CSI1_D15	IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D16__CSI1_D16	IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D17__CSI1_D17	IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D18__CSI1_D18	IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_D19__CSI1_D19	IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC	IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC	IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK	IOMUX_PAD(0x5B4, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_MCLK__CSI1_MCLK	IOMUX_PAD(0x5B8, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI1_PKE0__CSI1_PKE0	IOMUX_PAD(0x860, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_9__CSI2_D12	IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_10__CSI2_D13	IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D14	IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D15	IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D16	IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D17	IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_11__CSI2_D18	IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_12__CSI2_D19	IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_13__CSI2_VSYNC	IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_14__CSI2_HSYNC	IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_15__CSI2_PIXCLK	IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_CSI2_PKE0__CSI2_PKE0	IOMUX_PAD(0x81C, 0x0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_I2C1_CLK__HSI2C_CLK	IOMUX_PAD(0x5E8, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_I2C1_DAT__HSI2C_DAT	IOMUX_PAD(0x5EC, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_18__AUD3_BB_TXD	IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_19__AUD3_BB_RXD	IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_20__AUD3_BB_CK	IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_21__AUD3_BB_FS	IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_22__CSPI1_MOSI	IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_23__CSPI1_MISO	IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_24__CSPI1_SS0	IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_25__CSPI1_SS1	IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_26__CSPI1_RDY	IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_4_27__CSPI1_SCLK	IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL)
-
-/* Babbage UART1 */
-#define MX51_PAD_UART1_RXD__UART1_RXD	IOMUX_PAD(0x618, 0x228,	IOMUX_CONFIG_ALT0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_TXD__UART1_TXD	IOMUX_PAD(0x61C, 0x22C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
-#define MX51_PAD_UART1_RTS__UART1_RTS	IOMUX_PAD(0x620, 0x230, IOMUX_CONFIG_ALT0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
-#define MX51_PAD_UART1_CTS__UART1_CTS	IOMUX_PAD(0x624, 0x234, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART1_PAD_CTRL)
-
-/* Babbage UART2 */
-#define MX51_PAD_UART2_RXD__UART2_RXD	IOMUX_PAD(0x628, 0x238, IOMUX_CONFIG_ALT0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
-#define MX51_PAD_UART2_TXD__UART2_TXD	IOMUX_PAD(0x62C, 0x23C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_UART2_PAD_CTRL)
-
-#define MX51_PAD_GPIO_1_22__UART3_RXD	IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_23__UART3_TXD	IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_24__OWIRE_LINE	IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW0__KEY_ROW0	IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW1__KEY_ROW1	IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW2__KEY_ROW2	IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_ROW3__KEY_ROW3	IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL0__KEY_COL0	IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL1__KEY_COL1	IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL2__KEY_COL2	IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL3__KEY_COL3	IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_KEY_COL4__I2C2_SCL	IOMUX_PAD(0x65C, 0x26C, IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION, \
-					0x09b8, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_KEY_COL5__I2C2_SDA	IOMUX_PAD(0x660, 0x270, IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION, \
-					0x09bc, 1, MX51_I2C_PAD_CTRL)
-#define MX51_PAD_USBH1_CLK__USBH1_CLK	IOMUX_PAD(0x678, 0x278, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DIR__USBH1_DIR	IOMUX_PAD(0x67C, 0x27C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__USBH1_STP	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_STP__GPIO_1_27	IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_NXT__USBH1_NXT	IOMUX_PAD(0x684, 0x284, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA0__USBH1_DATA0	IOMUX_PAD(0x688, 0x288, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA1__USBH1_DATA1	IOMUX_PAD(0x68C, 0x28C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA2__USBH1_DATA2	IOMUX_PAD(0x690, 0x290, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA3__USBH1_DATA3	IOMUX_PAD(0x694, 0x294, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA4__USBH1_DATA4	IOMUX_PAD(0x698, 0x298, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA5__USBH1_DATA5	IOMUX_PAD(0x69C, 0x29C, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA6__USBH1_DATA6	IOMUX_PAD(0x6A0, 0x2A0, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_USBH1_DATA7__USBH1_DATA7	IOMUX_PAD(0x6A4, 0x2A4, IOMUX_CONFIG_ALT0, 0x0, 0, MX51_USBH1_PAD_CTRL)
-#define MX51_PAD_GPIO_3_0__DI1_PIN11	IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_1__DI1_PIN12	IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_2__DI1_PIN13	IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_3__DI1_D0_CS	IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_4__DI1_D1_CS	IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_5__DISPB2_SER_DIN	IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_6__DISPB2_SER_DIO	IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_7__DISPB2_SER_CLK	IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_3_8__DISPB2_SER_RS	IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT0__DISP1_DAT0	IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT1__DISP1_DAT1	IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT2__DISP1_DAT2	IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT3__DISP1_DAT3	IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT4__DISP1_DAT4	IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT5__DISP1_DAT5	IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT6__DISP1_DAT6	IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT7__DISP1_DAT7	IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT8__DISP1_DAT8	IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT9__DISP1_DAT9	IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT10__DISP1_DAT10	IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT11__DISP1_DAT11	IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT12__DISP1_DAT12	IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT13__DISP1_DAT13	IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT14__DISP1_DAT14	IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT15__DISP1_DAT15	IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT16__DISP1_DAT16	IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT17__DISP1_DAT17	IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT18__DISP1_DAT18	IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT19__DISP1_DAT19	IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT20__DISP1_DAT20	IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT21__DISP1_DAT21	IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT22__DISP1_DAT22	IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP1_DAT23__DISP1_DAT23	IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN3__DI1_PIN3	IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI1_PIN2__DI1_PIN2	IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP1__DI_GP1	IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP2__DI_GP2	IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP3__DI_GP3	IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN4__DI2_PIN4	IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN2__DI2_PIN2	IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_PIN3__DI2_PIN3	IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DI_GP4__DI_GP4	IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT0__DISP2_DAT0	IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT1__DISP2_DAT1	IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT2__DISP2_DAT2	IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT3__DISP2_DAT3	IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT4__DISP2_DAT4	IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT5__DISP2_DAT5	IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_19__DISP2_DAT6	IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_29__DISP2_DAT7	IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_30__DISP2_DAT8	IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_31__DISP2_DAT9	IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT10__DISP2_DAT10	IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT11__DISP2_DAT11	IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT12__DISP2_DAT12	IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT13__DISP2_DAT13	IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT14__DISP2_DAT14	IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_DISP2_DAT15__DISP2_DAT15	IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CMD__SD1_CMD	IOMUX_PAD(0x79C, 0x394, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_CLK__SD1_CLK	IOMUX_PAD(0x7A0, 0x398, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA0__SD1_DATA0	IOMUX_PAD(0x7A4, 0x39C, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA1__SD1_DATA1	IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA2__SD1_DATA2	IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD1_DATA3__SD1_DATA3	IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_0__GPIO1_0	IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_1__GPIO1_1	IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CMD__SD2_CMD	IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_CLK__SD2_CLK	IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA0__SD2_DATA0	IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA1__SD2_DATA1	IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA2__SD2_DATA2	IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_SD2_DATA3__SD2_DATA3	IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_2__GPIO1_2	IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_3__GPIO1_3	IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_4__GPIO1_4	IOMUX_PAD(0x804, 0x3D8, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_5__GPIO1_5	IOMUX_PAD(0x808, 0x3DC, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_6__GPIO1_6	IOMUX_PAD(0x80C, 0x3E0, 0, 0x0, 0, NO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_7__GPIO1_7	IOMUX_PAD(0x810, 0x3E4, 0, 0x0, 0, MX51_GPIO_PAD_CTRL)
-#define MX51_PAD_GPIO_1_8__GPIO1_8	IOMUX_PAD(0x814, 0x3E8, 0, 0x0, 1, \
-						(PAD_CTL_SRE_SLOW | PAD_CTL_DSE_MED | PAD_CTL_PUS_100K_UP |  PAD_CTL_HYS))
-#define MX51_PAD_GPIO_1_9__GPIO1_9	IOMUX_PAD(0x818, 0x3EC, 0, 0x0, 0, NO_PAD_CTRL)
-
-/* EIM */
-#define MX51_PAD_EIM_DA0__EIM_DA0	IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA1__EIM_DA1	IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA2__EIM_DA2	IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA3__EIM_DA3	IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA4__EIM_DA4	IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA5__EIM_DA5	IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA6__EIM_DA6	IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA7__EIM_DA7	IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
-
-#define MX51_PAD_EIM_DA8__EIM_DA8	IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA9__EIM_DA9	IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA10__EIM_DA10	IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA11__EIM_DA11	IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA12__EIM_DA12	IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA13__EIM_DA13	IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA14__EIM_DA14	IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
-#define MX51_PAD_EIM_DA15__EIM_DA15	IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+/*							  PAD    MUX   ALT INPSE PATH PADCTRL */
+#define MX51_PAD_EIM_DA0__EIM_DA0		IOMUX_PAD(0x7a8, 0x01c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA1__EIM_DA1		IOMUX_PAD(0x7a8, 0x020, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA2__EIM_DA2		IOMUX_PAD(0x7a8, 0x024, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA3__EIM_DA3		IOMUX_PAD(0x7a8, 0x028, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA4__EIM_DA4		IOMUX_PAD(0x7ac, 0x02c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA5__EIM_DA5		IOMUX_PAD(0x7ac, 0x030, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA6__EIM_DA6		IOMUX_PAD(0x7ac, 0x034, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA7__EIM_DA7		IOMUX_PAD(0x7ac, 0x038, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA8__EIM_DA8		IOMUX_PAD(0x7b0, 0x03c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA9__EIM_DA9		IOMUX_PAD(0x7b0, 0x040, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA10__EIM_DA10		IOMUX_PAD(0x7b0, 0x044, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA11__EIM_DA11		IOMUX_PAD(0x7b0, 0x048, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA12__EIM_DA12		IOMUX_PAD(0x7bc, 0x04c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA13__EIM_DA13		IOMUX_PAD(0x7bc, 0x050, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA14__EIM_DA14		IOMUX_PAD(0x7bc, 0x054, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DA15__EIM_DA15		IOMUX_PAD(0x7bc, 0x058, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__GPIO_2_0              IOMUX_PAD(0x3f0, 0x05c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D16__I2C1_SDA		IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \
+							0x09b4, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D17__GPIO_2_1              IOMUX_PAD(0x3f4, 0x060, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D18__GPIO_2_2              IOMUX_PAD(0x3f8, 0x064, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__GPIO_2_3              IOMUX_PAD(0x3fc, 0x068, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D19__I2C1_SCL		IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \
+							0x09b0, 0, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_EIM_D20__GPIO_2_4              IOMUX_PAD(0x400, 0x06c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D21__GPIO_2_5		IOMUX_PAD(0x404, 0x070, 1, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_EIM_D22__GPIO_2_6              IOMUX_PAD(0x408, 0x074, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D23__GPIO_2_7              IOMUX_PAD(0x40c, 0x078, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D24__UART3_CTS             IOMUX_PAD(0x410, 0x07c, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, 0x0,   0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D27__UART3_RTS             IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 0, MX51_UART3_PAD_CTRL)
+#define MX51_PAD_EIM_D28__EIM_D28               IOMUX_PAD(0x420, 0x08c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D29__EIM_D29               IOMUX_PAD(0x424, 0x090, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D30__EIM_D30               IOMUX_PAD(0x428, 0x094, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D31__EIM_D31               IOMUX_PAD(0x42c, 0x09c, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A16__GPIO_2_10             IOMUX_PAD(0x430, 0x09c, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A17__GPIO_2_11             IOMUX_PAD(0x434, 0x0a0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A18__GPIO_2_12             IOMUX_PAD(0x438, 0x0a4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A19__GPIO_2_13             IOMUX_PAD(0x43c, 0x0a8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A20__GPIO_2_14             IOMUX_PAD(0x440, 0x0ac, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A21__GPIO_2_15             IOMUX_PAD(0x444, 0x0b0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A22__GPIO_2_16             IOMUX_PAD(0x448, 0x0b4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A23__GPIO_2_17             IOMUX_PAD(0x44c, 0x0b8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A24__GPIO_2_18             IOMUX_PAD(0x450, 0x0bc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A25__GPIO_2_19             IOMUX_PAD(0x454, 0x0c0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A26__GPIO_2_20             IOMUX_PAD(0x458, 0x0c4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_A27__GPIO_2_21             IOMUX_PAD(0x45c, 0x0c8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB0__EIM_EB0               IOMUX_PAD(0x460, 0x0cc, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB1__EIM_EB1               IOMUX_PAD(0x464, 0x0d0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB2__GPIO_2_22             IOMUX_PAD(0x468, 0x0d4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_EB3__GPIO_2_23             IOMUX_PAD(0x46c, 0x0d8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_OE__GPIO_2_24              IOMUX_PAD(0x470, 0x0dc, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS0__GPIO_2_25             IOMUX_PAD(0x474, 0x0e0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS1__GPIO_2_26             IOMUX_PAD(0x478, 0x0e4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS2__GPIO_2_27             IOMUX_PAD(0x47c, 0x0e8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS3__GPIO_2_28             IOMUX_PAD(0x480, 0x0ec, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS4__GPIO_2_29             IOMUX_PAD(0x484, 0x0f0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CS5__GPIO_2_30             IOMUX_PAD(0x488, 0x0f4, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_DTACK__GPIO_2_31           IOMUX_PAD(0x48c, 0x0f8, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_LBA__GPIO_3_1              IOMUX_PAD(0x494, 0x0FC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_CRE__GPIO_3_2              IOMUX_PAD(0x4A0, 0x100, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4D0, 0x104, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WE_B__GPIO_3_3           IOMUX_PAD(0x4E4, 0x108, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RE_B__GPIO_3_4           IOMUX_PAD(0x4E8, 0x10C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_ALE__GPIO_3_5            IOMUX_PAD(0x4EC, 0x110, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CLE__GPIO_3_6            IOMUX_PAD(0x4F0, 0x114, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_WP_B__GPIO_3_7           IOMUX_PAD(0x4F4, 0x118, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_NAND__GPIO_3_12           IOMUX_PAD(0x514, 0x12C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS0__GPIO_3_16           IOMUX_PAD(0x518, 0x130, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS1__GPIO_3_17           IOMUX_PAD(0x51C, 0x134, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS2__GPIO_3_18           IOMUX_PAD(0x520, 0x138, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS3__GPIO_3_19           IOMUX_PAD(0x524, 0x13C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS4__GPIO_3_20           IOMUX_PAD(0x528, 0x140, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS5__GPIO_3_21           IOMUX_PAD(0x52C, 0x144, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS6__GPIO_3_22           IOMUX_PAD(0x530, 0x148, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_CS7__GPIO_3_23           IOMUX_PAD(0x534, 0x14C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D11__GPIO_3_29           IOMUX_PAD(0x54C, 0x164, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D10__GPIO_3_30           IOMUX_PAD(0x550, 0x168, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D9__GPIO_3_31            IOMUX_PAD(0x554, 0x16C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D8__GPIO_4_0             IOMUX_PAD(0x558, 0x170, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D7__GPIO_4_1             IOMUX_PAD(0x55C, 0x174, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D6__GPIO_4_2             IOMUX_PAD(0x560, 0x178, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D5__GPIO_4_3             IOMUX_PAD(0x564, 0x17C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D4__GPIO_4_4             IOMUX_PAD(0x568, 0x180, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D3__GPIO_4_5             IOMUX_PAD(0x56C, 0x184, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D2__GPIO_4_6             IOMUX_PAD(0x570, 0x188, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D1__GPIO_4_7             IOMUX_PAD(0x574, 0x18C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D0__GPIO_4_8             IOMUX_PAD(0x578, 0x190, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D8__GPIO_3_12             IOMUX_PAD(0x57C, 0x194, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D9__GPIO_3_13             IOMUX_PAD(0x580, 0x198, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D10__CSI1_D10             IOMUX_PAD(0x584, 0x19C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D11__CSI1_D11             IOMUX_PAD(0x588, 0x1A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D12__CSI1_D12             IOMUX_PAD(0x58C, 0x1A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D13__CSI1_D13             IOMUX_PAD(0x590, 0x1A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D14__CSI1_D14             IOMUX_PAD(0x594, 0x1AC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D15__CSI1_D15             IOMUX_PAD(0x598, 0x1B0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D16__CSI1_D16             IOMUX_PAD(0x59C, 0x1B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D17__CSI1_D17             IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D18__CSI1_D18             IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_D19__CSI1_D19             IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC         IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC         IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK       IOMUX_PAD(0x5B4, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_MCLK__CSI1_MCLK           IOMUX_PAD(0x5B8, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI1_PKE0__CSI1_PKE0           IOMUX_PAD(0x860, 0x000, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D12__GPIO_4_9             IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D13__GPIO_4_10            IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D14__GPIO_4_11            IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D15__GPIO_4_12            IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D16__GPIO_4_11            IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D17__GPIO_4_12            IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D18__GPIO_4_11            IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_D19__GPIO_4_12            IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_VSYNC__GPIO_4_13          IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_HSYNC__GPIO_4_14          IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15         IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__GPIO_4_16            IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_CLK__HSI2C_CLK		IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__GPIO_4_17            IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_I2C1_DAT__HSI2C_DAT		IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18         IOMUX_PAD(0x5F0, 0x200, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19         IOMUX_PAD(0x5F4, 0x204, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_CK__GPIO_4_20          IOMUX_PAD(0x5F8, 0x208, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_AUD3_BB_FS__GPIO_4_21          IOMUX_PAD(0x5FC, 0x20C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MOSI__GPIO_4_22          IOMUX_PAD(0x600, 0x210, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_MISO__GPIO_4_23          IOMUX_PAD(0x604, 0x214, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS0__GPIO_4_24           IOMUX_PAD(0x608, 0x218, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SS1__GPIO_4_25           IOMUX_PAD(0x60C, 0x21C, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_RDY__GPIO_4_26           IOMUX_PAD(0x610, 0x220, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_CSPI1_SCLK__GPIO_4_27          IOMUX_PAD(0x614, 0x224, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART1_RXD__UART1_RXD           IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_TXD__UART1_TXD           IOMUX_PAD(0x61C, 0x22C, 0, 0x0,   0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST)
+#define MX51_PAD_UART1_RTS__UART1_RTS           IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART1_CTS__UART1_CTS           IOMUX_PAD(0x624, 0x234, 0, 0x0,   0, MX51_UART1_PAD_CTRL)
+#define MX51_PAD_UART2_RXD__UART2_RXD           IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART2_TXD__UART2_TXD           IOMUX_PAD(0x62C, 0x23C, 0, 0x0,   0, MX51_UART2_PAD_CTRL)
+#define MX51_PAD_UART3_RXD__GPIO_1_22           IOMUX_PAD(0x630, 0x240, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_UART3_TXD__GPIO_1_23           IOMUX_PAD(0x634, 0x244, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_OWIRE_LINE__GPIO_1_24          IOMUX_PAD(0x638, 0x248, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW0__KEY_ROW0             IOMUX_PAD(0x63C, 0x24C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW1__KEY_ROW1             IOMUX_PAD(0x640, 0x250, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW2__KEY_ROW2             IOMUX_PAD(0x644, 0x254, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_ROW3__KEY_ROW3             IOMUX_PAD(0x648, 0x258, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL0__KEY_COL0             IOMUX_PAD(0x64C, 0x25C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL1__KEY_COL1             IOMUX_PAD(0x650, 0x260, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL2__KEY_COL2             IOMUX_PAD(0x654, 0x264, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL3__KEY_COL3             IOMUX_PAD(0x658, 0x268, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__KEY_COL4             IOMUX_PAD(0x65C, 0x26C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL4__I2C2_SCL		IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \
+							0x09b8, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__KEY_COL5             IOMUX_PAD(0x660, 0x270, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_KEY_COL5__I2C2_SDA		IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \
+							0x09bc, 1, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_USBH1_CLK__USBH1_CLK           IOMUX_PAD(0x678, 0x278, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DIR__USBH1_DIR           IOMUX_PAD(0x67C, 0x27C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__USBH1_STP           IOMUX_PAD(0x680, 0x280, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_STP__GPIO_1_27           IOMUX_PAD(0x680, 0x280, IOMUX_CONFIG_GPIO, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_NXT__USBH1_NXT           IOMUX_PAD(0x684, 0x284, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA0__USBH1_DATA0       IOMUX_PAD(0x688, 0x288, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA1__USBH1_DATA1       IOMUX_PAD(0x68C, 0x28C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA2__USBH1_DATA2       IOMUX_PAD(0x690, 0x290, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA3__USBH1_DATA3       IOMUX_PAD(0x694, 0x294, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA4__USBH1_DATA4       IOMUX_PAD(0x698, 0x298, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA5__USBH1_DATA5       IOMUX_PAD(0x69C, 0x29C, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA6__USBH1_DATA6       IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_USBH1_DATA7__USBH1_DATA7       IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0,   0, MX51_USBH1_PAD_CTRL)
+#define MX51_PAD_DI1_PIN11__GPIO_3_0            IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN12__GPIO_3_1            IOMUX_PAD(0x6AC, 0x2AC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN13__GPIO_3_2            IOMUX_PAD(0x6B0, 0x2B0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D0_CS__GPIO_3_3            IOMUX_PAD(0x6B4, 0x2B4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_D1_CS__GPIO_3_4            IOMUX_PAD(0x6B8, 0x2B8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5       IOMUX_PAD(0x6BC, 0x2BC, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6       IOMUX_PAD(0x6C0, 0x2C0, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7       IOMUX_PAD(0x6C4, 0x2C4, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8        IOMUX_PAD(0x6C8, 0x2C8, 4, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT0__DISP1_DAT0         IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT1__DISP1_DAT1         IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT2__DISP1_DAT2         IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT3__DISP1_DAT3         IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT4__DISP1_DAT4         IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT5__DISP1_DAT5         IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT6__DISP1_DAT6         IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT7__DISP1_DAT7         IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT8__DISP1_DAT8         IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT9__DISP1_DAT9         IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT10__DISP1_DAT10       IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT11__DISP1_DAT11       IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT12__DISP1_DAT12       IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT13__DISP1_DAT13       IOMUX_PAD(0x700, 0x300, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT14__DISP1_DAT14       IOMUX_PAD(0x704, 0x304, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT15__DISP1_DAT15       IOMUX_PAD(0x708, 0x308, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT16__DISP1_DAT16       IOMUX_PAD(0x70C, 0x30C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT17__DISP1_DAT17       IOMUX_PAD(0x710, 0x310, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT18__DISP1_DAT18       IOMUX_PAD(0x714, 0x314, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT19__DISP1_DAT19       IOMUX_PAD(0x718, 0x318, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT20__DISP1_DAT20       IOMUX_PAD(0x71C, 0x31C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT21__DISP1_DAT21       IOMUX_PAD(0x720, 0x320, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT22__DISP1_DAT22       IOMUX_PAD(0x724, 0x324, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP1_DAT23__DISP1_DAT23       IOMUX_PAD(0x728, 0x328, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72C, 0x32C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP1__DI_GP1                 IOMUX_PAD(0x73C, 0x334, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP2__DI_GP2                 IOMUX_PAD(0x740, 0x338, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP3__DI_GP3                 IOMUX_PAD(0x744, 0x33C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN4__DI2_PIN4             IOMUX_PAD(0x748, 0x340, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN2__DI2_PIN2             IOMUX_PAD(0x74C, 0x344, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_PIN3__DI2_PIN3             IOMUX_PAD(0x750, 0x348, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK     IOMUX_PAD(0x754, 0x34C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DI_GP4__DI_GP4                 IOMUX_PAD(0x758, 0x350, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT0__DISP2_DAT0         IOMUX_PAD(0x75C, 0x354, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT1__DISP2_DAT1         IOMUX_PAD(0x760, 0x358, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT2__DISP2_DAT2         IOMUX_PAD(0x764, 0x35C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT3__DISP2_DAT3         IOMUX_PAD(0x768, 0x360, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT4__DISP2_DAT4         IOMUX_PAD(0x76C, 0x364, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT5__DISP2_DAT5         IOMUX_PAD(0x770, 0x368, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT6__GPIO_1_19          IOMUX_PAD(0x774, 0x36C, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT7__GPIO_1_29          IOMUX_PAD(0x778, 0x370, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT8__GPIO_1_30          IOMUX_PAD(0x77C, 0x374, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT9__GPIO_1_31          IOMUX_PAD(0x780, 0x378, 5, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT10__DISP2_DAT10       IOMUX_PAD(0x784, 0x37C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT11__DISP2_DAT11       IOMUX_PAD(0x788, 0x380, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT12__DISP2_DAT12       IOMUX_PAD(0x78C, 0x384, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT13__DISP2_DAT13       IOMUX_PAD(0x790, 0x388, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT14__DISP2_DAT14       IOMUX_PAD(0x794, 0x38C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_DISP2_DAT15__DISP2_DAT15       IOMUX_PAD(0x798, 0x390, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CMD__SD1_CMD               IOMUX_PAD(0x79C, 0x394, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_CLK__SD1_CLK               IOMUX_PAD(0x7A0, 0x398, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA0__SD1_DATA0           IOMUX_PAD(0x7A4, 0x39C, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA1__SD1_DATA1           IOMUX_PAD(0x7A8, 0x3A0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA2__SD1_DATA2           IOMUX_PAD(0x7AC, 0x3A4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD1_DATA3__SD1_DATA3           IOMUX_PAD(0x7B0, 0x3A8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_0__GPIO_1_0		IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_1__GPIO_1_1		IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CMD__SD2_CMD               IOMUX_PAD(0x7BC, 0x3B4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_CLK__SD2_CLK               IOMUX_PAD(0x7C0, 0x3B8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA0__SD2_DATA0           IOMUX_PAD(0x7C4, 0x3BC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA1__SD2_DATA1           IOMUX_PAD(0x7C8, 0x3C0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA2__SD2_DATA2           IOMUX_PAD(0x7CC, 0x3C4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_SD2_DATA3__SD2_DATA3           IOMUX_PAD(0x7D0, 0x3C8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_2__GPIO_1_2		IOMUX_PAD(0x7D4, 0x3CC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_3__GPIO_1_3		IOMUX_PAD(0x7D8, 0x3D0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ	IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_4__GPIO_1_4		IOMUX_PAD(0x804, 0x3D8, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_5__GPIO_1_5		IOMUX_PAD(0x808, 0x3DC, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_6__GPIO_1_6		IOMUX_PAD(0x80C, 0x3E0, 0, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_7__GPIO_1_7		IOMUX_PAD(0x810, 0x3E4, 0, 0x0,   0, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_8__GPIO_1_8		IOMUX_PAD(0x814, 0x3E8, 0, 0x0,   1, MX51_GPIO_PAD_CTRL)
+#define MX51_PAD_GPIO_1_9__GPIO_1_9		IOMUX_PAD(0x818, 0x3EC, 0, 0x0,   0, NO_PAD_CTRL)
 
 #endif /* __MACH_IOMUX_MX51_H__ */
-- 
1.7.0.4



From jamie at shareable.org  Wed Jun 16 07:41:51 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Wed, 16 Jun 2010 12:41:51 +0100
Subject: Request review of device tree documentation
In-Reply-To: <4C18A9C7.5070800@compulab.co.il>
References: <alpine.LFD.2.00.1006141044510.13427@xanadu.home>
	<20100614160201.GD9550@shareable.org>
	<4C165FD1.6080505@firmworks.com> <4C186AA8.4040709@compulab.co.il>
	<4C186B7B.1060308@firmworks.com> <4C186C72.2020506@compulab.co.il>
	<4C187013.5000400@firmworks.com> <4C18738C.4090809@compulab.co.il>
	<4C187FF0.5020806@firmworks.com> <4C18A9C7.5070800@compulab.co.il>
Message-ID: <20100616114151.GB15054@shareable.org>

Mike Rapoport wrote:
> >Which of course raises the question:  How does the Linux community view 
> >such SoC vendors?  Are they embraced and eagerly supported, or (either 
> >openly or secretly) viewed as a nuisance?  How does the widespread 
> >objection to something that such vendors "would make extensive use of" 
> >mesh with that view?
> 
> I cannot tell for the entire Linux community, but from what I know, such 
> vendors are not much welcomed in the community.

As far as I can tell, many such vendors don't have much interest in
contributing to the Linux community either.  They use Linux code, glue
in their black-box binary modules and/or HALs, and engage poorly with
the community.  It is not just end-product makers, but upstream
component, board and SDK manufacturers too.

-- Jamie


From nicolas.ferre at atmel.com  Wed Jun 16 09:21:27 2010
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Wed, 16 Jun 2010 15:21:27 +0200
Subject: [PATCH] MAINTAINERS: some Atmel drivers change maintainer
Message-ID: <1276694487-20065-1-git-send-email-nicolas.ferre@atmel.com>

I take over the maintenance of SPI, USART, Ethernet and USB gadget drivers.
Those drivers are found in Atmel microcontrollers, both AT32/AVR32 and
AT91/ARM.

Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
Acked-by: Haavard Skinnemoen <haavard.skinnemoen at atmel.com>
---
 MAINTAINERS |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 6d119c9..5f71809 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1148,7 +1148,7 @@ F:	drivers/mmc/host/atmel-mci.c
 F:	drivers/mmc/host/atmel-mci-regs.h
 
 ATMEL AT91 / AT32 SERIAL DRIVER
-M:	Haavard Skinnemoen <hskinnemoen at atmel.com>
+M:	Nicolas Ferre <nicolas.ferre at atmel.com>
 S:	Supported
 F:	drivers/serial/atmel_serial.c
 
@@ -1160,18 +1160,18 @@ F:	drivers/video/atmel_lcdfb.c
 F:	include/video/atmel_lcdc.h
 
 ATMEL MACB ETHERNET DRIVER
-M:	Haavard Skinnemoen <hskinnemoen at atmel.com>
+M:	Nicolas Ferre <nicolas.ferre at atmel.com>
 S:	Supported
 F:	drivers/net/macb.*
 
 ATMEL SPI DRIVER
-M:	Haavard Skinnemoen <hskinnemoen at atmel.com>
+M:	Nicolas Ferre <nicolas.ferre at atmel.com>
 S:	Supported
 F:	drivers/spi/atmel_spi.*
 
 ATMEL USBA UDC DRIVER
-M:	Haavard Skinnemoen <hskinnemoen at atmel.com>
-L:	kernel at avr32linux.org
+M:	Nicolas Ferre <nicolas.ferre at atmel.com>
+L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
 W:	http://avr32linux.org/twiki/bin/view/Main/AtmelUsbDeviceDriver
 S:	Supported
 F:	drivers/usb/gadget/atmel_usba_udc.*
-- 
1.5.6.5



From will.deacon at arm.com  Wed Jun 16 08:33:22 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 16 Jun 2010 13:33:22 +0100
Subject: [PATCH] OMAP3: pmu: make CPU_HAS_PMU dependent on OMAP3_EMU
In-Reply-To: <AANLkTikIiLybBr-wV_SRWFNLkZn892gwsWHCxsIYenFJ@mail.gmail.com>
References: <1274972448-10721-1-git-send-email-will.deacon@arm.com>
	<AANLkTikIiLybBr-wV_SRWFNLkZn892gwsWHCxsIYenFJ@mail.gmail.com>
Message-ID: <000c01cb0d50$1bdc7a90$53956fb0$@deacon@arm.com>

Jean,

> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > index 1f254bd..98922f7 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -955,7 +955,8 @@ config XSCALE_PMU
> >        default y
> >
> >  config CPU_HAS_PMU
> > -       depends on CPU_V6 || CPU_V7 || XSCALE_PMU
> > +       depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
> > +                  (!ARCH_OMAP3 || OMAP3_EMU)
> >        default y
> >        bool
> >
> > --
> > 1.6.3.3
> >
> >
> 
> The patch nicely fixes the issue. Tested with Oprofile on OMAP3530
> EVM. RETention and OFF power modes succesfully tested.
> 
> Acked-by: Jean Pihet <jpihet at mvista.com>

Brilliant - thanks for testing this.
Tony: would you mind picking this patch up please or would
you prefer that I posted it to Russell's patch system?

Thanks,

Will




From kristoffer.ericson at gmail.com  Wed Jun 16 09:34:46 2010
From: kristoffer.ericson at gmail.com (Kristoffer Ericson)
Date: Wed, 16 Jun 2010 15:34:46 +0200
Subject: SSP and SA1111 misbehaving
Message-ID: <20100616133445.GA1124@boggieman>

Greetings,

Im having great difficulty deciding where the error exists, if its
inside kernel or bootloader.
What Im seeing is problems initializing hardware when using
Flashrom + U-boot + 2.6.32:
SA1111 fails to set trigger mode 3
SSP seems fine but doesnt work when trying to use it, it just times out.

Ive configured u-boot to essentially only configure memory
and standard booting policy (d-cache off, no irqs).

Grateful for any feedback/advice on this.

Best wishes
Kristoffer




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From jb at canonical.com  Wed Jun 16 09:48:07 2010
From: jb at canonical.com (Jamie Bennett)
Date: Wed, 16 Jun 2010 14:48:07 +0100
Subject: Request review of device tree documentation
In-Reply-To: <20100616114151.GB15054@shareable.org>
References: <alpine.LFD.2.00.1006141044510.13427@xanadu.home>
	<20100614160201.GD9550@shareable.org>
	<4C165FD1.6080505@firmworks.com> <4C186AA8.4040709@compulab.co.il>
	<4C186B7B.1060308@firmworks.com> <4C186C72.2020506@compulab.co.il>
	<4C187013.5000400@firmworks.com> <4C18738C.4090809@compulab.co.il>
	<4C187FF0.5020806@firmworks.com> <4C18A9C7.5070800@compulab.co.il>
	<20100616114151.GB15054@shareable.org>
Message-ID: <63BD2B99-2B94-4DA0-8489-29C1EE56E21D@canonical.com>

On 16 Jun 2010, at 12:41, Jamie Lokier wrote:
> Mike Rapoport wrote:
>>> Which of course raises the question:  How does the Linux community view 
>>> such SoC vendors?  Are they embraced and eagerly supported, or (either 
>>> openly or secretly) viewed as a nuisance?  How does the widespread 
>>> objection to something that such vendors "would make extensive use of" 
>>> mesh with that view?
>> 
>> I cannot tell for the entire Linux community, but from what I know, such 
>> vendors are not much welcomed in the community.
> 
> As far as I can tell, many such vendors don't have much interest in
> contributing to the Linux community either.  They use Linux code, glue
> in their black-box binary modules and/or HALs, and engage poorly with
> the community.  It is not just end-product makers, but upstream
> component, board and SDK manufacturers too.

That is what we are trying to change [1].

> -- Jamie

Regards,
Jamie.

[1] http://www.linaro.org



From olof at lixom.net  Wed Jun 16 10:13:06 2010
From: olof at lixom.net (Olof Johansson)
Date: Wed, 16 Jun 2010 09:13:06 -0500
Subject: [PATCH] ARM: Add ARCH_HAS_L2X0 and make CACHE_L2X0 config
	depend on that
In-Reply-To: <AANLkTimH979ASCut4dEE0FGJ-3PA3jzfHg_SzVM6eor_@mail.gmail.com>
References: <1276272211-13065-1-git-send-email-olof@lixom.net>
	<1276279087.31800.6.camel@c-dwalke-linux.qualcomm.com>
	<20100613051625.GA7248@trinity.fluff.org>
	<20100614145956.GA29355@lixom.net>
	<AANLkTimH979ASCut4dEE0FGJ-3PA3jzfHg_SzVM6eor_@mail.gmail.com>
Message-ID: <20100616141306.GA21030@lixom.net>

On Wed, Jun 16, 2010 at 11:43:29AM +0800, Eric Miao wrote:
> On Mon, Jun 14, 2010 at 10:59 PM, Olof Johansson <olof at lixom.net> wrote:
> > On Sun, Jun 13, 2010 at 06:16:26AM +0100, Ben Dooks wrote:
> >> On Fri, Jun 11, 2010 at 10:58:07AM -0700, Daniel Walker wrote:
> >> >
> >> > I made a similar change not too long ago, but Russell wanted the define
> >> > to be HAVE_CACHE_L2X0 ..
> >>
> >> possibly, I was thinking ARM_L2X0 would also be an option, since if I
> >> remeber correctly it is selecting the driver not the availability of
> >> it.
> >
> > Yeah, there are lots of different possible names. :)
> >
> > Let's just go with the one Russell preferred and not worry too much
> > about it. There's some presendence to using HAVE_.* already.
> >
> 
> Sometimes I am thinking that maybe ARCH_HAS_* has some benefits:
> 
> HAVE_* for those kernel-wide and general capabilities
> ARCH_HAS_* for those ARM machine-class specific capabilities?
> 
> So to make things a bit more clear? If ARCH_HAS_* is widely adopted
> on architectures other than ARM, maybe we can then switch that name
> to HAVE_*?

We're nowhere near depleting the HAVE_.* namespace, it's quite sparsely
used at the moment. I don't see a need to overengineer things here.

A bike shed of any color will do, etc.


-Olof


From richardcochran at gmail.com  Wed Jun 16 10:22:24 2010
From: richardcochran at gmail.com (Richard Cochran)
Date: Wed, 16 Jun 2010 16:22:24 +0200
Subject: [PATCH 08/12] ptp: Added a brand new class driver for ptp clocks.
In-Reply-To: <AANLkTin4lYghEWhjzEyARvYDgHaXdniwLbfyZ4jY0rwm@mail.gmail.com>
References: <cover.1276615626.git.richard.cochran@omicron.at>
	<4a030d2bace90f089f2f3f61496b918c6f1dfb52.1276615626.git.richard.cochran@omicron.at>
	<AANLkTin4lYghEWhjzEyARvYDgHaXdniwLbfyZ4jY0rwm@mail.gmail.com>
Message-ID: <20100616142224.GA4146@riccoc20.at.omicron.at>

On Tue, Jun 15, 2010 at 11:00:10AM -0600, Grant Likely wrote:
> 
> Question from an ignorant reviewer:  Why a new interface instead of
> working with the existing high resolution timers infrastructure?

Short answer: Timers are only one part of the PTP API. If you offer
the PTP clock as a Linux clock source, then you could just use the
existing POSIX timers. However, we decided not to offer the PTP clock
in that way. The following excerpts from an upcoming paper explain
why:

\subsection{Basic Clock Operations}

   Based on our experience with a number of commercially available
   hardware clocks, we identified a set of four basic clock
   operations. Besides simply setting or getting the clock's time
   value, two additional operations are needed for clock control.
   Once a PTP slave has an initial estimate of the offset to its
   master, it typically would need to shift the clock by the offset
   atomically.  Also, the servo loop of a slave periodically needs to
   adjust the clock frequency.

\subsection{Ancillary Clock Features}

   Perhaps the most challenging design issue was deciding how to offer
   a PTP clock's capabilities to the GNU/Linux operating system.  As
   John Eidson pointed out~\cite{eidson2006measurement}, modern
   operating systems provide surprisingly little support for
   programming based on absolute time.  As the IEEE 1588 standard is
   being applied to a wide variety of test, measurement, and control
   applications, we can imagine many possible ways to use an embedded
   computer equipped with a PTP hardware clock.  We do not expect that
   any API will be able to cover every conceivable application of this
   technology.  However, the design presented here does cover common
   use cases based on the capabilities of currently available hardware
   clocks.

   The design allows user space programs to control all of a clock's
   ancillary features.  Programs may create one-shot or periodic
   alarms, with signal delivery on expiration.  \Timestamps on
   external events are provided via a First In, First Out (FIFO)
   interface.  If the clock has output signals, then their periods are
   configurable from user space.  Synchronization of the Linux system
   time via the PPS subsystem may be enabled or disabled as desired.

\subsection{Synchronizing the Linux System Clock}

   One important question that needed to be addressed was, now that we
   have a precise time source, how do we synchronize the Linux kernel
   to it?  The Linux kernel offers a modular clock infrastructure
   comprising ``clock sources'' and ``clock event devices.'' Clock
   sources provide a monotonically increasing time base, and clock
   event devices are used to schedule the next interrupt for various
   timer events.

   We considered but ultimately rejected the idea of offering the PTP
   clock to the Linux kernel as a combined clock source and clock
   event device.  The one great advantage of this approach would have
   been that it obviates the need for synchronization when the PTP
   clock is selected as the system timer.

   However, this approach is problematic when using certain kinds of
   clock hardware. For example, physical layer (PHY) chip based clocks
   can only be accessed by the relatively slow 16 bit wide MDIO
   bus. Such a clock would not be suitable for providing high
   resolution timers, which are now a standard Linux kernel feature.
   Furthermore, we cannot even be sure that a given hardware clock
   will offer any interrupt to the system at all.

   Instead, we elected to use the Pulse Per Second (PPS) subsystem as
   a method to optionally synchronize the Linux system time to the PTP
   clock.  This method is feasible even for clocks that do not offer
   fast register access, such as the PHY clocks.  Of course, the main
   disadvantage of this approach is that the Linux system time will
   not be exactly synchronized to the PTP clock time.  Since PTP
   clocks can be synchronized an order of magnitude better than the
   typical operating system scheduling latency, we expect that this
   method will still yield acceptable results for many applications.
   Applications with more demanding time requirements may use the new
   PTP interfaces directly when needed.

\subsection{System Calls or Character Device}

   When adding new functionality to an operating system, a basic design
   decision is how user space programs will call into the kernel.  For
   the Linux kernel, two different ways come into question, namely
   system calls or as a ``character device.''  In an attempt to make
   the PTP clock API easy to understand, we patterned it after the
   existing Network Time Protocol (NTP) and the POSIX timer APIs, as
   described in Section~\ref{UserAPI}.  Both of these services are
   exported to the user space as system calls.  However, we decided to
   offer the PTP clock as a character device because extending the NTP
   and POSIX interfaces seemed impractical.  In addition, the
   character device's \fn{read()} method provides a
   convenient way to deliver time stamped events to user space
   programs.



From eric.y.miao at gmail.com  Wed Jun 16 10:22:07 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 16 Jun 2010 22:22:07 +0800
Subject: [PATCH] ARM: Add ARCH_HAS_L2X0 and make CACHE_L2X0 config depend 
	on that
In-Reply-To: <20100616141306.GA21030@lixom.net>
References: <1276272211-13065-1-git-send-email-olof@lixom.net> 
	<1276279087.31800.6.camel@c-dwalke-linux.qualcomm.com>
	<20100613051625.GA7248@trinity.fluff.org> 
	<20100614145956.GA29355@lixom.net>
	<AANLkTimH979ASCut4dEE0FGJ-3PA3jzfHg_SzVM6eor_@mail.gmail.com> 
	<20100616141306.GA21030@lixom.net>
Message-ID: <AANLkTinL44V08toDrfuOJ73Idxe77UeLHWEbZxQ4Wa_C@mail.gmail.com>

On Wed, Jun 16, 2010 at 10:13 PM, Olof Johansson <olof at lixom.net> wrote:
> On Wed, Jun 16, 2010 at 11:43:29AM +0800, Eric Miao wrote:
>> On Mon, Jun 14, 2010 at 10:59 PM, Olof Johansson <olof at lixom.net> wrote:
>> > On Sun, Jun 13, 2010 at 06:16:26AM +0100, Ben Dooks wrote:
>> >> On Fri, Jun 11, 2010 at 10:58:07AM -0700, Daniel Walker wrote:
>> >> >
>> >> > I made a similar change not too long ago, but Russell wanted the define
>> >> > to be HAVE_CACHE_L2X0 ..
>> >>
>> >> possibly, I was thinking ARM_L2X0 would also be an option, since if I
>> >> remeber correctly it is selecting the driver not the availability of
>> >> it.
>> >
>> > Yeah, there are lots of different possible names. :)
>> >
>> > Let's just go with the one Russell preferred and not worry too much
>> > about it. There's some presendence to using HAVE_.* already.
>> >
>>
>> Sometimes I am thinking that maybe ARCH_HAS_* has some benefits:
>>
>> HAVE_* for those kernel-wide and general capabilities
>> ARCH_HAS_* for those ARM machine-class specific capabilities?
>>
>> So to make things a bit more clear? If ARCH_HAS_* is widely adopted
>> on architectures other than ARM, maybe we can then switch that name
>> to HAVE_*?
>
> We're nowhere near depleting the HAVE_.* namespace, it's quite sparsely
> used at the moment.

No I'm not talking about depleting the HAVE_* , just wondering if there is a way
to make things a bit clearer.

> I don't see a need to overengineer things here.
>
> A bike shed of any color will do, etc.
>

Agreed.


From grant.likely at secretlab.ca  Wed Jun 16 11:10:42 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Wed, 16 Jun 2010 09:10:42 -0600
Subject: [PATCH 12/12] ptp: Added a clock driver for the National 
	Semiconductor PHYTER.
In-Reply-To: <20100616100539.GA3569@riccoc20.at.omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at> 
	<37f5015b186bdd51f8451ade042f90c8b39a5cc8.1276615626.git.richard.cochran@omicron.at>
	<AANLkTilqd-wxqMWDxssC-XMDJqZ8iIiSrvp2t8xARAQV@mail.gmail.com> 
	<20100616100539.GA3569@riccoc20.at.omicron.at>
Message-ID: <AANLkTilYBL6gpeg5Yp0wOmqwIo3K5YKW4mtVlE2p6jkp@mail.gmail.com>

On Wed, Jun 16, 2010 at 4:05 AM, Richard Cochran
<richardcochran at gmail.com> wrote:
> On Tue, Jun 15, 2010 at 12:49:13PM -0600, Grant Likely wrote:
>> Won't this break things for existing DP83640 users?
>
> Nope, the driver was only added five patches ago, and it only offers
> the timestamping stuff. The standard PHY functions just call the
> generic functions, so the PHY works fine even without this driver.
>
>> > +static struct ptp_clock *dp83640_clock;
>> > +DEFINE_SPINLOCK(clock_lock); /* protects the one and only dp83640_clock */
>>
>> Why only one? ?Is it not possible to have 2 of these PHYs in a system?
>
> Yes, you can have multiple PHYs, but only one PTP clock.
>
> If you do use multiple PHYs, then you must wire their clocks together
> and adjust the PTP clock on only one of the PHYs.
>
>
> Thanks for your other comments,

You're welcome.  Make sure to cc: linux-kernel on your next posting.
I commented on what I could, but there is a lot of code outside my
areas of expertise.  In particular the time keeping code needs to be
looked at by the maintainers in that area.

Cheers,
g.


From nico at fluxnic.net  Wed Jun 16 10:39:07 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 16 Jun 2010 10:39:07 -0400 (EDT)
Subject: Request review of device tree documentation
In-Reply-To: <4C18A9C7.5070800@compulab.co.il>
References: <4C13430B.5000907@firmworks.com>
	<1276339529.1962.184.camel@pasglop> <1276339684.1962.186.camel@pasglop>
	<4C13B618.1030006@firmworks.com> <1276383132.1962.195.camel@pasglop>
	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>
	<4C146F18.9030008@firmworks.com>
	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>
	<20100614124438.GF9323@yookeroo>
	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>
	<20100614160201.GD9550@shareable.org> <4C165FD1.6080505@firmworks.com>
	<4C186AA8.4040709@compulab.co.il> <4C186B7B.1060308@firmworks.com>
	<4C186C72.2020506@compulab.co.il> <4C187013.5000400@firmworks.com>
	<4C18738C.4090809@compulab.co.il> <4C187FF0.5020806@firmworks.com>
	<4C18A9C7.5070800@compulab.co.il>
Message-ID: <alpine.LFD.2.00.1006160917390.13427@xanadu.home>

On Wed, 16 Jun 2010, Mike Rapoport wrote:
> Mitch Bradley wrote:
> > One counterargument, of course, is that "there is a better way".  But it is
> > only "better" under a cost function that values things differently than the
> > vendors value them.  Were that not so, the vendors would gladly use the
> > "better" way and not be tempted to use the objectionable feature. (Unless,
> > of course, the vendors are just ignorant or unskilled - but I generally find
> > that different cost functions cause more disconnects than lack of ability.)
> 
> It's hardly arguable that Linux community and decision makers at chip vendor
> companies use different cost functions. But it's not that obvious that vendors
> cost functions based on well established _technical_ analysis.
> Many vendors try to use the same code base for several operating systems. From
> the high level perspective it sounds logical: use the same core functionality
> and thin adaptation layers to fit the core functionality into several OSes.
> But in reality, developing the OS abstraction layer and "thin" adaptation
> layers may become more expensive than developing each OS support from scratch.
> Besides, such code becomes a real mess after a while, and it's maintainability
> is very questionable.

The cost function _is_ different for the Linux community and decision 
makers at chip vendor companies. I know that for having worked long 
enough at a prominent chip vendor already.

Those vendors want to ship a product and be first on the market before 
the competitors do.  They grab a kernel tree, fit in their existing HAL 
as quickly as they can, so that they are able to demo the new chip to 
potential customers even before moving to full production.  And if the 
HAL fitting work has been done into last year's kernel already, then 
they will simply reuse that kernel to minimize the effort further as in 
theory only the HAL part needs to be swapped with the new one (doesn't 
matter if last year's kernel was itself already based on a kernel from 
the year before).  Once the software appears to work, they send it to 
customers and forget about it as they move to the next chip design.  So 
here, the cost is directly related to bring-up time, and quick (or big) 
ugly software hacks are more than a convenience but rather a necessity 
if you want to win the race.

People from the Linux community care about totally different things. The 
most important factor here is _long term_ maintainability.  It is 
important that the code be clean, use a uniform coding style, and follow 
common interfaces.  This is so because the cost function here is 
directly related to the difficulty for the Linux community to evolve the 
kernel with generic improvements and new features.  If each driver has a 
different style, or rely on a different HAL, then it quickly becomes 
extremely expensive to update those drivers along with the generic 
improvements.  And if the HAL is in binary form only, or stuck behind 
some unalterable BIOS-like calls or firmware API, then it may even be 
impossible to update those drivers as the execution context assumed by 
the HAL firmware may not be guaranteed anymore (think about UP vs SMP, 
different preemption modes, different realtime kernel modes, etc.)  And 
of course it is impossible to anticipate what execution context and 
requirements the kernel might need in the future, hence this can't be 
provisioned for (and much less validated) into the HAL design in advance 
(and see above why it is next to hopeless to expect vendors to update 
their HAL for old products in a timely fashion).

So there *is* indeed a big difference between both points of view.  And 
sometimes the imperatives from each group are in total conflict.

> > Which of course raises the question:  How does the Linux community view such
> > SoC vendors?  Are they embraced and eagerly supported, or (either openly or
> > secretly) viewed as a nuisance?  How does the widespread objection to
> > something that such vendors "would make extensive use of" mesh with that
> > view?
> 
> I cannot tell for the entire Linux community, but from what I know, such
> vendors are not much welcomed in the community.

And the reverse is also true: those vendors are not amenable to more 
openness and early community involvement which could help them get to 
market with "community acceptable" support for their products due to 
NDAs and such, or simply because of the perception that the Linux 
community is putting too much value on "expendable software".  It is way 
too common to hear from hardware designers that "software is cheap"... 
which is not quite the case in the end.  That's a real pity.


Nicolas


From jdzheng at broadcom.com  Wed Jun 16 12:49:24 2010
From: jdzheng at broadcom.com (JD (Jiandong) Zheng)
Date: Wed, 16 Jun 2010 09:49:24 -0700
Subject: [PATCH] MAINTAINERS: Change BCMRING maintainer
In-Reply-To: <AANLkTilI2toj42vZcHzPC4ru82CDMf2UWsTasPyOD3Nh@mail.gmail.com>
References: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E3F7@SJEXCHCCR02.corp.ad.broadcom.com>
	<AANLkTil6o6tHQdDM0YQRgxme3VLVuk8HUOzqscxsBQBi@mail.gmail.com>
	<1276655981.1586.172.camel@Joe-Laptop.home>
	<AANLkTilI2toj42vZcHzPC4ru82CDMf2UWsTasPyOD3Nh@mail.gmail.com>
Message-ID: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E57D@SJEXCHCCR02.corp.ad.broadcom.com>

Hi Eric and Joe,

It is true that I didn't contribute to kernel directly using my company's email address. My company wants to have an engineer to be the contact point and submit patch for BCMRING code and as Leo is not longer with our company I took over this responsibility from him so that any BCMRING maintenance issue or question will be directed to me firstly in Broadcom.

I'd say I am new as a *direct* kernel contributor and I have a lot to learn. I understand I need to show some credits by submitting patches, etc. and I will.

Thanks,
JD

-----Original Message-----
From: Eric Miao [mailto:eric.y.miao at gmail.com] 
Sent: Tuesday, June 15, 2010 7:58 PM
To: Joe Perches
Cc: JD (Jiandong) Zheng; linux-arm-kernel at lists.infradead.org
Subject: Re: [PATCH] MAINTAINERS: Change BCMRING maintainer

On Wed, Jun 16, 2010 at 10:39 AM, Joe Perches <joe at perches.com> wrote:
> On Wed, 2010-06-16 at 10:17 +0800, Eric Miao wrote:
>> On Wed, Jun 16, 2010 at 4:42 AM, JD (Jiandong) Zheng
>> <jdzheng at broadcom.com> wrote:
>> > I am Jiandong Zheng working on BCMRING in Broadcom Canada Ltd.
>> > I am replacing Leo Chen (leochen at broadcom.com) as
>> > "ARM/BCMRING ARM ARCHITECTURE" and "ARM/BCMRING MTD NAND DRIVER"
>> > ?maintainer.
>> > Signed-off-by: Jiandong Zheng <jdzheng at broadcom.com>
>> Search your email address in linux-2.6 tree, no result found. This is
>> community, not a company. Maintainer is not assigned. Show us some
>> credits please?
>
> I think you're going overboard Eric.
> You'll find several company addresses, some with names, in MAINTAINERS.

Well, I'm not against a company address at all, I myself am employed and
use company address very often. And I really welcome some one to come up
and take the responsibility of some orphaned code. But the first impression
of this, to me, it's more like a Broadcom internal policy to assign someone
or not (maybe some work transition of Leo Chen). And I haven't seen much
contribution from JD so far, honestly, (but doesn't mean I don't believe
he's going to contribute a lot).

Sorry, JD, I was a bit rude on this and this is not personal at all. Nice to
know you actually, bcmring was not actively maintained since last year.
I hope we can know more about you.

>
> for instance:
> $ grep M:.*support MAINTAINERS
> M: ? ? ?support at lsi.com
> M: ? ? ?Vincent Sanders <support at simtec.co.uk>
> M: ? ? ?Vincent Sanders <support at simtec.co.uk>
> M: ? ? ?Matthias Bruestle and Harald Welte <support at reiner-sct.com>
> M: ? ? ?Support Department <support at connecttech.com>
>
> Some others:
> M: ? ? ?STEricsson <STEricsson_nomadik_linux at list.st.com>
> M: ? ? ?"Digi International, Inc" <Eng.Linux at digi.com>
> M: ? ? ?HighPoint Linux Team <linux at highpoint-tech.com>
> M: ? ? ?Intel Linux Wireless <ilw at linux.intel.com>
> M: ? ? ?linux-wimax at intel.com
> M: ? ? ?linux390 at de.ibm.com
> M: ? ? ?linux-driver at qlogic.com
> M: ? ? ?Solarflare linux maintainers <linux-net-drivers at solarflare.com>
> M: ? ? ?davinci-linux-open-source at linux.davincidsp.com
>
> Would you prefer that broadcom go the way of intel with the
> ipw2x00 or just have a faceless "linux-support at broadcom.com"?
>
> Not me.
>
> Welcome JD.
>
>
>


From PeterHuewe at gmx.de  Wed Jun 16 13:32:00 2010
From: PeterHuewe at gmx.de (Peter Huewe)
Date: Wed, 16 Jun 2010 19:32:00 +0200
Subject: [PATCH] arm/include: Fix missing semicolon in module.h
Message-ID: <201006161932.00542.PeterHuewe@gmx.de>

From: Peter Huewe <peterhuewe at gmx.de>

This patch fixes a missing semicolon which introduced buildfailures [2] for
almost every arm defconfig, introduced by patch cecaa4c6b [1]

This issue arises only if CONFIG_ARM_UNWIND is not set.

Signed-off-by: Peter Huewe <peterhuewe at gmx.de>
---
KernelVersion: linux-next-20100616
References:
[1] cecaa4c6b ARM: 6172/1: module - additional unwind tables for exit/devexit
[2] http://kisskb.ellerman.id.au/kisskb/compiler/11/
[3] http://kisskb.ellerman.id.au/kisskb/buildresult/2725882/

 arch/arm/include/asm/module.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
index fcff0d2..cbb0bc2 100644
--- a/arch/arm/include/asm/module.h
+++ b/arch/arm/include/asm/module.h
@@ -26,7 +26,7 @@ struct mod_arch_specific {
 };
 #else
 struct mod_arch_specific {
-}
+};
 #endif
 
 /*
-- 
1.6.4.4



From tim.bird at am.sony.com  Wed Jun 16 13:43:44 2010
From: tim.bird at am.sony.com (Tim Bird)
Date: Wed, 16 Jun 2010 10:43:44 -0700
Subject: Request review of device tree documentation
In-Reply-To: <alpine.LFD.2.00.1006160917390.13427@xanadu.home>
References: <4C13430B.5000907@firmworks.com>	<1276339529.1962.184.camel@pasglop>
	<1276339684.1962.186.camel@pasglop>	<4C13B618.1030006@firmworks.com>
	<1276383132.1962.195.camel@pasglop>	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>	<4C146F18.9030008@firmworks.com>	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>	<20100614124438.GF9323@yookeroo>	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>	<20100614160201.GD9550@shareable.org>
	<4C165FD1.6080505@firmworks.com>	<4C186AA8.4040709@compulab.co.il>
	<4C186B7B.1060308@firmworks.com>	<4C186C72.2020506@compulab.co.il>
	<4C187013.5000400@firmworks.com>	<4C18738C.4090809@compulab.co.il>
	<4C187FF0.5020806@firmworks.com>	<4C18A9C7.5070800@compulab.co.il>
	<alpine.LFD.2.00.1006160917390.13427@xanadu.home>
Message-ID: <4C190D50.2010501@am.sony.com>

On 06/16/2010 07:39 AM, Nicolas Pitre wrote:
> The cost function _is_ different for the Linux community and decision 
> makers at chip vendor companies. I know that for having worked long 
> enough at a prominent chip vendor already.
> 
> Those vendors want to ship a product and be first on the market before 
> the competitors do.  They grab a kernel tree, fit in their existing HAL 
> as quickly as they can, so that they are able to demo the new chip to 
> potential customers even before moving to full production.  And if the 
> HAL fitting work has been done into last year's kernel already, then 
> they will simply reuse that kernel to minimize the effort further as in 
> theory only the HAL part needs to be swapped with the new one (doesn't 
> matter if last year's kernel was itself already based on a kernel from 
> the year before).  Once the software appears to work, they send it to 
> customers and forget about it as they move to the next chip design.  So 
> here, the cost is directly related to bring-up time, and quick (or big) 
> ugly software hacks are more than a convenience but rather a necessity 
> if you want to win the race.
> 
> People from the Linux community care about totally different things. The 
> most important factor here is _long term_ maintainability.  It is 
> important that the code be clean, use a uniform coding style, and follow 
> common interfaces.  This is so because the cost function here is 
> directly related to the difficulty for the Linux community to evolve the 
> kernel with generic improvements and new features.  If each driver has a 
> different style, or rely on a different HAL, then it quickly becomes 
> extremely expensive to update those drivers along with the generic 
> improvements.  And if the HAL is in binary form only, or stuck behind 
> some unalterable BIOS-like calls or firmware API, then it may even be 
> impossible to update those drivers as the execution context assumed by 
> the HAL firmware may not be guaranteed anymore (think about UP vs SMP, 
> different preemption modes, different realtime kernel modes, etc.)  And 
> of course it is impossible to anticipate what execution context and 
> requirements the kernel might need in the future, hence this can't be 
> provisioned for (and much less validated) into the HAL design in advance 
> (and see above why it is next to hopeless to expect vendors to update 
> their HAL for old products in a timely fashion).
> 
> So there *is* indeed a big difference between both points of view.  And 
> sometimes the imperatives from each group are in total conflict.

This is absolutely correct.  At the CE Linux Forum, we've been working
for years to try to get vendors more involved in the community, with
a variety of techniques, including white papers for management,
magazine articles, outreach at industry events, and hosting our
own events to introduce "industry" and "community" developers.

It is not uncommon for vendors to throw the software away (or big
chunks of it) for each release, which is completely contrary
to the goals of mainline developers.  I once had a product line
where each year for 3 years, the product team used a different
processor ARCHITECTURE.  Stuff like that significantly impairs
the argument that they'll see big wins from mainlining things.

>>> Which of course raises the question:  How does the Linux community view such
>>> SoC vendors?  Are they embraced and eagerly supported,

No.  Mostly, they get chastised and told how wrong they are,
so they just stay away.   Any work they have done is often thrown
under the bus by people who refuse to acknowledge their requirements.
(Witness the suspend blockers thread on linux-pm).

>>> or (either openly or
>>> secretly) viewed as a nuisance?  How does the widespread objection to
>>> something that such vendors "would make extensive use of" mesh with that
>>> view?
>>
>> I cannot tell for the entire Linux community, but from what I know, such
>> vendors are not much welcomed in the community.
> 
> And the reverse is also true: those vendors are not amenable to more 
> openness and early community involvement which could help them get to 
> market with "community acceptable" support for their products due to 
> NDAs and such, or simply because of the perception that the Linux 
> community is putting too much value on "expendable software".  It is way 
> too common to hear from hardware designers that "software is cheap"... 
> which is not quite the case in the end.  That's a real pity.

Also true.  Nicolas - you're on a roll today. :-)
 -- Tim

=============================
Tim Bird
Architecture Group Chair, CE Linux Forum
Senior Staff Engineer, Sony Network Entertainment
=============================



From hjk at linutronix.de  Wed Jun 16 15:05:38 2010
From: hjk at linutronix.de (Hans J. Koch)
Date: Wed, 16 Jun 2010 21:05:38 +0200
Subject: [PATCH 2/7 v6] Add the clock framework for Telechips TCC8xxx
	processors.
In-Reply-To: <20100526174846.GE2006@bluebox.local>
References: <20100526174240.GC2006@bluebox.local>
	<20100526174846.GE2006@bluebox.local>
Message-ID: <20100616190536.GB2010@bluebox.local>

The previous implementation contains a rather confusing handling of
(struct clk)->root_id, adding and subtracting 1 all the time. This
is a clearer version of the patch for adding the clock framework for
Telechips TCC8xxx processors.

Signed-off-by: "Hans J. Koch" <hjk at linutronix.de>
---
 arch/arm/mach-tcc8k/Makefile                |    6 +
 arch/arm/mach-tcc8k/clock.c                 |  571 +++++++++++++++++++++++++++
 arch/arm/plat-tcc/Makefile                  |    2 +-
 arch/arm/plat-tcc/clock.c                   |  180 +++++++++
 arch/arm/plat-tcc/include/mach/clkdev.h     |    7 +
 arch/arm/plat-tcc/include/mach/clock.h      |   48 +++
 arch/arm/plat-tcc/include/mach/tcc8k-regs.h |   31 +-
 7 files changed, 834 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/mach-tcc8k/Makefile
 create mode 100644 arch/arm/mach-tcc8k/clock.c
 create mode 100644 arch/arm/plat-tcc/clock.c
 create mode 100644 arch/arm/plat-tcc/include/mach/clkdev.h
 create mode 100644 arch/arm/plat-tcc/include/mach/clock.h

diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile
new file mode 100644
index 0000000..805d850
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for TCC8K boards and common files.
+#
+
+# Common support
+obj-y += clock.o
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
new file mode 100644
index 0000000..9b95ee3
--- /dev/null
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -0,0 +1,571 @@
+/*
+ * Lowlevel clock handling for Telechips TCC8xxx SoCs
+ *
+ * Copyright (C) 2010 by Hans J. Koch <hjk at linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/irqs.h>
+#include <mach/tcc8k-regs.h>
+
+extern int __init tcc8k_timer_init(struct clk *clock,
+					void __iomem *base, int irq);
+
+#define BCLKCTR0	(CKC_BASE + BCLKCTR0_OFFS)
+#define BCLKCTR1	(CKC_BASE + BCLKCTR1_OFFS)
+
+#define ACLKREF		(CKC_BASE + ACLKREF_OFFS)
+#define ACLKUART0	(CKC_BASE + ACLKUART0_OFFS)
+#define ACLKUART1	(CKC_BASE + ACLKUART1_OFFS)
+#define ACLKUART2	(CKC_BASE + ACLKUART2_OFFS)
+#define ACLKUART3	(CKC_BASE + ACLKUART3_OFFS)
+#define ACLKUART4	(CKC_BASE + ACLKUART4_OFFS)
+#define ACLKI2C		(CKC_BASE + ACLKI2C_OFFS)
+#define ACLKADC		(CKC_BASE + ACLKADC_OFFS)
+#define ACLKUSBH	(CKC_BASE + ACLKUSBH_OFFS)
+#define ACLKLCD		(CKC_BASE + ACLKLCD_OFFS)
+#define ACLKSDH0	(CKC_BASE + ACLKSDH0_OFFS)
+#define ACLKSDH1	(CKC_BASE + ACLKSDH1_OFFS)
+#define ACLKSPI0	(CKC_BASE + ACLKSPI0_OFFS)
+#define ACLKSPI1	(CKC_BASE + ACLKSPI1_OFFS)
+#define ACLKSPDIF	(CKC_BASE + ACLKSPDIF_OFFS)
+#define ACLKC3DEC	(CKC_BASE + ACLKC3DEC_OFFS)
+#define ACLKCAN0	(CKC_BASE + ACLKCAN0_OFFS)
+#define ACLKCAN1	(CKC_BASE + ACLKCAN1_OFFS)
+#define ACLKGSB0	(CKC_BASE + ACLKGSB0_OFFS)
+#define ACLKGSB1	(CKC_BASE + ACLKGSB1_OFFS)
+#define ACLKGSB2	(CKC_BASE + ACLKGSB2_OFFS)
+#define ACLKGSB3	(CKC_BASE + ACLKGSB3_OFFS)
+#define ACLKUSBH	(CKC_BASE + ACLKUSBH_OFFS)
+#define ACLKTCT		(CKC_BASE + ACLKTCT_OFFS)
+#define ACLKTCX		(CKC_BASE + ACLKTCX_OFFS)
+#define ACLKTCZ		(CKC_BASE + ACLKTCZ_OFFS)
+
+/* Crystal frequencies */
+static unsigned long xi_rate, xti_rate;
+
+static int index_of_root_clk(struct clk *clock);
+
+static void __iomem *pll_cfg_addr(int pll)
+{
+	switch (pll) {
+	case 0: return (CKC_BASE + PLL0CFG_OFFS);
+	case 1: return (CKC_BASE + PLL1CFG_OFFS);
+	case 2: return (CKC_BASE + PLL2CFG_OFFS);
+	default:
+		BUG();
+	}
+}
+
+static int pll_enable(int pll, int enable)
+{
+	u32 reg;
+	void __iomem *addr = pll_cfg_addr(pll);
+
+	reg = __raw_readl(addr);
+	if (enable)
+		reg &= ~PLLxCFG_PD;
+	else
+		reg |= PLLxCFG_PD;
+
+	__raw_writel(reg, addr);
+	return 0;
+}
+
+static int xi_enable(int enable)
+{
+	u32 reg;
+
+	reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
+	if (enable)
+		reg |= CLKCTRL_XE;
+	else
+		reg &= ~CLKCTRL_XE;
+
+	__raw_writel(reg, CKC_BASE + CLKCTRL_OFFS);
+	return 0;
+}
+
+static int root_clk_enable(enum root_clks src)
+{
+	switch (src) {
+	case CLK_SRC_PLL0: return pll_enable(0, 1);
+	case CLK_SRC_PLL1: return pll_enable(1, 1);
+	case CLK_SRC_PLL2: return pll_enable(2, 1);
+	case CLK_SRC_XI: return xi_enable(1);
+	default:
+		BUG();
+	}
+	return 0;
+}
+
+static int root_clk_disable(enum root_clks root_src)
+{
+	switch (root_src) {
+	case CLK_SRC_PLL0: return pll_enable(0, 0);
+	case CLK_SRC_PLL1: return pll_enable(1, 0);
+	case CLK_SRC_PLL2: return pll_enable(2, 0);
+	case CLK_SRC_XI: return xi_enable(0);
+	default:
+		BUG();
+	}
+	return 0;
+}
+
+static int enable_clk(struct clk *clk)
+{
+	u32 reg;
+
+	if (clk->root_id != CLK_SRC_NOROOT)
+		return root_clk_enable(clk->root_id);
+
+	if (clk->aclkreg) {
+		reg = __raw_readl(clk->aclkreg);
+		reg |= ACLK_EN;
+		__raw_writel(reg, clk->aclkreg);
+	}
+	if (clk->bclkctr) {
+		reg = __raw_readl(clk->bclkctr);
+		reg |= 1 << clk->bclk_shift;
+		__raw_writel(reg, clk->bclkctr);
+	}
+	return 0;
+}
+
+static void disable_clk(struct clk *clk)
+{
+	u32 reg;
+
+	if (clk->root_id != CLK_SRC_NOROOT) {
+		root_clk_disable(clk->root_id);
+		return;
+	}
+
+	if (clk->bclkctr) {
+		reg = __raw_readl(clk->bclkctr);
+		reg &= ~(1 << clk->bclk_shift);
+		__raw_writel(reg, clk->bclkctr);
+	}
+	if (clk->aclkreg) {
+		reg = __raw_readl(clk->aclkreg);
+		reg &= ~ACLK_EN;
+		__raw_writel(reg, clk->aclkreg);
+	}
+}
+
+static unsigned long get_rate_pll(int pll)
+{
+	u32 reg;
+	unsigned long s, m, p;
+	void __iomem *addr = pll_cfg_addr(pll);
+
+	reg = __raw_readl(addr);
+	s = (reg >> 16) & 0x07;
+	m = (reg >> 8) & 0xff;
+	p = reg & 0x3f;
+
+	return (m * xi_rate) / (p * (1 << s));
+}
+
+static unsigned long get_rate_pll_div(int pll)
+{
+	u32 reg;
+	unsigned long div = 0;
+	void __iomem *addr;
+
+	switch (pll) {
+	case 0:
+		addr = CKC_BASE + CLKDIVC0_OFFS;
+		reg = __raw_readl(addr);
+		if (reg & CLKDIVC0_P0E)
+			div = (reg >> 24) & 0x3f;
+		break;
+	case 1:
+		addr = CKC_BASE + CLKDIVC0_OFFS;
+		reg = __raw_readl(addr);
+		if (reg & CLKDIVC0_P1E)
+			div = (reg >> 16) & 0x3f;
+		break;
+	case 2:
+		addr = CKC_BASE + CLKDIVC1_OFFS;
+		reg = __raw_readl(addr);
+		if (reg & CLKDIVC1_P2E)
+			div = __raw_readl(addr) & 0x3f;
+		break;
+	}
+	return get_rate_pll(pll) / (div + 1);
+}
+
+static unsigned long get_rate_xi_div(void)
+{
+	unsigned long div = 0;
+	u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
+
+	if (reg & CLKDIVC0_XE)
+		div = (reg >> 8) & 0x3f;
+
+	return xi_rate / (div + 1);
+}
+
+static unsigned long get_rate_xti_div(void)
+{
+	unsigned long div = 0;
+	u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
+
+	if (reg & CLKDIVC0_XTE)
+		div = reg & 0x3f;
+
+	return xti_rate / (div + 1);
+}
+
+static unsigned long root_clk_get_rate(enum root_clks src)
+{
+	switch (src) {
+	case CLK_SRC_PLL0: return get_rate_pll(0);
+	case CLK_SRC_PLL1: return get_rate_pll(1);
+	case CLK_SRC_PLL2: return get_rate_pll(2);
+	case CLK_SRC_PLL0DIV: return get_rate_pll_div(0);
+	case CLK_SRC_PLL1DIV: return get_rate_pll_div(1);
+	case CLK_SRC_PLL2DIV: return get_rate_pll_div(2);
+	case CLK_SRC_XI: return xi_rate;
+	case CLK_SRC_XTI: return xti_rate;
+	case CLK_SRC_XIDIV: return get_rate_xi_div();
+	case CLK_SRC_XTIDIV: return get_rate_xti_div();
+	default: return 0;
+	}
+}
+
+static unsigned long aclk_get_rate(struct clk *clk)
+{
+	u32 reg;
+	unsigned long div;
+	unsigned int src;
+
+	reg = __raw_readl(clk->aclkreg);
+	div = reg & 0x0fff;
+	src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK;
+	return root_clk_get_rate(src) / (div + 1);
+}
+
+static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
+{
+	unsigned long div, src, freq, r1, r2;
+
+	src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+	src &= CLK_SRC_MASK;
+	freq = root_clk_get_rate(src);
+	div = freq / rate + 1;
+	r1 = freq / div;
+	r2 = freq / (div + 1);
+	if (r2 >= rate)
+		return div + 1;
+	if ((rate - r2) < (r1 - rate))
+		return div + 1;
+
+	return div;
+}
+
+static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int src;
+
+	src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+	src &= CLK_SRC_MASK;
+
+	return root_clk_get_rate(src) / aclk_best_div(clk, rate);
+}
+
+static int aclk_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg;
+
+	reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
+	reg |= aclk_best_div(clk, rate);
+	return 0;
+}
+
+static unsigned long get_rate_sys(struct clk *clk)
+{
+	unsigned int src;
+
+	src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
+		return root_clk_get_rate(src);
+}
+
+static unsigned long get_rate_bus(struct clk *clk)
+{
+	unsigned int div;
+
+	div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
+	return get_rate_sys(clk) / (div + 1);
+}
+
+static unsigned long get_rate_cpu(struct clk *clk)
+{
+	unsigned int reg, div, fsys, fbus;
+
+	fbus = get_rate_bus(clk);
+	reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
+	if (reg & (1 << 29))
+		return fbus;
+	fsys = get_rate_sys(clk);
+	div = (reg >> 16) & 0x0f;
+	return fbus + ((fsys - fbus) * (div + 1)) / 16;
+}
+
+static unsigned long get_rate_root(struct clk *clk)
+{
+	return root_clk_get_rate(clk->root_id);
+}
+
+static int aclk_set_parent(struct clk *clock, struct clk *parent)
+{
+	u32 reg;
+
+	if (clock->parent == parent)
+		return 0;
+
+	clock->parent = parent;
+
+	if (!parent)
+		return 0;
+
+	if (parent->root_id == CLK_SRC_NOROOT)
+		return 0;
+	reg = __raw_readl(clock->aclkreg);
+	reg &= ~ACLK_SEL_MASK;
+	reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK;
+	__raw_writel(reg, clock->aclkreg);
+
+	return 0;
+}
+
+#define DEFINE_ROOT_CLOCK(name, ri, p)	\
+	static struct clk name = {		\
+		.root_id = ri,			\
+		.get_rate = get_rate_root,			\
+		.enable = enable_clk,		\
+		.disable = disable_clk,		\
+		.parent = p,			\
+	};
+
+#define DEFINE_SPECIAL_CLOCK(name, gr, p)	\
+	static struct clk name = {		\
+		.root_id = CLK_SRC_NOROOT,	\
+		.get_rate = gr,			\
+		.parent = p,			\
+	};
+
+#define DEFINE_ACLOCK(name, bc, bs, ar)		\
+	static struct clk name = {		\
+		.root_id = CLK_SRC_NOROOT,	\
+		.bclkctr = bc,			\
+		.bclk_shift = bs,		\
+		.aclkreg = ar,			\
+		.get_rate = aclk_get_rate,	\
+		.set_rate = aclk_set_rate,	\
+		.round_rate = aclk_round_rate,	\
+		.enable = enable_clk,		\
+		.disable = disable_clk,		\
+		.set_parent = aclk_set_parent,	\
+	};
+
+#define DEFINE_BCLOCK(name, bc, bs, gr, p)	\
+	static struct clk name = {		\
+		.root_id = CLK_SRC_NOROOT,	\
+		.bclkctr = bc,			\
+		.bclk_shift = bs,		\
+		.get_rate = gr,			\
+		.enable = enable_clk,		\
+		.disable = disable_clk,		\
+		.parent = p,			\
+	};
+
+DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL)
+DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL)
+DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi)
+DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti)
+DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi)
+DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi)
+DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi)
+DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0)
+DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1)
+DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2)
+
+/* The following 3 clocks are special and are initialized explicitly later */
+DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL)
+DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys)
+DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys)
+
+DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT)
+DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX)
+DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ)
+DEFINE_ACLOCK(ref, NULL, 0, ACLKREF)
+DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0)
+DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1)
+DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2)
+DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3)
+DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4)
+DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C)
+DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC)
+DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH)
+DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD)
+DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0)
+DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1)
+DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0)
+DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1)
+DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF)
+DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC)
+DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0)
+DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1)
+DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0)
+DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1)
+DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2)
+DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3)
+DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH)
+
+DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL)
+DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL)
+DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL)
+DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL)
+DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL)
+DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL)
+DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL)
+DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL)
+DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL)
+DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL)
+DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL)
+DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL)
+DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL)
+DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL)
+DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL)
+DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL)
+DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL)
+DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL)
+DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL)
+DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL)
+DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL)
+DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL)
+
+#define _REGISTER_CLOCK(d, n, c) \
+	{ \
+		.dev_id = d, \
+		.con_id = n, \
+		.clk = &c, \
+	},
+
+static struct clk_lookup lookups[] = {
+	_REGISTER_CLOCK(NULL, "bus", bus)
+	_REGISTER_CLOCK(NULL, "cpu", cpu)
+	_REGISTER_CLOCK(NULL, "tct", tct)
+	_REGISTER_CLOCK(NULL, "tcx", tcx)
+	_REGISTER_CLOCK(NULL, "tcz", tcz)
+	_REGISTER_CLOCK(NULL, "ref", ref)
+	_REGISTER_CLOCK(NULL, "dai0", dai0)
+	_REGISTER_CLOCK(NULL, "pic", pic)
+	_REGISTER_CLOCK(NULL, "tc", tc)
+	_REGISTER_CLOCK(NULL, "gpio", gpio)
+	_REGISTER_CLOCK(NULL, "usbd", usbd)
+	_REGISTER_CLOCK("tcc-uart.0", NULL, uart0)
+	_REGISTER_CLOCK("tcc-uart.2", NULL, uart2)
+	_REGISTER_CLOCK("tcc-i2c", NULL, i2c)
+	_REGISTER_CLOCK("tcc-uart.3", NULL, uart3)
+	_REGISTER_CLOCK(NULL, "ecc", ecc)
+	_REGISTER_CLOCK(NULL, "adc", adc)
+	_REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0)
+	_REGISTER_CLOCK(NULL, "gdma0", gdma0)
+	_REGISTER_CLOCK(NULL, "lcd", lcd)
+	_REGISTER_CLOCK(NULL, "rtc", rtc)
+	_REGISTER_CLOCK(NULL, "nfc", nfc)
+	_REGISTER_CLOCK("tcc-mmc.0", NULL, sd0)
+	_REGISTER_CLOCK(NULL, "g2d", g2d)
+	_REGISTER_CLOCK(NULL, "gdma1", gdma1)
+	_REGISTER_CLOCK("tcc-uart.1", NULL, uart1)
+	_REGISTER_CLOCK("tcc-spi.0", NULL, spi0)
+	_REGISTER_CLOCK(NULL, "mscl", mscl)
+	_REGISTER_CLOCK("tcc-spi.1", NULL, spi1)
+	_REGISTER_CLOCK(NULL, "bdma", bdma)
+	_REGISTER_CLOCK(NULL, "adma0", adma0)
+	_REGISTER_CLOCK(NULL, "spdif", spdif)
+	_REGISTER_CLOCK(NULL, "scfg", scfg)
+	_REGISTER_CLOCK(NULL, "cid", cid)
+	_REGISTER_CLOCK("tcc-mmc.1", NULL, sd1)
+	_REGISTER_CLOCK("tcc-uart.4", NULL, uart4)
+	_REGISTER_CLOCK(NULL, "dai1", dai1)
+	_REGISTER_CLOCK(NULL, "adma1", adma1)
+	_REGISTER_CLOCK(NULL, "c3dec", c3dec)
+	_REGISTER_CLOCK("tcc-can.0", NULL, can0)
+	_REGISTER_CLOCK("tcc-can.1", NULL, can1)
+	_REGISTER_CLOCK(NULL, "gps", gps)
+	_REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0)
+	_REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1)
+	_REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2)
+	_REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3)
+	_REGISTER_CLOCK(NULL, "gdma2", gdma2)
+	_REGISTER_CLOCK(NULL, "gdma3", gdma3)
+	_REGISTER_CLOCK(NULL, "ddrc", ddrc)
+	_REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1)
+};
+
+static struct clk *root_clk_by_index(enum root_clks src)
+{
+	switch (src) {
+	case CLK_SRC_PLL0: return &pll0;
+	case CLK_SRC_PLL1: return &pll1;
+	case CLK_SRC_PLL2: return &pll2;
+	case CLK_SRC_PLL0DIV: return &pll0div;
+	case CLK_SRC_PLL1DIV: return &pll1div;
+	case CLK_SRC_PLL2DIV: return &pll2div;
+	case CLK_SRC_XI: return &xi;
+	case CLK_SRC_XTI: return &xti;
+	case CLK_SRC_XIDIV: return &xidiv;
+	case CLK_SRC_XTIDIV: return &xtidiv;
+	default: return NULL;
+	}
+}
+
+static void find_aclk_parent(struct clk *clk)
+{
+	unsigned int src;
+	struct clk *clock;
+
+	if (!clk->aclkreg)
+		return;
+
+	src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+	src &= CLK_SRC_MASK;
+
+	clock = root_clk_by_index(src);
+	if (!clock)
+		return;
+
+	clk->parent = clock;
+	clk->set_parent = aclk_set_parent;
+}
+
+int __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq)
+{
+	int i;
+
+	xi_rate = xi_freq;
+	xti_rate = xti_freq;
+
+	/* fixup parents and add the clock */
+	for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+		find_aclk_parent(lookups[i].clk);
+		clkdev_add(&lookups[i]);
+	}
+
+	return tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32);
+}
diff --git a/arch/arm/plat-tcc/Makefile b/arch/arm/plat-tcc/Makefile
index 3f2e4fe..eceabc8 100644
--- a/arch/arm/plat-tcc/Makefile
+++ b/arch/arm/plat-tcc/Makefile
@@ -1,3 +1,3 @@
 # "Telechips Platform Common Modules"
 
-obj-y := system.o
+obj-y := clock.o system.o
diff --git a/arch/arm/plat-tcc/clock.c b/arch/arm/plat-tcc/clock.c
new file mode 100644
index 0000000..31b3ee8
--- /dev/null
+++ b/arch/arm/plat-tcc/clock.c
@@ -0,0 +1,180 @@
+/*
+ * Clock framework for Telechips SoCs
+ * Based on arch/arm/plat-mxc/clock.c
+ *
+ * Copyright (C) 2004 - 2005 Nokia corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen at elektrobit.com>
+ * Modified for omap shared clock framework by Tony Lindgren <tony at atomide.com>
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel at pengutronix.de
+ * Copyright 2010 Hans J. Koch, hjk at linutronix.de
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/string.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+
+static DEFINE_MUTEX(clocks_mutex);
+
+/*-------------------------------------------------------------------------
+ * Standard clock functions defined in include/linux/clk.h
+ *-------------------------------------------------------------------------*/
+
+static void __clk_disable(struct clk *clk)
+{
+	BUG_ON(clk->refcount == 0);
+
+	if (!(--clk->refcount) && clk->disable) {
+		/* Unconditionally disable the clock in hardware */
+		clk->disable(clk);
+		/* recursively disable parents */
+		if (clk->parent)
+			__clk_disable(clk->parent);
+	}
+}
+
+static int __clk_enable(struct clk *clk)
+{
+	int ret = 0;
+
+	if (clk->refcount++ == 0 && clk->enable) {
+		if (clk->parent)
+			ret = __clk_enable(clk->parent);
+		if (ret)
+			return ret;
+		else
+			return clk->enable(clk);
+	}
+
+	return 0;
+}
+
+/* This function increments the reference count on the clock and enables the
+ * clock if not already enabled. The parent clock tree is recursively enabled
+ */
+int clk_enable(struct clk *clk)
+{
+	int ret = 0;
+
+	if (!clk)
+		return -EINVAL;
+
+	mutex_lock(&clocks_mutex);
+	ret = __clk_enable(clk);
+	mutex_unlock(&clocks_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+/* This function decrements the reference count on the clock and disables
+ * the clock when reference count is 0. The parent clock tree is
+ * recursively disabled
+ */
+void clk_disable(struct clk *clk)
+{
+	if (!clk)
+		return;
+
+	mutex_lock(&clocks_mutex);
+	__clk_disable(clk);
+	mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+/* Retrieve the *current* clock rate. If the clock itself
+ * does not provide a special calculation routine, ask
+ * its parent and so on, until one is able to return
+ * a valid clock rate
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+	if (!clk)
+		return 0UL;
+
+	if (clk->get_rate)
+		return clk->get_rate(clk);
+
+	return clk_get_rate(clk->parent);
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+/* Round the requested clock rate to the nearest supported
+ * rate that is less than or equal to the requested rate.
+ * This is dependent on the clock's current parent.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	if (!clk)
+		return 0;
+	if (!clk->round_rate)
+		return 0;
+
+	return clk->round_rate(clk, rate);
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+/* Set the clock to the requested clock rate. The rate must
+ * match a supported rate exactly based on what clk_round_rate returns
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	int ret = -EINVAL;
+
+	if (!clk)
+		return ret;
+	if (!clk->set_rate || !rate)
+		return ret;
+
+	mutex_lock(&clocks_mutex);
+	ret = clk->set_rate(clk, rate);
+	mutex_unlock(&clocks_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+/* Set the clock's parent to another clock source */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct clk *old;
+	int ret = -EINVAL;
+
+	if (!clk)
+		return ret;
+	if (!clk->set_parent || !parent)
+		return ret;
+
+	mutex_lock(&clocks_mutex);
+	old = clk->parent;
+	if (clk->refcount)
+		__clk_enable(parent);
+	ret = clk->set_parent(clk, parent);
+	if (ret)
+		old = parent;
+	if (clk->refcount)
+		__clk_disable(old);
+	mutex_unlock(&clocks_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+/* Retrieve the clock's parent clock source */
+struct clk *clk_get_parent(struct clk *clk)
+{
+	if (!clk)
+		return NULL;
+
+	return clk->parent;
+}
+EXPORT_SYMBOL_GPL(clk_get_parent);
+
diff --git a/arch/arm/plat-tcc/include/mach/clkdev.h b/arch/arm/plat-tcc/include/mach/clkdev.h
new file mode 100644
index 0000000..04b37a8
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/clock.h b/arch/arm/plat-tcc/include/mach/clock.h
new file mode 100644
index 0000000..a12f58a
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clock.h
@@ -0,0 +1,48 @@
+/*
+ * Low level clock header file for Telechips TCC architecture
+ * (C) 2010 Hans J. Koch <hjk at linutronix.de>
+ *
+ * Licensed under the GPL v2.
+ */
+
+#ifndef __ASM_ARCH_TCC_CLOCK_H__
+#define __ASM_ARCH_TCC_CLOCK_H__
+
+#ifndef __ASSEMBLY__
+
+struct clk {
+	struct clk *parent;
+	/* id number of a root clock, 0 for normal clocks */
+	int root_id;
+	/* Reference count of clock enable/disable */
+	int refcount;
+	/* Address of associated BCLKCTRx register. Must be set. */
+	void __iomem *bclkctr;
+	/* Bit position for BCLKCTRx. Must be set. */
+	int bclk_shift;
+	/* Address of ACLKxxx register, if any. */
+	void __iomem *aclkreg;
+	/* get the current clock rate (always a fresh value) */
+	unsigned long (*get_rate) (struct clk *);
+	/* Function ptr to set the clock to a new rate. The rate must match a
+	   supported rate returned from round_rate. Leave blank if clock is not
+	   programmable */
+	int (*set_rate) (struct clk *, unsigned long);
+	/* Function ptr to round the requested clock rate to the nearest
+	   supported rate that is less than or equal to the requested rate. */
+	unsigned long (*round_rate) (struct clk *, unsigned long);
+	/* Function ptr to enable the clock. Leave blank if clock can not
+	   be gated. */
+	int (*enable) (struct clk *);
+	/* Function ptr to disable the clock. Leave blank if clock can not
+	   be gated. */
+	void (*disable) (struct clk *);
+	/* Function ptr to set the parent clock of the clock. */
+	int (*set_parent) (struct clk *, struct clk *);
+};
+
+int clk_register(struct clk *clk);
+void clk_unregister(struct clk *clk);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
index f3243eb..1786867 100644
--- a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
+++ b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
@@ -30,13 +30,13 @@
 #define EXT_MEM_CTRL_BASE	0xf0000000
 #define EXT_MEM_CTRL_SIZE	SZ_4K
 
-#define CS1_BASE_VIRT		0xf7000000
-#define AHB_PERI_BASE_VIRT	0xf4000000
-#define APB0_PERI_BASE_VIRT	0xf1000000
-#define APB1_PERI_BASE_VIRT	0xf2000000
-#define EXT_MEM_CTRL_BASE_VIRT	0xf3000000
-#define INT_SRAM_BASE_VIRT	0xf5000000
-#define DATA_TCM_BASE_VIRT	0xf6000000
+#define CS1_BASE_VIRT		(void __iomem *)0xf7000000
+#define AHB_PERI_BASE_VIRT	(void __iomem *)0xf4000000
+#define APB0_PERI_BASE_VIRT	(void __iomem *)0xf1000000
+#define APB1_PERI_BASE_VIRT	(void __iomem *)0xf2000000
+#define EXT_MEM_CTRL_BASE_VIRT	(void __iomem *)0xf3000000
+#define INT_SRAM_BASE_VIRT	(void __iomem *)0xf5000000
+#define DATA_TCM_BASE_VIRT	(void __iomem *)0xf6000000
 
 #define __REG(x)     (*((volatile u32 *)(x)))
 
@@ -649,8 +649,7 @@
 #define PMGPIO_APB_OFFS		0x800
 
 /* Clock controller registers */
-#define CKC_BASE		(APB1_PERI_BASE_VIRT + 0x6000)
-#define CKC_BASE_PHYS		(APB1_PERI_BASE + 0x6000)
+#define CKC_BASE	((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000))
 
 #define CLKCTRL_OFFS		0x00
 #define PLL0CFG_OFFS		0x04
@@ -724,8 +723,20 @@
 /* SWRESET1 bits */
 #define SWRESET1_USBH1		(1 << 20)
 
-/* System clock sources */
+/* System clock sources. 
+ * Note: These are the clock sources that serve as parents for
+ * all other clocks. They have no parents themselves.
+ *
+ * These values are used for struct clk->root_id. All clocks
+ * that are not system clock sources have this value set to
+ * CLK_SRC_NOROOT. 
+ * The values for system clocks start with CLK_SRC_PLL0 == 0
+ * because this gives us exactly the values needed for the lower
+ * 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is
+ * defined as -1 to not disturb the order.
+ */
 enum root_clks {
+	CLK_SRC_NOROOT = -1,
 	CLK_SRC_PLL0 = 0,
 	CLK_SRC_PLL1,
 	CLK_SRC_PLL0DIV,
-- 
1.6.3.3



From hjk at linutronix.de  Wed Jun 16 16:18:05 2010
From: hjk at linutronix.de (Hans J. Koch)
Date: Wed, 16 Jun 2010 22:18:05 +0200
Subject: [PATCH 2/7 v6] Add the clock framework for Telechips TCC8xxx
	processors.
In-Reply-To: <20100616190536.GB2010@bluebox.local>
References: <20100526174240.GC2006@bluebox.local>
	<20100526174846.GE2006@bluebox.local>
	<20100616190536.GB2010@bluebox.local>
Message-ID: <20100616201804.GA2550@local>

(The last patch had one unneeded forward declaration left over and produced a
compiler warning, here's the correct version.)

This adds definitions and low-level functions to handle clocks in
TCC8xxx processors.

Signed-off-by: "Hans J. Koch" <hjk at linutronix.de>
---
 arch/arm/mach-tcc8k/Makefile                |    6 +
 arch/arm/mach-tcc8k/clock.c                 |  571 +++++++++++++++++++++++++++
 arch/arm/plat-tcc/Makefile                  |    2 +-
 arch/arm/plat-tcc/clock.c                   |  180 +++++++++
 arch/arm/plat-tcc/include/mach/clkdev.h     |    7 +
 arch/arm/plat-tcc/include/mach/clock.h      |   48 +++
 arch/arm/plat-tcc/include/mach/tcc8k-regs.h |   31 +-
 7 files changed, 834 insertions(+), 11 deletions(-)
 create mode 100644 arch/arm/mach-tcc8k/Makefile
 create mode 100644 arch/arm/mach-tcc8k/clock.c
 create mode 100644 arch/arm/plat-tcc/clock.c
 create mode 100644 arch/arm/plat-tcc/include/mach/clkdev.h
 create mode 100644 arch/arm/plat-tcc/include/mach/clock.h

diff --git a/arch/arm/mach-tcc8k/Makefile b/arch/arm/mach-tcc8k/Makefile
new file mode 100644
index 0000000..805d850
--- /dev/null
+++ b/arch/arm/mach-tcc8k/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for TCC8K boards and common files.
+#
+
+# Common support
+obj-y += clock.o
diff --git a/arch/arm/mach-tcc8k/clock.c b/arch/arm/mach-tcc8k/clock.c
new file mode 100644
index 0000000..9b95ee3
--- /dev/null
+++ b/arch/arm/mach-tcc8k/clock.c
@@ -0,0 +1,571 @@
+/*
+ * Lowlevel clock handling for Telechips TCC8xxx SoCs
+ *
+ * Copyright (C) 2010 by Hans J. Koch <hjk at linutronix.de>
+ *
+ * Licensed under the terms of the GPL v2
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/irqs.h>
+#include <mach/tcc8k-regs.h>
+
+extern int __init tcc8k_timer_init(struct clk *clock,
+					void __iomem *base, int irq);
+
+#define BCLKCTR0	(CKC_BASE + BCLKCTR0_OFFS)
+#define BCLKCTR1	(CKC_BASE + BCLKCTR1_OFFS)
+
+#define ACLKREF		(CKC_BASE + ACLKREF_OFFS)
+#define ACLKUART0	(CKC_BASE + ACLKUART0_OFFS)
+#define ACLKUART1	(CKC_BASE + ACLKUART1_OFFS)
+#define ACLKUART2	(CKC_BASE + ACLKUART2_OFFS)
+#define ACLKUART3	(CKC_BASE + ACLKUART3_OFFS)
+#define ACLKUART4	(CKC_BASE + ACLKUART4_OFFS)
+#define ACLKI2C		(CKC_BASE + ACLKI2C_OFFS)
+#define ACLKADC		(CKC_BASE + ACLKADC_OFFS)
+#define ACLKUSBH	(CKC_BASE + ACLKUSBH_OFFS)
+#define ACLKLCD		(CKC_BASE + ACLKLCD_OFFS)
+#define ACLKSDH0	(CKC_BASE + ACLKSDH0_OFFS)
+#define ACLKSDH1	(CKC_BASE + ACLKSDH1_OFFS)
+#define ACLKSPI0	(CKC_BASE + ACLKSPI0_OFFS)
+#define ACLKSPI1	(CKC_BASE + ACLKSPI1_OFFS)
+#define ACLKSPDIF	(CKC_BASE + ACLKSPDIF_OFFS)
+#define ACLKC3DEC	(CKC_BASE + ACLKC3DEC_OFFS)
+#define ACLKCAN0	(CKC_BASE + ACLKCAN0_OFFS)
+#define ACLKCAN1	(CKC_BASE + ACLKCAN1_OFFS)
+#define ACLKGSB0	(CKC_BASE + ACLKGSB0_OFFS)
+#define ACLKGSB1	(CKC_BASE + ACLKGSB1_OFFS)
+#define ACLKGSB2	(CKC_BASE + ACLKGSB2_OFFS)
+#define ACLKGSB3	(CKC_BASE + ACLKGSB3_OFFS)
+#define ACLKUSBH	(CKC_BASE + ACLKUSBH_OFFS)
+#define ACLKTCT		(CKC_BASE + ACLKTCT_OFFS)
+#define ACLKTCX		(CKC_BASE + ACLKTCX_OFFS)
+#define ACLKTCZ		(CKC_BASE + ACLKTCZ_OFFS)
+
+/* Crystal frequencies */
+static unsigned long xi_rate, xti_rate;
+
+static int index_of_root_clk(struct clk *clock);
+
+static void __iomem *pll_cfg_addr(int pll)
+{
+	switch (pll) {
+	case 0: return (CKC_BASE + PLL0CFG_OFFS);
+	case 1: return (CKC_BASE + PLL1CFG_OFFS);
+	case 2: return (CKC_BASE + PLL2CFG_OFFS);
+	default:
+		BUG();
+	}
+}
+
+static int pll_enable(int pll, int enable)
+{
+	u32 reg;
+	void __iomem *addr = pll_cfg_addr(pll);
+
+	reg = __raw_readl(addr);
+	if (enable)
+		reg &= ~PLLxCFG_PD;
+	else
+		reg |= PLLxCFG_PD;
+
+	__raw_writel(reg, addr);
+	return 0;
+}
+
+static int xi_enable(int enable)
+{
+	u32 reg;
+
+	reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
+	if (enable)
+		reg |= CLKCTRL_XE;
+	else
+		reg &= ~CLKCTRL_XE;
+
+	__raw_writel(reg, CKC_BASE + CLKCTRL_OFFS);
+	return 0;
+}
+
+static int root_clk_enable(enum root_clks src)
+{
+	switch (src) {
+	case CLK_SRC_PLL0: return pll_enable(0, 1);
+	case CLK_SRC_PLL1: return pll_enable(1, 1);
+	case CLK_SRC_PLL2: return pll_enable(2, 1);
+	case CLK_SRC_XI: return xi_enable(1);
+	default:
+		BUG();
+	}
+	return 0;
+}
+
+static int root_clk_disable(enum root_clks root_src)
+{
+	switch (root_src) {
+	case CLK_SRC_PLL0: return pll_enable(0, 0);
+	case CLK_SRC_PLL1: return pll_enable(1, 0);
+	case CLK_SRC_PLL2: return pll_enable(2, 0);
+	case CLK_SRC_XI: return xi_enable(0);
+	default:
+		BUG();
+	}
+	return 0;
+}
+
+static int enable_clk(struct clk *clk)
+{
+	u32 reg;
+
+	if (clk->root_id != CLK_SRC_NOROOT)
+		return root_clk_enable(clk->root_id);
+
+	if (clk->aclkreg) {
+		reg = __raw_readl(clk->aclkreg);
+		reg |= ACLK_EN;
+		__raw_writel(reg, clk->aclkreg);
+	}
+	if (clk->bclkctr) {
+		reg = __raw_readl(clk->bclkctr);
+		reg |= 1 << clk->bclk_shift;
+		__raw_writel(reg, clk->bclkctr);
+	}
+	return 0;
+}
+
+static void disable_clk(struct clk *clk)
+{
+	u32 reg;
+
+	if (clk->root_id != CLK_SRC_NOROOT) {
+		root_clk_disable(clk->root_id);
+		return;
+	}
+
+	if (clk->bclkctr) {
+		reg = __raw_readl(clk->bclkctr);
+		reg &= ~(1 << clk->bclk_shift);
+		__raw_writel(reg, clk->bclkctr);
+	}
+	if (clk->aclkreg) {
+		reg = __raw_readl(clk->aclkreg);
+		reg &= ~ACLK_EN;
+		__raw_writel(reg, clk->aclkreg);
+	}
+}
+
+static unsigned long get_rate_pll(int pll)
+{
+	u32 reg;
+	unsigned long s, m, p;
+	void __iomem *addr = pll_cfg_addr(pll);
+
+	reg = __raw_readl(addr);
+	s = (reg >> 16) & 0x07;
+	m = (reg >> 8) & 0xff;
+	p = reg & 0x3f;
+
+	return (m * xi_rate) / (p * (1 << s));
+}
+
+static unsigned long get_rate_pll_div(int pll)
+{
+	u32 reg;
+	unsigned long div = 0;
+	void __iomem *addr;
+
+	switch (pll) {
+	case 0:
+		addr = CKC_BASE + CLKDIVC0_OFFS;
+		reg = __raw_readl(addr);
+		if (reg & CLKDIVC0_P0E)
+			div = (reg >> 24) & 0x3f;
+		break;
+	case 1:
+		addr = CKC_BASE + CLKDIVC0_OFFS;
+		reg = __raw_readl(addr);
+		if (reg & CLKDIVC0_P1E)
+			div = (reg >> 16) & 0x3f;
+		break;
+	case 2:
+		addr = CKC_BASE + CLKDIVC1_OFFS;
+		reg = __raw_readl(addr);
+		if (reg & CLKDIVC1_P2E)
+			div = __raw_readl(addr) & 0x3f;
+		break;
+	}
+	return get_rate_pll(pll) / (div + 1);
+}
+
+static unsigned long get_rate_xi_div(void)
+{
+	unsigned long div = 0;
+	u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
+
+	if (reg & CLKDIVC0_XE)
+		div = (reg >> 8) & 0x3f;
+
+	return xi_rate / (div + 1);
+}
+
+static unsigned long get_rate_xti_div(void)
+{
+	unsigned long div = 0;
+	u32 reg = __raw_readl(CKC_BASE + CLKDIVC0_OFFS);
+
+	if (reg & CLKDIVC0_XTE)
+		div = reg & 0x3f;
+
+	return xti_rate / (div + 1);
+}
+
+static unsigned long root_clk_get_rate(enum root_clks src)
+{
+	switch (src) {
+	case CLK_SRC_PLL0: return get_rate_pll(0);
+	case CLK_SRC_PLL1: return get_rate_pll(1);
+	case CLK_SRC_PLL2: return get_rate_pll(2);
+	case CLK_SRC_PLL0DIV: return get_rate_pll_div(0);
+	case CLK_SRC_PLL1DIV: return get_rate_pll_div(1);
+	case CLK_SRC_PLL2DIV: return get_rate_pll_div(2);
+	case CLK_SRC_XI: return xi_rate;
+	case CLK_SRC_XTI: return xti_rate;
+	case CLK_SRC_XIDIV: return get_rate_xi_div();
+	case CLK_SRC_XTIDIV: return get_rate_xti_div();
+	default: return 0;
+	}
+}
+
+static unsigned long aclk_get_rate(struct clk *clk)
+{
+	u32 reg;
+	unsigned long div;
+	unsigned int src;
+
+	reg = __raw_readl(clk->aclkreg);
+	div = reg & 0x0fff;
+	src = (reg >> ACLK_SEL_SHIFT) & CLK_SRC_MASK;
+	return root_clk_get_rate(src) / (div + 1);
+}
+
+static unsigned long aclk_best_div(struct clk *clk, unsigned long rate)
+{
+	unsigned long div, src, freq, r1, r2;
+
+	src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+	src &= CLK_SRC_MASK;
+	freq = root_clk_get_rate(src);
+	div = freq / rate + 1;
+	r1 = freq / div;
+	r2 = freq / (div + 1);
+	if (r2 >= rate)
+		return div + 1;
+	if ((rate - r2) < (r1 - rate))
+		return div + 1;
+
+	return div;
+}
+
+static unsigned long aclk_round_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int src;
+
+	src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+	src &= CLK_SRC_MASK;
+
+	return root_clk_get_rate(src) / aclk_best_div(clk, rate);
+}
+
+static int aclk_set_rate(struct clk *clk, unsigned long rate)
+{
+	u32 reg;
+
+	reg = __raw_readl(clk->aclkreg) & ~ACLK_DIV_MASK;
+	reg |= aclk_best_div(clk, rate);
+	return 0;
+}
+
+static unsigned long get_rate_sys(struct clk *clk)
+{
+	unsigned int src;
+
+	src = __raw_readl(CKC_BASE + CLKCTRL_OFFS) & CLK_SRC_MASK;
+		return root_clk_get_rate(src);
+}
+
+static unsigned long get_rate_bus(struct clk *clk)
+{
+	unsigned int div;
+
+	div = (__raw_readl(CKC_BASE + CLKCTRL_OFFS) >> 4) & 0xff;
+	return get_rate_sys(clk) / (div + 1);
+}
+
+static unsigned long get_rate_cpu(struct clk *clk)
+{
+	unsigned int reg, div, fsys, fbus;
+
+	fbus = get_rate_bus(clk);
+	reg = __raw_readl(CKC_BASE + CLKCTRL_OFFS);
+	if (reg & (1 << 29))
+		return fbus;
+	fsys = get_rate_sys(clk);
+	div = (reg >> 16) & 0x0f;
+	return fbus + ((fsys - fbus) * (div + 1)) / 16;
+}
+
+static unsigned long get_rate_root(struct clk *clk)
+{
+	return root_clk_get_rate(clk->root_id);
+}
+
+static int aclk_set_parent(struct clk *clock, struct clk *parent)
+{
+	u32 reg;
+
+	if (clock->parent == parent)
+		return 0;
+
+	clock->parent = parent;
+
+	if (!parent)
+		return 0;
+
+	if (parent->root_id == CLK_SRC_NOROOT)
+		return 0;
+	reg = __raw_readl(clock->aclkreg);
+	reg &= ~ACLK_SEL_MASK;
+	reg |= (parent->root_id << ACLK_SEL_SHIFT) & ACLK_SEL_MASK;
+	__raw_writel(reg, clock->aclkreg);
+
+	return 0;
+}
+
+#define DEFINE_ROOT_CLOCK(name, ri, p)	\
+	static struct clk name = {		\
+		.root_id = ri,			\
+		.get_rate = get_rate_root,			\
+		.enable = enable_clk,		\
+		.disable = disable_clk,		\
+		.parent = p,			\
+	};
+
+#define DEFINE_SPECIAL_CLOCK(name, gr, p)	\
+	static struct clk name = {		\
+		.root_id = CLK_SRC_NOROOT,	\
+		.get_rate = gr,			\
+		.parent = p,			\
+	};
+
+#define DEFINE_ACLOCK(name, bc, bs, ar)		\
+	static struct clk name = {		\
+		.root_id = CLK_SRC_NOROOT,	\
+		.bclkctr = bc,			\
+		.bclk_shift = bs,		\
+		.aclkreg = ar,			\
+		.get_rate = aclk_get_rate,	\
+		.set_rate = aclk_set_rate,	\
+		.round_rate = aclk_round_rate,	\
+		.enable = enable_clk,		\
+		.disable = disable_clk,		\
+		.set_parent = aclk_set_parent,	\
+	};
+
+#define DEFINE_BCLOCK(name, bc, bs, gr, p)	\
+	static struct clk name = {		\
+		.root_id = CLK_SRC_NOROOT,	\
+		.bclkctr = bc,			\
+		.bclk_shift = bs,		\
+		.get_rate = gr,			\
+		.enable = enable_clk,		\
+		.disable = disable_clk,		\
+		.parent = p,			\
+	};
+
+DEFINE_ROOT_CLOCK(xi, CLK_SRC_XI, NULL)
+DEFINE_ROOT_CLOCK(xti, CLK_SRC_XTI, NULL)
+DEFINE_ROOT_CLOCK(xidiv, CLK_SRC_XIDIV, &xi)
+DEFINE_ROOT_CLOCK(xtidiv, CLK_SRC_XTIDIV, &xti)
+DEFINE_ROOT_CLOCK(pll0, CLK_SRC_PLL0, &xi)
+DEFINE_ROOT_CLOCK(pll1, CLK_SRC_PLL1, &xi)
+DEFINE_ROOT_CLOCK(pll2, CLK_SRC_PLL2, &xi)
+DEFINE_ROOT_CLOCK(pll0div, CLK_SRC_PLL0DIV, &pll0)
+DEFINE_ROOT_CLOCK(pll1div, CLK_SRC_PLL1DIV, &pll1)
+DEFINE_ROOT_CLOCK(pll2div, CLK_SRC_PLL2DIV, &pll2)
+
+/* The following 3 clocks are special and are initialized explicitly later */
+DEFINE_SPECIAL_CLOCK(sys, get_rate_sys, NULL)
+DEFINE_SPECIAL_CLOCK(bus, get_rate_bus, &sys)
+DEFINE_SPECIAL_CLOCK(cpu, get_rate_cpu, &sys)
+
+DEFINE_ACLOCK(tct, NULL, 0, ACLKTCT)
+DEFINE_ACLOCK(tcx, NULL, 0, ACLKTCX)
+DEFINE_ACLOCK(tcz, NULL, 0, ACLKTCZ)
+DEFINE_ACLOCK(ref, NULL, 0, ACLKREF)
+DEFINE_ACLOCK(uart0, BCLKCTR0, 5, ACLKUART0)
+DEFINE_ACLOCK(uart1, BCLKCTR0, 23, ACLKUART1)
+DEFINE_ACLOCK(uart2, BCLKCTR0, 6, ACLKUART2)
+DEFINE_ACLOCK(uart3, BCLKCTR0, 8, ACLKUART3)
+DEFINE_ACLOCK(uart4, BCLKCTR1, 6, ACLKUART4)
+DEFINE_ACLOCK(i2c, BCLKCTR0, 7, ACLKI2C)
+DEFINE_ACLOCK(adc, BCLKCTR0, 10, ACLKADC)
+DEFINE_ACLOCK(usbh0, BCLKCTR0, 11, ACLKUSBH)
+DEFINE_ACLOCK(lcd, BCLKCTR0, 13, ACLKLCD)
+DEFINE_ACLOCK(sd0, BCLKCTR0, 17, ACLKSDH0)
+DEFINE_ACLOCK(sd1, BCLKCTR1, 5, ACLKSDH1)
+DEFINE_ACLOCK(spi0, BCLKCTR0, 24, ACLKSPI0)
+DEFINE_ACLOCK(spi1, BCLKCTR0, 30, ACLKSPI1)
+DEFINE_ACLOCK(spdif, BCLKCTR1, 2, ACLKSPDIF)
+DEFINE_ACLOCK(c3dec, BCLKCTR1, 9, ACLKC3DEC)
+DEFINE_ACLOCK(can0, BCLKCTR1, 10, ACLKCAN0)
+DEFINE_ACLOCK(can1, BCLKCTR1, 11, ACLKCAN1)
+DEFINE_ACLOCK(gsb0, BCLKCTR1, 13, ACLKGSB0)
+DEFINE_ACLOCK(gsb1, BCLKCTR1, 14, ACLKGSB1)
+DEFINE_ACLOCK(gsb2, BCLKCTR1, 15, ACLKGSB2)
+DEFINE_ACLOCK(gsb3, BCLKCTR1, 16, ACLKGSB3)
+DEFINE_ACLOCK(usbh1, BCLKCTR1, 20, ACLKUSBH)
+
+DEFINE_BCLOCK(dai0, BCLKCTR0, 0, NULL, NULL)
+DEFINE_BCLOCK(pic, BCLKCTR0, 1, NULL, NULL)
+DEFINE_BCLOCK(tc, BCLKCTR0, 2, NULL, NULL)
+DEFINE_BCLOCK(gpio, BCLKCTR0, 3, NULL, NULL)
+DEFINE_BCLOCK(usbd, BCLKCTR0, 4, NULL, NULL)
+DEFINE_BCLOCK(ecc, BCLKCTR0, 9, NULL, NULL)
+DEFINE_BCLOCK(gdma0, BCLKCTR0, 12, NULL, NULL)
+DEFINE_BCLOCK(rtc, BCLKCTR0, 15, NULL, NULL)
+DEFINE_BCLOCK(nfc, BCLKCTR0, 16, NULL, NULL)
+DEFINE_BCLOCK(g2d, BCLKCTR0, 18, NULL, NULL)
+DEFINE_BCLOCK(gdma1, BCLKCTR0, 22, NULL, NULL)
+DEFINE_BCLOCK(mscl, BCLKCTR0, 25, NULL, NULL)
+DEFINE_BCLOCK(bdma, BCLKCTR1, 0, NULL, NULL)
+DEFINE_BCLOCK(adma0, BCLKCTR1, 1, NULL, NULL)
+DEFINE_BCLOCK(scfg, BCLKCTR1, 3, NULL, NULL)
+DEFINE_BCLOCK(cid, BCLKCTR1, 4, NULL, NULL)
+DEFINE_BCLOCK(dai1, BCLKCTR1, 7, NULL, NULL)
+DEFINE_BCLOCK(adma1, BCLKCTR1, 8, NULL, NULL)
+DEFINE_BCLOCK(gps, BCLKCTR1, 12, NULL, NULL)
+DEFINE_BCLOCK(gdma2, BCLKCTR1, 17, NULL, NULL)
+DEFINE_BCLOCK(gdma3, BCLKCTR1, 18, NULL, NULL)
+DEFINE_BCLOCK(ddrc, BCLKCTR1, 19, NULL, NULL)
+
+#define _REGISTER_CLOCK(d, n, c) \
+	{ \
+		.dev_id = d, \
+		.con_id = n, \
+		.clk = &c, \
+	},
+
+static struct clk_lookup lookups[] = {
+	_REGISTER_CLOCK(NULL, "bus", bus)
+	_REGISTER_CLOCK(NULL, "cpu", cpu)
+	_REGISTER_CLOCK(NULL, "tct", tct)
+	_REGISTER_CLOCK(NULL, "tcx", tcx)
+	_REGISTER_CLOCK(NULL, "tcz", tcz)
+	_REGISTER_CLOCK(NULL, "ref", ref)
+	_REGISTER_CLOCK(NULL, "dai0", dai0)
+	_REGISTER_CLOCK(NULL, "pic", pic)
+	_REGISTER_CLOCK(NULL, "tc", tc)
+	_REGISTER_CLOCK(NULL, "gpio", gpio)
+	_REGISTER_CLOCK(NULL, "usbd", usbd)
+	_REGISTER_CLOCK("tcc-uart.0", NULL, uart0)
+	_REGISTER_CLOCK("tcc-uart.2", NULL, uart2)
+	_REGISTER_CLOCK("tcc-i2c", NULL, i2c)
+	_REGISTER_CLOCK("tcc-uart.3", NULL, uart3)
+	_REGISTER_CLOCK(NULL, "ecc", ecc)
+	_REGISTER_CLOCK(NULL, "adc", adc)
+	_REGISTER_CLOCK("tcc-usbh.0", "usb", usbh0)
+	_REGISTER_CLOCK(NULL, "gdma0", gdma0)
+	_REGISTER_CLOCK(NULL, "lcd", lcd)
+	_REGISTER_CLOCK(NULL, "rtc", rtc)
+	_REGISTER_CLOCK(NULL, "nfc", nfc)
+	_REGISTER_CLOCK("tcc-mmc.0", NULL, sd0)
+	_REGISTER_CLOCK(NULL, "g2d", g2d)
+	_REGISTER_CLOCK(NULL, "gdma1", gdma1)
+	_REGISTER_CLOCK("tcc-uart.1", NULL, uart1)
+	_REGISTER_CLOCK("tcc-spi.0", NULL, spi0)
+	_REGISTER_CLOCK(NULL, "mscl", mscl)
+	_REGISTER_CLOCK("tcc-spi.1", NULL, spi1)
+	_REGISTER_CLOCK(NULL, "bdma", bdma)
+	_REGISTER_CLOCK(NULL, "adma0", adma0)
+	_REGISTER_CLOCK(NULL, "spdif", spdif)
+	_REGISTER_CLOCK(NULL, "scfg", scfg)
+	_REGISTER_CLOCK(NULL, "cid", cid)
+	_REGISTER_CLOCK("tcc-mmc.1", NULL, sd1)
+	_REGISTER_CLOCK("tcc-uart.4", NULL, uart4)
+	_REGISTER_CLOCK(NULL, "dai1", dai1)
+	_REGISTER_CLOCK(NULL, "adma1", adma1)
+	_REGISTER_CLOCK(NULL, "c3dec", c3dec)
+	_REGISTER_CLOCK("tcc-can.0", NULL, can0)
+	_REGISTER_CLOCK("tcc-can.1", NULL, can1)
+	_REGISTER_CLOCK(NULL, "gps", gps)
+	_REGISTER_CLOCK("tcc-gsb.0", NULL, gsb0)
+	_REGISTER_CLOCK("tcc-gsb.1", NULL, gsb1)
+	_REGISTER_CLOCK("tcc-gsb.2", NULL, gsb2)
+	_REGISTER_CLOCK("tcc-gsb.3", NULL, gsb3)
+	_REGISTER_CLOCK(NULL, "gdma2", gdma2)
+	_REGISTER_CLOCK(NULL, "gdma3", gdma3)
+	_REGISTER_CLOCK(NULL, "ddrc", ddrc)
+	_REGISTER_CLOCK("tcc-usbh.1", "usb", usbh1)
+};
+
+static struct clk *root_clk_by_index(enum root_clks src)
+{
+	switch (src) {
+	case CLK_SRC_PLL0: return &pll0;
+	case CLK_SRC_PLL1: return &pll1;
+	case CLK_SRC_PLL2: return &pll2;
+	case CLK_SRC_PLL0DIV: return &pll0div;
+	case CLK_SRC_PLL1DIV: return &pll1div;
+	case CLK_SRC_PLL2DIV: return &pll2div;
+	case CLK_SRC_XI: return &xi;
+	case CLK_SRC_XTI: return &xti;
+	case CLK_SRC_XIDIV: return &xidiv;
+	case CLK_SRC_XTIDIV: return &xtidiv;
+	default: return NULL;
+	}
+}
+
+static void find_aclk_parent(struct clk *clk)
+{
+	unsigned int src;
+	struct clk *clock;
+
+	if (!clk->aclkreg)
+		return;
+
+	src = __raw_readl(clk->aclkreg) >> ACLK_SEL_SHIFT;
+	src &= CLK_SRC_MASK;
+
+	clock = root_clk_by_index(src);
+	if (!clock)
+		return;
+
+	clk->parent = clock;
+	clk->set_parent = aclk_set_parent;
+}
+
+int __init tcc_clocks_init(unsigned long xi_freq, unsigned long xti_freq)
+{
+	int i;
+
+	xi_rate = xi_freq;
+	xti_rate = xti_freq;
+
+	/* fixup parents and add the clock */
+	for (i = 0; i < ARRAY_SIZE(lookups); i++) {
+		find_aclk_parent(lookups[i].clk);
+		clkdev_add(&lookups[i]);
+	}
+
+	return tcc8k_timer_init(&tcz, (void __iomem *)TIMER_BASE, INT_TC32);
+}
diff --git a/arch/arm/plat-tcc/Makefile b/arch/arm/plat-tcc/Makefile
index 3f2e4fe..eceabc8 100644
--- a/arch/arm/plat-tcc/Makefile
+++ b/arch/arm/plat-tcc/Makefile
@@ -1,3 +1,3 @@
 # "Telechips Platform Common Modules"
 
-obj-y := system.o
+obj-y := clock.o system.o
diff --git a/arch/arm/plat-tcc/clock.c b/arch/arm/plat-tcc/clock.c
new file mode 100644
index 0000000..31b3ee8
--- /dev/null
+++ b/arch/arm/plat-tcc/clock.c
@@ -0,0 +1,180 @@
+/*
+ * Clock framework for Telechips SoCs
+ * Based on arch/arm/plat-mxc/clock.c
+ *
+ * Copyright (C) 2004 - 2005 Nokia corporation
+ * Written by Tuukka Tikkanen <tuukka.tikkanen at elektrobit.com>
+ * Modified for omap shared clock framework by Tony Lindgren <tony at atomide.com>
+ * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Juergen Beisert, kernel at pengutronix.de
+ * Copyright 2010 Hans J. Koch, hjk at linutronix.de
+ *
+ * Licensed under the terms of the GPL v2.
+ */
+
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/string.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+
+static DEFINE_MUTEX(clocks_mutex);
+
+/*-------------------------------------------------------------------------
+ * Standard clock functions defined in include/linux/clk.h
+ *-------------------------------------------------------------------------*/
+
+static void __clk_disable(struct clk *clk)
+{
+	BUG_ON(clk->refcount == 0);
+
+	if (!(--clk->refcount) && clk->disable) {
+		/* Unconditionally disable the clock in hardware */
+		clk->disable(clk);
+		/* recursively disable parents */
+		if (clk->parent)
+			__clk_disable(clk->parent);
+	}
+}
+
+static int __clk_enable(struct clk *clk)
+{
+	int ret = 0;
+
+	if (clk->refcount++ == 0 && clk->enable) {
+		if (clk->parent)
+			ret = __clk_enable(clk->parent);
+		if (ret)
+			return ret;
+		else
+			return clk->enable(clk);
+	}
+
+	return 0;
+}
+
+/* This function increments the reference count on the clock and enables the
+ * clock if not already enabled. The parent clock tree is recursively enabled
+ */
+int clk_enable(struct clk *clk)
+{
+	int ret = 0;
+
+	if (!clk)
+		return -EINVAL;
+
+	mutex_lock(&clocks_mutex);
+	ret = __clk_enable(clk);
+	mutex_unlock(&clocks_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+/* This function decrements the reference count on the clock and disables
+ * the clock when reference count is 0. The parent clock tree is
+ * recursively disabled
+ */
+void clk_disable(struct clk *clk)
+{
+	if (!clk)
+		return;
+
+	mutex_lock(&clocks_mutex);
+	__clk_disable(clk);
+	mutex_unlock(&clocks_mutex);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+/* Retrieve the *current* clock rate. If the clock itself
+ * does not provide a special calculation routine, ask
+ * its parent and so on, until one is able to return
+ * a valid clock rate
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+	if (!clk)
+		return 0UL;
+
+	if (clk->get_rate)
+		return clk->get_rate(clk);
+
+	return clk_get_rate(clk->parent);
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+/* Round the requested clock rate to the nearest supported
+ * rate that is less than or equal to the requested rate.
+ * This is dependent on the clock's current parent.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	if (!clk)
+		return 0;
+	if (!clk->round_rate)
+		return 0;
+
+	return clk->round_rate(clk, rate);
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+/* Set the clock to the requested clock rate. The rate must
+ * match a supported rate exactly based on what clk_round_rate returns
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	int ret = -EINVAL;
+
+	if (!clk)
+		return ret;
+	if (!clk->set_rate || !rate)
+		return ret;
+
+	mutex_lock(&clocks_mutex);
+	ret = clk->set_rate(clk, rate);
+	mutex_unlock(&clocks_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+/* Set the clock's parent to another clock source */
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	struct clk *old;
+	int ret = -EINVAL;
+
+	if (!clk)
+		return ret;
+	if (!clk->set_parent || !parent)
+		return ret;
+
+	mutex_lock(&clocks_mutex);
+	old = clk->parent;
+	if (clk->refcount)
+		__clk_enable(parent);
+	ret = clk->set_parent(clk, parent);
+	if (ret)
+		old = parent;
+	if (clk->refcount)
+		__clk_disable(old);
+	mutex_unlock(&clocks_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+/* Retrieve the clock's parent clock source */
+struct clk *clk_get_parent(struct clk *clk)
+{
+	if (!clk)
+		return NULL;
+
+	return clk->parent;
+}
+EXPORT_SYMBOL_GPL(clk_get_parent);
+
diff --git a/arch/arm/plat-tcc/include/mach/clkdev.h b/arch/arm/plat-tcc/include/mach/clkdev.h
new file mode 100644
index 0000000..04b37a8
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/plat-tcc/include/mach/clock.h b/arch/arm/plat-tcc/include/mach/clock.h
new file mode 100644
index 0000000..a12f58a
--- /dev/null
+++ b/arch/arm/plat-tcc/include/mach/clock.h
@@ -0,0 +1,48 @@
+/*
+ * Low level clock header file for Telechips TCC architecture
+ * (C) 2010 Hans J. Koch <hjk at linutronix.de>
+ *
+ * Licensed under the GPL v2.
+ */
+
+#ifndef __ASM_ARCH_TCC_CLOCK_H__
+#define __ASM_ARCH_TCC_CLOCK_H__
+
+#ifndef __ASSEMBLY__
+
+struct clk {
+	struct clk *parent;
+	/* id number of a root clock, 0 for normal clocks */
+	int root_id;
+	/* Reference count of clock enable/disable */
+	int refcount;
+	/* Address of associated BCLKCTRx register. Must be set. */
+	void __iomem *bclkctr;
+	/* Bit position for BCLKCTRx. Must be set. */
+	int bclk_shift;
+	/* Address of ACLKxxx register, if any. */
+	void __iomem *aclkreg;
+	/* get the current clock rate (always a fresh value) */
+	unsigned long (*get_rate) (struct clk *);
+	/* Function ptr to set the clock to a new rate. The rate must match a
+	   supported rate returned from round_rate. Leave blank if clock is not
+	   programmable */
+	int (*set_rate) (struct clk *, unsigned long);
+	/* Function ptr to round the requested clock rate to the nearest
+	   supported rate that is less than or equal to the requested rate. */
+	unsigned long (*round_rate) (struct clk *, unsigned long);
+	/* Function ptr to enable the clock. Leave blank if clock can not
+	   be gated. */
+	int (*enable) (struct clk *);
+	/* Function ptr to disable the clock. Leave blank if clock can not
+	   be gated. */
+	void (*disable) (struct clk *);
+	/* Function ptr to set the parent clock of the clock. */
+	int (*set_parent) (struct clk *, struct clk *);
+};
+
+int clk_register(struct clk *clk);
+void clk_unregister(struct clk *clk);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
index f3243eb..1786867 100644
--- a/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
+++ b/arch/arm/plat-tcc/include/mach/tcc8k-regs.h
@@ -30,13 +30,13 @@
 #define EXT_MEM_CTRL_BASE	0xf0000000
 #define EXT_MEM_CTRL_SIZE	SZ_4K
 
-#define CS1_BASE_VIRT		0xf7000000
-#define AHB_PERI_BASE_VIRT	0xf4000000
-#define APB0_PERI_BASE_VIRT	0xf1000000
-#define APB1_PERI_BASE_VIRT	0xf2000000
-#define EXT_MEM_CTRL_BASE_VIRT	0xf3000000
-#define INT_SRAM_BASE_VIRT	0xf5000000
-#define DATA_TCM_BASE_VIRT	0xf6000000
+#define CS1_BASE_VIRT		(void __iomem *)0xf7000000
+#define AHB_PERI_BASE_VIRT	(void __iomem *)0xf4000000
+#define APB0_PERI_BASE_VIRT	(void __iomem *)0xf1000000
+#define APB1_PERI_BASE_VIRT	(void __iomem *)0xf2000000
+#define EXT_MEM_CTRL_BASE_VIRT	(void __iomem *)0xf3000000
+#define INT_SRAM_BASE_VIRT	(void __iomem *)0xf5000000
+#define DATA_TCM_BASE_VIRT	(void __iomem *)0xf6000000
 
 #define __REG(x)     (*((volatile u32 *)(x)))
 
@@ -649,8 +649,7 @@
 #define PMGPIO_APB_OFFS		0x800
 
 /* Clock controller registers */
-#define CKC_BASE		(APB1_PERI_BASE_VIRT + 0x6000)
-#define CKC_BASE_PHYS		(APB1_PERI_BASE + 0x6000)
+#define CKC_BASE	((void __iomem *)(APB1_PERI_BASE_VIRT + 0x6000))
 
 #define CLKCTRL_OFFS		0x00
 #define PLL0CFG_OFFS		0x04
@@ -724,8 +723,20 @@
 /* SWRESET1 bits */
 #define SWRESET1_USBH1		(1 << 20)
 
-/* System clock sources */
+/* System clock sources. 
+ * Note: These are the clock sources that serve as parents for
+ * all other clocks. They have no parents themselves.
+ *
+ * These values are used for struct clk->root_id. All clocks
+ * that are not system clock sources have this value set to
+ * CLK_SRC_NOROOT. 
+ * The values for system clocks start with CLK_SRC_PLL0 == 0
+ * because this gives us exactly the values needed for the lower
+ * 4 bits of ACLK_* registers. Therefore, CLK_SRC_NOROOT is
+ * defined as -1 to not disturb the order.
+ */
 enum root_clks {
+	CLK_SRC_NOROOT = -1,
 	CLK_SRC_PLL0 = 0,
 	CLK_SRC_PLL1,
 	CLK_SRC_PLL0DIV,
-- 
1.6.3.3



From nico at fluxnic.net  Wed Jun 16 16:33:18 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 16 Jun 2010 16:33:18 -0400
Subject: [PATCH 0/5] enablement of some security features missing on ARM
Message-ID: <1276720403-27918-1-git-send-email-nico@fluxnic.net>

Those are simple patches adding address space layout randomization for
the user space heap and mmap(), as well as stack protector support.

The stack protector support depends on GCC's ability to insert a canary
on the stack upon entering a function, and validating it before leaving
that function. The included test module in patch #5 intends to test that,
but (at least with the GCC version I have here) the canary code is not
inserted in that particular test code unless it is forced with
-fstack-protector-all (if anyone has a clue to why I'd be interested).

 [PATCH 1/5] [ARM] implement arch_randomize_brk()
 [PATCH 2/5] [ARM] add address randomization to mmap()
 [PATCH 3/5] ARM: initial stack protector (-fstack-protector) support
 [PATCH 4/5] ARM: stack protector: change the canary value per task
 [PATCH 5/5] Stack protector: test module


Nicolas



From nico at fluxnic.net  Wed Jun 16 16:33:19 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 16 Jun 2010 16:33:19 -0400
Subject: [PATCH 1/5] [ARM] implement arch_randomize_brk()
In-Reply-To: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
References: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
Message-ID: <1276720403-27918-2-git-send-email-nico@fluxnic.net>

For this feature to take effect, CONFIG_COMPAT_BRK must be turned
off.  This can safely be turned off for any EABI user space versions.

Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
---
 arch/arm/include/asm/elf.h |    3 +++
 arch/arm/kernel/process.c  |    7 +++++++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 51662fe..0a96e8c 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -121,4 +121,7 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
 extern void elf_set_personality(const struct elf32_hdr *);
 #define SET_PERSONALITY(ex)	elf_set_personality(&(ex))
 
+extern unsigned long arch_randomize_brk(struct mm_struct *mm);
+#define arch_randomize_brk arch_randomize_brk
+
 #endif
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index acf5e6f..1c6eb7e 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -28,6 +28,7 @@
 #include <linux/tick.h>
 #include <linux/utsname.h>
 #include <linux/uaccess.h>
+#include <linux/random.h>
 
 #include <asm/leds.h>
 #include <asm/processor.h>
@@ -421,3 +422,9 @@ unsigned long get_wchan(struct task_struct *p)
 	} while (count ++ < 16);
 	return 0;
 }
+
+unsigned long arch_randomize_brk(struct mm_struct *mm)
+{
+	unsigned long range_end = mm->brk + 0x02000000;
+	return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
+}
-- 
1.7.1.337.gbd0bc



From nico at fluxnic.net  Wed Jun 16 16:33:20 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 16 Jun 2010 16:33:20 -0400
Subject: [PATCH 2/5] [ARM] add address randomization to mmap()
In-Reply-To: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
References: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
Message-ID: <1276720403-27918-3-git-send-email-nico@fluxnic.net>

Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
---
 arch/arm/mm/mmap.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
index f5abc51..4f5b396 100644
--- a/arch/arm/mm/mmap.c
+++ b/arch/arm/mm/mmap.c
@@ -7,6 +7,7 @@
 #include <linux/shm.h>
 #include <linux/sched.h>
 #include <linux/io.h>
+#include <linux/random.h>
 #include <asm/cputype.h>
 #include <asm/system.h>
 
@@ -80,6 +81,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
 	        start_addr = addr = TASK_UNMAPPED_BASE;
 	        mm->cached_hole_size = 0;
 	}
+	/* 8 bits of randomness in 20 address space bits */
+	if (current->flags & PF_RANDOMIZE)
+		addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT;
 
 full_search:
 	if (do_align)
-- 
1.7.1.337.gbd0bc



From nico at fluxnic.net  Wed Jun 16 16:33:21 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 16 Jun 2010 16:33:21 -0400
Subject: [PATCH 3/5] ARM: initial stack protector (-fstack-protector) support
In-Reply-To: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
References: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
Message-ID: <1276720403-27918-4-git-send-email-nico@fluxnic.net>

This is the very basic stuff without the changing canary upon
task switch yet.  Just the Kconfig option and a constant canary
value initialized at boot time.

Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
---
 arch/arm/Kconfig                      |   12 ++++++++++
 arch/arm/Makefile                     |    4 +++
 arch/arm/include/asm/stackprotector.h |   38 +++++++++++++++++++++++++++++++++
 arch/arm/kernel/process.c             |    6 +++++
 4 files changed, 60 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/include/asm/stackprotector.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..f160b93 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1374,6 +1374,18 @@ config UACCESS_WITH_MEMCPY
 	  However, if the CPU data cache is using a write-allocate mode,
 	  this option is unlikely to provide any performance gain.
 
+config CC_STACKPROTECTOR
+	bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
+	help
+	  This option turns on the -fstack-protector GCC feature. This
+	  feature puts, at the beginning of functions, a canary value on
+	  the stack just before the return address, and validates
+	  the value just before actually returning.  Stack based buffer
+	  overflows (that need to overwrite this return address) now also
+	  overwrite the canary, which gets detected and the attack is then
+	  neutralized via a kernel panic.
+	  This feature requires gcc version 4.2 or above.
+
 endmenu
 
 menu "Boot options"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 64ba313..ddf6da1 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -34,6 +34,10 @@ ifeq ($(CONFIG_FRAME_POINTER),y)
 KBUILD_CFLAGS	+=-fno-omit-frame-pointer -mapcs -mno-sched-prolog
 endif
 
+ifeq ($(CONFIG_CC_STACKPROTECTOR),y)
+KBUILD_CFLAGS	+=-fstack-protector
+endif
+
 ifeq ($(CONFIG_CPU_BIG_ENDIAN),y)
 KBUILD_CPPFLAGS	+= -mbig-endian
 AS		+= -EB
diff --git a/arch/arm/include/asm/stackprotector.h b/arch/arm/include/asm/stackprotector.h
new file mode 100644
index 0000000..de00332
--- /dev/null
+++ b/arch/arm/include/asm/stackprotector.h
@@ -0,0 +1,38 @@
+/*
+ * GCC stack protector support.
+ *
+ * Stack protector works by putting predefined pattern at the start of
+ * the stack frame and verifying that it hasn't been overwritten when
+ * returning from the function.  The pattern is called stack canary
+ * and gcc expects it to be defined by a global variable called
+ * "__stack_chk_guard" on ARM.  This unfortunately means that on SMP
+ * we cannot have a different canary value per task.
+ */
+
+#ifndef _ASM_STACKPROTECTOR_H
+#define _ASM_STACKPROTECTOR_H 1
+
+#include <linux/random.h>
+#include <linux/version.h>
+
+extern unsigned long __stack_chk_guard;
+
+/*
+ * Initialize the stackprotector canary value.
+ *
+ * NOTE: this must only be called from functions that never return,
+ * and it must always be inlined.
+ */
+static __always_inline void boot_init_stack_canary(void)
+{
+	unsigned long canary;
+
+	/* Try to get a semi random initial value. */
+	get_random_bytes(&canary, sizeof(canary));
+	canary ^= LINUX_VERSION_CODE;
+
+	current->stack_canary = canary;
+	__stack_chk_guard = current->stack_canary;
+}
+
+#endif	/* _ASM_STACKPROTECTOR_H */
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 1c6eb7e..090ac94 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -37,6 +37,12 @@
 #include <asm/stacktrace.h>
 #include <asm/mach/time.h>
 
+#ifdef CONFIG_CC_STACKPROTECTOR
+#include <linux/stackprotector.h>
+unsigned long __stack_chk_guard __read_mostly;
+EXPORT_SYMBOL(__stack_chk_guard);
+#endif
+
 static const char *processor_modes[] = {
   "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
   "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
-- 
1.7.1.337.gbd0bc



From nico at fluxnic.net  Wed Jun 16 16:33:22 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 16 Jun 2010 16:33:22 -0400
Subject: [PATCH 4/5] ARM: stack protector: change the canary value per task
In-Reply-To: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
References: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
Message-ID: <1276720403-27918-5-git-send-email-nico@fluxnic.net>

A new random value for the canary is stored in the task struct whenever
a new task is forked.  This is meant to allow for different canary values
per task.  On ARM, GCC expects the canary value to be found in a global
variable called __stack_chk_guard.  So this variable has to be updated
with the value stored in the task struct whenever a task switch occurs.

Because the variable GCC expects is global, this cannot work on SMP
unfortunately.  So, on SMP, the same initial canary value is kept
throughout, making this feature a bit less effective although it is still
useful.

One way to overcome this GCC limitation would be to locate the
__stack_chk_guard variable into a memory page of its own for each CPU,
and then use TLB locking to have each CPU see its own page at the same
virtual address for each of them.

Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
---
 arch/arm/kernel/asm-offsets.c |    3 +++
 arch/arm/kernel/entry-armv.S  |    8 ++++++++
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 8835115..85f2a01 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -40,6 +40,9 @@
 int main(void)
 {
   DEFINE(TSK_ACTIVE_MM,		offsetof(struct task_struct, active_mm));
+#ifdef CONFIG_CC_STACKPROTECTOR
+  DEFINE(TSK_STACK_CANARY,	offsetof(struct task_struct, stack_canary));
+#endif
   BLANK();
   DEFINE(TI_FLAGS,		offsetof(struct thread_info, flags));
   DEFINE(TI_PREEMPT,		offsetof(struct thread_info, preempt_count));
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 7ee48e7..2d14081 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -745,6 +745,11 @@ ENTRY(__switch_to)
 	mov	r4, #0xffff0fff
 	str	r3, [r4, #-15]			@ TLS val at 0xffff0ff0
 #endif
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+	ldr	r7, [r2, #TI_TASK]
+	ldr	r8, =__stack_chk_guard
+	ldr	r7, [r7, #TSK_STACK_CANARY]
+#endif
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r6, c3, c0, 0		@ Set domain register
 #endif
@@ -753,6 +758,9 @@ ENTRY(__switch_to)
 	ldr	r0, =thread_notify_head
 	mov	r1, #THREAD_NOTIFY_SWITCH
 	bl	atomic_notifier_call_chain
+#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
+	str	r7, [r8]
+#endif
  THUMB(	mov	ip, r4			   )
 	mov	r0, r5
  ARM(	ldmia	r4, {r4 - sl, fp, sp, pc}  )	@ Load all regs saved previously
-- 
1.7.1.337.gbd0bc



From nico at fluxnic.net  Wed Jun 16 16:33:23 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 16 Jun 2010 16:33:23 -0400
Subject: [PATCH 5/5] Stack protector: test module
In-Reply-To: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
References: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
Message-ID: <1276720403-27918-6-git-send-email-nico@fluxnic.net>

This module creates a stack overflow and tests if the stack protector
actually catches it.

Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
---
 samples/Kconfig                     |    8 +++
 samples/Makefile                    |    2 +-
 samples/tests/Makefile              |    5 ++
 samples/tests/test_stackprotector.c |   86 +++++++++++++++++++++++++++++++++++
 4 files changed, 100 insertions(+), 1 deletions(-)
 create mode 100644 samples/tests/Makefile
 create mode 100644 samples/tests/test_stackprotector.c

diff --git a/samples/Kconfig b/samples/Kconfig
index 8924f72..13f0eb2 100644
--- a/samples/Kconfig
+++ b/samples/Kconfig
@@ -44,4 +44,12 @@ config SAMPLE_HW_BREAKPOINT
 	help
 	  This builds kernel hardware breakpoint example modules.
 
+config SAMPLE_TEST_STACKPROTECTOR
+	tristate "Build test module for the stack protector -- loadable modules only"
+	depends on CC_STACKPROTECTOR && m
+	help
+	  This build a test module which upon insertion will exercize
+	  the -fstack-protector buffer overflow detection feature.
+	  Beware that this test is destructive as it will panic the kernel. 
+
 endif # SAMPLES
diff --git a/samples/Makefile b/samples/Makefile
index 0f15e6d..69132eb 100644
--- a/samples/Makefile
+++ b/samples/Makefile
@@ -1,4 +1,4 @@
 # Makefile for Linux samples code
 
 obj-$(CONFIG_SAMPLES)	+= kobject/ kprobes/ tracepoints/ trace_events/ \
-			   hw_breakpoint/
+			   hw_breakpoint/ tests/
diff --git a/samples/tests/Makefile b/samples/tests/Makefile
new file mode 100644
index 0000000..b174287
--- /dev/null
+++ b/samples/tests/Makefile
@@ -0,0 +1,5 @@
+# builds those example test modules, then to use one
+# (as root):insmod <module_name.ko>
+# Beware: those tests may be destructive!
+
+obj-$(CONFIG_SAMPLE_TEST_STACKPROTECTOR) += test_stackprotector.o
diff --git a/samples/tests/test_stackprotector.c b/samples/tests/test_stackprotector.c
new file mode 100644
index 0000000..1ea19a7
--- /dev/null
+++ b/samples/tests/test_stackprotector.c
@@ -0,0 +1,86 @@
+/*
+ * Sample test module to exercize the -fstack-protector buffer overflow
+ * detection feature.
+ *
+ * Author:	Nicolas Pitre
+ * Created:	June 7, 2010
+ * Copyright:	Canonical Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Beware: upon insertion of this module, the kernel should panic!
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+static long (*test_fn)(long *);
+
+static long test_good(long *x)
+{
+	int i;
+	long v;
+
+	x[0] = 0;
+	x[1] = 1;
+	for (i = 2; i < 50; i++) {
+		v = x[i-1] + x[i-2];
+		x[i] = v;
+	}
+
+	return v;
+}
+
+static void test_bad_target(void)
+{
+	/* Execution should never get here. */
+	panic("*** FAIL: STACK OVERFLOW DETECTION DID NOT TRIGGER ***\n");
+}
+
+static long test_stack_attack(long *x)
+{
+	int i;
+
+	/*
+	 * Let's overwrite the stack to scrub over our caller's
+	 * own return address.
+	 */
+	for (i = 50; i < 70; i++)
+		x[i] = (long)&test_bad_target;
+
+	/*
+	 * And then pretend some normality.
+	 */
+	return test_good(x);
+}
+
+/* this is not marked "static" to make sure it is not inlined */
+long test_stackprotected_caller(long *x)
+{
+	long buffer[50];
+	return test_fn(buffer);
+}
+
+static int __init test_stackprotector_init(void)
+{
+	long dummy_buffer[20];
+
+	printk(KERN_CRIT "*** stack protector test module ***\n");
+
+	test_fn = &test_good;
+	printk(KERN_CRIT "... testing normal function call\n");
+	test_stackprotected_caller(dummy_buffer);
+
+	test_fn = &test_stack_attack;
+	printk(KERN_CRIT "... testing rogue function call\n");
+	test_stackprotected_caller(dummy_buffer);
+
+	/* the kernel should have panicked by now */
+	printk(KERN_CRIT "*** FAIL: stack overflow attempt did not work ***\n");
+	return -EINVAL;
+}
+
+module_init(test_stackprotector_init)
+MODULE_LICENSE("GPL");
-- 
1.7.1.337.gbd0bc



From lilja.magnus at gmail.com  Wed Jun 16 16:36:31 2010
From: lilja.magnus at gmail.com (Magnus Lilja)
Date: Wed, 16 Jun 2010 22:36:31 +0200
Subject: [PATCH 2/2] mx31_3ds: revert cpld debug board relate code
In-Reply-To: <20100616065708.GJ20799@pengutronix.de>
References: <1276352707-8199-1-git-send-email-jason77.wang@gmail.com>
	<1276352707-8199-2-git-send-email-jason77.wang@gmail.com>
	<1276352707-8199-3-git-send-email-jason77.wang@gmail.com>
	<20100616065708.GJ20799@pengutronix.de>
Message-ID: <4C1935CF.3090108@gmail.com>

Sascha,


On 2010-06-16 08:57, Sascha Hauer wrote:
> 
> [Added Magnus to Cc]
> 
> Magnus,
> 
> As you are the original author of the removed code, can I have you
> Acked-by or Tested-by here?


Yes, I added the debugboard support. I've looked at the patches and the restructure looks ok.

The only thing that really differs is the interrupt function but I don't know which variant is more correct. I haven't had a chance to test the patches yet, perhaps in a couple of days.

Acked-by: Magnus Lilja <lilja.magnus at gmail.com>

/Magnus

> 
> Sascha
> 
> On Sat, Jun 12, 2010 at 10:25:07PM +0800, Jason Wang wrote:
>> Because we add a cpld debug board support in mxc level, we remove
>> those redudent codes from board level.
>>
>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>> ---
>>  arch/arm/mach-mx3/Kconfig                       |    1 +
>>  arch/arm/mach-mx3/mach-mx31_3ds.c               |  168 +----------------------
>>  arch/arm/plat-mxc/include/mach/board-mx31_3ds.h |   42 ------
>>  3 files changed, 4 insertions(+), 207 deletions(-)
>>
>> diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
>> index 344753f..fd422cf 100644
>> --- a/arch/arm/mach-mx3/Kconfig
>> +++ b/arch/arm/mach-mx3/Kconfig
>> @@ -58,6 +58,7 @@ config MACH_MX31LITE
>>  config MACH_MX31_3DS
>>  	bool "Support MX31PDK (3DS)"
>>  	select ARCH_MX31
>> +	select MXC_DEBUG_BOARD
>>  	help
>>  	  Include support for MX31PDK (3DS) platform. This includes specific
>>  	  configurations for the board and its peripherals.
>> diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
>> index 58e5729..d8af726 100644
>> --- a/arch/arm/mach-mx3/mach-mx31_3ds.c
>> +++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
>> @@ -22,7 +22,6 @@
>>  #include <linux/clk.h>
>>  #include <linux/irq.h>
>>  #include <linux/gpio.h>
>> -#include <linux/smsc911x.h>
>>  #include <linux/platform_device.h>
>>  #include <linux/mfd/mc13783.h>
>>  #include <linux/spi/spi.h>
>> @@ -38,6 +37,7 @@
>>  #include <asm/mach/map.h>
>>  #include <mach/common.h>
>>  #include <mach/board-mx31_3ds.h>
>> +#include <mach/cpld_debugboard.h>
>>  #include <mach/imx-uart.h>
>>  #include <mach/iomux-mx3.h>
>>  #include <mach/mxc_nand.h>
>> @@ -213,173 +213,11 @@ static struct imxuart_platform_data uart_pdata = {
>>  };
>>  
>>  /*
>> - * Support for the SMSC9217 on the Debug board.
>> - */
>> -
>> -static struct smsc911x_platform_config smsc911x_config = {
>> -	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
>> -	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
>> -	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
>> -	.phy_interface	= PHY_INTERFACE_MODE_MII,
>> -};
>> -
>> -static struct resource smsc911x_resources[] = {
>> -	{
>> -		.start		= LAN9217_BASE_ADDR,
>> -		.end		= LAN9217_BASE_ADDR + 0xff,
>> -		.flags		= IORESOURCE_MEM,
>> -	}, {
>> -		.start		= EXPIO_INT_ENET,
>> -		.end		= EXPIO_INT_ENET,
>> -		.flags		= IORESOURCE_IRQ,
>> -	},
>> -};
>> -
>> -static struct platform_device smsc911x_device = {
>> -	.name		= "smsc911x",
>> -	.id		= -1,
>> -	.num_resources	= ARRAY_SIZE(smsc911x_resources),
>> -	.resource	= smsc911x_resources,
>> -	.dev		= {
>> -		.platform_data = &smsc911x_config,
>> -	},
>> -};
>> -
>> -/*
>> - * Routines for the CPLD on the debug board. It contains a CPLD handling
>> - * LEDs, switches, interrupts for Ethernet.
>> - */
>> -
>> -static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
>> -{
>> -	uint32_t imr_val;
>> -	uint32_t int_valid;
>> -	uint32_t expio_irq;
>> -
>> -	imr_val = __raw_readw(CPLD_INT_MASK_REG);
>> -	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
>> -
>> -	expio_irq = MXC_EXP_IO_BASE;
>> -	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
>> -		if ((int_valid & 1) == 0)
>> -			continue;
>> -		generic_handle_irq(expio_irq);
>> -	}
>> -}
>> -
>> -/*
>> - * Disable an expio pin's interrupt by setting the bit in the imr.
>> - * @param irq           an expio virtual irq number
>> - */
>> -static void expio_mask_irq(uint32_t irq)
>> -{
>> -	uint16_t reg;
>> -	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
>> -
>> -	/* mask the interrupt */
>> -	reg = __raw_readw(CPLD_INT_MASK_REG);
>> -	reg |= 1 << expio;
>> -	__raw_writew(reg, CPLD_INT_MASK_REG);
>> -}
>> -
>> -/*
>> - * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
>> - * @param irq           an expanded io virtual irq number
>> - */
>> -static void expio_ack_irq(uint32_t irq)
>> -{
>> -	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
>> -
>> -	/* clear the interrupt status */
>> -	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
>> -	__raw_writew(0, CPLD_INT_RESET_REG);
>> -	/* mask the interrupt */
>> -	expio_mask_irq(irq);
>> -}
>> -
>> -/*
>> - * Enable a expio pin's interrupt by clearing the bit in the imr.
>> - * @param irq           a expio virtual irq number
>> - */
>> -static void expio_unmask_irq(uint32_t irq)
>> -{
>> -	uint16_t reg;
>> -	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
>> -
>> -	/* unmask the interrupt */
>> -	reg = __raw_readw(CPLD_INT_MASK_REG);
>> -	reg &= ~(1 << expio);
>> -	__raw_writew(reg, CPLD_INT_MASK_REG);
>> -}
>> -
>> -static struct irq_chip expio_irq_chip = {
>> -	.ack = expio_ack_irq,
>> -	.mask = expio_mask_irq,
>> -	.unmask = expio_unmask_irq,
>> -};
>> -
>> -static int __init mx31_3ds_init_expio(void)
>> -{
>> -	int i;
>> -	int ret;
>> -
>> -	/* Check if there's a debug board connected */
>> -	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
>> -	    (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
>> -	    (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
>> -		/* No Debug board found */
>> -		return -ENODEV;
>> -	}
>> -
>> -	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
>> -		__raw_readw(CPLD_CODE_VER_REG));
>> -
>> -	/*
>> -	 * Configure INT line as GPIO input
>> -	 */
>> -	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
>> -	if (ret)
>> -		pr_warning("could not get LAN irq gpio\n");
>> -	else
>> -		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
>> -
>> -	/* Disable the interrupts and clear the status */
>> -	__raw_writew(0, CPLD_INT_MASK_REG);
>> -	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
>> -	__raw_writew(0, CPLD_INT_RESET_REG);
>> -	__raw_writew(0x1F, CPLD_INT_MASK_REG);
>> -	for (i = MXC_EXP_IO_BASE;
>> -	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
>> -	     i++) {
>> -		set_irq_chip(i, &expio_irq_chip);
>> -		set_irq_handler(i, handle_level_irq);
>> -		set_irq_flags(i, IRQF_VALID);
>> -	}
>> -	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
>> -	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
>> -
>> -	return 0;
>> -}
>> -
>> -/*
>> - * This structure defines the MX31 memory map.
>> - */
>> -static struct map_desc mx31_3ds_io_desc[] __initdata = {
>> -	{
>> -		.virtual = MX31_CS5_BASE_ADDR_VIRT,
>> -		.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
>> -		.length = MX31_CS5_SIZE,
>> -		.type = MT_DEVICE,
>> -	},
>> -};
>> -
>> -/*
>>   * Set up static virtual mappings.
>>   */
>>  static void __init mx31_3ds_map_io(void)
>>  {
>>  	mx31_map_io();
>> -	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
>>  }
>>  
>>  /*!
>> @@ -402,8 +240,8 @@ static void __init mxc_board_init(void)
>>  	mx31_3ds_usbotg_init();
>>  	mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
>>  
>> -	if (!mx31_3ds_init_expio())
>> -		platform_device_register(&smsc911x_device);
>> +	if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
>> +		platform_device_register(&smsc_lan9217_device);
>>  }
>>  
>>  static void __init mx31_3ds_timer_init(void)
>> diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
>> index da92933..c26d88d 100644
>> --- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
>> +++ b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
>> @@ -12,48 +12,6 @@
>>  #define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
>>  
>>  /* Definitions for components on the Debug board */
>> -
>> -/* Base address of CPLD controller on the Debug board */
>> -#define DEBUG_BASE_ADDRESS		CS5_IO_ADDRESS(CS5_BASE_ADDR)
>> -
>> -/* LAN9217 ethernet base address */
>> -#define LAN9217_BASE_ADDR		CS5_BASE_ADDR
>> -
>> -/* CPLD config and interrupt base address */
>> -#define CPLD_ADDR			(DEBUG_BASE_ADDRESS + 0x20000)
>> -
>> -/* LED switchs */
>> -#define CPLD_LED_REG			(CPLD_ADDR + 0x00)
>> -/* buttons */
>> -#define CPLD_SWITCH_BUTTONS_REG	(EXPIO_ADDR + 0x08)
>> -/* status, interrupt */
>> -#define CPLD_INT_STATUS_REG		(CPLD_ADDR + 0x10)
>> -#define CPLD_INT_MASK_REG		(CPLD_ADDR + 0x38)
>> -#define CPLD_INT_RESET_REG		(CPLD_ADDR + 0x20)
>> -/* magic word for debug CPLD */
>> -#define CPLD_MAGIC_NUMBER1_REG		(CPLD_ADDR + 0x40)
>> -#define CPLD_MAGIC_NUMBER2_REG		(CPLD_ADDR + 0x48)
>> -/* CPLD code version */
>> -#define CPLD_CODE_VER_REG		(CPLD_ADDR + 0x50)
>> -/* magic word for debug CPLD */
>> -#define CPLD_MAGIC_NUMBER3_REG		(CPLD_ADDR + 0x58)
>> -/* module reset register */
>> -#define CPLD_MODULE_RESET_REG		(CPLD_ADDR + 0x60)
>> -/* CPU ID and Personality ID */
>> -#define CPLD_MCU_BOARD_ID_REG		(CPLD_ADDR + 0x68)
>> -
>> -/* CPLD IRQ line for external uart, external ethernet etc */
>>  #define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
>>  
>> -#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
>> -#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)
>> -
>> -#define EXPIO_INT_ENET		(MXC_EXP_IO_BASE + 0)
>> -#define EXPIO_INT_XUART_A	(MXC_EXP_IO_BASE + 1)
>> -#define EXPIO_INT_XUART_B	(MXC_EXP_IO_BASE + 2)
>> -#define EXPIO_INT_BUTTON_A	(MXC_EXP_IO_BASE + 3)
>> -#define EXPIO_INT_BUTTON_B	(MXC_EXP_IO_BASE + 4)
>> -
>> -#define MXC_MAX_EXP_IO_LINES	16
>> -
>>  #endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
>> -- 
>> 1.5.6.5
>>
>>
> 



From ben-linux at fluff.org  Wed Jun 16 17:14:58 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Wed, 16 Jun 2010 22:14:58 +0100
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100614093459.GD12159@pengutronix.de>
References: <19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
	<1276319643.1962.181.camel@pasglop>
	<19477.52889.982995.407051@ipc1.ka-ro>
	<20100614064028.GA12159@pengutronix.de>
	<19477.53673.644128.558827@ipc1.ka-ro>
	<20100614093459.GD12159@pengutronix.de>
Message-ID: <20100616211458.GB30005@fluff.org.uk>

On Mon, Jun 14, 2010 at 11:34:59AM +0200, Uwe Kleine-K?nig wrote:
> Hello,
> 
> > And arch/arm/plat-s3c/clock.c has the following comment:
> > |/* We originally used an mutex here, but some contexts (see resume)
> > | * are calling functions such as clk_set_parent() with IRQs disabled
> > | * causing an BUG to be triggered.
> > | */
> > |DEFINE_SPINLOCK(clocks_lock);
> I wonder why it's needed to reparent clocks during resume.  And where
> exactly IRQs are disabled.  Hmm, this comment was initially introduced
> by v2.6.28-rc7-180-gc3391e3, its commit log talks about cpufreq, not
> resume.
> 
> Ben (Dooks): Is this still relevant?

Yes, unfortunately the system may not resume with the clock registers
in the same state as they where before, and there are things that may
need to set the parents before the resume can continue.

We may have ended up saving quite a bit of the clock state by force,
but it isn't the nicest way, and there's still issues with any clocks
that require pll stabilisation.

-- 
Ben (ben at fluff.org, http://www.fluff.org/)

  'a smiley only costs 4 bytes'


From ben-linux at fluff.org  Wed Jun 16 17:16:45 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Wed, 16 Jun 2010 22:16:45 +0100
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100614094310.GE12159@pengutronix.de>
References: <19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
	<1276319643.1962.181.camel@pasglop>
	<19477.52889.982995.407051@ipc1.ka-ro>
	<1276507378.2552.39.camel@pasglop>
	<19477.63136.664249.167207@ipc1.ka-ro>
	<20100614094310.GE12159@pengutronix.de>
Message-ID: <20100616211645.GC30005@fluff.org.uk>

On Mon, Jun 14, 2010 at 11:43:10AM +0200, Uwe Kleine-K?nig wrote:
> On Mon, Jun 14, 2010 at 11:30:08AM +0200, Lothar Wa?mann wrote:
> > Benjamin Herrenschmidt writes:
> > > On Mon, 2010-06-14 at 08:39 +0200, Lothar Wa?mann wrote:
> > > > All implementations so far use spin_lock_irq_save()!
> > > 
> > > Nothing prevents your implementation to be a tad smarter.
> > > 
> > I vote for consistency, so that device drivers can be kept arch
> > independent instead of having to care about implentation details of
> > each arch.
> Back when I implemented clock support for ns9xxx (unfortunately not in
> mainline) I tried with a spinlock first and later switched to a mutex.
> IIRC the reason was that on ns9215 enabling the rtc clock took long
> (don't remember a number) and successfull enabling was signaled by an
> irq.  So I would have had to implement irq polling in the clock code.

Ok, you could have implemented a lock ot update the state, then had
some form of wake-queue to wake up the task once it did.

> I think you can find different examples that make both possiblities bad.
> All in all I think that a sleeping clock implementation is preferable as
> it improves (general) latencies.

It may be that we need to do a bit of work on some of the drivers to
ensure that they don't fully re-set their clocks until they are able
to sleep.

-- 
Ben (ben at fluff.org, http://www.fluff.org/)

  'a smiley only costs 4 bytes'


From ohad at wizery.com  Wed Jun 16 17:17:58 2010
From: ohad at wizery.com (Ohad Ben-Cohen)
Date: Wed, 16 Jun 2010 16:17:58 -0500
Subject: [PATCH] mailbox: change full flag per mailbox queue instead of 
	global
In-Reply-To: <1276534269-19179-1-git-send-email-x0095840@ti.com>
References: <1276534269-19179-1-git-send-email-x0095840@ti.com>
Message-ID: <AANLkTimQrOIbsvQw7yv2x_KJmsv2p5KfNdcsNk2_DWGm@mail.gmail.com>

On Mon, Jun 14, 2010 at 11:51 AM, Fernando Guzman Lugo <x0095840 at ti.com> wrote:
> As pointed by Ben Ohand, the variable rq_full flag is a global
> variable, so if there are multiple mailbox users there will be
> conflics. Now there is a full flag per mailbox queue.
>
> Reported-by: Ohad Ben-Cohen <ohad at wizery.com>
> Signed-off-by: Fernando Guzman Lugo <x0095840 at ti.com>
> ---
> ?arch/arm/plat-omap/include/plat/mailbox.h | ? ?1 +
> ?arch/arm/plat-omap/mailbox.c ? ? ? ? ? ? ?| ? ?7 +++----
> ?2 files changed, 4 insertions(+), 4 deletions(-)


Thanks, Fernando, it looks good !

Since the original patch wasn't merged yet, it might make more sense
to squash it with this fix into a single patch, instead of introducing
this fix as a new patch. what do you think ?

>
> diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-omap/include/plat/mailbox.h
> index 729166b..a6144b8 100644
> --- a/arch/arm/plat-omap/include/plat/mailbox.h
> +++ b/arch/arm/plat-omap/include/plat/mailbox.h
> @@ -47,6 +47,7 @@ struct omap_mbox_queue {
> ? ? ? ?struct tasklet_struct ? tasklet;
> ? ? ? ?int ? ? (*callback)(void *);
> ? ? ? ?struct omap_mbox ? ? ? ?*mbox;
> + ? ? ? bool ? ?full;
> ?};
>
> ?struct omap_mbox {
> diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
> index 8d86b0b..a1e274e 100644
> --- a/arch/arm/plat-omap/mailbox.c
> +++ b/arch/arm/plat-omap/mailbox.c
> @@ -30,7 +30,6 @@
>
> ?static struct omap_mbox *mboxes;
> ?static DEFINE_RWLOCK(mboxes_lock);
> -static bool rq_full;
>
> ?static int mbox_configured;
> ?static DEFINE_MUTEX(mbox_configured_lock);
> @@ -140,9 +139,9 @@ static void mbox_rx_work(struct work_struct *work)
> ? ? ? ?while (1) {
> ? ? ? ? ? ? ? ?spin_lock_irqsave(q->queue_lock, flags);
> ? ? ? ? ? ? ? ?rq = blk_fetch_request(q);
> - ? ? ? ? ? ? ? if (rq_full) {
> + ? ? ? ? ? ? ? if (mbox->rxq->full) {
> ? ? ? ? ? ? ? ? ? ? ? ?omap_mbox_enable_irq(mbox, IRQ_RX);
> - ? ? ? ? ? ? ? ? ? ? ? rq_full = false;
> + ? ? ? ? ? ? ? ? ? ? ? mbox->rxq->full = false;
> ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ?spin_unlock_irqrestore(q->queue_lock, flags);
> ? ? ? ? ? ? ? ?if (!rq)
> @@ -183,7 +182,7 @@ static void __mbox_rx_interrupt(struct omap_mbox *mbox)
> ? ? ? ? ? ? ? ?rq = blk_get_request(q, WRITE, GFP_ATOMIC);
> ? ? ? ? ? ? ? ?if (unlikely(!rq)) {
> ? ? ? ? ? ? ? ? ? ? ? ?omap_mbox_disable_irq(mbox, IRQ_RX);
> - ? ? ? ? ? ? ? ? ? ? ? rq_full = true;
> + ? ? ? ? ? ? ? ? ? ? ? mbox->rxq->full = true;
> ? ? ? ? ? ? ? ? ? ? ? ?goto nomem;
> ? ? ? ? ? ? ? ?}
>
> --
> 1.6.3.3
>
>


From ben-linux at fluff.org  Wed Jun 16 17:13:11 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Wed, 16 Jun 2010 22:13:11 +0100
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <19477.53673.644128.558827@ipc1.ka-ro>
References: <201006111557.12249.jeremy.kerr@canonical.com>
	<19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
	<1276319643.1962.181.camel@pasglop>
	<19477.52889.982995.407051@ipc1.ka-ro>
	<20100614064028.GA12159@pengutronix.de>
	<19477.53673.644128.558827@ipc1.ka-ro>
Message-ID: <20100616211311.GA30005@fluff.org.uk>

On Mon, Jun 14, 2010 at 08:52:25AM +0200, Lothar Wa?mann wrote:
> Hi,
> 
> Uwe Kleine-K?nig writes:
> > Hello Lothar,
> > 
> > On Mon, Jun 14, 2010 at 08:39:21AM +0200, Lothar Wa?mann wrote:
> > > Hi,
> > > 
> > > Benjamin Herrenschmidt writes:
> > > > On Fri, 2010-06-11 at 12:08 +0200, Lothar Wa?mann wrote:
> > > > > Hi,
> > > > > 
> > > > > > > > > Using a mutex in clk_enable()/clk_disable() is a bad idea, since that
> > > > > > > > > makes it impossible to call those functions in interrupt context.
> > > > > > IMHO if a device generates an irq its clock should already be on.  This
> > > > > > way you don't need to enable or disable a clock in irq context.
> > > > > >  
> > > > > You may want to disable a clock in the IRQ handler. The VPU driver in
> > > > > the Freescale BSP for i.MX51 does exactly this.
> > > > > Anyway I don't see any reason for using a mutex here instead of
> > > > > spin_lock_irq_save() as all other implementations do.
> > > > 
> > > > Because you suddenly make it impossible to sleep inside enable/disable
> > >               ^^^^^^^^^^^^^^^^^^^^^^^^^^^
> > > ???
> > > All implementations so far use spin_lock_irq_save()!
> > > 
> > > How would you be able to sleep with a mutex held?
> > > If you hold a lock you must not sleep, no matter what sort of lock it
> > > is.
> > That's wrong.  With a mutex hold you may sleep.
> > 
> OK, you're right. But still all other implementations (omap, mxc,
> davinci,...) use spin_lock_irqsave() to protect the enable/disable
> functions and don't seem to have any problem with this.
> Is there any reason to change this, or make it inconsistent
> for one arch?
> 
> And arch/arm/plat-s3c/clock.c has the following comment:
> |/* We originally used an mutex here, but some contexts (see resume)
> | * are calling functions such as clk_set_parent() with IRQs disabled
> | * causing an BUG to be triggered.
> | */
> |DEFINE_SPINLOCK(clocks_lock);

It entirely depends on what you are protecting, in some cases a mutex
is good enough for finding clocks, sometimes you may well end up with
the case you need to spin.

However, none of these clock implementations really thought through
all the subtleties of how it works. The s3c gets the clock naming
wrong (will be trying to sort that out soon).

-- 
Ben (ben at fluff.org, http://www.fluff.org/)

  'a smiley only costs 4 bytes'


From ryan at bluewatersys.com  Wed Jun 16 17:20:22 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Thu, 17 Jun 2010 09:20:22 +1200
Subject: [PATCH 1/3] AT91: Define NR_BUILTIN_GPIO
In-Reply-To: <1276723224-23252-1-git-send-email-ryan@bluewatersys.com>
References: <1276723224-23252-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1276723224-23252-2-git-send-email-ryan@bluewatersys.com>

Add definition for NR_BUILTIN_GPIO for AT91 family

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-at91/include/mach/gpio.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 04c91e3..bfdd8ab 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -19,6 +19,7 @@
 #define PIN_BASE		NR_AIC_IRQS
 
 #define MAX_GPIO_BANKS		5
+#define NR_BUILTIN_GPIO		(PIN_BASE + (MAX_GPIO_BANKS * 32))
 
 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
 
-- 
1.5.5.1



From ryan at bluewatersys.com  Wed Jun 16 17:20:21 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Thu, 17 Jun 2010 09:20:21 +1200
Subject: [PATCH 0/3] at91: Add support for Snapper 9260/9G20 modules
Message-ID: <1276723224-23252-1-git-send-email-ryan@bluewatersys.com>

Add support for Bluewater Systems Snapper 9260/9G20 modules. 

In order to fully support the modules, NR_BUILTIN_GPIO must be defined
for at91 and vbus polarity and polling have been added to the at91 udc
driver.

Ryan Mallon (3):
  AT91: Define NR_BUILTIN_GPIO
  at91_udc: Add vbus polarity and polling mode
  at91: Add support for Bluewater Systems Snapper 9260/9G20 modules

 arch/arm/mach-at91/Kconfig              |   11 ++
 arch/arm/mach-at91/Makefile             |    3 +
 arch/arm/mach-at91/board-snapper9260.c  |  189 +++++++++++++++++++++++++++++++
 arch/arm/mach-at91/include/mach/board.h |    2 +
 arch/arm/mach-at91/include/mach/gpio.h  |    1 +
 drivers/usb/gadget/at91_udc.c           |   45 ++++++--
 drivers/usb/gadget/at91_udc.h           |    1 +
 7 files changed, 242 insertions(+), 10 deletions(-)
 create mode 100644 arch/arm/mach-at91/board-snapper9260.c



From ryan at bluewatersys.com  Wed Jun 16 17:20:23 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Thu, 17 Jun 2010 09:20:23 +1200
Subject: [PATCH 2/3] at91_udc: Add vbus polarity and polling mode
In-Reply-To: <1276723224-23252-1-git-send-email-ryan@bluewatersys.com>
References: <1276723224-23252-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1276723224-23252-3-git-send-email-ryan@bluewatersys.com>

Allow the vbus signal to optionally use polling. This is required if
the vbus signal is connected to an non-interrupting io expander for
example. Also add an option to have vbus be an active low signal. Both
options are set in the platform data for the device.

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-at91/include/mach/board.h |    2 +
 drivers/usb/gadget/at91_udc.c           |   45 ++++++++++++++++++++++++-------
 drivers/usb/gadget/at91_udc.h           |    1 +
 3 files changed, 38 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index df2ed84..58528aa 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -44,6 +44,8 @@
  /* USB Device */
 struct at91_udc_data {
 	u8	vbus_pin;		/* high == host powering us */
+	u8	vbus_active_low;	/* vbus polarity */
+	u8	vbus_polled;		/* Use polling, not interrupt */
 	u8	pullup_pin;		/* active == D+ pulled up */
 	u8	pullup_active_low;	/* true == pullup_pin is active low */
 };
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index eaa79c8..9649d76 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -76,6 +76,7 @@
 static const char driver_name [] = "at91_udc";
 static const char ep0name[] = "ep0";
 
+#define VBUS_POLL_TIMEOUT	msecs_to_jiffies(1000)
 
 #define at91_udp_read(dev, reg) \
 	__raw_readl((dev)->udp_baseaddr + (reg))
@@ -1556,20 +1557,37 @@ static struct at91_udc controller = {
 	/* ep6 and ep7 are also reserved (custom silicon might use them) */
 };
 
+static void at91_vbus_update(struct at91_udc *udc)
+{
+	unsigned value;
+
+	value = gpio_get_value(udc->board.vbus_pin);
+	if (udc->board.vbus_active_low)
+		value ^= 1;
+	if (value != udc->vbus)
+		at91_vbus_session(&udc->gadget, value);
+}
+
 static irqreturn_t at91_vbus_irq(int irq, void *_udc)
 {
 	struct at91_udc	*udc = _udc;
-	unsigned	value;
 
 	/* vbus needs at least brief debouncing */
 	udelay(10);
-	value = gpio_get_value(udc->board.vbus_pin);
-	if (value != udc->vbus)
-		at91_vbus_session(&udc->gadget, value);
+	at91_vbus_update(udc);
 
 	return IRQ_HANDLED;
 }
 
+static void at91_vbus_timer(unsigned long data)
+{
+	struct at91_udc *udc = (struct at91_udc *)data;
+
+	at91_vbus_update(udc);
+	if (!timer_pending(&udc->vbus_timer))
+	    mod_timer(&udc->vbus_timer, jiffies + VBUS_POLL_TIMEOUT);
+}
+
 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
 {
 	struct at91_udc	*udc = &controller;
@@ -1764,12 +1782,19 @@ static int __init at91udc_probe(struct platform_device *pdev)
 		 * a pending interrupt.
 		 */
 		udc->vbus = gpio_get_value(udc->board.vbus_pin);
-		if (request_irq(udc->board.vbus_pin, at91_vbus_irq,
-				IRQF_DISABLED, driver_name, udc)) {
-			DBG("request vbus irq %d failed\n",
-					udc->board.vbus_pin);
-			retval = -EBUSY;
-			goto fail3;
+		if (udc->board.vbus_polled) {
+			setup_timer(&udc->vbus_timer, at91_vbus_timer,
+				    (unsigned long)udc);
+			mod_timer(&udc->vbus_timer,
+				  jiffies + VBUS_POLL_TIMEOUT);
+		} else {
+			if (request_irq(udc->board.vbus_pin, at91_vbus_irq,
+					IRQF_DISABLED, driver_name, udc)) {
+				DBG("request vbus irq %d failed\n",
+				    udc->board.vbus_pin);
+				retval = -EBUSY;
+				goto fail3;
+			}
 		}
 	} else {
 		DBG("no VBUS detection, assuming always-on\n");
diff --git a/drivers/usb/gadget/at91_udc.h b/drivers/usb/gadget/at91_udc.h
index c65d622..2ebd665 100644
--- a/drivers/usb/gadget/at91_udc.h
+++ b/drivers/usb/gadget/at91_udc.h
@@ -144,6 +144,7 @@ struct at91_udc {
 	struct proc_dir_entry		*pde;
 	void __iomem			*udp_baseaddr;
 	int				udp_irq;
+	struct timer_list		vbus_timer;
 };
 
 static inline struct at91_udc *to_udc(struct usb_gadget *g)
-- 
1.5.5.1



From ryan at bluewatersys.com  Wed Jun 16 17:20:24 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Thu, 17 Jun 2010 09:20:24 +1200
Subject: [PATCH 3/3] at91: Add support for Bluewater Systems Snapper 9260/9G20
	modules
In-Reply-To: <1276723224-23252-1-git-send-email-ryan@bluewatersys.com>
References: <1276723224-23252-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1276723224-23252-4-git-send-email-ryan@bluewatersys.com>

Add support for Bluewater Systems Snapper 9260/9G20 modules

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-at91/Kconfig             |   11 ++
 arch/arm/mach-at91/Makefile            |    3 +
 arch/arm/mach-at91/board-snapper9260.c |  189 ++++++++++++++++++++++++++++++++
 3 files changed, 203 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-at91/board-snapper9260.c

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 841eaf8..939bccd 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -366,6 +366,17 @@ config MACH_STAMP9G20
 
 endif
 
+if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
+comment "AT91SAM9260/AT91SAM9G20 boards"
+
+config MACH_SNAPPER_9260
+        bool "Bluewater Systems Snapper 9260/9G20 module"
+        help
+          Select this if you are using the Bluewater Systems Snapper 9260 or
+          Snapper 9G20 modules.
+          <http://www.bluewatersys.com/>
+endif
+
 # ----------------------------------------------------------
 
 if ARCH_AT91SAM9G45
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c1f821e..ca2ac00 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -66,6 +66,9 @@ obj-$(CONFIG_MACH_CPU9G20)	+= board-cpu9krea.o
 obj-$(CONFIG_MACH_STAMP9G20)	+= board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)	+= board-stamp9g20.o
 
+# AT91SAM9260/AT91SAM9G20 board-specific support
+obj-$(CONFIG_MACH_SNAPPER_9260)	+= board-snapper9260.o
+
 # AT91SAM9G45 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
 
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
new file mode 100644
index 0000000..91ed809
--- /dev/null
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -0,0 +1,189 @@
+/*
+ * linux/arch/arm/mach-at91/board-snapper9260.c
+ *
+ *  Copyright (C) 2010 Bluewater System Ltd
+ *
+ * Author: Andre Renaud <andre at bluewatersys.com>
+ * Author: Ryan Mallon  <ryan at bluewatersys.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c/pca953x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/at91sam9_smc.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+#define SNAPPER9260_IO_EXP_GPIO(x)	(NR_BUILTIN_GPIO + (x))
+
+static void __init snapper9260_map_io(void)
+{
+	at91sam9260_initialize(18432000);
+
+	/* Debug on ttyS0 */
+	at91_register_uart(0, 0, 0);
+	at91_set_serial_console(0);
+
+	at91_register_uart(AT91SAM9260_ID_US0, 1, 
+			   ATMEL_UART_CTS | ATMEL_UART_RTS);
+	at91_register_uart(AT91SAM9260_ID_US1, 2,
+			   ATMEL_UART_CTS | ATMEL_UART_RTS);	
+	at91_register_uart(AT91SAM9260_ID_US2, 3, 0);	
+}
+
+static void __init snapper9260_init_irq(void)
+{
+	at91sam9260_init_interrupts(NULL);
+}
+
+static struct at91_usbh_data __initdata snapper9260_usbh_data = {
+	.ports		= 2,
+};
+
+static struct at91_udc_data __initdata snapper9260_udc_data = {
+	.vbus_pin		= SNAPPER9260_IO_EXP_GPIO(5),
+	.vbus_active_low	= 1,
+	.vbus_polled		= 1,
+};
+
+static struct at91_eth_data snapper9260_macb_data = {
+	.is_rmii	= 1,
+};
+
+static struct mtd_partition __initdata snapper9260_nand_partitions[] = {
+	{
+		.name	= "Preboot",
+		.offset	= 0,
+		.size	= SZ_128K,
+	},
+	{
+		.name	= "Bootloader",
+		.offset	= MTDPART_OFS_APPEND,
+		.size	= SZ_256K,
+	},
+	{
+		.name	= "Environment",
+		.offset	= MTDPART_OFS_APPEND,
+		.size	= SZ_128K,
+	},
+	{
+		.name	= "Kernel",
+		.offset	= MTDPART_OFS_APPEND,
+		.size	= SZ_4M,
+	},
+	{
+		.name	= "Filesystem",
+		.offset	= MTDPART_OFS_APPEND,
+		.size	= MTDPART_SIZ_FULL,
+	},
+};
+
+static struct mtd_partition * __init 
+snapper9260_nand_partition_info(int size, int *num_partitions)
+{
+	*num_partitions = ARRAY_SIZE(snapper9260_nand_partitions);
+	return snapper9260_nand_partitions;
+}
+
+static struct atmel_nand_data __initdata snapper9260_nand_data = {
+	.ale		= 21,
+	.cle		= 22,
+	.rdy_pin	= AT91_PIN_PC13,
+	.partition_info	= snapper9260_nand_partition_info,
+	.bus_width_16	= 0,
+};
+
+static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
+	.ncs_read_setup		= 0,
+	.nrd_setup		= 0,
+	.ncs_write_setup	= 0,
+	.nwe_setup		= 0,
+
+	.ncs_read_pulse		= 5,
+	.nrd_pulse		= 2,
+	.ncs_write_pulse	= 5,
+	.nwe_pulse		= 2,
+	
+	.read_cycle		= 7,
+	.write_cycle		= 7,
+
+	.mode			= (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+				   AT91_SMC_EXNWMODE_DISABLE),
+	.tdf_cycles		= 1,
+};
+
+static struct pca953x_platform_data snapper9260_io_expander_data = {
+	.gpio_base		= SNAPPER9260_IO_EXP_GPIO(0),
+};
+
+static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
+	{
+		/* IO expander */
+		I2C_BOARD_INFO("max7312", 0x28),
+		.platform_data = &snapper9260_io_expander_data,
+	},
+	{
+		/* Audio codec */
+		I2C_BOARD_INFO("tlv320aic23", 0x1a),
+	},
+	{
+		/* RTC */
+		I2C_BOARD_INFO("isl1208", 0x6f),
+	},
+};
+
+static void __init snapper9260_add_device_nand(void)
+{
+	at91_set_A_periph(AT91_PIN_PC14, 0);
+	sam9_smc_configure(3, &snapper9260_nand_smc_config);
+	at91_add_device_nand(&snapper9260_nand_data);
+}
+
+static void __init snapper9260_board_init(void)
+{
+	at91_add_device_i2c(snapper9260_i2c_devices,
+			    ARRAY_SIZE(snapper9260_i2c_devices));
+	at91_add_device_serial();
+	at91_add_device_usbh(&snapper9260_usbh_data);
+	at91_add_device_udc(&snapper9260_udc_data);
+	at91_add_device_eth(&snapper9260_macb_data);
+	at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK |
+						 ATMEL_SSC_TD | ATMEL_SSC_RD));
+	snapper9260_add_device_nand();
+}
+
+MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
+	.phys_io	= AT91_BASE_SYS,
+	.io_pg_offst	= (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+	.boot_params	= AT91_SDRAM_BASE + 0x100,
+	.timer		= &at91sam926x_timer,
+	.map_io		= snapper9260_map_io,
+	.init_irq	= snapper9260_init_irq,
+	.init_machine	= snapper9260_board_init,
+MACHINE_END
+
+
-- 
1.5.5.1



From benh at kernel.crashing.org  Wed Jun 16 19:33:51 2010
From: benh at kernel.crashing.org (Benjamin Herrenschmidt)
Date: Thu, 17 Jun 2010 09:33:51 +1000
Subject: [RFC,PATCH 1/2] Add a common struct clk
In-Reply-To: <20100616211645.GC30005@fluff.org.uk>
References: <19473.61547.684572.647641@ipc1.ka-ro>
	<201006111718.47426.jeremy.kerr@canonical.com>
	<19474.172.742782.972629@ipc1.ka-ro>
	<20100611095839.GC10894@pengutronix.de>
	<19474.2817.333749.485028@ipc1.ka-ro>
	<1276319643.1962.181.camel@pasglop>
	<19477.52889.982995.407051@ipc1.ka-ro>
	<1276507378.2552.39.camel@pasglop>
	<19477.63136.664249.167207@ipc1.ka-ro>
	<20100614094310.GE12159@pengutronix.de>
	<20100616211645.GC30005@fluff.org.uk>
Message-ID: <1276731231.2552.645.camel@pasglop>

On Wed, 2010-06-16 at 22:16 +0100, Ben Dooks wrote:
> > I think you can find different examples that make both possiblities
> bad.
> > All in all I think that a sleeping clock implementation is
> preferable as
> > it improves (general) latencies.
> 
> It may be that we need to do a bit of work on some of the drivers to
> ensure that they don't fully re-set their clocks until they are able
> to sleep. 

With the move of the interrupt disable we did upstream not long ago,
most drivers now can sleep at any stage of resume. sysdev's can't so
those are the main issue, but then, I don't like sysdevs :-)

I must say that on powermac I avoid some of these problems by, in
addition to the normal suspend/resume process, having some platform code
that (almost) blindly saves & restores a bunch of ASIC regs on late
suspend/early resume. It ends up being faster and simpler than going
through convolutions of suspend/resume callbacks left and right that
need to happen in the right order.

Cheers,
Ben.




From kmpark at infradead.org  Wed Jun 16 19:42:22 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Thu, 17 Jun 2010 08:42:22 +0900
Subject: [PATCH 2/5] [ARM] add address randomization to mmap()
In-Reply-To: <1276720403-27918-3-git-send-email-nico@fluxnic.net>
References: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
	<1276720403-27918-3-git-send-email-nico@fluxnic.net>
Message-ID: <AANLkTimXn525QZosUxSsd1SM2JUDxWTfBqHoM1kxz86_@mail.gmail.com>

Hi,

On Thu, Jun 17, 2010 at 5:33 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
> ---
> ?arch/arm/mm/mmap.c | ? ?4 ++++
> ?1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
> index f5abc51..4f5b396 100644
> --- a/arch/arm/mm/mmap.c
> +++ b/arch/arm/mm/mmap.c
> @@ -7,6 +7,7 @@
> ?#include <linux/shm.h>
> ?#include <linux/sched.h>
> ?#include <linux/io.h>
> +#include <linux/random.h>
> ?#include <asm/cputype.h>
> ?#include <asm/system.h>
>
> @@ -80,6 +81,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
> ? ? ? ? ? ? ? ?start_addr = addr = TASK_UNMAPPED_BASE;
> ? ? ? ? ? ? ? ?mm->cached_hole_size = 0;
> ? ? ? ?}
> + ? ? ? /* 8 bits of randomness in 20 address space bits */
> + ? ? ? if (current->flags & PF_RANDOMIZE)
> + ? ? ? ? ? ? ? addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT;

Doesn't better to use mask operation?
                   addr += (get_random_int() & ((1 << 8) - 1)) << PAGE_SHIFT;

Thank you,
Kyungmin Park
>
> ?full_search:
> ? ? ? ?if (do_align)
> --
> 1.7.1.337.gbd0bc
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From nico at fluxnic.net  Wed Jun 16 20:05:24 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 16 Jun 2010 20:05:24 -0400 (EDT)
Subject: [PATCH 2/5] [ARM] add address randomization to mmap()
In-Reply-To: <AANLkTimXn525QZosUxSsd1SM2JUDxWTfBqHoM1kxz86_@mail.gmail.com>
References: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
	<1276720403-27918-3-git-send-email-nico@fluxnic.net>
	<AANLkTimXn525QZosUxSsd1SM2JUDxWTfBqHoM1kxz86_@mail.gmail.com>
Message-ID: <alpine.LFD.2.00.1006161959580.13427@xanadu.home>

On Thu, 17 Jun 2010, Kyungmin Park wrote:

> Hi,
> 
> On Thu, Jun 17, 2010 at 5:33 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> > Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
> > ---
> > ?arch/arm/mm/mmap.c | ? ?4 ++++
> > ?1 files changed, 4 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
> > index f5abc51..4f5b396 100644
> > --- a/arch/arm/mm/mmap.c
> > +++ b/arch/arm/mm/mmap.c
> > @@ -7,6 +7,7 @@
> > ?#include <linux/shm.h>
> > ?#include <linux/sched.h>
> > ?#include <linux/io.h>
> > +#include <linux/random.h>
> > ?#include <asm/cputype.h>
> > ?#include <asm/system.h>
> >
> > @@ -80,6 +81,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
> > ? ? ? ? ? ? ? ?start_addr = addr = TASK_UNMAPPED_BASE;
> > ? ? ? ? ? ? ? ?mm->cached_hole_size = 0;
> > ? ? ? ?}
> > + ? ? ? /* 8 bits of randomness in 20 address space bits */
> > + ? ? ? if (current->flags & PF_RANDOMIZE)
> > + ? ? ? ? ? ? ? addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT;
> 
> Doesn't better to use mask operation?
>                    addr += (get_random_int() & ((1 << 8) - 1)) << PAGE_SHIFT;

GCC is smart enough to optimize the modulus into a mask, effectively 
generating the exact same assembly code in both cases.


Nicolas

From kmpark at infradead.org  Wed Jun 16 20:25:41 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Thu, 17 Jun 2010 09:25:41 +0900
Subject: [PATCH 2/5] [ARM] add address randomization to mmap()
In-Reply-To: <alpine.LFD.2.00.1006161959580.13427@xanadu.home>
References: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
	<1276720403-27918-3-git-send-email-nico@fluxnic.net>
	<AANLkTimXn525QZosUxSsd1SM2JUDxWTfBqHoM1kxz86_@mail.gmail.com>
	<alpine.LFD.2.00.1006161959580.13427@xanadu.home>
Message-ID: <AANLkTinVxE_fiq3_ZLInRTbNKeI-k-07v9x3l73UhWji@mail.gmail.com>

On Thu, Jun 17, 2010 at 9:05 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Thu, 17 Jun 2010, Kyungmin Park wrote:
>
>> Hi,
>>
>> On Thu, Jun 17, 2010 at 5:33 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
>> > Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
>> > ---
>> > ?arch/arm/mm/mmap.c | ? ?4 ++++
>> > ?1 files changed, 4 insertions(+), 0 deletions(-)
>> >
>> > diff --git a/arch/arm/mm/mmap.c b/arch/arm/mm/mmap.c
>> > index f5abc51..4f5b396 100644
>> > --- a/arch/arm/mm/mmap.c
>> > +++ b/arch/arm/mm/mmap.c
>> > @@ -7,6 +7,7 @@
>> > ?#include <linux/shm.h>
>> > ?#include <linux/sched.h>
>> > ?#include <linux/io.h>
>> > +#include <linux/random.h>
>> > ?#include <asm/cputype.h>
>> > ?#include <asm/system.h>
>> >
>> > @@ -80,6 +81,9 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
>> > ? ? ? ? ? ? ? ?start_addr = addr = TASK_UNMAPPED_BASE;
>> > ? ? ? ? ? ? ? ?mm->cached_hole_size = 0;
>> > ? ? ? ?}
>> > + ? ? ? /* 8 bits of randomness in 20 address space bits */
>> > + ? ? ? if (current->flags & PF_RANDOMIZE)
>> > + ? ? ? ? ? ? ? addr += (get_random_int() % (1 << 8)) << PAGE_SHIFT;
>>
>> Doesn't better to use mask operation?
>> ? ? ? ? ? ? ? ? ? ?addr += (get_random_int() & ((1 << 8) - 1)) << PAGE_SHIFT;
>
> GCC is smart enough to optimize the modulus into a mask, effectively
> generating the exact same assembly code in both cases.
>

Right, Good to know

  1c:   e0822003        add     r2, r2, r3
  20:   e20220ff        and     r2, r2, #255    ; 0xff

Thank you,
Kyungmin Park


From davem at davemloft.net  Wed Jun 16 21:03:41 2010
From: davem at davemloft.net (David Miller)
Date: Wed, 16 Jun 2010 18:03:41 -0700 (PDT)
Subject: [PATCH 04/12] phylib: add a way to make PHY time stamps possible.
In-Reply-To: <27c0ad283f025c2bb71e7ceb71be07f969939429.1276615626.git.richard.cochran@omicron.at>
References: <cover.1276615626.git.richard.cochran@omicron.at>
	<27c0ad283f025c2bb71e7ceb71be07f969939429.1276615626.git.richard.cochran@omicron.at>
Message-ID: <20100616.180341.242128217.davem@davemloft.net>

From: Richard Cochran <richardcochran at gmail.com>
Date: Tue, 15 Jun 2010 18:08:20 +0200

> +static inline void skb_tx_timetamp(struct phy_device *phy, struct sk_buff *skb)
> +{
> +	union skb_shared_tx *shtx = skb_tx(skb);
> +
> +	if (shtx->hardware && phy && phy->drv->txtstamp)
> +		phy->drv->txtstamp(phy, skb);
> +
> +	if (shtx->software && !shtx->in_progress)
> +		skb_tstamp_tx(skb, NULL);
> +}
> +
> +static inline void skb_rx_timetamp(struct phy_device *phy, struct sk_buff *skb)
> +{
> +	if (phy && phy->drv->rxtstamp)
> +		phy->drv->rxtstamp(phy, skb);
> +}

Since, as you say, this can provide a way to deal with the sw TX
timestamping sequencing problem we have right now, I'd rather
you implement this from the inside out instead of from the
outside in.

By this I mean you should provide these inline helpers by default
then we can begin to put them into the drivers.

You could also split the SW tstamp handling into a seperate inline
function, which drivers call immediately once they know they will
actually give the packet to the hardware for sending.


From eric.y.miao at gmail.com  Wed Jun 16 23:18:40 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Thu, 17 Jun 2010 11:18:40 +0800
Subject: [PATCH] MAINTAINERS: Change BCMRING maintainer
In-Reply-To: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E57D@SJEXCHCCR02.corp.ad.broadcom.com>
References: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E3F7@SJEXCHCCR02.corp.ad.broadcom.com>
	<AANLkTil6o6tHQdDM0YQRgxme3VLVuk8HUOzqscxsBQBi@mail.gmail.com> 
	<1276655981.1586.172.camel@Joe-Laptop.home>
	<AANLkTilI2toj42vZcHzPC4ru82CDMf2UWsTasPyOD3Nh@mail.gmail.com> 
	<8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E57D@SJEXCHCCR02.corp.ad.broadcom.com>
Message-ID: <AANLkTink0mz5pS-QE0v7-_xXl_SXhY_Bx9ZH0PGUlUiz@mail.gmail.com>

On Thu, Jun 17, 2010 at 12:49 AM, JD (Jiandong) Zheng
<jdzheng at broadcom.com> wrote:
> Hi Eric and Joe,
>
> It is true that I didn't contribute to kernel directly using my company's email address. My company wants to have an engineer to be the contact point and submit patch for BCMRING code and as Leo is not longer with our company I took over this responsibility from him so that any BCMRING maintenance issue or question will be directed to me firstly in Broadcom.
>

Now we know the story :-) Welcome.

> I'd say I am new as a *direct* kernel contributor and I have a lot to learn. I understand I need to show some credits by submitting patches, etc. and I will.
>

Guess the first rule is wrap your line to less than 80 characters since
that really improves readability, and there are a lot geeks out there
using console based email clients :-)


From benjamin.zores at alcatel-lucent.com  Thu Jun 17 02:45:29 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Thu, 17 Jun 2010 08:45:29 +0200
Subject: Request review of device tree documentation
In-Reply-To: <4C190D50.2010501@am.sony.com>
References: <4C13430B.5000907@firmworks.com>	<1276339529.1962.184.camel@pasglop>	<1276339684.1962.186.camel@pasglop>	<4C13B618.1030006@firmworks.com>	<1276383132.1962.195.camel@pasglop>	<AANLkTimRV8u3gDNCAIlROJoPcKs7jFwj2na3ZDFOg3O0@mail.gmail.com>	<4C146F18.9030008@firmworks.com>	<AANLkTikls3hjXOmKFqG2D_9GaJSjOXNuuRXPlanAjo5E@mail.gmail.com>	<20100614124438.GF9323@yookeroo>	<alpine.LFD.2.00.1006141044510.13427@xanadu.home>	<20100614160201.GD9550@shareable.org>	<4C165FD1.6080505@firmworks.com>	<4C186AA8.4040709@compulab.co.il>	<4C186B7B.1060308@firmworks.com>	<4C186C72.2020506@compulab.co.il>	<4C187013.5000400@firmworks.com>	<4C18738C.4090809@compulab.co.il>	<4C187FF0.5020806@firmworks.com>	<4C18A9C7.5070800@compulab.co.il>	<alpine.LFD.2.00.1006160917390.13427@xanadu.home>
	<4C190D50.2010501@am.sony.com>
Message-ID: <4C19C489.1010008@alcatel-lucent.com>

On 16/06/2010 19:43, Tim Bird wrote:
> On 06/16/2010 07:39 AM, Nicolas Pitre wrote:
>    
>> The cost function _is_ different for the Linux community and decision
>> makers at chip vendor companies. I know that for having worked long
>> enough at a prominent chip vendor already.
>>
>> Those vendors want to ship a product and be first on the market before
>> the competitors do.  They grab a kernel tree, fit in their existing HAL
>> as quickly as they can, so that they are able to demo the new chip to
>> potential customers even before moving to full production.  And if the
>> HAL fitting work has been done into last year's kernel already, then
>> they will simply reuse that kernel to minimize the effort further as in
>> theory only the HAL part needs to be swapped with the new one (doesn't
>> matter if last year's kernel was itself already based on a kernel from
>> the year before).  Once the software appears to work, they send it to
>> customers and forget about it as they move to the next chip design.  So
>> here, the cost is directly related to bring-up time, and quick (or big)
>> ugly software hacks are more than a convenience but rather a necessity
>> if you want to win the race.
>>
>> People from the Linux community care about totally different things. The
>> most important factor here is _long term_ maintainability.  It is
>> important that the code be clean, use a uniform coding style, and follow
>> common interfaces.  This is so because the cost function here is
>> directly related to the difficulty for the Linux community to evolve the
>> kernel with generic improvements and new features.  If each driver has a
>> different style, or rely on a different HAL, then it quickly becomes
>> extremely expensive to update those drivers along with the generic
>> improvements.  And if the HAL is in binary form only, or stuck behind
>> some unalterable BIOS-like calls or firmware API, then it may even be
>> impossible to update those drivers as the execution context assumed by
>> the HAL firmware may not be guaranteed anymore (think about UP vs SMP,
>> different preemption modes, different realtime kernel modes, etc.)  And
>> of course it is impossible to anticipate what execution context and
>> requirements the kernel might need in the future, hence this can't be
>> provisioned for (and much less validated) into the HAL design in advance
>> (and see above why it is next to hopeless to expect vendors to update
>> their HAL for old products in a timely fashion).
>>
>> So there *is* indeed a big difference between both points of view.  And
>> sometimes the imperatives from each group are in total conflict.
>>      
> This is absolutely correct.  At the CE Linux Forum, we've been working
> for years to try to get vendors more involved in the community, with
> a variety of techniques, including white papers for management,
> magazine articles, outreach at industry events, and hosting our
> own events to introduce "industry" and "community" developers.
>    

Which they somehow do more and more.

I second Nicolas' theory (for having worked with his previous employer 
he's talking about but also others)
and it's true that chip vendors usually want to have their chip 
supported in a BSP ASAP
whatever the code looks like or how easy/hard it may be to use it for a 
customized board.

Though, more and more are now duplicating efforts, having 2 kernel 
development teams: one doing BSP
and one trying to push code in upstream Linux, conforming to the 
expected level of quality and maintainability.

While it's true that having this second team doing so is fully welcomed, 
one has to say that most of the times
there are no communication between these teams in the same company, 
people redoing the same mistakes
(or having to fix the same bugs) twice.

Ben





From benjamin.zores at alcatel-lucent.com  Thu Jun 17 02:58:38 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Thu, 17 Jun 2010 08:58:38 +0200
Subject: [PATCH 3/4] arch/arm/mach-kirkwood: add support for 2nd PCIe
	port 	on 88f6282.
In-Reply-To: <AANLkTikRdFDxwQskaCz6ScATh8WHUFN4XwLIyqJ_1U1k@mail.gmail.com>
References: <20100610135936.14097.22635.stgit@localhost.localdomain>	<20100610135946.14097.39894.stgit@localhost.localdomain>
	<AANLkTikRdFDxwQskaCz6ScATh8WHUFN4XwLIyqJ_1U1k@mail.gmail.com>
Message-ID: <4C19C79E.7020903@alcatel-lucent.com>

On 10/06/2010 17:29, saeed bishara wrote:
>
> you didn't updated the comment the describes the address map.
> also, I suggest you to take this part from the patch I sent, in that
> patch I made sure to make the pcie1 IO physical and virtual address
> consecutive to pcie0, I think without this the IO access to pcie1 will
> not work. please see the __io() macro at
> mach-kirkwood/include/mach/io.h
>    

Will do.

>>      
> you're still using the pcie_port global structure. the patch I sent
> removed it,  can you take this part (changes to kirkwood/pcie.c) from
> my patch?
>    

I removed these parts of your patch because PCIe was no longer working 
on my board with this approach.
I took the same one that was used in mach-mv78xx0.

Ben


From benjamin.zores at alcatel-lucent.com  Thu Jun 17 03:58:52 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Thu, 17 Jun 2010 09:58:52 +0200
Subject: [PATCH 0/4] Series short description
Message-ID: <20100617075711.15387.69398.stgit@localhost.localdomain>

The following series implements support for Marvell 88F6282 SoC.
It should take into account all previously made comments.

---

Benjamin Zores (4):
      arch/arm/mach-kirkwood: update MPP definition.
      arch/arm/mach-kirkwood: add support for 88F6282-A0 revision
      arch/arm/mach-kirkwood: add support for 2nd PCIe port on 88f6282.
      arch/arm/mach-kirkwood: add support for 2nd TWSI controller on 88f6282.


 arch/arm/mach-kirkwood/addr-map.c                 |   21 +
 arch/arm/mach-kirkwood/common.c                   |   90 +++
 arch/arm/mach-kirkwood/common.h                   |   10 
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c       |    2 
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h |    3 
 arch/arm/mach-kirkwood/include/mach/irqs.h        |    4 
 arch/arm/mach-kirkwood/include/mach/kirkwood.h    |   43 +-
 arch/arm/mach-kirkwood/mpp.c                      |    2 
 arch/arm/mach-kirkwood/mpp.h                      |  595 +++++++++++----------
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c    |    2 
 arch/arm/mach-kirkwood/netspace_v2-setup.c        |    6 
 arch/arm/mach-kirkwood/netxbig_v2-setup.c         |   34 +
 arch/arm/mach-kirkwood/openrd-setup.c             |    4 
 arch/arm/mach-kirkwood/pcie.c                     |  204 +++++--
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c      |    2 
 arch/arm/mach-kirkwood/rd88f6281-setup.c          |    2 
 arch/arm/mach-kirkwood/ts219-setup.c              |    8 
 arch/arm/mach-kirkwood/ts41x-setup.c              |   32 +
 18 files changed, 663 insertions(+), 401 deletions(-)

-- 
Signature


From benjamin.zores at alcatel-lucent.com  Thu Jun 17 03:58:58 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Thu, 17 Jun 2010 09:58:58 +0200
Subject: [PATCH 1/4] arch/arm/mach-kirkwood: update MPP definition.
In-Reply-To: <20100617075711.15387.69398.stgit@localhost.localdomain>
References: <20100617075711.15387.69398.stgit@localhost.localdomain>
Message-ID: <20100617075858.15387.93749.stgit@localhost.localdomain>

Add MPP definitions for Marvell Kirkwood 88F6282 revision.
Update some defines to reflect datasheet's MPP names.

Signed-off-by: Benjamin Zores <benjamin.zores at alcatel-lucent.com>
---
 arch/arm/mach-kirkwood/mpp.h               |  595 +++++++++++++++-------------
 arch/arm/mach-kirkwood/netspace_v2-setup.c |    4 
 arch/arm/mach-kirkwood/netxbig_v2-setup.c  |   32 +-
 arch/arm/mach-kirkwood/ts219-setup.c       |    4 
 arch/arm/mach-kirkwood/ts41x-setup.c       |   28 +
 5 files changed, 356 insertions(+), 307 deletions(-)

diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index bc74278..51a2974 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -11,7 +11,7 @@
 #ifndef __KIRKWOOD_MPP_H
 #define __KIRKWOOD_MPP_H
 
-#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281) ( \
+#define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \
 	/* MPP number */		((_num) & 0xff) | \
 	/* MPP select value */		(((_sel) & 0xf) << 8) | \
 	/* may be input signal */	((!!(_in)) << 12) | \
@@ -19,282 +19,331 @@
 	/* available on F6180 */	((!!(_F6180)) << 14) | \
 	/* available on F6190 */	((!!(_F6190)) << 15) | \
 	/* available on F6192 */	((!!(_F6192)) << 16) | \
-	/* available on F6281 */	((!!(_F6281)) << 17))
+	/* available on F6281 */	((!!(_F6281)) << 17) | \
+	/* available on F6282 */	((!!(_F6282)) << 18))
 
 #define MPP_NUM(x)	((x) & 0xff)
 #define MPP_SEL(x)	(((x) >> 8) & 0xf)
 
-				/*   num sel  i  o  6180 6190 6192 6281 */
-
-#define MPP_INPUT_MASK		MPP(  0, 0x0, 1, 0, 0,   0,   0,   0    )
-#define MPP_OUTPUT_MASK		MPP(  0, 0x0, 0, 1, 0,   0,   0,   0    )
-
-#define MPP_F6180_MASK		MPP(  0, 0x0, 0, 0, 1,   0,   0,   0    )
-#define MPP_F6190_MASK		MPP(  0, 0x0, 0, 0, 0,   1,   0,   0    )
-#define MPP_F6192_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   1,   0    )
-#define MPP_F6281_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   0,   1    )
-
-#define MPP0_GPIO		MPP(  0, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP0_NF_IO2		MPP(  0, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP0_SPI_SCn		MPP(  0, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP1_GPO		MPP(  1, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP1_NF_IO3		MPP(  1, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP1_SPI_MOSI		MPP(  1, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP2_GPO		MPP(  2, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP2_NF_IO4		MPP(  2, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP2_SPI_SCK		MPP(  2, 0x2, 0, 1, 1,   1,   1,   1    )
-
-#define MPP3_GPO		MPP(  3, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP3_NF_IO5		MPP(  3, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP3_SPI_MISO		MPP(  3, 0x2, 1, 0, 1,   1,   1,   1    )
-
-#define MPP4_GPIO		MPP(  4, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP4_NF_IO6		MPP(  4, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP4_UART0_RXD		MPP(  4, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP4_SATA1_ACTn		MPP(  4, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP4_PTP_CLK		MPP(  4, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP5_GPO		MPP(  5, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP5_NF_IO7		MPP(  5, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP5_UART0_TXD		MPP(  5, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP5_PTP_TRIG_GEN	MPP(  5, 0x4, 0, 1, 1,   1,   1,   1    )
-#define MPP5_SATA0_ACTn		MPP(  5, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP6_SYSRST_OUTn	MPP(  6, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP6_SPI_MOSI		MPP(  6, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP6_PTP_TRIG_GEN	MPP(  6, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP7_GPO		MPP(  7, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PEX_RST_OUTn	MPP(  7, 0x1, 0, 1, 1,   1,   1,   1    )
-#define MPP7_SPI_SCn		MPP(  7, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP7_PTP_TRIG_GEN	MPP(  7, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP8_GPIO		MPP(  8, 0x0, 1, 1, 1,    1,  1,   1    )
-#define MPP8_TW_SDA		MPP(  8, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP8_UART0_RTS		MPP(  8, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP8_UART1_RTS		MPP(  8, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP8_MII0_RXERR		MPP(  8, 0x4, 1, 0, 0,   1,   1,   1    )
-#define MPP8_SATA1_PRESENTn	MPP(  8, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP8_PTP_CLK		MPP(  8, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP8_MII0_COL		MPP(  8, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP9_GPIO		MPP(  9, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP9_TW_SCK		MPP(  9, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP9_UART0_CTS		MPP(  9, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP9_UART1_CTS		MPP(  9, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP9_SATA0_PRESENTn	MPP(  9, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP9_PTP_EVENT_REQ	MPP(  9, 0xc, 1, 0, 1,   1,   1,   1    )
-#define MPP9_MII0_CRS		MPP(  9, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP10_GPO		MPP( 10, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SPI_SCK		MPP( 10, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP10_UART0_TXD		MPP( 10, 0X3, 0, 1, 1,   1,   1,   1    )
-#define MPP10_SATA1_ACTn	MPP( 10, 0x5, 0, 1, 0,   0,   1,   1    )
-#define MPP10_PTP_TRIG_GEN	MPP( 10, 0xc, 0, 1, 1,   1,   1,   1    )
-
-#define MPP11_GPIO		MPP( 11, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP11_SPI_MISO		MPP( 11, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP11_UART0_RXD		MPP( 11, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_EVENT_REQ	MPP( 11, 0x4, 1, 0, 1,   1,   1,   1    )
-#define MPP11_PTP_TRIG_GEN	MPP( 11, 0xc, 0, 1, 1,   1,   1,   1    )
-#define MPP11_PTP_CLK		MPP( 11, 0xd, 1, 0, 1,   1,   1,   1    )
-#define MPP11_SATA0_ACTn	MPP( 11, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP12_GPO		MPP( 12, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP12_SD_CLK		MPP( 12, 0x1, 0, 1, 1,   1,   1,   1    )
-
-#define MPP13_GPIO		MPP( 13, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP13_SD_CMD		MPP( 13, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP13_UART1_TXD		MPP( 13, 0x3, 0, 1, 1,   1,   1,   1    )
-
-#define MPP14_GPIO		MPP( 14, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP14_SD_D0		MPP( 14, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP14_UART1_RXD		MPP( 14, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP14_SATA1_PRESENTn	MPP( 14, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP14_MII0_COL		MPP( 14, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP15_GPIO		MPP( 15, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP15_SD_D1		MPP( 15, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP15_UART0_RTS		MPP( 15, 0x2, 0, 1, 1,   1,   1,   1    )
-#define MPP15_UART1_TXD		MPP( 15, 0x3, 0, 1, 1,   1,   1,   1    )
-#define MPP15_SATA0_ACTn	MPP( 15, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP16_GPIO		MPP( 16, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP16_SD_D2		MPP( 16, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP16_UART0_CTS		MPP( 16, 0x2, 1, 0, 1,   1,   1,   1    )
-#define MPP16_UART1_RXD		MPP( 16, 0x3, 1, 0, 1,   1,   1,   1    )
-#define MPP16_SATA1_ACTn	MPP( 16, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP16_MII0_CRS		MPP( 16, 0xd, 1, 0, 1,   1,   1,   1    )
-
-#define MPP17_GPIO		MPP( 17, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SD_D3		MPP( 17, 0x1, 1, 1, 1,   1,   1,   1    )
-#define MPP17_SATA0_PRESENTn	MPP( 17, 0x4, 0, 1, 0,   1,   1,   1    )
-
-#define MPP18_GPO		MPP( 18, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP18_NF_IO0		MPP( 18, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP19_GPO		MPP( 19, 0x0, 0, 1, 1,   1,   1,   1    )
-#define MPP19_NF_IO1		MPP( 19, 0x1, 1, 1, 1,   1,   1,   1    )
-
-#define MPP20_GPIO		MPP( 20, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP20_TSMP0		MPP( 20, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP20_TDM_CH0_TX_QL	MPP( 20, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP20_GE1_0		MPP( 20, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP20_AUDIO_SPDIFI	MPP( 20, 0x4, 1, 0, 0,   0,   1,   1    )
-#define MPP20_SATA1_ACTn	MPP( 20, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP21_GPIO		MPP( 21, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP21_TSMP1		MPP( 21, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP21_TDM_CH0_RX_QL	MPP( 21, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP21_GE1_1		MPP( 21, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP21_AUDIO_SPDIFO	MPP( 21, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP21_SATA0_ACTn	MPP( 21, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP22_GPIO		MPP( 22, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP22_TSMP2		MPP( 22, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP22_TDM_CH2_TX_QL	MPP( 22, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP22_GE1_2		MPP( 22, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP22_AUDIO_SPDIFRMKCLK	MPP( 22, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP22_SATA1_PRESENTn	MPP( 22, 0x5, 0, 1, 0,   0,   1,   1    )
-
-#define MPP23_GPIO		MPP( 23, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP23_TSMP3		MPP( 23, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP23_TDM_CH2_RX_QL	MPP( 23, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP23_GE1_3		MPP( 23, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP23_AUDIO_I2SBCLK	MPP( 23, 0x4, 0, 1, 0,   0,   1,   1    )
-#define MPP23_SATA0_PRESENTn	MPP( 23, 0x5, 0, 1, 0,   1,   1,   1    )
-
-#define MPP24_GPIO		MPP( 24, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP24_TSMP4		MPP( 24, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP24_TDM_SPI_CS0	DEV( 24, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP24_GE1_4		MPP( 24, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP24_AUDIO_I2SDO	MPP( 24, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP25_GPIO		MPP( 25, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP25_TSMP5		MPP( 25, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP25_TDM_SPI_SCK	MPP( 25, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP25_GE1_5		MPP( 25, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP25_AUDIO_I2SLRCLK	MPP( 25, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP26_GPIO		MPP( 26, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP26_TSMP6		MPP( 26, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP26_TDM_SPI_MISO	MPP( 26, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP26_GE1_6		MPP( 26, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP26_AUDIO_I2SMCLK	MPP( 26, 0x4, 0, 1, 0,   0,   1,   1    )
-
-#define MPP27_GPIO		MPP( 27, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP27_TSMP7		MPP( 27, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP27_TDM_SPI_MOSI	MPP( 27, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP27_GE1_7		MPP( 27, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP27_AUDIO_I2SDI	MPP( 27, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP28_GPIO		MPP( 28, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP28_TSMP8		MPP( 28, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP28_TDM_CODEC_INTn	MPP( 28, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP28_GE1_8		MPP( 28, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP28_AUDIO_EXTCLK	MPP( 28, 0x4, 1, 0, 0,   0,   1,   1    )
-
-#define MPP29_GPIO		MPP( 29, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP29_TSMP9		MPP( 29, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP29_TDM_CODEC_RSTn	MPP( 29, 0x2, 0, 0, 0,   0,   1,   1    )
-#define MPP29_GE1_9		MPP( 29, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP30_GPIO		MPP( 30, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP30_TSMP10		MPP( 30, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP30_TDM_PCLK		MPP( 30, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP30_GE1_10		MPP( 30, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP31_GPIO		MPP( 31, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP31_TSMP11		MPP( 31, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP31_TDM_FS		MPP( 31, 0x2, 1, 1, 0,   0,   1,   1    )
-#define MPP31_GE1_11		MPP( 31, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP32_GPIO		MPP( 32, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP32_TSMP12		MPP( 32, 0x1, 1, 1, 0,   0,   1,   1    )
-#define MPP32_TDM_DRX		MPP( 32, 0x2, 1, 0, 0,   0,   1,   1    )
-#define MPP32_GE1_12		MPP( 32, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP33_GPIO		MPP( 33, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP33_TDM_DTX		MPP( 33, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP33_GE1_13		MPP( 33, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP34_GPIO		MPP( 34, 0x0, 1, 1, 0,   1,   1,   1    )
-#define MPP34_TDM_SPI_CS1	MPP( 34, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP34_GE1_14		MPP( 34, 0x3, 0, 0, 0,   1,   1,   1    )
-
-#define MPP35_GPIO		MPP( 35, 0x0, 1, 1, 1,   1,   1,   1    )
-#define MPP35_TDM_CH0_TX_QL	MPP( 35, 0x2, 0, 1, 0,   0,   1,   1    )
-#define MPP35_GE1_15		MPP( 35, 0x3, 0, 0, 0,   1,   1,   1    )
-#define MPP35_SATA0_ACTn	MPP( 35, 0x5, 0, 1, 0,   1,   1,   1    )
-#define MPP35_MII0_RXERR	MPP( 35, 0xc, 1, 0, 1,   1,   1,   1    )
-
-#define MPP36_GPIO		MPP( 36, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP36_TSMP0		MPP( 36, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP36_TDM_SPI_CS1	MPP( 36, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP36_AUDIO_SPDIFI	MPP( 36, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP37_GPIO		MPP( 37, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP37_TSMP1		MPP( 37, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP37_TDM_CH2_TX_QL	MPP( 37, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP37_AUDIO_SPDIFO	MPP( 37, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP38_GPIO		MPP( 38, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP38_TSMP2		MPP( 38, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP38_TDM_CH2_RX_QL	MPP( 38, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP38_AUDIO_SPDIFRMLCLK	MPP( 38, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP39_GPIO		MPP( 39, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP39_TSMP3		MPP( 39, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP39_TDM_SPI_CS0	MPP( 39, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP39_AUDIO_I2SBCLK	MPP( 39, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP40_GPIO		MPP( 40, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP40_TSMP4		MPP( 40, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP40_TDM_SPI_SCK	MPP( 40, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP40_AUDIO_I2SDO	MPP( 40, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP41_GPIO		MPP( 41, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP41_TSMP5		MPP( 41, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP41_TDM_SPI_MISO	MPP( 41, 0x2, 1, 0, 0,   0,   0,   1    )
-#define MPP41_AUDIO_I2SLRC	MPP( 41, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP42_GPIO		MPP( 42, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP42_TSMP6		MPP( 42, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP42_TDM_SPI_MOSI	MPP( 42, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP42_AUDIO_I2SMCLK	MPP( 42, 0x4, 0, 1, 1,   0,   0,   1    )
-
-#define MPP43_GPIO		MPP( 43, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP43_TSMP7		MPP( 43, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP43_TDM_CODEC_INTn	MPP( 43, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP43_AUDIO_I2SDI	MPP( 43, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP44_GPIO		MPP( 44, 0x0, 1, 1, 1,   0,   0,   1    )
-#define MPP44_TSMP8		MPP( 44, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP44_TDM_CODEC_RSTn	MPP( 44, 0x2, 0, 0, 0,   0,   0,   1    )
-#define MPP44_AUDIO_EXTCLK	MPP( 44, 0x4, 1, 0, 1,   0,   0,   1    )
-
-#define MPP45_GPIO		MPP( 45, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TSMP9		MPP( 45, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP45_TDM_PCLK		MPP( 45, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP46_GPIO		MPP( 46, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TSMP10		MPP( 46, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP46_TDM_FS		MPP( 46, 0x2, 1, 1, 0,   0,   0,   1    )
-
-#define MPP47_GPIO		MPP( 47, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TSMP11		MPP( 47, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP47_TDM_DRX		MPP( 47, 0x2, 1, 0, 0,   0,   0,   1    )
-
-#define MPP48_GPIO		MPP( 48, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TSMP12		MPP( 48, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP48_TDM_DTX		MPP( 48, 0x2, 0, 1, 0,   0,   0,   1    )
-
-#define MPP49_GPIO		MPP( 49, 0x0, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TSMP9		MPP( 49, 0x1, 1, 1, 0,   0,   0,   1    )
-#define MPP49_TDM_CH0_RX_QL	MPP( 49, 0x2, 0, 1, 0,   0,   0,   1    )
-#define MPP49_PTP_CLK		MPP( 49, 0x5, 1, 0, 0,   0,   0,   1    )
+				/*   num sel  i  o  6180 6190 6192 6281 6282 */
+
+#define MPP_INPUT_MASK		MPP(  0, 0x0, 1, 0, 0,   0,   0,   0,   0 )
+#define MPP_OUTPUT_MASK		MPP(  0, 0x0, 0, 1, 0,   0,   0,   0,   0 )
+
+#define MPP_F6180_MASK		MPP(  0, 0x0, 0, 0, 1,   0,   0,   0,   0 )
+#define MPP_F6190_MASK		MPP(  0, 0x0, 0, 0, 0,   1,   0,   0,   0 )
+#define MPP_F6192_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   1,   0,   0 )
+#define MPP_F6281_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   0,   1,   0 )
+#define MPP_F6282_MASK		MPP(  0, 0x0, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP0_GPIO		MPP(  0, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP0_NF_IO2		MPP(  0, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP0_SPI_SCn		MPP(  0, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP1_GPO		MPP(  1, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP1_NF_IO3		MPP(  1, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP1_SPI_MOSI		MPP(  1, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP2_GPO		MPP(  2, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP2_NF_IO4		MPP(  2, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP2_SPI_SCK		MPP(  2, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+
+#define MPP3_GPO		MPP(  3, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP3_NF_IO5		MPP(  3, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP3_SPI_MISO		MPP(  3, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP4_GPIO		MPP(  4, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP4_NF_IO6		MPP(  4, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP4_UART0_RXD		MPP(  4, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP4_SATA1_ACTn		MPP(  4, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP4_LCD_VGA_HSYNC	MPP(  4, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+#define MPP4_PTP_CLK		MPP(  4, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+
+#define MPP5_GPO		MPP(  5, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP5_NF_IO7		MPP(  5, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP5_UART0_TXD		MPP(  5, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP5_PTP_TRIG_GEN	MPP(  5, 0x4, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP5_SATA0_ACTn		MPP(  5, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP5_LCD_VGA_VSYNC	MPP(  5, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP6_SYSRST_OUTn	MPP(  6, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP6_SPI_MOSI		MPP(  6, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP6_PTP_TRIG_GEN	MPP(  6, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+
+#define MPP7_GPO		MPP(  7, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP7_PEX_RST_OUTn	MPP(  7, 0x1, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP7_SPI_SCn		MPP(  7, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP7_PTP_TRIG_GEN	MPP(  7, 0x3, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP7_LCD_PWM		MPP(  7, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP8_GPIO		MPP(  8, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP8_TW0_SDA		MPP(  8, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP8_UART0_RTS		MPP(  8, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP8_UART1_RTS		MPP(  8, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP8_MII0_RXERR		MPP(  8, 0x4, 1, 0, 0,   1,   1,   1,   1 )
+#define MPP8_SATA1_PRESENTn	MPP(  8, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP8_PTP_CLK		MPP(  8, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP8_MII0_COL		MPP(  8, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP9_GPIO		MPP(  9, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP9_TW0_SCK		MPP(  9, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP9_UART0_CTS		MPP(  9, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_UART1_CTS		MPP(  9, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP9_SATA0_PRESENTn	MPP(  9, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP9_PTP_EVENT_REQ	MPP(  9, 0xc, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP9_MII0_CRS		MPP(  9, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP10_GPO		MPP( 10, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_SPI_SCK		MPP( 10, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_UART0_TXD		MPP( 10, 0X3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP10_SATA1_ACTn	MPP( 10, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP10_PTP_TRIG_GEN	MPP( 10, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+
+#define MPP11_GPIO		MPP( 11, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP11_SPI_MISO		MPP( 11, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP11_UART0_RXD		MPP( 11, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP11_PTP_EVENT_REQ	MPP( 11, 0x4, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_TRIG_GEN	MPP( 11, 0xc, 0, 1, 1,   1,   1,   1,   0 )
+#define MPP11_PTP_CLK		MPP( 11, 0xd, 1, 0, 1,   1,   1,   1,   0 )
+#define MPP11_SATA0_ACTn	MPP( 11, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+
+#define MPP12_GPO		MPP( 12, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_SD_CLK		MPP( 12, 0x1, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP12_AU_SPDIF0		MPP( 12, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP12_SPI_MOSI		MPP( 12, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP12_TW1_SDA		MPP( 12, 0xd, 1, 0, 0,   0,   0,   0,   1 )
+
+#define MPP13_GPIO		MPP( 13, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP13_SD_CMD		MPP( 13, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP13_UART1_TXD		MPP( 13, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP13_AU_SPDIFRMCLK	MPP( 13, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP13_LCDPWM		MPP( 13, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP14_GPIO		MPP( 14, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP14_SD_D0		MPP( 14, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP14_UART1_RXD		MPP( 14, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP14_SATA1_PRESENTn	MPP( 14, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP14_AU_SPDIFI		MPP( 14, 0xa, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP14_AU_I2SDI		MPP( 14, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP14_MII0_COL		MPP( 14, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP15_GPIO		MPP( 15, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP15_SD_D1		MPP( 15, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP15_UART0_RTS		MPP( 15, 0x2, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP15_UART1_TXD		MPP( 15, 0x3, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP15_SATA0_ACTn	MPP( 15, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP15_SPI_CSn		MPP( 15, 0xb, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP16_GPIO		MPP( 16, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP16_SD_D2		MPP( 16, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP16_UART0_CTS		MPP( 16, 0x2, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_UART1_RXD		MPP( 16, 0x3, 1, 0, 1,   1,   1,   1,   1 )
+#define MPP16_SATA1_ACTn	MPP( 16, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP16_LCD_EXT_REF_CLK	MPP( 16, 0xb, 1, 0, 0,   0,   0,   0,   1 )
+#define MPP16_MII0_CRS		MPP( 16, 0xd, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP17_GPIO		MPP( 17, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP17_SD_D3		MPP( 17, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP17_SATA0_PRESENTn	MPP( 17, 0x4, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP17_SATA1_ACTn	MPP( 17, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP17_TW1_SCK		MPP( 17, 0xd, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP18_GPO		MPP( 18, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP18_NF_IO0		MPP( 18, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP18_PEX0_CLKREQ	MPP( 18, 0x2, 0, 1, 0,   0,   0,   0,   1 )
+
+#define MPP19_GPO		MPP( 19, 0x0, 0, 1, 1,   1,   1,   1,   1 )
+#define MPP19_NF_IO1		MPP( 19, 0x1, 1, 1, 1,   1,   1,   1,   1 )
+
+#define MPP20_GPIO		MPP( 20, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP20_TSMP0		MPP( 20, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP20_TDM_CH0_TX_QL	MPP( 20, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP20_GE1_TXD0		MPP( 20, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP20_AU_SPDIFI		MPP( 20, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP20_SATA1_ACTn	MPP( 20, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP20_LCD_D0		MPP( 20, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP21_GPIO		MPP( 21, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP21_TSMP1		MPP( 21, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP21_TDM_CH0_RX_QL	MPP( 21, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP21_GE1_TXD1		MPP( 21, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP21_AU_SPDIFO		MPP( 21, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP21_SATA0_ACTn	MPP( 21, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP21_LCD_D1		MPP( 21, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP22_GPIO		MPP( 22, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP22_TSMP2		MPP( 22, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP22_TDM_CH2_TX_QL	MPP( 22, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_GE1_TXD2		MPP( 22, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP22_AU_SPDIFRMKCLK	MPP( 22, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_SATA1_PRESENTn	MPP( 22, 0x5, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP22_LCD_D2		MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP23_GPIO		MPP( 23, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP23_TSMP3		MPP( 23, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP23_TDM_CH2_RX_QL	MPP( 23, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP23_GE1_TXD3		MPP( 23, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP23_AU_I2SBCLK	MPP( 23, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP23_SATA0_PRESENTn	MPP( 23, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP23_LCD_D3		MPP( 23, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP24_GPIO		MPP( 24, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP24_TSMP4		MPP( 24, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP24_TDM_SPI_CS0	MPP( 24, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP24_GE1_RXD0		MPP( 24, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP24_AU_I2SDO		MPP( 24, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP24_LCD_D4		MPP( 24, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP25_GPIO		MPP( 25, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP25_TSMP5		MPP( 25, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP25_TDM_SPI_SCK	MPP( 25, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP25_GE1_RXD1		MPP( 25, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP25_AU_I2SLRCLK	MPP( 25, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP25_LCD_D5		MPP( 25, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP26_GPIO		MPP( 26, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP26_TSMP6		MPP( 26, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP26_TDM_SPI_MISO	MPP( 26, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP26_GE1_RXD2		MPP( 26, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP26_AU_I2SMCLK	MPP( 26, 0x4, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP26_LCD_D6		MPP( 26, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP27_GPIO		MPP( 27, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP27_TSMP7		MPP( 27, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP27_TDM_SPI_MOSI	MPP( 27, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP27_GE1_RXD3		MPP( 27, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP27_AU_I2SDI		MPP( 27, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP27_LCD_D7		MPP( 27, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP28_GPIO		MPP( 28, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP28_TSMP8		MPP( 28, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP28_TDM_CODEC_INTn	MPP( 28, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+#define MPP28_GE1_COL		MPP( 28, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP28_AU_EXTCLK		MPP( 28, 0x4, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP28_LCD_D8		MPP( 28, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP29_GPIO		MPP( 29, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP29_TSMP9		MPP( 29, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP29_TDM_CODEC_RSTn	MPP( 29, 0x2, 0, 0, 0,   0,   1,   1,   1 )
+#define MPP29_GE1_TCLK		MPP( 29, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP29_LCD_D9		MPP( 29, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP30_GPIO		MPP( 30, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP30_TSMP10		MPP( 30, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP30_TDM_PCLK		MPP( 30, 0x2, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP30_GE1_RXCTL		MPP( 30, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP30_LCD_D10		MPP( 30, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP31_GPIO		MPP( 31, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP31_TSMP11		MPP( 31, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP31_TDM_FS		MPP( 31, 0x2, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP31_GE1_RXCLK		MPP( 31, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP31_LCD_D11		MPP( 31, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP32_GPIO		MPP( 32, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP32_TSMP12		MPP( 32, 0x1, 1, 1, 0,   0,   1,   1,   1 )
+#define MPP32_TDM_DRX		MPP( 32, 0x2, 1, 0, 0,   0,   1,   1,   1 )
+#define MPP32_GE1_TCLKOUT	MPP( 32, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP32_LCD_D12		MPP( 32, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP33_GPO		MPP( 33, 0x0, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP33_TDM_DTX		MPP( 33, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP33_GE1_TXCTL		MPP( 33, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP33_LCD_D13		MPP( 33, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP34_GPIO		MPP( 34, 0x0, 1, 1, 0,   1,   1,   1,   1 )
+#define MPP34_TDM_SPI_CS1	MPP( 34, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP34_GE1_TXEN		MPP( 34, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP34_SATA1_ACTn	MPP( 34, 0x5, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP34_LCD_D14		MPP( 34, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP35_GPIO		MPP( 35, 0x0, 1, 1, 1,   1,   1,   1,   1 )
+#define MPP35_TDM_CH0_TX_QL	MPP( 35, 0x2, 0, 1, 0,   0,   1,   1,   1 )
+#define MPP35_GE1_RXERR		MPP( 35, 0x3, 0, 0, 0,   1,   1,   1,   1 )
+#define MPP35_SATA0_ACTn	MPP( 35, 0x5, 0, 1, 0,   1,   1,   1,   1 )
+#define MPP35_LCD_D15		MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+#define MPP35_MII0_RXERR	MPP( 35, 0xc, 1, 0, 1,   1,   1,   1,   1 )
+
+#define MPP36_GPIO		MPP( 36, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP36_TSMP0		MPP( 36, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP36_TDM_SPI_CS1	MPP( 36, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP36_AU_SPDIFI		MPP( 36, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP36_TW1_SDA		MPP( 36, 0xb, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP37_GPIO		MPP( 37, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP37_TSMP1		MPP( 37, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP37_TDM_CH2_TX_QL	MPP( 37, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP37_AU_SPDIFO		MPP( 37, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP37_TW1_SCK		MPP( 37, 0xb, 1, 1, 0,   0,   0,   0,   1 )
+
+#define MPP38_GPIO		MPP( 38, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP38_TSMP2		MPP( 38, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP38_TDM_CH2_RX_QL	MPP( 38, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP38_AU_SPDIFRMLCLK	MPP( 38, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP38_LCD_D18		MPP( 38, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP39_GPIO		MPP( 39, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP39_TSMP3		MPP( 39, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP39_TDM_SPI_CS0	MPP( 39, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP39_AU_I2SBCLK	MPP( 39, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP39_LCD_D19		MPP( 39, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP40_GPIO		MPP( 40, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP40_TSMP4		MPP( 40, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP40_TDM_SPI_SCK	MPP( 40, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP40_AU_I2SDO		MPP( 40, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP40_LCD_D20		MPP( 40, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP41_GPIO		MPP( 41, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP41_TSMP5		MPP( 41, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP41_TDM_SPI_MISO	MPP( 41, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+#define MPP41_AU_I2SLRCLK	MPP( 41, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP41_LCD_D21		MPP( 41, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP42_GPIO		MPP( 42, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP42_TSMP6		MPP( 42, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP42_TDM_SPI_MOSI	MPP( 42, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP42_AU_I2SMCLK	MPP( 42, 0x4, 0, 1, 1,   0,   0,   1,   1 )
+#define MPP42_LCD_D22		MPP( 42, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP43_GPIO		MPP( 43, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP43_TSMP7		MPP( 43, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP43_TDM_CODEC_INTn	MPP( 43, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+#define MPP43_AU_I2SDI		MPP( 43, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP43_LCD_D23		MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP44_GPIO		MPP( 44, 0x0, 1, 1, 1,   0,   0,   1,   1 )
+#define MPP44_TSMP8		MPP( 44, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP44_TDM_CODEC_RSTn	MPP( 44, 0x2, 0, 0, 0,   0,   0,   1,   1 )
+#define MPP44_AU_EXTCLK		MPP( 44, 0x4, 1, 0, 1,   0,   0,   1,   1 )
+#define MPP44_LCD_CLK		MPP( 44, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP45_GPIO		MPP( 45, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP45_TSMP9		MPP( 45, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP45_TDM_PCLK		MPP( 45, 0x2, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP245_LCD_E		MPP( 45, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP46_GPIO		MPP( 46, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_TSMP10		MPP( 46, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_TDM_FS		MPP( 46, 0x2, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP46_LCD_HSYNC		MPP( 46, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP47_GPIO		MPP( 47, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP47_TSMP11		MPP( 47, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP47_TDM_DRX		MPP( 47, 0x2, 1, 0, 0,   0,   0,   1,   1 )
+#define MPP47_LCD_VSYNC		MPP( 47, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP48_GPIO		MPP( 48, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP48_TSMP12		MPP( 48, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP48_TDM_DTX		MPP( 48, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP48_LCD_D16		MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
+
+#define MPP49_GPIO		MPP( 49, 0x0, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP49_TSMP9		MPP( 49, 0x1, 1, 1, 0,   0,   0,   1,   1 )
+#define MPP49_TDM_CH0_RX_QL	MPP( 49, 0x2, 0, 1, 0,   0,   0,   1,   1 )
+#define MPP49_PTP_CLK		MPP( 49, 0x5, 1, 0, 0,   0,   0,   1,   0 )
+#define MPP49_PEX0_CLKREQ	MPP( 49, 0xa, 0, 1, 0,   0,   0,   0,   1 )
+#define MPP49_LCD_D17		MPP( 49, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 
 #define MPP_MAX			49
 
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 3ae158d..b96e43b 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -249,8 +249,8 @@ static unsigned int netspace_v2_mpp_config[] __initdata = {
 	MPP4_NF_IO6,
 	MPP5_NF_IO7,
 	MPP6_SYSRST_OUTn,
-	MPP8_TW_SDA,
-	MPP9_TW_SCK,
+	MPP8_TW0_SDA,
+	MPP9_TW0_SCK,
 	MPP10_UART0_TXD,
 	MPP11_UART0_RXD,
 	MPP12_GPO,		/* Red led */
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 8a2bb02..2bd14c5 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -270,8 +270,8 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
 	MPP3_SPI_MISO,
 	MPP6_SYSRST_OUTn,
 	MPP7_GPO,		/* Request power-off */
-	MPP8_TW_SDA,
-	MPP9_TW_SCK,
+	MPP8_TW0_SDA,
+	MPP9_TW0_SCK,
 	MPP10_UART0_TXD,
 	MPP11_UART0_RXD,
 	MPP13_GPIO,		/* Rear power switch (on|auto) */
@@ -306,8 +306,8 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
 	MPP3_SPI_MISO,
 	MPP6_SYSRST_OUTn,
 	MPP7_GPO,		/* Request power-off */
-	MPP8_TW_SDA,
-	MPP9_TW_SCK,
+	MPP8_TW0_SDA,
+	MPP9_TW0_SCK,
 	MPP10_UART0_TXD,
 	MPP11_UART0_RXD,
 	MPP13_GPIO,		/* Rear power switch (on|auto) */
@@ -315,20 +315,20 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
 	MPP15_GPIO,		/* Rear power switch (auto|off) */
 	MPP16_GPIO,		/* SATA HDD1 power */
 	MPP17_GPIO,		/* SATA HDD2 power */
-	MPP20_GE1_0,
-	MPP21_GE1_1,
-	MPP22_GE1_2,
-	MPP23_GE1_3,
-	MPP24_GE1_4,
-	MPP25_GE1_5,
-	MPP26_GE1_6,
-	MPP27_GE1_7,
+	MPP20_GE1_TXD0,
+	MPP21_GE1_TXD1,
+	MPP22_GE1_TXD2,
+	MPP23_GE1_TXD3,
+	MPP24_GE1_RXD0,
+	MPP25_GE1_RXD1,
+	MPP26_GE1_RXD2,
+	MPP27_GE1_RXD3,
 	MPP28_GPIO,		/* USB enable host vbus */
 	MPP29_GPIO,		/* CPLD extension ALE */
-	MPP30_GE1_10,
-	MPP31_GE1_11,
-	MPP32_GE1_12,
-	MPP33_GE1_13,
+	MPP30_GE1_RXCTL,
+	MPP31_GE1_RXCLK,
+	MPP32_GE1_TCLKOUT,
+	MPP33_GE1_TXCTL,
 	MPP34_GPIO,		/* Rear Push button */
 	MPP35_GPIO,		/* Inhibit switch power-off */
 	MPP36_GPIO,		/* SATA HDD1 presence */
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 2830f0f..d23aff9 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -74,8 +74,8 @@ static unsigned int qnap_ts219_mpp_config[] __initdata = {
 	MPP3_SPI_MISO,
 	MPP4_SATA1_ACTn,
 	MPP5_SATA0_ACTn,
-	MPP8_TW_SDA,
-	MPP9_TW_SCK,
+	MPP8_TW0_SDA,
+	MPP9_TW0_SCK,
 	MPP10_UART0_TXD,
 	MPP11_UART0_RXD,
 	MPP13_UART1_TXD,	/* PIC controller */
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index de49c2d..ecd0d5f 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -78,26 +78,26 @@ static unsigned int qnap_ts41x_mpp_config[] __initdata = {
 	MPP3_SPI_MISO,
 	MPP6_SYSRST_OUTn,
 	MPP7_PEX_RST_OUTn,
-	MPP8_TW_SDA,
-	MPP9_TW_SCK,
+	MPP8_TW0_SDA,
+	MPP9_TW0_SCK,
 	MPP10_UART0_TXD,
 	MPP11_UART0_RXD,
 	MPP13_UART1_TXD,	/* PIC controller */
 	MPP14_UART1_RXD,	/* PIC controller */
 	MPP15_SATA0_ACTn,
 	MPP16_SATA1_ACTn,
-	MPP20_GE1_0,
-	MPP21_GE1_1,
-	MPP22_GE1_2,
-	MPP23_GE1_3,
-	MPP24_GE1_4,
-	MPP25_GE1_5,
-	MPP26_GE1_6,
-	MPP27_GE1_7,
-	MPP30_GE1_10,
-	MPP31_GE1_11,
-	MPP32_GE1_12,
-	MPP33_GE1_13,
+	MPP20_GE1_TXD0,
+	MPP21_GE1_TXD1,
+	MPP22_GE1_TXD2,
+	MPP23_GE1_TXD3,
+	MPP24_GE1_RXD0,
+	MPP25_GE1_RXD1,
+	MPP26_GE1_RXD2,
+	MPP27_GE1_RXD3,
+	MPP30_GE1_RXCTL,
+	MPP31_GE1_RXCLK,
+	MPP32_GE1_TCLKOUT,
+	MPP33_GE1_TXCTL,
 	MPP36_GPIO,		/* RAM: 0: 256 MB, 1: 512 MB */
 	MPP37_GPIO,		/* Reset button */
 	MPP43_GPIO,		/* USB Copy button */



From benjamin.zores at alcatel-lucent.com  Thu Jun 17 03:59:03 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Thu, 17 Jun 2010 09:59:03 +0200
Subject: [PATCH 2/4] arch/arm/mach-kirkwood: add support for 88F6282-A0
	revision
In-Reply-To: <20100617075711.15387.69398.stgit@localhost.localdomain>
References: <20100617075711.15387.69398.stgit@localhost.localdomain>
Message-ID: <20100617075903.15387.69442.stgit@localhost.localdomain>

Signed-off-by: Benjamin Zores <benjamin.zores at alcatel-lucent.com>
---
 arch/arm/mach-kirkwood/common.c                |   10 +++++++++-
 arch/arm/mach-kirkwood/include/mach/kirkwood.h |    5 ++++-
 arch/arm/mach-kirkwood/mpp.c                   |    2 ++
 3 files changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 6072eaa..94f629d 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -402,7 +402,7 @@ void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
 	u32 dev, rev;
 
 	kirkwood_pcie_id(&dev, &rev);
-	if (rev == 0)  /* catch all Kirkwood Z0's */
+	if (rev == 0 && dev != MV88F6282_DEV_ID)  /* catch all Kirkwood Z0's and 6282 */
 		mvsdio_data->clock = 100000000;
 	else
 		mvsdio_data->clock = 200000000;
@@ -851,6 +851,9 @@ int __init kirkwood_find_tclk(void)
 					rev == MV88F6281_REV_A1))
 		return 200000000;
 
+	if (dev == MV88F6282_DEV_ID)
+		return 200000000;
+
 	return 166666667;
 }
 
@@ -886,6 +889,11 @@ static char * __init kirkwood_id(void)
 			return "MV88F6281-A1";
 		else
 			return "MV88F6281-Rev-Unsupported";
+	} if (dev == MV88F6282_DEV_ID) {
+		if (rev == MV88F6282_REV_A0)
+			return "MV88F6282-A0";
+		else
+			return "MV88F6282-Rev-Unsupported";
 	} else if (dev == MV88F6192_DEV_ID) {
 		if (rev == MV88F6192_REV_Z0)
 			return "MV88F6192-Z0";
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a15cf0e..a571860 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -2,7 +2,7 @@
  * arch/arm/mach-kirkwood/include/mach/kirkwood.h
  *
  * Generic definitions for Marvell Kirkwood SoC flavors:
- *  88F6180, 88F6192 and 88F6281.
+ *  88F6180, 88F6192, 88F6281 and 88F6282.
  *
  * This file is licensed under the terms of the GNU General Public
  * License version 2.  This program is licensed "as is" without any
@@ -104,6 +104,9 @@
 #define MV88F6281_REV_A0	2
 #define MV88F6281_REV_A1	3
 
+#define MV88F6282_DEV_ID	0x6282
+#define MV88F6282_REV_A0	0
+
 #define MV88F6192_DEV_ID	0x6192
 #define MV88F6192_REV_Z0	0
 #define MV88F6192_REV_A0	2
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index a5900f6..330a5a1 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -25,6 +25,8 @@ static unsigned int __init kirkwood_variant(void)
 
 	if (dev == MV88F6281_DEV_ID && rev >= MV88F6281_REV_A0)
 		return MPP_F6281_MASK;
+	if (dev == MV88F6282_DEV_ID && rev >= MV88F6282_REV_A0)
+		return MPP_F6282_MASK;
 	if (dev == MV88F6192_DEV_ID && rev >= MV88F6192_REV_A0)
 		return MPP_F6192_MASK;
 	if (dev == MV88F6180_DEV_ID)



From benjamin.zores at alcatel-lucent.com  Thu Jun 17 03:59:09 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Thu, 17 Jun 2010 09:59:09 +0200
Subject: [PATCH 3/4] arch/arm/mach-kirkwood: add support for 2nd PCIe port on
	88f6282.
In-Reply-To: <20100617075711.15387.69398.stgit@localhost.localdomain>
References: <20100617075711.15387.69398.stgit@localhost.localdomain>
Message-ID: <20100617075909.15387.93914.stgit@localhost.localdomain>

Signed-off-by: Benjamin Zores <benjamin.zores at alcatel-lucent.com>
---
 arch/arm/mach-kirkwood/addr-map.c                 |   21 ++
 arch/arm/mach-kirkwood/common.c                   |   28 +++
 arch/arm/mach-kirkwood/common.h                   |    5 -
 arch/arm/mach-kirkwood/db88f6281-bp-setup.c       |    2 
 arch/arm/mach-kirkwood/include/mach/bridge-regs.h |    3 
 arch/arm/mach-kirkwood/include/mach/irqs.h        |    1 
 arch/arm/mach-kirkwood/include/mach/kirkwood.h    |   35 +++-
 arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c    |    2 
 arch/arm/mach-kirkwood/openrd-setup.c             |    2 
 arch/arm/mach-kirkwood/pcie.c                     |  204 ++++++++++++++++-----
 arch/arm/mach-kirkwood/rd88f6192-nas-setup.c      |    2 
 arch/arm/mach-kirkwood/rd88f6281-setup.c          |    2 
 arch/arm/mach-kirkwood/ts219-setup.c              |    2 
 arch/arm/mach-kirkwood/ts41x-setup.c              |    2 
 14 files changed, 237 insertions(+), 74 deletions(-)

diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index 2e69168..e8f547c 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -31,6 +31,8 @@
 #define ATTR_DEV_CS0		0x3e
 #define ATTR_PCIE_IO		0xe0
 #define ATTR_PCIE_MEM		0xe8
+#define ATTR_PCIE1_IO		0xd0
+#define ATTR_PCIE1_MEM		0xd8
 #define ATTR_SRAM		0x01
 
 /*
@@ -84,6 +86,8 @@ void __init kirkwood_setup_cpu_mbus(void)
 	void __iomem *addr;
 	int i;
 	int cs;
+	int id = 0;
+	u32 dev, rev;
 
 	/*
 	 * First, disable and clear windows.
@@ -102,21 +106,30 @@ void __init kirkwood_setup_cpu_mbus(void)
 	/*
 	 * Setup windows for PCIe IO+MEM space.
 	 */
-	setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
+	setup_cpu_win(id++, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
 		      TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
-	setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
+	setup_cpu_win(id++, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
 		      TARGET_PCIE, ATTR_PCIE_MEM, KIRKWOOD_PCIE_MEM_BUS_BASE);
 
+	kirkwood_pcie_id(&dev, &rev);
+
+	if (dev == MV88F6282_DEV_ID) {
+	  setup_cpu_win(id++, KIRKWOOD_PCIE1_IO_PHYS_BASE, KIRKWOOD_PCIE1_IO_SIZE,
+			TARGET_PCIE, ATTR_PCIE1_IO, KIRKWOOD_PCIE1_IO_BUS_BASE);
+	  setup_cpu_win(id++, KIRKWOOD_PCIE1_MEM_PHYS_BASE, KIRKWOOD_PCIE1_MEM_SIZE,
+			TARGET_PCIE, ATTR_PCIE1_MEM, KIRKWOOD_PCIE1_MEM_BUS_BASE);
+	}
+
 	/*
 	 * Setup window for NAND controller.
 	 */
-	setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
+	setup_cpu_win(id++, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
 		      TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
 
 	/*
 	 * Setup window for SRAM.
 	 */
-	setup_cpu_win(3, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
+	setup_cpu_win(id++, KIRKWOOD_SRAM_PHYS_BASE, KIRKWOOD_SRAM_SIZE,
 		      TARGET_SRAM, ATTR_SRAM, -1);
 
 	/*
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 94f629d..10592ae 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -44,6 +44,11 @@ static struct map_desc kirkwood_io_desc[] __initdata = {
 		.length		= KIRKWOOD_PCIE_IO_SIZE,
 		.type		= MT_DEVICE,
 	}, {
+		.virtual	= KIRKWOOD_PCIE1_IO_VIRT_BASE,
+		.pfn		= __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
+		.length		= KIRKWOOD_PCIE1_IO_SIZE,
+		.type		= MT_DEVICE,
+	}, {
 		.virtual	= KIRKWOOD_REGS_VIRT_BASE,
 		.pfn		= __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
 		.length		= KIRKWOOD_REGS_SIZE,
@@ -957,12 +962,20 @@ void __init kirkwood_init(void)
 static int __init kirkwood_clock_gate(void)
 {
 	unsigned int curr = readl(CLOCK_GATING_CTRL);
+	u32 dev, rev;
+	int flags;
 
 	printk(KERN_DEBUG "Gating clock of unused units\n");
 	printk(KERN_DEBUG "before: 0x%08x\n", curr);
 
+	kirkwood_pcie_id(&dev, &rev);
+
 	/* Make sure those units are accessible */
-	writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0, CLOCK_GATING_CTRL);
+	flags = curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0;
+
+	if (dev == MV88F6282_DEV_ID)
+		flags |= CGC_PEX1;	
+	writel(flags, CLOCK_GATING_CTRL);
 
 	/* For SATA: first shutdown the phy */
 	if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
@@ -978,7 +991,7 @@ static int __init kirkwood_clock_gate(void)
 		writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
 	}
 	
-	/* For PCIe: first shutdown the phy */
+	/* For PCIe #0: first shutdown the phy */
 	if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
 		writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
 		while (1)
@@ -987,6 +1000,17 @@ static int __init kirkwood_clock_gate(void)
 		writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
 	}
 
+	/* For PCIe #1: first shutdown the phy */
+	if (dev == MV88F6282_DEV_ID) {
+		if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
+			writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
+			while (1)
+				if (readl(PCIE1_STATUS) & 0x1)
+					break;
+			writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
+		}
+	}
+
 	/* Now gate clock the required units */
 	writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
 	printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 05e8a8a..5b2c1c1 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -18,6 +18,9 @@ struct mvsdio_platform_data;
 struct mtd_partition;
 struct mtd_info;
 
+#define KW_PCIE0	(1 << 0)
+#define KW_PCIE1	(1 << 1)
+
 /*
  * Basic Kirkwood init functions used early by machine-setup.
  */
@@ -34,7 +37,7 @@ void kirkwood_ehci_init(void);
 void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data);
 void kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq);
-void kirkwood_pcie_init(void);
+void kirkwood_pcie_init(unsigned int portmask);
 void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
 void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
 void kirkwood_spi_init(void);
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 39bdf4b..7550c4e 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -75,7 +75,7 @@ static void __init db88f6281_init(void)
 static int __init db88f6281_pci_init(void)
 {
 	if (machine_is_db88f6281_bp())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index 418f501..aff0e13 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -59,8 +59,9 @@
 #define CGC_SATA1		(1 << 15)
 #define CGC_XOR1		(1 << 16)
 #define CGC_CRYPTO		(1 << 17)
+#define CGC_PEX1		(1 << 18)
 #define CGC_GE1			(1 << 19)
 #define CGC_TDM			(1 << 20)
-#define CGC_RESERVED		((1 << 18) | (0x6 << 21))
+#define CGC_RESERVED		(0x6 << 21)
 
 #endif
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index f00a0a4..9da2eb5 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -23,6 +23,7 @@
 #define IRQ_KIRKWOOD_XOR_10	7
 #define IRQ_KIRKWOOD_XOR_11	8
 #define IRQ_KIRKWOOD_PCIE	9
+#define IRQ_KIRKWOOD_PCIE1	10
 #define IRQ_KIRKWOOD_GE00_SUM	11
 #define IRQ_KIRKWOOD_GE01_SUM	15
 #define IRQ_KIRKWOOD_USB	19
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index a571860..7938347 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -16,36 +16,48 @@
  * Marvell Kirkwood address maps.
  *
  * phys
- * e0000000	PCIe Memory space
+ * e0000000	PCIe #0 Memory space
+ * e8000000	PCIe #1 Memory space
  * f1000000	on-chip peripheral registers
- * f2000000	PCIe I/O space
- * f3000000	NAND controller address window
- * f4000000	Security Accelerator SRAM
+ * f2000000	PCIe #0 I/O space
+ * f3000000	PCIe #1 I/O space
+ * f4000000	NAND controller address window
+ * f5000000	Security Accelerator SRAM
  *
  * virt		phys		size
- * fee00000	f1000000	1M	on-chip peripheral registers
- * fef00000	f2000000	1M	PCIe I/O space
+ * fed00000	f1000000	1M	on-chip peripheral registers
+ * fee00000	f2000000	1M	PCIe #0 I/O space
+ * fef00000	f3000000	1M	PCIe #1 I/O space
  */
 
-#define KIRKWOOD_SRAM_PHYS_BASE		0xf4000000
+#define KIRKWOOD_SRAM_PHYS_BASE		0xf5000000
 #define KIRKWOOD_SRAM_SIZE		SZ_2K
 
-#define KIRKWOOD_NAND_MEM_PHYS_BASE	0xf3000000
+#define KIRKWOOD_NAND_MEM_PHYS_BASE	0xf4000000
 #define KIRKWOOD_NAND_MEM_SIZE		SZ_1K
 
+#define KIRKWOOD_PCIE1_IO_PHYS_BASE	0xf3000000
+#define KIRKWOOD_PCIE1_IO_VIRT_BASE	0xfef00000
+#define KIRKWOOD_PCIE1_IO_BUS_BASE	0x00000000
+#define KIRKWOOD_PCIE1_IO_SIZE		SZ_1M
+
 #define KIRKWOOD_PCIE_IO_PHYS_BASE	0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE	0xfef00000
+#define KIRKWOOD_PCIE_IO_VIRT_BASE	0xfee00000
 #define KIRKWOOD_PCIE_IO_BUS_BASE	0x00000000
 #define KIRKWOOD_PCIE_IO_SIZE		SZ_1M
 
 #define KIRKWOOD_REGS_PHYS_BASE		0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE		0xfee00000
+#define KIRKWOOD_REGS_VIRT_BASE		0xfed00000
 #define KIRKWOOD_REGS_SIZE		SZ_1M
 
 #define KIRKWOOD_PCIE_MEM_PHYS_BASE	0xe0000000
 #define KIRKWOOD_PCIE_MEM_BUS_BASE	0xe0000000
 #define KIRKWOOD_PCIE_MEM_SIZE		SZ_128M
 
+#define KIRKWOOD_PCIE1_MEM_PHYS_BASE	0xe8000000
+#define KIRKWOOD_PCIE1_MEM_BUS_BASE	0xe8000000
+#define KIRKWOOD_PCIE1_MEM_SIZE		SZ_128M
+
 /*
  * Register Map
  */
@@ -72,6 +84,9 @@
 #define PCIE_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x40000)
 #define PCIE_LINK_CTRL		(PCIE_VIRT_BASE | 0x70)
 #define PCIE_STATUS		(PCIE_VIRT_BASE | 0x1a04)
+#define PCIE1_VIRT_BASE		(KIRKWOOD_REGS_VIRT_BASE | 0x44000)
+#define PCIE1_LINK_CTRL		(PCIE1_VIRT_BASE | 0x70)
+#define PCIE1_STATUS		(PCIE1_VIRT_BASE | 0x1a04)
 
 #define USB_PHYS_BASE		(KIRKWOOD_REGS_PHYS_BASE | 0x50000)
 
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 5e6f711..c6b92b4 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -155,7 +155,7 @@ static void __init mv88f6281gtw_ge_init(void)
 static int __init mv88f6281gtw_ge_pci_init(void)
 {
 	if (machine_is_mv88f6281gtw_ge())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index ad3f1ec..2400207 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -85,7 +85,7 @@ static void __init openrd_init(void)
 static int __init openrd_pci_init(void)
 {
 	if (machine_is_openrd_base() || machine_is_openrd_client())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index dee1eff..bdf1e6b 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,29 +18,51 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
+void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+{
+	*dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
+	*rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+}
 
-#define PCIE_BASE	((void __iomem *)PCIE_VIRT_BASE)
+struct pcie_port {
+	int			index;
+	u8			root_bus_nr;
+	void __iomem		*base;
+	spinlock_t		conf_lock;
+	int			irq;
+	struct resource		res[2];
+};
 
-void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
+static struct pcie_port pcie_port[2];
+static int num_pcie_ports;
+
+static inline struct pcie_port *bus_to_port(int bus)
 {
-	*dev = orion_pcie_dev_id(PCIE_BASE);
-	*rev = orion_pcie_rev(PCIE_BASE);
+	int i;
+
+	for (i = num_pcie_ports - 1; i >= 0; i--) {
+        	int rbus = pcie_port[i].root_bus_nr;
+		if (rbus != -1 && rbus <= bus)
+			break;
+	}
+
+	return i >= 0 ? pcie_port + i : NULL;
 }
 
-static int pcie_valid_config(int bus, int dev)
+static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
 {
 	/*
 	 * Don't go out when trying to access --
 	 * 1. nonexisting device on local bus
 	 * 2. where there's no device connected (no link)
 	 */
-	if (bus == 0 && dev == 0)
+	if (bus == pp->root_bus_nr && dev == 0)
 		return 1;
 
-	if (!orion_pcie_link_up(PCIE_BASE))
+	if (!orion_pcie_link_up(pp->base))
 		return 0;
 
-	if (bus == 0 && dev != 1)
+	if (bus == pp->root_bus_nr && dev != 1)
 		return 0;
 
 	return 1;
@@ -52,22 +74,22 @@ static int pcie_valid_config(int bus, int dev)
  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  * transactions are atomic.
  */
-static DEFINE_SPINLOCK(kirkwood_pcie_lock);
 
 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 			int size, u32 *val)
 {
+	struct pcie_port *pp = bus_to_port(bus->number);
 	unsigned long flags;
 	int ret;
 
-	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
+	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
 		*val = 0xffffffff;
 		return PCIBIOS_DEVICE_NOT_FOUND;
 	}
 
-	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-	ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
-	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+	spin_lock_irqsave(&pp->conf_lock, flags);
+	ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
+	spin_unlock_irqrestore(&pp->conf_lock, flags);
 
 	return ret;
 }
@@ -75,15 +97,16 @@ static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 			int where, int size, u32 val)
 {
+	struct pcie_port *pp = bus_to_port(bus->number);
 	unsigned long flags;
 	int ret;
 
-	if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
+	if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
 		return PCIBIOS_DEVICE_NOT_FOUND;
 
-	spin_lock_irqsave(&kirkwood_pcie_lock, flags);
-	ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
-	spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
+	spin_lock_irqsave(&pp->conf_lock, flags);
+	ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
+	spin_unlock_irqrestore(&pp->conf_lock, flags);
 
 	return ret;
 }
@@ -93,50 +116,106 @@ static struct pci_ops pcie_ops = {
 	.write = pcie_wr_conf,
 };
 
-
-static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+static int __init pcie0_ioresouces_setup(struct pcie_port *pp)
 {
-	struct resource *res;
-	extern unsigned int kirkwood_clk_ctrl;
-
 	/*
-	 * Generic PCIe unit setup.
+	 * IORESOURCE_IO
 	 */
-	orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
+	pp->res[0].name  = "PCIe 0 I/O Space";
+	pp->res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
+	pp->res[0].end   = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
+	pp->res[0].flags = IORESOURCE_IO;
+	if (request_resource(&ioport_resource, &pp->res[0]))
+		panic("Request PCIe 0 IO resource failed\n");
 
 	/*
-	 * Request resources.
+	 * IORESOURCE_MEM
 	 */
-	res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
-	if (!res)
-		panic("pcie_setup unable to alloc resources");
+	pp->res[1].name  = "PCIe 0 MEM";
+	pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+	pp->res[1].end   = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+	pp->res[1].flags = IORESOURCE_MEM;
+	if (request_resource(&iomem_resource, &pp->res[1]))
+		panic("Request PCIe 0 Memory resource failed\n");
+
+	return 1;
+}
 
+static int __init pcie1_ioresouces_setup(struct pcie_port *pp)
+{
 	/*
 	 * IORESOURCE_IO
 	 */
-	res[0].name = "PCIe I/O Space";
-	res[0].flags = IORESOURCE_IO;
-	res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
-	res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
-	if (request_resource(&ioport_resource, &res[0]))
-		panic("Request PCIe IO resource failed\n");
-	sys->resource[0] = &res[0];
+	pp->res[0].name  = "PCIe 1 I/O Space";
+	pp->res[0].start = KIRKWOOD_PCIE1_IO_PHYS_BASE;
+	pp->res[0].end   = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
+	pp->res[0].flags = IORESOURCE_IO;
+	if (request_resource(&ioport_resource, &pp->res[0]))
+		panic("Request PCIe 1 IO resource failed\n");
 
 	/*
 	 * IORESOURCE_MEM
 	 */
-	res[1].name = "PCIe Memory Space";
-	res[1].flags = IORESOURCE_MEM;
-	res[1].start = KIRKWOOD_PCIE_MEM_BUS_BASE;
-	res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
-	if (request_resource(&iomem_resource, &res[1]))
-		panic("Request PCIe Memory resource failed\n");
-	sys->resource[1] = &res[1];
+	pp->res[1].name  = "PCIe 1 MEM";
+	pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+	pp->res[1].end   = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+	pp->res[1].flags = IORESOURCE_MEM;
+	if (request_resource(&iomem_resource, &pp->res[1]))
+		panic("Request PCIe 1 Memory resource failed\n");
 
-	sys->resource[2] = NULL;
-	sys->io_offset = 0;
+	return 1;
+}
+
+static void __init kirkwood_pcie_preinit(void)
+{
+	int i;
+
+	for (i = 0; i < num_pcie_ports; i++) {
+		struct pcie_port *pp = pcie_port + i;
+		extern unsigned int kirkwood_clk_ctrl;
+
+		switch (pp->index) {
+		case 0:
+			pp->base = (void __iomem *)PCIE_VIRT_BASE;
+			pp->irq	= IRQ_KIRKWOOD_PCIE;
+			kirkwood_clk_ctrl |= CGC_PEX0;
+			pcie0_ioresouces_setup(pp);
+			break;
+		case 1:
+			pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+			pp->irq	= IRQ_KIRKWOOD_PCIE1;
+			kirkwood_clk_ctrl |= CGC_PEX1;
+			pcie1_ioresouces_setup(pp);
+			break;
+		default:
+			panic("PCIe setup: invalid controller");
+		}
+	}
+}
+
+static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+	struct pcie_port *pp;
+
+	if (nr >= num_pcie_ports)
+		return 0;
+
+	pp = &pcie_port[nr];
+	pp->root_bus_nr = sys->busnr;
+
+	printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n",
+	       sys->busnr, pp->index);
+
+	/*
+	 * Generic PCIe unit setup.
+	 */
+	orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
+	orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
 
-	kirkwood_clk_ctrl |= CGC_PEX0;
+	sys->resource[0] = &pp->res[0];
+	sys->resource[1] = &pp->res[1];
+	sys->resource[2] = NULL;
+	sys->io_offset   = 0;
 
 	return 1;
 }
@@ -163,7 +242,7 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 {
 	struct pci_bus *bus;
 
-	if (nr == 0) {
+	if (nr < num_pcie_ports) {
 		bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
 	} else {
 		bus = NULL;
@@ -175,18 +254,45 @@ kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
 
 static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
-	return IRQ_KIRKWOOD_PCIE;
+	struct pcie_port *pp = bus_to_port(dev->bus->number);
+
+	return pp->irq;
 }
 
 static struct hw_pci kirkwood_pci __initdata = {
-	.nr_controllers	= 1,
+	.preinit	= kirkwood_pcie_preinit,
 	.swizzle	= pci_std_swizzle,
 	.setup		= kirkwood_pcie_setup,
 	.scan		= kirkwood_pcie_scan_bus,
 	.map_irq	= kirkwood_pcie_map_irq,
 };
 
-void __init kirkwood_pcie_init(void)
+static void __init add_pcie_port(int index, unsigned long base)
+{
+	printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
+
+	if (orion_pcie_link_up((void __iomem *)base)) {
+		struct pcie_port *pp = &pcie_port[num_pcie_ports++];
+
+		printk(KERN_INFO "link up\n");
+
+		pp->index = index;
+		pp->root_bus_nr = -1;
+		pp->base = (void __iomem *)base;
+		spin_lock_init(&pp->conf_lock);
+		memset(pp->res, 0, sizeof(pp->res));
+	} else
+		printk(KERN_INFO "link down, ignoring\n");
+}
+
+void __init kirkwood_pcie_init(unsigned int portmask)
 {
+	if (portmask & KW_PCIE0)
+		add_pcie_port(0, PCIE_VIRT_BASE);
+
+	if (portmask & KW_PCIE1)
+		add_pcie_port(1, PCIE1_VIRT_BASE);
+
+	kirkwood_pci.nr_controllers = num_pcie_ports;
 	pci_common_init(&kirkwood_pci);
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 3bf6304..c34718c 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -71,7 +71,7 @@ static void __init rd88f6192_init(void)
 static int __init rd88f6192_pci_init(void)
 {
 	if (machine_is_rd88f6192_nas())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 31708dd..3d14771 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -107,7 +107,7 @@ static void __init rd88f6281_init(void)
 static int __init rd88f6281_pci_init(void)
 {
 	if (machine_is_rd88f6281())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
 	return 0;
 }
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index d23aff9..5c7dd85 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -111,7 +111,7 @@ static void __init qnap_ts219_init(void)
 static int __init ts219_pci_init(void)
 {
    if (machine_is_ts219())
-           kirkwood_pcie_init();
+	kirkwood_pcie_init(KW_PCIE0);
 
    return 0;
 }
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index ecd0d5f..a2c5f70 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -136,7 +136,7 @@ static void __init qnap_ts41x_init(void)
 static int __init ts41x_pci_init(void)
 {
 	if (machine_is_ts41x())
-		kirkwood_pcie_init();
+		kirkwood_pcie_init(KW_PCIE0);
 
    return 0;
 }



From benjamin.zores at alcatel-lucent.com  Thu Jun 17 03:59:14 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Thu, 17 Jun 2010 09:59:14 +0200
Subject: [PATCH 4/4] arch/arm/mach-kirkwood: add support for 2nd TWSI
	controller on 88f6282.
In-Reply-To: <20100617075711.15387.69398.stgit@localhost.localdomain>
References: <20100617075711.15387.69398.stgit@localhost.localdomain>
Message-ID: <20100617075914.15387.91307.stgit@localhost.localdomain>

Signed-off-by: Benjamin Zores <benjamin.zores at alcatel-lucent.com>
---
 arch/arm/mach-kirkwood/common.c                |   52 +++++++++++++++++++-----
 arch/arm/mach-kirkwood/common.h                |    5 ++
 arch/arm/mach-kirkwood/include/mach/irqs.h     |    3 +
 arch/arm/mach-kirkwood/include/mach/kirkwood.h |    3 +
 arch/arm/mach-kirkwood/netspace_v2-setup.c     |    2 -
 arch/arm/mach-kirkwood/netxbig_v2-setup.c      |    2 -
 arch/arm/mach-kirkwood/openrd-setup.c          |    2 -
 arch/arm/mach-kirkwood/ts219-setup.c           |    2 -
 arch/arm/mach-kirkwood/ts41x-setup.c           |    2 -
 9 files changed, 55 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 10592ae..8382a56 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -458,31 +458,63 @@ static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
 	.timeout	= 1000, /* Default timeout of 1 second */
 };
 
-static struct resource kirkwood_i2c_resources[] = {
+static struct resource kirkwood_i2c_0_resources[] = {
 	{
-		.start	= I2C_PHYS_BASE,
-		.end	= I2C_PHYS_BASE + 0x1f,
+		.start	= I2C_0_PHYS_BASE,
+		.end	= I2C_0_PHYS_BASE + 0x1f,
 		.flags	= IORESOURCE_MEM,
 	}, {
-		.start	= IRQ_KIRKWOOD_TWSI,
-		.end	= IRQ_KIRKWOOD_TWSI,
+		.start	= IRQ_KIRKWOOD_TWSI0,
+		.end	= IRQ_KIRKWOOD_TWSI0,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
 
-static struct platform_device kirkwood_i2c = {
+static struct resource kirkwood_i2c_1_resources[] = {
+	{
+		.start	= I2C_1_PHYS_BASE,
+		.end	= I2C_1_PHYS_BASE + 0x1f,
+		.flags	= IORESOURCE_MEM,
+	}, {
+		.start	= IRQ_KIRKWOOD_TWSI1,
+		.end	= IRQ_KIRKWOOD_TWSI1,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device kirkwood_i2c_0 = {
+	.name		= MV64XXX_I2C_CTLR_NAME,
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(kirkwood_i2c_0_resources),
+	.resource	= kirkwood_i2c_0_resources,
+	.dev		= {
+		.platform_data	= &kirkwood_i2c_pdata,
+	},
+};
+
+static struct platform_device kirkwood_i2c_1 = {
 	.name		= MV64XXX_I2C_CTLR_NAME,
 	.id		= 0,
-	.num_resources	= ARRAY_SIZE(kirkwood_i2c_resources),
-	.resource	= kirkwood_i2c_resources,
+	.num_resources	= ARRAY_SIZE(kirkwood_i2c_1_resources),
+	.resource	= kirkwood_i2c_1_resources,
 	.dev		= {
 		.platform_data	= &kirkwood_i2c_pdata,
 	},
 };
 
-void __init kirkwood_i2c_init(void)
+void __init kirkwood_i2c_init(unsigned int mask)
 {
-	platform_device_register(&kirkwood_i2c);
+	if (mask & KW_TWSI0)
+		platform_device_register(&kirkwood_i2c_0);
+
+	if (mask & KW_TWSI1) {
+		u32 dev, rev;
+
+		kirkwood_pcie_id(&dev, &rev);
+
+		if (dev == MV88F6282_DEV_ID && (rev == MV88F6282_REV_A0))
+			platform_device_register(&kirkwood_i2c_1);
+	}
 }
 
 
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 5b2c1c1..fc05200 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -21,6 +21,9 @@ struct mtd_info;
 #define KW_PCIE0	(1 << 0)
 #define KW_PCIE1	(1 << 1)
 
+#define KW_TWSI0	(1 << 0)
+#define KW_TWSI1	(1 << 1)
+
 /*
  * Basic Kirkwood init functions used early by machine-setup.
  */
@@ -41,7 +44,7 @@ void kirkwood_pcie_init(unsigned int portmask);
 void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
 void kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data);
 void kirkwood_spi_init(void);
-void kirkwood_i2c_init(void);
+void kirkwood_i2c_init(unsigned int mask);
 void kirkwood_uart0_init(void);
 void kirkwood_uart1_init(void);
 void kirkwood_nand_init(struct mtd_partition *parts, int nr_parts, int delay);
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index 9da2eb5..d82ecf0 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -33,13 +33,14 @@
 #define IRQ_KIRKWOOD_I2S	24
 #define IRQ_KIRKWOOD_TS_0	26
 #define IRQ_KIRKWOOD_SDIO	28
-#define IRQ_KIRKWOOD_TWSI	29
+#define IRQ_KIRKWOOD_TWSI0	29
 #define IRQ_KIRKWOOD_AVB	30
 #define IRQ_KIRKWOOD_TDMI	31
 
 /*
  * High Interrupt Controller
  */
+#define IRQ_KIRKWOOD_TWSI1	32
 #define IRQ_KIRKWOOD_UART_0	33
 #define IRQ_KIRKWOOD_UART_1	34
 #define IRQ_KIRKWOOD_GPIO_LOW_0_7	35
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 7938347..6138884 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -71,7 +71,8 @@
 #define  DEVICE_ID		(DEV_BUS_VIRT_BASE | 0x0034)
 #define  RTC_PHYS_BASE		(DEV_BUS_PHYS_BASE | 0x0300)
 #define  SPI_PHYS_BASE		(DEV_BUS_PHYS_BASE | 0x0600)
-#define  I2C_PHYS_BASE		(DEV_BUS_PHYS_BASE | 0x1000)
+#define  I2C_0_PHYS_BASE	(DEV_BUS_PHYS_BASE | 0x1000)
+#define  I2C_1_PHYS_BASE	(DEV_BUS_PHYS_BASE | 0x1100)
 #define  UART0_PHYS_BASE	(DEV_BUS_PHYS_BASE | 0x2000)
 #define  UART0_VIRT_BASE	(DEV_BUS_VIRT_BASE | 0x2000)
 #define  UART1_PHYS_BASE	(DEV_BUS_PHYS_BASE | 0x2100)
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index b96e43b..ddf1e89 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -295,7 +295,7 @@ static void __init netspace_v2_init(void)
 	spi_register_board_info(netspace_v2_spi_slave_info,
 				ARRAY_SIZE(netspace_v2_spi_slave_info));
 	kirkwood_spi_init();
-	kirkwood_i2c_init();
+	kirkwood_i2c_init(KW_TWSI0);
 	i2c_register_board_info(0, netspace_v2_i2c_info,
 				ARRAY_SIZE(netspace_v2_i2c_info));
 
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 2bd14c5..1812a0c 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -377,7 +377,7 @@ static void __init netxbig_v2_init(void)
 	spi_register_board_info(netxbig_v2_spi_slave_info,
 				ARRAY_SIZE(netxbig_v2_spi_slave_info));
 	kirkwood_spi_init();
-	kirkwood_i2c_init();
+	kirkwood_i2c_init(KW_TWSI0);
 	i2c_register_board_info(0, netxbig_v2_i2c_info,
 				ARRAY_SIZE(netxbig_v2_i2c_info));
 
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 2400207..605a8d9 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -79,7 +79,7 @@ static void __init openrd_init(void)
 	kirkwood_sata_init(&openrd_sata_data);
 	kirkwood_sdio_init(&openrd_mvsdio_data);
 
-	kirkwood_i2c_init();
+	kirkwood_i2c_init(KW_TWSI0);
 }
 
 static int __init openrd_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 5c7dd85..d1115d4 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -97,7 +97,7 @@ static void __init qnap_ts219_init(void)
 	kirkwood_uart0_init();
 	kirkwood_uart1_init(); /* A PIC controller is connected here. */
 	qnap_tsx1x_register_flash();
-	kirkwood_i2c_init();
+	kirkwood_i2c_init(KW_TWSI0);
 	i2c_register_board_info(0, &qnap_ts219_i2c_rtc, 1);
 	kirkwood_ge00_init(&qnap_ts219_ge00_data);
 	kirkwood_sata_init(&qnap_ts219_sata_data);
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index a2c5f70..7d19691 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -121,7 +121,7 @@ static void __init qnap_ts41x_init(void)
 	kirkwood_uart0_init();
 	kirkwood_uart1_init(); /* A PIC controller is connected here. */
 	qnap_tsx1x_register_flash();
-	kirkwood_i2c_init();
+	kirkwood_i2c_init(KW_TWSI0);
 	i2c_register_board_info(0, &qnap_ts41x_i2c_rtc, 1);
 	kirkwood_ge00_init(&qnap_ts41x_ge00_data);
 	kirkwood_ge01_init(&qnap_ts41x_ge01_data);



From mhowe at cwlinux.com  Thu Jun 17 04:33:40 2010
From: mhowe at cwlinux.com (Morgan Howe)
Date: Thu, 17 Jun 2010 16:33:40 +0800
Subject: mxcmmc driver hangs on sync
In-Reply-To: <20100615072237.GW17833@buzzloop.caiaq.de>
References: <20100615112936.5d03ce92@morgan>
	<20100615063142.GU17833@buzzloop.caiaq.de>
	<20100615152051.26e4589c@morgan>
	<20100615072237.GW17833@buzzloop.caiaq.de>
Message-ID: <20100617163340.69409a3f@morgan>

Daniel,

On Tue, 15 Jun 2010 09:22:37 +0200
Daniel Mack <daniel at caiaq.de> wrote:
> On Tue, Jun 15, 2010 at 03:20:51PM +0800, Morgan Howe wrote:
> > On Tue, 15 Jun 2010 08:31:43 +0200
> > Daniel Mack <daniel at caiaq.de> wrote:
> > > On Tue, Jun 15, 2010 at 11:29:36AM +0800, Morgan Howe wrote:
> > > > With the older kernel this would hang on sync after a few
> > > > thousand loops, and much sooner if you ran 2 or 3 of these
> > > > processes at a time. I tried last night with the newer kernel
> > > > and kicking off 3 processes and after ~100-150 loops per
> > > > process I get this:
> > > 
> > > Which 'newer kernel' did you try?
> > 
> > Hey Daniel,
> > 
> > Sorry, I said current mainline, but actually it's 2.6.35-rc1.
> 
> Could you try two things:
> 
> a) build a kernel without MX2 DMA support
> b) try 2.6.34, as there were some updates to the mxcmmc driver after
>    2.6.34 which could be related

I have just been able to confirm using the final release of the 2.6.34
kernel that the problem also exists, with the same behavior as
described for 2.6.35.

Regards,
Morgan


From myungjoo.ham at samsung.com  Thu Jun 17 04:33:16 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Thu, 17 Jun 2010 17:33:16 +0900
Subject: [PATCH] S5PV210 Correct clock register properties
Message-ID: <1276763596-6175-1-git-send-email-myungjoo.ham@samsung.com>

From: MyungJoo Ham <myungJoo.ham at samsung.com>

Corrected shift values of I2S and UART clocks (CLK_GATE_IP3).

I2S (CLK_GATE_IP3) and UART (CLK_GATE_IP3) had wrong register shift
values, which in turn, made them turn on and off wrong clocks.

Please note that each clock definition should access different control
register; otherwise, the system may suffer lockups. For example, if we
have two clock definitions "a" and "b" which access the same register
(and the shift value). Then, when we do:

	module B
	1 clk = clk_get("b");
	2 clk->clk_enable(clk);
	3 do something with clk.
	4 clk->clk_disable(clk);

	module A
	1 clk = clk_get("a");
	2 clk->clk_enable(clk);
	3 do something with clk
	4 clk->clk_disable(clk);

	And if the execution order is

	B1->B2->A1->A2->A3->A4->B3 ...

	Then, the system may hang at the point B3.


Therefore, there should be no clock definitions with the same contol
register/shift. If we need to create "aliases", then, creating child
clocks sharing the clock should be fine.

However, we did not mitigate this doppelganger clock problem for "struct
clksrc_clk" vs "struct clk"; look at "hsmmc" vs "mmc_bus". In the next
patch, we plan to let "struct clksrc_clk" access "CLK_SRC_MASK0" and
"CLK_SRC_MASK1"; i.e., clock source enable/disable should mask the clock
source itself, not the clock that is supplied by the clock source.

Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
---
 arch/arm/mach-s5pv210/clock.c |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 154bca4..ec5ad8c 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -406,13 +406,13 @@ static struct clk init_clocks_disable[] = {
 		.id		= 0,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1<<5),
 	}, {
 		.name		= "i2s_v32",
 		.id		= 1,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1<<6),
 	}
 };
 
@@ -429,25 +429,25 @@ static struct clk init_clocks[] = {
 		.id		= 0,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<7),
+		.ctrlbit	= (1<<17),
 	}, {
 		.name		= "uart",
 		.id		= 1,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<8),
+		.ctrlbit	= (1<<18),
 	}, {
 		.name		= "uart",
 		.id		= 2,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<9),
+		.ctrlbit	= (1<<19),
 	}, {
 		.name		= "uart",
 		.id		= 3,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<10),
+		.ctrlbit	= (1<<20),
 	},
 };
 
-- 
1.6.3.3



From myungjoo.ham at samsung.com  Thu Jun 17 05:15:16 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Thu, 17 Jun 2010 18:15:16 +0900
Subject: [PATCH] S5PV210 Correct clock source control register properties
Message-ID: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>

The clock source controls (struct clksrc_clk) have been often accessing
CLK_GATE_IPx, which are for clock gating and are accessed by each clock
as well as the clock source. This duplicated clock issue may incur
lockup problems when there are two modules accessing the same clock with
different names.

Besides, the clock source control is supposed to control (setting values
of MASK, SRC, DIV), not to turn on/off individual clock.

Another point is that there are registers (CLK_SRC_MASK0/1) specialized
for masking clock source control in S5PV210/S5PC110 according to the
user manual (rev 20100201).

Therefore, accessing CLK_SRC_MASK0/1 (rather than accessing
CLK_GATE_IPx) for the clock source control is safer and fits to the
semantics of S5PV210/S5PC110 registers. And fortuneatly, each clock
source defined in clock.c has corresponding bit at CLK_SRC_MASK0/1
except for MFC, G2D, and G3D.

In this patch,

- DAC, HDMI, AUDIO 0/1/2, UCLK(uart) 0/1/2/3, MIXER, FIMC 0/1/2,
FIMC, MMC 0/1/2/3, CSIS, SPI 0/1, PWI, and PWM clock sources are
modified to use CLK_SRC_MASK0/1, which were using CLK_GATE_IPx.

- CAM 0/1 did not have enable/disable control. They now access
  CLK_SRC_MASK0.

- MFC, G3D, G2D were using CLK_GATE_IPx. However, as there are no clocks
  defined to control MFC, G3D, and G2D, we kept them to access
CLK_GATE_IPx. These may need to be modified (erase .enable, .ctrlbit
from sclk_mfc, sclk_g2d, sclk_g3d and create clocks: g3d, g2d, mfc)
later.

Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
---
 arch/arm/mach-s5pv210/clock.c |  101 ++++++++++++++++++++++-------------------
 1 files changed, 55 insertions(+), 46 deletions(-)

diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index ec5ad8c..08c1063 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -183,6 +183,11 @@ static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 }
 
+static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
+}
+
 static struct clk clk_sclk_hdmi27m = {
 	.name		= "sclk_hdmi27m",
 	.id		= -1,
@@ -497,8 +502,8 @@ static struct clksrc_clk clk_sclk_dac = {
 	.clk		= {
 		.name		= "sclk_dac",
 		.id		= -1,
-		.ctrlbit	= (1 << 10),
-		.enable		= s5pv210_clk_ip1_ctrl,
+		.ctrlbit	= (1 << 2),
+		.enable		= s5pv210_clk_mask0_ctrl,
 	},
 	.sources	= &clkset_sclk_dac,
 	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
@@ -527,8 +532,8 @@ static struct clksrc_clk clk_sclk_hdmi = {
 	.clk		= {
 		.name		= "sclk_hdmi",
 		.id		= -1,
-		.enable		= s5pv210_clk_ip1_ctrl,
-		.ctrlbit	= (1 << 11),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 0),
 	},
 	.sources	= &clkset_sclk_hdmi,
 	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
@@ -565,8 +570,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 0,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 4),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 24),
 	},
 	.sources = &clkset_sclk_audio0,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
@@ -594,8 +599,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 1,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 5),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 25),
 	},
 	.sources = &clkset_sclk_audio1,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
@@ -623,8 +628,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 2,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 6),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 26),
 	},
 	.sources = &clkset_sclk_audio2,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
@@ -680,8 +685,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "uclk1",
 			.id		= 0,
-			.ctrlbit	= (1<<17),
-			.enable		= s5pv210_clk_ip3_ctrl,
+			.ctrlbit	= (1 << 12),
+			.enable		= s5pv210_clk_mask0_ctrl,
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
@@ -690,8 +695,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 18),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 13),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
@@ -700,8 +705,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 19),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 14),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
@@ -710,8 +715,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 3,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 20),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 15),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
@@ -720,8 +725,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_mixer",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip1_ctrl,
-			.ctrlbit	= (1 << 9),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 1),
 		},
 		.sources = &clkset_sclk_mixer,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
@@ -738,8 +743,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_fimc",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 24),
+			.enable		= s5pv210_clk_mask1_ctrl,
+			.ctrlbit	= (1 << 2),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
@@ -748,8 +753,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_fimc",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 25),
+			.enable		= s5pv210_clk_mask1_ctrl,
+			.ctrlbit	= (1 << 3),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
@@ -758,8 +763,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_fimc",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 26),
+			.enable		= s5pv210_clk_mask1_ctrl,
+			.ctrlbit	= (1 << 4),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
@@ -768,6 +773,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_cam",
 			.id		= 0,
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 3),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
@@ -776,6 +783,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_cam",
 			.id		= 1,
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 4),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
@@ -784,8 +793,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_fimd",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip1_ctrl,
-			.ctrlbit	= (1 << 0),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 5),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
@@ -794,8 +803,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 16),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 8),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
@@ -804,8 +813,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 17),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 9),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
@@ -814,8 +823,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 18),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 10),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
@@ -824,8 +833,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 3,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 19),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 11),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
@@ -864,8 +873,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_csis",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 31),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 6),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
@@ -874,8 +883,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_spi",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 12),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 16),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
@@ -884,8 +893,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_spi",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 13),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 17),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
@@ -894,8 +903,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_pwi",
 			.id		= -1,
-			.enable		= &s5pv210_clk_ip4_ctrl,
-			.ctrlbit	= (1 << 2),
+			.enable		= &s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 29),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
@@ -904,8 +913,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_pwm",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 23),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 19),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
-- 
1.6.3.3



From eric.miao at canonical.com  Thu Jun 17 05:19:54 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 17 Jun 2010 17:19:54 +0800
Subject: [PATCH 07/10] arm/zImage: don't define unused symbol initrd_phys
In-Reply-To: <1276165636-20150-7-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-7-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <AANLkTilac0HGok-e571zfZTNIoxWEVSweOshwwL_JNnV@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> The only user of initrd_phys is arch/arm/boot/bootp/init.S which still
> gets the value passed to.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

Acked-by: Eric Miao <eric.miao at canonical.com>

> ---
> ?arch/arm/boot/compressed/Makefile | ? ?9 +++------
> ?1 files changed, 3 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
> index 53faa90..5419448 100644
> --- a/arch/arm/boot/compressed/Makefile
> +++ b/arch/arm/boot/compressed/Makefile
> @@ -79,16 +79,13 @@ endif
> ?EXTRA_CFLAGS ?:= -fpic -fno-builtin
> ?EXTRA_AFLAGS ?:= -Wa,-march=all
>
> -# Supply ZRELADDR, INITRD_PHYS and PARAMS_PHYS to the decompressor via
> -# linker symbols. ?We only define initrd_phys and params_phys if the
> -# machine class defined the corresponding makefile variable.
> +# Supply ZRELADDR and PARAMS_PHYS to the decompressor via linker symbols. ?We
> +# only define params_phys if the machine class defined the corresponding
> +# makefile variable.
> ?LDFLAGS_vmlinux := --defsym zreladdr=$(ZRELADDR)
> ?ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
> ?LDFLAGS_vmlinux += --be8
> ?endif
> -ifneq ($(INITRD_PHYS),)
> -LDFLAGS_vmlinux += --defsym initrd_phys=$(INITRD_PHYS)
> -endif
> ?ifneq ($(PARAMS_PHYS),)
> ?LDFLAGS_vmlinux += --defsym params_phys=$(PARAMS_PHYS)
> ?endif
> --
> 1.7.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From ext-phil.2.carmody at nokia.com  Thu Jun 17 05:24:19 2010
From: ext-phil.2.carmody at nokia.com (Phil Carmody)
Date: Thu, 17 Jun 2010 12:24:19 +0300
Subject: [PATCH] arm/include: Fix missing semicolon in module.h
In-Reply-To: <201006161932.00542.PeterHuewe@gmx.de>
References: <201006161932.00542.PeterHuewe@gmx.de>
Message-ID: <20100617092419.GI17639@pcarmody-desktop>

On 16/06/10 19:32 +0200, ext Peter Huewe wrote:
> From: Peter Huewe <peterhuewe at gmx.de>
> 
> This patch fixes a missing semicolon which introduced buildfailures [2] for
> almost every arm defconfig, introduced by patch cecaa4c6b [1]
> 
> This issue arises only if CONFIG_ARM_UNWIND is not set.
> 
> Signed-off-by: Peter Huewe <peterhuewe at gmx.de>

My bad, sorry. 

Acked-by: Phil Carmody <ext-phil.2.carmody at nokia.com>

> ---
> KernelVersion: linux-next-20100616
> References:
> [1] cecaa4c6b ARM: 6172/1: module - additional unwind tables for exit/devexit
> [2] http://kisskb.ellerman.id.au/kisskb/compiler/11/
> [3] http://kisskb.ellerman.id.au/kisskb/buildresult/2725882/
> 
>  arch/arm/include/asm/module.h |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h
> index fcff0d2..cbb0bc2 100644
> --- a/arch/arm/include/asm/module.h
> +++ b/arch/arm/include/asm/module.h
> @@ -26,7 +26,7 @@ struct mod_arch_specific {
>  };
>  #else
>  struct mod_arch_specific {
> -}
> +};
>  #endif
>  
>  /*
> -- 
> 1.6.4.4


From eric.miao at canonical.com  Thu Jun 17 05:28:14 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 17 Jun 2010 17:28:14 +0800
Subject: [PATCH 04/10] arm/zImage: fix comments for cache_on, cache_off 
	and cache_clean_flush
In-Reply-To: <1276165636-20150-4-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-4-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <AANLkTimZeF_tZ6lApQRbRFdPYugb1JbnT8bGfpiOlm3g@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> This adds missing registers to the list of corrupted registers and
> removes a wrong comment about r9 on entry
>
> While at it the formatting of the comment to cache_off is changed to
> resemble the other two.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> ---
> ?arch/arm/boot/compressed/head.S | ? 11 ++++++-----
> ?1 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index 4058294..f8a210b 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -339,9 +339,8 @@ params: ? ? ? ? ? ? ldr ? ? r0, =params_phys
> ?* ?r4 = kernel execution address
> ?* ?r7 = architecture number
> ?* ?r8 = atags pointer
> - * ?r9 = run-time address of "start" ?(???)

OK. r9 is actually loaded with CPUID at the very first of call_cache_fn,
so I seriously doubt its usage on entrance.

> ?* On exit,
> - * ?r1, r2, r3, r9, r10, r12 corrupted
> + * ?r0, r1, r2, r3, r9, r10, r12 corrupted

OK.

> ?* This routine must preserve:
> ?* ?r4, r5, r6, r7, r8
> ?*/
> @@ -774,8 +773,10 @@ proc_types:
> ?* Turn off the Cache and MMU. ?ARMv3 does not support
> ?* reading the control register, but ARMv4 does.
> ?*
> - * On exit, r0, r1, r2, r3, r9, r12 corrupted
> - * This routine must preserve: r4, r6, r7
> + * On exit,
> + * ?r0, r1, r2, r3, r9, r12 corrupted
> + * This routine must preserve:
> + * ?r4, r6, r7

OK, as talked, this looks to align with other comments in this file.

> ?*/
> ? ? ? ? ? ? ? ?.align ?5
> ?cache_off: ? ? mov ? ? r3, #12 ? ? ? ? ? ? ? ? @ cache_off function
> @@ -848,7 +849,7 @@ __armv3_mmu_cache_off:
> ?* Clean and flush the cache to maintain consistency.
> ?*
> ?* On exit,
> - * ?r1, r2, r3, r9, r11, r12 corrupted
> + * ?r1, r2, r3, r9, r10, r11, r12 corrupted

OK, took another look and r10 is corrupted in __armv7_mmu_cache_flush,
where it's used to hold the ID_MMFR1.

> ?* This routine must preserve:
> ?* ?r0, r4, r5, r6, r7
> ?*/

So,

Acked-by: Eric Miao <eric.miao at canonical.com>


From eric.miao at canonical.com  Thu Jun 17 05:37:52 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 17 Jun 2010 17:37:52 +0800
Subject: [PATCH 05/10] arm/zImage: annotate debug functions about 
	corrupted registers
In-Reply-To: <1276165636-20150-5-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-5-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <AANLkTingMRjp-7IUddg7gV9eXVBLRmd598MqH7ykbeCk@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

Not sure if this is absolutely necessary, though.

> ---
> ?arch/arm/boot/compressed/head.S | ? ?4 ++++
> ?1 files changed, 4 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
> index f8a210b..dbeeb56 100644
> --- a/arch/arm/boot/compressed/head.S
> +++ b/arch/arm/boot/compressed/head.S
> @@ -1005,6 +1005,7 @@ __armv3_mpu_cache_flush:
> ?phexbuf: ? ? ? .space ?12
> ? ? ? ? ? ? ? ?.size ? phexbuf, . - phexbuf
>
> +@ phex corrupts {r0, r1, r2, r3}
> ?phex: ? ? ? ? ?adr ? ? r3, phexbuf
> ? ? ? ? ? ? ? ?mov ? ? r2, #0
> ? ? ? ? ? ? ? ?strb ? ?r2, [r3, r1]
> @@ -1019,6 +1020,7 @@ phex: ? ? ? ? ? ? adr ? ? r3, phexbuf
> ? ? ? ? ? ? ? ?strb ? ?r2, [r3, r1]
> ? ? ? ? ? ? ? ?b ? ? ? 1b
>
> +@ puts corrupts {r0, r1, r2, r3}
> ?puts: ? ? ? ? ?loadsp ?r3, r1
> ?1: ? ? ? ? ? ? ldrb ? ?r2, [r0], #1
> ? ? ? ? ? ? ? ?teq ? ? r2, #0
> @@ -1033,12 +1035,14 @@ puts: ? ? ? ? ? loadsp ?r3, r1
> ? ? ? ? ? ? ? ?teq ? ? r0, #0
> ? ? ? ? ? ? ? ?bne ? ? 1b
> ? ? ? ? ? ? ? ?mov ? ? pc, lr
> +@ putc corrupts {r0, r1, r2, r3}
> ?putc:
> ? ? ? ? ? ? ? ?mov ? ? r2, r0
> ? ? ? ? ? ? ? ?mov ? ? r0, #0
> ? ? ? ? ? ? ? ?loadsp ?r3, r1
> ? ? ? ? ? ? ? ?b ? ? ? 2b
>
> +@ memdump corrupts {r0, r1, r2, r3, r10, r11, r12, lr}
> ?memdump: ? ? ? mov ? ? r12, r0
> ? ? ? ? ? ? ? ?mov ? ? r10, lr
> ? ? ? ? ? ? ? ?mov ? ? r11, #0
> --
> 1.7.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

From u.kleine-koenig at pengutronix.de  Thu Jun 17 05:49:31 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 17 Jun 2010 11:49:31 +0200
Subject: [PATCH 05/10] arm/zImage: annotate debug functions about
	corrupted registers
In-Reply-To: <AANLkTingMRjp-7IUddg7gV9eXVBLRmd598MqH7ykbeCk@mail.gmail.com>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-5-git-send-email-u.kleine-koenig@pengutronix.de>
	<AANLkTingMRjp-7IUddg7gV9eXVBLRmd598MqH7ykbeCk@mail.gmail.com>
Message-ID: <20100617094931.GA27312@pengutronix.de>

On Thu, Jun 17, 2010 at 05:37:52PM +0800, Eric Miao wrote:
> 2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> > Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> 
> Not sure if this is absolutely necessary, though.
I had to analyze which registers are corrupted to create the last patch
in the series.  I don't have strong feelings but thought to document my
findings.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From eric.miao at canonical.com  Thu Jun 17 05:50:44 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 17 Jun 2010 17:50:44 +0800
Subject: [PATCH 06/10] arm: remove bit-rotten STANDALONE_DEBUG for 
	decompressor
In-Reply-To: <1276165636-20150-6-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-6-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <AANLkTilN4n8-rgSJYQXHnLBPxg-UHAM3H3nOrlsT0-ej@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> I tried to get this running to debug the regression introduced by
> e7db7b4 without success. ?But this has several problems that make it
> hard to fix:
>
> ?- lib/decompress_inflate.c includes in-kernel headers that make
> ? ?it difficult to compile for user space.
> ?- the binary formats changed both in kernel and user space and
> ? ?at least for the kernel side there isn't only a single
> ? ?variant.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

If it's not fixable, my personal feeling is agree with you to remove it.

> ---
> ?arch/arm/boot/compressed/Makefile.debug | ? 23 -----------------------
> ?arch/arm/boot/compressed/misc.c ? ? ? ? | ? 20 --------------------
> ?2 files changed, 0 insertions(+), 43 deletions(-)
> ?delete mode 100644 arch/arm/boot/compressed/Makefile.debug
>
> diff --git a/arch/arm/boot/compressed/Makefile.debug b/arch/arm/boot/compressed/Makefile.debug
> deleted file mode 100644
> index 491a037..0000000
> --- a/arch/arm/boot/compressed/Makefile.debug
> +++ /dev/null
> @@ -1,23 +0,0 @@
> -#
> -# linux/arch/arm/boot/compressed/Makefile
> -#
> -# create a compressed vmlinux image from the original vmlinux
> -#
> -
> -COMPRESSED_EXTRA=../../lib/ll_char_wr.o
> -OBJECTS=misc-debug.o ll_char_wr.aout.o
> -
> -CFLAGS=-D__KERNEL__ -O2 -DSTDC_HEADERS -DSTANDALONE_DEBUG -Wall -I../../../../include -c
> -
> -test-gzip: piggy.aout.o $(OBJECTS)
> - ? ? ? $(CC) -o $@ $(OBJECTS) piggy.aout.o
> -
> -misc-debug.o: misc.c
> - ? ? ? $(CC) $(CFLAGS) -o $@ misc.c
> -
> -piggy.aout.o: piggy.o
> - ? ? ? arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux piggy.o piggy.aout.o
> -
> -ll_char_wr.aout.o: $(COMPRESSED_EXTRA)
> - ? ? ? arm-linuxelf-objcopy --change-leading-char -I elf32-arm -O arm-aout32-linux $(COMPRESSED_EXTRA) ll_char_wr.aout.o
> -
> diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
> index d2b2ef4..e653a6d 100644
> --- a/arch/arm/boot/compressed/misc.c
> +++ b/arch/arm/boot/compressed/misc.c
> @@ -28,9 +28,6 @@ unsigned int __machine_arch_type;
>
> ?#include <asm/unaligned.h>
>
> -#ifdef STANDALONE_DEBUG
> -#define putstr printf
> -#else
>
> ?static void putstr(const char *ptr);
> ?extern void error(char *x);
> @@ -116,7 +113,6 @@ static void putstr(const char *ptr)
> ? ? ? ?flush();
> ?}
>
> -#endif
>
> ?void *memcpy(void *__dest, __const void *__src, size_t __n)
> ?{
> @@ -186,7 +182,6 @@ asmlinkage void __div0(void)
>
> ?extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
>
> -#ifndef STANDALONE_DEBUG
>
> ?unsigned long
> ?decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
> @@ -211,18 +206,3 @@ decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
> ? ? ? ?putstr(" done, booting the kernel.\n");
> ? ? ? ?return output_ptr;
> ?}
> -#else
> -
> -char output_buffer[1500*1024];
> -
> -int main()
> -{
> - ? ? ? output_data = output_buffer;
> -
> - ? ? ? putstr("Uncompressing Linux...");
> - ? ? ? decompress(input_data, input_data_end - input_data,
> - ? ? ? ? ? ? ? ? ? ? ? NULL, NULL, output_data, NULL, error);
> - ? ? ? putstr("done.\n");
> - ? ? ? return 0;
> -}
> -#endif
> --
> 1.7.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From eric.miao at canonical.com  Thu Jun 17 05:58:42 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Thu, 17 Jun 2010 17:58:42 +0800
Subject: [PATCH 08/10] arm: deprecate support for old way to pass kernel 
	parameters
In-Reply-To: <1276165636-20150-8-git-send-email-u.kleine-koenig@pengutronix.de>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-8-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <AANLkTikNtX5TiPlWOAf_C-HqK7kchZgwi-MQzQqgtush@mail.gmail.com>

2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> This was deprecated in 2001 and announced to live on for 5 years.
>
> For now provide a kernel parameter for those who still need it.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>

Looks OK to me, Acked.

BTW, is there any existing usage of this and can we remove this
completely from now on?

> ---
> ?arch/arm/Kconfig ? ? ? ? | ? ?6 ++++++
> ?arch/arm/kernel/Makefile | ? ?4 +++-
> ?arch/arm/kernel/compat.c | ? ?7 -------
> ?arch/arm/kernel/compat.h | ? ?2 --
> ?arch/arm/kernel/setup.c ?| ? 11 +++++++++++
> ?5 files changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 1f254bd..a53ac65 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1374,6 +1374,12 @@ config UACCESS_WITH_MEMCPY
> ? ? ? ? ?However, if the CPU data cache is using a write-allocate mode,
> ? ? ? ? ?this option is unlikely to provide any performance gain.
>
> +config DEPRECATED_PARAM_STRUCT
> + ? ? ? bool "Provide old way to pass kernel parameters"
> + ? ? ? help
> + ? ? ? ? This was deprecated in 2001 and announced to live on for 5 years.
> + ? ? ? ? Some old boot loaders still use this way.
> +
> ?endmenu
>
> ?menu "Boot options"
> diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
> index 26d302c..021f72d 100644
> --- a/arch/arm/kernel/Makefile
> +++ b/arch/arm/kernel/Makefile
> @@ -13,10 +13,12 @@ CFLAGS_REMOVE_return_address.o = -pg
>
> ?# Object file lists.
>
> -obj-y ? ? ? ? ?:= compat.o elf.o entry-armv.o entry-common.o irq.o \
> +obj-y ? ? ? ? ?:= elf.o entry-armv.o entry-common.o irq.o \
> ? ? ? ? ? ? ? ? ? process.o ptrace.o return_address.o setup.o signal.o \
> ? ? ? ? ? ? ? ? ? sys_arm.o stacktrace.o time.o traps.o
>
> +obj-$(CONFIG_DEPRECATED_PARAM_STRUCT) += compat.o
> +
> ?obj-$(CONFIG_LEDS) ? ? ? ? ? ? += leds.o
> ?obj-$(CONFIG_OC_ETM) ? ? ? ? ? += etm.o
>
> diff --git a/arch/arm/kernel/compat.c b/arch/arm/kernel/compat.c
> index 0a13854..9256523 100644
> --- a/arch/arm/kernel/compat.c
> +++ b/arch/arm/kernel/compat.c
> @@ -217,10 +217,3 @@ void __init convert_to_tag_list(struct tag *tags)
> ? ? ? ?struct param_struct *params = (struct param_struct *)tags;
> ? ? ? ?build_tag_list(params, &params->u2);
> ?}
> -
> -void __init squash_mem_tags(struct tag *tag)
> -{
> - ? ? ? for (; tag->hdr.size; tag = tag_next(tag))
> - ? ? ? ? ? ? ? if (tag->hdr.tag == ATAG_MEM)
> - ? ? ? ? ? ? ? ? ? ? ? tag->hdr.tag = ATAG_NONE;
> -}
> diff --git a/arch/arm/kernel/compat.h b/arch/arm/kernel/compat.h
> index 27e61a6..39264ab 100644
> --- a/arch/arm/kernel/compat.h
> +++ b/arch/arm/kernel/compat.h
> @@ -9,5 +9,3 @@
> ?*/
>
> ?extern void convert_to_tag_list(struct tag *tags);
> -
> -extern void squash_mem_tags(struct tag *tag);
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index 122d999..cbc6ddb 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -44,7 +44,9 @@
> ?#include <asm/traps.h>
> ?#include <asm/unwind.h>
>
> +#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
> ?#include "compat.h"
> +#endif
> ?#include "atags.h"
> ?#include "tcm.h"
>
> @@ -663,6 +665,13 @@ static int __init customize_machine(void)
> ?}
> ?arch_initcall(customize_machine);
>
> +static void __init squash_mem_tags(struct tag *tag)
> +{
> + ? ? ? for (; tag->hdr.size; tag = tag_next(tag))
> + ? ? ? ? ? ? ? if (tag->hdr.tag == ATAG_MEM)
> + ? ? ? ? ? ? ? ? ? ? ? tag->hdr.tag = ATAG_NONE;
> +}
> +
> ?void __init setup_arch(char **cmdline_p)
> ?{
> ? ? ? ?struct tag *tags = (struct tag *)&init_tags;
> @@ -683,12 +692,14 @@ void __init setup_arch(char **cmdline_p)
> ? ? ? ?else if (mdesc->boot_params)
> ? ? ? ? ? ? ? ?tags = phys_to_virt(mdesc->boot_params);
>
> +#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
> ? ? ? ?/*
> ? ? ? ? * If we have the old style parameters, convert them to
> ? ? ? ? * a tag list.
> ? ? ? ? */
> ? ? ? ?if (tags->hdr.tag != ATAG_CORE)
> ? ? ? ? ? ? ? ?convert_to_tag_list(tags);
> +#endif
> ? ? ? ?if (tags->hdr.tag != ATAG_CORE)
> ? ? ? ? ? ? ? ?tags = (struct tag *)&init_tags;
>
> --
> 1.7.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From alexander.stein at systec-electronic.com  Thu Jun 17 06:30:37 2010
From: alexander.stein at systec-electronic.com (Alexander Stein)
Date: Thu, 17 Jun 2010 12:30:37 +0200
Subject: invalid address for enqueue_task
Message-ID: <201006171230.38101.alexander.stein@systec-electronic.com>

Hello,

I've been redirecting to this mailing list after mailing to Ingo Molnar.
On several AT91SAM9G20 (arm9) based boards i get the following kernel panic 
message:

Unable to handle kernel paging request at virtual address f0bc5a20                                                                           
pgd = c1e7c000                                                                                                                                                   
[f0bc5a20] *pgd=00000000                                                                                                                                         
Internal error: Oops: 0 [#1]                                                                                                                                     
Modules linked in:                                                                                                                                               
CPU: 0    Not tainted  (2.6.31.12 #3)                                                                                                                            
PC is at 0xf0bc5a20                                                                                                                                              
LR is at enqueue_task+0x28/0x34                                                                                                                                  
pc : [<f0bc5a20>]    lr : [<c0031108>]    psr: 200000b3                                                                                                          
sp : c1e0de38  ip : 00000000  fp : c1e0de4c                                                                                                                      
r10: 00005b2a  r9 : 7fffffff  r8 : ffffffff                                                                                                                      
r7 : 00000187  r6 : 197f8400  r5 : c1d9b0c0  r4 : c1d9b0c0                                                                                                       
r3 : c023ccd8  r2 : 00000001  r1 : c1d9b0c0  r0 : c030d480                                                                                                       
Flags: nzCv  IRQs off  FIQs on  Mode SVC_32  ISA Thumb  Segment user
Control: 0005317f  Table: 21e7c000  DAC: 00000015
Process gpsnewag (pid: 482, stack limit = 0xc1e0c270)
Stack: (0xc1e0de38 to 0xc1e0e000)
de20:                                                       00000001 c030d480
de40: 00000000 00000001 c1e0de5c c00311cc c030d480 c1d9b0c0 c1e0de7c c0033614
de60: 60000093 a0000093 c1e4df28 c030f408 c030f3b8 c004e26c 3a2cdb8c c004e28c
de80: ffffffff c004e57c 00000000 00000001 c0326430 3a2cdb8c c030f408 c004f118
dea0: 00000000 c030f408 0d8566c7 4c192744 0000004e 00005b2a 3a2cdb8c 00005b2a
dec0: befaccfc c0326480 00000000 00000000 00000013 c0026e84 c1e0c000 401a0b60
dee0: befaccfc c01b3ec8 ffffffff c0065bcc ffffffff c0310a1c 00000013 c0310a58
df00: c0326480 c006749c 00000013 00000000 00000013 0000004e c0026e84 c0026068
df20: 60000013 ffffffff fefff000 c0026994 befaccd8 c1e0df90 00000004 00000000
df40: 00000000 befaccd8 c1e0df90 0000004e c0026e84 c1e0c000 401a0b60 befaccfc
df60: 00000000 c1e0df7c c003bd0c c012dc34 60000013 ffffffff c1e0c000 befaccd8
df80: 00000008 00000000 00000000 c003bd0c 4c192744 0003760f befacce8 00000140
dfa0: 00000000 c0026d00 befacce8 00000140 befaccd8 00000000 00000000 befacce8
dfc0: befacce8 00000140 00000000 0000004e 00000000 00000000 401a0b60 befaccfc
dfe0: 00000000 befaccd8 400eb3fc 400eb42c 60000010 befaccd8 00000000 00000000
Code: bad PC value.
Kernel panic - not syncing: Fatal exception in interrupt
[<c002b86c>] (unwind_backtrace+0x0/0xd4) from [<c0237580>] (panic+0x40/0x118)
[<c0237580>] (panic+0x40/0x118) from [<c002a6b8>] (die+0xa8/0xc8)
[<c002a6b8>] (die+0xa8/0xc8) from [<c002c974>] (__do_kernel_fault+0x64/0x74)
[<c002c974>] (__do_kernel_fault+0x64/0x74) from [<c002cb9c>] 
(do_translation_fault+0x68/0x74)
[<c002cb9c>] (do_translation_fault+0x68/0x74) from [<c0026a6c>] 
(__pabt_svc+0x4c/0x80)
[<c0026a6c>] (__pabt_svc+0x4c/0x80) from [<f0bc5a20>] (0xf0bc5a20)

After doing some research I found out that sched_class inside struct_task has 
been modified to some bogus address so sched_class->enqueue_task 
(kernel/sched.c:1886) jumps to some invalid address.
I also tried using the 2.6.34 kernel which results in quite the same problem.

BUG: sleeping function called from invalid context at mm/slub.c:1705                                                                                   
in_atomic(): 1, irqs_disabled(): 128, pid: 484, name: gpsnewag                                                                                                   
1 lock held by gpsnewag/484:                                                                                                                                     
 #0:  (&rq->lock){......}, at: [<c0030d20>] task_rq_lock+0x60/0x78                                                                                               
[<c002a7d8>] (unwind_backtrace+0x0/0xec) from [<c008fdc8>] 
(kmem_cache_alloc+0x38/0xc0)                                                                          
[<c008fdc8>] (kmem_cache_alloc+0x38/0xc0) from [<c0233024>] 
(generic_create_cred+0x14/0xe8)                                                                      
[<c0233024>] (generic_create_cred+0x14/0xe8) from [<c0232630>] 
(rpcauth_lookup_credcache+0x128/0x2a0)                                                            
[<c0232630>] (rpcauth_lookup_credcache+0x128/0x2a0) from [<c0232420>] 
(rpcauth_lookupcred+0xa0/0xe8)                                                             
[<c0232420>] (rpcauth_lookupcred+0xa0/0xe8) from [<c00f3e2c>] 
(nfs_open+0xc/0x64)                                                                                
[<c00f3e2c>] (nfs_open+0xc/0x64) from [<c002ff38>] (enqueue_task+0x28/0x34)                                                                                      
^^^^
A valid but wrong pointer obviously here!

[<c002ff38>] (enqueue_task+0x28/0x34) from [<c0030000>] 
(activate_task+0x38/0x44)                                                                                
[<c0030000>] (activate_task+0x38/0x44) from [<c00327b0>] 
(try_to_wake_up+0x60/0xf0)                                                                              
[<c00327b0>] (try_to_wake_up+0x60/0xf0) from [<c004f0ac>] 
(hrtimer_wakeup+0x20/0x28)                                                                             
[<c004f0ac>] (hrtimer_wakeup+0x20/0x28) from [<c004f3ec>] 
(__run_hrtimer+0x50/0xa4)                                                                              
[<c004f3ec>] (__run_hrtimer+0x50/0xa4) from [<c004f578>] 
(hrtimer_interrupt+0x138/0x310)                                                                         
[<c004f578>] (hrtimer_interrupt+0x138/0x310) from [<c01bb690>] 
(ch2_irq+0x20/0x28)                                                                               
[<c01bb690>] (ch2_irq+0x20/0x28) from [<c006817c>] 
(handle_IRQ_event+0x24/0xc4)                                                                                  
[<c006817c>] (handle_IRQ_event+0x24/0xc4) from [<c0069e10>] 
(handle_level_irq+0xb8/0x134)                                                                        
[<c0069e10>] (handle_level_irq+0xb8/0x134) from [<c002506c>] 
(asm_do_IRQ+0x6c/0x98)                                                                              
[<c002506c>] (asm_do_IRQ+0x6c/0x98) from [<c00259f4>] (__irq_svc+0x34/0x60)                                                                                      
Exception stack(0xc1e6df20 to 0xc1e6df68)                                                                                                                        
df20: beaefcdc c1e6df98 ffffffe8 00000000 00000000 beaefcd8 c1e6df90 0000004e                                                                                    
df40: 4752a851 c1e6c000 401a0b60 beaefcfc 00000018 c1e6df6c 0005c228 c01314f4                                                                                    
df60: 00000013 ffffffff                                                                                                                                          
[<c00259f4>] (__irq_svc+0x34/0x60) from [<c01314f4>] 
(__copy_to_user_std+0xd4/0x3a8)                     

Again sched_class is destroyed again. This problem only occurs after several 
hours of run time (5h or more). Sometimes only 30min.
Have you any idea which could cause such a problem? Do you need more 
information?

Best regards
Alexander


From jason77.wang at gmail.com  Thu Jun 17 09:34:09 2010
From: jason77.wang at gmail.com (jason)
Date: Thu, 17 Jun 2010 21:34:09 +0800
Subject: [PATCH 0/4]Refine iomux files for i.MX51
In-Reply-To: <20100616064723.GH20799@pengutronix.de>
References: <1276352559-8105-1-git-send-email-jason77.wang@gmail.com>
	<20100616064723.GH20799@pengutronix.de>
Message-ID: <4C1A2451.1070101@gmail.com>

Sascha Hauer wrote:
> On Sat, Jun 12, 2010 at 10:22:35PM +0800, Jason Wang wrote:
>   
>> Through the discussion, I divide my patches to 3 parts.
>> part1: mx51 iomux related part, the first patch in this part is from
>>        Amit, other patches are based off this patch and they are some
>>        fix or adding definitions for imx51_3ds board.
>>     
>
> This is ok now. Can you please rebase onto
> git://git.pengutronix.de/git/imx/linux-2.6.git imx-for-2.6.36
>
> The first patch conflicts with another of your patches:
>
> e5ceef78 mx5: Add i2c to Freescale MX51 Babbage HW
>
>
>   
OK, i will use Amit's new patch and test it based on your repository.

Thanks,
Jason.




From jason77.wang at gmail.com  Thu Jun 17 09:37:50 2010
From: jason77.wang at gmail.com (jason)
Date: Thu, 17 Jun 2010 21:37:50 +0800
Subject: [PATCH 1/2] mxc: add common debug board for 3-stack platforms
In-Reply-To: <20100616065540.GI20799@pengutronix.de>
References: <1276352707-8199-1-git-send-email-jason77.wang@gmail.com>
	<1276352707-8199-2-git-send-email-jason77.wang@gmail.com>
	<20100616065540.GI20799@pengutronix.de>
Message-ID: <4C1A252E.8090101@gmail.com>

Sascha Hauer wrote:
> On Sat, Jun 12, 2010 at 10:25:06PM +0800, Jason Wang wrote:
>   
>> The debug board is little different for all mxc 3-stack(PDK)
>> platforms, it is possible here to add a common implementation to
>> support this board.
>>     
>
> Two small things left:
>
> Could you change the name cpld_debugboard.c to something like
> 3ds_debugboard.c? That we are talking about the 3ds is much more
> interesting than that there's a cpld on the board.
>
> Also, I really prefer having no extra header file for the debug board.
> All information in this header file is only interesting in this single C
> file.
>
> Sascha
>
>
>   
Accept, will fix in next version.

Thanks,
Jason.
>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>> ---
>>  arch/arm/plat-mxc/Kconfig                        |   11 ++
>>  arch/arm/plat-mxc/Makefile                       |    1 +
>>  arch/arm/plat-mxc/cpld_debugboard.c              |  161 ++++++++++++++++++++++
>>  arch/arm/plat-mxc/include/mach/cpld_debugboard.h |   60 ++++++++
>>  4 files changed, 233 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/plat-mxc/cpld_debugboard.c
>>  create mode 100644 arch/arm/plat-mxc/include/mach/cpld_debugboard.h
>>     
<snip>


From jekhor at gmail.com  Thu Jun 17 10:50:21 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Thu, 17 Jun 2010 17:50:21 +0300
Subject: [PATCH] SMDK2416: Select MACH_SMDK, S3C_DEV_NAND, S3C_DEV_USB_HOST
Message-ID: <1276786221-29640-1-git-send-email-jekhor@gmail.com>

Enable compilation of platform devices and initialization code used in
SMDK2416 board file.

Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
---
 arch/arm/mach-s3c2416/Kconfig |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
index 657e4fe..eafb0ed 100644
--- a/arch/arm/mach-s3c2416/Kconfig
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -30,9 +30,12 @@ menu "S3C2416 Machines"
 config MACH_SMDK2416
 	bool "SMDK2416"
 	select CPU_S3C2416
+	select MACH_SMDK
 	select S3C_DEV_FB
 	select S3C_DEV_HSMMC
 	select S3C_DEV_HSMMC1
+	select S3C_DEV_NAND
+	select S3C_DEV_USB_HOST
 	help
 	  Say Y here if you are using an SMDK2416
 
-- 
1.6.6.1



From sumeet4linux at gmail.com  Thu Jun 17 10:08:45 2010
From: sumeet4linux at gmail.com (sumeet linux)
Date: Thu, 17 Jun 2010 19:38:45 +0530
Subject: [Question] SuspendToDisk Feature on ARM ?
Message-ID: <AANLkTinXqVqe9xWQYj-CyzPHl9k7qAqxX6ueOqB3qTve@mail.gmail.com>

Hi List,

Does there exists a support for Suspend To Disk (Hibernate) for ARM
platforms?
I have been googling for it but could not find any information other than
some links to the suspend2 support for some ancient kernels.
Can anyone provide any clue on how much effort is required to implement this
feature to ARM architecture ?

Thanks in advance.

Regards,
Sumeet
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From eric at eukrea.com  Thu Jun 17 12:25:24 2010
From: eric at eukrea.com (=?UTF-8?B?RXJpYyBCw6luYXJk?=)
Date: Thu, 17 Jun 2010 18:25:24 +0200
Subject: Hung kernel on SD writeback while suspending to RAM
In-Reply-To: <AANLkTikHHcnJygPWKAlDk4NWGBE_fxexeLt3WO0xea0M@mail.gmail.com>
References: <AANLkTikHHcnJygPWKAlDk4NWGBE_fxexeLt3WO0xea0M@mail.gmail.com>
Message-ID: <4C1A4C74.1040008@eukrea.com>

Hi,

Le 15/06/2010 09:58, Alex Gonzalez a ?crit :
> I am looking into suspend to RAM on a Freescale MX51 running a 2.6.31
> kernel. The
> system suspends and resumes OK except when an SD card is mounted.
>
> What happens then is that it finds a page which is being written to disk
> (writeback flag is set), so it waits forever in uninterruptible state
> for the write to finish, which never happens.
>
> I was expecting the filesystem sync previous to the tasks freezing to
> have written all page caches to disk.
>
> Any suggestion as to how to debug this forward?
>
I think you need to enable
[ ] Assume MMC/SD cards are non-removable (DANGEROUS)
in order to be able to suspend / resume a mounted SDCard.

Eric


From fernando.lugo at ti.com  Thu Jun 17 12:42:41 2010
From: fernando.lugo at ti.com (Guzman Lugo, Fernando)
Date: Thu, 17 Jun 2010 11:42:41 -0500
Subject: [PATCH] mailbox: change full flag per mailbox queue instead of
	global
In-Reply-To: <AANLkTimQrOIbsvQw7yv2x_KJmsv2p5KfNdcsNk2_DWGm@mail.gmail.com>
References: <1276534269-19179-1-git-send-email-x0095840@ti.com>
	<AANLkTimQrOIbsvQw7yv2x_KJmsv2p5KfNdcsNk2_DWGm@mail.gmail.com>
Message-ID: <496565EC904933469F292DDA3F1663E602CBC9385B@dlee06.ent.ti.com>

Hi Ohad,

> -----Original Message-----
> From: Ohad Ben-Cohen [mailto:ohad at wizery.com]
> Sent: Wednesday, June 16, 2010 4:18 PM
> To: Guzman Lugo, Fernando
> Cc: linux-arm-kernel at lists.infradead.org; linux-omap at vger.kernel.org;
> hiroshi.doyu at nokia.com
> Subject: Re: [PATCH] mailbox: change full flag per mailbox queue instead
> of global
> 
> On Mon, Jun 14, 2010 at 11:51 AM, Fernando Guzman Lugo <x0095840 at ti.com>
> wrote:
> > As pointed by Ben Ohand, the variable rq_full flag is a global
> > variable, so if there are multiple mailbox users there will be
> > conflics. Now there is a full flag per mailbox queue.
> >
> > Reported-by: Ohad Ben-Cohen <ohad at wizery.com>
> > Signed-off-by: Fernando Guzman Lugo <x0095840 at ti.com>
> > ---
> > ?arch/arm/plat-omap/include/plat/mailbox.h | ? ?1 +
> > ?arch/arm/plat-omap/mailbox.c ? ? ? ? ? ? ?| ? ?7 +++----
> > ?2 files changed, 4 insertions(+), 4 deletions(-)
> 
> 
> Thanks, Fernando, it looks good !
> 
> Since the original patch wasn't merged yet, it might make more sense
> to squash it with this fix into a single patch, instead of introducing
> this fix as a new patch. what do you think ?

Sound good. I will send that patch again then. Please discard this pathc.

Regards,
Fernando.

> 
> >
> > diff --git a/arch/arm/plat-omap/include/plat/mailbox.h b/arch/arm/plat-
> omap/include/plat/mailbox.h
> > index 729166b..a6144b8 100644
> > --- a/arch/arm/plat-omap/include/plat/mailbox.h
> > +++ b/arch/arm/plat-omap/include/plat/mailbox.h
> > @@ -47,6 +47,7 @@ struct omap_mbox_queue {
> > ? ? ? ?struct tasklet_struct ? tasklet;
> > ? ? ? ?int ? ? (*callback)(void *);
> > ? ? ? ?struct omap_mbox ? ? ? ?*mbox;
> > + ? ? ? bool ? ?full;
> > ?};
> >
> > ?struct omap_mbox {
> > diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
> > index 8d86b0b..a1e274e 100644
> > --- a/arch/arm/plat-omap/mailbox.c
> > +++ b/arch/arm/plat-omap/mailbox.c
> > @@ -30,7 +30,6 @@
> >
> > ?static struct omap_mbox *mboxes;
> > ?static DEFINE_RWLOCK(mboxes_lock);
> > -static bool rq_full;
> >
> > ?static int mbox_configured;
> > ?static DEFINE_MUTEX(mbox_configured_lock);
> > @@ -140,9 +139,9 @@ static void mbox_rx_work(struct work_struct *work)
> > ? ? ? ?while (1) {
> > ? ? ? ? ? ? ? ?spin_lock_irqsave(q->queue_lock, flags);
> > ? ? ? ? ? ? ? ?rq = blk_fetch_request(q);
> > - ? ? ? ? ? ? ? if (rq_full) {
> > + ? ? ? ? ? ? ? if (mbox->rxq->full) {
> > ? ? ? ? ? ? ? ? ? ? ? ?omap_mbox_enable_irq(mbox, IRQ_RX);
> > - ? ? ? ? ? ? ? ? ? ? ? rq_full = false;
> > + ? ? ? ? ? ? ? ? ? ? ? mbox->rxq->full = false;
> > ? ? ? ? ? ? ? ?}
> > ? ? ? ? ? ? ? ?spin_unlock_irqrestore(q->queue_lock, flags);
> > ? ? ? ? ? ? ? ?if (!rq)
> > @@ -183,7 +182,7 @@ static void __mbox_rx_interrupt(struct omap_mbox
> *mbox)
> > ? ? ? ? ? ? ? ?rq = blk_get_request(q, WRITE, GFP_ATOMIC);
> > ? ? ? ? ? ? ? ?if (unlikely(!rq)) {
> > ? ? ? ? ? ? ? ? ? ? ? ?omap_mbox_disable_irq(mbox, IRQ_RX);
> > - ? ? ? ? ? ? ? ? ? ? ? rq_full = true;
> > + ? ? ? ? ? ? ? ? ? ? ? mbox->rxq->full = true;
> > ? ? ? ? ? ? ? ? ? ? ? ?goto nomem;
> > ? ? ? ? ? ? ? ?}
> >
> > --
> > 1.6.3.3
> >
> >


From mattjreimer at gmail.com  Thu Jun 17 12:54:19 2010
From: mattjreimer at gmail.com (Matt Reimer)
Date: Thu, 17 Jun 2010 09:54:19 -0700
Subject: Hung kernel on SD writeback while suspending to RAM
In-Reply-To: <4C1A4C74.1040008@eukrea.com>
References: <AANLkTikHHcnJygPWKAlDk4NWGBE_fxexeLt3WO0xea0M@mail.gmail.com>
	<4C1A4C74.1040008@eukrea.com>
Message-ID: <AANLkTiml6DjWuP-_YEu3J6qRNYbogM52wa8mSHIuqY-z@mail.gmail.com>

On Thu, Jun 17, 2010 at 9:25 AM, Eric B?nard <eric at eukrea.com> wrote:
> Hi,
>
> Le 15/06/2010 09:58, Alex Gonzalez a ?crit :
>>
>> I am looking into suspend to RAM on a Freescale MX51 running a 2.6.31
>> kernel. The
>> system suspends and resumes OK except when an SD card is mounted.
>>
>> What happens then is that it finds a page which is being written to disk
>> (writeback flag is set), so it waits forever in uninterruptible state
>> for the write to finish, which never happens.
>>
>> I was expecting the filesystem sync previous to the tasks freezing to
>> have written all page caches to disk.
>>
>> Any suggestion as to how to debug this forward?
>>
> I think you need to enable
> [ ] Assume MMC/SD cards are non-removable (DANGEROUS)
> in order to be able to suspend / resume a mounted SDCard.

Also see the thread "[PATCH] Fix the outstanding issue with hangs on
insert/removal of mmc cards" on linux-mmc:

http://article.gmane.org/gmane.linux.kernel.mmc/2233

Matt


From jdzheng at broadcom.com  Thu Jun 17 13:14:57 2010
From: jdzheng at broadcom.com (JD (Jiandong) Zheng)
Date: Thu, 17 Jun 2010 10:14:57 -0700
Subject: [PATCH] MAINTAINERS: Change BCMRING maintainer
In-Reply-To: <AANLkTink0mz5pS-QE0v7-_xXl_SXhY_Bx9ZH0PGUlUiz@mail.gmail.com>
References: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E3F7@SJEXCHCCR02.corp.ad.broadcom.com>
	<AANLkTil6o6tHQdDM0YQRgxme3VLVuk8HUOzqscxsBQBi@mail.gmail.com>
	<1276655981.1586.172.camel@Joe-Laptop.home>
	<AANLkTilI2toj42vZcHzPC4ru82CDMf2UWsTasPyOD3Nh@mail.gmail.com>
	<8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E57D@SJEXCHCCR02.corp.ad.broadcom.com>
	<AANLkTink0mz5pS-QE0v7-_xXl_SXhY_Bx9ZH0PGUlUiz@mail.gmail.com>
Message-ID: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC69DDF19@SJEXCHCCR02.corp.ad.broadcom.com>

> Guess the first rule is wrap your line to less than 80 characters since
> that really improves readability, and there are a lot geeks out there
> using console based email clients :-)
Thanks for this!

I know it is better to use git to create patch in the future and seems 
I just need to clone linus' release tree 
(git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git) 
instead of arm linux tree (linux-arm.org/linux-2.6-stable.git) to 
make change and create patches, is this correct understanding?

Thanks,
JD

From linux at arm.linux.org.uk  Thu Jun 17 14:40:22 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 17 Jun 2010 19:40:22 +0100
Subject: [PATCH] MAINTAINERS: Change BCMRING maintainer
In-Reply-To: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC69DDF19@SJEXCHCCR02.corp.ad.broadcom.com>
References: <8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E3F7@SJEXCHCCR02.corp.ad.broadcom.com>
	<AANLkTil6o6tHQdDM0YQRgxme3VLVuk8HUOzqscxsBQBi@mail.gmail.com>
	<1276655981.1586.172.camel@Joe-Laptop.home>
	<AANLkTilI2toj42vZcHzPC4ru82CDMf2UWsTasPyOD3Nh@mail.gmail.com>
	<8628FE4E7912BF47A96AE7DD7BAC0AADDDC694E57D@SJEXCHCCR02.corp.ad.broadcom.com>
	<AANLkTink0mz5pS-QE0v7-_xXl_SXhY_Bx9ZH0PGUlUiz@mail.gmail.com>
	<8628FE4E7912BF47A96AE7DD7BAC0AADDDC69DDF19@SJEXCHCCR02.corp.ad.broadcom.com>
Message-ID: <20100617184022.GA7973@n2100.arm.linux.org.uk>

On Thu, Jun 17, 2010 at 10:14:57AM -0700, JD (Jiandong) Zheng wrote:
> I know it is better to use git to create patch in the future and seems 
> I just need to clone linus' release tree 
> (git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git) 
> instead of arm linux tree (linux-arm.org/linux-2.6-stable.git) to 
> make change and create patches, is this correct understanding?

Note that the linux-arm tree is ARM Ltd's tree, and isn't a tree which
feeds directly into Linus' tree.  You can find that via
http://www.arm.linux.org.uk/developer/ but I suggest that you use
Linus' tree as a base line unless I have something which conflicts
in my tree.

I maintain three primary branches:
- master, for stuff scheduled for -rc
- devel, for stuff scheduled for the next merge window, and is unstable
  (iow, commits don't have a stable ID, so it is inadvisable to base
   work off this.)
- devel-stable, for stuff scheduled for the next merge window, where the
  commits are immutable.


From erik.oomen at zepcam.com  Thu Jun 17 14:51:37 2010
From: erik.oomen at zepcam.com (Erik Oomen)
Date: Thu, 17 Jun 2010 20:51:37 +0200
Subject: mxcmmc driver hangs on sync
In-Reply-To: <20100617163340.69409a3f@morgan>
References: <20100615112936.5d03ce92@morgan>
	<20100615063142.GU17833@buzzloop.caiaq.de>
	<20100615152051.26e4589c@morgan>
	<20100615072237.GW17833@buzzloop.caiaq.de>
	<20100617163340.69409a3f@morgan>
Message-ID: <45DEC573-1158-477E-A971-03CB4633F442@zepcam.com>

Morgan,

> Daniel,
> 
> On Tue, 15 Jun 2010 09:22:37 +0200
> Daniel Mack <daniel at caiaq.de> wrote:
>> On Tue, Jun 15, 2010 at 03:20:51PM +0800, Morgan Howe wrote:
>>> On Tue, 15 Jun 2010 08:31:43 +0200
>>> Daniel Mack <daniel at caiaq.de> wrote:
>>>> On Tue, Jun 15, 2010 at 11:29:36AM +0800, Morgan Howe wrote:
>>>>> With the older kernel this would hang on sync after a few
>>>>> thousand loops, and much sooner if you ran 2 or 3 of these
>>>>> processes at a time. I tried last night with the newer kernel
>>>>> and kicking off 3 processes and after ~100-150 loops per
>>>>> process I get this:
>>>> 
>>>> Which 'newer kernel' did you try?
>>> 
>>> Hey Daniel,
>>> 
>>> Sorry, I said current mainline, but actually it's 2.6.35-rc1.
>> 
>> Could you try two things:
>> 
>> a) build a kernel without MX2 DMA support
>> b) try 2.6.34, as there were some updates to the mxcmmc driver after
>>   2.6.34 which could be related

We've had the same problems for various kernels and mxcmmc modifications. The following fixed it.  We applied it to the 2.6.28 kernel and have been writing and reading *many* Gigabytes without a problem. 

diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
index e16014b..f295d68 100644
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
@@ -653,7 +653,9 @@ static void dma_irq_handle_channel(int chno)
 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 {
        int i, disr;
+       unsigned long flags;
 
+       local_irq_save(flags); 
 #ifdef CONFIG_ARCH_MX2
        if (cpu_is_mx21() || cpu_is_mx27())
                dma_err_handler(irq, dev_id);
@@ -669,7 +671,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
                if (disr & (1 << i))
                        dma_irq_handle_channel(i);
        }
-
+       local_irq_restore(flags);
        return IRQ_HANDLED;
 }
 
Regards,
  Erik




From eric at eukrea.com  Thu Jun 17 14:59:01 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Thu, 17 Jun 2010 20:59:01 +0200
Subject: [PATCH v2] input/imx_keypad: add PM support
Message-ID: <1276801147-4103-1-git-send-email-eric@eukrea.com>

We use keypad_data to enable wakeup from platform data

suspend/resume is tested on an i.MX27 when keypad is not
in use and when it's is in use (in which case we immediatly
get the key pressed at wakeup)

Signed-off-by: Eric B?nard <eric at eukrea.com>
Cc: maramaopercheseimorto at gmail.com
Cc: linux-input at vger.kernel.org
Cc: dmitry.torokhov at gmail.com
Cc: linux-arm-kernel at lists.infradead.org
---
v2 :
	- simplify suspend & resume functions
	- convert to pm_ops

 drivers/input/keyboard/imx_keypad.c |   40 +++++++++++++++++++++++++++++++++-
 1 files changed, 38 insertions(+), 2 deletions(-)

diff --git a/drivers/input/keyboard/imx_keypad.c b/drivers/input/keyboard/imx_keypad.c
index d92c15c..9aa0005 100644
--- a/drivers/input/keyboard/imx_keypad.c
+++ b/drivers/input/keyboard/imx_keypad.c
@@ -364,6 +364,38 @@ static void imx_keypad_inhibit(struct imx_keypad *keypad)
 	writew(0xff00, keypad->mmio_base + KPCR);
 }
 
+#ifdef CONFIG_PM
+static int mxc_kpp_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct imx_keypad *keypad = platform_get_drvdata(pdev);
+
+	keypad->enabled = false;
+	synchronize_irq(keypad->irq);
+	disable_irq(keypad->irq);
+	clk_disable(keypad->clk);
+
+	return 0;
+}
+
+static int mxc_kpp_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct imx_keypad *keypad = platform_get_drvdata(pdev);
+
+	keypad->enabled = true;
+	clk_enable(keypad->clk);
+	enable_irq(keypad->irq);
+
+	return 0;
+}
+
+static const struct dev_pm_ops mxc_kpp_pm_ops = {
+	.suspend	= mxc_kpp_suspend,
+	.resume		= mxc_kpp_resume,
+};
+#endif
+
 static void imx_keypad_close(struct input_dev *dev)
 {
 	struct imx_keypad *keypad = input_get_drvdata(dev);
@@ -410,7 +442,8 @@ open_err:
 
 static int __devinit imx_keypad_probe(struct platform_device *pdev)
 {
-	const struct matrix_keymap_data *keymap_data = pdev->dev.platform_data;
+	const struct matrix_keypad_platform_data *keypad_data = pdev->dev.platform_data;
+	const struct matrix_keymap_data *keymap_data = keypad_data->keymap_data;
 	struct imx_keypad *keypad;
 	struct input_dev *input_dev;
 	struct resource *res;
@@ -525,7 +558,7 @@ static int __devinit imx_keypad_probe(struct platform_device *pdev)
 	}
 
 	platform_set_drvdata(pdev, keypad);
-	device_init_wakeup(&pdev->dev, 1);
+	device_init_wakeup(&pdev->dev, keypad_data->wakeup);
 
 	return 0;
 
@@ -571,6 +604,9 @@ static struct platform_driver imx_keypad_driver = {
 	.driver		= {
 		.name	= "imx-keypad",
 		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &mxc_kpp_pm_ops,
+#endif
 	},
 	.probe		= imx_keypad_probe,
 	.remove		= __devexit_p(imx_keypad_remove),
-- 
1.6.3.3



From eric at eukrea.com  Thu Jun 17 14:59:02 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Thu, 17 Jun 2010 20:59:02 +0200
Subject: [PATCH] eukrea_mbimx27: update keyboard platform data
In-Reply-To: <1276801147-4103-1-git-send-email-eric@eukrea.com>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>
Message-ID: <1276801147-4103-2-git-send-email-eric@eukrea.com>

use matrix_keypad_platform_data
enable wakeup

Signed-off-by: Eric B?nard <eric at eukrea.com>
Cc: s.hauer at pengutronix.de
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
index 80f6268..e7fd65a 100644
--- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
@@ -116,6 +116,11 @@ static struct matrix_keymap_data eukrea_mbimx27_keymap_data = {
 	.keymap_size    = ARRAY_SIZE(eukrea_mbimx27_keymap),
 };
 
+static struct matrix_keypad_platform_data eukrea_mbimx27_keypad_data = {
+	.keymap_data	= &eukrea_mbimx27_keymap_data,
+	.wakeup		= 1,
+};
+
 static struct gpio_led gpio_leds[] = {
 	{
 		.name			= "led1",
@@ -392,7 +397,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
 	gpio_request(GPIO_PORTA | 25, "lcd_enable");
 	platform_device_register(&eukrea_mbimx27_lcd_powerdev);
 
-	mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data);
+	mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keypad_data);
 
 	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
-- 
1.6.3.3



From eric at eukrea.com  Thu Jun 17 14:59:03 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Thu, 17 Jun 2010 20:59:03 +0200
Subject: [PATCH] eukrea_mbimx27-baseboard: fix compile when CONFIG_SPI_IMX is
	disabled
In-Reply-To: <1276801147-4103-2-git-send-email-eric@eukrea.com>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>
	<1276801147-4103-2-git-send-email-eric@eukrea.com>
Message-ID: <1276801147-4103-3-git-send-email-eric@eukrea.com>

the i2c_board_info structure landed into the SPI #if/#endif
which is wrong.

Signed-off-by: Eric B?nard <eric at eukrea.com>
Cc: s.hauer at pengutronix.de
Cc: linux-arm-kernel at lists.infradead.org
---
 arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
index e7fd65a..2e57912 100644
--- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
@@ -301,11 +301,6 @@ static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
 	},
 };
 
-static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
-	{
-		I2C_BOARD_INFO("tlv320aic23", 0x1a),
-	},
-};
 
 static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
 
@@ -315,6 +310,11 @@ static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
 };
 #endif
 
+static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("tlv320aic23", 0x1a),
+	},
+};
 static struct platform_device *platform_devices[] __initdata = {
 	&leds_gpio,
 };
-- 
1.6.3.3



From eric at eukrea.com  Thu Jun 17 14:59:04 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Thu, 17 Jun 2010 20:59:04 +0200
Subject: [PATCH v2] mtd/mxc_nand: don't call mtd->{suspend,resume} explicitly
In-Reply-To: <1276801147-4103-3-git-send-email-eric@eukrea.com>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>
	<1276801147-4103-2-git-send-email-eric@eukrea.com>
	<1276801147-4103-3-git-send-email-eric@eukrea.com>
Message-ID: <1276801147-4103-4-git-send-email-eric@eukrea.com>

The mtd layer is responsible to call mtd->{suspend,resume}.  Doing it
again in the driver is wrong and results in a warning:

	nand_resume called for a chip which is not in suspended state

at resume time.  Removing the calls from the resume and suspend
functions makes them empty allowing them to be deleted completely.

Signed-off-by: Eric B?nard <eric at eukrea.com>
Acked-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-mtd at lists.infradead.org
---
v2:
	fix commit log (writen by Uwe Kleine-K?nig)

 drivers/mtd/nand/mxc_nand.c |   44 +------------------------------------------
 1 files changed, 1 insertions(+), 43 deletions(-)

diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 0d76b16..ad19dc6 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -873,53 +873,11 @@ static int __devexit mxcnd_remove(struct platform_device *pdev)
 	return 0;
 }
 
-#ifdef CONFIG_PM
-static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
-{
-	struct mtd_info *mtd = platform_get_drvdata(pdev);
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
-	int ret = 0;
-
-	DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
-
-	ret = mtd->suspend(mtd);
-
-	/*
-	 * nand_suspend locks the device for exclusive access, so
-	 * the clock must already be off.
-	 */
-	BUG_ON(!ret && host->clk_act);
-
-	return ret;
-}
-
-static int mxcnd_resume(struct platform_device *pdev)
-{
-	struct mtd_info *mtd = platform_get_drvdata(pdev);
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
-	int ret = 0;
-
-	DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
-
-	mtd->resume(mtd);
-
-	return ret;
-}
-
-#else
-# define mxcnd_suspend   NULL
-# define mxcnd_resume    NULL
-#endif				/* CONFIG_PM */
-
 static struct platform_driver mxcnd_driver = {
 	.driver = {
 		   .name = DRIVER_NAME,
-		   },
+	},
 	.remove = __devexit_p(mxcnd_remove),
-	.suspend = mxcnd_suspend,
-	.resume = mxcnd_resume,
 };
 
 static int __init mxc_nd_init(void)
-- 
1.6.3.3



From eric at eukrea.com  Thu Jun 17 14:59:05 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Thu, 17 Jun 2010 20:59:05 +0200
Subject: [PATCH] video/imxfb: fix suspend when screen is blanked
In-Reply-To: <1276801147-4103-4-git-send-email-eric@eukrea.com>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>
	<1276801147-4103-2-git-send-email-eric@eukrea.com>
	<1276801147-4103-3-git-send-email-eric@eukrea.com>
	<1276801147-4103-4-git-send-email-eric@eukrea.com>
Message-ID: <1276801147-4103-5-git-send-email-eric@eukrea.com>

if the screen is blanked when suspending, the clock is already disabled,
leading to the following log :
WARNING: at arch/arm/plat-mxc/clock.c:59 __clk_disable+0x68/0x74()
Modules linked in:
[<c002d200>] (unwind_backtrace+0x0/0xf8) from [<c0046008>] (warn_slowpath_common+0x48/0x78)
[<c0046008>] (warn_slowpath_common+0x48/0x78) from [<c0031e28>] (__clk_disable+0x68/0x74)
[<c0031e28>] (__clk_disable+0x68/0x74) from [<c0031ddc>] (__clk_disable+0x1c/0x74)
[<c0031ddc>] (__clk_disable+0x1c/0x74) from [<c0031e58>] (clk_disable+0x24/0x34)
[<c0031e58>] (clk_disable+0x24/0x34) from [<c019808c>] (imxfb_disable_controller+0x38/0x48)
[<c019808c>] (imxfb_disable_controller+0x38/0x48) from [<c01980b0>] (imxfb_suspend+0x14/0x1c)

Signed-off-by: Eric B?nard <eric at eukrea.com>
Cc: kernel at pengutronix.de
Cc: u.kleine-koenig at pengutronix.de
Cc: linux-fbdev at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 drivers/video/imxfb.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index b4b6dec..6cbfbff 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -597,8 +597,8 @@ static int imxfb_suspend(struct platform_device *dev, pm_message_t state)
 	struct imxfb_info *fbi = info->par;
 
 	pr_debug("%s\n", __func__);
-
-	imxfb_disable_controller(fbi);
+	if (readl(fbi->regs + LCDC_RMCR))
+		imxfb_disable_controller(fbi);
 	return 0;
 }
 
-- 
1.6.3.3



From eric at eukrea.com  Thu Jun 17 14:59:06 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Thu, 17 Jun 2010 20:59:06 +0200
Subject: [PATCH] mach-mx3/mach-mx31_3ds: update keypad registration
In-Reply-To: <1276801147-4103-5-git-send-email-eric@eukrea.com>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>
	<1276801147-4103-2-git-send-email-eric@eukrea.com>
	<1276801147-4103-3-git-send-email-eric@eukrea.com>
	<1276801147-4103-4-git-send-email-eric@eukrea.com>
	<1276801147-4103-5-git-send-email-eric@eukrea.com>
Message-ID: <1276801147-4103-6-git-send-email-eric@eukrea.com>

depends on "input/imx_keypad: add PM support"
Note : this patch is not tested

Signed-off-by: Eric B?nard <eric at eukrea.com>
Cc: s.hauer at pengutronix.de
Cc: linux-arm-kernel at lists.infradead.org
Cc: maramaopercheseimorto at gmail.com
---
 arch/arm/mach-mx3/mach-mx31_3ds.c |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 58e5729..04c8700 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -114,6 +114,11 @@ static struct matrix_keymap_data mx31_3ds_keymap_data = {
 	.keymap_size	= ARRAY_SIZE(mx31_3ds_keymap),
 };
 
+static struct matrix_keypad_platform_data mx31_3ds_keypad_data = {
+	.keymap_data	= &mx31_3ds_keymap_data,
+	.wakeup		= 1,
+};
+
 /* Regulators */
 static struct regulator_init_data pwgtx_init = {
 	.constraints = {
@@ -397,7 +402,7 @@ static void __init mxc_board_init(void)
 	spi_register_board_info(mx31_3ds_spi_devs,
 						ARRAY_SIZE(mx31_3ds_spi_devs));
 
-	mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data);
+	mxc_register_device(&imx_kpp_device, &mx31_3ds_keypad_data);
 
 	mx31_3ds_usbotg_init();
 	mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
-- 
1.6.3.3



From eric at eukrea.com  Thu Jun 17 14:59:07 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Thu, 17 Jun 2010 20:59:07 +0200
Subject: [PATCH] mxcmmc: convert to pm_ops and enable/disable clock
In-Reply-To: <1276801147-4103-6-git-send-email-eric@eukrea.com>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>
	<1276801147-4103-2-git-send-email-eric@eukrea.com>
	<1276801147-4103-3-git-send-email-eric@eukrea.com>
	<1276801147-4103-4-git-send-email-eric@eukrea.com>
	<1276801147-4103-5-git-send-email-eric@eukrea.com>
	<1276801147-4103-6-git-send-email-eric@eukrea.com>
Message-ID: <1276801147-4103-7-git-send-email-eric@eukrea.com>

Signed-off-by: Eric B?nard <eric at eukrea.com>
Cc: s.hauer at pengutronix.de
Cc: linux-mmc at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
---
 drivers/mmc/host/mxcmmc.c |   32 ++++++++++++++++++--------------
 1 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/drivers/mmc/host/mxcmmc.c b/drivers/mmc/host/mxcmmc.c
index fdf33e8..350f78e 100644
--- a/drivers/mmc/host/mxcmmc.c
+++ b/drivers/mmc/host/mxcmmc.c
@@ -936,43 +936,47 @@ static int mxcmci_remove(struct platform_device *pdev)
 }
 
 #ifdef CONFIG_PM
-static int mxcmci_suspend(struct platform_device *dev, pm_message_t state)
+static int mxcmci_suspend(struct device *dev)
 {
-	struct mmc_host *mmc = platform_get_drvdata(dev);
+	struct mmc_host *mmc = dev_get_drvdata(dev);
+	struct mxcmci_host *host = mmc_priv(mmc);
 	int ret = 0;
 
 	if (mmc)
 		ret = mmc_suspend_host(mmc);
+	clk_disable(host->clk);
 
 	return ret;
 }
 
-static int mxcmci_resume(struct platform_device *dev)
+static int mxcmci_resume(struct device *dev)
 {
-	struct mmc_host *mmc = platform_get_drvdata(dev);
-	struct mxcmci_host *host;
+	struct mmc_host *mmc = dev_get_drvdata(dev);
+	struct mxcmci_host *host = mmc_priv(mmc);
 	int ret = 0;
 
-	if (mmc) {
-		host = mmc_priv(mmc);
+	clk_enable(host->clk);
+	if (mmc)
 		ret = mmc_resume_host(mmc);
-	}
 
 	return ret;
 }
-#else
-#define mxcmci_suspend  NULL
-#define mxcmci_resume   NULL
-#endif /* CONFIG_PM */
+
+static const struct dev_pm_ops mxcmci_pm_ops = {
+	.suspend	= mxcmci_suspend,
+	.resume		= mxcmci_resume,
+};
+#endif
 
 static struct platform_driver mxcmci_driver = {
 	.probe		= mxcmci_probe,
 	.remove		= mxcmci_remove,
-	.suspend	= mxcmci_suspend,
-	.resume		= mxcmci_resume,
 	.driver		= {
 		.name		= DRIVER_NAME,
 		.owner		= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &mxcmci_pm_ops,
+#endif
 	}
 };
 
-- 
1.6.3.3



From augulis.darius at gmail.com  Thu Jun 17 15:05:26 2010
From: augulis.darius at gmail.com (Darius Augulis)
Date: Thu, 17 Jun 2010 22:05:26 +0300
Subject: [PATCH 11/15] ARM: S3C2416: Add support for second HSMMC channel
In-Reply-To: <1273631766-15693-11-git-send-email-ben-linux@fluff.org>
References: <1273631766-15693-1-git-send-email-ben-linux@fluff.org>
	<1273631766-15693-11-git-send-email-ben-linux@fluff.org>
Message-ID: <4C1A71F6.5030203@gmail.com>

On 05/12/2010 05:36 AM, Ben Dooks wrote:
> Add support for the second HSMMC channel on the S3C2416.

There is issue with mach-s3c2416 and sdhci-s3c driver.
Driver probe crashes with following backtrace:

sdhci: Secure Digital Host Controller Interface driver
sdhci: Copyright(c) Pierre Ossman
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0004000
[00000000] *pgd=00000000
Internal error: Oops: 5 [#1]
last sysfs file:
CPU: 0    Not tainted  (2.6.35-rc3-00001-g7dfb002 #31)
PC is at sdhci_s3c_probe+0x188/0x42c
LR is at clk_enable+0x50/0x60

The reason is not completely initialised s3c_sdhci_platdata structure. 
When getting clocks in sdhci_s3c_probe():

for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
                 struct clk *clk;
                 char *name = pdata->clocks[ptr];

Pointer clocks is not initialised at all, because mach-s3c2416 doesn't 
have such helpers like mach-s3c64xx does:

s3c6400_default_sdhci0()
s3c6400_default_sdhci1()
s3c6400_default_sdhci2()

Also other necessary s3c_sdhci_platdata members cfg_gpio and cfg_card 
are missing on s3c2416.

Is there any patch adding this missing info to mach-s3c2416?

>
> Signed-off-by: Ben Dooks<ben-linux at fluff.org>
> ---
>   arch/arm/mach-s3c2410/include/mach/irqs.h |    3 +++
>   arch/arm/mach-s3c2410/include/mach/map.h  |    5 +++--
>   arch/arm/mach-s3c2416/Kconfig             |    1 +
>   arch/arm/mach-s3c2416/mach-smdk2416.c     |    1 +
>   4 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
> index c1b8ec0..877c15e 100644
> --- a/arch/arm/mach-s3c2410/include/mach/irqs.h
> +++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
> @@ -150,7 +150,10 @@
>   #define IRQ_S3C2443_HSMMC	S3C2410_IRQ(20)		/* IRQ_SDI */
>   #define IRQ_S3C2443_NAND	S3C2410_IRQ(24)		/* reserved */
>
> +#define IRQ_S3C2416_HSMMC0	S3C2410_IRQ(21)		/* S3C2416/S3C2450 */
> +
>   #define IRQ_HSMMC0		IRQ_S3C2443_HSMMC
> +#define IRQ_HSMMC1		IRQ_S3C2416_HSMMC0
>
>   #define IRQ_S3C2443_LCD1	S3C2410_IRQSUB(14)
>   #define IRQ_S3C2443_LCD2	S3C2410_IRQSUB(15)
> diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
> index b049e61..f07d680 100644
> --- a/arch/arm/mach-s3c2410/include/mach/map.h
> +++ b/arch/arm/mach-s3c2410/include/mach/map.h
> @@ -63,9 +63,9 @@
>   #define S3C2440_PA_AC97	   (0x5B000000)
>   #define S3C2440_SZ_AC97	   SZ_1M
>
> -/* S3C2443 High-speed SD/MMC */
> +/* S3C2443/S3C2416 High-speed SD/MMC */
>   #define S3C2443_PA_HSMMC   (0x4A800000)
> -#define S3C2443_SZ_HSMMC   (256)
> +#define S3C2416_PA_HSMMC0  (0x4AC00000)
>
>   /* S3C2412 memory and IO controls */
>   #define S3C2412_PA_SSMC	(0x4F000000)
> @@ -110,6 +110,7 @@
>   #define S3C_PA_UART	    S3C24XX_PA_UART
>   #define S3C_PA_USBHOST	S3C2410_PA_USBHOST
>   #define S3C_PA_HSMMC0	    S3C2443_PA_HSMMC
> +#define S3C_PA_HSMMC1	    S3C2416_PA_HSMMC0
>   #define S3C_PA_NAND	    S3C24XX_PA_NAND
>
>   #endif /* __ASM_ARCH_MAP_H */
> diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
> index 677f963..a1308d4 100644
> --- a/arch/arm/mach-s3c2416/Kconfig
> +++ b/arch/arm/mach-s3c2416/Kconfig
> @@ -27,6 +27,7 @@ config MACH_SMDK2416
>   	bool "SMDK2416"
>   	select CPU_S3C2416
>   	select S3C_DEV_HSMMC
> +	select S3C_DEV_HSMMC1
>   	help
>   	  Say Y here if you are using an SMDK2416
>
> diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
> index 8c9aed6..a51973c 100644
> --- a/arch/arm/mach-s3c2416/mach-smdk2416.c
> +++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
> @@ -112,6 +112,7 @@ static struct platform_device *smdk2416_devices[] __initdata = {
>   	&s3c_device_wdt,
>   	&s3c_device_i2c0,
>   	&s3c_device_hsmmc0,
> +	&s3c_device_hsmmc1,
>   };
>
>   static void __init smdk2416_map_io(void)



From jekhor at gmail.com  Thu Jun 17 15:19:01 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Thu, 17 Jun 2010 22:19:01 +0300
Subject: [PATCH 11/15] ARM: S3C2416: Add support for second HSMMC channel
In-Reply-To: <4C1A71F6.5030203@gmail.com>
References: <1273631766-15693-1-git-send-email-ben-linux@fluff.org>
	<1273631766-15693-11-git-send-email-ben-linux@fluff.org>
	<4C1A71F6.5030203@gmail.com>
Message-ID: <20100617191901.GA5864@jeknote.loshitsa1.net>

On Thu, Jun 17, 2010 at 10:05:26PM +0300, Darius Augulis wrote:
> On 05/12/2010 05:36 AM, Ben Dooks wrote:
> >Add support for the second HSMMC channel on the S3C2416.
> 
> There is issue with mach-s3c2416 and sdhci-s3c driver.
> Driver probe crashes with following backtrace:
> 
> sdhci: Secure Digital Host Controller Interface driver
> sdhci: Copyright(c) Pierre Ossman
> Unable to handle kernel NULL pointer dereference at virtual address 00000000
> pgd = c0004000
> [00000000] *pgd=00000000
> Internal error: Oops: 5 [#1]
> last sysfs file:
> CPU: 0    Not tainted  (2.6.35-rc3-00001-g7dfb002 #31)
> PC is at sdhci_s3c_probe+0x188/0x42c
> LR is at clk_enable+0x50/0x60
> 
> The reason is not completely initialised s3c_sdhci_platdata
> structure. When getting clocks in sdhci_s3c_probe():
> 
> for (clks = 0, ptr = 0; ptr < MAX_BUS_CLK; ptr++) {
>                 struct clk *clk;
>                 char *name = pdata->clocks[ptr];
> 
> Pointer clocks is not initialised at all, because mach-s3c2416
> doesn't have such helpers like mach-s3c64xx does:
> 
> s3c6400_default_sdhci0()
> s3c6400_default_sdhci1()
> s3c6400_default_sdhci2()
> 
> Also other necessary s3c_sdhci_platdata members cfg_gpio and
> cfg_card are missing on s3c2416.
> 
> Is there any patch adding this missing info to mach-s3c2416?

I am already wrote such patch today and will post it after testing
tomorrow, I hope.

-- 
Yauhen Kharuzhy		jekhor _at_ gmail.com
			JID: jek at jabber.ru

A: No
Q: Should I quote below my post?


From nico at fluxnic.net  Thu Jun 17 15:22:05 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 17 Jun 2010 15:22:05 -0400 (EDT)
Subject: [PATCH 0/5] Makefile.boot cleanup
In-Reply-To: <20100603075704.GB336@pengutronix.de>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<20100603075704.GB336@pengutronix.de>
Message-ID: <alpine.LFD.2.00.1006171203030.13427@xanadu.home>

On Thu, 3 Jun 2010, Uwe Kleine-K?nig wrote:

> Hello Eric,
> 
> On Thu, Jun 03, 2010 at 03:36:48PM +0800, Eric Miao wrote:
> > Several facts:
> > 
> > 1. ZRELADDR in most cases can be auto detected by maksing PC with
> >    0xf000_0000 if the zImage is placed within the first 256MiB from
> >    the memory start, which is a sane assumption except for:
> > 
> >    - when ARCH_MX1 or ARCH_SHARK is defined
> >    - when ARCH_U300 is defined (U300 really is strange when defining
> >      PHYS_OFFSET and ZRELADDR)
> >    - or when ZBOOT_ROM is defined
> If you guess ZRELADDR based on sp instead of pc it even should work if
> ZBOOT_ROM is defined?!

What is the relation between sp and ZRELADDR?

While we're pushing forward the notion of a relation between phys offset 
and the location where zImage is loaded in memory, I think that making 
the association with sp is a bit too obscur.  Knowing where you upload 
your kernel is clear, knowing where the stack is allocated in relation 
to that is not that clear.  It is in the .bss section of course, but 
when ZBOOT_ROM is not defined then the .bss happens to be right after 
the zImage binary, while it must be explicitly specified otherwise.

On Sun, 6 Jun 2010, Uwe Kleine-K?nig wrote:

> On Thu, Jun 10, 2010 at 02:44:53PM -0400, Nicolas Pitre wrote:
> > If you're using ZBOOT_ROM that means you want to execute zImage directly
> > from ROM.  This is therefore a highly customized configuration.  In that
> > context, having a variable phys-offset doesn't make much sense to start
> > with.
> Right, but then the kernel needs to know this fixed value for
> phys-offset.  In the patches presented by Eric the person configuring
> the kernel needs to know that value.  When guessing based on sp she
> doesn't need to read addional docs when enabling ZBOOT_ROM.

That's presuming phys offset would still be runtime determined.  Again, 
if you care about ZBOOT_ROM, you probably want a fixed phys offset at 
compile time too.  So that value has to be determined at kernel config 
time, not at run time from pc or sp.  And when dealing with such 
customized expert config options, she better know what she's doing and 
be familiar with the memory layout so not to have to read the datasheet 
only for the physical RAM offset while she already must know what flash 
offset to use.

If anything, you _could_ try doing something similar to:

config PHYS_OFFSET
	[prompt]
	default (CONFIG_ZBOOT_ROM_BSS & 0xf0000000) if ZBOOT_ROM

but I doubt Kconfig might accept such a syntax.


Nicolas

From l.fu at pengutronix.de  Thu Jun 17 15:22:57 2010
From: l.fu at pengutronix.de (Luotao Fu)
Date: Thu, 17 Jun 2010 21:22:57 +0200
Subject: [PATCH] video/imxfb: fix suspend when screen is blanked
In-Reply-To: <1276801147-4103-5-git-send-email-eric@eukrea.com>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>
	<1276801147-4103-2-git-send-email-eric@eukrea.com>
	<1276801147-4103-3-git-send-email-eric@eukrea.com>
	<1276801147-4103-4-git-send-email-eric@eukrea.com>
	<1276801147-4103-5-git-send-email-eric@eukrea.com>
Message-ID: <20100617192257.GA18802@pengutronix.de>

Hi,

On Thu, Jun 17, 2010 at 08:59:05PM +0200, Eric B?nard wrote:
> if the screen is blanked when suspending, the clock is already disabled,
> leading to the following log :
> WARNING: at arch/arm/plat-mxc/clock.c:59 __clk_disable+0x68/0x74()
> Modules linked in:
> [<c002d200>] (unwind_backtrace+0x0/0xf8) from [<c0046008>] (warn_slowpath_common+0x48/0x78)
> [<c0046008>] (warn_slowpath_common+0x48/0x78) from [<c0031e28>] (__clk_disable+0x68/0x74)
> [<c0031e28>] (__clk_disable+0x68/0x74) from [<c0031ddc>] (__clk_disable+0x1c/0x74)
> [<c0031ddc>] (__clk_disable+0x1c/0x74) from [<c0031e58>] (clk_disable+0x24/0x34)
> [<c0031e58>] (clk_disable+0x24/0x34) from [<c019808c>] (imxfb_disable_controller+0x38/0x48)
> [<c019808c>] (imxfb_disable_controller+0x38/0x48) from [<c01980b0>] (imxfb_suspend+0x14/0x1c)
> 
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> Cc: kernel at pengutronix.de
> Cc: u.kleine-koenig at pengutronix.de
> Cc: linux-fbdev at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> ---
>  drivers/video/imxfb.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
> index b4b6dec..6cbfbff 100644
> --- a/drivers/video/imxfb.c
> +++ b/drivers/video/imxfb.c
> @@ -597,8 +597,8 @@ static int imxfb_suspend(struct platform_device *dev, pm_message_t state)
>  	struct imxfb_info *fbi = info->par;
>  
>  	pr_debug("%s\n", __func__);
> -
> -	imxfb_disable_controller(fbi);
> +	if (readl(fbi->regs + LCDC_RMCR))
> +		imxfb_disable_controller(fbi);
>  	return 0;
>  }

I've already submitted a patch to fix this issue:
http://lkml.org/lkml/2010/6/3/187

cheers
Luotao Fu
-- 
Pengutronix e.K.                           | Dipl.-Ing. Luotao Fu        |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
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From linux at arm.linux.org.uk  Thu Jun 17 15:33:24 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 17 Jun 2010 20:33:24 +0100
Subject: [PATCH 4/5] [ARM] Auto calculate ZRELADDR and provide option
	for exceptions
In-Reply-To: <20100611063733.GB10894@pengutronix.de>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com>
	<1275550613-9553-5-git-send-email-eric.miao@canonical.com>
	<AANLkTiltifSEFdpXB0avw4ZyDzP_IrDpipafBAJbN17U@mail.gmail.com>
	<20100611063733.GB10894@pengutronix.de>
Message-ID: <20100617193324.GA8805@n2100.arm.linux.org.uk>

On Fri, Jun 11, 2010 at 08:37:33AM +0200, Uwe Kleine-K?nig wrote:
> Hello Linus,
> 
> On Fri, Jun 11, 2010 at 12:17:44AM +0200, Linus Walleij wrote:
> > I assume it should be submitted simultaneously with a patch nuking off
> > all Makefile.boot files and that infrastructure then?
> Only when bootp is deleted or fixed not to use these variables.

You can't really "fix" it not to use these variables.  The placement
of things like the ramdisk image is something that can only be
specified with a certain amount of information, such as where the
kernel will be located, how large the decompressed kernel will be,
where the RAM is located, whether there's any platform specific
restrictions on what RAM can be used.

ARM is its own enemy here - not having started out with the memory
architected to be in a certain location like it is on x86 makes all
this very much more complicated, and I doubt that any wrapper around
the kernel which performs in a way like the bootp wrapper could be
made to work reliably without being told explicitly where to place
stuff.

And I'm not in favour of it being deleted; there are boot loaders
out there which can only fetch and boot one image.  Such boot loaders
make it difficult to wrap a ramdisk image with the kernel.  The bootp
wrapper solves that.  It's also not something you want to use ZBOOT=y
with.


From daniel at caiaq.de  Thu Jun 17 15:59:18 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Thu, 17 Jun 2010 21:59:18 +0200
Subject: mxcmmc driver hangs on sync
In-Reply-To: <45DEC573-1158-477E-A971-03CB4633F442@zepcam.com>
References: <20100615112936.5d03ce92@morgan>
	<20100615063142.GU17833@buzzloop.caiaq.de>
	<20100615152051.26e4589c@morgan>
	<20100615072237.GW17833@buzzloop.caiaq.de>
	<20100617163340.69409a3f@morgan>
	<45DEC573-1158-477E-A971-03CB4633F442@zepcam.com>
Message-ID: <20100617195918.GN17833@buzzloop.caiaq.de>

On Thu, Jun 17, 2010 at 08:51:37PM +0200, Erik Oomen wrote:
> > On Tue, 15 Jun 2010 09:22:37 +0200
> > Daniel Mack <daniel at caiaq.de> wrote:
> >> On Tue, Jun 15, 2010 at 03:20:51PM +0800, Morgan Howe wrote:
> >>> On Tue, 15 Jun 2010 08:31:43 +0200
> >>> Daniel Mack <daniel at caiaq.de> wrote:
> >>>> On Tue, Jun 15, 2010 at 11:29:36AM +0800, Morgan Howe wrote:
> >>>>> With the older kernel this would hang on sync after a few
> >>>>> thousand loops, and much sooner if you ran 2 or 3 of these
> >>>>> processes at a time. I tried last night with the newer kernel
> >>>>> and kicking off 3 processes and after ~100-150 loops per
> >>>>> process I get this:
> >>>> 
> >>>> Which 'newer kernel' did you try?
> >>> 
> >>> Hey Daniel,
> >>> 
> >>> Sorry, I said current mainline, but actually it's 2.6.35-rc1.
> >> 
> >> Could you try two things:
> >> 
> >> a) build a kernel without MX2 DMA support
> >> b) try 2.6.34, as there were some updates to the mxcmmc driver after
> >>   2.6.34 which could be related
> 
> We've had the same problems for various kernels and mxcmmc modifications. The following fixed it.  We applied it to the 2.6.28 kernel and have been writing and reading *many* Gigabytes without a problem. 

Interesting. Did you try to push this back to mainline?

Daniel

> 
> diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
> index e16014b..f295d68 100644
> --- a/arch/arm/plat-mxc/dma-mx1-mx2.c
> +++ b/arch/arm/plat-mxc/dma-mx1-mx2.c
> @@ -653,7 +653,9 @@ static void dma_irq_handle_channel(int chno)
>  static irqreturn_t dma_irq_handler(int irq, void *dev_id)
>  {
>         int i, disr;
> +       unsigned long flags;
>  
> +       local_irq_save(flags); 
>  #ifdef CONFIG_ARCH_MX2
>         if (cpu_is_mx21() || cpu_is_mx27())
>                 dma_err_handler(irq, dev_id);
> @@ -669,7 +671,7 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
>                 if (disr & (1 << i))
>                         dma_irq_handle_channel(i);
>         }
> -
> +       local_irq_restore(flags);
>         return IRQ_HANDLED;
>  }
>  
> Regards,
>   Erik
> 
> 


From erik.oomen at zepcam.com  Thu Jun 17 16:43:03 2010
From: erik.oomen at zepcam.com (Erik Oomen)
Date: Thu, 17 Jun 2010 22:43:03 +0200
Subject: mxcmmc driver hangs on sync
In-Reply-To: <20100617195918.GN17833@buzzloop.caiaq.de>
References: <20100615112936.5d03ce92@morgan>
	<20100615063142.GU17833@buzzloop.caiaq.de>
	<20100615152051.26e4589c@morgan>
	<20100615072237.GW17833@buzzloop.caiaq.de>
	<20100617163340.69409a3f@morgan>
	<45DEC573-1158-477E-A971-03CB4633F442@zepcam.com>
	<20100617195918.GN17833@buzzloop.caiaq.de>
Message-ID: <316135C6-8571-4B02-9268-52419AEAC56D@zepcam.com>


>> We've had the same problems for various kernels and mxcmmc modifications. The following fixed it.  We applied it to the 2.6.28 kernel and have been writing and reading *many* Gigabytes without a problem. 
> 
> Interesting. Did you try to push this back to mainline?
> 
> Daniel

No, at that time we where not sure this patch was a fix. Let's see if this solves Morgan's problems.

Erik.

From ryan at bluewatersys.com  Thu Jun 17 17:47:59 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Fri, 18 Jun 2010 09:47:59 +1200
Subject: gpiolib and sleeping gpios
Message-ID: <4C1A980F.8080908@bluewatersys.com>

Hi,

Currently implementors of gpiolib must provide implementations for
gpio_get_value, gpio_set_value and gpio_cansleep. Most of the
implementations just #define these to the double underscore prefixed
versions in drivers/gpio/gpiolib.c. A few implementations have a simple
wrapper function which provides a fast path for the SoC gpios, and calls
gpiolib for the any additional gpios, such as those added by an io expander.

Although gpio_chips know whether or not they may sleep, gpios which can
sleep need to call gpio_[set/get]_value_cansleep. The only difference
between __gpio_(set/get)_value and gpio_(set/get)_value_cansleep is that
the cansleep versions calls might_sleep_if. Most drivers call
gpio_(get/set)_value, rather than the cansleep variants. I haven't done
a full audit of all of the drivers (which is a reasonably involved
task), but I would hazard a guess that some of these could be replaced
by the cansleep versions.

Would it not be simpler to combine the calls and have something like this:

void __gpio_get_value(unsigned gpio, int value)
{
	struct gpio_chip *chip;

	chip = gpio_to_chip(gpio);
	might_sleep_if(extra_checks && chip->can_sleep);
	chip->set(chip, gpio - chip->base, value);
}

Then all drivers can just call gpio_(set/get)_value and any attempts to
use sleeping gpios from an non-sleeping context will be caught by the
might_sleep_if check. Is there something I am missing about this?

I can prepare a patch which combines the non-sleeping and sleeping
variants, but I wanted to check that I'm not missing something
fundamental first.

Thanks,
~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From ben-linux at fluff.org  Thu Jun 17 17:59:59 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Thu, 17 Jun 2010 22:59:59 +0100
Subject: [PATCH] SMDK2416: Select MACH_SMDK, S3C_DEV_NAND, S3C_DEV_USB_HOST
In-Reply-To: <1276786221-29640-1-git-send-email-jekhor@gmail.com>
References: <1276786221-29640-1-git-send-email-jekhor@gmail.com>
Message-ID: <20100617215959.GF7248@trinity.fluff.org>

On Thu, Jun 17, 2010 at 05:50:21PM +0300, Yauhen Kharuzhy wrote:
> Enable compilation of platform devices and initialization code used in
> SMDK2416 board file.
> 
> Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
Acked-by: Ben Dooks <ben-linux at fluff.org>
> ---
>  arch/arm/mach-s3c2416/Kconfig |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
> index 657e4fe..eafb0ed 100644
> --- a/arch/arm/mach-s3c2416/Kconfig
> +++ b/arch/arm/mach-s3c2416/Kconfig
> @@ -30,9 +30,12 @@ menu "S3C2416 Machines"
>  config MACH_SMDK2416
>  	bool "SMDK2416"
>  	select CPU_S3C2416
> +	select MACH_SMDK
>  	select S3C_DEV_FB
>  	select S3C_DEV_HSMMC
>  	select S3C_DEV_HSMMC1
> +	select S3C_DEV_NAND
> +	select S3C_DEV_USB_HOST
>  	help
>  	  Say Y here if you are using an SMDK2416
>  
> -- 
> 1.6.6.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From ryan at bluewatersys.com  Thu Jun 17 18:03:27 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Fri, 18 Jun 2010 10:03:27 +1200
Subject: [PATCH 2/3] at91_udc: Add vbus polarity and polling mode
In-Reply-To: <1276723224-23252-3-git-send-email-ryan@bluewatersys.com>
References: <1276723224-23252-1-git-send-email-ryan@bluewatersys.com>
	<1276723224-23252-3-git-send-email-ryan@bluewatersys.com>
Message-ID: <4C1A9BAF.6050907@bluewatersys.com>

I realised this patch was not quite correct. If vbus is on an io
expander then the gpio can potentially sleep, so use the gpiolib
cansleep variants when in polling mode. Also, do not try and
enable/disable wakeups on vbus if it is polled.

---
at91_udc: Add vbus polarity and polling mode

Allow the vbus signal to optionally use polling. This is required if the
vbus signal is connected to an non-interrupting io expander for example.
If vbus is in polling mode, then it is assumed that the vbus gpio may
sleep. Also add an option to have vbus be an active low signal. Both
options are set in the platform data for the device.

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---

diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index df2ed84..58528aa 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -44,6 +44,8 @@
  /* USB Device */
 struct at91_udc_data {
 	u8	vbus_pin;		/* high == host powering us */
+	u8	vbus_active_low;	/* vbus polarity */
+	u8	vbus_polled;		/* Use polling, not interrupt */
 	u8	pullup_pin;		/* active == D+ pulled up */
 	u8	pullup_active_low;	/* true == pullup_pin is active low */
 };
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index eaa79c8..469a64c 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -76,6 +76,7 @@
 static const char driver_name [] = "at91_udc";
 static const char ep0name[] = "ep0";
 
+#define VBUS_POLL_TIMEOUT	msecs_to_jiffies(1000)
 
 #define at91_udp_read(dev, reg) \
 	__raw_readl((dev)->udp_baseaddr + (reg))
@@ -1556,20 +1557,49 @@ static struct at91_udc controller = {
 	/* ep6 and ep7 are also reserved (custom silicon might use them) */
 };
 
+static void at91_vbus_update(struct at91_udc *udc, unsigned value)
+{
+	if (udc->board.vbus_active_low)
+		value ^= 1;
+	if (value != udc->vbus)
+		at91_vbus_session(&udc->gadget, value);
+}
+
 static irqreturn_t at91_vbus_irq(int irq, void *_udc)
 {
 	struct at91_udc	*udc = _udc;
-	unsigned	value;
 
 	/* vbus needs at least brief debouncing */
 	udelay(10);
-	value = gpio_get_value(udc->board.vbus_pin);
-	if (value != udc->vbus)
-		at91_vbus_session(&udc->gadget, value);
+	at91_vbus_update(udc, gpio_get_value(udc->board.vbus_pin));
 
 	return IRQ_HANDLED;
 }
 
+static void at91_vbus_timer_work(struct work_struct *work)
+{
+	struct at91_udc *udc = container_of(work, struct at91_udc, 
+					    vbus_timer_work);
+
+	at91_vbus_update(udc, gpio_get_value_cansleep(udc->board.vbus_pin));
+
+	if (!timer_pending(&udc->vbus_timer))
+		mod_timer(&udc->vbus_timer, jiffies + VBUS_POLL_TIMEOUT);
+}
+
+static void at91_vbus_timer(unsigned long data)
+{
+	struct at91_udc *udc = (struct at91_udc *)data;
+
+	/*
+	 * If we are polling vbus it is likely that the gpio is on an
+	 * bus such as i2c or spi which may sleep, so schedule some work
+	 * to read the vbus gpio
+	 */
+	if (!work_pending(&udc->vbus_timer_work))
+		schedule_work(&udc->vbus_timer_work);
+}
+
 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
 {
 	struct at91_udc	*udc = &controller;
@@ -1763,13 +1793,22 @@ static int __init at91udc_probe(struct platform_device *pdev)
 		 * Get the initial state of VBUS - we cannot expect
 		 * a pending interrupt.
 		 */
-		udc->vbus = gpio_get_value(udc->board.vbus_pin);
-		if (request_irq(udc->board.vbus_pin, at91_vbus_irq,
-				IRQF_DISABLED, driver_name, udc)) {
-			DBG("request vbus irq %d failed\n",
-					udc->board.vbus_pin);
-			retval = -EBUSY;
-			goto fail3;
+		if (udc->board.vbus_polled) {
+			udc->vbus = gpio_get_value_cansleep(udc->board.vbus_pin);
+			INIT_WORK(&udc->vbus_timer_work, at91_vbus_timer_work);
+			setup_timer(&udc->vbus_timer, at91_vbus_timer,
+				    (unsigned long)udc);		
+			mod_timer(&udc->vbus_timer,
+				  jiffies + VBUS_POLL_TIMEOUT);
+		} else {
+			udc->vbus = gpio_get_value(udc->board.vbus_pin);
+			if (request_irq(udc->board.vbus_pin, at91_vbus_irq,
+					IRQF_DISABLED, driver_name, udc)) {
+				DBG("request vbus irq %d failed\n",
+				    udc->board.vbus_pin);
+				retval = -EBUSY;
+				goto fail3;
+			}
 		}
 	} else {
 		DBG("no VBUS detection, assuming always-on\n");
@@ -1855,7 +1894,7 @@ static int at91udc_suspend(struct platform_device *pdev, pm_message_t mesg)
 		enable_irq_wake(udc->udp_irq);
 
 	udc->active_suspend = wake;
-	if (udc->board.vbus_pin > 0 && wake)
+	if (udc->board.vbus_pin > 0 && !udc->board.vbus_polled && wake)
 		enable_irq_wake(udc->board.vbus_pin);
 	return 0;
 }
@@ -1864,7 +1903,8 @@ static int at91udc_resume(struct platform_device *pdev)
 {
 	struct at91_udc *udc = platform_get_drvdata(pdev);
 
-	if (udc->board.vbus_pin > 0 && udc->active_suspend)
+	if (udc->board.vbus_pin > 0 && !udc->board.vbus_polled && 
+	    udc->active_suspend)
 		disable_irq_wake(udc->board.vbus_pin);
 
 	/* maybe reconnect to host; if so, clocks on */
diff --git a/drivers/usb/gadget/at91_udc.h b/drivers/usb/gadget/at91_udc.h
index c65d622..a1f4f54 100644
--- a/drivers/usb/gadget/at91_udc.h
+++ b/drivers/usb/gadget/at91_udc.h
@@ -144,6 +144,8 @@ struct at91_udc {
 	struct proc_dir_entry		*pde;
 	void __iomem			*udp_baseaddr;
 	int				udp_irq;
+	struct timer_list		vbus_timer;
+	struct work_struct		vbus_timer_work;
 };
 
 static inline struct at91_udc *to_udc(struct usb_gadget *g)



From konkers at android.com  Thu Jun 17 18:38:19 2010
From: konkers at android.com (Erik Gilling)
Date: Thu, 17 Jun 2010 15:38:19 -0700
Subject: [GIT PULL linux-next] tegra
Message-ID: <AANLkTikXH_UtE95ZGHp5AAm5IRD6dN8cnrNK9A3-MRwY@mail.gmail.com>

Hello Stephen,

Can you please pull the following into linux-next?

git://android.git.kernel.org/kernel/tegra.git for-next

This tree adds support for the Nvidia Tegra ARM SOCs.  It's received
review on linux-arm-kernel.

Thanks,
    Erik Gilling


From linux at arm.linux.org.uk  Thu Jun 17 19:00:08 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 18 Jun 2010 00:00:08 +0100
Subject: [PATCH 08/10] arm: deprecate support for old way to pass
	kernel parameters
In-Reply-To: <AANLkTikNtX5TiPlWOAf_C-HqK7kchZgwi-MQzQqgtush@mail.gmail.com>
References: <20100610102427.GC31057@pengutronix.de>
	<1276165636-20150-8-git-send-email-u.kleine-koenig@pengutronix.de>
	<AANLkTikNtX5TiPlWOAf_C-HqK7kchZgwi-MQzQqgtush@mail.gmail.com>
Message-ID: <20100617230008.GA10780@n2100.arm.linux.org.uk>

On Thu, Jun 17, 2010 at 05:58:42PM +0800, Eric Miao wrote:
> 2010/6/10 Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>:
> > This was deprecated in 2001 and announced to live on for 5 years.
> >
> > For now provide a kernel parameter for those who still need it.
> >
> > Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
> 
> Looks OK to me, Acked.
> 
> BTW, is there any existing usage of this and can we remove this
> completely from now on?

Boot messages from my firewall:

Linux version 2.6.32.8 (rmk at rmk-PC) (gcc version 3.4.3) #11 Sat Mar 27 20:51:49 GMT 2010
CPU: StrongARM-110 [4401a102] revision 2 (ARMv4), cr=0000517d
CPU: VIVT data cache, VIVT instruction cache
Machine: EBSA110
Converting old-style param struct to taglist
ATAG_INITRD is deprecated; please update your bootloader.
Memory policy: ECC disabled, Data cache writeback

Obviously, being a critical machine here, and that I have no way to jtag
it if I brick it, I'm not going to replace the boot loader (which
incidentally can only bootp/tftp one file - the one in the bootp packet.)


From sfr at canb.auug.org.au  Thu Jun 17 19:08:57 2010
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Fri, 18 Jun 2010 09:08:57 +1000
Subject: [GIT PULL linux-next] tegra
In-Reply-To: <AANLkTikXH_UtE95ZGHp5AAm5IRD6dN8cnrNK9A3-MRwY@mail.gmail.com>
References: <AANLkTikXH_UtE95ZGHp5AAm5IRD6dN8cnrNK9A3-MRwY@mail.gmail.com>
Message-ID: <20100618090857.057e0a7a.sfr@canb.auug.org.au>

Hi Eric,

On Thu, 17 Jun 2010 15:38:19 -0700 Erik Gilling <konkers at android.com> wrote:
>
> Can you please pull the following into linux-next?
> 
> git://android.git.kernel.org/kernel/tegra.git for-next
> 
> This tree adds support for the Nvidia Tegra ARM SOCs.  It's received
> review on linux-arm-kernel.

Added from today.  Should the contact be just you or should I add others
as well.

Thanks for adding your subsystem tree as a participant of linux-next.  As
you may know, this is not a judgment of your code.  The purpose of
linux-next is for integration testing and to lower the impact of
conflicts between subsystems in the next merge window. 

You will need to ensure that the patches/commits in your tree/series have
been:
     * submitted under GPL v2 (or later) and include the Contributor's
	Signed-off-by,
     * posted to the relevant mailing list,
     * reviewed by you (or another maintainer of your subsystem tree),
     * successfully unit tested, and 
     * destined for the current or next Linux merge window.

Basically, this should be just what you would send to Linus (or ask him
to fetch).  It is allowed to be rebased if you deem it necessary.

-- 
Cheers,
Stephen Rothwell 
sfr at canb.auug.org.au

Legal Stuff:
By participating in linux-next, your subsystem tree contributions are
public and will be included in the linux-next trees.  You may be sent
e-mail messages indicating errors or other issues when the
patches/commits from your subsystem tree are merged and tested in
linux-next.  These messages may also be cross-posted to the linux-next
mailing list, the linux-kernel mailing list, etc.  The linux-next tree
project and IBM (my employer) make no warranties regarding the linux-next
project, the testing procedures, the results, the e-mails, etc.  If you
don't agree to these ground rules, let me know and I'll remove your tree
from participation in linux-next.
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From konkers at android.com  Thu Jun 17 19:12:23 2010
From: konkers at android.com (Erik Gilling)
Date: Thu, 17 Jun 2010 16:12:23 -0700
Subject: [GIT PULL linux-next] tegra
In-Reply-To: <20100618090857.057e0a7a.sfr@canb.auug.org.au>
References: <AANLkTikXH_UtE95ZGHp5AAm5IRD6dN8cnrNK9A3-MRwY@mail.gmail.com>
	<20100618090857.057e0a7a.sfr@canb.auug.org.au>
Message-ID: <AANLkTin7ZT5YyL7vUjiQ-5s9wjmEWEqfw7tnaHP4k5U_@mail.gmail.com>

Thanks Stephen,
    Add Colin and Olof as contacts as well.

Cheers,
    Erik

On Thu, Jun 17, 2010 at 4:08 PM, Stephen Rothwell <sfr at canb.auug.org.au> wrote:
> Hi Eric,
>
> On Thu, 17 Jun 2010 15:38:19 -0700 Erik Gilling <konkers at android.com> wrote:
>>
>> Can you please pull the following into linux-next?
>>
>> git://android.git.kernel.org/kernel/tegra.git for-next
>>
>> This tree adds support for the Nvidia Tegra ARM SOCs. ?It's received
>> review on linux-arm-kernel.
>
> Added from today. ?Should the contact be just you or should I add others
> as well.
>
> Thanks for adding your subsystem tree as a participant of linux-next. ?As
> you may know, this is not a judgment of your code. ?The purpose of
> linux-next is for integration testing and to lower the impact of
> conflicts between subsystems in the next merge window.
>
> You will need to ensure that the patches/commits in your tree/series have
> been:
> ? ? * submitted under GPL v2 (or later) and include the Contributor's
> ? ? ? ?Signed-off-by,
> ? ? * posted to the relevant mailing list,
> ? ? * reviewed by you (or another maintainer of your subsystem tree),
> ? ? * successfully unit tested, and
> ? ? * destined for the current or next Linux merge window.
>
> Basically, this should be just what you would send to Linus (or ask him
> to fetch). ?It is allowed to be rebased if you deem it necessary.
>
> --
> Cheers,
> Stephen Rothwell
> sfr at canb.auug.org.au
>
> Legal Stuff:
> By participating in linux-next, your subsystem tree contributions are
> public and will be included in the linux-next trees. ?You may be sent
> e-mail messages indicating errors or other issues when the
> patches/commits from your subsystem tree are merged and tested in
> linux-next. ?These messages may also be cross-posted to the linux-next
> mailing list, the linux-kernel mailing list, etc. ?The linux-next tree
> project and IBM (my employer) make no warranties regarding the linux-next
> project, the testing procedures, the results, the e-mails, etc. ?If you
> don't agree to these ground rules, let me know and I'll remove your tree
> from participation in linux-next.
>


From kmpark at infradead.org  Thu Jun 17 19:40:10 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 18 Jun 2010 08:40:10 +0900
Subject: [PATCH] S5PV210 Correct clock register properties
In-Reply-To: <1276763596-6175-1-git-send-email-myungjoo.ham@samsung.com>
References: <1276763596-6175-1-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <AANLkTikhPeiBzFFOEFQHr4bvV_hiGwkck6weuJi5A72G@mail.gmail.com>

Acked-by: Kyungmin Park <kyungmin.park at samsung.com>

To Ben,

My concern is happen. that's reason to use the macro instead of
hard-coded values.

It's need to merge 2.6.35-rc4.

Thank you,
Kyungmin Park

On Thu, Jun 17, 2010 at 5:33 PM, MyungJoo Ham <myungjoo.ham at samsung.com> wrote:
> From: MyungJoo Ham <myungJoo.ham at samsung.com>
>
> Corrected shift values of I2S and UART clocks (CLK_GATE_IP3).
>
> I2S (CLK_GATE_IP3) and UART (CLK_GATE_IP3) had wrong register shift
> values, which in turn, made them turn on and off wrong clocks.
>
> Please note that each clock definition should access different control
> register; otherwise, the system may suffer lockups. For example, if we
> have two clock definitions "a" and "b" which access the same register
> (and the shift value). Then, when we do:
>
> ? ? ? ?module B
> ? ? ? ?1 clk = clk_get("b");
> ? ? ? ?2 clk->clk_enable(clk);
> ? ? ? ?3 do something with clk.
> ? ? ? ?4 clk->clk_disable(clk);
>
> ? ? ? ?module A
> ? ? ? ?1 clk = clk_get("a");
> ? ? ? ?2 clk->clk_enable(clk);
> ? ? ? ?3 do something with clk
> ? ? ? ?4 clk->clk_disable(clk);
>
> ? ? ? ?And if the execution order is
>
> ? ? ? ?B1->B2->A1->A2->A3->A4->B3 ...
>
> ? ? ? ?Then, the system may hang at the point B3.
>
>
> Therefore, there should be no clock definitions with the same contol
> register/shift. If we need to create "aliases", then, creating child
> clocks sharing the clock should be fine.
>
> However, we did not mitigate this doppelganger clock problem for "struct
> clksrc_clk" vs "struct clk"; look at "hsmmc" vs "mmc_bus". In the next
> patch, we plan to let "struct clksrc_clk" access "CLK_SRC_MASK0" and
> "CLK_SRC_MASK1"; i.e., clock source enable/disable should mask the clock
> source itself, not the clock that is supplied by the clock source.
>
> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> ---
> ?arch/arm/mach-s5pv210/clock.c | ? 12 ++++++------
> ?1 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> index 154bca4..ec5ad8c 100644
> --- a/arch/arm/mach-s5pv210/clock.c
> +++ b/arch/arm/mach-s5pv210/clock.c
> @@ -406,13 +406,13 @@ static struct clk init_clocks_disable[] = {
> ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 0,
> ? ? ? ? ? ? ? ?.parent ? ? ? ? = &clk_p,
> ? ? ? ? ? ? ? ?.enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
> - ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<4),
> + ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<5),
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "i2s_v32",
> ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 1,
> ? ? ? ? ? ? ? ?.parent ? ? ? ? = &clk_p,
> ? ? ? ? ? ? ? ?.enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
> - ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<4),
> + ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<6),
> ? ? ? ?}
> ?};
>
> @@ -429,25 +429,25 @@ static struct clk init_clocks[] = {
> ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 0,
> ? ? ? ? ? ? ? ?.parent ? ? ? ? = &clk_pclk_psys.clk,
> ? ? ? ? ? ? ? ?.enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
> - ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<7),
> + ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<17),
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "uart",
> ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 1,
> ? ? ? ? ? ? ? ?.parent ? ? ? ? = &clk_pclk_psys.clk,
> ? ? ? ? ? ? ? ?.enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
> - ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<8),
> + ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<18),
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "uart",
> ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 2,
> ? ? ? ? ? ? ? ?.parent ? ? ? ? = &clk_pclk_psys.clk,
> ? ? ? ? ? ? ? ?.enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
> - ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<9),
> + ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<19),
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "uart",
> ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 3,
> ? ? ? ? ? ? ? ?.parent ? ? ? ? = &clk_pclk_psys.clk,
> ? ? ? ? ? ? ? ?.enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
> - ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<10),
> + ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<20),
> ? ? ? ?},
> ?};
>
> --
> 1.6.3.3
>
>


From sfr at canb.auug.org.au  Thu Jun 17 20:08:30 2010
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Fri, 18 Jun 2010 10:08:30 +1000
Subject: [GIT PULL linux-next] tegra
In-Reply-To: <AANLkTin7ZT5YyL7vUjiQ-5s9wjmEWEqfw7tnaHP4k5U_@mail.gmail.com>
References: <AANLkTikXH_UtE95ZGHp5AAm5IRD6dN8cnrNK9A3-MRwY@mail.gmail.com>
	<20100618090857.057e0a7a.sfr@canb.auug.org.au>
	<AANLkTin7ZT5YyL7vUjiQ-5s9wjmEWEqfw7tnaHP4k5U_@mail.gmail.com>
Message-ID: <20100618100830.d6589e23.sfr@canb.auug.org.au>

Hi Eric,

On Thu, 17 Jun 2010 16:12:23 -0700 Erik Gilling <konkers at android.com> wrote:
>
>     Add Colin and Olof as contacts as well.

Done.

-- 
Cheers,
Stephen Rothwell                    sfr at canb.auug.org.au
http://www.canb.auug.org.au/~sfr/
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From eric.miao at canonical.com  Thu Jun 17 21:31:03 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Fri, 18 Jun 2010 09:31:03 +0800
Subject: [PATCH 0/5] Makefile.boot cleanup
In-Reply-To: <alpine.LFD.2.00.1006171203030.13427@xanadu.home>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com> 
	<20100603075704.GB336@pengutronix.de>
	<alpine.LFD.2.00.1006171203030.13427@xanadu.home>
Message-ID: <AANLkTiloOzJk-TWDaFCLytjOWLEGSv-u_poJnC13tlD_@mail.gmail.com>

2010/6/18 Nicolas Pitre <nico at fluxnic.net>:
> On Thu, 3 Jun 2010, Uwe Kleine-K?nig wrote:
>
>> Hello Eric,
>>
>> On Thu, Jun 03, 2010 at 03:36:48PM +0800, Eric Miao wrote:
>> > Several facts:
>> >
>> > 1. ZRELADDR in most cases can be auto detected by maksing PC with
>> > ? ?0xf000_0000 if the zImage is placed within the first 256MiB from
>> > ? ?the memory start, which is a sane assumption except for:
>> >
>> > ? ?- when ARCH_MX1 or ARCH_SHARK is defined
>> > ? ?- when ARCH_U300 is defined (U300 really is strange when defining
>> > ? ? ?PHYS_OFFSET and ZRELADDR)
>> > ? ?- or when ZBOOT_ROM is defined
>> If you guess ZRELADDR based on sp instead of pc it even should work if
>> ZBOOT_ROM is defined?!
>
> What is the relation between sp and ZRELADDR?
>
> While we're pushing forward the notion of a relation between phys offset
> and the location where zImage is loaded in memory, I think that making
> the association with sp is a bit too obscur. ?Knowing where you upload
> your kernel is clear, knowing where the stack is allocated in relation
> to that is not that clear. ?It is in the .bss section of course, but
> when ZBOOT_ROM is not defined then the .bss happens to be right after
> the zImage binary, while it must be explicitly specified otherwise.
>
> On Sun, 6 Jun 2010, Uwe Kleine-K?nig wrote:
>
>> On Thu, Jun 10, 2010 at 02:44:53PM -0400, Nicolas Pitre wrote:
>> > If you're using ZBOOT_ROM that means you want to execute zImage directly
>> > from ROM. ?This is therefore a highly customized configuration. ?In that
>> > context, having a variable phys-offset doesn't make much sense to start
>> > with.
>> Right, but then the kernel needs to know this fixed value for
>> phys-offset. ?In the patches presented by Eric the person configuring
>> the kernel needs to know that value. ?When guessing based on sp she
>> doesn't need to read addional docs when enabling ZBOOT_ROM.
>
> That's presuming phys offset would still be runtime determined. ?Again,
> if you care about ZBOOT_ROM, you probably want a fixed phys offset at
> compile time too. ?So that value has to be determined at kernel config
> time, not at run time from pc or sp. ?And when dealing with such
> customized expert config options, she better know what she's doing and
> be familiar with the memory layout so not to have to read the datasheet
> only for the physical RAM offset while she already must know what flash
> offset to use.
>
> If anything, you _could_ try doing something similar to:
>
> config PHYS_OFFSET
> ? ? ? ?[prompt]
> ? ? ? ?default (CONFIG_ZBOOT_ROM_BSS & 0xf0000000) if ZBOOT_ROM
>
> but I doubt Kconfig might accept such a syntax.
>

No, Kconfig doesn't. I tried to play this a bit with Kconfig, but failed.


From eric.miao at canonical.com  Thu Jun 17 22:30:54 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Fri, 18 Jun 2010 10:30:54 +0800
Subject: [PATCH 0/5] Makefile.boot cleanup
In-Reply-To: <alpine.LFD.2.00.1006171203030.13427@xanadu.home>
References: <1275550613-9553-1-git-send-email-eric.miao@canonical.com> 
	<20100603075704.GB336@pengutronix.de>
	<alpine.LFD.2.00.1006171203030.13427@xanadu.home>
Message-ID: <AANLkTinhQgeEXHnlYVtbGrPpPGDeW34ZT_c_tyI--hGM@mail.gmail.com>

2010/6/18 Nicolas Pitre <nico at fluxnic.net>:
> On Thu, 3 Jun 2010, Uwe Kleine-K?nig wrote:
>
>> Hello Eric,
>>
>> On Thu, Jun 03, 2010 at 03:36:48PM +0800, Eric Miao wrote:
>> > Several facts:
>> >
>> > 1. ZRELADDR in most cases can be auto detected by maksing PC with
>> > ? ?0xf000_0000 if the zImage is placed within the first 256MiB from
>> > ? ?the memory start, which is a sane assumption except for:
>> >
>> > ? ?- when ARCH_MX1 or ARCH_SHARK is defined
>> > ? ?- when ARCH_U300 is defined (U300 really is strange when defining
>> > ? ? ?PHYS_OFFSET and ZRELADDR)
>> > ? ?- or when ZBOOT_ROM is defined
>> If you guess ZRELADDR based on sp instead of pc it even should work if
>> ZBOOT_ROM is defined?!
>
> What is the relation between sp and ZRELADDR?
>
> While we're pushing forward the notion of a relation between phys offset
> and the location where zImage is loaded in memory, I think that making
> the association with sp is a bit too obscur. ?Knowing where you upload
> your kernel is clear, knowing where the stack is allocated in relation
> to that is not that clear. ?It is in the .bss section of course, but
> when ZBOOT_ROM is not defined then the .bss happens to be right after
> the zImage binary, while it must be explicitly specified otherwise.
>

I agree with Nico. Associating PHYS_OFFSET with pc is more straight-forward,
and I think it will save us some effort just not to support a runtime
phys_offset
with ZBOOT enabled.


From kgene.kim at samsung.com  Thu Jun 17 22:31:40 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 18 Jun 2010 11:31:40 +0900
Subject: [PATCH] S5PV210 Correct clock register properties
In-Reply-To: <1276763596-6175-1-git-send-email-myungjoo.ham@samsung.com>
References: <1276763596-6175-1-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <000f01cb0e8e$64d44950$2e7cdbf0$%kim@samsung.com>

MyungJoo Ham wrote:
> 
> From: MyungJoo Ham <myungJoo.ham at samsung.com>
> 
I think you're author of this patch, so no need above 'From'.
Maybe from wrong e-mail which should be 'myungjoo.ham...'

Please ensure that your setting of '.gitconfig' is right before submitting.

> Corrected shift values of I2S and UART clocks (CLK_GATE_IP3).
> 
> I2S (CLK_GATE_IP3) and UART (CLK_GATE_IP3) had wrong register shift
> values, which in turn, made them turn on and off wrong clocks.

Yes..should be fixed.

> 
> Please note that each clock definition should access different control
> register; otherwise, the system may suffer lockups. For example, if we
> have two clock definitions "a" and "b" which access the same register
> (and the shift value). Then, when we do:
> 
> 	module B
> 	1 clk = clk_get("b");
> 	2 clk->clk_enable(clk);
> 	3 do something with clk.
> 	4 clk->clk_disable(clk);
> 
> 	module A
> 	1 clk = clk_get("a");
> 	2 clk->clk_enable(clk);
> 	3 do something with clk
> 	4 clk->clk_disable(clk);
> 
> 	And if the execution order is
> 
> 	B1->B2->A1->A2->A3->A4->B3 ...
> 
> 	Then, the system may hang at the point B3.
> 
> 
> Therefore, there should be no clock definitions with the same contol
> register/shift. If we need to create "aliases", then, creating child
> clocks sharing the clock should be fine.

Yeah, but actually just should be fixed wrong bit.

> 
> However, we did not mitigate this doppelganger clock problem for "struct
> clksrc_clk" vs "struct clk"; look at "hsmmc" vs "mmc_bus". In the next
> patch, we plan to let "struct clksrc_clk" access "CLK_SRC_MASK0" and
> "CLK_SRC_MASK1"; i.e., clock source enable/disable should mask the clock
> source itself, not the clock that is supplied by the clock source.

No need above message in here.

> 
> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> ---
>  arch/arm/mach-s5pv210/clock.c |   12 ++++++------
>  1 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> index 154bca4..ec5ad8c 100644
> --- a/arch/arm/mach-s5pv210/clock.c
> +++ b/arch/arm/mach-s5pv210/clock.c
> @@ -406,13 +406,13 @@ static struct clk init_clocks_disable[] = {
>  		.id		= 0,
>  		.parent		= &clk_p,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<4),
> +		.ctrlbit	= (1<<5),
>  	}, {
>  		.name		= "i2s_v32",
>  		.id		= 1,
>  		.parent		= &clk_p,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<4),
> +		.ctrlbit	= (1<<6),

Your point is right..but your updated code was wrong :-(

Should be like below.

@@ -400,19 +400,19 @@ static struct clk init_clocks_disable[] = {
 		.id		= 0,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1 << 4),
 	}, {
 		.name		= "i2s_v32",
 		.id		= 0,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1 << 5),
 	}, {
 		.name		= "i2s_v32",
 		.id		= 1,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1 << 6),

>  	}
>  };
> 
> @@ -429,25 +429,25 @@ static struct clk init_clocks[] = {
>  		.id		= 0,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<7),
> +		.ctrlbit	= (1<<17),
>  	}, {
>  		.name		= "uart",
>  		.id		= 1,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<8),
> +		.ctrlbit	= (1<<18),
>  	}, {
>  		.name		= "uart",
>  		.id		= 2,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<9),
> +		.ctrlbit	= (1<<19),
>  	}, {
>  		.name		= "uart",
>  		.id		= 3,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<10),
> +		.ctrlbit	= (1<<20),

How about adding blank on both of '<<' like (1 << x) for easily reading?

>  	},
>  };
> 
> --

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Thu Jun 17 22:38:04 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 18 Jun 2010 11:38:04 +0900
Subject: [PATCH] S5PV210 Correct clock register properties
In-Reply-To: <1276763596-6175-1-git-send-email-myungjoo.ham@samsung.com>
References: <1276763596-6175-1-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <001001cb0e8f$47e2a8e0$d7a7faa0$%kim@samsung.com>

MyungJoo Ham wrote:
> 
> From: MyungJoo Ham <myungJoo.ham at samsung.com>
> 
> Corrected shift values of I2S and UART clocks (CLK_GATE_IP3).
> 
> I2S (CLK_GATE_IP3) and UART (CLK_GATE_IP3) had wrong register shift
> values, which in turn, made them turn on and off wrong clocks.

(snip)

Sorry..kindly ignore below comments.
My mistake..

---
Your point is right..but your updated code was wrong :-(

Should be like below.

@@ -400,19 +400,19 @@ static struct clk init_clocks_disable[] = {
 		.id		= 0,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1 << 4),
 	}, {
 		.name		= "i2s_v32",
 		.id		= 0,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1 << 5),
 	}, {
 		.name		= "i2s_v32",
 		.id		= 1,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1 << 6),
---

(snip)


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From redhatter at gentoo.org  Thu Jun 17 22:56:10 2010
From: redhatter at gentoo.org (Stuart Longland)
Date: Fri, 18 Jun 2010 12:56:10 +1000
Subject: [PATCH] ASoC: Fix overflow bug in SOC_DOUBLE_R_SX_TLV
In-Reply-To: <20100618023810.GS7759@www.longlandclan.yi.org>
References: <20100618023810.GS7759@www.longlandclan.yi.org>
Message-ID: <1276829770-31557-1-git-send-email-redhatter@gentoo.org>

When SX_TLV widgets are read, if the gain is set to a value below 0dB,
the mixer control is erroniously read as being at maximum volume.

The value read out of the CODEC register is never sign-extended, and
when the minimum value is subtracted (read; added, since the minimum is
negative) the result is a number greater than the maximum allowed value
for the control, and hence it saturates.

Solution: Mask the result so that it "wraps around", emulating
sign-extension.

Signed-off-by: Stuart Longland <redhatter at gentoo.org>
---
 sound/soc/soc-core.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
index a82a797..0470288 100644
--- a/sound/soc/soc-core.c
+++ b/sound/soc/soc-core.c
@@ -2400,8 +2400,8 @@ int snd_soc_get_volsw_2r_sx(struct snd_kcontrol *kcontrol,
 	int val = snd_soc_read(codec, mc->reg) & mask;
 	int valr = snd_soc_read(codec, mc->rreg) & mask;
 
-	ucontrol->value.integer.value[0] = ((val & 0xff)-min);
-	ucontrol->value.integer.value[1] = ((valr & 0xff)-min);
+	ucontrol->value.integer.value[0] = ((val & 0xff)-min) & mask;
+	ucontrol->value.integer.value[1] = ((valr & 0xff)-min) & mask;
 	return 0;
 }
 EXPORT_SYMBOL_GPL(snd_soc_get_volsw_2r_sx);
-- 
1.6.4.4



From jy0922.shim at samsung.com  Thu Jun 17 23:30:42 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 18 Jun 2010 12:30:42 +0900
Subject: [PATCH] S5PV210 Correct clock register properties
In-Reply-To: <000f01cb0e8e$64d44950$2e7cdbf0$%kim@samsung.com>
References: <1276763596-6175-1-git-send-email-myungjoo.ham@samsung.com>
	<000f01cb0e8e$64d44950$2e7cdbf0$%kim@samsung.com>
Message-ID: <4C1AE862.8000407@samsung.com>

On 6/18/2010 11:31 AM, Kukjin Kim wrote:
> MyungJoo Ham wrote:
>> From: MyungJoo Ham <myungJoo.ham at samsung.com>
>>
> I think you're author of this patch, so no need above 'From'.
> Maybe from wrong e-mail which should be 'myungjoo.ham...'
> 
> Please ensure that your setting of '.gitconfig' is right before submitting.
> 
>> Corrected shift values of I2S and UART clocks (CLK_GATE_IP3).
>>
>> I2S (CLK_GATE_IP3) and UART (CLK_GATE_IP3) had wrong register shift
>> values, which in turn, made them turn on and off wrong clocks.
> 
> Yes..should be fixed.
> 
>> Please note that each clock definition should access different control
>> register; otherwise, the system may suffer lockups. For example, if we
>> have two clock definitions "a" and "b" which access the same register
>> (and the shift value). Then, when we do:
>>
>> 	module B
>> 	1 clk = clk_get("b");
>> 	2 clk->clk_enable(clk);
>> 	3 do something with clk.
>> 	4 clk->clk_disable(clk);
>>
>> 	module A
>> 	1 clk = clk_get("a");
>> 	2 clk->clk_enable(clk);
>> 	3 do something with clk
>> 	4 clk->clk_disable(clk);
>>
>> 	And if the execution order is
>>
>> 	B1->B2->A1->A2->A3->A4->B3 ...
>>
>> 	Then, the system may hang at the point B3.
>>
>>
>> Therefore, there should be no clock definitions with the same contol
>> register/shift. If we need to create "aliases", then, creating child
>> clocks sharing the clock should be fine.
> 
> Yeah, but actually just should be fixed wrong bit.
> 
>> However, we did not mitigate this doppelganger clock problem for "struct
>> clksrc_clk" vs "struct clk"; look at "hsmmc" vs "mmc_bus". In the next
>> patch, we plan to let "struct clksrc_clk" access "CLK_SRC_MASK0" and
>> "CLK_SRC_MASK1"; i.e., clock source enable/disable should mask the clock
>> source itself, not the clock that is supplied by the clock source.
> 
> No need above message in here.
> 
>> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
>> ---
>>  arch/arm/mach-s5pv210/clock.c |   12 ++++++------
>>  1 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
>> index 154bca4..ec5ad8c 100644
>> --- a/arch/arm/mach-s5pv210/clock.c
>> +++ b/arch/arm/mach-s5pv210/clock.c
>> @@ -406,13 +406,13 @@ static struct clk init_clocks_disable[] = {
>>  		.id		= 0,
>>  		.parent		= &clk_p,
>>  		.enable		= s5pv210_clk_ip3_ctrl,
>> -		.ctrlbit	= (1<<4),
>> +		.ctrlbit	= (1<<5),
>>  	}, {
>>  		.name		= "i2s_v32",
>>  		.id		= 1,
>>  		.parent		= &clk_p,
>>  		.enable		= s5pv210_clk_ip3_ctrl,
>> -		.ctrlbit	= (1<<4),
>> +		.ctrlbit	= (1<<6),
> 
> Your point is right..but your updated code was wrong :-(
> 

?

> Should be like below.
> 

It's same code.

> @@ -400,19 +400,19 @@ static struct clk init_clocks_disable[] = {
>  		.id		= 0,
>  		.parent		= &clk_p,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<4),
> +		.ctrlbit	= (1 << 4),
>  	}, {
>  		.name		= "i2s_v32",
>  		.id		= 0,
>  		.parent		= &clk_p,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<4),
> +		.ctrlbit	= (1 << 5),
>  	}, {
>  		.name		= "i2s_v32",
>  		.id		= 1,
>  		.parent		= &clk_p,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<4),
> +		.ctrlbit	= (1 << 6),
> 
>>  	}
>>  };
>>
>> @@ -429,25 +429,25 @@ static struct clk init_clocks[] = {
>>  		.id		= 0,
>>  		.parent		= &clk_pclk_psys.clk,
>>  		.enable		= s5pv210_clk_ip3_ctrl,
>> -		.ctrlbit	= (1<<7),
>> +		.ctrlbit	= (1<<17),
>>  	}, {
>>  		.name		= "uart",
>>  		.id		= 1,
>>  		.parent		= &clk_pclk_psys.clk,
>>  		.enable		= s5pv210_clk_ip3_ctrl,
>> -		.ctrlbit	= (1<<8),
>> +		.ctrlbit	= (1<<18),
>>  	}, {
>>  		.name		= "uart",
>>  		.id		= 2,
>>  		.parent		= &clk_pclk_psys.clk,
>>  		.enable		= s5pv210_clk_ip3_ctrl,
>> -		.ctrlbit	= (1<<9),
>> +		.ctrlbit	= (1<<19),
>>  	}, {
>>  		.name		= "uart",
>>  		.id		= 3,
>>  		.parent		= &clk_pclk_psys.clk,
>>  		.enable		= s5pv210_clk_ip3_ctrl,
>> -		.ctrlbit	= (1<<10),
>> +		.ctrlbit	= (1<<20),
> 
> How about adding blank on both of '<<' like (1 << x) for easily reading?
> 
>>  	},
>>  };
>>
>> --
> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 



From eric.y.miao at gmail.com  Thu Jun 17 23:43:37 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 11:43:37 +0800
Subject: Several questions regarding ARCH_S3C2410
Message-ID: <AANLkTimPk6mtyB57jXuAq1ugQseS655OCPEuP9-qZYoT@mail.gmail.com>

Hi Ben,

While working towards a unified kernel, I found that ARCH_S3C2410 actually
includes multiple mach-* already.

linux-2.6$ git grep "ARCH_S3C2410" arch/arm/Makefile
arch/arm/Makefile:machine-$(CONFIG_ARCH_S3C2410)	:= s3c2410 s3c2400
s3c2412 s3c2416 s3c2440 s3c2443

There are several questions though:

1. It looks like only s3c2410 is significant, so all the common definitions
   like PHYS_OFFSET are actually same across all mach-s3c24* (except for
   s3c24a0) ? Yet I've found arch/arm/mach-s3c2400/include/mach/memory.h,
   where a different PHYS_OFFSET is defined, just feel a bit confused.

2. So except for s3c24a0, theretically, it's possible to combine all these
   mach into something mach-s3c24xx?

3. When trying building of s3c2410_defconfig, there are a lot complaints
   about re-definitions of {in,out}[s]{b,w,l}.  Taking a look into io.h,
   I'm wondering if it's possible to use those definitions in asm/io.h?
   (possibly with a customized __io())

In file included from linux-2.6/include/linux/scatterlist.h:8,
                 from linux-2.6/include/linux/dma-mapping.h:7,
                 from linux-2.6/include/linux/dmaengine.h:26,
                 from linux-2.6/include/linux/skbuff.h:30,
                 from linux-2.6/lib/kobject_uevent.c:24:
linux-2.6/arch/arm/include/asm/io.h:137: warning: "outb" redefined
linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:196: note: this is
the location of the previous definition
linux-2.6/arch/arm/include/asm/io.h:138: warning: "outw" redefined
linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:197: note: this is
the location of the previous definition
linux-2.6/arch/arm/include/asm/io.h:140: warning: "outl" redefined
linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:198: note: this is
the location of the previous definition
linux-2.6/arch/arm/include/asm/io.h:143: warning: "inb" redefined
linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:193: note: this is
the location of the previous definition
linux-2.6/arch/arm/include/asm/io.h:144: warning: "inw" redefined
linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:194: note: this is
the location of the previous definition
linux-2.6/arch/arm/include/asm/io.h:146: warning: "inl" redefined
linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:195: note: this is
the location of the previous definition
linux-2.6/arch/arm/include/asm/io.h:149: warning: "outsb" redefined
linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:207: note: this is
the location of the previous definition
linux-2.6/arch/arm/include/asm/io.h:150: warning: "outsw" redefined
linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:208: note: this is
the location of the previous definition
linux-2.6/arch/arm/include/asm/io.h:151: warning: "outsl" redefined
linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:209: note: this is
the location of the previous definition
linux-2.6/arch/arm/include/asm/io.h:153: warning: "insb" redefined
linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:203: note: this is
the location of the previous definition
linux-2.6/arch/arm/include/asm/io.h:154: warning: "insw" redefined
linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:204: note: this is
the location of the previous definition
linux-2.6/arch/arm/include/asm/io.h:155: warning: "insl" redefined
linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:205: note: this is
the location of the previous definition


From eric.y.miao at gmail.com  Fri Jun 18 00:03:46 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 12:03:46 +0800
Subject: [PATCH 1/4] [ARM] Remove now unnecessary dma_needs_bounce()
In-Reply-To: <1275724538-5075-2-git-send-email-eric.y.miao@gmail.com>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com> 
	<1275724538-5075-2-git-send-email-eric.y.miao@gmail.com>
Message-ID: <AANLkTilJ3UpyHEplDqS_nV8SVDcl_pRRn4glDn7JS1GW@mail.gmail.com>

On Sat, Jun 5, 2010 at 3:55 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> With a correct dev->dma_mask before calling dmabounce_register_dev(),
> dma_needs_bounce() is not necessary.
>
> The above is true for it8152.c and ixp4xx/common-pci.c.
>
> The sa1111, though, is a bit complicated. Until it's fully understood
> and fixed, dma_needs_bounce() for sa1111 is kept if CONFIG_SA1111 is
> enabled with no side effect (with the condition of machine_is_*)
>

Sorry I forgot to CC you two. Any feedback is welcome, thanks.

> Signed-off-by: Eric Miao <eric.y.miao at gmail.com>
> ---
> ?arch/arm/common/it8152.c ? ? ? ? ? | ? ?8 --------
> ?arch/arm/include/asm/dma-mapping.h | ? ?7 +++++++
> ?arch/arm/mach-ixp4xx/common-pci.c ?| ? ?5 -----
> ?3 files changed, 7 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
> index 7974baa..6c09135 100644
> --- a/arch/arm/common/it8152.c
> +++ b/arch/arm/common/it8152.c
> @@ -263,14 +263,6 @@ static int it8152_pci_platform_notify_remove(struct device *dev)
> ? ? ? ?return 0;
> ?}
>
> -int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
> -{
> - ? ? ? dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
> - ? ? ? ? ? ? ? __func__, dma_addr, size);
> - ? ? ? return (dev->bus == &pci_bus_type) &&
> - ? ? ? ? ? ? ? ((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
> -}
> -
> ?int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
> ?{
> ? ? ? ?it8152_io.start = IT8152_IO_BASE + 0x12000;
> diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
> index 69ce072..c80d4d2 100644
> --- a/arch/arm/include/asm/dma-mapping.h
> +++ b/arch/arm/include/asm/dma-mapping.h
> @@ -298,7 +298,14 @@ extern void dmabounce_unregister_dev(struct device *);
> ?* DMA access and 1 if the buffer needs to be bounced.
> ?*
> ?*/
> +#ifdef CONFIG_SA1111
> ?extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
> +#else
> +static inline int dma_needs_bounce(struct device*, dma_addr_t, size_t)
> +{
> + ? ? ? return 0;
> +}
> +#endif
>
> ?/*
> ?* The DMA API, implemented by dmabounce.c. ?See below for descriptions.
> diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
> index e318153..c7aa0ac 100644
> --- a/arch/arm/mach-ixp4xx/common-pci.c
> +++ b/arch/arm/mach-ixp4xx/common-pci.c
> @@ -337,11 +337,6 @@ static int ixp4xx_pci_platform_notify_remove(struct device *dev)
> ? ? ? ?return 0;
> ?}
>
> -int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
> -{
> - ? ? ? return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
> -}
> -
> ?/*
> ?* Only first 64MB of memory can be accessed via PCI.
> ?* We use GFP_DMA to allocate safe buffers to do map/unmap.
> --
> 1.7.0.4
>
>


From eric.y.miao at gmail.com  Fri Jun 18 00:15:45 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 12:15:45 +0800
Subject: [Question] SuspendToDisk Feature on ARM ?
In-Reply-To: <AANLkTinXqVqe9xWQYj-CyzPHl9k7qAqxX6ueOqB3qTve@mail.gmail.com>
References: <AANLkTinXqVqe9xWQYj-CyzPHl9k7qAqxX6ueOqB3qTve@mail.gmail.com>
Message-ID: <AANLkTimmvPMG0GFEXfgFlXgC7V4dIWmW8vEC5gegsKSE@mail.gmail.com>

On Thu, Jun 17, 2010 at 10:08 PM, sumeet linux <sumeet4linux at gmail.com> wrote:
> Hi List,
>
> Does there exists a support for Suspend To Disk (Hibernate) for ARM
> platforms?
> I have been googling for it but could not find any information other than
> some links to the suspend2 support for some ancient kernels.
> Can anyone provide any clue on how much effort is required to implement this
> feature to ARM architecture ?
>

Marvell has done a great job on this for a preliminary enabling on their Dove
processor, please have a look into:

http://kernel.ubuntu.com/git?p=ubuntu/ubuntu-lucid.git;a=shortlog;h=refs/heads/mvl-dove

arch/arm/mach-dove/swsusp.S

The code, mostly, is generic enough to be made common if you are
interested and have other platforms (with HDD or large NAND) to
test. x86 is, of course, the reference.


From u.kleine-koenig at pengutronix.de  Fri Jun 18 01:27:09 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 18 Jun 2010 07:27:09 +0200
Subject: gpiolib and sleeping gpios
In-Reply-To: <4C1A980F.8080908@bluewatersys.com>
References: <4C1A980F.8080908@bluewatersys.com>
Message-ID: <20100618052709.GA6392@pengutronix.de>

Hi Ryan,

On Fri, Jun 18, 2010 at 09:47:59AM +1200, Ryan Mallon wrote:
> Then all drivers can just call gpio_(set/get)_value and any attempts to
> use sleeping gpios from an non-sleeping context will be caught by the
> might_sleep_if check. Is there something I am missing about this?
The downside is that you change the semantic of gpio_get_value (and
gpio_set_value I assume?).  But as calling gpio_get_value with a gpio
that gpio_cansleep() is an error anyhow, so I think that's OK.  The big
pro is that the API is simplified.
 
> I can prepare a patch which combines the non-sleeping and sleeping
> variants, but I wanted to check that I'm not missing something
> fundamental first.
I will happily look at such a patch and give my comments.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From haojian.zhuang at gmail.com  Fri Jun 18 01:32:42 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:32:42 +0800
Subject: [PATCH 01/25] pxa3xx_nand: condense the flash definition
Message-ID: <AANLkTil1FnPkGS7l6W0HWeXyOxXzWbZkvFWY4jJF_I_A@mail.gmail.com>


From haojian.zhuang at gmail.com  Fri Jun 18 01:33:29 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:33:29 +0800
Subject: [PATCH 0/25] update pxa3xx nand
Message-ID: <AANLkTimrYNN0JYnWw5peeuVYkiOF7Yz5Hn5oIBXdlg9m@mail.gmail.com>

This patch series are used to upgrade NAND controller of PXA series.

1. Support multi chips.
2. Support new NAND controller in PXA series.
3. Support MLC NAND.
4. Support BCH ECC.
5. Optimize flash definition.


From haojian.zhuang at gmail.com  Fri Jun 18 01:33:38 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:33:38 +0800
Subject: [PATCH 02/25] pxa3xx_nand: introduce common timing to reduce read id 
	times
Message-ID: <AANLkTim1qcVoqSS7T8bE0Vsu6phC2iY_Ok671WYHcD0z@mail.gmail.com>


From leiwen at marvell.com  Wed Jun  2 09:50:25 2010
From: leiwen at marvell.com (Lei Wen)
Date: Wed, 2 Jun 2010 21:50:25 +0800
Subject: [PATCH 02/25] pxa3xx_nand: introduce common timing to reduce
Message-ID: <mailman.4.1276839228.27306.linux-arm-kernel@lists.infradead.org>

read id times

We certainly don't need to send read id command times by times, since
we already know what the id is after the first read id...

So create a common timing which could ensure it would successfully read id
out all supported chip. Then follow the build-in table to reconfigure
the timing.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |   72 ++++++++++++++++-----------------------
 1 files changed, 30 insertions(+), 42 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 013e075..f939083 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -226,23 +226,26 @@ const static struct pxa3xx_nand_cmdset cmdset = {
 };

 static struct pxa3xx_nand_timing __devinitdata timing[] = {
+	/* common timing used to detect flash id */
+	{ 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
 	/* Samsung NAND series */
-	{ 10,  0, 20, 40, 30, 40, 11123, 110, 10, },
+	{ 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
 	/* Micron NAND series */
-	{ 10, 25, 15, 25, 15, 30, 25000,  60, 10, },
+	{ 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
 	/* ST NAND series */
-	{ 10, 35, 15, 25, 15, 25, 25000,  60, 10, },
+	{ 10, 35, 15,  25, 15,  25, 25000,  60, 10, },
 };

 static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
-	{ 0x46ec,  32,  512, 16, 16, 4096, &timing[0], },
-	{ 0xdaec,  64, 2048,  8,  8, 2048, &timing[0], },
-	{ 0xd7ec, 128, 4096,  8,  8, 8192, &timing[0], },
-	{ 0xa12c,  64, 2048,  8,  8, 1024, &timing[1], },
-	{ 0xb12c,  64, 2048, 16, 16, 1024, &timing[1], },
-	{ 0xdc2c,  64, 2048,  8,  8, 4096, &timing[1], },
-	{ 0xcc2c,  64, 2048, 16, 16, 4096, &timing[1], },
-	{ 0xba20,  64, 2048, 16, 16, 2048, &timing[2], },
+	{      0,   0,    0,  0,  0,    0, &timing[0], },
+	{ 0x46ec,  32,  512, 16, 16, 4096, &timing[1], },
+	{ 0xdaec,  64, 2048,  8,  8, 2048, &timing[1], },
+	{ 0xd7ec, 128, 4096,  8,  8, 8192, &timing[1], },
+	{ 0xa12c,  64, 2048,  8,  8, 1024, &timing[2], },
+	{ 0xb12c,  64, 2048, 16, 16, 1024, &timing[2], },
+	{ 0xdc2c,  64, 2048,  8,  8, 4096, &timing[2], },
+	{ 0xcc2c,  64, 2048, 16, 16, 4096, &timing[2], },
+	{ 0xba20,  64, 2048, 16, 16, 2048, &timing[3], },
 };

 #define NDTR0_tCH(c)	(min((c), 7) << 19)
@@ -859,12 +862,6 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 	uint32_t ndcr = 0x00000FFF; /* disable all interrupts */

-	if (f->page_size != 2048 && f->page_size != 512)
-		return -EINVAL;
-
-	if (f->flash_width != 16 && f->flash_width != 8)
-		return -EINVAL;
-
 	/* calculate flash information */
 	info->oob_size = (f->page_size == 2048) ? 64 : 16;
 	info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
@@ -976,36 +973,27 @@ static int pxa3xx_nand_detect_flash(struct
pxa3xx_nand_info *info,
 		if (pxa3xx_nand_detect_config(info) == 0)
 			return 0;

-	for (i = 0; i<pdata->num_flash; ++i) {
-		f = pdata->flash + i;
-
-		if (pxa3xx_nand_config_flash(info, f))
-			continue;
-
-		if (__readid(info, &id))
-			continue;
-
-		if (id == f->chip_id)
-			return 0;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
-
-		f = &builtin_flash_types[i];
-
-		if (pxa3xx_nand_config_flash(info, f))
-			continue;
-
-		if (__readid(info, &id))
-			continue;
-
-		if (id == f->chip_id)
+	f = &builtin_flash_types[0];
+	pxa3xx_nand_config_flash(info, f);
+	if (__readid(info, &id))
+		goto fail_detect;
+
+	for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
+		if (i < pdata->num_flash)
+			f = pdata->flash + i;
+		else
+			f = &builtin_flash_types[i - pdata->num_flash + 1];
+		if (f->chip_id == id) {
+			dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
+			pxa3xx_nand_config_flash(info, f);
 			return 0;
+		}
 	}

 	dev_warn(&info->pdev->dev,
-		 "failed to detect configured nand flash; found %04x instead of\n",
+			"failed to detect configured nand flash; found %04x instead of\n",
 		 id);
+fail_detect:
 	return -ENODEV;
 }

-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:33:54 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:33:54 +0800
Subject: [PATCH 04/25] pxa3xx_nand: make scan procedure more clear
Message-ID: <AANLkTiliVtvBEmJPgkha444k9XGB_dNm0lQ9TCif8AAj@mail.gmail.com>


From haojian.zhuang at gmail.com  Fri Jun 18 01:34:18 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:34:18 +0800
Subject: [PATCH 07/25] pxa3xx_nand: mtd scan id process could be defined by 
	driver itself
Message-ID: <AANLkTilY1gnS_jwZ_xPKhchTLR5cWj7FEla1V76OuMVK@mail.gmail.com>


From leiwen at marvell.com  Wed Jun  2 09:55:51 2010
From: leiwen at marvell.com (Lei Wen)
Date: Wed, 2 Jun 2010 21:55:51 +0800
Subject: [PATCH 07/25] pxa3xx_nand: mtd scan id process could be
Message-ID: <mailman.11.1276839348.27306.linux-arm-kernel@lists.infradead.org>

defined by driver itself

Different NAND driver may require its unique detection. For pxa3xx_nand,
it use its self id database to get the necessary info.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  255 ++++++++++++++++++++++++++--------------
 1 files changed, 165 insertions(+), 90 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 9ab292b..481cb25 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -158,6 +158,7 @@ struct pxa3xx_nand_flash {
 struct pxa3xx_nand_info {
 	struct nand_chip	nand_chip;

+	struct nand_hw_control	controller;
 	struct platform_device	 *pdev;

 	struct clk		*clk;
@@ -261,6 +262,8 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
 	{ 0xba20,  64, 2048, 16, 16, 2048, &timing[3], },
 };

+static const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
+
 #define NDTR0_tCH(c)	(min((c), 7) << 19)
 #define NDTR0_tCS(c)	(min((c), 7) << 16)
 #define NDTR0_tWH(c)	(min((c), 7) << 11)
@@ -899,40 +902,6 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand_info *info)
 	return 0;
 }

-static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
-				    const struct pxa3xx_nand_platform_data *pdata)
-{
-	const struct pxa3xx_nand_flash *f;
-	uint32_t id = -1;
-	int i;
-
-	if (pdata->keep_config)
-		if (pxa3xx_nand_detect_config(info) == 0)
-			return 0;
-
-	f = &builtin_flash_types[0];
-	pxa3xx_nand_config_flash(info, f);
-	pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
-	id = *((uint16_t *)(info->data_buff));
-
-	for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
-		if (i < pdata->num_flash)
-			f = pdata->flash + i;
-		else
-			f = &builtin_flash_types[i - pdata->num_flash + 1];
-		if (f->chip_id == id) {
-			dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
-			pxa3xx_nand_config_flash(info, f);
-			return 0;
-		}
-	}
-
-	dev_warn(&info->pdev->dev,
-			"failed to detect configured nand flash; found %04x instead of\n",
-		 id);
-	return -ENODEV;
-}
-
 /* the maximum possible buffer size for large page with OOB data
  * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
  * data buffer and the DMA descriptor
@@ -974,56 +943,153 @@ static int pxa3xx_nand_init_buff(struct
pxa3xx_nand_info *info)
 	return 0;
 }

-static struct nand_ecclayout hw_smallpage_ecclayout = {
-	.eccbytes = 6,
-	.eccpos = {8, 9, 10, 11, 12, 13 },
-	.oobfree = { {2, 6} }
-};
+static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
+		struct nand_chip *chip, uint8_t *buf, int page)
+{
+	struct pxa3xx_nand_info *info = mtd->priv;

-static struct nand_ecclayout hw_largepage_ecclayout = {
-	.eccbytes = 24,
-	.eccpos = {
-		40, 41, 42, 43, 44, 45, 46, 47,
-		48, 49, 50, 51, 52, 53, 54, 55,
-		56, 57, 58, 59, 60, 61, 62, 63},
-	.oobfree = { {2, 38} }
-};
+	chip->read_buf(mtd, buf, mtd->writesize);
+	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+	if (info->retcode == ERR_SBERR) {
+		switch (info->use_ecc) {
+			case 1:
+				mtd->ecc_stats.corrected ++;
+				break;
+
+			case 0:
+			default:
+				break;
+		}
+	}
+	else if (info->retcode == ERR_DBERR) {
+		int buf_blank;
+
+		buf_blank = is_buf_blank(buf, mtd->writesize);
+		if (!buf_blank)
+			mtd->ecc_stats.failed++;
+	}
+
+	return 0;
+}
+
+static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
+		struct nand_chip *chip, const uint8_t *buf)
+{
+	chip->write_buf(mtd, buf, mtd->writesize);
+	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+}
+
+static void pxa3xx_nand_erase_cmd(struct mtd_info *mtd, int page)
+{
+	struct nand_chip *chip = mtd->priv;
+	/* Send commands to erase a block */
+	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+}

-static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
-				 struct pxa3xx_nand_info *info)
+static int __devinit pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
 {
-	struct nand_chip *this = &info->nand_chip;
-
-	this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;
-
-	this->waitfunc		= pxa3xx_nand_waitfunc;
-	this->select_chip	= pxa3xx_nand_select_chip;
-	this->dev_ready		= pxa3xx_nand_dev_ready;
-	this->cmdfunc		= pxa3xx_nand_cmdfunc;
-	this->read_word		= pxa3xx_nand_read_word;
-	this->read_byte		= pxa3xx_nand_read_byte;
-	this->read_buf		= pxa3xx_nand_read_buf;
-	this->write_buf		= pxa3xx_nand_write_buf;
-	this->verify_buf	= pxa3xx_nand_verify_buf;
-
-	this->ecc.mode		= NAND_ECC_HW;
-	this->ecc.hwctl		= pxa3xx_nand_ecc_hwctl;
-	this->ecc.calculate	= pxa3xx_nand_ecc_calculate;
-	this->ecc.correct	= pxa3xx_nand_ecc_correct;
-	this->ecc.size		= info->page_size;
-
-	if (info->page_size == 2048)
-		this->ecc.layout = &hw_largepage_ecclayout;
+	struct mtd_info *mtd = info->mtd;
+	struct nand_chip *chip = mtd->priv;
+
+	/* use the common timing to make a try */
+	pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
+	chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
+	if (info->state & STATE_READY)
+		return 1;
 	else
-		this->ecc.layout = &hw_smallpage_ecclayout;
+		return 0;
+}
+
+static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd)
+{
+	struct pxa3xx_nand_info *info = mtd->priv;
+	struct platform_device *pdev = info->pdev;
+	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
+	const struct pxa3xx_nand_flash *f = NULL;
+	struct nand_chip *chip = mtd->priv;
+	uint32_t id = -1;
+	int i, ret;
+
+	if (pdata->keep_config)
+		if (pxa3xx_nand_detect_config(info) == 0)
+			return 0;
+
+	ret = pxa3xx_nand_sensing(info);
+	if (!ret) {
+		kfree(mtd);
+		info->mtd = NULL;
+		printk(KERN_INFO "There is no nand chip on cs 0!\n");

-	this->chip_delay = 25;
+		return -EINVAL;
+	}
+
+	chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
+	id = *((uint16_t *)(info->data_buff));
+	if (id != 0)
+		printk(KERN_INFO "Detect a flash id %x\n", id);
+	else {
+		kfree(mtd);
+		info->mtd = NULL;
+		printk(KERN_WARNING "Read out ID 0, potential timing set wrong!!\n");
+
+		return -EINVAL;
+	}
+
+	for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
+		if (i < pdata->num_flash)
+			f = pdata->flash + i;
+		else
+			f = &builtin_flash_types[i - pdata->num_flash + 1];
+
+		/* find the chip in default list */
+		if (f->chip_id == id) {
+			pxa3xx_nand_config_flash(info, f);
+			mtd->writesize = f->page_size;
+			mtd->writesize_shift = ffs(mtd->writesize) - 1;
+			mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
+			mtd->oobsize = mtd->writesize / 32;
+			mtd->erasesize = f->page_size * f->page_per_block;
+			mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
+			mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
+
+			mtd->name = mtd_names[0];
+			break;
+		}
+	}
+
+	if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash)) {
+		kfree(mtd);
+		info->mtd = NULL;
+		printk(KERN_ERR "ERROR!! flash not defined!!!\n");
+
+		return -EINVAL;
+	}
+
+	chip->ecc.mode = NAND_ECC_HW;
+	chip->ecc.size = f->page_size;
+	chip->chipsize 	= (uint64_t)f->num_blocks * f->page_per_block
+				* f->page_size;
+	mtd->size = chip->chipsize;
+
+	/* Calculate the address shift from the page size */
+	chip->page_shift = ffs(mtd->writesize) - 1;
+	chip->pagemask = mtd_div_by_ws(chip->chipsize, mtd) - 1;
+	chip->numchips = 1;
+	chip->bbt_erase_shift = chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
+
+	chip->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
+	chip->options |= NAND_NO_AUTOINCR;
+	chip->options |= NAND_NO_READRDY;
+	chip->options |= NAND_USE_FLASH_BBT;
+
+	return nand_scan_tail(mtd);
 }

 static int alloc_nand_resource(struct platform_device *pdev)
 {
-	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 	struct pxa3xx_nand_info *info;
+	struct nand_chip *chip;
 	struct mtd_info *mtd;
 	struct resource *r;
 	int ret, irq;
@@ -1036,12 +1102,31 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 	}

 	info = (struct pxa3xx_nand_info *)(&mtd[1]);
+	chip = (struct nand_chip *)(&mtd[1]);
 	info->pdev = pdev;
-
-	mtd->priv = info;
 	info->mtd = mtd;
+	mtd->priv = info;
 	mtd->owner = THIS_MODULE;

+	chip->ecc.read_page	= pxa3xx_nand_read_page_hwecc;
+	chip->ecc.write_page	= pxa3xx_nand_write_page_hwecc;
+	chip->ecc.hwctl		= pxa3xx_nand_ecc_hwctl;
+	chip->ecc.calculate	= pxa3xx_nand_ecc_calculate;
+	chip->ecc.correct	= pxa3xx_nand_ecc_correct;
+	chip->controller        = &info->controller;
+	chip->waitfunc		= pxa3xx_nand_waitfunc;
+	chip->select_chip	= pxa3xx_nand_select_chip;
+	chip->dev_ready		= pxa3xx_nand_dev_ready;
+	chip->cmdfunc		= pxa3xx_nand_cmdfunc;
+	chip->read_word		= pxa3xx_nand_read_word;
+	chip->read_byte		= pxa3xx_nand_read_byte;
+	chip->read_buf		= pxa3xx_nand_read_buf;
+	chip->write_buf		= pxa3xx_nand_write_buf;
+	chip->verify_buf	= pxa3xx_nand_verify_buf;
+	chip->erase_cmd		= pxa3xx_nand_erase_cmd;
+
+	spin_lock_init(&chip->controller->lock);
+	init_waitqueue_head(&chip->controller->wq);
 	info->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(info->clk)) {
 		dev_err(&pdev->dev, "failed to get nand clock\n");
@@ -1109,21 +1194,11 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		goto fail_free_buf;
 	}

-	ret = pxa3xx_nand_detect_flash(info, pdata);
-	if (ret) {
-		dev_err(&pdev->dev, "failed to detect flash\n");
-		ret = -ENODEV;
-		goto fail_free_irq;
-	}
-
-	pxa3xx_nand_init_mtd(mtd, info);
 	platform_set_drvdata(pdev, info);
-
 	return 0;

-fail_free_irq:
-	free_irq(irq, info);
 fail_free_buf:
+	free_irq(irq, info);
 	if (use_dma) {
 		pxa_free_dma(info->data_dma_ch);
 		dma_free_coherent(&pdev->dev, info->data_buff_size,
@@ -1191,7 +1266,7 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 		return ret;

 	info = platform_get_drvdata(pdev);
-	if (nand_scan(info->mtd, 1)) {
+	if (pxa3xx_nand_scan(info->mtd)) {
 		dev_err(&pdev->dev, "failed to scan nand\n");
 		pxa3xx_nand_remove(pdev);
 		return -ENODEV;
@@ -1202,10 +1277,10 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 		struct mtd_partition *parts;
 		int nr_parts;

-		nr_parts = parse_mtd_partitions(mtd, probes, &parts, 0);
+		nr_parts = parse_mtd_partitions(info->mtd, probes, &parts, 0);

 		if (nr_parts)
-			return add_mtd_partitions(mtd, parts, nr_parts);
+			return add_mtd_partitions(info->mtd, parts, nr_parts);
 	}

 	return add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts);
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:33:46 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:33:46 +0800
Subject: [PATCH 03/25] pxa3xx_nand: remove the flash info in driver structure
Message-ID: <AANLkTimbCSM3Kk-Mq3MhRDyhHAaERR-dXhtuplauB3ki@mail.gmail.com>


From leiwen at marvell.com  Wed Jun  2 09:54:33 2010
From: leiwen at marvell.com (Lei Wen)
Date: Wed, 2 Jun 2010 21:54:33 +0800
Subject: [PATCH 03/25] pxa3xx_nand: remove the flash info in driver structure
Message-ID: <mailman.13.1276839365.27306.linux-arm-kernel@lists.infradead.org>

After probe, all info already transfer to driver structure.
There is no need to keep the original flash info.
So that we could safely free the flash info in memory, which may grows
larger when more flash is suported.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |   70 ++++++++++++++++++++++++++--------------
 1 files changed, 46 insertions(+), 24 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index f939083..291610a 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -152,7 +152,6 @@ struct pxa3xx_nand_info {
 	struct nand_chip	nand_chip;

 	struct platform_device	 *pdev;
-	const struct pxa3xx_nand_flash *flash_info;

 	struct clk		*clk;
 	void __iomem		*mmio_base;
@@ -166,6 +165,7 @@ struct pxa3xx_nand_info {
 	int			drcmr_cmd;

 	unsigned char		*data_buff;
+	unsigned char		*oob_buff;
 	dma_addr_t 		data_buff_phys;
 	size_t			data_buff_size;
 	int 			data_dma_ch;
@@ -184,7 +184,8 @@ struct pxa3xx_nand_info {
 	int			use_ecc;	/* use HW ECC ? */
 	int			use_dma;	/* use DMA ? */

-	size_t			data_size;	/* data size in FIFO */
+	unsigned int		page_size;	/* page size of attached chip */
+	unsigned int		data_size;	/* data size in FIFO */
 	int 			retcode;
 	struct completion 	cmd_complete;

@@ -193,6 +194,10 @@ struct pxa3xx_nand_info {
 	uint32_t		ndcb1;
 	uint32_t		ndcb2;

+	/* timing calcuted from setting */
+	uint32_t		ndtr0cs0;
+	uint32_t		ndtr1cs0;
+
 	/* calculated from pxa3xx_nand_flash data */
 	size_t		oob_size;
 	size_t		read_id_bytes;
@@ -293,6 +298,8 @@ static void pxa3xx_nand_set_timing(struct
pxa3xx_nand_info *info,
 		NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
 		NDTR1_tAR(ns2cycle(t->tAR, nand_clk));

+	info->ndtr0cs0 = ndtr0;
+	info->ndtr1cs0 = ndtr1;
 	nand_writel(info, NDTR0CS0, ndtr0);
 	nand_writel(info, NDTR1CS0, ndtr1);
 }
@@ -316,22 +323,29 @@ static int wait_for_event(struct
pxa3xx_nand_info *info, uint32_t event)
 	return -ETIMEDOUT;
 }

-static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
-			uint16_t cmd, int column, int page_addr)
+static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 {
-	const struct pxa3xx_nand_flash *f = info->flash_info;
+	int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;

-	/* calculate data size */
-	switch (f->page_size) {
-	case 2048:
-		info->data_size = (info->use_ecc) ? 2088 : 2112;
-		break;
-	case 512:
-		info->data_size = (info->use_ecc) ? 520 : 528;
-		break;
-	default:
-		return -EINVAL;
+	info->data_size = info->page_size;
+	if (!oob_enable) {
+		info->oob_size = 0;
+		return;
 	}
+	switch (info->page_size) {
+		case 2048:
+			info->oob_size = (info->use_ecc) ? 40 : 64;
+			break;
+		case 512:
+			info->oob_size = (info->use_ecc) ? 8 : 16;
+			break;
+	}
+}
+
+static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
+		uint16_t cmd, int column, int page_addr)
+{
+	pxa3xx_set_datasize(info);

 	/* generate values for NDCBx registers */
 	info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
@@ -442,6 +456,9 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
 	case STATE_PIO_WRITING:
 		__raw_writesl(info->mmio_base + NDDB, info->data_buff,
 				DIV_ROUND_UP(info->data_size, 4));
+		if (info->oob_size > 0)
+			__raw_writesl(info->mmio_base + NDDB, info->oob_buff,
+					DIV_ROUND_UP(info->oob_size, 4));

 		enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);

@@ -454,6 +471,10 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
 	case STATE_PIO_READING:
 		__raw_readsl(info->mmio_base + NDDB, info->data_buff,
 				DIV_ROUND_UP(info->data_size, 4));
+		if (info->oob_size > 0)
+			__raw_readsl(info->mmio_base + NDDB, info->oob_buff,
+					DIV_ROUND_UP(info->oob_size, 4));
+
 		break;
 	default:
 		printk(KERN_ERR "%s: invalid state %d\n", __func__,
@@ -468,7 +489,7 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
 static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
 {
 	struct pxa_dma_desc *desc = info->data_desc;
-	int dma_len = ALIGN(info->data_size, 32);
+	int dma_len = ALIGN(info->data_size + info->oob_size, 32);

 	desc->ddadr = DDADR_STOP;
 	desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
@@ -863,6 +884,8 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	uint32_t ndcr = 0x00000FFF; /* disable all interrupts */

 	/* calculate flash information */
+	info->page_size = f->page_size;
+	info->oob_buff = info->data_buff + f->page_size;
 	info->oob_size = (f->page_size == 2048) ? 64 : 16;
 	info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;

@@ -887,7 +910,6 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	info->reg_ndcr = ndcr;

 	pxa3xx_nand_set_timing(info, f->timing);
-	info->flash_info = f;
 	return 0;
 }

@@ -923,7 +945,6 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand_info *info)
 	default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;

 	/* set info fields needed to __readid */
-	info->flash_info = &default_flash;
 	info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
 	info->reg_ndcr = ndcr;

@@ -1056,10 +1077,9 @@ static struct nand_ecclayout hw_largepage_ecclayout = {
 static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
 				 struct pxa3xx_nand_info *info)
 {
-	const struct pxa3xx_nand_flash *f = info->flash_info;
 	struct nand_chip *this = &info->nand_chip;

-	this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
+	this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;

 	this->waitfunc		= pxa3xx_nand_waitfunc;
 	this->select_chip	= pxa3xx_nand_select_chip;
@@ -1075,9 +1095,9 @@ static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
 	this->ecc.hwctl		= pxa3xx_nand_ecc_hwctl;
 	this->ecc.calculate	= pxa3xx_nand_ecc_calculate;
 	this->ecc.correct	= pxa3xx_nand_ecc_correct;
-	this->ecc.size		= f->page_size;
+	this->ecc.size		= info->page_size;

-	if (f->page_size == 2048)
+	if (info->page_size == 2048)
 		this->ecc.layout = &hw_largepage_ecclayout;
 	else
 		this->ecc.layout = &hw_smallpage_ecclayout;
@@ -1085,7 +1105,7 @@ static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
 	this->chip_delay = 25;
 }

-static int pxa3xx_nand_probe(struct platform_device *pdev)
+static int __devinit pxa3xx_nand_probe(struct platform_device *pdev)
 {
 	struct pxa3xx_nand_platform_data *pdata;
 	struct pxa3xx_nand_info *info;
@@ -1284,9 +1304,11 @@ static int pxa3xx_nand_resume(struct
platform_device *pdev)
 	struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
 	struct pxa3xx_nand_info *info = mtd->priv;

+	nand_writel(info, NDTR0CS0, info->ndtr0cs0);
+	nand_writel(info, NDTR1CS0, info->ndtr1cs0);
 	clk_enable(info->clk);

-	return pxa3xx_nand_config_flash(info, info->flash_info);
+	return 0;
 }
 #else
 #define pxa3xx_nand_suspend	NULL
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:34:02 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:34:02 +0800
Subject: [PATCH 05/25] pxa3xx_nand: rework irq logic
Message-ID: <AANLkTimvhEWIDupsj3Ty8vB9ualwU9RsaIxa0CDgWgYQ@mail.gmail.com>


From haojian.zhuang at gmail.com  Fri Jun 18 01:34:11 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:34:11 +0800
Subject: [PATCH 06/25] pxa3xx_nand: unify prepare command
Message-ID: <AANLkTilhattkx7AiyG-R4zbWSZ3-qkPIM6VhyFW4lk4D@mail.gmail.com>


From haojian.zhuang at gmail.com  Fri Jun 18 01:34:46 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:34:46 +0800
Subject: [PATCH 10/25] pxa3xx_nand: add two chip select
Message-ID: <AANLkTilhoWJIMoRD2p7rnLx2s9TUlLjfDyTvN2S-fJHx@mail.gmail.com>


From leiwen at marvell.com  Sun Jun  6 09:58:12 2010
From: leiwen at marvell.com (Lei Wen)
Date: Sun, 6 Jun 2010 21:58:12 +0800
Subject: [PATCH 10/25] pxa3xx_nand: add two chip select
Message-ID: <mailman.18.1276839401.27306.linux-arm-kernel@lists.infradead.org>

Current pxa3xx_nand controller has two chip select which
both be workable. This patch enable this feature.

Update platform driver to support this feature.

Another notice should be taken that:
When you want to use this feature, you should not enable the
keep configuration feature, for two chip select could be
attached with different nand chip. The different page size
and timing requirement make the keep configuration impossible.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/mach-mmp/aspenite.c                 |    4 +-
 arch/arm/mach-mmp/avengers_lite.c            |   50 ++
 arch/arm/mach-pxa/cm-x300.c                  |    4 +-
 arch/arm/mach-pxa/colibri-pxa3xx.c           |    4 +-
 arch/arm/mach-pxa/littleton.c                |    4 +-
 arch/arm/mach-pxa/mxm8x10.c                  |    8 +-
 arch/arm/mach-pxa/raumfeld.c                 |    4 +-
 arch/arm/mach-pxa/zylonite.c                 |    4 +-
 arch/arm/plat-pxa/include/plat/pxa3xx_nand.h |    5 +-
 drivers/mtd/nand/pxa3xx_nand.c               |  770 +++++++++++++-------------
 10 files changed, 462 insertions(+), 395 deletions(-)

diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 244655d..81ad58d 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -126,8 +126,8 @@ static struct mtd_partition aspenite_nand_partitions[] = {

 static struct pxa3xx_nand_platform_data aspenite_nand_info = {
 	.enable_arbiter	= 1,
-	.parts		= aspenite_nand_partitions,
-	.nr_parts	= ARRAY_SIZE(aspenite_nand_partitions),
+	.parts[0]	= aspenite_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(aspenite_nand_partitions),
 };

 static struct i2c_board_info aspenite_i2c_info[] __initdata = {
diff --git a/arch/arm/mach-mmp/avengers_lite.c
b/arch/arm/mach-mmp/avengers_lite.c
index 8c3fa5d..a828b1c 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -32,12 +32,62 @@ static unsigned long
avengers_lite_pin_config_V16F[] __initdata = {
 	GPIO89_UART2_RXD,
 };

+static struct mtd_partition avengers_nand_partitions_0[] = {
+	{
+		.name		= "bootloader",
+		.offset		= 0,
+		.size		= SZ_1M,
+		.mask_flags	= MTD_WRITEABLE,
+	}, {
+		.name		= "kernel",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= (SZ_2M + SZ_1M),
+	}, {
+		.name		= "mass0",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_48M,
+	}
+};
+
+static struct mtd_partition avengers_nand_partitions_1[] = {
+	{
+		.name		= "reserved",
+		.offset		= 0,
+		.size		= SZ_2M,
+		.mask_flags	= MTD_WRITEABLE,
+	}, {
+		.name		= "filesystem",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_512M,
+	}, {
+		.name		= "mass1",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_16M,
+	}, {
+		.name		= "mass2",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_256M,
+	}
+};
+
+static struct pxa3xx_nand_platform_data avengers_nand_info;
+static void __init avengers_init_flash(void)
+{
+	avengers_nand_info.parts[0] = avengers_nand_partitions_0;
+	avengers_nand_info.nr_parts[0] = ARRAY_SIZE(avengers_nand_partitions_0);
+	avengers_nand_info.parts[1] = avengers_nand_partitions_1;
+	avengers_nand_info.nr_parts[1] = ARRAY_SIZE(avengers_nand_partitions_1);
+	avengers_nand_info.enable_arbiter = 1;
+	pxa168_add_nand(&avengers_nand_info);
+}
+
 static void __init avengers_lite_init(void)
 {
 	mfp_config(ARRAY_AND_SIZE(avengers_lite_pin_config_V16F));

 	/* on-chip devices */
 	pxa168_add_uart(2);
+	avengers_init_flash();
 }

 MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index fdda6be..ce1f6d3 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -419,8 +419,8 @@ static struct mtd_partition cm_x300_nand_partitions[] = {
 static struct pxa3xx_nand_platform_data cm_x300_nand_info = {
 	.enable_arbiter	= 1,
 	.keep_config	= 1,
-	.parts		= cm_x300_nand_partitions,
-	.nr_parts	= ARRAY_SIZE(cm_x300_nand_partitions),
+	.parts[0]	= cm_x300_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(cm_x300_nand_partitions),
 };

 static void __init cm_x300_init_nand(void)
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c
b/arch/arm/mach-pxa/colibri-pxa3xx.c
index 199afa2..b33559c 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -188,8 +188,8 @@ static struct mtd_partition colibri_nand_partitions[] = {
 static struct pxa3xx_nand_platform_data colibri_nand_info = {
 	.enable_arbiter	= 1,
 	.keep_config	= 1,
-	.parts		= colibri_nand_partitions,
-	.nr_parts	= ARRAY_SIZE(colibri_nand_partitions),
+	.parts[0]	= colibri_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(colibri_nand_partitions),
 };

 void __init colibri_pxa3xx_init_nand(void)
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 9b90461..717cf92 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -325,8 +325,8 @@ static struct mtd_partition littleton_nand_partitions[] = {

 static struct pxa3xx_nand_platform_data littleton_nand_info = {
 	.enable_arbiter	= 1,
-	.parts		= littleton_nand_partitions,
-	.nr_parts	= ARRAY_SIZE(littleton_nand_partitions),
+	.parts[0]	= littleton_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(littleton_nand_partitions),
 };

 static void __init littleton_init_nand(void)
diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c
index 462167a..66c2086 100644
--- a/arch/arm/mach-pxa/mxm8x10.c
+++ b/arch/arm/mach-pxa/mxm8x10.c
@@ -389,10 +389,10 @@ static struct mtd_partition mxm_8x10_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data mxm_8x10_nand_info = {
-	.enable_arbiter = 1,
-	.keep_config = 1,
-	.parts = mxm_8x10_nand_partitions,
-	.nr_parts = ARRAY_SIZE(mxm_8x10_nand_partitions)
+	.enable_arbiter	= 1,
+	.keep_config	= 1,
+	.parts[0]	= mxm_8x10_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(mxm_8x10_nand_partitions)
 };

 static void __init mxm_8x10_nand_init(void)
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index d4b61b3..df75d4d 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -350,8 +350,8 @@ static struct mtd_partition raumfeld_nand_partitions[] = {
 static struct pxa3xx_nand_platform_data raumfeld_nand_info = {
 	.enable_arbiter	= 1,
 	.keep_config	= 1,
-	.parts		= raumfeld_nand_partitions,
-	.nr_parts	= ARRAY_SIZE(raumfeld_nand_partitions),
+	.parts[0]	= raumfeld_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(raumfeld_nand_partitions),
 };

 /**
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index c479cbe..9e5c6cd 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -356,8 +356,8 @@ static struct mtd_partition zylonite_nand_partitions[] = {

 static struct pxa3xx_nand_platform_data zylonite_nand_info = {
 	.enable_arbiter	= 1,
-	.parts		= zylonite_nand_partitions,
-	.nr_parts	= ARRAY_SIZE(zylonite_nand_partitions),
+	.parts[0]	= zylonite_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(zylonite_nand_partitions),
 };

 static void __init zylonite_init_nand(void)
diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index 7e5a28f..56015bd 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -4,6 +4,7 @@
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>

+#define NUM_CHIP_SELECT		(2)
 struct pxa3xx_nand_platform_data {

 	/* the data flash bus is shared between the Static Memory
@@ -15,8 +16,8 @@ struct pxa3xx_nand_platform_data {
 	/* allow platform code to keep OBM/bootloader defined NFC config */
 	int	keep_config;

-	const struct mtd_partition		*parts;
-	unsigned int				nr_parts;
+	const struct mtd_partition		*parts[NUM_CHIP_SELECT];
+	unsigned int				nr_parts[NUM_CHIP_SELECT];

 	const struct pxa3xx_nand_flash * 	flash;
 	size_t					num_flash;
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 8628fc1..215677f 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -51,11 +51,9 @@
 #define NDCR_DWIDTH_M		(0x1 << 26)
 #define NDCR_PAGE_SZ		(0x1 << 24)
 #define NDCR_NCSX		(0x1 << 23)
-#define NDCR_STOP_ON_UNCOR	(0x1 << 22)
 #define NDCR_ND_MODE		(0x3 << 21)
-#define NDCR_NAND_MODE   	(0x0)
 #define NDCR_CLR_PG_CNT		(0x1 << 20)
-#define NDCR_CLR_ECC		(0x1 << 19)
+#define NDCR_STOP_ON_UNCOR	(0x1 << 19)
 #define NDCR_RD_ID_CNT_MASK	(0x7 << 16)
 #define NDCR_RD_ID_CNT(x)	(((x) << 16) & NDCR_RD_ID_CNT_MASK)

@@ -98,6 +96,8 @@

 #define nand_readl(info, off)		\
 	__raw_readl((info)->mmio_base + (off))
+#define get_mtd_by_info(info)		\
+	(struct mtd_info *)((void *)info - sizeof(struct mtd_info))

 /* error code and state */
 enum {
@@ -158,62 +158,63 @@ struct pxa3xx_nand_flash {

 struct pxa3xx_nand_info {
 	struct nand_chip	nand_chip;
+	/* page size of attached chip */
+	uint16_t		page_size;
+	uint8_t			chip_select;
+	uint8_t			use_ecc;

-	struct nand_hw_control	controller;
-	struct platform_device	 *pdev;
+	/* calculated from pxa3xx_nand_flash data */
+	uint8_t			col_addr_cycles;
+	uint8_t			row_addr_cycles;
+	uint8_t			read_id_bytes;
+
+	/* cached register value */
+	uint32_t		reg_ndcr;
+	uint32_t		ndtr0cs0;
+	uint32_t		ndtr1cs0;
+
+	void			*nand_data;
+};

+struct pxa3xx_nand {
 	struct clk		*clk;
 	void __iomem		*mmio_base;
 	unsigned long		mmio_phys;
+	struct nand_hw_control	controller;
+	struct completion 	cmd_complete;
+	struct platform_device	 *pdev;

-	unsigned int 		buf_start;
-	unsigned int		buf_count;
-
-	struct mtd_info         *mtd;
 	/* DMA information */
 	int			drcmr_dat;
 	int			drcmr_cmd;
-
-	unsigned char		*data_buff;
-	unsigned char		*oob_buff;
-	dma_addr_t 		data_buff_phys;
-	size_t			data_buff_size;
 	int 			data_dma_ch;
-	struct pxa_dma_desc	*data_desc;
+	dma_addr_t 		data_buff_phys;
 	dma_addr_t 		data_desc_addr;
+	struct pxa_dma_desc	*data_desc;

-	uint32_t		reg_ndcr;
-
-	/* saved column/page_addr during CMD_SEQIN */
-	int			seqin_column;
-	int			seqin_page_addr;
+	struct pxa3xx_nand_info *info[NUM_CHIP_SELECT];
+	uint32_t		command;
+	uint16_t		data_size;	/* data size in FIFO */
+	uint16_t		oob_size;
+	uint32_t		bad_count;
+	unsigned char		*dma_buff;
+	unsigned char		*data_buff;
+	unsigned char		*oob_buff;
+	uint32_t		buf_start;
+	uint32_t		buf_count;
+	uint8_t			total_cmds;

 	/* relate to the command */
+	uint8_t			chip_select;
 	unsigned int		state;
-
 	int			use_ecc;	/* use HW ECC ? */
 	int			use_dma;	/* use DMA ? */
-
-	unsigned int		page_size;	/* page size of attached chip */
-	unsigned int		data_size;	/* data size in FIFO */
 	int 			retcode;
-	struct completion 	cmd_complete;

 	/* generated NDCBx register values */
 	uint32_t		ndcb0;
 	uint32_t		ndcb1;
 	uint32_t		ndcb2;
-
-	/* timing calcuted from setting */
-	uint32_t		ndtr0cs0;
-	uint32_t		ndtr1cs0;
-
-	/* calculated from pxa3xx_nand_flash data */
-	size_t		oob_size;
-	size_t		read_id_bytes;
-
-	unsigned int	col_addr_cycles;
-	unsigned int	row_addr_cycles;
 };

 static int use_dma = 1;
@@ -248,6 +249,7 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
 	{ 		0,	0,   0,    0,  0,  0,    0, &timing[0], },
 	{ "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, &timing[1], },
 	{ "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, &timing[1], },
+	{ "1GiB 8-bit",    0xd3ec, 128, 2048,  8,  8, 4096, &timing[1], },
 	{ "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, &timing[1], },
 	{ "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, &timing[2], },
 	{ "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, &timing[2], },
@@ -256,7 +258,7 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
 	{ "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, &timing[3], },
 };

-static const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
+static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};

 #define NDTR0_tCH(c)	(min((c), 7) << 19)
 #define NDTR0_tCS(c)	(min((c), 7) << 16)
@@ -274,9 +276,11 @@ static const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
 				   const struct pxa3xx_nand_timing *t)
 {
-	unsigned long nand_clk = clk_get_rate(info->clk);
+	struct pxa3xx_nand *nand = info->nand_data;
+	unsigned long nand_clk;
 	uint32_t ndtr0, ndtr1;

+	nand_clk = clk_get_rate(nand->clk);
 	ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
 		NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
 		NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
@@ -290,25 +294,26 @@ static void pxa3xx_nand_set_timing(struct
pxa3xx_nand_info *info,

 	info->ndtr0cs0 = ndtr0;
 	info->ndtr1cs0 = ndtr1;
-	nand_writel(info, NDTR0CS0, ndtr0);
-	nand_writel(info, NDTR1CS0, ndtr1);
+	nand_writel(nand, NDTR0CS0, ndtr0);
+	nand_writel(nand, NDTR1CS0, ndtr1);
 }

 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 {
+	struct pxa3xx_nand *nand = info->nand_data;
 	int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;

-	info->data_size = info->page_size;
+	nand->data_size = info->page_size;
 	if (!oob_enable) {
-		info->oob_size = 0;
+		nand->oob_size = 0;
 		return;
 	}
 	switch (info->page_size) {
 		case 2048:
-			info->oob_size = (info->use_ecc) ? 40 : 64;
+			nand->oob_size = (nand->use_ecc) ? 40 : 64;
 			break;
 		case 512:
-			info->oob_size = (info->use_ecc) ? 8 : 16;
+			nand->oob_size = (nand->use_ecc) ? 8 : 16;
 			break;
 	}
 }
@@ -319,22 +324,24 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
  * We enable all the interrupt at the same time, and
  * let pxa3xx_nand_irq to handle all logic.
  */
-static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
+static void pxa3xx_nand_start(struct pxa3xx_nand *nand)
 {
+	struct pxa3xx_nand_info *info;
 	uint32_t ndcr;

+	info = nand->info[nand->chip_select];
 	ndcr = info->reg_ndcr;
-	ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
-	ndcr |= info->use_dma ? NDCR_DMA_EN : NDCR_STOP_ON_UNCOR;
+	ndcr |= nand->use_ecc ? NDCR_ECC_EN : 0;
+	ndcr |= nand->use_dma ? NDCR_DMA_EN : NDCR_STOP_ON_UNCOR;
 	ndcr |= NDCR_ND_RUN;

 	/* clear status bits and run */
-	nand_writel(info, NDCR, 0);
-	nand_writel(info, NDSR, NDSR_MASK);
-	nand_writel(info, NDCR, ndcr);
+	nand_writel(nand, NDCR, 0);
+	nand_writel(nand, NDSR, NDSR_MASK);
+	nand_writel(nand, NDCR, ndcr);
 }

-static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
+static void pxa3xx_nand_stop(struct pxa3xx_nand *nand)
 {
 	uint32_t ndcr;
 	int timeout = NAND_STOP_DELAY;
@@ -342,146 +349,149 @@ static void pxa3xx_nand_stop(struct
pxa3xx_nand_info *info)
 	/* wait RUN bit in NDCR become 0 */
 	do {
 		/* clear status bits */
-		nand_writel(info, NDSR, NDSR_MASK);
-		ndcr = nand_readl(info, NDCR);
+		nand_writel(nand, NDSR, NDSR_MASK);
+		ndcr = nand_readl(nand, NDCR);
 		udelay(1);
 	} while ((ndcr & NDCR_ND_RUN) && (timeout -- > 0));

 	if (timeout <= 0) {
 		ndcr &= ~(NDCR_ND_RUN);
-		nand_writel(info, NDCR, ndcr);
+		nand_writel(nand, NDCR, ndcr);
 	}
 }

-static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
+static void enable_int(struct pxa3xx_nand *nand, uint32_t int_mask)
 {
 	uint32_t ndcr;

-	ndcr = nand_readl(info, NDCR);
-	nand_writel(info, NDCR, ndcr & ~int_mask);
+	ndcr = nand_readl(nand, NDCR);
+	nand_writel(nand, NDCR, ndcr & ~int_mask);
 }

-static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
+static void disable_int(struct pxa3xx_nand *nand, uint32_t int_mask)
 {
 	uint32_t ndcr;

-	ndcr = nand_readl(info, NDCR);
-	nand_writel(info, NDCR, ndcr | int_mask);
+	ndcr = nand_readl(nand, NDCR);
+	nand_writel(nand, NDCR, ndcr | int_mask);
 }

-static void handle_data_pio(struct pxa3xx_nand_info *info)
+static void handle_data_pio(struct pxa3xx_nand *nand)
 {
-	if (info->state & STATE_IS_WRITE) {
-		__raw_writesl(info->mmio_base + NDDB, info->data_buff,
-				DIV_ROUND_UP(info->data_size, 4));
-		if (info->oob_size > 0)
-			__raw_writesl(info->mmio_base + NDDB, info->oob_buff,
-					DIV_ROUND_UP(info->oob_size, 4));
+	if (nand->state & STATE_IS_WRITE) {
+		__raw_writesl(nand->mmio_base + NDDB, nand->data_buff,
+				DIV_ROUND_UP(nand->data_size, 4));
+		if (nand->oob_size > 0)
+			__raw_writesl(nand->mmio_base + NDDB, nand->oob_buff,
+					DIV_ROUND_UP(nand->oob_size, 4));

 	}
 	else {
-		__raw_readsl(info->mmio_base + NDDB, info->data_buff,
-				DIV_ROUND_UP(info->data_size, 4));
-		if (info->oob_size > 0)
-			__raw_readsl(info->mmio_base + NDDB, info->oob_buff,
-					DIV_ROUND_UP(info->oob_size, 4));
+		__raw_readsl(nand->mmio_base + NDDB, nand->data_buff,
+				DIV_ROUND_UP(nand->data_size, 4));
+		if (nand->oob_size > 0)
+			__raw_readsl(nand->mmio_base + NDDB, nand->oob_buff,
+					DIV_ROUND_UP(nand->oob_size, 4));
 	}
 }

-static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
+static void start_data_dma(struct pxa3xx_nand *nand, int dir_out)
 {
-	struct pxa_dma_desc *desc = info->data_desc;
-	int dma_len = ALIGN(info->data_size + info->oob_size, 32);
+	struct pxa_dma_desc *desc = nand->data_desc;
+	int dma_len = ALIGN(nand->data_size + nand->oob_size, 32);

 	desc->ddadr = DDADR_STOP;
 	desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;

 	if (dir_out) {
-		desc->dsadr = info->data_buff_phys;
-		desc->dtadr = info->mmio_phys + NDDB;
+		desc->dsadr = nand->data_buff_phys;
+		desc->dtadr = nand->mmio_phys + NDDB;
 		desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
 	} else {
-		desc->dtadr = info->data_buff_phys;
-		desc->dsadr = info->mmio_phys + NDDB;
+		desc->dtadr = nand->data_buff_phys;
+		desc->dsadr = nand->mmio_phys + NDDB;
 		desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
 	}

-	DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
-	DDADR(info->data_dma_ch) = info->data_desc_addr;
-	DCSR(info->data_dma_ch) |= DCSR_RUN;
+	DRCMR(nand->drcmr_dat) = DRCMR_MAPVLD | nand->data_dma_ch;
+	DDADR(nand->data_dma_ch) = nand->data_desc_addr;
+	DCSR(nand->data_dma_ch) |= DCSR_RUN;
 }

 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
 {
-	struct pxa3xx_nand_info *info = data;
+	struct pxa3xx_nand *nand = data;
 	uint32_t dcsr;

 	dcsr = DCSR(channel);
 	DCSR(channel) = dcsr;

 	if (dcsr & DCSR_BUSERR) {
-		info->retcode = ERR_DMABUSERR;
+		nand->retcode = ERR_DMABUSERR;
 	}

-	enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
+	enable_int(nand, NDCR_INT_MASK);
+	nand_writel(nand, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
 }

 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 {
-	struct pxa3xx_nand_info *info = devid;
-	unsigned int status, is_completed = 0;
+	struct pxa3xx_nand *nand = devid;
+	struct pxa3xx_nand_info *info;
+	unsigned int status, is_completed = 0, cs;
+	unsigned int ready, cmd_done, page_done, badblock_detect;

-	status = nand_readl(info, NDSR);
+	cs		= nand->chip_select;
+	ready           = (cs) ? NDSR_RDY : NDSR_FLASH_RDY;
+	cmd_done        = (cs) ? NDSR_CS1_CMDD : NDSR_CS0_CMDD;
+	page_done       = (cs) ? NDSR_CS1_PAGED : NDSR_CS0_PAGED;
+	badblock_detect = (cs) ? NDSR_CS1_BBD : NDSR_CS0_BBD;
+	info            = nand->info[cs];

+	status = nand_readl(nand, NDSR);
 	if (status & NDSR_DBERR)
-		info->retcode = ERR_DBERR;
+		nand->retcode = ERR_DBERR;
 	if (status & NDSR_SBERR)
-		info->retcode = ERR_SBERR;
+		nand->retcode = ERR_SBERR;
 	if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {

-		info->state |= STATE_DATA_PROCESSING;
+		nand->state |= STATE_DATA_PROCESSING;
 		/* whether use dma to transfer data */
-		if (info->use_dma) {
-			disable_int(info, NDSR_WRDREQ);
-			start_data_dma(info, 0);
+		if (nand->use_dma) {
+			disable_int(nand, NDCR_INT_MASK);
+			start_data_dma(nand, nand->state & STATE_IS_WRITE);
 			goto NORMAL_IRQ_EXIT;
 		} else
-			handle_data_pio(info);
+			handle_data_pio(nand);

-		info->state |= STATE_DATA_DONE;
+		nand->state |= STATE_DATA_DONE;
 	}
-	if (status & NDSR_CS0_CMDD) {
-		info->state |= STATE_CMD_DONE;
+	if (status & cmd_done) {
+		nand->state |= STATE_CMD_DONE;
 		is_completed = 1;
 	}
-	if (status & NDSR_FLASH_RDY)
-		info->state |= STATE_READY;
-	if (status & NDSR_CS0_PAGED)
-		info->state |= STATE_PAGE_DONE;
+	if (status & ready)
+		nand->state |= STATE_READY;
+	if (status & page_done)
+		nand->state |= STATE_PAGE_DONE;

 	if (status & NDSR_WRCMDREQ) {
-		nand_writel(info, NDSR, NDSR_WRCMDREQ);
+		nand_writel(nand, NDSR, NDSR_WRCMDREQ);
 		status &= ~NDSR_WRCMDREQ;
-		info->state |= STATE_CMD_WAIT_DONE;
-		nand_writel(info, NDCB0, info->ndcb0);
-		nand_writel(info, NDCB0, info->ndcb1);
-		nand_writel(info, NDCB0, info->ndcb2);
+		nand->state |= STATE_CMD_WAIT_DONE;
+		nand_writel(nand, NDCB0, nand->ndcb0);
+		nand_writel(nand, NDCB0, nand->ndcb1);
+		nand_writel(nand, NDCB0, nand->ndcb2);
 	}

 	/* clear NDSR to let the controller exit the IRQ */
-	nand_writel(info, NDSR, status);
+	nand_writel(nand, NDSR, status);
 	if (is_completed)
-		complete(&info->cmd_complete);
+		complete(&nand->cmd_complete);
 NORMAL_IRQ_EXIT:
 	return IRQ_HANDLED;
 }

-static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
-{
-	struct pxa3xx_nand_info *info = mtd->priv;
-	return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
-}
-
 static inline int is_buf_blank(uint8_t *buf, size_t len)
 {
 	for (; len > 0; len--)
@@ -490,40 +500,48 @@ static inline int is_buf_blank(uint8_t *buf, size_t len)
 	return 1;
 }

-static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
+static int prepare_command_pool(struct pxa3xx_nand *nand, int command,
 		uint16_t column, int page_addr)
 {
 	uint16_t cmd;
 	int addr_cycle, exec_cmd, ndcb0;
-	struct mtd_info *mtd = info->mtd;
+	struct mtd_info *mtd;
+	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];

-	ndcb0 = 0;
+	mtd = get_mtd_by_info(info);
+	ndcb0 = (nand->chip_select) ? NDCB0_CSEL : 0;;
 	addr_cycle = 0;
 	exec_cmd = 1;

 	/* reset data and oob column point to handle data */
-	info->buf_start		= 0;
-	info->buf_count		= 0;
-	info->oob_size		= 0;
-	info->use_ecc		= 0;
+	nand->buf_start		= 0;
+	nand->buf_count		= 0;
+	nand->ndcb0		= ndcb0;
+	nand->data_size		= 0;
+	nand->oob_size		= 0;
+	nand->use_ecc		= 0;
+	nand->use_dma		= 0;
+	nand->state		= 0;
+	nand->command		= command;

 	switch (command) {
 	case NAND_CMD_READ0:
 	case NAND_CMD_PAGEPROG:
-		info->use_ecc = 1;
+		nand->use_ecc = info->use_ecc;
 	case NAND_CMD_READOOB:
 		pxa3xx_set_datasize(info);
+		nand->oob_buff = nand->data_buff + nand->data_size;
+		nand->use_dma = use_dma;
 		break;
 	case NAND_CMD_SEQIN:
 		exec_cmd = 0;
 		break;
 	default:
-		info->ndcb1 = 0;
-		info->ndcb2 = 0;
+		nand->ndcb1 = 0;
+		nand->ndcb2 = 0;
 		break;
 	}

-	info->ndcb0 = ndcb0;
 	addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
 			+ info->col_addr_cycles);

@@ -533,16 +551,16 @@ static int prepare_command_pool(struct
pxa3xx_nand_info *info, int command,

 		cmd  = cmdset.read1;
 		if (command == NAND_CMD_READOOB)
-			info->buf_start = mtd->writesize + column;
+			nand->buf_start = mtd->writesize + column;
 		else
-			info->buf_start = column;
+			nand->buf_start = column;

 		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
-			info->ndcb0 |= NDCB0_CMD_TYPE(0)
+			nand->ndcb0 |= NDCB0_CMD_TYPE(0)
 					| addr_cycle
 					| (cmd & NDCB0_CMD1_MASK);
 		else
-			info->ndcb0 |= NDCB0_CMD_TYPE(0)
+			nand->ndcb0 |= NDCB0_CMD_TYPE(0)
 					| NDCB0_DBC
 					| addr_cycle
 					| cmd;
@@ -550,35 +568,35 @@ static int prepare_command_pool(struct
pxa3xx_nand_info *info, int command,
 	case NAND_CMD_SEQIN:
 		/* small page addr setting */
 		if (unlikely(info->page_size < PAGE_CHUNK_SIZE)) {
-			info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
+			nand->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
 					| (column & 0xFF);

-			info->ndcb2 = 0;
+			nand->ndcb2 = 0;
 		}
 		else {
-			info->ndcb1 = ((page_addr & 0xFFFF) << 16)
+			nand->ndcb1 = ((page_addr & 0xFFFF) << 16)
 					| (column & 0xFFFF);

 			if (page_addr & 0xFF0000)
-				info->ndcb2 = (page_addr & 0xFF0000) >> 16;
+				nand->ndcb2 = (page_addr & 0xFF0000) >> 16;
 			else
-				info->ndcb2 = 0;
+				nand->ndcb2 = 0;
 		}

-		info->buf_count = mtd->writesize + mtd->oobsize;
-		memset(info->data_buff, 0xFF, info->buf_count);
+		nand->buf_count = mtd->writesize + mtd->oobsize;
+		memset(nand->data_buff, 0xFF, nand->buf_count);

 		break;

 	case NAND_CMD_PAGEPROG:
-		if (is_buf_blank(info->data_buff, (mtd->writesize + mtd->oobsize))) {
+		if (is_buf_blank(nand->data_buff, (mtd->writesize + mtd->oobsize))) {
 			exec_cmd = 0;
 			break;
 		}

 		cmd = cmdset.program;
-		info->state |= STATE_IS_WRITE;
-		info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
+		nand->state |= STATE_IS_WRITE;
+		nand->ndcb0 |= NDCB0_CMD_TYPE(0x1)
 				| NDCB0_AUTO_RS
 				| NDCB0_ST_ROW_EN
 				| NDCB0_DBC
@@ -588,38 +606,38 @@ static int prepare_command_pool(struct
pxa3xx_nand_info *info, int command,

 	case NAND_CMD_READID:
 		cmd = cmdset.read_id;
-		info->buf_count = info->read_id_bytes;
-		info->ndcb0 |= NDCB0_CMD_TYPE(3)
+		nand->buf_count = info->read_id_bytes;
+		nand->ndcb0 |= NDCB0_CMD_TYPE(3)
 				| NDCB0_ADDR_CYC(1)
 				| cmd;

-		info->data_size = 8;
+		nand->data_size = 8;
 		break;

 	case NAND_CMD_STATUS:
 		cmd = cmdset.read_status;
-		info->buf_count = 1;
-		info->ndcb0 |= NDCB0_CMD_TYPE(4)
+		nand->buf_count = 1;
+		nand->ndcb0 |= NDCB0_CMD_TYPE(4)
 				| NDCB0_ADDR_CYC(1)
 				| cmd;

-		info->data_size = 8;
+		nand->data_size = 8;
 		break;

 	case NAND_CMD_ERASE1:
 		cmd = cmdset.erase;
-		info->ndcb0 |= NDCB0_CMD_TYPE(2)
+		nand->ndcb0 |= NDCB0_CMD_TYPE(2)
 				| NDCB0_AUTO_RS
 				| NDCB0_ADDR_CYC(3)
 				| NDCB0_DBC
 				| cmd;
-		info->ndcb1 = page_addr;
-		info->ndcb2 = 0;
+		nand->ndcb1 = page_addr;
+		nand->ndcb2 = 0;

 		break;
 	case NAND_CMD_RESET:
 		cmd = cmdset.reset;
-		info->ndcb0 |= NDCB0_CMD_TYPE(5)
+		nand->ndcb0 |= NDCB0_CMD_TYPE(5)
 				| cmd;

 		break;
@@ -630,7 +648,7 @@ static int prepare_command_pool(struct
pxa3xx_nand_info *info, int command,

 	default:
 		exec_cmd = 0;
-		printk(KERN_ERR "pxa3xx-nand: non-supported command %x\n", command);
+		dev_err(&nand->pdev->dev, "non-supported command %x\n", command);
 		break;
 	}

@@ -641,6 +659,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 				int column, int page_addr)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;
 	int ret, exec_cmd;

 	/* if this is a x16 device ,then convert the input
@@ -650,32 +669,40 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 	if (info->reg_ndcr & NDCR_DWIDTH_M)
 		column /= 2;

-	exec_cmd = prepare_command_pool(info, command, column, page_addr);
+	/* reset timing */
+	if (nand->chip_select != info->chip_select) {
+		nand->chip_select = info->chip_select;
+		nand_writel(nand, NDTR0CS0, info->ndtr0cs0);
+		nand_writel(nand, NDTR1CS0, info->ndtr1cs0);
+	}
+
+	exec_cmd = prepare_command_pool(nand, command, column, page_addr);
 	if (exec_cmd) {
-		init_completion(&info->cmd_complete);
-		info->state |= STATE_CMD_PREPARED;
-		pxa3xx_nand_start(info);
+		init_completion(&nand->cmd_complete);
+		nand->state |= STATE_CMD_PREPARED;
+		pxa3xx_nand_start(nand);

-		ret = wait_for_completion_timeout(&info->cmd_complete,
+		ret = wait_for_completion_timeout(&nand->cmd_complete,
 				CHIP_DELAY_TIMEOUT);
 		if (!ret) {
-			printk(KERN_ERR "Wait time out!!!\n");
+			dev_err(&nand->pdev->dev, "Wait time out!!!\n");
 		}
 		/* Stop State Machine for next command cycle */
-		pxa3xx_nand_stop(info);
-		disable_int(info, NDCR_INT_MASK);
-		info->state &= ~STATE_CMD_PREPARED;
+		pxa3xx_nand_stop(nand);
+		disable_int(nand, NDCR_INT_MASK);
+		nand->state &= ~STATE_CMD_PREPARED;
 	}
 }

 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;
 	char retval = 0xFF;

-	if (info->buf_start < info->buf_count)
+	if (nand->buf_start < nand->buf_count)
 		/* Has just send a new command? */
-		retval = info->data_buff[info->buf_start++];
+		retval = nand->data_buff[nand->buf_start++];

 	return retval;
 }
@@ -683,11 +710,12 @@ static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;
 	u16 retval = 0xFFFF;

-	if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
-		retval = *((u16 *)(info->data_buff+info->buf_start));
-		info->buf_start += 2;
+	if (!(nand->buf_start & 0x01) && nand->buf_start < nand->buf_count) {
+		retval = *((u16 *)(nand->data_buff+nand->buf_start));
+		nand->buf_start += 2;
 	}
 	return retval;
 }
@@ -695,20 +723,22 @@ static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
-	int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
+	struct pxa3xx_nand *nand = info->nand_data;
+	int real_len = min_t(size_t, len, nand->buf_count - nand->buf_start);

-	memcpy(buf, info->data_buff + info->buf_start, real_len);
-	info->buf_start += real_len;
+	memcpy(buf, nand->data_buff + nand->buf_start, real_len);
+	nand->buf_start += real_len;
 }

 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 		const uint8_t *buf, int len)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
-	int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
+	struct pxa3xx_nand *nand = info->nand_data;
+	int real_len = min_t(size_t, len, nand->buf_count - nand->buf_start);

-	memcpy(info->data_buff + info->buf_start, buf, real_len);
-	info->buf_start += real_len;
+	memcpy(nand->data_buff + nand->buf_start, buf, real_len);
+	nand->buf_start += real_len;
 }

 static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
@@ -725,10 +755,11 @@ static void pxa3xx_nand_select_chip(struct
mtd_info *mtd, int chip)
 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;

 	/* pxa3xx_nand_send_command has waited for command complete */
 	if (this->state == FL_WRITING || this->state == FL_ERASING) {
-		if (info->retcode == ERR_NONE)
+		if (nand->retcode == ERR_NONE)
 			return 0;
 		else {
 			/*
@@ -742,47 +773,16 @@ static int pxa3xx_nand_waitfunc(struct mtd_info
*mtd, struct nand_chip *this)
 	return 0;
 }

-static void pxa3xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
-{
-	return;
-}
-
-static int pxa3xx_nand_ecc_calculate(struct mtd_info *mtd,
-		const uint8_t *dat, uint8_t *ecc_code)
-{
-	return 0;
-}
-
-static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
-		uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
-{
-	struct pxa3xx_nand_info *info = mtd->priv;
-	/*
-	 * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
-	 * consider it as a ecc error which will tell the caller the
-	 * read fail We have distinguish all the errors, but the
-	 * nand_read_ecc only check this function return value
-	 *
-	 * Corrected (single-bit) errors must also be noted.
-	 */
-	if (info->retcode == ERR_SBERR)
-		return 1;
-	else if (info->retcode != ERR_NONE)
-		return -1;
-
-	return 0;
-}
-
 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
 				    const struct pxa3xx_nand_flash *f)
 {
-	struct platform_device *pdev = info->pdev;
+	struct pxa3xx_nand *nand = info->nand_data;
+	struct platform_device *pdev = nand->pdev;
 	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 	uint32_t ndcr = 0;

 	/* calculate flash information */
 	info->page_size = f->page_size;
-	info->oob_size = (f->page_size == 2048) ? 64 : 16;
 	info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;

 	/* calculate addressing information */
@@ -804,19 +804,24 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	ndcr |= NDCR_SPARE_EN; /* enable spare by default */

 	info->reg_ndcr = ndcr;
+	info->use_ecc = 1;

 	pxa3xx_nand_set_timing(info, f->timing);
 	return 0;
 }

-static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
+static int pxa3xx_nand_detect_config(struct pxa3xx_nand *nand)
 {
-	uint32_t ndcr = nand_readl(info, NDCR);
+	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
+	uint32_t ndcr = nand_readl(nand, NDCR);

-	info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
+	if (nand->chip_select > 0) {
+		printk(KERN_ERR "We could not detect configure if two cs is supported!!\n");
+		BUG();
+	}
 	info->reg_ndcr = ndcr & ~(NDCR_INT_MASK | NDCR_ECC_EN | NDCR_DMA_EN
| NDCR_ND_RUN);
-	info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
-	info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
+	info->ndtr0cs0 = nand_readl(nand, NDTR0CS0);
+	info->ndtr1cs0 = nand_readl(nand, NDTR1CS0);

 	return 0;
 }
@@ -826,62 +831,40 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand_info *info)
  * data buffer and the DMA descriptor
  */
 #define MAX_BUFF_SIZE	PAGE_SIZE
-
-static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
+static void free_cs_resource(struct pxa3xx_nand_info *info, int cs)
 {
-	struct platform_device *pdev = info->pdev;
-	int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
-
-	if (use_dma == 0) {
-		info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
-		if (info->data_buff == NULL)
-			return -ENOMEM;
-		return 0;
-	}
-
-	info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
-				&info->data_buff_phys, GFP_KERNEL);
-	if (info->data_buff == NULL) {
-		dev_err(&pdev->dev, "failed to allocate dma buffer\n");
-		return -ENOMEM;
-	}
-
-	info->data_buff_size = MAX_BUFF_SIZE;
-	info->data_desc = (void *)info->data_buff + data_desc_offset;
-	info->data_desc_addr = info->data_buff_phys + data_desc_offset;
+	struct pxa3xx_nand *nand;
+	struct mtd_info *mtd;

-	info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
-				pxa3xx_nand_data_dma_irq, info);
-	if (info->data_dma_ch < 0) {
-		dev_err(&pdev->dev, "failed to request data dma\n");
-		dma_free_coherent(&pdev->dev, info->data_buff_size,
-				info->data_buff, info->data_buff_phys);
-		return info->data_dma_ch;
-	}
+	if (!info)
+		return;

-	return 0;
+	nand = info->nand_data;
+	mtd = get_mtd_by_info(info);
+	kfree(mtd);
+	nand->info[cs] = NULL;
 }

 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 		struct nand_chip *chip, uint8_t *buf, int page)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;

 	chip->read_buf(mtd, buf, mtd->writesize);
 	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);

-	if (info->retcode == ERR_SBERR) {
-		switch (info->use_ecc) {
+	if (nand->retcode == ERR_SBERR) {
+		switch (nand->use_ecc) {
 			case 1:
-				mtd->ecc_stats.corrected ++;
+				mtd->ecc_stats.corrected++;
 				break;

 			case 0:
 			default:
 				break;
 		}
-	}
-	else if (info->retcode == ERR_DBERR) {
+	} else if (nand->retcode == ERR_DBERR) {
 		int buf_blank;

 		buf_blank = is_buf_blank(buf, mtd->writesize);
@@ -901,20 +884,19 @@ static void pxa3xx_nand_write_page_hwecc(struct
mtd_info *mtd,

 static void pxa3xx_nand_erase_cmd(struct mtd_info *mtd, int page)
 {
-	struct nand_chip *chip = mtd->priv;
 	/* Send commands to erase a block */
-	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+	pxa3xx_nand_cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
 }

-static int __devinit pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
+static int __devinit pxa3xx_nand_sensing(struct pxa3xx_nand *nand)
 {
-	struct mtd_info *mtd = info->mtd;
-	struct nand_chip *chip = mtd->priv;
+	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
+	struct mtd_info *mtd = get_mtd_by_info(info);

 	/* use the common timing to make a try */
 	pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
-	chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
-	if (info->state & STATE_READY)
+	pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
+	if (nand->state & STATE_READY)
 		return 1;
 	else
 		return 0;
@@ -923,7 +905,8 @@ static int __devinit pxa3xx_nand_sensing(struct
pxa3xx_nand_info *info)
 static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
-	struct platform_device *pdev = info->pdev;
+	struct pxa3xx_nand *nand = info->nand_data;
+	struct platform_device *pdev = nand->pdev;
 	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 	struct nand_flash_dev pxa3xx_flash_ids[2] = {{NULL,}, {NULL,}};
 	const struct pxa3xx_nand_flash *f = NULL;
@@ -933,28 +916,23 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 	int i, ret;

 	if (pdata->keep_config) {
-		if (pxa3xx_nand_detect_config(info) == 0)
+		if (pxa3xx_nand_detect_config(nand) == 0)
 			goto KEEP_CONFIG;
 	}

-	ret = pxa3xx_nand_sensing(info);
+	ret = pxa3xx_nand_sensing(nand);
 	if (!ret) {
-		kfree(mtd);
-		info->mtd = NULL;
-		printk(KERN_INFO "There is no nand chip on cs 0!\n");
-
+		free_cs_resource(info, nand->chip_select);
 		return -EINVAL;
 	}

 	chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
-	id = *((uint16_t *)(info->data_buff));
+	id = *((uint16_t *)(nand->data_buff));
 	if (id != 0)
-		printk(KERN_INFO "Detect a flash id %x\n", id);
+		dev_info(&nand->pdev->dev, "Detect a flash id %x\n", id);
 	else {
-		kfree(mtd);
-		info->mtd = NULL;
-		printk(KERN_WARNING "Read out ID 0, potential timing set wrong!!\n");
-
+		dev_warn(&nand->pdev->dev, "Read out ID 0, potential timing set wrong!!\n");
+		free_cs_resource(info, nand->chip_select);
 		return -EINVAL;
 	}

@@ -970,10 +948,8 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd)
 	}

 	if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
-		kfree(mtd);
-		info->mtd = NULL;
-		printk(KERN_ERR "ERROR!! flash not defined!!!\n");
-
+		dev_err(&nand->pdev->dev, "ERROR!! flash not defined!!!\n");
+		free_cs_resource(info, nand->chip_select);
 		return -EINVAL;
 	}

@@ -990,15 +966,15 @@ KEEP_CONFIG:
 		return -ENODEV;
 	/* calculate addressing information */
 	info->col_addr_cycles = (mtd->writesize >= 2048) ? 2 : 1;
-	info->oob_buff = info->data_buff + mtd->writesize;
 	if ((mtd->size >> chip->page_shift) > 65536)
 		info->row_addr_cycles = 3;
 	else
 		info->row_addr_cycles = 2;
-	mtd->name = mtd_names[0];
+	info->page_size = mtd->writesize;
+	mtd->name = mtd_names[nand->chip_select];
 	chip->ecc.mode = NAND_ECC_HW;
 	chip->ecc.size = mtd->writesize;
-	chip->options = (info->reg_ndcr & NDCR_DWIDTH_M) ? NAND_BUSWIDTH_16: 0;
+	chip->options |= (info->reg_ndcr & NDCR_DWIDTH_M) ? NAND_BUSWIDTH_16: 0;
 	chip->options |= NAND_NO_READRDY;
 	chip->options |= NAND_USE_FLASH_BBT;

@@ -1010,49 +986,25 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 	struct pxa3xx_nand_info *info;
 	struct nand_chip *chip;
 	struct mtd_info *mtd;
+	struct pxa3xx_nand *nand;
 	struct resource *r;
-	int ret, irq;
+	int ret, irq, cs;
+	int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);

-	mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
-			GFP_KERNEL);
-	if (!mtd) {
+	nand = kzalloc(sizeof(struct pxa3xx_nand), GFP_KERNEL);
+	if (!nand) {
 		dev_err(&pdev->dev, "failed to allocate memory\n");
 		return -ENOMEM;
 	}

-	info = (struct pxa3xx_nand_info *)(&mtd[1]);
-	chip = (struct nand_chip *)(&mtd[1]);
-	info->pdev = pdev;
-	info->mtd = mtd;
-	mtd->priv = info;
-	mtd->owner = THIS_MODULE;
-
-	chip->ecc.read_page	= pxa3xx_nand_read_page_hwecc;
-	chip->ecc.write_page	= pxa3xx_nand_write_page_hwecc;
-	chip->ecc.hwctl		= pxa3xx_nand_ecc_hwctl;
-	chip->ecc.calculate	= pxa3xx_nand_ecc_calculate;
-	chip->ecc.correct	= pxa3xx_nand_ecc_correct;
-	chip->controller        = &info->controller;
-	chip->waitfunc		= pxa3xx_nand_waitfunc;
-	chip->select_chip	= pxa3xx_nand_select_chip;
-	chip->dev_ready		= pxa3xx_nand_dev_ready;
-	chip->cmdfunc		= pxa3xx_nand_cmdfunc;
-	chip->read_word		= pxa3xx_nand_read_word;
-	chip->read_byte		= pxa3xx_nand_read_byte;
-	chip->read_buf		= pxa3xx_nand_read_buf;
-	chip->write_buf		= pxa3xx_nand_write_buf;
-	chip->verify_buf	= pxa3xx_nand_verify_buf;
-	chip->erase_cmd		= pxa3xx_nand_erase_cmd;
-
-	spin_lock_init(&chip->controller->lock);
-	init_waitqueue_head(&chip->controller->wq);
-	info->clk = clk_get(&pdev->dev, NULL);
-	if (IS_ERR(info->clk)) {
+	nand->pdev = pdev;
+	nand->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(nand->clk)) {
 		dev_err(&pdev->dev, "failed to get nand clock\n");
-		ret = PTR_ERR(info->clk);
-		goto fail_free_mtd;
+		ret = PTR_ERR(nand->clk);
+		goto fail_alloc;
 	}
-	clk_enable(info->clk);
+	clk_enable(nand->clk);

 	r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 	if (r == NULL) {
@@ -1060,7 +1012,7 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		ret = -ENXIO;
 		goto fail_put_clk;
 	}
-	info->drcmr_dat = r->start;
+	nand->drcmr_dat = r->start;

 	r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 	if (r == NULL) {
@@ -1068,14 +1020,7 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		ret = -ENXIO;
 		goto fail_put_clk;
 	}
-	info->drcmr_cmd = r->start;
-
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
-		dev_err(&pdev->dev, "no IRQ resource defined\n");
-		ret = -ENXIO;
-		goto fail_put_clk;
-	}
+	nand->drcmr_cmd = r->start;

 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (r == NULL) {
@@ -1091,80 +1036,142 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		goto fail_put_clk;
 	}

-	info->mmio_base = ioremap(r->start, resource_size(r));
-	if (info->mmio_base == NULL) {
+	nand->mmio_base = ioremap(r->start, resource_size(r));
+	if (nand->mmio_base == NULL) {
 		dev_err(&pdev->dev, "ioremap() failed\n");
 		ret = -ENODEV;
 		goto fail_free_res;
 	}
-	info->mmio_phys = r->start;
-
-	ret = pxa3xx_nand_init_buff(info);
-	if (ret)
-		goto fail_free_io;
+	nand->mmio_phys = r->start;

 	/* initialize all interrupts to be disabled */
-	disable_int(info, NDSR_MASK);
+	disable_int(nand, NDSR_MASK);
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "no IRQ resource defined\n");
+		ret = -ENXIO;
+		goto fail_put_clk;
+	}

 	ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
-			  pdev->name, info);
+			  pdev->name, nand);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "failed to request IRQ\n");
+		ret = -ENXIO;
+		goto fail_free_irq;
+	}
+
+	platform_set_drvdata(pdev, nand);
+	spin_lock_init(&nand->controller.lock);
+	init_waitqueue_head(&nand->controller.wq);
+	for (cs = 0; cs < NUM_CHIP_SELECT; cs++) {
+		mtd = kzalloc(sizeof(struct mtd_info)
+				+ sizeof(struct pxa3xx_nand_info),
+				GFP_KERNEL);
+		if (!mtd) {
+			dev_err(&pdev->dev, "failed to allocate memory\n");
+			ret = -ENOMEM;
+			goto fail_free_irq;
+		}
+
+		info = (struct pxa3xx_nand_info *)(&mtd[1]);
+		info->nand_data = nand;
+		info->chip_select = cs;
+		mtd->priv = info;
+		mtd->owner = THIS_MODULE;
+		nand->info[cs] = info;
+
+		chip = (struct nand_chip *)(&mtd[1]);
+		chip->controller        = &nand->controller;
+		chip->ecc.read_page	= pxa3xx_nand_read_page_hwecc;
+		chip->ecc.write_page	= pxa3xx_nand_write_page_hwecc;
+		chip->waitfunc		= pxa3xx_nand_waitfunc;
+		chip->select_chip	= pxa3xx_nand_select_chip;
+		chip->cmdfunc		= pxa3xx_nand_cmdfunc;
+		chip->read_word		= pxa3xx_nand_read_word;
+		chip->read_byte		= pxa3xx_nand_read_byte;
+		chip->read_buf		= pxa3xx_nand_read_buf;
+		chip->write_buf		= pxa3xx_nand_write_buf;
+		chip->verify_buf	= pxa3xx_nand_verify_buf;
+		chip->erase_cmd		= pxa3xx_nand_erase_cmd;
+	}
+
+	if (use_dma == 0) {
+		nand->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
+		if (nand->data_buff == NULL) {
+			ret = -ENOMEM;
+			goto fail_free_buf;
+		}
+		goto success_exit;
+	}
+
+	nand->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
+			&nand->data_buff_phys, GFP_KERNEL);
+	if (nand->data_buff == NULL) {
+		dev_err(&pdev->dev, "failed to allocate dma buffer\n");
+		ret = -ENOMEM;
 		goto fail_free_buf;
 	}

-	platform_set_drvdata(pdev, info);
+	nand->data_desc = (void *)nand->data_buff + data_desc_offset;
+	nand->data_desc_addr = nand->data_buff_phys + data_desc_offset;
+	nand->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
+			pxa3xx_nand_data_dma_irq, nand);
+	if (nand->data_dma_ch < 0) {
+		dev_err(&pdev->dev, "failed to request data dma\n");
+		ret = -ENXIO;
+		goto fail_free_buf;
+	}
+success_exit:
 	return 0;

 fail_free_buf:
-	free_irq(irq, info);
-	if (use_dma) {
-		pxa_free_dma(info->data_dma_ch);
-		dma_free_coherent(&pdev->dev, info->data_buff_size,
-			info->data_buff, info->data_buff_phys);
-	} else
-		kfree(info->data_buff);
-fail_free_io:
-	iounmap(info->mmio_base);
+	for (cs = 0; cs < NUM_CHIP_SELECT; cs++) {
+		info = nand->info[cs];
+		free_cs_resource(info, cs);
+	}
+fail_free_irq:
+	free_irq(irq, nand);
+	iounmap(nand->mmio_base);
 fail_free_res:
 	release_mem_region(r->start, resource_size(r));
 fail_put_clk:
-	clk_disable(info->clk);
-	clk_put(info->clk);
-fail_free_mtd:
-	kfree(mtd);
+	clk_disable(nand->clk);
+	clk_put(nand->clk);
+fail_alloc:
+	kfree(nand);
 	return ret;
 }

 static int pxa3xx_nand_remove(struct platform_device *pdev)
 {
-	struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
-	struct mtd_info *mtd = info->mtd;
+	struct pxa3xx_nand *nand = platform_get_drvdata(pdev);
+	struct pxa3xx_nand_info *info;
+	struct mtd_info *mtd;
 	struct resource *r;
-	int irq;
+	int irq, cs;

 	platform_set_drvdata(pdev, NULL);

-	del_mtd_device(mtd);
-	del_mtd_partitions(mtd);
 	irq = platform_get_irq(pdev, 0);
 	if (irq >= 0)
-		free_irq(irq, info);
-	if (use_dma) {
-		pxa_free_dma(info->data_dma_ch);
-		dma_free_writecombine(&pdev->dev, info->data_buff_size,
-				info->data_buff, info->data_buff_phys);
-	} else
-		kfree(info->data_buff);
-
-	iounmap(info->mmio_base);
+		free_irq(irq, nand);
+
+	iounmap(nand->mmio_base);
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	release_mem_region(r->start, resource_size(r));
-
-	clk_disable(info->clk);
-	clk_put(info->clk);
-
-	kfree(mtd);
+	clk_disable(nand->clk);
+	clk_put(nand->clk);
+
+	for (cs = 0; cs < NUM_CHIP_SELECT; cs++) {
+		info = nand->info[cs];
+		if (!info)
+			continue;
+		mtd = get_mtd_by_info(info);
+		del_mtd_partitions(mtd);
+		del_mtd_device(mtd);
+		free_cs_resource(info, cs);
+	}
 	return 0;
 }

@@ -1172,7 +1179,11 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 {
 	struct pxa3xx_nand_platform_data *pdata;
 	struct pxa3xx_nand_info *info;
-	int ret;
+	struct pxa3xx_nand *nand;
+	struct mtd_info *mtd;
+	static const char *probes[] = { "cmdlinepart", NULL };
+	struct mtd_partition *parts;
+	int nr_parts, ret, cs, probe_success = 0;

 	pdata = pdev->dev.platform_data;
 	if (!pdata) {
@@ -1184,25 +1195,30 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 	if (ret)
 		return ret;

-	info = platform_get_drvdata(pdev);
-	if (pxa3xx_nand_scan(info->mtd)) {
-		dev_err(&pdev->dev, "failed to scan nand\n");
-		pxa3xx_nand_remove(pdev);
-		return -ENODEV;
-	}
-
-	if (mtd_has_cmdlinepart()) {
-		static const char *probes[] = { "cmdlinepart", NULL };
-		struct mtd_partition *parts;
-		int nr_parts;
-
-		nr_parts = parse_mtd_partitions(info->mtd, probes, &parts, 0);
-
-		if (nr_parts)
-			return add_mtd_partitions(info->mtd, parts, nr_parts);
+	nand = platform_get_drvdata(pdev);
+	for (cs = 0; cs < NUM_CHIP_SELECT; cs++) {
+		info = nand->info[cs];
+		mtd = get_mtd_by_info(info);
+		if (pxa3xx_nand_scan(mtd)) {
+			dev_err(&pdev->dev, "failed to scan cs#%d nand\n", cs);
+			continue;
+		}
+		nr_parts = 0;
+		if (mtd_has_cmdlinepart()) {
+			nr_parts = parse_mtd_partitions(mtd, probes, &parts, 0);
+			if (nr_parts)
+				ret = add_mtd_partitions(mtd, parts, nr_parts);
+		}
+		if (!nr_parts)
+			ret = add_mtd_partitions(mtd, pdata->parts[cs],
+					pdata->nr_parts[cs]);
+		if (!ret)
+			probe_success = 1;
 	}

-	return add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts);
+	if (!probe_success)
+		pxa3xx_nand_remove(pdev);
+	return ret;
 }

 #ifdef CONFIG_PM
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:34:55 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:34:55 +0800
Subject: [PATCH 11/25] pxa3xx_nand: add bch ecc support
Message-ID: <AANLkTikXUmtoINqXaf0XDMF-EDq99rLVsWGS6VyDC1OL@mail.gmail.com>


From leiwen at marvell.com  Sun Jun  6 10:01:35 2010
From: leiwen at marvell.com (Lei Wen)
Date: Sun, 6 Jun 2010 22:01:35 +0800
Subject: [PATCH 11/25] pxa3xx_nand: add bch ecc support
Message-ID: <mailman.20.1276839416.27306.linux-arm-kernel@lists.infradead.org>

Enable the controller internal bch ecc engine when need.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  126 +++++++++++++++++++++++++++++----------
 1 files changed, 93 insertions(+), 33 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 215677f..c75bed6 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -29,6 +29,7 @@
 #define	CHIP_DELAY_TIMEOUT	(2 * HZ/10)
 #define NAND_STOP_DELAY		(2 * HZ/50)
 #define PAGE_CHUNK_SIZE		(2048)
+#define BCH_THRESHOLD           (8)

 /* registers and bit definitions */
 #define NDCR		(0x00) /* Control register */
@@ -38,12 +39,15 @@
 #define NDPCR		(0x18) /* Page Count Register */
 #define NDBDR0		(0x1C) /* Bad Block Register 0 */
 #define NDBDR1		(0x20) /* Bad Block Register 1 */
+#define NDECCCTRL	(0x28) /* ECC Control Register */
 #define NDDB		(0x40) /* Data Buffer */
 #define NDCB0		(0x48) /* Command Buffer0 */
 #define NDCB1		(0x4C) /* Command Buffer1 */
 #define NDCB2		(0x50) /* Command Buffer2 */

 #define NDCR_SPARE_EN		(0x1 << 31)
+#define NDSR_ERR_CNT_MASK       (0x1F << 16)
+#define NDSR_ERR_CNT(x)         (((x) << 16) & NDSR_ERR_CNT_MASK)
 #define NDCR_ECC_EN		(0x1 << 30)
 #define NDCR_DMA_EN		(0x1 << 29)
 #define NDCR_ND_RUN		(0x1 << 28)
@@ -90,6 +94,13 @@
 #define NDCB0_CMD1_MASK		(0xff)
 #define NDCB0_ADDR_CYC_SHIFT	(16)

+/* ECC Control Register */
+#define NDECCCTRL_ECC_SPARE_MSK (0xFF << 7)
+#define NDECCCTRL_ECC_SPARE(x)  (((x) << 7) & NDECCCTRL_ECC_SPARE_MSK)
+#define NDECCCTRL_ECC_THR_MSK   (0x3F << 1)
+#define NDECCCTRL_ECC_THRESH(x) (((x) << 1) & NDECCCTRL_ECC_THR_MSK)
+#define NDECCCTRL_BCH_EN        (0x1)
+
 /* macros for registers read/write */
 #define nand_writel(info, off, val)	\
 	__raw_writel((val), (info)->mmio_base + (off))
@@ -120,6 +131,13 @@ enum {
 	STATE_IS_WRITE		= (1 << 7),
 };

+/* error code and state */
+enum {
+	ECC_NONE = 0,
+	ECC_HAMMIN,
+	ECC_BCH,
+};
+
 struct pxa3xx_nand_timing {
 	uint32_t	tCH;  /* Enable signal hold time */
 	uint32_t	tCS;  /* Enable signal setup time */
@@ -148,10 +166,11 @@ struct pxa3xx_nand_cmdset {
 struct pxa3xx_nand_flash {
 	char		*name;
 	uint32_t	chip_id;
-	uint16_t	page_per_block; /* Pages per block (PG_PER_BLK) */
-	uint16_t 	page_size;	/* Page size in bytes (PAGE_SZ) */
+	uint16_t	page_per_block; /* Pages per block */
+	uint16_t 	page_size;	/* Page size in bytes */
 	uint8_t		flash_width;	/* Width of Flash memory (DWIDTH_M) */
 	uint8_t 	dfc_width;	/* Width of flash controller(DWIDTH_C) */
+	uint8_t		ecc_type;	/* Which ECC is applied */
 	uint32_t	num_blocks;	/* Number of physical blocks in Flash */
 	struct pxa3xx_nand_timing *timing;	/* NAND Flash timing */
 };
@@ -246,16 +265,16 @@ static struct pxa3xx_nand_timing __devinitdata
timing[] = {
 };

 static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
-	{ 		0,	0,   0,    0,  0,  0,    0, &timing[0], },
-	{ "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, &timing[1], },
-	{ "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, &timing[1], },
-	{ "1GiB 8-bit",    0xd3ec, 128, 2048,  8,  8, 4096, &timing[1], },
-	{ "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, &timing[1], },
-	{ "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, &timing[2], },
-	{ "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, &timing[2], },
-	{ "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, 4096, &timing[2], },
-	{ "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, 4096, &timing[2], },
-	{ "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, &timing[3], },
+{ 		0,	0,   0,    0,  0,  0, ECC_NONE,      0, &timing[0], },
+{ "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, ECC_HAMMIN, 4096, &timing[1], },
+{ "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, ECC_HAMMIN, 2048, &timing[1], },
+{ "1GiB 8-bit",    0xd3ec, 128, 2048,  8,  8, ECC_BCH,    4096, &timing[1], },
+{ "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, ECC_BCH,    8192, &timing[1], },
+{ "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, ECC_HAMMIN, 1024, &timing[2], },
+{ "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, ECC_HAMMIN, 1024, &timing[2], },
+{ "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, ECC_HAMMIN, 4096, &timing[2], },
+{ "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, ECC_HAMMIN, 4096, &timing[2], },
+{ "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, ECC_HAMMIN, 2048, &timing[3], },
 };

 static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
@@ -303,18 +322,43 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
 	struct pxa3xx_nand *nand = info->nand_data;
 	int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;

-	nand->data_size = info->page_size;
-	if (!oob_enable) {
-		nand->oob_size = 0;
-		return;
-	}
-	switch (info->page_size) {
-		case 2048:
-			nand->oob_size = (nand->use_ecc) ? 40 : 64;
+	if (info->page_size >= PAGE_CHUNK_SIZE) {
+		nand->data_size = PAGE_CHUNK_SIZE;
+		if (!oob_enable) {
+			nand->oob_size = 0;
+			return;
+		}
+
+		switch (nand->use_ecc) {
+		case ECC_HAMMIN:
+			nand->oob_size = 40;
+			break;
+		case ECC_BCH:
+			nand->oob_size = 32;
+			break;
+		default:
+			nand->oob_size = 64;
+			break;
+		}
+	} else {
+		nand->data_size = 512;
+		if (!oob_enable) {
+			nand->oob_size = 0;
+			return;
+		}
+
+		switch (nand->use_ecc) {
+		case ECC_HAMMIN:
+			nand->oob_size = 8;
 			break;
-		case 512:
-			nand->oob_size = (nand->use_ecc) ? 8 : 16;
+		case ECC_BCH:
+			printk("Don't support BCH on small page device!!!\n");
+			BUG();
 			break;
+		default:
+			nand->oob_size = 16;
+			break;
+		}
 	}
 }

@@ -327,16 +371,26 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
 static void pxa3xx_nand_start(struct pxa3xx_nand *nand)
 {
 	struct pxa3xx_nand_info *info;
-	uint32_t ndcr;
+	uint32_t ndcr, ndeccctrl = 0;

 	info = nand->info[nand->chip_select];
 	ndcr = info->reg_ndcr;
-	ndcr |= nand->use_ecc ? NDCR_ECC_EN : 0;
 	ndcr |= nand->use_dma ? NDCR_DMA_EN : NDCR_STOP_ON_UNCOR;
 	ndcr |= NDCR_ND_RUN;

+	switch (nand->use_ecc) {
+	case ECC_BCH:
+		ndeccctrl |= NDECCCTRL_BCH_EN;
+		ndeccctrl |= NDECCCTRL_ECC_THRESH(BCH_THRESHOLD);
+	case ECC_HAMMIN:
+		ndcr |= NDCR_ECC_EN;
+	default:
+		break;
+	}
+
 	/* clear status bits and run */
 	nand_writel(nand, NDCR, 0);
+	nand_writel(nand, NDECCCTRL, ndeccctrl);
 	nand_writel(nand, NDSR, NDSR_MASK);
 	nand_writel(nand, NDCR, ndcr);
 }
@@ -449,6 +503,7 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 	info            = nand->info[cs];

 	status = nand_readl(nand, NDSR);
+	nand->bad_count = (status & NDSR_ERR_CNT_MASK) >> 16;
 	if (status & NDSR_DBERR)
 		nand->retcode = ERR_DBERR;
 	if (status & NDSR_SBERR)
@@ -782,6 +837,7 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	uint32_t ndcr = 0;

 	/* calculate flash information */
+	info->use_ecc = f->ecc_type;
 	info->page_size = f->page_size;
 	info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;

@@ -804,7 +860,6 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	ndcr |= NDCR_SPARE_EN; /* enable spare by default */

 	info->reg_ndcr = ndcr;
-	info->use_ecc = 1;

 	pxa3xx_nand_set_timing(info, f->timing);
 	return 0;
@@ -814,6 +869,7 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand *nand)
 {
 	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
 	uint32_t ndcr = nand_readl(nand, NDCR);
+	uint32_t ndeccctrl = nand_readl(nand, NDECCCTRL);

 	if (nand->chip_select > 0) {
 		printk(KERN_ERR "We could not detect configure if two cs is supported!!\n");
@@ -822,6 +878,7 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand *nand)
 	info->reg_ndcr = ndcr & ~(NDCR_INT_MASK | NDCR_ECC_EN | NDCR_DMA_EN
| NDCR_ND_RUN);
 	info->ndtr0cs0 = nand_readl(nand, NDTR0CS0);
 	info->ndtr1cs0 = nand_readl(nand, NDTR1CS0);
+	info->use_ecc = (ndeccctrl & NDECCCTRL_BCH_EN) ? ECC_BCH : ECC_HAMMIN;

 	return 0;
 }
@@ -856,13 +913,16 @@ static int pxa3xx_nand_read_page_hwecc(struct
mtd_info *mtd,

 	if (nand->retcode == ERR_SBERR) {
 		switch (nand->use_ecc) {
-			case 1:
-				mtd->ecc_stats.corrected++;
-				break;
-
-			case 0:
-			default:
-				break;
+		case ECC_BCH:
+			if (nand->bad_count > BCH_THRESHOLD)
+				mtd->ecc_stats.corrected +=
+					(nand->bad_count - BCH_THRESHOLD);
+			break;
+		case ECC_HAMMIN:
+			mtd->ecc_stats.corrected ++;
+		case ECC_NONE:
+		default:
+			break;
 		}
 	} else if (nand->retcode == ERR_DBERR) {
 		int buf_blank;
@@ -1045,8 +1105,8 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 	nand->mmio_phys = r->start;

 	/* initialize all interrupts to be disabled */
-	disable_int(nand, NDSR_MASK);
 	irq = platform_get_irq(pdev, 0);
+	disable_int(nand, NDCR_INT_MASK);
 	if (irq < 0) {
 		dev_err(&pdev->dev, "no IRQ resource defined\n");
 		ret = -ENXIO;
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:35:02 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:35:02 +0800
Subject: [PATCH 12/25] pxa3xx_nand: add more attribute that platform could 
	choose from
Message-ID: <AANLkTikqQl2rmEJyee01f1Oq-oMf2C225cysCE53sykA@mail.gmail.com>


From leiwen at marvell.com  Sun Jun  6 10:02:08 2010
From: leiwen at marvell.com (Lei Wen)
Date: Sun, 6 Jun 2010 22:02:08 +0800
Subject: [PATCH 12/25] pxa3xx_nand: add more attribute that platform
Message-ID: <mailman.22.1276839425.27306.linux-arm-kernel@lists.infradead.org>

could choose from

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 arch/arm/mach-mmp/aspenite.c                 |    3 ++-
 arch/arm/mach-mmp/avengers_lite.c            |    3 ++-
 arch/arm/mach-pxa/cm-x300.c                  |    3 +--
 arch/arm/mach-pxa/colibri-pxa3xx.c           |    3 +--
 arch/arm/mach-pxa/littleton.c                |    2 +-
 arch/arm/mach-pxa/mxm8x10.c                  |    3 +--
 arch/arm/mach-pxa/raumfeld.c                 |    3 +--
 arch/arm/mach-pxa/zylonite.c                 |    2 +-
 arch/arm/plat-pxa/include/plat/pxa3xx_nand.h |   23 +++++++++++++----------
 drivers/mtd/nand/pxa3xx_nand.c               |   11 +++++++----
 10 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 81ad58d..8d739d1 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -125,7 +125,8 @@ static struct mtd_partition aspenite_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data aspenite_nand_info = {
-	.enable_arbiter	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_NAKED_CMD_EN | PXA3XX_DMA_EN
+				| PXA3XX_ADV_TIME_TUNING | PXA3XX_TWO_CHIP_EN,
 	.parts[0]	= aspenite_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(aspenite_nand_partitions),
 };
diff --git a/arch/arm/mach-mmp/avengers_lite.c
b/arch/arm/mach-mmp/avengers_lite.c
index a828b1c..3a07613 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -77,7 +77,8 @@ static void __init avengers_init_flash(void)
 	avengers_nand_info.nr_parts[0] = ARRAY_SIZE(avengers_nand_partitions_0);
 	avengers_nand_info.parts[1] = avengers_nand_partitions_1;
 	avengers_nand_info.nr_parts[1] = ARRAY_SIZE(avengers_nand_partitions_1);
-	avengers_nand_info.enable_arbiter = 1;
+	avengers_nand_info.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_NAKED_CMD_EN
+		| PXA3XX_DMA_EN | PXA3XX_ADV_TIME_TUNING | PXA3XX_TWO_CHIP_EN;
 	pxa168_add_nand(&avengers_nand_info);
 }

diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index ce1f6d3..9f0282b 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -417,8 +417,7 @@ static struct mtd_partition cm_x300_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data cm_x300_nand_info = {
-	.enable_arbiter	= 1,
-	.keep_config	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_DMA_EN | PXA3XX_KEEP_CONFIG,
 	.parts[0]	= cm_x300_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(cm_x300_nand_partitions),
 };
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c
b/arch/arm/mach-pxa/colibri-pxa3xx.c
index b33559c..627b289 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -186,8 +186,7 @@ static struct mtd_partition colibri_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data colibri_nand_info = {
-	.enable_arbiter	= 1,
-	.keep_config	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_DMA_EN | PXA3XX_KEEP_CONFIG,
 	.parts[0]	= colibri_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(colibri_nand_partitions),
 };
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 717cf92..e63451c 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -324,7 +324,7 @@ static struct mtd_partition littleton_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data littleton_nand_info = {
-	.enable_arbiter	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_DMA_EN,
 	.parts[0]	= littleton_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(littleton_nand_partitions),
 };
diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c
index 66c2086..baca736 100644
--- a/arch/arm/mach-pxa/mxm8x10.c
+++ b/arch/arm/mach-pxa/mxm8x10.c
@@ -389,8 +389,7 @@ static struct mtd_partition mxm_8x10_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data mxm_8x10_nand_info = {
-	.enable_arbiter	= 1,
-	.keep_config	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_DMA_EN | PXA3XX_KEEP_CONFIG,
 	.parts[0]	= mxm_8x10_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(mxm_8x10_nand_partitions)
 };
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index df75d4d..8761775 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -348,8 +348,7 @@ static struct mtd_partition raumfeld_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data raumfeld_nand_info = {
-	.enable_arbiter	= 1,
-	.keep_config	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_DMA_EN | PXA3XX_KEEP_CONFIG,
 	.parts[0]	= raumfeld_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(raumfeld_nand_partitions),
 };
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 9e5c6cd..5cf3d10 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -355,7 +355,7 @@ static struct mtd_partition zylonite_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data zylonite_nand_info = {
-	.enable_arbiter	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_DMA_EN,
 	.parts[0]	= zylonite_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(zylonite_nand_partitions),
 };
diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index 56015bd..72bb70e 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -5,17 +5,20 @@
 #include <linux/mtd/partitions.h>

 #define NUM_CHIP_SELECT		(2)
+/* the data flash bus is shared between the Static Memory
+ * Controller and the Data Flash Controller,  the arbiter
+ * controls the ownership of the bus
+ */
+#define PXA3XX_ARBI_EN		(1)
+#define PXA3XX_NAKED_CMD_EN	(1 << 1)
+#define PXA3XX_TWO_CHIP_EN	(1 << 2)
+#define PXA3XX_DMA_EN		(1 << 3)
+/* for newer controller support more precise timing tuning, only
+ * enable such tuning for those platform which support it */
+#define PXA3XX_ADV_TIME_TUNING	(1 << 4)
+#define PXA3XX_KEEP_CONFIG	(1 << 5)
 struct pxa3xx_nand_platform_data {
-
-	/* the data flash bus is shared between the Static Memory
-	 * Controller and the Data Flash Controller,  the arbiter
-	 * controls the ownership of the bus
-	 */
-	int	enable_arbiter;
-
-	/* allow platform code to keep OBM/bootloader defined NFC config */
-	int	keep_config;
-
+	unsigned int				controller_attrs;
 	const struct mtd_partition		*parts[NUM_CHIP_SELECT];
 	unsigned int				nr_parts[NUM_CHIP_SELECT];

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index c75bed6..8ec9172 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -849,7 +849,7 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	else
 		info->row_addr_cycles = 2;

-	ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
+	ndcr |= (pdata->controller_attrs & PXA3XX_ARBI_EN) ? NDCR_ND_ARB_EN : 0;
 	ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
 	ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
 	ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
@@ -975,7 +975,7 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd)
 	uint64_t chipsize;
 	int i, ret;

-	if (pdata->keep_config) {
+	if (pdata->controller_attrs & PXA3XX_KEEP_CONFIG) {
 		if (pxa3xx_nand_detect_config(nand) == 0)
 			goto KEEP_CONFIG;
 	}
@@ -1243,7 +1243,7 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 	struct mtd_info *mtd;
 	static const char *probes[] = { "cmdlinepart", NULL };
 	struct mtd_partition *parts;
-	int nr_parts, ret, cs, probe_success = 0;
+	int nr_parts, ret, cs, probe_success = 0, cs_to_scan;

 	pdata = pdev->dev.platform_data;
 	if (!pdata) {
@@ -1251,12 +1251,15 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 		return -ENODEV;
 	}

+	if (!(pdata->controller_attrs & PXA3XX_DMA_EN))
+		use_dma = 0;
 	ret = alloc_nand_resource(pdev);
 	if (ret)
 		return ret;

 	nand = platform_get_drvdata(pdev);
-	for (cs = 0; cs < NUM_CHIP_SELECT; cs++) {
+	cs_to_scan = (pdata->controller_attrs & PXA3XX_TWO_CHIP_EN)? 2 : 1;
+	for (cs = 0; cs < cs_to_scan; cs++) {
 		info = nand->info[cs];
 		mtd = get_mtd_by_info(info);
 		if (pxa3xx_nand_scan(mtd)) {
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:35:13 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:35:13 +0800
Subject: [PATCH 13/25] pxa3xx_nand: enable 4k page operation
Message-ID: <AANLkTik-MM98PEznLcu5YUO0GqValtpw-hTmSdr3GtAR@mail.gmail.com>


From leiwen at marvell.com  Sun Jun  6 10:05:06 2010
From: leiwen at marvell.com (Lei Wen)
Date: Sun, 6 Jun 2010 22:05:06 +0800
Subject: [PATCH 13/25] pxa3xx_nand: enable 4k page operation
Message-ID: <mailman.24.1276839437.27306.linux-arm-kernel@lists.infradead.org>

For limitation of our controller, we only could do large page
nand chip by dividing the original page size into what we could
afford. We call one divide operation as chunk.

The divide operation need naked command support, which may not
be existed in so old version. You should check it first before
you want to use this feature.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  355 +++++++++++++++++++++++++++++++---------
 1 files changed, 280 insertions(+), 75 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 8ec9172..1e75df4 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -29,7 +29,10 @@
 #define	CHIP_DELAY_TIMEOUT	(2 * HZ/10)
 #define NAND_STOP_DELAY		(2 * HZ/50)
 #define PAGE_CHUNK_SIZE		(2048)
+#define OOB_CHUNK_SIZE		(64)
 #define BCH_THRESHOLD           (8)
+#define CMD_POOL_SIZE           (5)
+#define READ_ID_BYTES		(4)

 /* registers and bit definitions */
 #define NDCR		(0x00) /* Control register */
@@ -39,33 +42,50 @@
 #define NDPCR		(0x18) /* Page Count Register */
 #define NDBDR0		(0x1C) /* Bad Block Register 0 */
 #define NDBDR1		(0x20) /* Bad Block Register 1 */
+#define NDREDEL		(0x24) /* Read Enable Return Delay Register */
 #define NDECCCTRL	(0x28) /* ECC Control Register */
+#define NDBZCNT		(0x2C) /* Timer for NDRnB0 and NDRnB1 */
 #define NDDB		(0x40) /* Data Buffer */
 #define NDCB0		(0x48) /* Command Buffer0 */
 #define NDCB1		(0x4C) /* Command Buffer1 */
 #define NDCB2		(0x50) /* Command Buffer2 */

 #define NDCR_SPARE_EN		(0x1 << 31)
-#define NDSR_ERR_CNT_MASK       (0x1F << 16)
-#define NDSR_ERR_CNT(x)         (((x) << 16) & NDSR_ERR_CNT_MASK)
 #define NDCR_ECC_EN		(0x1 << 30)
 #define NDCR_DMA_EN		(0x1 << 29)
 #define NDCR_ND_RUN		(0x1 << 28)
 #define NDCR_DWIDTH_C		(0x1 << 27)
 #define NDCR_DWIDTH_M		(0x1 << 26)
-#define NDCR_PAGE_SZ		(0x1 << 24)
-#define NDCR_NCSX		(0x1 << 23)
-#define NDCR_ND_MODE		(0x3 << 21)
+#define NDCR_PAGE_SZ_MASK	(0x3 << 24)
+#define NDCR_PAGE_SZ(x)		(((x) << 24) & NDCR_PAGE_SZ_MASK)
+#define NDCR_SEQ_DIS		(0x1 << 23)
+#define NDCR_ND_STOP		(0x1 << 22)
+#define NDCR_FORCE_CSX		(0x1 << 21)
 #define NDCR_CLR_PG_CNT		(0x1 << 20)
 #define NDCR_STOP_ON_UNCOR	(0x1 << 19)
 #define NDCR_RD_ID_CNT_MASK	(0x7 << 16)
 #define NDCR_RD_ID_CNT(x)	(((x) << 16) & NDCR_RD_ID_CNT_MASK)

 #define NDCR_RA_START		(0x1 << 15)
-#define NDCR_PG_PER_BLK		(0x1 << 14)
+#define NDCR_PG_PER_BLK_MASK	(0x3 << 13)
+#define NDCR_PG_PER_BLK(x)	(((x) << 13) & NDCR_PG_PER_BLK_MASK)
 #define NDCR_ND_ARB_EN		(0x1 << 12)
 #define NDCR_INT_MASK           (0xFFF)
+#define NDCR_RDYM               (0x1 << 11)
+#define NDCR_CS0_PAGEDM         (0x1 << 10)
+#define NDCR_CS1_PAGEDM         (0x1 << 9)
+#define NDCR_CS0_CMDDM          (0x1 << 8)
+#define NDCR_CS1_CMDDM          (0x1 << 7)
+#define NDCR_CS0_BBDM           (0x1 << 6)
+#define NDCR_CS1_BBDM           (0x1 << 5)
+#define NDCR_UNCERRM            (0x1 << 4)
+#define NDCR_CORERRM            (0x1 << 3)
+#define NDCR_WRDREQM            (0x1 << 2)
+#define NDCR_RDDREQM            (0x1 << 1)
+#define NDCR_WRCMDREQM          (0x1)

+#define NDSR_ERR_CNT_MASK       (0x1F << 16)
+#define NDSR_ERR_CNT(x)         (((x) << 16) & NDSR_ERR_CNT_MASK)
 #define NDSR_MASK		(0xfff)
 #define NDSR_RDY                (0x1 << 12)
 #define NDSR_FLASH_RDY          (0x1 << 11)
@@ -81,6 +101,8 @@
 #define NDSR_RDDREQ		(0x1 << 1)
 #define NDSR_WRCMDREQ		(0x1)

+#define NDCB0_CMD_XTYPE_MASK    (0x7 << 29)
+#define NDCB0_CMD_XTYPE(x)      (((x) << 29) & NDCB0_CMD_XTYPE_MASK)
 #define NDCB0_ST_ROW_EN         (0x1 << 26)
 #define NDCB0_AUTO_RS		(0x1 << 25)
 #define NDCB0_CSEL		(0x1 << 24)
@@ -131,6 +153,7 @@ enum {
 	STATE_IS_WRITE		= (1 << 7),
 };

+#define STATE_MASK		(0x3f)
 /* error code and state */
 enum {
 	ECC_NONE = 0,
@@ -185,7 +208,6 @@ struct pxa3xx_nand_info {
 	/* calculated from pxa3xx_nand_flash data */
 	uint8_t			col_addr_cycles;
 	uint8_t			row_addr_cycles;
-	uint8_t			read_id_bytes;

 	/* cached register value */
 	uint32_t		reg_ndcr;
@@ -221,7 +243,8 @@ struct pxa3xx_nand {
 	unsigned char		*oob_buff;
 	uint32_t		buf_start;
 	uint32_t		buf_count;
-	uint8_t			total_cmds;
+	uint16_t		data_column;
+	uint16_t		oob_column;

 	/* relate to the command */
 	uint8_t			chip_select;
@@ -230,8 +253,11 @@ struct pxa3xx_nand {
 	int			use_dma;	/* use DMA ? */
 	int 			retcode;

-	/* generated NDCBx register values */
-	uint32_t		ndcb0;
+	/* cached register value */
+	uint8_t			cmd_seqs;
+	uint8_t			total_cmds;
+	uint8_t			wait_ready[CMD_POOL_SIZE];
+	uint32_t		ndcb0[CMD_POOL_SIZE];
 	uint32_t		ndcb1;
 	uint32_t		ndcb2;
 };
@@ -274,6 +300,7 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
 { "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, ECC_HAMMIN, 1024, &timing[2], },
 { "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, ECC_HAMMIN, 4096, &timing[2], },
 { "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, ECC_HAMMIN, 4096, &timing[2], },
+{ "1GiB 8-bit",    0x382c, 128, 4096,  8,  8, ECC_BCH,    2048, &timing[2], },
 { "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, ECC_HAMMIN, 2048, &timing[3], },
 };

@@ -430,41 +457,98 @@ static void disable_int(struct pxa3xx_nand
*nand, uint32_t int_mask)
 	nand_writel(nand, NDCR, ndcr | int_mask);
 }

+static void nand_error_dump(struct pxa3xx_nand *nand)
+{
+	int i;
+
+	printk(KERN_ERR "NAND controller state wrong!!!\n");
+	printk(KERN_ERR "command %x, state %x, current seqs %d, errcode %x,
bad count %d\n",
+			nand->command, nand->state, nand->cmd_seqs,
+			nand->retcode, nand->bad_count);
+	printk(KERN_ERR "Totally %d command for sending\n",
+			nand->total_cmds);
+	for (i = 0; i < nand->total_cmds; i ++)
+		printk(KERN_ERR "NDCB0:%d: %x\n",
+				i, nand->ndcb0[i]);
+	printk(KERN_ERR "NDCB1: %x; NDCB2 %x\n", nand->ndcb1, nand->ndcb2);
+
+	printk(KERN_ERR "\nRegister DUMPing ##############\n");
+	printk(KERN_ERR "NDCR %x\n"
+			"NDSR %x\n"
+			"NDCB0 %x\n"
+			"NDCB1 %x\n"
+			"NDCB2 %x\n"
+			"NDTR0CS0 %x\n"
+			"NDTR1CS0 %x\n"
+			"NDBDR0 %x\n"
+			"NDBDR1 %x\n"
+			"NDREDEL %x\n"
+			"NDECCCTRL %x\n"
+			"NDBZCNT %x\n\n",
+			nand_readl(nand, NDCR),
+			nand_readl(nand, NDSR),
+			nand_readl(nand, NDCB0),
+			nand_readl(nand, NDCB1),
+			nand_readl(nand, NDCB2),
+			nand_readl(nand, NDTR0CS0),
+			nand_readl(nand, NDTR1CS0),
+			nand_readl(nand, NDBDR0),
+			nand_readl(nand, NDBDR1),
+			nand_readl(nand, NDREDEL),
+			nand_readl(nand, NDECCCTRL),
+			nand_readl(nand, NDBZCNT));
+}
+
 static void handle_data_pio(struct pxa3xx_nand *nand)
 {
+	unsigned int data_size, oob_size;
+
+	data_size = DIV_ROUND_UP(nand->data_size, 4);
+	oob_size = DIV_ROUND_UP(nand->oob_size, 4);
 	if (nand->state & STATE_IS_WRITE) {
-		__raw_writesl(nand->mmio_base + NDDB, nand->data_buff,
-				DIV_ROUND_UP(nand->data_size, 4));
+		__raw_writesl(nand->mmio_base + NDDB,
+				nand->data_buff + nand->data_column, data_size);
 		if (nand->oob_size > 0)
-			__raw_writesl(nand->mmio_base + NDDB, nand->oob_buff,
-					DIV_ROUND_UP(nand->oob_size, 4));
-
+			__raw_writesl(nand->mmio_base + NDDB,
+				nand->oob_buff + nand->oob_column, oob_size);
 	}
 	else {
-		__raw_readsl(nand->mmio_base + NDDB, nand->data_buff,
-				DIV_ROUND_UP(nand->data_size, 4));
+		__raw_readsl(nand->mmio_base + NDDB,
+				nand->data_buff + nand->data_column, data_size);
 		if (nand->oob_size > 0)
-			__raw_readsl(nand->mmio_base + NDDB, nand->oob_buff,
-					DIV_ROUND_UP(nand->oob_size, 4));
+			__raw_readsl(nand->mmio_base + NDDB,
+				nand->oob_buff + nand->oob_column, oob_size);
 	}
+	nand->data_column += (data_size << 2);
+	nand->oob_column += (oob_size << 2);
 }

 static void start_data_dma(struct pxa3xx_nand *nand, int dir_out)
 {
+	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
 	struct pxa_dma_desc *desc = nand->data_desc;
-	int dma_len = ALIGN(nand->data_size + nand->oob_size, 32);
-
-	desc->ddadr = DDADR_STOP;
-	desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
+	struct pxa_dma_desc *desc_oob = nand->data_desc + 1;
+	unsigned int data_len = ALIGN(nand->data_size, 32);
+	unsigned int oob_len = ALIGN(nand->oob_size, 32);

+	desc_oob->ddadr = desc->ddadr = DDADR_STOP;
+	desc_oob->dcmd = desc->dcmd = DCMD_WIDTH4 | DCMD_BURST32;
 	if (dir_out) {
-		desc->dsadr = nand->data_buff_phys;
+		desc->dsadr = nand->data_buff_phys + nand->data_column;
 		desc->dtadr = nand->mmio_phys + NDDB;
-		desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
+		desc->dcmd |= DCMD_ENDIRQEN | DCMD_INCSRCADDR | DCMD_FLOWTRG |
(data_len + oob_len);
 	} else {
-		desc->dtadr = nand->data_buff_phys;
-		desc->dsadr = nand->mmio_phys + NDDB;
-		desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
+		if (nand->oob_size > 0) {
+			desc_oob->dtadr = nand->data_buff_phys
+					+ info->page_size + nand->oob_column;
+			desc_oob->dcmd |= DCMD_ENDIRQEN | DCMD_INCTRGADDR | DCMD_FLOWSRC | oob_len;
+			desc->ddadr = nand->data_desc_addr + sizeof(struct pxa_dma_desc);
+			desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC | data_len;
+		}
+		else
+			desc->dcmd |= DCMD_ENDIRQEN | DCMD_INCTRGADDR | DCMD_FLOWSRC | data_len;
+		desc->dtadr = nand->data_buff_phys + nand->data_column;
+		desc_oob->dsadr = desc->dsadr = nand->mmio_phys + NDDB;
 	}

 	DRCMR(nand->drcmr_dat) = DRCMR_MAPVLD | nand->data_dma_ch;
@@ -484,6 +568,8 @@ static void pxa3xx_nand_data_dma_irq(int channel,
void *data)
 		nand->retcode = ERR_DMABUSERR;
 	}

+	nand->data_column += nand->data_size;
+	nand->oob_column += nand->oob_size;
 	enable_int(nand, NDCR_INT_MASK);
 	nand_writel(nand, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
 }
@@ -492,7 +578,7 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 {
 	struct pxa3xx_nand *nand = devid;
 	struct pxa3xx_nand_info *info;
-	unsigned int status, is_completed = 0, cs;
+	unsigned int status, is_completed = 0, cs, cmd_seqs, ndcb1, ndcb2;
 	unsigned int ready, cmd_done, page_done, badblock_detect;

 	cs		= nand->chip_select;
@@ -501,13 +587,14 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 	page_done       = (cs) ? NDSR_CS1_PAGED : NDSR_CS0_PAGED;
 	badblock_detect = (cs) ? NDSR_CS1_BBD : NDSR_CS0_BBD;
 	info            = nand->info[cs];
+	cmd_seqs	= nand->cmd_seqs;

 	status = nand_readl(nand, NDSR);
 	nand->bad_count = (status & NDSR_ERR_CNT_MASK) >> 16;
-	if (status & NDSR_DBERR)
-		nand->retcode = ERR_DBERR;
 	if (status & NDSR_SBERR)
 		nand->retcode = ERR_SBERR;
+	if (status & NDSR_DBERR)
+		nand->retcode = ERR_DBERR;
 	if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {

 		nand->state |= STATE_DATA_PROCESSING;
@@ -521,24 +608,51 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)

 		nand->state |= STATE_DATA_DONE;
 	}
+	if (status & page_done)
+		nand->state |= STATE_PAGE_DONE;
+	if (status & ready) {
+		nand->state |= STATE_READY;
+		if (nand->wait_ready[cmd_seqs]) {
+			enable_int(nand, NDCR_WRCMDREQM);
+			if (cmd_seqs == nand->total_cmds)
+				is_completed = 1;
+		}
+	}
 	if (status & cmd_done) {
 		nand->state |= STATE_CMD_DONE;
-		is_completed = 1;
+		if (cmd_seqs == nand->total_cmds && !nand->wait_ready[cmd_seqs])
+			is_completed = 1;
 	}
-	if (status & ready)
-		nand->state |= STATE_READY;
-	if (status & page_done)
-		nand->state |= STATE_PAGE_DONE;

 	if (status & NDSR_WRCMDREQ) {
-		nand_writel(nand, NDSR, NDSR_WRCMDREQ);
 		status &= ~NDSR_WRCMDREQ;
-		nand->state |= STATE_CMD_WAIT_DONE;
-		nand_writel(nand, NDCB0, nand->ndcb0);
-		nand_writel(nand, NDCB0, nand->ndcb1);
-		nand_writel(nand, NDCB0, nand->ndcb2);
+		if (nand->wait_ready[cmd_seqs] && !(nand->state & STATE_READY)) {
+			disable_int(nand, NDCR_WRCMDREQM);
+			goto IRQ_FORCE_EXIT;
+		}
+
+		nand_writel(nand, NDSR, NDSR_WRCMDREQ);
+		if (cmd_seqs < nand->total_cmds) {
+			nand->cmd_seqs ++;
+			if (cmd_seqs == 0) {
+				ndcb1 = nand->ndcb1;
+				ndcb2 = nand->ndcb2;
+			}
+			else {
+				ndcb1 = 0;
+				ndcb2 = 0;
+			}
+			nand->state &= ~STATE_MASK;
+			nand->state |= STATE_CMD_WAIT_DONE;
+			nand_writel(nand, NDCB0, nand->ndcb0[cmd_seqs]);
+			nand_writel(nand, NDCB0, ndcb1);
+			nand_writel(nand, NDCB0, ndcb2);
+		}
+		else
+			is_completed = 1;
 	}

+IRQ_FORCE_EXIT:
 	/* clear NDSR to let the controller exit the IRQ */
 	nand_writel(nand, NDSR, status);
 	if (is_completed)
@@ -559,7 +673,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 		uint16_t column, int page_addr)
 {
 	uint16_t cmd;
-	int addr_cycle, exec_cmd, ndcb0;
+	int addr_cycle, exec_cmd, ndcb0, i, chunks = 0;
 	struct mtd_info *mtd;
 	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];

@@ -569,14 +683,19 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 	exec_cmd = 1;

 	/* reset data and oob column point to handle data */
+	nand->data_column	= 0;
+	nand->oob_column	= 0;
 	nand->buf_start		= 0;
 	nand->buf_count		= 0;
-	nand->ndcb0		= ndcb0;
+	nand->total_cmds	= 1;
+	nand->cmd_seqs		= 0;
 	nand->data_size		= 0;
 	nand->oob_size		= 0;
 	nand->use_ecc		= 0;
 	nand->use_dma		= 0;
 	nand->state		= 0;
+	nand->bad_count		= 0;
+	nand->retcode		= ERR_NONE;
 	nand->command		= command;

 	switch (command) {
@@ -587,6 +706,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 		pxa3xx_set_datasize(info);
 		nand->oob_buff = nand->data_buff + nand->data_size;
 		nand->use_dma = use_dma;
+		chunks = info->page_size / nand->data_size;
 		break;
 	case NAND_CMD_SEQIN:
 		exec_cmd = 0;
@@ -597,6 +717,11 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 		break;
 	}

+	/* clear the command buffer */
+	for (i = 0; i < CMD_POOL_SIZE; i ++) {
+		nand->ndcb0[i] = ndcb0;
+		nand->wait_ready[i] = 0;
+	}
 	addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
 			+ info->col_addr_cycles);

@@ -611,14 +736,37 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 			nand->buf_start = column;

 		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
-			nand->ndcb0 |= NDCB0_CMD_TYPE(0)
+			nand->ndcb0[0] |= NDCB0_CMD_TYPE(0)
 					| addr_cycle
 					| (cmd & NDCB0_CMD1_MASK);
-		else
-			nand->ndcb0 |= NDCB0_CMD_TYPE(0)
-					| NDCB0_DBC
-					| addr_cycle
-					| cmd;
+		else {
+			if (chunks == 1)
+				nand->ndcb0[0] |= NDCB0_CMD_TYPE(0)
+						| NDCB0_DBC
+						| addr_cycle
+						| cmd;
+			else {
+				nand->total_cmds = chunks + 1;
+				nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x6)
+						| NDCB0_CMD_TYPE(0)
+						| NDCB0_DBC
+						| NDCB0_NC
+						| addr_cycle
+						| cmd;
+
+				nand->ndcb0[1] |= NDCB0_CMD_XTYPE(0x5)
+						| NDCB0_NC
+						| addr_cycle;
+
+				for (i = 2; i <= chunks; i ++)
+					nand->ndcb0[i] = nand->ndcb0[1];
+
+				nand->ndcb0[chunks] &= ~NDCB0_NC;
+				/* we should wait RnB go high again
+				 * before read out data*/
+				nand->wait_ready[1] = 1;
+			}
+		}

 	case NAND_CMD_SEQIN:
 		/* small page addr setting */
@@ -651,18 +799,46 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,

 		cmd = cmdset.program;
 		nand->state |= STATE_IS_WRITE;
-		nand->ndcb0 |= NDCB0_CMD_TYPE(0x1)
-				| NDCB0_AUTO_RS
-				| NDCB0_ST_ROW_EN
-				| NDCB0_DBC
-				| cmd
-				| addr_cycle;
+		if (chunks == 1)
+			nand->ndcb0[0] |= NDCB0_CMD_TYPE(0x1)
+					| NDCB0_AUTO_RS
+					| NDCB0_ST_ROW_EN
+					| NDCB0_DBC
+					| cmd
+					| addr_cycle;
+		else {
+			nand->total_cmds = chunks + 1;
+			nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x4)
+					| NDCB0_CMD_TYPE(0x1)
+					| NDCB0_NC
+					| NDCB0_AUTO_RS
+					| (cmd & NDCB0_CMD1_MASK)
+					| addr_cycle;
+
+			for (i = 1; i < chunks; i ++)
+				nand->ndcb0[i] |= NDCB0_CMD_XTYPE(0x5)
+						| NDCB0_NC
+						| NDCB0_AUTO_RS
+						| NDCB0_CMD_TYPE(0x1)
+						| addr_cycle;
+
+			nand->ndcb0[chunks] |= NDCB0_CMD_XTYPE(0x3)
+						| NDCB0_CMD_TYPE(0x1)
+						| NDCB0_ST_ROW_EN
+						| NDCB0_DBC
+						| (cmd & NDCB0_CMD2_MASK)
+						| NDCB0_CMD1_MASK
+						| addr_cycle;
+			/* we should wait for RnB goes high which
+			 * indicate the data has been written succesfully*/
+			nand->wait_ready[nand->total_cmds] = 1;
+		}
 		break;

 	case NAND_CMD_READID:
 		cmd = cmdset.read_id;
-		nand->buf_count = info->read_id_bytes;
-		nand->ndcb0 |= NDCB0_CMD_TYPE(3)
+		nand->buf_count = READ_ID_BYTES;
+		nand->ndcb0[0] |= NDCB0_CMD_TYPE(3)
 				| NDCB0_ADDR_CYC(1)
 				| cmd;

@@ -672,7 +848,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 	case NAND_CMD_STATUS:
 		cmd = cmdset.read_status;
 		nand->buf_count = 1;
-		nand->ndcb0 |= NDCB0_CMD_TYPE(4)
+		nand->ndcb0[0] |= NDCB0_CMD_TYPE(4)
 				| NDCB0_ADDR_CYC(1)
 				| cmd;

@@ -681,7 +857,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,

 	case NAND_CMD_ERASE1:
 		cmd = cmdset.erase;
-		nand->ndcb0 |= NDCB0_CMD_TYPE(2)
+		nand->ndcb0[0] |= NDCB0_CMD_TYPE(2)
 				| NDCB0_AUTO_RS
 				| NDCB0_ADDR_CYC(3)
 				| NDCB0_DBC
@@ -692,7 +868,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 		break;
 	case NAND_CMD_RESET:
 		cmd = cmdset.reset;
-		nand->ndcb0 |= NDCB0_CMD_TYPE(5)
+		nand->ndcb0[0] |= NDCB0_CMD_TYPE(5)
 				| cmd;

 		break;
@@ -741,10 +917,10 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 				CHIP_DELAY_TIMEOUT);
 		if (!ret) {
 			dev_err(&nand->pdev->dev, "Wait time out!!!\n");
+			nand_error_dump(nand);
+			/* Stop State Machine for next command cycle */
+			pxa3xx_nand_stop(nand);
 		}
-		/* Stop State Machine for next command cycle */
-		pxa3xx_nand_stop(nand);
-		disable_int(nand, NDCR_INT_MASK);
 		nand->state &= ~STATE_CMD_PREPARED;
 	}
 }
@@ -828,7 +1004,7 @@ static int pxa3xx_nand_waitfunc(struct mtd_info
*mtd, struct nand_chip *this)
 	return 0;
 }

-static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
+static void pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
 				    const struct pxa3xx_nand_flash *f)
 {
 	struct pxa3xx_nand *nand = info->nand_data;
@@ -836,13 +1012,18 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 	uint32_t ndcr = 0;

+	if (f->page_size > PAGE_CHUNK_SIZE
+			&& !(pdata->controller_attrs & PXA3XX_NAKED_CMD_EN)) {
+		printk(KERN_ERR "Your controller don't support 4k or larger "
+			       "page NAND for don't support naked command\n");
+		BUG();
+	}
 	/* calculate flash information */
 	info->use_ecc = f->ecc_type;
 	info->page_size = f->page_size;
-	info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;

 	/* calculate addressing information */
-	info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
+	info->col_addr_cycles = (f->page_size >= 2048) ? 2 : 1;

 	if (f->num_blocks * f->page_per_block > 65536)
 		info->row_addr_cycles = 3;
@@ -851,18 +1032,42 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,

 	ndcr |= (pdata->controller_attrs & PXA3XX_ARBI_EN) ? NDCR_ND_ARB_EN : 0;
 	ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
-	ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
-	ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
 	ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
 	ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
+	switch (f->page_per_block) {
+		case 32:
+			ndcr |= NDCR_PG_PER_BLK(0x0);
+			break;
+		case 128:
+			ndcr |= NDCR_PG_PER_BLK(0x1);
+			break;
+		case 256:
+			ndcr |= NDCR_PG_PER_BLK(0x3);
+			break;
+		case 64:
+		default:
+			ndcr |= NDCR_PG_PER_BLK(0x2);
+			break;
+	}

-	ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
+	switch (f->page_size) {
+		case 512:
+			ndcr |= NDCR_PAGE_SZ(0x0);
+			break;
+		case 2048:
+		default:
+			ndcr |= NDCR_PAGE_SZ(0x1);
+			ndcr |= NDCR_FORCE_CSX;
+			break;
+
+	}
+
+	ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
 	ndcr |= NDCR_SPARE_EN; /* enable spare by default */

 	info->reg_ndcr = ndcr;

 	pxa3xx_nand_set_timing(info, f->timing);
-	return 0;
 }

 static int pxa3xx_nand_detect_config(struct pxa3xx_nand *nand)
@@ -883,11 +1088,10 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand *nand)
 	return 0;
 }

-/* the maximum possible buffer size for large page with OOB data
- * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
- * data buffer and the DMA descriptor
+/* the max buff size should be large than the largest size
+ * of page of NAND flash that currently controller support
  */
-#define MAX_BUFF_SIZE	PAGE_SIZE
+#define MAX_BUFF_SIZE	((PAGE_CHUNK_SIZE + OOB_CHUNK_SIZE) * 2) +
sizeof(struct pxa_dma_desc) * 2
 static void free_cs_resource(struct pxa3xx_nand_info *info, int cs)
 {
 	struct pxa3xx_nand *nand;
@@ -975,6 +1179,7 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd)
 	uint64_t chipsize;
 	int i, ret;

+	nand->chip_select = info->chip_select;
 	if (pdata->controller_attrs & PXA3XX_KEEP_CONFIG) {
 		if (pxa3xx_nand_detect_config(nand) == 0)
 			goto KEEP_CONFIG;
@@ -1049,7 +1254,7 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 	struct pxa3xx_nand *nand;
 	struct resource *r;
 	int ret, irq, cs;
-	int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
+	int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc) * 2;

 	nand = kzalloc(sizeof(struct pxa3xx_nand), GFP_KERNEL);
 	if (!nand) {
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:35:21 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:35:21 +0800
Subject: [PATCH 14/25] mmp: correct nand clock setting for pxa168 and pxa910
Message-ID: <AANLkTilfAX6_mEkeXCO9MYPzMYXTanvnCbRqjM4KIFxo@mail.gmail.com>


From leiwen at marvell.com  Thu Jun  3 03:46:50 2010
From: leiwen at marvell.com (Lei Wen)
Date: Thu, 3 Jun 2010 15:46:50 +0800
Subject: [PATCH 14/25] mmp: correct nand clock setting for pxa168 and pxa910
Message-ID: <mailman.26.1276839452.27306.linux-arm-kernel@lists.infradead.org>

There is no clock setting at 208Mhz for nand on pxa168 and pxa910
platform. Set correct register and lock the clock at
156MHZ.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 arch/arm/mach-mmp/pxa168.c |    2 +-
 arch/arm/mach-mmp/pxa910.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 652ae66..70d2231 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -78,7 +78,7 @@ static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
 static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);

-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19B, 156000000);

 /* device and clock bindings */
 static struct clk_lookup pxa168_clkregs[] = {
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 46f2d69..96f2b61 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -110,7 +110,7 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
 static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);

-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19B, 156000000);

 /* device and clock bindings */
 static struct clk_lookup pxa910_clkregs[] = {
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:35:29 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:35:29 +0800
Subject: [PATCH 15/25] mmp: add nand support to mmp2
Message-ID: <AANLkTikzX_3shKAC16E7BKqZPFAw2a4b8_ToaYnSny6K@mail.gmail.com>


From leiwen at marvell.com  Thu Jun  3 04:21:04 2010
From: leiwen at marvell.com (Lei Wen)
Date: Thu, 3 Jun 2010 16:21:04 +0800
Subject: [PATCH 15/25] mmp: add nand support to mmp2
Message-ID: <mailman.28.1276839467.27306.linux-arm-kernel@lists.infradead.org>

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/configs/mmp2_defconfig       |    4 +-
 arch/arm/mach-mmp/include/mach/mmp2.h |    6 ++++
 arch/arm/mach-mmp/jasper.c            |   52 +++++++++++++++++++++++++++++++++
 3 files changed, 60 insertions(+), 2 deletions(-)

diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 4b55dcb..e63dec3 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -469,7 +469,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
 #
 # User Modules And Translation Layers
 #
-# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
@@ -525,7 +525,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_GPIO is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_PXA3xx is not set
+CONFIG_MTD_NAND_PXA3xx=y
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 CONFIG_MTD_ONENAND=y
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h
b/arch/arm/mach-mmp/include/mach/mmp2.h
index fec220b..d68890b 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -4,6 +4,7 @@
 #include <linux/i2c.h>
 #include <mach/devices.h>
 #include <plat/i2c.h>
+#include <plat/pxa3xx_nand.h>

 extern struct pxa_device_desc mmp2_device_uart1;
 extern struct pxa_device_desc mmp2_device_uart2;
@@ -15,6 +16,7 @@ extern struct pxa_device_desc mmp2_device_twsi3;
 extern struct pxa_device_desc mmp2_device_twsi4;
 extern struct pxa_device_desc mmp2_device_twsi5;
 extern struct pxa_device_desc mmp2_device_twsi6;
+extern struct pxa_device_desc mmp2_device_nand;

 static inline int mmp2_add_uart(int id)
 {
@@ -56,5 +58,9 @@ static inline int mmp2_add_twsi(int id, struct
i2c_pxa_platform_data *data,
 	return pxa_register_device(d, data, sizeof(*data));
 }

+static inline int mmp2_add_nand(struct pxa3xx_nand_platform_data *data)
+{
+	return pxa_register_device(&mmp2_device_nand, data, sizeof(*data));
+}
 #endif /* __ASM_MACH_MMP2_H */

diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index d77dd41..5d055f3 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -67,6 +67,57 @@ static unsigned long jasper_pin_config[] __initdata = {
 	PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
 };

+static struct mtd_partition jasper_nand_partitions[] = {
+	[0] = {
+		.name		= "Bootloader",
+		.offset		= 0,
+		.size		= 0x100000,
+		.mask_flags	= MTD_WRITEABLE,
+	},
+	[1] = {
+		.name		= "Reserve",
+		.offset		= 0x100000,
+		.size		= 0x080000,
+	},
+	[2] = {
+		.name		= "Reserve",
+		.offset		= 0x180000,
+		.size		= 0x800000,
+		.mask_flags	= MTD_WRITEABLE,
+	},
+	[3] = {
+		.name		= "Kernel",
+		.offset		= 0x980000,
+		.size		= 0x300000,
+		.mask_flags	= MTD_WRITEABLE,
+	},
+	[4] = {
+		.name		= "system",
+		.offset		= 0x0c80000,
+		.size		= 0x7000000,
+	},
+	[5] = {
+		.name		= "userdata",
+		.offset		= 0x7c80000,
+		.size		= 0x7000000,
+	},
+	[6] = {
+		.name		= "filesystem",
+		.offset		= 0x0ec80000,
+		.size		= MTDPART_SIZ_FULL,
+	}
+};
+
+static struct pxa3xx_nand_platform_data jasper_nand_info;
+static void __init jasper_init_flash(void)
+{
+	jasper_nand_info.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_NAKED_CMD_EN
+		| PXA3XX_DMA_EN | PXA3XX_ADV_TIME_TUNING | PXA3XX_TWO_CHIP_EN;
+	jasper_nand_info.parts[0] = jasper_nand_partitions;
+	jasper_nand_info.nr_parts[0] = ARRAY_SIZE(jasper_nand_partitions);
+	mmp2_add_nand(&jasper_nand_info);
+}
+
 static struct regulator_consumer_supply max8649_supply[] = {
 	REGULATOR_SUPPLY("vcc_core", NULL),
 };
@@ -128,6 +179,7 @@ static void __init jasper_init(void)
 	/* on-chip devices */
 	mmp2_add_uart(1);
 	mmp2_add_uart(3);
+	jasper_init_flash();
 	mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));

 	regulator_has_full_constraints();
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:35:36 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:35:36 +0800
Subject: [PATCH 16/25] pxa3xx_nand: update ns2cycle calculation method
Message-ID: <AANLkTilw9YwdJThmCo1l31kF2kSYaiNiFJ3B_sqzY1HX@mail.gmail.com>


From leiwen at marvell.com  Fri Jun  4 02:10:45 2010
From: leiwen at marvell.com (Lei Wen)
Date: Fri, 4 Jun 2010 14:10:45 +0800
Subject: [PATCH 16/25] pxa3xx_nand: update ns2cycle calculation method
Message-ID: <mailman.30.1276839482.27306.linux-arm-kernel@lists.infradead.org>

For the original method change from plus 1 to minus 1,
this way make the default timing like tCS become 0 after calculation,
although we set the timing as 0xa...

Change the method to no plus and minus, and make the result
closer to what the timing specified in the NAND chip spec.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 1e75df4..bdcc881 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -318,7 +318,7 @@ static const char *mtd_names[] = {"pxa3xx_nand-0",
"pxa3xx_nand-1", NULL};
 #define NDTR1_tAR(c)	(min((c), 15) << 0)

 /* convert nano-seconds to nand flash controller clock cycles */
-#define ns2cycle(ns, clk)	(int)(((ns) * (clk / 1000000) / 1000) - 1)
+#define ns2cycle(ns, clk)	(int)((ns) * (clk / 1000000) / 1000)
 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
 				   const struct pxa3xx_nand_timing *t)
 {
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:34:27 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:34:27 +0800
Subject: [PATCH 08/25] mmp: add nand support to pxa168
Message-ID: <AANLkTinxMQjZIG4G1d9WVOiUX8-zHjTuTc1eRuInDRGW@mail.gmail.com>


From haojian.zhuang at gmail.com  Fri Jun 18 01:34:37 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:34:37 +0800
Subject: [PATCH 09/25] pxa3xx_nand: clean the keep configure code
Message-ID: <AANLkTikXQcGjwEpxo-ahNcleAyasY-UfA0Czw8jxGIcQ@mail.gmail.com>


From leiwen at marvell.com  Wed Jun  2 22:26:21 2010
From: leiwen at marvell.com (Lei Wen)
Date: Thu, 3 Jun 2010 10:26:21 +0800
Subject: [PATCH 09/25] pxa3xx_nand: clean the keep configure code
Message-ID: <mailman.33.1276839514.27306.linux-arm-kernel@lists.infradead.org>

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  165 ++++++++++------------------------------
 1 files changed, 42 insertions(+), 123 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 481cb25..8628fc1 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -146,6 +146,7 @@ struct pxa3xx_nand_cmdset {
 };

 struct pxa3xx_nand_flash {
+	char		*name;
 	uint32_t	chip_id;
 	uint16_t	page_per_block; /* Pages per block (PG_PER_BLK) */
 	uint16_t 	page_size;	/* Page size in bytes (PAGE_SZ) */
@@ -219,13 +220,6 @@ static int use_dma = 1;
 module_param(use_dma, bool, 0444);
 MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");

-/*
- * Default NAND flash controller configuration setup by the
- * bootloader. This configuration is used only when pdata->keep_config is set
- */
-static struct pxa3xx_nand_timing default_timing;
-static struct pxa3xx_nand_flash default_flash;
-
 const static struct pxa3xx_nand_cmdset cmdset = {
 	.read1		= 0x3000,
 	.read2		= 0x0050,
@@ -251,15 +245,15 @@ static struct pxa3xx_nand_timing __devinitdata
timing[] = {
 };

 static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
-	{      0,   0,    0,  0,  0,    0, &timing[0], },
-	{ 0x46ec,  32,  512, 16, 16, 4096, &timing[1], },
-	{ 0xdaec,  64, 2048,  8,  8, 2048, &timing[1], },
-	{ 0xd7ec, 128, 4096,  8,  8, 8192, &timing[1], },
-	{ 0xa12c,  64, 2048,  8,  8, 1024, &timing[2], },
-	{ 0xb12c,  64, 2048, 16, 16, 1024, &timing[2], },
-	{ 0xdc2c,  64, 2048,  8,  8, 4096, &timing[2], },
-	{ 0xcc2c,  64, 2048, 16, 16, 4096, &timing[2], },
-	{ 0xba20,  64, 2048, 16, 16, 2048, &timing[3], },
+	{ 		0,	0,   0,    0,  0,  0,    0, &timing[0], },
+	{ "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, &timing[1], },
+	{ "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, &timing[1], },
+	{ "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, &timing[1], },
+	{ "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, &timing[2], },
+	{ "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, &timing[2], },
+	{ "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, 4096, &timing[2], },
+	{ "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, 4096, &timing[2], },
+	{ "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, &timing[3], },
 };

 static const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
@@ -275,23 +269,8 @@ static const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
 #define NDTR1_tWHR(c)	(min((c), 15) << 4)
 #define NDTR1_tAR(c)	(min((c), 15) << 0)

-#define tCH_NDTR0(r)	(((r) >> 19) & 0x7)
-#define tCS_NDTR0(r)	(((r) >> 16) & 0x7)
-#define tWH_NDTR0(r)	(((r) >> 11) & 0x7)
-#define tWP_NDTR0(r)	(((r) >> 8) & 0x7)
-#define tRH_NDTR0(r)	(((r) >> 3) & 0x7)
-#define tRP_NDTR0(r)	(((r) >> 0) & 0x7)
-
-#define tR_NDTR1(r)	(((r) >> 16) & 0xffff)
-#define tWHR_NDTR1(r)	(((r) >> 4) & 0xf)
-#define tAR_NDTR1(r)	(((r) >> 0) & 0xf)
-
 /* convert nano-seconds to nand flash controller clock cycles */
 #define ns2cycle(ns, clk)	(int)(((ns) * (clk / 1000000) / 1000) - 1)
-
-/* convert nand flash controller clock cycles to nano-seconds */
-#define cycle2ns(c, clk)	((((c) + 1) * 1000000 + clk / 500) / (clk / 1000))
-
 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
 				   const struct pxa3xx_nand_timing *t)
 {
@@ -803,7 +782,6 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,

 	/* calculate flash information */
 	info->page_size = f->page_size;
-	info->oob_buff = info->data_buff + f->page_size;
 	info->oob_size = (f->page_size == 2048) ? 64 : 16;
 	info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;

@@ -831,73 +809,14 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	return 0;
 }

-static void pxa3xx_nand_detect_timing(struct pxa3xx_nand_info *info,
-				      struct pxa3xx_nand_timing *t)
-{
-	unsigned long nand_clk = clk_get_rate(info->clk);
-	uint32_t ndtr0 = nand_readl(info, NDTR0CS0);
-	uint32_t ndtr1 = nand_readl(info, NDTR1CS0);
-
-	t->tCH = cycle2ns(tCH_NDTR0(ndtr0), nand_clk);
-	t->tCS = cycle2ns(tCS_NDTR0(ndtr0), nand_clk);
-	t->tWH = cycle2ns(tWH_NDTR0(ndtr0), nand_clk);
-	t->tWP = cycle2ns(tWP_NDTR0(ndtr0), nand_clk);
-	t->tRH = cycle2ns(tRH_NDTR0(ndtr0), nand_clk);
-	t->tRP = cycle2ns(tRP_NDTR0(ndtr0), nand_clk);
-
-	t->tR = cycle2ns(tR_NDTR1(ndtr1), nand_clk);
-	t->tWHR = cycle2ns(tWHR_NDTR1(ndtr1), nand_clk);
-	t->tAR = cycle2ns(tAR_NDTR1(ndtr1), nand_clk);
-}
-
 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 {
 	uint32_t ndcr = nand_readl(info, NDCR);
-	struct nand_flash_dev *type = NULL;
-	uint32_t id = -1;
-	int i;
-
-	default_flash.page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
-	default_flash.page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
-	default_flash.flash_width = ndcr & NDCR_DWIDTH_M ? 16 : 8;
-	default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;
-
-	/* set info fields needed to __readid */
-	info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
-	info->reg_ndcr = ndcr;
-
-
-	pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
-	id = *((uint16_t *)(info->data_buff));
-
-	/* Lookup the flash id */
-	id = (id >> 8) & 0xff;		/* device id is byte 2 */
-	for (i = 0; nand_flash_ids[i].name != NULL; i++) {
-		if (id == nand_flash_ids[i].id) {
-			type =  &nand_flash_ids[i];
-			break;
-		}
-	}
-
-	if (!type)
-		return -ENODEV;
-
-	/* fill the missing flash information */
-	i = __ffs(default_flash.page_per_block * default_flash.page_size);
-	default_flash.num_blocks = type->chipsize << (20 - i);
-
-	info->oob_size = (default_flash.page_size == 2048) ? 64 : 16;
-
-	/* calculate addressing information */
-	info->col_addr_cycles = (default_flash.page_size == 2048) ? 2 : 1;
-
-	if (default_flash.num_blocks * default_flash.page_per_block > 65536)
-		info->row_addr_cycles = 3;
-	else
-		info->row_addr_cycles = 2;

-	pxa3xx_nand_detect_timing(info, &default_timing);
-	memcpy(&default_flash.timing, &default_timing, sizeof(default_timing));
+	info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
+	info->reg_ndcr = ndcr & ~(NDCR_INT_MASK | NDCR_ECC_EN | NDCR_DMA_EN
| NDCR_ND_RUN);
+	info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
+	info->ndtr1cs0 = nand_readl(info, NDTR1CS0);

 	return 0;
 }
@@ -1006,14 +925,17 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 	struct pxa3xx_nand_info *info = mtd->priv;
 	struct platform_device *pdev = info->pdev;
 	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
+	struct nand_flash_dev pxa3xx_flash_ids[2] = {{NULL,}, {NULL,}};
 	const struct pxa3xx_nand_flash *f = NULL;
 	struct nand_chip *chip = mtd->priv;
 	uint32_t id = -1;
+	uint64_t chipsize;
 	int i, ret;

-	if (pdata->keep_config)
+	if (pdata->keep_config) {
 		if (pxa3xx_nand_detect_config(info) == 0)
-			return 0;
+			goto KEEP_CONFIG;
+	}

 	ret = pxa3xx_nand_sensing(info);
 	if (!ret) {
@@ -1043,22 +965,11 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 			f = &builtin_flash_types[i - pdata->num_flash + 1];

 		/* find the chip in default list */
-		if (f->chip_id == id) {
-			pxa3xx_nand_config_flash(info, f);
-			mtd->writesize = f->page_size;
-			mtd->writesize_shift = ffs(mtd->writesize) - 1;
-			mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
-			mtd->oobsize = mtd->writesize / 32;
-			mtd->erasesize = f->page_size * f->page_per_block;
-			mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
-			mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
-
-			mtd->name = mtd_names[0];
+		if (f->chip_id == id)
 			break;
-		}
 	}

-	if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash)) {
+	if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
 		kfree(mtd);
 		info->mtd = NULL;
 		printk(KERN_ERR "ERROR!! flash not defined!!!\n");
@@ -1066,20 +977,28 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 		return -EINVAL;
 	}

+	pxa3xx_nand_config_flash(info, f);
+	pxa3xx_flash_ids[0].name = f->name;
+	pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff;
+	pxa3xx_flash_ids[0].pagesize = f->page_size;
+	chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
+	pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
+	pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
+	pxa3xx_flash_ids[0].options = (f->flash_width == 16) ? NAND_BUSWIDTH_16 : 0;
+KEEP_CONFIG:
+	if (nand_scan_ident(mtd, 1, pxa3xx_flash_ids))
+		return -ENODEV;
+	/* calculate addressing information */
+	info->col_addr_cycles = (mtd->writesize >= 2048) ? 2 : 1;
+	info->oob_buff = info->data_buff + mtd->writesize;
+	if ((mtd->size >> chip->page_shift) > 65536)
+		info->row_addr_cycles = 3;
+	else
+		info->row_addr_cycles = 2;
+	mtd->name = mtd_names[0];
 	chip->ecc.mode = NAND_ECC_HW;
-	chip->ecc.size = f->page_size;
-	chip->chipsize 	= (uint64_t)f->num_blocks * f->page_per_block
-				* f->page_size;
-	mtd->size = chip->chipsize;
-
-	/* Calculate the address shift from the page size */
-	chip->page_shift = ffs(mtd->writesize) - 1;
-	chip->pagemask = mtd_div_by_ws(chip->chipsize, mtd) - 1;
-	chip->numchips = 1;
-	chip->bbt_erase_shift = chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
-
-	chip->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
-	chip->options |= NAND_NO_AUTOINCR;
+	chip->ecc.size = mtd->writesize;
+	chip->options = (info->reg_ndcr & NDCR_DWIDTH_M) ? NAND_BUSWIDTH_16: 0;
 	chip->options |= NAND_NO_READRDY;
 	chip->options |= NAND_USE_FLASH_BBT;

-- 
1.7.0.4


From kgene.kim at samsung.com  Fri Jun 18 01:36:56 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 18 Jun 2010 14:36:56 +0900
Subject: [PATCH] S5PV210 Correct clock source control register properties
In-Reply-To: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>
References: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <003301cb0ea8$474d1640$d5e742c0$%kim@samsung.com>

MyungJoo Ham wrote:
> 
> The clock source controls (struct clksrc_clk) have been often accessing
> CLK_GATE_IPx, which are for clock gating and are accessed by each clock
> as well as the clock source. This duplicated clock issue may incur
> lockup problems when there are two modules accessing the same clock with
> different names.
> 
Actually, S5V210/S5PC110 CLK_GATE_IPx can disable the clock operation of each
IP if it is not required. And this reduces dynamic power. CLK_SRC_MASKx is
used to control clock mux of each IP's SCLK.

Basically CLK_SRC_MASKx is for mux control (output masking) of each IP
source, and actually that can _not_ control relevant every source clock of
each IP. So CLK_GATE_IPx exists, can do it.

I know, in the several case, i.e, camera and fimc, each sclk_xxx need to
control. And can be controlled each sclk_xxx by using your patch, but in this
case, need to additional control relevant clock gating for dynamic clock
gating of each IP in its device driver.

> Besides, the clock source control is supposed to control (setting values
> of MASK, SRC, DIV), not to turn on/off individual clock.
> 
> Another point is that there are registers (CLK_SRC_MASK0/1) specialized
> for masking clock source control in S5PV210/S5PC110 according to the
> user manual (rev 20100201).
> 
> Therefore, accessing CLK_SRC_MASK0/1 (rather than accessing
> CLK_GATE_IPx) for the clock source control is safer and fits to the
> semantics of S5PV210/S5PC110 registers. And fortuneatly, each clock
> source defined in clock.c has corresponding bit at CLK_SRC_MASK0/1
> except for MFC, G2D, and G3D.
> 
> In this patch,
> 
> - DAC, HDMI, AUDIO 0/1/2, UCLK(uart) 0/1/2/3, MIXER, FIMC 0/1/2,
> FIMC, MMC 0/1/2/3, CSIS, SPI 0/1, PWI, and PWM clock sources are
> modified to use CLK_SRC_MASK0/1, which were using CLK_GATE_IPx.
> 
> - CAM 0/1 did not have enable/disable control. They now access
>   CLK_SRC_MASK0.
> 
> - MFC, G3D, G2D were using CLK_GATE_IPx. However, as there are no clocks
>   defined to control MFC, G3D, and G2D, we kept them to access
> CLK_GATE_IPx. These may need to be modified (erase .enable, .ctrlbit
> from sclk_mfc, sclk_g2d, sclk_g3d and create clocks: g3d, g2d, mfc)
> later.
> 
Hmm..need to check about multimedia usage.

And in my opinion, it would be helpful to understand that should be short and
clear.

> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> ---
>  arch/arm/mach-s5pv210/clock.c |  101
++++++++++++++++++++++-------------------
>  1 files changed, 55 insertions(+), 46 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> index ec5ad8c..08c1063 100644
> --- a/arch/arm/mach-s5pv210/clock.c
> +++ b/arch/arm/mach-s5pv210/clock.c
> @@ -183,6 +183,11 @@ static int s5pv210_clk_mask0_ctrl(struct clk *clk, int
enable)
>  	return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
>  }
> 
> +static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
> +{
> +	return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
> +}
> +
>  static struct clk clk_sclk_hdmi27m = {
>  	.name		= "sclk_hdmi27m",
>  	.id		= -1,
> @@ -497,8 +502,8 @@ static struct clksrc_clk clk_sclk_dac = {
>  	.clk		= {
>  		.name		= "sclk_dac",
>  		.id		= -1,
> -		.ctrlbit	= (1 << 10),
> -		.enable		= s5pv210_clk_ip1_ctrl,
> +		.ctrlbit	= (1 << 2),
> +		.enable		= s5pv210_clk_mask0_ctrl,
>  	},
>  	.sources	= &clkset_sclk_dac,
>  	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
> @@ -527,8 +532,8 @@ static struct clksrc_clk clk_sclk_hdmi = {
>  	.clk		= {
>  		.name		= "sclk_hdmi",
>  		.id		= -1,
> -		.enable		= s5pv210_clk_ip1_ctrl,
> -		.ctrlbit	= (1 << 11),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 0),
>  	},
>  	.sources	= &clkset_sclk_hdmi,
>  	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
> @@ -565,8 +570,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
>  	.clk		= {
>  		.name		= "sclk_audio",
>  		.id		= 0,
> -		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1 << 4),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 24),
>  	},
>  	.sources = &clkset_sclk_audio0,
>  	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
> @@ -594,8 +599,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
>  	.clk		= {
>  		.name		= "sclk_audio",
>  		.id		= 1,
> -		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1 << 5),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 25),
>  	},
>  	.sources = &clkset_sclk_audio1,
>  	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
> @@ -623,8 +628,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
>  	.clk		= {
>  		.name		= "sclk_audio",
>  		.id		= 2,
> -		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1 << 6),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 26),
>  	},
>  	.sources = &clkset_sclk_audio2,
>  	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
> @@ -680,8 +685,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "uclk1",
>  			.id		= 0,
> -			.ctrlbit	= (1<<17),
> -			.enable		= s5pv210_clk_ip3_ctrl,
> +			.ctrlbit	= (1 << 12),
> +			.enable		= s5pv210_clk_mask0_ctrl,
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
> @@ -690,8 +695,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "uclk1",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 18),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 13),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
> @@ -700,8 +705,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "uclk1",
>  			.id		= 2,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 19),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 14),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
> @@ -710,8 +715,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "uclk1",
>  			.id		= 3,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 20),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 15),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
> @@ -720,8 +725,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "sclk_mixer",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip1_ctrl,
> -			.ctrlbit	= (1 << 9),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 1),
>  		},
>  		.sources = &clkset_sclk_mixer,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
> @@ -738,8 +743,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "sclk_fimc",
>  			.id		= 0,
> -			.enable		= s5pv210_clk_ip0_ctrl,
> -			.ctrlbit	= (1 << 24),
> +			.enable		= s5pv210_clk_mask1_ctrl,
> +			.ctrlbit	= (1 << 2),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
> @@ -748,8 +753,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "sclk_fimc",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip0_ctrl,
> -			.ctrlbit	= (1 << 25),
> +			.enable		= s5pv210_clk_mask1_ctrl,
> +			.ctrlbit	= (1 << 3),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
> @@ -758,8 +763,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "sclk_fimc",
>  			.id		= 2,
> -			.enable		= s5pv210_clk_ip0_ctrl,
> -			.ctrlbit	= (1 << 26),
> +			.enable		= s5pv210_clk_mask1_ctrl,
> +			.ctrlbit	= (1 << 4),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
> @@ -768,6 +773,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_cam",
>  			.id		= 0,
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 3),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
> @@ -776,6 +783,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_cam",
>  			.id		= 1,
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 4),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
> @@ -784,8 +793,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_fimd",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip1_ctrl,
> -			.ctrlbit	= (1 << 0),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 5),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
> @@ -794,8 +803,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 0,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 16),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 8),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
> @@ -804,8 +813,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 17),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 9),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
> @@ -814,8 +823,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 2,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 18),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 10),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
> @@ -824,8 +833,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 3,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 19),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 11),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
> @@ -864,8 +873,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_csis",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip0_ctrl,
> -			.ctrlbit	= (1 << 31),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 6),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
> @@ -874,8 +883,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_spi",
>  			.id		= 0,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 12),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 16),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
> @@ -884,8 +893,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_spi",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 13),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 17),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
> @@ -894,8 +903,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_pwi",
>  			.id		= -1,
> -			.enable		= &s5pv210_clk_ip4_ctrl,
> -			.ctrlbit	= (1 << 2),
> +			.enable		= &s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 29),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
> @@ -904,8 +913,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_pwm",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 23),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 19),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
> --

I'm not sure that need to control of all sclk_xxx like above method, mux
output masking.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From haojian.zhuang at gmail.com  Fri Jun 18 01:37:05 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:37:05 +0800
Subject: [PATCH 17/25] pxa3xx_nand: use the buff passed from upper layer 
	directly if not use dma
Message-ID: <AANLkTimrtkwcaX8SF6w5D2acLa4tmo8gOr_DuuBsPaLX@mail.gmail.com>


From leiwen at marvell.com  Sun Jun  6 05:25:02 2010
From: leiwen at marvell.com (Lei Wen)
Date: Sun, 6 Jun 2010 17:25:02 +0800
Subject: [PATCH 17/25] pxa3xx_nand: use the buff passed from upper
Message-ID: <mailman.34.1276839531.27306.linux-arm-kernel@lists.infradead.org>

layer directly if not use dma

For dma enabling case, we couldn't avoid the memcpy, for the buffer
in the upper layer may not be the physical consecutive.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  300 ++++++++++++++++++++++++----------------
 1 files changed, 182 insertions(+), 118 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index bdcc881..67acea4 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -201,6 +201,7 @@ struct pxa3xx_nand_flash {
 struct pxa3xx_nand_info {
 	struct nand_chip	nand_chip;
 	/* page size of attached chip */
+	int			page_addr;
 	uint16_t		page_size;
 	uint8_t			chip_select;
 	uint8_t			use_ecc;
@@ -229,8 +230,8 @@ struct pxa3xx_nand {
 	int			drcmr_dat;
 	int			drcmr_cmd;
 	int 			data_dma_ch;
-	dma_addr_t 		data_buff_phys;
-	dma_addr_t 		data_desc_addr;
+	dma_addr_t 		dma_buff_phys;
+	dma_addr_t 		dma_desc_addr;
 	struct pxa_dma_desc	*data_desc;

 	struct pxa3xx_nand_info *info[NUM_CHIP_SELECT];
@@ -534,25 +535,25 @@ static void start_data_dma(struct pxa3xx_nand
*nand, int dir_out)
 	desc_oob->ddadr = desc->ddadr = DDADR_STOP;
 	desc_oob->dcmd = desc->dcmd = DCMD_WIDTH4 | DCMD_BURST32;
 	if (dir_out) {
-		desc->dsadr = nand->data_buff_phys + nand->data_column;
+		desc->dsadr = nand->dma_buff_phys + nand->data_column;
 		desc->dtadr = nand->mmio_phys + NDDB;
 		desc->dcmd |= DCMD_ENDIRQEN | DCMD_INCSRCADDR | DCMD_FLOWTRG |
(data_len + oob_len);
 	} else {
 		if (nand->oob_size > 0) {
-			desc_oob->dtadr = nand->data_buff_phys
+			desc_oob->dtadr = nand->dma_buff_phys
 					+ info->page_size + nand->oob_column;
 			desc_oob->dcmd |= DCMD_ENDIRQEN | DCMD_INCTRGADDR | DCMD_FLOWSRC | oob_len;
-			desc->ddadr = nand->data_desc_addr + sizeof(struct pxa_dma_desc);
+			desc->ddadr = nand->dma_desc_addr + sizeof(struct pxa_dma_desc);
 			desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC | data_len;
 		}
 		else
 			desc->dcmd |= DCMD_ENDIRQEN | DCMD_INCTRGADDR | DCMD_FLOWSRC | data_len;
-		desc->dtadr = nand->data_buff_phys + nand->data_column;
+		desc->dtadr = nand->dma_buff_phys + nand->data_column;
 		desc_oob->dsadr = desc->dsadr = nand->mmio_phys + NDDB;
 	}

 	DRCMR(nand->drcmr_dat) = DRCMR_MAPVLD | nand->data_dma_ch;
-	DDADR(nand->data_dma_ch) = nand->data_desc_addr;
+	DDADR(nand->data_dma_ch) = nand->dma_desc_addr;
 	DCSR(nand->data_dma_ch) |= DCSR_RUN;
 }

@@ -676,6 +677,8 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 	int addr_cycle, exec_cmd, ndcb0, i, chunks = 0;
 	struct mtd_info *mtd;
 	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
+	struct platform_device *pdev = nand->pdev;
+	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;

 	mtd = get_mtd_by_info(info);
 	ndcb0 = (nand->chip_select) ? NDCB0_CSEL : 0;;
@@ -685,37 +688,33 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 	/* reset data and oob column point to handle data */
 	nand->data_column	= 0;
 	nand->oob_column	= 0;
-	nand->buf_start		= 0;
-	nand->buf_count		= 0;
 	nand->total_cmds	= 1;
 	nand->cmd_seqs		= 0;
 	nand->data_size		= 0;
 	nand->oob_size		= 0;
-	nand->use_ecc		= 0;
 	nand->use_dma		= 0;
 	nand->state		= 0;
 	nand->bad_count		= 0;
 	nand->retcode		= ERR_NONE;
-	nand->command		= command;
+	nand->buf_start		= column;

 	switch (command) {
-	case NAND_CMD_READ0:
 	case NAND_CMD_PAGEPROG:
-		nand->use_ecc = info->use_ecc;
-	case NAND_CMD_READOOB:
+	case NAND_CMD_RNDOUT:
 		pxa3xx_set_datasize(info);
-		nand->oob_buff = nand->data_buff + nand->data_size;
 		nand->use_dma = use_dma;
 		chunks = info->page_size / nand->data_size;
 		break;
-	case NAND_CMD_SEQIN:
-		exec_cmd = 0;
-		break;
 	default:
 		nand->ndcb1 = 0;
 		nand->ndcb2 = 0;
+		nand->use_ecc = 0;
 		break;
 	}
+	if (nand->use_dma) {
+		nand->data_buff = nand->dma_buff;
+		nand->oob_buff = nand->dma_buff + mtd->writesize;
+	}

 	/* clear the command buffer */
 	for (i = 0; i < CMD_POOL_SIZE; i ++) {
@@ -726,68 +725,67 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 			+ info->col_addr_cycles);

 	switch (command) {
-	case NAND_CMD_READOOB:
 	case NAND_CMD_READ0:
-
-		cmd  = cmdset.read1;
-		if (command == NAND_CMD_READOOB)
-			nand->buf_start = mtd->writesize + column;
-		else
-			nand->buf_start = column;
-
-		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
-			nand->ndcb0[0] |= NDCB0_CMD_TYPE(0)
-					| addr_cycle
-					| (cmd & NDCB0_CMD1_MASK);
-		else {
-			if (chunks == 1)
-				nand->ndcb0[0] |= NDCB0_CMD_TYPE(0)
-						| NDCB0_DBC
-						| addr_cycle
-						| cmd;
-			else {
-				nand->total_cmds = chunks + 1;
-				nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x6)
-						| NDCB0_CMD_TYPE(0)
-						| NDCB0_DBC
-						| NDCB0_NC
-						| addr_cycle
-						| cmd;
-
-				nand->ndcb0[1] |= NDCB0_CMD_XTYPE(0x5)
-						| NDCB0_NC
-						| addr_cycle;
-
-				for (i = 2; i <= chunks; i ++)
-					nand->ndcb0[i] = nand->ndcb0[1];
-
-				nand->ndcb0[chunks] &= ~NDCB0_NC;
-				/* we should wait RnB go high again
-				 * before read out data*/
-				nand->wait_ready[1] = 1;
-			}
-		}
-
 	case NAND_CMD_SEQIN:
+		nand->use_ecc = info->use_ecc;
+	case NAND_CMD_READOOB:
+		memset(nand->data_buff, 0xff, column);
+		nand->buf_count = mtd->writesize + mtd->oobsize;
+		exec_cmd = 0;
+		info->page_addr = page_addr;
 		/* small page addr setting */
-		if (unlikely(info->page_size < PAGE_CHUNK_SIZE)) {
+		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
 			nand->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
 					| (column & 0xFF);
-
-			nand->ndcb2 = 0;
-		}
 		else {
 			nand->ndcb1 = ((page_addr & 0xFFFF) << 16)
 					| (column & 0xFFFF);

 			if (page_addr & 0xFF0000)
 				nand->ndcb2 = (page_addr & 0xFF0000) >> 16;
+		}
+		break;
+
+	case NAND_CMD_RNDOUT:
+		cmd = cmdset.read1;
+		if (nand->command == NAND_CMD_READOOB) {
+			nand->buf_start = mtd->writesize + column;
+			nand->buf_count = mtd->oobsize;
+		}
+
+		if (unlikely(info->page_size < PAGE_CHUNK_SIZE)
+			|| !(pdata->controller_attrs & PXA3XX_NAKED_CMD_EN)) {
+			if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
+				nand->ndcb0[0] |= NDCB0_CMD_TYPE(0)
+						| addr_cycle
+						| (cmd & NDCB0_CMD1_MASK);
 			else
-				nand->ndcb2 = 0;
+				nand->ndcb0[0] |= NDCB0_CMD_TYPE(0)
+						| NDCB0_DBC
+						| addr_cycle
+						| cmd;
+			break;
 		}

-		nand->buf_count = mtd->writesize + mtd->oobsize;
-		memset(nand->data_buff, 0xFF, nand->buf_count);
+		nand->total_cmds = chunks + 1;
+		nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x6)
+				| NDCB0_CMD_TYPE(0)
+				| NDCB0_DBC
+				| NDCB0_NC
+				| addr_cycle
+				| cmd;
+
+		nand->ndcb0[1] |= NDCB0_CMD_XTYPE(0x5)
+				| NDCB0_NC
+				| addr_cycle;
+
+		for (i = 2; i <= chunks; i ++)
+			nand->ndcb0[i] = nand->ndcb0[1];
+
+		nand->ndcb0[chunks] &= ~NDCB0_NC;
+		/* we should wait RnB go high again
+		 * before read out data*/
+		nand->wait_ready[1] = 1;

 		break;

@@ -799,40 +797,42 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,

 		cmd = cmdset.program;
 		nand->state |= STATE_IS_WRITE;
-		if (chunks == 1)
+		if (unlikely(info->page_size < PAGE_CHUNK_SIZE)
+			|| !(pdata->controller_attrs & PXA3XX_NAKED_CMD_EN)) {
 			nand->ndcb0[0] |= NDCB0_CMD_TYPE(0x1)
 					| NDCB0_AUTO_RS
 					| NDCB0_ST_ROW_EN
 					| NDCB0_DBC
 					| cmd
 					| addr_cycle;
-		else {
-			nand->total_cmds = chunks + 1;
-			nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x4)
-					| NDCB0_CMD_TYPE(0x1)
+			break;
+		}
+
+		nand->total_cmds = chunks + 1;
+		nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x4)
+				| NDCB0_CMD_TYPE(0x1)
+				| NDCB0_NC
+				| NDCB0_AUTO_RS
+				| (cmd & NDCB0_CMD1_MASK)
+				| addr_cycle;
+
+		for (i = 1; i < chunks; i ++)
+			nand->ndcb0[i] |= NDCB0_CMD_XTYPE(0x5)
 					| NDCB0_NC
 					| NDCB0_AUTO_RS
-					| (cmd & NDCB0_CMD1_MASK)
+					| NDCB0_CMD_TYPE(0x1)
 					| addr_cycle;

-			for (i = 1; i < chunks; i ++)
-				nand->ndcb0[i] |= NDCB0_CMD_XTYPE(0x5)
-						| NDCB0_NC
-						| NDCB0_AUTO_RS
-						| NDCB0_CMD_TYPE(0x1)
-						| addr_cycle;
-
-			nand->ndcb0[chunks] |= NDCB0_CMD_XTYPE(0x3)
-						| NDCB0_CMD_TYPE(0x1)
-						| NDCB0_ST_ROW_EN
-						| NDCB0_DBC
-						| (cmd & NDCB0_CMD2_MASK)
-						| NDCB0_CMD1_MASK
-						| addr_cycle;
-			/* we should wait for RnB goes high which
-			 * indicate the data has been written succesfully*/
-			nand->wait_ready[nand->total_cmds] = 1;
-		}
+		nand->ndcb0[chunks] |= NDCB0_CMD_XTYPE(0x3)
+				| NDCB0_CMD_TYPE(0x1)
+				| NDCB0_ST_ROW_EN
+				| NDCB0_DBC
+				| (cmd & NDCB0_CMD2_MASK)
+				| NDCB0_CMD1_MASK
+				| addr_cycle;
+		/* we should wait for RnB goes high which
+		 * indicate the data has been written succesfully*/
+		nand->wait_ready[nand->total_cmds] = 1;
 		break;

 	case NAND_CMD_READID:
@@ -847,6 +847,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,

 	case NAND_CMD_STATUS:
 		cmd = cmdset.read_status;
+		nand->data_buff = nand->dma_buff;
 		nand->buf_count = 1;
 		nand->ndcb0[0] |= NDCB0_CMD_TYPE(4)
 				| NDCB0_ADDR_CYC(1)
@@ -883,6 +884,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 		break;
 	}

+	nand->command = command;
 	return exec_cmd;
 }

@@ -1106,44 +1108,104 @@ static void free_cs_resource(struct
pxa3xx_nand_info *info, int cs)
 	nand->info[cs] = NULL;
 }

-static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
-		struct nand_chip *chip, uint8_t *buf, int page)
+static void pxa3xx_read_page(struct mtd_info *mtd, uint8_t *buf)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 	struct pxa3xx_nand *nand = info->nand_data;
+	int buf_blank;

-	chip->read_buf(mtd, buf, mtd->writesize);
-	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
-
-	if (nand->retcode == ERR_SBERR) {
+	nand->data_buff = buf;
+	nand->oob_buff = chip->oob_poi;
+	pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RNDOUT, 0, info->page_addr);
+	switch (nand->retcode) {
+	case ERR_SBERR:
 		switch (nand->use_ecc) {
 		case ECC_BCH:
 			if (nand->bad_count > BCH_THRESHOLD)
 				mtd->ecc_stats.corrected +=
 					(nand->bad_count - BCH_THRESHOLD);
 			break;
+
 		case ECC_HAMMIN:
 			mtd->ecc_stats.corrected ++;
+			break;
+
 		case ECC_NONE:
 		default:
 			break;
 		}
-	} else if (nand->retcode == ERR_DBERR) {
-		int buf_blank;
-
-		buf_blank = is_buf_blank(buf, mtd->writesize);
+		break;
+	case ERR_DBERR:
+		buf_blank = is_buf_blank(nand->data_buff, mtd->writesize);
 		if (!buf_blank)
 			mtd->ecc_stats.failed++;
+		break;
+	case ERR_NONE:
+		break;
+	default:
+		mtd->ecc_stats.failed++;
+		break;
 	}
+}

+static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
+		struct nand_chip *chip, uint8_t *buf, int page)
+{
+	pxa3xx_read_page(mtd, buf);
+	if (use_dma) {
+		chip->read_buf(mtd, buf, mtd->writesize);
+		chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+	}
+	return 0;
+}
+
+static int pxa3xx_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+		int page, int sndcmd)
+{
+	if (sndcmd) {
+		pxa3xx_nand_cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+		pxa3xx_read_page(mtd, chip->oob_poi);
+	}
+	if (use_dma)
+		chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 	return 0;
 }

 static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
 		struct nand_chip *chip, const uint8_t *buf)
 {
-	chip->write_buf(mtd, buf, mtd->writesize);
-	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;
+	if (use_dma) {
+		chip->write_buf(mtd, buf, mtd->writesize);
+		chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+	}
+	else {
+		nand->data_buff = (uint8_t *)buf;
+		nand->oob_buff = chip->oob_poi;
+	}
+}
+
+static int pxa3xx_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+			      int page)
+{
+	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;
+	int status = 0;
+
+	nand->data_buff = nand->dma_buff;
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+	if (use_dma)
+		chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+	else
+		nand->oob_buff = chip->oob_poi;
+	/* Send command to program the OOB data */
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+	status = chip->waitfunc(mtd, chip);
+
+	return status & NAND_STATUS_FAIL ? -EIO : 0;
 }

 static void pxa3xx_nand_erase_cmd(struct mtd_info *mtd, int page)
@@ -1191,8 +1253,8 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 		return -EINVAL;
 	}

+	nand->data_buff = (unsigned char *)&id;
 	chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
-	id = *((uint16_t *)(nand->data_buff));
 	if (id != 0)
 		dev_info(&nand->pdev->dev, "Detect a flash id %x\n", id);
 	else {
@@ -1349,7 +1411,11 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		chip = (struct nand_chip *)(&mtd[1]);
 		chip->controller        = &nand->controller;
 		chip->ecc.read_page	= pxa3xx_nand_read_page_hwecc;
+		chip->ecc.read_page_raw = pxa3xx_nand_read_page_hwecc;
+		chip->ecc.read_oob      = pxa3xx_nand_read_oob;
 		chip->ecc.write_page	= pxa3xx_nand_write_page_hwecc;
+		chip->ecc.write_page_raw= pxa3xx_nand_write_page_hwecc;
+		chip->ecc.write_oob     = pxa3xx_nand_write_oob;
 		chip->waitfunc		= pxa3xx_nand_waitfunc;
 		chip->select_chip	= pxa3xx_nand_select_chip;
 		chip->cmdfunc		= pxa3xx_nand_cmdfunc;
@@ -1361,25 +1427,16 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		chip->erase_cmd		= pxa3xx_nand_erase_cmd;
 	}

-	if (use_dma == 0) {
-		nand->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
-		if (nand->data_buff == NULL) {
-			ret = -ENOMEM;
-			goto fail_free_buf;
-		}
-		goto success_exit;
-	}
-
-	nand->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
-			&nand->data_buff_phys, GFP_KERNEL);
-	if (nand->data_buff == NULL) {
+	nand->dma_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
+			&nand->dma_buff_phys, GFP_KERNEL);
+	if (nand->dma_buff == NULL) {
 		dev_err(&pdev->dev, "failed to allocate dma buffer\n");
 		ret = -ENOMEM;
 		goto fail_free_buf;
 	}

-	nand->data_desc = (void *)nand->data_buff + data_desc_offset;
-	nand->data_desc_addr = nand->data_buff_phys + data_desc_offset;
+	nand->data_desc = (void *)nand->dma_buff + data_desc_offset;
+	nand->dma_desc_addr = nand->dma_buff_phys + data_desc_offset;
 	nand->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
 			pxa3xx_nand_data_dma_irq, nand);
 	if (nand->data_dma_ch < 0) {
@@ -1387,7 +1444,6 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		ret = -ENXIO;
 		goto fail_free_buf;
 	}
-success_exit:
 	return 0;

 fail_free_buf:
@@ -1437,6 +1493,14 @@ static int pxa3xx_nand_remove(struct
platform_device *pdev)
 		del_mtd_device(mtd);
 		free_cs_resource(info, cs);
 	}
+	if (nand->dma_buff_phys) {
+		if (nand->data_dma_ch >= 0)
+			pxa_free_dma(nand->data_dma_ch);
+		if (nand->dma_buff)
+			dma_free_coherent(&nand->pdev->dev, MAX_BUFF_SIZE,
+					nand->dma_buff, nand->dma_buff_phys);
+		nand->dma_buff_phys = 0;
+	}
 	return 0;
 }

-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:37:13 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:37:13 +0800
Subject: [PATCH 18/25] pxa3xx_nand: add ext id to distinguish different flash 
	with the same chip id
Message-ID: <AANLkTinf5DtfsXFrQagjrDFdBk3YnqD9kNJFlaPjJt9-@mail.gmail.com>


From leiwen at marvell.com  Sun Jun  6 21:24:11 2010
From: leiwen at marvell.com (Lei Wen)
Date: Mon, 7 Jun 2010 09:24:11 +0800
Subject: [PATCH 18/25] pxa3xx_nand: add ext id to distinguish
Message-ID: <mailman.36.1276839542.27306.linux-arm-kernel@lists.infradead.org>

different flash with the same chip id

For K9LBG08U0M and K9LBG08UXD two nand chip, they have the same chip id as
0xd7ec. So we should use the ext id to distinguish them.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |   35 ++++++++++++++++++-----------------
 1 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 67acea4..e4ccf7c 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -188,7 +188,8 @@ struct pxa3xx_nand_cmdset {

 struct pxa3xx_nand_flash {
 	char		*name;
-	uint32_t	chip_id;
+	uint16_t	chip_id;
+	uint16_t	ext_id;
 	uint16_t	page_per_block; /* Pages per block */
 	uint16_t 	page_size;	/* Page size in bytes */
 	uint8_t		flash_width;	/* Width of Flash memory (DWIDTH_M) */
@@ -292,17 +293,17 @@ static struct pxa3xx_nand_timing __devinitdata
timing[] = {
 };

 static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
-{ 		0,	0,   0,    0,  0,  0, ECC_NONE,      0, &timing[0], },
-{ "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, ECC_HAMMIN, 4096, &timing[1], },
-{ "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, ECC_HAMMIN, 2048, &timing[1], },
-{ "1GiB 8-bit",    0xd3ec, 128, 2048,  8,  8, ECC_BCH,    4096, &timing[1], },
-{ "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, ECC_BCH,    8192, &timing[1], },
-{ "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, ECC_HAMMIN, 1024, &timing[2], },
-{ "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, ECC_HAMMIN, 1024, &timing[2], },
-{ "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, ECC_HAMMIN, 4096, &timing[2], },
-{ "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, ECC_HAMMIN, 4096, &timing[2], },
-{ "1GiB 8-bit",    0x382c, 128, 4096,  8,  8, ECC_BCH,    2048, &timing[2], },
-{ "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, ECC_HAMMIN, 2048, &timing[3], },
+{ 		0,	0,	0,   0,	   0,  0,  0, ECC_NONE,      0, &timing[0], },
+{ "64MiB 16-bit",  0x46ec, 0xffff,  32,  512, 16, 16, ECC_HAMMIN,
4096, &timing[1], },
+{ "256MiB 8-bit",  0xdaec, 0xffff,  64, 2048,  8,  8, ECC_HAMMIN,
2048, &timing[1], },
+{ "1GiB 8-bit",    0xd3ec, 0xffff, 128, 2048,  8,  8, ECC_BCH,
4096, &timing[1], },
+{ "4GiB 8-bit",    0xd7ec, 0x29d5, 128, 4096,  8,  8, ECC_BCH,
8192, &timing[1], },
+{ "128MiB 8-bit",  0xa12c, 0xffff,  64, 2048,  8,  8, ECC_HAMMIN,
1024, &timing[2], },
+{ "128MiB 16-bit", 0xb12c, 0xffff,  64, 2048, 16, 16, ECC_HAMMIN,
1024, &timing[2], },
+{ "512MiB 8-bit",  0xdc2c, 0xffff,  64, 2048,  8,  8, ECC_HAMMIN,
4096, &timing[2], },
+{ "512MiB 16-bit", 0xcc2c, 0xffff,  64, 2048, 16, 16, ECC_HAMMIN,
4096, &timing[2], },
+{ "1GiB 8-bit",    0x382c, 0xffff, 128, 4096,  8,  8, ECC_BCH,
2048, &timing[2], },
+{ "256MiB 16-bit", 0xba20, 0xffff,  64, 2048, 16, 16, ECC_HAMMIN,
2048, &timing[3], },
 };

 static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
@@ -1237,7 +1238,7 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 	struct nand_flash_dev pxa3xx_flash_ids[2] = {{NULL,}, {NULL,}};
 	const struct pxa3xx_nand_flash *f = NULL;
 	struct nand_chip *chip = mtd->priv;
-	uint32_t id = -1;
+	uint16_t id[2];
 	uint64_t chipsize;
 	int i, ret;

@@ -1253,10 +1254,10 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 		return -EINVAL;
 	}

-	nand->data_buff = (unsigned char *)&id;
+	nand->data_buff = (unsigned char *)id;
 	chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
-	if (id != 0)
-		dev_info(&nand->pdev->dev, "Detect a flash id %x\n", id);
+	if (id[0] != 0)
+		dev_info(&nand->pdev->dev, "Detect a flash id %x\n", id[0]);
 	else {
 		dev_warn(&nand->pdev->dev, "Read out ID 0, potential timing set wrong!!\n");
 		free_cs_resource(info, nand->chip_select);
@@ -1270,7 +1271,7 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 			f = &builtin_flash_types[i - pdata->num_flash + 1];

 		/* find the chip in default list */
-		if (f->chip_id == id)
+		if ((f->chip_id == id[0]) && ((f->ext_id & id[1]) == id[1]))
 			break;
 	}

-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:37:37 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:37:37 +0800
Subject: [PATCH 21/25] pxa3xx_nand: add polling mode support
Message-ID: <AANLkTimyukBDuRU86Q8iegluZ5WsGKxqB0_5DuSBYGaC@mail.gmail.com>


From leiwen at marvell.com  Tue Jun  8 03:10:41 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 8 Jun 2010 15:10:41 +0800
Subject: [PATCH 21/25] pxa3xx_nand: add polling mode support
Message-ID: <mailman.40.1276839563.27306.linux-arm-kernel@lists.infradead.org>

Add polling mode to facilitate debugging.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa3xx_nand.h |    1 +
 drivers/mtd/nand/pxa3xx_nand.c               |   55 +++++++++++++++++++++----
 2 files changed, 47 insertions(+), 9 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index 72bb70e..ae63a5f 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -17,6 +17,7 @@
  * enable such tuning for those platform which support it */
 #define PXA3XX_ADV_TIME_TUNING	(1 << 4)
 #define PXA3XX_KEEP_CONFIG	(1 << 5)
+#define PXA3XX_POOLING_MODE	(1 << 6)
 struct pxa3xx_nand_platform_data {
 	unsigned int				controller_attrs;
 	const struct mtd_partition		*parts[NUM_CHIP_SELECT];
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 834422d..7f8bae7 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -274,6 +274,10 @@ static int use_dma = 1;
 module_param(use_dma, bool, 0444);
 MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");

+static int use_polling = 0;
+module_param(use_polling, bool, 0444);
+MODULE_PARM_DESC(use_polling, "Use full polling mode");
+
 const static struct pxa3xx_nand_cmdset cmdset = {
 	.read1		= 0x3000,
 	.read2		= 0x0050,
@@ -444,6 +448,7 @@ static void pxa3xx_nand_start(struct pxa3xx_nand *nand)
 	info = nand->info[nand->chip_select];
 	ndcr = info->reg_ndcr;
 	ndcr |= nand->use_dma ? NDCR_DMA_EN : 0;
+	ndcr |= use_polling ? NDCR_INT_MASK : 0;
 	ndcr |= NDCR_ND_RUN;

 	switch (nand->ecc_strength) {
@@ -615,9 +620,8 @@ static void pxa3xx_nand_data_dma_irq(int channel,
void *data)
 	nand_writel(nand, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
 }

-static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
+static int pxa3xx_nand_transaction(struct pxa3xx_nand *nand)
 {
-	struct pxa3xx_nand *nand = devid;
 	struct pxa3xx_nand_info *info;
 	unsigned int status, is_completed = 0, cs, cmd_seqs, ndcb1, ndcb2;
 	unsigned int ready, cmd_done, page_done, badblock_detect;
@@ -654,13 +658,20 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 	if (status & ready) {
 		nand->state |= STATE_READY;
 		if (nand->wait_ready[cmd_seqs]) {
-			enable_int(nand, NDCR_WRCMDREQM);
+			if (!use_polling)
+				enable_int(nand, NDCR_WRCMDREQM | NDCR_CS0_CMDDM
+						| NDCR_CS1_CMDDM);
 			if (cmd_seqs == nand->total_cmds)
 				is_completed = 1;
 		}
 	}
 	if (status & cmd_done) {
 		nand->state |= STATE_CMD_DONE;
+		if (nand->wait_ready[cmd_seqs] && !(nand->state & STATE_READY)) {
+			status &= ~cmd_done;
+			if (!use_polling)
+				disable_int(nand, NDCR_CS0_CMDDM | NDCR_CS1_CMDDM);
+		}
 		if (cmd_seqs == nand->total_cmds && !nand->wait_ready[cmd_seqs])
 			is_completed = 1;
 	}
@@ -668,7 +679,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 	if (status & NDSR_WRCMDREQ) {
 		status &= ~NDSR_WRCMDREQ;
 		if (nand->wait_ready[cmd_seqs] && !(nand->state & STATE_READY)) {
-			disable_int(nand, NDCR_WRCMDREQM);
+			if (!use_polling)
+				disable_int(nand, NDCR_WRCMDREQM);
 			goto IRQ_FORCE_EXIT;
 		}

@@ -698,12 +710,32 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 IRQ_FORCE_EXIT:
 	/* clear NDSR to let the controller exit the IRQ */
 	nand_writel(nand, NDSR, status);
-	if (is_completed)
-		complete(&nand->cmd_complete);
 NORMAL_IRQ_EXIT:
+	return is_completed;
+}
+
+static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
+{
+	struct pxa3xx_nand *nand = devid;
+	if (pxa3xx_nand_transaction(nand))
+		complete(&nand->cmd_complete);
 	return IRQ_HANDLED;
 }

+static int pxa3xx_nand_polling(struct pxa3xx_nand *nand, unsigned long timeout)
+{
+	int i, ret = 0;
+
+	for (i = 0; i < timeout; i++) {
+		ret = pxa3xx_nand_transaction(nand);
+		if (ret)
+			break;
+		udelay(10);
+	}
+
+	return ret;
+}
+
 static inline int is_buf_blank(uint8_t *buf, size_t len)
 {
 	for (; len > 0; len--)
@@ -973,8 +1005,11 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 		nand->state |= STATE_CMD_PREPARED;
 		pxa3xx_nand_start(nand);

-		ret = wait_for_completion_timeout(&nand->cmd_complete,
-				CHIP_DELAY_TIMEOUT);
+		if (!use_polling)
+			ret = wait_for_completion_timeout(&nand->cmd_complete,
+					CHIP_DELAY_TIMEOUT);
+		else
+			ret = pxa3xx_nand_polling(nand, CHIP_DELAY_TIMEOUT);
 		if (!ret) {
 			dev_err(&nand->pdev->dev, "Wait time out!!!\n");
 			nand_error_dump(nand);
@@ -1582,7 +1617,9 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 		return -ENODEV;
 	}

-	if (!(pdata->controller_attrs & PXA3XX_DMA_EN))
+	if (pdata->controller_attrs & PXA3XX_POOLING_MODE)
+		use_polling = 1;
+	if (!(pdata->controller_attrs & PXA3XX_DMA_EN) || use_polling)
 		use_dma = 0;
 	ret = alloc_nand_resource(pdev);
 	if (ret)
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:37:47 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:37:47 +0800
Subject: [PATCH 22/25] pxa3xx_nand: reimplement the read oob logic
Message-ID: <AANLkTikqS9j4uRQ_8nzKTPnbpnoHHH_LzTdi3CQTlC8U@mail.gmail.com>


From leiwen at marvell.com  Tue Jun  8 04:37:35 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 8 Jun 2010 16:37:35 +0800
Subject: [PATCH 22/25] pxa3xx_nand: reimplement the read oob logic
Message-ID: <mailman.42.1276839578.27306.linux-arm-kernel@lists.infradead.org>

For readoob command only need the content of oob part, it certainly
don't need the controller transfer the data part, which greatly downgrade
the performance.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  182 +++++++++++++++++++++-------------------
 1 files changed, 96 insertions(+), 86 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 7f8bae7..e76264c 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -244,30 +244,28 @@ struct pxa3xx_nand {
 	uint32_t		command;
 	uint16_t		data_size;	/* data size in FIFO */
 	uint16_t		oob_size;
-	uint32_t		bad_count;
 	unsigned char		*dma_buff;
 	unsigned char		*data_buff;
 	unsigned char		*oob_buff;
+	uint8_t			chip_select;
+	uint8_t			total_cmds;
 	uint32_t		buf_start;
 	uint32_t		buf_count;
+
+	uint32_t		state;
+	uint32_t		bad_count;
 	uint16_t		data_column;
 	uint16_t		oob_column;
-
-	/* relate to the command */
-	uint8_t			chip_select;
-	uint8_t			ecc_strength;
-	unsigned int		state;
 	int			use_dma;	/* use DMA ? */
 	int 			retcode;
+	uint8_t			ecc_strength;

 	/* cached register value */
 	uint8_t			cmd_seqs;
-	uint8_t			total_cmds;
 	uint8_t			wait_ready[CMD_POOL_SIZE];
 	uint32_t		ndcb0[CMD_POOL_SIZE];
-	uint32_t		ndcb1;
+	uint32_t		ndcb1[CMD_POOL_SIZE];
 	uint32_t		ndcb2;
-	uint32_t		ndcb3[CMD_POOL_SIZE];
 };

 static int use_dma = 1;
@@ -396,8 +394,8 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
 	struct pxa3xx_nand *nand = info->nand_data;
 	int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;

-	if (info->page_size >= PAGE_CHUNK_SIZE) {
-		nand->data_size = PAGE_CHUNK_SIZE;
+	if (info->page_size < PAGE_CHUNK_SIZE) {
+		nand->data_size = 512;
 		if (!oob_enable) {
 			nand->oob_size = 0;
 			return;
@@ -405,32 +403,54 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)

 		switch (nand->ecc_strength) {
 		case 0:
-			nand->oob_size = 64;
+			nand->oob_size = 16;
 			break;
 		case HAMMING_STRENGTH:
-			nand->oob_size = 40;
+			nand->oob_size = 8;
 			break;
 		default:
-			nand->oob_size = 32;
-		}
-	} else {
-		nand->data_size = 512;
-		if (!oob_enable) {
-			nand->oob_size = 0;
-			return;
+			printk("Don't support BCH on small page device!!!\n");
+			BUG();
 		}
+		return;
+	}
+	nand->data_size = PAGE_CHUNK_SIZE;
+	if (!oob_enable) {
+		nand->oob_size = 0;
+		return;
+	}

-		switch (nand->ecc_strength) {
-		case 0:
-			nand->oob_size = 16;
-			break;
+	if (nand->command == NAND_CMD_READOOB) {
+		switch (info->ecc_strength) {
 		case HAMMING_STRENGTH:
-			nand->oob_size = 8;
+			nand->ndcb1[3] = 2 * PAGE_CHUNK_SIZE + OOB_CHUNK_SIZE;
+			nand->data_size = 40;
+			break;
+		case BCH_STRENGTH:
+			nand->ndcb1[3] = 2 * PAGE_CHUNK_SIZE + OOB_CHUNK_SIZE - 2;
+			nand->data_size = 32;
 			break;
 		default:
-			printk("Don't support BCH on small page device!!!\n");
 			BUG();
 		}
+		if (info->reg_ndcr & NDCR_DWIDTH_M) {
+			nand->ndcb1[1] = PAGE_CHUNK_SIZE / 2;
+			nand->ndcb1[3] /= 2;
+		}
+		else
+			nand->ndcb1[1] = PAGE_CHUNK_SIZE;
+		nand->oob_size = 0;
+		return;
+	}
+	switch (nand->ecc_strength) {
+	case 0:
+		nand->oob_size = 64;
+		break;
+	case HAMMING_STRENGTH:
+		nand->oob_size = 40;
+		break;
+	default:
+		nand->oob_size = 32;
 	}
 }

@@ -514,9 +534,8 @@ static void nand_error_dump(struct pxa3xx_nand *nand)
 	printk(KERN_ERR "Totally %d command for sending\n",
 			nand->total_cmds);
 	for (i = 0; i < nand->total_cmds; i ++)
-		printk(KERN_ERR "NDCB0:%d: %x\n",
-				i, nand->ndcb0[i]);
-	printk(KERN_ERR "NDCB1: %x; NDCB2 %x\n", nand->ndcb1, nand->ndcb2);
+		printk(KERN_ERR "%d::NDCB0: %x, NDCB1: %x, NDCB2: %x\n",
+			i, nand->ndcb0[i], nand->ndcb1[i], nand->ndcb2);

 	printk(KERN_ERR "\nRegister DUMPing ##############\n");
 	printk(KERN_ERR "NDCR %x\n"
@@ -623,8 +642,8 @@ static void pxa3xx_nand_data_dma_irq(int channel,
void *data)
 static int pxa3xx_nand_transaction(struct pxa3xx_nand *nand)
 {
 	struct pxa3xx_nand_info *info;
-	unsigned int status, is_completed = 0, cs, cmd_seqs, ndcb1, ndcb2;
-	unsigned int ready, cmd_done, page_done, badblock_detect;
+	unsigned int status, is_completed = 0, cs, cmd_seqs;
+	unsigned int ready, cmd_done, page_done, badblock_detect, ndcb2;

 	cs		= nand->chip_select;
 	ready           = (cs) ? NDSR_RDY : NDSR_FLASH_RDY;
@@ -686,22 +705,19 @@ static int pxa3xx_nand_transaction(struct
pxa3xx_nand *nand)

 		nand_writel(nand, NDSR, NDSR_WRCMDREQ);
 		if (cmd_seqs < nand->total_cmds) {
-			nand->cmd_seqs ++;
-			if (cmd_seqs == 0) {
-				ndcb1 = nand->ndcb1;
+			if (cmd_seqs == 0)
 				ndcb2 = nand->ndcb2;
-			}
-			else {
-				ndcb1 = 0;
+			else
 				ndcb2 = 0;
-			}
+			nand->cmd_seqs ++;
 			nand->state &= ~STATE_MASK;
 			nand->state |= STATE_CMD_WAIT_DONE;
 			nand_writel(nand, NDCB0, nand->ndcb0[cmd_seqs]);
-			nand_writel(nand, NDCB0, ndcb1);
+			nand_writel(nand, NDCB0, nand->ndcb1[cmd_seqs]);
 			nand_writel(nand, NDCB0, ndcb2);
-			if (nand->ndcb3[cmd_seqs])
-				nand_writel(nand, NDCB0, nand->ndcb3[cmd_seqs]);
+			if (nand->ndcb0[cmd_seqs] & NDCB0_LEN_OVRD)
+				nand_writel(nand, NDCB0, nand->data_size
+						+ nand->oob_size);
 		}
 		else
 			is_completed = 1;
@@ -760,24 +776,15 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 	exec_cmd = 1;

 	/* reset data and oob column point to handle data */
-	nand->data_column	= 0;
-	nand->oob_column	= 0;
-	nand->total_cmds	= 1;
-	nand->cmd_seqs		= 0;
-	nand->data_size		= 0;
-	nand->oob_size		= 0;
-	nand->use_dma		= 0;
-	nand->state		= 0;
-	nand->bad_count		= 0;
-	nand->retcode		= ERR_NONE;
-	nand->buf_start		= column;
+	nand->total_cmds = 1;
+	nand->buf_start	= column;

 	switch (command) {
 	case NAND_CMD_PAGEPROG:
 	case NAND_CMD_RNDOUT:
 		pxa3xx_set_datasize(info);
 		nand->use_dma = use_dma;
-		chunks = info->page_size / nand->data_size;
+		chunks = info->page_size / PAGE_CHUNK_SIZE;
 		if (info->ecc_strength > BCH_STRENGTH) {
 			i = info->ecc_strength / BCH_STRENGTH;
 			nand->data_size /= i;
@@ -792,9 +799,8 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 			BUG();
 		}
 	default:
-		nand->ndcb1 = 0;
-		nand->ndcb2 = 0;
-		nand->ecc_strength = 0;
+		i = (uint32_t)(&nand->state) - (uint32_t)nand;
+		memset(&nand->state, 0, sizeof(struct pxa3xx_nand) - i);
 		break;
 	}
 	if (nand->use_dma) {
@@ -803,11 +809,8 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 	}

 	/* clear the command buffer */
-	for (i = 0; i < CMD_POOL_SIZE; i ++) {
+	for (i = 0; i < CMD_POOL_SIZE; i ++)
 		nand->ndcb0[i] = ndcb0;
-		nand->wait_ready[i] = 0;
-		nand->ndcb3[i] = (ndcb0 & NDCB0_LEN_OVRD)? nand->data_size : 0;
-	}
 	addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
 			+ info->col_addr_cycles);

@@ -822,10 +825,10 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 		info->page_addr = page_addr;
 		/* small page addr setting */
 		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
-			nand->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
+			nand->ndcb1[0] = ((page_addr & 0xFFFFFF) << 8)
 					| (column & 0xFF);
 		else {
-			nand->ndcb1 = ((page_addr & 0xFFFF) << 16)
+			nand->ndcb1[0] = ((page_addr & 0xFFFF) << 16)
 					| (column & 0xFFFF);

 			if (page_addr & 0xFF0000)
@@ -835,11 +838,6 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,

 	case NAND_CMD_RNDOUT:
 		cmd = cmdset.read1;
-		if (nand->command == NAND_CMD_READOOB) {
-			nand->buf_start = mtd->writesize + column;
-			nand->buf_count = mtd->oobsize;
-		}
-
 		if (unlikely(info->page_size < PAGE_CHUNK_SIZE)
 			|| !(pdata->controller_attrs & PXA3XX_NAKED_CMD_EN)) {
 			if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
@@ -851,10 +849,18 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 						| NDCB0_DBC
 						| addr_cycle
 						| cmd;
+			if (nand->command == NAND_CMD_READOOB) {
+				nand->buf_start = mtd->writesize + column;
+				nand->buf_count = mtd->oobsize;
+			}
 			break;
 		}

-		nand->total_cmds = chunks + 1;
+		if (nand->command == NAND_CMD_READOOB)
+			nand->total_cmds = 2 * chunks + 1;
+		else
+			nand->total_cmds = chunks + 1;
+
 		nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x6)
 				| NDCB0_CMD_TYPE(0)
 				| NDCB0_DBC
@@ -862,15 +868,23 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 				| addr_cycle
 				| cmd;
 		nand->ndcb0[0] &= ~NDCB0_LEN_OVRD;
-		nand->ndcb3[0] = 0;
-		nand->ndcb0[1] |= NDCB0_CMD_XTYPE(0x5)
-				| NDCB0_NC
-				| addr_cycle;

-		for (i = 2; i <= chunks; i ++)
-			nand->ndcb0[i] = nand->ndcb0[1];
+		for (i = 1; i <= nand->total_cmds - 1;) {
+			if (nand->command == NAND_CMD_READOOB) {
+				nand->ndcb0[i ++] |= NDCB0_CMD_XTYPE(0x6)
+						| NDCB0_CMD_TYPE(0)
+						| NDCB0_ADDR_CYC(info->col_addr_cycles)
+						| NDCB0_DBC
+						| NDCB0_NC
+						| (NAND_CMD_RNDOUTSTART << 8)
+						| NAND_CMD_RNDOUT;
+				nand->ndcb0[i] |= NDCB0_LEN_OVRD;
+			}
+			nand->ndcb0[i ++] |= NDCB0_CMD_XTYPE(0x5)
+					| NDCB0_NC;
+		}

-		nand->ndcb0[chunks] &= ~NDCB0_NC;
+		nand->ndcb0[nand->total_cmds - 1] &= ~NDCB0_NC;
 		/* we should wait RnB go high again
 		 * before read out data*/
 		nand->wait_ready[1] = 1;
@@ -908,18 +922,15 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 			nand->ndcb0[i] |= NDCB0_CMD_XTYPE(0x5)
 					| NDCB0_NC
 					| NDCB0_AUTO_RS
-					| NDCB0_CMD_TYPE(0x1)
-					| addr_cycle;
+					| NDCB0_CMD_TYPE(0x1);

 		nand->ndcb0[chunks] |= NDCB0_CMD_XTYPE(0x3)
-				| NDCB0_CMD_TYPE(0x1)
-				| NDCB0_ST_ROW_EN
-				| NDCB0_DBC
-				| (cmd & NDCB0_CMD2_MASK)
-				| NDCB0_CMD1_MASK
-				| addr_cycle;
+					| NDCB0_CMD_TYPE(0x1)
+					| NDCB0_ST_ROW_EN
+					| NDCB0_DBC
+					| (cmd & NDCB0_CMD2_MASK)
+					| NDCB0_CMD1_MASK;
 		nand->ndcb0[chunks] &= ~NDCB0_LEN_OVRD;
-		nand->ndcb3[chunks] = 0;
 		/* we should wait for RnB goes high which
 		 * indicate the data has been written succesfully*/
 		nand->wait_ready[nand->total_cmds] = 1;
@@ -953,8 +964,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 				| NDCB0_ADDR_CYC(3)
 				| NDCB0_DBC
 				| cmd;
-		nand->ndcb1 = page_addr;
-		nand->ndcb2 = 0;
+		nand->ndcb1[0] = page_addr;

 		break;
 	case NAND_CMD_RESET:
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:37:20 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:37:20 +0800
Subject: [PATCH 19/25] pxa3xx_nand: support ecc requirement higher than 4bit 
	per 512 bytes
Message-ID: <AANLkTimSs22EFQRYNTEEOv4YSlwNRKaWReOfVHINJ2Vj@mail.gmail.com>


From leiwen at marvell.com  Mon Jun  7 03:13:50 2010
From: leiwen at marvell.com (Lei Wen)
Date: Mon, 7 Jun 2010 15:13:50 +0800
Subject: [PATCH 19/25] pxa3xx_nand: support ecc requirement higher
Message-ID: <mailman.44.1276839588.27306.linux-arm-kernel@lists.infradead.org>

than 4bit per 512 bytes

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  118 ++++++++++++++++++++++++----------------
 1 files changed, 71 insertions(+), 47 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index e4ccf7c..04bf875 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -33,6 +33,8 @@
 #define BCH_THRESHOLD           (8)
 #define CMD_POOL_SIZE           (5)
 #define READ_ID_BYTES		(4)
+#define BCH_STRENGTH		(4)
+#define HAMMING_STRENGTH	(1)

 /* registers and bit definitions */
 #define NDCR		(0x00) /* Control register */
@@ -84,9 +86,9 @@
 #define NDCR_RDDREQM            (0x1 << 1)
 #define NDCR_WRCMDREQM          (0x1)

+#define NDSR_MASK		(0xffffffff)
 #define NDSR_ERR_CNT_MASK       (0x1F << 16)
 #define NDSR_ERR_CNT(x)         (((x) << 16) & NDSR_ERR_CNT_MASK)
-#define NDSR_MASK		(0xfff)
 #define NDSR_RDY                (0x1 << 12)
 #define NDSR_FLASH_RDY          (0x1 << 11)
 #define NDSR_CS0_PAGED		(0x1 << 10)
@@ -103,6 +105,7 @@

 #define NDCB0_CMD_XTYPE_MASK    (0x7 << 29)
 #define NDCB0_CMD_XTYPE(x)      (((x) << 29) & NDCB0_CMD_XTYPE_MASK)
+#define NDCB0_LEN_OVRD		(0x1 << 28)
 #define NDCB0_ST_ROW_EN         (0x1 << 26)
 #define NDCB0_AUTO_RS		(0x1 << 25)
 #define NDCB0_CSEL		(0x1 << 24)
@@ -194,7 +197,7 @@ struct pxa3xx_nand_flash {
 	uint16_t 	page_size;	/* Page size in bytes */
 	uint8_t		flash_width;	/* Width of Flash memory (DWIDTH_M) */
 	uint8_t 	dfc_width;	/* Width of flash controller(DWIDTH_C) */
-	uint8_t		ecc_type;	/* Which ECC is applied */
+	uint8_t		ecc_strength;	/* How strong a ecc should be applied */
 	uint32_t	num_blocks;	/* Number of physical blocks in Flash */
 	struct pxa3xx_nand_timing *timing;	/* NAND Flash timing */
 };
@@ -205,7 +208,7 @@ struct pxa3xx_nand_info {
 	int			page_addr;
 	uint16_t		page_size;
 	uint8_t			chip_select;
-	uint8_t			use_ecc;
+	uint8_t			ecc_strength;

 	/* calculated from pxa3xx_nand_flash data */
 	uint8_t			col_addr_cycles;
@@ -250,8 +253,8 @@ struct pxa3xx_nand {

 	/* relate to the command */
 	uint8_t			chip_select;
+	uint8_t			ecc_strength;
 	unsigned int		state;
-	int			use_ecc;	/* use HW ECC ? */
 	int			use_dma;	/* use DMA ? */
 	int 			retcode;

@@ -262,6 +265,7 @@ struct pxa3xx_nand {
 	uint32_t		ndcb0[CMD_POOL_SIZE];
 	uint32_t		ndcb1;
 	uint32_t		ndcb2;
+	uint32_t		ndcb3[CMD_POOL_SIZE];
 };

 static int use_dma = 1;
@@ -293,17 +297,17 @@ static struct pxa3xx_nand_timing __devinitdata
timing[] = {
 };

 static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
-{ 		0,	0,	0,   0,	   0,  0,  0, ECC_NONE,      0, &timing[0], },
-{ "64MiB 16-bit",  0x46ec, 0xffff,  32,  512, 16, 16, ECC_HAMMIN,
4096, &timing[1], },
-{ "256MiB 8-bit",  0xdaec, 0xffff,  64, 2048,  8,  8, ECC_HAMMIN,
2048, &timing[1], },
-{ "1GiB 8-bit",    0xd3ec, 0xffff, 128, 2048,  8,  8, ECC_BCH,
4096, &timing[1], },
-{ "4GiB 8-bit",    0xd7ec, 0x29d5, 128, 4096,  8,  8, ECC_BCH,
8192, &timing[1], },
-{ "128MiB 8-bit",  0xa12c, 0xffff,  64, 2048,  8,  8, ECC_HAMMIN,
1024, &timing[2], },
-{ "128MiB 16-bit", 0xb12c, 0xffff,  64, 2048, 16, 16, ECC_HAMMIN,
1024, &timing[2], },
-{ "512MiB 8-bit",  0xdc2c, 0xffff,  64, 2048,  8,  8, ECC_HAMMIN,
4096, &timing[2], },
-{ "512MiB 16-bit", 0xcc2c, 0xffff,  64, 2048, 16, 16, ECC_HAMMIN,
4096, &timing[2], },
-{ "1GiB 8-bit",    0x382c, 0xffff, 128, 4096,  8,  8, ECC_BCH,
2048, &timing[2], },
-{ "256MiB 16-bit", 0xba20, 0xffff,  64, 2048, 16, 16, ECC_HAMMIN,
2048, &timing[3], },
+{ 		0,	0,	0,   0,	   0,  0,  0, 0,    0, &timing[0], },
+{ "64MiB 16-bit",  0x46ec, 0xffff,  32,  512, 16, 16, 1, 4096, &timing[1], },
+{ "256MiB 8-bit",  0xdaec, 0xffff,  64, 2048,  8,  8, 1, 2048, &timing[1], },
+{ "1GiB 8-bit",    0xd3ec, 0xffff, 128, 2048,  8,  8, 4, 4096, &timing[1], },
+{ "4GiB 8-bit",    0xd7ec, 0x29d5, 128, 4096,  8,  8, 8, 8192, &timing[1], },
+{ "128MiB 8-bit",  0xa12c, 0xffff,  64, 2048,  8,  8, 1, 1024, &timing[2], },
+{ "128MiB 16-bit", 0xb12c, 0xffff,  64, 2048, 16, 16, 1, 1024, &timing[2], },
+{ "512MiB 8-bit",  0xdc2c, 0xffff,  64, 2048,  8,  8, 1, 4096, &timing[2], },
+{ "512MiB 16-bit", 0xcc2c, 0xffff,  64, 2048, 16, 16, 1, 4096, &timing[2], },
+{ "1GiB 8-bit",    0x382c, 0xffff, 128, 4096,  8,  8, 4, 2048, &timing[2], },
+{ "256MiB 16-bit", 0xba20, 0xffff,  64, 2048, 16, 16, 1, 2048, &timing[3], },
 };

 static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
@@ -358,16 +362,15 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
 			return;
 		}

-		switch (nand->use_ecc) {
-		case ECC_HAMMIN:
-			nand->oob_size = 40;
+		switch (nand->ecc_strength) {
+		case 0:
+			nand->oob_size = 64;
 			break;
-		case ECC_BCH:
-			nand->oob_size = 32;
+		case HAMMING_STRENGTH:
+			nand->oob_size = 40;
 			break;
 		default:
-			nand->oob_size = 64;
-			break;
+			nand->oob_size = 32;
 		}
 	} else {
 		nand->data_size = 512;
@@ -376,17 +379,16 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
 			return;
 		}

-		switch (nand->use_ecc) {
-		case ECC_HAMMIN:
+		switch (nand->ecc_strength) {
+		case 0:
+			nand->oob_size = 16;
+			break;
+		case HAMMING_STRENGTH:
 			nand->oob_size = 8;
 			break;
-		case ECC_BCH:
+		default:
 			printk("Don't support BCH on small page device!!!\n");
 			BUG();
-			break;
-		default:
-			nand->oob_size = 16;
-			break;
 		}
 	}
 }
@@ -404,16 +406,16 @@ static void pxa3xx_nand_start(struct pxa3xx_nand *nand)

 	info = nand->info[nand->chip_select];
 	ndcr = info->reg_ndcr;
-	ndcr |= nand->use_dma ? NDCR_DMA_EN : NDCR_STOP_ON_UNCOR;
+	ndcr |= nand->use_dma ? NDCR_DMA_EN : 0;
 	ndcr |= NDCR_ND_RUN;

-	switch (nand->use_ecc) {
-	case ECC_BCH:
+	switch (nand->ecc_strength) {
+	default:
 		ndeccctrl |= NDECCCTRL_BCH_EN;
 		ndeccctrl |= NDECCCTRL_ECC_THRESH(BCH_THRESHOLD);
-	case ECC_HAMMIN:
+	case HAMMING_STRENGTH:
 		ndcr |= NDCR_ECC_EN;
-	default:
+	case 0:
 		break;
 	}

@@ -649,6 +651,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 			nand_writel(nand, NDCB0, nand->ndcb0[cmd_seqs]);
 			nand_writel(nand, NDCB0, ndcb1);
 			nand_writel(nand, NDCB0, ndcb2);
+			if (nand->ndcb3[cmd_seqs])
+				nand_writel(nand, NDCB0, nand->ndcb3[cmd_seqs]);
 		}
 		else
 			is_completed = 1;
@@ -705,11 +709,23 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 		pxa3xx_set_datasize(info);
 		nand->use_dma = use_dma;
 		chunks = info->page_size / nand->data_size;
+		if (info->ecc_strength > BCH_STRENGTH) {
+			i = info->ecc_strength / BCH_STRENGTH;
+			nand->data_size /= i;
+			ndcb0 |= NDCB0_LEN_OVRD;
+			chunks *= i;
+		}
 		break;
+	case NAND_CMD_READOOB:
+		if (info->ecc_strength > BCH_STRENGTH) {
+			printk(KERN_ERR "we don't support oob command if use"
+				     " 8bit per 512bytes ecc feature!!\n");
+			BUG();
+		}
 	default:
 		nand->ndcb1 = 0;
 		nand->ndcb2 = 0;
-		nand->use_ecc = 0;
+		nand->ecc_strength = 0;
 		break;
 	}
 	if (nand->use_dma) {
@@ -721,6 +737,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 	for (i = 0; i < CMD_POOL_SIZE; i ++) {
 		nand->ndcb0[i] = ndcb0;
 		nand->wait_ready[i] = 0;
+		nand->ndcb3[i] = (ndcb0 & NDCB0_LEN_OVRD)? nand->data_size : 0;
 	}
 	addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
 			+ info->col_addr_cycles);
@@ -728,7 +745,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 	switch (command) {
 	case NAND_CMD_READ0:
 	case NAND_CMD_SEQIN:
-		nand->use_ecc = info->use_ecc;
+		nand->ecc_strength = info->ecc_strength;
 	case NAND_CMD_READOOB:
 		memset(nand->data_buff, 0xff, column);
 		nand->buf_count = mtd->writesize + mtd->oobsize;
@@ -775,7 +792,8 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 				| NDCB0_NC
 				| addr_cycle
 				| cmd;
-
+		nand->ndcb0[0] &= ~NDCB0_LEN_OVRD;
+		nand->ndcb3[0] = 0;
 		nand->ndcb0[1] |= NDCB0_CMD_XTYPE(0x5)
 				| NDCB0_NC
 				| addr_cycle;
@@ -831,6 +849,8 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 				| (cmd & NDCB0_CMD2_MASK)
 				| NDCB0_CMD1_MASK
 				| addr_cycle;
+		nand->ndcb0[chunks] &= ~NDCB0_LEN_OVRD;
+		nand->ndcb3[chunks] = 0;
 		/* we should wait for RnB goes high which
 		 * indicate the data has been written succesfully*/
 		nand->wait_ready[nand->total_cmds] = 1;
@@ -1022,7 +1042,12 @@ static void pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 		BUG();
 	}
 	/* calculate flash information */
-	info->use_ecc = f->ecc_type;
+	if (f->ecc_strength != 0 && f->ecc_strength != HAMMING_STRENGTH
+			&& (f->ecc_strength % BCH_STRENGTH != 0)) {
+		printk(KERN_ERR "ECC strength definition error, please recheck!!\n");
+		BUG();
+	}
+	info->ecc_strength = f->ecc_strength;
 	info->page_size = f->page_size;

 	/* calculate addressing information */
@@ -1066,7 +1091,9 @@ static void pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	}

 	ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
-	ndcr |= NDCR_SPARE_EN; /* enable spare by default */
+	/* only enable spare area when ecc is lower than 8bits per 512 bytes */
+	if (f->ecc_strength <= BCH_STRENGTH)
+		ndcr |= NDCR_SPARE_EN;

 	info->reg_ndcr = ndcr;

@@ -1086,7 +1113,7 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand *nand)
 	info->reg_ndcr = ndcr & ~(NDCR_INT_MASK | NDCR_ECC_EN | NDCR_DMA_EN
| NDCR_ND_RUN);
 	info->ndtr0cs0 = nand_readl(nand, NDTR0CS0);
 	info->ndtr1cs0 = nand_readl(nand, NDTR1CS0);
-	info->use_ecc = (ndeccctrl & NDECCCTRL_BCH_EN) ? ECC_BCH : ECC_HAMMIN;
+	info->ecc_strength = (ndeccctrl & NDECCCTRL_BCH_EN) ? BCH_STRENGTH :
HAMMING_STRENGTH;

 	return 0;
 }
@@ -1121,19 +1148,16 @@ static void pxa3xx_read_page(struct mtd_info
*mtd, uint8_t *buf)
 	pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RNDOUT, 0, info->page_addr);
 	switch (nand->retcode) {
 	case ERR_SBERR:
-		switch (nand->use_ecc) {
-		case ECC_BCH:
+		switch (nand->ecc_strength) {
+		default:
 			if (nand->bad_count > BCH_THRESHOLD)
 				mtd->ecc_stats.corrected +=
 					(nand->bad_count - BCH_THRESHOLD);
 			break;

-		case ECC_HAMMIN:
+		case HAMMING_STRENGTH:
 			mtd->ecc_stats.corrected ++;
-			break;
-
-		case ECC_NONE:
-		default:
+		case 0:
 			break;
 		}
 		break;
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:37:30 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:37:30 +0800
Subject: [PATCH 20/25] pxa3xx_nand: add advanced timing tuning feature
Message-ID: <AANLkTikeAtEbhzZa_T-pcvOb0vfYMXY1cYH7RMjHGAqm@mail.gmail.com>


From leiwen at marvell.com  Tue Jun  8 00:13:08 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 8 Jun 2010 12:13:08 +0800
Subject: [PATCH 20/25] pxa3xx_nand: add advanced timing tuning feature
Message-ID: <mailman.45.1276839596.27306.linux-arm-kernel@lists.infradead.org>

For new controller, it has more power at more precise timing
tuning.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |   93 ++++++++++++++++++++++++++++------------
 1 files changed, 65 insertions(+), 28 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 04bf875..834422d 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -165,6 +165,7 @@ enum {
 };

 struct pxa3xx_nand_timing {
+	uint32_t	tADL; /* Adress to Write Data delay */
 	uint32_t	tCH;  /* Enable signal hold time */
 	uint32_t	tCS;  /* Enable signal setup time */
 	uint32_t	tWH;  /* ND_nWE high duration */
@@ -172,6 +173,7 @@ struct pxa3xx_nand_timing {
 	uint32_t	tRH;  /* ND_nRE high duration */
 	uint32_t	tRP;  /* ND_nRE pulse width */
 	uint32_t	tR;   /* ND_nWE high to ND_nRE low for read */
+	uint32_t	tRHW; /* delay for next command issue */
 	uint32_t	tWHR; /* ND_nWE high to ND_nRE low for status read */
 	uint32_t	tAR;  /* ND_ALE low to ND_nRE low delay */
 };
@@ -287,13 +289,13 @@ const static struct pxa3xx_nand_cmdset cmdset = {

 static struct pxa3xx_nand_timing __devinitdata timing[] = {
 	/* common timing used to detect flash id */
-	{ 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
+	{   0, 40, 80, 60, 100, 80, 100, 90000,  0, 400, 40, },
 	/* Samsung NAND series */
-	{ 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
+	{ 200, 10, 15, 20,  40, 30,  40, 11123, 20, 110, 10, },
 	/* Micron NAND series */
-	{ 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
+	{   0, 10, 25, 15,  25, 15,  30, 25000,  0,  60, 10, },
 	/* ST NAND series */
-	{ 10, 35, 15,  25, 15,  25, 25000,  60, 10, },
+	{   0, 10, 35, 15,  25, 15,  25, 25000,  0,  60, 10, },
 };

 static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
@@ -312,16 +314,20 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {

 static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};

-#define NDTR0_tCH(c)	(min((c), 7) << 19)
-#define NDTR0_tCS(c)	(min((c), 7) << 16)
-#define NDTR0_tWH(c)	(min((c), 7) << 11)
-#define NDTR0_tWP(c)	(min((c), 7) << 8)
-#define NDTR0_tRH(c)	(min((c), 7) << 3)
-#define NDTR0_tRP(c)	(min((c), 7) << 0)
-
-#define NDTR1_tR(c)	(min((c), 65535) << 16)
-#define NDTR1_tWHR(c)	(min((c), 15) << 4)
-#define NDTR1_tAR(c)	(min((c), 15) << 0)
+#define NDTR0_tADL(c)		(min_t(uint32_t, (c), 31) << 27)
+#define NDTR0_tCH(c)		(min_t(uint32_t, (c), 7) << 19)
+#define NDTR0_tCS(c)		(min_t(uint32_t, (c), 7) << 16)
+#define NDTR0_tWH(c)		(min_t(uint32_t, (c), 7) << 11)
+#define NDTR0_tWP(c)		(min_t(uint32_t, (c), 7) << 8)
+#define NDTR0_ETRP		(0x1 << 6)
+#define NDTR0_tRH(c)		(min_t(uint32_t, (c), 7) << 3)
+#define NDTR0_tRP(c)		(min_t(uint32_t, (c), 7) << 0)
+
+#define NDTR1_tR(c)		(min_t(uint32_t, (c), 65535) << 16)
+#define NDTR1_PRESCALE		(0x1 << 14)
+#define NDTR1_tRHW(c)		(min_t(uint32_t, (c), 3) << 8)
+#define NDTR1_tWHR(c)		(min_t(uint32_t, (c), 15) << 4)
+#define NDTR1_tAR(c)		(min_t(uint32_t, (c), 15) << 0)

 /* convert nano-seconds to nand flash controller clock cycles */
 #define ns2cycle(ns, clk)	(int)((ns) * (clk / 1000000) / 1000)
@@ -329,20 +335,51 @@ static void pxa3xx_nand_set_timing(struct
pxa3xx_nand_info *info,
 				   const struct pxa3xx_nand_timing *t)
 {
 	struct pxa3xx_nand *nand = info->nand_data;
-	unsigned long nand_clk;
-	uint32_t ndtr0, ndtr1;
-
-	nand_clk = clk_get_rate(nand->clk);
-	ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
-		NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
-		NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
-		NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
-		NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
-		NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
-
-	ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
-		NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
-		NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
+	struct platform_device *pdev = nand->pdev;
+	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
+	unsigned long nand_clk = clk_get_rate(nand->clk);
+	uint32_t ndtr0, ndtr1, tRP, tR, tRHW, tADL;
+
+	tR = ns2cycle(t->tR, nand_clk);
+	tRP = ns2cycle(t->tRP, nand_clk);
+	tRHW = tADL = ndtr0 = ndtr1 = 0;
+	if (pdata->controller_attrs & PXA3XX_NAKED_CMD_EN)
+		tR = 0;
+	if (pdata->controller_attrs & PXA3XX_ADV_TIME_TUNING) {
+		if (tRP > 0x7) {
+			ndtr0 |= NDTR0_ETRP;
+			tRP -= 0x7;
+		}
+		if (tR > 0xffff) {
+			ndtr1 |= NDTR1_PRESCALE;
+			tR /= 16;
+		}
+		if (t->tRHW > 0) {
+			tRHW = ns2cycle(t->tRHW, nand_clk);
+			if (tRHW < 16)
+				tRHW = 1;
+			else {
+				if (tRHW < 32)
+					tRHW = 2;
+				else
+					tRHW = 3;
+			}
+		}
+		tADL = ns2cycle(t->tADL, nand_clk);
+	}
+
+	ndtr0 |= NDTR0_tADL(tADL)
+		| NDTR0_tCH(ns2cycle(t->tCH, nand_clk))
+		| NDTR0_tCS(ns2cycle(t->tCS, nand_clk))
+		| NDTR0_tWH(ns2cycle(t->tWH, nand_clk))
+		| NDTR0_tWP(ns2cycle(t->tWP, nand_clk))
+		| NDTR0_tRH(ns2cycle(t->tRH, nand_clk))
+		| NDTR0_tRP(tRP);
+
+	ndtr1 |= NDTR1_tR(tR)
+		| NDTR1_tRHW(tRHW)
+		| NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk))
+		| NDTR1_tAR(ns2cycle(t->tAR, nand_clk));

 	info->ndtr0cs0 = ndtr0;
 	info->ndtr1cs0 = ndtr1;
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:37:56 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:37:56 +0800
Subject: [PATCH 23/25] pxa3xx_nand: fix reset timeout on mmp2
Message-ID: <AANLkTil4P4BuMuCXWwALcgxqUgPFB1wlb3rnzEdiC_On@mail.gmail.com>


From leiwen at marvell.com  Tue Jun  8 21:53:18 2010
From: leiwen at marvell.com (Lei Wen)
Date: Wed, 9 Jun 2010 09:53:18 +0800
Subject: [PATCH 23/25] pxa3xx_nand: fix reset timeout on mmp2
Message-ID: <mailman.46.1276839603.27306.linux-arm-kernel@lists.infradead.org>

For mmp2 board, reset command would always have timeout when enable
the IRQ processing. The command done would comes after exit the IRQ
processing whatever the timeout value is set.

Change reset command use polling mode fix the issue.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index e76264c..99f4088 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -968,6 +968,10 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,

 		break;
 	case NAND_CMD_RESET:
+		/* on some platform, it is stranger that when issue reset command,
+		 * cmd done would not come till timeout cause irq exit.
+		 * Force polling mode for reset command*/
+		use_polling = 1;
 		cmd = cmdset.reset;
 		nand->ndcb0[0] |= NDCB0_CMD_TYPE(5)
 				| cmd;
@@ -993,7 +997,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
 	struct pxa3xx_nand *nand = info->nand_data;
-	int ret, exec_cmd;
+	int ret, exec_cmd, polling_mode;

 	/* if this is a x16 device ,then convert the input
 	 * "byte" address into a "word" address appropriate
@@ -1009,6 +1013,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 		nand_writel(nand, NDTR1CS0, info->ndtr1cs0);
 	}

+	polling_mode = use_polling;
 	exec_cmd = prepare_command_pool(nand, command, column, page_addr);
 	if (exec_cmd) {
 		init_completion(&nand->cmd_complete);
@@ -1028,6 +1033,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 		}
 		nand->state &= ~STATE_CMD_PREPARED;
 	}
+	use_polling = polling_mode;
 }

 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:38:03 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:38:03 +0800
Subject: [PATCH 24/25] pxa3xx_nand: fix write oob bug
Message-ID: <AANLkTikhoddXubBcuRw1K1u9GFNCp710rArmE4L7K43-@mail.gmail.com>


From leiwen at marvell.com  Wed Jun  9 04:55:14 2010
From: leiwen at marvell.com (Lei Wen)
Date: Wed, 9 Jun 2010 16:55:14 +0800
Subject: [PATCH 24/25] pxa3xx_nand: fix write oob bug
Message-ID: <mailman.48.1276839611.27306.linux-arm-kernel@lists.infradead.org>

For column addressing is only used to subpage and oob operation,
and the fact that our controller is performing poor at such two
operations, disable the column addressing in writing the ndcb1.

If not add this patch, write_oob function would fail.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |   42 +++++++++++++++++++++++++++++++--------
 1 files changed, 33 insertions(+), 9 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 99f4088..96b46e1 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -314,6 +314,20 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
 { "256MiB 16-bit", 0xba20, 0xffff,  64, 2048, 16, 16, 1, 2048, &timing[3], },
 };

+static struct nand_ecclayout nand_oob_128_BCH = {
+	.eccbytes = 64,
+	.eccpos = {
+		64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
+		76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
+		88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,
+		100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
+		110, 111, 112, 113, 114, 115, 116, 117, 118, 119,
+		120, 121, 122, 123, 124, 125, 126, 127},
+	.oobfree = {
+		{.offset = 2,
+		.length = 62}}
+};
+
 static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};

 #define NDTR0_tADL(c)		(min_t(uint32_t, (c), 31) << 27)
@@ -599,13 +613,19 @@ static void start_data_dma(struct pxa3xx_nand
*nand, int dir_out)
 	desc_oob->ddadr = desc->ddadr = DDADR_STOP;
 	desc_oob->dcmd = desc->dcmd = DCMD_WIDTH4 | DCMD_BURST32;
 	if (dir_out) {
+		if (nand->oob_size > 0) {
+			desc_oob->dsadr = nand->dma_buff_phys + info->page_size + nand->oob_column;
+			desc_oob->dcmd |= DCMD_ENDIRQEN | DCMD_INCSRCADDR | DCMD_FLOWTRG | oob_len;
+			desc->ddadr = nand->dma_desc_addr + sizeof(struct pxa_dma_desc);
+			desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG | data_len;
+		}
+		else
+			desc->dcmd |= DCMD_ENDIRQEN | DCMD_INCSRCADDR | DCMD_FLOWTRG | data_len;
 		desc->dsadr = nand->dma_buff_phys + nand->data_column;
-		desc->dtadr = nand->mmio_phys + NDDB;
-		desc->dcmd |= DCMD_ENDIRQEN | DCMD_INCSRCADDR | DCMD_FLOWTRG |
(data_len + oob_len);
+		desc_oob->dtadr = desc->dtadr = nand->mmio_phys + NDDB;
 	} else {
 		if (nand->oob_size > 0) {
-			desc_oob->dtadr = nand->dma_buff_phys
-					+ info->page_size + nand->oob_column;
+			desc_oob->dtadr = nand->dma_buff_phys + info->page_size + nand->oob_column;
 			desc_oob->dcmd |= DCMD_ENDIRQEN | DCMD_INCTRGADDR | DCMD_FLOWSRC | oob_len;
 			desc->ddadr = nand->dma_desc_addr + sizeof(struct pxa_dma_desc);
 			desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC | data_len;
@@ -766,11 +786,13 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 	uint16_t cmd;
 	int addr_cycle, exec_cmd, ndcb0, i, chunks = 0;
 	struct mtd_info *mtd;
+	struct nand_chip *chip;
 	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
 	struct platform_device *pdev = nand->pdev;
 	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;

 	mtd = get_mtd_by_info(info);
+	chip = mtd->priv;
 	ndcb0 = (nand->chip_select) ? NDCB0_CSEL : 0;;
 	addr_cycle = 0;
 	exec_cmd = 1;
@@ -825,11 +847,9 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 		info->page_addr = page_addr;
 		/* small page addr setting */
 		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
-			nand->ndcb1[0] = ((page_addr & 0xFFFFFF) << 8)
-					| (column & 0xFF);
+			nand->ndcb1[0] = ((page_addr & 0xFFFFFF) << 8);
 		else {
-			nand->ndcb1[0] = ((page_addr & 0xFFFF) << 16)
-					| (column & 0xFFFF);
+			nand->ndcb1[0] = ((page_addr & 0xFFFF) << 16);

 			if (page_addr & 0xFF0000)
 				nand->ndcb2 = (page_addr & 0xFF0000) >> 16;
@@ -892,7 +912,9 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 		break;

 	case NAND_CMD_PAGEPROG:
-		if (is_buf_blank(nand->data_buff, (mtd->writesize + mtd->oobsize))) {
+		if (is_buf_blank(nand->data_buff, mtd->writesize) &&
+		    is_buf_blank(nand->oob_buff + chip->ecc.layout->oobfree[0].offset,
+			    chip->ecc.layout->oobfree[0].length)) {
 			exec_cmd = 0;
 			break;
 		}
@@ -1394,6 +1416,8 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 	}

 	pxa3xx_nand_config_flash(info, f);
+	if (f->page_size == 4096 && f->ecc_strength == 4)
+		chip->ecc.layout = &nand_oob_128_BCH;
 	pxa3xx_flash_ids[0].name = f->name;
 	pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff;
 	pxa3xx_flash_ids[0].pagesize = f->page_size;
-- 
1.7.0.4


From haojian.zhuang at gmail.com  Fri Jun 18 01:38:11 2010
From: haojian.zhuang at gmail.com (Haojian Zhuang)
Date: Fri, 18 Jun 2010 13:38:11 +0800
Subject: [PATCH 25/25] pxa3xx_nand: fix power management support
Message-ID: <AANLkTilYSzvQfpHtdIVv1w4yMyMZhk_FW59wgkPEXU_X@mail.gmail.com>


From leiwen at marvell.com  Wed Jun 16 21:43:24 2010
From: leiwen at marvell.com (Lei Wen)
Date: Thu, 17 Jun 2010 09:43:24 +0800
Subject: [PATCH 25/25] pxa3xx_nand: fix power management support
Message-ID: <mailman.50.1276839621.27306.linux-arm-kernel@lists.infradead.org>

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |   48 +++++++++++++++++++++++++++++++--------
 1 files changed, 38 insertions(+), 10 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 96b46e1..e4de69c 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1695,26 +1695,54 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 #ifdef CONFIG_PM
 static int pxa3xx_nand_suspend(struct platform_device *pdev,
pm_message_t state)
 {
-	struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
-	struct mtd_info *mtd = info->mtd;
+	struct pxa3xx_nand *nand= platform_get_drvdata(pdev);
+	struct pxa3xx_nand_info *info;
+	struct mtd_info *mtd;
+	int ret = 0;
+	uint8_t cs;

-	if (info->state & STATE_CMD_PREPARED) {
-		dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
+	if (nand->state & STATE_CMD_PREPARED) {
+		dev_err(&pdev->dev, "driver busy, state = %d\n", nand->state);
 		return -EAGAIN;
 	}

-	return 0;
+	for (cs = 0; cs < NUM_CHIP_SELECT; cs ++) {
+		info = nand->info[cs];
+		if (!info)
+			continue;
+		mtd = get_mtd_by_info(info);
+		ret = mtd->suspend(mtd);
+	}
+
+	return ret;
 }

 static int pxa3xx_nand_resume(struct platform_device *pdev)
 {
-	struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
-	struct mtd_info *mtd = info->mtd;
+	struct pxa3xx_nand *nand= platform_get_drvdata(pdev);
+	struct pxa3xx_nand_info *info;
+	struct mtd_info *mtd;
+	uint8_t cs;

-	nand_writel(info, NDTR0CS0, info->ndtr0cs0);
-	nand_writel(info, NDTR1CS0, info->ndtr1cs0);
-	clk_enable(info->clk);
+	for (cs = 0; cs < NUM_CHIP_SELECT; cs ++) {
+		info = nand->info[cs];
+		if (!info)
+			continue;
+		nand_writel(nand, NDTR0CS0, info->ndtr0cs0);
+		nand_writel(nand, NDTR1CS0, info->ndtr1cs0);
+		nand->chip_select = cs;
+		/* Sometimes nand chip would raise a ready interrupt
+		 * when resume, reset the by start and stop to prevent
+		 * it damage driver's state machine */
+		pxa3xx_nand_start(nand);
+		pxa3xx_nand_stop(nand);
+		mtd = get_mtd_by_info(info);
+		mtd->resume(mtd);
+	}

+	/* set the controller cs to a invalid num to let driver
+	 * reconfigure the timing when it call the cmdfunc */
+	nand->chip_select = 0xff;
 	return 0;
 }
 #else
-- 
1.7.0.4


From mhowe at cwlinux.com  Fri Jun 18 01:47:12 2010
From: mhowe at cwlinux.com (Morgan Howe)
Date: Fri, 18 Jun 2010 13:47:12 +0800
Subject: mxcmmc driver hangs on sync
In-Reply-To: <45DEC573-1158-477E-A971-03CB4633F442@zepcam.com>
References: <20100615112936.5d03ce92@morgan>
	<20100615063142.GU17833@buzzloop.caiaq.de>
	<20100615152051.26e4589c@morgan>
	<20100615072237.GW17833@buzzloop.caiaq.de>
	<20100617163340.69409a3f@morgan>
	<45DEC573-1158-477E-A971-03CB4633F442@zepcam.com>
Message-ID: <20100618134712.2d8d949f@morgan>

Hey Erik,

On Thu, 17 Jun 2010 20:51:37 +0200
Erik Oomen <erik.oomen at zepcam.com> wrote:
> We've had the same problems for various kernels and mxcmmc
> modifications. The following fixed it.  We applied it to the 2.6.28
> kernel and have been writing and reading *many* Gigabytes without a
> problem. 

We ran into this problem using 2 SD cards and assumed that it was
directly related to that.  This morning I decided to try and reproduce
this problem using only a single SD card, and I was indeed able to do
so.

Thanks for the patch - it does appear to fix the problem for a single
SD, but when using 2 SD cards I still ran into the issue.  However,
replacing your irq_save/restore calls with a spinlock seems to fix the
issue for multiple SD cards.  Is using a spinlock an appropriate way to
fix this or is there some other way that would be preferable?

Regards,
Morgan



From marek.vasut at gmail.com  Fri Jun 18 01:48:53 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 18 Jun 2010 07:48:53 +0200
Subject: [PATCH 2/4] pxa2xx/cpufreq: Simplify DRI recomputation routine
In-Reply-To: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
References: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1276840135-5982-2-git-send-email-marek.vasut@gmail.com>

This patch:
1) Simpifies the DRI recomputation routine by pulling out the common code
2) Fixes a bug in PXA27x DRI recomputation caused by incorrect parenthesis

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/cpufreq-pxa2xx.c |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 1949850..74fc4b5 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -256,12 +256,13 @@ static void init_sdram_rows(void)
 
 static u32 mdrefr_dri(unsigned int freq)
 {
-	u32 dri = 0;
+	u32 dri = freq * SDRAM_TREF / sdram_rows;
 
-	if (cpu_is_pxa25x())
-		dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
 	if (cpu_is_pxa27x())
-		dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
+		dri -= 31;
+
+	dri /= 32;
+
 	return dri;
 }
 
-- 
1.7.1



From marek.vasut at gmail.com  Fri Jun 18 01:48:52 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 18 Jun 2010 07:48:52 +0200
Subject: [PATCH 1/4] pxa2xx/cpufreq: Simplify CPU frequency change asm
Message-ID: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>

This patch does the following changes to cpufreq-pxa2xx:
1) Simplifies the assembler code for frequency change
2) Reads back the MDREFR value to make sure data latched
3) Does as little operations in lock as possible

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/cpufreq-pxa2xx.c |   35 ++++++++++++++++-------------------
 1 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 9e4d981..1949850 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -297,7 +297,7 @@ static int pxa_set_target(struct cpufreq_policy *policy,
 	unsigned int idx;
 	unsigned long flags;
 	unsigned int new_freq_cpu, new_freq_mem;
-	unsigned int unused, preset_mdrefr, postset_mdrefr, cclkcfg;
+	unsigned int preset_mdrefr, postset_mdrefr, cclkcfg;
 	int ret = 0;
 
 	/* Get the current policy */
@@ -355,29 +355,26 @@ static int pxa_set_target(struct cpufreq_policy *policy,
 		postset_mdrefr &= ~MDREFR_DB2_MASK;
 	}
 
+	/* Prepare CCLKCFG */
+	cclkcfg = pxa_freq_settings[idx].cclkcfg;
+
 	local_irq_save(flags);
 
-	/* Set new the CCCR and prepare CCLKCFG */
+	/* Set new the CCCR */
 	CCCR = pxa_freq_settings[idx].cccr;
-	cclkcfg = pxa_freq_settings[idx].cclkcfg;
 
 	asm volatile("							\n\
-		ldr	r4, [%1]		/* load MDREFR */	\n\
-		b	2f						\n\
-		.align	5						\n\
-1:									\n\
-		str	%3, [%1]		/* preset the MDREFR */	\n\
-		mcr	p14, 0, %2, c6, c0, 0	/* set CCLKCFG[FCS] */	\n\
-		str	%4, [%1]		/* postset the MDREFR */ \n\
-									\n\
-		b	3f						\n\
-2:		b	1b						\n\
-3:		nop							\n\
-	  "
-		     : "=&r" (unused)
-		     : "r" (&MDREFR), "r" (cclkcfg),
-		       "r" (preset_mdrefr), "r" (postset_mdrefr)
-		     : "r4", "r5");
+		.align	5		/* align to cache line */	\n\
+		str	%2, [%0]	/* preset the MDREFR */		\n\
+		ldr	r4, [%0]	/* make sure data latched */	\n\
+		mcr	p14, 0, %1, c6, c0, 0	/* set CCLKCFG[FCS] */	\n\
+		str	%3, [%0]	/* postset the MDREFR */	\n\
+		ldr	r4, [%0]	/* make sure data latched */	\n\
+	"
+		:: "r" (&MDREFR), "r" (cclkcfg),
+		   "r" (preset_mdrefr), "r" (postset_mdrefr)
+		: "r4");
+
 	local_irq_restore(flags);
 
 	/*
-- 
1.7.1



From marek.vasut at gmail.com  Fri Jun 18 01:48:54 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 18 Jun 2010 07:48:54 +0200
Subject: [PATCH 3/4] pxa2xx/cpufreq: Fix PCMCIA frequency scaling
In-Reply-To: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
References: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1276840135-5982-3-git-send-email-marek.vasut@gmail.com>

The MCxx values must be based off memory clock, not CPU core clock.

This also fixes the bug where on some machines the LCD went crazy while using
PCMCIA.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/pcmcia/pxa2xx_base.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c
index df4532e..f370476 100644
--- a/drivers/pcmcia/pxa2xx_base.c
+++ b/drivers/pcmcia/pxa2xx_base.c
@@ -178,7 +178,6 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
 			       unsigned long val,
 			       struct cpufreq_freqs *freqs)
 {
-#warning "it's not clear if this is right since the core CPU (N) clock has no effect on the memory (L) clock"
 	switch (val) {
 	case CPUFREQ_PRECHANGE:
 		if (freqs->new > freqs->old) {
@@ -186,7 +185,7 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
 			       "pre-updating\n",
 			       freqs->new / 1000, (freqs->new / 100) % 10,
 			       freqs->old / 1000, (freqs->old / 100) % 10);
-			pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
+			pxa2xx_pcmcia_set_timing(skt);
 		}
 		break;
 
@@ -196,7 +195,7 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
 			       "post-updating\n",
 			       freqs->new / 1000, (freqs->new / 100) % 10,
 			       freqs->old / 1000, (freqs->old / 100) % 10);
-			pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
+			pxa2xx_pcmcia_set_timing(skt);
 		}
 		break;
 	}
-- 
1.7.1



From marek.vasut at gmail.com  Fri Jun 18 01:48:55 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 18 Jun 2010 07:48:55 +0200
Subject: [PATCH 4/4] pxa2xx/pcmcia: Prepare for pxa320
In-Reply-To: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
References: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1276840135-5982-4-git-send-email-marek.vasut@gmail.com>

PXA320 also supports PCMCIA/CF interface. This patch generalizes register access
in pxa2xx_pcmcia so the pxa320 is now supported as well.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/pcmcia/pxa2xx_base.c |   40 +++++++++++++++++++++++++++++++++++++---
 1 files changed, 37 insertions(+), 3 deletions(-)

diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c
index f370476..3d63d2f 100644
--- a/drivers/pcmcia/pxa2xx_base.c
+++ b/drivers/pcmcia/pxa2xx_base.c
@@ -85,6 +85,12 @@
 #define MCXX_ASST_SHIFT     (7)
 #define MCXX_HOLD_SHIFT     (14)
 
+#define	PXA2XX_SMC_BASE		(0x48000000)
+#define	PXA3XX_SMC_BASE		(0x4a000000)
+#define	MCMEM_OFFSET		(0x28)
+#define	MCATT_OFFSET		(0x30)
+#define	MCIO_OFFSET		(0x38)
+
 static inline u_int pxa2xx_mcxx_hold(u_int pcmcia_cycle_ns,
 				     u_int mem_clk_10khz)
 {
@@ -115,39 +121,62 @@ static inline u_int pxa2xx_pcmcia_cmd_time(u_int mem_clk_10khz,
 	return (300000 * (pcmcia_mcxx_asst + 1) / mem_clk_10khz);
 }
 
+static inline void pxa2xx_pcmcia_set_reg( uint32_t reg, uint32_t sock,
+					uint32_t val )
+{
+	if (cpu_is_pxa2xx())
+		reg = PXA2XX_SMC_BASE | (reg + (sock << 4));
+	if (cpu_is_pxa320())
+		reg |= PXA3XX_SMC_BASE;
+
+	__REG2(reg, val);
+}
+
 static int pxa2xx_pcmcia_set_mcmem( int sock, int speed, int clock )
 {
-	MCMEM(sock) = ((pxa2xx_mcxx_setup(speed, clock)
+	uint32_t val;
+
+	val = ((pxa2xx_mcxx_setup(speed, clock)
 		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
 		| ((pxa2xx_mcxx_asst(speed, clock)
 		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
 		| ((pxa2xx_mcxx_hold(speed, clock)
 		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
 
+	pxa2xx_pcmcia_set_reg(MCMEM_OFFSET, sock, val);
+
 	return 0;
 }
 
 static int pxa2xx_pcmcia_set_mcio( int sock, int speed, int clock )
 {
-	MCIO(sock) = ((pxa2xx_mcxx_setup(speed, clock)
+	uint32_t val;
+
+	val = ((pxa2xx_mcxx_setup(speed, clock)
 		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
 		| ((pxa2xx_mcxx_asst(speed, clock)
 		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
 		| ((pxa2xx_mcxx_hold(speed, clock)
 		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
 
+	pxa2xx_pcmcia_set_reg(MCIO_OFFSET, sock, val);
+
 	return 0;
 }
 
 static int pxa2xx_pcmcia_set_mcatt( int sock, int speed, int clock )
 {
-	MCATT(sock) = ((pxa2xx_mcxx_setup(speed, clock)
+	uint32_t val;
+
+	val = ((pxa2xx_mcxx_setup(speed, clock)
 		& MCXX_SETUP_MASK) << MCXX_SETUP_SHIFT)
 		| ((pxa2xx_mcxx_asst(speed, clock)
 		& MCXX_ASST_MASK) << MCXX_ASST_SHIFT)
 		| ((pxa2xx_mcxx_hold(speed, clock)
 		& MCXX_HOLD_MASK) << MCXX_HOLD_SHIFT);
 
+	pxa2xx_pcmcia_set_reg(MCATT_OFFSET, sock, val);
+
 	return 0;
 }
 
@@ -276,6 +305,11 @@ static int pxa2xx_drv_pcmcia_probe(struct platform_device *dev)
 	if (!ops)
 		return -ENODEV;
 
+	if (cpu_is_pxa320() && ops->nr > 1) {
+		dev_err(&dev->dev, "pxa320 supports only one pcmcia slot");
+		return -EINVAL;
+	}
+
 	pxa2xx_drv_pcmcia_ops(ops);
 
 	sinfo = kzalloc(SKT_DEV_INFO_SIZE(ops->nr), GFP_KERNEL);
-- 
1.7.1



From myungjoo.ham at samsung.com  Fri Jun 18 02:03:44 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Fri, 18 Jun 2010 15:03:44 +0900
Subject: [PATCH] S5PV210 Correct clock source control register properties
In-Reply-To: <003301cb0ea8$474d1640$d5e742c0$%kim@samsung.com>
References: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>
	<003301cb0ea8$474d1640$d5e742c0$%kim@samsung.com>
Message-ID: <AANLkTik78ycpNKYIhdu7SKeQ_9htcjCJlXch5bobUxHq@mail.gmail.com>

On Fri, Jun 18, 2010 at 2:36 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> MyungJoo Ham wrote:
>>
>> The clock source controls (struct clksrc_clk) have been often accessing
>> CLK_GATE_IPx, which are for clock gating and are accessed by each clock
>> as well as the clock source. This duplicated clock issue may incur
>> lockup problems when there are two modules accessing the same clock with
>> different names.
>>
> Actually, S5V210/S5PC110 CLK_GATE_IPx can disable the clock operation of each
> IP if it is not required. And this reduces dynamic power. CLK_SRC_MASKx is
> used to control clock mux of each IP's SCLK.
>
> Basically CLK_SRC_MASKx is for mux control (output masking) of each IP
> source, and actually that can _not_ control relevant every source clock of
> each IP. So CLK_GATE_IPx exists, can do it.
>
> I know, in the several case, i.e, camera and fimc, each sclk_xxx need to
> control. And can be controlled each sclk_xxx by using your patch, but in this
> case, need to additional control relevant clock gating for dynamic clock
> gating of each IP in its device driver.

We've changed clksrc_clk's not to access CLK_GATE_IPx because of the
duplicated clock (or doppelganger) problem. We need to either get rid
of ".enable / .ctrlbit" from
struct clk of struct clksrc_clk, change them to use "CLK_SRC_MASKx",
or get rid of their twins
(e.g., "hsmmc" for "mmc_bus") as long as there are clock definitions
with different names
accessing the same CLK_GATE_IPx. Letting clksrc_clk access
CLK_GATE_IPx creates potential
kernel lockups.

Drivers should get clocks defined in "static struct clk init_clocks[],
init_clocks_disable[]" in order
to access CLK_GATE_IPx though we still have some missing clocks there;
e.g., mfc, g2d, and g3d.
Again, there should be NO duplicated clock definitions if we are going
to use .enable function that
accesses the same address & bit.

----------- from the previous patch -----------
Please note that each clock definition should access different control
register; otherwise, the system may suffer lockups. For example, if we
have two clock definitions "a" and "b" which access the same register
(and the shift value). Then, when we do:

       module B
       1 clk = clk_get("b");
       2 clk->clk_enable(clk);
       3 do something with clk.
       4 clk->clk_disable(clk);

       module A
       1 clk = clk_get("a");
       2 clk->clk_enable(clk);
       3 do something with clk
       4 clk->clk_disable(clk);

       And if the execution order is

       B1->B2->A1->A2->A3->A4->B3 ...

       Then, the system may hang at the point B3.
------------------------------------------------------------------------------------

>
>> Besides, the clock source control is supposed to control (setting values
>> of MASK, SRC, DIV), not to turn on/off individual clock.
>>
>> Another point is that there are registers (CLK_SRC_MASK0/1) specialized
>> for masking clock source control in S5PV210/S5PC110 according to the
>> user manual (rev 20100201).
>>
>> Therefore, accessing CLK_SRC_MASK0/1 (rather than accessing
>> CLK_GATE_IPx) for the clock source control is safer and fits to the
>> semantics of S5PV210/S5PC110 registers. And fortuneatly, each clock
>> source defined in clock.c has corresponding bit at CLK_SRC_MASK0/1
>> except for MFC, G2D, and G3D.
>>
>> In this patch,
>>
>> - DAC, HDMI, AUDIO 0/1/2, UCLK(uart) 0/1/2/3, MIXER, FIMC 0/1/2,
>> FIMC, MMC 0/1/2/3, CSIS, SPI 0/1, PWI, and PWM clock sources are
>> modified to use CLK_SRC_MASK0/1, which were using CLK_GATE_IPx.
>>
>> - CAM 0/1 did not have enable/disable control. They now access
>> ? CLK_SRC_MASK0.
>>
>> - MFC, G3D, G2D were using CLK_GATE_IPx. However, as there are no clocks
>> ? defined to control MFC, G3D, and G2D, we kept them to access
>> CLK_GATE_IPx. These may need to be modified (erase .enable, .ctrlbit
>> from sclk_mfc, sclk_g2d, sclk_g3d and create clocks: g3d, g2d, mfc)
>> later.
>>
> Hmm..need to check about multimedia usage.
>
> And in my opinion, it would be helpful to understand that should be short and
> clear.
>
>> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
>> ---
>> ?arch/arm/mach-s5pv210/clock.c | ?101
> ++++++++++++++++++++++-------------------
>> ?1 files changed, 55 insertions(+), 46 deletions(-)
>>
>> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
>> index ec5ad8c..08c1063 100644
>> --- a/arch/arm/mach-s5pv210/clock.c
>> +++ b/arch/arm/mach-s5pv210/clock.c
>> @@ -183,6 +183,11 @@ static int s5pv210_clk_mask0_ctrl(struct clk *clk, int
> enable)
>> ? ? ? return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
>> ?}
>>
>> +static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
>> +{
>> + ? ? return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
>> +}
>> +
>> ?static struct clk clk_sclk_hdmi27m = {
>> ? ? ? .name ? ? ? ? ? = "sclk_hdmi27m",
>> ? ? ? .id ? ? ? ? ? ? = -1,
>> @@ -497,8 +502,8 @@ static struct clksrc_clk clk_sclk_dac = {
>> ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_dac",
>> ? ? ? ? ? ? ? .id ? ? ? ? ? ? = -1,
>> - ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 10),
>> - ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip1_ctrl,
>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 2),
>> + ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> ? ? ? },
>> ? ? ? .sources ? ? ? ?= &clkset_sclk_dac,
>> ? ? ? .reg_src ? ? ? ?= { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
>> @@ -527,8 +532,8 @@ static struct clksrc_clk clk_sclk_hdmi = {
>> ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_hdmi",
>> ? ? ? ? ? ? ? .id ? ? ? ? ? ? = -1,
>> - ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip1_ctrl,
>> - ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 11),
>> + ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 0),
>> ? ? ? },
>> ? ? ? .sources ? ? ? ?= &clkset_sclk_hdmi,
>> ? ? ? .reg_src ? ? ? ?= { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
>> @@ -565,8 +570,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
>> ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_audio",
>> ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 0,
>> - ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
>> - ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 4),
>> + ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 24),
>> ? ? ? },
>> ? ? ? .sources = &clkset_sclk_audio0,
>> ? ? ? .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
>> @@ -594,8 +599,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
>> ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_audio",
>> ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 1,
>> - ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
>> - ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 5),
>> + ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 25),
>> ? ? ? },
>> ? ? ? .sources = &clkset_sclk_audio1,
>> ? ? ? .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
>> @@ -623,8 +628,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
>> ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_audio",
>> ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 2,
>> - ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
>> - ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 6),
>> + ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 26),
>> ? ? ? },
>> ? ? ? .sources = &clkset_sclk_audio2,
>> ? ? ? .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
>> @@ -680,8 +685,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "uclk1",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 0,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1<<17),
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 12),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_uart,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
>> @@ -690,8 +695,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "uclk1",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 1,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 18),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 13),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_uart,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
>> @@ -700,8 +705,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "uclk1",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 2,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 19),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 14),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_uart,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
>> @@ -710,8 +715,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "uclk1",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 3,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 20),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 15),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_uart,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
>> @@ -720,8 +725,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mixer",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = -1,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip1_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 9),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 1),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_sclk_mixer,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
>> @@ -738,8 +743,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_fimc",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 0,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip0_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 24),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask1_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 2),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
>> @@ -748,8 +753,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_fimc",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 1,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip0_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 25),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask1_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 3),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
>> @@ -758,8 +763,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_fimc",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 2,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip0_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 26),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask1_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 4),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
>> @@ -768,6 +773,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_cam",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 0,
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 3),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
>> @@ -776,6 +783,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_cam",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 1,
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 4),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
>> @@ -784,8 +793,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_fimd",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = -1,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip1_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 0),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 5),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
>> @@ -794,8 +803,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 0,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip2_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 16),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 8),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
>> @@ -804,8 +813,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 1,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip2_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 17),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 9),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
>> @@ -814,8 +823,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 2,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip2_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 18),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 10),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
>> @@ -824,8 +833,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_mmc",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 3,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip2_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 19),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 11),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
>> @@ -864,8 +873,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_csis",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = -1,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip0_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 31),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 6),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
>> @@ -874,8 +883,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_spi",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 0,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 12),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 16),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
>> @@ -884,8 +893,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_spi",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = 1,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 13),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 17),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
>> @@ -894,8 +903,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_pwi",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = -1,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = &s5pv210_clk_ip4_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 2),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = &s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 29),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
>> @@ -904,8 +913,8 @@ static struct clksrc_clk clksrcs[] = {
>> ? ? ? ? ? ? ? .clk ? ? ? ? ? ?= {
>> ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "sclk_pwm",
>> ? ? ? ? ? ? ? ? ? ? ? .id ? ? ? ? ? ? = -1,
>> - ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip3_ctrl,
>> - ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 23),
>> + ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
>> + ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ?= (1 << 19),
>> ? ? ? ? ? ? ? },
>> ? ? ? ? ? ? ? .sources = &clkset_group2,
>> ? ? ? ? ? ? ? .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
>> --
>
> I'm not sure that need to control of all sclk_xxx like above method, mux
> output masking.
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

ps. I forgot to erase .enable and .ctrlbit of "sclk_fimc"s. The user
manual states that
the three "sclk_fimc" clocks should be controlled identically at the
same time; thus,
there should be no individual clock masking control on them. This will
be done later.
(we may let them control (0x7<<2) so that they are controlled at the
same time, however,
we create "doppelganger" clocks there by doing so.)


-- 
MyungJoo Ham (???), Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858

From david-b at pacbell.net  Fri Jun 18 02:16:10 2010
From: david-b at pacbell.net (David Brownell)
Date: Thu, 17 Jun 2010 23:16:10 -0700 (PDT)
Subject: gpiolib and sleeping gpios
In-Reply-To: <4C1A980F.8080908@bluewatersys.com>
Message-ID: <514259.95052.qm@web180315.mail.gq1.yahoo.com>



--- On Thu, 6/17/10, Ryan Mallon <ryan at bluewatersys.com> wrote:
> Currently implementors of gpiolib must provide
> implementations for
> gpio_get_value, gpio_set_value and gpio_cansleep. 

Not true.  There is ONE implementation of gpiolib.

I think you mean "implementors of the GPIO calls".
many of those implementors will use gpiolib, to
make their lives easier.  They are not, however,
re-implementing gpiolib itself...

Most of
> the
> implementations just #define these to the double underscore
> prefixed
> versions in drivers/gpio/gpiolib.c. A few implementations
> have a simple
> wrapper function which provides a fast path for the SoC
> gpios, and calls
> gpiolib for the any additional gpios, such as those added
> by an io expander.

Right...


> Although gpio_chips know whether or not they may sleep,
> gpios which can
> sleep need to call gpio_[set/get]_value_cansleep. 

GPIOsare hardware, or maybe software abstractions;
either way,  can't call those.
  Driver level code does
when it accesses a GPIO.
for example,peripheral setup logic might.


The only
> difference
> between __gpio_(set/get)_value and
> gpio_(set/get)_value_cansleep is that


only the cansleep() versions may be used for
GPIOs whose operation requires use of sleeping
calls.  Most SoC GPIOs are safe to access with
IRQs disabled, spinlocks, held and so on.

That's why only the non-cansleep() versions
are documented as being spinlock-safe.


> the cansleep versions calls might_sleep_if. Most drivers


That's an implemenation detail, internal to the
gpiolib code.

Note that "can" sleep means exactly that...  It
doesn't mean "must sleep".  A valid way to
implement a cansleep() variant is to 

just call the spinlock-safe routine, so that
it never sleeps.

THe converse is not true; the spinlock-safe
routine must never call a cansleep() version.


>  Most drivers call > gpio_(get/set)_value, rather than the cansleep variants. I
> haven't done
> a full audit of all of the drivers (which is a reasonably
> involved
> task), but I would hazard a guess that some of these could
> be replaced
> by the cansleep versions.


One hopes that the runtime warnings have gotten
folk to fix bugs where the cansleep() version
should have been used, but wasn't...


Better IMO not to make that change except as
part
of a bugfix:  e.g. remove a runtime warning
that boils down to not using the cansleep()
version when it should have been used.
> 
> Would it not be simpler to combine the calls and have
> something like this:
> 
> void __gpio_get_value(unsigned gpio, int value)
> {
> ??? struct gpio_chip *chip;
> 
> ??? chip = gpio_to_chip(gpio);
> ??? might_sleep_if(extra_checks &&
> chip->can_sleep);
> ??? chip->set(chip, gpio - chip->base,

> value);

calling chip->set() when  chip->can_sleep
and the call context can't be preempted,
would be a bug.  So that code is wrong ...
it should at least warn about the error
made by the caller.  If we had error returns from gpio get/set calls 9sigh), it'd be right to
fail that call.

> }
> 
> Then all drivers can just call gpio_(set/get)_value


Bad idea.  Those calls are only for
use in non-sleeping contexts; don't
train developers to misuse calls.

 and any
> attempts to
> use sleeping gpios from an non-sleeping context will be
> caught by the
> might_sleep_if check. Is there something I am missing about
> this?

The fact that such attempts are errors
in the calling code, and should not be
swept under therug...


> 
> I can prepare a patch which combines the non-sleeping and
> sleeping
> variants, but I wanted to check that I'm not missing
> something
> fundamental first.
> 
> Thanks,
> ~Ryan
> 
> -- 
> Bluewater Systems Ltd - ARM Technology Solution Centre
> 
> Ryan Mallon? ? ?
> ?????? ??? 5
> Amuri Park, 404 Barbadoes St
> ryan at bluewatersys.com?
> ? ? ?????? PO Box 13
> 889, Christchurch 8013
> http://www.bluewatersys.com??? New
> Zealand
> Phone: +64 3 3779127??? ???
> Freecall: Australia 1800 148 751
> Fax:???+64 3 3779135???
> ??? ??? ? USA 1800 261
> 2934
> 



From eric.y.miao at gmail.com  Fri Jun 18 02:23:02 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 14:23:02 +0800
Subject: [PATCH 01/25] pxa3xx_nand: condense the flash definition
In-Reply-To: <AANLkTil1FnPkGS7l6W0HWeXyOxXzWbZkvFWY4jJF_I_A@mail.gmail.com>
References: <AANLkTil1FnPkGS7l6W0HWeXyOxXzWbZkvFWY4jJF_I_A@mail.gmail.com>
Message-ID: <AANLkTinOsQ8AcH-As91CRqrEQVnXdsm_CmFQgyj7gI1_@mail.gmail.com>

On Fri, Jun 18, 2010 at 1:32 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> From 76684334fbf214ab164ed07791b02535a3f04779 Mon Sep 17 00:00:00 2001
> From: Lei Wen <leiwen at marvell.com>
> Date: Sat, 20 Mar 2010 19:01:23 +0800
> Subject: [PATCH 01/25] pxa3xx_nand: condense the flash definition
>
> Adding a new flash definition would need less code.
> Keep the platform passing flash defition method.
                                  ^^^^^^^^ definition?
> If one flash is both defined in platform data and builtin table,
> driver would select the one from platform data first.

This makes sense. I thin the CONFIG_MTD_NAND_PXA3xx_BUILTIN is introduced
as an optimization so to reduce the code size if platform flash definition
is provided, instead of an option to remove built-in definitions.

>
> By this way, platform could select the timing most suit for itself,
                                                     ^^^^ suitable
> not need to follow the common settings.
>
> Signed-off-by: Lei Wen <leiwen at marvell.com>
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>

// there are some line wrapped though, maybe it's my gmail fault.

> ---
> ?arch/arm/plat-pxa/include/plat/pxa3xx_nand.h | ? 37 ----
> ?drivers/mtd/nand/Kconfig ? ? ? ? ? ? ? ? ? ? | ? ?7 -
> ?drivers/mtd/nand/pxa3xx_nand.c ? ? ? ? ? ? ? | ?241 +++++++-------------------
> ?3 files changed, 66 insertions(+), 219 deletions(-)
>
> diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
> b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
> index 3478eae..7e5a28f 100644
> --- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
> +++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
> @@ -4,43 +4,6 @@
> ?#include <linux/mtd/mtd.h>
> ?#include <linux/mtd/partitions.h>
>
> -struct pxa3xx_nand_timing {
> - ? ? ? unsigned int ? ?tCH; ?/* Enable signal hold time */
> - ? ? ? unsigned int ? ?tCS; ?/* Enable signal setup time */
> - ? ? ? unsigned int ? ?tWH; ?/* ND_nWE high duration */
> - ? ? ? unsigned int ? ?tWP; ?/* ND_nWE pulse time */
> - ? ? ? unsigned int ? ?tRH; ?/* ND_nRE high duration */
> - ? ? ? unsigned int ? ?tRP; ?/* ND_nRE pulse width */
> - ? ? ? unsigned int ? ?tR; ? /* ND_nWE high to ND_nRE low for read */
> - ? ? ? unsigned int ? ?tWHR; /* ND_nWE high to ND_nRE low for status read */
> - ? ? ? unsigned int ? ?tAR; ?/* ND_ALE low to ND_nRE low delay */
> -};
> -
> -struct pxa3xx_nand_cmdset {
> - ? ? ? uint16_t ? ? ? ?read1;
> - ? ? ? uint16_t ? ? ? ?read2;
> - ? ? ? uint16_t ? ? ? ?program;
> - ? ? ? uint16_t ? ? ? ?read_status;
> - ? ? ? uint16_t ? ? ? ?read_id;
> - ? ? ? uint16_t ? ? ? ?erase;
> - ? ? ? uint16_t ? ? ? ?reset;
> - ? ? ? uint16_t ? ? ? ?lock;
> - ? ? ? uint16_t ? ? ? ?unlock;
> - ? ? ? uint16_t ? ? ? ?lock_status;
> -};
> -
> -struct pxa3xx_nand_flash {
> - ? ? ? const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
> - ? ? ? const struct pxa3xx_nand_cmdset *cmdset;
> -
> - ? ? ? uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */
> - ? ? ? uint32_t page_size; ? ? /* Page size in bytes (PAGE_SZ) */
> - ? ? ? uint32_t flash_width; ? /* Width of Flash memory (DWIDTH_M) */
> - ? ? ? uint32_t dfc_width; ? ? /* Width of flash controller(DWIDTH_C) */
> - ? ? ? uint32_t num_blocks; ? ?/* Number of physical blocks in Flash */
> - ? ? ? uint32_t chip_id;
> -};
> -

So does this prevent board code from defining their own timing and etc?

> ?struct pxa3xx_nand_platform_data {
>
> ? ? ? ?/* the data flash bus is shared between the Static Memory
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 98a04b3..9a35d92 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -399,13 +399,6 @@ config MTD_NAND_PXA3xx
> ? ? ? ? ?This enables the driver for the NAND flash device found on
> ? ? ? ? ?PXA3xx processors
>
> -config MTD_NAND_PXA3xx_BUILTIN
> - ? ? ? bool "Use builtin definitions for some NAND chips (deprecated)"
> - ? ? ? depends on MTD_NAND_PXA3xx
> - ? ? ? help
> - ? ? ? ? This enables builtin definitions for some NAND chips. This
> - ? ? ? ? is deprecated in favor of platform specific data.
> -
> ?config MTD_NAND_CM_X270
> ? ? ? ?tristate "Support for NAND Flash on CM-X270 modules"
> ? ? ? ?depends on MTD_NAND && MACH_ARMCORE
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index e02fa4f..013e075 100644
> --- a/drivers/mtd/nand/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/pxa3xx_nand.c

... snipped ...

> ?static struct pxa3xx_nand_timing default_timing;
> ?static struct pxa3xx_nand_flash default_flash;
>
> -static struct pxa3xx_nand_cmdset smallpage_cmdset = {
> - ? ? ? .read1 ? ? ? ? ?= 0x0000,
> - ? ? ? .read2 ? ? ? ? ?= 0x0050,
> - ? ? ? .program ? ? ? ?= 0x1080,
> - ? ? ? .read_status ? ?= 0x0070,
> - ? ? ? .read_id ? ? ? ?= 0x0090,
> - ? ? ? .erase ? ? ? ? ?= 0xD060,
> - ? ? ? .reset ? ? ? ? ?= 0x00FF,
> - ? ? ? .lock ? ? ? ? ? = 0x002A,
> - ? ? ? .unlock ? ? ? ? = 0x2423,
> - ? ? ? .lock_status ? ?= 0x007A,
> -};
> -
> -static struct pxa3xx_nand_cmdset largepage_cmdset = {
> +const static struct pxa3xx_nand_cmdset cmdset = {

So how to handle the difference of command set between smallpage and
largepage?

> ? ? ? ?.read1 ? ? ? ? ?= 0x3000,
> ? ? ? ?.read2 ? ? ? ? ?= 0x0050,
> ? ? ? ?.program ? ? ? ?= 0x1080,
> @@ -203,143 +225,26 @@ static struct pxa3xx_nand_cmdset largepage_cmdset = {
> ? ? ? ?.lock_status ? ?= 0x007A,
> ?};
>
> -#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
> -static struct pxa3xx_nand_timing samsung512MbX16_timing = {
> - ? ? ? .tCH ? ?= 10,
> - ? ? ? .tCS ? ?= 0,
> - ? ? ? .tWH ? ?= 20,
> - ? ? ? .tWP ? ?= 40,

...

> +static struct pxa3xx_nand_timing __devinitdata timing[] = {

Better with some comment columns like below:

  /*	    tCH tCS tWH tWP ... */
> + ? ? ? /* Samsung NAND series */
> + ? ? ? { 10, ?0, 20, 40, 30, 40, 11123, 110, 10, },
> + ? ? ? /* Micron NAND series */
> + ? ? ? { 10, 25, 15, 25, 15, 30, 25000, ?60, 10, },
> + ? ? ? /* ST NAND series */
> + ? ? ? { 10, 35, 15, 25, 15, 25, 25000, ?60, 10, },

Now define something like

#define NAND_TIMING_SAMSUNG	(&timing[0])
#define NAND_TIMING_MICRON	(&timing[1])
#define NAND_TIMING_ST		(&timing[2])

> ?};
>
> -static struct pxa3xx_nand_flash samsung32GbX8 = {
> - ? ? ? .timing ? ? ? ? = &samsung512MbX16_timing,
> - ? ? ? .cmdset ? ? ? ? = &smallpage_cmdset,
> - ? ? ? .page_per_block = 128,
> - ? ? ? .page_size ? ? ?= 4096,
> - ? ? ? .flash_width ? ?= 8,
> - ? ? ? .dfc_width ? ? ?= 8,
> - ? ? ? .num_blocks ? ? = 8192,
> - ? ? ? .chip_id ? ? ? ?= 0xd7ec,
> +static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {

/*	  Chip ID, page per block, page size, flash width, .... */

> + ? ? ? { 0x46ec, ?32, ?512, 16, 16, 4096, &timing[0], },
> + ? ? ? { 0xdaec, ?64, 2048, ?8, ?8, 2048, &timing[0], },
> + ? ? ? { 0xd7ec, 128, 4096, ?8, ?8, 8192, &timing[0], },
> + ? ? ? { 0xa12c, ?64, 2048, ?8, ?8, 1024, &timing[1], },
> + ? ? ? { 0xb12c, ?64, 2048, 16, 16, 1024, &timing[1], },
> + ? ? ? { 0xdc2c, ?64, 2048, ?8, ?8, 4096, &timing[1], },
> + ? ? ? { 0xcc2c, ?64, 2048, 16, 16, 4096, &timing[1], },
> + ? ? ? { 0xba20, ?64, 2048, 16, 16, 2048, &timing[2], },
> ?};

BTW, I like the array above very much.

>
> -static struct pxa3xx_nand_timing micron_timing = {
> - ? ? ? .tCH ? ?= 10,
> - ? ? ? .tCS ? ?= 25,
> - ? ? ? .tWH ? ?= 15,
> - ? ? ? .tWP ? ?= 25,
> - ? ? ? .tRH ? ?= 15,
> - ? ? ? .tRP ? ?= 30,
> - ? ? ? .tR ? ? = 25000,

... snipped ...

> -};
> -#endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
> -
> ?#define NDTR0_tCH(c) ? (min((c), 7) << 19)
> ?#define NDTR0_tCS(c) ? (min((c), 7) << 16)
> ?#define NDTR0_tWH(c) ? (min((c), 7) << 11)
> @@ -412,7 +317,6 @@ static int prepare_read_prog_cmd(struct
> pxa3xx_nand_info *info,
> ? ? ? ? ? ? ? ? ? ? ? ?uint16_t cmd, int column, int page_addr)
> ?{
> ? ? ? ?const struct pxa3xx_nand_flash *f = info->flash_info;
> - ? ? ? const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;

I think it's better to keep a local pointer. Reference within a function
to a global structure is always a bad idea, one day you will find you've
to modify all these references again when you add a new cmdset.

And most of the modifications below can thus be removed and patch simplified.


From eric at eukrea.com  Fri Jun 18 02:30:19 2010
From: eric at eukrea.com (=?ISO-8859-1?Q?Eric_B=E9nard?=)
Date: Fri, 18 Jun 2010 08:30:19 +0200
Subject: [PATCH] video/imxfb: fix suspend when screen is blanked
In-Reply-To: <20100617192257.GA18802@pengutronix.de>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>	<1276801147-4103-2-git-send-email-eric@eukrea.com>	<1276801147-4103-3-git-send-email-eric@eukrea.com>	<1276801147-4103-4-git-send-email-eric@eukrea.com>	<1276801147-4103-5-git-send-email-eric@eukrea.com>
	<20100617192257.GA18802@pengutronix.de>
Message-ID: <4C1B127B.5020305@eukrea.com>

Le 17/06/2010 21:22, Luotao Fu a ?crit :
> I've already submitted a patch to fix this issue:
> http://lkml.org/lkml/2010/6/3/187
>
I also already submited this same patch before :
http://permalink.gmane.org/gmane.linux.ports.arm.kernel/80975

Eric


From eric.y.miao at gmail.com  Fri Jun 18 02:33:59 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 14:33:59 +0800
Subject: [PATCH 02/25] pxa3xx_nand: introduce common timing to reduce read
	id times
In-Reply-To: <AANLkTim1qcVoqSS7T8bE0Vsu6phC2iY_Ok671WYHcD0z@mail.gmail.com>
References: <AANLkTim1qcVoqSS7T8bE0Vsu6phC2iY_Ok671WYHcD0z@mail.gmail.com>
Message-ID: <AANLkTil6QDRdh3s63J9Mm-B1qjMcnYjEEm-W5lC1NXVb@mail.gmail.com>

On Fri, Jun 18, 2010 at 1:33 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> From 832379d0da4d772e45872de365053f9a15733967 Mon Sep 17 00:00:00 2001
> From: Lei Wen <leiwen at marvell.com>
> Date: Wed, 2 Jun 2010 21:50:25 +0800
> Subject: [PATCH 02/25] pxa3xx_nand: introduce common timing to reduce
> read id times
>
> We certainly don't need to send read id command times by times, since
> we already know what the id is after the first read id...
>
> So create a common timing which could ensure it would successfully read id
> out all supported chip. Then follow the build-in table to reconfigure
> the timing.

This is clever trick we'd like to have. And I'd prefer to call this a
'loose timing'
or a 'default safe timing' instead of 'common timing'.

>
> Signed-off-by: Lei Wen <leiwen at marvell.com>
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
> ---
> ?drivers/mtd/nand/pxa3xx_nand.c | ? 72 ++++++++++++++++-----------------------
> ?1 files changed, 30 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index 013e075..f939083 100644
> --- a/drivers/mtd/nand/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/pxa3xx_nand.c
> @@ -226,23 +226,26 @@ const static struct pxa3xx_nand_cmdset cmdset = {
> ?};
>
> ?static struct pxa3xx_nand_timing __devinitdata timing[] = {
> + ? ? ? /* common timing used to detect flash id */
> + ? ? ? { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },

Make sure this is the loose and safe enough timing.

> ? ? ? ?/* Samsung NAND series */
> - ? ? ? { 10, ?0, 20, 40, 30, 40, 11123, 110, 10, },
> + ? ? ? { 10, ?0, 20, ?40, 30, ?40, 11123, 110, 10, },
> ? ? ? ?/* Micron NAND series */
> - ? ? ? { 10, 25, 15, 25, 15, 30, 25000, ?60, 10, },
> + ? ? ? { 10, 25, 15, ?25, 15, ?30, 25000, ?60, 10, },
> ? ? ? ?/* ST NAND series */
> - ? ? ? { 10, 35, 15, 25, 15, 25, 25000, ?60, 10, },
> + ? ? ? { 10, 35, 15, ?25, 15, ?25, 25000, ?60, 10, },
> ?};
>
> ?static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
> - ? ? ? { 0x46ec, ?32, ?512, 16, 16, 4096, &timing[0], },
> - ? ? ? { 0xdaec, ?64, 2048, ?8, ?8, 2048, &timing[0], },
> - ? ? ? { 0xd7ec, 128, 4096, ?8, ?8, 8192, &timing[0], },
> - ? ? ? { 0xa12c, ?64, 2048, ?8, ?8, 1024, &timing[1], },
> - ? ? ? { 0xb12c, ?64, 2048, 16, 16, 1024, &timing[1], },
> - ? ? ? { 0xdc2c, ?64, 2048, ?8, ?8, 4096, &timing[1], },
> - ? ? ? { 0xcc2c, ?64, 2048, 16, 16, 4096, &timing[1], },
> - ? ? ? { 0xba20, ?64, 2048, 16, 16, 2048, &timing[2], },
> + ? ? ? { ? ? ?0, ? 0, ? ?0, ?0, ?0, ? ?0, &timing[0], },
> + ? ? ? { 0x46ec, ?32, ?512, 16, 16, 4096, &timing[1], },
> + ? ? ? { 0xdaec, ?64, 2048, ?8, ?8, 2048, &timing[1], },
> + ? ? ? { 0xd7ec, 128, 4096, ?8, ?8, 8192, &timing[1], },
> + ? ? ? { 0xa12c, ?64, 2048, ?8, ?8, 1024, &timing[2], },
> + ? ? ? { 0xb12c, ?64, 2048, 16, 16, 1024, &timing[2], },
> + ? ? ? { 0xdc2c, ?64, 2048, ?8, ?8, 4096, &timing[2], },
> + ? ? ? { 0xcc2c, ?64, 2048, 16, 16, 4096, &timing[2], },
> + ? ? ? { 0xba20, ?64, 2048, 16, 16, 2048, &timing[3], },
> ?};
>
> ?#define NDTR0_tCH(c) ? (min((c), 7) << 19)
> @@ -859,12 +862,6 @@ static int pxa3xx_nand_config_flash(struct
> pxa3xx_nand_info *info,
> ? ? ? ?struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
> ? ? ? ?uint32_t ndcr = 0x00000FFF; /* disable all interrupts */
>
> - ? ? ? if (f->page_size != 2048 && f->page_size != 512)
> - ? ? ? ? ? ? ? return -EINVAL;
> -
> - ? ? ? if (f->flash_width != 16 && f->flash_width != 8)
> - ? ? ? ? ? ? ? return -EINVAL;
> -

I do think these are sanity check, that's useful to prevent incorrectly defined
data (esp. coming from board code). Can we define the loose flash type as:

> ?static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
> + ? ? ? { ?0x0000, ? 0, ? ?512, ?8, ?8, ? ?0, &timing[0], },
> + ? ? ? { 0x46ec, ?32, ?512, 16, 16, 4096, &timing[1], },
> + ? ? ? { 0xdaec, ?64, 2048, ?8, ?8, 2048, &timing[1], },

with a comment of /* default flash type to detect ID */?

My understanding is the minimum requirement to detect the NAND ID is a
loose timing and 512 small page, 8-bit wide bus, so with a chip_id being
0x0000, that should be enough to tell it's a special flash type to detect ID.

> ? ? ? ?/* calculate flash information */
> ? ? ? ?info->oob_size = (f->page_size == 2048) ? 64 : 16;
> ? ? ? ?info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
> @@ -976,36 +973,27 @@ static int pxa3xx_nand_detect_flash(struct
> pxa3xx_nand_info *info,
> ? ? ? ? ? ? ? ?if (pxa3xx_nand_detect_config(info) == 0)
> ? ? ? ? ? ? ? ? ? ? ? ?return 0;
>
> - ? ? ? for (i = 0; i<pdata->num_flash; ++i) {
> - ? ? ? ? ? ? ? f = pdata->flash + i;
> -
> - ? ? ? ? ? ? ? if (pxa3xx_nand_config_flash(info, f))
> - ? ? ? ? ? ? ? ? ? ? ? continue;
> -
> - ? ? ? ? ? ? ? if (__readid(info, &id))
> - ? ? ? ? ? ? ? ? ? ? ? continue;
> -
> - ? ? ? ? ? ? ? if (id == f->chip_id)
> - ? ? ? ? ? ? ? ? ? ? ? return 0;
> - ? ? ? }
> -
> - ? ? ? for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
> -
> - ? ? ? ? ? ? ? f = &builtin_flash_types[i];
> -
> - ? ? ? ? ? ? ? if (pxa3xx_nand_config_flash(info, f))
> - ? ? ? ? ? ? ? ? ? ? ? continue;
> -
> - ? ? ? ? ? ? ? if (__readid(info, &id))
> - ? ? ? ? ? ? ? ? ? ? ? continue;
> -
> - ? ? ? ? ? ? ? if (id == f->chip_id)
> + ? ? ? f = &builtin_flash_types[0];
> + ? ? ? pxa3xx_nand_config_flash(info, f);
> + ? ? ? if (__readid(info, &id))
> + ? ? ? ? ? ? ? goto fail_detect;
> +
> + ? ? ? for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
> + ? ? ? ? ? ? ? if (i < pdata->num_flash)
> + ? ? ? ? ? ? ? ? ? ? ? f = pdata->flash + i;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? f = &builtin_flash_types[i - pdata->num_flash + 1];

This looks a bit tricky and difficult to read, can you improve the
readability here?

> + ? ? ? ? ? ? ? if (f->chip_id == id) {
> + ? ? ? ? ? ? ? ? ? ? ? dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
> + ? ? ? ? ? ? ? ? ? ? ? pxa3xx_nand_config_flash(info, f);
> ? ? ? ? ? ? ? ? ? ? ? ?return 0;
> + ? ? ? ? ? ? ? }
> ? ? ? ?}
>
> ? ? ? ?dev_warn(&info->pdev->dev,
> - ? ? ? ? ? ? ? ?"failed to detect configured nand flash; found %04x instead of\n",
> + ? ? ? ? ? ? ? ? ? ? ? "failed to detect configured nand flash; found %04x instead of\n",
> ? ? ? ? ? ? ? ? id);
> +fail_detect:
> ? ? ? ?return -ENODEV;
> ?}
>

I'm generally OK with the idea.


From eric.y.miao at gmail.com  Fri Jun 18 02:40:17 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 14:40:17 +0800
Subject: [PATCH 03/25] pxa3xx_nand: remove the flash info in driver 
	structure
In-Reply-To: <AANLkTimbCSM3Kk-Mq3MhRDyhHAaERR-dXhtuplauB3ki@mail.gmail.com>
References: <AANLkTimbCSM3Kk-Mq3MhRDyhHAaERR-dXhtuplauB3ki@mail.gmail.com>
Message-ID: <AANLkTilnlE7hl4FKo5qRJ4PeTCuxA3Mfm13eedGPehrk@mail.gmail.com>

On Fri, Jun 18, 2010 at 1:33 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> From 643765e6ae0f37902321f31e14b565896217dd3a Mon Sep 17 00:00:00 2001
> From: Lei Wen <leiwen at marvell.com>
> Date: Wed, 2 Jun 2010 21:54:33 +0800
> Subject: [PATCH 03/25] pxa3xx_nand: remove the flash info in driver structure
>
> After probe, all info already transfer to driver structure.
> There is no need to keep the original flash info.
> So that we could safely free the flash info in memory, which may grows
> larger when more flash is suported.
>

Some of the changes should be separated from my POV? Like the
change to oob_size, and pxa3xx_nand_resume?


From eric.y.miao at gmail.com  Fri Jun 18 02:43:08 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 14:43:08 +0800
Subject: [PATCH 04/25] pxa3xx_nand: make scan procedure more clear
In-Reply-To: <AANLkTiliVtvBEmJPgkha444k9XGB_dNm0lQ9TCif8AAj@mail.gmail.com>
References: <AANLkTiliVtvBEmJPgkha444k9XGB_dNm0lQ9TCif8AAj@mail.gmail.com>
Message-ID: <AANLkTikKNw7purkGZoYMN7rWuHwkLdILSoDAaIzpugYe@mail.gmail.com>

On Fri, Jun 18, 2010 at 1:33 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> From 9023ee9b020ebda0c6ee299807a7fd2eb8fae53d Mon Sep 17 00:00:00 2001
> From: Lei Wen <leiwen at marvell.com>
> Date: Sun, 16 May 2010 17:03:52 +0800
> Subject: [PATCH 04/25] pxa3xx_nand: make scan procedure more clear
>

Looks like a good cleanup to me. The git diff, though, seems to generate poor
differences here.

> Signed-off-by: Lei Wen <leiwen at marvell.com>
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
> ---
> ?drivers/mtd/nand/pxa3xx_nand.c | ? 88 ++++++++++++++++++++++-----------------
> ?1 files changed, 50 insertions(+), 38 deletions(-)
>
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index 291610a..1f52701 100644
> --- a/drivers/mtd/nand/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/pxa3xx_nand.c
> @@ -160,6 +160,7 @@ struct pxa3xx_nand_info {
> ? ? ? ?unsigned int ? ? ? ? ? ?buf_start;
> ? ? ? ?unsigned int ? ? ? ? ? ?buf_count;
>
> + ? ? ? struct mtd_info ? ? ? ? *mtd;
> ? ? ? ?/* DMA information */
> ? ? ? ?int ? ? ? ? ? ? ? ? ? ? drcmr_dat;
> ? ? ? ?int ? ? ? ? ? ? ? ? ? ? drcmr_cmd;
> @@ -1105,21 +1106,13 @@ static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
> ? ? ? ?this->chip_delay = 25;
> ?}
>
> -static int __devinit pxa3xx_nand_probe(struct platform_device *pdev)
> +static int alloc_nand_resource(struct platform_device *pdev)
> ?{
> - ? ? ? struct pxa3xx_nand_platform_data *pdata;
> + ? ? ? struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
> ? ? ? ?struct pxa3xx_nand_info *info;
> - ? ? ? struct nand_chip *this;
> ? ? ? ?struct mtd_info *mtd;
> ? ? ? ?struct resource *r;
> - ? ? ? int ret = 0, irq;
> -
> - ? ? ? pdata = pdev->dev.platform_data;
> -
> - ? ? ? if (!pdata) {
> - ? ? ? ? ? ? ? dev_err(&pdev->dev, "no platform data defined\n");
> - ? ? ? ? ? ? ? return -ENODEV;
> - ? ? ? }
> + ? ? ? int ret, irq;
>
> ? ? ? ?mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
> ? ? ? ? ? ? ? ? ? ? ? ?GFP_KERNEL);
> @@ -1131,8 +1124,8 @@ static int __devinit pxa3xx_nand_probe(struct
> platform_device *pdev)
> ? ? ? ?info = (struct pxa3xx_nand_info *)(&mtd[1]);
> ? ? ? ?info->pdev = pdev;
>
> - ? ? ? this = &info->nand_chip;
> ? ? ? ?mtd->priv = info;
> + ? ? ? info->mtd = mtd;
> ? ? ? ?mtd->owner = THIS_MODULE;
>
> ? ? ? ?info->clk = clk_get(&pdev->dev, NULL);
> @@ -1210,27 +1203,9 @@ static int __devinit pxa3xx_nand_probe(struct
> platform_device *pdev)
> ? ? ? ?}
>
> ? ? ? ?pxa3xx_nand_init_mtd(mtd, info);
> + ? ? ? platform_set_drvdata(pdev, info);
>
> - ? ? ? platform_set_drvdata(pdev, mtd);
> -
> - ? ? ? if (nand_scan(mtd, 1)) {
> - ? ? ? ? ? ? ? dev_err(&pdev->dev, "failed to scan nand\n");
> - ? ? ? ? ? ? ? ret = -ENXIO;
> - ? ? ? ? ? ? ? goto fail_free_irq;
> - ? ? ? }
> -
> - ? ? ? if (mtd_has_cmdlinepart()) {
> - ? ? ? ? ? ? ? static const char *probes[] = { "cmdlinepart", NULL };
> - ? ? ? ? ? ? ? struct mtd_partition *parts;
> - ? ? ? ? ? ? ? int nr_parts;
> -
> - ? ? ? ? ? ? ? nr_parts = parse_mtd_partitions(mtd, probes, &parts, 0);
> -
> - ? ? ? ? ? ? ? if (nr_parts)
> - ? ? ? ? ? ? ? ? ? ? ? return add_mtd_partitions(mtd, parts, nr_parts);
> - ? ? ? }
> -
> - ? ? ? return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
> + ? ? ? return 0;
>
> ?fail_free_irq:
> ? ? ? ?free_irq(irq, info);
> @@ -1255,8 +1230,8 @@ fail_free_mtd:
>
> ?static int pxa3xx_nand_remove(struct platform_device *pdev)
> ?{
> - ? ? ? struct mtd_info *mtd = platform_get_drvdata(pdev);
> - ? ? ? struct pxa3xx_nand_info *info = mtd->priv;
> + ? ? ? struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
> + ? ? ? struct mtd_info *mtd = info->mtd;
> ? ? ? ?struct resource *r;
> ? ? ? ?int irq;
>
> @@ -1285,11 +1260,48 @@ static int pxa3xx_nand_remove(struct
> platform_device *pdev)
> ? ? ? ?return 0;
> ?}
>
> +static int __devinit pxa3xx_nand_probe(struct platform_device *pdev)
> +{
> + ? ? ? struct pxa3xx_nand_platform_data *pdata;
> + ? ? ? struct pxa3xx_nand_info *info;
> + ? ? ? int ret;
> +
> + ? ? ? pdata = pdev->dev.platform_data;
> + ? ? ? if (!pdata) {
> + ? ? ? ? ? ? ? dev_err(&pdev->dev, "no platform data defined\n");
> + ? ? ? ? ? ? ? return -ENODEV;
> + ? ? ? }
> +
> + ? ? ? ret = alloc_nand_resource(pdev);
> + ? ? ? if (ret)
> + ? ? ? ? ? ? ? return ret;
> +
> + ? ? ? info = platform_get_drvdata(pdev);
> + ? ? ? if (nand_scan(info->mtd, 1)) {
> + ? ? ? ? ? ? ? dev_err(&pdev->dev, "failed to scan nand\n");
> + ? ? ? ? ? ? ? pxa3xx_nand_remove(pdev);
> + ? ? ? ? ? ? ? return -ENODEV;
> + ? ? ? }
> +
> + ? ? ? if (mtd_has_cmdlinepart()) {
> + ? ? ? ? ? ? ? static const char *probes[] = { "cmdlinepart", NULL };
> + ? ? ? ? ? ? ? struct mtd_partition *parts;
> + ? ? ? ? ? ? ? int nr_parts;
> +
> + ? ? ? ? ? ? ? nr_parts = parse_mtd_partitions(mtd, probes, &parts, 0);
> +
> + ? ? ? ? ? ? ? if (nr_parts)
> + ? ? ? ? ? ? ? ? ? ? ? return add_mtd_partitions(mtd, parts, nr_parts);
> + ? ? ? }
> +
> + ? ? ? return add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts);
> +}
> +
> ?#ifdef CONFIG_PM
> ?static int pxa3xx_nand_suspend(struct platform_device *pdev,
> pm_message_t state)
> ?{
> - ? ? ? struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
> - ? ? ? struct pxa3xx_nand_info *info = mtd->priv;
> + ? ? ? struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
> + ? ? ? struct mtd_info *mtd = info->mtd;
>
> ? ? ? ?if (info->state != STATE_READY) {
> ? ? ? ? ? ? ? ?dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
> @@ -1301,8 +1313,8 @@ static int pxa3xx_nand_suspend(struct
> platform_device *pdev, pm_message_t state)
>
> ?static int pxa3xx_nand_resume(struct platform_device *pdev)
> ?{
> - ? ? ? struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
> - ? ? ? struct pxa3xx_nand_info *info = mtd->priv;
> + ? ? ? struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
> + ? ? ? struct mtd_info *mtd = info->mtd;
>
> ? ? ? ?nand_writel(info, NDTR0CS0, info->ndtr0cs0);
> ? ? ? ?nand_writel(info, NDTR1CS0, info->ndtr1cs0);
> --
> 1.7.0.4
>


From eric.y.miao at gmail.com  Fri Jun 18 02:50:37 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 14:50:37 +0800
Subject: [PATCH 05/25] pxa3xx_nand: rework irq logic
In-Reply-To: <AANLkTimvhEWIDupsj3Ty8vB9ualwU9RsaIxa0CDgWgYQ@mail.gmail.com>
References: <AANLkTimvhEWIDupsj3Ty8vB9ualwU9RsaIxa0CDgWgYQ@mail.gmail.com>
Message-ID: <AANLkTikTzNY2hI0JDTOOZpGeOPc_MU79jVJ_1L9XxA_e@mail.gmail.com>

On Fri, Jun 18, 2010 at 1:34 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> From 18d589a078871a09dec0862241fedd2d1d07be85 Mon Sep 17 00:00:00 2001
> From: Lei Wen <leiwen at marvell.com>
> Date: Mon, 31 May 2010 14:05:46 +0800
> Subject: [PATCH 05/25] pxa3xx_nand: rework irq logic
>
> Enable all irq when we start the nand controller, and
> put all the transaction logic in the pxa3xx_nand_irq.
>

Didn't look into the change too much, but the idea sounds to me like
chaining all the logic with different IRQ events, which was my original
reason of having different states. And considering the page read/write
is actually to an internal SRAM within the controller, I guess it's quick
enough. (though I'd suggest to do some experiments of time profiling
to see if it's going to increase the interrupt latency)

> By doing this way, we could dramatically increase the
> performance by avoid unnecessary delay.
>

The removal of __read_id() doesn't look to be part of this patch, no?

> Signed-off-by: Lei Wen <leiwen at marvell.com>
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
> ---
> ?drivers/mtd/nand/pxa3xx_nand.c | ?382 +++++++++++++++-------------------------
> ?1 files changed, 140 insertions(+), 242 deletions(-)
>
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index 1f52701..753346f 100644
> --- a/drivers/mtd/nand/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/pxa3xx_nand.c
> @@ -27,6 +27,7 @@
> ?#include <plat/pxa3xx_nand.h>
>
> ?#define ? ? ? ?CHIP_DELAY_TIMEOUT ? ? ?(2 * HZ/10)
> +#define NAND_STOP_DELAY ? ? ? ? ? ? ? ?(2 * HZ/50)
>
> ?/* registers and bit definitions */
> ?#define NDCR ? ? ? ? ? (0x00) /* Control register */
> @@ -49,6 +50,7 @@
> ?#define NDCR_DWIDTH_M ? ? ? ? ?(0x1 << 26)
> ?#define NDCR_PAGE_SZ ? ? ? ? ? (0x1 << 24)
> ?#define NDCR_NCSX ? ? ? ? ? ? ?(0x1 << 23)
> +#define NDCR_STOP_ON_UNCOR ? ? (0x1 << 22)
> ?#define NDCR_ND_MODE ? ? ? ? ? (0x3 << 21)
> ?#define NDCR_NAND_MODE ? ? ? ? (0x0)
> ?#define NDCR_CLR_PG_CNT ? ? ? ? ? ? ? ?(0x1 << 20)
> @@ -59,9 +61,11 @@
> ?#define NDCR_RA_START ? ? ? ? ?(0x1 << 15)
> ?#define NDCR_PG_PER_BLK ? ? ? ? ? ? ? ?(0x1 << 14)
> ?#define NDCR_ND_ARB_EN ? ? ? ? (0x1 << 12)
> +#define NDCR_INT_MASK ? ? ? ? ? (0xFFF)
>
> ?#define NDSR_MASK ? ? ? ? ? ? ?(0xfff)
> -#define NDSR_RDY ? ? ? ? ? ? ? (0x1 << 11)
> +#define NDSR_RDY ? ? ? ? ? ? ? ?(0x1 << 12)
> +#define NDSR_FLASH_RDY ? ? ? ? ?(0x1 << 11)
> ?#define NDSR_CS0_PAGED ? ? ? ? (0x1 << 10)
> ?#define NDSR_CS1_PAGED ? ? ? ? (0x1 << 9)
> ?#define NDSR_CS0_CMDD ? ? ? ? ?(0x1 << 8)
> @@ -104,13 +108,14 @@ enum {
> ?};
>
> ?enum {
> - ? ? ? STATE_READY ? ? = 0,
> - ? ? ? STATE_CMD_HANDLE,
> - ? ? ? STATE_DMA_READING,
> - ? ? ? STATE_DMA_WRITING,
> - ? ? ? STATE_DMA_DONE,
> - ? ? ? STATE_PIO_READING,
> - ? ? ? STATE_PIO_WRITING,
> + ? ? ? STATE_CMD_WAIT_DONE ? ? = 1,
> + ? ? ? STATE_DATA_PROCESSING ? = (1 << 1),
> + ? ? ? STATE_DATA_DONE ? ? ? ? = (1 << 2),
> + ? ? ? STATE_PAGE_DONE ? ? ? ? = (1 << 3),
> + ? ? ? STATE_CMD_DONE ? ? ? ? ?= (1 << 4),
> + ? ? ? STATE_READY ? ? ? ? ? ? = (1 << 5),
> + ? ? ? STATE_CMD_PREPARED ? ? ?= (1 << 6),
> + ? ? ? STATE_IS_WRITE ? ? ? ? ?= (1 << 7),
> ?};
>
> ?struct pxa3xx_nand_timing {
> @@ -305,25 +310,6 @@ static void pxa3xx_nand_set_timing(struct
> pxa3xx_nand_info *info,
> ? ? ? ?nand_writel(info, NDTR1CS0, ndtr1);
> ?}
>
> -#define WAIT_EVENT_TIMEOUT ? ? 10
> -
> -static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
> -{
> - ? ? ? int timeout = WAIT_EVENT_TIMEOUT;
> - ? ? ? uint32_t ndsr;
> -
> - ? ? ? while (timeout--) {
> - ? ? ? ? ? ? ? ndsr = nand_readl(info, NDSR) & NDSR_MASK;
> - ? ? ? ? ? ? ? if (ndsr & event) {
> - ? ? ? ? ? ? ? ? ? ? ? nand_writel(info, NDSR, ndsr);
> - ? ? ? ? ? ? ? ? ? ? ? return 0;
> - ? ? ? ? ? ? ? }
> - ? ? ? ? ? ? ? udelay(10);
> - ? ? ? }
> -
> - ? ? ? return -ETIMEDOUT;
> -}
> -
> ?static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
> ?{
> ? ? ? ?int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
> @@ -343,7 +329,47 @@ static void pxa3xx_set_datasize(struct
> pxa3xx_nand_info *info)
> ? ? ? ?}
> ?}
>
> -static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
> +/**
> + * NOTE: it is a must to set ND_RUN firstly, then write
> + * command buffer, otherwise, it does not work.
> + * We enable all the interrupt at the same time, and
> + * let pxa3xx_nand_irq to handle all logic.
> + */
> +static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
> +{
> + ? ? ? uint32_t ndcr;
> +
> + ? ? ? ndcr = info->reg_ndcr;
> + ? ? ? ndcr |= NDCR_ECC_EN;
> + ? ? ? ndcr |= info->use_dma ? NDCR_DMA_EN : NDCR_STOP_ON_UNCOR;
> + ? ? ? ndcr |= NDCR_ND_RUN;
> +
> + ? ? ? /* clear status bits and run */
> + ? ? ? nand_writel(info, NDCR, 0);
> + ? ? ? nand_writel(info, NDSR, NDSR_MASK);
> + ? ? ? nand_writel(info, NDCR, ndcr);
> +}
> +
> +static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
> +{
> + ? ? ? uint32_t ndcr;
> + ? ? ? int timeout = NAND_STOP_DELAY;
> +
> + ? ? ? /* wait RUN bit in NDCR become 0 */
> + ? ? ? do {
> + ? ? ? ? ? ? ? /* clear status bits */
> + ? ? ? ? ? ? ? nand_writel(info, NDSR, NDSR_MASK);
> + ? ? ? ? ? ? ? ndcr = nand_readl(info, NDCR);
> + ? ? ? ? ? ? ? udelay(1);
> + ? ? ? } while ((ndcr & NDCR_ND_RUN) && (timeout -- > 0));
> +
> + ? ? ? if (timeout <= 0) {
> + ? ? ? ? ? ? ? ndcr &= ~(NDCR_ND_RUN);
> + ? ? ? ? ? ? ? nand_writel(info, NDCR, ndcr);
> + ? ? ? }
> +}
> +
> +static void prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
> ? ? ? ? ? ? ? ?uint16_t cmd, int column, int page_addr)
> ?{
> ? ? ? ?pxa3xx_set_datasize(info);
> @@ -369,21 +395,18 @@ static int prepare_read_prog_cmd(struct
> pxa3xx_nand_info *info,
>
> ? ? ? ?if (cmd == cmdset.program)
> ? ? ? ? ? ? ? ?info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
> -
> - ? ? ? return 0;
> ?}
>
> -static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
> +static void prepare_erase_cmd(struct pxa3xx_nand_info *info,
> ? ? ? ? ? ? ? ? ? ? ? ?uint16_t cmd, int page_addr)
> ?{
> ? ? ? ?info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
> ? ? ? ?info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
> ? ? ? ?info->ndcb1 = page_addr;
> ? ? ? ?info->ndcb2 = 0;
> - ? ? ? return 0;
> ?}
>
> -static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
> +static void prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
> ?{
> ? ? ? ?info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
> ? ? ? ?info->ndcb1 = 0;
> @@ -398,10 +421,7 @@ static int prepare_other_cmd(struct
> pxa3xx_nand_info *info, uint16_t cmd)
> ? ? ? ?} else if (cmd == cmdset.reset || cmd == cmdset.lock ||
> ? ? ? ? ? ? ? ? ? cmd == cmdset.unlock) {
> ? ? ? ? ? ? ? ?info->ndcb0 |= NDCB0_CMD_TYPE(5);
> - ? ? ? } else
> - ? ? ? ? ? ? ? return -EINVAL;
> -
> - ? ? ? return 0;
> + ? ? ? }
> ?}
>
> ?static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
> @@ -420,71 +440,23 @@ static void disable_int(struct pxa3xx_nand_info
> *info, uint32_t int_mask)
> ? ? ? ?nand_writel(info, NDCR, ndcr | int_mask);
> ?}
>
> -/* NOTE: it is a must to set ND_RUN firstly, then write command buffer
> - * otherwise, it does not work
> - */
> -static int write_cmd(struct pxa3xx_nand_info *info)
> -{
> - ? ? ? uint32_t ndcr;
> -
> - ? ? ? /* clear status bits and run */
> - ? ? ? nand_writel(info, NDSR, NDSR_MASK);
> -
> - ? ? ? ndcr = info->reg_ndcr;
> -
> - ? ? ? ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
> - ? ? ? ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
> - ? ? ? ndcr |= NDCR_ND_RUN;
> -
> - ? ? ? nand_writel(info, NDCR, ndcr);
> -
> - ? ? ? if (wait_for_event(info, NDSR_WRCMDREQ)) {
> - ? ? ? ? ? ? ? printk(KERN_ERR "timed out writing command\n");
> - ? ? ? ? ? ? ? return -ETIMEDOUT;
> - ? ? ? }
> -
> - ? ? ? nand_writel(info, NDCB0, info->ndcb0);
> - ? ? ? nand_writel(info, NDCB0, info->ndcb1);
> - ? ? ? nand_writel(info, NDCB0, info->ndcb2);
> - ? ? ? return 0;
> -}
> -
> -static int handle_data_pio(struct pxa3xx_nand_info *info)
> +static void handle_data_pio(struct pxa3xx_nand_info *info)
> ?{
> - ? ? ? int ret, timeout = CHIP_DELAY_TIMEOUT;
> -
> - ? ? ? switch (info->state) {
> - ? ? ? case STATE_PIO_WRITING:
> + ? ? ? if (info->state & STATE_IS_WRITE) {
> ? ? ? ? ? ? ? ?__raw_writesl(info->mmio_base + NDDB, info->data_buff,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIV_ROUND_UP(info->data_size, 4));
> ? ? ? ? ? ? ? ?if (info->oob_size > 0)
> ? ? ? ? ? ? ? ? ? ? ? ?__raw_writesl(info->mmio_base + NDDB, info->oob_buff,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIV_ROUND_UP(info->oob_size, 4));
>
> - ? ? ? ? ? ? ? enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
> -
> - ? ? ? ? ? ? ? ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
> - ? ? ? ? ? ? ? if (!ret) {
> - ? ? ? ? ? ? ? ? ? ? ? printk(KERN_ERR "program command time out\n");
> - ? ? ? ? ? ? ? ? ? ? ? return -1;
> - ? ? ? ? ? ? ? }
> - ? ? ? ? ? ? ? break;
> - ? ? ? case STATE_PIO_READING:
> + ? ? ? }
> + ? ? ? else {
> ? ? ? ? ? ? ? ?__raw_readsl(info->mmio_base + NDDB, info->data_buff,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIV_ROUND_UP(info->data_size, 4));
> ? ? ? ? ? ? ? ?if (info->oob_size > 0)
> ? ? ? ? ? ? ? ? ? ? ? ?__raw_readsl(info->mmio_base + NDDB, info->oob_buff,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?DIV_ROUND_UP(info->oob_size, 4));
> -
> - ? ? ? ? ? ? ? break;
> - ? ? ? default:
> - ? ? ? ? ? ? ? printk(KERN_ERR "%s: invalid state %d\n", __func__,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? info->state);
> - ? ? ? ? ? ? ? return -EINVAL;
> ? ? ? ?}
> -
> - ? ? ? info->state = STATE_READY;
> - ? ? ? return 0;
> ?}
>
> ?static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
> @@ -520,93 +492,59 @@ static void pxa3xx_nand_data_dma_irq(int
> channel, void *data)
>
> ? ? ? ?if (dcsr & DCSR_BUSERR) {
> ? ? ? ? ? ? ? ?info->retcode = ERR_DMABUSERR;
> - ? ? ? ? ? ? ? complete(&info->cmd_complete);
> ? ? ? ?}
>
> - ? ? ? if (info->state == STATE_DMA_WRITING) {
> - ? ? ? ? ? ? ? info->state = STATE_DMA_DONE;
> - ? ? ? ? ? ? ? enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
> - ? ? ? } else {
> - ? ? ? ? ? ? ? info->state = STATE_READY;
> - ? ? ? ? ? ? ? complete(&info->cmd_complete);
> - ? ? ? }
> + ? ? ? enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
> ?}
>
> ?static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
> ?{
> ? ? ? ?struct pxa3xx_nand_info *info = devid;
> - ? ? ? unsigned int status;
> + ? ? ? unsigned int status, is_completed = 0;
>
> ? ? ? ?status = nand_readl(info, NDSR);
>
> - ? ? ? if (status & (NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR)) {
> - ? ? ? ? ? ? ? if (status & NDSR_DBERR)
> - ? ? ? ? ? ? ? ? ? ? ? info->retcode = ERR_DBERR;
> - ? ? ? ? ? ? ? else if (status & NDSR_SBERR)
> - ? ? ? ? ? ? ? ? ? ? ? info->retcode = ERR_SBERR;
> -
> - ? ? ? ? ? ? ? disable_int(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
> + ? ? ? if (status & NDSR_DBERR)
> + ? ? ? ? ? ? ? info->retcode = ERR_DBERR;
> + ? ? ? if (status & NDSR_SBERR)
> + ? ? ? ? ? ? ? info->retcode = ERR_SBERR;
> + ? ? ? if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
>
> + ? ? ? ? ? ? ? info->state |= STATE_DATA_PROCESSING;
> + ? ? ? ? ? ? ? /* whether use dma to transfer data */
> ? ? ? ? ? ? ? ?if (info->use_dma) {
> - ? ? ? ? ? ? ? ? ? ? ? info->state = STATE_DMA_READING;
> + ? ? ? ? ? ? ? ? ? ? ? disable_int(info, NDSR_WRDREQ);
> ? ? ? ? ? ? ? ? ? ? ? ?start_data_dma(info, 0);
> - ? ? ? ? ? ? ? } else {
> - ? ? ? ? ? ? ? ? ? ? ? info->state = STATE_PIO_READING;
> - ? ? ? ? ? ? ? ? ? ? ? complete(&info->cmd_complete);
> - ? ? ? ? ? ? ? }
> - ? ? ? } else if (status & NDSR_WRDREQ) {
> - ? ? ? ? ? ? ? disable_int(info, NDSR_WRDREQ);
> - ? ? ? ? ? ? ? if (info->use_dma) {
> - ? ? ? ? ? ? ? ? ? ? ? info->state = STATE_DMA_WRITING;
> - ? ? ? ? ? ? ? ? ? ? ? start_data_dma(info, 1);
> - ? ? ? ? ? ? ? } else {
> - ? ? ? ? ? ? ? ? ? ? ? info->state = STATE_PIO_WRITING;
> - ? ? ? ? ? ? ? ? ? ? ? complete(&info->cmd_complete);
> - ? ? ? ? ? ? ? }
> - ? ? ? } else if (status & (NDSR_CS0_BBD | NDSR_CS0_CMDD)) {
> - ? ? ? ? ? ? ? if (status & NDSR_CS0_BBD)
> - ? ? ? ? ? ? ? ? ? ? ? info->retcode = ERR_BBERR;
> + ? ? ? ? ? ? ? ? ? ? ? goto NORMAL_IRQ_EXIT;
> + ? ? ? ? ? ? ? } else
> + ? ? ? ? ? ? ? ? ? ? ? handle_data_pio(info);
>
> - ? ? ? ? ? ? ? disable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
> - ? ? ? ? ? ? ? info->state = STATE_READY;
> - ? ? ? ? ? ? ? complete(&info->cmd_complete);
> + ? ? ? ? ? ? ? info->state |= STATE_DATA_DONE;
> ? ? ? ?}
> - ? ? ? nand_writel(info, NDSR, status);
> - ? ? ? return IRQ_HANDLED;
> -}
> -
> -static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info *info, uint32_t event)
> -{
> - ? ? ? uint32_t ndcr;
> - ? ? ? int ret, timeout = CHIP_DELAY_TIMEOUT;
> -
> - ? ? ? if (write_cmd(info)) {
> - ? ? ? ? ? ? ? info->retcode = ERR_SENDCMD;
> - ? ? ? ? ? ? ? goto fail_stop;
> + ? ? ? if (status & NDSR_CS0_CMDD) {
> + ? ? ? ? ? ? ? info->state |= STATE_CMD_DONE;
> + ? ? ? ? ? ? ? is_completed = 1;
> ? ? ? ?}
> -
> - ? ? ? info->state = STATE_CMD_HANDLE;
> -
> - ? ? ? enable_int(info, event);
> -
> - ? ? ? ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
> - ? ? ? if (!ret) {
> - ? ? ? ? ? ? ? printk(KERN_ERR "command execution timed out\n");
> - ? ? ? ? ? ? ? info->retcode = ERR_SENDCMD;
> - ? ? ? ? ? ? ? goto fail_stop;
> + ? ? ? if (status & NDSR_FLASH_RDY)
> + ? ? ? ? ? ? ? info->state |= STATE_READY;
> + ? ? ? if (status & NDSR_CS0_PAGED)
> + ? ? ? ? ? ? ? info->state |= STATE_PAGE_DONE;
> +
> + ? ? ? if (status & NDSR_WRCMDREQ) {
> + ? ? ? ? ? ? ? nand_writel(info, NDSR, NDSR_WRCMDREQ);
> + ? ? ? ? ? ? ? status &= ~NDSR_WRCMDREQ;
> + ? ? ? ? ? ? ? info->state |= STATE_CMD_WAIT_DONE;
> + ? ? ? ? ? ? ? nand_writel(info, NDCB0, info->ndcb0);
> + ? ? ? ? ? ? ? nand_writel(info, NDCB0, info->ndcb1);
> + ? ? ? ? ? ? ? nand_writel(info, NDCB0, info->ndcb2);
> ? ? ? ?}
>
> - ? ? ? if (info->use_dma == 0 && info->data_size > 0)
> - ? ? ? ? ? ? ? if (handle_data_pio(info))
> - ? ? ? ? ? ? ? ? ? ? ? goto fail_stop;
> -
> - ? ? ? return 0;
> -
> -fail_stop:
> - ? ? ? ndcr = nand_readl(info, NDCR);
> - ? ? ? nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
> - ? ? ? udelay(10);
> - ? ? ? return -ETIMEDOUT;
> + ? ? ? /* clear NDSR to let the controller exit the IRQ */
> + ? ? ? nand_writel(info, NDSR, status);
> + ? ? ? if (is_completed)
> + ? ? ? ? ? ? ? complete(&info->cmd_complete);
> +NORMAL_IRQ_EXIT:
> + ? ? ? return IRQ_HANDLED;
> ?}
>
> ?static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
> @@ -627,14 +565,12 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
> *mtd, unsigned command,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?int column, int page_addr)
> ?{
> ? ? ? ?struct pxa3xx_nand_info *info = mtd->priv;
> - ? ? ? int ret;
> + ? ? ? int ret, exec_cmd = 0;
>
> ? ? ? ?info->use_dma = (use_dma) ? 1 : 0;
> ? ? ? ?info->use_ecc = 0;
> ? ? ? ?info->data_size = 0;
> - ? ? ? info->state = STATE_READY;
> -
> - ? ? ? init_completion(&info->cmd_complete);
> + ? ? ? info->state = 0;
>
> ? ? ? ?switch (command) {
> ? ? ? ?case NAND_CMD_READOOB:
> @@ -643,14 +579,13 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
> *mtd, unsigned command,
> ? ? ? ? ? ? ? ?info->buf_start = mtd->writesize + column;
> ? ? ? ? ? ? ? ?memset(info->data_buff, 0xFF, info->buf_count);
>
> - ? ? ? ? ? ? ? if (prepare_read_prog_cmd(info, cmdset.read1, column, page_addr))
> - ? ? ? ? ? ? ? ? ? ? ? break;
> -
> - ? ? ? ? ? ? ? pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
> + ? ? ? ? ? ? ? prepare_read_prog_cmd(info, cmdset.read1, column, page_addr);
>
> ? ? ? ? ? ? ? ?/* We only are OOB, so if the data has error, does not matter */
> ? ? ? ? ? ? ? ?if (info->retcode == ERR_DBERR)
> ? ? ? ? ? ? ? ? ? ? ? ?info->retcode = ERR_NONE;
> +
> + ? ? ? ? ? ? ? exec_cmd = 1;
> ? ? ? ? ? ? ? ?break;
>
> ? ? ? ?case NAND_CMD_READ0:
> @@ -660,11 +595,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
> *mtd, unsigned command,
> ? ? ? ? ? ? ? ?info->buf_count = mtd->writesize + mtd->oobsize;
> ? ? ? ? ? ? ? ?memset(info->data_buff, 0xFF, info->buf_count);
>
> - ? ? ? ? ? ? ? if (prepare_read_prog_cmd(info, cmdset.read1, column, page_addr))
> - ? ? ? ? ? ? ? ? ? ? ? break;
> -
> - ? ? ? ? ? ? ? pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
> -
> + ? ? ? ? ? ? ? prepare_read_prog_cmd(info, cmdset.read1, column, page_addr);
> ? ? ? ? ? ? ? ?if (info->retcode == ERR_DBERR) {
> ? ? ? ? ? ? ? ? ? ? ? ?/* for blank page (all 0xff), HW will calculate its ECC as
> ? ? ? ? ? ? ? ? ? ? ? ? * 0, which is different from the ECC information within
> @@ -673,6 +604,8 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
> *mtd, unsigned command,
> ? ? ? ? ? ? ? ? ? ? ? ?if (is_buf_blank(info->data_buff, mtd->writesize))
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?info->retcode = ERR_NONE;
> ? ? ? ? ? ? ? ?}
> +
> + ? ? ? ? ? ? ? exec_cmd = 1;
> ? ? ? ? ? ? ? ?break;
> ? ? ? ?case NAND_CMD_SEQIN:
> ? ? ? ? ? ? ? ?info->buf_start = column;
> @@ -686,18 +619,14 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
> *mtd, unsigned command,
> ? ? ? ?case NAND_CMD_PAGEPROG:
> ? ? ? ? ? ? ? ?info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
>
> - ? ? ? ? ? ? ? if (prepare_read_prog_cmd(info, cmdset.program,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? info->seqin_column, info->seqin_page_addr))
> - ? ? ? ? ? ? ? ? ? ? ? break;
> -
> - ? ? ? ? ? ? ? pxa3xx_nand_do_cmd(info, NDSR_WRDREQ);
> + ? ? ? ? ? ? ? prepare_read_prog_cmd(info, cmdset.program,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? info->seqin_column, info->seqin_page_addr);
> + ? ? ? ? ? ? ? info->state |= STATE_IS_WRITE;
> + ? ? ? ? ? ? ? exec_cmd = 1;
> ? ? ? ? ? ? ? ?break;
> ? ? ? ?case NAND_CMD_ERASE1:
> - ? ? ? ? ? ? ? if (prepare_erase_cmd(info, cmdset.erase, page_addr))
> - ? ? ? ? ? ? ? ? ? ? ? break;
> -
> - ? ? ? ? ? ? ? pxa3xx_nand_do_cmd(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
> - ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? prepare_erase_cmd(info, cmdset.erase, page_addr);
> + ? ? ? ? ? ? ? exec_cmd = 1;
> ? ? ? ?case NAND_CMD_ERASE2:
> ? ? ? ? ? ? ? ?break;
> ? ? ? ?case NAND_CMD_READID:
> @@ -707,39 +636,37 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
> *mtd, unsigned command,
> ? ? ? ? ? ? ? ?info->buf_count = (command == NAND_CMD_READID) ?
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?info->read_id_bytes : 1;
>
> - ? ? ? ? ? ? ? if (prepare_other_cmd(info, (command == NAND_CMD_READID) ?
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cmdset.read_id : cmdset.read_status))
> - ? ? ? ? ? ? ? ? ? ? ? break;
> -
> - ? ? ? ? ? ? ? pxa3xx_nand_do_cmd(info, NDSR_RDDREQ);
> + ? ? ? ? ? ? ? prepare_other_cmd(info, (command == NAND_CMD_READID) ?
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cmdset.read_id : cmdset.read_status);
> + ? ? ? ? ? ? ? exec_cmd = 1;
> ? ? ? ? ? ? ? ?break;
> ? ? ? ?case NAND_CMD_RESET:
> - ? ? ? ? ? ? ? if (prepare_other_cmd(info, cmdset.reset))
> - ? ? ? ? ? ? ? ? ? ? ? break;
> -
> - ? ? ? ? ? ? ? ret = pxa3xx_nand_do_cmd(info, NDSR_CS0_CMDD);
> - ? ? ? ? ? ? ? if (ret == 0) {
> - ? ? ? ? ? ? ? ? ? ? ? int timeout = 2;
> - ? ? ? ? ? ? ? ? ? ? ? uint32_t ndcr;
> -
> - ? ? ? ? ? ? ? ? ? ? ? while (timeout--) {
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? if (nand_readl(info, NDSR) & NDSR_RDY)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? break;
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? msleep(10);
> - ? ? ? ? ? ? ? ? ? ? ? }
> -
> - ? ? ? ? ? ? ? ? ? ? ? ndcr = nand_readl(info, NDCR);
> - ? ? ? ? ? ? ? ? ? ? ? nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
> - ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? prepare_other_cmd(info, cmdset.reset);
> + ? ? ? ? ? ? ? exec_cmd = 1;
> ? ? ? ? ? ? ? ?break;
> ? ? ? ?default:
> ? ? ? ? ? ? ? ?printk(KERN_ERR "non-supported command.\n");
> ? ? ? ? ? ? ? ?break;
> ? ? ? ?}
>
> - ? ? ? if (info->retcode == ERR_DBERR) {
> - ? ? ? ? ? ? ? printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
> - ? ? ? ? ? ? ? info->retcode = ERR_NONE;
> + ? ? ? if (exec_cmd) {
> + ? ? ? ? ? ? ? init_completion(&info->cmd_complete);
> + ? ? ? ? ? ? ? info->state |= STATE_CMD_PREPARED;
> + ? ? ? ? ? ? ? pxa3xx_nand_start(info);
> +
> + ? ? ? ? ? ? ? ret = wait_for_completion_timeout(&info->cmd_complete,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? CHIP_DELAY_TIMEOUT);
> + ? ? ? ? ? ? ? if (!ret) {
> + ? ? ? ? ? ? ? ? ? ? ? printk(KERN_ERR "Wait time out!!!\n");
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? /* Stop State Machine for next command cycle */
> + ? ? ? ? ? ? ? pxa3xx_nand_stop(info);
> + ? ? ? ? ? ? ? disable_int(info, NDCR_INT_MASK);
> + ? ? ? ? ? ? ? info->state &= ~STATE_CMD_PREPARED;
> + ? ? ? ? ? ? ? if (info->retcode == ERR_DBERR) {
> + ? ? ? ? ? ? ? ? ? ? ? printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
> + ? ? ? ? ? ? ? ? ? ? ? info->retcode = ERR_NONE;
> + ? ? ? ? ? ? ? }
> ? ? ? ?}
> ?}
>
> @@ -848,41 +775,12 @@ static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
> ? ? ? ?return 0;
> ?}
>
> -static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
> -{
> - ? ? ? uint32_t ndcr;
> - ? ? ? uint8_t ?id_buff[8];
> -
> - ? ? ? if (prepare_other_cmd(info, cmdset.read_id)) {
> - ? ? ? ? ? ? ? printk(KERN_ERR "failed to prepare command\n");
> - ? ? ? ? ? ? ? return -EINVAL;
> - ? ? ? }
> -
> - ? ? ? /* Send command */
> - ? ? ? if (write_cmd(info))
> - ? ? ? ? ? ? ? goto fail_timeout;
> -
> - ? ? ? /* Wait for CMDDM(command done successfully) */
> - ? ? ? if (wait_for_event(info, NDSR_RDDREQ))
> - ? ? ? ? ? ? ? goto fail_timeout;
> -
> - ? ? ? __raw_readsl(info->mmio_base + NDDB, id_buff, 2);
> - ? ? ? *id = id_buff[0] | (id_buff[1] << 8);
> - ? ? ? return 0;
> -
> -fail_timeout:
> - ? ? ? ndcr = nand_readl(info, NDCR);
> - ? ? ? nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
> - ? ? ? udelay(10);
> - ? ? ? return -ETIMEDOUT;
> -}
> -
> ?static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const struct pxa3xx_nand_flash *f)
> ?{
> ? ? ? ?struct platform_device *pdev = info->pdev;
> ? ? ? ?struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
> - ? ? ? uint32_t ndcr = 0x00000FFF; /* disable all interrupts */
> + ? ? ? uint32_t ndcr = 0;
>
> ? ? ? ?/* calculate flash information */
> ? ? ? ?info->page_size = f->page_size;
> @@ -949,8 +847,9 @@ static int pxa3xx_nand_detect_config(struct
> pxa3xx_nand_info *info)
> ? ? ? ?info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
> ? ? ? ?info->reg_ndcr = ndcr;
>
> - ? ? ? if (__readid(info, &id))
> - ? ? ? ? ? ? ? return -ENODEV;
> +
> + ? ? ? pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
> + ? ? ? id = *((uint16_t *)(info->data_buff));
>
> ? ? ? ?/* Lookup the flash id */
> ? ? ? ?id = (id >> 8) & 0xff; ? ? ? ? ?/* device id is byte 2 */
> @@ -997,8 +896,8 @@ static int pxa3xx_nand_detect_flash(struct
> pxa3xx_nand_info *info,
>
> ? ? ? ?f = &builtin_flash_types[0];
> ? ? ? ?pxa3xx_nand_config_flash(info, f);
> - ? ? ? if (__readid(info, &id))
> - ? ? ? ? ? ? ? goto fail_detect;
> + ? ? ? pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
> + ? ? ? id = *((uint16_t *)(info->data_buff));
>
> ? ? ? ?for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
> ? ? ? ? ? ? ? ?if (i < pdata->num_flash)
> @@ -1015,7 +914,6 @@ static int pxa3xx_nand_detect_flash(struct
> pxa3xx_nand_info *info,
> ? ? ? ?dev_warn(&info->pdev->dev,
> ? ? ? ? ? ? ? ? ? ? ? ?"failed to detect configured nand flash; found %04x instead of\n",
> ? ? ? ? ? ? ? ? id);
> -fail_detect:
> ? ? ? ?return -ENODEV;
> ?}
>
> @@ -1303,7 +1201,7 @@ static int pxa3xx_nand_suspend(struct
> platform_device *pdev, pm_message_t state)
> ? ? ? ?struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
> ? ? ? ?struct mtd_info *mtd = info->mtd;
>
> - ? ? ? if (info->state != STATE_READY) {
> + ? ? ? if (info->state & STATE_CMD_PREPARED) {
> ? ? ? ? ? ? ? ?dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
> ? ? ? ? ? ? ? ?return -EAGAIN;
> ? ? ? ?}
> --
> 1.7.0.4
>

From eric.y.miao at gmail.com  Fri Jun 18 02:52:34 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 14:52:34 +0800
Subject: [PATCH 06/25] pxa3xx_nand: unify prepare command
In-Reply-To: <AANLkTilhattkx7AiyG-R4zbWSZ3-qkPIM6VhyFW4lk4D@mail.gmail.com>
References: <AANLkTilhattkx7AiyG-R4zbWSZ3-qkPIM6VhyFW4lk4D@mail.gmail.com>
Message-ID: <AANLkTinNqtnL3LRFsPuUQXcTnRda0_B059bRLGlJuzlh@mail.gmail.com>

On Fri, Jun 18, 2010 at 1:34 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> From ac05ddc3c13d2b80b243e91cba9922572841f34a Mon Sep 17 00:00:00 2001
> From: Lei Wen <leiwen at marvell.com>
> Date: Mon, 22 Mar 2010 12:04:22 +0800
> Subject: [PATCH 06/25] pxa3xx_nand: unify prepare command
>
> Make the interface simpler which could make both debug
> and enhancement easier.

What is the benefit of combining them into one big several pages lengthy
function? I dislike lengthy function :-/

>
> Signed-off-by: Lei Wen <leiwen at marvell.com>
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
> ---
> ?drivers/mtd/nand/pxa3xx_nand.c | ?256 +++++++++++++++++++++-------------------
> ?1 files changed, 136 insertions(+), 120 deletions(-)
>
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index 753346f..9ab292b 100644
> --- a/drivers/mtd/nand/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/pxa3xx_nand.c
> @@ -28,6 +28,7 @@
>
> ?#define ? ? ? ?CHIP_DELAY_TIMEOUT ? ? ?(2 * HZ/10)
> ?#define NAND_STOP_DELAY ? ? ? ? ? ? ? ?(2 * HZ/50)
> +#define PAGE_CHUNK_SIZE ? ? ? ? ? ? ? ?(2048)
>
> ?/* registers and bit definitions */
> ?#define NDCR ? ? ? ? ? (0x00) /* Control register */
> @@ -78,6 +79,7 @@
> ?#define NDSR_RDDREQ ? ? ? ? ? ?(0x1 << 1)
> ?#define NDSR_WRCMDREQ ? ? ? ? ?(0x1)
>
> +#define NDCB0_ST_ROW_EN ? ? ? ? (0x1 << 26)
> ?#define NDCB0_AUTO_RS ? ? ? ? ?(0x1 << 25)
> ?#define NDCB0_CSEL ? ? ? ? ? ? (0x1 << 24)
> ?#define NDCB0_CMD_TYPE_MASK ? ?(0x7 << 21)
> @@ -340,7 +342,7 @@ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
> ? ? ? ?uint32_t ndcr;
>
> ? ? ? ?ndcr = info->reg_ndcr;
> - ? ? ? ndcr |= NDCR_ECC_EN;
> + ? ? ? ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
> ? ? ? ?ndcr |= info->use_dma ? NDCR_DMA_EN : NDCR_STOP_ON_UNCOR;
> ? ? ? ?ndcr |= NDCR_ND_RUN;
>
> @@ -369,61 +371,6 @@ static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
> ? ? ? ?}
> ?}
>
> -static void prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
> - ? ? ? ? ? ? ? uint16_t cmd, int column, int page_addr)
> -{
> - ? ? ? pxa3xx_set_datasize(info);
> -
> - ? ? ? /* generate values for NDCBx registers */
> - ? ? ? info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
> - ? ? ? info->ndcb1 = 0;
> - ? ? ? info->ndcb2 = 0;
> - ? ? ? info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
> -
> - ? ? ? if (info->col_addr_cycles == 2) {
> - ? ? ? ? ? ? ? /* large block, 2 cycles for column address
> - ? ? ? ? ? ? ? ?* row address starts from 3rd cycle
> - ? ? ? ? ? ? ? ?*/
> - ? ? ? ? ? ? ? info->ndcb1 |= page_addr << 16;
> - ? ? ? ? ? ? ? if (info->row_addr_cycles == 3)
> - ? ? ? ? ? ? ? ? ? ? ? info->ndcb2 = (page_addr >> 16) & 0xff;
> - ? ? ? } else
> - ? ? ? ? ? ? ? /* small block, 1 cycles for column address
> - ? ? ? ? ? ? ? ?* row address starts from 2nd cycle
> - ? ? ? ? ? ? ? ?*/
> - ? ? ? ? ? ? ? info->ndcb1 = page_addr << 8;
> -
> - ? ? ? if (cmd == cmdset.program)
> - ? ? ? ? ? ? ? info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
> -}
> -
> -static void prepare_erase_cmd(struct pxa3xx_nand_info *info,
> - ? ? ? ? ? ? ? ? ? ? ? uint16_t cmd, int page_addr)
> -{
> - ? ? ? info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
> - ? ? ? info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
> - ? ? ? info->ndcb1 = page_addr;
> - ? ? ? info->ndcb2 = 0;
> -}
> -
> -static void prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
> -{
> - ? ? ? info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
> - ? ? ? info->ndcb1 = 0;
> - ? ? ? info->ndcb2 = 0;
> -
> - ? ? ? if (cmd == cmdset.read_id) {
> - ? ? ? ? ? ? ? info->ndcb0 |= NDCB0_CMD_TYPE(3);
> - ? ? ? ? ? ? ? info->data_size = 8;
> - ? ? ? } else if (cmd == cmdset.read_status) {
> - ? ? ? ? ? ? ? info->ndcb0 |= NDCB0_CMD_TYPE(4);
> - ? ? ? ? ? ? ? info->data_size = 8;
> - ? ? ? } else if (cmd == cmdset.reset || cmd == cmdset.lock ||
> - ? ? ? ? ? ? ? ? ?cmd == cmdset.unlock) {
> - ? ? ? ? ? ? ? info->ndcb0 |= NDCB0_CMD_TYPE(5);
> - ? ? ? }
> -}
> -
> ?static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
> ?{
> ? ? ? ?uint32_t ndcr;
> @@ -561,94 +508,167 @@ static inline int is_buf_blank(uint8_t *buf, size_t len)
> ? ? ? ?return 1;
> ?}
>
> -static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int column, int page_addr)
> +static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
> + ? ? ? ? ? ? ? uint16_t column, int page_addr)
> ?{
> - ? ? ? struct pxa3xx_nand_info *info = mtd->priv;
> - ? ? ? int ret, exec_cmd = 0;
> + ? ? ? uint16_t cmd;
> + ? ? ? int addr_cycle, exec_cmd, ndcb0;
> + ? ? ? struct mtd_info *mtd = info->mtd;
>
> - ? ? ? info->use_dma = (use_dma) ? 1 : 0;
> - ? ? ? info->use_ecc = 0;
> - ? ? ? info->data_size = 0;
> - ? ? ? info->state = 0;
> + ? ? ? ndcb0 = 0;
> + ? ? ? addr_cycle = 0;
> + ? ? ? exec_cmd = 1;
> +
> + ? ? ? /* reset data and oob column point to handle data */
> + ? ? ? info->buf_start ? ? ? ? = 0;
> + ? ? ? info->buf_count ? ? ? ? = 0;
> + ? ? ? info->oob_size ? ? ? ? ?= 0;
> + ? ? ? info->use_ecc ? ? ? ? ? = 0;
>
> ? ? ? ?switch (command) {
> + ? ? ? case NAND_CMD_READ0:
> + ? ? ? case NAND_CMD_PAGEPROG:
> + ? ? ? ? ? ? ? info->use_ecc = 1;
> ? ? ? ?case NAND_CMD_READOOB:
> - ? ? ? ? ? ? ? /* disable HW ECC to get all the OOB data */
> - ? ? ? ? ? ? ? info->buf_count = mtd->writesize + mtd->oobsize;
> - ? ? ? ? ? ? ? info->buf_start = mtd->writesize + column;
> - ? ? ? ? ? ? ? memset(info->data_buff, 0xFF, info->buf_count);
> + ? ? ? ? ? ? ? pxa3xx_set_datasize(info);
> + ? ? ? ? ? ? ? break;
> + ? ? ? case NAND_CMD_SEQIN:
> + ? ? ? ? ? ? ? exec_cmd = 0;
> + ? ? ? ? ? ? ? break;
> + ? ? ? default:
> + ? ? ? ? ? ? ? info->ndcb1 = 0;
> + ? ? ? ? ? ? ? info->ndcb2 = 0;
> + ? ? ? ? ? ? ? break;
> + ? ? ? }
>
> - ? ? ? ? ? ? ? prepare_read_prog_cmd(info, cmdset.read1, column, page_addr);
> + ? ? ? info->ndcb0 = ndcb0;
> + ? ? ? addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
> + ? ? ? ? ? ? ? ? ? ? ? + info->col_addr_cycles);
>
> - ? ? ? ? ? ? ? /* We only are OOB, so if the data has error, does not matter */
> - ? ? ? ? ? ? ? if (info->retcode == ERR_DBERR)
> - ? ? ? ? ? ? ? ? ? ? ? info->retcode = ERR_NONE;
> + ? ? ? switch (command) {
> + ? ? ? case NAND_CMD_READOOB:
> + ? ? ? case NAND_CMD_READ0:
>
> - ? ? ? ? ? ? ? exec_cmd = 1;
> - ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? cmd ?= cmdset.read1;
> + ? ? ? ? ? ? ? if (command == NAND_CMD_READOOB)
> + ? ? ? ? ? ? ? ? ? ? ? info->buf_start = mtd->writesize + column;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? info->buf_start = column;
>
> - ? ? ? case NAND_CMD_READ0:
> - ? ? ? ? ? ? ? info->use_ecc = 1;
> - ? ? ? ? ? ? ? info->retcode = ERR_NONE;
> - ? ? ? ? ? ? ? info->buf_start = column;
> - ? ? ? ? ? ? ? info->buf_count = mtd->writesize + mtd->oobsize;
> - ? ? ? ? ? ? ? memset(info->data_buff, 0xFF, info->buf_count);
> + ? ? ? ? ? ? ? if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
> + ? ? ? ? ? ? ? ? ? ? ? info->ndcb0 |= NDCB0_CMD_TYPE(0)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | addr_cycle
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | (cmd & NDCB0_CMD1_MASK);
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? info->ndcb0 |= NDCB0_CMD_TYPE(0)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | NDCB0_DBC
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | addr_cycle
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | cmd;
>
> - ? ? ? ? ? ? ? prepare_read_prog_cmd(info, cmdset.read1, column, page_addr);
> - ? ? ? ? ? ? ? if (info->retcode == ERR_DBERR) {
> - ? ? ? ? ? ? ? ? ? ? ? /* for blank page (all 0xff), HW will calculate its ECC as
> - ? ? ? ? ? ? ? ? ? ? ? ?* 0, which is different from the ECC information within
> - ? ? ? ? ? ? ? ? ? ? ? ?* OOB, ignore such double bit errors
> - ? ? ? ? ? ? ? ? ? ? ? ?*/
> - ? ? ? ? ? ? ? ? ? ? ? if (is_buf_blank(info->data_buff, mtd->writesize))
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? info->retcode = ERR_NONE;
> + ? ? ? case NAND_CMD_SEQIN:
> + ? ? ? ? ? ? ? /* small page addr setting */
> + ? ? ? ? ? ? ? if (unlikely(info->page_size < PAGE_CHUNK_SIZE)) {
> + ? ? ? ? ? ? ? ? ? ? ? info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | (column & 0xFF);
> +
> + ? ? ? ? ? ? ? ? ? ? ? info->ndcb2 = 0;
> + ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? else {
> + ? ? ? ? ? ? ? ? ? ? ? info->ndcb1 = ((page_addr & 0xFFFF) << 16)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | (column & 0xFFFF);
> +
> + ? ? ? ? ? ? ? ? ? ? ? if (page_addr & 0xFF0000)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? info->ndcb2 = (page_addr & 0xFF0000) >> 16;
> + ? ? ? ? ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? info->ndcb2 = 0;
> ? ? ? ? ? ? ? ?}
>
> - ? ? ? ? ? ? ? exec_cmd = 1;
> - ? ? ? ? ? ? ? break;
> - ? ? ? case NAND_CMD_SEQIN:
> - ? ? ? ? ? ? ? info->buf_start = column;
> ? ? ? ? ? ? ? ?info->buf_count = mtd->writesize + mtd->oobsize;
> - ? ? ? ? ? ? ? memset(info->data_buff, 0xff, info->buf_count);
> + ? ? ? ? ? ? ? memset(info->data_buff, 0xFF, info->buf_count);
>
> - ? ? ? ? ? ? ? /* save column/page_addr for next CMD_PAGEPROG */
> - ? ? ? ? ? ? ? info->seqin_column = column;
> - ? ? ? ? ? ? ? info->seqin_page_addr = page_addr;
> ? ? ? ? ? ? ? ?break;
> +
> ? ? ? ?case NAND_CMD_PAGEPROG:
> - ? ? ? ? ? ? ? info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
> + ? ? ? ? ? ? ? if (is_buf_blank(info->data_buff, (mtd->writesize + mtd->oobsize))) {
> + ? ? ? ? ? ? ? ? ? ? ? exec_cmd = 0;
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
>
> - ? ? ? ? ? ? ? prepare_read_prog_cmd(info, cmdset.program,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? info->seqin_column, info->seqin_page_addr);
> + ? ? ? ? ? ? ? cmd = cmdset.program;
> ? ? ? ? ? ? ? ?info->state |= STATE_IS_WRITE;
> - ? ? ? ? ? ? ? exec_cmd = 1;
> - ? ? ? ? ? ? ? break;
> - ? ? ? case NAND_CMD_ERASE1:
> - ? ? ? ? ? ? ? prepare_erase_cmd(info, cmdset.erase, page_addr);
> - ? ? ? ? ? ? ? exec_cmd = 1;
> - ? ? ? case NAND_CMD_ERASE2:
> + ? ? ? ? ? ? ? info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | NDCB0_AUTO_RS
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | NDCB0_ST_ROW_EN
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | NDCB0_DBC
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | cmd
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | addr_cycle;
> ? ? ? ? ? ? ? ?break;
> +
> ? ? ? ?case NAND_CMD_READID:
> + ? ? ? ? ? ? ? cmd = cmdset.read_id;
> + ? ? ? ? ? ? ? info->buf_count = info->read_id_bytes;
> + ? ? ? ? ? ? ? info->ndcb0 |= NDCB0_CMD_TYPE(3)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | NDCB0_ADDR_CYC(1)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | cmd;
> +
> + ? ? ? ? ? ? ? info->data_size = 8;
> + ? ? ? ? ? ? ? break;
> +
> ? ? ? ?case NAND_CMD_STATUS:
> - ? ? ? ? ? ? ? info->use_dma = 0; ? ? ?/* force PIO read */
> - ? ? ? ? ? ? ? info->buf_start = 0;
> - ? ? ? ? ? ? ? info->buf_count = (command == NAND_CMD_READID) ?
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? info->read_id_bytes : 1;
> -
> - ? ? ? ? ? ? ? prepare_other_cmd(info, (command == NAND_CMD_READID) ?
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? cmdset.read_id : cmdset.read_status);
> - ? ? ? ? ? ? ? exec_cmd = 1;
> + ? ? ? ? ? ? ? cmd = cmdset.read_status;
> + ? ? ? ? ? ? ? info->buf_count = 1;
> + ? ? ? ? ? ? ? info->ndcb0 |= NDCB0_CMD_TYPE(4)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | NDCB0_ADDR_CYC(1)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | cmd;
> +
> + ? ? ? ? ? ? ? info->data_size = 8;
> + ? ? ? ? ? ? ? break;
> +
> + ? ? ? case NAND_CMD_ERASE1:
> + ? ? ? ? ? ? ? cmd = cmdset.erase;
> + ? ? ? ? ? ? ? info->ndcb0 |= NDCB0_CMD_TYPE(2)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | NDCB0_AUTO_RS
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | NDCB0_ADDR_CYC(3)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | NDCB0_DBC
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | cmd;
> + ? ? ? ? ? ? ? info->ndcb1 = page_addr;
> + ? ? ? ? ? ? ? info->ndcb2 = 0;
> +
> ? ? ? ? ? ? ? ?break;
> ? ? ? ?case NAND_CMD_RESET:
> - ? ? ? ? ? ? ? prepare_other_cmd(info, cmdset.reset);
> - ? ? ? ? ? ? ? exec_cmd = 1;
> + ? ? ? ? ? ? ? cmd = cmdset.reset;
> + ? ? ? ? ? ? ? info->ndcb0 |= NDCB0_CMD_TYPE(5)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | cmd;
> +
> ? ? ? ? ? ? ? ?break;
> +
> + ? ? ? case NAND_CMD_ERASE2:
> + ? ? ? ? ? ? ? exec_cmd = 0;
> + ? ? ? ? ? ? ? break;
> +
> ? ? ? ?default:
> - ? ? ? ? ? ? ? printk(KERN_ERR "non-supported command.\n");
> + ? ? ? ? ? ? ? exec_cmd = 0;
> + ? ? ? ? ? ? ? printk(KERN_ERR "pxa3xx-nand: non-supported command %x\n", command);
> ? ? ? ? ? ? ? ?break;
> ? ? ? ?}
>
> + ? ? ? return exec_cmd;
> +}
> +
> +static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int column, int page_addr)
> +{
> + ? ? ? struct pxa3xx_nand_info *info = mtd->priv;
> + ? ? ? int ret, exec_cmd;
> +
> + ? ? ? /* if this is a x16 device ,then convert the input
> + ? ? ? ?* "byte" address into a "word" address appropriate
> + ? ? ? ?* for indexing a word-oriented device
> + ? ? ? ?*/
> + ? ? ? if (info->reg_ndcr & NDCR_DWIDTH_M)
> + ? ? ? ? ? ? ? column /= 2;
> +
> + ? ? ? exec_cmd = prepare_command_pool(info, command, column, page_addr);
> ? ? ? ?if (exec_cmd) {
> ? ? ? ? ? ? ? ?init_completion(&info->cmd_complete);
> ? ? ? ? ? ? ? ?info->state |= STATE_CMD_PREPARED;
> @@ -663,10 +683,6 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
> *mtd, unsigned command,
> ? ? ? ? ? ? ? ?pxa3xx_nand_stop(info);
> ? ? ? ? ? ? ? ?disable_int(info, NDCR_INT_MASK);
> ? ? ? ? ? ? ? ?info->state &= ~STATE_CMD_PREPARED;
> - ? ? ? ? ? ? ? if (info->retcode == ERR_DBERR) {
> - ? ? ? ? ? ? ? ? ? ? ? printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
> - ? ? ? ? ? ? ? ? ? ? ? info->retcode = ERR_NONE;
> - ? ? ? ? ? ? ? }
> ? ? ? ?}
> ?}
>
> --
> 1.7.0.4
>

From eric.y.miao at gmail.com  Fri Jun 18 02:58:47 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 14:58:47 +0800
Subject: [PATCH 07/25] pxa3xx_nand: mtd scan id process could be defined 
	by driver itself
In-Reply-To: <AANLkTilY1gnS_jwZ_xPKhchTLR5cWj7FEla1V76OuMVK@mail.gmail.com>
References: <AANLkTilY1gnS_jwZ_xPKhchTLR5cWj7FEla1V76OuMVK@mail.gmail.com>
Message-ID: <AANLkTimnaBO_Zb0UvPZYzmQNmqJafTv1gWV8KQm_LwC3@mail.gmail.com>

On Fri, Jun 18, 2010 at 1:34 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> From d2958ecbec5d0b7f7aee311fd3e87ed1a858864d Mon Sep 17 00:00:00 2001
> From: Lei Wen <leiwen at marvell.com>
> Date: Wed, 2 Jun 2010 21:55:51 +0800
> Subject: [PATCH 07/25] pxa3xx_nand: mtd scan id process could be
> defined by driver itself
>
> Different NAND driver may require its unique detection. For pxa3xx_nand,
> it use its self id database to get the necessary info.

I believe I get the central point of this patch: to have a specific
pxa3xx_nand_scan()
instead of using the generic nand_scan(). This point is good, yet I
found it extremely
difficult to read the patch. Like those chip->xxxx assignment, is that
also part of this
patch, I strongly recommend to remove irrelevant changes into separate patches.

>
> Signed-off-by: Lei Wen <leiwen at marvell.com>
> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
> ---
> ?drivers/mtd/nand/pxa3xx_nand.c | ?255 ++++++++++++++++++++++++++--------------
> ?1 files changed, 165 insertions(+), 90 deletions(-)
>
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index 9ab292b..481cb25 100644
> --- a/drivers/mtd/nand/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/pxa3xx_nand.c
> @@ -158,6 +158,7 @@ struct pxa3xx_nand_flash {
> ?struct pxa3xx_nand_info {
> ? ? ? ?struct nand_chip ? ? ? ?nand_chip;
>
> + ? ? ? struct nand_hw_control ?controller;
> ? ? ? ?struct platform_device ? *pdev;
>
> ? ? ? ?struct clk ? ? ? ? ? ? ?*clk;
> @@ -261,6 +262,8 @@ static struct pxa3xx_nand_flash __devinitdata
> builtin_flash_types[] = {
> ? ? ? ?{ 0xba20, ?64, 2048, 16, 16, 2048, &timing[3], },
> ?};
>
> +static const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
> +
> ?#define NDTR0_tCH(c) ? (min((c), 7) << 19)
> ?#define NDTR0_tCS(c) ? (min((c), 7) << 16)
> ?#define NDTR0_tWH(c) ? (min((c), 7) << 11)
> @@ -899,40 +902,6 @@ static int pxa3xx_nand_detect_config(struct
> pxa3xx_nand_info *info)
> ? ? ? ?return 0;
> ?}
>
> -static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const struct pxa3xx_nand_platform_data *pdata)
> -{
> - ? ? ? const struct pxa3xx_nand_flash *f;
> - ? ? ? uint32_t id = -1;
> - ? ? ? int i;
> -
> - ? ? ? if (pdata->keep_config)
> - ? ? ? ? ? ? ? if (pxa3xx_nand_detect_config(info) == 0)
> - ? ? ? ? ? ? ? ? ? ? ? return 0;
> -
> - ? ? ? f = &builtin_flash_types[0];
> - ? ? ? pxa3xx_nand_config_flash(info, f);
> - ? ? ? pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
> - ? ? ? id = *((uint16_t *)(info->data_buff));
> -
> - ? ? ? for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
> - ? ? ? ? ? ? ? if (i < pdata->num_flash)
> - ? ? ? ? ? ? ? ? ? ? ? f = pdata->flash + i;
> - ? ? ? ? ? ? ? else
> - ? ? ? ? ? ? ? ? ? ? ? f = &builtin_flash_types[i - pdata->num_flash + 1];
> - ? ? ? ? ? ? ? if (f->chip_id == id) {
> - ? ? ? ? ? ? ? ? ? ? ? dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
> - ? ? ? ? ? ? ? ? ? ? ? pxa3xx_nand_config_flash(info, f);
> - ? ? ? ? ? ? ? ? ? ? ? return 0;
> - ? ? ? ? ? ? ? }
> - ? ? ? }
> -
> - ? ? ? dev_warn(&info->pdev->dev,
> - ? ? ? ? ? ? ? ? ? ? ? "failed to detect configured nand flash; found %04x instead of\n",
> - ? ? ? ? ? ? ? ?id);
> - ? ? ? return -ENODEV;
> -}
> -
> ?/* the maximum possible buffer size for large page with OOB data
> ?* is: 2048 + 64 = 2112 bytes, allocate a page here for both the
> ?* data buffer and the DMA descriptor
> @@ -974,56 +943,153 @@ static int pxa3xx_nand_init_buff(struct
> pxa3xx_nand_info *info)
> ? ? ? ?return 0;
> ?}
>
> -static struct nand_ecclayout hw_smallpage_ecclayout = {
> - ? ? ? .eccbytes = 6,
> - ? ? ? .eccpos = {8, 9, 10, 11, 12, 13 },
> - ? ? ? .oobfree = { {2, 6} }
> -};
> +static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
> + ? ? ? ? ? ? ? struct nand_chip *chip, uint8_t *buf, int page)
> +{
> + ? ? ? struct pxa3xx_nand_info *info = mtd->priv;
>
> -static struct nand_ecclayout hw_largepage_ecclayout = {
> - ? ? ? .eccbytes = 24,
> - ? ? ? .eccpos = {
> - ? ? ? ? ? ? ? 40, 41, 42, 43, 44, 45, 46, 47,
> - ? ? ? ? ? ? ? 48, 49, 50, 51, 52, 53, 54, 55,
> - ? ? ? ? ? ? ? 56, 57, 58, 59, 60, 61, 62, 63},
> - ? ? ? .oobfree = { {2, 38} }
> -};
> + ? ? ? chip->read_buf(mtd, buf, mtd->writesize);
> + ? ? ? chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
> +
> + ? ? ? if (info->retcode == ERR_SBERR) {
> + ? ? ? ? ? ? ? switch (info->use_ecc) {
> + ? ? ? ? ? ? ? ? ? ? ? case 1:
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? mtd->ecc_stats.corrected ++;
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? break;
> +
> + ? ? ? ? ? ? ? ? ? ? ? case 0:
> + ? ? ? ? ? ? ? ? ? ? ? default:
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> + ? ? ? else if (info->retcode == ERR_DBERR) {
> + ? ? ? ? ? ? ? int buf_blank;
> +
> + ? ? ? ? ? ? ? buf_blank = is_buf_blank(buf, mtd->writesize);
> + ? ? ? ? ? ? ? if (!buf_blank)
> + ? ? ? ? ? ? ? ? ? ? ? mtd->ecc_stats.failed++;
> + ? ? ? }
> +
> + ? ? ? return 0;
> +}
> +
> +static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
> + ? ? ? ? ? ? ? struct nand_chip *chip, const uint8_t *buf)
> +{
> + ? ? ? chip->write_buf(mtd, buf, mtd->writesize);
> + ? ? ? chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
> +}
> +
> +static void pxa3xx_nand_erase_cmd(struct mtd_info *mtd, int page)
> +{
> + ? ? ? struct nand_chip *chip = mtd->priv;
> + ? ? ? /* Send commands to erase a block */
> + ? ? ? chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
> +}
>
> -static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct pxa3xx_nand_info *info)
> +static int __devinit pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
> ?{
> - ? ? ? struct nand_chip *this = &info->nand_chip;
> -
> - ? ? ? this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;
> -
> - ? ? ? this->waitfunc ? ? ? ? ?= pxa3xx_nand_waitfunc;
> - ? ? ? this->select_chip ? ? ? = pxa3xx_nand_select_chip;
> - ? ? ? this->dev_ready ? ? ? ? = pxa3xx_nand_dev_ready;
> - ? ? ? this->cmdfunc ? ? ? ? ? = pxa3xx_nand_cmdfunc;
> - ? ? ? this->read_word ? ? ? ? = pxa3xx_nand_read_word;
> - ? ? ? this->read_byte ? ? ? ? = pxa3xx_nand_read_byte;
> - ? ? ? this->read_buf ? ? ? ? ?= pxa3xx_nand_read_buf;
> - ? ? ? this->write_buf ? ? ? ? = pxa3xx_nand_write_buf;
> - ? ? ? this->verify_buf ? ? ? ?= pxa3xx_nand_verify_buf;
> -
> - ? ? ? this->ecc.mode ? ? ? ? ?= NAND_ECC_HW;
> - ? ? ? this->ecc.hwctl ? ? ? ? = pxa3xx_nand_ecc_hwctl;
> - ? ? ? this->ecc.calculate ? ? = pxa3xx_nand_ecc_calculate;
> - ? ? ? this->ecc.correct ? ? ? = pxa3xx_nand_ecc_correct;
> - ? ? ? this->ecc.size ? ? ? ? ?= info->page_size;
> -
> - ? ? ? if (info->page_size == 2048)
> - ? ? ? ? ? ? ? this->ecc.layout = &hw_largepage_ecclayout;
> + ? ? ? struct mtd_info *mtd = info->mtd;
> + ? ? ? struct nand_chip *chip = mtd->priv;
> +
> + ? ? ? /* use the common timing to make a try */
> + ? ? ? pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
> + ? ? ? chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
> + ? ? ? if (info->state & STATE_READY)
> + ? ? ? ? ? ? ? return 1;
> ? ? ? ?else
> - ? ? ? ? ? ? ? this->ecc.layout = &hw_smallpage_ecclayout;
> + ? ? ? ? ? ? ? return 0;
> +}
> +
> +static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd)
> +{
> + ? ? ? struct pxa3xx_nand_info *info = mtd->priv;
> + ? ? ? struct platform_device *pdev = info->pdev;
> + ? ? ? struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
> + ? ? ? const struct pxa3xx_nand_flash *f = NULL;
> + ? ? ? struct nand_chip *chip = mtd->priv;
> + ? ? ? uint32_t id = -1;
> + ? ? ? int i, ret;
> +
> + ? ? ? if (pdata->keep_config)
> + ? ? ? ? ? ? ? if (pxa3xx_nand_detect_config(info) == 0)
> + ? ? ? ? ? ? ? ? ? ? ? return 0;
> +
> + ? ? ? ret = pxa3xx_nand_sensing(info);
> + ? ? ? if (!ret) {
> + ? ? ? ? ? ? ? kfree(mtd);
> + ? ? ? ? ? ? ? info->mtd = NULL;
> + ? ? ? ? ? ? ? printk(KERN_INFO "There is no nand chip on cs 0!\n");
>
> - ? ? ? this->chip_delay = 25;
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> + ? ? ? chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
> + ? ? ? id = *((uint16_t *)(info->data_buff));
> + ? ? ? if (id != 0)
> + ? ? ? ? ? ? ? printk(KERN_INFO "Detect a flash id %x\n", id);
> + ? ? ? else {
> + ? ? ? ? ? ? ? kfree(mtd);
> + ? ? ? ? ? ? ? info->mtd = NULL;
> + ? ? ? ? ? ? ? printk(KERN_WARNING "Read out ID 0, potential timing set wrong!!\n");
> +
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> + ? ? ? for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
> + ? ? ? ? ? ? ? if (i < pdata->num_flash)
> + ? ? ? ? ? ? ? ? ? ? ? f = pdata->flash + i;
> + ? ? ? ? ? ? ? else
> + ? ? ? ? ? ? ? ? ? ? ? f = &builtin_flash_types[i - pdata->num_flash + 1];
> +
> + ? ? ? ? ? ? ? /* find the chip in default list */
> + ? ? ? ? ? ? ? if (f->chip_id == id) {
> + ? ? ? ? ? ? ? ? ? ? ? pxa3xx_nand_config_flash(info, f);
> + ? ? ? ? ? ? ? ? ? ? ? mtd->writesize = f->page_size;
> + ? ? ? ? ? ? ? ? ? ? ? mtd->writesize_shift = ffs(mtd->writesize) - 1;
> + ? ? ? ? ? ? ? ? ? ? ? mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
> + ? ? ? ? ? ? ? ? ? ? ? mtd->oobsize = mtd->writesize / 32;
> + ? ? ? ? ? ? ? ? ? ? ? mtd->erasesize = f->page_size * f->page_per_block;
> + ? ? ? ? ? ? ? ? ? ? ? mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
> + ? ? ? ? ? ? ? ? ? ? ? mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
> +
> + ? ? ? ? ? ? ? ? ? ? ? mtd->name = mtd_names[0];
> + ? ? ? ? ? ? ? ? ? ? ? break;
> + ? ? ? ? ? ? ? }
> + ? ? ? }
> +
> + ? ? ? if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash)) {
> + ? ? ? ? ? ? ? kfree(mtd);
> + ? ? ? ? ? ? ? info->mtd = NULL;
> + ? ? ? ? ? ? ? printk(KERN_ERR "ERROR!! flash not defined!!!\n");
> +
> + ? ? ? ? ? ? ? return -EINVAL;
> + ? ? ? }
> +
> + ? ? ? chip->ecc.mode = NAND_ECC_HW;
> + ? ? ? chip->ecc.size = f->page_size;
> + ? ? ? chip->chipsize ?= (uint64_t)f->num_blocks * f->page_per_block
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? * f->page_size;
> + ? ? ? mtd->size = chip->chipsize;
> +
> + ? ? ? /* Calculate the address shift from the page size */
> + ? ? ? chip->page_shift = ffs(mtd->writesize) - 1;
> + ? ? ? chip->pagemask = mtd_div_by_ws(chip->chipsize, mtd) - 1;
> + ? ? ? chip->numchips = 1;
> + ? ? ? chip->bbt_erase_shift = chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
> +
> + ? ? ? chip->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
> + ? ? ? chip->options |= NAND_NO_AUTOINCR;
> + ? ? ? chip->options |= NAND_NO_READRDY;
> + ? ? ? chip->options |= NAND_USE_FLASH_BBT;
> +
> + ? ? ? return nand_scan_tail(mtd);
> ?}
>
> ?static int alloc_nand_resource(struct platform_device *pdev)
> ?{
> - ? ? ? struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
> ? ? ? ?struct pxa3xx_nand_info *info;
> + ? ? ? struct nand_chip *chip;
> ? ? ? ?struct mtd_info *mtd;
> ? ? ? ?struct resource *r;
> ? ? ? ?int ret, irq;
> @@ -1036,12 +1102,31 @@ static int alloc_nand_resource(struct
> platform_device *pdev)
> ? ? ? ?}
>
> ? ? ? ?info = (struct pxa3xx_nand_info *)(&mtd[1]);
> + ? ? ? chip = (struct nand_chip *)(&mtd[1]);
> ? ? ? ?info->pdev = pdev;
> -
> - ? ? ? mtd->priv = info;
> ? ? ? ?info->mtd = mtd;
> + ? ? ? mtd->priv = info;
> ? ? ? ?mtd->owner = THIS_MODULE;
>
> + ? ? ? chip->ecc.read_page ? ? = pxa3xx_nand_read_page_hwecc;
> + ? ? ? chip->ecc.write_page ? ?= pxa3xx_nand_write_page_hwecc;
> + ? ? ? chip->ecc.hwctl ? ? ? ? = pxa3xx_nand_ecc_hwctl;
> + ? ? ? chip->ecc.calculate ? ? = pxa3xx_nand_ecc_calculate;
> + ? ? ? chip->ecc.correct ? ? ? = pxa3xx_nand_ecc_correct;
> + ? ? ? chip->controller ? ? ? ?= &info->controller;
> + ? ? ? chip->waitfunc ? ? ? ? ?= pxa3xx_nand_waitfunc;
> + ? ? ? chip->select_chip ? ? ? = pxa3xx_nand_select_chip;
> + ? ? ? chip->dev_ready ? ? ? ? = pxa3xx_nand_dev_ready;
> + ? ? ? chip->cmdfunc ? ? ? ? ? = pxa3xx_nand_cmdfunc;
> + ? ? ? chip->read_word ? ? ? ? = pxa3xx_nand_read_word;
> + ? ? ? chip->read_byte ? ? ? ? = pxa3xx_nand_read_byte;
> + ? ? ? chip->read_buf ? ? ? ? ?= pxa3xx_nand_read_buf;
> + ? ? ? chip->write_buf ? ? ? ? = pxa3xx_nand_write_buf;
> + ? ? ? chip->verify_buf ? ? ? ?= pxa3xx_nand_verify_buf;
> + ? ? ? chip->erase_cmd ? ? ? ? = pxa3xx_nand_erase_cmd;
> +
> + ? ? ? spin_lock_init(&chip->controller->lock);
> + ? ? ? init_waitqueue_head(&chip->controller->wq);
> ? ? ? ?info->clk = clk_get(&pdev->dev, NULL);
> ? ? ? ?if (IS_ERR(info->clk)) {
> ? ? ? ? ? ? ? ?dev_err(&pdev->dev, "failed to get nand clock\n");
> @@ -1109,21 +1194,11 @@ static int alloc_nand_resource(struct
> platform_device *pdev)
> ? ? ? ? ? ? ? ?goto fail_free_buf;
> ? ? ? ?}
>
> - ? ? ? ret = pxa3xx_nand_detect_flash(info, pdata);
> - ? ? ? if (ret) {
> - ? ? ? ? ? ? ? dev_err(&pdev->dev, "failed to detect flash\n");
> - ? ? ? ? ? ? ? ret = -ENODEV;
> - ? ? ? ? ? ? ? goto fail_free_irq;
> - ? ? ? }
> -
> - ? ? ? pxa3xx_nand_init_mtd(mtd, info);
> ? ? ? ?platform_set_drvdata(pdev, info);
> -
> ? ? ? ?return 0;
>
> -fail_free_irq:
> - ? ? ? free_irq(irq, info);
> ?fail_free_buf:
> + ? ? ? free_irq(irq, info);
> ? ? ? ?if (use_dma) {
> ? ? ? ? ? ? ? ?pxa_free_dma(info->data_dma_ch);
> ? ? ? ? ? ? ? ?dma_free_coherent(&pdev->dev, info->data_buff_size,
> @@ -1191,7 +1266,7 @@ static int __devinit pxa3xx_nand_probe(struct
> platform_device *pdev)
> ? ? ? ? ? ? ? ?return ret;
>
> ? ? ? ?info = platform_get_drvdata(pdev);
> - ? ? ? if (nand_scan(info->mtd, 1)) {
> + ? ? ? if (pxa3xx_nand_scan(info->mtd)) {
> ? ? ? ? ? ? ? ?dev_err(&pdev->dev, "failed to scan nand\n");
> ? ? ? ? ? ? ? ?pxa3xx_nand_remove(pdev);
> ? ? ? ? ? ? ? ?return -ENODEV;
> @@ -1202,10 +1277,10 @@ static int __devinit pxa3xx_nand_probe(struct
> platform_device *pdev)
> ? ? ? ? ? ? ? ?struct mtd_partition *parts;
> ? ? ? ? ? ? ? ?int nr_parts;
>
> - ? ? ? ? ? ? ? nr_parts = parse_mtd_partitions(mtd, probes, &parts, 0);
> + ? ? ? ? ? ? ? nr_parts = parse_mtd_partitions(info->mtd, probes, &parts, 0);
>
> ? ? ? ? ? ? ? ?if (nr_parts)
> - ? ? ? ? ? ? ? ? ? ? ? return add_mtd_partitions(mtd, parts, nr_parts);
> + ? ? ? ? ? ? ? ? ? ? ? return add_mtd_partitions(info->mtd, parts, nr_parts);
> ? ? ? ?}
>
> ? ? ? ?return add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts);
> --
> 1.7.0.4
>

From eric.y.miao at gmail.com  Fri Jun 18 02:59:46 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 14:59:46 +0800
Subject: [PATCH 08/25] mmp: add nand support to pxa168
In-Reply-To: <AANLkTinxMQjZIG4G1d9WVOiUX8-zHjTuTc1eRuInDRGW@mail.gmail.com>
References: <AANLkTinxMQjZIG4G1d9WVOiUX8-zHjTuTc1eRuInDRGW@mail.gmail.com>
Message-ID: <AANLkTilOIds0GEPmTWgi_y7UzJT4g9qx6iAtDJDgVxWu@mail.gmail.com>

On Fri, Jun 18, 2010 at 1:34 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
> From 55adf11cb4ba8ba0b88148c9bce0cc08f94b97bd Mon Sep 17 00:00:00 2001
> From: Lei Wen <leiwen at marvell.com>
> Date: Mon, 31 May 2010 14:57:49 +0800
> Subject: [PATCH 08/25] mmp: add nand support to pxa168
>
> Signed-off-by: Lei Wen <leiwen at marvell.com>
> ---
> ?arch/arm/configs/pxa168_defconfig | ? ?9 ++++++++-
> ?drivers/mtd/nand/Kconfig ? ? ? ? ?| ? ?2 +-
> ?2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/configs/pxa168_defconfig
> b/arch/arm/configs/pxa168_defconfig
> index 113511f..a01ea99 100644
> --- a/arch/arm/configs/pxa168_defconfig
> +++ b/arch/arm/configs/pxa168_defconfig
> @@ -438,7 +438,14 @@ CONFIG_EXTRA_FIRMWARE=""
> ?# CONFIG_DEBUG_DEVRES is not set
> ?# CONFIG_SYS_HYPERVISOR is not set
> ?# CONFIG_CONNECTOR is not set
> -# CONFIG_MTD is not set
> +CONFIG_MTD=y
> +CONFIG_MTD_PARTITIONS=y
> +CONFIG_MTD_CMDLINE_PARTS=y
> +CONFIG_MTD_CHAR=y
> +CONFIG_MTD_BLKDEVS=y
> +CONFIG_MTD_BLOCK=y
> +CONFIG_MTD_NAND=y
> +CONFIG_MTD_NAND_PXA3xx=y
> ?# CONFIG_PARPORT is not set
> ?# CONFIG_BLK_DEV is not set
> ?# CONFIG_MISC_DEVICES is not set
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 9a35d92..0d29b5d 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -394,7 +394,7 @@ endchoice
>
> ?config MTD_NAND_PXA3xx
> ? ? ? ?tristate "Support for NAND flash devices on PXA3xx"
> - ? ? ? depends on MTD_NAND && (PXA3xx || ARCH_MMP)
> + ? ? ? depends on MTD_NAND && PLAT_PXA

I'd prefer this not being changed, as pxa3xx_nand isn't applicable to
pxa25x/pxa27x.

> ? ? ? ?help
> ? ? ? ? ?This enables the driver for the NAND flash device found on
> ? ? ? ? ?PXA3xx processors
> --
> 1.7.0.4
>


From l.fu at pengutronix.de  Fri Jun 18 03:23:17 2010
From: l.fu at pengutronix.de (Luotao Fu)
Date: Fri, 18 Jun 2010 09:23:17 +0200
Subject: pca100 patches [V2]
In-Reply-To: <1275573348-26564-3-git-send-email-l.fu@pengutronix.de>
References: <1275573348-26564-3-git-send-email-l.fu@pengutronix.de>
Message-ID: <1276845799-6122-1-git-send-email-l.fu@pengutronix.de>

Hi,

this is the V2 of the pach serie for PhyCARD-S(pca100) Board. In the last patch
serie I brought in a regression by using an undefined macro..doh!. V2 fixed this
issue.

cheers
Luotao Fu



From l.fu at pengutronix.de  Fri Jun 18 03:23:19 2010
From: l.fu at pengutronix.de (Luotao Fu)
Date: Fri, 18 Jun 2010 09:23:19 +0200
Subject: [PATCH 2/2 V2] pca100: clean up GPIO pin multiplexing
In-Reply-To: <1275573348-26564-3-git-send-email-l.fu@pengutronix.de>
References: <1275573348-26564-3-git-send-email-l.fu@pengutronix.de>
Message-ID: <1276845799-6122-3-git-send-email-l.fu@pengutronix.de>

cleaned up some duplicated mxc_gpio_mode calls and move the correpsonding
pin multiplexing either into the initial pin config table or ifdef blocks.

Signed-off-by: Luotao Fu <l.fu at pengutronix.de>
---
V2 Changes: removed undefined LVDS_PWR macro.

 arch/arm/mach-mx2/mach-pca100.c |   23 +++++++++++------------
 1 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c
index 47173d1..5357020 100644
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-mx2/mach-pca100.c
@@ -55,6 +55,9 @@
 
 #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
 #define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
+#define SPI1_SS0 (GPIO_PORTD + 28)
+#define SPI1_SS1 (GPIO_PORTD + 27)
+#define SD2_CD (GPIO_PORTC + 29)
 
 static int pca100_pins[] = {
 	/* UART1 */
@@ -69,6 +72,7 @@ static int pca100_pins[] = {
 	PB7_PF_SD2_D3,
 	PB8_PF_SD2_CMD,
 	PB9_PF_SD2_CLK,
+	SD2_CD | GPIO_GPIO | GPIO_IN,
 	/* FEC */
 	PD0_AIN_FEC_TXD0,
 	PD1_AIN_FEC_TXD1,
@@ -156,6 +160,10 @@ static int pca100_pins[] = {
 	PA28_PF_HSYNC,
 	PA29_PF_VSYNC,
 	PA31_PF_OE_ACD,
+	/* free GPIO */
+	GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN, /* GPIO0_IRQ */
+	GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN, /* GPIO1_IRQ */
+	GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN, /* GPIO2_IRQ */
 };
 
 static struct imxuart_platform_data uart_pdata = {
@@ -214,7 +222,7 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = {
 	},
 };
 
-static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
+static int pca100_spi_cs[] = {SPI1_SS0, SPI1_SS1};
 
 static struct spi_imx_master pca100_spi_0_data = {
 	.chipselect	= pca100_spi_cs,
@@ -386,7 +394,6 @@ static void __init pca100_init(void)
 
 	mxc_register_device(&mxc_uart_device0, &uart_pdata);
 
-	mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
 	mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
 
 	mxc_register_device(&imx27_nand_device, &pca100_nand_board_info);
@@ -397,17 +404,9 @@ static void __init pca100_init(void)
 
 	mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
 
-	mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
-	mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
-
-	/* GPIO0_IRQ */
-	mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
-	/* GPIO1_IRQ */
-	mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
-	/* GPIO2_IRQ */
-	mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
-
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+	mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
+	mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
 	spi_register_board_info(pca100_spi_board_info,
 				ARRAY_SIZE(pca100_spi_board_info));
 	mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
-- 
1.7.1



From l.fu at pengutronix.de  Fri Jun 18 03:23:18 2010
From: l.fu at pengutronix.de (Luotao Fu)
Date: Fri, 18 Jun 2010 09:23:18 +0200
Subject: [PATCH 1/2 V2] pca100: add framebuffer device support and TFT
In-Reply-To: <1275573348-26564-3-git-send-email-l.fu@pengutronix.de>
References: <1275573348-26564-3-git-send-email-l.fu@pengutronix.de>
Message-ID: <1276845799-6122-2-git-send-email-l.fu@pengutronix.de>

this one adds the frambuffer device and a TFT panel to the PhyCard-S
(pca100) board.

Signed-off-by: Luotao Fu <l.fu at pengutronix.de>

---
V2 Changes: removed undefined LVDS_PWR macro.

 arch/arm/mach-mx2/mach-pca100.c |   66 +++++++++++++++++++++++++++++++++++++++
 1 files changed, 66 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-mx2/mach-pca100.c
index a87422e..47173d1 100644
--- a/arch/arm/mach-mx2/mach-pca100.c
+++ b/arch/arm/mach-mx2/mach-pca100.c
@@ -49,6 +49,7 @@
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
+#include <mach/imxfb.h>
 
 #include "devices.h"
 
@@ -131,6 +132,30 @@ static int pca100_pins[] = {
 	PD23_AF_USBH2_DATA2,
 	PD24_AF_USBH2_DATA1,
 	PD26_AF_USBH2_DATA5,
+	/* display */
+	PA5_PF_LSCLK,
+	PA6_PF_LD0,
+	PA7_PF_LD1,
+	PA8_PF_LD2,
+	PA9_PF_LD3,
+	PA10_PF_LD4,
+	PA11_PF_LD5,
+	PA12_PF_LD6,
+	PA13_PF_LD7,
+	PA14_PF_LD8,
+	PA15_PF_LD9,
+	PA16_PF_LD10,
+	PA17_PF_LD11,
+	PA18_PF_LD12,
+	PA19_PF_LD13,
+	PA20_PF_LD14,
+	PA21_PF_LD15,
+	PA22_PF_LD16,
+	PA23_PF_LD17,
+	PA26_PF_PS,
+	PA28_PF_HSYNC,
+	PA29_PF_VSYNC,
+	PA31_PF_OE_ACD,
 };
 
 static struct imxuart_platform_data uart_pdata = {
@@ -297,6 +322,45 @@ static int __init pca100_otg_mode(char *options)
 }
 __setup("otg_mode=", pca100_otg_mode);
 
+/* framebuffer info */
+static struct imx_fb_videomode pca100_fb_modes[] = {
+	{
+		.mode = {
+			.name		= "EMERGING-ETV570G0DHU",
+			.refresh	= 60,
+			.xres		= 640,
+			.yres		= 480,
+			.pixclock	= 39722, /* in ps (25.175 MHz) */
+			.hsync_len	= 30,
+			.left_margin	= 114,
+			.right_margin	= 16,
+			.vsync_len	= 3,
+			.upper_margin	= 32,
+			.lower_margin	= 0,
+		},
+		/*
+		 * TFT
+		 * Pixel pol active high
+		 * HSYNC active low
+		 * VSYNC active low
+		 * use HSYNC for ACD count
+		 * line clock disable while idle
+		 * always enable line clock even if no data
+		 */
+		.pcr = 0xf0c08080,
+		.bpp = 16,
+	},
+};
+
+static struct imx_fb_platform_data pca100_fb_data = {
+	.mode = pca100_fb_modes,
+	.num_modes = ARRAY_SIZE(pca100_fb_modes),
+
+	.pwmr		= 0x00A903FF,
+	.lscr1		= 0x00120300,
+	.dmacr		= 0x00020010,
+};
+
 static void __init pca100_init(void)
 {
 	int ret;
@@ -372,6 +436,8 @@ static void __init pca100_init(void)
 		mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
 	}
 
+	mxc_register_device(&mxc_fb_device, &pca100_fb_data);
+
 	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
-- 
1.7.1



From kmpark at infradead.org  Fri Jun 18 03:44:59 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 18 Jun 2010 16:44:59 +0900
Subject: Several questions regarding ARCH_S3C2410
In-Reply-To: <AANLkTimPk6mtyB57jXuAq1ugQseS655OCPEuP9-qZYoT@mail.gmail.com>
References: <AANLkTimPk6mtyB57jXuAq1ugQseS655OCPEuP9-qZYoT@mail.gmail.com>
Message-ID: <AANLkTilbEYR28lrVBAIXXuJ6sEf5uCp4Tpr7wriBZLj3@mail.gmail.com>

CCing Mr. Kim

On Fri, Jun 18, 2010 at 12:43 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> Hi Ben,
>
> While working towards a unified kernel, I found that ARCH_S3C2410 actually
> includes multiple mach-* already.
>
> linux-2.6$ git grep "ARCH_S3C2410" arch/arm/Makefile
> arch/arm/Makefile:machine-$(CONFIG_ARCH_S3C2410) ? ? ? ?:= s3c2410 s3c2400
> s3c2412 s3c2416 s3c2440 s3c2443
>
> There are several questions though:
>
> 1. It looks like only s3c2410 is significant, so all the common definitions
> ? like PHYS_OFFSET are actually same across all mach-s3c24* (except for
> ? s3c24a0) ? Yet I've found arch/arm/mach-s3c2400/include/mach/memory.h,
> ? where a different PHYS_OFFSET is defined, just feel a bit confused.
>
> 2. So except for s3c24a0, theretically, it's possible to combine all these
> ? mach into something mach-s3c24xx?
>
> 3. When trying building of s3c2410_defconfig, there are a lot complaints
> ? about re-definitions of {in,out}[s]{b,w,l}. ?Taking a look into io.h,
> ? I'm wondering if it's possible to use those definitions in asm/io.h?
> ? (possibly with a customized __io())
>
> In file included from linux-2.6/include/linux/scatterlist.h:8,
> ? ? ? ? ? ? ? ? from linux-2.6/include/linux/dma-mapping.h:7,
> ? ? ? ? ? ? ? ? from linux-2.6/include/linux/dmaengine.h:26,
> ? ? ? ? ? ? ? ? from linux-2.6/include/linux/skbuff.h:30,
> ? ? ? ? ? ? ? ? from linux-2.6/lib/kobject_uevent.c:24:
> linux-2.6/arch/arm/include/asm/io.h:137: warning: "outb" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:196: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:138: warning: "outw" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:197: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:140: warning: "outl" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:198: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:143: warning: "inb" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:193: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:144: warning: "inw" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:194: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:146: warning: "inl" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:195: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:149: warning: "outsb" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:207: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:150: warning: "outsw" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:208: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:151: warning: "outsl" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:209: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:153: warning: "insb" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:203: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:154: warning: "insw" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:204: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:155: warning: "insl" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:205: note: this is
> the location of the previous definition
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From adrian.wenl at gmail.com  Fri Jun 18 03:55:21 2010
From: adrian.wenl at gmail.com (Lei Wen)
Date: Fri, 18 Jun 2010 15:55:21 +0800
Subject: [PATCH 01/25] pxa3xx_nand: condense the flash definition
In-Reply-To: <AANLkTinOsQ8AcH-As91CRqrEQVnXdsm_CmFQgyj7gI1_@mail.gmail.com>
References: <AANLkTil1FnPkGS7l6W0HWeXyOxXzWbZkvFWY4jJF_I_A@mail.gmail.com>
	<AANLkTinOsQ8AcH-As91CRqrEQVnXdsm_CmFQgyj7gI1_@mail.gmail.com>
Message-ID: <AANLkTim9O5kuGzvQoB65fWDr3Bi9siiVBMCPx6heqZjd@mail.gmail.com>

On Fri, Jun 18, 2010 at 2:23 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 1:32 PM, Haojian Zhuang
> <haojian.zhuang at gmail.com> wrote:
>> From 76684334fbf214ab164ed07791b02535a3f04779 Mon Sep 17 00:00:00 2001
>> From: Lei Wen <leiwen at marvell.com>
>> Date: Sat, 20 Mar 2010 19:01:23 +0800
>> Subject: [PATCH 01/25] pxa3xx_nand: condense the flash definition
>>
>> Adding a new flash definition would need less code.
>> Keep the platform passing flash defition method.
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?^^^^^^^^ definition?
Oops... Typo...
>> If one flash is both defined in platform data and builtin table,
>> driver would select the one from platform data first.
>
> This makes sense. I thin the CONFIG_MTD_NAND_PXA3xx_BUILTIN is introduced
> as an optimization so to reduce the code size if platform flash definition
> is provided, instead of an option to remove built-in definitions.

Em... I agree...
>
>>
>> By this way, platform could select the timing most suit for itself,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ^^^^ suitable
>> not need to follow the common settings.
>>
>> Signed-off-by: Lei Wen <leiwen at marvell.com>
>> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
>
> // there are some line wrapped though, maybe it's my gmail fault.
>
>> ---
>> ?arch/arm/plat-pxa/include/plat/pxa3xx_nand.h | ? 37 ----
>> ?drivers/mtd/nand/Kconfig ? ? ? ? ? ? ? ? ? ? | ? ?7 -
>> ?drivers/mtd/nand/pxa3xx_nand.c ? ? ? ? ? ? ? | ?241 +++++++-------------------
>> ?3 files changed, 66 insertions(+), 219 deletions(-)
>>
>> diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
>> b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
>> index 3478eae..7e5a28f 100644
>> --- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
>> +++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
>> @@ -4,43 +4,6 @@
>> ?#include <linux/mtd/mtd.h>
>> ?#include <linux/mtd/partitions.h>
>>
>> -struct pxa3xx_nand_timing {
>> - ? ? ? unsigned int ? ?tCH; ?/* Enable signal hold time */
>> - ? ? ? unsigned int ? ?tCS; ?/* Enable signal setup time */
>> - ? ? ? unsigned int ? ?tWH; ?/* ND_nWE high duration */
>> - ? ? ? unsigned int ? ?tWP; ?/* ND_nWE pulse time */
>> - ? ? ? unsigned int ? ?tRH; ?/* ND_nRE high duration */
>> - ? ? ? unsigned int ? ?tRP; ?/* ND_nRE pulse width */
>> - ? ? ? unsigned int ? ?tR; ? /* ND_nWE high to ND_nRE low for read */
>> - ? ? ? unsigned int ? ?tWHR; /* ND_nWE high to ND_nRE low for status read */
>> - ? ? ? unsigned int ? ?tAR; ?/* ND_ALE low to ND_nRE low delay */
>> -};
>> -
>> -struct pxa3xx_nand_cmdset {
>> - ? ? ? uint16_t ? ? ? ?read1;
>> - ? ? ? uint16_t ? ? ? ?read2;
>> - ? ? ? uint16_t ? ? ? ?program;
>> - ? ? ? uint16_t ? ? ? ?read_status;
>> - ? ? ? uint16_t ? ? ? ?read_id;
>> - ? ? ? uint16_t ? ? ? ?erase;
>> - ? ? ? uint16_t ? ? ? ?reset;
>> - ? ? ? uint16_t ? ? ? ?lock;
>> - ? ? ? uint16_t ? ? ? ?unlock;
>> - ? ? ? uint16_t ? ? ? ?lock_status;
>> -};
>> -
>> -struct pxa3xx_nand_flash {
>> - ? ? ? const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
>> - ? ? ? const struct pxa3xx_nand_cmdset *cmdset;
>> -
>> - ? ? ? uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */
>> - ? ? ? uint32_t page_size; ? ? /* Page size in bytes (PAGE_SZ) */
>> - ? ? ? uint32_t flash_width; ? /* Width of Flash memory (DWIDTH_M) */
>> - ? ? ? uint32_t dfc_width; ? ? /* Width of flash controller(DWIDTH_C) */
>> - ? ? ? uint32_t num_blocks; ? ?/* Number of physical blocks in Flash */
>> - ? ? ? uint32_t chip_id;
>> -};
>> -
>
> So does this prevent board code from defining their own timing and etc?

No, platform could define its own timing. If there is definition for
the same chip,
driver would choose the one from platform definition first.

>
>> ?struct pxa3xx_nand_platform_data {
>>
>> ? ? ? ?/* the data flash bus is shared between the Static Memory
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index 98a04b3..9a35d92 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -399,13 +399,6 @@ config MTD_NAND_PXA3xx
>> ? ? ? ? ?This enables the driver for the NAND flash device found on
>> ? ? ? ? ?PXA3xx processors
>>
>> -config MTD_NAND_PXA3xx_BUILTIN
>> - ? ? ? bool "Use builtin definitions for some NAND chips (deprecated)"
>> - ? ? ? depends on MTD_NAND_PXA3xx
>> - ? ? ? help
>> - ? ? ? ? This enables builtin definitions for some NAND chips. This
>> - ? ? ? ? is deprecated in favor of platform specific data.
>> -
>> ?config MTD_NAND_CM_X270
>> ? ? ? ?tristate "Support for NAND Flash on CM-X270 modules"
>> ? ? ? ?depends on MTD_NAND && MACH_ARMCORE
>> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
>> index e02fa4f..013e075 100644
>> --- a/drivers/mtd/nand/pxa3xx_nand.c
>> +++ b/drivers/mtd/nand/pxa3xx_nand.c
>
> ... snipped ...
>
>> ?static struct pxa3xx_nand_timing default_timing;
>> ?static struct pxa3xx_nand_flash default_flash;
>>
>> -static struct pxa3xx_nand_cmdset smallpage_cmdset = {
>> - ? ? ? .read1 ? ? ? ? ?= 0x0000,
>> - ? ? ? .read2 ? ? ? ? ?= 0x0050,
>> - ? ? ? .program ? ? ? ?= 0x1080,
>> - ? ? ? .read_status ? ?= 0x0070,
>> - ? ? ? .read_id ? ? ? ?= 0x0090,
>> - ? ? ? .erase ? ? ? ? ?= 0xD060,
>> - ? ? ? .reset ? ? ? ? ?= 0x00FF,
>> - ? ? ? .lock ? ? ? ? ? = 0x002A,
>> - ? ? ? .unlock ? ? ? ? = 0x2423,
>> - ? ? ? .lock_status ? ?= 0x007A,
>> -};
>> -
>> -static struct pxa3xx_nand_cmdset largepage_cmdset = {
>> +const static struct pxa3xx_nand_cmdset cmdset = {
>
> So how to handle the difference of command set between smallpage and
> largepage?

The only difference of cmdsetbetween the small page and large page is
at the read command.
While large page is 0x3000, small page is 0x0.
This handle is not address in this patch, but put to latter patch of
0006 in this seris patch set.
For whole patch set chnage is so large, that it is not easy to make it
very clear at each patch...



>
>> ? ? ? ?.read1 ? ? ? ? ?= 0x3000,
>> ? ? ? ?.read2 ? ? ? ? ?= 0x0050,
>> ? ? ? ?.program ? ? ? ?= 0x1080,
>> @@ -203,143 +225,26 @@ static struct pxa3xx_nand_cmdset largepage_cmdset = {
>> ? ? ? ?.lock_status ? ?= 0x007A,
>> ?};
>>
>> -#ifdef CONFIG_MTD_NAND_PXA3xx_BUILTIN
>> -static struct pxa3xx_nand_timing samsung512MbX16_timing = {
>> - ? ? ? .tCH ? ?= 10,
>> - ? ? ? .tCS ? ?= 0,
>> - ? ? ? .tWH ? ?= 20,
>> - ? ? ? .tWP ? ?= 40,
>
> ...
>
>> +static struct pxa3xx_nand_timing __devinitdata timing[] = {
>
> Better with some comment columns like below:
>
> ?/* ? ? ? ?tCH tCS tWH tWP ... */
>> + ? ? ? /* Samsung NAND series */
>> + ? ? ? { 10, ?0, 20, 40, 30, 40, 11123, 110, 10, },
>> + ? ? ? /* Micron NAND series */
>> + ? ? ? { 10, 25, 15, 25, 15, 30, 25000, ?60, 10, },
>> + ? ? ? /* ST NAND series */
>> + ? ? ? { 10, 35, 15, 25, 15, 25, 25000, ?60, 10, },
>
> Now define something like
>
> #define NAND_TIMING_SAMSUNG ? ? (&timing[0])
> #define NAND_TIMING_MICRON ? ? ?(&timing[1])
> #define NAND_TIMING_ST ? ? ? ? ?(&timing[2])
>
>> ?};
>>
>> -static struct pxa3xx_nand_flash samsung32GbX8 = {
>> - ? ? ? .timing ? ? ? ? = &samsung512MbX16_timing,
>> - ? ? ? .cmdset ? ? ? ? = &smallpage_cmdset,
>> - ? ? ? .page_per_block = 128,
>> - ? ? ? .page_size ? ? ?= 4096,
>> - ? ? ? .flash_width ? ?= 8,
>> - ? ? ? .dfc_width ? ? ?= 8,
>> - ? ? ? .num_blocks ? ? = 8192,
>> - ? ? ? .chip_id ? ? ? ?= 0xd7ec,
>> +static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
>
> /* ? ? ? ?Chip ID, page per block, page size, flash width, .... */
Agree.

>
>> + ? ? ? { 0x46ec, ?32, ?512, 16, 16, 4096, &timing[0], },
>> + ? ? ? { 0xdaec, ?64, 2048, ?8, ?8, 2048, &timing[0], },
>> + ? ? ? { 0xd7ec, 128, 4096, ?8, ?8, 8192, &timing[0], },
>> + ? ? ? { 0xa12c, ?64, 2048, ?8, ?8, 1024, &timing[1], },
>> + ? ? ? { 0xb12c, ?64, 2048, 16, 16, 1024, &timing[1], },
>> + ? ? ? { 0xdc2c, ?64, 2048, ?8, ?8, 4096, &timing[1], },
>> + ? ? ? { 0xcc2c, ?64, 2048, 16, 16, 4096, &timing[1], },
>> + ? ? ? { 0xba20, ?64, 2048, 16, 16, 2048, &timing[2], },
>> ?};
>
> BTW, I like the array above very much.
>
>>
>> -static struct pxa3xx_nand_timing micron_timing = {
>> - ? ? ? .tCH ? ?= 10,
>> - ? ? ? .tCS ? ?= 25,
>> - ? ? ? .tWH ? ?= 15,
>> - ? ? ? .tWP ? ?= 25,
>> - ? ? ? .tRH ? ?= 15,
>> - ? ? ? .tRP ? ?= 30,
>> - ? ? ? .tR ? ? = 25000,
>
> ... snipped ...
>
>> -};
>> -#endif /* CONFIG_MTD_NAND_PXA3xx_BUILTIN */
>> -
>> ?#define NDTR0_tCH(c) ? (min((c), 7) << 19)
>> ?#define NDTR0_tCS(c) ? (min((c), 7) << 16)
>> ?#define NDTR0_tWH(c) ? (min((c), 7) << 11)
>> @@ -412,7 +317,6 @@ static int prepare_read_prog_cmd(struct
>> pxa3xx_nand_info *info,
>> ? ? ? ? ? ? ? ? ? ? ? ?uint16_t cmd, int column, int page_addr)
>> ?{
>> ? ? ? ?const struct pxa3xx_nand_flash *f = info->flash_info;
>> - ? ? ? const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
>
> I think it's better to keep a local pointer. Reference within a function
> to a global structure is always a bad idea, one day you will find you've
> to modify all these references again when you add a new cmdset.
>
> And most of the modifications below can thus be removed and patch simplified.

My original thinking is for the cmdset is almost standardized, so make
such change for global structure.
Well, the suggestion also make sense. I would revert this change.

Best regards,
Lei


From eric.y.miao at gmail.com  Fri Jun 18 04:00:59 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 16:00:59 +0800
Subject: [PATCH 01/25] pxa3xx_nand: condense the flash definition
In-Reply-To: <AANLkTim9O5kuGzvQoB65fWDr3Bi9siiVBMCPx6heqZjd@mail.gmail.com>
References: <AANLkTil1FnPkGS7l6W0HWeXyOxXzWbZkvFWY4jJF_I_A@mail.gmail.com> 
	<AANLkTinOsQ8AcH-As91CRqrEQVnXdsm_CmFQgyj7gI1_@mail.gmail.com> 
	<AANLkTim9O5kuGzvQoB65fWDr3Bi9siiVBMCPx6heqZjd@mail.gmail.com>
Message-ID: <AANLkTimGzVtuJuuxipim-f6UhdK287EjF41UlhdKCWRM@mail.gmail.com>

>>> -struct pxa3xx_nand_timing {
>>> - ? ? ? unsigned int ? ?tCH; ?/* Enable signal hold time */
>>> - ? ? ? unsigned int ? ?tCS; ?/* Enable signal setup time */
>>> - ? ? ? unsigned int ? ?tWH; ?/* ND_nWE high duration */
>>> - ? ? ? unsigned int ? ?tWP; ?/* ND_nWE pulse time */
>>> - ? ? ? unsigned int ? ?tRH; ?/* ND_nRE high duration */
>>> - ? ? ? unsigned int ? ?tRP; ?/* ND_nRE pulse width */
>>> - ? ? ? unsigned int ? ?tR; ? /* ND_nWE high to ND_nRE low for read */
>>> - ? ? ? unsigned int ? ?tWHR; /* ND_nWE high to ND_nRE low for status read */
>>> - ? ? ? unsigned int ? ?tAR; ?/* ND_ALE low to ND_nRE low delay */
>>> -};
>>> -
>>> -struct pxa3xx_nand_cmdset {
>>> - ? ? ? uint16_t ? ? ? ?read1;
>>> - ? ? ? uint16_t ? ? ? ?read2;
>>> - ? ? ? uint16_t ? ? ? ?program;
>>> - ? ? ? uint16_t ? ? ? ?read_status;
>>> - ? ? ? uint16_t ? ? ? ?read_id;
>>> - ? ? ? uint16_t ? ? ? ?erase;
>>> - ? ? ? uint16_t ? ? ? ?reset;
>>> - ? ? ? uint16_t ? ? ? ?lock;
>>> - ? ? ? uint16_t ? ? ? ?unlock;
>>> - ? ? ? uint16_t ? ? ? ?lock_status;
>>> -};
>>> -
>>> -struct pxa3xx_nand_flash {
>>> - ? ? ? const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
>>> - ? ? ? const struct pxa3xx_nand_cmdset *cmdset;
>>> -
>>> - ? ? ? uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */
>>> - ? ? ? uint32_t page_size; ? ? /* Page size in bytes (PAGE_SZ) */
>>> - ? ? ? uint32_t flash_width; ? /* Width of Flash memory (DWIDTH_M) */
>>> - ? ? ? uint32_t dfc_width; ? ? /* Width of flash controller(DWIDTH_C) */
>>> - ? ? ? uint32_t num_blocks; ? ?/* Number of physical blocks in Flash */
>>> - ? ? ? uint32_t chip_id;
>>> -};
>>> -
>>
>> So does this prevent board code from defining their own timing and etc?
>
> No, platform could define its own timing. If there is definition for
> the same chip,
> driver would choose the one from platform definition first.
>

I'm seeing pxa3xx_nand_flash being referenced in pxa3xx_nand_platform_data
below, though?

struct pxa3xx_nand_platform_data {

      ......

	const struct pxa3xx_nand_flash * 	flash;
	size_t					num_flash;
};


From adrian.wenl at gmail.com  Fri Jun 18 04:08:13 2010
From: adrian.wenl at gmail.com (Lei Wen)
Date: Fri, 18 Jun 2010 16:08:13 +0800
Subject: [PATCH 02/25] pxa3xx_nand: introduce common timing to reduce read
	id times
In-Reply-To: <AANLkTil6QDRdh3s63J9Mm-B1qjMcnYjEEm-W5lC1NXVb@mail.gmail.com>
References: <AANLkTim1qcVoqSS7T8bE0Vsu6phC2iY_Ok671WYHcD0z@mail.gmail.com>
	<AANLkTil6QDRdh3s63J9Mm-B1qjMcnYjEEm-W5lC1NXVb@mail.gmail.com>
Message-ID: <AANLkTikbzXgwMvnNVRkcOO-9El9hmAXhKZK_dFgStbwY@mail.gmail.com>

On Fri, Jun 18, 2010 at 2:33 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 1:33 PM, Haojian Zhuang
> <haojian.zhuang at gmail.com> wrote:
>> From 832379d0da4d772e45872de365053f9a15733967 Mon Sep 17 00:00:00 2001
>> From: Lei Wen <leiwen at marvell.com>
>> Date: Wed, 2 Jun 2010 21:50:25 +0800
>> Subject: [PATCH 02/25] pxa3xx_nand: introduce common timing to reduce
>> read id times
>>
>> We certainly don't need to send read id command times by times, since
>> we already know what the id is after the first read id...
>>
>> So create a common timing which could ensure it would successfully read id
>> out all supported chip. Then follow the build-in table to reconfigure
>> the timing.
>
> This is clever trick we'd like to have. And I'd prefer to call this a
> 'loose timing'
> or a 'default safe timing' instead of 'common timing'.
>
>>
>> Signed-off-by: Lei Wen <leiwen at marvell.com>
>> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
>> ---
>> ?drivers/mtd/nand/pxa3xx_nand.c | ? 72 ++++++++++++++++-----------------------
>> ?1 files changed, 30 insertions(+), 42 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
>> index 013e075..f939083 100644
>> --- a/drivers/mtd/nand/pxa3xx_nand.c
>> +++ b/drivers/mtd/nand/pxa3xx_nand.c
>> @@ -226,23 +226,26 @@ const static struct pxa3xx_nand_cmdset cmdset = {
>> ?};
>>
>> ?static struct pxa3xx_nand_timing __devinitdata timing[] = {
>> + ? ? ? /* common timing used to detect flash id */
>> + ? ? ? { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
>
> Make sure this is the loose and safe enough timing.
>
>> ? ? ? ?/* Samsung NAND series */
>> - ? ? ? { 10, ?0, 20, 40, 30, 40, 11123, 110, 10, },
>> + ? ? ? { 10, ?0, 20, ?40, 30, ?40, 11123, 110, 10, },
>> ? ? ? ?/* Micron NAND series */
>> - ? ? ? { 10, 25, 15, 25, 15, 30, 25000, ?60, 10, },
>> + ? ? ? { 10, 25, 15, ?25, 15, ?30, 25000, ?60, 10, },
>> ? ? ? ?/* ST NAND series */
>> - ? ? ? { 10, 35, 15, 25, 15, 25, 25000, ?60, 10, },
>> + ? ? ? { 10, 35, 15, ?25, 15, ?25, 25000, ?60, 10, },
>> ?};
>>
>> ?static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
>> - ? ? ? { 0x46ec, ?32, ?512, 16, 16, 4096, &timing[0], },
>> - ? ? ? { 0xdaec, ?64, 2048, ?8, ?8, 2048, &timing[0], },
>> - ? ? ? { 0xd7ec, 128, 4096, ?8, ?8, 8192, &timing[0], },
>> - ? ? ? { 0xa12c, ?64, 2048, ?8, ?8, 1024, &timing[1], },
>> - ? ? ? { 0xb12c, ?64, 2048, 16, 16, 1024, &timing[1], },
>> - ? ? ? { 0xdc2c, ?64, 2048, ?8, ?8, 4096, &timing[1], },
>> - ? ? ? { 0xcc2c, ?64, 2048, 16, 16, 4096, &timing[1], },
>> - ? ? ? { 0xba20, ?64, 2048, 16, 16, 2048, &timing[2], },
>> + ? ? ? { ? ? ?0, ? 0, ? ?0, ?0, ?0, ? ?0, &timing[0], },
>> + ? ? ? { 0x46ec, ?32, ?512, 16, 16, 4096, &timing[1], },
>> + ? ? ? { 0xdaec, ?64, 2048, ?8, ?8, 2048, &timing[1], },
>> + ? ? ? { 0xd7ec, 128, 4096, ?8, ?8, 8192, &timing[1], },
>> + ? ? ? { 0xa12c, ?64, 2048, ?8, ?8, 1024, &timing[2], },
>> + ? ? ? { 0xb12c, ?64, 2048, 16, 16, 1024, &timing[2], },
>> + ? ? ? { 0xdc2c, ?64, 2048, ?8, ?8, 4096, &timing[2], },
>> + ? ? ? { 0xcc2c, ?64, 2048, 16, 16, 4096, &timing[2], },
>> + ? ? ? { 0xba20, ?64, 2048, 16, 16, 2048, &timing[3], },
>> ?};
>>
>> ?#define NDTR0_tCH(c) ? (min((c), 7) << 19)
>> @@ -859,12 +862,6 @@ static int pxa3xx_nand_config_flash(struct
>> pxa3xx_nand_info *info,
>> ? ? ? ?struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
>> ? ? ? ?uint32_t ndcr = 0x00000FFF; /* disable all interrupts */
>>
>> - ? ? ? if (f->page_size != 2048 && f->page_size != 512)
>> - ? ? ? ? ? ? ? return -EINVAL;
>> -
>> - ? ? ? if (f->flash_width != 16 && f->flash_width != 8)
>> - ? ? ? ? ? ? ? return -EINVAL;
>> -
>
> I do think these are sanity check, that's useful to prevent incorrectly defined
> data (esp. coming from board code). Can we define the loose flash type as:
>
>> ?static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
>> + ? ? ? { ?0x0000, ? 0, ? ?512, ?8, ?8, ? ?0, &timing[0], },
>> + ? ? ? { 0x46ec, ?32, ?512, 16, 16, 4096, &timing[1], },
>> + ? ? ? { 0xdaec, ?64, 2048, ?8, ?8, 2048, &timing[1], },
>
> with a comment of /* default flash type to detect ID */?
>
> My understanding is the minimum requirement to detect the NAND ID is a
> loose timing and 512 small page, 8-bit wide bus, so with a chip_id being
> 0x0000, that should be enough to tell it's a special flash type to detect ID.

There is no need to add the flash page size and bus width for the
common timing, or loose timing...
For the chip identification only need reset and read id command, and
reset and read id command only care
for the first command in NDCB0 and the timing setting in NDTR0CS0 and
NDTR1CS0, the page size is not useful
here and could make confussion if give such definition...
>
>> ? ? ? ?/* calculate flash information */
>> ? ? ? ?info->oob_size = (f->page_size == 2048) ? 64 : 16;
>> ? ? ? ?info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
>> @@ -976,36 +973,27 @@ static int pxa3xx_nand_detect_flash(struct
>> pxa3xx_nand_info *info,
>> ? ? ? ? ? ? ? ?if (pxa3xx_nand_detect_config(info) == 0)
>> ? ? ? ? ? ? ? ? ? ? ? ?return 0;
>>
>> - ? ? ? for (i = 0; i<pdata->num_flash; ++i) {
>> - ? ? ? ? ? ? ? f = pdata->flash + i;
>> -
>> - ? ? ? ? ? ? ? if (pxa3xx_nand_config_flash(info, f))
>> - ? ? ? ? ? ? ? ? ? ? ? continue;
>> -
>> - ? ? ? ? ? ? ? if (__readid(info, &id))
>> - ? ? ? ? ? ? ? ? ? ? ? continue;
>> -
>> - ? ? ? ? ? ? ? if (id == f->chip_id)
>> - ? ? ? ? ? ? ? ? ? ? ? return 0;
>> - ? ? ? }
>> -
>> - ? ? ? for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
>> -
>> - ? ? ? ? ? ? ? f = &builtin_flash_types[i];
>> -
>> - ? ? ? ? ? ? ? if (pxa3xx_nand_config_flash(info, f))
>> - ? ? ? ? ? ? ? ? ? ? ? continue;
>> -
>> - ? ? ? ? ? ? ? if (__readid(info, &id))
>> - ? ? ? ? ? ? ? ? ? ? ? continue;
>> -
>> - ? ? ? ? ? ? ? if (id == f->chip_id)
>> + ? ? ? f = &builtin_flash_types[0];
>> + ? ? ? pxa3xx_nand_config_flash(info, f);
>> + ? ? ? if (__readid(info, &id))
>> + ? ? ? ? ? ? ? goto fail_detect;
>> +
>> + ? ? ? for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
>> + ? ? ? ? ? ? ? if (i < pdata->num_flash)
>> + ? ? ? ? ? ? ? ? ? ? ? f = pdata->flash + i;
>> + ? ? ? ? ? ? ? else
>> + ? ? ? ? ? ? ? ? ? ? ? f = &builtin_flash_types[i - pdata->num_flash + 1];
>
> This looks a bit tricky and difficult to read, can you improve the
> readability here?

The chip id identification logic here is changed in latter patch in
this patch set...
If from the last patch of view, does this part looks better?

>
>> + ? ? ? ? ? ? ? if (f->chip_id == id) {
>> + ? ? ? ? ? ? ? ? ? ? ? dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
>> + ? ? ? ? ? ? ? ? ? ? ? pxa3xx_nand_config_flash(info, f);
>> ? ? ? ? ? ? ? ? ? ? ? ?return 0;
>> + ? ? ? ? ? ? ? }
>> ? ? ? ?}
>>
>> ? ? ? ?dev_warn(&info->pdev->dev,
>> - ? ? ? ? ? ? ? ?"failed to detect configured nand flash; found %04x instead of\n",
>> + ? ? ? ? ? ? ? ? ? ? ? "failed to detect configured nand flash; found %04x instead of\n",
>> ? ? ? ? ? ? ? ? id);
>> +fail_detect:
>> ? ? ? ?return -ENODEV;
>> ?}
>>
>
> I'm generally OK with the idea.
>
Best regards,
Lei


From adrian.wenl at gmail.com  Fri Jun 18 04:10:51 2010
From: adrian.wenl at gmail.com (Lei Wen)
Date: Fri, 18 Jun 2010 16:10:51 +0800
Subject: [PATCH 01/25] pxa3xx_nand: condense the flash definition
In-Reply-To: <AANLkTimGzVtuJuuxipim-f6UhdK287EjF41UlhdKCWRM@mail.gmail.com>
References: <AANLkTil1FnPkGS7l6W0HWeXyOxXzWbZkvFWY4jJF_I_A@mail.gmail.com>
	<AANLkTinOsQ8AcH-As91CRqrEQVnXdsm_CmFQgyj7gI1_@mail.gmail.com>
	<AANLkTim9O5kuGzvQoB65fWDr3Bi9siiVBMCPx6heqZjd@mail.gmail.com>
	<AANLkTimGzVtuJuuxipim-f6UhdK287EjF41UlhdKCWRM@mail.gmail.com>
Message-ID: <AANLkTindDgsvPK-ZZsyB2cdsrh0IyykBuhgStuwvyIdg@mail.gmail.com>

On Fri, Jun 18, 2010 at 4:00 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>>>> -struct pxa3xx_nand_timing {
>>>> - ? ? ? unsigned int ? ?tCH; ?/* Enable signal hold time */
>>>> - ? ? ? unsigned int ? ?tCS; ?/* Enable signal setup time */
>>>> - ? ? ? unsigned int ? ?tWH; ?/* ND_nWE high duration */
>>>> - ? ? ? unsigned int ? ?tWP; ?/* ND_nWE pulse time */
>>>> - ? ? ? unsigned int ? ?tRH; ?/* ND_nRE high duration */
>>>> - ? ? ? unsigned int ? ?tRP; ?/* ND_nRE pulse width */
>>>> - ? ? ? unsigned int ? ?tR; ? /* ND_nWE high to ND_nRE low for read */
>>>> - ? ? ? unsigned int ? ?tWHR; /* ND_nWE high to ND_nRE low for status read */
>>>> - ? ? ? unsigned int ? ?tAR; ?/* ND_ALE low to ND_nRE low delay */
>>>> -};
>>>> -
>>>> -struct pxa3xx_nand_cmdset {
>>>> - ? ? ? uint16_t ? ? ? ?read1;
>>>> - ? ? ? uint16_t ? ? ? ?read2;
>>>> - ? ? ? uint16_t ? ? ? ?program;
>>>> - ? ? ? uint16_t ? ? ? ?read_status;
>>>> - ? ? ? uint16_t ? ? ? ?read_id;
>>>> - ? ? ? uint16_t ? ? ? ?erase;
>>>> - ? ? ? uint16_t ? ? ? ?reset;
>>>> - ? ? ? uint16_t ? ? ? ?lock;
>>>> - ? ? ? uint16_t ? ? ? ?unlock;
>>>> - ? ? ? uint16_t ? ? ? ?lock_status;
>>>> -};
>>>> -
>>>> -struct pxa3xx_nand_flash {
>>>> - ? ? ? const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
>>>> - ? ? ? const struct pxa3xx_nand_cmdset *cmdset;
>>>> -
>>>> - ? ? ? uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */
>>>> - ? ? ? uint32_t page_size; ? ? /* Page size in bytes (PAGE_SZ) */
>>>> - ? ? ? uint32_t flash_width; ? /* Width of Flash memory (DWIDTH_M) */
>>>> - ? ? ? uint32_t dfc_width; ? ? /* Width of flash controller(DWIDTH_C) */
>>>> - ? ? ? uint32_t num_blocks; ? ?/* Number of physical blocks in Flash */
>>>> - ? ? ? uint32_t chip_id;
>>>> -};
>>>> -
>>>
>>> So does this prevent board code from defining their own timing and etc?
>>
>> No, platform could define its own timing. If there is definition for
>> the same chip,
>> driver would choose the one from platform definition first.
>>
>
> I'm seeing pxa3xx_nand_flash being referenced in pxa3xx_nand_platform_data
> below, though?
>
> struct pxa3xx_nand_platform_data {
>
> ? ? ?......
>
> ? ? ? ?const struct pxa3xx_nand_flash * ? ? ? ?flash;
> ? ? ? ?size_t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?num_flash;
> };
>

Yes, platform could define its own pxa3xx_nand_flash structure in its
own code, and pass the structure to let driver know.


From eric.y.miao at gmail.com  Fri Jun 18 04:12:41 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 16:12:41 +0800
Subject: [PATCH 02/25] pxa3xx_nand: introduce common timing to reduce read
	id times
In-Reply-To: <AANLkTikbzXgwMvnNVRkcOO-9El9hmAXhKZK_dFgStbwY@mail.gmail.com>
References: <AANLkTim1qcVoqSS7T8bE0Vsu6phC2iY_Ok671WYHcD0z@mail.gmail.com> 
	<AANLkTil6QDRdh3s63J9Mm-B1qjMcnYjEEm-W5lC1NXVb@mail.gmail.com> 
	<AANLkTikbzXgwMvnNVRkcOO-9El9hmAXhKZK_dFgStbwY@mail.gmail.com>
Message-ID: <AANLkTikDDFYY65l5YYGW3a0O2bWDyKRO6VRb15aaFtF7@mail.gmail.com>

>>> - ? ? ? if (f->page_size != 2048 && f->page_size != 512)
>>> - ? ? ? ? ? ? ? return -EINVAL;
>>> -
>>> - ? ? ? if (f->flash_width != 16 && f->flash_width != 8)
>>> - ? ? ? ? ? ? ? return -EINVAL;
>>> -
>>
>> I do think these are sanity check, that's useful to prevent incorrectly defined
>> data (esp. coming from board code). Can we define the loose flash type as:
>>
>>> ?static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
>>> + ? ? ? { ?0x0000, ? 0, ? ?512, ?8, ?8, ? ?0, &timing[0], },
>>> + ? ? ? { 0x46ec, ?32, ?512, 16, 16, 4096, &timing[1], },
>>> + ? ? ? { 0xdaec, ?64, 2048, ?8, ?8, 2048, &timing[1], },
>>
>> with a comment of /* default flash type to detect ID */?
>>
>> My understanding is the minimum requirement to detect the NAND ID is a
>> loose timing and 512 small page, 8-bit wide bus, so with a chip_id being
>> 0x0000, that should be enough to tell it's a special flash type to detect ID.
>
> There is no need to add the flash page size and bus width for the
> common timing, or loose timing...
> For the chip identification only need reset and read id command, and
> reset and read id command only care
> for the first command in NDCB0 and the timing setting in NDTR0CS0 and
> NDTR1CS0, the page size is not useful
> here and could make confussion if give such definition...

I know, but I'd like to keep the checking of page_size, and flash_width,
if you take a look into the rest of the code how much it is assumed that
page_size being either 2048 or 512, flash_width being 8 or 16, you'll
know why such an error checking here is mandatory actually.

>>
>>> ? ? ? ?/* calculate flash information */
>>> ? ? ? ?info->oob_size = (f->page_size == 2048) ? 64 : 16;
>>> ? ? ? ?info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
>>> @@ -976,36 +973,27 @@ static int pxa3xx_nand_detect_flash(struct
>>> pxa3xx_nand_info *info,
>>> ? ? ? ? ? ? ? ?if (pxa3xx_nand_detect_config(info) == 0)
>>> ? ? ? ? ? ? ? ? ? ? ? ?return 0;
>>>
>>> - ? ? ? for (i = 0; i<pdata->num_flash; ++i) {
>>> - ? ? ? ? ? ? ? f = pdata->flash + i;
>>> -
>>> - ? ? ? ? ? ? ? if (pxa3xx_nand_config_flash(info, f))
>>> - ? ? ? ? ? ? ? ? ? ? ? continue;
>>> -
>>> - ? ? ? ? ? ? ? if (__readid(info, &id))
>>> - ? ? ? ? ? ? ? ? ? ? ? continue;
>>> -
>>> - ? ? ? ? ? ? ? if (id == f->chip_id)
>>> - ? ? ? ? ? ? ? ? ? ? ? return 0;
>>> - ? ? ? }
>>> -
>>> - ? ? ? for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
>>> -
>>> - ? ? ? ? ? ? ? f = &builtin_flash_types[i];
>>> -
>>> - ? ? ? ? ? ? ? if (pxa3xx_nand_config_flash(info, f))
>>> - ? ? ? ? ? ? ? ? ? ? ? continue;
>>> -
>>> - ? ? ? ? ? ? ? if (__readid(info, &id))
>>> - ? ? ? ? ? ? ? ? ? ? ? continue;
>>> -
>>> - ? ? ? ? ? ? ? if (id == f->chip_id)
>>> + ? ? ? f = &builtin_flash_types[0];
>>> + ? ? ? pxa3xx_nand_config_flash(info, f);
>>> + ? ? ? if (__readid(info, &id))
>>> + ? ? ? ? ? ? ? goto fail_detect;
>>> +
>>> + ? ? ? for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
>>> + ? ? ? ? ? ? ? if (i < pdata->num_flash)
>>> + ? ? ? ? ? ? ? ? ? ? ? f = pdata->flash + i;
>>> + ? ? ? ? ? ? ? else
>>> + ? ? ? ? ? ? ? ? ? ? ? f = &builtin_flash_types[i - pdata->num_flash + 1];
>>
>> This looks a bit tricky and difficult to read, can you improve the
>> readability here?
>
> The chip id identification logic here is changed in latter patch in
> this patch set...
> If from the last patch of view, does this part looks better?
>

Not sure, I'd rather this being separated into two loops if that helps
readability.

>>
>>> + ? ? ? ? ? ? ? if (f->chip_id == id) {
>>> + ? ? ? ? ? ? ? ? ? ? ? dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
>>> + ? ? ? ? ? ? ? ? ? ? ? pxa3xx_nand_config_flash(info, f);
>>> ? ? ? ? ? ? ? ? ? ? ? ?return 0;
>>> + ? ? ? ? ? ? ? }
>>> ? ? ? ?}
>>>
>>> ? ? ? ?dev_warn(&info->pdev->dev,
>>> - ? ? ? ? ? ? ? ?"failed to detect configured nand flash; found %04x instead of\n",
>>> + ? ? ? ? ? ? ? ? ? ? ? "failed to detect configured nand flash; found %04x instead of\n",
>>> ? ? ? ? ? ? ? ? id);
>>> +fail_detect:
>>> ? ? ? ?return -ENODEV;
>>> ?}
>>>
>>
>> I'm generally OK with the idea.
>>
> Best regards,
> Lei
>


From redhatter at gentoo.org  Thu Jun 17 23:57:45 2010
From: redhatter at gentoo.org (Stuart Longland)
Date: Fri, 18 Jun 2010 13:57:45 +1000
Subject: [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
Message-ID: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>

The TLV320AIC3204 is a low-power stereo audio CODEC capable of sample
rates of up to 192kHz.  This driver implements basic functionality,
using I?C for the control channel.

The audio interface supports many data bus formats, including I?S
master/slave, DSP, left/right justified and TDM.

What works:
	- Playback at various bitrates up to 96kHz
	- Recording at various bitrates up to 96kHz
	- Mixer interface
	- PLL generation of CODEC clocks from MCLK

What could work better:
	- DAPM

What isn't tested:
	- Audio interfaces other than I?S
	- PLL with clocks other than ~12MHz
	- Mono recording/playback
	- 192kHz recording/playback

What isn't implemented:
	- SPI interface support
	- PLL without fractional divider (would allow <10MHz clocks)
	- Clock sources other than MCLK
	- Adaptive filtering
	- AGC
	- Headset detection, JACK framework

Signed-off-by: Stuart Longland <redhatter at gentoo.org>
---
 include/sound/tlv320aic3204.h    |   64 +
 sound/soc/codecs/Kconfig         |    5 +
 sound/soc/codecs/Makefile        |    2 +
 sound/soc/codecs/tlv320aic3204.c | 4128 ++++++++++++++++++++++++++++++++++++++
 sound/soc/codecs/tlv320aic3204.h | 1415 +++++++++++++
 5 files changed, 5614 insertions(+), 0 deletions(-)
 create mode 100644 include/sound/tlv320aic3204.h
 create mode 100644 sound/soc/codecs/tlv320aic3204.c
 create mode 100644 sound/soc/codecs/tlv320aic3204.h

diff --git a/include/sound/tlv320aic3204.h b/include/sound/tlv320aic3204.h
new file mode 100644
index 0000000..491cd22
--- /dev/null
+++ b/include/sound/tlv320aic3204.h
@@ -0,0 +1,64 @@
+/*
+ * Platform data for Texas Instruments TLV320AIC3204 codec
+ *
+ * Copyright (C) 2010 Jacques Electronics Pty Ltd
+ * Author: Stuart Longland <redhatter at gentoo.org>
+ *
+ * Based on tlv320aic3x.h:
+ * Author: Jarkko Nikula <jhnikula at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __TLV320AIC3204_H__
+#define __TLV320AIC3204_H__
+
+/*
+ * Analogue Input Quick-Charge Power Up Delay
+ */
+enum {
+	/* Power up time: Default Value (whatever that is) */
+	AIC3204_PDATA_AIN_PWRUP_DEFAULT	= (0x00),
+	/* Power up time: 3.1ms */
+	AIC3204_PDATA_AIN_PWRUP_3M1S	= (0x31),
+	/* Power up time: 6.4ms */
+	AIC3204_PDATA_AIN_PWRUP_6M4S	= (0x32),
+	/* Power up time: 1.6ms */
+	AIC3204_PDATA_AIN_PWRUP_1M6S	= (0x33),
+};
+
+/*
+ * Analogue Reference Power Up Delay
+ */
+enum {
+	/* Reference Power-Up delay: Slow */
+	AIC3204_PDATA_REF_PWRUP_SLOW	= (0 << 0),
+	/* Reference Power-Up delay: 40ms */
+	AIC3204_PDATA_REF_PWRUP_40MS	= (1 << 0),
+	/* Reference Power-Up delay: 80ms */
+	AIC3204_PDATA_REF_PWRUP_80MS	= (2 << 0),
+	/* Reference Power-Up delay: 120ms */
+	AIC3204_PDATA_REF_PWRUP_120MS	= (3 << 0),
+};
+
+struct aic3204_pdata {
+	int gpio_reset; /* < 0 if not used */
+
+	/* Analogue-in Power up delay */
+	u8	ain_pwrup_delay;
+
+	/* Analogue Reference Power up delay */
+	u8	ref_pwrup_delay;
+
+	/* AVDD <->DVDD Link enable */
+	u8	avdd_link_en;
+
+	/* LDO Enable */
+	u8	ldo_en;
+
+	/* Oversampling rate (both ADC and DAC) */
+	u8	osr;
+};
+
+#endif
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index c37c844..80b56a4 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -32,6 +32,7 @@ config SND_SOC_ALL_CODECS
 	select SND_SOC_STAC9766 if SND_SOC_AC97_BUS
 	select SND_SOC_TLV320AIC23 if I2C
 	select SND_SOC_TLV320AIC26 if SPI_MASTER
+	select SND_SOC_TLV320AIC3204 if I2C
 	select SND_SOC_TLV320AIC3X if I2C
 	select SND_SOC_TPA6130A2 if I2C
 	select SND_SOC_TLV320DAC33 if I2C
@@ -164,6 +165,10 @@ config SND_SOC_TLV320AIC26
 	tristate "TI TLV320AIC26 Codec support" if SND_SOC_OF_SIMPLE
 	depends on SPI
 
+config SND_SOC_TLV320AIC3204
+	tristate
+	depends on I2C
+
 config SND_SOC_TLV320AIC3X
 	tristate
 
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 4a9c205..c649f14 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -20,6 +20,7 @@ snd-soc-ssm2602-objs := ssm2602.o
 snd-soc-stac9766-objs := stac9766.o
 snd-soc-tlv320aic23-objs := tlv320aic23.o
 snd-soc-tlv320aic26-objs := tlv320aic26.o
+snd-soc-tlv320aic3204-objs := tlv320aic3204.o
 snd-soc-tlv320aic3x-objs := tlv320aic3x.o
 snd-soc-tlv320dac33-objs := tlv320dac33.o
 snd-soc-twl4030-objs := twl4030.o
@@ -86,6 +87,7 @@ obj-$(CONFIG_SND_SOC_SSM2602)	+= snd-soc-ssm2602.o
 obj-$(CONFIG_SND_SOC_STAC9766)	+= snd-soc-stac9766.o
 obj-$(CONFIG_SND_SOC_TLV320AIC23)	+= snd-soc-tlv320aic23.o
 obj-$(CONFIG_SND_SOC_TLV320AIC26)	+= snd-soc-tlv320aic26.o
+obj-$(CONFIG_SND_SOC_TLV320AIC3204)	+= snd-soc-tlv320aic3204.o
 obj-$(CONFIG_SND_SOC_TLV320AIC3X)	+= snd-soc-tlv320aic3x.o
 obj-$(CONFIG_SND_SOC_TLV320DAC33)	+= snd-soc-tlv320dac33.o
 obj-$(CONFIG_SND_SOC_TWL4030)	+= snd-soc-twl4030.o
diff --git a/sound/soc/codecs/tlv320aic3204.c b/sound/soc/codecs/tlv320aic3204.c
new file mode 100644
index 0000000..a00f487
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic3204.c
@@ -0,0 +1,4128 @@
+/*
+ * ALSA SoC TLV320AIC3204 codec driver
+ *
+ * Author:	Stuart Longland, <redhatter at gentoo.org>
+ * Copyright:	(C) 2010 Jacques Electronics Pty. Ltd.
+ *
+ * Based upon the TLV320AIC3X driver:
+ * Author:      Vladimir Barinov, <vbarinov at embeddedalley.com>
+ * Copyright:   (C) 2007 MontaVista Software, Inc., <source at mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <sound/tlv320aic3204.h>
+
+#include "tlv320aic3204.h"
+
+/*
+ * Default settings; these will be used if no platform data is provided.
+ */
+const static struct aic3204_pdata aic3204_default_pdata = {
+	.gpio_reset 		= -1,
+	.ain_pwrup_delay	= AIC3204_PDATA_AIN_PWRUP_DEFAULT,
+	.ref_pwrup_delay	= AIC3204_PDATA_REF_PWRUP_SLOW,
+	.avdd_link_en		= 1,
+	.ldo_en			= 0,
+	.osr			= 128,
+};
+
+/*
+ * Default Register Values; this is used to initialise the register cache.
+ * There are 128 pages, of 128 registers each stored here.  The data was
+ * captured from a TLV320AIC3204 immediately after reset, and therefore should
+ * be representative of what's displayed in the datasheet.
+ */
+static const u8 aic3204_default_reg_data[128*128] = {
+	/* --- Page 0 --- */
+	0x00, 0x00, 0x50, 0x00, 0x00, 0x11, 0x04, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02,
+	0x00, 0x08, 0x01, 0x01, 0x80, 0x01, 0x00, 0x04,
+	0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x03, 0x02,
+	0x02, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x14,
+	0x0c, 0x00, 0x00, 0x00, 0x6f, 0x38, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0xee, 0x10, 0xd8, 0x7e, 0xe3,
+	0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 1 --- */
+	0x01, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
+	0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 2 --- */
+	0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 3 --- */
+	0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 4 --- */
+	0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 5 --- */
+	0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 6 --- */
+	0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 7 --- */
+	0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 8 --- */
+	0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x01, 0x17, 0x00, 0x00,
+	0x01, 0x17, 0x00, 0x00, 0x7d, 0xd3, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 9 --- */
+	0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+
+	/* --- Page 10 --- */
+	0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 11 --- */
+	0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 12 --- */
+	0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 13 --- */
+	0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 14 --- */
+	0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 15 --- */
+	0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 16 --- */
+	0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x01, 0x17, 0x00, 0x00,
+	0x01, 0x17, 0x00, 0x00, 0x7d, 0xd3, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 17 --- */
+	0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 18 --- */
+	0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 19 --- */
+	0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 20 --- */
+	0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 21 --- */
+	0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 22 --- */
+	0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 23 --- */
+	0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 24 --- */
+	0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 25 --- */
+	0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 26 --- */
+	0x1a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x01, 0x17, 0x00, 0x00,
+	0x01, 0x17, 0x00, 0x00, 0x7d, 0xd3, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 27 --- */
+	0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+
+	/* --- Page 28 --- */
+	0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 29 --- */
+	0x1d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 30 --- */
+	0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 31 --- */
+	0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 32 --- */
+	0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 33 --- */
+	0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 34 --- */
+	0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x01, 0x17, 0x00, 0x00,
+	0x01, 0x17, 0x00, 0x00, 0x7d, 0xd3, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 35 --- */
+	0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 36 --- */
+	0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 37 --- */
+	0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 38 --- */
+	0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 39 --- */
+	0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 40 --- */
+	0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 41 --- */
+	0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 42 --- */
+	0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 43 --- */
+	0x2b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 44 --- */
+	0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 45 --- */
+	0x2d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 46 --- */
+	0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xf7, 0x00, 0x00,
+	0x80, 0x09, 0x00, 0x00, 0x7f, 0xef, 0x00, 0x00,
+	0x00, 0x11, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00,
+	0x7f, 0xde, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 47 --- */
+	0x2f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 48 --- */
+	0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 49 --- */
+	0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 50 --- */
+	0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 51 --- */
+	0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 52 --- */
+	0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 53 --- */
+	0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 54 --- */
+	0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 55 --- */
+	0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 56 --- */
+	0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 57 --- */
+	0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 58 --- */
+	0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 59 --- */
+	0x3b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 60 --- */
+	0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 61 --- */
+	0x3d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 62 --- */
+	0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 63 --- */
+	0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 64 --- */
+	0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xf7, 0x00, 0x00,
+	0x80, 0x09, 0x00, 0x00, 0x7f, 0xef, 0x00, 0x00,
+	0x00, 0x11, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00,
+	0x7f, 0xde, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 65 --- */
+	0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 66 --- */
+	0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 67 --- */
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+
+	/* --- Page 68 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 69 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 70 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 71 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 72 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 73 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 74 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 75 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 76 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 77 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 78 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 79 --- */
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+
+	/* --- Page 80 --- */
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+
+	/* --- Page 81 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 82 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 83 --- */
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+
+	/* --- Page 84 --- */
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+
+	/* --- Page 85 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 86 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 87 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 88 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 89 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 90 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 91 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 92 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 93 --- */
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+
+	/* --- Page 94 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 95 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 96 --- */
+	0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 97 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 98 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 99 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 100 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 101 --- */
+	0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 102 --- */
+	0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 103 --- */
+	0x67, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 104 --- */
+	0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 105 --- */
+	0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 106 --- */
+	0x6a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 107 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 108 --- */
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+
+	/* --- Page 109 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 110 --- */
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+
+	/* --- Page 111 --- */
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+
+	/* --- Page 112 --- */
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+
+	/* --- Page 113 --- */
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+
+	/* --- Page 114 --- */
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+
+	/* --- Page 115 --- */
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+
+	/* --- Page 116 --- */
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+
+	/* --- Page 117 --- */
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+
+	/* --- Page 118 --- */
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+
+	/* --- Page 119 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 120 --- */
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+
+	/* --- Page 121 --- */
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+	/* --- Page 122 --- */
+	0x7a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 123 --- */
+	0x7b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 124 --- */
+	0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 125 --- */
+	0x7d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 126 --- */
+	0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 127 --- */
+	0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+#define AIC3204_NUM_SUPPLIES	4
+static const char *aic3204_supply_names[AIC3204_NUM_SUPPLIES] = {
+	"IOVDD",	/* I/O Voltage */
+	"DVDD",		/* Digital Core Voltage */
+	"AVDD",		/* Analog DAC Voltage */
+	"LDOin",	/* Supply for internal LDOs and output amplifiers */
+};
+
+/* codec private data */
+struct aic3204_priv {
+	struct snd_soc_codec codec;
+	struct regulator_bulk_data supplies[AIC3204_NUM_SUPPLIES];
+	unsigned int sysclk;
+	struct aic3204_pdata pdata;
+};
+
+/*
+ * Determine whether a register is readable.
+ */
+static int aic3204_reg_is_readable(unsigned int reg)
+{
+	u8 page = reg >> 7;
+	reg &= 0x7f;
+
+	/* Anything beyond page 70 is undefined */
+	if (page > 70)			return 0;
+	
+	/* Page 62..70 */
+	if (page >= 62) {
+		/* Register 0 is page select */
+		if (reg == 0)		return 1;
+		/* Registers 1..7 are reserved */
+		if (reg <= 7)		return 0;
+		/* Registers 8..127 are valid */
+		return 1;
+	}
+
+	/* Pages 53..62 are undefined */
+	if (page >= 53)			return 0;
+
+	/* Pages 45..52 */
+	if (page >= 45) {
+		/* Register 0 is page select */
+		if (reg == 0)		return 1;
+		/* Registers 1..7 are reserved */
+		if (reg <= 7)		return 0;
+		/* Registers 8..127 are valid */
+		return 1;
+	}
+
+	/* Page 44 --- XXX The datasheet may have some typos here! */
+	if (page == 44) {
+		/* 
+		 * Register 0 is page select
+		 * Register 1 enables adaptive filtering
+		 */
+		if (reg <= 1)		return 1;
+		/* Registers 2..7 are reserved */
+		if (reg <= 7)		return 0;
+		/* Registers 8..127 are valid */
+		return 1;
+	}
+
+	/* Pages 35..43 are undefined */
+	if (page >= 35)			return 0;
+
+	/* Pages 26..34 */
+	if (page >= 26) {
+		/* Register 0 is page select */
+		if (reg == 0)		return 1;
+		/* Registers 1..7 are reserved */
+		if (reg <= 7)		return 0;
+		/* Registers 8..127 are valid */
+		return 1;
+	}
+
+	/* Pages 17..25 are undefined */
+	if (page >= 17)			return 0;
+
+	/* Pages 9..16 */
+	if (page >= 9) {
+		if (reg == 0)		return 1;
+		if (reg <= 7)		return 0;
+		return 1;
+	}
+
+	/* Page 8 */
+	if (page == 8) {
+		if (reg <= 1)		return 1;
+		if (reg <= 7)		return 0;
+		return 1;
+	}
+
+	/* Page 2..7 are undefined */
+	if (page >= 2)			return 0;
+
+	/* Page 1 */
+	if (page == 1) {
+		if (reg <= 4)		return 1;
+		if (reg <= 8)		return 0;
+		if (reg <= 20) 		return 1;
+		if (reg == 21) 		return 0;
+		if (reg <= 25)		return 1;
+		if (reg <= 50)		return 0;
+		if (reg <= 52)		return 1;
+		if (reg == 53)		return 0;
+		if (reg <= 55)		return 1;
+		if (reg == 56)		return 0;
+		if (reg <= 63)		return 1;
+		if (reg <= 70)		return 0;
+		if (reg == 71)		return 1;
+		if (reg <= 122)		return 0;
+		if (reg == 123)		return 1;
+		return 0;
+	}
+
+	/* Page 0 */
+	if (reg == 0)			return 1;
+	if (reg <= 3)			return 0;
+	if (reg <= 8)			return 1;
+	if (reg <= 10) 			return 0;
+	if (reg <= 14)			return 1;
+	if (reg <= 17)			return 0;
+	if (reg <= 20)			return 1;
+	if (reg <= 24)			return 0;
+	if (reg <= 34)			return 1;
+	if (reg == 35)			return 0;
+	if (reg <= 38)			return 1;
+	if (reg <= 41)			return 0;
+	if (reg <= 49)			return 1;
+	if (reg <= 51)			return 0;
+	if (reg <= 56)			return 1;
+	if (reg <= 59)			return 0;
+	if (reg <= 61)			return 1;
+	if (reg == 62)			return 0;
+	if (reg <= 79)			return 1;
+	if (reg == 80)			return 0;
+	if (reg <= 109)			return 1;
+	return 0;
+}
+
+/*
+ * read aic3204 register cache
+ */
+static inline unsigned int aic3204_read_reg_cache(struct snd_soc_codec *codec,
+						unsigned int reg)
+{
+	u8 *cache = codec->reg_cache;
+	if (reg >= AIC3204_CACHEREGNUM)
+		return -EINVAL;
+
+	return cache[reg];
+}
+
+/*
+ * Pretty-print the value of a register
+ */
+static int aic3204_show_reg(struct snd_soc_codec* codec, char *buf,
+		int buf_sz, unsigned int reg)
+{
+	return snprintf(buf, buf_sz, "%02x",
+			aic3204_read_reg_cache(codec, reg));
+}
+
+/*
+ * write aic3204 register cache
+ */
+static inline void aic3204_write_reg_cache(struct snd_soc_codec *codec,
+					 u16 reg, u8 value)
+{
+	u8 *cache = codec->reg_cache;
+
+	if (reg >= AIC3204_CACHEREGNUM)
+		return;
+	cache[reg] = value;
+}
+
+/*
+ * write to the aic3204 register space
+ */
+static int aic3204_write(struct snd_soc_codec *codec, unsigned int reg,
+		       unsigned int value)
+{
+	/* data is
+	 *   D15..D8 aic3204 register offset
+	 *   D7...D0 register data
+	 */
+	u8 data[2];
+
+	/*
+	 * Register number; upper 8 bits indicate page
+	 */
+	if (reg && (aic3204_read_reg_cache(codec, AIC3204_PAGE_SELECT) 
+			!= (reg >> 7))) {
+		/* Select the required page */
+		data[0] = 0;
+		data[1] = reg >> 7;
+		if (codec->hw_write(codec->control_data, data, 2) != 2)
+			return -EIO;
+		aic3204_write_reg_cache(codec, AIC3204_PAGE_SELECT, reg >> 7);
+		dev_dbg(codec->dev, "%s: Page %d selected\n", 
+				__func__, reg >> 7);
+	}
+
+	data[0] = reg & 0x7f;
+	data[1] = value & 0xff;
+
+	if (codec->hw_write(codec->control_data, data, 2) != 2)
+		return -EIO;
+
+	dev_dbg(codec->dev, "%s: pg %d reg %d[%04x] <= %02x\n",
+			__func__, reg >> 7, reg & 0x7f, reg, value);
+	aic3204_write_reg_cache(codec, reg, value);
+	return 0;
+}
+
+/*
+ * read from the aic3204 register space
+ */
+static int aic3204_read(struct snd_soc_codec *codec, unsigned int reg,
+		      u8 *value)
+{
+	*value = reg & 0xff;
+
+	/*
+	 * Register number; upper 8 bits indicate page
+	 */
+	if (reg && (aic3204_read_reg_cache(codec, AIC3204_PAGE_SELECT) 
+			!= (reg >> 7)))
+		/* Select the required page */
+		aic3204_write(codec, AIC3204_PAGE_SELECT, (reg >> 7));
+
+	value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
+	dev_dbg(codec->dev, "%s: pg %d reg %d[%04x] => %02x\n",
+			__func__, reg >> 7, reg & 0x7f, reg, value[0]);
+	aic3204_write_reg_cache(codec, reg, *value);
+	return 0;
+}
+
+/*
+ * Check BCLK direction.  Returns >0 if the BCLK pin is an output, 0 if it's an
+ * input, or negative error.
+ */
+static inline int aic3204_check_bclk_is_output(
+		struct snd_soc_dapm_widget *source,
+		struct snd_soc_dapm_widget *sink)
+{
+	int reg = snd_soc_read(source->codec, AIC3204_AISR1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR1_BCLK;
+
+	return reg & AIC3204_AISR1_BCLK_OUT;
+}
+
+/*
+ * Check WCLK direction.  Returns >0 if the WCLK pin is an output, 0 if it's an
+ * input, or negative error.
+ */
+
+static inline int aic3204_check_wclk_is_output(
+		struct snd_soc_dapm_widget *source,
+		struct snd_soc_dapm_widget *sink)
+{
+	int reg = snd_soc_read(source->codec, AIC3204_AISR1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR1_WCLK;
+
+	return reg & AIC3204_AISR1_WCLK_OUT;
+}
+
+/*
+ * Check PLL source; called by the PLL input clock DAPM widgets.
+ * Returns 1 if the two given widgets are presently connected, 0 otherwise.
+ * Negative error number returned on error.
+ */
+static int aic3204_check_pll_clk_src(struct snd_soc_dapm_widget *source,
+		struct snd_soc_dapm_widget *sink)
+{
+	int reg = snd_soc_read(source->codec, AIC3204_CLK1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+
+	reg &= AIC3204_CLK1_PLLSRC;
+
+	if (reg == AIC3204_CLK1_PLLSRC_MCLK)
+		reg = (!strcmp(source->name, "MCLK"));
+	else if (reg == AIC3204_CLK1_PLLSRC_BCLK)
+		reg = (!strcmp(source->name, "BCLK"));
+	else if (reg == AIC3204_CLK1_PLLSRC_GPIO)
+		reg = (!strcmp(source->name, "GPIO"));
+	else if (reg == AIC3204_CLK1_PLLSRC_DIN)
+		reg = (!strcmp(source->name, "DIN"));
+	else
+		reg = 0;
+
+	if (reg)
+		dev_dbg(source->codec->dev, "%s: %s is connected to %s\n",
+				__func__, source->name, sink->name);
+	return reg;
+}
+
+/*
+ * Check CODEC source; called by the CODEC_CLKIN input clock DAPM widgets.
+ * Returns 1 if the two given widgets are presently connected, 0 otherwise.
+ * Negative error number returned on error.
+ */
+static int aic3204_check_codec_clk_src(struct snd_soc_dapm_widget *source,
+		struct snd_soc_dapm_widget *sink)
+{
+	int reg = snd_soc_read(source->codec, AIC3204_CLK1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+
+	reg &= AIC3204_CLK1_CODECCLK;
+
+	if (reg == AIC3204_CLK1_CODECCLK_MCLK)
+		reg = (!strcmp(source->name, "MCLK"));
+	else if (reg == AIC3204_CLK1_CODECCLK_BCLK)
+		reg = (!strcmp(source->name, "BCLK"));
+	else if (reg == AIC3204_CLK1_CODECCLK_GPIO)
+		reg = (!strcmp(source->name, "GPIO"));
+	else if (reg == AIC3204_CLK1_CODECCLK_PLL)
+		reg = (!strcmp(source->name, "PLL_CLK"));
+	else
+		reg = 0;
+
+	if (reg)
+		dev_dbg(source->codec->dev, "%s: %s is connected to %s\n",
+				__func__, source->name, sink->name);
+	return reg;
+}
+
+/*
+ * Check BCLK source; called by the BCLK input clock DAPM widgets.
+ * Returns 1 if the two given widgets are presently connected, 0 otherwise.
+ * Negative error number returned on error.
+ */
+static int aic3204_check_bclk_src(struct snd_soc_dapm_widget *source,
+		struct snd_soc_dapm_widget *sink)
+{
+	int reg = snd_soc_read(source->codec, AIC3204_AISR1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR1_BCLK;
+
+	if (reg == AIC3204_AISR1_BCLK_IN)
+		/* BCLK is externally generated */
+		return 0;
+
+	reg = snd_soc_read(source->codec, AIC3204_AISR3);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR3_BDIV;
+
+	if (reg == AIC3204_AISR3_BDIV_DAC)
+		reg = (!strcmp(source->name, "DAC_CLK"));
+	else if (reg == AIC3204_AISR3_BDIV_DAC_MOD)
+		reg = (!strcmp(source->name, "DAC_MOD_CLK"));
+	else if (reg == AIC3204_AISR3_BDIV_ADC)
+		reg = (!strcmp(source->name, "ADC_CLK"));
+	else if (reg == AIC3204_AISR3_BDIV_ADC_MOD)
+		reg = (!strcmp(source->name, "ADC_MOD_CLK"));
+	else
+		reg = 0;
+
+	if (reg)
+		dev_dbg(source->codec->dev, "%s: %s is connected to %s\n",
+				__func__, source->name, sink->name);
+	return reg;
+}
+
+/*
+ * Check WCLK source; called by the WCLK input clock DAPM widgets.
+ * Returns 1 if the two given widgets are presently connected, 0 otherwise.
+ * Negative error number returned on error.
+ */
+static int aic3204_check_wclk_src(struct snd_soc_dapm_widget *source,
+		struct snd_soc_dapm_widget *sink)
+{
+	int reg = snd_soc_read(source->codec, AIC3204_AISR1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR1_WCLK;
+
+	if (reg == AIC3204_AISR1_WCLK_IN)
+		/* WCLK is externally generated */
+		return 0;
+
+	reg = snd_soc_read(source->codec, AIC3204_AISR6);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR6_WCLKOUT;
+
+	if (reg == AIC3204_AISR6_WCLKOUT_DAC)
+		reg = (!strcmp(source->name, "DAC_FS"));
+	else if (reg == AIC3204_AISR6_WCLKOUT_ADC)
+		reg = (!strcmp(source->name, "ADC_FS"));
+	else
+		reg = 0;
+
+	if (reg)
+		dev_dbg(source->codec->dev, "%s: %s is connected to %s\n",
+				__func__, source->name, sink->name);
+
+	return reg;
+}
+
+/*
+ * Event handler for audio interface BCLK; checks the state of the ADCs and
+ * DACs and switches the audio interface to the presently active clock.
+ */
+static int aic3204_aif_bclk_event(struct snd_soc_dapm_widget *w,
+			 struct snd_kcontrol *kcontrol, int event) {
+	u8 adcs_up;
+	u8 dacs_up;
+	u8 bclk_src;
+	/* Determine the current source */
+	int reg = snd_soc_read(w->codec, AIC3204_AISR1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR1_BCLK;
+	if (reg == AIC3204_AISR1_BCLK_IN)
+		/* BCLK is an input, not our concirn */
+		return 0;
+	
+	reg = snd_soc_read(w->codec, AIC3204_AISR3);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	bclk_src = reg & AIC3204_AISR3_BDIV;
+
+	/* 
+	 * These registers are not manipulated by us, so we must read them from
+	 * the CODEC directly. 
+	 */
+	reg = aic3204_read(w->codec, AIC3204_ADCF, &adcs_up);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	adcs_up &= (AIC3204_ADCF_LEFT_UP | AIC3204_ADCF_RIGHT_UP);
+
+	reg = aic3204_read(w->codec, AIC3204_DACF1, &dacs_up);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	dacs_up &= (AIC3204_DACF1_LEFT_UP | AIC3204_DACF1_RIGHT_UP);
+
+	dev_dbg(w->codec->dev, "%s: BCLK source=0x%02x, event=%d, "
+			"dacf1=0x%02x, adcf=0x%02x\n", __func__, bclk_src,
+			event, dacs_up, adcs_up);
+
+	/* What are we set to now? */
+	if (bclk_src == AIC3204_AISR3_BDIV_DAC) {
+		/* Currently listening to DAC... check that it's up */
+		if (adcs_up && !dacs_up)
+			/* No, but the ADCs are up; switch to those */
+			bclk_src = AIC3204_AISR3_BDIV_ADC;
+	} else if (bclk_src == AIC3204_AISR3_BDIV_DAC_MOD) {
+		/* Currently listening to DAC... check that it's up */
+		if (adcs_up && !dacs_up)
+			/* No, but the ADCs are up; switch to those */
+			bclk_src = AIC3204_AISR3_BDIV_ADC_MOD;
+	} else if (bclk_src == AIC3204_AISR3_BDIV_ADC) {
+		/* Currently listening to ADC... check that it's up */
+		if (dacs_up && !adcs_up)
+			/* No, but the DACs are up; switch to those */
+			bclk_src = AIC3204_AISR3_BDIV_DAC;
+	} else if (bclk_src == AIC3204_AISR3_BDIV_ADC_MOD) {
+		/* Currently listening to ADC... check that it's up */
+		if (adcs_up && !dacs_up)
+			/* No, but the DACs are up; switch to those */
+			bclk_src = AIC3204_AISR3_BDIV_DAC_MOD;
+	}
+
+	dev_dbg(w->codec->dev, "%s: setting source 0x%02x\n",
+			__func__, bclk_src);
+
+	snd_soc_update_bits(w->codec, AIC3204_AISR3,
+			AIC3204_AISR3_BDIV, bclk_src);
+	return 0;
+}
+
+/*
+ * Event handler for audio interface WCLK; checks the state of the ADCs and
+ * DACs and switches the audio interface to the presently active clock.
+ */
+static int aic3204_aif_wclk_event(struct snd_soc_dapm_widget *w,
+			 struct snd_kcontrol *kcontrol, int event) {
+	u8 wclk_src;
+	u8 adcs_up;
+	u8 dacs_up;
+	/* Determine the current source */
+	int reg = snd_soc_read(w->codec, AIC3204_AISR1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR1_WCLK;
+
+	if (reg == AIC3204_AISR1_WCLK_IN)
+		/* WCLK is an input, not our concirn */
+		return 0;
+		
+	reg = snd_soc_read(w->codec, AIC3204_AISR6);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	wclk_src = reg & AIC3204_AISR6_WCLKOUT;
+
+	/* 
+	 * These registers are not manipulated by us, so we must read them from
+	 * the CODEC directly. 
+	 */
+	reg = aic3204_read(w->codec, AIC3204_ADCF, &adcs_up);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	adcs_up &= (AIC3204_ADCF_LEFT_UP | AIC3204_ADCF_RIGHT_UP);
+
+	reg = aic3204_read(w->codec, AIC3204_DACF1, &dacs_up);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	dacs_up &= (AIC3204_DACF1_LEFT_UP | AIC3204_DACF1_RIGHT_UP);
+
+	dev_dbg(w->codec->dev, "%s: WCLK source=0x%02x, event=%d, "
+			"dacf1=0x%02x, adcf=0x%02x\n", __func__, wclk_src,
+			event, dacs_up, adcs_up);
+
+	/* What are we set to now? */
+	if (wclk_src == AIC3204_AISR6_WCLKOUT_DAC) {
+		/* Currently listening to DAC... check that it's up */
+		if (adcs_up && !dacs_up)
+			/* No, but the ADCs are up; switch to those */
+			wclk_src = AIC3204_AISR6_WCLKOUT_ADC;
+	} else if (wclk_src == AIC3204_AISR6_WCLKOUT_ADC) {
+		/* Currently listening to ADC... check that it's up */
+		if (dacs_up && !adcs_up)
+			/* No, but the DACs are up; switch to those */
+			wclk_src = AIC3204_AISR6_WCLKOUT_DAC;
+	}
+
+	dev_dbg(w->codec->dev, "%s: setting source 0x%02x\n",
+			__func__, wclk_src);
+
+	snd_soc_update_bits(w->codec, AIC3204_AISR6,
+			AIC3204_AISR6_WCLKOUT, wclk_src);
+	return 0;
+}
+
+/* 
+ * For MICPGA inputs; inputs may either be disconnected, or connected via one
+ * of three resistances. 
+ */
+static const char *aic3204_micpga_input_mux[] = {
+	"not-connected", "10k", "20k", "40k"
+};
+
+static struct soc_enum aic3204_enum_in1l_lmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGAPROUTE,
+				6, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in2l_lmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGAPROUTE,
+				4, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in3l_lmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGAPROUTE,
+				2, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in1r_lmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGAPROUTE,
+				0, 4, aic3204_micpga_input_mux);
+
+static struct soc_enum aic3204_enum_cm1l_lmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGANROUTE,
+				6, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in2r_lmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGANROUTE,
+				4, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in3r_lmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGANROUTE,
+				2, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_cm2l_lmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGANROUTE,
+				0, 4, aic3204_micpga_input_mux);
+
+static struct soc_enum aic3204_enum_in1r_rmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGAPROUTE,
+				6, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in2r_rmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGAPROUTE,
+				4, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in3r_rmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGAPROUTE,
+				2, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in2l_rmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGAPROUTE,
+				0, 4, aic3204_micpga_input_mux);
+
+static struct soc_enum aic3204_enum_cm1r_rmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGANROUTE,
+				6, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in1l_rmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGANROUTE,
+				4, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in3l_rmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGANROUTE,
+				2, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_cm2r_rmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGANROUTE,
+				0, 4, aic3204_micpga_input_mux);
+
+/*
+ * MICBIAS Voltages; The exact voltage depends on the common mode voltage
+ * setting...
+ *
+ * 		CM=0.75V	CM=0.9V
+ * 	Low	1.04V		1.25V
+ * 	Medium	1.425V		1.7V
+ * 	High	2.075V		2.5V
+ * 	V+	Connects to power supply directly in both cases.
+ */
+static const char *aic3204_micbias_voltages[] = {
+	"Low", "Med", "High", "V+"
+};
+static struct soc_enum aic3204_enum_micbias_voltage =
+			SOC_ENUM_SINGLE(AIC3204_MICBIAS,
+				4, 4, aic3204_micbias_voltages);
+
+/*
+ * MICBIAS Voltage Source
+ */
+static const char *aic3204_micbias_srcs[] = {
+	"AVDD", "LDOIN"
+};
+static struct soc_enum aic3204_enum_micbias_src =
+			SOC_ENUM_SINGLE(AIC3204_MICBIAS,
+				3, 2, aic3204_micbias_srcs);
+
+/*
+ * Left DAC Data Source
+ */
+static const char *aic3204_ldac_srcs[] = {
+	"disabled", "left channel", "right channel", "mix"
+};
+static struct soc_enum aic3204_enum_ldac_src =
+			SOC_ENUM_SINGLE(AIC3204_DACS1,
+				4, 4, aic3204_ldac_srcs);
+
+/*
+ * Right DAC Data Source
+ */
+static const char *aic3204_rdac_srcs[] = {
+	"disabled", "right channel", "left channel", "mix"
+};
+static struct soc_enum aic3204_enum_rdac_src =
+			SOC_ENUM_SINGLE(AIC3204_DACS1,
+				2, 4, aic3204_rdac_srcs);
+
+/*
+ * DAC digital volumes. From -63.5 to +24 dB in 0.5 dB steps.
+ * Does not mute control.
+ */
+static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
+/* 
+ * ADC gain volumes. From -12dB to 20 dB in 0.5dB steps.
+ * Does not mute control.
+ */
+static DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0);
+#if 0
+/*
+ * ADC Fine gain volumes. From -0.4 to 0 dB in 0.1dB steps
+ * Does not mute control.
+ */
+static DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0);
+#endif
+/*
+ * Output driver stage volumes; -6dB through to +29dB in 1dB steps
+ * Does not mute control.
+ */
+static DECLARE_TLV_DB_SCALE(output_stage_tlv, -600, 100, 0);
+/* 
+ * MICPGA volumes; 0dB through to +47.5dB in 0.5dB steps.
+ * Does not mute control
+ */
+static DECLARE_TLV_DB_SCALE(micpga_tlv, 0, 50, 0);
+
+static const struct snd_kcontrol_new aic3204_snd_controls[] = {
+	/* Output */
+
+	/*
+	 * Note regarding SOC_DOUBLE_R_SX_TLV...
+	 *
+	 * This is a bit misleading; xshift refers to the bit one bit *past*
+	 * the most significant bit.  Or at least that's what it appears to be
+	 * doing the math.  Mask needs to select the last 6 bits; which is the
+	 * signed bitfield specifiying the gain in dB.
+	 */
+	SOC_DOUBLE_R_SX_TLV("Headphone Output Volume",
+			 AIC3204_HPLGAIN, AIC3204_HPRGAIN,
+			 6, -6, 29, output_stage_tlv),
+	SOC_DOUBLE_R("Headphone Output Playback Switch",
+		AIC3204_HPLGAIN, AIC3204_HPRGAIN,
+		AIC3204_HPLGAIN_MUTE_SHIFT, 0x01, 1),
+	SOC_DOUBLE_R_SX_TLV("Line Output Playback Volume",
+			 AIC3204_LOLGAIN, AIC3204_LORGAIN,
+			 6, -6, 29, output_stage_tlv),
+	SOC_DOUBLE_R("Line Output Playback Switch", AIC3204_LOLGAIN, 
+			AIC3204_LORGAIN, AIC3204_LOLGAIN_MUTE_SHIFT, 0x01, 1),
+	SOC_DOUBLE_R_SX_TLV("PCM Playback Volume",
+			 AIC3204_LDACVOL, AIC3204_RDACVOL,
+			 8, -127, 48, dac_tlv),
+	SOC_DOUBLE("PCM Playback Switch", AIC3204_DACS2, 
+			AIC3204_DACS2_LEFT_MUTE_SHIFT,
+			AIC3204_DACS2_RIGHT_MUTE_SHIFT, 0x01, 1),
+	SOC_DOUBLE_R_SX_TLV("Mixer Amplifier Volume",
+			 AIC3204_MALGAIN, AIC3204_MARGAIN,
+			 6, -6, 29, output_stage_tlv),
+
+	/* DAC Options */
+	SOC_ENUM("Left Playback Source", aic3204_enum_ldac_src),
+	SOC_ENUM("Right Playback Source", aic3204_enum_rdac_src),
+	SOC_SINGLE("Differential Output Switch", AIC3204_DACS2,
+			AIC3204_DACS2_RMOD_INV_SHIFT, 1, 0),
+
+	/* MICPGA Options */
+	SOC_DOUBLE_R_TLV("MICPGA Capture Volume",
+			 AIC3204_LMICPGAVOL, AIC3204_RMICPGAVOL,
+			 0, 95, 0, micpga_tlv),
+	SOC_DOUBLE_R("MICPGA Capture Switch", 
+			AIC3204_LMICPGAVOL, AIC3204_RMICPGAVOL, 7, 0x1, 1),
+
+	/* MICBIAS Options */
+	SOC_SINGLE("MICBIAS Enable", AIC3204_MICBIAS, 6, 0x1, 0),
+	SOC_ENUM("MICBIAS Level", aic3204_enum_micbias_voltage),
+	SOC_ENUM("MICBIAS Source", aic3204_enum_micbias_src),
+
+	/* ADC */
+	SOC_DOUBLE_R_SX_TLV("PCM Capture Volume",
+			 AIC3204_LADCVOL, AIC3204_RADCVOL,
+			 7, -24, 40, adc_tlv),
+	SOC_DOUBLE("PCM Capture Switch", AIC3204_ADCFINE, 7, 3, 0x01, 1),
+
+	/* Driver/Amplifier Selection -- DAPM should handle this! */
+	SOC_DOUBLE("HP Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_HPL_UP_SHIFT,
+			AIC3204_OUTDRV_HPR_UP_SHIFT, 0x1, 0),
+	SOC_DOUBLE("LO Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_LOL_UP_SHIFT,
+			AIC3204_OUTDRV_LOR_UP_SHIFT, 0x1, 0),
+	SOC_DOUBLE("MA Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_MAL_UP_SHIFT,
+			AIC3204_OUTDRV_MAR_UP_SHIFT, 0x1, 0),
+};
+
+/* Driver/Amplifier Selection */
+static const struct snd_kcontrol_new aic3204_hpl_switch =
+	SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_HPL_UP_SHIFT, 0x1, 0);
+static const struct snd_kcontrol_new aic3204_hpr_switch =
+	SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_HPR_UP_SHIFT, 0x1, 0);
+static const struct snd_kcontrol_new aic3204_lol_switch =
+	SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_LOL_UP_SHIFT, 0x1, 0);
+static const struct snd_kcontrol_new aic3204_lor_switch =
+	SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_LOR_UP_SHIFT, 0x1, 0);
+static const struct snd_kcontrol_new aic3204_mal_switch =
+	SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_MAL_UP_SHIFT, 0x1, 0);
+static const struct snd_kcontrol_new aic3204_mar_switch =
+	SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_MAR_UP_SHIFT, 0x1, 0);
+
+/* Line Output Left Driver Inputs */
+static const struct snd_kcontrol_new aic3204_lol_in_controls[] = {
+	SOC_DAPM_SINGLE("LOR Switch", AIC3204_LOLROUTE,
+			AIC3204_LOLROUTE_LOR_SHIFT, 1, 0),
+	SOC_DAPM_SINGLE("MAL Switch", AIC3204_LOLROUTE,
+			AIC3204_LOLROUTE_MAL_SHIFT, 1, 0),
+	SOC_DAPM_SINGLE("LDAC+ Switch", AIC3204_LOLROUTE,
+			AIC3204_LOLROUTE_LDACP_SHIFT, 1, 0),
+	SOC_DAPM_SINGLE("RDAC- Switch", AIC3204_LOLROUTE,
+			AIC3204_LOLROUTE_RDACN_SHIFT, 1, 0),
+};
+
+/* Line Output Right Driver Inputs */
+static const struct snd_kcontrol_new aic3204_lor_in_controls[] = {
+	SOC_DAPM_SINGLE("MAR Switch", AIC3204_LORROUTE,
+			AIC3204_LORROUTE_MAR_SHIFT, 1, 0),
+	SOC_DAPM_SINGLE("RDAC+ Switch", AIC3204_LORROUTE,
+			AIC3204_LORROUTE_RDACP_SHIFT, 1, 0),
+};
+
+/* Headphone Output Left Driver Inputs */
+static const struct snd_kcontrol_new aic3204_hpl_in_controls[] = {
+	SOC_DAPM_SINGLE("MAR Switch", AIC3204_HPLROUTE,
+			AIC3204_HPLROUTE_MAR_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("MAL Switch", AIC3204_HPLROUTE, 
+			AIC3204_HPLROUTE_MAL_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("IN1L Switch", AIC3204_HPLROUTE, 
+			AIC3204_HPLROUTE_IN1L_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("LDAC+ Switch", AIC3204_HPLROUTE, 
+			AIC3204_HPLROUTE_LDACP_SHIFT, 0x1, 0),
+};
+
+/* Headphone Output Right Driver Inputs */
+static const struct snd_kcontrol_new aic3204_hpr_in_controls[] = {
+	SOC_DAPM_SINGLE("HPL Switch", AIC3204_HPRROUTE,
+			AIC3204_HPRROUTE_HPL_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("MAR Switch", AIC3204_HPRROUTE,
+			AIC3204_HPRROUTE_MAR_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("IN1R Switch", AIC3204_HPRROUTE,
+			AIC3204_HPRROUTE_IN1R_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("RDAC+ Switch", AIC3204_HPRROUTE,
+			AIC3204_HPRROUTE_RDACP_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("LDAC- Switch", AIC3204_HPRROUTE,
+			AIC3204_HPRROUTE_LDACN_SHIFT, 0x1, 0),
+};
+
+static const struct snd_kcontrol_new aic3204_lmicpgap_in_controls[] = {
+	SOC_DAPM_ENUM("IN1L Switch", aic3204_enum_in1l_lmicpgap),
+	SOC_DAPM_ENUM("IN2L Switch", aic3204_enum_in2l_lmicpgap),
+	SOC_DAPM_ENUM("IN3L Switch", aic3204_enum_in3l_lmicpgap),
+	SOC_DAPM_ENUM("IN1R Switch", aic3204_enum_in1r_lmicpgap),
+};
+
+static const struct snd_kcontrol_new aic3204_lmicpgan_in_controls[] = {
+	SOC_DAPM_ENUM("CM1L Switch", aic3204_enum_cm1l_lmicpgan),
+	SOC_DAPM_ENUM("IN2R Switch", aic3204_enum_in2r_lmicpgan),
+	SOC_DAPM_ENUM("IN3R Switch", aic3204_enum_in3r_lmicpgan),
+	SOC_DAPM_ENUM("CM2L Switch", aic3204_enum_cm2l_lmicpgan),
+};
+
+static const struct snd_kcontrol_new aic3204_rmicpgap_in_controls[] = {
+	SOC_DAPM_ENUM("IN1R Switch", aic3204_enum_in1r_rmicpgap),
+	SOC_DAPM_ENUM("IN2R Switch", aic3204_enum_in2r_rmicpgap),
+	SOC_DAPM_ENUM("IN3R Switch", aic3204_enum_in3r_rmicpgap),
+	SOC_DAPM_ENUM("IN2L Switch", aic3204_enum_in2l_rmicpgap),
+};
+
+static const struct snd_kcontrol_new aic3204_rmicpgan_in_controls[] = {
+	SOC_DAPM_ENUM("CM1R Switch", aic3204_enum_cm1r_rmicpgan),
+	SOC_DAPM_ENUM("IN1L Switch", aic3204_enum_in1l_rmicpgan),
+	SOC_DAPM_ENUM("IN3L Switch", aic3204_enum_in3l_rmicpgan),
+	SOC_DAPM_ENUM("CM2R Switch", aic3204_enum_cm2r_rmicpgan),
+};
+
+static const struct snd_soc_dapm_widget aic3204_dapm_widgets[] = {
+	/* Driver/Amplifier Selection */
+	SND_SOC_DAPM_SWITCH("HPL Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_HPL_UP_SHIFT, 0,
+			&aic3204_hpl_switch),
+	SND_SOC_DAPM_SWITCH("HPR Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_HPR_UP_SHIFT, 0,
+			&aic3204_hpr_switch),
+	SND_SOC_DAPM_SWITCH("LOL Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_LOL_UP_SHIFT, 0,
+			&aic3204_lol_switch),
+	SND_SOC_DAPM_SWITCH("LOR Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_LOR_UP_SHIFT, 0,
+			&aic3204_lor_switch),
+	SND_SOC_DAPM_SWITCH("MAL Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_MAL_UP_SHIFT, 0,
+			&aic3204_mal_switch),
+	SND_SOC_DAPM_SWITCH("MAR Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_MAR_UP_SHIFT, 0,
+			&aic3204_mar_switch),
+
+	/* Line Output Driver Inputs */
+	SND_SOC_DAPM_MIXER("Left Line Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_lol_in_controls,
+			ARRAY_SIZE(aic3204_lol_in_controls)),
+	SND_SOC_DAPM_MIXER("Right Line Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_lor_in_controls,
+			ARRAY_SIZE(aic3204_lor_in_controls)),
+
+	/* Headphone Output Driver Inputs */
+	SND_SOC_DAPM_MIXER("Left Headphone Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_hpl_in_controls,
+			ARRAY_SIZE(aic3204_hpl_in_controls)),
+	SND_SOC_DAPM_MIXER("Right Headphone Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_hpr_in_controls,
+			ARRAY_SIZE(aic3204_hpr_in_controls)),
+
+	/* DACs, ADCs and audio interfaces */
+	SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC3204_DACS1,
+			AIC3204_DACS1_LDAC_UP_SHIFT, 0),
+	SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC3204_DACS1,
+			AIC3204_DACS1_RDAC_UP_SHIFT, 0),
+	SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC3204_ADCS,
+			AIC3204_ADCS_RADC_UP_SHIFT, 0),
+	SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC3204_ADCS,
+			AIC3204_ADCS_RADC_UP_SHIFT, 0),
+	SND_SOC_DAPM_AIF_IN("Left Data In", "Left Playback",
+			0, SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_AIF_IN("Right Data In", "Right Playback",
+			1, SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_AIF_OUT("Left Data Out", "Left Capture",
+			0, SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_AIF_OUT("Right Data Out", "Right Capture",
+			1, SND_SOC_NOPM, 0, 0),
+
+	/* System clock sources */
+	SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("BCLK", AIC3204_CLK12,
+			AIC3204_CLK12_BCLK_STATE_SHIFT, 0,
+			aic3204_aif_bclk_event,
+			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+	SND_SOC_DAPM_SUPPLY("WCLK", SND_SOC_NOPM, 0, 0,
+			aic3204_aif_wclk_event,
+			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+	SND_SOC_DAPM_SUPPLY("GPIO", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("DIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("PLL_CLK", AIC3204_CLK2,
+			AIC3204_CLK2_PLL_SHIFT, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("CODEC_CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("DAC_CLK", AIC3204_CLK6, 
+			AIC3204_CLK6_NDAC_STATE_SHIFT, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("DAC_MOD_CLK", AIC3204_CLK7,
+			AIC3204_CLK7_MDAC_STATE_SHIFT, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("ADC_CLK", AIC3204_CLK8,
+			AIC3204_CLK8_NADC_STATE_SHIFT, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK", AIC3204_CLK9,
+			AIC3204_CLK9_MADC_STATE_SHIFT, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("DAC_FS", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("ADC_FS", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+	/* MICPGA Input Sources */
+	SND_SOC_DAPM_MIXER("Left MICPGA+ Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_lmicpgap_in_controls,
+			ARRAY_SIZE(aic3204_lmicpgap_in_controls)),
+	SND_SOC_DAPM_MIXER("Left MICPGA- Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_lmicpgan_in_controls,
+			ARRAY_SIZE(aic3204_lmicpgan_in_controls)),
+	SND_SOC_DAPM_MIXER("Right MICPGA+ Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_rmicpgap_in_controls,
+			ARRAY_SIZE(aic3204_rmicpgap_in_controls)),
+	SND_SOC_DAPM_MIXER("Right MICPGA- Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_rmicpgan_in_controls,
+			ARRAY_SIZE(aic3204_rmicpgan_in_controls)),
+	SND_SOC_DAPM_PGA("Left MICPGA", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("Right MICPGA", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_MICBIAS("Mic Bias", AIC3204_MICBIAS, 6, 0),
+
+	/* Bypass PGAs */
+	SND_SOC_DAPM_PGA("IN1L Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("IN1R Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+	/* Input Pins */
+	SND_SOC_DAPM_INPUT("IN1L"),
+	SND_SOC_DAPM_INPUT("IN1R"),
+	SND_SOC_DAPM_INPUT("IN2L"),
+	SND_SOC_DAPM_INPUT("IN2R"),
+	SND_SOC_DAPM_INPUT("IN3L"),
+	SND_SOC_DAPM_INPUT("IN3R"),
+
+	/* Output Pins */
+	SND_SOC_DAPM_OUTPUT("LOL"),
+	SND_SOC_DAPM_OUTPUT("LOR"),
+	SND_SOC_DAPM_OUTPUT("HPL"),
+	SND_SOC_DAPM_OUTPUT("HPR"),
+
+	/* Common-mode pins */
+	SND_SOC_DAPM_VMID("CM1L"),
+	SND_SOC_DAPM_VMID("CM1R"),
+	SND_SOC_DAPM_VMID("CM2L"),
+	SND_SOC_DAPM_VMID("CM2R"),
+};
+
+static const struct snd_soc_dapm_route intercon[] = {
+	/* Clock Signals and routing */
+	{"PLL_CLK", NULL, "MCLK", aic3204_check_pll_clk_src},
+	{"PLL_CLK", NULL, "BCLK", aic3204_check_pll_clk_src},
+	{"PLL_CLK", NULL, "GPIO", aic3204_check_pll_clk_src},
+	{"PLL_CLK", NULL, "DIN", aic3204_check_pll_clk_src},
+	{"CODEC_CLKIN", NULL, "MCLK", aic3204_check_codec_clk_src},
+	{"CODEC_CLKIN", NULL, "BCLK", aic3204_check_codec_clk_src},
+	{"CODEC_CLKIN", NULL, "GPIO", aic3204_check_codec_clk_src},
+	{"CODEC_CLKIN", NULL, "PLL_CLK", aic3204_check_codec_clk_src},
+	{"DAC_CLK", NULL, "CODEC_CLKIN"},
+	{"DAC_MOD_CLK", NULL, "DAC_CLK"},
+	{"DAC_FS", NULL, "DAC_MOD_CLK"},
+	{"ADC_CLK", NULL, "CODEC_CLKIN"},
+	{"ADC_MOD_CLK", NULL, "ADC_CLK"},
+	{"ADC_FS", NULL, "ADC_MOD_CLK"},
+	{"BCLK", NULL, "DAC_CLK", aic3204_check_bclk_src},
+	{"BCLK", NULL, "DAC_MOD_CLK", aic3204_check_bclk_src},
+	{"BCLK", NULL, "ADC_CLK", aic3204_check_bclk_src},
+	{"BCLK", NULL, "ADC_MOD_CLK", aic3204_check_bclk_src},
+	{"WCLK", NULL, "DAC_FS", aic3204_check_wclk_src},
+	{"WCLK", NULL, "ADC_FS", aic3204_check_wclk_src},
+
+	/* Clock sinks */
+	{"Left DAC", NULL, "DAC_MOD_CLK"},
+	{"Right DAC", NULL, "DAC_MOD_CLK"},
+	{"Left ADC", NULL, "ADC_MOD_CLK"},
+	{"Right ADC", NULL, "ADC_MOD_CLK"},
+	{"Left Data Out", NULL, "BCLK", aic3204_check_bclk_is_output},
+	{"Right Data Out", NULL, "BCLK", aic3204_check_bclk_is_output},
+	{"Left Data Out", NULL, "WCLK", aic3204_check_wclk_is_output},
+	{"Right Data Out", NULL, "WCLK", aic3204_check_wclk_is_output},
+	{"Left Data In", NULL, "BCLK", aic3204_check_bclk_is_output},
+	{"Right Data In", NULL, "BCLK", aic3204_check_bclk_is_output},
+	{"Left Data In", NULL, "WCLK", aic3204_check_wclk_is_output},
+	{"Right Data In", NULL, "WCLK", aic3204_check_wclk_is_output},
+
+	/* Data Connections */
+	{"Left Data Out", NULL, "Left ADC"},
+	{"Right Data Out", NULL, "Right ADC"},
+	{"Left DAC", NULL, "Left Data In"},
+	{"Right DAC", NULL, "Right Data In"},
+
+	/* Line Output */
+	{"Left Line Output Mixer", "LOR Switch", "Right Line Output Mixer"},
+	{"Left Line Output Mixer", "MAL Switch", "Left MICPGA"},
+	{"Left Line Output Mixer", "LDAC+ Switch", "Left DAC"},
+	{"Left Line Output Mixer", "RDAC- Switch", "Right DAC"},
+	{"Right Line Output Mixer", "MAR Switch", "Right MICPGA"},
+	{"Right Line Output Mixer", "RDAC+ Switch", "Right DAC"},
+	{"LOL", "LOL Playback Switch", "Left Line Output Mixer"},
+	{"LOR", "LOR Playback Switch", "Right Line Output Mixer"},
+
+	/* Headphone Output */
+	{"Left Headphone Output Mixer", "MAR Switch", "Right MICPGA"},
+	{"Left Headphone Output Mixer", "MAL Switch", "Left MICPGA"},
+	{"Left Headphone Output Mixer", "IN1L Switch", "IN1L Bypass PGA"},
+	{"Left Headphone Output Mixer", "LDAC+ Switch", "Left DAC"},
+	{"Right Headphone Output Mixer", "HPL Switch", "Left Headphone Output Mixer"},
+	{"Right Headphone Output Mixer", "MAR Switch", "Right MICPGA"},
+	{"Right Headphone Output Mixer", "IN1R Switch", "IN1R Bypass PGA"},
+	{"Right Headphone Output Mixer", "RDAC+ Switch", "Right DAC"},
+	{"Right Headphone Output Mixer", "LDAC- Switch", "Left DAC"},
+	{"HPL", "HPL Playback Switch", "Left Headphone Output Mixer"},
+	{"HPR", "HPR Playback Switch", "Right Headphone Output Mixer"},
+
+	/* MICPGA Input */
+	{"Left MICPGA+ Output Mixer", "IN1L Switch", "IN1L"},
+	{"Left MICPGA+ Output Mixer", "IN2L Switch", "IN2L"},
+	{"Left MICPGA+ Output Mixer", "IN3L Switch", "IN3L"},
+	{"Left MICPGA+ Output Mixer", "IN1R Switch", "IN1R"},
+	{"Left MICPGA- Output Mixer", "CM1L Switch", "CM1L"},
+	{"Left MICPGA- Output Mixer", "IN2R Switch", "IN2R"},
+	{"Left MICPGA- Output Mixer", "IN3R Switch", "IN3R"},
+	{"Left MICPGA- Output Mixer", "CM2L Switch", "CM2L"},
+	{"Right MICPGA+ Output Mixer", "IN1R Switch", "IN1R"},
+	{"Right MICPGA+ Output Mixer", "IN2R Switch", "IN2R"},
+	{"Right MICPGA+ Output Mixer", "IN3R Switch", "IN3R"},
+	{"Right MICPGA+ Output Mixer", "IN2L Switch", "IN2L"},
+	{"Right MICPGA- Output Mixer", "CM1R Switch", "CM1R"},
+	{"Right MICPGA- Output Mixer", "IN1L Switch", "IN1L"},
+	{"Right MICPGA- Output Mixer", "IN3L Switch", "IN3L"},
+	{"Right MICPGA- Output Mixer", "CM2R Switch", "CM2R"},
+	{"Left MICPGA", "MAL Playback Switch", "Left MICPGA+ Output Mixer"},
+	{"Right MICPGA", "MAR Playback Switch", "Right MICPGA+ Output Mixer"},
+	{"Left MICPGA", "MAL Playback Switch", "Left MICPGA- Output Mixer"},
+	{"Right MICPGA", "MAR Playback Switch", "Right MICPGA- Output Mixer"},
+
+	/* ADC Input */
+	{"Left ADC", NULL, "Left MICPGA"},
+	{"Right ADC", NULL, "Right MICPGA"},
+};
+
+static int aic3204_add_widgets(struct snd_soc_codec *codec)
+{
+	snd_soc_dapm_new_controls(codec, aic3204_dapm_widgets,
+				  ARRAY_SIZE(aic3204_dapm_widgets));
+
+	/* set up audio path interconnects */
+	snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
+	return 0;
+}
+
+static int aic3204_hw_params(struct snd_pcm_substream *substream,
+			   struct snd_pcm_hw_params *params,
+			   struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_device *socdev = rtd->socdev;
+	struct snd_soc_codec *codec = socdev->card->codec;
+	struct aic3204_priv *aic3204 = snd_soc_codec_get_drvdata(codec);
+	int dac_clk = 0, bit_clk = 0;
+	int codec_clk = 0, bypass_pll = 0, last_clk = 0, last_error = 0;
+	u8 data = 0, ndac = 0, mdac = 0, pll_p = 1, pll_r = 1, pll_j = 1, bdiv = 1;
+	u16 pll_d = 0;
+
+	int this_clk = 0, this_error = 0;
+	unsigned int this_abs_error;
+	u8 j, this_ndac;
+	u16 d;
+
+	/* Determine the DAC clock and bit clock needed */
+	dac_clk = aic3204->pdata.osr * params_rate(params);
+	bit_clk = params_rate(params) * params_channels(params);
+
+	/* 
+	 * Select data word length.
+	 * Note that the number of bits per frame used
+	 * to determine BDIV is double the number of bits per sample, as there
+	 * are two samples per frame.
+	 */
+	switch (params_format(params)) {
+		case SNDRV_PCM_FORMAT_S16_LE:
+			pr_debug("%s: Sample format 16 bits\n", __func__);
+			bit_clk *= 16;
+			data = AIC3204_AISR1_WL_16BITS;
+			break;
+		case SNDRV_PCM_FORMAT_S20_3LE:
+			pr_debug("%s: Sample format 20 bits\n", __func__);
+			bit_clk *= 32;
+			data = AIC3204_AISR1_WL_20BITS;
+			break;
+		case SNDRV_PCM_FORMAT_S24_LE:
+			pr_debug("%s: Sample format 24 bits\n", __func__);
+			bit_clk *= 40;
+			data = AIC3204_AISR1_WL_24BITS;
+			break;
+		case SNDRV_PCM_FORMAT_S32_LE:
+			pr_debug("%s: Sample format 32 bits\n", __func__);
+			bit_clk *= 48;
+			data = AIC3204_AISR1_WL_32BITS;
+			break;
+	}
+	snd_soc_update_bits(codec, AIC3204_AISR1, AIC3204_AISR1_WL, data);
+
+	pr_debug("%s: DAC Clock = %d Hz, Bit clock = %d Hz\n", __func__,
+			dac_clk, bit_clk);
+
+	/* Try to find a value for div which allows us to bypass the PLL and
+	 * generate CODEC_CLK directly. */
+	for (this_ndac = 128; this_ndac >= 1; this_ndac--) {
+		this_clk = aic3204->sysclk / this_ndac;
+		
+		if (this_clk == dac_clk) {
+			pr_debug("%s: Scored exact match.  NDAC=%d; DAC_CLK=%d\n", 
+					__func__, this_ndac, this_clk);
+			bypass_pll = 1;
+			ndac =  this_ndac;
+			break;
+		}
+	}
+
+	if (bypass_pll) {
+		/* Select MCLK as CODEC_CLKIN */
+		aic3204_write(codec, AIC3204_CLK1, AIC3204_CLK1_CODECCLK_MCLK);
+		codec_clk = aic3204->sysclk;
+		goto setup_codec;
+	}
+
+	/*
+	 * Determine PLL Parameters... the input/output frequency ratio
+	 * of the PLL is given in the datasheet:
+	 *
+	 *   out   R * J * (D/10000)       J      D
+	 *   --- = ----------------- = R * - * -------
+	 *   in	          P                P    10000
+	 *
+	 * Limitations:
+	 * - R range: 1..4
+	 * - J range: 4..63
+	 * - D range: 0..9999
+	 * - P range: 1..8
+	 * - If D == 0;
+	 *   	512 kHz <= in / P <= 20 MHz
+	 *   else
+	 *   	10 MHz <= in / P <= 20 MHz
+	 *
+	 * We will try for 8* the target frequency; then use NDAC/NADC to divide
+	 * that down.  If we set P = 1, and R = 1; we simplify the solution.
+	 */
+	pll_p = 1;
+	pll_r = 1;
+	for (this_ndac = 1; this_ndac <= 128; this_ndac++) {
+		int ratio, init_ratio;
+
+		codec_clk = dac_clk * this_ndac;
+
+		/* Ensure maximum CODEC frequency is not exceeded */
+		if (codec_clk > 137000000) continue;
+		if ((this_ndac % 2) && (codec_clk > 110000000)) continue;
+
+		/* Initial Fixed-point ratio ... this will be slightly lower */
+		init_ratio = codec_clk / (aic3204->sysclk / 10000);
+
+		pr_debug("%s: NDAC = %d, PLL J.D * 10000 = %d\n", 
+				__func__, this_ndac, init_ratio);
+		if (init_ratio < 40000) continue;
+		if (init_ratio > 639999) continue;
+
+		for(ratio = init_ratio; (ratio < init_ratio + 10000) 
+				&& (ratio < 639999); ratio++) {
+			j = ratio / 10000;
+			d = ratio % 10000;
+
+			this_clk = aic3204->sysclk / 10000;
+			this_clk *= (10000 * j) + d;
+			this_error = this_clk - codec_clk;
+			this_abs_error = abs(this_error);
+
+			if (this_abs_error > 1000) continue;
+
+			pr_debug("%s: Fractional PLL search; "
+					"P=%d R=%d J=%d D=%04d => "
+					"(%d * %d) / 10000 => %d "
+					"(%d error) [NDAC=%d]\n",
+					__func__, pll_p, pll_r, j, d, aic3204->sysclk,
+					ratio, this_clk, this_error, this_ndac);
+			if (!last_clk || (this_abs_error < last_error)) {
+				last_clk = this_clk;
+				last_error = this_abs_error;
+				ndac = this_ndac;
+				pll_j = j;
+				pll_d = d;
+				/* Early finish for exact match */
+				if (! this_abs_error)
+					break;
+			}
+		}
+	}
+
+	/* If we still haven't found anything; bail out here! */
+	if (!last_clk) goto fail;
+
+	pr_debug("%s: Best Output: %d (%d Hz Error)\n",
+			__func__, last_clk, last_error);
+	pr_debug("%s: setting up PLL: P=%d R=%d J.D=%d.%04d\n",
+			__func__, pll_p, pll_r, pll_j, pll_d);
+
+	codec_clk = last_clk;
+
+	aic3204_write(codec, AIC3204_CLK4, (pll_d >> AIC3204_CLK4_PLL_D_VSHIFT) 
+			& AIC3204_CLK4_PLL_D); 		/* PLL D[14:8] */
+	aic3204_write(codec, AIC3204_CLK5, pll_d & AIC3204_CLK5_PLL_D);
+							/* PLL D[7:0] */
+	aic3204_write(codec, AIC3204_CLK3, pll_j & AIC3204_CLK3_PLL_J);
+							/* PLL J */
+	aic3204_write(codec, AIC3204_CLK2,	
+			(pll_r & AIC3204_CLK2_PLL_R)	/* PLL R */
+			| ((pll_p << AIC3204_CLK2_PLL_P_SHIFT) 
+				& AIC3204_CLK2_PLL_P)
+							/* PLL P */
+			| AIC3204_CLK2_PLL_ON);	/* PLL on */
+
+	/* Select PLL as CODEC_CLKIN */
+	aic3204_write(codec, AIC3204_CLK1, AIC3204_CLK1_CODECCLK_PLL);
+
+setup_codec:
+	pr_debug("%s: CODEC CLK = %d => DAC CLK = %d\n",
+		__func__, codec_clk, codec_clk / ndac);
+	/* Calculate BDIV and NDAC */
+	mdac = codec_clk / (ndac * dac_clk);
+	if (!mdac) mdac = 1;
+
+	bdiv = dac_clk / bit_clk;
+	if (!bdiv) bdiv = 1;
+
+	/* Set AOSR and DOSR */
+	aic3204_write(codec, AIC3204_DOSR1, 
+			(aic3204->pdata.osr >> AIC3204_DOSR1_MSB_VSHIFT) 
+			& AIC3204_DOSR1_MSB);			/* DOSR[9:8] */
+	aic3204_write(codec, AIC3204_DOSR2, aic3204->pdata.osr 
+			& AIC3204_DOSR2_LSB);			/* DOSR[7:0] */
+	aic3204_write(codec, AIC3204_AOSR, aic3204->pdata.osr);	/* AOSR */
+
+	pr_debug("%s: NDAC = %d\n", __func__, ndac);
+	/* Set NDAC to divider value */
+	aic3204_write(codec, AIC3204_CLK6, AIC3204_CLK6_NDAC_STATE_ON | ndac);
+	/* Set NADC to match NDAC */
+	aic3204_write(codec, AIC3204_CLK8, AIC3204_CLK8_NADC_STATE_ON | ndac);
+	/* Set MDAC and turn on */
+	aic3204_write(codec, AIC3204_CLK7, AIC3204_CLK7_MDAC_STATE_ON | mdac);
+	/* Use MDAC for MADC */
+	aic3204_write(codec, AIC3204_CLK9, AIC3204_CLK7_MDAC_STATE_ON | mdac);
+
+	/* Set BCLK and WCLK */
+	pr_debug("%s: Bit clock divider = %d\n", __func__, bdiv);
+	/* Turn on and set BCLK N divider */
+	aic3204_write(codec, AIC3204_CLK12, bdiv
+			| AIC3204_CLK12_BCLK_STATE_ON);
+
+	/* 
+	 * Set BCLK and WCLK sources...
+	 *
+	 * Despite DAPM; this is still needed, as DAPM doesn't yet set the
+	 * source at the right time.
+	 *
+	 * TODO: See if we can change the order of initialisation so this
+	 * selection is made after bringing up the ADCs/DACs.  Alternative:
+	 * see if we can find out ahead of time which one to use.
+	 */
+	snd_soc_update_bits(codec, AIC3204_AISR3, AIC3204_AISR3_BDIV,
+			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+				? AIC3204_AISR3_BDIV_DAC
+				: AIC3204_AISR3_BDIV_ADC);
+	snd_soc_update_bits(codec, AIC3204_AISR6, AIC3204_AISR6_WCLKOUT,
+			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+				? AIC3204_AISR6_WCLKOUT_DAC
+				: AIC3204_AISR6_WCLKOUT_ADC);
+	return 0;
+fail:
+	printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
+	return -EINVAL;
+}
+
+static int aic3204_mute(struct snd_soc_dai *dai, int mute)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	u8 dacs2;
+	
+	dacs2 = aic3204_read_reg_cache(codec, AIC3204_DACS2);
+
+	if (mute) {
+		dacs2 	|= (1 << AIC3204_DACS2_LEFT_MUTE_SHIFT)
+			| (1 << AIC3204_DACS2_RIGHT_MUTE_SHIFT);
+	} else {
+		dacs2 	&= ~((1 << AIC3204_DACS2_LEFT_MUTE_SHIFT)
+			| (1 << AIC3204_DACS2_RIGHT_MUTE_SHIFT));
+	}
+
+	aic3204_write(codec, AIC3204_DACS2, dacs2);	/* Unmute DAC */
+	return 0;
+}
+
+static int aic3204_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+				int clk_id, unsigned int freq, int dir)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	struct aic3204_priv *aic3204 = snd_soc_codec_get_drvdata(codec);
+
+	aic3204->sysclk = freq;
+	return 0;
+}
+
+static int aic3204_set_dai_fmt(struct snd_soc_dai *codec_dai,
+			     unsigned int fmt)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	u8 aisr1 = 0, aisr2 = 0, aisr3 = 0;
+
+	/* set master/slave audio interface */
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+		case SND_SOC_DAIFMT_CBM_CFM:
+			aisr1	|= AIC3204_AISR1_BCLK_OUT
+				| AIC3204_AISR1_WCLK_OUT;
+			break;
+		case SND_SOC_DAIFMT_CBM_CFS:
+			aisr1	|= AIC3204_AISR1_BCLK_OUT
+				| AIC3204_AISR1_WCLK_IN;
+			break;
+		case SND_SOC_DAIFMT_CBS_CFM:
+			aisr1	|= AIC3204_AISR1_BCLK_IN
+				| AIC3204_AISR1_WCLK_OUT;
+			break;
+		case SND_SOC_DAIFMT_CBS_CFS:
+			aisr1	|= AIC3204_AISR1_BCLK_IN
+				| AIC3204_AISR1_WCLK_IN;
+			break;
+		default:
+			printk(KERN_ERR "%s: Clock mode not supported "
+				"(fmt=0x%08x)\n", __func__, fmt);
+			return -EINVAL;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+		case SND_SOC_DAIFMT_I2S:
+			aisr1	|= AIC3204_AISR1_INT_I2S;
+			break;
+		case SND_SOC_DAIFMT_DSP_A:
+			aisr2 = 1;
+		case SND_SOC_DAIFMT_DSP_B:
+			aisr1	|= AIC3204_AISR1_INT_DSP;
+			break;
+		case SND_SOC_DAIFMT_RIGHT_J:
+			aisr1 |= AIC3204_AISR1_INT_RJF;
+			break;
+		case SND_SOC_DAIFMT_LEFT_J:
+			aisr1 |= AIC3204_AISR1_INT_LJF;
+			break;
+		default:
+			printk(KERN_ERR "%s: SSI mode not supported "
+				"(fmt=0x%08x)\n", __func__, fmt);
+			return -EINVAL;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+		case SND_SOC_DAIFMT_NB_NF:
+			aisr3	|= AIC3204_AISR3_BCLKPOL_NOR;
+			break;
+		case SND_SOC_DAIFMT_IB_NF:
+			aisr3	|= AIC3204_AISR3_BCLKPOL_INV;
+			break;
+		default:
+			printk(KERN_ERR "%s: Clock inversion mode not "
+				"supported (fmt=0x%08x)\n", __func__, fmt);
+			return -EINVAL;
+	}
+
+	/* set iface */
+	aic3204_write(codec, AIC3204_AISR1, aisr1);
+	aic3204_write(codec, AIC3204_AISR2, aisr2);
+	aic3204_write(codec, AIC3204_AISR3, aisr3);
+
+	return 0;
+}
+
+#define AIC3204_RATES	SNDRV_PCM_RATE_8000_96000
+#define AIC3204_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+			 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_ops aic3204_dai_ops = {
+	.hw_params	= aic3204_hw_params,
+	.digital_mute	= aic3204_mute,
+	.set_sysclk	= aic3204_set_dai_sysclk,
+	.set_fmt	= aic3204_set_dai_fmt,
+};
+
+struct snd_soc_dai aic3204_dai = {
+	.name = "tlv320aic3204",
+	.playback = {
+		.stream_name = "Playback",
+		.channels_min = 1,
+		.channels_max = 2,
+		.rates = AIC3204_RATES,
+		.formats = AIC3204_FORMATS,},
+	.capture = {
+		.stream_name = "Capture",
+		.channels_min = 1,
+		.channels_max = 2,
+		.rates = AIC3204_RATES,
+		.formats = AIC3204_FORMATS,},
+	.ops = &aic3204_dai_ops,
+};
+EXPORT_SYMBOL_GPL(aic3204_dai);
+
+static int aic3204_resume(struct platform_device *pdev)
+{
+	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+	struct snd_soc_codec *codec = socdev->card->codec;
+	int i;
+	u8 data[2];
+	u8 *cache = codec->reg_cache;
+
+	/* Sync reg_cache with the hardware */
+	for (i = 0; i < AIC3204_CACHEREGNUM; i++) {
+		data[0] = i;
+		data[1] = cache[i];
+		codec->hw_write(codec->control_data, data, 2);
+	}
+
+	return 0;
+}
+
+/*
+ * initialise the AIC3204 driver
+ * register the mixer and dsp interfaces with the kernel
+ */
+static int aic3204_init(struct snd_soc_codec *codec)
+{
+	mutex_init(&codec->mutex);
+	INIT_LIST_HEAD(&codec->dapm_widgets);
+	INIT_LIST_HEAD(&codec->dapm_paths);
+
+	codec->name = "tlv320aic3204";
+	codec->owner = THIS_MODULE;
+	codec->read = aic3204_read_reg_cache;
+	codec->write = aic3204_write;
+	codec->dai = &aic3204_dai;
+	codec->num_dai = 1;
+	codec->reg_cache_size = AIC3204_CACHEREGNUM;
+	codec->reg_cache = kmemdup(aic3204_default_reg_data,
+			AIC3204_CACHEREGNUM, GFP_KERNEL);
+	codec->readable_register = aic3204_reg_is_readable;
+	codec->display_register = aic3204_show_reg;
+	if (codec->reg_cache == NULL)
+		return -ENOMEM;
+
+	/* Reset the CODEC */
+	aic3204_write(codec, AIC3204_PAGE_SELECT, 0);
+	aic3204_write(codec, AIC3204_RESET, AIC3204_RESET_SOFT);
+
+	return 0;
+}
+
+static struct snd_soc_codec *aic3204_codec;
+
+static int aic3204_register(struct snd_soc_codec *codec)
+{
+	int ret;
+
+	ret = aic3204_init(codec);
+	if (ret < 0) {
+		dev_err(codec->dev, "Failed to initialise device\n");
+		return ret;
+	}
+
+	aic3204_codec = codec;
+
+	ret = snd_soc_register_codec(codec);
+	if (ret) {
+		dev_err(codec->dev, "Failed to register codec\n");
+		return ret;
+	}
+
+	ret = snd_soc_register_dai(&aic3204_dai);
+	if (ret) {
+		dev_err(codec->dev, "Failed to register dai\n");
+		snd_soc_unregister_codec(codec);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int aic3204_unregister(struct aic3204_priv *aic3204)
+{
+	snd_soc_unregister_dai(&aic3204_dai);
+	snd_soc_unregister_codec(&aic3204->codec);
+
+	if (aic3204->pdata.gpio_reset >= 0) {
+		gpio_set_value(aic3204->pdata.gpio_reset, 0);
+		gpio_free(aic3204->pdata.gpio_reset);
+	}
+	regulator_bulk_disable(ARRAY_SIZE(aic3204->supplies), aic3204->supplies);
+	regulator_bulk_free(ARRAY_SIZE(aic3204->supplies), aic3204->supplies);
+
+	kfree(aic3204);
+	aic3204_codec = NULL;
+
+	return 0;
+}
+
+static int aic3204_i2c_probe(struct i2c_client *i2c,
+			   const struct i2c_device_id *id)
+{
+	struct snd_soc_codec *codec;
+	struct aic3204_priv *aic3204;
+	struct aic3204_pdata *pdata = i2c->dev.platform_data;
+	int ret, i;
+
+	aic3204 = kzalloc(sizeof(struct aic3204_priv), GFP_KERNEL);
+	if (aic3204 == NULL) {
+		dev_err(&i2c->dev, "failed to create private data\n");
+		return -ENOMEM;
+	}
+
+	codec = &aic3204->codec;
+	codec->dev = &i2c->dev;
+	snd_soc_codec_set_drvdata(codec, aic3204);
+	codec->control_data = i2c;
+	codec->hw_write = (hw_write_t) i2c_master_send;
+
+	i2c_set_clientdata(i2c, aic3204);
+
+	dev_dbg(&i2c->dev, "%s: platform data at %p\n",
+			__func__, pdata);
+	if (pdata)
+		memcpy(&aic3204->pdata, pdata, sizeof(struct aic3204_pdata));
+	else
+		memcpy(&aic3204->pdata, &aic3204_default_pdata,
+				sizeof(struct aic3204_pdata));
+
+	if (aic3204->pdata.gpio_reset >= 0) {
+		ret = gpio_request(aic3204->pdata.gpio_reset,
+				"tlv320aic3204 reset");
+		if (ret != 0)
+			goto err_gpio;
+		gpio_direction_output(aic3204->pdata.gpio_reset, 0);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(aic3204->supplies); i++)
+		aic3204->supplies[i].supply = aic3204_supply_names[i];
+
+	ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3204->supplies),
+				 aic3204->supplies);
+	if (ret != 0) {
+		dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+		goto err_get;
+	}
+
+	ret = regulator_bulk_enable(ARRAY_SIZE(aic3204->supplies),
+				    aic3204->supplies);
+	if (ret != 0) {
+		dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
+		goto err_enable;
+	}
+
+	if (aic3204->pdata.gpio_reset >= 0) {
+		udelay(1);
+		gpio_set_value(aic3204->pdata.gpio_reset, 1);
+	}
+
+	return aic3204_register(codec);
+
+err_enable:
+	regulator_bulk_free(ARRAY_SIZE(aic3204->supplies), aic3204->supplies);
+err_get:
+	if (aic3204->pdata.gpio_reset >= 0)
+		gpio_free(aic3204->pdata.gpio_reset);
+err_gpio:
+	kfree(aic3204);
+	return ret;
+}
+
+static int aic3204_i2c_remove(struct i2c_client *client)
+{
+	struct aic3204_priv *aic3204 = i2c_get_clientdata(client);
+
+	return aic3204_unregister(aic3204);
+}
+
+static const struct i2c_device_id aic3204_i2c_id[] = {
+	{ "tlv320aic3204", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, aic3204_i2c_id);
+
+/* machine i2c codec control layer */
+static struct i2c_driver aic3204_i2c_driver = {
+	.driver = {
+		.name = "tlv320aic3204-i2c",
+		.owner = THIS_MODULE,
+	},
+	.probe	= aic3204_i2c_probe,
+	.remove = aic3204_i2c_remove,
+	.id_table = aic3204_i2c_id,
+};
+
+static inline void aic3204_i2c_init(void)
+{
+	int ret;
+
+	ret = i2c_add_driver(&aic3204_i2c_driver);
+	if (ret)
+		printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
+		       __func__, ret);
+}
+
+static inline void aic3204_i2c_exit(void)
+{
+	i2c_del_driver(&aic3204_i2c_driver);
+}
+
+static int aic3204_probe(struct platform_device *pdev)
+{
+	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+	struct aic3204_setup_data *setup;
+	struct snd_soc_codec *codec;
+	struct aic3204_priv *aic3204;
+	int ret = 0;
+
+	codec = aic3204_codec;
+	if (!codec) {
+		dev_err(&pdev->dev, "Codec not registered\n");
+		return -ENODEV;
+	}
+
+	socdev->card->codec = codec;
+	setup = socdev->codec_data;
+	aic3204 = snd_soc_codec_get_drvdata(codec);
+
+	dev_dbg(codec->dev, "%s: private data at %p\n",
+			__func__, aic3204);
+	/* Initialise the CODEC with the given settings */
+	/* Analogue Input Quick-Charge Power-Up delay */
+	ret = aic3204_write(codec, AIC3204_AIQC,
+			aic3204->pdata.ain_pwrup_delay);
+	if (ret) return ret;
+
+	/* Analogue Reference Power-Up delay */
+	aic3204_write(codec, AIC3204_REFPU,
+			aic3204->pdata.ref_pwrup_delay);
+	if (ret) return ret;
+
+	/* AVDD<->DVDD link */
+	snd_soc_update_bits(codec, AIC3204_POWER,
+			AIC3204_POWER_AVDD_DVDD_UNLINK,
+			aic3204->pdata.avdd_link_en ?
+			0 : AIC3204_POWER_AVDD_DVDD_UNLINK);
+
+	/* LDO enable, analogue blocks enable */
+	snd_soc_update_bits(codec, AIC3204_LDO,
+			AIC3204_LDO_ANALOG | AIC3204_LDO_AVDD_UP,
+			AIC3204_LDO_ANALOG_ENABLED |
+			(aic3204->pdata.ldo_en 
+			  ? AIC3204_LDO_AVDD_UP : 0));
+
+	/* register pcms */
+	ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
+	if (ret < 0) {
+		printk(KERN_ERR "aic3204: failed to create pcms\n");
+		goto pcm_err;
+	}
+
+	snd_soc_add_controls(codec, aic3204_snd_controls,
+			ARRAY_SIZE(aic3204_snd_controls));
+
+	aic3204_add_widgets(codec);
+
+	return ret;
+
+pcm_err:
+	kfree(codec->reg_cache);
+	return ret;
+}
+
+static int aic3204_remove(struct platform_device *pdev)
+{
+	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+	struct snd_soc_codec *codec = socdev->card->codec;
+
+	snd_soc_free_pcms(socdev);
+	snd_soc_dapm_free(socdev);
+
+	kfree(codec->reg_cache);
+
+	return 0;
+}
+
+struct snd_soc_codec_device soc_codec_dev_aic3204 = {
+	.probe = aic3204_probe,
+	.remove = aic3204_remove,
+	.resume = aic3204_resume,
+};
+EXPORT_SYMBOL_GPL(soc_codec_dev_aic3204);
+
+static int __init aic3204_modinit(void)
+{
+	aic3204_i2c_init();
+
+	return 0;
+}
+module_init(aic3204_modinit);
+
+static void __exit aic3204_exit(void)
+{
+	aic3204_i2c_exit();
+}
+module_exit(aic3204_exit);
+
+MODULE_DESCRIPTION("ASoC TLV320AIC3204 codec driver");
+MODULE_AUTHOR("Jacques Electronics Pty Ltd");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/tlv320aic3204.h b/sound/soc/codecs/tlv320aic3204.h
new file mode 100644
index 0000000..cb95a4e
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic3204.h
@@ -0,0 +1,1415 @@
+/*
+ * ALSA SoC TLV320AIC3204 codec driver
+ *
+ * Author:	Stuart Longland, <redhatter at gentoo.org>
+ * Copyright:	(C) 2010 Jacques Electronics, Pty, Ltd.
+ *
+ * Author:      Vladimir Barinov, <vbarinov at embeddedalley.com>
+ * Copyright:   (C) 2007 MontaVista Software, Inc., <source at mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _AIC3204_H
+#define _AIC3204_H
+
+/*
+ * The AIC3204's registers are divided into separate pages, the first page of
+ * every register is a "page select", which sets the current page being
+ * accessed.  For the purposes of simplicity; we shall consider all registers
+ * as being addressed by a 16-bit value, consisting of the page number as
+ * most-significant 9 bits, followed by the register number as given in the
+ * datasheet.
+ *
+ * The register access functions will look after page flipping from here.
+ */
+
+/* 
+ * AIC3204 register space; 128 registers each page, we pages 0..127.  It's not
+ * clear from the datasheet exactly how many pages are in use... and it's a
+ * sparse register map!  Ideally, I'd like to just cache the pages that are
+ * needed, but the ALSA framework doesn't allow this easily.
+ *
+ * It does look as if up to and including page 70 is needed.  For now, we will
+ * cache up to page 128 however; as this ensures we get *everything*.
+ */
+#define AIC3204_CACHEREGNUM		(128*128)
+
+/* Page select register */
+#define AIC3204_PAGE_SELECT		0
+
+/* Register Page/Number => Address Mapping Macro */
+#define AIC3204_PGREG(page,reg)		(((page) << 7) | ((reg) & 0x7f))
+
+/* Software reset register */
+#define AIC3204_RESET			AIC3204_PGREG(0, 1)
+/* Perform software reset */
+#define AIC3204_RESET_SOFT		1
+
+/* Clock Setting Register 1, Multiplexers */
+#define AIC3204_CLK1			AIC3204_PGREG(0, 4)
+/* PLL Range Select: Low Range */
+#define AIC3204_CLK1_PLLRANGE_LOW	(0 << 6)
+/* PLL Range Select: High Range */
+#define AIC3204_CLK1_PLLRANGE_HIGH	(1 << 6)
+/* PLL Range Select Mask */
+#define AIC3204_CLK1_PLLRANGE		(1 << 6)
+/* PLL Input Clock Select: MCLK */
+#define AIC3204_CLK1_PLLSRC_MCLK	(0 << 2)
+/* PLL Input Clock Select: BCLK */
+#define AIC3204_CLK1_PLLSRC_BCLK	(1 << 2)
+/* PLL Input Clock Select: GPIO */
+#define AIC3204_CLK1_PLLSRC_GPIO	(2 << 2)
+/* PLL Input Clock Select: Data In */
+#define AIC3204_CLK1_PLLSRC_DIN		(3 << 2)
+/* PLL Input Clock Select Mask */
+#define AIC3204_CLK1_PLLSRC		(3 << 2)
+/* CODEC Clock Source Select: MCLK */
+#define AIC3204_CLK1_CODECCLK_MCLK	(0)
+/* CODEC Clock Source Select: BCLK */
+#define AIC3204_CLK1_CODECCLK_BCLK	(1)
+/* CODEC Clock Source Select: GPIO */
+#define AIC3204_CLK1_CODECCLK_GPIO	(2)
+/* CODEC Clock Source Select: PLL */
+#define AIC3204_CLK1_CODECCLK_PLL	(3)
+/* CODEC Clock Source Select Mask */
+#define AIC3204_CLK1_CODECCLK		(3)
+
+/* Clock Setting Register 2, PLL P & R Values */
+#define AIC3204_CLK2			AIC3204_PGREG(0, 5)
+/* PLL State: Powered Down */
+#define AIC3204_CLK2_PLL_OFF		(0 << 7)
+/* PLL State: Powered Up */
+#define AIC3204_CLK2_PLL_ON		(1 << 7)
+/* PLL State Mask */
+#define AIC3204_CLK2_PLL		(1 << 7)
+/* PLL State bitfield location */
+#define AIC3204_CLK2_PLL_SHIFT		(7)
+/* PLL P Divider value bitfield location */
+#define AIC3204_CLK2_PLL_P_SHIFT	(4)
+/* PLL P Divider value bitfield mask */
+#define AIC3204_CLK2_PLL_P		(7 << 4)
+/* PLL R Divider value bitfield location */
+#define AIC3204_CLK2_PLL_R_SHIFT	(0)
+/* PLL R Divider value bitfield mask */
+#define AIC3204_CLK2_PLL_R		(0xf)
+
+/* Clock Setting Register 3, PLL J Values */
+#define AIC3204_CLK3			AIC3204_PGREG(0, 6)
+/* PLL J Divider value bitfield location */
+#define AIC3204_CLK3_PLL_J_SHIFT	(0)
+/* PLL J Divider value bitfield mask */
+#define AIC3204_CLK3_PLL_J		(0x3f)
+
+/* Clock Setting Register 4, PLL D MSB */
+#define AIC3204_CLK4			AIC3204_PGREG(0, 7)
+/* PLL D most significant portion bitfield location */
+#define AIC3204_CLK4_PLL_D_SHIFT	(0)
+/* PLL D most significant portion bitfield mask */
+#define AIC3204_CLK4_PLL_D		(0x3f)
+/* PLL D most significant portion value shift */
+#define AIC3204_CLK4_PLL_D_VSHIFT	(8)
+
+/* Clock Setting Register 5, PLL D LSB */
+#define AIC3204_CLK5			AIC3204_PGREG(0, 8)
+/* PLL D least significant portion bitfield location */
+#define AIC3204_CLK5_PLL_D_SHIFT	(0)
+/* PLL D least significant portion bitfield mask */
+#define AIC3204_CLK5_PLL_D		(0xff)
+/* PLL D least significant portion value shift */
+#define AIC3204_CLK5_PLL_D_VSHIFT	(0)
+
+/* Clock Setting Register 6, NDAC Values */
+#define AIC3204_CLK6			AIC3204_PGREG(0, 11)
+/* NDAC State: Powered Down */
+#define AIC3204_CLK6_NDAC_STATE_OFF	(0 << 7)
+/* NDAC State: Powered Up */
+#define AIC3204_CLK6_NDAC_STATE_ON	(1 << 7)
+/* NDAC State Mask */
+#define AIC3204_CLK6_NDAC_STATE		(1 << 7)
+/* NDAC State bitfield location */
+#define AIC3204_CLK6_NDAC_STATE_SHIFT	(7)
+/* NDAC value bitfield location */
+#define AIC3204_CLK6_NDAC_SHIFT		(0)
+/* NDAC value bitfield mask */
+#define AIC3204_CLK6_NDAC		(0x7f)
+
+/* Clock Setting Register 7, MDAC Values */
+#define AIC3204_CLK7			AIC3204_PGREG(0, 12)
+/* MDAC State: Powered Down */
+#define AIC3204_CLK7_MDAC_STATE_OFF	(0 << 7)
+/* MDAC State: Powered Up */
+#define AIC3204_CLK7_MDAC_STATE_ON	(1 << 7)
+/* MDAC State Mask */
+#define AIC3204_CLK7_MDAC_STATE		(1 << 7)
+/* MDAC State bitfield location */
+#define AIC3204_CLK7_MDAC_STATE_SHIFT	(7)
+/* MDAC value bitfield location */
+#define AIC3204_CLK7_MDAC_SHIFT		(0)
+/* MDAC value bitfield mask */
+#define AIC3204_CLK7_MDAC		(0x7f)
+
+/* DAC OSR Setting Register 1, MSB */
+#define AIC3204_DOSR1			AIC3204_PGREG(0, 13)
+/* DOSR most significant portion bitfield location */
+#define AIC3204_DOSR1_MSB_SHIFT		(0)
+/* DOSR most significant portion bitfield mask */
+#define AIC3204_DOSR1_MSB		(3)
+/* DOSR most significant portion value shift */
+#define AIC3204_DOSR1_MSB_VSHIFT	(8)
+
+/* DAC OSR Setting Register 2, LSB */
+#define AIC3204_DOSR2			AIC3204_PGREG(0, 14)
+/* DOSR least significant portion bitfield location */
+#define AIC3204_DOSR2_LSB_SHIFT		(0)
+/* DOSR least significant portion bitfield mask */
+#define AIC3204_DOSR2_LSB		(0xff)
+/* DOSR least significant portion value shift */
+#define AIC3204_DOSR2_LSB_VSHIFT	(0)
+
+/* Clock Setting Register 8, NADC Values */
+#define AIC3204_CLK8			AIC3204_PGREG(0, 18)
+/* NADC State: Powered Down */
+#define AIC3204_CLK8_NADC_STATE_OFF	(0 << 7)
+/* NADC State: Powered Up */
+#define AIC3204_CLK8_NADC_STATE_ON	(1 << 7)
+/* NADC State Mask */
+#define AIC3204_CLK8_NADC_STATE		(1 << 7)
+/* NADC State bitfield location */
+#define AIC3204_CLK8_NADC_STATE_SHIFT	(7)
+/* NADC value bitfield location */
+#define AIC3204_CLK8_NADC_SHIFT		(0)
+/* NADC value bitfield mask */
+#define AIC3204_CLK8_NADC		(0x7f)
+
+/* Clock Setting Register 9, MADC Values */
+#define AIC3204_CLK9			AIC3204_PGREG(0, 19)
+/* MADC State: Powered Down */
+#define AIC3204_CLK9_MADC_STATE_OFF	(0 << 7)
+/* MADC State: Powered Up */
+#define AIC3204_CLK9_MADC_STATE_ON	(1 << 7)
+/* MADC State Mask */
+#define AIC3204_CLK9_MADC_STATE		(1 << 7)
+/* MADC State bitfield location */
+#define AIC3204_CLK9_MADC_STATE_SHIFT	(7)
+/* MADC value bitfield location */
+#define AIC3204_CLK9_MADC_SHIFT		(0)
+/* MADC value bitfield mask */
+#define AIC3204_CLK9_MADC		(0x7f)
+
+/* ADC OSR Setting Register */
+#define AIC3204_AOSR			AIC3204_PGREG(0, 20)
+
+/* 
+ * Clock Register setting 10, Multiplexers
+ *
+ * XXX: Note that the datasheet goofs up here, calling this register 9, but we
+ * already had a register 9 just before AOSR.  Therefore, we will call this
+ * register 10, and will increment all following by one to correct TI's
+ * mistake.
+ */
+#define AIC3204_CLK10			AIC3204_PGREG(0, 25)
+/* CDIV Clock Source: MCLK */
+#define AIC3204_CLK10_CDIV_MCLK		(0)
+/* CDIV Clock Source: BCLK */
+#define AIC3204_CLK10_CDIV_BCLK		(1)
+/* CDIV Clock Source: Data IN */
+#define AIC3204_CLK10_CDIV_DIN		(2)
+/* CDIV Clock Source: PLL */
+#define AIC3204_CLK10_CDIV_PLL		(3)
+/* CDIV Clock Source: DAC */
+#define AIC3204_CLK10_CDIV_DAC		(4)
+/* CDIV Clock Source: DAC Modulation */
+#define AIC3204_CLK10_CDIV_DAC_MOD	(5)
+/* CDIV Clock Source: ADC */
+#define AIC3204_CLK10_CDIV_ADC		(6)
+/* CDIV Clock Source: ADC Modulation */
+#define AIC3204_CLK10_CDIV_ADC_MOD	(7)
+/* CDIV Clock Source Mask */
+#define AIC3204_CLK10_CDIV		(7)
+
+/* Clock Register setting 11, CLKOUT M divider value */
+#define AIC3204_CLK11			AIC3204_PGREG(0, 26)
+/* CLKOUT Divider State: Off */
+#define AIC3204_CLK11_CLKOUT_OFF	(0 << 7)
+/* CLKOUT Divider State: On */
+#define AIC3204_CLK11_CLKOUT_ON		(1 << 7)
+/* CLKOUT Divider State Mask */
+#define AIC3204_CLK11_CLKOUT		(1 << 7)
+/* CLKOUT Divider M value bitfield location */
+#define AIC3204_CLK11_CLKOUTM_SHIFT	(0)
+/* CLKOUT Divider M value bitfield mask */
+#define AIC3204_CLK11_CLKOUTM		(0x7f)
+
+/* Audio Interface Setting Register 1 */
+#define AIC3204_AISR1			AIC3204_PGREG(0, 27)
+/* Audio Interface Select: I2S */
+#define AIC3204_AISR1_INT_I2S		(0 << 6)
+/* Audio Interface Select: DSP */
+#define AIC3204_AISR1_INT_DSP		(1 << 6)
+/* Audio Interface Select: Right-Justified Format */
+#define AIC3204_AISR1_INT_RJF		(2 << 6)
+/* Audio Interface Select: Left-Justified Format */
+#define AIC3204_AISR1_INT_LJF		(3 << 6)
+/* Audio Interface Select Mask */
+#define AIC3204_AISR1_INT		(3 << 6)
+/* Audio Data Word Length: 16 bits */
+#define AIC3204_AISR1_WL_16BITS		(0 << 4)
+/* Audio Data Word Length: 20 bits */
+#define AIC3204_AISR1_WL_20BITS		(1 << 4)
+/* Audio Data Word Length: 24 bits */
+#define AIC3204_AISR1_WL_24BITS		(2 << 4)
+/* Audio Data Word Length: 32 bits */
+#define AIC3204_AISR1_WL_32BITS		(3 << 4)
+/* Audio Data Word Length Mask */
+#define AIC3204_AISR1_WL		(3 << 4)
+/* BCLK Direction Control: Input */
+#define AIC3204_AISR1_BCLK_IN		(0 << 3)
+/* BCLK Direction Control: Output */
+#define AIC3204_AISR1_BCLK_OUT		(1 << 3)
+/* BCLK Direction Control: Mask */
+#define AIC3204_AISR1_BCLK		(1 << 3)
+/* WCLK Direction Control: Input */
+#define AIC3204_AISR1_WCLK_IN		(0 << 2)
+/* WCLK Direction Control: Output */
+#define AIC3204_AISR1_WCLK_OUT		(1 << 2)
+/* WCLK Direction Control: Mask */
+#define AIC3204_AISR1_WCLK		(1 << 2)
+/* DOUT High Impedance Output Control: Never high impedance */
+#define AIC3204_AISR1_HIZ_NEVER		(0 << 0)
+/* DOUT High Impedance Output Control: High impedance when idle */
+#define AIC3204_AISR1_HIZ_IDLE		(1 << 0)
+/* DOUT High Impedance Output Control Mask */
+#define AIC3204_AISR1_HIZ		(1 << 0)
+
+/* Audio Interface Register 2, Data offset setting */
+#define AIC3204_AISR2			AIC3204_PGREG(0, 28)
+
+/* Audio Interface Register 3 */
+#define AIC3204_AISR3			AIC3204_PGREG(0, 29)
+/* Audio Data Loopback Control: Disabled */
+#define AIC3204_AISR3_ADLO_OFF		(0 << 5)
+/* Audio Data Loopback Control: Enabled */
+#define AIC3204_AISR3_ADLO_ON		(1 << 5)
+/* Audio Data Loopback Control Mask */
+#define AIC3204_AISR3_ADLO		(1 << 5)
+/* ADC->DAC Loopback Control: Disabled */
+#define AIC3204_AISR3_ADDALO_OFF	(0 << 4)
+/* ADC->DAC Loopback Control: Enabled */
+#define AIC3204_AISR3_ADDALO_ON		(1 << 4)
+/* ADC->DAC Loopback Control Mask */
+#define AIC3204_AISR3_ADDALO		(1 << 4)
+/* Audio Bit Clock Polarity: Normal */
+#define AIC3204_AISR3_BCLKPOL_NOR	(0 << 3)
+/* Audio Bit Clock Polarity: Inverted */
+#define AIC3204_AISR3_BCLKPOL_INV	(1 << 3)
+/* Audio Bit Clock Polarity Mask */
+#define AIC3204_AISR3_BCLKPOL		(1 << 3)
+/* Audio Data Interface Clock Buffers: Always powered */
+#define AIC3204_AISR3_ADICLK_ALWAYS	(0 << 2)
+/* Audio Data Interface Clock Buffers: Powered with CODEC only */
+#define AIC3204_AISR3_ADICLK_CODEC	(1 << 2)
+/* Audio Data Interface Clock Buffers' State */
+#define AIC3204_AISR3_ADICLK		(1 << 2)
+/* Audio Bit Clock Divider Source: DAC */
+#define AIC3204_AISR3_BDIV_DAC		(0 << 0)
+/* Audio Bit Clock Divider Source: DAC Modulation */
+#define AIC3204_AISR3_BDIV_DAC_MOD	(1 << 0)
+/* Audio Bit Clock Divider Source: ADC */
+#define AIC3204_AISR3_BDIV_ADC		(2 << 0)
+/* Audio Bit Clock Divider Source: ADC Modulation */
+#define AIC3204_AISR3_BDIV_ADC_MOD	(3 << 0)
+/* Audio Bit Clock Divider Source Mask */
+#define AIC3204_AISR3_BDIV		(3 << 0)
+
+/* Clock Setting Register 12, BCLK N Divider */
+#define AIC3204_CLK12			AIC3204_PGREG(0, 30)
+/* BCLK N State: Powered Down */
+#define AIC3204_PG0_CLK12_BCLK_STATE_OFF (0 << 7)
+/* BCLK N State: Powered Up */
+#define AIC3204_CLK12_BCLK_STATE_ON	(1 << 7)
+/* BCLK N State Mask */
+#define AIC3204_CLK12_BCLK_STATE	(1 << 7)
+/* BCLK N State bitfield location */
+#define AIC3204_CLK12_BCLK_STATE_SHIFT	(7)
+/* BCLK N value bitfield location */
+#define AIC3204_CLK12_BCLK_SHIFT	(0)
+/* BCLK N value bitfield mask */
+#define AIC3204_CLK12_BCLK		(0x7f)
+
+/* Audio Interface Setting Register 4, Secondary Audio Interface */
+#define AIC3204_AISR4			AIC3204_PGREG(0, 31)
+/* Secondary Bit Clock: GPIO */
+#define AIC3204_AISR4_SECBCLK_GPIO	(0 << 5)
+/* Secondary Bit Clock: SCLK */
+#define AIC3204_AISR4_SECBCLK_SCLK	(1 << 5)
+/* Secondary Bit Clock: MISO */
+#define AIC3204_AISR4_SECBCLK_MISO	(2 << 5)
+/* Secondary Bit Clock: DOUT */
+#define AIC3204_AISR4_SECBCLK_DOUT	(3 << 5)
+/* Secondary Bit Clock Mask */
+#define AIC3204_AISR4_SECBCLK		(3 << 5)
+/* Secondary Word Clock: GPIO */
+#define AIC3204_AISR4_SECWCLK_GPIO	(0 << 3)
+/* Secondary Word Clock: SCLK */
+#define AIC3204_AISR4_SECWCLK_SCLK	(1 << 3)
+/* Secondary Word Clock: MISO */
+#define AIC3204_AISR4_SECWCLK_MISO	(2 << 3)
+/* Secondary Word Clock: DOUT */
+#define AIC3204_AISR4_SECWCLK_DOUT	(3 << 3)
+/* Secondary Word Clock Mask */
+#define AIC3204_AISR4_SECWCLK		(3 << 3)
+/* ADC Word Clock: GPIO */
+#define AIC3204_AISR4_ADCWCLK_GPIO	(0 << 3)
+/* ADC Word Clock: SCLK */
+#define AIC3204_AISR4_ADCWCLK_SCLK	(1 << 3)
+/* ADC Word Clock: MISO */
+#define AIC3204_AISR4_ADCWCLK_MISO	(2 << 3)
+/* ADC Word Clock Mask */
+#define AIC3204_AISR4_ADCWCLK		(3 << 3)
+/* Secondary Data Input: GPIO */
+#define AIC3204_AISR4_SECDIN_GPIO	(0 << 0)
+/* Secondary Data Input: SCLK */
+#define AIC3204_AISR4_SECDIN_SCLK	(1 << 0)
+/* Secondary Data Input Mask */
+#define AIC3204_AISR4_SECDIN		(1 << 0)
+
+/* Audio Interface Setting Register 5 */
+#define AIC3204_AISR5			AIC3204_PGREG(0, 32)
+/* Audio Interface Bit Clock: Primary (BCLK) */
+#define AIC3204_AISR5_BCLKIN_PRI	(0 << 3)
+/* Audio Interface Bit Clock: Secondary */
+#define AIC3204_AISR5_BCLKIN_SEC	(1 << 3)
+/* Audio Interface Bit Clock Mask */
+#define AIC3204_AISR5_WCLKIN		(1 << 2)
+/* Audio Interface Word Clock: Primary (BCLK) */
+#define AIC3204_AISR5_WCLKIN_PRI	(0 << 2)
+/* Audio Interface Word Clock: Secondary */
+#define AIC3204_AISR5_WCLKIN_SEC	(1 << 2)
+/* Audio Interface Word Clock Mask */
+#define AIC3204_AISR5_WCLKIN		(1 << 2)
+/* ADC Word Clock Control: ADC WCLK = DAC WCLK */
+#define ADC3204_PG0_AISR5_ADCWCLK_DAC	(0 << 1)
+/* ADC Word Clock Control: ADC WCLK = Secondary ADC WCLK */
+#define ADC3204_PG0_AISR5_ADCWCLK_SEC	(1 << 1)
+/* ADC Word Clock Control Mask */
+#define ADC3204_PG0_AISR5_ADCWCLK	(1 << 1)
+/* Audio Data In: Primary Data In */
+#define ADC3204_PG0_AISR5_DIN_PRI	(0 << 0)
+/* Audio Data In: Secondary Data In */
+#define ADC3204_PG0_AISR5_DIN_SEC	(1 << 0)
+/* Audio Data In Mask */
+#define ADC3204_PG0_AISR5_DIN		(1 << 0)
+
+/* Audio Interface Setting Register 6 */
+#define AIC3204_AISR6			AIC3204_PGREG(0, 33)
+/* BCLK Output Control: Generated Primary Bit Clock */
+#define AIC3204_AISR6_BCLKOUT_GEN	(0 << 7)
+/* BCLK Output Control: Secondary Bit Clock */
+#define AIC3204_AISR6_BCLKOUT_SEC	(1 << 7)
+/* BCLK Output Control Mask */
+#define AIC3204_AISR6_BCLKOUT		(1 << 7)
+/* Secondary BCLK Output Control: Primary Bit Clock Input */
+#define AIC3204_AISR6_SBCLKOUT_BCLK	(0 << 6)
+/* Secondary BCLK Output Control: Generated Primary Bit Clock */
+#define AIC3204_AISR6_SBCLKOUT_GEN	(1 << 6)
+/* Secondary BCLK Output Control Mask */
+#define AIC3204_AISR6_SBCLKOUT		(1 << 6)
+/* WCLK Output Control: Generated DAC_FS */
+#define AIC3204_AISR6_WCLKOUT_DAC	(0 << 4)
+/* WCLK Output Control: Generated ADC_FS */
+#define AIC3204_AISR6_WCLKOUT_ADC	(1 << 4)
+/* WCLK Output Control: Secondary WCLK Input */
+#define AIC3204_AISR6_WCLKOUT_SWCLK	(2 << 4)
+/* WCLK Output Control Mask */
+#define AIC3204_AISR6_WCLKOUT		(3 << 4)
+/* Secondary WCLK Output Control: WCLK Input */
+#define AIC3204_AISR6_SWCLKOUT_WCLK	(0 << 2)
+/* Secondary WCLK Output Control: Generated DAC_FS */
+#define AIC3204_AISR6_SWCLKOUT_DAC	(1 << 2)
+/* Secondary WCLK Output Control: Generated ADC_FS */
+#define AIC3204_AISR6_SWCLKOUT_ADC	(2 << 2)
+/* Secondary WCLK Output Control Mask */
+#define AIC3204_AISR6_SWCLKOUT		(3 << 2)
+/* Primary Data Output Control: Serial Interface */
+#define AIC3204_AISR6_DOUT_INT		(0 << 1)
+/* Primary Data Output Control: Secondary Data Input */
+#define AIC3204_AISR6_DOUT_SDIN		(1 << 1)
+/* Primary Data Output Control Mask */
+#define AIC3204_AISR6_DOUT		(1 << 1)
+/* Secondary Data Output Control: Primary Data In */
+#define AIC3204_AISR6_SDOUT_DIN		(0 << 0)
+/* Secondary Data Output Control: Serial Interface */
+#define AIC3204_AISR6_SDOUT_INT		(1 << 0)
+/* Secondary Data Output Control Mask */
+#define AIC3204_AISR6_SDOUT		(1 << 0)
+
+/* Digital Interface Misc. Setting Register */
+#define AIC3204_DIMISC			AIC3204_PGREG(0, 34)
+/* I2C General Call Address Configuration: Ignore */
+#define AIC3204_DIMISC_I2CGC_IGNORE	(0 << 5)
+/* I2C General Call Address Configuration: Accept */
+#define AIC3204_DIMISC_I2CGC_ACCEPT	(1 << 5)
+
+/* ADC Flag Register */
+#define AIC3204_ADCF			AIC3204_PGREG(0, 36)
+/* Left ADC PGA Status: Gain is set */
+#define AIC3204_ADCF_LEFT_PGASET	(1 << 7)
+/* Left ADC Power Status: Powered Up */
+#define AIC3204_ADCF_LEFT_UP		(1 << 6)
+/* Left ADC AGC Status: Gain is saturated */
+#define AIC3204_ADCF_LEFT_AGCSAT	(1 << 5)
+/* Right ADC PGA Status: Gain is set */
+#define AIC3204_ADCF_RIGHT_PGASET	(1 << 3)
+/* Right ADC Power Status: Powered Up */
+#define AIC3204_ADCF_RIGHT_UP		(1 << 2)
+/* Right ADC AGC Status: Gain is saturated */
+#define AIC3204_ADCF_RIGHT_AGCSAT	(1 << 1)
+
+/* DAC Flag Register 1 */
+#define AIC3204_DACF1			AIC3204_PGREG(0, 37)
+/* Left DAC powered up */
+#define AIC3204_DACF1_LEFT_UP		(1 << 7)
+/* Left Line Output Driver powered up */
+#define AIC3204_DACF1_LOL_UP		(1 << 6)
+/* Left Headphone Output Driver powered up */
+#define AIC3204_DACF1_HPL_UP		(1 << 5)
+/* Right DAC powered up */
+#define AIC3204_DACF1_RIGHT_UP		(1 << 7)
+/* Right Line Output Driver powered up */
+#define AIC3204_DACF1_LOR_UP		(1 << 6)
+/* Right Headphone Output Driver powered up */
+#define AIC3204_DACF1_HPR_UP		(1 << 5)
+
+/* DAC Flag Register 2 */
+#define AIC3204_DACF2			AIC3204_PGREG(0, 38)
+/* Left DAC PGA Status: Gain is set */
+#define AIC3204_DACF2_LEFT_PGASET	(1 << 4)
+/* Right DAC PGA Status: Gain is set */
+#define AIC3204_DACF2_RIGHT_PGASET	(1 << 0)
+
+/* Sticky Flag Register 1 */
+#define AIC3204_STICK1			AIC3204_PGREG(0, 42)
+/* Left DAC Overflow */
+#define AIC3204_STICK1_LDAC_OVER	(1 << 7)
+/* Right DAC Overflow */
+#define AIC3204_STICK1_RDAC_OVER	(1 << 6)
+/* Left ADC Overflow */
+#define AIC3204_STICK1_LADC_OVER	(1 << 3)
+/* Right ADC Overflow */
+#define AIC3204_STICK1_RADC_OVER	(1 << 2)
+
+/* Interrupt Flag Register 1 */
+#define AIC3204_INTF1			AIC3204_PGREG(0, 43)
+/* Left DAC Overflow */
+#define AIC3204_INTF1_LDAC_OVER		(1 << 7)
+/* Right DAC Overflow */
+#define AIC3204_INTF1_RDAC_OVER		(1 << 6)
+/* Left ADC Overflow */
+#define AIC3204_INTF1_LADC_OVER		(1 << 3)
+/* Right ADC Overflow */
+#define AIC3204_INTF1_RADC_OVER		(1 << 2)
+
+/* Sticky Flag Register 2 */
+#define AIC3204_STICK2			AIC3204_PGREG(0, 44)
+/* Left Headphone Driver Over Current */
+#define AIC3204_STICK2_HPL_OVER		(1 << 7)
+/* Right Headphone Driver Over Current */
+#define AIC3204_STICK2_HPR_OVER		(1 << 6)
+/* Headset button pressed */
+#define AIC3204_STICK2_HS_BUTTON	(1 << 5)
+/* Headset plug inserted/removed */
+#define AIC3204_STICK2_HS_PLUGGED	(1 << 4)
+/* Left Channel DRC: Over threshold */
+#define AIC3204_STICK2_LDRC_OVER	(1 << 3)
+/* Right Channel DRC: Over threshold */
+#define AIC3204_STICK2_RDRC_OVER	(1 << 2)
+
+/* Sticky Flag Register 3 */
+#define AIC3204_STICK3			AIC3204_PGREG(0, 45)
+/* Left AGC Noise Threshold Flag: Over threshold */
+#define AIC3204_STICK3_LAGC_OVER	(1 << 6)
+/* Right AGC Noise Threshold Flag: Over threshold */
+#define AIC3204_STICK3_RAGC_OVER	(1 << 5)
+/* Left ADC DC Measurement Available */
+#define AIC3204_STICK3_LADC_DC		(1 << 2)
+/* Right ADC DC Measurement Available */
+#define AIC3204_STICK3_RADC_DC		(1 << 1)
+
+/* Interrupt Flag Register 2 */
+#define AIC3204_INTF2			AIC3204_PGREG(0, 46)
+/* Left Headphone Driver Over Current */
+#define AIC3204_INTF2_HPL_OVER		(1 << 7)
+/* Right Headphone Driver Over Current */
+#define AIC3204_INTF2_HPR_OVER		(1 << 6)
+/* Headset button pressed */
+#define AIC3204_INTF2_HS_BUTTON		(1 << 5)
+/* Headset plug inserted/removed */
+#define AIC3204_INTF2_HS_PLUGGED	(1 << 4)
+/* Left Channel DRC: Over threshold */
+#define AIC3204_INTF2_LDRC_OVER		(1 << 3)
+/* Right Channel DRC: Over threshold */
+#define AIC3204_INTF2_RDRC_OVER		(1 << 2)
+
+/* Interrupt Flag Register 3 */
+#define AIC3204_INTF3			AIC3204_PGREG(0, 47)
+/* Left AGC Noise Threshold Flag: Over threshold */
+#define AIC3204_INTF3_LAGC_OVER		(1 << 6)
+/* Right AGC Noise Threshold Flag: Over threshold */
+#define AIC3204_INTF3_RAGC_OVER		(1 << 5)
+/* Left ADC DC Measurement Available */
+#define AIC3204_INTF3_LADC_DC		(1 << 2)
+/* Right ADC DC Measurement Available */
+#define AIC3204_INTF3_RADC_DC		(1 << 1)
+
+/* INT1 Interrupt Control Register */
+#define AIC3204_INT1			AIC3204_PGREG(0, 48)
+/* INT1 Generated on Headset insertion */
+#define AIC3204_INT1_HS_PLUG		(1 << 7)
+/* INT1 Generated on Headset Button press */
+#define AIC3204_INT1_HS_BUTTON		(1 << 6)
+/* INT1 Generated on DAC DRC Signal Threshold */
+#define AIC3204_INT1_DAC_DRC		(1 << 5)
+/* INT1 Generated on AGC Noise Interrupt */
+#define AIC3204_INT1_ADC_NOISE		(1 << 4)
+/* INT1 Generated on Over Current */
+#define AIC3204_INT1_HP_OVERCURRENT	(1 << 3)
+/* INT1 Generated on overflow event */
+#define AIC3204_INT1_OVERFLOW		(1 << 2)
+/* INT1 Generated on DC measurement */
+#define AIC3204_INT1_DC			(1 << 1)
+/* INT1 pulse control: Continuous pulse train */
+#define AIC3204_INT1_CONT_PULSE		(1 << 0)
+
+/* INT2 Interrupt Control Register */
+#define AIC3204_INT2			AIC3204_PGREG(0, 49)
+/* INT2 Generated on Headset insertion */
+#define AIC3204_INT2_HS_PLUG		(1 << 7)
+/* INT2 Generated on Headset Button press */
+#define AIC3204_INT2_HS_BUTTON		(1 << 6)
+/* INT2 Generated on DAC DRC Signal Threshold */
+#define AIC3204_INT2_DAC_DRC		(1 << 5)
+/* INT2 Generated on AGC Noise Interrupt */
+#define AIC3204_INT2_ADC_NOISE		(1 << 4)
+/* INT2 Generated on Over Current */
+#define AIC3204_INT2_HP_OVERCURRENT	(1 << 3)
+/* INT2 Generated on overflow event */
+#define AIC3204_INT2_OVERFLOW		(1 << 2)
+/* INT2 Generated on DC measurement */
+#define AIC3204_INT2_DC			(1 << 1)
+/* INT2 pulse control: Continuous pulse train */
+#define AIC3204_INT2_CONT_PULSE		(1 << 0)
+
+/* GPIO/MFP5 Control Register */
+#define AIC3204_MFP5			AIC3204_PGREG(0, 52)
+/* GPIO Control: Disabled */
+#define AIC3204_MFP5_FUNC_DISABLED	(0 << 2)
+/* GPIO Control: Secondary audio interface/digital microphone/clock input */
+#define AIC3204_MFP5_FUNC_SAI_DM_CI	(1 << 2)
+/* GPIO Control: General Purpose Input */
+#define AIC3204_MFP5_FUNC_INPUT		(2 << 2)
+/* GPIO Control: General Purpose Output */
+#define AIC3204_MFP5_FUNC_OUTPUT	(3 << 2)
+/* GPIO Control: CLKOUT Output */
+#define AIC3204_MFP5_FUNC_CLKOUT	(4 << 2)
+/* GPIO Control: INT1 Output */
+#define AIC3204_MFP5_FUNC_INT1		(4 << 2)
+/* GPIO Control: INT2 Output */
+#define AIC3204_MFP5_FUNC_INT2		(4 << 2)
+/* GPIO Control: ADC_WCLK */
+#define AIC3204_MFP5_FUNC_ADC_WCLK	(4 << 2)
+/* GPIO Control: Secondary Bit Clock */
+#define AIC3204_MFP5_FUNC_SEC_BCLK	(4 << 2)
+/* GPIO Control: Secondary Word Clock */
+#define AIC3204_MFP5_FUNC_SEC_WCLK	(4 << 2)
+/* GPIO Control: Digital Microphone Clock */
+#define AIC3204_MFP5_FUNC_DMIC_CLK	(4 << 2)
+/* GPIO Control Mask */
+#define AIC3204_MFP5_FUNC		(15 << 2)
+/* GPIO Input State */
+#define AIC3204_MFP5_IN			(1 << 1)
+/* GPIO Output State */
+#define AIC3204_MFP5_OUT		(1 << 0)
+
+/* DOUT/MFP2 Function Control Register */
+#define AIC3204_MFP2			AIC3204_PGREG(0, 53)
+/* DOUT Bus Keeper Enabled */
+#define AIC3204_MFP2_BK			(1 << 4)
+/* DOUT MUX Control: Disabled */
+#define AIC3204_MFP2_FUNC_DISABLED	(0 << 1)
+/* DOUT MUX Control: Primary DOUT */
+#define AIC3204_MFP2_FUNC_PRI_DOUT	(1 << 1)
+/* DOUT MUX Control: General Purpose Output */
+#define AIC3204_MFP2_FUNC_OUTPUT	(2 << 1)
+/* DOUT MUX Control: CLKOUT Clock Output */
+#define AIC3204_MFP2_FUNC_CLKOUT	(3 << 1)
+/* DOUT MUX Control: INT1 Output */
+#define AIC3204_MFP2_FUNC_INT1		(4 << 1)
+/* DOUT MUX Control: INT2 Output */
+#define AIC3204_MFP2_FUNC_INT2		(5 << 1)
+/* DOUT MUX Control: Secondary Bit Clock */
+#define AIC3204_MFP2_FUNC_SEC_BCLK	(6 << 1)
+/* DOUT MUX Control: Secondary Word Clock */
+#define AIC3204_MFP2_FUNC_SEC_WCLK	(7 << 1)
+/* DOUT MUX Control Mask */
+#define AIC3204_MFP2_FUNC		(7 << 1)
+/* DOUT General Purpose Output State */
+#define AIC3204_MFP2_OUT		(1 << 0)
+
+/* DIN/MFP1 Function Control Register */
+#define AIC3204_MFP1			AIC3204_PGREG(0, 54)
+/* DIN Function Control: Disabled */
+#define AIC3204_MFP1_FUNC_DISABLED	(0 << 1)
+/* DIN Function Control: Primary Data Input/Digital Microphone/Clock Input */
+#define AIC3204_MFP1_FUNC_DIN_DM_CI	(1 << 1)
+/* DIN Function Control: General Purpose Input */
+#define AIC3204_MFP1_FUNC_INPUT		(2 << 1)
+/* DIN Function Control Mask */
+#define AIC3204_MFP1_FUNC		(3 << 1)
+/* DIN Input State */
+#define AIC3204_MFP1_IN			(1 << 0)
+
+/* MISO/MFP4 Function Control Register */
+#define AIC3204_MFP4			AIC3204_PGREG(0, 55)
+/* MISO Function Control: Disabled */
+#define AIC3204_MFP4_FUNC_DISABLED	(0 << 1)
+/* MISO Function Control: SPI Data Output (disabled in I2C mode) */
+#define AIC3204_MFP4_FUNC_SPI_OUT	(1 << 1)
+/* MISO Function Control: General Purpose Output */
+#define AIC3204_MFP4_FUNC_OUTPUT	(2 << 1)
+/* MISO Function Control: CLKOUT Clock Output */
+#define AIC3204_MFP4_FUNC_CLKOUT	(3 << 1)
+/* MISO Function Control: INT1 Output */
+#define AIC3204_MFP4_FUNC_INT1		(4 << 1)
+/* MISO Function Control: INT2 Output */
+#define AIC3204_MFP4_FUNC_INT2		(5 << 1)
+/* MISO Function Control: ADC Word Clock Output */
+#define AIC3204_MFP4_FUNC_ADC_WCLK	(6 << 1)
+/* MISO Function Control: Digital Microphone Clock Output */
+#define AIC3204_MFP4_FUNC_DMIC_CLK	(7 << 1)
+/* MISO Function Control: Secondary Data Output */
+#define AIC3204_MFP4_FUNC_SEC_DOUT	(8 << 1)
+/* MISO Function Control: Secondary Bit Clock */
+#define AIC3204_MFP4_FUNC_SEC_BCLK	(9 << 1)
+/* MISO Function Control: Secondary Word Clock */
+#define AIC3204_MFP4_FUNC_SEC_WCLK	(10 << 1)
+/* MISO Function Control Mask */
+#define AIC3204_MFP4_FUNC		(15 << 1)
+/* MISO Output State */
+#define AIC3204_MFP4_OUT		(1 << 0)
+
+/* SCLK/MFP3 Function Control Register */
+#define AIC3204_MFP3			AIC3204_PGREG(0, 56)
+/* SCLK Function Control: Disabled */
+#define AIC3204_MFP3_FUNC_DISABLED	(0 << 1)
+/* SCLK Function Control: SPI Clock / Secondary Interface / Digital Mic Input */
+#define AIC3204_MFP3_FUNC_SPI_SI_DM	(1 << 1)
+/* SCLK Function Control: General Purpose Input */
+#define AIC3204_MFP3_FUNC_INPUT		(2 << 1)
+/* SCLK Function Control Mask */
+#define AIC3204_MFP3_FUNC		(3 << 1)
+/* SCLK Input State */
+#define AIC3204_MFP3_IN			(1 << 0)
+
+/* DAC Signal Processing Block Control Register */
+#define AIC3204_DACSPB			AIC3204_PGREG(0, 60)
+/* DAC Signal Processing Block Mask */
+#define AIC3204_DACSPB_MASK		0x1f
+
+/* ADC Signal Processing Block Control Register */
+#define AIC3204_ADCSPB			AIC3204_PGREG(0, 61)
+/* ADC Signal Processing Block Mask */
+#define AIC3204_ADCSPB_MASK		0x1f
+
+/* DAC Channel Setup Register 1 */
+#define AIC3204_DACS1			AIC3204_PGREG(0, 63)
+/* Left DAC Powered Up */
+#define AIC3204_DACS1_LDAC_UP_SHIFT	(7)
+/* Right DAC Powered Up */
+#define AIC3204_DACS1_RDAC_UP_SHIFT	(6)
+/* Left DAC Data Path Control: Disabled */
+#define AIC3204_DACS1_LDACD_DIS		(0 << 4)
+/* Left DAC Data Path Control: Left Data */
+#define AIC3204_DACS1_LDACD_LEFT	(1 << 4)
+/* Left DAC Data Path Control: Right Data */
+#define AIC3204_DACS1_LDACD_RIGHT	(2 << 4)
+/* Left DAC Data Path Control: Left + Right */
+#define AIC3204_DACS1_LDACD_MIX		(3 << 4)
+/* Left DAC Data Path Control Mask */
+#define AIC3204_DACS1_LDACD		(3 << 4)
+/* Right DAC Data Path Control: Disabled */
+#define AIC3204_DACS1_RDACD_DIS		(0 << 2)
+/* Right DAC Data Path Control: Right Data */
+#define AIC3204_DACS1_RDACD_RIGHT	(1 << 2)
+/* Right DAC Data Path Control: Left Data */
+#define AIC3204_DACS1_RDACD_LEFT	(2 << 2)
+/* Right DAC Data Path Control: Left + Right */
+#define AIC3204_DACS1_RDACD_MIX		(3 << 2)
+/* Right DAC Data Path Control Mask */
+#define AIC3204_DACS1_RDACD		(3 << 2)
+/* DAC Soft-Step: Disabled */
+#define AIC3204_DACS1_SOFT_DIS		(0 << 0)
+/* DAC Soft-Step: 1 step every clock */
+#define AIC3204_DACS1_SOFT_1SEC		(1 << 0)
+/* DAC Soft-Step: 1 step every 2 clocks */
+#define AIC3204_DACS1_SOFT_1SE2C	(2 << 0)
+/* DAC Soft-Step Mask */
+#define AIC3204_DACS1_SOFT		(3 << 0)
+
+/* DAC Channel Setup Register 2 */
+#define AIC3204_DACS2			AIC3204_PGREG(0, 64)
+/* Right Modulator Output Control: Output is inverted left output */
+#define AIC3204_DACS2_RMOD_INV_SHIFT	(7)
+/* DAC Auto Mute: Disabled */
+#define AIC3204_DACS2_AMUTE_DIS		(0 << 4)
+/* DAC Auto Mute: After 100 samples of DC */
+#define AIC3204_DACS2_AMUTE_100		(1 << 4)
+/* DAC Auto Mute: After 200 samples of DC */
+#define AIC3204_DACS2_AMUTE_200		(2 << 4)
+/* DAC Auto Mute: After 400 samples of DC */
+#define AIC3204_DACS2_AMUTE_400		(3 << 4)
+/* DAC Auto Mute: After 800 samples of DC */
+#define AIC3204_DACS2_AMUTE_800		(4 << 4)
+/* DAC Auto Mute: After 1600 samples of DC */
+#define AIC3204_DACS2_AMUTE_1600	(5 << 4)
+/* DAC Auto Mute: After 3200 samples of DC */
+#define AIC3204_DACS2_AMUTE_3200	(6 << 4)
+/* DAC Auto Mute: After 6400 samples of DC */
+#define AIC3204_DACS2_AMUTE_6400	(7 << 4)
+/* DAC Auto Mute Mask */
+#define AIC3204_DACS2_AMUTE		(7 << 4)
+/* Left DAC Muted */
+#define AIC3204_DACS2_LEFT_MUTE_SHIFT	(3)
+/* Right DAC Muted */
+#define AIC3204_DACS2_RIGHT_MUTE_SHIFT	(2)
+/* DAC Master Volume Control: Independant */
+#define AIC3204_DACS2_VOL_IND		(0 << 0)
+/* DAC Master Volume Control: Left controls right */
+#define AIC3204_DACS2_VOL_LEFT		(1 << 0)
+/* DAC Master Volume Control: Right controls left */
+#define AIC3204_DACS2_VOL_RIGHT		(2 << 0)
+/* DAC Master Volume Control Mask */
+#define AIC3204_DACS2_VOL			(3 << 0)
+
+/* Left DAC Digital Volume Control */
+#define AIC3204_LDACVOL			AIC3204_PGREG(0, 65)
+
+/* Right DAC Digital Volume Control */
+#define AIC3204_RDACVOL			AIC3204_PGREG(0, 66)
+
+/* Headset Detection Configuration Register */
+#define AIC3204_HSDET			AIC3204_PGREG(0, 67)
+/* Enable Headset Detection */
+#define AIC3204_HSDET_ENABLE		(1 << 7)
+/* Headset Type: No Headset */
+#define AIC3204_HSDET_NONE		(0 << 5)
+/* Headset Type: Stereo Headset */
+#define AIC3204_HSDET_STEREO		(1 << 5)
+/* Headset Type: Cellular Stereo Headset */
+#define AIC3204_HSDET_CELLSTEREO	(3 << 5)
+/* Headset Detection Debounce Time: 16ms */
+#define AIC3204_HSDET_PLUGDT_16		(0 << 2)
+/* Headset Detection Debounce Time: 32ms */
+#define AIC3204_HSDET_PLUGDT_32		(1 << 2)
+/* Headset Detection Debounce Time: 64ms */
+#define AIC3204_HSDET_PLUGDT_64		(2 << 2)
+/* Headset Detection Debounce Time: 128ms */
+#define AIC3204_HSDET_PLUGDT_128	(3 << 2)
+/* Headset Detection Debounce Time: 256ms */
+#define AIC3204_HSDET_PLUGDT_256	(4 << 2)
+/* Headset Detection Debounce Time: 512ms */
+#define AIC3204_HSDET_PLUGDT_512	(5 << 2)
+/* Headset Detection Debounce Time Mask */
+#define AIC3204_HSDET_PLUGDT		(7 << 2)
+/* Headset Button Debounce Time: 8ms */
+#define AIC3204_HSDET_BTNDT_8		(0 << 0)
+/* Headset Button Debounce Time: 16ms */
+#define AIC3204_HSDET_BTNDT_16		(1 << 0)
+/* Headset Button Debounce Time: 32ms */
+#define AIC3204_HSDET_BTNDT_32		(2 << 0)
+/* Headset Button Debounce Time Mask */
+#define AIC3204_HSDET_BTNDT		(3 << 0)
+
+/* DRC Control Register 1 */
+#define AIC3204_DRC1			AIC3204_PGREG(0, 68)
+/* Left Channel DRC Enable */
+#define AIC3204_DRC1_LEFT_EN		(1 << 6)
+/* Right Channel DRC Enable */
+#define AIC3204_DRC1_RIGHT_EN		(1 << 5)
+/* DRC Threshold: -3dBFS */
+#define AIC3204_DRC1_THOLD_3DBFS	(0 << 2)
+/* DRC Threshold: -6dBFS */
+#define AIC3204_DRC1_THOLD_6DBFS	(1 << 2)
+/* DRC Threshold: -9dBFS */
+#define AIC3204_DRC1_THOLD_9DBFS	(2 << 2)
+/* DRC Threshold: -12dBFS */
+#define AIC3204_DRC1_THOLD_12DBFS	(3 << 2)
+/* DRC Threshold: -15dBFS */
+#define AIC3204_DRC1_THOLD_15DBFS	(4 << 2)
+/* DRC Threshold: -18dBFS */
+#define AIC3204_DRC1_THOLD_18DBFS	(5 << 2)
+/* DRC Threshold: -21dBFS */
+#define AIC3204_DRC1_THOLD_21DBFS	(6 << 2)
+/* DRC Threshold: -24dBFS */
+#define AIC3204_DRC1_THOLD_24DBFS	(7 << 2)
+/* DRC Threshold Mask */
+#define AIC3204_DRC1_THOLD		(7 << 2)
+/* DRC Hysteresis: 0dB */
+#define AIC3204_DRC1_HYST_0DB		(0 << 0)
+/* DRC Hysteresis: 1dB */
+#define AIC3204_DRC1_HYST_1DB		(1 << 0)
+/* DRC Hysteresis: 2dB */
+#define AIC3204_DRC1_HYST_2DB		(2 << 0)
+/* DRC Hysteresis: 3dB */
+#define AIC3204_DRC1_HYST_3DB		(3 << 0)
+/* DRC Hysteresis Mask */
+#define AIC3204_DRC1_HYST		(3 << 0)
+
+/* DRC Control Register 2 */
+#define AIC3204_DRC2			AIC3204_PGREG(0, 69)
+/* DRC Hold: Disabled */
+#define AIC3204_DRC2_HOLD_DISABLED	(0 << 3)
+/* DRC Hold: 32 Word Clocks */
+#define AIC3204_DRC2_HOLD_32WC		(1 << 3)
+/* DRC Hold: 64 Word Clocks */
+#define AIC3204_DRC2_HOLD_64WC		(2 << 3)
+/* DRC Hold: 128 Word Clocks */
+#define AIC3204_DRC2_HOLD_128WC		(3 << 3)
+/* DRC Hold: 256 Word Clocks */
+#define AIC3204_DRC2_HOLD_256WC		(4 << 3)
+/* DRC Hold: 512 Word Clocks */
+#define AIC3204_DRC2_HOLD_512WC		(5 << 3)
+/* DRC Hold: 1024 Word Clocks */
+#define AIC3204_DRC2_HOLD_1024WC	(6 << 3)
+/* DRC Hold: 2048 Word Clocks */
+#define AIC3204_DRC2_HOLD_2048WC	(7 << 3)
+/* DRC Hold: 4096 Word Clocks */
+#define AIC3204_DRC2_HOLD_4096WC	(8 << 3)
+/* DRC Hold: 8192 Word Clocks */
+#define AIC3204_DRC2_HOLD_8192WC	(9 << 3)
+/* DRC Hold: 16384 Word Clocks */
+#define AIC3204_DRC2_HOLD_16384WC	(10 << 3)
+/* DRC Hold: 32768 Word Clocks */
+#define AIC3204_DRC2_HOLD_32768WC	(11 << 3)
+/* DRC Hold: 65536 Word Clocks */
+#define AIC3204_DRC2_HOLD_65536WC	(12 << 3)
+/* DRC Hold: 98304 Word Clocks */
+#define AIC3204_DRC2_HOLD_98304WC	(13 << 3)
+/* DRC Hold: 131072 Word Clocks */
+#define AIC3204_DRC2_HOLD_131072WC	(14 << 3)
+/* DRC Hold: 163840 Word Clocks */
+#define AIC3204_DRC2_HOLD_163840WC	(15 << 3)
+/* DRC Hold Mask */
+#define AIC3204_DRC2_HOLD		(15 << 3)
+
+/* DRC Control Register 3 */
+#define AIC3204_DRC3			AIC3204_PGREG(0, 70)
+/* DRC Attack Rate Shift */
+#define AIC3204_DRC3_ATTACK_SHIFT	4
+/* DRC Attack Rate Mask */
+#define AIC3204_DRC3_ATTACK		(15 << AIC3204_DRC3_ATTACK_SHIFT)
+/* DRC Decay Rate Shift */
+#define AIC3204_DRC3_DECAY_SHIFT	0
+/* DRC Decay Rate Mask */
+#define AIC3204_DRC3_DECAY		(15 << AIC3204_DRC3_DECAY_SHIFT)
+
+/* Beep Generator Register 1 */
+#define AIC3204_BEEP1			AIC3204_PGREG(0, 71)
+/* Enable Beep Generator */
+#define AIC3204_BEEP1_EN		(1 << 7)
+/* Left Channel Beep Volume Shift */
+#define AIC3204_BEEP1_VOL_SHIFT		0
+/* Left Channel Beep Volume Mask */
+#define AIC3204_BEEP1_VOL		(0x3f)
+
+/* Beep Generator Register 2 */
+#define AIC3204_BEEP2			AIC3204_PGREG(0, 72)
+/* Beep Generator Master Volume: Independant Left/Right Channels */
+#define AIC3204_BEEP2_MVOL_IND		(0 << 6)
+/* Beep Generator Master Volume: Left Channel controls Right */
+#define AIC3204_BEEP2_MVOL_LEFT		(1 << 6)
+/* Beep Generator Master Volume: Right Channel controls Left */
+#define AIC3204_BEEP2_MVOL_RIGHT	(2 << 6)
+/* Beep Generator Master Volume Mask */
+#define AIC3204_BEEP2_MVOL		(3 << 6)
+
+/* Beep Generator Register 3 */
+#define AIC3204_BEEP3			AIC3204_PGREG(0, 73)
+/* Sample Length Value Shift */
+#define AIC3204_BEEP3_LENGTH_VSHIFT	16
+/* Sample Length Shift */
+#define AIC3204_BEEP3_LENGTH_SHIFT	0
+/* Sample Length Mask */
+#define AIC3204_BEEP3_LENGTH		(0xff)
+
+/* Beep Generator Register 4 */
+#define AIC3204_BEEP4			AIC3204_PGREG(0, 74)
+/* Sample Length Value Shift */
+#define AIC3204_BEEP4_LENGTH_VSHIFT	8
+/* Sample Length Shift */
+#define AIC3204_BEEP4_LENGTH_SHIFT	0
+/* Sample Length Mask */
+#define AIC3204_BEEP4_LENGTH		(0xff)
+
+/* Beep Generator Register 5 */
+#define AIC3204_BEEP5			AIC3204_PGREG(0, 75)
+/* Sample Length Value Shift */
+#define AIC3204_BEEP5_LENGTH_VSHIFT	0
+/* Sample Length Shift */
+#define AIC3204_BEEP5_LENGTH_SHIFT	0
+/* Sample Length Mask */
+#define AIC3204_BEEP5_LENGTH		(0xff)
+
+/* Beep Generator Register 6 */
+#define AIC3204_BEEP6			AIC3204_PGREG(0, 76)
+/* Relative Sine Frequency Value Shift */
+#define AIC3204_BEEP6_SINFREQ_VSHIFT	8
+/* Relative Sine Frequency Shift */
+#define AIC3204_BEEP6_SINFREQ_SHIFT	0
+/* Relative Sine Frequency Mask */
+#define AIC3204_BEEP6_SINFREQ		(0xff)
+
+/* Beep Generator Register 7 */
+#define AIC3204_BEEP7			AIC3204_PGREG(0, 77)
+/* Relative Sine Frequency Value Shift */
+#define AIC3204_BEEP7_SINFREQ_VSHIFT	0
+/* Relative Sine Frequency Shift */
+#define AIC3204_BEEP7_SINFREQ_SHIFT	0
+/* Relative Sine Frequency Mask */
+#define AIC3204_BEEP7_SINFREQ		(0xff)
+
+/* Beep Generator Register 8 */
+#define AIC3204_BEEP8			AIC3204_PGREG(0, 78)
+/* Relative Cosine Frequency Value Shift */
+#define AIC3204_BEEP8_COSFREQ_VSHIFT	8
+/* Relative Cosine Frequency Shift */
+#define AIC3204_BEEP8_COSFREQ_SHIFT	0
+/* Relative Cosine Frequency Mask */
+#define AIC3204_BEEP8_COSFREQ		(0xff)
+
+/* Beep Generator Register 9 */
+#define AIC3204_BEEP9			AIC3204_PGREG(0, 79)
+/* Relative Cosine Frequency Value Shift */
+#define AIC3204_BEEP9_COSFREQ_VSHIFT	0
+/* Relative Cosine Frequency Shift */
+#define AIC3204_BEEP9_COSFREQ_SHIFT	0
+/* Relative Cosine Frequency Mask */
+#define AIC3204_BEEP9_COSFREQ		(0xff)
+
+/* ADC Channel Setup Register */
+#define AIC3204_ADCS			AIC3204_PGREG(0, 81)
+/* Left Channel ADC Powered Up */
+#define AIC3204_ADCS_LADC_UP_SHIFT	(7)
+/* Right Channel ADC Powered Up */
+#define AIC3204_ADCS_RADC_UP_SHIFT	(6)
+/* Digital Microphone Input: GPIO */
+#define AIC3204_ADC5_DMICIN_GPIO	(0 << 4)
+/* Digital Microphone Input: SCLK */
+#define AIC3204_ADC5_DMICIN_SCLK	(1 << 4)
+/* Digital Microphone Input: DIN */
+#define AIC3204_ADC5_DMICIN_DIN		(2 << 4)
+/* Digital Microphone Input Mask */
+#define AIC3204_ADC5_DMICIN		(3 << 4)
+/* Left ADC Source: Digital Microphone */
+#define AIC3204_ADC5_LADC_DMIC		(1 << 3)
+/* Right ADC Source: Digital Microphone */
+#define AIC3204_ADC5_RADC_DMIC		(1 << 2)
+/* ADC Volume Soft Step: 1 step / word clock */
+#define AIC3204_ADC5_VOLSS_1SPWC	(0 << 0)
+/* ADC Volume Soft Step: 1 step / 2 word clocks */
+#define AIC3204_ADC5_VOLSS_1SP2WC	(1 << 0)
+/* ADC Volume Soft Step: Disabled */
+#define AIC3204_ADC5_VOLSS_DISABLED	(2 << 0)
+/* ADC Volume Soft Step Mask */
+#define AIC3204_ADC5_VOLSS		(3 << 0)
+
+/* ADC Fine Gain Adjust Register */
+#define AIC3204_ADCFINE			AIC3204_PGREG(0, 82)
+/* Left ADC Mute */
+#define AIC3204_ADCFINE_LEFT_MUTE	(1 << 7)
+/* Left ADC Gain: 0dB */
+#define AIC3204_ADCFINE_LEFT_0DB	(0 << 4)
+/* Left ADC Gain: -0.1dB */
+#define AIC3204_ADCFINE_LEFT_0DB1	(1 << 4)
+/* Left ADC Gain: -0.2dB */
+#define AIC3204_ADCFINE_LEFT_0DB2	(2 << 4)
+/* Left ADC Gain: -0.3dB */
+#define AIC3204_ADCFINE_LEFT_0DB3	(2 << 4)
+/* Left ADC Gain: -0.4dB */
+#define AIC3204_ADCFINE_LEFT_0DB4	(3 << 4)
+/* Left ADC Gain Mask */
+#define AIC3204_ADCFINE_LEFT		(7 << 4)
+/* Right ADC Mute */
+#define AIC3204_ADCFINE_RIGHT_MUTE	(1 << 3)
+/* Right ADC Gain: 0dB */
+#define AIC3204_ADCFINE_RIGHT_0DB	(0 << 0)
+/* Right ADC Gain: -0.1dB */
+#define AIC3204_ADCFINE_RIGHT_0DB1	(1 << 0)
+/* Right ADC Gain: -0.2dB */
+#define AIC3204_ADCFINE_RIGHT_0DB2	(2 << 0)
+/* Right ADC Gain: -0.3dB */
+#define AIC3204_ADCFINE_RIGHT_0DB3	(2 << 0)
+/* Right ADC Gain: -0.4dB */
+#define AIC3204_ADCFINE_RIGHT_0DB4	(3 << 0)
+/* Right ADC Gain Mask */
+#define AIC3204_ADCFINE_RIGHT		(7 << 0)
+
+/* Left ADC Channel Volume Register */
+#define AIC3204_LADCVOL			AIC3204_PGREG(0, 83)
+/* Left ADC Channel Volume Mask */
+#define AIC3204_LADCVOL_MASK		0x7f
+
+/* Right ADC Channel Volume Register */
+#define AIC3204_RADCVOL			AIC3204_PGREG(0, 84)
+/* Right ADC Channel Volume Mask */
+#define AIC3204_RADCVOL_MASK		0x7f
+
+/* ADC Phase Adjust Register */
+#define AIC3204_ADCPHASE		AIC3204_PGREG(0, 85)
+
+/* Left Channel AGC Control Register 1 */
+#define AIC3204_LAGC1			AIC3204_PGREG(0, 86)
+/* Left Channel AGC Enabled */
+#define AIC3204_LAGC1_ENABLE		(1 << 7)
+/* Left Channel Target Level: -5.5dBFS */
+#define AIC3204_LAGC1_LEVEL_5DBFS5	(0 << 4)
+/* Left Channel Target Level: -8.0dBFS */
+#define AIC3204_LAGC1_LEVEL_8DBFS	(1 << 4)
+/* Left Channel Target Level: -10dBFS */
+#define AIC3204_LAGC1_LEVEL_10DBFS	(2 << 4)
+/* Left Channel Target Level: -12dBFS */
+#define AIC3204_LAGC1_LEVEL_12DBFS	(3 << 4)
+/* Left Channel Target Level: -14dBFS */
+#define AIC3204_LAGC1_LEVEL_14DBFS	(4 << 4)
+/* Left Channel Target Level: -17dBFS */
+#define AIC3204_LAGC1_LEVEL_17DBFS	(5 << 4)
+/* Left Channel Target Level: -20dBFS */
+#define AIC3204_LAGC1_LEVEL_20DBFS	(6 << 4)
+/* Left Channel Target Level: -24dBFS */
+#define AIC3204_LAGC1_LEVEL_24DBFS	(7 << 4)
+/* Left Channel Target Level Mask */
+#define AIC3204_LAGC1_LEVEL		(7 << 4)
+/* Left Channel Gain Hysteresis: Disabled */
+#define AIC3204_LAGC1_GAINHYST_DISABLED	(0 << 0)
+/* Left Channel Gain Hysteresis: 0.5dB */
+#define AIC3204_LAGC1_GAINHYST_0DB5	(1 << 0)
+/* Left Channel Gain Hysteresis: 1dB */
+#define AIC3204_LAGC1_GAINHYST_1DB	(2 << 0)
+/* Left Channel Gain Hysteresis: 1.5dB */
+#define AIC3204_LAGC1_GAINHYST_1DB5	(3 << 0)
+/* Left Channel Gain Hysteresis Mask */
+#define AIC3204_LAGC1_GAINHYST		(3 << 0)
+
+/* Left Channel AGC Control Register 2 */
+#define AIC3204_LAGC2			AIC3204_PGREG(0, 87)
+/* Left Channel AGC Hysteresis: 1dB */
+#define AIC3204_LAGC2_HYST_1DB		(0 << 6)
+/* Left Channel AGC Hysteresis: 2dB */
+#define AIC3204_LAGC2_HYST_2DB		(1 << 6)
+/* Left Channel AGC Hysteresis: 4dB */
+#define AIC3204_LAGC2_HYST_4DB		(2 << 6)
+/* Left Channel AGC Hysteresis: Disabled */
+#define AIC3204_LAGC2_HYST_DISABLED	(3 << 6)
+/* Left Channel AGC Hysteresis Mask */
+#define AIC3204_LAGC2_HYST		(3 << 6)
+/* Left Channel AGC Noise Gate Threshold Mask */
+#define AIC3204_LAGC2_NGATE		(0x1f)
+/* Left Channel AGC Noise Gate Threshold Shift */
+#define AIC3204_LAGC2_NGATE_SHIFT	1
+
+/* TODO: Remaining AGC registers, DC measurement registers */
+
+/* Power Configuration Register */
+#define AIC3204_POWER			AIC3204_PGREG(1, 1)
+/* Disable AVDD -> DVDD Link */
+#define AIC3204_POWER_AVDD_DVDD_UNLINK	(1 << 3)
+
+/* LDO Control Register */
+#define AIC3204_LDO			AIC3204_PGREG(1, 2)
+/* DVDD LDO: 1.72V */
+#define AIC3204_LDO_DVDD_1V72		(0 << 6)
+/* DVDD LDO: 1.67V */
+#define AIC3204_LDO_DVDD_1V67		(1 << 6)
+/* DVDD LDO: 1.77V */
+#define AIC3204_LDO_DVDD_1V77		(2 << 6)
+/* DVDD LDO Mask */
+#define AIC3204_LDO_DVDD		(3 << 6)
+/* AVDD LDO: 1.72V */
+#define AIC3204_LDO_AVDD_1V72		(0 << 4)
+/* AVDD LDO: 1.67V */
+#define AIC3204_LDO_AVDD_1V67		(1 << 4)
+/* AVDD LDO: 1.77V */
+#define AIC3204_LDO_AVDD_1V77		(2 << 4)
+/* AVDD LDO Mask */
+#define AIC3204_LDO_AVDD		(3 << 4)
+/* Analog Blocks Enabled */
+#define AIC3204_LDO_ANALOG_ENABLED	(0 << 3)
+/* Analog Blocks Disabled */
+#define AIC3204_LDO_ANALOG_DISABLED	(1 << 3)
+/* Analog Block Status */
+#define AIC3204_LDO_ANALOG		(1 << 3)
+/* DVDD Over Current Detect */
+#define AIC3204_LDO_DVDD_OVERCURRENT	(1 << 2)
+/* AVDD Over Current Detect */
+#define AIC3204_LDO_AVDD_OVERCURRENT	(1 << 1)
+/* AVDD Powered Up */
+#define AIC3204_LDO_AVDD_UP		(1 << 0)
+
+/* TODO: Playback Configuration Registers */
+
+/* Output Driver Power Control Register */
+#define AIC3204_OUTDRV			AIC3204_PGREG(1, 9)
+/* Left Headphone Driver Up */
+#define AIC3204_OUTDRV_HPL_UP_SHIFT	(5)
+/* Right Headphone Driver Up */
+#define AIC3204_OUTDRV_HPR_UP_SHIFT	(4)
+/* Left Line Output Driver Up */
+#define AIC3204_OUTDRV_LOL_UP_SHIFT	(3)
+/* Right Line Output Driver Up */
+#define AIC3204_OUTDRV_LOR_UP_SHIFT	(2)
+/* Left Mixer Amplifier Up */
+#define AIC3204_OUTDRV_MAL_UP_SHIFT	(1)
+/* Right Mixer Amplifier Up */
+#define AIC3204_OUTDRV_MAR_UP_SHIFT	(0)
+
+/* Common Mode Control Register */
+#define AIC3204_CMCTL			AIC3204_PGREG(1, 10)
+/* Full Chip Common Mode = 0.9V */
+#define AIC3204_CMCTL_FCCM_0V9		(0 << 6)
+/* Full Chip Common Mode = 0.75V */
+#define AIC3204_CMCTL_FCCM_0V75		(1 << 6)
+/* Full Chip Common Mode Mask */
+#define AIC3204_CMCTL_FCCM		(1 << 6)
+/* Headphone Output Common Mode = Full Chip Common Mode */
+#define AIC3204_CMCTL_HPCM_FCCM		(0 << 4)
+/* Headphone Output Common Mode = 1.25V */
+#define AIC3204_CMCTL_HPCM_1V25		(1 << 4)
+/* Headphone Output Common Mode = 1.5V */
+#define AIC3204_CMCTL_HPCM_1V5		(2 << 4)
+/* Headphone Output Common Mode = 1.65V */
+#define AIC3204_CMCTL_HPCM_1V65		(3 << 4)
+/* Headphone Output Common Mode Mask */
+#define AIC3204_CMCTL_HPCM		(3 << 4)
+/* Line Output Common Mode = Full Chip Common Mode */
+#define AIC3204_CMCTL_LOCM_FCCM		(0 << 3)
+/* Line Output Common Mode = 1.65V from LDOin */
+#define AIC3204_CMCTL_LOCM_1V65LDOIN	(1 << 3)
+/* Line Output Common Mode Mask */
+#define AIC3204_CMCTL_LOCM		(1 << 3)
+/* Headphone Output Common Mode Source = AVDD */
+#define AIC3204_CMCTL_HPCMSRC_AVDD	(0 << 1)
+/* Headphone Output Common Mode Source = LDOin */
+#define AIC3204_CMCTL_HPCMSRC_LDOIN	(1 << 1)
+/* Headphone Output Common Mode Source Mask */
+#define AIC3204_CMCTL_HPCMSRC		(1 << 1)
+/* LDO Input Range = 1.5~1.95V */
+#define AIC3204_CMCTL_LDORANGE_1V5_1V95	(0 << 0)
+/* LDO Input Range = 1.8~3.6V */
+#define AIC3204_CMCTL_LDORANGE_1V8_3V6	(1 << 0)
+/* LDO Input Range Mask (effective when HPCMSRC = LDOIN) */
+#define AIC3204_CMCTL_LDORANGE		(1 << 0)
+
+/* Over Current Protection Configuration Register TODO */
+#define AIC3204_OCP			AIC3204_PGREG(1, 11)
+
+/* Left Headphone Driver Routing Register */
+#define AIC3204_HPLROUTE		AIC3204_PGREG(1, 12)
+/* Left Headphone Driver connects to LDAC+ */
+#define AIC3204_HPLROUTE_LDACP_SHIFT	(3)
+/* Left Headphone Driver connects to IN1L */
+#define AIC3204_HPLROUTE_IN1L_SHIFT	(2)
+/* Left Headphone Driver connects to MAL */
+#define AIC3204_HPLROUTE_MAL_SHIFT	(1)
+/* Left Headphone Driver connects to MAR */
+#define AIC3204_HPLROUTE_MAR_SHIFT	(0)
+
+/* Right Headphone Driver Routing Register */
+#define AIC3204_HPRROUTE		AIC3204_PGREG(1, 13)
+/* Right Headphone Driver connects to LDAC- */
+#define AIC3204_HPRROUTE_LDACN_SHIFT	(4)
+/* Right Headphone Driver connects to RDAC+ */
+#define AIC3204_HPRROUTE_RDACP_SHIFT	(3)
+/* Right Headphone Driver connects to IN1L */
+#define AIC3204_HPRROUTE_IN1R_SHIFT	(2)
+/* Right Headphone Driver connects to MAL */
+#define AIC3204_HPRROUTE_MAR_SHIFT	(1)
+/* Right Headphone Driver connects to HPL */
+#define AIC3204_HPRROUTE_HPL_SHIFT	(0)
+
+/* Left Line Output Routing Register */
+#define AIC3204_LOLROUTE		AIC3204_PGREG(1, 14)
+/* Left Line Output Driver connects to RDAC- */
+#define AIC3204_LOLROUTE_RDACN_SHIFT	(4)
+/* Left Line Output Driver connects to LDAC+ */
+#define AIC3204_LOLROUTE_LDACP_SHIFT	(3)
+/* Left Line Output Driver connects to MAL */
+#define AIC3204_LOLROUTE_MAL_SHIFT	(1)
+/* Left Line Output Driver connects to LOR */
+#define AIC3204_LOLROUTE_LOR_SHIFT	(0)
+
+/* Right Line Output Routing Register */
+#define AIC3204_LORROUTE		AIC3204_PGREG(1, 15)
+/* Right Line Output Driver connects to RDAC+ */
+#define AIC3204_LORROUTE_RDACP_SHIFT	(3)
+/* Right Line Output Driver connects to MAR */
+#define AIC3204_LORROUTE_MAR_SHIFT	(1)
+
+/* Left Headphone Gain Setting Register */
+#define AIC3204_HPLGAIN			AIC3204_PGREG(1, 16)
+/* Left Headphone Mute */
+#define AIC3204_HPLGAIN_MUTE_SHIFT	(6)
+/* Left Headphone Gain Mask */
+#define AIC3204_HPLGAIN_MASK		(0x3f)
+
+/* Right Headphone Gain Setting Register */
+#define AIC3204_HPRGAIN			AIC3204_PGREG(1, 17)
+/* Right Headphone Mute */
+#define AIC3204_HPRGAIN_MUTE_SHIFT	(6)
+/* Right Headphone Gain Mask */
+#define AIC3204_HPRGAIN_MASK		(0x3f)
+
+/* Left Line Output Gain Setting Register */
+#define AIC3204_LOLGAIN			AIC3204_PGREG(1, 18)
+/* Left Line Output Mute */
+#define AIC3204_LOLGAIN_MUTE_SHIFT	(6)
+/* Left Line Output Gain Mask */
+#define AIC3204_LOLGAIN_MASK		(0x3f)
+
+/* Right Line Output Gain Setting Register */
+#define AIC3204_LORGAIN			AIC3204_PGREG(1, 19)
+/* Right Line Output Mute */
+#define AIC3204_LORGAIN_MUTE_SHIFT	(6)
+/* Right Line Output Gain Mask */
+#define AIC3204_LORGAIN_MASK		(0x3f)
+
+/* Left Mixer Amplifier Gain Setting Register */
+#define AIC3204_MALGAIN			AIC3204_PGREG(1, 24)
+/* Left Mixer Amplifier Gain Mask */
+#define AIC3204_MALGAIN_MASK		(0x3f)
+
+/* Right Mixer Amplifier Gain Setting Register */
+#define AIC3204_MARGAIN			AIC3204_PGREG(1, 25)
+/* Right Mixer Amplifier Gain Mask */
+#define AIC3204_MARGAIN_MASK		(0x3f)
+
+#define AIC3204_MICBIAS			AIC3204_PGREG(1, 51)
+
+#define AIC3204_LMICPGAPROUTE		AIC3204_PGREG(1, 52)
+#define AIC3204_LMICPGANROUTE		AIC3204_PGREG(1, 54)
+
+#define AIC3204_RMICPGAPROUTE		AIC3204_PGREG(1, 55)
+#define AIC3204_RMICPGANROUTE		AIC3204_PGREG(1, 57)
+
+#define AIC3204_LMICPGAVOL		AIC3204_PGREG(1, 59)
+#define AIC3204_RMICPGAVOL		AIC3204_PGREG(1, 60)
+
+/* ADC Power Tune Mode Register */
+#define AIC3204_ADCPTM			AIC3204_PGREG(1, 61)
+/* ADC Power Tune Mode: PTM_R4 */
+#define AIC3204_ADCPTM_R4		(0x00)
+/* ADC Power Tune Mode: PTM_R3 */
+#define AIC3204_ADCPTM_R3		(0x64)
+/* ADC Power Tune Mode: PTM_R2 */
+#define AIC3204_ADCPTM_R2		(0xb6)
+/* ADC Power Tune Mode: PTM_R1 */
+#define AIC3204_ADCPTM_R1		(0xff)
+
+/* Analogue Input Quick Charging Configuration Register */
+#define AIC3204_AIQC			AIC3204_PGREG(1, 71)
+/* Power up time: Default Value (whatever that is) */
+#define AIC3204_AIQC_PWRUP_DEFAULT	(0x00)
+/* Power up time: 3.1ms */
+#define AIC3204_AIQC_PWRUP_3M1S		(0x31)
+/* Power up time: 6.4ms */
+#define AIC3204_AIQC_PWRUP_6M4S		(0x32)
+/* Power up time: 1.6ms */
+#define AIC3204_AIQC_PWRUP_1M6S		(0x33)
+/* Power up time mask */
+#define AIC3204_AIQC_PWRUP		(0x3f)
+
+/* Reference Power-Up Configuration Register */
+#define AIC3204_REFPU			AIC3204_PGREG(1, 123)
+/* Reference Power-Up delay: Slow */
+#define AIC3204_REFPU_DELAY_SLOW	(0 << 0)
+/* Reference Power-Up delay: 40ms */
+#define AIC3204_REFPU_DELAY_40MS	(1 << 0)
+/* Reference Power-Up delay: 80ms */
+#define AIC3204_REFPU_DELAY_80MS	(2 << 0)
+/* Reference Power-Up delay: 120ms */
+#define AIC3204_REFPU_DELAY_120MS	(3 << 0)
+/* Force power-up */
+#define AIC3204_REFPU_FORCE		(1 << 2)
+
+/* TODO: Define the remaining registers ... this will do for now */
+
+/*
+ * Since the AIC3204 has a great variety of settings to configure, rather than
+ * provide individual module parameters for each of them, instead the machine
+ * driver may pass in a const array of structs like this.
+ *
+ * This script of register modifications is run at initialisation, and is
+ * intended to configure the AIC3204 for use with the particular hardware
+ * surrounding it, e.g. GPIOs, filter coefficients, etc.
+ */
+struct aic3204_init_reg {
+	/*
+	 * The register to manipulate.  This register address contains the
+	 * page number in the upper 8 bits -- use the AIC3204_PGREG macro
+	 * to generate such a number.
+	 */
+	u16	reg;
+	/*
+	 * Flags: See the flags below; but this basically allows for the 
+	 * value field to be ANDed or ORed with the register value, rather
+	 * than setting it explicitly.
+	 */
+	u8	flags;
+	/*
+	 * The value to use in the operation
+	 */
+	u8	value;
+};
+
+/* Set Register = Value */
+#define AIC3204_INITFLAG_SET		(0 << 0)
+/* Set Register = Register & Value */
+#define AIC3204_INITFLAG_AND		(1 << 0)
+/* Set Register = Register | Value */
+#define AIC3204_INITFLAG_OR		(2 << 0)
+/* Set Register = Register ^ Value */
+#define AIC3204_INITFLAG_XOR		(3 << 0)
+/* Fail on Register != Value */
+#define AIC3204_INITFLAG_FAILNEQ	(4 << 0)
+/* Fail on Register == Value */
+#define AIC3204_INITFLAG_FAILEQ		(5 << 0)
+/* Fail on (Register & Value) == 0 */
+#define AIC3204_INITFLAG_FAILNSET	(6 << 0)
+/* Fail on (Register & Value) != 0 */
+#define AIC3204_INITFLAG_FAILSET	(7 << 0)
+/* Fail on (Register | Value) == 0xff */
+#define AIC3204_INITFLAG_FAILCLR	(8 << 0)
+/* Fail on (Register | Value) != 0xff */
+#define AIC3204_INITFLAG_FAILNCLR	(9 << 0)
+/* Register operation mask */
+#define AIC3204_INITFLAG_OPMASK		(15 << 0)
+
+struct aic3204_setup_data {
+	/* List of initialisation settings to perform at startup */
+	const struct aic3204_init_reg *init_reg_list;
+	/* Length of initialisation register list */
+	int init_reg_length;
+	/* ADC/DAC channel mask */
+	u8 channels;
+};
+
+#define AIC3204_LDAC_EN			(1 << 3)
+#define AIC3204_RDAC_EN			(1 << 2)
+#define AIC3204_LADC_EN			(1 << 1)
+#define AIC3204_RADC_EN			(1 << 0)
+
+extern struct snd_soc_dai aic3204_dai;
+extern struct snd_soc_codec_device soc_codec_dev_aic3204;
+
+#endif /* _AIC3204_H */
-- 
1.6.4.4



From eric.y.miao at gmail.com  Fri Jun 18 04:14:53 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 16:14:53 +0800
Subject: [PATCH 01/25] pxa3xx_nand: condense the flash definition
In-Reply-To: <AANLkTindDgsvPK-ZZsyB2cdsrh0IyykBuhgStuwvyIdg@mail.gmail.com>
References: <AANLkTil1FnPkGS7l6W0HWeXyOxXzWbZkvFWY4jJF_I_A@mail.gmail.com> 
	<AANLkTinOsQ8AcH-As91CRqrEQVnXdsm_CmFQgyj7gI1_@mail.gmail.com> 
	<AANLkTim9O5kuGzvQoB65fWDr3Bi9siiVBMCPx6heqZjd@mail.gmail.com> 
	<AANLkTimGzVtuJuuxipim-f6UhdK287EjF41UlhdKCWRM@mail.gmail.com> 
	<AANLkTindDgsvPK-ZZsyB2cdsrh0IyykBuhgStuwvyIdg@mail.gmail.com>
Message-ID: <AANLkTinwlsrxvjHyEs1IAwaw-8GXYN2lVrUOtYp0C52n@mail.gmail.com>

On Fri, Jun 18, 2010 at 4:10 PM, Lei Wen <adrian.wenl at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 4:00 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>>>>> -struct pxa3xx_nand_timing {
>>>>> - ? ? ? unsigned int ? ?tCH; ?/* Enable signal hold time */
>>>>> - ? ? ? unsigned int ? ?tCS; ?/* Enable signal setup time */
>>>>> - ? ? ? unsigned int ? ?tWH; ?/* ND_nWE high duration */
>>>>> - ? ? ? unsigned int ? ?tWP; ?/* ND_nWE pulse time */
>>>>> - ? ? ? unsigned int ? ?tRH; ?/* ND_nRE high duration */
>>>>> - ? ? ? unsigned int ? ?tRP; ?/* ND_nRE pulse width */
>>>>> - ? ? ? unsigned int ? ?tR; ? /* ND_nWE high to ND_nRE low for read */
>>>>> - ? ? ? unsigned int ? ?tWHR; /* ND_nWE high to ND_nRE low for status read */
>>>>> - ? ? ? unsigned int ? ?tAR; ?/* ND_ALE low to ND_nRE low delay */
>>>>> -};
>>>>> -
>>>>> -struct pxa3xx_nand_cmdset {
>>>>> - ? ? ? uint16_t ? ? ? ?read1;
>>>>> - ? ? ? uint16_t ? ? ? ?read2;
>>>>> - ? ? ? uint16_t ? ? ? ?program;
>>>>> - ? ? ? uint16_t ? ? ? ?read_status;
>>>>> - ? ? ? uint16_t ? ? ? ?read_id;
>>>>> - ? ? ? uint16_t ? ? ? ?erase;
>>>>> - ? ? ? uint16_t ? ? ? ?reset;
>>>>> - ? ? ? uint16_t ? ? ? ?lock;
>>>>> - ? ? ? uint16_t ? ? ? ?unlock;
>>>>> - ? ? ? uint16_t ? ? ? ?lock_status;
>>>>> -};
>>>>> -
>>>>> -struct pxa3xx_nand_flash {
>>>>> - ? ? ? const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
>>>>> - ? ? ? const struct pxa3xx_nand_cmdset *cmdset;
>>>>> -
>>>>> - ? ? ? uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */
>>>>> - ? ? ? uint32_t page_size; ? ? /* Page size in bytes (PAGE_SZ) */
>>>>> - ? ? ? uint32_t flash_width; ? /* Width of Flash memory (DWIDTH_M) */
>>>>> - ? ? ? uint32_t dfc_width; ? ? /* Width of flash controller(DWIDTH_C) */
>>>>> - ? ? ? uint32_t num_blocks; ? ?/* Number of physical blocks in Flash */
>>>>> - ? ? ? uint32_t chip_id;
>>>>> -};
>>>>> -
>>>>
>>>> So does this prevent board code from defining their own timing and etc?
>>>
>>> No, platform could define its own timing. If there is definition for
>>> the same chip,
>>> driver would choose the one from platform definition first.
>>>
>>
>> I'm seeing pxa3xx_nand_flash being referenced in pxa3xx_nand_platform_data
>> below, though?
>>
>> struct pxa3xx_nand_platform_data {
>>
>> ? ? ?......
>>
>> ? ? ? ?const struct pxa3xx_nand_flash * ? ? ? ?flash;
>> ? ? ? ?size_t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?num_flash;
>> };
>>
>
> Yes, platform could define its own pxa3xx_nand_flash structure in its
> own code, and pass the structure to let driver know.
>

I'm actually quite confused here. Did you ever try build a kernel with
platform defined flash info?


From adrian.wenl at gmail.com  Fri Jun 18 04:16:26 2010
From: adrian.wenl at gmail.com (Lei Wen)
Date: Fri, 18 Jun 2010 16:16:26 +0800
Subject: [PATCH 03/25] pxa3xx_nand: remove the flash info in driver 
	structure
In-Reply-To: <AANLkTilnlE7hl4FKo5qRJ4PeTCuxA3Mfm13eedGPehrk@mail.gmail.com>
References: <AANLkTimbCSM3Kk-Mq3MhRDyhHAaERR-dXhtuplauB3ki@mail.gmail.com>
	<AANLkTilnlE7hl4FKo5qRJ4PeTCuxA3Mfm13eedGPehrk@mail.gmail.com>
Message-ID: <AANLkTikT1hzTe4nEKj5n0cay0Q_277GlygXftYOlHI0q@mail.gmail.com>

On Fri, Jun 18, 2010 at 2:40 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 1:33 PM, Haojian Zhuang
> <haojian.zhuang at gmail.com> wrote:
>> From 643765e6ae0f37902321f31e14b565896217dd3a Mon Sep 17 00:00:00 2001
>> From: Lei Wen <leiwen at marvell.com>
>> Date: Wed, 2 Jun 2010 21:54:33 +0800
>> Subject: [PATCH 03/25] pxa3xx_nand: remove the flash info in driver structure
>>
>> After probe, all info already transfer to driver structure.
>> There is no need to keep the original flash info.
>> So that we could safely free the flash info in memory, which may grows
>> larger when more flash is suported.
>>
>
> Some of the changes should be separated from my POV? Like the
> change to oob_size, and pxa3xx_nand_resume?
>

This patch is only servered as the prepraration of latter patch
seris... So hard to seperate them...


From mika.westerberg at iki.fi  Fri Jun 18 04:33:55 2010
From: mika.westerberg at iki.fi (Mika Westerberg)
Date: Fri, 18 Jun 2010 11:33:55 +0300
Subject: invalid address for enqueue_task
In-Reply-To: <201006171230.38101.alexander.stein@systec-electronic.com>
References: <201006171230.38101.alexander.stein@systec-electronic.com>
Message-ID: <20100618083355.GA28107@gw.healthdatacare.com>

On Thu, Jun 17, 2010 at 12:30:37PM +0200, Alexander Stein wrote:
> 
> After doing some research I found out that sched_class inside struct_task has 
> been modified to some bogus address so sched_class->enqueue_task 
> (kernel/sched.c:1886) jumps to some invalid address.

While I cannot help you with this specific problem, I think it is
worth to mention that this kind of bugs are exactly where kdump
might prove to be useful. As now you have a snapshot of the system
during the time of the crash, you might be able to dig out the cause
using tools like gdb and crash[1]

Currently kdump patches are not in mainline but if you decide to
take that route, they can be found by searching this ML and I can
provide assistance for setting them up.

Regards,
MW

[1] http://people.redhat.com/~anderson/

( crash doesn't have ARM support but I have experimental patches
  to make it work on ARM as well )


From adrian.wenl at gmail.com  Fri Jun 18 04:44:43 2010
From: adrian.wenl at gmail.com (Lei Wen)
Date: Fri, 18 Jun 2010 16:44:43 +0800
Subject: [PATCH 01/25] pxa3xx_nand: condense the flash definition
In-Reply-To: <AANLkTinwlsrxvjHyEs1IAwaw-8GXYN2lVrUOtYp0C52n@mail.gmail.com>
References: <AANLkTil1FnPkGS7l6W0HWeXyOxXzWbZkvFWY4jJF_I_A@mail.gmail.com>
	<AANLkTinOsQ8AcH-As91CRqrEQVnXdsm_CmFQgyj7gI1_@mail.gmail.com>
	<AANLkTim9O5kuGzvQoB65fWDr3Bi9siiVBMCPx6heqZjd@mail.gmail.com>
	<AANLkTimGzVtuJuuxipim-f6UhdK287EjF41UlhdKCWRM@mail.gmail.com>
	<AANLkTindDgsvPK-ZZsyB2cdsrh0IyykBuhgStuwvyIdg@mail.gmail.com>
	<AANLkTinwlsrxvjHyEs1IAwaw-8GXYN2lVrUOtYp0C52n@mail.gmail.com>
Message-ID: <AANLkTikDXl0XwO_08T87l8jY-Lf_uNZDfOjrMfsnuCto@mail.gmail.com>

On Fri, Jun 18, 2010 at 4:14 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 4:10 PM, Lei Wen <adrian.wenl at gmail.com> wrote:
>> On Fri, Jun 18, 2010 at 4:00 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>>>>>> -struct pxa3xx_nand_timing {
>>>>>> - ? ? ? unsigned int ? ?tCH; ?/* Enable signal hold time */
>>>>>> - ? ? ? unsigned int ? ?tCS; ?/* Enable signal setup time */
>>>>>> - ? ? ? unsigned int ? ?tWH; ?/* ND_nWE high duration */
>>>>>> - ? ? ? unsigned int ? ?tWP; ?/* ND_nWE pulse time */
>>>>>> - ? ? ? unsigned int ? ?tRH; ?/* ND_nRE high duration */
>>>>>> - ? ? ? unsigned int ? ?tRP; ?/* ND_nRE pulse width */
>>>>>> - ? ? ? unsigned int ? ?tR; ? /* ND_nWE high to ND_nRE low for read */
>>>>>> - ? ? ? unsigned int ? ?tWHR; /* ND_nWE high to ND_nRE low for status read */
>>>>>> - ? ? ? unsigned int ? ?tAR; ?/* ND_ALE low to ND_nRE low delay */
>>>>>> -};
>>>>>> -
>>>>>> -struct pxa3xx_nand_cmdset {
>>>>>> - ? ? ? uint16_t ? ? ? ?read1;
>>>>>> - ? ? ? uint16_t ? ? ? ?read2;
>>>>>> - ? ? ? uint16_t ? ? ? ?program;
>>>>>> - ? ? ? uint16_t ? ? ? ?read_status;
>>>>>> - ? ? ? uint16_t ? ? ? ?read_id;
>>>>>> - ? ? ? uint16_t ? ? ? ?erase;
>>>>>> - ? ? ? uint16_t ? ? ? ?reset;
>>>>>> - ? ? ? uint16_t ? ? ? ?lock;
>>>>>> - ? ? ? uint16_t ? ? ? ?unlock;
>>>>>> - ? ? ? uint16_t ? ? ? ?lock_status;
>>>>>> -};
>>>>>> -
>>>>>> -struct pxa3xx_nand_flash {
>>>>>> - ? ? ? const struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
>>>>>> - ? ? ? const struct pxa3xx_nand_cmdset *cmdset;
>>>>>> -
>>>>>> - ? ? ? uint32_t page_per_block;/* Pages per block (PG_PER_BLK) */
>>>>>> - ? ? ? uint32_t page_size; ? ? /* Page size in bytes (PAGE_SZ) */
>>>>>> - ? ? ? uint32_t flash_width; ? /* Width of Flash memory (DWIDTH_M) */
>>>>>> - ? ? ? uint32_t dfc_width; ? ? /* Width of flash controller(DWIDTH_C) */
>>>>>> - ? ? ? uint32_t num_blocks; ? ?/* Number of physical blocks in Flash */
>>>>>> - ? ? ? uint32_t chip_id;
>>>>>> -};
>>>>>> -
>>>>>
>>>>> So does this prevent board code from defining their own timing and etc?
>>>>
>>>> No, platform could define its own timing. If there is definition for
>>>> the same chip,
>>>> driver would choose the one from platform definition first.
>>>>
>>>
>>> I'm seeing pxa3xx_nand_flash being referenced in pxa3xx_nand_platform_data
>>> below, though?
>>>
>>> struct pxa3xx_nand_platform_data {
>>>
>>> ? ? ?......
>>>
>>> ? ? ? ?const struct pxa3xx_nand_flash * ? ? ? ?flash;
>>> ? ? ? ?size_t ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?num_flash;
>>> };
>>>
>>
>> Yes, platform could define its own pxa3xx_nand_flash structure in its
>> own code, and pass the structure to let driver know.
>>
>
> I'm actually quite confused here. Did you ever try build a kernel with
> platform defined flash info?
>

I haven't tried to build one platform code with flash definition
yet... My fault...
I would correct this error in .h file.


From adrian.wenl at gmail.com  Fri Jun 18 04:51:30 2010
From: adrian.wenl at gmail.com (Lei Wen)
Date: Fri, 18 Jun 2010 16:51:30 +0800
Subject: [PATCH 06/25] pxa3xx_nand: unify prepare command
In-Reply-To: <AANLkTinNqtnL3LRFsPuUQXcTnRda0_B059bRLGlJuzlh@mail.gmail.com>
References: <AANLkTilhattkx7AiyG-R4zbWSZ3-qkPIM6VhyFW4lk4D@mail.gmail.com>
	<AANLkTinNqtnL3LRFsPuUQXcTnRda0_B059bRLGlJuzlh@mail.gmail.com>
Message-ID: <AANLkTikqhHK2snjdEb1jDURueQm5WclZ3xnGNsgew08X@mail.gmail.com>

On Fri, Jun 18, 2010 at 2:52 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 1:34 PM, Haojian Zhuang
> <haojian.zhuang at gmail.com> wrote:
>> From ac05ddc3c13d2b80b243e91cba9922572841f34a Mon Sep 17 00:00:00 2001
>> From: Lei Wen <leiwen at marvell.com>
>> Date: Mon, 22 Mar 2010 12:04:22 +0800
>> Subject: [PATCH 06/25] pxa3xx_nand: unify prepare command
>>
>> Make the interface simpler which could make both debug
>> and enhancement easier.
>
> What is the benefit of combining them into one big several pages lengthy
> function? I dislike lengthy function :-/

The reason why I combine those function is to make a common patch for
all command to quick
identify error during driver development and make code more robust...
Another reason is to share some common setting for different command,
and make code more concise.


From adrian.wenl at gmail.com  Fri Jun 18 04:56:24 2010
From: adrian.wenl at gmail.com (Lei Wen)
Date: Fri, 18 Jun 2010 16:56:24 +0800
Subject: [PATCH 08/25] mmp: add nand support to pxa168
In-Reply-To: <AANLkTilOIds0GEPmTWgi_y7UzJT4g9qx6iAtDJDgVxWu@mail.gmail.com>
References: <AANLkTinxMQjZIG4G1d9WVOiUX8-zHjTuTc1eRuInDRGW@mail.gmail.com>
	<AANLkTilOIds0GEPmTWgi_y7UzJT4g9qx6iAtDJDgVxWu@mail.gmail.com>
Message-ID: <AANLkTimzn6YyOX8CuCJ2UbchRtHjrrhWxkAL_s4gZovG@mail.gmail.com>

On Fri, Jun 18, 2010 at 2:59 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 1:34 PM, Haojian Zhuang
> <haojian.zhuang at gmail.com> wrote:
>> From 55adf11cb4ba8ba0b88148c9bce0cc08f94b97bd Mon Sep 17 00:00:00 2001
>> From: Lei Wen <leiwen at marvell.com>
>> Date: Mon, 31 May 2010 14:57:49 +0800
>> Subject: [PATCH 08/25] mmp: add nand support to pxa168
>>
>> Signed-off-by: Lei Wen <leiwen at marvell.com>
>> ---
>> ?arch/arm/configs/pxa168_defconfig | ? ?9 ++++++++-
>> ?drivers/mtd/nand/Kconfig ? ? ? ? ?| ? ?2 +-
>> ?2 files changed, 9 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/configs/pxa168_defconfig
>> b/arch/arm/configs/pxa168_defconfig
>> index 113511f..a01ea99 100644
>> --- a/arch/arm/configs/pxa168_defconfig
>> +++ b/arch/arm/configs/pxa168_defconfig
>> @@ -438,7 +438,14 @@ CONFIG_EXTRA_FIRMWARE=""
>> ?# CONFIG_DEBUG_DEVRES is not set
>> ?# CONFIG_SYS_HYPERVISOR is not set
>> ?# CONFIG_CONNECTOR is not set
>> -# CONFIG_MTD is not set
>> +CONFIG_MTD=y
>> +CONFIG_MTD_PARTITIONS=y
>> +CONFIG_MTD_CMDLINE_PARTS=y
>> +CONFIG_MTD_CHAR=y
>> +CONFIG_MTD_BLKDEVS=y
>> +CONFIG_MTD_BLOCK=y
>> +CONFIG_MTD_NAND=y
>> +CONFIG_MTD_NAND_PXA3xx=y
>> ?# CONFIG_PARPORT is not set
>> ?# CONFIG_BLK_DEV is not set
>> ?# CONFIG_MISC_DEVICES is not set
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index 9a35d92..0d29b5d 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -394,7 +394,7 @@ endchoice
>>
>> ?config MTD_NAND_PXA3xx
>> ? ? ? ?tristate "Support for NAND flash devices on PXA3xx"
>> - ? ? ? depends on MTD_NAND && (PXA3xx || ARCH_MMP)
>> + ? ? ? depends on MTD_NAND && PLAT_PXA
>
> I'd prefer this not being changed, as pxa3xx_nand isn't applicable to
> pxa25x/pxa27x.
>

I see... I would remove that change


From ben-linux at fluff.org  Fri Jun 18 05:00:10 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 18 Jun 2010 10:00:10 +0100
Subject: Several questions regarding ARCH_S3C2410
In-Reply-To: <AANLkTimPk6mtyB57jXuAq1ugQseS655OCPEuP9-qZYoT@mail.gmail.com>
References: <AANLkTimPk6mtyB57jXuAq1ugQseS655OCPEuP9-qZYoT@mail.gmail.com>
Message-ID: <20100618090010.GX3498@trinity.fluff.org>

On Fri, Jun 18, 2010 at 11:43:37AM +0800, Eric Miao wrote:
> Hi Ben,
> 
> While working towards a unified kernel, I found that ARCH_S3C2410 actually
> includes multiple mach-* already.
> 
> linux-2.6$ git grep "ARCH_S3C2410" arch/arm/Makefile
> arch/arm/Makefile:machine-$(CONFIG_ARCH_S3C2410)	:= s3c2410 s3c2400
> s3c2412 s3c2416 s3c2440 s3c2443
> 
> There are several questions though:
> 
> 1. It looks like only s3c2410 is significant, so all the common definitions
>    like PHYS_OFFSET are actually same across all mach-s3c24* (except for
>    s3c24a0) ? Yet I've found arch/arm/mach-s3c2400/include/mach/memory.h,
>    where a different PHYS_OFFSET is defined, just feel a bit confused.

You can safely ignore the s3c24a0 for the moment, there's no-one interested
in actually getting it submitted.
 
> 2. So except for s3c24a0, theretically, it's possible to combine all these
>    mach into something mach-s3c24xx?

Theoretically yes, practically leave it alone.

> 3. When trying building of s3c2410_defconfig, there are a lot complaints
>    about re-definitions of {in,out}[s]{b,w,l}.  Taking a look into io.h,
>    I'm wondering if it's possible to use those definitions in asm/io.h?
>    (possibly with a customized __io())
> 
> In file included from linux-2.6/include/linux/scatterlist.h:8,
>                  from linux-2.6/include/linux/dma-mapping.h:7,
>                  from linux-2.6/include/linux/dmaengine.h:26,
>                  from linux-2.6/include/linux/skbuff.h:30,
>                  from linux-2.6/lib/kobject_uevent.c:24:
> linux-2.6/arch/arm/include/asm/io.h:137: warning: "outb" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:196: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:138: warning: "outw" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:197: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:140: warning: "outl" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:198: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:143: warning: "inb" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:193: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:144: warning: "inw" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:194: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:146: warning: "inl" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:195: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:149: warning: "outsb" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:207: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:150: warning: "outsw" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:208: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:151: warning: "outsl" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:209: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:153: warning: "insb" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:203: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:154: warning: "insw" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:204: note: this is
> the location of the previous definition
> linux-2.6/arch/arm/include/asm/io.h:155: warning: "insl" redefined
> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:205: note: this is
> the location of the previous definition

that's something for you to sort out.

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From ben-linux at fluff.org  Fri Jun 18 05:00:42 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Fri, 18 Jun 2010 10:00:42 +0100
Subject: Several questions regarding ARCH_S3C2410
In-Reply-To: <AANLkTilbEYR28lrVBAIXXuJ6sEf5uCp4Tpr7wriBZLj3@mail.gmail.com>
References: <AANLkTimPk6mtyB57jXuAq1ugQseS655OCPEuP9-qZYoT@mail.gmail.com>
	<AANLkTilbEYR28lrVBAIXXuJ6sEf5uCp4Tpr7wriBZLj3@mail.gmail.com>
Message-ID: <20100618090042.GY3498@trinity.fluff.org>

On Fri, Jun 18, 2010 at 04:44:59PM +0900, Kyungmin Park wrote:
> CCing Mr. Kim

not sure it really needs him to be involved at-all

-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From adrian.wenl at gmail.com  Fri Jun 18 05:15:20 2010
From: adrian.wenl at gmail.com (Lei Wen)
Date: Fri, 18 Jun 2010 17:15:20 +0800
Subject: [PATCH 02/25] pxa3xx_nand: introduce common timing to reduce read
	id times
In-Reply-To: <AANLkTikDDFYY65l5YYGW3a0O2bWDyKRO6VRb15aaFtF7@mail.gmail.com>
References: <AANLkTim1qcVoqSS7T8bE0Vsu6phC2iY_Ok671WYHcD0z@mail.gmail.com>
	<AANLkTil6QDRdh3s63J9Mm-B1qjMcnYjEEm-W5lC1NXVb@mail.gmail.com>
	<AANLkTikbzXgwMvnNVRkcOO-9El9hmAXhKZK_dFgStbwY@mail.gmail.com>
	<AANLkTikDDFYY65l5YYGW3a0O2bWDyKRO6VRb15aaFtF7@mail.gmail.com>
Message-ID: <AANLkTil6D3Cijy1JZ3aQLBGBfi99zOGDy5Xl8OmY_T_8@mail.gmail.com>

On Fri, Jun 18, 2010 at 4:12 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>>>> - ? ? ? if (f->page_size != 2048 && f->page_size != 512)
>>>> - ? ? ? ? ? ? ? return -EINVAL;
>>>> -
>>>> - ? ? ? if (f->flash_width != 16 && f->flash_width != 8)
>>>> - ? ? ? ? ? ? ? return -EINVAL;
>>>> -
>>>
>>> I do think these are sanity check, that's useful to prevent incorrectly defined
>>> data (esp. coming from board code). Can we define the loose flash type as:
>>>
>>>> ?static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
>>>> + ? ? ? { ?0x0000, ? 0, ? ?512, ?8, ?8, ? ?0, &timing[0], },
>>>> + ? ? ? { 0x46ec, ?32, ?512, 16, 16, 4096, &timing[1], },
>>>> + ? ? ? { 0xdaec, ?64, 2048, ?8, ?8, 2048, &timing[1], },
>>>
>>> with a comment of /* default flash type to detect ID */?
>>>
>>> My understanding is the minimum requirement to detect the NAND ID is a
>>> loose timing and 512 small page, 8-bit wide bus, so with a chip_id being
>>> 0x0000, that should be enough to tell it's a special flash type to detect ID.
>>
>> There is no need to add the flash page size and bus width for the
>> common timing, or loose timing...
>> For the chip identification only need reset and read id command, and
>> reset and read id command only care
>> for the first command in NDCB0 and the timing setting in NDTR0CS0 and
>> NDTR1CS0, the page size is not useful
>> here and could make confussion if give such definition...
>
> I know, but I'd like to keep the checking of page_size, and flash_width,
> if you take a look into the rest of the code how much it is assumed that
> page_size being either 2048 or 512, flash_width being 8 or 16, you'll
> know why such an error checking here is mandatory actually.

I know that the configure_flash function need to check page_size &
flash_width to set the
ndcr. But what the setting would not affect the reset/read id result anyway...
For there is some chip has the same bytes in the first two bytes, I
choose to always read out
4 bytes data when send read id command in latter patch of this patch set...

>
>>>
>>>> ? ? ? ?/* calculate flash information */
>>>> ? ? ? ?info->oob_size = (f->page_size == 2048) ? 64 : 16;
>>>> ? ? ? ?info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
>>>> @@ -976,36 +973,27 @@ static int pxa3xx_nand_detect_flash(struct
>>>> pxa3xx_nand_info *info,
>>>> ? ? ? ? ? ? ? ?if (pxa3xx_nand_detect_config(info) == 0)
>>>> ? ? ? ? ? ? ? ? ? ? ? ?return 0;
>>>>
>>>> - ? ? ? for (i = 0; i<pdata->num_flash; ++i) {
>>>> - ? ? ? ? ? ? ? f = pdata->flash + i;
>>>> -
>>>> - ? ? ? ? ? ? ? if (pxa3xx_nand_config_flash(info, f))
>>>> - ? ? ? ? ? ? ? ? ? ? ? continue;
>>>> -
>>>> - ? ? ? ? ? ? ? if (__readid(info, &id))
>>>> - ? ? ? ? ? ? ? ? ? ? ? continue;
>>>> -
>>>> - ? ? ? ? ? ? ? if (id == f->chip_id)
>>>> - ? ? ? ? ? ? ? ? ? ? ? return 0;
>>>> - ? ? ? }
>>>> -
>>>> - ? ? ? for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
>>>> -
>>>> - ? ? ? ? ? ? ? f = &builtin_flash_types[i];
>>>> -
>>>> - ? ? ? ? ? ? ? if (pxa3xx_nand_config_flash(info, f))
>>>> - ? ? ? ? ? ? ? ? ? ? ? continue;
>>>> -
>>>> - ? ? ? ? ? ? ? if (__readid(info, &id))
>>>> - ? ? ? ? ? ? ? ? ? ? ? continue;
>>>> -
>>>> - ? ? ? ? ? ? ? if (id == f->chip_id)
>>>> + ? ? ? f = &builtin_flash_types[0];
>>>> + ? ? ? pxa3xx_nand_config_flash(info, f);
>>>> + ? ? ? if (__readid(info, &id))
>>>> + ? ? ? ? ? ? ? goto fail_detect;
>>>> +
>>>> + ? ? ? for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
>>>> + ? ? ? ? ? ? ? if (i < pdata->num_flash)
>>>> + ? ? ? ? ? ? ? ? ? ? ? f = pdata->flash + i;
>>>> + ? ? ? ? ? ? ? else
>>>> + ? ? ? ? ? ? ? ? ? ? ? f = &builtin_flash_types[i - pdata->num_flash + 1];
>>>
>>> This looks a bit tricky and difficult to read, can you improve the
>>> readability here?
>>
>> The chip id identification logic here is changed in latter patch in
>> this patch set...
>> If from the last patch of view, does this part looks better?
>>
>
> Not sure, I'd rather this being separated into two loops if that helps
> readability.
>
>>>
>>>> + ? ? ? ? ? ? ? if (f->chip_id == id) {
>>>> + ? ? ? ? ? ? ? ? ? ? ? dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
>>>> + ? ? ? ? ? ? ? ? ? ? ? pxa3xx_nand_config_flash(info, f);
>>>> ? ? ? ? ? ? ? ? ? ? ? ?return 0;
>>>> + ? ? ? ? ? ? ? }
>>>> ? ? ? ?}
>>>>
>>>> ? ? ? ?dev_warn(&info->pdev->dev,
>>>> - ? ? ? ? ? ? ? ?"failed to detect configured nand flash; found %04x instead of\n",
>>>> + ? ? ? ? ? ? ? ? ? ? ? "failed to detect configured nand flash; found %04x instead of\n",
>>>> ? ? ? ? ? ? ? ? id);
>>>> +fail_detect:
>>>> ? ? ? ?return -ENODEV;
>>>> ?}
>>>>
>>>
>>> I'm generally OK with the idea.
>>>
>> Best regards,
>> Lei
>>
>


From eric.y.miao at gmail.com  Fri Jun 18 05:15:23 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 17:15:23 +0800
Subject: Several questions regarding ARCH_S3C2410
In-Reply-To: <20100618090010.GX3498@trinity.fluff.org>
References: <AANLkTimPk6mtyB57jXuAq1ugQseS655OCPEuP9-qZYoT@mail.gmail.com> 
	<20100618090010.GX3498@trinity.fluff.org>
Message-ID: <AANLkTin8g1jSGvju_-7rctjw0PTuunSKDivS1_yxp_lS@mail.gmail.com>

On Fri, Jun 18, 2010 at 5:00 PM, Ben Dooks <ben-linux at fluff.org> wrote:
> On Fri, Jun 18, 2010 at 11:43:37AM +0800, Eric Miao wrote:
>> Hi Ben,
>>
>> While working towards a unified kernel, I found that ARCH_S3C2410 actually
>> includes multiple mach-* already.
>>
>> linux-2.6$ git grep "ARCH_S3C2410" arch/arm/Makefile
>> arch/arm/Makefile:machine-$(CONFIG_ARCH_S3C2410) ? ? ?:= s3c2410 s3c2400
>> s3c2412 s3c2416 s3c2440 s3c2443
>>
>> There are several questions though:
>>
>> 1. It looks like only s3c2410 is significant, so all the common definitions
>> ? ?like PHYS_OFFSET are actually same across all mach-s3c24* (except for
>> ? ?s3c24a0) ? Yet I've found arch/arm/mach-s3c2400/include/mach/memory.h,
>> ? ?where a different PHYS_OFFSET is defined, just feel a bit confused.
>
> You can safely ignore the s3c24a0 for the moment, there's no-one interested
> in actually getting it submitted.

Grrr... indeed.Looking into mach-s3c24a0, it's almost empty except for some
header files.

>
>> 2. So except for s3c24a0, theretically, it's possible to combine all these
>> ? ?mach into something mach-s3c24xx?
>
> Theoretically yes, practically leave it alone.
>
>> 3. When trying building of s3c2410_defconfig, there are a lot complaints
>> ? ?about re-definitions of {in,out}[s]{b,w,l}. ?Taking a look into io.h,
>> ? ?I'm wondering if it's possible to use those definitions in asm/io.h?
>> ? ?(possibly with a customized __io())
>>
>> In file included from linux-2.6/include/linux/scatterlist.h:8,
>> ? ? ? ? ? ? ? ? ?from linux-2.6/include/linux/dma-mapping.h:7,
>> ? ? ? ? ? ? ? ? ?from linux-2.6/include/linux/dmaengine.h:26,
>> ? ? ? ? ? ? ? ? ?from linux-2.6/include/linux/skbuff.h:30,
>> ? ? ? ? ? ? ? ? ?from linux-2.6/lib/kobject_uevent.c:24:
>> linux-2.6/arch/arm/include/asm/io.h:137: warning: "outb" redefined
>> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:196: note: this is
>> the location of the previous definition
>> linux-2.6/arch/arm/include/asm/io.h:138: warning: "outw" redefined
>> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:197: note: this is
>> the location of the previous definition
>> linux-2.6/arch/arm/include/asm/io.h:140: warning: "outl" redefined
>> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:198: note: this is
>> the location of the previous definition
>> linux-2.6/arch/arm/include/asm/io.h:143: warning: "inb" redefined
>> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:193: note: this is
>> the location of the previous definition
>> linux-2.6/arch/arm/include/asm/io.h:144: warning: "inw" redefined
>> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:194: note: this is
>> the location of the previous definition
>> linux-2.6/arch/arm/include/asm/io.h:146: warning: "inl" redefined
>> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:195: note: this is
>> the location of the previous definition
>> linux-2.6/arch/arm/include/asm/io.h:149: warning: "outsb" redefined
>> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:207: note: this is
>> the location of the previous definition
>> linux-2.6/arch/arm/include/asm/io.h:150: warning: "outsw" redefined
>> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:208: note: this is
>> the location of the previous definition
>> linux-2.6/arch/arm/include/asm/io.h:151: warning: "outsl" redefined
>> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:209: note: this is
>> the location of the previous definition
>> linux-2.6/arch/arm/include/asm/io.h:153: warning: "insb" redefined
>> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:203: note: this is
>> the location of the previous definition
>> linux-2.6/arch/arm/include/asm/io.h:154: warning: "insw" redefined
>> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:204: note: this is
>> the location of the previous definition
>> linux-2.6/arch/arm/include/asm/io.h:155: warning: "insl" redefined
>> linux-2.6/arch/arm/mach-s3c2410/include/mach/io.h:205: note: this is
>> the location of the previous definition
>
> that's something for you to sort out.
>

Come on, you must be kidding me. I have no idea how that crap was
being formed :-)


From eric.y.miao at gmail.com  Fri Jun 18 05:19:59 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 17:19:59 +0800
Subject: [PATCH 02/25] pxa3xx_nand: introduce common timing to reduce read
	id times
In-Reply-To: <AANLkTil6D3Cijy1JZ3aQLBGBfi99zOGDy5Xl8OmY_T_8@mail.gmail.com>
References: <AANLkTim1qcVoqSS7T8bE0Vsu6phC2iY_Ok671WYHcD0z@mail.gmail.com> 
	<AANLkTil6QDRdh3s63J9Mm-B1qjMcnYjEEm-W5lC1NXVb@mail.gmail.com> 
	<AANLkTikbzXgwMvnNVRkcOO-9El9hmAXhKZK_dFgStbwY@mail.gmail.com> 
	<AANLkTikDDFYY65l5YYGW3a0O2bWDyKRO6VRb15aaFtF7@mail.gmail.com> 
	<AANLkTil6D3Cijy1JZ3aQLBGBfi99zOGDy5Xl8OmY_T_8@mail.gmail.com>
Message-ID: <AANLkTimeJYwret1ZlEHaX_-T14qB3WteQwpn9y7_1Zo9@mail.gmail.com>

On Fri, Jun 18, 2010 at 5:15 PM, Lei Wen <adrian.wenl at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 4:12 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>>>>> - ? ? ? if (f->page_size != 2048 && f->page_size != 512)
>>>>> - ? ? ? ? ? ? ? return -EINVAL;
>>>>> -
>>>>> - ? ? ? if (f->flash_width != 16 && f->flash_width != 8)
>>>>> - ? ? ? ? ? ? ? return -EINVAL;
>>>>> -
>>>>
>>>> I do think these are sanity check, that's useful to prevent incorrectly defined
>>>> data (esp. coming from board code). Can we define the loose flash type as:
>>>>
>>>>> ?static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
>>>>> + ? ? ? { ?0x0000, ? 0, ? ?512, ?8, ?8, ? ?0, &timing[0], },
>>>>> + ? ? ? { 0x46ec, ?32, ?512, 16, 16, 4096, &timing[1], },
>>>>> + ? ? ? { 0xdaec, ?64, 2048, ?8, ?8, 2048, &timing[1], },
>>>>
>>>> with a comment of /* default flash type to detect ID */?
>>>>
>>>> My understanding is the minimum requirement to detect the NAND ID is a
>>>> loose timing and 512 small page, 8-bit wide bus, so with a chip_id being
>>>> 0x0000, that should be enough to tell it's a special flash type to detect ID.
>>>
>>> There is no need to add the flash page size and bus width for the
>>> common timing, or loose timing...
>>> For the chip identification only need reset and read id command, and
>>> reset and read id command only care
>>> for the first command in NDCB0 and the timing setting in NDTR0CS0 and
>>> NDTR1CS0, the page size is not useful
>>> here and could make confussion if give such definition...
>>
>> I know, but I'd like to keep the checking of page_size, and flash_width,
>> if you take a look into the rest of the code how much it is assumed that
>> page_size being either 2048 or 512, flash_width being 8 or 16, you'll
>> know why such an error checking here is mandatory actually.
>
> I know that the configure_flash function need to check page_size &
> flash_width to set the
> ndcr. But what the setting would not affect the reset/read id result anyway...
> For there is some chip has the same bytes in the first two bytes, I
> choose to always read out
> 4 bytes data when send read id command in latter patch of this patch set...
>

My understanding is that NAND READID will at least work with the assumption
of 512bytes/page and 8-bit wide bus, no matter how the NAND chips are
connected. (unless some one comes up with a insane design of using multiple
interlaced NAND chips of different types).

Again, assume the NAND controller is not initialized (register values being
garbage or all zero-ed), do you still think you can read out the ID without
letting it know the page size, bus width and etc?


From eric at eukrea.com  Fri Jun 18 05:29:10 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Fri, 18 Jun 2010 11:29:10 +0200
Subject: [PATCH 1/2] net/fec: clean suspend/resume
Message-ID: <1276853351-20790-1-git-send-email-eric@eukrea.com>

Commit 59d4289b83b11379d867e2f7146904b19cc96404 converted fec to dev_pm_ops but
didn't update the suspend/resume functions thus leading to the following warning :
"initialization from incompatible pointer type" when CONFIG_PM is set.

This patch also fixe a few indentation and style around CONFIG_PM area.

Signed-off-by: Eric B?nard <eric at eukrea.com>
To: netdev at vger.kernel.org
Cc: davem at davemloft.net
Cc: amit.kucheria at canonical.com
Cc: s.hauer at pengutronix.de
Cc: linux-arm-kernel at lists.infradead.org
---
 drivers/net/fec.c |   30 ++++++++++++------------------
 1 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index a3cae4e..b4afd7a 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1360,11 +1360,10 @@ fec_drv_remove(struct platform_device *pdev)
 }
 
 #ifdef CONFIG_PM
-
 static int
-fec_suspend(struct platform_device *dev, pm_message_t state)
+fec_suspend(struct device *dev)
 {
-	struct net_device *ndev = platform_get_drvdata(dev);
+	struct net_device *ndev = dev_get_drvdata(dev);
 	struct fec_enet_private *fep;
 
 	if (ndev) {
@@ -1377,9 +1376,9 @@ fec_suspend(struct platform_device *dev, pm_message_t state)
 }
 
 static int
-fec_resume(struct platform_device *dev)
+fec_resume(struct device *dev)
 {
-	struct net_device *ndev = platform_get_drvdata(dev);
+	struct net_device *ndev = dev_get_drvdata(dev);
 	struct fec_enet_private *fep;
 
 	if (ndev) {
@@ -1399,23 +1398,18 @@ static const struct dev_pm_ops fec_pm_ops = {
 	.poweroff	= fec_suspend,
 	.restore	= fec_resume,
 };
-
-#define FEC_PM_OPS (&fec_pm_ops)
-
-#else /* !CONFIG_PM */
-
-#define FEC_PM_OPS NULL
-
-#endif /* !CONFIG_PM */
+#endif
 
 static struct platform_driver fec_driver = {
 	.driver	= {
-		.name    = "fec",
-		.owner	 = THIS_MODULE,
-		.pm		 = FEC_PM_OPS,
+		.name	= "fec",
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &fec_pm_ops,
+#endif
 	},
-	.probe   = fec_probe,
-	.remove  = __devexit_p(fec_drv_remove),
+	.probe	= fec_probe,
+	.remove	= __devexit_p(fec_drv_remove),
 };
 
 static int __init
-- 
1.6.3.3



From kgene.kim at samsung.com  Fri Jun 18 05:50:58 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 18 Jun 2010 18:50:58 +0900
Subject: [PATCH] S5PV210 Correct clock source control register properties
In-Reply-To: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>
References: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <005401cb0ecb$c3f16c00$4bd44400$%kim@samsung.com>

MyungJoo Ham wrote:
> 
> The clock source controls (struct clksrc_clk) have been often accessing
> CLK_GATE_IPx, which are for clock gating and are accessed by each clock
> as well as the clock source. This duplicated clock issue may incur
> lockup problems when there are two modules accessing the same clock with
> different names.
> 
Could you please explain further about the above the statement " accessed by
each clock as well as the clock source"

> Besides, the clock source control is supposed to control (setting values
> of MASK, SRC, DIV), not to turn on/off individual clock.
> 
That is not quite true. Only S5PV210/S5PC110 have the gate for the clock mux.
S5P6440 and S5PC100, for instance, do not have a gate for the output for
_just_ the clock mux. And the reason why the Clock Mux Gate is provide for
the mux is explained in Section 3.4 of the user manual.

> Another point is that there are registers (CLK_SRC_MASK0/1) specialized
> for masking clock source control in S5PV210/S5PC110 according to the
> user manual (rev 20100201).
> 
> Therefore, accessing CLK_SRC_MASK0/1 (rather than accessing
> CLK_GATE_IPx) for the clock source control is safer and fits to the
> semantics of S5PV210/S5PC110 registers. And fortuneatly, each clock
> source defined in clock.c has corresponding bit at CLK_SRC_MASK0/1
> except for MFC, G2D, and G3D.
> 
Can you please explain how the use CLK_SRC_MASKx makes it safer. The reason
why MFC, G2D and G3D do not have a corresponding bit in CLK_SRC_MASKx is
mentioned in Section 3.4 of the user manual.

Let me know your opinion.

> In this patch,
> 
> - DAC, HDMI, AUDIO 0/1/2, UCLK(uart) 0/1/2/3, MIXER, FIMC 0/1/2,
> FIMC, MMC 0/1/2/3, CSIS, SPI 0/1, PWI, and PWM clock sources are
> modified to use CLK_SRC_MASK0/1, which were using CLK_GATE_IPx.
> 
> - CAM 0/1 did not have enable/disable control. They now access
>   CLK_SRC_MASK0.
> 
> - MFC, G3D, G2D were using CLK_GATE_IPx. However, as there are no clocks
>   defined to control MFC, G3D, and G2D, we kept them to access
> CLK_GATE_IPx. These may need to be modified (erase .enable, .ctrlbit
> from sclk_mfc, sclk_g2d, sclk_g3d and create clocks: g3d, g2d, mfc)
> later.
> 
> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> ---
>  arch/arm/mach-s5pv210/clock.c |  101
++++++++++++++++++++++-------------------
>  1 files changed, 55 insertions(+), 46 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> index ec5ad8c..08c1063 100644
> --- a/arch/arm/mach-s5pv210/clock.c
> +++ b/arch/arm/mach-s5pv210/clock.c

(snip)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Fri Jun 18 05:58:35 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 18 Jun 2010 18:58:35 +0900
Subject: [PATCH] S5PV210 Correct clock source control register properties
In-Reply-To: <AANLkTik78ycpNKYIhdu7SKeQ_9htcjCJlXch5bobUxHq@mail.gmail.com>
References: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>
	<003301cb0ea8$474d1640$d5e742c0$%kim@samsung.com>
	<AANLkTik78ycpNKYIhdu7SKeQ_9htcjCJlXch5bobUxHq@mail.gmail.com>
Message-ID: <005501cb0ecc$d1de38b0$759aaa10$%kim@samsung.com>

MyungJoo Ham wrote:
> 
> On Fri, Jun 18, 2010 at 2:36 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > MyungJoo Ham wrote:
> >>
> >> The clock source controls (struct clksrc_clk) have been often accessing
> >> CLK_GATE_IPx, which are for clock gating and are accessed by each clock
> >> as well as the clock source. This duplicated clock issue may incur
> >> lockup problems when there are two modules accessing the same clock with
> >> different names.
> >>
> > Actually, S5V210/S5PC110 CLK_GATE_IPx can disable the clock operation of
> each
> > IP if it is not required. And this reduces dynamic power. CLK_SRC_MASKx is
> > used to control clock mux of each IP's SCLK.
> >
> > Basically CLK_SRC_MASKx is for mux control (output masking) of each IP
> > source, and actually that can _not_ control relevant every source clock of
> > each IP. So CLK_GATE_IPx exists, can do it.
> >
> > I know, in the several case, i.e, camera and fimc, each sclk_xxx need to
> > control. And can be controlled each sclk_xxx by using your patch, but in this
> > case, need to additional control relevant clock gating for dynamic clock
> > gating of each IP in its device driver.
> 
> We've changed clksrc_clk's not to access CLK_GATE_IPx because of the
> duplicated clock (or doppelganger) problem. We need to either get rid
> of ".enable / .ctrlbit" from
> struct clk of struct clksrc_clk, change them to use "CLK_SRC_MASKx",
> or get rid of their twins
> (e.g., "hsmmc" for "mmc_bus") as long as there are clock definitions
> with different names
> accessing the same CLK_GATE_IPx. Letting clksrc_clk access
> CLK_GATE_IPx creates potential
> kernel lockups.
> 
Hmm..duplicated clock problem?

The clk_enable and clk_disable functions maintain a reference count and base the decision about enabling/disabling the clock on the reference count. Could you please explain how kernel lockups will occur in this case (considering the use of reference count in clk_enable and clk_disable)

> Drivers should get clocks defined in "static struct clk init_clocks[],
> init_clocks_disable[]" in order
> to access CLK_GATE_IPx though we still have some missing clocks there;
> e.g., mfc, g2d, and g3d.
> Again, there should be NO duplicated clock definitions if we are going
> to use .enable function that
> accesses the same address & bit.
> 
> ----------- from the previous patch -----------
> Please note that each clock definition should access different control
> register; otherwise, the system may suffer lockups. For example, if we
> have two clock definitions "a" and "b" which access the same register
> (and the shift value). Then, when we do:
> 
>        module B
>        1 clk = clk_get("b");
>        2 clk->clk_enable(clk);
>        3 do something with clk.
>        4 clk->clk_disable(clk);
> 
>        module A
>        1 clk = clk_get("a");
>        2 clk->clk_enable(clk);
>        3 do something with clk
>        4 clk->clk_disable(clk);
> 
>        And if the execution order is
> 
>        B1->B2->A1->A2->A3->A4->B3 ...
> 
>        Then, the system may hang at the point B3.
> ------------------------------------------------------------------------------------
> 
> >
> >> Besides, the clock source control is supposed to control (setting values
> >> of MASK, SRC, DIV), not to turn on/off individual clock.
> >>
> >> Another point is that there are registers (CLK_SRC_MASK0/1) specialized
> >> for masking clock source control in S5PV210/S5PC110 according to the
> >> user manual (rev 20100201).
> >>
> >> Therefore, accessing CLK_SRC_MASK0/1 (rather than accessing
> >> CLK_GATE_IPx) for the clock source control is safer and fits to the
> >> semantics of S5PV210/S5PC110 registers. And fortuneatly, each clock
> >> source defined in clock.c has corresponding bit at CLK_SRC_MASK0/1
> >> except for MFC, G2D, and G3D.
> >>
> >> In this patch,
> >>
> >> - DAC, HDMI, AUDIO 0/1/2, UCLK(uart) 0/1/2/3, MIXER, FIMC 0/1/2,
> >> FIMC, MMC 0/1/2/3, CSIS, SPI 0/1, PWI, and PWM clock sources are
> >> modified to use CLK_SRC_MASK0/1, which were using CLK_GATE_IPx.
> >>
> >> - CAM 0/1 did not have enable/disable control. They now access
> >>   CLK_SRC_MASK0.
> >>
> >> - MFC, G3D, G2D were using CLK_GATE_IPx. However, as there are no clocks
> >>   defined to control MFC, G3D, and G2D, we kept them to access
> >> CLK_GATE_IPx. These may need to be modified (erase .enable, .ctrlbit
> >> from sclk_mfc, sclk_g2d, sclk_g3d and create clocks: g3d, g2d, mfc)
> >> later.
> >>
> > Hmm..need to check about multimedia usage.
> >
> > And in my opinion, it would be helpful to understand that should be short and
> > clear.
> >
> >> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> >> ---
> >>  arch/arm/mach-s5pv210/clock.c |  101
> > ++++++++++++++++++++++-------------------
> >>  1 files changed, 55 insertions(+), 46 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> >> index ec5ad8c..08c1063 100644
> >> --- a/arch/arm/mach-s5pv210/clock.c
> >> +++ b/arch/arm/mach-s5pv210/clock.c

(snip)

> >> --
> >
> > I'm not sure that need to control of all sclk_xxx like above method, mux
> > output masking.
> >

Please let me know your opinion about above question based on scenario.

> > Thanks.
> >
> > Best regards,
> > Kgene.
> > --
> > Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> > SW Solution Development Team, Samsung Electronics Co., Ltd.
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel at lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >
> 
> ps. I forgot to erase .enable and .ctrlbit of "sclk_fimc"s. The user
> manual states that
> the three "sclk_fimc" clocks should be controlled identically at the
> same time; thus,
> there should be no individual clock masking control on them. This will
> be done later.
> (we may let them control (0x7<<2) so that they are controlled at the
> same time, however,
> we create "doppelganger" clocks there by doing so.)
> 
> 


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From adrian.wenl at gmail.com  Fri Jun 18 06:01:02 2010
From: adrian.wenl at gmail.com (Lei Wen)
Date: Fri, 18 Jun 2010 18:01:02 +0800
Subject: [PATCH 02/25] pxa3xx_nand: introduce common timing to reduce read
	id times
In-Reply-To: <AANLkTimeJYwret1ZlEHaX_-T14qB3WteQwpn9y7_1Zo9@mail.gmail.com>
References: <AANLkTim1qcVoqSS7T8bE0Vsu6phC2iY_Ok671WYHcD0z@mail.gmail.com>
	<AANLkTil6QDRdh3s63J9Mm-B1qjMcnYjEEm-W5lC1NXVb@mail.gmail.com>
	<AANLkTikbzXgwMvnNVRkcOO-9El9hmAXhKZK_dFgStbwY@mail.gmail.com>
	<AANLkTikDDFYY65l5YYGW3a0O2bWDyKRO6VRb15aaFtF7@mail.gmail.com>
	<AANLkTil6D3Cijy1JZ3aQLBGBfi99zOGDy5Xl8OmY_T_8@mail.gmail.com>
	<AANLkTimeJYwret1ZlEHaX_-T14qB3WteQwpn9y7_1Zo9@mail.gmail.com>
Message-ID: <AANLkTimU35i4hpzwb34lbqYrP0ijoWw6KH3q_ntb2fHh@mail.gmail.com>

On Fri, Jun 18, 2010 at 5:19 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 5:15 PM, Lei Wen <adrian.wenl at gmail.com> wrote:
>> On Fri, Jun 18, 2010 at 4:12 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>>>>>> - ? ? ? if (f->page_size != 2048 && f->page_size != 512)
>>>>>> - ? ? ? ? ? ? ? return -EINVAL;
>>>>>> -
>>>>>> - ? ? ? if (f->flash_width != 16 && f->flash_width != 8)
>>>>>> - ? ? ? ? ? ? ? return -EINVAL;
>>>>>> -
>>>>>
>>>>> I do think these are sanity check, that's useful to prevent incorrectly defined
>>>>> data (esp. coming from board code). Can we define the loose flash type as:
>>>>>
>>>>>> ?static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
>>>>>> + ? ? ? { ?0x0000, ? 0, ? ?512, ?8, ?8, ? ?0, &timing[0], },
>>>>>> + ? ? ? { 0x46ec, ?32, ?512, 16, 16, 4096, &timing[1], },
>>>>>> + ? ? ? { 0xdaec, ?64, 2048, ?8, ?8, 2048, &timing[1], },
>>>>>
>>>>> with a comment of /* default flash type to detect ID */?
>>>>>
>>>>> My understanding is the minimum requirement to detect the NAND ID is a
>>>>> loose timing and 512 small page, 8-bit wide bus, so with a chip_id being
>>>>> 0x0000, that should be enough to tell it's a special flash type to detect ID.
>>>>
>>>> There is no need to add the flash page size and bus width for the
>>>> common timing, or loose timing...
>>>> For the chip identification only need reset and read id command, and
>>>> reset and read id command only care
>>>> for the first command in NDCB0 and the timing setting in NDTR0CS0 and
>>>> NDTR1CS0, the page size is not useful
>>>> here and could make confussion if give such definition...
>>>
>>> I know, but I'd like to keep the checking of page_size, and flash_width,
>>> if you take a look into the rest of the code how much it is assumed that
>>> page_size being either 2048 or 512, flash_width being 8 or 16, you'll
>>> know why such an error checking here is mandatory actually.
>>
>> I know that the configure_flash function need to check page_size &
>> flash_width to set the
>> ndcr. But what the setting would not affect the reset/read id result anyway...
>> For there is some chip has the same bytes in the first two bytes, I
>> choose to always read out
>> 4 bytes data when send read id command in latter patch of this patch set...
>>
>
> My understanding is that NAND READID will at least work with the assumption
> of 512bytes/page and 8-bit wide bus, no matter how the NAND chips are
> connected. (unless some one comes up with a insane design of using multiple
> interlaced NAND chips of different types).
>
> Again, assume the NAND controller is not initialized (register values being
> garbage or all zero-ed), do you still think you can read out the ID without
> letting it know the page size, bus width and etc?
>

Well... I understand it is good to reserve the page size and width
judgement in configuration.
I would make this part revert back to its original state...
For read id, it would not care for the page size and width setting in NDCR...


From myungjoo.ham at samsung.com  Fri Jun 18 06:12:25 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Fri, 18 Jun 2010 19:12:25 +0900
Subject: [PATCH] S5PV210 Correct clock source control register properties
In-Reply-To: <005501cb0ecc$d1de38b0$759aaa10$%kim@samsung.com>
References: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>
	<003301cb0ea8$474d1640$d5e742c0$%kim@samsung.com>
	<AANLkTik78ycpNKYIhdu7SKeQ_9htcjCJlXch5bobUxHq@mail.gmail.com>
	<005501cb0ecc$d1de38b0$759aaa10$%kim@samsung.com>
Message-ID: <AANLkTin_CgGAzW2Lla2P4PZJyeANAahVZ9_pdqi8Xacf@mail.gmail.com>

On Fri, Jun 18, 2010 at 6:58 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> MyungJoo Ham wrote:
>>
>> On Fri, Jun 18, 2010 at 2:36 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>> > MyungJoo Ham wrote:
>> >>
>> >> The clock source controls (struct clksrc_clk) have been often accessing
>> >> CLK_GATE_IPx, which are for clock gating and are accessed by each clock
>> >> as well as the clock source. This duplicated clock issue may incur
>> >> lockup problems when there are two modules accessing the same clock with
>> >> different names.
>> >>
>> > Actually, S5V210/S5PC110 CLK_GATE_IPx can disable the clock operation of
>> each
>> > IP if it is not required. And this reduces dynamic power. CLK_SRC_MASKx is
>> > used to control clock mux of each IP's SCLK.
>> >
>> > Basically CLK_SRC_MASKx is for mux control (output masking) of each IP
>> > source, and actually that can _not_ control relevant every source clock of
>> > each IP. So CLK_GATE_IPx exists, can do it.
>> >
>> > I know, in the several case, i.e, camera and fimc, each sclk_xxx need to
>> > control. And can be controlled each sclk_xxx by using your patch, but in this
>> > case, need to additional control relevant clock gating for dynamic clock
>> > gating of each IP in its device driver.
>>
>> We've changed clksrc_clk's not to access CLK_GATE_IPx because of the
>> duplicated clock (or doppelganger) problem. We need to either get rid
>> of ".enable / .ctrlbit" from
>> struct clk of struct clksrc_clk, change them to use "CLK_SRC_MASKx",
>> or get rid of their twins
>> (e.g., "hsmmc" for "mmc_bus") as long as there are clock definitions
>> with different names
>> accessing the same CLK_GATE_IPx. Letting clksrc_clk access
>> CLK_GATE_IPx creates potential
>> kernel lockups.
>>
> Hmm..duplicated clock problem?
>

> The clk_enable and clk_disable functions maintain a reference count and base the decision about enabling/disabling the clock on the reference count. Could you please explain how kernel lockups will occur in this case (considering the use of reference count in clk_enable and clk_disable)
>

It's because each struct clk keeps its own count value, not a shared
count value.

The lockup example (rephrased example of the previous reply)



(not an exact code / assume that initially the clock is off)

struct clk clkA = {.name="a", .ctrlbit=1, .enable=func};
struct clk clkB = {.name="b", .ctrlbit=1, .enable=func};

module A
{
 struct clk *a = clk_get("a");
 clk_enable(a);
 while (1)
   access registers related with the clock;
 clk_disable(a);
}

module B
{
 struct clk *b = clk_get("b");
 clk_enable(b);
   do a short job related with the clock;
 clk_disable(b);
}

Imagine when A started first, but while A stays in the loop, B runs
and exits. Then, in the module A, accessing registers may fail, which,
in turn, can lead to a lockup.


In this example, they do NOT share their count value, but access the
same register; i.e., a.count is not related with b.count while
a.enable(a.ctrlbit) will do the exactly same thing with
b.enable(b.ctrlbit). When there are one module using clkA and another
using clkB, the system may suffer from lockups.

Unless we change "struct clk" or "plat/clock.c:clk_disable" so that
they can refer to other "struct clk" (which does not appear to be a
good idea anyway), we should not define a clock more than once.


>> Drivers should get clocks defined in "static struct clk init_clocks[],
>> init_clocks_disable[]" in order
>> to access CLK_GATE_IPx though we still have some missing clocks there;
>> e.g., mfc, g2d, and g3d.
>> Again, there should be NO duplicated clock definitions if we are going
>> to use .enable function that
>> accesses the same address & bit.
>>
>> ----------- from the previous patch -----------
>> Please note that each clock definition should access different control
>> register; otherwise, the system may suffer lockups. For example, if we
>> have two clock definitions "a" and "b" which access the same register
>> (and the shift value). Then, when we do:
>>
>> ? ? ? ?module B
>> ? ? ? ?1 clk = clk_get("b");
>> ? ? ? ?2 clk->clk_enable(clk);
>> ? ? ? ?3 do something with clk.
>> ? ? ? ?4 clk->clk_disable(clk);
>>
>> ? ? ? ?module A
>> ? ? ? ?1 clk = clk_get("a");
>> ? ? ? ?2 clk->clk_enable(clk);
>> ? ? ? ?3 do something with clk
>> ? ? ? ?4 clk->clk_disable(clk);
>>
>> ? ? ? ?And if the execution order is
>>
>> ? ? ? ?B1->B2->A1->A2->A3->A4->B3 ...
>>
>> ? ? ? ?Then, the system may hang at the point B3.
>> ------------------------------------------------------------------------------------
>>
>> >
>> >> Besides, the clock source control is supposed to control (setting values
>> >> of MASK, SRC, DIV), not to turn on/off individual clock.
>> >>
>> >> Another point is that there are registers (CLK_SRC_MASK0/1) specialized
>> >> for masking clock source control in S5PV210/S5PC110 according to the
>> >> user manual (rev 20100201).
>> >>
>> >> Therefore, accessing CLK_SRC_MASK0/1 (rather than accessing
>> >> CLK_GATE_IPx) for the clock source control is safer and fits to the
>> >> semantics of S5PV210/S5PC110 registers. And fortuneatly, each clock
>> >> source defined in clock.c has corresponding bit at CLK_SRC_MASK0/1
>> >> except for MFC, G2D, and G3D.
>> >>
>> >> In this patch,
>> >>
>> >> - DAC, HDMI, AUDIO 0/1/2, UCLK(uart) 0/1/2/3, MIXER, FIMC 0/1/2,
>> >> FIMC, MMC 0/1/2/3, CSIS, SPI 0/1, PWI, and PWM clock sources are
>> >> modified to use CLK_SRC_MASK0/1, which were using CLK_GATE_IPx.
>> >>
>> >> - CAM 0/1 did not have enable/disable control. They now access
>> >> ? CLK_SRC_MASK0.
>> >>
>> >> - MFC, G3D, G2D were using CLK_GATE_IPx. However, as there are no clocks
>> >> ? defined to control MFC, G3D, and G2D, we kept them to access
>> >> CLK_GATE_IPx. These may need to be modified (erase .enable, .ctrlbit
>> >> from sclk_mfc, sclk_g2d, sclk_g3d and create clocks: g3d, g2d, mfc)
>> >> later.
>> >>
>> > Hmm..need to check about multimedia usage.
>> >
>> > And in my opinion, it would be helpful to understand that should be short and
>> > clear.
>> >
>> >> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
>> >> ---
>> >> ?arch/arm/mach-s5pv210/clock.c | ?101
>> > ++++++++++++++++++++++-------------------
>> >> ?1 files changed, 55 insertions(+), 46 deletions(-)
>> >>
>> >> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
>> >> index ec5ad8c..08c1063 100644
>> >> --- a/arch/arm/mach-s5pv210/clock.c
>> >> +++ b/arch/arm/mach-s5pv210/clock.c
>
> (snip)
>
>> >> --
>> >
>> > I'm not sure that need to control of all sclk_xxx like above method, mux
>> > output masking.
>> >
>
> Please let me know your opinion about above question based on scenario.
>
>> > Thanks.
>> >
>> > Best regards,
>> > Kgene.
>> > --
>> > Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
>> > SW Solution Development Team, Samsung Electronics Co., Ltd.
>> >
>> >
>> > _______________________________________________
>> > linux-arm-kernel mailing list
>> > linux-arm-kernel at lists.infradead.org
>> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>> >
>>
>> ps. I forgot to erase .enable and .ctrlbit of "sclk_fimc"s. The user
>> manual states that
>> the three "sclk_fimc" clocks should be controlled identically at the
>> same time; thus,
>> there should be no individual clock masking control on them. This will
>> be done later.
>> (we may let them control (0x7<<2) so that they are controlled at the
>> same time, however,
>> we create "doppelganger" clocks there by doing so.)
>>
>>
>
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
MyungJoo Ham (???), Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858


From maramaopercheseimorto at gmail.com  Fri Jun 18 06:16:26 2010
From: maramaopercheseimorto at gmail.com (Alberto Panizzo)
Date: Fri, 18 Jun 2010 12:16:26 +0200
Subject: [PATCH v2] input/imx_keypad: add PM support
In-Reply-To: <1276801147-4103-1-git-send-email-eric@eukrea.com>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>
Message-ID: <1276856186.3146.5.camel@realization>

Hi Eric,

On gio, 2010-06-17 at 20:59 +0200, Eric B?nard wrote:
> We use keypad_data to enable wakeup from platform data
> 
> suspend/resume is tested on an i.MX27 when keypad is not
> in use and when it's is in use (in which case we immediatly
> get the key pressed at wakeup)
> 
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> Cc: maramaopercheseimorto at gmail.com
> Cc: linux-input at vger.kernel.org
> Cc: dmitry.torokhov at gmail.com
> Cc: linux-arm-kernel at lists.infradead.org
> ---
> v2 :
> 	- simplify suspend & resume functions
> 	- convert to pm_ops
> 
>  drivers/input/keyboard/imx_keypad.c |   40 +++++++++++++++++++++++++++++++++-
>  1 files changed, 38 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/input/keyboard/imx_keypad.c b/drivers/input/keyboard/imx_keypad.c
> index d92c15c..9aa0005 100644
> --- a/drivers/input/keyboard/imx_keypad.c
> +++ b/drivers/input/keyboard/imx_keypad.c
> @@ -364,6 +364,38 @@ static void imx_keypad_inhibit(struct imx_keypad *keypad)
>  	writew(0xff00, keypad->mmio_base + KPCR);
>  }
>  
> +#ifdef CONFIG_PM
> +static int mxc_kpp_suspend(struct device *dev)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct imx_keypad *keypad = platform_get_drvdata(pdev);
> +
> +	keypad->enabled = false;
> +	synchronize_irq(keypad->irq);
> +	disable_irq(keypad->irq);
> +	clk_disable(keypad->clk);
> +
> +	return 0;
> +}
> +
> +static int mxc_kpp_resume(struct device *dev)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct imx_keypad *keypad = platform_get_drvdata(pdev);
> +
> +	keypad->enabled = true;
> +	clk_enable(keypad->clk);
> +	enable_irq(keypad->irq);
> +
> +	return 0;
> +}

Ok, so with this patch the keypad cannot wake the system?
It is scheduled another patch?


-- 
Alberto!

        Be Persistent!
                - Greg Kroah-Hartman (FOSDEM 2010)



From myungjoo.ham at samsung.com  Fri Jun 18 06:25:02 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Fri, 18 Jun 2010 19:25:02 +0900
Subject: [PATCH] S5PV210 Correct clock source control register properties
In-Reply-To: <005401cb0ecb$c3f16c00$4bd44400$%kim@samsung.com>
References: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>
	<005401cb0ecb$c3f16c00$4bd44400$%kim@samsung.com>
Message-ID: <AANLkTim1psO4ZeZGAgNteJp_ytRhzoPlu4D3VblPgz6w@mail.gmail.com>

On Fri, Jun 18, 2010 at 6:50 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> MyungJoo Ham wrote:
>>
>> The clock source controls (struct clksrc_clk) have been often accessing
>> CLK_GATE_IPx, which are for clock gating and are accessed by each clock
>> as well as the clock source. This duplicated clock issue may incur
>> lockup problems when there are two modules accessing the same clock with
>> different names.
>>
> Could you please explain further about the above the statement " accessed by
> each clock as well as the clock source"

For example, "CLK_GATE_IP2[16:19]" is accessed by "hsmmc" of struct
clk (a clock) and "sclk_mmc" of struct clksrc_clk's struct clk (a
clock source's clk representation).

>
>> Besides, the clock source control is supposed to control (setting values
>> of MASK, SRC, DIV), not to turn on/off individual clock.
>>
> That is not quite true. Only S5PV210/S5PC110 have the gate for the clock mux.
> S5P6440 and S5PC100, for instance, do not have a gate for the output for
> _just_ the clock mux. And the reason why the Clock Mux Gate is provide for
> the mux is explained in Section 3.4 of the user manual.

In cases where clock mux gating is not available and we have each
clock (supplied by this cluck mux) defined separatedly with .enable
and .ctrlbit, we'd better omit .enable/.ctrlbit from struct
clksrc_clk's struct clk.

>
>> Another point is that there are registers (CLK_SRC_MASK0/1) specialized
>> for masking clock source control in S5PV210/S5PC110 according to the
>> user manual (rev 20100201).
>>
>> Therefore, accessing CLK_SRC_MASK0/1 (rather than accessing
>> CLK_GATE_IPx) for the clock source control is safer and fits to the
>> semantics of S5PV210/S5PC110 registers. And fortuneatly, each clock
>> source defined in clock.c has corresponding bit at CLK_SRC_MASK0/1
>> except for MFC, G2D, and G3D.
>>
> Can you please explain how the use CLK_SRC_MASKx makes it safer. The reason
> why MFC, G2D and G3D do not have a corresponding bit in CLK_SRC_MASKx is
> mentioned in Section 3.4 of the user manual.
>
> Let me know your opinion.
>

It's "EXCEPT FOR MFC, G2D, G3D". I'm not saying that using
CLK_SRC_MASKx is safer for these three. For other cases, I guess the
lock up example should be fine.

However, in most cases, this lockup issue does not make visible problem because:
1. normally, drivers use both clksrc_clk's clk and clk at the same
time. for example
"mmc_bus".clk_enable;
"hsmmc".clk_enable;
 blahblah
"hsmmc".clk_disable;
"mmc_bus".clk_disable;
or
2. drivers sharing the same clock uses only one side of the two.
or
3. the execution block between clk_enable and clk_disable is extremely short.

Nevertheless, this potential lockup issue is critical and we'd better
address it.


>> In this patch,
>>
>> - DAC, HDMI, AUDIO 0/1/2, UCLK(uart) 0/1/2/3, MIXER, FIMC 0/1/2,
>> FIMC, MMC 0/1/2/3, CSIS, SPI 0/1, PWI, and PWM clock sources are
>> modified to use CLK_SRC_MASK0/1, which were using CLK_GATE_IPx.
>>
>> - CAM 0/1 did not have enable/disable control. They now access
>> ? CLK_SRC_MASK0.
>>
>> - MFC, G3D, G2D were using CLK_GATE_IPx. However, as there are no clocks
>> ? defined to control MFC, G3D, and G2D, we kept them to access
>> CLK_GATE_IPx. These may need to be modified (erase .enable, .ctrlbit
>> from sclk_mfc, sclk_g2d, sclk_g3d and create clocks: g3d, g2d, mfc)
>> later.
>>
>> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
>> ---
>> ?arch/arm/mach-s5pv210/clock.c | ?101
> ++++++++++++++++++++++-------------------
>> ?1 files changed, 55 insertions(+), 46 deletions(-)
>>
>> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
>> index ec5ad8c..08c1063 100644
>> --- a/arch/arm/mach-s5pv210/clock.c
>> +++ b/arch/arm/mach-s5pv210/clock.c
>
> (snip)
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
MyungJoo Ham (???), Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858


From rabin.vincent at stericsson.com  Fri Jun 18 06:28:35 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Fri, 18 Jun 2010 15:58:35 +0530
Subject: [PATCH 1/2] ux500: add separate irq lists for DB8500 and DB5500
Message-ID: <1276856916-19124-1-git-send-email-rabin.vincent@stericsson.com>

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Acked-by: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 arch/arm/mach-ux500/board-mop500.c             |    2 +-
 arch/arm/mach-ux500/devices-db8500.c           |   14 ++--
 arch/arm/mach-ux500/include/mach/irqs-db5500.h |   85 +++++++++++++++++++++
 arch/arm/mach-ux500/include/mach/irqs-db8500.h |   96 ++++++++++++++++++++++++
 arch/arm/mach-ux500/include/mach/irqs.h        |   18 +++--
 5 files changed, 201 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/mach-ux500/include/mach/irqs-db5500.h
 create mode 100644 arch/arm/mach-ux500/include/mach/irqs-db8500.h

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index b83005e..0331e4b 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -78,7 +78,7 @@ static struct spi_board_info u8500_spi_devices[] = {
 		.bus_num = 0,
 		.chip_select = 0,
 		.mode = SPI_MODE_0,
-		.irq = IRQ_AB4500,
+		.irq = IRQ_DB8500_AB8500,
 	},
 };
 
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 8229034..56197b2 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -65,7 +65,7 @@ struct amba_device u8500_ssp0_device = {
 		.end   = U8500_SSP0_BASE + SZ_4K - 1,
 		.flags = IORESOURCE_MEM,
 	},
-	.irq = {IRQ_SSP0, NO_IRQ },
+	.irq = {IRQ_DB8500_SSP0, NO_IRQ },
 	/* ST-Ericsson modified id */
 	.periphid = SSP_PER_ID,
 };
@@ -77,8 +77,8 @@ static struct resource u8500_i2c0_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= IRQ_I2C0,
-		.end	= IRQ_I2C0,
+		.start	= IRQ_DB8500_I2C0,
+		.end	= IRQ_DB8500_I2C0,
 		.flags	= IORESOURCE_IRQ,
 	}
 };
@@ -97,8 +97,8 @@ static struct resource u8500_i2c4_resources[] = {
 		.flags	= IORESOURCE_MEM,
 	},
 	[1] = {
-		.start	= IRQ_I2C4,
-		.end	= IRQ_I2C4,
+		.start	= IRQ_DB8500_I2C4,
+		.end	= IRQ_DB8500_I2C4,
 		.flags	= IORESOURCE_IRQ,
 	}
 };
@@ -130,8 +130,8 @@ static struct resource dma40_resources[] = {
 		.name = "lcla",
 	},
 	[3] = {
-		.start = IRQ_DMA,
-		.end = IRQ_DMA,
+		.start = IRQ_DB8500_DMA,
+		.end = IRQ_DB8500_DMA,
 		.flags = IORESOURCE_IRQ}
 };
 
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
new file mode 100644
index 0000000..6fbfe5e
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent at stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_DB5500_H
+#define __MACH_IRQS_DB5500_H
+
+#define IRQ_DB5500_MTU0			(IRQ_SHPI_START + 4)
+#define IRQ_DB5500_SPI2			(IRQ_SHPI_START + 6)
+#define IRQ_DB5500_PMU0			(IRQ_SHPI_START + 7)
+#define IRQ_DB5500_SPI0			(IRQ_SHPI_START + 8)
+#define IRQ_DB5500_RTT			(IRQ_SHPI_START + 9)
+#define IRQ_DB5500_PKA			(IRQ_SHPI_START + 10)
+#define IRQ_DB5500_UART0		(IRQ_SHPI_START + 11)
+#define IRQ_DB5500_I2C3			(IRQ_SHPI_START + 12)
+#define IRQ_DB5500_L2CC			(IRQ_SHPI_START + 13)
+#define IRQ_DB5500_MSP0			(IRQ_SHPI_START + 14)
+#define IRQ_DB5500_CRYP1		(IRQ_SHPI_START + 15)
+#define IRQ_DB5500_PMU1			(IRQ_SHPI_START + 16)
+#define IRQ_DB5500_MTU1			(IRQ_SHPI_START + 17)
+#define IRQ_DB5500_RTC			(IRQ_SHPI_START + 18)
+#define IRQ_DB5500_UART1		(IRQ_SHPI_START + 19)
+#define IRQ_DB5500_USB_WAKEUP		(IRQ_SHPI_START + 20)
+#define IRQ_DB5500_I2C0			(IRQ_SHPI_START + 21)
+#define IRQ_DB5500_I2C1			(IRQ_SHPI_START + 22)
+#define IRQ_DB5500_USBOTG		(IRQ_SHPI_START + 23)
+#define IRQ_DB5500_DMA_SECURE		(IRQ_SHPI_START + 24)
+#define IRQ_DB5500_DMA			(IRQ_SHPI_START + 25)
+#define IRQ_DB5500_UART2		(IRQ_SHPI_START + 26)
+#define IRQ_DB5500_ICN_PMU1		(IRQ_SHPI_START + 27)
+#define IRQ_DB5500_ICN_PMU2		(IRQ_SHPI_START + 28)
+#define IRQ_DB5500_UART3		(IRQ_SHPI_START + 29)
+#define IRQ_DB5500_SPI3			(IRQ_SHPI_START + 30)
+#define IRQ_DB5500_SDMMC4		(IRQ_SHPI_START + 31)
+#define IRQ_DB5500_IRRC			(IRQ_SHPI_START + 33)
+#define IRQ_DB5500_IRDA_FT		(IRQ_SHPI_START + 34)
+#define IRQ_DB5500_IRDA_SD		(IRQ_SHPI_START + 35)
+#define IRQ_DB5500_IRDA_FI		(IRQ_SHPI_START + 36)
+#define IRQ_DB5500_IRDA_FD		(IRQ_SHPI_START + 37)
+#define IRQ_DB5500_FSMC_CODEREADY	(IRQ_SHPI_START + 38)
+#define IRQ_DB5500_FSMC_NANDWAIT	(IRQ_SHPI_START + 39)
+#define IRQ_DB5500_AB5500		(IRQ_SHPI_START + 40)
+#define IRQ_DB5500_SDMMC2		(IRQ_SHPI_START + 41)
+#define IRQ_DB5500_SIA			(IRQ_SHPI_START + 42)
+#define IRQ_DB5500_SIA2			(IRQ_SHPI_START + 43)
+#define IRQ_DB5500_HVA			(IRQ_SHPI_START + 44)
+#define IRQ_DB5500_HVA2			(IRQ_SHPI_START + 45)
+#define IRQ_DB5500_PRCMU0		(IRQ_SHPI_START + 46)
+#define IRQ_DB5500_PRCMU1		(IRQ_SHPI_START + 47)
+#define IRQ_DB5500_DISP			(IRQ_SHPI_START + 48)
+#define IRQ_DB5500_SDMMC1		(IRQ_SHPI_START + 50)
+#define IRQ_DB5500_MSP1			(IRQ_SHPI_START + 52)
+#define IRQ_DB5500_KBD			(IRQ_SHPI_START + 53)
+#define IRQ_DB5500_I2C2			(IRQ_SHPI_START + 55)
+#define IRQ_DB5500_B2R2			(IRQ_SHPI_START + 56)
+#define IRQ_DB5500_CRYP0		(IRQ_SHPI_START + 57)
+#define IRQ_DB5500_SDMMC3		(IRQ_SHPI_START + 59)
+#define IRQ_DB5500_SDMMC0		(IRQ_SHPI_START + 60)
+#define IRQ_DB5500_HSEM			(IRQ_SHPI_START + 61)
+#define IRQ_DB5500_SBAG			(IRQ_SHPI_START + 63)
+#define IRQ_DB5500_SPI1			(IRQ_SHPI_START + 96)
+#define IRQ_DB5500_MSP2			(IRQ_SHPI_START + 98)
+#define IRQ_DB5500_SRPTIMER		(IRQ_SHPI_START + 101)
+#define IRQ_DB5500_CTI0			(IRQ_SHPI_START + 108)
+#define IRQ_DB5500_CTI1			(IRQ_SHPI_START + 109)
+#define IRQ_DB5500_ICN_ERR		(IRQ_SHPI_START + 110)
+#define IRQ_DB5500_MALI_PPMMU		(IRQ_SHPI_START + 112)
+#define IRQ_DB5500_MALI_PP		(IRQ_SHPI_START + 113)
+#define IRQ_DB5500_MALI_GPMMU		(IRQ_SHPI_START + 114)
+#define IRQ_DB5500_MALI_GP		(IRQ_SHPI_START + 115)
+#define IRQ_DB5500_MALI			(IRQ_SHPI_START + 116)
+#define IRQ_DB5500_PRCMU_SEM		(IRQ_SHPI_START + 118)
+#define IRQ_DB5500_GPIO0		(IRQ_SHPI_START + 119)
+#define IRQ_DB5500_GPIO1		(IRQ_SHPI_START + 120)
+#define IRQ_DB5500_GPIO2		(IRQ_SHPI_START + 121)
+#define IRQ_DB5500_GPIO3		(IRQ_SHPI_START + 122)
+#define IRQ_DB5500_GPIO4		(IRQ_SHPI_START + 123)
+#define IRQ_DB5500_GPIO5		(IRQ_SHPI_START + 124)
+#define IRQ_DB5500_GPIO6		(IRQ_SHPI_START + 125)
+#define IRQ_DB5500_GPIO7		(IRQ_SHPI_START + 126)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
new file mode 100644
index 0000000..8b5d9f0
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent at stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_DB8500_H
+#define __MACH_IRQS_DB8500_H
+
+#define IRQ_DB8500_MTU0			(IRQ_SHPI_START + 4)
+#define IRQ_DB8500_SPI2			(IRQ_SHPI_START + 6)
+#define IRQ_DB8500_PMU			(IRQ_SHPI_START + 7)
+#define IRQ_DB8500_SPI0			(IRQ_SHPI_START + 8)
+#define IRQ_DB8500_RTT			(IRQ_SHPI_START + 9)
+#define IRQ_DB8500_PKA			(IRQ_SHPI_START + 10)
+#define IRQ_DB8500_UART0		(IRQ_SHPI_START + 11)
+#define IRQ_DB8500_I2C3			(IRQ_SHPI_START + 12)
+#define IRQ_DB8500_L2CC			(IRQ_SHPI_START + 13)
+#define IRQ_DB8500_SSP0			(IRQ_SHPI_START + 14)
+#define IRQ_DB8500_CRYP1		(IRQ_SHPI_START + 15)
+#define IRQ_DB8500_MSP1_RX		(IRQ_SHPI_START + 16)
+#define IRQ_DB8500_MTU1			(IRQ_SHPI_START + 17)
+#define IRQ_DB8500_RTC			(IRQ_SHPI_START + 18)
+#define IRQ_DB8500_UART1		(IRQ_SHPI_START + 19)
+#define IRQ_DB8500_USB_WAKEUP		(IRQ_SHPI_START + 20)
+#define IRQ_DB8500_I2C0			(IRQ_SHPI_START + 21)
+#define IRQ_DB8500_I2C1			(IRQ_SHPI_START + 22)
+#define IRQ_DB8500_USBOTG		(IRQ_SHPI_START + 23)
+#define IRQ_DB8500_DMA_SECURE		(IRQ_SHPI_START + 24)
+#define IRQ_DB8500_DMA			(IRQ_SHPI_START + 25)
+#define IRQ_DB8500_UART2		(IRQ_SHPI_START + 26)
+#define IRQ_DB8500_ICN_PMU1		(IRQ_SHPI_START + 27)
+#define IRQ_DB8500_ICN_PMU2		(IRQ_SHPI_START + 28)
+#define IRQ_DB8500_HSIR_EXCEP		(IRQ_SHPI_START + 29)
+#define IRQ_DB8500_MSP0			(IRQ_SHPI_START + 31)
+#define IRQ_DB8500_HSIR_CH0_OVRRUN	(IRQ_SHPI_START + 32)
+#define IRQ_DB8500_HSIR_CH1_OVRRUN	(IRQ_SHPI_START + 33)
+#define IRQ_DB8500_HSIR_CH2_OVRRUN	(IRQ_SHPI_START + 34)
+#define IRQ_DB8500_HSIR_CH3_OVRRUN	(IRQ_SHPI_START + 35)
+#define IRQ_DB8500_HSIR_CH4_OVRRUN	(IRQ_SHPI_START + 36)
+#define IRQ_DB8500_HSIR_CH5_OVRRUN	(IRQ_SHPI_START + 37)
+#define IRQ_DB8500_HSIR_CH6_OVRRUN	(IRQ_SHPI_START + 38)
+#define IRQ_DB8500_HSIR_CH7_OVRRUN	(IRQ_SHPI_START + 39)
+#define IRQ_DB8500_AB8500		(IRQ_SHPI_START + 40)
+#define IRQ_DB8500_SDMMC2		(IRQ_SHPI_START + 41)
+#define IRQ_DB8500_SIA			(IRQ_SHPI_START + 42)
+#define IRQ_DB8500_SIA2			(IRQ_SHPI_START + 43)
+#define IRQ_DB8500_SVA			(IRQ_SHPI_START + 44)
+#define IRQ_DB8500_SVA2			(IRQ_SHPI_START + 45)
+#define IRQ_DB8500_PRCMU0		(IRQ_SHPI_START + 46)
+#define IRQ_DB8500_PRCMU1		(IRQ_SHPI_START + 47)
+#define IRQ_DB8500_DISP			(IRQ_SHPI_START + 48)
+#define IRQ_DB8500_SPI3			(IRQ_SHPI_START + 49)
+#define IRQ_DB8500_SDMMC1		(IRQ_SHPI_START + 50)
+#define IRQ_DB8500_I2C4			(IRQ_SHPI_START + 51)
+#define IRQ_DB8500_SSP1			(IRQ_SHPI_START + 52)
+#define IRQ_DB8500_SKE			(IRQ_SHPI_START + 53)
+#define IRQ_DB8500_KB			(IRQ_SHPI_START + 54)
+#define IRQ_DB8500_I2C2			(IRQ_SHPI_START + 55)
+#define IRQ_DB8500_B2R2			(IRQ_SHPI_START + 56)
+#define IRQ_DB8500_CRYP0		(IRQ_SHPI_START + 57)
+#define IRQ_DB8500_SDMMC3		(IRQ_SHPI_START + 59)
+#define IRQ_DB8500_SDMMC0		(IRQ_SHPI_START + 60)
+#define IRQ_DB8500_HSEM			(IRQ_SHPI_START + 61)
+#define IRQ_DB8500_MSP1			(IRQ_SHPI_START + 62)
+#define IRQ_DB8500_SBAG			(IRQ_SHPI_START + 63)
+#define IRQ_DB8500_SPI1			(IRQ_SHPI_START + 96)
+#define IRQ_DB8500_SRPTIMER		(IRQ_SHPI_START + 97)
+#define IRQ_DB8500_MSP2			(IRQ_SHPI_START + 98)
+#define IRQ_DB8500_SDMMC4		(IRQ_SHPI_START + 99)
+#define IRQ_DB8500_SDMMC5		(IRQ_SHPI_START + 100)
+#define IRQ_DB8500_HSIRD0		(IRQ_SHPI_START + 104)
+#define IRQ_DB8500_HSIRD1		(IRQ_SHPI_START + 105)
+#define IRQ_DB8500_HSITD0		(IRQ_SHPI_START + 106)
+#define IRQ_DB8500_HSITD1		(IRQ_SHPI_START + 107)
+#define IRQ_DB8500_CTI0			(IRQ_SHPI_START + 108)
+#define IRQ_DB8500_CTI1			(IRQ_SHPI_START + 109)
+#define IRQ_DB8500_ICN_ERR		(IRQ_SHPI_START + 110)
+#define IRQ_DB8500_MALI_PPMMU		(IRQ_SHPI_START + 112)
+#define IRQ_DB8500_MALI_PP		(IRQ_SHPI_START + 113)
+#define IRQ_DB8500_MALI_GPMMU		(IRQ_SHPI_START + 114)
+#define IRQ_DB8500_MALI_GP		(IRQ_SHPI_START + 115)
+#define IRQ_DB8500_MALI			(IRQ_SHPI_START + 116)
+#define IRQ_DB8500_PRCMU_SEM		(IRQ_SHPI_START + 118)
+#define IRQ_DB8500_GPIO0		(IRQ_SHPI_START + 119)
+#define IRQ_DB8500_GPIO1		(IRQ_SHPI_START + 120)
+#define IRQ_DB8500_GPIO2		(IRQ_SHPI_START + 121)
+#define IRQ_DB8500_GPIO3		(IRQ_SHPI_START + 122)
+#define IRQ_DB8500_GPIO4		(IRQ_SHPI_START + 123)
+#define IRQ_DB8500_GPIO5		(IRQ_SHPI_START + 124)
+#define IRQ_DB8500_GPIO6		(IRQ_SHPI_START + 125)
+#define IRQ_DB8500_GPIO7		(IRQ_SHPI_START + 126)
+#define IRQ_DB8500_GPIO8		(IRQ_SHPI_START + 127)
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index 7970684..a6fb1fc 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -10,7 +10,8 @@
 #ifndef ASM_ARCH_IRQS_H
 #define ASM_ARCH_IRQS_H
 
-#include <mach/hardware.h>
+#include <mach/irqs-db5500.h>
+#include <mach/irqs-db8500.h>
 
 #define IRQ_LOCALTIMER                  29
 #define IRQ_LOCALWDOG                   30
@@ -67,12 +68,17 @@
 /* There are 128 shared peripheral interrupts assigned to
  * INTID[160:32]. The first 32 interrupts are reserved.
  */
-#define U8500_SOC_NR_IRQS		161
+#define DBX500_NR_INTERNAL_IRQS		161
 
 /* After chip-specific IRQ numbers we have the GPIO ones */
 #define NOMADIK_NR_GPIO			288
-#define NOMADIK_GPIO_TO_IRQ(gpio)	((gpio) + U8500_SOC_NR_IRQS)
-#define NOMADIK_IRQ_TO_GPIO(irq)	((irq) - U8500_SOC_NR_IRQS)
-#define NR_IRQS				NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
+#define NOMADIK_GPIO_TO_IRQ(gpio)	((gpio) + DBX500_NR_INTERNAL_IRQS)
+#define NOMADIK_IRQ_TO_GPIO(irq)	((irq) - DBX500_NR_INTERNAL_IRQS)
+#define IRQ_BOARD_START			NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
 
-#endif /*ASM_ARCH_IRQS_H*/
+/* This will be overridden by board-specific irq headers */
+#define IRQ_BOARD_END			IRQ_BOARD_START
+
+#define NR_IRQS				IRQ_BOARD_END
+
+#endif /* ASM_ARCH_IRQS_H */
-- 
1.7.0



From rabin.vincent at stericsson.com  Fri Jun 18 06:28:36 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Fri, 18 Jun 2010 15:58:36 +0530
Subject: [PATCH 2/2] mop500: add AB8500 interrupt support
In-Reply-To: <1276856916-19124-1-git-send-email-rabin.vincent@stericsson.com>
References: <1276856916-19124-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1276856916-19124-2-git-send-email-rabin.vincent@stericsson.com>

Add the platform data to enable AB8500 interrupt support.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Acked-by: Srinidhi Kasagar <srinidhi.kasagar at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 arch/arm/mach-ux500/board-mop500.c                 |    6 +++++
 .../mach-ux500/include/mach/irqs-board-mop500.h    |   23 ++++++++++++++++++++
 arch/arm/mach-ux500/include/mach/irqs.h            |    4 +++
 3 files changed, 33 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-ux500/include/mach/irqs-board-mop500.h

diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 0331e4b..0e8fd13 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -17,6 +17,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/pl022.h>
 #include <linux/spi/spi.h>
+#include <linux/mfd/ab8500.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -70,10 +71,15 @@ struct pl022_config_chip ab4500_chip_info = {
 	.cs_control = ab4500_spi_cs_control,
 };
 
+static struct ab8500_platform_data ab8500_platdata = {
+	.irq_base	= MOP500_AB8500_IRQ_BASE,
+};
+
 static struct spi_board_info u8500_spi_devices[] = {
 	{
 		.modalias = "ab8500",
 		.controller_data = &ab4500_chip_info,
+		.platform_data = &ab8500_platdata,
 		.max_speed_hz = 12000000,
 		.bus_num = 0,
 		.chip_select = 0,
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
new file mode 100644
index 0000000..cca4f70
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Rabin Vincent <rabin.vincent at stericsson.com>
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_BOARD_MOP500_H
+#define __MACH_IRQS_BOARD_MOP500_H
+
+#define AB8500_NR_IRQS			104
+
+#define MOP500_AB8500_IRQ_BASE		IRQ_BOARD_START
+#define MOP500_AB8500_IRQ_END		(MOP500_AB8500_IRQ_BASE \
+					 + AB8500_NR_IRQS)
+#define MOP500_IRQ_END			MOP500_AB8500_IRQ_END
+
+#if MOP500_IRQ_END > IRQ_BOARD_END
+#undef IRQ_BOARD_END
+#define IRQ_BOARD_END	MOP500_IRQ_END
+#endif
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index a6fb1fc..10385bd 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -79,6 +79,10 @@
 /* This will be overridden by board-specific irq headers */
 #define IRQ_BOARD_END			IRQ_BOARD_START
 
+#ifdef CONFIG_MACH_U8500_MOP
+#include <mach/irqs-board-mop500.h>
+#endif
+
 #define NR_IRQS				IRQ_BOARD_END
 
 #endif /* ASM_ARCH_IRQS_H */
-- 
1.7.0



From lrg at slimlogic.co.uk  Fri Jun 18 06:29:24 2010
From: lrg at slimlogic.co.uk (Liam Girdwood)
Date: Fri, 18 Jun 2010 11:29:24 +0100
Subject: [PATCH] ASoC: Fix overflow bug in SOC_DOUBLE_R_SX_TLV
In-Reply-To: <1276829770-31557-1-git-send-email-redhatter@gentoo.org>
References: <20100618023810.GS7759@www.longlandclan.yi.org>
	<1276829770-31557-1-git-send-email-redhatter@gentoo.org>
Message-ID: <1276856964.3054.1.camel@odin>

On Fri, 2010-06-18 at 12:56 +1000, Stuart Longland wrote:
> When SX_TLV widgets are read, if the gain is set to a value below 0dB,
> the mixer control is erroniously read as being at maximum volume.
> 
> The value read out of the CODEC register is never sign-extended, and
> when the minimum value is subtracted (read; added, since the minimum is
> negative) the result is a number greater than the maximum allowed value
> for the control, and hence it saturates.
> 
> Solution: Mask the result so that it "wraps around", emulating
> sign-extension.
> 
> Signed-off-by: Stuart Longland <redhatter at gentoo.org>
> ---
>  sound/soc/soc-core.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
> index a82a797..0470288 100644
> --- a/sound/soc/soc-core.c
> +++ b/sound/soc/soc-core.c
> @@ -2400,8 +2400,8 @@ int snd_soc_get_volsw_2r_sx(struct snd_kcontrol *kcontrol,
>  	int val = snd_soc_read(codec, mc->reg) & mask;
>  	int valr = snd_soc_read(codec, mc->rreg) & mask;
>  
> -	ucontrol->value.integer.value[0] = ((val & 0xff)-min);
> -	ucontrol->value.integer.value[1] = ((valr & 0xff)-min);
> +	ucontrol->value.integer.value[0] = ((val & 0xff)-min) & mask;
> +	ucontrol->value.integer.value[1] = ((valr & 0xff)-min) & mask;
>  	return 0;
>  }
>  EXPORT_SYMBOL_GPL(snd_soc_get_volsw_2r_sx);

Acked-by: Liam Girdwood <lrg at slimlogic.co.uk>
-- 
Freelance Developer, SlimLogic Ltd
ASoC and Voltage Regulator Maintainer.
http://www.slimlogic.co.uk



From sshtylyov at mvista.com  Fri Jun 18 06:55:38 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 18 Jun 2010 14:55:38 +0400
Subject: [PATCH 1/5] [ARM] implement arch_randomize_brk()
In-Reply-To: <1276720403-27918-2-git-send-email-nico@fluxnic.net>
References: <1276720403-27918-1-git-send-email-nico@fluxnic.net>
	<1276720403-27918-2-git-send-email-nico@fluxnic.net>
Message-ID: <4C1B50AA.9050507@ru.mvista.com>

Hello.

Nicolas Pitre wrote:

> For this feature to take effect, CONFIG_COMPAT_BRK must be turned
> off.  This can safely be turned off for any EABI user space versions.

> Signed-off-by: Nicolas Pitre <nicolas.pitre at linaro.org>
[...]
> diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
> index 51662fe..0a96e8c 100644
> --- a/arch/arm/include/asm/elf.h
> +++ b/arch/arm/include/asm/elf.h
> @@ -121,4 +121,7 @@ int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
>  extern void elf_set_personality(const struct elf32_hdr *);
>  #define SET_PERSONALITY(ex)	elf_set_personality(&(ex))
>  
> +extern unsigned long arch_randomize_brk(struct mm_struct *mm);
> +#define arch_randomize_brk arch_randomize_brk

    Isn't this an "infinitely recursive" macro?

WBR, Sergei


From kgene.kim at samsung.com  Fri Jun 18 07:00:10 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 18 Jun 2010 20:00:10 +0900
Subject: Several questions regarding ARCH_S3C2410
In-Reply-To: <20100618090042.GY3498@trinity.fluff.org>
References: <AANLkTimPk6mtyB57jXuAq1ugQseS655OCPEuP9-qZYoT@mail.gmail.com>
	<AANLkTilbEYR28lrVBAIXXuJ6sEf5uCp4Tpr7wriBZLj3@mail.gmail.com>
	<20100618090042.GY3498@trinity.fluff.org>
Message-ID: <005d01cb0ed5$6bb83b90$4328b2b0$%kim@samsung.com>

Ben Dooks wrote:
> 
> On Fri, Jun 18, 2010 at 04:44:59PM +0900, Kyungmin Park wrote:
> > CCing Mr. Kim
> 
> not sure it really needs him to be involved at-all
> 
I'd like to focus on S5P SoCs and Samsung common(plat-samsung) :-)

And maybe Ben is more interested in S3C SoCs and Samsung common.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From sshtylyov at mvista.com  Fri Jun 18 06:59:27 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 18 Jun 2010 14:59:27 +0400
Subject: [PATCH] MAINTAINERS: some Atmel drivers change maintainer
In-Reply-To: <1276694487-20065-1-git-send-email-nicolas.ferre@atmel.com>
References: <1276694487-20065-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <4C1B518F.4090307@ru.mvista.com>

Hello.

Nicolas Ferre wrote:

> I take over the maintenance of SPI, USART, Ethernet and USB gadget drivers.
> Those drivers are found in Atmel microcontrollers, both AT32/AVR32 and
> AT91/ARM.

> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
> Acked-by: Haavard Skinnemoen <haavard.skinnemoen at atmel.com>
> ---
>  MAINTAINERS |   10 +++++-----
>  1 files changed, 5 insertions(+), 5 deletions(-)

> diff --git a/MAINTAINERS b/MAINTAINERS
> index 6d119c9..5f71809 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1148,7 +1148,7 @@ F:	drivers/mmc/host/atmel-mci.c
[...]
>  ATMEL USBA UDC DRIVER
> -M:	Haavard Skinnemoen <hskinnemoen at atmel.com>
> -L:	kernel at avr32linux.org
> +M:	Nicolas Ferre <nicolas.ferre at atmel.com>
> +L:	linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)

    Not linux-usb at vger.kernel.org?

WBR, Sergei



From lrg at slimlogic.co.uk  Fri Jun 18 07:01:02 2010
From: lrg at slimlogic.co.uk (Liam Girdwood)
Date: Fri, 18 Jun 2010 12:01:02 +0100
Subject: [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
In-Reply-To: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
References: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
Message-ID: <1276858862.3054.28.camel@odin>

On Fri, 2010-06-18 at 13:57 +1000, Stuart Longland wrote:
> The TLV320AIC3204 is a low-power stereo audio CODEC capable of sample
> rates of up to 192kHz.  This driver implements basic functionality,
> using I?C for the control channel.
> 
> The audio interface supports many data bus formats, including I?S
> master/slave, DSP, left/right justified and TDM.
> 
> What works:
> 	- Playback at various bitrates up to 96kHz
> 	- Recording at various bitrates up to 96kHz
> 	- Mixer interface
> 	- PLL generation of CODEC clocks from MCLK
> 
> What could work better:
> 	- DAPM
> 
> What isn't tested:
> 	- Audio interfaces other than I?S
> 	- PLL with clocks other than ~12MHz
> 	- Mono recording/playback
> 	- 192kHz recording/playback
> 
> What isn't implemented:
> 	- SPI interface support
> 	- PLL without fractional divider (would allow <10MHz clocks)
> 	- Clock sources other than MCLK
> 	- Adaptive filtering
> 	- AGC
> 	- Headset detection, JACK framework
> 
> Signed-off-by: Stuart Longland <redhatter at gentoo.org>

Just had a quick check and the register caching needs addressed.

I agree with your comments, I don't think we really want to cache all
16K of codec registers here as we will probably only ever use a handful
of them. I think a smaller lookup table containing only the registers
that we care about will do.

Fwiw, a generic ASoC lookup table would be best as this could be used by
other codecs with large register maps too. The table should be ordered
(for quick lookup) and also contain a readable/writeable/volatile flag
for each register.

Thanks

Liam
-- 
Freelance Developer, SlimLogic Ltd
ASoC and Voltage Regulator Maintainer.
http://www.slimlogic.co.uk



From redhatter at gentoo.org  Fri Jun 18 07:33:35 2010
From: redhatter at gentoo.org (Stuart Longland)
Date: Fri, 18 Jun 2010 21:33:35 +1000
Subject: [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
In-Reply-To: <1276858862.3054.28.camel@odin>
References: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
	<1276858862.3054.28.camel@odin>
Message-ID: <20100618113335.GB30868@www.longlandclan.yi.org>

Hi,

To others: In case you're wondering where the patch is... I pulled it
from the moderation queue because there were a few style errors, and
some definitions I forgot to delete.  A fresh one that meets coding
style requirements is on its way, as soon as scripts/checkpatch.pl is
finished (this seems to take a while on my hardware).

On Fri, Jun 18, 2010 at 12:01:02PM +0100, Liam Girdwood wrote:
> On Fri, 2010-06-18 at 13:57 +1000, Stuart Longland wrote:
> > The TLV320AIC3204 is a low-power stereo audio CODEC capable of sample
> > rates of up to 192kHz.  This driver implements basic functionality,
> > using I??C for the control channel.
> > 
> > The audio interface supports many data bus formats, including I??S
> > master/slave, DSP, left/right justified and TDM.
> 
> Just had a quick check and the register caching needs addressed.
> 
> I agree with your comments, I don't think we really want to cache all
> 16K of codec registers here as we will probably only ever use a handful
> of them. I think a smaller lookup table containing only the registers
> that we care about will do.

Yeah, I wasn't sure how to go about it.  It's inefficient, but it's
simple, and works.  Other options I've considered;

(1) Mark's suggestion of using per-page arrays
(2) Using address translation. that is:
	- Page 0 registers 0-127 stored in cache array elements 0-127
	- Page 1 registers 0-127 stored in cache array elements 128-255
	- Page 2..7 are skipped
	- Page 8 registers 0-127 stored in cache array elements 256-383
	... etc.

> Fwiw, a generic ASoC lookup table would be best as this could be used by
> other codecs with large register maps too. The table should be ordered
> (for quick lookup) and also contain a readable/writeable/volatile flag
> for each register.

Indeed, the 'AIC3204 is not the only CODEC to use sparse register maps.
16KB is not a lot of RAM these days, but it's a lot more RAM than I'm
comfortable using for an audio driver.  I'll give this some thought, but
for now I'll press on with what I have since I know it works reliably.

Another thought regarding register cache, rather than hard-coding it the
way we presently do, we could also build up the cache on demand... that
is, we maintain a table of previously read registers; if a register
value is read for the first time, an actual read is done from the CODEC
(or the value is copied from a static table).  All subsequent reads then
come from cache.  On suspend; if a register has not been touched, it is
deemed to be left at default settings, and skipped on resume.

The downside of this is having to maintain a table of what registers
have been read already; which would possibly be as big as the cache is
anyway.  But the flip side; if a company brought out a new CODEC which
had differing power-up defaults to a similar CODEC handled by the same
driver, it would prevent the wrong default getting assumed or loaded in.
-- 
Stuart Longland (aka Redhatter, VK4MSL)      .'''.
Gentoo Linux/MIPS Cobalt and Docs Developer  '.'` :
. . . . . . . . . . . . . . . . . . . . . .   .'.'
http://dev.gentoo.org/~redhatter             :.'

I haven't lost my mind...
  ...it's backed up on a tape somewhere.


From jamie at shareable.org  Fri Jun 18 08:15:52 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Fri, 18 Jun 2010 13:15:52 +0100
Subject: [PATCH 1/5] [ARM] implement arch_randomize_brk()
In-Reply-To: <4C1B50AA.9050507@ru.mvista.com>
Message-ID: <20100618121552.GA19044@shareable.org>

Sergei Shtylyov wrote:
> >+extern unsigned long arch_randomize_brk(struct mm_struct *mm);
> >+#define arch_randomize_brk arch_randomize_brk
> 
>    Isn't this an "infinitely recursive" macro?

Not in ISO C.  It'll expand to itself and stop.  This is a handy trick
for confirming #ifdef tests elsewhere.  Glibc does it a lot for enums
defined in header files, for those which applications commonly test
with #ifdef because they were traditionally defined using macros.

-- Jamie


From Lorenzo.Pieralisi at arm.com  Fri Jun 18 08:47:28 2010
From: Lorenzo.Pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 18 Jun 2010 13:47:28 +0100
Subject: Platform data with function pointers
In-Reply-To: <AANLkTikqONUs722_ev6hqfpJiehUq2qAGWGhmxg6WkTs@mail.gmail.com>
References: <-71663801230973480@unknownmsgid>
	<AANLkTikqONUs722_ev6hqfpJiehUq2qAGWGhmxg6WkTs@mail.gmail.com>
Message-ID: <000901cb0ee4$68e19e20$3aa4da60$@Pieralisi@arm.com>

Hi Grant,

Thank you for your feedback. I went for solution 2 below temporarily, but embedding data in the match table could be a better
solution, at least it is contained within the driver, it is a case-by-case choice. A couple of questions.

- platform_device dynamic allocation. How should the id field in platform_device be initialized at run-time with FDT (for now it is
set to -1 in of_device_register) ? 

Should we follow the methodology in the thread below where a memory mapped device defines its address space (reg) through indexes
into a range of the parent node and id becomes the offset field within a "chip-select - like" reg property ?

http://www.mail-archive.com/linuxppc-dev at lists.ozlabs.org/msg29921.html

I think chip-select addressing should be used if that is the way HW handles it. If the device is described through a memory-mapping,
ex. snippet follows:

serial at 101f2000 {
        compatible = "arm,pl011";
        reg = <0x101f2000 0x1000 >;
};

how id should be defined ? A property ? Translated somehow from the name ? we have to keep id for compatibility with existing
drivers in ARM tree.

- IMHO initializing the map_desc array (array used for MMU io mapping, see below) dynamically might be done using FDT. Its fields
cannot be "guessed" as the PHYS_OFFSET (but many addresses correspond to devices register file base address so there is a bit of
overlap here with devices node), because it is about mapping specific physical address ranges (mach specific).
The point is: the structure does not really describe HW (but on some platforms the virtual address is obtained through a common
macro applied to physical addresses, see below, which can be passed through FDT), so I reckon it is frowned upon and not acceptable.


struct map_desc {
	unsigned long virtual;
	unsigned long pfn;
	unsigned long length;
	unsigned int type;
};

static struct map_desc realview_eb_io_desc[] __initdata = {
	{
		.virtual	= IO_ADDRESS(REALVIEW_SYS_BASE),
		.pfn		= __phys_to_pfn(REALVIEW_SYS_BASE),
		.length		= SZ_4K,
		.type		= MT_DEVICE,
	}, ...


Comments very much welcome, thank you.  

Lorenzo



-----Original Message-----
From: glikely at secretlab.ca [mailto:glikely at secretlab.ca] On Behalf Of Grant Likely
Sent: Monday, June 14, 2010 6:32 PM
To: Lorenzo Pieralisi; devicetree-discuss; linux-arm-kernel at lists.infradead.org; Jeremy Kerr; Nicolas Pitre
Subject: Re: Platform data with function pointers

[cc'ing devicetree-discuss - this conversation should be kept on-list]

Hi Lorenzo,

On Mon, Jun 14, 2010 at 4:42 AM, Lorenzo Pieralisi
<Lorenzo.Pieralisi at arm.com> wrote:
> Hi Grant,
>
> Sorry to bother you, we had a chat about this at UDS, but I wanted to make sure I am doing it the PPC way.

Well, I wouldn't call it the PPC way.  PPC doesn't have a great
solution either.  A new approach is needed.  See below...

> When a platform_data pointer is initialized statically to a struct like e.g. the following:
> struct flash_platform_data {
> ? ? ? ?const char ? ? ?*map_name;
> ? ? ? ?const char ? ? ?*name;
> ? ? ? ?unsigned int ? ?width;
> ? ? ? ?int ? ? ? ? ? ? (*init)(void);
> ? ? ? ?void ? ? ? ? ? ?(*exit)(void);
> ? ? ? ?void ? ? ? ? ? ?(*set_vpp)(int on);
> ? ? ? ?void ? ? ? ? ? ?(*mmcontrol)(struct mtd_info *mtd, int sync_read);
> ? ? ? ?struct mtd_partition *parts;
> ? ? ? ?unsigned int ? ?nr_parts;
> };
>
> static struct flash_platform_data v2m_flash_data = {
> ? ? ? ?.map_name ? ? ? = "cfi_probe",
> ? ? ? ?.width ? ? ? ? ?= 4,
> ? ? ? ?.init ? ? ? ? ? = v2m_flash_init,
> ? ? ? ?.exit ? ? ? ? ? = v2m_flash_exit,
> ? ? ? ?.set_vpp ? ? ? ?= v2m_flash_set_vpp,
> };
>
> I think that the driver depending on a compatible property should initialize the platform_data pointer from FDT accordingly
> (dynamically, but there are function pointers in there, so they are not _really_ data). But how ? Do we compile in all existing
> static struct and pick off one depending on the compatible string ? Is there an example I can check in the PPC tree to port
drivers
> the _proper_ way ?

There isn't a full example, partially because powerpc has mostly
avoided anonymous function pointers up to this point, and partially
because we don't have a good mechanism for handling it.

To start with, I must state that I really dislike platform data
because it is an anonymous pointer passed from mach code to the device
driver.  There is absolutely no type checking, and lots of opportunity
for a mismatch between the provided structure and what the driver
things it is provided.  I'm far more interested in passing parseable
data to the driver.

That being said, I completely understand the need to pass
mach-specific function pointers to a driver, and there are situations
where it must be done.

There is no single _proper_ way, but there are a number of options
depending on the situation.

One option is to build the mach specific functions into the
of_match_table for the driver.  Almost exactly like your suggestion of
compiling them in and choosing the correct one based on the matched
compatible value.  This works best if the mach code is well contained
and doesn't have to interact with other parts of mach code..  It also
works well if a lot of machines share the same hooks.  It keeps all
the driver code together, but it can get very unwieldy if a lot of
platforms need to add their custom code to a driver.  An example of
this can be seen in drivers/char/xilinx_hwicap/xilinx_hwicap.c.  Look
for the hwicap_of_match table.

If the function pointer truly is a one-off that isn't going to be
shared by other mach code, then I see two options (in both cases, I'm
assuming that the normal OF mechanisms are used to register the
devices).

1) Create a global function pointer to be populated by mach code.
Drivers would call the function at .probe() time and pass in a pointer
to the data structure.  Machine-specific code can then populate it
with the correct driver data including the function pointers.  This
works, and it preserves type safety, but it also lacks taste.  It
feels like an ugly hack to me.

2) In mach code, register a bus notifier before calling
of_platform_bus_probe().  Doing so ensures that the mach callback gets
called before a driver gets bound to the device.  Then mach code can
allocate and attach the correct platform data.  (See device_add() in
driver/base/core.c.  The bus notifiers get called before the driver is
probed with bus_probe_device()).  This solution is more elegant to me,
but it still has the problem of no type safety on the platform_data
pointer.

I'm open to other ideas on this if anyone else has a suggestion.

g.




From nicolas.ferre at atmel.com  Fri Jun 18 09:09:12 2010
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Fri, 18 Jun 2010 15:09:12 +0200
Subject: [PATCH] MAINTAINERS: some Atmel drivers change maintainer
In-Reply-To: <4C1B518F.4090307@ru.mvista.com>
References: <1276694487-20065-1-git-send-email-nicolas.ferre@atmel.com>
	<4C1B518F.4090307@ru.mvista.com>
Message-ID: <4C1B6FF8.1060504@atmel.com>

Le 18/06/2010 12:59, Sergei Shtylyov :
> Hello.
> 
> Nicolas Ferre wrote:
> 
>> I take over the maintenance of SPI, USART, Ethernet and USB gadget
>> drivers.
>> Those drivers are found in Atmel microcontrollers, both AT32/AVR32 and
>> AT91/ARM.
> 
>> Signed-off-by: Nicolas Ferre <nicolas.ferre at atmel.com>
>> Acked-by: Haavard Skinnemoen <haavard.skinnemoen at atmel.com>
>> ---
>>  MAINTAINERS |   10 +++++-----
>>  1 files changed, 5 insertions(+), 5 deletions(-)
> 
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 6d119c9..5f71809 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1148,7 +1148,7 @@ F:    drivers/mmc/host/atmel-mci.c
> [...]
>>  ATMEL USBA UDC DRIVER
>> -M:    Haavard Skinnemoen <hskinnemoen at atmel.com>
>> -L:    kernel at avr32linux.org
>> +M:    Nicolas Ferre <nicolas.ferre at atmel.com>
>> +L:    linux-arm-kernel at lists.infradead.org (moderated for
>> non-subscribers)
> 
>    Not linux-usb at vger.kernel.org?

The problem is that I am not subscribing to it at the moment...
Maybe I should add it to the USBA driver entry...

Best regards,
-- 
Nicolas Ferre



From linux at arm.linux.org.uk  Fri Jun 18 09:13:01 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 18 Jun 2010 14:13:01 +0100
Subject: Platform data with function pointers
In-Reply-To: <000901cb0ee4$68e19e20$3aa4da60$@Pieralisi@arm.com>
References: <-71663801230973480@unknownmsgid>
	<AANLkTikqONUs722_ev6hqfpJiehUq2qAGWGhmxg6WkTs@mail.gmail.com>
	<000901cb0ee4$68e19e20$3aa4da60$@Pieralisi@arm.com>
Message-ID: <20100618131301.GA21333@n2100.arm.linux.org.uk>

On Fri, Jun 18, 2010 at 01:47:28PM +0100, Lorenzo Pieralisi wrote:
> I think chip-select addressing should be used if that is the way HW handles it. If the device is described through a memory-mapping,
> ex. snippet follows:
> 
> serial at 101f2000 {
>         compatible = "arm,pl011";
>         reg = <0x101f2000 0x1000 >;
> };

Primecell devices aren't platform devices.  They have no 'id' field as
such.  Instead, modern implementations have PCI-like IDs.

> struct map_desc {
> 	unsigned long virtual;
> 	unsigned long pfn;
> 	unsigned long length;
> 	unsigned int type;
> };
> 
> static struct map_desc realview_eb_io_desc[] __initdata = {
> 	{
> 		.virtual	= IO_ADDRESS(REALVIEW_SYS_BASE),
> 		.pfn		= __phys_to_pfn(REALVIEW_SYS_BASE),
> 		.length		= SZ_4K,
> 		.type		= MT_DEVICE,
> 	}, ...

These mappings are entirely arbitary, and change according to the
implementation of the platform.

Some platforms want to avoid using ioremap() to create 4K page mappings
for their devices, so instead they statically map them and arrange for
ioremap() to know about that static mapping.

Given that PAGE_OFFSET can be changed, it would be absolutely silly to
put this into the device tree.


From viresh.kumar at st.com  Fri Jun 18 09:33:43 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Fri, 18 Jun 2010 19:03:43 +0530
Subject: Query dw_dmac driver: All descriptors done, but channel not idle!
Message-ID: <4C1B75B7.1080104@st.com>

Hello,

We have Synopsys Designware DMAC Controller on ST SPEAr13xx platform.
When i run dmatest for all 8 channels then i see following error some times.

"dma dma0chan7: BUG: All descriptors done, but channel not idle!"

I saw the code in driver, and i think it looks to be a known issue for this
peripheral, that's why special handling is done in driver.

Can somebody please confirm, if it a known issue or not? Or if there
are some solutions for this problem.

viresh.


From nico at fluxnic.net  Fri Jun 18 09:39:17 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 18 Jun 2010 09:39:17 -0400 (EDT)
Subject: Several questions regarding ARCH_S3C2410
In-Reply-To: <AANLkTin8g1jSGvju_-7rctjw0PTuunSKDivS1_yxp_lS@mail.gmail.com>
References: <AANLkTimPk6mtyB57jXuAq1ugQseS655OCPEuP9-qZYoT@mail.gmail.com>
	<20100618090010.GX3498@trinity.fluff.org>
	<AANLkTin8g1jSGvju_-7rctjw0PTuunSKDivS1_yxp_lS@mail.gmail.com>
Message-ID: <alpine.LFD.2.00.1006180937280.13427@xanadu.home>

On Fri, 18 Jun 2010, Eric Miao wrote:

> On Fri, Jun 18, 2010 at 5:00 PM, Ben Dooks <ben-linux at fluff.org> wrote:
> > On Fri, Jun 18, 2010 at 11:43:37AM +0800, Eric Miao wrote:
> >> Hi Ben,
> >>
> >> While working towards a unified kernel, I found that ARCH_S3C2410 actually
> >> includes multiple mach-* already.
> >>
> >> linux-2.6$ git grep "ARCH_S3C2410" arch/arm/Makefile
> >> arch/arm/Makefile:machine-$(CONFIG_ARCH_S3C2410) ? ? ?:= s3c2410 s3c2400
> >> s3c2412 s3c2416 s3c2440 s3c2443
> >>
> >> There are several questions though:
> >>
> >> 1. It looks like only s3c2410 is significant, so all the common definitions
> >> ? ?like PHYS_OFFSET are actually same across all mach-s3c24* (except for
> >> ? ?s3c24a0) ? Yet I've found arch/arm/mach-s3c2400/include/mach/memory.h,
> >> ? ?where a different PHYS_OFFSET is defined, just feel a bit confused.
> >
> > You can safely ignore the s3c24a0 for the moment, there's no-one interested
> > in actually getting it submitted.
> 
> Grrr... indeed.Looking into mach-s3c24a0, it's almost empty except for some
> header files.

What about simply removing that useless stuff from the tree then?

It could always be retrieved from the Git history if someone wants to 
revive it.


Nicolas

From haavard.skinnemoen at atmel.com  Fri Jun 18 09:52:34 2010
From: haavard.skinnemoen at atmel.com (Haavard Skinnemoen)
Date: Fri, 18 Jun 2010 15:52:34 +0200
Subject: Query dw_dmac driver: All descriptors done, but channel not idle!
In-Reply-To: <4C1B75B7.1080104@st.com>
References: <4C1B75B7.1080104@st.com>
Message-ID: <20100618155234.1fc40ce7@hskinnemoen-d830>

Viresh KUMAR <viresh.kumar at st.com> wrote:
> Can somebody please confirm, if it a known issue or not? Or if there
> are some solutions for this problem.

I'm not aware of any such issue. The code was added as a purely
defensive thing; when writing it, I just thought about what might
happen if we go through all our descriptors without finding the current
one, and added some code to report the issue and try to recover.

I suppose it might be caused by some issue with the peripheral itself,
but I think it's more likely to be caused by some race condition in the
driver, i.e. something goes wrong when inserting or removing
descriptors in the chain.

What might be very good to know at this point is the value of
the llp variable, and perhaps also the value of the CH_EN register to
see if the channel is idle or not.

Haavard


From viresh.kumar at st.com  Fri Jun 18 09:56:02 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Fri, 18 Jun 2010 19:26:02 +0530
Subject: Query dw_dmac driver: All descriptors done, but channel not idle!
In-Reply-To: <20100618155234.1fc40ce7@hskinnemoen-d830>
References: <4C1B75B7.1080104@st.com>
	<20100618155234.1fc40ce7@hskinnemoen-d830>
Message-ID: <4C1B7AF2.1060500@st.com>

On 6/18/2010 7:22 PM, Haavard Skinnemoen wrote:
> Viresh KUMAR <viresh.kumar at st.com> wrote:
>> Can somebody please confirm, if it a known issue or not? Or if there
>> are some solutions for this problem.
> 
> I'm not aware of any such issue. The code was added as a purely
> defensive thing; when writing it, I just thought about what might
> happen if we go through all our descriptors without finding the current
> one, and added some code to report the issue and try to recover.
> 
> I suppose it might be caused by some issue with the peripheral itself,
> but I think it's more likely to be caused by some race condition in the
> driver, i.e. something goes wrong when inserting or removing
> descriptors in the chain.
> 
> What might be very good to know at this point is the value of
> the llp variable, and perhaps also the value of the CH_EN register to
> see if the channel is idle or not.
> 

Thanks Haavard,

Will debug it further.

viresh.


From jason77.wang at gmail.com  Fri Jun 18 10:06:34 2010
From: jason77.wang at gmail.com (jason)
Date: Fri, 18 Jun 2010 22:06:34 +0800
Subject: [PATCH 1/2] mxc: add common debug board for 3-stack platforms
In-Reply-To: <20100616065540.GI20799@pengutronix.de>
References: <1276352707-8199-1-git-send-email-jason77.wang@gmail.com>
	<1276352707-8199-2-git-send-email-jason77.wang@gmail.com>
	<20100616065540.GI20799@pengutronix.de>
Message-ID: <4C1B7D6A.4010301@gmail.com>

Sascha Hauer wrote:
> On Sat, Jun 12, 2010 at 10:25:06PM +0800, Jason Wang wrote:
>   
>> The debug board is little different for all mxc 3-stack(PDK)
>> platforms, it is possible here to add a common implementation to
>> support this board.
>>     
>
> Two small things left:
>
> Could you change the name cpld_debugboard.c to something like
> 3ds_debugboard.c? That we are talking about the 3ds is much more
> interesting than that there's a cpld on the board.
>
> Also, I really prefer having no extra header file for the debug board.
> All information in this header file is only interesting in this single C
> file.
>
> Sascha
>
>
>   
Hi Sascha,

About the header file, most contents can be moved to c file,
but there are two declarations:

extern struct platform_device smsc_lan9217_device;
int __init mxc_expio_init(u32 base, u32 p_irq);

which will be used by board_mxNN_3ds.c, should i move them to mach/common.h and
drop 3ds_debugboard.h or keep them in 3ds_debugboard.h?

Thanks,
Jason.

>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>> ---
>>  arch/arm/plat-mxc/Kconfig                        |   11 ++
>>  arch/arm/plat-mxc/Makefile                       |    1 +
>>  arch/arm/plat-mxc/cpld_debugboard.c              |  161 ++++++++++++++++++++++
>>     
<snip>


From eric at eukrea.com  Fri Jun 18 10:19:54 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Fri, 18 Jun 2010 16:19:54 +0200
Subject: [PATCH 1/2] net/fec: clean suspend/resume
Message-ID: <1276870795-21594-1-git-send-email-eric@eukrea.com>

Commit 59d4289b83b11379d867e2f7146904b19cc96404 converted fec to dev_pm_ops but
didn't update the suspend/resume functions thus leading to the following warning :
"initialization from incompatible pointer type" when CONFIG_PM is set.

This patch also fixe a few indentation and style around CONFIG_PM area.

Signed-off-by: Eric B?nard <eric at eukrea.com>
Cc: netdev at vger.kernel.org
Cc: davem at davemloft.net
Cc: amit.kucheria at canonical.com
Cc: s.hauer at pengutronix.de
Cc: linux-arm-kernel at lists.infradead.org
---
 drivers/net/fec.c |   30 ++++++++++++------------------
 1 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/drivers/net/fec.c b/drivers/net/fec.c
index a3cae4e..b4afd7a 100644
--- a/drivers/net/fec.c
+++ b/drivers/net/fec.c
@@ -1360,11 +1360,10 @@ fec_drv_remove(struct platform_device *pdev)
 }
 
 #ifdef CONFIG_PM
-
 static int
-fec_suspend(struct platform_device *dev, pm_message_t state)
+fec_suspend(struct device *dev)
 {
-	struct net_device *ndev = platform_get_drvdata(dev);
+	struct net_device *ndev = dev_get_drvdata(dev);
 	struct fec_enet_private *fep;
 
 	if (ndev) {
@@ -1377,9 +1376,9 @@ fec_suspend(struct platform_device *dev, pm_message_t state)
 }
 
 static int
-fec_resume(struct platform_device *dev)
+fec_resume(struct device *dev)
 {
-	struct net_device *ndev = platform_get_drvdata(dev);
+	struct net_device *ndev = dev_get_drvdata(dev);
 	struct fec_enet_private *fep;
 
 	if (ndev) {
@@ -1399,23 +1398,18 @@ static const struct dev_pm_ops fec_pm_ops = {
 	.poweroff	= fec_suspend,
 	.restore	= fec_resume,
 };
-
-#define FEC_PM_OPS (&fec_pm_ops)
-
-#else /* !CONFIG_PM */
-
-#define FEC_PM_OPS NULL
-
-#endif /* !CONFIG_PM */
+#endif
 
 static struct platform_driver fec_driver = {
 	.driver	= {
-		.name    = "fec",
-		.owner	 = THIS_MODULE,
-		.pm		 = FEC_PM_OPS,
+		.name	= "fec",
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &fec_pm_ops,
+#endif
 	},
-	.probe   = fec_probe,
-	.remove  = __devexit_p(fec_drv_remove),
+	.probe	= fec_probe,
+	.remove	= __devexit_p(fec_drv_remove),
 };
 
 static int __init
-- 
1.6.3.3



From eric at eukrea.com  Fri Jun 18 10:19:55 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Fri, 18 Jun 2010 16:19:55 +0200
Subject: [PATCH 2/2] mach-cpuimx27: fix USB_ULPI build warnings
In-Reply-To: <1276870795-21594-1-git-send-email-eric@eukrea.com>
References: <1276870795-21594-1-git-send-email-eric@eukrea.com>
Message-ID: <1276870795-21594-2-git-send-email-eric@eukrea.com>

when CONFIG_USB_ULPI is not defined we actually get :
warning: 'otg_pdata' defined but not used
warning: 'usbh2_pdata' defined but not used

Signed-off-by: Eric B?nard <eric at eukrea.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: s.hauer at pengutronix.de
---
 arch/arm/mach-mx2/mach-cpuimx27.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-mx2/mach-cpuimx27.c
index dc2dca3..5529178 100644
--- a/arch/arm/mach-mx2/mach-cpuimx27.c
+++ b/arch/arm/mach-mx2/mach-cpuimx27.c
@@ -219,6 +219,7 @@ static struct platform_device serial_device = {
 };
 #endif
 
+#if defined(CONFIG_USB_ULPI)
 static struct mxc_usbh_platform_data otg_pdata = {
 	.portsc	= MXC_EHCI_MODE_ULPI,
 	.flags	= MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -228,6 +229,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
 	.portsc	= MXC_EHCI_MODE_ULPI,
 	.flags	= MXC_EHCI_INTERFACE_DIFF_UNI,
 };
+#endif
 
 static struct fsl_usb2_platform_data otg_device_pdata = {
 	.operating_mode = FSL_USB2_DR_DEVICE,
-- 
1.6.3.3



From kmpark at infradead.org  Fri Jun 18 10:21:30 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Fri, 18 Jun 2010 23:21:30 +0900
Subject: Several questions regarding ARCH_S3C2410
In-Reply-To: <005d01cb0ed5$6bb83b90$4328b2b0$%kim@samsung.com>
References: <AANLkTimPk6mtyB57jXuAq1ugQseS655OCPEuP9-qZYoT@mail.gmail.com>
	<AANLkTilbEYR28lrVBAIXXuJ6sEf5uCp4Tpr7wriBZLj3@mail.gmail.com>
	<20100618090042.GY3498@trinity.fluff.org>
	<005d01cb0ed5$6bb83b90$4328b2b0$%kim@samsung.com>
Message-ID: <AANLkTinzTIxh06xDCcl34P5QhGS1nSHvrlmmQWWeISrW@mail.gmail.com>

Then how about to prepare the these activities.

Next time we will use the s5pc210 (or whatever) and I hope to use it
with s5pc110.
To to this how about to merge the s5p series?

I suggest to read the OMAP mailing list how to support OMAP2, 3, and 4
with single kernel.

Thank you,
Kyungmin Park

On Fri, Jun 18, 2010 at 8:00 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Ben Dooks wrote:
>>
>> On Fri, Jun 18, 2010 at 04:44:59PM +0900, Kyungmin Park wrote:
>> > CCing Mr. Kim
>>
>> not sure it really needs him to be involved at-all
>>
> I'd like to focus on S5P SoCs and Samsung common(plat-samsung) :-)
>
> And maybe Ben is more interested in S3C SoCs and Samsung common.
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>


From Lorenzo.Pieralisi at arm.com  Fri Jun 18 10:25:43 2010
From: Lorenzo.Pieralisi at arm.com (Lorenzo Pieralisi)
Date: Fri, 18 Jun 2010 15:25:43 +0100
Subject: Platform data with function pointers
In-Reply-To: <20100618131301.GA21333@n2100.arm.linux.org.uk>
References: <-71663801230973480@unknownmsgid>
	<AANLkTikqONUs722_ev6hqfpJiehUq2qAGWGhmxg6WkTs@mail.gmail.com>
	<000901cb0ee4$68e19e20$3aa4da60$@Pieralisi@arm.com>
	<20100618131301.GA21333@n2100.arm.linux.org.uk>
Message-ID: <000a01cb0ef2$23160030$69420090$@Pieralisi@arm.com>

Concerning platform_devices ids, sorry I wasn't meant to report an amba primecell binding snippet, I wanted to report here just a
binding for a simple memory mapped platform device (not a primecell one). I was asking that question about platform_device
statically defined structs that use the id for enumeration, and going with FDT the id has to be initialized somehow from the tree
because the struct is allocated dynamically.

Wrt map_desc point taken, I was looking into possible ways of getting rid of platform specific statically defined data, that array
in particular.

Thanks a lot for your feedback,

Lorenzo

-----Original Message-----
From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk] 
Sent: Friday, June 18, 2010 2:13 PM
To: Lorenzo Pieralisi
Cc: 'Grant Likely'; devicetree-discuss; linux-arm-kernel at lists.infradead.org; Jeremy Kerr; Nicolas Pitre
Subject: Re: Platform data with function pointers

On Fri, Jun 18, 2010 at 01:47:28PM +0100, Lorenzo Pieralisi wrote:
> I think chip-select addressing should be used if that is the way HW handles it. If the device is described through a
memory-mapping,
> ex. snippet follows:
> 
> serial at 101f2000 {
>         compatible = "arm,pl011";
>         reg = <0x101f2000 0x1000 >;
> };

Primecell devices aren't platform devices.  They have no 'id' field as
such.  Instead, modern implementations have PCI-like IDs.

> struct map_desc {
> 	unsigned long virtual;
> 	unsigned long pfn;
> 	unsigned long length;
> 	unsigned int type;
> };
> 
> static struct map_desc realview_eb_io_desc[] __initdata = {
> 	{
> 		.virtual	= IO_ADDRESS(REALVIEW_SYS_BASE),
> 		.pfn		= __phys_to_pfn(REALVIEW_SYS_BASE),
> 		.length		= SZ_4K,
> 		.type		= MT_DEVICE,
> 	}, ...

These mappings are entirely arbitary, and change according to the
implementation of the platform.

Some platforms want to avoid using ioremap() to create 4K page mappings
for their devices, so instead they statically map them and arrange for
ioremap() to know about that static mapping.

Given that PAGE_OFFSET can be changed, it would be absolutely silly to
put this into the device tree.




From eric.y.miao at gmail.com  Fri Jun 18 10:28:50 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 22:28:50 +0800
Subject: Several questions regarding ARCH_S3C2410
In-Reply-To: <AANLkTinzTIxh06xDCcl34P5QhGS1nSHvrlmmQWWeISrW@mail.gmail.com>
References: <AANLkTimPk6mtyB57jXuAq1ugQseS655OCPEuP9-qZYoT@mail.gmail.com> 
	<AANLkTilbEYR28lrVBAIXXuJ6sEf5uCp4Tpr7wriBZLj3@mail.gmail.com> 
	<20100618090042.GY3498@trinity.fluff.org>
	<005d01cb0ed5$6bb83b90$4328b2b0$%kim@samsung.com> 
	<AANLkTinzTIxh06xDCcl34P5QhGS1nSHvrlmmQWWeISrW@mail.gmail.com>
Message-ID: <AANLkTillhXSrUKpyOzg6zXA2DCwQmgQyNVH0bd4-lMcy@mail.gmail.com>

On Fri, Jun 18, 2010 at 10:21 PM, Kyungmin Park <kmpark at infradead.org> wrote:
> Then how about to prepare the these activities.
>
> Next time we will use the s5pc210 (or whatever) and I hope to use it
> with s5pc110.

Better merge them into one, no more mach-* is recommended unless that's
inevitable.

> To to this how about to merge the s5p series?
>
> I suggest to read the OMAP mailing list how to support OMAP2, 3, and 4
> with single kernel.
>

Not necessary maybe. Just post your difficulties when merging them
into a single kernel and we can discuss.


From eric.y.miao at gmail.com  Fri Jun 18 10:33:32 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 18 Jun 2010 22:33:32 +0800
Subject: Platform data with function pointers
In-Reply-To: <-8400781325900388878@unknownmsgid>
References: <-71663801230973480@unknownmsgid>
	<AANLkTikqONUs722_ev6hqfpJiehUq2qAGWGhmxg6WkTs@mail.gmail.com> 
	<20100618131301.GA21333@n2100.arm.linux.org.uk>
	<-8400781325900388878@unknownmsgid>
Message-ID: <AANLkTik4B8yyxWDbN4J7aWXb7v3HGkAabaRdyIAzmnGC@mail.gmail.com>

On Fri, Jun 18, 2010 at 10:25 PM, Lorenzo Pieralisi
<Lorenzo.Pieralisi at arm.com> wrote:
> Concerning platform_devices ids, sorry I wasn't meant to report an amba primecell binding snippet, I wanted to report here just a
> binding for a simple memory mapped platform device (not a primecell one). I was asking that question about platform_device
> statically defined structs that use the id for enumeration, and going with FDT the id has to be initialized somehow from the tree
> because the struct is allocated dynamically.
>
> Wrt map_desc point taken, I was looking into possible ways of getting rid of platform specific statically defined data, that array
> in particular.
>

That's actually quite challenging. And as DT is used to 'describe' the hardware
as is, instead of directing the software how to do a mapping, I doubt
this should
be done with DT.

> Thanks a lot for your feedback,
>
> Lorenzo
>
> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux at arm.linux.org.uk]
> Sent: Friday, June 18, 2010 2:13 PM
> To: Lorenzo Pieralisi
> Cc: 'Grant Likely'; devicetree-discuss; linux-arm-kernel at lists.infradead.org; Jeremy Kerr; Nicolas Pitre
> Subject: Re: Platform data with function pointers
>
> On Fri, Jun 18, 2010 at 01:47:28PM +0100, Lorenzo Pieralisi wrote:
>> I think chip-select addressing should be used if that is the way HW handles it. If the device is described through a
> memory-mapping,
>> ex. snippet follows:
>>
>> serial at 101f2000 {
>> ? ? ? ? compatible = "arm,pl011";
>> ? ? ? ? reg = <0x101f2000 0x1000 >;
>> };
>
> Primecell devices aren't platform devices. ?They have no 'id' field as
> such. ?Instead, modern implementations have PCI-like IDs.
>
>> struct map_desc {
>> ? ? ? unsigned long virtual;
>> ? ? ? unsigned long pfn;
>> ? ? ? unsigned long length;
>> ? ? ? unsigned int type;
>> };
>>
>> static struct map_desc realview_eb_io_desc[] __initdata = {
>> ? ? ? {
>> ? ? ? ? ? ? ? .virtual ? ? ? ?= IO_ADDRESS(REALVIEW_SYS_BASE),
>> ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(REALVIEW_SYS_BASE),
>> ? ? ? ? ? ? ? .length ? ? ? ? = SZ_4K,
>> ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
>> ? ? ? }, ...
>
> These mappings are entirely arbitary, and change according to the
> implementation of the platform.
>
> Some platforms want to avoid using ioremap() to create 4K page mappings
> for their devices, so instead they statically map them and arrange for
> ioremap() to know about that static mapping.
>
> Given that PAGE_OFFSET can be changed, it would be absolutely silly to
> put this into the device tree.
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From eric at eukrea.com  Fri Jun 18 10:37:23 2010
From: eric at eukrea.com (=?UTF-8?B?RXJpYyBCw6luYXJk?=)
Date: Fri, 18 Jun 2010 16:37:23 +0200
Subject: [PATCH v2] input/imx_keypad: add PM support
In-Reply-To: <1276856186.3146.5.camel@realization>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>
	<1276856186.3146.5.camel@realization>
Message-ID: <4C1B84A3.8080300@eukrea.com>

Hi Alberto,

Le 18/06/2010 12:16, Alberto Panizzo a ?crit :
> Ok, so with this patch the keypad cannot wake the system?
> It is scheduled another patch?
>
well, actually, the keypad wakes the system, at least on my board here.

I was quite surprised to get this working this way as I would have 
expected disable_irq + clk_disable would prevent the keypad from being a 
wake source.
Can you try on your board as this cleanup may be wrong on i.MX3 ?

Thanks,
Eric


From kmpark at infradead.org  Fri Jun 18 11:01:37 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Sat, 19 Jun 2010 00:01:37 +0900
Subject: Several questions regarding ARCH_S3C2410
In-Reply-To: <AANLkTillhXSrUKpyOzg6zXA2DCwQmgQyNVH0bd4-lMcy@mail.gmail.com>
References: <AANLkTimPk6mtyB57jXuAq1ugQseS655OCPEuP9-qZYoT@mail.gmail.com>
	<AANLkTilbEYR28lrVBAIXXuJ6sEf5uCp4Tpr7wriBZLj3@mail.gmail.com>
	<20100618090042.GY3498@trinity.fluff.org>
	<005d01cb0ed5$6bb83b90$4328b2b0$%kim@samsung.com>
	<AANLkTinzTIxh06xDCcl34P5QhGS1nSHvrlmmQWWeISrW@mail.gmail.com>
	<AANLkTillhXSrUKpyOzg6zXA2DCwQmgQyNVH0bd4-lMcy@mail.gmail.com>
Message-ID: <AANLkTikIDQS-3PABHovz_JM-ar47Gpn6OGoE35BVDRdw@mail.gmail.com>

On Fri, Jun 18, 2010 at 11:28 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 10:21 PM, Kyungmin Park <kmpark at infradead.org> wrote:
>> Then how about to prepare the these activities.
>>
>> Next time we will use the s5pc210 (or whatever) and I hope to use it
>> with s5pc110.
>
> Better merge them into one, no more mach-* is recommended unless that's
> inevitable.

Agree.

>
>> To to this how about to merge the s5p series?
>>
>> I suggest to read the OMAP mailing list how to support OMAP2, 3, and 4
>> with single kernel.
>>
>
> Not necessary maybe. Just post your difficulties when merging them
> into a single kernel and we can discuss.
>

I hope so, before starting this work, I make a consensus with ben and kukjin.
I like the OMAP style, runtime detection. IMHO Samsung SoCs goes like
these approaches.

Thank you,
Kyungmin Park


From langabe at gmail.com  Fri Jun 18 11:28:51 2010
From: langabe at gmail.com (Alex Gonzalez)
Date: Fri, 18 Jun 2010 17:28:51 +0200
Subject: Hung kernel on SD writeback while suspending to RAM
In-Reply-To: <4C1A4C74.1040008@eukrea.com>
References: <AANLkTikHHcnJygPWKAlDk4NWGBE_fxexeLt3WO0xea0M@mail.gmail.com> 
	<4C1A4C74.1040008@eukrea.com>
Message-ID: <AANLkTilNtj4Q2_-iQw6ncnkmYaO2hZKUTyhbjQlxv9iH@mail.gmail.com>

Hi Eric,

That indeed did the trick.

The Kconfig help confused me as I was neither removing the card from
the slot or booting from it.

Thanks a lot,
Alex

--------------------------------

If you say Y here, the MMC layer will assume that all cards
stayed in their respective slots during the suspend. The
normal behaviour is to remove them at suspend and
redetecting them at resume.

This option is usually just for embedded systems which use
a MMC/SD card for rootfs. Most people should say N here.


On Thu, Jun 17, 2010 at 6:25 PM, Eric B?nard <eric at eukrea.com> wrote:
> Hi,
>
> Le 15/06/2010 09:58, Alex Gonzalez a ?crit :
>>
>> I am looking into suspend to RAM on a Freescale MX51 running a 2.6.31
>> kernel. The
>> system suspends and resumes OK except when an SD card is mounted.
>>
>> What happens then is that it finds a page which is being written to disk
>> (writeback flag is set), so it waits forever in uninterruptible state
>> for the write to finish, which never happens.
>>
>> I was expecting the filesystem sync previous to the tasks freezing to
>> have written all page caches to disk.
>>
>> Any suggestion as to how to debug this forward?
>>
> I think you need to enable
> [ ] Assume MMC/SD cards are non-removable (DANGEROUS)
> in order to be able to suspend / resume a mounted SDCard.
>
> Eric
>


From broonie at opensource.wolfsonmicro.com  Fri Jun 18 11:53:23 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 18 Jun 2010 16:53:23 +0100
Subject: [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
In-Reply-To: <20100618113335.GB30868@www.longlandclan.yi.org>
References: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
	<1276858862.3054.28.camel@odin>
	<20100618113335.GB30868@www.longlandclan.yi.org>
Message-ID: <20100618155322.GB16941@rakim.wolfsonmicro.main>

On Fri, Jun 18, 2010 at 09:33:35PM +1000, Stuart Longland wrote:
> On Fri, Jun 18, 2010 at 12:01:02PM +0100, Liam Girdwood wrote:
> > On Fri, 2010-06-18 at 13:57 +1000, Stuart Longland wrote:

> > > The audio interface supports many data bus formats, including I??S
> > > master/slave, DSP, left/right justified and TDM.

> > Just had a quick check and the register caching needs addressed.

> > I agree with your comments, I don't think we really want to cache all
> > 16K of codec registers here as we will probably only ever use a handful
> > of them. I think a smaller lookup table containing only the registers
> > that we care about will do.

> Yeah, I wasn't sure how to go about it.  It's inefficient, but it's
> simple, and works.  Other options I've considered;

> (1) Mark's suggestion of using per-page arrays
> (2) Using address translation. that is:
> 	- Page 0 registers 0-127 stored in cache array elements 0-127
> 	- Page 1 registers 0-127 stored in cache array elements 128-255
> 	- Page 2..7 are skipped
> 	- Page 8 registers 0-127 stored in cache array elements 256-383
> 	... etc.

Option 2 is what others have used here.  I do think that anything we do
here really ought to have some sort of page mapping support whatever the
actual implementation it uses - TI in particular have a bunch of chips
which do this so there's a general call for something that can handle
them.

If you are going to do a lookup table one way of doing this would be to
have the lookup table be a table of range mappings (I've not looked at
the patch, perhaps that's what you've done already) - just so long as
it's got the concept of pages covered somehow.

> Another thought regarding register cache, rather than hard-coding it the
> way we presently do, we could also build up the cache on demand... that
> is, we maintain a table of previously read registers; if a register
> value is read for the first time, an actual read is done from the CODEC
> (or the value is copied from a static table).  All subsequent reads then
> come from cache.  On suspend; if a register has not been touched, it is
> deemed to be left at default settings, and skipped on resume.

The only problem with this is that for a number of reasons a lot of
devices have no read functionality at all.  These need us to supply the
defaults from outside the device, though other devices could use what
you suggest.  I'd not be so bothered about the performance here - this
has to be high performance in comparison with doing I/O on a slow bus
such as I2C.  If we do run into performance issues we can always work on
substituting in a higher performance algorithm later, if everything is
well encapsulated this should be doable without much disruption.

It's also useful to have the actual defaults available for allowing
writes to be skipped when powering up the device (eg, on resume) - these
could be cached on first write so it's not insurmountable but it does
need to be considered.

> The downside of this is having to maintain a table of what registers
> have been read already; which would possibly be as big as the cache is
> anyway.  But the flip side; if a company brought out a new CODEC which
> had differing power-up defaults to a similar CODEC handled by the same
> driver, it would prevent the wrong default getting assumed or loaded in.

I'm not sure that's a big risk to be honest - the reuse you see tends to
be much more complete than this.


From john.ogness at linutronix.de  Fri Jun 18 12:58:59 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Fri, 18 Jun 2010 18:58:59 +0200
Subject: [PATCH 0/5] mtd: mxc_nand fixups
Message-ID: <80ljacb7l8.fsf@merkur.tec.linutronix.de>

Hi,

The following 5 patches fix several issues with the MXC NFC
driver. These changes were tested using an i.MX35 with a 16-bit flash
chip (2K pages, 64 pages per eraseblock).

Many of the changes are sitting behind a nfc_is_v21() check because I do
not know if the older NAND controllers are the same.

John Ogness


From john.ogness at linutronix.de  Fri Jun 18 12:59:47 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Fri, 18 Jun 2010 18:59:47 +0200
Subject: [PATCH 1/5] mtd: mxc_nand fixups
Message-ID: <80hbl0b7jw.fsf@merkur.tec.linutronix.de>

This patch avoids byte access to the NFC buffer. Byte access to the
NFC is not allowed.

The patch is against linux-next 20100618.

Signed-off-by: John Ogness <john.ogness at linutronix.de>
---
 drivers/mtd/nand/mxc_nand.c |   14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

Index: linux-next-20100618/drivers/mtd/nand/mxc_nand.c
===================================================================
--- linux-next-20100618.orig/drivers/mtd/nand/mxc_nand.c
+++ linux-next-20100618/drivers/mtd/nand/mxc_nand.c
@@ -289,16 +289,16 @@ static void send_read_id(struct mxc_nand
 	/* Wait for operation to complete */
 	wait_op_done(host, true);
 
+	memcpy(host->data_buf, host->main_area0, 16);
+
 	if (this->options & NAND_BUSWIDTH_16) {
-		void __iomem *main_buf = host->main_area0;
 		/* compress the ID info */
-		writeb(readb(main_buf + 2), main_buf + 1);
-		writeb(readb(main_buf + 4), main_buf + 2);
-		writeb(readb(main_buf + 6), main_buf + 3);
-		writeb(readb(main_buf + 8), main_buf + 4);
-		writeb(readb(main_buf + 10), main_buf + 5);
+		host->data_buf[1] = host->data_buf[2];
+		host->data_buf[2] = host->data_buf[4];
+		host->data_buf[3] = host->data_buf[6];
+		host->data_buf[4] = host->data_buf[8];
+		host->data_buf[5] = host->data_buf[10];
 	}
-	memcpy(host->data_buf, host->main_area0, 16);
 }
 
 /* This function requests the NANDFC to perform a read of the


From john.ogness at linutronix.de  Fri Jun 18 13:00:27 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Fri, 18 Jun 2010 19:00:27 +0200
Subject: [PATCH 2/5] mtd: mxc_nand fixups
Message-ID: <80d3vob7is.fsf@merkur.tec.linutronix.de>

This patch sets the NFC registers for spare size and pages per block.
For NFCv21 it also sets the ECC mode to 4-bit, since this driver only
supports up to 16 OOB bytes per 512 data bytes.

The patch is against linux-next 20100618.

Signed-off-by: John Ogness <john.ogness at linutronix.de>
---
 drivers/mtd/nand/mxc_nand.c |   48 +++++++++++++++++++++++++++++++++-
 1 file changed, 47 insertions(+), 1 deletion(-)

Index: linux-next-20100618/drivers/mtd/nand/mxc_nand.c
===================================================================
--- linux-next-20100618.orig/drivers/mtd/nand/mxc_nand.c
+++ linux-next-20100618/drivers/mtd/nand/mxc_nand.c
@@ -86,6 +86,7 @@
  * Status operation */
 #define NFC_INT            0x8000
 
+#define NFC_ECC_4BIT        (1 << 0)
 #define NFC_SP_EN           (1 << 2)
 #define NFC_ECC_EN          (1 << 3)
 #define NFC_INT_MSK         (1 << 4)
@@ -94,6 +95,11 @@
 #define NFC_CE              (1 << 7)
 #define NFC_ONE_CYCLE       (1 << 8)
 
+#define NFC_PPB_SHIFT       9
+#define NFC_PPB_MASK        (3 << NFC_PPB_SHIFT)
+
+#define NFC_RSLTSPARE_AREA_MASK  0xff
+
 struct mxc_nand_host {
 	struct mtd_info		mtd;
 	struct nand_chip	nand;
@@ -557,21 +563,35 @@ static void preset(struct mtd_info *mtd)
 	struct mxc_nand_host *host = nand_chip->priv;
 	uint16_t tmp;
 
-	/* enable interrupt, disable spare enable */
+	/* enable interrupt, disable spare enable, setup ECC */
 	tmp = readw(host->regs + NFC_CONFIG1);
 	tmp &= ~NFC_INT_MSK;
 	tmp &= ~NFC_SP_EN;
 	if (nand_chip->ecc.mode == NAND_ECC_HW) {
 		tmp |= NFC_ECC_EN;
+
+		if (nfc_is_v21()) {
+			/* use 4-bit ECC mode */
+			tmp |= NFC_ECC_4BIT;
+		}
 	} else {
 		tmp &= ~NFC_ECC_EN;
 	}
 	writew(tmp, host->regs + NFC_CONFIG1);
+
 	/* preset operation */
 
 	/* Unlock the internal RAM Buffer */
 	writew(0x2, host->regs + NFC_CONFIG);
 
+	if (nfc_is_v21()) {
+		/* configure spare size (in 16-bit blocks) */
+		tmp = readw(host->regs + NFC_RSLTSPARE_AREA);
+		tmp &= ~NFC_RSLTSPARE_AREA_MASK;
+		tmp |= host->spare_len / 2;
+		writew(tmp, host->regs + NFC_RSLTSPARE_AREA);
+	}
+
 	/* Blocks to be unlocked */
 	if (nfc_is_v21()) {
 		writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
@@ -817,6 +837,32 @@ static int __init mxcnd_probe(struct pla
 		goto escan;
 	}
 
+	if (nfc_is_v21()) {
+		/* setup PPB */
+
+		uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
+		uint16_t tmp;
+
+		tmp = readw(host->regs + NFC_CONFIG1);
+		tmp &= ~NFC_PPB_MASK;
+		switch (pages_per_block) {
+		case 32:
+			/* PPB set to 0 */
+			break;
+		case 64:
+			tmp |= 1 << NFC_PPB_SHIFT;
+			break;
+		case 256:
+			tmp |= 3 << NFC_PPB_SHIFT;
+			break;
+		default:
+			/* 128 (reset value) */
+			tmp |= 2 << NFC_PPB_SHIFT;
+			break;
+		}
+		writew(tmp, host->regs + NFC_CONFIG1);
+	}
+
 	if (mtd->writesize == 2048)
 		this->ecc.layout = oob_largepage;
 


From john.ogness at linutronix.de  Fri Jun 18 13:01:03 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Fri, 18 Jun 2010 19:01:03 +0200
Subject: [PATCH 3/5] mtd: mxc_nand fixups
Message-ID: <808w6cb7hs.fsf@merkur.tec.linutronix.de>

This patch fixes how failures with the hardware ECC error correction
for the NFCv21 are detected.

The patch is against linux-next 20100618.

Signed-off-by: John Ogness <john.ogness at linutronix.de>
---
 drivers/mtd/nand/mxc_nand.c |   39 +++++++++++++++++++++++++---------
 1 file changed, 29 insertions(+), 10 deletions(-)

Index: linux-next-20100618/drivers/mtd/nand/mxc_nand.c
===================================================================
--- linux-next-20100618.orig/drivers/mtd/nand/mxc_nand.c
+++ linux-next-20100618/drivers/mtd/nand/mxc_nand.c
@@ -359,18 +359,37 @@ static int mxc_nand_correct_data(struct 
 	struct nand_chip *nand_chip = mtd->priv;
 	struct mxc_nand_host *host = nand_chip->priv;
 
-	/*
-	 * 1-Bit errors are automatically corrected in HW.  No need for
-	 * additional correction.  2-Bit errors cannot be corrected by
-	 * HW ECC, so we need to return failure
-	 */
 	uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
 
-	if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
-		DEBUG(MTD_DEBUG_LEVEL0,
-		      "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
-		return -1;
-	}
+	if (nfc_is_v21()) {
+		/*
+		 * Up to 8 9-bit symbol errors can be corrected by the HW.
+		 * A status value of 0xf means that an uncorrectable error
+		 * occurred, so we need to return failure.
+		 */
+		if ((ecc_status & 0xf) == 0xf ||
+		    ((ecc_status >> 4) & 0xf) == 0xf ||
+		    ((ecc_status >> 8) & 0xf) == 0xf ||
+		    ((ecc_status >> 12) & 0xf) == 0xf) {
+			DEBUG(MTD_DEBUG_LEVEL0,
+			      "MXC_NAND: "
+			      "HWECC uncorrectable ECC error\n");
+			return -1;
+		}
+	} else if (nfc_is_v1()) {
+		/*
+		 * 1-Bit errors are automatically corrected in HW. No need for
+		 * additional correction. 2-Bit errors cannot be corrected by
+		 * HW ECC, so we need to return failure.
+		 */
+		if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
+			DEBUG(MTD_DEBUG_LEVEL0,
+			      "MXC_NAND: "
+			      "HWECC uncorrectable 2-bit ECC error\n");
+			return -1;
+		}
+	} else
+		BUG();
 
 	return 0;
 }


From john.ogness at linutronix.de  Fri Jun 18 13:01:34 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Fri, 18 Jun 2010 19:01:34 +0200
Subject: [PATCH 4/5] mtd: mxc_nand fixups
Message-ID: <804oh0b7gx.fsf@merkur.tec.linutronix.de>

This patch reverts the driver to enabling/disabling the NFC interrupt
mask rather than enabling/disabling the system interrupt. This cleans
up the driver so that it doesn't rely on interrupts being disabled
within the interrupt handler.

The patch is against linux-next 20100618.

Signed-off-by: John Ogness <john.ogness at linutronix.de>
---
 drivers/mtd/nand/mxc_nand.c |   11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

Index: linux-next-20100618/drivers/mtd/nand/mxc_nand.c
===================================================================
--- linux-next-20100618.orig/drivers/mtd/nand/mxc_nand.c
+++ linux-next-20100618/drivers/mtd/nand/mxc_nand.c
@@ -173,8 +173,11 @@ static const char *part_probes[] = { "Re
 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 {
 	struct mxc_nand_host *host = dev_id;
+	uint16_t tmp;
 
-	disable_irq_nosync(irq);
+	tmp = readw(host->regs + NFC_CONFIG1);
+	tmp |= NFC_INT_MSK; /* disable NFC interrupts */
+	writew(tmp, host->regs + NFC_CONFIG1);
 
 	wake_up(&host->irq_waitq);
 
@@ -192,7 +195,9 @@ static void wait_op_done(struct mxc_nand
 	if (useirq) {
 		if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
 
-			enable_irq(host->irq);
+			tmp = readw(host->regs + NFC_CONFIG1);
+			tmp  &= ~NFC_INT_MSK;   /* enable NFC interrupts */
+			writew(tmp, host->regs + NFC_CONFIG1);
 
 			wait_event(host->irq_waitq,
 				readw(host->regs + NFC_CONFIG2) & NFC_INT);
@@ -846,7 +851,7 @@ static int __init mxcnd_probe(struct pla
 
 	host->irq = platform_get_irq(pdev, 0);
 
-	err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
+	err = request_irq(host->irq, mxc_nfc_irq, 0, DRIVER_NAME, host);
 	if (err)
 		goto eirq;
 


From john.ogness at linutronix.de  Fri Jun 18 13:02:03 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Fri, 18 Jun 2010 19:02:03 +0200
Subject: [PATCH 5/5] mtd: mxc_nand fixups
Message-ID: <80zkys9svo.fsf@merkur.tec.linutronix.de>

This patch removes some unused variable declarations.

The patch is against linux-next 20100618.

Signed-off-by: John Ogness <john.ogness at linutronix.de>
---
 drivers/mtd/nand/mxc_nand.c |    2 --
 1 file changed, 2 deletions(-)

Index: linux-next-20100618/drivers/mtd/nand/mxc_nand.c
===================================================================
--- linux-next-20100618.orig/drivers/mtd/nand/mxc_nand.c
+++ linux-next-20100618/drivers/mtd/nand/mxc_nand.c
@@ -967,8 +967,6 @@ static int mxcnd_suspend(struct platform
 static int mxcnd_resume(struct platform_device *pdev)
 {
 	struct mtd_info *mtd = platform_get_drvdata(pdev);
-	struct nand_chip *nand_chip = mtd->priv;
-	struct mxc_nand_host *host = nand_chip->priv;
 	int ret = 0;
 
 	DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");


From maramaopercheseimorto at gmail.com  Fri Jun 18 13:40:04 2010
From: maramaopercheseimorto at gmail.com (Alberto Panizzo)
Date: Fri, 18 Jun 2010 19:40:04 +0200
Subject: [PATCH v2] input/imx_keypad: add PM support
In-Reply-To: <4C1B84A3.8080300@eukrea.com>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>
	<1276856186.3146.5.camel@realization>  <4C1B84A3.8080300@eukrea.com>
Message-ID: <1276882804.3146.14.camel@realization>

On ven, 2010-06-18 at 16:37 +0200, Eric B?nard wrote:
> Hi Alberto,
> 
> Le 18/06/2010 12:16, Alberto Panizzo a ?crit :
> > Ok, so with this patch the keypad cannot wake the system?
> > It is scheduled another patch?
> >
> well, actually, the keypad wakes the system, at least on my board here.
> 
> I was quite surprised to get this working this way as I would have 
> expected disable_irq + clk_disable would prevent the keypad from being a 
> wake source.
> Can you try on your board as this cleanup may be wrong on i.MX3 ?
> 
> Thanks,
> Eric
Well.. it is a surprise to me too. I have to look down the documentation
ad soon I will try on the mx31pdk.
I don't wont to tell you wrong things.


-- 
Alberto!

        Be Persistent!
                - Greg Kroah-Hartman (FOSDEM 2010)



From eric at eukrea.com  Fri Jun 18 13:50:54 2010
From: eric at eukrea.com (=?UTF-8?B?RXJpYyBCw6luYXJk?=)
Date: Fri, 18 Jun 2010 19:50:54 +0200
Subject: [PATCH v2] input/imx_keypad: add PM support
In-Reply-To: <1276882804.3146.14.camel@realization>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>	
	<1276856186.3146.5.camel@realization> <4C1B84A3.8080300@eukrea.com>
	<1276882804.3146.14.camel@realization>
Message-ID: <4C1BB1FE.9090403@eukrea.com>

Le 18/06/2010 19:40, Alberto Panizzo a ?crit :
> Well.. it is a surprise to me too. I have to look down the documentation
> ad soon I will try on the mx31pdk.

OK, I'm waiting for your feedback on the mx31pdk.

 From my understanding of the documentation, in order to be able to 
wakeup the CPU, the interrupt of a peripheral and its clock should stay 
enabled while going to suspend.

Eric


From sameo at linux.intel.com  Fri Jun 18 14:04:20 2010
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Fri, 18 Jun 2010 20:04:20 +0200
Subject: [PATCH 02/05] mfd: enable onkey on max8925
In-Reply-To: <AANLkTiko7PRpnVlgsOwVHi5EjvEnpfEtC44zUnDMuQxp@mail.gmail.com>
References: <AANLkTiko7PRpnVlgsOwVHi5EjvEnpfEtC44zUnDMuQxp@mail.gmail.com>
Message-ID: <20100618180419.GB3582@sortiz.org>

Hi Haojian,

On Wed, May 19, 2010 at 02:57:17PM +0800, Haojian Zhuang wrote:
> @@ -596,6 +614,15 @@ int __devinit max8925_device_init(struct
> max8925_chip *chip,
>  		dev_err(chip->dev, "Failed to add rtc subdev\n");
>  		goto out;
>  	}
> +
> +	ret = mfd_add_devices(chip->dev, 0, &onkey_devs[0],
> +			      ARRAY_SIZE(onkey_devs),
> +			      &onkey_resources[0], 0);
> +	if (ret < 0) {
> +		dev_err(chip->dev, "Failed to add onkey subdev\n");
> +		goto out;
I think you want goto out_dev here.
I fixed it up for you and applied this patch to my for-next tree.

Cheers,
Samuel.


> +	}
> +
>  	if (pdata && pdata->regulator[0]) {
>  		ret = mfd_add_devices(chip->dev, 0, &regulator_devs[0],
>  				      ARRAY_SIZE(regulator_devs),
> -- 
> 1.5.6.5

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From sameo at linux.intel.com  Fri Jun 18 14:04:56 2010
From: sameo at linux.intel.com (Samuel Ortiz)
Date: Fri, 18 Jun 2010 20:04:56 +0200
Subject: [PATCH 04/05] mfd: fix led resource in 88pm860x
In-Reply-To: <AANLkTinsJdF2b78Bodc_HqNsjbt5st33DkIClEFevctX@mail.gmail.com>
References: <AANLkTinsJdF2b78Bodc_HqNsjbt5st33DkIClEFevctX@mail.gmail.com>
Message-ID: <20100618180455.GC3582@sortiz.org>

Hi Haojian,

On Wed, May 19, 2010 at 02:58:49PM +0800, Haojian Zhuang wrote:
> From 226ccebaf7d776467d44931132eafef9078d8e70 Mon Sep 17 00:00:00 2001
> From: Haojian Zhuang <haojian.zhuang at marvell.com>
> Date: Wed, 19 May 2010 13:06:59 +0800
> Subject: [PATCH] mfd: fix led resource in 88pm860x
> 
> Fix typo error in LED resource of 88pm860x.
Patch applied, thanks a lot.

Cheers,
Samuel.


> Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
> ---
>  drivers/mfd/88pm860x-core.c |   12 ++++++------
>  1 files changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/mfd/88pm860x-core.c b/drivers/mfd/88pm860x-core.c
> index 2c65a2c..1580f1f 100644
> --- a/drivers/mfd/88pm860x-core.c
> +++ b/drivers/mfd/88pm860x-core.c
> @@ -74,12 +74,12 @@ static struct mfd_cell backlight_devs[] = {
>  }
> 
>  static struct resource led_resources[] = {
> -	PM8606_LED_RESOURCE(PM8606_LED1_RED, RGB2B),
> -	PM8606_LED_RESOURCE(PM8606_LED1_GREEN, RGB2C),
> -	PM8606_LED_RESOURCE(PM8606_LED1_BLUE, RGB2D),
> -	PM8606_LED_RESOURCE(PM8606_LED2_RED, RGB1B),
> -	PM8606_LED_RESOURCE(PM8606_LED2_GREEN, RGB1C),
> -	PM8606_LED_RESOURCE(PM8606_LED2_BLUE, RGB1D),
> +	PM8606_LED_RESOURCE(PM8606_LED1_RED, RGB1B),
> +	PM8606_LED_RESOURCE(PM8606_LED1_GREEN, RGB1C),
> +	PM8606_LED_RESOURCE(PM8606_LED1_BLUE, RGB1D),
> +	PM8606_LED_RESOURCE(PM8606_LED2_RED, RGB2B),
> +	PM8606_LED_RESOURCE(PM8606_LED2_GREEN, RGB2C),
> +	PM8606_LED_RESOURCE(PM8606_LED2_BLUE, RGB2D),
>  };
> 
>  #define PM8606_LED_DEVS(_i)				\
> -- 
> 1.5.6.5

-- 
Intel Open Source Technology Centre
http://oss.intel.com/


From cbouatmailru at gmail.com  Fri Jun 18 14:14:51 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Fri, 18 Jun 2010 22:14:51 +0400
Subject: [PATCH 1/2] ARM: Factor out secondary CPU bootup code from
	RealView platforms
Message-ID: <20100618181451.GA17455@oksana.dev.rtsoft.ru>

For CNS3xxx we want to reuse the original ARM approach of booting
secondary CPUs. This patch turns RealView's code into "SCU library",
so that now platform code can call the generic routines.

Note that there are also mach-{omap2,ux500,vexpress} that might
benefit from this change.

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/include/asm/smp_scu.h   |    8 ++
 arch/arm/kernel/Makefile         |    2 +-
 arch/arm/kernel/smp_scu.c        |  164 +++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/smp_scu_head.S   |   37 +++++++++
 arch/arm/mach-realview/Makefile  |    2 +-
 arch/arm/mach-realview/headsmp.S |   39 ---------
 arch/arm/mach-realview/platsmp.c |  165 ++------------------------------------
 7 files changed, 217 insertions(+), 200 deletions(-)
 create mode 100644 arch/arm/kernel/smp_scu_head.S
 delete mode 100644 arch/arm/mach-realview/headsmp.S

diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 2376835..45a281a 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -4,4 +4,12 @@
 unsigned int scu_get_core_count(void __iomem *);
 void scu_enable(void __iomem *);
 
+extern volatile int __cpuinitdata scu_pen_release;
+void scu_secondary_startup(void);
+void __cpuinit scu_secondary_init(unsigned int cpu);
+int __cpuinit scu_boot_secondary(unsigned int cpu, struct task_struct *idle);
+void __init scu_init_cpus(void __iomem *scu_base);
+void __init scu_prepare_cpus(void __iomem *scu_base, void __iomem *maddr,
+			     unsigned int max_cpus);
+
 #endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 26d302c..2fc7cb1 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -28,7 +28,7 @@ obj-$(CONFIG_ARTHUR)		+= arthur.o
 obj-$(CONFIG_ISA_DMA)		+= dma-isa.o
 obj-$(CONFIG_PCI)		+= bios32.o isa.o
 obj-$(CONFIG_SMP)		+= smp.o
-obj-$(CONFIG_HAVE_ARM_SCU)	+= smp_scu.o
+obj-$(CONFIG_HAVE_ARM_SCU)	+= smp_scu.o smp_scu_head.o
 obj-$(CONFIG_HAVE_ARM_TWD)	+= smp_twd.o
 obj-$(CONFIG_DYNAMIC_FTRACE)	+= ftrace.o
 obj-$(CONFIG_KEXEC)		+= machine_kexec.o relocate_kernel.o
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 9ab4149..810d91c 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -8,10 +8,16 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/compiler.h>
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/delay.h>
 
 #include <asm/smp_scu.h>
+#include <asm/unified.h>
+#include <asm/localtimer.h>
 #include <asm/cacheflush.h>
 
 #define SCU_CTRL		0x00
@@ -50,3 +56,161 @@ void __init scu_enable(void __iomem *scu_base)
 	 */
 	flush_cache_all();
 }
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata scu_pen_release = -1;
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit scu_secondary_init(unsigned int cpu)
+{
+	/*
+	 * let the primary processor know we're out of the
+	 * pen, then head off into the C entry point
+	 */
+	scu_pen_release = -1;
+	smp_wmb();
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+int __cpuinit scu_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+
+	/*
+	 * set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+	/*
+	 * The secondary processor is waiting to be released from
+	 * the holding pen - release it, then wait for it to flag
+	 * that it has been released by resetting scu_pen_release.
+	 *
+	 * Note that "scu_pen_release" is the hardware CPU ID, whereas
+	 * "cpu" is Linux's internal ID.
+	 */
+	scu_pen_release = cpu;
+	flush_cache_all();
+
+	/*
+	 * XXX
+	 *
+	 * This is a later addition to the booting protocol: the
+	 * bootMonitor now puts secondary cores into WFI, so
+	 * poke_milo() no longer gets the cores moving; we need
+	 * to send a soft interrupt to wake the secondary core.
+	 * Use smp_cross_call() for this, since there's little
+	 * point duplicating the code here
+	 */
+	smp_cross_call(cpumask_of(cpu));
+
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		smp_rmb();
+		if (scu_pen_release == -1)
+			break;
+
+		udelay(10);
+	}
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return scu_pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init scu_init_cpus(void __iomem *scu_base)
+{
+	unsigned int ncores = scu_get_core_count(scu_base);
+	unsigned int i;
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+}
+
+static void __init poke_milo(void __iomem *maddr)
+{
+	/* nobody is to be released from the pen yet */
+	scu_pen_release = -1;
+
+	/*
+	 * Write the address of secondary startup into the system-wide flags
+	 * register. The BootMonitor waits for this register to become
+	 * non-zero.
+	 */
+	__raw_writel(BSYM(virt_to_phys(scu_secondary_startup)), maddr);
+
+	mb();
+}
+
+void __init scu_prepare_cpus(void __iomem *scu_base, void __iomem *maddr,
+			     unsigned int max_cpus)
+{
+	unsigned int ncores = scu_get_core_count(scu_base);
+	unsigned int cpu = smp_processor_id();
+	int i;
+
+	/* sanity check */
+	if (ncores == 0) {
+		pr_err("%s: strange CM count of 0? Default to 1\n", __func__);
+
+		ncores = 1;
+	}
+
+	if (ncores > NR_CPUS) {
+		pr_warn("%s: no. of cores (%d) greater than configured "
+		       "maximum of %d - clipping\n", __func__,
+		       ncores, NR_CPUS);
+		ncores = NR_CPUS;
+	}
+
+	smp_store_cpu_info(cpu);
+
+	/*
+	 * are we trying to boot more cores than exist?
+	 */
+	if (max_cpus > ncores)
+		max_cpus = ncores;
+
+	/*
+	 * Initialise the present map, which describes the set of CPUs
+	 * actually populated at the present time.
+	 */
+	for (i = 0; i < max_cpus; i++)
+		set_cpu_present(i, true);
+
+	/*
+	 * Initialise the SCU if there are more than one CPU and let
+	 * them know where to start. Note that, on modern versions of
+	 * MILO, the "poke" doesn't actually do anything until each
+	 * individual core is sent a soft interrupt to get it out of
+	 * WFI
+	 */
+	if (max_cpus > 1) {
+		/*
+		 * Enable the local timer or broadcast device for the
+		 * boot CPU, but only if we have more than one CPU.
+		 */
+		percpu_timer_setup();
+
+		scu_enable(scu_base);
+		poke_milo(maddr);
+	}
+}
diff --git a/arch/arm/kernel/smp_scu_head.S b/arch/arm/kernel/smp_scu_head.S
new file mode 100644
index 0000000..200010b
--- /dev/null
+++ b/arch/arm/kernel/smp_scu_head.S
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+	__INIT
+
+/*
+ * SCU specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(scu_secondary_startup)
+	mrc	p15, 0, r0, c0, c0, 5
+	and	r0, r0, #15
+	adr	r4, 1f
+	ldmia	r4, {r5, r6}
+	sub	r4, r4, r5
+	add	r6, r6, r4
+pen:	ldr	r7, [r6]
+	cmp	r7, r0
+	bne	pen
+
+	/*
+	 * we've been released from the holding pen: secondary_stack
+	 * should now contain the SVC stack for this core
+	 */
+	b	secondary_startup
+
+1:	.long	.
+	.long	scu_pen_release
diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index a01b76b..d456163 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -8,6 +8,6 @@ obj-$(CONFIG_MACH_REALVIEW_PB11MP)	+= realview_pb11mp.o
 obj-$(CONFIG_MACH_REALVIEW_PB1176)	+= realview_pb1176.o
 obj-$(CONFIG_MACH_REALVIEW_PBA8)	+= realview_pba8.o
 obj-$(CONFIG_MACH_REALVIEW_PBX)		+= realview_pbx.o
-obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
+obj-$(CONFIG_SMP)			+= platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS)		+= localtimer.o
diff --git a/arch/arm/mach-realview/headsmp.S b/arch/arm/mach-realview/headsmp.S
deleted file mode 100644
index 4075473..0000000
--- a/arch/arm/mach-realview/headsmp.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/arch/arm/mach-realview/headsmp.S
- *
- *  Copyright (c) 2003 ARM Limited
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-	__INIT
-
-/*
- * Realview specific entry point for secondary CPUs.  This provides
- * a "holding pen" into which all secondary cores are held until we're
- * ready for them to initialise.
- */
-ENTRY(realview_secondary_startup)
-	mrc	p15, 0, r0, c0, c0, 5
-	and	r0, r0, #15
-	adr	r4, 1f
-	ldmia	r4, {r5, r6}
-	sub	r4, r4, r5
-	add	r6, r6, r4
-pen:	ldr	r7, [r6]
-	cmp	r7, r0
-	bne	pen
-
-	/*
-	 * we've been released from the holding pen: secondary_stack
-	 * should now contain the SVC stack for this core
-	 */
-	b	secondary_startup
-
-1:	.long	.
-	.long	pen_release
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 0092658..a41e169 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -9,18 +9,11 @@
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 
-#include <asm/cacheflush.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/localtimer.h>
-#include <asm/unified.h>
 
 #include <mach/board-eb.h>
 #include <mach/board-pb11mp.h>
@@ -29,14 +22,6 @@
 
 #include "core.h"
 
-extern void realview_secondary_startup(void);
-
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int __cpuinitdata pen_release = -1;
-
 static void __iomem *scu_base_addr(void)
 {
 	if (machine_is_realview_eb_mp())
@@ -50,16 +35,6 @@ static void __iomem *scu_base_addr(void)
 		return (void __iomem *)0;
 }
 
-static inline unsigned int get_core_count(void)
-{
-	void __iomem *scu_base = scu_base_addr();
-	if (scu_base)
-		return scu_get_core_count(scu_base);
-	return 1;
-}
-
-static DEFINE_SPINLOCK(boot_lock);
-
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
 	trace_hardirqs_off();
@@ -71,151 +46,23 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 	 */
 	gic_cpu_init(0, gic_cpu_base_addr);
 
-	/*
-	 * let the primary processor know we're out of the
-	 * pen, then head off into the C entry point
-	 */
-	pen_release = -1;
-	smp_wmb();
-
-	/*
-	 * Synchronise with the boot thread.
-	 */
-	spin_lock(&boot_lock);
-	spin_unlock(&boot_lock);
+	scu_secondary_init(cpu);
 }
 
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-	unsigned long timeout;
-
-	/*
-	 * set synchronisation state between this boot processor
-	 * and the secondary one
-	 */
-	spin_lock(&boot_lock);
-
-	/*
-	 * The secondary processor is waiting to be released from
-	 * the holding pen - release it, then wait for it to flag
-	 * that it has been released by resetting pen_release.
-	 *
-	 * Note that "pen_release" is the hardware CPU ID, whereas
-	 * "cpu" is Linux's internal ID.
-	 */
-	pen_release = cpu;
-	flush_cache_all();
-
-	/*
-	 * XXX
-	 *
-	 * This is a later addition to the booting protocol: the
-	 * bootMonitor now puts secondary cores into WFI, so
-	 * poke_milo() no longer gets the cores moving; we need
-	 * to send a soft interrupt to wake the secondary core.
-	 * Use smp_cross_call() for this, since there's little
-	 * point duplicating the code here
-	 */
-	smp_cross_call(cpumask_of(cpu));
-
-	timeout = jiffies + (1 * HZ);
-	while (time_before(jiffies, timeout)) {
-		smp_rmb();
-		if (pen_release == -1)
-			break;
-
-		udelay(10);
-	}
-
-	/*
-	 * now the secondary core is starting up let it run its
-	 * calibrations, then wait for it to finish
-	 */
-	spin_unlock(&boot_lock);
-
-	return pen_release != -1 ? -ENOSYS : 0;
+	return scu_boot_secondary(cpu, idle);
 }
 
-static void __init poke_milo(void)
-{
-	/* nobody is to be released from the pen yet */
-	pen_release = -1;
-
-	/*
-	 * Write the address of secondary startup into the system-wide flags
-	 * register. The BootMonitor waits for this register to become
-	 * non-zero.
-	 */
-	__raw_writel(BSYM(virt_to_phys(realview_secondary_startup)),
-		     __io_address(REALVIEW_SYS_FLAGSSET));
-
-	mb();
-}
-
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
 void __init smp_init_cpus(void)
 {
-	unsigned int i, ncores = get_core_count();
-
-	for (i = 0; i < ncores; i++)
-		set_cpu_possible(i, true);
+	scu_init_cpus(scu_base_addr());
 }
 
 void __init smp_prepare_cpus(unsigned int max_cpus)
 {
-	unsigned int ncores = get_core_count();
-	unsigned int cpu = smp_processor_id();
-	int i;
-
-	/* sanity check */
-	if (ncores == 0) {
-		printk(KERN_ERR
-		       "Realview: strange CM count of 0? Default to 1\n");
-
-		ncores = 1;
-	}
-
-	if (ncores > NR_CPUS) {
-		printk(KERN_WARNING
-		       "Realview: no. of cores (%d) greater than configured "
-		       "maximum of %d - clipping\n",
-		       ncores, NR_CPUS);
-		ncores = NR_CPUS;
-	}
-
-	smp_store_cpu_info(cpu);
-
-	/*
-	 * are we trying to boot more cores than exist?
-	 */
-	if (max_cpus > ncores)
-		max_cpus = ncores;
-
-	/*
-	 * Initialise the present map, which describes the set of CPUs
-	 * actually populated at the present time.
-	 */
-	for (i = 0; i < max_cpus; i++)
-		set_cpu_present(i, true);
-
-	/*
-	 * Initialise the SCU if there are more than one CPU and let
-	 * them know where to start. Note that, on modern versions of
-	 * MILO, the "poke" doesn't actually do anything until each
-	 * individual core is sent a soft interrupt to get it out of
-	 * WFI
-	 */
-	if (max_cpus > 1) {
-		/*
-		 * Enable the local timer or broadcast device for the
-		 * boot CPU, but only if we have more than one CPU.
-		 */
-		percpu_timer_setup();
+	void __iomem *scu_base = scu_base_addr();
+	void __iomem *maddr = __io_address(REALVIEW_SYS_FLAGSSET);
 
-		scu_enable(scu_base_addr());
-		poke_milo();
-	}
+	scu_prepare_cpus(scu_base, maddr, max_cpus);
 }
-- 
1.7.0.5



From cbouatmailru at gmail.com  Fri Jun 18 14:15:01 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Fri, 18 Jun 2010 22:15:01 +0400
Subject: [PATCH 2/2] ARM: cns3xxx: Add support for SMP
Message-ID: <20100618181501.GB17455@oksana.dev.rtsoft.ru>

Thanks to the previous refactorings, nothing fancy needs to be
done, just use generic SCU routines.

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/Kconfig                         |    2 +-
 arch/arm/mach-cns3xxx/Kconfig            |    1 +
 arch/arm/mach-cns3xxx/Makefile           |    1 +
 arch/arm/mach-cns3xxx/include/mach/smp.h |   31 +++++++++++++++++
 arch/arm/mach-cns3xxx/platsmp.c          |   54 ++++++++++++++++++++++++++++++
 5 files changed, 88 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-cns3xxx/include/mach/smp.h
 create mode 100644 arch/arm/mach-cns3xxx/platsmp.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fab2ddd..c6e12d7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1100,7 +1100,7 @@ config SMP
 	bool "Symmetric Multi-Processing (EXPERIMENTAL)"
 	depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
 		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
-		 ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
+		 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_CNS3XXX)
 	depends on GENERIC_CLOCKEVENTS
 	select USE_GENERIC_SMP_HELPERS
 	select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index 9ebfcc4..b510dab 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -3,6 +3,7 @@ menu "CNS3XXX platform type"
 
 config MACH_CNS3420VB
 	bool "Support for CNS3420 Validation Board"
+	select HAVE_ARM_SCU
 	help
 	  Include support for the Cavium Networks CNS3420 MPCore Platform
 	  Baseboard.
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 11033f1..ba4ee7b 100644
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o pm.o devices.o
+obj-$(CONFIG_SMP)			+= platsmp.o
 obj-$(CONFIG_PCI)			+= pcie.o
 obj-$(CONFIG_MACH_CNS3420VB)		+= cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/include/mach/smp.h b/arch/arm/mach-cns3xxx/include/mach/smp.h
new file mode 100644
index 0000000..afb2fef
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/smp.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2002 ARM Ltd.
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_SMP_H
+#define __MACH_SMP_H
+
+#include <asm/hardware/gic.h>
+
+#define hard_smp_processor_id()				\
+	({						\
+		unsigned int cpunum;			\
+		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
+			: "=r" (cpunum));		\
+		cpunum &= 0x0F;				\
+	})
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(const struct cpumask *mask)
+{
+	gic_raise_softirq(mask, 1);
+}
+
+#endif /* __MACH_SMP_H */
diff --git a/arch/arm/mach-cns3xxx/platsmp.c b/arch/arm/mach-cns3xxx/platsmp.c
new file mode 100644
index 0000000..0b629b8
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/platsmp.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2002 ARM Ltd
+ * Copyright 2008 Cavium Networks
+ * Copyright 2010 MontaVista Software, LLC.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <asm/smp_scu.h>
+#include <mach/cns3xxx.h>
+#include "core.h"
+
+static void __iomem *scu_base_addr(void)
+{
+	return (void __iomem *)CNS3XXX_TC11MP_SCU_BASE_VIRT;
+}
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+	trace_hardirqs_off();
+
+	/*
+	 * if any interrupts are already enabled for the primary
+	 * core (e.g. timer irq), then they will not have been enabled
+	 * for us: do so
+	 */
+	gic_cpu_init(0, gic_cpu_base_addr);
+
+	scu_secondary_init(cpu);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	return scu_boot_secondary(cpu, idle);
+}
+
+void __init smp_init_cpus(void)
+{
+	scu_init_cpus(scu_base_addr());
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+	void __iomem *scu_base = scu_base_addr();
+	void __iomem *maddr = (void __iomem *)(0xFFF07000 + 0x0600);
+
+	scu_prepare_cpus(scu_base, maddr, max_cpus);
+}
-- 
1.7.0.5


From linux at arm.linux.org.uk  Fri Jun 18 14:17:07 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 18 Jun 2010 19:17:07 +0100
Subject: [PATCH 1/2] ARM: Factor out secondary CPU bootup code from
	RealView platforms
In-Reply-To: <20100618181451.GA17455@oksana.dev.rtsoft.ru>
References: <20100618181451.GA17455@oksana.dev.rtsoft.ru>
Message-ID: <20100618181707.GA21578@n2100.arm.linux.org.uk>

On Fri, Jun 18, 2010 at 10:14:51PM +0400, Anton Vorontsov wrote:
> For CNS3xxx we want to reuse the original ARM approach of booting
> secondary CPUs. This patch turns RealView's code into "SCU library",
> so that now platform code can call the generic routines.

Please use vexpress as the basis for taking code from, not realview.


From augulis.darius at gmail.com  Fri Jun 18 14:30:46 2010
From: augulis.darius at gmail.com (Darius Augulis)
Date: Fri, 18 Jun 2010 21:30:46 +0300
Subject: [PATCH 11/15] ARM: S3C2416: Add support for second HSMMC channel
In-Reply-To: <20100617191901.GA5864@jeknote.loshitsa1.net>
References: <1273631766-15693-1-git-send-email-ben-linux@fluff.org>
	<1273631766-15693-11-git-send-email-ben-linux@fluff.org>
	<4C1A71F6.5030203@gmail.com>
	<20100617191901.GA5864@jeknote.loshitsa1.net>
Message-ID: <4C1BBB56.4090205@gmail.com>

On 06/17/2010 10:19 PM, Yauhen Kharuzhy wrote:
> On Thu, Jun 17, 2010 at 10:05:26PM +0300, Darius Augulis wrote:
>> On 05/12/2010 05:36 AM, Ben Dooks wrote:
>>> Add support for the second HSMMC channel on the S3C2416.
>>
>> There is issue with mach-s3c2416 and sdhci-s3c driver.
>> Driver probe crashes with following backtrace:
>>
>> sdhci: Secure Digital Host Controller Interface driver
>> sdhci: Copyright(c) Pierre Ossman
>> Unable to handle kernel NULL pointer dereference at virtual address 00000000
>> pgd = c0004000
>> [00000000] *pgd=00000000
>> Internal error: Oops: 5 [#1]
>> last sysfs file:
>> CPU: 0    Not tainted  (2.6.35-rc3-00001-g7dfb002 #31)
>> PC is at sdhci_s3c_probe+0x188/0x42c
>> LR is at clk_enable+0x50/0x60
>>
>> The reason is not completely initialised s3c_sdhci_platdata
>> structure. When getting clocks in sdhci_s3c_probe():
>>
>> for (clks = 0, ptr = 0; ptr<  MAX_BUS_CLK; ptr++) {
>>                  struct clk *clk;
>>                  char *name = pdata->clocks[ptr];
>>
>> Pointer clocks is not initialised at all, because mach-s3c2416
>> doesn't have such helpers like mach-s3c64xx does:
>>
>> s3c6400_default_sdhci0()
>> s3c6400_default_sdhci1()
>> s3c6400_default_sdhci2()
>>
>> Also other necessary s3c_sdhci_platdata members cfg_gpio and
>> cfg_card are missing on s3c2416.
>>
>> Is there any patch adding this missing info to mach-s3c2416?
>
> I am already wrote such patch today and will post it after testing
> tomorrow, I hope.

Hi Yauhen,

could you please send me this patch? I will test it too by my side.
thanks.


>



From cbouatmailru at gmail.com  Fri Jun 18 16:36:30 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Sat, 19 Jun 2010 00:36:30 +0400
Subject: [PATCH v2 1/3] ARM: Factor out secondary CPU bootup code from
	VExpress platforms
In-Reply-To: <20100618181707.GA21578@n2100.arm.linux.org.uk>
References: <20100618181707.GA21578@n2100.arm.linux.org.uk>
Message-ID: <20100618203630.GA9155@oksana.dev.rtsoft.ru>

For CNS3xxx we want to reuse the original ARM approach of booting
secondary CPUs. This patch turns VExpress' code into "SCU library",
so that now platform code can call the generic routines.

Note that there are also mach-{omap2,ux500,realview} that might
benefit from this change.

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/include/asm/smp_scu.h   |    7 ++
 arch/arm/kernel/Makefile         |    2 +-
 arch/arm/kernel/smp_scu.c        |  136 ++++++++++++++++++++++++++++++++++
 arch/arm/kernel/smp_scu_head.S   |   37 +++++++++
 arch/arm/mach-vexpress/Makefile  |    2 +-
 arch/arm/mach-vexpress/headsmp.S |   39 ----------
 arch/arm/mach-vexpress/platsmp.c |  150 ++++----------------------------------
 7 files changed, 196 insertions(+), 177 deletions(-)
 create mode 100644 arch/arm/kernel/smp_scu_head.S
 delete mode 100644 arch/arm/mach-vexpress/headsmp.S

diff --git a/arch/arm/include/asm/smp_scu.h b/arch/arm/include/asm/smp_scu.h
index 2376835..2474590 100644
--- a/arch/arm/include/asm/smp_scu.h
+++ b/arch/arm/include/asm/smp_scu.h
@@ -4,4 +4,11 @@
 unsigned int scu_get_core_count(void __iomem *);
 void scu_enable(void __iomem *);
 
+extern volatile int __cpuinitdata scu_pen_release;
+void scu_secondary_startup(void);
+void __cpuinit scu_secondary_init(unsigned int cpu);
+int __cpuinit scu_boot_secondary(unsigned int cpu, struct task_struct *idle);
+void __init scu_init_cpus(void __iomem *scu_base);
+void __init scu_prepare_cpus(void __iomem *scu_base, unsigned int max_cpus);
+
 #endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 26d302c..2fc7cb1 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -28,7 +28,7 @@ obj-$(CONFIG_ARTHUR)		+= arthur.o
 obj-$(CONFIG_ISA_DMA)		+= dma-isa.o
 obj-$(CONFIG_PCI)		+= bios32.o isa.o
 obj-$(CONFIG_SMP)		+= smp.o
-obj-$(CONFIG_HAVE_ARM_SCU)	+= smp_scu.o
+obj-$(CONFIG_HAVE_ARM_SCU)	+= smp_scu.o smp_scu_head.o
 obj-$(CONFIG_HAVE_ARM_TWD)	+= smp_twd.o
 obj-$(CONFIG_DYNAMIC_FTRACE)	+= ftrace.o
 obj-$(CONFIG_KEXEC)		+= machine_kexec.o relocate_kernel.o
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c
index 9ab4149..b18414c 100644
--- a/arch/arm/kernel/smp_scu.c
+++ b/arch/arm/kernel/smp_scu.c
@@ -8,10 +8,15 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
+#include <linux/compiler.h>
+#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/io.h>
+#include <linux/jiffies.h>
+#include <linux/delay.h>
 
 #include <asm/smp_scu.h>
+#include <asm/localtimer.h>
 #include <asm/cacheflush.h>
 
 #define SCU_CTRL		0x00
@@ -50,3 +55,134 @@ void __init scu_enable(void __iomem *scu_base)
 	 */
 	flush_cache_all();
 }
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata scu_pen_release = -1;
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit scu_secondary_init(unsigned int cpu)
+{
+	/*
+	 * let the primary processor know we're out of the
+	 * pen, then head off into the C entry point
+	 */
+	scu_pen_release = -1;
+	smp_wmb();
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+int __cpuinit scu_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+
+	/*
+	 * Set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+	/*
+	 * This is really belt and braces; we hold unintended secondary
+	 * CPUs in the holding pen until we're ready for them.  However,
+	 * since we haven't sent them a soft interrupt, they shouldn't
+	 * be there.
+	 */
+	scu_pen_release = cpu;
+	__cpuc_flush_dcache_area((void *)&scu_pen_release,
+				 sizeof(scu_pen_release));
+	outer_clean_range(__pa(&scu_pen_release), __pa(&scu_pen_release + 1));
+
+	/*
+	 * Send the secondary CPU a soft interrupt, thereby causing
+	 * the boot monitor to read the system wide flags register,
+	 * and branch to the address found there.
+	 */
+	smp_cross_call(cpumask_of(cpu));
+
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		smp_rmb();
+		if (scu_pen_release == -1)
+			break;
+
+		udelay(10);
+	}
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return scu_pen_release != -1 ? -ENOSYS : 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init scu_init_cpus(void __iomem *scu_base)
+{
+	unsigned int ncores = scu_base ? scu_get_core_count(scu_base) : 1;
+	unsigned int i;
+
+	/* sanity check */
+	if (ncores == 0) {
+		pr_err("%s: strange CM count of 0? Default to 1\n", __func__);
+		ncores = 1;
+	}
+
+	if (ncores > NR_CPUS) {
+		pr_warn("%s: no. of cores (%d) greater than configured "
+		       "maximum of %d - clipping\n", __func__, ncores, NR_CPUS);
+		ncores = NR_CPUS;
+	}
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+}
+
+void __init scu_prepare_cpus(void __iomem *scu_base, unsigned int max_cpus)
+{
+	unsigned int ncores = num_possible_cpus();
+	unsigned int cpu = smp_processor_id();
+	int i;
+
+	smp_store_cpu_info(cpu);
+
+	/*
+	 * are we trying to boot more cores than exist?
+	 */
+	if (max_cpus > ncores)
+		max_cpus = ncores;
+
+	/*
+	 * Initialise the present map, which describes the set of CPUs
+	 * actually populated at the present time.
+	 */
+	for (i = 0; i < max_cpus; i++)
+		set_cpu_present(i, true);
+
+	/*
+	 * Initialise the SCU if there are more than one CPU and let
+	 * them know where to start.
+	 */
+	if (max_cpus > 1) {
+		/*
+		 * Enable the local timer or broadcast device for the
+		 * boot CPU, but only if we have more than one CPU.
+		 */
+		percpu_timer_setup();
+
+		scu_enable(scu_base);
+	}
+}
diff --git a/arch/arm/kernel/smp_scu_head.S b/arch/arm/kernel/smp_scu_head.S
new file mode 100644
index 0000000..200010b
--- /dev/null
+++ b/arch/arm/kernel/smp_scu_head.S
@@ -0,0 +1,37 @@
+/*
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+	__INIT
+
+/*
+ * SCU specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(scu_secondary_startup)
+	mrc	p15, 0, r0, c0, c0, 5
+	and	r0, r0, #15
+	adr	r4, 1f
+	ldmia	r4, {r5, r6}
+	sub	r4, r4, r5
+	add	r6, r6, r4
+pen:	ldr	r7, [r6]
+	cmp	r7, r0
+	bne	pen
+
+	/*
+	 * we've been released from the holding pen: secondary_stack
+	 * should now contain the SVC stack for this core
+	 */
+	b	secondary_startup
+
+1:	.long	.
+	.long	scu_pen_release
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 1b71b77..6533d11 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -4,5 +4,5 @@
 
 obj-y					:= v2m.o
 obj-$(CONFIG_ARCH_VEXPRESS_CA9X4)	+= ct-ca9x4.o
-obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
+obj-$(CONFIG_SMP)			+= platsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)		+= localtimer.o
diff --git a/arch/arm/mach-vexpress/headsmp.S b/arch/arm/mach-vexpress/headsmp.S
deleted file mode 100644
index 8a78ff6..0000000
--- a/arch/arm/mach-vexpress/headsmp.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/arch/arm/mach-vexpress/headsmp.S
- *
- *  Copyright (c) 2003 ARM Limited
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-	__INIT
-
-/*
- * Versatile Express specific entry point for secondary CPUs.  This
- * provides a "holding pen" into which all secondary cores are held
- * until we're ready for them to initialise.
- */
-ENTRY(vexpress_secondary_startup)
-	mrc	p15, 0, r0, c0, c0, 5
-	and	r0, r0, #15
-	adr	r4, 1f
-	ldmia	r4, {r5, r6}
-	sub	r4, r4, r5
-	add	r6, r6, r4
-pen:	ldr	r7, [r6]
-	cmp	r7, r0
-	bne	pen
-
-	/*
-	 * we've been released from the holding pen: secondary_stack
-	 * should now contain the SVC stack for this core
-	 */
-	b	secondary_startup
-
-1:	.long	.
-	.long	pen_release
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 6709706..2d4146f 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -9,15 +9,9 @@
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 
-#include <asm/cacheflush.h>
-#include <asm/localtimer.h>
 #include <asm/smp_scu.h>
 #include <asm/unified.h>
 
@@ -27,21 +21,11 @@
 
 #include "core.h"
 
-extern void vexpress_secondary_startup(void);
-
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int __cpuinitdata pen_release = -1;
-
 static void __iomem *scu_base_addr(void)
 {
 	return MMIO_P2V(A9_MPCORE_SCU);
 }
 
-static DEFINE_SPINLOCK(boot_lock);
-
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
 	trace_hardirqs_off();
@@ -53,138 +37,32 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 	 */
 	gic_cpu_init(0, gic_cpu_base_addr);
 
-	/*
-	 * let the primary processor know we're out of the
-	 * pen, then head off into the C entry point
-	 */
-	pen_release = -1;
-	smp_wmb();
-
-	/*
-	 * Synchronise with the boot thread.
-	 */
-	spin_lock(&boot_lock);
-	spin_unlock(&boot_lock);
+	scu_secondary_init(cpu);
 }
 
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-	unsigned long timeout;
-
-	/*
-	 * Set synchronisation state between this boot processor
-	 * and the secondary one
-	 */
-	spin_lock(&boot_lock);
-
-	/*
-	 * This is really belt and braces; we hold unintended secondary
-	 * CPUs in the holding pen until we're ready for them.  However,
-	 * since we haven't sent them a soft interrupt, they shouldn't
-	 * be there.
-	 */
-	pen_release = cpu;
-	__cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
-	outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
-
-	/*
-	 * Send the secondary CPU a soft interrupt, thereby causing
-	 * the boot monitor to read the system wide flags register,
-	 * and branch to the address found there.
-	 */
-	smp_cross_call(cpumask_of(cpu));
-
-	timeout = jiffies + (1 * HZ);
-	while (time_before(jiffies, timeout)) {
-		smp_rmb();
-		if (pen_release == -1)
-			break;
-
-		udelay(10);
-	}
-
-	/*
-	 * now the secondary core is starting up let it run its
-	 * calibrations, then wait for it to finish
-	 */
-	spin_unlock(&boot_lock);
-
-	return pen_release != -1 ? -ENOSYS : 0;
+	return scu_boot_secondary(cpu, idle);
 }
 
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
 void __init smp_init_cpus(void)
 {
-	void __iomem *scu_base = scu_base_addr();
-	unsigned int i, ncores;
-
-	ncores = scu_base ? scu_get_core_count(scu_base) : 1;
-
-	/* sanity check */
-	if (ncores == 0) {
-		printk(KERN_ERR
-		       "vexpress: strange CM count of 0? Default to 1\n");
-
-		ncores = 1;
-	}
+	scu_init_cpus(scu_base_addr());
+}
 
-	if (ncores > NR_CPUS) {
-		printk(KERN_WARNING
-		       "vexpress: no. of cores (%d) greater than configured "
-		       "maximum of %d - clipping\n",
-		       ncores, NR_CPUS);
-		ncores = NR_CPUS;
-	}
+/* If there are more than one CPU let them know where to start. */
+static void __init smp_point_cpus(void)
+{
+	if (num_present_cpus() <= 1)
+		return;
 
-	for (i = 0; i < ncores; i++)
-		set_cpu_possible(i, true);
+	writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
+	writel(BSYM(virt_to_phys(scu_secondary_startup)),
+	       MMIO_P2V(V2M_SYS_FLAGSSET));
 }
 
 void __init smp_prepare_cpus(unsigned int max_cpus)
 {
-	unsigned int ncores = num_possible_cpus();
-	unsigned int cpu = smp_processor_id();
-	int i;
-
-	smp_store_cpu_info(cpu);
-
-	/*
-	 * are we trying to boot more cores than exist?
-	 */
-	if (max_cpus > ncores)
-		max_cpus = ncores;
-
-	/*
-	 * Initialise the present map, which describes the set of CPUs
-	 * actually populated at the present time.
-	 */
-	for (i = 0; i < max_cpus; i++)
-		set_cpu_present(i, true);
-
-	/*
-	 * Initialise the SCU if there are more than one CPU and let
-	 * them know where to start.
-	 */
-	if (max_cpus > 1) {
-		/*
-		 * Enable the local timer or broadcast device for the
-		 * boot CPU, but only if we have more than one CPU.
-		 */
-		percpu_timer_setup();
-
-		scu_enable(scu_base_addr());
-
-		/*
-		 * Write the address of secondary startup into the
-		 * system-wide flags register. The boot monitor waits
-		 * until it receives a soft interrupt, and then the
-		 * secondary CPU branches to this address.
-		 */
-		writel(~0, MMIO_P2V(V2M_SYS_FLAGSCLR));
-		writel(BSYM(virt_to_phys(vexpress_secondary_startup)),
-			MMIO_P2V(V2M_SYS_FLAGSSET));
-	}
+	scu_prepare_cpus(scu_base_addr(), max_cpus);
+	smp_point_cpus();
 }
-- 
1.7.0.5



From cbouatmailru at gmail.com  Fri Jun 18 16:36:48 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Sat, 19 Jun 2010 00:36:48 +0400
Subject: [PATCH v2 2/3] ARM: RealView: Switch to generic SCU routines
In-Reply-To: <20100618181707.GA21578@n2100.arm.linux.org.uk>
References: <20100618181707.GA21578@n2100.arm.linux.org.uk>
Message-ID: <20100618203648.GB9155@oksana.dev.rtsoft.ru>

This shrinks platform-specific code quite a bit.

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/mach-realview/Makefile  |    2 +-
 arch/arm/mach-realview/headsmp.S |   39 ---------
 arch/arm/mach-realview/platsmp.c |  161 +++-----------------------------------
 3 files changed, 12 insertions(+), 190 deletions(-)
 delete mode 100644 arch/arm/mach-realview/headsmp.S

diff --git a/arch/arm/mach-realview/Makefile b/arch/arm/mach-realview/Makefile
index a01b76b..d456163 100644
--- a/arch/arm/mach-realview/Makefile
+++ b/arch/arm/mach-realview/Makefile
@@ -8,6 +8,6 @@ obj-$(CONFIG_MACH_REALVIEW_PB11MP)	+= realview_pb11mp.o
 obj-$(CONFIG_MACH_REALVIEW_PB1176)	+= realview_pb1176.o
 obj-$(CONFIG_MACH_REALVIEW_PBA8)	+= realview_pba8.o
 obj-$(CONFIG_MACH_REALVIEW_PBX)		+= realview_pbx.o
-obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
+obj-$(CONFIG_SMP)			+= platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o
 obj-$(CONFIG_LOCAL_TIMERS)		+= localtimer.o
diff --git a/arch/arm/mach-realview/headsmp.S b/arch/arm/mach-realview/headsmp.S
deleted file mode 100644
index 4075473..0000000
--- a/arch/arm/mach-realview/headsmp.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  linux/arch/arm/mach-realview/headsmp.S
- *
- *  Copyright (c) 2003 ARM Limited
- *  All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <linux/init.h>
-
-	__INIT
-
-/*
- * Realview specific entry point for secondary CPUs.  This provides
- * a "holding pen" into which all secondary cores are held until we're
- * ready for them to initialise.
- */
-ENTRY(realview_secondary_startup)
-	mrc	p15, 0, r0, c0, c0, 5
-	and	r0, r0, #15
-	adr	r4, 1f
-	ldmia	r4, {r5, r6}
-	sub	r4, r4, r5
-	add	r6, r6, r4
-pen:	ldr	r7, [r6]
-	cmp	r7, r0
-	bne	pen
-
-	/*
-	 * we've been released from the holding pen: secondary_stack
-	 * should now contain the SVC stack for this core
-	 */
-	b	secondary_startup
-
-1:	.long	.
-	.long	pen_release
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 0092658..3c1000b 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -9,17 +9,11 @@
  * published by the Free Software Foundation.
  */
 #include <linux/init.h>
-#include <linux/errno.h>
-#include <linux/delay.h>
-#include <linux/device.h>
-#include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
 
-#include <asm/cacheflush.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
-#include <asm/localtimer.h>
 #include <asm/unified.h>
 
 #include <mach/board-eb.h>
@@ -29,14 +23,6 @@
 
 #include "core.h"
 
-extern void realview_secondary_startup(void);
-
-/*
- * control for which core is the next to come out of the secondary
- * boot "holding pen"
- */
-volatile int __cpuinitdata pen_release = -1;
-
 static void __iomem *scu_base_addr(void)
 {
 	if (machine_is_realview_eb_mp())
@@ -50,16 +36,6 @@ static void __iomem *scu_base_addr(void)
 		return (void __iomem *)0;
 }
 
-static inline unsigned int get_core_count(void)
-{
-	void __iomem *scu_base = scu_base_addr();
-	if (scu_base)
-		return scu_get_core_count(scu_base);
-	return 1;
-}
-
-static DEFINE_SPINLOCK(boot_lock);
-
 void __cpuinit platform_secondary_init(unsigned int cpu)
 {
 	trace_hardirqs_off();
@@ -71,151 +47,36 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
 	 */
 	gic_cpu_init(0, gic_cpu_base_addr);
 
-	/*
-	 * let the primary processor know we're out of the
-	 * pen, then head off into the C entry point
-	 */
-	pen_release = -1;
-	smp_wmb();
-
-	/*
-	 * Synchronise with the boot thread.
-	 */
-	spin_lock(&boot_lock);
-	spin_unlock(&boot_lock);
+	scu_secondary_init(cpu);
 }
 
 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-	unsigned long timeout;
-
-	/*
-	 * set synchronisation state between this boot processor
-	 * and the secondary one
-	 */
-	spin_lock(&boot_lock);
-
-	/*
-	 * The secondary processor is waiting to be released from
-	 * the holding pen - release it, then wait for it to flag
-	 * that it has been released by resetting pen_release.
-	 *
-	 * Note that "pen_release" is the hardware CPU ID, whereas
-	 * "cpu" is Linux's internal ID.
-	 */
-	pen_release = cpu;
-	flush_cache_all();
-
-	/*
-	 * XXX
-	 *
-	 * This is a later addition to the booting protocol: the
-	 * bootMonitor now puts secondary cores into WFI, so
-	 * poke_milo() no longer gets the cores moving; we need
-	 * to send a soft interrupt to wake the secondary core.
-	 * Use smp_cross_call() for this, since there's little
-	 * point duplicating the code here
-	 */
-	smp_cross_call(cpumask_of(cpu));
-
-	timeout = jiffies + (1 * HZ);
-	while (time_before(jiffies, timeout)) {
-		smp_rmb();
-		if (pen_release == -1)
-			break;
-
-		udelay(10);
-	}
-
-	/*
-	 * now the secondary core is starting up let it run its
-	 * calibrations, then wait for it to finish
-	 */
-	spin_unlock(&boot_lock);
+	return scu_boot_secondary(cpu, idle);
+}
 
-	return pen_release != -1 ? -ENOSYS : 0;
+void __init smp_init_cpus(void)
+{
+	scu_init_cpus(scu_base_addr());
 }
 
 static void __init poke_milo(void)
 {
-	/* nobody is to be released from the pen yet */
-	pen_release = -1;
-
+	if (num_present_cpus() <= 1)
+		return;
 	/*
 	 * Write the address of secondary startup into the system-wide flags
 	 * register. The BootMonitor waits for this register to become
 	 * non-zero.
 	 */
-	__raw_writel(BSYM(virt_to_phys(realview_secondary_startup)),
+	__raw_writel(BSYM(virt_to_phys(scu_secondary_startup)),
 		     __io_address(REALVIEW_SYS_FLAGSSET));
 
 	mb();
 }
 
-/*
- * Initialise the CPU possible map early - this describes the CPUs
- * which may be present or become present in the system.
- */
-void __init smp_init_cpus(void)
-{
-	unsigned int i, ncores = get_core_count();
-
-	for (i = 0; i < ncores; i++)
-		set_cpu_possible(i, true);
-}
-
 void __init smp_prepare_cpus(unsigned int max_cpus)
 {
-	unsigned int ncores = get_core_count();
-	unsigned int cpu = smp_processor_id();
-	int i;
-
-	/* sanity check */
-	if (ncores == 0) {
-		printk(KERN_ERR
-		       "Realview: strange CM count of 0? Default to 1\n");
-
-		ncores = 1;
-	}
-
-	if (ncores > NR_CPUS) {
-		printk(KERN_WARNING
-		       "Realview: no. of cores (%d) greater than configured "
-		       "maximum of %d - clipping\n",
-		       ncores, NR_CPUS);
-		ncores = NR_CPUS;
-	}
-
-	smp_store_cpu_info(cpu);
-
-	/*
-	 * are we trying to boot more cores than exist?
-	 */
-	if (max_cpus > ncores)
-		max_cpus = ncores;
-
-	/*
-	 * Initialise the present map, which describes the set of CPUs
-	 * actually populated at the present time.
-	 */
-	for (i = 0; i < max_cpus; i++)
-		set_cpu_present(i, true);
-
-	/*
-	 * Initialise the SCU if there are more than one CPU and let
-	 * them know where to start. Note that, on modern versions of
-	 * MILO, the "poke" doesn't actually do anything until each
-	 * individual core is sent a soft interrupt to get it out of
-	 * WFI
-	 */
-	if (max_cpus > 1) {
-		/*
-		 * Enable the local timer or broadcast device for the
-		 * boot CPU, but only if we have more than one CPU.
-		 */
-		percpu_timer_setup();
-
-		scu_enable(scu_base_addr());
-		poke_milo();
-	}
+	scu_prepare_cpus(scu_base_addr(), max_cpus);
+	poke_milo();
 }
-- 
1.7.0.5



From cbouatmailru at gmail.com  Fri Jun 18 16:37:02 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Sat, 19 Jun 2010 00:37:02 +0400
Subject: [PATCH v2 3/3] ARM: cns3xxx: Add support for SMP
In-Reply-To: <20100618181707.GA21578@n2100.arm.linux.org.uk>
References: <20100618181707.GA21578@n2100.arm.linux.org.uk>
Message-ID: <20100618203702.GC9155@oksana.dev.rtsoft.ru>

Thanks to the previous refactorings, nothing fancy needs to be
done, just use generic SCU routines.

Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
---
 arch/arm/Kconfig                         |    2 +-
 arch/arm/mach-cns3xxx/Kconfig            |    1 +
 arch/arm/mach-cns3xxx/Makefile           |    1 +
 arch/arm/mach-cns3xxx/include/mach/smp.h |   31 +++++++++++++
 arch/arm/mach-cns3xxx/platsmp.c          |   69 ++++++++++++++++++++++++++++++
 5 files changed, 103 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-cns3xxx/include/mach/smp.h
 create mode 100644 arch/arm/mach-cns3xxx/platsmp.c

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index fab2ddd..c6e12d7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1100,7 +1100,7 @@ config SMP
 	bool "Symmetric Multi-Processing (EXPERIMENTAL)"
 	depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
 		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
-		 ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
+		 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_CNS3XXX)
 	depends on GENERIC_CLOCKEVENTS
 	select USE_GENERIC_SMP_HELPERS
 	select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index 9ebfcc4..b510dab 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -3,6 +3,7 @@ menu "CNS3XXX platform type"
 
 config MACH_CNS3420VB
 	bool "Support for CNS3420 Validation Board"
+	select HAVE_ARM_SCU
 	help
 	  Include support for the Cavium Networks CNS3420 MPCore Platform
 	  Baseboard.
diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile
index 11033f1..ba4ee7b 100644
--- a/arch/arm/mach-cns3xxx/Makefile
+++ b/arch/arm/mach-cns3xxx/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_ARCH_CNS3XXX)		+= core.o pm.o devices.o
+obj-$(CONFIG_SMP)			+= platsmp.o
 obj-$(CONFIG_PCI)			+= pcie.o
 obj-$(CONFIG_MACH_CNS3420VB)		+= cns3420vb.o
diff --git a/arch/arm/mach-cns3xxx/include/mach/smp.h b/arch/arm/mach-cns3xxx/include/mach/smp.h
new file mode 100644
index 0000000..afb2fef
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/include/mach/smp.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2002 ARM Ltd.
+ * Copyright 2008 Cavium Networks
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_SMP_H
+#define __MACH_SMP_H
+
+#include <asm/hardware/gic.h>
+
+#define hard_smp_processor_id()				\
+	({						\
+		unsigned int cpunum;			\
+		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
+			: "=r" (cpunum));		\
+		cpunum &= 0x0F;				\
+	})
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(const struct cpumask *mask)
+{
+	gic_raise_softirq(mask, 1);
+}
+
+#endif /* __MACH_SMP_H */
diff --git a/arch/arm/mach-cns3xxx/platsmp.c b/arch/arm/mach-cns3xxx/platsmp.c
new file mode 100644
index 0000000..fc1595c
--- /dev/null
+++ b/arch/arm/mach-cns3xxx/platsmp.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2002 ARM Ltd
+ * Copyright 2008 Cavium Networks
+ * Copyright 2010 MontaVista Software, LLC.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License, Version 2, as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <asm/unified.h>
+#include <asm/smp_scu.h>
+#include <mach/cns3xxx.h>
+#include "core.h"
+
+static void __iomem *scu_base_addr(void)
+{
+	return (void __iomem *)CNS3XXX_TC11MP_SCU_BASE_VIRT;
+}
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+	trace_hardirqs_off();
+
+	/*
+	 * if any interrupts are already enabled for the primary
+	 * core (e.g. timer irq), then they will not have been enabled
+	 * for us: do so
+	 */
+	gic_cpu_init(0, gic_cpu_base_addr);
+
+	scu_secondary_init(cpu);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	return scu_boot_secondary(cpu, idle);
+}
+
+void __init smp_init_cpus(void)
+{
+	scu_init_cpus(scu_base_addr());
+}
+
+static void __init poke_milo(void)
+{
+	if (num_present_cpus() <= 1)
+		return;
+	/*
+	 * Write the address of secondary startup into the system-wide flags
+	 * register. The BootMonitor waits for this register to become
+	 * non-zero.
+	 */
+	__raw_writel(BSYM(virt_to_phys(scu_secondary_startup)),
+		     (void __iomem *)(0xFFF07000 + 0x0600));
+
+	mb();
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+	scu_prepare_cpus(scu_base_addr(), max_cpus);
+	poke_milo();
+}
-- 
1.7.0.5


From s.hauer at pengutronix.de  Fri Jun 18 16:54:01 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Fri, 18 Jun 2010 22:54:01 +0200
Subject: [PATCH 4/5] mtd: mxc_nand fixups
In-Reply-To: <804oh0b7gx.fsf@merkur.tec.linutronix.de>
References: <804oh0b7gx.fsf@merkur.tec.linutronix.de>
Message-ID: <20100618205401.GA12115@pengutronix.de>

[added Ivo to Cc]

On Fri, Jun 18, 2010 at 07:01:34PM +0200, John Ogness wrote:
> This patch reverts the driver to enabling/disabling the NFC interrupt
> mask rather than enabling/disabling the system interrupt. This cleans
> up the driver so that it doesn't rely on interrupts being disabled
> within the interrupt handler.

This behaviour was introduced in
a47bfd2eb66837653dc3b42541dfe4283dd41251 mxc_nand: support i.MX21

I guess this won't work on i.MX21.

Sascha

> 
> The patch is against linux-next 20100618.
> 
> Signed-off-by: John Ogness <john.ogness at linutronix.de>
> ---
>  drivers/mtd/nand/mxc_nand.c |   11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> Index: linux-next-20100618/drivers/mtd/nand/mxc_nand.c
> ===================================================================
> --- linux-next-20100618.orig/drivers/mtd/nand/mxc_nand.c
> +++ linux-next-20100618/drivers/mtd/nand/mxc_nand.c
> @@ -173,8 +173,11 @@ static const char *part_probes[] = { "Re
>  static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
>  {
>  	struct mxc_nand_host *host = dev_id;
> +	uint16_t tmp;
>  
> -	disable_irq_nosync(irq);
> +	tmp = readw(host->regs + NFC_CONFIG1);
> +	tmp |= NFC_INT_MSK; /* disable NFC interrupts */
> +	writew(tmp, host->regs + NFC_CONFIG1);
>  
>  	wake_up(&host->irq_waitq);
>  
> @@ -192,7 +195,9 @@ static void wait_op_done(struct mxc_nand
>  	if (useirq) {
>  		if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
>  
> -			enable_irq(host->irq);
> +			tmp = readw(host->regs + NFC_CONFIG1);
> +			tmp  &= ~NFC_INT_MSK;   /* enable NFC interrupts */
> +			writew(tmp, host->regs + NFC_CONFIG1);
>  
>  			wait_event(host->irq_waitq,
>  				readw(host->regs + NFC_CONFIG2) & NFC_INT);
> @@ -846,7 +851,7 @@ static int __init mxcnd_probe(struct pla
>  
>  	host->irq = platform_get_irq(pdev, 0);
>  
> -	err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
> +	err = request_irq(host->irq, mxc_nfc_irq, 0, DRIVER_NAME, host);
>  	if (err)
>  		goto eirq;
>  
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From ryan at bluewatersys.com  Fri Jun 18 18:01:45 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Sat, 19 Jun 2010 10:01:45 +1200
Subject: gpiolib and sleeping gpios
In-Reply-To: <514259.95052.qm@web180315.mail.gq1.yahoo.com>
References: <514259.95052.qm@web180315.mail.gq1.yahoo.com>
Message-ID: <4C1BECC9.7000805@bluewatersys.com>

David Brownell wrote:
> 
> --- On Thu, 6/17/10, Ryan Mallon <ryan at bluewatersys.com> wrote:
>> Currently implementors of gpiolib must provide
>> implementations for
>> gpio_get_value, gpio_set_value and gpio_cansleep. 
> 
> Not true.  There is ONE implementation of gpiolib.
> 
> I think you mean "implementors of the GPIO calls".
> many of those implementors will use gpiolib, to
> make their lives easier.  They are not, however,
> re-implementing gpiolib itself...

Okay, so I got the semantics wrong. You know what I mean :-).

<snip>

> 
> only the cansleep() versions may be used for
> GPIOs whose operation requires use of sleeping
> calls.  Most SoC GPIOs are safe to access with
> IRQs disabled, spinlocks, held and so on.
> 
> That's why only the non-cansleep() versions
> are documented as being spinlock-safe.
> 
> 
>> the cansleep versions calls might_sleep_if. Most drivers
> 
> 
> That's an implemenation detail, internal to the
> gpiolib code.
> 
> Note that "can" sleep means exactly that...  It
> doesn't mean "must sleep".  A valid way to
> implement a cansleep() variant is to 
> 
> just call the spinlock-safe routine, so that
> it never sleeps.
> 
> THe converse is not true; the spinlock-safe
> routine must never call a cansleep() version.

Right, so it is just an implementation detail. When can easily change
that to gpio_(set/get)_value is only safe to call from spinlock context
if the gpio will not sleep. Having the the might_sleep_if check inside
those calls will give a warning if that condition is not met.

> 
>>  Most drivers call > gpio_(get/set)_value, rather than the cansleep variants. I
>> haven't done
>> a full audit of all of the drivers (which is a reasonably
>> involved
>> task), but I would hazard a guess that some of these could
>> be replaced
>> by the cansleep versions.
> 
> 
> One hopes that the runtime warnings have gotten
> folk to fix bugs where the cansleep() version
> should have been used, but wasn't...

The runtime warnings will only show instances where the non-sleeping
versions where called instead of the sleeping versions. There is no
warning to say that we are calling the spinlock safe version, where it
is possible to sleep.

The point I was trying to make is that there are lots of drivers which
will not work with gpios on sleeping io expanders because they call the
spinlock safe gpio calls. Some of these drivers may be able to use the
sleeping variants. There are two possible ways to fix this:

1) Audit each driver which uses non-sleeping gpio calls and determine
whether they can use the sleeping versions instead.
2) Modify the gpiolib calls as I suggested. Any attempts to use a
sleeping gpio with a driver which cannot support it will result in a
warning.

> 
> Better IMO not to make that change except as
> part
> of a bugfix:  e.g. remove a runtime warning
> that boils down to not using the cansleep()
> version when it should have been used.
>> Would it not be simpler to combine the calls and have
>> something like this:
>>
>> void __gpio_get_value(unsigned gpio, int value)
>> {
>>     struct gpio_chip *chip;
>>
>>     chip = gpio_to_chip(gpio);
>>     might_sleep_if(extra_checks &&
>> chip->can_sleep);
>>     chip->set(chip, gpio - chip->base,
> 
>> value);
> 
> calling chip->set() when  chip->can_sleep
> and the call context can't be preempted,
> would be a bug.  So that code is wrong ...
> it should at least warn about the error
> made by the caller.  If we had error returns from gpio get/set calls 9sigh), it'd be right to
> fail that call.

Not quite sure what you mean here? Many drivers are generic in that they
get passed a gpio to use with the gpiolib calls via some platform/driver
data. Some drivers will be able to use sleeping gpios, but may not be
correctly using the cansleep variants.

I agree about the errors from the gpio_(set/get)_value calls. set isn't
too bad, but returning an error and a value from the get calls is a bit
of a pain.

Possibly a solution is to have an additional argument to gpio_request
which specifies whether the driver this gpio is able to be a sleeping
gpio or not. That way the request can fail immediately if a sleeping
gpio is passed to a driver that calls gpiolibs calls from sleeping context.

~Ryan



From frank.rowand at am.sony.com  Fri Jun 18 18:12:03 2010
From: frank.rowand at am.sony.com (Frank Rowand)
Date: Fri, 18 Jun 2010 15:12:03 -0700
Subject: Request review of device tree documentation
In-Reply-To: <20100616.005237.338122493954307067.imp@bsdimp.com>
References: <4C186B7B.1060308@firmworks.com>
	<4C186C72.2020506@compulab.co.il>	<4C187013.5000400@firmworks.com>
	<20100616.005237.338122493954307067.imp@bsdimp.com>
Message-ID: <4C1BEF33.7090400@am.sony.com>

On 06/15/10 23:52, M. Warner Losh wrote:
> In message: <4C187013.5000400 at firmworks.com>
>             Mitch Bradley <wmb at firmworks.com> writes:
> : Mike Rapoport wrote:
> : > Mitch Bradley wrote:
> : >> Mike Rapoport wrote:
> : >>> Mitch Bradley wrote:
> : >>>
> : >>>> The second topic is the hypothetical use of OFW as a HAL. That will
> : >>>> not happen for several reasons.  The opposition to the idea is
> : >>>> widespread and deeply held, and there are good arguments to support
> : >>>> that opposition.  Furthermore, the economic conditions necessary for
> : >>>> the creation of such a HAL do not exist in the ARM world, nor indeed
> : >>>> in the Linux world in general.  (The necessary condition is the
> : >>>> ability for one company to impose a substantial change by fiat -
> : >>>> essentially a monopoly position.)
> : >>>>
> : >>>> Shall we agree, then, that any further discussion of the HAL issue is
> : >>>> "just for fun", and that nobody needs to feel threatened that it would
> : >>>> actually happen?
> : >>>
> : >>> I've recently worked with vendor versions of U-Boot for advanced ARM
> : >>> SoCs. There is already *huge* chunk of HAL code in those versions. And
> : >>> if there would be possibility to have callbacks into the firmware
> : >>> these chunks would only grow, IMHO.
> : >>
> : >> How can there be HAL code in U-Boot unless there is already the
> : >> possibility to have callbacks into the firmware?
> : >
> : > Currently it aims to abstract hardware from U-Boot and reuse the same
> : > HW access code across operating systems and bootloaders. If this code
> : > would have callbacks I afraid the things would became worse.
> : 
> : The only way I can understand what you said is if I assume that by
> : "callback", you mean the following sequence:
> : 
> : a) U-boot loads and executes the OS, providing to the OS the address
> : of some HW access routines that it can use
> : b) The OS calls one of those HW access routines
> : c) During the execution of that HW access routine, that routine calls
> : "back" into the OS, before returning.  So a call into the OS is nested
> : inside a call into U-boot resident code.
> : 
> : If that is what you are worried about, it is not what we were
> : discussing.  We were discussing - and many people were against - step
> : (b).
> : 
> : Are you saying that step (b) - the OS calling into routines provided
> : by U-Boot - is already the status quo?
> 
> I don't know about status quo, but it certainly is supported.  There's
> an option to allow for a secondary boot loader, such as FreeBSD's
> /boot/loader, to call back into uboot to read things from
> flash/disk/whatever, do network access, etc.  Not so much a HAL, but
> more of an echo of the functionality provided by PC BIOS functions.
> /boot/loader can be viewed as a mini OS that calls back into uboot to
> have it do things.  Once /boot/loader loads FreeBSD, btw, it and uboot
> disappear from the scene, so this isn't exactly a HAL situation...

Just for reference, there is a patch request on LKML to enable calling
openfirmware from the kernel on OLPC:

   http://lkml.org/lkml/2010/6/18/336

-Frank



From redhatter at gentoo.org  Fri Jun 18 18:43:14 2010
From: redhatter at gentoo.org (Stuart Longland)
Date: Sat, 19 Jun 2010 08:43:14 +1000
Subject: [alsa-devel] [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
In-Reply-To: <20100618155322.GB16941@rakim.wolfsonmicro.main>
References: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
	<1276858862.3054.28.camel@odin>
	<20100618113335.GB30868@www.longlandclan.yi.org>
	<20100618155322.GB16941@rakim.wolfsonmicro.main>
Message-ID: <20100618224313.GC30868@www.longlandclan.yi.org>

On Fri, Jun 18, 2010 at 04:53:23PM +0100, Mark Brown wrote:
> On Fri, Jun 18, 2010 at 09:33:35PM +1000, Stuart Longland wrote:
> > On Fri, Jun 18, 2010 at 12:01:02PM +0100, Liam Girdwood wrote:
> > > On Fri, 2010-06-18 at 13:57 +1000, Stuart Longland wrote:
> 
> > > > The audio interface supports many data bus formats, including I??S
> > > > master/slave, DSP, left/right justified and TDM.
> 
> > > Just had a quick check and the register caching needs addressed.
> 
> > > I agree with your comments, I don't think we really want to cache all
> > > 16K of codec registers here as we will probably only ever use a handful
> > > of them. I think a smaller lookup table containing only the registers
> > > that we care about will do.
> 
> > Yeah, I wasn't sure how to go about it.  It's inefficient, but it's
> > simple, and works.  Other options I've considered;
> 
> > (1) Mark's suggestion of using per-page arrays
> > (2) Using address translation. that is:
> > 	- Page 0 registers 0-127 stored in cache array elements 0-127
> > 	- Page 1 registers 0-127 stored in cache array elements 128-255
> > 	- Page 2..7 are skipped
> > 	- Page 8 registers 0-127 stored in cache array elements 256-383
> > 	... etc.
> 
> Option 2 is what others have used here.  I do think that anything we do
> here really ought to have some sort of page mapping support whatever the
> actual implementation it uses - TI in particular have a bunch of chips
> which do this so there's a general call for something that can handle
> them.
> 
> If you are going to do a lookup table one way of doing this would be to
> have the lookup table be a table of range mappings (I've not looked at
> the patch, perhaps that's what you've done already) - just so long as
> it's got the concept of pages covered somehow.

Yeah... for now I've re-sent a new patch... it's on its way... with the
register cache in its present form.  It's huge and unsightly, but won't
otherwise cause a problem.

I'd sooner get the driver out there in its known working form, then come
up with a solution to fix the problem in a scalable fashion, then
quickly try to hack something up here (I'm at home presently) where I
have no test hardware to check I haven't broken something... and where
the implementation and design will likely be an appauling mess. ;-)

> > Another thought regarding register cache, rather than hard-coding it the
> > way we presently do, we could also build up the cache on demand... that
> > is, we maintain a table of previously read registers; if a register
> > value is read for the first time, an actual read is done from the CODEC
> > (or the value is copied from a static table).  All subsequent reads then
> > come from cache.  On suspend; if a register has not been touched, it is
> > deemed to be left at default settings, and skipped on resume.
> 
> The only problem with this is that for a number of reasons a lot of
> devices have no read functionality at all.  These need us to supply the
> defaults from outside the device, though other devices could use what
> you suggest.  I'd not be so bothered about the performance here - this
> has to be high performance in comparison with doing I/O on a slow bus
> such as I2C.  If we do run into performance issues we can always work on
> substituting in a higher performance algorithm later, if everything is
> well encapsulated this should be doable without much disruption.
> 
> It's also useful to have the actual defaults available for allowing
> writes to be skipped when powering up the device (eg, on resume) - these
> could be cached on first write so it's not insurmountable but it does
> need to be considered.

Indeed... I don't check if a register has been modified; I just copy it
across anyway.  I'm aware some devices do not implement reads, that was
a comment made about the TLV320AIC3X device driver that I based my
driver on... in this situation you'd have no choice but to do it the way
it's presently done now.

I'll think about this over the next few days... but I'm thinking the
basic structure of such a register cache would possibly take the form of
something like this:

struct soc_reg_cache_pg {
	/* Page index; for single-page registers, this would be zero */
	int index;
	/* Number of registers cached */
	int size;
	/* Register offset cached */
	int offset;
	/* Pointer to register flags */
	const int *flags_data[];
	/* Pointer to default values */
	const int *default_data[];
	/* Pointer to cached values */
	int *cached_data[];
	/* Pointer to next block of page registers (for sparse maps) */
	struct soc_reg_cache_pg *next_block;
};

... then you'd use several of these in an array... one for each block of
registers in a page.  If your device uses sparse registers, you can use
the next_block pointer to point to the next such struct that has the
next bank of registers, to save you scanning through *every* struct.

The register cache could be an array of pointers, size equal to the
total number of pages, if a page is not used; it is set to NULL.  If a
page is sparse, the other blocks would be accessed using the next_block
pointer.

The flags_data array would be optional; and could be used to indicate
the read/write status, volatile bits, and other information.  It'd be a
bitfield.

Thoughts?

Regards,
-- 
Stuart Longland (aka Redhatter, VK4MSL)      .'''.
Gentoo Linux/MIPS Cobalt and Docs Developer  '.'` :
. . . . . . . . . . . . . . . . . . . . . .   .'.'
http://dev.gentoo.org/~redhatter             :.'

I haven't lost my mind...
  ...it's backed up on a tape somewhere.


From broonie at opensource.wolfsonmicro.com  Fri Jun 18 21:12:21 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 19 Jun 2010 02:12:21 +0100
Subject: [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
In-Reply-To: <1276899876-19001-1-git-send-email-redhatter@gentoo.org>
References: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
	<1276899876-19001-1-git-send-email-redhatter@gentoo.org>
Message-ID: <20100619011221.GC2463@opensource.wolfsonmicro.com>

On Sat, Jun 19, 2010 at 08:24:36AM +1000, Stuart Longland wrote:

This all looks pretty good, the comments below are fairly minor.

> +	/* AVDD <->DVDD Link enable */
> +	u8	avdd_link_en;

What's this?  It looks like a boolean which makes u8 an odd choice.

> +	/* LDO Enable */
> +	u8	ldo_en;

Similarly here.

> +
> +	/* Oversampling rate (both ADC and DAC) */
> +	u8	osr;

Why is this platform data rather than a runtime configurable option?

> +config SND_SOC_TLV320AIC3204
> +	tristate
> +	depends on I2C
> +

Drop the depends, it doesn't actually do anything for selected items.

> +	/* Page 1 */
> +	if (page == 1) {
> +		if (reg <= 4)
> +			return 1;

I can't help but think that this'd be more legible with switch ()
statements (GCC has an extension for ranges in switch statements which
you could use).

> +/*
> + * Pretty-print the value of a register
> + */
> +static int aic3204_show_reg(struct snd_soc_codec *codec, char *buf,
> +		int buf_sz, unsigned int reg)
> +{
> +	return snprintf(buf, buf_sz, "%02x",
> +			aic3204_read_reg_cache(codec, reg));
> +}

This looks suspiciously close to the standard show_reg() - it seems
wrong that you should need it.

> +	/*
> +	 * These registers are not manipulated by us, so we must read them from
> +	 * the CODEC directly.
> +	 */

Hrm?  Also, it strikes me that this code is also used in the WCLK
function and might benefit from being factored out - it's moderately
verbose.

> +static const char *aic3204_micbias_voltages[] = {
> +	"Low", "Med", "High", "V+"
> +};

I'd be inclined to spell medium out and write "V+" as "Supply" or
similar unless there's a strong reason to do otherwise - it seems more
legible.

> +static const char *aic3204_ldac_srcs[] = {
> +	"disabled", "left channel", "right channel", "mix"
> +};

Capital letters are more idiomatic for enumerations.

> +/*
> + * DAC digital volumes. From -63.5 to +24 dB in 0.5 dB steps.
> + * Does not mute control.
> + */

I'm finding these comments a little too verbose but that's just me -
I stop and read them only to find there's nothing odd going on here.

> +	/*
> +	 * Note regarding SOC_DOUBLE_R_SX_TLV...
> +	 *
> +	 * This is a bit misleading; xshift refers to the bit one bit *past*
> +	 * the most significant bit.  Or at least that's what it appears to be
> +	 * doing the math.  Mask needs to select the last 6 bits; which is the
> +	 * signed bitfield specifiying the gain in dB.
> +	 */

I suspect that fixing the control may break what you're doing here?  It
would certainly bitrot the comment.

> +	SOC_SINGLE("Differential Output Switch", AIC3204_DACS2,
> +			AIC3204_DACS2_RMOD_INV_SHIFT, 1, 0),

This feels like platform data - the use of differential outputs is
normally a property of the physical wiring of the board, it's very rare
to be able to vary this usefully at runtime.

> +	/* MICBIAS Options */
> +	SOC_SINGLE("MICBIAS Enable", AIC3204_MICBIAS, 6, 0x1, 0),

MICBIAS Enable should definitely be DAPM.

> +	SOC_ENUM("MICBIAS Level", aic3204_enum_micbias_voltage),
> +	SOC_ENUM("MICBIAS Source", aic3204_enum_micbias_src),

These I would expect to be managed in kernel - they're normally either a
property of the board or need to be managed in conjunction with jack
detection code which tends to live in kernel.

> +static const struct snd_soc_dapm_widget aic3204_dapm_widgets[] = {
> +	/* Driver/Amplifier Selection */
> +	SND_SOC_DAPM_SWITCH("HPL Playback Switch", AIC3204_OUTDRV,
> +			AIC3204_OUTDRV_HPL_UP_SHIFT, 0,
> +			&aic3204_hpl_switch),
> +	SND_SOC_DAPM_SWITCH("HPR Playback Switch", AIC3204_OUTDRV,
> +			AIC3204_OUTDRV_HPR_UP_SHIFT, 0,
> +			&aic3204_hpr_switch),

A lot of these SWITCH controls feel like they ought to be PGAs and the
switch controls mutes on those.  When muting an output you normally
don't want to power up and down the path since that is slow and tends to
trigger audible issues, you'd normally control the power for path
endpoints and elements that affect routing only.

> +	SND_SOC_DAPM_AIF_IN("Left Data In", "Left Playback",
> +			0, SND_SOC_NOPM, 0, 0),
> +	SND_SOC_DAPM_AIF_IN("Right Data In", "Right Playback",
> +			1, SND_SOC_NOPM, 0, 0),
> +	SND_SOC_DAPM_AIF_OUT("Left Data Out", "Left Capture",
> +			0, SND_SOC_NOPM, 0, 0),
> +	SND_SOC_DAPM_AIF_OUT("Right Data Out", "Right Capture",
> +			1, SND_SOC_NOPM, 0, 0),

You have these AIF widgets but at least the DAC input selection was
being done in the regular controls rather than in the DAPM routing.

> +	/*
> +	 * Set BCLK and WCLK sources...
> +	 *
> +	 * Despite DAPM; this is still needed, as DAPM doesn't yet set the
> +	 * source at the right time.
> +	 *
> +	 * TODO: See if we can change the order of initialisation so this
> +	 * selection is made after bringing up the ADCs/DACs.  Alternative:
> +	 * see if we can find out ahead of time which one to use.

It surprises me that the ordering matters too much here; worst case you
leave the interface declocked a little longer when you need to switch
sources but that doesn't seem like the end of the world?

> +	snd_soc_update_bits(codec, AIC3204_AISR3, AIC3204_AISR3_BDIV,
> +			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
> +				? AIC3204_AISR3_BDIV_DAC
> +				: AIC3204_AISR3_BDIV_ADC);

I have to say that I'm really not a fan of the ternery operator for
legibility.

> +static int aic3204_mute(struct snd_soc_dai *dai, int mute)
> +{

...

> +	aic3204_write(codec, AIC3204_DACS2, dacs2);	/* Unmute DAC */

...or possibly mute it :)

> +static int aic3204_resume(struct platform_device *pdev)
> +{
> +	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
> +	struct snd_soc_codec *codec = socdev->card->codec;
> +	int i;
> +	u8 data[2];
> +	u8 *cache = codec->reg_cache;
> +
> +	/* Sync reg_cache with the hardware */
> +	for (i = 0; i < AIC3204_CACHEREGNUM; i++) {
> +		data[0] = i;
> +		data[1] = cache[i];
> +		codec->hw_write(codec->control_data, data, 2);

Since you've got a register defaults table you could skip rewriting
registers which have their default value.

> +	/* LDO enable, analogue blocks enable */
> +	snd_soc_update_bits(codec, AIC3204_LDO,
> +			AIC3204_LDO_ANALOG | AIC3204_LDO_AVDD_UP,
> +			AIC3204_LDO_ANALOG_ENABLED |
> +			(aic3204->pdata.ldo_en
> +			  ? AIC3204_LDO_AVDD_UP : 0));

This looks a bit fishy since the mask covers more bits than can ever be
enabled - it reads like the other two bits should be unconditionally
cleared.


From broonie at opensource.wolfsonmicro.com  Fri Jun 18 21:25:09 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 19 Jun 2010 02:25:09 +0100
Subject: [alsa-devel] [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
In-Reply-To: <20100618224313.GC30868@www.longlandclan.yi.org>
References: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
	<1276858862.3054.28.camel@odin>
	<20100618113335.GB30868@www.longlandclan.yi.org>
	<20100618155322.GB16941@rakim.wolfsonmicro.main>
	<20100618224313.GC30868@www.longlandclan.yi.org>
Message-ID: <20100619012509.GD2463@opensource.wolfsonmicro.com>

On Sat, Jun 19, 2010 at 08:43:14AM +1000, Stuart Longland wrote:

> I'll think about this over the next few days... but I'm thinking the
> basic structure of such a register cache would possibly take the form of
> something like this:
> 
> struct soc_reg_cache_pg {
> 	/* Page index; for single-page registers, this would be zero */
> 	int index;
> 	/* Number of registers cached */
> 	int size;
> 	/* Register offset cached */
> 	int offset;
> 	/* Pointer to register flags */
> 	const int *flags_data[];
> 	/* Pointer to default values */
> 	const int *default_data[];

This should probably be either unsigned or void (the latter allowing for
pluggable register sizes - otherwise you might burn as much data as you
save from the sparseness on chips that have small registers).

> ... then you'd use several of these in an array... one for each block of
> registers in a page.  If your device uses sparse registers, you can use
> the next_block pointer to point to the next such struct that has the
> next bank of registers, to save you scanning through *every* struct.

This is going to be painful to write out when writing the data table -
if it's useful to do it'd be better to do it at runtime, but I think
rather than handling pages it would be at least as easy to munge the
page number into the register number like everyone does at the minute
and then just optimise plain register lookups in a sparse map.  That way
way sparse chips of all kinds get the benefit.

> The register cache could be an array of pointers, size equal to the
> total number of pages, if a page is not used; it is set to NULL.  If a
> page is sparse, the other blocks would be accessed using the next_block
> pointer.

Like I say, I think optimising for page based access is not the most
general approach - it'd be better to optimise sparse register maps in
general and then map page based register maps onto this.


From broonie at opensource.wolfsonmicro.com  Fri Jun 18 21:36:29 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 19 Jun 2010 02:36:29 +0100
Subject: [PATCH] ASoC: Fix overflow bug in SOC_DOUBLE_R_SX_TLV
In-Reply-To: <1276829770-31557-1-git-send-email-redhatter@gentoo.org>
References: <20100618023810.GS7759@www.longlandclan.yi.org>
	<1276829770-31557-1-git-send-email-redhatter@gentoo.org>
Message-ID: <20100619013629.GA2974@opensource.wolfsonmicro.com>

On Fri, Jun 18, 2010 at 12:56:10PM +1000, Stuart Longland wrote:
> When SX_TLV widgets are read, if the gain is set to a value below 0dB,
> the mixer control is erroniously read as being at maximum volume.

Applied, thanks.

BTW, you might want to have a look at the CCs - you probably don't need
to CCing the ARM list for ASoC patches that aren't ARM specific, for
example.


From kgene.kim at samsung.com  Fri Jun 18 22:28:31 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 19 Jun 2010 11:28:31 +0900
Subject: [PATCH 2/2] ARM: SAMSUNG: Make WDT driver dependency SoC specific
	instead of machine specific
In-Reply-To: <1276914511-7677-1-git-send-email-kgene.kim@samsung.com>
References: <1276914511-7677-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1276914511-7677-2-git-send-email-kgene.kim@samsung.com>

From: Banajit Goswami <banajit.g at samsung.com>

This patch moves the dependency of watchdog timer driver from
MACH_XXX(board) to ARCH_XXX(SoC). This will enable all machines
using Samsung S3C64XX, S5P6440, S5PC100 and S5PV210/S5PC110 SoCs
to use the WDT driver by default.

Signed-off-by: Banajit Goswami <banajit.g at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/Kconfig              |    4 ++++
 arch/arm/mach-s3c64xx/Kconfig |    1 -
 arch/arm/mach-s5p6440/Kconfig |    1 -
 arch/arm/mach-s5pc100/Kconfig |    1 -
 arch/arm/mach-s5pv210/Kconfig |    2 --
 5 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..47fb03e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -663,6 +663,7 @@ config ARCH_S3C64XX
 	select S3C_DEV_NAND
 	select USB_ARCH_HAS_OHCI
 	select SAMSUNG_GPIOLIB_4BIT
+	select HAVE_S3C2410_WATCHDOG
 	help
 	  Samsung S3C64XX series based systems
 
@@ -672,6 +673,7 @@ config ARCH_S5P6440
 	select GENERIC_GPIO
 	select HAVE_CLK
 	select ARCH_USES_GETTIMEOFFSET
+	select HAVE_S3C2410_WATCHDOG
 	help
 	  Samsung S5P6440 CPU based systems
 
@@ -691,6 +693,7 @@ config ARCH_S5PC100
 	select CPU_V7
 	select ARM_L1_CACHE_SHIFT_6
 	select ARCH_USES_GETTIMEOFFSET
+	select HAVE_S3C2410_WATCHDOG
 	help
 	  Samsung S5PC100 series based systems
 
@@ -701,6 +704,7 @@ config ARCH_S5PV210
 	select HAVE_CLK
 	select ARM_L1_CACHE_SHIFT_6
 	select ARCH_USES_GETTIMEOFFSET
+	select HAVE_S3C2410_WATCHDOG
 	help
 	  Samsung S5PV210/S5PC110 series based systems
 
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index f5a5972..915cb47 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -100,7 +100,6 @@ config MACH_SMDK6410
 	select S3C_DEV_USB_HOST
 	select S3C_DEV_USB_HSOTG
 	select S3C_DEV_WDT
-	select HAVE_S3C2410_WATCHDOG
 	select S3C64XX_SETUP_SDHCI
 	select S3C64XX_SETUP_I2C1
 	select S3C64XX_SETUP_FB_24BPP
diff --git a/arch/arm/mach-s5p6440/Kconfig b/arch/arm/mach-s5p6440/Kconfig
index f066fae..084c0bc 100644
--- a/arch/arm/mach-s5p6440/Kconfig
+++ b/arch/arm/mach-s5p6440/Kconfig
@@ -19,7 +19,6 @@ config MACH_SMDK6440
 	select SAMSUNG_DEV_TS
 	select SAMSUNG_DEV_ADC
 	select S3C_DEV_WDT
-	select HAVE_S3C2410_WATCHDOG
 	help
 	  Machine support for the Samsung SMDK6440
 
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b63b440..0593b3f 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -45,7 +45,6 @@ config MACH_SMDKC100
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_HSMMC2
 	select S3C_DEV_WDT
-	select HAVE_S3C2410_WATCHDOG
 	select S5PC100_SETUP_FB_24BPP
 	select S5PC100_SETUP_I2C1
 	select S5PC100_SETUP_SDHCI
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0761eac..2e3ed18 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -74,7 +74,6 @@ config MACH_SMDKV210
 	select SAMSUNG_DEV_ADC
 	select SAMSUNG_DEV_TS
 	select S3C_DEV_WDT
-	select HAVE_S3C2410_WATCHDOG
 	help
 	  Machine support for Samsung SMDKV210
 
@@ -83,7 +82,6 @@ config MACH_SMDKC110
 	select CPU_S5PV210
 	select ARCH_SPARSEMEM_ENABLE
 	select S3C_DEV_WDT
-	select HAVE_S3C2410_WATCHDOG
 	help
 	  Machine support for Samsung SMDKC110
 	  S5PC110(MCP) is one of package option of S5PV210
-- 
1.6.2.5



From kgene.kim at samsung.com  Fri Jun 18 22:28:30 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 19 Jun 2010 11:28:30 +0900
Subject: [PATCH 1/2] ARM: S5PC100: Add Watchdog support for S5PC100
Message-ID: <1276914511-7677-1-git-send-email-kgene.kim@samsung.com>

From: Banajit Goswami <banajit.g at samsung.com>

This patch adds support for Watchdog timer for Samsung S5PC100.

Signed-off-by: Banajit Goswami <banajit.g at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pc100/Kconfig            |    2 ++
 arch/arm/mach-s5pc100/include/mach/map.h |    3 +++
 arch/arm/mach-s5pc100/mach-smdkc100.c    |    1 +
 3 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b2a11df..b63b440 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -44,6 +44,8 @@ config MACH_SMDKC100
 	select S3C_DEV_HSMMC
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_HSMMC2
+	select S3C_DEV_WDT
+	select HAVE_S3C2410_WATCHDOG
 	select S5PC100_SETUP_FB_24BPP
 	select S5PC100_SETUP_I2C1
 	select S5PC100_SETUP_SDHCI
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index cadae43..4b3a7b7 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -72,6 +72,8 @@
 
 #define S5PC100_PA_SYSTIMER	(0xEA100000)
 
+#define S5PC100_PA_WATCHDOG	(0xEA200000)
+
 #define S5PC100_PA_UART		(0xEC000000)
 
 #define S5P_PA_UART0		(S5PC100_PA_UART + 0x0)
@@ -131,6 +133,7 @@
 #define S3C_PA_HSMMC2		S5PC100_PA_HSMMC(2)
 #define S3C_PA_KEYPAD		S5PC100_PA_KEYPAD
 #define S3C_PA_TSADC		S5PC100_PA_TSADC
+#define S3C_PA_WDT		S5PC100_PA_WATCHDOG
 #define S3C_PA_ONENAND		S5PC100_PA_ONENAND
 #define S3C_PA_ONENAND_BUF	S5PC100_PA_ONENAND_BUF
 #define S3C_SZ_ONENAND_BUF	S5PC100_SZ_ONENAND_BUF
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index af22f82..6fc0bff 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -156,6 +156,7 @@ static struct platform_device *smdkc100_devices[] __initdata = {
 	&s3c_device_hsmmc0,
 	&s3c_device_hsmmc1,
 	&s3c_device_hsmmc2,
+	&s3c_device_wdt,
 	&smdkc100_lcd_powerdev,
 	&s5pc100_device_iis0,
 	&s5pc100_device_ac97,
-- 
1.6.2.5



From kgene.kim at samsung.com  Fri Jun 18 23:55:05 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Sat, 19 Jun 2010 12:55:05 +0900
Subject: [PATCH] S5PV210 Correct clock source control register properties
In-Reply-To: <AANLkTim1psO4ZeZGAgNteJp_ytRhzoPlu4D3VblPgz6w@mail.gmail.com>
References: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>
	<005401cb0ecb$c3f16c00$4bd44400$%kim@samsung.com>
	<AANLkTim1psO4ZeZGAgNteJp_ytRhzoPlu4D3VblPgz6w@mail.gmail.com>
Message-ID: <000001cb0f63$3682c5b0$a3885110$%kim@samsung.com>

MyungJoo Ham wrote:
> 
> On Fri, Jun 18, 2010 at 6:50 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > MyungJoo Ham wrote:
> >>
> >> The clock source controls (struct clksrc_clk) have been often accessing
> >> CLK_GATE_IPx, which are for clock gating and are accessed by each clock
> >> as well as the clock source. This duplicated clock issue may incur
> >> lockup problems when there are two modules accessing the same clock with
> >> different names.
> >>
> > Could you please explain further about the above the statement " accessed by
> > each clock as well as the clock source"
> 
> For example, "CLK_GATE_IP2[16:19]" is accessed by "hsmmc" of struct
> clk (a clock) and "sclk_mmc" of struct clksrc_clk's struct clk (a
> clock source's clk representation).
> 
> >
> >> Besides, the clock source control is supposed to control (setting values
> >> of MASK, SRC, DIV), not to turn on/off individual clock.
> >>
> > That is not quite true. Only S5PV210/S5PC110 have the gate for the clock mux.
> > S5P6440 and S5PC100, for instance, do not have a gate for the output for
> > _just_ the clock mux. And the reason why the Clock Mux Gate is provide for
> > the mux is explained in Section 3.4 of the user manual.
> 
> In cases where clock mux gating is not available and we have each
> clock (supplied by this cluck mux) defined separatedly with .enable
> and .ctrlbit, we'd better omit .enable/.ctrlbit from struct
> clksrc_clk's struct clk.
> 
> >
> >> Another point is that there are registers (CLK_SRC_MASK0/1) specialized
> >> for masking clock source control in S5PV210/S5PC110 according to the
> >> user manual (rev 20100201).
> >>
> >> Therefore, accessing CLK_SRC_MASK0/1 (rather than accessing
> >> CLK_GATE_IPx) for the clock source control is safer and fits to the
> >> semantics of S5PV210/S5PC110 registers. And fortuneatly, each clock
> >> source defined in clock.c has corresponding bit at CLK_SRC_MASK0/1
> >> except for MFC, G2D, and G3D.
> >>
> > Can you please explain how the use CLK_SRC_MASKx makes it safer. The reason
> > why MFC, G2D and G3D do not have a corresponding bit in CLK_SRC_MASKx is
> > mentioned in Section 3.4 of the user manual.
> >
> > Let me know your opinion.
> >
> 
> It's "EXCEPT FOR MFC, G2D, G3D". I'm not saying that using
> CLK_SRC_MASKx is safer for these three. For other cases, I guess the
> lock up example should be fine.
> 
> However, in most cases, this lockup issue does not make visible problem because:
> 1. normally, drivers use both clksrc_clk's clk and clk at the same
> time. for example
> "mmc_bus".clk_enable;
> "hsmmc".clk_enable;
>  blahblah
> "hsmmc".clk_disable;
> "mmc_bus".clk_disable;
> or
> 2. drivers sharing the same clock uses only one side of the two.
> or
> 3. the execution block between clk_enable and clk_disable is extremely short.
> 
> Nevertheless, this potential lockup issue is critical and we'd better
> address it.
> 
> 
> >> In this patch,
> >>
> >> - DAC, HDMI, AUDIO 0/1/2, UCLK(uart) 0/1/2/3, MIXER, FIMC 0/1/2,
> >> FIMC, MMC 0/1/2/3, CSIS, SPI 0/1, PWI, and PWM clock sources are
> >> modified to use CLK_SRC_MASK0/1, which were using CLK_GATE_IPx.
> >>
> >> - CAM 0/1 did not have enable/disable control. They now access
> >>   CLK_SRC_MASK0.
> >>
> >> - MFC, G3D, G2D were using CLK_GATE_IPx. However, as there are no clocks
> >>   defined to control MFC, G3D, and G2D, we kept them to access
> >> CLK_GATE_IPx. These may need to be modified (erase .enable, .ctrlbit
> >> from sclk_mfc, sclk_g2d, sclk_g3d and create clocks: g3d, g2d, mfc)
> >> later.
> >>
> >> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> >> ---
> >>  arch/arm/mach-s5pv210/clock.c |  101
> > ++++++++++++++++++++++-------------------
> >>  1 files changed, 55 insertions(+), 46 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> >> index ec5ad8c..08c1063 100644
> >> --- a/arch/arm/mach-s5pv210/clock.c
> >> +++ b/arch/arm/mach-s5pv210/clock.c
> >
> > (snip)
> >
> > --

Strictly speaking, 'duplicated clock problem' and 'clock gating issue which is controlled by CLK_GATE_IPx or CLK_SRC_MASKx' are different problem.
But mixed above two things in your patch.

I think just need bug fix.

See below mmc case.

Following is for clock gating mmc IP by using CLK_GATE_IPx and can control(clock gating) clocks, 'aclk_hsmmcX' and 'sclk_mmcX' in the mmc IP.

	{
		.name	= "hsmmc",
		.id	= 0,
		.parent	= &clk_hclk_psys.clk,
		.enable	= s5pv210_clk_ip2_ctrl,
		.ctrlbit	= (1<<16),
	}, {
		.name	= "hsmmc",
		.id	= 1,
		.parent	= &clk_hclk_psys.clk,
		.enable	= s5pv210_clk_ip2_ctrl,
		.ctrlbit	= (1<<17),
	}, {
		.name	= "hsmmc",
		.id	= 2,
		.parent	= &clk_hclk_psys.clk,
		.enable	= s5pv210_clk_ip2_ctrl,
		.ctrlbit	= (1<<18),
	}, {
		.name	= "hsmmc",
		.id	= 3,
		.parent	= &clk_hclk_psys.clk,
		.enable	= s5pv210_clk_ip2_ctrl,
		.ctrlbit	= (1<<19),
	}...

And following is for clock gating just 'sclk_mmcX' by using CLK_SRC_MASKx.
But as you know should be 's5pv210_clk_mask0_ctrl' instead of 's5pv210_clk_ip2_ctrl' like below.

@@ -794,8 +794,8 @@ static struct clksrc_clk clksrcs[] = {
		.clk		= {
			.name		= "sclk_mmc",
			.id		= 0,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit		= (1 << 16),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit		= (1 << 8),
		},
		.sources = &clkset_group2,
		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
@@ -804,8 +804,8 @@ static struct clksrc_clk clksrcs[] = {
		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit		= (1 << 17),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit		= (1 << 9),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
@@ -814,8 +814,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit		= (1 << 18),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit		= (1 << 10),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
@@ -824,8 +824,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 3,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit		= (1 << 19),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit		= (1 << 11),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }


I think there is no lockup issue(problem) after bug fix about 'sclk_xxx'.
Of course, carefully used distinguished clock gating in the relevant device driver.
Because as I said, CLK_GATE_IPx can disable all of the clock operation of each IP.
If no need CLK_GATE_IPx, just do clock gating each 'sclk_xxx'.

Could you please re-submit new stuff for bug fix?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kmpark at infradead.org  Sat Jun 19 00:03:46 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Sat, 19 Jun 2010 13:03:46 +0900
Subject: Pending patches for s5p series
Message-ID: <AANLkTik0r1MXwJ7Htfreh6MSPDWjqiGstiMDLNjFhtBP@mail.gmail.com>

Hi,

Pending or no comments at these patches.

1. [PATCH/RFC] Samsung multimedia (FIMC and FB) drivers proposal
http://marc.info/?l=linux-arm-kernel&m=127668321706310&w=2

2. [PATCH v2] Various s3c-fb updates
http://marc.info/?l=linux-arm-kernel&m=127668095702084&w=2

3. [PATCH v2] SDHCI-S3C fixes and enhancements (driver specific code)
http://marc.info/?l=linux-arm-kernel&m=127667104617587&w=2

4. [RFC/PATCH 0/9] Samsung crypto engine
http://marc.info/?l=linux-arm-kernel&m=127628580015805&w=2

5. [PATCH v2 0/4] ARM: S5P: Support gpio interrupts
http://marc.info/?l=linux-arm-kernel&m=127624524906617&w=2

6. [PATCH v4 0/3] Add samsung keypad
http://marc.info/?l=linux-arm-kernel&m=127624378103808&w=2

Thank you,
Kyungmin Park


From kmpark at infradead.org  Sat Jun 19 00:14:34 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Sat, 19 Jun 2010 13:14:34 +0900
Subject: [PATCH] S5PV210 Correct clock source control register properties
In-Reply-To: <000001cb0f63$3682c5b0$a3885110$%kim@samsung.com>
References: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>
	<005401cb0ecb$c3f16c00$4bd44400$%kim@samsung.com>
	<AANLkTim1psO4ZeZGAgNteJp_ytRhzoPlu4D3VblPgz6w@mail.gmail.com>
	<000001cb0f63$3682c5b0$a3885110$%kim@samsung.com>
Message-ID: <AANLkTikKREVQrwkdc9OW5zlzK0esY8GV9hEmK_TnRM7y@mail.gmail.com>

On Sat, Jun 19, 2010 at 12:55 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> MyungJoo Ham wrote:
>>
>> On Fri, Jun 18, 2010 at 6:50 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>> > MyungJoo Ham wrote:
>> >>
>> >> The clock source controls (struct clksrc_clk) have been often accessing
>> >> CLK_GATE_IPx, which are for clock gating and are accessed by each clock
>> >> as well as the clock source. This duplicated clock issue may incur
>> >> lockup problems when there are two modules accessing the same clock with
>> >> different names.
>> >>
>> > Could you please explain further about the above the statement " accessed by
>> > each clock as well as the clock source"
>>
>> For example, "CLK_GATE_IP2[16:19]" is accessed by "hsmmc" of struct
>> clk (a clock) and "sclk_mmc" of struct clksrc_clk's struct clk (a
>> clock source's clk representation).
>>
>> >
>> >> Besides, the clock source control is supposed to control (setting values
>> >> of MASK, SRC, DIV), not to turn on/off individual clock.
>> >>
>> > That is not quite true. Only S5PV210/S5PC110 have the gate for the clock mux.
>> > S5P6440 and S5PC100, for instance, do not have a gate for the output for
>> > _just_ the clock mux. And the reason why the Clock Mux Gate is provide for
>> > the mux is explained in Section 3.4 of the user manual.
>>
>> In cases where clock mux gating is not available and we have each
>> clock (supplied by this cluck mux) defined separatedly with .enable
>> and .ctrlbit, we'd better omit .enable/.ctrlbit from struct
>> clksrc_clk's struct clk.
>>
>> >
>> >> Another point is that there are registers (CLK_SRC_MASK0/1) specialized
>> >> for masking clock source control in S5PV210/S5PC110 according to the
>> >> user manual (rev 20100201).
>> >>
>> >> Therefore, accessing CLK_SRC_MASK0/1 (rather than accessing
>> >> CLK_GATE_IPx) for the clock source control is safer and fits to the
>> >> semantics of S5PV210/S5PC110 registers. And fortuneatly, each clock
>> >> source defined in clock.c has corresponding bit at CLK_SRC_MASK0/1
>> >> except for MFC, G2D, and G3D.
>> >>
>> > Can you please explain how the use CLK_SRC_MASKx makes it safer. The reason
>> > why MFC, G2D and G3D do not have a corresponding bit in CLK_SRC_MASKx is
>> > mentioned in Section 3.4 of the user manual.
>> >
>> > Let me know your opinion.
>> >
>>
>> It's "EXCEPT FOR MFC, G2D, G3D". I'm not saying that using
>> CLK_SRC_MASKx is safer for these three. For other cases, I guess the
>> lock up example should be fine.
>>
>> However, in most cases, this lockup issue does not make visible problem because:
>> 1. normally, drivers use both clksrc_clk's clk and clk at the same
>> time. for example
>> "mmc_bus".clk_enable;
>> "hsmmc".clk_enable;
>> ?blahblah
>> "hsmmc".clk_disable;
>> "mmc_bus".clk_disable;
>> or
>> 2. drivers sharing the same clock uses only one side of the two.
>> or
>> 3. the execution block between clk_enable and clk_disable is extremely short.
>>
>> Nevertheless, this potential lockup issue is critical and we'd better
>> address it.
>>
>>
>> >> In this patch,
>> >>
>> >> - DAC, HDMI, AUDIO 0/1/2, UCLK(uart) 0/1/2/3, MIXER, FIMC 0/1/2,
>> >> FIMC, MMC 0/1/2/3, CSIS, SPI 0/1, PWI, and PWM clock sources are
>> >> modified to use CLK_SRC_MASK0/1, which were using CLK_GATE_IPx.
>> >>
>> >> - CAM 0/1 did not have enable/disable control. They now access
>> >> ? CLK_SRC_MASK0.
>> >>
>> >> - MFC, G3D, G2D were using CLK_GATE_IPx. However, as there are no clocks
>> >> ? defined to control MFC, G3D, and G2D, we kept them to access
>> >> CLK_GATE_IPx. These may need to be modified (erase .enable, .ctrlbit
>> >> from sclk_mfc, sclk_g2d, sclk_g3d and create clocks: g3d, g2d, mfc)
>> >> later.
>> >>
>> >> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
>> >> ---
>> >> ?arch/arm/mach-s5pv210/clock.c | ?101
>> > ++++++++++++++++++++++-------------------
>> >> ?1 files changed, 55 insertions(+), 46 deletions(-)
>> >>
>> >> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
>> >> index ec5ad8c..08c1063 100644
>> >> --- a/arch/arm/mach-s5pv210/clock.c
>> >> +++ b/arch/arm/mach-s5pv210/clock.c
>> >
>> > (snip)
>> >
>> > --
>
> Strictly speaking, 'duplicated clock problem' and 'clock gating issue which is controlled by CLK_GATE_IPx or CLK_SRC_MASKx' are different problem.
> But mixed above two things in your patch.
>
> I think just need bug fix.
>
> See below mmc case.
>
> Following is for clock gating mmc IP by using CLK_GATE_IPx and can control(clock gating) clocks, 'aclk_hsmmcX' and 'sclk_mmcX' in the mmc IP.
>
> ? ? ? ?{
> ? ? ? ? ? ? ? ?.name ? = "hsmmc",
> ? ? ? ? ? ? ? ?.id ? ? = 0,
> ? ? ? ? ? ? ? ?.parent = &clk_hclk_psys.clk,
> ? ? ? ? ? ? ? ?.enable = s5pv210_clk_ip2_ctrl,
> ? ? ? ? ? ? ? ?.ctrlbit ? ? ? ?= (1<<16),
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.name ? = "hsmmc",
> ? ? ? ? ? ? ? ?.id ? ? = 1,
> ? ? ? ? ? ? ? ?.parent = &clk_hclk_psys.clk,
> ? ? ? ? ? ? ? ?.enable = s5pv210_clk_ip2_ctrl,
> ? ? ? ? ? ? ? ?.ctrlbit ? ? ? ?= (1<<17),
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.name ? = "hsmmc",
> ? ? ? ? ? ? ? ?.id ? ? = 2,
> ? ? ? ? ? ? ? ?.parent = &clk_hclk_psys.clk,
> ? ? ? ? ? ? ? ?.enable = s5pv210_clk_ip2_ctrl,
> ? ? ? ? ? ? ? ?.ctrlbit ? ? ? ?= (1<<18),
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.name ? = "hsmmc",
> ? ? ? ? ? ? ? ?.id ? ? = 3,
> ? ? ? ? ? ? ? ?.parent = &clk_hclk_psys.clk,
> ? ? ? ? ? ? ? ?.enable = s5pv210_clk_ip2_ctrl,
> ? ? ? ? ? ? ? ?.ctrlbit ? ? ? ?= (1<<19),
> ? ? ? ?}...
>
> And following is for clock gating just 'sclk_mmcX' by using CLK_SRC_MASKx.
> But as you know should be 's5pv210_clk_mask0_ctrl' instead of 's5pv210_clk_ip2_ctrl' like below.

Right, that's the patch of Mr. Ham. Inn case of clksrc_clk use the
mask_ctrl instead of ip_ctrl.
The original codes use it by mix-up. his patch addresses it.

Thank you,
Kyungmin Park

>
> @@ -794,8 +794,8 @@ static struct clksrc_clk clksrcs[] = {
> ? ? ? ? ? ? ? ?.clk ? ? ? ? ? ?= {
> ? ? ? ? ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "sclk_mmc",
> ? ? ? ? ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 0,
> - ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip2_ctrl,
> - ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 16),
> + ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
> + ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 8),
> ? ? ? ? ? ? ? ?},
> ? ? ? ? ? ? ? ?.sources = &clkset_group2,
> ? ? ? ? ? ? ? ?.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
> @@ -804,8 +804,8 @@ static struct clksrc_clk clksrcs[] = {
> ? ? ? ? ? ? ? ?.clk ? ? ? ? ? ?= {
> ? ? ? ? ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "sclk_mmc",
> ? ? ? ? ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 1,
> - ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip2_ctrl,
> - ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 17),
> + ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
> + ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 9),
> ? ? ? ? ? ? ? ?},
> ? ? ? ? ? ? ? ?.sources = &clkset_group2,
> ? ? ? ? ? ? ? ?.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
> @@ -814,8 +814,8 @@ static struct clksrc_clk clksrcs[] = {
> ? ? ? ? ? ? ? ?.clk ? ? ? ? ? ?= {
> ? ? ? ? ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "sclk_mmc",
> ? ? ? ? ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 2,
> - ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip2_ctrl,
> - ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 18),
> + ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
> + ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 10),
> ? ? ? ? ? ? ? ?},
> ? ? ? ? ? ? ? ?.sources = &clkset_group2,
> ? ? ? ? ? ? ? ?.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
> @@ -824,8 +824,8 @@ static struct clksrc_clk clksrcs[] = {
> ? ? ? ? ? ? ? ?.clk ? ? ? ? ? ?= {
> ? ? ? ? ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "sclk_mmc",
> ? ? ? ? ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 3,
> - ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip2_ctrl,
> - ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 19),
> + ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
> + ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 11),
> ? ? ? ? ? ? ? ?},
> ? ? ? ? ? ? ? ?.sources = &clkset_group2,
> ? ? ? ? ? ? ? ?.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }
>
>
> I think there is no lockup issue(problem) after bug fix about 'sclk_xxx'.
> Of course, carefully used distinguished clock gating in the relevant device driver.
> Because as I said, CLK_GATE_IPx can disable all of the clock operation of each IP.
> If no need CLK_GATE_IPx, just do clock gating each 'sclk_xxx'.
>
> Could you please re-submit new stuff for bug fix?
>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>


From kmpark at infradead.org  Sat Jun 19 00:22:05 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Sat, 19 Jun 2010 13:22:05 +0900
Subject: [PATCH] Remove unused serial flags
Message-ID: <20100619042205.GA24864@july>

From: Kyungmin Park <kyungmin.park at samsung.com>

Remove unused serial flags. Only s5p series.
After remove s3c series then remove s3c240_uartcfg flags field.

Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index af22f82..1698d03 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -60,28 +60,24 @@
 static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = S5PC100_UCON_DEFAULT,
 		.ulcon	     = S5PC100_ULCON_DEFAULT,
 		.ufcon	     = S5PC100_UFCON_DEFAULT,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = S5PC100_UCON_DEFAULT,
 		.ulcon	     = S5PC100_ULCON_DEFAULT,
 		.ufcon	     = S5PC100_UFCON_DEFAULT,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = S5PC100_UCON_DEFAULT,
 		.ulcon	     = S5PC100_ULCON_DEFAULT,
 		.ufcon	     = S5PC100_UFCON_DEFAULT,
 	},
 	[3] = {
 		.hwport	     = 3,
-		.flags	     = 0,
 		.ucon	     = S5PC100_UCON_DEFAULT,
 		.ulcon	     = S5PC100_ULCON_DEFAULT,
 		.ufcon	     = S5PC100_UFCON_DEFAULT,
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 10bc76e..37a62dd 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -46,28 +46,24 @@
 static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport		= 0,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[1] = {
 		.hwport		= 1,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[2] = {
 		.hwport		= 2,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[3] = {
 		.hwport		= 3,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 4863b13..b0e54ea 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -43,28 +43,24 @@
 static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport		= 0,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[1] = {
 		.hwport		= 1,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[2] = {
 		.hwport		= 2,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[3] = {
 		.hwport		= 3,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 4c8903c..1410a5f 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -43,28 +43,24 @@
 static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport		= 0,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[1] = {
 		.hwport		= 1,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[2] = {
 		.hwport		= 2,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[3] = {
 		.hwport		= 3,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 0d46279..e0d72fc 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -45,28 +45,24 @@
 static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport		= 0,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[1] = {
 		.hwport		= 1,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[2] = {
 		.hwport		= 2,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[3] = {
 		.hwport		= 3,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,


From david-b at pacbell.net  Sat Jun 19 02:21:55 2010
From: david-b at pacbell.net (David Brownell)
Date: Fri, 18 Jun 2010 23:21:55 -0700 (PDT)
Subject: gpiolib and sleeping gpios
In-Reply-To: <4C1BECC9.7000805@bluewatersys.com>
Message-ID: <386783.17931.qm@web180310.mail.gq1.yahoo.com>


> 
> The runtime warnings will only show instances where the
> non-sleeping
> versions where called instead of the sleeping versions.

... *AND* the GPIO requires the cansleep() version...

Right; such calls are errors.  We issue
warnings since fault returns are inapplicable. 

> There is no
> warning to say that we are calling the spinlock safe
> version, where it is possible to sleep.

The call context isn't what controls whether
gpio_get_value() or gpio_get_value_cansleep()
is appropriate ... it's the GPIO itself, and
how its implementation works.

"possible to sleep" is a GPIO attribute,
exposed by a predicate.  If spinlock-safe
calls are used on GPIOs with that attribute,
 a warning *IS* issued.




> 
> The point I was trying to make is that there are lots of
> drivers which
> will not work with gpios on sleeping io expanders because
> they call the
> spinlock safe gpio calls.

And they will trigger runtime warnings, and
thus eventually get fixed.  The way to do that
is to check if the GPIO needs the cansleep()
call


That's the first category above:  the driver
should have used the cansleep() variant, and
sotriggers a runtime warning.





From redhatter at gentoo.org  Sat Jun 19 05:49:08 2010
From: redhatter at gentoo.org (Stuart Longland)
Date: Sat, 19 Jun 2010 19:49:08 +1000
Subject: [alsa-devel] [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
In-Reply-To: <20100619011221.GC2463@opensource.wolfsonmicro.com>
References: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
	<1276899876-19001-1-git-send-email-redhatter@gentoo.org>
	<20100619011221.GC2463@opensource.wolfsonmicro.com>
Message-ID: <20100619094908.GD30868@www.longlandclan.yi.org>

On Sat, Jun 19, 2010 at 02:12:21AM +0100, Mark Brown wrote:
> On Sat, Jun 19, 2010 at 08:24:36AM +1000, Stuart Longland wrote:
> 
> This all looks pretty good, the comments below are fairly minor.
> 
> > +	/* AVDD <->DVDD Link enable */
> > +	u8	avdd_link_en;
> 
> What's this?  It looks like a boolean which makes u8 an odd choice.
> 
> > +	/* LDO Enable */
> > +	u8	ldo_en;
> 
> Similarly here.

Well, I didn't see the point in allocating 32-bits when I'd only be
using 1 of them.  However, I can change it to an int if need be.  I'm
not certain that C has a true "bool" type, but I could be wrong.

> > +
> > +	/* Oversampling rate (both ADC and DAC) */
> > +	u8	osr;
> 
> Why is this platform data rather than a runtime configurable option?

How would the application elect a particular oversampling rate?  I'll
admit I'm very new to the ALSA framework in general, but I didn't
realise there was an oversampling rate setting.  I'll have a look at how
the other drivers do it.

> > +config SND_SOC_TLV320AIC3204
> > +	tristate
> > +	depends on I2C
> > +
> 
> Drop the depends, it doesn't actually do anything for selected items.
> 
> > +	/* Page 1 */
> > +	if (page == 1) {
> > +		if (reg <= 4)
> > +			return 1;
> 
> I can't help but think that this'd be more legible with switch ()
> statements (GCC has an extension for ranges in switch statements which
> you could use).

I did if statements here for two reasons:

(1) Range selection (I was unaware of the GCC extension)
(2) I found by experiment that if is slighly more efficient than
	switch... at least that was the case on MSP430 (using mspgcc).
	Other platforms could be very different.

> > +/*
> > + * Pretty-print the value of a register
> > + */
> > +static int aic3204_show_reg(struct snd_soc_codec *codec, char *buf,
> > +		int buf_sz, unsigned int reg)
> > +{
> > +	return snprintf(buf, buf_sz, "%02x",
> > +			aic3204_read_reg_cache(codec, reg));
> > +}
> 
> This looks suspiciously close to the standard show_reg() - it seems
> wrong that you should need it.

Well, the main difference; standard show_reg uses %4x as its format; and
therefore wastes two characters printing nothing useful.  Given space is
already tight for displaying register dumps via debugfs, any little bit
helps. :-)

Certainly there's no explicit reason why it is necessary and it can go.

> > +	/*
> > +	 * These registers are not manipulated by us, so we must read them from
> > +	 * the CODEC directly.
> > +	 */
> 
> Hrm?  Also, it strikes me that this code is also used in the WCLK
> function and might benefit from being factored out - it's moderately
> verbose.

The ADC flags register (and the DAC flags registers) are read-only and
manipulated by the CODEC when the ADCs and DACs are actually powered up.
I could use the flags set elsewhere, but this reflects what *is* the
present state, not what ought to be the present state.

There is common code between the WCLK and BCLK functions; in fact I did
consider making it the one callback, but since they are separate in the
registers, I kept them separate in the callbacks.

> > +static const char *aic3204_micbias_voltages[] = {
> > +	"Low", "Med", "High", "V+"
> > +};
> 
> I'd be inclined to spell medium out and write "V+" as "Supply" or
> similar unless there's a strong reason to do otherwise - it seems more
> legible.

Fair enough... I was originally going to try and use some shortened
version of what's in the datasheet... but the values of "Low", "Medium"
and "High" are dependant on the selected source and the power rails.
"Supply" is probably just as descriptive, if not as compact as "V+"...
I'll update that.

> > +static const char *aic3204_ldac_srcs[] = {
> > +	"disabled", "left channel", "right channel", "mix"
> > +};
> 
> Capital letters are more idiomatic for enumerations.
> 
> > +/*
> > + * DAC digital volumes. From -63.5 to +24 dB in 0.5 dB steps.
> > + * Does not mute control.
> > + */
> 
> I'm finding these comments a little too verbose but that's just me -
> I stop and read them only to find there's nothing odd going on here.

Yeah, some of this is due to the fact that, in the early days, I wasn't
too sure if this was the "right way".  So I figured I'd describe my
intentions, and then if I was doing it wrong, people would at least
know what was intended, and could suggest improvements.

Now that the mixer is working okay, I could cut this down... but also I
hope that others who follow the same path as me, might find this helpful
to determine what's going on.

> > +	/*
> > +	 * Note regarding SOC_DOUBLE_R_SX_TLV...
> > +	 *
> > +	 * This is a bit misleading; xshift refers to the bit one bit *past*
> > +	 * the most significant bit.  Or at least that's what it appears to be
> > +	 * doing the math.  Mask needs to select the last 6 bits; which is the
> > +	 * signed bitfield specifiying the gain in dB.
> > +	 */
> 
> I suspect that fixing the control may break what you're doing here?  It
> would certainly bitrot the comment.

Well, when the problem goes, so can the comment. :-)  One question
though, the shift value derives the mask for further operations on these
registers... if we were to change the shift value so it reflected how
other widget types work, how does one define the mask?

> > +	SOC_SINGLE("Differential Output Switch", AIC3204_DACS2,
> > +			AIC3204_DACS2_RMOD_INV_SHIFT, 1, 0),
> 
> This feels like platform data - the use of differential outputs is
> normally a property of the physical wiring of the board, it's very rare
> to be able to vary this usefully at runtime.

Arguably, so is the DAC audio path routing.  I wasn't sure how to set
this up at the time, initially it was CODEC setup data, then I moved it
into the mixer.

The other consideration here; is the use case where a device with a mono
speaker, but a stereo line-out jack... I wasn't sure how to handle these
features.

> > +	/* MICBIAS Options */
> > +	SOC_SINGLE("MICBIAS Enable", AIC3204_MICBIAS, 6, 0x1, 0),
> 
> MICBIAS Enable should definitely be DAPM.
> 
> > +	SOC_ENUM("MICBIAS Level", aic3204_enum_micbias_voltage),
> > +	SOC_ENUM("MICBIAS Source", aic3204_enum_micbias_src),
> 
> These I would expect to be managed in kernel - they're normally either a
> property of the board or need to be managed in conjunction with jack
> detection code which tends to live in kernel.

I'll look into this... I was aware of the MICBIAS widget, but will have
to do some further research here.  As to the others... I wasn't sure how
they should be handled.

> > +static const struct snd_soc_dapm_widget aic3204_dapm_widgets[] = {
> > +	/* Driver/Amplifier Selection */
> > +	SND_SOC_DAPM_SWITCH("HPL Playback Switch", AIC3204_OUTDRV,
> > +			AIC3204_OUTDRV_HPL_UP_SHIFT, 0,
> > +			&aic3204_hpl_switch),
> > +	SND_SOC_DAPM_SWITCH("HPR Playback Switch", AIC3204_OUTDRV,
> > +			AIC3204_OUTDRV_HPR_UP_SHIFT, 0,
> > +			&aic3204_hpr_switch),
> 
> A lot of these SWITCH controls feel like they ought to be PGAs and the
> switch controls mutes on those.  When muting an output you normally
> don't want to power up and down the path since that is slow and tends to
> trigger audible issues, you'd normally control the power for path
> endpoints and elements that affect routing only.

They are PGAs connecting the driver to its mixer... I wasn't sure how
the PGAs worked in DAPM.  I knew this did work however, the only catch
is that DAPM won't power up the DACs unless you switch them through via
these mixers to one of the output drivers.  I'll have a closer look at
the PGAs and see what they're doing.

> > +	SND_SOC_DAPM_AIF_IN("Left Data In", "Left Playback",
> > +			0, SND_SOC_NOPM, 0, 0),
> > +	SND_SOC_DAPM_AIF_IN("Right Data In", "Right Playback",
> > +			1, SND_SOC_NOPM, 0, 0),
> > +	SND_SOC_DAPM_AIF_OUT("Left Data Out", "Left Capture",
> > +			0, SND_SOC_NOPM, 0, 0),
> > +	SND_SOC_DAPM_AIF_OUT("Right Data Out", "Right Capture",
> > +			1, SND_SOC_NOPM, 0, 0),
> 
> You have these AIF widgets but at least the DAC input selection was
> being done in the regular controls rather than in the DAPM routing.

Indeed, DAC inputs are selectable, the ADC is not.  I should probably
making the DAC inputs a MUX... I'll give this a re-think too.

> > +	/*
> > +	 * Set BCLK and WCLK sources...
> > +	 *
> > +	 * Despite DAPM; this is still needed, as DAPM doesn't yet set the
> > +	 * source at the right time.
> > +	 *
> > +	 * TODO: See if we can change the order of initialisation so this
> > +	 * selection is made after bringing up the ADCs/DACs.  Alternative:
> > +	 * see if we can find out ahead of time which one to use.
> 
> It surprises me that the ordering matters too much here; worst case you
> leave the interface declocked a little longer when you need to switch
> sources but that doesn't seem like the end of the world?

Well, what I found is that if I didn't do it there... it would call the
WCLK and BCLK functions before powering up the DACs/ADCs.  Since they
have no idea whether recording or playback is in progress (I wasn't sure
how to extract this information), the functions rely on the flags
registers to determine this.

Therefore, it only works *after* DAPM has turned on the respective
parts.  Without manually switching it here, the functions see that
neither ADC nor DAC is active, and therefore don't do any switching of
the BCLK and WCLK.  End result; no clocks, DMA times out and the user is
left with deafening silence.

This, is probably one of the biggest areas where the DAPM support in
this CODEC driver needs work.  I tried to follow what was going on in
the other CODEC drivers, and I know what's submitted isn't quite right,
but it does at least work.

> > +	snd_soc_update_bits(codec, AIC3204_AISR3, AIC3204_AISR3_BDIV,
> > +			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
> > +				? AIC3204_AISR3_BDIV_DAC
> > +				: AIC3204_AISR3_BDIV_ADC);
> 
> I have to say that I'm really not a fan of the ternery operator for
> legibility.
>
> > +static int aic3204_mute(struct snd_soc_dai *dai, int mute)
> > +{
> 
> ...
> 
> > +	aic3204_write(codec, AIC3204_DACS2, dacs2);	/* Unmute DAC */
> 
> ...or possibly mute it :)

Yes, obsolete comment I guess. :-)  This is also a mixer control...
which is better... leave it to ASoC core, or the user to control PCM
mute?  The user can mute using the line driver controls... so I guess I
should ditch the "PCM Playback Switch" control.

> > +static int aic3204_resume(struct platform_device *pdev)
> > +{
> > +	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
> > +	struct snd_soc_codec *codec = socdev->card->codec;
> > +	int i;
> > +	u8 data[2];
> > +	u8 *cache = codec->reg_cache;
> > +
> > +	/* Sync reg_cache with the hardware */
> > +	for (i = 0; i < AIC3204_CACHEREGNUM; i++) {
> > +		data[0] = i;
> > +		data[1] = cache[i];
> > +		codec->hw_write(codec->control_data, data, 2);
> 
> Since you've got a register defaults table you could skip rewriting
> registers which have their default value.

Indeed, suspend/resume isn't tested at all, so no idea if it works or
not.  I should probably do a forced reset too just to be on the safe
side.  This is a reminant from the aic3x driver.

> > +	/* LDO enable, analogue blocks enable */
> > +	snd_soc_update_bits(codec, AIC3204_LDO,
> > +			AIC3204_LDO_ANALOG | AIC3204_LDO_AVDD_UP,
> > +			AIC3204_LDO_ANALOG_ENABLED |
> > +			(aic3204->pdata.ldo_en
> > +			  ? AIC3204_LDO_AVDD_UP : 0));
> 
> This looks a bit fishy since the mask covers more bits than can ever be
> enabled - it reads like the other two bits should be unconditionally
> cleared.

Would I be better breaking that statement up into two statements?  I did
them as one for efficiency, but I do recognise there is a potential
readability issue.  Basically, it clears the "analog power-down" bit in
the LDO register (yes, this inverse logic irritates me) and optionally
turns on the LDO.  I figure some users may wish to provide their own
AVDD and thus won't want the LDO.

I wasn't sure about the link between AVDD and DVDD, so I left that
configurable.  I'm guessing most will probably want it disabled.  This
was configured using arbitrary register initialisation scripts, passed
in via the CODEC setup data... so at least things are headded in the
right direction. :-)

Regards,
-- 
Stuart Longland (aka Redhatter, VK4MSL)      .'''.
Gentoo Linux/MIPS Cobalt and Docs Developer  '.'` :
. . . . . . . . . . . . . . . . . . . . . .   .'.'
http://dev.gentoo.org/~redhatter             :.'

I haven't lost my mind...
  ...it's backed up on a tape somewhere.


From broonie at opensource.wolfsonmicro.com  Sat Jun 19 06:57:07 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 19 Jun 2010 11:57:07 +0100
Subject: [alsa-devel] [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
In-Reply-To: <20100619094908.GD30868@www.longlandclan.yi.org>
References: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
	<1276899876-19001-1-git-send-email-redhatter@gentoo.org>
	<20100619011221.GC2463@opensource.wolfsonmicro.com>
	<20100619094908.GD30868@www.longlandclan.yi.org>
Message-ID: <20100619105706.GA2409@opensource.wolfsonmicro.com>

On Sat, Jun 19, 2010 at 07:49:08PM +1000, Stuart Longland wrote:
> On Sat, Jun 19, 2010 at 02:12:21AM +0100, Mark Brown wrote:
> > On Sat, Jun 19, 2010 at 08:24:36AM +1000, Stuart Longland wrote:

> > > +	/* LDO Enable */
> > > +	u8	ldo_en;

> > Similarly here.

> Well, I didn't see the point in allocating 32-bits when I'd only be
> using 1 of them.  However, I can change it to an int if need be.  I'm
> not certain that C has a true "bool" type, but I could be wrong.

C99 introduced a bool type, and there's always been bitfields.  Besides,
you're microoptimising something that doesn't need it.  When you write
u8 that means you really need this field to be unsigned and 8 bits which
is a bit confusing for something that's actually just a flag.

> > > +	/* Oversampling rate (both ADC and DAC) */
> > > +	u8	osr;

> > Why is this platform data rather than a runtime configurable option?

> How would the application elect a particular oversampling rate?  I'll
> admit I'm very new to the ALSA framework in general, but I didn't
> realise there was an oversampling rate setting.  I'll have a look at how
> the other drivers do it.

The oversampling rate selection is a performance/power tradeoff.  The
user may choose to do things like use high performance when listening to
music but step back a bit when playing system sounds, for example.

There's no specific ALSA control for it, just make it a Switch.

> > > +/*
> > > + * Pretty-print the value of a register
> > > + */
> > > +static int aic3204_show_reg(struct snd_soc_codec *codec, char *buf,
> > > +		int buf_sz, unsigned int reg)
> > > +{
> > > +	return snprintf(buf, buf_sz, "%02x",
> > > +			aic3204_read_reg_cache(codec, reg));
> > > +}

> > This looks suspiciously close to the standard show_reg() - it seems
> > wrong that you should need it.

> Well, the main difference; standard show_reg uses %4x as its format; and
> therefore wastes two characters printing nothing useful.  Given space is
> already tight for displaying register dumps via debugfs, any little bit
> helps. :-)

> Certainly there's no explicit reason why it is necessary and it can go.

If you want to do this it'd be better to add support to the core, for
example by keying off a register width supplied by the CODEC.

> > > +	/*
> > > +	 * These registers are not manipulated by us, so we must read them from
> > > +	 * the CODEC directly.
> > > +	 */

> > Hrm?  Also, it strikes me that this code is also used in the WCLK
> > function and might benefit from being factored out - it's moderately
> > verbose.

> The ADC flags register (and the DAC flags registers) are read-only and
> manipulated by the CODEC when the ADCs and DACs are actually powered up.
> I could use the flags set elsewhere, but this reflects what *is* the
> present state, not what ought to be the present state.

This strikes me as something that's going to hit a race condition at
some point - if the two differ I'd hope that the state the driver has
set is going to be the actual CODEC state very soon.

> There is common code between the WCLK and BCLK functions; in fact I did
> consider making it the one callback, but since they are separate in the
> registers, I kept them separate in the callbacks.

I was thinking more a utility function that both callbacks use to work
out which of the DACs and ADCs are powered.

> Now that the mixer is working okay, I could cut this down... but also I
> hope that others who follow the same path as me, might find this helpful
> to determine what's going on.

If we're going to do that we'd need to be doing it for every single TLV
control in every single driver...

> Well, when the problem goes, so can the comment. :-)  One question
> though, the shift value derives the mask for further operations on these
> registers... if we were to change the shift value so it reflected how
> other widget types work, how does one define the mask?

I'd intuitively expect it to be relative to the start of the controlled
data rather than the start of the register.

> > > +	SOC_SINGLE("Differential Output Switch", AIC3204_DACS2,
> > > +			AIC3204_DACS2_RMOD_INV_SHIFT, 1, 0),

> > This feels like platform data - the use of differential outputs is
> > normally a property of the physical wiring of the board, it's very rare
> > to be able to vary this usefully at runtime.

> Arguably, so is the DAC audio path routing.  I wasn't sure how to set
> this up at the time, initially it was CODEC setup data, then I moved it
> into the mixer.

The DAC routing can be usefully varied at runtime depending on the use
case - for example, sometimes people choose to route a mono signal into
both DACs to give stereo output.  It would be very unusual hardware that 
provided a way of switching between single ended and differential in a
similar fashion.

> The other consideration here; is the use case where a device with a mono
> speaker, but a stereo line-out jack... I wasn't sure how to handle these
> features.

Presumably you can make individual outputs differential and single ended
then?

> > > +	SOC_ENUM("MICBIAS Level", aic3204_enum_micbias_voltage),
> > > +	SOC_ENUM("MICBIAS Source", aic3204_enum_micbias_src),

> > These I would expect to be managed in kernel - they're normally either a
> > property of the board or need to be managed in conjunction with jack
> > detection code which tends to live in kernel.

> I'll look into this... I was aware of the MICBIAS widget, but will have
> to do some further research here.  As to the others... I wasn't sure how
> they should be handled.

Platform data initially then provide a runtime API for machine drivers
if requireed.

> > > +static const struct snd_soc_dapm_widget aic3204_dapm_widgets[] = {
> > > +	/* Driver/Amplifier Selection */
> > > +	SND_SOC_DAPM_SWITCH("HPL Playback Switch", AIC3204_OUTDRV,
> > > +			AIC3204_OUTDRV_HPL_UP_SHIFT, 0,
> > > +			&aic3204_hpl_switch),
> > > +	SND_SOC_DAPM_SWITCH("HPR Playback Switch", AIC3204_OUTDRV,
> > > +			AIC3204_OUTDRV_HPR_UP_SHIFT, 0,
> > > +			&aic3204_hpr_switch),

> > A lot of these SWITCH controls feel like they ought to be PGAs and the
> > switch controls mutes on those.  When muting an output you normally
> > don't want to power up and down the path since that is slow and tends to
> > trigger audible issues, you'd normally control the power for path
> > endpoints and elements that affect routing only.

> They are PGAs connecting the driver to its mixer... I wasn't sure how
> the PGAs worked in DAPM.  I knew this did work however, the only catch

These should definitely be PGA widgets as described above.

> is that DAPM won't power up the DACs unless you switch them through via
> these mixers to one of the output drivers.  I'll have a closer look at
> the PGAs and see what they're doing.

Not powering up the DACs unless there is a connected output path is the
expected behaviour.

> > It surprises me that the ordering matters too much here; worst case you
> > leave the interface declocked a little longer when you need to switch
> > sources but that doesn't seem like the end of the world?

> Well, what I found is that if I didn't do it there... it would call the
> WCLK and BCLK functions before powering up the DACs/ADCs.  Since they
> have no idea whether recording or playback is in progress (I wasn't sure
> how to extract this information), the functions rely on the flags
> registers to determine this.

If you track this in the audio path setup/teardown path instead of
looking at the DAC power status you should find everything works fine.

> > > +static int aic3204_mute(struct snd_soc_dai *dai, int mute)
> > > +{

> > ...

> > > +	aic3204_write(codec, AIC3204_DACS2, dacs2);	/* Unmute DAC */

> > ...or possibly mute it :)

> Yes, obsolete comment I guess. :-)  This is also a mixer control...
> which is better... leave it to ASoC core, or the user to control PCM
> mute?  The user can mute using the line driver controls... so I guess I
> should ditch the "PCM Playback Switch" control.

Remove the mixer control.  The automatic management ensures that no
noise that is generated when starting up the audio stream propagates
into the output path and that any soft unmute support in the CODEC gets
used to stop you having a hard power up with an active signal.

> > > +	for (i = 0; i < AIC3204_CACHEREGNUM; i++) {
> > > +		data[0] = i;
> > > +		data[1] = cache[i];
> > > +		codec->hw_write(codec->control_data, data, 2);

> > Since you've got a register defaults table you could skip rewriting
> > registers which have their default value.

> Indeed, suspend/resume isn't tested at all, so no idea if it works or
> not.  I should probably do a forced reset too just to be on the safe
> side.  This is a reminant from the aic3x driver.

The reset should not be required, either the device will be as you left
it or the power will have gone so it will be in the reset state anyway.

> > > +	/* LDO enable, analogue blocks enable */
> > > +	snd_soc_update_bits(codec, AIC3204_LDO,
> > > +			AIC3204_LDO_ANALOG | AIC3204_LDO_AVDD_UP,
> > > +			AIC3204_LDO_ANALOG_ENABLED |
> > > +			(aic3204->pdata.ldo_en
> > > +			  ? AIC3204_LDO_AVDD_UP : 0));

> > This looks a bit fishy since the mask covers more bits than can ever be
> > enabled - it reads like the other two bits should be unconditionally
> > cleared.

> Would I be better breaking that statement up into two statements?  I did

Yes, it would be much more legible.

> I wasn't sure about the link between AVDD and DVDD, so I left that
> configurable.  I'm guessing most will probably want it disabled.  This
> was configured using arbitrary register initialisation scripts, passed
> in via the CODEC setup data... so at least things are headded in the
> right direction. :-)

What does this register actually do?  Does it describe the hardware
configuration to the device?


From tbm at cyrius.com  Sat Jun 19 10:06:29 2010
From: tbm at cyrius.com (Martin Michlmayr)
Date: Sat, 19 Jun 2010 15:06:29 +0100
Subject: [PATCH] orion/kirkwood: reset PCIe unit on boot
In-Reply-To: <1276029158-22159-1-git-send-email-razzor@kopf-tisch.de>
References: <1276029158-22159-1-git-send-email-razzor@kopf-tisch.de>
Message-ID: <20100619140628.GP1573@jirafa.cyrius.com>

* Olaf Rempel <razzor at kopf-tisch.de> [2010-06-08 22:32]:
> Patch found in QNAPs vendor source package, with some cleanups
> (proper defines, shortened max. timeout from 1s to 200ms).
> 
> Without this patch the PCIe SATA controller (Marvell 88sx7042/sata_mv)
> in my QNAP TS-419P (Marvell 88f6281/Kirkwood) stops working after a
> few minutes.
> The symptomes are described in this thread:
> http://marc.info/?l=linux-ide&m=124822863706181&w=2

Nico, Saeed: do you have any comments on this patch?

A number of Debian users ran into this issue so I'm glad Olaf found a
solution.


> ---
>  arch/arm/plat-orion/pcie.c |   34 ++++++++++++++++++++++++++++++++++
>  1 files changed, 34 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
> index 54c84a4..779553a 100644
> --- a/arch/arm/plat-orion/pcie.c
> +++ b/arch/arm/plat-orion/pcie.c
> @@ -13,6 +13,7 @@
>  #include <linux/mbus.h>
>  #include <asm/mach/pci.h>
>  #include <plat/pcie.h>
> +#include <linux/delay.h>
>  
>  /*
>   * PCIe unit register offsets.
> @@ -46,6 +47,8 @@
>  #define  PCIE_STAT_BUS_OFFS		8
>  #define  PCIE_STAT_BUS_MASK		0xff
>  #define  PCIE_STAT_LINK_DOWN		1
> +#define PCIE_DEBUG_CTRL         0x1a60
> +#define  PCIE_DEBUG_SOFT_RESET		(1<<20)
>  
>  
>  u32 __init orion_pcie_dev_id(void __iomem *base)
> @@ -85,6 +88,32 @@ void __init orion_pcie_set_local_bus_nr(void __iomem *base, int nr)
>  	writel(stat, base + PCIE_STAT_OFF);
>  }
>  
> +void __init orion_pcie_reset(void __iomem *base)
> +{
> +	u32 reg;
> +	int i;
> +
> +	/*
> +	 * MV-S104860-U0, Rev. C:
> +	 * PCI Express Unit Soft Reset
> +	 * When set, generates an internal reset in the PCI Express unit.
> +	 * This bit should be cleared after the link is re-established.
> +	 */
> +	reg = readl(base + PCIE_DEBUG_CTRL);
> +	reg |= PCIE_DEBUG_SOFT_RESET;
> +	writel(reg, base + PCIE_DEBUG_CTRL);
> +
> +	for (i = 0; i < 20; i++) {
> +		mdelay(10);
> +
> +		if (orion_pcie_link_up(base))
> +			break;
> +	}
> +
> +	reg &= ~(PCIE_DEBUG_SOFT_RESET);
> +	writel(reg, base + PCIE_DEBUG_CTRL);
> +}
> +
>  /*
>   * Setup PCIE BARs and Address Decode Wins:
>   * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
> @@ -153,6 +182,11 @@ void __init orion_pcie_setup(void __iomem *base,
>  	u32 mask;
>  
>  	/*
> +	 * soft reset PCIe unit
> +	 */
> +	orion_pcie_reset(base);
> +
> +	/*
>  	 * Point PCIe unit MBUS decode windows to DRAM space.
>  	 */
>  	orion_pcie_setup_wins(base, dram);
> -- 
> 1.6.3.3

-- 
Martin Michlmayr
http://www.cyrius.com/


From g.liakhovetski at gmx.de  Sat Jun 19 10:13:31 2010
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Sat, 19 Jun 2010 16:13:31 +0200 (CEST)
Subject: [PATCH v3 1/3] mx2_camera: Add soc_camera support for
	i.MX25/i.MX27
In-Reply-To: <190248f3b311ccfcb73f1fc71d185e3927f0bf05.1274865040.git.baruch@tkos.co.il>
References: <cover.1274865040.git.baruch@tkos.co.il>
	<190248f3b311ccfcb73f1fc71d185e3927f0bf05.1274865040.git.baruch@tkos.co.il>
Message-ID: <Pine.LNX.4.64.1006191458420.11313@axis700.grange>

Hi Baruch

On Wed, 26 May 2010, Baruch Siach wrote:

> This is the soc_camera support developed by Sascha Hauer for the i.MX27.  Alan
> Carvalho de Assis modified the original driver to get it working on more recent
> kernels. I modified it further to add support for i.MX25. This driver has been
> tested on i.MX25 and i.MX27 based platforms.

I hoped, this would be the final version, but if I'm not mistaken, you've 
introduced an error, which we better fix before committing. And as we 
anyway will likely need a v4, I'll also ask you to improve a couple of 
stylistic issues, which otherwise I'd just fix myself with your 
permission.

> Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> ---
>  arch/arm/plat-mxc/include/mach/memory.h  |    4 +-
>  arch/arm/plat-mxc/include/mach/mx2_cam.h |   46 +
>  drivers/media/video/Kconfig              |   13 +
>  drivers/media/video/Makefile             |    1 +
>  drivers/media/video/mx2_camera.c         | 1488 ++++++++++++++++++++++++++++++
>  5 files changed, 1550 insertions(+), 2 deletions(-)
>  create mode 100644 arch/arm/plat-mxc/include/mach/mx2_cam.h
>  create mode 100644 drivers/media/video/mx2_camera.c
> 
> diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
> index c4b40c3..5803836 100644
> --- a/arch/arm/plat-mxc/include/mach/memory.h
> +++ b/arch/arm/plat-mxc/include/mach/memory.h

[snip]

> +static void mx2_videobuf_queue(struct videobuf_queue *vq,
> +			       struct videobuf_buffer *vb)
> +{
> +	struct soc_camera_device *icd = vq->priv_data;
> +	struct soc_camera_host *ici =
> +		to_soc_camera_host(icd->dev.parent);
> +	struct mx2_camera_dev *pcdev = ici->priv;
> +	struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
> +	unsigned long flags;
> +	int ret;
> +
> +	dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
> +		vb, vb->baddr, vb->bsize);
> +
> +	spin_lock_irqsave(&pcdev->lock, flags);
> +
> +	vb->state = VIDEOBUF_QUEUED;
> +	list_add_tail(&vb->queue, &pcdev->capture);
> +
> +	if (mx27_camera_emma(pcdev))
> +		goto out;
> +	else if (cpu_is_mx27()) {

One of the minor ones - please, add braces in the "if" case.

[snip]

> +static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
> +{
> +	struct mx2_camera_dev *pcdev = data;
> +	unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
> +	struct mx2_buffer *buf;
> +
> +	if ((status & (3 << 5)) == (3 << 5)
> +			&& !list_empty(&pcdev->active_bufs)) {
> +		/*
> +		 * Both buffers have triggered, process the one we're expecting
> +		 * to first
> +		 */
> +		buf = list_entry(pcdev->active_bufs.next,
> +			struct mx2_buffer, vb.queue);
> +		mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE);
> +	}
> +	if (status & (1 << 6))
> +		mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE);
> +	if (status & (1 << 5))
> +		mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE);

Now, this is the important one. In my review of v2 I proposed the above 
fix for the both-bits-set case. But, I think, your implementation is not 
correct. Don't you have to clear the expected buffer number, so that you 
don't process it twice? Something like

		status &= ~(1 << 6 - buf->bufnum);

anywhere inside the first of the three ifs?

> +	if (status & (1 << 7)) {

Bit 7 is overflow. A correct handling could be resetting the buffer, 
returning an error frame and continuing with the next one. However, I 
understand, that you do not have a chance to implement this properly 
now. So, please, at least add a "FIXME" comment, explaining, what should 
be done here. Besides, error states are normally checked before normal 
data processing. So, either mention this in the comment too, or move this 
above the buffer completion processing.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From buytenh at wantstofly.org  Sat Jun 19 10:23:22 2010
From: buytenh at wantstofly.org (Lennert Buytenhek)
Date: Sat, 19 Jun 2010 16:23:22 +0200
Subject: [PATCH] orion/kirkwood: reset PCIe unit on boot
In-Reply-To: <20100619140628.GP1573@jirafa.cyrius.com>
References: <1276029158-22159-1-git-send-email-razzor@kopf-tisch.de>
	<20100619140628.GP1573@jirafa.cyrius.com>
Message-ID: <20100619142322.GO14513@mail.wantstofly.org>

On Sat, Jun 19, 2010 at 03:06:29PM +0100, Martin Michlmayr wrote:

> > Patch found in QNAPs vendor source package, with some cleanups
> > (proper defines, shortened max. timeout from 1s to 200ms).
> > 
> > Without this patch the PCIe SATA controller (Marvell 88sx7042/sata_mv)
> > in my QNAP TS-419P (Marvell 88f6281/Kirkwood) stops working after a
> > few minutes.
> > The symptomes are described in this thread:
> > http://marc.info/?l=linux-ide&m=124822863706181&w=2
> 
> Nico, Saeed: do you have any comments on this patch?
> 
> A number of Debian users ran into this issue so I'm glad Olaf found a
> solution.

I'm not very happy with it, as (as far as I understand) even though
it might solve the problem, so far it's unclear why exactly it does so.

And consequently, e.g. whether it's needed on other SoCs as well.


From mfuzzey at gmail.com  Sat Jun 19 11:48:08 2010
From: mfuzzey at gmail.com (Martin Fuzzey)
Date: Sat, 19 Jun 2010 17:48:08 +0200
Subject: [PATCH] imxfb: add flag to avoid disabling clk multiple times
In-Reply-To: <1275561288-20661-1-git-send-email-l.fu@pengutronix.de>
References: <1275561288-20661-1-git-send-email-l.fu@pengutronix.de>
Message-ID: <4C1CE6B8.4090504@gmail.com>

Hi Luotao,

Luotao Fu wrote:
> while the imxfb driver blanks the screen. The clock supply to the framebuffer
> controller is disabled. The same callback to disable the fb is, however, also
> used the remove and shutdown hooks of the imxfb platform driver. This means that
> the imxfb driver can run into a WARN in clock_disable while unloading or
> rebooting, if the screen is blanked previously, since the same clock will be
> than eventually disabled multiple times.  This patch adds a flag to make sure
> that the clock will only be disabled, if it was not already disabled before.
>
>   
Actually it's worse than that - you don't need to unload the
driver or reboot to run into this problem because imxfb_blank()
calls imxfb_disable_controller() for cases
    case FB_BLANK_POWERDOWN:
    case FB_BLANK_VSYNC_SUSPEND:
    case FB_BLANK_HSYNC_SUSPEND:
    case FB_BLANK_NORMAL:

Often an X server will call these after successive timeouts
(eg Normal, Suspend, Powerdown) so you can get into the
multiple suspend problem you describe just by waiting long
enough for at least two blank levels to be activated.

Furthermore once this happens, not only does a WARN occur
in clock_disable but the clock usage counter will actually become
negative so it will require multiple wake up requests to switch
the display back on.

I was just about to post a patch for this but I see you beat
me to it :).

Your patch fixes the clock_disable problem but fbi->backlight_power()
and fbi->lcd_power() can still be called multiple times.
Not sure if that is really a problem - they should be idempotent.

I did it by making all of imxfb_disable_controller() do nothing if the
disable was already done like this  (just for illustration not submission,
lines may be mangled):


--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -175,6 +175,7 @@ struct imxfb_info {
 
        struct imx_fb_videomode *mode;
        int                     num_modes;
+       int                     enabled;
 
        void (*lcd_power)(int);
        void (*backlight_power)(int);
@@ -451,6 +452,9 @@ static int imxfb_set_par(struct fb_info *info)
 
 static void imxfb_enable_controller(struct imxfb_info *fbi)
 {
+       if (fbi->enabled)
+               return;
+
        pr_debug("Enabling LCD controller\n");
 
        writel(fbi->screen_dma, fbi->regs + LCDC_SSA);
@@ -470,10 +474,13 @@ static void imxfb_enable_controller(struct
imxfb_info *fbi)
                fbi->backlight_power(1);
        if (fbi->lcd_power)
                fbi->lcd_power(1);
+       fbi->enabled = 1;
 }
 
 static void imxfb_disable_controller(struct imxfb_info *fbi)
 {
+       if (!fbi->enabled)
+               return;
        pr_debug("Disabling LCD controller\n");
 
        if (fbi->backlight_power)
@@ -484,6 +491,7 @@ static void imxfb_disable_controller(struct
imxfb_info *fbi)
        clk_disable(fbi->clk);
 
        writel(0, fbi->regs + LCDC_RMCR);
+       fbi->enabled = 0;
 }
 
 static int imxfb_blank(int blank, struct fb_info *info)


Though this does miss the explicit  clk_disable() in imxfb_remove()


Cheers,

Martin




From john.ogness at linutronix.de  Sat Jun 19 16:25:25 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Sat, 19 Jun 2010 22:25:25 +0200
Subject: [PATCH 4/5] mtd: mxc_nand fixups
In-Reply-To: <20100618205401.GA12115@pengutronix.de> (Sascha Hauer's message
	of "Fri, 18 Jun 2010 22:54:01 +0200")
References: <804oh0b7gx.fsf@merkur.tec.linutronix.de>
	<20100618205401.GA12115@pengutronix.de>
Message-ID: <80sk4ivkga.fsf@merkur.tec.linutronix.de>

On 2010-06-18, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>> This patch reverts the driver to enabling/disabling the NFC interrupt
>> mask rather than enabling/disabling the system interrupt. This cleans
>> up the driver so that it doesn't rely on interrupts being disabled
>> within the interrupt handler.
>
> This behaviour was introduced in
> a47bfd2eb66837653dc3b42541dfe4283dd41251 mxc_nand: support i.MX21
>
> I guess this won't work on i.MX21.

I just downloaded the i.MX21 reference manual and its NFC interrupts can
also be masked with INT_MASK (bit 4) of NFC_Flash_Config1 (0xdf003e1a).

IMHO we should revert the driver to masking the NFC interrupts. The
current linux-next version with nosync irq disabling within the
interrupt handler is a bit silly. Especially since the interrupt handler
does nothing except signal a wait queue.

John Ogness


From jy0922.shim at samsung.com  Sat Jun 19 21:13:54 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Sun, 20 Jun 2010 10:13:54 +0900
Subject: [PATCH] ARM: SAMSUNG: Remove flags of struct s3c2410_uartcfg
Message-ID: <1276996434-32606-1-git-send-email-jy0922.shim@samsung.com>

The flags of struct s3c2410_uartcfg is assigned to 0 to the all samsung
arch machines and it isn't used by samsung uart driver.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s3c2410/mach-amlm5900.c            |    3 ---
 arch/arm/mach-s3c2410/mach-bast.c                |    3 ---
 arch/arm/mach-s3c2410/mach-h1940.c               |    3 ---
 arch/arm/mach-s3c2410/mach-n30.c                 |    3 ---
 arch/arm/mach-s3c2410/mach-otom.c                |    3 ---
 arch/arm/mach-s3c2410/mach-qt2410.c              |    3 ---
 arch/arm/mach-s3c2410/mach-smdk2410.c            |    3 ---
 arch/arm/mach-s3c2410/mach-tct_hammer.c          |    3 ---
 arch/arm/mach-s3c2410/mach-vr1000.c              |    3 ---
 arch/arm/mach-s3c2412/mach-jive.c                |    3 ---
 arch/arm/mach-s3c2412/mach-smdk2413.c            |    3 ---
 arch/arm/mach-s3c2412/mach-vstms.c               |    3 ---
 arch/arm/mach-s3c2416/mach-smdk2416.c            |    3 ---
 arch/arm/mach-s3c2440/mach-anubis.c              |    2 --
 arch/arm/mach-s3c2440/mach-at2440evb.c           |    2 --
 arch/arm/mach-s3c2440/mach-gta02.c               |    3 ---
 arch/arm/mach-s3c2440/mach-mini2440.c            |    3 ---
 arch/arm/mach-s3c2440/mach-nexcoder.c            |    3 ---
 arch/arm/mach-s3c2440/mach-osiris.c              |    3 ---
 arch/arm/mach-s3c2440/mach-rx1950.c              |    3 ---
 arch/arm/mach-s3c2440/mach-rx3715.c              |    2 --
 arch/arm/mach-s3c2440/mach-smdk2440.c            |    3 ---
 arch/arm/mach-s3c2443/mach-smdk2443.c            |    3 ---
 arch/arm/mach-s3c64xx/mach-anw6410.c             |    2 --
 arch/arm/mach-s3c64xx/mach-hmt.c                 |    3 ---
 arch/arm/mach-s3c64xx/mach-ncp.c                 |    3 ---
 arch/arm/mach-s3c64xx/mach-smartq.c              |    3 ---
 arch/arm/mach-s3c64xx/mach-smdk6400.c            |    2 --
 arch/arm/mach-s3c64xx/mach-smdk6410.c            |    4 ----
 arch/arm/mach-s5p6440/mach-smdk6440.c            |    4 ----
 arch/arm/mach-s5p6442/mach-smdk6442.c            |    3 ---
 arch/arm/mach-s5pc100/mach-smdkc100.c            |    4 ----
 arch/arm/mach-s5pv210/mach-aquila.c              |    4 ----
 arch/arm/mach-s5pv210/mach-goni.c                |    4 ----
 arch/arm/mach-s5pv210/mach-smdkc110.c            |    4 ----
 arch/arm/mach-s5pv210/mach-smdkv210.c            |    4 ----
 arch/arm/plat-samsung/include/plat/regs-serial.h |    1 -
 37 files changed, 0 insertions(+), 111 deletions(-)

diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 34fc05a..cc7de3a 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -125,21 +125,18 @@ static struct map_desc amlm5900_iodesc[] __initdata = {
 static struct s3c2410_uartcfg amlm5900_uartcfgs[] = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index c1f90f6..75a2df0 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -183,7 +183,6 @@ static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
@@ -192,7 +191,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
@@ -202,7 +200,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 	/* port 2 is not actually used */
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 779b45b..eec80f6 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -74,14 +74,12 @@ static struct map_desc h1940_iodesc[] __initdata = {
 static struct s3c2410_uartcfg h1940_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = 0x245,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x00,
@@ -89,7 +87,6 @@ static struct s3c2410_uartcfg h1940_uartcfgs[] __initdata = {
 	/* IR port */
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.uart_flags  = UPF_CONS_FLOW,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x43,
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 41f299d..52244cb 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -59,7 +59,6 @@ static struct s3c2410_uartcfg n30_uartcfgs[] = {
 	/* Normal serial port */
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = 0x2c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
@@ -67,7 +66,6 @@ static struct s3c2410_uartcfg n30_uartcfgs[] = {
 	/* IR port */
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.uart_flags  = UPF_CONS_FLOW,
 		.ucon	     = 0x2c5,
 		.ulcon	     = 0x43,
@@ -77,7 +75,6 @@ static struct s3c2410_uartcfg n30_uartcfgs[] = {
 	 * On the N35 and variants the GPS receiver is connected here. */
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = 0x2c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index d8c7f2e..c9925fc 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -50,14 +50,12 @@ static struct map_desc otom11_iodesc[] __initdata = {
 static struct s3c2410_uartcfg otom11_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
@@ -65,7 +63,6 @@ static struct s3c2410_uartcfg otom11_uartcfgs[] __initdata = {
 	/* port 2 is not actually used */
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index d0e87b6..a8efc13 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -74,21 +74,18 @@ static struct map_desc qt2410_iodesc[] __initdata = {
 static struct s3c2410_uartcfg smdk2410_uartcfgs[] = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index 4522230..c3aaa31 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -65,21 +65,18 @@ static struct map_desc smdk2410_iodesc[] __initdata = {
 static struct s3c2410_uartcfg smdk2410_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
index 929164a..78775fd 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -103,21 +103,18 @@ static struct map_desc tct_hammer_iodesc[] __initdata = {
 static struct s3c2410_uartcfg tct_hammer_uartcfgs[] = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index d540d79..eafcc5f 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -129,7 +129,6 @@ static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
 static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
@@ -138,7 +137,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
@@ -148,7 +146,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
 	/* port 2 is not actually used */
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 478f4b4..dfe494e 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -65,21 +65,18 @@ static struct map_desc jive_iodesc[] __initdata = {
 static struct s3c2410_uartcfg jive_uartcfgs[] = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index ba93a35..8cc2f9f 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -56,14 +56,12 @@ static struct map_desc smdk2413_iodesc[] __initdata = {
 static struct s3c2410_uartcfg smdk2413_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
@@ -71,7 +69,6 @@ static struct s3c2410_uartcfg smdk2413_uartcfgs[] __initdata = {
 	/* IR port */
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x43,
 		.ufcon	     = 0x51,
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index 3ca9265..9827c89 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -55,21 +55,18 @@ static struct map_desc vstms_iodesc[] __initdata = {
 static struct s3c2410_uartcfg vstms_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
index 5fc3f67..912e64e 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -91,14 +91,12 @@ static struct map_desc smdk2416_iodesc[] __initdata = {
 static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
@@ -106,7 +104,6 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
 	/* IR port */
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON | 0x50,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index b73f78a..b29a37f 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -115,7 +115,6 @@ static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
 static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
@@ -124,7 +123,6 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
 	},
 	[1] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 8472579..6503ce3 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -76,7 +76,6 @@ static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = {
 static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
@@ -85,7 +84,6 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index 9e39faa..d128f4c 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -128,21 +128,18 @@ static struct map_desc gta02_iodesc[] __initdata = {
 static struct s3c2410_uartcfg gta02_uartcfgs[] = {
 	[0] = {
 		.hwport		= 0,
-		.flags		= 0,
 		.ucon		= UCON,
 		.ulcon		= ULCON,
 		.ufcon		= UFCON,
 	},
 	[1] = {
 		.hwport		= 1,
-		.flags		= 0,
 		.ucon		= UCON,
 		.ulcon		= ULCON,
 		.ufcon		= UFCON,
 	},
 	[2] = {
 		.hwport		= 2,
-		.flags		= 0,
 		.ucon		= UCON,
 		.ulcon		= ULCON,
 		.ufcon		= UFCON,
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index a76bcda..61d2bf0 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -74,21 +74,18 @@ static struct map_desc mini2440_iodesc[] __initdata = {
 static struct s3c2410_uartcfg mini2440_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 3ff62de..727862c 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -58,21 +58,18 @@ static struct map_desc nexcoder_iodesc[] __initdata = {
 static struct s3c2410_uartcfg nexcoder_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 319458d..0a4af5b 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -118,7 +118,6 @@ static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
 static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
@@ -127,7 +126,6 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
@@ -136,7 +134,6 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 8603b57..a144861 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -72,7 +72,6 @@ static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = {
 static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
 	[0] = {
 	       .hwport = 0,
-	       .flags = 0,
 	       .ucon = 0x3c5,
 	       .ulcon = 0x03,
 	       .ufcon = 0x51,
@@ -81,7 +80,6 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
 	},
 	[1] = {
 	       .hwport = 1,
-	       .flags = 0,
 	       .ucon = 0x3c5,
 	       .ulcon = 0x03,
 	       .ufcon = 0x51,
@@ -91,7 +89,6 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = {
 	/* IR port */
 	[2] = {
 	       .hwport = 2,
-	       .flags = 0,
 	       .ucon = 0x3c5,
 	       .ulcon = 0x43,
 	       .ufcon = 0xf1,
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index d2946de..a31961f 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -79,7 +79,6 @@ static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = {
 static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
@@ -88,7 +87,6 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = {
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x00,
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index df83276..b6c9de1 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -80,14 +80,12 @@ static struct map_desc smdk2440_iodesc[] __initdata = {
 static struct s3c2410_uartcfg smdk2440_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
@@ -95,7 +93,6 @@ static struct s3c2410_uartcfg smdk2440_uartcfgs[] __initdata = {
 	/* IR port */
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x43,
 		.ufcon	     = 0x51,
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index 4c863d3..a1c1de0 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -80,14 +80,12 @@ static struct map_desc smdk2443_iodesc[] __initdata = {
 static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
@@ -95,7 +93,6 @@ static struct s3c2410_uartcfg smdk2443_uartcfgs[] __initdata = {
 	/* IR port */
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x43,
 		.ufcon	     = 0x51,
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index 4a0bb24..baa91a1 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -69,14 +69,12 @@ static __u32 anw6410_extdev_status;
 static struct s3c2410_uartcfg anw6410_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 187441a..4790294 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -50,21 +50,18 @@
 static struct s3c2410_uartcfg hmt_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index bf65747..7b9d86e 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -53,21 +53,18 @@ static struct s3c2410_uartcfg ncp_uartcfgs[] __initdata = {
 	/* REVISIT: NCP uses only serial 1, 2 */
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 028d080..e772890 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -46,21 +46,18 @@
 static struct s3c2410_uartcfg smartq_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 5991667..15269ae 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -44,14 +44,12 @@
 static struct s3c2410_uartcfg smdk6400_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = 0x3c5,
 		.ulcon	     = 0x03,
 		.ufcon	     = 0x51,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index d9a0355..2e7b261 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -74,28 +74,24 @@
 static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
 	},
 	[3] = {
 		.hwport	     = 3,
-		.flags	     = 0,
 		.ucon	     = UCON,
 		.ulcon	     = ULCON,
 		.ufcon	     = UFCON,
diff --git a/arch/arm/mach-s5p6440/mach-smdk6440.c b/arch/arm/mach-s5p6440/mach-smdk6440.c
index 8291fec..f93c8c5 100644
--- a/arch/arm/mach-s5p6440/mach-smdk6440.c
+++ b/arch/arm/mach-s5p6440/mach-smdk6440.c
@@ -57,28 +57,24 @@
 static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = S5P6440_UCON_DEFAULT,
 		.ulcon	     = S5P6440_ULCON_DEFAULT,
 		.ufcon	     = S5P6440_UFCON_DEFAULT,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = S5P6440_UCON_DEFAULT,
 		.ulcon	     = S5P6440_ULCON_DEFAULT,
 		.ufcon	     = S5P6440_UFCON_DEFAULT,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = S5P6440_UCON_DEFAULT,
 		.ulcon	     = S5P6440_ULCON_DEFAULT,
 		.ufcon	     = S5P6440_UFCON_DEFAULT,
 	},
 	[3] = {
 		.hwport	     = 3,
-		.flags	     = 0,
 		.ucon	     = S5P6440_UCON_DEFAULT,
 		.ulcon	     = S5P6440_ULCON_DEFAULT,
 		.ufcon	     = S5P6440_UFCON_DEFAULT,
diff --git a/arch/arm/mach-s5p6442/mach-smdk6442.c b/arch/arm/mach-s5p6442/mach-smdk6442.c
index ebcf997..dc0fa72 100644
--- a/arch/arm/mach-s5p6442/mach-smdk6442.c
+++ b/arch/arm/mach-s5p6442/mach-smdk6442.c
@@ -43,21 +43,18 @@
 static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport		= 0,
-		.flags		= 0,
 		.ucon		= S5P6442_UCON_DEFAULT,
 		.ulcon		= S5P6442_ULCON_DEFAULT,
 		.ufcon		= S5P6442_UFCON_DEFAULT,
 	},
 	[1] = {
 		.hwport		= 1,
-		.flags		= 0,
 		.ucon		= S5P6442_UCON_DEFAULT,
 		.ulcon		= S5P6442_ULCON_DEFAULT,
 		.ufcon		= S5P6442_UFCON_DEFAULT,
 	},
 	[2] = {
 		.hwport		= 2,
-		.flags		= 0,
 		.ucon		= S5P6442_UCON_DEFAULT,
 		.ulcon		= S5P6442_ULCON_DEFAULT,
 		.ufcon		= S5P6442_UFCON_DEFAULT,
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index af22f82..1698d03 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -60,28 +60,24 @@
 static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport	     = 0,
-		.flags	     = 0,
 		.ucon	     = S5PC100_UCON_DEFAULT,
 		.ulcon	     = S5PC100_ULCON_DEFAULT,
 		.ufcon	     = S5PC100_UFCON_DEFAULT,
 	},
 	[1] = {
 		.hwport	     = 1,
-		.flags	     = 0,
 		.ucon	     = S5PC100_UCON_DEFAULT,
 		.ulcon	     = S5PC100_ULCON_DEFAULT,
 		.ufcon	     = S5PC100_UFCON_DEFAULT,
 	},
 	[2] = {
 		.hwport	     = 2,
-		.flags	     = 0,
 		.ucon	     = S5PC100_UCON_DEFAULT,
 		.ulcon	     = S5PC100_ULCON_DEFAULT,
 		.ufcon	     = S5PC100_UFCON_DEFAULT,
 	},
 	[3] = {
 		.hwport	     = 3,
-		.flags	     = 0,
 		.ucon	     = S5PC100_UCON_DEFAULT,
 		.ulcon	     = S5PC100_ULCON_DEFAULT,
 		.ufcon	     = S5PC100_UFCON_DEFAULT,
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 10bc76e..37a62dd 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -46,28 +46,24 @@
 static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport		= 0,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[1] = {
 		.hwport		= 1,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[2] = {
 		.hwport		= 2,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[3] = {
 		.hwport		= 3,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 4863b13..b0e54ea 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -43,28 +43,24 @@
 static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport		= 0,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[1] = {
 		.hwport		= 1,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[2] = {
 		.hwport		= 2,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[3] = {
 		.hwport		= 3,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 4c8903c..1410a5f 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -43,28 +43,24 @@
 static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport		= 0,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[1] = {
 		.hwport		= 1,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[2] = {
 		.hwport		= 2,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[3] = {
 		.hwport		= 3,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 0d46279..e0d72fc 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -45,28 +45,24 @@
 static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport		= 0,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[1] = {
 		.hwport		= 1,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[2] = {
 		.hwport		= 2,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
 	},
 	[3] = {
 		.hwport		= 3,
-		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
 		.ufcon		= S5PV210_UFCON_DEFAULT,
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index a6eba84..24c1e92 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -256,7 +256,6 @@ struct s3c24xx_uart_clksrc {
 struct s3c2410_uartcfg {
 	unsigned char	   hwport;	 /* hardware port number */
 	unsigned char	   unused;
-	unsigned short	   flags;
 	upf_t		   uart_flags;	 /* default uart flags */
 
 	unsigned long	   ucon;	 /* value of ucon for port */
-- 
1.7.0.4



From john.ogness at linutronix.de  Sun Jun 20 05:21:25 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Sun, 20 Jun 2010 11:21:25 +0200
Subject: [PATCHv2 4/5] mtd: mxc_nand fixups
In-Reply-To: <AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
	(Ivo Clarysse's message of "Sun, 20 Jun 2010 11:09:03 +0200")
References: <804oh0b7gx.fsf@merkur.tec.linutronix.de>
	<20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
	<AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
Message-ID: <80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>

On 2010-06-20, Ivo Clarysse <ivo.clarysse at gmail.com> wrote:
> Yes, on i.MX21, NFC interrupts can be masked using
> NFC_CONFIG1:NFC_INT_MSK.  But I observed that as long as NFC_INT_MSK
> is set, NFC_CONFIG2:NFC_INT will always read out 0 on i.MX21, even if
> the operation is completed.
>
> So the driver will remain stuck at:
>
>                  wait_event(host->irq_waitq,
>                          readw(host->regs + NFC_CONFIG2) & NFC_INT);

OK. Here is alternative patch. Do you have access to an i.MX21 to test
this on?

This patch fixes the driver so that the irq is requested as disabled. This
prevents double irq enabling and also does not require the interrupt to
be disabled within the interrupt handler. (Actually, I beleive this was
the true intention of the original author.)

The patch is against linux-next 20100618.

Signed-off-by: John Ogness <john.ogness at linutronix.de>
---
 drivers/mtd/nand/mxc_nand.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Index: linux-next-20100618/drivers/mtd/nand/mxc_nand.c
===================================================================
--- linux-next-20100618.orig/drivers/mtd/nand/mxc_nand.c
+++ linux-next-20100618/drivers/mtd/nand/mxc_nand.c
@@ -30,6 +30,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/irq.h>
 
 #include <asm/mach/flash.h>
 #include <mach/mxc_nand.h>
@@ -846,7 +847,9 @@ static int __init mxcnd_probe(struct pla
 
 	host->irq = platform_get_irq(pdev, 0);
 
-	err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
+	/* request irq as disabled */
+	err = request_irq(host->irq, mxc_nfc_irq, IRQF_NOAUTOEN,
+			  DRIVER_NAME, host);
 	if (err)
 		goto eirq;
 


From redhatter at gentoo.org  Fri Jun 18 18:24:36 2010
From: redhatter at gentoo.org (Stuart Longland)
Date: Sat, 19 Jun 2010 08:24:36 +1000
Subject: [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
In-Reply-To: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
References: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
Message-ID: <1276899876-19001-1-git-send-email-redhatter@gentoo.org>

The TLV320AIC3204 is a low-power stereo audio CODEC capable of sample
rates of up to 192kHz.  This driver implements basic functionality,
using I?C for the control channel.

The audio interface supports many data bus formats, including I?S
master/slave, DSP, left/right justified and TDM.

What works:
	- Playback at various bitrates up to 96kHz
	- Recording at various bitrates up to 96kHz
	- Mixer interface
	- PLL generation of CODEC clocks from MCLK

What could work better:
	- DAPM

What isn't tested:
	- Audio interfaces other than I?S
	- PLL with clocks other than ~12MHz
	- Mono recording/playback
	- 192kHz recording/playback
	- Suspend & Resume

What isn't implemented:
	- SPI interface support
	- PLL without fractional divider (would allow <10MHz clocks)
	- Clock sources other than MCLK
	- Adaptive filtering
	- AGC
	- Headset detection, JACK framework

TODO list:
	- Clean up the register cache ... this is in the early
	  planning phase

Signed-off-by: Stuart Longland <redhatter at gentoo.org>
---
 include/sound/tlv320aic3204.h    |   64 +
 sound/soc/codecs/Kconfig         |    5 +
 sound/soc/codecs/Makefile        |    2 +
 sound/soc/codecs/tlv320aic3204.c | 4197 ++++++++++++++++++++++++++++++++++++++
 sound/soc/codecs/tlv320aic3204.h | 1350 ++++++++++++
 5 files changed, 5618 insertions(+), 0 deletions(-)
 create mode 100644 include/sound/tlv320aic3204.h
 create mode 100644 sound/soc/codecs/tlv320aic3204.c
 create mode 100644 sound/soc/codecs/tlv320aic3204.h

diff --git a/include/sound/tlv320aic3204.h b/include/sound/tlv320aic3204.h
new file mode 100644
index 0000000..491cd22
--- /dev/null
+++ b/include/sound/tlv320aic3204.h
@@ -0,0 +1,64 @@
+/*
+ * Platform data for Texas Instruments TLV320AIC3204 codec
+ *
+ * Copyright (C) 2010 Jacques Electronics Pty Ltd
+ * Author: Stuart Longland <redhatter at gentoo.org>
+ *
+ * Based on tlv320aic3x.h:
+ * Author: Jarkko Nikula <jhnikula at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __TLV320AIC3204_H__
+#define __TLV320AIC3204_H__
+
+/*
+ * Analogue Input Quick-Charge Power Up Delay
+ */
+enum {
+	/* Power up time: Default Value (whatever that is) */
+	AIC3204_PDATA_AIN_PWRUP_DEFAULT	= (0x00),
+	/* Power up time: 3.1ms */
+	AIC3204_PDATA_AIN_PWRUP_3M1S	= (0x31),
+	/* Power up time: 6.4ms */
+	AIC3204_PDATA_AIN_PWRUP_6M4S	= (0x32),
+	/* Power up time: 1.6ms */
+	AIC3204_PDATA_AIN_PWRUP_1M6S	= (0x33),
+};
+
+/*
+ * Analogue Reference Power Up Delay
+ */
+enum {
+	/* Reference Power-Up delay: Slow */
+	AIC3204_PDATA_REF_PWRUP_SLOW	= (0 << 0),
+	/* Reference Power-Up delay: 40ms */
+	AIC3204_PDATA_REF_PWRUP_40MS	= (1 << 0),
+	/* Reference Power-Up delay: 80ms */
+	AIC3204_PDATA_REF_PWRUP_80MS	= (2 << 0),
+	/* Reference Power-Up delay: 120ms */
+	AIC3204_PDATA_REF_PWRUP_120MS	= (3 << 0),
+};
+
+struct aic3204_pdata {
+	int gpio_reset; /* < 0 if not used */
+
+	/* Analogue-in Power up delay */
+	u8	ain_pwrup_delay;
+
+	/* Analogue Reference Power up delay */
+	u8	ref_pwrup_delay;
+
+	/* AVDD <->DVDD Link enable */
+	u8	avdd_link_en;
+
+	/* LDO Enable */
+	u8	ldo_en;
+
+	/* Oversampling rate (both ADC and DAC) */
+	u8	osr;
+};
+
+#endif
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
index c37c844..80b56a4 100644
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -32,6 +32,7 @@ config SND_SOC_ALL_CODECS
 	select SND_SOC_STAC9766 if SND_SOC_AC97_BUS
 	select SND_SOC_TLV320AIC23 if I2C
 	select SND_SOC_TLV320AIC26 if SPI_MASTER
+	select SND_SOC_TLV320AIC3204 if I2C
 	select SND_SOC_TLV320AIC3X if I2C
 	select SND_SOC_TPA6130A2 if I2C
 	select SND_SOC_TLV320DAC33 if I2C
@@ -164,6 +165,10 @@ config SND_SOC_TLV320AIC26
 	tristate "TI TLV320AIC26 Codec support" if SND_SOC_OF_SIMPLE
 	depends on SPI
 
+config SND_SOC_TLV320AIC3204
+	tristate
+	depends on I2C
+
 config SND_SOC_TLV320AIC3X
 	tristate
 
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
index 4a9c205..c649f14 100644
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -20,6 +20,7 @@ snd-soc-ssm2602-objs := ssm2602.o
 snd-soc-stac9766-objs := stac9766.o
 snd-soc-tlv320aic23-objs := tlv320aic23.o
 snd-soc-tlv320aic26-objs := tlv320aic26.o
+snd-soc-tlv320aic3204-objs := tlv320aic3204.o
 snd-soc-tlv320aic3x-objs := tlv320aic3x.o
 snd-soc-tlv320dac33-objs := tlv320dac33.o
 snd-soc-twl4030-objs := twl4030.o
@@ -86,6 +87,7 @@ obj-$(CONFIG_SND_SOC_SSM2602)	+= snd-soc-ssm2602.o
 obj-$(CONFIG_SND_SOC_STAC9766)	+= snd-soc-stac9766.o
 obj-$(CONFIG_SND_SOC_TLV320AIC23)	+= snd-soc-tlv320aic23.o
 obj-$(CONFIG_SND_SOC_TLV320AIC26)	+= snd-soc-tlv320aic26.o
+obj-$(CONFIG_SND_SOC_TLV320AIC3204)	+= snd-soc-tlv320aic3204.o
 obj-$(CONFIG_SND_SOC_TLV320AIC3X)	+= snd-soc-tlv320aic3x.o
 obj-$(CONFIG_SND_SOC_TLV320DAC33)	+= snd-soc-tlv320dac33.o
 obj-$(CONFIG_SND_SOC_TWL4030)	+= snd-soc-twl4030.o
diff --git a/sound/soc/codecs/tlv320aic3204.c b/sound/soc/codecs/tlv320aic3204.c
new file mode 100644
index 0000000..6b185c5
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic3204.c
@@ -0,0 +1,4197 @@
+/*
+ * ALSA SoC TLV320AIC3204 codec driver
+ *
+ * Author:	Stuart Longland, <redhatter at gentoo.org>
+ * Copyright:	(C) 2010 Jacques Electronics Pty. Ltd.
+ *
+ * Based upon the TLV320AIC3X driver:
+ * Author:      Vladimir Barinov, <vbarinov at embeddedalley.com>
+ * Copyright:   (C) 2007 MontaVista Software, Inc., <source at mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/pm.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <sound/soc-dapm.h>
+#include <sound/initval.h>
+#include <sound/tlv.h>
+#include <sound/tlv320aic3204.h>
+
+#include "tlv320aic3204.h"
+
+/*
+ * Default settings; these will be used if no platform data is provided.
+ */
+static const struct aic3204_pdata aic3204_default_pdata = {
+	.gpio_reset		= -1,
+	.ain_pwrup_delay	= AIC3204_PDATA_AIN_PWRUP_DEFAULT,
+	.ref_pwrup_delay	= AIC3204_PDATA_REF_PWRUP_SLOW,
+	.avdd_link_en		= 1,
+	.ldo_en			= 0,
+	.osr			= 128,
+};
+
+/*
+ * Default Register Values; this is used to initialise the register cache.
+ * There are 128 pages, of 128 registers each stored here.  The data was
+ * captured from a TLV320AIC3204 immediately after reset, and therefore should
+ * be representative of what's displayed in the datasheet.
+ */
+static const u8 aic3204_default_reg_data[128*128] = {
+	/* --- Page 0 --- */
+	0x00, 0x00, 0x50, 0x00, 0x00, 0x11, 0x04, 0x00,
+	0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x80, 0x02,
+	0x00, 0x08, 0x01, 0x01, 0x80, 0x01, 0x00, 0x04,
+	0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0x03, 0x02,
+	0x02, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00, 0x14,
+	0x0c, 0x00, 0x00, 0x00, 0x6f, 0x38, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0xee, 0x10, 0xd8, 0x7e, 0xe3,
+	0x00, 0x00, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 1 --- */
+	0x01, 0x00, 0x0e, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
+	0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 2 --- */
+	0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 3 --- */
+	0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 4 --- */
+	0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 5 --- */
+	0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 6 --- */
+	0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 7 --- */
+	0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 8 --- */
+	0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x01, 0x17, 0x00, 0x00,
+	0x01, 0x17, 0x00, 0x00, 0x7d, 0xd3, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 9 --- */
+	0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+
+	/* --- Page 10 --- */
+	0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 11 --- */
+	0x0b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 12 --- */
+	0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 13 --- */
+	0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 14 --- */
+	0x0e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 15 --- */
+	0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 16 --- */
+	0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x01, 0x17, 0x00, 0x00,
+	0x01, 0x17, 0x00, 0x00, 0x7d, 0xd3, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 17 --- */
+	0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 18 --- */
+	0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 19 --- */
+	0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 20 --- */
+	0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 21 --- */
+	0x15, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 22 --- */
+	0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 23 --- */
+	0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 24 --- */
+	0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 25 --- */
+	0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 26 --- */
+	0x1a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x01, 0x17, 0x00, 0x00,
+	0x01, 0x17, 0x00, 0x00, 0x7d, 0xd3, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 27 --- */
+	0x1b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+
+	/* --- Page 28 --- */
+	0x1c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 29 --- */
+	0x1d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 30 --- */
+	0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 31 --- */
+	0x1f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 32 --- */
+	0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 33 --- */
+	0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 34 --- */
+	0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x01, 0x17, 0x00, 0x00,
+	0x01, 0x17, 0x00, 0x00, 0x7d, 0xd3, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 35 --- */
+	0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 36 --- */
+	0x24, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 37 --- */
+	0x25, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 38 --- */
+	0x26, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 39 --- */
+	0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 40 --- */
+	0x28, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 41 --- */
+	0x29, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 42 --- */
+	0x2a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 43 --- */
+	0x2b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 44 --- */
+	0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 45 --- */
+	0x2d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 46 --- */
+	0x2e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xf7, 0x00, 0x00,
+	0x80, 0x09, 0x00, 0x00, 0x7f, 0xef, 0x00, 0x00,
+	0x00, 0x11, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00,
+	0x7f, 0xde, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 47 --- */
+	0x2f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 48 --- */
+	0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 49 --- */
+	0x31, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 50 --- */
+	0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 51 --- */
+	0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 52 --- */
+	0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 53 --- */
+	0x35, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 54 --- */
+	0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 55 --- */
+	0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 56 --- */
+	0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 57 --- */
+	0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 58 --- */
+	0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 59 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 60 --- */
+	0x3c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 61 --- */
+	0x3d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 62 --- */
+	0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 63 --- */
+	0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 64 --- */
+	0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xf7, 0x00, 0x00,
+	0x80, 0x09, 0x00, 0x00, 0x7f, 0xef, 0x00, 0x00,
+	0x00, 0x11, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00,
+	0x7f, 0xde, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 65 --- */
+	0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 66 --- */
+	0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 67 --- */
+	0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 68 --- */
+	0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 69 --- */
+	0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 70 --- */
+	0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x7f, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x7f, 0xff, 0xff, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 71 --- */
+	0x47, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 72 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 73 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 74 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 75 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 76 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 77 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 78 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 79 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 80 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 81 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 82 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 83 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 84 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 85 --- */
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+
+	/* --- Page 86 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 87 --- */
+	0x57, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 88 --- */
+	0x58, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 89 --- */
+	0x59, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 90 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 91 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 92 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 93 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 94 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 95 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 96 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 97 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 98 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 99 --- */
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+
+	/* --- Page 100 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 101 --- */
+	0x65, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 102 --- */
+	0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 103 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 104 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 105 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 106 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 107 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 108 --- */
+	0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 109 --- */
+	0x6d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 110 --- */
+	0x6e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 111 --- */
+	0x6f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 112 --- */
+	0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 113 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+
+	/* --- Page 114 --- */
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+
+	/* --- Page 115 --- */
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+	/* --- Page 116 --- */
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+	/* --- Page 117 --- */
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+
+	/* --- Page 118 --- */
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+	/* --- Page 119 --- */
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+	/* --- Page 120 --- */
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+
+	/* --- Page 121 --- */
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+
+	/* --- Page 122 --- */
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+
+	/* --- Page 123 --- */
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+
+	/* --- Page 124 --- */
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+
+	/* --- Page 125 --- */
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+
+	/* --- Page 126 --- */
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+	/* --- Page 127 --- */
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+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+#define AIC3204_NUM_SUPPLIES	4
+static const char *aic3204_supply_names[AIC3204_NUM_SUPPLIES] = {
+	"IOVDD",	/* I/O Voltage */
+	"DVDD",		/* Digital Core Voltage */
+	"AVDD",		/* Analog DAC Voltage */
+	"LDOin",	/* Supply for internal LDOs and output amplifiers */
+};
+
+/* codec private data */
+struct aic3204_priv {
+	struct snd_soc_codec codec;
+	struct regulator_bulk_data supplies[AIC3204_NUM_SUPPLIES];
+	unsigned int sysclk;
+	struct aic3204_pdata pdata;
+};
+
+/*
+ * Determine whether a register is readable.
+ */
+static int aic3204_reg_is_readable(unsigned int reg)
+{
+	u8 page = reg >> 7;
+	reg &= 0x7f;
+
+	/* Anything beyond page 70 is undefined */
+	if (page > 70)
+		return 0;
+
+	/* Page 62..70 */
+	if (page >= 62) {
+		/* Register 0 is page select */
+		if (reg == 0)
+			return 1;
+		/* Registers 1..7 are reserved */
+		if (reg <= 7)
+			return 0;
+		/* Registers 8..127 are valid */
+		return 1;
+	}
+
+	/* Pages 53..62 are undefined */
+	if (page >= 53)
+		return 0;
+
+	/* Pages 45..52 */
+	if (page >= 45) {
+		/* Register 0 is page select */
+		if (reg == 0)
+			return 1;
+		/* Registers 1..7 are reserved */
+		if (reg <= 7)
+			return 0;
+		/* Registers 8..127 are valid */
+		return 1;
+	}
+
+	/* Page 44 --- XXX The datasheet may have some typos here! */
+	if (page == 44) {
+		/*
+		 * Register 0 is page select
+		 * Register 1 enables adaptive filtering
+		 */
+		if (reg <= 1)
+			return 1;
+		/* Registers 2..7 are reserved */
+		if (reg <= 7)
+			return 0;
+		/* Registers 8..127 are valid */
+		return 1;
+	}
+
+	/* Pages 35..43 are undefined */
+	if (page >= 35)
+		return 0;
+
+	/* Pages 26..34 */
+	if (page >= 26) {
+		/* Register 0 is page select */
+		if (reg == 0)
+			return 1;
+		/* Registers 1..7 are reserved */
+		if (reg <= 7)
+			return 0;
+		/* Registers 8..127 are valid */
+		return 1;
+	}
+
+	/* Pages 17..25 are undefined */
+	if (page >= 17)
+		return 0;
+
+	/* Pages 9..16 */
+	if (page >= 9) {
+		if (reg == 0)
+			return 1;
+		if (reg <= 7)
+			return 0;
+		return 1;
+	}
+
+	/* Page 8 */
+	if (page == 8) {
+		if (reg <= 1)
+			return 1;
+		if (reg <= 7)
+			return 0;
+		return 1;
+	}
+
+	/* Page 2..7 are undefined */
+	if (page >= 2)
+		return 0;
+
+	/* Page 1 */
+	if (page == 1) {
+		if (reg <= 4)
+			return 1;
+		if (reg <= 8)
+			return 0;
+		if (reg <= 20)
+			return 1;
+		if (reg == 21)
+			return 0;
+		if (reg <= 25)
+			return 1;
+		if (reg <= 50)
+			return 0;
+		if (reg <= 52)
+			return 1;
+		if (reg == 53)
+			return 0;
+		if (reg <= 55)
+			return 1;
+		if (reg == 56)
+			return 0;
+		if (reg <= 63)
+			return 1;
+		if (reg <= 70)
+			return 0;
+		if (reg == 71)
+			return 1;
+		if (reg <= 122)
+			return 0;
+		if (reg == 123)
+			return 1;
+		return 0;
+	}
+
+	/* Page 0 */
+	if (reg == 0)
+		return 1;
+	if (reg <= 3)
+		return 0;
+	if (reg <= 8)
+		return 1;
+	if (reg <= 10)
+		return 0;
+	if (reg <= 14)
+		return 1;
+	if (reg <= 17)
+		return 0;
+	if (reg <= 20)
+		return 1;
+	if (reg <= 24)
+		return 0;
+	if (reg <= 34)
+		return 1;
+	if (reg == 35)
+		return 0;
+	if (reg <= 38)
+		return 1;
+	if (reg <= 41)
+		return 0;
+	if (reg <= 49)
+		return 1;
+	if (reg <= 51)
+		return 0;
+	if (reg <= 56)
+		return 1;
+	if (reg <= 59)
+		return 0;
+	if (reg <= 61)
+		return 1;
+	if (reg == 62)
+		return 0;
+	if (reg <= 79)
+		return 1;
+	if (reg == 80)
+		return 0;
+	if (reg <= 109)
+		return 1;
+	return 0;
+}
+
+/*
+ * read aic3204 register cache
+ */
+static inline unsigned int aic3204_read_reg_cache(struct snd_soc_codec *codec,
+						unsigned int reg)
+{
+	u8 *cache = codec->reg_cache;
+	if (reg >= AIC3204_CACHEREGNUM)
+		return -EINVAL;
+
+	return cache[reg];
+}
+
+/*
+ * Pretty-print the value of a register
+ */
+static int aic3204_show_reg(struct snd_soc_codec *codec, char *buf,
+		int buf_sz, unsigned int reg)
+{
+	return snprintf(buf, buf_sz, "%02x",
+			aic3204_read_reg_cache(codec, reg));
+}
+
+/*
+ * write aic3204 register cache
+ */
+static inline void aic3204_write_reg_cache(struct snd_soc_codec *codec,
+					 u16 reg, u8 value)
+{
+	u8 *cache = codec->reg_cache;
+
+	if (reg >= AIC3204_CACHEREGNUM)
+		return;
+	cache[reg] = value;
+}
+
+/*
+ * write to the aic3204 register space
+ */
+static int aic3204_write(struct snd_soc_codec *codec, unsigned int reg,
+		       unsigned int value)
+{
+	/* data is
+	 *   D15..D8 aic3204 register offset
+	 *   D7...D0 register data
+	 */
+	u8 data[2];
+
+	/*
+	 * Register number; upper 8 bits indicate page
+	 */
+	if (reg && (aic3204_read_reg_cache(codec, AIC3204_PAGE_SELECT)
+			!= (reg >> 7))) {
+		/* Select the required page */
+		data[0] = 0;
+		data[1] = reg >> 7;
+		if (codec->hw_write(codec->control_data, data, 2) != 2)
+			return -EIO;
+		aic3204_write_reg_cache(codec, AIC3204_PAGE_SELECT, reg >> 7);
+		dev_dbg(codec->dev, "%s: Page %d selected\n",
+				__func__, reg >> 7);
+	}
+
+	data[0] = reg & 0x7f;
+	data[1] = value & 0xff;
+
+	if (codec->hw_write(codec->control_data, data, 2) != 2)
+		return -EIO;
+
+	dev_dbg(codec->dev, "%s: pg %d reg %d[%04x] <= %02x\n",
+			__func__, reg >> 7, reg & 0x7f, reg, value);
+	aic3204_write_reg_cache(codec, reg, value);
+	return 0;
+}
+
+/*
+ * read from the aic3204 register space
+ */
+static int aic3204_read(struct snd_soc_codec *codec, unsigned int reg,
+		      u8 *value)
+{
+	*value = reg & 0xff;
+
+	/*
+	 * Register number; upper 8 bits indicate page
+	 */
+	if (reg && (aic3204_read_reg_cache(codec, AIC3204_PAGE_SELECT)
+			!= (reg >> 7)))
+		/* Select the required page */
+		aic3204_write(codec, AIC3204_PAGE_SELECT, (reg >> 7));
+
+	value[0] = i2c_smbus_read_byte_data(codec->control_data, value[0]);
+	dev_dbg(codec->dev, "%s: pg %d reg %d[%04x] => %02x\n",
+			__func__, reg >> 7, reg & 0x7f, reg, value[0]);
+	aic3204_write_reg_cache(codec, reg, *value);
+	return 0;
+}
+
+/*
+ * Check BCLK direction.  Returns >0 if the BCLK pin is an output, 0 if it's an
+ * input, or negative error.
+ */
+static inline int aic3204_check_bclk_is_output(
+		struct snd_soc_dapm_widget *source,
+		struct snd_soc_dapm_widget *sink)
+{
+	int reg = snd_soc_read(source->codec, AIC3204_AISR1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR1_BCLK;
+
+	return reg & AIC3204_AISR1_BCLK_OUT;
+}
+
+/*
+ * Check WCLK direction.  Returns >0 if the WCLK pin is an output, 0 if it's an
+ * input, or negative error.
+ */
+
+static inline int aic3204_check_wclk_is_output(
+		struct snd_soc_dapm_widget *source,
+		struct snd_soc_dapm_widget *sink)
+{
+	int reg = snd_soc_read(source->codec, AIC3204_AISR1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR1_WCLK;
+
+	return reg & AIC3204_AISR1_WCLK_OUT;
+}
+
+/*
+ * Check PLL source; called by the PLL input clock DAPM widgets.
+ * Returns 1 if the two given widgets are presently connected, 0 otherwise.
+ * Negative error number returned on error.
+ */
+static int aic3204_check_pll_clk_src(struct snd_soc_dapm_widget *source,
+		struct snd_soc_dapm_widget *sink)
+{
+	int reg = snd_soc_read(source->codec, AIC3204_CLK1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+
+	reg &= AIC3204_CLK1_PLLSRC;
+
+	if (reg == AIC3204_CLK1_PLLSRC_MCLK)
+		reg = (!strcmp(source->name, "MCLK"));
+	else if (reg == AIC3204_CLK1_PLLSRC_BCLK)
+		reg = (!strcmp(source->name, "BCLK"));
+	else if (reg == AIC3204_CLK1_PLLSRC_GPIO)
+		reg = (!strcmp(source->name, "GPIO"));
+	else if (reg == AIC3204_CLK1_PLLSRC_DIN)
+		reg = (!strcmp(source->name, "DIN"));
+	else
+		reg = 0;
+
+	if (reg)
+		dev_dbg(source->codec->dev, "%s: %s is connected to %s\n",
+				__func__, source->name, sink->name);
+	return reg;
+}
+
+/*
+ * Check CODEC source; called by the CODEC_CLKIN input clock DAPM widgets.
+ * Returns 1 if the two given widgets are presently connected, 0 otherwise.
+ * Negative error number returned on error.
+ */
+static int aic3204_check_codec_clk_src(struct snd_soc_dapm_widget *source,
+		struct snd_soc_dapm_widget *sink)
+{
+	int reg = snd_soc_read(source->codec, AIC3204_CLK1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+
+	reg &= AIC3204_CLK1_CODECCLK;
+
+	if (reg == AIC3204_CLK1_CODECCLK_MCLK)
+		reg = (!strcmp(source->name, "MCLK"));
+	else if (reg == AIC3204_CLK1_CODECCLK_BCLK)
+		reg = (!strcmp(source->name, "BCLK"));
+	else if (reg == AIC3204_CLK1_CODECCLK_GPIO)
+		reg = (!strcmp(source->name, "GPIO"));
+	else if (reg == AIC3204_CLK1_CODECCLK_PLL)
+		reg = (!strcmp(source->name, "PLL_CLK"));
+	else
+		reg = 0;
+
+	if (reg)
+		dev_dbg(source->codec->dev, "%s: %s is connected to %s\n",
+				__func__, source->name, sink->name);
+	return reg;
+}
+
+/*
+ * Check BCLK source; called by the BCLK input clock DAPM widgets.
+ * Returns 1 if the two given widgets are presently connected, 0 otherwise.
+ * Negative error number returned on error.
+ */
+static int aic3204_check_bclk_src(struct snd_soc_dapm_widget *source,
+		struct snd_soc_dapm_widget *sink)
+{
+	int reg = snd_soc_read(source->codec, AIC3204_AISR1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR1_BCLK;
+
+	if (reg == AIC3204_AISR1_BCLK_IN)
+		/* BCLK is externally generated */
+		return 0;
+
+	reg = snd_soc_read(source->codec, AIC3204_AISR3);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR3_BDIV;
+
+	if (reg == AIC3204_AISR3_BDIV_DAC)
+		reg = (!strcmp(source->name, "DAC_CLK"));
+	else if (reg == AIC3204_AISR3_BDIV_DAC_MOD)
+		reg = (!strcmp(source->name, "DAC_MOD_CLK"));
+	else if (reg == AIC3204_AISR3_BDIV_ADC)
+		reg = (!strcmp(source->name, "ADC_CLK"));
+	else if (reg == AIC3204_AISR3_BDIV_ADC_MOD)
+		reg = (!strcmp(source->name, "ADC_MOD_CLK"));
+	else
+		reg = 0;
+
+	if (reg)
+		dev_dbg(source->codec->dev, "%s: %s is connected to %s\n",
+				__func__, source->name, sink->name);
+	return reg;
+}
+
+/*
+ * Check WCLK source; called by the WCLK input clock DAPM widgets.
+ * Returns 1 if the two given widgets are presently connected, 0 otherwise.
+ * Negative error number returned on error.
+ */
+static int aic3204_check_wclk_src(struct snd_soc_dapm_widget *source,
+		struct snd_soc_dapm_widget *sink)
+{
+	int reg = snd_soc_read(source->codec, AIC3204_AISR1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR1_WCLK;
+
+	if (reg == AIC3204_AISR1_WCLK_IN)
+		/* WCLK is externally generated */
+		return 0;
+
+	reg = snd_soc_read(source->codec, AIC3204_AISR6);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR6_WCLKOUT;
+
+	if (reg == AIC3204_AISR6_WCLKOUT_DAC)
+		reg = (!strcmp(source->name, "DAC_FS"));
+	else if (reg == AIC3204_AISR6_WCLKOUT_ADC)
+		reg = (!strcmp(source->name, "ADC_FS"));
+	else
+		reg = 0;
+
+	if (reg)
+		dev_dbg(source->codec->dev, "%s: %s is connected to %s\n",
+				__func__, source->name, sink->name);
+
+	return reg;
+}
+
+/*
+ * Event handler for audio interface BCLK; checks the state of the ADCs and
+ * DACs and switches the audio interface to the presently active clock.
+ */
+static int aic3204_aif_bclk_event(struct snd_soc_dapm_widget *w,
+			 struct snd_kcontrol *kcontrol, int event) {
+	u8 adcs_up;
+	u8 dacs_up;
+	u8 bclk_src;
+	/* Determine the current source */
+	int reg = snd_soc_read(w->codec, AIC3204_AISR1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR1_BCLK;
+	if (reg == AIC3204_AISR1_BCLK_IN)
+		/* BCLK is an input, not our concirn */
+		return 0;
+
+	reg = snd_soc_read(w->codec, AIC3204_AISR3);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	bclk_src = reg & AIC3204_AISR3_BDIV;
+
+	/*
+	 * These registers are not manipulated by us, so we must read them from
+	 * the CODEC directly.
+	 */
+	reg = aic3204_read(w->codec, AIC3204_ADCF, &adcs_up);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	adcs_up &= (AIC3204_ADCF_LEFT_UP | AIC3204_ADCF_RIGHT_UP);
+
+	reg = aic3204_read(w->codec, AIC3204_DACF1, &dacs_up);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	dacs_up &= (AIC3204_DACF1_LEFT_UP | AIC3204_DACF1_RIGHT_UP);
+
+	dev_dbg(w->codec->dev, "%s: BCLK source=0x%02x, event=%d, "
+			"dacf1=0x%02x, adcf=0x%02x\n", __func__, bclk_src,
+			event, dacs_up, adcs_up);
+
+	/* What are we set to now? */
+	if (bclk_src == AIC3204_AISR3_BDIV_DAC) {
+		/* Currently listening to DAC... check that it's up */
+		if (adcs_up && !dacs_up)
+			/* No, but the ADCs are up; switch to those */
+			bclk_src = AIC3204_AISR3_BDIV_ADC;
+	} else if (bclk_src == AIC3204_AISR3_BDIV_DAC_MOD) {
+		/* Currently listening to DAC... check that it's up */
+		if (adcs_up && !dacs_up)
+			/* No, but the ADCs are up; switch to those */
+			bclk_src = AIC3204_AISR3_BDIV_ADC_MOD;
+	} else if (bclk_src == AIC3204_AISR3_BDIV_ADC) {
+		/* Currently listening to ADC... check that it's up */
+		if (dacs_up && !adcs_up)
+			/* No, but the DACs are up; switch to those */
+			bclk_src = AIC3204_AISR3_BDIV_DAC;
+	} else if (bclk_src == AIC3204_AISR3_BDIV_ADC_MOD) {
+		/* Currently listening to ADC... check that it's up */
+		if (adcs_up && !dacs_up)
+			/* No, but the DACs are up; switch to those */
+			bclk_src = AIC3204_AISR3_BDIV_DAC_MOD;
+	}
+
+	dev_dbg(w->codec->dev, "%s: setting source 0x%02x\n",
+			__func__, bclk_src);
+
+	snd_soc_update_bits(w->codec, AIC3204_AISR3,
+			AIC3204_AISR3_BDIV, bclk_src);
+	return 0;
+}
+
+/*
+ * Event handler for audio interface WCLK; checks the state of the ADCs and
+ * DACs and switches the audio interface to the presently active clock.
+ */
+static int aic3204_aif_wclk_event(struct snd_soc_dapm_widget *w,
+			 struct snd_kcontrol *kcontrol, int event) {
+	u8 wclk_src;
+	u8 adcs_up;
+	u8 dacs_up;
+	/* Determine the current source */
+	int reg = snd_soc_read(w->codec, AIC3204_AISR1);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	reg &= AIC3204_AISR1_WCLK;
+
+	if (reg == AIC3204_AISR1_WCLK_IN)
+		/* WCLK is an input, not our concirn */
+		return 0;
+
+	reg = snd_soc_read(w->codec, AIC3204_AISR6);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	wclk_src = reg & AIC3204_AISR6_WCLKOUT;
+
+	/*
+	 * These registers are not manipulated by us, so we must read them from
+	 * the CODEC directly.
+	 */
+	reg = aic3204_read(w->codec, AIC3204_ADCF, &adcs_up);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	adcs_up &= (AIC3204_ADCF_LEFT_UP | AIC3204_ADCF_RIGHT_UP);
+
+	reg = aic3204_read(w->codec, AIC3204_DACF1, &dacs_up);
+	if (reg < 0) {
+		printk(KERN_WARNING "%s: read returned %d\n", __func__, reg);
+		return reg;
+	}
+	dacs_up &= (AIC3204_DACF1_LEFT_UP | AIC3204_DACF1_RIGHT_UP);
+
+	dev_dbg(w->codec->dev, "%s: WCLK source=0x%02x, event=%d, "
+			"dacf1=0x%02x, adcf=0x%02x\n", __func__, wclk_src,
+			event, dacs_up, adcs_up);
+
+	/* What are we set to now? */
+	if (wclk_src == AIC3204_AISR6_WCLKOUT_DAC) {
+		/* Currently listening to DAC... check that it's up */
+		if (adcs_up && !dacs_up)
+			/* No, but the ADCs are up; switch to those */
+			wclk_src = AIC3204_AISR6_WCLKOUT_ADC;
+	} else if (wclk_src == AIC3204_AISR6_WCLKOUT_ADC) {
+		/* Currently listening to ADC... check that it's up */
+		if (dacs_up && !adcs_up)
+			/* No, but the DACs are up; switch to those */
+			wclk_src = AIC3204_AISR6_WCLKOUT_DAC;
+	}
+
+	dev_dbg(w->codec->dev, "%s: setting source 0x%02x\n",
+			__func__, wclk_src);
+
+	snd_soc_update_bits(w->codec, AIC3204_AISR6,
+			AIC3204_AISR6_WCLKOUT, wclk_src);
+	return 0;
+}
+
+/*
+ * For MICPGA inputs; inputs may either be disconnected, or connected via one
+ * of three resistances.
+ */
+static const char *aic3204_micpga_input_mux[] = {
+	"not-connected", "10k", "20k", "40k"
+};
+
+static struct soc_enum aic3204_enum_in1l_lmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGAPROUTE,
+				6, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in2l_lmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGAPROUTE,
+				4, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in3l_lmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGAPROUTE,
+				2, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in1r_lmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGAPROUTE,
+				0, 4, aic3204_micpga_input_mux);
+
+static struct soc_enum aic3204_enum_cm1l_lmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGANROUTE,
+				6, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in2r_lmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGANROUTE,
+				4, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in3r_lmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGANROUTE,
+				2, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_cm2l_lmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_LMICPGANROUTE,
+				0, 4, aic3204_micpga_input_mux);
+
+static struct soc_enum aic3204_enum_in1r_rmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGAPROUTE,
+				6, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in2r_rmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGAPROUTE,
+				4, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in3r_rmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGAPROUTE,
+				2, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in2l_rmicpgap =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGAPROUTE,
+				0, 4, aic3204_micpga_input_mux);
+
+static struct soc_enum aic3204_enum_cm1r_rmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGANROUTE,
+				6, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in1l_rmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGANROUTE,
+				4, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_in3l_rmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGANROUTE,
+				2, 4, aic3204_micpga_input_mux);
+static struct soc_enum aic3204_enum_cm2r_rmicpgan =
+			SOC_ENUM_SINGLE(AIC3204_RMICPGANROUTE,
+				0, 4, aic3204_micpga_input_mux);
+
+/*
+ * MICBIAS Voltages; The exact voltage depends on the common mode voltage
+ * setting...
+ *
+ *		CM=0.75V	CM=0.9V
+ *	Low	1.04V		1.25V
+ *	Medium	1.425V		1.7V
+ *	High	2.075V		2.5V
+ *	V+	Connects to power supply directly in both cases.
+ */
+static const char *aic3204_micbias_voltages[] = {
+	"Low", "Med", "High", "V+"
+};
+static struct soc_enum aic3204_enum_micbias_voltage =
+			SOC_ENUM_SINGLE(AIC3204_MICBIAS,
+				4, 4, aic3204_micbias_voltages);
+
+/*
+ * MICBIAS Voltage Source
+ */
+static const char *aic3204_micbias_srcs[] = {
+	"AVDD", "LDOIN"
+};
+static struct soc_enum aic3204_enum_micbias_src =
+			SOC_ENUM_SINGLE(AIC3204_MICBIAS,
+				3, 2, aic3204_micbias_srcs);
+
+/*
+ * Left DAC Data Source
+ */
+static const char *aic3204_ldac_srcs[] = {
+	"disabled", "left channel", "right channel", "mix"
+};
+static struct soc_enum aic3204_enum_ldac_src =
+			SOC_ENUM_SINGLE(AIC3204_DACS1,
+				4, 4, aic3204_ldac_srcs);
+
+/*
+ * Right DAC Data Source
+ */
+static const char *aic3204_rdac_srcs[] = {
+	"disabled", "right channel", "left channel", "mix"
+};
+static struct soc_enum aic3204_enum_rdac_src =
+			SOC_ENUM_SINGLE(AIC3204_DACS1,
+				2, 4, aic3204_rdac_srcs);
+
+/*
+ * DAC digital volumes. From -63.5 to +24 dB in 0.5 dB steps.
+ * Does not mute control.
+ */
+static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
+/*
+ * ADC gain volumes. From -12dB to 20 dB in 0.5dB steps.
+ * Does not mute control.
+ */
+static DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 50, 0);
+#if 0
+/*
+ * ADC Fine gain volumes. From -0.4 to 0 dB in 0.1dB steps
+ * Does not mute control.
+ */
+static DECLARE_TLV_DB_SCALE(adc_fine_tlv, -40, 10, 0);
+#endif
+/*
+ * Output driver stage volumes; -6dB through to +29dB in 1dB steps
+ * Does not mute control.
+ */
+static DECLARE_TLV_DB_SCALE(output_stage_tlv, -600, 100, 0);
+/*
+ * MICPGA volumes; 0dB through to +47.5dB in 0.5dB steps.
+ * Does not mute control
+ */
+static DECLARE_TLV_DB_SCALE(micpga_tlv, 0, 50, 0);
+
+static const struct snd_kcontrol_new aic3204_snd_controls[] = {
+	/* Output */
+
+	/*
+	 * Note regarding SOC_DOUBLE_R_SX_TLV...
+	 *
+	 * This is a bit misleading; xshift refers to the bit one bit *past*
+	 * the most significant bit.  Or at least that's what it appears to be
+	 * doing the math.  Mask needs to select the last 6 bits; which is the
+	 * signed bitfield specifiying the gain in dB.
+	 */
+	SOC_DOUBLE_R_SX_TLV("Headphone Output Volume",
+			 AIC3204_HPLGAIN, AIC3204_HPRGAIN,
+			 6, -6, 29, output_stage_tlv),
+	SOC_DOUBLE_R("Headphone Output Playback Switch",
+		AIC3204_HPLGAIN, AIC3204_HPRGAIN,
+		AIC3204_HPLGAIN_MUTE_SHIFT, 0x01, 1),
+	SOC_DOUBLE_R_SX_TLV("Line Output Playback Volume",
+			 AIC3204_LOLGAIN, AIC3204_LORGAIN,
+			 6, -6, 29, output_stage_tlv),
+	SOC_DOUBLE_R("Line Output Playback Switch", AIC3204_LOLGAIN,
+			AIC3204_LORGAIN, AIC3204_LOLGAIN_MUTE_SHIFT, 0x01, 1),
+	SOC_DOUBLE_R_SX_TLV("PCM Playback Volume",
+			 AIC3204_LDACVOL, AIC3204_RDACVOL,
+			 8, -127, 48, dac_tlv),
+	SOC_DOUBLE("PCM Playback Switch", AIC3204_DACS2,
+			AIC3204_DACS2_LEFT_MUTE_SHIFT,
+			AIC3204_DACS2_RIGHT_MUTE_SHIFT, 0x01, 1),
+	SOC_DOUBLE_R_SX_TLV("Mixer Amplifier Volume",
+			 AIC3204_MALGAIN, AIC3204_MARGAIN,
+			 6, -6, 29, output_stage_tlv),
+
+	/* DAC Options */
+	SOC_ENUM("Left Playback Source", aic3204_enum_ldac_src),
+	SOC_ENUM("Right Playback Source", aic3204_enum_rdac_src),
+	SOC_SINGLE("Differential Output Switch", AIC3204_DACS2,
+			AIC3204_DACS2_RMOD_INV_SHIFT, 1, 0),
+
+	/* MICPGA Options */
+	SOC_DOUBLE_R_TLV("MICPGA Capture Volume",
+			 AIC3204_LMICPGAVOL, AIC3204_RMICPGAVOL,
+			 0, 95, 0, micpga_tlv),
+	SOC_DOUBLE_R("MICPGA Capture Switch",
+			AIC3204_LMICPGAVOL, AIC3204_RMICPGAVOL, 7, 0x1, 1),
+
+	/* MICBIAS Options */
+	SOC_SINGLE("MICBIAS Enable", AIC3204_MICBIAS, 6, 0x1, 0),
+	SOC_ENUM("MICBIAS Level", aic3204_enum_micbias_voltage),
+	SOC_ENUM("MICBIAS Source", aic3204_enum_micbias_src),
+
+	/* ADC */
+	SOC_DOUBLE_R_SX_TLV("PCM Capture Volume",
+			 AIC3204_LADCVOL, AIC3204_RADCVOL,
+			 7, -24, 40, adc_tlv),
+	SOC_DOUBLE("PCM Capture Switch", AIC3204_ADCFINE, 7, 3, 0x01, 1),
+
+	/* Driver/Amplifier Selection -- DAPM should handle this! */
+	SOC_DOUBLE("HP Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_HPL_UP_SHIFT,
+			AIC3204_OUTDRV_HPR_UP_SHIFT, 0x1, 0),
+	SOC_DOUBLE("LO Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_LOL_UP_SHIFT,
+			AIC3204_OUTDRV_LOR_UP_SHIFT, 0x1, 0),
+	SOC_DOUBLE("MA Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_MAL_UP_SHIFT,
+			AIC3204_OUTDRV_MAR_UP_SHIFT, 0x1, 0),
+};
+
+/* Driver/Amplifier Selection */
+static const struct snd_kcontrol_new aic3204_hpl_switch =
+	SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_HPL_UP_SHIFT, 0x1, 0);
+static const struct snd_kcontrol_new aic3204_hpr_switch =
+	SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_HPR_UP_SHIFT, 0x1, 0);
+static const struct snd_kcontrol_new aic3204_lol_switch =
+	SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_LOL_UP_SHIFT, 0x1, 0);
+static const struct snd_kcontrol_new aic3204_lor_switch =
+	SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_LOR_UP_SHIFT, 0x1, 0);
+static const struct snd_kcontrol_new aic3204_mal_switch =
+	SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_MAL_UP_SHIFT, 0x1, 0);
+static const struct snd_kcontrol_new aic3204_mar_switch =
+	SOC_DAPM_SINGLE("Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_MAR_UP_SHIFT, 0x1, 0);
+
+/* Line Output Left Driver Inputs */
+static const struct snd_kcontrol_new aic3204_lol_in_controls[] = {
+	SOC_DAPM_SINGLE("LOR Switch", AIC3204_LOLROUTE,
+			AIC3204_LOLROUTE_LOR_SHIFT, 1, 0),
+	SOC_DAPM_SINGLE("MAL Switch", AIC3204_LOLROUTE,
+			AIC3204_LOLROUTE_MAL_SHIFT, 1, 0),
+	SOC_DAPM_SINGLE("LDAC+ Switch", AIC3204_LOLROUTE,
+			AIC3204_LOLROUTE_LDACP_SHIFT, 1, 0),
+	SOC_DAPM_SINGLE("RDAC- Switch", AIC3204_LOLROUTE,
+			AIC3204_LOLROUTE_RDACN_SHIFT, 1, 0),
+};
+
+/* Line Output Right Driver Inputs */
+static const struct snd_kcontrol_new aic3204_lor_in_controls[] = {
+	SOC_DAPM_SINGLE("MAR Switch", AIC3204_LORROUTE,
+			AIC3204_LORROUTE_MAR_SHIFT, 1, 0),
+	SOC_DAPM_SINGLE("RDAC+ Switch", AIC3204_LORROUTE,
+			AIC3204_LORROUTE_RDACP_SHIFT, 1, 0),
+};
+
+/* Headphone Output Left Driver Inputs */
+static const struct snd_kcontrol_new aic3204_hpl_in_controls[] = {
+	SOC_DAPM_SINGLE("MAR Switch", AIC3204_HPLROUTE,
+			AIC3204_HPLROUTE_MAR_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("MAL Switch", AIC3204_HPLROUTE,
+			AIC3204_HPLROUTE_MAL_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("IN1L Switch", AIC3204_HPLROUTE,
+			AIC3204_HPLROUTE_IN1L_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("LDAC+ Switch", AIC3204_HPLROUTE,
+			AIC3204_HPLROUTE_LDACP_SHIFT, 0x1, 0),
+};
+
+/* Headphone Output Right Driver Inputs */
+static const struct snd_kcontrol_new aic3204_hpr_in_controls[] = {
+	SOC_DAPM_SINGLE("HPL Switch", AIC3204_HPRROUTE,
+			AIC3204_HPRROUTE_HPL_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("MAR Switch", AIC3204_HPRROUTE,
+			AIC3204_HPRROUTE_MAR_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("IN1R Switch", AIC3204_HPRROUTE,
+			AIC3204_HPRROUTE_IN1R_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("RDAC+ Switch", AIC3204_HPRROUTE,
+			AIC3204_HPRROUTE_RDACP_SHIFT, 0x1, 0),
+	SOC_DAPM_SINGLE("LDAC- Switch", AIC3204_HPRROUTE,
+			AIC3204_HPRROUTE_LDACN_SHIFT, 0x1, 0),
+};
+
+static const struct snd_kcontrol_new aic3204_lmicpgap_in_controls[] = {
+	SOC_DAPM_ENUM("IN1L Switch", aic3204_enum_in1l_lmicpgap),
+	SOC_DAPM_ENUM("IN2L Switch", aic3204_enum_in2l_lmicpgap),
+	SOC_DAPM_ENUM("IN3L Switch", aic3204_enum_in3l_lmicpgap),
+	SOC_DAPM_ENUM("IN1R Switch", aic3204_enum_in1r_lmicpgap),
+};
+
+static const struct snd_kcontrol_new aic3204_lmicpgan_in_controls[] = {
+	SOC_DAPM_ENUM("CM1L Switch", aic3204_enum_cm1l_lmicpgan),
+	SOC_DAPM_ENUM("IN2R Switch", aic3204_enum_in2r_lmicpgan),
+	SOC_DAPM_ENUM("IN3R Switch", aic3204_enum_in3r_lmicpgan),
+	SOC_DAPM_ENUM("CM2L Switch", aic3204_enum_cm2l_lmicpgan),
+};
+
+static const struct snd_kcontrol_new aic3204_rmicpgap_in_controls[] = {
+	SOC_DAPM_ENUM("IN1R Switch", aic3204_enum_in1r_rmicpgap),
+	SOC_DAPM_ENUM("IN2R Switch", aic3204_enum_in2r_rmicpgap),
+	SOC_DAPM_ENUM("IN3R Switch", aic3204_enum_in3r_rmicpgap),
+	SOC_DAPM_ENUM("IN2L Switch", aic3204_enum_in2l_rmicpgap),
+};
+
+static const struct snd_kcontrol_new aic3204_rmicpgan_in_controls[] = {
+	SOC_DAPM_ENUM("CM1R Switch", aic3204_enum_cm1r_rmicpgan),
+	SOC_DAPM_ENUM("IN1L Switch", aic3204_enum_in1l_rmicpgan),
+	SOC_DAPM_ENUM("IN3L Switch", aic3204_enum_in3l_rmicpgan),
+	SOC_DAPM_ENUM("CM2R Switch", aic3204_enum_cm2r_rmicpgan),
+};
+
+static const struct snd_soc_dapm_widget aic3204_dapm_widgets[] = {
+	/* Driver/Amplifier Selection */
+	SND_SOC_DAPM_SWITCH("HPL Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_HPL_UP_SHIFT, 0,
+			&aic3204_hpl_switch),
+	SND_SOC_DAPM_SWITCH("HPR Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_HPR_UP_SHIFT, 0,
+			&aic3204_hpr_switch),
+	SND_SOC_DAPM_SWITCH("LOL Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_LOL_UP_SHIFT, 0,
+			&aic3204_lol_switch),
+	SND_SOC_DAPM_SWITCH("LOR Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_LOR_UP_SHIFT, 0,
+			&aic3204_lor_switch),
+	SND_SOC_DAPM_SWITCH("MAL Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_MAL_UP_SHIFT, 0,
+			&aic3204_mal_switch),
+	SND_SOC_DAPM_SWITCH("MAR Playback Switch", AIC3204_OUTDRV,
+			AIC3204_OUTDRV_MAR_UP_SHIFT, 0,
+			&aic3204_mar_switch),
+
+	/* Line Output Driver Inputs */
+	SND_SOC_DAPM_MIXER("Left Line Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_lol_in_controls,
+			ARRAY_SIZE(aic3204_lol_in_controls)),
+	SND_SOC_DAPM_MIXER("Right Line Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_lor_in_controls,
+			ARRAY_SIZE(aic3204_lor_in_controls)),
+
+	/* Headphone Output Driver Inputs */
+	SND_SOC_DAPM_MIXER("Left Headphone Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_hpl_in_controls,
+			ARRAY_SIZE(aic3204_hpl_in_controls)),
+	SND_SOC_DAPM_MIXER("Right Headphone Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_hpr_in_controls,
+			ARRAY_SIZE(aic3204_hpr_in_controls)),
+
+	/* DACs, ADCs and audio interfaces */
+	SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC3204_DACS1,
+			AIC3204_DACS1_LDAC_UP_SHIFT, 0),
+	SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC3204_DACS1,
+			AIC3204_DACS1_RDAC_UP_SHIFT, 0),
+	SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC3204_ADCS,
+			AIC3204_ADCS_RADC_UP_SHIFT, 0),
+	SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC3204_ADCS,
+			AIC3204_ADCS_RADC_UP_SHIFT, 0),
+	SND_SOC_DAPM_AIF_IN("Left Data In", "Left Playback",
+			0, SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_AIF_IN("Right Data In", "Right Playback",
+			1, SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_AIF_OUT("Left Data Out", "Left Capture",
+			0, SND_SOC_NOPM, 0, 0),
+	SND_SOC_DAPM_AIF_OUT("Right Data Out", "Right Capture",
+			1, SND_SOC_NOPM, 0, 0),
+
+	/* System clock sources */
+	SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("BCLK", AIC3204_CLK12,
+			AIC3204_CLK12_BCLK_STATE_SHIFT, 0,
+			aic3204_aif_bclk_event,
+			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+	SND_SOC_DAPM_SUPPLY("WCLK", SND_SOC_NOPM, 0, 0,
+			aic3204_aif_wclk_event,
+			SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
+	SND_SOC_DAPM_SUPPLY("GPIO", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("DIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("PLL_CLK", AIC3204_CLK2,
+			AIC3204_CLK2_PLL_SHIFT, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("CODEC_CLKIN", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("DAC_CLK", AIC3204_CLK6,
+			AIC3204_CLK6_NDAC_STATE_SHIFT, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("DAC_MOD_CLK", AIC3204_CLK7,
+			AIC3204_CLK7_MDAC_STATE_SHIFT, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("ADC_CLK", AIC3204_CLK8,
+			AIC3204_CLK8_NADC_STATE_SHIFT, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("ADC_MOD_CLK", AIC3204_CLK9,
+			AIC3204_CLK9_MADC_STATE_SHIFT, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("DAC_FS", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_SUPPLY("ADC_FS", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+	/* MICPGA Input Sources */
+	SND_SOC_DAPM_MIXER("Left MICPGA+ Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_lmicpgap_in_controls,
+			ARRAY_SIZE(aic3204_lmicpgap_in_controls)),
+	SND_SOC_DAPM_MIXER("Left MICPGA- Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_lmicpgan_in_controls,
+			ARRAY_SIZE(aic3204_lmicpgan_in_controls)),
+	SND_SOC_DAPM_MIXER("Right MICPGA+ Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_rmicpgap_in_controls,
+			ARRAY_SIZE(aic3204_rmicpgap_in_controls)),
+	SND_SOC_DAPM_MIXER("Right MICPGA- Output Mixer", SND_SOC_NOPM, 0, 0,
+			aic3204_rmicpgan_in_controls,
+			ARRAY_SIZE(aic3204_rmicpgan_in_controls)),
+	SND_SOC_DAPM_PGA("Left MICPGA", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("Right MICPGA", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_MICBIAS("Mic Bias", AIC3204_MICBIAS, 6, 0),
+
+	/* Bypass PGAs */
+	SND_SOC_DAPM_PGA("IN1L Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
+	SND_SOC_DAPM_PGA("IN1R Bypass PGA", SND_SOC_NOPM, 0, 0, NULL, 0),
+
+	/* Input Pins */
+	SND_SOC_DAPM_INPUT("IN1L"),
+	SND_SOC_DAPM_INPUT("IN1R"),
+	SND_SOC_DAPM_INPUT("IN2L"),
+	SND_SOC_DAPM_INPUT("IN2R"),
+	SND_SOC_DAPM_INPUT("IN3L"),
+	SND_SOC_DAPM_INPUT("IN3R"),
+
+	/* Output Pins */
+	SND_SOC_DAPM_OUTPUT("LOL"),
+	SND_SOC_DAPM_OUTPUT("LOR"),
+	SND_SOC_DAPM_OUTPUT("HPL"),
+	SND_SOC_DAPM_OUTPUT("HPR"),
+
+	/* Common-mode pins */
+	SND_SOC_DAPM_VMID("CM1L"),
+	SND_SOC_DAPM_VMID("CM1R"),
+	SND_SOC_DAPM_VMID("CM2L"),
+	SND_SOC_DAPM_VMID("CM2R"),
+};
+
+static const struct snd_soc_dapm_route intercon[] = {
+	/* Clock Signals and routing */
+	{"PLL_CLK", NULL, "MCLK", aic3204_check_pll_clk_src},
+	{"PLL_CLK", NULL, "BCLK", aic3204_check_pll_clk_src},
+	{"PLL_CLK", NULL, "GPIO", aic3204_check_pll_clk_src},
+	{"PLL_CLK", NULL, "DIN", aic3204_check_pll_clk_src},
+	{"CODEC_CLKIN", NULL, "MCLK", aic3204_check_codec_clk_src},
+	{"CODEC_CLKIN", NULL, "BCLK", aic3204_check_codec_clk_src},
+	{"CODEC_CLKIN", NULL, "GPIO", aic3204_check_codec_clk_src},
+	{"CODEC_CLKIN", NULL, "PLL_CLK", aic3204_check_codec_clk_src},
+	{"DAC_CLK", NULL, "CODEC_CLKIN"},
+	{"DAC_MOD_CLK", NULL, "DAC_CLK"},
+	{"DAC_FS", NULL, "DAC_MOD_CLK"},
+	{"ADC_CLK", NULL, "CODEC_CLKIN"},
+	{"ADC_MOD_CLK", NULL, "ADC_CLK"},
+	{"ADC_FS", NULL, "ADC_MOD_CLK"},
+	{"BCLK", NULL, "DAC_CLK", aic3204_check_bclk_src},
+	{"BCLK", NULL, "DAC_MOD_CLK", aic3204_check_bclk_src},
+	{"BCLK", NULL, "ADC_CLK", aic3204_check_bclk_src},
+	{"BCLK", NULL, "ADC_MOD_CLK", aic3204_check_bclk_src},
+	{"WCLK", NULL, "DAC_FS", aic3204_check_wclk_src},
+	{"WCLK", NULL, "ADC_FS", aic3204_check_wclk_src},
+
+	/* Clock sinks */
+	{"Left DAC", NULL, "DAC_MOD_CLK"},
+	{"Right DAC", NULL, "DAC_MOD_CLK"},
+	{"Left ADC", NULL, "ADC_MOD_CLK"},
+	{"Right ADC", NULL, "ADC_MOD_CLK"},
+	{"Left Data Out", NULL, "BCLK", aic3204_check_bclk_is_output},
+	{"Right Data Out", NULL, "BCLK", aic3204_check_bclk_is_output},
+	{"Left Data Out", NULL, "WCLK", aic3204_check_wclk_is_output},
+	{"Right Data Out", NULL, "WCLK", aic3204_check_wclk_is_output},
+	{"Left Data In", NULL, "BCLK", aic3204_check_bclk_is_output},
+	{"Right Data In", NULL, "BCLK", aic3204_check_bclk_is_output},
+	{"Left Data In", NULL, "WCLK", aic3204_check_wclk_is_output},
+	{"Right Data In", NULL, "WCLK", aic3204_check_wclk_is_output},
+
+	/* Data Connections */
+	{"Left Data Out", NULL, "Left ADC"},
+	{"Right Data Out", NULL, "Right ADC"},
+	{"Left DAC", NULL, "Left Data In"},
+	{"Right DAC", NULL, "Right Data In"},
+
+	/* Line Output */
+	{"Left Line Output Mixer", "LOR Switch", "Right Line Output Mixer"},
+	{"Left Line Output Mixer", "MAL Switch", "Left MICPGA"},
+	{"Left Line Output Mixer", "LDAC+ Switch", "Left DAC"},
+	{"Left Line Output Mixer", "RDAC- Switch", "Right DAC"},
+	{"Right Line Output Mixer", "MAR Switch", "Right MICPGA"},
+	{"Right Line Output Mixer", "RDAC+ Switch", "Right DAC"},
+	{"LOL", "LOL Playback Switch", "Left Line Output Mixer"},
+	{"LOR", "LOR Playback Switch", "Right Line Output Mixer"},
+
+	/* Headphone Output */
+	{"Left Headphone Output Mixer", "MAR Switch", "Right MICPGA"},
+	{"Left Headphone Output Mixer", "MAL Switch", "Left MICPGA"},
+	{"Left Headphone Output Mixer", "IN1L Switch", "IN1L Bypass PGA"},
+	{"Left Headphone Output Mixer", "LDAC+ Switch", "Left DAC"},
+	{"Right Headphone Output Mixer", "HPL Switch",
+		"Left Headphone Output Mixer"},
+	{"Right Headphone Output Mixer", "MAR Switch", "Right MICPGA"},
+	{"Right Headphone Output Mixer", "IN1R Switch", "IN1R Bypass PGA"},
+	{"Right Headphone Output Mixer", "RDAC+ Switch", "Right DAC"},
+	{"Right Headphone Output Mixer", "LDAC- Switch", "Left DAC"},
+	{"HPL", "HPL Playback Switch", "Left Headphone Output Mixer"},
+	{"HPR", "HPR Playback Switch", "Right Headphone Output Mixer"},
+
+	/* MICPGA Input */
+	{"Left MICPGA+ Output Mixer", "IN1L Switch", "IN1L"},
+	{"Left MICPGA+ Output Mixer", "IN2L Switch", "IN2L"},
+	{"Left MICPGA+ Output Mixer", "IN3L Switch", "IN3L"},
+	{"Left MICPGA+ Output Mixer", "IN1R Switch", "IN1R"},
+	{"Left MICPGA- Output Mixer", "CM1L Switch", "CM1L"},
+	{"Left MICPGA- Output Mixer", "IN2R Switch", "IN2R"},
+	{"Left MICPGA- Output Mixer", "IN3R Switch", "IN3R"},
+	{"Left MICPGA- Output Mixer", "CM2L Switch", "CM2L"},
+	{"Right MICPGA+ Output Mixer", "IN1R Switch", "IN1R"},
+	{"Right MICPGA+ Output Mixer", "IN2R Switch", "IN2R"},
+	{"Right MICPGA+ Output Mixer", "IN3R Switch", "IN3R"},
+	{"Right MICPGA+ Output Mixer", "IN2L Switch", "IN2L"},
+	{"Right MICPGA- Output Mixer", "CM1R Switch", "CM1R"},
+	{"Right MICPGA- Output Mixer", "IN1L Switch", "IN1L"},
+	{"Right MICPGA- Output Mixer", "IN3L Switch", "IN3L"},
+	{"Right MICPGA- Output Mixer", "CM2R Switch", "CM2R"},
+	{"Left MICPGA", "MAL Playback Switch", "Left MICPGA+ Output Mixer"},
+	{"Right MICPGA", "MAR Playback Switch", "Right MICPGA+ Output Mixer"},
+	{"Left MICPGA", "MAL Playback Switch", "Left MICPGA- Output Mixer"},
+	{"Right MICPGA", "MAR Playback Switch", "Right MICPGA- Output Mixer"},
+
+	/* ADC Input */
+	{"Left ADC", NULL, "Left MICPGA"},
+	{"Right ADC", NULL, "Right MICPGA"},
+};
+
+static int aic3204_add_widgets(struct snd_soc_codec *codec)
+{
+	snd_soc_dapm_new_controls(codec, aic3204_dapm_widgets,
+				  ARRAY_SIZE(aic3204_dapm_widgets));
+
+	/* set up audio path interconnects */
+	snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
+	return 0;
+}
+
+static int aic3204_hw_params(struct snd_pcm_substream *substream,
+			   struct snd_pcm_hw_params *params,
+			   struct snd_soc_dai *dai)
+{
+	struct snd_soc_pcm_runtime *rtd = substream->private_data;
+	struct snd_soc_device *socdev = rtd->socdev;
+	struct snd_soc_codec *codec = socdev->card->codec;
+	struct aic3204_priv *aic3204 = snd_soc_codec_get_drvdata(codec);
+	int dac_clk = 0, bit_clk = 0;
+	int codec_clk = 0, bypass_pll = 0, last_clk = 0, last_error = 0;
+	u8 data = 0, ndac = 0, mdac = 0, bdiv = 1;
+	u8 pll_p = 1, pll_r = 1, pll_j = 1;
+	u16 pll_d = 0;
+
+	int this_clk = 0, this_error = 0;
+	unsigned int this_abs_error;
+	u8 j, this_ndac;
+	u16 d;
+
+	/* Determine the DAC clock and bit clock needed */
+	dac_clk = aic3204->pdata.osr * params_rate(params);
+	bit_clk = params_rate(params) * params_channels(params);
+
+	/*
+	 * Select data word length.
+	 * Note that the number of bits per frame used
+	 * to determine BDIV is double the number of bits per sample, as there
+	 * are two samples per frame.
+	 */
+	switch (params_format(params)) {
+	case SNDRV_PCM_FORMAT_S16_LE:
+		pr_debug("%s: Sample format 16 bits\n", __func__);
+		bit_clk *= 16;
+		data = AIC3204_AISR1_WL_16BITS;
+		break;
+	case SNDRV_PCM_FORMAT_S20_3LE:
+		pr_debug("%s: Sample format 20 bits\n", __func__);
+		bit_clk *= 32;
+		data = AIC3204_AISR1_WL_20BITS;
+		break;
+	case SNDRV_PCM_FORMAT_S24_LE:
+		pr_debug("%s: Sample format 24 bits\n", __func__);
+		bit_clk *= 40;
+		data = AIC3204_AISR1_WL_24BITS;
+		break;
+	case SNDRV_PCM_FORMAT_S32_LE:
+		pr_debug("%s: Sample format 32 bits\n", __func__);
+		bit_clk *= 48;
+		data = AIC3204_AISR1_WL_32BITS;
+		break;
+	}
+	snd_soc_update_bits(codec, AIC3204_AISR1, AIC3204_AISR1_WL, data);
+
+	pr_debug("%s: DAC Clock = %d Hz, Bit clock = %d Hz\n", __func__,
+			dac_clk, bit_clk);
+
+	/* Try to find a value for div which allows us to bypass the PLL and
+	 * generate CODEC_CLK directly. */
+	for (this_ndac = 128; this_ndac >= 1; this_ndac--) {
+		this_clk = aic3204->sysclk / this_ndac;
+
+		if (this_clk == dac_clk) {
+			pr_debug("%s: Scored exact match.  NDAC=%d; "
+					"DAC_CLK=%d\n",
+					__func__, this_ndac, this_clk);
+			bypass_pll = 1;
+			ndac =  this_ndac;
+			break;
+		}
+	}
+
+	if (bypass_pll) {
+		/* Select MCLK as CODEC_CLKIN */
+		aic3204_write(codec, AIC3204_CLK1, AIC3204_CLK1_CODECCLK_MCLK);
+		codec_clk = aic3204->sysclk;
+		goto setup_codec;
+	}
+
+	/*
+	 * Determine PLL Parameters... the input/output frequency ratio
+	 * of the PLL is given in the datasheet:
+	 *
+	 *   out   R * J * (D/10000)       J      D
+	 *   --- = ----------------- = R * - * -------
+	 *   in	          P                P    10000
+	 *
+	 * Limitations:
+	 * - R range: 1..4
+	 * - J range: 4..63
+	 * - D range: 0..9999
+	 * - P range: 1..8
+	 * - If D == 0;
+	 * 	512 kHz <= in / P <= 20 MHz
+	 *   else
+	 * 	10 MHz <= in / P <= 20 MHz
+	 *
+	 * We will try for 8* the target frequency; then use NDAC/NADC to divide
+	 * that down.  If we set P = 1, and R = 1; we simplify the solution.
+	 */
+	pll_p = 1;
+	pll_r = 1;
+	for (this_ndac = 1; this_ndac <= 128; this_ndac++) {
+		int ratio, init_ratio;
+
+		codec_clk = dac_clk * this_ndac;
+
+		/* Ensure maximum CODEC frequency is not exceeded */
+		if (codec_clk > 137000000)
+			continue;
+		if ((this_ndac % 2) && (codec_clk > 110000000))
+			continue;
+
+		/* Initial Fixed-point ratio ... this will be slightly lower */
+		init_ratio = codec_clk / (aic3204->sysclk / 10000);
+
+		pr_debug("%s: NDAC = %d, PLL J.D * 10000 = %d\n",
+				__func__, this_ndac, init_ratio);
+		if (init_ratio < 40000)
+			continue;
+		if (init_ratio > 639999)
+			continue;
+
+		for (ratio = init_ratio; (ratio < init_ratio + 10000)
+				&& (ratio < 639999); ratio++) {
+			j = ratio / 10000;
+			d = ratio % 10000;
+
+			this_clk = aic3204->sysclk / 10000;
+			this_clk *= (10000 * j) + d;
+			this_error = this_clk - codec_clk;
+			this_abs_error = abs(this_error);
+
+			if (this_abs_error > 1000)
+				continue;
+
+			pr_debug("%s: Fractional PLL search; "
+					"P=%d R=%d J=%d D=%04d => "
+					"(%d * %d) / 10000 => %d "
+					"(%d error) [NDAC=%d]\n",
+					__func__, pll_p, pll_r,
+					j, d, aic3204->sysclk,
+					ratio, this_clk, this_error,
+					this_ndac);
+			if (!last_clk || (this_abs_error < last_error)) {
+				last_clk = this_clk;
+				last_error = this_abs_error;
+				ndac = this_ndac;
+				pll_j = j;
+				pll_d = d;
+				/* Early finish for exact match */
+				if (!this_abs_error)
+					break;
+			}
+		}
+	}
+
+	/* If we still haven't found anything; bail out here! */
+	if (!last_clk)
+		goto fail;
+
+	pr_debug("%s: Best Output: %d (%d Hz Error)\n",
+			__func__, last_clk, last_error);
+	pr_debug("%s: setting up PLL: P=%d R=%d J.D=%d.%04d\n",
+			__func__, pll_p, pll_r, pll_j, pll_d);
+
+	codec_clk = last_clk;
+
+	aic3204_write(codec, AIC3204_CLK4, (pll_d >> AIC3204_CLK4_PLL_D_VSHIFT)
+			& AIC3204_CLK4_PLL_D);		/* PLL D[14:8] */
+	aic3204_write(codec, AIC3204_CLK5, pll_d & AIC3204_CLK5_PLL_D);
+							/* PLL D[7:0] */
+	aic3204_write(codec, AIC3204_CLK3, pll_j & AIC3204_CLK3_PLL_J);
+							/* PLL J */
+	aic3204_write(codec, AIC3204_CLK2,
+			(pll_r & AIC3204_CLK2_PLL_R)	/* PLL R */
+			| ((pll_p << AIC3204_CLK2_PLL_P_SHIFT)
+				& AIC3204_CLK2_PLL_P)
+							/* PLL P */
+			| AIC3204_CLK2_PLL_ON);	/* PLL on */
+
+	/* Select PLL as CODEC_CLKIN */
+	aic3204_write(codec, AIC3204_CLK1, AIC3204_CLK1_CODECCLK_PLL);
+
+setup_codec:
+	pr_debug("%s: CODEC CLK = %d => DAC CLK = %d\n",
+		__func__, codec_clk, codec_clk / ndac);
+	/* Calculate BDIV and NDAC */
+	mdac = codec_clk / (ndac * dac_clk);
+	if (!mdac)
+		mdac = 1;
+
+	bdiv = dac_clk / bit_clk;
+	if (!bdiv)
+		bdiv = 1;
+
+	/* Set AOSR and DOSR */
+	aic3204_write(codec, AIC3204_DOSR1,
+			(aic3204->pdata.osr >> AIC3204_DOSR1_MSB_VSHIFT)
+			& AIC3204_DOSR1_MSB);			/* DOSR[9:8] */
+	aic3204_write(codec, AIC3204_DOSR2, aic3204->pdata.osr
+			& AIC3204_DOSR2_LSB);			/* DOSR[7:0] */
+	aic3204_write(codec, AIC3204_AOSR, aic3204->pdata.osr);	/* AOSR */
+
+	pr_debug("%s: NDAC = %d\n", __func__, ndac);
+	/* Set NDAC to divider value */
+	aic3204_write(codec, AIC3204_CLK6, AIC3204_CLK6_NDAC_STATE_ON | ndac);
+	/* Set NADC to match NDAC */
+	aic3204_write(codec, AIC3204_CLK8, AIC3204_CLK8_NADC_STATE_ON | ndac);
+	/* Set MDAC and turn on */
+	aic3204_write(codec, AIC3204_CLK7, AIC3204_CLK7_MDAC_STATE_ON | mdac);
+	/* Use MDAC for MADC */
+	aic3204_write(codec, AIC3204_CLK9, AIC3204_CLK7_MDAC_STATE_ON | mdac);
+
+	/* Set BCLK and WCLK */
+	pr_debug("%s: Bit clock divider = %d\n", __func__, bdiv);
+	/* Turn on and set BCLK N divider */
+	aic3204_write(codec, AIC3204_CLK12, bdiv
+			| AIC3204_CLK12_BCLK_STATE_ON);
+
+	/*
+	 * Set BCLK and WCLK sources...
+	 *
+	 * Despite DAPM; this is still needed, as DAPM doesn't yet set the
+	 * source at the right time.
+	 *
+	 * TODO: See if we can change the order of initialisation so this
+	 * selection is made after bringing up the ADCs/DACs.  Alternative:
+	 * see if we can find out ahead of time which one to use.
+	 */
+	snd_soc_update_bits(codec, AIC3204_AISR3, AIC3204_AISR3_BDIV,
+			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+				? AIC3204_AISR3_BDIV_DAC
+				: AIC3204_AISR3_BDIV_ADC);
+	snd_soc_update_bits(codec, AIC3204_AISR6, AIC3204_AISR6_WCLKOUT,
+			(substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
+				? AIC3204_AISR6_WCLKOUT_DAC
+				: AIC3204_AISR6_WCLKOUT_ADC);
+	return 0;
+fail:
+	printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
+	return -EINVAL;
+}
+
+static int aic3204_mute(struct snd_soc_dai *dai, int mute)
+{
+	struct snd_soc_codec *codec = dai->codec;
+	u8 dacs2;
+
+	dacs2 = aic3204_read_reg_cache(codec, AIC3204_DACS2);
+
+	if (mute) {
+		dacs2	|= (1 << AIC3204_DACS2_LEFT_MUTE_SHIFT)
+			| (1 << AIC3204_DACS2_RIGHT_MUTE_SHIFT);
+	} else {
+		dacs2	&= ~((1 << AIC3204_DACS2_LEFT_MUTE_SHIFT)
+			| (1 << AIC3204_DACS2_RIGHT_MUTE_SHIFT));
+	}
+
+	aic3204_write(codec, AIC3204_DACS2, dacs2);	/* Unmute DAC */
+	return 0;
+}
+
+static int aic3204_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+				int clk_id, unsigned int freq, int dir)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	struct aic3204_priv *aic3204 = snd_soc_codec_get_drvdata(codec);
+
+	aic3204->sysclk = freq;
+	return 0;
+}
+
+static int aic3204_set_dai_fmt(struct snd_soc_dai *codec_dai,
+			     unsigned int fmt)
+{
+	struct snd_soc_codec *codec = codec_dai->codec;
+	u8 aisr1 = 0, aisr2 = 0, aisr3 = 0;
+
+	/* set master/slave audio interface */
+	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBM_CFM:
+		aisr1	|= AIC3204_AISR1_BCLK_OUT
+			| AIC3204_AISR1_WCLK_OUT;
+		break;
+	case SND_SOC_DAIFMT_CBM_CFS:
+		aisr1	|= AIC3204_AISR1_BCLK_OUT
+			| AIC3204_AISR1_WCLK_IN;
+		break;
+	case SND_SOC_DAIFMT_CBS_CFM:
+		aisr1	|= AIC3204_AISR1_BCLK_IN
+			| AIC3204_AISR1_WCLK_OUT;
+		break;
+	case SND_SOC_DAIFMT_CBS_CFS:
+		aisr1	|= AIC3204_AISR1_BCLK_IN
+			| AIC3204_AISR1_WCLK_IN;
+		break;
+	default:
+		printk(KERN_ERR "%s: Clock mode not supported "
+				"(fmt=0x%08x)\n", __func__, fmt);
+		return -EINVAL;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+	case SND_SOC_DAIFMT_I2S:
+		aisr1	|= AIC3204_AISR1_INT_I2S;
+		break;
+	case SND_SOC_DAIFMT_DSP_A:
+		aisr2 = 1;
+	case SND_SOC_DAIFMT_DSP_B:
+		aisr1	|= AIC3204_AISR1_INT_DSP;
+		break;
+	case SND_SOC_DAIFMT_RIGHT_J:
+		aisr1 |= AIC3204_AISR1_INT_RJF;
+		break;
+	case SND_SOC_DAIFMT_LEFT_J:
+		aisr1 |= AIC3204_AISR1_INT_LJF;
+		break;
+	default:
+		printk(KERN_ERR "%s: SSI mode not supported "
+				"(fmt=0x%08x)\n", __func__, fmt);
+		return -EINVAL;
+	}
+
+	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+	case SND_SOC_DAIFMT_NB_NF:
+		aisr3	|= AIC3204_AISR3_BCLKPOL_NOR;
+		break;
+	case SND_SOC_DAIFMT_IB_NF:
+		aisr3	|= AIC3204_AISR3_BCLKPOL_INV;
+		break;
+	default:
+		printk(KERN_ERR "%s: Clock inversion mode not "
+				"supported (fmt=0x%08x)\n", __func__, fmt);
+		return -EINVAL;
+	}
+
+	/* set iface */
+	aic3204_write(codec, AIC3204_AISR1, aisr1);
+	aic3204_write(codec, AIC3204_AISR2, aisr2);
+	aic3204_write(codec, AIC3204_AISR3, aisr3);
+
+	return 0;
+}
+
+#define AIC3204_RATES	SNDRV_PCM_RATE_8000_96000
+#define AIC3204_FORMATS	(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+			 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+static struct snd_soc_dai_ops aic3204_dai_ops = {
+	.hw_params	= aic3204_hw_params,
+	.digital_mute	= aic3204_mute,
+	.set_sysclk	= aic3204_set_dai_sysclk,
+	.set_fmt	= aic3204_set_dai_fmt,
+};
+
+struct snd_soc_dai aic3204_dai = {
+	.name = "tlv320aic3204",
+	.playback = {
+		.stream_name = "Playback",
+		.channels_min = 1,
+		.channels_max = 2,
+		.rates = AIC3204_RATES,
+		.formats = AIC3204_FORMATS,},
+	.capture = {
+		.stream_name = "Capture",
+		.channels_min = 1,
+		.channels_max = 2,
+		.rates = AIC3204_RATES,
+		.formats = AIC3204_FORMATS,},
+	.ops = &aic3204_dai_ops,
+};
+EXPORT_SYMBOL_GPL(aic3204_dai);
+
+static int aic3204_resume(struct platform_device *pdev)
+{
+	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+	struct snd_soc_codec *codec = socdev->card->codec;
+	int i;
+	u8 data[2];
+	u8 *cache = codec->reg_cache;
+
+	/* Sync reg_cache with the hardware */
+	for (i = 0; i < AIC3204_CACHEREGNUM; i++) {
+		data[0] = i;
+		data[1] = cache[i];
+		codec->hw_write(codec->control_data, data, 2);
+	}
+
+	return 0;
+}
+
+/*
+ * initialise the AIC3204 driver
+ * register the mixer and dsp interfaces with the kernel
+ */
+static int aic3204_init(struct snd_soc_codec *codec)
+{
+	mutex_init(&codec->mutex);
+	INIT_LIST_HEAD(&codec->dapm_widgets);
+	INIT_LIST_HEAD(&codec->dapm_paths);
+
+	codec->name = "tlv320aic3204";
+	codec->owner = THIS_MODULE;
+	codec->read = aic3204_read_reg_cache;
+	codec->write = aic3204_write;
+	codec->dai = &aic3204_dai;
+	codec->num_dai = 1;
+	codec->reg_cache_size = AIC3204_CACHEREGNUM;
+	codec->reg_cache = kmemdup(aic3204_default_reg_data,
+			AIC3204_CACHEREGNUM, GFP_KERNEL);
+	codec->readable_register = aic3204_reg_is_readable;
+	codec->display_register = aic3204_show_reg;
+	if (codec->reg_cache == NULL)
+		return -ENOMEM;
+
+	/* Reset the CODEC */
+	aic3204_write(codec, AIC3204_PAGE_SELECT, 0);
+	aic3204_write(codec, AIC3204_RESET, AIC3204_RESET_SOFT);
+
+	return 0;
+}
+
+static struct snd_soc_codec *aic3204_codec;
+
+static int aic3204_register(struct snd_soc_codec *codec)
+{
+	int ret;
+
+	ret = aic3204_init(codec);
+	if (ret < 0) {
+		dev_err(codec->dev, "Failed to initialise device\n");
+		return ret;
+	}
+
+	aic3204_codec = codec;
+
+	ret = snd_soc_register_codec(codec);
+	if (ret) {
+		dev_err(codec->dev, "Failed to register codec\n");
+		return ret;
+	}
+
+	ret = snd_soc_register_dai(&aic3204_dai);
+	if (ret) {
+		dev_err(codec->dev, "Failed to register dai\n");
+		snd_soc_unregister_codec(codec);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int aic3204_unregister(struct aic3204_priv *aic3204)
+{
+	snd_soc_unregister_dai(&aic3204_dai);
+	snd_soc_unregister_codec(&aic3204->codec);
+
+	if (aic3204->pdata.gpio_reset >= 0) {
+		gpio_set_value(aic3204->pdata.gpio_reset, 0);
+		gpio_free(aic3204->pdata.gpio_reset);
+	}
+	regulator_bulk_disable(ARRAY_SIZE(aic3204->supplies),
+			aic3204->supplies);
+	regulator_bulk_free(ARRAY_SIZE(aic3204->supplies), aic3204->supplies);
+
+	kfree(aic3204);
+	aic3204_codec = NULL;
+
+	return 0;
+}
+
+static int aic3204_i2c_probe(struct i2c_client *i2c,
+			   const struct i2c_device_id *id)
+{
+	struct snd_soc_codec *codec;
+	struct aic3204_priv *aic3204;
+	struct aic3204_pdata *pdata = i2c->dev.platform_data;
+	int ret, i;
+
+	aic3204 = kzalloc(sizeof(struct aic3204_priv), GFP_KERNEL);
+	if (aic3204 == NULL) {
+		dev_err(&i2c->dev, "failed to create private data\n");
+		return -ENOMEM;
+	}
+
+	codec = &aic3204->codec;
+	codec->dev = &i2c->dev;
+	snd_soc_codec_set_drvdata(codec, aic3204);
+	codec->control_data = i2c;
+	codec->hw_write = (hw_write_t) i2c_master_send;
+
+	i2c_set_clientdata(i2c, aic3204);
+
+	dev_dbg(&i2c->dev, "%s: platform data at %p\n",
+			__func__, pdata);
+	if (pdata)
+		memcpy(&aic3204->pdata, pdata, sizeof(struct aic3204_pdata));
+	else
+		memcpy(&aic3204->pdata, &aic3204_default_pdata,
+				sizeof(struct aic3204_pdata));
+
+	if (aic3204->pdata.gpio_reset >= 0) {
+		ret = gpio_request(aic3204->pdata.gpio_reset,
+				"tlv320aic3204 reset");
+		if (ret != 0)
+			goto err_gpio;
+		gpio_direction_output(aic3204->pdata.gpio_reset, 0);
+	}
+
+	for (i = 0; i < ARRAY_SIZE(aic3204->supplies); i++)
+		aic3204->supplies[i].supply = aic3204_supply_names[i];
+
+	ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3204->supplies),
+				 aic3204->supplies);
+	if (ret != 0) {
+		dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
+		goto err_get;
+	}
+
+	ret = regulator_bulk_enable(ARRAY_SIZE(aic3204->supplies),
+				    aic3204->supplies);
+	if (ret != 0) {
+		dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
+		goto err_enable;
+	}
+
+	if (aic3204->pdata.gpio_reset >= 0) {
+		udelay(1);
+		gpio_set_value(aic3204->pdata.gpio_reset, 1);
+	}
+
+	return aic3204_register(codec);
+
+err_enable:
+	regulator_bulk_free(ARRAY_SIZE(aic3204->supplies), aic3204->supplies);
+err_get:
+	if (aic3204->pdata.gpio_reset >= 0)
+		gpio_free(aic3204->pdata.gpio_reset);
+err_gpio:
+	kfree(aic3204);
+	return ret;
+}
+
+static int aic3204_i2c_remove(struct i2c_client *client)
+{
+	struct aic3204_priv *aic3204 = i2c_get_clientdata(client);
+
+	return aic3204_unregister(aic3204);
+}
+
+static const struct i2c_device_id aic3204_i2c_id[] = {
+	{ "tlv320aic3204", 0 },
+	{ }
+};
+MODULE_DEVICE_TABLE(i2c, aic3204_i2c_id);
+
+/* machine i2c codec control layer */
+static struct i2c_driver aic3204_i2c_driver = {
+	.driver = {
+		.name = "tlv320aic3204-i2c",
+		.owner = THIS_MODULE,
+	},
+	.probe	= aic3204_i2c_probe,
+	.remove = aic3204_i2c_remove,
+	.id_table = aic3204_i2c_id,
+};
+
+static inline void aic3204_i2c_init(void)
+{
+	int ret;
+
+	ret = i2c_add_driver(&aic3204_i2c_driver);
+	if (ret)
+		printk(KERN_ERR "%s: error regsitering i2c driver, %d\n",
+		       __func__, ret);
+}
+
+static inline void aic3204_i2c_exit(void)
+{
+	i2c_del_driver(&aic3204_i2c_driver);
+}
+
+static int aic3204_probe(struct platform_device *pdev)
+{
+	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+	struct aic3204_setup_data *setup;
+	struct snd_soc_codec *codec;
+	struct aic3204_priv *aic3204;
+	int ret = 0;
+
+	codec = aic3204_codec;
+	if (!codec) {
+		dev_err(&pdev->dev, "Codec not registered\n");
+		return -ENODEV;
+	}
+
+	socdev->card->codec = codec;
+	setup = socdev->codec_data;
+	aic3204 = snd_soc_codec_get_drvdata(codec);
+
+	dev_dbg(codec->dev, "%s: private data at %p\n",
+			__func__, aic3204);
+	/* Initialise the CODEC with the given settings */
+	/* Analogue Input Quick-Charge Power-Up delay */
+	ret = aic3204_write(codec, AIC3204_AIQC,
+			aic3204->pdata.ain_pwrup_delay);
+	if (ret)
+		return ret;
+
+	/* Analogue Reference Power-Up delay */
+	aic3204_write(codec, AIC3204_REFPU,
+			aic3204->pdata.ref_pwrup_delay);
+	if (ret)
+		return ret;
+
+	/* AVDD<->DVDD link */
+	snd_soc_update_bits(codec, AIC3204_POWER,
+			AIC3204_POWER_AVDD_DVDD_UNLINK,
+			aic3204->pdata.avdd_link_en ?
+			0 : AIC3204_POWER_AVDD_DVDD_UNLINK);
+
+	/* LDO enable, analogue blocks enable */
+	snd_soc_update_bits(codec, AIC3204_LDO,
+			AIC3204_LDO_ANALOG | AIC3204_LDO_AVDD_UP,
+			AIC3204_LDO_ANALOG_ENABLED |
+			(aic3204->pdata.ldo_en
+			  ? AIC3204_LDO_AVDD_UP : 0));
+
+	/* register pcms */
+	ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
+	if (ret < 0) {
+		printk(KERN_ERR "aic3204: failed to create pcms\n");
+		goto pcm_err;
+	}
+
+	snd_soc_add_controls(codec, aic3204_snd_controls,
+			ARRAY_SIZE(aic3204_snd_controls));
+
+	aic3204_add_widgets(codec);
+
+	return ret;
+
+pcm_err:
+	kfree(codec->reg_cache);
+	return ret;
+}
+
+static int aic3204_remove(struct platform_device *pdev)
+{
+	struct snd_soc_device *socdev = platform_get_drvdata(pdev);
+	struct snd_soc_codec *codec = socdev->card->codec;
+
+	snd_soc_free_pcms(socdev);
+	snd_soc_dapm_free(socdev);
+
+	kfree(codec->reg_cache);
+
+	return 0;
+}
+
+struct snd_soc_codec_device soc_codec_dev_aic3204 = {
+	.probe = aic3204_probe,
+	.remove = aic3204_remove,
+	.resume = aic3204_resume,
+};
+EXPORT_SYMBOL_GPL(soc_codec_dev_aic3204);
+
+static int __init aic3204_modinit(void)
+{
+	aic3204_i2c_init();
+
+	return 0;
+}
+module_init(aic3204_modinit);
+
+static void __exit aic3204_exit(void)
+{
+	aic3204_i2c_exit();
+}
+module_exit(aic3204_exit);
+
+MODULE_DESCRIPTION("ASoC TLV320AIC3204 codec driver");
+MODULE_AUTHOR("Jacques Electronics Pty Ltd");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/tlv320aic3204.h b/sound/soc/codecs/tlv320aic3204.h
new file mode 100644
index 0000000..8f9ee43
--- /dev/null
+++ b/sound/soc/codecs/tlv320aic3204.h
@@ -0,0 +1,1350 @@
+/*
+ * ALSA SoC TLV320AIC3204 codec driver
+ *
+ * Author:	Stuart Longland, <redhatter at gentoo.org>
+ * Copyright:	(C) 2010 Jacques Electronics, Pty, Ltd.
+ *
+ * Author:      Vladimir Barinov, <vbarinov at embeddedalley.com>
+ * Copyright:   (C) 2007 MontaVista Software, Inc., <source at mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _AIC3204_H
+#define _AIC3204_H
+
+/*
+ * The AIC3204's registers are divided into separate pages, the first page of
+ * every register is a "page select", which sets the current page being
+ * accessed.  For the purposes of simplicity; we shall consider all registers
+ * as being addressed by a 16-bit value, consisting of the page number as
+ * most-significant 9 bits, followed by the register number as given in the
+ * datasheet.
+ *
+ * The register access functions will look after page flipping from here.
+ */
+
+/*
+ * AIC3204 register space; 128 registers each page, we pages 0..127.  It's not
+ * clear from the datasheet exactly how many pages are in use... and it's a
+ * sparse register map!  Ideally, I'd like to just cache the pages that are
+ * needed, but the ALSA framework doesn't allow this easily.
+ *
+ * It does look as if up to and including page 70 is needed.  For now, we will
+ * cache up to page 128 however; as this ensures we get *everything*.
+ */
+#define AIC3204_CACHEREGNUM		(128*128)
+
+/* Page select register */
+#define AIC3204_PAGE_SELECT		0
+
+/* Register Page/Number => Address Mapping Macro */
+#define AIC3204_PGREG(page, reg)	(((page) << 7) | ((reg) & 0x7f))
+
+/* Software reset register */
+#define AIC3204_RESET			AIC3204_PGREG(0, 1)
+/* Perform software reset */
+#define AIC3204_RESET_SOFT		1
+
+/* Clock Setting Register 1, Multiplexers */
+#define AIC3204_CLK1			AIC3204_PGREG(0, 4)
+/* PLL Range Select: Low Range */
+#define AIC3204_CLK1_PLLRANGE_LOW	(0 << 6)
+/* PLL Range Select: High Range */
+#define AIC3204_CLK1_PLLRANGE_HIGH	(1 << 6)
+/* PLL Range Select Mask */
+#define AIC3204_CLK1_PLLRANGE		(1 << 6)
+/* PLL Input Clock Select: MCLK */
+#define AIC3204_CLK1_PLLSRC_MCLK	(0 << 2)
+/* PLL Input Clock Select: BCLK */
+#define AIC3204_CLK1_PLLSRC_BCLK	(1 << 2)
+/* PLL Input Clock Select: GPIO */
+#define AIC3204_CLK1_PLLSRC_GPIO	(2 << 2)
+/* PLL Input Clock Select: Data In */
+#define AIC3204_CLK1_PLLSRC_DIN		(3 << 2)
+/* PLL Input Clock Select Mask */
+#define AIC3204_CLK1_PLLSRC		(3 << 2)
+/* CODEC Clock Source Select: MCLK */
+#define AIC3204_CLK1_CODECCLK_MCLK	(0)
+/* CODEC Clock Source Select: BCLK */
+#define AIC3204_CLK1_CODECCLK_BCLK	(1)
+/* CODEC Clock Source Select: GPIO */
+#define AIC3204_CLK1_CODECCLK_GPIO	(2)
+/* CODEC Clock Source Select: PLL */
+#define AIC3204_CLK1_CODECCLK_PLL	(3)
+/* CODEC Clock Source Select Mask */
+#define AIC3204_CLK1_CODECCLK		(3)
+
+/* Clock Setting Register 2, PLL P & R Values */
+#define AIC3204_CLK2			AIC3204_PGREG(0, 5)
+/* PLL State: Powered Down */
+#define AIC3204_CLK2_PLL_OFF		(0 << 7)
+/* PLL State: Powered Up */
+#define AIC3204_CLK2_PLL_ON		(1 << 7)
+/* PLL State Mask */
+#define AIC3204_CLK2_PLL		(1 << 7)
+/* PLL State bitfield location */
+#define AIC3204_CLK2_PLL_SHIFT		(7)
+/* PLL P Divider value bitfield location */
+#define AIC3204_CLK2_PLL_P_SHIFT	(4)
+/* PLL P Divider value bitfield mask */
+#define AIC3204_CLK2_PLL_P		(7 << 4)
+/* PLL R Divider value bitfield location */
+#define AIC3204_CLK2_PLL_R_SHIFT	(0)
+/* PLL R Divider value bitfield mask */
+#define AIC3204_CLK2_PLL_R		(0xf)
+
+/* Clock Setting Register 3, PLL J Values */
+#define AIC3204_CLK3			AIC3204_PGREG(0, 6)
+/* PLL J Divider value bitfield location */
+#define AIC3204_CLK3_PLL_J_SHIFT	(0)
+/* PLL J Divider value bitfield mask */
+#define AIC3204_CLK3_PLL_J		(0x3f)
+
+/* Clock Setting Register 4, PLL D MSB */
+#define AIC3204_CLK4			AIC3204_PGREG(0, 7)
+/* PLL D most significant portion bitfield location */
+#define AIC3204_CLK4_PLL_D_SHIFT	(0)
+/* PLL D most significant portion bitfield mask */
+#define AIC3204_CLK4_PLL_D		(0x3f)
+/* PLL D most significant portion value shift */
+#define AIC3204_CLK4_PLL_D_VSHIFT	(8)
+
+/* Clock Setting Register 5, PLL D LSB */
+#define AIC3204_CLK5			AIC3204_PGREG(0, 8)
+/* PLL D least significant portion bitfield location */
+#define AIC3204_CLK5_PLL_D_SHIFT	(0)
+/* PLL D least significant portion bitfield mask */
+#define AIC3204_CLK5_PLL_D		(0xff)
+/* PLL D least significant portion value shift */
+#define AIC3204_CLK5_PLL_D_VSHIFT	(0)
+
+/* Clock Setting Register 6, NDAC Values */
+#define AIC3204_CLK6			AIC3204_PGREG(0, 11)
+/* NDAC State: Powered Down */
+#define AIC3204_CLK6_NDAC_STATE_OFF	(0 << 7)
+/* NDAC State: Powered Up */
+#define AIC3204_CLK6_NDAC_STATE_ON	(1 << 7)
+/* NDAC State Mask */
+#define AIC3204_CLK6_NDAC_STATE		(1 << 7)
+/* NDAC State bitfield location */
+#define AIC3204_CLK6_NDAC_STATE_SHIFT	(7)
+/* NDAC value bitfield location */
+#define AIC3204_CLK6_NDAC_SHIFT		(0)
+/* NDAC value bitfield mask */
+#define AIC3204_CLK6_NDAC		(0x7f)
+
+/* Clock Setting Register 7, MDAC Values */
+#define AIC3204_CLK7			AIC3204_PGREG(0, 12)
+/* MDAC State: Powered Down */
+#define AIC3204_CLK7_MDAC_STATE_OFF	(0 << 7)
+/* MDAC State: Powered Up */
+#define AIC3204_CLK7_MDAC_STATE_ON	(1 << 7)
+/* MDAC State Mask */
+#define AIC3204_CLK7_MDAC_STATE		(1 << 7)
+/* MDAC State bitfield location */
+#define AIC3204_CLK7_MDAC_STATE_SHIFT	(7)
+/* MDAC value bitfield location */
+#define AIC3204_CLK7_MDAC_SHIFT		(0)
+/* MDAC value bitfield mask */
+#define AIC3204_CLK7_MDAC		(0x7f)
+
+/* DAC OSR Setting Register 1, MSB */
+#define AIC3204_DOSR1			AIC3204_PGREG(0, 13)
+/* DOSR most significant portion bitfield location */
+#define AIC3204_DOSR1_MSB_SHIFT		(0)
+/* DOSR most significant portion bitfield mask */
+#define AIC3204_DOSR1_MSB		(3)
+/* DOSR most significant portion value shift */
+#define AIC3204_DOSR1_MSB_VSHIFT	(8)
+
+/* DAC OSR Setting Register 2, LSB */
+#define AIC3204_DOSR2			AIC3204_PGREG(0, 14)
+/* DOSR least significant portion bitfield location */
+#define AIC3204_DOSR2_LSB_SHIFT		(0)
+/* DOSR least significant portion bitfield mask */
+#define AIC3204_DOSR2_LSB		(0xff)
+/* DOSR least significant portion value shift */
+#define AIC3204_DOSR2_LSB_VSHIFT	(0)
+
+/* Clock Setting Register 8, NADC Values */
+#define AIC3204_CLK8			AIC3204_PGREG(0, 18)
+/* NADC State: Powered Down */
+#define AIC3204_CLK8_NADC_STATE_OFF	(0 << 7)
+/* NADC State: Powered Up */
+#define AIC3204_CLK8_NADC_STATE_ON	(1 << 7)
+/* NADC State Mask */
+#define AIC3204_CLK8_NADC_STATE		(1 << 7)
+/* NADC State bitfield location */
+#define AIC3204_CLK8_NADC_STATE_SHIFT	(7)
+/* NADC value bitfield location */
+#define AIC3204_CLK8_NADC_SHIFT		(0)
+/* NADC value bitfield mask */
+#define AIC3204_CLK8_NADC		(0x7f)
+
+/* Clock Setting Register 9, MADC Values */
+#define AIC3204_CLK9			AIC3204_PGREG(0, 19)
+/* MADC State: Powered Down */
+#define AIC3204_CLK9_MADC_STATE_OFF	(0 << 7)
+/* MADC State: Powered Up */
+#define AIC3204_CLK9_MADC_STATE_ON	(1 << 7)
+/* MADC State Mask */
+#define AIC3204_CLK9_MADC_STATE		(1 << 7)
+/* MADC State bitfield location */
+#define AIC3204_CLK9_MADC_STATE_SHIFT	(7)
+/* MADC value bitfield location */
+#define AIC3204_CLK9_MADC_SHIFT		(0)
+/* MADC value bitfield mask */
+#define AIC3204_CLK9_MADC		(0x7f)
+
+/* ADC OSR Setting Register */
+#define AIC3204_AOSR			AIC3204_PGREG(0, 20)
+
+/*
+ * Clock Register setting 10, Multiplexers
+ *
+ * XXX: Note that the datasheet goofs up here, calling this register 9, but we
+ * already had a register 9 just before AOSR.  Therefore, we will call this
+ * register 10, and will increment all following by one to correct TI's
+ * mistake.
+ */
+#define AIC3204_CLK10			AIC3204_PGREG(0, 25)
+/* CDIV Clock Source: MCLK */
+#define AIC3204_CLK10_CDIV_MCLK		(0)
+/* CDIV Clock Source: BCLK */
+#define AIC3204_CLK10_CDIV_BCLK		(1)
+/* CDIV Clock Source: Data IN */
+#define AIC3204_CLK10_CDIV_DIN		(2)
+/* CDIV Clock Source: PLL */
+#define AIC3204_CLK10_CDIV_PLL		(3)
+/* CDIV Clock Source: DAC */
+#define AIC3204_CLK10_CDIV_DAC		(4)
+/* CDIV Clock Source: DAC Modulation */
+#define AIC3204_CLK10_CDIV_DAC_MOD	(5)
+/* CDIV Clock Source: ADC */
+#define AIC3204_CLK10_CDIV_ADC		(6)
+/* CDIV Clock Source: ADC Modulation */
+#define AIC3204_CLK10_CDIV_ADC_MOD	(7)
+/* CDIV Clock Source Mask */
+#define AIC3204_CLK10_CDIV		(7)
+
+/* Clock Register setting 11, CLKOUT M divider value */
+#define AIC3204_CLK11			AIC3204_PGREG(0, 26)
+/* CLKOUT Divider State: Off */
+#define AIC3204_CLK11_CLKOUT_OFF	(0 << 7)
+/* CLKOUT Divider State: On */
+#define AIC3204_CLK11_CLKOUT_ON		(1 << 7)
+/* CLKOUT Divider State Mask */
+#define AIC3204_CLK11_CLKOUT		(1 << 7)
+/* CLKOUT Divider M value bitfield location */
+#define AIC3204_CLK11_CLKOUTM_SHIFT	(0)
+/* CLKOUT Divider M value bitfield mask */
+#define AIC3204_CLK11_CLKOUTM		(0x7f)
+
+/* Audio Interface Setting Register 1 */
+#define AIC3204_AISR1			AIC3204_PGREG(0, 27)
+/* Audio Interface Select: I2S */
+#define AIC3204_AISR1_INT_I2S		(0 << 6)
+/* Audio Interface Select: DSP */
+#define AIC3204_AISR1_INT_DSP		(1 << 6)
+/* Audio Interface Select: Right-Justified Format */
+#define AIC3204_AISR1_INT_RJF		(2 << 6)
+/* Audio Interface Select: Left-Justified Format */
+#define AIC3204_AISR1_INT_LJF		(3 << 6)
+/* Audio Interface Select Mask */
+#define AIC3204_AISR1_INT		(3 << 6)
+/* Audio Data Word Length: 16 bits */
+#define AIC3204_AISR1_WL_16BITS		(0 << 4)
+/* Audio Data Word Length: 20 bits */
+#define AIC3204_AISR1_WL_20BITS		(1 << 4)
+/* Audio Data Word Length: 24 bits */
+#define AIC3204_AISR1_WL_24BITS		(2 << 4)
+/* Audio Data Word Length: 32 bits */
+#define AIC3204_AISR1_WL_32BITS		(3 << 4)
+/* Audio Data Word Length Mask */
+#define AIC3204_AISR1_WL		(3 << 4)
+/* BCLK Direction Control: Input */
+#define AIC3204_AISR1_BCLK_IN		(0 << 3)
+/* BCLK Direction Control: Output */
+#define AIC3204_AISR1_BCLK_OUT		(1 << 3)
+/* BCLK Direction Control: Mask */
+#define AIC3204_AISR1_BCLK		(1 << 3)
+/* WCLK Direction Control: Input */
+#define AIC3204_AISR1_WCLK_IN		(0 << 2)
+/* WCLK Direction Control: Output */
+#define AIC3204_AISR1_WCLK_OUT		(1 << 2)
+/* WCLK Direction Control: Mask */
+#define AIC3204_AISR1_WCLK		(1 << 2)
+/* DOUT High Impedance Output Control: Never high impedance */
+#define AIC3204_AISR1_HIZ_NEVER		(0 << 0)
+/* DOUT High Impedance Output Control: High impedance when idle */
+#define AIC3204_AISR1_HIZ_IDLE		(1 << 0)
+/* DOUT High Impedance Output Control Mask */
+#define AIC3204_AISR1_HIZ		(1 << 0)
+
+/* Audio Interface Register 2, Data offset setting */
+#define AIC3204_AISR2			AIC3204_PGREG(0, 28)
+
+/* Audio Interface Register 3 */
+#define AIC3204_AISR3			AIC3204_PGREG(0, 29)
+/* Audio Data Loopback Control: Disabled */
+#define AIC3204_AISR3_ADLO_OFF		(0 << 5)
+/* Audio Data Loopback Control: Enabled */
+#define AIC3204_AISR3_ADLO_ON		(1 << 5)
+/* Audio Data Loopback Control Mask */
+#define AIC3204_AISR3_ADLO		(1 << 5)
+/* ADC->DAC Loopback Control: Disabled */
+#define AIC3204_AISR3_ADDALO_OFF	(0 << 4)
+/* ADC->DAC Loopback Control: Enabled */
+#define AIC3204_AISR3_ADDALO_ON		(1 << 4)
+/* ADC->DAC Loopback Control Mask */
+#define AIC3204_AISR3_ADDALO		(1 << 4)
+/* Audio Bit Clock Polarity: Normal */
+#define AIC3204_AISR3_BCLKPOL_NOR	(0 << 3)
+/* Audio Bit Clock Polarity: Inverted */
+#define AIC3204_AISR3_BCLKPOL_INV	(1 << 3)
+/* Audio Bit Clock Polarity Mask */
+#define AIC3204_AISR3_BCLKPOL		(1 << 3)
+/* Audio Data Interface Clock Buffers: Always powered */
+#define AIC3204_AISR3_ADICLK_ALWAYS	(0 << 2)
+/* Audio Data Interface Clock Buffers: Powered with CODEC only */
+#define AIC3204_AISR3_ADICLK_CODEC	(1 << 2)
+/* Audio Data Interface Clock Buffers' State */
+#define AIC3204_AISR3_ADICLK		(1 << 2)
+/* Audio Bit Clock Divider Source: DAC */
+#define AIC3204_AISR3_BDIV_DAC		(0 << 0)
+/* Audio Bit Clock Divider Source: DAC Modulation */
+#define AIC3204_AISR3_BDIV_DAC_MOD	(1 << 0)
+/* Audio Bit Clock Divider Source: ADC */
+#define AIC3204_AISR3_BDIV_ADC		(2 << 0)
+/* Audio Bit Clock Divider Source: ADC Modulation */
+#define AIC3204_AISR3_BDIV_ADC_MOD	(3 << 0)
+/* Audio Bit Clock Divider Source Mask */
+#define AIC3204_AISR3_BDIV		(3 << 0)
+
+/* Clock Setting Register 12, BCLK N Divider */
+#define AIC3204_CLK12			AIC3204_PGREG(0, 30)
+/* BCLK N State: Powered Down */
+#define AIC3204_PG0_CLK12_BCLK_STATE_OFF (0 << 7)
+/* BCLK N State: Powered Up */
+#define AIC3204_CLK12_BCLK_STATE_ON	(1 << 7)
+/* BCLK N State Mask */
+#define AIC3204_CLK12_BCLK_STATE	(1 << 7)
+/* BCLK N State bitfield location */
+#define AIC3204_CLK12_BCLK_STATE_SHIFT	(7)
+/* BCLK N value bitfield location */
+#define AIC3204_CLK12_BCLK_SHIFT	(0)
+/* BCLK N value bitfield mask */
+#define AIC3204_CLK12_BCLK		(0x7f)
+
+/* Audio Interface Setting Register 4, Secondary Audio Interface */
+#define AIC3204_AISR4			AIC3204_PGREG(0, 31)
+/* Secondary Bit Clock: GPIO */
+#define AIC3204_AISR4_SECBCLK_GPIO	(0 << 5)
+/* Secondary Bit Clock: SCLK */
+#define AIC3204_AISR4_SECBCLK_SCLK	(1 << 5)
+/* Secondary Bit Clock: MISO */
+#define AIC3204_AISR4_SECBCLK_MISO	(2 << 5)
+/* Secondary Bit Clock: DOUT */
+#define AIC3204_AISR4_SECBCLK_DOUT	(3 << 5)
+/* Secondary Bit Clock Mask */
+#define AIC3204_AISR4_SECBCLK		(3 << 5)
+/* Secondary Word Clock: GPIO */
+#define AIC3204_AISR4_SECWCLK_GPIO	(0 << 3)
+/* Secondary Word Clock: SCLK */
+#define AIC3204_AISR4_SECWCLK_SCLK	(1 << 3)
+/* Secondary Word Clock: MISO */
+#define AIC3204_AISR4_SECWCLK_MISO	(2 << 3)
+/* Secondary Word Clock: DOUT */
+#define AIC3204_AISR4_SECWCLK_DOUT	(3 << 3)
+/* Secondary Word Clock Mask */
+#define AIC3204_AISR4_SECWCLK		(3 << 3)
+/* ADC Word Clock: GPIO */
+#define AIC3204_AISR4_ADCWCLK_GPIO	(0 << 3)
+/* ADC Word Clock: SCLK */
+#define AIC3204_AISR4_ADCWCLK_SCLK	(1 << 3)
+/* ADC Word Clock: MISO */
+#define AIC3204_AISR4_ADCWCLK_MISO	(2 << 3)
+/* ADC Word Clock Mask */
+#define AIC3204_AISR4_ADCWCLK		(3 << 3)
+/* Secondary Data Input: GPIO */
+#define AIC3204_AISR4_SECDIN_GPIO	(0 << 0)
+/* Secondary Data Input: SCLK */
+#define AIC3204_AISR4_SECDIN_SCLK	(1 << 0)
+/* Secondary Data Input Mask */
+#define AIC3204_AISR4_SECDIN		(1 << 0)
+
+/* Audio Interface Setting Register 5 */
+#define AIC3204_AISR5			AIC3204_PGREG(0, 32)
+/* Audio Interface Bit Clock: Primary (BCLK) */
+#define AIC3204_AISR5_BCLKIN_PRI	(0 << 3)
+/* Audio Interface Bit Clock: Secondary */
+#define AIC3204_AISR5_BCLKIN_SEC	(1 << 3)
+/* Audio Interface Bit Clock Mask */
+#define AIC3204_AISR5_WCLKIN		(1 << 2)
+/* Audio Interface Word Clock: Primary (BCLK) */
+#define AIC3204_AISR5_WCLKIN_PRI	(0 << 2)
+/* Audio Interface Word Clock: Secondary */
+#define AIC3204_AISR5_WCLKIN_SEC	(1 << 2)
+/* Audio Interface Word Clock Mask */
+#define AIC3204_AISR5_WCLKIN		(1 << 2)
+/* ADC Word Clock Control: ADC WCLK = DAC WCLK */
+#define ADC3204_PG0_AISR5_ADCWCLK_DAC	(0 << 1)
+/* ADC Word Clock Control: ADC WCLK = Secondary ADC WCLK */
+#define ADC3204_PG0_AISR5_ADCWCLK_SEC	(1 << 1)
+/* ADC Word Clock Control Mask */
+#define ADC3204_PG0_AISR5_ADCWCLK	(1 << 1)
+/* Audio Data In: Primary Data In */
+#define ADC3204_PG0_AISR5_DIN_PRI	(0 << 0)
+/* Audio Data In: Secondary Data In */
+#define ADC3204_PG0_AISR5_DIN_SEC	(1 << 0)
+/* Audio Data In Mask */
+#define ADC3204_PG0_AISR5_DIN		(1 << 0)
+
+/* Audio Interface Setting Register 6 */
+#define AIC3204_AISR6			AIC3204_PGREG(0, 33)
+/* BCLK Output Control: Generated Primary Bit Clock */
+#define AIC3204_AISR6_BCLKOUT_GEN	(0 << 7)
+/* BCLK Output Control: Secondary Bit Clock */
+#define AIC3204_AISR6_BCLKOUT_SEC	(1 << 7)
+/* BCLK Output Control Mask */
+#define AIC3204_AISR6_BCLKOUT		(1 << 7)
+/* Secondary BCLK Output Control: Primary Bit Clock Input */
+#define AIC3204_AISR6_SBCLKOUT_BCLK	(0 << 6)
+/* Secondary BCLK Output Control: Generated Primary Bit Clock */
+#define AIC3204_AISR6_SBCLKOUT_GEN	(1 << 6)
+/* Secondary BCLK Output Control Mask */
+#define AIC3204_AISR6_SBCLKOUT		(1 << 6)
+/* WCLK Output Control: Generated DAC_FS */
+#define AIC3204_AISR6_WCLKOUT_DAC	(0 << 4)
+/* WCLK Output Control: Generated ADC_FS */
+#define AIC3204_AISR6_WCLKOUT_ADC	(1 << 4)
+/* WCLK Output Control: Secondary WCLK Input */
+#define AIC3204_AISR6_WCLKOUT_SWCLK	(2 << 4)
+/* WCLK Output Control Mask */
+#define AIC3204_AISR6_WCLKOUT		(3 << 4)
+/* Secondary WCLK Output Control: WCLK Input */
+#define AIC3204_AISR6_SWCLKOUT_WCLK	(0 << 2)
+/* Secondary WCLK Output Control: Generated DAC_FS */
+#define AIC3204_AISR6_SWCLKOUT_DAC	(1 << 2)
+/* Secondary WCLK Output Control: Generated ADC_FS */
+#define AIC3204_AISR6_SWCLKOUT_ADC	(2 << 2)
+/* Secondary WCLK Output Control Mask */
+#define AIC3204_AISR6_SWCLKOUT		(3 << 2)
+/* Primary Data Output Control: Serial Interface */
+#define AIC3204_AISR6_DOUT_INT		(0 << 1)
+/* Primary Data Output Control: Secondary Data Input */
+#define AIC3204_AISR6_DOUT_SDIN		(1 << 1)
+/* Primary Data Output Control Mask */
+#define AIC3204_AISR6_DOUT		(1 << 1)
+/* Secondary Data Output Control: Primary Data In */
+#define AIC3204_AISR6_SDOUT_DIN		(0 << 0)
+/* Secondary Data Output Control: Serial Interface */
+#define AIC3204_AISR6_SDOUT_INT		(1 << 0)
+/* Secondary Data Output Control Mask */
+#define AIC3204_AISR6_SDOUT		(1 << 0)
+
+/* Digital Interface Misc. Setting Register */
+#define AIC3204_DIMISC			AIC3204_PGREG(0, 34)
+/* I2C General Call Address Configuration: Ignore */
+#define AIC3204_DIMISC_I2CGC_IGNORE	(0 << 5)
+/* I2C General Call Address Configuration: Accept */
+#define AIC3204_DIMISC_I2CGC_ACCEPT	(1 << 5)
+
+/* ADC Flag Register */
+#define AIC3204_ADCF			AIC3204_PGREG(0, 36)
+/* Left ADC PGA Status: Gain is set */
+#define AIC3204_ADCF_LEFT_PGASET	(1 << 7)
+/* Left ADC Power Status: Powered Up */
+#define AIC3204_ADCF_LEFT_UP		(1 << 6)
+/* Left ADC AGC Status: Gain is saturated */
+#define AIC3204_ADCF_LEFT_AGCSAT	(1 << 5)
+/* Right ADC PGA Status: Gain is set */
+#define AIC3204_ADCF_RIGHT_PGASET	(1 << 3)
+/* Right ADC Power Status: Powered Up */
+#define AIC3204_ADCF_RIGHT_UP		(1 << 2)
+/* Right ADC AGC Status: Gain is saturated */
+#define AIC3204_ADCF_RIGHT_AGCSAT	(1 << 1)
+
+/* DAC Flag Register 1 */
+#define AIC3204_DACF1			AIC3204_PGREG(0, 37)
+/* Left DAC powered up */
+#define AIC3204_DACF1_LEFT_UP		(1 << 7)
+/* Left Line Output Driver powered up */
+#define AIC3204_DACF1_LOL_UP		(1 << 6)
+/* Left Headphone Output Driver powered up */
+#define AIC3204_DACF1_HPL_UP		(1 << 5)
+/* Right DAC powered up */
+#define AIC3204_DACF1_RIGHT_UP		(1 << 7)
+/* Right Line Output Driver powered up */
+#define AIC3204_DACF1_LOR_UP		(1 << 6)
+/* Right Headphone Output Driver powered up */
+#define AIC3204_DACF1_HPR_UP		(1 << 5)
+
+/* DAC Flag Register 2 */
+#define AIC3204_DACF2			AIC3204_PGREG(0, 38)
+/* Left DAC PGA Status: Gain is set */
+#define AIC3204_DACF2_LEFT_PGASET	(1 << 4)
+/* Right DAC PGA Status: Gain is set */
+#define AIC3204_DACF2_RIGHT_PGASET	(1 << 0)
+
+/* Sticky Flag Register 1 */
+#define AIC3204_STICK1			AIC3204_PGREG(0, 42)
+/* Left DAC Overflow */
+#define AIC3204_STICK1_LDAC_OVER	(1 << 7)
+/* Right DAC Overflow */
+#define AIC3204_STICK1_RDAC_OVER	(1 << 6)
+/* Left ADC Overflow */
+#define AIC3204_STICK1_LADC_OVER	(1 << 3)
+/* Right ADC Overflow */
+#define AIC3204_STICK1_RADC_OVER	(1 << 2)
+
+/* Interrupt Flag Register 1 */
+#define AIC3204_INTF1			AIC3204_PGREG(0, 43)
+/* Left DAC Overflow */
+#define AIC3204_INTF1_LDAC_OVER		(1 << 7)
+/* Right DAC Overflow */
+#define AIC3204_INTF1_RDAC_OVER		(1 << 6)
+/* Left ADC Overflow */
+#define AIC3204_INTF1_LADC_OVER		(1 << 3)
+/* Right ADC Overflow */
+#define AIC3204_INTF1_RADC_OVER		(1 << 2)
+
+/* Sticky Flag Register 2 */
+#define AIC3204_STICK2			AIC3204_PGREG(0, 44)
+/* Left Headphone Driver Over Current */
+#define AIC3204_STICK2_HPL_OVER		(1 << 7)
+/* Right Headphone Driver Over Current */
+#define AIC3204_STICK2_HPR_OVER		(1 << 6)
+/* Headset button pressed */
+#define AIC3204_STICK2_HS_BUTTON	(1 << 5)
+/* Headset plug inserted/removed */
+#define AIC3204_STICK2_HS_PLUGGED	(1 << 4)
+/* Left Channel DRC: Over threshold */
+#define AIC3204_STICK2_LDRC_OVER	(1 << 3)
+/* Right Channel DRC: Over threshold */
+#define AIC3204_STICK2_RDRC_OVER	(1 << 2)
+
+/* Sticky Flag Register 3 */
+#define AIC3204_STICK3			AIC3204_PGREG(0, 45)
+/* Left AGC Noise Threshold Flag: Over threshold */
+#define AIC3204_STICK3_LAGC_OVER	(1 << 6)
+/* Right AGC Noise Threshold Flag: Over threshold */
+#define AIC3204_STICK3_RAGC_OVER	(1 << 5)
+/* Left ADC DC Measurement Available */
+#define AIC3204_STICK3_LADC_DC		(1 << 2)
+/* Right ADC DC Measurement Available */
+#define AIC3204_STICK3_RADC_DC		(1 << 1)
+
+/* Interrupt Flag Register 2 */
+#define AIC3204_INTF2			AIC3204_PGREG(0, 46)
+/* Left Headphone Driver Over Current */
+#define AIC3204_INTF2_HPL_OVER		(1 << 7)
+/* Right Headphone Driver Over Current */
+#define AIC3204_INTF2_HPR_OVER		(1 << 6)
+/* Headset button pressed */
+#define AIC3204_INTF2_HS_BUTTON		(1 << 5)
+/* Headset plug inserted/removed */
+#define AIC3204_INTF2_HS_PLUGGED	(1 << 4)
+/* Left Channel DRC: Over threshold */
+#define AIC3204_INTF2_LDRC_OVER		(1 << 3)
+/* Right Channel DRC: Over threshold */
+#define AIC3204_INTF2_RDRC_OVER		(1 << 2)
+
+/* Interrupt Flag Register 3 */
+#define AIC3204_INTF3			AIC3204_PGREG(0, 47)
+/* Left AGC Noise Threshold Flag: Over threshold */
+#define AIC3204_INTF3_LAGC_OVER		(1 << 6)
+/* Right AGC Noise Threshold Flag: Over threshold */
+#define AIC3204_INTF3_RAGC_OVER		(1 << 5)
+/* Left ADC DC Measurement Available */
+#define AIC3204_INTF3_LADC_DC		(1 << 2)
+/* Right ADC DC Measurement Available */
+#define AIC3204_INTF3_RADC_DC		(1 << 1)
+
+/* INT1 Interrupt Control Register */
+#define AIC3204_INT1			AIC3204_PGREG(0, 48)
+/* INT1 Generated on Headset insertion */
+#define AIC3204_INT1_HS_PLUG		(1 << 7)
+/* INT1 Generated on Headset Button press */
+#define AIC3204_INT1_HS_BUTTON		(1 << 6)
+/* INT1 Generated on DAC DRC Signal Threshold */
+#define AIC3204_INT1_DAC_DRC		(1 << 5)
+/* INT1 Generated on AGC Noise Interrupt */
+#define AIC3204_INT1_ADC_NOISE		(1 << 4)
+/* INT1 Generated on Over Current */
+#define AIC3204_INT1_HP_OVERCURRENT	(1 << 3)
+/* INT1 Generated on overflow event */
+#define AIC3204_INT1_OVERFLOW		(1 << 2)
+/* INT1 Generated on DC measurement */
+#define AIC3204_INT1_DC			(1 << 1)
+/* INT1 pulse control: Continuous pulse train */
+#define AIC3204_INT1_CONT_PULSE		(1 << 0)
+
+/* INT2 Interrupt Control Register */
+#define AIC3204_INT2			AIC3204_PGREG(0, 49)
+/* INT2 Generated on Headset insertion */
+#define AIC3204_INT2_HS_PLUG		(1 << 7)
+/* INT2 Generated on Headset Button press */
+#define AIC3204_INT2_HS_BUTTON		(1 << 6)
+/* INT2 Generated on DAC DRC Signal Threshold */
+#define AIC3204_INT2_DAC_DRC		(1 << 5)
+/* INT2 Generated on AGC Noise Interrupt */
+#define AIC3204_INT2_ADC_NOISE		(1 << 4)
+/* INT2 Generated on Over Current */
+#define AIC3204_INT2_HP_OVERCURRENT	(1 << 3)
+/* INT2 Generated on overflow event */
+#define AIC3204_INT2_OVERFLOW		(1 << 2)
+/* INT2 Generated on DC measurement */
+#define AIC3204_INT2_DC			(1 << 1)
+/* INT2 pulse control: Continuous pulse train */
+#define AIC3204_INT2_CONT_PULSE		(1 << 0)
+
+/* GPIO/MFP5 Control Register */
+#define AIC3204_MFP5			AIC3204_PGREG(0, 52)
+/* GPIO Control: Disabled */
+#define AIC3204_MFP5_FUNC_DISABLED	(0 << 2)
+/* GPIO Control: Secondary audio interface/digital microphone/clock input */
+#define AIC3204_MFP5_FUNC_SAI_DM_CI	(1 << 2)
+/* GPIO Control: General Purpose Input */
+#define AIC3204_MFP5_FUNC_INPUT		(2 << 2)
+/* GPIO Control: General Purpose Output */
+#define AIC3204_MFP5_FUNC_OUTPUT	(3 << 2)
+/* GPIO Control: CLKOUT Output */
+#define AIC3204_MFP5_FUNC_CLKOUT	(4 << 2)
+/* GPIO Control: INT1 Output */
+#define AIC3204_MFP5_FUNC_INT1		(4 << 2)
+/* GPIO Control: INT2 Output */
+#define AIC3204_MFP5_FUNC_INT2		(4 << 2)
+/* GPIO Control: ADC_WCLK */
+#define AIC3204_MFP5_FUNC_ADC_WCLK	(4 << 2)
+/* GPIO Control: Secondary Bit Clock */
+#define AIC3204_MFP5_FUNC_SEC_BCLK	(4 << 2)
+/* GPIO Control: Secondary Word Clock */
+#define AIC3204_MFP5_FUNC_SEC_WCLK	(4 << 2)
+/* GPIO Control: Digital Microphone Clock */
+#define AIC3204_MFP5_FUNC_DMIC_CLK	(4 << 2)
+/* GPIO Control Mask */
+#define AIC3204_MFP5_FUNC		(15 << 2)
+/* GPIO Input State */
+#define AIC3204_MFP5_IN			(1 << 1)
+/* GPIO Output State */
+#define AIC3204_MFP5_OUT		(1 << 0)
+
+/* DOUT/MFP2 Function Control Register */
+#define AIC3204_MFP2			AIC3204_PGREG(0, 53)
+/* DOUT Bus Keeper Enabled */
+#define AIC3204_MFP2_BK			(1 << 4)
+/* DOUT MUX Control: Disabled */
+#define AIC3204_MFP2_FUNC_DISABLED	(0 << 1)
+/* DOUT MUX Control: Primary DOUT */
+#define AIC3204_MFP2_FUNC_PRI_DOUT	(1 << 1)
+/* DOUT MUX Control: General Purpose Output */
+#define AIC3204_MFP2_FUNC_OUTPUT	(2 << 1)
+/* DOUT MUX Control: CLKOUT Clock Output */
+#define AIC3204_MFP2_FUNC_CLKOUT	(3 << 1)
+/* DOUT MUX Control: INT1 Output */
+#define AIC3204_MFP2_FUNC_INT1		(4 << 1)
+/* DOUT MUX Control: INT2 Output */
+#define AIC3204_MFP2_FUNC_INT2		(5 << 1)
+/* DOUT MUX Control: Secondary Bit Clock */
+#define AIC3204_MFP2_FUNC_SEC_BCLK	(6 << 1)
+/* DOUT MUX Control: Secondary Word Clock */
+#define AIC3204_MFP2_FUNC_SEC_WCLK	(7 << 1)
+/* DOUT MUX Control Mask */
+#define AIC3204_MFP2_FUNC		(7 << 1)
+/* DOUT General Purpose Output State */
+#define AIC3204_MFP2_OUT		(1 << 0)
+
+/* DIN/MFP1 Function Control Register */
+#define AIC3204_MFP1			AIC3204_PGREG(0, 54)
+/* DIN Function Control: Disabled */
+#define AIC3204_MFP1_FUNC_DISABLED	(0 << 1)
+/* DIN Function Control: Primary Data Input/Digital Microphone/Clock Input */
+#define AIC3204_MFP1_FUNC_DIN_DM_CI	(1 << 1)
+/* DIN Function Control: General Purpose Input */
+#define AIC3204_MFP1_FUNC_INPUT		(2 << 1)
+/* DIN Function Control Mask */
+#define AIC3204_MFP1_FUNC		(3 << 1)
+/* DIN Input State */
+#define AIC3204_MFP1_IN			(1 << 0)
+
+/* MISO/MFP4 Function Control Register */
+#define AIC3204_MFP4			AIC3204_PGREG(0, 55)
+/* MISO Function Control: Disabled */
+#define AIC3204_MFP4_FUNC_DISABLED	(0 << 1)
+/* MISO Function Control: SPI Data Output (disabled in I2C mode) */
+#define AIC3204_MFP4_FUNC_SPI_OUT	(1 << 1)
+/* MISO Function Control: General Purpose Output */
+#define AIC3204_MFP4_FUNC_OUTPUT	(2 << 1)
+/* MISO Function Control: CLKOUT Clock Output */
+#define AIC3204_MFP4_FUNC_CLKOUT	(3 << 1)
+/* MISO Function Control: INT1 Output */
+#define AIC3204_MFP4_FUNC_INT1		(4 << 1)
+/* MISO Function Control: INT2 Output */
+#define AIC3204_MFP4_FUNC_INT2		(5 << 1)
+/* MISO Function Control: ADC Word Clock Output */
+#define AIC3204_MFP4_FUNC_ADC_WCLK	(6 << 1)
+/* MISO Function Control: Digital Microphone Clock Output */
+#define AIC3204_MFP4_FUNC_DMIC_CLK	(7 << 1)
+/* MISO Function Control: Secondary Data Output */
+#define AIC3204_MFP4_FUNC_SEC_DOUT	(8 << 1)
+/* MISO Function Control: Secondary Bit Clock */
+#define AIC3204_MFP4_FUNC_SEC_BCLK	(9 << 1)
+/* MISO Function Control: Secondary Word Clock */
+#define AIC3204_MFP4_FUNC_SEC_WCLK	(10 << 1)
+/* MISO Function Control Mask */
+#define AIC3204_MFP4_FUNC		(15 << 1)
+/* MISO Output State */
+#define AIC3204_MFP4_OUT		(1 << 0)
+
+/* SCLK/MFP3 Function Control Register */
+#define AIC3204_MFP3			AIC3204_PGREG(0, 56)
+/* SCLK Function Control: Disabled */
+#define AIC3204_MFP3_FUNC_DISABLED	(0 << 1)
+/* SCLK Function Control: SPI Clock / Secondary Interface / Digital Mic Input */
+#define AIC3204_MFP3_FUNC_SPI_SI_DM	(1 << 1)
+/* SCLK Function Control: General Purpose Input */
+#define AIC3204_MFP3_FUNC_INPUT		(2 << 1)
+/* SCLK Function Control Mask */
+#define AIC3204_MFP3_FUNC		(3 << 1)
+/* SCLK Input State */
+#define AIC3204_MFP3_IN			(1 << 0)
+
+/* DAC Signal Processing Block Control Register */
+#define AIC3204_DACSPB			AIC3204_PGREG(0, 60)
+/* DAC Signal Processing Block Mask */
+#define AIC3204_DACSPB_MASK		0x1f
+
+/* ADC Signal Processing Block Control Register */
+#define AIC3204_ADCSPB			AIC3204_PGREG(0, 61)
+/* ADC Signal Processing Block Mask */
+#define AIC3204_ADCSPB_MASK		0x1f
+
+/* DAC Channel Setup Register 1 */
+#define AIC3204_DACS1			AIC3204_PGREG(0, 63)
+/* Left DAC Powered Up */
+#define AIC3204_DACS1_LDAC_UP_SHIFT	(7)
+/* Right DAC Powered Up */
+#define AIC3204_DACS1_RDAC_UP_SHIFT	(6)
+/* Left DAC Data Path Control: Disabled */
+#define AIC3204_DACS1_LDACD_DIS		(0 << 4)
+/* Left DAC Data Path Control: Left Data */
+#define AIC3204_DACS1_LDACD_LEFT	(1 << 4)
+/* Left DAC Data Path Control: Right Data */
+#define AIC3204_DACS1_LDACD_RIGHT	(2 << 4)
+/* Left DAC Data Path Control: Left + Right */
+#define AIC3204_DACS1_LDACD_MIX		(3 << 4)
+/* Left DAC Data Path Control Mask */
+#define AIC3204_DACS1_LDACD		(3 << 4)
+/* Right DAC Data Path Control: Disabled */
+#define AIC3204_DACS1_RDACD_DIS		(0 << 2)
+/* Right DAC Data Path Control: Right Data */
+#define AIC3204_DACS1_RDACD_RIGHT	(1 << 2)
+/* Right DAC Data Path Control: Left Data */
+#define AIC3204_DACS1_RDACD_LEFT	(2 << 2)
+/* Right DAC Data Path Control: Left + Right */
+#define AIC3204_DACS1_RDACD_MIX		(3 << 2)
+/* Right DAC Data Path Control Mask */
+#define AIC3204_DACS1_RDACD		(3 << 2)
+/* DAC Soft-Step: Disabled */
+#define AIC3204_DACS1_SOFT_DIS		(0 << 0)
+/* DAC Soft-Step: 1 step every clock */
+#define AIC3204_DACS1_SOFT_1SEC		(1 << 0)
+/* DAC Soft-Step: 1 step every 2 clocks */
+#define AIC3204_DACS1_SOFT_1SE2C	(2 << 0)
+/* DAC Soft-Step Mask */
+#define AIC3204_DACS1_SOFT		(3 << 0)
+
+/* DAC Channel Setup Register 2 */
+#define AIC3204_DACS2			AIC3204_PGREG(0, 64)
+/* Right Modulator Output Control: Output is inverted left output */
+#define AIC3204_DACS2_RMOD_INV_SHIFT	(7)
+/* DAC Auto Mute: Disabled */
+#define AIC3204_DACS2_AMUTE_DIS		(0 << 4)
+/* DAC Auto Mute: After 100 samples of DC */
+#define AIC3204_DACS2_AMUTE_100		(1 << 4)
+/* DAC Auto Mute: After 200 samples of DC */
+#define AIC3204_DACS2_AMUTE_200		(2 << 4)
+/* DAC Auto Mute: After 400 samples of DC */
+#define AIC3204_DACS2_AMUTE_400		(3 << 4)
+/* DAC Auto Mute: After 800 samples of DC */
+#define AIC3204_DACS2_AMUTE_800		(4 << 4)
+/* DAC Auto Mute: After 1600 samples of DC */
+#define AIC3204_DACS2_AMUTE_1600	(5 << 4)
+/* DAC Auto Mute: After 3200 samples of DC */
+#define AIC3204_DACS2_AMUTE_3200	(6 << 4)
+/* DAC Auto Mute: After 6400 samples of DC */
+#define AIC3204_DACS2_AMUTE_6400	(7 << 4)
+/* DAC Auto Mute Mask */
+#define AIC3204_DACS2_AMUTE		(7 << 4)
+/* Left DAC Muted */
+#define AIC3204_DACS2_LEFT_MUTE_SHIFT	(3)
+/* Right DAC Muted */
+#define AIC3204_DACS2_RIGHT_MUTE_SHIFT	(2)
+/* DAC Master Volume Control: Independant */
+#define AIC3204_DACS2_VOL_IND		(0 << 0)
+/* DAC Master Volume Control: Left controls right */
+#define AIC3204_DACS2_VOL_LEFT		(1 << 0)
+/* DAC Master Volume Control: Right controls left */
+#define AIC3204_DACS2_VOL_RIGHT		(2 << 0)
+/* DAC Master Volume Control Mask */
+#define AIC3204_DACS2_VOL			(3 << 0)
+
+/* Left DAC Digital Volume Control */
+#define AIC3204_LDACVOL			AIC3204_PGREG(0, 65)
+
+/* Right DAC Digital Volume Control */
+#define AIC3204_RDACVOL			AIC3204_PGREG(0, 66)
+
+/* Headset Detection Configuration Register */
+#define AIC3204_HSDET			AIC3204_PGREG(0, 67)
+/* Enable Headset Detection */
+#define AIC3204_HSDET_ENABLE		(1 << 7)
+/* Headset Type: No Headset */
+#define AIC3204_HSDET_NONE		(0 << 5)
+/* Headset Type: Stereo Headset */
+#define AIC3204_HSDET_STEREO		(1 << 5)
+/* Headset Type: Cellular Stereo Headset */
+#define AIC3204_HSDET_CELLSTEREO	(3 << 5)
+/* Headset Detection Debounce Time: 16ms */
+#define AIC3204_HSDET_PLUGDT_16		(0 << 2)
+/* Headset Detection Debounce Time: 32ms */
+#define AIC3204_HSDET_PLUGDT_32		(1 << 2)
+/* Headset Detection Debounce Time: 64ms */
+#define AIC3204_HSDET_PLUGDT_64		(2 << 2)
+/* Headset Detection Debounce Time: 128ms */
+#define AIC3204_HSDET_PLUGDT_128	(3 << 2)
+/* Headset Detection Debounce Time: 256ms */
+#define AIC3204_HSDET_PLUGDT_256	(4 << 2)
+/* Headset Detection Debounce Time: 512ms */
+#define AIC3204_HSDET_PLUGDT_512	(5 << 2)
+/* Headset Detection Debounce Time Mask */
+#define AIC3204_HSDET_PLUGDT		(7 << 2)
+/* Headset Button Debounce Time: 8ms */
+#define AIC3204_HSDET_BTNDT_8		(0 << 0)
+/* Headset Button Debounce Time: 16ms */
+#define AIC3204_HSDET_BTNDT_16		(1 << 0)
+/* Headset Button Debounce Time: 32ms */
+#define AIC3204_HSDET_BTNDT_32		(2 << 0)
+/* Headset Button Debounce Time Mask */
+#define AIC3204_HSDET_BTNDT		(3 << 0)
+
+/* DRC Control Register 1 */
+#define AIC3204_DRC1			AIC3204_PGREG(0, 68)
+/* Left Channel DRC Enable */
+#define AIC3204_DRC1_LEFT_EN		(1 << 6)
+/* Right Channel DRC Enable */
+#define AIC3204_DRC1_RIGHT_EN		(1 << 5)
+/* DRC Threshold: -3dBFS */
+#define AIC3204_DRC1_THOLD_3DBFS	(0 << 2)
+/* DRC Threshold: -6dBFS */
+#define AIC3204_DRC1_THOLD_6DBFS	(1 << 2)
+/* DRC Threshold: -9dBFS */
+#define AIC3204_DRC1_THOLD_9DBFS	(2 << 2)
+/* DRC Threshold: -12dBFS */
+#define AIC3204_DRC1_THOLD_12DBFS	(3 << 2)
+/* DRC Threshold: -15dBFS */
+#define AIC3204_DRC1_THOLD_15DBFS	(4 << 2)
+/* DRC Threshold: -18dBFS */
+#define AIC3204_DRC1_THOLD_18DBFS	(5 << 2)
+/* DRC Threshold: -21dBFS */
+#define AIC3204_DRC1_THOLD_21DBFS	(6 << 2)
+/* DRC Threshold: -24dBFS */
+#define AIC3204_DRC1_THOLD_24DBFS	(7 << 2)
+/* DRC Threshold Mask */
+#define AIC3204_DRC1_THOLD		(7 << 2)
+/* DRC Hysteresis: 0dB */
+#define AIC3204_DRC1_HYST_0DB		(0 << 0)
+/* DRC Hysteresis: 1dB */
+#define AIC3204_DRC1_HYST_1DB		(1 << 0)
+/* DRC Hysteresis: 2dB */
+#define AIC3204_DRC1_HYST_2DB		(2 << 0)
+/* DRC Hysteresis: 3dB */
+#define AIC3204_DRC1_HYST_3DB		(3 << 0)
+/* DRC Hysteresis Mask */
+#define AIC3204_DRC1_HYST		(3 << 0)
+
+/* DRC Control Register 2 */
+#define AIC3204_DRC2			AIC3204_PGREG(0, 69)
+/* DRC Hold: Disabled */
+#define AIC3204_DRC2_HOLD_DISABLED	(0 << 3)
+/* DRC Hold: 32 Word Clocks */
+#define AIC3204_DRC2_HOLD_32WC		(1 << 3)
+/* DRC Hold: 64 Word Clocks */
+#define AIC3204_DRC2_HOLD_64WC		(2 << 3)
+/* DRC Hold: 128 Word Clocks */
+#define AIC3204_DRC2_HOLD_128WC		(3 << 3)
+/* DRC Hold: 256 Word Clocks */
+#define AIC3204_DRC2_HOLD_256WC		(4 << 3)
+/* DRC Hold: 512 Word Clocks */
+#define AIC3204_DRC2_HOLD_512WC		(5 << 3)
+/* DRC Hold: 1024 Word Clocks */
+#define AIC3204_DRC2_HOLD_1024WC	(6 << 3)
+/* DRC Hold: 2048 Word Clocks */
+#define AIC3204_DRC2_HOLD_2048WC	(7 << 3)
+/* DRC Hold: 4096 Word Clocks */
+#define AIC3204_DRC2_HOLD_4096WC	(8 << 3)
+/* DRC Hold: 8192 Word Clocks */
+#define AIC3204_DRC2_HOLD_8192WC	(9 << 3)
+/* DRC Hold: 16384 Word Clocks */
+#define AIC3204_DRC2_HOLD_16384WC	(10 << 3)
+/* DRC Hold: 32768 Word Clocks */
+#define AIC3204_DRC2_HOLD_32768WC	(11 << 3)
+/* DRC Hold: 65536 Word Clocks */
+#define AIC3204_DRC2_HOLD_65536WC	(12 << 3)
+/* DRC Hold: 98304 Word Clocks */
+#define AIC3204_DRC2_HOLD_98304WC	(13 << 3)
+/* DRC Hold: 131072 Word Clocks */
+#define AIC3204_DRC2_HOLD_131072WC	(14 << 3)
+/* DRC Hold: 163840 Word Clocks */
+#define AIC3204_DRC2_HOLD_163840WC	(15 << 3)
+/* DRC Hold Mask */
+#define AIC3204_DRC2_HOLD		(15 << 3)
+
+/* DRC Control Register 3 */
+#define AIC3204_DRC3			AIC3204_PGREG(0, 70)
+/* DRC Attack Rate Shift */
+#define AIC3204_DRC3_ATTACK_SHIFT	4
+/* DRC Attack Rate Mask */
+#define AIC3204_DRC3_ATTACK		(15 << AIC3204_DRC3_ATTACK_SHIFT)
+/* DRC Decay Rate Shift */
+#define AIC3204_DRC3_DECAY_SHIFT	0
+/* DRC Decay Rate Mask */
+#define AIC3204_DRC3_DECAY		(15 << AIC3204_DRC3_DECAY_SHIFT)
+
+/* Beep Generator Register 1 */
+#define AIC3204_BEEP1			AIC3204_PGREG(0, 71)
+/* Enable Beep Generator */
+#define AIC3204_BEEP1_EN		(1 << 7)
+/* Left Channel Beep Volume Shift */
+#define AIC3204_BEEP1_VOL_SHIFT		0
+/* Left Channel Beep Volume Mask */
+#define AIC3204_BEEP1_VOL		(0x3f)
+
+/* Beep Generator Register 2 */
+#define AIC3204_BEEP2			AIC3204_PGREG(0, 72)
+/* Beep Generator Master Volume: Independant Left/Right Channels */
+#define AIC3204_BEEP2_MVOL_IND		(0 << 6)
+/* Beep Generator Master Volume: Left Channel controls Right */
+#define AIC3204_BEEP2_MVOL_LEFT		(1 << 6)
+/* Beep Generator Master Volume: Right Channel controls Left */
+#define AIC3204_BEEP2_MVOL_RIGHT	(2 << 6)
+/* Beep Generator Master Volume Mask */
+#define AIC3204_BEEP2_MVOL		(3 << 6)
+
+/* Beep Generator Register 3 */
+#define AIC3204_BEEP3			AIC3204_PGREG(0, 73)
+/* Sample Length Value Shift */
+#define AIC3204_BEEP3_LENGTH_VSHIFT	16
+/* Sample Length Shift */
+#define AIC3204_BEEP3_LENGTH_SHIFT	0
+/* Sample Length Mask */
+#define AIC3204_BEEP3_LENGTH		(0xff)
+
+/* Beep Generator Register 4 */
+#define AIC3204_BEEP4			AIC3204_PGREG(0, 74)
+/* Sample Length Value Shift */
+#define AIC3204_BEEP4_LENGTH_VSHIFT	8
+/* Sample Length Shift */
+#define AIC3204_BEEP4_LENGTH_SHIFT	0
+/* Sample Length Mask */
+#define AIC3204_BEEP4_LENGTH		(0xff)
+
+/* Beep Generator Register 5 */
+#define AIC3204_BEEP5			AIC3204_PGREG(0, 75)
+/* Sample Length Value Shift */
+#define AIC3204_BEEP5_LENGTH_VSHIFT	0
+/* Sample Length Shift */
+#define AIC3204_BEEP5_LENGTH_SHIFT	0
+/* Sample Length Mask */
+#define AIC3204_BEEP5_LENGTH		(0xff)
+
+/* Beep Generator Register 6 */
+#define AIC3204_BEEP6			AIC3204_PGREG(0, 76)
+/* Relative Sine Frequency Value Shift */
+#define AIC3204_BEEP6_SINFREQ_VSHIFT	8
+/* Relative Sine Frequency Shift */
+#define AIC3204_BEEP6_SINFREQ_SHIFT	0
+/* Relative Sine Frequency Mask */
+#define AIC3204_BEEP6_SINFREQ		(0xff)
+
+/* Beep Generator Register 7 */
+#define AIC3204_BEEP7			AIC3204_PGREG(0, 77)
+/* Relative Sine Frequency Value Shift */
+#define AIC3204_BEEP7_SINFREQ_VSHIFT	0
+/* Relative Sine Frequency Shift */
+#define AIC3204_BEEP7_SINFREQ_SHIFT	0
+/* Relative Sine Frequency Mask */
+#define AIC3204_BEEP7_SINFREQ		(0xff)
+
+/* Beep Generator Register 8 */
+#define AIC3204_BEEP8			AIC3204_PGREG(0, 78)
+/* Relative Cosine Frequency Value Shift */
+#define AIC3204_BEEP8_COSFREQ_VSHIFT	8
+/* Relative Cosine Frequency Shift */
+#define AIC3204_BEEP8_COSFREQ_SHIFT	0
+/* Relative Cosine Frequency Mask */
+#define AIC3204_BEEP8_COSFREQ		(0xff)
+
+/* Beep Generator Register 9 */
+#define AIC3204_BEEP9			AIC3204_PGREG(0, 79)
+/* Relative Cosine Frequency Value Shift */
+#define AIC3204_BEEP9_COSFREQ_VSHIFT	0
+/* Relative Cosine Frequency Shift */
+#define AIC3204_BEEP9_COSFREQ_SHIFT	0
+/* Relative Cosine Frequency Mask */
+#define AIC3204_BEEP9_COSFREQ		(0xff)
+
+/* ADC Channel Setup Register */
+#define AIC3204_ADCS			AIC3204_PGREG(0, 81)
+/* Left Channel ADC Powered Up */
+#define AIC3204_ADCS_LADC_UP_SHIFT	(7)
+/* Right Channel ADC Powered Up */
+#define AIC3204_ADCS_RADC_UP_SHIFT	(6)
+/* Digital Microphone Input: GPIO */
+#define AIC3204_ADC5_DMICIN_GPIO	(0 << 4)
+/* Digital Microphone Input: SCLK */
+#define AIC3204_ADC5_DMICIN_SCLK	(1 << 4)
+/* Digital Microphone Input: DIN */
+#define AIC3204_ADC5_DMICIN_DIN		(2 << 4)
+/* Digital Microphone Input Mask */
+#define AIC3204_ADC5_DMICIN		(3 << 4)
+/* Left ADC Source: Digital Microphone */
+#define AIC3204_ADC5_LADC_DMIC		(1 << 3)
+/* Right ADC Source: Digital Microphone */
+#define AIC3204_ADC5_RADC_DMIC		(1 << 2)
+/* ADC Volume Soft Step: 1 step / word clock */
+#define AIC3204_ADC5_VOLSS_1SPWC	(0 << 0)
+/* ADC Volume Soft Step: 1 step / 2 word clocks */
+#define AIC3204_ADC5_VOLSS_1SP2WC	(1 << 0)
+/* ADC Volume Soft Step: Disabled */
+#define AIC3204_ADC5_VOLSS_DISABLED	(2 << 0)
+/* ADC Volume Soft Step Mask */
+#define AIC3204_ADC5_VOLSS		(3 << 0)
+
+/* ADC Fine Gain Adjust Register */
+#define AIC3204_ADCFINE			AIC3204_PGREG(0, 82)
+/* Left ADC Mute */
+#define AIC3204_ADCFINE_LEFT_MUTE	(1 << 7)
+/* Left ADC Gain: 0dB */
+#define AIC3204_ADCFINE_LEFT_0DB	(0 << 4)
+/* Left ADC Gain: -0.1dB */
+#define AIC3204_ADCFINE_LEFT_0DB1	(1 << 4)
+/* Left ADC Gain: -0.2dB */
+#define AIC3204_ADCFINE_LEFT_0DB2	(2 << 4)
+/* Left ADC Gain: -0.3dB */
+#define AIC3204_ADCFINE_LEFT_0DB3	(2 << 4)
+/* Left ADC Gain: -0.4dB */
+#define AIC3204_ADCFINE_LEFT_0DB4	(3 << 4)
+/* Left ADC Gain Mask */
+#define AIC3204_ADCFINE_LEFT		(7 << 4)
+/* Right ADC Mute */
+#define AIC3204_ADCFINE_RIGHT_MUTE	(1 << 3)
+/* Right ADC Gain: 0dB */
+#define AIC3204_ADCFINE_RIGHT_0DB	(0 << 0)
+/* Right ADC Gain: -0.1dB */
+#define AIC3204_ADCFINE_RIGHT_0DB1	(1 << 0)
+/* Right ADC Gain: -0.2dB */
+#define AIC3204_ADCFINE_RIGHT_0DB2	(2 << 0)
+/* Right ADC Gain: -0.3dB */
+#define AIC3204_ADCFINE_RIGHT_0DB3	(2 << 0)
+/* Right ADC Gain: -0.4dB */
+#define AIC3204_ADCFINE_RIGHT_0DB4	(3 << 0)
+/* Right ADC Gain Mask */
+#define AIC3204_ADCFINE_RIGHT		(7 << 0)
+
+/* Left ADC Channel Volume Register */
+#define AIC3204_LADCVOL			AIC3204_PGREG(0, 83)
+/* Left ADC Channel Volume Mask */
+#define AIC3204_LADCVOL_MASK		0x7f
+
+/* Right ADC Channel Volume Register */
+#define AIC3204_RADCVOL			AIC3204_PGREG(0, 84)
+/* Right ADC Channel Volume Mask */
+#define AIC3204_RADCVOL_MASK		0x7f
+
+/* ADC Phase Adjust Register */
+#define AIC3204_ADCPHASE		AIC3204_PGREG(0, 85)
+
+/* Left Channel AGC Control Register 1 */
+#define AIC3204_LAGC1			AIC3204_PGREG(0, 86)
+/* Left Channel AGC Enabled */
+#define AIC3204_LAGC1_ENABLE		(1 << 7)
+/* Left Channel Target Level: -5.5dBFS */
+#define AIC3204_LAGC1_LEVEL_5DBFS5	(0 << 4)
+/* Left Channel Target Level: -8.0dBFS */
+#define AIC3204_LAGC1_LEVEL_8DBFS	(1 << 4)
+/* Left Channel Target Level: -10dBFS */
+#define AIC3204_LAGC1_LEVEL_10DBFS	(2 << 4)
+/* Left Channel Target Level: -12dBFS */
+#define AIC3204_LAGC1_LEVEL_12DBFS	(3 << 4)
+/* Left Channel Target Level: -14dBFS */
+#define AIC3204_LAGC1_LEVEL_14DBFS	(4 << 4)
+/* Left Channel Target Level: -17dBFS */
+#define AIC3204_LAGC1_LEVEL_17DBFS	(5 << 4)
+/* Left Channel Target Level: -20dBFS */
+#define AIC3204_LAGC1_LEVEL_20DBFS	(6 << 4)
+/* Left Channel Target Level: -24dBFS */
+#define AIC3204_LAGC1_LEVEL_24DBFS	(7 << 4)
+/* Left Channel Target Level Mask */
+#define AIC3204_LAGC1_LEVEL		(7 << 4)
+/* Left Channel Gain Hysteresis: Disabled */
+#define AIC3204_LAGC1_GAINHYST_DISABLED	(0 << 0)
+/* Left Channel Gain Hysteresis: 0.5dB */
+#define AIC3204_LAGC1_GAINHYST_0DB5	(1 << 0)
+/* Left Channel Gain Hysteresis: 1dB */
+#define AIC3204_LAGC1_GAINHYST_1DB	(2 << 0)
+/* Left Channel Gain Hysteresis: 1.5dB */
+#define AIC3204_LAGC1_GAINHYST_1DB5	(3 << 0)
+/* Left Channel Gain Hysteresis Mask */
+#define AIC3204_LAGC1_GAINHYST		(3 << 0)
+
+/* Left Channel AGC Control Register 2 */
+#define AIC3204_LAGC2			AIC3204_PGREG(0, 87)
+/* Left Channel AGC Hysteresis: 1dB */
+#define AIC3204_LAGC2_HYST_1DB		(0 << 6)
+/* Left Channel AGC Hysteresis: 2dB */
+#define AIC3204_LAGC2_HYST_2DB		(1 << 6)
+/* Left Channel AGC Hysteresis: 4dB */
+#define AIC3204_LAGC2_HYST_4DB		(2 << 6)
+/* Left Channel AGC Hysteresis: Disabled */
+#define AIC3204_LAGC2_HYST_DISABLED	(3 << 6)
+/* Left Channel AGC Hysteresis Mask */
+#define AIC3204_LAGC2_HYST		(3 << 6)
+/* Left Channel AGC Noise Gate Threshold Mask */
+#define AIC3204_LAGC2_NGATE		(0x1f)
+/* Left Channel AGC Noise Gate Threshold Shift */
+#define AIC3204_LAGC2_NGATE_SHIFT	1
+
+/* TODO: Remaining AGC registers, DC measurement registers */
+
+/* Power Configuration Register */
+#define AIC3204_POWER			AIC3204_PGREG(1, 1)
+/* Disable AVDD -> DVDD Link */
+#define AIC3204_POWER_AVDD_DVDD_UNLINK	(1 << 3)
+
+/* LDO Control Register */
+#define AIC3204_LDO			AIC3204_PGREG(1, 2)
+/* DVDD LDO: 1.72V */
+#define AIC3204_LDO_DVDD_1V72		(0 << 6)
+/* DVDD LDO: 1.67V */
+#define AIC3204_LDO_DVDD_1V67		(1 << 6)
+/* DVDD LDO: 1.77V */
+#define AIC3204_LDO_DVDD_1V77		(2 << 6)
+/* DVDD LDO Mask */
+#define AIC3204_LDO_DVDD		(3 << 6)
+/* AVDD LDO: 1.72V */
+#define AIC3204_LDO_AVDD_1V72		(0 << 4)
+/* AVDD LDO: 1.67V */
+#define AIC3204_LDO_AVDD_1V67		(1 << 4)
+/* AVDD LDO: 1.77V */
+#define AIC3204_LDO_AVDD_1V77		(2 << 4)
+/* AVDD LDO Mask */
+#define AIC3204_LDO_AVDD		(3 << 4)
+/* Analog Blocks Enabled */
+#define AIC3204_LDO_ANALOG_ENABLED	(0 << 3)
+/* Analog Blocks Disabled */
+#define AIC3204_LDO_ANALOG_DISABLED	(1 << 3)
+/* Analog Block Status */
+#define AIC3204_LDO_ANALOG		(1 << 3)
+/* DVDD Over Current Detect */
+#define AIC3204_LDO_DVDD_OVERCURRENT	(1 << 2)
+/* AVDD Over Current Detect */
+#define AIC3204_LDO_AVDD_OVERCURRENT	(1 << 1)
+/* AVDD Powered Up */
+#define AIC3204_LDO_AVDD_UP		(1 << 0)
+
+/* TODO: Playback Configuration Registers */
+
+/* Output Driver Power Control Register */
+#define AIC3204_OUTDRV			AIC3204_PGREG(1, 9)
+/* Left Headphone Driver Up */
+#define AIC3204_OUTDRV_HPL_UP_SHIFT	(5)
+/* Right Headphone Driver Up */
+#define AIC3204_OUTDRV_HPR_UP_SHIFT	(4)
+/* Left Line Output Driver Up */
+#define AIC3204_OUTDRV_LOL_UP_SHIFT	(3)
+/* Right Line Output Driver Up */
+#define AIC3204_OUTDRV_LOR_UP_SHIFT	(2)
+/* Left Mixer Amplifier Up */
+#define AIC3204_OUTDRV_MAL_UP_SHIFT	(1)
+/* Right Mixer Amplifier Up */
+#define AIC3204_OUTDRV_MAR_UP_SHIFT	(0)
+
+/* Common Mode Control Register */
+#define AIC3204_CMCTL			AIC3204_PGREG(1, 10)
+/* Full Chip Common Mode = 0.9V */
+#define AIC3204_CMCTL_FCCM_0V9		(0 << 6)
+/* Full Chip Common Mode = 0.75V */
+#define AIC3204_CMCTL_FCCM_0V75		(1 << 6)
+/* Full Chip Common Mode Mask */
+#define AIC3204_CMCTL_FCCM		(1 << 6)
+/* Headphone Output Common Mode = Full Chip Common Mode */
+#define AIC3204_CMCTL_HPCM_FCCM		(0 << 4)
+/* Headphone Output Common Mode = 1.25V */
+#define AIC3204_CMCTL_HPCM_1V25		(1 << 4)
+/* Headphone Output Common Mode = 1.5V */
+#define AIC3204_CMCTL_HPCM_1V5		(2 << 4)
+/* Headphone Output Common Mode = 1.65V */
+#define AIC3204_CMCTL_HPCM_1V65		(3 << 4)
+/* Headphone Output Common Mode Mask */
+#define AIC3204_CMCTL_HPCM		(3 << 4)
+/* Line Output Common Mode = Full Chip Common Mode */
+#define AIC3204_CMCTL_LOCM_FCCM		(0 << 3)
+/* Line Output Common Mode = 1.65V from LDOin */
+#define AIC3204_CMCTL_LOCM_1V65LDOIN	(1 << 3)
+/* Line Output Common Mode Mask */
+#define AIC3204_CMCTL_LOCM		(1 << 3)
+/* Headphone Output Common Mode Source = AVDD */
+#define AIC3204_CMCTL_HPCMSRC_AVDD	(0 << 1)
+/* Headphone Output Common Mode Source = LDOin */
+#define AIC3204_CMCTL_HPCMSRC_LDOIN	(1 << 1)
+/* Headphone Output Common Mode Source Mask */
+#define AIC3204_CMCTL_HPCMSRC		(1 << 1)
+/* LDO Input Range = 1.5~1.95V */
+#define AIC3204_CMCTL_LDORANGE_1V5_1V95	(0 << 0)
+/* LDO Input Range = 1.8~3.6V */
+#define AIC3204_CMCTL_LDORANGE_1V8_3V6	(1 << 0)
+/* LDO Input Range Mask (effective when HPCMSRC = LDOIN) */
+#define AIC3204_CMCTL_LDORANGE		(1 << 0)
+
+/* Over Current Protection Configuration Register TODO */
+#define AIC3204_OCP			AIC3204_PGREG(1, 11)
+
+/* Left Headphone Driver Routing Register */
+#define AIC3204_HPLROUTE		AIC3204_PGREG(1, 12)
+/* Left Headphone Driver connects to LDAC+ */
+#define AIC3204_HPLROUTE_LDACP_SHIFT	(3)
+/* Left Headphone Driver connects to IN1L */
+#define AIC3204_HPLROUTE_IN1L_SHIFT	(2)
+/* Left Headphone Driver connects to MAL */
+#define AIC3204_HPLROUTE_MAL_SHIFT	(1)
+/* Left Headphone Driver connects to MAR */
+#define AIC3204_HPLROUTE_MAR_SHIFT	(0)
+
+/* Right Headphone Driver Routing Register */
+#define AIC3204_HPRROUTE		AIC3204_PGREG(1, 13)
+/* Right Headphone Driver connects to LDAC- */
+#define AIC3204_HPRROUTE_LDACN_SHIFT	(4)
+/* Right Headphone Driver connects to RDAC+ */
+#define AIC3204_HPRROUTE_RDACP_SHIFT	(3)
+/* Right Headphone Driver connects to IN1L */
+#define AIC3204_HPRROUTE_IN1R_SHIFT	(2)
+/* Right Headphone Driver connects to MAL */
+#define AIC3204_HPRROUTE_MAR_SHIFT	(1)
+/* Right Headphone Driver connects to HPL */
+#define AIC3204_HPRROUTE_HPL_SHIFT	(0)
+
+/* Left Line Output Routing Register */
+#define AIC3204_LOLROUTE		AIC3204_PGREG(1, 14)
+/* Left Line Output Driver connects to RDAC- */
+#define AIC3204_LOLROUTE_RDACN_SHIFT	(4)
+/* Left Line Output Driver connects to LDAC+ */
+#define AIC3204_LOLROUTE_LDACP_SHIFT	(3)
+/* Left Line Output Driver connects to MAL */
+#define AIC3204_LOLROUTE_MAL_SHIFT	(1)
+/* Left Line Output Driver connects to LOR */
+#define AIC3204_LOLROUTE_LOR_SHIFT	(0)
+
+/* Right Line Output Routing Register */
+#define AIC3204_LORROUTE		AIC3204_PGREG(1, 15)
+/* Right Line Output Driver connects to RDAC+ */
+#define AIC3204_LORROUTE_RDACP_SHIFT	(3)
+/* Right Line Output Driver connects to MAR */
+#define AIC3204_LORROUTE_MAR_SHIFT	(1)
+
+/* Left Headphone Gain Setting Register */
+#define AIC3204_HPLGAIN			AIC3204_PGREG(1, 16)
+/* Left Headphone Mute */
+#define AIC3204_HPLGAIN_MUTE_SHIFT	(6)
+/* Left Headphone Gain Mask */
+#define AIC3204_HPLGAIN_MASK		(0x3f)
+
+/* Right Headphone Gain Setting Register */
+#define AIC3204_HPRGAIN			AIC3204_PGREG(1, 17)
+/* Right Headphone Mute */
+#define AIC3204_HPRGAIN_MUTE_SHIFT	(6)
+/* Right Headphone Gain Mask */
+#define AIC3204_HPRGAIN_MASK		(0x3f)
+
+/* Left Line Output Gain Setting Register */
+#define AIC3204_LOLGAIN			AIC3204_PGREG(1, 18)
+/* Left Line Output Mute */
+#define AIC3204_LOLGAIN_MUTE_SHIFT	(6)
+/* Left Line Output Gain Mask */
+#define AIC3204_LOLGAIN_MASK		(0x3f)
+
+/* Right Line Output Gain Setting Register */
+#define AIC3204_LORGAIN			AIC3204_PGREG(1, 19)
+/* Right Line Output Mute */
+#define AIC3204_LORGAIN_MUTE_SHIFT	(6)
+/* Right Line Output Gain Mask */
+#define AIC3204_LORGAIN_MASK		(0x3f)
+
+/* Left Mixer Amplifier Gain Setting Register */
+#define AIC3204_MALGAIN			AIC3204_PGREG(1, 24)
+/* Left Mixer Amplifier Gain Mask */
+#define AIC3204_MALGAIN_MASK		(0x3f)
+
+/* Right Mixer Amplifier Gain Setting Register */
+#define AIC3204_MARGAIN			AIC3204_PGREG(1, 25)
+/* Right Mixer Amplifier Gain Mask */
+#define AIC3204_MARGAIN_MASK		(0x3f)
+
+#define AIC3204_MICBIAS			AIC3204_PGREG(1, 51)
+
+#define AIC3204_LMICPGAPROUTE		AIC3204_PGREG(1, 52)
+#define AIC3204_LMICPGANROUTE		AIC3204_PGREG(1, 54)
+
+#define AIC3204_RMICPGAPROUTE		AIC3204_PGREG(1, 55)
+#define AIC3204_RMICPGANROUTE		AIC3204_PGREG(1, 57)
+
+#define AIC3204_LMICPGAVOL		AIC3204_PGREG(1, 59)
+#define AIC3204_RMICPGAVOL		AIC3204_PGREG(1, 60)
+
+/* ADC Power Tune Mode Register */
+#define AIC3204_ADCPTM			AIC3204_PGREG(1, 61)
+/* ADC Power Tune Mode: PTM_R4 */
+#define AIC3204_ADCPTM_R4		(0x00)
+/* ADC Power Tune Mode: PTM_R3 */
+#define AIC3204_ADCPTM_R3		(0x64)
+/* ADC Power Tune Mode: PTM_R2 */
+#define AIC3204_ADCPTM_R2		(0xb6)
+/* ADC Power Tune Mode: PTM_R1 */
+#define AIC3204_ADCPTM_R1		(0xff)
+
+/* Analogue Input Quick Charging Configuration Register */
+#define AIC3204_AIQC			AIC3204_PGREG(1, 71)
+/* Power up time: Default Value (whatever that is) */
+#define AIC3204_AIQC_PWRUP_DEFAULT	(0x00)
+/* Power up time: 3.1ms */
+#define AIC3204_AIQC_PWRUP_3M1S		(0x31)
+/* Power up time: 6.4ms */
+#define AIC3204_AIQC_PWRUP_6M4S		(0x32)
+/* Power up time: 1.6ms */
+#define AIC3204_AIQC_PWRUP_1M6S		(0x33)
+/* Power up time mask */
+#define AIC3204_AIQC_PWRUP		(0x3f)
+
+/* Reference Power-Up Configuration Register */
+#define AIC3204_REFPU			AIC3204_PGREG(1, 123)
+/* Reference Power-Up delay: Slow */
+#define AIC3204_REFPU_DELAY_SLOW	(0 << 0)
+/* Reference Power-Up delay: 40ms */
+#define AIC3204_REFPU_DELAY_40MS	(1 << 0)
+/* Reference Power-Up delay: 80ms */
+#define AIC3204_REFPU_DELAY_80MS	(2 << 0)
+/* Reference Power-Up delay: 120ms */
+#define AIC3204_REFPU_DELAY_120MS	(3 << 0)
+/* Force power-up */
+#define AIC3204_REFPU_FORCE		(1 << 2)
+
+/* TODO: Define the remaining registers ... this will do for now */
+
+extern struct snd_soc_dai aic3204_dai;
+extern struct snd_soc_codec_device soc_codec_dev_aic3204;
+
+#endif /* _AIC3204_H */
-- 
1.6.4.4



From ivo.clarysse at gmail.com  Sun Jun 20 05:09:03 2010
From: ivo.clarysse at gmail.com (Ivo Clarysse)
Date: Sun, 20 Jun 2010 11:09:03 +0200
Subject: [PATCH 4/5] mtd: mxc_nand fixups
In-Reply-To: <80sk4ivkga.fsf@merkur.tec.linutronix.de>
References: <804oh0b7gx.fsf@merkur.tec.linutronix.de>
	<20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
Message-ID: <AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>

On Sat, Jun 19, 2010 at 10:25 PM, John Ogness <john.ogness at linutronix.de>wrote:

> On 2010-06-18, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> >> This patch reverts the driver to enabling/disabling the NFC interrupt
> >> mask rather than enabling/disabling the system interrupt. This cleans
> >> up the driver so that it doesn't rely on interrupts being disabled
> >> within the interrupt handler.
> >
> > This behaviour was introduced in
> > a47bfd2eb66837653dc3b42541dfe4283dd41251 mxc_nand: support i.MX21
> >
> > I guess this won't work on i.MX21.
>
> I just downloaded the i.MX21 reference manual and its NFC interrupts can
> also be masked with INT_MASK (bit 4) of NFC_Flash_Config1 (0xdf003e1a).
>
> IMHO we should revert the driver to masking the NFC interrupts. The
> current linux-next version with nosync irq disabling within the
> interrupt handler is a bit silly. Especially since the interrupt handler
> does nothing except signal a wait queue.
>
> John Ogness
>

Yes, on i.MX21, NFC interrupts can be masked using NFC_CONFIG1:NFC_INT_MSK.
But I observed that as long as NFC_INT_MSK is set, NFC_CONFIG2:NFC_INT will
always read out 0 on i.MX21, even if the operation is completed.

So the driver will remain stuck at:

                       wait_event(host->irq_waitq,
                               readw(host->regs + NFC_CONFIG2) & NFC_INT);

This behavior is not documented by Freescale (Freescale's (linux 2.4) i.MX21
reference kernel avoid this by always using polling).

Ivo.
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From saeed.bishara at gmail.com  Sun Jun 20 07:49:56 2010
From: saeed.bishara at gmail.com (saeed bishara)
Date: Sun, 20 Jun 2010 06:49:56 -0500
Subject: [PATCH 1/2 v2] mv643xx_eth: use sw csum for big packets
In-Reply-To: <20100614093237.GG14513@mail.wantstofly.org>
References: <FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>
	<1276073483-17208-1-git-send-email-saeed@marvell.com>
	<20100610064330.GK1743@mail.wantstofly.org>
	<FCBE654890C0334289D0AD3AF4EF009F9FAC75AA96@IL-MB01.marvell.com>
	<20100612083137.GO1743@mail.wantstofly.org>
	<FCBE654890C0334289D0AD3AF4EF009F9FAC7B6E2B@IL-MB01.marvell.com>
	<20100614093237.GG14513@mail.wantstofly.org>
Message-ID: <AANLkTik1QFcRKy95sLTr6MlPfhEyR84iTCcAzpuSg47D@mail.gmail.com>

On Mon, Jun 14, 2010 at 4:32 AM, Lennert Buytenhek
<buytenh at wantstofly.org> wrote:
> On Sun, Jun 13, 2010 at 10:38:10AM +0300, Saeed Bishara wrote:
>
>> >> >> @@ -2666,6 +2668,9 @@ static int
>> >> >mv643xx_eth_shared_probe(struct platform_device *pdev)
>> >> >> ? ? ? ? ?* Detect hardware parameters.
>> >> >> ? ? ? ? ?*/
>> >> >> ? ? ? ? msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk
>> >> >: 133000000;
>> >> >> + ? ? ? msp->tx_csum_limit = pd->tx_csum_limit ?
>> >> >pd->tx_csum_limit : 9 * 1024;
>> >> >> + ? ? ? /* add header count so we can compare against skb->len */
>> >> >> + ? ? ? msp->tx_csum_limit += ETH_HLEN;
>> >> >> ? ? ? ? infer_hw_params(msp);
>> >> >
>> >> >Is the limit 9 * 1024 + 14 for the whole packet, or 9 *
>> >1024 for the IP
>> >> >part?
>> >>
>> >> the limit is for the IP part, but I thought that adding the
>> >header length, then comparing agains skb->len will be the
>> >same. What do you suggest?
>> >
>> >Right, but for the header length you take 14, while if to include VLAN
>> >tags or DSA tags the header might actually be longer -- how does that
>> >affect the ability of the hardware to compute the checksum?
>> >
>> >I.e. is the restriction "total packet length must be < N + 14 bytes"
>> >or is it "the IP part must be < N bytes and it doesn't matter whether
>> >there are VLAN tags or not"?
>>
>> It's the second option: "the IP part must be < N" regardless to the L2 header.
>
> Then I suppose you want to do something like:
>
> ? ? ? ?int hdr_len;
> ? ? ? ?int tag_bytes;
>
> ? ? ? ?hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
> ? ? ? ?tag_bytes = hdr_len - 4;
that should be 14 instead of 4, right?
> ? ? ? ?if (skb->len - hdr_len > the limit || unlikely(tag_bytes & ~12)) {
>
> (And then keep the limit as maximum number of bytes in the packet
> starting from the IP header part.)
ok. here is the updated patch:

From saeed at marvell.com  Sun Jun  6 07:40:49 2010
From: saeed at marvell.com (Saeed Bishara)
Date: Sun, 6 Jun 2010 14:40:49 +0300
Subject: [PATCH 1/2 v3] mv643xx_eth: use sw csum for big packets
Message-ID: <mailman.53.1277034601.27306.linux-arm-kernel@lists.infradead.org>

Some controllers (KW, Dove) limits the TX IP/layer4 checksum
offloading to a max size.

Signed-off-by: Saeed Bishara <saeed at marvell.com>
---
 drivers/net/mv643xx_eth.c   |    9 +++++++--
 include/linux/mv643xx_eth.h |    5 +++++
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/drivers/net/mv643xx_eth.c b/drivers/net/mv643xx_eth.c
index e345ec8..73bb8ea 100644
--- a/drivers/net/mv643xx_eth.c
+++ b/drivers/net/mv643xx_eth.c
@@ -289,6 +289,7 @@ struct mv643xx_eth_shared_private {
 	unsigned int t_clk;
 	int extended_rx_coal_limit;
 	int tx_bw_control;
+	int tx_csum_limit;
 };

 #define TX_BW_CONTROL_ABSENT		0
@@ -776,13 +777,16 @@ static int txq_submit_skb(struct tx_queue *txq,
struct sk_buff *skb)
 	l4i_chk =3D 0;

 	if (skb->ip_summed =3D=3D CHECKSUM_PARTIAL) {
+		int hdr_len;
 		int tag_bytes;

 		BUG_ON(skb->protocol !=3D htons(ETH_P_IP) &&
 		       skb->protocol !=3D htons(ETH_P_8021Q));

-		tag_bytes =3D (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
-		if (unlikely(tag_bytes & ~12)) {
+		hdr_len =3D (void *)ip_hdr(skb) - (void *)skb->data;
+		tag_bytes =3D hdr_len - ETH_HLEN;
+		if (skb->len - hdr_len > mp->shared->tx_csum_limit ||
+		    unlikely(tag_bytes & ~12)) {
 			if (skb_checksum_help(skb) =3D=3D 0)
 				goto no_csum;
 			kfree_skb(skb);
@@ -2666,6 +2670,7 @@ static int mv643xx_eth_shared_probe(struct
platform_device *pdev)
 	 * Detect hardware parameters.
 	 */
 	msp->t_clk =3D (pd !=3D NULL && pd->t_clk !=3D 0) ? pd->t_clk : 133000000=
;
+	msp->tx_csum_limit =3D pd->tx_csum_limit ? pd->tx_csum_limit : 9 * 1024;
 	infer_hw_params(msp);

 	platform_set_drvdata(pdev, msp);
diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
index cbbbe9b..30b0c4e 100644
--- a/include/linux/mv643xx_eth.h
+++ b/include/linux/mv643xx_eth.h
@@ -19,6 +19,11 @@ struct mv643xx_eth_shared_platform_data {
 	struct mbus_dram_target_info	*dram;
 	struct platform_device	*shared_smi;
 	unsigned int		t_clk;
+	/*
+	 * Max packet size for Tx IP/Layer 4 checksum, when set to 0, default
+	 * limit of 9KiB will be used.
+	 */
+	int			tx_csum_limit;
 };

 #define MV643XX_ETH_PHY_ADDR_DEFAULT	0
--=20
1.6.0.4


From buytenh at wantstofly.org  Sun Jun 20 07:58:59 2010
From: buytenh at wantstofly.org (Lennert Buytenhek)
Date: Sun, 20 Jun 2010 13:58:59 +0200
Subject: [PATCH 1/2 v2] mv643xx_eth: use sw csum for big packets
In-Reply-To: <AANLkTik1QFcRKy95sLTr6MlPfhEyR84iTCcAzpuSg47D@mail.gmail.com>
References: <FCBE654890C0334289D0AD3AF4EF009F9FAC75A69C@IL-MB01.marvell.com>
	<1276073483-17208-1-git-send-email-saeed@marvell.com>
	<20100610064330.GK1743@mail.wantstofly.org>
	<FCBE654890C0334289D0AD3AF4EF009F9FAC75AA96@IL-MB01.marvell.com>
	<20100612083137.GO1743@mail.wantstofly.org>
	<FCBE654890C0334289D0AD3AF4EF009F9FAC7B6E2B@IL-MB01.marvell.com>
	<20100614093237.GG14513@mail.wantstofly.org>
	<AANLkTik1QFcRKy95sLTr6MlPfhEyR84iTCcAzpuSg47D@mail.gmail.com>
Message-ID: <20100620115859.GT14513@mail.wantstofly.org>

On Sun, Jun 20, 2010 at 06:49:56AM -0500, saeed bishara wrote:

> >> >> >> @@ -2666,6 +2668,9 @@ static int
> >> >> >mv643xx_eth_shared_probe(struct platform_device *pdev)
> >> >> >> ? ? ? ? ?* Detect hardware parameters.
> >> >> >> ? ? ? ? ?*/
> >> >> >> ? ? ? ? msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk
> >> >> >: 133000000;
> >> >> >> + ? ? ? msp->tx_csum_limit = pd->tx_csum_limit ?
> >> >> >pd->tx_csum_limit : 9 * 1024;
> >> >> >> + ? ? ? /* add header count so we can compare against skb->len */
> >> >> >> + ? ? ? msp->tx_csum_limit += ETH_HLEN;
> >> >> >> ? ? ? ? infer_hw_params(msp);
> >> >> >
> >> >> >Is the limit 9 * 1024 + 14 for the whole packet, or 9 *
> >> >1024 for the IP
> >> >> >part?
> >> >>
> >> >> the limit is for the IP part, but I thought that adding the
> >> >header length, then comparing agains skb->len will be the
> >> >same. What do you suggest?
> >> >
> >> >Right, but for the header length you take 14, while if to include VLAN
> >> >tags or DSA tags the header might actually be longer -- how does that
> >> >affect the ability of the hardware to compute the checksum?
> >> >
> >> >I.e. is the restriction "total packet length must be < N + 14 bytes"
> >> >or is it "the IP part must be < N bytes and it doesn't matter whether
> >> >there are VLAN tags or not"?
> >>
> >> It's the second option: "the IP part must be < N" regardless to the L2 header.
> >
> > Then I suppose you want to do something like:
> >
> > ? ? ? ?int hdr_len;
> > ? ? ? ?int tag_bytes;
> >
> > ? ? ? ?hdr_len = (void *)ip_hdr(skb) - (void *)skb->data;
> > ? ? ? ?tag_bytes = hdr_len - 4;
>
> that should be 14 instead of 4, right?

Yes, sorry.


> > ? ? ? ?if (skb->len - hdr_len > the limit || unlikely(tag_bytes & ~12)) {
> >
> > (And then keep the limit as maximum number of bytes in the packet
> > starting from the IP header part.)
>
> ok. here is the updated patch:
> >From 009530d4220dd710737d5a357629edcbc102727a Mon Sep 17 00:00:00 2001
> From: Saeed Bishara <saeed at marvell.com>
> Date: Sun, 6 Jun 2010 14:40:49 +0300
> Subject: [PATCH 1/2 v3] mv643xx_eth: use sw csum for big packets
> 
> Some controllers (KW, Dove) limits the TX IP/layer4 checksum
> offloading to a max size.
> 
> Signed-off-by: Saeed Bishara <saeed at marvell.com>

Looks good!

Acked-by: Lennert Buytenhek <buytenh at wantstofly.org>


From eric.miao at canonical.com  Sun Jun 20 10:00:49 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Sun, 20 Jun 2010 22:00:49 +0800
Subject: [PATCH 1/2] [ARM] Introduce 'struct machine_class' for SoC level
	abstraction
Message-ID: <1277042450-30382-1-git-send-email-eric.miao@canonical.com>

From: Eric Miao <eric.y.miao at gmail.com>

For machine class (mostly equivalent to SoC) level abstraction.

The modification to head.S is preliminary, working but possibly
can be made more elegant.

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/include/asm/mach/arch.h |   13 +++++++++++++
 arch/arm/kernel/asm-offsets.c    |    4 ++++
 arch/arm/kernel/head-common.S    |    3 +++
 arch/arm/kernel/head.S           |   12 +++++++++---
 arch/arm/kernel/setup.c          |   14 ++++++++++----
 arch/arm/mm/mmu.c                |    5 ++++-
 6 files changed, 43 insertions(+), 8 deletions(-)

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index c59842d..214ca29 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -14,6 +14,18 @@ struct tag;
 struct meminfo;
 struct sys_timer;
 
+struct machine_class {
+	unsigned int		phys_io;	/* start of physical io	*/
+	unsigned int		io_pg_offst;	/* byte offset for io
+						 * page tabe entry	*/
+	const char		*name;		/* machine class name	*/
+	unsigned long		boot_params;	/* tagged list		*/
+
+	void			(*map_io)(void);/* IO mapping function */
+	void			(*init_irq)(void);
+	struct sys_timer	*timer;
+};
+
 struct machine_desc {
 	/*
 	 * Note! The first four elements are used
@@ -25,6 +37,7 @@ struct machine_desc {
 						 * page tabe entry	*/
 
 	const char		*name;		/* architecture name	*/
+	struct machine_class	*class;		/* machine class */
 	unsigned long		boot_params;	/* tagged list		*/
 
 	unsigned int		video_start;	/* start of video RAM	*/
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 8835115..5c9038a 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -101,6 +101,10 @@ int main(void)
   DEFINE(MACHINFO_NAME,		offsetof(struct machine_desc, name));
   DEFINE(MACHINFO_PHYSIO,	offsetof(struct machine_desc, phys_io));
   DEFINE(MACHINFO_PGOFFIO,	offsetof(struct machine_desc, io_pg_offst));
+  DEFINE(MACHINFO_CLASS,	offsetof(struct machine_desc, class));
+  BLANK();
+  DEFINE(MACHCLASS_PHYSIO,	offsetof(struct machine_class, phys_io));
+  DEFINE(MACHCLASS_PGOFFIO,	offsetof(struct machine_class, io_pg_offst));
   BLANK();
   DEFINE(PROC_INFO_SZ,		sizeof(struct proc_info_list));
   DEFINE(PROCINFO_INITFUNC,	offsetof(struct proc_info_list, __cpu_flush));
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index b9505aa..660756b 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -207,6 +207,7 @@ ENDPROC(lookup_processor_type)
  * Returns:
  *  r3, r4, r6 corrupted
  *  r5 = mach_info pointer in physical address space
+ *  r7 = machine_class pointer in physical address space
  */
 __lookup_machine_type:
 	adr	r3, 4b
@@ -214,6 +215,8 @@ __lookup_machine_type:
 	sub	r3, r3, r4			@ get offset between virt&phys
 	add	r5, r5, r3			@ convert virt addresses to
 	add	r6, r6, r3			@ physical address space
+	ldr	r7, [r5, #MACHINFO_CLASS]	@ get machine class
+	add	r7, r7, r3
 1:	ldr	r3, [r5, #MACHINFO_TYPE]	@ get machine type
 	teq	r3, r1				@ matches loader number?
 	beq	2f				@ found
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..06f8834 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -82,8 +82,9 @@ ENTRY(stext)
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
 	beq	__error_p			@ yes, error 'p'
-	bl	__lookup_machine_type		@ r5=machinfo
+	bl	__lookup_machine_type		@ r5=machinfo,r7=machine_class
 	movs	r8, r5				@ invalid machine (r5=0)?
+	mov	r11, r7
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
 	bl	__create_page_tables
@@ -211,6 +212,7 @@ ENDPROC(__turn_mmu_on)
  * r8  = machinfo
  * r9  = cpuid
  * r10 = procinfo
+ * r11 = machine_class
  *
  * Returns:
  *  r0, r3, r6, r7 corrupted
@@ -295,13 +297,17 @@ __create_page_tables:
 	 * This allows debug messages to be output
 	 * via a serial console before paging_init.
 	 */
-	ldr	r3, [r8, #MACHINFO_PGOFFIO]
+	cmp	r11, #0
+	ldrne	r3, [r11, #MACHCLASS_PGOFFIO]
+	ldreq	r3, [r8, #MACHINFO_PGOFFIO]
 	add	r0, r4, r3
 	rsb	r3, r3, #0x4000			@ PTRS_PER_PGD*sizeof(long)
 	cmp	r3, #0x0800			@ limit to 512MB
 	movhi	r3, #0x0800
 	add	r6, r0, r3
-	ldr	r3, [r8, #MACHINFO_PHYSIO]
+	cmp	r11, #0
+	ldrne	r3, [r11, #MACHCLASS_PHYSIO]
+	ldreq	r3, [r8, #MACHINFO_PHYSIO]
 	orr	r3, r3, r7
 1:	str	r3, [r0], #4
 	add	r3, r3, #1 << 20
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 122d999..e5627da 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -667,12 +667,14 @@ void __init setup_arch(char **cmdline_p)
 {
 	struct tag *tags = (struct tag *)&init_tags;
 	struct machine_desc *mdesc;
+	struct machine_class *class;
 	char *from = default_command_line;
 
 	unwind_init();
 
 	setup_processor();
 	mdesc = setup_machine(machine_arch_type);
+	class = mdesc->class;
 	machine_name = mdesc->name;
 
 	if (mdesc->soft_reboot)
@@ -680,8 +682,12 @@ void __init setup_arch(char **cmdline_p)
 
 	if (__atags_pointer)
 		tags = phys_to_virt(__atags_pointer);
-	else if (mdesc->boot_params)
-		tags = phys_to_virt(mdesc->boot_params);
+	else {
+		unsigned long boot_params = class ? class->boot_params :
+						    mdesc->boot_params;
+		if (boot_params)
+			tags = phys_to_virt(boot_params);
+	}
 
 	/*
 	 * If we have the old style parameters, convert them to
@@ -729,8 +735,8 @@ void __init setup_arch(char **cmdline_p)
 	/*
 	 * Set up various architecture-specific pointers
 	 */
-	init_arch_irq = mdesc->init_irq;
-	system_timer = mdesc->timer;
+	init_arch_irq = class ? class->init_irq : mdesc->init_irq;
+	system_timer = class ? class->timer : mdesc->timer;
 	init_machine = mdesc->init_machine;
 
 #ifdef CONFIG_VT
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 2858941..2af11dc 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -933,6 +933,7 @@ void __init reserve_node_zero(pg_data_t *pgdat)
  */
 static void __init devicemaps_init(struct machine_desc *mdesc)
 {
+	struct machine_class *class = mdesc->class;
 	struct map_desc map;
 	unsigned long addr;
 	void *vectors;
@@ -995,7 +996,9 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 	/*
 	 * Ask the machine support to map in the statically mapped devices.
 	 */
-	if (mdesc->map_io)
+	if (class && class->map_io)
+		class->map_io();
+	else if (mdesc->map_io)
 		mdesc->map_io();
 
 	/*
-- 
1.7.1



From eric.miao at canonical.com  Sun Jun 20 10:00:50 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Sun, 20 Jun 2010 22:00:50 +0800
Subject: [PATCH 2/2] [ARM] pxa: make use of 'struct machine_class'
In-Reply-To: <1277042450-30382-1-git-send-email-eric.miao@canonical.com>
References: <1277042450-30382-1-git-send-email-eric.miao@canonical.com>
Message-ID: <1277042450-30382-2-git-send-email-eric.miao@canonical.com>

From: Eric Miao <eric.y.miao at gmail.com>

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/mach-pxa/ezx.c      |   60 ++++-------------------------------------
 arch/arm/mach-pxa/generic.h  |   15 ++++++++++
 arch/arm/mach-pxa/hx4700.c   |   10 +------
 arch/arm/mach-pxa/magician.c |    9 +-----
 arch/arm/mach-pxa/pxa25x.c   |   11 +++++++
 arch/arm/mach-pxa/pxa27x.c   |   11 +++++++
 6 files changed, 46 insertions(+), 70 deletions(-)

diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index 626c82b..2f4c8f1 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -795,15 +795,7 @@ static void __init a780_init(void)
 	platform_add_devices(ARRAY_AND_SIZE(a780_devices));
 }
 
-MACHINE_START(EZX_A780, "Motorola EZX A780")
-	.phys_io        = 0x40000000,
-	.io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params    = 0xa0000100,
-	.map_io         = pxa_map_io,
-	.init_irq       = pxa27x_init_irq,
-	.timer          = &pxa_timer,
-	.init_machine   = a780_init,
-MACHINE_END
+PXA27X_MACHINE(EZX_A780, a780_init, "Motorola EZX A780");
 #endif
 
 #ifdef CONFIG_MACH_EZX_E680
@@ -861,15 +853,7 @@ static void __init e680_init(void)
 	platform_add_devices(ARRAY_AND_SIZE(e680_devices));
 }
 
-MACHINE_START(EZX_E680, "Motorola EZX E680")
-	.phys_io        = 0x40000000,
-	.io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params    = 0xa0000100,
-	.map_io         = pxa_map_io,
-	.init_irq       = pxa27x_init_irq,
-	.timer          = &pxa_timer,
-	.init_machine   = e680_init,
-MACHINE_END
+PXA27X_MACHINE(EZX_E680, e680_init, "Motorola EZX E680");
 #endif
 
 #ifdef CONFIG_MACH_EZX_A1200
@@ -927,15 +911,7 @@ static void __init a1200_init(void)
 	platform_add_devices(ARRAY_AND_SIZE(a1200_devices));
 }
 
-MACHINE_START(EZX_A1200, "Motorola EZX A1200")
-	.phys_io        = 0x40000000,
-	.io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params    = 0xa0000100,
-	.map_io         = pxa_map_io,
-	.init_irq       = pxa27x_init_irq,
-	.timer          = &pxa_timer,
-	.init_machine   = a1200_init,
-MACHINE_END
+PXA27X_MACHINE(EZX_A1200, a1200_init, "Motorola EZX A1200");
 #endif
 
 #ifdef CONFIG_MACH_EZX_A910
@@ -1119,15 +1095,7 @@ static void __init a910_init(void)
 	platform_add_devices(ARRAY_AND_SIZE(a910_devices));
 }
 
-MACHINE_START(EZX_A910, "Motorola EZX A910")
-	.phys_io        = 0x40000000,
-	.io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params    = 0xa0000100,
-	.map_io         = pxa_map_io,
-	.init_irq       = pxa27x_init_irq,
-	.timer          = &pxa_timer,
-	.init_machine   = a910_init,
-MACHINE_END
+PXA27X_MACHINE(EZX_A910, a910_init, "Motorola EZX A910");
 #endif
 
 #ifdef CONFIG_MACH_EZX_E6
@@ -1185,15 +1153,7 @@ static void __init e6_init(void)
 	platform_add_devices(ARRAY_AND_SIZE(e6_devices));
 }
 
-MACHINE_START(EZX_E6, "Motorola EZX E6")
-	.phys_io        = 0x40000000,
-	.io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params    = 0xa0000100,
-	.map_io         = pxa_map_io,
-	.init_irq       = pxa27x_init_irq,
-	.timer          = &pxa_timer,
-	.init_machine   = e6_init,
-MACHINE_END
+PXA27X_MACHINE(EZX_E6, e6_init, "Motorola EZX E6");
 #endif
 
 #ifdef CONFIG_MACH_EZX_E2
@@ -1225,13 +1185,5 @@ static void __init e2_init(void)
 	platform_add_devices(ARRAY_AND_SIZE(e2_devices));
 }
 
-MACHINE_START(EZX_E2, "Motorola EZX E2")
-	.phys_io        = 0x40000000,
-	.io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params    = 0xa0000100,
-	.map_io         = pxa_map_io,
-	.init_irq       = pxa27x_init_irq,
-	.timer          = &pxa_timer,
-	.init_machine   = e2_init,
-MACHINE_END
+PXA27X_MACHINE(EZX_E2, e2_init, "Motorola EZX E2");
 #endif
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index 890fb90..6b6d767 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -72,3 +72,18 @@ void __init pxa_set_ffuart_info(void *info);
 void __init pxa_set_btuart_info(void *info);
 void __init pxa_set_stuart_info(void *info);
 void __init pxa_set_hwuart_info(void *info);
+
+extern struct machine_class machine_class_pxa25x;
+extern struct machine_class machine_class_pxa27x;
+
+#define PXA25X_MACHINE(_type,_init,_name)		\
+MACHINE_START(_type,_name)				\
+	.class		= &machine_class_pxa25x,	\
+	.init_machine	= _init,			\
+}
+
+#define PXA27X_MACHINE(_type,_init,_name)		\
+MACHINE_START(_type,_name)				\
+	.class		= &machine_class_pxa27x,	\
+	.init_machine	= _init,			\
+}
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 848c861..a1b1587 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -869,12 +869,4 @@ static void __init hx4700_init(void)
 	mdelay(10);
 }
 
-MACHINE_START(H4700, "HP iPAQ HX4700")
-	.phys_io      = 0x40000000,
-	.io_pg_offst  = (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params  = 0xa0000100,
-	.map_io       = pxa_map_io,
-	.init_irq     = pxa27x_init_irq,
-	.init_machine = hx4700_init,
-	.timer        = &pxa_timer,
-MACHINE_END
+PXA27X_MACHINE_START(H4700, hx4700_init, "HP iPAQ HX4700");
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index e81dd0c..6a86f22 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -764,11 +764,6 @@ static void __init magician_init(void)
 
 
 MACHINE_START(MAGICIAN, "HTC Magician")
-	.phys_io = 0x40000000,
-	.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params = 0xa0000100,
-	.map_io = pxa_map_io,
-	.init_irq = pxa27x_init_irq,
-	.init_machine = magician_init,
-	.timer = &pxa_timer,
+	.class		= &machine_class_pxa27x,
+	.init_machine	= magician_init,
 MACHINE_END
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 0b9ad30..8993df6 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -23,6 +23,7 @@
 #include <linux/suspend.h>
 #include <linux/sysdev.h>
 
+#include <asm/mach/arch.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/gpio.h>
@@ -341,6 +342,16 @@ static struct sys_device pxa25x_sysdev[] = {
 	},
 };
 
+struct machine_class machine_class_pxa25x __initdata = {
+	.name		= "PXA25x",
+	.phys_io	= 0x40000000,
+	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
+	.boot_params	= 0xa0000100,
+	.timer		= &pxa_timer,
+	.map_io		= pxa_map_io,
+	.init_irq	= pxa25x_init_irq,
+};
+
 static int __init pxa25x_init(void)
 {
 	int i, ret = 0;
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 0af3617..d64b194 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 
+#include <asm/mach/arch.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <mach/irqs.h>
@@ -403,6 +404,16 @@ static struct sys_device pxa27x_sysdev[] = {
 	},
 };
 
+struct machine_class machine_class_pxa27x __initdata = {
+	.name		= "PXA27x",
+	.phys_io	= 0x40000000,
+	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
+	.boot_params	= 0xa0000100,
+	.timer		= &pxa_timer,
+	.map_io		= pxa_map_io,
+	.init_irq	= pxa27x_init_irq,
+};
+
 static int __init pxa27x_init(void)
 {
 	int i, ret = 0;
-- 
1.7.1



From ospite at studenti.unina.it  Sun Jun 20 12:08:17 2010
From: ospite at studenti.unina.it (Antonio Ospite)
Date: Sun, 20 Jun 2010 18:08:17 +0200
Subject: [PATCH 2/2] [ARM] pxa: make use of 'struct machine_class'
In-Reply-To: <1277042450-30382-2-git-send-email-eric.miao@canonical.com>
References: <1277042450-30382-1-git-send-email-eric.miao@canonical.com>
	<1277042450-30382-2-git-send-email-eric.miao@canonical.com>
Message-ID: <20100620180817.2de11de2.ospite@studenti.unina.it>

On Sun, 20 Jun 2010 22:00:50 +0800
Eric Miao <eric.miao at canonical.com> wrote:

> From: Eric Miao <eric.y.miao at gmail.com>
> 
> Signed-off-by: Eric Miao <eric.miao at canonical.com>
> ---
>  arch/arm/mach-pxa/ezx.c      |   60 ++++-------------------------------------

The ezx part looks OK. A comment about magician below.

[...]
> diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
> index e81dd0c..6a86f22 100644
> --- a/arch/arm/mach-pxa/magician.c
> +++ b/arch/arm/mach-pxa/magician.c
> @@ -764,11 +764,6 @@ static void __init magician_init(void)
>  
>  
>  MACHINE_START(MAGICIAN, "HTC Magician")
> -	.phys_io = 0x40000000,
> -	.io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
> -	.boot_params = 0xa0000100,
> -	.map_io = pxa_map_io,
> -	.init_irq = pxa27x_init_irq,
> -	.init_machine = magician_init,
> -	.timer = &pxa_timer,
> +	.class		= &machine_class_pxa27x,
> +	.init_machine	= magician_init,
>  MACHINE_END

Magician can use PXA27X_MACHINE() as well, can't it?

[...]

Regards,
   Antonio

-- 
Antonio Ospite
http://ao2.it

PGP public key ID: 0x4553B001

A: Because it messes up the order in which people normally read text.
   See http://en.wikipedia.org/wiki/Posting_style
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?
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From eric at eukrea.com  Sun Jun 20 15:22:54 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Sun, 20 Jun 2010 21:22:54 +0200
Subject: [PATCH] eukrea_mbimx27: fix audio support when SOC is compiled as
	module
Message-ID: <1277061774-24309-1-git-send-email-eric@eukrea.com>

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
index 2e57912..75559aa 100644
--- a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
@@ -96,7 +96,8 @@ static int eukrea_mbimx27_pins[] = {
 	PD30_PF_CSPI1_MISO,
 	PD31_PF_CSPI1_MOSI,
 	/* SSI4 */
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
+	|| defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
 	PC16_PF_SSI4_FS,
 	PC17_PF_SSI4_RXD | GPIO_PUEN,
 	PC18_PF_SSI4_TXD | GPIO_PUEN,
@@ -338,7 +339,8 @@ void __init eukrea_mbimx27_baseboard_init(void)
 	mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
 		ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
 
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320) \
+	|| defined(CONFIG_SND_SOC_EUKREA_TLV320_MODULE)
 	/* SSI unit master I2S codec connected to SSI_PINS_4*/
 	mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
 			MXC_AUDMUX_V1_PCR_SYN |
-- 
1.6.3.3



From ryan at bluewatersys.com  Sun Jun 20 17:31:26 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Mon, 21 Jun 2010 09:31:26 +1200
Subject: gpiolib and sleeping gpios
In-Reply-To: <386783.17931.qm@web180310.mail.gq1.yahoo.com>
References: <386783.17931.qm@web180310.mail.gq1.yahoo.com>
Message-ID: <4C1E88AE.5070808@bluewatersys.com>

On 06/19/2010 06:21 PM, David Brownell wrote:
> 
>>
>> The runtime warnings will only show instances where the
>> non-sleeping
>> versions where called instead of the sleeping versions.
> 
> ... *AND* the GPIO requires the cansleep() version...
> 
> Right; such calls are errors.  We issue
> warnings since fault returns are inapplicable.

A driver which only uses the non-sleeping versions, but _could_ use the
cansleep variants (ie all calls to gpio_(set/get)_value are made from
contexts where it is possible to sleep) is not so easy to spot. Passing
a sleeping to gpio to such a driver will result in spurious warnings.

>> There is no
>> warning to say that we are calling the spinlock safe
>> version, where it is possible to sleep.
> 
> The call context isn't what controls whether
> gpio_get_value() or gpio_get_value_cansleep()
> is appropriate ... it's the GPIO itself, and
> how its implementation works.

No, a driver should not know anything about a gpio which is passed to
it. If a driver is able to call the cansleep variants, then it should,
and it will allow any gpio, sleeping or non-sleeping, to be used with
that driver.

If a driver uses a gpio in such a way that it cannot sleep, ie the
gpio_(get/set)_value calls are made from spinlock context, then only
gpios which do not sleep may be used with that driver.

Thats why I think specifying whether the gpio is able to sleep when it
is requested is a good idea. A driver which cannot use a sleeping gpio


> "possible to sleep" is a GPIO attribute,
> exposed by a predicate.  If spinlock-safe
> calls are used on GPIOs with that attribute,
>  a warning *IS* issued.

Possible to sleep is also an attribute of how a driver _uses_ a gpio.

>>
>> The point I was trying to make is that there are lots of
>> drivers which
>> will not work with gpios on sleeping io expanders because
>> they call the
>> spinlock safe gpio calls.
> 
> And they will trigger runtime warnings, and
> thus eventually get fixed.  The way to do that
> is to check if the GPIO needs the cansleep()
> call

Hmm, maybe this then for drivers which cannot accept sleeping gpios:

  if (gpio_cansleep(some_gpio)) {
  	  dev_err(&dev, "This driver only supports non-sleeping gpios");
	  return -EINVAL;
  }

  err = gpio_request(some_gpio, "some_gpio");

I think ideally, gpio_request should specify this via a flags argument, ie:

  #define GPIOF_NO_SLEEP	0x0
  #define GPIOF_CANSLEEP	0x1

  err = gpio_request(some_gpio, "some_gpio", GPIOF_NO_SLEEP);

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From orenl at cs.columbia.edu  Sun Jun 20 17:34:10 2010
From: orenl at cs.columbia.edu (Oren Laadan)
Date: Sun, 20 Jun 2010 17:34:10 -0400
Subject: [C/R ARM v2][PATCH 0/3] Linux Checkpoint-Restart - ARM port
In-Reply-To: <1272318223-28438-1-git-send-email-christofferdall@christofferdall.dk>
References: <1272318223-28438-1-git-send-email-christofferdall@christofferdall.dk>
Message-ID: <4C1E8952.7010503@cs.columbia.edu>

Applied.

On 04/26/2010 05:43 PM, Christoffer Dall wrote:
> Following there will be two preparatory patches for an ARM port of the
> checkpoint-restart code and finally a third patch implementing the
> architecture-specific parts of c/r.
> 
> The preparatory patches consist of a partial syscall trace implementation
> for ARM and an eclone implementation for ARM. The syscall trace
> implementation provides only the needed functionality for c/r.
> 
> There is a separate patch for the user space code, which supports
> cross-compilation, extracting headers for ARM and an eclone implementation
> for ARM.
> 
> The kernel patches presented here are based on the ckpt-v21-rc6 patch set.
> 
> ---
> 
> CHANGELOG:
> 
> [2010-Apr-08] v2:
> 	- Systrace implementation now inspects process state to get the
> 	  system call number thereby avoiding extra work on system calls.
> 	- Removed __user attribute on long type in eclone implementation
> 	- Better check for architecture versions across C/R
> 	- Improved checking of user space ABI settings across C/R
> 	- Code simplifications
> 
> [2010-Mar-22] v1:
> 	- Initial version
> 	- Systrace implementation modified the system call entry path to
> 	  store the system call number globally in memory.
> 	- ARM implementation lightly tested
> _______________________________________________
> Containers mailing list
> Containers at lists.linux-foundation.org
> https://lists.linux-foundation.org/mailman/listinfo/containers
> 


From ben-linux at fluff.org  Sun Jun 20 18:38:17 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Sun, 20 Jun 2010 23:38:17 +0100
Subject: [PATCH 1/2] NUC900:  Add i2c0 driver support for NUC900
In-Reply-To: <4C15143C.1020603@gmail.com>
References: <4C15143C.1020603@gmail.com>
Message-ID: <20100620223817.GC12387@fluff.org.uk>

On Mon, Jun 14, 2010 at 01:24:12AM +0800, Wan ZongShun wrote:
> This patch is to add i2c0 driver support for NUC900.
> 
> Signed-off-by: Wan ZongShun <mcuos.com at gmail.com>
> 
> ---
>  arch/arm/mach-w90x900/include/mach/i2c.h |   11 +
>  drivers/i2c/busses/Kconfig               |    7 +
>  drivers/i2c/busses/Makefile              |    1 +
>  drivers/i2c/busses/i2c-nuc900.c          |  699 ++++++++++++++++++++++++++++++
>  4 files changed, 718 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-w90x900/include/mach/i2c.h
>  create mode 100644 drivers/i2c/busses/i2c-nuc900.c
> 
> diff --git a/arch/arm/mach-w90x900/include/mach/i2c.h b/arch/arm/mach-w90x900/include/mach/i2c.h
> new file mode 100644
> index 0000000..292f3f9
> --- /dev/null
> +++ b/arch/arm/mach-w90x900/include/mach/i2c.h
> @@ -0,0 +1,11 @@
> +#ifndef __ASM_ARCH_NUC900_I2C_H
> +#define __ASM_ARCH_NUC900_I2C_H
> +
> +struct nuc900_platform_i2c {
> +	int		bus_num;
> +	unsigned long   bus_freq;
> +	void	(*get_clock)(unsigned int *cpuclk_khz,
> +			unsigned int *ahbclk_khz, unsigned int *apbclk_khz);
> +};
> +
> +#endif /* __ASM_ARCH_NUC900_I2C_H */
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index bceafbf..ee284d2 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -448,6 +448,13 @@ config I2C_NOMADIK
>  	  If you say yes to this option, support will be included for the
>  	  I2C interface from ST-Ericsson's Nomadik and Ux500 architectures.
> 
> +config I2C_NUC900
> +	tristate "NUC900 I2C Driver"
> +	depends on ARCH_W90X900
> +	help
> +	  Say Y here to include support for I2C controller in the
> +	  Winbond/Nuvoton NUC900 based System-on-Chip devices.
> +
>  config I2C_OCORES
>  	tristate "OpenCores I2C Controller"
>  	depends on EXPERIMENTAL
> diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile
> index 936880b..c3ef492 100644
> --- a/drivers/i2c/busses/Makefile
> +++ b/drivers/i2c/busses/Makefile
> @@ -43,6 +43,7 @@ obj-$(CONFIG_I2C_IXP2000)	+= i2c-ixp2000.o
>  obj-$(CONFIG_I2C_MPC)		+= i2c-mpc.o
>  obj-$(CONFIG_I2C_MV64XXX)	+= i2c-mv64xxx.o
>  obj-$(CONFIG_I2C_NOMADIK)	+= i2c-nomadik.o
> +obj-$(CONFIG_I2C_NUC900)	+= i2c-nuc900.o
>  obj-$(CONFIG_I2C_OCORES)	+= i2c-ocores.o
>  obj-$(CONFIG_I2C_OMAP)		+= i2c-omap.o
>  obj-$(CONFIG_I2C_PASEMI)	+= i2c-pasemi.o
> diff --git a/drivers/i2c/busses/i2c-nuc900.c b/drivers/i2c/busses/i2c-nuc900.c
> new file mode 100644
> index 0000000..c8e043a
> --- /dev/null
> +++ b/drivers/i2c/busses/i2c-nuc900.c
> @@ -0,0 +1,699 @@
> +/*
> + * linux/drivers/i2c/busses/i2c-nuc900.c
> + *
> + * Copyright (c) 2010 Nuvoton technology corporation.
> + *
> + * This driver based on S3C2410 I2C Controller of Ben Dooks <ben at simtec.co.uk>.
> + * Written by Wan ZongShun <mcuos.com at gmail.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation;version 2 of the License.
> + *
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +
> +#include <linux/i2c.h>
> +#include <linux/i2c-id.h>
> +#include <linux/init.h>
> +#include <linux/time.h>
> +#include <linux/interrupt.h>
> +#include <linux/delay.h>
> +#include <linux/errno.h>
> +#include <linux/err.h>
> +#include <linux/platform_device.h>
> +#include <linux/clk.h>
> +#include <linux/cpufreq.h>
> +#include <linux/slab.h>
> +#include <linux/io.h>
> +
> +#include <mach/mfp.h>
> +#include <mach/i2c.h>
> +
> +#define CSR		0x00
> +#define DIVIDER		0x04
> +#define CMDR		0x08
> +#define SWR		0x0C
> +#define RXR		0x10
> +#define TXR		0x14
> +
> +#define IRQEN		0x003
> +#define I2CBUSY		0x400
> +#define I2CSTART	0x018
> +
> +#define I2C_CMD_START	0x10
> +#define I2C_CMD_STOP	0x08
> +#define I2C_CMD_READ	0x04
> +#define I2C_CMD_WRITE	0x02
> +#define I2C_CMD_NACK	0x01
> +
> +#define IRQFLAG		0x004
> +#define ARBIT_LOST	0x200
> +#define SLAVE_ACK	0x800
> +
> +/* i2c controller state */
> +
> +enum nuc900_i2c_state {
> +	STATE_IDLE,
> +	STATE_START,
> +	STATE_READ,
> +	STATE_WRITE,
> +	STATE_STOP
> +};
> +
> +struct nuc900_i2c {
> +	spinlock_t		lock;
> +	wait_queue_head_t	wait;
> +
> +	struct i2c_msg		*msg;
> +	unsigned int		msg_num;
> +	unsigned int		msg_idx;
> +	unsigned int		msg_ptr;
> +	unsigned int		irq;
> +
> +	enum nuc900_i2c_state	state;
> +
> +	void __iomem		*regs;
> +	struct clk		*clk;
> +	struct device		*dev;
> +	struct resource		*ioarea;
> +	struct i2c_adapter	adap;
> +};

would be nice to document these.

> +/* nuc900_i2c_master_complete
> + *
> + * complete the message and wake up the caller, using the given return code,
> + * or zero to mean ok.
> +*/
> +
> +static inline void nuc900_i2c_master_complete(struct nuc900_i2c *i2c, int ret)
> +{
> +	dev_dbg(i2c->dev, "master_complete %d\n", ret);
> +
> +	i2c->msg_ptr = 0;
> +	i2c->msg = NULL;
> +	i2c->msg_idx++;
> +	i2c->msg_num = 0;
> +	if (ret)
> +		i2c->msg_idx = ret;
> +
> +	wake_up(&i2c->wait);
> +}
> +
> +/* irq enable/disable functions */
> +
> +static inline void nuc900_i2c_disable_irq(struct nuc900_i2c *i2c)
> +{
> +	unsigned long tmp;
> +
> +	tmp = readl(i2c->regs + CSR);
> +	writel(tmp & ~IRQEN, i2c->regs + CSR);
> +}
> +
> +static inline void nuc900_i2c_enable_irq(struct nuc900_i2c *i2c)
> +{
> +	unsigned long tmp;
> +
> +	tmp = readl(i2c->regs + CSR);
> +	writel(tmp | IRQEN, i2c->regs + CSR);
> +}

might be easeir to have an call to set the irq state?

> +
> +/* nuc900_i2c_message_start
> + *
> + * put the start of a message onto the bus
> +*/
> +
> +static void nuc900_i2c_message_start(struct nuc900_i2c *i2c,
> +				      struct i2c_msg *msg)
> +{
> +	unsigned int addr = (msg->addr & 0x7f) << 1;
> +
> +	if (msg->flags & I2C_M_RD)
> +		addr |= 0x1;
> +	writel(addr & 0xff, i2c->regs + TXR);
> +	writel(I2C_CMD_START | I2C_CMD_WRITE, i2c->regs + CMDR);
> +}
> +
> +static inline void nuc900_i2c_stop(struct nuc900_i2c *i2c, int ret)
> +{
> +
> +	dev_dbg(i2c->dev, "STOP\n");
> +
> +	/* stop the transfer */
> +	i2c->state = STATE_STOP;
> +	writel(I2C_CMD_STOP, i2c->regs + CMDR);
> +
> +	nuc900_i2c_master_complete(i2c, ret);
> +	nuc900_i2c_disable_irq(i2c);
> +}
> +
> +/* helper functions to determine the current state in the set of
> + * messages we are sending */
> +
> +/* is_lastmsg()
> + *
> + * returns TRUE if the current message is the last in the set
> +*/
> +
> +static inline int is_lastmsg(struct nuc900_i2c *i2c)
> +{
> +	return i2c->msg_idx >= (i2c->msg_num - 1);
> +}
> +
> +/* is_msglast
> + *
> + * returns TRUE if we this is the last byte in the current message
> +*/
> +
> +static inline int is_msglast(struct nuc900_i2c *i2c)
> +{
> +	return i2c->msg_ptr == i2c->msg->len-1;
> +}
> +
> +/* is_msgend
> + *
> + * returns TRUE if we reached the end of the current message
> +*/
> +
> +static inline int is_msgend(struct nuc900_i2c *i2c)
> +{
> +	return i2c->msg_ptr >= i2c->msg->len;
> +}

maybe we should have a library header for processing i2c messages
like this.

> +/* i2s_s3c_irq_nextbyte
> + *
> + * process an interrupt and work out what to do
> + */
> +
> +static int i2s_nuc900_irq_nextbyte(struct nuc900_i2c *i2c,

not i2s, and doesn't match prototype.

maybe change the docs to kerneldoc style?

> +							unsigned long iicstat)

[snip]

> +/* nuc900_i2c_irq
> + *
> + * top level IRQ servicing routine
> +*/
> +
> +static irqreturn_t nuc900_i2c_irq(int irqno, void *dev_id)
> +{
> +	struct nuc900_i2c *i2c = dev_id;
> +	unsigned long status;
> +
> +	status = readl(i2c->regs + CSR);
> +	writel(status | IRQFLAG, i2c->regs + CSR);
> +
> +	if (status & ARBIT_LOST) {
> +		/* deal with arbitration loss */
> +		dev_err(i2c->dev, "deal with arbitration loss\n");
> +		goto out;
> +	}
> +
> +	if (i2c->state == STATE_IDLE) {
> +		dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
> +		goto out;
> +	}
> +
> +	/* pretty much this leaves us with the fact that we've
> +	 * transmitted or received whatever byte we last sent */
> +
> +	i2s_nuc900_irq_nextbyte(i2c, status);
> +
> + out:
> +	return IRQ_HANDLED;
> +}
> +
> +
> +/* nuc900_i2c_set_master
> + *
> + * get the i2c bus for a master transaction
> +*/
> +
> +static int nuc900_i2c_set_master(struct nuc900_i2c *i2c)
> +{
> +	int timeout = 400;
> +
> +	while (timeout-- > 0) {
> +		if (((readl(i2c->regs + SWR) & I2CSTART) == I2CSTART) &&
> +				((readl(i2c->regs + CSR) & I2CBUSY) == 0)) {
> +			return 0;
> +		}
> +
> +		msleep(1);
> +	}
> +
> +	return -ETIMEDOUT;
> +}
> +
> +/* nuc900_i2c_doxfer
> + *
> + * this starts an i2c transfer
> +*/
> +
> +static int nuc900_i2c_doxfer(struct nuc900_i2c *i2c,
> +			      struct i2c_msg *msgs, int num)
> +{
> +	unsigned long iicstat, timeout;
> +	int spins = 20;
> +	int ret;
> +
> +	ret = nuc900_i2c_set_master(i2c);
> +	if (ret != 0) {
> +		dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
> +		ret = -EAGAIN;
> +		goto out;
> +	}
> +
> +	spin_lock_irq(&i2c->lock);
> +
> +	i2c->msg     = msgs;
> +	i2c->msg_num = num;
> +	i2c->msg_ptr = 0;
> +	i2c->msg_idx = 0;
> +	i2c->state   = STATE_START;
> +
> +	nuc900_i2c_enable_irq(i2c);
> +	nuc900_i2c_message_start(i2c, msgs);
> +	spin_unlock_irq(&i2c->lock);
> +
> +	timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
> +
> +	ret = i2c->msg_idx;
> +
> +	/* having these next two as dev_err() makes life very
> +	 * noisy when doing an i2cdetect */
> +
> +	if (timeout == 0)
> +		dev_dbg(i2c->dev, "timeout\n");
> +	else if (ret != num)
> +		dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
> +
> +	/* ensure the stop has been through the bus */
> +
> +	dev_dbg(i2c->dev, "waiting for bus idle\n");
> +
> +	/* first, try busy waiting briefly */
> +	do {
> +		iicstat = readl(i2c->regs + CSR);
> +	} while ((iicstat & I2CBUSY) && --spins);
> +
> +	/* if that timed out sleep */
> +	if (!spins) {
> +		msleep(1);
> +		iicstat = readl(i2c->regs + CSR);
> +	}
> +
> +	if (iicstat & I2CBUSY)
> +		dev_warn(i2c->dev, "timeout waiting for bus idle\n");
> +
> + out:
> +	return ret;
> +}
> +
> +/* nuc900_i2c_xfer
> + *
> + * first port of call from the i2c bus code when an message needs
> + * transferring across the i2c bus.
> +*/
> +
> +static int nuc900_i2c_xfer(struct i2c_adapter *adap,
> +			struct i2c_msg *msgs, int num)
> +{
> +	struct nuc900_i2c *i2c = (struct nuc900_i2c *)adap->algo_data;
> +	int retry;
> +	int ret;
> +
> +	for (retry = 0; retry < adap->retries; retry++) {
> +
> +		ret = nuc900_i2c_doxfer(i2c, msgs, num);
> +
> +		if (ret != -EAGAIN)
> +			return ret;
> +
> +		dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
> +
> +		udelay(100);
> +	}
> +
> +	return -EREMOTEIO;
> +}
> +
> +/* declare our i2c functionality */
> +static u32 nuc900_i2c_func(struct i2c_adapter *adap)
> +{
> +	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
> +}
> +
> +/* i2c bus registration info */
> +
> +static const struct i2c_algorithm nuc900_i2c_algorithm = {
> +	.master_xfer		= nuc900_i2c_xfer,
> +	.functionality		= nuc900_i2c_func,
> +};
> +
> +/* nuc900_i2c_probe
> + *
> + * called by the bus driver when a suitable device is found
> +*/
> +
> +static int __devinit nuc900_i2c_probe(struct platform_device *pdev)
> +{
> +	struct nuc900_i2c *i2c;
> +	struct nuc900_platform_i2c *pdata;
> +	struct resource *res;
> +	unsigned int apbclk_khz;
> +	int ret;
> +
> +	pdata = pdev->dev.platform_data;
> +	if (!pdata) {
> +		dev_err(&pdev->dev, "no platform data\n");
> +		return -EINVAL;
> +	}
> +
> +	i2c = kzalloc(sizeof(struct nuc900_i2c), GFP_KERNEL);
> +	if (!i2c) {
> +		dev_err(&pdev->dev, "no memory for state\n");
> +		return -ENOMEM;
> +	}
> +
> +	strlcpy(i2c->adap.name, "nuc900-i2c0", sizeof(i2c->adap.name));
> +	i2c->adap.owner   = THIS_MODULE;
> +	i2c->adap.algo    = &nuc900_i2c_algorithm;
> +	i2c->adap.retries = 2;
> +	i2c->adap.class   = I2C_CLASS_HWMON | I2C_CLASS_SPD;
> +
> +	spin_lock_init(&i2c->lock);
> +	init_waitqueue_head(&i2c->wait);
> +
> +	/* find the clock and enable it */
> +
> +	i2c->dev = &pdev->dev;
> +	i2c->clk = clk_get(&pdev->dev, "nuc900-i2c0");

you really shouldn't need the second argument, the bus clock for
a device should be findable with NULL.

note, fixing the s3c series as soon as possible.

> +	if (IS_ERR(i2c->clk)) {
> +		dev_err(&pdev->dev, "cannot get clock\n");
> +		ret = -ENOENT;
> +		goto err_noclk;
> +	}
> +
> +	dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
> +
> +	clk_enable(i2c->clk);
> +
> +	/* map the registers */
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (res == NULL) {
> +		dev_err(&pdev->dev, "cannot find IO resource\n");
> +		ret = -ENOENT;
> +		goto err_clk;
> +	}
> +
> +	i2c->ioarea = request_mem_region(res->start, resource_size(res),
> +					 pdev->name);
> +
> +	if (i2c->ioarea == NULL) {
> +		dev_err(&pdev->dev, "cannot request IO\n");
> +		ret = -ENXIO;
> +		goto err_clk;
> +	}
> +
> +	i2c->regs = ioremap(res->start, resource_size(res));
> +
> +	if (i2c->regs == NULL) {
> +		dev_err(&pdev->dev, "cannot map IO\n");
> +		ret = -ENXIO;
> +		goto err_ioarea;
> +	}
> +
> +	dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
> +		i2c->regs, i2c->ioarea, res);
> +
> +	/* setup info block for the i2c core */
> +
> +	i2c->adap.algo_data = i2c;
> +	i2c->adap.dev.parent = &pdev->dev;
> +
> +	mfp_set_groupg(&pdev->dev);
> +
> +	pdata->get_clock(NULL, NULL, &apbclk_khz);

clk_get_rate() should be used here.


> +	ret = apbclk_khz/(pdata->bus_freq * 5) - 1;
> +	writel(ret & 0xffff, i2c->regs + DIVIDER);
> +
> +	/* find the IRQ for this unit (note, this relies on the init call to
> +	 * ensure no current IRQs pending
> +	 */
> +
> +	i2c->irq = ret = platform_get_irq(pdev, 0);
> +	if (ret <= 0) {
> +		dev_err(&pdev->dev, "cannot find IRQ\n");
> +		goto err_iomap;
> +	}
> +
> +	ret = request_irq(i2c->irq, nuc900_i2c_irq, IRQF_DISABLED,
> +			  dev_name(&pdev->dev), i2c);

do you really want to run this with all irqs disabled?

> +	if (ret != 0) {
> +		dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
> +		goto err_iomap;
> +	}
> +
> +	/* Note, previous versions of the driver used i2c_add_adapter()
> +	 * to add the bus at any number. We now pass the bus number via
> +	 * the platform data, so if unset it will now default to always
> +	 * being bus 0.
> +	 */
> +
> +	i2c->adap.nr = pdata->bus_num;
> +
> +	ret = i2c_add_numbered_adapter(&i2c->adap);
> +	if (ret < 0) {
> +		dev_err(&pdev->dev, "failed to add bus to i2c core\n");
> +		goto err_irq;
> +	}
> +
> +	platform_set_drvdata(pdev, i2c);
> +
> +	dev_info(&pdev->dev, "%s: NUC900 I2C adapter\n",
> +						dev_name(&i2c->adap.dev));
> +	return 0;
> +
> + err_irq:
> +	free_irq(i2c->irq, i2c);
> +
> + err_iomap:
> +	iounmap(i2c->regs);
> +
> + err_ioarea:
> +	release_resource(i2c->ioarea);
> +	kfree(i2c->ioarea);
> +
> + err_clk:
> +	clk_disable(i2c->clk);
> +	clk_put(i2c->clk);
> +
> + err_noclk:
> +	kfree(i2c);
> +	return ret;
> +}
> +
> +/* nuc900_i2c_remove
> + *
> + * called when device is removed from the bus
> +*/
> +
> +static int __devexit nuc900_i2c_remove(struct platform_device *pdev)
> +{
> +	struct nuc900_i2c *i2c = platform_get_drvdata(pdev);
> +
> +	i2c_del_adapter(&i2c->adap);
> +	free_irq(i2c->irq, i2c);
> +
> +	clk_disable(i2c->clk);
> +	clk_put(i2c->clk);
> +
> +	iounmap(i2c->regs);
> +
> +	release_resource(i2c->ioarea);
> +	kfree(i2c->ioarea);
> +	kfree(i2c);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver nuc900_i2c_driver = {
> +	.probe		= nuc900_i2c_probe,
> +	.remove		= __devexit_p(nuc900_i2c_remove),
> +	.driver		= {
> +		.owner	= THIS_MODULE,
> +		.name	= "nuc900-i2c0",
> +	},
> +};
> +
> +static int __init i2c_adap_nuc900_init(void)
> +{
> +	return platform_driver_register(&nuc900_i2c_driver);
> +}
> +
> +static void __exit i2c_adap_nuc900_exit(void)
> +{
> +	platform_driver_unregister(&nuc900_i2c_driver);
> +}
> +subsys_initcall(i2c_adap_nuc900_init);
> +module_exit(i2c_adap_nuc900_exit);
> +
> +MODULE_DESCRIPTION("NUC900 I2C Bus driver");
> +MODULE_AUTHOR("Wan ZongShun, <mcuos.com at gmail.com>");
> +MODULE_LICENSE("GPL");
> +MODULE_ALIAS("platform:nuc900-i2c0");

-- 
Ben (ben at fluff.org, http://www.fluff.org/)

  'a smiley only costs 4 bytes'


From linus.walleij at stericsson.com  Sun Jun 20 19:17:09 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 21 Jun 2010 01:17:09 +0200
Subject: [PATCH] ux500: use neutral PRCMU base
Message-ID: <1277075829-1051-1-git-send-email-linus.walleij@stericsson.com>

The MTU wallclock timing fix-up patch was hardwired to the DB8500
causing a regression. This makes it work on the DB5500 as well.

Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/mach-ux500/clock.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index fe84b90..0a1318f 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -131,7 +131,7 @@ EXPORT_SYMBOL(clk_disable);
  */
 static unsigned long clk_mtu_get_rate(struct clk *clk)
 {
-	void __iomem *addr = __io_address(U8500_PRCMU_BASE)
+	void __iomem *addr = __io_address(UX500_PRCMU_BASE)
 		+ PRCM_TCR;
 	u32 tcr = readl(addr);
 	int mtu = (int) clk->data;
-- 
1.6.3.3



From eric.miao at canonical.com  Sun Jun 20 21:06:33 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Mon, 21 Jun 2010 09:06:33 +0800
Subject: [PATCH 2/2] [ARM] pxa: make use of 'struct machine_class'
In-Reply-To: <20100620180817.2de11de2.ospite@studenti.unina.it>
References: <1277042450-30382-1-git-send-email-eric.miao@canonical.com> 
	<1277042450-30382-2-git-send-email-eric.miao@canonical.com> 
	<20100620180817.2de11de2.ospite@studenti.unina.it>
Message-ID: <AANLkTiklVdwCrys88T-Qy6pvFQ1Y-V7oM6IHjyznyhGX@mail.gmail.com>

On Mon, Jun 21, 2010 at 12:08 AM, Antonio Ospite
<ospite at studenti.unina.it> wrote:
> On Sun, 20 Jun 2010 22:00:50 +0800
> Eric Miao <eric.miao at canonical.com> wrote:
>
>> From: Eric Miao <eric.y.miao at gmail.com>
>>
>> Signed-off-by: Eric Miao <eric.miao at canonical.com>
>> ---
>> ?arch/arm/mach-pxa/ezx.c ? ? ?| ? 60 ++++-------------------------------------
>
> The ezx part looks OK. A comment about magician below.
>
> [...]
>> diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
>> index e81dd0c..6a86f22 100644
>> --- a/arch/arm/mach-pxa/magician.c
>> +++ b/arch/arm/mach-pxa/magician.c
>> @@ -764,11 +764,6 @@ static void __init magician_init(void)
>>
>>
>> ?MACHINE_START(MAGICIAN, "HTC Magician")
>> - ? ? .phys_io = 0x40000000,
>> - ? ? .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
>> - ? ? .boot_params = 0xa0000100,
>> - ? ? .map_io = pxa_map_io,
>> - ? ? .init_irq = pxa27x_init_irq,
>> - ? ? .init_machine = magician_init,
>> - ? ? .timer = &pxa_timer,
>> + ? ? .class ? ? ? ? ?= &machine_class_pxa27x,
>> + ? ? .init_machine ? = magician_init,
>> ?MACHINE_END
>
> Magician can use PXA27X_MACHINE() as well, can't it?

Yes, it can. Missed that :-)


From david-b at pacbell.net  Sun Jun 20 22:40:46 2010
From: david-b at pacbell.net (David Brownell)
Date: Sun, 20 Jun 2010 19:40:46 -0700 (PDT)
Subject: gpiolib and sleeping gpios
In-Reply-To: <4C1E88AE.5070808@bluewatersys.com>
Message-ID: <887171.45295.qm@web180307.mail.gq1.yahoo.com>



--- On Sun, 6/20/10, Ryan Mallon <ryan at bluewatersys.com> wrote:


> >> The point I was trying to make is that
> >> there are lots of drivers which
> >> will not work with gpios on sleeping io expandersbecause they call the
> >> spinlock safe gpio calls.

"Lots"?  You mean there are lots of
maintainers who aren't even bothering to
provide trivial fixes for bug which are
clearly reported to them by warnings?
These one-liner fixes are not hard...

Such problems are people-problems, not issues
with any framework. 
> > 
> > And they will trigger runtime warnings, and
> > thus eventually get fixed.
> \
> ? }
> 
> ? err = gpio_request(some_gpio, "some_gpio",
>           GPIOF_NO_SLEEP);


NAK ... keep it simple.  Such flags are
clearly not necessary...

I understand that some folk are bothered
by concepts/frameworks that seem "too simple"
and thus want to complexify them.  In this
case I am in a position to help avoid that.
Complexity is not a virtue.




From u.kleine-koenig at pengutronix.de  Mon Jun 21 01:09:57 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Mon, 21 Jun 2010 07:09:57 +0200
Subject: gpiolib and sleeping gpios
In-Reply-To: <887171.45295.qm@web180307.mail.gq1.yahoo.com>
References: <4C1E88AE.5070808@bluewatersys.com>
	<887171.45295.qm@web180307.mail.gq1.yahoo.com>
Message-ID: <20100621050957.GA23094@pengutronix.de>

Hi,

On Sun, Jun 20, 2010 at 07:40:46PM -0700, David Brownell wrote:
> > > And they will trigger runtime warnings, and
> > > thus eventually get fixed.
> > \
> > ? }
> > 
> > ? err = gpio_request(some_gpio, "some_gpio",
> >           GPIOF_NO_SLEEP);
> 
> 
> NAK ... keep it simple.  Such flags are
> clearly not necessary...
> 
> I understand that some folk are bothered
> by concepts/frameworks that seem "too simple"
> and thus want to complexify them.  In this
> case I am in a position to help avoid that.
> Complexity is not a virtue.
I'm against such an additional flag, too.  But I still think merging
gpio_get_value and gpio_get_value_cansleep is nice.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From baruch at tkos.co.il  Mon Jun 21 01:15:19 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Mon, 21 Jun 2010 08:15:19 +0300
Subject: [PATCH v3 1/3] mx2_camera: Add soc_camera support for
	i.MX25/i.MX27
In-Reply-To: <Pine.LNX.4.64.1006191458420.11313@axis700.grange>
References: <cover.1274865040.git.baruch@tkos.co.il>
	<190248f3b311ccfcb73f1fc71d185e3927f0bf05.1274865040.git.baruch@tkos.co.il>
	<Pine.LNX.4.64.1006191458420.11313@axis700.grange>
Message-ID: <20100621051519.GB18217@jasper.tkos.co.il>

Hi Guennadi,

On Sat, Jun 19, 2010 at 04:13:31PM +0200, Guennadi Liakhovetski wrote:
> On Wed, 26 May 2010, Baruch Siach wrote:
> 
> > This is the soc_camera support developed by Sascha Hauer for the i.MX27.  Alan
> > Carvalho de Assis modified the original driver to get it working on more recent
> > kernels. I modified it further to add support for i.MX25. This driver has been
> > tested on i.MX25 and i.MX27 based platforms.

Tanks for your review. I'll send v4 shortly.

baruch

> I hoped, this would be the final version, but if I'm not mistaken, you've 
> introduced an error, which we better fix before committing. And as we anyway 
> will likely need a v4, I'll also ask you to improve a couple of stylistic 
> issues, which otherwise I'd just fix myself with your permission.
> 
> > Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> > ---
> >  arch/arm/plat-mxc/include/mach/memory.h  |    4 +-
> >  arch/arm/plat-mxc/include/mach/mx2_cam.h |   46 +
> >  drivers/media/video/Kconfig              |   13 +
> >  drivers/media/video/Makefile             |    1 +
> >  drivers/media/video/mx2_camera.c         | 1488 ++++++++++++++++++++++++++++++
> >  5 files changed, 1550 insertions(+), 2 deletions(-)
> >  create mode 100644 arch/arm/plat-mxc/include/mach/mx2_cam.h
> >  create mode 100644 drivers/media/video/mx2_camera.c
> > 
> > diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
> > index c4b40c3..5803836 100644
> > --- a/arch/arm/plat-mxc/include/mach/memory.h
> > +++ b/arch/arm/plat-mxc/include/mach/memory.h
> 
> [snip]
> 
> > +static void mx2_videobuf_queue(struct videobuf_queue *vq,
> > +			       struct videobuf_buffer *vb)
> > +{
> > +	struct soc_camera_device *icd = vq->priv_data;
> > +	struct soc_camera_host *ici =
> > +		to_soc_camera_host(icd->dev.parent);
> > +	struct mx2_camera_dev *pcdev = ici->priv;
> > +	struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
> > +	unsigned long flags;
> > +	int ret;
> > +
> > +	dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
> > +		vb, vb->baddr, vb->bsize);
> > +
> > +	spin_lock_irqsave(&pcdev->lock, flags);
> > +
> > +	vb->state = VIDEOBUF_QUEUED;
> > +	list_add_tail(&vb->queue, &pcdev->capture);
> > +
> > +	if (mx27_camera_emma(pcdev))
> > +		goto out;
> > +	else if (cpu_is_mx27()) {
> 
> One of the minor ones - please, add braces in the "if" case.
> 
> [snip]
> 
> > +static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
> > +{
> > +	struct mx2_camera_dev *pcdev = data;
> > +	unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
> > +	struct mx2_buffer *buf;
> > +
> > +	if ((status & (3 << 5)) == (3 << 5)
> > +			&& !list_empty(&pcdev->active_bufs)) {
> > +		/*
> > +		 * Both buffers have triggered, process the one we're expecting
> > +		 * to first
> > +		 */
> > +		buf = list_entry(pcdev->active_bufs.next,
> > +			struct mx2_buffer, vb.queue);
> > +		mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE);
> > +	}
> > +	if (status & (1 << 6))
> > +		mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE);
> > +	if (status & (1 << 5))
> > +		mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE);
> 
> Now, this is the important one. In my review of v2 I proposed the above 
> fix for the both-bits-set case. But, I think, your implementation is not 
> correct. Don't you have to clear the expected buffer number, so that you 
> don't process it twice? Something like
> 
> 		status &= ~(1 << 6 - buf->bufnum);
> 
> anywhere inside the first of the three ifs?
> 
> > +	if (status & (1 << 7)) {
> 
> Bit 7 is overflow. A correct handling could be resetting the buffer, 
> returning an error frame and continuing with the next one. However, I 
> understand, that you do not have a chance to implement this properly 
> now. So, please, at least add a "FIXME" comment, explaining, what should 
> be done here. Besides, error states are normally checked before normal 
> data processing. So, either mention this in the comment too, or move this 
> above the buffer completion processing.
> 
> Thanks
> Guennadi
> ---
> Guennadi Liakhovetski, Ph.D.
> Freelance Open-Source Software Developer
> http://www.open-technology.de/

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From baruch at tkos.co.il  Mon Jun 21 01:15:57 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Mon, 21 Jun 2010 08:15:57 +0300
Subject: [PATCHv4 0/3] Driver for the i.MX2x CMOS Sensor Interface
Message-ID: <cover.1277096909.git.baruch@tkos.co.il>

This series contains a soc_camera driver for the i.MX25/i.MX27 CSI device, and
platform code for the i.MX25 and i.MX27 chips. This driver is based on a 
driver for i.MX27 CSI from Sascha Hauer, that  Alan Carvalho de Assis has 
posted in linux-media last December[1]. I tested the mx2_camera driver on the 
i.MX25 PDK. Sascha Hauer has tested a earlier version of this driver on an 
i.MX27 based board. I included in this version some fixes from Sascha that 
enable i.MX27 support.

[1] https://patchwork.kernel.org/patch/67636/

Changes v3 -> v4
    Address more comments from Guennadi Liakhovetski, including:

    * Fix the double trigger handling of mx27 eMMA

    * Add a FIXME comment in the code of eMMA overflow handling

Changes v2 -> v3
    Address more comments from Guennadi Liakhovetski.

    Applied part of Sashca's patch that I forgot in v2.

Changes v1 -> v2
    Addressed the comments of Guennadi Liakhovetski except from the following:

    1. The mclk_get_divisor implementation, since I don't know what this code 
       is good for

    2. mx2_videobuf_release should not set pcdev->active on i.MX27, because 
       mx27_camera_frame_done needs this pointer

    3. In mx27_camera_emma_buf_init I don't know the meaning of those hard 
       coded magic numbers

    Applied i.MX27 fixes from Sascha.

Baruch Siach (3):
  mx2_camera: Add soc_camera support for i.MX25/i.MX27
  mx27: add support for the CSI device
  mx25: add support for the CSI device

 arch/arm/mach-mx2/clock_imx27.c          |    2 +-
 arch/arm/mach-mx2/devices.c              |   31 +
 arch/arm/mach-mx2/devices.h              |    1 +
 arch/arm/mach-mx25/clock.c               |   14 +-
 arch/arm/mach-mx25/devices.c             |   22 +
 arch/arm/mach-mx25/devices.h             |    1 +
 arch/arm/plat-mxc/include/mach/memory.h  |    4 +-
 arch/arm/plat-mxc/include/mach/mx25.h    |    2 +
 arch/arm/plat-mxc/include/mach/mx2_cam.h |   46 +
 drivers/media/video/Kconfig              |   13 +
 drivers/media/video/Makefile             |    1 +
 drivers/media/video/mx2_camera.c         | 1493 ++++++++++++++++++++++++++++++
 12 files changed, 1625 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/plat-mxc/include/mach/mx2_cam.h
 create mode 100644 drivers/media/video/mx2_camera.c



From baruch at tkos.co.il  Mon Jun 21 01:15:58 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Mon, 21 Jun 2010 08:15:58 +0300
Subject: [PATCHv4 1/3] mx2_camera: Add soc_camera support for i.MX25/i.MX27
In-Reply-To: <cover.1277096909.git.baruch@tkos.co.il>
References: <cover.1277096909.git.baruch@tkos.co.il>
Message-ID: <03d6e55c39690618e92a91a580ec34549a135c79.1277096909.git.baruch@tkos.co.il>

This is the soc_camera support developed by Sascha Hauer for the i.MX27.  Alan
Carvalho de Assis modified the original driver to get it working on more recent
kernels. I modified it further to add support for i.MX25. This driver has been
tested on i.MX25 and i.MX27 based platforms.

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 arch/arm/plat-mxc/include/mach/memory.h  |    4 +-
 arch/arm/plat-mxc/include/mach/mx2_cam.h |   46 +
 drivers/media/video/Kconfig              |   13 +
 drivers/media/video/Makefile             |    1 +
 drivers/media/video/mx2_camera.c         | 1493 ++++++++++++++++++++++++++++++
 5 files changed, 1555 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/plat-mxc/include/mach/mx2_cam.h
 create mode 100644 drivers/media/video/mx2_camera.c

diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index c4b40c3..5803836 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -44,12 +44,12 @@
  */
 #define CONSISTENT_DMA_SIZE SZ_8M
 
-#elif defined(CONFIG_MX1_VIDEO)
+#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_MX2_VIDEO)
 /*
  * Increase size of DMA-consistent memory region.
  * This is required for i.MX camera driver to capture at least four VGA frames.
  */
 #define CONSISTENT_DMA_SIZE SZ_4M
-#endif /* CONFIG_MX1_VIDEO */
+#endif /* CONFIG_MX1_VIDEO || CONFIG_MX2_VIDEO */
 
 #endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h
new file mode 100644
index 0000000..3c080a3
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h
@@ -0,0 +1,46 @@
+/*
+ * mx2-cam.h - i.MX27/i.MX25 camera driver header file
+ *
+ * Copyright (C) 2003, Intel Corporation
+ * Copyright (C) 2008, Sascha Hauer <s.hauer at pengutronix.de>
+ * Copyright (C) 2010, Baruch Siach <baruch at tkos.co.il>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __MACH_MX2_CAM_H_
+#define __MACH_MX2_CAM_H_
+
+#define MX2_CAMERA_SWAP16		(1 << 0)
+#define MX2_CAMERA_EXT_VSYNC		(1 << 1)
+#define MX2_CAMERA_CCIR			(1 << 2)
+#define MX2_CAMERA_CCIR_INTERLACE	(1 << 3)
+#define MX2_CAMERA_HSYNC_HIGH		(1 << 4)
+#define MX2_CAMERA_GATED_CLOCK		(1 << 5)
+#define MX2_CAMERA_INV_DATA		(1 << 6)
+#define MX2_CAMERA_PCLK_SAMPLE_RISING	(1 << 7)
+#define MX2_CAMERA_PACK_DIR_MSB		(1 << 8)
+
+/**
+ * struct mx2_camera_platform_data - optional platform data for mx2_camera
+ * @flags: any combination of MX2_CAMERA_*
+ * @clk: clock rate of the csi block / 2
+ */
+struct mx2_camera_platform_data {
+	unsigned long flags;
+	unsigned long clk;
+};
+
+#endif /* __MACH_MX2_CAM_H_ */
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index bdbc9d3..47bf6e6 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -969,6 +969,19 @@ config VIDEO_OMAP2
 	---help---
 	  This is a v4l2 driver for the TI OMAP2 camera capture interface
 
+config MX2_VIDEO
+        bool
+
+config VIDEO_MX2
+	tristate "i.MX27/i.MX25 Camera Sensor Interface driver"
+	depends on VIDEO_DEV && SOC_CAMERA && (MACH_MX27 || ARCH_MX25)
+	select VIDEOBUF_DMA_CONTIG
+	select MX2_VIDEO
+	---help---
+	  This is a v4l2 driver for the i.MX27 and the i.MX25 Camera Sensor
+	  Interface
+
+
 #
 # USB Multimedia device configuration
 #
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index cc93859..b08bd2b 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -162,6 +162,7 @@ obj-$(CONFIG_SOC_CAMERA)		+= soc_camera.o soc_mediabus.o
 obj-$(CONFIG_SOC_CAMERA_PLATFORM)	+= soc_camera_platform.o
 # soc-camera host drivers have to be linked after camera drivers
 obj-$(CONFIG_VIDEO_MX1)			+= mx1_camera.o
+obj-$(CONFIG_VIDEO_MX2)			+= mx2_camera.o
 obj-$(CONFIG_VIDEO_MX3)			+= mx3_camera.o
 obj-$(CONFIG_VIDEO_PXA27x)		+= pxa_camera.o
 obj-$(CONFIG_VIDEO_SH_MOBILE_CEU)	+= sh_mobile_ceu_camera.o
diff --git a/drivers/media/video/mx2_camera.c b/drivers/media/video/mx2_camera.c
new file mode 100644
index 0000000..79ad522
--- /dev/null
+++ b/drivers/media/video/mx2_camera.c
@@ -0,0 +1,1493 @@
+/*
+ * V4L2 Driver for i.MX27/i.MX25 camera host
+ *
+ * Copyright (C) 2008, Sascha Hauer, Pengutronix
+ * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/dma-mapping.h>
+#include <linux/errno.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <linux/moduleparam.h>
+#include <linux/time.h>
+#include <linux/version.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+#include <linux/clk.h>
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-dev.h>
+#include <media/videobuf-dma-contig.h>
+#include <media/soc_camera.h>
+#include <media/soc_mediabus.h>
+
+#include <linux/videodev2.h>
+
+#include <mach/mx2_cam.h>
+#include <mach/dma-mx1-mx2.h>
+#include <mach/hardware.h>
+
+#include <asm/dma.h>
+
+#define MX2_CAM_DRV_NAME "mx2-camera"
+#define MX2_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
+#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
+
+/* reset values */
+#define CSICR1_RESET_VAL	0x40000800
+#define CSICR2_RESET_VAL	0x0
+#define CSICR3_RESET_VAL	0x0
+
+/* csi control reg 1 */
+#define CSICR1_SWAP16_EN	(1 << 31)
+#define CSICR1_EXT_VSYNC	(1 << 30)
+#define CSICR1_EOF_INTEN	(1 << 29)
+#define CSICR1_PRP_IF_EN	(1 << 28)
+#define CSICR1_CCIR_MODE	(1 << 27)
+#define CSICR1_COF_INTEN	(1 << 26)
+#define CSICR1_SF_OR_INTEN	(1 << 25)
+#define CSICR1_RF_OR_INTEN	(1 << 24)
+#define CSICR1_STATFF_LEVEL	(3 << 22)
+#define CSICR1_STATFF_INTEN	(1 << 21)
+#define CSICR1_RXFF_LEVEL(l)	(((l) & 3) << 19)	/* MX27 */
+#define CSICR1_FB2_DMA_INTEN	(1 << 20)		/* MX25 */
+#define CSICR1_FB1_DMA_INTEN	(1 << 19)		/* MX25 */
+#define CSICR1_RXFF_INTEN	(1 << 18)
+#define CSICR1_SOF_POL		(1 << 17)
+#define CSICR1_SOF_INTEN	(1 << 16)
+#define CSICR1_MCLKDIV(d)	(((d) & 0xF) << 12)
+#define CSICR1_HSYNC_POL	(1 << 11)
+#define CSICR1_CCIR_EN		(1 << 10)
+#define CSICR1_MCLKEN		(1 << 9)
+#define CSICR1_FCC		(1 << 8)
+#define CSICR1_PACK_DIR		(1 << 7)
+#define CSICR1_CLR_STATFIFO	(1 << 6)
+#define CSICR1_CLR_RXFIFO	(1 << 5)
+#define CSICR1_GCLK_MODE	(1 << 4)
+#define CSICR1_INV_DATA		(1 << 3)
+#define CSICR1_INV_PCLK		(1 << 2)
+#define CSICR1_REDGE		(1 << 1)
+
+#define SHIFT_STATFF_LEVEL	22
+#define SHIFT_RXFF_LEVEL	19
+#define SHIFT_MCLKDIV		12
+
+/* control reg 3 */
+#define CSICR3_FRMCNT		(0xFFFF << 16)
+#define CSICR3_FRMCNT_RST	(1 << 15)
+#define CSICR3_DMA_REFLASH_RFF	(1 << 14)
+#define CSICR3_DMA_REFLASH_SFF	(1 << 13)
+#define CSICR3_DMA_REQ_EN_RFF	(1 << 12)
+#define CSICR3_DMA_REQ_EN_SFF	(1 << 11)
+#define CSICR3_RXFF_LEVEL(l)	(((l) & 7) << 4)	/* MX25 */
+#define CSICR3_CSI_SUP		(1 << 3)
+#define CSICR3_ZERO_PACK_EN	(1 << 2)
+#define CSICR3_ECC_INT_EN	(1 << 1)
+#define CSICR3_ECC_AUTO_EN	(1 << 0)
+
+#define SHIFT_FRMCNT		16
+
+/* csi status reg */
+#define CSISR_SFF_OR_INT	(1 << 25)
+#define CSISR_RFF_OR_INT	(1 << 24)
+#define CSISR_STATFF_INT	(1 << 21)
+#define CSISR_DMA_TSF_FB2_INT	(1 << 20)	/* MX25 */
+#define CSISR_DMA_TSF_FB1_INT	(1 << 19)	/* MX25 */
+#define CSISR_RXFF_INT		(1 << 18)
+#define CSISR_EOF_INT		(1 << 17)
+#define CSISR_SOF_INT		(1 << 16)
+#define CSISR_F2_INT		(1 << 15)
+#define CSISR_F1_INT		(1 << 14)
+#define CSISR_COF_INT		(1 << 13)
+#define CSISR_ECC_INT		(1 << 1)
+#define CSISR_DRDY		(1 << 0)
+
+#define CSICR1			0x00
+#define CSICR2			0x04
+#define CSISR			(cpu_is_mx27() ? 0x08 : 0x18)
+#define CSISTATFIFO		0x0c
+#define CSIRFIFO		0x10
+#define CSIRXCNT		0x14
+#define CSICR3			(cpu_is_mx27() ? 0x1C : 0x08)
+#define CSIDMASA_STATFIFO	0x20
+#define CSIDMATA_STATFIFO	0x24
+#define CSIDMASA_FB1		0x28
+#define CSIDMASA_FB2		0x2c
+#define CSIFBUF_PARA		0x30
+#define CSIIMAG_PARA		0x34
+
+/* EMMA PrP */
+#define PRP_CNTL			0x00
+#define PRP_INTR_CNTL			0x04
+#define PRP_INTRSTATUS			0x08
+#define PRP_SOURCE_Y_PTR		0x0c
+#define PRP_SOURCE_CB_PTR		0x10
+#define PRP_SOURCE_CR_PTR		0x14
+#define PRP_DEST_RGB1_PTR		0x18
+#define PRP_DEST_RGB2_PTR		0x1c
+#define PRP_DEST_Y_PTR			0x20
+#define PRP_DEST_CB_PTR			0x24
+#define PRP_DEST_CR_PTR			0x28
+#define PRP_SRC_FRAME_SIZE		0x2c
+#define PRP_DEST_CH1_LINE_STRIDE	0x30
+#define PRP_SRC_PIXEL_FORMAT_CNTL	0x34
+#define PRP_CH1_PIXEL_FORMAT_CNTL	0x38
+#define PRP_CH1_OUT_IMAGE_SIZE		0x3c
+#define PRP_CH2_OUT_IMAGE_SIZE		0x40
+#define PRP_SRC_LINE_STRIDE		0x44
+#define PRP_CSC_COEF_012		0x48
+#define PRP_CSC_COEF_345		0x4c
+#define PRP_CSC_COEF_678		0x50
+#define PRP_CH1_RZ_HORI_COEF1		0x54
+#define PRP_CH1_RZ_HORI_COEF2		0x58
+#define PRP_CH1_RZ_HORI_VALID		0x5c
+#define PRP_CH1_RZ_VERT_COEF1		0x60
+#define PRP_CH1_RZ_VERT_COEF2		0x64
+#define PRP_CH1_RZ_VERT_VALID		0x68
+#define PRP_CH2_RZ_HORI_COEF1		0x6c
+#define PRP_CH2_RZ_HORI_COEF2		0x70
+#define PRP_CH2_RZ_HORI_VALID		0x74
+#define PRP_CH2_RZ_VERT_COEF1		0x78
+#define PRP_CH2_RZ_VERT_COEF2		0x7c
+#define PRP_CH2_RZ_VERT_VALID		0x80
+
+#define PRP_CNTL_CH1EN		(1 << 0)
+#define PRP_CNTL_CH2EN		(1 << 1)
+#define PRP_CNTL_CSIEN		(1 << 2)
+#define PRP_CNTL_DATA_IN_YUV420	(0 << 3)
+#define PRP_CNTL_DATA_IN_YUV422	(1 << 3)
+#define PRP_CNTL_DATA_IN_RGB16	(2 << 3)
+#define PRP_CNTL_DATA_IN_RGB32	(3 << 3)
+#define PRP_CNTL_CH1_OUT_RGB8	(0 << 5)
+#define PRP_CNTL_CH1_OUT_RGB16	(1 << 5)
+#define PRP_CNTL_CH1_OUT_RGB32	(2 << 5)
+#define PRP_CNTL_CH1_OUT_YUV422	(3 << 5)
+#define PRP_CNTL_CH2_OUT_YUV420	(0 << 7)
+#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
+#define PRP_CNTL_CH2_OUT_YUV444	(2 << 7)
+#define PRP_CNTL_CH1_LEN	(1 << 9)
+#define PRP_CNTL_CH2_LEN	(1 << 10)
+#define PRP_CNTL_SKIP_FRAME	(1 << 11)
+#define PRP_CNTL_SWRST		(1 << 12)
+#define PRP_CNTL_CLKEN		(1 << 13)
+#define PRP_CNTL_WEN		(1 << 14)
+#define PRP_CNTL_CH1BYP		(1 << 15)
+#define PRP_CNTL_IN_TSKIP(x)	((x) << 16)
+#define PRP_CNTL_CH1_TSKIP(x)	((x) << 19)
+#define PRP_CNTL_CH2_TSKIP(x)	((x) << 22)
+#define PRP_CNTL_INPUT_FIFO_LEVEL(x)	((x) << 25)
+#define PRP_CNTL_RZ_FIFO_LEVEL(x)	((x) << 27)
+#define PRP_CNTL_CH2B1EN	(1 << 29)
+#define PRP_CNTL_CH2B2EN	(1 << 30)
+#define PRP_CNTL_CH2FEN		(1 << 31)
+
+/* IRQ Enable and status register */
+#define PRP_INTR_RDERR		(1 << 0)
+#define PRP_INTR_CH1WERR	(1 << 1)
+#define PRP_INTR_CH2WERR	(1 << 2)
+#define PRP_INTR_CH1FC		(1 << 3)
+#define PRP_INTR_CH2FC		(1 << 5)
+#define PRP_INTR_LBOVF		(1 << 7)
+#define PRP_INTR_CH2OVF		(1 << 8)
+
+#define mx27_camera_emma(pcdev)	(cpu_is_mx27() && pcdev->use_emma)
+
+#define MAX_VIDEO_MEM	16
+
+struct mx2_camera_dev {
+	struct device		*dev;
+	struct soc_camera_host	soc_host;
+	struct soc_camera_device *icd;
+	struct clk		*clk_csi, *clk_emma;
+
+	unsigned int		irq_csi, irq_emma;
+	void __iomem		*base_csi, *base_emma;
+	unsigned long		base_dma;
+
+	struct mx2_camera_platform_data *pdata;
+	struct resource		*res_csi, *res_emma;
+	unsigned long		platform_flags;
+
+	struct list_head	capture;
+	struct list_head	active_bufs;
+
+	spinlock_t		lock;
+
+	int			dma;
+	struct mx2_buffer	*active;
+	struct mx2_buffer	*fb1_active;
+	struct mx2_buffer	*fb2_active;
+
+	int			use_emma;
+
+	u32			csicr1;
+
+	void __iomem		*discard_buffer;
+	dma_addr_t		discard_buffer_dma;
+	size_t			discard_size;
+};
+
+/* buffer for one video frame */
+struct mx2_buffer {
+	/* common v4l buffer stuff -- must be first */
+	struct videobuf_buffer		vb;
+
+	enum v4l2_mbus_pixelcode	code;
+
+	int bufnum;
+};
+
+static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
+{
+	unsigned long flags;
+
+	clk_disable(pcdev->clk_csi);
+	writel(0, pcdev->base_csi + CSICR1);
+	if (mx27_camera_emma(pcdev)) {
+		writel(0, pcdev->base_emma + PRP_CNTL);
+	} else if (cpu_is_mx25()) {
+		spin_lock_irqsave(&pcdev->lock, flags);
+		pcdev->fb1_active = NULL;
+		pcdev->fb2_active = NULL;
+		writel(0, pcdev->base_csi + CSIDMASA_FB1);
+		writel(0, pcdev->base_csi + CSIDMASA_FB2);
+		spin_unlock_irqrestore(&pcdev->lock, flags);
+	}
+}
+
+/*
+ * The following two functions absolutely depend on the fact, that
+ * there can be only one camera on mx2 camera sensor interface
+ */
+static int mx2_camera_add_device(struct soc_camera_device *icd)
+{
+	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+	struct mx2_camera_dev *pcdev = ici->priv;
+	int ret;
+	u32 csicr1;
+
+	if (pcdev->icd)
+		return -EBUSY;
+
+	ret = clk_enable(pcdev->clk_csi);
+	if (ret < 0)
+		return ret;
+
+	csicr1 = CSICR1_MCLKEN;
+
+	if (mx27_camera_emma(pcdev)) {
+		csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
+			CSICR1_RXFF_LEVEL(0);
+	} else if (cpu_is_mx27())
+		csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2);
+
+	pcdev->csicr1 = csicr1;
+	writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
+
+	pcdev->icd = icd;
+
+	dev_info(icd->dev.parent, "Camera driver attached to camera %d\n",
+		 icd->devnum);
+
+	return 0;
+}
+
+static void mx2_camera_remove_device(struct soc_camera_device *icd)
+{
+	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+	struct mx2_camera_dev *pcdev = ici->priv;
+
+	BUG_ON(icd != pcdev->icd);
+
+	dev_info(icd->dev.parent, "Camera driver detached from camera %d\n",
+		 icd->devnum);
+
+	mx2_camera_deactivate(pcdev);
+
+	if (pcdev->discard_buffer) {
+		dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size,
+				pcdev->discard_buffer,
+				pcdev->discard_buffer_dma);
+		pcdev->discard_buffer = NULL;
+	}
+
+	pcdev->icd = NULL;
+}
+
+static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev)
+{
+	u32 tmp;
+
+	imx_dma_enable(pcdev->dma);
+
+	tmp = readl(pcdev->base_csi + CSICR1);
+	tmp |= CSICR1_RF_OR_INTEN;
+	writel(tmp, pcdev->base_csi + CSICR1);
+}
+
+static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
+{
+	struct mx2_camera_dev *pcdev = data;
+	u32 status = readl(pcdev->base_csi + CSISR);
+
+	if (status & CSISR_SOF_INT && pcdev->active) {
+		u32 tmp;
+
+		tmp = readl(pcdev->base_csi + CSICR1);
+		writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1);
+		mx27_camera_dma_enable(pcdev);
+	}
+
+	writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR);
+
+	return IRQ_HANDLED;
+}
+
+static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
+		int state)
+{
+	struct videobuf_buffer *vb;
+	struct mx2_buffer *buf;
+	struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
+		&pcdev->fb2_active;
+	u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pcdev->lock, flags);
+
+	vb = &(*fb_active)->vb;
+	dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+		vb, vb->baddr, vb->bsize);
+
+	vb->state = state;
+	do_gettimeofday(&vb->ts);
+	vb->field_count++;
+
+	wake_up(&vb->done);
+
+	if (list_empty(&pcdev->capture)) {
+		buf = NULL;
+		writel(0, pcdev->base_csi + fb_reg);
+	} else {
+		buf = list_entry(pcdev->capture.next, struct mx2_buffer,
+				vb.queue);
+		vb = &buf->vb;
+		list_del(&vb->queue);
+		vb->state = VIDEOBUF_ACTIVE;
+		writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg);
+	}
+
+	*fb_active = buf;
+
+	spin_unlock_irqrestore(&pcdev->lock, flags);
+}
+
+static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
+{
+	struct mx2_camera_dev *pcdev = data;
+	u32 status = readl(pcdev->base_csi + CSISR);
+
+	if (status & CSISR_DMA_TSF_FB1_INT)
+		mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE);
+	else if (status & CSISR_DMA_TSF_FB2_INT)
+		mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE);
+
+	/* FIXME: handle CSISR_RFF_OR_INT */
+
+	writel(status, pcdev->base_csi + CSISR);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ *  Videobuf operations
+ */
+static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
+			      unsigned int *size)
+{
+	struct soc_camera_device *icd = vq->priv_data;
+	int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
+			icd->current_fmt->host_fmt);
+
+	dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
+
+	if (bytes_per_line < 0)
+		return bytes_per_line;
+
+	*size = bytes_per_line * icd->user_height;
+
+	if (0 == *count)
+		*count = 32;
+	if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)
+		*count = (MAX_VIDEO_MEM * 1024 * 1024) / *size;
+
+	return 0;
+}
+
+static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf)
+{
+	struct soc_camera_device *icd = vq->priv_data;
+	struct videobuf_buffer *vb = &buf->vb;
+
+	dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+		vb, vb->baddr, vb->bsize);
+
+	/*
+	 * This waits until this buffer is out of danger, i.e., until it is no
+	 * longer in STATE_QUEUED or STATE_ACTIVE
+	 */
+	videobuf_waiton(vb, 0, 0);
+
+	videobuf_dma_contig_free(vq, vb);
+	dev_dbg(&icd->dev, "%s freed\n", __func__);
+
+	vb->state = VIDEOBUF_NEEDS_INIT;
+}
+
+static int mx2_videobuf_prepare(struct videobuf_queue *vq,
+		struct videobuf_buffer *vb, enum v4l2_field field)
+{
+	struct soc_camera_device *icd = vq->priv_data;
+	struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
+	int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
+			icd->current_fmt->host_fmt);
+	int ret = 0;
+
+	dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+		vb, vb->baddr, vb->bsize);
+
+	if (bytes_per_line < 0)
+		return bytes_per_line;
+
+#ifdef DEBUG
+	/*
+	 * This can be useful if you want to see if we actually fill
+	 * the buffer with something
+	 */
+	memset((void *)vb->baddr, 0xaa, vb->bsize);
+#endif
+
+	if (buf->code	!= icd->current_fmt->code ||
+	    vb->width	!= icd->user_width ||
+	    vb->height	!= icd->user_height ||
+	    vb->field	!= field) {
+		buf->code	= icd->current_fmt->code;
+		vb->width	= icd->user_width;
+		vb->height	= icd->user_height;
+		vb->field	= field;
+		vb->state	= VIDEOBUF_NEEDS_INIT;
+	}
+
+	vb->size = bytes_per_line * vb->height;
+	if (vb->baddr && vb->bsize < vb->size) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	if (vb->state == VIDEOBUF_NEEDS_INIT) {
+		ret = videobuf_iolock(vq, vb, NULL);
+		if (ret)
+			goto fail;
+
+		vb->state = VIDEOBUF_PREPARED;
+	}
+
+	return 0;
+
+fail:
+	free_buffer(vq, buf);
+out:
+	return ret;
+}
+
+static void mx2_videobuf_queue(struct videobuf_queue *vq,
+			       struct videobuf_buffer *vb)
+{
+	struct soc_camera_device *icd = vq->priv_data;
+	struct soc_camera_host *ici =
+		to_soc_camera_host(icd->dev.parent);
+	struct mx2_camera_dev *pcdev = ici->priv;
+	struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
+	unsigned long flags;
+	int ret;
+
+	dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+		vb, vb->baddr, vb->bsize);
+
+	spin_lock_irqsave(&pcdev->lock, flags);
+
+	vb->state = VIDEOBUF_QUEUED;
+	list_add_tail(&vb->queue, &pcdev->capture);
+
+	if (mx27_camera_emma(pcdev)) {
+		goto out;
+	} else if (cpu_is_mx27()) {
+		if (pcdev->active == NULL) {
+			ret = imx_dma_setup_single(pcdev->dma,
+					videobuf_to_dma_contig(vb), vb->size,
+					(u32)pcdev->base_dma + 0x10,
+					DMA_MODE_READ);
+			if (ret) {
+				vb->state = VIDEOBUF_ERROR;
+				wake_up(&vb->done);
+				goto out;
+			}
+
+			vb->state = VIDEOBUF_ACTIVE;
+			pcdev->active = buf;
+		}
+	} else { /* cpu_is_mx25() */
+		u32 csicr3, dma_inten = 0;
+
+		if (pcdev->fb1_active == NULL) {
+			writel(videobuf_to_dma_contig(vb),
+					pcdev->base_csi + CSIDMASA_FB1);
+			pcdev->fb1_active = buf;
+			dma_inten = CSICR1_FB1_DMA_INTEN;
+		} else if (pcdev->fb2_active == NULL) {
+			writel(videobuf_to_dma_contig(vb),
+					pcdev->base_csi + CSIDMASA_FB2);
+			pcdev->fb2_active = buf;
+			dma_inten = CSICR1_FB2_DMA_INTEN;
+		}
+
+		if (dma_inten) {
+			list_del(&vb->queue);
+			vb->state = VIDEOBUF_ACTIVE;
+
+			csicr3 = readl(pcdev->base_csi + CSICR3);
+
+			/* Reflash DMA */
+			writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
+					pcdev->base_csi + CSICR3);
+
+			/* clear & enable interrupts */
+			writel(dma_inten, pcdev->base_csi + CSISR);
+			pcdev->csicr1 |= dma_inten;
+			writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
+
+			/* enable DMA */
+			csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
+			writel(csicr3, pcdev->base_csi + CSICR3);
+		}
+	}
+
+out:
+	spin_unlock_irqrestore(&pcdev->lock, flags);
+}
+
+static void mx2_videobuf_release(struct videobuf_queue *vq,
+				 struct videobuf_buffer *vb)
+{
+	struct soc_camera_device *icd = vq->priv_data;
+	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+	struct mx2_camera_dev *pcdev = ici->priv;
+	struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
+	unsigned long flags;
+
+#ifdef DEBUG
+	dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+		vb, vb->baddr, vb->bsize);
+
+	switch (vb->state) {
+	case VIDEOBUF_ACTIVE:
+		dev_info(&icd->dev, "%s (active)\n", __func__);
+		break;
+	case VIDEOBUF_QUEUED:
+		dev_info(&icd->dev, "%s (queued)\n", __func__);
+		break;
+	case VIDEOBUF_PREPARED:
+		dev_info(&icd->dev, "%s (prepared)\n", __func__);
+		break;
+	default:
+		dev_info(&icd->dev, "%s (unknown) %d\n", __func__,
+				vb->state);
+		break;
+	}
+#endif
+
+	/*
+	 * Terminate only queued but inactive buffers. Active buffers are
+	 * released when they become inactive after videobuf_waiton().
+	 *
+	 * FIXME: implement forced termination of active buffers, so that the
+	 * user won't get stuck in an uninterruptible state. This requires a
+	 * specific handling for each of the three DMA types that this driver
+	 * supports.
+	 */
+	spin_lock_irqsave(&pcdev->lock, flags);
+	if (vb->state == VIDEOBUF_QUEUED) {
+		list_del(&vb->queue);
+		vb->state = VIDEOBUF_ERROR;
+	}
+	spin_unlock_irqrestore(&pcdev->lock, flags);
+
+	free_buffer(vq, buf);
+}
+
+static struct videobuf_queue_ops mx2_videobuf_ops = {
+	.buf_setup      = mx2_videobuf_setup,
+	.buf_prepare    = mx2_videobuf_prepare,
+	.buf_queue      = mx2_videobuf_queue,
+	.buf_release    = mx2_videobuf_release,
+};
+
+static void mx2_camera_init_videobuf(struct videobuf_queue *q,
+			      struct soc_camera_device *icd)
+{
+	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+	struct mx2_camera_dev *pcdev = ici->priv;
+
+	videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev,
+			&pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE,
+			V4L2_FIELD_NONE, sizeof(struct mx2_buffer), icd);
+}
+
+#define MX2_BUS_FLAGS	(SOCAM_DATAWIDTH_8 | \
+			SOCAM_MASTER | \
+			SOCAM_VSYNC_ACTIVE_HIGH | \
+			SOCAM_VSYNC_ACTIVE_LOW | \
+			SOCAM_HSYNC_ACTIVE_HIGH | \
+			SOCAM_HSYNC_ACTIVE_LOW | \
+			SOCAM_PCLK_SAMPLE_RISING | \
+			SOCAM_PCLK_SAMPLE_FALLING | \
+			SOCAM_DATA_ACTIVE_HIGH | \
+			SOCAM_DATA_ACTIVE_LOW)
+
+static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
+{
+	u32 cntl;
+	int count = 0;
+
+	cntl = readl(pcdev->base_emma + PRP_CNTL);
+	writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
+	while (count++ < 100) {
+		if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
+			return 0;
+		barrier();
+		udelay(1);
+	}
+
+	return -ETIMEDOUT;
+}
+
+static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
+		int bytesperline)
+{
+	struct soc_camera_host *ici =
+		to_soc_camera_host(icd->dev.parent);
+	struct mx2_camera_dev *pcdev = ici->priv;
+
+	writel(pcdev->discard_buffer_dma,
+			pcdev->base_emma + PRP_DEST_RGB1_PTR);
+	writel(pcdev->discard_buffer_dma,
+			pcdev->base_emma + PRP_DEST_RGB2_PTR);
+
+	/*
+	 * We only use the EMMA engine to get rid of the broken
+	 * DMA Engine. No color space consversion at the moment.
+	 * We adjust incoming and outgoing pixelformat to rgb16
+	 * and adjust the bytesperline accordingly.
+	 */
+	writel(PRP_CNTL_CH1EN |
+			PRP_CNTL_CSIEN |
+			PRP_CNTL_DATA_IN_RGB16 |
+			PRP_CNTL_CH1_OUT_RGB16 |
+			PRP_CNTL_CH1_LEN |
+			PRP_CNTL_CH1BYP |
+			PRP_CNTL_CH1_TSKIP(0) |
+			PRP_CNTL_IN_TSKIP(0),
+			pcdev->base_emma + PRP_CNTL);
+
+	writel(((bytesperline >> 1) << 16) | icd->user_height,
+			pcdev->base_emma + PRP_SRC_FRAME_SIZE);
+	writel(((bytesperline >> 1) << 16) | icd->user_height,
+			pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
+	writel(bytesperline,
+			pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
+	writel(0x2ca00565, /* RGB565 */
+			pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
+	writel(0x2ca00565, /* RGB565 */
+			pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
+
+	/* Enable interrupts */
+	writel(PRP_INTR_RDERR |
+			PRP_INTR_CH1WERR |
+			PRP_INTR_CH2WERR |
+			PRP_INTR_CH1FC |
+			PRP_INTR_CH2FC |
+			PRP_INTR_LBOVF |
+			PRP_INTR_CH2OVF,
+			pcdev->base_emma + PRP_INTR_CNTL);
+}
+
+static int mx2_camera_set_bus_param(struct soc_camera_device *icd,
+		__u32 pixfmt)
+{
+	struct soc_camera_host *ici =
+		to_soc_camera_host(icd->dev.parent);
+	struct mx2_camera_dev *pcdev = ici->priv;
+	unsigned long camera_flags, common_flags;
+	int ret = 0;
+	int bytesperline;
+	u32 csicr1 = pcdev->csicr1;
+
+	camera_flags = icd->ops->query_bus_param(icd);
+
+	common_flags = soc_camera_bus_param_compatible(camera_flags,
+				MX2_BUS_FLAGS);
+	if (!common_flags)
+		return -EINVAL;
+
+	if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
+	    (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
+		if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
+			common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
+		else
+			common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
+	}
+
+	if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
+	    (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
+		if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
+			common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
+		else
+			common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
+	}
+
+	ret = icd->ops->set_bus_param(icd, common_flags);
+	if (ret < 0)
+		return ret;
+
+	if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
+		csicr1 |= CSICR1_INV_PCLK;
+	if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH)
+		csicr1 |= CSICR1_SOF_POL;
+	if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH)
+		csicr1 |= CSICR1_HSYNC_POL;
+	if (pcdev->platform_flags & MX2_CAMERA_SWAP16)
+		csicr1 |= CSICR1_SWAP16_EN;
+	if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
+		csicr1 |= CSICR1_EXT_VSYNC;
+	if (pcdev->platform_flags & MX2_CAMERA_CCIR)
+		csicr1 |= CSICR1_CCIR_EN;
+	if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
+		csicr1 |= CSICR1_CCIR_MODE;
+	if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
+		csicr1 |= CSICR1_GCLK_MODE;
+	if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
+		csicr1 |= CSICR1_INV_DATA;
+	if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB)
+		csicr1 |= CSICR1_PACK_DIR;
+
+	pcdev->csicr1 = csicr1;
+
+	bytesperline = soc_mbus_bytes_per_line(icd->user_width,
+			icd->current_fmt->host_fmt);
+	if (bytesperline < 0)
+		return bytesperline;
+
+	if (mx27_camera_emma(pcdev)) {
+		ret = mx27_camera_emma_prp_reset(pcdev);
+		if (ret)
+			return ret;
+
+		if (pcdev->discard_buffer)
+			dma_free_coherent(ici->v4l2_dev.dev,
+				pcdev->discard_size, pcdev->discard_buffer,
+				pcdev->discard_buffer_dma);
+
+		/*
+		 * I didn't manage to properly enable/disable the prp
+		 * on a per frame basis during running transfers,
+		 * thus we allocate a buffer here and use it to
+		 * discard frames when no buffer is available.
+		 * Feel free to work on this ;)
+		 */
+		pcdev->discard_size = icd->user_height * bytesperline;
+		pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
+				pcdev->discard_size, &pcdev->discard_buffer_dma,
+				GFP_KERNEL);
+		if (!pcdev->discard_buffer)
+			return -ENOMEM;
+
+		mx27_camera_emma_buf_init(icd, bytesperline);
+	} else if (cpu_is_mx25()) {
+		writel((bytesperline * icd->user_height) >> 2,
+				pcdev->base_csi + CSIRXCNT);
+		writel((bytesperline << 16) | icd->user_height,
+				pcdev->base_csi + CSIIMAG_PARA);
+	}
+
+	writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
+
+	return 0;
+}
+
+static int mx2_camera_set_crop(struct soc_camera_device *icd,
+				struct v4l2_crop *a)
+{
+	struct v4l2_rect *rect = &a->c;
+	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+	struct v4l2_mbus_framefmt mf;
+	int ret;
+
+	soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
+	soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
+
+	ret = v4l2_subdev_call(sd, video, s_crop, a);
+	if (ret < 0)
+		return ret;
+
+	/* The capture device might have changed its output  */
+	ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
+	if (ret < 0)
+		return ret;
+
+	dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n",
+		mf.width, mf.height);
+
+	icd->user_width		= mf.width;
+	icd->user_height	= mf.height;
+
+	return ret;
+}
+
+static int mx2_camera_set_fmt(struct soc_camera_device *icd,
+			       struct v4l2_format *f)
+{
+	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+	struct mx2_camera_dev *pcdev = ici->priv;
+	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+	const struct soc_camera_format_xlate *xlate;
+	struct v4l2_pix_format *pix = &f->fmt.pix;
+	struct v4l2_mbus_framefmt mf;
+	int ret;
+
+	xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
+	if (!xlate) {
+		dev_warn(icd->dev.parent, "Format %x not found\n",
+				pix->pixelformat);
+		return -EINVAL;
+	}
+
+	/* eMMA can only do RGB565 */
+	if (mx27_camera_emma(pcdev) && pix->pixelformat != V4L2_PIX_FMT_RGB565)
+		return -EINVAL;
+
+	mf.width	= pix->width;
+	mf.height	= pix->height;
+	mf.field	= pix->field;
+	mf.colorspace	= pix->colorspace;
+	mf.code		= xlate->code;
+
+	ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
+	if (ret < 0 && ret != -ENOIOCTLCMD)
+		return ret;
+
+	if (mf.code != xlate->code)
+		return -EINVAL;
+
+	pix->width		= mf.width;
+	pix->height		= mf.height;
+	pix->field		= mf.field;
+	pix->colorspace		= mf.colorspace;
+	icd->current_fmt	= xlate;
+
+	return 0;
+}
+
+static int mx2_camera_try_fmt(struct soc_camera_device *icd,
+				  struct v4l2_format *f)
+{
+	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+	struct mx2_camera_dev *pcdev = ici->priv;
+	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+	const struct soc_camera_format_xlate *xlate;
+	struct v4l2_pix_format *pix = &f->fmt.pix;
+	struct v4l2_mbus_framefmt mf;
+	__u32 pixfmt = pix->pixelformat;
+	unsigned int width_limit;
+	int ret;
+
+	xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
+	if (pixfmt && !xlate) {
+		dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt);
+		return -EINVAL;
+	}
+
+	/* FIXME: implement MX27 limits */
+
+	/* eMMA can only do RGB565 */
+	if (mx27_camera_emma(pcdev) && pixfmt != V4L2_PIX_FMT_RGB565)
+		return -EINVAL;
+
+	/* limit to MX25 hardware capabilities */
+	if (cpu_is_mx25()) {
+		if (xlate->host_fmt->bits_per_sample <= 8)
+			width_limit = 0xffff * 4;
+		else
+			width_limit = 0xffff * 2;
+		/* CSIIMAG_PARA limit */
+		if (pix->width > width_limit)
+			pix->width = width_limit;
+		if (pix->height > 0xffff)
+			pix->height = 0xffff;
+
+		pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
+				xlate->host_fmt);
+		if (pix->bytesperline < 0)
+			return pix->bytesperline;
+		pix->sizeimage = pix->height * pix->bytesperline;
+		if (pix->sizeimage > (4 * 0x3ffff)) { /* CSIRXCNT limit */
+			dev_warn(icd->dev.parent,
+					"Image size (%u) above limit\n",
+					pix->sizeimage);
+			return -EINVAL;
+		}
+	}
+
+	/* limit to sensor capabilities */
+	mf.width	= pix->width;
+	mf.height	= pix->height;
+	mf.field	= pix->field;
+	mf.colorspace	= pix->colorspace;
+	mf.code		= xlate->code;
+
+	ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
+	if (ret < 0)
+		return ret;
+
+	if (mf.field == V4L2_FIELD_ANY)
+		mf.field = V4L2_FIELD_NONE;
+	if (mf.field != V4L2_FIELD_NONE) {
+		dev_err(icd->dev.parent, "Field type %d unsupported.\n",
+				mf.field);
+		return -EINVAL;
+	}
+
+	pix->width	= mf.width;
+	pix->height	= mf.height;
+	pix->field	= mf.field;
+	pix->colorspace	= mf.colorspace;
+
+	return 0;
+}
+
+static int mx2_camera_querycap(struct soc_camera_host *ici,
+			       struct v4l2_capability *cap)
+{
+	/* cap->name is set by the friendly caller:-> */
+	strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
+	cap->version = MX2_CAM_VERSION_CODE;
+	cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
+
+	return 0;
+}
+
+static int mx2_camera_reqbufs(struct soc_camera_file *icf,
+			      struct v4l2_requestbuffers *p)
+{
+	int i;
+
+	for (i = 0; i < p->count; i++) {
+		struct mx2_buffer *buf = container_of(icf->vb_vidq.bufs[i],
+						      struct mx2_buffer, vb);
+		INIT_LIST_HEAD(&buf->vb.queue);
+	}
+
+	return 0;
+}
+
+static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state)
+{
+	struct videobuf_buffer *vb;
+	struct mx2_buffer *buf;
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&pcdev->lock, flags);
+
+	if (!pcdev->active) {
+		dev_err(pcdev->dev, "%s called with no active buffer!\n",
+				__func__);
+		goto out;
+	}
+
+	vb = &pcdev->active->vb;
+	buf = container_of(vb, struct mx2_buffer, vb);
+	WARN_ON(list_empty(&vb->queue));
+	dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
+		vb, vb->baddr, vb->bsize);
+
+	/* _init is used to debug races, see comment in pxa_camera_reqbufs() */
+	list_del_init(&vb->queue);
+	vb->state = state;
+	do_gettimeofday(&vb->ts);
+	vb->field_count++;
+
+	wake_up(&vb->done);
+
+	if (list_empty(&pcdev->capture)) {
+		pcdev->active = NULL;
+		goto out;
+	}
+
+	pcdev->active = list_entry(pcdev->capture.next,
+			struct mx2_buffer, vb.queue);
+
+	vb = &pcdev->active->vb;
+	vb->state = VIDEOBUF_ACTIVE;
+
+	ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb),
+			vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ);
+
+	if (ret) {
+		vb->state = VIDEOBUF_ERROR;
+		pcdev->active = NULL;
+		wake_up(&vb->done);
+	}
+
+out:
+	spin_unlock_irqrestore(&pcdev->lock, flags);
+}
+
+static void mx27_camera_dma_err_callback(int channel, void *data, int err)
+{
+	struct mx2_camera_dev *pcdev = data;
+
+	mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR);
+}
+
+static void mx27_camera_dma_callback(int channel, void *data)
+{
+	struct mx2_camera_dev *pcdev = data;
+
+	mx27_camera_frame_done(pcdev, VIDEOBUF_DONE);
+}
+
+#define DMA_REQ_CSI_RX          31 /* FIXME: Add this to a resource */
+
+static int __devinit mx27_camera_dma_init(struct platform_device *pdev,
+		struct mx2_camera_dev *pcdev)
+{
+	int err;
+
+	pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH);
+	if (pcdev->dma < 0) {
+		dev_err(&pdev->dev, "%s failed to request DMA channel\n",
+				__func__);
+		return pcdev->dma;
+	}
+
+	err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback,
+					mx27_camera_dma_err_callback, pcdev);
+	if (err) {
+		dev_err(&pdev->dev, "%s failed to set DMA callback\n",
+				__func__);
+		goto err_out;
+	}
+
+	err = imx_dma_config_channel(pcdev->dma,
+			IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
+			IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
+			DMA_REQ_CSI_RX, 1);
+	if (err) {
+		dev_err(&pdev->dev, "%s failed to config DMA channel\n",
+				__func__);
+		goto err_out;
+	}
+
+	imx_dma_config_burstlen(pcdev->dma, 64);
+
+	return 0;
+
+err_out:
+	imx_dma_free(pcdev->dma);
+
+	return err;
+}
+
+static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
+{
+	struct soc_camera_file *icf = file->private_data;
+
+	return videobuf_poll_stream(file, &icf->vb_vidq, pt);
+}
+
+static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
+	.owner		= THIS_MODULE,
+	.add		= mx2_camera_add_device,
+	.remove		= mx2_camera_remove_device,
+	.set_fmt	= mx2_camera_set_fmt,
+	.set_crop	= mx2_camera_set_crop,
+	.try_fmt	= mx2_camera_try_fmt,
+	.init_videobuf	= mx2_camera_init_videobuf,
+	.reqbufs	= mx2_camera_reqbufs,
+	.poll		= mx2_camera_poll,
+	.querycap	= mx2_camera_querycap,
+	.set_bus_param	= mx2_camera_set_bus_param,
+};
+
+static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
+		int bufnum, int state)
+{
+	struct mx2_buffer *buf;
+	struct videobuf_buffer *vb;
+	unsigned long phys;
+
+	if (!list_empty(&pcdev->active_bufs)) {
+		buf = list_entry(pcdev->active_bufs.next,
+			struct mx2_buffer, vb.queue);
+
+		BUG_ON(buf->bufnum != bufnum);
+
+		vb = &buf->vb;
+#ifdef DEBUG
+		phys = videobuf_to_dma_contig(vb);
+		if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum)
+				!= phys) {
+			dev_err(pcdev->dev, "%p != %p\n", phys,
+					readl(pcdev->base_emma +
+						PRP_DEST_RGB1_PTR +
+						4 * bufnum));
+		}
+#endif
+		dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb,
+				vb->baddr, vb->bsize);
+
+		list_del(&vb->queue);
+		vb->state = state;
+		do_gettimeofday(&vb->ts);
+		vb->field_count++;
+
+		wake_up(&vb->done);
+	}
+
+	if (list_empty(&pcdev->capture)) {
+		writel(pcdev->discard_buffer_dma, pcdev->base_emma +
+				PRP_DEST_RGB1_PTR + 4 * bufnum);
+		return;
+	}
+
+	buf = list_entry(pcdev->capture.next,
+			struct mx2_buffer, vb.queue);
+
+	buf->bufnum = bufnum;
+
+	list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
+
+	vb = &buf->vb;
+	vb->state = VIDEOBUF_ACTIVE;
+
+	phys = videobuf_to_dma_contig(vb);
+	writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum);
+}
+
+static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
+{
+	struct mx2_camera_dev *pcdev = data;
+	unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
+	struct mx2_buffer *buf;
+
+	if (status & (1 << 7)) { /* overflow */
+		u32 cntl;
+		/*
+		 * We only disable channel 1 here since this is the only
+		 * enabled channel
+		 *
+		 * FIXME: the correct DMA overflow handling should be resetting
+		 * the buffer, returning an error frame, and continuing with
+		 * the next one.
+		 */
+		cntl = readl(pcdev->base_emma + PRP_CNTL);
+		writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL);
+		writel(cntl, pcdev->base_emma + PRP_CNTL);
+	}
+	if ((status & (3 << 5)) == (3 << 5)
+			&& !list_empty(&pcdev->active_bufs)) {
+		/*
+		 * Both buffers have triggered, process the one we're expecting
+		 * to first
+		 */
+		buf = list_entry(pcdev->active_bufs.next,
+			struct mx2_buffer, vb.queue);
+		mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE);
+		status &= ~(1 << (6 - buf->bufnum)); /* mark processed */
+	}
+	if (status & (1 << 6))
+		mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE);
+	if (status & (1 << 5))
+		mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE);
+
+	writel(status, pcdev->base_emma + PRP_INTRSTATUS);
+
+	return IRQ_HANDLED;
+}
+
+static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev)
+{
+	struct resource *res_emma = pcdev->res_emma;
+	int err = 0;
+
+	if (!request_mem_region(res_emma->start, resource_size(res_emma),
+				MX2_CAM_DRV_NAME)) {
+		err = -EBUSY;
+		goto out;
+	}
+
+	pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma));
+	if (!pcdev->base_emma) {
+		err = -ENOMEM;
+		goto exit_release;
+	}
+
+	err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0,
+			MX2_CAM_DRV_NAME, pcdev);
+	if (err) {
+		dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
+		goto exit_iounmap;
+	}
+
+	pcdev->clk_emma = clk_get(NULL, "emma");
+	if (IS_ERR(pcdev->clk_emma)) {
+		err = PTR_ERR(pcdev->clk_emma);
+		goto exit_free_irq;
+	}
+
+	clk_enable(pcdev->clk_emma);
+
+	err = mx27_camera_emma_prp_reset(pcdev);
+	if (err)
+		goto exit_clk_emma_put;
+
+	return err;
+
+exit_clk_emma_put:
+	clk_disable(pcdev->clk_emma);
+	clk_put(pcdev->clk_emma);
+exit_free_irq:
+	free_irq(pcdev->irq_emma, pcdev);
+exit_iounmap:
+	iounmap(pcdev->base_emma);
+exit_release:
+	release_mem_region(res_emma->start, resource_size(res_emma));
+out:
+	return err;
+}
+
+static int __devinit mx2_camera_probe(struct platform_device *pdev)
+{
+	struct mx2_camera_dev *pcdev;
+	struct resource *res_csi, *res_emma;
+	void __iomem *base_csi;
+	int irq_csi, irq_emma;
+	irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq
+		: mx27_camera_irq;
+	int err = 0;
+
+	dev_dbg(&pdev->dev, "initialising\n");
+
+	res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	irq_csi = platform_get_irq(pdev, 0);
+	if (res_csi == NULL || irq_csi < 0) {
+		dev_err(&pdev->dev, "Missing platform resources data\n");
+		err = -ENODEV;
+		goto exit;
+	}
+
+	pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
+	if (!pcdev) {
+		dev_err(&pdev->dev, "Could not allocate pcdev\n");
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	pcdev->clk_csi = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(pcdev->clk_csi)) {
+		err = PTR_ERR(pcdev->clk_csi);
+		goto exit_kfree;
+	}
+
+	dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n",
+			clk_get_rate(pcdev->clk_csi));
+
+	/* Initialize DMA */
+	if (cpu_is_mx27()) {
+		err = mx27_camera_dma_init(pdev, pcdev);
+		if (err)
+			goto exit_clk_put;
+	}
+
+	pcdev->res_csi = res_csi;
+	pcdev->pdata = pdev->dev.platform_data;
+	if (pcdev->pdata) {
+		long rate;
+
+		pcdev->platform_flags = pcdev->pdata->flags;
+
+		rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
+		if (rate <= 0) {
+			err = -ENODEV;
+			goto exit_dma_free;
+		}
+		err = clk_set_rate(pcdev->clk_csi, rate);
+		if (err < 0)
+			goto exit_dma_free;
+	}
+
+	INIT_LIST_HEAD(&pcdev->capture);
+	INIT_LIST_HEAD(&pcdev->active_bufs);
+	spin_lock_init(&pcdev->lock);
+
+	/*
+	 * Request the regions.
+	 */
+	if (!request_mem_region(res_csi->start, resource_size(res_csi),
+				MX2_CAM_DRV_NAME)) {
+		err = -EBUSY;
+		goto exit_dma_free;
+	}
+
+	base_csi = ioremap(res_csi->start, resource_size(res_csi));
+	if (!base_csi) {
+		err = -ENOMEM;
+		goto exit_release;
+	}
+	pcdev->irq_csi = irq_csi;
+	pcdev->base_csi = base_csi;
+	pcdev->base_dma = res_csi->start;
+	pcdev->dev = &pdev->dev;
+
+	err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0,
+			MX2_CAM_DRV_NAME, pcdev);
+	if (err) {
+		dev_err(pcdev->dev, "Camera interrupt register failed \n");
+		goto exit_iounmap;
+	}
+
+	if (cpu_is_mx27()) {
+		/* EMMA support */
+		res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+		irq_emma = platform_get_irq(pdev, 1);
+
+		if (res_emma && irq_emma >= 0) {
+			dev_info(&pdev->dev, "Using EMMA\n");
+			pcdev->use_emma = 1;
+			pcdev->res_emma = res_emma;
+			pcdev->irq_emma = irq_emma;
+			if (mx27_camera_emma_init(pcdev))
+				goto exit_free_irq;
+		}
+	}
+
+	pcdev->soc_host.drv_name	= MX2_CAM_DRV_NAME,
+	pcdev->soc_host.ops		= &mx2_soc_camera_host_ops,
+	pcdev->soc_host.priv		= pcdev;
+	pcdev->soc_host.v4l2_dev.dev	= &pdev->dev;
+	pcdev->soc_host.nr		= pdev->id;
+	err = soc_camera_host_register(&pcdev->soc_host);
+	if (err)
+		goto exit_free_emma;
+
+	return 0;
+
+exit_free_emma:
+	if (mx27_camera_emma(pcdev)) {
+		free_irq(pcdev->irq_emma, pcdev);
+		clk_disable(pcdev->clk_emma);
+		clk_put(pcdev->clk_emma);
+		iounmap(pcdev->base_emma);
+		release_mem_region(res_emma->start, resource_size(res_emma));
+	}
+exit_free_irq:
+	free_irq(pcdev->irq_csi, pcdev);
+exit_iounmap:
+	iounmap(base_csi);
+exit_release:
+	release_mem_region(res_csi->start, resource_size(res_csi));
+exit_dma_free:
+	if (cpu_is_mx27())
+		imx_dma_free(pcdev->dma);
+exit_clk_put:
+	clk_put(pcdev->clk_csi);
+exit_kfree:
+	kfree(pcdev);
+exit:
+	return err;
+}
+
+static int __devexit mx2_camera_remove(struct platform_device *pdev)
+{
+	struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
+	struct mx2_camera_dev *pcdev = container_of(soc_host,
+			struct mx2_camera_dev, soc_host);
+	struct resource *res;
+
+	clk_put(pcdev->clk_csi);
+	if (cpu_is_mx27())
+		imx_dma_free(pcdev->dma);
+	free_irq(pcdev->irq_csi, pcdev);
+	if (mx27_camera_emma(pcdev))
+		free_irq(pcdev->irq_emma, pcdev);
+
+	soc_camera_host_unregister(&pcdev->soc_host);
+
+	iounmap(pcdev->base_csi);
+
+	if (mx27_camera_emma(pcdev)) {
+		clk_disable(pcdev->clk_emma);
+		clk_put(pcdev->clk_emma);
+		iounmap(pcdev->base_emma);
+		res = pcdev->res_emma;
+		release_mem_region(res->start, resource_size(res));
+	}
+
+	res = pcdev->res_csi;
+	release_mem_region(res->start, resource_size(res));
+
+	kfree(pcdev);
+
+	dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
+
+	return 0;
+}
+
+static struct platform_driver mx2_camera_driver = {
+	.driver 	= {
+		.name	= MX2_CAM_DRV_NAME,
+	},
+	.remove		= __devexit_p(mx2_camera_remove),
+};
+
+
+static int __init mx2_camera_init(void)
+{
+	return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
+}
+
+static void __exit mx2_camera_exit(void)
+{
+	return platform_driver_unregister(&mx2_camera_driver);
+}
+
+module_init(mx2_camera_init);
+module_exit(mx2_camera_exit);
+
+MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
+MODULE_AUTHOR("Sascha Hauer <sha at pengutronix.de>");
+MODULE_LICENSE("GPL");
-- 
1.7.1



From baruch at tkos.co.il  Mon Jun 21 01:15:59 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Mon, 21 Jun 2010 08:15:59 +0300
Subject: [PATCHv4 2/3] mx27: add support for the CSI device
In-Reply-To: <cover.1277096909.git.baruch@tkos.co.il>
References: <cover.1277096909.git.baruch@tkos.co.il>
Message-ID: <72e1ece6cc4f2e733dbb5f16dc5f06e7f1498f6c.1277096909.git.baruch@tkos.co.il>

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 arch/arm/mach-mx2/clock_imx27.c |    2 +-
 arch/arm/mach-mx2/devices.c     |   31 +++++++++++++++++++++++++++++++
 arch/arm/mach-mx2/devices.h     |    1 +
 3 files changed, 33 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index 0f0823c..5a1aa15 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -644,7 +644,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
 	_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
 	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-	_REGISTER_CLOCK(NULL, "csi", csi_clk)
+	_REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
 	_REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index a0aeb8a..08201f5 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -40,6 +40,37 @@
 
 #include "devices.h"
 
+#ifdef CONFIG_MACH_MX27
+static struct resource mx27_camera_resources[] = {
+	{
+	       .start = MX27_CSI_BASE_ADDR,
+	       .end = MX27_CSI_BASE_ADDR + 0x1f,
+	       .flags = IORESOURCE_MEM,
+	}, {
+	       .start = MX27_EMMA_PRP_BASE_ADDR,
+	       .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
+	       .flags = IORESOURCE_MEM,
+	}, {
+	       .start = MX27_INT_CSI,
+	       .end = MX27_INT_CSI,
+	       .flags = IORESOURCE_IRQ,
+	},{
+	       .start = MX27_INT_EMMAPRP,
+	       .end = MX27_INT_EMMAPRP,
+	       .flags = IORESOURCE_IRQ,
+	},
+};
+struct platform_device mx27_camera_device = {
+	.name = "mx2-camera",
+	.id = 0,
+	.num_resources = ARRAY_SIZE(mx27_camera_resources),
+	.resource = mx27_camera_resources,
+	.dev = {
+		.coherent_dma_mask = 0xffffffff,
+	},
+};
+#endif
+
 /*
  * SPI master controller
  *
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index 84ed513..8bdf018 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -29,6 +29,7 @@ extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_sdhc_device0;
 extern struct platform_device mxc_sdhc_device1;
 extern struct platform_device mxc_otg_udc_device;
+extern struct platform_device mx27_camera_device;
 extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
-- 
1.7.1



From baruch at tkos.co.il  Mon Jun 21 01:16:00 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Mon, 21 Jun 2010 08:16:00 +0300
Subject: [PATCHv4 3/3] mx25: add support for the CSI device
In-Reply-To: <cover.1277096909.git.baruch@tkos.co.il>
References: <cover.1277096909.git.baruch@tkos.co.il>
Message-ID: <36c9db771cd895d7bbfe422fbd910dc9bf211219.1277096909.git.baruch@tkos.co.il>

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 arch/arm/mach-mx25/clock.c            |   14 ++++++++++++--
 arch/arm/mach-mx25/devices.c          |   22 ++++++++++++++++++++++
 arch/arm/mach-mx25/devices.h          |    1 +
 arch/arm/plat-mxc/include/mach/mx25.h |    2 ++
 4 files changed, 37 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 1550149..7a98d18 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -129,6 +129,11 @@ static unsigned long get_rate_lcdc(struct clk *clk)
 	return get_rate_per(7);
 }
 
+static unsigned long get_rate_csi(struct clk *clk)
+{
+	return get_rate_per(0);
+}
+
 static unsigned long get_rate_otg(struct clk *clk)
 {
 	return 48000000; /* FIXME */
@@ -174,6 +179,8 @@ DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL,	 NULL, NULL);
 DEFINE_CLOCK(lcdc_ahb_clk, 0, CCM_CGCR0, 24, NULL,	 NULL, NULL);
 DEFINE_CLOCK(lcdc_per_clk, 0, CCM_CGCR0,  7, NULL,	 NULL, &lcdc_ahb_clk);
+DEFINE_CLOCK(csi_ahb_clk, 0, CCM_CGCR0, 18, get_rate_csi, NULL, NULL);
+DEFINE_CLOCK(csi_per_clk, 0, CCM_CGCR0, 0, get_rate_csi, NULL, &csi_ahb_clk);
 DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
 DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
 DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
@@ -191,6 +198,7 @@ DEFINE_CLOCK(i2c_clk,	 0, CCM_CGCR0,  6, get_rate_i2c, NULL, NULL);
 DEFINE_CLOCK(fec_clk,	 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
 DEFINE_CLOCK(dryice_clk, 0, CCM_CGCR1,  8, get_rate_ipg, NULL, NULL);
 DEFINE_CLOCK(lcdc_clk,	 0, CCM_CGCR1, 29, get_rate_lcdc, NULL, &lcdc_per_clk);
+DEFINE_CLOCK(csi_clk,    0, CCM_CGCR1,  4, get_rate_csi, NULL,  &csi_per_clk);
 
 #define _REGISTER_CLOCK(d, n, c)	\
 	{				\
@@ -225,6 +233,7 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("fec.0", NULL, fec_clk)
 	_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
 	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+	_REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
 };
 
 int __init mx25_clocks_init(void)
@@ -239,8 +248,9 @@ int __init mx25_clocks_init(void)
 	__raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
 	__raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
 
-	/* Clock source for lcdc is upll */
-	__raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7), CRM_BASE + 0x64);
+	/* Clock source for lcdc and csi is upll */
+	__raw_writel(__raw_readl(CRM_BASE+0x64) | (1 << 7) | (1 << 0),
+			CRM_BASE + 0x64);
 
 	mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
 
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 3a405fa..cbecbe1 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -515,3 +515,25 @@ struct platform_device mxc_wdt = {
 	.num_resources = ARRAY_SIZE(mxc_wdt_resources),
 	.resource = mxc_wdt_resources,
 };
+
+static struct resource mx25_csi_resources[] = {
+	{
+		.start	= MX25_CSI_BASE_ADDR,
+		.end	= MX25_CSI_BASE_ADDR + 0xfff,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= MX25_INT_CSI,
+		.flags	= IORESOURCE_IRQ
+	},
+};
+
+struct platform_device mx25_csi_device = {
+	.name	= "mx2-camera",
+	.id	= 0,
+	.num_resources	= ARRAY_SIZE(mx25_csi_resources),
+	.resource	= mx25_csi_resources,
+	.dev		= {
+		.coherent_dma_mask = 0xFFFFFFFF,
+	},
+};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index cee12c0..b46f122 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -22,3 +22,4 @@ extern struct platform_device mxc_nand_device;
 extern struct platform_device mx25_rtc_device;
 extern struct platform_device mx25_fb_device;
 extern struct platform_device mxc_wdt;
+extern struct platform_device mx25_csi_device;
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 4eb6e33..5e6a8b5 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -34,11 +34,13 @@
 #define MX25_NFC_BASE_ADDR		0xbb000000
 #define MX25_DRYICE_BASE_ADDR		0x53ffc000
 #define MX25_LCDC_BASE_ADDR		0x53fbc000
+#define MX25_CSI_BASE_ADDR		0x53ff8000
 
 #define MX25_INT_DRYICE	25
 #define MX25_INT_FEC	57
 #define MX25_INT_NANDFC	33
 #define MX25_INT_LCDC	39
+#define MX25_INT_CSI	17
 
 #if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
 #define UART1_BASE_ADDR			MX25_UART1_BASE_ADDR
-- 
1.7.1



From jeremy.kerr at canonical.com  Mon Jun 21 01:35:13 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Mon, 21 Jun 2010 13:35:13 +0800
Subject: [PATCH 2/2] clk: Generic support for fixed-rate clocks
In-Reply-To: <1277098513.947165.104554431018.0.gpush@pororo>
Message-ID: <1277098513.947920.264679354891.2.gpush@pororo>

Since most platforms will need a fixed-rate clock, add one. This will
also serve as a basic example of an implementation of struct clk.

Signed-off-by: Jeremy Kerr <jeremy.kerr at canonical.com>

---
 include/linux/clk.h |   13 +++++++++++++
 kernel/clk.c        |   14 ++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/include/linux/clk.h b/include/linux/clk.h
index 5c1098b..1dce473 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -79,6 +79,19 @@ struct clk_ops {
  */
 int __clk_get(struct clk *clk);
 
+/* Simple fixed-rate clock */
+struct clk_fixed {
+	struct clk	clk;
+	unsigned long	rate;
+};
+
+extern struct clk_ops clk_fixed_ops;
+
+#define INIT_CLK_FIXED(r) { \
+	.clk = INIT_CLK(clk_fixed_ops), \
+	.rate = (r) \
+}
+
 #else /* !CONFIG_USE_COMMON_STRUCT_CLK */
 
 /*
diff --git a/kernel/clk.c b/kernel/clk.c
index cdea25f..32f25ef 100644
--- a/kernel/clk.c
+++ b/kernel/clk.c
@@ -99,3 +99,17 @@ struct clk *clk_get_parent(struct clk *clk)
 	return ERR_PTR(-ENOSYS);
 }
 EXPORT_SYMBOL_GPL(clk_get_parent);
+
+/* clk_fixed support */
+
+#define to_clk_fixed(clk) (container_of(clk, struct clk_fixed, clk))
+
+static unsigned long clk_fixed_get_rate(struct clk *clk)
+{
+	return to_clk_fixed(clk)->rate;
+}
+
+struct clk_ops clk_fixed_ops = {
+	.get_rate = clk_fixed_get_rate,
+};
+EXPORT_SYMBOL_GPL(clk_fixed_ops);


From jeremy.kerr at canonical.com  Mon Jun 21 01:35:13 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Mon, 21 Jun 2010 13:35:13 +0800
Subject: [PATCH 1/2] Add a common struct clk
In-Reply-To: <1277098513.947165.104554431018.0.gpush@pororo>
Message-ID: <1277098513.947633.945838133095.1.gpush@pororo>

We currently have 21 definitions of struct clk in the ARM architecture,
each defined on a per-platform basis. This makes it difficult to define
platform- (or architecture-) independent clock sources without making
assumptions about struct clk, and impossible to compile two
platforms with different struct clks into a single image.

This change is an effort to unify struct clk where possible, by defining
a common struct clk, containing a set of clock operations. Different
clock implementations can set their own operations, and have a standard
interface for generic code. The callback interface is exposed to the
kernel proper, while the clock implementations only need to be seen by
the platform internals.

This allows us to share clock code among platforms, and makes it
possible to dynamically create clock devices in platform-independent
code.

Platforms can enable the generic struct clock through
CONFIG_USE_COMMON_STRUCT_CLK. In this case, the clock infrastructure
consists of a common struct clk:

struct clk {
	const struct clk_ops	*ops;
	unsigned int		enable_count;
	struct mutex		mutex;
};

And a set of clock operations (defined per type of clock):

struct clk_operations {
       int             (*enable)(struct clk *);
       void            (*disable)(struct clk *);
       unsigned long   (*get_rate)(struct clk *);
       [...]
};

To define a hardware-specific clock, machine code can "subclass" the
struct clock into a new struct (adding any device-specific data), and
provide a set of operations:

struct clk_foo {
	struct clk	clk;
	void __iomem	*some_register;
};

struct clk_operations clk_foo_ops = {
	.get_rate = clk_foo_get_rate,
};

The common clock definitions are based on a development patch from Ben
Herrenschmidt <benh at kernel.crashing.org>.

Signed-off-by: Jeremy Kerr <jeremy.kerr at canonical.com>

---
 arch/Kconfig        |    3 +
 include/linux/clk.h |   77 +++++++++++++++++++++++++++++----
 kernel/Makefile     |    1 
 kernel/clk.c        |  101 ++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 173 insertions(+), 9 deletions(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index acda512..2458b5e 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -151,4 +151,7 @@ config HAVE_MIXED_BREAKPOINTS_REGS
 config HAVE_USER_RETURN_NOTIFIER
 	bool
 
+config USE_COMMON_STRUCT_CLK
+	bool
+
 source "kernel/gcov/Kconfig"
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 1d37f42..5c1098b 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -3,6 +3,7 @@
  *
  *  Copyright (C) 2004 ARM Limited.
  *  Written by Deep Blue Solutions Limited.
+ *  Copyright (c) 2010 Jeremy Kerr <jeremy.kerr at canonical.com>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -11,18 +12,82 @@
 #ifndef __LINUX_CLK_H
 #define __LINUX_CLK_H
 
+#include <linux/err.h>
+#include <linux/mutex.h>
+
 struct device;
 
-/*
- * The base API.
+#ifdef CONFIG_USE_COMMON_STRUCT_CLK
+
+/* If we're using the common struct clk, we define the base clk object here */
+
+/**
+ * struct clk - hardware independent clock structure
+ * @clk_ops:		implementation-specific ops for this clock
+ * @enable_count:	count of clk_enable() calls active on this clock
+ * @mutex:		lock for enable/disable or other HW-specific ops
+ *
+ * The base clock object, used by drivers for hardware-independent manipulation
+ * of clock lines. This will be 'subclassed' by device-specific implementations,
+ * which add device-specific data to struct clk. For example:
+ *
+ *  struct clk_foo {
+ *      struct clk;
+ *      [device specific fields]
+ *  };
+ *
+ * The clock driver code will manage the device-specific data, and pass
+ * clk_foo.clk to the common clock code. The clock driver will be called
+ * through the @ops callbacks.
+ *
+ * The @enable_count and @mutex members are initialised when a clock is
+ * registered with the arch-specific clock management code; the clock driver
+ * code does not need to handle these.
+ */
+struct clk {
+	const struct clk_ops	*ops;
+	unsigned int		enable_count;
+	struct mutex		mutex;
+};
+
+#define INIT_CLK(o) { .ops = &o, }
+
+struct clk_ops {
+       int		(*enable)(struct clk *);
+       void		(*disable)(struct clk *);
+       int		(*get)(struct clk *);
+       void		(*put)(struct clk *);
+       unsigned long	(*get_rate)(struct clk *);
+       long		(*round_rate)(struct clk *, unsigned long);
+       int		(*set_rate)(struct clk *, unsigned long);
+       int		(*set_parent)(struct clk *, struct clk *);
+       struct clk *	(*get_parent)(struct clk *);
+};
+
+/**
+ * __clk_get - update clock-specific refcounter
+ *
+ * @clk: The clock to refcount
+ *
+ * Before a clock is returned from clk_get, this function should be called
+ * to update any clock-specific refcounting.
+ *
+ * Returns non-zero on success, zero on failure. 
+ *
+ * Drivers should not need this function; it is only needed by the
+ * arch-specific clk_get() implementations.
  */
+int __clk_get(struct clk *clk);
 
+#else /* !CONFIG_USE_COMMON_STRUCT_CLK */
 
 /*
- * struct clk - an machine class defined object / cookie.
+ * Global clock object, actual structure is declared per-machine
  */
 struct clk;
 
+#endif /* !CONFIG_USE_COMMON_STRUCT_CLK */
+
 /**
  * clk_get - lookup and obtain a reference to a clock producer.
  * @dev: device for clock "consumer"
@@ -83,12 +148,6 @@ unsigned long clk_get_rate(struct clk *clk);
  */
 void clk_put(struct clk *clk);
 
-
-/*
- * The remaining APIs are optional for machine class support.
- */
-
-
 /**
  * clk_round_rate - adjust a rate to the exact rate a clock can provide
  * @clk: clock source
diff --git a/kernel/Makefile b/kernel/Makefile
index 057472f..1ae15aa 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -105,6 +105,7 @@ obj-$(CONFIG_PERF_EVENTS) += perf_event.o
 obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
 obj-$(CONFIG_USER_RETURN_NOTIFIER) += user-return-notifier.o
 obj-$(CONFIG_PADATA) += padata.o
+obj-$(CONFIG_USE_COMMON_STRUCT_CLK) += clk.o
 
 ifneq ($(CONFIG_SCHED_OMIT_FRAME_POINTER),y)
 # According to Alan Modra <alan at linuxcare.com.au>, the -fno-omit-frame-pointer is
diff --git a/kernel/clk.c b/kernel/clk.c
new file mode 100644
index 0000000..cdea25f
--- /dev/null
+++ b/kernel/clk.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2010 Canonical Ltd <jeremy.kerr at canonical.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Standard functionality for the common clock API.
+ */
+
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/module.h>
+
+int clk_enable(struct clk *clk)
+{
+	int ret = 0;
+
+	if (!clk->ops->enable)
+		return 0;
+
+	mutex_lock(&clk->mutex);
+	if (!clk->enable_count)
+		ret = clk->ops->enable(clk);
+
+	if (!ret)
+		clk->enable_count++;
+	mutex_unlock(&clk->mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+	if (!clk->ops->disable)
+		return;
+
+	mutex_lock(&clk->mutex);
+
+	if (!--clk->enable_count)
+		clk->ops->disable(clk);
+
+	mutex_unlock(&clk->mutex);
+}
+EXPORT_SYMBOL_GPL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	if (clk->ops->get_rate)
+		return clk->ops->get_rate(clk);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(clk_get_rate);
+
+int __clk_get(struct clk *clk)
+{
+	if (clk->ops->get)
+		return clk->ops->get(clk);
+	return 1;
+}
+EXPORT_SYMBOL_GPL(__clk_get);
+
+void clk_put(struct clk *clk)
+{
+	if (clk->ops->put)
+		clk->ops->put(clk);
+}
+EXPORT_SYMBOL_GPL(clk_put);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	if (clk->ops->round_rate)
+		return clk->ops->round_rate(clk, rate);
+	return -ENOSYS;
+}
+EXPORT_SYMBOL_GPL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	if (clk->ops->set_rate)
+		return clk->ops->set_rate(clk, rate);
+	return -ENOSYS;
+}
+EXPORT_SYMBOL_GPL(clk_set_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	if (clk->ops->set_parent)
+		return clk->ops->set_parent(clk, parent);
+	return -ENOSYS;
+}
+EXPORT_SYMBOL_GPL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+	if (clk->ops->get_parent)
+		return clk->ops->get_parent(clk);
+	return ERR_PTR(-ENOSYS);
+}
+EXPORT_SYMBOL_GPL(clk_get_parent);


From jeremy.kerr at canonical.com  Mon Jun 21 01:35:13 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Mon, 21 Jun 2010 13:35:13 +0800
Subject: [PATCH 0/2] Common struct clk implementation, v5
Message-ID: <1277098513.947165.104554431018.0.gpush@pororo>

Hi all,

These patches are an attempt to allow platforms to share clock code. At
present, the definitions of 'struct clk' are local to platform code,
which makes allocating and initialising cross-platform clock sources
difficult, and makes it impossible to compile a single image containing
support for two ARM platforms with different struct clks.

The two patches are for the architecture-independent kernel code,
introducing the common clk infrastructure. The changelog for the first
patch includes details about the new clock definitions.

As requested by rmk, I've put together a small series of patches
illustrating the usage of the common struct clock on the ARM imx51
platform. These are available in my git tree:

 git://kernel.ubuntu.com/jk/dt/linux-2.6

in the clk-common-mx51 branch (clk-common..clk-common-mx51).

The approach I've taken with the imx51 port is to temporarly duplicate
the platform-common clock code (ie, for all mxc-based boards) to enable
usage of the common struct clk on one machine (imx51), while leaving the
others as-is. For a proper platform-wide usage of the common struct clk,
we'd be better off doing the whole platform at once. However, mx51 is
the only mxc-based HW I have, hence the duplicated example port.

In the example port, the first change simply converts the mxc's struct
clk to a struct clk_mxc, using the new API.  The subsequent patches move
certain clocks to more specific data structures (eg clk_fixed and
clk_pll) where possible.

Ben Herrenschmidt is looking at using common struct clk code for powerpc
too, hence the kernel-wide approach.

Comments most welcome.

Cheers,


Jeremy

--
v5:
 * uninline main API, and share definitions with !USE_COMMON_STRUCT_CLK
 * add __clk_get
 * delay mutex init
 * kerneldoc for struct clk

v4:
 * use mutex for enable/disable locking
 * DEFINE_CLK -> INIT_CLK, and pass the clk name for mutex init
 * struct clk_operations -> struct clk_ops

v3:
 * do clock usage refcounting in common code
 * provide sample port

v2:
 * no longer ARM-specific
 * use clk_operations

---
Jeremy Kerr (2):
      Add a common struct clk
      clk: Generic support for fixed-rate clocks



From mike at compulab.co.il  Mon Jun 21 01:38:04 2010
From: mike at compulab.co.il (Mike Rapoport)
Date: Mon, 21 Jun 2010 08:38:04 +0300
Subject: [PATCH 1/4] [ARM] Remove now unnecessary dma_needs_bounce()
In-Reply-To: <AANLkTilJ3UpyHEplDqS_nV8SVDcl_pRRn4glDn7JS1GW@mail.gmail.com>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com>
	<1275724538-5075-2-git-send-email-eric.y.miao@gmail.com>
	<AANLkTilJ3UpyHEplDqS_nV8SVDcl_pRRn4glDn7JS1GW@mail.gmail.com>
Message-ID: <4C1EFABC.4020601@compulab.co.il>

Eric

Eric Miao wrote:
> On Sat, Jun 5, 2010 at 3:55 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>> With a correct dev->dma_mask before calling dmabounce_register_dev(),
>> dma_needs_bounce() is not necessary.
>>
>> The above is true for it8152.c and ixp4xx/common-pci.c.
>>
>> The sa1111, though, is a bit complicated. Until it's fully understood
>> and fixed, dma_needs_bounce() for sa1111 is kept if CONFIG_SA1111 is
>> enabled with no side effect (with the condition of machine_is_*)
>>
> 
> Sorry I forgot to CC you two. Any feedback is welcome, thanks.

Can I pull these changes from your git tree?

>> Signed-off-by: Eric Miao <eric.y.miao at gmail.com>
>> ---
>>  arch/arm/common/it8152.c           |    8 --------
>>  arch/arm/include/asm/dma-mapping.h |    7 +++++++
>>  arch/arm/mach-ixp4xx/common-pci.c  |    5 -----
>>  3 files changed, 7 insertions(+), 13 deletions(-)
>>
>> diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
>> index 7974baa..6c09135 100644
>> --- a/arch/arm/common/it8152.c
>> +++ b/arch/arm/common/it8152.c
>> @@ -263,14 +263,6 @@ static int it8152_pci_platform_notify_remove(struct device *dev)
>>        return 0;
>>  }
>>
>> -int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
>> -{
>> -       dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
>> -               __func__, dma_addr, size);
>> -       return (dev->bus == &pci_bus_type) &&
>> -               ((dma_addr + size - PHYS_OFFSET) >= SZ_64M);
>> -}
>> -
>>  int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
>>  {
>>        it8152_io.start = IT8152_IO_BASE + 0x12000;
>> diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
>> index 69ce072..c80d4d2 100644
>> --- a/arch/arm/include/asm/dma-mapping.h
>> +++ b/arch/arm/include/asm/dma-mapping.h
>> @@ -298,7 +298,14 @@ extern void dmabounce_unregister_dev(struct device *);
>>  * DMA access and 1 if the buffer needs to be bounced.
>>  *
>>  */
>> +#ifdef CONFIG_SA1111
>>  extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
>> +#else
>> +static inline int dma_needs_bounce(struct device*, dma_addr_t, size_t)
>> +{
>> +       return 0;
>> +}
>> +#endif
>>
>>  /*
>>  * The DMA API, implemented by dmabounce.c.  See below for descriptions.
>> diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
>> index e318153..c7aa0ac 100644
>> --- a/arch/arm/mach-ixp4xx/common-pci.c
>> +++ b/arch/arm/mach-ixp4xx/common-pci.c
>> @@ -337,11 +337,6 @@ static int ixp4xx_pci_platform_notify_remove(struct device *dev)
>>        return 0;
>>  }
>>
>> -int dma_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
>> -{
>> -       return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
>> -}
>> -
>>  /*
>>  * Only first 64MB of memory can be accessed via PCI.
>>  * We use GFP_DMA to allocate safe buffers to do map/unmap.
>> --
>> 1.7.0.4
>>
>>


-- 
Sincerely yours,
Mike.


From viresh.kumar at st.com  Mon Jun 21 01:39:13 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Mon, 21 Jun 2010 11:09:13 +0530
Subject: [PATCH] GPIO PL061: Adding Clk framework support
Message-ID: <1277098753-5780-1-git-send-email-viresh.kumar@st.com>

From: Viresh KUMAR <viresh.kumar at st.com>

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/gpio/pl061.c |   44 +++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/pl061.c b/drivers/gpio/pl061.c
index 105701a..5848237 100644
--- a/drivers/gpio/pl061.c
+++ b/drivers/gpio/pl061.c
@@ -11,7 +11,10 @@
  *
  * Data sheet: ARM DDI 0190B, September 2000
  */
+
+#include <linux/clk.h>
 #include <linux/spinlock.h>
+#include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/module.h>
 #include <linux/list.h>
@@ -56,8 +59,33 @@ struct pl061_gpio {
 	void __iomem		*base;
 	unsigned		irq_base;
 	struct gpio_chip	gc;
+	unsigned		usage_count;
+	struct clk		*clk;
 };
 
+static int pl061_request(struct gpio_chip *gc, unsigned offset)
+{
+	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
+
+	if (offset >= gc->ngpio)
+		return -EINVAL;
+
+	if (!chip->usage_count)
+		clk_enable(chip->clk);
+
+	chip->usage_count++;
+	return 0;
+}
+
+static void pl061_free(struct gpio_chip *gc, unsigned offset)
+{
+	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
+
+	chip->usage_count--;
+	if (!chip->usage_count)
+		clk_disable(chip->clk);
+}
+
 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
 {
 	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
@@ -260,10 +288,18 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 		goto release_region;
 	}
 
+	chip->clk = clk_get(&dev->dev, NULL);
+	if (IS_ERR(chip->clk)) {
+		ret = PTR_ERR(chip->clk);
+		goto iounmap;
+	}
+
 	spin_lock_init(&chip->lock);
 	spin_lock_init(&chip->irq_lock);
 	INIT_LIST_HEAD(&chip->list);
 
+	chip->gc.request = pl061_request;
+	chip->gc.free = pl061_free;
 	chip->gc.direction_input = pl061_direction_input;
 	chip->gc.direction_output = pl061_direction_output;
 	chip->gc.get = pl061_get_value;
@@ -279,7 +315,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 
 	ret = gpiochip_add(&chip->gc);
 	if (ret)
-		goto iounmap;
+		goto free_clk;
 
 	/*
 	 * irq_chip support
@@ -292,7 +328,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 	irq = dev->irq[0];
 	if (irq < 0) {
 		ret = -ENODEV;
-		goto iounmap;
+		goto free_clk;
 	}
 	set_irq_chained_handler(irq, pl061_irq_handler);
 	if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
@@ -300,7 +336,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 		if (chip_list == NULL) {
 			clear_bit(irq, init_irq);
 			ret = -ENOMEM;
-			goto iounmap;
+			goto free_clk;
 		}
 		INIT_LIST_HEAD(chip_list);
 		set_irq_data(irq, chip_list);
@@ -323,6 +359,8 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 
 	return 0;
 
+free_clk:
+	clk_put(chip->clk);
 iounmap:
 	iounmap(chip->base);
 release_region:
-- 
1.6.0.2



From baruch at tkos.co.il  Mon Jun 21 02:01:51 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Mon, 21 Jun 2010 09:01:51 +0300
Subject: [PATCH] GPIO PL061: Adding Clk framework support
In-Reply-To: <1277098753-5780-1-git-send-email-viresh.kumar@st.com>
References: <1277098753-5780-1-git-send-email-viresh.kumar@st.com>
Message-ID: <20100621060151.GC18217@jasper.tkos.co.il>

Hi Viresh,

On Mon, Jun 21, 2010 at 11:09:13AM +0530, Viresh KUMAR wrote:
> From: Viresh KUMAR <viresh.kumar at st.com>
> 
> Signed-off-by: Viresh Kumar <viresh.kumar at st.com>

Please add a commit log explaining the need for this change.

baruch

> ---
>  drivers/gpio/pl061.c |   44 +++++++++++++++++++++++++++++++++++++++++---
>  1 files changed, 41 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpio/pl061.c b/drivers/gpio/pl061.c
> index 105701a..5848237 100644
> --- a/drivers/gpio/pl061.c
> +++ b/drivers/gpio/pl061.c
> @@ -11,7 +11,10 @@
>   *
>   * Data sheet: ARM DDI 0190B, September 2000
>   */
> +
> +#include <linux/clk.h>
>  #include <linux/spinlock.h>
> +#include <linux/err.h>
>  #include <linux/errno.h>
>  #include <linux/module.h>
>  #include <linux/list.h>
> @@ -56,8 +59,33 @@ struct pl061_gpio {
>  	void __iomem		*base;
>  	unsigned		irq_base;
>  	struct gpio_chip	gc;
> +	unsigned		usage_count;
> +	struct clk		*clk;
>  };
>  
> +static int pl061_request(struct gpio_chip *gc, unsigned offset)
> +{
> +	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
> +
> +	if (offset >= gc->ngpio)
> +		return -EINVAL;
> +
> +	if (!chip->usage_count)
> +		clk_enable(chip->clk);
> +
> +	chip->usage_count++;
> +	return 0;
> +}
> +
> +static void pl061_free(struct gpio_chip *gc, unsigned offset)
> +{
> +	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
> +
> +	chip->usage_count--;
> +	if (!chip->usage_count)
> +		clk_disable(chip->clk);
> +}
> +
>  static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
>  {
>  	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
> @@ -260,10 +288,18 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
>  		goto release_region;
>  	}
>  
> +	chip->clk = clk_get(&dev->dev, NULL);
> +	if (IS_ERR(chip->clk)) {
> +		ret = PTR_ERR(chip->clk);
> +		goto iounmap;
> +	}
> +
>  	spin_lock_init(&chip->lock);
>  	spin_lock_init(&chip->irq_lock);
>  	INIT_LIST_HEAD(&chip->list);
>  
> +	chip->gc.request = pl061_request;
> +	chip->gc.free = pl061_free;
>  	chip->gc.direction_input = pl061_direction_input;
>  	chip->gc.direction_output = pl061_direction_output;
>  	chip->gc.get = pl061_get_value;
> @@ -279,7 +315,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
>  
>  	ret = gpiochip_add(&chip->gc);
>  	if (ret)
> -		goto iounmap;
> +		goto free_clk;
>  
>  	/*
>  	 * irq_chip support
> @@ -292,7 +328,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
>  	irq = dev->irq[0];
>  	if (irq < 0) {
>  		ret = -ENODEV;
> -		goto iounmap;
> +		goto free_clk;
>  	}
>  	set_irq_chained_handler(irq, pl061_irq_handler);
>  	if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
> @@ -300,7 +336,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
>  		if (chip_list == NULL) {
>  			clear_bit(irq, init_irq);
>  			ret = -ENOMEM;
> -			goto iounmap;
> +			goto free_clk;
>  		}
>  		INIT_LIST_HEAD(chip_list);
>  		set_irq_data(irq, chip_list);
> @@ -323,6 +359,8 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
>  
>  	return 0;
>  
> +free_clk:
> +	clk_put(chip->clk);
>  iounmap:
>  	iounmap(chip->base);
>  release_region:
> -- 
> 1.6.0.2
> 

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From viresh.kumar at st.com  Mon Jun 21 02:20:04 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Mon, 21 Jun 2010 11:50:04 +0530
Subject: [PATCH] GPIO PL061: Adding Clk framework support
In-Reply-To: <20100621060151.GC18217@jasper.tkos.co.il>
References: <1277098753-5780-1-git-send-email-viresh.kumar@st.com>
	<20100621060151.GC18217@jasper.tkos.co.il>
Message-ID: <4C1F0494.9040309@st.com>

On 6/21/2010 11:31 AM, Baruch Siach wrote:
> Hi Viresh,
> 
> On Mon, Jun 21, 2010 at 11:09:13AM +0530, Viresh KUMAR wrote:
>> From: Viresh KUMAR <viresh.kumar at st.com>
>>
>> Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
> 
> Please add a commit log explaining the need for this change.
> 

OK. Will resend it.


From jy0922.shim at samsung.com  Mon Jun 21 02:26:56 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Mon, 21 Jun 2010 15:26:56 +0900
Subject: [PATCH v5 0/3] Add samsung keypad
Message-ID: <4C1F0630.7090501@samsung.com>

This is patch v5 series to add Samsung keypad.

Changes since v1:
- Include linux/gpio.h instead of mach/gpio.h
- Switch to dev_pm_ops in the samsung keypad driver

Changes since v2:
- Add keypad device types to remove platform specific #ifdef
- Remove unnecessary include and checking codes.
- Rename from 'kp' to 'keypad'
- Rename keypad registers definition
- Modify 'rep' variable declaration

Changes since v3:
- Use schedule_delayed_work and remove timer
- Modify memory alloc codes
- Add MODULE_ALIAS() and missing error printk
- Change from rep to no_autorepeat and it's type to bool
- Add report EV_MSC/MSC_SCAN and wakeup control
- Remove s3c_set_platdata() call because there is not yet

Changes since v4:
- Add and use samsung_keypad_setname function
- Add more specific gpio comments

Joonyoung Shim (3):
      ARM: SAMSUNG: Add keypad device support
      ARM: S5PV210: Add keypad device helpers
      input: samsung-keypad - Add samsung keypad driver

 arch/arm/mach-s5pv210/Kconfig                    |    5 +
 arch/arm/mach-s5pv210/Makefile                   |    1 +
 arch/arm/mach-s5pv210/cpu.c                      |    4 +
 arch/arm/mach-s5pv210/include/mach/map.h         |    3 +
 arch/arm/mach-s5pv210/setup-keypad.c             |   34 ++
 arch/arm/plat-samsung/Kconfig                    |    5 +
 arch/arm/plat-samsung/Makefile                   |    1 +
 arch/arm/plat-samsung/dev-keypad.c               |   58 ++++
 arch/arm/plat-samsung/include/plat/devs.h        |    2 +
 arch/arm/plat-samsung/include/plat/keypad-core.h |   31 ++
 arch/arm/plat-samsung/include/plat/keypad.h      |   59 ++++
 arch/arm/plat-samsung/include/plat/regs-keypad.h |   49 +++
 drivers/input/keyboard/Kconfig                   |    9 +
 drivers/input/keyboard/Makefile                  |    1 +
 drivers/input/keyboard/samsung-keypad.c          |  400 ++++++++++++++++++++++
 15 files changed, 662 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pv210/setup-keypad.c
 create mode 100644 arch/arm/plat-samsung/dev-keypad.c
 create mode 100644 arch/arm/plat-samsung/include/plat/keypad-core.h
 create mode 100644 arch/arm/plat-samsung/include/plat/keypad.h
 create mode 100644 arch/arm/plat-samsung/include/plat/regs-keypad.h
 create mode 100644 drivers/input/keyboard/samsung-keypad.c


From jy0922.shim at samsung.com  Mon Jun 21 02:26:44 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Mon, 21 Jun 2010 15:26:44 +0900
Subject: [PATCH v5 2/3] ARM: S5PV210: Add keypad device helpers
In-Reply-To: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1277101605-2435-2-git-send-email-jy0922.shim@samsung.com>

This patch adds the keypad device platform helpers for S5PV210 cpu.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pv210/Kconfig                    |    5 +++
 arch/arm/mach-s5pv210/Makefile                   |    1 +
 arch/arm/mach-s5pv210/cpu.c                      |    4 ++
 arch/arm/mach-s5pv210/include/mach/map.h         |    3 ++
 arch/arm/mach-s5pv210/setup-keypad.c             |   34 ++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/keypad-core.h |   31 ++++++++++++++++++++
 6 files changed, 78 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pv210/setup-keypad.c
 create mode 100644 arch/arm/plat-samsung/include/plat/keypad-core.h

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0761eac..692d01c 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -32,6 +32,11 @@ config S5PV210_SETUP_FB_24BPP
 	help
           Common setup code for S5PV210 with an 24bpp RGB display helper.
 
+config S5PV210_SETUP_KEYPAD
+	bool
+	help
+	  Common setup code for keypad.
+
 config S5PV210_SETUP_SDHCI
         bool
         select S5PV210_SETUP_SDHCI_GPIO
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 30be9a6..aae592a 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o
 obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
 obj-$(CONFIG_S5PV210_SETUP_I2C1) 	+= setup-i2c1.o
 obj-$(CONFIG_S5PV210_SETUP_I2C2) 	+= setup-i2c2.o
+obj-$(CONFIG_S5PV210_SETUP_KEYPAD)	+= setup-keypad.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 411a4a9..94c632b 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -33,6 +33,7 @@
 #include <plat/clock.h>
 #include <plat/s5pv210.h>
 #include <plat/iic-core.h>
+#include <plat/keypad-core.h>
 #include <plat/sdhci.h>
 
 /* Initial IO mappings */
@@ -91,6 +92,9 @@ void __init s5pv210_map_io(void)
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
 	s3c_i2c2_setname("s3c2440-i2c");
+
+	/* Use s5pv210-keypad instead of samsung-keypad */
+	samsung_keypad_setname("s5pv210-keypad");
 }
 
 void __init s5pv210_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 34eb168..e2f6e2a 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -32,6 +32,8 @@
 #define S5PV210_PA_SPI0		0xE1300000
 #define S5PV210_PA_SPI1		0xE1400000
 
+#define S5PV210_PA_KEYPAD	(0xE1600000)
+
 #define S5PV210_PA_IIC0		(0xE1800000)
 #define S5PV210_PA_IIC1		(0xFAB00000)
 #define S5PV210_PA_IIC2		(0xE1A00000)
@@ -104,5 +106,6 @@
 #define S3C_PA_WDT		S5PV210_PA_WATCHDOG
 
 #define SAMSUNG_PA_ADC		S5PV210_PA_ADC
+#define SAMSUNG_PA_KEYPAD	S5PV210_PA_KEYPAD
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/setup-keypad.c b/arch/arm/mach-s5pv210/setup-keypad.c
new file mode 100644
index 0000000..37b2790
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-keypad.c
@@ -0,0 +1,34 @@
+/*
+ * linux/arch/arm/mach-s5pv210/setup-keypad.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+
+void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
+{
+	unsigned int gpio, end;
+
+	/* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
+	end = S5PV210_GPH3(rows);
+	for (gpio = S5PV210_GPH3(0); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
+	end = S5PV210_GPH2(cols);
+	for (gpio = S5PV210_GPH2(0); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+}
diff --git a/arch/arm/plat-samsung/include/plat/keypad-core.h b/arch/arm/plat-samsung/include/plat/keypad-core.h
new file mode 100644
index 0000000..d513e1b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/keypad-core.h
@@ -0,0 +1,31 @@
+/*
+ * linux/arch/arm/plat-samsung/include/plat/keypad-core.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ * Samsung keypad controller core function
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_KEYPAD_CORE_H
+#define __ASM_ARCH_KEYPAD_CORE_H
+
+/* These function are only for use with the core support code, such as
+ * the cpu specific initialisation code
+ */
+
+/* re-define device name depending on support. */
+static inline void samsung_keypad_setname(char *name)
+{
+#ifdef CONFIG_SAMSUNG_DEV_KEYPAD
+	samsung_device_keypad.name = name;
+#endif
+}
+
+#endif /* __ASM_ARCH_KEYPAD_CORE_H */
-- 
1.7.0.4



From jy0922.shim at samsung.com  Mon Jun 21 02:26:43 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Mon, 21 Jun 2010 15:26:43 +0900
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
Message-ID: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>

This patch adds samsung keypad device definition for samsung cpus.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-samsung/Kconfig                    |    5 ++
 arch/arm/plat-samsung/Makefile                   |    1 +
 arch/arm/plat-samsung/dev-keypad.c               |   58 +++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h        |    2 +
 arch/arm/plat-samsung/include/plat/keypad.h      |   59 ++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/regs-keypad.h |   49 ++++++++++++++++++
 6 files changed, 174 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-samsung/dev-keypad.c
 create mode 100644 arch/arm/plat-samsung/include/plat/keypad.h
 create mode 100644 arch/arm/plat-samsung/include/plat/regs-keypad.h

diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 2753fb3..bd007e3 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -227,6 +227,11 @@ config SAMSUNG_DEV_TS
 	help
 	    Common in platform device definitions for touchscreen device
 
+config SAMSUNG_DEV_KEYPAD
+	bool
+	help
+	  Compile in platform device definitions for keypad
+
 # DMA
 
 config S3C_DMA
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index b1d82cc..8269d80 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_S3C_DEV_RTC)	+= dev-rtc.o
 
 obj-$(CONFIG_SAMSUNG_DEV_ADC)	+= dev-adc.o
 obj-$(CONFIG_SAMSUNG_DEV_TS)	+= dev-ts.o
+obj-$(CONFIG_SAMSUNG_DEV_KEYPAD)	+= dev-keypad.o
 
 # DMA support
 
diff --git a/arch/arm/plat-samsung/dev-keypad.c b/arch/arm/plat-samsung/dev-keypad.c
new file mode 100644
index 0000000..679b444
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-keypad.c
@@ -0,0 +1,58 @@
+/*
+ * linux/arch/arm/plat-samsung/dev-keypad.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/keypad.h>
+
+static struct resource samsung_keypad_resources[] = {
+	[0] = {
+		.start	= SAMSUNG_PA_KEYPAD,
+		.end	= SAMSUNG_PA_KEYPAD + 0x20 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_KEYPAD,
+		.end	= IRQ_KEYPAD,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device samsung_device_keypad = {
+	.name		= "samsung-keypad",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(samsung_keypad_resources),
+	.resource	= samsung_keypad_resources,
+};
+
+void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
+{
+	struct samsung_keypad_platdata *npd;
+
+	if (!pd) {
+		printk(KERN_ERR "%s: no platform data\n", __func__);
+		return;
+	}
+
+	npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
+	if (!npd)
+		printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+
+	if (!npd->cfg_gpio)
+		npd->cfg_gpio = samsung_keypad_cfg_gpio;
+
+	samsung_device_keypad.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index e6144e4..6d9f01b 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -100,6 +100,8 @@ extern struct platform_device s5pc100_device_iis0;
 extern struct platform_device s5pc100_device_iis1;
 extern struct platform_device s5pc100_device_iis2;
 
+extern struct platform_device samsung_device_keypad;
+
 /* s3c2440 specific devices */
 
 #ifdef CONFIG_CPU_S3C2440
diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/plat-samsung/include/plat/keypad.h
new file mode 100644
index 0000000..6d139d6
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/keypad.h
@@ -0,0 +1,59 @@
+/*
+ * linux/arch/arm/plat-samsung/include/plat/keypad.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ * Samsung Platform - Keypad platform data definitions
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __PLAT_SAMSUNG_KEYPAD_H
+#define __PLAT_SAMSUNG_KEYPAD_H
+
+#include <linux/input/matrix_keypad.h>
+
+#define SAMSUNG_MAX_ROWS	8
+#define SAMSUNG_MAX_COLS	8
+
+/**
+ * struct samsung_keypad_platdata - Platform device data for Samsung Keypad.
+ * @keymap_data: pointer to &matrix_keymap_data.
+ * @rows: number of keypad row supported.
+ * @cols: number of keypad col supported.
+ * @no_autorepeat: disable key autorepeat.
+ * @wakeup: controls whether the device should be set up as wakeup source.
+ * @cfg_gpio: configure the GPIO.
+ *
+ * Initialisation data specific to either the machine or the platform
+ * for the device driver to use or call-back when configuring gpio.
+ */
+struct samsung_keypad_platdata {
+	const struct matrix_keymap_data	*keymap_data;
+	unsigned int		rows;
+	unsigned int		cols;
+	bool			no_autorepeat;
+	bool			wakeup;
+
+	void	(*cfg_gpio)(unsigned int rows, unsigned int cols);
+};
+
+/**
+ * samsung_keypad_set_platdata - Set platform data for Samsung Keypad device.
+ * @pd: Platform data to register to device.
+ *
+ * Register the given platform data for use with Samsung Keypad device.
+ * The call will copy the platform data, so the board definitions can
+ * make the structure itself __initdata.
+ */
+extern void samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd);
+
+/* defined by architecture to configure gpio. */
+extern void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols);
+
+#endif /* __PLAT_SAMSUNG_KEYPAD_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-keypad.h b/arch/arm/plat-samsung/include/plat/regs-keypad.h
new file mode 100644
index 0000000..e4688f0
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-keypad.h
@@ -0,0 +1,49 @@
+/*
+ * linux/arch/arm/plat-samsung/include/plat/regs-keypad.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __SAMSUNG_KEYPAD_H__
+#define __SAMSUNG_KEYPAD_H__
+
+#define SAMSUNG_KEYIFCON			0x00
+#define SAMSUNG_KEYIFSTSCLR			0x04
+#define SAMSUNG_KEYIFCOL			0x08
+#define SAMSUNG_KEYIFROW			0x0c
+#define SAMSUNG_KEYIFFC				0x10
+
+/* SAMSUNG_KEYIFCON */
+#define SAMSUNG_KEYIFCON_INT_F_EN		(1 << 0)
+#define SAMSUNG_KEYIFCON_INT_R_EN		(1 << 1)
+#define SAMSUNG_KEYIFCON_DF_EN			(1 << 2)
+#define SAMSUNG_KEYIFCON_FC_EN			(1 << 3)
+#define SAMSUNG_KEYIFCON_WAKEUPEN		(1 << 4)
+
+/* SAMSUNG_KEYIFSTSCLR */
+#define SAMSUNG_KEYIFSTSCLR_P_INT_MASK		(0xff << 0)
+#define SAMSUNG_KEYIFSTSCLR_R_INT_MASK		(0xff << 8)
+#define SAMSUNG_KEYIFSTSCLR_R_INT_OFFSET	8
+#define S5PV210_KEYIFSTSCLR_P_INT_MASK		(0x3fff << 0)
+#define S5PV210_KEYIFSTSCLR_R_INT_MASK		(0x3fff << 16)
+#define S5PV210_KEYIFSTSCLR_R_INT_OFFSET	16
+
+/* SAMSUNG_KEYIFCOL */
+#define SAMSUNG_KEYIFCOL_MASK			(0xff << 0)
+#define S5PV210_KEYIFCOLEN_MASK			(0xff << 8)
+
+/* SAMSUNG_KEYIFROW */
+#define SAMSUNG_KEYIFROW_MASK			(0xff << 0)
+#define S5PV210_KEYIFROW_MASK			(0x3fff << 0)
+
+/* SAMSUNG_KEYIFFC */
+#define SAMSUNG_KEYIFFC_MASK			(0x3ff << 0)
+
+#endif /* __SAMSUNG_KEYPAD_H__ */
-- 
1.7.0.4



From jy0922.shim at samsung.com  Mon Jun 21 02:26:45 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Mon, 21 Jun 2010 15:26:45 +0900
Subject: [PATCH v5 3/3] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1277101605-2435-3-git-send-email-jy0922.shim@samsung.com>

This patch adds support for keypad driver running on Samsung cpus. This
driver is tested on GONI and Aquila board using S5PC110 cpu.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/input/keyboard/Kconfig          |    9 +
 drivers/input/keyboard/Makefile         |    1 +
 drivers/input/keyboard/samsung-keypad.c |  400 +++++++++++++++++++++++++++++++
 3 files changed, 410 insertions(+), 0 deletions(-)
 create mode 100644 drivers/input/keyboard/samsung-keypad.c

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index d8fa5d7..bf6a50f 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -342,6 +342,15 @@ config KEYBOARD_PXA930_ROTARY
 	  To compile this driver as a module, choose M here: the
 	  module will be called pxa930_rotary.
 
+config KEYBOARD_SAMSUNG
+	tristate "Samsung keypad support"
+	depends on SAMSUNG_DEV_KEYPAD
+	help
+	  Say Y here if you want to use the Samsung keypad.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called samsung-keypad.
+
 config KEYBOARD_STOWAWAY
 	tristate "Stowaway keyboard"
 	select SERIO
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 4596d0c..8f973ed 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_KEYBOARD_OPENCORES)	+= opencores-kbd.o
 obj-$(CONFIG_KEYBOARD_PXA27x)		+= pxa27x_keypad.o
 obj-$(CONFIG_KEYBOARD_PXA930_ROTARY)	+= pxa930_rotary.o
 obj-$(CONFIG_KEYBOARD_QT2160)		+= qt2160.o
+obj-$(CONFIG_KEYBOARD_SAMSUNG)		+= samsung-keypad.o
 obj-$(CONFIG_KEYBOARD_SH_KEYSC)		+= sh_keysc.o
 obj-$(CONFIG_KEYBOARD_STOWAWAY)		+= stowaway.o
 obj-$(CONFIG_KEYBOARD_SUNKBD)		+= sunkbd.o
diff --git a/drivers/input/keyboard/samsung-keypad.c b/drivers/input/keyboard/samsung-keypad.c
new file mode 100644
index 0000000..4b56e6f
--- /dev/null
+++ b/drivers/input/keyboard/samsung-keypad.c
@@ -0,0 +1,400 @@
+/*
+ * samsung-keypad.c  --  Samsung keypad driver
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ * Author: Donghwa Lee <dh09.lee at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <plat/keypad.h>
+#include <plat/regs-keypad.h>
+
+enum samsung_keypad_type {
+	KEYPAD_TYPE_SAMSUNG,
+	KEYPAD_TYPE_S5PV210,
+};
+
+struct samsung_keypad {
+	struct input_dev *input_dev;
+	struct clk *clk;
+	struct delayed_work work;
+	void __iomem *base;
+	unsigned short *keycodes;
+	unsigned int row_shift;
+	unsigned int rows;
+	unsigned int cols;
+	unsigned int row_state[SAMSUNG_MAX_COLS];
+	int irq;
+};
+
+static int samsung_keypad_is_s5pv210(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	enum samsung_keypad_type type;
+
+	type = platform_get_device_id(pdev)->driver_data;
+	return type == KEYPAD_TYPE_S5PV210;
+}
+
+static void samsung_keypad_scan(struct samsung_keypad *keypad,
+		unsigned int *row_state)
+{
+	struct device *dev = keypad->input_dev->dev.parent;
+	unsigned int col;
+	unsigned int val;
+
+	for (col = 0; col < keypad->cols; col++) {
+		if (samsung_keypad_is_s5pv210(dev)) {
+			val = S5PV210_KEYIFCOLEN_MASK;
+			val &= ~(1 << col) << 8;
+		} else {
+			val = SAMSUNG_KEYIFCOL_MASK;
+			val &= ~(1 << col);
+		}
+
+		writel(val, keypad->base + SAMSUNG_KEYIFCOL);
+		mdelay(1);
+
+		val = readl(keypad->base + SAMSUNG_KEYIFROW);
+		row_state[col] = ~val & ((1 << keypad->rows) - 1);
+	}
+
+	/* KEYIFCOL reg clear */
+	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+}
+
+static void samsung_keypad_worker(struct work_struct *work)
+{
+	struct samsung_keypad *keypad = container_of(work,
+			struct samsung_keypad, work.work);
+	unsigned int row_state[SAMSUNG_MAX_COLS];
+	unsigned int val;
+	unsigned int changed;
+	unsigned int pressed;
+	unsigned int key_down = 0;
+	int col, row;
+
+	clk_enable(keypad->clk);
+
+	val = readl(keypad->base + SAMSUNG_KEYIFSTSCLR);
+
+	/* interrupt clear */
+	writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR);
+
+	val = readl(keypad->base + SAMSUNG_KEYIFCON);
+	val &= ~(SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN);
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	samsung_keypad_scan(keypad, row_state);
+
+	for (col = 0; col < keypad->cols; col++) {
+		changed = row_state[col] ^ keypad->row_state[col];
+		key_down |= row_state[col];
+		if (!changed)
+			continue;
+
+		for (row = 0; row < keypad->rows; row++) {
+			if (!(changed & (1 << row)))
+				continue;
+
+			pressed = row_state[col] & (1 << row);
+
+			dev_dbg(&keypad->input_dev->dev,
+				"key %s, row: %d, col: %d\n",
+				pressed ? "pressed" : "released", row, col);
+
+			val = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
+
+			input_event(keypad->input_dev, EV_MSC, MSC_SCAN, val);
+			input_report_key(keypad->input_dev,
+					keypad->keycodes[val], pressed);
+			input_sync(keypad->input_dev);
+		}
+	}
+	memcpy(keypad->row_state, row_state, sizeof(row_state));
+
+	if (key_down)
+		schedule_delayed_work(&keypad->work, HZ / 20);
+	else {
+		/* enable interrupt bit */
+		val = readl(keypad->base + SAMSUNG_KEYIFCON);
+		val |= (SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN);
+		writel(val, keypad->base + SAMSUNG_KEYIFCON);
+		enable_irq(keypad->irq);
+	}
+	clk_disable(keypad->clk);
+}
+
+static irqreturn_t samsung_keypad_interrupt(int irq, void *dev_id)
+{
+	struct samsung_keypad *keypad = dev_id;
+
+	if (!work_pending(&keypad->work.work)) {
+		disable_irq_nosync(keypad->irq);
+		schedule_delayed_work(&keypad->work, 0);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int __devinit samsung_keypad_probe(struct platform_device *pdev)
+{
+	const struct samsung_keypad_platdata *pdata;
+	const struct matrix_keymap_data *keymap_data;
+	struct samsung_keypad *keypad;
+	struct resource *res;
+	struct input_dev *input_dev;
+	unsigned short *keycodes;
+	unsigned int row_shift;
+	unsigned int val;
+	int ret;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "no platform data defined\n");
+		return -EINVAL;
+	}
+
+	keymap_data = pdata->keymap_data;
+	if (!keymap_data) {
+		dev_err(&pdev->dev, "no keymap data defined\n");
+		return -EINVAL;
+	}
+
+	if (!pdata->rows || (pdata->rows > SAMSUNG_MAX_ROWS))
+		return -EINVAL;
+
+	if (!pdata->cols || (pdata->cols > SAMSUNG_MAX_COLS))
+		return -EINVAL;
+
+	/* initialize the gpio */
+	if (pdata->cfg_gpio)
+		pdata->cfg_gpio(pdata->rows, pdata->cols);
+
+	row_shift = get_count_order(pdata->cols);
+	/* alloc with keycodes memory */
+	keypad = kzalloc(sizeof(*keypad) + sizeof(*keycodes) *
+			(pdata->rows << row_shift), GFP_KERNEL);
+	input_dev = input_allocate_device();
+	if (!keypad || !input_dev) {
+		ret = -ENOMEM;
+		goto err_free_mem;
+	}
+	keycodes = (unsigned short *)(keypad + 1);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		ret = -ENODEV;
+		goto err_free_mem;
+	}
+
+	keypad->base = ioremap(res->start, resource_size(res));
+	if (!keypad->base) {
+		ret = -EBUSY;
+		goto err_free_mem;
+	}
+
+	keypad->clk = clk_get(&pdev->dev, "keypad");
+	if (IS_ERR(keypad->clk)) {
+		dev_err(&pdev->dev, "failed to get keypad clk\n");
+		ret = PTR_ERR(keypad->clk);
+		goto err_unmap_base;
+	}
+	clk_enable(keypad->clk);
+
+	keypad->input_dev = input_dev;
+	keypad->keycodes = keycodes;
+	keypad->row_shift = row_shift;
+	keypad->rows = pdata->rows;
+	keypad->cols = pdata->cols;
+
+	INIT_DELAYED_WORK(&keypad->work, samsung_keypad_worker);
+
+	/* enable interrupt and wakeup bit */
+	val = SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN |
+		SAMSUNG_KEYIFCON_WAKEUPEN;
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	/* KEYIFCOL reg clear */
+	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+
+	keypad->irq = platform_get_irq(pdev, 0);
+	if (keypad->irq < 0) {
+		ret = keypad->irq;
+		goto err_disable_clk;
+	}
+
+	ret = request_irq(keypad->irq, samsung_keypad_interrupt, 0,
+			dev_name(&pdev->dev), keypad);
+
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register keypad interrupt\n");
+		goto err_disable_clk;
+	}
+
+	input_dev->name = pdev->name;
+	input_dev->id.bustype = BUS_HOST;
+	input_dev->dev.parent = &pdev->dev;
+
+	input_dev->evbit[0] = BIT_MASK(EV_KEY);
+	if (!pdata->no_autorepeat)
+		input_dev->evbit[0] |= BIT_MASK(EV_REP);
+
+	input_dev->keycode = keycodes;
+	input_dev->keycodesize = sizeof(*keycodes);
+	input_dev->keycodemax = pdata->rows << row_shift;
+
+	matrix_keypad_build_keymap(keymap_data, row_shift,
+			input_dev->keycode, input_dev->keybit);
+
+	input_set_capability(input_dev, EV_MSC, MSC_SCAN);
+
+	ret = input_register_device(keypad->input_dev);
+	if (ret)
+		goto err_free_irq;
+
+	device_init_wakeup(&pdev->dev, pdata->wakeup);
+	platform_set_drvdata(pdev, keypad);
+	clk_disable(keypad->clk);
+
+	return 0;
+
+err_free_irq:
+	free_irq(keypad->irq, keypad);
+err_disable_clk:
+	clk_disable(keypad->clk);
+	clk_put(keypad->clk);
+err_unmap_base:
+	iounmap(keypad->base);
+err_free_mem:
+	input_free_device(input_dev);
+	kfree(keypad);
+
+	return ret;
+}
+
+static int __devexit samsung_keypad_remove(struct platform_device *pdev)
+{
+	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+
+	device_init_wakeup(&pdev->dev, 0);
+
+	free_irq(keypad->irq, keypad);
+	cancel_delayed_work_sync(&keypad->work);
+
+	platform_set_drvdata(pdev, NULL);
+	input_unregister_device(keypad->input_dev);
+
+	clk_disable(keypad->clk);
+	clk_put(keypad->clk);
+
+	iounmap(keypad->base);
+	kfree(keypad);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int samsung_keypad_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+
+	disable_irq(keypad->irq);
+
+	if (device_may_wakeup(&pdev->dev))
+		enable_irq_wake(keypad->irq);
+
+	return 0;
+}
+
+static int samsung_keypad_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+	unsigned int val;
+
+	if (device_may_wakeup(&pdev->dev))
+		disable_irq_wake(keypad->irq);
+
+	clk_enable(keypad->clk);
+
+	/* enable interrupt and wakeup bit */
+	val = SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN |
+		SAMSUNG_KEYIFCON_WAKEUPEN;
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	/* KEYIFCOL reg clear */
+	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+
+	clk_disable(keypad->clk);
+
+	enable_irq(keypad->irq);
+
+	return 0;
+}
+
+static const struct dev_pm_ops samsung_keypad_pm_ops = {
+	.suspend	= samsung_keypad_suspend,
+	.resume		= samsung_keypad_resume,
+};
+#endif
+
+static struct platform_device_id samsung_keypad_driver_ids[] = {
+	{
+		.name		= "samsung-keypad",
+		.driver_data	= KEYPAD_TYPE_SAMSUNG,
+	}, {
+		.name		= "s5pv210-keypad",
+		.driver_data	= KEYPAD_TYPE_S5PV210,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(platform, samsung_keypad_driver_ids);
+
+static struct platform_driver samsung_keypad_driver = {
+	.probe		= samsung_keypad_probe,
+	.remove		= __devexit_p(samsung_keypad_remove),
+	.driver		= {
+		.name	= "samsung-keypad",
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &samsung_keypad_pm_ops,
+#endif
+	},
+	.id_table	= samsung_keypad_driver_ids,
+};
+
+static int __init samsung_keypad_init(void)
+{
+	return platform_driver_register(&samsung_keypad_driver);
+}
+
+static void __exit samsung_keypad_exit(void)
+{
+	platform_driver_unregister(&samsung_keypad_driver);
+}
+
+module_init(samsung_keypad_init);
+module_exit(samsung_keypad_exit);
+
+MODULE_DESCRIPTION("Samsung keypad driver");
+MODULE_AUTHOR("Joonyoung Shim <jy0922.shim at samsung.com>");
+MODULE_AUTHOR("Donghwa Lee <dh09.lee at samsung.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:samsung-keypad");
-- 
1.7.0.4



From viresh.kumar at st.com  Mon Jun 21 02:32:23 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Mon, 21 Jun 2010 12:02:23 +0530
Subject: [PATCH resend] GPIO PL061: Adding Clk framework support
Message-ID: <1277101943-6887-1-git-send-email-viresh.kumar@st.com>

From: Viresh KUMAR <viresh.kumar at st.com>

GPIO Clk is never enabled on Platforms, like: SPEAr, which are based upon clock
framework and use PL061 driver. This patch adds support for Clk enabling and
disabling as and when gpios are requested and freed.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/gpio/pl061.c |   44 +++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/pl061.c b/drivers/gpio/pl061.c
index 105701a..5848237 100644
--- a/drivers/gpio/pl061.c
+++ b/drivers/gpio/pl061.c
@@ -11,7 +11,10 @@
  *
  * Data sheet: ARM DDI 0190B, September 2000
  */
+
+#include <linux/clk.h>
 #include <linux/spinlock.h>
+#include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/module.h>
 #include <linux/list.h>
@@ -56,8 +59,33 @@ struct pl061_gpio {
 	void __iomem		*base;
 	unsigned		irq_base;
 	struct gpio_chip	gc;
+	unsigned		usage_count;
+	struct clk		*clk;
 };
 
+static int pl061_request(struct gpio_chip *gc, unsigned offset)
+{
+	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
+
+	if (offset >= gc->ngpio)
+		return -EINVAL;
+
+	if (!chip->usage_count)
+		clk_enable(chip->clk);
+
+	chip->usage_count++;
+	return 0;
+}
+
+static void pl061_free(struct gpio_chip *gc, unsigned offset)
+{
+	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
+
+	chip->usage_count--;
+	if (!chip->usage_count)
+		clk_disable(chip->clk);
+}
+
 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
 {
 	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
@@ -260,10 +288,18 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 		goto release_region;
 	}
 
+	chip->clk = clk_get(&dev->dev, NULL);
+	if (IS_ERR(chip->clk)) {
+		ret = PTR_ERR(chip->clk);
+		goto iounmap;
+	}
+
 	spin_lock_init(&chip->lock);
 	spin_lock_init(&chip->irq_lock);
 	INIT_LIST_HEAD(&chip->list);
 
+	chip->gc.request = pl061_request;
+	chip->gc.free = pl061_free;
 	chip->gc.direction_input = pl061_direction_input;
 	chip->gc.direction_output = pl061_direction_output;
 	chip->gc.get = pl061_get_value;
@@ -279,7 +315,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 
 	ret = gpiochip_add(&chip->gc);
 	if (ret)
-		goto iounmap;
+		goto free_clk;
 
 	/*
 	 * irq_chip support
@@ -292,7 +328,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 	irq = dev->irq[0];
 	if (irq < 0) {
 		ret = -ENODEV;
-		goto iounmap;
+		goto free_clk;
 	}
 	set_irq_chained_handler(irq, pl061_irq_handler);
 	if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
@@ -300,7 +336,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 		if (chip_list == NULL) {
 			clear_bit(irq, init_irq);
 			ret = -ENOMEM;
-			goto iounmap;
+			goto free_clk;
 		}
 		INIT_LIST_HEAD(chip_list);
 		set_irq_data(irq, chip_list);
@@ -323,6 +359,8 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 
 	return 0;
 
+free_clk:
+	clk_put(chip->clk);
 iounmap:
 	iounmap(chip->base);
 release_region:
-- 
1.6.0.2



From linux at arm.linux.org.uk  Mon Jun 21 02:38:48 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 07:38:48 +0100
Subject: [PATCH resend] GPIO PL061: Adding Clk framework support
In-Reply-To: <1277101943-6887-1-git-send-email-viresh.kumar@st.com>
References: <1277101943-6887-1-git-send-email-viresh.kumar@st.com>
Message-ID: <20100621063848.GA7582@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 12:02:23PM +0530, Viresh KUMAR wrote:
> @@ -56,8 +59,33 @@ struct pl061_gpio {
>  	void __iomem		*base;
>  	unsigned		irq_base;
>  	struct gpio_chip	gc;
> +	unsigned		usage_count;
> +	struct clk		*clk;
>  };
>  
> +static int pl061_request(struct gpio_chip *gc, unsigned offset)
> +{
> +	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
> +
> +	if (offset >= gc->ngpio)
> +		return -EINVAL;
> +
> +	if (!chip->usage_count)
> +		clk_enable(chip->clk);

Clocks are already use-counted.


From viresh.kumar at st.com  Mon Jun 21 02:44:28 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Mon, 21 Jun 2010 12:14:28 +0530
Subject: [PATCH resend] GPIO PL061: Adding Clk framework support
In-Reply-To: <20100621063848.GA7582@n2100.arm.linux.org.uk>
References: <1277101943-6887-1-git-send-email-viresh.kumar@st.com>
	<20100621063848.GA7582@n2100.arm.linux.org.uk>
Message-ID: <4C1F0A4C.2070201@st.com>

On 6/21/2010 12:08 PM, Russell King - ARM Linux wrote:
> On Mon, Jun 21, 2010 at 12:02:23PM +0530, Viresh KUMAR wrote:
>> @@ -56,8 +59,33 @@ struct pl061_gpio {
>>  	void __iomem		*base;
>>  	unsigned		irq_base;
>>  	struct gpio_chip	gc;
>> +	unsigned		usage_count;
>> +	struct clk		*clk;
>>  };
>>  
>> +static int pl061_request(struct gpio_chip *gc, unsigned offset)
>> +{
>> +	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
>> +
>> +	if (offset >= gc->ngpio)
>> +		return -EINVAL;
>> +
>> +	if (!chip->usage_count)
>> +		clk_enable(chip->clk);
> 
> Clocks are already use-counted.
> 

Yes. This is not required. Can simple call clk_enable and clk_disable.


From s.hauer at pengutronix.de  Mon Jun 21 02:51:58 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 21 Jun 2010 08:51:58 +0200
Subject: [PATCH 2/2] mach-cpuimx27: fix USB_ULPI build warnings
In-Reply-To: <1276870795-21594-2-git-send-email-eric@eukrea.com>
References: <1276870795-21594-1-git-send-email-eric@eukrea.com>
	<1276870795-21594-2-git-send-email-eric@eukrea.com>
Message-ID: <20100621065158.GD12115@pengutronix.de>


On Fri, Jun 18, 2010 at 04:19:55PM +0200, Eric B?nard wrote:
> when CONFIG_USB_ULPI is not defined we actually get :
> warning: 'otg_pdata' defined but not used
> warning: 'usbh2_pdata' defined but not used

Ok, applied.

> 
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: s.hauer at pengutronix.de
> ---
>  arch/arm/mach-mx2/mach-cpuimx27.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-mx2/mach-cpuimx27.c
> index dc2dca3..5529178 100644
> --- a/arch/arm/mach-mx2/mach-cpuimx27.c
> +++ b/arch/arm/mach-mx2/mach-cpuimx27.c
> @@ -219,6 +219,7 @@ static struct platform_device serial_device = {
>  };
>  #endif
>  
> +#if defined(CONFIG_USB_ULPI)
>  static struct mxc_usbh_platform_data otg_pdata = {
>  	.portsc	= MXC_EHCI_MODE_ULPI,
>  	.flags	= MXC_EHCI_INTERFACE_DIFF_UNI,
> @@ -228,6 +229,7 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
>  	.portsc	= MXC_EHCI_MODE_ULPI,
>  	.flags	= MXC_EHCI_INTERFACE_DIFF_UNI,
>  };
> +#endif
>  
>  static struct fsl_usb2_platform_data otg_device_pdata = {
>  	.operating_mode = FSL_USB2_DR_DEVICE,
> -- 
> 1.6.3.3
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From viresh.kumar at st.com  Mon Jun 21 02:57:43 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Mon, 21 Jun 2010 12:27:43 +0530
Subject: [PATCH V2] GPIO PL061: Adding Clk framework support
Message-ID: <1277103463-7311-1-git-send-email-viresh.kumar@st.com>

From: Viresh KUMAR <viresh.kumar at st.com>

GPIO Clk is never enabled on Platforms, like: SPEAr, which are based upon clock
framework and use PL061 driver. This patch adds support for Clk enabling and
disabling as and when gpios are requested and freed.

Modifications since V1:
 - Removed usage_count, as already done by clk framework.
 - Checking error case of clk_enable.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/gpio/pl061.c |   37 ++++++++++++++++++++++++++++++++++---
 1 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/pl061.c b/drivers/gpio/pl061.c
index 105701a..fd37349 100644
--- a/drivers/gpio/pl061.c
+++ b/drivers/gpio/pl061.c
@@ -11,7 +11,10 @@
  *
  * Data sheet: ARM DDI 0190B, September 2000
  */
+
+#include <linux/clk.h>
 #include <linux/spinlock.h>
+#include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/module.h>
 #include <linux/list.h>
@@ -56,8 +59,26 @@ struct pl061_gpio {
 	void __iomem		*base;
 	unsigned		irq_base;
 	struct gpio_chip	gc;
+	struct clk		*clk;
 };
 
+static int pl061_request(struct gpio_chip *gc, unsigned offset)
+{
+	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
+
+	if (offset >= gc->ngpio)
+		return -EINVAL;
+
+	return clk_enable(chip->clk);
+}
+
+static void pl061_free(struct gpio_chip *gc, unsigned offset)
+{
+	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
+
+	clk_disable(chip->clk);
+}
+
 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
 {
 	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
@@ -260,10 +281,18 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 		goto release_region;
 	}
 
+	chip->clk = clk_get(&dev->dev, NULL);
+	if (IS_ERR(chip->clk)) {
+		ret = PTR_ERR(chip->clk);
+		goto iounmap;
+	}
+
 	spin_lock_init(&chip->lock);
 	spin_lock_init(&chip->irq_lock);
 	INIT_LIST_HEAD(&chip->list);
 
+	chip->gc.request = pl061_request;
+	chip->gc.free = pl061_free;
 	chip->gc.direction_input = pl061_direction_input;
 	chip->gc.direction_output = pl061_direction_output;
 	chip->gc.get = pl061_get_value;
@@ -279,7 +308,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 
 	ret = gpiochip_add(&chip->gc);
 	if (ret)
-		goto iounmap;
+		goto free_clk;
 
 	/*
 	 * irq_chip support
@@ -292,7 +321,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 	irq = dev->irq[0];
 	if (irq < 0) {
 		ret = -ENODEV;
-		goto iounmap;
+		goto free_clk;
 	}
 	set_irq_chained_handler(irq, pl061_irq_handler);
 	if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
@@ -300,7 +329,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 		if (chip_list == NULL) {
 			clear_bit(irq, init_irq);
 			ret = -ENOMEM;
-			goto iounmap;
+			goto free_clk;
 		}
 		INIT_LIST_HEAD(chip_list);
 		set_irq_data(irq, chip_list);
@@ -323,6 +352,8 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 
 	return 0;
 
+free_clk:
+	clk_put(chip->clk);
 iounmap:
 	iounmap(chip->base);
 release_region:
-- 
1.6.0.2



From s.hauer at pengutronix.de  Mon Jun 21 03:11:48 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 21 Jun 2010 09:11:48 +0200
Subject: [PATCH 1/2] mxc: add common debug board for 3-stack platforms
In-Reply-To: <4C1B7D6A.4010301@gmail.com>
References: <1276352707-8199-1-git-send-email-jason77.wang@gmail.com>
	<1276352707-8199-2-git-send-email-jason77.wang@gmail.com>
	<20100616065540.GI20799@pengutronix.de>
	<4C1B7D6A.4010301@gmail.com>
Message-ID: <20100621071148.GF12115@pengutronix.de>

On Fri, Jun 18, 2010 at 10:06:34PM +0800, jason wrote:
> Sascha Hauer wrote:
>> On Sat, Jun 12, 2010 at 10:25:06PM +0800, Jason Wang wrote:
>>   
>>> The debug board is little different for all mxc 3-stack(PDK)
>>> platforms, it is possible here to add a common implementation to
>>> support this board.
>>>     
>>
>> Two small things left:
>>
>> Could you change the name cpld_debugboard.c to something like
>> 3ds_debugboard.c? That we are talking about the 3ds is much more
>> interesting than that there's a cpld on the board.
>>
>> Also, I really prefer having no extra header file for the debug board.
>> All information in this header file is only interesting in this single C
>> file.
>>
>> Sascha
>>
>>
>>   
> Hi Sascha,
>
> About the header file, most contents can be moved to c file,
> but there are two declarations:
>
> extern struct platform_device smsc_lan9217_device;

What do you need this one for?

> int __init mxc_expio_init(u32 base, u32 p_irq);

You'll definitely need this one of course.

>
> which will be used by board_mxNN_3ds.c, should i move them to mach/common.h and
> drop 3ds_debugboard.h or keep them in 3ds_debugboard.h?

Keep them in 3ds_debugboard.h. This way we can easily grep for all users
of the 3ds debug board code.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Mon Jun 21 03:19:31 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Mon, 21 Jun 2010 09:19:31 +0200
Subject: [PATCHv4 0/3] Driver for the i.MX2x CMOS Sensor Interface
In-Reply-To: <cover.1277096909.git.baruch@tkos.co.il>
References: <cover.1277096909.git.baruch@tkos.co.il>
Message-ID: <20100621071931.GG12115@pengutronix.de>

Hi Baruch,


> 
> Baruch Siach (3):
>   mx2_camera: Add soc_camera support for i.MX25/i.MX27
>   mx27: add support for the CSI device
>   mx25: add support for the CSI device

applied 2/3 and 3/3 for 2.6.36.

Sascha

> 
>  arch/arm/mach-mx2/clock_imx27.c          |    2 +-
>  arch/arm/mach-mx2/devices.c              |   31 +
>  arch/arm/mach-mx2/devices.h              |    1 +
>  arch/arm/mach-mx25/clock.c               |   14 +-
>  arch/arm/mach-mx25/devices.c             |   22 +
>  arch/arm/mach-mx25/devices.h             |    1 +
>  arch/arm/plat-mxc/include/mach/memory.h  |    4 +-
>  arch/arm/plat-mxc/include/mach/mx25.h    |    2 +
>  arch/arm/plat-mxc/include/mach/mx2_cam.h |   46 +
>  drivers/media/video/Kconfig              |   13 +
>  drivers/media/video/Makefile             |    1 +
>  drivers/media/video/mx2_camera.c         | 1493 ++++++++++++++++++++++++++++++
>  12 files changed, 1625 insertions(+), 5 deletions(-)
>  create mode 100644 arch/arm/plat-mxc/include/mach/mx2_cam.h
>  create mode 100644 drivers/media/video/mx2_camera.c
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From jeremy.kerr at canonical.com  Mon Jun 21 03:27:49 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Mon, 21 Jun 2010 15:27:49 +0800
Subject: [PATCH 1/2] [ARM] Introduce 'struct machine_class' for SoC level
	abstraction
In-Reply-To: <1277042450-30382-1-git-send-email-eric.miao@canonical.com>
References: <1277042450-30382-1-git-send-email-eric.miao@canonical.com>
Message-ID: <201006211527.49786.jeremy.kerr@canonical.com>

Hi Eric,

> For machine class (mostly equivalent to SoC) level abstraction.

Could you detail your intended usage of machine_class and how this will fit in 
with the mdesc? Will the mdesc fields override the machine_class fields, or is 
this intended to be a replacement?

Cheers,


Jeremy


From l.fu at pengutronix.de  Mon Jun 21 03:37:36 2010
From: l.fu at pengutronix.de (Luotao Fu)
Date: Mon, 21 Jun 2010 09:37:36 +0200
Subject: [PATCH] imxfb: add flag to avoid disabling clk multiple times
In-Reply-To: <4C1CE6B8.4090504@gmail.com>
References: <1275561288-20661-1-git-send-email-l.fu@pengutronix.de>
	<4C1CE6B8.4090504@gmail.com>
Message-ID: <20100621073736.GA24817@pengutronix.de>

Hi Martin,

On Sat, Jun 19, 2010 at 05:48:08PM +0200, Martin Fuzzey wrote:
> Hi Luotao,
> 
> Luotao Fu wrote:
> > while the imxfb driver blanks the screen. The clock supply to the framebuffer
> > controller is disabled. The same callback to disable the fb is, however, also
> > used the remove and shutdown hooks of the imxfb platform driver. This means that
> > the imxfb driver can run into a WARN in clock_disable while unloading or
> > rebooting, if the screen is blanked previously, since the same clock will be
> > than eventually disabled multiple times.  This patch adds a flag to make sure
> > that the clock will only be disabled, if it was not already disabled before.
> >
> >   
> Actually it's worse than that - you don't need to unload the
> driver or reboot to run into this problem because imxfb_blank()
> calls imxfb_disable_controller() for cases
>     case FB_BLANK_POWERDOWN:
>     case FB_BLANK_VSYNC_SUSPEND:
>     case FB_BLANK_HSYNC_SUSPEND:
>     case FB_BLANK_NORMAL:
> 
> Often an X server will call these after successive timeouts
> (eg Normal, Suspend, Powerdown) so you can get into the
> multiple suspend problem you describe just by waiting long
> enough for at least two blank levels to be activated.
> 
> Furthermore once this happens, not only does a WARN occur
> in clock_disable but the clock usage counter will actually become
> negative so it will require multiple wake up requests to switch
> the display back on.
> 
> I was just about to post a patch for this but I see you beat
> me to it :).
> 
> Your patch fixes the clock_disable problem but fbi->backlight_power()
> and fbi->lcd_power() can still be called multiple times.
> Not sure if that is really a problem - they should be idempotent.
> 

Multiple calling of the backlight_power and lcd_power function hooks
should be no trouble on most platforms since they mostly control some
PWM or GPIO lines, which won't complain to be turned on or off again.
Never the less I agree with you that this is quite unneccessary.

> I did it by making all of imxfb_disable_controller() do nothing if the
> disable was already done like this  (just for illustration not submission,
> lines may be mangled):
> 

This solution looks better and more clear than mine, which only concentrate
on clock. Only nitpickings: I'd probably defined "enabled" as a bool. Further
it might be nice to change pr_debug so that one would see a failed
enable/disable call. some like
pr_debug("Disabling LCD controller ... ");

if (!fbi->enabled) {
	pr_debug("already disabled\n");
	return;
} else
		pr_debug("\n");

Applied and tested on my board here. (consolefb only, no X running.)
so far:
Acked-by: Luotao Fu <l.fu at pengutronix.de>

 
thanks
and
cheers

Luotao Fu
-- 
Pengutronix e.K.                           | Dipl.-Ing. Luotao Fu        |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |
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From linus.walleij at stericsson.com  Mon Jun 21 03:54:01 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Mon, 21 Jun 2010 09:54:01 +0200
Subject: [PATCH 0/2] Common struct clk implementation, v5
In-Reply-To: <1277098513.947165.104554431018.0.gpush@pororo>
References: <1277098513.947165.104554431018.0.gpush@pororo>
Message-ID: <AANLkTikBESJzzQ87AzVg7ZBB3ygbWXK4aw3u0xSJSJi2@mail.gmail.com>

2010/6/21 Jeremy Kerr <jeremy.kerr at canonical.com>:

> Comments most welcome.

I think this is a step in the right direction, if it gets merged I will switch
the U300 over to it.


Yours,
Linus Walleij


From eric.y.miao at gmail.com  Mon Jun 21 04:23:22 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 16:23:22 +0800
Subject: [PATCH 1/2] [ARM] Introduce 'struct machine_class' for SoC level 
	abstraction
In-Reply-To: <201006211527.49786.jeremy.kerr@canonical.com>
References: <1277042450-30382-1-git-send-email-eric.miao@canonical.com> 
	<201006211527.49786.jeremy.kerr@canonical.com>
Message-ID: <AANLkTilUddhIW0C5LN4b7igh6vEDvelhnT8a3or677Zk@mail.gmail.com>

On Mon, Jun 21, 2010 at 3:27 PM, Jeremy Kerr <jeremy.kerr at canonical.com> wrote:
> Hi Eric,
>
>> For machine class (mostly equivalent to SoC) level abstraction.
>
> Could you detail your intended usage of machine_class and how this will fit in
> with the mdesc? Will the mdesc fields override the machine_class fields, or is
> this intended to be a replacement?
>

Good question, I've missed that part in the commit message. So my idea
is to have machine_class fields to replace machine_desc completely in
the end, but the situation is we need a smooth transition:

1. so for newly added machines with machine_class pointer, the fields in
machine_class will dominate (ignoring the fields in machine_desc)

2. for legacy machine_desc (apparently without machine_class pointer),
the fields within will be used, and these machines are not affected

So my intention of machine_class is really a class of machines, instead of
the class concept in C++. There might be useful situations for derivative,
E.g. some PXA machines have their specific map_io, mainstone:

static struct map_desc mainstone_io_desc[] __initdata = {
  	{	/* CPLD */
		.virtual	=  MST_FPGA_VIRT,
		.pfn		= __phys_to_pfn(MST_FPGA_PHYS),
		.length		= 0x00100000,
		.type		= MT_DEVICE
	}
};

static void __init mainstone_map_io(void)
{
	pxa_map_io();
	iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
}

So that from derivative POV, it can be expressed as:

	if (mdesc->class && mdesc->class->map_io)
		mdesc->class->map_io();
	if (mdesc->map_io())
		mdesc->map_io();

But this seems to make things a bit over complicated, so for such cases
I'd prefer:

1. have a separate machine_class for mainstone
2. or move the board specific map_io() separatedly


From linux at arm.linux.org.uk  Mon Jun 21 05:02:45 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 10:02:45 +0100
Subject: [PATCH 1/2] [ARM] Introduce 'struct machine_class' for SoC
	level abstraction
In-Reply-To: <AANLkTilUddhIW0C5LN4b7igh6vEDvelhnT8a3or677Zk@mail.gmail.com>
References: <1277042450-30382-1-git-send-email-eric.miao@canonical.com>
	<201006211527.49786.jeremy.kerr@canonical.com>
	<AANLkTilUddhIW0C5LN4b7igh6vEDvelhnT8a3or677Zk@mail.gmail.com>
Message-ID: <20100621090245.GA7702@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 04:23:22PM +0800, Eric Miao wrote:
> So that from derivative POV, it can be expressed as:
> 
> 	if (mdesc->class && mdesc->class->map_io)
> 		mdesc->class->map_io();
> 	if (mdesc->map_io())
> 		mdesc->map_io();
> 
> But this seems to make things a bit over complicated, so for such cases
> I'd prefer:
> 
> 1. have a separate machine_class for mainstone
> 2. or move the board specific map_io() separatedly

How about making the presence of mdesc->map_io override the class
version?

So if mainstone provides its own map_io() function, it is still
responsible (as is today) for calling the PXA specific map_io().
The same behaviour seems sensible to apply to the other class
functions as well - allow platforms to override the class
version, and leave the replacement platform function responsible
for calling the class if that's what it needs to do.


From eric.y.miao at gmail.com  Mon Jun 21 05:05:34 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 17:05:34 +0800
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>

On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
> This patch adds samsung keypad device definition for samsung cpus.
>
> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
> ?arch/arm/plat-samsung/Kconfig ? ? ? ? ? ? ? ? ? ?| ? ?5 ++
> ?arch/arm/plat-samsung/Makefile ? ? ? ? ? ? ? ? ? | ? ?1 +
> ?arch/arm/plat-samsung/dev-keypad.c ? ? ? ? ? ? ? | ? 58 +++++++++++++++++++++

Why need an individual file for a simple device?  In the end, these files
will flood over the plat-samsung/ directory. And now think this - in your
new SoC design ,the keypad IP is replaced with a completely new one, does
that mean a new dev-keypad-new1.c, dev-keypad-new2.c?

I personally prefer a single devices.c for all the devices, if you
orgnize well, shouldn't take up much code size in that single file.

> ?arch/arm/plat-samsung/include/plat/devs.h ? ? ? ?| ? ?2 +
> ?arch/arm/plat-samsung/include/plat/keypad.h ? ? ?| ? 59 ++++++++++++++++++++++
> ?arch/arm/plat-samsung/include/plat/regs-keypad.h | ? 49 ++++++++++++++++++

Will these registers be used elsewhere except within the keypad driver?
If no, they might be better moved to the keypad driver itself, it makes
the driver more self-contained and avoid the registers being accessed
anywhere.

> ?6 files changed, 174 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/arm/plat-samsung/dev-keypad.c
> ?create mode 100644 arch/arm/plat-samsung/include/plat/keypad.h
> ?create mode 100644 arch/arm/plat-samsung/include/plat/regs-keypad.h
>
> diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
> index 2753fb3..bd007e3 100644
> --- a/arch/arm/plat-samsung/Kconfig
> +++ b/arch/arm/plat-samsung/Kconfig
> @@ -227,6 +227,11 @@ config SAMSUNG_DEV_TS
> ? ? ? ?help
> ? ? ? ? ? ?Common in platform device definitions for touchscreen device
>
> +config SAMSUNG_DEV_KEYPAD
> + ? ? ? bool
> + ? ? ? help
> + ? ? ? ? Compile in platform device definitions for keypad
> +
> ?# DMA
>
> ?config S3C_DMA
> diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
> index b1d82cc..8269d80 100644
> --- a/arch/arm/plat-samsung/Makefile
> +++ b/arch/arm/plat-samsung/Makefile
> @@ -48,6 +48,7 @@ obj-$(CONFIG_S3C_DEV_RTC) ? ? += dev-rtc.o
>
> ?obj-$(CONFIG_SAMSUNG_DEV_ADC) ?+= dev-adc.o
> ?obj-$(CONFIG_SAMSUNG_DEV_TS) ? += dev-ts.o
> +obj-$(CONFIG_SAMSUNG_DEV_KEYPAD) ? ? ? += dev-keypad.o
>
> ?# DMA support
>
> diff --git a/arch/arm/plat-samsung/dev-keypad.c b/arch/arm/plat-samsung/dev-keypad.c
> new file mode 100644
> index 0000000..679b444
> --- /dev/null
> +++ b/arch/arm/plat-samsung/dev-keypad.c
> @@ -0,0 +1,58 @@
> +/*
> + * linux/arch/arm/plat-samsung/dev-keypad.c
> + *
> + * Copyright (C) 2010 Samsung Electronics Co.Ltd
> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
> + *
> + * ?This program is free software; you can redistribute ?it and/or modify it
> + * ?under ?the terms of ?the GNU General ?Public License as published by the
> + * ?Free Software Foundation; ?either version 2 of the ?License, or (at your
> + * ?option) any later version.
> + *
> + */
> +
> +#include <linux/platform_device.h>
> +#include <mach/irqs.h>
> +#include <mach/map.h>
> +#include <plat/cpu.h>
> +#include <plat/devs.h>
> +#include <plat/keypad.h>
> +
> +static struct resource samsung_keypad_resources[] = {
> + ? ? ? [0] = {
> + ? ? ? ? ? ? ? .start ?= SAMSUNG_PA_KEYPAD,
> + ? ? ? ? ? ? ? .end ? ?= SAMSUNG_PA_KEYPAD + 0x20 - 1,
> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_MEM,
> + ? ? ? },
> + ? ? ? [1] = {
> + ? ? ? ? ? ? ? .start ?= IRQ_KEYPAD,
> + ? ? ? ? ? ? ? .end ? ?= IRQ_KEYPAD,
> + ? ? ? ? ? ? ? .flags ?= IORESOURCE_IRQ,
> + ? ? ? },
> +};
> +
> +struct platform_device samsung_device_keypad = {
> + ? ? ? .name ? ? ? ? ? = "samsung-keypad",
> + ? ? ? .id ? ? ? ? ? ? = -1,
> + ? ? ? .num_resources ?= ARRAY_SIZE(samsung_keypad_resources),
> + ? ? ? .resource ? ? ? = samsung_keypad_resources,
> +};
> +
> +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
> +{
> + ? ? ? struct samsung_keypad_platdata *npd;
> +
> + ? ? ? if (!pd) {
> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no platform data\n", __func__);
> + ? ? ? ? ? ? ? return;
> + ? ? ? }
> +
> + ? ? ? npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
> + ? ? ? if (!npd)
> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no memory for platform data\n", __func__);

This part of the code is actually duplicated again and again and again
for each device, PXA and other legacy platforms are bad references for
this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
major points:

 1. A minimum 'struct pxa_device_desc' for a simple description of a
    device (more than 90% of the devices can be described that way),
    and avoid using a comparatively heavier weight platform_device,
    which can be generated at run-time

 2. pxa_register_device() to allocate and register the platform_device
    at run-time, along with the platform data

 3. pxa168_add_*() as a consistent/clearly named API, and with type
    checking for the platform_data type (it's a bit difficult to check
    type in pxa_register_device())

Just for your reference.

> +
> + ? ? ? if (!npd->cfg_gpio)
> + ? ? ? ? ? ? ? npd->cfg_gpio = samsung_keypad_cfg_gpio;

More and more platforms are moving their IO-mux to a static descriptive
array and have some API to configure. E.g. PXA, Orion/Kirkwood, iMX....
The idea basically is:

  1) IO-Mux and the internal peripheral controller are conceptually
     separate entities (the extreme case is the internal peripheral
     controller can function normally even without IO-mux being setup
     correct, only that signals not proplery routed in/out)

  2) IO-mux should be configured before the peripheral drivers are
     ready to go (there are cases that IO-mux will have to be changed
     at run-time, so IO-mux API should be able to handle that, though
     such cases are rare)

  3) Peripheral drivers should not be concerned with IO-mux config

Not sure though how the IO-mux is designed in S5P, so treat the above
as reference only.

> +
> + ? ? ? samsung_device_keypad.dev.platform_data = npd;
> +}
> diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
> index e6144e4..6d9f01b 100644
> --- a/arch/arm/plat-samsung/include/plat/devs.h
> +++ b/arch/arm/plat-samsung/include/plat/devs.h
> @@ -100,6 +100,8 @@ extern struct platform_device s5pc100_device_iis0;
> ?extern struct platform_device s5pc100_device_iis1;
> ?extern struct platform_device s5pc100_device_iis2;
>
> +extern struct platform_device samsung_device_keypad;
> +
> ?/* s3c2440 specific devices */
>
> ?#ifdef CONFIG_CPU_S3C2440
> diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/plat-samsung/include/plat/keypad.h
> new file mode 100644
> index 0000000..6d139d6
> --- /dev/null
> +++ b/arch/arm/plat-samsung/include/plat/keypad.h
> @@ -0,0 +1,59 @@
> +/*
> + * linux/arch/arm/plat-samsung/include/plat/keypad.h
> + *
> + * Copyright (C) 2010 Samsung Electronics Co.Ltd
> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
> + *
> + * Samsung Platform - Keypad platform data definitions
> + *
> + * ?This program is free software; you can redistribute ?it and/or modify it
> + * ?under ?the terms of ?the GNU General ?Public License as published by the
> + * ?Free Software Foundation; ?either version 2 of the ?License, or (at your
> + * ?option) any later version.
> + *
> + */
> +
> +#ifndef __PLAT_SAMSUNG_KEYPAD_H
> +#define __PLAT_SAMSUNG_KEYPAD_H
> +
> +#include <linux/input/matrix_keypad.h>
> +
> +#define SAMSUNG_MAX_ROWS ? ? ? 8
> +#define SAMSUNG_MAX_COLS ? ? ? 8
> +
> +/**
> + * struct samsung_keypad_platdata - Platform device data for Samsung Keypad.
> + * @keymap_data: pointer to &matrix_keymap_data.
> + * @rows: number of keypad row supported.
> + * @cols: number of keypad col supported.
> + * @no_autorepeat: disable key autorepeat.
> + * @wakeup: controls whether the device should be set up as wakeup source.
> + * @cfg_gpio: configure the GPIO.
> + *
> + * Initialisation data specific to either the machine or the platform
> + * for the device driver to use or call-back when configuring gpio.
> + */
> +struct samsung_keypad_platdata {
> + ? ? ? const struct matrix_keymap_data *keymap_data;
> + ? ? ? unsigned int ? ? ? ? ? ?rows;
> + ? ? ? unsigned int ? ? ? ? ? ?cols;
> + ? ? ? bool ? ? ? ? ? ? ? ? ? ?no_autorepeat;
> + ? ? ? bool ? ? ? ? ? ? ? ? ? ?wakeup;
> +
> + ? ? ? void ? ?(*cfg_gpio)(unsigned int rows, unsigned int cols);
> +};

Why are you calling everything samsung_this, samsung_that? Now think about:

  1. Is this keypad applicable to all Samsung silicon?
  2. Samsung has a new IP for the keypad, now what? samsung_new_keypad_platdata?

s5p_keypad sounds more reasable to me if it's applicable to all the s5p
series. Now I also doubt that's the case. So normally, we will name it
after the first silicon where this IP appears, e.g.

  s5pc100_keypad

and now in s5pc200 code, you can also register/re-use the s5pc100_keypad
device/driver, and everyone knows - OK, the IP on S5PC100 is now re-used
here.

> +
> +/**
> + * samsung_keypad_set_platdata - Set platform data for Samsung Keypad device.
> + * @pd: Platform data to register to device.
> + *
> + * Register the given platform data for use with Samsung Keypad device.
> + * The call will copy the platform data, so the board definitions can
> + * make the structure itself __initdata.
> + */
> +extern void samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd);
> +
> +/* defined by architecture to configure gpio. */
> +extern void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols);
> +
> +#endif /* __PLAT_SAMSUNG_KEYPAD_H */
> diff --git a/arch/arm/plat-samsung/include/plat/regs-keypad.h b/arch/arm/plat-samsung/include/plat/regs-keypad.h
> new file mode 100644
> index 0000000..e4688f0
> --- /dev/null
> +++ b/arch/arm/plat-samsung/include/plat/regs-keypad.h
> @@ -0,0 +1,49 @@
> +/*
> + * linux/arch/arm/plat-samsung/include/plat/regs-keypad.h
> + *
> + * Copyright (C) 2010 Samsung Electronics Co.Ltd
> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
> + *
> + * ?This program is free software; you can redistribute ?it and/or modify it
> + * ?under ?the terms of ?the GNU General ?Public License as published by the
> + * ?Free Software Foundation; ?either version 2 of the ?License, or (at your
> + * ?option) any later version.
> + *
> + */
> +
> +#ifndef __SAMSUNG_KEYPAD_H__
> +#define __SAMSUNG_KEYPAD_H__
> +
> +#define SAMSUNG_KEYIFCON ? ? ? ? ? ? ? ? ? ? ? 0x00
> +#define SAMSUNG_KEYIFSTSCLR ? ? ? ? ? ? ? ? ? ?0x04
> +#define SAMSUNG_KEYIFCOL ? ? ? ? ? ? ? ? ? ? ? 0x08
> +#define SAMSUNG_KEYIFROW ? ? ? ? ? ? ? ? ? ? ? 0x0c
> +#define SAMSUNG_KEYIFFC ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?0x10
> +
> +/* SAMSUNG_KEYIFCON */
> +#define SAMSUNG_KEYIFCON_INT_F_EN ? ? ? ? ? ? ?(1 << 0)
> +#define SAMSUNG_KEYIFCON_INT_R_EN ? ? ? ? ? ? ?(1 << 1)
> +#define SAMSUNG_KEYIFCON_DF_EN ? ? ? ? ? ? ? ? (1 << 2)
> +#define SAMSUNG_KEYIFCON_FC_EN ? ? ? ? ? ? ? ? (1 << 3)
> +#define SAMSUNG_KEYIFCON_WAKEUPEN ? ? ? ? ? ? ?(1 << 4)
> +
> +/* SAMSUNG_KEYIFSTSCLR */
> +#define SAMSUNG_KEYIFSTSCLR_P_INT_MASK ? ? ? ? (0xff << 0)
> +#define SAMSUNG_KEYIFSTSCLR_R_INT_MASK ? ? ? ? (0xff << 8)
> +#define SAMSUNG_KEYIFSTSCLR_R_INT_OFFSET ? ? ? 8
> +#define S5PV210_KEYIFSTSCLR_P_INT_MASK ? ? ? ? (0x3fff << 0)
> +#define S5PV210_KEYIFSTSCLR_R_INT_MASK ? ? ? ? (0x3fff << 16)
> +#define S5PV210_KEYIFSTSCLR_R_INT_OFFSET ? ? ? 16
> +
> +/* SAMSUNG_KEYIFCOL */
> +#define SAMSUNG_KEYIFCOL_MASK ? ? ? ? ? ? ? ? ?(0xff << 0)
> +#define S5PV210_KEYIFCOLEN_MASK ? ? ? ? ? ? ? ? ? ? ? ?(0xff << 8)
> +
> +/* SAMSUNG_KEYIFROW */
> +#define SAMSUNG_KEYIFROW_MASK ? ? ? ? ? ? ? ? ?(0xff << 0)
> +#define S5PV210_KEYIFROW_MASK ? ? ? ? ? ? ? ? ?(0x3fff << 0)
> +
> +/* SAMSUNG_KEYIFFC */
> +#define SAMSUNG_KEYIFFC_MASK ? ? ? ? ? ? ? ? ? (0x3ff << 0)
> +
> +#endif /* __SAMSUNG_KEYPAD_H__ */
> --
> 1.7.0.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From catalin.marinas at arm.com  Mon Jun 21 05:13:25 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:13:25 +0100
Subject: [PATCH v3 0/7] Patches/fixes for 2.6.35
Message-ID: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>

Hi,

Just reposting these patches as they contain some bug-fixes and should
get in before 2.6.35 is released.

>From my previous posts, I removed the PL310 lock optimisation patch
(there are some discussions on optimising the range operations for large
memory blocks and these would be faster as background All operations).

If there are no further comments to these patches, I'll send them to the
patch system.

Thanks.


Catalin Marinas (7):
      ARM: Align machine_desc.phys_io to a 1MB section
      ARM: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds
      ARM: The v6_dma_inv_range() function must preserve data on SMP
      ARM: Add a config option for the ARM11MPCore DMA cache maintenance workaround
      ARM: Add support for the MOVW/MOVT relocations in Thumb-2
      ARM: Remove dummy loads from the original relocation address
      ARM: Do not compile the Thumb-2 module relocations on an ARM kernel


 arch/arm/include/asm/elf.h |    2 ++
 arch/arm/kernel/head.S     |    2 ++
 arch/arm/kernel/module.c   |   34 ++++++++++++++++++++++++++++++++++
 arch/arm/mm/Kconfig        |   19 +++++++++++++++++++
 arch/arm/mm/cache-v6.S     |   18 ++++++++++++++----
 arch/arm/mm/dma-mapping.c  |    2 ++
 6 files changed, 73 insertions(+), 4 deletions(-)

-- 
Catalin


From catalin.marinas at arm.com  Mon Jun 21 05:13:31 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:13:31 +0100
Subject: [PATCH v3 1/7] ARM: Align machine_desc.phys_io to a 1MB section
In-Reply-To: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621091331.22752.73990.stgit@e102109-lin.cambridge.arm.com>

Platforms like RealView don't pass a section-aligned pointer via the
machine_desc structure. This patch aligns the pointer in the
__create_page_tables function. Reported by Tony Thompson.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/kernel/head.S |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..82ea924 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -302,6 +302,8 @@ __create_page_tables:
 	movhi	r3, #0x0800
 	add	r6, r0, r3
 	ldr	r3, [r8, #MACHINFO_PHYSIO]
+	mov	r3, r3, lsr #20			@ 1MB-aligned address
+	mov	r3, r3, lsl #20
 	orr	r3, r3, r7
 1:	str	r3, [r0], #4
 	add	r3, r3, #1 << 20



From catalin.marinas at arm.com  Mon Jun 21 05:13:36 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:13:36 +0100
Subject: [PATCH v3 2/7] ARM: Avoid the CONSISTENT_DMA_SIZE warning on noMMU
	builds
In-Reply-To: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621091336.22752.78477.stgit@e102109-lin.cambridge.arm.com>

This macro is not defined when !CONFIG_MMU.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/mm/dma-mapping.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 13fa536..c4de90f 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -25,6 +25,7 @@
 #include <asm/sizes.h>
 
 /* Sanity check size */
+#ifdef CONFIG_MMU
 #if (CONSISTENT_DMA_SIZE % SZ_2M)
 #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
 #endif
@@ -32,6 +33,7 @@
 #define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
 #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
 #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
+#endif
 
 static u64 get_coherent_dma_mask(struct device *dev)
 {



From catalin.marinas at arm.com  Mon Jun 21 05:13:42 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:13:42 +0100
Subject: [PATCH v3 3/7] ARM: The v6_dma_inv_range() function must preserve
	data on SMP
In-Reply-To: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621091342.22752.83707.stgit@e102109-lin.cambridge.arm.com>

A recent patch for DMA cache maintenance on ARM11MPCore added a write
for ownership trick to the v6_dma_inv_range() function. Such operation
destroys data already present in the buffer. However, this function is
used with with dma_sync_single_for_device() which is supposed to
preserve the existing data transfered into the buffer. This patch adds a
combination of read/write for ownership to preserve the original data.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Reported-by: Ronen Shitrit <rshitrit at marvell.com>
---
 arch/arm/mm/cache-v6.S |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index e46ecd8..332b48c 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -212,7 +212,8 @@ v6_dma_inv_range:
 #endif
 1:
 #ifdef CONFIG_SMP
-	str	r0, [r0]			@ write for ownership
+	ldr	r2, [r0]			@ read for ownership
+	str	r2, [r0]			@ write for ownership
 #endif
 #ifdef HARVARD_CACHE
 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D line



From catalin.marinas at arm.com  Mon Jun 21 05:13:48 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:13:48 +0100
Subject: [PATCH v3 4/7] ARM: Add a config option for the ARM11MPCore DMA
	cache maintenance workaround
In-Reply-To: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621091348.22752.90443.stgit@e102109-lin.cambridge.arm.com>

Commit f4d6477f introduced a workaround for the lack of hardware
broadcasting of the cache maintenance operations on ARM11MPCore.
However, the workaround is only valid on CPUs that do not do speculative
loads into the D-cache.

This patch adds a Kconfig option with the corresponding help to make the
above clear. When the DMA_CACHE_RWFO option is disabled, the kernel
behaviour is that prior to the f4d6477f commit. This also allows ARMv6
UP processors with speculative loads to work correctly.

For other processors, a different workaround may be needed.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Ronen Shitrit <rshitrit at marvell.com>
---
 arch/arm/mm/Kconfig    |   19 +++++++++++++++++++
 arch/arm/mm/cache-v6.S |   15 ++++++++++++---
 2 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..fc1b2fa 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -735,6 +735,25 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
 	  Forget about fast user space cmpxchg support.
 	  It is just not possible.
 
+config DMA_CACHE_RWFO
+	bool "Enable read/write for ownership DMA cache maintenance"
+	depends on CPU_V6 && SMP
+	default y
+	help
+	  The Snoop Control Unit on ARM11MPCore does not detect the
+	  cache maintenance operations and the dma_{map,unmap}_area()
+	  functions may leave stale cache entries on other CPUs. By
+	  enabling this option, Read or Write For Ownership in the ARMv6
+	  DMA cache maintenance functions is performed. These LDR/STR
+	  instructions change the cache line state to shared or modified
+	  so that the cache operation has the desired effect.
+
+	  Note that the workaround is only valid on processors that do
+	  not perform speculative loads into the D-cache. For such
+	  processors, if cache maintenance operations are not broadcast
+	  in hardware, other workarounds are needed (e.g. cache
+	  maintenance broadcasting in software via FIQ).
+
 config OUTER_CACHE
 	bool
 
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 332b48c..86aa689 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -211,7 +211,7 @@ v6_dma_inv_range:
 	mcrne	p15, 0, r1, c7, c15, 1		@ clean & invalidate unified line
 #endif
 1:
-#ifdef CONFIG_SMP
+#ifdef CONFIG_DMA_CACHE_RWFO
 	ldr	r2, [r0]			@ read for ownership
 	str	r2, [r0]			@ write for ownership
 #endif
@@ -235,7 +235,7 @@ v6_dma_inv_range:
 v6_dma_clean_range:
 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
-#ifdef CONFIG_SMP
+#ifdef CONFIG_DMA_CACHE_RWFO
 	ldr	r2, [r0]			@ read for ownership
 #endif
 #ifdef HARVARD_CACHE
@@ -258,7 +258,7 @@ v6_dma_clean_range:
 ENTRY(v6_dma_flush_range)
 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
-#ifdef CONFIG_SMP
+#ifdef CONFIG_DMA_CACHE_RWFO
 	ldr	r2, [r0]			@ read for ownership
 	str	r2, [r0]			@ write for ownership
 #endif
@@ -284,9 +284,13 @@ ENTRY(v6_dma_map_area)
 	add	r1, r1, r0
 	teq	r2, #DMA_FROM_DEVICE
 	beq	v6_dma_inv_range
+#ifndef CONFIG_DMA_CACHE_RWFO
+	b	v6_dma_clean_range
+#else
 	teq	r2, #DMA_TO_DEVICE
 	beq	v6_dma_clean_range
 	b	v6_dma_flush_range
+#endif
 ENDPROC(v6_dma_map_area)
 
 /*
@@ -296,6 +300,11 @@ ENDPROC(v6_dma_map_area)
  *	- dir	- DMA direction
  */
 ENTRY(v6_dma_unmap_area)
+#ifndef CONFIG_DMA_CACHE_RWFO
+	add	r1, r1, r0
+	teq	r2, #DMA_TO_DEVICE
+	bne	v6_dma_inv_range
+#endif
 	mov	pc, lr
 ENDPROC(v6_dma_unmap_area)
 



From catalin.marinas at arm.com  Mon Jun 21 05:13:53 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:13:53 +0100
Subject: [PATCH v3 5/7] ARM: Add support for the MOVW/MOVT relocations in
	Thumb-2
In-Reply-To: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621091353.22752.57015.stgit@e102109-lin.cambridge.arm.com>

The patch adds handling case for the R_ARM_THM_MOVW_ABS_NC and
R_ARM_THM_MOVT_ABS relocations in arch/arm/kernel/module.c. Such
relocations may appear in Thumb-2 compiled kernel modules.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Reported-by: Kyungmin Park <kmpark at infradead.org>
---
 arch/arm/include/asm/elf.h |    2 ++
 arch/arm/kernel/module.c   |   32 ++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 51662fe..4d0e730 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -59,6 +59,8 @@ typedef struct user_fp elf_fpregset_t;
 
 #define R_ARM_THM_CALL		10
 #define R_ARM_THM_JUMP24	30
+#define R_ARM_THM_MOVW_ABS_NC	47
+#define R_ARM_THM_MOVT_ABS	48
 
 /*
  * These are used to set parameters in the core dumps.
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index c628bdf..ae3c804 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -237,6 +237,38 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 			lower = *(u16 *)(loc + 2);
 			break;
 
+		case R_ARM_THM_MOVW_ABS_NC:
+		case R_ARM_THM_MOVT_ABS:
+			upper = *(u16 *)loc;
+			lower = *(u16 *)(loc + 2);
+
+			/*
+			 * MOVT/MOVW instructions encoding in Thumb-2:
+			 *
+			 * i	= upper[10]
+			 * imm4	= upper[3:0]
+			 * imm3	= lower[14:12]
+			 * imm8	= lower[7:0]
+			 *
+			 * imm16 = imm4:i:imm3:imm8
+			 */
+			offset = ((upper & 0x000f) << 12) |
+				((upper & 0x0400) << 1) |
+				((lower & 0x7000) >> 4) | (lower & 0x00ff);
+			offset = (offset ^ 0x8000) - 0x8000;
+			offset += sym->st_value;
+
+			if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS)
+				offset >>= 16;
+
+			*(u16 *)loc = (u16)((upper & 0xfbf0) |
+					    ((offset & 0xf000) >> 12) |
+					    ((offset & 0x0800) >> 1));
+			*(u16 *)(loc + 2) = (u16)((lower & 0x8f00) |
+						  ((offset & 0x0700) << 4) |
+						  (offset & 0x00ff));
+			break;
+
 		default:
 			printk(KERN_ERR "%s: unknown relocation: %u\n",
 			       module->name, ELF32_R_TYPE(rel->r_info));



From catalin.marinas at arm.com  Mon Jun 21 05:13:59 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:13:59 +0100
Subject: [PATCH v3 6/7] ARM: Remove dummy loads from the original relocation
	address
In-Reply-To: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621091359.22752.31023.stgit@e102109-lin.cambridge.arm.com>

Reading back the upper and lower values in the R_ARM_THM_CALL and
R_ARM_THM_JUMP24 case was introduced by a previous commit but they are
not needed.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/kernel/module.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index ae3c804..aab7fca 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -233,8 +233,6 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 			*(u16 *)(loc + 2) = (u16)((lower & 0xd000) |
 						  (j1 << 13) | (j2 << 11) |
 						  ((offset >> 1) & 0x07ff));
-			upper = *(u16 *)loc;
-			lower = *(u16 *)(loc + 2);
 			break;
 
 		case R_ARM_THM_MOVW_ABS_NC:



From catalin.marinas at arm.com  Mon Jun 21 05:14:04 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:14:04 +0100
Subject: [PATCH v3 7/7] ARM: Do not compile the Thumb-2 module relocations
	on an ARM kernel
In-Reply-To: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621091404.22752.10456.stgit@e102109-lin.cambridge.arm.com>

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/kernel/module.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index aab7fca..6b46058 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -102,7 +102,9 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 		unsigned long loc;
 		Elf32_Sym *sym;
 		s32 offset;
+#ifdef CONFIG_THUMB2_KERNEL
 		u32 upper, lower, sign, j1, j2;
+#endif
 
 		offset = ELF32_R_SYM(rel->r_info);
 		if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) {
@@ -185,6 +187,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 					(offset & 0x0fff);
 			break;
 
+#ifdef CONFIG_THUMB2_KERNEL
 		case R_ARM_THM_CALL:
 		case R_ARM_THM_JUMP24:
 			upper = *(u16 *)loc;
@@ -266,6 +269,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 						  ((offset & 0x0700) << 4) |
 						  (offset & 0x00ff));
 			break;
+#endif
 
 		default:
 			printk(KERN_ERR "%s: unknown relocation: %u\n",



From catalin.marinas at arm.com  Mon Jun 21 05:20:17 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:20:17 +0100
Subject: [PATCH v3 0/4] Patches for -next
Message-ID: <20100621091745.23136.67979.stgit@e102109-lin.cambridge.arm.com>

Just reposting these patches, no changes other than rebasing them on
2.6.35-rc3.

I would like to push them to the -next tree and aim to merge them in
2.6.37-rc1 (two merging windows from now).

Please let me know if there are any objections.

Thanks.


Catalin Marinas (4):
      ARM: Remove the domain switching on ARMv6k/v7 CPUs
      ARM: Use lazy cache flushing on ARMv7 SMP systems
      ARM: Assume new page cache pages have dirty D-cache
      ARM: Synchronise the I and D caches via set_pte_at() on SMP systems


 arch/arm/include/asm/assembler.h  |   13 +++---
 arch/arm/include/asm/cacheflush.h |    6 +--
 arch/arm/include/asm/domain.h     |   31 +++++++++++++-
 arch/arm/include/asm/futex.h      |    9 ++--
 arch/arm/include/asm/pgtable.h    |   25 ++++++++++-
 arch/arm/include/asm/smp_plat.h   |    4 ++
 arch/arm/include/asm/tlbflush.h   |   12 ++++-
 arch/arm/include/asm/traps.h      |    2 +
 arch/arm/include/asm/uaccess.h    |   16 ++++---
 arch/arm/kernel/entry-armv.S      |    4 +-
 arch/arm/kernel/fiq.c             |    5 ++
 arch/arm/kernel/traps.c           |   14 ++++--
 arch/arm/lib/getuser.S            |   13 +++---
 arch/arm/lib/putuser.S            |   29 +++++++------
 arch/arm/lib/uaccess.S            |   83 +++++++++++++++++++------------------
 arch/arm/mm/Kconfig               |    8 ++++
 arch/arm/mm/copypage-v4mc.c       |    2 -
 arch/arm/mm/copypage-v6.c         |    2 -
 arch/arm/mm/copypage-xscale.c     |    2 -
 arch/arm/mm/dma-mapping.c         |    6 +++
 arch/arm/mm/fault-armv.c          |    8 ++--
 arch/arm/mm/flush.c               |   31 +++++++++-----
 arch/arm/mm/mmu.c                 |    6 +--
 arch/arm/mm/proc-macros.S         |    7 +++
 arch/arm/mm/proc-v7.S             |    5 +-
 25 files changed, 226 insertions(+), 117 deletions(-)

-- 
Catalin


From catalin.marinas at arm.com  Mon Jun 21 05:20:23 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:20:23 +0100
Subject: [PATCH v3 1/4] ARM: Remove the domain switching on ARMv6k/v7 CPUs
In-Reply-To: <20100621091745.23136.67979.stgit@e102109-lin.cambridge.arm.com>
References: <20100621091745.23136.67979.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621092023.23136.39581.stgit@e102109-lin.cambridge.arm.com>

This patch removes the domain switching functionality via the set_fs and
__switch_to functions on cores that have a TLS register.

Currently, the ioremap and vmalloc areas share the same level 1 page
tables and therefore have the same domain (DOMAIN_KERNEL). When the
kernel domain is modified from Client to Manager (via the __set_fs or in
the __switch_to function), the XN (eXecute Never) bit is overridden and
newer CPUs can speculatively prefetch the ioremap'ed memory.

Linux performs the kernel domain switching to allow user-specific
functions (copy_to/from_user, get/put_user etc.) to access kernel
memory. In order for these functions to work with the kernel domain set
to Client, the patch modifies the LDRT/STRT and related instructions to
the LDR/STR ones.

The user pages access rights are also modified for kernel read-only
access rather than read/write so that the copy-on-write mechanism still
works. CPU_USE_DOMAINS gets disabled only if HAS_TLS_REG is defined
since writing the TLS value to the high vectors page isn't possible.

The user addresses passed to the kernel are checked by the access_ok()
function so that they do not point to the kernel space.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/assembler.h |   13 +++---
 arch/arm/include/asm/domain.h    |   31 +++++++++++++-
 arch/arm/include/asm/futex.h     |    9 ++--
 arch/arm/include/asm/traps.h     |    2 +
 arch/arm/include/asm/uaccess.h   |   16 ++++---
 arch/arm/kernel/entry-armv.S     |    4 +-
 arch/arm/kernel/fiq.c            |    5 ++
 arch/arm/kernel/traps.c          |   14 +++++-
 arch/arm/lib/getuser.S           |   13 +++---
 arch/arm/lib/putuser.S           |   29 +++++++------
 arch/arm/lib/uaccess.S           |   83 +++++++++++++++++++-------------------
 arch/arm/mm/Kconfig              |    8 ++++
 arch/arm/mm/mmu.c                |    6 +--
 arch/arm/mm/proc-macros.S        |    7 +++
 arch/arm/mm/proc-v7.S            |    5 +-
 15 files changed, 153 insertions(+), 92 deletions(-)

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..66db132 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -18,6 +18,7 @@
 #endif
 
 #include <asm/ptrace.h>
+#include <asm/domain.h>
 
 /*
  * Endian independent macros for shifting bytes within registers.
@@ -183,12 +184,12 @@
  */
 #ifdef CONFIG_THUMB2_KERNEL
 
-	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort
+	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T()
 9999:
 	.if	\inc == 1
-	\instr\cond\()bt \reg, [\ptr, #\off]
+	\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
 	.elseif	\inc == 4
-	\instr\cond\()t \reg, [\ptr, #\off]
+	\instr\cond\()\t\().w \reg, [\ptr, #\off]
 	.else
 	.error	"Unsupported inc macro argument"
 	.endif
@@ -223,13 +224,13 @@
 
 #else	/* !CONFIG_THUMB2_KERNEL */
 
-	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort
+	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort, t=T()
 	.rept	\rept
 9999:
 	.if	\inc == 1
-	\instr\cond\()bt \reg, [\ptr], #\inc
+	\instr\cond\()b\()\t \reg, [\ptr], #\inc
 	.elseif	\inc == 4
-	\instr\cond\()t \reg, [\ptr], #\inc
+	\instr\cond\()\t \reg, [\ptr], #\inc
 	.else
 	.error	"Unsupported inc macro argument"
 	.endif
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
index cc7ef40..af18cea 100644
--- a/arch/arm/include/asm/domain.h
+++ b/arch/arm/include/asm/domain.h
@@ -45,13 +45,17 @@
  */
 #define DOMAIN_NOACCESS	0
 #define DOMAIN_CLIENT	1
+#ifdef CONFIG_CPU_USE_DOMAINS
 #define DOMAIN_MANAGER	3
+#else
+#define DOMAIN_MANAGER	1
+#endif
 
 #define domain_val(dom,type)	((type) << (2*(dom)))
 
 #ifndef __ASSEMBLY__
 
-#ifdef CONFIG_MMU
+#ifdef CONFIG_CPU_USE_DOMAINS
 #define set_domain(x)					\
 	do {						\
 	__asm__ __volatile__(				\
@@ -74,5 +78,28 @@
 #define modify_domain(dom,type)	do { } while (0)
 #endif
 
+/*
+ * Generate the T (user) versions of the LDR/STR and related
+ * instructions (inline assembly)
+ */
+#ifdef CONFIG_CPU_USE_DOMAINS
+#define T(instr)	#instr "t"
+#else
+#define T(instr)	#instr
 #endif
-#endif /* !__ASSEMBLY__ */
+
+#else /* __ASSEMBLY__ */
+
+/*
+ * Generate the T (user) versions of the LDR/STR and related
+ * instructions
+ */
+#ifdef CONFIG_CPU_USE_DOMAINS
+#define T(instr)	instr ## t
+#else
+#define T(instr)	instr
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* !__ASM_PROC_DOMAIN_H */
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 540a044..b33fe70 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -13,12 +13,13 @@
 #include <linux/preempt.h>
 #include <linux/uaccess.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)	\
 	__asm__ __volatile__(					\
-	"1:	ldrt	%1, [%2]\n"				\
+	"1:	" T(ldr) "	%1, [%2]\n"			\
 	"	" insn "\n"					\
-	"2:	strt	%0, [%2]\n"				\
+	"2:	" T(str) "	%0, [%2]\n"			\
 	"	mov	%0, #0\n"				\
 	"3:\n"							\
 	"	.pushsection __ex_table,\"a\"\n"		\
@@ -97,10 +98,10 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
 	pagefault_disable();	/* implies preempt_disable() */
 
 	__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
-	"1:	ldrt	%0, [%3]\n"
+	"1:	" T(ldr) "	%0, [%3]\n"
 	"	teq	%0, %1\n"
 	"	it	eq	@ explicit IT needed for the 2b label\n"
-	"2:	streqt	%2, [%3]\n"
+	"2:	" T(streq) "	%2, [%3]\n"
 	"3:\n"
 	"	.pushsection __ex_table,\"a\"\n"
 	"	.align	3\n"
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h
index 491960b..af5d5d1 100644
--- a/arch/arm/include/asm/traps.h
+++ b/arch/arm/include/asm/traps.h
@@ -27,4 +27,6 @@ static inline int in_exception_text(unsigned long ptr)
 extern void __init early_trap_init(void);
 extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame);
 
+extern void *vectors_page;
+
 #endif
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 33e4a48..b293616 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -227,7 +227,7 @@ do {									\
 
 #define __get_user_asm_byte(x,addr,err)				\
 	__asm__ __volatile__(					\
-	"1:	ldrbt	%1,[%2]\n"				\
+	"1:	" T(ldrb) "	%1,[%2],#0\n"			\
 	"2:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
@@ -263,7 +263,7 @@ do {									\
 
 #define __get_user_asm_word(x,addr,err)				\
 	__asm__ __volatile__(					\
-	"1:	ldrt	%1,[%2]\n"				\
+	"1:	" T(ldr) "	%1,[%2],#0\n"			\
 	"2:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
@@ -308,7 +308,7 @@ do {									\
 
 #define __put_user_asm_byte(x,__pu_addr,err)			\
 	__asm__ __volatile__(					\
-	"1:	strbt	%1,[%2]\n"				\
+	"1:	" T(strb) "	%1,[%2],#0\n"			\
 	"2:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
@@ -341,7 +341,7 @@ do {									\
 
 #define __put_user_asm_word(x,__pu_addr,err)			\
 	__asm__ __volatile__(					\
-	"1:	strt	%1,[%2]\n"				\
+	"1:	" T(str) "	%1,[%2],#0\n"			\
 	"2:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
@@ -366,10 +366,10 @@ do {									\
 
 #define __put_user_asm_dword(x,__pu_addr,err)			\
 	__asm__ __volatile__(					\
- ARM(	"1:	strt	" __reg_oper1 ", [%1], #4\n"	)	\
- ARM(	"2:	strt	" __reg_oper0 ", [%1]\n"	)	\
- THUMB(	"1:	strt	" __reg_oper1 ", [%1]\n"	)	\
- THUMB(	"2:	strt	" __reg_oper0 ", [%1, #4]\n"	)	\
+ ARM(	"1:	" T(str) "	" __reg_oper1 ", [%1], #4\n"	)	\
+ ARM(	"2:	" T(str) "	" __reg_oper0 ", [%1]\n"	)	\
+ THUMB(	"1:	" T(str) "	" __reg_oper1 ", [%1]\n"	)	\
+ THUMB(	"2:	" T(str) "	" __reg_oper0 ", [%1, #4]\n"	)	\
 	"3:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 7ee48e7..ba654fa 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -736,7 +736,7 @@ ENTRY(__switch_to)
  THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
  THUMB(	str	sp, [ip], #4		   )
  THUMB(	str	lr, [ip], #4		   )
-#ifdef CONFIG_MMU
+#ifdef CONFIG_CPU_USE_DOMAINS
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
 #if defined(CONFIG_HAS_TLS_REG)
@@ -745,7 +745,7 @@ ENTRY(__switch_to)
 	mov	r4, #0xffff0fff
 	str	r3, [r4, #-15]			@ TLS val at 0xffff0ff0
 #endif
-#ifdef CONFIG_MMU
+#ifdef CONFIG_CPU_USE_DOMAINS
 	mcr	p15, 0, r6, c3, c0, 0		@ Set domain register
 #endif
 	mov	r5, r0
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 6ff7919..d601ef2 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -45,6 +45,7 @@
 #include <asm/fiq.h>
 #include <asm/irq.h>
 #include <asm/system.h>
+#include <asm/traps.h>
 
 static unsigned long no_fiq_insn;
 
@@ -77,7 +78,11 @@ int show_fiq_list(struct seq_file *p, void *v)
 
 void set_fiq_handler(void *start, unsigned int length)
 {
+#if defined(CONFIG_CPU_USE_DOMAINS)
 	memcpy((void *)0xffff001c, start, length);
+#else
+	memcpy(vectors_page + 0x1c, start, length);
+#endif
 	flush_icache_range(0xffff001c, 0xffff001c + length);
 	if (!vectors_high())
 		flush_icache_range(0x1c, 0x1c + length);
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1621e53..6bc57c5 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -36,6 +36,8 @@
 
 static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" };
 
+void *vectors_page;
+
 #ifdef CONFIG_DEBUG_USER
 unsigned int user_debug;
 
@@ -745,7 +747,11 @@ void __init trap_init(void)
 
 void __init early_trap_init(void)
 {
+#if defined(CONFIG_CPU_USE_DOMAINS)
 	unsigned long vectors = CONFIG_VECTORS_BASE;
+#else
+	unsigned long vectors = (unsigned long)vectors_page;
+#endif
 	extern char __stubs_start[], __stubs_end[];
 	extern char __vectors_start[], __vectors_end[];
 	extern char __kuser_helper_start[], __kuser_helper_end[];
@@ -764,10 +770,10 @@ void __init early_trap_init(void)
 	 * Copy signal return handlers into the vector page, and
 	 * set sigreturn to be a pointer to these.
 	 */
-	memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes,
-	       sizeof(sigreturn_codes));
-	memcpy((void *)KERN_RESTART_CODE, syscall_restart_code,
-	       sizeof(syscall_restart_code));
+	memcpy((void *)(vectors + KERN_SIGRETURN_CODE - CONFIG_VECTORS_BASE),
+	       sigreturn_codes, sizeof(sigreturn_codes));
+	memcpy((void *)(vectors + KERN_RESTART_CODE - CONFIG_VECTORS_BASE),
+	       syscall_restart_code, sizeof(syscall_restart_code));
 
 	flush_icache_range(vectors, vectors + PAGE_SIZE);
 	modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index b1631a7..1b049cd 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -28,20 +28,21 @@
  */
 #include <linux/linkage.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 ENTRY(__get_user_1)
-1:	ldrbt	r2, [r0]
+1:	T(ldrb)	r2, [r0]
 	mov	r0, #0
 	mov	pc, lr
 ENDPROC(__get_user_1)
 
 ENTRY(__get_user_2)
 #ifdef CONFIG_THUMB2_KERNEL
-2:	ldrbt	r2, [r0]
-3:	ldrbt	r3, [r0, #1]
+2:	T(ldrb)	r2, [r0]
+3:	T(ldrb)	r3, [r0, #1]
 #else
-2:	ldrbt	r2, [r0], #1
-3:	ldrbt	r3, [r0]
+2:	T(ldrb)	r2, [r0], #1
+3:	T(ldrb)	r3, [r0]
 #endif
 #ifndef __ARMEB__
 	orr	r2, r2, r3, lsl #8
@@ -53,7 +54,7 @@ ENTRY(__get_user_2)
 ENDPROC(__get_user_2)
 
 ENTRY(__get_user_4)
-4:	ldrt	r2, [r0]
+4:	T(ldr)	r2, [r0]
 	mov	r0, #0
 	mov	pc, lr
 ENDPROC(__get_user_4)
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index 5a01a23..c023fc1 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -28,9 +28,10 @@
  */
 #include <linux/linkage.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 ENTRY(__put_user_1)
-1:	strbt	r2, [r0]
+1:	T(strb)	r2, [r0]
 	mov	r0, #0
 	mov	pc, lr
 ENDPROC(__put_user_1)
@@ -39,19 +40,19 @@ ENTRY(__put_user_2)
 	mov	ip, r2, lsr #8
 #ifdef CONFIG_THUMB2_KERNEL
 #ifndef __ARMEB__
-2:	strbt	r2, [r0]
-3:	strbt	ip, [r0, #1]
+2:	T(strb)	r2, [r0]
+3:	T(strb)	ip, [r0, #1]
 #else
-2:	strbt	ip, [r0]
-3:	strbt	r2, [r0, #1]
+2:	T(strb)	ip, [r0]
+3:	T(strb)	r2, [r0, #1]
 #endif
 #else	/* !CONFIG_THUMB2_KERNEL */
 #ifndef __ARMEB__
-2:	strbt	r2, [r0], #1
-3:	strbt	ip, [r0]
+2:	T(strb)	r2, [r0], #1
+3:	T(strb)	ip, [r0]
 #else
-2:	strbt	ip, [r0], #1
-3:	strbt	r2, [r0]
+2:	T(strb)	ip, [r0], #1
+3:	T(strb)	r2, [r0]
 #endif
 #endif	/* CONFIG_THUMB2_KERNEL */
 	mov	r0, #0
@@ -59,18 +60,18 @@ ENTRY(__put_user_2)
 ENDPROC(__put_user_2)
 
 ENTRY(__put_user_4)
-4:	strt	r2, [r0]
+4:	T(str)	r2, [r0]
 	mov	r0, #0
 	mov	pc, lr
 ENDPROC(__put_user_4)
 
 ENTRY(__put_user_8)
 #ifdef CONFIG_THUMB2_KERNEL
-5:	strt	r2, [r0]
-6:	strt	r3, [r0, #4]
+5:	T(str)	r2, [r0]
+6:	T(str)	r3, [r0, #4]
 #else
-5:	strt	r2, [r0], #4
-6:	strt	r3, [r0]
+5:	T(str)	r2, [r0], #4
+6:	T(str)	r3, [r0]
 #endif
 	mov	r0, #0
 	mov	pc, lr
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
index fee9f6f..d0ece2a 100644
--- a/arch/arm/lib/uaccess.S
+++ b/arch/arm/lib/uaccess.S
@@ -14,6 +14,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 		.text
 
@@ -31,11 +32,11 @@
 		rsb	ip, ip, #4
 		cmp	ip, #2
 		ldrb	r3, [r1], #1
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		ldrgeb	r3, [r1], #1
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		ldrgtb	r3, [r1], #1
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		sub	r2, r2, ip
 		b	.Lc2u_dest_aligned
 
@@ -58,7 +59,7 @@ ENTRY(__copy_to_user)
 		addmi	ip, r2, #4
 		bmi	.Lc2u_0nowords
 		ldr	r3, [r1], #4
-USER(		strt	r3, [r0], #4)			@ May fault
+USER(		T(str)	r3, [r0], #4)			@ May fault
 		mov	ip, r0, lsl #32 - PAGE_SHIFT	@ On each page, use a ld/st??t instruction
 		rsb	ip, ip, #0
 		movs	ip, ip, lsr #32 - PAGE_SHIFT
@@ -87,18 +88,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		stmneia	r0!, {r3 - r4}			@ Shouldnt fault
 		tst	ip, #4
 		ldrne	r3, [r1], #4
-		strnet	r3, [r0], #4			@ Shouldnt fault
+		T(strne) r3, [r0], #4			@ Shouldnt fault
 		ands	ip, ip, #3
 		beq	.Lc2u_0fupi
 .Lc2u_0nowords:	teq	ip, #0
 		beq	.Lc2u_finished
 .Lc2u_nowords:	cmp	ip, #2
 		ldrb	r3, [r1], #1
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		ldrgeb	r3, [r1], #1
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		ldrgtb	r3, [r1], #1
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		b	.Lc2u_finished
 
 .Lc2u_not_enough:
@@ -119,7 +120,7 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
 		mov	r3, r7, pull #8
 		ldr	r7, [r1], #4
 		orr	r3, r3, r7, push #24
-USER(		strt	r3, [r0], #4)			@ May fault
+USER(		T(str)	r3, [r0], #4)			@ May fault
 		mov	ip, r0, lsl #32 - PAGE_SHIFT
 		rsb	ip, ip, #0
 		movs	ip, ip, lsr #32 - PAGE_SHIFT
@@ -154,18 +155,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		movne	r3, r7, pull #8
 		ldrne	r7, [r1], #4
 		orrne	r3, r3, r7, push #24
-		strnet	r3, [r0], #4			@ Shouldnt fault
+		T(strne) r3, [r0], #4			@ Shouldnt fault
 		ands	ip, ip, #3
 		beq	.Lc2u_1fupi
 .Lc2u_1nowords:	mov	r3, r7, get_byte_1
 		teq	ip, #0
 		beq	.Lc2u_finished
 		cmp	ip, #2
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		movge	r3, r7, get_byte_2
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		movgt	r3, r7, get_byte_3
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		b	.Lc2u_finished
 
 .Lc2u_2fupi:	subs	r2, r2, #4
@@ -174,7 +175,7 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
 		mov	r3, r7, pull #16
 		ldr	r7, [r1], #4
 		orr	r3, r3, r7, push #16
-USER(		strt	r3, [r0], #4)			@ May fault
+USER(		T(str)	r3, [r0], #4)			@ May fault
 		mov	ip, r0, lsl #32 - PAGE_SHIFT
 		rsb	ip, ip, #0
 		movs	ip, ip, lsr #32 - PAGE_SHIFT
@@ -209,18 +210,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		movne	r3, r7, pull #16
 		ldrne	r7, [r1], #4
 		orrne	r3, r3, r7, push #16
-		strnet	r3, [r0], #4			@ Shouldnt fault
+		T(strne) r3, [r0], #4			@ Shouldnt fault
 		ands	ip, ip, #3
 		beq	.Lc2u_2fupi
 .Lc2u_2nowords:	mov	r3, r7, get_byte_2
 		teq	ip, #0
 		beq	.Lc2u_finished
 		cmp	ip, #2
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		movge	r3, r7, get_byte_3
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		ldrgtb	r3, [r1], #0
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		b	.Lc2u_finished
 
 .Lc2u_3fupi:	subs	r2, r2, #4
@@ -229,7 +230,7 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
 		mov	r3, r7, pull #24
 		ldr	r7, [r1], #4
 		orr	r3, r3, r7, push #8
-USER(		strt	r3, [r0], #4)			@ May fault
+USER(		T(str)	r3, [r0], #4)			@ May fault
 		mov	ip, r0, lsl #32 - PAGE_SHIFT
 		rsb	ip, ip, #0
 		movs	ip, ip, lsr #32 - PAGE_SHIFT
@@ -264,18 +265,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		movne	r3, r7, pull #24
 		ldrne	r7, [r1], #4
 		orrne	r3, r3, r7, push #8
-		strnet	r3, [r0], #4			@ Shouldnt fault
+		T(strne) r3, [r0], #4			@ Shouldnt fault
 		ands	ip, ip, #3
 		beq	.Lc2u_3fupi
 .Lc2u_3nowords:	mov	r3, r7, get_byte_3
 		teq	ip, #0
 		beq	.Lc2u_finished
 		cmp	ip, #2
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		ldrgeb	r3, [r1], #1
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		ldrgtb	r3, [r1], #0
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		b	.Lc2u_finished
 ENDPROC(__copy_to_user)
 
@@ -294,11 +295,11 @@ ENDPROC(__copy_to_user)
 .Lcfu_dest_not_aligned:
 		rsb	ip, ip, #4
 		cmp	ip, #2
-USER(		ldrbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrb)	r3, [r1], #1)			@ May fault
 		strb	r3, [r0], #1
-USER(		ldrgebt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgeb) r3, [r1], #1)			@ May fault
 		strgeb	r3, [r0], #1
-USER(		ldrgtbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgtb) r3, [r1], #1)			@ May fault
 		strgtb	r3, [r0], #1
 		sub	r2, r2, ip
 		b	.Lcfu_dest_aligned
@@ -321,7 +322,7 @@ ENTRY(__copy_from_user)
 .Lcfu_0fupi:	subs	r2, r2, #4
 		addmi	ip, r2, #4
 		bmi	.Lcfu_0nowords
-USER(		ldrt	r3, [r1], #4)
+USER(		T(ldr)	r3, [r1], #4)
 		str	r3, [r0], #4
 		mov	ip, r1, lsl #32 - PAGE_SHIFT	@ On each page, use a ld/st??t instruction
 		rsb	ip, ip, #0
@@ -350,18 +351,18 @@ USER(		ldrt	r3, [r1], #4)
 		ldmneia	r1!, {r3 - r4}			@ Shouldnt fault
 		stmneia	r0!, {r3 - r4}
 		tst	ip, #4
-		ldrnet	r3, [r1], #4			@ Shouldnt fault
+		T(ldrne) r3, [r1], #4			@ Shouldnt fault
 		strne	r3, [r0], #4
 		ands	ip, ip, #3
 		beq	.Lcfu_0fupi
 .Lcfu_0nowords:	teq	ip, #0
 		beq	.Lcfu_finished
 .Lcfu_nowords:	cmp	ip, #2
-USER(		ldrbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrb)	r3, [r1], #1)			@ May fault
 		strb	r3, [r0], #1
-USER(		ldrgebt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgeb) r3, [r1], #1)			@ May fault
 		strgeb	r3, [r0], #1
-USER(		ldrgtbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgtb) r3, [r1], #1)			@ May fault
 		strgtb	r3, [r0], #1
 		b	.Lcfu_finished
 
@@ -374,7 +375,7 @@ USER(		ldrgtbt	r3, [r1], #1)			@ May fault
 
 .Lcfu_src_not_aligned:
 		bic	r1, r1, #3
-USER(		ldrt	r7, [r1], #4)			@ May fault
+USER(		T(ldr)	r7, [r1], #4)			@ May fault
 		cmp	ip, #2
 		bgt	.Lcfu_3fupi
 		beq	.Lcfu_2fupi
@@ -382,7 +383,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		addmi	ip, r2, #4
 		bmi	.Lcfu_1nowords
 		mov	r3, r7, pull #8
-USER(		ldrt	r7, [r1], #4)			@ May fault
+USER(		T(ldr)	r7, [r1], #4)			@ May fault
 		orr	r3, r3, r7, push #24
 		str	r3, [r0], #4
 		mov	ip, r1, lsl #32 - PAGE_SHIFT
@@ -417,7 +418,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		stmneia	r0!, {r3 - r4}
 		tst	ip, #4
 		movne	r3, r7, pull #8
-USER(		ldrnet	r7, [r1], #4)			@ May fault
+USER(		T(ldrne) r7, [r1], #4)			@ May fault
 		orrne	r3, r3, r7, push #24
 		strne	r3, [r0], #4
 		ands	ip, ip, #3
@@ -437,7 +438,7 @@ USER(		ldrnet	r7, [r1], #4)			@ May fault
 		addmi	ip, r2, #4
 		bmi	.Lcfu_2nowords
 		mov	r3, r7, pull #16
-USER(		ldrt	r7, [r1], #4)			@ May fault
+USER(		T(ldr)	r7, [r1], #4)			@ May fault
 		orr	r3, r3, r7, push #16
 		str	r3, [r0], #4
 		mov	ip, r1, lsl #32 - PAGE_SHIFT
@@ -473,7 +474,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		stmneia	r0!, {r3 - r4}
 		tst	ip, #4
 		movne	r3, r7, pull #16
-USER(		ldrnet	r7, [r1], #4)			@ May fault
+USER(		T(ldrne) r7, [r1], #4)			@ May fault
 		orrne	r3, r3, r7, push #16
 		strne	r3, [r0], #4
 		ands	ip, ip, #3
@@ -485,7 +486,7 @@ USER(		ldrnet	r7, [r1], #4)			@ May fault
 		strb	r3, [r0], #1
 		movge	r3, r7, get_byte_3
 		strgeb	r3, [r0], #1
-USER(		ldrgtbt	r3, [r1], #0)			@ May fault
+USER(		T(ldrgtb) r3, [r1], #0)			@ May fault
 		strgtb	r3, [r0], #1
 		b	.Lcfu_finished
 
@@ -493,7 +494,7 @@ USER(		ldrgtbt	r3, [r1], #0)			@ May fault
 		addmi	ip, r2, #4
 		bmi	.Lcfu_3nowords
 		mov	r3, r7, pull #24
-USER(		ldrt	r7, [r1], #4)			@ May fault
+USER(		T(ldr)	r7, [r1], #4)			@ May fault
 		orr	r3, r3, r7, push #8
 		str	r3, [r0], #4
 		mov	ip, r1, lsl #32 - PAGE_SHIFT
@@ -528,7 +529,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		stmneia	r0!, {r3 - r4}
 		tst	ip, #4
 		movne	r3, r7, pull #24
-USER(		ldrnet	r7, [r1], #4)			@ May fault
+USER(		T(ldrne) r7, [r1], #4)			@ May fault
 		orrne	r3, r3, r7, push #8
 		strne	r3, [r0], #4
 		ands	ip, ip, #3
@@ -538,9 +539,9 @@ USER(		ldrnet	r7, [r1], #4)			@ May fault
 		beq	.Lcfu_finished
 		cmp	ip, #2
 		strb	r3, [r0], #1
-USER(		ldrgebt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgeb) r3, [r1], #1)			@ May fault
 		strgeb	r3, [r0], #1
-USER(		ldrgtbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgtb) r3, [r1], #1)			@ May fault
 		strgtb	r3, [r0], #1
 		b	.Lcfu_finished
 ENDPROC(__copy_from_user)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..f33c422 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -599,6 +599,14 @@ config CPU_CP15_MPU
 	help
 	  Processor has the CP15 register, which has MPU related registers.
 
+config CPU_USE_DOMAINS
+	bool
+	depends on MMU
+	default y if !HAS_TLS_REG
+	help
+	  This option enables or disables the use of domain switching
+	  via the set_fs() function.
+
 #
 # CPU supports 36-bit I/O
 #
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 2858941..499e22d 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -25,6 +25,7 @@
 #include <asm/smp_plat.h>
 #include <asm/tlb.h>
 #include <asm/highmem.h>
+#include <asm/traps.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -935,12 +936,11 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 {
 	struct map_desc map;
 	unsigned long addr;
-	void *vectors;
 
 	/*
 	 * Allocate the vector page early.
 	 */
-	vectors = alloc_bootmem_low_pages(PAGE_SIZE);
+	vectors_page = alloc_bootmem_low_pages(PAGE_SIZE);
 
 	for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
 		pmd_clear(pmd_off_k(addr));
@@ -980,7 +980,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 	 * location (0xffff0000).  If we aren't using high-vectors, also
 	 * create a mapping at the low-vectors virtual address.
 	 */
-	map.pfn = __phys_to_pfn(virt_to_phys(vectors));
+	map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
 	map.virtual = 0xffff0000;
 	map.length = PAGE_SIZE;
 	map.type = MT_HIGH_VECTORS;
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 7d63bea..337f102 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -99,6 +99,10 @@
  *  110x   0   1   0	r/w	r/o
  *  11x0   0   1   0	r/w	r/o
  *  1111   0   1   1	r/w	r/w
+ *
+ * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
+ *  110x   1   1   1	r/o	r/o
+ *  11x0   1   1   1	r/o	r/o
  */
 	.macro	armv6_mt_table pfx
 \pfx\()_mt_table:
@@ -138,8 +142,11 @@
 
 	tst	r1, #L_PTE_USER
 	orrne	r3, r3, #PTE_EXT_AP1
+#ifdef CONFIG_CPU_USE_DOMAINS
+	@ allow kernel read/write access to read-only user pages
 	tstne	r3, #PTE_EXT_APX
 	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+#endif
 
 	tst	r1, #L_PTE_EXEC
 	orreq	r3, r3, #PTE_EXT_XN
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a..c1c3fe0 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -152,8 +152,11 @@ ENTRY(cpu_v7_set_pte_ext)
 
 	tst	r1, #L_PTE_USER
 	orrne	r3, r3, #PTE_EXT_AP1
+#ifdef CONFIG_CPU_USE_DOMAINS
+	@ allow kernel read/write access to read-only user pages
 	tstne	r3, #PTE_EXT_APX
 	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+#endif
 
 	tst	r1, #L_PTE_EXEC
 	orreq	r3, r3, #PTE_EXT_XN
@@ -240,8 +243,6 @@ __v7_setup:
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
 	orr	r4, r4, #TTB_FLAGS
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
-	mov	r10, #0x1f			@ domains 0, 1 = manager
-	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
 	/*
 	 * Memory region attributes with SCTLR.TRE=1
 	 *



From linux at arm.linux.org.uk  Mon Jun 21 05:19:52 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 10:19:52 +0100
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>
Message-ID: <20100621091952.GB7702@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 05:05:34PM +0800, Eric Miao wrote:
> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
> > +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
> > +{
> > + ? ? ? struct samsung_keypad_platdata *npd;
> > +
> > + ? ? ? if (!pd) {
> > + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no platform data\n", __func__);
> > + ? ? ? ? ? ? ? return;
> > + ? ? ? }
> > +
> > + ? ? ? npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
> > + ? ? ? if (!npd)
> > + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no memory for platform data\n", __func__);
> 
> This part of the code is actually duplicated again and again and again
> for each device, PXA and other legacy platforms are bad references for
> this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
> major points:
> 
>  1. A minimum 'struct pxa_device_desc' for a simple description of a
>     device (more than 90% of the devices can be described that way),
>     and avoid using a comparatively heavier weight platform_device,
>     which can be generated at run-time
> 
>  2. pxa_register_device() to allocate and register the platform_device
>     at run-time, along with the platform data

It's a bad idea to make platform data be run-time discardable like this:

> > +struct samsung_keypad_platdata {
> > + ? ? ? const struct matrix_keymap_data *keymap_data;

What you end up with is some platform data structures which must be kept
(those which have pointers to them from the platform data), and others
(the platform data itself) which can be discarded at runtime.

We know that the __initdata attributations cause lots of problems -
they're frequently wrong.  Just see the constant hastle with __devinit
et.al.  The same issue happens with __initdata as well.

So why make things more complicated by allowing some platform data
structures to be discardable and others not to be?  Is their small
size (maybe 6 words for this one) really worth the hastle of getting
__initdata attributations wrong (eg, on the keymap data?)


From catalin.marinas at arm.com  Mon Jun 21 05:20:29 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:20:29 +0100
Subject: [PATCH v3 2/4] ARM: Use lazy cache flushing on ARMv7 SMP systems
In-Reply-To: <20100621091745.23136.67979.stgit@e102109-lin.cambridge.arm.com>
References: <20100621091745.23136.67979.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621092029.23136.39916.stgit@e102109-lin.cambridge.arm.com>

ARMv7 processors like Cortex-A9 broadcast the cache maintenance
operations in hardware. This patch allows the
flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
similar to the UP case.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/smp_plat.h |    4 ++++
 arch/arm/mm/fault-armv.c        |    2 --
 arch/arm/mm/flush.c             |   13 ++++---------
 3 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e621530..963a338 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -13,9 +13,13 @@ static inline int tlb_ops_need_broadcast(void)
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
 
+#if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
+#define cache_ops_need_broadcast()	0
+#else
 static inline int cache_ops_need_broadcast(void)
 {
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
+#endif
 
 #endif
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 9b906de..9d77d90 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -168,10 +168,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 		return;
 
 	mapping = page_mapping(page);
-#ifndef CONFIG_SMP
 	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
 		__flush_dcache_page(mapping, page);
-#endif
 	if (mapping) {
 		if (cache_is_vivt())
 			make_coherent(mapping, vma, addr, ptep, pfn);
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index c6844cb..5ad8711 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -17,6 +17,7 @@
 #include <asm/smp_plat.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
+#include <asm/smp_plat.h>
 
 #include "mm.h"
 
@@ -93,12 +94,10 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
 #define flush_pfn_alias(pfn,vaddr)	do { } while (0)
 #endif
 
-#ifdef CONFIG_SMP
 static void flush_ptrace_access_other(void *args)
 {
 	__flush_icache_all();
 }
-#endif
 
 static
 void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
@@ -122,11 +121,9 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 	if (vma->vm_flags & VM_EXEC) {
 		unsigned long addr = (unsigned long)kaddr;
 		__cpuc_coherent_kern_range(addr, addr + len);
-#ifdef CONFIG_SMP
 		if (cache_ops_need_broadcast())
 			smp_call_function(flush_ptrace_access_other,
 					  NULL, 1);
-#endif
 	}
 }
 
@@ -246,12 +243,10 @@ void flush_dcache_page(struct page *page)
 
 	mapping = page_mapping(page);
 
-#ifndef CONFIG_SMP
-	if (!PageHighMem(page) && mapping && !mapping_mapped(mapping))
+	if (!cache_ops_need_broadcast() &&
+	    !PageHighMem(page) && mapping && !mapping_mapped(mapping))
 		set_bit(PG_dcache_dirty, &page->flags);
-	else
-#endif
-	{
+	else {
 		__flush_dcache_page(mapping, page);
 		if (mapping && cache_is_vivt())
 			__flush_dcache_aliases(mapping, page);



From catalin.marinas at arm.com  Mon Jun 21 05:20:34 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:20:34 +0100
Subject: [PATCH v3 3/4] ARM: Assume new page cache pages have dirty D-cache
In-Reply-To: <20100621091745.23136.67979.stgit@e102109-lin.cambridge.arm.com>
References: <20100621091745.23136.67979.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621092034.23136.7580.stgit@e102109-lin.cambridge.arm.com>

There are places in Linux where writes to newly allocated page cache
pages happen without a subsequent call to flush_dcache_page() (several
PIO drivers including USB HCD). This patch changes the meaning of
PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly
mapped page in update_mmu_cache().

The patch also sets the PG_arch_1 bit in the DMA cache maintenance
function to avoid additional cache flushing in update_mmu_cache().

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/cacheflush.h |    6 +++---
 arch/arm/include/asm/tlbflush.h   |    2 +-
 arch/arm/mm/copypage-v4mc.c       |    2 +-
 arch/arm/mm/copypage-v6.c         |    2 +-
 arch/arm/mm/copypage-xscale.c     |    2 +-
 arch/arm/mm/dma-mapping.c         |    6 ++++++
 arch/arm/mm/fault-armv.c          |    4 ++--
 arch/arm/mm/flush.c               |    3 ++-
 8 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..d3730f0 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -137,10 +137,10 @@
 #endif
 
 /*
- * This flag is used to indicate that the page pointed to by a pte
- * is dirty and requires cleaning before returning it to the user.
+ * This flag is used to indicate that the page pointed to by a pte is clean
+ * and does not require cleaning before returning it to the user.
  */
-#define PG_dcache_dirty PG_arch_1
+#define PG_dcache_clean PG_arch_1
 
 /*
  *	MM Cache Management
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index bd863d8..40a7092 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -552,7 +552,7 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 #endif
 
 /*
- * if PG_dcache_dirty is set for the page, we need to ensure that any
+ * If PG_dcache_clean is not set for the page, we need to ensure that any
  * cache entries for the kernels virtual memory range are written
  * back to the page.
  */
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 598c51a..b806151 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -73,7 +73,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
 {
 	void *kto = kmap_atomic(to, KM_USER1);
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index f55fa10..bdba6c6 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -79,7 +79,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
 	unsigned int offset = CACHE_COLOUR(vaddr);
 	unsigned long kfrom, kto;
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	/* FIXME: not highmem safe */
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 9920c0a..649bbcd 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -95,7 +95,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
 {
 	void *kto = kmap_atomic(to, KM_USER1);
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 13fa536..bb9b612 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -508,6 +508,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
 		outer_inv_range(paddr, paddr + size);
 
 	dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+
+	/*
+	 * Mark the D-cache clean for this page to avoid extra flushing.
+	 */
+	if (dir != DMA_TO_DEVICE)
+		set_bit(PG_dcache_clean, &page->flags);
 }
 EXPORT_SYMBOL(___dma_page_dev_to_cpu);
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 9d77d90..91a691f 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -141,7 +141,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
  * a page table, or changing an existing PTE.  Basically, there are two
  * things that we need to take care of:
  *
- *  1. If PG_dcache_dirty is set for the page, we need to ensure
+ *  1. If PG_dcache_clean is not set for the page, we need to ensure
  *     that any cache entries for the kernels virtual memory
  *     range are written back to the page.
  *  2. If we have multiple shared mappings of the same space in
@@ -168,7 +168,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 		return;
 
 	mapping = page_mapping(page);
-	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
 		__flush_dcache_page(mapping, page);
 	if (mapping) {
 		if (cache_is_vivt())
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 5ad8711..6f55e36 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -245,13 +245,14 @@ void flush_dcache_page(struct page *page)
 
 	if (!cache_ops_need_broadcast() &&
 	    !PageHighMem(page) && mapping && !mapping_mapped(mapping))
-		set_bit(PG_dcache_dirty, &page->flags);
+		clear_bit(PG_dcache_clean, &page->flags);
 	else {
 		__flush_dcache_page(mapping, page);
 		if (mapping && cache_is_vivt())
 			__flush_dcache_aliases(mapping, page);
 		else if (mapping)
 			__flush_icache_all();
+		set_bit(PG_dcache_clean, &page->flags);
 	}
 }
 EXPORT_SYMBOL(flush_dcache_page);



From catalin.marinas at arm.com  Mon Jun 21 05:20:41 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:20:41 +0100
Subject: [PATCH v3 4/4] ARM: Synchronise the I and D caches via set_pte_at()
	on SMP systems
In-Reply-To: <20100621091745.23136.67979.stgit@e102109-lin.cambridge.arm.com>
References: <20100621091745.23136.67979.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621092041.23136.12579.stgit@e102109-lin.cambridge.arm.com>

On SMP systems, there is a small chance of a PTE becoming visible to a
different CPU before the cache maintenance operations in
update_mmu_cache(). This patch follows the IA-64 and PowerPC approach of
synchronising the I and D caches via the set_pte_at() function. In this
case, there is no need for update_mmu_cache() to be implemented since
lazy cache flushing is already handled by the time this function is
called.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/pgtable.h  |   25 ++++++++++++++++++++++---
 arch/arm/include/asm/tlbflush.h |   10 +++++++++-
 arch/arm/mm/fault-armv.c        |    2 ++
 arch/arm/mm/flush.c             |   15 +++++++++++++++
 4 files changed, 48 insertions(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index ab68cf1..a3752f5 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -278,9 +278,24 @@ extern struct page *empty_zero_page;
 
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
 
-#define set_pte_at(mm,addr,ptep,pteval) do { \
-	set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \
- } while (0)
+#ifndef CONFIG_SMP
+static inline void __sync_icache_dcache(pte_t pteval)
+{
+}
+#else
+extern void __sync_icache_dcache(pte_t pteval);
+#endif
+
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+			      pte_t *ptep, pte_t pteval)
+{
+	if (addr >= TASK_SIZE)
+		set_pte_ext(ptep, pteval, 0);
+	else {
+		__sync_icache_dcache(pteval);
+		set_pte_ext(ptep, pteval, PTE_EXT_NG);
+	}
+}
 
 /*
  * The following only work if pte_present() is true.
@@ -292,6 +307,10 @@ extern struct page *empty_zero_page;
 #define pte_young(pte)		(pte_val(pte) & L_PTE_YOUNG)
 #define pte_special(pte)	(0)
 
+#define pte_present_exec_user(pte) \
+	((pte_val(pte) & (L_PTE_PRESENT | L_PTE_EXEC | L_PTE_USER)) == \
+	 (L_PTE_PRESENT | L_PTE_EXEC | L_PTE_USER))
+
 #define PTE_BIT_FUNC(fn,op) \
 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
 
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 40a7092..6aabedd 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -554,10 +554,18 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 /*
  * If PG_dcache_clean is not set for the page, we need to ensure that any
  * cache entries for the kernels virtual memory range are written
- * back to the page.
+ * back to the page. On SMP systems, the cache coherency is handled in the
+ * set_pte_at() function.
  */
+#ifndef CONFIG_SMP
 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 	pte_t *ptep);
+#else
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+				    unsigned long addr, pte_t *ptep)
+{
+}
+#endif
 
 #endif
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 91a691f..030f1da 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -28,6 +28,7 @@
 
 static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
 
+#ifndef CONFIG_SMP
 /*
  * We take the easy way out of this problem - we make the
  * PTE uncacheable.  However, we leave the write buffer on.
@@ -177,6 +178,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 			__flush_icache_all();
 	}
 }
+#endif	/* !CONFIG_SMP */
 
 /*
  * Check whether the write buffer has physical address aliasing
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 6f55e36..2d08a5e 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -212,6 +212,21 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p
 	flush_dcache_mmap_unlock(mapping);
 }
 
+#ifdef CONFIG_SMP
+void __sync_icache_dcache(pte_t pteval)
+{
+	unsigned long pfn = pte_pfn(pteval);
+
+	if (pfn_valid(pfn) && pte_present_exec_user(pteval)) {
+		struct page *page = pfn_to_page(pfn);
+
+		if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+			__flush_dcache_page(NULL, page);
+		__flush_icache_all();
+	}
+}
+#endif
+
 /*
  * Ensure cache coherency between kernel mapping and userspace mapping
  * of this page.



From linux at arm.linux.org.uk  Mon Jun 21 05:23:07 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 10:23:07 +0100
Subject: [PATCH v3 2/7] ARM: Avoid the CONSISTENT_DMA_SIZE warning on
	noMMU builds
In-Reply-To: <20100621091336.22752.78477.stgit@e102109-lin.cambridge.arm.com>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
	<20100621091336.22752.78477.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621092307.GC7702@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 10:13:36AM +0100, Catalin Marinas wrote:
> This macro is not defined when !CONFIG_MMU.

Just move the definitions into the !CONFIG_MMU section.  No need for
any more ifdefs.


From linux at arm.linux.org.uk  Mon Jun 21 05:26:11 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 10:26:11 +0100
Subject: [PATCH v3 7/7] ARM: Do not compile the Thumb-2 module
	relocations on an ARM kernel
In-Reply-To: <20100621091404.22752.10456.stgit@e102109-lin.cambridge.arm.com>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
	<20100621091404.22752.10456.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621092611.GD7702@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 10:14:04AM +0100, Catalin Marinas wrote:
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>

Commit message?  What is the reasoning behind this change?

It'd be useful for those who don't know anything about T2 to have
some such information about this change.


From m.szyprowski at samsung.com  Mon Jun 21 05:29:21 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 21 Jun 2010 11:29:21 +0200
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>
Message-ID: <003701cb1124$3e335f00$ba9a1d00$%szyprowski@samsung.com>

Hello,

On Monday, June 21, 2010 11:06 AM Eric Miao wrote:

> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com>
> wrote:
> > This patch adds samsung keypad device definition for samsung cpus.
> >
> > Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> >  arch/arm/plat-samsung/Kconfig                    |    5 ++
> >  arch/arm/plat-samsung/Makefile                   |    1 +
> >  arch/arm/plat-samsung/dev-keypad.c               |   58
> +++++++++++++++++++++
> 
> Why need an individual file for a simple device?  In the end, these files
> will flood over the plat-samsung/ directory. And now think this - in your
> new SoC design ,the keypad IP is replaced with a completely new one, does
> that mean a new dev-keypad-new1.c, dev-keypad-new2.c?
> 
> I personally prefer a single devices.c for all the devices, if you
> orgnize well, shouldn't take up much code size in that single file.

A separate dev-abc.c files has been chosen by a platform maintainer. This
has some advantages as some unused data can be easily not compiled into
the kernel which is configured specially for a particular board.

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center





From linux at arm.linux.org.uk  Mon Jun 21 05:35:30 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 10:35:30 +0100
Subject: [PATCH v3 1/7] ARM: Align machine_desc.phys_io to a 1MB section
In-Reply-To: <20100621091331.22752.73990.stgit@e102109-lin.cambridge.arm.com>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
	<20100621091331.22752.73990.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621093530.GE7702@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 10:13:31AM +0100, Catalin Marinas wrote:
> Platforms like RealView don't pass a section-aligned pointer via the
> machine_desc structure. This patch aligns the pointer in the
> __create_page_tables function. Reported by Tony Thompson.

I still say this is the wrong way.  As I've said before, please fix it
at the machine_desc initialization point.  If you want, pass it as the
section frame number itself (address >> 20) rather than the address to
allow for more addressing space.


From catalin.marinas at arm.com  Mon Jun 21 05:37:12 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:37:12 +0100
Subject: [PATCH v3 7/7] ARM: Do not compile the Thumb-2
	modulerelocations on an ARM kernel
In-Reply-To: <20100621092611.GD7702@n2100.arm.linux.org.uk>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
	<20100621091404.22752.10456.stgit@e102109-lin.cambridge.arm.com>
	<20100621092611.GD7702@n2100.arm.linux.org.uk>
Message-ID: <1277113032.20758.6.camel@e102109-lin.cambridge.arm.com>

On Mon, 2010-06-21 at 10:26 +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 21, 2010 at 10:14:04AM +0100, Catalin Marinas wrote:
> > Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> 
> Commit message?  What is the reasoning behind this change?
> 
> It'd be useful for those who don't know anything about T2 to have
> some such information about this change.

It looks like I forgot to write a description. The reason is just to
avoid extra code to be compiled in when you don't really need to handle
such relocations (i.e. ARM-only kernel). Do you think it's not worth?

-- 
Catalin



From linux at arm.linux.org.uk  Mon Jun 21 05:38:56 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 10:38:56 +0100
Subject: [PATCH v3 2/4] ARM: Use lazy cache flushing on ARMv7 SMP systems
In-Reply-To: <20100621092029.23136.39916.stgit@e102109-lin.cambridge.arm.com>
References: <20100621091745.23136.67979.stgit@e102109-lin.cambridge.arm.com>
	<20100621092029.23136.39916.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621093856.GF7702@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 10:20:29AM +0100, Catalin Marinas wrote:
> ARMv7 processors like Cortex-A9 broadcast the cache maintenance
> operations in hardware. This patch allows the
> flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
> similar to the UP case.

No.  We know that this trick can't be used on SMP, because update_mmu_cache
is called after the PTE has been established and the page has become
visible to other CPUs in the system.

So this optimization must remain disabled on SMP for correctness.


From linux at arm.linux.org.uk  Mon Jun 21 05:39:44 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 10:39:44 +0100
Subject: [PATCH v3 7/7] ARM: Do not compile the Thumb-2
	modulerelocations on an ARM kernel
In-Reply-To: <1277113032.20758.6.camel@e102109-lin.cambridge.arm.com>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
	<20100621091404.22752.10456.stgit@e102109-lin.cambridge.arm.com>
	<20100621092611.GD7702@n2100.arm.linux.org.uk>
	<1277113032.20758.6.camel@e102109-lin.cambridge.arm.com>
Message-ID: <20100621093944.GG7702@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 10:37:12AM +0100, Catalin Marinas wrote:
> On Mon, 2010-06-21 at 10:26 +0100, Russell King - ARM Linux wrote:
> > On Mon, Jun 21, 2010 at 10:14:04AM +0100, Catalin Marinas wrote:
> > > Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> > 
> > Commit message?  What is the reasoning behind this change?
> > 
> > It'd be useful for those who don't know anything about T2 to have
> > some such information about this change.
> 
> It looks like I forgot to write a description. The reason is just to
> avoid extra code to be compiled in when you don't really need to handle
> such relocations (i.e. ARM-only kernel). Do you think it's not worth?

I think its worth giving other people the information they need to
understand the change if they review the patch.


From catalin.marinas at arm.com  Mon Jun 21 05:42:35 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:42:35 +0100
Subject: [PATCH v3 2/4] ARM: Use lazy cache flushing on ARMv7 SMPsystems
In-Reply-To: <20100621093856.GF7702@n2100.arm.linux.org.uk>
References: <20100621091745.23136.67979.stgit@e102109-lin.cambridge.arm.com>
	<20100621092029.23136.39916.stgit@e102109-lin.cambridge.arm.com>
	<20100621093856.GF7702@n2100.arm.linux.org.uk>
Message-ID: <1277113355.20758.11.camel@e102109-lin.cambridge.arm.com>

On Mon, 2010-06-21 at 10:38 +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 21, 2010 at 10:20:29AM +0100, Catalin Marinas wrote:
> > ARMv7 processors like Cortex-A9 broadcast the cache maintenance
> > operations in hardware. This patch allows the
> > flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
> > similar to the UP case.
> 
> No.  We know that this trick can't be used on SMP, because update_mmu_cache
> is called after the PTE has been established and the page has become
> visible to other CPUs in the system.
> 
> So this optimization must remain disabled on SMP for correctness.

Even the current code isn't correct because the I-cache is invalidated
via update_mmu_cache() but set_pte_at() gets called before.

So this is handled by patch 4/4 in the series. I can reorder them but I
couldn't see any reason since the current non-lazy behaviour isn't
correct either.

-- 
Catalin



From catalin.marinas at arm.com  Mon Jun 21 05:53:05 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 10:53:05 +0100
Subject: [PATCH v3 2/7] ARM: Avoid the CONSISTENT_DMA_SIZE warning on
	noMMU builds
In-Reply-To: <20100621092307.GC7702@n2100.arm.linux.org.uk>
References: <20100621090801.22752.21039.stgit@e102109-lin.cambridge.arm.com>
	<20100621091336.22752.78477.stgit@e102109-lin.cambridge.arm.com>
	<20100621092307.GC7702@n2100.arm.linux.org.uk>
Message-ID: <1277113985.20758.14.camel@e102109-lin.cambridge.arm.com>

On Mon, 2010-06-21 at 10:23 +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 21, 2010 at 10:13:36AM +0100, Catalin Marinas wrote:
> > This macro is not defined when !CONFIG_MMU.
> 
> Just move the definitions into the !CONFIG_MMU section.  No need for
> any more ifdefs.

Done.


ARM: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds

From: Catalin Marinas <catalin.marinas at arm.com>

This macro is not defined when !CONFIG_MMU so this patch moves the
CONSISTENT_* definitions to the CONFIG_MMU section.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/mm/dma-mapping.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 13fa536..9e7742f 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -24,15 +24,6 @@
 #include <asm/tlbflush.h>
 #include <asm/sizes.h>
 
-/* Sanity check size */
-#if (CONSISTENT_DMA_SIZE % SZ_2M)
-#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
-#endif
-
-#define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
-#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
-#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
-
 static u64 get_coherent_dma_mask(struct device *dev)
 {
 	u64 mask = ISA_DMA_THRESHOLD;
@@ -123,6 +114,15 @@ static void __dma_free_buffer(struct page *page, size_t size)
 }
 
 #ifdef CONFIG_MMU
+/* Sanity check size */
+#if (CONSISTENT_DMA_SIZE % SZ_2M)
+#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
+#endif
+
+#define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
+#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
+#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
+
 /*
  * These are the page tables (2MB each) covering uncached, DMA consistent allocations
  */

-- 
Catalin



From kmpark at infradead.org  Mon Jun 21 06:00:06 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Mon, 21 Jun 2010 19:00:06 +0900
Subject: Samsung SoCs naming rules
Message-ID: <AANLkTiljyiQohHVJxUsn7Q6_IwTZk2AdNlLRxgGmxNpQ@mail.gmail.com>

Dear all,

Now Samsung SoCs doesn't have any special rules include chip name.

Historically s5pc100 is successor form s3c6410 and this chip from
s3c2410 series.
on the other hand, s5pc110 (cortex a8) and s5pc64xx (armv6) is
different from previous chips.

So it's not good idea grouping with the prefix. e.g., s5p series. and
the reason to create the samsung.

we tried to find a common name several times but failed to get proper
name, I hope community give good name rules.

Thank you,
Kyungmin Park


From catalin.marinas at arm.com  Mon Jun 21 06:05:49 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 11:05:49 +0100
Subject: [PATCH v3 1/7] ARM: Align machine_desc.phys_io to a 1MB section
In-Reply-To: <20100621093530.GE7702@n2100.arm.linux.org.uk>
References: <20100621093530.GE7702@n2100.arm.linux.org.uk>
Message-ID: <1277114749.20758.24.camel@e102109-lin.cambridge.arm.com>

On Mon, 2010-06-21 at 10:35 +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 21, 2010 at 10:13:31AM +0100, Catalin Marinas wrote:
> > Platforms like RealView don't pass a section-aligned pointer via the
> > machine_desc structure. This patch aligns the pointer in the
> > __create_page_tables function. Reported by Tony Thompson.
> 
> I still say this is the wrong way.  As I've said before, please fix it
> at the machine_desc initialization point.  

This requirement doesn't seem to be well documented and platforms don't
follow it (e.g. RealView and VExpress). Since it's the head.S code
responsible for this temporary mapping, the platform code wouldn't need
to know whether sections or pages or something else are used to map it.
But io_pg_offst already makes the assumption about sections.

> If you want, pass it as the
> section frame number itself (address >> 20) rather than the address to
> allow for more addressing space.

I would rather go for a PFN to allow more addressing space (but doesn't
solve the section alignment).

For now, I'll send a couple of patches to fix RealView and VExpress
boards.

-- 
Catalin



From eric.y.miao at gmail.com  Mon Jun 21 06:19:17 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 18:19:17 +0800
Subject: [PATCH 1/2] [ARM] Introduce 'struct machine_class' for SoC level 
	abstraction
In-Reply-To: <20100621090245.GA7702@n2100.arm.linux.org.uk>
References: <1277042450-30382-1-git-send-email-eric.miao@canonical.com> 
	<201006211527.49786.jeremy.kerr@canonical.com>
	<AANLkTilUddhIW0C5LN4b7igh6vEDvelhnT8a3or677Zk@mail.gmail.com> 
	<20100621090245.GA7702@n2100.arm.linux.org.uk>
Message-ID: <AANLkTimHuNuaVrRqPMiLpItBNgBeW3Cdqg6hBYT1DEpl@mail.gmail.com>

On Mon, Jun 21, 2010 at 5:02 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, Jun 21, 2010 at 04:23:22PM +0800, Eric Miao wrote:
>> So that from derivative POV, it can be expressed as:
>>
>> ? ? ? if (mdesc->class && mdesc->class->map_io)
>> ? ? ? ? ? ? ? mdesc->class->map_io();
>> ? ? ? if (mdesc->map_io())
>> ? ? ? ? ? ? ? mdesc->map_io();
>>
>> But this seems to make things a bit over complicated, so for such cases
>> I'd prefer:
>>
>> 1. have a separate machine_class for mainstone
>> 2. or move the board specific map_io() separatedly
>
> How about making the presence of mdesc->map_io override the class
> version?
>
> So if mainstone provides its own map_io() function, it is still
> responsible (as is today) for calling the PXA specific map_io().
> The same behaviour seems sensible to apply to the other class
> functions as well - allow platforms to override the class
> version, and leave the replacement platform function responsible
> for calling the class if that's what it needs to do.
>

Yep, that's a good idea, and actually was as my first version. Yet my
concern is this doesn't easily fit for the class data, i.e., allow the
machine specific data to override the class data like below:

	if (valid_value(mdesc->phys_io))
		use(mdesc->phys_io);
	else
		use(mdesc->class->phys_io);

but since phys_io could be valid for value zero (as if not explicitly
initialized), so we may end up defining like below to allow use of the
default class values:

MACHINE_START(....)
	.phys_io	= INVALID_ADDRESS,
	.io_pg_offst	= INVALID_ADDRESS,
	....
MACHINE_END

This, however, creates some incompatiblity in semantics from the functions.
That's why I chose a much simpler scheme: use the class version if class
is there, otherwise use the machine specific one.


From linux at arm.linux.org.uk  Mon Jun 21 06:26:23 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 11:26:23 +0100
Subject: [PATCH v3 1/7] ARM: Align machine_desc.phys_io to a 1MB section
In-Reply-To: <1277114749.20758.24.camel@e102109-lin.cambridge.arm.com>
References: <20100621093530.GE7702@n2100.arm.linux.org.uk>
	<1277114749.20758.24.camel@e102109-lin.cambridge.arm.com>
Message-ID: <20100621102623.GI7702@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 11:05:49AM +0100, Catalin Marinas wrote:
> On Mon, 2010-06-21 at 10:35 +0100, Russell King - ARM Linux wrote:
> > On Mon, Jun 21, 2010 at 10:13:31AM +0100, Catalin Marinas wrote:
> > > Platforms like RealView don't pass a section-aligned pointer via the
> > > machine_desc structure. This patch aligns the pointer in the
> > > __create_page_tables function. Reported by Tony Thompson.
> > 
> > I still say this is the wrong way.  As I've said before, please fix it
> > at the machine_desc initialization point.  
> 
> This requirement doesn't seem to be well documented and platforms don't
> follow it (e.g. RealView and VExpress). Since it's the head.S code
> responsible for this temporary mapping, the platform code wouldn't need
> to know whether sections or pages or something else are used to map it.
> But io_pg_offst already makes the assumption about sections.

We're never going to map it using sections - using pages implies a
way to allocate 2nd level page tables, and we don't have any memory
allocators which can work this early.

> > If you want, pass it as the
> > section frame number itself (address >> 20) rather than the address to
> > allow for more addressing space.
> 
> I would rather go for a PFN to allow more addressing space (but doesn't
> solve the section alignment).

PFNs don't solve the problem you've brought up - might as well stick
with what we have in that case.


From catalin.marinas at arm.com  Mon Jun 21 06:29:29 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 11:29:29 +0100
Subject: [PATCH v4 0/8] Patches/fixes for 2.6.35
Message-ID: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>

Updates from version 3 of these series:

- noMMU warning patch changed by moving the CONSISTENT_* definitions to
  the CONFIG_MMU section
- .phys_io alignment patch replaced by two patches that enforce the
  alignment in the machine_desc structures for VExpress and RealView
- commit log added to the T2 module relocations patch


Catalin Marinas (8):
      ARM: Avoid the CONSISTENT_DMA_SIZE warning on noMMU builds
      ARM: The v6_dma_inv_range() function must preserve data on SMP
      ARM: Add a config option for the ARM11MPCore DMA cache maintenance workaround
      ARM: Add support for the MOVW/MOVT relocations in Thumb-2
      ARM: Remove dummy loads from the original relocation address
      ARM: Do not compile the Thumb-2 module relocations on an ARM kernel
      ARM: VExpress: Align the machine_desc.phys_io to 1MB section
      ARM: RealView: Align the machine_desc.phys_io to 1MB section


 arch/arm/include/asm/elf.h               |    2 ++
 arch/arm/kernel/module.c                 |   34 ++++++++++++++++++++++++++++++
 arch/arm/mach-realview/realview_eb.c     |    3 ++-
 arch/arm/mach-realview/realview_pb1176.c |    3 ++-
 arch/arm/mach-realview/realview_pb11mp.c |    3 ++-
 arch/arm/mach-realview/realview_pba8.c   |    3 ++-
 arch/arm/mach-realview/realview_pbx.c    |    3 ++-
 arch/arm/mach-vexpress/ct-ca9x4.c        |    3 ++-
 arch/arm/mm/Kconfig                      |   19 +++++++++++++++++
 arch/arm/mm/cache-v6.S                   |   18 ++++++++++++----
 arch/arm/mm/dma-mapping.c                |   18 ++++++++--------
 11 files changed, 90 insertions(+), 19 deletions(-)

-- 
Catalin


From catalin.marinas at arm.com  Mon Jun 21 06:29:35 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 11:29:35 +0100
Subject: [PATCH v4 1/8] ARM: Avoid the CONSISTENT_DMA_SIZE warning on noMMU
	builds
In-Reply-To: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
References: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621102935.9353.82172.stgit@e102109-lin.cambridge.arm.com>

This macro is not defined when !CONFIG_MMU so this patch moves the
CONSISTENT_* definitions to the CONFIG_MMU section.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/mm/dma-mapping.c |   18 +++++++++---------
 1 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 13fa536..9e7742f 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -24,15 +24,6 @@
 #include <asm/tlbflush.h>
 #include <asm/sizes.h>
 
-/* Sanity check size */
-#if (CONSISTENT_DMA_SIZE % SZ_2M)
-#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
-#endif
-
-#define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
-#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
-#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
-
 static u64 get_coherent_dma_mask(struct device *dev)
 {
 	u64 mask = ISA_DMA_THRESHOLD;
@@ -123,6 +114,15 @@ static void __dma_free_buffer(struct page *page, size_t size)
 }
 
 #ifdef CONFIG_MMU
+/* Sanity check size */
+#if (CONSISTENT_DMA_SIZE % SZ_2M)
+#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
+#endif
+
+#define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT)
+#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
+#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
+
 /*
  * These are the page tables (2MB each) covering uncached, DMA consistent allocations
  */



From catalin.marinas at arm.com  Mon Jun 21 06:29:40 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 11:29:40 +0100
Subject: [PATCH v4 2/8] ARM: The v6_dma_inv_range() function must preserve
	data on SMP
In-Reply-To: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
References: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621102940.9353.60695.stgit@e102109-lin.cambridge.arm.com>

A recent patch for DMA cache maintenance on ARM11MPCore added a write
for ownership trick to the v6_dma_inv_range() function. Such operation
destroys data already present in the buffer. However, this function is
used with with dma_sync_single_for_device() which is supposed to
preserve the existing data transfered into the buffer. This patch adds a
combination of read/write for ownership to preserve the original data.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Reported-by: Ronen Shitrit <rshitrit at marvell.com>
---
 arch/arm/mm/cache-v6.S |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index e46ecd8..332b48c 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -212,7 +212,8 @@ v6_dma_inv_range:
 #endif
 1:
 #ifdef CONFIG_SMP
-	str	r0, [r0]			@ write for ownership
+	ldr	r2, [r0]			@ read for ownership
+	str	r2, [r0]			@ write for ownership
 #endif
 #ifdef HARVARD_CACHE
 	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D line



From catalin.marinas at arm.com  Mon Jun 21 06:29:46 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 11:29:46 +0100
Subject: [PATCH v4 3/8] ARM: Add a config option for the ARM11MPCore DMA
	cache maintenance workaround
In-Reply-To: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
References: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621102946.9353.22352.stgit@e102109-lin.cambridge.arm.com>

Commit f4d6477f introduced a workaround for the lack of hardware
broadcasting of the cache maintenance operations on ARM11MPCore.
However, the workaround is only valid on CPUs that do not do speculative
loads into the D-cache.

This patch adds a Kconfig option with the corresponding help to make the
above clear. When the DMA_CACHE_RWFO option is disabled, the kernel
behaviour is that prior to the f4d6477f commit. This also allows ARMv6
UP processors with speculative loads to work correctly.

For other processors, a different workaround may be needed.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Ronen Shitrit <rshitrit at marvell.com>
---
 arch/arm/mm/Kconfig    |   19 +++++++++++++++++++
 arch/arm/mm/cache-v6.S |   15 ++++++++++++---
 2 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..fc1b2fa 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -735,6 +735,25 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
 	  Forget about fast user space cmpxchg support.
 	  It is just not possible.
 
+config DMA_CACHE_RWFO
+	bool "Enable read/write for ownership DMA cache maintenance"
+	depends on CPU_V6 && SMP
+	default y
+	help
+	  The Snoop Control Unit on ARM11MPCore does not detect the
+	  cache maintenance operations and the dma_{map,unmap}_area()
+	  functions may leave stale cache entries on other CPUs. By
+	  enabling this option, Read or Write For Ownership in the ARMv6
+	  DMA cache maintenance functions is performed. These LDR/STR
+	  instructions change the cache line state to shared or modified
+	  so that the cache operation has the desired effect.
+
+	  Note that the workaround is only valid on processors that do
+	  not perform speculative loads into the D-cache. For such
+	  processors, if cache maintenance operations are not broadcast
+	  in hardware, other workarounds are needed (e.g. cache
+	  maintenance broadcasting in software via FIQ).
+
 config OUTER_CACHE
 	bool
 
diff --git a/arch/arm/mm/cache-v6.S b/arch/arm/mm/cache-v6.S
index 332b48c..86aa689 100644
--- a/arch/arm/mm/cache-v6.S
+++ b/arch/arm/mm/cache-v6.S
@@ -211,7 +211,7 @@ v6_dma_inv_range:
 	mcrne	p15, 0, r1, c7, c15, 1		@ clean & invalidate unified line
 #endif
 1:
-#ifdef CONFIG_SMP
+#ifdef CONFIG_DMA_CACHE_RWFO
 	ldr	r2, [r0]			@ read for ownership
 	str	r2, [r0]			@ write for ownership
 #endif
@@ -235,7 +235,7 @@ v6_dma_inv_range:
 v6_dma_clean_range:
 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
-#ifdef CONFIG_SMP
+#ifdef CONFIG_DMA_CACHE_RWFO
 	ldr	r2, [r0]			@ read for ownership
 #endif
 #ifdef HARVARD_CACHE
@@ -258,7 +258,7 @@ v6_dma_clean_range:
 ENTRY(v6_dma_flush_range)
 	bic	r0, r0, #D_CACHE_LINE_SIZE - 1
 1:
-#ifdef CONFIG_SMP
+#ifdef CONFIG_DMA_CACHE_RWFO
 	ldr	r2, [r0]			@ read for ownership
 	str	r2, [r0]			@ write for ownership
 #endif
@@ -284,9 +284,13 @@ ENTRY(v6_dma_map_area)
 	add	r1, r1, r0
 	teq	r2, #DMA_FROM_DEVICE
 	beq	v6_dma_inv_range
+#ifndef CONFIG_DMA_CACHE_RWFO
+	b	v6_dma_clean_range
+#else
 	teq	r2, #DMA_TO_DEVICE
 	beq	v6_dma_clean_range
 	b	v6_dma_flush_range
+#endif
 ENDPROC(v6_dma_map_area)
 
 /*
@@ -296,6 +300,11 @@ ENDPROC(v6_dma_map_area)
  *	- dir	- DMA direction
  */
 ENTRY(v6_dma_unmap_area)
+#ifndef CONFIG_DMA_CACHE_RWFO
+	add	r1, r1, r0
+	teq	r2, #DMA_TO_DEVICE
+	bne	v6_dma_inv_range
+#endif
 	mov	pc, lr
 ENDPROC(v6_dma_unmap_area)
 



From catalin.marinas at arm.com  Mon Jun 21 06:29:51 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 11:29:51 +0100
Subject: [PATCH v4 4/8] ARM: Add support for the MOVW/MOVT relocations in
	Thumb-2
In-Reply-To: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
References: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621102951.9353.99611.stgit@e102109-lin.cambridge.arm.com>

The patch adds handling case for the R_ARM_THM_MOVW_ABS_NC and
R_ARM_THM_MOVT_ABS relocations in arch/arm/kernel/module.c. Such
relocations may appear in Thumb-2 compiled kernel modules.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Reported-by: Kyungmin Park <kmpark at infradead.org>
---
 arch/arm/include/asm/elf.h |    2 ++
 arch/arm/kernel/module.c   |   32 ++++++++++++++++++++++++++++++++
 2 files changed, 34 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index 51662fe..4d0e730 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -59,6 +59,8 @@ typedef struct user_fp elf_fpregset_t;
 
 #define R_ARM_THM_CALL		10
 #define R_ARM_THM_JUMP24	30
+#define R_ARM_THM_MOVW_ABS_NC	47
+#define R_ARM_THM_MOVT_ABS	48
 
 /*
  * These are used to set parameters in the core dumps.
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index c628bdf..ae3c804 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -237,6 +237,38 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 			lower = *(u16 *)(loc + 2);
 			break;
 
+		case R_ARM_THM_MOVW_ABS_NC:
+		case R_ARM_THM_MOVT_ABS:
+			upper = *(u16 *)loc;
+			lower = *(u16 *)(loc + 2);
+
+			/*
+			 * MOVT/MOVW instructions encoding in Thumb-2:
+			 *
+			 * i	= upper[10]
+			 * imm4	= upper[3:0]
+			 * imm3	= lower[14:12]
+			 * imm8	= lower[7:0]
+			 *
+			 * imm16 = imm4:i:imm3:imm8
+			 */
+			offset = ((upper & 0x000f) << 12) |
+				((upper & 0x0400) << 1) |
+				((lower & 0x7000) >> 4) | (lower & 0x00ff);
+			offset = (offset ^ 0x8000) - 0x8000;
+			offset += sym->st_value;
+
+			if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS)
+				offset >>= 16;
+
+			*(u16 *)loc = (u16)((upper & 0xfbf0) |
+					    ((offset & 0xf000) >> 12) |
+					    ((offset & 0x0800) >> 1));
+			*(u16 *)(loc + 2) = (u16)((lower & 0x8f00) |
+						  ((offset & 0x0700) << 4) |
+						  (offset & 0x00ff));
+			break;
+
 		default:
 			printk(KERN_ERR "%s: unknown relocation: %u\n",
 			       module->name, ELF32_R_TYPE(rel->r_info));



From catalin.marinas at arm.com  Mon Jun 21 06:29:57 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 11:29:57 +0100
Subject: [PATCH v4 5/8] ARM: Remove dummy loads from the original relocation
	address
In-Reply-To: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
References: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621102957.9353.12084.stgit@e102109-lin.cambridge.arm.com>

Reading back the upper and lower values in the R_ARM_THM_CALL and
R_ARM_THM_JUMP24 case was introduced by a previous commit but they are
not needed.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/kernel/module.c |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index ae3c804..aab7fca 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -233,8 +233,6 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 			*(u16 *)(loc + 2) = (u16)((lower & 0xd000) |
 						  (j1 << 13) | (j2 << 11) |
 						  ((offset >> 1) & 0x07ff));
-			upper = *(u16 *)loc;
-			lower = *(u16 *)(loc + 2);
 			break;
 
 		case R_ARM_THM_MOVW_ABS_NC:



From catalin.marinas at arm.com  Mon Jun 21 06:30:02 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 11:30:02 +0100
Subject: [PATCH v4 6/8] ARM: Do not compile the Thumb-2 module relocations
	on an ARM kernel
In-Reply-To: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
References: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621103002.9353.14704.stgit@e102109-lin.cambridge.arm.com>

Kernels compiled to ARM do not need to handle Thumb-2 module relocations
as interworking is not allowed. This patch #ifdef's out the handling of
such relocations.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/kernel/module.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index aab7fca..6b46058 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -102,7 +102,9 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 		unsigned long loc;
 		Elf32_Sym *sym;
 		s32 offset;
+#ifdef CONFIG_THUMB2_KERNEL
 		u32 upper, lower, sign, j1, j2;
+#endif
 
 		offset = ELF32_R_SYM(rel->r_info);
 		if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) {
@@ -185,6 +187,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 					(offset & 0x0fff);
 			break;
 
+#ifdef CONFIG_THUMB2_KERNEL
 		case R_ARM_THM_CALL:
 		case R_ARM_THM_JUMP24:
 			upper = *(u16 *)loc;
@@ -266,6 +269,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
 						  ((offset & 0x0700) << 4) |
 						  (offset & 0x00ff));
 			break;
+#endif
 
 		default:
 			printk(KERN_ERR "%s: unknown relocation: %u\n",



From catalin.marinas at arm.com  Mon Jun 21 06:30:08 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 11:30:08 +0100
Subject: [PATCH v4 7/8] ARM: VExpress: Align the machine_desc.phys_io to 1MB
	section
In-Reply-To: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
References: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621103008.9353.17436.stgit@e102109-lin.cambridge.arm.com>

When not aligned, random bits could be written in the initial page table
by the __create_page_tables() function.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/mach-vexpress/ct-ca9x4.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index e6f7303..dcbe39e 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -9,6 +9,7 @@
 #include <linux/amba/clcd.h>
 
 #include <asm/clkdev.h>
+#include <asm/pgtable.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
@@ -235,7 +236,7 @@ static void ct_ca9x4_init(void)
 }
 
 MACHINE_START(VEXPRESS, "ARM-Versatile Express CA9x4")
-	.phys_io	= V2M_UART0,
+	.phys_io	= V2M_UART0 & SECTION_MASK,
 	.io_pg_offst	= (__MMIO_P2V(V2M_UART0) >> 18) & 0xfffc,
 	.boot_params	= PHYS_OFFSET + 0x00000100,
 	.map_io		= ct_ca9x4_map_io,



From catalin.marinas at arm.com  Mon Jun 21 06:30:14 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 11:30:14 +0100
Subject: [PATCH v4 8/8] ARM: RealView: Align the machine_desc.phys_io to 1MB
	section
In-Reply-To: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
References: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621103014.9353.82108.stgit@e102109-lin.cambridge.arm.com>

When not aligned, random bits could be written in the initial page table
by the __create_page_tables() function.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/mach-realview/realview_eb.c     |    3 ++-
 arch/arm/mach-realview/realview_pb1176.c |    3 ++-
 arch/arm/mach-realview/realview_pb11mp.c |    3 ++-
 arch/arm/mach-realview/realview_pba8.c   |    3 ++-
 arch/arm/mach-realview/realview_pbx.c    |    3 ++-
 5 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 422ccd7..4425018 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -32,6 +32,7 @@
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
+#include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/localtimer.h>
@@ -457,7 +458,7 @@ static void __init realview_eb_init(void)
 
 MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
 	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-	.phys_io	= REALVIEW_EB_UART0_BASE,
+	.phys_io	= REALVIEW_EB_UART0_BASE & SECTION_MASK,
 	.io_pg_offst	= (IO_ADDRESS(REALVIEW_EB_UART0_BASE) >> 18) & 0xfffc,
 	.boot_params	= PHYS_OFFSET + 0x00000100,
 	.fixup		= realview_fixup,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 96568eb..099a1f1 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -32,6 +32,7 @@
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
+#include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 
@@ -351,7 +352,7 @@ static void __init realview_pb1176_init(void)
 
 MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
 	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-	.phys_io	= REALVIEW_PB1176_UART0_BASE,
+	.phys_io	= REALVIEW_PB1176_UART0_BASE & SECTION_MASK,
 	.io_pg_offst	= (IO_ADDRESS(REALVIEW_PB1176_UART0_BASE) >> 18) & 0xfffc,
 	.boot_params	= PHYS_OFFSET + 0x00000100,
 	.fixup		= realview_pb1176_fixup,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 7fbefbb..0e07a5c 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -32,6 +32,7 @@
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
+#include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/localtimer.h>
@@ -373,7 +374,7 @@ static void __init realview_pb11mp_init(void)
 
 MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
 	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-	.phys_io	= REALVIEW_PB11MP_UART0_BASE,
+	.phys_io	= REALVIEW_PB11MP_UART0_BASE & SECTION_MASK,
 	.io_pg_offst	= (IO_ADDRESS(REALVIEW_PB11MP_UART0_BASE) >> 18) & 0xfffc,
 	.boot_params	= PHYS_OFFSET + 0x00000100,
 	.fixup		= realview_fixup,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index d3c113b..ac2f06f 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -31,6 +31,7 @@
 #include <asm/leds.h>
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
+#include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 
 #include <asm/mach/arch.h>
@@ -323,7 +324,7 @@ static void __init realview_pba8_init(void)
 
 MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
 	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-	.phys_io	= REALVIEW_PBA8_UART0_BASE,
+	.phys_io	= REALVIEW_PBA8_UART0_BASE & SECTION_MASK,
 	.io_pg_offst	= (IO_ADDRESS(REALVIEW_PBA8_UART0_BASE) >> 18) & 0xfffc,
 	.boot_params	= PHYS_OFFSET + 0x00000100,
 	.fixup		= realview_fixup,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index a235ba3..08fd683 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -31,6 +31,7 @@
 #include <asm/mach-types.h>
 #include <asm/pmu.h>
 #include <asm/smp_twd.h>
+#include <asm/pgtable.h>
 #include <asm/hardware/gic.h>
 #include <asm/hardware/cache-l2x0.h>
 
@@ -409,7 +410,7 @@ static void __init realview_pbx_init(void)
 
 MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
 	/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-	.phys_io	= REALVIEW_PBX_UART0_BASE,
+	.phys_io	= REALVIEW_PBX_UART0_BASE & SECTION_MASK,
 	.io_pg_offst	= (IO_ADDRESS(REALVIEW_PBX_UART0_BASE) >> 18) & 0xfffc,
 	.boot_params	= PHYS_OFFSET + 0x00000100,
 	.fixup		= realview_pbx_fixup,



From eric.y.miao at gmail.com  Mon Jun 21 06:36:13 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 18:36:13 +0800
Subject: Samsung SoCs naming rules
In-Reply-To: <AANLkTiljyiQohHVJxUsn7Q6_IwTZk2AdNlLRxgGmxNpQ@mail.gmail.com>
References: <AANLkTiljyiQohHVJxUsn7Q6_IwTZk2AdNlLRxgGmxNpQ@mail.gmail.com>
Message-ID: <AANLkTilnjN1dBWPKCuDt_bg8-5GEuSCrOh7vhqGf-VQU@mail.gmail.com>

On Mon, Jun 21, 2010 at 6:00 PM, Kyungmin Park <kmpark at infradead.org> wrote:
> Dear all,
>
> Now Samsung SoCs doesn't have any special rules include chip name.
>
> Historically s5pc100 is successor form s3c6410 and this chip from
> s3c2410 series.
> on the other hand, s5pc110 (cortex a8) and s5pc64xx (armv6) is
> different from previous chips.

Don't be shy, Samsung is not the only vendor messes the naming of their
SoCs. Marvell might have done a better job on this :-)

>
> So it's not good idea grouping with the prefix. e.g., s5p series. and
> the reason to create the samsung.
>

My guess is your s5p will focus more on Cortex-A8 (or A9 possibly),
even with subsequent processors. And only s5pc100 is an exception,
that's fine, you can still put s5pc100 into mach-s3c6410, and people
will know it's actually closer to s3c6410. And other SoCs will share the
common s5p prefix.

> we tried to find a common name several times but failed to get proper
> name, I hope community give good name rules.


From eric.y.miao at gmail.com  Mon Jun 21 06:39:10 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 18:39:10 +0800
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <20100621091952.GB7702@n2100.arm.linux.org.uk>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com> 
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com> 
	<20100621091952.GB7702@n2100.arm.linux.org.uk>
Message-ID: <AANLkTilU1X1LR33Eed9BVGE2n-dqRuIuUFfbDd3gzEVc@mail.gmail.com>

On Mon, Jun 21, 2010 at 5:19 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, Jun 21, 2010 at 05:05:34PM +0800, Eric Miao wrote:
>> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>> > +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
>> > +{
>> > + ? ? ? struct samsung_keypad_platdata *npd;
>> > +
>> > + ? ? ? if (!pd) {
>> > + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no platform data\n", __func__);
>> > + ? ? ? ? ? ? ? return;
>> > + ? ? ? }
>> > +
>> > + ? ? ? npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
>> > + ? ? ? if (!npd)
>> > + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no memory for platform data\n", __func__);
>>
>> This part of the code is actually duplicated again and again and again
>> for each device, PXA and other legacy platforms are bad references for
>> this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
>> major points:
>>
>> ?1. A minimum 'struct pxa_device_desc' for a simple description of a
>> ? ? device (more than 90% of the devices can be described that way),
>> ? ? and avoid using a comparatively heavier weight platform_device,
>> ? ? which can be generated at run-time
>>
>> ?2. pxa_register_device() to allocate and register the platform_device
>> ? ? at run-time, along with the platform data
>
> It's a bad idea to make platform data be run-time discardable like this:
>
>> > +struct samsung_keypad_platdata {
>> > + ? ? ? const struct matrix_keymap_data *keymap_data;
>
> What you end up with is some platform data structures which must be kept
> (those which have pointers to them from the platform data), and others
> (the platform data itself) which can be discarded at runtime.
>
> We know that the __initdata attributations cause lots of problems -
> they're frequently wrong. ?Just see the constant hastle with __devinit
> et.al. ?The same issue happens with __initdata as well.
>
> So why make things more complicated by allowing some platform data
> structures to be discardable and others not to be? ?Is their small
> size (maybe 6 words for this one) really worth the hastle of getting
> __initdata attributations wrong (eg, on the keymap data?)
>

Russell,

The benefit I see is when multiple boards are compiled in, those
data not used can be automatically discarded.


From eric.y.miao at gmail.com  Mon Jun 21 06:43:50 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 18:43:50 +0800
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <003701cb1124$3e335f00$ba9a1d00$%szyprowski@samsung.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com> 
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com> 
	<003701cb1124$3e335f00$ba9a1d00$%szyprowski@samsung.com>
Message-ID: <AANLkTiny_KNR0mZy9D52gZrGqJuYDPkK-P_zCFTfrAcm@mail.gmail.com>

On Mon, Jun 21, 2010 at 5:29 PM, Marek Szyprowski
<m.szyprowski at samsung.com> wrote:
> Hello,
>
> On Monday, June 21, 2010 11:06 AM Eric Miao wrote:
>
>> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com>
>> wrote:
>> > This patch adds samsung keypad device definition for samsung cpus.
>> >
>> > Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
>> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>> > ---
>> > ?arch/arm/plat-samsung/Kconfig ? ? ? ? ? ? ? ? ? ?| ? ?5 ++
>> > ?arch/arm/plat-samsung/Makefile ? ? ? ? ? ? ? ? ? | ? ?1 +
>> > ?arch/arm/plat-samsung/dev-keypad.c ? ? ? ? ? ? ? | ? 58
>> +++++++++++++++++++++
>>
>> Why need an individual file for a simple device? ?In the end, these files
>> will flood over the plat-samsung/ directory. And now think this - in your
>> new SoC design ,the keypad IP is replaced with a completely new one, does
>> that mean a new dev-keypad-new1.c, dev-keypad-new2.c?
>>
>> I personally prefer a single devices.c for all the devices, if you
>> orgnize well, shouldn't take up much code size in that single file.
>
> A separate dev-abc.c files has been chosen by a platform maintainer. This
> has some advantages as some unused data can be easily not compiled into
> the kernel which is configured specially for a particular board.

This also can be done by something like below:

#if defined(CONFIG_S5P_KEYPAD) || defined(CONFIG_S5P_KEYPAD_MODULE)
struct platform_device s5p_device_keypad {
        ........
};
#endif

And if you want run-time discardable platform_device, you have to mark
this structure as __initdata, and duplicate that device when registering.

That's why in arch/arm/mach-mmp/, a light weight and descriptive
'struct pxa_device_desc' is introduced, so only those platform_devices
registered will be generated and registered.


From eric.y.miao at gmail.com  Mon Jun 21 06:43:50 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 18:43:50 +0800
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <003701cb1124$3e335f00$ba9a1d00$%szyprowski@samsung.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com> 
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com> 
	<003701cb1124$3e335f00$ba9a1d00$%szyprowski@samsung.com>
Message-ID: <AANLkTiny_KNR0mZy9D52gZrGqJuYDPkK-P_zCFTfrAcm@mail.gmail.com>

On Mon, Jun 21, 2010 at 5:29 PM, Marek Szyprowski
<m.szyprowski at samsung.com> wrote:
> Hello,
>
> On Monday, June 21, 2010 11:06 AM Eric Miao wrote:
>
>> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com>
>> wrote:
>> > This patch adds samsung keypad device definition for samsung cpus.
>> >
>> > Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
>> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>> > ---
>> > ?arch/arm/plat-samsung/Kconfig ? ? ? ? ? ? ? ? ? ?| ? ?5 ++
>> > ?arch/arm/plat-samsung/Makefile ? ? ? ? ? ? ? ? ? | ? ?1 +
>> > ?arch/arm/plat-samsung/dev-keypad.c ? ? ? ? ? ? ? | ? 58
>> +++++++++++++++++++++
>>
>> Why need an individual file for a simple device? ?In the end, these files
>> will flood over the plat-samsung/ directory. And now think this - in your
>> new SoC design ,the keypad IP is replaced with a completely new one, does
>> that mean a new dev-keypad-new1.c, dev-keypad-new2.c?
>>
>> I personally prefer a single devices.c for all the devices, if you
>> orgnize well, shouldn't take up much code size in that single file.
>
> A separate dev-abc.c files has been chosen by a platform maintainer. This
> has some advantages as some unused data can be easily not compiled into
> the kernel which is configured specially for a particular board.

This also can be done by something like below:

#if defined(CONFIG_S5P_KEYPAD) || defined(CONFIG_S5P_KEYPAD_MODULE)
struct platform_device s5p_device_keypad {
        ........
};
#endif

And if you want run-time discardable platform_device, you have to mark
this structure as __initdata, and duplicate that device when registering.

That's why in arch/arm/mach-mmp/, a light weight and descriptive
'struct pxa_device_desc' is introduced, so only those platform_devices
registered will be generated and registered.


From jassisinghbrar at gmail.com  Mon Jun 21 07:16:45 2010
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Mon, 21 Jun 2010 20:16:45 +0900
Subject: Samsung SoCs naming rules
In-Reply-To: <AANLkTilnjN1dBWPKCuDt_bg8-5GEuSCrOh7vhqGf-VQU@mail.gmail.com>
References: <AANLkTiljyiQohHVJxUsn7Q6_IwTZk2AdNlLRxgGmxNpQ@mail.gmail.com>
	<AANLkTilnjN1dBWPKCuDt_bg8-5GEuSCrOh7vhqGf-VQU@mail.gmail.com>
Message-ID: <AANLkTilILGmuETQSpmLysNhbECwmciZZdxojLVHHbdzO@mail.gmail.com>

On Mon, Jun 21, 2010 at 7:36 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Mon, Jun 21, 2010 at 6:00 PM, Kyungmin Park <kmpark at infradead.org> wrote:
>> Dear all,
>>
>> Now Samsung SoCs doesn't have any special rules include chip name.
>>
>> Historically s5pc100 is successor form s3c6410 and this chip from
>> s3c2410 series.
>> on the other hand, s5pc110 (cortex a8) and s5pc64xx (armv6) is
>> different from previous chips.
>
> Don't be shy, Samsung is not the only vendor messes the naming of their
> SoCs. Marvell might have done a better job on this :-)
Actually the names are selected based upon a set of criteria such as target
market, technology etc. The chart used to be available online, don't remember
the location now.


From linux at arm.linux.org.uk  Mon Jun 21 07:16:12 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 12:16:12 +0100
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <AANLkTilU1X1LR33Eed9BVGE2n-dqRuIuUFfbDd3gzEVc@mail.gmail.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>
	<20100621091952.GB7702@n2100.arm.linux.org.uk>
	<AANLkTilU1X1LR33Eed9BVGE2n-dqRuIuUFfbDd3gzEVc@mail.gmail.com>
Message-ID: <20100621111612.GJ7702@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 06:39:10PM +0800, Eric Miao wrote:
> On Mon, Jun 21, 2010 at 5:19 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> > On Mon, Jun 21, 2010 at 05:05:34PM +0800, Eric Miao wrote:
> >> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
> >> > +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
> >> > +{
> >> > + ? ? ? struct samsung_keypad_platdata *npd;
> >> > +
> >> > + ? ? ? if (!pd) {
> >> > + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no platform data\n", __func__);
> >> > + ? ? ? ? ? ? ? return;
> >> > + ? ? ? }
> >> > +
> >> > + ? ? ? npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
> >> > + ? ? ? if (!npd)
> >> > + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no memory for platform data\n", __func__);
> >>
> >> This part of the code is actually duplicated again and again and again
> >> for each device, PXA and other legacy platforms are bad references for
> >> this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
> >> major points:
> >>
> >> ?1. A minimum 'struct pxa_device_desc' for a simple description of a
> >> ? ? device (more than 90% of the devices can be described that way),
> >> ? ? and avoid using a comparatively heavier weight platform_device,
> >> ? ? which can be generated at run-time
> >>
> >> ?2. pxa_register_device() to allocate and register the platform_device
> >> ? ? at run-time, along with the platform data
> >
> > It's a bad idea to make platform data be run-time discardable like this:
> >
> >> > +struct samsung_keypad_platdata {
> >> > + ? ? ? const struct matrix_keymap_data *keymap_data;
> >
> > What you end up with is some platform data structures which must be kept
> > (those which have pointers to them from the platform data), and others
> > (the platform data itself) which can be discarded at runtime.
> >
> > We know that the __initdata attributations cause lots of problems -
> > they're frequently wrong. ?Just see the constant hastle with __devinit
> > et.al. ?The same issue happens with __initdata as well.
> >
> > So why make things more complicated by allowing some platform data
> > structures to be discardable and others not to be? ?Is their small
> > size (maybe 6 words for this one) really worth the hastle of getting
> > __initdata attributations wrong (eg, on the keymap data?)
> >
> 
> Russell,
> 
> The benefit I see is when multiple boards are compiled in, those
> data not used can be automatically discarded.

Yes, but only some of the data can be discarded.  Continuing with the
example in hand, while you can discard the six words which represent
samsung_keypad_platdata, but the keymap_data can't be because that won't
be re-allocated, which is probably a much larger data structure.

So, samsung_keypad_platdata can be marked with __initdata, but the keymap
data must not be - and this is where the confusion about what can be
marked with __initdata starts - and eventually leads to the keymap data
also being mistakenly marked __initdata.

Is saving six words (or so) worth the effort to track down stuff
inappropriately marked with __initdata ?  I'm sure there's bigger savings
to be had in other parts of the kernel (such as shrinking the size of
tcp hash tables, reducing the kernel message ring buffer, etc) if size is
really a concern.


From jy0922.shim at samsung.com  Mon Jun 21 07:21:20 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Mon, 21 Jun 2010 20:21:20 +0900
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>
Message-ID: <4C1F4B30.3020006@samsung.com>

On 6/21/2010 6:05 PM, Eric Miao wrote:
> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>> This patch adds samsung keypad device definition for samsung cpus.
>>
>> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>> ---
>>  arch/arm/plat-samsung/Kconfig                    |    5 ++
>>  arch/arm/plat-samsung/Makefile                   |    1 +
>>  arch/arm/plat-samsung/dev-keypad.c               |   58 +++++++++++++++++++++
> 
> Why need an individual file for a simple device?  In the end, these files
> will flood over the plat-samsung/ directory. And now think this - in your
> new SoC design ,the keypad IP is replaced with a completely new one, does
> that mean a new dev-keypad-new1.c, dev-keypad-new2.c?
> 
> I personally prefer a single devices.c for all the devices, if you
> orgnize well, shouldn't take up much code size in that single file.
> 

I know, but will need more effort of other device as well as keypad to
do it.

>>  arch/arm/plat-samsung/include/plat/devs.h        |    2 +
>>  arch/arm/plat-samsung/include/plat/keypad.h      |   59 ++++++++++++++++++++++
>>  arch/arm/plat-samsung/include/plat/regs-keypad.h |   49 ++++++++++++++++++
> 
> Will these registers be used elsewhere except within the keypad driver?
> If no, they might be better moved to the keypad driver itself, it makes
> the driver more self-contained and avoid the registers being accessed
> anywhere.
> 

Right, these registers are used only in the keypad driver. I think it's 
possible.

>>  6 files changed, 174 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/plat-samsung/dev-keypad.c
>>  create mode 100644 arch/arm/plat-samsung/include/plat/keypad.h
>>  create mode 100644 arch/arm/plat-samsung/include/plat/regs-keypad.h
>>
>> diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
>> index 2753fb3..bd007e3 100644
>> --- a/arch/arm/plat-samsung/Kconfig
>> +++ b/arch/arm/plat-samsung/Kconfig
>> @@ -227,6 +227,11 @@ config SAMSUNG_DEV_TS
>>        help
>>            Common in platform device definitions for touchscreen device
>>
>> +config SAMSUNG_DEV_KEYPAD
>> +       bool
>> +       help
>> +         Compile in platform device definitions for keypad
>> +
>>  # DMA
>>
>>  config S3C_DMA
>> diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
>> index b1d82cc..8269d80 100644
>> --- a/arch/arm/plat-samsung/Makefile
>> +++ b/arch/arm/plat-samsung/Makefile
>> @@ -48,6 +48,7 @@ obj-$(CONFIG_S3C_DEV_RTC)     += dev-rtc.o
>>
>>  obj-$(CONFIG_SAMSUNG_DEV_ADC)  += dev-adc.o
>>  obj-$(CONFIG_SAMSUNG_DEV_TS)   += dev-ts.o
>> +obj-$(CONFIG_SAMSUNG_DEV_KEYPAD)       += dev-keypad.o
>>
>>  # DMA support
>>
>> diff --git a/arch/arm/plat-samsung/dev-keypad.c b/arch/arm/plat-samsung/dev-keypad.c
>> new file mode 100644
>> index 0000000..679b444
>> --- /dev/null
>> +++ b/arch/arm/plat-samsung/dev-keypad.c
>> @@ -0,0 +1,58 @@
>> +/*
>> + * linux/arch/arm/plat-samsung/dev-keypad.c
>> + *
>> + * Copyright (C) 2010 Samsung Electronics Co.Ltd
>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>> + *
>> + *  This program is free software; you can redistribute  it and/or modify it
>> + *  under  the terms of  the GNU General  Public License as published by the
>> + *  Free Software Foundation;  either version 2 of the  License, or (at your
>> + *  option) any later version.
>> + *
>> + */
>> +
>> +#include <linux/platform_device.h>
>> +#include <mach/irqs.h>
>> +#include <mach/map.h>
>> +#include <plat/cpu.h>
>> +#include <plat/devs.h>
>> +#include <plat/keypad.h>
>> +
>> +static struct resource samsung_keypad_resources[] = {
>> +       [0] = {
>> +               .start  = SAMSUNG_PA_KEYPAD,
>> +               .end    = SAMSUNG_PA_KEYPAD + 0x20 - 1,
>> +               .flags  = IORESOURCE_MEM,
>> +       },
>> +       [1] = {
>> +               .start  = IRQ_KEYPAD,
>> +               .end    = IRQ_KEYPAD,
>> +               .flags  = IORESOURCE_IRQ,
>> +       },
>> +};
>> +
>> +struct platform_device samsung_device_keypad = {
>> +       .name           = "samsung-keypad",
>> +       .id             = -1,
>> +       .num_resources  = ARRAY_SIZE(samsung_keypad_resources),
>> +       .resource       = samsung_keypad_resources,
>> +};
>> +
>> +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
>> +{
>> +       struct samsung_keypad_platdata *npd;
>> +
>> +       if (!pd) {
>> +               printk(KERN_ERR "%s: no platform data\n", __func__);
>> +               return;
>> +       }
>> +
>> +       npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
>> +       if (!npd)
>> +               printk(KERN_ERR "%s: no memory for platform data\n", __func__);
> 
> This part of the code is actually duplicated again and again and again
> for each device, PXA and other legacy platforms are bad references for
> this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
> major points:
> 

I know ben posted patches to remove duplicated codes such this.
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg01474.html

>  1. A minimum 'struct pxa_device_desc' for a simple description of a
>     device (more than 90% of the devices can be described that way),
>     and avoid using a comparatively heavier weight platform_device,
>     which can be generated at run-time
> 
>  2. pxa_register_device() to allocate and register the platform_device
>     at run-time, along with the platform data
> 
>  3. pxa168_add_*() as a consistent/clearly named API, and with type
>     checking for the platform_data type (it's a bit difficult to check
>     type in pxa_register_device())
> 
> Just for your reference.
> 
>> +
>> +       if (!npd->cfg_gpio)
>> +               npd->cfg_gpio = samsung_keypad_cfg_gpio;
> 
> More and more platforms are moving their IO-mux to a static descriptive
> array and have some API to configure. E.g. PXA, Orion/Kirkwood, iMX....
> The idea basically is:
> 
>   1) IO-Mux and the internal peripheral controller are conceptually
>      separate entities (the extreme case is the internal peripheral
>      controller can function normally even without IO-mux being setup
>      correct, only that signals not proplery routed in/out)
> 
>   2) IO-mux should be configured before the peripheral drivers are
>      ready to go (there are cases that IO-mux will have to be changed
>      at run-time, so IO-mux API should be able to handle that, though
>      such cases are rare)
> 
>   3) Peripheral drivers should not be concerned with IO-mux config
> 
> Not sure though how the IO-mux is designed in S5P, so treat the above
> as reference only.
> 

Hmm... i think it don't care to go to above reference.
Ben, what do you think about this?

>> +
>> +       samsung_device_keypad.dev.platform_data = npd;
>> +}
>> diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
>> index e6144e4..6d9f01b 100644
>> --- a/arch/arm/plat-samsung/include/plat/devs.h
>> +++ b/arch/arm/plat-samsung/include/plat/devs.h
>> @@ -100,6 +100,8 @@ extern struct platform_device s5pc100_device_iis0;
>>  extern struct platform_device s5pc100_device_iis1;
>>  extern struct platform_device s5pc100_device_iis2;
>>
>> +extern struct platform_device samsung_device_keypad;
>> +
>>  /* s3c2440 specific devices */
>>
>>  #ifdef CONFIG_CPU_S3C2440
>> diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/plat-samsung/include/plat/keypad.h
>> new file mode 100644
>> index 0000000..6d139d6
>> --- /dev/null
>> +++ b/arch/arm/plat-samsung/include/plat/keypad.h
>> @@ -0,0 +1,59 @@
>> +/*
>> + * linux/arch/arm/plat-samsung/include/plat/keypad.h
>> + *
>> + * Copyright (C) 2010 Samsung Electronics Co.Ltd
>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>> + *
>> + * Samsung Platform - Keypad platform data definitions
>> + *
>> + *  This program is free software; you can redistribute  it and/or modify it
>> + *  under  the terms of  the GNU General  Public License as published by the
>> + *  Free Software Foundation;  either version 2 of the  License, or (at your
>> + *  option) any later version.
>> + *
>> + */
>> +
>> +#ifndef __PLAT_SAMSUNG_KEYPAD_H
>> +#define __PLAT_SAMSUNG_KEYPAD_H
>> +
>> +#include <linux/input/matrix_keypad.h>
>> +
>> +#define SAMSUNG_MAX_ROWS       8
>> +#define SAMSUNG_MAX_COLS       8
>> +
>> +/**
>> + * struct samsung_keypad_platdata - Platform device data for Samsung Keypad.
>> + * @keymap_data: pointer to &matrix_keymap_data.
>> + * @rows: number of keypad row supported.
>> + * @cols: number of keypad col supported.
>> + * @no_autorepeat: disable key autorepeat.
>> + * @wakeup: controls whether the device should be set up as wakeup source.
>> + * @cfg_gpio: configure the GPIO.
>> + *
>> + * Initialisation data specific to either the machine or the platform
>> + * for the device driver to use or call-back when configuring gpio.
>> + */
>> +struct samsung_keypad_platdata {
>> +       const struct matrix_keymap_data *keymap_data;
>> +       unsigned int            rows;
>> +       unsigned int            cols;
>> +       bool                    no_autorepeat;
>> +       bool                    wakeup;
>> +
>> +       void    (*cfg_gpio)(unsigned int rows, unsigned int cols);
>> +};
> 
> Why are you calling everything samsung_this, samsung_that? Now think about:
> 
>   1. Is this keypad applicable to all Samsung silicon?
>   2. Samsung has a new IP for the keypad, now what? samsung_new_keypad_platdata?
> 
> s5p_keypad sounds more reasable to me if it's applicable to all the s5p
> series. Now I also doubt that's the case. So normally, we will name it
> after the first silicon where this IP appears, e.g.
> 
>   s5pc100_keypad
> 
> and now in s5pc200 code, you can also register/re-use the s5pc100_keypad
> device/driver, and everyone knows - OK, the IP on S5PC100 is now re-used
> here.
> 

This is naming issue and i know it was not desided yet. 
This keypad driver can support s3c64xx, s5pc100, s5pc110, s5pv210. 

>> +
>> +/**
>> + * samsung_keypad_set_platdata - Set platform data for Samsung Keypad device.
>> + * @pd: Platform data to register to device.
>> + *
>> + * Register the given platform data for use with Samsung Keypad device.
>> + * The call will copy the platform data, so the board definitions can
>> + * make the structure itself __initdata.
>> + */
>> +extern void samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd);
>> +
>> +/* defined by architecture to configure gpio. */
>> +extern void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols);
>> +
>> +#endif /* __PLAT_SAMSUNG_KEYPAD_H */
>> diff --git a/arch/arm/plat-samsung/include/plat/regs-keypad.h b/arch/arm/plat-samsung/include/plat/regs-keypad.h
>> new file mode 100644
>> index 0000000..e4688f0
>> --- /dev/null
>> +++ b/arch/arm/plat-samsung/include/plat/regs-keypad.h
>> @@ -0,0 +1,49 @@
>> +/*
>> + * linux/arch/arm/plat-samsung/include/plat/regs-keypad.h
>> + *
>> + * Copyright (C) 2010 Samsung Electronics Co.Ltd
>> + * Author: Joonyoung Shim <jy0922.shim at samsung.com>
>> + *
>> + *  This program is free software; you can redistribute  it and/or modify it
>> + *  under  the terms of  the GNU General  Public License as published by the
>> + *  Free Software Foundation;  either version 2 of the  License, or (at your
>> + *  option) any later version.
>> + *
>> + */
>> +
>> +#ifndef __SAMSUNG_KEYPAD_H__
>> +#define __SAMSUNG_KEYPAD_H__
>> +
>> +#define SAMSUNG_KEYIFCON                       0x00
>> +#define SAMSUNG_KEYIFSTSCLR                    0x04
>> +#define SAMSUNG_KEYIFCOL                       0x08
>> +#define SAMSUNG_KEYIFROW                       0x0c
>> +#define SAMSUNG_KEYIFFC                                0x10
>> +
>> +/* SAMSUNG_KEYIFCON */
>> +#define SAMSUNG_KEYIFCON_INT_F_EN              (1 << 0)
>> +#define SAMSUNG_KEYIFCON_INT_R_EN              (1 << 1)
>> +#define SAMSUNG_KEYIFCON_DF_EN                 (1 << 2)
>> +#define SAMSUNG_KEYIFCON_FC_EN                 (1 << 3)
>> +#define SAMSUNG_KEYIFCON_WAKEUPEN              (1 << 4)
>> +
>> +/* SAMSUNG_KEYIFSTSCLR */
>> +#define SAMSUNG_KEYIFSTSCLR_P_INT_MASK         (0xff << 0)
>> +#define SAMSUNG_KEYIFSTSCLR_R_INT_MASK         (0xff << 8)
>> +#define SAMSUNG_KEYIFSTSCLR_R_INT_OFFSET       8
>> +#define S5PV210_KEYIFSTSCLR_P_INT_MASK         (0x3fff << 0)
>> +#define S5PV210_KEYIFSTSCLR_R_INT_MASK         (0x3fff << 16)
>> +#define S5PV210_KEYIFSTSCLR_R_INT_OFFSET       16
>> +
>> +/* SAMSUNG_KEYIFCOL */
>> +#define SAMSUNG_KEYIFCOL_MASK                  (0xff << 0)
>> +#define S5PV210_KEYIFCOLEN_MASK                        (0xff << 8)
>> +
>> +/* SAMSUNG_KEYIFROW */
>> +#define SAMSUNG_KEYIFROW_MASK                  (0xff << 0)
>> +#define S5PV210_KEYIFROW_MASK                  (0x3fff << 0)
>> +
>> +/* SAMSUNG_KEYIFFC */
>> +#define SAMSUNG_KEYIFFC_MASK                   (0x3ff << 0)
>> +
>> +#endif /* __SAMSUNG_KEYPAD_H__ */
>> --
>> 1.7.0.4
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel



From ivo.clarysse at gmail.com  Mon Jun 21 07:47:41 2010
From: ivo.clarysse at gmail.com (Ivo Clarysse)
Date: Mon, 21 Jun 2010 13:47:41 +0200
Subject: [PATCHv2 4/5] mtd: mxc_nand fixups
In-Reply-To: <80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>
References: <804oh0b7gx.fsf@merkur.tec.linutronix.de>
	<20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
	<AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
	<80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>
Message-ID: <AANLkTikRj_dMkKLyFhW78yld9jIYAIFncfPaPAF8WqUY@mail.gmail.com>

On Sun, Jun 20, 2010 at 11:21 AM, John Ogness <john.ogness at linutronix.de> wrote:
>
> On 2010-06-20, Ivo Clarysse <ivo.clarysse at gmail.com> wrote:
> > Yes, on i.MX21, NFC interrupts can be masked using
> > NFC_CONFIG1:NFC_INT_MSK. ?But I observed that as long as NFC_INT_MSK
> > is set, NFC_CONFIG2:NFC_INT will always read out 0 on i.MX21, even if
> > the operation is completed.
> >
> > So the driver will remain stuck at:
> >
> > ? ? ? ? ? ? ? ? ?wait_event(host->irq_waitq,
> > ? ? ? ? ? ? ? ? ? ? ? ? ?readw(host->regs + NFC_CONFIG2) & NFC_INT);
>
> OK. Here is alternative patch. Do you have access to an i.MX21 to test
> this on?
>
> This patch fixes the driver so that the irq is requested as disabled. This
> prevents double irq enabling and also does not require the interrupt to
> be disabled within the interrupt handler. (Actually, I beleive this was
> the true intention of the original author.)
[...]

Yes, that was indeed my true intention :)

I tested this change on an MX21ADS board.

Acked-by: Ivo Clarysse <ivo.clarysse at gmail.com>


From benjamin.zores at alcatel-lucent.com  Mon Jun 21 08:08:55 2010
From: benjamin.zores at alcatel-lucent.com (Benjamin Zores)
Date: Mon, 21 Jun 2010 14:08:55 +0200
Subject: [PATCH 1/4] arch/arm/mach-kirkwood: update MPP definition.
In-Reply-To: <20100617075858.15387.93749.stgit@localhost.localdomain>
References: <20100617075711.15387.69398.stgit@localhost.localdomain>
	<20100617075858.15387.93749.stgit@localhost.localdomain>
Message-ID: <4C1F5657.9000800@alcatel-lucent.com>

On 17/06/2010 09:58, Benjamin Zores wrote:
> Add MPP definitions for Marvell Kirkwood 88F6282 revision.
> Update some defines to reflect datasheet's MPP names.
>    

Marvell published an errata note regarding 6282 MPPs.
Attached is a slightly modified patch (for MPP49, others were ok).

Nicolas, Catalin, can you merge the 4 patches to your tree ?

Ben
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From catalin.marinas at arm.com  Mon Jun 21 08:23:23 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 13:23:23 +0100
Subject: [PATCH 0/2] Barrier changes with !ARM_DMA_MEM_BUFFERABLE
Message-ID: <20100621115703.7162.95491.stgit@e102109-lin.cambridge.arm.com>

The patches are relatively simple but without them the RealView boards
cannot be used with L210/L220 enabled (hardware deadlock, not a software
issue).

Catalin Marinas (2):
      ARM: Do not use outer_sync() in mb() if !ARM_DMA_MEM_BUFFERABLE
      ARM: Do not enable ARM_DMA_MEM_BUFFERABLE for some RealView boards


 arch/arm/include/asm/system.h |    6 +++++-
 arch/arm/mm/Kconfig           |    2 ++
 2 files changed, 7 insertions(+), 1 deletions(-)

-- 
Catalin


From catalin.marinas at arm.com  Mon Jun 21 08:23:29 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 13:23:29 +0100
Subject: [PATCH 1/2] ARM: Do not use outer_sync() in mb() if
	!ARM_DMA_MEM_BUFFERABLE
In-Reply-To: <20100621115703.7162.95491.stgit@e102109-lin.cambridge.arm.com>
References: <20100621115703.7162.95491.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621122329.7162.61895.stgit@e102109-lin.cambridge.arm.com>

This patch changes the mb() barrier implementation for the
!ARM_DMA_MEM_BUFFERABLE case so that it no longer performs an outer
cache sync. When this is option is disabled, the coherent DMA buffers
are mapped as Strongly Ordered and there is no need for an L2 cache
sync.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/system.h |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 5f4f480..3b2abcf 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -141,10 +141,14 @@ extern unsigned int user_debug;
 
 #ifdef CONFIG_ARCH_HAS_BARRIERS
 #include <mach/barriers.h>
-#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
+#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE)
 #define mb()		do { dsb(); outer_sync(); } while (0)
 #define rmb()		dmb()
 #define wmb()		mb()
+#elif defined(CONFIG_SMP)
+#define mb()		dsb()
+#define rmb()		dmb()
+#define wmb()		mb()
 #else
 #define mb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
 #define rmb()	do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)



From catalin.marinas at arm.com  Mon Jun 21 08:23:35 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 13:23:35 +0100
Subject: [PATCH 2/2] ARM: Do not enable ARM_DMA_MEM_BUFFERABLE for some
	RealView boards
In-Reply-To: <20100621115703.7162.95491.stgit@e102109-lin.cambridge.arm.com>
References: <20100621115703.7162.95491.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621122335.7162.55877.stgit@e102109-lin.cambridge.arm.com>

RealView boards with certain revisions of the L210/L220 cache controller
may have issues with recent changes to the mb() barrier implementation
(DSB followed by an L2 cache sync). The patch disables
ARM_DMA_MEM_BUFFERABLE for some of the RealView boards with L210/L220.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/mm/Kconfig |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index fc1b2fa..101105e 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -813,6 +813,8 @@ config ARM_L1_CACHE_SHIFT
 
 config ARM_DMA_MEM_BUFFERABLE
 	bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
+	depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
+		     MACH_REALVIEW_PB11MP)
 	default y if CPU_V6 || CPU_V7
 	help
 	  Historically, the kernel has used strongly ordered mappings to



From hongjiujing at gmail.com  Mon Jun 21 06:45:25 2010
From: hongjiujing at gmail.com (tommy.hong)
Date: Mon, 21 Jun 2010 18:45:25 +0800
Subject: Samsung SoCs naming rules
In-Reply-To: <AANLkTinMVzettYAHjnslYFAmxD2rmGS8FgoJu9KLaUdL@mail.gmail.com>
References: <AANLkTiljyiQohHVJxUsn7Q6_IwTZk2AdNlLRxgGmxNpQ@mail.gmail.com>
	<AANLkTilnjN1dBWPKCuDt_bg8-5GEuSCrOh7vhqGf-VQU@mail.gmail.com>
	<AANLkTinMVzettYAHjnslYFAmxD2rmGS8FgoJu9KLaUdL@mail.gmail.com>
Message-ID: <AANLkTinxcGeTSOVsNqjY_pJMEhjVLLjOzkF8Nm4l3tp0@mail.gmail.com>

I agree eric,also TI OMAP naming is a good example,you can use
s3c-armv6,s3c-armv7 ?just make people clear of ARM instruction version?

Tommy

2010/6/21 tommy.hong <hongjiujing at gmail.com>

> I agree eric,also TI OMAP naming is a good example,you can use
> s3c-armv6,s3c-armv7 ?just make people clear of ARM instruction version?
>
>
>
> Tommy
>
> 2010/6/21 Eric Miao <eric.y.miao at gmail.com>
>
> On Mon, Jun 21, 2010 at 6:00 PM, Kyungmin Park <kmpark at infradead.org>
>> wrote:
>> > Dear all,
>> >
>> > Now Samsung SoCs doesn't have any special rules include chip name.
>> >
>> > Historically s5pc100 is successor form s3c6410 and this chip from
>> > s3c2410 series.
>> > on the other hand, s5pc110 (cortex a8) and s5pc64xx (armv6) is
>> > different from previous chips.
>>
>> Don't be shy, Samsung is not the only vendor messes the naming of their
>> SoCs. Marvell might have done a better job on this :-)
>>
>> >
>> > So it's not good idea grouping with the prefix. e.g., s5p series. and
>> > the reason to create the samsung.
>> >
>>
>> My guess is your s5p will focus more on Cortex-A8 (or A9 possibly),
>> even with subsequent processors. And only s5pc100 is an exception,
>> that's fine, you can still put s5pc100 into mach-s3c6410, and people
>> will know it's actually closer to s3c6410. And other SoCs will share the
>> common s5p prefix.
>>
>> > we tried to find a common name several times but failed to get proper
>> > name, I hope community give good name rules.
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
>
>
>
> --
> concentrate for work && keep calm and carry on,Achievement provides the
> only real pleasure in life!
>



-- 
concentrate for work && keep calm and carry on,Achievement provides the only
real pleasure in life!
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From nicolas.ferre at atmel.com  Mon Jun 21 08:55:30 2010
From: nicolas.ferre at atmel.com (Nicolas Ferre)
Date: Mon, 21 Jun 2010 14:55:30 +0200
Subject: [PATCH] AT91: PM: dual ram controller support
In-Reply-To: <1273492287-7647-1-git-send-email-nicolas.ferre@atmel.com>
References: <1273492287-7647-1-git-send-email-nicolas.ferre@atmel.com>
Message-ID: <4C1F6142.3050004@atmel.com>

Le 10/05/2010 13:51, Nicolas Ferre :
> This rework allows to address tow memory controllers. AT91SAM9263 and
> AT91SAM9G45 family have tow SDRAM or DDR/SDRAM controllers. Power management
> should take care of this.
> This patch modify the way RAM IP header files are implemented to allow
> access to registers of both controllers ; it also adds some macros.
> 
> We also modify the power management files to use those modified header files.
> Slow clock (assembly) and regular power management functions are synchronized
> for setting of RAM self-refresh procedure: 
> (lpr & ~AT91_DDRSDRC_LPCB) | AT91_DDRSDRC_LPCB_SELF_REFRESH

Queued as patch 6185/1 with Ack from Andrew Victor.

http://www.arm.linux.org.uk/developer/patches/viewpatch.php?id=6185/1

Best regards,
-- 
Nicolas Ferre



From linux at arm.linux.org.uk  Mon Jun 21 09:19:03 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 14:19:03 +0100
Subject: [PATCH v4 0/8] Patches/fixes for 2.6.35
In-Reply-To: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
References: <20100621102639.9353.37648.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621131903.GA13624@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 11:29:29AM +0100, Catalin Marinas wrote:
> Updates from version 3 of these series:
> 
> - noMMU warning patch changed by moving the CONSISTENT_* definitions to
>   the CONFIG_MMU section
> - .phys_io alignment patch replaced by two patches that enforce the
>   alignment in the machine_desc structures for VExpress and RealView
> - commit log added to the T2 module relocations patch

Ok.


From tony at atomide.com  Mon Jun 21 09:51:13 2010
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 21 Jun 2010 16:51:13 +0300
Subject: [PATCH 0/2] Make ARMv6 behave with TLS, VFPv3, and NEON
Message-ID: <20100621133749.24299.36154.stgit@baageli.muru.com>

Hi all,

Here is an updated version of the earlier patch for the TLS [1], and a related
patch for VFPv3 and NEON. Sorry it took a while before I got around updating
this patch.

This series allows booting ARMv6 and 7 with the same kernel binary, such as
omap24xx (ARMv6), omap34xx (ARMv7) and omap44xx (ARMv7 SMP).

To summarize the problem, ARM1136 has TLS and MVFR registers only starting with
r1 p0, and at least omap2420 is earlier at r0 p2 and does not have TLS or
MVFR registers.

Regards,

Tony


[1] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6
    http://lists.infradead.org/pipermail/linux-arm-kernel/2010-March/011667.html

---

Tony Lindgren (2):
      arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6
      arm: Make VFPv3 usable on ARMv6


 arch/arm/include/asm/hwcap.h     |    1 +
 arch/arm/include/asm/vfpmacros.h |   18 ++++++++++++++++++
 arch/arm/kernel/entry-armv.S     |   29 ++++++++++++++---------------
 arch/arm/kernel/setup.c          |   20 ++++++++++++++++++++
 arch/arm/kernel/traps.c          |   23 +++++++++++++----------
 arch/arm/mm/Kconfig              |   11 -----------
 arch/arm/mm/proc-v6.S            |    6 ++++--
 arch/arm/mm/proc-v7.S            |    2 +-
 arch/arm/vfp/vfpmodule.c         |   10 +++++++---
 9 files changed, 78 insertions(+), 42 deletions(-)

-- 
Signature


From tony at atomide.com  Mon Jun 21 09:51:20 2010
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 21 Jun 2010 16:51:20 +0300
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check
	for it on V6
In-Reply-To: <20100621133749.24299.36154.stgit@baageli.muru.com>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
Message-ID: <20100621135120.24299.98499.stgit@baageli.muru.com>

The TLS register is only available on ARM1136 r1p0 and later.
Set HWCAP_TLS flags if hardware TLS is available.

Note that we now use 0xffff0ff4 for flagging software TLS to
__kuser_get_tls, and 0xffff0ff8 for storing the software TLS value.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/include/asm/hwcap.h |    1 +
 arch/arm/kernel/entry-armv.S |   29 ++++++++++++++---------------
 arch/arm/kernel/setup.c      |   20 ++++++++++++++++++++
 arch/arm/kernel/traps.c      |   23 +++++++++++++----------
 arch/arm/mm/Kconfig          |   11 -----------
 arch/arm/mm/proc-v6.S        |    6 ++++--
 arch/arm/mm/proc-v7.S        |    2 +-
 7 files changed, 53 insertions(+), 39 deletions(-)

diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index f7bd52b..c1062c3 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -19,6 +19,7 @@
 #define HWCAP_NEON	4096
 #define HWCAP_VFPv3	8192
 #define HWCAP_VFPv3D16	16384
+#define HWCAP_TLS	32768
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 /*
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 7ee48e7..9de5357 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -739,11 +739,14 @@ ENTRY(__switch_to)
 #ifdef CONFIG_MMU
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
-#if defined(CONFIG_HAS_TLS_REG)
-	mcr	p15, 0, r3, c13, c0, 3		@ set TLS register
-#elif !defined(CONFIG_TLS_REG_EMUL)
-	mov	r4, #0xffff0fff
-	str	r3, [r4, #-15]			@ TLS val at 0xffff0ff0
+#if !defined(CONFIG_TLS_REG_EMUL)
+	ldr	r4, =elf_hwcap
+	ldr	r4, [r4, #0]
+	mov	r5, #0xffff0fff
+	tst	r4, #HWCAP_TLS			@ hardware TLS available?
+	mcrne	p15, 0, r3, c13, c0, 3		@ yes, set TLS register
+	streq	r5, [r5, #-11]			@ flag software TLS at 0xffff0ff4
+	streq	r3, [r5, #-7]			@ set TLS value at 0xffff0ff8
 #endif
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r6, c3, c0, 0		@ Set domain register
@@ -1009,17 +1012,13 @@ kuser_cmpxchg_fixup:
  */
 
 __kuser_get_tls:				@ 0xffff0fe0
-
-#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
-	ldr	r0, [pc, #(16 - 8)]		@ TLS stored at 0xffff0ff0
-#else
-	mrc	p15, 0, r0, c13, c0, 3		@ read TLS register
-#endif
+	ldr     r0, [pc, #(20 - 8)]		@ software TLS set in 0xffff0ff4?
+	cmp	r0, #0				@ hardware TLS if flag not set
+	mrceq	p15, 0, r0, c13, c0, 3		@ read hardware TLS register
+	ldrne	r0, [pc, #(12 - 8)]		@ software TLS val at 0xffff0ff8
 	usr_ret	lr
-
-	.rep	5
-	.word	0			@ pad up to __kuser_helper_version
-	.endr
+	.word	0				@ non-zero for software TLS
+	.word	0				@ software TLS value
 
 /*
  * Reference declaration:
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 122d999..fcfa9c2 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -269,6 +269,24 @@ static void __init cacheid_init(void)
 extern struct proc_info_list *lookup_processor_type(unsigned int);
 extern struct machine_desc *lookup_machine_type(unsigned int);
 
+#ifdef CONFIG_CPU_V6
+static void __init feat_v6_fixup(void)
+{
+	int id = read_cpuid_id();
+
+	if (id & 0x000f0000 != 0x00070000)
+		return;
+
+	/* HWCAP_TLS is available only on V6 r1p0 and later */
+	if (((id >> 20) & 3) == 0)
+		elf_hwcap &= ~HWCAP_TLS;
+}
+#else
+static inline void feat_v6_fixup(void)
+{
+}
+#endif
+
 static void __init setup_processor(void)
 {
 	struct proc_info_list *list;
@@ -311,6 +329,8 @@ static void __init setup_processor(void)
 	elf_hwcap &= ~HWCAP_THUMB;
 #endif
 
+	feat_v6_fixup();
+
 	cacheid_init();
 	cpu_proc_init();
 }
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1621e53..3dd72b7 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -518,16 +518,19 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 
 	case NR(set_tls):
 		thread->tp_value = regs->ARM_r0;
-#if defined(CONFIG_HAS_TLS_REG)
-		asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
-#elif !defined(CONFIG_TLS_REG_EMUL)
-		/*
-		 * User space must never try to access this directly.
-		 * Expect your app to break eventually if you do so.
-		 * The user helper at 0xffff0fe0 must be used instead.
-		 * (see entry-armv.S for details)
-		 */
-		*((unsigned int *)0xffff0ff0) = regs->ARM_r0;
+#if !defined(CONFIG_TLS_REG_EMUL)
+		if (elf_hwcap & HWCAP_TLS) {
+			asm ("mcr p15, 0, %0, c13, c0, 3"
+				: : "r" (regs->ARM_r0));
+		} else {
+			/*
+			 * User space must never try to access this directly.
+			 * Expect your app to break eventually if you do so.
+			 * The user helper at 0xffff0fe0 must be used instead.
+			 * (see entry-armv.S for details)
+			 */
+			*((unsigned int *)0xffff0ff8) = regs->ARM_r0;
+		}
 #endif
 		return 0;
 
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..71d5d5e 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -717,17 +717,6 @@ config TLS_REG_EMUL
 	  a few prototypes like that in existence) and therefore access to
 	  that required register must be emulated.
 
-config HAS_TLS_REG
-	bool
-	depends on !TLS_REG_EMUL
-	default y if SMP || CPU_32v7
-	help
-	  This selects support for the CP15 thread register.
-	  It is defined to be available on some ARMv6 processors (including
-	  all SMP capable ARMv6's) or later processors.  User space may
-	  assume directly accessing that register and always obtain the
-	  expected value only on ARMv7 and above.
-
 config NEEDS_SYSCALL_FOR_CMPXCHG
 	bool
 	help
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 7a5337e..e10626a 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -239,7 +239,8 @@ __v6_proc_info:
 	b	__v6_setup
 	.long	cpu_arch_name
 	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
+	/* See also feat_v6_fixup() for HWCAP_TLS */
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
 	.long	cpu_v6_name
 	.long	v6_processor_functions
 	.long	v6wbi_tlb_fns
@@ -262,7 +263,8 @@ __pj4_v6_proc_info:
 	b	__v6_setup
 	.long	cpu_arch_name
 	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+	/* See also feat_v6_fixup() for HWCAP_TLS */
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
 	.long	cpu_pj4_name
 	.long	v6_processor_functions
 	.long	v6wbi_tlb_fns
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a..8071bcd 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -344,7 +344,7 @@ __v7_proc_info:
 	b	__v7_setup
 	.long	cpu_arch_name
 	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
 	.long	cpu_v7_name
 	.long	v7_processor_functions
 	.long	v7wbi_tlb_fns



From tony at atomide.com  Mon Jun 21 09:51:25 2010
From: tony at atomide.com (Tony Lindgren)
Date: Mon, 21 Jun 2010 16:51:25 +0300
Subject: [PATCH 2/2] arm: Make VFPv3 usable on ARMv6
In-Reply-To: <20100621133749.24299.36154.stgit@baageli.muru.com>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
Message-ID: <20100621135125.24299.91290.stgit@baageli.muru.com>

MVFR0 and MVFR1 are only available starting with ARM1136 r1p0 release
according to "B.5 VFP changes" in DDI0211F_arm1136_r1p0_trm.pdf. This is
also when TLS register got added, so we can use HAS_TLS also to test for
MVFR0 and MVFR1.

Otherwise VFPFMRX and VFPFMXR access fails and we get:

Internal error: Oops - undefined instruction: 0 [#1]
PC is at no_old_VFP_process+0x8/0x3c
LR is at __und_svc+0x48/0x80
...

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/include/asm/vfpmacros.h |   18 ++++++++++++++++++
 arch/arm/vfp/vfpmodule.c         |   10 +++++++---
 2 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/arch/arm/include/asm/vfpmacros.h b/arch/arm/include/asm/vfpmacros.h
index 422f3cc..3d5fc41 100644
--- a/arch/arm/include/asm/vfpmacros.h
+++ b/arch/arm/include/asm/vfpmacros.h
@@ -3,6 +3,8 @@
  *
  * Assembler-only file containing VFP macros and register definitions.
  */
+#include <asm/hwcap.h>
+
 #include "vfp.h"
 
 @ Macros to allow building with old toolkits (with no VFP support)
@@ -22,12 +24,20 @@
 	LDC	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+#if __LINUX_ARM_ARCH__ <= 6
+	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs
+	ldr	\tmp, [\tmp, #0]
+	tst	\tmp, #HWCAP_VFPv3D16
+	ldceq	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}
+	addne	\base, \base, #32*4		    @ step over unused register space
+#else
 	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0
 	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field
 	cmp	\tmp, #2			    @ 32 x 64bit registers?
 	ldceql	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}
 	addne	\base, \base, #32*4		    @ step over unused register space
 #endif
+#endif
 	.endm
 
 	@ write all the working registers out of the VFP
@@ -38,10 +48,18 @@
 	STC	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d0-d15}
 #endif
 #ifdef CONFIG_VFPv3
+#if __LINUX_ARM_ARCH__ <= 6
+	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs
+	ldr	\tmp, [\tmp, #0]
+	tst	\tmp, #HWCAP_VFPv3D16
+	stceq	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}
+	addne	\base, \base, #32*4		    @ step over unused register space
+#else
 	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0
 	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field
 	cmp	\tmp, #2			    @ 32 x 64bit registers?
 	stceql	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}
 	addne	\base, \base, #32*4		    @ step over unused register space
 #endif
+#endif
 	.endm
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 315a540..19ba626 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -549,10 +549,14 @@ static int __init vfp_init(void)
 		/*
 		 * Check for the presence of the Advanced SIMD
 		 * load/store instructions, integer and single
-		 * precision floating point operations.
+		 * precision floating point operations. Only check
+		 * for NEON if the hardware has TLS register as the
+		 * MVFR registers got added in ARM1136 r1p0 with TLS.
 		 */
-		if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
-			elf_hwcap |= HWCAP_NEON;
+		if (elf_hwcap & HWCAP_TLS) {
+			if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
+				elf_hwcap |= HWCAP_NEON;
+		}
 #endif
 	}
 	return 0;



From eric.y.miao at gmail.com  Mon Jun 21 10:15:42 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 22:15:42 +0800
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <20100621111612.GJ7702@n2100.arm.linux.org.uk>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com> 
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com> 
	<20100621091952.GB7702@n2100.arm.linux.org.uk>
	<AANLkTilU1X1LR33Eed9BVGE2n-dqRuIuUFfbDd3gzEVc@mail.gmail.com> 
	<20100621111612.GJ7702@n2100.arm.linux.org.uk>
Message-ID: <AANLkTin2ap24Jn38eXx3uHLiJ32otXA6PgtL-yORU7sr@mail.gmail.com>

On Mon, Jun 21, 2010 at 7:16 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, Jun 21, 2010 at 06:39:10PM +0800, Eric Miao wrote:
>> On Mon, Jun 21, 2010 at 5:19 PM, Russell King - ARM Linux
>> <linux at arm.linux.org.uk> wrote:
>> > On Mon, Jun 21, 2010 at 05:05:34PM +0800, Eric Miao wrote:
>> >> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>> >> > +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
>> >> > +{
>> >> > + ? ? ? struct samsung_keypad_platdata *npd;
>> >> > +
>> >> > + ? ? ? if (!pd) {
>> >> > + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no platform data\n", __func__);
>> >> > + ? ? ? ? ? ? ? return;
>> >> > + ? ? ? }
>> >> > +
>> >> > + ? ? ? npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
>> >> > + ? ? ? if (!npd)
>> >> > + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no memory for platform data\n", __func__);
>> >>
>> >> This part of the code is actually duplicated again and again and again
>> >> for each device, PXA and other legacy platforms are bad references for
>> >> this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
>> >> major points:
>> >>
>> >> ?1. A minimum 'struct pxa_device_desc' for a simple description of a
>> >> ? ? device (more than 90% of the devices can be described that way),
>> >> ? ? and avoid using a comparatively heavier weight platform_device,
>> >> ? ? which can be generated at run-time
>> >>
>> >> ?2. pxa_register_device() to allocate and register the platform_device
>> >> ? ? at run-time, along with the platform data
>> >
>> > It's a bad idea to make platform data be run-time discardable like this:
>> >
>> >> > +struct samsung_keypad_platdata {
>> >> > + ? ? ? const struct matrix_keymap_data *keymap_data;
>> >
>> > What you end up with is some platform data structures which must be kept
>> > (those which have pointers to them from the platform data), and others
>> > (the platform data itself) which can be discarded at runtime.
>> >
>> > We know that the __initdata attributations cause lots of problems -
>> > they're frequently wrong. ?Just see the constant hastle with __devinit
>> > et.al. ?The same issue happens with __initdata as well.
>> >
>> > So why make things more complicated by allowing some platform data
>> > structures to be discardable and others not to be? ?Is their small
>> > size (maybe 6 words for this one) really worth the hastle of getting
>> > __initdata attributations wrong (eg, on the keymap data?)
>> >
>>
>> Russell,
>>
>> The benefit I see is when multiple boards are compiled in, those
>> data not used can be automatically discarded.
>
> Yes, but only some of the data can be discarded. ?Continuing with the
> example in hand, while you can discard the six words which represent
> samsung_keypad_platdata, but the keymap_data can't be because that won't
> be re-allocated, which is probably a much larger data structure.
>
> So, samsung_keypad_platdata can be marked with __initdata, but the keymap
> data must not be - and this is where the confusion about what can be
> marked with __initdata starts - and eventually leads to the keymap data
> also being mistakenly marked __initdata.

Indeed. One ideal solution would be to make all the board code into
a module, yet since some of the code should be executed really
early and need to stay as built-in, looks like we need a way to
separate these two parts.

>
> Is saving six words (or so) worth the effort to track down stuff
> inappropriately marked with __initdata ? ?I'm sure there's bigger savings
> to be had in other parts of the kernel (such as shrinking the size of
> tcp hash tables, reducing the kernel message ring buffer, etc) if size is
> really a concern.
>

That's true, however, I think the size will become a bit more significant
if more and more board code is compiled into a single kernel.


From eric.y.miao at gmail.com  Mon Jun 21 10:19:55 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 22:19:55 +0800
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <4C1F4B30.3020006@samsung.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com> 
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com> 
	<4C1F4B30.3020006@samsung.com>
Message-ID: <AANLkTimhik3BOQNzybs1tUuHUXri-yxm5v7wH1JjQ5B1@mail.gmail.com>

>> and now in s5pc200 code, you can also register/re-use the s5pc100_keypad
>> device/driver, and everyone knows - OK, the IP on S5PC100 is now re-used
>> here.
>>
>
> This is naming issue and i know it was not desided yet.
> This keypad driver can support s3c64xx, s5pc100, s5pc110, s5pv210.
>

I bet the first silicon this IP is deployed is s3c64xx, so my understanding
's3c64xx-keypad.c' should be an acceptable name.  And it's also reasonable,
a s3c64xx-keypad driver, and is later expanded to support subsequent silicons
without the file name being changed.


From anarsoul at gmail.com  Mon Jun 21 10:21:32 2010
From: anarsoul at gmail.com (Vasily Khoruzhick)
Date: Mon, 21 Jun 2010 17:21:32 +0300
Subject: [PATCH] h1940: implement mmc_power function
In-Reply-To: <1276346763-29309-1-git-send-email-anarsoul@gmail.com>
References: <1276346763-29309-1-git-send-email-anarsoul@gmail.com>
Message-ID: <201006211721.48347.anarsoul@gmail.com>

? ????????? ?? 12 ???? 2010 15:46:03 ????? Vasily Khoruzhick ???????:
> Signed-off-by: Vasily Khoruzhick <anarsoul at gmail.com>
> ---
>  arch/arm/mach-s3c2410/include/mach/h1940-latch.h |    7 +++----
>  arch/arm/mach-s3c2410/mach-h1940.c               |   17 ++++++++++++++++-
>  2 files changed, 19 insertions(+), 5 deletions(-)

Ping :)
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From eric.y.miao at gmail.com  Mon Jun 21 10:22:32 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 22:22:32 +0800
Subject: [PATCH 1/3] [ARM] pxa: move pmu device back into mach-pxa/
Message-ID: <1277130154-25912-1-git-send-email-eric.y.miao@gmail.com>

Not tested and enabled on MMP at this moment, and since the IRQ
is different from mach-pxa, I'd prefer to move the PMU device
back into mach-pxa/. Will introduce the PMU device to MMP once
it's enabled and tested.

Signed-off-by: Eric Miao <eric.y.miao at gmail.com>
---
 arch/arm/mach-pxa/devices.c |   14 ++++++++++++++
 arch/arm/mach-pxa/devices.h |    1 +
 arch/arm/mach-pxa/pxa25x.c  |    1 +
 arch/arm/mach-pxa/pxa27x.c  |    1 +
 arch/arm/mach-pxa/pxa3xx.c  |    1 +
 arch/arm/plat-pxa/Makefile  |    1 -
 arch/arm/plat-pxa/pmu.c     |   33 ---------------------------------
 7 files changed, 18 insertions(+), 34 deletions(-)
 delete mode 100644 arch/arm/plat-pxa/pmu.c

diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 8e10db1..65447dc 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -4,6 +4,7 @@
 #include <linux/platform_device.h>
 #include <linux/dma-mapping.h>
 
+#include <asm/pmu.h>
 #include <mach/udc.h>
 #include <mach/pxafb.h>
 #include <mach/mmc.h>
@@ -31,6 +32,19 @@ void __init pxa_register_device(struct platform_device *dev, void *data)
 		dev_err(&dev->dev, "unable to register device: %d\n", ret);
 }
 
+static struct resource pxa_resource_pmu = {
+	.start	= IRQ_PMU,
+	.end	= IRQ_PMU,
+	.flags	= IORESOURCE_IRQ,
+};
+
+struct platform_device pxa_device_pmu = {
+	.name		= "arm-pmu",
+	.id		= ARM_PMU_DEVICE_CPU,
+	.resource	= &pxa_resource_pmu,
+	.num_resources	= 1,
+};
+
 static struct resource pxamci_resources[] = {
 	[0] = {
 		.start	= 0x41100000,
diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h
index 93817d9..50353ea 100644
--- a/arch/arm/mach-pxa/devices.h
+++ b/arch/arm/mach-pxa/devices.h
@@ -1,3 +1,4 @@
+extern struct platform_device pxa_device_pmu;
 extern struct platform_device pxa_device_mci;
 extern struct platform_device pxa3xx_device_mci2;
 extern struct platform_device pxa3xx_device_mci3;
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c
index 0b9ad30..de53f2e 100644
--- a/arch/arm/mach-pxa/pxa25x.c
+++ b/arch/arm/mach-pxa/pxa25x.c
@@ -322,6 +322,7 @@ void __init pxa26x_init_irq(void)
 
 static struct platform_device *pxa25x_devices[] __initdata = {
 	&pxa25x_device_udc,
+	&pxa_device_pmu,
 	&pxa_device_i2s,
 	&sa1100_device_rtc,
 	&pxa25x_device_ssp,
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 0af3617..c3d53dd 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -383,6 +383,7 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 
 static struct platform_device *devices[] __initdata = {
 	&pxa27x_device_udc,
+	&pxa_device_pmu,
 	&pxa_device_i2s,
 	&sa1100_device_rtc,
 	&pxa_device_rtc,
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index c18d2df..acfa9f7 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -608,6 +608,7 @@ void __init pxa3xx_set_i2c_power_info(struct i2c_pxa_platform_data *info)
 
 static struct platform_device *devices[] __initdata = {
 	&pxa27x_device_udc,
+	&pxa_device_pmu,
 	&pxa_device_i2s,
 	&sa1100_device_rtc,
 	&pxa_device_rtc,
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
index a17cc0c..4aacdd1 100644
--- a/arch/arm/plat-pxa/Makefile
+++ b/arch/arm/plat-pxa/Makefile
@@ -4,7 +4,6 @@
 
 obj-y	:= dma.o
 
-obj-$(CONFIG_ARCH_PXA)		+= pmu.o
 obj-$(CONFIG_GENERIC_GPIO)	+= gpio.o
 obj-$(CONFIG_PXA3xx)		+= mfp.o
 obj-$(CONFIG_ARCH_MMP)		+= mfp.o
diff --git a/arch/arm/plat-pxa/pmu.c b/arch/arm/plat-pxa/pmu.c
deleted file mode 100644
index 267ceb6..0000000
--- a/arch/arm/plat-pxa/pmu.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * PMU IRQ registration for the PXA xscale PMU families.
- * Copyright (C) 2010 Will Deacon, ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/platform_device.h>
-#include <asm/pmu.h>
-#include <mach/irqs.h>
-
-static struct resource pmu_resource = {
-	.start	= IRQ_PMU,
-	.end	= IRQ_PMU,
-	.flags	= IORESOURCE_IRQ,
-};
-
-static struct platform_device pmu_device = {
-	.name		= "arm-pmu",
-	.id		= ARM_PMU_DEVICE_CPU,
-	.resource	= &pmu_resource,
-	.num_resources	= 1,
-};
-
-static int __init pxa_pmu_init(void)
-{
-	platform_device_register(&pmu_device);
-	return 0;
-}
-arch_initcall(pxa_pmu_init);
-- 
1.7.1



From eric.y.miao at gmail.com  Mon Jun 21 10:22:33 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 22:22:33 +0800
Subject: [PATCH 2/3] [ARM] pxa: remove useless NODE_MEM_SIZE_BITS
In-Reply-To: <1277130154-25912-1-git-send-email-eric.y.miao@gmail.com>
References: <1277130154-25912-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1277130154-25912-2-git-send-email-eric.y.miao@gmail.com>

As DISCONTIGMEM is not enabled on PXA, remove this useless bit.

Signed-off-by: Eric Miao <eric.y.miao at gmail.com>
---
 arch/arm/mach-pxa/include/mach/memory.h |   12 ------------
 1 files changed, 0 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index f626730..81fd4a0 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -17,18 +17,6 @@
  */
 #define PHYS_OFFSET	UL(0xa0000000)
 
-/*
- * The nodes are matched with the physical SDRAM banks as follows:
- *
- * 	node 0:  0xa0000000-0xa3ffffff	-->  0xc0000000-0xc3ffffff
- * 	node 1:  0xa4000000-0xa7ffffff	-->  0xc4000000-0xc7ffffff
- * 	node 2:  0xa8000000-0xabffffff	-->  0xc8000000-0xcbffffff
- * 	node 3:  0xac000000-0xafffffff	-->  0xcc000000-0xcfffffff
- *
- * This needs a node mem size of 26 bits.
- */
-#define NODE_MEM_SIZE_BITS	26
-
 #if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
 void cmx2xx_pci_adjust_zones(int node, unsigned long *size,
 			     unsigned long *holes);
-- 
1.7.1



From eric.y.miao at gmail.com  Mon Jun 21 10:22:34 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 22:22:34 +0800
Subject: [PATCH 3/3] [ARM] pxa: merge all eseries board code into eseries.c
In-Reply-To: <1277130154-25912-1-git-send-email-eric.y.miao@gmail.com>
References: <1277130154-25912-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1277130154-25912-3-git-send-email-eric.y.miao@gmail.com>

Signed-off-by: Eric Miao <eric.y.miao at gmail.com>
---
 arch/arm/mach-pxa/Makefile  |    6 -
 arch/arm/mach-pxa/e330.c    |   78 -----
 arch/arm/mach-pxa/e350.c    |   79 -----
 arch/arm/mach-pxa/e400.c    |  155 ---------
 arch/arm/mach-pxa/e740.c    |  225 ------------
 arch/arm/mach-pxa/e750.c    |  226 ------------
 arch/arm/mach-pxa/e800.c    |  229 ------------
 arch/arm/mach-pxa/eseries.c |  809 +++++++++++++++++++++++++++++++++++++++++++
 8 files changed, 809 insertions(+), 998 deletions(-)
 delete mode 100644 arch/arm/mach-pxa/e330.c
 delete mode 100644 arch/arm/mach-pxa/e350.c
 delete mode 100644 arch/arm/mach-pxa/e400.c
 delete mode 100644 arch/arm/mach-pxa/e740.c
 delete mode 100644 arch/arm/mach-pxa/e750.c
 delete mode 100644 arch/arm/mach-pxa/e800.c

diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index 3f72218..cb408ef 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -86,12 +86,6 @@ obj-$(CONFIG_MACH_POODLE)	+= poodle.o
 obj-$(CONFIG_MACH_TOSA)		+= tosa.o
 obj-$(CONFIG_MACH_ICONTROL)     += icontrol.o mxm8x10.o
 obj-$(CONFIG_ARCH_PXA_ESERIES)	+= eseries.o
-obj-$(CONFIG_MACH_E330)		+= e330.o
-obj-$(CONFIG_MACH_E350)		+= e350.o
-obj-$(CONFIG_MACH_E740)		+= e740.o
-obj-$(CONFIG_MACH_E750)		+= e750.o
-obj-$(CONFIG_MACH_E400)		+= e400.o
-obj-$(CONFIG_MACH_E800)		+= e800.o
 obj-$(CONFIG_MACH_RAUMFELD_RC)		+= raumfeld.o
 obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR)	+= raumfeld.o
 obj-$(CONFIG_MACH_RAUMFELD_SPEAKER)	+= raumfeld.o
diff --git a/arch/arm/mach-pxa/e330.c b/arch/arm/mach-pxa/e330.c
deleted file mode 100644
index 8fde338..0000000
--- a/arch/arm/mach-pxa/e330.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Hardware definitions for the Toshiba e330 PDAs
- *
- * Copyright (c) 2003 Ian Molton <spyro at f2s.com>
- *
- * This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/tc6387xb.h>
-
-#include <asm/setup.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <mach/pxa25x.h>
-#include <mach/eseries-gpio.h>
-#include <mach/udc.h>
-
-#include "generic.h"
-#include "eseries.h"
-#include "clock.h"
-
-/* -------------------- e330 tc6387xb parameters -------------------- */
-
-static struct tc6387xb_platform_data e330_tc6387xb_info = {
-	.enable   = &eseries_tmio_enable,
-	.disable  = &eseries_tmio_disable,
-	.suspend  = &eseries_tmio_suspend,
-	.resume   = &eseries_tmio_resume,
-};
-
-static struct platform_device e330_tc6387xb_device = {
-	.name           = "tc6387xb",
-	.id             = -1,
-	.dev            = {
-		.platform_data = &e330_tc6387xb_info,
-	},
-	.num_resources = 2,
-	.resource      = eseries_tmio_resources,
-};
-
-/* --------------------------------------------------------------- */
-
-static struct platform_device *devices[] __initdata = {
-	&e330_tc6387xb_device,
-};
-
-static void __init e330_init(void)
-{
-	pxa_set_ffuart_info(NULL);
-	pxa_set_btuart_info(NULL);
-	pxa_set_stuart_info(NULL);
-	eseries_register_clks();
-	eseries_get_tmio_gpios();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	pxa_set_udc_info(&e7xx_udc_mach_info);
-}
-
-MACHINE_START(E330, "Toshiba e330")
-	/* Maintainer: Ian Molton (spyro at f2s.com) */
-	.phys_io	= 0x40000000,
-	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params	= 0xa0000100,
-	.map_io		= pxa_map_io,
-	.init_irq	= pxa25x_init_irq,
-	.fixup		= eseries_fixup,
-	.init_machine	= e330_init,
-	.timer		= &pxa_timer,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/e350.c b/arch/arm/mach-pxa/e350.c
deleted file mode 100644
index f50f055..0000000
--- a/arch/arm/mach-pxa/e350.c
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Hardware definitions for the Toshiba e350 PDAs
- *
- * Copyright (c) 2003 Ian Molton <spyro at f2s.com>
- *
- * This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/t7l66xb.h>
-
-#include <asm/setup.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <mach/irqs.h>
-#include <mach/pxa25x.h>
-#include <mach/eseries-gpio.h>
-#include <mach/udc.h>
-
-#include "generic.h"
-#include "eseries.h"
-#include "clock.h"
-
-/* -------------------- e350 t7l66xb parameters -------------------- */
-
-static struct t7l66xb_platform_data e350_t7l66xb_info = {
-	.irq_base               = IRQ_BOARD_START,
-	.enable                 = &eseries_tmio_enable,
-	.suspend                = &eseries_tmio_suspend,
-	.resume                 = &eseries_tmio_resume,
-};
-
-static struct platform_device e350_t7l66xb_device = {
-	.name           = "t7l66xb",
-	.id             = -1,
-	.dev            = {
-		.platform_data = &e350_t7l66xb_info,
-	},
-	.num_resources = 2,
-	.resource      = eseries_tmio_resources,
-};
-
-/* ---------------------------------------------------------- */
-
-static struct platform_device *devices[] __initdata = {
-	&e350_t7l66xb_device,
-};
-
-static void __init e350_init(void)
-{
-	pxa_set_ffuart_info(NULL);
-	pxa_set_btuart_info(NULL);
-	pxa_set_stuart_info(NULL);
-	eseries_register_clks();
-	eseries_get_tmio_gpios();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	pxa_set_udc_info(&e7xx_udc_mach_info);
-}
-
-MACHINE_START(E350, "Toshiba e350")
-	/* Maintainer: Ian Molton (spyro at f2s.com) */
-	.phys_io	= 0x40000000,
-	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params	= 0xa0000100,
-	.map_io		= pxa_map_io,
-	.init_irq	= pxa25x_init_irq,
-	.fixup		= eseries_fixup,
-	.init_machine	= e350_init,
-	.timer		= &pxa_timer,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/e400.c b/arch/arm/mach-pxa/e400.c
deleted file mode 100644
index 55b950f..0000000
--- a/arch/arm/mach-pxa/e400.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * Hardware definitions for the Toshiba eseries PDAs
- *
- * Copyright (c) 2003 Ian Molton <spyro at f2s.com>
- *
- * This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/t7l66xb.h>
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-
-#include <asm/setup.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <mach/pxa25x.h>
-#include <mach/eseries-gpio.h>
-#include <mach/pxafb.h>
-#include <mach/udc.h>
-#include <mach/irqs.h>
-
-#include "generic.h"
-#include "eseries.h"
-#include "clock.h"
-
-/* ------------------------ E400 LCD definitions ------------------------ */
-
-static struct pxafb_mode_info e400_pxafb_mode_info = {
-	.pixclock       = 140703,
-	.xres           = 240,
-	.yres           = 320,
-	.bpp            = 16,
-	.hsync_len      = 4,
-	.left_margin    = 28,
-	.right_margin   = 8,
-	.vsync_len      = 3,
-	.upper_margin   = 5,
-	.lower_margin   = 6,
-	.sync           = 0,
-};
-
-static struct pxafb_mach_info e400_pxafb_mach_info = {
-	.modes          = &e400_pxafb_mode_info,
-	.num_modes      = 1,
-	.lcd_conn	= LCD_COLOR_TFT_16BPP,
-	.lccr3          = 0,
-	.pxafb_backlight_power  = NULL,
-};
-
-/* ------------------------ E400 MFP config ----------------------------- */
-
-static unsigned long e400_pin_config[] __initdata = {
-	/* Chip selects */
-	GPIO15_nCS_1,   /* CS1 - Flash */
-	GPIO80_nCS_4,   /* CS4 - TMIO */
-
-	/* Clocks */
-	GPIO12_32KHz,
-
-	/* BTUART */
-	GPIO42_BTUART_RXD,
-	GPIO43_BTUART_TXD,
-	GPIO44_BTUART_CTS,
-
-	/* TMIO controller */
-	GPIO19_GPIO, /* t7l66xb #PCLR */
-	GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */
-
-	/* wakeup */
-	GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
-};
-
-/* ---------------------------------------------------------------------- */
-
-static struct mtd_partition partition_a = {
-	.name = "Internal NAND flash",
-	.offset =  0,
-	.size =  MTDPART_SIZ_FULL,
-};
-
-static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
-
-static struct nand_bbt_descr e400_t7l66xb_nand_bbt = {
-	.options = 0,
-	.offs = 4,
-	.len = 2,
-	.pattern = scan_ff_pattern
-};
-
-static struct tmio_nand_data e400_t7l66xb_nand_config = {
-	.num_partitions = 1,
-	.partition = &partition_a,
-	.badblock_pattern = &e400_t7l66xb_nand_bbt,
-};
-
-static struct t7l66xb_platform_data e400_t7l66xb_info = {
-	.irq_base 		= IRQ_BOARD_START,
-	.enable                 = &eseries_tmio_enable,
-	.suspend                = &eseries_tmio_suspend,
-	.resume                 = &eseries_tmio_resume,
-
-	.nand_data              = &e400_t7l66xb_nand_config,
-};
-
-static struct platform_device e400_t7l66xb_device = {
-	.name           = "t7l66xb",
-	.id             = -1,
-	.dev            = {
-		.platform_data = &e400_t7l66xb_info,
-	},
-	.num_resources = 2,
-	.resource      = eseries_tmio_resources,
-};
-
-/* ---------------------------------------------------------- */
-
-static struct platform_device *devices[] __initdata = {
-	&e400_t7l66xb_device,
-};
-
-static void __init e400_init(void)
-{
-	pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config));
-	pxa_set_ffuart_info(NULL);
-	pxa_set_btuart_info(NULL);
-	pxa_set_stuart_info(NULL);
-	/* Fixme - e400 may have a switched clock */
-	eseries_register_clks();
-	eseries_get_tmio_gpios();
-	set_pxa_fb_info(&e400_pxafb_mach_info);
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	pxa_set_udc_info(&e7xx_udc_mach_info);
-}
-
-MACHINE_START(E400, "Toshiba e400")
-	/* Maintainer: Ian Molton (spyro at f2s.com) */
-	.phys_io	= 0x40000000,
-	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params	= 0xa0000100,
-	.map_io		= pxa_map_io,
-	.init_irq	= pxa25x_init_irq,
-	.fixup		= eseries_fixup,
-	.init_machine	= e400_init,
-	.timer		= &pxa_timer,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/e740.c b/arch/arm/mach-pxa/e740.c
deleted file mode 100644
index d578021..0000000
--- a/arch/arm/mach-pxa/e740.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * Hardware definitions for the Toshiba eseries PDAs
- *
- * Copyright (c) 2003 Ian Molton <spyro at f2s.com>
- *
- * This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/fb.h>
-#include <linux/clk.h>
-#include <linux/mfd/t7l66xb.h>
-
-#include <video/w100fb.h>
-
-#include <asm/setup.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <mach/pxa25x.h>
-#include <mach/eseries-gpio.h>
-#include <mach/udc.h>
-#include <mach/irda.h>
-#include <mach/irqs.h>
-#include <mach/audio.h>
-
-#include "generic.h"
-#include "eseries.h"
-#include "clock.h"
-#include "devices.h"
-
-/* ------------------------ e740 video support --------------------------- */
-
-static struct w100_gen_regs e740_lcd_regs = {
-	.lcd_format =            0x00008023,
-	.lcdd_cntl1 =            0x0f000000,
-	.lcdd_cntl2 =            0x0003ffff,
-	.genlcd_cntl1 =          0x00ffff03,
-	.genlcd_cntl2 =          0x003c0f03,
-	.genlcd_cntl3 =          0x000143aa,
-};
-
-static struct w100_mode e740_lcd_mode = {
-	.xres            = 240,
-	.yres            = 320,
-	.left_margin     = 20,
-	.right_margin    = 28,
-	.upper_margin    = 9,
-	.lower_margin    = 8,
-	.crtc_ss         = 0x80140013,
-	.crtc_ls         = 0x81150110,
-	.crtc_gs         = 0x80050005,
-	.crtc_vpos_gs    = 0x000a0009,
-	.crtc_rev        = 0x0040010a,
-	.crtc_dclk       = 0xa906000a,
-	.crtc_gclk       = 0x80050108,
-	.crtc_goe        = 0x80050108,
-	.pll_freq        = 57,
-	.pixclk_divider         = 4,
-	.pixclk_divider_rotated = 4,
-	.pixclk_src     = CLK_SRC_XTAL,
-	.sysclk_divider  = 1,
-	.sysclk_src     = CLK_SRC_PLL,
-	.crtc_ps1_active =       0x41060010,
-};
-
-static struct w100_gpio_regs e740_w100_gpio_info = {
-	.init_data1 = 0x21002103,
-	.gpio_dir1  = 0xffffdeff,
-	.gpio_oe1   = 0x03c00643,
-	.init_data2 = 0x003f003f,
-	.gpio_dir2  = 0xffffffff,
-	.gpio_oe2   = 0x000000ff,
-};
-
-static struct w100fb_mach_info e740_fb_info = {
-	.modelist   = &e740_lcd_mode,
-	.num_modes  = 1,
-	.regs       = &e740_lcd_regs,
-	.gpio       = &e740_w100_gpio_info,
-	.xtal_freq = 14318000,
-	.xtal_dbl   = 1,
-};
-
-static struct resource e740_fb_resources[] = {
-	[0] = {
-		.start          = 0x0c000000,
-		.end            = 0x0cffffff,
-		.flags          = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device e740_fb_device = {
-	.name           = "w100fb",
-	.id             = -1,
-	.dev            = {
-		.platform_data  = &e740_fb_info,
-	},
-	.num_resources  = ARRAY_SIZE(e740_fb_resources),
-	.resource       = e740_fb_resources,
-};
-
-/* --------------------------- MFP Pin config -------------------------- */
-
-static unsigned long e740_pin_config[] __initdata = {
-	/* Chip selects */
-	GPIO15_nCS_1,   /* CS1 - Flash */
-	GPIO79_nCS_3,   /* CS3 - IMAGEON */
-	GPIO80_nCS_4,   /* CS4 - TMIO */
-
-	/* Clocks */
-	GPIO12_32KHz,
-
-	/* BTUART */
-	GPIO42_BTUART_RXD,
-	GPIO43_BTUART_TXD,
-	GPIO44_BTUART_CTS,
-
-	/* TMIO controller */
-	GPIO19_GPIO, /* t7l66xb #PCLR */
-	GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */
-
-	/* UDC */
-	GPIO13_GPIO,
-	GPIO3_GPIO,
-
-	/* IrDA */
-	GPIO38_GPIO | MFP_LPM_DRIVE_HIGH,
-
-	/* AC97 */
-	GPIO28_AC97_BITCLK,
-	GPIO29_AC97_SDATA_IN_0,
-	GPIO30_AC97_SDATA_OUT,
-	GPIO31_AC97_SYNC,
-
-	/* Audio power control */
-	GPIO16_GPIO,  /* AC97 codec AVDD2 supply (analogue power) */
-	GPIO40_GPIO,  /* Mic amp power */
-	GPIO41_GPIO,  /* Headphone amp power */
-
-	/* PC Card */
-	GPIO8_GPIO,   /* CD0 */
-	GPIO44_GPIO,  /* CD1 */
-	GPIO11_GPIO,  /* IRQ0 */
-	GPIO6_GPIO,   /* IRQ1 */
-	GPIO27_GPIO,  /* RST0 */
-	GPIO24_GPIO,  /* RST1 */
-	GPIO20_GPIO,  /* PWR0 */
-	GPIO23_GPIO,  /* PWR1 */
-	GPIO48_nPOE,
-	GPIO49_nPWE,
-	GPIO50_nPIOR,
-	GPIO51_nPIOW,
-	GPIO52_nPCE_1,
-	GPIO53_nPCE_2,
-	GPIO54_nPSKTSEL,
-	GPIO55_nPREG,
-	GPIO56_nPWAIT,
-	GPIO57_nIOIS16,
-
-	/* wakeup */
-	GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
-};
-
-/* -------------------- e740 t7l66xb parameters -------------------- */
-
-static struct t7l66xb_platform_data e740_t7l66xb_info = {
-	.irq_base 		= IRQ_BOARD_START,
-	.enable                 = &eseries_tmio_enable,
-	.suspend                = &eseries_tmio_suspend,
-	.resume                 = &eseries_tmio_resume,
-};
-
-static struct platform_device e740_t7l66xb_device = {
-	.name           = "t7l66xb",
-	.id             = -1,
-	.dev            = {
-		.platform_data = &e740_t7l66xb_info,
-	},
-	.num_resources = 2,
-	.resource      = eseries_tmio_resources,
-};
-
-/* ----------------------------------------------------------------------- */
-
-static struct platform_device *devices[] __initdata = {
-	&e740_fb_device,
-	&e740_t7l66xb_device,
-};
-
-static void __init e740_init(void)
-{
-	pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config));
-	pxa_set_ffuart_info(NULL);
-	pxa_set_btuart_info(NULL);
-	pxa_set_stuart_info(NULL);
-	eseries_register_clks();
-	clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name,
-			"UDCCLK", &pxa25x_device_udc.dev),
-	eseries_get_tmio_gpios();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	pxa_set_udc_info(&e7xx_udc_mach_info);
-	pxa_set_ac97_info(NULL);
-	pxa_set_ficp_info(&e7xx_ficp_platform_data);
-}
-
-MACHINE_START(E740, "Toshiba e740")
-	/* Maintainer: Ian Molton (spyro at f2s.com) */
-	.phys_io	= 0x40000000,
-	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params	= 0xa0000100,
-	.map_io		= pxa_map_io,
-	.init_irq	= pxa25x_init_irq,
-	.fixup		= eseries_fixup,
-	.init_machine	= e740_init,
-	.timer		= &pxa_timer,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/e750.c b/arch/arm/mach-pxa/e750.c
deleted file mode 100644
index af83caa..0000000
--- a/arch/arm/mach-pxa/e750.c
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * Hardware definitions for the Toshiba eseries PDAs
- *
- * Copyright (c) 2003 Ian Molton <spyro at f2s.com>
- *
- * This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/fb.h>
-#include <linux/mfd/tc6393xb.h>
-
-#include <video/w100fb.h>
-
-#include <asm/setup.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <mach/pxa25x.h>
-#include <mach/eseries-gpio.h>
-#include <mach/udc.h>
-#include <mach/irda.h>
-#include <mach/irqs.h>
-#include <mach/audio.h>
-
-#include "generic.h"
-#include "eseries.h"
-#include "clock.h"
-
-/* ---------------------- E750 LCD definitions -------------------- */
-
-static struct w100_gen_regs e750_lcd_regs = {
-	.lcd_format =            0x00008003,
-	.lcdd_cntl1 =            0x00000000,
-	.lcdd_cntl2 =            0x0003ffff,
-	.genlcd_cntl1 =          0x00fff003,
-	.genlcd_cntl2 =          0x003c0f03,
-	.genlcd_cntl3 =          0x000143aa,
-};
-
-static struct w100_mode e750_lcd_mode = {
-	.xres            = 240,
-	.yres            = 320,
-	.left_margin     = 21,
-	.right_margin    = 22,
-	.upper_margin    = 5,
-	.lower_margin    = 4,
-	.crtc_ss         = 0x80150014,
-	.crtc_ls         = 0x8014000d,
-	.crtc_gs         = 0xc1000005,
-	.crtc_vpos_gs    = 0x00020147,
-	.crtc_rev        = 0x0040010a,
-	.crtc_dclk       = 0xa1700030,
-	.crtc_gclk       = 0x80cc0015,
-	.crtc_goe        = 0x80cc0015,
-	.crtc_ps1_active = 0x61060017,
-	.pll_freq        = 57,
-	.pixclk_divider         = 4,
-	.pixclk_divider_rotated = 4,
-	.pixclk_src     = CLK_SRC_XTAL,
-	.sysclk_divider  = 1,
-	.sysclk_src     = CLK_SRC_PLL,
-};
-
-static struct w100_gpio_regs e750_w100_gpio_info = {
-	.init_data1 = 0x01192f1b,
-	.gpio_dir1  = 0xd5ffdeff,
-	.gpio_oe1   = 0x000020bf,
-	.init_data2 = 0x010f010f,
-	.gpio_dir2  = 0xffffffff,
-	.gpio_oe2   = 0x000001cf,
-};
-
-static struct w100fb_mach_info e750_fb_info = {
-	.modelist   = &e750_lcd_mode,
-	.num_modes  = 1,
-	.regs       = &e750_lcd_regs,
-	.gpio       = &e750_w100_gpio_info,
-	.xtal_freq  = 14318000,
-	.xtal_dbl   = 1,
-};
-
-static struct resource e750_fb_resources[] = {
-	[0] = {
-		.start          = 0x0c000000,
-		.end            = 0x0cffffff,
-		.flags          = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device e750_fb_device = {
-	.name           = "w100fb",
-	.id             = -1,
-	.dev            = {
-		.platform_data  = &e750_fb_info,
-	},
-	.num_resources  = ARRAY_SIZE(e750_fb_resources),
-	.resource       = e750_fb_resources,
-};
-
-/* -------------------- e750 MFP parameters -------------------- */
-
-static unsigned long e750_pin_config[] __initdata = {
-	/* Chip selects */
-	GPIO15_nCS_1,   /* CS1 - Flash */
-	GPIO79_nCS_3,   /* CS3 - IMAGEON */
-	GPIO80_nCS_4,   /* CS4 - TMIO */
-
-	/* Clocks */
-	GPIO11_3_6MHz,
-
-	/* BTUART */
-	GPIO42_BTUART_RXD,
-	GPIO43_BTUART_TXD,
-	GPIO44_BTUART_CTS,
-
-	/* TMIO controller */
-	GPIO19_GPIO, /* t7l66xb #PCLR */
-	GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */
-
-	/* UDC */
-	GPIO13_GPIO,
-	GPIO3_GPIO,
-
-	/* IrDA */
-	GPIO38_GPIO | MFP_LPM_DRIVE_HIGH,
-
-	/* AC97 */
-	GPIO28_AC97_BITCLK,
-	GPIO29_AC97_SDATA_IN_0,
-	GPIO30_AC97_SDATA_OUT,
-	GPIO31_AC97_SYNC,
-
-	/* Audio power control */
-	GPIO4_GPIO,  /* Headphone amp power */
-	GPIO7_GPIO,  /* Speaker amp power */
-	GPIO37_GPIO, /* Headphone detect */
-
-	/* PC Card */
-	GPIO8_GPIO,   /* CD0 */
-	GPIO44_GPIO,  /* CD1 */
-	GPIO11_GPIO,  /* IRQ0 */
-	GPIO6_GPIO,   /* IRQ1 */
-	GPIO27_GPIO,  /* RST0 */
-	GPIO24_GPIO,  /* RST1 */
-	GPIO20_GPIO,  /* PWR0 */
-	GPIO23_GPIO,  /* PWR1 */
-	GPIO48_nPOE,
-	GPIO49_nPWE,
-	GPIO50_nPIOR,
-	GPIO51_nPIOW,
-	GPIO52_nPCE_1,
-	GPIO53_nPCE_2,
-	GPIO54_nPSKTSEL,
-	GPIO55_nPREG,
-	GPIO56_nPWAIT,
-	GPIO57_nIOIS16,
-
-	/* wakeup */
-	GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
-};
-
-/* ----------------- e750 tc6393xb parameters ------------------ */
-
-static struct tc6393xb_platform_data e750_tc6393xb_info = {
-	.irq_base       = IRQ_BOARD_START,
-	.scr_pll2cr     = 0x0cc1,
-	.scr_gper       = 0,
-	.gpio_base      = -1,
-	.suspend        = &eseries_tmio_suspend,
-	.resume         = &eseries_tmio_resume,
-	.enable         = &eseries_tmio_enable,
-	.disable        = &eseries_tmio_disable,
-};
-
-static struct platform_device e750_tc6393xb_device = {
-	.name           = "tc6393xb",
-	.id             = -1,
-	.dev            = {
-		.platform_data = &e750_tc6393xb_info,
-	},
-	.num_resources = 2,
-	.resource      = eseries_tmio_resources,
-};
-
-/* ------------------------------------------------------------- */
-
-static struct platform_device *devices[] __initdata = {
-	&e750_fb_device,
-	&e750_tc6393xb_device,
-};
-
-static void __init e750_init(void)
-{
-	pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config));
-	pxa_set_ffuart_info(NULL);
-	pxa_set_btuart_info(NULL);
-	pxa_set_stuart_info(NULL);
-	clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name,
-			"GPIO11_CLK", NULL),
-	eseries_get_tmio_gpios();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	pxa_set_udc_info(&e7xx_udc_mach_info);
-	pxa_set_ac97_info(NULL);
-	pxa_set_ficp_info(&e7xx_ficp_platform_data);
-}
-
-MACHINE_START(E750, "Toshiba e750")
-	/* Maintainer: Ian Molton (spyro at f2s.com) */
-	.phys_io	= 0x40000000,
-	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params	= 0xa0000100,
-	.map_io		= pxa_map_io,
-	.init_irq	= pxa25x_init_irq,
-	.fixup		= eseries_fixup,
-	.init_machine	= e750_init,
-	.timer		= &pxa_timer,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/e800.c b/arch/arm/mach-pxa/e800.c
deleted file mode 100644
index 8ea97bf..0000000
--- a/arch/arm/mach-pxa/e800.c
+++ /dev/null
@@ -1,229 +0,0 @@
-/*
- * Hardware definitions for the Toshiba eseries PDAs
- *
- * Copyright (c) 2003 Ian Molton <spyro at f2s.com>
- *
- * This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/fb.h>
-#include <linux/mfd/tc6393xb.h>
-
-#include <video/w100fb.h>
-
-#include <asm/setup.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <mach/pxa25x.h>
-#include <mach/eseries-gpio.h>
-#include <mach/udc.h>
-#include <mach/irqs.h>
-#include <mach/audio.h>
-
-#include "generic.h"
-#include "eseries.h"
-#include "clock.h"
-
-/* ------------------------ e800 LCD definitions ------------------------- */
-
-static unsigned long e800_pin_config[] __initdata = {
-	/* AC97 */
-	GPIO28_AC97_BITCLK,
-	GPIO29_AC97_SDATA_IN_0,
-	GPIO30_AC97_SDATA_OUT,
-	GPIO31_AC97_SYNC,
-};
-
-static struct w100_gen_regs e800_lcd_regs = {
-	.lcd_format =            0x00008003,
-	.lcdd_cntl1 =            0x02a00000,
-	.lcdd_cntl2 =            0x0003ffff,
-	.genlcd_cntl1 =          0x000ff2a3,
-	.genlcd_cntl2 =          0x000002a3,
-	.genlcd_cntl3 =          0x000102aa,
-};
-
-static struct w100_mode e800_lcd_mode[2] = {
-	[0] = {
-		.xres            = 480,
-		.yres            = 640,
-		.left_margin     = 52,
-		.right_margin    = 148,
-		.upper_margin    = 2,
-		.lower_margin    = 6,
-		.crtc_ss         = 0x80350034,
-		.crtc_ls         = 0x802b0026,
-		.crtc_gs         = 0x80160016,
-		.crtc_vpos_gs    = 0x00020003,
-		.crtc_rev        = 0x0040001d,
-		.crtc_dclk       = 0xe0000000,
-		.crtc_gclk       = 0x82a50049,
-		.crtc_goe        = 0x80ee001c,
-		.crtc_ps1_active = 0x00000000,
-		.pll_freq        = 128,
-		.pixclk_divider         = 4,
-		.pixclk_divider_rotated = 6,
-		.pixclk_src     = CLK_SRC_PLL,
-		.sysclk_divider  = 0,
-		.sysclk_src     = CLK_SRC_PLL,
-	},
-	[1] = {
-		.xres            = 240,
-		.yres            = 320,
-		.left_margin     = 15,
-		.right_margin    = 88,
-		.upper_margin    = 0,
-		.lower_margin    = 7,
-		.crtc_ss         = 0xd010000f,
-		.crtc_ls         = 0x80070003,
-		.crtc_gs         = 0x80000000,
-		.crtc_vpos_gs    = 0x01460147,
-		.crtc_rev        = 0x00400003,
-		.crtc_dclk       = 0xa1700030,
-		.crtc_gclk       = 0x814b0008,
-		.crtc_goe        = 0x80cc0015,
-		.crtc_ps1_active = 0x00000000,
-		.pll_freq        = 100,
-		.pixclk_divider         = 6, /* Wince uses 14 which gives a */
-		.pixclk_divider_rotated = 6, /* 7MHz Pclk. We use a 14MHz one */
-		.pixclk_src     = CLK_SRC_PLL,
-		.sysclk_divider  = 0,
-		.sysclk_src     = CLK_SRC_PLL,
-	}
-};
-
-
-static struct w100_gpio_regs e800_w100_gpio_info = {
-	.init_data1 = 0xc13fc019,
-	.gpio_dir1  = 0x3e40df7f,
-	.gpio_oe1   = 0x003c3000,
-	.init_data2 = 0x00000000,
-	.gpio_dir2  = 0x00000000,
-	.gpio_oe2   = 0x00000000,
-};
-
-static struct w100_mem_info e800_w100_mem_info = {
-	.ext_cntl        = 0x09640011,
-	.sdram_mode_reg  = 0x00600021,
-	.ext_timing_cntl = 0x10001545,
-	.io_cntl         = 0x7ddd7333,
-	.size            = 0x1fffff,
-};
-
-static void e800_tg_change(struct w100fb_par *par)
-{
-	unsigned long tmp;
-
-	tmp = w100fb_gpio_read(W100_GPIO_PORT_A);
-	if (par->mode->xres == 480)
-		tmp |= 0x100;
-	else
-		tmp &= ~0x100;
-	w100fb_gpio_write(W100_GPIO_PORT_A, tmp);
-}
-
-static struct w100_tg_info e800_tg_info = {
-	.change = e800_tg_change,
-};
-
-static struct w100fb_mach_info e800_fb_info = {
-	.modelist   = e800_lcd_mode,
-	.num_modes  = 2,
-	.regs       = &e800_lcd_regs,
-	.gpio       = &e800_w100_gpio_info,
-	.mem        = &e800_w100_mem_info,
-	.tg         = &e800_tg_info,
-	.xtal_freq  = 16000000,
-};
-
-static struct resource e800_fb_resources[] = {
-	[0] = {
-		.start          = 0x0c000000,
-		.end            = 0x0cffffff,
-		.flags          = IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device e800_fb_device = {
-	.name           = "w100fb",
-	.id             = -1,
-	.dev            = {
-		.platform_data  = &e800_fb_info,
-	},
-	.num_resources  = ARRAY_SIZE(e800_fb_resources),
-	.resource       = e800_fb_resources,
-};
-
-/* --------------------------- UDC definitions --------------------------- */
-
-static struct pxa2xx_udc_mach_info e800_udc_mach_info = {
-	.gpio_vbus   = GPIO_E800_USB_DISC,
-	.gpio_pullup = GPIO_E800_USB_PULLUP,
-	.gpio_pullup_inverted = 1
-};
-
-/* ----------------- e800 tc6393xb parameters ------------------ */
-
-static struct tc6393xb_platform_data e800_tc6393xb_info = {
-	.irq_base       = IRQ_BOARD_START,
-	.scr_pll2cr     = 0x0cc1,
-	.scr_gper       = 0,
-	.gpio_base      = -1,
-	.suspend        = &eseries_tmio_suspend,
-	.resume         = &eseries_tmio_resume,
-	.enable         = &eseries_tmio_enable,
-	.disable        = &eseries_tmio_disable,
-};
-
-static struct platform_device e800_tc6393xb_device = {
-	.name           = "tc6393xb",
-	.id             = -1,
-	.dev            = {
-		.platform_data = &e800_tc6393xb_info,
-	},
-	.num_resources = 2,
-	.resource      = eseries_tmio_resources,
-};
-
-/* ----------------------------------------------------------------------- */
-
-static struct platform_device *devices[] __initdata = {
-	&e800_fb_device,
-	&e800_tc6393xb_device,
-};
-
-static void __init e800_init(void)
-{
-	pxa2xx_mfp_config(ARRAY_AND_SIZE(e800_pin_config));
-	pxa_set_ffuart_info(NULL);
-	pxa_set_btuart_info(NULL);
-	pxa_set_stuart_info(NULL);
-	clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name,
-			"GPIO11_CLK", NULL),
-	eseries_get_tmio_gpios();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	pxa_set_udc_info(&e800_udc_mach_info);
-	pxa_set_ac97_info(NULL);
-}
-
-MACHINE_START(E800, "Toshiba e800")
-	/* Maintainer: Ian Molton (spyro at f2s.com) */
-	.phys_io	= 0x40000000,
-	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.boot_params	= 0xa0000100,
-	.map_io		= pxa_map_io,
-	.init_irq	= pxa25x_init_irq,
-	.fixup		= eseries_fixup,
-	.init_machine	= e800_init,
-	.timer		= &pxa_timer,
-MACHINE_END
-
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 96ed130..1d67f02 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -15,6 +15,13 @@
 #include <linux/gpio.h>
 #include <linux/delay.h>
 #include <linux/platform_device.h>
+#include <linux/mfd/tc6387xb.h>
+#include <linux/mfd/tc6393xb.h>
+#include <linux/mfd/t7l66xb.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+
+#include <video/w100fb.h>
 
 #include <asm/setup.h>
 #include <asm/mach/arch.h>
@@ -22,9 +29,12 @@
 
 #include <mach/pxa25x.h>
 #include <mach/eseries-gpio.h>
+#include <mach/audio.h>
+#include <mach/pxafb.h>
 #include <mach/udc.h>
 #include <mach/irda.h>
 
+#include "devices.h"
 #include "generic.h"
 #include "clock.h"
 
@@ -131,3 +141,802 @@ void eseries_register_clks(void)
 	clkdev_add_table(eseries_clkregs, ARRAY_SIZE(eseries_clkregs));
 }
 
+#ifdef CONFIG_MACH_E330
+/* -------------------- e330 tc6387xb parameters -------------------- */
+
+static struct tc6387xb_platform_data e330_tc6387xb_info = {
+	.enable   = &eseries_tmio_enable,
+	.disable  = &eseries_tmio_disable,
+	.suspend  = &eseries_tmio_suspend,
+	.resume   = &eseries_tmio_resume,
+};
+
+static struct platform_device e330_tc6387xb_device = {
+	.name           = "tc6387xb",
+	.id             = -1,
+	.dev            = {
+		.platform_data = &e330_tc6387xb_info,
+	},
+	.num_resources = 2,
+	.resource      = eseries_tmio_resources,
+};
+
+/* --------------------------------------------------------------- */
+
+static struct platform_device *e330_devices[] __initdata = {
+	&e330_tc6387xb_device,
+};
+
+static void __init e330_init(void)
+{
+	pxa_set_ffuart_info(NULL);
+	pxa_set_btuart_info(NULL);
+	pxa_set_stuart_info(NULL);
+	eseries_register_clks();
+	eseries_get_tmio_gpios();
+	platform_add_devices(ARRAY_AND_SIZE(e330_devices));
+	pxa_set_udc_info(&e7xx_udc_mach_info);
+}
+
+MACHINE_START(E330, "Toshiba e330")
+	/* Maintainer: Ian Molton (spyro at f2s.com) */
+	.phys_io	= 0x40000000,
+	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
+	.boot_params	= 0xa0000100,
+	.map_io		= pxa_map_io,
+	.init_irq	= pxa25x_init_irq,
+	.fixup		= eseries_fixup,
+	.init_machine	= e330_init,
+	.timer		= &pxa_timer,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_E350
+/* -------------------- e350 t7l66xb parameters -------------------- */
+
+static struct t7l66xb_platform_data e350_t7l66xb_info = {
+	.irq_base               = IRQ_BOARD_START,
+	.enable                 = &eseries_tmio_enable,
+	.suspend                = &eseries_tmio_suspend,
+	.resume                 = &eseries_tmio_resume,
+};
+
+static struct platform_device e350_t7l66xb_device = {
+	.name           = "t7l66xb",
+	.id             = -1,
+	.dev            = {
+		.platform_data = &e350_t7l66xb_info,
+	},
+	.num_resources = 2,
+	.resource      = eseries_tmio_resources,
+};
+
+/* ---------------------------------------------------------- */
+
+static struct platform_device *e350_devices[] __initdata = {
+	&e350_t7l66xb_device,
+};
+
+static void __init e350_init(void)
+{
+	pxa_set_ffuart_info(NULL);
+	pxa_set_btuart_info(NULL);
+	pxa_set_stuart_info(NULL);
+	eseries_register_clks();
+	eseries_get_tmio_gpios();
+	platform_add_devices(ARRAY_AND_SIZE(e350_devices));
+	pxa_set_udc_info(&e7xx_udc_mach_info);
+}
+
+MACHINE_START(E350, "Toshiba e350")
+	/* Maintainer: Ian Molton (spyro at f2s.com) */
+	.phys_io	= 0x40000000,
+	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
+	.boot_params	= 0xa0000100,
+	.map_io		= pxa_map_io,
+	.init_irq	= pxa25x_init_irq,
+	.fixup		= eseries_fixup,
+	.init_machine	= e350_init,
+	.timer		= &pxa_timer,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_E400
+/* ------------------------ E400 LCD definitions ------------------------ */
+
+static struct pxafb_mode_info e400_pxafb_mode_info = {
+	.pixclock       = 140703,
+	.xres           = 240,
+	.yres           = 320,
+	.bpp            = 16,
+	.hsync_len      = 4,
+	.left_margin    = 28,
+	.right_margin   = 8,
+	.vsync_len      = 3,
+	.upper_margin   = 5,
+	.lower_margin   = 6,
+	.sync           = 0,
+};
+
+static struct pxafb_mach_info e400_pxafb_mach_info = {
+	.modes          = &e400_pxafb_mode_info,
+	.num_modes      = 1,
+	.lcd_conn	= LCD_COLOR_TFT_16BPP,
+	.lccr3          = 0,
+	.pxafb_backlight_power  = NULL,
+};
+
+/* ------------------------ E400 MFP config ----------------------------- */
+
+static unsigned long e400_pin_config[] __initdata = {
+	/* Chip selects */
+	GPIO15_nCS_1,   /* CS1 - Flash */
+	GPIO80_nCS_4,   /* CS4 - TMIO */
+
+	/* Clocks */
+	GPIO12_32KHz,
+
+	/* BTUART */
+	GPIO42_BTUART_RXD,
+	GPIO43_BTUART_TXD,
+	GPIO44_BTUART_CTS,
+
+	/* TMIO controller */
+	GPIO19_GPIO, /* t7l66xb #PCLR */
+	GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */
+
+	/* wakeup */
+	GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
+};
+
+/* ---------------------------------------------------------------------- */
+
+static struct mtd_partition partition_a = {
+	.name = "Internal NAND flash",
+	.offset =  0,
+	.size =  MTDPART_SIZ_FULL,
+};
+
+static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
+
+static struct nand_bbt_descr e400_t7l66xb_nand_bbt = {
+	.options = 0,
+	.offs = 4,
+	.len = 2,
+	.pattern = scan_ff_pattern
+};
+
+static struct tmio_nand_data e400_t7l66xb_nand_config = {
+	.num_partitions = 1,
+	.partition = &partition_a,
+	.badblock_pattern = &e400_t7l66xb_nand_bbt,
+};
+
+static struct t7l66xb_platform_data e400_t7l66xb_info = {
+	.irq_base 		= IRQ_BOARD_START,
+	.enable                 = &eseries_tmio_enable,
+	.suspend                = &eseries_tmio_suspend,
+	.resume                 = &eseries_tmio_resume,
+
+	.nand_data              = &e400_t7l66xb_nand_config,
+};
+
+static struct platform_device e400_t7l66xb_device = {
+	.name           = "t7l66xb",
+	.id             = -1,
+	.dev            = {
+		.platform_data = &e400_t7l66xb_info,
+	},
+	.num_resources = 2,
+	.resource      = eseries_tmio_resources,
+};
+
+/* ---------------------------------------------------------- */
+
+static struct platform_device *e400_devices[] __initdata = {
+	&e400_t7l66xb_device,
+};
+
+static void __init e400_init(void)
+{
+	pxa2xx_mfp_config(ARRAY_AND_SIZE(e400_pin_config));
+	pxa_set_ffuart_info(NULL);
+	pxa_set_btuart_info(NULL);
+	pxa_set_stuart_info(NULL);
+	/* Fixme - e400 may have a switched clock */
+	eseries_register_clks();
+	eseries_get_tmio_gpios();
+	set_pxa_fb_info(&e400_pxafb_mach_info);
+	platform_add_devices(ARRAY_AND_SIZE(e400_devices));
+	pxa_set_udc_info(&e7xx_udc_mach_info);
+}
+
+MACHINE_START(E400, "Toshiba e400")
+	/* Maintainer: Ian Molton (spyro at f2s.com) */
+	.phys_io	= 0x40000000,
+	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
+	.boot_params	= 0xa0000100,
+	.map_io		= pxa_map_io,
+	.init_irq	= pxa25x_init_irq,
+	.fixup		= eseries_fixup,
+	.init_machine	= e400_init,
+	.timer		= &pxa_timer,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_E740
+/* ------------------------ e740 video support --------------------------- */
+
+static struct w100_gen_regs e740_lcd_regs = {
+	.lcd_format =            0x00008023,
+	.lcdd_cntl1 =            0x0f000000,
+	.lcdd_cntl2 =            0x0003ffff,
+	.genlcd_cntl1 =          0x00ffff03,
+	.genlcd_cntl2 =          0x003c0f03,
+	.genlcd_cntl3 =          0x000143aa,
+};
+
+static struct w100_mode e740_lcd_mode = {
+	.xres            = 240,
+	.yres            = 320,
+	.left_margin     = 20,
+	.right_margin    = 28,
+	.upper_margin    = 9,
+	.lower_margin    = 8,
+	.crtc_ss         = 0x80140013,
+	.crtc_ls         = 0x81150110,
+	.crtc_gs         = 0x80050005,
+	.crtc_vpos_gs    = 0x000a0009,
+	.crtc_rev        = 0x0040010a,
+	.crtc_dclk       = 0xa906000a,
+	.crtc_gclk       = 0x80050108,
+	.crtc_goe        = 0x80050108,
+	.pll_freq        = 57,
+	.pixclk_divider         = 4,
+	.pixclk_divider_rotated = 4,
+	.pixclk_src     = CLK_SRC_XTAL,
+	.sysclk_divider  = 1,
+	.sysclk_src     = CLK_SRC_PLL,
+	.crtc_ps1_active =       0x41060010,
+};
+
+static struct w100_gpio_regs e740_w100_gpio_info = {
+	.init_data1 = 0x21002103,
+	.gpio_dir1  = 0xffffdeff,
+	.gpio_oe1   = 0x03c00643,
+	.init_data2 = 0x003f003f,
+	.gpio_dir2  = 0xffffffff,
+	.gpio_oe2   = 0x000000ff,
+};
+
+static struct w100fb_mach_info e740_fb_info = {
+	.modelist   = &e740_lcd_mode,
+	.num_modes  = 1,
+	.regs       = &e740_lcd_regs,
+	.gpio       = &e740_w100_gpio_info,
+	.xtal_freq = 14318000,
+	.xtal_dbl   = 1,
+};
+
+static struct resource e740_fb_resources[] = {
+	[0] = {
+		.start          = 0x0c000000,
+		.end            = 0x0cffffff,
+		.flags          = IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device e740_fb_device = {
+	.name           = "w100fb",
+	.id             = -1,
+	.dev            = {
+		.platform_data  = &e740_fb_info,
+	},
+	.num_resources  = ARRAY_SIZE(e740_fb_resources),
+	.resource       = e740_fb_resources,
+};
+
+/* --------------------------- MFP Pin config -------------------------- */
+
+static unsigned long e740_pin_config[] __initdata = {
+	/* Chip selects */
+	GPIO15_nCS_1,   /* CS1 - Flash */
+	GPIO79_nCS_3,   /* CS3 - IMAGEON */
+	GPIO80_nCS_4,   /* CS4 - TMIO */
+
+	/* Clocks */
+	GPIO12_32KHz,
+
+	/* BTUART */
+	GPIO42_BTUART_RXD,
+	GPIO43_BTUART_TXD,
+	GPIO44_BTUART_CTS,
+
+	/* TMIO controller */
+	GPIO19_GPIO, /* t7l66xb #PCLR */
+	GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */
+
+	/* UDC */
+	GPIO13_GPIO,
+	GPIO3_GPIO,
+
+	/* IrDA */
+	GPIO38_GPIO | MFP_LPM_DRIVE_HIGH,
+
+	/* AC97 */
+	GPIO28_AC97_BITCLK,
+	GPIO29_AC97_SDATA_IN_0,
+	GPIO30_AC97_SDATA_OUT,
+	GPIO31_AC97_SYNC,
+
+	/* Audio power control */
+	GPIO16_GPIO,  /* AC97 codec AVDD2 supply (analogue power) */
+	GPIO40_GPIO,  /* Mic amp power */
+	GPIO41_GPIO,  /* Headphone amp power */
+
+	/* PC Card */
+	GPIO8_GPIO,   /* CD0 */
+	GPIO44_GPIO,  /* CD1 */
+	GPIO11_GPIO,  /* IRQ0 */
+	GPIO6_GPIO,   /* IRQ1 */
+	GPIO27_GPIO,  /* RST0 */
+	GPIO24_GPIO,  /* RST1 */
+	GPIO20_GPIO,  /* PWR0 */
+	GPIO23_GPIO,  /* PWR1 */
+	GPIO48_nPOE,
+	GPIO49_nPWE,
+	GPIO50_nPIOR,
+	GPIO51_nPIOW,
+	GPIO52_nPCE_1,
+	GPIO53_nPCE_2,
+	GPIO54_nPSKTSEL,
+	GPIO55_nPREG,
+	GPIO56_nPWAIT,
+	GPIO57_nIOIS16,
+
+	/* wakeup */
+	GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
+};
+
+/* -------------------- e740 t7l66xb parameters -------------------- */
+
+static struct t7l66xb_platform_data e740_t7l66xb_info = {
+	.irq_base 		= IRQ_BOARD_START,
+	.enable                 = &eseries_tmio_enable,
+	.suspend                = &eseries_tmio_suspend,
+	.resume                 = &eseries_tmio_resume,
+};
+
+static struct platform_device e740_t7l66xb_device = {
+	.name           = "t7l66xb",
+	.id             = -1,
+	.dev            = {
+		.platform_data = &e740_t7l66xb_info,
+	},
+	.num_resources = 2,
+	.resource      = eseries_tmio_resources,
+};
+
+/* ----------------------------------------------------------------------- */
+
+static struct platform_device *e740_devices[] __initdata = {
+	&e740_fb_device,
+	&e740_t7l66xb_device,
+};
+
+static void __init e740_init(void)
+{
+	pxa2xx_mfp_config(ARRAY_AND_SIZE(e740_pin_config));
+	pxa_set_ffuart_info(NULL);
+	pxa_set_btuart_info(NULL);
+	pxa_set_stuart_info(NULL);
+	eseries_register_clks();
+	clk_add_alias("CLK_CK48M", e740_t7l66xb_device.name,
+			"UDCCLK", &pxa25x_device_udc.dev),
+	eseries_get_tmio_gpios();
+	platform_add_devices(ARRAY_AND_SIZE(e740_devices));
+	pxa_set_udc_info(&e7xx_udc_mach_info);
+	pxa_set_ac97_info(NULL);
+	pxa_set_ficp_info(&e7xx_ficp_platform_data);
+}
+
+MACHINE_START(E740, "Toshiba e740")
+	/* Maintainer: Ian Molton (spyro at f2s.com) */
+	.phys_io	= 0x40000000,
+	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
+	.boot_params	= 0xa0000100,
+	.map_io		= pxa_map_io,
+	.init_irq	= pxa25x_init_irq,
+	.fixup		= eseries_fixup,
+	.init_machine	= e740_init,
+	.timer		= &pxa_timer,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_E750
+/* ---------------------- E750 LCD definitions -------------------- */
+
+static struct w100_gen_regs e750_lcd_regs = {
+	.lcd_format =            0x00008003,
+	.lcdd_cntl1 =            0x00000000,
+	.lcdd_cntl2 =            0x0003ffff,
+	.genlcd_cntl1 =          0x00fff003,
+	.genlcd_cntl2 =          0x003c0f03,
+	.genlcd_cntl3 =          0x000143aa,
+};
+
+static struct w100_mode e750_lcd_mode = {
+	.xres            = 240,
+	.yres            = 320,
+	.left_margin     = 21,
+	.right_margin    = 22,
+	.upper_margin    = 5,
+	.lower_margin    = 4,
+	.crtc_ss         = 0x80150014,
+	.crtc_ls         = 0x8014000d,
+	.crtc_gs         = 0xc1000005,
+	.crtc_vpos_gs    = 0x00020147,
+	.crtc_rev        = 0x0040010a,
+	.crtc_dclk       = 0xa1700030,
+	.crtc_gclk       = 0x80cc0015,
+	.crtc_goe        = 0x80cc0015,
+	.crtc_ps1_active = 0x61060017,
+	.pll_freq        = 57,
+	.pixclk_divider         = 4,
+	.pixclk_divider_rotated = 4,
+	.pixclk_src     = CLK_SRC_XTAL,
+	.sysclk_divider  = 1,
+	.sysclk_src     = CLK_SRC_PLL,
+};
+
+static struct w100_gpio_regs e750_w100_gpio_info = {
+	.init_data1 = 0x01192f1b,
+	.gpio_dir1  = 0xd5ffdeff,
+	.gpio_oe1   = 0x000020bf,
+	.init_data2 = 0x010f010f,
+	.gpio_dir2  = 0xffffffff,
+	.gpio_oe2   = 0x000001cf,
+};
+
+static struct w100fb_mach_info e750_fb_info = {
+	.modelist   = &e750_lcd_mode,
+	.num_modes  = 1,
+	.regs       = &e750_lcd_regs,
+	.gpio       = &e750_w100_gpio_info,
+	.xtal_freq  = 14318000,
+	.xtal_dbl   = 1,
+};
+
+static struct resource e750_fb_resources[] = {
+	[0] = {
+		.start          = 0x0c000000,
+		.end            = 0x0cffffff,
+		.flags          = IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device e750_fb_device = {
+	.name           = "w100fb",
+	.id             = -1,
+	.dev            = {
+		.platform_data  = &e750_fb_info,
+	},
+	.num_resources  = ARRAY_SIZE(e750_fb_resources),
+	.resource       = e750_fb_resources,
+};
+
+/* -------------------- e750 MFP parameters -------------------- */
+
+static unsigned long e750_pin_config[] __initdata = {
+	/* Chip selects */
+	GPIO15_nCS_1,   /* CS1 - Flash */
+	GPIO79_nCS_3,   /* CS3 - IMAGEON */
+	GPIO80_nCS_4,   /* CS4 - TMIO */
+
+	/* Clocks */
+	GPIO11_3_6MHz,
+
+	/* BTUART */
+	GPIO42_BTUART_RXD,
+	GPIO43_BTUART_TXD,
+	GPIO44_BTUART_CTS,
+
+	/* TMIO controller */
+	GPIO19_GPIO, /* t7l66xb #PCLR */
+	GPIO45_GPIO, /* t7l66xb #SUSPEND (NOT BTUART!) */
+
+	/* UDC */
+	GPIO13_GPIO,
+	GPIO3_GPIO,
+
+	/* IrDA */
+	GPIO38_GPIO | MFP_LPM_DRIVE_HIGH,
+
+	/* AC97 */
+	GPIO28_AC97_BITCLK,
+	GPIO29_AC97_SDATA_IN_0,
+	GPIO30_AC97_SDATA_OUT,
+	GPIO31_AC97_SYNC,
+
+	/* Audio power control */
+	GPIO4_GPIO,  /* Headphone amp power */
+	GPIO7_GPIO,  /* Speaker amp power */
+	GPIO37_GPIO, /* Headphone detect */
+
+	/* PC Card */
+	GPIO8_GPIO,   /* CD0 */
+	GPIO44_GPIO,  /* CD1 */
+	GPIO11_GPIO,  /* IRQ0 */
+	GPIO6_GPIO,   /* IRQ1 */
+	GPIO27_GPIO,  /* RST0 */
+	GPIO24_GPIO,  /* RST1 */
+	GPIO20_GPIO,  /* PWR0 */
+	GPIO23_GPIO,  /* PWR1 */
+	GPIO48_nPOE,
+	GPIO49_nPWE,
+	GPIO50_nPIOR,
+	GPIO51_nPIOW,
+	GPIO52_nPCE_1,
+	GPIO53_nPCE_2,
+	GPIO54_nPSKTSEL,
+	GPIO55_nPREG,
+	GPIO56_nPWAIT,
+	GPIO57_nIOIS16,
+
+	/* wakeup */
+	GPIO0_GPIO | WAKEUP_ON_EDGE_RISE,
+};
+
+/* ----------------- e750 tc6393xb parameters ------------------ */
+
+static struct tc6393xb_platform_data e750_tc6393xb_info = {
+	.irq_base       = IRQ_BOARD_START,
+	.scr_pll2cr     = 0x0cc1,
+	.scr_gper       = 0,
+	.gpio_base      = -1,
+	.suspend        = &eseries_tmio_suspend,
+	.resume         = &eseries_tmio_resume,
+	.enable         = &eseries_tmio_enable,
+	.disable        = &eseries_tmio_disable,
+};
+
+static struct platform_device e750_tc6393xb_device = {
+	.name           = "tc6393xb",
+	.id             = -1,
+	.dev            = {
+		.platform_data = &e750_tc6393xb_info,
+	},
+	.num_resources = 2,
+	.resource      = eseries_tmio_resources,
+};
+
+/* ------------------------------------------------------------- */
+
+static struct platform_device *e750_devices[] __initdata = {
+	&e750_fb_device,
+	&e750_tc6393xb_device,
+};
+
+static void __init e750_init(void)
+{
+	pxa2xx_mfp_config(ARRAY_AND_SIZE(e750_pin_config));
+	pxa_set_ffuart_info(NULL);
+	pxa_set_btuart_info(NULL);
+	pxa_set_stuart_info(NULL);
+	clk_add_alias("CLK_CK3P6MI", e750_tc6393xb_device.name,
+			"GPIO11_CLK", NULL),
+	eseries_get_tmio_gpios();
+	platform_add_devices(ARRAY_AND_SIZE(e750_devices));
+	pxa_set_udc_info(&e7xx_udc_mach_info);
+	pxa_set_ac97_info(NULL);
+	pxa_set_ficp_info(&e7xx_ficp_platform_data);
+}
+
+MACHINE_START(E750, "Toshiba e750")
+	/* Maintainer: Ian Molton (spyro at f2s.com) */
+	.phys_io	= 0x40000000,
+	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
+	.boot_params	= 0xa0000100,
+	.map_io		= pxa_map_io,
+	.init_irq	= pxa25x_init_irq,
+	.fixup		= eseries_fixup,
+	.init_machine	= e750_init,
+	.timer		= &pxa_timer,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_E800
+/* ------------------------ e800 LCD definitions ------------------------- */
+
+static unsigned long e800_pin_config[] __initdata = {
+	/* AC97 */
+	GPIO28_AC97_BITCLK,
+	GPIO29_AC97_SDATA_IN_0,
+	GPIO30_AC97_SDATA_OUT,
+	GPIO31_AC97_SYNC,
+};
+
+static struct w100_gen_regs e800_lcd_regs = {
+	.lcd_format =            0x00008003,
+	.lcdd_cntl1 =            0x02a00000,
+	.lcdd_cntl2 =            0x0003ffff,
+	.genlcd_cntl1 =          0x000ff2a3,
+	.genlcd_cntl2 =          0x000002a3,
+	.genlcd_cntl3 =          0x000102aa,
+};
+
+static struct w100_mode e800_lcd_mode[2] = {
+	[0] = {
+		.xres            = 480,
+		.yres            = 640,
+		.left_margin     = 52,
+		.right_margin    = 148,
+		.upper_margin    = 2,
+		.lower_margin    = 6,
+		.crtc_ss         = 0x80350034,
+		.crtc_ls         = 0x802b0026,
+		.crtc_gs         = 0x80160016,
+		.crtc_vpos_gs    = 0x00020003,
+		.crtc_rev        = 0x0040001d,
+		.crtc_dclk       = 0xe0000000,
+		.crtc_gclk       = 0x82a50049,
+		.crtc_goe        = 0x80ee001c,
+		.crtc_ps1_active = 0x00000000,
+		.pll_freq        = 128,
+		.pixclk_divider         = 4,
+		.pixclk_divider_rotated = 6,
+		.pixclk_src     = CLK_SRC_PLL,
+		.sysclk_divider  = 0,
+		.sysclk_src     = CLK_SRC_PLL,
+	},
+	[1] = {
+		.xres            = 240,
+		.yres            = 320,
+		.left_margin     = 15,
+		.right_margin    = 88,
+		.upper_margin    = 0,
+		.lower_margin    = 7,
+		.crtc_ss         = 0xd010000f,
+		.crtc_ls         = 0x80070003,
+		.crtc_gs         = 0x80000000,
+		.crtc_vpos_gs    = 0x01460147,
+		.crtc_rev        = 0x00400003,
+		.crtc_dclk       = 0xa1700030,
+		.crtc_gclk       = 0x814b0008,
+		.crtc_goe        = 0x80cc0015,
+		.crtc_ps1_active = 0x00000000,
+		.pll_freq        = 100,
+		.pixclk_divider         = 6, /* Wince uses 14 which gives a */
+		.pixclk_divider_rotated = 6, /* 7MHz Pclk. We use a 14MHz one */
+		.pixclk_src     = CLK_SRC_PLL,
+		.sysclk_divider  = 0,
+		.sysclk_src     = CLK_SRC_PLL,
+	}
+};
+
+
+static struct w100_gpio_regs e800_w100_gpio_info = {
+	.init_data1 = 0xc13fc019,
+	.gpio_dir1  = 0x3e40df7f,
+	.gpio_oe1   = 0x003c3000,
+	.init_data2 = 0x00000000,
+	.gpio_dir2  = 0x00000000,
+	.gpio_oe2   = 0x00000000,
+};
+
+static struct w100_mem_info e800_w100_mem_info = {
+	.ext_cntl        = 0x09640011,
+	.sdram_mode_reg  = 0x00600021,
+	.ext_timing_cntl = 0x10001545,
+	.io_cntl         = 0x7ddd7333,
+	.size            = 0x1fffff,
+};
+
+static void e800_tg_change(struct w100fb_par *par)
+{
+	unsigned long tmp;
+
+	tmp = w100fb_gpio_read(W100_GPIO_PORT_A);
+	if (par->mode->xres == 480)
+		tmp |= 0x100;
+	else
+		tmp &= ~0x100;
+	w100fb_gpio_write(W100_GPIO_PORT_A, tmp);
+}
+
+static struct w100_tg_info e800_tg_info = {
+	.change = e800_tg_change,
+};
+
+static struct w100fb_mach_info e800_fb_info = {
+	.modelist   = e800_lcd_mode,
+	.num_modes  = 2,
+	.regs       = &e800_lcd_regs,
+	.gpio       = &e800_w100_gpio_info,
+	.mem        = &e800_w100_mem_info,
+	.tg         = &e800_tg_info,
+	.xtal_freq  = 16000000,
+};
+
+static struct resource e800_fb_resources[] = {
+	[0] = {
+		.start          = 0x0c000000,
+		.end            = 0x0cffffff,
+		.flags          = IORESOURCE_MEM,
+	},
+};
+
+static struct platform_device e800_fb_device = {
+	.name           = "w100fb",
+	.id             = -1,
+	.dev            = {
+		.platform_data  = &e800_fb_info,
+	},
+	.num_resources  = ARRAY_SIZE(e800_fb_resources),
+	.resource       = e800_fb_resources,
+};
+
+/* --------------------------- UDC definitions --------------------------- */
+
+static struct pxa2xx_udc_mach_info e800_udc_mach_info = {
+	.gpio_vbus   = GPIO_E800_USB_DISC,
+	.gpio_pullup = GPIO_E800_USB_PULLUP,
+	.gpio_pullup_inverted = 1
+};
+
+/* ----------------- e800 tc6393xb parameters ------------------ */
+
+static struct tc6393xb_platform_data e800_tc6393xb_info = {
+	.irq_base       = IRQ_BOARD_START,
+	.scr_pll2cr     = 0x0cc1,
+	.scr_gper       = 0,
+	.gpio_base      = -1,
+	.suspend        = &eseries_tmio_suspend,
+	.resume         = &eseries_tmio_resume,
+	.enable         = &eseries_tmio_enable,
+	.disable        = &eseries_tmio_disable,
+};
+
+static struct platform_device e800_tc6393xb_device = {
+	.name           = "tc6393xb",
+	.id             = -1,
+	.dev            = {
+		.platform_data = &e800_tc6393xb_info,
+	},
+	.num_resources = 2,
+	.resource      = eseries_tmio_resources,
+};
+
+/* ----------------------------------------------------------------------- */
+
+static struct platform_device *e800_devices[] __initdata = {
+	&e800_fb_device,
+	&e800_tc6393xb_device,
+};
+
+static void __init e800_init(void)
+{
+	pxa2xx_mfp_config(ARRAY_AND_SIZE(e800_pin_config));
+	pxa_set_ffuart_info(NULL);
+	pxa_set_btuart_info(NULL);
+	pxa_set_stuart_info(NULL);
+	clk_add_alias("CLK_CK3P6MI", e800_tc6393xb_device.name,
+			"GPIO11_CLK", NULL),
+	eseries_get_tmio_gpios();
+	platform_add_devices(ARRAY_AND_SIZE(e800_devices));
+	pxa_set_udc_info(&e800_udc_mach_info);
+	pxa_set_ac97_info(NULL);
+}
+
+MACHINE_START(E800, "Toshiba e800")
+	/* Maintainer: Ian Molton (spyro at f2s.com) */
+	.phys_io	= 0x40000000,
+	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
+	.boot_params	= 0xa0000100,
+	.map_io		= pxa_map_io,
+	.init_irq	= pxa25x_init_irq,
+	.fixup		= eseries_fixup,
+	.init_machine	= e800_init,
+	.timer		= &pxa_timer,
+MACHINE_END
+#endif
-- 
1.7.1



From lhrossouw at gmail.com  Mon Jun 21 10:30:56 2010
From: lhrossouw at gmail.com (Lucas)
Date: Mon, 21 Jun 2010 14:30:56 +0000 (UTC)
Subject: [PATCH] Fix AT91SAM9G20 reset
References: <20100528153725.GA5102@axolotl.localnet>
Message-ID: <loom.20100621T162410-494@post.gmane.org>

Peter Horton <phorton <at> bitbox.co.uk> writes:

> 
> Fix AT91SAM9G20 as per the errata in the datasheet.
> 
> If the SDRAM is not cleanly shutdown before reset it can be left driving
> the bus, which then stops the bootloader booting from NAND.
> 
> Signed-off-by: Peter Horton <phorton <at> bitbox.co.uk>
> --
> 


Hi Peter,

Any Idea how to implement this for the WDT and hardware reset(NRST)?
A hardware reset sometimes still stops the bootloader booting from NAND.

Lucas 




From will.deacon at arm.com  Mon Jun 21 10:35:12 2010
From: will.deacon at arm.com (Will Deacon)
Date: Mon, 21 Jun 2010 15:35:12 +0100
Subject: [PATCH] OMAP3: pmu: make CPU_HAS_PMU dependent on OMAP3_EMU
References: <1274972448-10721-1-git-send-email-will.deacon@arm.com>
	<AANLkTikIiLybBr-wV_SRWFNLkZn892gwsWHCxsIYenFJ@mail.gmail.com> 
Message-ID: <002f01cb114e$f5546060$dffd2120$@deacon@arm.com>

Hello,

* I wrote: 

> Tony: would you mind picking this patch up please or would
> you prefer that I posted it to Russell's patch system?

Since this only modifies arch/arm/KConfig and Jean has acked it,
I've submitted it to Russell's patch system as #6195/1.

Will




From catalin.marinas at arm.com  Mon Jun 21 10:46:21 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 15:46:21 +0100
Subject: [PATCH v4 0/4] Patches for -next
Message-ID: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>

Pretty much the same content as v3 but I reordered the last three
patches to make sure that switching to lazy cache flushing on ARMv7 SMP
doesn't make the set_pte/cache flushing race more visible (issue handled
by the set_pte_at patch).


Catalin Marinas (4):
      ARM: Remove the domain switching on ARMv6k/v7 CPUs
      ARM: Assume new page cache pages have dirty D-cache
      ARM: Synchronise the I and D caches via set_pte_at() on SMP systems
      ARM: Use lazy cache flushing on ARMv7 SMP systems


 arch/arm/include/asm/assembler.h  |   13 +++---
 arch/arm/include/asm/cacheflush.h |    6 +--
 arch/arm/include/asm/domain.h     |   31 +++++++++++++-
 arch/arm/include/asm/futex.h      |    9 ++--
 arch/arm/include/asm/pgtable.h    |   25 ++++++++++-
 arch/arm/include/asm/smp_plat.h   |    4 ++
 arch/arm/include/asm/tlbflush.h   |   12 ++++-
 arch/arm/include/asm/traps.h      |    2 +
 arch/arm/include/asm/uaccess.h    |   16 ++++---
 arch/arm/kernel/entry-armv.S      |    4 +-
 arch/arm/kernel/fiq.c             |    5 ++
 arch/arm/kernel/traps.c           |   14 ++++--
 arch/arm/lib/getuser.S            |   13 +++---
 arch/arm/lib/putuser.S            |   29 +++++++------
 arch/arm/lib/uaccess.S            |   83 +++++++++++++++++++------------------
 arch/arm/mm/Kconfig               |    8 ++++
 arch/arm/mm/copypage-v4mc.c       |    2 -
 arch/arm/mm/copypage-v6.c         |    2 -
 arch/arm/mm/copypage-xscale.c     |    2 -
 arch/arm/mm/dma-mapping.c         |    6 +++
 arch/arm/mm/fault-armv.c          |    8 ++--
 arch/arm/mm/flush.c               |   31 +++++++++-----
 arch/arm/mm/mmu.c                 |    6 +--
 arch/arm/mm/proc-macros.S         |    7 +++
 arch/arm/mm/proc-v7.S             |    5 +-
 25 files changed, 226 insertions(+), 117 deletions(-)

-- 
Catalin


From catalin.marinas at arm.com  Mon Jun 21 10:46:26 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 15:46:26 +0100
Subject: [PATCH v4 1/4] ARM: Remove the domain switching on ARMv6k/v7 CPUs
In-Reply-To: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
References: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621144626.26309.59790.stgit@e102109-lin.cambridge.arm.com>

This patch removes the domain switching functionality via the set_fs and
__switch_to functions on cores that have a TLS register.

Currently, the ioremap and vmalloc areas share the same level 1 page
tables and therefore have the same domain (DOMAIN_KERNEL). When the
kernel domain is modified from Client to Manager (via the __set_fs or in
the __switch_to function), the XN (eXecute Never) bit is overridden and
newer CPUs can speculatively prefetch the ioremap'ed memory.

Linux performs the kernel domain switching to allow user-specific
functions (copy_to/from_user, get/put_user etc.) to access kernel
memory. In order for these functions to work with the kernel domain set
to Client, the patch modifies the LDRT/STRT and related instructions to
the LDR/STR ones.

The user pages access rights are also modified for kernel read-only
access rather than read/write so that the copy-on-write mechanism still
works. CPU_USE_DOMAINS gets disabled only if HAS_TLS_REG is defined
since writing the TLS value to the high vectors page isn't possible.

The user addresses passed to the kernel are checked by the access_ok()
function so that they do not point to the kernel space.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/assembler.h |   13 +++---
 arch/arm/include/asm/domain.h    |   31 +++++++++++++-
 arch/arm/include/asm/futex.h     |    9 ++--
 arch/arm/include/asm/traps.h     |    2 +
 arch/arm/include/asm/uaccess.h   |   16 ++++---
 arch/arm/kernel/entry-armv.S     |    4 +-
 arch/arm/kernel/fiq.c            |    5 ++
 arch/arm/kernel/traps.c          |   14 +++++-
 arch/arm/lib/getuser.S           |   13 +++---
 arch/arm/lib/putuser.S           |   29 +++++++------
 arch/arm/lib/uaccess.S           |   83 +++++++++++++++++++-------------------
 arch/arm/mm/Kconfig              |    8 ++++
 arch/arm/mm/mmu.c                |    6 +--
 arch/arm/mm/proc-macros.S        |    7 +++
 arch/arm/mm/proc-v7.S            |    5 +-
 15 files changed, 153 insertions(+), 92 deletions(-)

diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 6e8f05c..66db132 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -18,6 +18,7 @@
 #endif
 
 #include <asm/ptrace.h>
+#include <asm/domain.h>
 
 /*
  * Endian independent macros for shifting bytes within registers.
@@ -183,12 +184,12 @@
  */
 #ifdef CONFIG_THUMB2_KERNEL
 
-	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort
+	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort, t=T()
 9999:
 	.if	\inc == 1
-	\instr\cond\()bt \reg, [\ptr, #\off]
+	\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
 	.elseif	\inc == 4
-	\instr\cond\()t \reg, [\ptr, #\off]
+	\instr\cond\()\t\().w \reg, [\ptr, #\off]
 	.else
 	.error	"Unsupported inc macro argument"
 	.endif
@@ -223,13 +224,13 @@
 
 #else	/* !CONFIG_THUMB2_KERNEL */
 
-	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort
+	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort, t=T()
 	.rept	\rept
 9999:
 	.if	\inc == 1
-	\instr\cond\()bt \reg, [\ptr], #\inc
+	\instr\cond\()b\()\t \reg, [\ptr], #\inc
 	.elseif	\inc == 4
-	\instr\cond\()t \reg, [\ptr], #\inc
+	\instr\cond\()\t \reg, [\ptr], #\inc
 	.else
 	.error	"Unsupported inc macro argument"
 	.endif
diff --git a/arch/arm/include/asm/domain.h b/arch/arm/include/asm/domain.h
index cc7ef40..af18cea 100644
--- a/arch/arm/include/asm/domain.h
+++ b/arch/arm/include/asm/domain.h
@@ -45,13 +45,17 @@
  */
 #define DOMAIN_NOACCESS	0
 #define DOMAIN_CLIENT	1
+#ifdef CONFIG_CPU_USE_DOMAINS
 #define DOMAIN_MANAGER	3
+#else
+#define DOMAIN_MANAGER	1
+#endif
 
 #define domain_val(dom,type)	((type) << (2*(dom)))
 
 #ifndef __ASSEMBLY__
 
-#ifdef CONFIG_MMU
+#ifdef CONFIG_CPU_USE_DOMAINS
 #define set_domain(x)					\
 	do {						\
 	__asm__ __volatile__(				\
@@ -74,5 +78,28 @@
 #define modify_domain(dom,type)	do { } while (0)
 #endif
 
+/*
+ * Generate the T (user) versions of the LDR/STR and related
+ * instructions (inline assembly)
+ */
+#ifdef CONFIG_CPU_USE_DOMAINS
+#define T(instr)	#instr "t"
+#else
+#define T(instr)	#instr
 #endif
-#endif /* !__ASSEMBLY__ */
+
+#else /* __ASSEMBLY__ */
+
+/*
+ * Generate the T (user) versions of the LDR/STR and related
+ * instructions
+ */
+#ifdef CONFIG_CPU_USE_DOMAINS
+#define T(instr)	instr ## t
+#else
+#define T(instr)	instr
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* !__ASM_PROC_DOMAIN_H */
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 540a044..b33fe70 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -13,12 +13,13 @@
 #include <linux/preempt.h>
 #include <linux/uaccess.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 #define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)	\
 	__asm__ __volatile__(					\
-	"1:	ldrt	%1, [%2]\n"				\
+	"1:	" T(ldr) "	%1, [%2]\n"			\
 	"	" insn "\n"					\
-	"2:	strt	%0, [%2]\n"				\
+	"2:	" T(str) "	%0, [%2]\n"			\
 	"	mov	%0, #0\n"				\
 	"3:\n"							\
 	"	.pushsection __ex_table,\"a\"\n"		\
@@ -97,10 +98,10 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
 	pagefault_disable();	/* implies preempt_disable() */
 
 	__asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
-	"1:	ldrt	%0, [%3]\n"
+	"1:	" T(ldr) "	%0, [%3]\n"
 	"	teq	%0, %1\n"
 	"	it	eq	@ explicit IT needed for the 2b label\n"
-	"2:	streqt	%2, [%3]\n"
+	"2:	" T(streq) "	%2, [%3]\n"
 	"3:\n"
 	"	.pushsection __ex_table,\"a\"\n"
 	"	.align	3\n"
diff --git a/arch/arm/include/asm/traps.h b/arch/arm/include/asm/traps.h
index 491960b..af5d5d1 100644
--- a/arch/arm/include/asm/traps.h
+++ b/arch/arm/include/asm/traps.h
@@ -27,4 +27,6 @@ static inline int in_exception_text(unsigned long ptr)
 extern void __init early_trap_init(void);
 extern void dump_backtrace_entry(unsigned long where, unsigned long from, unsigned long frame);
 
+extern void *vectors_page;
+
 #endif
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 33e4a48..b293616 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -227,7 +227,7 @@ do {									\
 
 #define __get_user_asm_byte(x,addr,err)				\
 	__asm__ __volatile__(					\
-	"1:	ldrbt	%1,[%2]\n"				\
+	"1:	" T(ldrb) "	%1,[%2],#0\n"			\
 	"2:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
@@ -263,7 +263,7 @@ do {									\
 
 #define __get_user_asm_word(x,addr,err)				\
 	__asm__ __volatile__(					\
-	"1:	ldrt	%1,[%2]\n"				\
+	"1:	" T(ldr) "	%1,[%2],#0\n"			\
 	"2:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
@@ -308,7 +308,7 @@ do {									\
 
 #define __put_user_asm_byte(x,__pu_addr,err)			\
 	__asm__ __volatile__(					\
-	"1:	strbt	%1,[%2]\n"				\
+	"1:	" T(strb) "	%1,[%2],#0\n"			\
 	"2:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
@@ -341,7 +341,7 @@ do {									\
 
 #define __put_user_asm_word(x,__pu_addr,err)			\
 	__asm__ __volatile__(					\
-	"1:	strt	%1,[%2]\n"				\
+	"1:	" T(str) "	%1,[%2],#0\n"			\
 	"2:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
@@ -366,10 +366,10 @@ do {									\
 
 #define __put_user_asm_dword(x,__pu_addr,err)			\
 	__asm__ __volatile__(					\
- ARM(	"1:	strt	" __reg_oper1 ", [%1], #4\n"	)	\
- ARM(	"2:	strt	" __reg_oper0 ", [%1]\n"	)	\
- THUMB(	"1:	strt	" __reg_oper1 ", [%1]\n"	)	\
- THUMB(	"2:	strt	" __reg_oper0 ", [%1, #4]\n"	)	\
+ ARM(	"1:	" T(str) "	" __reg_oper1 ", [%1], #4\n"	)	\
+ ARM(	"2:	" T(str) "	" __reg_oper0 ", [%1]\n"	)	\
+ THUMB(	"1:	" T(str) "	" __reg_oper1 ", [%1]\n"	)	\
+ THUMB(	"2:	" T(str) "	" __reg_oper0 ", [%1, #4]\n"	)	\
 	"3:\n"							\
 	"	.pushsection .fixup,\"ax\"\n"			\
 	"	.align	2\n"					\
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 7ee48e7..ba654fa 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -736,7 +736,7 @@ ENTRY(__switch_to)
  THUMB(	stmia	ip!, {r4 - sl, fp}	   )	@ Store most regs on stack
  THUMB(	str	sp, [ip], #4		   )
  THUMB(	str	lr, [ip], #4		   )
-#ifdef CONFIG_MMU
+#ifdef CONFIG_CPU_USE_DOMAINS
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
 #if defined(CONFIG_HAS_TLS_REG)
@@ -745,7 +745,7 @@ ENTRY(__switch_to)
 	mov	r4, #0xffff0fff
 	str	r3, [r4, #-15]			@ TLS val at 0xffff0ff0
 #endif
-#ifdef CONFIG_MMU
+#ifdef CONFIG_CPU_USE_DOMAINS
 	mcr	p15, 0, r6, c3, c0, 0		@ Set domain register
 #endif
 	mov	r5, r0
diff --git a/arch/arm/kernel/fiq.c b/arch/arm/kernel/fiq.c
index 6ff7919..d601ef2 100644
--- a/arch/arm/kernel/fiq.c
+++ b/arch/arm/kernel/fiq.c
@@ -45,6 +45,7 @@
 #include <asm/fiq.h>
 #include <asm/irq.h>
 #include <asm/system.h>
+#include <asm/traps.h>
 
 static unsigned long no_fiq_insn;
 
@@ -77,7 +78,11 @@ int show_fiq_list(struct seq_file *p, void *v)
 
 void set_fiq_handler(void *start, unsigned int length)
 {
+#if defined(CONFIG_CPU_USE_DOMAINS)
 	memcpy((void *)0xffff001c, start, length);
+#else
+	memcpy(vectors_page + 0x1c, start, length);
+#endif
 	flush_icache_range(0xffff001c, 0xffff001c + length);
 	if (!vectors_high())
 		flush_icache_range(0x1c, 0x1c + length);
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1621e53..6bc57c5 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -36,6 +36,8 @@
 
 static const char *handler[]= { "prefetch abort", "data abort", "address exception", "interrupt" };
 
+void *vectors_page;
+
 #ifdef CONFIG_DEBUG_USER
 unsigned int user_debug;
 
@@ -745,7 +747,11 @@ void __init trap_init(void)
 
 void __init early_trap_init(void)
 {
+#if defined(CONFIG_CPU_USE_DOMAINS)
 	unsigned long vectors = CONFIG_VECTORS_BASE;
+#else
+	unsigned long vectors = (unsigned long)vectors_page;
+#endif
 	extern char __stubs_start[], __stubs_end[];
 	extern char __vectors_start[], __vectors_end[];
 	extern char __kuser_helper_start[], __kuser_helper_end[];
@@ -764,10 +770,10 @@ void __init early_trap_init(void)
 	 * Copy signal return handlers into the vector page, and
 	 * set sigreturn to be a pointer to these.
 	 */
-	memcpy((void *)KERN_SIGRETURN_CODE, sigreturn_codes,
-	       sizeof(sigreturn_codes));
-	memcpy((void *)KERN_RESTART_CODE, syscall_restart_code,
-	       sizeof(syscall_restart_code));
+	memcpy((void *)(vectors + KERN_SIGRETURN_CODE - CONFIG_VECTORS_BASE),
+	       sigreturn_codes, sizeof(sigreturn_codes));
+	memcpy((void *)(vectors + KERN_RESTART_CODE - CONFIG_VECTORS_BASE),
+	       syscall_restart_code, sizeof(syscall_restart_code));
 
 	flush_icache_range(vectors, vectors + PAGE_SIZE);
 	modify_domain(DOMAIN_USER, DOMAIN_CLIENT);
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index b1631a7..1b049cd 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -28,20 +28,21 @@
  */
 #include <linux/linkage.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 ENTRY(__get_user_1)
-1:	ldrbt	r2, [r0]
+1:	T(ldrb)	r2, [r0]
 	mov	r0, #0
 	mov	pc, lr
 ENDPROC(__get_user_1)
 
 ENTRY(__get_user_2)
 #ifdef CONFIG_THUMB2_KERNEL
-2:	ldrbt	r2, [r0]
-3:	ldrbt	r3, [r0, #1]
+2:	T(ldrb)	r2, [r0]
+3:	T(ldrb)	r3, [r0, #1]
 #else
-2:	ldrbt	r2, [r0], #1
-3:	ldrbt	r3, [r0]
+2:	T(ldrb)	r2, [r0], #1
+3:	T(ldrb)	r3, [r0]
 #endif
 #ifndef __ARMEB__
 	orr	r2, r2, r3, lsl #8
@@ -53,7 +54,7 @@ ENTRY(__get_user_2)
 ENDPROC(__get_user_2)
 
 ENTRY(__get_user_4)
-4:	ldrt	r2, [r0]
+4:	T(ldr)	r2, [r0]
 	mov	r0, #0
 	mov	pc, lr
 ENDPROC(__get_user_4)
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index 5a01a23..c023fc1 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -28,9 +28,10 @@
  */
 #include <linux/linkage.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 ENTRY(__put_user_1)
-1:	strbt	r2, [r0]
+1:	T(strb)	r2, [r0]
 	mov	r0, #0
 	mov	pc, lr
 ENDPROC(__put_user_1)
@@ -39,19 +40,19 @@ ENTRY(__put_user_2)
 	mov	ip, r2, lsr #8
 #ifdef CONFIG_THUMB2_KERNEL
 #ifndef __ARMEB__
-2:	strbt	r2, [r0]
-3:	strbt	ip, [r0, #1]
+2:	T(strb)	r2, [r0]
+3:	T(strb)	ip, [r0, #1]
 #else
-2:	strbt	ip, [r0]
-3:	strbt	r2, [r0, #1]
+2:	T(strb)	ip, [r0]
+3:	T(strb)	r2, [r0, #1]
 #endif
 #else	/* !CONFIG_THUMB2_KERNEL */
 #ifndef __ARMEB__
-2:	strbt	r2, [r0], #1
-3:	strbt	ip, [r0]
+2:	T(strb)	r2, [r0], #1
+3:	T(strb)	ip, [r0]
 #else
-2:	strbt	ip, [r0], #1
-3:	strbt	r2, [r0]
+2:	T(strb)	ip, [r0], #1
+3:	T(strb)	r2, [r0]
 #endif
 #endif	/* CONFIG_THUMB2_KERNEL */
 	mov	r0, #0
@@ -59,18 +60,18 @@ ENTRY(__put_user_2)
 ENDPROC(__put_user_2)
 
 ENTRY(__put_user_4)
-4:	strt	r2, [r0]
+4:	T(str)	r2, [r0]
 	mov	r0, #0
 	mov	pc, lr
 ENDPROC(__put_user_4)
 
 ENTRY(__put_user_8)
 #ifdef CONFIG_THUMB2_KERNEL
-5:	strt	r2, [r0]
-6:	strt	r3, [r0, #4]
+5:	T(str)	r2, [r0]
+6:	T(str)	r3, [r0, #4]
 #else
-5:	strt	r2, [r0], #4
-6:	strt	r3, [r0]
+5:	T(str)	r2, [r0], #4
+6:	T(str)	r3, [r0]
 #endif
 	mov	r0, #0
 	mov	pc, lr
diff --git a/arch/arm/lib/uaccess.S b/arch/arm/lib/uaccess.S
index fee9f6f..d0ece2a 100644
--- a/arch/arm/lib/uaccess.S
+++ b/arch/arm/lib/uaccess.S
@@ -14,6 +14,7 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
 #include <asm/errno.h>
+#include <asm/domain.h>
 
 		.text
 
@@ -31,11 +32,11 @@
 		rsb	ip, ip, #4
 		cmp	ip, #2
 		ldrb	r3, [r1], #1
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		ldrgeb	r3, [r1], #1
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		ldrgtb	r3, [r1], #1
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		sub	r2, r2, ip
 		b	.Lc2u_dest_aligned
 
@@ -58,7 +59,7 @@ ENTRY(__copy_to_user)
 		addmi	ip, r2, #4
 		bmi	.Lc2u_0nowords
 		ldr	r3, [r1], #4
-USER(		strt	r3, [r0], #4)			@ May fault
+USER(		T(str)	r3, [r0], #4)			@ May fault
 		mov	ip, r0, lsl #32 - PAGE_SHIFT	@ On each page, use a ld/st??t instruction
 		rsb	ip, ip, #0
 		movs	ip, ip, lsr #32 - PAGE_SHIFT
@@ -87,18 +88,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		stmneia	r0!, {r3 - r4}			@ Shouldnt fault
 		tst	ip, #4
 		ldrne	r3, [r1], #4
-		strnet	r3, [r0], #4			@ Shouldnt fault
+		T(strne) r3, [r0], #4			@ Shouldnt fault
 		ands	ip, ip, #3
 		beq	.Lc2u_0fupi
 .Lc2u_0nowords:	teq	ip, #0
 		beq	.Lc2u_finished
 .Lc2u_nowords:	cmp	ip, #2
 		ldrb	r3, [r1], #1
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		ldrgeb	r3, [r1], #1
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		ldrgtb	r3, [r1], #1
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		b	.Lc2u_finished
 
 .Lc2u_not_enough:
@@ -119,7 +120,7 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
 		mov	r3, r7, pull #8
 		ldr	r7, [r1], #4
 		orr	r3, r3, r7, push #24
-USER(		strt	r3, [r0], #4)			@ May fault
+USER(		T(str)	r3, [r0], #4)			@ May fault
 		mov	ip, r0, lsl #32 - PAGE_SHIFT
 		rsb	ip, ip, #0
 		movs	ip, ip, lsr #32 - PAGE_SHIFT
@@ -154,18 +155,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		movne	r3, r7, pull #8
 		ldrne	r7, [r1], #4
 		orrne	r3, r3, r7, push #24
-		strnet	r3, [r0], #4			@ Shouldnt fault
+		T(strne) r3, [r0], #4			@ Shouldnt fault
 		ands	ip, ip, #3
 		beq	.Lc2u_1fupi
 .Lc2u_1nowords:	mov	r3, r7, get_byte_1
 		teq	ip, #0
 		beq	.Lc2u_finished
 		cmp	ip, #2
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		movge	r3, r7, get_byte_2
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		movgt	r3, r7, get_byte_3
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		b	.Lc2u_finished
 
 .Lc2u_2fupi:	subs	r2, r2, #4
@@ -174,7 +175,7 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
 		mov	r3, r7, pull #16
 		ldr	r7, [r1], #4
 		orr	r3, r3, r7, push #16
-USER(		strt	r3, [r0], #4)			@ May fault
+USER(		T(str)	r3, [r0], #4)			@ May fault
 		mov	ip, r0, lsl #32 - PAGE_SHIFT
 		rsb	ip, ip, #0
 		movs	ip, ip, lsr #32 - PAGE_SHIFT
@@ -209,18 +210,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		movne	r3, r7, pull #16
 		ldrne	r7, [r1], #4
 		orrne	r3, r3, r7, push #16
-		strnet	r3, [r0], #4			@ Shouldnt fault
+		T(strne) r3, [r0], #4			@ Shouldnt fault
 		ands	ip, ip, #3
 		beq	.Lc2u_2fupi
 .Lc2u_2nowords:	mov	r3, r7, get_byte_2
 		teq	ip, #0
 		beq	.Lc2u_finished
 		cmp	ip, #2
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		movge	r3, r7, get_byte_3
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		ldrgtb	r3, [r1], #0
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		b	.Lc2u_finished
 
 .Lc2u_3fupi:	subs	r2, r2, #4
@@ -229,7 +230,7 @@ USER(		strgtbt	r3, [r0], #1)			@ May fault
 		mov	r3, r7, pull #24
 		ldr	r7, [r1], #4
 		orr	r3, r3, r7, push #8
-USER(		strt	r3, [r0], #4)			@ May fault
+USER(		T(str)	r3, [r0], #4)			@ May fault
 		mov	ip, r0, lsl #32 - PAGE_SHIFT
 		rsb	ip, ip, #0
 		movs	ip, ip, lsr #32 - PAGE_SHIFT
@@ -264,18 +265,18 @@ USER(		strt	r3, [r0], #4)			@ May fault
 		movne	r3, r7, pull #24
 		ldrne	r7, [r1], #4
 		orrne	r3, r3, r7, push #8
-		strnet	r3, [r0], #4			@ Shouldnt fault
+		T(strne) r3, [r0], #4			@ Shouldnt fault
 		ands	ip, ip, #3
 		beq	.Lc2u_3fupi
 .Lc2u_3nowords:	mov	r3, r7, get_byte_3
 		teq	ip, #0
 		beq	.Lc2u_finished
 		cmp	ip, #2
-USER(		strbt	r3, [r0], #1)			@ May fault
+USER(		T(strb)	r3, [r0], #1)			@ May fault
 		ldrgeb	r3, [r1], #1
-USER(		strgebt	r3, [r0], #1)			@ May fault
+USER(		T(strgeb) r3, [r0], #1)			@ May fault
 		ldrgtb	r3, [r1], #0
-USER(		strgtbt	r3, [r0], #1)			@ May fault
+USER(		T(strgtb) r3, [r0], #1)			@ May fault
 		b	.Lc2u_finished
 ENDPROC(__copy_to_user)
 
@@ -294,11 +295,11 @@ ENDPROC(__copy_to_user)
 .Lcfu_dest_not_aligned:
 		rsb	ip, ip, #4
 		cmp	ip, #2
-USER(		ldrbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrb)	r3, [r1], #1)			@ May fault
 		strb	r3, [r0], #1
-USER(		ldrgebt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgeb) r3, [r1], #1)			@ May fault
 		strgeb	r3, [r0], #1
-USER(		ldrgtbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgtb) r3, [r1], #1)			@ May fault
 		strgtb	r3, [r0], #1
 		sub	r2, r2, ip
 		b	.Lcfu_dest_aligned
@@ -321,7 +322,7 @@ ENTRY(__copy_from_user)
 .Lcfu_0fupi:	subs	r2, r2, #4
 		addmi	ip, r2, #4
 		bmi	.Lcfu_0nowords
-USER(		ldrt	r3, [r1], #4)
+USER(		T(ldr)	r3, [r1], #4)
 		str	r3, [r0], #4
 		mov	ip, r1, lsl #32 - PAGE_SHIFT	@ On each page, use a ld/st??t instruction
 		rsb	ip, ip, #0
@@ -350,18 +351,18 @@ USER(		ldrt	r3, [r1], #4)
 		ldmneia	r1!, {r3 - r4}			@ Shouldnt fault
 		stmneia	r0!, {r3 - r4}
 		tst	ip, #4
-		ldrnet	r3, [r1], #4			@ Shouldnt fault
+		T(ldrne) r3, [r1], #4			@ Shouldnt fault
 		strne	r3, [r0], #4
 		ands	ip, ip, #3
 		beq	.Lcfu_0fupi
 .Lcfu_0nowords:	teq	ip, #0
 		beq	.Lcfu_finished
 .Lcfu_nowords:	cmp	ip, #2
-USER(		ldrbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrb)	r3, [r1], #1)			@ May fault
 		strb	r3, [r0], #1
-USER(		ldrgebt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgeb) r3, [r1], #1)			@ May fault
 		strgeb	r3, [r0], #1
-USER(		ldrgtbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgtb) r3, [r1], #1)			@ May fault
 		strgtb	r3, [r0], #1
 		b	.Lcfu_finished
 
@@ -374,7 +375,7 @@ USER(		ldrgtbt	r3, [r1], #1)			@ May fault
 
 .Lcfu_src_not_aligned:
 		bic	r1, r1, #3
-USER(		ldrt	r7, [r1], #4)			@ May fault
+USER(		T(ldr)	r7, [r1], #4)			@ May fault
 		cmp	ip, #2
 		bgt	.Lcfu_3fupi
 		beq	.Lcfu_2fupi
@@ -382,7 +383,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		addmi	ip, r2, #4
 		bmi	.Lcfu_1nowords
 		mov	r3, r7, pull #8
-USER(		ldrt	r7, [r1], #4)			@ May fault
+USER(		T(ldr)	r7, [r1], #4)			@ May fault
 		orr	r3, r3, r7, push #24
 		str	r3, [r0], #4
 		mov	ip, r1, lsl #32 - PAGE_SHIFT
@@ -417,7 +418,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		stmneia	r0!, {r3 - r4}
 		tst	ip, #4
 		movne	r3, r7, pull #8
-USER(		ldrnet	r7, [r1], #4)			@ May fault
+USER(		T(ldrne) r7, [r1], #4)			@ May fault
 		orrne	r3, r3, r7, push #24
 		strne	r3, [r0], #4
 		ands	ip, ip, #3
@@ -437,7 +438,7 @@ USER(		ldrnet	r7, [r1], #4)			@ May fault
 		addmi	ip, r2, #4
 		bmi	.Lcfu_2nowords
 		mov	r3, r7, pull #16
-USER(		ldrt	r7, [r1], #4)			@ May fault
+USER(		T(ldr)	r7, [r1], #4)			@ May fault
 		orr	r3, r3, r7, push #16
 		str	r3, [r0], #4
 		mov	ip, r1, lsl #32 - PAGE_SHIFT
@@ -473,7 +474,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		stmneia	r0!, {r3 - r4}
 		tst	ip, #4
 		movne	r3, r7, pull #16
-USER(		ldrnet	r7, [r1], #4)			@ May fault
+USER(		T(ldrne) r7, [r1], #4)			@ May fault
 		orrne	r3, r3, r7, push #16
 		strne	r3, [r0], #4
 		ands	ip, ip, #3
@@ -485,7 +486,7 @@ USER(		ldrnet	r7, [r1], #4)			@ May fault
 		strb	r3, [r0], #1
 		movge	r3, r7, get_byte_3
 		strgeb	r3, [r0], #1
-USER(		ldrgtbt	r3, [r1], #0)			@ May fault
+USER(		T(ldrgtb) r3, [r1], #0)			@ May fault
 		strgtb	r3, [r0], #1
 		b	.Lcfu_finished
 
@@ -493,7 +494,7 @@ USER(		ldrgtbt	r3, [r1], #0)			@ May fault
 		addmi	ip, r2, #4
 		bmi	.Lcfu_3nowords
 		mov	r3, r7, pull #24
-USER(		ldrt	r7, [r1], #4)			@ May fault
+USER(		T(ldr)	r7, [r1], #4)			@ May fault
 		orr	r3, r3, r7, push #8
 		str	r3, [r0], #4
 		mov	ip, r1, lsl #32 - PAGE_SHIFT
@@ -528,7 +529,7 @@ USER(		ldrt	r7, [r1], #4)			@ May fault
 		stmneia	r0!, {r3 - r4}
 		tst	ip, #4
 		movne	r3, r7, pull #24
-USER(		ldrnet	r7, [r1], #4)			@ May fault
+USER(		T(ldrne) r7, [r1], #4)			@ May fault
 		orrne	r3, r3, r7, push #8
 		strne	r3, [r0], #4
 		ands	ip, ip, #3
@@ -538,9 +539,9 @@ USER(		ldrnet	r7, [r1], #4)			@ May fault
 		beq	.Lcfu_finished
 		cmp	ip, #2
 		strb	r3, [r0], #1
-USER(		ldrgebt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgeb) r3, [r1], #1)			@ May fault
 		strgeb	r3, [r0], #1
-USER(		ldrgtbt	r3, [r1], #1)			@ May fault
+USER(		T(ldrgtb) r3, [r1], #1)			@ May fault
 		strgtb	r3, [r0], #1
 		b	.Lcfu_finished
 ENDPROC(__copy_from_user)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..f33c422 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -599,6 +599,14 @@ config CPU_CP15_MPU
 	help
 	  Processor has the CP15 register, which has MPU related registers.
 
+config CPU_USE_DOMAINS
+	bool
+	depends on MMU
+	default y if !HAS_TLS_REG
+	help
+	  This option enables or disables the use of domain switching
+	  via the set_fs() function.
+
 #
 # CPU supports 36-bit I/O
 #
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 2858941..499e22d 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -25,6 +25,7 @@
 #include <asm/smp_plat.h>
 #include <asm/tlb.h>
 #include <asm/highmem.h>
+#include <asm/traps.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -935,12 +936,11 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 {
 	struct map_desc map;
 	unsigned long addr;
-	void *vectors;
 
 	/*
 	 * Allocate the vector page early.
 	 */
-	vectors = alloc_bootmem_low_pages(PAGE_SIZE);
+	vectors_page = alloc_bootmem_low_pages(PAGE_SIZE);
 
 	for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE)
 		pmd_clear(pmd_off_k(addr));
@@ -980,7 +980,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc)
 	 * location (0xffff0000).  If we aren't using high-vectors, also
 	 * create a mapping at the low-vectors virtual address.
 	 */
-	map.pfn = __phys_to_pfn(virt_to_phys(vectors));
+	map.pfn = __phys_to_pfn(virt_to_phys(vectors_page));
 	map.virtual = 0xffff0000;
 	map.length = PAGE_SIZE;
 	map.type = MT_HIGH_VECTORS;
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 7d63bea..337f102 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -99,6 +99,10 @@
  *  110x   0   1   0	r/w	r/o
  *  11x0   0   1   0	r/w	r/o
  *  1111   0   1   1	r/w	r/w
+ *
+ * If !CONFIG_CPU_USE_DOMAINS, the following permissions are changed:
+ *  110x   1   1   1	r/o	r/o
+ *  11x0   1   1   1	r/o	r/o
  */
 	.macro	armv6_mt_table pfx
 \pfx\()_mt_table:
@@ -138,8 +142,11 @@
 
 	tst	r1, #L_PTE_USER
 	orrne	r3, r3, #PTE_EXT_AP1
+#ifdef CONFIG_CPU_USE_DOMAINS
+	@ allow kernel read/write access to read-only user pages
 	tstne	r3, #PTE_EXT_APX
 	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+#endif
 
 	tst	r1, #L_PTE_EXEC
 	orreq	r3, r3, #PTE_EXT_XN
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a..c1c3fe0 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -152,8 +152,11 @@ ENTRY(cpu_v7_set_pte_ext)
 
 	tst	r1, #L_PTE_USER
 	orrne	r3, r3, #PTE_EXT_AP1
+#ifdef CONFIG_CPU_USE_DOMAINS
+	@ allow kernel read/write access to read-only user pages
 	tstne	r3, #PTE_EXT_APX
 	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
+#endif
 
 	tst	r1, #L_PTE_EXEC
 	orreq	r3, r3, #PTE_EXT_XN
@@ -240,8 +243,6 @@ __v7_setup:
 	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
 	orr	r4, r4, #TTB_FLAGS
 	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
-	mov	r10, #0x1f			@ domains 0, 1 = manager
-	mcr	p15, 0, r10, c3, c0, 0		@ load domain access register
 	/*
 	 * Memory region attributes with SCTLR.TRE=1
 	 *



From catalin.marinas at arm.com  Mon Jun 21 10:46:32 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 15:46:32 +0100
Subject: [PATCH v4 2/4] ARM: Assume new page cache pages have dirty D-cache
In-Reply-To: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
References: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621144632.26309.63314.stgit@e102109-lin.cambridge.arm.com>

There are places in Linux where writes to newly allocated page cache
pages happen without a subsequent call to flush_dcache_page() (several
PIO drivers including USB HCD). This patch changes the meaning of
PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly
mapped page in update_mmu_cache().

The patch also sets the PG_arch_1 bit in the DMA cache maintenance
function to avoid additional cache flushing in update_mmu_cache().

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/cacheflush.h |    6 +++---
 arch/arm/include/asm/tlbflush.h   |    2 +-
 arch/arm/mm/copypage-v4mc.c       |    2 +-
 arch/arm/mm/copypage-v6.c         |    2 +-
 arch/arm/mm/copypage-xscale.c     |    2 +-
 arch/arm/mm/dma-mapping.c         |    6 ++++++
 arch/arm/mm/fault-armv.c          |    4 ++--
 arch/arm/mm/flush.c               |    3 ++-
 8 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..d3730f0 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -137,10 +137,10 @@
 #endif
 
 /*
- * This flag is used to indicate that the page pointed to by a pte
- * is dirty and requires cleaning before returning it to the user.
+ * This flag is used to indicate that the page pointed to by a pte is clean
+ * and does not require cleaning before returning it to the user.
  */
-#define PG_dcache_dirty PG_arch_1
+#define PG_dcache_clean PG_arch_1
 
 /*
  *	MM Cache Management
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index bd863d8..40a7092 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -552,7 +552,7 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 #endif
 
 /*
- * if PG_dcache_dirty is set for the page, we need to ensure that any
+ * If PG_dcache_clean is not set for the page, we need to ensure that any
  * cache entries for the kernels virtual memory range are written
  * back to the page.
  */
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 598c51a..b806151 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -73,7 +73,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
 {
 	void *kto = kmap_atomic(to, KM_USER1);
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index f55fa10..bdba6c6 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -79,7 +79,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
 	unsigned int offset = CACHE_COLOUR(vaddr);
 	unsigned long kfrom, kto;
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	/* FIXME: not highmem safe */
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 9920c0a..649bbcd 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -95,7 +95,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
 {
 	void *kto = kmap_atomic(to, KM_USER1);
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 13fa536..bb9b612 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -508,6 +508,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
 		outer_inv_range(paddr, paddr + size);
 
 	dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+
+	/*
+	 * Mark the D-cache clean for this page to avoid extra flushing.
+	 */
+	if (dir != DMA_TO_DEVICE)
+		set_bit(PG_dcache_clean, &page->flags);
 }
 EXPORT_SYMBOL(___dma_page_dev_to_cpu);
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 9b906de..58846cb 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -141,7 +141,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
  * a page table, or changing an existing PTE.  Basically, there are two
  * things that we need to take care of:
  *
- *  1. If PG_dcache_dirty is set for the page, we need to ensure
+ *  1. If PG_dcache_clean is not set for the page, we need to ensure
  *     that any cache entries for the kernels virtual memory
  *     range are written back to the page.
  *  2. If we have multiple shared mappings of the same space in
@@ -169,7 +169,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 
 	mapping = page_mapping(page);
 #ifndef CONFIG_SMP
-	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
 		__flush_dcache_page(mapping, page);
 #endif
 	if (mapping) {
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index c6844cb..9f9919b 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -248,7 +248,7 @@ void flush_dcache_page(struct page *page)
 
 #ifndef CONFIG_SMP
 	if (!PageHighMem(page) && mapping && !mapping_mapped(mapping))
-		set_bit(PG_dcache_dirty, &page->flags);
+		clear_bit(PG_dcache_clean, &page->flags);
 	else
 #endif
 	{
@@ -257,6 +257,7 @@ void flush_dcache_page(struct page *page)
 			__flush_dcache_aliases(mapping, page);
 		else if (mapping)
 			__flush_icache_all();
+		set_bit(PG_dcache_clean, &page->flags);
 	}
 }
 EXPORT_SYMBOL(flush_dcache_page);



From catalin.marinas at arm.com  Mon Jun 21 10:46:38 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 15:46:38 +0100
Subject: [PATCH v4 3/4] ARM: Synchronise the I and D caches via set_pte_at()
	on SMP systems
In-Reply-To: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
References: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621144638.26309.6586.stgit@e102109-lin.cambridge.arm.com>

On SMP systems, there is a small chance of a PTE becoming visible to a
different CPU before the cache maintenance operations in
update_mmu_cache(). This patch follows the IA-64 and PowerPC approach of
synchronising the I and D caches via the set_pte_at() function. In this
case, there is no need for update_mmu_cache() to be implemented since
lazy cache flushing is already handled by the time this function is
called.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/pgtable.h  |   25 ++++++++++++++++++++++---
 arch/arm/include/asm/tlbflush.h |   10 +++++++++-
 arch/arm/mm/fault-armv.c        |    4 ++--
 arch/arm/mm/flush.c             |   15 +++++++++++++++
 4 files changed, 48 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index ab68cf1..a3752f5 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -278,9 +278,24 @@ extern struct page *empty_zero_page;
 
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
 
-#define set_pte_at(mm,addr,ptep,pteval) do { \
-	set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \
- } while (0)
+#ifndef CONFIG_SMP
+static inline void __sync_icache_dcache(pte_t pteval)
+{
+}
+#else
+extern void __sync_icache_dcache(pte_t pteval);
+#endif
+
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+			      pte_t *ptep, pte_t pteval)
+{
+	if (addr >= TASK_SIZE)
+		set_pte_ext(ptep, pteval, 0);
+	else {
+		__sync_icache_dcache(pteval);
+		set_pte_ext(ptep, pteval, PTE_EXT_NG);
+	}
+}
 
 /*
  * The following only work if pte_present() is true.
@@ -292,6 +307,10 @@ extern struct page *empty_zero_page;
 #define pte_young(pte)		(pte_val(pte) & L_PTE_YOUNG)
 #define pte_special(pte)	(0)
 
+#define pte_present_exec_user(pte) \
+	((pte_val(pte) & (L_PTE_PRESENT | L_PTE_EXEC | L_PTE_USER)) == \
+	 (L_PTE_PRESENT | L_PTE_EXEC | L_PTE_USER))
+
 #define PTE_BIT_FUNC(fn,op) \
 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
 
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 40a7092..6aabedd 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -554,10 +554,18 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 /*
  * If PG_dcache_clean is not set for the page, we need to ensure that any
  * cache entries for the kernels virtual memory range are written
- * back to the page.
+ * back to the page. On SMP systems, the cache coherency is handled in the
+ * set_pte_at() function.
  */
+#ifndef CONFIG_SMP
 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 	pte_t *ptep);
+#else
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+				    unsigned long addr, pte_t *ptep)
+{
+}
+#endif
 
 #endif
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 58846cb..030f1da 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -28,6 +28,7 @@
 
 static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
 
+#ifndef CONFIG_SMP
 /*
  * We take the easy way out of this problem - we make the
  * PTE uncacheable.  However, we leave the write buffer on.
@@ -168,10 +169,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 		return;
 
 	mapping = page_mapping(page);
-#ifndef CONFIG_SMP
 	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
 		__flush_dcache_page(mapping, page);
-#endif
 	if (mapping) {
 		if (cache_is_vivt())
 			make_coherent(mapping, vma, addr, ptep, pfn);
@@ -179,6 +178,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 			__flush_icache_all();
 	}
 }
+#endif	/* !CONFIG_SMP */
 
 /*
  * Check whether the write buffer has physical address aliasing
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 9f9919b..18a8467 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -215,6 +215,21 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p
 	flush_dcache_mmap_unlock(mapping);
 }
 
+#ifdef CONFIG_SMP
+void __sync_icache_dcache(pte_t pteval)
+{
+	unsigned long pfn = pte_pfn(pteval);
+
+	if (pfn_valid(pfn) && pte_present_exec_user(pteval)) {
+		struct page *page = pfn_to_page(pfn);
+
+		if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+			__flush_dcache_page(NULL, page);
+		__flush_icache_all();
+	}
+}
+#endif
+
 /*
  * Ensure cache coherency between kernel mapping and userspace mapping
  * of this page.



From catalin.marinas at arm.com  Mon Jun 21 10:46:43 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 21 Jun 2010 15:46:43 +0100
Subject: [PATCH v4 4/4] ARM: Use lazy cache flushing on ARMv7 SMP systems
In-Reply-To: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
References: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100621144643.26309.74292.stgit@e102109-lin.cambridge.arm.com>

ARMv7 processors like Cortex-A9 broadcast the cache maintenance
operations in hardware. This patch allows the
flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
similar to the UP case.

Note that cache flushing on SMP systems now takes place via the
set_pte_at() call (__sync_icache_dcache) and there is no race with other
CPUs executing code from the new PTE before the cache flushing took
place.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
---
 arch/arm/include/asm/smp_plat.h |    4 ++++
 arch/arm/mm/flush.c             |   13 ++++---------
 2 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e621530..963a338 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -13,9 +13,13 @@ static inline int tlb_ops_need_broadcast(void)
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
 
+#if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
+#define cache_ops_need_broadcast()	0
+#else
 static inline int cache_ops_need_broadcast(void)
 {
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
+#endif
 
 #endif
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 18a8467..2d08a5e 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -17,6 +17,7 @@
 #include <asm/smp_plat.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
+#include <asm/smp_plat.h>
 
 #include "mm.h"
 
@@ -93,12 +94,10 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
 #define flush_pfn_alias(pfn,vaddr)	do { } while (0)
 #endif
 
-#ifdef CONFIG_SMP
 static void flush_ptrace_access_other(void *args)
 {
 	__flush_icache_all();
 }
-#endif
 
 static
 void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
@@ -122,11 +121,9 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 	if (vma->vm_flags & VM_EXEC) {
 		unsigned long addr = (unsigned long)kaddr;
 		__cpuc_coherent_kern_range(addr, addr + len);
-#ifdef CONFIG_SMP
 		if (cache_ops_need_broadcast())
 			smp_call_function(flush_ptrace_access_other,
 					  NULL, 1);
-#endif
 	}
 }
 
@@ -261,12 +258,10 @@ void flush_dcache_page(struct page *page)
 
 	mapping = page_mapping(page);
 
-#ifndef CONFIG_SMP
-	if (!PageHighMem(page) && mapping && !mapping_mapped(mapping))
+	if (!cache_ops_need_broadcast() &&
+	    !PageHighMem(page) && mapping && !mapping_mapped(mapping))
 		clear_bit(PG_dcache_clean, &page->flags);
-	else
-#endif
-	{
+	else {
 		__flush_dcache_page(mapping, page);
 		if (mapping && cache_is_vivt())
 			__flush_dcache_aliases(mapping, page);



From phorton at bitbox.co.uk  Mon Jun 21 11:14:22 2010
From: phorton at bitbox.co.uk (Peter Horton)
Date: Mon, 21 Jun 2010 16:14:22 +0100
Subject: [PATCH] Fix AT91SAM9G20 reset
In-Reply-To: <loom.20100621T162410-494@post.gmane.org>
References: <20100528153725.GA5102@axolotl.localnet>
	<loom.20100621T162410-494@post.gmane.org>
Message-ID: <4C1F81CE.6000905@bitbox.co.uk>

On 21/06/2010 15:30, Lucas wrote:
> Peter Horton<phorton<at>  bitbox.co.uk>  writes:
>
>>
>> Fix AT91SAM9G20 as per the errata in the datasheet.
>>
>> If the SDRAM is not cleanly shutdown before reset it can be left driving
>> the bus, which then stops the bootloader booting from NAND.
>>
>> Signed-off-by: Peter Horton<phorton<at>  bitbox.co.uk>
>> --
>>
>
>
> Hi Peter,
>
> Any Idea how to implement this for the WDT and hardware reset(NRST)?
> A hardware reset sometimes still stops the bootloader booting from NAND.
>

Not possible to fix as far as I understand it. We've had to put down a 
small DataFlash which then boots from NAND.

Turns out we needed DataFlash anyway as the Atmel boot ROM is not 
compatible with newer NANDs (newer NANDs no longer guarantee block 0 
without ECC and the Atmel boot ROM doesn't support ECC).

P.


From eric.y.miao at gmail.com  Mon Jun 21 11:22:51 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 23:22:51 +0800
Subject: [PATCH 1/4] [ARM] Remove now unnecessary dma_needs_bounce()
In-Reply-To: <4C1EFABC.4020601@compulab.co.il>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com> 
	<1275724538-5075-2-git-send-email-eric.y.miao@gmail.com>
	<AANLkTilJ3UpyHEplDqS_nV8SVDcl_pRRn4glDn7JS1GW@mail.gmail.com> 
	<4C1EFABC.4020601@compulab.co.il>
Message-ID: <AANLkTimugHXfVUcEmq_DwaSLwelvnS9QoDJcxJaphahJ@mail.gmail.com>

2010/6/21 Mike Rapoport <mike at compulab.co.il>:
> Eric
>
> Eric Miao wrote:
>>
>> On Sat, Jun 5, 2010 at 3:55 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>>>
>>> With a correct dev->dma_mask before calling dmabounce_register_dev(),
>>> dma_needs_bounce() is not necessary.
>>>
>>> The above is true for it8152.c and ixp4xx/common-pci.c.
>>>
>>> The sa1111, though, is a bit complicated. Until it's fully understood
>>> and fixed, dma_needs_bounce() for sa1111 is kept if CONFIG_SA1111 is
>>> enabled with no side effect (with the condition of machine_is_*)
>>>
>>
>> Sorry I forgot to CC you two. Any feedback is welcome, thanks.
>
> Can I pull these changes from your git tree?

Sorry, just pushed them to the branch below:

  git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git
defconfig_cleanup


From linus.walleij at stericsson.com  Mon Jun 21 11:36:29 2010
From: linus.walleij at stericsson.com (Linus WALLEIJ)
Date: Mon, 21 Jun 2010 17:36:29 +0200
Subject: [PATCH 07/12] arm: remove duplicated #include
In-Reply-To: <1274548354-2088-1-git-send-email-weiyi.huang@gmail.com>
References: <1274548354-2088-1-git-send-email-weiyi.huang@gmail.com>
Message-ID: <CEE6BB42CAD6E947908279175AF8470A025E8B03A7@EXDCVYMBSTM006.EQ1STM.local>

[Huang]
> From: Huang Weiyi [mailto:weiyi.huang at gmail.com]
> Sent: den 22 maj 2010 19:13
> To: Linus WALLEIJ
> Cc: linux-arm-kernel at lists.infradead.org; Huang Weiyi
> Subject: [PATCH 07/12] arm: remove duplicated #include
> 
> Remove duplicated #include('s) in
>   arch/arm/plat-nomadik/include/plat/ste_dma40.h
> 
> Signed-off-by: Huang Weiyi <weiyi.huang at gmail.com>

Acked-by: Linus Walleij <linus.walleij at stericsson.com>

But you have to send the patch to the DMAengine subsystem maintainer
Dan Williams.

Linus Walleij


From nico at fluxnic.net  Mon Jun 21 11:38:27 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 21 Jun 2010 11:38:27 -0400 (EDT)
Subject: [PATCH 1/2] [ARM] Introduce 'struct machine_class' for SoC level
	abstraction
In-Reply-To: <AANLkTimHuNuaVrRqPMiLpItBNgBeW3Cdqg6hBYT1DEpl@mail.gmail.com>
References: <1277042450-30382-1-git-send-email-eric.miao@canonical.com>
	<201006211527.49786.jeremy.kerr@canonical.com>
	<AANLkTilUddhIW0C5LN4b7igh6vEDvelhnT8a3or677Zk@mail.gmail.com>
	<20100621090245.GA7702@n2100.arm.linux.org.uk>
	<AANLkTimHuNuaVrRqPMiLpItBNgBeW3Cdqg6hBYT1DEpl@mail.gmail.com>
Message-ID: <alpine.LFD.2.00.1006211131170.24097@xanadu.home>

On Mon, 21 Jun 2010, Eric Miao wrote:

> On Mon, Jun 21, 2010 at 5:02 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> > The same behaviour seems sensible to apply to the other class
> > functions as well - allow platforms to override the class
> > version, and leave the replacement platform function responsible
> > for calling the class if that's what it needs to do.
> >
> 
> Yep, that's a good idea, and actually was as my first version. Yet my
> concern is this doesn't easily fit for the class data, i.e., allow the
> machine specific data to override the class data like below:
> 
> 	if (valid_value(mdesc->phys_io))
> 		use(mdesc->phys_io);
> 	else
> 		use(mdesc->class->phys_io);
> 
> but since phys_io could be valid for value zero (as if not explicitly
> initialized), so we may end up defining like below to allow use of the
> default class values:
> 
> MACHINE_START(....)
> 	.phys_io	= INVALID_ADDRESS,
> 	.io_pg_offst	= INVALID_ADDRESS,
> 	....
> MACHINE_END

No, please don't do that.  This is horribly ugly.

And in fact I would actually be highly surprised if 0 was a sensible 
value to use for either of those fields anyway.  No SOCs I know about 
has its IO at physical address0, and we're even less likely to remap 
them at virtual address 0 either.  So having 0 meaning uninitialized 
makes perfect sense in practice.


Nicolas


From rabin at rab.in  Mon Jun 21 11:41:21 2010
From: rabin at rab.in (Rabin Vincent)
Date: Mon, 21 Jun 2010 21:11:21 +0530
Subject: [PATCH V2] GPIO PL061: Adding Clk framework support
In-Reply-To: <1277103463-7311-1-git-send-email-viresh.kumar@st.com>
References: <1277103463-7311-1-git-send-email-viresh.kumar@st.com>
Message-ID: <20100621154121.GA4290@debian>

On Mon, Jun 21, 2010 at 12:27:43PM +0530, Viresh KUMAR wrote:
> GPIO Clk is never enabled on Platforms, like: SPEAr, which are based upon clock
> framework and use PL061 driver. This patch adds support for Clk enabling and
> disabling as and when gpios are requested and freed.
[...]
> +	chip->clk = clk_get(&dev->dev, NULL);
> +	if (IS_ERR(chip->clk)) {
> +		ret = PTR_ERR(chip->clk);
> +		goto iounmap;
> +	}

Have you verified that all platforms using this driver already have
clocks with the appropriate names?   Otherwise this patch will break
those platforms.

Rabin


From eric.y.miao at gmail.com  Mon Jun 21 11:44:02 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 21 Jun 2010 23:44:02 +0800
Subject: [PATCH 1/2] [ARM] Introduce 'struct machine_class' for SoC level 
	abstraction
In-Reply-To: <alpine.LFD.2.00.1006211131170.24097@xanadu.home>
References: <1277042450-30382-1-git-send-email-eric.miao@canonical.com> 
	<201006211527.49786.jeremy.kerr@canonical.com>
	<AANLkTilUddhIW0C5LN4b7igh6vEDvelhnT8a3or677Zk@mail.gmail.com> 
	<20100621090245.GA7702@n2100.arm.linux.org.uk>
	<AANLkTimHuNuaVrRqPMiLpItBNgBeW3Cdqg6hBYT1DEpl@mail.gmail.com> 
	<alpine.LFD.2.00.1006211131170.24097@xanadu.home>
Message-ID: <AANLkTilzTEqCzI5RqE0ejyrdq5df2A5bFIZTCcEnUDk8@mail.gmail.com>

On Mon, Jun 21, 2010 at 11:38 PM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Mon, 21 Jun 2010, Eric Miao wrote:
>
>> On Mon, Jun 21, 2010 at 5:02 PM, Russell King - ARM Linux
>> <linux at arm.linux.org.uk> wrote:
>> > The same behaviour seems sensible to apply to the other class
>> > functions as well - allow platforms to override the class
>> > version, and leave the replacement platform function responsible
>> > for calling the class if that's what it needs to do.
>> >
>>
>> Yep, that's a good idea, and actually was as my first version. Yet my
>> concern is this doesn't easily fit for the class data, i.e., allow the
>> machine specific data to override the class data like below:
>>
>> ? ? ? if (valid_value(mdesc->phys_io))
>> ? ? ? ? ? ? ? use(mdesc->phys_io);
>> ? ? ? else
>> ? ? ? ? ? ? ? use(mdesc->class->phys_io);
>>
>> but since phys_io could be valid for value zero (as if not explicitly
>> initialized), so we may end up defining like below to allow use of the
>> default class values:
>>
>> MACHINE_START(....)
>> ? ? ? .phys_io ? ? ? ?= INVALID_ADDRESS,
>> ? ? ? .io_pg_offst ? ?= INVALID_ADDRESS,
>> ? ? ? ....
>> MACHINE_END
>
> No, please don't do that. ?This is horribly ugly.
>
> And in fact I would actually be highly surprised if 0 was a sensible
> value to use for either of those fields anyway. ?No SOCs I know about
> has its IO at physical address0, and we're even less likely to remap
> them at virtual address 0 either. ?So having 0 meaning uninitialized
> makes perfect sense in practice.
>

Hrm... that makes sense. I'll add some comment to the 'struct machine_class'
and get this patch updated later.


From linus.ml.walleij at gmail.com  Mon Jun 21 13:34:59 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Mon, 21 Jun 2010 19:34:59 +0200
Subject: [PATCH V2] GPIO PL061: Adding Clk framework support
In-Reply-To: <20100621154121.GA4290@debian>
References: <1277103463-7311-1-git-send-email-viresh.kumar@st.com>
	<20100621154121.GA4290@debian>
Message-ID: <AANLkTim0x5_4re3CWzWDRr1QMq46sQa1SCSyAiymmiUW@mail.gmail.com>

2010/6/21 Rabin Vincent <rabin at rab.in>:
> On Mon, Jun 21, 2010 at 12:27:43PM +0530, Viresh KUMAR wrote:
>> GPIO Clk is never enabled on Platforms, like: SPEAr, which are based upon clock
>> framework and use PL061 driver. This patch adds support for Clk enabling and
>> disabling as and when gpios are requested and freed.
> [...]
>> + ? ? chip->clk = clk_get(&dev->dev, NULL);
>> + ? ? if (IS_ERR(chip->clk)) {
>> + ? ? ? ? ? ? ret = PTR_ERR(chip->clk);
>> + ? ? ? ? ? ? goto iounmap;
>> + ? ? }
>
> Have you verified that all platforms using this driver already have
> clocks with the appropriate names? ? Otherwise this patch will break
> those platforms.

The ARM Versatiles and RealViews are always clocked I think,
so clock support should be optional.

When I added a clock lookup to the PL08x block recently I used
a construct like this for an optional clock:

chip->clk = clk_get(&dev->dev, NULL);
if (IS_ERR(chip->clk)) {
       ret = PTR_ERR(chip->clk);
       if (ret == -ENOENT)
          /* No block clock in this platform */
          chip->clk = NULL;
       else
          goto iounmap;
}

This will work whenever clkdevice is used, since that
returns -ENOENT for nonexisting entries.

Then:

if (chip->clk)
  clk_enable(chip->clk);

etc

Yours,
Linus Walleij


From baruch at tkos.co.il  Mon Jun 21 13:41:02 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Mon, 21 Jun 2010 20:41:02 +0300
Subject: [PATCH V2] GPIO PL061: Adding Clk framework support
In-Reply-To: <1277103463-7311-1-git-send-email-viresh.kumar@st.com>
References: <1277103463-7311-1-git-send-email-viresh.kumar@st.com>
Message-ID: <20100621174101.GB11851@tarshish>

Hi Viresh,

On Mon, Jun 21, 2010 at 12:27:43PM +0530, Viresh KUMAR wrote:
> From: Viresh KUMAR <viresh.kumar at st.com>
> 
> GPIO Clk is never enabled on Platforms, like: SPEAr, which are based upon clock
> framework and use PL061 driver. This patch adds support for Clk enabling and
> disabling as and when gpios are requested and freed.
> 
> Modifications since V1:
>  - Removed usage_count, as already done by clk framework.
>  - Checking error case of clk_enable.
> 
> Signed-off-by: Viresh Kumar <viresh.kumar at st.com>

Acked-by: Baruch Siach <baruch at tkos.co.il>


-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From linux at arm.linux.org.uk  Mon Jun 21 14:22:19 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 19:22:19 +0100
Subject: [PATCH 2/3] [ARM] pxa: remove useless NODE_MEM_SIZE_BITS
In-Reply-To: <1277130154-25912-2-git-send-email-eric.y.miao@gmail.com>
References: <1277130154-25912-1-git-send-email-eric.y.miao@gmail.com>
	<1277130154-25912-2-git-send-email-eric.y.miao@gmail.com>
Message-ID: <20100621182219.GB13624@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 10:22:33PM +0800, Eric Miao wrote:
> As DISCONTIGMEM is not enabled on PXA, remove this useless bit.

You need to look at my LMB or devel branch.  This is gone already there.


From fabioestevam at yahoo.com  Mon Jun 21 16:33:05 2010
From: fabioestevam at yahoo.com (Fabio Estevam)
Date: Mon, 21 Jun 2010 13:33:05 -0700 (PDT)
Subject: [PATCH] mx31_3ds: Handle USB OTG GPIO Errors
Message-ID: <261388.38765.qm@web51008.mail.re2.yahoo.com>

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-mx3/mach-mx31_3ds.c |   23 ++++++++++++++++++++---
 1 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 58e5729..974748b 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -182,8 +182,10 @@ static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
 
 #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
 
-static void mx31_3ds_usbotg_init(void)
+static int mx31_3ds_usbotg_init(void)
 {
+	int err;
+	
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
@@ -197,10 +199,25 @@ static void mx31_3ds_usbotg_init(void)
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
 	mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
 
-	gpio_request(USBOTG_RST_B, "otgusb-reset");
-	gpio_direction_output(USBOTG_RST_B, 0);
+	err = gpio_request(USBOTG_RST_B, "otgusb-reset");
+	if (err) {
+		pr_err("Failed to request the USB OTG reset gpio\n");
+		return err;
+	}
+
+	err = gpio_direction_output(USBOTG_RST_B, 0);
+	if (err) {
+		pr_err("Failed to drive the USB OTG reset gpio\n");
+		goto usbotg_free_reset;
+	}
+
 	mdelay(1);
 	gpio_set_value(USBOTG_RST_B, 1);
+	return 0;
+
+usbotg_free_reset:
+	gpio_free(USBOTG_RST_B);
+	return err;
 }
 
 static struct fsl_usb2_platform_data usbotg_pdata = {
-- 
1.6.0.4




      


From ryan at bluewatersys.com  Mon Jun 21 16:43:06 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Tue, 22 Jun 2010 08:43:06 +1200
Subject: [PATCH 2/2] clk: Generic support for fixed-rate clocks
In-Reply-To: <1277098513.947920.264679354891.2.gpush@pororo>
References: <1277098513.947920.264679354891.2.gpush@pororo>
Message-ID: <4C1FCEDA.3000303@bluewatersys.com>

On 06/21/2010 05:35 PM, Jeremy Kerr wrote:
> Since most platforms will need a fixed-rate clock, add one. This will
> also serve as a basic example of an implementation of struct clk.
> 
> Signed-off-by: Jeremy Kerr <jeremy.kerr at canonical.com>
> 
> ---
>  include/linux/clk.h |   13 +++++++++++++
>  kernel/clk.c        |   14 ++++++++++++++
>  2 files changed, 27 insertions(+)
> 
> diff --git a/include/linux/clk.h b/include/linux/clk.h
> index 5c1098b..1dce473 100644
> --- a/include/linux/clk.h
> +++ b/include/linux/clk.h
> @@ -79,6 +79,19 @@ struct clk_ops {
>   */
>  int __clk_get(struct clk *clk);
>  
> +/* Simple fixed-rate clock */
> +struct clk_fixed {
> +	struct clk	clk;
> +	unsigned long	rate;
> +};

Not sure if this has been discussed already, but shouldn't rate be const
for a fixed clock?

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From marek.vasut at gmail.com  Mon Jun 21 17:02:03 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 21 Jun 2010 23:02:03 +0200
Subject: [PATCH] pxa3xx: Fix HSIO bus x24 multiplier
Message-ID: <1277154123-31532-1-git-send-email-marek.vasut@gmail.com>

The value should be 24, not 0 in the possibilities array. It was just a silly
mistake.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/pxa3xx.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index acfa9f7..fa00148 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -52,7 +52,7 @@
 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
 
 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
-static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
+static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
 
 /*
  * Get the clock frequency as reflected by CCSR and the turbo flag.
-- 
1.7.1



From dwalker at codeaurora.org  Mon Jun 21 17:40:22 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Mon, 21 Jun 2010 14:40:22 -0700
Subject: [RFC PATCH] smp: parallel smp boot option
Message-ID: <1277156422-9130-1-git-send-email-dwalker@codeaurora.org>

From: Steve Muckle <smuckle at codeaurora.org>

Some SMP configurations start all available cores in parallel
through the kernel entrypoint, rather than secondary CPUs waiting to be
brought out of reset into machine specific startup code.

Signed-off-by: Steve Muckle <smuckle at codeaurora.org>
---
 arch/arm/Kconfig       |    9 +++++++++
 arch/arm/kernel/head.S |    3 +++
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 021b1d5..39103d2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1020,6 +1020,15 @@ config NR_CPUS
 	depends on SMP
 	default "4"
 
+config SMP_PARALLEL_START
+	bool "Parallel start of SMP cores"
+	depends on SMP
+	default n
+	help
+	  Say Y here if all CPUs boot to the kernel entrypoint in
+	  parallel, rather than non-master CPUs waiting to be brought
+	  out of reset into machine specific startup code.
+
 config HOTPLUG_CPU
 	bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
 	depends on SMP && HOTPLUG && EXPERIMENTAL
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 4946c72..9730b7a 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -78,6 +78,9 @@
 ENTRY(stext)
 	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
 						@ and irqs disabled
+#ifdef CONFIG_SMP_PARALLEL_START
+	bl	__smp_secondary_spin
+#endif
 	mrc	p15, 0, r9, c0, c0		@ get processor id
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
-- 
1.7.1

-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From linux at arm.linux.org.uk  Mon Jun 21 18:00:30 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 23:00:30 +0100
Subject: [RFC PATCH] smp: parallel smp boot option
In-Reply-To: <1277156422-9130-1-git-send-email-dwalker@codeaurora.org>
References: <1277156422-9130-1-git-send-email-dwalker@codeaurora.org>
Message-ID: <20100621220030.GC13624@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 02:40:22PM -0700, Daniel Walker wrote:
> +#ifdef CONFIG_SMP_PARALLEL_START
> +	bl	__smp_secondary_spin
> +#endif

This seems to be half a patch - this doesn't exist.


From dwalker at codeaurora.org  Mon Jun 21 18:03:13 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Mon, 21 Jun 2010 15:03:13 -0700
Subject: [RFC PATCH] msm: initial MSM8X60 early kernel boot support
In-Reply-To: <1277156422-9130-1-git-send-email-dwalker@codeaurora.org>
References: <1277156422-9130-1-git-send-email-dwalker@codeaurora.org>
Message-ID: <1277157793-9712-1-git-send-email-dwalker@codeaurora.org>

From: Steve Muckle <smuckle at codeaurora.org>

Current MSM8X60 platforms boot all available cores into the kernel
entrypoint in parallel.

Signed-off-by: Steve Muckle <smuckle at codeaurora.org>
---
Additional stuff needed to get the last smp patch working,
"smp: parallel smp boot option".

 arch/arm/mach-msm/Makefile  |    2 +
 arch/arm/mach-msm/headsmp.S |   57 ++++++++++++++++++++++
 arch/arm/mach-msm/platsmp.c |  112 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 171 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/headsmp.S
 create mode 100644 arch/arm/mach-msm/platsmp.c

diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 31719cd..df0b9ad 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -24,6 +24,8 @@ ifdef CONFIG_ARCH_QSD8X50
 	obj-$(CONFIG_MSM_SOC_REV_A) += acpuclock-8x50a.o
 endif
 
+obj-$(CONFIG_SMP) += headsmp.o platsmp.o
+
 obj-$(CONFIG_MSM_CPU_AVS) += avs.o avs_hw.o
 obj-$(CONFIG_CPU_V6) += idle-v6.o
 obj-$(CONFIG_CPU_V7) += idle-v7.o
diff --git a/arch/arm/mach-msm/headsmp.S b/arch/arm/mach-msm/headsmp.S
new file mode 100644
index 0000000..351783c
--- /dev/null
+++ b/arch/arm/mach-msm/headsmp.S
@@ -0,0 +1,57 @@
+/*
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *  Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+	__INIT
+
+/* Called very early during init. Only allowed to continue if we are the
+ * primary CPU, otherwise go to the secondary startup waiting to be brought
+ * out of reset.
+ */
+ENTRY(__smp_secondary_spin)
+	mrc	p15, 0, r0, c0, c0, 5	@ MPIDR
+	ands	r0, r0, #15		@ What CPU am I
+	moveq	pc,lr			@ if 0 (aka primary), return
+	/* Fall through  */
+
+/*
+ * MSM specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ *
+ * This is executing in physical space with cache's off.
+ */
+ENTRY(msm_secondary_startup)
+	mrc	p15, 0, r0, c0, c0, 5 	@ MPIDR
+	and	r0, r0, #15		@ What CPU am I
+	adr	r4, 1f			@ address of
+	ldmia	r4, {r5, r6}		@ load curr addr and pen_rel addr
+	sub	r4, r4, r5		@ determine virtual/phys offsets
+	add	r6, r6, r4		@ apply
+pen:
+	wfe
+	dsb				@ ensure subsequent access is
+					@ after event
+
+	ldr	r7, [r6]		@ pen_rel has cpu to remove from reset
+	cmp	r7, r0			@ are we lucky?
+	bne	pen
+
+	/*
+	 * we've been released from the holding pen: secondary_stack
+	 * should now contain the SVC stack for this core
+	 */
+	mvn	r7, #0			@ -1 to registers
+	str r7,[r6]			@ back to the pen for ack
+	b	secondary_startup
+
+1:	.long	.
+	.long	pen_release
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
new file mode 100644
index 0000000..9dfd092
--- /dev/null
+++ b/arch/arm/mach-msm/platsmp.c
@@ -0,0 +1,112 @@
+/*
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *  Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/cpumask.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+
+#include <asm/hardware/gic.h>
+#include <asm/cacheflush.h>
+
+#include <mach/smp.h>
+#include <mach/hardware.h>
+#include <mach/msm_iomap.h>
+
+#define SECONDARY_CPU_WAIT_MS 10
+
+int pen_release = -1;
+
+int get_core_count(void)
+{
+#ifdef CONFIG_NR_CPUS
+	return CONFIG_NR_CPUS;
+#else
+	return 1;
+#endif
+}
+
+/* Initialize the present map (cpu_set(i, cpu_present_map)). */
+void smp_prepare_cpus(unsigned int max_cpus)
+{
+	int i;
+
+	for (i = 0; i < max_cpus; i++)
+		cpu_set(i, cpu_present_map);
+}
+
+void smp_init_cpus(void)
+{
+	unsigned int i, ncores = get_core_count();
+
+	for (i = 0; i < ncores; i++)
+		cpu_set(i, cpu_possible_map);
+}
+
+/* Executed by primary CPU, brings other CPUs out of reset. Called at boot
+   as well as when a CPU is coming out of shutdown induced by echo 0 >
+   /sys/devices/.../cpuX.
+*/
+int boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	int cnt = 0;
+	printk(KERN_DEBUG "Starting secondary CPU %d\n", cpu);
+
+	/* Tell other CPUs to come out or reset.  Note that secondary CPUs
+	 * are probably running with caches off, so we'll need to clean to
+	 * memory. Normal cache ops will only clean to L2.
+	 */
+	pen_release = cpu;
+	dmac_clean_range((void *)&pen_release,
+			 (void *)(&pen_release + sizeof(pen_release)));
+	dmac_clean_range((void *)&secondary_data,
+			 (void *)(&secondary_data + sizeof(secondary_data)));
+	sev();
+	dsb();
+
+	/* Wait for done signal. The cpu receiving the signal does not
+	 * have the MMU or caching turned on, so all of its reads and
+	 * writes are to/from memory.  Need to ensure that when
+	 * reading the value we invalidate the cache line so we see the
+	 * fresh data from memory as the normal routines may only
+	 * invalidate to POU or L1.
+	 */
+	while (pen_release != 0xFFFFFFFF) {
+		dmac_inv_range((void *)&pen_release,
+			       (void *)(&pen_release+sizeof(pen_release)));
+		msleep_interruptible(1);
+		if (cnt++ >= SECONDARY_CPU_WAIT_MS)
+			break;
+	}
+
+	if (pen_release == 0xFFFFFFFF)
+		printk(KERN_DEBUG "Secondary CPU start acked %d\n", cpu);
+	else
+		printk(KERN_ERR "Secondary CPU failed to start..." \
+		       "continuing\n");
+
+	return 0;
+}
+
+/* Initialization routine for secondary CPUs after they are brought out of
+ * reset.
+*/
+void platform_secondary_init(unsigned int cpu)
+{
+	printk(KERN_DEBUG "%s: cpu:%d\n", __func__, cpu);
+
+	trace_hardirqs_off();
+
+	/*
+	 * setup GIC (GIC number NOT CPU number and the base address of the
+	 * GIC CPU interface
+	 */
+	gic_cpu_init(0, MSM_QGIC_CPU_BASE);
+}
-- 
1.7.1



From dwalker at codeaurora.org  Mon Jun 21 18:07:13 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Mon, 21 Jun 2010 15:07:13 -0700
Subject: [RFC PATCH] smp: parallel smp boot option
In-Reply-To: <20100621220030.GC13624@n2100.arm.linux.org.uk>
References: <1277156422-9130-1-git-send-email-dwalker@codeaurora.org>
	<20100621220030.GC13624@n2100.arm.linux.org.uk>
Message-ID: <1277158033.17092.58.camel@c-dwalke-linux.qualcomm.com>

On Mon, 2010-06-21 at 23:00 +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 21, 2010 at 02:40:22PM -0700, Daniel Walker wrote:
> > +#ifdef CONFIG_SMP_PARALLEL_START
> > +	bl	__smp_secondary_spin
> > +#endif
> 
> This seems to be half a patch - this doesn't exist.

Yeah, I missed part of it. It was spread across two commits.. Also it's
against 2.6.32 , so it may be partly out of date.

Daniel

-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From linux at arm.linux.org.uk  Mon Jun 21 18:07:17 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 23:07:17 +0100
Subject: [RFC PATCH] msm: initial MSM8X60 early kernel boot support
In-Reply-To: <1277157793-9712-1-git-send-email-dwalker@codeaurora.org>
References: <1277156422-9130-1-git-send-email-dwalker@codeaurora.org>
	<1277157793-9712-1-git-send-email-dwalker@codeaurora.org>
Message-ID: <20100621220716.GD13624@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 03:03:13PM -0700, Daniel Walker wrote:
> +int boot_secondary(unsigned int cpu, struct task_struct *idle)
> +{
> +	int cnt = 0;
> +	printk(KERN_DEBUG "Starting secondary CPU %d\n", cpu);
> +
> +	/* Tell other CPUs to come out or reset.  Note that secondary CPUs
> +	 * are probably running with caches off, so we'll need to clean to
> +	 * memory. Normal cache ops will only clean to L2.
> +	 */
> +	pen_release = cpu;
> +	dmac_clean_range((void *)&pen_release,
> +			 (void *)(&pen_release + sizeof(pen_release)));

dmac_clean_range() and dmac_inv_range() no longer exist.

> +	dmac_clean_range((void *)&secondary_data,
> +			 (void *)(&secondary_data + sizeof(secondary_data)));

We've already fixed this.


From dwalker at codeaurora.org  Mon Jun 21 18:22:29 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Mon, 21 Jun 2010 15:22:29 -0700
Subject: [RFC PATCH] smp: parallel smp boot option
In-Reply-To: <20100621220030.GC13624@n2100.arm.linux.org.uk>
References: <1277156422-9130-1-git-send-email-dwalker@codeaurora.org>
	<20100621220030.GC13624@n2100.arm.linux.org.uk>
Message-ID: <1277158949.17092.61.camel@c-dwalke-linux.qualcomm.com>

On Mon, 2010-06-21 at 23:00 +0100, Russell King - ARM Linux wrote:
> On Mon, Jun 21, 2010 at 02:40:22PM -0700, Daniel Walker wrote:
> > +#ifdef CONFIG_SMP_PARALLEL_START
> > +	bl	__smp_secondary_spin
> > +#endif
> 

Your OK with this hook? I was thinking it might be better to check if
it's the book cpu or the secondary here instead of in
arch/arm/mach-msm .

Steve, do you have any thoughts on that?

Daniel


-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From arnaud.patard at rtp-net.org  Mon Jun 21 18:26:59 2010
From: arnaud.patard at rtp-net.org (Arnaud Patard (Rtp))
Date: Tue, 22 Jun 2010 00:26:59 +0200
Subject: [PATCH] h1940: implement mmc_power function
In-Reply-To: <201006211721.48347.anarsoul@gmail.com> (Vasily Khoruzhick's
	message of "Mon\, 21 Jun 2010 17\:21\:32 +0300")
References: <1276346763-29309-1-git-send-email-anarsoul@gmail.com>
	<201006211721.48347.anarsoul@gmail.com>
Message-ID: <87iq5crpho.fsf@lechat.rtp-net.org>

Vasily Khoruzhick <anarsoul at gmail.com> writes:

> ? ????????? ?? 12 ???? 2010 15:46:03 ????? Vasily Khoruzhick ???????:
>> Signed-off-by: Vasily Khoruzhick <anarsoul at gmail.com>
>> ---
>>  arch/arm/mach-s3c2410/include/mach/h1940-latch.h |    7 +++----
>>  arch/arm/mach-s3c2410/mach-h1940.c               |   17 ++++++++++++++++-
>>  2 files changed, 19 insertions(+), 5 deletions(-)
>
> Ping :)

Fine for me.

Acked-by: Arnaud Patard <arnaud.patard at rtp-net.org>


From linux at arm.linux.org.uk  Mon Jun 21 18:31:46 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 21 Jun 2010 23:31:46 +0100
Subject: [RFC PATCH] smp: parallel smp boot option
In-Reply-To: <1277158949.17092.61.camel@c-dwalke-linux.qualcomm.com>
References: <1277156422-9130-1-git-send-email-dwalker@codeaurora.org>
	<20100621220030.GC13624@n2100.arm.linux.org.uk>
	<1277158949.17092.61.camel@c-dwalke-linux.qualcomm.com>
Message-ID: <20100621223146.GE13624@n2100.arm.linux.org.uk>

On Mon, Jun 21, 2010 at 03:22:29PM -0700, Daniel Walker wrote:
> On Mon, 2010-06-21 at 23:00 +0100, Russell King - ARM Linux wrote:
> > On Mon, Jun 21, 2010 at 02:40:22PM -0700, Daniel Walker wrote:
> > > +#ifdef CONFIG_SMP_PARALLEL_START
> > > +	bl	__smp_secondary_spin
> > > +#endif
> > 
> 
> Your OK with this hook? I was thinking it might be better to check if
> it's the book cpu or the secondary here instead of in
> arch/arm/mach-msm .

Not entirely.  It would appear that it means you can never used a
compressed kernel on MSM, since if you do, you'll have all CPUs in
the system decompressing the kernel simultaneously.

If we have to have this hook, how about making it a weak reference
rather than something dealt with by the configuration system?


From kgene.kim at samsung.com  Mon Jun 21 19:24:01 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 08:24:01 +0900
Subject: Add Samsung Keypad driver
Message-ID: <1277162642-10137-1-git-send-email-kgene.kim@samsung.com>

Following is for Samsung Keypad driver.
Tested on SMDK6410(S3C6410), SMDKC100(S5PC100), Aquila(S5PC110),
GONI(S5PC110) and SMDKV210(S5PV210) boards.

Please apply.

Thanks.

[PATCH] input: samsung-keypad - Add samsung keypad driver


From kgene.kim at samsung.com  Mon Jun 21 19:31:38 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 08:31:38 +0900
Subject: [PATCH] input: samsung-keypad - Add samsung keypad driver
Message-ID: <1277163098-10263-1-git-send-email-kgene.kim@samsung.com>

From: Joonyoung Shim <jy0922.shim at samsung.com>

This patch adds support for keypad driver running on Samsung SoCs. This
driver is tested on SMDK6410(S3C6410), SMDKC100(S5PC100), Aquila(S5PC110),
GONI(S5PC110) and SMDKV210(S5PV210) boards.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Tested-by: Naveen Krishna Ch <ch.naveen at samsung.com>
[kgene.kim at samsung.com: added comments]
Acked-by: Kukjin Kim <kgene.kim at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 drivers/input/keyboard/Kconfig          |    9 +
 drivers/input/keyboard/Makefile         |    1 +
 drivers/input/keyboard/samsung-keypad.c |  400 +++++++++++++++++++++++++++++++
 3 files changed, 410 insertions(+), 0 deletions(-)
 create mode 100644 drivers/input/keyboard/samsung-keypad.c

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index d8fa5d7..bf6a50f 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -342,6 +342,15 @@ config KEYBOARD_PXA930_ROTARY
 	  To compile this driver as a module, choose M here: the
 	  module will be called pxa930_rotary.
 
+config KEYBOARD_SAMSUNG
+	tristate "Samsung keypad support"
+	depends on SAMSUNG_DEV_KEYPAD
+	help
+	  Say Y here if you want to use the Samsung keypad.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called samsung-keypad.
+
 config KEYBOARD_STOWAWAY
 	tristate "Stowaway keyboard"
 	select SERIO
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 4596d0c..8f973ed 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_KEYBOARD_OPENCORES)	+= opencores-kbd.o
 obj-$(CONFIG_KEYBOARD_PXA27x)		+= pxa27x_keypad.o
 obj-$(CONFIG_KEYBOARD_PXA930_ROTARY)	+= pxa930_rotary.o
 obj-$(CONFIG_KEYBOARD_QT2160)		+= qt2160.o
+obj-$(CONFIG_KEYBOARD_SAMSUNG)		+= samsung-keypad.o
 obj-$(CONFIG_KEYBOARD_SH_KEYSC)		+= sh_keysc.o
 obj-$(CONFIG_KEYBOARD_STOWAWAY)		+= stowaway.o
 obj-$(CONFIG_KEYBOARD_SUNKBD)		+= sunkbd.o
diff --git a/drivers/input/keyboard/samsung-keypad.c b/drivers/input/keyboard/samsung-keypad.c
new file mode 100644
index 0000000..4b56e6f
--- /dev/null
+++ b/drivers/input/keyboard/samsung-keypad.c
@@ -0,0 +1,400 @@
+/*
+ * samsung-keypad.c  --  Samsung keypad driver
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ * Author: Donghwa Lee <dh09.lee at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <plat/keypad.h>
+#include <plat/regs-keypad.h>
+
+enum samsung_keypad_type {
+	KEYPAD_TYPE_SAMSUNG,
+	KEYPAD_TYPE_S5PV210,
+};
+
+struct samsung_keypad {
+	struct input_dev *input_dev;
+	struct clk *clk;
+	struct delayed_work work;
+	void __iomem *base;
+	unsigned short *keycodes;
+	unsigned int row_shift;
+	unsigned int rows;
+	unsigned int cols;
+	unsigned int row_state[SAMSUNG_MAX_COLS];
+	int irq;
+};
+
+static int samsung_keypad_is_s5pv210(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	enum samsung_keypad_type type;
+
+	type = platform_get_device_id(pdev)->driver_data;
+	return type == KEYPAD_TYPE_S5PV210;
+}
+
+static void samsung_keypad_scan(struct samsung_keypad *keypad,
+		unsigned int *row_state)
+{
+	struct device *dev = keypad->input_dev->dev.parent;
+	unsigned int col;
+	unsigned int val;
+
+	for (col = 0; col < keypad->cols; col++) {
+		if (samsung_keypad_is_s5pv210(dev)) {
+			val = S5PV210_KEYIFCOLEN_MASK;
+			val &= ~(1 << col) << 8;
+		} else {
+			val = SAMSUNG_KEYIFCOL_MASK;
+			val &= ~(1 << col);
+		}
+
+		writel(val, keypad->base + SAMSUNG_KEYIFCOL);
+		mdelay(1);
+
+		val = readl(keypad->base + SAMSUNG_KEYIFROW);
+		row_state[col] = ~val & ((1 << keypad->rows) - 1);
+	}
+
+	/* KEYIFCOL reg clear */
+	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+}
+
+static void samsung_keypad_worker(struct work_struct *work)
+{
+	struct samsung_keypad *keypad = container_of(work,
+			struct samsung_keypad, work.work);
+	unsigned int row_state[SAMSUNG_MAX_COLS];
+	unsigned int val;
+	unsigned int changed;
+	unsigned int pressed;
+	unsigned int key_down = 0;
+	int col, row;
+
+	clk_enable(keypad->clk);
+
+	val = readl(keypad->base + SAMSUNG_KEYIFSTSCLR);
+
+	/* interrupt clear */
+	writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR);
+
+	val = readl(keypad->base + SAMSUNG_KEYIFCON);
+	val &= ~(SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN);
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	samsung_keypad_scan(keypad, row_state);
+
+	for (col = 0; col < keypad->cols; col++) {
+		changed = row_state[col] ^ keypad->row_state[col];
+		key_down |= row_state[col];
+		if (!changed)
+			continue;
+
+		for (row = 0; row < keypad->rows; row++) {
+			if (!(changed & (1 << row)))
+				continue;
+
+			pressed = row_state[col] & (1 << row);
+
+			dev_dbg(&keypad->input_dev->dev,
+				"key %s, row: %d, col: %d\n",
+				pressed ? "pressed" : "released", row, col);
+
+			val = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
+
+			input_event(keypad->input_dev, EV_MSC, MSC_SCAN, val);
+			input_report_key(keypad->input_dev,
+					keypad->keycodes[val], pressed);
+			input_sync(keypad->input_dev);
+		}
+	}
+	memcpy(keypad->row_state, row_state, sizeof(row_state));
+
+	if (key_down)
+		schedule_delayed_work(&keypad->work, HZ / 20);
+	else {
+		/* enable interrupt bit */
+		val = readl(keypad->base + SAMSUNG_KEYIFCON);
+		val |= (SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN);
+		writel(val, keypad->base + SAMSUNG_KEYIFCON);
+		enable_irq(keypad->irq);
+	}
+	clk_disable(keypad->clk);
+}
+
+static irqreturn_t samsung_keypad_interrupt(int irq, void *dev_id)
+{
+	struct samsung_keypad *keypad = dev_id;
+
+	if (!work_pending(&keypad->work.work)) {
+		disable_irq_nosync(keypad->irq);
+		schedule_delayed_work(&keypad->work, 0);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static int __devinit samsung_keypad_probe(struct platform_device *pdev)
+{
+	const struct samsung_keypad_platdata *pdata;
+	const struct matrix_keymap_data *keymap_data;
+	struct samsung_keypad *keypad;
+	struct resource *res;
+	struct input_dev *input_dev;
+	unsigned short *keycodes;
+	unsigned int row_shift;
+	unsigned int val;
+	int ret;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "no platform data defined\n");
+		return -EINVAL;
+	}
+
+	keymap_data = pdata->keymap_data;
+	if (!keymap_data) {
+		dev_err(&pdev->dev, "no keymap data defined\n");
+		return -EINVAL;
+	}
+
+	if (!pdata->rows || (pdata->rows > SAMSUNG_MAX_ROWS))
+		return -EINVAL;
+
+	if (!pdata->cols || (pdata->cols > SAMSUNG_MAX_COLS))
+		return -EINVAL;
+
+	/* initialize the gpio */
+	if (pdata->cfg_gpio)
+		pdata->cfg_gpio(pdata->rows, pdata->cols);
+
+	row_shift = get_count_order(pdata->cols);
+	/* alloc with keycodes memory */
+	keypad = kzalloc(sizeof(*keypad) + sizeof(*keycodes) *
+			(pdata->rows << row_shift), GFP_KERNEL);
+	input_dev = input_allocate_device();
+	if (!keypad || !input_dev) {
+		ret = -ENOMEM;
+		goto err_free_mem;
+	}
+	keycodes = (unsigned short *)(keypad + 1);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		ret = -ENODEV;
+		goto err_free_mem;
+	}
+
+	keypad->base = ioremap(res->start, resource_size(res));
+	if (!keypad->base) {
+		ret = -EBUSY;
+		goto err_free_mem;
+	}
+
+	keypad->clk = clk_get(&pdev->dev, "keypad");
+	if (IS_ERR(keypad->clk)) {
+		dev_err(&pdev->dev, "failed to get keypad clk\n");
+		ret = PTR_ERR(keypad->clk);
+		goto err_unmap_base;
+	}
+	clk_enable(keypad->clk);
+
+	keypad->input_dev = input_dev;
+	keypad->keycodes = keycodes;
+	keypad->row_shift = row_shift;
+	keypad->rows = pdata->rows;
+	keypad->cols = pdata->cols;
+
+	INIT_DELAYED_WORK(&keypad->work, samsung_keypad_worker);
+
+	/* enable interrupt and wakeup bit */
+	val = SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN |
+		SAMSUNG_KEYIFCON_WAKEUPEN;
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	/* KEYIFCOL reg clear */
+	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+
+	keypad->irq = platform_get_irq(pdev, 0);
+	if (keypad->irq < 0) {
+		ret = keypad->irq;
+		goto err_disable_clk;
+	}
+
+	ret = request_irq(keypad->irq, samsung_keypad_interrupt, 0,
+			dev_name(&pdev->dev), keypad);
+
+	if (ret) {
+		dev_err(&pdev->dev, "failed to register keypad interrupt\n");
+		goto err_disable_clk;
+	}
+
+	input_dev->name = pdev->name;
+	input_dev->id.bustype = BUS_HOST;
+	input_dev->dev.parent = &pdev->dev;
+
+	input_dev->evbit[0] = BIT_MASK(EV_KEY);
+	if (!pdata->no_autorepeat)
+		input_dev->evbit[0] |= BIT_MASK(EV_REP);
+
+	input_dev->keycode = keycodes;
+	input_dev->keycodesize = sizeof(*keycodes);
+	input_dev->keycodemax = pdata->rows << row_shift;
+
+	matrix_keypad_build_keymap(keymap_data, row_shift,
+			input_dev->keycode, input_dev->keybit);
+
+	input_set_capability(input_dev, EV_MSC, MSC_SCAN);
+
+	ret = input_register_device(keypad->input_dev);
+	if (ret)
+		goto err_free_irq;
+
+	device_init_wakeup(&pdev->dev, pdata->wakeup);
+	platform_set_drvdata(pdev, keypad);
+	clk_disable(keypad->clk);
+
+	return 0;
+
+err_free_irq:
+	free_irq(keypad->irq, keypad);
+err_disable_clk:
+	clk_disable(keypad->clk);
+	clk_put(keypad->clk);
+err_unmap_base:
+	iounmap(keypad->base);
+err_free_mem:
+	input_free_device(input_dev);
+	kfree(keypad);
+
+	return ret;
+}
+
+static int __devexit samsung_keypad_remove(struct platform_device *pdev)
+{
+	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+
+	device_init_wakeup(&pdev->dev, 0);
+
+	free_irq(keypad->irq, keypad);
+	cancel_delayed_work_sync(&keypad->work);
+
+	platform_set_drvdata(pdev, NULL);
+	input_unregister_device(keypad->input_dev);
+
+	clk_disable(keypad->clk);
+	clk_put(keypad->clk);
+
+	iounmap(keypad->base);
+	kfree(keypad);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int samsung_keypad_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+
+	disable_irq(keypad->irq);
+
+	if (device_may_wakeup(&pdev->dev))
+		enable_irq_wake(keypad->irq);
+
+	return 0;
+}
+
+static int samsung_keypad_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+	unsigned int val;
+
+	if (device_may_wakeup(&pdev->dev))
+		disable_irq_wake(keypad->irq);
+
+	clk_enable(keypad->clk);
+
+	/* enable interrupt and wakeup bit */
+	val = SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN |
+		SAMSUNG_KEYIFCON_WAKEUPEN;
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	/* KEYIFCOL reg clear */
+	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+
+	clk_disable(keypad->clk);
+
+	enable_irq(keypad->irq);
+
+	return 0;
+}
+
+static const struct dev_pm_ops samsung_keypad_pm_ops = {
+	.suspend	= samsung_keypad_suspend,
+	.resume		= samsung_keypad_resume,
+};
+#endif
+
+static struct platform_device_id samsung_keypad_driver_ids[] = {
+	{
+		.name		= "samsung-keypad",
+		.driver_data	= KEYPAD_TYPE_SAMSUNG,
+	}, {
+		.name		= "s5pv210-keypad",
+		.driver_data	= KEYPAD_TYPE_S5PV210,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(platform, samsung_keypad_driver_ids);
+
+static struct platform_driver samsung_keypad_driver = {
+	.probe		= samsung_keypad_probe,
+	.remove		= __devexit_p(samsung_keypad_remove),
+	.driver		= {
+		.name	= "samsung-keypad",
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &samsung_keypad_pm_ops,
+#endif
+	},
+	.id_table	= samsung_keypad_driver_ids,
+};
+
+static int __init samsung_keypad_init(void)
+{
+	return platform_driver_register(&samsung_keypad_driver);
+}
+
+static void __exit samsung_keypad_exit(void)
+{
+	platform_driver_unregister(&samsung_keypad_driver);
+}
+
+module_init(samsung_keypad_init);
+module_exit(samsung_keypad_exit);
+
+MODULE_DESCRIPTION("Samsung keypad driver");
+MODULE_AUTHOR("Joonyoung Shim <jy0922.shim at samsung.com>");
+MODULE_AUTHOR("Donghwa Lee <dh09.lee at samsung.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:samsung-keypad");
-- 
1.6.2.5



From redhatter at gentoo.org  Mon Jun 21 19:43:14 2010
From: redhatter at gentoo.org (Stuart Longland)
Date: Tue, 22 Jun 2010 09:43:14 +1000
Subject: [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
In-Reply-To: <20100619011221.GC2463@opensource.wolfsonmicro.com>
References: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
	<1276899876-19001-1-git-send-email-redhatter@gentoo.org>
	<20100619011221.GC2463@opensource.wolfsonmicro.com>
Message-ID: <20100621234314.GZ7759@www.longlandclan.yi.org>

On Sat, Jun 19, 2010 at 02:12:21AM +0100, Mark Brown wrote:
> On Sat, Jun 19, 2010 at 08:24:36AM +1000, Stuart Longland wrote:
> > +	/* Page 1 */
> > +	if (page == 1) {
> > +		if (reg <= 4)
> > +			return 1;
> 
> I can't help but think that this'd be more legible with switch ()
> statements (GCC has an extension for ranges in switch statements which
> you could use).

I gave this some further thought... I'm not certain that a switch
statement is going to be much clearer.  There are two ways I can tackle
this.

One is to go on a page-by-page basis, which is how I do it using the if
statements.  Here; I define my ranges so that I start from the very
end... anything beyond page 70 is invalid ... voila, I eliminate those
early on.  A number of pages have a similar register pattern, and so I
make use of nested if statements to explain this.  The if block for
pages following always use the block before to define the upper,
non-inclusive bound.

The register tests start from register 0.  I could perhaps reverse the
outer ifs to start at page 0 and work forwards too... but I instead work
backwards from page 70.

I exit the function as early as possible to skip unneeded checks, as
soon as I know a range is valid or not, I return 1 or 0.  Perhaps the 1
or 0 could be made clearer (a couple of #defines maybe?) but to me, it
looks fairly clear.

I could use switch statements to replace some or all of the if
statements.  There'd be a small benefit I suppose in making the outer if
statements a switch, but little anywhere else from what I can see.

The other way is that I ignore pages completely; and use the
AIC3204_PGREG macro to define ranges of absolute register addresses.
This may have a small benefit in speed since these are compiled in... as
opposed to runtime masking/shifting, but I don't see that being much
clearer either.  I'd still come to a case statement, then return.

This is a function largely intended for debugging, in fact, I'm thinking
I should probably wrap it in #ifdef CONFIG_DEBUG_FS, since the function
isn't called unless debugfs is enabled.  So I'm not certain that
performance is worth chasing here given the intended purpose -- it's not
something that's called all the time, nor something that will be used in
a production environment.

That's my thoughts on the issue, perhaps na??ve, but I'm not sure
there's any real gain in refactoring this.
-- 
Stuart Longland (aka Redhatter, VK4MSL)      .'''.
Gentoo Linux/MIPS Cobalt and Docs Developer  '.'` :
. . . . . . . . . . . . . . . . . . . . . .   .'.'
http://dev.gentoo.org/~redhatter             :.'

I haven't lost my mind...
  ...it's backed up on a tape somewhere.


From kgene.kim at samsung.com  Mon Jun 21 19:43:51 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 08:43:51 +0900
Subject: [PATCH 0/4] Add keypad support for SMDK6410, SMDKC100 and SMDKV210
Message-ID: <1277163835-12439-1-git-send-email-kgene.kim@samsung.com>

This patches add keypad support for SMDK6410, SMDKC100 and SMDKV210.

NOTE: depends on Joonyoung Shim's 'Add samsung keypad'

[PATCH 1/4] ARM: S5PV210: Add keypad device to the SMDKV210 board
[PATCH 2/4] ARM: S3C64XX: Add keypad device to the SMDK6410 board
[PATCH 3/4] ARM: S5PC100: Rename keypad clock for S5PC100.
[PATCH 4/4] ARM: S5PC100: Add keypad device to the SMDKC100 board


From kgene.kim at samsung.com  Mon Jun 21 19:43:52 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 08:43:52 +0900
Subject: [PATCH 1/4] ARM: S5PV210: Add keypad device to the SMDKV210 board
In-Reply-To: <1277163835-12439-1-git-send-email-kgene.kim@samsung.com>
References: <1277163835-12439-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277163835-12439-2-git-send-email-kgene.kim@samsung.com>

From: Naveen Krishna Ch <ch.naveen at samsung.com>

This patch is to support keypad device to the SMDKV210 board.

Signed-off-by: Naveen Krishna Ch <ch.naveen at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pv210/Kconfig         |    2 ++
 arch/arm/mach-s5pv210/mach-smdkv210.c |   23 +++++++++++++++++++++++
 2 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 692d01c..4ae365d 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -77,8 +77,10 @@ config MACH_SMDKV210
 	select CPU_S5PV210
 	select ARCH_SPARSEMEM_ENABLE
 	select SAMSUNG_DEV_ADC
+	select SAMSUNG_DEV_KEYPAD
 	select SAMSUNG_DEV_TS
 	select S3C_DEV_WDT
+	select S5PV210_SETUP_KEYPAD
 	select HAVE_S3C2410_WATCHDOG
 	help
 	  Machine support for Samsung SMDKV210
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 0d46279..43bc10a 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -27,6 +27,7 @@
 #include <plat/cpu.h>
 #include <plat/adc.h>
 #include <plat/ts.h>
+#include <plat/keypad.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define S5PV210_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
@@ -73,10 +74,30 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
 	},
 };
 
+static uint32_t smdkv210_keymap[] __initdata = {
+	/* KEY(row, col, keycode) */
+	KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
+	KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
+	KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
+	KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
+};
+
+static struct matrix_keymap_data smdkv210_keymap_data __initdata = {
+	.keymap		= smdkv210_keymap,
+	.keymap_size	= ARRAY_SIZE(smdkv210_keymap),
+};
+
+static struct samsung_keypad_platdata smdkv210_keypad_data __initdata = {
+	.keymap_data	= &smdkv210_keymap_data,
+	.rows		= 8,
+	.cols		= 8,
+};
+
 static struct platform_device *smdkv210_devices[] __initdata = {
 	&s5pv210_device_iis0,
 	&s5pv210_device_ac97,
 	&s3c_device_adc,
+	&samsung_device_keypad,
 	&s3c_device_ts,
 	&s3c_device_wdt,
 };
@@ -96,7 +117,9 @@ static void __init smdkv210_map_io(void)
 
 static void __init smdkv210_machine_init(void)
 {
+	samsung_keypad_set_platdata(&smdkv210_keypad_data);
 	s3c24xx_ts_set_platdata(&s3c_ts_platform);
+
 	platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
 }
 
-- 
1.6.2.5



From kgene.kim at samsung.com  Mon Jun 21 19:43:54 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 08:43:54 +0900
Subject: [PATCH 3/4] ARM: S5PC100: Rename keypad clock for S5PC100.
In-Reply-To: <1277163835-12439-1-git-send-email-kgene.kim@samsung.com>
References: <1277163835-12439-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277163835-12439-4-git-send-email-kgene.kim@samsung.com>

From: Naveen Krishna Ch <ch.naveen at samsung.com>

This patch renames the keypad clock for S5PC100 from keyif to keypad.

Signed-off-by: Naveen Krishna Ch <ch.naveen at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pc100/clock.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index e3fed4c..e1136f4 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -737,7 +737,7 @@ static struct clk init_clocks_disable[] = {
 		.enable		= s5pc100_d1_5_ctrl,
 		.ctrlbit	= (1 << 7),
 	}, {
-		.name		= "keyif",
+		.name		= "keypad",
 		.id		= -1,
 		.parent		= &clk_div_d1_bus.clk,
 		.enable		= s5pc100_d1_5_ctrl,
-- 
1.6.2.5



From kgene.kim at samsung.com  Mon Jun 21 19:43:53 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 08:43:53 +0900
Subject: [PATCH 2/4] ARM: S3C64XX: Add keypad device to the SMDK6410 board
In-Reply-To: <1277163835-12439-1-git-send-email-kgene.kim@samsung.com>
References: <1277163835-12439-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277163835-12439-3-git-send-email-kgene.kim@samsung.com>

From: Naveen Krishna Ch <ch.naveen at samsung.com>

This patch is to support keypad device to the SMDK6410 board.

Signed-off-by: Naveen Krishna Ch <ch.naveen at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s3c64xx/Kconfig            |    7 ++++++
 arch/arm/mach-s3c64xx/Makefile           |    1 +
 arch/arm/mach-s3c64xx/clock.c            |    6 +++++
 arch/arm/mach-s3c64xx/include/mach/map.h |    2 +
 arch/arm/mach-s3c64xx/mach-smdk6410.c    |   24 +++++++++++++++++++++
 arch/arm/mach-s3c64xx/setup-keypad.c     |   34 ++++++++++++++++++++++++++++++
 6 files changed, 74 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s3c64xx/setup-keypad.c

diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index f5a5972..08fdb7f 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -62,6 +62,11 @@ config S3C64XX_SETUP_FB_24BPP
 	help
 	  Common setup code for S3C64XX with an 24bpp RGB display helper.
 
+config S3C64XX_SETUP_KEYPAD
+	bool
+	help
+	  Common setup code for S3C64XX KEYPAD GPIO configurations
+
 config S3C64XX_SETUP_SDHCI_GPIO
 	bool
 	help
@@ -100,10 +105,12 @@ config MACH_SMDK6410
 	select S3C_DEV_USB_HOST
 	select S3C_DEV_USB_HSOTG
 	select S3C_DEV_WDT
+	select SAMSUNG_DEV_KEYPAD
 	select HAVE_S3C2410_WATCHDOG
 	select S3C64XX_SETUP_SDHCI
 	select S3C64XX_SETUP_I2C1
 	select S3C64XX_SETUP_FB_24BPP
+	select S3C64XX_SETUP_KEYPAD
 	help
 	  Machine support for the Samsung SMDK6410
 
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 9d10069..b1b4d10 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_S3C64XX_DMA)	+= dma.o
 
 obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
 obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
+obj-$(CONFIG_S3C64XX_SETUP_KEYPAD) += setup-keypad.o
 obj-$(CONFIG_S3C64XX_SETUP_SDHCI) += setup-sdhci.o
 obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
 obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index fbd85a9..ec8f097 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -165,6 +165,12 @@ static struct clk init_clocks_disable[] = {
 		.ctrlbit	= S3C6410_CLKCON_PCLK_IIS2,
 	}, {
 #endif
+		.name		= "keypad",
+		.id		= -1,
+		.parent		= &clk_p,
+		.enable		= s3c64xx_pclk_ctrl,
+		.ctrlbit	= S3C_CLKCON_PCLK_KEYPAD,
+	}, {
 		.name		= "spi",
 		.id		= 0,
 		.parent		= &clk_p,
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index e1eab3c..f57ff08 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -67,6 +67,7 @@
 #define S3C64XX_PA_USB_HSOTG	(0x7C000000)
 #define S3C64XX_PA_WATCHDOG	(0x7E004000)
 #define S3C64XX_PA_RTC		(0x7E005000)
+#define S3C64XX_PA_KEYPAD	(0x7E00A000)
 #define S3C64XX_PA_ADC		(0x7E00B000)
 #define S3C64XX_PA_SYSCON	(0x7E00F000)
 #define S3C64XX_PA_AC97		(0x7F001000)
@@ -120,5 +121,6 @@
 #define S3C_PA_WDT		S3C64XX_PA_WATCHDOG
 
 #define SAMSUNG_PA_ADC		S3C64XX_PA_ADC
+#define SAMSUNG_PA_KEYPAD	S3C64XX_PA_KEYPAD
 
 #endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index d9a0355..52dd17e 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -17,6 +17,7 @@
 #include <linux/list.h>
 #include <linux/timer.h>
 #include <linux/init.h>
+#include <linux/input.h>
 #include <linux/serial_core.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
@@ -66,6 +67,7 @@
 #include <plat/cpu.h>
 #include <plat/adc.h>
 #include <plat/ts.h>
+#include <plat/keypad.h>
 
 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
@@ -242,6 +244,25 @@ static struct platform_device smdk6410_b_pwr_5v = {
 };
 #endif
 
+static uint32_t smdk6410_keymap[] __initdata = {
+	/* KEY(row, col, keycode) */
+	KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
+	KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
+	KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
+	KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
+};
+
+static struct matrix_keymap_data smdk6410_keymap_data __initdata = {
+	.keymap		= smdk6410_keymap,
+	.keymap_size	= ARRAY_SIZE(smdk6410_keymap),
+};
+
+static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
+	.keymap_data	= &smdk6410_keymap_data,
+	.rows		= 2,
+	.cols		= 8,
+};
+
 static struct map_desc smdk6410_iodesc[] = {};
 
 static struct platform_device *smdk6410_devices[] __initdata = {
@@ -257,6 +278,7 @@ static struct platform_device *smdk6410_devices[] __initdata = {
 	&s3c_device_ohci,
 	&s3c_device_usb_hsotg,
 	&s3c64xx_device_iisv4,
+	&samsung_device_keypad,
 
 #ifdef CONFIG_REGULATOR
 	&smdk6410_b_pwr_5v,
@@ -636,6 +658,8 @@ static void __init smdk6410_machine_init(void)
 	s3c_i2c1_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk6410_lcd_pdata);
 
+	samsung_keypad_set_platdata(&smdk6410_keypad_data);
+
 	s3c24xx_ts_set_platdata(&s3c_ts_platform);
 
 	/* configure nCS1 width to 16 bits */
diff --git a/arch/arm/mach-s3c64xx/setup-keypad.c b/arch/arm/mach-s3c64xx/setup-keypad.c
new file mode 100644
index 0000000..abc34e4
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/setup-keypad.c
@@ -0,0 +1,34 @@
+/* linux/arch/arm/mach-s3c64xx/setup-keypad.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * GPIO configuration for S3C64XX KeyPad device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+
+void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
+{
+	unsigned int gpio;
+	unsigned int end;
+
+	/* Set all the necessary GPK pins to special-function 3: KP_ROW[x] */
+	end = S3C64XX_GPK(8 + rows);
+	for (gpio = S3C64XX_GPK(8); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* Set all the necessary GPL pins to special-function 3: KP_COL[x] */
+	end = S3C64XX_GPL(0 + cols);
+	for (gpio = S3C64XX_GPL(0); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+}
-- 
1.6.2.5



From kgene.kim at samsung.com  Mon Jun 21 19:43:55 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 08:43:55 +0900
Subject: [PATCH 4/4] ARM: S5PC100: Add keypad device to the SMDKC100 board
In-Reply-To: <1277163835-12439-1-git-send-email-kgene.kim@samsung.com>
References: <1277163835-12439-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277163835-12439-5-git-send-email-kgene.kim@samsung.com>

From: Naveen Krishna Ch <ch.naveen at samsung.com>

This patch is to support keypad device to the SMDKC100 board.

Signed-off-by: Naveen Krishna Ch <ch.naveen at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pc100/Kconfig            |    7 ++++++
 arch/arm/mach-s5pc100/Makefile           |    1 +
 arch/arm/mach-s5pc100/include/mach/map.h |    3 +-
 arch/arm/mach-s5pc100/mach-smdkc100.c    |   24 +++++++++++++++++++++
 arch/arm/mach-s5pc100/setup-keypad.c     |   34 ++++++++++++++++++++++++++++++
 5 files changed, 68 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-s5pc100/setup-keypad.c

diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b2a11df..a3f5695 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -25,6 +25,11 @@ config S5PC100_SETUP_I2C1
 	help
 	  Common setup code for i2c bus 1.
 
+config S5PC100_SETUP_KEYPAD
+	bool
+	help
+	  Common setup code for KEYPAD GPIO configurations.
+
 config S5PC100_SETUP_SDHCI
 	bool
 	select S5PC100_SETUP_SDHCI_GPIO
@@ -44,8 +49,10 @@ config MACH_SMDKC100
 	select S3C_DEV_HSMMC
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_HSMMC2
+	select SAMSUNG_DEV_KEYPAD
 	select S5PC100_SETUP_FB_24BPP
 	select S5PC100_SETUP_I2C1
+	select S5PC100_SETUP_KEYPAD
 	select S5PC100_SETUP_SDHCI
 	help
 	  Machine support for the Samsung SMDKC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
index 543f3de..69cfd34 100644
--- a/arch/arm/mach-s5pc100/Makefile
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_CPU_S5PC100)	+= dma.o
 
 obj-$(CONFIG_S5PC100_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
 obj-$(CONFIG_S5PC100_SETUP_I2C1)	+= setup-i2c1.o
+obj-$(CONFIG_S5PC100_SETUP_KEYPAD)	+= setup-keypad.o
 obj-$(CONFIG_S5PC100_SETUP_SDHCI)	+= setup-sdhci.o
 obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
 
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index cadae43..eb57d7f 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -129,10 +129,11 @@
 #define S3C_PA_HSMMC0		S5PC100_PA_HSMMC(0)
 #define S3C_PA_HSMMC1		S5PC100_PA_HSMMC(1)
 #define S3C_PA_HSMMC2		S5PC100_PA_HSMMC(2)
-#define S3C_PA_KEYPAD		S5PC100_PA_KEYPAD
 #define S3C_PA_TSADC		S5PC100_PA_TSADC
 #define S3C_PA_ONENAND		S5PC100_PA_ONENAND
 #define S3C_PA_ONENAND_BUF	S5PC100_PA_ONENAND_BUF
 #define S3C_SZ_ONENAND_BUF	S5PC100_SZ_ONENAND_BUF
 
+#define SAMSUNG_PA_KEYPAD	S5PC100_PA_KEYPAD
+
 #endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index af22f82..d006873 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -22,6 +22,7 @@
 #include <linux/i2c.h>
 #include <linux/fb.h>
 #include <linux/delay.h>
+#include <linux/input.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -42,6 +43,7 @@
 #include <plat/s5pc100.h>
 #include <plat/fb.h>
 #include <plat/iic.h>
+#include <plat/keypad.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define S5PC100_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
@@ -149,6 +151,25 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
 	.setup_gpio	= s5pc100_fb_gpio_setup_24bpp,
 };
 
+static uint32_t smdkc100_keymap[] __initdata = {
+	/* KEY(row, col, keycode) */
+	KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
+	KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
+	KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
+	KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
+};
+
+static struct matrix_keymap_data smdkc100_keymap_data __initdata = {
+	.keymap		= smdkc100_keymap,
+	.keymap_size	= ARRAY_SIZE(smdkc100_keymap),
+};
+
+static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = {
+	.keymap_data	= &smdkc100_keymap_data,
+	.rows		= 2,
+	.cols		= 8,
+};
+
 static struct platform_device *smdkc100_devices[] __initdata = {
 	&s3c_device_i2c0,
 	&s3c_device_i2c1,
@@ -158,6 +179,7 @@ static struct platform_device *smdkc100_devices[] __initdata = {
 	&s3c_device_hsmmc2,
 	&smdkc100_lcd_powerdev,
 	&s5pc100_device_iis0,
+	&samsung_device_keypad,
 	&s5pc100_device_ac97,
 };
 
@@ -178,6 +200,8 @@ static void __init smdkc100_machine_init(void)
 
 	s3c_fb_set_platdata(&smdkc100_lcd_pdata);
 
+	samsung_keypad_set_platdata(&smdkc100_keypad_data);
+
 	/* LCD init */
 	gpio_request(S5PC100_GPD(0), "GPD");
 	gpio_request(S5PC100_GPH0(6), "GPH0");
diff --git a/arch/arm/mach-s5pc100/setup-keypad.c b/arch/arm/mach-s5pc100/setup-keypad.c
new file mode 100644
index 0000000..d0837a7
--- /dev/null
+++ b/arch/arm/mach-s5pc100/setup-keypad.c
@@ -0,0 +1,34 @@
+/* linux/arch/arm/mach-s5pc100/setup-keypad.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * GPIO configuration for S5PC100 KeyPad device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+
+void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
+{
+	unsigned int gpio;
+	unsigned int end;
+
+	/* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
+	end = S5PC100_GPH3(rows);
+	for (gpio = S5PC100_GPH3(0); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
+	end = S5PC100_GPH2(cols);
+	for (gpio = S5PC100_GPH2(0); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+}
-- 
1.6.2.5



From kgene.kim at samsung.com  Mon Jun 21 20:18:35 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 09:18:35 +0900
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <AANLkTimhik3BOQNzybs1tUuHUXri-yxm5v7wH1JjQ5B1@mail.gmail.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>
	<4C1F4B30.3020006@samsung.com>
	<AANLkTimhik3BOQNzybs1tUuHUXri-yxm5v7wH1JjQ5B1@mail.gmail.com>
Message-ID: <00fb01cb11a0$76cfa3b0$646eeb10$%kim@samsung.com>

Eric Miao wrote:
> 
> >> and now in s5pc200 code, you can also register/re-use the s5pc100_keypad
> >> device/driver, and everyone knows - OK, the IP on S5PC100 is now re-used
> >> here.
> >>
> >
> > This is naming issue and i know it was not desided yet.
> > This keypad driver can support s3c64xx, s5pc100, s5pc110, s5pv210.
> >
> 
> I bet the first silicon this IP is deployed is s3c64xx, so my understanding
> 's3c64xx-keypad.c' should be an acceptable name.  And it's also reasonable,
> a s3c64xx-keypad driver, and is later expanded to support subsequent silicons
> without the file name being changed.

Hi,

Seems to be more suitable 'samsung-keypad', because can support S5PC100, S5PC110, and S5PV210 as well as S3C64XX.
Already tested on SMDK6410(S3C6410), SMDKC100(S5PC100), Aquila(S5PC110), GONI(S5PC110) and SMDKV210(S5PV210) boards.


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From smuckle at codeaurora.org  Mon Jun 21 20:23:38 2010
From: smuckle at codeaurora.org (smuckle at codeaurora.org)
Date: Mon, 21 Jun 2010 17:23:38 -0700 (PDT)
Subject: [RFC PATCH] smp: parallel smp boot option
In-Reply-To: <1277158949.17092.61.camel@c-dwalke-linux.qualcomm.com>
References: <1277156422-9130-1-git-send-email-dwalker@codeaurora.org>
	<20100621220030.GC13624@n2100.arm.linux.org.uk>
	<1277158949.17092.61.camel@c-dwalke-linux.qualcomm.com>
Message-ID: <1267e9ffe4a72e14bb7ede32a2d893f3.squirrel@www.codeaurora.org>

> On Mon, 2010-06-21 at 23:00 +0100, Russell King - ARM Linux wrote:
>> On Mon, Jun 21, 2010 at 02:40:22PM -0700, Daniel Walker wrote:
>> > +#ifdef CONFIG_SMP_PARALLEL_START
>> > +	bl	__smp_secondary_spin
>> > +#endif
>>
>
> Your OK with this hook? I was thinking it might be better to check if
> it's the book cpu or the secondary here instead of in
> arch/arm/mach-msm .
>
> Steve, do you have any thoughts on that?

If we do keep the hook, I think it'd be better to leave it up to the
platform specific code to do the test, in case for some reason it's not as
simple as reading the MPIDR register. It also keeps the impact to head.S
minimal.

thanks,
Steve

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From smuckle at codeaurora.org  Mon Jun 21 20:47:17 2010
From: smuckle at codeaurora.org (smuckle at codeaurora.org)
Date: Mon, 21 Jun 2010 17:47:17 -0700 (PDT)
Subject: [RFC PATCH] smp: parallel smp boot option
In-Reply-To: <20100621223146.GE13624@n2100.arm.linux.org.uk>
References: <1277156422-9130-1-git-send-email-dwalker@codeaurora.org>
	<20100621220030.GC13624@n2100.arm.linux.org.uk>
	<1277158949.17092.61.camel@c-dwalke-linux.qualcomm.com>
	<20100621223146.GE13624@n2100.arm.linux.org.uk>
Message-ID: <ec4622af344be763d55b91bc867f3330.squirrel@www.codeaurora.org>

>> Your OK with this hook? I was thinking it might be better to check if
>> it's the book cpu or the secondary here instead of in
>> arch/arm/mach-msm .
>
> Not entirely.  It would appear that it means you can never used a
> compressed kernel on MSM, since if you do, you'll have all CPUs in
> the system decompressing the kernel simultaneously.
>
> If we have to have this hook, how about making it a weak reference
> rather than something dealt with by the configuration system?

This is something we're using until we get a more complex/featureful
bootchain in place. It probably only has value in development
platforms/early enablement. A weak reference seems fine or we could drop
it alltogether.

thanks,
Steve

--
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From jy0922.shim at samsung.com  Mon Jun 21 20:48:07 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Tue, 22 Jun 2010 09:48:07 +0900
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <20100621111612.GJ7702@n2100.arm.linux.org.uk>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>
	<20100621091952.GB7702@n2100.arm.linux.org.uk>
	<AANLkTilU1X1LR33Eed9BVGE2n-dqRuIuUFfbDd3gzEVc@mail.gmail.com>
	<20100621111612.GJ7702@n2100.arm.linux.org.uk>
Message-ID: <4C200847.9010200@samsung.com>

On 6/21/2010 8:16 PM, Russell King - ARM Linux wrote:
> On Mon, Jun 21, 2010 at 06:39:10PM +0800, Eric Miao wrote:
>> On Mon, Jun 21, 2010 at 5:19 PM, Russell King - ARM Linux
>> <linux at arm.linux.org.uk> wrote:
>>> On Mon, Jun 21, 2010 at 05:05:34PM +0800, Eric Miao wrote:
>>>> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>>>>> +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
>>>>> +{
>>>>> + ? ? ? struct samsung_keypad_platdata *npd;
>>>>> +
>>>>> + ? ? ? if (!pd) {
>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no platform data\n", __func__);
>>>>> + ? ? ? ? ? ? ? return;
>>>>> + ? ? ? }
>>>>> +
>>>>> + ? ? ? npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
>>>>> + ? ? ? if (!npd)
>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no memory for platform data\n", __func__);
>>>> This part of the code is actually duplicated again and again and again
>>>> for each device, PXA and other legacy platforms are bad references for
>>>> this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
>>>> major points:
>>>>
>>>> ?1. A minimum 'struct pxa_device_desc' for a simple description of a
>>>> ? ? device (more than 90% of the devices can be described that way),
>>>> ? ? and avoid using a comparatively heavier weight platform_device,
>>>> ? ? which can be generated at run-time
>>>>
>>>> ?2. pxa_register_device() to allocate and register the platform_device
>>>> ? ? at run-time, along with the platform data
>>> It's a bad idea to make platform data be run-time discardable like this:
>>>
>>>>> +struct samsung_keypad_platdata {
>>>>> + ? ? ? const struct matrix_keymap_data *keymap_data;
>>> What you end up with is some platform data structures which must be kept
>>> (those which have pointers to them from the platform data), and others
>>> (the platform data itself) which can be discarded at runtime.
>>>
>>> We know that the __initdata attributations cause lots of problems -
>>> they're frequently wrong. ?Just see the constant hastle with __devinit
>>> et.al. ?The same issue happens with __initdata as well.
>>>
>>> So why make things more complicated by allowing some platform data
>>> structures to be discardable and others not to be? ?Is their small
>>> size (maybe 6 words for this one) really worth the hastle of getting
>>> __initdata attributations wrong (eg, on the keymap data?)
>>>
>> Russell,
>>
>> The benefit I see is when multiple boards are compiled in, those
>> data not used can be automatically discarded.
> 
> Yes, but only some of the data can be discarded.  Continuing with the
> example in hand, while you can discard the six words which represent
> samsung_keypad_platdata, but the keymap_data can't be because that won't
> be re-allocated, which is probably a much larger data structure.
> 

No. the keymap_data is possible too. The keypad driver allocates other
keymap area of input device and it is assigned from datas based on this
keymap_data.


From jeremy.kerr at canonical.com  Mon Jun 21 21:05:56 2010
From: jeremy.kerr at canonical.com (Jeremy Kerr)
Date: Tue, 22 Jun 2010 09:05:56 +0800
Subject: [PATCH 2/2] clk: Generic support for fixed-rate clocks
In-Reply-To: <4C1FCEDA.3000303@bluewatersys.com>
References: <1277098513.947920.264679354891.2.gpush@pororo>
	<4C1FCEDA.3000303@bluewatersys.com>
Message-ID: <201006220905.57533.jeremy.kerr@canonical.com>

Hi Ryan,

> Not sure if this has been discussed already, but shouldn't rate be const
> for a fixed clock?

No, we may need to set the rate at some point - eg, when setting up the 
clocks, or parsing from the device tree.

Cheers,


Jeremy


From kgene.kim at samsung.com  Mon Jun 21 21:05:59 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 10:05:59 +0900
Subject: [PATCH] ARM: S5P6442: Fix PLL setting announce message.
Message-ID: <1277168759-4599-1-git-send-email-kgene.kim@samsung.com>

From: Thomas Abraham <thomas at localhost.localdomain>

The S5P6442 PLL setting announce message incorrectly displays S5P6440
as the SoC. Change it to S5P6442.

Signed-off-by: Thomas Abraham <thomas.ab at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5p6442/clock.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-s5p6442/clock.c b/arch/arm/mach-s5p6442/clock.c
index 3aadbf4..087e57f 100644
--- a/arch/arm/mach-s5p6442/clock.c
+++ b/arch/arm/mach-s5p6442/clock.c
@@ -294,7 +294,7 @@ void __init_or_cpufreq s5p6442_setup_clocks(void)
 	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502);
 	epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500);
 
-	printk(KERN_INFO "S5P6440: PLL settings, A=%ld, M=%ld, E=%ld",
+	printk(KERN_INFO "S5P6442: PLL settings, A=%ld, M=%ld, E=%ld",
 			apll, mpll, epll);
 
 	clk_fout_apll.rate = apll;
-- 
1.6.6.rc2



From skannan at codeaurora.org  Mon Jun 21 21:14:10 2010
From: skannan at codeaurora.org (Saravana Kannan)
Date: Mon, 21 Jun 2010 18:14:10 -0700
Subject: [PATCH V2] [ARM] Add ARCH_PROVIDES_UDELAY config option
In-Reply-To: <4BFF112A.2060700@codeaurora.org>
References: <1272654736-28837-1-git-send-email-ccross@android.com>
	<u2pd73d4eaf1004301237k3ceb859dobe74fe53abec774d@mail.gmail.com>
	<87d3xgd20n.fsf@deeprootsystems.com>
	<20100501100148.GE12172@n2100.arm.linux.org.uk>
	<4BF702CC.5000401@codeaurora.org>
	<20100521220653.GL11042@n2100.arm.linux.org.uk>
	<4BFF112A.2060700@codeaurora.org>
Message-ID: <4C200E62.4090604@codeaurora.org>

Russel,

Would appreciate your thoughts on this.

Colin,

Are you continuing to use the approach used in your patch in your 
development tree? I just want to make sure we have a solution that 
everyone can agree to.

Thanks,
Saravana

Saravana Kannan wrote:
> Russell King - ARM Linux wrote:
>> My point is not specific to sched_clock, but to counters which on ARM
>> are 99.9% always memory mapped, and therefore inaccessible during the
>> very early kernel boot.  sched_clock was merely an illustration of the
>> problem.
> 
> Do you know any code which uses udelay that early? I can't imagine any 
> non-driver code using udelay. If it's just drivers using udelay, then 
> they need IO mapping to have been completed for the device register 
> access to work and hence udelay won't have any problems.
> 
> -Saravana
> 



From kgene.kim at samsung.com  Mon Jun 21 21:45:23 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 10:45:23 +0900
Subject: [PATCH v4] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
References: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <010c01cb11ac$9844e490$c8ceadb0$%kim@samsung.com>

Kukjin Kim wrote:
> 
> From: Abhilash Kesavan <a.kesavan at samsung.com>
> 
> Adds support for the Samsung PATA controller. This driver is based on the
> Libata subsystem and references the earlier patches sent for IDE
subsystem.
> 
> Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---

Hi,

Maybe missed? :-(

If no problems, please apply or kindly let me know how this should be
handled.

> 
> Changes since v3:
> 
> Addressed comments from
> 
> Sergei Shtylyov:
> 	- Removed filename in header
> 	- Used ata_timing_compute for obtaining timing parameters
> 	- Removed valid PIO mode check
> 	- Added softreset method and associated functions
> 	- Used devm_request_mem_region function as had used devm_ioremap
> 	  earlier
> 	- Removed kree and release_mem_region calls because of managed
> 	  kzalloc and request_mem_region fns being used
> 	- Added return in clk_get function
> 	- Added missing clk_put
> 	- Corrected indentation issue
> 
> Ben Dooks:
> 	- Added missing 'void __iomem' parameters
> 	- Added check for trailing bytes in data_xfer function
> 	- Removed assignment in data_xfer function
> 	- Coding changes - e.g. in pata_s3c_enable, pata_s3c_dev_select,
> 	  wait_for_host_ready
> 	- Removed host checks in suspend/resume functions
> 
>  drivers/ata/Kconfig           |    9 +
>  drivers/ata/Makefile          |    1 +
>  drivers/ata/pata_samsung_cf.c |  735
> +++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 745 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/ata/pata_samsung_cf.c
> 
(snip)


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From jy0922.shim at samsung.com  Mon Jun 21 22:03:00 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Tue, 22 Jun 2010 11:03:00 +0900
Subject: [PATCH] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <1277163098-10263-1-git-send-email-kgene.kim@samsung.com>
References: <1277163098-10263-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <4C2019D4.1040105@samsung.com>

On 6/22/2010 8:31 AM, Kukjin Kim wrote:
> From: Joonyoung Shim <jy0922.shim at samsung.com>
> 
> This patch adds support for keypad driver running on Samsung SoCs. This
> driver is tested on SMDK6410(S3C6410), SMDKC100(S5PC100), Aquila(S5PC110),
> GONI(S5PC110) and SMDKV210(S5PV210) boards.
> 
> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> Tested-by: Naveen Krishna Ch <ch.naveen at samsung.com>
> [kgene.kim at samsung.com: added comments]
> Acked-by: Kukjin Kim <kgene.kim at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>

I think this is duplicated posting. Why don't you just reply the
tested-by or acked-by at previous my mail?


From eric.y.miao at gmail.com  Mon Jun 21 23:02:15 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 22 Jun 2010 11:02:15 +0800
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <4C200847.9010200@samsung.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com> 
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com> 
	<20100621091952.GB7702@n2100.arm.linux.org.uk>
	<AANLkTilU1X1LR33Eed9BVGE2n-dqRuIuUFfbDd3gzEVc@mail.gmail.com> 
	<20100621111612.GJ7702@n2100.arm.linux.org.uk>
	<4C200847.9010200@samsung.com>
Message-ID: <AANLkTikbBkDOVF6ti_bTultATuW1KhciAmKc1Geg1OSH@mail.gmail.com>

On Tue, Jun 22, 2010 at 8:48 AM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
> On 6/21/2010 8:16 PM, Russell King - ARM Linux wrote:
>> On Mon, Jun 21, 2010 at 06:39:10PM +0800, Eric Miao wrote:
>>> On Mon, Jun 21, 2010 at 5:19 PM, Russell King - ARM Linux
>>> <linux at arm.linux.org.uk> wrote:
>>>> On Mon, Jun 21, 2010 at 05:05:34PM +0800, Eric Miao wrote:
>>>>> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>>>>>> +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
>>>>>> +{
>>>>>> + ? ? ? struct samsung_keypad_platdata *npd;
>>>>>> +
>>>>>> + ? ? ? if (!pd) {
>>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no platform data\n", __func__);
>>>>>> + ? ? ? ? ? ? ? return;
>>>>>> + ? ? ? }
>>>>>> +
>>>>>> + ? ? ? npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
>>>>>> + ? ? ? if (!npd)
>>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no memory for platform data\n", __func__);
>>>>> This part of the code is actually duplicated again and again and again
>>>>> for each device, PXA and other legacy platforms are bad references for
>>>>> this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
>>>>> major points:
>>>>>
>>>>> ?1. A minimum 'struct pxa_device_desc' for a simple description of a
>>>>> ? ? device (more than 90% of the devices can be described that way),
>>>>> ? ? and avoid using a comparatively heavier weight platform_device,
>>>>> ? ? which can be generated at run-time
>>>>>
>>>>> ?2. pxa_register_device() to allocate and register the platform_device
>>>>> ? ? at run-time, along with the platform data
>>>> It's a bad idea to make platform data be run-time discardable like this:
>>>>
>>>>>> +struct samsung_keypad_platdata {
>>>>>> + ? ? ? const struct matrix_keymap_data *keymap_data;
>>>> What you end up with is some platform data structures which must be kept
>>>> (those which have pointers to them from the platform data), and others
>>>> (the platform data itself) which can be discarded at runtime.
>>>>
>>>> We know that the __initdata attributations cause lots of problems -
>>>> they're frequently wrong. ?Just see the constant hastle with __devinit
>>>> et.al. ?The same issue happens with __initdata as well.
>>>>
>>>> So why make things more complicated by allowing some platform data
>>>> structures to be discardable and others not to be? ?Is their small
>>>> size (maybe 6 words for this one) really worth the hastle of getting
>>>> __initdata attributations wrong (eg, on the keymap data?)
>>>>
>>> Russell,
>>>
>>> The benefit I see is when multiple boards are compiled in, those
>>> data not used can be automatically discarded.
>>
>> Yes, but only some of the data can be discarded. ?Continuing with the
>> example in hand, while you can discard the six words which represent
>> samsung_keypad_platdata, but the keymap_data can't be because that won't
>> be re-allocated, which is probably a much larger data structure.
>>
>
> No. the keymap_data is possible too. The keypad driver allocates other
> keymap area of input device and it is assigned from datas based on this
> keymap_data.
>

This is a generic issue. Even if in your example, you can avoid this by
re-allocation and re-assignment (ignore the performance issue for such
behavior), the real question is the difficult to track all these down. Since
matrix_keypad_data is something out of your control (it was actually
drafted by me and Dmitry if you are interested), and think about one day
I changed it's definition, now you have to sync your driver and code every
time to make sure the discarded data is not referenced.


From eric.y.miao at gmail.com  Mon Jun 21 23:05:07 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 22 Jun 2010 11:05:07 +0800
Subject: [PATCH 2/3] [ARM] pxa: remove useless NODE_MEM_SIZE_BITS
In-Reply-To: <20100621182219.GB13624@n2100.arm.linux.org.uk>
References: <1277130154-25912-1-git-send-email-eric.y.miao@gmail.com> 
	<1277130154-25912-2-git-send-email-eric.y.miao@gmail.com> 
	<20100621182219.GB13624@n2100.arm.linux.org.uk>
Message-ID: <AANLkTikx9dbpPKk1D7yTH0ypVsrY5fRZPekPQoOOSnsm@mail.gmail.com>

On Tue, Jun 22, 2010 at 2:22 AM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Mon, Jun 21, 2010 at 10:22:33PM +0800, Eric Miao wrote:
>> As DISCONTIGMEM is not enabled on PXA, remove this useless bit.
>
> You need to look at my LMB or devel branch. ?This is gone already there.
>

Excellent, wanting this removed for a long time. I'll keep eyes more on
those bits now.


From jy0922.shim at samsung.com  Mon Jun 21 23:27:11 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Tue, 22 Jun 2010 12:27:11 +0900
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <AANLkTikbBkDOVF6ti_bTultATuW1KhciAmKc1Geg1OSH@mail.gmail.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>
	<20100621091952.GB7702@n2100.arm.linux.org.uk>
	<AANLkTilU1X1LR33Eed9BVGE2n-dqRuIuUFfbDd3gzEVc@mail.gmail.com>
	<20100621111612.GJ7702@n2100.arm.linux.org.uk>
	<4C200847.9010200@samsung.com>
	<AANLkTikbBkDOVF6ti_bTultATuW1KhciAmKc1Geg1OSH@mail.gmail.com>
Message-ID: <4C202D8F.7030005@samsung.com>

On 6/22/2010 12:02 PM, Eric Miao wrote:
> On Tue, Jun 22, 2010 at 8:48 AM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>> On 6/21/2010 8:16 PM, Russell King - ARM Linux wrote:
>>> On Mon, Jun 21, 2010 at 06:39:10PM +0800, Eric Miao wrote:
>>>> On Mon, Jun 21, 2010 at 5:19 PM, Russell King - ARM Linux
>>>> <linux at arm.linux.org.uk> wrote:
>>>>> On Mon, Jun 21, 2010 at 05:05:34PM +0800, Eric Miao wrote:
>>>>>> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>>>>>>> +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
>>>>>>> +{
>>>>>>> + ? ? ? struct samsung_keypad_platdata *npd;
>>>>>>> +
>>>>>>> + ? ? ? if (!pd) {
>>>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no platform data\n", __func__);
>>>>>>> + ? ? ? ? ? ? ? return;
>>>>>>> + ? ? ? }
>>>>>>> +
>>>>>>> + ? ? ? npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
>>>>>>> + ? ? ? if (!npd)
>>>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no memory for platform data\n", __func__);
>>>>>> This part of the code is actually duplicated again and again and again
>>>>>> for each device, PXA and other legacy platforms are bad references for
>>>>>> this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
>>>>>> major points:
>>>>>>
>>>>>> ?1. A minimum 'struct pxa_device_desc' for a simple description of a
>>>>>> ? ? device (more than 90% of the devices can be described that way),
>>>>>> ? ? and avoid using a comparatively heavier weight platform_device,
>>>>>> ? ? which can be generated at run-time
>>>>>>
>>>>>> ?2. pxa_register_device() to allocate and register the platform_device
>>>>>> ? ? at run-time, along with the platform data
>>>>> It's a bad idea to make platform data be run-time discardable like this:
>>>>>
>>>>>>> +struct samsung_keypad_platdata {
>>>>>>> + ? ? ? const struct matrix_keymap_data *keymap_data;
>>>>> What you end up with is some platform data structures which must be kept
>>>>> (those which have pointers to them from the platform data), and others
>>>>> (the platform data itself) which can be discarded at runtime.
>>>>>
>>>>> We know that the __initdata attributations cause lots of problems -
>>>>> they're frequently wrong. ?Just see the constant hastle with __devinit
>>>>> et.al. ?The same issue happens with __initdata as well.
>>>>>
>>>>> So why make things more complicated by allowing some platform data
>>>>> structures to be discardable and others not to be? ?Is their small
>>>>> size (maybe 6 words for this one) really worth the hastle of getting
>>>>> __initdata attributations wrong (eg, on the keymap data?)
>>>>>
>>>> Russell,
>>>>
>>>> The benefit I see is when multiple boards are compiled in, those
>>>> data not used can be automatically discarded.
>>> Yes, but only some of the data can be discarded.  Continuing with the
>>> example in hand, while you can discard the six words which represent
>>> samsung_keypad_platdata, but the keymap_data can't be because that won't
>>> be re-allocated, which is probably a much larger data structure.
>>>
>> No. the keymap_data is possible too. The keypad driver allocates other
>> keymap area of input device and it is assigned from datas based on this
>> keymap_data.
>>
> 
> This is a generic issue. Even if in your example, you can avoid this by
> re-allocation and re-assignment (ignore the performance issue for such
> behavior), the real question is the difficult to track all these down. Since

Right, it can occur difficulty of maintain. I wanted just to inform the
current fact.

> matrix_keypad_data is something out of your control (it was actually
> drafted by me and Dmitry if you are interested), and think about one day
> I changed it's definition, now you have to sync your driver and code every
> time to make sure the discarded data is not referenced.
> 

if matrix_keypad_data is changed, i think the patchset should included
change of related other parts using it.


From eric.y.miao at gmail.com  Mon Jun 21 23:38:47 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 22 Jun 2010 11:38:47 +0800
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <4C202D8F.7030005@samsung.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com> 
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com> 
	<20100621091952.GB7702@n2100.arm.linux.org.uk>
	<AANLkTilU1X1LR33Eed9BVGE2n-dqRuIuUFfbDd3gzEVc@mail.gmail.com> 
	<20100621111612.GJ7702@n2100.arm.linux.org.uk>
	<4C200847.9010200@samsung.com> 
	<AANLkTikbBkDOVF6ti_bTultATuW1KhciAmKc1Geg1OSH@mail.gmail.com> 
	<4C202D8F.7030005@samsung.com>
Message-ID: <AANLkTik5ScLMuo5OTSFl_k7qfrBR8xAicVrt98CXqqBa@mail.gmail.com>

On Tue, Jun 22, 2010 at 11:27 AM, Joonyoung Shim
<jy0922.shim at samsung.com> wrote:
> On 6/22/2010 12:02 PM, Eric Miao wrote:
>> On Tue, Jun 22, 2010 at 8:48 AM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>>> On 6/21/2010 8:16 PM, Russell King - ARM Linux wrote:
>>>> On Mon, Jun 21, 2010 at 06:39:10PM +0800, Eric Miao wrote:
>>>>> On Mon, Jun 21, 2010 at 5:19 PM, Russell King - ARM Linux
>>>>> <linux at arm.linux.org.uk> wrote:
>>>>>> On Mon, Jun 21, 2010 at 05:05:34PM +0800, Eric Miao wrote:
>>>>>>> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>>>>>>>> +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
>>>>>>>> +{
>>>>>>>> + ? ? ? struct samsung_keypad_platdata *npd;
>>>>>>>> +
>>>>>>>> + ? ? ? if (!pd) {
>>>>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no platform data\n", __func__);
>>>>>>>> + ? ? ? ? ? ? ? return;
>>>>>>>> + ? ? ? }
>>>>>>>> +
>>>>>>>> + ? ? ? npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
>>>>>>>> + ? ? ? if (!npd)
>>>>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no memory for platform data\n", __func__);
>>>>>>> This part of the code is actually duplicated again and again and again
>>>>>>> for each device, PXA and other legacy platforms are bad references for
>>>>>>> this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
>>>>>>> major points:
>>>>>>>
>>>>>>> ?1. A minimum 'struct pxa_device_desc' for a simple description of a
>>>>>>> ? ? device (more than 90% of the devices can be described that way),
>>>>>>> ? ? and avoid using a comparatively heavier weight platform_device,
>>>>>>> ? ? which can be generated at run-time
>>>>>>>
>>>>>>> ?2. pxa_register_device() to allocate and register the platform_device
>>>>>>> ? ? at run-time, along with the platform data
>>>>>> It's a bad idea to make platform data be run-time discardable like this:
>>>>>>
>>>>>>>> +struct samsung_keypad_platdata {
>>>>>>>> + ? ? ? const struct matrix_keymap_data *keymap_data;
>>>>>> What you end up with is some platform data structures which must be kept
>>>>>> (those which have pointers to them from the platform data), and others
>>>>>> (the platform data itself) which can be discarded at runtime.
>>>>>>
>>>>>> We know that the __initdata attributations cause lots of problems -
>>>>>> they're frequently wrong. ?Just see the constant hastle with __devinit
>>>>>> et.al. ?The same issue happens with __initdata as well.
>>>>>>
>>>>>> So why make things more complicated by allowing some platform data
>>>>>> structures to be discardable and others not to be? ?Is their small
>>>>>> size (maybe 6 words for this one) really worth the hastle of getting
>>>>>> __initdata attributations wrong (eg, on the keymap data?)
>>>>>>
>>>>> Russell,
>>>>>
>>>>> The benefit I see is when multiple boards are compiled in, those
>>>>> data not used can be automatically discarded.
>>>> Yes, but only some of the data can be discarded. ?Continuing with the
>>>> example in hand, while you can discard the six words which represent
>>>> samsung_keypad_platdata, but the keymap_data can't be because that won't
>>>> be re-allocated, which is probably a much larger data structure.
>>>>
>>> No. the keymap_data is possible too. The keypad driver allocates other
>>> keymap area of input device and it is assigned from datas based on this
>>> keymap_data.
>>>
>>
>> This is a generic issue. Even if in your example, you can avoid this by
>> re-allocation and re-assignment (ignore the performance issue for such
>> behavior), the real question is the difficult to track all these down. Since
>
> Right, it can occur difficulty of maintain. I wanted just to inform the
> current fact.
>
>> matrix_keypad_data is something out of your control (it was actually
>> drafted by me and Dmitry if you are interested), and think about one day
>> I changed it's definition, now you have to sync your driver and code every
>> time to make sure the discarded data is not referenced.
>>
>
> if matrix_keypad_data is changed, i think the patchset should included
> change of related other parts using it.
>

That's reasonable but difficult in practice, every keypad driver using
matrix_keypad_data could be doing things differently. That's what I'm
concerned about. Things will be much easier for driver writers if he
knows the data passed in will always be reference-able.


From jy0922.shim at samsung.com  Tue Jun 22 00:00:42 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Tue, 22 Jun 2010 13:00:42 +0900
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <AANLkTik5ScLMuo5OTSFl_k7qfrBR8xAicVrt98CXqqBa@mail.gmail.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>
	<20100621091952.GB7702@n2100.arm.linux.org.uk>
	<AANLkTilU1X1LR33Eed9BVGE2n-dqRuIuUFfbDd3gzEVc@mail.gmail.com>
	<20100621111612.GJ7702@n2100.arm.linux.org.uk>
	<4C200847.9010200@samsung.com>
	<AANLkTikbBkDOVF6ti_bTultATuW1KhciAmKc1Geg1OSH@mail.gmail.com>
	<4C202D8F.7030005@samsung.com>
	<AANLkTik5ScLMuo5OTSFl_k7qfrBR8xAicVrt98CXqqBa@mail.gmail.com>
Message-ID: <4C20356A.1050309@samsung.com>

On 6/22/2010 12:38 PM, Eric Miao wrote:
> On Tue, Jun 22, 2010 at 11:27 AM, Joonyoung Shim
> <jy0922.shim at samsung.com> wrote:
>> On 6/22/2010 12:02 PM, Eric Miao wrote:
>>> On Tue, Jun 22, 2010 at 8:48 AM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>>>> On 6/21/2010 8:16 PM, Russell King - ARM Linux wrote:
>>>>> On Mon, Jun 21, 2010 at 06:39:10PM +0800, Eric Miao wrote:
>>>>>> On Mon, Jun 21, 2010 at 5:19 PM, Russell King - ARM Linux
>>>>>> <linux at arm.linux.org.uk> wrote:
>>>>>>> On Mon, Jun 21, 2010 at 05:05:34PM +0800, Eric Miao wrote:
>>>>>>>> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>>>>>>>>> +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
>>>>>>>>> +{
>>>>>>>>> + ? ? ? struct samsung_keypad_platdata *npd;
>>>>>>>>> +
>>>>>>>>> + ? ? ? if (!pd) {
>>>>>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no platform data\n", __func__);
>>>>>>>>> + ? ? ? ? ? ? ? return;
>>>>>>>>> + ? ? ? }
>>>>>>>>> +
>>>>>>>>> + ? ? ? npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
>>>>>>>>> + ? ? ? if (!npd)
>>>>>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no memory for platform data\n", __func__);
>>>>>>>> This part of the code is actually duplicated again and again and again
>>>>>>>> for each device, PXA and other legacy platforms are bad references for
>>>>>>>> this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
>>>>>>>> major points:
>>>>>>>>
>>>>>>>> ?1. A minimum 'struct pxa_device_desc' for a simple description of a
>>>>>>>> ? ? device (more than 90% of the devices can be described that way),
>>>>>>>> ? ? and avoid using a comparatively heavier weight platform_device,
>>>>>>>> ? ? which can be generated at run-time
>>>>>>>>
>>>>>>>> ?2. pxa_register_device() to allocate and register the platform_device
>>>>>>>> ? ? at run-time, along with the platform data
>>>>>>> It's a bad idea to make platform data be run-time discardable like this:
>>>>>>>
>>>>>>>>> +struct samsung_keypad_platdata {
>>>>>>>>> + ? ? ? const struct matrix_keymap_data *keymap_data;
>>>>>>> What you end up with is some platform data structures which must be kept
>>>>>>> (those which have pointers to them from the platform data), and others
>>>>>>> (the platform data itself) which can be discarded at runtime.
>>>>>>>
>>>>>>> We know that the __initdata attributations cause lots of problems -
>>>>>>> they're frequently wrong. ?Just see the constant hastle with __devinit
>>>>>>> et.al. ?The same issue happens with __initdata as well.
>>>>>>>
>>>>>>> So why make things more complicated by allowing some platform data
>>>>>>> structures to be discardable and others not to be? ?Is their small
>>>>>>> size (maybe 6 words for this one) really worth the hastle of getting
>>>>>>> __initdata attributations wrong (eg, on the keymap data?)
>>>>>>>
>>>>>> Russell,
>>>>>>
>>>>>> The benefit I see is when multiple boards are compiled in, those
>>>>>> data not used can be automatically discarded.
>>>>> Yes, but only some of the data can be discarded.  Continuing with the
>>>>> example in hand, while you can discard the six words which represent
>>>>> samsung_keypad_platdata, but the keymap_data can't be because that won't
>>>>> be re-allocated, which is probably a much larger data structure.
>>>>>
>>>> No. the keymap_data is possible too. The keypad driver allocates other
>>>> keymap area of input device and it is assigned from datas based on this
>>>> keymap_data.
>>>>
>>> This is a generic issue. Even if in your example, you can avoid this by
>>> re-allocation and re-assignment (ignore the performance issue for such
>>> behavior), the real question is the difficult to track all these down. Since
>> Right, it can occur difficulty of maintain. I wanted just to inform the
>> current fact.
>>
>>> matrix_keypad_data is something out of your control (it was actually
>>> drafted by me and Dmitry if you are interested), and think about one day
>>> I changed it's definition, now you have to sync your driver and code every
>>> time to make sure the discarded data is not referenced.
>>>
>> if matrix_keypad_data is changed, i think the patchset should included
>> change of related other parts using it.
>>
> 
> That's reasonable but difficult in practice, every keypad driver using
> matrix_keypad_data could be doing things differently. That's what I'm

Just FYI, correct name is matrix_keymap_data and current all keypad 
drivers using matrix_keymap_data use it to same way.

> concerned about. Things will be much easier for driver writers if he
> knows the data passed in will always be reference-able.
> 



From viresh.kumar at st.com  Tue Jun 22 00:00:54 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Tue, 22 Jun 2010 09:30:54 +0530
Subject: [PATCH V2] GPIO PL061: Adding Clk framework support
In-Reply-To: <AANLkTim0x5_4re3CWzWDRr1QMq46sQa1SCSyAiymmiUW@mail.gmail.com>
References: <1277103463-7311-1-git-send-email-viresh.kumar@st.com>	<20100621154121.GA4290@debian>
	<AANLkTim0x5_4re3CWzWDRr1QMq46sQa1SCSyAiymmiUW@mail.gmail.com>
Message-ID: <4C203576.2060200@st.com>

On 6/21/2010 11:04 PM, Linus Walleij wrote:
> 2010/6/21 Rabin Vincent <rabin at rab.in>:
>> On Mon, Jun 21, 2010 at 12:27:43PM +0530, Viresh KUMAR wrote:
>>> +     chip->clk = clk_get(&dev->dev, NULL);
>>> +     if (IS_ERR(chip->clk)) {
>>> +             ret = PTR_ERR(chip->clk);
>>> +             goto iounmap;
>>> +     }
>>
>> Have you verified that all platforms using this driver already have
>> clocks with the appropriate names?   Otherwise this patch will break
>> those platforms.
> 
> The ARM Versatiles and RealViews are always clocked I think,
> so clock support should be optional.
> 
> When I added a clock lookup to the PL08x block recently I used
> a construct like this for an optional clock:
> 
> chip->clk = clk_get(&dev->dev, NULL);
> if (IS_ERR(chip->clk)) {
>        ret = PTR_ERR(chip->clk);
>        if (ret == -ENOENT)
>           /* No block clock in this platform */
>           chip->clk = NULL;
>        else
>           goto iounmap;
> }
> 
> This will work whenever clkdevice is used, since that
> returns -ENOENT for nonexisting entries.
> 
> Then:
> 
> if (chip->clk)
>   clk_enable(chip->clk);
> 

Will modify it, as suggested.

thanks
viresh.


From viresh.kumar at st.com  Tue Jun 22 00:07:26 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Tue, 22 Jun 2010 09:37:26 +0530
Subject: [PATCH V2] GPIO PL061: Adding Clk framework support
In-Reply-To: <20100621174101.GB11851@tarshish>
References: <1277103463-7311-1-git-send-email-viresh.kumar@st.com>
	<20100621174101.GB11851@tarshish>
Message-ID: <4C2036FE.40603@st.com>

On 6/21/2010 11:11 PM, Baruch Siach wrote:
> Hi Viresh,
> 
> On Mon, Jun 21, 2010 at 12:27:43PM +0530, Viresh KUMAR wrote:
>> From: Viresh KUMAR <viresh.kumar at st.com>
>>
>> GPIO Clk is never enabled on Platforms, like: SPEAr, which are based upon clock
>> framework and use PL061 driver. This patch adds support for Clk enabling and
>> disabling as and when gpios are requested and freed.
>>
>> Modifications since V1:
>>  - Removed usage_count, as already done by clk framework.
>>  - Checking error case of clk_enable.
>>
>> Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
> 
> Acked-by: Baruch Siach <baruch at tkos.co.il>
> 

Baruch,

Sorry, but you need to review another version.

viresh.


From viresh.kumar at st.com  Tue Jun 22 00:07:30 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Tue, 22 Jun 2010 09:37:30 +0530
Subject: [PATCH v2] GPIO PL061: Adding Clk framework support
Message-ID: <1277179650-1440-1-git-send-email-viresh.kumar@st.com>

From: Viresh KUMAR <viresh.kumar at st.com>

GPIO Clk is never enabled on Platforms, like: SPEAr, which are based upon clock
framework and use PL061 driver. This patch adds support for Clk enabling and
disabling as and when gpios are requested and freed.

modifications since V2:
 - if clk_get returns -ENOENT, then work without clk enable/disable.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/gpio/pl061.c |   47 ++++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 44 insertions(+), 3 deletions(-)

diff --git a/drivers/gpio/pl061.c b/drivers/gpio/pl061.c
index 105701a..b2a556b 100644
--- a/drivers/gpio/pl061.c
+++ b/drivers/gpio/pl061.c
@@ -11,7 +11,10 @@
  *
  * Data sheet: ARM DDI 0190B, September 2000
  */
+
+#include <linux/clk.h>
 #include <linux/spinlock.h>
+#include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/module.h>
 #include <linux/list.h>
@@ -56,8 +59,31 @@ struct pl061_gpio {
 	void __iomem		*base;
 	unsigned		irq_base;
 	struct gpio_chip	gc;
+	struct clk		*clk;
 };
 
+static int pl061_request(struct gpio_chip *gc, unsigned offset)
+{
+	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
+	int ret;
+
+	if (offset >= gc->ngpio)
+		return -EINVAL;
+
+	if (chip->clk)
+		ret = clk_enable(chip->clk);
+
+	return ret
+}
+
+static void pl061_free(struct gpio_chip *gc, unsigned offset)
+{
+	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
+
+	if (chip->clk)
+		clk_disable(chip->clk);
+}
+
 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
 {
 	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
@@ -260,10 +286,22 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 		goto release_region;
 	}
 
+	chip->clk = clk_get(&dev->dev, NULL);
+	if (IS_ERR(chip->clk)) {
+		ret = PTR_ERR(chip->clk);
+		/* clk Not present */
+		if (ret == -ENOENT)
+			chip->clk = NULL;
+		else
+			goto iounmap;
+	}
+
 	spin_lock_init(&chip->lock);
 	spin_lock_init(&chip->irq_lock);
 	INIT_LIST_HEAD(&chip->list);
 
+	chip->gc.request = pl061_request;
+	chip->gc.free = pl061_free;
 	chip->gc.direction_input = pl061_direction_input;
 	chip->gc.direction_output = pl061_direction_output;
 	chip->gc.get = pl061_get_value;
@@ -279,7 +317,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 
 	ret = gpiochip_add(&chip->gc);
 	if (ret)
-		goto iounmap;
+		goto free_clk;
 
 	/*
 	 * irq_chip support
@@ -292,7 +330,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 	irq = dev->irq[0];
 	if (irq < 0) {
 		ret = -ENODEV;
-		goto iounmap;
+		goto free_clk;
 	}
 	set_irq_chained_handler(irq, pl061_irq_handler);
 	if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
@@ -300,7 +338,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 		if (chip_list == NULL) {
 			clear_bit(irq, init_irq);
 			ret = -ENOMEM;
-			goto iounmap;
+			goto free_clk;
 		}
 		INIT_LIST_HEAD(chip_list);
 		set_irq_data(irq, chip_list);
@@ -323,6 +361,9 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 
 	return 0;
 
+free_clk:
+	if (chip->clk)
+		clk_put(chip->clk);
 iounmap:
 	iounmap(chip->base);
 release_region:
-- 
1.6.0.2



From rabin at rab.in  Tue Jun 22 00:21:16 2010
From: rabin at rab.in (Rabin Vincent)
Date: Tue, 22 Jun 2010 09:51:16 +0530
Subject: [PATCH v2] GPIO PL061: Adding Clk framework support
In-Reply-To: <1277179650-1440-1-git-send-email-viresh.kumar@st.com>
References: <1277179650-1440-1-git-send-email-viresh.kumar@st.com>
Message-ID: <AANLkTimtw4_M4V1ZinQfvi8BGarElXjr47PvTpbQJeiy@mail.gmail.com>

On Tue, Jun 22, 2010 at 9:37 AM, Viresh KUMAR <viresh.kumar at st.com> wrote:
> +static int pl061_request(struct gpio_chip *gc, unsigned offset)
> +{
> + ? ? ? struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
> + ? ? ? int ret;
> +
> + ? ? ? if (offset >= gc->ngpio)
> + ? ? ? ? ? ? ? return -EINVAL;
> +
> + ? ? ? if (chip->clk)
> + ? ? ? ? ? ? ? ret = clk_enable(chip->clk);
> +
> + ? ? ? return ret

Missing semicolon.

Also, returning uninitialized values when chip->clk is not set.

You can probably just not register these callbacks for the
!chip->clk case.

Rabin


From baruch at tkos.co.il  Tue Jun 22 00:43:10 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Tue, 22 Jun 2010 07:43:10 +0300
Subject: [PATCH 1/2] Add a common struct clk
In-Reply-To: <1277098513.947633.945838133095.1.gpush@pororo>
References: <1277098513.947165.104554431018.0.gpush@pororo>
	<1277098513.947633.945838133095.1.gpush@pororo>
Message-ID: <20100622044310.GB26865@jasper.tkos.co.il>

Hi Jeremy,

On Mon, Jun 21, 2010 at 01:35:13PM +0800, Jeremy Kerr wrote:
> We currently have 21 definitions of struct clk in the ARM architecture,
> each defined on a per-platform basis. This makes it difficult to define
> platform- (or architecture-) independent clock sources without making
> assumptions about struct clk, and impossible to compile two
> platforms with different struct clks into a single image.
> 
> This change is an effort to unify struct clk where possible, by defining
> a common struct clk, containing a set of clock operations. Different
> clock implementations can set their own operations, and have a standard
> interface for generic code. The callback interface is exposed to the
> kernel proper, while the clock implementations only need to be seen by
> the platform internals.
> 
> This allows us to share clock code among platforms, and makes it
> possible to dynamically create clock devices in platform-independent
> code.
> 
> Platforms can enable the generic struct clock through
> CONFIG_USE_COMMON_STRUCT_CLK. In this case, the clock infrastructure
> consists of a common struct clk:
> 
> struct clk {
> 	const struct clk_ops	*ops;
> 	unsigned int		enable_count;
> 	struct mutex		mutex;
> };
> 
> And a set of clock operations (defined per type of clock):
> 
> struct clk_operations {

That's clk_ops above, and in the code.

>        int             (*enable)(struct clk *);
>        void            (*disable)(struct clk *);
>        unsigned long   (*get_rate)(struct clk *);
>        [...]
> };
> 
> To define a hardware-specific clock, machine code can "subclass" the
> struct clock into a new struct (adding any device-specific data), and
> provide a set of operations:
> 
> struct clk_foo {
> 	struct clk	clk;
> 	void __iomem	*some_register;
> };
> 
> struct clk_operations clk_foo_ops = {

Ditto.

> 	.get_rate = clk_foo_get_rate,
> };
> 
> The common clock definitions are based on a development patch from Ben
> Herrenschmidt <benh at kernel.crashing.org>.
> 
> Signed-off-by: Jeremy Kerr <jeremy.kerr at canonical.com>

baruch

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From viresh.kumar at st.com  Tue Jun 22 00:42:29 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Tue, 22 Jun 2010 10:12:29 +0530
Subject: [PATCH v2] GPIO PL061: Adding Clk framework support
In-Reply-To: <AANLkTimtw4_M4V1ZinQfvi8BGarElXjr47PvTpbQJeiy@mail.gmail.com>
References: <1277179650-1440-1-git-send-email-viresh.kumar@st.com>
	<AANLkTimtw4_M4V1ZinQfvi8BGarElXjr47PvTpbQJeiy@mail.gmail.com>
Message-ID: <4C203F35.3060402@st.com>

On 6/22/2010 9:51 AM, Rabin Vincent wrote:
> On Tue, Jun 22, 2010 at 9:37 AM, Viresh KUMAR <viresh.kumar at st.com> wrote:
>> +static int pl061_request(struct gpio_chip *gc, unsigned offset)
>> +{
>> +       struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
>> +       int ret;
>> +
>> +       if (offset >= gc->ngpio)
>> +               return -EINVAL;
>> +
>> +       if (chip->clk)
>> +               ret = clk_enable(chip->clk);
>> +
>> +       return ret
> 
> Also, returning uninitialized values when chip->clk is not set.
> 
> You can probably just not register these callbacks for the
> !chip->clk case.
> 

Sorry. Will correct it.


From kgene.kim at samsung.com  Tue Jun 22 01:05:12 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 14:05:12 +0900
Subject: Samsung SoCs naming rules
In-Reply-To: <AANLkTilnjN1dBWPKCuDt_bg8-5GEuSCrOh7vhqGf-VQU@mail.gmail.com>
References: <AANLkTiljyiQohHVJxUsn7Q6_IwTZk2AdNlLRxgGmxNpQ@mail.gmail.com>
	<AANLkTilnjN1dBWPKCuDt_bg8-5GEuSCrOh7vhqGf-VQU@mail.gmail.com>
Message-ID: <011201cb11c8$8236c530$86a44f90$%kim@samsung.com>

Eric Miao wrote:
> 
> On Mon, Jun 21, 2010 at 6:00 PM, Kyungmin Park <kmpark at infradead.org>
wrote:
> > Dear all,
> >
> > Now Samsung SoCs doesn't have any special rules include chip name.
> >
> > Historically s5pc100 is successor form s3c6410 and this chip from
> > s3c2410 series.
> > on the other hand, s5pc110 (cortex a8) and s5pc64xx (armv6) is
> > different from previous chips.
> 
> Don't be shy, Samsung is not the only vendor messes the naming of their
> SoCs. Marvell might have done a better job on this :-)
> 
> >
> > So it's not good idea grouping with the prefix. e.g., s5p series. and
> > the reason to create the samsung.
> >
> 
> My guess is your s5p will focus more on Cortex-A8 (or A9 possibly),
> even with subsequent processors. And only s5pc100 is an exception,
> that's fine, you can still put s5pc100 into mach-s3c6410, and people
> will know it's actually closer to s3c6410. And other SoCs will share the
> common s5p prefix.

Hi Eric,

Actually, S5P does not focus on only Cortex-A8 or -A9.
The S5P6440 and S5P6442 which have ARM11 core are S5P series in Samsung
SoCs, too.

Besides, other S5P SoC which has ARM11 core will be produced.

And S5PC100 is Cortex-A8 SoC, the architecture is different from S3C6410.

Please refer to below URLs.
http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=
835&partnum=S3C6410&xFmly_id=229
http://www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=
834&partnum=S5PC100&xFmly_id=229

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From viresh.kumar at st.com  Tue Jun 22 01:07:27 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Tue, 22 Jun 2010 10:37:27 +0530
Subject: [PATCH v4] GPIO PL061: Adding Clk framework support
Message-ID: <1277183247-4557-1-git-send-email-viresh.kumar@st.com>

From: Viresh KUMAR <viresh.kumar at st.com>

GPIO Clk is never enabled on Platforms, like: SPEAr, which are based upon clock
framework and use PL061 driver. This patch adds support for Clk enabling and
disabling as and when gpios are requested and freed.

Modifications in V4:
 - Not registering gpio_request and gpio_free if clk is not found.

Modifications in V3:
 - if clk_get returns -ENOENT, then work without clk enable/disable.

Signed-off-by: Viresh Kumar <viresh.kumar at st.com>
---
 drivers/gpio/pl061.c |   49 +++++++++++++++++++++++++++++++++++++++++++------
 1 files changed, 43 insertions(+), 6 deletions(-)

diff --git a/drivers/gpio/pl061.c b/drivers/gpio/pl061.c
index 105701a..b826d2b 100644
--- a/drivers/gpio/pl061.c
+++ b/drivers/gpio/pl061.c
@@ -11,7 +11,10 @@
  *
  * Data sheet: ARM DDI 0190B, September 2000
  */
+
+#include <linux/clk.h>
 #include <linux/spinlock.h>
+#include <linux/err.h>
 #include <linux/errno.h>
 #include <linux/module.h>
 #include <linux/list.h>
@@ -56,8 +59,26 @@ struct pl061_gpio {
 	void __iomem		*base;
 	unsigned		irq_base;
 	struct gpio_chip	gc;
+	struct clk		*clk;
 };
 
+static int pl061_request(struct gpio_chip *gc, unsigned offset)
+{
+	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
+
+	if (offset >= gc->ngpio)
+		return -EINVAL;
+
+	return clk_enable(chip->clk);
+}
+
+static void pl061_free(struct gpio_chip *gc, unsigned offset)
+{
+	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
+
+	clk_disable(chip->clk);
+}
+
 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
 {
 	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
@@ -260,9 +281,18 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 		goto release_region;
 	}
 
-	spin_lock_init(&chip->lock);
-	spin_lock_init(&chip->irq_lock);
-	INIT_LIST_HEAD(&chip->list);
+	chip->clk = clk_get(&dev->dev, NULL);
+	if (IS_ERR(chip->clk)) {
+		ret = PTR_ERR(chip->clk);
+		/* clk Not present */
+		if (ret == -ENOENT)
+			chip->clk = NULL;
+		else
+			goto iounmap;
+	} else {
+		chip->gc.request = pl061_request;
+		chip->gc.free = pl061_free;
+	}
 
 	chip->gc.direction_input = pl061_direction_input;
 	chip->gc.direction_output = pl061_direction_output;
@@ -277,9 +307,13 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 
 	chip->irq_base = pdata->irq_base;
 
+	spin_lock_init(&chip->lock);
+	spin_lock_init(&chip->irq_lock);
+	INIT_LIST_HEAD(&chip->list);
+
 	ret = gpiochip_add(&chip->gc);
 	if (ret)
-		goto iounmap;
+		goto free_clk;
 
 	/*
 	 * irq_chip support
@@ -292,7 +326,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 	irq = dev->irq[0];
 	if (irq < 0) {
 		ret = -ENODEV;
-		goto iounmap;
+		goto free_clk;
 	}
 	set_irq_chained_handler(irq, pl061_irq_handler);
 	if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
@@ -300,7 +334,7 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 		if (chip_list == NULL) {
 			clear_bit(irq, init_irq);
 			ret = -ENOMEM;
-			goto iounmap;
+			goto free_clk;
 		}
 		INIT_LIST_HEAD(chip_list);
 		set_irq_data(irq, chip_list);
@@ -323,6 +357,9 @@ static int __init pl061_probe(struct amba_device *dev, struct amba_id *id)
 
 	return 0;
 
+free_clk:
+	if (chip->clk)
+		clk_put(chip->clk);
 iounmap:
 	iounmap(chip->base);
 release_region:
-- 
1.6.0.2



From kmpark at infradead.org  Tue Jun 22 01:20:39 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Tue, 22 Jun 2010 14:20:39 +0900
Subject: Samsung SoCs naming rules
In-Reply-To: <011201cb11c8$8236c530$86a44f90$%kim@samsung.com>
References: <AANLkTiljyiQohHVJxUsn7Q6_IwTZk2AdNlLRxgGmxNpQ@mail.gmail.com>
	<AANLkTilnjN1dBWPKCuDt_bg8-5GEuSCrOh7vhqGf-VQU@mail.gmail.com>
	<011201cb11c8$8236c530$86a44f90$%kim@samsung.com>
Message-ID: <AANLkTikXrvcchcguw4mK4tFKK8AgpH13Q0RcaynSG79d@mail.gmail.com>

On Tue, Jun 22, 2010 at 2:05 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Eric Miao wrote:
>>
>> On Mon, Jun 21, 2010 at 6:00 PM, Kyungmin Park <kmpark at infradead.org>
> wrote:
>> > Dear all,
>> >
>> > Now Samsung SoCs doesn't have any special rules include chip name.
>> >
>> > Historically s5pc100 is successor form s3c6410 and this chip from
>> > s3c2410 series.
>> > on the other hand, s5pc110 (cortex a8) and s5pc64xx (armv6) is
>> > different from previous chips.
>>
>> Don't be shy, Samsung is not the only vendor messes the naming of their
>> SoCs. Marvell might have done a better job on this :-)
>>
>> >
>> > So it's not good idea grouping with the prefix. e.g., s5p series. and
>> > the reason to create the samsung.
>> >
>>
>> My guess is your s5p will focus more on Cortex-A8 (or A9 possibly),
>> even with subsequent processors. And only s5pc100 is an exception,
>> that's fine, you can still put s5pc100 into mach-s3c6410, and people
>> will know it's actually closer to s3c6410. And other SoCs will share the
>> common s5p prefix.
>
> Hi Eric,
>
> Actually, S5P does not focus on only Cortex-A8 or -A9.
> The S5P6440 and S5P6442 which have ARM11 core are S5P series in Samsung
> SoCs, too.
>
> Besides, other S5P SoC which has ARM11 core will be produced.

Then what's base IPs? I mean which cpu either s3c6410 or s5p6440 are similar?

>
> And S5PC100 is Cortex-A8 SoC, the architecture is different from S3C6410.

I can't tell the cpu core. In the view of IPs. it's similar. e.g.,
which 3D core used at 6410 and c100?
Does it same as c110?

Thank you,
Kyungmin Park


From ext-mika.1.westerberg at nokia.com  Tue Jun 22 02:59:12 2010
From: ext-mika.1.westerberg at nokia.com (Mika Westerberg)
Date: Tue, 22 Jun 2010 09:59:12 +0300
Subject: [PATCH 3/3] add ARM crashdump support
In-Reply-To: <cover.1277188127.git.ext-mika.1.westerberg@nokia.com>
References: <cover.1277188127.git.ext-mika.1.westerberg@nokia.com>
Message-ID: <b567a76e7f4502ccd56f818ebd3d6509ebd4a96d.1277188128.git.ext-mika.1.westerberg@nokia.com>

This patch adds support for processing ARM kernel crashdumps as well.

Signed-off-by: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
---
 Makefile       |    4 +-
 arm.c          |  200 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 makedumpfile.h |   33 +++++++++
 3 files changed, 235 insertions(+), 2 deletions(-)
 create mode 100644 arm.c

diff --git a/Makefile b/Makefile
index 4a8a060..3d2ee34 100644
--- a/Makefile
+++ b/Makefile
@@ -23,8 +23,8 @@ CFLAGS_ARCH += -m64
 endif
 
 SRC	= makedumpfile.c makedumpfile.h diskdump_mod.h
-SRC_ARCH = x86.c x86_64.c ia64.c ppc64.c
-OBJ_ARCH = x86.o x86_64.o ia64.o ppc64.o
+SRC_ARCH = arm.c x86.c x86_64.c ia64.c ppc64.c
+OBJ_ARCH = arm.o x86.o x86_64.o ia64.o ppc64.o
 
 all: makedumpfile
 
diff --git a/arm.c b/arm.c
new file mode 100644
index 0000000..5acad78
--- /dev/null
+++ b/arm.c
@@ -0,0 +1,200 @@
+/*
+ * arm.c
+ *
+ * Created by: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifdef __arm__
+
+#include "makedumpfile.h"
+
+#define PMD_TYPE_MASK	3
+#define PMD_TYPE_SECT	2
+#define PMD_TYPE_TABLE	1
+
+#define pgd_index(vaddr) ((vaddr) >> PGDIR_SHIFT)
+#define pte_index(vaddr) ((vaddr >> PAGESHIFT()) & (PTRS_PER_PTE - 1))
+
+#define pgd_offset(pgdir, vaddr) \
+	((pgdir) + pgd_index(vaddr) * 2 * sizeof(unsigned long))
+#define pmd_offset(dir, vaddr) (dir)
+#define pte_offset(pmd, vaddr) \
+	(pmd_page_vaddr(pmd) + pte_index(vaddr) * sizeof(unsigned long))
+
+/*
+ * These only work for kernel directly mapped addresses.
+ */
+#define __va(paddr) ((paddr) - info->phys_base + info->page_offset)
+#define __pa(vaddr) ((vaddr) - info->page_offset + info->phys_base)
+
+static inline unsigned long
+pmd_page_vaddr(unsigned long pmd)
+{
+	unsigned long ptr;
+
+	ptr = pmd & ~(PTRS_PER_PTE * sizeof(void *) - 1);
+	ptr += PTRS_PER_PTE * sizeof(void *);
+
+	return __va(ptr);
+}
+
+int
+get_phys_base_arm(void)
+{
+	unsigned long phys_base = ULONG_MAX;
+	int i;
+
+	/*
+	 * We resolve phys_base from PT_LOAD segments. LMA contains physical
+	 * address of the segment, and we use the first one.
+	 */
+	for (i = 0; i < info->num_load_memory; i++) {
+		const struct pt_load_segment *pls = &info->pt_load_segments[i];
+
+		if (pls->phys_start < phys_base)
+			phys_base = pls->phys_start;
+	}
+
+	if (phys_base == ULONG_MAX) {
+		ERRMSG("Can't determine phys_base.\n");
+		return FALSE;
+	}
+
+	info->phys_base = phys_base;
+	DEBUG_MSG("phys_base    : %lx\n", phys_base);
+
+	return TRUE;
+}
+
+int
+get_machdep_info_arm(void)
+{
+	unsigned long vmlist, vmalloc_start;
+
+	info->page_offset = __PAGE_OFFSET;
+	info->max_physmem_bits = _MAX_PHYSMEM_BITS;
+	info->kernel_start = SYMBOL(_stext);
+	info->section_size_bits = _SECTION_SIZE_BITS;
+
+	/*
+	 * For the compatibility, makedumpfile should run without the symbol
+	 * vmlist and the offset of vm_struct.addr if they are not necessary.
+	 */
+	if ((SYMBOL(vmlist) == NOT_FOUND_SYMBOL) ||
+		OFFSET(vm_struct.addr) == NOT_FOUND_STRUCTURE) {
+		return TRUE;
+	}
+
+	if (!readmem(VADDR, SYMBOL(vmlist), &vmlist, sizeof(vmlist))) {
+		ERRMSG("Can't get vmlist.\n");
+		return FALSE;
+	}
+	if (!readmem(VADDR, vmlist + OFFSET(vm_struct.addr), &vmalloc_start,
+		     sizeof(vmalloc_start))) {
+		ERRMSG("Can't get vmalloc_start.\n");
+		return FALSE;
+	}
+
+	info->vmalloc_start = vmalloc_start;
+
+	DEBUG_MSG("page_offset  : %lx\n", info->page_offset);
+	DEBUG_MSG("kernel_start : %lx\n", info->kernel_start);
+	DEBUG_MSG("vmalloc_start: %lx\n", vmalloc_start);
+
+	return TRUE;
+}
+
+static int
+is_vmalloc_addr_arm(unsigned long vaddr)
+{
+	return (info->vmalloc_start && vaddr >= info->vmalloc_start);
+}
+
+/*
+ * vtop_arm() - translate arbitrary virtual address to physical
+ * @vaddr: virtual address to translate
+ *
+ * Function translates @vaddr into physical address using page tables. This
+ * address can be any virtual address. Returns physical address of the
+ * corresponding virtual address or %NOT_PADDR when there is no translation.
+ */
+static unsigned long long
+vtop_arm(unsigned long vaddr)
+{
+	unsigned long long paddr = NOT_PADDR;
+	unsigned long ptr, pgd, pte, pmd;
+
+	if (SYMBOL(swapper_pg_dir) == NOT_FOUND_SYMBOL) {
+		ERRMSG("Can't get the symbol of swapper_pg_dir.\n");
+		return NOT_PADDR;
+	}
+
+	ptr = pgd_offset(SYMBOL(swapper_pg_dir), vaddr);
+	if (!readmem(VADDR, ptr, &pgd, sizeof(pmd))) {
+		ERRMSG("Can't read pgd\n");
+		return NOT_PADDR;
+	}
+
+	if (info->vaddr_for_vtop == vaddr)
+		MSG("  PGD : %08lx => %08lx\n", ptr, pgd);
+
+	pmd = pmd_offset(pgd, vaddr);
+
+	switch (pmd & PMD_TYPE_MASK) {
+	case PMD_TYPE_TABLE: {
+		/* 4k small page */
+		ptr = pte_offset(pmd, vaddr);
+		if (!readmem(VADDR, ptr, &pte, sizeof(pte))) {
+			ERRMSG("Can't read pte\n");
+			return NOT_PADDR;
+		}
+
+		if (info->vaddr_for_vtop == vaddr)
+			MSG("  PTE : %08lx => %08lx\n", ptr, pte);
+
+		if (!(pte & _PAGE_PRESENT)) {
+			ERRMSG("Can't get a valid pte.\n");
+			return NOT_PADDR;
+		}
+
+		paddr = PAGEBASE(pte) + (vaddr & (PAGESIZE() - 1));
+		break;
+	}
+
+	case PMD_TYPE_SECT:
+		/* 1MB section */
+		pte = pmd & PMD_MASK;
+		paddr = pte + (vaddr & (PMD_SIZE - 1));
+		break;
+	}
+
+	return paddr;
+}
+
+unsigned long long
+vaddr_to_paddr_arm(unsigned long vaddr)
+{
+	unsigned long long paddr;
+
+	if ((paddr = vaddr_to_paddr_general(vaddr)) != NOT_PADDR)
+		return paddr;
+
+	if (is_vmalloc_addr_arm(vaddr))
+		paddr = vtop_arm(vaddr);
+	else
+		paddr = __pa(vaddr);
+
+	return paddr;
+}
+
+#endif /* __arm__ */
diff --git a/makedumpfile.h b/makedumpfile.h
index 2717d81..8a74b34 100644
--- a/makedumpfile.h
+++ b/makedumpfile.h
@@ -506,6 +506,24 @@ do { \
 #define VMEMMAP_START		(info->vmemmap_start)
 #define VMEMMAP_END		(info->vmemmap_end)
 
+#ifdef __arm__
+#define __PAGE_OFFSET		(0xc0000000)
+#define KVBASE_MASK		(0xffff)
+#define KVBASE			(SYMBOL(_stext) & ~KVBASE_MASK)
+#define _SECTION_SIZE_BITS	(28)
+#define _MAX_PHYSMEM_BITS	(32)
+#define ARCH_PFN_OFFSET		(info->phys_base >> PAGESHIFT())
+
+#define PTRS_PER_PTE		(512)
+#define PGDIR_SHIFT		(21)
+#define PMD_SHIFT		(21)
+#define PMD_SIZE		(1UL << PMD_SHIFT)
+#define PMD_MASK		(~(PMD_SIZE - 1))
+
+#define _PAGE_PRESENT		(1 << 0)
+
+#endif /* arm */
+
 #ifdef __x86__
 #define __PAGE_OFFSET		(0xc0000000)
 #define __VMALLOC_RESERVE       (128 << 20)
@@ -653,6 +671,16 @@ do { \
 /*
  * The function of dependence on machine
  */
+#ifdef __arm__
+int get_phys_base_arm(void);
+int get_machdep_info_arm(void);
+unsigned long long vaddr_to_paddr_arm(unsigned long vaddr);
+#define get_phys_base()		get_phys_base_arm()
+#define get_machdep_info()	get_machdep_info_arm()
+#define get_versiondep_info()	TRUE
+#define vaddr_to_paddr(X)	vaddr_to_paddr_arm(X)
+#endif /* arm */
+
 #ifdef __x86__
 int get_machdep_info_x86(void);
 int get_versiondep_info_x86(void);
@@ -1148,6 +1176,11 @@ struct domain_list {
 #define PAGES_PER_MAPWORD 	(sizeof(unsigned long) * 8)
 #define MFNS_PER_FRAME		(info->page_size / sizeof(unsigned long))
 
+#ifdef __arm__
+#define kvtop_xen(X)	FALSE
+#define get_xen_info_arch(X) FALSE
+#endif	/* arm */
+
 #ifdef __x86__
 #define HYPERVISOR_VIRT_START_PAE	(0xF5800000UL)
 #define HYPERVISOR_VIRT_START		(0xFC000000UL)
-- 
1.5.6.5



From ext-mika.1.westerberg at nokia.com  Tue Jun 22 02:59:09 2010
From: ext-mika.1.westerberg at nokia.com (Mika Westerberg)
Date: Tue, 22 Jun 2010 09:59:09 +0300
Subject: [PATCH 0/3] makedumpfile: add support for ARM crashdumps
Message-ID: <cover.1277188127.git.ext-mika.1.westerberg@nokia.com>

Hello,

This series adds support for ARM kernel crashdumps to makedumpfile. Although,
kernel support is not yet in mainline, I think that it doesn't hurt to have
necessary userspace tools available when that happens.

If someone wants to try, kernel patches can be found:
	http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/014230.html

and kexec-tools already contain ARM crashdump support.

Regards,
MW

Mika Westerberg (3):
  use ARCH_PFN_OFFSET for pfn_to_paddr/paddr_to_pfn translations
  page_to_pfn(): use ULONGLONG_MAX to for invalid pfn
  add ARM crashdump support

 Makefile       |    4 +-
 arm.c          |  200 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 makedumpfile.c |    7 +-
 makedumpfile.h |   43 ++++++++++++-
 4 files changed, 247 insertions(+), 7 deletions(-)
 create mode 100644 arm.c



From ext-mika.1.westerberg at nokia.com  Tue Jun 22 02:59:10 2010
From: ext-mika.1.westerberg at nokia.com (Mika Westerberg)
Date: Tue, 22 Jun 2010 09:59:10 +0300
Subject: [PATCH 1/3] use ARCH_PFN_OFFSET for pfn_to_paddr/paddr_to_pfn
	translations
In-Reply-To: <cover.1277188127.git.ext-mika.1.westerberg@nokia.com>
References: <cover.1277188127.git.ext-mika.1.westerberg@nokia.com>
Message-ID: <5867f5fbc8c566b76fa9ccc92ee1587b06cf18c4.1277188128.git.ext-mika.1.westerberg@nokia.com>

This is needed on architectures where PHYS_OFFSET is not always zero.
By default ARCH_PFN_OFFSET is zero but archs may redefine it if needed.

Also make sure that exclude_zero_pages() uses pfn_to_paddr().

Signed-off-by: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
---
 makedumpfile.c |    2 +-
 makedumpfile.h |   10 ++++++++--
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/makedumpfile.c b/makedumpfile.c
index 8a90baa..a33bab6 100644
--- a/makedumpfile.c
+++ b/makedumpfile.c
@@ -4810,7 +4810,7 @@ exclude_zero_pages(void)
 
 	initialize_2nd_bitmap(&bitmap2);
 
-	for (pfn = paddr = 0; pfn < info->max_mapnr;
+	for (pfn = 0, paddr = pfn_to_paddr(pfn); pfn < info->max_mapnr;
 	    pfn++, paddr += info->page_size) {
 
 		print_progress(PROGRESS_ZERO_PAGES, pfn, info->max_mapnr);
diff --git a/makedumpfile.h b/makedumpfile.h
index 2785001..2717d81 100644
--- a/makedumpfile.h
+++ b/makedumpfile.h
@@ -112,8 +112,6 @@ isAnon(unsigned long mapping)
 #define PAGEOFFSET(X)		(((unsigned long)(X)) & (PAGESIZE() - 1))
 #define PAGEBASE(X)		(((unsigned long)(X)) & ~(PAGESIZE() - 1))
 #define _2MB_PAGE_MASK		(~((2*1048576)-1))
-#define paddr_to_pfn(X)		((unsigned long long)(X) >> PAGESHIFT())
-#define pfn_to_paddr(X)		((unsigned long long)(X) << PAGESHIFT())
 
 /*
  * for SPARSEMEM
@@ -696,6 +694,14 @@ unsigned long long vaddr_to_paddr_ia64(unsigned long vaddr);
 #define VADDR_REGION(X)		(((unsigned long)(X)) >> REGION_SHIFT)
 #endif          /* ia64 */
 
+#ifndef ARCH_PFN_OFFSET
+#define ARCH_PFN_OFFSET		0
+#endif
+#define paddr_to_pfn(X) \
+	(((unsigned long long)(X) >> PAGESHIFT()) - ARCH_PFN_OFFSET)
+#define pfn_to_paddr(X) \
+	(((unsigned long long)(X) + ARCH_PFN_OFFSET) << PAGESHIFT())
+
 struct pt_load_segment {
 	off_t			file_offset;
 	unsigned long long	phys_start;
-- 
1.5.6.5



From ext-mika.1.westerberg at nokia.com  Tue Jun 22 02:59:11 2010
From: ext-mika.1.westerberg at nokia.com (Mika Westerberg)
Date: Tue, 22 Jun 2010 09:59:11 +0300
Subject: [PATCH 2/3] page_to_pfn(): use ULONGLONG_MAX to for invalid pfn
In-Reply-To: <cover.1277188127.git.ext-mika.1.westerberg@nokia.com>
References: <cover.1277188127.git.ext-mika.1.westerberg@nokia.com>
Message-ID: <c9fc6b9efa07b4e203d9c4bf13c94e84e9d0bb40.1277188128.git.ext-mika.1.westerberg@nokia.com>

Some architectures define PHYS_PFN_OFFSET to be != 0 (ARM for example). This
means that mem_map[0] is actually first page in kernel direct mapped view (which
is a valid page).

Change invalid pfn to be ULONGLONG_MAX instead of 0 to handle such cases.

Signed-off-by: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
---
 makedumpfile.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/makedumpfile.c b/makedumpfile.c
index a33bab6..89360bd 100644
--- a/makedumpfile.c
+++ b/makedumpfile.c
@@ -4383,7 +4383,8 @@ unsigned long long
 page_to_pfn(unsigned long page)
 {
 	unsigned int num;
-	unsigned long long pfn = 0, index = 0;
+	unsigned long long pfn = ULONGLONG_MAX;
+	unsigned long long index = 0;
 	struct mem_map_data *mmd;
 
 	mmd = info->mem_map_data;
@@ -4398,7 +4399,7 @@ page_to_pfn(unsigned long page)
 		pfn = mmd->pfn_start + index;
 		break;
 	}
-	if (!pfn) {
+	if (pfn == ULONGLONG_MAX) {
 		ERRMSG("Can't convert the address of page descriptor (%lx) to pfn.\n", page);
 		return ULONGLONG_MAX;
 	}
-- 
1.5.6.5



From eric.y.miao at gmail.com  Tue Jun 22 03:15:44 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 22 Jun 2010 15:15:44 +0800
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <4C20356A.1050309@samsung.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com> 
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com> 
	<20100621091952.GB7702@n2100.arm.linux.org.uk>
	<AANLkTilU1X1LR33Eed9BVGE2n-dqRuIuUFfbDd3gzEVc@mail.gmail.com> 
	<20100621111612.GJ7702@n2100.arm.linux.org.uk>
	<4C200847.9010200@samsung.com> 
	<AANLkTikbBkDOVF6ti_bTultATuW1KhciAmKc1Geg1OSH@mail.gmail.com> 
	<4C202D8F.7030005@samsung.com>
	<AANLkTik5ScLMuo5OTSFl_k7qfrBR8xAicVrt98CXqqBa@mail.gmail.com> 
	<4C20356A.1050309@samsung.com>
Message-ID: <AANLkTil-yVO2cDKLccpWVsJFVn3rpaPF7LJOUo5TlAr3@mail.gmail.com>

On Tue, Jun 22, 2010 at 12:00 PM, Joonyoung Shim
<jy0922.shim at samsung.com> wrote:
> On 6/22/2010 12:38 PM, Eric Miao wrote:
>> On Tue, Jun 22, 2010 at 11:27 AM, Joonyoung Shim
>> <jy0922.shim at samsung.com> wrote:
>>> On 6/22/2010 12:02 PM, Eric Miao wrote:
>>>> On Tue, Jun 22, 2010 at 8:48 AM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>>>>> On 6/21/2010 8:16 PM, Russell King - ARM Linux wrote:
>>>>>> On Mon, Jun 21, 2010 at 06:39:10PM +0800, Eric Miao wrote:
>>>>>>> On Mon, Jun 21, 2010 at 5:19 PM, Russell King - ARM Linux
>>>>>>> <linux at arm.linux.org.uk> wrote:
>>>>>>>> On Mon, Jun 21, 2010 at 05:05:34PM +0800, Eric Miao wrote:
>>>>>>>>> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>>>>>>>>>> +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
>>>>>>>>>> +{
>>>>>>>>>> + ? ? ? struct samsung_keypad_platdata *npd;
>>>>>>>>>> +
>>>>>>>>>> + ? ? ? if (!pd) {
>>>>>>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no platform data\n", __func__);
>>>>>>>>>> + ? ? ? ? ? ? ? return;
>>>>>>>>>> + ? ? ? }
>>>>>>>>>> +
>>>>>>>>>> + ? ? ? npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
>>>>>>>>>> + ? ? ? if (!npd)
>>>>>>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no memory for platform data\n", __func__);
>>>>>>>>> This part of the code is actually duplicated again and again and again
>>>>>>>>> for each device, PXA and other legacy platforms are bad references for
>>>>>>>>> this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
>>>>>>>>> major points:
>>>>>>>>>
>>>>>>>>> ?1. A minimum 'struct pxa_device_desc' for a simple description of a
>>>>>>>>> ? ? device (more than 90% of the devices can be described that way),
>>>>>>>>> ? ? and avoid using a comparatively heavier weight platform_device,
>>>>>>>>> ? ? which can be generated at run-time
>>>>>>>>>
>>>>>>>>> ?2. pxa_register_device() to allocate and register the platform_device
>>>>>>>>> ? ? at run-time, along with the platform data
>>>>>>>> It's a bad idea to make platform data be run-time discardable like this:
>>>>>>>>
>>>>>>>>>> +struct samsung_keypad_platdata {
>>>>>>>>>> + ? ? ? const struct matrix_keymap_data *keymap_data;
>>>>>>>> What you end up with is some platform data structures which must be kept
>>>>>>>> (those which have pointers to them from the platform data), and others
>>>>>>>> (the platform data itself) which can be discarded at runtime.
>>>>>>>>
>>>>>>>> We know that the __initdata attributations cause lots of problems -
>>>>>>>> they're frequently wrong. ?Just see the constant hastle with __devinit
>>>>>>>> et.al. ?The same issue happens with __initdata as well.
>>>>>>>>
>>>>>>>> So why make things more complicated by allowing some platform data
>>>>>>>> structures to be discardable and others not to be? ?Is their small
>>>>>>>> size (maybe 6 words for this one) really worth the hastle of getting
>>>>>>>> __initdata attributations wrong (eg, on the keymap data?)
>>>>>>>>
>>>>>>> Russell,
>>>>>>>
>>>>>>> The benefit I see is when multiple boards are compiled in, those
>>>>>>> data not used can be automatically discarded.
>>>>>> Yes, but only some of the data can be discarded. ?Continuing with the
>>>>>> example in hand, while you can discard the six words which represent
>>>>>> samsung_keypad_platdata, but the keymap_data can't be because that won't
>>>>>> be re-allocated, which is probably a much larger data structure.
>>>>>>
>>>>> No. the keymap_data is possible too. The keypad driver allocates other
>>>>> keymap area of input device and it is assigned from datas based on this
>>>>> keymap_data.
>>>>>
>>>> This is a generic issue. Even if in your example, you can avoid this by
>>>> re-allocation and re-assignment (ignore the performance issue for such
>>>> behavior), the real question is the difficult to track all these down. Since
>>> Right, it can occur difficulty of maintain. I wanted just to inform the
>>> current fact.
>>>
>>>> matrix_keypad_data is something out of your control (it was actually
>>>> drafted by me and Dmitry if you are interested), and think about one day
>>>> I changed it's definition, now you have to sync your driver and code every
>>>> time to make sure the discarded data is not referenced.
>>>>
>>> if matrix_keypad_data is changed, i think the patchset should included
>>> change of related other parts using it.
>>>
>>
>> That's reasonable but difficult in practice, every keypad driver using
>> matrix_keypad_data could be doing things differently. That's what I'm
>
> Just FYI, correct name is matrix_keymap_data and current all keypad
> drivers using matrix_keymap_data use it to same way.
>

Note I was just thinking there is a potential issue as been pointed out that
we can improve. And I'm not NACKing your perfect patch. Sorry if I made
you think so.


From myungjoo.ham at samsung.com  Tue Jun 22 03:19:19 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Tue, 22 Jun 2010 16:19:19 +0900
Subject: [PATCH] S5PV210 Correct clock source control register properties
In-Reply-To: <000001cb0f63$3682c5b0$a3885110$%kim@samsung.com>
References: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>
	<005401cb0ecb$c3f16c00$4bd44400$%kim@samsung.com>
	<AANLkTim1psO4ZeZGAgNteJp_ytRhzoPlu4D3VblPgz6w@mail.gmail.com>
	<000001cb0f63$3682c5b0$a3885110$%kim@samsung.com>
Message-ID: <AANLkTimjiBOzK1IfGTEY2xLjZ73uchjJACe8d5LQRB9s@mail.gmail.com>

On Sat, Jun 19, 2010 at 12:55 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> MyungJoo Ham wrote:
>>
>> On Fri, Jun 18, 2010 at 6:50 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>> > MyungJoo Ham wrote:
>> >>
>> >> The clock source controls (struct clksrc_clk) have been often accessing
>> >> CLK_GATE_IPx, which are for clock gating and are accessed by each clock
>> >> as well as the clock source. This duplicated clock issue may incur
>> >> lockup problems when there are two modules accessing the same clock with
>> >> different names.
>> >>
>> > Could you please explain further about the above the statement " accessed by
>> > each clock as well as the clock source"
>>
>> For example, "CLK_GATE_IP2[16:19]" is accessed by "hsmmc" of struct
>> clk (a clock) and "sclk_mmc" of struct clksrc_clk's struct clk (a
>> clock source's clk representation).
>>
>> >
>> >> Besides, the clock source control is supposed to control (setting values
>> >> of MASK, SRC, DIV), not to turn on/off individual clock.
>> >>
>> > That is not quite true. Only S5PV210/S5PC110 have the gate for the clock mux.
>> > S5P6440 and S5PC100, for instance, do not have a gate for the output for
>> > _just_ the clock mux. And the reason why the Clock Mux Gate is provide for
>> > the mux is explained in Section 3.4 of the user manual.
>>
>> In cases where clock mux gating is not available and we have each
>> clock (supplied by this cluck mux) defined separatedly with .enable
>> and .ctrlbit, we'd better omit .enable/.ctrlbit from struct
>> clksrc_clk's struct clk.
>>
>> >
>> >> Another point is that there are registers (CLK_SRC_MASK0/1) specialized
>> >> for masking clock source control in S5PV210/S5PC110 according to the
>> >> user manual (rev 20100201).
>> >>
>> >> Therefore, accessing CLK_SRC_MASK0/1 (rather than accessing
>> >> CLK_GATE_IPx) for the clock source control is safer and fits to the
>> >> semantics of S5PV210/S5PC110 registers. And fortuneatly, each clock
>> >> source defined in clock.c has corresponding bit at CLK_SRC_MASK0/1
>> >> except for MFC, G2D, and G3D.
>> >>
>> > Can you please explain how the use CLK_SRC_MASKx makes it safer. The reason
>> > why MFC, G2D and G3D do not have a corresponding bit in CLK_SRC_MASKx is
>> > mentioned in Section 3.4 of the user manual.
>> >
>> > Let me know your opinion.
>> >
>>
>> It's "EXCEPT FOR MFC, G2D, G3D". I'm not saying that using
>> CLK_SRC_MASKx is safer for these three. For other cases, I guess the
>> lock up example should be fine.
>>
>> However, in most cases, this lockup issue does not make visible problem because:
>> 1. normally, drivers use both clksrc_clk's clk and clk at the same
>> time. for example
>> "mmc_bus".clk_enable;
>> "hsmmc".clk_enable;
>> ?blahblah
>> "hsmmc".clk_disable;
>> "mmc_bus".clk_disable;
>> or
>> 2. drivers sharing the same clock uses only one side of the two.
>> or
>> 3. the execution block between clk_enable and clk_disable is extremely short.
>>
>> Nevertheless, this potential lockup issue is critical and we'd better
>> address it.
>>
>>
>> >> In this patch,
>> >>
>> >> - DAC, HDMI, AUDIO 0/1/2, UCLK(uart) 0/1/2/3, MIXER, FIMC 0/1/2,
>> >> FIMC, MMC 0/1/2/3, CSIS, SPI 0/1, PWI, and PWM clock sources are
>> >> modified to use CLK_SRC_MASK0/1, which were using CLK_GATE_IPx.
>> >>
>> >> - CAM 0/1 did not have enable/disable control. They now access
>> >> ? CLK_SRC_MASK0.
>> >>
>> >> - MFC, G3D, G2D were using CLK_GATE_IPx. However, as there are no clocks
>> >> ? defined to control MFC, G3D, and G2D, we kept them to access
>> >> CLK_GATE_IPx. These may need to be modified (erase .enable, .ctrlbit
>> >> from sclk_mfc, sclk_g2d, sclk_g3d and create clocks: g3d, g2d, mfc)
>> >> later.
>> >>
>> >> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
>> >> ---
>> >> ?arch/arm/mach-s5pv210/clock.c | ?101
>> > ++++++++++++++++++++++-------------------
>> >> ?1 files changed, 55 insertions(+), 46 deletions(-)
>> >>
>> >> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
>> >> index ec5ad8c..08c1063 100644
>> >> --- a/arch/arm/mach-s5pv210/clock.c
>> >> +++ b/arch/arm/mach-s5pv210/clock.c
>> >
>> > (snip)
>> >
>> > --
>
> Strictly speaking, 'duplicated clock problem' and 'clock gating issue which is controlled by CLK_GATE_IPx or CLK_SRC_MASKx' are different problem.
> But mixed above two things in your patch.
>
> I think just need bug fix.
>
> See below mmc case.
>
> Following is for clock gating mmc IP by using CLK_GATE_IPx and can control(clock gating) clocks, 'aclk_hsmmcX' and 'sclk_mmcX' in the mmc IP.
>
> ? ? ? ?{
> ? ? ? ? ? ? ? ?.name ? = "hsmmc",
> ? ? ? ? ? ? ? ?.id ? ? = 0,
> ? ? ? ? ? ? ? ?.parent = &clk_hclk_psys.clk,
> ? ? ? ? ? ? ? ?.enable = s5pv210_clk_ip2_ctrl,
> ? ? ? ? ? ? ? ?.ctrlbit ? ? ? ?= (1<<16),
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.name ? = "hsmmc",
> ? ? ? ? ? ? ? ?.id ? ? = 1,
> ? ? ? ? ? ? ? ?.parent = &clk_hclk_psys.clk,
> ? ? ? ? ? ? ? ?.enable = s5pv210_clk_ip2_ctrl,
> ? ? ? ? ? ? ? ?.ctrlbit ? ? ? ?= (1<<17),
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.name ? = "hsmmc",
> ? ? ? ? ? ? ? ?.id ? ? = 2,
> ? ? ? ? ? ? ? ?.parent = &clk_hclk_psys.clk,
> ? ? ? ? ? ? ? ?.enable = s5pv210_clk_ip2_ctrl,
> ? ? ? ? ? ? ? ?.ctrlbit ? ? ? ?= (1<<18),
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.name ? = "hsmmc",
> ? ? ? ? ? ? ? ?.id ? ? = 3,
> ? ? ? ? ? ? ? ?.parent = &clk_hclk_psys.clk,
> ? ? ? ? ? ? ? ?.enable = s5pv210_clk_ip2_ctrl,
> ? ? ? ? ? ? ? ?.ctrlbit ? ? ? ?= (1<<19),
> ? ? ? ?}...
>
> And following is for clock gating just 'sclk_mmcX' by using CLK_SRC_MASKx.
> But as you know should be 's5pv210_clk_mask0_ctrl' instead of 's5pv210_clk_ip2_ctrl' like below.
>
> @@ -794,8 +794,8 @@ static struct clksrc_clk clksrcs[] = {
> ? ? ? ? ? ? ? ?.clk ? ? ? ? ? ?= {
> ? ? ? ? ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "sclk_mmc",
> ? ? ? ? ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 0,
> - ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip2_ctrl,
> - ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 16),
> + ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
> + ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 8),
> ? ? ? ? ? ? ? ?},
> ? ? ? ? ? ? ? ?.sources = &clkset_group2,
> ? ? ? ? ? ? ? ?.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
> @@ -804,8 +804,8 @@ static struct clksrc_clk clksrcs[] = {
> ? ? ? ? ? ? ? ?.clk ? ? ? ? ? ?= {
> ? ? ? ? ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "sclk_mmc",
> ? ? ? ? ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 1,
> - ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip2_ctrl,
> - ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 17),
> + ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
> + ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 9),
> ? ? ? ? ? ? ? ?},
> ? ? ? ? ? ? ? ?.sources = &clkset_group2,
> ? ? ? ? ? ? ? ?.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
> @@ -814,8 +814,8 @@ static struct clksrc_clk clksrcs[] = {
> ? ? ? ? ? ? ? ?.clk ? ? ? ? ? ?= {
> ? ? ? ? ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "sclk_mmc",
> ? ? ? ? ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 2,
> - ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip2_ctrl,
> - ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 18),
> + ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
> + ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 10),
> ? ? ? ? ? ? ? ?},
> ? ? ? ? ? ? ? ?.sources = &clkset_group2,
> ? ? ? ? ? ? ? ?.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
> @@ -824,8 +824,8 @@ static struct clksrc_clk clksrcs[] = {
> ? ? ? ? ? ? ? ?.clk ? ? ? ? ? ?= {
> ? ? ? ? ? ? ? ? ? ? ? ?.name ? ? ? ? ? = "sclk_mmc",
> ? ? ? ? ? ? ? ? ? ? ? ?.id ? ? ? ? ? ? = 3,
> - ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_ip2_ctrl,
> - ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 19),
> + ? ? ? ? ? ? ? ? ? ? ? .enable ? ? ? ? = s5pv210_clk_mask0_ctrl,
> + ? ? ? ? ? ? ? ? ? ? ? .ctrlbit ? ? ? ? ? ? ? ?= (1 << 11),
> ? ? ? ? ? ? ? ?},
> ? ? ? ? ? ? ? ?.sources = &clkset_group2,
> ? ? ? ? ? ? ? ?.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }
>
>
> I think there is no lockup issue(problem) after bug fix about 'sclk_xxx'.
> Of course, carefully used distinguished clock gating in the relevant device driver.
> Because as I said, CLK_GATE_IPx can disable all of the clock operation of each IP.
> If no need CLK_GATE_IPx, just do clock gating each 'sclk_xxx'.
>
> Could you please re-submit new stuff for bug fix?


Ah, I've got it. So, your intention is to keep clocks with
CLK_SRC/CLK_DIV as a form struct clksrc_clk[] list to control clock
gating and get rid of them from struct clk[] list, right? As long as
we are not going to list a clock in both struct clksrc_clk list and
struct clk list, it should be fine.

However, what about merging hsmmc and sclk_mmc? It there any reason to
keep them separated? (e.g., remove "hsmmc" and let "sclk_mmc" use
CLK_GATE_IPx.

>
> Thanks.
>
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
MyungJoo Ham (???), Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858


From eric.y.miao at gmail.com  Tue Jun 22 03:30:51 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 22 Jun 2010 15:30:51 +0800
Subject: Samsung SoCs naming rules
In-Reply-To: <011201cb11c8$8236c530$86a44f90$%kim@samsung.com>
References: <AANLkTiljyiQohHVJxUsn7Q6_IwTZk2AdNlLRxgGmxNpQ@mail.gmail.com> 
	<AANLkTilnjN1dBWPKCuDt_bg8-5GEuSCrOh7vhqGf-VQU@mail.gmail.com> 
	<011201cb11c8$8236c530$86a44f90$%kim@samsung.com>
Message-ID: <AANLkTinRpWoVSUvDhNsMSF3-zdh-tyCy_xMBwdOV1iLz@mail.gmail.com>

On Tue, Jun 22, 2010 at 1:05 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Eric Miao wrote:
>>
>> On Mon, Jun 21, 2010 at 6:00 PM, Kyungmin Park <kmpark at infradead.org>
> wrote:
>> > Dear all,
>> >
>> > Now Samsung SoCs doesn't have any special rules include chip name.
>> >
>> > Historically s5pc100 is successor form s3c6410 and this chip from
>> > s3c2410 series.
>> > on the other hand, s5pc110 (cortex a8) and s5pc64xx (armv6) is
>> > different from previous chips.
>>
>> Don't be shy, Samsung is not the only vendor messes the naming of their
>> SoCs. Marvell might have done a better job on this :-)
>>
>> >
>> > So it's not good idea grouping with the prefix. e.g., s5p series. and
>> > the reason to create the samsung.
>> >
>>
>> My guess is your s5p will focus more on Cortex-A8 (or A9 possibly),
>> even with subsequent processors. And only s5pc100 is an exception,
>> that's fine, you can still put s5pc100 into mach-s3c6410, and people
>> will know it's actually closer to s3c6410. And other SoCs will share the
>> common s5p prefix.
>
> Hi Eric,
>
> Actually, S5P does not focus on only Cortex-A8 or -A9.
> The S5P6440 and S5P6442 which have ARM11 core are S5P series in Samsung
> SoCs, too.

Sometimes it's not possible to have a perfect and consistent naming.
So if s5p644x is more like s3c64xx, actually it's OK to merge them
unless there are fundamental changes.

>
> Besides, other S5P SoC which has ARM11 core will be produced.
>
> And S5PC100 is Cortex-A8 SoC, the architecture is different from S3C6410.

And sometimes it's not a problem even with different ARM cores, the
core does actually have a good abstraction already. The major differences
are the components around that core, at the SoC level.

I'm still a bit puzzled since the question seems to be too generic. Could you
please give some examples of the naming issues you have, specifically?


From jy0922.shim at samsung.com  Tue Jun 22 03:33:39 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Tue, 22 Jun 2010 16:33:39 +0900
Subject: [PATCH v5 1/3] ARM: SAMSUNG: Add keypad device support
In-Reply-To: <AANLkTil-yVO2cDKLccpWVsJFVn3rpaPF7LJOUo5TlAr3@mail.gmail.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<AANLkTil1aiJ1gu6jRrO4LeB0fYltOq4A3wXJJB1ZOa8q@mail.gmail.com>
	<20100621091952.GB7702@n2100.arm.linux.org.uk>
	<AANLkTilU1X1LR33Eed9BVGE2n-dqRuIuUFfbDd3gzEVc@mail.gmail.com>
	<20100621111612.GJ7702@n2100.arm.linux.org.uk>
	<4C200847.9010200@samsung.com>
	<AANLkTikbBkDOVF6ti_bTultATuW1KhciAmKc1Geg1OSH@mail.gmail.com>
	<4C202D8F.7030005@samsung.com>
	<AANLkTik5ScLMuo5OTSFl_k7qfrBR8xAicVrt98CXqqBa@mail.gmail.com>
	<4C20356A.1050309@samsung.com>
	<AANLkTil-yVO2cDKLccpWVsJFVn3rpaPF7LJOUo5TlAr3@mail.gmail.com>
Message-ID: <4C206753.1070202@samsung.com>

On 6/22/2010 4:15 PM, Eric Miao wrote:
> On Tue, Jun 22, 2010 at 12:00 PM, Joonyoung Shim
> <jy0922.shim at samsung.com> wrote:
>> On 6/22/2010 12:38 PM, Eric Miao wrote:
>>> On Tue, Jun 22, 2010 at 11:27 AM, Joonyoung Shim
>>> <jy0922.shim at samsung.com> wrote:
>>>> On 6/22/2010 12:02 PM, Eric Miao wrote:
>>>>> On Tue, Jun 22, 2010 at 8:48 AM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>>>>>> On 6/21/2010 8:16 PM, Russell King - ARM Linux wrote:
>>>>>>> On Mon, Jun 21, 2010 at 06:39:10PM +0800, Eric Miao wrote:
>>>>>>>> On Mon, Jun 21, 2010 at 5:19 PM, Russell King - ARM Linux
>>>>>>>> <linux at arm.linux.org.uk> wrote:
>>>>>>>>> On Mon, Jun 21, 2010 at 05:05:34PM +0800, Eric Miao wrote:
>>>>>>>>>> On Mon, Jun 21, 2010 at 2:26 PM, Joonyoung Shim <jy0922.shim at samsung.com> wrote:
>>>>>>>>>>> +void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
>>>>>>>>>>> +{
>>>>>>>>>>> + ? ? ? struct samsung_keypad_platdata *npd;
>>>>>>>>>>> +
>>>>>>>>>>> + ? ? ? if (!pd) {
>>>>>>>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no platform data\n", __func__);
>>>>>>>>>>> + ? ? ? ? ? ? ? return;
>>>>>>>>>>> + ? ? ? }
>>>>>>>>>>> +
>>>>>>>>>>> + ? ? ? npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
>>>>>>>>>>> + ? ? ? if (!npd)
>>>>>>>>>>> + ? ? ? ? ? ? ? printk(KERN_ERR "%s: no memory for platform data\n", __func__);
>>>>>>>>>> This part of the code is actually duplicated again and again and again
>>>>>>>>>> for each device, PXA and other legacy platforms are bad references for
>>>>>>>>>> this. In arch/arm/mach-mmp/, it might be a bit cleaner, there are three
>>>>>>>>>> major points:
>>>>>>>>>>
>>>>>>>>>> ?1. A minimum 'struct pxa_device_desc' for a simple description of a
>>>>>>>>>> ? ? device (more than 90% of the devices can be described that way),
>>>>>>>>>> ? ? and avoid using a comparatively heavier weight platform_device,
>>>>>>>>>> ? ? which can be generated at run-time
>>>>>>>>>>
>>>>>>>>>> ?2. pxa_register_device() to allocate and register the platform_device
>>>>>>>>>> ? ? at run-time, along with the platform data
>>>>>>>>> It's a bad idea to make platform data be run-time discardable like this:
>>>>>>>>>
>>>>>>>>>>> +struct samsung_keypad_platdata {
>>>>>>>>>>> + ? ? ? const struct matrix_keymap_data *keymap_data;
>>>>>>>>> What you end up with is some platform data structures which must be kept
>>>>>>>>> (those which have pointers to them from the platform data), and others
>>>>>>>>> (the platform data itself) which can be discarded at runtime.
>>>>>>>>>
>>>>>>>>> We know that the __initdata attributations cause lots of problems -
>>>>>>>>> they're frequently wrong. ?Just see the constant hastle with __devinit
>>>>>>>>> et.al. ?The same issue happens with __initdata as well.
>>>>>>>>>
>>>>>>>>> So why make things more complicated by allowing some platform data
>>>>>>>>> structures to be discardable and others not to be? ?Is their small
>>>>>>>>> size (maybe 6 words for this one) really worth the hastle of getting
>>>>>>>>> __initdata attributations wrong (eg, on the keymap data?)
>>>>>>>>>
>>>>>>>> Russell,
>>>>>>>>
>>>>>>>> The benefit I see is when multiple boards are compiled in, those
>>>>>>>> data not used can be automatically discarded.
>>>>>>> Yes, but only some of the data can be discarded.  Continuing with the
>>>>>>> example in hand, while you can discard the six words which represent
>>>>>>> samsung_keypad_platdata, but the keymap_data can't be because that won't
>>>>>>> be re-allocated, which is probably a much larger data structure.
>>>>>>>
>>>>>> No. the keymap_data is possible too. The keypad driver allocates other
>>>>>> keymap area of input device and it is assigned from datas based on this
>>>>>> keymap_data.
>>>>>>
>>>>> This is a generic issue. Even if in your example, you can avoid this by
>>>>> re-allocation and re-assignment (ignore the performance issue for such
>>>>> behavior), the real question is the difficult to track all these down. Since
>>>> Right, it can occur difficulty of maintain. I wanted just to inform the
>>>> current fact.
>>>>
>>>>> matrix_keypad_data is something out of your control (it was actually
>>>>> drafted by me and Dmitry if you are interested), and think about one day
>>>>> I changed it's definition, now you have to sync your driver and code every
>>>>> time to make sure the discarded data is not referenced.
>>>>>
>>>> if matrix_keypad_data is changed, i think the patchset should included
>>>> change of related other parts using it.
>>>>
>>> That's reasonable but difficult in practice, every keypad driver using
>>> matrix_keypad_data could be doing things differently. That's what I'm
>> Just FYI, correct name is matrix_keymap_data and current all keypad
>> drivers using matrix_keymap_data use it to same way.
>>
> 
> Note I was just thinking there is a potential issue as been pointed out that
> we can improve. And I'm not NACKing your perfect patch. Sorry if I made
> you think so.
> 

Don't mind me. I appreciate your interest.


From mike at compulab.co.il  Tue Jun 22 03:38:01 2010
From: mike at compulab.co.il (Mike Rapoport)
Date: Tue, 22 Jun 2010 10:38:01 +0300
Subject: [PATCH 1/4] [ARM] Remove now unnecessary dma_needs_bounce()
In-Reply-To: <AANLkTimugHXfVUcEmq_DwaSLwelvnS9QoDJcxJaphahJ@mail.gmail.com>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com>
	<1275724538-5075-2-git-send-email-eric.y.miao@gmail.com>
	<AANLkTilJ3UpyHEplDqS_nV8SVDcl_pRRn4glDn7JS1GW@mail.gmail.com>
	<4C1EFABC.4020601@compulab.co.il>
	<AANLkTimugHXfVUcEmq_DwaSLwelvnS9QoDJcxJaphahJ@mail.gmail.com>
Message-ID: <4C206859.6090604@compulab.co.il>

Eric,

Eric Miao wrote:
> 2010/6/21 Mike Rapoport <mike at compulab.co.il>:
>> Eric
>>
>> Eric Miao wrote:
>>> On Sat, Jun 5, 2010 at 3:55 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>>>> With a correct dev->dma_mask before calling dmabounce_register_dev(),
>>>> dma_needs_bounce() is not necessary.
>>>>
>>>> The above is true for it8152.c and ixp4xx/common-pci.c.
>>>>
>>>> The sa1111, though, is a bit complicated. Until it's fully understood
>>>> and fixed, dma_needs_bounce() for sa1111 is kept if CONFIG_SA1111 is
>>>> enabled with no side effect (with the condition of machine_is_*)
>>>>
>>> Sorry I forgot to CC you two. Any feedback is welcome, thanks.
>> Can I pull these changes from your git tree?
> 
> Sorry, just pushed them to the branch below:
> 
>   git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git
> defconfig_cleanup

Can you please enroll the below patch into your tree? Otherwise the kernel
build fails if CONFIG_SA1111 is not selected and I hardly believe anyone
would use pxa2xx_defconfig on CM-X270 :)

Except that, IT8152 works fine and IT8152 part can have
Acked-by: Mike Rapoport <mike at compulab.co.il>


diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index c80d4d2..8bc64bd 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -301,7 +301,8 @@ extern void dmabounce_unregister_dev(struct device *);
  #ifdef CONFIG_SA1111
  extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
  #else
-static inline int dma_needs_bounce(struct device*, dma_addr_t, size_t)
+static inline int dma_needs_bounce(struct device* dev, dma_addr_t dma_addr,
+				   size_t size)
  {
  	return 0;
  }


-- 
Sincerely yours,
Mike.


From igawa at mxs.nes.nec.co.jp  Tue Jun 22 03:40:19 2010
From: igawa at mxs.nes.nec.co.jp (Masayuki Igawa)
Date: Tue, 22 Jun 2010 16:40:19 +0900 (JST)
Subject: [PATCH 0/3] makedumpfile: add support for ARM crashdumps
In-Reply-To: <cover.1277188127.git.ext-mika.1.westerberg@nokia.com>
References: <cover.1277188127.git.ext-mika.1.westerberg@nokia.com>
Message-ID: <20100622.164019.11984249.igawa@mxs.nes.nec.co.jp>

Hi, Mika.

Thank you for your patches.

I'll check them.

BTW, I'm preparing for makedumpfile-v1.3.6 release now.
So I'll skip merging these patches in this v1.3.6 release.
These patches will be merged in the next release(may be v1.3.7).

Thanks.
-- 
Masayuki Igawa


From: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
Subject: [PATCH 0/3] makedumpfile: add support for ARM crashdumps
Date: Tue, 22 Jun 2010 09:59:09 +0300
> Hello,
> 
> This series adds support for ARM kernel crashdumps to makedumpfile. Although,
> kernel support is not yet in mainline, I think that it doesn't hurt to have
> necessary userspace tools available when that happens.
> 
> If someone wants to try, kernel patches can be found:
> 	http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/014230.html
> 
> and kexec-tools already contain ARM crashdump support.
> 
> Regards,
> MW
> 
> Mika Westerberg (3):
>   use ARCH_PFN_OFFSET for pfn_to_paddr/paddr_to_pfn translations
>   page_to_pfn(): use ULONGLONG_MAX to for invalid pfn
>   add ARM crashdump support
> 
>  Makefile       |    4 +-
>  arm.c          |  200 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  makedumpfile.c |    7 +-
>  makedumpfile.h |   43 ++++++++++++-
>  4 files changed, 247 insertions(+), 7 deletions(-)
>  create mode 100644 arm.c
> 
> 
> _______________________________________________
> kexec mailing list
> kexec at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kexec



From kgene.kim at samsung.com  Tue Jun 22 03:45:11 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 16:45:11 +0900
Subject: [PATCH] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <4C2019D4.1040105@samsung.com>
References: <1277163098-10263-1-git-send-email-kgene.kim@samsung.com>
	<4C2019D4.1040105@samsung.com>
Message-ID: <013301cb11de$dac50cf0$904f26d0$%kim@samsung.com>

Joonyoung Shim wrote:
> 
> On 6/22/2010 8:31 AM, Kukjin Kim wrote:
> > From: Joonyoung Shim <jy0922.shim at samsung.com>
> >
> > This patch adds support for keypad driver running on Samsung SoCs. This
> > driver is tested on SMDK6410(S3C6410), SMDKC100(S5PC100),
> Aquila(S5PC110),
> > GONI(S5PC110) and SMDKV210(S5PV210) boards.
> >
> > Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > Tested-by: Naveen Krishna Ch <ch.naveen at samsung.com>
> > [kgene.kim at samsung.com: added comments]
> > Acked-by: Kukjin Kim <kgene.kim at samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> 
> I think this is duplicated posting. Why don't you just reply the
> tested-by or acked-by at previous my mail?

I was just thinking, need to modify comments when added 'Tested-by'.

Anyway, if any problems in here, please kindly ignore.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From eric.y.miao at gmail.com  Tue Jun 22 03:52:18 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 22 Jun 2010 15:52:18 +0800
Subject: [PATCH 1/4] [ARM] Remove now unnecessary dma_needs_bounce()
In-Reply-To: <4C206859.6090604@compulab.co.il>
References: <1275724538-5075-1-git-send-email-eric.y.miao@gmail.com> 
	<1275724538-5075-2-git-send-email-eric.y.miao@gmail.com>
	<AANLkTilJ3UpyHEplDqS_nV8SVDcl_pRRn4glDn7JS1GW@mail.gmail.com> 
	<4C1EFABC.4020601@compulab.co.il>
	<AANLkTimugHXfVUcEmq_DwaSLwelvnS9QoDJcxJaphahJ@mail.gmail.com> 
	<4C206859.6090604@compulab.co.il>
Message-ID: <AANLkTilux5aqK09mYex7bBZq66hjdT2_fWuCywpKDT2Q@mail.gmail.com>

2010/6/22 Mike Rapoport <mike at compulab.co.il>:
> Eric,
>
> Eric Miao wrote:
>>
>> 2010/6/21 Mike Rapoport <mike at compulab.co.il>:
>>>
>>> Eric
>>>
>>> Eric Miao wrote:
>>>>
>>>> On Sat, Jun 5, 2010 at 3:55 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>>>>>
>>>>> With a correct dev->dma_mask before calling dmabounce_register_dev(),
>>>>> dma_needs_bounce() is not necessary.
>>>>>
>>>>> The above is true for it8152.c and ixp4xx/common-pci.c.
>>>>>
>>>>> The sa1111, though, is a bit complicated. Until it's fully understood
>>>>> and fixed, dma_needs_bounce() for sa1111 is kept if CONFIG_SA1111 is
>>>>> enabled with no side effect (with the condition of machine_is_*)
>>>>>
>>>> Sorry I forgot to CC you two. Any feedback is welcome, thanks.
>>>
>>> Can I pull these changes from your git tree?
>>
>> Sorry, just pushed them to the branch below:
>>
>> ?git://git.kernel.org/pub/scm/linux/kernel/git/ycmiao/pxa-linux-2.6.git
>> defconfig_cleanup
>
> Can you please enroll the below patch into your tree? Otherwise the kernel
> build fails if CONFIG_SA1111 is not selected and I hardly believe anyone
> would use pxa2xx_defconfig on CM-X270 :)

Grrr... thanks for the fix.

>
> Except that, IT8152 works fine and IT8152 part can have
> Acked-by: Mike Rapoport <mike at compulab.co.il>
>

Thanks again for the testing.

>
> diff --git a/arch/arm/include/asm/dma-mapping.h
> b/arch/arm/include/asm/dma-mapping.h
> index c80d4d2..8bc64bd 100644
> --- a/arch/arm/include/asm/dma-mapping.h
> +++ b/arch/arm/include/asm/dma-mapping.h
> @@ -301,7 +301,8 @@ extern void dmabounce_unregister_dev(struct device *);
> ?#ifdef CONFIG_SA1111
> ?extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
> ?#else
> -static inline int dma_needs_bounce(struct device*, dma_addr_t, size_t)
> +static inline int dma_needs_bounce(struct device* dev, dma_addr_t dma_addr,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?size_t size)
> ?{
> ? ? ? ?return 0;
> ?}
>
>
> --
> Sincerely yours,
> Mike.
>


From myungjoo.ham at samsung.com  Tue Jun 22 04:05:51 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Tue, 22 Jun 2010 17:05:51 +0900
Subject: [PATCH v2] S5PV210 Correct clock register properties
Message-ID: <1277193951-22559-1-git-send-email-myungjoo.ham@samsung.com>

Note that this patch revises and merges the two previous patches:
[PATCH] S5PV210 Correct clock register properties 
[PATCH] S5PV210 Correct clock source control register properties 

1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which were
defined incorrectly.

2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc,
sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their
twins defined in struct clk init_clocks_disable[] and struct clk
init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK
register to avoid the duplicated clock problem described below.

--- Duplicated Clock Problem ---
Please note that each clock definition should access different control
register; otherwise, the system may suffer lockups. For example, if we
have two clock definitions "a" and "b" which access the same register
(and the shift value). Then, when we do:

	module A
	clk = clk_get("a");
	clk->clk_enable(clk);

	module B (context switch)
	clk = clk_get("b");
	clk->clk_enable(clk);
	do something with clk.
	clk->clk_disable(clk);

	module A (context switch)
	do something with clk
	* At this point, the system may hang.

Therefore, there should be no clock definitions with the same contol
register/shift. If we need to create "aliases", then, creating child
clocks sharing the clock should be fine.

Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
---
 arch/arm/mach-s5pv210/clock.c |   72 ++++++++++++++++++++--------------------
 1 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 154bca4..10a9f84 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -406,13 +406,13 @@ static struct clk init_clocks_disable[] = {
 		.id		= 0,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1<<5),
 	}, {
 		.name		= "i2s_v32",
 		.id		= 1,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1<<6),
 	}
 };
 
@@ -429,25 +429,25 @@ static struct clk init_clocks[] = {
 		.id		= 0,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<7),
+		.ctrlbit	= (1<<17),
 	}, {
 		.name		= "uart",
 		.id		= 1,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<8),
+		.ctrlbit	= (1<<18),
 	}, {
 		.name		= "uart",
 		.id		= 2,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<9),
+		.ctrlbit	= (1<<19),
 	}, {
 		.name		= "uart",
 		.id		= 3,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<10),
+		.ctrlbit	= (1<<20),
 	},
 };
 
@@ -565,8 +565,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 0,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 4),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 24),
 	},
 	.sources = &clkset_sclk_audio0,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
@@ -594,8 +594,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 1,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 5),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 25),
 	},
 	.sources = &clkset_sclk_audio1,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
@@ -623,8 +623,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 2,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 6),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 26),
 	},
 	.sources = &clkset_sclk_audio2,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
@@ -680,8 +680,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "uclk1",
 			.id		= 0,
-			.ctrlbit	= (1<<17),
-			.enable		= s5pv210_clk_ip3_ctrl,
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 12),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
@@ -690,8 +690,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 18),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 13),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
@@ -700,8 +700,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 19),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 14),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
@@ -710,8 +710,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 3,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 20),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 15),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
@@ -784,8 +784,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_fimd",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip1_ctrl,
-			.ctrlbit	= (1 << 0),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 5),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
@@ -794,8 +794,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 16),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 8),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
@@ -804,8 +804,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 17),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 9),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
@@ -814,8 +814,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 18),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 10),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
@@ -824,8 +824,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 3,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 19),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 11),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
@@ -874,8 +874,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_spi",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 12),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 16),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
@@ -884,8 +884,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_spi",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 13),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 17),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
@@ -904,8 +904,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_pwm",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 23),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 19),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
-- 
1.6.3.3



From pieterg at gmx.com  Tue Jun 22 04:06:20 2010
From: pieterg at gmx.com (pieterg)
Date: Tue, 22 Jun 2010 10:06:20 +0200
Subject: [PATCH] pxa3xx: Fix HSIO bus x24 multiplier
In-Reply-To: <1277154123-31532-1-git-send-email-marek.vasut@gmail.com>
References: <1277154123-31532-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <201006221006.20590.pieterg@gmx.com>

On Monday 21 June 2010 23:02:03 Marek Vasut wrote:
> The value should be 24, not 0 in the possibilities array. It was just a
> silly mistake.

Good one, reminds me that I've had this one on my list as well for a while. 
I actually went one step further, made the pxa310 use HSIO 312MHz when 
running on 624MHz.

(not sure whether the patch will apply cleanly, but cpufreq-pxa3xx.c still 
looks roughly the same at first glance..)

Rgds, Pieter
-------------- next part --------------
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From adrian.wenl at gmail.com  Tue Jun 22 04:20:29 2010
From: adrian.wenl at gmail.com (Lei Wen)
Date: Tue, 22 Jun 2010 16:20:29 +0800
Subject: [PATCH 07/25] pxa3xx_nand: mtd scan id process could be defined 
	by driver itself
In-Reply-To: <AANLkTimnaBO_Zb0UvPZYzmQNmqJafTv1gWV8KQm_LwC3@mail.gmail.com>
References: <AANLkTilY1gnS_jwZ_xPKhchTLR5cWj7FEla1V76OuMVK@mail.gmail.com>
	<AANLkTimnaBO_Zb0UvPZYzmQNmqJafTv1gWV8KQm_LwC3@mail.gmail.com>
Message-ID: <AANLkTimPAVPFX3vhYhkCBUCXk6-EEirsNBtD5R3xW8Yt@mail.gmail.com>

On Fri, Jun 18, 2010 at 2:58 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 1:34 PM, Haojian Zhuang
> <haojian.zhuang at gmail.com> wrote:
>> From d2958ecbec5d0b7f7aee311fd3e87ed1a858864d Mon Sep 17 00:00:00 2001
>> From: Lei Wen <leiwen at marvell.com>
>> Date: Wed, 2 Jun 2010 21:55:51 +0800
>> Subject: [PATCH 07/25] pxa3xx_nand: mtd scan id process could be
>> defined by driver itself
>>
>> Different NAND driver may require its unique detection. For pxa3xx_nand,
>> it use its self id database to get the necessary info.
>
> I believe I get the central point of this patch: to have a specific
> pxa3xx_nand_scan()
> instead of using the generic nand_scan(). This point is good, yet I
> found it extremely
> difficult to read the patch. Like those chip->xxxx assignment, is that
> also part of this
> patch, I strongly recommend to remove irrelevant changes into separate patches.
>

That is also the part of this patch...
-       this->read_word         = pxa3xx_nand_read_word;
+       chip->read_word         = pxa3xx_nand_read_word;
Just use "chip" to take place of "this"...

Best regards,
Lei


From rabin.vincent at stericsson.com  Tue Jun 22 04:23:01 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 13:53:01 +0530
Subject: [PATCH] Fix flush_kernel_dcache_page for VIPT non-aliasing caches
Message-ID: <1277194981-21548-1-git-send-email-rabin.vincent@stericsson.com>

flush_kernel_dcache_page() is currently a no-op on CPUs with VIPT
non-aliasing data caches.

Because the data and instruction caches are not coherent, not flushing
the D-cache when PIO is done in the kernel could mean that data stays in
the D-cache and stale data is loaded from memory into the I-cache when
this page is later executed from.

This can be observed, for example, as random crashes in the init process
when a file system is mounted from MMC, if the drivers (or the MMC block
driver bounce buffer) uses flush_kernel_dcache_page() (usually
indirectly via the sg_miter API).

This problem is visible on systems with write-allocate caches.  To fix
it, flush the D-cache in flush_kernel_dcache_page() even on VIPT
non-aliasing caches.

Cc: Catalin Marinas <catalin.marinas at arm.com>
Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 arch/arm/include/asm/cacheflush.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..ddbee95 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -406,7 +406,7 @@ static inline void flush_anon_page(struct vm_area_struct *vma,
 static inline void flush_kernel_dcache_page(struct page *page)
 {
 	/* highmem pages are always flushed upon kunmap already */
-	if ((cache_is_vivt() || cache_is_vipt_aliasing()) && !PageHighMem(page))
+	if (!PageHighMem(page))
 		__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
 }
 
-- 
1.7.0



From rabin.vincent at stericsson.com  Tue Jun 22 05:17:36 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 14:47:36 +0530
Subject: [PATCH 01/12] mmci: use sg_miter API to fix multi-page sg handling
Message-ID: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>

The mmci driver's SG list iteration logic assumes that each SG entry
spans only one page, and only maps and flushes one page of the sg.  This
is not a valid assumption.  Fix it by converting the driver to the
sg_miter API, which correctly handles sgs which span multiple pages.
Cache flushing is handled inside the sg_miter API implementation.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 drivers/mmc/host/mmci.c |   55 ++++++++++++++++++++++------------------------
 drivers/mmc/host/mmci.h |   35 +-----------------------------
 2 files changed, 27 insertions(+), 63 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 4917af9..683516b 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -26,7 +26,6 @@
 #include <linux/amba/mmci.h>
 #include <linux/regulator/consumer.h>
 
-#include <asm/cacheflush.h>
 #include <asm/div64.h>
 #include <asm/io.h>
 #include <asm/sizes.h>
@@ -98,6 +97,18 @@ static void mmci_stop_data(struct mmci_host *host)
 	host->data = NULL;
 }
 
+static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
+{
+	unsigned int flags = SG_MITER_ATOMIC;
+
+	if (data->flags & MMC_DATA_READ)
+		flags |= SG_MITER_TO_SG;
+	else
+		flags |= SG_MITER_FROM_SG;
+
+	sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
+}
+
 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 {
 	unsigned int datactrl, timeout, irqmask;
@@ -205,13 +216,6 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
 		else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
 			data->error = -EIO;
 		status |= MCI_DATAEND;
-
-		/*
-		 * We hit an error condition.  Ensure that any data
-		 * partially written to a page is properly coherent.
-		 */
-		if (host->sg_len && data->flags & MMC_DATA_READ)
-			flush_dcache_page(sg_page(host->sg_ptr));
 	}
 	if (status & MCI_DATAEND) {
 		mmci_stop_data(host);
@@ -314,15 +318,18 @@ static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int rem
 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 {
 	struct mmci_host *host = dev_id;
+	struct sg_mapping_iter *sg_miter = &host->sg_miter;
 	void __iomem *base = host->base;
+	unsigned long flags;
 	u32 status;
 
 	status = readl(base + MMCISTATUS);
 
 	dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
 
+	local_irq_save(flags);
+
 	do {
-		unsigned long flags;
 		unsigned int remain, len;
 		char *buffer;
 
@@ -336,11 +343,11 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 		if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
 			break;
 
-		/*
-		 * Map the current scatter buffer.
-		 */
-		buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
-		remain = host->sg_ptr->length - host->sg_off;
+		if (!sg_miter_next(sg_miter))
+			break;
+
+		buffer = sg_miter->addr;
+		remain = sg_miter->length;
 
 		len = 0;
 		if (status & MCI_RXACTIVE)
@@ -348,31 +355,21 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 		if (status & MCI_TXACTIVE)
 			len = mmci_pio_write(host, buffer, remain, status);
 
-		/*
-		 * Unmap the buffer.
-		 */
-		mmci_kunmap_atomic(host, buffer, &flags);
+		sg_miter->consumed = len;
 
-		host->sg_off += len;
 		host->size -= len;
 		remain -= len;
 
 		if (remain)
 			break;
 
-		/*
-		 * If we were reading, and we have completed this
-		 * page, ensure that the data cache is coherent.
-		 */
-		if (status & MCI_RXACTIVE)
-			flush_dcache_page(sg_page(host->sg_ptr));
-
-		if (!mmci_next_sg(host))
-			break;
-
 		status = readl(base + MMCISTATUS);
 	} while (1);
 
+	sg_miter_stop(sg_miter);
+
+	local_irq_restore(flags);
+
 	/*
 	 * If we're nearing the end of the read, switch to
 	 * "any data available" mode.
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index d77062e..7cb24ab 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -171,42 +171,9 @@ struct mmci_host {
 	struct timer_list	timer;
 	unsigned int		oldstat;
 
-	unsigned int		sg_len;
-
 	/* pio stuff */
-	struct scatterlist	*sg_ptr;
-	unsigned int		sg_off;
+	struct sg_mapping_iter	sg_miter;
 	unsigned int		size;
 	struct regulator	*vcc;
 };
 
-static inline void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
-{
-	/*
-	 * Ideally, we want the higher levels to pass us a scatter list.
-	 */
-	host->sg_len = data->sg_len;
-	host->sg_ptr = data->sg;
-	host->sg_off = 0;
-}
-
-static inline int mmci_next_sg(struct mmci_host *host)
-{
-	host->sg_ptr++;
-	host->sg_off = 0;
-	return --host->sg_len;
-}
-
-static inline char *mmci_kmap_atomic(struct mmci_host *host, unsigned long *flags)
-{
-	struct scatterlist *sg = host->sg_ptr;
-
-	local_irq_save(*flags);
-	return kmap_atomic(sg_page(sg), KM_BIO_SRC_IRQ) + sg->offset;
-}
-
-static inline void mmci_kunmap_atomic(struct mmci_host *host, void *buffer, unsigned long *flags)
-{
-	kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
-	local_irq_restore(*flags);
-}
-- 
1.7.0



From rabin.vincent at stericsson.com  Tue Jun 22 05:17:39 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 14:47:39 +0530
Subject: [PATCH 04/12] mmci: allow the card detect status not to be inverted
In-Reply-To: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1277198267-10860-4-git-send-email-rabin.vincent@stericsson.com>

On some platforms, the GPIO value from the gpio_cd pin doesn't need to
be inverted to get it active high.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 drivers/mmc/host/mmci.c   |    2 +-
 include/linux/amba/mmci.h |    2 ++
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 65f0e12..7e56726 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -538,7 +538,7 @@ static int mmci_get_cd(struct mmc_host *mmc)
 	else
 		status = gpio_get_value(host->gpio_cd);
 
-	return !status;
+	return !status ^ host->plat->cd_noinvert;
 }
 
 static const struct mmc_host_ops mmci_ops = {
diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h
index 7e466fe..f9d1bb5 100644
--- a/include/linux/amba/mmci.h
+++ b/include/linux/amba/mmci.h
@@ -23,6 +23,7 @@
  * whether a card is present in the MMC slot or not
  * @gpio_wp: read this GPIO pin to see if the card is write protected
  * @gpio_cd: read this GPIO pin to detect card insertion
+ * @cd_noinvert: true if the gpio_cd pin value or status are active high
  * @capabilities: the capabilities of the block as implemented in
  * this platform, signify anything MMC_CAP_* from mmc/host.h
  */
@@ -33,6 +34,7 @@ struct mmci_platform_data {
 	unsigned int (*status)(struct device *);
 	int	gpio_wp;
 	int	gpio_cd;
+	bool	cd_noinvert;
 	unsigned long capabilities;
 };
 
-- 
1.7.0



From rabin.vincent at stericsson.com  Tue Jun 22 05:17:40 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 14:47:40 +0530
Subject: [PATCH 05/12] mmci: support card detection interrupts
In-Reply-To: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1277198267-10860-5-git-send-email-rabin.vincent@stericsson.com>

If an IRQ can be requested on the card detected GPIO, use it instead of
polling.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 drivers/mmc/host/mmci.c |   24 +++++++++++++++++++++++-
 drivers/mmc/host/mmci.h |    1 +
 2 files changed, 24 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 7e56726..e6477e6 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -541,6 +541,15 @@ static int mmci_get_cd(struct mmc_host *mmc)
 	return !status ^ host->plat->cd_noinvert;
 }
 
+static irqreturn_t mmci_cd_irq(int irq, void *dev_id)
+{
+	struct mmci_host *host = dev_id;
+
+	mmc_detect_change(host->mmc, msecs_to_jiffies(500));
+
+	return IRQ_HANDLED;
+}
+
 static const struct mmc_host_ops mmci_ops = {
 	.request	= mmci_request,
 	.set_ios	= mmci_set_ios,
@@ -576,6 +585,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 
 	host->gpio_wp = -ENOSYS;
 	host->gpio_cd = -ENOSYS;
+	host->gpio_cd_irq = -1;
 
 	host->hw_designer = amba_manf(dev);
 	host->hw_revision = amba_rev(dev);
@@ -654,7 +664,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 	if (host->vcc == NULL)
 		mmc->ocr_avail = plat->ocr_mask;
 	mmc->caps = plat->capabilities;
-	mmc->caps |= MMC_CAP_NEEDS_POLL;
 
 	/*
 	 * We can do SGIO
@@ -698,6 +707,12 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 			host->gpio_cd = plat->gpio_cd;
 		else if (ret != -ENOSYS)
 			goto err_gpio_cd;
+
+		ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd),
+					      mmci_cd_irq, 0,
+					      DRIVER_NAME " (cd)", host);
+		if (ret >= 0)
+			host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd);
 	}
 	if (gpio_is_valid(plat->gpio_wp)) {
 		ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)");
@@ -709,6 +724,9 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 			goto err_gpio_wp;
 	}
 
+	if (host->gpio_cd_irq < 0)
+		mmc->caps |= MMC_CAP_NEEDS_POLL;
+
 	ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
 	if (ret)
 		goto unmap;
@@ -735,6 +753,8 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 	if (host->gpio_wp != -ENOSYS)
 		gpio_free(host->gpio_wp);
  err_gpio_wp:
+	if (host->gpio_cd_irq >= 0)
+		free_irq(host->gpio_cd_irq, host);
 	if (host->gpio_cd != -ENOSYS)
 		gpio_free(host->gpio_cd);
  err_gpio_cd:
@@ -773,6 +793,8 @@ static int __devexit mmci_remove(struct amba_device *dev)
 
 		if (host->gpio_wp != -ENOSYS)
 			gpio_free(host->gpio_wp);
+		if (host->gpio_cd_irq >= 0)
+			free_irq(host->gpio_cd_irq, host);
 		if (host->gpio_cd != -ENOSYS)
 			gpio_free(host->gpio_cd);
 
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 7cb24ab..516adc6 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -155,6 +155,7 @@ struct mmci_host {
 	struct clk		*clk;
 	int			gpio_cd;
 	int			gpio_wp;
+	int			gpio_cd_irq;
 
 	unsigned int		data_xfered;
 
-- 
1.7.0



From rabin.vincent at stericsson.com  Tue Jun 22 05:17:41 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 14:47:41 +0530
Subject: [PATCH 06/12] mmci: allow neither ->status nor gpio_cd to be specified
In-Reply-To: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1277198267-10860-6-git-send-email-rabin.vincent@stericsson.com>

The card may be always present on the board, and for these cases neither
a status callback nor a card detect GPIO is required, and card detection
polling can be disabled.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 drivers/mmc/host/mmci.c |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index e6477e6..322958f 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -533,9 +533,12 @@ static int mmci_get_cd(struct mmc_host *mmc)
 	struct mmci_host *host = mmc_priv(mmc);
 	unsigned int status;
 
-	if (host->gpio_cd == -ENOSYS)
+	if (host->gpio_cd == -ENOSYS) {
+		if (!host->plat->status)
+			return 1; /* Assume always present */
+
 		status = host->plat->status(mmc_dev(host->mmc));
-	else
+	} else
 		status = gpio_get_value(host->gpio_cd);
 
 	return !status ^ host->plat->cd_noinvert;
@@ -724,7 +727,8 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 			goto err_gpio_wp;
 	}
 
-	if (host->gpio_cd_irq < 0)
+	if ((host->plat->status || host->gpio_cd != -ENOSYS)
+	    && host->gpio_cd_irq < 0)
 		mmc->caps |= MMC_CAP_NEEDS_POLL;
 
 	ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host);
-- 
1.7.0



From rabin.vincent at stericsson.com  Tue Jun 22 05:17:37 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 14:47:37 +0530
Subject: [PATCH 02/12] mmci: fix multi block transfers
In-Reply-To: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1277198267-10860-2-git-send-email-rabin.vincent@stericsson.com>

Fix the data transfer size to allow multi block transfers to work.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 drivers/mmc/host/mmci.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 683516b..84d782b 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -120,7 +120,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 		data->blksz, data->blocks, data->flags);
 
 	host->data = data;
-	host->size = data->blksz;
+	host->size = data->blksz * data->blocks;
 	host->data_xfered = 0;
 
 	mmci_init_sg(host, data);
-- 
1.7.0



From rabin.vincent at stericsson.com  Tue Jun 22 05:17:42 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 14:47:42 +0530
Subject: [PATCH 07/12] mmci: pass power_mode to the translate_vdd callback
In-Reply-To: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1277198267-10860-7-git-send-email-rabin.vincent@stericsson.com>

Platforms may have some external power control which need to be
controlled from board specific code.  This is the case for some versions
of the MOP500 board (U8500 platform).

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 drivers/mmc/host/mmci.c   |    3 ++-
 include/linux/amba/mmci.h |    6 ++++--
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 322958f..63eb7f4 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -483,7 +483,8 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 		 * power control behind this translate function.
 		 */
 		if (!host->vcc && host->plat->translate_vdd)
-			pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
+			pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd,
+							 ios->power_mode);
 		/* The ST version does not have this, fall through to POWER_ON */
 		if (host->hw_designer != AMBA_VENDOR_ST) {
 			pwr |= MCI_PWR_UP;
diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h
index f9d1bb5..61b5810 100644
--- a/include/linux/amba/mmci.h
+++ b/include/linux/amba/mmci.h
@@ -17,7 +17,8 @@
  * mmc/host.h
  * @translate_vdd: a callback function to translate a MMC_VDD_*
  * mask into a value to be binary or:ed and written into the
- * MMCIPWR register of the block
+ * MMCIPWR register of the block.  May also control external power
+ * based on the power_mode.
  * @status: if no GPIO read function was given to the block in
  * gpio_wp (below) this function will be called to determine
  * whether a card is present in the MMC slot or not
@@ -30,7 +31,8 @@
 struct mmci_platform_data {
 	unsigned int f_max;
 	unsigned int ocr_mask;
-	u32 (*translate_vdd)(struct device *, unsigned int);
+	u32 (*translate_vdd)(struct device *, unsigned int vdd,
+			     unsigned char power_mode);
 	unsigned int (*status)(struct device *);
 	int	gpio_wp;
 	int	gpio_cd;
-- 
1.7.0



From rabin.vincent at stericsson.com  Tue Jun 22 05:17:43 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 14:47:43 +0530
Subject: [PATCH 08/12] mmci: add variant data and default MCICLOCK support
In-Reply-To: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1277198267-10860-8-git-send-email-rabin.vincent@stericsson.com>

Add a variant_data structure to handle the differences between the
various variants of this peripheral.  Add a first quirk for a default
MCICLOCK value, required on the Ux500 variant where the enable bit needs
to be always set, since it controls access to some registers.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 drivers/mmc/host/mmci.c |   31 ++++++++++++++++++++++++++++++-
 drivers/mmc/host/mmci.h |    2 ++
 2 files changed, 32 insertions(+), 1 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 63eb7f4..a1d1023 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -36,12 +36,30 @@
 
 static unsigned int fmax = 515633;
 
+/**
+ * struct variant_data - MMCI variant-specific quirks
+ * @clkreg: default value for MCICLOCK register
+ */
+struct variant_data {
+	unsigned int		clkreg;
+};
+
+static struct variant_data variant_arm = {
+};
+
+static struct variant_data variant_u300 = {
+};
+
+static struct variant_data variant_ux500 = {
+	.clkreg			= MCI_CLK_ENABLE,
+};
 /*
  * This must be called with host->lock held
  */
 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
 {
-	u32 clk = 0;
+	struct variant_data *variant = host->variant;
+	u32 clk = variant->clkreg;
 
 	if (desired) {
 		if (desired >= host->mclk) {
@@ -564,6 +582,7 @@ static const struct mmc_host_ops mmci_ops = {
 static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 {
 	struct mmci_platform_data *plat = dev->dev.platform_data;
+	struct variant_data *variant = id->data;
 	struct mmci_host *host;
 	struct mmc_host *mmc;
 	int ret;
@@ -608,6 +627,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 		goto clk_free;
 
 	host->plat = plat;
+	host->variant = variant;
 	host->mclk = clk_get_rate(host->clk);
 	/*
 	 * According to the spec, mclk is max 100 MHz,
@@ -860,19 +880,28 @@ static struct amba_id mmci_ids[] = {
 	{
 		.id	= 0x00041180,
 		.mask	= 0x000fffff,
+		.data	= &variant_arm,
 	},
 	{
 		.id	= 0x00041181,
 		.mask	= 0x000fffff,
+		.data	= &variant_arm,
 	},
 	/* ST Micro variants */
 	{
 		.id     = 0x00180180,
 		.mask   = 0x00ffffff,
+		.data	= &variant_u300,
 	},
 	{
 		.id     = 0x00280180,
 		.mask   = 0x00ffffff,
+		.data	= &variant_u300,
+	},
+	{
+		.id     = 0x00480180,
+		.mask   = 0x00ffffff,
+		.data	= &variant_ux500,
 	},
 	{ 0, 0 },
 };
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 516adc6..5e635e1 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -145,6 +145,7 @@
 #define NR_SG		16
 
 struct clk;
+struct variant_data;
 
 struct mmci_host {
 	void __iomem		*base;
@@ -165,6 +166,7 @@ struct mmci_host {
 	unsigned int		cclk;
 	u32			pwr;
 	struct mmci_platform_data *plat;
+	struct variant_data	*variant;
 
 	u8			hw_designer;
 	u8			hw_revision:4;
-- 
1.7.0



From rabin.vincent at stericsson.com  Tue Jun 22 05:17:44 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 14:47:44 +0530
Subject: [PATCH 09/12] mmci: enable hardware flow control on Ux500 variants
In-Reply-To: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1277198267-10860-9-git-send-email-rabin.vincent@stericsson.com>

Although both the U300 and Ux500 use ST variants, the HWFCEN bits are at
different positions, so use the variant_data to store the information.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 drivers/mmc/host/mmci.c |    8 ++++++--
 drivers/mmc/host/mmci.h |    2 --
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index a1d1023..3fca46d 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -39,19 +39,23 @@ static unsigned int fmax = 515633;
 /**
  * struct variant_data - MMCI variant-specific quirks
  * @clkreg: default value for MCICLOCK register
+ * @clkreg_enable: enable value for MMCICLOCK register
  */
 struct variant_data {
 	unsigned int		clkreg;
+	unsigned int		clkreg_enable;
 };
 
 static struct variant_data variant_arm = {
 };
 
 static struct variant_data variant_u300 = {
+	.clkreg_enable		= 1 << 13, /* HWFCEN */
 };
 
 static struct variant_data variant_ux500 = {
 	.clkreg			= MCI_CLK_ENABLE,
+	.clkreg_enable		= 1 << 14, /* HWFCEN */
 };
 /*
  * This must be called with host->lock held
@@ -71,8 +75,8 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
 				clk = 255;
 			host->cclk = host->mclk / (2 * (clk + 1));
 		}
-		if (host->hw_designer == AMBA_VENDOR_ST)
-			clk |= MCI_ST_FCEN; /* Bug fix in ST IP block */
+
+		clk |= variant->clkreg_enable;
 		clk |= MCI_CLK_ENABLE;
 		/* This hasn't proven to be worthwhile */
 		/* clk |= MCI_CLK_PWRSAVE; */
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 5e635e1..0a11ddc 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -28,8 +28,6 @@
 #define MCI_4BIT_BUS		(1 << 11)
 /* 8bit wide buses supported in ST Micro versions */
 #define MCI_ST_8BIT_BUS		(1 << 12)
-/* HW flow control on the ST Micro version */
-#define MCI_ST_FCEN		(1 << 13)
 
 #define MMCIARGUMENT		0x008
 #define MMCICOMMAND		0x00c
-- 
1.7.0



From rabin.vincent at stericsson.com  Tue Jun 22 05:17:38 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 14:47:38 +0530
Subject: [PATCH 03/12] mmci: let core poll for card detection
In-Reply-To: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1277198267-10860-3-git-send-email-rabin.vincent@stericsson.com>

Use the MMC core's ability to poll for card detection.  This also has
the advantage of doing the gpio_get_value from a workqueue instead of
timer, allowing the gpio to be on a sleeping gpiochip.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 drivers/mmc/host/mmci.c |   22 +---------------------
 1 files changed, 1 insertions(+), 21 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 84d782b..65f0e12 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -548,18 +548,6 @@ static const struct mmc_host_ops mmci_ops = {
 	.get_cd		= mmci_get_cd,
 };
 
-static void mmci_check_status(unsigned long data)
-{
-	struct mmci_host *host = (struct mmci_host *)data;
-	unsigned int status = mmci_get_cd(host->mmc);
-
-	if (status ^ host->oldstat)
-		mmc_detect_change(host->mmc, 0);
-
-	host->oldstat = status;
-	mod_timer(&host->timer, jiffies + HZ);
-}
-
 static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 {
 	struct mmci_platform_data *plat = dev->dev.platform_data;
@@ -666,6 +654,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 	if (host->vcc == NULL)
 		mmc->ocr_avail = plat->ocr_mask;
 	mmc->caps = plat->capabilities;
+	mmc->caps |= MMC_CAP_NEEDS_POLL;
 
 	/*
 	 * We can do SGIO
@@ -731,7 +720,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
 
 	amba_set_drvdata(dev, mmc);
-	host->oldstat = mmci_get_cd(host->mmc);
 
 	mmc_add_host(mmc);
 
@@ -739,12 +727,6 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 		mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
 		(unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]);
 
-	init_timer(&host->timer);
-	host->timer.data = (unsigned long)host;
-	host->timer.function = mmci_check_status;
-	host->timer.expires = jiffies + HZ;
-	add_timer(&host->timer);
-
 	return 0;
 
  irq0_free:
@@ -778,8 +760,6 @@ static int __devexit mmci_remove(struct amba_device *dev)
 	if (mmc) {
 		struct mmci_host *host = mmc_priv(mmc);
 
-		del_timer_sync(&host->timer);
-
 		mmc_remove_host(mmc);
 
 		writel(0, host->base + MMCIMASK0);
-- 
1.7.0



From rabin.vincent at stericsson.com  Tue Jun 22 05:17:46 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 14:47:46 +0530
Subject: [PATCH 11/12] mmci: support different FIFO sizes
In-Reply-To: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1277198267-10860-11-git-send-email-rabin.vincent@stericsson.com>

The Ux500 variant has a 32-word FIFO (TXFIFOEMPTY is asserted when it
has 2 left) and TXFIFOHALFEMPTY is repurposed as TXFIFOBURSTWRITEABLE,
with a burst being defined as 8-words.  Likewise for RX.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 drivers/mmc/host/mmci.c |   22 +++++++++++++++++++---
 drivers/mmc/host/mmci.h |    7 -------
 2 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 6c8e41b..4eb7265 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -41,23 +41,35 @@ static unsigned int fmax = 515633;
  * @clkreg: default value for MCICLOCK register
  * @clkreg_enable: enable value for MMCICLOCK register
  * @datalength_bits: number of bits in the MMCIDATALENGTH register
+ * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY
+ *	      is asserted (likewise for RX)
+ * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
+ *		  is asserted (likewise for RX)
  */
 struct variant_data {
 	unsigned int		clkreg;
 	unsigned int		clkreg_enable;
 	unsigned int		datalength_bits;
+	unsigned int		fifosize;
+	unsigned int		fifohalfsize;
 };
 
 static struct variant_data variant_arm = {
+	.fifosize		= 16 * 4,
+	.fifohalfsize		= 8 * 4,
 	.datalength_bits	= 16,
 };
 
 static struct variant_data variant_u300 = {
+	.fifosize		= 16 * 4,
+	.fifohalfsize		= 8 * 4,
 	.clkreg_enable		= 1 << 13, /* HWFCEN */
 	.datalength_bits	= 16,
 };
 
 static struct variant_data variant_ux500 = {
+	.fifosize		= 30 * 4,
+	.fifohalfsize		= 8 * 4,
 	.clkreg			= MCI_CLK_ENABLE,
 	.clkreg_enable		= 1 << 14, /* HWFCEN */
 	.datalength_bits	= 24,
@@ -138,6 +150,7 @@ static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
 
 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 {
+	struct variant_data *variant = host->variant;
 	unsigned int datactrl, timeout, irqmask;
 	unsigned long long clks;
 	void __iomem *base;
@@ -173,7 +186,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 		 * If we have less than a FIFOSIZE of bytes to transfer,
 		 * trigger a PIO interrupt as soon as any data is available.
 		 */
-		if (host->size < MCI_FIFOSIZE)
+		if (host->size < variant->fifosize)
 			irqmask |= MCI_RXDATAAVLBLMASK;
 	} else {
 		/*
@@ -316,13 +329,15 @@ static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int rema
 
 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
 {
+	struct variant_data *variant = host->variant;
 	void __iomem *base = host->base;
 	char *ptr = buffer;
 
 	do {
 		unsigned int count, maxcnt;
 
-		maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
+		maxcnt = status & MCI_TXFIFOEMPTY ?
+			 variant->fifosize : variant->fifohalfsize;
 		count = min(remain, maxcnt);
 
 		writesl(base + MMCIFIFO, ptr, count >> 2);
@@ -346,6 +361,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 {
 	struct mmci_host *host = dev_id;
 	struct sg_mapping_iter *sg_miter = &host->sg_miter;
+	struct variant_data *variant = host->variant;
 	void __iomem *base = host->base;
 	unsigned long flags;
 	u32 status;
@@ -401,7 +417,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 	 * If we're nearing the end of the read, switch to
 	 * "any data available" mode.
 	 */
-	if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
+	if (status & MCI_RXACTIVE && host->size < variant->fifosize)
 		writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
 
 	/*
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 0a11ddc..c7d373c 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -133,13 +133,6 @@
 	MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK|	\
 	MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK)
 
-/*
- * The size of the FIFO in bytes.
- */
-#define MCI_FIFOSIZE	(16*4)
-	
-#define MCI_FIFOHALFSIZE (MCI_FIFOSIZE / 2)
-
 #define NR_SG		16
 
 struct clk;
-- 
1.7.0



From rabin.vincent at stericsson.com  Tue Jun 22 05:17:45 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 14:47:45 +0530
Subject: [PATCH 10/12] mmci: support larger MMCIDATALENGTH register
In-Reply-To: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1277198267-10860-10-git-send-email-rabin.vincent@stericsson.com>

The Ux500 variant has a 24-bit MMCIDATALENGTH register, as opposed to
the 16-bit one on the ARM version.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 drivers/mmc/host/mmci.c |   12 +++++++++---
 1 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 3fca46d..6c8e41b 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -40,22 +40,27 @@ static unsigned int fmax = 515633;
  * struct variant_data - MMCI variant-specific quirks
  * @clkreg: default value for MCICLOCK register
  * @clkreg_enable: enable value for MMCICLOCK register
+ * @datalength_bits: number of bits in the MMCIDATALENGTH register
  */
 struct variant_data {
 	unsigned int		clkreg;
 	unsigned int		clkreg_enable;
+	unsigned int		datalength_bits;
 };
 
 static struct variant_data variant_arm = {
+	.datalength_bits	= 16,
 };
 
 static struct variant_data variant_u300 = {
 	.clkreg_enable		= 1 << 13, /* HWFCEN */
+	.datalength_bits	= 16,
 };
 
 static struct variant_data variant_ux500 = {
 	.clkreg			= MCI_CLK_ENABLE,
 	.clkreg_enable		= 1 << 14, /* HWFCEN */
+	.datalength_bits	= 24,
 };
 /*
  * This must be called with host->lock held
@@ -700,10 +705,11 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 	mmc->max_phys_segs = NR_SG;
 
 	/*
-	 * Since we only have a 16-bit data length register, we must
-	 * ensure that we don't exceed 2^16-1 bytes in a single request.
+	 * Since only a certain number of bits are valid in the data length
+	 * register, we must ensure that we don't exceed 2^num-1 bytes in a
+	 * single request.
 	 */
-	mmc->max_req_size = 65535;
+	mmc->max_req_size = (1 << variant->datalength_bits) - 1;
 
 	/*
 	 * Set the maximum segment size.  Since we aren't doing DMA
-- 
1.7.0



From rabin.vincent at stericsson.com  Tue Jun 22 05:17:47 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Tue, 22 Jun 2010 14:47:47 +0530
Subject: [PATCH 12/12] mmci: support variants with only one irq
In-Reply-To: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1277198267-10860-12-git-send-email-rabin.vincent@stericsson.com>

The Ux500 variants have only one IRQ line hooked up.  Allow these to
work by directing the PIO interrupts also to the first IRQ line.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 drivers/mmc/host/mmci.c |   67 ++++++++++++++++++++++++++++++++++++++++------
 drivers/mmc/host/mmci.h |    5 +++
 2 files changed, 63 insertions(+), 9 deletions(-)

diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 4eb7265..5baa3bd 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -45,6 +45,7 @@ static unsigned int fmax = 515633;
  *	      is asserted (likewise for RX)
  * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY
  *		  is asserted (likewise for RX)
+ * @singleirq: true if only one IRQ line is available
  */
 struct variant_data {
 	unsigned int		clkreg;
@@ -52,6 +53,7 @@ struct variant_data {
 	unsigned int		datalength_bits;
 	unsigned int		fifosize;
 	unsigned int		fifohalfsize;
+	bool			singleirq;
 };
 
 static struct variant_data variant_arm = {
@@ -73,7 +75,9 @@ static struct variant_data variant_ux500 = {
 	.clkreg			= MCI_CLK_ENABLE,
 	.clkreg_enable		= 1 << 14, /* HWFCEN */
 	.datalength_bits	= 24,
+	.singleirq		= true,
 };
+
 /*
  * This must be called with host->lock held
  */
@@ -129,10 +133,27 @@ mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
 	spin_lock(&host->lock);
 }
 
+static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
+{
+	struct variant_data *variant = host->variant;
+	void __iomem *base = host->base;
+
+	if (variant->singleirq) {
+		unsigned int mask0 = readl(base + MMCIMASK0);
+
+		mask0 &= ~MCI_IRQ1MASK;
+		mask0 |= mask;
+
+		writel(mask0, base + MMCIMASK0);
+	}
+
+	writel(mask, base + MMCIMASK1);
+}
+
 static void mmci_stop_data(struct mmci_host *host)
 {
 	writel(0, host->base + MMCIDATACTRL);
-	writel(0, host->base + MMCIMASK1);
+	mmci_set_mask1(host, 0);
 	host->data = NULL;
 }
 
@@ -198,7 +219,7 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
 
 	writel(datactrl, base + MMCIDATACTRL);
 	writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
-	writel(irqmask, base + MMCIMASK1);
+	mmci_set_mask1(host, irqmask);
 }
 
 static void
@@ -260,6 +281,10 @@ mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
 	if (status & MCI_DATAEND) {
 		mmci_stop_data(host);
 
+		/* MCI_DATABLOCKEND not used with single irq */
+		if (host->variant->singleirq && !data->error)
+			host->data_xfered = data->blksz * data->blocks;
+
 		if (!data->stop) {
 			mmci_request_end(host, data->mrq);
 		} else {
@@ -418,7 +443,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 	 * "any data available" mode.
 	 */
 	if (status & MCI_RXACTIVE && host->size < variant->fifosize)
-		writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
+		mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
 
 	/*
 	 * If we run out of data, disable the data IRQs; this
@@ -427,7 +452,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 	 * stops us racing with our data end IRQ.
 	 */
 	if (host->size == 0) {
-		writel(0, base + MMCIMASK1);
+		mmci_set_mask1(host, 0);
 		writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
 	}
 
@@ -440,6 +465,7 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
 static irqreturn_t mmci_irq(int irq, void *dev_id)
 {
 	struct mmci_host *host = dev_id;
+	struct variant_data *variant = host->variant;
 	u32 status;
 	int ret = 0;
 
@@ -450,6 +476,14 @@ static irqreturn_t mmci_irq(int irq, void *dev_id)
 		struct mmc_data *data;
 
 		status = readl(host->base + MMCISTATUS);
+
+		if (variant->singleirq) {
+			if (status & readl(host->base + MMCIMASK1))
+				mmci_pio_irq(irq, dev_id);
+
+			status &= ~MCI_IRQ1MASK;
+		}
+
 		status &= readl(host->base + MMCIMASK0);
 		writel(status, host->base + MMCICLEAR);
 
@@ -610,6 +644,7 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 	struct variant_data *variant = id->data;
 	struct mmci_host *host;
 	struct mmc_host *mmc;
+	unsigned int mask;
 	int ret;
 
 	/* must have platform data */
@@ -782,11 +817,23 @@ static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id)
 	if (ret)
 		goto unmap;
 
-	ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host);
-	if (ret)
-		goto irq0_free;
+	if (!variant->singleirq) {
+		ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED,
+				  DRIVER_NAME " (pio)", host);
+		if (ret)
+			goto irq0_free;
+	}
+
+	/*
+	 * MCI_DATABLOCKEND doesn't seem to immediately clear from the status,
+	 * so we can't use it keep count when only one irq is used because the
+	 * irq will hit for other reasons.
+	 */
+	mask = MCI_IRQENABLE;
+	if (variant->singleirq)
+		mask &= ~MCI_DATABLOCKEND;
 
-	writel(MCI_IRQENABLE, host->base + MMCIMASK0);
+	writel(mask, host->base + MMCIMASK0);
 
 	amba_set_drvdata(dev, mmc);
 
@@ -830,6 +877,7 @@ static int __devexit mmci_remove(struct amba_device *dev)
 
 	if (mmc) {
 		struct mmci_host *host = mmc_priv(mmc);
+		struct variant_data *variant = host->variant;
 
 		mmc_remove_host(mmc);
 
@@ -840,7 +888,8 @@ static int __devexit mmci_remove(struct amba_device *dev)
 		writel(0, host->base + MMCIDATACTRL);
 
 		free_irq(dev->irq[0], host);
-		free_irq(dev->irq[1], host);
+		if (!variant->singleirq)
+			free_irq(dev->irq[1], host);
 
 		if (host->gpio_wp != -ENOSYS)
 			gpio_free(host->gpio_wp);
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index c7d373c..ba203b8 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -133,6 +133,11 @@
 	MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK|	\
 	MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_DATABLOCKENDMASK)
 
+/* These interrupts are directed to IRQ1 when two IRQ lines are available */
+#define MCI_IRQ1MASK \
+	(MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
+	 MCI_TXFIFOHALFEMPTYMASK)
+
 #define NR_SG		16
 
 struct clk;
-- 
1.7.0



From catalin.marinas at arm.com  Tue Jun 22 05:26:13 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 22 Jun 2010 10:26:13 +0100
Subject: [PATCH] Fix flush_kernel_dcache_page for VIPT non-aliasing caches
In-Reply-To: <1277194981-21548-1-git-send-email-rabin.vincent@stericsson.com>
References: <1277194981-21548-1-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <1277198773.22719.16.camel@e102109-lin.cambridge.arm.com>

On Tue, 2010-06-22 at 09:23 +0100, Rabin Vincent wrote:
> flush_kernel_dcache_page() is currently a no-op on CPUs with VIPT
> non-aliasing data caches.
> 
> Because the data and instruction caches are not coherent, not flushing
> the D-cache when PIO is done in the kernel could mean that data stays in
> the D-cache and stale data is loaded from memory into the I-cache when
> this page is later executed from.

That's a long standing problem which I think we have resolved, though
patches not in mainline yet. There have been many discussions in the
past (FYI, more like bed-time reading):

http://comments.gmane.org/gmane.linux.usb.general/27072
http://comments.gmane.org/gmane.linux.ide/44847
http://comments.gmane.org/gmane.linux.kernel.cross-arch/5136
http://comments.gmane.org/gmane.linux.kernel.cross-arch/5170

> This can be observed, for example, as random crashes in the init process
> when a file system is mounted from MMC, if the drivers (or the MMC block
> driver bounce buffer) uses flush_kernel_dcache_page() (usually
> indirectly via the sg_miter API).
> 
> This problem is visible on systems with write-allocate caches.  To fix
> it, flush the D-cache in flush_kernel_dcache_page() even on VIPT
> non-aliasing caches.

I don't think this patch is needed. Implementing this function is only
required if we don't have a coherent D-cache (which is not the case with
non-aliasing VIPT). See Documentation/cachetlb.txt (though not always
accurate but we try to stay close to it).

Block device drivers should use flush_dcache_page() instead of
flush_kernel_dcache_page(). Since not all drivers do this, the solution
I'm proposing (under review so far) is assuming pages to be dirty by
default and thus you get a cache flushing via update_mmu_cache() (or
set_pte_at() on SMP systems).

Could you please try patches 2, 3 and 4 from this thread (can try 1 as
well, I don't mind):

http://thread.gmane.org/gmane.linux.ports.arm.kernel/82987

and post a Tested-by in reply?

The patches are also available in my "proposed" branch, if it is easier
for you to grab:

http://git.kernel.org/?p=linux/kernel/git/cmarinas/linux-2.6-cm.git;a=shortlog;h=refs/heads/proposed

Thanks.

-- 
Catalin



From tony at atomide.com  Tue Jun 22 05:28:09 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 22 Jun 2010 12:28:09 +0300
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100621135120.24299.98499.stgit@baageli.muru.com>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
Message-ID: <20100622092809.GX12255@atomide.com>

* Tony Lindgren <tony at atomide.com> [100621 16:45]:
> The TLS register is only available on ARM1136 r1p0 and later.
> Set HWCAP_TLS flags if hardware TLS is available.
> 
> Note that we now use 0xffff0ff4 for flagging software TLS to
> __kuser_get_tls, and 0xffff0ff8 for storing the software TLS value.

Forgot my own earlier comment to check only for ARM1136, will update
with this patch.

Tony
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From adrian.wenl at gmail.com  Tue Jun 22 05:34:07 2010
From: adrian.wenl at gmail.com (Lei Wen)
Date: Tue, 22 Jun 2010 17:34:07 +0800
Subject: [PATCH 05/25] pxa3xx_nand: rework irq logic
In-Reply-To: <AANLkTikTzNY2hI0JDTOOZpGeOPc_MU79jVJ_1L9XxA_e@mail.gmail.com>
References: <AANLkTimvhEWIDupsj3Ty8vB9ualwU9RsaIxa0CDgWgYQ@mail.gmail.com>
	<AANLkTikTzNY2hI0JDTOOZpGeOPc_MU79jVJ_1L9XxA_e@mail.gmail.com>
Message-ID: <AANLkTikmuCHqJQY2g8G3FsrufO5dKGt9WNZFnmvoSGl2@mail.gmail.com>

On Fri, Jun 18, 2010 at 2:50 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 1:34 PM, Haojian Zhuang
> <haojian.zhuang at gmail.com> wrote:
>> From 18d589a078871a09dec0862241fedd2d1d07be85 Mon Sep 17 00:00:00 2001
>> From: Lei Wen <leiwen at marvell.com>
>> Date: Mon, 31 May 2010 14:05:46 +0800
>> Subject: [PATCH 05/25] pxa3xx_nand: rework irq logic
>>
>> Enable all irq when we start the nand controller, and
>> put all the transaction logic in the pxa3xx_nand_irq.
>>
>
> Didn't look into the change too much, but the idea sounds to me like
> chaining all the logic with different IRQ events, which was my original
> reason of having different states. And considering the page read/write
> is actually to an internal SRAM within the controller, I guess it's quick
> enough. (though I'd suggest to do some experiments of time profiling
> to see if it's going to increase the interrupt latency)
>
>> By doing this way, we could dramatically increase the
>> performance by avoid unnecessary delay.
>>
>
> The removal of __read_id() doesn't look to be part of this patch, no?
>
For write_cmd function has been discard and __read_id function would
not be used, if
continue to keep the __read_id() definition would lead to make failure...

Best regards,
Lei


From eric.y.miao at gmail.com  Tue Jun 22 06:02:25 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Tue, 22 Jun 2010 18:02:25 +0800
Subject: [PATCH 05/25] pxa3xx_nand: rework irq logic
In-Reply-To: <AANLkTikmuCHqJQY2g8G3FsrufO5dKGt9WNZFnmvoSGl2@mail.gmail.com>
References: <AANLkTimvhEWIDupsj3Ty8vB9ualwU9RsaIxa0CDgWgYQ@mail.gmail.com> 
	<AANLkTikTzNY2hI0JDTOOZpGeOPc_MU79jVJ_1L9XxA_e@mail.gmail.com> 
	<AANLkTikmuCHqJQY2g8G3FsrufO5dKGt9WNZFnmvoSGl2@mail.gmail.com>
Message-ID: <AANLkTinzmIud44FuZhZSs94yo16F0ipP-uPdX9gAhdPf@mail.gmail.com>

On Tue, Jun 22, 2010 at 5:34 PM, Lei Wen <adrian.wenl at gmail.com> wrote:
> On Fri, Jun 18, 2010 at 2:50 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>> On Fri, Jun 18, 2010 at 1:34 PM, Haojian Zhuang
>> <haojian.zhuang at gmail.com> wrote:
>>> From 18d589a078871a09dec0862241fedd2d1d07be85 Mon Sep 17 00:00:00 2001
>>> From: Lei Wen <leiwen at marvell.com>
>>> Date: Mon, 31 May 2010 14:05:46 +0800
>>> Subject: [PATCH 05/25] pxa3xx_nand: rework irq logic
>>>
>>> Enable all irq when we start the nand controller, and
>>> put all the transaction logic in the pxa3xx_nand_irq.
>>>
>>
>> Didn't look into the change too much, but the idea sounds to me like
>> chaining all the logic with different IRQ events, which was my original
>> reason of having different states. And considering the page read/write
>> is actually to an internal SRAM within the controller, I guess it's quick
>> enough. (though I'd suggest to do some experiments of time profiling
>> to see if it's going to increase the interrupt latency)
>>
>>> By doing this way, we could dramatically increase the
>>> performance by avoid unnecessary delay.
>>>
>>
>> The removal of __read_id() doesn't look to be part of this patch, no?
>>
> For write_cmd function has been discard and __read_id function would
> not be used, if
> continue to keep the __read_id() definition would lead to make failure...
>

Well, the logic is: this change doesn't belong to this patch, so is it possible
to separate the change apart and still keep it compiling?


From broonie at opensource.wolfsonmicro.com  Tue Jun 22 06:15:00 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Tue, 22 Jun 2010 11:15:00 +0100
Subject: [PATCH] ASoC: Add new TI TLV320AIC3204 CODEC driver
In-Reply-To: <20100621234314.GZ7759@www.longlandclan.yi.org>
References: <1276833465-31702-1-git-send-email-redhatter@gentoo.org>
	<1276899876-19001-1-git-send-email-redhatter@gentoo.org>
	<20100619011221.GC2463@opensource.wolfsonmicro.com>
	<20100621234314.GZ7759@www.longlandclan.yi.org>
Message-ID: <20100622101500.GA15255@opensource.wolfsonmicro.com>

On Tue, Jun 22, 2010 at 09:43:14AM +1000, Stuart Longland wrote:
> On Sat, Jun 19, 2010 at 02:12:21AM +0100, Mark Brown wrote:
> > On Sat, Jun 19, 2010 at 08:24:36AM +1000, Stuart Longland wrote:
> > > +	/* Page 1 */
> > > +	if (page == 1) {
> > > +		if (reg <= 4)
> > > +			return 1;

> > I can't help but think that this'd be more legible with switch ()
> > statements (GCC has an extension for ranges in switch statements which
> > you could use).

> One is to go on a page-by-page basis, which is how I do it using the if
> statements.  Here; I define my ranges so that I start from the very
> end... anything beyond page 70 is invalid ... voila, I eliminate those
> early on.  A number of pages have a similar register pattern, and so I
> make use of nested if statements to explain this.  The if block for
> pages following always use the block before to define the upper,
> non-inclusive bound.

It's not so much the outer ifs that were bothering me, it's the inner
ones where you're doing the final register ranges as just a sequence of
if statements (not even if ... else) which really bothered me here.  The
code just doesn't look like what it's trying to do.

> This is a function largely intended for debugging, in fact, I'm thinking
> I should probably wrap it in #ifdef CONFIG_DEBUG_FS, since the function
> isn't called unless debugfs is enabled.  So I'm not certain that
> performance is worth chasing here given the intended purpose -- it's not
> something that's called all the time, nor something that will be used in
> a production environment.

Oh, I thought you were using it to filter the CODEC register displays?

> That's my thoughts on the issue, perhaps na??ve, but I'm not sure
> there's any real gain in refactoring this.

It's fairly hard to read at the minute - 


From rabin at rab.in  Tue Jun 22 06:29:22 2010
From: rabin at rab.in (Rabin Vincent)
Date: Tue, 22 Jun 2010 15:59:22 +0530
Subject: [PATCH v4 0/4] Patches for -next
In-Reply-To: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
References: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <AANLkTimFl8rOzipTjsJ39HyPQDkEjZeliKHssxyL4df6@mail.gmail.com>

On Mon, Jun 21, 2010 at 8:16 PM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
> Pretty much the same content as v3 but I reordered the last three
> patches to make sure that switching to lazy cache flushing on ARMv7 SMP
> doesn't make the set_pte/cache flushing race more visible (issue handled
> by the set_pte_at patch).
>
>
> Catalin Marinas (4):
> ? ? ?ARM: Remove the domain switching on ARMv6k/v7 CPUs
> ? ? ?ARM: Assume new page cache pages have dirty D-cache
> ? ? ?ARM: Synchronise the I and D caches via set_pte_at() on SMP systems
> ? ? ?ARM: Use lazy cache flushing on ARMv7 SMP systems

I've tried patches 2, 3, and 4 on a Cortex-A9 SMP system and it resolves the
MMC rootfs init crash without the need for the flush_kernel_dcache_page()
change.

Tested-by: Rabin Vincent <rabin.vincent at stericsson.com>

Rabin

P.S.: Patch 1 (at least the version on your proposed branch), doesn't seem to
apply cleanly on linux-next.


From marek.vasut at gmail.com  Tue Jun 22 07:19:02 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Tue, 22 Jun 2010 13:19:02 +0200
Subject: [PATCH] pxa3xx: Fix HSIO bus x24 multiplier
In-Reply-To: <201006221006.20590.pieterg@gmx.com>
References: <1277154123-31532-1-git-send-email-marek.vasut@gmail.com>
	<201006221006.20590.pieterg@gmx.com>
Message-ID: <201006221319.02992.marek.vasut@gmail.com>

Dne ?t 22. ?ervna 2010 10:06:20 pieterg napsal(a):
> On Monday 21 June 2010 23:02:03 Marek Vasut wrote:
> > The value should be 24, not 0 in the possibilities array. It was just a
> > silly mistake.
> 
> Good one, reminds me that I've had this one on my list as well for a while.
> I actually went one step further, made the pxa310 use HSIO 312MHz when
> running on 624MHz.
> 
> (not sure whether the patch will apply cleanly, but cpufreq-pxa3xx.c still
> looks roughly the same at first glance..)
> 
> Rgds, Pieter

Hi,

I'd suggest you to submit a proper patch. With your whole name and using git-
send-email.

Cheers


From adrian.wenl at gmail.com  Tue Jun 22 07:24:20 2010
From: adrian.wenl at gmail.com (Lei Wen)
Date: Tue, 22 Jun 2010 19:24:20 +0800
Subject: [PATCH 05/25] pxa3xx_nand: rework irq logic
In-Reply-To: <AANLkTinzmIud44FuZhZSs94yo16F0ipP-uPdX9gAhdPf@mail.gmail.com>
References: <AANLkTimvhEWIDupsj3Ty8vB9ualwU9RsaIxa0CDgWgYQ@mail.gmail.com>
	<AANLkTikTzNY2hI0JDTOOZpGeOPc_MU79jVJ_1L9XxA_e@mail.gmail.com>
	<AANLkTikmuCHqJQY2g8G3FsrufO5dKGt9WNZFnmvoSGl2@mail.gmail.com>
	<AANLkTinzmIud44FuZhZSs94yo16F0ipP-uPdX9gAhdPf@mail.gmail.com>
Message-ID: <AANLkTinEOvQX0f6jKsGEALSLBMPmeSgx9n6QIsCcHVKG@mail.gmail.com>

On Tue, Jun 22, 2010 at 6:02 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Tue, Jun 22, 2010 at 5:34 PM, Lei Wen <adrian.wenl at gmail.com> wrote:
>> On Fri, Jun 18, 2010 at 2:50 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>>> On Fri, Jun 18, 2010 at 1:34 PM, Haojian Zhuang
>>> <haojian.zhuang at gmail.com> wrote:
>>>> From 18d589a078871a09dec0862241fedd2d1d07be85 Mon Sep 17 00:00:00 2001
>>>> From: Lei Wen <leiwen at marvell.com>
>>>> Date: Mon, 31 May 2010 14:05:46 +0800
>>>> Subject: [PATCH 05/25] pxa3xx_nand: rework irq logic
>>>>
>>>> Enable all irq when we start the nand controller, and
>>>> put all the transaction logic in the pxa3xx_nand_irq.
>>>>
>>>
>>> Didn't look into the change too much, but the idea sounds to me like
>>> chaining all the logic with different IRQ events, which was my original
>>> reason of having different states. And considering the page read/write
>>> is actually to an internal SRAM within the controller, I guess it's quick
>>> enough. (though I'd suggest to do some experiments of time profiling
>>> to see if it's going to increase the interrupt latency)
>>>
>>>> By doing this way, we could dramatically increase the
>>>> performance by avoid unnecessary delay.
>>>>
>>>
>>> The removal of __read_id() doesn't look to be part of this patch, no?
>>>
>> For write_cmd function has been discard and __read_id function would
>> not be used, if
>> continue to keep the __read_id() definition would lead to make failure...
>>
>
> Well, the logic is: this change doesn't belong to this patch, so is it possible
> to separate the change apart and still keep it compiling?
>

Em... Seems reasonable, I'll try to do that. :-)

Best regards,
Lei


From catalin.marinas at arm.com  Tue Jun 22 07:34:01 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 22 Jun 2010 12:34:01 +0100
Subject: [PATCH v4 0/4] Patches for -next
In-Reply-To: <AANLkTimFl8rOzipTjsJ39HyPQDkEjZeliKHssxyL4df6@mail.gmail.com>
References: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
	<AANLkTimFl8rOzipTjsJ39HyPQDkEjZeliKHssxyL4df6@mail.gmail.com>
Message-ID: <1277206441.22719.41.camel@e102109-lin.cambridge.arm.com>

On Tue, 2010-06-22 at 11:29 +0100, Rabin Vincent wrote:
> On Mon, Jun 21, 2010 at 8:16 PM, Catalin Marinas
> <catalin.marinas at arm.com> wrote:
> > Pretty much the same content as v3 but I reordered the last three
> > patches to make sure that switching to lazy cache flushing on ARMv7 SMP
> > doesn't make the set_pte/cache flushing race more visible (issue handled
> > by the set_pte_at patch).
> >
> >
> > Catalin Marinas (4):
> >      ARM: Remove the domain switching on ARMv6k/v7 CPUs
> >      ARM: Assume new page cache pages have dirty D-cache
> >      ARM: Synchronise the I and D caches via set_pte_at() on SMP systems
> >      ARM: Use lazy cache flushing on ARMv7 SMP systems
> 
> I've tried patches 2, 3, and 4 on a Cortex-A9 SMP system and it resolves the
> MMC rootfs init crash without the need for the flush_kernel_dcache_page()
> change.
> 
> Tested-by: Rabin Vincent <rabin.vincent at stericsson.com>

Thanks.

> P.S.: Patch 1 (at least the version on your proposed branch), doesn't seem to
> apply cleanly on linux-next.

It's a bit more intrusive and I'd like to push it to linux-next (but
still waiting for review on this list).

-- 
Catalin



From kgene.kim at samsung.com  Tue Jun 22 08:29:09 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 22 Jun 2010 21:29:09 +0900
Subject: [PATCH v2] s3c64xx: Fix build without SDHCI controllers
In-Reply-To: <1276235941-12114-1-git-send-email-m.szyprowski@samsung.com>
References: <000801cb0900$f64bbdc0$e2e33940$%kim@samsung.com>
	<1276235941-12114-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <015c01cb1206$86bfeda0$943fc8e0$%kim@samsung.com>

Marek Szyprowski wrote:
> 
> This patch fixes the following compilation problem if only NCP machine
> is selected:
> 
> arch/arm/mach-s3c64xx/s3c6410.c: In function ?s3c6410_map_io?:
> arch/arm/mach-s3c64xx/s3c6410.c:51: error: implicit declaration of function
> ?s3c6410_default_sdhci2?
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>

Applied :-)

> ---
>  arch/arm/plat-samsung/include/plat/sdhci.h |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-
> samsung/include/plat/sdhci.h
> index 13f9fb2..2e263a8 100644
> --- a/arch/arm/plat-samsung/include/plat/sdhci.h
> +++ b/arch/arm/plat-samsung/include/plat/sdhci.h
> @@ -166,8 +166,10 @@ static inline void s3c6410_default_sdhci2(void) { }
>  #else
>  static inline void s3c6410_default_sdhci0(void) { }
>  static inline void s3c6410_default_sdhci1(void) { }
> +static inline void s3c6410_default_sdhci2(void) { }
>  static inline void s3c6400_default_sdhci0(void) { }
>  static inline void s3c6400_default_sdhci1(void) { }
> +static inline void s3c6400_default_sdhci2(void) { }
> 
>  #endif /* CONFIG_S3C64XX_SETUP_SDHCI */
> 
> --


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From cbouatmailru at gmail.com  Tue Jun 22 08:47:03 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 22 Jun 2010 16:47:03 +0400
Subject: [PATCH v4 1/4] ARM: Remove the domain switching on ARMv6k/v7 CPUs
In-Reply-To: <20100621144626.26309.59790.stgit@e102109-lin.cambridge.arm.com>
References: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
	<20100621144626.26309.59790.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100622124703.GA12613@oksana.dev.rtsoft.ru>

On Mon, Jun 21, 2010 at 03:46:26PM +0100, Catalin Marinas wrote:
> This patch removes the domain switching functionality via the set_fs and
> __switch_to functions on cores that have a TLS register.
> 
> Currently, the ioremap and vmalloc areas share the same level 1 page
> tables and therefore have the same domain (DOMAIN_KERNEL). When the
> kernel domain is modified from Client to Manager (via the __set_fs or in
> the __switch_to function), the XN (eXecute Never) bit is overridden and
> newer CPUs can speculatively prefetch the ioremap'ed memory.
> 
> Linux performs the kernel domain switching to allow user-specific
> functions (copy_to/from_user, get/put_user etc.) to access kernel
> memory. In order for these functions to work with the kernel domain set
> to Client, the patch modifies the LDRT/STRT and related instructions to
> the LDR/STR ones.
> 
> The user pages access rights are also modified for kernel read-only
> access rather than read/write so that the copy-on-write mechanism still
> works. CPU_USE_DOMAINS gets disabled only if HAS_TLS_REG is defined
> since writing the TLS value to the high vectors page isn't possible.
> 
> The user addresses passed to the kernel are checked by the access_ok()
> function so that they do not point to the kernel space.
> 
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>

I tested this on ARMv6K (ARM11 MPcore) and ARMv7 (Cortex-A9), and
didn't notice any issues. This is also needed for robust mutextes
support... so, if that helps,

Tested-by: Anton Vorontsov <cbouatmailru at gmail.com>

Thanks!


From catalin.marinas at arm.com  Tue Jun 22 08:59:52 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 22 Jun 2010 13:59:52 +0100
Subject: [PATCH 2/2] arm: Make VFPv3 usable on ARMv6
In-Reply-To: <20100621135125.24299.91290.stgit@baageli.muru.com>
References: <20100621135125.24299.91290.stgit@baageli.muru.com>
Message-ID: <1277211592.29532.20.camel@e102109-lin.cambridge.arm.com>

On Mon, 2010-06-21 at 14:51 +0100, Tony Lindgren wrote:
> diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
> index 315a540..19ba626 100644
> --- a/arch/arm/vfp/vfpmodule.c
> +++ b/arch/arm/vfp/vfpmodule.c
> @@ -549,10 +549,14 @@ static int __init vfp_init(void)
>                 /*
>                  * Check for the presence of the Advanced SIMD
>                  * load/store instructions, integer and single
> -                * precision floating point operations.
> +                * precision floating point operations. Only check
> +                * for NEON if the hardware has TLS register as the
> +                * MVFR registers got added in ARM1136 r1p0 with TLS.
>                  */
> -               if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
> -                       elf_hwcap |= HWCAP_NEON;
> +               if (elf_hwcap & HWCAP_TLS) {
> +                       if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
> +                               elf_hwcap |= HWCAP_NEON;
> +               }

MVFR should be available with the new CPU id format:

	((read_cpuid_id() & 0x000f0000) == 0x000f0000)

I think that would be a cleaner test than relying on the TLS presence.

-- 
Catalin



From catalin.marinas at arm.com  Tue Jun 22 09:01:19 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 22 Jun 2010 14:01:19 +0100
Subject: [PATCH v4 1/4] ARM: Remove the domain switching on ARMv6k/v7 CPUs
In-Reply-To: <20100622124703.GA12613@oksana.dev.rtsoft.ru>
References: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
	<20100621144626.26309.59790.stgit@e102109-lin.cambridge.arm.com>
	<20100622124703.GA12613@oksana.dev.rtsoft.ru>
Message-ID: <1277211679.29532.24.camel@e102109-lin.cambridge.arm.com>

On Tue, 2010-06-22 at 13:47 +0100, Anton Vorontsov wrote:
> On Mon, Jun 21, 2010 at 03:46:26PM +0100, Catalin Marinas wrote:
> > This patch removes the domain switching functionality via the set_fs and
> > __switch_to functions on cores that have a TLS register.
> >
> > Currently, the ioremap and vmalloc areas share the same level 1 page
> > tables and therefore have the same domain (DOMAIN_KERNEL). When the
> > kernel domain is modified from Client to Manager (via the __set_fs or in
> > the __switch_to function), the XN (eXecute Never) bit is overridden and
> > newer CPUs can speculatively prefetch the ioremap'ed memory.
> >
> > Linux performs the kernel domain switching to allow user-specific
> > functions (copy_to/from_user, get/put_user etc.) to access kernel
> > memory. In order for these functions to work with the kernel domain set
> > to Client, the patch modifies the LDRT/STRT and related instructions to
> > the LDR/STR ones.
> >
> > The user pages access rights are also modified for kernel read-only
> > access rather than read/write so that the copy-on-write mechanism still
> > works. CPU_USE_DOMAINS gets disabled only if HAS_TLS_REG is defined
> > since writing the TLS value to the high vectors page isn't possible.
> >
> > The user addresses passed to the kernel are checked by the access_ok()
> > function so that they do not point to the kernel space.
> >
> > Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> 
> I tested this on ARMv6K (ARM11 MPcore) and ARMv7 (Cortex-A9), and
> didn't notice any issues. This is also needed for robust mutextes
> support... so, if that helps,
> 
> Tested-by: Anton Vorontsov <cbouatmailru at gmail.com>

Thanks.

-- 
Catalin



From jekhor at gmail.com  Tue Jun 22 09:16:21 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 16:16:21 +0300
Subject: S3C2416 fixes (gpiolib, SDHCI, compilation without FB device)
Message-ID: <1277212585-25605-1-git-send-email-jekhor@gmail.com>

This patch series fixes SDHCI on S3C2416. I got SD card working with this patches
and with patches for GPIO card detection support by Marek Szyprowski.



From jekhor at gmail.com  Tue Jun 22 09:16:22 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 16:16:22 +0300
Subject: [PATCH 1/4] ARM: S3C24XX: Fix gpiolib support for ports K..M
In-Reply-To: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
References: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
Message-ID: <1277212585-25605-2-git-send-email-jekhor@gmail.com>

S3C2443 and S3C2416 has 12 GPIO banks (from A to M), increase
ARCH_NR_GPIOS for this architectures.

Also typo from previous commit has been fixed: CONFIG_CPU_S3C24XX
instead CONFIG_CPU_244X.

Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
---
 arch/arm/mach-s3c2410/include/mach/gpio.h |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
index b649bf2..f7f6b07 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -22,6 +22,8 @@
 
 #ifdef CONFIG_CPU_S3C244X
 #define ARCH_NR_GPIOS	(32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
+#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
+#define ARCH_NR_GPIOS	(32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA)
 #else
 #define ARCH_NR_GPIOS	(256 + CONFIG_S3C24XX_GPIO_EXTRA)
 #endif
@@ -30,8 +32,10 @@
 #include <mach/gpio-nrs.h>
 #include <mach/gpio-fns.h>
 
-#ifdef CONFIG_CPU_S3C24XX
-#define S3C_GPIO_END	(S3C2410_GPIO_BANKJ + 32)
+#ifdef CONFIG_CPU_S3C244X
+#define S3C_GPIO_END	(S3C2410_GPJ(0) + 32)
+#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
+#define S3C_GPIO_END	(S3C2410_GPM(0) + 32)
 #else
-#define S3C_GPIO_END	(S3C2410_GPIO_BANKH + 32)
+#define S3C_GPIO_END	(S3C2410_GPH(0) + 32)
 #endif
-- 
1.6.6.1



From jekhor at gmail.com  Tue Jun 22 09:16:23 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 16:16:23 +0300
Subject: [PATCH 2/4] ARM: S3C2416: Set name of the framebuffer device only if
	it present
In-Reply-To: <1277212585-25605-2-git-send-email-jekhor@gmail.com>
References: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
	<1277212585-25605-2-git-send-email-jekhor@gmail.com>
Message-ID: <1277212585-25605-3-git-send-email-jekhor@gmail.com>

Fix case when board doesn't have LCD connected and doesn't have
corresponding platform device compiled.

Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
---
 arch/arm/mach-s3c2416/s3c2416.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index 35dabcc..355ab62 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -90,7 +90,9 @@ int __init s3c2416_init(void)
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
 
+#ifdef CONFIG_S3C_DEV_FB
 	s3c_device_fb.name = "s3c2443-fb";
+#endif
 
 	return sysdev_register(&s3c2416_sysdev);
 }
-- 
1.6.6.1



From jekhor at gmail.com  Tue Jun 22 09:16:24 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 16:16:24 +0300
Subject: [PATCH 3/4] ARM: S3C2416: Add clock definition for HSMMC1
In-Reply-To: <1277212585-25605-3-git-send-email-jekhor@gmail.com>
References: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
	<1277212585-25605-2-git-send-email-jekhor@gmail.com>
	<1277212585-25605-3-git-send-email-jekhor@gmail.com>
Message-ID: <1277212585-25605-4-git-send-email-jekhor@gmail.com>

Define clock for hsmmc1 device and register it.

Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
---
 .../mach-s3c2410/include/mach/regs-s3c2443-clock.h |    1 +
 arch/arm/mach-s3c2416/clock.c                      |    9 +++++++++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
index 08ab9df..c073a5a 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
@@ -86,6 +86,7 @@
 #define S3C2443_HCLKCON_LCDC		(1<<9)
 #define S3C2443_HCLKCON_USBH		(1<<11)
 #define S3C2443_HCLKCON_USBD		(1<<12)
+#define S3C2416_HCLKCON_HSMMC0		(1<<15)
 #define S3C2443_HCLKCON_HSMMC		(1<<16)
 #define S3C2443_HCLKCON_CFC		(1<<17)
 #define S3C2443_HCLKCON_SSMC		(1<<18)
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 7ccf5a2..f11d131 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -93,6 +93,13 @@ static struct clksrc_clk hsmmc_mux[] = {
 	},
 };
 
+static struct clk hsmmc1_clk = {
+	.name		= "hsmmc",
+	.id		= 1,
+	.parent		= &clk_h,
+	.enable		= s3c2443_clkcon_enable_h,
+	.ctrlbit	= S3C2416_HCLKCON_HSMMC0,
+};
 
 static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
 {
@@ -130,6 +137,8 @@ void __init s3c2416_init_clocks(int xtal)
 	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 		s3c_register_clksrc(clksrcs[ptr], 1);
 
+	s3c24xx_register_clock(&hsmmc1_clk);
+
 	s3c_pwmclk_init();
 
 }
-- 
1.6.6.1



From jekhor at gmail.com  Tue Jun 22 09:16:25 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 16:16:25 +0300
Subject: [PATCH 4/4] ARM: S3C2416: Add platform helpers for setup SDHCI
In-Reply-To: <1277212585-25605-4-git-send-email-jekhor@gmail.com>
References: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
	<1277212585-25605-2-git-send-email-jekhor@gmail.com>
	<1277212585-25605-3-git-send-email-jekhor@gmail.com>
	<1277212585-25605-4-git-send-email-jekhor@gmail.com>
Message-ID: <1277212585-25605-5-git-send-email-jekhor@gmail.com>

Samsung S3C2416 has two SDHCI controllers compatible with other
Samsung's SoCs (S3C64XX, S5PC100 etc...).

Add required platform setup code that the devices can be used with
sdhci-s3c driver.

Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
---
 arch/arm/mach-s3c2416/Kconfig              |   23 ++++++++++
 arch/arm/mach-s3c2416/Makefile             |    5 ++
 arch/arm/mach-s3c2416/s3c2416.c            |    5 ++
 arch/arm/mach-s3c2416/setup-sdhci-gpio.c   |   60 +++++++++++++++++++++++++++
 arch/arm/mach-s3c2416/setup-sdhci.c        |   62 ++++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/sdhci.h |   34 +++++++++++++++
 6 files changed, 189 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s3c2416/setup-sdhci-gpio.c
 create mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c

diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
index eafb0ed..e055c7f 100644
--- a/arch/arm/mach-s3c2416/Kconfig
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -25,6 +25,17 @@ config S3C2416_DMA
 	help
 	  Internal config node for S3C2416 DMA support
 
+config S3C2416_SETUP_SDHCI
+	bool
+	select S3C2416_SETUP_SDHCI_GPIO
+	help
+	  Internal helper functions for S3C2416 based SDHCI systems
+
+config S3C2416_SETUP_SDHCI_GPIO
+	bool
+	help
+	  Common setup code for SDHCI gpio.
+
 menu "S3C2416 Machines"
 
 config MACH_SMDK2416
@@ -36,7 +47,19 @@ config MACH_SMDK2416
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_NAND
 	select S3C_DEV_USB_HOST
+	select S3C2416_SETUP_SDHCI
 	help
 	  Say Y here if you are using an SMDK2416
 
+config MACH_HANLIN_V3C
+	bool "Hanlin eReader V3C"
+	select CPU_S3C2416
+	select S3C_DEV_HSMMC
+	select S3C_DEV_HSMMC1
+	select S3C_DEV_NAND
+	select S3C_DEV_USB_HOST
+	select S3C2416_SETUP_SDHCI
+	help
+	  Say Y here if you are using an Jinke's Hanlin V3C eReader
+
 endmenu
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
index 6c12c7b..678e148 100644
--- a/arch/arm/mach-s3c2416/Makefile
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -14,6 +14,11 @@ obj-$(CONFIG_CPU_S3C2416)	+= irq.o
 
 #obj-$(CONFIG_S3C2416_DMA)	+= dma.o
 
+# Device setup
+obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
+obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
+
 # Machine support
 
 obj-$(CONFIG_MACH_SMDK2416)	+= mach-smdk2416.o
+obj-$(CONFIG_MACH_HANLIN_V3C)	+= mach-v3c.o
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index 355ab62..06eacf8 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -53,6 +53,7 @@
 #include <plat/s3c2416.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/sdhci.h>
 
 #include <plat/iic-core.h>
 
@@ -115,6 +116,10 @@ void __init s3c2416_map_io(void)
 	s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
 	s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
 
+	/* initialize device information early */
+	s3c2416_default_sdhci0();
+	s3c2416_default_sdhci1();
+
 	iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
 }
 
diff --git a/arch/arm/mach-s3c2416/setup-sdhci-gpio.c b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
new file mode 100644
index 0000000..ebdab15
--- /dev/null
+++ b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
@@ -0,0 +1,60 @@
+/* linux/arch/arm/plat-s3c2416/setup-sdhci-gpio.c
+ *
+ * Copyright 2010 Promwad Innovation Company
+ *	Yauhen Kharuzhy <yauhen.kharuzhy at promwad.com>
+ *
+ * S3C2416 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * Based on mach-s3c64xx/setup-sdhci-gpio.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/gpio.h>
+#include <mach/regs-gpio.h>
+#include <plat/gpio-cfg.h>
+
+/* Note: hsmmc1 and hsmmc0 are swapped versus datasheet */
+
+void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+	unsigned int end;
+
+	end = S3C2410_GPE(7 + width);
+
+	/* Set all the necessary GPE pins to special-function 0 */
+	for (gpio = S3C2410_GPE(5); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+}
+
+void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+	unsigned int end;
+
+	end = S3C2410_GPL(0 + width);
+
+	/* Set all the necessary GPG pins to special-function 0 */
+	for (gpio = S3C2410_GPL(0); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	s3c_gpio_cfgpin(S3C2410_GPL(8), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S3C2410_GPL(8), S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(S3C2410_GPL(9), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S3C2410_GPL(9), S3C_GPIO_PULL_NONE);
+}
+
+
diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
new file mode 100644
index 0000000..345ddd1
--- /dev/null
+++ b/arch/arm/mach-s3c2416/setup-sdhci.c
@@ -0,0 +1,62 @@
+/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
+ *
+ * Copyright 2010 Promwad Innovation Company
+ *	Yauhen Kharuzhy <yauhen.kharuzhy at promwad.com>
+ *
+ * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * Based on mach-s3c64xx/setup-sdhci.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *s3c2416_hsmmc_clksrcs[4] = {
+	[0] = "hsmmc",
+	[1] = "hsmmc",
+	[2] = "hsmmc-if",
+	/* [3] = "48m", - note not successfully used yet */
+};
+
+void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
+				  void __iomem *r,
+				  struct mmc_ios *ios,
+				  struct mmc_card *card)
+{
+	u32 ctrl2, ctrl3;
+
+	ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+		  S3C_SDHCI_CTRL2_ENFBCLKRX |
+		  S3C_SDHCI_CTRL2_DFCNT_NONE |
+		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+	if (ios->clock < 25 * 1000000)
+		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+			 S3C_SDHCI_CTRL3_FCSEL2 |
+			 S3C_SDHCI_CTRL3_FCSEL1 |
+			 S3C_SDHCI_CTRL3_FCSEL0);
+	else
+		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+
+	writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+	writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
+
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 13f9fb2..d408140 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -78,6 +78,8 @@ extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 
 /* S3C6400 SDHCI setup */
 
@@ -270,6 +272,38 @@ static inline void s5pv210_default_sdhci1(void) { }
 static inline void s5pv210_default_sdhci2(void) { }
 #endif /* CONFIG_S5PC100_SETUP_SDHCI */
 
+/* S3C2416 SDHCI setup */
+#ifdef CONFIG_S3C2416_SETUP_SDHCI
+extern char *s3c2416_hsmmc_clksrcs[4];
+
+extern void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
+					   void __iomem *r,
+					   struct mmc_ios *ios,
+					   struct mmc_card *card);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static inline void s3c2416_default_sdhci0(void)
+{
+	s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
+	s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
+	s3c_hsmmc0_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c2416_default_sdhci0(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC */
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static inline void s3c2416_default_sdhci1(void)
+{
+	s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
+	s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
+	s3c_hsmmc1_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c2416_default_sdhci1(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+
+#endif /* CONFIG_S3C2416_SETUP_SDHCI */
 
 
 
-- 
1.6.6.1



From mcuelenaere at gmail.com  Tue Jun 22 09:19:28 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Tue, 22 Jun 2010 15:19:28 +0200
Subject: [PATCH 4/4] ARM: S3C2416: Add platform helpers for setup SDHCI
In-Reply-To: <1277212585-25605-5-git-send-email-jekhor@gmail.com>
References: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
	<1277212585-25605-2-git-send-email-jekhor@gmail.com>
	<1277212585-25605-3-git-send-email-jekhor@gmail.com>
	<1277212585-25605-4-git-send-email-jekhor@gmail.com>
	<1277212585-25605-5-git-send-email-jekhor@gmail.com>
Message-ID: <4C20B860.80308@gmail.com>

Op 22-06-10 15:16, Yauhen Kharuzhy schreef:
> Samsung S3C2416 has two SDHCI controllers compatible with other
> Samsung's SoCs (S3C64XX, S5PC100 etc...).
>
> Add required platform setup code that the devices can be used with
> sdhci-s3c driver.
>
> Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
> ---
>  arch/arm/mach-s3c2416/Kconfig              |   23 ++++++++++
>  arch/arm/mach-s3c2416/Makefile             |    5 ++
>  arch/arm/mach-s3c2416/s3c2416.c            |    5 ++
>  arch/arm/mach-s3c2416/setup-sdhci-gpio.c   |   60 +++++++++++++++++++++++++++
>  arch/arm/mach-s3c2416/setup-sdhci.c        |   62 ++++++++++++++++++++++++++++
>  arch/arm/plat-samsung/include/plat/sdhci.h |   34 +++++++++++++++
>  6 files changed, 189 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-s3c2416/setup-sdhci-gpio.c
>  create mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c
>
> diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
> index eafb0ed..e055c7f 100644
> --- a/arch/arm/mach-s3c2416/Kconfig
> +++ b/arch/arm/mach-s3c2416/Kconfig
> @@ -25,6 +25,17 @@ config S3C2416_DMA
>  	help
>  	  Internal config node for S3C2416 DMA support
>  
> +config S3C2416_SETUP_SDHCI
> +	bool
> +	select S3C2416_SETUP_SDHCI_GPIO
> +	help
> +	  Internal helper functions for S3C2416 based SDHCI systems
> +
> +config S3C2416_SETUP_SDHCI_GPIO
> +	bool
> +	help
> +	  Common setup code for SDHCI gpio.
> +
>  menu "S3C2416 Machines"
>  
>  config MACH_SMDK2416
> @@ -36,7 +47,19 @@ config MACH_SMDK2416
>  	select S3C_DEV_HSMMC1
>  	select S3C_DEV_NAND
>  	select S3C_DEV_USB_HOST
> +	select S3C2416_SETUP_SDHCI
>  	help
>  	  Say Y here if you are using an SMDK2416
>  
> +config MACH_HANLIN_V3C
> +	bool "Hanlin eReader V3C"
> +	select CPU_S3C2416
> +	select S3C_DEV_HSMMC
> +	select S3C_DEV_HSMMC1
> +	select S3C_DEV_NAND
> +	select S3C_DEV_USB_HOST
> +	select S3C2416_SETUP_SDHCI
> +	help
> +	  Say Y here if you are using an Jinke's Hanlin V3C eReader
> +
>   

This seems to be unrelated to the patch?

>  endmenu
> diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
> index 6c12c7b..678e148 100644
> --- a/arch/arm/mach-s3c2416/Makefile
> +++ b/arch/arm/mach-s3c2416/Makefile
> @@ -14,6 +14,11 @@ obj-$(CONFIG_CPU_S3C2416)	+= irq.o
>  
>  #obj-$(CONFIG_S3C2416_DMA)	+= dma.o
>  
> +# Device setup
> +obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
> +obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
> +
>  # Machine support
>  
>  obj-$(CONFIG_MACH_SMDK2416)	+= mach-smdk2416.o
> +obj-$(CONFIG_MACH_HANLIN_V3C)	+= mach-v3c.o
> diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
> index 355ab62..06eacf8 100644
> --- a/arch/arm/mach-s3c2416/s3c2416.c
> +++ b/arch/arm/mach-s3c2416/s3c2416.c
> @@ -53,6 +53,7 @@
>  #include <plat/s3c2416.h>
>  #include <plat/devs.h>
>  #include <plat/cpu.h>
> +#include <plat/sdhci.h>
>  
>  #include <plat/iic-core.h>
>  
> @@ -115,6 +116,10 @@ void __init s3c2416_map_io(void)
>  	s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
>  	s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
>  
> +	/* initialize device information early */
> +	s3c2416_default_sdhci0();
> +	s3c2416_default_sdhci1();
> +
>  	iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
>  }
>  
> diff --git a/arch/arm/mach-s3c2416/setup-sdhci-gpio.c b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
> new file mode 100644
> index 0000000..ebdab15
> --- /dev/null
> +++ b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
> @@ -0,0 +1,60 @@
> +/* linux/arch/arm/plat-s3c2416/setup-sdhci-gpio.c
> + *
> + * Copyright 2010 Promwad Innovation Company
> + *	Yauhen Kharuzhy <yauhen.kharuzhy at promwad.com>
> + *
> + * S3C2416 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
> + *
> + * Based on mach-s3c64xx/setup-sdhci-gpio.c
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#include <mach/gpio.h>
> +#include <mach/regs-gpio.h>
> +#include <plat/gpio-cfg.h>
> +
> +/* Note: hsmmc1 and hsmmc0 are swapped versus datasheet */
> +
> +void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
> +{
> +	unsigned int gpio;
> +	unsigned int end;
> +
> +	end = S3C2410_GPE(7 + width);
> +
> +	/* Set all the necessary GPE pins to special-function 0 */
> +	for (gpio = S3C2410_GPE(5); gpio < end; gpio++) {
> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> +	}
> +}
> +
> +void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
> +{
> +	unsigned int gpio;
> +	unsigned int end;
> +
> +	end = S3C2410_GPL(0 + width);
> +
> +	/* Set all the necessary GPG pins to special-function 0 */
> +	for (gpio = S3C2410_GPL(0); gpio < end; gpio++) {
> +		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> +	}
> +
> +	s3c_gpio_cfgpin(S3C2410_GPL(8), S3C_GPIO_SFN(2));
> +	s3c_gpio_setpull(S3C2410_GPL(8), S3C_GPIO_PULL_NONE);
> +	s3c_gpio_cfgpin(S3C2410_GPL(9), S3C_GPIO_SFN(2));
> +	s3c_gpio_setpull(S3C2410_GPL(9), S3C_GPIO_PULL_NONE);
> +}
> +
> +
> diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
> new file mode 100644
> index 0000000..345ddd1
> --- /dev/null
> +++ b/arch/arm/mach-s3c2416/setup-sdhci.c
> @@ -0,0 +1,62 @@
> +/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
> + *
> + * Copyright 2010 Promwad Innovation Company
> + *	Yauhen Kharuzhy <yauhen.kharuzhy at promwad.com>
> + *
> + * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
> + *
> + * Based on mach-s3c64xx/setup-sdhci.c
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#include <linux/mmc/card.h>
> +#include <linux/mmc/host.h>
> +
> +#include <plat/regs-sdhci.h>
> +#include <plat/sdhci.h>
> +
> +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
> +
> +char *s3c2416_hsmmc_clksrcs[4] = {
> +	[0] = "hsmmc",
> +	[1] = "hsmmc",
> +	[2] = "hsmmc-if",
> +	/* [3] = "48m", - note not successfully used yet */
> +};
> +
> +void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
> +				  void __iomem *r,
> +				  struct mmc_ios *ios,
> +				  struct mmc_card *card)
> +{
> +	u32 ctrl2, ctrl3;
> +
> +	ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
> +	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
> +	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
> +		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
> +		  S3C_SDHCI_CTRL2_ENFBCLKRX |
> +		  S3C_SDHCI_CTRL2_DFCNT_NONE |
> +		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
> +
> +	if (ios->clock < 25 * 1000000)
> +		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
> +			 S3C_SDHCI_CTRL3_FCSEL2 |
> +			 S3C_SDHCI_CTRL3_FCSEL1 |
> +			 S3C_SDHCI_CTRL3_FCSEL0);
> +	else
> +		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
> +
> +	writel(ctrl2, r + S3C_SDHCI_CONTROL2);
> +	writel(ctrl3, r + S3C_SDHCI_CONTROL3);
> +}
> +
> diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
> index 13f9fb2..d408140 100644
> --- a/arch/arm/plat-samsung/include/plat/sdhci.h
> +++ b/arch/arm/plat-samsung/include/plat/sdhci.h
> @@ -78,6 +78,8 @@ extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
>  extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
>  extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
>  extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
> +extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
> +extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
>  
>  /* S3C6400 SDHCI setup */
>  
> @@ -270,6 +272,38 @@ static inline void s5pv210_default_sdhci1(void) { }
>  static inline void s5pv210_default_sdhci2(void) { }
>  #endif /* CONFIG_S5PC100_SETUP_SDHCI */
>  
> +/* S3C2416 SDHCI setup */
> +#ifdef CONFIG_S3C2416_SETUP_SDHCI
> +extern char *s3c2416_hsmmc_clksrcs[4];
> +
> +extern void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
> +					   void __iomem *r,
> +					   struct mmc_ios *ios,
> +					   struct mmc_card *card);
> +
> +#ifdef CONFIG_S3C_DEV_HSMMC
> +static inline void s3c2416_default_sdhci0(void)
> +{
> +	s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
> +	s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
> +	s3c_hsmmc0_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
> +}
> +#else
> +static inline void s3c2416_default_sdhci0(void) { }
> +#endif /* CONFIG_S3C_DEV_HSMMC */
> +
> +#ifdef CONFIG_S3C_DEV_HSMMC1
> +static inline void s3c2416_default_sdhci1(void)
> +{
> +	s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
> +	s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
> +	s3c_hsmmc1_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
> +}
> +#else
> +static inline void s3c2416_default_sdhci1(void) { }
> +#endif /* CONFIG_S3C_DEV_HSMMC1 */
> +
> +#endif /* CONFIG_S3C2416_SETUP_SDHCI */
>  
>  
>  
>   


-- 
Maurus Cuelenaere



From tony at atomide.com  Tue Jun 22 09:20:38 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 22 Jun 2010 16:20:38 +0300
Subject: [PATCH 2/2] arm: Make VFPv3 usable on ARMv6
In-Reply-To: <1277211592.29532.20.camel@e102109-lin.cambridge.arm.com>
References: <20100621135125.24299.91290.stgit@baageli.muru.com>
	<1277211592.29532.20.camel@e102109-lin.cambridge.arm.com>
Message-ID: <20100622132037.GV12255@atomide.com>

* Catalin Marinas <catalin.marinas at arm.com> [100622 15:53]:
> On Mon, 2010-06-21 at 14:51 +0100, Tony Lindgren wrote:
> > diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
> > index 315a540..19ba626 100644
> > --- a/arch/arm/vfp/vfpmodule.c
> > +++ b/arch/arm/vfp/vfpmodule.c
> > @@ -549,10 +549,14 @@ static int __init vfp_init(void)
> >                 /*
> >                  * Check for the presence of the Advanced SIMD
> >                  * load/store instructions, integer and single
> > -                * precision floating point operations.
> > +                * precision floating point operations. Only check
> > +                * for NEON if the hardware has TLS register as the
> > +                * MVFR registers got added in ARM1136 r1p0 with TLS.
> >                  */
> > -               if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
> > -                       elf_hwcap |= HWCAP_NEON;
> > +               if (elf_hwcap & HWCAP_TLS) {
> > +                       if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
> > +                               elf_hwcap |= HWCAP_NEON;
> > +               }
> 
> MVFR should be available with the new CPU id format:
> 
> 	((read_cpuid_id() & 0x000f0000) == 0x000f0000)
> 
> I think that would be a cleaner test than relying on the TLS presence.

OK, thanks that's better. Will update accordingly and repost.

Tony


From jason77.wang at gmail.com  Tue Jun 22 09:08:43 2010
From: jason77.wang at gmail.com (jason)
Date: Tue, 22 Jun 2010 21:08:43 +0800
Subject: [PATCH 1/2] mxc: add common debug board for 3-stack platforms
In-Reply-To: <20100621071148.GF12115@pengutronix.de>
References: <1276352707-8199-1-git-send-email-jason77.wang@gmail.com>
	<1276352707-8199-2-git-send-email-jason77.wang@gmail.com>
	<20100616065540.GI20799@pengutronix.de>
	<4C1B7D6A.4010301@gmail.com>
	<20100621071148.GF12115@pengutronix.de>
Message-ID: <4C20B5DB.9040007@gmail.com>

Sascha Hauer wrote:
> On Fri, Jun 18, 2010 at 10:06:34PM +0800, jason wrote:
>   
>> Sascha Hauer wrote:
>>     
>>> On Sat, Jun 12, 2010 at 10:25:06PM +0800, Jason Wang wrote:
>>>   
>>>       
>>>> The debug board is little different for all mxc 3-stack(PDK)
>>>> platforms, it is possible here to add a common implementation to
>>>> support this board.
>>>>     
>>>>         
>>> Two small things left:
>>>
>>> Could you change the name cpld_debugboard.c to something like
>>> 3ds_debugboard.c? That we are talking about the 3ds is much more
>>> interesting than that there's a cpld on the board.
>>>
>>> Also, I really prefer having no extra header file for the debug board.
>>> All information in this header file is only interesting in this single C
>>> file.
>>>
>>> Sascha
>>>
>>>
>>>   
>>>       
>> Hi Sascha,
>>
>> About the header file, most contents can be moved to c file,
>> but there are two declarations:
>>
>> extern struct platform_device smsc_lan9217_device;
>>     
>
> What do you need this one for?
>
>   
Originally i want to register lan9217 in the board-mxNN-3ds.c, just like:
if (!mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
platform_device_register(&smsc_lan9217_device);

Of course, i can give it a wrapper like mxc_expio_lan_init();

Please see my next version.

Thanks,
Jason.
>> int __init mxc_expio_init(u32 base, u32 p_irq);
>>     
>
> You'll definitely need this one of course.
>
>   
>> which will be used by board_mxNN_3ds.c, should i move them to mach/common.h and
>> drop 3ds_debugboard.h or keep them in 3ds_debugboard.h?
>>     
>
> Keep them in 3ds_debugboard.h. This way we can easily grep for all users
> of the 3ds debug board code.
>
> Sascha
>
>
>   



From anarsoul at gmail.com  Tue Jun 22 09:40:13 2010
From: anarsoul at gmail.com (Vasily Khoruzhick)
Date: Tue, 22 Jun 2010 16:40:13 +0300
Subject: [PATCH 1/4] ARM: S3C24XX: Fix gpiolib support for ports K..M
In-Reply-To: <1277212585-25605-2-git-send-email-jekhor@gmail.com>
References: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
	<1277212585-25605-2-git-send-email-jekhor@gmail.com>
Message-ID: <201006221640.26196.anarsoul@gmail.com>

? ????????? ?? 22 ???? 2010 16:16:22 ????? Yauhen Kharuzhy ???????:
> S3C2443 and S3C2416 has 12 GPIO banks (from A to M), increase
> ARCH_NR_GPIOS for this architectures.
> 
> Also typo from previous commit has been fixed: CONFIG_CPU_S3C24XX
> instead CONFIG_CPU_244X.
> 
> Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>

Tested-by: Vasily Khoruzhick <anarsoul at gmail.com>

> ---
>  arch/arm/mach-s3c2410/include/mach/gpio.h |   10 +++++++---
>  1 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h
> b/arch/arm/mach-s3c2410/include/mach/gpio.h index b649bf2..f7f6b07 100644
> --- a/arch/arm/mach-s3c2410/include/mach/gpio.h
> +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
> @@ -22,6 +22,8 @@
> 
>  #ifdef CONFIG_CPU_S3C244X
>  #define ARCH_NR_GPIOS	(32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
> +#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
> +#define ARCH_NR_GPIOS	(32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA)
>  #else
>  #define ARCH_NR_GPIOS	(256 + CONFIG_S3C24XX_GPIO_EXTRA)
>  #endif
> @@ -30,8 +32,10 @@
>  #include <mach/gpio-nrs.h>
>  #include <mach/gpio-fns.h>
> 
> -#ifdef CONFIG_CPU_S3C24XX
> -#define S3C_GPIO_END	(S3C2410_GPIO_BANKJ + 32)
> +#ifdef CONFIG_CPU_S3C244X
> +#define S3C_GPIO_END	(S3C2410_GPJ(0) + 32)
> +#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
> +#define S3C_GPIO_END	(S3C2410_GPM(0) + 32)
>  #else
> -#define S3C_GPIO_END	(S3C2410_GPIO_BANKH + 32)
> +#define S3C_GPIO_END	(S3C2410_GPH(0) + 32)
>  #endif
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From dwalker at codeaurora.org  Tue Jun 22 09:52:59 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Tue, 22 Jun 2010 06:52:59 -0700
Subject: [PATCH] arm: kconfig: add HAVE_SMP
Message-ID: <1277214779-14227-1-git-send-email-dwalker@codeaurora.org>

This replaces the board listing for SMP with a HAVE_SMP
config option which can be selected when the sub-architecture
is selected.

Signed-off-by: Daniel Walker <dwalker at codeaurora.org>
---
 arch/arm/Kconfig               |    8 +++++---
 arch/arm/mach-realview/Kconfig |    4 ++++
 arch/arm/mach-vexpress/Kconfig |    1 +
 arch/arm/plat-omap/Kconfig     |    1 +
 4 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..4cf10d5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -748,6 +748,7 @@ config ARCH_U8500
 	select GENERIC_CLOCKEVENTS
 	select COMMON_CLKDEV
 	select ARCH_REQUIRE_GPIOLIB
+	select HAVE_SMP
 	help
 	  Support for ST-Ericsson's Ux500 architecture
 
@@ -1095,11 +1096,12 @@ menu "Kernel Features"
 
 source "kernel/time/Kconfig"
 
+config HAVE_SMP
+	bool
+
 config SMP
 	bool "Symmetric Multi-Processing (EXPERIMENTAL)"
-	depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
-		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
-		 ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
+	depends on EXPERIMENTAL && HAVE_SMP
 	depends on GENERIC_CLOCKEVENTS
 	select USE_GENERIC_SMP_HELPERS
 	select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index ee5e392..fcfdfb7 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -11,6 +11,7 @@ config REALVIEW_EB_A9MP
 	bool "Support Multicore Cortex-A9"
 	depends on MACH_REALVIEW_EB
 	select CPU_V7
+	select HAVE_SMP
 	help
 	  Enable support for the Cortex-A9MPCore tile on the Realview platform.
 
@@ -18,6 +19,7 @@ config REALVIEW_EB_ARM11MP
 	bool "Support ARM11MPCore tile"
 	depends on MACH_REALVIEW_EB
 	select CPU_V6
+	select HAVE_SMP
 	help
 	  Enable support for the ARM11MPCore tile on the Realview platform.
 
@@ -35,6 +37,7 @@ config MACH_REALVIEW_PB11MP
 	select CPU_V6
 	select ARM_GIC
 	select HAVE_PATA_PLATFORM
+	select HAVE_SMP
 	help
 	  Include support for the ARM(R) RealView MPCore Platform Baseboard.
 	  PB11MPCore is a platform with an on-board ARM11MPCore and has
@@ -70,6 +73,7 @@ config MACH_REALVIEW_PBX
 	bool "Support RealView/PBX platform"
 	select ARM_GIC
 	select HAVE_PATA_PLATFORM
+	select HAVE_SMP
 	select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
 	select ZONE_DMA if SPARSEMEM
 	help
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 3f19b66..a20fa2f 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -5,5 +5,6 @@ config ARCH_VEXPRESS_CA9X4
 	bool "Versatile Express Cortex-A9x4 tile"
 	select CPU_V7
 	select ARM_GIC
+	select HAVE_SMP
 
 endmenu
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 78b49a6..6a2636a 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -38,6 +38,7 @@ config ARCH_OMAP4
 	depends on ARCH_OMAP2PLUS
 	select CPU_V7
 	select ARM_GIC
+	select HAVE_SMP
 
 endchoice
 
-- 
1.7.0.4



From jekhor at gmail.com  Tue Jun 22 09:54:16 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 16:54:16 +0300
Subject: Add support of SD/MMC card detection on SMDK2416 board
Message-ID: <1277214857-817-1-git-send-email-jekhor@gmail.com>

This patch adds card detection setup to SDHCI platform data on SMDK2416.
It was not tested because I don't have access to SMDK2416 board anymore,
but I tested similar patch on another board.


Note: it depends on patches:

ARM: S3C24XX: Fix gpiolib support for ports K..M
ARM: S3C2416: Add clock definition for HSMMC1
ARM: S3C2416: Add platform helpers for setup SDHCI
Samsung: sdhci-s3c: add support for new card detection methods
sdhci-s3c: add support for the non standard minimal clock value
sdhci-s3c: add support for new card detection methods




From jekhor at gmail.com  Tue Jun 22 09:54:17 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 16:54:17 +0300
Subject: [PATCH] ARM: S3C2416: Add support of SD/MMC card detect on SMDK2416
In-Reply-To: <1277214857-817-1-git-send-email-jekhor@gmail.com>
References: <1277214857-817-1-git-send-email-jekhor@gmail.com>
Message-ID: <1277214857-817-2-git-send-email-jekhor@gmail.com>

Enable card detect by GPIO pin on hsmmc1 device (SD0 on SMDK2416
board) and enable card polling on hsmmc0 (SD1).

Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
---
 arch/arm/mach-s3c2416/mach-smdk2416.c |   16 ++++++++++++++++
 1 files changed, 16 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
index 5fc3f67..14c2a2e 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -46,6 +46,7 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/nand.h>
+#include <plat/sdhci.h>
 
 #include <plat/regs-fb-v4.h>
 #include <plat/fb.h>
@@ -159,6 +160,18 @@ static struct s3c_fb_platdata smdk2416_fb_platdata = {
 	.vidcon1	= VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
 };
 
+static struct s3c_sdhci_platdata smdk2416_hsmmc1_pdata __initdata = {
+	.max_width		= 4,
+	.cd_type		= S3C_SDHCI_CD_GPIO,
+	.ext_cd_gpio		= S3C2410_GPF(1),
+	.ext_cd_gpio_invert	= 1,
+};
+
+static struct s3c_sdhci_platdata smdk2416_hsmmc0_pdata __initdata = {
+	.max_width		= 4,
+	.cd_type		= S3C_SDHCI_CD_NONE,
+};
+
 static struct platform_device *smdk2416_devices[] __initdata = {
 	&s3c_device_fb,
 	&s3c_device_wdt,
@@ -180,6 +193,9 @@ static void __init smdk2416_machine_init(void)
 	s3c_i2c0_set_platdata(NULL);
 	s3c_fb_set_platdata(&smdk2416_fb_platdata);
 
+	s3c_sdhci0_set_platdata(&smdk2416_hsmmc0_pdata);
+	s3c_sdhci1_set_platdata(&smdk2416_hsmmc1_pdata);
+
 	gpio_request(S3C2410_GPB(4), "USBHost Power");
 	gpio_direction_output(S3C2410_GPB(4), 1);
 
-- 
1.6.6.1



From jekhor at gmail.com  Tue Jun 22 10:05:37 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 17:05:37 +0300
Subject: [PATCH 4/4] ARM: S3C2416: Add platform helpers for setup SDHCI
In-Reply-To: <4C20B860.80308@gmail.com>
References: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
	<1277212585-25605-2-git-send-email-jekhor@gmail.com>
	<1277212585-25605-3-git-send-email-jekhor@gmail.com>
	<1277212585-25605-4-git-send-email-jekhor@gmail.com>
	<1277212585-25605-5-git-send-email-jekhor@gmail.com>
	<4C20B860.80308@gmail.com>
Message-ID: <20100622140537.GA3669@jeknote.loshitsa1.net>

On Tue, Jun 22, 2010 at 03:19:28PM +0200, Maurus Cuelenaere wrote:
> Op 22-06-10 15:16, Yauhen Kharuzhy schreef:
> > Samsung S3C2416 has two SDHCI controllers compatible with other
> > Samsung's SoCs (S3C64XX, S5PC100 etc...).
> >
> > Add required platform setup code that the devices can be used with
> > sdhci-s3c driver.
> >
> > Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
> > ---
> >  arch/arm/mach-s3c2416/Kconfig              |   23 ++++++++++
> >  arch/arm/mach-s3c2416/Makefile             |    5 ++
> >  arch/arm/mach-s3c2416/s3c2416.c            |    5 ++
> >  arch/arm/mach-s3c2416/setup-sdhci-gpio.c   |   60 +++++++++++++++++++++++++++
> >  arch/arm/mach-s3c2416/setup-sdhci.c        |   62 ++++++++++++++++++++++++++++
> >  arch/arm/plat-samsung/include/plat/sdhci.h |   34 +++++++++++++++
> >  6 files changed, 189 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/mach-s3c2416/setup-sdhci-gpio.c
> >  create mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c
> >
> > diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
> > index eafb0ed..e055c7f 100644
> > --- a/arch/arm/mach-s3c2416/Kconfig
> > +++ b/arch/arm/mach-s3c2416/Kconfig
> > @@ -25,6 +25,17 @@ config S3C2416_DMA
> >  	help
> >  	  Internal config node for S3C2416 DMA support
> >  
> > +config S3C2416_SETUP_SDHCI
> > +	bool
> > +	select S3C2416_SETUP_SDHCI_GPIO
> > +	help
> > +	  Internal helper functions for S3C2416 based SDHCI systems
> > +
> > +config S3C2416_SETUP_SDHCI_GPIO
> > +	bool
> > +	help
> > +	  Common setup code for SDHCI gpio.
> > +
> >  menu "S3C2416 Machines"
> >  
> >  config MACH_SMDK2416
> > @@ -36,7 +47,19 @@ config MACH_SMDK2416
> >  	select S3C_DEV_HSMMC1
> >  	select S3C_DEV_NAND
> >  	select S3C_DEV_USB_HOST
> > +	select S3C2416_SETUP_SDHCI
> >  	help
> >  	  Say Y here if you are using an SMDK2416
> >  
> > +config MACH_HANLIN_V3C
> > +	bool "Hanlin eReader V3C"
> > +	select CPU_S3C2416
> > +	select S3C_DEV_HSMMC
> > +	select S3C_DEV_HSMMC1
> > +	select S3C_DEV_NAND
> > +	select S3C_DEV_USB_HOST
> > +	select S3C2416_SETUP_SDHCI
> > +	help
> > +	  Say Y here if you are using an Jinke's Hanlin V3C eReader
> > +
> >   
> 
> This seems to be unrelated to the patch?
I am sorry, will resend.
> 
> >  endmenu

-- 
Yauhen Kharuzhy		jekhor _at_ gmail.com
			JID: jek at jabber.ru

A: No
Q: Should I quote below my post?


From jekhor at gmail.com  Tue Jun 22 10:19:40 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 17:19:40 +0300
Subject: [PATCH 4/4] ARM: S3C2416: Add platform helpers for setup SDHCI
In-Reply-To: <AANLkTimUijwXx5UozqVZiJ8BBDysnxd5nQz8P5d1slRC@mail.gmail.com>
References: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
	<1277212585-25605-2-git-send-email-jekhor@gmail.com>
	<1277212585-25605-3-git-send-email-jekhor@gmail.com>
	<1277212585-25605-4-git-send-email-jekhor@gmail.com>
	<1277212585-25605-5-git-send-email-jekhor@gmail.com>
	<AANLkTimUijwXx5UozqVZiJ8BBDysnxd5nQz8P5d1slRC@mail.gmail.com>
Message-ID: <20100622141940.GB3669@jeknote.loshitsa1.net>

On Tue, Jun 22, 2010 at 04:45:18PM +0300, Darius Augulis wrote:
> On Tue, Jun 22, 2010 at 4:16 PM, Yauhen Kharuzhy <jekhor at gmail.com> wrote:
> 
> > Samsung S3C2416 has two SDHCI controllers compatible with other
> > Samsung's SoCs (S3C64XX, S5PC100 etc...).
> >
> > Add required platform setup code that the devices can be used with
> > sdhci-s3c driver.
> >
> > Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
> > ---
> >  arch/arm/mach-s3c2416/Kconfig              |   23 ++++++++++
> >  arch/arm/mach-s3c2416/Makefile             |    5 ++
> >  arch/arm/mach-s3c2416/s3c2416.c            |    5 ++
> >  arch/arm/mach-s3c2416/setup-sdhci-gpio.c   |   60
> > +++++++++++++++++++++++++++
> >  arch/arm/mach-s3c2416/setup-sdhci.c        |   62
> > ++++++++++++++++++++++++++++
> >  arch/arm/plat-samsung/include/plat/sdhci.h |   34 +++++++++++++++
> >  6 files changed, 189 insertions(+), 0 deletions(-)
> >  create mode 100644 arch/arm/mach-s3c2416/setup-sdhci-gpio.c
> >  create mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c
> >
> > diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
> > index eafb0ed..e055c7f 100644
> > --- a/arch/arm/mach-s3c2416/Kconfig
> > +++ b/arch/arm/mach-s3c2416/Kconfig
> > @@ -25,6 +25,17 @@ config S3C2416_DMA
> >        help
> >          Internal config node for S3C2416 DMA support
> >
> > +config S3C2416_SETUP_SDHCI
> > +       bool
> > +       select S3C2416_SETUP_SDHCI_GPIO
> > +       help
> > +         Internal helper functions for S3C2416 based SDHCI systems
> > +
> > +config S3C2416_SETUP_SDHCI_GPIO
> > +       bool
> > +       help
> > +         Common setup code for SDHCI gpio.
> > +
> >  menu "S3C2416 Machines"
> >
> >  config MACH_SMDK2416
> > @@ -36,7 +47,19 @@ config MACH_SMDK2416
> >        select S3C_DEV_HSMMC1
> >        select S3C_DEV_NAND
> >        select S3C_DEV_USB_HOST
> > +       select S3C2416_SETUP_SDHCI
> >        help
> >          Say Y here if you are using an SMDK2416
> >
> > +config MACH_HANLIN_V3C
> > +       bool "Hanlin eReader V3C"
> > +       select CPU_S3C2416
> > +       select S3C_DEV_HSMMC
> > +       select S3C_DEV_HSMMC1
> > +       select S3C_DEV_NAND
> > +       select S3C_DEV_USB_HOST
> > +       select S3C2416_SETUP_SDHCI
> > +       help
> > +         Say Y here if you are using an Jinke's Hanlin V3C eReader
> > +
> >  endmenu
> > diff --git a/arch/arm/mach-s3c2416/Makefile
> > b/arch/arm/mach-s3c2416/Makefile
> > index 6c12c7b..678e148 100644
> > --- a/arch/arm/mach-s3c2416/Makefile
> > +++ b/arch/arm/mach-s3c2416/Makefile
> > @@ -14,6 +14,11 @@ obj-$(CONFIG_CPU_S3C2416)    += irq.o
> >
> >  #obj-$(CONFIG_S3C2416_DMA)     += dma.o
> >
> > +# Device setup
> > +obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
> > +obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
> > +
> >  # Machine support
> >
> >  obj-$(CONFIG_MACH_SMDK2416)    += mach-smdk2416.o
> > +obj-$(CONFIG_MACH_HANLIN_V3C)  += mach-v3c.o
> > diff --git a/arch/arm/mach-s3c2416/s3c2416.c
> > b/arch/arm/mach-s3c2416/s3c2416.c
> > index 355ab62..06eacf8 100644
> > --- a/arch/arm/mach-s3c2416/s3c2416.c
> > +++ b/arch/arm/mach-s3c2416/s3c2416.c
> > @@ -53,6 +53,7 @@
> >  #include <plat/s3c2416.h>
> >  #include <plat/devs.h>
> >  #include <plat/cpu.h>
> > +#include <plat/sdhci.h>
> >
> >  #include <plat/iic-core.h>
> >
> > @@ -115,6 +116,10 @@ void __init s3c2416_map_io(void)
> >        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
> >        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
> >
> > +       /* initialize device information early */
> > +       s3c2416_default_sdhci0();
> > +       s3c2416_default_sdhci1();
> > +
> >        iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
> >  }
> >
> > diff --git a/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
> > b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
> > new file mode 100644
> > index 0000000..ebdab15
> > --- /dev/null
> > +++ b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
> > @@ -0,0 +1,60 @@
> > +/* linux/arch/arm/plat-s3c2416/setup-sdhci-gpio.c
> > + *
> > + * Copyright 2010 Promwad Innovation Company
> > + *     Yauhen Kharuzhy <yauhen.kharuzhy at promwad.com>
> > + *
> > + * S3C2416 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
> > + *
> > + * Based on mach-s3c64xx/setup-sdhci-gpio.c
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > +*/
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/types.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/io.h>
> > +
> > +#include <mach/gpio.h>
> > +#include <mach/regs-gpio.h>
> > +#include <plat/gpio-cfg.h>
> > +
> > +/* Note: hsmmc1 and hsmmc0 are swapped versus datasheet */
> >
> 
> would be nice to provide more accurate link to information source (document
> version, page).
> And there is a bit tricky place: clock ids are swapped and names of helper
> functions are not.
> So, it's not clear which helper function corresponds to real physical SDHC
> interface.

S3C2416 User's Manual, pages 238 (10-4) and 241 (10-7): GPE5-GPE10
correspond to SD0, GPL0-GPL3, GPL8-GPL9 --- to SD1. So all platform
devices and GPIO config functions have namas swapped versus datasheet.

We have HSMMC1 and HSMMC0 swapped due to historical reasons --- there are HSMMC
block in S3C2443 and HSMMC1 block in S3C2416 on same address. I am going
to revert this swapping later.

> > +void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
> > +{
> > +       unsigned int gpio;
> > +       unsigned int end;
> > +
> > +       end = S3C2410_GPE(7 + width);
> > +
> > +       /* Set all the necessary GPE pins to special-function 0 */
> > +       for (gpio = S3C2410_GPE(5); gpio < end; gpio++) {
> > +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> > +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> > +       }
> > +}
> > +
> > +void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
> > +{
> > +       unsigned int gpio;
> > +       unsigned int end;
> > +
> > +       end = S3C2410_GPL(0 + width);
> > +
> > +       /* Set all the necessary GPG pins to special-function 0 */
> > +       for (gpio = S3C2410_GPL(0); gpio < end; gpio++) {
> > +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> > +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> > +       }
> > +
> > +       s3c_gpio_cfgpin(S3C2410_GPL(8), S3C_GPIO_SFN(2));
> > +       s3c_gpio_setpull(S3C2410_GPL(8), S3C_GPIO_PULL_NONE);
> > +       s3c_gpio_cfgpin(S3C2410_GPL(9), S3C_GPIO_SFN(2));
> > +       s3c_gpio_setpull(S3C2410_GPL(9), S3C_GPIO_PULL_NONE);
> > +}
> > +
> > +
> > diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c
> > b/arch/arm/mach-s3c2416/setup-sdhci.c
> > new file mode 100644
> > index 0000000..345ddd1
> > --- /dev/null
> > +++ b/arch/arm/mach-s3c2416/setup-sdhci.c
> > @@ -0,0 +1,62 @@
> > +/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
> > + *
> > + * Copyright 2010 Promwad Innovation Company
> > + *     Yauhen Kharuzhy <yauhen.kharuzhy at promwad.com>
> > + *
> > + * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
> > + *
> > + * Based on mach-s3c64xx/setup-sdhci.c
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > +*/
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/types.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/io.h>
> > +
> > +#include <linux/mmc/card.h>
> > +#include <linux/mmc/host.h>
> > +
> > +#include <plat/regs-sdhci.h>
> > +#include <plat/sdhci.h>
> > +
> > +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
> > +
> > +char *s3c2416_hsmmc_clksrcs[4] = {
> > +       [0] = "hsmmc",
> > +       [1] = "hsmmc",
> > +       [2] = "hsmmc-if",
> > +       /* [3] = "48m", - note not successfully used yet */
> > +};
> > +
> > +void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
> > +                                 void __iomem *r,
> > +                                 struct mmc_ios *ios,
> > +                                 struct mmc_card *card)
> > +{
> > +       u32 ctrl2, ctrl3;
> > +
> > +       ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
> > +       ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
> > +       ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
> > +                 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
> > +                 S3C_SDHCI_CTRL2_ENFBCLKRX |
> > +                 S3C_SDHCI_CTRL2_DFCNT_NONE |
> > +                 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
> > +
> > +       if (ios->clock < 25 * 1000000)
> > +               ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
> > +                        S3C_SDHCI_CTRL3_FCSEL2 |
> > +                        S3C_SDHCI_CTRL3_FCSEL1 |
> > +                        S3C_SDHCI_CTRL3_FCSEL0);
> > +       else
> > +               ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
> > +
> > +       writel(ctrl2, r + S3C_SDHCI_CONTROL2);
> > +       writel(ctrl3, r + S3C_SDHCI_CONTROL3);
> > +}
> > +
> > diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h
> > b/arch/arm/plat-samsung/include/plat/sdhci.h
> > index 13f9fb2..d408140 100644
> > --- a/arch/arm/plat-samsung/include/plat/sdhci.h
> > +++ b/arch/arm/plat-samsung/include/plat/sdhci.h
> > @@ -78,6 +78,8 @@ extern void s3c64xx_setup_sdhci2_cfg_gpio(struct
> > platform_device *, int w);
> >  extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int
> > w);
> >  extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int
> > w);
> >  extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int
> > w);
> > +extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int
> > w);
> > +extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int
> > w);
> >
> >  /* S3C6400 SDHCI setup */
> >
> > @@ -270,6 +272,38 @@ static inline void s5pv210_default_sdhci1(void) { }
> >  static inline void s5pv210_default_sdhci2(void) { }
> >  #endif /* CONFIG_S5PC100_SETUP_SDHCI */
> >
> > +/* S3C2416 SDHCI setup */
> > +#ifdef CONFIG_S3C2416_SETUP_SDHCI
> > +extern char *s3c2416_hsmmc_clksrcs[4];
> > +
> > +extern void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
> > +                                          void __iomem *r,
> > +                                          struct mmc_ios *ios,
> > +                                          struct mmc_card *card);
> > +
> > +#ifdef CONFIG_S3C_DEV_HSMMC
> > +static inline void s3c2416_default_sdhci0(void)
> > +{
> > +       s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
> > +       s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
> > +       s3c_hsmmc0_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
> >
> 
> helper id 0 gets to interface 0 - not swapped.
> 
> 
> > +}
> > +#else
> > +static inline void s3c2416_default_sdhci0(void) { }
> > +#endif /* CONFIG_S3C_DEV_HSMMC */
> > +
> > +#ifdef CONFIG_S3C_DEV_HSMMC1
> > +static inline void s3c2416_default_sdhci1(void)
> > +{
> > +       s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
> > +       s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
> > +       s3c_hsmmc1_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
> >
> 
> helper id 1 gets to interface 1 - not swapped.
> 
> 
> > +}
> > +#else
> > +static inline void s3c2416_default_sdhci1(void) { }
> > +#endif /* CONFIG_S3C_DEV_HSMMC1 */
> > +
> > +#endif /* CONFIG_S3C2416_SETUP_SDHCI */
> >
> >
> >
> > --
> > 1.6.6.1
> >
> >

-- 
Yauhen Kharuzhy		jekhor _at_ gmail.com
			JID: jek at jabber.ru

A: No
Q: Should I quote below my post?


From dwalker at codeaurora.org  Tue Jun 22 10:24:46 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Tue, 22 Jun 2010 07:24:46 -0700
Subject: [Fwd: Mail delivery failed: returning message to sender]
Message-ID: <1277216686.21512.11.camel@m0nster>


Is anyone else getting these failure notices? Seems like we should exit
this address from the list..

Daniel
-------------- next part --------------
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From jason77.wang at gmail.com  Tue Jun 22 10:27:30 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Tue, 22 Jun 2010 22:27:30 +0800
Subject: [PATCH V2 1/2] mxc: add common debug board for 3-stack platforms
In-Reply-To: <1277216851-15782-1-git-send-email-jason77.wang@gmail.com>
References: <1277216851-15782-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <1277216851-15782-2-git-send-email-jason77.wang@gmail.com>

The debug board is little different for all mxc 3-stack(PDK)
platforms, it is possible here to add a common implementation to
support this board.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/3ds_debugboard.c              |  205 +++++++++++++++++++++++
 arch/arm/plat-mxc/Kconfig                       |   11 ++
 arch/arm/plat-mxc/Makefile                      |    1 +
 arch/arm/plat-mxc/include/mach/3ds_debugboard.h |   19 ++
 4 files changed, 236 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-mxc/3ds_debugboard.c
 create mode 100644 arch/arm/plat-mxc/include/mach/3ds_debugboard.h

diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
new file mode 100644
index 0000000..7b193c3
--- /dev/null
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <mach/hardware.h>
+
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR(n)	(n + 0x0)
+/* External UART */
+#define UARTA_BASE_ADDR(n)	(n + 0x8000)
+#define UARTB_BASE_ADDR(n)	(n + 0x10000)
+
+#define BOARD_IO_ADDR(n)	(n + 0x20000)
+/* LED switchs */
+#define LED_SWITCH_REG		0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG	0x08
+/* status, interrupt */
+#define INTR_STATUS_REG	0x10
+#define INTR_MASK_REG		0x38
+#define INTR_RESET_REG		0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG	0x40
+#define MAGIC_NUMBER2_REG	0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG	0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG	0x58
+/* module reset register*/
+#define MODULE_RESET_REG	0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG	0x68
+
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_GPIO(irq)	((irq) - MXC_INTERNAL_IRQS)
+
+#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
+#define MXC_MAX_EXP_IO_LINES	16
+
+/* interrupts like external uart , external ethernet etc*/
+#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
+#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
+#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
+#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
+#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
+
+static void __iomem *brd_io;
+static void expio_ack_irq(u32 irq);
+
+static struct resource smsc911x_resources[] = {
+	{
+		.flags = IORESOURCE_MEM,
+	} , {
+		.start = EXPIO_INT_ENET,
+		.end = EXPIO_INT_ENET,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct smsc911x_platform_config smsc911x_config = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+};
+
+static struct platform_device smsc_lan9217_device = {
+	.name = "smsc911x",
+	.id = 0,
+	.dev = {
+		.platform_data = &smsc911x_config,
+	},
+	.num_resources = ARRAY_SIZE(smsc911x_resources),
+	.resource = smsc911x_resources,
+};
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+	u32 imr_val;
+	u32 int_valid;
+	u32 expio_irq;
+
+	desc->chip->mask(irq);	/* irq = gpio irq number */
+
+	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
+	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
+
+	expio_irq = MXC_BOARD_IRQ_START;
+	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+		struct irq_desc *d;
+		if ((int_valid & 1) == 0)
+			continue;
+		d = irq_desc + expio_irq;
+		if (unlikely(!(d->handle_irq)))
+			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
+		else
+			d->handle_irq(expio_irq, d);
+	}
+
+	desc->chip->ack(irq);
+	desc->chip->unmask(irq);
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * Irq is an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg |= (1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static void expio_ack_irq(u32 irq)
+{
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	expio_mask_irq(irq);
+}
+
+static void expio_unmask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg &= ~(1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+	.ack = expio_ack_irq,
+	.mask = expio_mask_irq,
+	.unmask = expio_unmask_irq,
+};
+
+void __init mxc_expio_lan_init(void)
+{
+	platform_device_register(&smsc_lan9217_device);
+}
+
+int __init mxc_expio_init(u32 base, u32 p_irq)
+{
+	int i;
+
+	brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
+	if (brd_io == NULL)
+		return -ENOMEM;
+
+	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
+		pr_info("3-Stack Debug board not detected\n");
+		iounmap(brd_io);
+		brd_io = NULL;
+		return -ENODEV;
+	}
+
+	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
+		readw(brd_io + CPLD_CODE_VER_REG));
+
+	smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
+	smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
+
+	/*
+	 * Configure INT line as GPIO input
+	 */
+	gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
+	gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
+
+	/* disable the interrupt and clear the status */
+	__raw_writew(0, brd_io + INTR_MASK_REG);
+	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
+	for (i = MXC_EXP_IO_BASE;
+	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
+		set_irq_chip(i, &expio_irq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+	set_irq_type(p_irq, IRQF_TRIGGER_LOW);
+	set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
+
+	return 0;
+}
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 7f7ad6f..8bf917e 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -81,6 +81,17 @@ config MXC_PWM
 	help
 	  Enable support for the i.MX PWM controller(s).
 
+config MXC_DEBUG_BOARD
+	bool "Enable MXC debug board(for 3-stack)"
+	help
+	  The debug board is an integral part of the MXC 3-stack(PDK)
+	  platforms, it can be attached or removed from the peripheral
+	  board. On debug board, several debug devices(ethernet, UART,
+	  buttons, LEDs and JTAG) are implemented. Between the MCU and
+	  these devices, a CPLD is added as a bridge which performs
+	  data/address de-multiplexing and decode, signal level shift,
+	  interrupt control and various board functions.
+
 config MXC_ULPI
 	bool
 
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 895bc3c..c4a24f2 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
+obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
new file mode 100644
index 0000000..25a12e9
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_3DS_DB_H__
+#define __ASM_ARCH_MXC_3DS_DB_H__
+
+extern int __init mxc_expio_init(u32 base, u32 p_irq);
+extern void __init mxc_expio_lan_init(void);
+
+#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */
-- 
1.5.6.5



From jason77.wang at gmail.com  Tue Jun 22 10:27:31 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Tue, 22 Jun 2010 22:27:31 +0800
Subject: [PATCH V2 2/2] mx31_3ds: revert 3ds debug board relate code
In-Reply-To: <1277216851-15782-2-git-send-email-jason77.wang@gmail.com>
References: <1277216851-15782-1-git-send-email-jason77.wang@gmail.com>
	<1277216851-15782-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <1277216851-15782-3-git-send-email-jason77.wang@gmail.com>

Because we add a 3ds debug board support in mxc level, we remove
those redundant codes from board level.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx3/Kconfig                       |    1 +
 arch/arm/mach-mx3/mach-mx31_3ds.c               |  168 +----------------------
 arch/arm/plat-mxc/include/mach/board-mx31_3ds.h |   42 ------
 3 files changed, 4 insertions(+), 207 deletions(-)

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753f..fd422cf 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -58,6 +58,7 @@ config MACH_MX31LITE
 config MACH_MX31_3DS
 	bool "Support MX31PDK (3DS)"
 	select ARCH_MX31
+	select MXC_DEBUG_BOARD
 	help
 	  Include support for MX31PDK (3DS) platform. This includes specific
 	  configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 58e5729..6bae1f4 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -22,7 +22,6 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/smsc911x.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
@@ -42,6 +41,7 @@
 #include <mach/iomux-mx3.h>
 #include <mach/mxc_nand.h>
 #include <mach/spi.h>
+#include <mach/3ds_debugboard.h>
 #include "devices.h"
 
 /*!
@@ -213,173 +213,11 @@ static struct imxuart_platform_data uart_pdata = {
 };
 
 /*
- * Support for the SMSC9217 on the Debug board.
- */
-
-static struct smsc911x_platform_config smsc911x_config = {
-	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
-	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-	.phy_interface	= PHY_INTERFACE_MODE_MII,
-};
-
-static struct resource smsc911x_resources[] = {
-	{
-		.start		= LAN9217_BASE_ADDR,
-		.end		= LAN9217_BASE_ADDR + 0xff,
-		.flags		= IORESOURCE_MEM,
-	}, {
-		.start		= EXPIO_INT_ENET,
-		.end		= EXPIO_INT_ENET,
-		.flags		= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device smsc911x_device = {
-	.name		= "smsc911x",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(smsc911x_resources),
-	.resource	= smsc911x_resources,
-	.dev		= {
-		.platform_data = &smsc911x_config,
-	},
-};
-
-/*
- * Routines for the CPLD on the debug board. It contains a CPLD handling
- * LEDs, switches, interrupts for Ethernet.
- */
-
-static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
-{
-	uint32_t imr_val;
-	uint32_t int_valid;
-	uint32_t expio_irq;
-
-	imr_val = __raw_readw(CPLD_INT_MASK_REG);
-	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
-
-	expio_irq = MXC_EXP_IO_BASE;
-	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
-		if ((int_valid & 1) == 0)
-			continue;
-		generic_handle_irq(expio_irq);
-	}
-}
-
-/*
- * Disable an expio pin's interrupt by setting the bit in the imr.
- * @param irq           an expio virtual irq number
- */
-static void expio_mask_irq(uint32_t irq)
-{
-	uint16_t reg;
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* mask the interrupt */
-	reg = __raw_readw(CPLD_INT_MASK_REG);
-	reg |= 1 << expio;
-	__raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-/*
- * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
- * @param irq           an expanded io virtual irq number
- */
-static void expio_ack_irq(uint32_t irq)
-{
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* clear the interrupt status */
-	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
-	__raw_writew(0, CPLD_INT_RESET_REG);
-	/* mask the interrupt */
-	expio_mask_irq(irq);
-}
-
-/*
- * Enable a expio pin's interrupt by clearing the bit in the imr.
- * @param irq           a expio virtual irq number
- */
-static void expio_unmask_irq(uint32_t irq)
-{
-	uint16_t reg;
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* unmask the interrupt */
-	reg = __raw_readw(CPLD_INT_MASK_REG);
-	reg &= ~(1 << expio);
-	__raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-static struct irq_chip expio_irq_chip = {
-	.ack = expio_ack_irq,
-	.mask = expio_mask_irq,
-	.unmask = expio_unmask_irq,
-};
-
-static int __init mx31_3ds_init_expio(void)
-{
-	int i;
-	int ret;
-
-	/* Check if there's a debug board connected */
-	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
-	    (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
-	    (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
-		/* No Debug board found */
-		return -ENODEV;
-	}
-
-	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
-		__raw_readw(CPLD_CODE_VER_REG));
-
-	/*
-	 * Configure INT line as GPIO input
-	 */
-	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
-	if (ret)
-		pr_warning("could not get LAN irq gpio\n");
-	else
-		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-
-	/* Disable the interrupts and clear the status */
-	__raw_writew(0, CPLD_INT_MASK_REG);
-	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
-	__raw_writew(0, CPLD_INT_RESET_REG);
-	__raw_writew(0x1F, CPLD_INT_MASK_REG);
-	for (i = MXC_EXP_IO_BASE;
-	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
-	     i++) {
-		set_irq_chip(i, &expio_irq_chip);
-		set_irq_handler(i, handle_level_irq);
-		set_irq_flags(i, IRQF_VALID);
-	}
-	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
-	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
-
-	return 0;
-}
-
-/*
- * This structure defines the MX31 memory map.
- */
-static struct map_desc mx31_3ds_io_desc[] __initdata = {
-	{
-		.virtual = MX31_CS5_BASE_ADDR_VIRT,
-		.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
-		.length = MX31_CS5_SIZE,
-		.type = MT_DEVICE,
-	},
-};
-
-/*
  * Set up static virtual mappings.
  */
 static void __init mx31_3ds_map_io(void)
 {
 	mx31_map_io();
-	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
 }
 
 /*!
@@ -402,8 +240,8 @@ static void __init mxc_board_init(void)
 	mx31_3ds_usbotg_init();
 	mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
 
-	if (!mx31_3ds_init_expio())
-		platform_device_register(&smsc911x_device);
+	if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
+		mxc_expio_lan_init();
 }
 
 static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
index da92933..c26d88d 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
@@ -12,48 +12,6 @@
 #define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
 
 /* Definitions for components on the Debug board */
-
-/* Base address of CPLD controller on the Debug board */
-#define DEBUG_BASE_ADDRESS		CS5_IO_ADDRESS(CS5_BASE_ADDR)
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR		CS5_BASE_ADDR
-
-/* CPLD config and interrupt base address */
-#define CPLD_ADDR			(DEBUG_BASE_ADDRESS + 0x20000)
-
-/* LED switchs */
-#define CPLD_LED_REG			(CPLD_ADDR + 0x00)
-/* buttons */
-#define CPLD_SWITCH_BUTTONS_REG	(EXPIO_ADDR + 0x08)
-/* status, interrupt */
-#define CPLD_INT_STATUS_REG		(CPLD_ADDR + 0x10)
-#define CPLD_INT_MASK_REG		(CPLD_ADDR + 0x38)
-#define CPLD_INT_RESET_REG		(CPLD_ADDR + 0x20)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER1_REG		(CPLD_ADDR + 0x40)
-#define CPLD_MAGIC_NUMBER2_REG		(CPLD_ADDR + 0x48)
-/* CPLD code version */
-#define CPLD_CODE_VER_REG		(CPLD_ADDR + 0x50)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER3_REG		(CPLD_ADDR + 0x58)
-/* module reset register */
-#define CPLD_MODULE_RESET_REG		(CPLD_ADDR + 0x60)
-/* CPU ID and Personality ID */
-#define CPLD_MCU_BOARD_ID_REG		(CPLD_ADDR + 0x68)
-
-/* CPLD IRQ line for external uart, external ethernet etc */
 #define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
 
-#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_ENET		(MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_XUART_A	(MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_XUART_B	(MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_BUTTON_A	(MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_BUTTON_B	(MXC_EXP_IO_BASE + 4)
-
-#define MXC_MAX_EXP_IO_LINES	16
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
-- 
1.5.6.5



From jason77.wang at gmail.com  Tue Jun 22 10:27:29 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Tue, 22 Jun 2010 22:27:29 +0800
Subject: [PATCH V2 0/2]Add mxc 3ds CPLD debugboard support
Message-ID: <1277216851-15782-1-git-send-email-jason77.wang@gmail.com>

part2(v2):

Diff VS v1:
1) change file name from cpld_debugboard to 3ds_debugboard.
2) move all macro definitions from 3ds_debugboard.h to 3ds_debugboard.c
3) add a wrapper function in the 3ds_debugboard.c for lan9127 init.

I have validated build test for mx31_3ds for v2, and performed boot test
for V1 on mx31_3ds(NFS worked fine).

 [PATCH 1/2] mxc: add common debug board for 3-stack platforms
 [PATCH 2/2] mx31_3ds: revert 3ds debug board relate code




From jekhor at gmail.com  Tue Jun 22 11:22:00 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 18:22:00 +0300
Subject: [PATCH v2 0/4] S3C2416 fixes (gpiolib, SDHCI,
	compilation without FB device)
Message-ID: <1277220124-16225-1-git-send-email-jekhor@gmail.com>

This patch series fixes SDHCI on S3C2416. I got SD card working with this patches
and with patches for GPIO card detection support by Marek Szyprowski.

Resent due error in previous post.



From jekhor at gmail.com  Tue Jun 22 11:22:02 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 18:22:02 +0300
Subject: [PATCH v2 2/4] ARM: S3C2416: Set name of the framebuffer device only
	if it present
In-Reply-To: <1277220124-16225-1-git-send-email-jekhor@gmail.com>
References: <1277220124-16225-1-git-send-email-jekhor@gmail.com>
Message-ID: <1277220124-16225-3-git-send-email-jekhor@gmail.com>

Fix case when board doesn't have LCD connected and doesn't have
corresponding platform device compiled.

Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
---
 arch/arm/mach-s3c2416/s3c2416.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index 35dabcc..355ab62 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -90,7 +90,9 @@ int __init s3c2416_init(void)
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
 
+#ifdef CONFIG_S3C_DEV_FB
 	s3c_device_fb.name = "s3c2443-fb";
+#endif
 
 	return sysdev_register(&s3c2416_sysdev);
 }
-- 
1.7.1



From jekhor at gmail.com  Tue Jun 22 11:22:03 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 18:22:03 +0300
Subject: [PATCH v2 3/4] ARM: S3C2416: Add clock definition for HSMMC1
In-Reply-To: <1277220124-16225-1-git-send-email-jekhor@gmail.com>
References: <1277220124-16225-1-git-send-email-jekhor@gmail.com>
Message-ID: <1277220124-16225-4-git-send-email-jekhor@gmail.com>

Define clock for hsmmc1 device and register it.

Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
---
 .../mach-s3c2410/include/mach/regs-s3c2443-clock.h |    1 +
 arch/arm/mach-s3c2416/clock.c                      |    9 +++++++++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
index 08ab9df..c073a5a 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
@@ -86,6 +86,7 @@
 #define S3C2443_HCLKCON_LCDC		(1<<9)
 #define S3C2443_HCLKCON_USBH		(1<<11)
 #define S3C2443_HCLKCON_USBD		(1<<12)
+#define S3C2416_HCLKCON_HSMMC0		(1<<15)
 #define S3C2443_HCLKCON_HSMMC		(1<<16)
 #define S3C2443_HCLKCON_CFC		(1<<17)
 #define S3C2443_HCLKCON_SSMC		(1<<18)
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 7ccf5a2..f11d131 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -93,6 +93,13 @@ static struct clksrc_clk hsmmc_mux[] = {
 	},
 };
 
+static struct clk hsmmc1_clk = {
+	.name		= "hsmmc",
+	.id		= 1,
+	.parent		= &clk_h,
+	.enable		= s3c2443_clkcon_enable_h,
+	.ctrlbit	= S3C2416_HCLKCON_HSMMC0,
+};
 
 static inline unsigned int s3c2416_fclk_div(unsigned long clkcon0)
 {
@@ -130,6 +137,8 @@ void __init s3c2416_init_clocks(int xtal)
 	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
 		s3c_register_clksrc(clksrcs[ptr], 1);
 
+	s3c24xx_register_clock(&hsmmc1_clk);
+
 	s3c_pwmclk_init();
 
 }
-- 
1.7.1



From jekhor at gmail.com  Tue Jun 22 11:22:01 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 18:22:01 +0300
Subject: [PATCH v2 1/4] ARM: S3C24XX: Fix gpiolib support for ports K..M
In-Reply-To: <1277220124-16225-1-git-send-email-jekhor@gmail.com>
References: <1277220124-16225-1-git-send-email-jekhor@gmail.com>
Message-ID: <1277220124-16225-2-git-send-email-jekhor@gmail.com>

S3C2443 and S3C2416 has 12 GPIO banks (from A to M), increase
ARCH_NR_GPIOS for this architectures.

Also typo from previous commit has been fixed: CONFIG_CPU_S3C24XX
instead CONFIG_CPU_244X.

Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
Tested-by: Vasily Khoruzhick <anarsoul at gmail.com>

---
 arch/arm/mach-s3c2410/include/mach/gpio.h |   10 +++++++---
 1 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
index b649bf2..f7f6b07 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -22,6 +22,8 @@
 
 #ifdef CONFIG_CPU_S3C244X
 #define ARCH_NR_GPIOS	(32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
+#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
+#define ARCH_NR_GPIOS	(32 * 12 + CONFIG_S3C24XX_GPIO_EXTRA)
 #else
 #define ARCH_NR_GPIOS	(256 + CONFIG_S3C24XX_GPIO_EXTRA)
 #endif
@@ -30,8 +32,10 @@
 #include <mach/gpio-nrs.h>
 #include <mach/gpio-fns.h>
 
-#ifdef CONFIG_CPU_S3C24XX
-#define S3C_GPIO_END	(S3C2410_GPIO_BANKJ + 32)
+#ifdef CONFIG_CPU_S3C244X
+#define S3C_GPIO_END	(S3C2410_GPJ(0) + 32)
+#elif defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2416)
+#define S3C_GPIO_END	(S3C2410_GPM(0) + 32)
 #else
-#define S3C_GPIO_END	(S3C2410_GPIO_BANKH + 32)
+#define S3C_GPIO_END	(S3C2410_GPH(0) + 32)
 #endif
-- 
1.7.1



From jekhor at gmail.com  Tue Jun 22 11:22:04 2010
From: jekhor at gmail.com (Yauhen Kharuzhy)
Date: Tue, 22 Jun 2010 18:22:04 +0300
Subject: [PATCH v2 4/4] ARM: S3C2416: Add platform helpers for setup SDHCI
In-Reply-To: <1277220124-16225-1-git-send-email-jekhor@gmail.com>
References: <1277220124-16225-1-git-send-email-jekhor@gmail.com>
Message-ID: <1277220124-16225-5-git-send-email-jekhor@gmail.com>

Samsung S3C2416 has two SDHCI controllers compatible with other
Samsung's SoCs (S3C64XX, S5PC100 etc...).

Add required platform setup code that the devices can be used with
sdhci-s3c driver.

Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
---
 arch/arm/mach-s3c2416/Kconfig              |   12 +++++
 arch/arm/mach-s3c2416/Makefile             |    4 ++
 arch/arm/mach-s3c2416/s3c2416.c            |    5 ++
 arch/arm/mach-s3c2416/setup-sdhci-gpio.c   |   60 +++++++++++++++++++++++++++
 arch/arm/mach-s3c2416/setup-sdhci.c        |   62 ++++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/sdhci.h |   34 +++++++++++++++
 6 files changed, 177 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s3c2416/setup-sdhci-gpio.c
 create mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c

diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
index eafb0ed..3e2b53d 100644
--- a/arch/arm/mach-s3c2416/Kconfig
+++ b/arch/arm/mach-s3c2416/Kconfig
@@ -25,6 +25,17 @@ config S3C2416_DMA
 	help
 	  Internal config node for S3C2416 DMA support
 
+config S3C2416_SETUP_SDHCI
+	bool
+	select S3C2416_SETUP_SDHCI_GPIO
+	help
+	  Internal helper functions for S3C2416 based SDHCI systems
+
+config S3C2416_SETUP_SDHCI_GPIO
+	bool
+	help
+	  Common setup code for SDHCI gpio.
+
 menu "S3C2416 Machines"
 
 config MACH_SMDK2416
@@ -36,6 +47,7 @@ config MACH_SMDK2416
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_NAND
 	select S3C_DEV_USB_HOST
+	select S3C2416_SETUP_SDHCI
 	help
 	  Say Y here if you are using an SMDK2416
 
diff --git a/arch/arm/mach-s3c2416/Makefile b/arch/arm/mach-s3c2416/Makefile
index 6c12c7b..4f83f94 100644
--- a/arch/arm/mach-s3c2416/Makefile
+++ b/arch/arm/mach-s3c2416/Makefile
@@ -14,6 +14,10 @@ obj-$(CONFIG_CPU_S3C2416)	+= irq.o
 
 #obj-$(CONFIG_S3C2416_DMA)	+= dma.o
 
+# Device setup
+obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
+obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
+
 # Machine support
 
 obj-$(CONFIG_MACH_SMDK2416)	+= mach-smdk2416.o
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index 355ab62..06eacf8 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -53,6 +53,7 @@
 #include <plat/s3c2416.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/sdhci.h>
 
 #include <plat/iic-core.h>
 
@@ -115,6 +116,10 @@ void __init s3c2416_map_io(void)
 	s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
 	s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
 
+	/* initialize device information early */
+	s3c2416_default_sdhci0();
+	s3c2416_default_sdhci1();
+
 	iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
 }
 
diff --git a/arch/arm/mach-s3c2416/setup-sdhci-gpio.c b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
new file mode 100644
index 0000000..ebdab15
--- /dev/null
+++ b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
@@ -0,0 +1,60 @@
+/* linux/arch/arm/plat-s3c2416/setup-sdhci-gpio.c
+ *
+ * Copyright 2010 Promwad Innovation Company
+ *	Yauhen Kharuzhy <yauhen.kharuzhy at promwad.com>
+ *
+ * S3C2416 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
+ *
+ * Based on mach-s3c64xx/setup-sdhci-gpio.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/gpio.h>
+#include <mach/regs-gpio.h>
+#include <plat/gpio-cfg.h>
+
+/* Note: hsmmc1 and hsmmc0 are swapped versus datasheet */
+
+void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+	unsigned int end;
+
+	end = S3C2410_GPE(7 + width);
+
+	/* Set all the necessary GPE pins to special-function 0 */
+	for (gpio = S3C2410_GPE(5); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+}
+
+void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
+{
+	unsigned int gpio;
+	unsigned int end;
+
+	end = S3C2410_GPL(0 + width);
+
+	/* Set all the necessary GPG pins to special-function 0 */
+	for (gpio = S3C2410_GPL(0); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	s3c_gpio_cfgpin(S3C2410_GPL(8), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S3C2410_GPL(8), S3C_GPIO_PULL_NONE);
+	s3c_gpio_cfgpin(S3C2410_GPL(9), S3C_GPIO_SFN(2));
+	s3c_gpio_setpull(S3C2410_GPL(9), S3C_GPIO_PULL_NONE);
+}
+
+
diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c b/arch/arm/mach-s3c2416/setup-sdhci.c
new file mode 100644
index 0000000..345ddd1
--- /dev/null
+++ b/arch/arm/mach-s3c2416/setup-sdhci.c
@@ -0,0 +1,62 @@
+/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
+ *
+ * Copyright 2010 Promwad Innovation Company
+ *	Yauhen Kharuzhy <yauhen.kharuzhy at promwad.com>
+ *
+ * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
+ *
+ * Based on mach-s3c64xx/setup-sdhci.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <linux/mmc/card.h>
+#include <linux/mmc/host.h>
+
+#include <plat/regs-sdhci.h>
+#include <plat/sdhci.h>
+
+/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
+
+char *s3c2416_hsmmc_clksrcs[4] = {
+	[0] = "hsmmc",
+	[1] = "hsmmc",
+	[2] = "hsmmc-if",
+	/* [3] = "48m", - note not successfully used yet */
+};
+
+void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
+				  void __iomem *r,
+				  struct mmc_ios *ios,
+				  struct mmc_card *card)
+{
+	u32 ctrl2, ctrl3;
+
+	ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
+	ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
+	ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
+		  S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
+		  S3C_SDHCI_CTRL2_ENFBCLKRX |
+		  S3C_SDHCI_CTRL2_DFCNT_NONE |
+		  S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
+
+	if (ios->clock < 25 * 1000000)
+		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
+			 S3C_SDHCI_CTRL3_FCSEL2 |
+			 S3C_SDHCI_CTRL3_FCSEL1 |
+			 S3C_SDHCI_CTRL3_FCSEL0);
+	else
+		ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
+
+	writel(ctrl2, r + S3C_SDHCI_CONTROL2);
+	writel(ctrl3, r + S3C_SDHCI_CONTROL3);
+}
+
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 13f9fb2..d408140 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -78,6 +78,8 @@ extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
+extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
+extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
 
 /* S3C6400 SDHCI setup */
 
@@ -270,6 +272,38 @@ static inline void s5pv210_default_sdhci1(void) { }
 static inline void s5pv210_default_sdhci2(void) { }
 #endif /* CONFIG_S5PC100_SETUP_SDHCI */
 
+/* S3C2416 SDHCI setup */
+#ifdef CONFIG_S3C2416_SETUP_SDHCI
+extern char *s3c2416_hsmmc_clksrcs[4];
+
+extern void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
+					   void __iomem *r,
+					   struct mmc_ios *ios,
+					   struct mmc_card *card);
+
+#ifdef CONFIG_S3C_DEV_HSMMC
+static inline void s3c2416_default_sdhci0(void)
+{
+	s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
+	s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
+	s3c_hsmmc0_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c2416_default_sdhci0(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC */
+
+#ifdef CONFIG_S3C_DEV_HSMMC1
+static inline void s3c2416_default_sdhci1(void)
+{
+	s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
+	s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
+	s3c_hsmmc1_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
+}
+#else
+static inline void s3c2416_default_sdhci1(void) { }
+#endif /* CONFIG_S3C_DEV_HSMMC1 */
+
+#endif /* CONFIG_S3C2416_SETUP_SDHCI */
 
 
 
-- 
1.7.1



From john.ogness at linutronix.de  Tue Jun 22 11:54:16 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Tue, 22 Jun 2010 17:54:16 +0200
Subject: [PATCHv3 4/5] mtd: mxc_nand fixups
In-Reply-To: <AANLkTikRj_dMkKLyFhW78yld9jIYAIFncfPaPAF8WqUY@mail.gmail.com>
	(Ivo Clarysse's message of "Mon, 21 Jun 2010 13:47:41 +0200")
References: <804oh0b7gx.fsf@merkur.tec.linutronix.de>
	<20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
	<AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
	<80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTikRj_dMkKLyFhW78yld9jIYAIFncfPaPAF8WqUY@mail.gmail.com>
Message-ID: <80iq5bqd07.fsf_-_@merkur.tec.linutronix.de>

The v2 version of this patch has 2 problems. I believe that this new
version addresses the problems and still respects the strange behavior
of the i.MX21.

Problem 1: The v2 patch passes IRQF_NOAUTOEN to request_irq(), but that
flag is not evaluated by request_irq(). That flag is only evaluated in
set_irq_flags(), which is now used by this patch.

Problem 2: We are still having problems with irq's possibly being
enabled twice when threaded interrupts are used. This happens because
the main thread that enables the irq can proceed even if the interrupt
hasn't fired yet (NFC_INT is set, but the irq thread hasn't processed it
yet). In this case it is possible for the main thread to enable the irq
again with a later call to wait_op_done().

This patch addresses the problem by allowing the function that enabled
the irq to also be responsible for disabling the irq. This obviously
avoids and double enabling.

In order to prevent interrupt flooding, the interrupt handler will mask
the interrupt. After the main thread has disabled the irq, it will
unmask the interrupt. This should allow the i.MX21 to work correctly
despite its masking behavior.

And finally, this patch correctly clears the interrupt bit each
time. Previously there was a case where the interrupt bit was not being
cleared.

The patch is against linux-next 20100618.

The patch is against linux-next 20100618.

Signed-off-by: John Ogness <john.ogness at linutronix.de>
---
 drivers/mtd/nand/mxc_nand.c |   25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

Index: linux-next-20100618/drivers/mtd/nand/mxc_nand.c
===================================================================
--- linux-next-20100618.orig/drivers/mtd/nand/mxc_nand.c
+++ linux-next-20100618/drivers/mtd/nand/mxc_nand.c
@@ -30,6 +30,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/irq.h>
 
 #include <asm/mach/flash.h>
 #include <mach/mxc_nand.h>
@@ -173,8 +174,12 @@ static const char *part_probes[] = { "Re
 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 {
 	struct mxc_nand_host *host = dev_id;
+	uint16_t tmp;
 
-	disable_irq_nosync(irq);
+	/* mask interrupts */
+	tmp = readw(host->regs + NFC_CONFIG1);
+	tmp |= NFC_INT_MSK;
+	writew(tmp, host->regs + NFC_CONFIG1);
 
 	wake_up(&host->irq_waitq);
 
@@ -197,10 +202,18 @@ static void wait_op_done(struct mxc_nand
 			wait_event(host->irq_waitq,
 				readw(host->regs + NFC_CONFIG2) & NFC_INT);
 
-			tmp = readw(host->regs + NFC_CONFIG2);
-			tmp  &= ~NFC_INT;
-			writew(tmp, host->regs + NFC_CONFIG2);
+			disable_irq(host->irq);
+
+			/* unmask interrupts */
+			tmp = readw(host->regs + NFC_CONFIG1);
+			tmp &= ~NFC_INT_MSK;
+			writew(tmp, host->regs + NFC_CONFIG1);
 		}
+
+		/* clear interrupt flag */
+		tmp = readw(host->regs + NFC_CONFIG2);
+		tmp &= ~NFC_INT;
+		writew(tmp, host->regs + NFC_CONFIG2);
 	} else {
 		while (max_retries-- > 0) {
 			if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
@@ -846,7 +859,9 @@ static int __init mxcnd_probe(struct pla
 
 	host->irq = platform_get_irq(pdev, 0);
 
-	err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
+	/* request irq as disabled */
+	set_irq_flags(host->irq, IRQF_VALID | IRQF_NOAUTOEN);
+	err = request_irq(host->irq, mxc_nfc_irq, 0, DRIVER_NAME, host);
 	if (err)
 		goto eirq;
 


From u.kleine-koenig at pengutronix.de  Tue Jun 22 12:13:14 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Tue, 22 Jun 2010 18:13:14 +0200
Subject: [PATCH 09/16] arm/mx2/mbimx27: compile fixes with
	CONFIG_TOUCHSCREEN_ADS7846=y
In-Reply-To: <20100524203428.GB29092@pengutronix.de>
References: <20100524195430.GA28403@pengutronix.de>
	<1274730951-29106-9-git-send-email-u.kleine-koenig@pengutronix.de>
	<4BFADD4F.80309@eukrea.com> <20100524203428.GB29092@pengutronix.de>
Message-ID: <20100622161314.GA18606@pengutronix.de>

Hi Eric,

On Mon, May 24, 2010 at 10:34:28PM +0200, Uwe Kleine-K?nig wrote:
> On Mon, May 24, 2010 at 10:10:55PM +0200, Eric B?nard wrote:
> > Hi Uwe,
> >
> > Le 24/05/2010 21:55, Uwe Kleine-K?nig a ?crit :
> >> This fixes:
> >>
> >> 	arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c:166: error: expected identifier or '(' before '||' token
> >> 	arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c:204: error: variable 'eukrea_mbimx27_spi_0_data' has initializer but incomplete type
> >> 	arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c:205: error: unknown field 'chipselect' specified in initializer
> >> 	arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c:205: warning: excess elements in struct initializer
> >> 	arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c:205: warning: (near initialization for 'eukrea_mbimx27_spi_0_data')
> >> 	arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c:206: error: unknown field 'num_chipselect' specified in initializer
> >> 	arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c:206: warning: excess elements in struct initializer
> >> 	arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c:206: warning: (near initialization for 'eukrea_mbimx27_spi_0_data')
> >> 	arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c: In function 'eukrea_mbimx27_baseboard_init':
> >> 	arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c:239: error: implicit declaration of function 'ads7846_dev_init'
> >>
> >> While at it add TOUCHSCREEN_ADS7846=m to mx27_defconfig.
> >>
> > I already fixed this in my patchset for this board :
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2010-May/015826.html
> 
> What do you think about adding TOUCHSCREEN_ADS7846=m to mx27_defconfig?
> 
> Other than that I'm OK with your patch, too.  I will remove this patch
> from my queue.
If we want to have ADS7846 at least compilable in .35 we should go with
my patch as your's is (IMHO) too intrusive after -rc1.

Sascha?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From jamie at shareable.org  Tue Jun 22 13:00:20 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Tue, 22 Jun 2010 18:00:20 +0100
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100621135120.24299.98499.stgit@baageli.muru.com>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
Message-ID: <20100622170020.GF4371@shareable.org>

Tony Lindgren wrote:
>  __kuser_get_tls:				@ 0xffff0fe0
> -
> -#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
> -	ldr	r0, [pc, #(16 - 8)]		@ TLS stored at 0xffff0ff0
> -#else
> -	mrc	p15, 0, r0, c13, c0, 3		@ read TLS register
> -#endif
> +	ldr     r0, [pc, #(20 - 8)]		@ software TLS set in 0xffff0ff4?
> +	cmp	r0, #0				@ hardware TLS if flag not set
> +	mrceq	p15, 0, r0, c13, c0, 3		@ read hardware TLS register
> +	ldrne	r0, [pc, #(12 - 8)]		@ software TLS val at 0xffff0ff8
>  	usr_ret	lr
> -
> -	.rep	5
> -	.word	0			@ pad up to __kuser_helper_version
> -	.endr
> +	.word	0				@ non-zero for software TLS
> +	.word	0				@ software TLS value

It'd be nice not to waste instructions checking for HWCAP_TLS on archs
which definitely don't have it.  I guess it doesn't matter elsewhere;
I'd expect this to be a warm path for some programs making extensive
use of TLS (I haven't measured though).

As it's only a single instruction, and the code is in a writable page
already (copied at init), how about just patching the instruction
when ELF_HWCAP is set?

-- Jamie


From baruch at tkos.co.il  Tue Jun 22 13:06:49 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Tue, 22 Jun 2010 20:06:49 +0300
Subject: [PATCH v4] GPIO PL061: Adding Clk framework support
In-Reply-To: <1277183247-4557-1-git-send-email-viresh.kumar@st.com>
References: <1277183247-4557-1-git-send-email-viresh.kumar@st.com>
Message-ID: <20100622170649.GC11851@tarshish>

Hi Viresh,

On Tue, Jun 22, 2010 at 10:37:27AM +0530, Viresh KUMAR wrote:
> From: Viresh KUMAR <viresh.kumar at st.com>
> 
> GPIO Clk is never enabled on Platforms, like: SPEAr, which are based upon clock
> framework and use PL061 driver. This patch adds support for Clk enabling and
> disabling as and when gpios are requested and freed.
> 
> Modifications in V4:
>  - Not registering gpio_request and gpio_free if clk is not found.
> 
> Modifications in V3:
>  - if clk_get returns -ENOENT, then work without clk enable/disable.
> 
> Signed-off-by: Viresh Kumar <viresh.kumar at st.com>

Acked-by: Baruch Siach <baruch at tkos.co.il>

baruch

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From eric at eukrea.com  Tue Jun 22 13:21:56 2010
From: eric at eukrea.com (=?ISO-8859-1?Q?Eric_B=E9nard?=)
Date: Tue, 22 Jun 2010 19:21:56 +0200
Subject: [PATCH 09/16] arm/mx2/mbimx27: compile fixes
	with	CONFIG_TOUCHSCREEN_ADS7846=y
In-Reply-To: <20100622161314.GA18606@pengutronix.de>
References: <20100524195430.GA28403@pengutronix.de>	<1274730951-29106-9-git-send-email-u.kleine-koenig@pengutronix.de>	<4BFADD4F.80309@eukrea.com>
	<20100524203428.GB29092@pengutronix.de>
	<20100622161314.GA18606@pengutronix.de>
Message-ID: <4C20F134.2070801@eukrea.com>

Hi Uwe,

Le 22/06/2010 18:13, Uwe Kleine-K?nig a ?crit :
> On Mon, May 24, 2010 at 10:34:28PM +0200, Uwe Kleine-K?nig wrote:
>> What do you think about adding TOUCHSCREEN_ADS7846=m to mx27_defconfig?
>>
>> Other than that I'm OK with your patch, too.  I will remove this patch
>> from my queue.
> If we want to have ADS7846 at least compilable in .35 we should go with
> my patch as your's is (IMHO) too intrusive after -rc1.
>
unless this has changed recently, this board is not in mx27_defconfig 
for 2.6.35-rc nor in Sasha's tree so adding  TOUCHSCREEN_ADS7846=m to 
defconfig shouldn't break anything.

Eric


From robert.jarzmik at free.fr  Tue Jun 22 14:33:50 2010
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Tue, 22 Jun 2010 20:33:50 +0200
Subject: [PATCH 2/4] pxa2xx/cpufreq: Simplify DRI recomputation routine
In-Reply-To: <1276840135-5982-2-git-send-email-marek.vasut@gmail.com> (Marek
	Vasut's message of "Fri\, 18 Jun 2010 07\:48\:53 +0200")
References: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
	<1276840135-5982-2-git-send-email-marek.vasut@gmail.com>
Message-ID: <87vd9aapdd.fsf@free.fr>

Marek Vasut <marek.vasut at gmail.com> writes:

> This patch:
> 1) Simpifies the DRI recomputation routine by pulling out the common code
> 2) Fixes a bug in PXA27x DRI recomputation caused by incorrect parenthesis
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
Acked-by: Robert Jarzmik <robert.jarzmik at free.fr>

Cheers.

--
Robert


From rabin at rab.in  Tue Jun 22 15:36:38 2010
From: rabin at rab.in (Rabin Vincent)
Date: Wed, 23 Jun 2010 01:06:38 +0530
Subject: [PATCH v4 2/4] ARM: Assume new page cache pages have dirty D-cache
In-Reply-To: <20100621144632.26309.63314.stgit@e102109-lin.cambridge.arm.com>
References: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
	<20100621144632.26309.63314.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100622193638.GA9780@debian>

On Mon, Jun 21, 2010 at 03:46:32PM +0100, Catalin Marinas wrote:
> There are places in Linux where writes to newly allocated page cache
> pages happen without a subsequent call to flush_dcache_page() (several
> PIO drivers including USB HCD). This patch changes the meaning of
> PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly
> mapped page in update_mmu_cache().

Correct me if I'm misreading the code, but don't this patch and the next
one make the assumption that CONFIG_SMP == VIPT non-aliasing (or PIPT)
caches?  This patch does not add flushing on SMP systems, and the next
one handles the I$-D$ coherency issues there (ignoring the set_pte race
fix for a moment).   Won't the flushing added in this patch be
unnecessary on non-SMP PIPT systems, since they too only need the
exec-related flushing?

Rabin


From xiachendong at hotmail.com  Tue Jun 22 15:40:35 2010
From: xiachendong at hotmail.com (Xiachen Dong)
Date: Tue, 22 Jun 2010 15:40:35 -0400
Subject: Possible methods for the kernel to terminate a process
Message-ID: <BAY134-W142753895B5626C329E273BDC40@phx.gbl>


Hi,

We have a quick question. Besides sending signals, are there any other ways for the kernel to terminate a process?

We have such question because we try to kill a user space process by the shell command kill and we cannot kill it probably because it is in an un-interruptible sleep/wait. 

However, we still wish to be able to kill the user space process under this circumstance. To our knowledge of the kernel, if the kernel wants to kill a process when special event such as exception happens, it usually sends a signal to the process. We really cannot think of any other methods for a kernel to terminate a process.

Can anyone provide some hints on this? Is rebooting the machine the only solution to the problem?

Thanks,

Xiachen

 		 	   		  
_________________________________________________________________
MSN Dating: Find someone special. Start now.
http://go.microsoft.com/?linkid=9734384

From linux at arm.linux.org.uk  Tue Jun 22 16:01:52 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 22 Jun 2010 21:01:52 +0100
Subject: Possible methods for the kernel to terminate a process
In-Reply-To: <BAY134-W142753895B5626C329E273BDC40@phx.gbl>
References: <BAY134-W142753895B5626C329E273BDC40@phx.gbl>
Message-ID: <20100622200152.GA7325@n2100.arm.linux.org.uk>

On Tue, Jun 22, 2010 at 03:40:35PM -0400, Xiachen Dong wrote:
> We have such question because we try to kill a user space process by the
> shell command kill and we cannot kill it probably because it is in an
> un-interruptible sleep/wait. 

Some applications block some signals while they wait for events.
SIGKILL is one signal which is unblockable.  Have you tried using
this rather than SIGTERM ?

> However, we still wish to be able to kill the user space process under
> this circumstance. To our knowledge of the kernel, if the kernel wants
> to kill a process when special event such as exception happens, it
> usually sends a signal to the process. We really cannot think of any
> other methods for a kernel to terminate a process.

Sometimes the kernel forcefully exits the task - but that can only happen
while the task's context is running.  If it's in an uninterruptible wait
then it won't be running.


From xiachendong at hotmail.com  Tue Jun 22 17:05:53 2010
From: xiachendong at hotmail.com (Xiachen Dong)
Date: Tue, 22 Jun 2010 17:05:53 -0400
Subject: Possible methods for the kernel to terminate a process
In-Reply-To: <20100622200152.GA7325@n2100.arm.linux.org.uk>
References: <BAY134-W142753895B5626C329E273BDC40@phx.gbl>,
	<20100622200152.GA7325@n2100.arm.linux.org.uk>
Message-ID: <BAY134-W52AC318A63E932EC6DDD6BDC40@phx.gbl>



Thanks for the reply.

Sorry that I forgot to mention that the process does not have any signals blocked. And we have tried sending signal from SIG_1 to SIG_64 to the process and we were still not able to kill it.

We also wrote a simple kernel char diver (say /dev/testKill) for testing purpose. The close() method of the driver does nothing but trying to down() a semaphore that is intentionally initialized to zero. We also wrote a user space program (say userTestKill) to help the test. What userTestKill does is:

1) open the device and then;
2) does the busy sleep forever;

Then we try to kill userTestKill by the shell kill command. We found out that we are not able to kill it because userTestKill will end up calling the close() method of /dev/testKill after it receives the signal (via __exit_files() in do_exit()). However, since down() method is an uninterruptible block/wait, userTestKill can not be killed by any signal.

What we wish to know is whether there are any other methods for the kernel to terminate userTestKill under such situation. We think over it very hard and could not find any. It looks to us like the only possible method is to reboot the machine.

Here is briefly how the driver for /dev/testKill is written:

static int testKill_release( struct inode* inode, struct file* filp )
{
??? ...

??? down( &sem_testKill );??? 

??? ...

??? return 0;
}

int __init testKill_init( void )
{
??? ...
??? // intentionally set the semaphore to zero
??? sema_init(&sem_testKill, 0);
??? ...

??? return 0;
}


Thanks,


Xiachen


----------------------------------------
> Date: Tue, 22 Jun 2010 21:01:52 +0100
> From: linux at arm.linux.org.uk
> To: xiachendong at hotmail.com
> Subject: Re: Possible methods for the kernel to terminate a process
> CC: linux-arm-kernel at lists.infradead.org
>
> On Tue, Jun 22, 2010 at 03:40:35PM -0400, Xiachen Dong wrote:
>> We have such question because we try to kill a user space process by the
>> shell command kill and we cannot kill it probably because it is in an
>> un-interruptible sleep/wait.
>
> Some applications block some signals while they wait for events.
> SIGKILL is one signal which is unblockable. Have you tried using
> this rather than SIGTERM ?
>
>> However, we still wish to be able to kill the user space process under
>> this circumstance. To our knowledge of the kernel, if the kernel wants
>> to kill a process when special event such as exception happens, it
>> usually sends a signal to the process. We really cannot think of any
>> other methods for a kernel to terminate a process.
>
> Sometimes the kernel forcefully exits the task - but that can only happen
> while the task's context is running. If it's in an uninterruptible wait
> then it won't be running.
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
 		 	   		  
_________________________________________________________________
Turn down-time into play-time with Messenger games
http://go.microsoft.com/?linkid=9734385

From linux at arm.linux.org.uk  Tue Jun 22 17:40:55 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 22 Jun 2010 22:40:55 +0100
Subject: Possible methods for the kernel to terminate a process
In-Reply-To: <BAY134-W52AC318A63E932EC6DDD6BDC40@phx.gbl>
References: <BAY134-W142753895B5626C329E273BDC40@phx.gbl>
	<20100622200152.GA7325@n2100.arm.linux.org.uk>
	<BAY134-W52AC318A63E932EC6DDD6BDC40@phx.gbl>
Message-ID: <20100622214055.GB7325@n2100.arm.linux.org.uk>

On Tue, Jun 22, 2010 at 05:05:53PM -0400, Xiachen Dong wrote:
> Sorry that I forgot to mention that the process does not have any
> signals blocked. And we have tried sending signal from SIG_1 to SIG_64
> to the process and we were still not able to kill it.
> 
> We also wrote a simple kernel char diver (say /dev/testKill) for testing
> purpose. The close() method of the driver does nothing but trying to
> down() a semaphore that is intentionally initialized to zero. We also
> wrote a user space program (say userTestKill) to help the test. What
> userTestKill does is:
> 
> 1) open the device and then;
> 2) does the busy sleep forever;
> 
> Then we try to kill userTestKill by the shell kill command. We found
> out that we are not able to kill it because userTestKill will end up
> calling the close() method of /dev/testKill after it receives the
> signal (via __exit_files() in do_exit()).

Yes - the kernel is trying to free the resources which were in use by
the program.

I think what you're really asking is "I'd like to be able to kill a
program _and_ leak the resources it's using, possibly rendering them
inoperative for use by future programs."

That's possible with a few kernel hacks - all you really need to do is
to arrange for the kernel to forget that the program ever existed.

However, I suspect that you don't actually want this - you want to be
able to terminate a program and free its resources, even if freeing
those resources ends up blocking with an uninterruptible wait.  I
don't think that's possible.

The other issue here is that blocking in close() like this is a very
bad thing - even with an interruptible wait there, if you could be
interrupted in __exit_files(), there's no recovery from an interrupted
wait, and you'll end up leaking resources (and if you did try to call
exit() from within __exit_files(), you'll find that the kernel will
throw a fit with "Fixing recursive fault but reboot is needed!".)


From linus.ml.walleij at gmail.com  Tue Jun 22 18:03:47 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Wed, 23 Jun 2010 00:03:47 +0200
Subject: [PATCH 07/12] mmci: pass power_mode to the translate_vdd callback
In-Reply-To: <1277198267-10860-7-git-send-email-rabin.vincent@stericsson.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
	<1277198267-10860-7-git-send-email-rabin.vincent@stericsson.com>
Message-ID: <AANLkTil2Cb4alVFkfEjXApMgIdkmNvEEarWkT9AhXIdU@mail.gmail.com>

Thinking a bit about this patch tonight:

2010/6/22 Rabin Vincent <rabin.vincent at stericsson.com>:

> Platforms may have some external power control which need to be
> controlled from board specific code. ?This is the case for some versions
> of the MOP500 board (U8500 platform).
>
> Acked-by: Linus Walleij <linus.walleij at stericsson.com>
> Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
> ---
> ?drivers/mmc/host/mmci.c ? | ? ?3 ++-
> ?include/linux/amba/mmci.h | ? ?6 ++++--
> ?2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> index 322958f..63eb7f4 100644
> --- a/drivers/mmc/host/mmci.c
> +++ b/drivers/mmc/host/mmci.c
> @@ -483,7 +483,8 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
> ? ? ? ? ? ? ? ? * power control behind this translate function.
> ? ? ? ? ? ? ? ? */
> ? ? ? ? ? ? ? ?if (!host->vcc && host->plat->translate_vdd)
> - ? ? ? ? ? ? ? ? ? ? ? pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
> + ? ? ? ? ? ? ? ? ? ? ? pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ios->power_mode);
> ? ? ? ? ? ? ? ?/* The ST version does not have this, fall through to POWER_ON */
> ? ? ? ? ? ? ? ?if (host->hw_designer != AMBA_VENDOR_ST) {
> ? ? ? ? ? ? ? ? ? ? ? ?pwr |= MCI_PWR_UP;
> diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h
> index f9d1bb5..61b5810 100644
> --- a/include/linux/amba/mmci.h
> +++ b/include/linux/amba/mmci.h
> @@ -17,7 +17,8 @@
> ?* mmc/host.h
> ?* @translate_vdd: a callback function to translate a MMC_VDD_*
> ?* mask into a value to be binary or:ed and written into the
> - * MMCIPWR register of the block
> + * MMCIPWR register of the block. ?May also control external power
> + * based on the power_mode.

Actually this callback is named like that for a reason: it is to be used
to translate the MMC_VDD_* into a u8:4 bitmask for the MMCIPWR
register, 4 bits possibly routed out of the PL180 block on some
designs (never seen in practice, but could be used in theory).

So it translates a voltage into a 4-bit bitmask, hence the name.

Now the semantics are altered to have other side-effects in
the platform, so the function should be renamed, something like
platform_vdd_handler() would be more appropriate.

Yours,
Linus Walleij


From catalin.marinas at arm.com  Tue Jun 22 18:39:04 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 22 Jun 2010 23:39:04 +0100
Subject: [PATCH v4 2/4] ARM: Assume new page cache pages have dirty D-cache
In-Reply-To: <20100622193638.GA9780@debian>
References: <20100621144409.26309.87173.stgit@e102109-lin.cambridge.arm.com>
	<20100621144632.26309.63314.stgit@e102109-lin.cambridge.arm.com>
	<20100622193638.GA9780@debian>
Message-ID: <1277246344.20311.30.camel@toshiba-laptop>

On Tue, 2010-06-22 at 20:36 +0100, Rabin Vincent wrote:
> On Mon, Jun 21, 2010 at 03:46:32PM +0100, Catalin Marinas wrote:
> > There are places in Linux where writes to newly allocated page cache
> > pages happen without a subsequent call to flush_dcache_page() (several
> > PIO drivers including USB HCD). This patch changes the meaning of
> > PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly
> > mapped page in update_mmu_cache().
> 
> Correct me if I'm misreading the code, but don't this patch and the next
> one make the assumption that CONFIG_SMP == VIPT non-aliasing (or PIPT)
> caches?  

Yes.

> This patch does not add flushing on SMP systems, and the next
> one handles the I$-D$ coherency issues there (ignoring the set_pte race
> fix for a moment).   

The aim of this patch isn't to add any new flushing, just changes the
default assumptions on the D-cache status for new pages (from clean to
dirty).

The following patch (sync I-D caches) is aimed at sorting out a race.
This patch indeed adds a __flush_dcache_page() call if the page is dirty
but with well-behaved drivers (calling flush_dcache_page), the
PG_dcache_clean bit should always be set when reaching set_pte_at().

On ARM11MPCore, the cache operations are not broadcast in hardware, so
flush_dcache_page() must be called on the CPU that dirtied the cache. So
not having a correct driver could lead to errors in user space on this
processor (if running with more than 1).

Cortex-A9 broadcasts the cache ops in hardware, so even if you don't do
it via the driver and flush_dcache_page, you catch the dirty page later
in set_pte_at().

So the sync I-D cache patch fixes both the race and the handling of not
well written drivers (the latter only on Cortex-A9). With all this in
place, the final patch in my series allows Cortex-A9 to use lazy cache
flushing as on UP systems (flush_dcache_page/update_mmu_cache pair).

BTW, I have a patch for ARM11MPCore which allows lazy cache flushing as
well (by performing a read-for-ownership before flushing the D-cache).
However, I can't guarantee that it works on anything other than
ARM11MPcore as it is to specific to the hardware implementation.

> Won't the flushing added in this patch be
> unnecessary on non-SMP PIPT systems, since they too only need the
> exec-related flushing?

Yes, this can be optimised. We could extend the __sync_icache_dcache()
patch to all the ARMv7 (UP) and SMP configurations (just a matter of
#ifdef's) where we know for sure that the hardware is VIPT non-aliasing.

I'll have a look tomorrow and post an update to this patch.

Thanks.

-- 
Catalin



From kmpark at infradead.org  Tue Jun 22 19:27:40 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Wed, 23 Jun 2010 08:27:40 +0900
Subject: Samsung SoCs: preparation for single kernel
Message-ID: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com>

To Ben,

I really need single kernel for s5pc110 (cortex A8) and s5pc210
(cortex A9) at least.
Fortunately arm move to these approaches recently. but current Samsung
SoCs not prepare these one.

So I wonder do you have a plan or how to address these issues?
How to assign the address at resources and use it at runtime?

Personally I want to use cpu_is_*. but you reject it to use.
Other way is that we can create the base address variables and assign
it at init time.

Please give your opinions.

Thank you,
Kyungmin Park

e.g., cpu_is_* usage at OMAP tree

static void omap_init_mcspi(void)
{
        if (cpu_is_omap44xx())
                omap4_mcspi_fixup();

        platform_device_register(&omap2_mcspi1);
        platform_device_register(&omap2_mcspi2);

        if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
                omap2_mcspi3_init();

        if (cpu_is_omap343x() || cpu_is_omap44xx())
                omap2_mcspi4_init();
}


From jamie at shareable.org  Tue Jun 22 20:44:22 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Wed, 23 Jun 2010 01:44:22 +0100
Subject: Possible methods for the kernel to terminate a process
In-Reply-To: <BAY134-W142753895B5626C329E273BDC40@phx.gbl>
References: <BAY134-W142753895B5626C329E273BDC40@phx.gbl>
Message-ID: <20100623004422.GB22367@shareable.org>

Xiachen Dong wrote:
> 
> Hi,
> 
> We have a quick question. Besides sending signals, are there any other ways for the kernel to terminate a process?
> 
> We have such question because we try to kill a user space process by the shell command kill and we cannot kill it probably because it is in an un-interruptible sleep/wait. 
> 
> However, we still wish to be able to kill the user space process under this circumstance. To our knowledge of the kernel, if the kernel wants to kill a process when special event such as exception happens, it usually sends a signal to the process. We really cannot think of any other methods for a kernel to terminate a process.
> 
> Can anyone provide some hints on this? Is rebooting the machine the only solution to the problem?

You can't kill a task that's in TASK_UNINTERRUPTIBLE state, except by
the condition the task is waiting on changing.

That's been a well known problem with unix for decades, because
uninterruptible wait is used for some things (like reading a disk
file) that it seems reasonable to be able to kill.

So, to fix that, TASK_KILLABLE was added.  It means you can't
interrupt the process with most signals, but you can at least "kill
-9" the process (SIGKILL).

I think for what you're asking, if the problem is some processes tend
to block on particular device drivers, or processes blocked while
accessing files gets stuck, or things like that, the best thing is to
look at the places they might be in TASK_UNINTERRUPTIBLE and
*carefully* change the code to use TASK_KILLABLE and handle the killed
condition.

It's not possible to just search-and-replace TASK_UNINTERRUPTIBLE.
You have to make sure the killed condition is handled by cleaning up
locked resources, and only then change to killable.

-- Jamie


From eric.y.miao at gmail.com  Tue Jun 22 20:50:34 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 08:50:34 +0800
Subject: Samsung SoCs: preparation for single kernel
In-Reply-To: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com>
References: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com>
Message-ID: <AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com>

On Wed, Jun 23, 2010 at 7:27 AM, Kyungmin Park <kmpark at infradead.org> wrote:
> To Ben,
>
> I really need single kernel for s5pc110 (cortex A8) and s5pc210
> (cortex A9) at least.
> Fortunately arm move to these approaches recently. but current Samsung
> SoCs not prepare these one.
>
> So I wonder do you have a plan or how to address these issues?
> How to assign the address at resources and use it at runtime?
>
> Personally I want to use cpu_is_*. but you reject it to use.
> Other way is that we can create the base address variables and assign
> it at init time.
>
> Please give your opinions.
>
> Thank you,
> Kyungmin Park
>
> e.g., cpu_is_* usage at OMAP tree
>
> static void omap_init_mcspi(void)
> {
> ? ? ? ?if (cpu_is_omap44xx())
> ? ? ? ? ? ? ? ?omap4_mcspi_fixup();
>
> ? ? ? ?platform_device_register(&omap2_mcspi1);
> ? ? ? ?platform_device_register(&omap2_mcspi2);
>
> ? ? ? ?if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
> ? ? ? ? ? ? ? ?omap2_mcspi3_init();
>
> ? ? ? ?if (cpu_is_omap343x() || cpu_is_omap44xx())
> ? ? ? ? ? ? ? ?omap2_mcspi4_init();
> }

Just my two cents: cpu_is_*() can be used, but only when absolutely necessary.
The s3c does a CPU detection at startup, so I guess the usage of cpu_is_*()
can be even reduced.

I'm not sure if the above case is a good reference or not. The omap_init_mcspi
is called from omap2_init_devices(), while the registration can actually be
made into the board init code when that device is used (some of the McSPIs are
not used, and it's not necessary to register them), and the differences be
handled in the driver.

>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


From kgene.kim at samsung.com  Tue Jun 22 20:56:52 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 23 Jun 2010 09:56:52 +0900
Subject: [GIT PULL linux-next] Samsung S5P SoCs
Message-ID: <000d01cb126e$fa193690$ee4ba3b0$%kim@samsung.com>

Dear Stephen Rothwell,

Could you please pull the following into linux-next?

git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git#for-ne
xt

This tree is for next- Samsung S5P SoCs such as S5P6440, S5P6442, S5PC100,
and S5PV210/S5PC110.

Of course, Ben Dooks' 'next-samsung' is appropriate for next- Samsung common
and S3C SoCs.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kmpark at infradead.org  Tue Jun 22 21:47:31 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Wed, 23 Jun 2010 10:47:31 +0900
Subject: Samsung SoCs: preparation for single kernel
In-Reply-To: <AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com>
References: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com>
	<AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com>
Message-ID: <AANLkTil1i_ZGI8bY14HhjrAk9RooVreAJsTteqqrMgqJ@mail.gmail.com>

On Wed, Jun 23, 2010 at 9:50 AM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Wed, Jun 23, 2010 at 7:27 AM, Kyungmin Park <kmpark at infradead.org> wrote:
>> To Ben,
>>
>> I really need single kernel for s5pc110 (cortex A8) and s5pc210
>> (cortex A9) at least.
>> Fortunately arm move to these approaches recently. but current Samsung
>> SoCs not prepare these one.
>>
>> So I wonder do you have a plan or how to address these issues?
>> How to assign the address at resources and use it at runtime?
>>
>> Personally I want to use cpu_is_*. but you reject it to use.
>> Other way is that we can create the base address variables and assign
>> it at init time.
>>
>> Please give your opinions.
>>
>> Thank you,
>> Kyungmin Park
>>
>> e.g., cpu_is_* usage at OMAP tree
>>
>> static void omap_init_mcspi(void)
>> {
>> ? ? ? ?if (cpu_is_omap44xx())
>> ? ? ? ? ? ? ? ?omap4_mcspi_fixup();
>>
>> ? ? ? ?platform_device_register(&omap2_mcspi1);
>> ? ? ? ?platform_device_register(&omap2_mcspi2);
>>
>> ? ? ? ?if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
>> ? ? ? ? ? ? ? ?omap2_mcspi3_init();
>>
>> ? ? ? ?if (cpu_is_omap343x() || cpu_is_omap44xx())
>> ? ? ? ? ? ? ? ?omap2_mcspi4_init();
>> }
>
> Just my two cents: cpu_is_*() can be used, but only when absolutely necessary.
> The s3c does a CPU detection at startup, so I guess the usage of cpu_is_*()
> can be even reduced.

My concern is that most device resources use the S3C_* or S5P_* prefix
and defined at each arch differently.

E.G., mmc resource drivers use the S3C_PA_HSMMC0. but each mach has
different base address.
then how to handle this or make it possible?

#define S5PV210_PA_HSMMC(x)     (0xEB000000 + ((x) * 0x100000))
#define S3C_PA_HSMMC0           S5PV210_PA_HSMMC(0)
#define S3C_PA_HSMMC1           S5PV210_PA_HSMMC(1)
#define S3C_PA_HSMMC2           S5PV210_PA_HSMMC(2)

#define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
#define S3C_PA_HSMMC0           S5PC100_PA_HSMMC(0)
#define S3C_PA_HSMMC1           S5PC100_PA_HSMMC(1)
#define S3C_PA_HSMMC2           S5PC100_PA_HSMMC(2)

#define S3C64XX_PA_HSMMC(x)     (0x7C200000 + ((x) * 0x100000))
#define S3C64XX_PA_HSMMC0       S3C64XX_PA_HSMMC(0)
#define S3C64XX_PA_HSMMC1       S3C64XX_PA_HSMMC(1)
#define S3C64XX_PA_HSMMC2       S3C64XX_PA_HSMMC(2)
#define S3C_PA_HSMMC0           S3C64XX_PA_HSMMC0
#define S3C_PA_HSMMC1           S3C64XX_PA_HSMMC1
#define S3C_PA_HSMMC2           S3C64XX_PA_HSMMC2

>
> I'm not sure if the above case is a good reference or not. The omap_init_mcspi
> is called from omap2_init_devices(), while the registration can actually be
> made into the board init code when that device is used (some of the McSPIs are
> not used, and it's not necessary to register them), and the differences be
> handled in the driver.

that's just example how to use cpu_is_* in others. the current schme
in samsung SoCs. we passed the different platform name for each arch.
e.g., s3c2410_i2c or s3c2440_i2c then i2c driver detect it and handle
properly. of course it assume base address is set correctly as above.

Thank you,
Kyungmin Park
>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>


From eric.y.miao at gmail.com  Tue Jun 22 21:54:49 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 09:54:49 +0800
Subject: Samsung SoCs: preparation for single kernel
In-Reply-To: <AANLkTil1i_ZGI8bY14HhjrAk9RooVreAJsTteqqrMgqJ@mail.gmail.com>
References: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com> 
	<AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com> 
	<AANLkTil1i_ZGI8bY14HhjrAk9RooVreAJsTteqqrMgqJ@mail.gmail.com>
Message-ID: <AANLkTikDml6gQAsiRrCjIt4bUD3hnpAATr1erqCGOJMd@mail.gmail.com>

On Wed, Jun 23, 2010 at 9:47 AM, Kyungmin Park <kmpark at infradead.org> wrote:
> On Wed, Jun 23, 2010 at 9:50 AM, Eric Miao <eric.y.miao at gmail.com> wrote:
>> On Wed, Jun 23, 2010 at 7:27 AM, Kyungmin Park <kmpark at infradead.org> wrote:
>>> To Ben,
>>>
>>> I really need single kernel for s5pc110 (cortex A8) and s5pc210
>>> (cortex A9) at least.
>>> Fortunately arm move to these approaches recently. but current Samsung
>>> SoCs not prepare these one.
>>>
>>> So I wonder do you have a plan or how to address these issues?
>>> How to assign the address at resources and use it at runtime?
>>>
>>> Personally I want to use cpu_is_*. but you reject it to use.
>>> Other way is that we can create the base address variables and assign
>>> it at init time.
>>>
>>> Please give your opinions.
>>>
>>> Thank you,
>>> Kyungmin Park
>>>
>>> e.g., cpu_is_* usage at OMAP tree
>>>
>>> static void omap_init_mcspi(void)
>>> {
>>> ? ? ? ?if (cpu_is_omap44xx())
>>> ? ? ? ? ? ? ? ?omap4_mcspi_fixup();
>>>
>>> ? ? ? ?platform_device_register(&omap2_mcspi1);
>>> ? ? ? ?platform_device_register(&omap2_mcspi2);
>>>
>>> ? ? ? ?if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
>>> ? ? ? ? ? ? ? ?omap2_mcspi3_init();
>>>
>>> ? ? ? ?if (cpu_is_omap343x() || cpu_is_omap44xx())
>>> ? ? ? ? ? ? ? ?omap2_mcspi4_init();
>>> }
>>
>> Just my two cents: cpu_is_*() can be used, but only when absolutely necessary.
>> The s3c does a CPU detection at startup, so I guess the usage of cpu_is_*()
>> can be even reduced.
>
> My concern is that most device resources use the S3C_* or S5P_* prefix
> and defined at each arch differently.
>
> E.G., mmc resource drivers use the S3C_PA_HSMMC0. but each mach has
> different base address.
> then how to handle this or make it possible?
>

Now you have

s5pv210_device_hsmmc0
s5pc100_device_hsmmc0
s3c64xx_device_hsmmc0
....

each with a different base.

> #define S5PV210_PA_HSMMC(x) ? ? (0xEB000000 + ((x) * 0x100000))
> #define S3C_PA_HSMMC0 ? ? ? ? ? S5PV210_PA_HSMMC(0)
> #define S3C_PA_HSMMC1 ? ? ? ? ? S5PV210_PA_HSMMC(1)
> #define S3C_PA_HSMMC2 ? ? ? ? ? S5PV210_PA_HSMMC(2)
>
> #define S5PC100_PA_HSMMC(x) ? ? (0xED800000 + ((x) * 0x100000))
> #define S3C_PA_HSMMC0 ? ? ? ? ? S5PC100_PA_HSMMC(0)
> #define S3C_PA_HSMMC1 ? ? ? ? ? S5PC100_PA_HSMMC(1)
> #define S3C_PA_HSMMC2 ? ? ? ? ? S5PC100_PA_HSMMC(2)
>
> #define S3C64XX_PA_HSMMC(x) ? ? (0x7C200000 + ((x) * 0x100000))
> #define S3C64XX_PA_HSMMC0 ? ? ? S3C64XX_PA_HSMMC(0)
> #define S3C64XX_PA_HSMMC1 ? ? ? S3C64XX_PA_HSMMC(1)
> #define S3C64XX_PA_HSMMC2 ? ? ? S3C64XX_PA_HSMMC(2)
> #define S3C_PA_HSMMC0 ? ? ? ? ? S3C64XX_PA_HSMMC0
> #define S3C_PA_HSMMC1 ? ? ? ? ? S3C64XX_PA_HSMMC1
> #define S3C_PA_HSMMC2 ? ? ? ? ? S3C64XX_PA_HSMMC2
>
>>
>> I'm not sure if the above case is a good reference or not. The omap_init_mcspi
>> is called from omap2_init_devices(), while the registration can actually be
>> made into the board init code when that device is used (some of the McSPIs are
>> not used, and it's not necessary to register them), and the differences be
>> handled in the driver.
>
> that's just example how to use cpu_is_* in others. the current schme
> in samsung SoCs. we passed the different platform name for each arch.
> e.g., s3c2410_i2c or s3c2440_i2c then i2c driver detect it and handle
> properly. of course it assume base address is set correctly as above.

For the device driver, when you register two different i2c devices:

struct platform_device s3c2410_device_i2c {
	.name	= "s3c2410-i2c",
	...
};

struct platform_device s3c2440_device_i2c {
	.name	= "s3c2440-i2c",
	...
};

And register the corresponding one in your board code (your board code
knows exactly which one to register, no? )

And then in your i2c driver, you declare:

const static struct platform_device_id s3c_i2c_ids[] = {
	{ "s3c2410-i2c", S3C2410_SPECIFIC_FLAGS },
	{ "s3c2440-i2c", S3C2440_SPECIFIC_FLAGS },
	.....
};

Now you have S3C2410_SPECIFIC_FLAGS and S3C2440_SPECIFIC_FLAGS for your
device driver to distinguish between the differences. Normally, the
differences won't be much, and make sure you have good abstraction of
those _SPECIFIC_FLAGS.
>
> Thank you,
> Kyungmin Park
>>
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>>
>


From ryan at bluewatersys.com  Tue Jun 22 21:59:21 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Wed, 23 Jun 2010 13:59:21 +1200
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping gpios)
In-Reply-To: <20100621050957.GA23094@pengutronix.de>
References: <4C1E88AE.5070808@bluewatersys.com>
	<887171.45295.qm@web180307.mail.gq1.yahoo.com>
	<20100621050957.GA23094@pengutronix.de>
Message-ID: <4C216A79.7000305@bluewatersys.com>

On 06/21/2010 05:09 PM, Uwe Kleine-K?nig wrote:
> Hi,
>
> On Sun, Jun 20, 2010 at 07:40:46PM -0700, David Brownell wrote:
>   
>>>> And they will trigger runtime warnings, and
>>>> thus eventually get fixed.
>>>>         
>>> \
>>>   }
>>>
>>>   err = gpio_request(some_gpio, "some_gpio",
>>>           GPIOF_NO_SLEEP);
>>>       
>>
>> NAK ... keep it simple.  Such flags are
>> clearly not necessary...
>>
>> I understand that some folk are bothered
>> by concepts/frameworks that seem "too simple"
>> and thus want to complexify them.  In this
>> case I am in a position to help avoid that.
>> Complexity is not a virtue.
>>     
> I'm against such an additional flag, too.  But I still think merging
> gpio_get_value and gpio_get_value_cansleep is nice.
>
> Best regards
> Uwe
>
>   

Okay, here is a rough patch to demonstrate how I think the gpiolib
framework could be simplified for cansleep gpios.

'Can sleep' for a gpio has two different meanings depending on context:
1) When talking about a gpio chip, 'can sleep' refers to whether or not
the set/get functions for the gpio may sleep. For example, io expanders
on the i2c or spi bus may sleep.
2) When talking about a drivers use of a gpio, 'can sleep' refers to
whether or not the the driver ever calls gpio_(set/get)_value for a
particular gpio in a context where it is not possible to sleep. For
example, if a driver calls gpio_get_value(gpio) from an interupt handler
then the gpio must not be a sleeping gpio.

This patch introduces a new flag, FLAG_CANSLEEP, internal to gpiolib
which denotes that a requested gpio may be used in a sleeping context. A
new request function, gpio_request_cansleep, requests a gpio which may
only be used from sleep possible contexts (ie cannot be used from
interrupt handlers, inside spinlocks, etc). The existing gpio_request
function requests a gpio, but does not allow it to be used from a
context where sleep is not possible. If a sleeping gpio is passed to
gpio_request then -EINVAL is returned.

The gpio_(set/get)_value_cansleep functions are removed, and all callers
now use gpio_(set/get)_value. might_sleep_if is used to warn about
incorrect uses of sleeping gpios.

The benefits I see to this approach are:
 - Using gpio_request/gpio_request_cansleep means that passing a
sleeping gpio to a driver that calls gpio_(set/get)_value from non-sleep
safe context is caught at request time and handled as an error.
 - The API is simplified by combining gpio_(set/get)_value and
gpio_(set/get)_value_cansleep

~Ryan

---

 arch/arm/mach-davinci/board-dm355-evm.c     |   12 ++--
 arch/arm/mach-davinci/board-dm355-leopard.c |   12 ++--
 arch/arm/mach-davinci/board-dm644x-evm.c    |    4 +-
 drivers/gpio/gpiolib.c                      |   67 ++++++++++++++-------------
 drivers/input/keyboard/matrix_keypad.c      |   10 ++--
 drivers/leds/leds-gpio.c                    |    7 ++-
 drivers/leds/leds-lt3593.c                  |   14 +++---
 drivers/mmc/host/omap_hsmmc.c               |   11 ++--
 drivers/regulator/fixed.c                   |    6 +-
 drivers/usb/musb/davinci.c                  |    4 +-
 drivers/watchdog/wm831x_wdt.c               |    4 +-
 include/asm-generic/gpio.h                  |   16 ------
 include/linux/gpio.h                        |   18 ++-----
 sound/soc/s3c24xx/s3c24xx_simtec.c          |    8 ++--
 14 files changed, 88 insertions(+), 105 deletions(-)

diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index a319101..853fd12 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -118,10 +118,10 @@ static int dm355evm_mmc_gpios = -EINVAL;
 
 static void dm355evm_mmcsd_gpios(unsigned gpio)
 {
-	gpio_request(gpio + 0, "mmc0_ro");
-	gpio_request(gpio + 1, "mmc0_cd");
-	gpio_request(gpio + 2, "mmc1_ro");
-	gpio_request(gpio + 3, "mmc1_cd");
+	gpio_request_cansleep(gpio + 0, "mmc0_ro");
+	gpio_request_cansleep(gpio + 1, "mmc0_cd");
+	gpio_request_cansleep(gpio + 2, "mmc1_ro");
+	gpio_request_cansleep(gpio + 3, "mmc1_cd");
 
 	/* we "know" these are input-only so we don't
 	 * need to call gpio_direction_input()
@@ -262,7 +262,7 @@ static int dm355evm_mmc_get_cd(int module)
 	if (!gpio_is_valid(dm355evm_mmc_gpios))
 		return -ENXIO;
 	/* low == card present */
-	return !gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 1);
+	return !gpio_get_value(dm355evm_mmc_gpios + 2 * module + 1);
 }
 
 static int dm355evm_mmc_get_ro(int module)
@@ -270,7 +270,7 @@ static int dm355evm_mmc_get_ro(int module)
 	if (!gpio_is_valid(dm355evm_mmc_gpios))
 		return -ENXIO;
 	/* high == card's write protect switch active */
-	return gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 0);
+	return gpio_get_value(dm355evm_mmc_gpios + 2 * module + 0);
 }
 
 static struct davinci_mmc_config dm355evm_mmc_config = {
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index f1d8132..99a9a9c 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -110,10 +110,10 @@ static int leopard_mmc_gpio = -EINVAL;
 
 static void dm355leopard_mmcsd_gpios(unsigned gpio)
 {
-	gpio_request(gpio + 0, "mmc0_ro");
-	gpio_request(gpio + 1, "mmc0_cd");
-	gpio_request(gpio + 2, "mmc1_ro");
-	gpio_request(gpio + 3, "mmc1_cd");
+	gpio_request_cansleep(gpio + 0, "mmc0_ro");
+	gpio_request_cansleep(gpio + 1, "mmc0_cd");
+	gpio_request_cansleep(gpio + 2, "mmc1_ro");
+	gpio_request_cansleep(gpio + 3, "mmc1_cd");
 
 	/* we "know" these are input-only so we don't
 	 * need to call gpio_direction_input()
@@ -185,7 +185,7 @@ static int dm355leopard_mmc_get_cd(int module)
 	if (!gpio_is_valid(leopard_mmc_gpio))
 		return -ENXIO;
 	/* low == card present */
-	return !gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 1);
+	return !gpio_get_value(leopard_mmc_gpio + 2 * module + 1);
 }
 
 static int dm355leopard_mmc_get_ro(int module)
@@ -193,7 +193,7 @@ static int dm355leopard_mmc_get_ro(int module)
 	if (!gpio_is_valid(leopard_mmc_gpio))
 		return -ENXIO;
 	/* high == card's write protect switch active */
-	return gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 0);
+	return gpio_get_value(leopard_mmc_gpio + 2 * module + 0);
 }
 
 static struct davinci_mmc_config dm355leopard_mmc_config = {
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 34c8b41..5cf037c 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -335,7 +335,7 @@ static int sw_gpio;
 static ssize_t
 sw_show(struct device *d, struct device_attribute *a, char *buf)
 {
-	char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
+	char *s = gpio_get_value(sw_gpio) ? "on\n" : "off\n";
 
 	strcpy(buf, s);
 	return strlen(s);
@@ -350,7 +350,7 @@ evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
 
 	/* export dip switch option */
 	sw_gpio = gpio + 7;
-	status = gpio_request(sw_gpio, "user_sw");
+	status = gpio_request_cansleep(sw_gpio, "user_sw");
 	if (status == 0)
 		status = gpio_direction_input(sw_gpio);
 	if (status == 0)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 3ca3654..6090ddc 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -55,6 +55,7 @@ struct gpio_desc {
 #define FLAG_TRIG_FALL	5	/* trigger on falling edge */
 #define FLAG_TRIG_RISE	6	/* trigger on rising edge */
 #define FLAG_ACTIVE_LOW	7	/* sysfs value has active low */
+#define FLAG_CANSLEEP	8	/* gpio may sleep during get/set */	
 
 #define PDESC_ID_SHIFT	16	/* add new flags before this one */
 
@@ -279,7 +280,7 @@ static ssize_t gpio_value_show(struct device *dev,
 	} else {
 		int value;
 
-		value = !!gpio_get_value_cansleep(gpio);
+		value = !!__gpio_get_value(gpio);
 		if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
 			value = !value;
 
@@ -310,7 +311,7 @@ static ssize_t gpio_value_store(struct device *dev,
 		if (status == 0) {
 			if (test_bit(FLAG_ACTIVE_LOW, &desc->flags))
 				value = !value;
-			gpio_set_value_cansleep(gpio, value != 0);
+			__gpio_set_value(gpio, value != 0);
 			status = size;
 		}
 	}
@@ -773,8 +774,10 @@ int gpio_export(unsigned gpio, bool direction_may_change)
 				device_unregister(dev);
 		} else
 			status = PTR_ERR(dev);
-		if (status == 0)
+		if (status == 0) {
 			set_bit(FLAG_EXPORT, &desc->flags);
+			set_bit(FLAG_CANSLEEP, &desc->flags);
+		}
 	}
 
 	mutex_unlock(&sysfs_lock);
@@ -1152,7 +1155,7 @@ EXPORT_SYMBOL_GPL(gpiochip_remove);
  * on each other, and help provide better diagnostics in debugfs.
  * They're called even less than the "set direction" calls.
  */
-int gpio_request(unsigned gpio, const char *label)
+static int __gpio_request(unsigned gpio, const char *label, int cansleep)
 {
 	struct gpio_desc	*desc;
 	struct gpio_chip	*chip;
@@ -1171,6 +1174,9 @@ int gpio_request(unsigned gpio, const char *label)
 	if (!try_module_get(chip->owner))
 		goto done;
 
+	if (!cansleep && chip->cansleep)
+		goto done;
+
 	/* NOTE:  gpio_request() can be called in early boot,
 	 * before IRQs are enabled, for non-sleeping (SOC) GPIOs.
 	 */
@@ -1184,6 +1190,9 @@ int gpio_request(unsigned gpio, const char *label)
 		goto done;
 	}
 
+	if (cansleep)
+		set_bit(FLAG_CANSLEEP, &desc->flags);
+
 	if (chip->request) {
 		/* chip->request may sleep */
 		spin_unlock_irqrestore(&gpio_lock, flags);
@@ -1204,8 +1213,19 @@ done:
 	spin_unlock_irqrestore(&gpio_lock, flags);
 	return status;
 }
+
+int gpio_request(unsigned gpio, const char *label)
+{
+	return __gpio_request(gpio, label, 0);
+}
 EXPORT_SYMBOL_GPL(gpio_request);
 
+int gpio_request_cansleep(unsigned gpio, const char *label)
+{
+	return __gpio_request(gpio, label, 1);
+}
+EXPORT_SYMBOL_GPL(gpio_request_cansleep);
+
 void gpio_free(unsigned gpio)
 {
 	unsigned long		flags;
@@ -1525,9 +1545,13 @@ EXPORT_SYMBOL_GPL(gpio_set_debounce);
 int __gpio_get_value(unsigned gpio)
 {
 	struct gpio_chip	*chip;
+	struct gpio_desc	*desc;
 
 	chip = gpio_to_chip(gpio);
-	WARN_ON(extra_checks && chip->can_sleep);
+	desc = &gpio_desc[gpio];
+
+	might_sleep_if(extra_checks && (chip->cansleep || 
+					test_bit(FLAG_CANSLEEP, &desc->flags));
 	return chip->get ? chip->get(chip, gpio - chip->base) : 0;
 }
 EXPORT_SYMBOL_GPL(__gpio_get_value);
@@ -1544,9 +1568,13 @@ EXPORT_SYMBOL_GPL(__gpio_get_value);
 void __gpio_set_value(unsigned gpio, int value)
 {
 	struct gpio_chip	*chip;
+	struct gpio_desc	*desc;
 
 	chip = gpio_to_chip(gpio);
-	WARN_ON(extra_checks && chip->can_sleep);
+	desc = &gpio_desc[gpio];
+
+	might_sleep_if(extra_checks && (chip->cansleep ||
+					test_bit(FLAG_CANSLEEP, &desc->flags));
 	chip->set(chip, gpio - chip->base, value);
 }
 EXPORT_SYMBOL_GPL(__gpio_set_value);
@@ -1588,33 +1616,6 @@ int __gpio_to_irq(unsigned gpio)
 }
 EXPORT_SYMBOL_GPL(__gpio_to_irq);
 
-
-
-/* There's no value in making it easy to inline GPIO calls that may sleep.
- * Common examples include ones connected to I2C or SPI chips.
- */
-
-int gpio_get_value_cansleep(unsigned gpio)
-{
-	struct gpio_chip	*chip;
-
-	might_sleep_if(extra_checks);
-	chip = gpio_to_chip(gpio);
-	return chip->get ? chip->get(chip, gpio - chip->base) : 0;
-}
-EXPORT_SYMBOL_GPL(gpio_get_value_cansleep);
-
-void gpio_set_value_cansleep(unsigned gpio, int value)
-{
-	struct gpio_chip	*chip;
-
-	might_sleep_if(extra_checks);
-	chip = gpio_to_chip(gpio);
-	chip->set(chip, gpio - chip->base, value);
-}
-EXPORT_SYMBOL_GPL(gpio_set_value_cansleep);
-
-
 #ifdef CONFIG_DEBUG_FS
 
 static void gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
diff --git a/drivers/input/keyboard/matrix_keypad.c b/drivers/input/keyboard/matrix_keypad.c
index b443e08..e0b3884 100644
--- a/drivers/input/keyboard/matrix_keypad.c
+++ b/drivers/input/keyboard/matrix_keypad.c
@@ -52,7 +52,7 @@ static void __activate_col(const struct matrix_keypad_platform_data *pdata,
 	if (on) {
 		gpio_direction_output(pdata->col_gpios[col], level_on);
 	} else {
-		gpio_set_value_cansleep(pdata->col_gpios[col], !level_on);
+		gpio_set_value(pdata->col_gpios[col], !level_on);
 		gpio_direction_input(pdata->col_gpios[col]);
 	}
 }
@@ -78,7 +78,7 @@ static void activate_all_cols(const struct matrix_keypad_platform_data *pdata,
 static bool row_asserted(const struct matrix_keypad_platform_data *pdata,
 			 int row)
 {
-	return gpio_get_value_cansleep(pdata->row_gpios[row]) ?
+	return gpio_get_value(pdata->row_gpios[row]) ?
 			!pdata->active_low : pdata->active_low;
 }
 
@@ -273,7 +273,8 @@ static int __devinit init_matrix_gpio(struct platform_device *pdev,
 
 	/* initialized strobe lines as outputs, activated */
 	for (i = 0; i < pdata->num_col_gpios; i++) {
-		err = gpio_request(pdata->col_gpios[i], "matrix_kbd_col");
+		err = gpio_request_cansleep(pdata->col_gpios[i],
+					    "matrix_kbd_col");
 		if (err) {
 			dev_err(&pdev->dev,
 				"failed to request GPIO%d for COL%d\n",
@@ -285,7 +286,8 @@ static int __devinit init_matrix_gpio(struct platform_device *pdev,
 	}
 
 	for (i = 0; i < pdata->num_row_gpios; i++) {
-		err = gpio_request(pdata->row_gpios[i], "matrix_kbd_row");
+		err = gpio_request_cansleep(pdata->row_gpios[i],
+					    "matrix_kbd_row");
 		if (err) {
 			dev_err(&pdev->dev,
 				"failed to request GPIO%d for ROW%d\n",
diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c
index cc22eee..89a8278 100644
--- a/drivers/leds/leds-gpio.c
+++ b/drivers/leds/leds-gpio.c
@@ -42,7 +42,7 @@ static void gpio_led_work(struct work_struct *work)
 						 NULL, NULL);
 		led_dat->blinking = 0;
 	} else
-		gpio_set_value_cansleep(led_dat->gpio, led_dat->new_level);
+		gpio_set_value(led_dat->gpio, led_dat->new_level);
 }
 
 static void gpio_led_set(struct led_classdev *led_cdev,
@@ -103,7 +103,10 @@ static int __devinit create_gpio_led(const struct gpio_led *template,
 		return 0;
 	}
 
-	ret = gpio_request(template->gpio, template->name);
+	if (gpio_cansleep(template->gpio))
+		ret = gpio_request_cansleep(template->gpio, template->name);
+	else
+		ret = gpio_request(template->gpio);
 	if (ret < 0)
 		return ret;
 
diff --git a/drivers/leds/leds-lt3593.c b/drivers/leds/leds-lt3593.c
index 2579678..605c6ca 100644
--- a/drivers/leds/leds-lt3593.c
+++ b/drivers/leds/leds-lt3593.c
@@ -48,25 +48,25 @@ static void lt3593_led_work(struct work_struct *work)
 	 */
 
 	if (led_dat->new_level == 0) {
-		gpio_set_value_cansleep(led_dat->gpio, 0);
+		gpio_set_value(led_dat->gpio, 0);
 		return;
 	}
 
 	pulses = 32 - (led_dat->new_level * 32) / 255;
 
 	if (pulses == 0) {
-		gpio_set_value_cansleep(led_dat->gpio, 0);
+		gpio_set_value(led_dat->gpio, 0);
 		mdelay(1);
-		gpio_set_value_cansleep(led_dat->gpio, 1);
+		gpio_set_value(led_dat->gpio, 1);
 		return;
 	}
 
-	gpio_set_value_cansleep(led_dat->gpio, 1);
+	gpio_set_value(led_dat->gpio, 1);
 
 	while (pulses--) {
-		gpio_set_value_cansleep(led_dat->gpio, 0);
+		gpio_set_value(led_dat->gpio, 0);
 		udelay(1);
-		gpio_set_value_cansleep(led_dat->gpio, 1);
+		gpio_set_value(led_dat->gpio, 1);
 		udelay(1);
 	}
 }
@@ -93,7 +93,7 @@ static int __devinit create_lt3593_led(const struct gpio_led *template,
 		return 0;
 	}
 
-	ret = gpio_request(template->gpio, template->name);
+	ret = gpio_request_cansleep(template->gpio, template->name);
 	if (ret < 0)
 		return ret;
 
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index b032828..0b362a6 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -191,7 +191,7 @@ static int omap_hsmmc_card_detect(struct device *dev, int slot)
 	struct omap_mmc_platform_data *mmc = dev->platform_data;
 
 	/* NOTE: assumes card detect signal is active-low */
-	return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
+	return !gpio_get_value(mmc->slots[0].switch_pin);
 }
 
 static int omap_hsmmc_get_wp(struct device *dev, int slot)
@@ -199,7 +199,7 @@ static int omap_hsmmc_get_wp(struct device *dev, int slot)
 	struct omap_mmc_platform_data *mmc = dev->platform_data;
 
 	/* NOTE: assumes write protect signal is active-high */
-	return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
+	return gpio_get_value(mmc->slots[0].gpio_wp);
 }
 
 static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
@@ -207,7 +207,7 @@ static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
 	struct omap_mmc_platform_data *mmc = dev->platform_data;
 
 	/* NOTE: assumes card detect signal is active-low */
-	return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
+	return !gpio_get_value(mmc->slots[0].switch_pin);
 }
 
 #ifdef CONFIG_PM
@@ -473,7 +473,8 @@ static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 			pdata->slots[0].card_detect = omap_hsmmc_card_detect;
 		pdata->slots[0].card_detect_irq =
 				gpio_to_irq(pdata->slots[0].switch_pin);
-		ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
+		ret = gpio_request_cansleep(pdata->slots[0].switch_pin,
+					    "mmc_cd");
 		if (ret)
 			return ret;
 		ret = gpio_direction_input(pdata->slots[0].switch_pin);
@@ -484,7 +485,7 @@ static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
 
 	if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
 		pdata->slots[0].get_ro = omap_hsmmc_get_wp;
-		ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
+		ret = gpio_request_cansleep(pdata->slots[0].gpio_wp, "mmc_wp");
 		if (ret)
 			goto err_free_cd;
 		ret = gpio_direction_input(pdata->slots[0].gpio_wp);
diff --git a/drivers/regulator/fixed.c b/drivers/regulator/fixed.c
index 2fe9d99..1e9392d 100644
--- a/drivers/regulator/fixed.c
+++ b/drivers/regulator/fixed.c
@@ -49,7 +49,7 @@ static int fixed_voltage_enable(struct regulator_dev *dev)
 	struct fixed_voltage_data *data = rdev_get_drvdata(dev);
 
 	if (gpio_is_valid(data->gpio)) {
-		gpio_set_value_cansleep(data->gpio, data->enable_high);
+		gpio_set_value(data->gpio, data->enable_high);
 		data->is_enabled = true;
 	}
 
@@ -61,7 +61,7 @@ static int fixed_voltage_disable(struct regulator_dev *dev)
 	struct fixed_voltage_data *data = rdev_get_drvdata(dev);
 
 	if (gpio_is_valid(data->gpio)) {
-		gpio_set_value_cansleep(data->gpio, !data->enable_high);
+		gpio_set_value(data->gpio, !data->enable_high);
 		data->is_enabled = false;
 	}
 
@@ -148,7 +148,7 @@ static int __devinit reg_fixed_voltage_probe(struct platform_device *pdev)
 			dev_warn(&pdev->dev,
 				"using GPIO 0 for regulator enable control\n");
 
-		ret = gpio_request(config->gpio, config->supply_name);
+		ret = gpio_request_cansleep(config->gpio, config->supply_name);
 		if (ret) {
 			dev_err(&pdev->dev,
 			   "Could not obtain regulator enable GPIO %d: %d\n",
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index 5762436..48d72d4 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -161,7 +161,7 @@ static int vbus_state = -1;
  */
 static void evm_deferred_drvvbus(struct work_struct *ignored)
 {
-	gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
+	gpio_set_value(GPIO_nVBUS_DRV, vbus_state);
 	vbus_state = !vbus_state;
 }
 
@@ -181,7 +181,7 @@ static void davinci_source_power(struct musb *musb, int is_on, int immediate)
 		static DECLARE_WORK(evm_vbus_work, evm_deferred_drvvbus);
 
 		if (immediate)
-			gpio_set_value_cansleep(GPIO_nVBUS_DRV, vbus_state);
+			gpio_set_value(GPIO_nVBUS_DRV, vbus_state);
 		else
 			schedule_work(&evm_vbus_work);
 	}
diff --git a/drivers/watchdog/wm831x_wdt.c b/drivers/watchdog/wm831x_wdt.c
index 8c4b2d5..1f37574 100644
--- a/drivers/watchdog/wm831x_wdt.c
+++ b/drivers/watchdog/wm831x_wdt.c
@@ -123,7 +123,7 @@ static int wm831x_wdt_kick(struct wm831x *wm831x)
 	mutex_lock(&wdt_mutex);
 
 	if (update_gpio) {
-		gpio_set_value_cansleep(update_gpio, update_state);
+		gpio_set_value(update_gpio, update_state);
 		update_state = !update_state;
 		ret = 0;
 		goto out;
@@ -350,7 +350,7 @@ static int __devinit wm831x_wdt_probe(struct platform_device *pdev)
 		reg |= pdata->software << WM831X_WDOG_RST_SRC_SHIFT;
 
 		if (pdata->update_gpio) {
-			ret = gpio_request(pdata->update_gpio,
+			ret = gpio_request_cansleep(pdata->update_gpio,
 					   "Watchdog update");
 			if (ret < 0) {
 				dev_err(wm831x->dev,
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 4f3d75e..8ae678b 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -128,10 +128,6 @@ extern int gpio_direction_output(unsigned gpio, int value);
 
 extern int gpio_set_debounce(unsigned gpio, unsigned debounce);
 
-extern int gpio_get_value_cansleep(unsigned gpio);
-extern void gpio_set_value_cansleep(unsigned gpio, int value);
-
-
 /* A platform's <asm/gpio.h> code may want to inline the I/O calls when
  * the GPIO is constant and refers to some always-present controller,
  * giving direct access to chip registers and tight bitbanging loops.
@@ -200,18 +196,6 @@ static inline int gpio_cansleep(unsigned gpio)
 	return 0;
 }
 
-static inline int gpio_get_value_cansleep(unsigned gpio)
-{
-	might_sleep();
-	return gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value_cansleep(unsigned gpio, int value)
-{
-	might_sleep();
-	gpio_set_value(gpio, value);
-}
-
 #endif /* !CONFIG_HAVE_GPIO_LIB */
 
 #ifndef CONFIG_GPIO_SYSFS
diff --git a/include/linux/gpio.h b/include/linux/gpio.h
index 03f616b..d02e4cd 100644
--- a/include/linux/gpio.h
+++ b/include/linux/gpio.h
@@ -33,6 +33,11 @@ static inline int gpio_request(unsigned gpio, const char *label)
 	return -ENOSYS;
 }
 
+static inline int gpio_request_cansleep(unsigned gpio, const char *label)
+{
+	return -ENOSYS;
+}
+
 static inline void gpio_free(unsigned gpio)
 {
 	might_sleep();
@@ -76,19 +81,6 @@ static inline int gpio_cansleep(unsigned gpio)
 	return 0;
 }
 
-static inline int gpio_get_value_cansleep(unsigned gpio)
-{
-	/* GPIO can never have been requested or set as {in,out}put */
-	WARN_ON(1);
-	return 0;
-}
-
-static inline void gpio_set_value_cansleep(unsigned gpio, int value)
-{
-	/* GPIO can never have been requested or set as output */
-	WARN_ON(1);
-}
-
 static inline int gpio_export(unsigned gpio, bool direction_may_change)
 {
 	/* GPIO can never have been requested or set as {in,out}put */
diff --git a/sound/soc/s3c24xx/s3c24xx_simtec.c b/sound/soc/s3c24xx/s3c24xx_simtec.c
index 4984754..b22b0d4 100644
--- a/sound/soc/s3c24xx/s3c24xx_simtec.c
+++ b/sound/soc/s3c24xx/s3c24xx_simtec.c
@@ -51,8 +51,8 @@ static int speaker_gain_get(struct snd_kcontrol *kcontrol,
  */
 static void speaker_gain_set(int value)
 {
-	gpio_set_value_cansleep(pdata->amp_gain[0], value & 1);
-	gpio_set_value_cansleep(pdata->amp_gain[1], value >> 1);
+	gpio_set_value(pdata->amp_gain[0], value & 1);
+	gpio_set_value(pdata->amp_gain[1], value >> 1);
 }
 
 /**
@@ -253,13 +253,13 @@ static int attach_gpio_amp(struct device *dev,
 
 	/* attach gpio amp gain (if any) */
 	if (pdata->amp_gain[0] > 0) {
-		ret = gpio_request(pd->amp_gain[0], "gpio-amp-gain0");
+		ret = gpio_request_cansleep(pd->amp_gain[0], "gpio-amp-gain0");
 		if (ret) {
 			dev_err(dev, "cannot get amp gpio gain0\n");
 			return ret;
 		}
 
-		ret = gpio_request(pd->amp_gain[1], "gpio-amp-gain1");
+		ret = gpio_request_cansleep(pd->amp_gain[1], "gpio-amp-gain1");
 		if (ret) {
 			dev_err(dev, "cannot get amp gpio gain1\n");
 			gpio_free(pdata->amp_gain[0]);



From kmpark at infradead.org  Tue Jun 22 22:01:03 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Wed, 23 Jun 2010 11:01:03 +0900
Subject: Samsung SoCs: preparation for single kernel
In-Reply-To: <AANLkTikDml6gQAsiRrCjIt4bUD3hnpAATr1erqCGOJMd@mail.gmail.com>
References: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com>
	<AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com>
	<AANLkTil1i_ZGI8bY14HhjrAk9RooVreAJsTteqqrMgqJ@mail.gmail.com>
	<AANLkTikDml6gQAsiRrCjIt4bUD3hnpAATr1erqCGOJMd@mail.gmail.com>
Message-ID: <AANLkTinKsmc1IZDFqZIUutvxFQzYeAWwiR9TOEHBsbOe@mail.gmail.com>

On Wed, Jun 23, 2010 at 10:54 AM, Eric Miao <eric.y.miao at gmail.com> wrote:
> On Wed, Jun 23, 2010 at 9:47 AM, Kyungmin Park <kmpark at infradead.org> wrote:
>> On Wed, Jun 23, 2010 at 9:50 AM, Eric Miao <eric.y.miao at gmail.com> wrote:
>>> On Wed, Jun 23, 2010 at 7:27 AM, Kyungmin Park <kmpark at infradead.org> wrote:
>>>> To Ben,
>>>>
>>>> I really need single kernel for s5pc110 (cortex A8) and s5pc210
>>>> (cortex A9) at least.
>>>> Fortunately arm move to these approaches recently. but current Samsung
>>>> SoCs not prepare these one.
>>>>
>>>> So I wonder do you have a plan or how to address these issues?
>>>> How to assign the address at resources and use it at runtime?
>>>>
>>>> Personally I want to use cpu_is_*. but you reject it to use.
>>>> Other way is that we can create the base address variables and assign
>>>> it at init time.
>>>>
>>>> Please give your opinions.
>>>>
>>>> Thank you,
>>>> Kyungmin Park
>>>>
>>>> e.g., cpu_is_* usage at OMAP tree
>>>>
>>>> static void omap_init_mcspi(void)
>>>> {
>>>> ? ? ? ?if (cpu_is_omap44xx())
>>>> ? ? ? ? ? ? ? ?omap4_mcspi_fixup();
>>>>
>>>> ? ? ? ?platform_device_register(&omap2_mcspi1);
>>>> ? ? ? ?platform_device_register(&omap2_mcspi2);
>>>>
>>>> ? ? ? ?if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
>>>> ? ? ? ? ? ? ? ?omap2_mcspi3_init();
>>>>
>>>> ? ? ? ?if (cpu_is_omap343x() || cpu_is_omap44xx())
>>>> ? ? ? ? ? ? ? ?omap2_mcspi4_init();
>>>> }
>>>
>>> Just my two cents: cpu_is_*() can be used, but only when absolutely necessary.
>>> The s3c does a CPU detection at startup, so I guess the usage of cpu_is_*()
>>> can be even reduced.
>>
>> My concern is that most device resources use the S3C_* or S5P_* prefix
>> and defined at each arch differently.
>>
>> E.G., mmc resource drivers use the S3C_PA_HSMMC0. but each mach has
>> different base address.
>> then how to handle this or make it possible?
>>
>
> Now you have
>
> s5pv210_device_hsmmc0
> s5pc100_device_hsmmc0
> s3c64xx_device_hsmmc0
> ....
>
> each with a different base.

Good, then wait Ben's opinions.

>
>> #define S5PV210_PA_HSMMC(x) ? ? (0xEB000000 + ((x) * 0x100000))
>> #define S3C_PA_HSMMC0 ? ? ? ? ? S5PV210_PA_HSMMC(0)
>> #define S3C_PA_HSMMC1 ? ? ? ? ? S5PV210_PA_HSMMC(1)
>> #define S3C_PA_HSMMC2 ? ? ? ? ? S5PV210_PA_HSMMC(2)
>>
>> #define S5PC100_PA_HSMMC(x) ? ? (0xED800000 + ((x) * 0x100000))
>> #define S3C_PA_HSMMC0 ? ? ? ? ? S5PC100_PA_HSMMC(0)
>> #define S3C_PA_HSMMC1 ? ? ? ? ? S5PC100_PA_HSMMC(1)
>> #define S3C_PA_HSMMC2 ? ? ? ? ? S5PC100_PA_HSMMC(2)
>>
>> #define S3C64XX_PA_HSMMC(x) ? ? (0x7C200000 + ((x) * 0x100000))
>> #define S3C64XX_PA_HSMMC0 ? ? ? S3C64XX_PA_HSMMC(0)
>> #define S3C64XX_PA_HSMMC1 ? ? ? S3C64XX_PA_HSMMC(1)
>> #define S3C64XX_PA_HSMMC2 ? ? ? S3C64XX_PA_HSMMC(2)
>> #define S3C_PA_HSMMC0 ? ? ? ? ? S3C64XX_PA_HSMMC0
>> #define S3C_PA_HSMMC1 ? ? ? ? ? S3C64XX_PA_HSMMC1
>> #define S3C_PA_HSMMC2 ? ? ? ? ? S3C64XX_PA_HSMMC2
>>
>>>
>>> I'm not sure if the above case is a good reference or not. The omap_init_mcspi
>>> is called from omap2_init_devices(), while the registration can actually be
>>> made into the board init code when that device is used (some of the McSPIs are
>>> not used, and it's not necessary to register them), and the differences be
>>> handled in the driver.
>>
>> that's just example how to use cpu_is_* in others. the current schme
>> in samsung SoCs. we passed the different platform name for each arch.
>> e.g., s3c2410_i2c or s3c2440_i2c then i2c driver detect it and handle
>> properly. of course it assume base address is set correctly as above.
>
> For the device driver, when you register two different i2c devices:
>
> struct platform_device s3c2410_device_i2c {
> ? ? ? ?.name ? = "s3c2410-i2c",
> ? ? ? ?...
> };
>
> struct platform_device s3c2440_device_i2c {
> ? ? ? ?.name ? = "s3c2440-i2c",
> ? ? ? ?...
> };
>
> And register the corresponding one in your board code (your board code
> knows exactly which one to register, no? )
>
> And then in your i2c driver, you declare:
>
> const static struct platform_device_id s3c_i2c_ids[] = {
> ? ? ? ?{ "s3c2410-i2c", S3C2410_SPECIFIC_FLAGS },
> ? ? ? ?{ "s3c2440-i2c", S3C2440_SPECIFIC_FLAGS },
> ? ? ? ?.....
> };
>
> Now you have S3C2410_SPECIFIC_FLAGS and S3C2440_SPECIFIC_FLAGS for your
> device driver to distinguish between the differences. Normally, the
> differences won't be much, and make sure you have good abstraction of
> those _SPECIFIC_FLAGS.

It's already done.
>>
>> Thank you,
>> Kyungmin Park
>>>
>>>>
>>>> _______________________________________________
>>>> linux-arm-kernel mailing list
>>>> linux-arm-kernel at lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>>> the body of a message to majordomo at vger.kernel.org
>>> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>>>
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>


From david-b at pacbell.net  Wed Jun 23 00:37:47 2010
From: david-b at pacbell.net (David Brownell)
Date: Tue, 22 Jun 2010 21:37:47 -0700 (PDT)
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping
	gpios)
In-Reply-To: <4C216A79.7000305@bluewatersys.com>
Message-ID: <191168.5104.qm@web180308.mail.gq1.yahoo.com>



--- On Tue, 6/22/10, Ryan Mallon <ryan at bluewatersys.com> wrote:


> gpiolib


Again, you're talking about "gpiolib" when
you seem to mean the GPIO framework itself
(for which gpiolib is only an implementation
option)...

> framework could be simplified for cansleep gpios.
> 
> 'Can sleep' for a gpio has two different meanings depending
> on context

NO; for the GPIO itself it's only ever had one
meaning, regardless of context.

You're trying to conflate the GPIO and one
of the contexts in which it's used.  That's
the problem you seem to be struggling with.

Please stop conflating/confusing
those two disparate concepts...

I hope you don't have such a hard time with
the distinction in other contexts.  Like,
the fact that some calls can't be made while
holding spinlocks.  That notion is everywhere
in Linux.


> example, if a driver calls gpio_get_value(gpio) from an
> interupt handler
> then the gpio must not be a sleeping gpio.

In a threaded IRQ handler it's OK to use
the get_value_cansleep() option..



> 
> This patch introduces a new flag, FLAG_CANSLEEP, internal
> to gpiolib

NAK; Superfluous; the gpio_chip already has
that information recorded.


> new request function, gpio_request_cansleep, requests a
> gpio which may
> only be used from sleep possible contexts

Also superfluous.


 The existing
> gpio_request
> function requests a gpio, but does not allow it to be used
> from a
> context where sleep is not possible.

Changing semantics of existing calls is a big
mess, and should be avoided even if it seems
appropriate.

Since the request is just reserving a resource
that's already been identified (and which has
known characteristics, like whether the GPIO
value must be accessed only from sleeping
contexts), this call would also be superfluous.

If you want to ensure the GPIO is a cansleep()
one, just check that before reserving it.  There
is no need for new calls to support that model;
it works today.

(NAK...)



> The benefits I see to this approach are:
>  ...
>  - The API is simplified by combining gpio_(set/get)_value
> and
> gpio_(set/get)_value_cansleep


You have a strange definition of "simplified"...

Recognize that you're also proposing to remove
an API characteristic which much simplifies
code review:  you can look at calls and see
that because they're the cansleep() version,
they are unsafe in IRQ context ...

That is, you're making code (and patch)
reviews much harder and more error-prone.
This isn't good, and doesn't simplify any
process I can think of...

So, NAK on these proposed changes.

- Dave




From eric.y.miao at gmail.com  Wed Jun 23 00:58:19 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 12:58:19 +0800
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping 
	gpios)
In-Reply-To: <191168.5104.qm@web180308.mail.gq1.yahoo.com>
References: <4C216A79.7000305@bluewatersys.com>
	<191168.5104.qm@web180308.mail.gq1.yahoo.com>
Message-ID: <AANLkTinuO053upBHzsiQ2llNdu4_XZN0rfz01QuIE7LW@mail.gmail.com>

2010/6/23 David Brownell <david-b at pacbell.net>:
>
>
> --- On Tue, 6/22/10, Ryan Mallon <ryan at bluewatersys.com> wrote:
>
>
>> gpiolib
>
>
> Again, you're talking about "gpiolib" when
> you seem to mean the GPIO framework itself
> (for which gpiolib is only an implementation
> option)...
>
>> framework could be simplified for cansleep gpios.
>>
>> 'Can sleep' for a gpio has two different meanings depending
>> on context
>
> NO; for the GPIO itself it's only ever had one
> meaning, regardless of context.
>
> You're trying to conflate the GPIO and one
> of the contexts in which it's used. ?That's
> the problem you seem to be struggling with.
>
> Please stop conflating/confusing
> those two disparate concepts...
>
> I hope you don't have such a hard time with
> the distinction in other contexts. ?Like,
> the fact that some calls can't be made while
> holding spinlocks. ?That notion is everywhere
> in Linux.
>
>
>> example, if a driver calls gpio_get_value(gpio) from an
>> interupt handler
>> then the gpio must not be a sleeping gpio.
>
> In a threaded IRQ handler it's OK to use
> the get_value_cansleep() option..
>
>
>
>>
>> This patch introduces a new flag, FLAG_CANSLEEP, internal
>> to gpiolib
>
> NAK; Superfluous; the gpio_chip already has
> that information recorded.
>
>
>> new request function, gpio_request_cansleep, requests a
>> gpio which may
>> only be used from sleep possible contexts
>
> Also superfluous.
>
>
> ?The existing
>> gpio_request
>> function requests a gpio, but does not allow it to be used
>> from a
>> context where sleep is not possible.
>
> Changing semantics of existing calls is a big
> mess, and should be avoided even if it seems
> appropriate.
>
> Since the request is just reserving a resource
> that's already been identified (and which has
> known characteristics, like whether the GPIO
> value must be accessed only from sleeping
> contexts), this call would also be superfluous.
>
> If you want to ensure the GPIO is a cansleep()
> one, just check that before reserving it. ?There
> is no need for new calls to support that model;
> it works today.
>
> (NAK...)
>
>
>
>> The benefits I see to this approach are:
>> ?...
>> ?- The API is simplified by combining gpio_(set/get)_value
>> and
>> gpio_(set/get)_value_cansleep
>
>
> You have a strange definition of "simplified"...
>
> Recognize that you're also proposing to remove
> an API characteristic which much simplifies
> code review: ?you can look at calls and see
> that because they're the cansleep() version,
> they are unsafe in IRQ context ...
>
> That is, you're making code (and patch)
> reviews much harder and more error-prone.
> This isn't good, and doesn't simplify any
> process I can think of...
>
> So, NAK on these proposed changes.
>

Hi David,

You are really a NAKing machine ;-) People get confused for a reason, and
I believe you have a good solution for this?


From kgene.kim at samsung.com  Wed Jun 23 01:01:29 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 23 Jun 2010 14:01:29 +0900
Subject: [PATCH] S5PV210 Correct clock source control register properties
In-Reply-To: <AANLkTimjiBOzK1IfGTEY2xLjZ73uchjJACe8d5LQRB9s@mail.gmail.com>
References: <1276766116-6839-1-git-send-email-myungjoo.ham@samsung.com>
	<005401cb0ecb$c3f16c00$4bd44400$%kim@samsung.com>
	<AANLkTim1psO4ZeZGAgNteJp_ytRhzoPlu4D3VblPgz6w@mail.gmail.com>
	<000001cb0f63$3682c5b0$a3885110$%kim@samsung.com>
	<AANLkTimjiBOzK1IfGTEY2xLjZ73uchjJACe8d5LQRB9s@mail.gmail.com>
Message-ID: <002a01cb1291$27ca2c30$775e8490$%kim@samsung.com>

MyungJoo Ham wrote:
> 
> On Sat, Jun 19, 2010 at 12:55 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > MyungJoo Ham wrote:
> >>
> >> On Fri, Jun 18, 2010 at 6:50 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> >> > MyungJoo Ham wrote:
> >> >>
> >> >> The clock source controls (struct clksrc_clk) have been often accessing
> >> >> CLK_GATE_IPx, which are for clock gating and are accessed by each clock
> >> >> as well as the clock source. This duplicated clock issue may incur
> >> >> lockup problems when there are two modules accessing the same clock with
> >> >> different names.
> >> >>
> >> > Could you please explain further about the above the statement " accessed
> by
> >> > each clock as well as the clock source"
> >>
> >> For example, "CLK_GATE_IP2[16:19]" is accessed by "hsmmc" of struct
> >> clk (a clock) and "sclk_mmc" of struct clksrc_clk's struct clk (a
> >> clock source's clk representation).
> >>
> >> >
> >> >> Besides, the clock source control is supposed to control (setting values
> >> >> of MASK, SRC, DIV), not to turn on/off individual clock.
> >> >>
> >> > That is not quite true. Only S5PV210/S5PC110 have the gate for the clock
> mux.
> >> > S5P6440 and S5PC100, for instance, do not have a gate for the output for
> >> > _just_ the clock mux. And the reason why the Clock Mux Gate is provide for
> >> > the mux is explained in Section 3.4 of the user manual.
> >>
> >> In cases where clock mux gating is not available and we have each
> >> clock (supplied by this cluck mux) defined separatedly with .enable
> >> and .ctrlbit, we'd better omit .enable/.ctrlbit from struct
> >> clksrc_clk's struct clk.
> >>
> >> >
> >> >> Another point is that there are registers (CLK_SRC_MASK0/1) specialized
> >> >> for masking clock source control in S5PV210/S5PC110 according to the
> >> >> user manual (rev 20100201).
> >> >>
> >> >> Therefore, accessing CLK_SRC_MASK0/1 (rather than accessing
> >> >> CLK_GATE_IPx) for the clock source control is safer and fits to the
> >> >> semantics of S5PV210/S5PC110 registers. And fortuneatly, each clock
> >> >> source defined in clock.c has corresponding bit at CLK_SRC_MASK0/1
> >> >> except for MFC, G2D, and G3D.
> >> >>
> >> > Can you please explain how the use CLK_SRC_MASKx makes it safer. The
> reason
> >> > why MFC, G2D and G3D do not have a corresponding bit in
> CLK_SRC_MASKx is
> >> > mentioned in Section 3.4 of the user manual.
> >> >
> >> > Let me know your opinion.
> >> >
> >>
> >> It's "EXCEPT FOR MFC, G2D, G3D". I'm not saying that using
> >> CLK_SRC_MASKx is safer for these three. For other cases, I guess the
> >> lock up example should be fine.
> >>
> >> However, in most cases, this lockup issue does not make visible problem
> because:
> >> 1. normally, drivers use both clksrc_clk's clk and clk at the same
> >> time. for example
> >> "mmc_bus".clk_enable;
> >> "hsmmc".clk_enable;
> >>  blahblah
> >> "hsmmc".clk_disable;
> >> "mmc_bus".clk_disable;
> >> or
> >> 2. drivers sharing the same clock uses only one side of the two.
> >> or
> >> 3. the execution block between clk_enable and clk_disable is extremely short.
> >>
> >> Nevertheless, this potential lockup issue is critical and we'd better
> >> address it.
> >>
> >>
> >> >> In this patch,
> >> >>
> >> >> - DAC, HDMI, AUDIO 0/1/2, UCLK(uart) 0/1/2/3, MIXER, FIMC 0/1/2,
> >> >> FIMC, MMC 0/1/2/3, CSIS, SPI 0/1, PWI, and PWM clock sources are
> >> >> modified to use CLK_SRC_MASK0/1, which were using CLK_GATE_IPx.
> >> >>
> >> >> - CAM 0/1 did not have enable/disable control. They now access
> >> >>   CLK_SRC_MASK0.
> >> >>
> >> >> - MFC, G3D, G2D were using CLK_GATE_IPx. However, as there are no
> clocks
> >> >>   defined to control MFC, G3D, and G2D, we kept them to access
> >> >> CLK_GATE_IPx. These may need to be modified (erase .enable, .ctrlbit
> >> >> from sclk_mfc, sclk_g2d, sclk_g3d and create clocks: g3d, g2d, mfc)
> >> >> later.
> >> >>
> >> >> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> >> >> ---
> >> >>  arch/arm/mach-s5pv210/clock.c |  101
> >> > ++++++++++++++++++++++-------------------
> >> >>  1 files changed, 55 insertions(+), 46 deletions(-)
> >> >>
> >> >> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> >> >> index ec5ad8c..08c1063 100644
> >> >> --- a/arch/arm/mach-s5pv210/clock.c
> >> >> +++ b/arch/arm/mach-s5pv210/clock.c
> >> >
> >> > (snip)
> >> >
> >> > --
> >
> > Strictly speaking, 'duplicated clock problem' and 'clock gating issue which is
> controlled by CLK_GATE_IPx or CLK_SRC_MASKx' are different problem.
> > But mixed above two things in your patch.
> >
> > I think just need bug fix.
> >
> > See below mmc case.
> >
> > Following is for clock gating mmc IP by using CLK_GATE_IPx and can
> control(clock gating) clocks, 'aclk_hsmmcX' and 'sclk_mmcX' in the mmc IP.
> >
> >        {
> >                .name   = "hsmmc",
> >                .id     = 0,
> >                .parent = &clk_hclk_psys.clk,
> >                .enable = s5pv210_clk_ip2_ctrl,
> >                .ctrlbit        = (1<<16),
> >        }, {
> >                .name   = "hsmmc",
> >                .id     = 1,
> >                .parent = &clk_hclk_psys.clk,
> >                .enable = s5pv210_clk_ip2_ctrl,
> >                .ctrlbit        = (1<<17),
> >        }, {
> >                .name   = "hsmmc",
> >                .id     = 2,
> >                .parent = &clk_hclk_psys.clk,
> >                .enable = s5pv210_clk_ip2_ctrl,
> >                .ctrlbit        = (1<<18),
> >        }, {
> >                .name   = "hsmmc",
> >                .id     = 3,
> >                .parent = &clk_hclk_psys.clk,
> >                .enable = s5pv210_clk_ip2_ctrl,
> >                .ctrlbit        = (1<<19),
> >        }...
> >
> > And following is for clock gating just 'sclk_mmcX' by using CLK_SRC_MASKx.
> > But as you know should be 's5pv210_clk_mask0_ctrl' instead of
> 's5pv210_clk_ip2_ctrl' like below.
> >
> > @@ -794,8 +794,8 @@ static struct clksrc_clk clksrcs[] = {
> >                .clk            = {
> >                        .name           = "sclk_mmc",
> >                        .id             = 0,
> > -                       .enable         = s5pv210_clk_ip2_ctrl,
> > -                       .ctrlbit                = (1 << 16),
> > +                       .enable         = s5pv210_clk_mask0_ctrl,
> > +                       .ctrlbit                = (1 << 8),
> >                },
> >                .sources = &clkset_group2,
> >                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
> > @@ -804,8 +804,8 @@ static struct clksrc_clk clksrcs[] = {
> >                .clk            = {
> >                        .name           = "sclk_mmc",
> >                        .id             = 1,
> > -                       .enable         = s5pv210_clk_ip2_ctrl,
> > -                       .ctrlbit                = (1 << 17),
> > +                       .enable         = s5pv210_clk_mask0_ctrl,
> > +                       .ctrlbit                = (1 << 9),
> >                },
> >                .sources = &clkset_group2,
> >                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
> > @@ -814,8 +814,8 @@ static struct clksrc_clk clksrcs[] = {
> >                .clk            = {
> >                        .name           = "sclk_mmc",
> >                        .id             = 2,
> > -                       .enable         = s5pv210_clk_ip2_ctrl,
> > -                       .ctrlbit                = (1 << 18),
> > +                       .enable         = s5pv210_clk_mask0_ctrl,
> > +                       .ctrlbit                = (1 << 10),
> >                },
> >                .sources = &clkset_group2,
> >                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
> > @@ -824,8 +824,8 @@ static struct clksrc_clk clksrcs[] = {
> >                .clk            = {
> >                        .name           = "sclk_mmc",
> >                        .id             = 3,
> > -                       .enable         = s5pv210_clk_ip2_ctrl,
> > -                       .ctrlbit                = (1 << 19),
> > +                       .enable         = s5pv210_clk_mask0_ctrl,
> > +                       .ctrlbit                = (1 << 11),
> >                },
> >                .sources = &clkset_group2,
> >                .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }
> >
> >
> > I think there is no lockup issue(problem) after bug fix about 'sclk_xxx'.
> > Of course, carefully used distinguished clock gating in the relevant device driver.
> > Because as I said, CLK_GATE_IPx can disable all of the clock operation of each
> IP.
> > If no need CLK_GATE_IPx, just do clock gating each 'sclk_xxx'.
> >
> > Could you please re-submit new stuff for bug fix?
> 
> 
Hi,

> Ah, I've got it. So, your intention is to keep clocks with
> CLK_SRC/CLK_DIV as a form struct clksrc_clk[] list to control clock
> gating and get rid of them from struct clk[] list, right? As long as
> we are not going to list a clock in both struct clksrc_clk list and
> struct clk list, it should be fine.
> 
Yes, I think need them, because SRC and DIV of clksrc_clk are a thing about
MUX and DIVIDER of each IP input sources.
And as your patch, sclk_xxx should be controlled by CLK_SRC_MASKx.

> However, what about merging hsmmc and sclk_mmc? It there any reason to
> keep them separated? (e.g., remove "hsmmc" and let "sclk_mmc" use
> CLK_GATE_IPx.
> 
Actually, the usage or purpose of the CLK_GATE_IPx and CLK_SRC_MASKx is
differs.
As you know, all input source of each IP can be controlled(clock gating) by
CLK_GATE_IPx like hsmmc, and each special(?) clock like sclk_mmc can be
controlled by CLK_SRC_MASKx.
And as I commented, carefully used distinguished clock gating in the
relevant device driver.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From ryan at bluewatersys.com  Wed Jun 23 01:02:21 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Wed, 23 Jun 2010 17:02:21 +1200
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping
	gpios)
In-Reply-To: <191168.5104.qm@web180308.mail.gq1.yahoo.com>
References: <191168.5104.qm@web180308.mail.gq1.yahoo.com>
Message-ID: <4C21955D.1020502@bluewatersys.com>

On 06/23/2010 04:37 PM, David Brownell wrote:
> 
> 
> --- On Tue, 6/22/10, Ryan Mallon <ryan at bluewatersys.com> wrote:
> 
> 
>> gpiolib
> 
> 
> Again, you're talking about "gpiolib" when
> you seem to mean the GPIO framework itself
> (for which gpiolib is only an implementation
> option)...

Fine, its just semantics. I think everyone knows what I mean when I
refer to gpiolib.

>> framework could be simplified for cansleep gpios.
>>
>> 'Can sleep' for a gpio has two different meanings depending
>> on context
> 
> NO; for the GPIO itself it's only ever had one
> meaning, regardless of context.
> 
> You're trying to conflate the GPIO and one
> of the contexts in which it's used.  That's
> the problem you seem to be struggling with.
> 
> Please stop conflating/confusing
> those two disparate concepts...

I'm not. Some gpios, such as those on io expanders, may sleep in their
implementations of the gpio_(set/get) functions.

Drivers, which use a gpio, may call gpio_(set/get) functions for a given
gpio from a context where it is not safe to sleep. In this case, a gpio
which may sleep (ie one on an i2c io-expander) cannot be used with this
driver. The gpio_request will succeed, but any call to
gpio_(set/get)_value will produce a warning.

>> example, if a driver calls gpio_get_value(gpio) from an
>> interupt handler
>> then the gpio must not be a sleeping gpio.
> 
> In a threaded IRQ handler it's OK to use
> the get_value_cansleep() option..

Ugh, you are really twisting my words. replace 'interrupt handler' with
'non sleep safe context'.

>>
>> This patch introduces a new flag, FLAG_CANSLEEP, internal
>> to gpiolib
> 
> NAK; Superfluous; the gpio_chip already has
> that information recorded.

It has a different meaning, but I think you are still correct here. The
might_sleep_if in gpio_(set/get)_value is only necessary if
chip->cansleep is set.

> 
>> new request function, gpio_request_cansleep, requests a
>> gpio which may
>> only be used from sleep possible contexts
> 
> Also superfluous.

Not so. In my opinion, it is better to have the gpio_request fail
immediately if it is being used incorrectly. For example, say you have
two gpios:

  soc_gpio:    An SoC gpio which does not sleep on set/get
  sleepy_gpio: An i2c io-expander gpio which may sleep on get/set

and some driver code which does this:

  gpio_request(gpio, "some_gpio");
  ...
  // Non-sleep safe context
  gpio_set_value(gpio, 0);

If you pass sleepy_gpio as the gpio to this driver the gpio_request will
succeed, but you will get a warning on the gpio_set_value because its
usage is incorrect.

In my proposed change, the gpio_request would fail because sleepy_gpio
might sleep, and therefore cannot be used by drivers which use gpios in
non sleep safe context. Basically I am moving the cansleep part of the
api from the usage of gpios to the registration time. In my opinion this
is better because it means there is only one set of gpio_(set/get)_value
calls and incorrect usage of sleeping gpios will be caught when the gpio
is registered, not when it is used.

> 
>  The existing
>> gpio_request
>> function requests a gpio, but does not allow it to be used
>> from a
>> context where sleep is not possible.
> 
> Changing semantics of existing calls is a big
> mess, and should be avoided even if it seems
> appropriate.
> 
> Since the request is just reserving a resource
> that's already been identified (and which has
> known characteristics, like whether the GPIO
> value must be accessed only from sleeping
> contexts), this call would also be superfluous.
>
> If you want to ensure the GPIO is a cansleep()
> one, just check that before reserving it.  There
> is no need for new calls to support that model;
> it works today.

Except that drivers do not do this.

> (NAK...)
> 
> 
> 
>> The benefits I see to this approach are:
>>  ...
>>  - The API is simplified by combining gpio_(set/get)_value
>> and
>> gpio_(set/get)_value_cansleep
> 
> 
> You have a strange definition of "simplified"...
> 
> Recognize that you're also proposing to remove
> an API characteristic which much simplifies
> code review:  you can look at calls and see
> that because they're the cansleep() version,
> they are unsafe in IRQ context ...

Hmm, fair point.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From kgene.kim at samsung.com  Wed Jun 23 01:21:51 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 23 Jun 2010 14:21:51 +0900
Subject: [PATCH v2] S5PV210 Correct clock register properties
In-Reply-To: <1277193951-22559-1-git-send-email-myungjoo.ham@samsung.com>
References: <1277193951-22559-1-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <002c01cb1293$ffe373e0$ffaa5ba0$%kim@samsung.com>

MyungJoo Ham wrote:
> 
> Note that this patch revises and merges the two previous patches:
> [PATCH] S5PV210 Correct clock register properties
> [PATCH] S5PV210 Correct clock source control register properties
> 
> 1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which
were
> defined incorrectly.
> 
> 2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc,
> sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their
> twins defined in struct clk init_clocks_disable[] and struct clk
> init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK
> register to avoid the duplicated clock problem described below.
> 
> --- Duplicated Clock Problem ---
> Please note that each clock definition should access different control
> register; otherwise, the system may suffer lockups. For example, if we
> have two clock definitions "a" and "b" which access the same register
> (and the shift value). Then, when we do:
> 
> 	module A
> 	clk = clk_get("a");
> 	clk->clk_enable(clk);
> 
> 	module B (context switch)
> 	clk = clk_get("b");
> 	clk->clk_enable(clk);
> 	do something with clk.
> 	clk->clk_disable(clk);
> 
> 	module A (context switch)
> 	do something with clk
> 	* At this point, the system may hang.
> 
> Therefore, there should be no clock definitions with the same contol
> register/shift. If we need to create "aliases", then, creating child
> clocks sharing the clock should be fine.
> 
> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> ---
>  arch/arm/mach-s5pv210/clock.c |   72
++++++++++++++++++++--------------------
>  1 files changed, 36 insertions(+), 36 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> index 154bca4..10a9f84 100644
> --- a/arch/arm/mach-s5pv210/clock.c
> +++ b/arch/arm/mach-s5pv210/clock.c
> @@ -406,13 +406,13 @@ static struct clk init_clocks_disable[] = {
>  		.id		= 0,
>  		.parent		= &clk_p,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<4),
> +		.ctrlbit	= (1<<5),

If possible, please add space between <<, like (1 << 5)

>  	}, {
>  		.name		= "i2s_v32",
>  		.id		= 1,
>  		.parent		= &clk_p,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<4),
> +		.ctrlbit	= (1<<6),
>  	}
>  };
> 
> @@ -429,25 +429,25 @@ static struct clk init_clocks[] = {
>  		.id		= 0,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<7),
> +		.ctrlbit	= (1<<17),
>  	}, {
>  		.name		= "uart",
>  		.id		= 1,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<8),
> +		.ctrlbit	= (1<<18),
>  	}, {
>  		.name		= "uart",
>  		.id		= 2,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<9),
> +		.ctrlbit	= (1<<19),
>  	}, {
>  		.name		= "uart",
>  		.id		= 3,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<10),
> +		.ctrlbit	= (1<<20),
>  	},
>  };
> 
> @@ -565,8 +565,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
>  	.clk		= {
>  		.name		= "sclk_audio",
>  		.id		= 0,
> -		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1 << 4),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 24),
>  	},
>  	.sources = &clkset_sclk_audio0,
>  	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
> @@ -594,8 +594,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
>  	.clk		= {
>  		.name		= "sclk_audio",
>  		.id		= 1,
> -		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1 << 5),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 25),
>  	},
>  	.sources = &clkset_sclk_audio1,
>  	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
> @@ -623,8 +623,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
>  	.clk		= {
>  		.name		= "sclk_audio",
>  		.id		= 2,
> -		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1 << 6),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 26),
>  	},
>  	.sources = &clkset_sclk_audio2,
>  	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
> @@ -680,8 +680,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "uclk1",
>  			.id		= 0,
> -			.ctrlbit	= (1<<17),
> -			.enable		= s5pv210_clk_ip3_ctrl,
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 12),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
> @@ -690,8 +690,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "uclk1",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 18),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 13),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
> @@ -700,8 +700,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "uclk1",
>  			.id		= 2,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 19),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 14),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
> @@ -710,8 +710,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "uclk1",
>  			.id		= 3,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 20),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 15),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
> @@ -784,8 +784,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_fimd",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip1_ctrl,
> -			.ctrlbit	= (1 << 0),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 5),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
> @@ -794,8 +794,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 0,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 16),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 8),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
> @@ -804,8 +804,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 17),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 9),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
> @@ -814,8 +814,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 2,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 18),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 10),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
> @@ -824,8 +824,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 3,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 19),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 11),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
> @@ -874,8 +874,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_spi",
>  			.id		= 0,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 12),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 16),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
> @@ -884,8 +884,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_spi",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 13),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 17),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
> @@ -904,8 +904,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_pwm",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 23),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 19),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
> --

Looks good.

But missed something such as sclk_dac, sclk_hdmi, sclk_mixer, sclk_fimc,
sclk_cam, sclk_csis, and sclk_pwi.
Any reason?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From eric.y.miao at gmail.com  Wed Jun 23 01:26:31 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 13:26:31 +0800
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping 
	gpios)
In-Reply-To: <4C21955D.1020502@bluewatersys.com>
References: <191168.5104.qm@web180308.mail.gq1.yahoo.com>
	<4C21955D.1020502@bluewatersys.com>
Message-ID: <AANLkTikEvq_qcOWaev79UbHFfWp7hnOil_q9x-QZuSlK@mail.gmail.com>

On Wed, Jun 23, 2010 at 1:02 PM, Ryan Mallon <ryan at bluewatersys.com> wrote:
> On 06/23/2010 04:37 PM, David Brownell wrote:
>>
>>
>> --- On Tue, 6/22/10, Ryan Mallon <ryan at bluewatersys.com> wrote:
>>
>>
>>> gpiolib
>>
>>
>> Again, you're talking about "gpiolib" when
>> you seem to mean the GPIO framework itself
>> (for which gpiolib is only an implementation
>> option)...
>
> Fine, its just semantics. I think everyone knows what I mean when I
> refer to gpiolib.
>
>>> framework could be simplified for cansleep gpios.
>>>
>>> 'Can sleep' for a gpio has two different meanings depending
>>> on context
>>
>> NO; for the GPIO itself it's only ever had one
>> meaning, regardless of context.
>>
>> You're trying to conflate the GPIO and one
>> of the contexts in which it's used. ?That's
>> the problem you seem to be struggling with.
>>
>> Please stop conflating/confusing
>> those two disparate concepts...
>
> I'm not. Some gpios, such as those on io expanders, may sleep in their
> implementations of the gpio_(set/get) functions.
>
> Drivers, which use a gpio, may call gpio_(set/get) functions for a given
> gpio from a context where it is not safe to sleep. In this case, a gpio
> which may sleep (ie one on an i2c io-expander) cannot be used with this
> driver. The gpio_request will succeed, but any call to
> gpio_(set/get)_value will produce a warning.
>
>>> example, if a driver calls gpio_get_value(gpio) from an
>>> interupt handler
>>> then the gpio must not be a sleeping gpio.
>>
>> In a threaded IRQ handler it's OK to use
>> the get_value_cansleep() option..
>
> Ugh, you are really twisting my words. replace 'interrupt handler' with
> 'non sleep safe context'.
>
>>>
>>> This patch introduces a new flag, FLAG_CANSLEEP, internal
>>> to gpiolib
>>
>> NAK; Superfluous; the gpio_chip already has
>> that information recorded.
>
> It has a different meaning, but I think you are still correct here. The
> might_sleep_if in gpio_(set/get)_value is only necessary if
> chip->cansleep is set.
>
>>
>>> new request function, gpio_request_cansleep, requests a
>>> gpio which may
>>> only be used from sleep possible contexts
>>
>> Also superfluous.
>
> Not so. In my opinion, it is better to have the gpio_request fail
> immediately if it is being used incorrectly. For example, say you have
> two gpios:
>
> ?soc_gpio: ? ?An SoC gpio which does not sleep on set/get
> ?sleepy_gpio: An i2c io-expander gpio which may sleep on get/set
>
> and some driver code which does this:
>
> ?gpio_request(gpio, "some_gpio");
> ?...
> ?// Non-sleep safe context
> ?gpio_set_value(gpio, 0);
>
> If you pass sleepy_gpio as the gpio to this driver the gpio_request will
> succeed, but you will get a warning on the gpio_set_value because its
> usage is incorrect.
>
> In my proposed change, the gpio_request would fail because sleepy_gpio
> might sleep, and therefore cannot be used by drivers which use gpios in
> non sleep safe context. Basically I am moving the cansleep part of the
> api from the usage of gpios to the registration time. In my opinion this
> is better because it means there is only one set of gpio_(set/get)_value
> calls and incorrect usage of sleeping gpios will be caught when the gpio
> is registered, not when it is used.
>
>>
>> ?The existing
>>> gpio_request
>>> function requests a gpio, but does not allow it to be used
>>> from a
>>> context where sleep is not possible.
>>
>> Changing semantics of existing calls is a big
>> mess, and should be avoided even if it seems
>> appropriate.
>>
>> Since the request is just reserving a resource
>> that's already been identified (and which has
>> known characteristics, like whether the GPIO
>> value must be accessed only from sleeping
>> contexts), this call would also be superfluous.
>>
>> If you want to ensure the GPIO is a cansleep()
>> one, just check that before reserving it. ?There
>> is no need for new calls to support that model;
>> it works today.
>
> Except that drivers do not do this.
>
>> (NAK...)
>>
>>
>>
>>> The benefits I see to this approach are:
>>> ?...
>>> ?- The API is simplified by combining gpio_(set/get)_value
>>> and
>>> gpio_(set/get)_value_cansleep
>>
>>
>> You have a strange definition of "simplified"...
>>
>> Recognize that you're also proposing to remove
>> an API characteristic which much simplifies
>> code review: ?you can look at calls and see
>> that because they're the cansleep() version,
>> they are unsafe in IRQ context ...
>
> Hmm, fair point.
>

My two cents, if it feels confused to use the _cansleep version, why don't
we just introduce an _atomic() version and use that in atomic situation,
since most usage of gpio API can actually _sleep_. I didn't read all the
scroll back, so if it's wrong, ignore me.


From m.szyprowski at samsung.com  Wed Jun 23 02:25:45 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 23 Jun 2010 08:25:45 +0200
Subject: Samsung SoCs: preparation for single kernel
In-Reply-To: <AANLkTikDml6gQAsiRrCjIt4bUD3hnpAATr1erqCGOJMd@mail.gmail.com>
References: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com>
	<AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com>
	<AANLkTil1i_ZGI8bY14HhjrAk9RooVreAJsTteqqrMgqJ@mail.gmail.com>
	<AANLkTikDml6gQAsiRrCjIt4bUD3hnpAATr1erqCGOJMd@mail.gmail.com>
Message-ID: <002301cb129c$ec59fe30$c50dfa90$%szyprowski@samsung.com>

Hello,

On Wednesday, June 23, 2010 3:55 AM Eric Miao wrote:

> ...

> >>> e.g., cpu_is_* usage at OMAP tree
> >>>
> >>> static void omap_init_mcspi(void)
> >>> {
> >>>        if (cpu_is_omap44xx())
> >>>                omap4_mcspi_fixup();
> >>>
> >>>        platform_device_register(&omap2_mcspi1);
> >>>        platform_device_register(&omap2_mcspi2);
> >>>
> >>>        if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
> >>>                omap2_mcspi3_init();
> >>>
> >>>        if (cpu_is_omap343x() || cpu_is_omap44xx())
> >>>                omap2_mcspi4_init();
> >>> }
> >>
> >> Just my two cents: cpu_is_*() can be used, but only when absolutely
> necessary.
> >> The s3c does a CPU detection at startup, so I guess the usage of
> cpu_is_*()
> >> can be even reduced.
> >
> > My concern is that most device resources use the S3C_* or S5P_* prefix
> > and defined at each arch differently.
> >
> > E.G., mmc resource drivers use the S3C_PA_HSMMC0. but each mach has
> > different base address.
> > then how to handle this or make it possible?
> >
> 
> Now you have
> 
> s5pv210_device_hsmmc0
> s5pc100_device_hsmmc0
> s3c64xx_device_hsmmc0
> ....
> 
> each with a different base.

There is no need for such code duplication. Ben is working on a solution for
a single kernel which supports multiple SoCs. Some of his work in progress can
be found here: git://git.fluff.org/bjdooks/linux branch wip-samsung-dev and
wip-samsung-dev2.

> ...

> >> I'm not sure if the above case is a good reference or not. The
> omap_init_mcspi
> >> is called from omap2_init_devices(), while the registration can actually
> be
> >> made into the board init code when that device is used (some of the
> McSPIs are
> >> not used, and it's not necessary to register them), and the differences
> be
> >> handled in the driver.
> >
> > that's just example how to use cpu_is_* in others. the current schme
> > in samsung SoCs. we passed the different platform name for each arch.
> > e.g., s3c2410_i2c or s3c2440_i2c then i2c driver detect it and handle
> > properly. of course it assume base address is set correctly as above.
> 
> For the device driver, when you register two different i2c devices:
> 
> struct platform_device s3c2410_device_i2c {
> 	.name	= "s3c2410-i2c",
> 	...
> };
> 
> struct platform_device s3c2440_device_i2c {
> 	.name	= "s3c2440-i2c",
> 	...
> };
> 
> And register the corresponding one in your board code (your board code
> knows exactly which one to register, no? )

Yes, this is a recommended way.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center





From eric.y.miao at gmail.com  Wed Jun 23 02:27:49 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 14:27:49 +0800
Subject: [PATCH v2] Introduce 'struct machine_class' for SoC level abstraction
Message-ID: <AANLkTilh-s1C5j1RwKCH1g-N30oEIaoSZVc6OhVGHp5L@mail.gmail.com>

commit d6610443815cb8152023e9859be9ca2f304f2a14
Author: Eric Miao <eric.y.miao at gmail.com>
Date:   Sun Jun 20 21:45:25 2010 +0800

    [ARM] Introduce 'struct machine_class' for SoC level abstraction

    Introduce 'struct machine_class' to group common elements shared by a
    class of machines (i.e. normally SoC level). The elements in 'struct
    machine_desc' will override if provided. (Note zero is considered
    invalid for phys_io, io_pg_offst and boot_params, and if they are
    zero, the version in 'class' will be used)

    Signed-off-by: Eric Miao <eric.miao at canonical.com>

diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index c59842d..28dcc18 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -14,6 +14,25 @@ struct tag;
 struct meminfo;
 struct sys_timer;

+/*
+ * 'struct machine_class' groups the common elements shared by a class
+ * of machines. The elements in 'struct machine_desc' will override if
+ * provided. (Note zero is considered invalid for phys_io, io_pg_offst
+ * and boot_params, and if they are zero, the version in 'class' will
+ * be used)
+ */
+struct machine_class {
+	unsigned int		phys_io;	/* start of physical io	*/
+	unsigned int		io_pg_offst;	/* byte offset for io
+						 * page tabe entry	*/
+	const char		*name;		/* machine class name	*/
+	unsigned long		boot_params;	/* tagged list		*/
+
+	void			(*map_io)(void);/* IO mapping function */
+	void			(*init_irq)(void);
+	struct sys_timer	*timer;
+};
+
 struct machine_desc {
 	/*
 	 * Note! The first four elements are used
@@ -25,6 +44,7 @@ struct machine_desc {
 						 * page tabe entry	*/

 	const char		*name;		/* architecture name	*/
+	struct machine_class	*class;		/* machine class */
 	unsigned long		boot_params;	/* tagged list		*/

 	unsigned int		video_start;	/* start of video RAM	*/
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c
index 8835115..5c9038a 100644
--- a/arch/arm/kernel/asm-offsets.c
+++ b/arch/arm/kernel/asm-offsets.c
@@ -101,6 +101,10 @@ int main(void)
   DEFINE(MACHINFO_NAME,		offsetof(struct machine_desc, name));
   DEFINE(MACHINFO_PHYSIO,	offsetof(struct machine_desc, phys_io));
   DEFINE(MACHINFO_PGOFFIO,	offsetof(struct machine_desc, io_pg_offst));
+  DEFINE(MACHINFO_CLASS,	offsetof(struct machine_desc, class));
+  BLANK();
+  DEFINE(MACHCLASS_PHYSIO,	offsetof(struct machine_class, phys_io));
+  DEFINE(MACHCLASS_PGOFFIO,	offsetof(struct machine_class, io_pg_offst));
   BLANK();
   DEFINE(PROC_INFO_SZ,		sizeof(struct proc_info_list));
   DEFINE(PROCINFO_INITFUNC,	offsetof(struct proc_info_list, __cpu_flush));
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index b9505aa..660756b 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -207,6 +207,7 @@ ENDPROC(lookup_processor_type)
  * Returns:
  *  r3, r4, r6 corrupted
  *  r5 = mach_info pointer in physical address space
+ *  r7 = machine_class pointer in physical address space
  */
 __lookup_machine_type:
 	adr	r3, 4b
@@ -214,6 +215,8 @@ __lookup_machine_type:
 	sub	r3, r3, r4			@ get offset between virt&phys
 	add	r5, r5, r3			@ convert virt addresses to
 	add	r6, r6, r3			@ physical address space
+	ldr	r7, [r5, #MACHINFO_CLASS]	@ get machine class
+	add	r7, r7, r3
 1:	ldr	r3, [r5, #MACHINFO_TYPE]	@ get machine type
 	teq	r3, r1				@ matches loader number?
 	beq	2f				@ found
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index eb62bf9..974d19d 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -82,8 +82,9 @@ ENTRY(stext)
 	bl	__lookup_processor_type		@ r5=procinfo r9=cpuid
 	movs	r10, r5				@ invalid processor (r5=0)?
 	beq	__error_p			@ yes, error 'p'
-	bl	__lookup_machine_type		@ r5=machinfo
+	bl	__lookup_machine_type		@ r5=machinfo,r7=machine_class
 	movs	r8, r5				@ invalid machine (r5=0)?
+	mov	r11, r7
 	beq	__error_a			@ yes, error 'a'
 	bl	__vet_atags
 	bl	__create_page_tables
@@ -211,6 +212,7 @@ ENDPROC(__turn_mmu_on)
  * r8  = machinfo
  * r9  = cpuid
  * r10 = procinfo
+ * r11 = machine_class
  *
  * Returns:
  *  r0, r3, r6, r7 corrupted
@@ -296,12 +298,16 @@ __create_page_tables:
 	 * via a serial console before paging_init.
 	 */
 	ldr	r3, [r8, #MACHINFO_PGOFFIO]
+	cmp	r3, #0				@ use class->io_pg_offst if
+	ldreq	r3, [r11, #MACHCLASS_PGOFFIO]	@ mdesc->io_pg_offst == 0
 	add	r0, r4, r3
 	rsb	r3, r3, #0x4000			@ PTRS_PER_PGD*sizeof(long)
 	cmp	r3, #0x0800			@ limit to 512MB
 	movhi	r3, #0x0800
 	add	r6, r0, r3
 	ldr	r3, [r8, #MACHINFO_PHYSIO]
+	cmp	r3, #0				@ use class->phys_io if
+	ldreq	r3, [r11, #MACHINFO_PHYSIO]	@ mdesc->phys_io == 0
 	orr	r3, r3, r7
 1:	str	r3, [r0], #4
 	add	r3, r3, #1 << 20
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 122d999..b1fa7b2 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -667,12 +667,14 @@ void __init setup_arch(char **cmdline_p)
 {
 	struct tag *tags = (struct tag *)&init_tags;
 	struct machine_desc *mdesc;
+	struct machine_class *class;
 	char *from = default_command_line;

 	unwind_init();

 	setup_processor();
 	mdesc = setup_machine(machine_arch_type);
+	class = mdesc->class;
 	machine_name = mdesc->name;

 	if (mdesc->soft_reboot)
@@ -680,8 +682,13 @@ void __init setup_arch(char **cmdline_p)

 	if (__atags_pointer)
 		tags = phys_to_virt(__atags_pointer);
-	else if (mdesc->boot_params)
-		tags = phys_to_virt(mdesc->boot_params);
+	else {
+		unsigned long boot_params = mdesc->boot_params ?
+					    mdesc->boot_params :
+					   (class ? class->boot_params: 0);
+		if (boot_params)
+			tags = phys_to_virt(boot_params);
+	}

 	/*
 	 * If we have the old style parameters, convert them to
@@ -729,8 +736,10 @@ void __init setup_arch(char **cmdline_p)
 	/*
 	 * Set up various architecture-specific pointers
 	 */
-	init_arch_irq = mdesc->init_irq;
-	system_timer = mdesc->timer;
+	init_arch_irq = mdesc->init_irq ? mdesc->init_irq :
+			(class ? class->init_irq : NULL);
+	system_timer = mdesc->timer ? mdesc->timer :
+			(class ? class->timer : NULL);
 	init_machine = mdesc->init_machine;

 #ifdef CONFIG_VT
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 2858941..e1a4aeb 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -933,6 +933,7 @@ void __init reserve_node_zero(pg_data_t *pgdat)
  */
 static void __init devicemaps_init(struct machine_desc *mdesc)
 {
+	struct machine_class *class = mdesc->class;
 	struct map_desc map;
 	unsigned long addr;
 	void *vectors;
@@ -997,6 +998,10 @@ static void __init devicemaps_init(struct
machine_desc *mdesc)
 	 */
 	if (mdesc->map_io)
 		mdesc->map_io();
+	else {
+		if (class && class->map_io)
+			class->map_io();
+	}

 	/*
 	 * Finally flush the caches and tlb to ensure that we're in a


From m.szyprowski at samsung.com  Wed Jun 23 02:38:39 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 23 Jun 2010 08:38:39 +0200
Subject: [PATCH v2 2/4] ARM: S3C2416: Set name of the framebuffer device
	only if it present
In-Reply-To: <1277220124-16225-3-git-send-email-jekhor@gmail.com>
References: <1277220124-16225-1-git-send-email-jekhor@gmail.com>
	<1277220124-16225-3-git-send-email-jekhor@gmail.com>
Message-ID: <002401cb129e$b93a75a0$2baf60e0$%szyprowski@samsung.com>

Hello,

On Tuesday, June 22, 2010 5:22 PM Yauhen Kharuzhy wrote:

> Fix case when board doesn't have LCD connected and doesn't have
> corresponding platform device compiled.
> 
> Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
> ---
>  arch/arm/mach-s3c2416/s3c2416.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-
> s3c2416/s3c2416.c
> index 35dabcc..355ab62 100644
> --- a/arch/arm/mach-s3c2416/s3c2416.c
> +++ b/arch/arm/mach-s3c2416/s3c2416.c
> @@ -90,7 +90,9 @@ int __init s3c2416_init(void)
>  	s3c_i2c0_setname("s3c2440-i2c");
>  	s3c_i2c1_setname("s3c2440-i2c");
> 
> +#ifdef CONFIG_S3C_DEV_FB
>  	s3c_device_fb.name = "s3c2443-fb";
> +#endif

The above line should be rather removed completely in favor of a
solution proposed by Pawel Osciak in his s3c-fb patches:
http://www.spinics.net/lists/arm-kernel/msg90906.html

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center





From s.hauer at pengutronix.de  Wed Jun 23 02:47:07 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 23 Jun 2010 08:47:07 +0200
Subject: [PATCH 0/5] mtd: mxc_nand fixups
In-Reply-To: <80ljacb7l8.fsf@merkur.tec.linutronix.de>
References: <80ljacb7l8.fsf@merkur.tec.linutronix.de>
Message-ID: <20100623064707.GN12115@pengutronix.de>

On Fri, Jun 18, 2010 at 06:58:59PM +0200, John Ogness wrote:
> Hi,
> 
> The following 5 patches fix several issues with the MXC NFC
> driver. These changes were tested using an i.MX35 with a 16-bit flash
> chip (2K pages, 64 pages per eraseblock).

All Acked-by: Sascha Hauer <s.hauer at pengutronix.de>

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Wed Jun 23 02:59:14 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Wed, 23 Jun 2010 08:59:14 +0200
Subject: [PATCH V2 1/2] mxc: add common debug board for 3-stack platforms
In-Reply-To: <1277216851-15782-2-git-send-email-jason77.wang@gmail.com>
References: <1277216851-15782-1-git-send-email-jason77.wang@gmail.com>
	<1277216851-15782-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <20100623065914.GO12115@pengutronix.de>

On Tue, Jun 22, 2010 at 10:27:30PM +0800, Jason Wang wrote:
> The debug board is little different for all mxc 3-stack(PDK)
> platforms, it is possible here to add a common implementation to
> support this board.
> 
> +
> +void __init mxc_expio_lan_init(void)
> +{
> +	platform_device_register(&smsc_lan9217_device);
> +}

What do we need this for? Can't we just call this from
mxc_expio_init()?


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From tony at atomide.com  Wed Jun 23 03:28:55 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 23 Jun 2010 10:28:55 +0300
Subject: Samsung SoCs: preparation for single kernel
In-Reply-To: <AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com>
References: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com>
	<AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com>
Message-ID: <20100623072855.GZ12255@atomide.com>

* Eric Miao <eric.y.miao at gmail.com> [100623 03:48]:
> On Wed, Jun 23, 2010 at 7:27 AM, Kyungmin Park <kmpark at infradead.org> wrote:
> > To Ben,
> >
> > I really need single kernel for s5pc110 (cortex A8) and s5pc210
> > (cortex A9) at least.
> > Fortunately arm move to these approaches recently. but current Samsung
> > SoCs not prepare these one.
> >
> > So I wonder do you have a plan or how to address these issues?
> > How to assign the address at resources and use it at runtime?
> >
> > Personally I want to use cpu_is_*. but you reject it to use.
> > Other way is that we can create the base address variables and assign
> > it at init time.
> >
> > Please give your opinions.
> >
> > Thank you,
> > Kyungmin Park
> >
> > e.g., cpu_is_* usage at OMAP tree
> >
> > static void omap_init_mcspi(void)
> > {
> > ? ? ? ?if (cpu_is_omap44xx())
> > ? ? ? ? ? ? ? ?omap4_mcspi_fixup();
> >
> > ? ? ? ?platform_device_register(&omap2_mcspi1);
> > ? ? ? ?platform_device_register(&omap2_mcspi2);
> >
> > ? ? ? ?if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
> > ? ? ? ? ? ? ? ?omap2_mcspi3_init();
> >
> > ? ? ? ?if (cpu_is_omap343x() || cpu_is_omap44xx())
> > ? ? ? ? ? ? ? ?omap2_mcspi4_init();
> > }
> 
> Just my two cents: cpu_is_*() can be used, but only when absolutely necessary.
> The s3c does a CPU detection at startup, so I guess the usage of cpu_is_*()
> can be even reduced.
> 
> I'm not sure if the above case is a good reference or not. The omap_init_mcspi
> is called from omap2_init_devices(), while the registration can actually be
> made into the board init code when that device is used (some of the McSPIs are
> not used, and it's not necessary to register them), and the differences be
> handled in the driver.

Few comments regarding the cpu_is_omap macros: The macros should really be
soc_is_omapxxxx() instead cpu_is_omapxxxx().

Also, sprinkling these too much makes the code messy and hard to patch for
new processors. So you should limit the use to very selected places during
init, then set some flag like OMAP_HAS_MCSPI2 | OMAP_HAS_MCSPI3 or something
similar.

Regards,

Tony


From ivo.clarysse at gmail.com  Wed Jun 23 03:34:55 2010
From: ivo.clarysse at gmail.com (Ivo Clarysse)
Date: Wed, 23 Jun 2010 09:34:55 +0200
Subject: [PATCHv3 4/5] mtd: mxc_nand fixups
In-Reply-To: <80iq5bqd07.fsf_-_@merkur.tec.linutronix.de>
References: <804oh0b7gx.fsf@merkur.tec.linutronix.de>
	<20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
	<AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
	<80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTikRj_dMkKLyFhW78yld9jIYAIFncfPaPAF8WqUY@mail.gmail.com>
	<80iq5bqd07.fsf_-_@merkur.tec.linutronix.de>
Message-ID: <AANLkTimJKNEwOoKldq4a4_ufxNY6IY7r6tAfAM055hlW@mail.gmail.com>

On Tue, Jun 22, 2010 at 5:54 PM, John Ogness <john.ogness at linutronix.de> wrote:
> The v2 version of this patch has 2 problems. I believe that this new
> version addresses the problems and still respects the strange behavior
> of the i.MX21.

Unfortunately, this breaks i.MX21 support.

With this patch, the driver gets stuck at the first send_addr() invocation:


barebox 2010.06.0-00202-gc2db375-dirty (Jun 21 2010 - 11:06:13)

Board: Freescale i.MX21 ADS
cfi_probe: cfi_flash base: 0xc8000000 size: 0x02000000
NAND device: Manufacturer ID: 0xec, Chip ID: 0x36 (Samsung NAND 64MiB
1,8V 8-bit)
Scanning device for bad blocks
Bad eraseblock 2133 at 0x02154000
CS8900A Rev. F (PID: 0x0a00) found at 0xcc000000
got MAC address from EEPROM: 00:04:9F:00:25:5C
Malloc space: 0xc0c00000 -> 0xc1000000 (size  4 MB)
Stack space : 0xc0bf8000 -> 0xc0c00000 (size 32 kB)
Open /dev/env0 No such file or directory
no valid environment found on /dev/env0. Using default environment
running /env/bin/init...
barebox:/ nand_parts="256k(barebox)ro,128k(bareboxenv),2176k(kernel),-(root)"
barebox:/ addpart /dev/nand0 $nand_parts
barebox:/ nand -a /dev/nand0.kernel
barebox:/ bootargs="console=ttymxc0,115200"
barebox:/ bootz /dev/nand0.kernel.bb
loaded zImage from /dev/nand0.kernel.bb with size 1696652
Uncompressing Linux... done, booting the kernel.
Linux version 2.6.35-rc3 (ycl at maestro-ycl-quad) (gcc version 4.4.1
(Sourcery G++ Lite 2010q1-202) ) #6 PREEMPT Wed Jun 23 09:11:46 CEST
2010
CPU: ARM926EJ-S [41069264] revision 4 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: Freescale i.MX21ADS
Memory policy: ECC disabled, Data cache writeback
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 16256
Kernel command line: console=ttymxc0,115200
PID hash table entries: 256 (order: -2, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 64MB = 64MB total
Memory: 61776k/61776k available, 3760k reserved, 0K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    DMA     : 0xffc00000 - 0xffe00000   (   2 MB)
    vmalloc : 0xc4800000 - 0xf4000000   ( 760 MB)
    lowmem  : 0xc0000000 - 0xc4000000   (  64 MB)
    modules : 0xbf000000 - 0xc0000000   (  16 MB)
      .init : 0xc0008000 - 0xc0021000   ( 100 kB)
      .text : 0xc0021000 - 0xc02dc000   (2796 kB)
      .data : 0xc02ee000 - 0xc0309160   ( 109 kB)
Hierarchical RCU implementation.
	RCU-based detection of stalled CPUs is disabled.
	Verbose stalled-CPUs detection is disabled.
NR_IRQS:272
MXC GPIO hardware
MXC IRQ initialized
Console: colour dummy device 80x30
Calibrating delay loop... 131.89 BogoMIPS (lpj=659456)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
NET: Registered protocol family 16
bio: create slab <bio-0> at 0
Switching to clocksource mxc_timer1
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
JFFS2 version 2.2. (NAND) ? 2001-2006 Red Hat, Inc.
msgmni has been set to 120
io scheduler noop registered (default)
imx-fb imx-fb.0: i.MX Framebuffer driver
Console: switching to colour frame buffer device 30x40
Serial: 8250/16550 driver, 1 ports, IRQ sharing disabled
Serial: IMX driver
imx-uart.0: ttymxc0 at MMIO 0x1000a000 (irq = 20) is a IMX
console [ttymxc0] enabled
imx-uart.2: ttymxc2 at MMIO 0x1000c000 (irq = 18) is a IMX
imx-uart.3: ttymxc3 at MMIO 0x1000d000 (irq = 17) is a IMX
physmap platform flash device: 02000000 at c8000000
physmap-flash.0: Found 2 x16 devices at 0x0 in 32-bit bank
Amd/Fujitsu Extended Query Table at 0x0040
physmap-flash.0: CFI contains unrecognised boot bank location (1).
Assuming bottom.
number of CFI chips: 1
Searching for RedBoot partition table in physmap-flash.0 at offset 0x1fe0000
No RedBoot partition table detected in physmap-flash.0
mtd: Giving out device 0 to physmap-flash.0
mxc_nand_command (cmd = 0xff, col = 0xffffffff, page = 0xffffffff)
send_cmd(host, 0xff, 0)
mxc_nand_command (cmd = 0x90, col = 0x0, page = 0xffffffff)
send_cmd(host, 0x90, 1)
send_addr(host, 0x0 1)


Setting NFC_CONFIG1:NFC_INT_MSK in the interrupt handler causes
NFC_CONFIG2:NFC_INT to always read out 0 (on i.MX21), causing

           wait_event(host->irq_waitq,
                        readw(host->regs + NFC_CONFIG2) & NFC_INT);

to wait forever.


From eric.y.miao at gmail.com  Wed Jun 23 03:36:46 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 15:36:46 +0800
Subject: Samsung SoCs: preparation for single kernel
In-Reply-To: <20100623072855.GZ12255@atomide.com>
References: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com> 
	<AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com> 
	<20100623072855.GZ12255@atomide.com>
Message-ID: <AANLkTinYTm-AZDXOSvtTptGg1HYhKfItYYW8tBuF4SPV@mail.gmail.com>

On Wed, Jun 23, 2010 at 3:28 PM, Tony Lindgren <tony at atomide.com> wrote:
> * Eric Miao <eric.y.miao at gmail.com> [100623 03:48]:
>> On Wed, Jun 23, 2010 at 7:27 AM, Kyungmin Park <kmpark at infradead.org> wrote:
>> > To Ben,
>> >
>> > I really need single kernel for s5pc110 (cortex A8) and s5pc210
>> > (cortex A9) at least.
>> > Fortunately arm move to these approaches recently. but current Samsung
>> > SoCs not prepare these one.
>> >
>> > So I wonder do you have a plan or how to address these issues?
>> > How to assign the address at resources and use it at runtime?
>> >
>> > Personally I want to use cpu_is_*. but you reject it to use.
>> > Other way is that we can create the base address variables and assign
>> > it at init time.
>> >
>> > Please give your opinions.
>> >
>> > Thank you,
>> > Kyungmin Park
>> >
>> > e.g., cpu_is_* usage at OMAP tree
>> >
>> > static void omap_init_mcspi(void)
>> > {
>> > ? ? ? ?if (cpu_is_omap44xx())
>> > ? ? ? ? ? ? ? ?omap4_mcspi_fixup();
>> >
>> > ? ? ? ?platform_device_register(&omap2_mcspi1);
>> > ? ? ? ?platform_device_register(&omap2_mcspi2);
>> >
>> > ? ? ? ?if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
>> > ? ? ? ? ? ? ? ?omap2_mcspi3_init();
>> >
>> > ? ? ? ?if (cpu_is_omap343x() || cpu_is_omap44xx())
>> > ? ? ? ? ? ? ? ?omap2_mcspi4_init();
>> > }
>>
>> Just my two cents: cpu_is_*() can be used, but only when absolutely necessary.
>> The s3c does a CPU detection at startup, so I guess the usage of cpu_is_*()
>> can be even reduced.
>>
>> I'm not sure if the above case is a good reference or not. The omap_init_mcspi
>> is called from omap2_init_devices(), while the registration can actually be
>> made into the board init code when that device is used (some of the McSPIs are
>> not used, and it's not necessary to register them), and the differences be
>> handled in the driver.
>
> Few comments regarding the cpu_is_omap macros: The macros should really be
> soc_is_omapxxxx() instead cpu_is_omapxxxx().

Right, that will be more specific. cpu_is_* could be used only
with the ARM core, like cpu_is_arm946ejs(), ... And apparently
we all have abusively used it :-)

>
> Also, sprinkling these too much makes the code messy and hard to patch for
> new processors. So you should limit the use to very selected places during
> init, then set some flag like OMAP_HAS_MCSPI2 | OMAP_HAS_MCSPI3 or something
> similar.

Exactly.


From tony at atomide.com  Wed Jun 23 03:39:13 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 23 Jun 2010 10:39:13 +0300
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100622170020.GF4371@shareable.org>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
Message-ID: <20100623073912.GA12255@atomide.com>

* Jamie Lokier <jamie at shareable.org> [100622 19:54]:
> Tony Lindgren wrote:
> >  __kuser_get_tls:				@ 0xffff0fe0
> > -
> > -#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
> > -	ldr	r0, [pc, #(16 - 8)]		@ TLS stored at 0xffff0ff0
> > -#else
> > -	mrc	p15, 0, r0, c13, c0, 3		@ read TLS register
> > -#endif
> > +	ldr     r0, [pc, #(20 - 8)]		@ software TLS set in 0xffff0ff4?
> > +	cmp	r0, #0				@ hardware TLS if flag not set
> > +	mrceq	p15, 0, r0, c13, c0, 3		@ read hardware TLS register
> > +	ldrne	r0, [pc, #(12 - 8)]		@ software TLS val at 0xffff0ff8
> >  	usr_ret	lr
> > -
> > -	.rep	5
> > -	.word	0			@ pad up to __kuser_helper_version
> > -	.endr
> > +	.word	0				@ non-zero for software TLS
> > +	.word	0				@ software TLS value
> 
> It'd be nice not to waste instructions checking for HWCAP_TLS on archs
> which definitely don't have it.  I guess it doesn't matter elsewhere;
> I'd expect this to be a warm path for some programs making extensive
> use of TLS (I haven't measured though).

OK, but let's try to figure out a way that does not add more ifdef else
code as that makes it harder to build support for multiple ARM cores.
 
> As it's only a single instruction, and the code is in a writable page
> already (copied at init), how about just patching the instruction
> when ELF_HWCAP is set?

Yeah that can be done for __kuser_get_tls if it's always writable.
But __switch_to is trickier because of the CONFIG_MMU ifdefs there.

What if we have optional __switch_to and __kuser_get_tls implementations
in the mm/proc-*.S files that get copied over the current locations
if implemented?

Regards,

Tony


From kgene.kim at samsung.com  Wed Jun 23 03:50:32 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 23 Jun 2010 16:50:32 +0900
Subject: [PATCH v2 0/4] ARM: S5P: Support gpio interrupts
In-Reply-To: <4C11F4CA.10802@samsung.com>
References: <4C11F4CA.10802@samsung.com>
Message-ID: <004601cb12a8$c869e560$593db020$%kim@samsung.com>

Joonyoung Shim wrote:
> 
> This patch v2 set is to support gpio interrupts of samsung s5p cpus, and
> the GPIOlib gpio_to_irq goes to plat-samsung gpiolib, so patch v2 set
> has four commit smaller than v1.
> 
> Changes since v1:
> - Add irq_base to s3c_gpio_chip struct
> - GPIOlib gpio_to_irq() is implemented to samsung_gpiolib_to_irq() of
>   plat-samsung gpiolib
> 
> Joonyoung Shim (4):
>       ARM: S5PV210: Add gpio interrupt support
>       ARM: S5PC100: Use S5P gpio interrupts interface
>       ARM: S5PC100: Move external interrupt defines
>       ARM: SAMSUNG: Add GPIOlib gpio_to_irq
> 
>  arch/arm/mach-s5pc100/Makefile                 |    2 +-
>  arch/arm/mach-s5pc100/gpiolib.c                |   70 ++-----
>  arch/arm/mach-s5pc100/include/mach/gpio.h      |    7 -
>  arch/arm/mach-s5pc100/include/mach/irqs.h      |   18 ++-
>  arch/arm/mach-s5pc100/include/mach/regs-gpio.h |    7 +
>  arch/arm/mach-s5pc100/irq-gpio.c               |  266
------------------------
>  arch/arm/mach-s5pv210/gpiolib.c                |   18 ++-
>  arch/arm/mach-s5pv210/include/mach/irqs.h      |   16 ++-
>  arch/arm/plat-s5p/Makefile                     |    2 +-
>  arch/arm/plat-s5p/irq-gpioint.c                |  208 ++++++++++++++++++
>  arch/arm/plat-samsung/gpiolib.c                |    9 +
>  arch/arm/plat-samsung/include/plat/gpio-core.h |    6 +
>  12 files changed, 295 insertions(+), 334 deletions(-)
>  delete mode 100644 arch/arm/mach-s5pc100/irq-gpio.c
>  create mode 100644 arch/arm/plat-s5p/irq-gpioint.c
> 

I am sure this patchset is working code, but Ben had made suggestion about
'sparse irq'...
It is because there are too many gpio interrupts and having support of all
of them is unnecessary as realistically only few of them maybe used.
In fact in SMDK board there is no use of gpio in interrupt mode.

Ben, I remember your suggestion for using 'sparse irq' for handling gpio
interrupts.
And in fact, sparse irq implementation can be beneficial to many other
boards...
Could you please explain about that?


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From tony at atomide.com  Wed Jun 23 03:57:03 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 23 Jun 2010 10:57:03 +0300
Subject: [PATCH 2/2] arm: Make VFPv3 usable on ARMv6
In-Reply-To: <20100622132037.GV12255@atomide.com>
References: <20100621135125.24299.91290.stgit@baageli.muru.com>
	<1277211592.29532.20.camel@e102109-lin.cambridge.arm.com>
	<20100622132037.GV12255@atomide.com>
Message-ID: <20100623075703.GB12255@atomide.com>

* Tony Lindgren <tony at atomide.com> [100622 16:15]:
> * Catalin Marinas <catalin.marinas at arm.com> [100622 15:53]:
> > On Mon, 2010-06-21 at 14:51 +0100, Tony Lindgren wrote:
> > > diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
> > > index 315a540..19ba626 100644
> > > --- a/arch/arm/vfp/vfpmodule.c
> > > +++ b/arch/arm/vfp/vfpmodule.c
> > > @@ -549,10 +549,14 @@ static int __init vfp_init(void)
> > >                 /*
> > >                  * Check for the presence of the Advanced SIMD
> > >                  * load/store instructions, integer and single
> > > -                * precision floating point operations.
> > > +                * precision floating point operations. Only check
> > > +                * for NEON if the hardware has TLS register as the
> > > +                * MVFR registers got added in ARM1136 r1p0 with TLS.
> > >                  */
> > > -               if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
> > > -                       elf_hwcap |= HWCAP_NEON;
> > > +               if (elf_hwcap & HWCAP_TLS) {
> > > +                       if ((fmrx(MVFR1) & 0x000fff00) == 0x00011100)
> > > +                               elf_hwcap |= HWCAP_NEON;
> > > +               }
> > 
> > MVFR should be available with the new CPU id format:
> > 
> > 	((read_cpuid_id() & 0x000f0000) == 0x000f0000)
> > 
> > I think that would be a cleaner test than relying on the TLS presence.
> 
> OK, thanks that's better. Will update accordingly and repost.

Here's this one updated. Using your better MVFR check also removes the
dependency to the previous patch.

Regards,

Tony
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From kgene.kim at samsung.com  Wed Jun 23 03:58:08 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 23 Jun 2010 16:58:08 +0900
Subject: [PATCH v2] S5PV210 Correct clock register properties
In-Reply-To: <AANLkTikd6KFVMYKVuCII7KFhoDxAq4jA1Pe7S25gF-ml@mail.gmail.com>
References: <1277193951-22559-1-git-send-email-myungjoo.ham@samsung.com>
	<002c01cb1293$ffe373e0$ffaa5ba0$%kim@samsung.com>
	<AANLkTikd6KFVMYKVuCII7KFhoDxAq4jA1Pe7S25gF-ml@mail.gmail.com>
Message-ID: <004701cb12a9$d6f67480$84e35d80$%kim@samsung.com>

MyungJoo Ham wrote:
> 
> On Wed, Jun 23, 2010 at 2:21 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > MyungJoo Ham wrote:
> >>
> >> Note that this patch revises and merges the two previous patches:
> >> [PATCH] S5PV210 Correct clock register properties
> >> [PATCH] S5PV210 Correct clock source control register properties
> >>
> >> 1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which
> > were
> >> defined incorrectly.
> >>
> >> 2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc,
> >> sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their
> >> twins defined in struct clk init_clocks_disable[] and struct clk
> >> init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK
> >> register to avoid the duplicated clock problem described below.
> >>
> >> --- Duplicated Clock Problem ---
> >> Please note that each clock definition should access different control
> >> register; otherwise, the system may suffer lockups. For example, if we
> >> have two clock definitions "a" and "b" which access the same register
> >> (and the shift value). Then, when we do:
> >>
> >>       module A
> >>       clk = clk_get("a");
> >>       clk->clk_enable(clk);
> >>
> >>       module B (context switch)
> >>       clk = clk_get("b");
> >>       clk->clk_enable(clk);
> >>       do something with clk.
> >>       clk->clk_disable(clk);
> >>
> >>       module A (context switch)
> >>       do something with clk
> >>       * At this point, the system may hang.
> >>
> >> Therefore, there should be no clock definitions with the same contol
> >> register/shift. If we need to create "aliases", then, creating child
> >> clocks sharing the clock should be fine.
> >>
> >> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> >> ---
> >>  arch/arm/mach-s5pv210/clock.c |   72
> > ++++++++++++++++++++--------------------
> >>  1 files changed, 36 insertions(+), 36 deletions(-)
> >>
> >> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> >> index 154bca4..10a9f84 100644
> >> --- a/arch/arm/mach-s5pv210/clock.c
> >> +++ b/arch/arm/mach-s5pv210/clock.c
> >> @@ -406,13 +406,13 @@ static struct clk init_clocks_disable[] = {
> >>               .id             = 0,
> >>               .parent         = &clk_p,
> >>               .enable         = s5pv210_clk_ip3_ctrl,
> >> -             .ctrlbit        = (1<<4),
> >> +             .ctrlbit        = (1<<5),
> >
> > If possible, please add space between <<, like (1 << 5)
> 
> Ok, then, we'll probably need to modify almost every clk definition in
> this file as most of shift operators don't have spaces around them. Do
> you still want to do so?
> 
I mean just about modified stuff in here.
So right now, no need additional work for others.

> >
> >>       }, {
> >>               .name           = "i2s_v32",
> >>               .id             = 1,
> >>               .parent         = &clk_p,
> >>               .enable         = s5pv210_clk_ip3_ctrl,
> >> -             .ctrlbit        = (1<<4),
> >> +             .ctrlbit        = (1<<6),
> >>       }
> >>  };
> >>
> >> @@ -429,25 +429,25 @@ static struct clk init_clocks[] = {
> >>               .id             = 0,
> >>               .parent         = &clk_pclk_psys.clk,
> >>               .enable         = s5pv210_clk_ip3_ctrl,
> >> -             .ctrlbit        = (1<<7),
> >> +             .ctrlbit        = (1<<17),
> >>       }, {
> >>               .name           = "uart",
> >>               .id             = 1,
> >>               .parent         = &clk_pclk_psys.clk,
> >>               .enable         = s5pv210_clk_ip3_ctrl,
> >> -             .ctrlbit        = (1<<8),
> >> +             .ctrlbit        = (1<<18),
> >>       }, {
> >>               .name           = "uart",
> >>               .id             = 2,
> >>               .parent         = &clk_pclk_psys.clk,
> >>               .enable         = s5pv210_clk_ip3_ctrl,
> >> -             .ctrlbit        = (1<<9),
> >> +             .ctrlbit        = (1<<19),
> >>       }, {
> >>               .name           = "uart",
> >>               .id             = 3,
> >>               .parent         = &clk_pclk_psys.clk,
> >>               .enable         = s5pv210_clk_ip3_ctrl,
> >> -             .ctrlbit        = (1<<10),
> >> +             .ctrlbit        = (1<<20),
> >>       },
> >>  };
> >>
> >> @@ -565,8 +565,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
> >>       .clk            = {
> >>               .name           = "sclk_audio",
> >>               .id             = 0,
> >> -             .enable         = s5pv210_clk_ip3_ctrl,
> >> -             .ctrlbit        = (1 << 4),
> >> +             .enable         = s5pv210_clk_mask0_ctrl,
> >> +             .ctrlbit        = (1 << 24),
> >>       },
> >>       .sources = &clkset_sclk_audio0,
> >>       .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
> >> @@ -594,8 +594,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
> >>       .clk            = {
> >>               .name           = "sclk_audio",
> >>               .id             = 1,
> >> -             .enable         = s5pv210_clk_ip3_ctrl,
> >> -             .ctrlbit        = (1 << 5),
> >> +             .enable         = s5pv210_clk_mask0_ctrl,
> >> +             .ctrlbit        = (1 << 25),
> >>       },
> >>       .sources = &clkset_sclk_audio1,
> >>       .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
> >> @@ -623,8 +623,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
> >>       .clk            = {
> >>               .name           = "sclk_audio",
> >>               .id             = 2,
> >> -             .enable         = s5pv210_clk_ip3_ctrl,
> >> -             .ctrlbit        = (1 << 6),
> >> +             .enable         = s5pv210_clk_mask0_ctrl,
> >> +             .ctrlbit        = (1 << 26),
> >>       },
> >>       .sources = &clkset_sclk_audio2,
> >>       .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
> >> @@ -680,8 +680,8 @@ static struct clksrc_clk clksrcs[] = {
> >>               .clk    = {
> >>                       .name           = "uclk1",
> >>                       .id             = 0,
> >> -                     .ctrlbit        = (1<<17),
> >> -                     .enable         = s5pv210_clk_ip3_ctrl,
> >> +                     .enable         = s5pv210_clk_mask0_ctrl,
> >> +                     .ctrlbit        = (1 << 12),
> >>               },
> >>               .sources = &clkset_uart,
> >>               .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
> >> @@ -690,8 +690,8 @@ static struct clksrc_clk clksrcs[] = {
> >>               .clk            = {
> >>                       .name           = "uclk1",
> >>                       .id             = 1,
> >> -                     .enable         = s5pv210_clk_ip3_ctrl,
> >> -                     .ctrlbit        = (1 << 18),
> >> +                     .enable         = s5pv210_clk_mask0_ctrl,
> >> +                     .ctrlbit        = (1 << 13),
> >>               },
> >>               .sources = &clkset_uart,
> >>               .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
> >> @@ -700,8 +700,8 @@ static struct clksrc_clk clksrcs[] = {
> >>               .clk            = {
> >>                       .name           = "uclk1",
> >>                       .id             = 2,
> >> -                     .enable         = s5pv210_clk_ip3_ctrl,
> >> -                     .ctrlbit        = (1 << 19),
> >> +                     .enable         = s5pv210_clk_mask0_ctrl,
> >> +                     .ctrlbit        = (1 << 14),
> >>               },
> >>               .sources = &clkset_uart,
> >>               .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
> >> @@ -710,8 +710,8 @@ static struct clksrc_clk clksrcs[] = {
> >>               .clk            = {
> >>                       .name           = "uclk1",
> >>                       .id             = 3,
> >> -                     .enable         = s5pv210_clk_ip3_ctrl,
> >> -                     .ctrlbit        = (1 << 20),
> >> +                     .enable         = s5pv210_clk_mask0_ctrl,
> >> +                     .ctrlbit        = (1 << 15),
> >>               },
> >>               .sources = &clkset_uart,
> >>               .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
> >> @@ -784,8 +784,8 @@ static struct clksrc_clk clksrcs[] = {
> >>               .clk            = {
> >>                       .name           = "sclk_fimd",
> >>                       .id             = -1,
> >> -                     .enable         = s5pv210_clk_ip1_ctrl,
> >> -                     .ctrlbit        = (1 << 0),
> >> +                     .enable         = s5pv210_clk_mask0_ctrl,
> >> +                     .ctrlbit        = (1 << 5),
> >>               },
> >>               .sources = &clkset_group2,
> >>               .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
> >> @@ -794,8 +794,8 @@ static struct clksrc_clk clksrcs[] = {
> >>               .clk            = {
> >>                       .name           = "sclk_mmc",
> >>                       .id             = 0,
> >> -                     .enable         = s5pv210_clk_ip2_ctrl,
> >> -                     .ctrlbit        = (1 << 16),
> >> +                     .enable         = s5pv210_clk_mask0_ctrl,
> >> +                     .ctrlbit        = (1 << 8),
> >>               },
> >>               .sources = &clkset_group2,
> >>               .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
> >> @@ -804,8 +804,8 @@ static struct clksrc_clk clksrcs[] = {
> >>               .clk            = {
> >>                       .name           = "sclk_mmc",
> >>                       .id             = 1,
> >> -                     .enable         = s5pv210_clk_ip2_ctrl,
> >> -                     .ctrlbit        = (1 << 17),
> >> +                     .enable         = s5pv210_clk_mask0_ctrl,
> >> +                     .ctrlbit        = (1 << 9),
> >>               },
> >>               .sources = &clkset_group2,
> >>               .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
> >> @@ -814,8 +814,8 @@ static struct clksrc_clk clksrcs[] = {
> >>               .clk            = {
> >>                       .name           = "sclk_mmc",
> >>                       .id             = 2,
> >> -                     .enable         = s5pv210_clk_ip2_ctrl,
> >> -                     .ctrlbit        = (1 << 18),
> >> +                     .enable         = s5pv210_clk_mask0_ctrl,
> >> +                     .ctrlbit        = (1 << 10),
> >>               },
> >>               .sources = &clkset_group2,
> >>               .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
> >> @@ -824,8 +824,8 @@ static struct clksrc_clk clksrcs[] = {
> >>               .clk            = {
> >>                       .name           = "sclk_mmc",
> >>                       .id             = 3,
> >> -                     .enable         = s5pv210_clk_ip2_ctrl,
> >> -                     .ctrlbit        = (1 << 19),
> >> +                     .enable         = s5pv210_clk_mask0_ctrl,
> >> +                     .ctrlbit        = (1 << 11),
> >>               },
> >>               .sources = &clkset_group2,
> >>               .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
> >> @@ -874,8 +874,8 @@ static struct clksrc_clk clksrcs[] = {
> >>               .clk            = {
> >>                       .name           = "sclk_spi",
> >>                       .id             = 0,
> >> -                     .enable         = s5pv210_clk_ip3_ctrl,
> >> -                     .ctrlbit        = (1 << 12),
> >> +                     .enable         = s5pv210_clk_mask0_ctrl,
> >> +                     .ctrlbit        = (1 << 16),
> >>               },
> >>               .sources = &clkset_group2,
> >>               .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
> >> @@ -884,8 +884,8 @@ static struct clksrc_clk clksrcs[] = {
> >>               .clk            = {
> >>                       .name           = "sclk_spi",
> >>                       .id             = 1,
> >> -                     .enable         = s5pv210_clk_ip3_ctrl,
> >> -                     .ctrlbit        = (1 << 13),
> >> +                     .enable         = s5pv210_clk_mask0_ctrl,
> >> +                     .ctrlbit        = (1 << 17),
> >>               },
> >>               .sources = &clkset_group2,
> >>               .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
> >> @@ -904,8 +904,8 @@ static struct clksrc_clk clksrcs[] = {
> >>               .clk            = {
> >>                       .name           = "sclk_pwm",
> >>                       .id             = -1,
> >> -                     .enable         = s5pv210_clk_ip3_ctrl,
> >> -                     .ctrlbit        = (1 << 23),
> >> +                     .enable         = s5pv210_clk_mask0_ctrl,
> >> +                     .ctrlbit        = (1 << 19),
> >>               },
> >>               .sources = &clkset_group2,
> >>               .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
> >> --
> >
> > Looks good.
> >
> > But missed something such as sclk_dac, sclk_hdmi, sclk_mixer, sclk_fimc,
> > sclk_cam, sclk_csis, and sclk_pwi.
> > Any reason?
> 
> I was going to separate duplicated clocks only in this one and
> modifying sclk_[dac|hdmi|mixer|fimc|cam|csis|pwi] would have required
> to define additional clks. However, if we agree on adding clks for
> [dac|hdmi|mixer|fimc|cam|csis|pwi], I'll add those in the next
> revision (PATCH V3) and let sclk_[dac|hdmi|mixer|fimc|cam|csis|pwi] to
> access MASK registers.
> 
yeah..I see.

That's 'duplicated clock problem' as you commented at once and bug :-(
So should be fixed :-)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From eric.y.miao at gmail.com  Wed Jun 23 04:01:35 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 16:01:35 +0800
Subject: Samsung SoCs: preparation for single kernel
In-Reply-To: <002301cb129c$ec59fe30$c50dfa90$%szyprowski@samsung.com>
References: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com> 
	<AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com> 
	<AANLkTil1i_ZGI8bY14HhjrAk9RooVreAJsTteqqrMgqJ@mail.gmail.com> 
	<AANLkTikDml6gQAsiRrCjIt4bUD3hnpAATr1erqCGOJMd@mail.gmail.com> 
	<002301cb129c$ec59fe30$c50dfa90$%szyprowski@samsung.com>
Message-ID: <AANLkTikspf9zHuSKe86wDQxI12HpJo_occBlLUXBkjef@mail.gmail.com>

On Wed, Jun 23, 2010 at 2:25 PM, Marek Szyprowski
<m.szyprowski at samsung.com> wrote:
> Hello,
>
> On Wednesday, June 23, 2010 3:55 AM Eric Miao wrote:
>
>> ...
>
>> >>> e.g., cpu_is_* usage at OMAP tree
>> >>>
>> >>> static void omap_init_mcspi(void)
>> >>> {
>> >>> ? ? ? ?if (cpu_is_omap44xx())
>> >>> ? ? ? ? ? ? ? ?omap4_mcspi_fixup();
>> >>>
>> >>> ? ? ? ?platform_device_register(&omap2_mcspi1);
>> >>> ? ? ? ?platform_device_register(&omap2_mcspi2);
>> >>>
>> >>> ? ? ? ?if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
>> >>> ? ? ? ? ? ? ? ?omap2_mcspi3_init();
>> >>>
>> >>> ? ? ? ?if (cpu_is_omap343x() || cpu_is_omap44xx())
>> >>> ? ? ? ? ? ? ? ?omap2_mcspi4_init();
>> >>> }
>> >>
>> >> Just my two cents: cpu_is_*() can be used, but only when absolutely
>> necessary.
>> >> The s3c does a CPU detection at startup, so I guess the usage of
>> cpu_is_*()
>> >> can be even reduced.
>> >
>> > My concern is that most device resources use the S3C_* or S5P_* prefix
>> > and defined at each arch differently.
>> >
>> > E.G., mmc resource drivers use the S3C_PA_HSMMC0. but each mach has
>> > different base address.
>> > then how to handle this or make it possible?
>> >
>>
>> Now you have
>>
>> s5pv210_device_hsmmc0
>> s5pc100_device_hsmmc0
>> s3c64xx_device_hsmmc0
>> ....
>>
>> each with a different base.
>
> There is no need for such code duplication.

However, I believe this is the right way to go. A certain level of
duplication is the price to pay for a generic and clean solution.

When a peripheral controller or IP is moved from one SoC to the
next generation, there are several things could have been changed:

1. new base address and IRQ number
2. fixes and enhancements to the original IP

1. will result in a different 'struct resource', and 2. will result in a
different 'struct platform_device' with a different name, so the driver
can match the platform_device_id table as you agreed I'm right on
that recommendation.

They are actually _two_ different devices.

> Ben is working on a solution for
> a single kernel which supports multiple SoCs. Some of his work in progress can
> be found here: git://git.fluff.org/bjdooks/linux branch wip-samsung-dev and
> wip-samsung-dev2.

Could you describe it a bit here and bring it on table for discussion?

PS: My feeling of commenting several of the samsung patches so far turns
out to be quite frustrated, or I'm just too sensitive. NOTE neither am I
NAKing Samsung patches, nor am I interested to be involved, I'm just givin
my suggestions.


From linux at arm.linux.org.uk  Wed Jun 23 04:12:18 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 23 Jun 2010 09:12:18 +0100
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100623073912.GA12255@atomide.com>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
	<20100623073912.GA12255@atomide.com>
Message-ID: <20100623081218.GA16385@n2100.arm.linux.org.uk>

On Wed, Jun 23, 2010 at 10:39:13AM +0300, Tony Lindgren wrote:
> Yeah that can be done for __kuser_get_tls if it's always writable.
> But __switch_to is trickier because of the CONFIG_MMU ifdefs there.

And impossible with XIP kernels.

> What if we have optional __switch_to and __kuser_get_tls implementations
> in the mm/proc-*.S files that get copied over the current locations
> if implemented?

Also problematical with XIP - if we go down the route of implementing
these by copying code fragments into the kernel, we need to strip out
XIP support or implement a second way.  Obviously having a second way
adds maintainence burden, and the second way will probably lose out
on updates.


From john.ogness at linutronix.de  Wed Jun 23 04:48:41 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Wed, 23 Jun 2010 10:48:41 +0200
Subject: [PATCHv3 4/5] mtd: mxc_nand fixups
In-Reply-To: <AANLkTimJKNEwOoKldq4a4_ufxNY6IY7r6tAfAM055hlW@mail.gmail.com>
	(Ivo Clarysse's message of "Wed, 23 Jun 2010 09:34:55 +0200")
References: <804oh0b7gx.fsf@merkur.tec.linutronix.de>
	<20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
	<AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
	<80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTikRj_dMkKLyFhW78yld9jIYAIFncfPaPAF8WqUY@mail.gmail.com>
	<80iq5bqd07.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTimJKNEwOoKldq4a4_ufxNY6IY7r6tAfAM055hlW@mail.gmail.com>
Message-ID: <80vd9ab0d2.fsf@merkur.tec.linutronix.de>

On 2010-06-23, Ivo Clarysse <ivo.clarysse at gmail.com> wrote:
> Unfortunately, this breaks i.MX21 support.
>
> With this patch, the driver gets stuck at the first send_addr()
> invocation:
>
> [...]
>
> Setting NFC_CONFIG1:NFC_INT_MSK in the interrupt handler causes
> NFC_CONFIG2:NFC_INT to always read out 0 (on i.MX21), causing
>
>     wait_event(host->irq_waitq,
>                readw(host->regs + NFC_CONFIG2) & NFC_INT);
>
> to wait forever.

OK. Now I understand the problem. Here is a new patch that introduces a
flag that is set by the interrupt handler. This way we do not rely on
the i.MX21 being able to read NFC_INT when the interrupt is masked.

I have also added a lot of comments so that it is (hopefully) clear why
we are enabling and disabling the irq line rather than only masking and
unmasking the interrupt.

The patch is against linux-next 20100618.

Signed-off-by: John Ogness <john.ogness at linutronix.de>
---
 drivers/mtd/nand/mxc_nand.c |   49 +++++++++++++++++++++++++++++-----
 1 file changed, 42 insertions(+), 7 deletions(-)

Index: linux-next-20100618/drivers/mtd/nand/mxc_nand.c
===================================================================
--- linux-next-20100618.orig/drivers/mtd/nand/mxc_nand.c
+++ linux-next-20100618/drivers/mtd/nand/mxc_nand.c
@@ -30,6 +30,7 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/irq.h>
 
 #include <asm/mach/flash.h>
 #include <mach/mxc_nand.h>
@@ -117,6 +118,7 @@ struct mxc_nand_host {
 	int			clk_act;
 	int			irq;
 
+	int			nfc_int;
 	wait_queue_head_t	irq_waitq;
 
 	uint8_t			*data_buf;
@@ -173,8 +175,21 @@ static const char *part_probes[] = { "Re
 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 {
 	struct mxc_nand_host *host = dev_id;
+	uint16_t tmp;
+
+	/* If NFC_INT is not set, we have a spurious interrupt! */
+	if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0)
+		return IRQ_NONE;
+
+	/* We use the host->nfc_int flag because the i.MX21 cannot
+	 * read the CONFIG2:NFC_INT bit if interrupts are masked. */
+	host->nfc_int = 1;
 
-	disable_irq_nosync(irq);
+	/* Mask the interrupts so that we avoid an interrupt
+	 * flood until the irq line is disabled. */
+	tmp = readw(host->regs + NFC_CONFIG1);
+	tmp |= NFC_INT_MSK;
+	writew(tmp, host->regs + NFC_CONFIG1);
 
 	wake_up(&host->irq_waitq);
 
@@ -192,15 +207,33 @@ static void wait_op_done(struct mxc_nand
 	if (useirq) {
 		if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
 
+			/* Clear the interrupt flag. It will be set
+			 * by the interrupt handler. */
+			host->nfc_int = 0;
+
+			/* We enable the irq line and wait for an interrupt.
+			 * We must use irq line enable/disable rather than
+			 * simply masking of the interrupt because the i.MX21
+			 * cannot read the CONFIG2:NFC_INT bit if the
+			 * interrupt is masked. This is also the reason we
+			 * use the host->nfc_int flag. */
 			enable_irq(host->irq);
 
-			wait_event(host->irq_waitq,
-				readw(host->regs + NFC_CONFIG2) & NFC_INT);
+			wait_event(host->irq_waitq, host->nfc_int);
+
+			disable_irq(host->irq);
 
-			tmp = readw(host->regs + NFC_CONFIG2);
-			tmp  &= ~NFC_INT;
-			writew(tmp, host->regs + NFC_CONFIG2);
+			/* The irq line has been disabled. We can now
+			 * unmask the interrupts. */
+			tmp = readw(host->regs + NFC_CONFIG1);
+			tmp &= ~NFC_INT_MSK;
+			writew(tmp, host->regs + NFC_CONFIG1);
 		}
+
+		/* clear interrupt flag */
+		tmp = readw(host->regs + NFC_CONFIG2);
+		tmp &= ~NFC_INT;
+		writew(tmp, host->regs + NFC_CONFIG2);
 	} else {
 		while (max_retries-- > 0) {
 			if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
@@ -846,7 +879,9 @@ static int __init mxcnd_probe(struct pla
 
 	host->irq = platform_get_irq(pdev, 0);
 
-	err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
+	/* request irq as disabled */
+	set_irq_flags(host->irq, IRQF_VALID | IRQF_NOAUTOEN);
+	err = request_irq(host->irq, mxc_nfc_irq, 0, DRIVER_NAME, host);
 	if (err)
 		goto eirq;
 


From myungjoo.ham at samsung.com  Wed Jun 23 05:01:28 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Wed, 23 Jun 2010 18:01:28 +0900
Subject: [PATCH v3] S5PV210 Correct clock register properties
Message-ID: <1277283688-4542-1-git-send-email-myungjoo.ham@samsung.com>

1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which were
defined incorrectly.

2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc,
sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their
twins defined in struct clk init_clocks_disable[] and struct clk
init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK
register to avoid the duplicated clock problem described below.

--- Duplicated Clock Problem ---
Please note that each clock definition should access different control
register; otherwise, the system may suffer lockups. For example, if we
have two clock definitions "a" and "b" which access the same register
(and the shift value). Then, when we do:

	module A
	clk = clk_get("a");
	clk->clk_enable(clk);

	module B (context switch)
	clk = clk_get("b");
	clk->clk_enable(clk);
	do something with clk.
	clk->clk_disable(clk);

	module A (context switch)
	do something with clk
	* At this point, the system may hang.

Therefore, there should be no clock definitions with the same contol
register/shift. If we need to create "aliases", then, creating child
clocks sharing the clock should be fine.

3. Added struct clk for clock gating (CLK_GATE_IPx) of the clksrc_clk's
which were accessing CLK_GATE_IP and modified to access CLK_SRC_MASK

Note that this patch revises and merges the two previous patches:
[PATCH] S5PV210 Correct clock register properties
[PATCH] S5PV210 Correct clock source control register properties
And follows the previous patch
[PATCH v2] S5PV210 Correct clock register properties

Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pv210/clock.c |  158 +++++++++++++++++++++++++++--------------
 1 files changed, 105 insertions(+), 53 deletions(-)

diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 154bca4..fd76e78 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -270,12 +270,54 @@ static struct clk_ops clk_hclk_imem_ops = {
 
 static struct clk init_clocks_disable[] = {
 	{
+		.name		= "csis",
+		.id		= -1,
+		.parent		= &clk_pclk_dsys.clk,
+		.enable		= s5pv210_clk_ip0_ctrl,
+		.ctrlbit	= (1 << 31),
+	}, {
 		.name		= "rot",
 		.id		= -1,
 		.parent		= &clk_hclk_dsys.clk,
 		.enable		= s5pv210_clk_ip0_ctrl,
 		.ctrlbit	= (1<<29),
 	}, {
+		.name		= "fimc",
+		.id		= 0,
+		.parent		= &clk_hclk_dsys.clk,
+		.enable		= s5pv210_clk_ip0_ctrl,
+		.ctrlbit	= (1 << 24),
+	}, {
+		.name		= "fimc",
+		.id		= 1,
+		.parent		= &clk_hclk_dsys.clk,
+		.enable		= s5pv210_clk_ip0_ctrl,
+		.ctrlbit	= (1 << 25),
+	}, {
+		.name		= "fimc",
+		.id		= 2,
+		.parent		= &clk_hclk_dsys.clk,
+		.enable		= s5pv210_clk_ip0_ctrl,
+		.ctrlbit	= (1 << 26),
+	}, {
+		.name		= "tvenc",
+		.id		= -1,
+		.parent		= &clk_hclk_dsys.clk,
+		.enable		= s5pv210_clk_ip1_ctrl,
+		.ctrlbit	= (1 << 10),
+	}, {
+		.name		= "hdmi",
+		.id		= -1,
+		.parent		= &clk_hclk_dsys.clk,
+		.enable		= s5pv210_clk_ip1_ctrl,
+		.ctrlbit	= (1 << 11),
+	}, {
+		.name		= "mixer",
+		.id		= -1,
+		.parent		= &clk_hclk_dsys.clk,
+		.enable		= s5pv210_clk_ip1_ctrl,
+		.ctrlbit	= (1 << 9),
+	}, {
 		.name		= "otg",
 		.id		= -1,
 		.parent		= &clk_hclk_psys.clk,
@@ -406,14 +448,20 @@ static struct clk init_clocks_disable[] = {
 		.id		= 0,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1 << 5),
 	}, {
 		.name		= "i2s_v32",
 		.id		= 1,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
-	}
+		.ctrlbit	= (1 << 6),
+	}, {
+		.name		= "iem_apc",
+		.id		= -1,
+		.parent		= &clk_p,
+		.enable		= s5pv210_clk_ip4_ctrl,
+		.ctrlbit	= (1 << 2),
+	},
 };
 
 static struct clk init_clocks[] = {
@@ -429,25 +477,25 @@ static struct clk init_clocks[] = {
 		.id		= 0,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<7),
+		.ctrlbit	= (1 << 17),
 	}, {
 		.name		= "uart",
 		.id		= 1,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<8),
+		.ctrlbit	= (1 << 18),
 	}, {
 		.name		= "uart",
 		.id		= 2,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<9),
+		.ctrlbit	= (1 << 19),
 	}, {
 		.name		= "uart",
 		.id		= 3,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<10),
+		.ctrlbit	= (1 << 20),
 	},
 };
 
@@ -497,8 +545,8 @@ static struct clksrc_clk clk_sclk_dac = {
 	.clk		= {
 		.name		= "sclk_dac",
 		.id		= -1,
-		.ctrlbit	= (1 << 10),
-		.enable		= s5pv210_clk_ip1_ctrl,
+		.ctrlbit	= (1 << 2),
+		.enable		= s5pv210_clk_mask0_ctrl,
 	},
 	.sources	= &clkset_sclk_dac,
 	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
@@ -527,8 +575,8 @@ static struct clksrc_clk clk_sclk_hdmi = {
 	.clk		= {
 		.name		= "sclk_hdmi",
 		.id		= -1,
-		.enable		= s5pv210_clk_ip1_ctrl,
-		.ctrlbit	= (1 << 11),
+		.ctrlbit	= (1 << 0),
+		.enable		= s5pv210_clk_mask0_ctrl,
 	},
 	.sources	= &clkset_sclk_hdmi,
 	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
@@ -565,8 +613,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 0,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 4),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 24),
 	},
 	.sources = &clkset_sclk_audio0,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
@@ -594,8 +642,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 1,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 5),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 25),
 	},
 	.sources = &clkset_sclk_audio1,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
@@ -623,8 +671,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 2,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 6),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 26),
 	},
 	.sources = &clkset_sclk_audio2,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
@@ -680,8 +728,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "uclk1",
 			.id		= 0,
-			.ctrlbit	= (1<<17),
-			.enable		= s5pv210_clk_ip3_ctrl,
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 12),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
@@ -690,8 +738,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 18),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 13),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
@@ -700,8 +748,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 19),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 14),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
@@ -710,8 +758,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 3,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 20),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 15),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
@@ -720,8 +768,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_mixer",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip1_ctrl,
-			.ctrlbit	= (1 << 9),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 1),
 		},
 		.sources = &clkset_sclk_mixer,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
@@ -738,8 +786,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_fimc",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 24),
+			.enable		= s5pv210_clk_mask1_ctrl,
+			.ctrlbit	= (1 << 2),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
@@ -748,8 +796,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_fimc",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 25),
+			.enable		= s5pv210_clk_mask1_ctrl,
+			.ctrlbit	= (1 << 3),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
@@ -758,8 +806,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_fimc",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 26),
+			.enable		= s5pv210_clk_mask1_ctrl,
+			.ctrlbit	= (1 << 4),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
@@ -768,6 +816,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_cam",
 			.id		= 0,
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 3),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
@@ -776,6 +826,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_cam",
 			.id		= 1,
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 4),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
@@ -784,8 +836,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_fimd",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip1_ctrl,
-			.ctrlbit	= (1 << 0),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 5),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
@@ -794,8 +846,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 16),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 8),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
@@ -804,8 +856,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 17),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 9),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
@@ -814,8 +866,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 18),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 10),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
@@ -824,8 +876,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 3,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 19),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 11),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
@@ -864,8 +916,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_csis",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 31),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 6),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
@@ -874,8 +926,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_spi",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 12),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 16),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
@@ -884,8 +936,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_spi",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 13),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 17),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
@@ -894,8 +946,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_pwi",
 			.id		= -1,
-			.enable		= &s5pv210_clk_ip4_ctrl,
-			.ctrlbit	= (1 << 2),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 29),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
@@ -904,8 +956,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_pwm",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 23),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 19),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
-- 
1.6.3.3



From linux at arm.linux.org.uk  Wed Jun 23 05:16:38 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 23 Jun 2010 10:16:38 +0100
Subject: [PATCH v3] S5PV210 Correct clock register properties
In-Reply-To: <1277283688-4542-1-git-send-email-myungjoo.ham@samsung.com>
References: <1277283688-4542-1-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <20100623091638.GA17436@n2100.arm.linux.org.uk>

On Wed, Jun 23, 2010 at 06:01:28PM +0900, MyungJoo Ham wrote:
> --- Duplicated Clock Problem ---
> Please note that each clock definition should access different control
> register; otherwise, the system may suffer lockups. For example, if we
> have two clock definitions "a" and "b" which access the same register
> (and the shift value). Then, when we do:
> 
> 	module A
> 	clk = clk_get("a");
> 	clk->clk_enable(clk);
> 
> 	module B (context switch)
> 	clk = clk_get("b");
> 	clk->clk_enable(clk);
> 	do something with clk.
> 	clk->clk_disable(clk);
> 
> 	module A (context switch)
> 	do something with clk
> 	* At this point, the system may hang.
> 
> Therefore, there should be no clock definitions with the same contol
> register/shift. If we need to create "aliases", then, creating child
> clocks sharing the clock should be fine.

Absolutely right, and the clk API has always allowed for this.  clk_get()
is supposed to translate a struct device + _clock_ _consumer_ _name_ to
the relevant struct clk, which may be the same struct clk which was
returned by clk_get for a completely different struct device & _clock_
_consumer_ _name_.

clkdev provides an easy way to do this by providing a tabular lookup
mechanism, which lists the device, clock consumer name and the struct
clk to return for that combination.


From m.szyprowski at samsung.com  Wed Jun 23 05:20:55 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Wed, 23 Jun 2010 11:20:55 +0200
Subject: Samsung SoCs: preparation for single kernel
In-Reply-To: <AANLkTikspf9zHuSKe86wDQxI12HpJo_occBlLUXBkjef@mail.gmail.com>
References: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com>
	<AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com>
	<AANLkTil1i_ZGI8bY14HhjrAk9RooVreAJsTteqqrMgqJ@mail.gmail.com>
	<AANLkTikDml6gQAsiRrCjIt4bUD3hnpAATr1erqCGOJMd@mail.gmail.com>
	<002301cb129c$ec59fe30$c50dfa90$%szyprowski@samsung.com>
	<AANLkTikspf9zHuSKe86wDQxI12HpJo_occBlLUXBkjef@mail.gmail.com>
Message-ID: <003e01cb12b5$656c0670$30441350$%szyprowski@samsung.com>

Hello,

On Wednesday, June 23, 2010 10:02 AM Eric Miao wrote:

> >> Now you have
> >>
> >> s5pv210_device_hsmmc0
> >> s5pc100_device_hsmmc0
> >> s3c64xx_device_hsmmc0
> >> ....
> >>
> >> each with a different base.
> >
> > There is no need for such code duplication.
> 
> However, I believe this is the right way to go. A certain level of
> duplication is the price to pay for a generic and clean solution.
> 
> When a peripheral controller or IP is moved from one SoC to the
> next generation, there are several things could have been changed:
> 
> 1. new base address and IRQ number
> 2. fixes and enhancements to the original IP
> 
> 1. will result in a different 'struct resource', and 2. will result in a
> different 'struct platform_device' with a different name, so the driver
> can match the platform_device_id table as you agreed I'm right on
> that recommendation.
> 
> They are actually _two_ different devices.

Right, they are separate entities, but would be really good if a similar
git brcode could be merged together.

> > Ben is working on a solution for
> > a single kernel which supports multiple SoCs. Some of his work in
> progress can
> > be found here: git://git.fluff.org/bjdooks/linux branch wip-samsung-dev
> and
> > wip-samsung-dev2.
> 
> Could you describe it a bit here and bring it on table for discussion?

The idea behind his patches is to provide a table for each SoC with short
description of all available devices and generate platform_device entries
dynamically from that table.

Here is a short code example:

struct s3c_pdev_table s3c6xxx_dev_table[] __initdata = {
	{
		.type	= SAMSUNG_DEVICE_UART,
		.name	= "s3c6400-uart",
		.index	= 0,
		.base	= S3C_PA_UART0,
		.irq	= IRQ_S3CUART_RX0,
		.template = &template_uart_s3c64xx,
	}, {
		.type	= SAMSUNG_DEVICE_UART,
		.name	= "s3c6400-uart",
		.index	= 1,
		.base	= S3C_PA_UART1,
		.irq	= IRQ_S3CUART_RX1,
		.template = &template_uart_s3c64xx,
	}, {
		.type	= SAMSUNG_DEVICE_UART,
		.name	= "s3c6400-uart",
		.index	= 2,
		.base	= S3C_PA_UART2,
		.irq	= IRQ_S3CUART_RX2,
		.template = &template_uart_s3c64xx,
	}, {
		.type	= SAMSUNG_DEVICE_UART,
		.name	= "s3c6400-uart",
		.index	= 3,
		.base	= S3C_PA_UART3,
		.irq	= IRQ_S3CUART_RX3,
		.template = &template_uart_s3c64xx,
	}, {
		.type	= SAMSUNG_DEVICE_WATCHDOG,
		.name	= "s3c2410-wdt",
		.index	= -1,
		.base	= S3C64XX_PA_WATCHDOG,
		.irq	= IRQ_WDT,
	}, {
		.type	= SAMSUNG_DEVICE_SDHCI,
		.name	= "s3c-sdhci",
		.index	= 0,
		.base	= S3C64XX_PA_HSMMC0 ,
		.irq	= IRQ_HSMMC0,
		.dma	= &samsung_std_dma_mask,
	}, {
		.type	= SAMSUNG_DEVICE_SDHCI,
		.name	= "s3c-sdhci",
		.index	= 1,
		.base	= S3C64XX_PA_HSMMC1,
		.irq	= IRQ_HSMMC1,
		.dma	= &samsung_std_dma_mask,
	}, {
		.type	= SAMSUNG_DEVICE_SDHCI,
		.name	= "s3c-sdhci",
		.index	= 2,
		.base	= S3C64XX_PA_HSMMC2,
		.irq	= IRQ_HSMMC1,
		.dma	= &samsung_std_dma_mask,
	}, {
		.type	= SAMSUNG_DEVICE_OHCI,
		.name	= "s3c2410-ohci",
		.index	= -1,
		.base	= S3C64XX_PA_USBHOST,
		.irq	= IRQ_USBH,
		.dma	= &samsung_std_dma_mask,
	}, {
		.type	= SAMSUNG_DEVICE_NAND,
		.name	= "s3c6400-nand",
		.index	= -1,
		.base	= 0x4E000000,
		.irq	= IRQ_NFC,
	}, {
		.type	= SAMSUNG_DEVICE_I2C,
		.name	= "s3c2440-i2c",
		.index	= 0,
		.base	= S3C64XX_PA_IIC0,
		.irq	= IRQ_IIC,
	}, {
...

This solution is imho really clean an easy to understand. It is also
easy to check which SoC has which peripherals defined and how.

I hope Ben will be able to finish it soon and all Samsung platforms can
be converted for it. Then creating a single kernel for more than one SoC
should be possible with only a few additional changes.

> PS: My feeling of commenting several of the samsung patches so far turns
> out to be quite frustrated, or I'm just too sensitive. NOTE neither am I
> NAKing Samsung patches, nor am I interested to be involved, I'm just givin
> my suggestions.

I'm sorry if I offended You. I just wanted to show that the solution has
been already found.

Best regards
--	
Marek Szyprowski
Samsung Poland R&D Center





From ivo.clarysse at gmail.com  Wed Jun 23 05:23:55 2010
From: ivo.clarysse at gmail.com (Ivo Clarysse)
Date: Wed, 23 Jun 2010 11:23:55 +0200
Subject: [PATCHv3 4/5] mtd: mxc_nand fixups
In-Reply-To: <80vd9ab0d2.fsf@merkur.tec.linutronix.de>
References: <804oh0b7gx.fsf@merkur.tec.linutronix.de>
	<20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
	<AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
	<80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTikRj_dMkKLyFhW78yld9jIYAIFncfPaPAF8WqUY@mail.gmail.com>
	<80iq5bqd07.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTimJKNEwOoKldq4a4_ufxNY6IY7r6tAfAM055hlW@mail.gmail.com>
	<80vd9ab0d2.fsf@merkur.tec.linutronix.de>
Message-ID: <AANLkTinVaXjCneg-XpxB7YNlmGOwQFTnm5RUcetPdToI@mail.gmail.com>

On Wed, Jun 23, 2010 at 10:48 AM, John Ogness <john.ogness at linutronix.de> wrote:
[...]
>
> OK. Now I understand the problem. Here is a new patch that introduces a
> flag that is set by the interrupt handler. This way we do not rely on
> the i.MX21 being able to read NFC_INT when the interrupt is masked.

Yes, this works on i.MX21 (tested on an MX21ADS board).

[...]
> @@ -117,6 +118,7 @@ struct mxc_nand_host {
> ? ? ? ?int ? ? ? ? ? ? ? ? ? ? clk_act;
> ? ? ? ?int ? ? ? ? ? ? ? ? ? ? irq;
>
> + ? ? ? int ? ? ? ? ? ? ? ? ? ? nfc_int;

But is it OK to use a regular (non-volatile) variable to communicate
between interrupt context and the non-interrupt context ?

My original patch for i.MX21 used completions instead:

http://lists.infradead.org/pipermail/linux-arm-kernel/2010-April/012694.html


From tony at atomide.com  Wed Jun 23 05:28:44 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 23 Jun 2010 12:28:44 +0300
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100623081218.GA16385@n2100.arm.linux.org.uk>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
	<20100623073912.GA12255@atomide.com>
	<20100623081218.GA16385@n2100.arm.linux.org.uk>
Message-ID: <20100623092843.GC12255@atomide.com>

* Russell King - ARM Linux <linux at arm.linux.org.uk> [100623 11:06]:
> On Wed, Jun 23, 2010 at 10:39:13AM +0300, Tony Lindgren wrote:
> > Yeah that can be done for __kuser_get_tls if it's always writable.
> > But __switch_to is trickier because of the CONFIG_MMU ifdefs there.
> 
> And impossible with XIP kernels.
> 
> > What if we have optional __switch_to and __kuser_get_tls implementations
> > in the mm/proc-*.S files that get copied over the current locations
> > if implemented?
> 
> Also problematical with XIP - if we go down the route of implementing
> these by copying code fragments into the kernel, we need to strip out
> XIP support or implement a second way.  Obviously having a second way
> adds maintainence burden, and the second way will probably lose out
> on updates.

How about if we implement the default XIP-safe unoptimized functions,
with minimal iffdeffery and then allow optional override for non-XIP
kernels from mm/proc-*.S files?

Regards,

Tony


From kgene.kim at samsung.com  Wed Jun 23 05:31:26 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 23 Jun 2010 18:31:26 +0900
Subject: [PATCH v3] S5PV210 Correct clock register properties
In-Reply-To: <1277283688-4542-1-git-send-email-myungjoo.ham@samsung.com>
References: <1277283688-4542-1-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <005901cb12b6$dd55d9d0$98018d70$%kim@samsung.com>

MyungJoo Ham wrote:
> 
> 1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which
were
> defined incorrectly.
> 
> 2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc,
> sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their
> twins defined in struct clk init_clocks_disable[] and struct clk
> init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK
> register to avoid the duplicated clock problem described below.
> 
> --- Duplicated Clock Problem ---
> Please note that each clock definition should access different control
> register; otherwise, the system may suffer lockups. For example, if we
> have two clock definitions "a" and "b" which access the same register
> (and the shift value). Then, when we do:
> 
> 	module A
> 	clk = clk_get("a");
> 	clk->clk_enable(clk);
> 
> 	module B (context switch)
> 	clk = clk_get("b");
> 	clk->clk_enable(clk);
> 	do something with clk.
> 	clk->clk_disable(clk);
> 
> 	module A (context switch)
> 	do something with clk
> 	* At this point, the system may hang.
> 
> Therefore, there should be no clock definitions with the same contol
> register/shift. If we need to create "aliases", then, creating child
> clocks sharing the clock should be fine.
> 
> 3. Added struct clk for clock gating (CLK_GATE_IPx) of the clksrc_clk's
> which were accessing CLK_GATE_IP and modified to access CLK_SRC_MASK
> 
> Note that this patch revises and merges the two previous patches:
> [PATCH] S5PV210 Correct clock register properties
> [PATCH] S5PV210 Correct clock source control register properties
> And follows the previous patch
> [PATCH v2] S5PV210 Correct clock register properties
> 
> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-s5pv210/clock.c |  158 +++++++++++++++++++++++++++---------
> -----
>  1 files changed, 105 insertions(+), 53 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> index 154bca4..fd76e78 100644
> --- a/arch/arm/mach-s5pv210/clock.c
> +++ b/arch/arm/mach-s5pv210/clock.c
> @@ -270,12 +270,54 @@ static struct clk_ops clk_hclk_imem_ops = {
> 
>  static struct clk init_clocks_disable[] = {
>  	{
> +		.name		= "csis",
> +		.id		= -1,
> +		.parent		= &clk_pclk_dsys.clk,
> +		.enable		= s5pv210_clk_ip0_ctrl,
> +		.ctrlbit	= (1 << 31),
> +	}, {
>  		.name		= "rot",
>  		.id		= -1,
>  		.parent		= &clk_hclk_dsys.clk,
>  		.enable		= s5pv210_clk_ip0_ctrl,
>  		.ctrlbit	= (1<<29),
>  	}, {
> +		.name		= "fimc",
> +		.id		= 0,
> +		.parent		= &clk_hclk_dsys.clk,
> +		.enable		= s5pv210_clk_ip0_ctrl,
> +		.ctrlbit	= (1 << 24),
> +	}, {
> +		.name		= "fimc",
> +		.id		= 1,
> +		.parent		= &clk_hclk_dsys.clk,
> +		.enable		= s5pv210_clk_ip0_ctrl,
> +		.ctrlbit	= (1 << 25),
> +	}, {
> +		.name		= "fimc",
> +		.id		= 2,
> +		.parent		= &clk_hclk_dsys.clk,
> +		.enable		= s5pv210_clk_ip0_ctrl,
> +		.ctrlbit	= (1 << 26),
> +	}, {
> +		.name		= "tvenc",
> +		.id		= -1,
> +		.parent		= &clk_hclk_dsys.clk,
> +		.enable		= s5pv210_clk_ip1_ctrl,
> +		.ctrlbit	= (1 << 10),
> +	}, {
> +		.name		= "hdmi",
> +		.id		= -1,
> +		.parent		= &clk_hclk_dsys.clk,
> +		.enable		= s5pv210_clk_ip1_ctrl,
> +		.ctrlbit	= (1 << 11),
> +	}, {
> +		.name		= "mixer",
> +		.id		= -1,
> +		.parent		= &clk_hclk_dsys.clk,
> +		.enable		= s5pv210_clk_ip1_ctrl,
> +		.ctrlbit	= (1 << 9),
> +	}, {

Why do you add new clocks in here?
I still say just need bug fix...

Bug fix and new additions have to be separate patch always.

>  		.name		= "otg",
>  		.id		= -1,
>  		.parent		= &clk_hclk_psys.clk,
> @@ -406,14 +448,20 @@ static struct clk init_clocks_disable[] = {
>  		.id		= 0,
>  		.parent		= &clk_p,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<4),
> +		.ctrlbit	= (1 << 5),
>  	}, {
>  		.name		= "i2s_v32",
>  		.id		= 1,
>  		.parent		= &clk_p,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<4),
> -	}
> +		.ctrlbit	= (1 << 6),
> +	}, {
> +		.name		= "iem_apc",
> +		.id		= -1,
> +		.parent		= &clk_p,
> +		.enable		= s5pv210_clk_ip4_ctrl,
> +		.ctrlbit	= (1 << 2),
> +	},

same...

>  };
> 
>  static struct clk init_clocks[] = {
> @@ -429,25 +477,25 @@ static struct clk init_clocks[] = {
>  		.id		= 0,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<7),
> +		.ctrlbit	= (1 << 17),
>  	}, {
>  		.name		= "uart",
>  		.id		= 1,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<8),
> +		.ctrlbit	= (1 << 18),
>  	}, {
>  		.name		= "uart",
>  		.id		= 2,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<9),
> +		.ctrlbit	= (1 << 19),
>  	}, {
>  		.name		= "uart",
>  		.id		= 3,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<10),
> +		.ctrlbit	= (1 << 20),
>  	},
>  };
> 
> @@ -497,8 +545,8 @@ static struct clksrc_clk clk_sclk_dac = {
>  	.clk		= {
>  		.name		= "sclk_dac",
>  		.id		= -1,
> -		.ctrlbit	= (1 << 10),
> -		.enable		= s5pv210_clk_ip1_ctrl,
> +		.ctrlbit	= (1 << 2),
> +		.enable		= s5pv210_clk_mask0_ctrl,
>  	},
>  	.sources	= &clkset_sclk_dac,
>  	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
> @@ -527,8 +575,8 @@ static struct clksrc_clk clk_sclk_hdmi = {
>  	.clk		= {
>  		.name		= "sclk_hdmi",
>  		.id		= -1,
> -		.enable		= s5pv210_clk_ip1_ctrl,
> -		.ctrlbit	= (1 << 11),
> +		.ctrlbit	= (1 << 0),
> +		.enable		= s5pv210_clk_mask0_ctrl,

Please keep the order of the additions like below because it will be easy to
review the code.

+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 0),

>  	},
>  	.sources	= &clkset_sclk_hdmi,
>  	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
> @@ -565,8 +613,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
>  	.clk		= {
>  		.name		= "sclk_audio",
>  		.id		= 0,
> -		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1 << 4),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 24),
>  	},
>  	.sources = &clkset_sclk_audio0,
>  	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
> @@ -594,8 +642,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
>  	.clk		= {
>  		.name		= "sclk_audio",
>  		.id		= 1,
> -		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1 << 5),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 25),
>  	},
>  	.sources = &clkset_sclk_audio1,
>  	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
> @@ -623,8 +671,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
>  	.clk		= {
>  		.name		= "sclk_audio",
>  		.id		= 2,
> -		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1 << 6),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 26),
>  	},
>  	.sources = &clkset_sclk_audio2,
>  	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
> @@ -680,8 +728,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "uclk1",
>  			.id		= 0,
> -			.ctrlbit	= (1<<17),
> -			.enable		= s5pv210_clk_ip3_ctrl,
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 12),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
> @@ -690,8 +738,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "uclk1",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 18),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 13),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
> @@ -700,8 +748,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "uclk1",
>  			.id		= 2,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 19),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 14),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
> @@ -710,8 +758,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "uclk1",
>  			.id		= 3,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 20),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 15),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
> @@ -720,8 +768,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "sclk_mixer",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip1_ctrl,
> -			.ctrlbit	= (1 << 9),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 1),
>  		},
>  		.sources = &clkset_sclk_mixer,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
> @@ -738,8 +786,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "sclk_fimc",
>  			.id		= 0,
> -			.enable		= s5pv210_clk_ip0_ctrl,
> -			.ctrlbit	= (1 << 24),
> +			.enable		= s5pv210_clk_mask1_ctrl,

Where is 's5pv210_clk_mask1_ctrl' ... ?
Please test at least compile before submitting.

's5pv210_clk_mask1_ctrl' was added in this your patch
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/018221.html

> +			.ctrlbit	= (1 << 2),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
> @@ -748,8 +796,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "sclk_fimc",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip0_ctrl,
> -			.ctrlbit	= (1 << 25),
> +			.enable		= s5pv210_clk_mask1_ctrl,
> +			.ctrlbit	= (1 << 3),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
> @@ -758,8 +806,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "sclk_fimc",
>  			.id		= 2,
> -			.enable		= s5pv210_clk_ip0_ctrl,
> -			.ctrlbit	= (1 << 26),
> +			.enable		= s5pv210_clk_mask1_ctrl,
> +			.ctrlbit	= (1 << 4),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
> @@ -768,6 +816,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_cam",
>  			.id		= 0,
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 3),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
> @@ -776,6 +826,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_cam",
>  			.id		= 1,
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 4),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
> @@ -784,8 +836,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_fimd",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip1_ctrl,
> -			.ctrlbit	= (1 << 0),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 5),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
> @@ -794,8 +846,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 0,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 16),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 8),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
> @@ -804,8 +856,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 17),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 9),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
> @@ -814,8 +866,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 2,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 18),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 10),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
> @@ -824,8 +876,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 3,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 19),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 11),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
> @@ -864,8 +916,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_csis",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip0_ctrl,
> -			.ctrlbit	= (1 << 31),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 6),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
> @@ -874,8 +926,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_spi",
>  			.id		= 0,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 12),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 16),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
> @@ -884,8 +936,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_spi",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 13),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 17),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
> @@ -894,8 +946,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_pwi",
>  			.id		= -1,
> -			.enable		= &s5pv210_clk_ip4_ctrl,
> -			.ctrlbit	= (1 << 2),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 29),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
> @@ -904,8 +956,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_pwm",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 23),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 19),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
> --

I think, your previous patch is better...

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From linux at arm.linux.org.uk  Wed Jun 23 05:32:42 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 23 Jun 2010 10:32:42 +0100
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100623092843.GC12255@atomide.com>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
	<20100623073912.GA12255@atomide.com>
	<20100623081218.GA16385@n2100.arm.linux.org.uk>
	<20100623092843.GC12255@atomide.com>
Message-ID: <20100623093242.GA17948@n2100.arm.linux.org.uk>

On Wed, Jun 23, 2010 at 12:28:44PM +0300, Tony Lindgren wrote:
> * Russell King - ARM Linux <linux at arm.linux.org.uk> [100623 11:06]:
> > On Wed, Jun 23, 2010 at 10:39:13AM +0300, Tony Lindgren wrote:
> > > Yeah that can be done for __kuser_get_tls if it's always writable.
> > > But __switch_to is trickier because of the CONFIG_MMU ifdefs there.
> > 
> > And impossible with XIP kernels.
> > 
> > > What if we have optional __switch_to and __kuser_get_tls implementations
> > > in the mm/proc-*.S files that get copied over the current locations
> > > if implemented?
> > 
> > Also problematical with XIP - if we go down the route of implementing
> > these by copying code fragments into the kernel, we need to strip out
> > XIP support or implement a second way.  Obviously having a second way
> > adds maintainence burden, and the second way will probably lose out
> > on updates.
> 
> How about if we implement the default XIP-safe unoptimized functions,
> with minimal iffdeffery and then allow optional override for non-XIP
> kernels from mm/proc-*.S files?

That's what I was referring to by "second way".


From will.deacon at arm.com  Wed Jun 23 05:36:03 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 23 Jun 2010 10:36:03 +0100
Subject: [PATCH 2/2] ARM: perf probe: Add ARM DWARF register number mappings
In-Reply-To: <1277285763-16213-2-git-send-email-will.deacon@arm.com>
References: <1277285763-16213-1-git-send-email-will.deacon@arm.com>
	<1277285763-16213-2-git-send-email-will.deacon@arm.com>
Message-ID: <1277285763-16213-3-git-send-email-will.deacon@arm.com>

This patch adds mappings from DWARF register numbers to the register
names used by the ARM `Regs and Stack Access API'.

Cc: Jamie Iles <jamie.iles at picochip.com>
Cc: Jean Pihet <jpihet at mvista.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 tools/perf/arch/arm/Makefile          |    4 ++
 tools/perf/arch/arm/util/dwarf-regs.c |   64 +++++++++++++++++++++++++++++++++
 2 files changed, 68 insertions(+), 0 deletions(-)
 create mode 100644 tools/perf/arch/arm/Makefile
 create mode 100644 tools/perf/arch/arm/util/dwarf-regs.c

diff --git a/tools/perf/arch/arm/Makefile b/tools/perf/arch/arm/Makefile
new file mode 100644
index 0000000..15130b5
--- /dev/null
+++ b/tools/perf/arch/arm/Makefile
@@ -0,0 +1,4 @@
+ifndef NO_DWARF
+PERF_HAVE_DWARF_REGS := 1
+LIB_OBJS += $(OUTPUT)arch/$(ARCH)/util/dwarf-regs.o
+endif
diff --git a/tools/perf/arch/arm/util/dwarf-regs.c b/tools/perf/arch/arm/util/dwarf-regs.c
new file mode 100644
index 0000000..fff6450
--- /dev/null
+++ b/tools/perf/arch/arm/util/dwarf-regs.c
@@ -0,0 +1,64 @@
+/*
+ * Mapping of DWARF debug register numbers into register names.
+ *
+ * Copyright (C) 2010 Will Deacon, ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <libio.h>
+#include <dwarf-regs.h>
+
+struct pt_regs_dwarfnum {
+	const char *name;
+	unsigned int dwarfnum;
+};
+
+#define STR(s) #s
+#define REG_DWARFNUM_NAME(r, num) {.name = r, .dwarfnum = num}
+#define GPR_DWARFNUM_NAME(num) \
+	{.name = STR(%r##num), .dwarfnum = num}
+#define REG_DWARFNUM_END {.name = NULL, .dwarfnum = 0}
+
+/*
+ * Reference:
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ihi0040a/IHI0040A_aadwarf.pdf
+ */
+static const struct pt_regs_dwarfnum regdwarfnum_table[] = {
+	GPR_DWARFNUM_NAME(0),
+	GPR_DWARFNUM_NAME(1),
+	GPR_DWARFNUM_NAME(2),
+	GPR_DWARFNUM_NAME(3),
+	GPR_DWARFNUM_NAME(4),
+	GPR_DWARFNUM_NAME(5),
+	GPR_DWARFNUM_NAME(6),
+	GPR_DWARFNUM_NAME(7),
+	GPR_DWARFNUM_NAME(8),
+	GPR_DWARFNUM_NAME(9),
+	GPR_DWARFNUM_NAME(10),
+	REG_DWARFNUM_NAME("%fp", 11),
+	REG_DWARFNUM_NAME("%ip", 12),
+	REG_DWARFNUM_NAME("%sp", 13),
+	REG_DWARFNUM_NAME("%lr", 14),
+	REG_DWARFNUM_NAME("%pc", 15),
+	REG_DWARFNUM_END,
+};
+
+/**
+ * get_arch_regstr() - lookup register name from it's DWARF register number
+ * @n:	the DWARF register number
+ *
+ * get_arch_regstr() returns the name of the register in struct
+ * regdwarfnum_table from it's DWARF register number. If the register is not
+ * found in the table, this returns NULL;
+ */
+const char *get_arch_regstr(unsigned int n)
+{
+	const struct pt_regs_dwarfnum *roff;
+	for (roff = regdwarfnum_table; roff->name != NULL; roff++)
+		if (roff->dwarfnum == n)
+			return roff->name;
+	return NULL;
+}
-- 
1.6.3.3



From will.deacon at arm.com  Wed Jun 23 05:36:02 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 23 Jun 2010 10:36:02 +0100
Subject: [PATCH 1/2] ARM: Add kprobe-based event tracer
In-Reply-To: <1277285763-16213-1-git-send-email-will.deacon@arm.com>
References: <1277285763-16213-1-git-send-email-will.deacon@arm.com>
Message-ID: <1277285763-16213-2-git-send-email-will.deacon@arm.com>

This patch enables the HAVE_REGS_AND_STACK_ACCESS_API option
for ARM which is required by the kprobe events tracer. Code based
on the PowerPC port.

Cc: Jamie Iles <jamie.iles at picochip.com>
Cc: Jean Pihet <jpihet at mvista.com>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/Kconfig              |    1 +
 arch/arm/include/asm/ptrace.h |   36 +++++++++++++++
 arch/arm/kernel/ptrace.c      |   96 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 133 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e57cb24..e0e7de6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -24,6 +24,7 @@ config ARM
 	select HAVE_KERNEL_LZMA
 	select HAVE_PERF_EVENTS
 	select PERF_USE_VMALLOC
+	select HAVE_REGS_AND_STACK_ACCESS_API
 	help
 	  The ARM series is a line of low-power-consumption RISC chip designs
 	  licensed by ARM Ltd and targeted at embedded applications and
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 9dcb11e..c974be8 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -184,6 +184,42 @@ extern unsigned long profile_pc(struct pt_regs *regs);
 #define predicate(x)		((x) & 0xf0000000)
 #define PREDICATE_ALWAYS	0xe0000000
 
+/*
+ * kprobe-based event tracer support
+ */
+#include <linux/stddef.h>
+#include <linux/types.h>
+#define MAX_REG_OFFSET (offsetof(struct pt_regs, ARM_ORIG_r0))
+
+extern int regs_query_register_offset(const char *name);
+extern const char *regs_query_register_name(unsigned int offset);
+extern bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr);
+extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
+					       unsigned int n);
+
+/**
+ * regs_get_register() - get register value from its offset
+ * @regs:	   pt_regs from which register value is gotten
+ * @offset:    offset number of the register.
+ *
+ * regs_get_register returns the value of a register whose offset from @regs.
+ * The @offset is the offset of the register in struct pt_regs.
+ * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
+ */
+static inline unsigned long regs_get_register(struct pt_regs *regs,
+					      unsigned int offset)
+{
+	if (unlikely(offset > MAX_REG_OFFSET))
+		return 0;
+	return *(unsigned long *)((unsigned long)regs + offset);
+}
+
+/* Valid only for Kernel mode traps. */
+static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
+{
+	return regs->ARM_sp;
+}
+
 #endif /* __KERNEL__ */
 
 #endif /* __ASSEMBLY__ */
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 3f562a7..f99d489 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -52,6 +52,102 @@
 #define BREAKINST_THUMB	0xde01
 #endif
 
+struct pt_regs_offset {
+	const char *name;
+	int offset;
+};
+
+#define REG_OFFSET_NAME(r) \
+	{.name = #r, .offset = offsetof(struct pt_regs, ARM_##r)}
+#define REG_OFFSET_END {.name = NULL, .offset = 0}
+
+static const struct pt_regs_offset regoffset_table[] = {
+	REG_OFFSET_NAME(r0),
+	REG_OFFSET_NAME(r1),
+	REG_OFFSET_NAME(r2),
+	REG_OFFSET_NAME(r3),
+	REG_OFFSET_NAME(r4),
+	REG_OFFSET_NAME(r5),
+	REG_OFFSET_NAME(r6),
+	REG_OFFSET_NAME(r7),
+	REG_OFFSET_NAME(r8),
+	REG_OFFSET_NAME(r9),
+	REG_OFFSET_NAME(r10),
+	REG_OFFSET_NAME(fp),
+	REG_OFFSET_NAME(ip),
+	REG_OFFSET_NAME(sp),
+	REG_OFFSET_NAME(lr),
+	REG_OFFSET_NAME(pc),
+	REG_OFFSET_NAME(cpsr),
+	REG_OFFSET_NAME(ORIG_r0),
+	REG_OFFSET_END,
+};
+
+/**
+ * regs_query_register_offset() - query register offset from its name
+ * @name:	the name of a register
+ *
+ * regs_query_register_offset() returns the offset of a register in struct
+ * pt_regs from its name. If the name is invalid, this returns -EINVAL;
+ */
+int regs_query_register_offset(const char *name)
+{
+	const struct pt_regs_offset *roff;
+	for (roff = regoffset_table; roff->name != NULL; roff++)
+		if (!strcmp(roff->name, name))
+			return roff->offset;
+	return -EINVAL;
+}
+
+/**
+ * regs_query_register_name() - query register name from its offset
+ * @offset:	the offset of a register in struct pt_regs.
+ *
+ * regs_query_register_name() returns the name of a register from its
+ * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
+ */
+const char *regs_query_register_name(unsigned int offset)
+{
+	const struct pt_regs_offset *roff;
+	for (roff = regoffset_table; roff->name != NULL; roff++)
+		if (roff->offset == offset)
+			return roff->name;
+	return NULL;
+}
+
+/**
+ * regs_within_kernel_stack() - check the address in the stack
+ * @regs:      pt_regs which contains kernel stack pointer.
+ * @addr:      address which is checked.
+ *
+ * regs_within_kernel_stack() checks @addr is within the kernel stack page(s).
+ * If @addr is within the kernel stack, it returns true. If not, returns false.
+ */
+bool regs_within_kernel_stack(struct pt_regs *regs, unsigned long addr)
+{
+	return ((addr & ~(THREAD_SIZE - 1))  ==
+		(kernel_stack_pointer(regs) & ~(THREAD_SIZE - 1)));
+}
+
+/**
+ * regs_get_kernel_stack_nth() - get Nth entry of the stack
+ * @regs:	pt_regs which contains kernel stack pointer.
+ * @n:		stack entry number.
+ *
+ * regs_get_kernel_stack_nth() returns @n th entry of the kernel stack which
+ * is specified by @regs. If the @n th entry is NOT in the kernel stack,
+ * this returns 0.
+ */
+unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs, unsigned int n)
+{
+	unsigned long *addr = (unsigned long *)kernel_stack_pointer(regs);
+	addr += n;
+	if (regs_within_kernel_stack(regs, (unsigned long)addr))
+		return *addr;
+	else
+		return 0;
+}
+
 /*
  * this routine will get a word off of the processes privileged stack.
  * the offset is how far from the base addr as stored in the THREAD.
-- 
1.6.3.3



From will.deacon at arm.com  Wed Jun 23 05:36:01 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 23 Jun 2010 10:36:01 +0100
Subject: [PATCH 0/2] add perf-probe support on ARM
Message-ID: <1277285763-16213-1-git-send-email-will.deacon@arm.com>

Perf-probe uses the KProbe events tracer to place and monitor probes
on the running Kernel.

This patch series adds both Kernel and tool support for this feature
on ARM.

Patches based on 2.6.35-rc3 [although perf record is currently broken
on all architectures for probe tracepoints. These patches also apply
cleanly to -tip/master where perf record works properly.]

Cc: Jamie Iles <jamie.iles at picochip.com>
Cc: Jean Pihet <jpihet at mvista.com>

Will Deacon (2):
  ARM: Add kprobe-based event tracer
  ARM: perf probe: Add ARM DWARF register number mappings

 arch/arm/Kconfig                      |    1 +
 arch/arm/include/asm/ptrace.h         |   36 ++++++++++++
 arch/arm/kernel/ptrace.c              |   96 +++++++++++++++++++++++++++++++++
 tools/perf/arch/arm/Makefile          |    4 ++
 tools/perf/arch/arm/util/dwarf-regs.c |   64 ++++++++++++++++++++++
 5 files changed, 201 insertions(+), 0 deletions(-)
 create mode 100644 tools/perf/arch/arm/Makefile
 create mode 100644 tools/perf/arch/arm/util/dwarf-regs.c



From david-b at pacbell.net  Wed Jun 23 05:39:46 2010
From: david-b at pacbell.net (David Brownell)
Date: Wed, 23 Jun 2010 02:39:46 -0700 (PDT)
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping
	gpios)
In-Reply-To: <4C21955D.1020502@bluewatersys.com>
Message-ID: <728731.73469.qm@web180307.mail.gq1.yahoo.com>



--- On Tue, 6/22/10, Ryan Mallon <ryan at bluewatersys.com> wrote:

> > --- On Tue, 6/22/10, Ryan Mallon <ryan at bluewatersys.com>
> wrote:
> > 
> > 
> >> gpiolib
> > 
> > 
> > Again, you're talking about "gpiolib" when
> > you seem to mean the GPIO framework itself
> > (for which gpiolib is only an implementation
> > option)...
> 
> Fine, its just semantics.

Yes, just the foundation of what you're
saying.  Stuff that, when you get it wrong,
prevents communication.  Try to get it right.

If you can't be bothered to get the basics
right, I'll just have to assume you're being
a troll.  There's enough evidence of that in
other parts of your latest message; sorry.


 I think everyone knows what I
> mean when I
> refer to gpiolib.

Not without first wasting tiime finding
that you don't really mean "gpiolib"; you
instead mean something else entirely.  Sigh.

 
> >> 'Can sleep' for a gpio has two different meanings
> depending
> >> on context
> > 
> > NO; for the GPIO itself it's only ever had one
> > meaning, regardless of context.
> > 
> > You're trying to conflate the GPIO and one
> > of the contexts in which it's used.? That's
> > the problem you seem to be struggling with.
> > 
> > Please stop conflating/confusing
> > those two disparate concepts...
> 
> I'm not. 

BUT Your "counter" example below is solid
proof that you are:  it shows exactly the
confusion I pointed out:  call context versus
the GPIO itself.  There's no way I can read
that as anything except "you are"...

 
Your intent here seems perhaps more to
be a troll than to address any real
technical issues.  I don't see much
point participating any further.


 Some gpios, such as those on io expanders, may
> sleep in their
> implementations of the gpio_(set/get) functions.
> 

Such GPIOs have a "cansleep" attribute, in short.


> Drivers, which use a gpio, may call gpio_(set/get)
> functions for a given
> gpio from a context where it is not safe to sleep.

And that's the call dontext
(in this case, from a driver).

  QED.  You are confusing two disparate concepts.


 In this
> case, a gpio
> which may sleep (ie one on an i2c io-expander) cannot be
> used with this
> driver. The gpio_request will succeed, but any call to
> gpio_(set/get)_value will produce a warning.
> 
> >> example, if a driver calls gpio_get_value(gpio)
> from an
> >> interupt handler


(YOU introduce interrupt/IRQ handlers...)

> >> then the gpio must not be a sleeping gpio.
> > 
> > In a threaded IRQ handler it's OK to use
> > the get_value_cansleep() option..
> 
> Ugh, you are really twisting my words.


You said IRQ handler, so did I.  In what csense could I
possibly be "twisting" your words"???


STOP TROLLING.




 replace 'interrupt
> handler' with
> 'non sleep safe context'.

No, that would really be "twisting", by
moving words from one place to another
and significantly changing meanings.





From david-b at pacbell.net  Wed Jun 23 05:51:46 2010
From: david-b at pacbell.net (David Brownell)
Date: Wed, 23 Jun 2010 02:51:46 -0700 (PDT)
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping
	gpios)
In-Reply-To: <AANLkTinuO053upBHzsiQ2llNdu4_XZN0rfz01QuIE7LW@mail.gmail.com>
Message-ID: <711634.79166.qm@web180314.mail.gq1.yahoo.com>


> >
> > So, NAK on these proposed changes.
> >
> 
> Hi David,
> 
> You are really a NAKing machine ;-)

I limit NAKs to bad ideas/code, like this.


 People get confused for
> a reason, and
> I believe you have a good solution  for this?


Ryan seems to need a cluebat application.  I've
tried, but he's resisted, and even denied the most
blatant sources of his personal confusion.  While
he esists, I can't do much. for him.




From john.ogness at linutronix.de  Wed Jun 23 06:10:08 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Wed, 23 Jun 2010 12:10:08 +0200
Subject: [PATCHv3 4/5] mtd: mxc_nand fixups
In-Reply-To: <AANLkTinVaXjCneg-XpxB7YNlmGOwQFTnm5RUcetPdToI@mail.gmail.com>
	(Ivo Clarysse's message of "Wed, 23 Jun 2010 11:23:55 +0200")
References: <804oh0b7gx.fsf@merkur.tec.linutronix.de>
	<20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
	<AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
	<80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTikRj_dMkKLyFhW78yld9jIYAIFncfPaPAF8WqUY@mail.gmail.com>
	<80iq5bqd07.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTimJKNEwOoKldq4a4_ufxNY6IY7r6tAfAM055hlW@mail.gmail.com>
	<80vd9ab0d2.fsf@merkur.tec.linutronix.de>
	<AANLkTinVaXjCneg-XpxB7YNlmGOwQFTnm5RUcetPdToI@mail.gmail.com>
Message-ID: <80lja6awlb.fsf@merkur.tec.linutronix.de>

On 2010-06-23, Ivo Clarysse <ivo.clarysse at gmail.com> wrote:
> But is it OK to use a regular (non-volatile) variable to communicate
> between interrupt context and the non-interrupt context ?

In this case, yes.

> My original patch for i.MX21 used completions instead:
>
> http://lists.infradead.org/pipermail/linux-arm-kernel/2010-April/012694.html

Ah. It seems you've been through all this before. I wish I had noticed
that thread before. I will need to check more carefully in the future.

Yes, your original patch achieves the exact same thing. Whether we use
wait_event() with a flag or wait_completion() really is the same
thing. So I guess Sascha can decide what we should do there.

What I like about your original patch is that only the i.MX21 has the
cost of constantly enabling/disabling the irq line. It adds 5
cpu_is_mx21() blocks to the code, but will lead to less work for the CPU
on non-i.MX21 boards.

John Ogness


From eric.y.miao at gmail.com  Wed Jun 23 06:24:18 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 18:24:18 +0800
Subject: Samsung SoCs: preparation for single kernel
In-Reply-To: <003e01cb12b5$656c0670$30441350$%szyprowski@samsung.com>
References: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com>
	<AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com>
	<AANLkTil1i_ZGI8bY14HhjrAk9RooVreAJsTteqqrMgqJ@mail.gmail.com>
	<AANLkTikDml6gQAsiRrCjIt4bUD3hnpAATr1erqCGOJMd@mail.gmail.com>
	<002301cb129c$ec59fe30$c50dfa90$%szyprowski@samsung.com>
	<AANLkTikspf9zHuSKe86wDQxI12HpJo_occBlLUXBkjef@mail.gmail.com>
	<003e01cb12b5$656c0670$30441350$%szyprowski@samsung.com>
Message-ID: <AANLkTilt7uncmA1Zfo77h4bGbRIlvmp6zOCbdDK3QMez@mail.gmail.com>

On Wednesday, June 23, 2010, Marek Szyprowski <m.szyprowski at samsung.com> wrote:
> Hello,
>
> On Wednesday, June 23, 2010 10:02 AM Eric Miao wrote:
>
>> >> Now you have
>> >>
>> >> s5pv210_device_hsmmc0
>> >> s5pc100_device_hsmmc0
>> >> s3c64xx_device_hsmmc0
>> >> ....
>> >>
>> >> each with a different base.
>> >
>> > There is no need for such code duplication.
>>
>> However, I believe this is the right way to go. A certain level of
>> duplication is the price to pay for a generic and clean solution.
>>
>> When a peripheral controller or IP is moved from one SoC to the
>> next generation, there are several things could have been changed:
>>
>> 1. new base address and IRQ number
>> 2. fixes and enhancements to the original IP
>>
>> 1. will result in a different 'struct resource', and 2. will result in a
>> different 'struct platform_device' with a different name, so the driver
>> can match the platform_device_id table as you agreed I'm right on
>> that recommendation.
>>
>> They are actually _two_ different devices.
>
> Right, they are separate entities, but would be really good if a similar
> git brcode could be merged together.
>
>> > Ben is working on a solution for
>> > a single kernel which supports multiple SoCs. Some of his work in
>> progress can
>> > be found here: git://git.fluff.org/bjdooks/linux branch wip-samsung-dev
>> and
>> > wip-samsung-dev2.
>>
>> Could you describe it a bit here and bring it on table for discussion?
>
> The idea behind his patches is to provide a table for each SoC with short
> description of all available devices and generate platform_device entries
> dynamically from that table.
>
> Here is a short code example:
>
> struct s3c_pdev_table s3c6xxx_dev_table[] __initdata = {
>  ? ? ? ?{
>  ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_UART,
>  ? ? ? ? ? ? ? ?.name ? = "s3c6400-uart",
>  ? ? ? ? ? ? ? ?.index ?= 0,
>  ? ? ? ? ? ? ? ?.base ? = S3C_PA_UART0,
>  ? ? ? ? ? ? ? ?.irq ? ?= IRQ_S3CUART_RX0,
>  ? ? ? ? ? ? ? ?.template = &template_uart_s3c64xx,
>  ? ? ? ?}, {
>  ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_UART,
>  ? ? ? ? ? ? ? ?.name ? = "s3c6400-uart",
>  ? ? ? ? ? ? ? ?.index ?= 1,
>  ? ? ? ? ? ? ? ?.base ? = S3C_PA_UART1,
>  ? ? ? ? ? ? ? ?.irq ? ?= IRQ_S3CUART_RX1,
>  ? ? ? ? ? ? ? ?.template = &template_uart_s3c64xx,
>  ? ? ? ?}, {
>  ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_UART,
>  ? ? ? ? ? ? ? ?.name ? = "s3c6400-uart",
>  ? ? ? ? ? ? ? ?.index ?= 2,
>  ? ? ? ? ? ? ? ?.base ? = S3C_PA_UART2,
>  ? ? ? ? ? ? ? ?.irq ? ?= IRQ_S3CUART_RX2,
>  ? ? ? ? ? ? ? ?.template = &template_uart_s3c64xx,
>  ? ? ? ?}, {
>  ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_UART,
>  ? ? ? ? ? ? ? ?.name ? = "s3c6400-uart",
>  ? ? ? ? ? ? ? ?.index ?= 3,
>  ? ? ? ? ? ? ? ?.base ? = S3C_PA_UART3,
>  ? ? ? ? ? ? ? ?.irq ? ?= IRQ_S3CUART_RX3,
>  ? ? ? ? ? ? ? ?.template = &template_uart_s3c64xx,
>  ? ? ? ?}, {
>  ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_WATCHDOG,
>  ? ? ? ? ? ? ? ?.name ? = "s3c2410-wdt",
>  ? ? ? ? ? ? ? ?.index ?= -1,
>  ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_WATCHDOG,
>  ? ? ? ? ? ? ? ?.irq ? ?= IRQ_WDT,
>  ? ? ? ?}, {
>  ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_SDHCI,
>  ? ? ? ? ? ? ? ?.name ? = "s3c-sdhci",
>  ? ? ? ? ? ? ? ?.index ?= 0,
>  ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_HSMMC0 ,
>  ? ? ? ? ? ? ? ?.irq ? ?= IRQ_HSMMC0,
>  ? ? ? ? ? ? ? ?.dma ? ?= &samsung_std_dma_mask,
>  ? ? ? ?}, {
>  ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_SDHCI,
>  ? ? ? ? ? ? ? ?.name ? = "s3c-sdhci",
>  ? ? ? ? ? ? ? ?.index ?= 1,
>  ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_HSMMC1,
>  ? ? ? ? ? ? ? ?.irq ? ?= IRQ_HSMMC1,
>  ? ? ? ? ? ? ? ?.dma ? ?= &samsung_std_dma_mask,
>  ? ? ? ?}, {
>  ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_SDHCI,
>  ? ? ? ? ? ? ? ?.name ? = "s3c-sdhci",
>  ? ? ? ? ? ? ? ?.index ?= 2,
>  ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_HSMMC2,
>  ? ? ? ? ? ? ? ?.irq ? ?= IRQ_HSMMC1,
>  ? ? ? ? ? ? ? ?.dma ? ?= &samsung_std_dma_mask,
>  ? ? ? ?}, {
>  ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_OHCI,
>  ? ? ? ? ? ? ? ?.name ? = "s3c2410-ohci",
>  ? ? ? ? ? ? ? ?.index ?= -1,
>  ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_USBHOST,
>  ? ? ? ? ? ? ? ?.irq ? ?= IRQ_USBH,
>  ? ? ? ? ? ? ? ?.dma ? ?= &samsung_std_dma_mask,
>  ? ? ? ?}, {
>  ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_NAND,
>  ? ? ? ? ? ? ? ?.name ? = "s3c6400-nand",
>  ? ? ? ? ? ? ? ?.index ?= -1,
>  ? ? ? ? ? ? ? ?.base ? = 0x4E000000,
>  ? ? ? ? ? ? ? ?.irq ? ?= IRQ_NFC,
>  ? ? ? ?}, {
>  ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_I2C,
>  ? ? ? ? ? ? ? ?.name ? = "s3c2440-i2c",
>  ? ? ? ? ? ? ? ?.index ?= 0,
>  ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_IIC0,
>  ? ? ? ? ? ? ? ?.irq ? ?= IRQ_IIC,
>  ? ? ? ?}, {
> ...
>
> This solution is imho really clean an easy to understand. It is also
> easy to check which SoC has which peripherals defined and how.
>

Yep, this was already used in arch/arm/mach-mmp, and I wrote that.

It's actually an improved version of multiple platform_device.

> I hope Ben will be able to finish it soon and all Samsung platforms can
> be converted for it. Then creating a single kernel for more than one SoC
> should be possible with only a few additional changes.
>
>> PS: My feeling of commenting several of the samsung patches so far turns
>> out to be quite frustrated, or I'm just too sensitive. NOTE neither am I
>> NAKing Samsung patches, nor am I interested to be involved, I'm just givin
>> my suggestions.
>
> I'm sorry if I offended You. I just wanted to show that the solution has
> been already found.
>
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
>
>

From baruch at tkos.co.il  Wed Jun 23 06:31:26 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed, 23 Jun 2010 13:31:26 +0300
Subject: [PATCH 1/2] mx25: add iomux defines for UART4 on KPP pins
In-Reply-To: <cover.1277288487.git.baruch@tkos.co.il>
References: <cover.1277288487.git.baruch@tkos.co.il>
Message-ID: <c50a5b2770e542b5c55613d54fa5a46a0ac80a48.1277288487.git.baruch@tkos.co.il>

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 arch/arm/plat-mxc/include/mach/iomux-mx25.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index e88d01a..a2c2657 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -389,15 +389,19 @@
 #define MX25_PAD_KPP_ROW3__GPIO_3_0	IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_KPP_COL0__KPP_COL0	IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
 #define MX25_PAD_KPP_COL0__GPIO_3_1	IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_KPP_COL1__KPP_COL1	IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_KPP_COL1__GPIO_3_2	IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_KPP_COL2__KPP_COL2	IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL2__UART4_RTS	IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_KPP_COL2__GPIO_3_3	IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_KPP_COL3__KPP_COL3	IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, KPP_CTL_COL)
+#define MX25_PAD_KPP_COL3__UART4_CTS	IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_KPP_COL3__GPIO_3_4	IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_FEC_MDC__FEC_MDC	IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTRL)
-- 
1.7.1



From baruch at tkos.co.il  Wed Jun 23 06:31:25 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed, 23 Jun 2010 13:31:25 +0300
Subject: [PATCH 0/2] mx25: add iomux defines
Message-ID: <cover.1277288487.git.baruch@tkos.co.il>

This series adds some iomux defines needed for the UART4 and the PWM4 devices.

Baruch Siach (2):
  mx25: add iomux defines for UART4 on KPP pins
  mx25: add PWM4 to iomux

 arch/arm/plat-mxc/include/mach/iomux-mx25.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)



From baruch at tkos.co.il  Wed Jun 23 06:31:27 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed, 23 Jun 2010 13:31:27 +0300
Subject: [PATCH 2/2] mx25: add PWM4 to iomux
In-Reply-To: <cover.1277288487.git.baruch@tkos.co.il>
References: <cover.1277288487.git.baruch@tkos.co.il>
Message-ID: <49f1aee11be41447c2098f1eac5846e63b3ba24d.1277288487.git.baruch@tkos.co.il>

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 arch/arm/plat-mxc/include/mach/iomux-mx25.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index a2c2657..564e03d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -252,6 +252,7 @@
 #define MX25_PAD_OE_ACD__GPIO_1_25	IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CONTRAST__CONTRAST	IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CONTRAST__PWM4_PWMO	IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CONTRAST__FEC_CRS	IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
 
 #define MX25_PAD_PWM__PWM		IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
-- 
1.7.1



From eric.y.miao at gmail.com  Wed Jun 23 07:52:12 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 19:52:12 +0800
Subject: [PATCH 0/6] Cleanup of mach/io.h
Message-ID: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>

Some definitions can be made common, like IO_SPACE_LIMIT, some can
be removed, e.g. __mem_isa(), and some can be made into a machine
specific call, e.g. arch_adjust_zones()

Many mach/io.h can actually be safely removed, except for the
following definitions:

	__io()

and
	__arch_ioremap(), __arch_iounmap() and so on

__io() in the end can be made generic into something like:

#define __io(x)		((x) - physical_address_of_IO_space +
			       virtual_base)

and __arch_ioremap(), __arch_iounmap() made into machine specific
function (again?)



From eric.y.miao at gmail.com  Wed Jun 23 07:52:14 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 19:52:14 +0800
Subject: [PATCH 2/6] [ARM] footbridge: remove the useless definition of
	__mem_pci()
In-Reply-To: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
References: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1277293938-25804-3-git-send-email-eric.y.miao@gmail.com>

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/mach-footbridge/include/mach/io.h |   12 ------------
 1 files changed, 0 insertions(+), 12 deletions(-)

diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h
index c65ed51..d3b14d2 100644
--- a/arch/arm/mach-footbridge/include/mach/io.h
+++ b/arch/arm/mach-footbridge/include/mach/io.h
@@ -21,18 +21,6 @@
  * Translation of various region addresses to virtual addresses
  */
 #define __io(a)			((void __iomem *)(PCIO_BASE + (a)))
-#if 1
 #define __mem_pci(a)		(a)
-#else
-
-static inline void __iomem *___mem_pci(void __iomem *p)
-{
-	unsigned long a = (unsigned long)p;
-	BUG_ON(a <= 0xc0000000 || a >= 0xe0000000);
-	return p;
-}
-
-#define __mem_pci(a)		___mem_pci(a)
-#endif
 
 #endif
-- 
1.7.1



From eric.y.miao at gmail.com  Wed Jun 23 07:52:13 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 19:52:13 +0800
Subject: [PATCH 1/6] [ARM] Make common definition for IO_SPACE_LIMIT
In-Reply-To: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
References: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1277293938-25804-2-git-send-email-eric.y.miao@gmail.com>

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/include/asm/io.h                  |    2 ++
 arch/arm/mach-aaec2000/include/mach/io.h   |    2 --
 arch/arm/mach-at91/include/mach/io.h       |    2 --
 arch/arm/mach-bcmring/include/mach/io.h    |    2 --
 arch/arm/mach-clps711x/include/mach/io.h   |    2 --
 arch/arm/mach-cns3xxx/include/mach/io.h    |    2 --
 arch/arm/mach-davinci/include/mach/io.h    |    2 --
 arch/arm/mach-dove/include/mach/io.h       |    2 --
 arch/arm/mach-ebsa110/include/mach/io.h    |    2 --
 arch/arm/mach-ep93xx/include/mach/io.h     |    2 --
 arch/arm/mach-footbridge/include/mach/io.h |    2 --
 arch/arm/mach-gemini/include/mach/io.h     |    2 --
 arch/arm/mach-h720x/include/mach/io.h      |    2 --
 arch/arm/mach-integrator/include/mach/io.h |    2 --
 arch/arm/mach-iop13xx/include/mach/io.h    |    2 --
 arch/arm/mach-iop32x/include/mach/io.h     |    1 -
 arch/arm/mach-iop33x/include/mach/io.h     |    1 -
 arch/arm/mach-ixp2000/include/mach/io.h    |    1 -
 arch/arm/mach-ixp23xx/include/mach/io.h    |    2 --
 arch/arm/mach-ixp4xx/include/mach/io.h     |    2 --
 arch/arm/mach-kirkwood/include/mach/io.h   |    2 --
 arch/arm/mach-ks8695/include/mach/io.h     |    2 --
 arch/arm/mach-l7200/include/mach/io.h      |    2 --
 arch/arm/mach-lh7a40x/include/mach/io.h    |    2 --
 arch/arm/mach-loki/include/mach/io.h       |    2 --
 arch/arm/mach-mmp/include/mach/io.h        |    2 --
 arch/arm/mach-msm/include/mach/io.h        |    2 --
 arch/arm/mach-mv78xx0/include/mach/io.h    |    2 --
 arch/arm/mach-netx/include/mach/io.h       |    2 --
 arch/arm/mach-nomadik/include/mach/io.h    |    2 --
 arch/arm/mach-ns9xxx/include/mach/io.h     |    2 --
 arch/arm/mach-nuc93x/include/mach/io.h     |    2 --
 arch/arm/mach-orion5x/include/mach/io.h    |    2 --
 arch/arm/mach-pnx4008/include/mach/io.h    |    2 --
 arch/arm/mach-pxa/include/mach/io.h        |    2 --
 arch/arm/mach-realview/include/mach/io.h   |    2 --
 arch/arm/mach-rpc/include/mach/io.h        |    2 --
 arch/arm/mach-s3c2410/include/mach/io.h    |    2 --
 arch/arm/mach-s3c24a0/include/mach/io.h    |    2 --
 arch/arm/mach-s3c64xx/include/mach/io.h    |    2 --
 arch/arm/mach-s5p6440/include/mach/io.h    |    2 --
 arch/arm/mach-s5p6442/include/mach/io.h    |    2 --
 arch/arm/mach-s5pc100/include/mach/io.h    |    2 --
 arch/arm/mach-s5pv210/include/mach/io.h    |    2 --
 arch/arm/mach-sa1100/include/mach/io.h     |    2 --
 arch/arm/mach-shark/include/mach/io.h      |    2 --
 arch/arm/mach-shmobile/include/mach/io.h   |    2 --
 arch/arm/mach-u300/include/mach/io.h       |    2 --
 arch/arm/mach-ux500/include/mach/io.h      |    2 --
 arch/arm/mach-versatile/include/mach/io.h  |    2 --
 arch/arm/mach-vexpress/include/mach/io.h   |    2 --
 arch/arm/mach-w90x900/include/mach/io.h    |    2 --
 arch/arm/plat-mxc/include/mach/io.h        |    2 --
 arch/arm/plat-omap/include/plat/io.h       |    2 --
 arch/arm/plat-spear/include/plat/io.h      |    2 --
 arch/arm/plat-stmp3xxx/include/mach/io.h   |    2 --
 56 files changed, 2 insertions(+), 107 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index c980156..01eec09 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -99,6 +99,8 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
  */
 #include <mach/io.h>
 
+#define IO_SPACE_LIMIT	0xffffffff
+
 /*
  *  IO port access primitives
  *  -------------------------
diff --git a/arch/arm/mach-aaec2000/include/mach/io.h b/arch/arm/mach-aaec2000/include/mach/io.h
index ab4fe5d..ce19850 100644
--- a/arch/arm/mach-aaec2000/include/mach/io.h
+++ b/arch/arm/mach-aaec2000/include/mach/io.h
@@ -6,8 +6,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /*
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
index 0b0cccc..34740b5 100644
--- a/arch/arm/mach-at91/include/mach/io.h
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -21,8 +21,6 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT		0xFFFFFFFF
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
diff --git a/arch/arm/mach-bcmring/include/mach/io.h b/arch/arm/mach-bcmring/include/mach/io.h
index dae5e9b..1dba26d 100644
--- a/arch/arm/mach-bcmring/include/mach/io.h
+++ b/arch/arm/mach-bcmring/include/mach/io.h
@@ -21,8 +21,6 @@
 
 #include <mach/hardware.h>
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /*
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
diff --git a/arch/arm/mach-clps711x/include/mach/io.h b/arch/arm/mach-clps711x/include/mach/io.h
index 2e0b3ce..2e90452 100644
--- a/arch/arm/mach-clps711x/include/mach/io.h
+++ b/arch/arm/mach-clps711x/include/mach/io.h
@@ -20,8 +20,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
diff --git a/arch/arm/mach-cns3xxx/include/mach/io.h b/arch/arm/mach-cns3xxx/include/mach/io.h
index 33b6fc1..396b959 100644
--- a/arch/arm/mach-cns3xxx/include/mach/io.h
+++ b/arch/arm/mach-cns3xxx/include/mach/io.h
@@ -9,8 +9,6 @@
 #ifndef __MACH_IO_H
 #define __MACH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(a)			__typesafe_io(a)
 #define __mem_pci(a)		(a)
 
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index 62b0a90..29a866f 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -11,8 +11,6 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /*
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
index 3b3e472..eaacc2a 100644
--- a/arch/arm/mach-dove/include/mach/io.h
+++ b/arch/arm/mach-dove/include/mach/io.h
@@ -11,8 +11,6 @@
 
 #include "dove.h"
 
-#define IO_SPACE_LIMIT		0xffffffff
-
 #define __io(a)  ((void __iomem *)(((a) - DOVE_PCIE0_IO_PHYS_BASE) +\
 				   DOVE_PCIE0_IO_VIRT_BASE))
 #define __mem_pci(a)		(a)
diff --git a/arch/arm/mach-ebsa110/include/mach/io.h b/arch/arm/mach-ebsa110/include/mach/io.h
index f68daa6..44679db 100644
--- a/arch/arm/mach-ebsa110/include/mach/io.h
+++ b/arch/arm/mach-ebsa110/include/mach/io.h
@@ -13,8 +13,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffff
-
 u8 __inb8(unsigned int port);
 void __outb8(u8  val, unsigned int port);
 
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
index 594b77f..8931f94 100644
--- a/arch/arm/mach-ep93xx/include/mach/io.h
+++ b/arch/arm/mach-ep93xx/include/mach/io.h
@@ -5,8 +5,6 @@
 #ifndef __ASM_MACH_IO_H
 #define __ASM_MACH_IO_H
 
-#define IO_SPACE_LIMIT		0xffffffff
-
 #define __io(p)			__typesafe_io(p)
 #define __mem_pci(p)		(p)
 
diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h
index 101a4fe..c65ed51 100644
--- a/arch/arm/mach-footbridge/include/mach/io.h
+++ b/arch/arm/mach-footbridge/include/mach/io.h
@@ -17,8 +17,6 @@
 #define PCIO_SIZE		0x00100000
 #define PCIO_BASE		0xff000000
 
-#define IO_SPACE_LIMIT 0xffff
-
 /*
  * Translation of various region addresses to virtual addresses
  */
diff --git a/arch/arm/mach-gemini/include/mach/io.h b/arch/arm/mach-gemini/include/mach/io.h
index c548056..37b2896 100644
--- a/arch/arm/mach-gemini/include/mach/io.h
+++ b/arch/arm/mach-gemini/include/mach/io.h
@@ -10,8 +10,6 @@
 #ifndef __MACH_IO_H
 #define __MACH_IO_H
 
-#define IO_SPACE_LIMIT	0xffffffff
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
diff --git a/arch/arm/mach-h720x/include/mach/io.h b/arch/arm/mach-h720x/include/mach/io.h
index 2c8659c..1b2229f 100644
--- a/arch/arm/mach-h720x/include/mach/io.h
+++ b/arch/arm/mach-h720x/include/mach/io.h
@@ -14,8 +14,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h
index f21bb54..37beed3 100644
--- a/arch/arm/mach-integrator/include/mach/io.h
+++ b/arch/arm/mach-integrator/include/mach/io.h
@@ -20,8 +20,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffff
-
 /*
  * WARNING: this has to mirror definitions in platform.h
  */
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
index a6e0f9e..a9368e6 100644
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
@@ -19,8 +19,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(a) __iop13xx_io(a)
 #define __mem_pci(a) (a)
 #define __mem_isa(a) (a)
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
index 339e585..9ddc4df 100644
--- a/arch/arm/mach-iop32x/include/mach/io.h
+++ b/arch/arm/mach-iop32x/include/mach/io.h
@@ -17,7 +17,6 @@ extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
 	unsigned int mtype);
 extern void __iop3xx_iounmap(void __iomem *addr);
 
-#define IO_SPACE_LIMIT		0xffffffff
 #define __io(p)		((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
 #define __mem_pci(a)		(a)
 
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
index e99a7ed..9c1341d 100644
--- a/arch/arm/mach-iop33x/include/mach/io.h
+++ b/arch/arm/mach-iop33x/include/mach/io.h
@@ -17,7 +17,6 @@ extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
 	unsigned int mtype);
 extern void __iop3xx_iounmap(void __iomem *addr);
 
-#define IO_SPACE_LIMIT		0xffffffff
 #define __io(p)		((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
 #define __mem_pci(a)		(a)
 
diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h
index 859e584..e441d97 100644
--- a/arch/arm/mach-ixp2000/include/mach/io.h
+++ b/arch/arm/mach-ixp2000/include/mach/io.h
@@ -17,7 +17,6 @@
 
 #include <mach/hardware.h>
 
-#define IO_SPACE_LIMIT		0xffffffff
 #define __mem_pci(a)		(a)
 
 /*
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
index fd9ef8e..1e3752d 100644
--- a/arch/arm/mach-ixp23xx/include/mach/io.h
+++ b/arch/arm/mach-ixp23xx/include/mach/io.h
@@ -15,8 +15,6 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(p)		((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
 #define __mem_pci(a)	(a)
 
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 6ea7e2f..72af996 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -17,8 +17,6 @@
 
 #include <mach/hardware.h>
 
-#define IO_SPACE_LIMIT 0x0000ffff
-
 extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
 extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
 
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
index 44e8be0..68560bf 100644
--- a/arch/arm/mach-kirkwood/include/mach/io.h
+++ b/arch/arm/mach-kirkwood/include/mach/io.h
@@ -11,8 +11,6 @@
 
 #include "kirkwood.h"
 
-#define IO_SPACE_LIMIT		0xffffffff
-
 static inline void __iomem *__io(unsigned long addr)
 {
 	return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE)
diff --git a/arch/arm/mach-ks8695/include/mach/io.h b/arch/arm/mach-ks8695/include/mach/io.h
index a7a63ac..1b2e825 100644
--- a/arch/arm/mach-ks8695/include/mach/io.h
+++ b/arch/arm/mach-ks8695/include/mach/io.h
@@ -11,8 +11,6 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT		0xffffffff
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
diff --git a/arch/arm/mach-l7200/include/mach/io.h b/arch/arm/mach-l7200/include/mach/io.h
index a770a89..814c0b3 100644
--- a/arch/arm/mach-l7200/include/mach/io.h
+++ b/arch/arm/mach-l7200/include/mach/io.h
@@ -10,8 +10,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /*
  * There are not real ISA nor PCI buses, so we fake it.
  */
diff --git a/arch/arm/mach-lh7a40x/include/mach/io.h b/arch/arm/mach-lh7a40x/include/mach/io.h
index 6ece459..f64cde6 100644
--- a/arch/arm/mach-lh7a40x/include/mach/io.h
+++ b/arch/arm/mach-lh7a40x/include/mach/io.h
@@ -11,8 +11,6 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /* No ISA or PCI bus on this machine. */
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
diff --git a/arch/arm/mach-loki/include/mach/io.h b/arch/arm/mach-loki/include/mach/io.h
index a373cd5..ea63e33 100644
--- a/arch/arm/mach-loki/include/mach/io.h
+++ b/arch/arm/mach-loki/include/mach/io.h
@@ -11,8 +11,6 @@
 
 #include "loki.h"
 
-#define IO_SPACE_LIMIT		0xffffffff
-
 static inline void __iomem *__io(unsigned long addr)
 {
 	return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h
index e7adf3d..dc24d77 100644
--- a/arch/arm/mach-mmp/include/mach/io.h
+++ b/arch/arm/mach-mmp/include/mach/io.h
@@ -9,8 +9,6 @@
 #ifndef __ASM_MACH_IO_H
 #define __ASM_MACH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /*
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index c35b29f..40698df 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -16,8 +16,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __arch_ioremap __msm_ioremap
 #define __arch_iounmap __iounmap
 
diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h
index 450e0e1..a92df8c 100644
--- a/arch/arm/mach-mv78xx0/include/mach/io.h
+++ b/arch/arm/mach-mv78xx0/include/mach/io.h
@@ -11,8 +11,6 @@
 
 #include "mv78xx0.h"
 
-#define IO_SPACE_LIMIT		0xffffffff
-
 static inline void __iomem *__io(unsigned long addr)
 {
 	return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
diff --git a/arch/arm/mach-netx/include/mach/io.h b/arch/arm/mach-netx/include/mach/io.h
index c3921cb..a1b7e23 100644
--- a/arch/arm/mach-netx/include/mach/io.h
+++ b/arch/arm/mach-netx/include/mach/io.h
@@ -20,8 +20,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)            (a)
 
diff --git a/arch/arm/mach-nomadik/include/mach/io.h b/arch/arm/mach-nomadik/include/mach/io.h
index 2e1eca1..d988297 100644
--- a/arch/arm/mach-nomadik/include/mach/io.h
+++ b/arch/arm/mach-nomadik/include/mach/io.h
@@ -10,8 +10,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /*
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h
index f08451d..fb401c9 100644
--- a/arch/arm/mach-ns9xxx/include/mach/io.h
+++ b/arch/arm/mach-ns9xxx/include/mach/io.h
@@ -11,8 +11,6 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT  0xffffffff /* XXX */
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)    (a)
 #define __mem_isa(a)    (IO_BASE + (a))
diff --git a/arch/arm/mach-nuc93x/include/mach/io.h b/arch/arm/mach-nuc93x/include/mach/io.h
index 72e5051..2d0d853 100644
--- a/arch/arm/mach-nuc93x/include/mach/io.h
+++ b/arch/arm/mach-nuc93x/include/mach/io.h
@@ -16,8 +16,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT	0xffffffff
-
 /*
  * 1:1 mapping for ioremapped regions.
  */
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
index c47b033..839b888 100644
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ b/arch/arm/mach-orion5x/include/mach/io.h
@@ -13,8 +13,6 @@
 
 #include "orion5x.h"
 
-#define IO_SPACE_LIMIT		0xffffffff
-
 static inline void __iomem *
 __arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
 {
diff --git a/arch/arm/mach-pnx4008/include/mach/io.h b/arch/arm/mach-pnx4008/include/mach/io.h
index cbf0904..76d5bca 100644
--- a/arch/arm/mach-pnx4008/include/mach/io.h
+++ b/arch/arm/mach-pnx4008/include/mach/io.h
@@ -13,8 +13,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
index 262691f..fedd427 100644
--- a/arch/arm/mach-pxa/include/mach/io.h
+++ b/arch/arm/mach-pxa/include/mach/io.h
@@ -6,8 +6,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /*
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
diff --git a/arch/arm/mach-realview/include/mach/io.h b/arch/arm/mach-realview/include/mach/io.h
index f05bcdf..2bdf15d 100644
--- a/arch/arm/mach-realview/include/mach/io.h
+++ b/arch/arm/mach-realview/include/mach/io.h
@@ -20,8 +20,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
diff --git a/arch/arm/mach-rpc/include/mach/io.h b/arch/arm/mach-rpc/include/mach/io.h
index 20da7f4..3ccc17d 100644
--- a/arch/arm/mach-rpc/include/mach/io.h
+++ b/arch/arm/mach-rpc/include/mach/io.h
@@ -15,8 +15,6 @@
 
 #include <mach/hardware.h>
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /*
  * We use two different types of addressing - PC style addresses, and ARM
  * addresses.  PC style accesses the PC hardware with the normal PC IO
diff --git a/arch/arm/mach-s3c2410/include/mach/io.h b/arch/arm/mach-s3c2410/include/mach/io.h
index 9813dbf..d9ba838 100644
--- a/arch/arm/mach-s3c2410/include/mach/io.h
+++ b/arch/arm/mach-s3c2410/include/mach/io.h
@@ -11,8 +11,6 @@
 
 #include <mach/hardware.h>
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /*
  * We use two different types of addressing - PC style addresses, and ARM
  * addresses.  PC style accesses the PC hardware with the normal PC IO
diff --git a/arch/arm/mach-s3c24a0/include/mach/io.h b/arch/arm/mach-s3c24a0/include/mach/io.h
index 4326c30..4ad89b9 100644
--- a/arch/arm/mach-s3c24a0/include/mach/io.h
+++ b/arch/arm/mach-s3c24a0/include/mach/io.h
@@ -13,6 +13,4 @@
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
 #endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/io.h b/arch/arm/mach-s3c64xx/include/mach/io.h
index de5716d..1e9625c 100644
--- a/arch/arm/mach-s3c64xx/include/mach/io.h
+++ b/arch/arm/mach-s3c64xx/include/mach/io.h
@@ -13,6 +13,4 @@
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
 #endif
diff --git a/arch/arm/mach-s5p6440/include/mach/io.h b/arch/arm/mach-s5p6440/include/mach/io.h
index fa2d69c..72611ec 100644
--- a/arch/arm/mach-s5p6440/include/mach/io.h
+++ b/arch/arm/mach-s5p6440/include/mach/io.h
@@ -13,6 +13,4 @@
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
 #endif
diff --git a/arch/arm/mach-s5p6442/include/mach/io.h b/arch/arm/mach-s5p6442/include/mach/io.h
index 5d2195a..7c1cb7c 100644
--- a/arch/arm/mach-s5p6442/include/mach/io.h
+++ b/arch/arm/mach-s5p6442/include/mach/io.h
@@ -12,6 +12,4 @@
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
 #endif
diff --git a/arch/arm/mach-s5pc100/include/mach/io.h b/arch/arm/mach-s5pc100/include/mach/io.h
index 819acf5..25a0e92 100644
--- a/arch/arm/mach-s5pc100/include/mach/io.h
+++ b/arch/arm/mach-s5pc100/include/mach/io.h
@@ -13,6 +13,4 @@
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
 #endif
diff --git a/arch/arm/mach-s5pv210/include/mach/io.h b/arch/arm/mach-s5pv210/include/mach/io.h
index 5ab9d56..32ff10e 100644
--- a/arch/arm/mach-s5pv210/include/mach/io.h
+++ b/arch/arm/mach-s5pv210/include/mach/io.h
@@ -21,6 +21,4 @@
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
 #endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h
index d8b43f3..bb1be3f 100644
--- a/arch/arm/mach-sa1100/include/mach/io.h
+++ b/arch/arm/mach-sa1100/include/mach/io.h
@@ -10,8 +10,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /*
  * We don't actually have real ISA nor PCI buses, but there is so many 
  * drivers out there that might just work if we fake them...
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h
index 9ccbcec..9e09e10 100644
--- a/arch/arm/mach-shark/include/mach/io.h
+++ b/arch/arm/mach-shark/include/mach/io.h
@@ -11,8 +11,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(a)                 ((void __iomem *)(0xe0000000 + (a)))
 
 #define __mem_pci(addr) (addr)
diff --git a/arch/arm/mach-shmobile/include/mach/io.h b/arch/arm/mach-shmobile/include/mach/io.h
index 7339fe4..7b4d896 100644
--- a/arch/arm/mach-shmobile/include/mach/io.h
+++ b/arch/arm/mach-shmobile/include/mach/io.h
@@ -1,8 +1,6 @@
 #ifndef __ASM_MACH_IO_H
 #define __ASM_MACH_IO_H
 
-#define IO_SPACE_LIMIT		0xffffffff
-
 #define __io(a)			((void __iomem *)(a))
 #define __mem_pci(a)		(a)
 
diff --git a/arch/arm/mach-u300/include/mach/io.h b/arch/arm/mach-u300/include/mach/io.h
index 5d6b4c1..49a1ceb 100644
--- a/arch/arm/mach-u300/include/mach/io.h
+++ b/arch/arm/mach-u300/include/mach/io.h
@@ -12,8 +12,6 @@
 #ifndef __MACH_IO_H
 #define __MACH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h
index 1cf3f44..03504ff 100644
--- a/arch/arm/mach-ux500/include/mach/io.h
+++ b/arch/arm/mach-ux500/include/mach/io.h
@@ -10,8 +10,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /*
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
index f067c14..e87fb4a 100644
--- a/arch/arm/mach-versatile/include/mach/io.h
+++ b/arch/arm/mach-versatile/include/mach/io.h
@@ -20,8 +20,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
diff --git a/arch/arm/mach-vexpress/include/mach/io.h b/arch/arm/mach-vexpress/include/mach/io.h
index 748bb52..13522d8 100644
--- a/arch/arm/mach-vexpress/include/mach/io.h
+++ b/arch/arm/mach-vexpress/include/mach/io.h
@@ -20,8 +20,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)	(a)
 
diff --git a/arch/arm/mach-w90x900/include/mach/io.h b/arch/arm/mach-w90x900/include/mach/io.h
index d96ab99..062d401 100644
--- a/arch/arm/mach-w90x900/include/mach/io.h
+++ b/arch/arm/mach-w90x900/include/mach/io.h
@@ -18,8 +18,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT	0xffffffff
-
 /*
  * 1:1 mapping for ioremapped regions.
  */
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index b4f2de7..18ab5ff 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -12,8 +12,6 @@
 #define __ASM_ARCH_MXC_IO_H__
 
 /* Allow IO space to be anywhere in the memory */
-#define IO_SPACE_LIMIT 0xffffffff
-
 #ifdef CONFIG_ARCH_MX3
 #define __arch_ioremap __mx3_ioremap
 #define __arch_iounmap __iounmap
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index 128b549..bb3f68f 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -39,8 +39,6 @@
 
 #include <mach/hardware.h>
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 /*
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
diff --git a/arch/arm/plat-spear/include/plat/io.h b/arch/arm/plat-spear/include/plat/io.h
index 4d4ba82..4358221 100644
--- a/arch/arm/plat-spear/include/plat/io.h
+++ b/arch/arm/plat-spear/include/plat/io.h
@@ -14,8 +14,6 @@
 #ifndef __PLAT_IO_H
 #define __PLAT_IO_H
 
-#define IO_SPACE_LIMIT		0xFFFFFFFF
-
 #define __io(a)			__typesafe_io(a)
 #define __mem_pci(a)		(a)
 
diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h
index d08b1b7..ccf0246 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/io.h
+++ b/arch/arm/plat-stmp3xxx/include/mach/io.h
@@ -16,8 +16,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define IO_SPACE_LIMIT 0xffffffff
-
 #define __io(a) 	__typesafe_io(a)
 #define __mem_pci(a)	(a)
 #define __mem_isa(a)	(a)
-- 
1.7.1



From eric.y.miao at gmail.com  Wed Jun 23 07:52:15 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 19:52:15 +0800
Subject: [PATCH 3/6] [ARM] Make __mem_pci() common to all ARM sub-architectures
In-Reply-To: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
References: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1277293938-25804-4-git-send-email-eric.y.miao@gmail.com>

On all ARM sub-architectures, __mem_pci() is defined to be a 1:1
mapping, make it a common definition for all.

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/include/asm/io.h                  |    4 ++++
 arch/arm/mach-aaec2000/include/mach/io.h   |    2 --
 arch/arm/mach-at91/include/mach/io.h       |    2 --
 arch/arm/mach-bcmring/include/mach/io.h    |    2 --
 arch/arm/mach-clps711x/include/mach/io.h   |    2 --
 arch/arm/mach-cns3xxx/include/mach/io.h    |    2 --
 arch/arm/mach-davinci/include/mach/io.h    |    1 -
 arch/arm/mach-dove/include/mach/io.h       |    2 --
 arch/arm/mach-ep93xx/include/mach/io.h     |    2 --
 arch/arm/mach-footbridge/include/mach/io.h |    2 --
 arch/arm/mach-gemini/include/mach/io.h     |    2 --
 arch/arm/mach-h720x/include/mach/io.h      |    2 --
 arch/arm/mach-integrator/include/mach/io.h |    2 --
 arch/arm/mach-iop13xx/include/mach/io.h    |    1 -
 arch/arm/mach-iop32x/include/mach/io.h     |    2 --
 arch/arm/mach-iop33x/include/mach/io.h     |    2 --
 arch/arm/mach-ixp2000/include/mach/io.h    |    2 --
 arch/arm/mach-ixp23xx/include/mach/io.h    |    2 --
 arch/arm/mach-ixp4xx/include/mach/io.h     |    2 --
 arch/arm/mach-kirkwood/include/mach/io.h   |    2 --
 arch/arm/mach-ks8695/include/mach/io.h     |    2 --
 arch/arm/mach-l7200/include/mach/io.h      |    2 --
 arch/arm/mach-lh7a40x/include/mach/io.h    |    2 --
 arch/arm/mach-loki/include/mach/io.h       |    2 --
 arch/arm/mach-mmp/include/mach/io.h        |    2 --
 arch/arm/mach-msm/include/mach/io.h        |    2 --
 arch/arm/mach-mv78xx0/include/mach/io.h    |    2 --
 arch/arm/mach-netx/include/mach/io.h       |    2 --
 arch/arm/mach-nomadik/include/mach/io.h    |    2 --
 arch/arm/mach-ns9xxx/include/mach/io.h     |    1 -
 arch/arm/mach-nuc93x/include/mach/io.h     |    1 -
 arch/arm/mach-orion5x/include/mach/io.h    |    2 --
 arch/arm/mach-pnx4008/include/mach/io.h    |    2 --
 arch/arm/mach-pxa/include/mach/io.h        |    2 --
 arch/arm/mach-realview/include/mach/io.h   |    2 --
 arch/arm/mach-rpc/include/mach/io.h        |    2 --
 arch/arm/mach-s3c2410/include/mach/io.h    |    2 --
 arch/arm/mach-s3c24a0/include/mach/io.h    |    2 --
 arch/arm/mach-s3c64xx/include/mach/io.h    |    2 --
 arch/arm/mach-s5p6440/include/mach/io.h    |    2 --
 arch/arm/mach-s5p6442/include/mach/io.h    |    2 --
 arch/arm/mach-s5pc100/include/mach/io.h    |    2 --
 arch/arm/mach-s5pv210/include/mach/io.h    |    2 --
 arch/arm/mach-sa1100/include/mach/io.h     |    2 --
 arch/arm/mach-shark/include/mach/io.h      |    2 --
 arch/arm/mach-shmobile/include/mach/io.h   |    2 --
 arch/arm/mach-u300/include/mach/io.h       |    2 --
 arch/arm/mach-ux500/include/mach/io.h      |    2 --
 arch/arm/mach-versatile/include/mach/io.h  |    2 --
 arch/arm/mach-vexpress/include/mach/io.h   |    2 --
 arch/arm/mach-w90x900/include/mach/io.h    |    1 -
 arch/arm/plat-mxc/include/mach/io.h        |    2 --
 arch/arm/plat-omap/include/plat/io.h       |    2 --
 arch/arm/plat-spear/include/plat/io.h      |    2 --
 arch/arm/plat-stmp3xxx/include/mach/io.h   |    1 -
 55 files changed, 4 insertions(+), 102 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 01eec09..c5b8803 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -101,6 +101,10 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 
 #define IO_SPACE_LIMIT	0xffffffff
 
+#ifndef __mem_pci
+#define __mem_pci(a)	(a)
+#endif
+
 /*
  *  IO port access primitives
  *  -------------------------
diff --git a/arch/arm/mach-aaec2000/include/mach/io.h b/arch/arm/mach-aaec2000/include/mach/io.h
index ce19850..8b9193d 100644
--- a/arch/arm/mach-aaec2000/include/mach/io.h
+++ b/arch/arm/mach-aaec2000/include/mach/io.h
@@ -11,6 +11,4 @@
  * drivers out there that might just work if we fake them...
  */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
index 34740b5..ab014c0 100644
--- a/arch/arm/mach-at91/include/mach/io.h
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -22,8 +22,6 @@
 #define __ASM_ARCH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/mach-bcmring/include/mach/io.h b/arch/arm/mach-bcmring/include/mach/io.h
index 1dba26d..3357d80 100644
--- a/arch/arm/mach-bcmring/include/mach/io.h
+++ b/arch/arm/mach-bcmring/include/mach/io.h
@@ -26,6 +26,4 @@
  * drivers out there that might just work if we fake them...
  */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/io.h b/arch/arm/mach-clps711x/include/mach/io.h
index 2e90452..83980b6 100644
--- a/arch/arm/mach-clps711x/include/mach/io.h
+++ b/arch/arm/mach-clps711x/include/mach/io.h
@@ -21,8 +21,6 @@
 #define __ASM_ARM_ARCH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 /*
  * We don't support ins[lb]/outs[lb].  Make them fault.
  */
diff --git a/arch/arm/mach-cns3xxx/include/mach/io.h b/arch/arm/mach-cns3xxx/include/mach/io.h
index 396b959..be5a0d2 100644
--- a/arch/arm/mach-cns3xxx/include/mach/io.h
+++ b/arch/arm/mach-cns3xxx/include/mach/io.h
@@ -10,6 +10,4 @@
 #define __MACH_IO_H
 
 #define __io(a)			__typesafe_io(a)
-#define __mem_pci(a)		(a)
-
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index 29a866f..71d6a0d 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -16,7 +16,6 @@
  * drivers out there that might just work if we fake them...
  */
 #define __io(a)			__typesafe_io(a)
-#define __mem_pci(a)		(a)
 #define __mem_isa(a)		(a)
 
 #ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
index eaacc2a..db0cf90 100644
--- a/arch/arm/mach-dove/include/mach/io.h
+++ b/arch/arm/mach-dove/include/mach/io.h
@@ -13,6 +13,4 @@
 
 #define __io(a)  ((void __iomem *)(((a) - DOVE_PCIE0_IO_PHYS_BASE) +\
 				   DOVE_PCIE0_IO_VIRT_BASE))
-#define __mem_pci(a)		(a)
-
 #endif
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
index 8931f94..b63e543 100644
--- a/arch/arm/mach-ep93xx/include/mach/io.h
+++ b/arch/arm/mach-ep93xx/include/mach/io.h
@@ -6,8 +6,6 @@
 #define __ASM_MACH_IO_H
 
 #define __io(p)			__typesafe_io(p)
-#define __mem_pci(p)		(p)
-
 /*
  * A typesafe __io() variation for variable initialisers
  */
diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h
index d3b14d2..6a030d5 100644
--- a/arch/arm/mach-footbridge/include/mach/io.h
+++ b/arch/arm/mach-footbridge/include/mach/io.h
@@ -21,6 +21,4 @@
  * Translation of various region addresses to virtual addresses
  */
 #define __io(a)			((void __iomem *)(PCIO_BASE + (a)))
-#define __mem_pci(a)		(a)
-
 #endif
diff --git a/arch/arm/mach-gemini/include/mach/io.h b/arch/arm/mach-gemini/include/mach/io.h
index 37b2896..9925714 100644
--- a/arch/arm/mach-gemini/include/mach/io.h
+++ b/arch/arm/mach-gemini/include/mach/io.h
@@ -11,6 +11,4 @@
 #define __MACH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-h720x/include/mach/io.h b/arch/arm/mach-h720x/include/mach/io.h
index 1b2229f..8745f59 100644
--- a/arch/arm/mach-h720x/include/mach/io.h
+++ b/arch/arm/mach-h720x/include/mach/io.h
@@ -15,6 +15,4 @@
 #define __ASM_ARM_ARCH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h
index 37beed3..de4ae05 100644
--- a/arch/arm/mach-integrator/include/mach/io.h
+++ b/arch/arm/mach-integrator/include/mach/io.h
@@ -29,6 +29,4 @@
 #define PCI_IO_VADDR            0xee000000
 
 #define __io(a)			((void __iomem *)(PCI_IO_VADDR + (a)))
-#define __mem_pci(a)		(a)
-
 #endif
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
index a9368e6..c1387df 100644
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
@@ -20,7 +20,6 @@
 #define __ASM_ARM_ARCH_IO_H
 
 #define __io(a) __iop13xx_io(a)
-#define __mem_pci(a) (a)
 #define __mem_isa(a) (a)
 
 extern void __iomem * __iop13xx_io(unsigned long io_addr);
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
index 9ddc4df..907516a 100644
--- a/arch/arm/mach-iop32x/include/mach/io.h
+++ b/arch/arm/mach-iop32x/include/mach/io.h
@@ -18,8 +18,6 @@ extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
 extern void __iop3xx_iounmap(void __iomem *addr);
 
 #define __io(p)		((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-#define __mem_pci(a)		(a)
-
 #define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f)
 #define __arch_iounmap(a)	 __iop3xx_iounmap(a)
 
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
index 9c1341d..0c0dad4 100644
--- a/arch/arm/mach-iop33x/include/mach/io.h
+++ b/arch/arm/mach-iop33x/include/mach/io.h
@@ -18,8 +18,6 @@ extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
 extern void __iop3xx_iounmap(void __iomem *addr);
 
 #define __io(p)		((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-#define __mem_pci(a)		(a)
-
 #define __arch_ioremap(a, s, f) __iop3xx_ioremap(a, s, f)
 #define __arch_iounmap(a)	 __iop3xx_iounmap(a)
 
diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h
index e441d97..7898788 100644
--- a/arch/arm/mach-ixp2000/include/mach/io.h
+++ b/arch/arm/mach-ixp2000/include/mach/io.h
@@ -17,8 +17,6 @@
 
 #include <mach/hardware.h>
 
-#define __mem_pci(a)		(a)
-
 /*
  * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
  * transactions the other way round (MEM transactions don't have this
diff --git a/arch/arm/mach-ixp23xx/include/mach/io.h b/arch/arm/mach-ixp23xx/include/mach/io.h
index 1e3752d..5d0f0b4 100644
--- a/arch/arm/mach-ixp23xx/include/mach/io.h
+++ b/arch/arm/mach-ixp23xx/include/mach/io.h
@@ -16,8 +16,6 @@
 #define __ASM_ARCH_IO_H
 
 #define __io(p)		((void __iomem*)((p) + IXP23XX_PCI_IO_VIRT))
-#define __mem_pci(a)	(a)
-
 static inline void __iomem *
 ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype)
 {
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 72af996..7489f8f 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -41,8 +41,6 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
  */
 #ifndef	CONFIG_IXP4XX_INDIRECT_PCI
 
-#define __mem_pci(a)		(a)
-
 #else
 
 /*
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
index 68560bf..be41fb2 100644
--- a/arch/arm/mach-kirkwood/include/mach/io.h
+++ b/arch/arm/mach-kirkwood/include/mach/io.h
@@ -43,7 +43,5 @@ __arch_iounmap(void __iomem *addr)
 #define __arch_ioremap(p, s, m)	__arch_ioremap(p, s, m)
 #define __arch_iounmap(a)	__arch_iounmap(a)
 #define __io(a)			__io(a)
-#define __mem_pci(a)		(a)
-
 
 #endif
diff --git a/arch/arm/mach-ks8695/include/mach/io.h b/arch/arm/mach-ks8695/include/mach/io.h
index 1b2e825..d2029d3 100644
--- a/arch/arm/mach-ks8695/include/mach/io.h
+++ b/arch/arm/mach-ks8695/include/mach/io.h
@@ -12,6 +12,4 @@
 #define __ASM_ARCH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-l7200/include/mach/io.h b/arch/arm/mach-l7200/include/mach/io.h
index 814c0b3..13b6e5c 100644
--- a/arch/arm/mach-l7200/include/mach/io.h
+++ b/arch/arm/mach-l7200/include/mach/io.h
@@ -14,6 +14,4 @@
  * There are not real ISA nor PCI buses, so we fake it.
  */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-lh7a40x/include/mach/io.h b/arch/arm/mach-lh7a40x/include/mach/io.h
index f64cde6..4de858b 100644
--- a/arch/arm/mach-lh7a40x/include/mach/io.h
+++ b/arch/arm/mach-lh7a40x/include/mach/io.h
@@ -13,6 +13,4 @@
 
 /* No ISA or PCI bus on this machine. */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-loki/include/mach/io.h b/arch/arm/mach-loki/include/mach/io.h
index ea63e33..b35cdf6 100644
--- a/arch/arm/mach-loki/include/mach/io.h
+++ b/arch/arm/mach-loki/include/mach/io.h
@@ -18,7 +18,5 @@ static inline void __iomem *__io(unsigned long addr)
 }
 
 #define __io(a)			__io(a)
-#define __mem_pci(a)		(a)
-
 
 #endif
diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h
index dc24d77..e9581d5 100644
--- a/arch/arm/mach-mmp/include/mach/io.h
+++ b/arch/arm/mach-mmp/include/mach/io.h
@@ -14,6 +14,4 @@
  * drivers out there that might just work if we fake them...
  */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index 40698df..5e0e93d 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -22,8 +22,6 @@
 void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)    (a)
-
 void msm_map_qsd8x50_io(void);
 void msm_map_msm7x30_io(void);
 
diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h
index a92df8c..da6fa21 100644
--- a/arch/arm/mach-mv78xx0/include/mach/io.h
+++ b/arch/arm/mach-mv78xx0/include/mach/io.h
@@ -18,7 +18,5 @@ static inline void __iomem *__io(unsigned long addr)
 }
 
 #define __io(a)			__io(a)
-#define __mem_pci(a)		(a)
-
 
 #endif
diff --git a/arch/arm/mach-netx/include/mach/io.h b/arch/arm/mach-netx/include/mach/io.h
index a1b7e23..ac134a8 100644
--- a/arch/arm/mach-netx/include/mach/io.h
+++ b/arch/arm/mach-netx/include/mach/io.h
@@ -21,6 +21,4 @@
 #define __ASM_ARM_ARCH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)            (a)
-
 #endif
diff --git a/arch/arm/mach-nomadik/include/mach/io.h b/arch/arm/mach-nomadik/include/mach/io.h
index d988297..a2b9e1a 100644
--- a/arch/arm/mach-nomadik/include/mach/io.h
+++ b/arch/arm/mach-nomadik/include/mach/io.h
@@ -15,6 +15,4 @@
  * drivers out there that might just work if we fake them...
  */
 #define __io(a)         __typesafe_io(a)
-#define __mem_pci(a)    (a)
-
 #endif
diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h
index fb401c9..edb9cdd 100644
--- a/arch/arm/mach-ns9xxx/include/mach/io.h
+++ b/arch/arm/mach-ns9xxx/include/mach/io.h
@@ -12,7 +12,6 @@
 #define __ASM_ARCH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)    (a)
 #define __mem_isa(a)    (IO_BASE + (a))
 
 #endif /* ifndef __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/io.h b/arch/arm/mach-nuc93x/include/mach/io.h
index 2d0d853..99fe76d 100644
--- a/arch/arm/mach-nuc93x/include/mach/io.h
+++ b/arch/arm/mach-nuc93x/include/mach/io.h
@@ -20,7 +20,6 @@
  * 1:1 mapping for ioremapped regions.
  */
 
-#define __mem_pci(a)	(a)
 #define __io(a)		__typesafe_io(a)
 
 #endif
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
index 839b888..34c2a5c 100644
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ b/arch/arm/mach-orion5x/include/mach/io.h
@@ -39,8 +39,6 @@ __arch_iounmap(void __iomem *addr)
 #define __arch_ioremap(p, s, m)	__arch_ioremap(p, s, m)
 #define __arch_iounmap(a)	__arch_iounmap(a)
 #define __io(a)			__typesafe_io(a)
-#define __mem_pci(a)		(a)
-
 
 /*****************************************************************************
  * Helpers to access Orion registers
diff --git a/arch/arm/mach-pnx4008/include/mach/io.h b/arch/arm/mach-pnx4008/include/mach/io.h
index 76d5bca..bd655e5 100644
--- a/arch/arm/mach-pnx4008/include/mach/io.h
+++ b/arch/arm/mach-pnx4008/include/mach/io.h
@@ -14,6 +14,4 @@
 #define __ASM_ARM_ARCH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
index fedd427..5bfd427 100644
--- a/arch/arm/mach-pxa/include/mach/io.h
+++ b/arch/arm/mach-pxa/include/mach/io.h
@@ -11,6 +11,4 @@
  * drivers out there that might just work if we fake them...
  */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-realview/include/mach/io.h b/arch/arm/mach-realview/include/mach/io.h
index 2bdf15d..cc45381 100644
--- a/arch/arm/mach-realview/include/mach/io.h
+++ b/arch/arm/mach-realview/include/mach/io.h
@@ -21,6 +21,4 @@
 #define __ASM_ARM_ARCH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-rpc/include/mach/io.h b/arch/arm/mach-rpc/include/mach/io.h
index 3ccc17d..5881e43 100644
--- a/arch/arm/mach-rpc/include/mach/io.h
+++ b/arch/arm/mach-rpc/include/mach/io.h
@@ -206,6 +206,4 @@ DECLARE_IO(int,l,"")
 /*
  * 1:1 mapping for ioremapped regions.
  */
-#define __mem_pci(x)	(x)
-
 #endif
diff --git a/arch/arm/mach-s3c2410/include/mach/io.h b/arch/arm/mach-s3c2410/include/mach/io.h
index d9ba838..7ff5def 100644
--- a/arch/arm/mach-s3c2410/include/mach/io.h
+++ b/arch/arm/mach-s3c2410/include/mach/io.h
@@ -211,6 +211,4 @@ DECLARE_IO(int,l,"")
 /*
  * 1:1 mapping for ioremapped regions.
  */
-#define __mem_pci(x)	(x)
-
 #endif
diff --git a/arch/arm/mach-s3c24a0/include/mach/io.h b/arch/arm/mach-s3c24a0/include/mach/io.h
index 4ad89b9..e04664f 100644
--- a/arch/arm/mach-s3c24a0/include/mach/io.h
+++ b/arch/arm/mach-s3c24a0/include/mach/io.h
@@ -11,6 +11,4 @@
 
 /* No current ISA/PCI bus support. */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/io.h b/arch/arm/mach-s3c64xx/include/mach/io.h
index 1e9625c..eb4dae8 100644
--- a/arch/arm/mach-s3c64xx/include/mach/io.h
+++ b/arch/arm/mach-s3c64xx/include/mach/io.h
@@ -11,6 +11,4 @@
 
 /* No current ISA/PCI bus support. */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-s5p6440/include/mach/io.h b/arch/arm/mach-s5p6440/include/mach/io.h
index 72611ec..10e18d3 100644
--- a/arch/arm/mach-s5p6440/include/mach/io.h
+++ b/arch/arm/mach-s5p6440/include/mach/io.h
@@ -11,6 +11,4 @@
 
 /* No current ISA/PCI bus support. */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-s5p6442/include/mach/io.h b/arch/arm/mach-s5p6442/include/mach/io.h
index 7c1cb7c..02cacba 100644
--- a/arch/arm/mach-s5p6442/include/mach/io.h
+++ b/arch/arm/mach-s5p6442/include/mach/io.h
@@ -10,6 +10,4 @@
 
 /* No current ISA/PCI bus support. */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-s5pc100/include/mach/io.h b/arch/arm/mach-s5pc100/include/mach/io.h
index 25a0e92..d0970e4 100644
--- a/arch/arm/mach-s5pc100/include/mach/io.h
+++ b/arch/arm/mach-s5pc100/include/mach/io.h
@@ -11,6 +11,4 @@
 
 /* No current ISA/PCI bus support. */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-s5pv210/include/mach/io.h b/arch/arm/mach-s5pv210/include/mach/io.h
index 32ff10e..f80590e 100644
--- a/arch/arm/mach-s5pv210/include/mach/io.h
+++ b/arch/arm/mach-s5pv210/include/mach/io.h
@@ -19,6 +19,4 @@
 
 /* No current ISA/PCI bus support. */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h
index bb1be3f..0817eb0 100644
--- a/arch/arm/mach-sa1100/include/mach/io.h
+++ b/arch/arm/mach-sa1100/include/mach/io.h
@@ -15,6 +15,4 @@
  * drivers out there that might just work if we fake them...
  */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h
index 9e09e10..0950cc1 100644
--- a/arch/arm/mach-shark/include/mach/io.h
+++ b/arch/arm/mach-shark/include/mach/io.h
@@ -13,6 +13,4 @@
 
 #define __io(a)                 ((void __iomem *)(0xe0000000 + (a)))
 
-#define __mem_pci(addr) (addr)
-
 #endif
diff --git a/arch/arm/mach-shmobile/include/mach/io.h b/arch/arm/mach-shmobile/include/mach/io.h
index 7b4d896..3e29649 100644
--- a/arch/arm/mach-shmobile/include/mach/io.h
+++ b/arch/arm/mach-shmobile/include/mach/io.h
@@ -2,6 +2,4 @@
 #define __ASM_MACH_IO_H
 
 #define __io(a)			((void __iomem *)(a))
-#define __mem_pci(a)		(a)
-
 #endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-u300/include/mach/io.h b/arch/arm/mach-u300/include/mach/io.h
index 49a1ceb..6770eea 100644
--- a/arch/arm/mach-u300/include/mach/io.h
+++ b/arch/arm/mach-u300/include/mach/io.h
@@ -13,6 +13,4 @@
 #define __MACH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h
index 03504ff..16acb3b 100644
--- a/arch/arm/mach-ux500/include/mach/io.h
+++ b/arch/arm/mach-ux500/include/mach/io.h
@@ -15,6 +15,4 @@
  * drivers out there that might just work if we fake them...
  */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
index e87fb4a..25c902a 100644
--- a/arch/arm/mach-versatile/include/mach/io.h
+++ b/arch/arm/mach-versatile/include/mach/io.h
@@ -21,6 +21,4 @@
 #define __ASM_ARM_ARCH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-vexpress/include/mach/io.h b/arch/arm/mach-vexpress/include/mach/io.h
index 13522d8..2b73325 100644
--- a/arch/arm/mach-vexpress/include/mach/io.h
+++ b/arch/arm/mach-vexpress/include/mach/io.h
@@ -21,6 +21,4 @@
 #define __ASM_ARM_ARCH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/mach-w90x900/include/mach/io.h b/arch/arm/mach-w90x900/include/mach/io.h
index 062d401..272f76b 100644
--- a/arch/arm/mach-w90x900/include/mach/io.h
+++ b/arch/arm/mach-w90x900/include/mach/io.h
@@ -22,7 +22,6 @@
  * 1:1 mapping for ioremapped regions.
  */
 
-#define __mem_pci(a)	(a)
 #define __io(a)		__typesafe_io(a)
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index 18ab5ff..ed05017 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -35,6 +35,4 @@ __mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 /* io address mapping macro */
 #define __io(a)		__typesafe_io(a)
 
-#define __mem_pci(a)	(a)
-
 #endif
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index bb3f68f..a9beb3c 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -44,8 +44,6 @@
  * drivers out there that might just work if we fake them...
  */
 #define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
 /*
  * ----------------------------------------------------------------------------
  * I/O mapping
diff --git a/arch/arm/plat-spear/include/plat/io.h b/arch/arm/plat-spear/include/plat/io.h
index 4358221..faf8e7e 100644
--- a/arch/arm/plat-spear/include/plat/io.h
+++ b/arch/arm/plat-spear/include/plat/io.h
@@ -15,6 +15,4 @@
 #define __PLAT_IO_H
 
 #define __io(a)			__typesafe_io(a)
-#define __mem_pci(a)		(a)
-
 #endif /* __PLAT_IO_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h
index ccf0246..73817a1 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/io.h
+++ b/arch/arm/plat-stmp3xxx/include/mach/io.h
@@ -17,7 +17,6 @@
 #define __ASM_ARM_ARCH_IO_H
 
 #define __io(a) 	__typesafe_io(a)
-#define __mem_pci(a)	(a)
 #define __mem_isa(a)	(a)
 
 #endif
-- 
1.7.1



From eric.y.miao at gmail.com  Wed Jun 23 07:52:16 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 19:52:16 +0800
Subject: [PATCH 4/6] [ARM] Remove useless __mem_isa() definitions
In-Reply-To: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
References: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1277293938-25804-5-git-send-email-eric.y.miao@gmail.com>

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/mach-davinci/include/mach/io.h  |    1 -
 arch/arm/mach-iop13xx/include/mach/io.h  |    1 -
 arch/arm/mach-ns9xxx/include/mach/io.h   |    1 -
 arch/arm/plat-stmp3xxx/include/mach/io.h |    1 -
 4 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index 71d6a0d..078d939 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -16,7 +16,6 @@
  * drivers out there that might just work if we fake them...
  */
 #define __io(a)			__typesafe_io(a)
-#define __mem_isa(a)		(a)
 
 #ifndef __ASSEMBLER__
 #define __arch_ioremap(p, s, t)	davinci_ioremap(p, s, t)
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
index c1387df..9a360c0 100644
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
@@ -20,7 +20,6 @@
 #define __ASM_ARM_ARCH_IO_H
 
 #define __io(a) __iop13xx_io(a)
-#define __mem_isa(a) (a)
 
 extern void __iomem * __iop13xx_io(unsigned long io_addr);
 extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h
index edb9cdd..11de350 100644
--- a/arch/arm/mach-ns9xxx/include/mach/io.h
+++ b/arch/arm/mach-ns9xxx/include/mach/io.h
@@ -12,6 +12,5 @@
 #define __ASM_ARCH_IO_H
 
 #define __io(a)		__typesafe_io(a)
-#define __mem_isa(a)    (IO_BASE + (a))
 
 #endif /* ifndef __ASM_ARCH_IO_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h
index 73817a1..4649a7b 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/io.h
+++ b/arch/arm/plat-stmp3xxx/include/mach/io.h
@@ -17,6 +17,5 @@
 #define __ASM_ARM_ARCH_IO_H
 
 #define __io(a) 	__typesafe_io(a)
-#define __mem_isa(a)	(a)
 
 #endif
-- 
1.7.1



From eric.y.miao at gmail.com  Wed Jun 23 07:52:17 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 19:52:17 +0800
Subject: [PATCH 5/6] [ARM] shmobile: change __io() definition to use
	__typesafe_io()
In-Reply-To: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
References: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1277293938-25804-6-git-send-email-eric.y.miao@gmail.com>

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/mach-shmobile/include/mach/io.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/io.h b/arch/arm/mach-shmobile/include/mach/io.h
index 3e29649..19d5120 100644
--- a/arch/arm/mach-shmobile/include/mach/io.h
+++ b/arch/arm/mach-shmobile/include/mach/io.h
@@ -1,5 +1,5 @@
 #ifndef __ASM_MACH_IO_H
 #define __ASM_MACH_IO_H
 
-#define __io(a)			((void __iomem *)(a))
+#define __io(a)			__typesafe_io(a)
 #endif /* __ASM_MACH_IO_H */
-- 
1.7.1



From eric.y.miao at gmail.com  Wed Jun 23 07:52:18 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 19:52:18 +0800
Subject: [PATCH 6/6] [ARM] Introduce common definition for __io()
In-Reply-To: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
References: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1277293938-25804-7-git-send-email-eric.y.miao@gmail.com>

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/include/asm/io.h                 |    4 ++++
 arch/arm/mach-aaec2000/include/mach/io.h  |    1 -
 arch/arm/mach-at91/include/mach/io.h      |    1 -
 arch/arm/mach-bcmring/include/mach/io.h   |    1 -
 arch/arm/mach-clps711x/include/mach/io.h  |    1 -
 arch/arm/mach-cns3xxx/include/mach/io.h   |    1 -
 arch/arm/mach-davinci/include/mach/io.h   |    1 -
 arch/arm/mach-ep93xx/include/mach/io.h    |    1 -
 arch/arm/mach-gemini/include/mach/io.h    |    1 -
 arch/arm/mach-h720x/include/mach/io.h     |    1 -
 arch/arm/mach-ixp4xx/include/mach/io.h    |    1 -
 arch/arm/mach-ks8695/include/mach/io.h    |    1 -
 arch/arm/mach-l7200/include/mach/io.h     |    1 -
 arch/arm/mach-lh7a40x/include/mach/io.h   |    1 -
 arch/arm/mach-mmp/include/mach/io.h       |    1 -
 arch/arm/mach-msm/include/mach/io.h       |    1 -
 arch/arm/mach-netx/include/mach/io.h      |    1 -
 arch/arm/mach-nomadik/include/mach/io.h   |    1 -
 arch/arm/mach-ns9xxx/include/mach/io.h    |    1 -
 arch/arm/mach-nuc93x/include/mach/io.h    |    1 -
 arch/arm/mach-orion5x/include/mach/io.h   |    1 -
 arch/arm/mach-pnx4008/include/mach/io.h   |    1 -
 arch/arm/mach-pxa/include/mach/io.h       |    1 -
 arch/arm/mach-realview/include/mach/io.h  |    1 -
 arch/arm/mach-s3c24a0/include/mach/io.h   |    1 -
 arch/arm/mach-s3c64xx/include/mach/io.h   |    1 -
 arch/arm/mach-s5p6440/include/mach/io.h   |    1 -
 arch/arm/mach-s5p6442/include/mach/io.h   |    1 -
 arch/arm/mach-s5pc100/include/mach/io.h   |    1 -
 arch/arm/mach-s5pv210/include/mach/io.h   |    1 -
 arch/arm/mach-sa1100/include/mach/io.h    |    1 -
 arch/arm/mach-u300/include/mach/io.h      |    1 -
 arch/arm/mach-ux500/include/mach/io.h     |    1 -
 arch/arm/mach-versatile/include/mach/io.h |    1 -
 arch/arm/mach-vexpress/include/mach/io.h  |    1 -
 arch/arm/mach-w90x900/include/mach/io.h   |    1 -
 arch/arm/plat-mxc/include/mach/io.h       |    1 -
 arch/arm/plat-omap/include/plat/io.h      |    1 -
 arch/arm/plat-spear/include/plat/io.h     |    1 -
 arch/arm/plat-stmp3xxx/include/mach/io.h  |    1 -
 40 files changed, 4 insertions(+), 39 deletions(-)

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index c5b8803..afcc58a 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -105,6 +105,10 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 #define __mem_pci(a)	(a)
 #endif
 
+#ifndef __io
+#define __io(a)		__typesafe_io(a)
+#endif
+
 /*
  *  IO port access primitives
  *  -------------------------
diff --git a/arch/arm/mach-aaec2000/include/mach/io.h b/arch/arm/mach-aaec2000/include/mach/io.h
index 8b9193d..b391dae 100644
--- a/arch/arm/mach-aaec2000/include/mach/io.h
+++ b/arch/arm/mach-aaec2000/include/mach/io.h
@@ -10,5 +10,4 @@
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
index ab014c0..fe4a498 100644
--- a/arch/arm/mach-at91/include/mach/io.h
+++ b/arch/arm/mach-at91/include/mach/io.h
@@ -21,7 +21,6 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#define __io(a)		__typesafe_io(a)
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/arm/mach-bcmring/include/mach/io.h b/arch/arm/mach-bcmring/include/mach/io.h
index 3357d80..ed1cacc 100644
--- a/arch/arm/mach-bcmring/include/mach/io.h
+++ b/arch/arm/mach-bcmring/include/mach/io.h
@@ -25,5 +25,4 @@
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-clps711x/include/mach/io.h b/arch/arm/mach-clps711x/include/mach/io.h
index 83980b6..7711803 100644
--- a/arch/arm/mach-clps711x/include/mach/io.h
+++ b/arch/arm/mach-clps711x/include/mach/io.h
@@ -20,7 +20,6 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define __io(a)		__typesafe_io(a)
 /*
  * We don't support ins[lb]/outs[lb].  Make them fault.
  */
diff --git a/arch/arm/mach-cns3xxx/include/mach/io.h b/arch/arm/mach-cns3xxx/include/mach/io.h
index be5a0d2..092eb41 100644
--- a/arch/arm/mach-cns3xxx/include/mach/io.h
+++ b/arch/arm/mach-cns3xxx/include/mach/io.h
@@ -9,5 +9,4 @@
 #ifndef __MACH_IO_H
 #define __MACH_IO_H
 
-#define __io(a)			__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index 078d939..a4343f0 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -15,7 +15,6 @@
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)			__typesafe_io(a)
 
 #ifndef __ASSEMBLER__
 #define __arch_ioremap(p, s, t)	davinci_ioremap(p, s, t)
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
index b63e543..e579eff 100644
--- a/arch/arm/mach-ep93xx/include/mach/io.h
+++ b/arch/arm/mach-ep93xx/include/mach/io.h
@@ -5,7 +5,6 @@
 #ifndef __ASM_MACH_IO_H
 #define __ASM_MACH_IO_H
 
-#define __io(p)			__typesafe_io(p)
 /*
  * A typesafe __io() variation for variable initialisers
  */
diff --git a/arch/arm/mach-gemini/include/mach/io.h b/arch/arm/mach-gemini/include/mach/io.h
index 9925714..8f94508 100644
--- a/arch/arm/mach-gemini/include/mach/io.h
+++ b/arch/arm/mach-gemini/include/mach/io.h
@@ -10,5 +10,4 @@
 #ifndef __MACH_IO_H
 #define __MACH_IO_H
 
-#define __io(a)		__typesafe_io(a)
 #endif /* __MACH_IO_H */
diff --git a/arch/arm/mach-h720x/include/mach/io.h b/arch/arm/mach-h720x/include/mach/io.h
index 8745f59..c632af0 100644
--- a/arch/arm/mach-h720x/include/mach/io.h
+++ b/arch/arm/mach-h720x/include/mach/io.h
@@ -14,5 +14,4 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h
index 7489f8f..8dc8d50 100644
--- a/arch/arm/mach-ixp4xx/include/mach/io.h
+++ b/arch/arm/mach-ixp4xx/include/mach/io.h
@@ -233,7 +233,6 @@ static inline void __indirect_readsl(const volatile void __iomem *bus_addr,
 
 #ifndef CONFIG_PCI
 
-#define	__io(v)		__typesafe_io(v)
 
 #else
 
diff --git a/arch/arm/mach-ks8695/include/mach/io.h b/arch/arm/mach-ks8695/include/mach/io.h
index d2029d3..5e7e96b 100644
--- a/arch/arm/mach-ks8695/include/mach/io.h
+++ b/arch/arm/mach-ks8695/include/mach/io.h
@@ -11,5 +11,4 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-l7200/include/mach/io.h b/arch/arm/mach-l7200/include/mach/io.h
index 13b6e5c..d3b837a 100644
--- a/arch/arm/mach-l7200/include/mach/io.h
+++ b/arch/arm/mach-l7200/include/mach/io.h
@@ -13,5 +13,4 @@
 /*
  * There are not real ISA nor PCI buses, so we fake it.
  */
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-lh7a40x/include/mach/io.h b/arch/arm/mach-lh7a40x/include/mach/io.h
index 4de858b..09e42f6 100644
--- a/arch/arm/mach-lh7a40x/include/mach/io.h
+++ b/arch/arm/mach-lh7a40x/include/mach/io.h
@@ -12,5 +12,4 @@
 #define __ASM_ARCH_IO_H
 
 /* No ISA or PCI bus on this machine. */
-#define __io(a)		__typesafe_io(a)
 #endif /* __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h
index e9581d5..3a0b9c8 100644
--- a/arch/arm/mach-mmp/include/mach/io.h
+++ b/arch/arm/mach-mmp/include/mach/io.h
@@ -13,5 +13,4 @@
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)		__typesafe_io(a)
 #endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-msm/include/mach/io.h b/arch/arm/mach-msm/include/mach/io.h
index 5e0e93d..94bc292 100644
--- a/arch/arm/mach-msm/include/mach/io.h
+++ b/arch/arm/mach-msm/include/mach/io.h
@@ -21,7 +21,6 @@
 
 void __iomem *__msm_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype);
 
-#define __io(a)		__typesafe_io(a)
 void msm_map_qsd8x50_io(void);
 void msm_map_msm7x30_io(void);
 
diff --git a/arch/arm/mach-netx/include/mach/io.h b/arch/arm/mach-netx/include/mach/io.h
index ac134a8..57e251c 100644
--- a/arch/arm/mach-netx/include/mach/io.h
+++ b/arch/arm/mach-netx/include/mach/io.h
@@ -20,5 +20,4 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-nomadik/include/mach/io.h b/arch/arm/mach-nomadik/include/mach/io.h
index a2b9e1a..9dffc02 100644
--- a/arch/arm/mach-nomadik/include/mach/io.h
+++ b/arch/arm/mach-nomadik/include/mach/io.h
@@ -14,5 +14,4 @@
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)         __typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h
index 11de350..f2495ae 100644
--- a/arch/arm/mach-ns9xxx/include/mach/io.h
+++ b/arch/arm/mach-ns9xxx/include/mach/io.h
@@ -11,6 +11,5 @@
 #ifndef __ASM_ARCH_IO_H
 #define __ASM_ARCH_IO_H
 
-#define __io(a)		__typesafe_io(a)
 
 #endif /* ifndef __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-nuc93x/include/mach/io.h b/arch/arm/mach-nuc93x/include/mach/io.h
index 99fe76d..96faf0e 100644
--- a/arch/arm/mach-nuc93x/include/mach/io.h
+++ b/arch/arm/mach-nuc93x/include/mach/io.h
@@ -20,6 +20,5 @@
  * 1:1 mapping for ioremapped regions.
  */
 
-#define __io(a)		__typesafe_io(a)
 
 #endif
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
index 34c2a5c..b3b24eb 100644
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ b/arch/arm/mach-orion5x/include/mach/io.h
@@ -38,7 +38,6 @@ __arch_iounmap(void __iomem *addr)
 
 #define __arch_ioremap(p, s, m)	__arch_ioremap(p, s, m)
 #define __arch_iounmap(a)	__arch_iounmap(a)
-#define __io(a)			__typesafe_io(a)
 
 /*****************************************************************************
  * Helpers to access Orion registers
diff --git a/arch/arm/mach-pnx4008/include/mach/io.h b/arch/arm/mach-pnx4008/include/mach/io.h
index bd655e5..cc9648b 100644
--- a/arch/arm/mach-pnx4008/include/mach/io.h
+++ b/arch/arm/mach-pnx4008/include/mach/io.h
@@ -13,5 +13,4 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
index 5bfd427..286be85 100644
--- a/arch/arm/mach-pxa/include/mach/io.h
+++ b/arch/arm/mach-pxa/include/mach/io.h
@@ -10,5 +10,4 @@
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-realview/include/mach/io.h b/arch/arm/mach-realview/include/mach/io.h
index cc45381..cfe167d 100644
--- a/arch/arm/mach-realview/include/mach/io.h
+++ b/arch/arm/mach-realview/include/mach/io.h
@@ -20,5 +20,4 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-s3c24a0/include/mach/io.h b/arch/arm/mach-s3c24a0/include/mach/io.h
index e04664f..67ec841 100644
--- a/arch/arm/mach-s3c24a0/include/mach/io.h
+++ b/arch/arm/mach-s3c24a0/include/mach/io.h
@@ -10,5 +10,4 @@
 #define __ASM_ARM_ARCH_IO_H
 
 /* No current ISA/PCI bus support. */
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/io.h b/arch/arm/mach-s3c64xx/include/mach/io.h
index eb4dae8..5588df0 100644
--- a/arch/arm/mach-s3c64xx/include/mach/io.h
+++ b/arch/arm/mach-s3c64xx/include/mach/io.h
@@ -10,5 +10,4 @@
 #define __ASM_ARM_ARCH_IO_H
 
 /* No current ISA/PCI bus support. */
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-s5p6440/include/mach/io.h b/arch/arm/mach-s5p6440/include/mach/io.h
index 10e18d3..00a9bf2 100644
--- a/arch/arm/mach-s5p6440/include/mach/io.h
+++ b/arch/arm/mach-s5p6440/include/mach/io.h
@@ -10,5 +10,4 @@
 #define __ASM_ARM_ARCH_IO_H
 
 /* No current ISA/PCI bus support. */
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-s5p6442/include/mach/io.h b/arch/arm/mach-s5p6442/include/mach/io.h
index 02cacba..ee3f30b 100644
--- a/arch/arm/mach-s5p6442/include/mach/io.h
+++ b/arch/arm/mach-s5p6442/include/mach/io.h
@@ -9,5 +9,4 @@
 #define __ASM_ARM_ARCH_IO_H
 
 /* No current ISA/PCI bus support. */
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-s5pc100/include/mach/io.h b/arch/arm/mach-s5pc100/include/mach/io.h
index d0970e4..cdabf13 100644
--- a/arch/arm/mach-s5pc100/include/mach/io.h
+++ b/arch/arm/mach-s5pc100/include/mach/io.h
@@ -10,5 +10,4 @@
 #define __ASM_ARM_ARCH_IO_H
 
 /* No current ISA/PCI bus support. */
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-s5pv210/include/mach/io.h b/arch/arm/mach-s5pv210/include/mach/io.h
index f80590e..3aa48f4 100644
--- a/arch/arm/mach-s5pv210/include/mach/io.h
+++ b/arch/arm/mach-s5pv210/include/mach/io.h
@@ -18,5 +18,4 @@
 #define __ASM_ARM_ARCH_IO_H __FILE__
 
 /* No current ISA/PCI bus support. */
-#define __io(a)		__typesafe_io(a)
 #endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h
index 0817eb0..32d1a64 100644
--- a/arch/arm/mach-sa1100/include/mach/io.h
+++ b/arch/arm/mach-sa1100/include/mach/io.h
@@ -14,5 +14,4 @@
  * We don't actually have real ISA nor PCI buses, but there is so many 
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-u300/include/mach/io.h b/arch/arm/mach-u300/include/mach/io.h
index 6770eea..e290b2c 100644
--- a/arch/arm/mach-u300/include/mach/io.h
+++ b/arch/arm/mach-u300/include/mach/io.h
@@ -12,5 +12,4 @@
 #ifndef __MACH_IO_H
 #define __MACH_IO_H
 
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-ux500/include/mach/io.h b/arch/arm/mach-ux500/include/mach/io.h
index 16acb3b..844d86a 100644
--- a/arch/arm/mach-ux500/include/mach/io.h
+++ b/arch/arm/mach-ux500/include/mach/io.h
@@ -14,5 +14,4 @@
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
index 25c902a..e329b57 100644
--- a/arch/arm/mach-versatile/include/mach/io.h
+++ b/arch/arm/mach-versatile/include/mach/io.h
@@ -20,5 +20,4 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-vexpress/include/mach/io.h b/arch/arm/mach-vexpress/include/mach/io.h
index 2b73325..33a77d4 100644
--- a/arch/arm/mach-vexpress/include/mach/io.h
+++ b/arch/arm/mach-vexpress/include/mach/io.h
@@ -20,5 +20,4 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define __io(a)		__typesafe_io(a)
 #endif
diff --git a/arch/arm/mach-w90x900/include/mach/io.h b/arch/arm/mach-w90x900/include/mach/io.h
index 272f76b..fdbde6d 100644
--- a/arch/arm/mach-w90x900/include/mach/io.h
+++ b/arch/arm/mach-w90x900/include/mach/io.h
@@ -22,6 +22,5 @@
  * 1:1 mapping for ioremapped regions.
  */
 
-#define __io(a)		__typesafe_io(a)
 
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index ed05017..784b421 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -33,6 +33,5 @@ __mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
 #endif
 
 /* io address mapping macro */
-#define __io(a)		__typesafe_io(a)
 
 #endif
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index a9beb3c..03e7d91 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -43,7 +43,6 @@
  * We don't actually have real ISA nor PCI buses, but there is so many
  * drivers out there that might just work if we fake them...
  */
-#define __io(a)		__typesafe_io(a)
 /*
  * ----------------------------------------------------------------------------
  * I/O mapping
diff --git a/arch/arm/plat-spear/include/plat/io.h b/arch/arm/plat-spear/include/plat/io.h
index faf8e7e..540d5ad 100644
--- a/arch/arm/plat-spear/include/plat/io.h
+++ b/arch/arm/plat-spear/include/plat/io.h
@@ -14,5 +14,4 @@
 #ifndef __PLAT_IO_H
 #define __PLAT_IO_H
 
-#define __io(a)			__typesafe_io(a)
 #endif /* __PLAT_IO_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h
index 4649a7b..64144c4 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/io.h
+++ b/arch/arm/plat-stmp3xxx/include/mach/io.h
@@ -16,6 +16,5 @@
 #ifndef __ASM_ARM_ARCH_IO_H
 #define __ASM_ARM_ARCH_IO_H
 
-#define __io(a) 	__typesafe_io(a)
 
 #endif
-- 
1.7.1



From ext-jani.1.nikula at nokia.com  Wed Jun 23 07:53:52 2010
From: ext-jani.1.nikula at nokia.com (Jani Nikula)
Date: Wed, 23 Jun 2010 14:53:52 +0300 (EEST)
Subject: gpiolib and sleeping gpios
In-Reply-To: <386783.17931.qm@web180310.mail.gq1.yahoo.com>
References: <386783.17931.qm@web180310.mail.gq1.yahoo.com>
Message-ID: <alpine.DEB.2.00.1006231435410.8344@wnav-qrfxgbc>


On Sat, 19 Jun 2010, ext David Brownell wrote:

>> The point I was trying to make is that there are lots of drivers which 
>> will not work with gpios on sleeping io expanders because they call the 
>> spinlock safe gpio calls.
>
> And they will trigger runtime warnings, and thus eventually get fixed. 
> The way to do that is to check if the GPIO needs the cansleep() call
>
> That's the first category above:  the driver should have used the 
> cansleep() variant, and sotriggers a runtime warning.

Hi David -

Part of the reason why such drivers haven't been fixed might be that the 
runtime warnings are only issued if DEBUG is defined in gpiolib.c:

/* When debugging, extend minimal trust to callers and platform code.
  * Also emit diagnostic messages that may help initial bringup, when
  * board setup or driver bugs are most common.
  *
  * Otherwise, minimize overhead in what may be bitbanging codepaths.
  */
#ifdef	DEBUG
#define	extra_checks	1
#else
#define	extra_checks	0
#endif

...

int __gpio_get_value(unsigned gpio)
{
 	struct gpio_chip	*chip;

 	chip = gpio_to_chip(gpio);
 	WARN_ON(extra_checks && chip->can_sleep);
 	return chip->get ? chip->get(chip, gpio - chip->base) : 0;
}

Do you think it would do more harm than good to unconditionally enable the 
extra checks? I do see the comment about overhead there, but having them 
enabled would probably aid driver developers in fixing existing code and 
choosing the correct calls in the future.


BR,
Jani.


From eric.y.miao at gmail.com  Wed Jun 23 07:59:04 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 23 Jun 2010 19:59:04 +0800
Subject: [PATCH 5/6] [ARM] shmobile: change __io() definition to use 
	__typesafe_io()
In-Reply-To: <1277293938-25804-6-git-send-email-eric.y.miao@gmail.com>
References: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com> 
	<1277293938-25804-6-git-send-email-eric.y.miao@gmail.com>
Message-ID: <AANLkTikqB-TPT5qNbkrmNfG0GQpJmc6MNcJd4Up1FFKi@mail.gmail.com>

On Wed, Jun 23, 2010 at 7:52 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> Signed-off-by: Eric Miao <eric.miao at canonical.com>

Sorry, forgot to CC Magnus.

> ---
> ?arch/arm/mach-shmobile/include/mach/io.h | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-shmobile/include/mach/io.h b/arch/arm/mach-shmobile/include/mach/io.h
> index 3e29649..19d5120 100644
> --- a/arch/arm/mach-shmobile/include/mach/io.h
> +++ b/arch/arm/mach-shmobile/include/mach/io.h
> @@ -1,5 +1,5 @@
> ?#ifndef __ASM_MACH_IO_H
> ?#define __ASM_MACH_IO_H
>
> -#define __io(a) ? ? ? ? ? ? ? ? ? ? ? ?((void __iomem *)(a))
> +#define __io(a) ? ? ? ? ? ? ? ? ? ? ? ?__typesafe_io(a)
> ?#endif /* __ASM_MACH_IO_H */
> --
> 1.7.1
>
>


From david-b at pacbell.net  Wed Jun 23 08:40:01 2010
From: david-b at pacbell.net (David Brownell)
Date: Wed, 23 Jun 2010 05:40:01 -0700 (PDT)
Subject: gpiolib and sleeping gpios
In-Reply-To: <alpine.DEB.2.00.1006231435410.8344@wnav-qrfxgbc>
Message-ID: <564390.64703.qm@web180307.mail.gq1.yahoo.com>



--- On Wed, 6/23/10, Jani Nikula <ext-jani.1.nikula at nokia.com> wrote:

> Hi David -
> 
> Part of the reason why such drivers haven't been fixed
> might be that the runtime warnings are only issued if DEBUG
> is defined in gpiolib.c:

A very good point.  those cansleep() warnings
should perhaps be issued more consistently.

(Other warnings are safer to skip.)

I think the normal case for the GPIO calls is
the spinlock-safe code path, so I'd probably
ack a patch which incurs the extra costs only
for gpio chips that are already sleeping.

(The desire to trim costs for bitbanging is
not going to affect gpio chips accesssed over
I2C or SPI ... ;)

- Dave




From ext-jani.1.nikula at nokia.com  Wed Jun 23 09:22:31 2010
From: ext-jani.1.nikula at nokia.com (Jani Nikula)
Date: Wed, 23 Jun 2010 16:22:31 +0300 (EEST)
Subject: gpiolib and sleeping gpios
In-Reply-To: <564390.64703.qm@web180307.mail.gq1.yahoo.com>
References: <564390.64703.qm@web180307.mail.gq1.yahoo.com>
Message-ID: <alpine.DEB.2.00.1006231601310.7850@wnav-qrfxgbc>


On Wed, 23 Jun 2010, ext David Brownell wrote:

> --- On Wed, 6/23/10, Jani Nikula <ext-jani.1.nikula at nokia.com> wrote:
>
>> Hi David -
>> 
>> Part of the reason why such drivers haven't been fixed
>> might be that the runtime warnings are only issued if DEBUG
>> is defined in gpiolib.c:
>
> A very good point.  those cansleep() warnings
> should perhaps be issued more consistently.
>
> (Other warnings are safer to skip.)
>
> I think the normal case for the GPIO calls is
> the spinlock-safe code path, so I'd probably
> ack a patch which incurs the extra costs only
> for gpio chips that are already sleeping.

Hi -

I'd think the most important and useful warning would be about 
gpio_{get,set}_value() in atomic context on a gpio chip that might sleep. 
I seem to have some trouble with my foreign language parser here, so let's 
move to a more natural language - see patch below. ;)

If you'd be willing to accept that, with the overhead of one conditional 
statement in atomic context for non-sleepy chips, I see no reason not to 
go all the way and modify whole gpiolib.c to match extra_check == 1.


BR,
Jani.


diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 3ca3654..33d82b7 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1527,7 +1527,7 @@ int __gpio_get_value(unsigned gpio)
  	struct gpio_chip	*chip;

  	chip = gpio_to_chip(gpio);
-	WARN_ON(extra_checks && chip->can_sleep);
+	might_sleep_if(chip->can_sleep);
  	return chip->get ? chip->get(chip, gpio - chip->base) : 0;
  }
  EXPORT_SYMBOL_GPL(__gpio_get_value);
@@ -1546,7 +1546,7 @@ void __gpio_set_value(unsigned gpio, int value)
  	struct gpio_chip	*chip;

  	chip = gpio_to_chip(gpio);
-	WARN_ON(extra_checks && chip->can_sleep);
+	might_sleep_if(chip->can_sleep);
  	chip->set(chip, gpio - chip->base, value);
  }
  EXPORT_SYMBOL_GPL(__gpio_set_value);


From jamie at shareable.org  Wed Jun 23 09:28:14 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Wed, 23 Jun 2010 14:28:14 +0100
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100623092843.GC12255@atomide.com>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
	<20100623073912.GA12255@atomide.com>
	<20100623081218.GA16385@n2100.arm.linux.org.uk>
	<20100623092843.GC12255@atomide.com>
Message-ID: <20100623132814.GB7058@shareable.org>

Tony Lindgren wrote:
> > Also problematical with XIP - if we go down the route of implementing
> > these by copying code fragments into the kernel, we need to strip out
> > XIP support or implement a second way.  Obviously having a second way
> > adds maintainence burden, and the second way will probably lose out
> > on updates.
> 
> How about if we implement the default XIP-safe unoptimized functions,
> with minimal iffdeffery and then allow optional override for non-XIP
> kernels from mm/proc-*.S files?

That might be a plan for some things like cache maintenance - skip a
function call when not needed, call direct instead of indirect, but
for XIP that status quo must remain.

-- Jamie


From jamie at shareable.org  Wed Jun 23 09:36:36 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Wed, 23 Jun 2010 14:36:36 +0100
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100623073912.GA12255@atomide.com>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
	<20100623073912.GA12255@atomide.com>
Message-ID: <20100623133636.GC7058@shareable.org>

Tony Lindgren wrote:
> * Jamie Lokier <jamie at shareable.org> [100622 19:54]:
> > Tony Lindgren wrote:
> > >  __kuser_get_tls:				@ 0xffff0fe0
> > > -
> > > -#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
> > > -	ldr	r0, [pc, #(16 - 8)]		@ TLS stored at 0xffff0ff0
> > > -#else
> > > -	mrc	p15, 0, r0, c13, c0, 3		@ read TLS register
> > > -#endif
> > > +	ldr     r0, [pc, #(20 - 8)]		@ software TLS set in 0xffff0ff4?
> > > +	cmp	r0, #0				@ hardware TLS if flag not set
> > > +	mrceq	p15, 0, r0, c13, c0, 3		@ read hardware TLS register
> > > +	ldrne	r0, [pc, #(12 - 8)]		@ software TLS val at 0xffff0ff8
> > >  	usr_ret	lr
> > > -
> > > -	.rep	5
> > > -	.word	0			@ pad up to __kuser_helper_version
> > > -	.endr
> > > +	.word	0				@ non-zero for software TLS
> > > +	.word	0				@ software TLS value
> > 
> > It'd be nice not to waste instructions checking for HWCAP_TLS on archs
> > which definitely don't have it.  I guess it doesn't matter elsewhere;
> > I'd expect this to be a warm path for some programs making extensive
> > use of TLS (I haven't measured though).
> 
> OK, but let's try to figure out a way that does not add more ifdef else
> code as that makes it harder to build support for multiple ARM cores.
>  
> > As it's only a single instruction, and the code is in a writable page
> > already (copied at init), how about just patching the instruction
> > when ELF_HWCAP is set?
> 
> Yeah that can be done for __kuser_get_tls if it's always writable.
> But __switch_to is trickier because of the CONFIG_MMU ifdefs there.

__kuser_get_tls must be writable in kernels where !HAS_TLS_REG is
supported, because the TLS value is written to the same page.

I was thinking of changing *only* __kuser_get_tls, by the way.  Out of
all the different places, that's the only one I'd expect to be a hot
path in some TLS-using programs.

> What if we have optional __switch_to and __kuser_get_tls implementations
> in the mm/proc-*.S files that get copied over the current locations
> if implemented?

As __kuser_get_tls varies by only ones instruction, I don't think
there's any point doing anything other than a single word write, at
the point where the HWCAP is set, with its initial value being the
!HAS_TLS_REG instruction.

For other things like __switch_to and maybe cache maintenance calls,
dmb() etc, I'd suggest first doing a generic asm mechanism like x86's
"alternatives", keeping in mind that one of the alternatives has to be
XIP friendly.

-- Jamie


From kyungmin.park at samsung.com  Wed Jun 23 09:36:54 2010
From: kyungmin.park at samsung.com (Kyungmin Park)
Date: Wed, 23 Jun 2010 22:36:54 +0900
Subject: [PATCH v2 0/4] ARM: S5P: Support gpio interrupts
In-Reply-To: <004601cb12a8$c869e560$593db020$%kim@samsung.com>
References: <4C11F4CA.10802@samsung.com>
	<004601cb12a8$c869e560$593db020$%kim@samsung.com>
Message-ID: <AANLkTilGbh8F-LzBhbB-q8h6bcrFPHlFSriuDo_WXKMB@mail.gmail.com>

On Wed, Jun 23, 2010 at 4:50 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Joonyoung Shim wrote:
>>
>> This patch v2 set is to support gpio interrupts of samsung s5p cpus, and
>> the GPIOlib gpio_to_irq goes to plat-samsung gpiolib, so patch v2 set
>> has four commit smaller than v1.
>>
>> Changes since v1:
>> - Add irq_base to s3c_gpio_chip struct
>> - GPIOlib gpio_to_irq() is implemented to samsung_gpiolib_to_irq() of
>> ? plat-samsung gpiolib
>>
>> Joonyoung Shim (4):
>> ? ? ? ARM: S5PV210: Add gpio interrupt support
>> ? ? ? ARM: S5PC100: Use S5P gpio interrupts interface
>> ? ? ? ARM: S5PC100: Move external interrupt defines
>> ? ? ? ARM: SAMSUNG: Add GPIOlib gpio_to_irq
>>
>> ?arch/arm/mach-s5pc100/Makefile ? ? ? ? ? ? ? ? | ? ?2 +-
>> ?arch/arm/mach-s5pc100/gpiolib.c ? ? ? ? ? ? ? ?| ? 70 ++-----
>> ?arch/arm/mach-s5pc100/include/mach/gpio.h ? ? ?| ? ?7 -
>> ?arch/arm/mach-s5pc100/include/mach/irqs.h ? ? ?| ? 18 ++-
>> ?arch/arm/mach-s5pc100/include/mach/regs-gpio.h | ? ?7 +
>> ?arch/arm/mach-s5pc100/irq-gpio.c ? ? ? ? ? ? ? | ?266
> ------------------------
>> ?arch/arm/mach-s5pv210/gpiolib.c ? ? ? ? ? ? ? ?| ? 18 ++-
>> ?arch/arm/mach-s5pv210/include/mach/irqs.h ? ? ?| ? 16 ++-
>> ?arch/arm/plat-s5p/Makefile ? ? ? ? ? ? ? ? ? ? | ? ?2 +-
>> ?arch/arm/plat-s5p/irq-gpioint.c ? ? ? ? ? ? ? ?| ?208 ++++++++++++++++++
>> ?arch/arm/plat-samsung/gpiolib.c ? ? ? ? ? ? ? ?| ? ?9 +
>> ?arch/arm/plat-samsung/include/plat/gpio-core.h | ? ?6 +
>> ?12 files changed, 295 insertions(+), 334 deletions(-)
>> ?delete mode 100644 arch/arm/mach-s5pc100/irq-gpio.c
>> ?create mode 100644 arch/arm/plat-s5p/irq-gpioint.c
>>
>
> I am sure this patchset is working code, but Ben had made suggestion about
> 'sparse irq'...
> It is because there are too many gpio interrupts and having support of all
> of them is unnecessary as realistically only few of them maybe used.
> In fact in SMDK board there is no use of gpio in interrupt mode.
>
> Ben, I remember your suggestion for using 'sparse irq' for handling gpio
> interrupts.
> And in fact, sparse irq implementation can be beneficial to many other
> boards...
> Could you please explain about that?
Interesting.
you can find it by "[ARM] Preliminary support for dynamic IRQ" written by Eric.
Instead define the 'NR_IRQS' of chip, board can define each 'nr_irqs'
at init time.

Maybe smdk don't use the GPIOs. but mobile phones at samsung use the until MP0x.
Sometime H/W team connect it at MP04 or MP05 which doesn't support
GPIO interrupt.

Thank you,
Kyungmin Park


From nico at fluxnic.net  Wed Jun 23 10:19:48 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 23 Jun 2010 10:19:48 -0400 (EDT)
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100623133636.GC7058@shareable.org>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
	<20100623073912.GA12255@atomide.com>
	<20100623133636.GC7058@shareable.org>
Message-ID: <alpine.LFD.2.00.1006231002530.24097@xanadu.home>

On Wed, 23 Jun 2010, Jamie Lokier wrote:

> For other things like __switch_to and maybe cache maintenance calls,
> dmb() etc, I'd suggest first doing a generic asm mechanism like x86's
> "alternatives", keeping in mind that one of the alternatives has to be
> XIP friendly.

You cannot be XIP friendly unless you rewrite the concerned function(s) 
into a RAM page in order to modify it.  And then of course you have to 
play tricks with the linker so that the rewritten functions are 
referenced with their final rewritten location.  And that means of 
course that the RAM location has to be a constant unless we introduce 
some indirect function calls.  And at that point we're not much better 
than the proposed runtime test.

Also, if you are interested by a XIP kernel, this usually means you have 
a fairly highly customized kernel config.  In this context it is 
senseless to have runtime patching of the kernel.  What you want in that 
case is as much stuff as possible selected and optimized at compile 
time, and anything you don't need configured out.

So it would be best if dynamic function patching could be statically 
generated from the same source when XIP is active.


Nicolas


From lamiaposta71 at gmail.com  Wed Jun 23 10:33:54 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Wed, 23 Jun 2010 16:33:54 +0200
Subject: [PATCH] ASoC: DaVinci: Added support for stereo I2S
Message-ID: <1277303635-5675-1-git-send-email-lamiaposta71@gmail.com>

From: Raffaele Recalcati <raffaele.recalcati at bticino.it>

	Added audio playback support with [frame sync master - clock master] mode
	and with [frame sync master - clock slave].
	Clock slave can be important when the external codec need system clock
	and bit clock synchronized.
	In the clock master case there is a FIXME message in the source code, because we
	(Davide and myself) have guessed a frequency of 122000000 that seems the base
	to be divided.
	This patch has been developed against the
		http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
	git tree and has been tested on bmx board (similar to dm365 evm, but using
	uda1345 as external audio codec).

Signed-off-by: Raffaele Recalcati <raffaele.recalcati at bticino.it>
Signed-off-by: Davide Bonfanti <davide.bonfanti at bticino.it>
---
 arch/arm/mach-davinci/include/mach/asp.h |    7 ++
 sound/soc/davinci/davinci-i2s.c          |  141 ++++++++++++++++++++++++++----
 2 files changed, 129 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
index 834725f..b1faeb9 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -63,6 +63,13 @@ struct snd_platform_data {
 	unsigned sram_size_playback;
 	unsigned sram_size_capture;
 
+	/*
+	 * This define works when both clock and FS are output for the cpu
+	 * and makes clock very fast (FS is not simmetrical, but sampling
+	 * frequency is better approximated
+	 */
+	int i2s_fast_clock;
+
 	/* McASP specific fields */
 	int tdm_slots;
 	u8 op_mode;
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index adadcd3..8811d25 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -68,16 +68,23 @@
 #define DAVINCI_MCBSP_RCR_RDATDLY(v)	((v) << 16)
 #define DAVINCI_MCBSP_RCR_RFIG		(1 << 18)
 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)	((v) << 21)
+#define DAVINCI_MCBSP_RCR_RFRLEN2(v)	((v) << 24)
+#define DAVINCI_MCBSP_RCR_RPHASE		(1 << 31)
 
 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)	((v) << 5)
 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)	((v) << 8)
 #define DAVINCI_MCBSP_XCR_XDATDLY(v)	((v) << 16)
 #define DAVINCI_MCBSP_XCR_XFIG		(1 << 18)
 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)	((v) << 21)
+#define DAVINCI_MCBSP_XCR_XFRLEN2(v)	((v) << 24)
+#define DAVINCI_MCBSP_XCR_XPHASE	(1 << 31)
 
+
+#define CLKGDV(v)				(v)     /* Bits 0:7 */
 #define DAVINCI_MCBSP_SRGR_FWID(v)	((v) << 8)
 #define DAVINCI_MCBSP_SRGR_FPER(v)	((v) << 16)
 #define DAVINCI_MCBSP_SRGR_FSGM		(1 << 28)
+#define DAVINCI_MCBSP_SRGR_CLKSM	(1 << 29)
 
 #define DAVINCI_MCBSP_PCR_CLKRP		(1 << 0)
 #define DAVINCI_MCBSP_PCR_CLKXP		(1 << 1)
@@ -144,8 +151,17 @@ struct davinci_mcbsp_dev {
 	 * won't end up being swapped because of the underrun.
 	 */
 	unsigned enable_channel_combine:1;
+
+	int i2s_fast_clock;
+};
+
+struct davinci_mcbsp_data {
+	unsigned int	fmt;
+	int             clk_div;
 };
 
+static struct davinci_mcbsp_data mcbsp_data;
+
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
 					   int reg, u32 val)
 {
@@ -255,24 +271,27 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 	unsigned int pcr;
 	unsigned int srgr;
 	srgr = DAVINCI_MCBSP_SRGR_FSGM |
-		DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
-		DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
+	       DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
+	       DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
+	/* Attention srgr is updated by hw_params! */
 
+	mcbsp_data.fmt = fmt;
 	/* set master/slave audio interface */
 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+	case SND_SOC_DAIFMT_CBS_CFM:
 	case SND_SOC_DAIFMT_CBS_CFS:
 		/* cpu is master */
 		pcr = DAVINCI_MCBSP_PCR_FSXM |
-			DAVINCI_MCBSP_PCR_FSRM |
-			DAVINCI_MCBSP_PCR_CLKXM |
-			DAVINCI_MCBSP_PCR_CLKRM;
+		      DAVINCI_MCBSP_PCR_FSRM |
+		      DAVINCI_MCBSP_PCR_CLKXM |
+		      DAVINCI_MCBSP_PCR_CLKRM;
 		break;
 	case SND_SOC_DAIFMT_CBM_CFS:
 		/* McBSP CLKR pin is the input for the Sample Rate Generator.
 		 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
 		pcr = DAVINCI_MCBSP_PCR_SCLKME |
-			DAVINCI_MCBSP_PCR_FSXM |
-			DAVINCI_MCBSP_PCR_FSRM;
+		      DAVINCI_MCBSP_PCR_FSXM |
+		      DAVINCI_MCBSP_PCR_FSRM;
 		break;
 	case SND_SOC_DAIFMT_CBM_CFM:
 		/* codec is master */
@@ -372,6 +391,17 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 	return 0;
 }
 
+static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
+				int div_id, int div)
+{
+	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
+	int srgr;
+
+	mcbsp_data.clk_div = div;
+	return 0;
+}
+
+
 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 				 struct snd_pcm_hw_params *params,
 				 struct snd_soc_dai *dai)
@@ -380,11 +410,12 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 	struct davinci_pcm_dma_params *dma_params =
 					&dev->dma_params[substream->stream];
 	struct snd_interval *i = NULL;
-	int mcbsp_word_length;
-	unsigned int rcr, xcr, srgr;
+	int mcbsp_word_length, master;
+	unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
 	u32 spcr;
 	snd_pcm_format_t fmt;
 	unsigned element_cnt = 1;
+	struct clk *clk;
 
 	/* general line settings */
 	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
@@ -396,12 +427,60 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 	}
 
-	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
-	srgr = DAVINCI_MCBSP_SRGR_FSGM;
-	srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
+	master = mcbsp_data.fmt & SND_SOC_DAIFMT_MASTER_MASK;
+	fmt = params_format(params);
+	mcbsp_word_length = asp_word_length[fmt];
 
-	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
-	srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
+	if (master == SND_SOC_DAIFMT_CBS_CFS) {
+		clk = clk_get(NULL, "pll1_sysclk6");
+		if (clk)
+			freq = clk_get_rate(clk);
+		freq = 122000000; /* FIXME ask to Texas */
+		if (dev->i2s_fast_clock) {
+			clk_div = 256;
+			do {
+				framesize = (freq / (--clk_div)) /
+					    params->rate_num *
+					    params->rate_den;
+			} while (((framesize < 33) || (framesize > 4095)) &&
+				 (clk_div));
+			clk_div--;
+			srgr = DAVINCI_MCBSP_SRGR_FSGM |
+			       DAVINCI_MCBSP_SRGR_CLKSM;
+			srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
+							8 - 1);
+			srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
+		} else {
+			/* simmetric waveforms */
+			srgr = DAVINCI_MCBSP_SRGR_FSGM |
+			       DAVINCI_MCBSP_SRGR_CLKSM;
+			srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
+							8 - 1);
+			srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
+							16 - 1);
+			clk_div = freq / (mcbsp_word_length * 16) /
+				  params->rate_num * params->rate_den;
+		}
+		clk_div &= 0xFF;
+		srgr |= clk_div;
+	} else if (master == SND_SOC_DAIFMT_CBS_CFM) {
+		/* Clock given on CLKS */
+		srgr = DAVINCI_MCBSP_SRGR_FSGM;
+		clk_div = mcbsp_data.clk_div - 1;
+		srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
+		srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
+		clk_div &= 0xFF;
+		srgr |= clk_div;
+	} else {
+		i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
+		srgr = DAVINCI_MCBSP_SRGR_FSGM;
+		srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
+		pr_debug("%s - %d  FWID set: re-read srgr = %X\n",
+			__func__, __LINE__, snd_interval_value(i) - 1);
+
+		i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
+		srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
+	}
 	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 
 	rcr = DAVINCI_MCBSP_RCR_RFIG;
@@ -426,22 +505,45 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 			element_cnt = 1;
 			fmt = double_fmt[fmt];
 		}
+		if (master == SND_SOC_DAIFMT_CBS_CFS ||
+				master == SND_SOC_DAIFMT_CBS_CFM) {
+			rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
+			xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
+			rcr |= DAVINCI_MCBSP_RCR_RPHASE;
+			xcr |= DAVINCI_MCBSP_XCR_XPHASE;
+		} else {
+			/* FIXME ask to Texas */
+			rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
+			xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
+		}
 	}
 	dma_params->acnt = dma_params->data_type = data_type[fmt];
 	dma_params->fifo_level = 0;
 	mcbsp_word_length = asp_word_length[fmt];
-	rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
-	xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
+
+	if (master == SND_SOC_DAIFMT_CBS_CFS ||
+			master == SND_SOC_DAIFMT_CBS_CFM) {
+		rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
+		xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
+	} else {
+		/* FIXME ask to Texas */
+		rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
+		xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
+	}
 
 	rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
-		DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
+	       DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
 	xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
-		DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
+	       DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
 
 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
 	else
 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
+
+	pr_debug("%s - %d  srgr=%X\n", __func__, __LINE__, srgr);
+	pr_debug("%s - %d  xcr=%X\n", __func__, __LINE__, xcr);
+	pr_debug("%s - %d  rcr=%X\n", __func__, __LINE__, rcr);
 	return 0;
 }
 
@@ -500,7 +602,7 @@ static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
 	.trigger	= davinci_i2s_trigger,
 	.hw_params	= davinci_i2s_hw_params,
 	.set_fmt	= davinci_i2s_set_dai_fmt,
-
+	.set_clkdiv = davinci_i2s_dai_set_clkdiv,
 };
 
 struct snd_soc_dai davinci_i2s_dai = {
@@ -548,6 +650,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
 	}
 	if (pdata) {
 		dev->enable_channel_combine = pdata->enable_channel_combine;
+		dev->i2s_fast_clock = pdata->i2s_fast_clock;
 		dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size =
 			pdata->sram_size_playback;
 		dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
-- 
1.7.0.4



From david-b at pacbell.net  Wed Jun 23 09:39:09 2010
From: david-b at pacbell.net (David Brownell)
Date: Wed, 23 Jun 2010 06:39:09 -0700 (PDT)
Subject: gpiolib and sleeping gpios
In-Reply-To: <alpine.DEB.2.00.1006231601310.7850@wnav-qrfxgbc>
Message-ID: <294115.59939.qm@web180308.mail.gq1.yahoo.com>



--- On Wed, 6/23/10, Jani Nikula <ext-jani.1.nikula at nokia.com> wrote:

> -??? WARN_ON(extra_checks &&
> chip->can_sleep);
> +??? might_sleep_if(chip->can_sleep);

 That looks like the right track.  For
those cases the "extra_checks" should
not be optional ... thanks.

- Dave




From eric at eukrea.com  Wed Jun 23 10:50:32 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Wed, 23 Jun 2010 16:50:32 +0200
Subject: [PATCH] otg/ulpi.c : fix register write
Message-ID: <1277304632-11314-1-git-send-email-eric@eukrea.com>

* drivers/usb/otg/ulpi.c :
ulpi_set_vbus and ulpi_set_flags are using ULPI_SET(register) to write
to the PHY's registers, which means we can only set bits in the PHY's
register and not clear them.
By directly using the address of the register without any offset, we
now get the expected behaviour for these functions.

* this patch also keep usage of otg_io_write & ulpi parameters coherent
as in include/linux/usb/otg.h we have :
otg_io_write(struct otg_transceiver *otg, u32 reg, u32 val)
so keep the same parameters order in drivers/usb/otg/ulpi.c and
arch/arm/plat-mxc/ulpi.c.

Signed-off-by: Eric B?nard <eric at eukrea.com>
Cc: Daniel Mack <daniel at caiaq.de>
Cc: linux-usb at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Sascha Hauer <kernel at pengutronix.de>
---
 arch/arm/plat-mxc/ulpi.c |    2 +-
 drivers/usb/otg/ulpi.c   |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
index 582c6df..84eb5c7 100644
--- a/arch/arm/plat-mxc/ulpi.c
+++ b/arch/arm/plat-mxc/ulpi.c
@@ -83,7 +83,7 @@ static int ulpi_read(struct otg_transceiver *otg, u32 reg)
 	return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
 }
 
-static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
+static int ulpi_write(struct otg_transceiver *otg, u32 reg, u32 val)
 {
 	int ret;
 	void __iomem *view = otg->io_priv;
diff --git a/drivers/usb/otg/ulpi.c b/drivers/usb/otg/ulpi.c
index b1b3469..f6048ca 100644
--- a/drivers/usb/otg/ulpi.c
+++ b/drivers/usb/otg/ulpi.c
@@ -54,7 +54,7 @@ static int ulpi_set_flags(struct otg_transceiver *otg)
 	if (otg->flags & USB_OTG_EXT_VBUS_INDICATOR)
 		flags |= ULPI_OTG_CTRL_EXTVBUSIND;
 
-	return otg_io_write(otg, flags, ULPI_SET(ULPI_OTG_CTRL));
+	return otg_io_write(otg, ULPI_OTG_CTRL, flags);
 }
 
 static int ulpi_init(struct otg_transceiver *otg)
@@ -90,7 +90,7 @@ static int ulpi_set_vbus(struct otg_transceiver *otg, bool on)
 			flags |= ULPI_OTG_CTRL_DRVVBUS_EXT;
 	}
 
-	return otg_io_write(otg, flags, ULPI_SET(ULPI_OTG_CTRL));
+	return otg_io_write(otg, ULPI_OTG_CTRL, flags);
 }
 
 struct otg_transceiver *
-- 
1.6.3.3



From jason77.wang at gmail.com  Wed Jun 23 10:54:19 2010
From: jason77.wang at gmail.com (jason)
Date: Wed, 23 Jun 2010 22:54:19 +0800
Subject: [PATCH V2 1/2] mxc: add common debug board for 3-stack	platforms
In-Reply-To: <20100623065914.GO12115@pengutronix.de>
References: <1277216851-15782-1-git-send-email-jason77.wang@gmail.com>
	<1277216851-15782-2-git-send-email-jason77.wang@gmail.com>
	<20100623065914.GO12115@pengutronix.de>
Message-ID: <4C22201B.7080906@gmail.com>

Sascha Hauer wrote:
> On Tue, Jun 22, 2010 at 10:27:30PM +0800, Jason Wang wrote:
>   
>> The debug board is little different for all mxc 3-stack(PDK)
>> platforms, it is possible here to add a common implementation to
>> support this board.
>>
>> +
>> +void __init mxc_expio_lan_init(void)
>> +{
>> +	platform_device_register(&smsc_lan9217_device);
>> +}
>>     
>
> What do we need this for? Can't we just call this from
> mxc_expio_init()?
>
>
>   
I add this function for lan because on the debugboard there are other 
potential
useful devices(like UART or keys). In future if we add these device 
definitions, we can select
which one will be registered to the system instead of all devices.

Currently only lan device is implemented, it is reasonable to move it to 
mxc_expio_init() and
let them to bind together. I will fix it.

Thanks,
Jason.




From daniel at caiaq.de  Wed Jun 23 10:58:16 2010
From: daniel at caiaq.de (Daniel Mack)
Date: Wed, 23 Jun 2010 16:58:16 +0200
Subject: [PATCH] otg/ulpi.c : fix register write
In-Reply-To: <1277304632-11314-1-git-send-email-eric@eukrea.com>
References: <1277304632-11314-1-git-send-email-eric@eukrea.com>
Message-ID: <20100623145816.GE2698@buzzloop.caiaq.de>

On Wed, Jun 23, 2010 at 04:50:32PM +0200, Eric B?nard wrote:
> * drivers/usb/otg/ulpi.c :
> ulpi_set_vbus and ulpi_set_flags are using ULPI_SET(register) to write
> to the PHY's registers, which means we can only set bits in the PHY's
> register and not clear them.
> By directly using the address of the register without any offset, we
> now get the expected behaviour for these functions.
> 
> * this patch also keep usage of otg_io_write & ulpi parameters coherent
> as in include/linux/usb/otg.h we have :
> otg_io_write(struct otg_transceiver *otg, u32 reg, u32 val)
> so keep the same parameters order in drivers/usb/otg/ulpi.c and
> arch/arm/plat-mxc/ulpi.c.
> 
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> Cc: Daniel Mack <daniel at caiaq.de>
> Cc: linux-usb at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Sascha Hauer <kernel at pengutronix.de>
> ---
>  arch/arm/plat-mxc/ulpi.c |    2 +-
>  drivers/usb/otg/ulpi.c   |    4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
> index 582c6df..84eb5c7 100644
> --- a/arch/arm/plat-mxc/ulpi.c
> +++ b/arch/arm/plat-mxc/ulpi.c
> @@ -83,7 +83,7 @@ static int ulpi_read(struct otg_transceiver *otg, u32 reg)
>  	return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
>  }
>  
> -static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
> +static int ulpi_write(struct otg_transceiver *otg, u32 reg, u32 val)

Urgs. Is this really necessary? It's not that I have a strong opinion
about the order of arguments in such cases (I kept to the convention
of __readl() when I wrote it). But _changing_ it like this is really
confusing. Once in awhile I stumble over such API changes and I always
wonder about the reason. The problem is that not even the compiler will
warn you if you got it wrong, when you copied a sniplet from older
sources etc.

And you really want to break someone knee caps once you find out what
caused the breakage ;)

So - if we can avoid that, we should do. If anyone speaks up with a real
reason for changing it, I'd be fine :)

Daniel


From will.deacon at arm.com  Wed Jun 23 11:02:16 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 23 Jun 2010 16:02:16 +0100
Subject: [PATCH 0/2] Fix atomic operations so that atomic64_test passes on ARM
Message-ID: <1277305338-26110-1-git-send-email-will.deacon@arm.com>

A recently introduced Kernel feature is the atomic64_test on boot.
ARM fails these tests because the compiler is not correctly informed about
updates occuring to memory and is at liberty to constant-fold atomic64_t
variables.

This patch series adds the correct memory constraints to the atomic operations
on ARM and also enables all of the atomic64 tests in atomic64_test.c.

Will Deacon (2):
  ARM: atomic ops: add memory constraints to inline asm
  ARM: atomic64_test: add ARM as supported architecture

 arch/arm/include/asm/atomic.h |  123 +++++++++++++++++++++--------------------
 lib/atomic64_test.c           |    2 +-
 2 files changed, 63 insertions(+), 62 deletions(-)



From will.deacon at arm.com  Wed Jun 23 11:02:18 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 23 Jun 2010 16:02:18 +0100
Subject: [PATCH 2/2] ARM: atomic64_test: add ARM as supported architecture
In-Reply-To: <1277305338-26110-2-git-send-email-will.deacon@arm.com>
References: <1277305338-26110-1-git-send-email-will.deacon@arm.com>
	<1277305338-26110-2-git-send-email-will.deacon@arm.com>
Message-ID: <1277305338-26110-3-git-send-email-will.deacon@arm.com>

ARM has support for the atomic64_dec_if_positive operation
so ensure that it is tested by the atomic64_test routine.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 lib/atomic64_test.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/lib/atomic64_test.c b/lib/atomic64_test.c
index 250ed11..44524cc 100644
--- a/lib/atomic64_test.c
+++ b/lib/atomic64_test.c
@@ -114,7 +114,7 @@ static __init int test_atomic64(void)
 	BUG_ON(v.counter != r);
 
 #if defined(CONFIG_X86) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
-    defined(CONFIG_S390) || defined(_ASM_GENERIC_ATOMIC64_H)
+    defined(CONFIG_S390) || defined(_ASM_GENERIC_ATOMIC64_H) || defined(CONFIG_ARM)
 	INIT(onestwos);
 	BUG_ON(atomic64_dec_if_positive(&v) != (onestwos - 1));
 	r -= one;
-- 
1.6.3.3



From will.deacon at arm.com  Wed Jun 23 11:02:17 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 23 Jun 2010 16:02:17 +0100
Subject: [PATCH 1/2] ARM: atomic ops: add memory constraints to inline asm
In-Reply-To: <1277305338-26110-1-git-send-email-will.deacon@arm.com>
References: <1277305338-26110-1-git-send-email-will.deacon@arm.com>
Message-ID: <1277305338-26110-2-git-send-email-will.deacon@arm.com>

Currently, the 32-bit and 64-bit atomic operations on ARM do not
include memory constraints in the inline assembly blocks. In the
case of barrier-less operations [for example, atomic_add], this
means that the compiler may constant fold values which have actually
been modified by a call to an atomic operation.

This issue can be observed in the atomic64_test routine in
<kernel root>/lib/atomic64_test.c:

00000000 <test_atomic64>:
   0:	e1a0c00d 	mov	ip, sp
   4:	e92dd830 	push	{r4, r5, fp, ip, lr, pc}
   8:	e24cb004 	sub	fp, ip, #4
   c:	e24dd008 	sub	sp, sp, #8
  10:	e24b3014 	sub	r3, fp, #20
  14:	e30d000d 	movw	r0, #53261	; 0xd00d
  18:	e3011337 	movw	r1, #4919	; 0x1337
  1c:	e34c0001 	movt	r0, #49153	; 0xc001
  20:	e34a1aa3 	movt	r1, #43683	; 0xaaa3
  24:	e16300f8 	strd	r0, [r3, #-8]!
  28:	e30c0afe 	movw	r0, #51966	; 0xcafe
  2c:	e30b1eef 	movw	r1, #48879	; 0xbeef
  30:	e34d0eaf 	movt	r0, #57007	; 0xdeaf
  34:	e34d1ead 	movt	r1, #57005	; 0xdead
  38:	e1b34f9f 	ldrexd	r4, [r3]
  3c:	e1a34f90 	strexd	r4, r0, [r3]
  40:	e3340000 	teq	r4, #0
  44:	1afffffb 	bne	38 <test_atomic64+0x38>
  48:	e59f0004 	ldr	r0, [pc, #4]	; 54 <test_atomic64+0x54>
  4c:	e3a0101e 	mov	r1, #30
  50:	ebfffffe 	bl	0 <__bug>
  54:	00000000 	.word	0x00000000

The atomic64_set (0x38-0x44) writes to the atomic64_t, but the
compiler doesn't see this, assumes the test condition is always
false and generates an unconditional branch to __bug. The rest of the
test is optimised away.

This patch adds suitable memory constraints to the atomic operations on ARM
to ensure that the compiler is informed of the correct data hazards.
Additionally, the implementations of atomic64_cmpxchg and atomic64_add_unless
are modified so that the portions of their implementation written in C are now
implemented in assembly to avoid miscompilation by buggy compilers.

Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/atomic.h |  123 +++++++++++++++++++++--------------------
 1 files changed, 62 insertions(+), 61 deletions(-)

diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index a0162fa..2471d72 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -40,12 +40,12 @@ static inline void atomic_add(int i, atomic_t *v)
 	int result;
 
 	__asm__ __volatile__("@ atomic_add\n"
-"1:	ldrex	%0, [%2]\n"
-"	add	%0, %0, %3\n"
-"	strex	%1, %0, [%2]\n"
+"1:	ldrex	%0, [%3]\n"
+"	add	%0, %0, %4\n"
+"	strex	%1, %0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+m" (v->counter)
 	: "r" (&v->counter), "Ir" (i)
 	: "cc");
 }
@@ -78,12 +78,12 @@ static inline void atomic_sub(int i, atomic_t *v)
 	int result;
 
 	__asm__ __volatile__("@ atomic_sub\n"
-"1:	ldrex	%0, [%2]\n"
-"	sub	%0, %0, %3\n"
-"	strex	%1, %0, [%2]\n"
+"1:	ldrex	%0, [%3]\n"
+"	sub	%0, %0, %4\n"
+"	strex	%1, %0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+m" (v->counter)
 	: "r" (&v->counter), "Ir" (i)
 	: "cc");
 }
@@ -137,12 +137,12 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
 	unsigned long tmp, tmp2;
 
 	__asm__ __volatile__("@ atomic_clear_mask\n"
-"1:	ldrex	%0, [%2]\n"
-"	bic	%0, %0, %3\n"
-"	strex	%1, %0, [%2]\n"
+"1:	ldrex	%0, [%3]\n"
+"	bic	%0, %0, %4\n"
+"	strex	%1, %0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (tmp), "=&r" (tmp2)
+	: "=&r" (tmp), "=&r" (tmp2), "+m" (*addr)
 	: "r" (addr), "Ir" (mask)
 	: "cc");
 }
@@ -249,7 +249,7 @@ static inline u64 atomic64_read(atomic64_t *v)
 	__asm__ __volatile__("@ atomic64_read\n"
 "	ldrexd	%0, %H0, [%1]"
 	: "=&r" (result)
-	: "r" (&v->counter)
+	: "r" (&v->counter), "m" (v->counter)
 	);
 
 	return result;
@@ -260,11 +260,11 @@ static inline void atomic64_set(atomic64_t *v, u64 i)
 	u64 tmp;
 
 	__asm__ __volatile__("@ atomic64_set\n"
-"1:	ldrexd	%0, %H0, [%1]\n"
-"	strexd	%0, %2, %H2, [%1]\n"
+"1:	ldrexd	%0, %H0, [%2]\n"
+"	strexd	%0, %3, %H3, [%2]\n"
 "	teq	%0, #0\n"
 "	bne	1b"
-	: "=&r" (tmp)
+	: "=&r" (tmp), "=m" (v->counter)
 	: "r" (&v->counter), "r" (i)
 	: "cc");
 }
@@ -275,13 +275,13 @@ static inline void atomic64_add(u64 i, atomic64_t *v)
 	unsigned long tmp;
 
 	__asm__ __volatile__("@ atomic64_add\n"
-"1:	ldrexd	%0, %H0, [%2]\n"
-"	adds	%0, %0, %3\n"
-"	adc	%H0, %H0, %H3\n"
-"	strexd	%1, %0, %H0, [%2]\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
+"	adds	%0, %0, %4\n"
+"	adc	%H0, %H0, %H4\n"
+"	strexd	%1, %0, %H0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+m" (v->counter)
 	: "r" (&v->counter), "r" (i)
 	: "cc");
 }
@@ -294,13 +294,13 @@ static inline u64 atomic64_add_return(u64 i, atomic64_t *v)
 	smp_mb();
 
 	__asm__ __volatile__("@ atomic64_add_return\n"
-"1:	ldrexd	%0, %H0, [%2]\n"
-"	adds	%0, %0, %3\n"
-"	adc	%H0, %H0, %H3\n"
-"	strexd	%1, %0, %H0, [%2]\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
+"	adds	%0, %0, %4\n"
+"	adc	%H0, %H0, %H4\n"
+"	strexd	%1, %0, %H0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+m" (v->counter)
 	: "r" (&v->counter), "r" (i)
 	: "cc");
 
@@ -315,13 +315,13 @@ static inline void atomic64_sub(u64 i, atomic64_t *v)
 	unsigned long tmp;
 
 	__asm__ __volatile__("@ atomic64_sub\n"
-"1:	ldrexd	%0, %H0, [%2]\n"
-"	subs	%0, %0, %3\n"
-"	sbc	%H0, %H0, %H3\n"
-"	strexd	%1, %0, %H0, [%2]\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
+"	subs	%0, %0, %4\n"
+"	sbc	%H0, %H0, %H4\n"
+"	strexd	%1, %0, %H0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+m" (v->counter)
 	: "r" (&v->counter), "r" (i)
 	: "cc");
 }
@@ -334,13 +334,13 @@ static inline u64 atomic64_sub_return(u64 i, atomic64_t *v)
 	smp_mb();
 
 	__asm__ __volatile__("@ atomic64_sub_return\n"
-"1:	ldrexd	%0, %H0, [%2]\n"
-"	subs	%0, %0, %3\n"
-"	sbc	%H0, %H0, %H3\n"
-"	strexd	%1, %0, %H0, [%2]\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
+"	subs	%0, %0, %4\n"
+"	sbc	%H0, %H0, %H4\n"
+"	strexd	%1, %0, %H0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+m" (v->counter)
 	: "r" (&v->counter), "r" (i)
 	: "cc");
 
@@ -356,17 +356,17 @@ static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new)
 
 	smp_mb();
 
-	do {
-		__asm__ __volatile__("@ atomic64_cmpxchg\n"
-		"ldrexd		%1, %H1, [%2]\n"
-		"mov		%0, #0\n"
-		"teq		%1, %3\n"
-		"teqeq		%H1, %H3\n"
-		"strexdeq	%0, %4, %H4, [%2]"
-		: "=&r" (res), "=&r" (oldval)
-		: "r" (&ptr->counter), "r" (old), "r" (new)
-		: "cc");
-	} while (res);
+	__asm__ __volatile__("@ atomic64_cmpxchg\n"
+"1:	ldrexd		%1, %H1, [%3]\n"
+"	mov		%0, #0\n"
+"	teq		%1, %4\n"
+"	teqeq		%H1, %H4\n"
+"	strexdeq	%0, %5, %H5, [%3]\n"
+"	teq		%0, #0\n"
+"	bne		1b"
+	: "=&r" (res), "=&r" (oldval), "+m" (ptr->counter)
+	: "r" (&ptr->counter), "r" (old), "r" (new)
+	: "cc");
 
 	smp_mb();
 
@@ -381,11 +381,11 @@ static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new)
 	smp_mb();
 
 	__asm__ __volatile__("@ atomic64_xchg\n"
-"1:	ldrexd	%0, %H0, [%2]\n"
-"	strexd	%1, %3, %H3, [%2]\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
+"	strexd	%1, %4, %H4, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+m" (ptr->counter)
 	: "r" (&ptr->counter), "r" (new)
 	: "cc");
 
@@ -402,16 +402,16 @@ static inline u64 atomic64_dec_if_positive(atomic64_t *v)
 	smp_mb();
 
 	__asm__ __volatile__("@ atomic64_dec_if_positive\n"
-"1:	ldrexd	%0, %H0, [%2]\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
 "	subs	%0, %0, #1\n"
 "	sbc	%H0, %H0, #0\n"
 "	teq	%H0, #0\n"
 "	bmi	2f\n"
-"	strexd	%1, %0, %H0, [%2]\n"
+"	strexd	%1, %0, %H0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b\n"
 "2:"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+m" (v->counter)
 	: "r" (&v->counter)
 	: "cc");
 
@@ -424,23 +424,24 @@ static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
 {
 	u64 val;
 	unsigned long tmp;
-	int ret = 1;
+	int ret;
 
 	smp_mb();
 
 	__asm__ __volatile__("@ atomic64_add_unless\n"
-"1:	ldrexd	%0, %H0, [%3]\n"
-"	teq	%0, %4\n"
-"	teqeq	%H0, %H4\n"
+"1:	ldrexd	%0, %H0, [%4]\n"
+"	teq	%0, %5\n"
+"	teqeq	%H0, %H5\n"
 "	moveq	%1, #0\n"
+"	movne	%1, #1\n"
 "	beq	2f\n"
-"	adds	%0, %0, %5\n"
-"	adc	%H0, %H0, %H5\n"
-"	strexd	%2, %0, %H0, [%3]\n"
+"	adds	%0, %0, %6\n"
+"	adc	%H0, %H0, %H6\n"
+"	strexd	%2, %0, %H0, [%4]\n"
 "	teq	%2, #0\n"
 "	bne	1b\n"
 "2:"
-	: "=&r" (val), "=&r" (ret), "=&r" (tmp)
+	: "=&r" (val), "=&r" (ret), "=&r" (tmp), "+m" (v->counter)
 	: "r" (&v->counter), "r" (u), "r" (a)
 	: "cc");
 
-- 
1.6.3.3



From schindele at nentec.de  Wed Jun 23 11:06:32 2010
From: schindele at nentec.de (Juergen Schindele)
Date: Wed, 23 Jun 2010 17:06:32 +0200
Subject: strange segfaults with CompactFlash in "true-ide" mode on PXA270
Message-ID: <201006231706.33182.schindele@nentec.de>

Dear developers,
we have a strange problem when booting from a Compact Flash card
as root-device. In one of 10 cases while booting an application from
root-filesystem dies with "Segmentation fault" without a visible error.
After booting the same application runs hundred times without error.
(we're talking about standard appl. like chat, pppd, hwclock and so on)

For debugging purposes we put printk's in kernels IDE driver 
and the problem disappeared. But replacing the printk by a usleep
or so (which is not a solution !) brings the problem back.
It seems that the application received faulty data from CF.
But how and why ?????????????????????????????

We tested with a custom PXA270 board with a CompactFlash in 
"true ide" on processor bus driven by "generic ide / pata_platform"
driver from linux-2.6.27.x.
(by the way linux-2.6.20.x showed the same problem).

Any ideas, hints, experiences, patches are very welcome :-)
--------------------------------------------------------------
J?rgen Schindele  
Software-Entwicklung

PSI NENTEC GmbH
Greschbachstr. 12
76229 Karlsruhe
Deutschland
Telefon: +49 721 94249-51
Telefax: +49 721 94249-10
E-Mail:  schindele at nentec.de
WEB:     www.nentec.de
 
Gesch?ftsf?hrung: Klaus Becker, Roland Knapp
Sitz der Gesellschaft: Karlsruhe
Handelsregister: Amtsgericht Mannheim HRB 107658
--------------------------------------------------------------


From eric at eukrea.com  Wed Jun 23 11:07:49 2010
From: eric at eukrea.com (=?ISO-8859-1?Q?Eric_B=E9nard?=)
Date: Wed, 23 Jun 2010 17:07:49 +0200
Subject: [PATCH] otg/ulpi.c : fix register write
In-Reply-To: <20100623145816.GE2698@buzzloop.caiaq.de>
References: <1277304632-11314-1-git-send-email-eric@eukrea.com>
	<20100623145816.GE2698@buzzloop.caiaq.de>
Message-ID: <4C222345.4000902@eukrea.com>

Le 23/06/2010 16:58, Daniel Mack a ?crit :
> On Wed, Jun 23, 2010 at 04:50:32PM +0200, Eric B?nard wrote:
>> -static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
>> +static int ulpi_write(struct otg_transceiver *otg, u32 reg, u32 val)
>
> Urgs. Is this really necessary? It's not that I have a strong opinion
> about the order of arguments in such cases (I kept to the convention
> of __readl() when I wrote it). But _changing_ it like this is really
> confusing. Once in awhile I stumble over such API changes and I always
> wonder about the reason. The problem is that not even the compiler will
> warn you if you got it wrong, when you copied a sniplet from older
> sources etc.
>
> And you really want to break someone knee caps once you find out what
> caused the breakage ;)
>
> So - if we can avoid that, we should do. If anyone speaks up with a real
> reason for changing it, I'd be fine :)
>
No problem if you prefer to keep as it is (this is "cosmetic" but val 
and reg are reversed in include/linux/usb/otg.h which I took as the 
reference in the present case).
Do you have any opinion on the other part of the patch which removes 
ULPI_SET as this prevents to clear bits in the phy register ? If ok for 
you, I send a revised patch containing only this change.

Thanks,
Eric


From grinberg at compulab.co.il  Wed Jun 23 11:16:53 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 23 Jun 2010 18:16:53 +0300
Subject: [PATCH] otg/ulpi.c : fix register write
In-Reply-To: <1277304632-11314-1-git-send-email-eric@eukrea.com>
References: <1277304632-11314-1-git-send-email-eric@eukrea.com>
Message-ID: <4C222565.5000407@compulab.co.il>



On 06/23/10 17:50, Eric B?nard wrote:
> * drivers/usb/otg/ulpi.c :
> ulpi_set_vbus and ulpi_set_flags are using ULPI_SET(register) to write
> to the PHY's registers, which means we can only set bits in the PHY's
> register and not clear them.
> By directly using the address of the register without any offset, we
> now get the expected behaviour for these functions.
>
> * this patch also keep usage of otg_io_write & ulpi parameters coherent
> as in include/linux/usb/otg.h we have :
> otg_io_write(struct otg_transceiver *otg, u32 reg, u32 val)
>   

and also:

struct otg_io_access_ops {
         int (*read)(struct otg_transceiver *otg, u32 reg);
<http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=include/linux/usb/otg.h;h=f8302d036a7674e33109bf8fce16d67325d2d17a;hb=HEAD#l60> 
       int (*write)(struct otg_transceiver *otg, u32 val, u32 reg);
};

and please, look here:
http://comments.gmane.org/gmane.linux.usb.general/32092

> so keep the same parameters order in drivers/usb/otg/ulpi.c and
> arch/arm/plat-mxc/ulpi.c.
>
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> Cc: Daniel Mack <daniel at caiaq.de>
> Cc: linux-usb at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Sascha Hauer <kernel at pengutronix.de>
> ---
>  arch/arm/plat-mxc/ulpi.c |    2 +-
>  drivers/usb/otg/ulpi.c   |    4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
> index 582c6df..84eb5c7 100644
> --- a/arch/arm/plat-mxc/ulpi.c
> +++ b/arch/arm/plat-mxc/ulpi.c
> @@ -83,7 +83,7 @@ static int ulpi_read(struct otg_transceiver *otg, u32 reg)
>  	return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
>  }
>  
> -static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
> +static int ulpi_write(struct otg_transceiver *otg, u32 reg, u32 val)
>  {
>  	int ret;
>  	void __iomem *view = otg->io_priv;
> diff --git a/drivers/usb/otg/ulpi.c b/drivers/usb/otg/ulpi.c
> index b1b3469..f6048ca 100644
> --- a/drivers/usb/otg/ulpi.c
> +++ b/drivers/usb/otg/ulpi.c
> @@ -54,7 +54,7 @@ static int ulpi_set_flags(struct otg_transceiver *otg)
>  	if (otg->flags & USB_OTG_EXT_VBUS_INDICATOR)
>  		flags |= ULPI_OTG_CTRL_EXTVBUSIND;
>  
> -	return otg_io_write(otg, flags, ULPI_SET(ULPI_OTG_CTRL));
> +	return otg_io_write(otg, ULPI_OTG_CTRL, flags);
>  }
>  
>  static int ulpi_init(struct otg_transceiver *otg)
> @@ -90,7 +90,7 @@ static int ulpi_set_vbus(struct otg_transceiver *otg, bool on)
>  			flags |= ULPI_OTG_CTRL_DRVVBUS_EXT;
>  	}
>  
> -	return otg_io_write(otg, flags, ULPI_SET(ULPI_OTG_CTRL));
> +	return otg_io_write(otg, ULPI_OTG_CTRL, flags);
>  }
>  
>  struct otg_transceiver *
>   

-- 
Regards,
Igor.



From grinberg at compulab.co.il  Wed Jun 23 11:20:41 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Wed, 23 Jun 2010 18:20:41 +0300
Subject: [PATCH] otg/ulpi.c : fix register write
In-Reply-To: <1277304632-11314-1-git-send-email-eric@eukrea.com>
References: <1277304632-11314-1-git-send-email-eric@eukrea.com>
Message-ID: <4C222649.8050100@compulab.co.il>

Sorry for that link inside the code, should be:

On 06/23/10 17:50, Eric B?nard wrote:
> * drivers/usb/otg/ulpi.c :
> ulpi_set_vbus and ulpi_set_flags are using ULPI_SET(register) to write
> to the PHY's registers, which means we can only set bits in the PHY's
> register and not clear them.
> By directly using the address of the register without any offset, we
> now get the expected behaviour for these functions.
>
> * this patch also keep usage of otg_io_write & ulpi parameters coherent
> as in include/linux/usb/otg.h we have :
> otg_io_write(struct otg_transceiver *otg, u32 reg, u32 val)
>   

and also:

struct otg_io_access_ops {
         int (*read)(struct otg_transceiver *otg, u32 reg);
         int (*write)(struct otg_transceiver *otg, u32 val, u32 reg);
};

and please, look here:
http://comments.gmane.org/gmane.linux.usb.general/32092


> so keep the same parameters order in drivers/usb/otg/ulpi.c and
> arch/arm/plat-mxc/ulpi.c.
>
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> Cc: Daniel Mack <daniel at caiaq.de>
> Cc: linux-usb at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Sascha Hauer <kernel at pengutronix.de>
> ---
>  arch/arm/plat-mxc/ulpi.c |    2 +-
>  drivers/usb/otg/ulpi.c   |    4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/plat-mxc/ulpi.c b/arch/arm/plat-mxc/ulpi.c
> index 582c6df..84eb5c7 100644
> --- a/arch/arm/plat-mxc/ulpi.c
> +++ b/arch/arm/plat-mxc/ulpi.c
> @@ -83,7 +83,7 @@ static int ulpi_read(struct otg_transceiver *otg, u32 reg)
>  	return (__raw_readl(view) >> ULPIVW_RDATA_SHIFT) & ULPIVW_RDATA_MASK;
>  }
>  
> -static int ulpi_write(struct otg_transceiver *otg, u32 val, u32 reg)
> +static int ulpi_write(struct otg_transceiver *otg, u32 reg, u32 val)
>  {
>  	int ret;
>  	void __iomem *view = otg->io_priv;
> diff --git a/drivers/usb/otg/ulpi.c b/drivers/usb/otg/ulpi.c
> index b1b3469..f6048ca 100644
> --- a/drivers/usb/otg/ulpi.c
> +++ b/drivers/usb/otg/ulpi.c
> @@ -54,7 +54,7 @@ static int ulpi_set_flags(struct otg_transceiver *otg)
>  	if (otg->flags & USB_OTG_EXT_VBUS_INDICATOR)
>  		flags |= ULPI_OTG_CTRL_EXTVBUSIND;
>  
> -	return otg_io_write(otg, flags, ULPI_SET(ULPI_OTG_CTRL));
> +	return otg_io_write(otg, ULPI_OTG_CTRL, flags);
>  }
>  
>  static int ulpi_init(struct otg_transceiver *otg)
> @@ -90,7 +90,7 @@ static int ulpi_set_vbus(struct otg_transceiver *otg, bool on)
>  			flags |= ULPI_OTG_CTRL_DRVVBUS_EXT;
>  	}
>  
> -	return otg_io_write(otg, flags, ULPI_SET(ULPI_OTG_CTRL));
> +	return otg_io_write(otg, ULPI_OTG_CTRL, flags);
>  }
>  
>  struct otg_transceiver *
>   

-- 
Regards,
Igor.



From eric at eukrea.com  Wed Jun 23 11:22:35 2010
From: eric at eukrea.com (=?UTF-8?B?RXJpYyBCw6luYXJk?=)
Date: Wed, 23 Jun 2010 17:22:35 +0200
Subject: [PATCH] otg/ulpi.c : fix register write
In-Reply-To: <4C222649.8050100@compulab.co.il>
References: <1277304632-11314-1-git-send-email-eric@eukrea.com>
	<4C222649.8050100@compulab.co.il>
Message-ID: <4C2226BB.1060402@eukrea.com>

Hi Igor,

Le 23/06/2010 17:20, Igor Grinberg a ?crit :
> and also:
>
> struct otg_io_access_ops {
>           int (*read)(struct otg_transceiver *otg, u32 reg);
>           int (*write)(struct otg_transceiver *otg, u32 val, u32 reg);
> };
>
> and please, look here:
> http://comments.gmane.org/gmane.linux.usb.general/32092
>
OK, you took the problem from the right side :-)

Thanks
Eric


From LW at KARO-electronics.de  Wed Jun 23 11:24:15 2010
From: LW at KARO-electronics.de (=?iso-8859-15?Q?Lothar_Wa=DFmann?=)
Date: Wed, 23 Jun 2010 17:24:15 +0200
Subject: strange segfaults with CompactFlash in "true-ide" mode on PXA270
In-Reply-To: <201006231706.33182.schindele@nentec.de>
References: <201006231706.33182.schindele@nentec.de>
Message-ID: <19490.10015.10027.750374@ipc1.ka-ro>

Hi,

> we have a strange problem when booting from a Compact Flash card
> as root-device. In one of 10 cases while booting an application from
> root-filesystem dies with "Segmentation fault" without a visible error.
> After booting the same application runs hundred times without error.
> (we're talking about standard appl. like chat, pppd, hwclock and so on)
> 
> For debugging purposes we put printk's in kernels IDE driver 
> and the problem disappeared. But replacing the printk by a usleep
> or so (which is not a solution !) brings the problem back.
> It seems that the application received faulty data from CF.
> But how and why ?????????????????????????????
> 
> We tested with a custom PXA270 board with a CompactFlash in 
> "true ide" on processor bus driven by "generic ide / pata_platform"
> driver from linux-2.6.27.x.
> (by the way linux-2.6.20.x showed the same problem).
> 
> Any ideas, hints, experiences, patches are very welcome :-)
> --------------------------------------------------------------
I guess that is the old cache problem that apparently was never really
fixed:
http://marc.info/?t=108537828400002&r=1&w=2


Lothar Wa?mann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstra?e 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Gesch?ftsf?hrer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info at karo-electronics.de
___________________________________________________________


From eric at eukrea.com  Wed Jun 23 12:43:55 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Wed, 23 Jun 2010 18:43:55 +0200
Subject: [PATCH v2] otg/ulpi.c : fix register write
Message-ID: <1277311435-12027-1-git-send-email-eric@eukrea.com>

ulpi_set_vbus and ulpi_set_flags are using ULPI_SET(register) to write
to the PHY's registers, which means we can only set bits in the PHY's
register and not clear them.
By directly using the address of the register without any offset, we
now get the expected behaviour for these functions.

Signed-off-by: Eric B?nard <eric at eukrea.com>
Cc: Daniel Mack <daniel at caiaq.de>
Cc: linux-usb at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: Sascha Hauer <kernel at pengutronix.de>
---
v2 :
drop reg/val swap which is handled in a better way by Igor's patch here :
http://comments.gmane.org/gmane.linux.usb.general/32092 
 
 drivers/usb/otg/ulpi.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/otg/ulpi.c b/drivers/usb/otg/ulpi.c
index b1b3469..086853b 100644
--- a/drivers/usb/otg/ulpi.c
+++ b/drivers/usb/otg/ulpi.c
@@ -54,7 +54,7 @@ static int ulpi_set_flags(struct otg_transceiver *otg)
 	if (otg->flags & USB_OTG_EXT_VBUS_INDICATOR)
 		flags |= ULPI_OTG_CTRL_EXTVBUSIND;
 
-	return otg_io_write(otg, flags, ULPI_SET(ULPI_OTG_CTRL));
+	return otg_io_write(otg, flags, ULPI_OTG_CTRL);
 }
 
 static int ulpi_init(struct otg_transceiver *otg)
@@ -90,7 +90,7 @@ static int ulpi_set_vbus(struct otg_transceiver *otg, bool on)
 			flags |= ULPI_OTG_CTRL_DRVVBUS_EXT;
 	}
 
-	return otg_io_write(otg, flags, ULPI_SET(ULPI_OTG_CTRL));
+	return otg_io_write(otg, flags, ULPI_OTG_CTRL);
 }
 
 struct otg_transceiver *
-- 
1.6.3.3



From robert.jarzmik at free.fr  Wed Jun 23 13:49:59 2010
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Wed, 23 Jun 2010 19:49:59 +0200
Subject: [PATCH 3/4] pxa2xx/cpufreq: Fix PCMCIA frequency scaling
In-Reply-To: <1276840135-5982-3-git-send-email-marek.vasut@gmail.com> (Marek
	Vasut's message of "Fri\, 18 Jun 2010 07\:48\:54 +0200")
References: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
	<1276840135-5982-3-git-send-email-marek.vasut@gmail.com>
Message-ID: <87mxulabaw.fsf@free.fr>

Marek Vasut <marek.vasut at gmail.com> writes:

> The MCxx values must be based off memory clock, not CPU core clock.
>
> This also fixes the bug where on some machines the LCD went crazy while using
> PCMCIA.
That looks correct to me.

Reviewed-by: Robert Jarzmik <robert.jarzmik at free.fr>

Cheers.

--
Robert


From augulis.darius at gmail.com  Tue Jun 22 09:45:18 2010
From: augulis.darius at gmail.com (Darius Augulis)
Date: Tue, 22 Jun 2010 16:45:18 +0300
Subject: [PATCH 4/4] ARM: S3C2416: Add platform helpers for setup SDHCI
In-Reply-To: <1277212585-25605-5-git-send-email-jekhor@gmail.com>
References: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
	<1277212585-25605-2-git-send-email-jekhor@gmail.com>
	<1277212585-25605-3-git-send-email-jekhor@gmail.com>
	<1277212585-25605-4-git-send-email-jekhor@gmail.com>
	<1277212585-25605-5-git-send-email-jekhor@gmail.com>
Message-ID: <AANLkTimUijwXx5UozqVZiJ8BBDysnxd5nQz8P5d1slRC@mail.gmail.com>

On Tue, Jun 22, 2010 at 4:16 PM, Yauhen Kharuzhy <jekhor at gmail.com> wrote:

> Samsung S3C2416 has two SDHCI controllers compatible with other
> Samsung's SoCs (S3C64XX, S5PC100 etc...).
>
> Add required platform setup code that the devices can be used with
> sdhci-s3c driver.
>
> Signed-off-by: Yauhen Kharuzhy <jekhor at gmail.com>
> ---
>  arch/arm/mach-s3c2416/Kconfig              |   23 ++++++++++
>  arch/arm/mach-s3c2416/Makefile             |    5 ++
>  arch/arm/mach-s3c2416/s3c2416.c            |    5 ++
>  arch/arm/mach-s3c2416/setup-sdhci-gpio.c   |   60
> +++++++++++++++++++++++++++
>  arch/arm/mach-s3c2416/setup-sdhci.c        |   62
> ++++++++++++++++++++++++++++
>  arch/arm/plat-samsung/include/plat/sdhci.h |   34 +++++++++++++++
>  6 files changed, 189 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-s3c2416/setup-sdhci-gpio.c
>  create mode 100644 arch/arm/mach-s3c2416/setup-sdhci.c
>
> diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig
> index eafb0ed..e055c7f 100644
> --- a/arch/arm/mach-s3c2416/Kconfig
> +++ b/arch/arm/mach-s3c2416/Kconfig
> @@ -25,6 +25,17 @@ config S3C2416_DMA
>        help
>          Internal config node for S3C2416 DMA support
>
> +config S3C2416_SETUP_SDHCI
> +       bool
> +       select S3C2416_SETUP_SDHCI_GPIO
> +       help
> +         Internal helper functions for S3C2416 based SDHCI systems
> +
> +config S3C2416_SETUP_SDHCI_GPIO
> +       bool
> +       help
> +         Common setup code for SDHCI gpio.
> +
>  menu "S3C2416 Machines"
>
>  config MACH_SMDK2416
> @@ -36,7 +47,19 @@ config MACH_SMDK2416
>        select S3C_DEV_HSMMC1
>        select S3C_DEV_NAND
>        select S3C_DEV_USB_HOST
> +       select S3C2416_SETUP_SDHCI
>        help
>          Say Y here if you are using an SMDK2416
>
> +config MACH_HANLIN_V3C
> +       bool "Hanlin eReader V3C"
> +       select CPU_S3C2416
> +       select S3C_DEV_HSMMC
> +       select S3C_DEV_HSMMC1
> +       select S3C_DEV_NAND
> +       select S3C_DEV_USB_HOST
> +       select S3C2416_SETUP_SDHCI
> +       help
> +         Say Y here if you are using an Jinke's Hanlin V3C eReader
> +
>  endmenu
> diff --git a/arch/arm/mach-s3c2416/Makefile
> b/arch/arm/mach-s3c2416/Makefile
> index 6c12c7b..678e148 100644
> --- a/arch/arm/mach-s3c2416/Makefile
> +++ b/arch/arm/mach-s3c2416/Makefile
> @@ -14,6 +14,11 @@ obj-$(CONFIG_CPU_S3C2416)    += irq.o
>
>  #obj-$(CONFIG_S3C2416_DMA)     += dma.o
>
> +# Device setup
> +obj-$(CONFIG_S3C2416_SETUP_SDHCI) += setup-sdhci.o
> +obj-$(CONFIG_S3C2416_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
> +
>  # Machine support
>
>  obj-$(CONFIG_MACH_SMDK2416)    += mach-smdk2416.o
> +obj-$(CONFIG_MACH_HANLIN_V3C)  += mach-v3c.o
> diff --git a/arch/arm/mach-s3c2416/s3c2416.c
> b/arch/arm/mach-s3c2416/s3c2416.c
> index 355ab62..06eacf8 100644
> --- a/arch/arm/mach-s3c2416/s3c2416.c
> +++ b/arch/arm/mach-s3c2416/s3c2416.c
> @@ -53,6 +53,7 @@
>  #include <plat/s3c2416.h>
>  #include <plat/devs.h>
>  #include <plat/cpu.h>
> +#include <plat/sdhci.h>
>
>  #include <plat/iic-core.h>
>
> @@ -115,6 +116,10 @@ void __init s3c2416_map_io(void)
>        s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown;
>        s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown;
>
> +       /* initialize device information early */
> +       s3c2416_default_sdhci0();
> +       s3c2416_default_sdhci1();
> +
>        iotable_init(s3c2416_iodesc, ARRAY_SIZE(s3c2416_iodesc));
>  }
>
> diff --git a/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
> b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
> new file mode 100644
> index 0000000..ebdab15
> --- /dev/null
> +++ b/arch/arm/mach-s3c2416/setup-sdhci-gpio.c
> @@ -0,0 +1,60 @@
> +/* linux/arch/arm/plat-s3c2416/setup-sdhci-gpio.c
> + *
> + * Copyright 2010 Promwad Innovation Company
> + *     Yauhen Kharuzhy <yauhen.kharuzhy at promwad.com>
> + *
> + * S3C2416 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
> + *
> + * Based on mach-s3c64xx/setup-sdhci-gpio.c
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#include <mach/gpio.h>
> +#include <mach/regs-gpio.h>
> +#include <plat/gpio-cfg.h>
> +
> +/* Note: hsmmc1 and hsmmc0 are swapped versus datasheet */
>

would be nice to provide more accurate link to information source (document
version, page).
And there is a bit tricky place: clock ids are swapped and names of helper
functions are not.
So, it's not clear which helper function corresponds to real physical SDHC
interface.

+
> +void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
> +{
> +       unsigned int gpio;
> +       unsigned int end;
> +
> +       end = S3C2410_GPE(7 + width);
> +
> +       /* Set all the necessary GPE pins to special-function 0 */
> +       for (gpio = S3C2410_GPE(5); gpio < end; gpio++) {
> +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> +       }
> +}
> +
> +void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
> +{
> +       unsigned int gpio;
> +       unsigned int end;
> +
> +       end = S3C2410_GPL(0 + width);
> +
> +       /* Set all the necessary GPG pins to special-function 0 */
> +       for (gpio = S3C2410_GPL(0); gpio < end; gpio++) {
> +               s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
> +               s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
> +       }
> +
> +       s3c_gpio_cfgpin(S3C2410_GPL(8), S3C_GPIO_SFN(2));
> +       s3c_gpio_setpull(S3C2410_GPL(8), S3C_GPIO_PULL_NONE);
> +       s3c_gpio_cfgpin(S3C2410_GPL(9), S3C_GPIO_SFN(2));
> +       s3c_gpio_setpull(S3C2410_GPL(9), S3C_GPIO_PULL_NONE);
> +}
> +
> +
> diff --git a/arch/arm/mach-s3c2416/setup-sdhci.c
> b/arch/arm/mach-s3c2416/setup-sdhci.c
> new file mode 100644
> index 0000000..345ddd1
> --- /dev/null
> +++ b/arch/arm/mach-s3c2416/setup-sdhci.c
> @@ -0,0 +1,62 @@
> +/* linux/arch/arm/mach-s3c2416/setup-sdhci.c
> + *
> + * Copyright 2010 Promwad Innovation Company
> + *     Yauhen Kharuzhy <yauhen.kharuzhy at promwad.com>
> + *
> + * S3C2416 - Helper functions for settign up SDHCI device(s) (HSMMC)
> + *
> + * Based on mach-s3c64xx/setup-sdhci.c
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/types.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#include <linux/mmc/card.h>
> +#include <linux/mmc/host.h>
> +
> +#include <plat/regs-sdhci.h>
> +#include <plat/sdhci.h>
> +
> +/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
> +
> +char *s3c2416_hsmmc_clksrcs[4] = {
> +       [0] = "hsmmc",
> +       [1] = "hsmmc",
> +       [2] = "hsmmc-if",
> +       /* [3] = "48m", - note not successfully used yet */
> +};
> +
> +void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
> +                                 void __iomem *r,
> +                                 struct mmc_ios *ios,
> +                                 struct mmc_card *card)
> +{
> +       u32 ctrl2, ctrl3;
> +
> +       ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
> +       ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
> +       ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
> +                 S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
> +                 S3C_SDHCI_CTRL2_ENFBCLKRX |
> +                 S3C_SDHCI_CTRL2_DFCNT_NONE |
> +                 S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
> +
> +       if (ios->clock < 25 * 1000000)
> +               ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
> +                        S3C_SDHCI_CTRL3_FCSEL2 |
> +                        S3C_SDHCI_CTRL3_FCSEL1 |
> +                        S3C_SDHCI_CTRL3_FCSEL0);
> +       else
> +               ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
> +
> +       writel(ctrl2, r + S3C_SDHCI_CONTROL2);
> +       writel(ctrl3, r + S3C_SDHCI_CONTROL3);
> +}
> +
> diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h
> b/arch/arm/plat-samsung/include/plat/sdhci.h
> index 13f9fb2..d408140 100644
> --- a/arch/arm/plat-samsung/include/plat/sdhci.h
> +++ b/arch/arm/plat-samsung/include/plat/sdhci.h
> @@ -78,6 +78,8 @@ extern void s3c64xx_setup_sdhci2_cfg_gpio(struct
> platform_device *, int w);
>  extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int
> w);
>  extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int
> w);
>  extern void s5pv210_setup_sdhci2_cfg_gpio(struct platform_device *, int
> w);
> +extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int
> w);
> +extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int
> w);
>
>  /* S3C6400 SDHCI setup */
>
> @@ -270,6 +272,38 @@ static inline void s5pv210_default_sdhci1(void) { }
>  static inline void s5pv210_default_sdhci2(void) { }
>  #endif /* CONFIG_S5PC100_SETUP_SDHCI */
>
> +/* S3C2416 SDHCI setup */
> +#ifdef CONFIG_S3C2416_SETUP_SDHCI
> +extern char *s3c2416_hsmmc_clksrcs[4];
> +
> +extern void s3c2416_setup_sdhci_cfg_card(struct platform_device *dev,
> +                                          void __iomem *r,
> +                                          struct mmc_ios *ios,
> +                                          struct mmc_card *card);
> +
> +#ifdef CONFIG_S3C_DEV_HSMMC
> +static inline void s3c2416_default_sdhci0(void)
> +{
> +       s3c_hsmmc0_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
> +       s3c_hsmmc0_def_platdata.cfg_gpio = s3c2416_setup_sdhci0_cfg_gpio;
> +       s3c_hsmmc0_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
>

helper id 0 gets to interface 0 - not swapped.


> +}
> +#else
> +static inline void s3c2416_default_sdhci0(void) { }
> +#endif /* CONFIG_S3C_DEV_HSMMC */
> +
> +#ifdef CONFIG_S3C_DEV_HSMMC1
> +static inline void s3c2416_default_sdhci1(void)
> +{
> +       s3c_hsmmc1_def_platdata.clocks = s3c2416_hsmmc_clksrcs;
> +       s3c_hsmmc1_def_platdata.cfg_gpio = s3c2416_setup_sdhci1_cfg_gpio;
> +       s3c_hsmmc1_def_platdata.cfg_card = s3c2416_setup_sdhci_cfg_card;
>

helper id 1 gets to interface 1 - not swapped.


> +}
> +#else
> +static inline void s3c2416_default_sdhci1(void) { }
> +#endif /* CONFIG_S3C_DEV_HSMMC1 */
> +
> +#endif /* CONFIG_S3C2416_SETUP_SDHCI */
>
>
>
> --
> 1.6.6.1
>
>
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From pankaj.embedded at gmail.com  Wed Jun 23 11:59:57 2010
From: pankaj.embedded at gmail.com (Pankaj Pandey)
Date: Wed, 23 Jun 2010 21:29:57 +0530
Subject: Unhandled fault: imprecise external abort
Message-ID: <AANLkTimFhC7PZaT9VVwyVH-jp7Ro74w7sSX2Ma1SX7Mn@mail.gmail.com>

Hi,

I am working on Freescale MXC series based target board runing  with 2.6.31
kernel. I have written a small test application to test the one of  driver.
In my test application, I am using mmap to map the kernel memory to user
space and  I am trying to read some register values.
My user space mmap function is as such :

 virt_addr = mmap(NULL, 4 * 1024, PROT_READ, MAP_SHARED ,fd, 0);

The mmap returns a specific address in virt_addr.

When I try to read the contents of this address , the kernel throws
following error :

 Unhandled fault: imprecise external abort (0xc06) at 0x00000000

Any pointers on this will great help to resolve this issue.

Thanks and Regards,
Pankaj Pandey
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From santosh.shilimkar at ti.com  Wed Jun 23 14:45:11 2010
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Thu, 24 Jun 2010 00:15:11 +0530
Subject: Unhandled fault: imprecise external abort
In-Reply-To: <EAF47CD23C76F840A9E7FCE10091EFAB02C5D15BE2@dbde02.ent.ti.com>
References: <AANLkTimFhC7PZaT9VVwyVH-jp7Ro74w7sSX2Ma1SX7Mn@mail.gmail.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C5D15BE2@dbde02.ent.ti.com>
Message-ID: <EAF47CD23C76F840A9E7FCE10091EFAB02C5D15BE3@dbde02.ent.ti.com>


> _______________________________________
> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-kernel-
> bounces at lists.infradead.org] On Behalf Of Pankaj Pandey
> Sent: Wednesday, June 23, 2010 9:30 PM
> To: linux-arm-kernel at lists.infradead.org
> Subject: Unhandled fault: imprecise external abort
> 
> Hi,
> 
> I am working on Freescale MXC series based target board runing? with 2.6.31 kernel. I have written a
> small test application to test the one of? driver. In my test application, I am using mmap to map the
> kernel memory to user space and? I am trying to read some register values.
> My user space mmap function is as such :
> 
> ?virt_addr = mmap(NULL, 4 * 1024, PROT_READ, MAP_SHARED ,fd, 0);
> 
> The mmap returns a specific address in virt_addr.
> 
> When I try to read the contents of this address , the kernel throws following error :
> 
> ?Unhandled fault: imprecise external abort (0xc06) at 0x00000000
> 
> Any pointers on this will great help to resolve this issue.
> 
Are you able to access these registers from kernel space ??
If the kernel space access also reports the external abort then looks like you
are trying to access the registers of module which is not clocked 
or is in non-accessible state.

Regards,
Santosh




From robert.jarzmik at free.fr  Wed Jun 23 15:00:19 2010
From: robert.jarzmik at free.fr (Robert Jarzmik)
Date: Wed, 23 Jun 2010 21:00:19 +0200
Subject: [PATCH 1/4] pxa2xx/cpufreq: Simplify CPU frequency change asm
In-Reply-To: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com> (Marek
	Vasut's message of "Fri\, 18 Jun 2010 07\:48\:52 +0200")
References: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <87eifxa81o.fsf@free.fr>

Marek Vasut <marek.vasut at gmail.com> writes:

> This patch does the following changes to cpufreq-pxa2xx:
> 1) Simplifies the assembler code for frequency change
OK, but did you think over what the old code was doing ?
My guess is that all the jumps were there to trigger a load into the I-Cache
before playing with memory timings. Did you consider that your new assembly fits
fully into a cache line, and hence is protected from memory shutdown for the
frequency change period ?

If you thought this over, then I would suggest to put a comment into the code to
state that the assembly bit fits fully in one cache line. If not, I don't see
clearly the benefit of removing the jumps ("b 2f" and "b 1b").

And I didn't find the reference for the need of reading the MDREFR register
after the write. Would you give me a pointer in the pxa27x TRM please ?

Cheers.

--
Robert


From ryan at bluewatersys.com  Wed Jun 23 15:12:50 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Thu, 24 Jun 2010 07:12:50 +1200
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping
	gpios)
In-Reply-To: <728731.73469.qm@web180307.mail.gq1.yahoo.com>
References: <728731.73469.qm@web180307.mail.gq1.yahoo.com>
Message-ID: <4C225CB2.6090407@bluewatersys.com>

David Brownell wrote:
> 
> --- On Tue, 6/22/10, Ryan Mallon <ryan at bluewatersys.com> wrote:
> 
>>> --- On Tue, 6/22/10, Ryan Mallon <ryan at bluewatersys.com>
>> wrote:

>>>> 'Can sleep' for a gpio has two different meanings
>> depending
>>>> on context
>>> NO; for the GPIO itself it's only ever had one
>>> meaning, regardless of context.
>>>
>>> You're trying to conflate the GPIO and one
>>> of the contexts in which it's used.  That's
>>> the problem you seem to be struggling with.
>>>
>>> Please stop conflating/confusing
>>> those two disparate concepts...
>> I'm not. 
> 
> BUT Your "counter" example below is solid
> proof that you are:  it shows exactly the
> confusion I pointed out:  call context versus
> the GPIO itself.  There's no way I can read
> that as anything except "you are"...
> 
>  
> Your intent here seems perhaps more to
> be a troll than to address any real
> technical issues.  I don't see much
> point participating any further.
> 
> 
>  Some gpios, such as those on io expanders, may
>> sleep in their
>> implementations of the gpio_(set/get) functions.
>>
> 
> Such GPIOs have a "cansleep" attribute, in short.
> 
> 
>> Drivers, which use a gpio, may call gpio_(set/get)
>> functions for a given
>> gpio from a context where it is not safe to sleep.
> 
> And that's the call dontext
> (in this case, from a driver).

Yes.

>   QED.  You are confusing two disparate concepts.

We are saying exactly the same thing.

> 
>  In this
>> case, a gpio
>> which may sleep (ie one on an i2c io-expander) cannot be
>> used with this
>> driver. The gpio_request will succeed, but any call to
>> gpio_(set/get)_value will produce a warning.
>>
>>>> example, if a driver calls gpio_get_value(gpio)
>> from an
>>>> interupt handler
> 
> 
> (YOU introduce interrupt/IRQ handlers...)
> 
>>>> then the gpio must not be a sleeping gpio.
>>> In a threaded IRQ handler it's OK to use
>>> the get_value_cansleep() option..
>> Ugh, you are really twisting my words.
> 
> 
> You said IRQ handler, so did I.  In what csense could I
> possibly be "twisting" your words"???
> 
> 
> STOP TROLLING.

Okay, I messed up the wording an used 'interrupt handler' as an example
of a non-sleep safe context. If I had said 'atomic' or 'spinlock'
context you would probably be telling me off for missing some other
non-sleep safe contexts.

The point is that we are discussing the issue of calls which may sleep.
Even if I was not entirely clear by getting the wording wrong, you _do_
know what I am talking about. You could correct on the bits on I get
wrong instead of labeling me a troll.

If we strip my patch back to just introducing gpio_request_cansleep,
which would be used in any driver where all of the calls are
gpio_(set/get)_cansleep, and make gpio_request only allow non-sleeping
gpios then incorrect use of gpios would be caught at request time and
returned to the caller as an error.

~Ryan




From linux at arm.linux.org.uk  Wed Jun 23 15:48:43 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 23 Jun 2010 20:48:43 +0100
Subject: [PATCH 1/6] [ARM] Make common definition for IO_SPACE_LIMIT
In-Reply-To: <1277293938-25804-2-git-send-email-eric.y.miao@gmail.com>
References: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
	<1277293938-25804-2-git-send-email-eric.y.miao@gmail.com>
Message-ID: <20100623194843.GA25070@n2100.arm.linux.org.uk>

On Wed, Jun 23, 2010 at 07:52:13PM +0800, Eric Miao wrote:
> diff --git a/arch/arm/mach-ebsa110/include/mach/io.h b/arch/arm/mach-ebsa110/include/mach/io.h
> index f68daa6..44679db 100644
> --- a/arch/arm/mach-ebsa110/include/mach/io.h
> +++ b/arch/arm/mach-ebsa110/include/mach/io.h
> @@ -13,8 +13,6 @@
>  #ifndef __ASM_ARM_ARCH_IO_H
>  #define __ASM_ARM_ARCH_IO_H
>  
> -#define IO_SPACE_LIMIT 0xffff
> -
>  u8 __inb8(unsigned int port);
>  void __outb8(u8  val, unsigned int port);
>  
> diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h
> index 101a4fe..c65ed51 100644
> --- a/arch/arm/mach-footbridge/include/mach/io.h
> +++ b/arch/arm/mach-footbridge/include/mach/io.h
> @@ -17,8 +17,6 @@
>  #define PCIO_SIZE		0x00100000
>  #define PCIO_BASE		0xff000000
>  
> -#define IO_SPACE_LIMIT 0xffff
> -
>  /*
>   * Translation of various region addresses to virtual addresses
>   */
> diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h
> index f21bb54..37beed3 100644
> --- a/arch/arm/mach-integrator/include/mach/io.h
> +++ b/arch/arm/mach-integrator/include/mach/io.h
> @@ -20,8 +20,6 @@
>  #ifndef __ASM_ARM_ARCH_IO_H
>  #define __ASM_ARM_ARCH_IO_H
>  
> -#define IO_SPACE_LIMIT 0xffff
> -
>  /*
>   * WARNING: this has to mirror definitions in platform.h
>   */

These three are 0xffff because they are PCI, and the PCI IO window is
64K.  Allowing reservations above this value could cause problems.


From linux at arm.linux.org.uk  Wed Jun 23 15:51:19 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 23 Jun 2010 20:51:19 +0100
Subject: [PATCH 3/6] [ARM] Make __mem_pci() common to all ARM
	sub-architectures
In-Reply-To: <1277293938-25804-4-git-send-email-eric.y.miao@gmail.com>
References: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
	<1277293938-25804-4-git-send-email-eric.y.miao@gmail.com>
Message-ID: <20100623195119.GB25070@n2100.arm.linux.org.uk>

On Wed, Jun 23, 2010 at 07:52:15PM +0800, Eric Miao wrote:
> On all ARM sub-architectures, __mem_pci() is defined to be a 1:1
> mapping, make it a common definition for all.

This is not true for ebsa110, which you'll notice is missing from
this diffstat.


From linux at arm.linux.org.uk  Wed Jun 23 15:54:56 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 23 Jun 2010 20:54:56 +0100
Subject: [PATCH 6/6] [ARM] Introduce common definition for __io()
In-Reply-To: <1277293938-25804-7-git-send-email-eric.y.miao@gmail.com>
References: <1277293938-25804-1-git-send-email-eric.y.miao@gmail.com>
	<1277293938-25804-7-git-send-email-eric.y.miao@gmail.com>
Message-ID: <20100623195456.GC25070@n2100.arm.linux.org.uk>

On Wed, Jun 23, 2010 at 07:52:18PM +0800, Eric Miao wrote:
> Signed-off-by: Eric Miao <eric.miao at canonical.com>
> ---
>  arch/arm/include/asm/io.h                 |    4 ++++
>  arch/arm/mach-aaec2000/include/mach/io.h  |    1 -
>  arch/arm/mach-at91/include/mach/io.h      |    1 -
>  arch/arm/mach-bcmring/include/mach/io.h   |    1 -
>  arch/arm/mach-clps711x/include/mach/io.h  |    1 -
>  arch/arm/mach-cns3xxx/include/mach/io.h   |    1 -
>  arch/arm/mach-davinci/include/mach/io.h   |    1 -
>  arch/arm/mach-ep93xx/include/mach/io.h    |    1 -

Again, ebsa110 is missing.

That's because __io() is a two-state definition.  It means something
if a platform does _not_ define it.  It also means something _if_ a
platform defines it.

You can't move it to asm/io.h because that precludes the first state
from ever occuring.  It's not a simple case that those platforms can
provide some subsitute definition for __io() - they have to supply
their own inb() et.al. accessors because they need to do something
uniquely special there.


From Jiri.Pinkava at vscht.cz  Wed Jun 23 16:06:52 2010
From: Jiri.Pinkava at vscht.cz (Pinkava J.)
Date: Wed, 23 Jun 2010 22:06:52 +0200
Subject: [PATCH] n35: fix key codes
Message-ID: <4C22695C.2010008@vscht.cz>

Someone copied code but forget set key codes.


Signed-off-by: Jiri Pinkava <jiri.pinkava at vscht.cz>
---
 arch/arm/mach-s3c2410/mach-n30.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 41f299d..c6bf1cf 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -193,13 +193,13 @@ static struct gpio_keys_button n35_buttons[] = {
 	},
 	{
 		.gpio		= S3C2410_GPG(6),
-		.code		= KEY_DOWN,
+		.code		= KEY_LEFT,
 		.desc		= "Joystick Left",
 		.active_low	= 0,
 	},
 	{
 		.gpio		= S3C2410_GPG(5),
-		.code		= KEY_DOWN,
+		.code		= KEY_RIGHT,
 		.desc		= "Joystick Right",
 		.active_low	= 0,
 	},
-- 
1.7.1



From Jiri.Pinkava at vscht.cz  Wed Jun 23 16:20:16 2010
From: Jiri.Pinkava at vscht.cz (Pinkava J.)
Date: Wed, 23 Jun 2010 22:20:16 +0200
Subject: [PATCH] n35: Update GPIO documentation for Acer n35
Message-ID: <4C226C80.20206@vscht.cz>



Signed-off-by: Jiri Pinkava <jiri.pinkava at vscht.cz>
---
 arch/arm/mach-s3c2410/mach-n30.c |   12 +++++-------
 1 files changed, 5 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index c6bf1cf..14c9882 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -411,13 +411,11 @@ static struct s3c2410_platform_i2c __initdata n30_i2ccfg = {
 static void __init n30_hwinit(void)
 {
 	/* GPA0-11 special functions -- unknown what they do
-	 * GPA12 N30 special function -- unknown what it does
-	 *       N35/PiN output -- unknown what it does
-	 *
-	 * A12 is nGCS1 on the N30 and an output on the N35/PiN.  I
-	 * don't think it does anything useful on the N30, so I ought
-	 * to make it an output there too since it always driven to 0
-	 * as far as I can tell. */
+	 * GPA12 N30 special function (nGCS1) -- unknown what it does
+	 *       PiN output -- unknown function
+	 *       N35 output -- turn on/off red led, 0 = normal operation,
+	 *       1 = turn off red led at all. Note: GPD9 must be output
+	 *       with value set to 1 before setting GPA12 to 0. */
 	if (machine_is_n30())
 		__raw_writel(0x007fffff, S3C2410_GPACON);
 	if (machine_is_n35())
-- 
1.7.1



From Jiri.Pinkava at vscht.cz  Wed Jun 23 16:31:04 2010
From: Jiri.Pinkava at vscht.cz (Pinkava J.)
Date: Wed, 23 Jun 2010 22:31:04 +0200
Subject: [PATCH] n30: Clean up UARTs configuration
Message-ID: <4C226F08.7090804@vscht.cz>


Signed-off-by: Jiri Pinkava <jiri.pinkava at vscht.cz>
---
 arch/arm/mach-s3c2410/mach-n30.c                 |   28 +++++++++++++++-------
 arch/arm/plat-samsung/include/plat/regs-serial.h |    3 ++
 2 files changed, 22 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 29fcb88..401460a 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -55,32 +55,42 @@ static struct map_desc n30_iodesc[] __initdata = {
 	/* nothing here yet */
 };

+#define UCON	(S3C2410_UCON_DEFAULT | \
+		 S3C2443_UCON_RXERR_IRQEN)
+
+#define ULCON	(S3C2410_LCON_CS8 | \
+		 S3C2410_LCON_PNONE)
+
+#define UFCON	(S3C2410_UFCON_FIFOMODE | \
+		 S3C2410_UFCON_RXTRIG8 | \
+		 S3C2410_UFCON_TXTRIG4)
+
 static struct s3c2410_uartcfg n30_uartcfgs[] = {
 	/* Normal serial port */
 	[0] = {
 		.hwport	     = 0,
 		.flags	     = 0,
-		.ucon	     = 0x2c5,
-		.ulcon	     = 0x03,
-		.ufcon	     = 0x51,
+		.ucon	     = UCON,
+		.ulcon	     = ULCON,
+		.ufcon	     = UFCON,
 	},
 	/* IR port */
 	[1] = {
 		.hwport	     = 1,
 		.flags	     = 0,
 		.uart_flags  = UPF_CONS_FLOW,
-		.ucon	     = 0x2c5,
-		.ulcon	     = 0x43,
-		.ufcon	     = 0x51,
+		.ucon	     = UCON,
+		.ulcon	     = ULCON | S3C2410_LCON_IRM,
+		.ufcon	     = UFCON,
 	},
 	/* On the N30 the bluetooth controller is connected here.
 	 * On the N35 and variants the GPS receiver is connected here. */
 	[2] = {
 		.hwport	     = 2,
 		.flags	     = 0,
-		.ucon	     = 0x2c5,
-		.ulcon	     = 0x03,
-		.ufcon	     = 0x51,
+		.ucon	     = UCON,
+		.ulcon	     = ULCON,
+		.ufcon	     = UFCON,
 	},
 };

diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h
b/arch/arm/plat-samsung/include/plat/regs-serial.h
index a6eba84..5840198 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -114,6 +114,9 @@

 #define S3C2410_UFCON_FIFOMODE	  (1<<0)
 #define S3C2410_UFCON_TXTRIG0	  (0<<6)
+#define S3C2410_UFCON_TXTRIG4	  (1<<6)
+#define S3C2410_UFCON_TXTRIG8	  (2<<6)
+#define S3C2410_UFCON_TXTRIG12	  (3<<6)
 #define S3C2410_UFCON_RXTRIG8	  (1<<4)
 #define S3C2410_UFCON_RXTRIG12	  (2<<4)

-- 
1.7.1



From jgarzik at pobox.com  Wed Jun 23 16:36:27 2010
From: jgarzik at pobox.com (Jeff Garzik)
Date: Wed, 23 Jun 2010 16:36:27 -0400
Subject: [PATCH v4] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
References: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <4C22704B.50103@pobox.com>

On 06/14/2010 03:07 AM, Kukjin Kim wrote:
> From: Abhilash Kesavan<a.kesavan at samsung.com>
>
> Adds support for the Samsung PATA controller. This driver is based on the
> Libata subsystem and references the earlier patches sent for IDE subsystem.
>
> Signed-off-by: Abhilash Kesavan<a.kesavan at samsung.com>
> Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>

Acked-by: Jeff Garzik <jgarzik at redhat.com>

Send it through the appropriate subsystem tree for this platform...




From lrg at slimlogic.co.uk  Wed Jun 23 16:50:59 2010
From: lrg at slimlogic.co.uk (Liam Girdwood)
Date: Wed, 23 Jun 2010 21:50:59 +0100
Subject: [PATCH] ASoC: DaVinci: Added support for stereo I2S
In-Reply-To: <1277303635-5675-1-git-send-email-lamiaposta71@gmail.com>
References: <1277303635-5675-1-git-send-email-lamiaposta71@gmail.com>
Message-ID: <1277326259.31686.57.camel@vega>

On Wed, 2010-06-23 at 16:33 +0200, Raffaele Recalcati wrote:
> From: Raffaele Recalcati <raffaele.recalcati at bticino.it>
> 
> 	Added audio playback support with [frame sync master - clock master] mode
> 	and with [frame sync master - clock slave].
> 	Clock slave can be important when the external codec need system clock
> 	and bit clock synchronized.
> 	In the clock master case there is a FIXME message in the source code, because we
> 	(Davide and myself) have guessed a frequency of 122000000 that seems the base
> 	to be divided.
> 	This patch has been developed against the
> 		http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
> 	git tree and has been tested on bmx board (similar to dm365 evm, but using
> 	uda1345 as external audio codec).
> 
> Signed-off-by: Raffaele Recalcati <raffaele.recalcati at bticino.it>
> Signed-off-by: Davide Bonfanti <davide.bonfanti at bticino.it>

Had a quick check, it looks like you have made some unintended
formatting changes that make the patch look more complex than necessary.

> ---
>  arch/arm/mach-davinci/include/mach/asp.h |    7 ++
>  sound/soc/davinci/davinci-i2s.c          |  141 ++++++++++++++++++++++++++----
>  2 files changed, 129 insertions(+), 19 deletions(-)
> 
> diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
> index 834725f..b1faeb9 100644
> --- a/arch/arm/mach-davinci/include/mach/asp.h
> +++ b/arch/arm/mach-davinci/include/mach/asp.h
> @@ -63,6 +63,13 @@ struct snd_platform_data {
>  	unsigned sram_size_playback;
>  	unsigned sram_size_capture;
>  
> +	/*
> +	 * This define works when both clock and FS are output for the cpu
> +	 * and makes clock very fast (FS is not simmetrical, but sampling
> +	 * frequency is better approximated
> +	 */
> +	int i2s_fast_clock;
> +
>  	/* McASP specific fields */
>  	int tdm_slots;
>  	u8 op_mode;
> diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
> index adadcd3..8811d25 100644
> --- a/sound/soc/davinci/davinci-i2s.c
> +++ b/sound/soc/davinci/davinci-i2s.c
> @@ -68,16 +68,23 @@
>  #define DAVINCI_MCBSP_RCR_RDATDLY(v)	((v) << 16)
>  #define DAVINCI_MCBSP_RCR_RFIG		(1 << 18)
>  #define DAVINCI_MCBSP_RCR_RWDLEN2(v)	((v) << 21)
> +#define DAVINCI_MCBSP_RCR_RFRLEN2(v)	((v) << 24)
> +#define DAVINCI_MCBSP_RCR_RPHASE		(1 << 31)
>  
>  #define DAVINCI_MCBSP_XCR_XWDLEN1(v)	((v) << 5)
>  #define DAVINCI_MCBSP_XCR_XFRLEN1(v)	((v) << 8)
>  #define DAVINCI_MCBSP_XCR_XDATDLY(v)	((v) << 16)
>  #define DAVINCI_MCBSP_XCR_XFIG		(1 << 18)
>  #define DAVINCI_MCBSP_XCR_XWDLEN2(v)	((v) << 21)
> +#define DAVINCI_MCBSP_XCR_XFRLEN2(v)	((v) << 24)
> +#define DAVINCI_MCBSP_XCR_XPHASE	(1 << 31)
>  
> +
> +#define CLKGDV(v)				(v)     /* Bits 0:7 */

Should you not have a DAVINCI prefix here too ?

>  #define DAVINCI_MCBSP_SRGR_FWID(v)	((v) << 8)
>  #define DAVINCI_MCBSP_SRGR_FPER(v)	((v) << 16)
>  #define DAVINCI_MCBSP_SRGR_FSGM		(1 << 28)
> +#define DAVINCI_MCBSP_SRGR_CLKSM	(1 << 29)
>  
>  #define DAVINCI_MCBSP_PCR_CLKRP		(1 << 0)
>  #define DAVINCI_MCBSP_PCR_CLKXP		(1 << 1)
> @@ -144,8 +151,17 @@ struct davinci_mcbsp_dev {
>  	 * won't end up being swapped because of the underrun.
>  	 */
>  	unsigned enable_channel_combine:1;
> +
> +	int i2s_fast_clock;
> +};
> +
> +struct davinci_mcbsp_data {
> +	unsigned int	fmt;
> +	int             clk_div;
>  };
>  
> +static struct davinci_mcbsp_data mcbsp_data;
> +

This struct should be part of the dai private data.

>  static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
>  					   int reg, u32 val)
>  {
> @@ -255,24 +271,27 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
>  	unsigned int pcr;
>  	unsigned int srgr;
>  	srgr = DAVINCI_MCBSP_SRGR_FSGM |
> -		DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
> -		DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
> +	       DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
> +	       DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
> +	/* Attention srgr is updated by hw_params! */
>  
> +	mcbsp_data.fmt = fmt;
>  	/* set master/slave audio interface */
>  	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
> +	case SND_SOC_DAIFMT_CBS_CFM:
>  	case SND_SOC_DAIFMT_CBS_CFS:
>  		/* cpu is master */
>  		pcr = DAVINCI_MCBSP_PCR_FSXM |
> -			DAVINCI_MCBSP_PCR_FSRM |
> -			DAVINCI_MCBSP_PCR_CLKXM |
> -			DAVINCI_MCBSP_PCR_CLKRM;
> +		      DAVINCI_MCBSP_PCR_FSRM |
> +		      DAVINCI_MCBSP_PCR_CLKXM |
> +		      DAVINCI_MCBSP_PCR_CLKRM;
>  		break;
>  	case SND_SOC_DAIFMT_CBM_CFS:
>  		/* McBSP CLKR pin is the input for the Sample Rate Generator.
>  		 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
>  		pcr = DAVINCI_MCBSP_PCR_SCLKME |
> -			DAVINCI_MCBSP_PCR_FSXM |
> -			DAVINCI_MCBSP_PCR_FSRM;
> +		      DAVINCI_MCBSP_PCR_FSXM |
> +		      DAVINCI_MCBSP_PCR_FSRM;

These two just look like unintended formatting changes.

>  		break;
>  	case SND_SOC_DAIFMT_CBM_CFM:
>  		/* codec is master */
> @@ -372,6 +391,17 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
>  	return 0;
>  }
>  
> +static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
> +				int div_id, int div)
> +{
> +	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
> +	int srgr;
> +
> +	mcbsp_data.clk_div = div;
> +	return 0;
> +}
> +
> +
>  static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
>  				 struct snd_pcm_hw_params *params,
>  				 struct snd_soc_dai *dai)
> @@ -380,11 +410,12 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
>  	struct davinci_pcm_dma_params *dma_params =
>  					&dev->dma_params[substream->stream];
>  	struct snd_interval *i = NULL;
> -	int mcbsp_word_length;
> -	unsigned int rcr, xcr, srgr;
> +	int mcbsp_word_length, master;
> +	unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
>  	u32 spcr;
>  	snd_pcm_format_t fmt;
>  	unsigned element_cnt = 1;
> +	struct clk *clk;
>  
>  	/* general line settings */
>  	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
> @@ -396,12 +427,60 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
>  		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
>  	}
>  
> -	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
> -	srgr = DAVINCI_MCBSP_SRGR_FSGM;
> -	srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
> +	master = mcbsp_data.fmt & SND_SOC_DAIFMT_MASTER_MASK;
> +	fmt = params_format(params);
> +	mcbsp_word_length = asp_word_length[fmt];
>  
> -	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
> -	srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
> +	if (master == SND_SOC_DAIFMT_CBS_CFS) {
> +		clk = clk_get(NULL, "pll1_sysclk6");
> +		if (clk)
> +			freq = clk_get_rate(clk);
> +		freq = 122000000; /* FIXME ask to Texas */

This frequency should either be passed in as platform data or by your
machine driver calling snd_soc_dai_set_sysclk(). 

> +		if (dev->i2s_fast_clock) {
> +			clk_div = 256;
> +			do {
> +				framesize = (freq / (--clk_div)) /
> +					    params->rate_num *
> +					    params->rate_den;
> +			} while (((framesize < 33) || (framesize > 4095)) &&
> +				 (clk_div));
> +			clk_div--;
> +			srgr = DAVINCI_MCBSP_SRGR_FSGM |
> +			       DAVINCI_MCBSP_SRGR_CLKSM;
> +			srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
> +							8 - 1);
> +			srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
> +		} else {
> +			/* simmetric waveforms */

symmetric

> +			srgr = DAVINCI_MCBSP_SRGR_FSGM |
> +			       DAVINCI_MCBSP_SRGR_CLKSM;
> +			srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
> +							8 - 1);
> +			srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
> +							16 - 1);
> +			clk_div = freq / (mcbsp_word_length * 16) /
> +				  params->rate_num * params->rate_den;
> +		}
> +		clk_div &= 0xFF;
> +		srgr |= clk_div;
> +	} else if (master == SND_SOC_DAIFMT_CBS_CFM) {
> +		/* Clock given on CLKS */
> +		srgr = DAVINCI_MCBSP_SRGR_FSGM;
> +		clk_div = mcbsp_data.clk_div - 1;
> +		srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
> +		srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
> +		clk_div &= 0xFF;
> +		srgr |= clk_div;
> +	} else {
> +		i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
> +		srgr = DAVINCI_MCBSP_SRGR_FSGM;
> +		srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
> +		pr_debug("%s - %d  FWID set: re-read srgr = %X\n",
> +			__func__, __LINE__, snd_interval_value(i) - 1);
> +
> +		i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
> +		srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
> +	}
>  	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
>  
>  	rcr = DAVINCI_MCBSP_RCR_RFIG;
> @@ -426,22 +505,45 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
>  			element_cnt = 1;
>  			fmt = double_fmt[fmt];
>  		}
> +		if (master == SND_SOC_DAIFMT_CBS_CFS ||
> +				master == SND_SOC_DAIFMT_CBS_CFM) {
> +			rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
> +			xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
> +			rcr |= DAVINCI_MCBSP_RCR_RPHASE;
> +			xcr |= DAVINCI_MCBSP_XCR_XPHASE;
> +		} else {
> +			/* FIXME ask to Texas */
> +			rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
> +			xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
> +		}
>  	}
>  	dma_params->acnt = dma_params->data_type = data_type[fmt];
>  	dma_params->fifo_level = 0;
>  	mcbsp_word_length = asp_word_length[fmt];
> -	rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
> -	xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
> +
> +	if (master == SND_SOC_DAIFMT_CBS_CFS ||
> +			master == SND_SOC_DAIFMT_CBS_CFM) {
> +		rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
> +		xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
> +	} else {
> +		/* FIXME ask to Texas */
> +		rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
> +		xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
> +	}
>  
>  	rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
> -		DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
> +	       DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);

more unintended formatting ?

>  	xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
> -		DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
> +	       DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);

ditto

>  
>  	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
>  		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
>  	else
>  		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
> +
> +	pr_debug("%s - %d  srgr=%X\n", __func__, __LINE__, srgr);
> +	pr_debug("%s - %d  xcr=%X\n", __func__, __LINE__, xcr);
> +	pr_debug("%s - %d  rcr=%X\n", __func__, __LINE__, rcr);
>  	return 0;
>  }
>  
> @@ -500,7 +602,7 @@ static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
>  	.trigger	= davinci_i2s_trigger,
>  	.hw_params	= davinci_i2s_hw_params,
>  	.set_fmt	= davinci_i2s_set_dai_fmt,
> -
> +	.set_clkdiv = davinci_i2s_dai_set_clkdiv,

the formatting is different to rest of struct here.

>  };
>  
>  struct snd_soc_dai davinci_i2s_dai = {
> @@ -548,6 +650,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
>  	}
>  	if (pdata) {
>  		dev->enable_channel_combine = pdata->enable_channel_combine;
> +		dev->i2s_fast_clock = pdata->i2s_fast_clock;
>  		dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size =
>  			pdata->sram_size_playback;
>  		dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =

The subject of the patch looks wrong as I can't really see where you are
adding stereo support to  the DAI. This patch looks likes it adds more
clocking options only,

Thanks

Liam
-- 
Freelance Developer, SlimLogic Ltd
ASoC and Voltage Regulator Maintainer.
http://www.slimlogic.co.uk



From fabioestevam at yahoo.com  Wed Jun 23 16:52:31 2010
From: fabioestevam at yahoo.com (Fabio Estevam)
Date: Wed, 23 Jun 2010 13:52:31 -0700 (PDT)
Subject: [PATCH] mx31_3ds: Allow selection between host/device modes on the
	OTG port
Message-ID: <343567.80487.qm@web51007.mail.re2.yahoo.com>

Allow selection between host/device modes on the OTG port.

Selection is made via kernel command line option:

'otg_mode=host' or 'otg_mode=device'. Default mode is device.

Signed-off-by: Fabio Estevam <fabio.estevam at freescale.com>
---
 arch/arm/mach-mx3/mach-mx31_3ds.c |   38 ++++++++++++++++++++++++++++++++++++-
 1 files changed, 37 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 7e8d09a..82ba957 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -29,6 +29,8 @@
 #include <linux/regulator/machine.h>
 #include <linux/fsl_devices.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
 
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -42,6 +44,8 @@
 #include <mach/iomux-mx3.h>
 #include <mach/mxc_nand.h>
 #include <mach/spi.h>
+#include <mach/mxc_ehci.h>
+#include <mach/ulpi.h>
 #include "devices.h"
 
 /*!
@@ -220,6 +224,14 @@ usbotg_free_reset:
 	return err;
 }
 
+#if defined(CONFIG_USB_ULPI)
+static struct mxc_usbh_platform_data otg_pdata = {
+	.portsc	= MXC_EHCI_MODE_ULPI,
+	.flags	= MXC_EHCI_INTERFACE_DIFF_UNI,
+};
+
+#endif
+
 static struct fsl_usb2_platform_data usbotg_pdata = {
 	.operating_mode = FSL_USB2_DR_DEVICE,
 	.phy_mode	= FSL_USB2_PHY_ULPI,
@@ -399,6 +411,20 @@ static void __init mx31_3ds_map_io(void)
 	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
 }
 
+static int otg_mode_host;
+
+static int __init mx31_3ds_otg_mode(char *options)
+{
+	if (!strcmp(options, "host"))
+		otg_mode_host = 1;
+	else if (!strcmp(options, "device"))
+		otg_mode_host = 0;
+	else
+		pr_info("otg_mode neither \"host\" nor \"device\". "
+			"Defaulting to device\n");
+	return 0;
+}
+__setup("otg_mode=", mx31_3ds_otg_mode);
 /*!
  * Board specific initialization.
  */
@@ -417,7 +443,17 @@ static void __init mxc_board_init(void)
 	mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data);
 
 	mx31_3ds_usbotg_init();
-	mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
+
+#if defined(CONFIG_USB_ULPI)
+	if (otg_mode_host) {
+		otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+		mxc_register_device(&mxc_otg_host, &otg_pdata);
+	}
+#endif
+	if (!otg_mode_host)
+		mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
 
 	if (!mx31_3ds_init_expio())
 		platform_device_register(&smsc911x_device);
-- 
1.6.0.4




      


From gbean at codeaurora.org  Wed Jun 23 17:30:33 2010
From: gbean at codeaurora.org (Gregory Bean)
Date: Wed, 23 Jun 2010 14:30:33 -0700
Subject: [PATCH 0/3 v3] msm: Add gpiolib devices to MSM7x30 and QSD8x50.
Message-ID: <1277328636-27421-1-git-send-email-gbean@codeaurora.org>

Hi folks:

Here is a proposed patch series which adds the configuration and devices
needed to enable gpiolib on the MSM7x30 and QSD8x50 chipsets.

Thanks,

G

Gregory Bean (3):
  msm: Add gpio register address mapping information.
  msm: 7x30: Add gpio device configuration.
  msm: 8x50: add gpio device configuration.

 arch/arm/mach-msm/board-msm7x30.c     |   27 ++++++++-
 arch/arm/mach-msm/board-qsd8x50.c     |   27 ++++++++-
 arch/arm/mach-msm/devices-msm7x30.c   |   21 +++++++
 arch/arm/mach-msm/devices-qsd8x50.c   |   21 +++++++
 arch/arm/mach-msm/devices.h           |   33 +++++++++++
 arch/arm/mach-msm/gpio_hw-7x30.h      |  100 +++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio_hw-7xxx.h      |   84 +++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio_hw-8x50.h      |  100 +++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio_hw.h           |   35 +++++++++++
 arch/arm/mach-msm/include/mach/gpio.h |    2 +
 10 files changed, 446 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm/mach-msm/gpio_hw-7x30.h
 create mode 100644 arch/arm/mach-msm/gpio_hw-7xxx.h
 create mode 100644 arch/arm/mach-msm/gpio_hw-8x50.h
 create mode 100644 arch/arm/mach-msm/gpio_hw.h

--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From gbean at codeaurora.org  Wed Jun 23 17:30:34 2010
From: gbean at codeaurora.org (Gregory Bean)
Date: Wed, 23 Jun 2010 14:30:34 -0700
Subject: [PATCH 1/3 v3] msm: Add gpio register address mapping information.
In-Reply-To: <1277328636-27421-1-git-send-email-gbean@codeaurora.org>
References: <1277328636-27421-1-git-send-email-gbean@codeaurora.org>
Message-ID: <1277328636-27421-2-git-send-email-gbean@codeaurora.org>

Add tables containing iomap information for gpio registers
on all supported MSM7x and QSD8x targets.

Signed-off-by: Gregory Bean <gbean at codeaurora.org>
---
 arch/arm/mach-msm/gpio_hw-7x30.h |  100 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio_hw-7xxx.h |   84 ++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio_hw-8x50.h |  100 ++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/gpio_hw.h      |   35 +++++++++++++
 4 files changed, 319 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-msm/gpio_hw-7x30.h
 create mode 100644 arch/arm/mach-msm/gpio_hw-7xxx.h
 create mode 100644 arch/arm/mach-msm/gpio_hw-8x50.h
 create mode 100644 arch/arm/mach-msm/gpio_hw.h

diff --git a/arch/arm/mach-msm/gpio_hw-7x30.h b/arch/arm/mach-msm/gpio_hw-7x30.h
new file mode 100644
index 0000000..8c28a3f
--- /dev/null
+++ b/arch/arm/mach-msm/gpio_hw-7x30.h
@@ -0,0 +1,100 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_7X30_H
+#define __ARCH_ARM_MACH_MSM_GPIO_HW_7X30_H
+
+/* output value */
+#define GPIO_OUT_0         GPIO1_REG(0x00)   /* gpio  15-0   */
+#define GPIO_OUT_1         GPIO2_REG(0x00)   /* gpio  43-16  */
+#define GPIO_OUT_2         GPIO1_REG(0x04)   /* gpio  67-44  */
+#define GPIO_OUT_3         GPIO1_REG(0x08)   /* gpio  94-68  */
+#define GPIO_OUT_4         GPIO1_REG(0x0C)   /* gpio 106-95  */
+#define GPIO_OUT_5         GPIO1_REG(0x50)   /* gpio 133-107 */
+#define GPIO_OUT_6         GPIO1_REG(0xC4)   /* gpio 150-134 */
+#define GPIO_OUT_7         GPIO1_REG(0x214)  /* gpio 181-151 */
+
+/* same pin map as above, output enable */
+#define GPIO_OE_0          GPIO1_REG(0x10)
+#define GPIO_OE_1          GPIO2_REG(0x08)
+#define GPIO_OE_2          GPIO1_REG(0x14)
+#define GPIO_OE_3          GPIO1_REG(0x18)
+#define GPIO_OE_4          GPIO1_REG(0x1C)
+#define GPIO_OE_5          GPIO1_REG(0x54)
+#define GPIO_OE_6          GPIO1_REG(0xC8)
+#define GPIO_OE_7          GPIO1_REG(0x218)
+
+/* same pin map as above, input read */
+#define GPIO_IN_0          GPIO1_REG(0x34)
+#define GPIO_IN_1          GPIO2_REG(0x20)
+#define GPIO_IN_2          GPIO1_REG(0x38)
+#define GPIO_IN_3          GPIO1_REG(0x3C)
+#define GPIO_IN_4          GPIO1_REG(0x40)
+#define GPIO_IN_5          GPIO1_REG(0x44)
+#define GPIO_IN_6          GPIO1_REG(0xCC)
+#define GPIO_IN_7          GPIO1_REG(0x21C)
+
+/* same pin map as above, 1=edge 0=level interrupt */
+#define GPIO_INT_EDGE_0    GPIO1_REG(0x60)
+#define GPIO_INT_EDGE_1    GPIO2_REG(0x50)
+#define GPIO_INT_EDGE_2    GPIO1_REG(0x64)
+#define GPIO_INT_EDGE_3    GPIO1_REG(0x68)
+#define GPIO_INT_EDGE_4    GPIO1_REG(0x6C)
+#define GPIO_INT_EDGE_5    GPIO1_REG(0xC0)
+#define GPIO_INT_EDGE_6    GPIO1_REG(0xD0)
+#define GPIO_INT_EDGE_7    GPIO1_REG(0x240)
+
+/* same pin map as above, 1=positive 0=negative */
+#define GPIO_INT_POS_0     GPIO1_REG(0x70)
+#define GPIO_INT_POS_1     GPIO2_REG(0x58)
+#define GPIO_INT_POS_2     GPIO1_REG(0x74)
+#define GPIO_INT_POS_3     GPIO1_REG(0x78)
+#define GPIO_INT_POS_4     GPIO1_REG(0x7C)
+#define GPIO_INT_POS_5     GPIO1_REG(0xBC)
+#define GPIO_INT_POS_6     GPIO1_REG(0xD4)
+#define GPIO_INT_POS_7     GPIO1_REG(0x228)
+
+/* same pin map as above, interrupt enable */
+#define GPIO_INT_EN_0      GPIO1_REG(0x80)
+#define GPIO_INT_EN_1      GPIO2_REG(0x60)
+#define GPIO_INT_EN_2      GPIO1_REG(0x84)
+#define GPIO_INT_EN_3      GPIO1_REG(0x88)
+#define GPIO_INT_EN_4      GPIO1_REG(0x8C)
+#define GPIO_INT_EN_5      GPIO1_REG(0xB8)
+#define GPIO_INT_EN_6      GPIO1_REG(0xD8)
+#define GPIO_INT_EN_7      GPIO1_REG(0x22C)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define GPIO_INT_CLEAR_0   GPIO1_REG(0x90)
+#define GPIO_INT_CLEAR_1   GPIO2_REG(0x68)
+#define GPIO_INT_CLEAR_2   GPIO1_REG(0x94)
+#define GPIO_INT_CLEAR_3   GPIO1_REG(0x98)
+#define GPIO_INT_CLEAR_4   GPIO1_REG(0x9C)
+#define GPIO_INT_CLEAR_5   GPIO1_REG(0xB4)
+#define GPIO_INT_CLEAR_6   GPIO1_REG(0xDC)
+#define GPIO_INT_CLEAR_7   GPIO1_REG(0x230)
+
+/* same pin map as above, 1=interrupt pending */
+#define GPIO_INT_STATUS_0  GPIO1_REG(0xA0)
+#define GPIO_INT_STATUS_1  GPIO2_REG(0x70)
+#define GPIO_INT_STATUS_2  GPIO1_REG(0xA4)
+#define GPIO_INT_STATUS_3  GPIO1_REG(0xA8)
+#define GPIO_INT_STATUS_4  GPIO1_REG(0xAC)
+#define GPIO_INT_STATUS_5  GPIO1_REG(0xB0)
+#define GPIO_INT_STATUS_6  GPIO1_REG(0xE0)
+#define GPIO_INT_STATUS_7  GPIO1_REG(0x234)
+
+#endif
diff --git a/arch/arm/mach-msm/gpio_hw-7xxx.h b/arch/arm/mach-msm/gpio_hw-7xxx.h
new file mode 100644
index 0000000..3408478
--- /dev/null
+++ b/arch/arm/mach-msm/gpio_hw-7xxx.h
@@ -0,0 +1,84 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_7XXX_H
+#define __ARCH_ARM_MACH_MSM_GPIO_HW_7XXX_H
+
+/* output value */
+#define GPIO_OUT_0         GPIO1_REG(0x00)  /* gpio  15-0  */
+#define GPIO_OUT_1         GPIO2_REG(0x00)  /* gpio  42-16 */
+#define GPIO_OUT_2         GPIO1_REG(0x04)  /* gpio  67-43 */
+#define GPIO_OUT_3         GPIO1_REG(0x08)  /* gpio  94-68 */
+#define GPIO_OUT_4         GPIO1_REG(0x0C)  /* gpio 106-95 */
+#define GPIO_OUT_5         GPIO1_REG(0x50)  /* gpio 107-121 */
+
+/* same pin map as above, output enable */
+#define GPIO_OE_0          GPIO1_REG(0x10)
+#define GPIO_OE_1          GPIO2_REG(0x08)
+#define GPIO_OE_2          GPIO1_REG(0x14)
+#define GPIO_OE_3          GPIO1_REG(0x18)
+#define GPIO_OE_4          GPIO1_REG(0x1C)
+#define GPIO_OE_5          GPIO1_REG(0x54)
+
+/* same pin map as above, input read */
+#define GPIO_IN_0          GPIO1_REG(0x34)
+#define GPIO_IN_1          GPIO2_REG(0x20)
+#define GPIO_IN_2          GPIO1_REG(0x38)
+#define GPIO_IN_3          GPIO1_REG(0x3C)
+#define GPIO_IN_4          GPIO1_REG(0x40)
+#define GPIO_IN_5          GPIO1_REG(0x44)
+
+/* same pin map as above, 1=edge 0=level interrupt */
+#define GPIO_INT_EDGE_0    GPIO1_REG(0x60)
+#define GPIO_INT_EDGE_1    GPIO2_REG(0x50)
+#define GPIO_INT_EDGE_2    GPIO1_REG(0x64)
+#define GPIO_INT_EDGE_3    GPIO1_REG(0x68)
+#define GPIO_INT_EDGE_4    GPIO1_REG(0x6C)
+#define GPIO_INT_EDGE_5    GPIO1_REG(0xC0)
+
+/* same pin map as above, 1=positive 0=negative */
+#define GPIO_INT_POS_0     GPIO1_REG(0x70)
+#define GPIO_INT_POS_1     GPIO2_REG(0x58)
+#define GPIO_INT_POS_2     GPIO1_REG(0x74)
+#define GPIO_INT_POS_3     GPIO1_REG(0x78)
+#define GPIO_INT_POS_4     GPIO1_REG(0x7C)
+#define GPIO_INT_POS_5     GPIO1_REG(0xBC)
+
+/* same pin map as above, interrupt enable */
+#define GPIO_INT_EN_0      GPIO1_REG(0x80)
+#define GPIO_INT_EN_1      GPIO2_REG(0x60)
+#define GPIO_INT_EN_2      GPIO1_REG(0x84)
+#define GPIO_INT_EN_3      GPIO1_REG(0x88)
+#define GPIO_INT_EN_4      GPIO1_REG(0x8C)
+#define GPIO_INT_EN_5      GPIO1_REG(0xB8)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define GPIO_INT_CLEAR_0   GPIO1_REG(0x90)
+#define GPIO_INT_CLEAR_1   GPIO2_REG(0x68)
+#define GPIO_INT_CLEAR_2   GPIO1_REG(0x94)
+#define GPIO_INT_CLEAR_3   GPIO1_REG(0x98)
+#define GPIO_INT_CLEAR_4   GPIO1_REG(0x9C)
+#define GPIO_INT_CLEAR_5   GPIO1_REG(0xB4)
+
+/* same pin map as above, 1=interrupt pending */
+#define GPIO_INT_STATUS_0  GPIO1_REG(0xA0)
+#define GPIO_INT_STATUS_1  GPIO2_REG(0x70)
+#define GPIO_INT_STATUS_2  GPIO1_REG(0xA4)
+#define GPIO_INT_STATUS_3  GPIO1_REG(0xA8)
+#define GPIO_INT_STATUS_4  GPIO1_REG(0xAC)
+#define GPIO_INT_STATUS_5  GPIO1_REG(0xB0)
+
+#endif
diff --git a/arch/arm/mach-msm/gpio_hw-8x50.h b/arch/arm/mach-msm/gpio_hw-8x50.h
new file mode 100644
index 0000000..9431943
--- /dev/null
+++ b/arch/arm/mach-msm/gpio_hw-8x50.h
@@ -0,0 +1,100 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_8X50_H
+#define __ARCH_ARM_MACH_MSM_GPIO_HW_8X50_H
+
+/* output value */
+#define GPIO_OUT_0         GPIO1_REG(0x00)  /* gpio  15-0   */
+#define GPIO_OUT_1         GPIO2_REG(0x00)  /* gpio  42-16  */
+#define GPIO_OUT_2         GPIO1_REG(0x04)  /* gpio  67-43  */
+#define GPIO_OUT_3         GPIO1_REG(0x08)  /* gpio  94-68  */
+#define GPIO_OUT_4         GPIO1_REG(0x0C)  /* gpio 103-95  */
+#define GPIO_OUT_5         GPIO1_REG(0x10)  /* gpio 121-104 */
+#define GPIO_OUT_6         GPIO1_REG(0x14)  /* gpio 152-122 */
+#define GPIO_OUT_7         GPIO1_REG(0x18)  /* gpio 164-153 */
+
+/* same pin map as above, output enable */
+#define GPIO_OE_0          GPIO1_REG(0x20)
+#define GPIO_OE_1          GPIO2_REG(0x08)
+#define GPIO_OE_2          GPIO1_REG(0x24)
+#define GPIO_OE_3          GPIO1_REG(0x28)
+#define GPIO_OE_4          GPIO1_REG(0x2C)
+#define GPIO_OE_5          GPIO1_REG(0x30)
+#define GPIO_OE_6          GPIO1_REG(0x34)
+#define GPIO_OE_7          GPIO1_REG(0x38)
+
+/* same pin map as above, input read */
+#define GPIO_IN_0          GPIO1_REG(0x50)
+#define GPIO_IN_1          GPIO2_REG(0x20)
+#define GPIO_IN_2          GPIO1_REG(0x54)
+#define GPIO_IN_3          GPIO1_REG(0x58)
+#define GPIO_IN_4          GPIO1_REG(0x5C)
+#define GPIO_IN_5          GPIO1_REG(0x60)
+#define GPIO_IN_6          GPIO1_REG(0x64)
+#define GPIO_IN_7          GPIO1_REG(0x68)
+
+/* same pin map as above, 1=edge 0=level interrupt */
+#define GPIO_INT_EDGE_0    GPIO1_REG(0x70)
+#define GPIO_INT_EDGE_1    GPIO2_REG(0x50)
+#define GPIO_INT_EDGE_2    GPIO1_REG(0x74)
+#define GPIO_INT_EDGE_3    GPIO1_REG(0x78)
+#define GPIO_INT_EDGE_4    GPIO1_REG(0x7C)
+#define GPIO_INT_EDGE_5    GPIO1_REG(0x80)
+#define GPIO_INT_EDGE_6    GPIO1_REG(0x84)
+#define GPIO_INT_EDGE_7    GPIO1_REG(0x88)
+
+/* same pin map as above, 1=positive 0=negative */
+#define GPIO_INT_POS_0     GPIO1_REG(0x90)
+#define GPIO_INT_POS_1     GPIO2_REG(0x58)
+#define GPIO_INT_POS_2     GPIO1_REG(0x94)
+#define GPIO_INT_POS_3     GPIO1_REG(0x98)
+#define GPIO_INT_POS_4     GPIO1_REG(0x9C)
+#define GPIO_INT_POS_5     GPIO1_REG(0xA0)
+#define GPIO_INT_POS_6     GPIO1_REG(0xA4)
+#define GPIO_INT_POS_7     GPIO1_REG(0xA8)
+
+/* same pin map as above, interrupt enable */
+#define GPIO_INT_EN_0      GPIO1_REG(0xB0)
+#define GPIO_INT_EN_1      GPIO2_REG(0x60)
+#define GPIO_INT_EN_2      GPIO1_REG(0xB4)
+#define GPIO_INT_EN_3      GPIO1_REG(0xB8)
+#define GPIO_INT_EN_4      GPIO1_REG(0xBC)
+#define GPIO_INT_EN_5      GPIO1_REG(0xC0)
+#define GPIO_INT_EN_6      GPIO1_REG(0xC4)
+#define GPIO_INT_EN_7      GPIO1_REG(0xC8)
+
+/* same pin map as above, write 1 to clear interrupt */
+#define GPIO_INT_CLEAR_0   GPIO1_REG(0xD0)
+#define GPIO_INT_CLEAR_1   GPIO2_REG(0x68)
+#define GPIO_INT_CLEAR_2   GPIO1_REG(0xD4)
+#define GPIO_INT_CLEAR_3   GPIO1_REG(0xD8)
+#define GPIO_INT_CLEAR_4   GPIO1_REG(0xDC)
+#define GPIO_INT_CLEAR_5   GPIO1_REG(0xE0)
+#define GPIO_INT_CLEAR_6   GPIO1_REG(0xE4)
+#define GPIO_INT_CLEAR_7   GPIO1_REG(0xE8)
+
+/* same pin map as above, 1=interrupt pending */
+#define GPIO_INT_STATUS_0  GPIO1_REG(0xF0)
+#define GPIO_INT_STATUS_1  GPIO2_REG(0x70)
+#define GPIO_INT_STATUS_2  GPIO1_REG(0xF4)
+#define GPIO_INT_STATUS_3  GPIO1_REG(0xF8)
+#define GPIO_INT_STATUS_4  GPIO1_REG(0xFC)
+#define GPIO_INT_STATUS_5  GPIO1_REG(0x100)
+#define GPIO_INT_STATUS_6  GPIO1_REG(0x104)
+#define GPIO_INT_STATUS_7  GPIO1_REG(0x108)
+
+#endif
diff --git a/arch/arm/mach-msm/gpio_hw.h b/arch/arm/mach-msm/gpio_hw.h
new file mode 100644
index 0000000..627dea5
--- /dev/null
+++ b/arch/arm/mach-msm/gpio_hw.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2007, Google, Inc.
+ * Copyright (c) 2008-2010, Code Aurora Forum. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef __ARCH_ARM_MACH_MSM_GPIO_HW_H
+#define __ARCH_ARM_MACH_MSM_GPIO_HW_H
+
+#include <mach/msm_iomap.h>
+
+#if defined(CONFIG_ARCH_MSM7X30)
+#define GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
+#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
+#else
+#define GPIO1_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
+#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
+#endif
+
+#if defined(CONFIG_ARCH_QSD8X50)
+#include "gpio_hw-8x50.h"
+#elif defined(CONFIG_ARCH_MSM7X30)
+#include "gpio_hw-7x30.h"
+#else
+#include "gpio_hw-7xxx.h"
+#endif
+
+#endif
-- 
1.7.0.4

--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From gbean at codeaurora.org  Wed Jun 23 17:30:35 2010
From: gbean at codeaurora.org (Gregory Bean)
Date: Wed, 23 Jun 2010 14:30:35 -0700
Subject: [PATCH 2/3 v3] msm: 7x30: Add gpio device configuration.
In-Reply-To: <1277328636-27421-1-git-send-email-gbean@codeaurora.org>
References: <1277328636-27421-1-git-send-email-gbean@codeaurora.org>
Message-ID: <1277328636-27421-3-git-send-email-gbean@codeaurora.org>

Add device configuration and board-init for gpio on the MSM7x30.

Signed-off-by: Gregory Bean <gbean at codeaurora.org>
---
 arch/arm/mach-msm/board-msm7x30.c     |   27 +++++++++++++++++++++++++--
 arch/arm/mach-msm/devices-msm7x30.c   |   21 +++++++++++++++++++++
 arch/arm/mach-msm/devices.h           |   33 +++++++++++++++++++++++++++++++++
 arch/arm/mach-msm/include/mach/gpio.h |    2 ++
 4 files changed, 81 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index edd5983..2db85d5 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -55,7 +55,29 @@ static void msm7x30_init_uart2(void)
 }
 #endif
 
-static struct platform_device *devices[] __initdata = {
+/*
+ * Early devices are those which provide a system service which will be
+ * required by one or more of the function calls in msm7x30_init.
+ * These devices must be probed and online first in order for
+ * the init routine to run successfully.
+ */
+static struct platform_device *early_devices[] __initdata = {
+	&msm_gpio_devices[0],
+	&msm_gpio_devices[1],
+	&msm_gpio_devices[2],
+	&msm_gpio_devices[3],
+	&msm_gpio_devices[4],
+	&msm_gpio_devices[5],
+	&msm_gpio_devices[6],
+	&msm_gpio_devices[7],
+};
+
+/*
+ * Late devices are those which are dependent upon services initialized
+ * by msm7x30_init, or which simply have no dependents and can have
+ * their initialization deferred.
+ */
+static struct platform_device *late_devices[] __initdata = {
 #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
         &msm_device_uart2,
 #endif
@@ -69,10 +91,11 @@ static void __init msm7x30_init_irq(void)
 
 static void __init msm7x30_init(void)
 {
+	platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
 #ifdef CONFIG_SERIAL_MSM_CONSOLE
 	msm7x30_init_uart2();
 #endif
-	platform_add_devices(devices, ARRAY_SIZE(devices));
+	platform_add_devices(late_devices, ARRAY_SIZE(late_devices));
 }
 
 static void __init msm7x30_map_io(void)
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index b449e8a..ef3185e 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -126,3 +126,24 @@ struct clk msm_clocks_7x30[] = {
 
 unsigned msm_num_clocks_7x30 = ARRAY_SIZE(msm_clocks_7x30);
 
+static struct msm7200a_gpio_platform_data gpio_platform_data[] = {
+	MSM7200A_GPIO_PLATFORM_DATA(0,   0,  15, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(1,  16,  43, INT_GPIO_GROUP2),
+	MSM7200A_GPIO_PLATFORM_DATA(2,  44,  67, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(3,  68,  94, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(4,  95, 106, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(5, 107, 133, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(6, 134, 150, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(7, 151, 181, INT_GPIO_GROUP1),
+};
+
+struct platform_device msm_gpio_devices[] = {
+	MSM7200A_GPIO_DEVICE(0, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(1, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(2, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(3, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(4, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(5, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(6, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(7, gpio_platform_data),
+};
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 568443e..fd71edc 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -17,6 +17,8 @@
 #define __ARCH_ARM_MACH_MSM_DEVICES_H
 
 #include "clock.h"
+#include "gpio_hw.h"
+#include "msm7200a-gpio.h"
 
 extern struct platform_device msm_device_uart1;
 extern struct platform_device msm_device_uart2;
@@ -44,4 +46,35 @@ extern unsigned msm_num_clocks_7x30;
 extern struct clk msm_clocks_8x50[];
 extern unsigned msm_num_clocks_8x50;
 
+#define MSM7200A_GPIO_PLATFORM_DATA(ix, begin, end, irq)		\
+	[ix] = {							\
+		.gpio_base		= begin,			\
+		.ngpio			= end - begin + 1,		\
+		.irq_base		= MSM_GPIO_TO_INT(begin),	\
+		.irq_summary		= irq,				\
+		.latch_level_irqs	= false,			\
+		.regs = {						\
+			.in		= GPIO_IN_ ## ix,		\
+			.out		= GPIO_OUT_ ## ix,		\
+			.oe		= GPIO_OE_ ## ix,		\
+			.int_status	= GPIO_INT_STATUS_ ## ix,	\
+			.int_clear	= GPIO_INT_CLEAR_ ## ix,	\
+			.int_en		= GPIO_INT_EN_ ## ix,		\
+			.int_edge	= GPIO_INT_EDGE_ ## ix,		\
+			.int_pos	= GPIO_INT_POS_ ## ix,		\
+		},							\
+	}
+
+#define MSM7200A_GPIO_DEVICE(ix, pdata)			\
+	{						\
+		.name		= "msm7200a-gpio",	\
+		.id		= ix,			\
+		.num_resources	= 0,			\
+		.dev = {				\
+			.platform_data = &pdata[ix],	\
+		},					\
+	}
+
+extern struct platform_device msm_gpio_devices[];
+
 #endif
diff --git a/arch/arm/mach-msm/include/mach/gpio.h b/arch/arm/mach-msm/include/mach/gpio.h
index 83e47c0..ff80758 100644
--- a/arch/arm/mach-msm/include/mach/gpio.h
+++ b/arch/arm/mach-msm/include/mach/gpio.h
@@ -16,6 +16,8 @@
 #ifndef __ASM_ARCH_MSM_GPIO_H
 #define __ASM_ARCH_MSM_GPIO_H
 
+#define ARCH_NR_GPIOS 512
+
 #include <asm-generic/gpio.h>
 
 #define gpio_get_value  __gpio_get_value
-- 
1.7.0.4

--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From gbean at codeaurora.org  Wed Jun 23 17:30:36 2010
From: gbean at codeaurora.org (Gregory Bean)
Date: Wed, 23 Jun 2010 14:30:36 -0700
Subject: [PATCH 3/3 v3] msm: 8x50: add gpio device configuration.
In-Reply-To: <1277328636-27421-1-git-send-email-gbean@codeaurora.org>
References: <1277328636-27421-1-git-send-email-gbean@codeaurora.org>
Message-ID: <1277328636-27421-4-git-send-email-gbean@codeaurora.org>

Add device configuration and board-init for gpio support on the QSD8x50.

Signed-off-by: Gregory Bean <gbean at codeaurora.org>
---
 arch/arm/mach-msm/board-qsd8x50.c   |   27 +++++++++++++++++++++++++--
 arch/arm/mach-msm/devices-qsd8x50.c |   21 +++++++++++++++++++++
 2 files changed, 46 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index e3cc807..508333c 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -40,7 +40,29 @@ static struct msm_gpio uart3_config_data[] = {
 	{ GPIO_CFG(87, 1, GPIO_OUTPUT,  GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"},
 };
 
-static struct platform_device *devices[] __initdata = {
+/*
+ * Early devices are those which provide a system service which will be
+ * required by one or more of the function calls in qsd8x50_init.
+ * These devices must be probed and online first in order for
+ * the init routine to run successfully.
+ */
+static struct platform_device *early_devices[] __initdata = {
+	&msm_gpio_devices[0],
+	&msm_gpio_devices[1],
+	&msm_gpio_devices[2],
+	&msm_gpio_devices[3],
+	&msm_gpio_devices[4],
+	&msm_gpio_devices[5],
+	&msm_gpio_devices[6],
+	&msm_gpio_devices[7],
+};
+
+/*
+ * Late devices are those which are dependent upon services initialized
+ * by qsd8x50_init, or which simply have no dependents and can have
+ * their initialization deferred.
+ */
+static struct platform_device *late_devices[] __initdata = {
 	&msm_device_uart3,
 };
 
@@ -64,8 +86,9 @@ static void __init qsd8x50_init_irq(void)
 
 static void __init qsd8x50_init(void)
 {
+	platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
 	msm8x50_init_uart3();
-	platform_add_devices(devices, ARRAY_SIZE(devices));
+	platform_add_devices(late_devices, ARRAY_SIZE(late_devices));
 }
 
 MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 4d4a507..2342654 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -90,3 +90,24 @@ struct clk msm_clocks_8x50[] = {
 
 unsigned msm_num_clocks_8x50 = ARRAY_SIZE(msm_clocks_8x50);
 
+static struct msm7200a_gpio_platform_data gpio_platform_data[] = {
+	MSM7200A_GPIO_PLATFORM_DATA(0,   0,  15, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(1,  16,  42, INT_GPIO_GROUP2),
+	MSM7200A_GPIO_PLATFORM_DATA(2,  43,  67, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(3,  68,  94, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(4,  95, 103, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(5, 104, 121, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(6, 122, 152, INT_GPIO_GROUP1),
+	MSM7200A_GPIO_PLATFORM_DATA(7, 153, 164, INT_GPIO_GROUP1),
+};
+
+struct platform_device msm_gpio_devices[] = {
+	MSM7200A_GPIO_DEVICE(0, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(1, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(2, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(3, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(4, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(5, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(6, gpio_platform_data),
+	MSM7200A_GPIO_DEVICE(7, gpio_platform_data),
+};
-- 
1.7.0.4

--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.


From dwalker at codeaurora.org  Wed Jun 23 18:22:20 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Wed, 23 Jun 2010 15:22:20 -0700
Subject: [PATCH 0/3 v3] msm: Add gpiolib devices to MSM7x30 and QSD8x50.
In-Reply-To: <1277325516-24111-1-git-send-email-gbean@codeaurora.org>
References: <1277325516-24111-1-git-send-email-gbean@codeaurora.org>
Message-ID: <1277331740.8495.0.camel@c-dwalke-linux.qualcomm.com>

On Wed, 2010-06-23 at 13:38 -0700, Gregory Bean wrote:
> Hi folks:
> 
> Here is a proposed patch series which adds the configuration and devices
> needed to enable gpiolib on the MSM7x30 and QSD8x50 chipsets.

Ok, I applied it to my -next branch.

Daniel

-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From kgene.kim at samsung.com  Wed Jun 23 18:31:54 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 24 Jun 2010 07:31:54 +0900
Subject: [PATCH] ARM: S5P: Add Support common arch_reset() for S5P SoCs
Message-ID: <1277332317-30192-1-git-send-email-kgene.kim@samsung.com>

This patch adds system define for arch_reset() for S5P SoCs
such as S5P6440, S5P6442, S5PC100 and S5PV210/S5PC110.
Now perform reset using Watchdog reset, SWRESET support with
s5p_reset_hook() will be added later.

NOTE: depends on 'Add Watchdog support for S5PC100'

ARM: S5P6442: Add Watchdog Timer map for S5P6442
ARM: S5P: Add System define for arch_reset()
ARM: S5P: Add Support common arch_reset() for S5P SoCs


From kgene.kim at samsung.com  Wed Jun 23 18:31:55 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 24 Jun 2010 07:31:55 +0900
Subject: [PATCH 1/3] ARM: S5P6442: Add Watchdog Timer map for S5P6442
In-Reply-To: <1277332317-30192-1-git-send-email-kgene.kim@samsung.com>
References: <1277332317-30192-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277332317-30192-2-git-send-email-kgene.kim@samsung.com>

From: Jongpill Lee <boyko.lee at samsung.com>

This patch adds definition of Watchdog Timer map.

Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5p6442/include/mach/map.h |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 32ca424..281d256 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -42,6 +42,8 @@
 
 #define S5P6442_PA_SYSTIMER   	(0xEA100000)
 
+#define S5P6442_PA_WATCHDOG	(0xEA200000)
+
 #define S5P6442_PA_UART		(0xEC000000)
 
 #define S5P_PA_UART0		(S5P6442_PA_UART + 0x0)
@@ -65,6 +67,7 @@
 #define S5P6442_PA_PCM1		0xF2500000
 
 /* compatibiltiy defines. */
+#define S3C_PA_WDT		S5P6442_PA_WATCHDOG
 #define S3C_PA_UART		S5P6442_PA_UART
 #define S3C_PA_IIC		S5P6442_PA_IIC0
 
-- 
1.6.2.5



From kgene.kim at samsung.com  Wed Jun 23 18:31:56 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 24 Jun 2010 07:31:56 +0900
Subject: [PATCH 2/3] ARM: S5P: Add System define for arch_reset()
In-Reply-To: <1277332317-30192-1-git-send-email-kgene.kim@samsung.com>
References: <1277332317-30192-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277332317-30192-3-git-send-email-kgene.kim@samsung.com>

From: Jongpill Lee <boyko.lee at samsung.com>

This patch adds system define for arch_reset() using Watchdog reset.
And adds IO mapping for using WDT.

Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/plat-s5p/cpu.c                       |    5 +++++
 arch/arm/plat-s5p/include/plat/system-reset.h |   24 ++++++++++++++++++++++++
 2 files changed, 29 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-s5p/include/plat/system-reset.h

diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 75cb8c3..1ab55e8 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -103,6 +103,11 @@ static struct map_desc s5p_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(S5P_PA_GPIO),
 		.length		= SZ_4K,
 		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S3C_VA_WATCHDOG,
+		.pfn		= __phys_to_pfn(S3C_PA_WDT),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
 	},
 };
 
diff --git a/arch/arm/plat-s5p/include/plat/system-reset.h b/arch/arm/plat-s5p/include/plat/system-reset.h
new file mode 100644
index 0000000..7f76a16
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/system-reset.h
@@ -0,0 +1,24 @@
+/* linux/arch/arm/plat-s5p/include/plat/system-reset.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Based on arch/arm/mach-s3c2410/include/mach/system-reset.h
+ *
+ * S5P - System define for arch_reset()
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <plat/watchdog-reset.h>
+
+static void arch_reset(char mode, const char *cmd)
+{
+	/* Perform reset using Watchdog reset.
+	 * SWRESET support will be added later.
+	 */
+
+	arch_wdt_reset();
+}
-- 
1.6.2.5



From kgene.kim at samsung.com  Wed Jun 23 18:31:57 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 24 Jun 2010 07:31:57 +0900
Subject: [PATCH 3/3] ARM: S5P: Add Support common arch_reset() for S5P SoCs
In-Reply-To: <1277332317-30192-1-git-send-email-kgene.kim@samsung.com>
References: <1277332317-30192-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277332317-30192-4-git-send-email-kgene.kim@samsung.com>

From: Jongpill Lee <boyko.lee at samsung.com>

This patch adds support common arch_reset() for
S5P6440, S5P6442, S5PC100 and S5PV210/S5PC110.
Now perform reset using Watchdog reset, SWRESET
support with s5p_reset_hook() will be added later.

Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5p6440/include/mach/system.h |    7 ++-----
 arch/arm/mach-s5p6442/include/mach/system.h |    7 ++-----
 arch/arm/mach-s5pc100/include/mach/system.h |    9 +--------
 arch/arm/mach-s5pv210/include/mach/system.h |    7 ++-----
 4 files changed, 7 insertions(+), 23 deletions(-)

diff --git a/arch/arm/mach-s5p6440/include/mach/system.h b/arch/arm/mach-s5p6440/include/mach/system.h
index d2dd817..a359ee3 100644
--- a/arch/arm/mach-s5p6440/include/mach/system.h
+++ b/arch/arm/mach-s5p6440/include/mach/system.h
@@ -13,12 +13,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
 
-static void arch_idle(void)
-{
-	/* nothing here yet */
-}
+#include <plat/system-reset.h>
 
-static void arch_reset(char mode, const char *cmd)
+static void arch_idle(void)
 {
 	/* nothing here yet */
 }
diff --git a/arch/arm/mach-s5p6442/include/mach/system.h b/arch/arm/mach-s5p6442/include/mach/system.h
index 8bcd8ed..c30c1cc 100644
--- a/arch/arm/mach-s5p6442/include/mach/system.h
+++ b/arch/arm/mach-s5p6442/include/mach/system.h
@@ -13,12 +13,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
 
-static void arch_idle(void)
-{
-	/* nothing here yet */
-}
+#include <plat/system-reset.h>
 
-static void arch_reset(char mode, const char *cmd)
+static void arch_idle(void)
 {
 	/* nothing here yet */
 }
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
index 681f626..a9ea57c 100644
--- a/arch/arm/mach-s5pc100/include/mach/system.h
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -11,18 +11,11 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
 
-#include <linux/io.h>
-#include <mach/map.h>
-#include <mach/regs-clock.h>
+#include <plat/system-reset.h>
 
 static void arch_idle(void)
 {
 	/* nothing here yet */
 }
 
-static void arch_reset(char mode, const char *cmd)
-{
-	__raw_writel(S5PC100_SWRESET_RESETVAL, S5PC100_SWRESET);
-	return;
-}
 #endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/system.h b/arch/arm/mach-s5pv210/include/mach/system.h
index 1ca04d5..af8a200 100644
--- a/arch/arm/mach-s5pv210/include/mach/system.h
+++ b/arch/arm/mach-s5pv210/include/mach/system.h
@@ -13,12 +13,9 @@
 #ifndef __ASM_ARCH_SYSTEM_H
 #define __ASM_ARCH_SYSTEM_H __FILE__
 
-static void arch_idle(void)
-{
-	/* nothing here yet */
-}
+#include <plat/system-reset.h>
 
-static void arch_reset(char mode, const char *cmd)
+static void arch_idle(void)
 {
 	/* nothing here yet */
 }
-- 
1.6.2.5



From jamie at shareable.org  Wed Jun 23 18:53:45 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Wed, 23 Jun 2010 23:53:45 +0100
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping
	gpios)
In-Reply-To: <4C21955D.1020502@bluewatersys.com>
References: <191168.5104.qm@web180308.mail.gq1.yahoo.com>
	<4C21955D.1020502@bluewatersys.com>
Message-ID: <20100623225345.GD7058@shareable.org>

Ryan Mallon wrote:
> On 06/23/2010 04:37 PM, David Brownell wrote:
> I'm not. Some gpios, such as those on io expanders, may sleep in their
> implementations of the gpio_(set/get) functions.

I'm having a hard time figuring out where some GPIOs I'm using fit
into this picture.

I have some hardware that is currently using a 2.4.26 kernel, but I
look from time to time at forward-porting all the drivers to 2.6.recent.

It has an I2C driven GPIO expander, with a watchdog reset chip hanging
off the expander.

The watchdog is kept alive off the back end of a timer BH, which means
the I2C GPIO routines are written to be safe in BH context (which
isn't sleepable), but they can't be used in IRQ context because the
necessary spin_lock_irqsave() would turn off interrupts for too long
for other subsystems to function properly.

How should I flag those GPIO routines in your scheme?  They're safe to
use in some non-sleeping contexts, but not safe in irq context.

Thanks,
-- Jamie


From ryan at bluewatersys.com  Wed Jun 23 19:06:23 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Thu, 24 Jun 2010 11:06:23 +1200
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping
	gpios)
In-Reply-To: <20100623225345.GD7058@shareable.org>
References: <191168.5104.qm@web180308.mail.gq1.yahoo.com>
	<4C21955D.1020502@bluewatersys.com>
	<20100623225345.GD7058@shareable.org>
Message-ID: <4C22936F.9050300@bluewatersys.com>

On 06/24/2010 10:53 AM, Jamie Lokier wrote:
> Ryan Mallon wrote:
>> On 06/23/2010 04:37 PM, David Brownell wrote:
>> I'm not. Some gpios, such as those on io expanders, may sleep in their
>> implementations of the gpio_(set/get) functions.
> 
> I'm having a hard time figuring out where some GPIOs I'm using fit
> into this picture.
> 
> I have some hardware that is currently using a 2.4.26 kernel, but I
> look from time to time at forward-porting all the drivers to 2.6.recent.
> 
> It has an I2C driven GPIO expander, with a watchdog reset chip hanging
> off the expander.
> 
> The watchdog is kept alive off the back end of a timer BH, which means
> the I2C GPIO routines are written to be safe in BH context (which
> isn't sleepable), but they can't be used in IRQ context because the
> necessary spin_lock_irqsave() would turn off interrupts for too long
> for other subsystems to function properly.

Do the implementations of the get/set calls for the io expander gpios
sleep at all?

> How should I flag those GPIO routines in your scheme?  They're safe to
> use in some non-sleeping contexts, but not safe in irq context.

The idea in my proposal is to use gpio_request in a driver if the
requested gpio can never sleep (ie because of the context it is used
in), and gpio_request_cansleep if the gpio is never used from non-sleep
safe context in a driver. I suggested stripping back the patch to just
add the gpio_request_cansleep function.

In the current code, if a driver ever calls gpio_(set/get)_value on a
gpio then you cannot pass a sleeping gpio to that driver. The request
will succeed, but you will get warnings with the get/get calls are made.
My idea is basically to move the denotation of whether a gpio will be
used in non-sleep safe context to the gpio request.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From broonie at opensource.wolfsonmicro.com  Wed Jun 23 19:24:16 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Thu, 24 Jun 2010 00:24:16 +0100
Subject: [PATCH] ASoC: DaVinci: Added support for stereo I2S
In-Reply-To: <1277303635-5675-1-git-send-email-lamiaposta71@gmail.com>
	(sfid-20100623_154205_545825_0E9CDE5F)
References: <1277303635-5675-1-git-send-email-lamiaposta71@gmail.com>
	(sfid-20100623_154205_545825_0E9CDE5F)
Message-ID: <ACF70CBE-6096-431C-A5A1-E3700642EB53@opensource.wolfsonmicro.com>

On 23 Jun 2010, at 15:33, Raffaele Recalcati wrote:

> From: Raffaele Recalcati <raffaele.recalcati at bticino.it>
> 
> 	Added audio playback support with [frame sync master - clock master] mode
> 	and with [frame sync master - clock slave].
> 	Clock slave can be important when the external codec need system clock
> 	and bit clock synchronized.
> 	In the clock master case there is a FIXME message in the source code, because we
> 	(Davide and myself) have guessed a frequency of 122000000 that seems the base
> 	to be divided.
> 	This patch has been developed against the
> 		http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
> 	git tree and has been tested on bmx board (similar to dm365 evm, but using
> 	uda1345 as external audio codec).
> 
> Signed-off-by: Raffaele Recalcati <raffaele.recalcati at bticino.it>
> Signed-off-by: Davide Bonfanti <davide.bonfanti at bticino.it>

I'd pretty much echo what Liam said - I'm not 100% sure from your description what the
patch is supposed to do and the code isn't particularly clear either. It *looks* like you're
trying to add a new clock source, but from the description this appears to be an
externally visible clock which makes it very unclear why you have to guess the frequency.

From ben-linux at fluff.org  Wed Jun 23 19:24:22 2010
From: ben-linux at fluff.org (Ben Dooks)
Date: Thu, 24 Jun 2010 00:24:22 +0100
Subject: clock updates
Message-ID: <20100623232422.GB16584@trinity.fluff.org>

I've been looking into updating the current samsung socs to use
clkdev to lookup clocks. Currently we have a few issues that we
could do with sorting before running the conversion to clkdev.

Firstly, the s5pc100 has some clocks that could be merged into
common s5p, and a few which don't seem to match the others in
the s5p series.

The i2s clocks which we should look at mergining are:

i2s_cdclk<0..2>
pcm_cdclk<0..l>

also, clocks that have may need changing:

rotator	     => rot
keyif	     => keypad

this isn't an complete list, still working on the changes.

The big changes with respect to drivers is that we will now be using
clk_get(dev, NULL) to get the clock names, and any bus clocks such
as the sdhci bus clock will be updated.

The intention with both the SDHCI and the SPI is to change the clock
lookups to reflect the mux positions, so the sdhci clocks on the
s3c64xx would be changed to use the following lookups:

hsmmc	=> mux0
mmc_bus	=> mux2
48m	=> mux3

This would avoid passing the clock names through the platform data, if
the boards or the arch needs to avoid a clock, an array of clock enable
or disable bits. Any unimplemented clocks will return NULL to ensure
that they can be distinguished from a clock that isn't available.

The changes would be to remove the .name field from all the s3c struct clk,
and replace it with a pointer to a lookup (so that if the clock does not
need a name then it doesn't need a lookup).

There are also a number of clocks that probably don't need a name as they
are part of the clock heirarchy, it would be useful to have a call that
returns all possible parents of a given clock.

I'll post the script whcih runs the changes once i've finished the last
few details to show what happens.

With resepect to the clkdev clk_get() function, we may need to do a couple of
updates (ie, override it for ourselves) due to the following two problems:

1) The s3c/s5p devices change name depending on the soc they are attached
   to, which means we may need to cut the s3cxxxx- part of the device name
   off before running the lookup

2) Some of the lookups are done early for the serial driver, which means
   that the platform devices's name has not been setup, so something needs
   to be done about this.

-- 
Ben










-- 
Ben

Q:      What's a light-year?
A:      One-third less calories than a regular year.



From PeterHuewe at gmx.de  Wed Jun 23 19:28:41 2010
From: PeterHuewe at gmx.de (Peter =?iso-8859-1?q?H=FCwe?=)
Date: Thu, 24 Jun 2010 01:28:41 +0200
Subject: [PATCH] arm/include: Fix missing semicolon in module.h
In-Reply-To: <20100617092419.GI17639@pcarmody-desktop>
References: <201006161932.00542.PeterHuewe@gmx.de>
	<20100617092419.GI17639@pcarmody-desktop>
Message-ID: <201006240128.41556.PeterHuewe@gmx.de>

Am Donnerstag 17 Juni 2010 11:24:19 schrieb Phil Carmody:
> On 16/06/10 19:32 +0200, ext Peter Huewe wrote:
> > From: Peter Huewe <peterhuewe at gmx.de>
> >
> > This patch fixes a missing semicolon which introduced buildfailures [2]
> > for almost every arm defconfig, introduced by patch cecaa4c6b [1]
> >
> > This issue arises only if CONFIG_ARM_UNWIND is not set.
> >
> > Signed-off-by: Peter Huewe <peterhuewe at gmx.de>
> 
> My bad, sorry.
> 
> Acked-by: Phil Carmody <ext-phil.2.carmody at nokia.com>


Any updates on this one ? 

Peter


From khilman at deeprootsystems.com  Wed Jun 23 19:37:03 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Wed, 23 Jun 2010 16:37:03 -0700
Subject: [PATCH 2/3] OMAP: PM: use omap_device API for suspend/resume
In-Reply-To: <1277336224-24826-1-git-send-email-khilman@deeprootsystems.com>
References: <1277336224-24826-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1277336224-24826-3-git-send-email-khilman@deeprootsystems.com>

Hook into the platform bus methods for suspend and resume and
use the omap_device API to automatically idle and enable the
device on suspend and resume.

This allows device drivers to get rid of direct management of their
clocks in their suspend/resume paths, and let omap_device do it for
them.

We currently use the _noirq (late suspend, early resume) versions of
the suspend/resume methods to ensure that the device is not disabled
too early for any drivers also using the _noirq methods.

NOTE: only works for devices with omap_hwmod support.

Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-omap2/pm_bus.c |   61 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 61 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
index 69acaa5..3787da8 100644
--- a/arch/arm/mach-omap2/pm_bus.c
+++ b/arch/arm/mach-omap2/pm_bus.c
@@ -70,3 +70,64 @@ int platform_pm_runtime_idle(struct device *dev)
 };
 #endif /* CONFIG_PM_RUNTIME */
 
+#ifdef CONFIG_SUSPEND
+int platform_pm_suspend_noirq(struct device *dev)
+{
+	struct device_driver *drv = dev->driver;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_device *odev = to_omap_device(pdev);
+	int ret = 0;
+
+	if (!drv)
+		return 0;
+
+	if (drv->pm) {
+		if (drv->pm->suspend_noirq)
+			ret = drv->pm->suspend_noirq(dev);
+	}
+
+	if (omap_device_is_valid(odev)) {
+		if (odev->flags & OMAP_DEVICE_NO_BUS_SUSPEND) {
+			dev_dbg(dev, "no automatic bus-level system resume.\n");
+			return 0;
+		}
+
+		dev_dbg(dev, "%s\n", __func__);
+		omap_device_idle(pdev);
+	} else {
+		dev_dbg(dev, "not an omap_device\n");
+	}
+
+	return ret;
+}
+
+int platform_pm_resume_noirq(struct device *dev)
+{
+	struct device_driver *drv = dev->driver;
+	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_device *odev = to_omap_device(pdev);
+	int ret = 0;
+
+	if (omap_device_is_valid(odev)) {
+		if (odev->flags & OMAP_DEVICE_NO_BUS_SUSPEND) {
+			dev_dbg(dev, "no automatic bus-level system resume.\n");
+			return 0;
+		}
+
+		dev_dbg(dev, "%s\n", __func__);
+		omap_device_enable(pdev);
+	} else {
+		dev_dbg(dev, "not an omap_device\n");
+	}
+
+	if (!drv)
+		return 0;
+
+	if (drv->pm) {
+		if (drv->pm->resume_noirq)
+			ret = drv->pm->resume_noirq(dev);
+	}
+
+	return ret;
+}
+#endif /* CONFIG_SUSPEND */
-- 
1.7.0.2



From khilman at deeprootsystems.com  Wed Jun 23 19:37:02 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Wed, 23 Jun 2010 16:37:02 -0700
Subject: [PATCH 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <1277336224-24826-1-git-send-email-khilman@deeprootsystems.com>
References: <1277336224-24826-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1277336224-24826-2-git-send-email-khilman@deeprootsystems.com>

Implement the new runtime PM framework as a thin layer on top of the
omap_device API.  Since we don't have an OMAP-specific bus, override
the runtime PM hooks for the platform_bus for the OMAP specific
implementation.

While the runtime PM API has three main states (idle, suspend, resume)
This version treats idle and suspend the same way by implementing both
on top of omap_device_disable(), which follows closely with how driver
are currently using clock enable/disable calls. Longer-termm
pm_runtime_idle() could take other constraints into consideration to
make the decision, but the current

Device driver ->runtime_suspend() hooks are called just before the
device is disabled (via omap_device_idle()), and device driver
->runtime_resume() hooks are called just after device has been
enabled (via omap_device_enable().)

Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-omap2/Makefile |    7 +++-
 arch/arm/mach-omap2/pm_bus.c |   72 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap2/pm_bus.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ea52b03..8ed47ea 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -46,12 +46,17 @@ obj-$(CONFIG_ARCH_OMAP2)		+= sdrc2xxx.o
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o
-obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o cpuidle34xx.o \
+					   pm_bus.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 
 AFLAGS_sleep24xx.o			:=-Wa,-march=armv6
 AFLAGS_sleep34xx.o			:=-Wa,-march=armv7-a
 
+ifeq ($(CONFIG_PM_VERBOSE),y)
+CFLAGS_pm_bus.o				+= -DDEBUG
+endif
+
 endif
 
 # PRCM
diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
new file mode 100644
index 0000000..69acaa5
--- /dev/null
+++ b/arch/arm/mach-omap2/pm_bus.c
@@ -0,0 +1,72 @@
+/*
+ * Runtime PM support code for OMAP
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+
+#include <plat/omap_device.h>
+#include <plat/omap-pm.h>
+
+#ifdef CONFIG_PM_RUNTIME
+int platform_pm_runtime_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_device *odev = to_omap_device(pdev);
+	int r, ret = 0;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	if (dev->driver->pm && dev->driver->pm->runtime_suspend)
+		ret = dev->driver->pm->runtime_suspend(dev);
+	if (!ret && omap_device_is_valid(odev)) {
+		r = omap_device_idle(pdev);
+		WARN_ON(r);
+	}
+
+	return ret;
+};
+
+int platform_pm_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_device *odev = to_omap_device(pdev);
+	int r, ret = 0;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	if (omap_device_is_valid(odev)) {
+		r = omap_device_enable(pdev);
+		WARN_ON(r);
+	}
+
+	if (dev->driver->pm && dev->driver->pm->runtime_resume)
+		ret = dev->driver->pm->runtime_resume(dev);
+
+	return ret;
+};
+
+int platform_pm_runtime_idle(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_device *odev = to_omap_device(pdev);
+	int ret;
+
+	ret = pm_runtime_suspend(dev);
+	dev_dbg(dev, "%s [%d]\n", __func__, ret);
+
+	return 0;
+};
+#endif /* CONFIG_PM_RUNTIME */
+
-- 
1.7.0.2



From khilman at deeprootsystems.com  Wed Jun 23 19:37:04 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Wed, 23 Jun 2010 16:37:04 -0700
Subject: [PATCH 3/3] OMAP1: PM: add simple runtime PM layer to manage clocks
In-Reply-To: <1277336224-24826-1-git-send-email-khilman@deeprootsystems.com>
References: <1277336224-24826-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1277336224-24826-4-git-send-email-khilman@deeprootsystems.com>

On OMAP1, we do not have omap_device + omap_hwmod to manage the
device-specific idle, enable and shutdown.  Instead, just
enable/disable device clocks automatically at the runtime PM level.

This allows drivers to not have any OMAP1 specific clock management
and allows them to simply use the runtime PM API to manage clocks.

Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-omap1/Makefile |    2 +-
 arch/arm/mach-omap1/pm_bus.c |   77 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap1/pm_bus.c

diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index ea231c7..fd4df71 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_OMAP_MPU_TIMER)	+= time.o
 obj-$(CONFIG_OMAP_32K_TIMER)	+= timer32k.o
 
 # Power Management
-obj-$(CONFIG_PM) += pm.o sleep.o
+obj-$(CONFIG_PM) += pm.o sleep.o pm_bus.o
 
 # DSP
 obj-$(CONFIG_OMAP_MBOX_FWK)	+= mailbox_mach.o
diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c
new file mode 100644
index 0000000..29d651a
--- /dev/null
+++ b/arch/arm/mach-omap1/pm_bus.c
@@ -0,0 +1,77 @@
+/*
+ * Runtime PM support code for OMAP1
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+
+#include <plat/omap_device.h>
+#include <plat/omap-pm.h>
+
+#ifdef CONFIG_PM_RUNTIME
+int platform_pm_runtime_suspend(struct device *dev)
+{
+	struct clk *iclk, *fclk;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	if (dev->driver->pm && dev->driver->pm->runtime_suspend)
+		ret = dev->driver->pm->runtime_suspend(dev);
+
+	fclk = clk_get(dev, "fck");
+	if (!IS_ERR(fclk)) {
+		clk_disable(fclk);
+		clk_put(fclk);
+	}
+
+	iclk = clk_get(dev, "ick");
+	if (!IS_ERR(iclk)) {
+		clk_disable(iclk);
+		clk_put(iclk);
+	}
+
+	return 0;
+};
+
+int platform_pm_runtime_resume(struct device *dev)
+{
+	int r, ret = 0;
+	struct clk *iclk, *fclk;
+
+	iclk = clk_get(dev, "ick");
+	if (!IS_ERR(iclk)) {
+		clk_enable(iclk);
+		clk_put(iclk);
+	}
+
+	fclk = clk_get(dev, "fck");
+	if (!IS_ERR(fclk)) {
+		clk_enable(fclk);
+		clk_put(fclk);
+	}
+
+	if (dev->driver->pm && dev->driver->pm->runtime_resume)
+		ret = dev->driver->pm->runtime_resume(dev);
+
+	return ret;
+};
+
+int platform_pm_runtime_idle(struct device *dev)
+{
+	ret = pm_runtime_suspend(dev);
+	dev_dbg(dev, "%s [%d]\n", __func__, ret);
+
+	return 0;
+};
+#endif /* CONFIG_PM_RUNTIME */
-- 
1.7.0.2



From khilman at deeprootsystems.com  Wed Jun 23 19:37:01 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Wed, 23 Jun 2010 16:37:01 -0700
Subject: [PATCH 0/3] OMAP: add runtime PM support at bus-level
Message-ID: <1277336224-24826-1-git-send-email-khilman@deeprootsystems.com>

This series introduces runtime PM support at the platform bus level
for OMAP.

In a nutshell, when using the runtime PM API for any device with an
assocated omap_device (and hwmod), the omap device API will be used to
handle the hardware-level power management of that device, including
managing clocks, etc.

Today, most drivers handle this by manually enabling/disabling their
clocks when needed.  With this series (and an omap_device/hwmod for
each device) direct clock managment can be removed from the driver in
favor of using the runtime PM API.

This series applies on top v2.6.35-rc2 + Tony's omap-fixes branch and
is also available in the pm-wip/runtime branch of my linux-omap-pm git
tree:

  git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git

Kevin Hilman (3):
  OMAP: PM: initial runtime PM core support
  OMAP: PM: use omap_device API for suspend/resume
  OMAP1: PM: add simple runtime PM layer to manage clocks

 arch/arm/mach-omap1/Makefile |    2 +-
 arch/arm/mach-omap1/pm_bus.c |   77 ++++++++++++++++++++++++
 arch/arm/mach-omap2/Makefile |    7 ++-
 arch/arm/mach-omap2/pm_bus.c |  133 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 217 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-omap1/pm_bus.c
 create mode 100644 arch/arm/mach-omap2/pm_bus.c



From sfr at canb.auug.org.au  Wed Jun 23 19:52:33 2010
From: sfr at canb.auug.org.au (Stephen Rothwell)
Date: Thu, 24 Jun 2010 09:52:33 +1000
Subject: [GIT PULL linux-next] Samsung S5P SoCs
In-Reply-To: <000d01cb126e$fa193690$ee4ba3b0$%kim@samsung.com>
References: <000d01cb126e$fa193690$ee4ba3b0$%kim@samsung.com>
Message-ID: <20100624095233.d2daaa4f.sfr@canb.auug.org.au>

Hi,

On Wed, 23 Jun 2010 09:56:52 +0900 Kukjin Kim <kgene.kim at samsung.com> wrote:
>
> Could you please pull the following into linux-next?
> 
> git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git#for-ne
> xt
> 
> This tree is for next- Samsung S5P SoCs such as S5P6440, S5P6442, S5PC100,
> and S5PV210/S5PC110.

I have added this from today.  I have called the tree s5p.  Currently you
alone are the contact for problems to do with this tree - should I add
anyone else (or a mailing list)?

Thanks for adding your subsystem tree as a participant of linux-next.  As
you may know, this is not a judgment of your code.  The purpose of
linux-next is for integration testing and to lower the impact of
conflicts between subsystems in the next merge window. 

You will need to ensure that the patches/commits in your tree/series have
been:
     * submitted under GPL v2 (or later) and include the Contributor's
	Signed-off-by,
     * posted to the relevant mailing list,
     * reviewed by you (or another maintainer of your subsystem tree),
     * successfully unit tested, and 
     * destined for the current or next Linux merge window.

Basically, this should be just what you would send to Linus (or ask him
to fetch).  It is allowed to be rebased if you deem it necessary.

-- 
Cheers,
Stephen Rothwell 
sfr at canb.auug.org.au

Legal Stuff:
By participating in linux-next, your subsystem tree contributions are
public and will be included in the linux-next trees.  You may be sent
e-mail messages indicating errors or other issues when the
patches/commits from your subsystem tree are merged and tested in
linux-next.  These messages may also be cross-posted to the linux-next
mailing list, the linux-kernel mailing list, etc.  The linux-next tree
project and IBM (my employer) make no warranties regarding the linux-next
project, the testing procedures, the results, the e-mails, etc.  If you
don't agree to these ground rules, let me know and I'll remove your tree
from participation in linux-next.
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From jamie at shareable.org  Wed Jun 23 20:04:03 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Thu, 24 Jun 2010 01:04:03 +0100
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping
	gpios)
In-Reply-To: <4C22936F.9050300@bluewatersys.com>
References: <191168.5104.qm@web180308.mail.gq1.yahoo.com>
	<4C21955D.1020502@bluewatersys.com>
	<20100623225345.GD7058@shareable.org>
	<4C22936F.9050300@bluewatersys.com>
Message-ID: <20100624000403.GH7058@shareable.org>

Ryan Mallon wrote:
> On 06/24/2010 10:53 AM, Jamie Lokier wrote:
> > Ryan Mallon wrote:
> >> On 06/23/2010 04:37 PM, David Brownell wrote:
> >> I'm not. Some gpios, such as those on io expanders, may sleep in their
> >> implementations of the gpio_(set/get) functions.
> > 
> > I'm having a hard time figuring out where some GPIOs I'm using fit
> > into this picture.
> > 
> > I have some hardware that is currently using a 2.4.26 kernel, but I
> > look from time to time at forward-porting all the drivers to 2.6.recent.
> > 
> > It has an I2C driven GPIO expander, with a watchdog reset chip hanging
> > off the expander.
> > 
> > The watchdog is kept alive off the back end of a timer BH, which means
> > the I2C GPIO routines are written to be safe in BH context (which
> > isn't sleepable), but they can't be used in IRQ context because the
> > necessary spin_lock_irqsave() would turn off interrupts for too long
> > for other subsystems to function properly.
> 
> Do the implementations of the get/set calls for the io expander gpios
> sleep at all?

No, because sleeping isn't allowed in BH context.  (Note that this is
2.4.26 code - things have changed a bit for 2.6, but the hardware is
the same, and still needs the I2C watchdog to be driven from a BH-like
context).

> > How should I flag those GPIO routines in your scheme?  They're safe to
> > use in some non-sleeping contexts, but not safe in irq context.
> 
> The idea in my proposal is to use gpio_request in a driver if the
> requested gpio can never sleep (ie because of the context it is used
> in), and gpio_request_cansleep if the gpio is never used from non-sleep
> safe context in a driver. I suggested stripping back the patch to just
> add the gpio_request_cansleep function.
> 
> In the current code, if a driver ever calls gpio_(set/get)_value on a
> gpio then you cannot pass a sleeping gpio to that driver. The request
> will succeed, but you will get warnings with the get/get calls are made.
> My idea is basically to move the denotation of whether a gpio will be
> used in non-sleep safe context to the gpio request.

The reason I'm asking about my scenario is because the GPIO routines
can't sleep and are used from a non-sleep safe context - but they are
not safe to call in irq contexts.

So my watchdog driver would have to call gpio_request (not _cansleep)
- that's fine.  But if I connected other GPIOs from the same GPIO
driver (other lines on the same I/O expander chip) to another
GPIO-using driver which happens to use them from irq context, then
your changes won't detect the problem - the code will just break at
runtime.

Of course if I did that, it would be my fault and my problem.  I get
to keep both pieces etc.  But it's a scenario which your proposal
would fail to catch at compile time, that's why I bring it up.

-- Jamie


From ryan at bluewatersys.com  Wed Jun 23 20:10:29 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Thu, 24 Jun 2010 12:10:29 +1200
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping
	gpios)
In-Reply-To: <20100624000403.GH7058@shareable.org>
References: <191168.5104.qm@web180308.mail.gq1.yahoo.com>
	<4C21955D.1020502@bluewatersys.com>
	<20100623225345.GD7058@shareable.org>
	<4C22936F.9050300@bluewatersys.com>
	<20100624000403.GH7058@shareable.org>
Message-ID: <4C22A275.3030102@bluewatersys.com>

On 06/24/2010 12:04 PM, Jamie Lokier wrote:
> Ryan Mallon wrote:
>> On 06/24/2010 10:53 AM, Jamie Lokier wrote:
>>> Ryan Mallon wrote:
>>>> On 06/23/2010 04:37 PM, David Brownell wrote:
>>>> I'm not. Some gpios, such as those on io expanders, may sleep in their
>>>> implementations of the gpio_(set/get) functions.
>>>
>>> I'm having a hard time figuring out where some GPIOs I'm using fit
>>> into this picture.
>>>
>>> I have some hardware that is currently using a 2.4.26 kernel, but I
>>> look from time to time at forward-porting all the drivers to 2.6.recent.
>>>
>>> It has an I2C driven GPIO expander, with a watchdog reset chip hanging
>>> off the expander.
>>>
>>> The watchdog is kept alive off the back end of a timer BH, which means
>>> the I2C GPIO routines are written to be safe in BH context (which
>>> isn't sleepable), but they can't be used in IRQ context because the
>>> necessary spin_lock_irqsave() would turn off interrupts for too long
>>> for other subsystems to function properly.
>>
>> Do the implementations of the get/set calls for the io expander gpios
>> sleep at all?
> 
> No, because sleeping isn't allowed in BH context.  (Note that this is
> 2.4.26 code - things have changed a bit for 2.6, but the hardware is
> the same, and still needs the I2C watchdog to be driven from a BH-like
> context).
> 
>>> How should I flag those GPIO routines in your scheme?  They're safe to
>>> use in some non-sleeping contexts, but not safe in irq context.
>>
>> The idea in my proposal is to use gpio_request in a driver if the
>> requested gpio can never sleep (ie because of the context it is used
>> in), and gpio_request_cansleep if the gpio is never used from non-sleep
>> safe context in a driver. I suggested stripping back the patch to just
>> add the gpio_request_cansleep function.
>>
>> In the current code, if a driver ever calls gpio_(set/get)_value on a
>> gpio then you cannot pass a sleeping gpio to that driver. The request
>> will succeed, but you will get warnings with the get/get calls are made.
>> My idea is basically to move the denotation of whether a gpio will be
>> used in non-sleep safe context to the gpio request.
> 
> The reason I'm asking about my scenario is because the GPIO routines
> can't sleep and are used from a non-sleep safe context - but they are
> not safe to call in irq contexts.
> 
> So my watchdog driver would have to call gpio_request (not _cansleep)
> - that's fine.  But if I connected other GPIOs from the same GPIO
> driver (other lines on the same I/O expander chip) to another
> GPIO-using driver which happens to use them from irq context, then
> your changes won't detect the problem - the code will just break at
> runtime.
> 
> Of course if I did that, it would be my fault and my problem.  I get
> to keep both pieces etc.  But it's a scenario which your proposal
> would fail to catch at compile time, that's why I bring it up.

That's true. It wouldn't be caught in the current code either. I'm not
sure how you would go about sensibly writing code to handle that
situation; it's really a problem that needs to be caught during patch
review.

~Ryan

-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From paul at pwsan.com  Wed Jun 23 20:24:38 2010
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 23 Jun 2010 18:24:38 -0600
Subject: [PATCH] OMAP: hwmod regression fix for 2.6.35-rc
Message-ID: <20100624002249.12347.37548.stgit@localhost.localdomain>

Hi,

This patch (intended for 2.6.35-rc) fixes a bad regression in
2.6.35-rc preventing the hwmod code from working.


- Paul


---

Benoit Cousson (1):
      OMAP: hwmod: Fix the missing braces


 arch/arm/mach-omap2/omap_hwmod.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)




From paul at pwsan.com  Wed Jun 23 20:24:47 2010
From: paul at pwsan.com (Paul Walmsley)
Date: Wed, 23 Jun 2010 18:24:47 -0600
Subject: [PATCH] OMAP: hwmod: Fix the missing braces
In-Reply-To: <20100624002249.12347.37548.stgit@localhost.localdomain>
References: <20100624002249.12347.37548.stgit@localhost.localdomain>
Message-ID: <20100624002438.12347.60529.stgit@localhost.localdomain>

From: Benoit Cousson <b-cousson at ti.com>

As reported by Sergei, a couple of braces were missing after
the WARN removal patch.

[07/22] OMAP: hwmod: Replace WARN by pr_warning if clock lookup failed

https://patchwork.kernel.org/patch/100756/

Signed-off-by: Benoit Cousson <b-cousson at ti.com>
[paul at pwsan.com: fixed patch description per Anand's E-mail]
Signed-off-by: Paul Walmsley <paul at pwsan.com>
Cc: Sergei Shtylyov <sshtylyov at mvista.com>
Cc: Anand Gadiyar <gadiyar at ti.com>
---
 arch/arm/mach-omap2/omap_hwmod.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 95c9a5f..b7a4133 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -409,10 +409,11 @@ static int _init_main_clk(struct omap_hwmod *oh)
 		return 0;
 
 	oh->_clk = omap_clk_get_by_name(oh->main_clk);
-	if (!oh->_clk)
+	if (!oh->_clk) {
 		pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
 			   oh->name, oh->main_clk);
 		return -EINVAL;
+	}
 
 	if (!oh->_clk->clkdm)
 		pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
@@ -444,10 +445,11 @@ static int _init_interface_clks(struct omap_hwmod *oh)
 			continue;
 
 		c = omap_clk_get_by_name(os->clk);
-		if (!c)
+		if (!c) {
 			pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
 				   oh->name, os->clk);
 			ret = -EINVAL;
+		}
 		os->_clk = c;
 	}
 
@@ -470,10 +472,11 @@ static int _init_opt_clks(struct omap_hwmod *oh)
 
 	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
 		c = omap_clk_get_by_name(oc->clk);
-		if (!c)
+		if (!c) {
 			pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
 				   oh->name, oc->clk);
 			ret = -EINVAL;
+		}
 		oc->_clk = c;
 	}
 




From jamie at shareable.org  Wed Jun 23 20:28:53 2010
From: jamie at shareable.org (Jamie Lokier)
Date: Thu, 24 Jun 2010 01:28:53 +0100
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <alpine.LFD.2.00.1006231002530.24097@xanadu.home>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
	<20100623073912.GA12255@atomide.com>
	<20100623133636.GC7058@shareable.org>
	<alpine.LFD.2.00.1006231002530.24097@xanadu.home>
Message-ID: <20100624002853.GJ7058@shareable.org>

Nicolas Pitre wrote:
> On Wed, 23 Jun 2010, Jamie Lokier wrote:
> 
> > For other things like __switch_to and maybe cache maintenance calls,
> > dmb() etc, I'd suggest first doing a generic asm mechanism like x86's
> > "alternatives", keeping in mind that one of the alternatives has to be
> > XIP friendly.
> 
> You cannot be XIP friendly unless you rewrite the concerned function(s) 
> into a RAM page in order to modify it.  And then of course you have to 
> play tricks with the linker so that the rewritten functions are 
> referenced with their final rewritten location.  And that means of 
> course that the RAM location has to be a constant unless we introduce 
> some indirect function calls.  And at that point we're not much better 
> than the proposed runtime test.
> 
> Also, if you are interested by a XIP kernel, this usually means you have 
> a fairly highly customized kernel config.  In this context it is 
> senseless to have runtime patching of the kernel.  What you want in that 
> case is as much stuff as possible selected and optimized at compile 
> time, and anything you don't need configured out.

I wasn't suggesting that XIP kernels do any run-time npatching.
Sorry, I thought that was obvious.

What I mean is to provide a set of macros, a bit like x86's
alternatives macros, which take various asm fragments and the
condition which would choose between them, and compiles to
unconditional code if the condition is known at compile time (XIP or
not), otherwise compiles to fixed, run-time conditional code on XIP
(it could be conditional code or an indirect functional call), and on
non-XIP compiles to patchable code with an alternate-table section.

-- Jamie


From kmpark at infradead.org  Wed Jun 23 21:35:27 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Thu, 24 Jun 2010 10:35:27 +0900
Subject: [PATCH 2/3] ARM: S5P: Add System define for arch_reset()
In-Reply-To: <1277332317-30192-3-git-send-email-kgene.kim@samsung.com>
References: <1277332317-30192-1-git-send-email-kgene.kim@samsung.com>
	<1277332317-30192-3-git-send-email-kgene.kim@samsung.com>
Message-ID: <AANLkTim2s6syCjpl5v_qVloktrzz27JsSrR6kgWqNHUm@mail.gmail.com>

On Thu, Jun 24, 2010 at 7:31 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> From: Jongpill Lee <boyko.lee at samsung.com>
>
> This patch adds system define for arch_reset() using Watchdog reset.
> And adds IO mapping for using WDT.

Are there any reason to use the WDT to system reset?
As original purpose of WDT. doesn't it better to use system reset?
Since we use the WDT reset at other purpose. but if you add the WDT
reset to system reset.
then we can't control it. bootloader check the reset reason then
report something wrong at previous operation.

So I want to use system reset as original purpose.

Thank you,
Kyungmin Park

>
> Signed-off-by: Jongpill Lee <boyko.lee at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> ---
> ?arch/arm/plat-s5p/cpu.c ? ? ? ? ? ? ? ? ? ? ? | ? ?5 +++++
> ?arch/arm/plat-s5p/include/plat/system-reset.h | ? 24 ++++++++++++++++++++++++
> ?2 files changed, 29 insertions(+), 0 deletions(-)
> ?create mode 100644 arch/arm/plat-s5p/include/plat/system-reset.h
>
> diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
> index 75cb8c3..1ab55e8 100644
> --- a/arch/arm/plat-s5p/cpu.c
> +++ b/arch/arm/plat-s5p/cpu.c
> @@ -103,6 +103,11 @@ static struct map_desc s5p_iodesc[] __initdata = {
> ? ? ? ? ? ? ? ?.pfn ? ? ? ? ? ?= __phys_to_pfn(S5P_PA_GPIO),
> ? ? ? ? ? ? ? ?.length ? ? ? ? = SZ_4K,
> ? ? ? ? ? ? ? ?.type ? ? ? ? ? = MT_DEVICE,
> + ? ? ? }, {
> + ? ? ? ? ? ? ? .virtual ? ? ? ?= (unsigned long)S3C_VA_WATCHDOG,
> + ? ? ? ? ? ? ? .pfn ? ? ? ? ? ?= __phys_to_pfn(S3C_PA_WDT),
> + ? ? ? ? ? ? ? .length ? ? ? ? = SZ_4K,
> + ? ? ? ? ? ? ? .type ? ? ? ? ? = MT_DEVICE,
> ? ? ? ?},
> ?};
>
> diff --git a/arch/arm/plat-s5p/include/plat/system-reset.h b/arch/arm/plat-s5p/include/plat/system-reset.h
> new file mode 100644
> index 0000000..7f76a16
> --- /dev/null
> +++ b/arch/arm/plat-s5p/include/plat/system-reset.h
> @@ -0,0 +1,24 @@
> +/* linux/arch/arm/plat-s5p/include/plat/system-reset.h
> + *
> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> + * ? ? ? ? ? ? http://www.samsung.com
> + *
> + * Based on arch/arm/mach-s3c2410/include/mach/system-reset.h
> + *
> + * S5P - System define for arch_reset()
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <plat/watchdog-reset.h>
> +
> +static void arch_reset(char mode, const char *cmd)
> +{
> + ? ? ? /* Perform reset using Watchdog reset.
> + ? ? ? ?* SWRESET support will be added later.
> + ? ? ? ?*/
> +
> + ? ? ? arch_wdt_reset();
> +}
> --
> 1.6.2.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>


From kmpark at infradead.org  Wed Jun 23 22:08:09 2010
From: kmpark at infradead.org (Kyungmin Park)
Date: Thu, 24 Jun 2010 11:08:09 +0900
Subject: Samsung SoCs: preparation for single kernel
In-Reply-To: <003e01cb12b5$656c0670$30441350$%szyprowski@samsung.com>
References: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com>
	<AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com>
	<AANLkTil1i_ZGI8bY14HhjrAk9RooVreAJsTteqqrMgqJ@mail.gmail.com>
	<AANLkTikDml6gQAsiRrCjIt4bUD3hnpAATr1erqCGOJMd@mail.gmail.com>
	<002301cb129c$ec59fe30$c50dfa90$%szyprowski@samsung.com>
	<AANLkTikspf9zHuSKe86wDQxI12HpJo_occBlLUXBkjef@mail.gmail.com>
	<003e01cb12b5$656c0670$30441350$%szyprowski@samsung.com>
Message-ID: <AANLkTimqQyHLm4KcxYwYC8slSoy9udi2gganKdsD_8Nw@mail.gmail.com>

On Wed, Jun 23, 2010 at 6:20 PM, Marek Szyprowski
<m.szyprowski at samsung.com> wrote:
> Hello,
>
> On Wednesday, June 23, 2010 10:02 AM Eric Miao wrote:
>
>> >> Now you have
>> >>
>> >> s5pv210_device_hsmmc0
>> >> s5pc100_device_hsmmc0
>> >> s3c64xx_device_hsmmc0
>> >> ....
>> >>
>> >> each with a different base.
>> >
>> > There is no need for such code duplication.
>>
>> However, I believe this is the right way to go. A certain level of
>> duplication is the price to pay for a generic and clean solution.
>>
>> When a peripheral controller or IP is moved from one SoC to the
>> next generation, there are several things could have been changed:
>>
>> 1. new base address and IRQ number
>> 2. fixes and enhancements to the original IP
>>
>> 1. will result in a different 'struct resource', and 2. will result in a
>> different 'struct platform_device' with a different name, so the driver
>> can match the platform_device_id table as you agreed I'm right on
>> that recommendation.
>>
>> They are actually _two_ different devices.
>
> Right, they are separate entities, but would be really good if a similar
> git brcode could be merged together.
>
>> > Ben is working on a solution for
>> > a single kernel which supports multiple SoCs. Some of his work in
>> progress can
>> > be found here: git://git.fluff.org/bjdooks/linux branch wip-samsung-dev
>> and
>> > wip-samsung-dev2.
>>
>> Could you describe it a bit here and bring it on table for discussion?
>
> The idea behind his patches is to provide a table for each SoC with short
> description of all available devices and generate platform_device entries
> dynamically from that table.
>
> Here is a short code example:
>
> struct s3c_pdev_table s3c6xxx_dev_table[] __initdata = {
> ? ? ? ?{
> ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_UART,
> ? ? ? ? ? ? ? ?.name ? = "s3c6400-uart",
> ? ? ? ? ? ? ? ?.index ?= 0,
> ? ? ? ? ? ? ? ?.base ? = S3C_PA_UART0,
> ? ? ? ? ? ? ? ?.irq ? ?= IRQ_S3CUART_RX0,
> ? ? ? ? ? ? ? ?.template = &template_uart_s3c64xx,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_UART,
> ? ? ? ? ? ? ? ?.name ? = "s3c6400-uart",
> ? ? ? ? ? ? ? ?.index ?= 1,
> ? ? ? ? ? ? ? ?.base ? = S3C_PA_UART1,
> ? ? ? ? ? ? ? ?.irq ? ?= IRQ_S3CUART_RX1,
> ? ? ? ? ? ? ? ?.template = &template_uart_s3c64xx,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_UART,
> ? ? ? ? ? ? ? ?.name ? = "s3c6400-uart",
> ? ? ? ? ? ? ? ?.index ?= 2,
> ? ? ? ? ? ? ? ?.base ? = S3C_PA_UART2,
> ? ? ? ? ? ? ? ?.irq ? ?= IRQ_S3CUART_RX2,
> ? ? ? ? ? ? ? ?.template = &template_uart_s3c64xx,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_UART,
> ? ? ? ? ? ? ? ?.name ? = "s3c6400-uart",
> ? ? ? ? ? ? ? ?.index ?= 3,
> ? ? ? ? ? ? ? ?.base ? = S3C_PA_UART3,
> ? ? ? ? ? ? ? ?.irq ? ?= IRQ_S3CUART_RX3,
> ? ? ? ? ? ? ? ?.template = &template_uart_s3c64xx,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_WATCHDOG,
> ? ? ? ? ? ? ? ?.name ? = "s3c2410-wdt",
> ? ? ? ? ? ? ? ?.index ?= -1,
> ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_WATCHDOG,
> ? ? ? ? ? ? ? ?.irq ? ?= IRQ_WDT,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_SDHCI,
> ? ? ? ? ? ? ? ?.name ? = "s3c-sdhci",
> ? ? ? ? ? ? ? ?.index ?= 0,
> ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_HSMMC0 ,
> ? ? ? ? ? ? ? ?.irq ? ?= IRQ_HSMMC0,
> ? ? ? ? ? ? ? ?.dma ? ?= &samsung_std_dma_mask,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_SDHCI,
> ? ? ? ? ? ? ? ?.name ? = "s3c-sdhci",
> ? ? ? ? ? ? ? ?.index ?= 1,
> ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_HSMMC1,
> ? ? ? ? ? ? ? ?.irq ? ?= IRQ_HSMMC1,
> ? ? ? ? ? ? ? ?.dma ? ?= &samsung_std_dma_mask,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_SDHCI,
> ? ? ? ? ? ? ? ?.name ? = "s3c-sdhci",
> ? ? ? ? ? ? ? ?.index ?= 2,
> ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_HSMMC2,
> ? ? ? ? ? ? ? ?.irq ? ?= IRQ_HSMMC1,
> ? ? ? ? ? ? ? ?.dma ? ?= &samsung_std_dma_mask,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_OHCI,
> ? ? ? ? ? ? ? ?.name ? = "s3c2410-ohci",
> ? ? ? ? ? ? ? ?.index ?= -1,
> ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_USBHOST,
> ? ? ? ? ? ? ? ?.irq ? ?= IRQ_USBH,
> ? ? ? ? ? ? ? ?.dma ? ?= &samsung_std_dma_mask,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_NAND,
> ? ? ? ? ? ? ? ?.name ? = "s3c6400-nand",
> ? ? ? ? ? ? ? ?.index ?= -1,
> ? ? ? ? ? ? ? ?.base ? = 0x4E000000,
> ? ? ? ? ? ? ? ?.irq ? ?= IRQ_NFC,
> ? ? ? ?}, {
> ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_I2C,
> ? ? ? ? ? ? ? ?.name ? = "s3c2440-i2c",
> ? ? ? ? ? ? ? ?.index ?= 0,
> ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_IIC0,
> ? ? ? ? ? ? ? ?.irq ? ?= IRQ_IIC,
> ? ? ? ?}, {
> ...
>
> This solution is imho really clean an easy to understand. It is also
> easy to check which SoC has which peripherals defined and how.

Question. recently it's changed to use MMC0, MMC2, MMC3, then how to define it?
More basically, where these info are defined for chip or board?
If chip, the how to handle several variants?

Thank you,
Kyungmin Park

>
> I hope Ben will be able to finish it soon and all Samsung platforms can
> be converted for it. Then creating a single kernel for more than one SoC
> should be possible with only a few additional changes.
>
>> PS: My feeling of commenting several of the samsung patches so far turns
>> out to be quite frustrated, or I'm just too sensitive. NOTE neither am I
>> NAKing Samsung patches, nor am I interested to be involved, I'm just givin
>> my suggestions.
>
> I'm sorry if I offended You. I just wanted to show that the solution has
> been already found.
>
> Best regards
> --
> Marek Szyprowski
> Samsung Poland R&D Center
>
>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
>


From marek.vasut at gmail.com  Wed Jun 23 23:17:23 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 24 Jun 2010 05:17:23 +0200
Subject: [PATCH 1/4] pxa2xx/cpufreq: Simplify CPU frequency change asm
In-Reply-To: <87eifxa81o.fsf@free.fr>
References: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
	<87eifxa81o.fsf@free.fr>
Message-ID: <201006240517.23651.marek.vasut@gmail.com>

Dne St 23. ?ervna 2010 21:00:19 Robert Jarzmik napsal(a):
> Marek Vasut <marek.vasut at gmail.com> writes:
> > This patch does the following changes to cpufreq-pxa2xx:
> > 1) Simplifies the assembler code for frequency change
> 
> OK, but did you think over what the old code was doing ?
> My guess is that all the jumps were there to trigger a load into the
> I-Cache before playing with memory timings. Did you consider that your new
> assembly fits fully into a cache line, and hence is protected from memory
> shutdown for the frequency change period ?

Good point, I'll rethink this. FTTB dropped from patchqueue.
> 
> If you thought this over, then I would suggest to put a comment into the
> code to state that the assembly bit fits fully in one cache line. If not,
> I don't see clearly the benefit of removing the jumps ("b 2f" and "b 1b").
> 
> And I didn't find the reference for the need of reading the MDREFR register
> after the write. Would you give me a pointer in the pxa27x TRM please ?

I believe the written data might be stuck in the Dcache, reading it back should 
prevent this from happening. We certainly don't want to end with locked-up 
machine, which I saw already. The reason is still unknown to me though.

Cheers
> 
> Cheers.
> 
> --
> Robert


From Jon.Povey at racelogic.co.uk  Thu Jun 24 00:33:56 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Thu, 24 Jun 2010 05:33:56 +0100
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and
	sleepinggpios)
In-Reply-To: <20100624000403.GH7058@shareable.org>
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08E0855B96@Cloud.RL.local>

Jamie Lokier wrote:
> Ryan Mallon wrote:
>> On 06/24/2010 10:53 AM, Jamie Lokier wrote:

>>> It has an I2C driven GPIO expander, with a watchdog reset chip
>>> hanging off the expander.
>>>
>>> The watchdog is kept alive off the back end of a timer BH, which
>>> means the I2C GPIO routines are written to be safe in BH context
>>> (which
>>> isn't sleepable), but they can't be used in IRQ context because the
>>> necessary spin_lock_irqsave() would turn off interrupts for too long
>>> for other subsystems to function properly.
>>
>> Do the implementations of the get/set calls for the io expander gpios
>> sleep at all?
>
> No, because sleeping isn't allowed in BH context.  (Note that this is
> 2.4.26 code - things have changed a bit for 2.6, but the hardware is
> the same, and still needs the I2C watchdog to be driven from a BH-like
> context).

Could you use a workqueue instead to prod the watchdog?
Then the GPIOs could sleep, you could rewrite them as such, and other things could use them safely.

Disabling IRQs while you talk to an I2C peripheral sounds like a hack that will impact performance.

Although, if it does that then I think your GPIOs qualify as non-sleeping.. so "safe" to use from a can't-sleep context but probably unacceptably slow as you say.

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network




From jy0922.shim at samsung.com  Thu Jun 24 00:35:04 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 24 Jun 2010 13:35:04 +0900
Subject: [PATCH 1/2] ARM: S5PV210: Fix Aquila board UART FIFO mode configration
Message-ID: <1277354105-13097-1-git-send-email-jy0922.shim@samsung.com>

The Aquila board uses max UART FIFO size to each UART channels. UART0
supports 256 bytes FIFO, but Aquila board supports 128 bytes FIFO
because of initial chip bug.

Also, this patch fixes to "s/smdkv210/aquila".

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pv210/mach-aquila.c |   24 +++++++++++++++---------
 1 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 10bc76e..5795a7c 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -39,38 +39,44 @@
 
 #define S5PV210_ULCON_DEFAULT	S3C2410_LCON_CS8
 
-#define S5PV210_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
-				 S5PV210_UFCON_TXTRIG4 |	\
-				 S5PV210_UFCON_RXTRIG4)
+#define S5PV210_UFCON_DEFAULT	S3C2410_UFCON_FIFOMODE
 
-static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
+static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
 	[0] = {
 		.hwport		= 0,
 		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
-		.ufcon		= S5PV210_UFCON_DEFAULT,
+		/*
+		 * Actually UART0 can support 256 bytes fifo, but aquila board
+		 * supports 128 bytes fifo because of initial chip bug
+		 */
+		.ufcon		= S5PV210_UFCON_DEFAULT |
+			S5PV210_UFCON_TXTRIG128 | S5PV210_UFCON_RXTRIG128,
 	},
 	[1] = {
 		.hwport		= 1,
 		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
-		.ufcon		= S5PV210_UFCON_DEFAULT,
+		.ufcon		= S5PV210_UFCON_DEFAULT |
+			S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
 	},
 	[2] = {
 		.hwport		= 2,
 		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
-		.ufcon		= S5PV210_UFCON_DEFAULT,
+		.ufcon		= S5PV210_UFCON_DEFAULT |
+			S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
 	},
 	[3] = {
 		.hwport		= 3,
 		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
-		.ufcon		= S5PV210_UFCON_DEFAULT,
+		.ufcon		= S5PV210_UFCON_DEFAULT |
+			S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
 	},
 };
 
@@ -124,7 +130,7 @@ static void __init aquila_map_io(void)
 {
 	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
 	s3c24xx_init_clocks(24000000);
-	s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
+	s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
 }
 
 static void __init aquila_machine_init(void)
-- 
1.7.0.4



From jy0922.shim at samsung.com  Thu Jun 24 00:35:05 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 24 Jun 2010 13:35:05 +0900
Subject: [PATCH 2/2] ARM: S5PV210: Fix GONI board UART FIFO mode configration
In-Reply-To: <1277354105-13097-1-git-send-email-jy0922.shim@samsung.com>
References: <1277354105-13097-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1277354105-13097-2-git-send-email-jy0922.shim@samsung.com>

The GONI board uses max UART FIFO size to each UART channels.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pv210/mach-goni.c |   16 +++++++++-------
 1 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 4863b13..0cfb8db 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -36,9 +36,7 @@
 
 #define S5PV210_ULCON_DEFAULT	S3C2410_LCON_CS8
 
-#define S5PV210_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
-				 S5PV210_UFCON_TXTRIG4 |	\
-				 S5PV210_UFCON_RXTRIG4)
+#define S5PV210_UFCON_DEFAULT	S3C2410_UFCON_FIFOMODE
 
 static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
 	[0] = {
@@ -46,28 +44,32 @@ static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
 		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
-		.ufcon		= S5PV210_UFCON_DEFAULT,
+		.ufcon		= S5PV210_UFCON_DEFAULT |
+			S5PV210_UFCON_TXTRIG256 | S5PV210_UFCON_RXTRIG256,
 	},
 	[1] = {
 		.hwport		= 1,
 		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
-		.ufcon		= S5PV210_UFCON_DEFAULT,
+		.ufcon		= S5PV210_UFCON_DEFAULT |
+			S5PV210_UFCON_TXTRIG64 | S5PV210_UFCON_RXTRIG64,
 	},
 	[2] = {
 		.hwport		= 2,
 		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
-		.ufcon		= S5PV210_UFCON_DEFAULT,
+		.ufcon		= S5PV210_UFCON_DEFAULT |
+			S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
 	},
 	[3] = {
 		.hwport		= 3,
 		.flags		= 0,
 		.ucon		= S5PV210_UCON_DEFAULT,
 		.ulcon		= S5PV210_ULCON_DEFAULT,
-		.ufcon		= S5PV210_UFCON_DEFAULT,
+		.ufcon		= S5PV210_UFCON_DEFAULT |
+			S5PV210_UFCON_TXTRIG16 | S5PV210_UFCON_RXTRIG16,
 	},
 };
 
-- 
1.7.0.4



From Jon.Povey at racelogic.co.uk  Thu Jun 24 00:46:11 2010
From: Jon.Povey at racelogic.co.uk (Jon Povey)
Date: Thu, 24 Jun 2010 05:46:11 +0100
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and
	sleepinggpios)
In-Reply-To: <4C225CB2.6090407@bluewatersys.com>
Message-ID: <70E876B0EA86DD4BAF101844BC814DFE08E0855B97@Cloud.RL.local>

Ryan Mallon wrote:

> If we strip my patch back to just introducing gpio_request_cansleep,
> which would be used in any driver where all of the calls are
> gpio_(set/get)_cansleep, and make gpio_request only allow non-sleeping
> gpios then incorrect use of gpios would be caught at request time and
> returned to the caller as an error.

It seems like a good idea to catch these at request time. There is support in the API for this already (gpio_cansleep), but driver writers are not steered towards checking and thinking in these ways by the current API or documentation. Perhaps a documentation change with some cut and paste boilerplate would be enough, but I think some API enforcement/encouragement would be helpful.

I think this agrees with you, Ryan:

gpio_request_cansleep would be the same as current gpio_request
gpio_request changes to error if this is a sleepy gpio.

Imagine a situation where GPIOs are being assigned and passed around between drivers in some dynamic way, or some way unpredictable to the driver writer. In development only non-sleeping GPIOs have been seen and everything is fine. One day someone feeds it a GPIO on an I2C expander and the driver crashes.
If gpio_request had this built-in check the driver could gracefuly fail to load instead with an appropriate error message.

--
Jon Povey
jon.povey at racelogic.co.uk

Racelogic is a limited company registered in England. Registered number 2743719 .
Registered Office Unit 10, Swan Business Centre, Osier Way, Buckingham, Bucks, MK18 1TB .

The information contained in this electronic mail transmission is intended by Racelogic Ltd for the use of the named individual or entity to which it is directed and may contain information that is confidential or privileged. If you have received this electronic mail transmission in error, please delete it from your system without copying or forwarding it, and notify the sender of the error by reply email so that the sender's address records can be corrected. The views expressed by the sender of this communication do not necessarily represent those of Racelogic Ltd. Please note that Racelogic reserves the right to monitor e-mail communications passing through its network




From myungjoo.ham at samsung.com  Thu Jun 24 01:18:07 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Thu, 24 Jun 2010 14:18:07 +0900
Subject: [PATCH v4] S5PV210 Correct clock register properties
Message-ID: <1277356687-9500-1-git-send-email-myungjoo.ham@samsung.com>

1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which were
defined incorrectly.

2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc,
sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their
twins defined in struct clk init_clocks_disable[] and struct clk
init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK
register to avoid the duplicated clock problem described below.

--- Duplicated Clock Problem ---
Please note that each clock definition should access different control
register; otherwise, the system may suffer lockups. For example, if we
have two clock definitions "a" and "b" which access the same register
(and the shift value). Then, when we do:

	module A
	clk = clk_get("a");
	clk->clk_enable(clk);

	module B (context switch)
	clk = clk_get("b");
	clk->clk_enable(clk);
	do something with clk.
	clk->clk_disable(clk);

	module A (context switch)
	do something with clk
	* At this point, the system may hang.

Therefore, there should be no clock definitions with the same contol
register/shift. If we need to create "aliases", then, creating child
clocks sharing the clock should be fine.

3. Corrected other sclk_* shift values and access registers.


Note that becuase UART clocks are properly disabled at boot time with
this patch, UART drivers or somebody else should turn on the clock
to read the console; otherwise, JIG willl not show any message.


Note that this patch revises and merges the two previous patches:
[PATCH] S5PV210 Correct clock register properties
[PATCH] S5PV210 Correct clock source control register properties
And follows the previous patch
[PATCH v2] S5PV210 Correct clock register properties
[PATCH v3] S5PV210 Correct clock register properties


Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pv210/clock.c |  115 ++++++++++++++++++++++-------------------
 1 files changed, 62 insertions(+), 53 deletions(-)

diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 154bca4..b3d156c 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -183,6 +183,11 @@ static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 }
 
+static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
+}
+
 static struct clk clk_sclk_hdmi27m = {
 	.name		= "sclk_hdmi27m",
 	.id		= -1,
@@ -406,14 +411,14 @@ static struct clk init_clocks_disable[] = {
 		.id		= 0,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1 << 5),
 	}, {
 		.name		= "i2s_v32",
 		.id		= 1,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
-	}
+		.ctrlbit	= (1 << 6),
+	},
 };
 
 static struct clk init_clocks[] = {
@@ -429,25 +434,25 @@ static struct clk init_clocks[] = {
 		.id		= 0,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<7),
+		.ctrlbit	= (1 << 17),
 	}, {
 		.name		= "uart",
 		.id		= 1,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<8),
+		.ctrlbit	= (1 << 18),
 	}, {
 		.name		= "uart",
 		.id		= 2,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<9),
+		.ctrlbit	= (1 << 19),
 	}, {
 		.name		= "uart",
 		.id		= 3,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<10),
+		.ctrlbit	= (1 << 20),
 	},
 };
 
@@ -497,8 +502,8 @@ static struct clksrc_clk clk_sclk_dac = {
 	.clk		= {
 		.name		= "sclk_dac",
 		.id		= -1,
-		.ctrlbit	= (1 << 10),
-		.enable		= s5pv210_clk_ip1_ctrl,
+		.ctrlbit	= (1 << 2),
+		.enable		= s5pv210_clk_mask0_ctrl,
 	},
 	.sources	= &clkset_sclk_dac,
 	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
@@ -527,8 +532,8 @@ static struct clksrc_clk clk_sclk_hdmi = {
 	.clk		= {
 		.name		= "sclk_hdmi",
 		.id		= -1,
-		.enable		= s5pv210_clk_ip1_ctrl,
-		.ctrlbit	= (1 << 11),
+		.ctrlbit	= (1 << 0),
+		.enable		= s5pv210_clk_mask0_ctrl,
 	},
 	.sources	= &clkset_sclk_hdmi,
 	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
@@ -565,8 +570,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 0,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 4),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 24),
 	},
 	.sources = &clkset_sclk_audio0,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
@@ -594,8 +599,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 1,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 5),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 25),
 	},
 	.sources = &clkset_sclk_audio1,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
@@ -623,8 +628,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 2,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 6),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 26),
 	},
 	.sources = &clkset_sclk_audio2,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
@@ -680,8 +685,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "uclk1",
 			.id		= 0,
-			.ctrlbit	= (1<<17),
-			.enable		= s5pv210_clk_ip3_ctrl,
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 12),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
@@ -690,8 +695,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 18),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 13),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
@@ -700,8 +705,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 19),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 14),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
@@ -710,8 +715,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 3,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 20),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 15),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
@@ -720,8 +725,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_mixer",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip1_ctrl,
-			.ctrlbit	= (1 << 9),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 1),
 		},
 		.sources = &clkset_sclk_mixer,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
@@ -738,8 +743,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_fimc",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 24),
+			.enable		= s5pv210_clk_mask1_ctrl,
+			.ctrlbit	= (1 << 2),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
@@ -748,8 +753,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_fimc",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 25),
+			.enable		= s5pv210_clk_mask1_ctrl,
+			.ctrlbit	= (1 << 3),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
@@ -758,8 +763,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_fimc",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 26),
+			.enable		= s5pv210_clk_mask1_ctrl,
+			.ctrlbit	= (1 << 4),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
@@ -768,6 +773,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_cam",
 			.id		= 0,
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 3),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
@@ -776,6 +783,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_cam",
 			.id		= 1,
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 4),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
@@ -784,8 +793,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_fimd",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip1_ctrl,
-			.ctrlbit	= (1 << 0),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 5),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
@@ -794,8 +803,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 16),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 8),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
@@ -804,8 +813,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 17),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 9),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
@@ -814,8 +823,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 18),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 10),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
@@ -824,8 +833,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 3,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 19),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 11),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
@@ -864,8 +873,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_csis",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 31),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 6),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
@@ -874,8 +883,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_spi",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 12),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 16),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
@@ -884,8 +893,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_spi",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 13),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 17),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
@@ -894,8 +903,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_pwi",
 			.id		= -1,
-			.enable		= &s5pv210_clk_ip4_ctrl,
-			.ctrlbit	= (1 << 2),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 29),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
@@ -904,8 +913,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_pwm",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 23),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 19),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
-- 
1.6.3.3



From jy0922.shim at samsung.com  Thu Jun 24 01:38:59 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Thu, 24 Jun 2010 14:38:59 +0900
Subject: [PATCH v4] S5PV210 Correct clock register properties
In-Reply-To: <1277356687-9500-1-git-send-email-myungjoo.ham@samsung.com>
References: <1277356687-9500-1-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <4C22EF73.8030108@samsung.com>

Hi,

On 6/24/2010 2:18 PM, MyungJoo Ham wrote:
> 1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which were
> defined incorrectly.
> 
> 2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc,
> sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their
> twins defined in struct clk init_clocks_disable[] and struct clk
> init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK
> register to avoid the duplicated clock problem described below.
> 
> --- Duplicated Clock Problem ---
> Please note that each clock definition should access different control
> register; otherwise, the system may suffer lockups. For example, if we
> have two clock definitions "a" and "b" which access the same register
> (and the shift value). Then, when we do:
> 
> 	module A
> 	clk = clk_get("a");
> 	clk->clk_enable(clk);
> 
> 	module B (context switch)
> 	clk = clk_get("b");
> 	clk->clk_enable(clk);
> 	do something with clk.
> 	clk->clk_disable(clk);
> 
> 	module A (context switch)
> 	do something with clk
> 	* At this point, the system may hang.
> 
> Therefore, there should be no clock definitions with the same contol
> register/shift. If we need to create "aliases", then, creating child
> clocks sharing the clock should be fine.
> 
> 3. Corrected other sclk_* shift values and access registers.
> 
> 
> Note that becuase UART clocks are properly disabled at boot time with
> this patch, UART drivers or somebody else should turn on the clock
> to read the console; otherwise, JIG willl not show any message.
> 
> 
> Note that this patch revises and merges the two previous patches:
> [PATCH] S5PV210 Correct clock register properties
> [PATCH] S5PV210 Correct clock source control register properties
> And follows the previous patch
> [PATCH v2] S5PV210 Correct clock register properties
> [PATCH v3] S5PV210 Correct clock register properties
> 

The history about patch is better to go to below --- line. The contents 
of below --- line aren't included to commit message at the git.

> 
> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---

Here.

>  arch/arm/mach-s5pv210/clock.c |  115 ++++++++++++++++++++++-------------------
>  1 files changed, 62 insertions(+), 53 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> index 154bca4..b3d156c 100644
> --- a/arch/arm/mach-s5pv210/clock.c
> +++ b/arch/arm/mach-s5pv210/clock.c
> @@ -183,6 +183,11 @@ static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
>  	return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
>  }
>  
> +static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
> +{
> +	return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
> +}
> +
>  static struct clk clk_sclk_hdmi27m = {
>  	.name		= "sclk_hdmi27m",
>  	.id		= -1,
> @@ -406,14 +411,14 @@ static struct clk init_clocks_disable[] = {
>  		.id		= 0,
>  		.parent		= &clk_p,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<4),
> +		.ctrlbit	= (1 << 5),
>  	}, {
>  		.name		= "i2s_v32",
>  		.id		= 1,
>  		.parent		= &clk_p,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<4),
> -	}
> +		.ctrlbit	= (1 << 6),
> +	},
>  };
>  
>  static struct clk init_clocks[] = {
> @@ -429,25 +434,25 @@ static struct clk init_clocks[] = {
>  		.id		= 0,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<7),
> +		.ctrlbit	= (1 << 17),
>  	}, {
>  		.name		= "uart",
>  		.id		= 1,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<8),
> +		.ctrlbit	= (1 << 18),
>  	}, {
>  		.name		= "uart",
>  		.id		= 2,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<9),
> +		.ctrlbit	= (1 << 19),
>  	}, {
>  		.name		= "uart",
>  		.id		= 3,
>  		.parent		= &clk_pclk_psys.clk,
>  		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1<<10),
> +		.ctrlbit	= (1 << 20),
>  	},
>  };
>  
> @@ -497,8 +502,8 @@ static struct clksrc_clk clk_sclk_dac = {
>  	.clk		= {
>  		.name		= "sclk_dac",
>  		.id		= -1,
> -		.ctrlbit	= (1 << 10),
> -		.enable		= s5pv210_clk_ip1_ctrl,
> +		.ctrlbit	= (1 << 2),
> +		.enable		= s5pv210_clk_mask0_ctrl,
>  	},
>  	.sources	= &clkset_sclk_dac,
>  	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
> @@ -527,8 +532,8 @@ static struct clksrc_clk clk_sclk_hdmi = {
>  	.clk		= {
>  		.name		= "sclk_hdmi",
>  		.id		= -1,
> -		.enable		= s5pv210_clk_ip1_ctrl,
> -		.ctrlbit	= (1 << 11),
> +		.ctrlbit	= (1 << 0),
> +		.enable		= s5pv210_clk_mask0_ctrl,
>  	},
>  	.sources	= &clkset_sclk_hdmi,
>  	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
> @@ -565,8 +570,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
>  	.clk		= {
>  		.name		= "sclk_audio",
>  		.id		= 0,
> -		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1 << 4),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 24),
>  	},
>  	.sources = &clkset_sclk_audio0,
>  	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
> @@ -594,8 +599,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
>  	.clk		= {
>  		.name		= "sclk_audio",
>  		.id		= 1,
> -		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1 << 5),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 25),
>  	},
>  	.sources = &clkset_sclk_audio1,
>  	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
> @@ -623,8 +628,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
>  	.clk		= {
>  		.name		= "sclk_audio",
>  		.id		= 2,
> -		.enable		= s5pv210_clk_ip3_ctrl,
> -		.ctrlbit	= (1 << 6),
> +		.enable		= s5pv210_clk_mask0_ctrl,
> +		.ctrlbit	= (1 << 26),
>  	},
>  	.sources = &clkset_sclk_audio2,
>  	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
> @@ -680,8 +685,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "uclk1",
>  			.id		= 0,
> -			.ctrlbit	= (1<<17),
> -			.enable		= s5pv210_clk_ip3_ctrl,
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 12),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
> @@ -690,8 +695,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "uclk1",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 18),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 13),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
> @@ -700,8 +705,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "uclk1",
>  			.id		= 2,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 19),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 14),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
> @@ -710,8 +715,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "uclk1",
>  			.id		= 3,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 20),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 15),
>  		},
>  		.sources = &clkset_uart,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
> @@ -720,8 +725,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "sclk_mixer",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip1_ctrl,
> -			.ctrlbit	= (1 << 9),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 1),
>  		},
>  		.sources = &clkset_sclk_mixer,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
> @@ -738,8 +743,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "sclk_fimc",
>  			.id		= 0,
> -			.enable		= s5pv210_clk_ip0_ctrl,
> -			.ctrlbit	= (1 << 24),
> +			.enable		= s5pv210_clk_mask1_ctrl,
> +			.ctrlbit	= (1 << 2),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
> @@ -748,8 +753,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "sclk_fimc",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip0_ctrl,
> -			.ctrlbit	= (1 << 25),
> +			.enable		= s5pv210_clk_mask1_ctrl,
> +			.ctrlbit	= (1 << 3),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
> @@ -758,8 +763,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk	= {
>  			.name		= "sclk_fimc",
>  			.id		= 2,
> -			.enable		= s5pv210_clk_ip0_ctrl,
> -			.ctrlbit	= (1 << 26),
> +			.enable		= s5pv210_clk_mask1_ctrl,
> +			.ctrlbit	= (1 << 4),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
> @@ -768,6 +773,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_cam",
>  			.id		= 0,
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 3),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
> @@ -776,6 +783,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_cam",
>  			.id		= 1,
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 4),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
> @@ -784,8 +793,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_fimd",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip1_ctrl,
> -			.ctrlbit	= (1 << 0),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 5),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
> @@ -794,8 +803,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 0,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 16),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 8),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
> @@ -804,8 +813,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 17),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 9),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
> @@ -814,8 +823,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 2,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 18),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 10),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
> @@ -824,8 +833,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_mmc",
>  			.id		= 3,
> -			.enable		= s5pv210_clk_ip2_ctrl,
> -			.ctrlbit	= (1 << 19),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 11),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
> @@ -864,8 +873,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_csis",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip0_ctrl,
> -			.ctrlbit	= (1 << 31),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 6),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
> @@ -874,8 +883,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_spi",
>  			.id		= 0,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 12),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 16),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
> @@ -884,8 +893,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_spi",
>  			.id		= 1,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 13),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 17),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
> @@ -894,8 +903,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_pwi",
>  			.id		= -1,
> -			.enable		= &s5pv210_clk_ip4_ctrl,
> -			.ctrlbit	= (1 << 2),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 29),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
> @@ -904,8 +913,8 @@ static struct clksrc_clk clksrcs[] = {
>  		.clk		= {
>  			.name		= "sclk_pwm",
>  			.id		= -1,
> -			.enable		= s5pv210_clk_ip3_ctrl,
> -			.ctrlbit	= (1 << 23),
> +			.enable		= s5pv210_clk_mask0_ctrl,
> +			.ctrlbit	= (1 << 19),
>  		},
>  		.sources = &clkset_group2,
>  		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },



From m.szyprowski at samsung.com  Thu Jun 24 01:52:16 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Thu, 24 Jun 2010 07:52:16 +0200
Subject: Samsung SoCs: preparation for single kernel
In-Reply-To: <AANLkTimqQyHLm4KcxYwYC8slSoy9udi2gganKdsD_8Nw@mail.gmail.com>
References: <AANLkTinGwWzIAOe2tj6V2kCrMiPT7PHlYs1kFS-IsiN4@mail.gmail.com>
	<AANLkTil-AOEqhMOXydaiA1X_v0rjoNQxALrO0UY638AS@mail.gmail.com>
	<AANLkTil1i_ZGI8bY14HhjrAk9RooVreAJsTteqqrMgqJ@mail.gmail.com>
	<AANLkTikDml6gQAsiRrCjIt4bUD3hnpAATr1erqCGOJMd@mail.gmail.com>
	<002301cb129c$ec59fe30$c50dfa90$%szyprowski@samsung.com>
	<AANLkTikspf9zHuSKe86wDQxI12HpJo_occBlLUXBkjef@mail.gmail.com>
	<003e01cb12b5$656c0670$30441350$%szyprowski@samsung.com>
	<AANLkTimqQyHLm4KcxYwYC8slSoy9udi2gganKdsD_8Nw@mail.gmail.com>
Message-ID: <002d01cb1361$69372c10$3ba58430$%szyprowski@samsung.com>

Hello,

On Thursday, June 24, 2010 4:08 AM Kyungmin Park wrote:

> On Wed, Jun 23, 2010 at 6:20 PM, Marek Szyprowski
> <m.szyprowski at samsung.com> wrote:
> > Hello,
> >
> > On Wednesday, June 23, 2010 10:02 AM Eric Miao wrote:
> >
> >> >> Now you have
> >> >>
> >> >> s5pv210_device_hsmmc0
> >> >> s5pc100_device_hsmmc0
> >> >> s3c64xx_device_hsmmc0
> >> >> ....
> >> >>
> >> >> each with a different base.
> >> >
> >> > There is no need for such code duplication.
> >>
> >> However, I believe this is the right way to go. A certain level of
> >> duplication is the price to pay for a generic and clean solution.
> >>
> >> When a peripheral controller or IP is moved from one SoC to the
> >> next generation, there are several things could have been changed:
> >>
> >> 1. new base address and IRQ number
> >> 2. fixes and enhancements to the original IP
> >>
> >> 1. will result in a different 'struct resource', and 2. will result in a
> >> different 'struct platform_device' with a different name, so the driver
> >> can match the platform_device_id table as you agreed I'm right on
> >> that recommendation.
> >>
> >> They are actually _two_ different devices.
> >
> > Right, they are separate entities, but would be really good if a similar
> > git brcode could be merged together.
> >
> >> > Ben is working on a solution for
> >> > a single kernel which supports multiple SoCs. Some of his work in
> >> progress can
> >> > be found here: git://git.fluff.org/bjdooks/linux branch wip-samsung-
> dev
> >> and
> >> > wip-samsung-dev2.
> >>
> >> Could you describe it a bit here and bring it on table for discussion?
> >
> > The idea behind his patches is to provide a table for each SoC with short
> > description of all available devices and generate platform_device entries
> > dynamically from that table.
> >
> > Here is a short code example:
> >
> > struct s3c_pdev_table s3c6xxx_dev_table[] __initdata = {
> > ? ? ? ?{
> > ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_UART,
> > ? ? ? ? ? ? ? ?.name ? = "s3c6400-uart",
> > ? ? ? ? ? ? ? ?.index ?= 0,
> > ? ? ? ? ? ? ? ?.base ? = S3C_PA_UART0,
> > ? ? ? ? ? ? ? ?.irq ? ?= IRQ_S3CUART_RX0,
> > ? ? ? ? ? ? ? ?.template = &template_uart_s3c64xx,
> > ? ? ? ?}, {
> > ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_UART,
> > ? ? ? ? ? ? ? ?.name ? = "s3c6400-uart",
> > ? ? ? ? ? ? ? ?.index ?= 1,
> > ? ? ? ? ? ? ? ?.base ? = S3C_PA_UART1,
> > ? ? ? ? ? ? ? ?.irq ? ?= IRQ_S3CUART_RX1,
> > ? ? ? ? ? ? ? ?.template = &template_uart_s3c64xx,
> > ? ? ? ?}, {
> > ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_UART,
> > ? ? ? ? ? ? ? ?.name ? = "s3c6400-uart",
> > ? ? ? ? ? ? ? ?.index ?= 2,
> > ? ? ? ? ? ? ? ?.base ? = S3C_PA_UART2,
> > ? ? ? ? ? ? ? ?.irq ? ?= IRQ_S3CUART_RX2,
> > ? ? ? ? ? ? ? ?.template = &template_uart_s3c64xx,
> > ? ? ? ?}, {
> > ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_UART,
> > ? ? ? ? ? ? ? ?.name ? = "s3c6400-uart",
> > ? ? ? ? ? ? ? ?.index ?= 3,
> > ? ? ? ? ? ? ? ?.base ? = S3C_PA_UART3,
> > ? ? ? ? ? ? ? ?.irq ? ?= IRQ_S3CUART_RX3,
> > ? ? ? ? ? ? ? ?.template = &template_uart_s3c64xx,
> > ? ? ? ?}, {
> > ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_WATCHDOG,
> > ? ? ? ? ? ? ? ?.name ? = "s3c2410-wdt",
> > ? ? ? ? ? ? ? ?.index ?= -1,
> > ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_WATCHDOG,
> > ? ? ? ? ? ? ? ?.irq ? ?= IRQ_WDT,
> > ? ? ? ?}, {
> > ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_SDHCI,
> > ? ? ? ? ? ? ? ?.name ? = "s3c-sdhci",
> > ? ? ? ? ? ? ? ?.index ?= 0,
> > ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_HSMMC0 ,
> > ? ? ? ? ? ? ? ?.irq ? ?= IRQ_HSMMC0,
> > ? ? ? ? ? ? ? ?.dma ? ?= &samsung_std_dma_mask,
> > ? ? ? ?}, {
> > ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_SDHCI,
> > ? ? ? ? ? ? ? ?.name ? = "s3c-sdhci",
> > ? ? ? ? ? ? ? ?.index ?= 1,
> > ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_HSMMC1,
> > ? ? ? ? ? ? ? ?.irq ? ?= IRQ_HSMMC1,
> > ? ? ? ? ? ? ? ?.dma ? ?= &samsung_std_dma_mask,
> > ? ? ? ?}, {
> > ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_SDHCI,
> > ? ? ? ? ? ? ? ?.name ? = "s3c-sdhci",
> > ? ? ? ? ? ? ? ?.index ?= 2,
> > ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_HSMMC2,
> > ? ? ? ? ? ? ? ?.irq ? ?= IRQ_HSMMC1,
> > ? ? ? ? ? ? ? ?.dma ? ?= &samsung_std_dma_mask,
> > ? ? ? ?}, {
> > ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_OHCI,
> > ? ? ? ? ? ? ? ?.name ? = "s3c2410-ohci",
> > ? ? ? ? ? ? ? ?.index ?= -1,
> > ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_USBHOST,
> > ? ? ? ? ? ? ? ?.irq ? ?= IRQ_USBH,
> > ? ? ? ? ? ? ? ?.dma ? ?= &samsung_std_dma_mask,
> > ? ? ? ?}, {
> > ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_NAND,
> > ? ? ? ? ? ? ? ?.name ? = "s3c6400-nand",
> > ? ? ? ? ? ? ? ?.index ?= -1,
> > ? ? ? ? ? ? ? ?.base ? = 0x4E000000,
> > ? ? ? ? ? ? ? ?.irq ? ?= IRQ_NFC,
> > ? ? ? ?}, {
> > ? ? ? ? ? ? ? ?.type ? = SAMSUNG_DEVICE_I2C,
> > ? ? ? ? ? ? ? ?.name ? = "s3c2440-i2c",
> > ? ? ? ? ? ? ? ?.index ?= 0,
> > ? ? ? ? ? ? ? ?.base ? = S3C64XX_PA_IIC0,
> > ? ? ? ? ? ? ? ?.irq ? ?= IRQ_IIC,
> > ? ? ? ?}, {
> > ...
> >
> > This solution is imho really clean an easy to understand. It is also
> > easy to check which SoC has which peripherals defined and how.
> 
> Question. recently it's changed to use MMC0, MMC2, MMC3, then how to define
> it?

There is index parameter that defines the instance of the device.

> More basically, where these info are defined for chip or board?

The above table is defined per SoC. Each board then registers the particular
devices like it is done in the current kernels. The following diff should
explain it better:

-static struct platform_device *smdk6400_devices[] __initdata = {
-	&s3c_device_hsmmc1,
-	&s3c_device_i2c0,
+static struct s3c_devtable  smdk6400_devtable[] __initdata = {
+	{ .type = SAMSUNG_DEVICE_SDHCI,	.index = 1, },
+	{ .type = SAMSUNG_DEVICE_I2C,	.index = 0, },

static void __init smdk6400_machine_init(void)
 {
 	i2c_register_board_info(0, i2c_devs, ARRAY_SIZE(i2c_devs));
-	platform_add_devices(smdk6400_devices, ARRAY_SIZE(smdk6400_devices));
+	samsung_add_devices(smdk6400_devtable, ARRAY_SIZE(smdk6400_devtable));
 }

> If chip, the how to handle several variants?

The same way it is handled in the current kernels. Machine init code can
even do some additional fixups if required.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center




From paul at pwsan.com  Thu Jun 24 02:30:37 2010
From: paul at pwsan.com (Paul Walmsley)
Date: Thu, 24 Jun 2010 00:30:37 -0600 (MDT)
Subject: [PATCH 2/3] OMAP: PM: use omap_device API for suspend/resume
In-Reply-To: <1277336224-24826-3-git-send-email-khilman@deeprootsystems.com>
References: <1277336224-24826-1-git-send-email-khilman@deeprootsystems.com>
	<1277336224-24826-3-git-send-email-khilman@deeprootsystems.com>
Message-ID: <alpine.DEB.2.00.1006232128390.1550@utopia.booyaka.com>

Hi Kevin,

aside from these comments:

   http://marc.info/?l=linux-omap&m=127735008820992&w=2

one other minor issue -

On Wed, 23 Jun 2010, Kevin Hilman wrote:

> Hook into the platform bus methods for suspend and resume and
> use the omap_device API to automatically idle and enable the
> device on suspend and resume.
> 
> This allows device drivers to get rid of direct management of their
> clocks in their suspend/resume paths, and let omap_device do it for
> them.
> 
> We currently use the _noirq (late suspend, early resume) versions of
> the suspend/resume methods to ensure that the device is not disabled
> too early for any drivers also using the _noirq methods.
> 
> NOTE: only works for devices with omap_hwmod support.
> 
> Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
> ---
>  arch/arm/mach-omap2/pm_bus.c |   61 ++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 61 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
> index 69acaa5..3787da8 100644
> --- a/arch/arm/mach-omap2/pm_bus.c
> +++ b/arch/arm/mach-omap2/pm_bus.c
> @@ -70,3 +70,64 @@ int platform_pm_runtime_idle(struct device *dev)
>  };
>  #endif /* CONFIG_PM_RUNTIME */
>  
> +#ifdef CONFIG_SUSPEND
> +int platform_pm_suspend_noirq(struct device *dev)
> +{
> +	struct device_driver *drv = dev->driver;
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct omap_device *odev = to_omap_device(pdev);
> +	int ret = 0;
> +
> +	if (!drv)
> +		return 0;
> +
> +	if (drv->pm) {
> +		if (drv->pm->suspend_noirq)
> +			ret = drv->pm->suspend_noirq(dev);
> +	}
> +
> +	if (omap_device_is_valid(odev)) {
> +		if (odev->flags & OMAP_DEVICE_NO_BUS_SUSPEND) {
> +			dev_dbg(dev, "no automatic bus-level system resume.\n");

I guess this should read "suspend" above?

> +			return 0;
> +		}
> +
> +		dev_dbg(dev, "%s\n", __func__);
> +		omap_device_idle(pdev);
> +	} else {
> +		dev_dbg(dev, "not an omap_device\n");
> +	}
> +
> +	return ret;
> +}
> +
> +int platform_pm_resume_noirq(struct device *dev)
> +{
> +	struct device_driver *drv = dev->driver;
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct omap_device *odev = to_omap_device(pdev);
> +	int ret = 0;
> +
> +	if (omap_device_is_valid(odev)) {
> +		if (odev->flags & OMAP_DEVICE_NO_BUS_SUSPEND) {
> +			dev_dbg(dev, "no automatic bus-level system resume.\n");
> +			return 0;
> +		}
> +
> +		dev_dbg(dev, "%s\n", __func__);
> +		omap_device_enable(pdev);
> +	} else {
> +		dev_dbg(dev, "not an omap_device\n");
> +	}
> +
> +	if (!drv)
> +		return 0;
> +
> +	if (drv->pm) {
> +		if (drv->pm->resume_noirq)
> +			ret = drv->pm->resume_noirq(dev);
> +	}
> +
> +	return ret;
> +}
> +#endif /* CONFIG_SUSPEND */
> -- 
> 1.7.0.2
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> 


- Paul


From u.kleine-koenig at pengutronix.de  Thu Jun 24 02:41:27 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 24 Jun 2010 08:41:27 +0200
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping
	gpios)
In-Reply-To: <4C225CB2.6090407@bluewatersys.com>
References: <728731.73469.qm@web180307.mail.gq1.yahoo.com>
	<4C225CB2.6090407@bluewatersys.com>
Message-ID: <20100624064127.GA23539@pengutronix.de>

Hello,

On Thu, Jun 24, 2010 at 07:12:50AM +1200, Ryan Mallon wrote:
> David Brownell wrote:
> > 
> > --- On Tue, 6/22/10, Ryan Mallon <ryan at bluewatersys.com> wrote:
> > 
> >>> --- On Tue, 6/22/10, Ryan Mallon <ryan at bluewatersys.com>
> >> wrote:
> 
> >>>> 'Can sleep' for a gpio has two different meanings
> >> depending
> >>>> on context
> >>> NO; for the GPIO itself it's only ever had one
> >>> meaning, regardless of context.
> >>>
> >>> You're trying to conflate the GPIO and one
> >>> of the contexts in which it's used.  That's
> >>> the problem you seem to be struggling with.
> >>>
> >>> Please stop conflating/confusing
> >>> those two disparate concepts...
> >> I'm not. 
> > 
> > BUT Your "counter" example below is solid
> > proof that you are:  it shows exactly the
> > confusion I pointed out:  call context versus
> > the GPIO itself.  There's no way I can read
> > that as anything except "you are"...
> > 
> >  
> > Your intent here seems perhaps more to
> > be a troll than to address any real
> > technical issues.  I don't see much
> > point participating any further.
> > 
> > 
> >  Some gpios, such as those on io expanders, may
> >> sleep in their
> >> implementations of the gpio_(set/get) functions.
> >>
> > 
> > Such GPIOs have a "cansleep" attribute, in short.
> > 
> > 
> >> Drivers, which use a gpio, may call gpio_(set/get)
> >> functions for a given
> >> gpio from a context where it is not safe to sleep.
> > 
> > And that's the call dontext
> > (in this case, from a driver).
> 
> Yes.
> 
> >   QED.  You are confusing two disparate concepts.
> 
> We are saying exactly the same thing.
> 
> > 
> >  In this
> >> case, a gpio
> >> which may sleep (ie one on an i2c io-expander) cannot be
> >> used with this
> >> driver. The gpio_request will succeed, but any call to
> >> gpio_(set/get)_value will produce a warning.
> >>
> >>>> example, if a driver calls gpio_get_value(gpio)
> >> from an
> >>>> interupt handler
> > 
> > 
> > (YOU introduce interrupt/IRQ handlers...)
> > 
> >>>> then the gpio must not be a sleeping gpio.
> >>> In a threaded IRQ handler it's OK to use
> >>> the get_value_cansleep() option..
> >> Ugh, you are really twisting my words.
> > 
> > 
> > You said IRQ handler, so did I.  In what csense could I
> > possibly be "twisting" your words"???
> > 
> > 
> > STOP TROLLING.
> 
> Okay, I messed up the wording an used 'interrupt handler' as an example
> of a non-sleep safe context. If I had said 'atomic' or 'spinlock'
> context you would probably be telling me off for missing some other
> non-sleep safe contexts.
> 
> The point is that we are discussing the issue of calls which may sleep.
> Even if I was not entirely clear by getting the wording wrong, you _do_
> know what I am talking about. You could correct on the bits on I get
> wrong instead of labeling me a troll.
> 
> If we strip my patch back to just introducing gpio_request_cansleep,
> which would be used in any driver where all of the calls are
> gpio_(set/get)_cansleep, and make gpio_request only allow non-sleeping
> gpios then incorrect use of gpios would be caught at request time and
> returned to the caller as an error.
I'm not sure that changing the API in this way is sensible.  I'd do
either what Jani Nikula suggested (i.e. substitute some WARN_ON(extra_checks
&& chip->can_sleep); by might_sleep_if(chip->can_sleep);) or
alternatively let gpio_get_value et al. return < 0 if they are called in
atomic context with chip->can_sleep != 0.  Maybe even return < 0
independant of the current context?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From s.hauer at pengutronix.de  Thu Jun 24 03:27:32 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 24 Jun 2010 09:27:32 +0200
Subject: [PATCHv3 4/5] mtd: mxc_nand fixups
In-Reply-To: <80lja6awlb.fsf@merkur.tec.linutronix.de>
References: <20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
	<AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
	<80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTikRj_dMkKLyFhW78yld9jIYAIFncfPaPAF8WqUY@mail.gmail.com>
	<80iq5bqd07.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTimJKNEwOoKldq4a4_ufxNY6IY7r6tAfAM055hlW@mail.gmail.com>
	<80vd9ab0d2.fsf@merkur.tec.linutronix.de>
	<AANLkTinVaXjCneg-XpxB7YNlmGOwQFTnm5RUcetPdToI@mail.gmail.com>
	<80lja6awlb.fsf@merkur.tec.linutronix.de>
Message-ID: <20100624072732.GQ12115@pengutronix.de>

On Wed, Jun 23, 2010 at 12:10:08PM +0200, John Ogness wrote:
> On 2010-06-23, Ivo Clarysse <ivo.clarysse at gmail.com> wrote:
> > But is it OK to use a regular (non-volatile) variable to communicate
> > between interrupt context and the non-interrupt context ?
> 
> In this case, yes.
> 
> > My original patch for i.MX21 used completions instead:
> >
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2010-April/012694.html
> 
> Ah. It seems you've been through all this before. I wish I had noticed
> that thread before. I will need to check more carefully in the future.
> 
> Yes, your original patch achieves the exact same thing. Whether we use
> wait_event() with a flag or wait_completion() really is the same
> thing. So I guess Sascha can decide what we should do there.
> 
> What I like about your original patch is that only the i.MX21 has the
> cost of constantly enabling/disabling the irq line. It adds 5
> cpu_is_mx21() blocks to the code, but will lead to less work for the CPU
> on non-i.MX21 boards.

Ok, if it's the only way out to have 5 cpu_is_* blocks, then lets go for
it.

BTW I observed that at least on i.MX27 the latencies introduced by
waiting for an interrupt cause a significant performance drop. The
driver gets much faster when we just poll all the time. I don't know how
this affects system performance otherwise, but it may be a possibility
to drop interrupt support at least for i.MX21. I have no idea how long
the longest possible time we'd have to poll is though.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From s.hauer at pengutronix.de  Thu Jun 24 03:35:44 2010
From: s.hauer at pengutronix.de (Sascha Hauer)
Date: Thu, 24 Jun 2010 09:35:44 +0200
Subject: [PATCH 0/2] mx25: add iomux defines
In-Reply-To: <cover.1277288487.git.baruch@tkos.co.il>
References: <cover.1277288487.git.baruch@tkos.co.il>
Message-ID: <20100624073544.GR12115@pengutronix.de>

On Wed, Jun 23, 2010 at 01:31:25PM +0300, Baruch Siach wrote:
> This series adds some iomux defines needed for the UART4 and the PWM4 devices.
> 
> Baruch Siach (2):
>   mx25: add iomux defines for UART4 on KPP pins
>   mx25: add PWM4 to iomux

Ok, can you please rebase onto
git://git.pengutronix.de/git/imx/linux-2.6.git imx-for-2.6.36?

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |


From baruch at tkos.co.il  Thu Jun 24 03:40:07 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Thu, 24 Jun 2010 10:40:07 +0300
Subject: [PATCH 0/2] mx25: add iomux defines
In-Reply-To: <20100624073544.GR12115@pengutronix.de>
References: <cover.1277288487.git.baruch@tkos.co.il>
	<20100624073544.GR12115@pengutronix.de>
Message-ID: <20100624074003.GC27906@jasper.tkos.co.il>

Hi Sascha,

On Thu, Jun 24, 2010 at 09:35:44AM +0200, Sascha Hauer wrote:
> On Wed, Jun 23, 2010 at 01:31:25PM +0300, Baruch Siach wrote:
> > This series adds some iomux defines needed for the UART4 and the PWM4 devices.
> > 
> > Baruch Siach (2):
> >   mx25: add iomux defines for UART4 on KPP pins
> >   mx25: add PWM4 to iomux
> 
> Ok, can you please rebase onto
> git://git.pengutronix.de/git/imx/linux-2.6.git imx-for-2.6.36?

OK. I'll send a rebased version later today.

baruch

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From igawa at mxs.nes.nec.co.jp  Thu Jun 24 03:33:56 2010
From: igawa at mxs.nes.nec.co.jp (Masayuki Igawa)
Date: Thu, 24 Jun 2010 16:33:56 +0900
Subject: [PATCH 3/3] add ARM crashdump support
In-Reply-To: <b567a76e7f4502ccd56f818ebd3d6509ebd4a96d.1277188128.git.ext-mika.1.westerberg@nokia.com>
References: <cover.1277188127.git.ext-mika.1.westerberg@nokia.com>
	<b567a76e7f4502ccd56f818ebd3d6509ebd4a96d.1277188128.git.ext-mika.1.westerberg@nokia.com>
Message-ID: <20100624163356.dbb849bc.igawa@mxs.nes.nec.co.jp>

Hi, Mika.

On Tue, 22 Jun 2010 09:59:12 +0300, Mika Westerberg wrote:
> This patch adds support for processing ARM kernel crashdumps as well.
> 
> Signed-off-by: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
> ---
>  Makefile       |    4 +-
>  arm.c          |  200 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  makedumpfile.h |   33 +++++++++
>  3 files changed, 235 insertions(+), 2 deletions(-)
>  create mode 100644 arm.c
> 
> diff --git a/Makefile b/Makefile
> index 4a8a060..3d2ee34 100644
> --- a/Makefile
> +++ b/Makefile
> @@ -23,8 +23,8 @@ CFLAGS_ARCH += -m64
>  endif
>  
>  SRC	= makedumpfile.c makedumpfile.h diskdump_mod.h
> -SRC_ARCH = x86.c x86_64.c ia64.c ppc64.c
> -OBJ_ARCH = x86.o x86_64.o ia64.o ppc64.o
> +SRC_ARCH = arm.c x86.c x86_64.c ia64.c ppc64.c
> +OBJ_ARCH = arm.o x86.o x86_64.o ia64.o ppc64.o
>  
>  all: makedumpfile
>  
> diff --git a/arm.c b/arm.c
> new file mode 100644
> index 0000000..5acad78
> --- /dev/null
> +++ b/arm.c
> @@ -0,0 +1,200 @@
> +/*
> + * arm.c
> + *
> + * Created by: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
> + * Copyright (C) 2010 Nokia Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#ifdef __arm__
> +
> +#include "makedumpfile.h"
> +
> +#define PMD_TYPE_MASK	3
> +#define PMD_TYPE_SECT	2
> +#define PMD_TYPE_TABLE	1
> +
> +#define pgd_index(vaddr) ((vaddr) >> PGDIR_SHIFT)
> +#define pte_index(vaddr) ((vaddr >> PAGESHIFT()) & (PTRS_PER_PTE - 1))
> +
> +#define pgd_offset(pgdir, vaddr) \
> +	((pgdir) + pgd_index(vaddr) * 2 * sizeof(unsigned long))
> +#define pmd_offset(dir, vaddr) (dir)
> +#define pte_offset(pmd, vaddr) \
> +	(pmd_page_vaddr(pmd) + pte_index(vaddr) * sizeof(unsigned long))
> +
> +/*
> + * These only work for kernel directly mapped addresses.
> + */
> +#define __va(paddr) ((paddr) - info->phys_base + info->page_offset)
> +#define __pa(vaddr) ((vaddr) - info->page_offset + info->phys_base)
> +
> +static inline unsigned long
> +pmd_page_vaddr(unsigned long pmd)
> +{
> +	unsigned long ptr;
> +
> +	ptr = pmd & ~(PTRS_PER_PTE * sizeof(void *) - 1);
> +	ptr += PTRS_PER_PTE * sizeof(void *);
> +
> +	return __va(ptr);
> +}
> +
> +int
> +get_phys_base_arm(void)
> +{
> +	unsigned long phys_base = ULONG_MAX;
> +	int i;
> +
> +	/*
> +	 * We resolve phys_base from PT_LOAD segments. LMA contains physical
> +	 * address of the segment, and we use the first one.
> +	 */
> +	for (i = 0; i < info->num_load_memory; i++) {
> +		const struct pt_load_segment *pls = &info->pt_load_segments[i];
> +
> +		if (pls->phys_start < phys_base)
> +			phys_base = pls->phys_start;
> +	}
> +
> +	if (phys_base == ULONG_MAX) {
> +		ERRMSG("Can't determine phys_base.\n");
> +		return FALSE;
> +	}
> +
> +	info->phys_base = phys_base;
> +	DEBUG_MSG("phys_base    : %lx\n", phys_base);
> +
> +	return TRUE;
> +}
> +
> +int
> +get_machdep_info_arm(void)
> +{
> +	unsigned long vmlist, vmalloc_start;
> +
> +	info->page_offset = __PAGE_OFFSET;
> +	info->max_physmem_bits = _MAX_PHYSMEM_BITS;
> +	info->kernel_start = SYMBOL(_stext);
> +	info->section_size_bits = _SECTION_SIZE_BITS;
> +
> +	/*
> +	 * For the compatibility, makedumpfile should run without the symbol
> +	 * vmlist and the offset of vm_struct.addr if they are not necessary.
> +	 */
> +	if ((SYMBOL(vmlist) == NOT_FOUND_SYMBOL) ||
> +		OFFSET(vm_struct.addr) == NOT_FOUND_STRUCTURE) {
> +		return TRUE;
> +	}
> +
> +	if (!readmem(VADDR, SYMBOL(vmlist), &vmlist, sizeof(vmlist))) {
> +		ERRMSG("Can't get vmlist.\n");
> +		return FALSE;
> +	}
> +	if (!readmem(VADDR, vmlist + OFFSET(vm_struct.addr), &vmalloc_start,
> +		     sizeof(vmalloc_start))) {
> +		ERRMSG("Can't get vmalloc_start.\n");
> +		return FALSE;
> +	}
> +
> +	info->vmalloc_start = vmalloc_start;
> +
> +	DEBUG_MSG("page_offset  : %lx\n", info->page_offset);
> +	DEBUG_MSG("kernel_start : %lx\n", info->kernel_start);
> +	DEBUG_MSG("vmalloc_start: %lx\n", vmalloc_start);
> +
> +	return TRUE;
> +}
> +
> +static int
> +is_vmalloc_addr_arm(unsigned long vaddr)
> +{
> +	return (info->vmalloc_start && vaddr >= info->vmalloc_start);
> +}
> +
> +/*
> + * vtop_arm() - translate arbitrary virtual address to physical
> + * @vaddr: virtual address to translate
> + *
> + * Function translates @vaddr into physical address using page tables. This
> + * address can be any virtual address. Returns physical address of the
> + * corresponding virtual address or %NOT_PADDR when there is no translation.
> + */
> +static unsigned long long
> +vtop_arm(unsigned long vaddr)
> +{
> +	unsigned long long paddr = NOT_PADDR;
> +	unsigned long ptr, pgd, pte, pmd;
> +
> +	if (SYMBOL(swapper_pg_dir) == NOT_FOUND_SYMBOL) {
> +		ERRMSG("Can't get the symbol of swapper_pg_dir.\n");
> +		return NOT_PADDR;
> +	}
> +
> +	ptr = pgd_offset(SYMBOL(swapper_pg_dir), vaddr);
> +	if (!readmem(VADDR, ptr, &pgd, sizeof(pmd))) {
> +		ERRMSG("Can't read pgd\n");
> +		return NOT_PADDR;
> +	}
> +
> +	if (info->vaddr_for_vtop == vaddr)
> +		MSG("  PGD : %08lx => %08lx\n", ptr, pgd);
> +
> +	pmd = pmd_offset(pgd, vaddr);
> +
> +	switch (pmd & PMD_TYPE_MASK) {
> +	case PMD_TYPE_TABLE: {
> +		/* 4k small page */
> +		ptr = pte_offset(pmd, vaddr);
> +		if (!readmem(VADDR, ptr, &pte, sizeof(pte))) {
> +			ERRMSG("Can't read pte\n");
> +			return NOT_PADDR;
> +		}
> +
> +		if (info->vaddr_for_vtop == vaddr)
> +			MSG("  PTE : %08lx => %08lx\n", ptr, pte);
> +
> +		if (!(pte & _PAGE_PRESENT)) {
> +			ERRMSG("Can't get a valid pte.\n");
> +			return NOT_PADDR;
> +		}
> +
> +		paddr = PAGEBASE(pte) + (vaddr & (PAGESIZE() - 1));
> +		break;
> +	}
> +
> +	case PMD_TYPE_SECT:
> +		/* 1MB section */
> +		pte = pmd & PMD_MASK;
> +		paddr = pte + (vaddr & (PMD_SIZE - 1));
> +		break;
> +	}
> +
> +	return paddr;
> +}
> +
> +unsigned long long
> +vaddr_to_paddr_arm(unsigned long vaddr)
> +{
> +	unsigned long long paddr;
> +
> +	if ((paddr = vaddr_to_paddr_general(vaddr)) != NOT_PADDR)
> +		return paddr;

Here is a checkpatche.pl's error.
====
ERROR: do not use assignment in if condition
#303: FILE: arm.c:189:
+       if ((paddr = vaddr_to_paddr_general(vaddr)) != NOT_PADDR)

total: 1 errors, 0 warnings, 261 lines checked
====

How about is this?
====
+unsigned long long
+vaddr_to_paddr_arm(unsigned long vaddr)
+{
+	unsigned long long paddr = vaddr_to_paddr_general(vaddr);
+
+	if (paddr != NOT_PADDR)
+		return paddr;
====

BTW, I'm testing these patches for x86/x86_64 arch now.
I'll merge these patches after my testing.

But I cannot test for ARM because have no test machines of ARM.

Thanks.
-- Masayuki Igawa


> +
> +	if (is_vmalloc_addr_arm(vaddr))
> +		paddr = vtop_arm(vaddr);
> +	else
> +		paddr = __pa(vaddr);
> +
> +	return paddr;
> +}
> +
> +#endif /* __arm__ */
> diff --git a/makedumpfile.h b/makedumpfile.h
> index 2717d81..8a74b34 100644
> --- a/makedumpfile.h
> +++ b/makedumpfile.h
> @@ -506,6 +506,24 @@ do { \
>  #define VMEMMAP_START		(info->vmemmap_start)
>  #define VMEMMAP_END		(info->vmemmap_end)
>  
> +#ifdef __arm__
> +#define __PAGE_OFFSET		(0xc0000000)
> +#define KVBASE_MASK		(0xffff)
> +#define KVBASE			(SYMBOL(_stext) & ~KVBASE_MASK)
> +#define _SECTION_SIZE_BITS	(28)
> +#define _MAX_PHYSMEM_BITS	(32)
> +#define ARCH_PFN_OFFSET		(info->phys_base >> PAGESHIFT())
> +
> +#define PTRS_PER_PTE		(512)
> +#define PGDIR_SHIFT		(21)
> +#define PMD_SHIFT		(21)
> +#define PMD_SIZE		(1UL << PMD_SHIFT)
> +#define PMD_MASK		(~(PMD_SIZE - 1))
> +
> +#define _PAGE_PRESENT		(1 << 0)
> +
> +#endif /* arm */
> +
>  #ifdef __x86__
>  #define __PAGE_OFFSET		(0xc0000000)
>  #define __VMALLOC_RESERVE       (128 << 20)
> @@ -653,6 +671,16 @@ do { \
>  /*
>   * The function of dependence on machine
>   */
> +#ifdef __arm__
> +int get_phys_base_arm(void);
> +int get_machdep_info_arm(void);
> +unsigned long long vaddr_to_paddr_arm(unsigned long vaddr);
> +#define get_phys_base()		get_phys_base_arm()
> +#define get_machdep_info()	get_machdep_info_arm()
> +#define get_versiondep_info()	TRUE
> +#define vaddr_to_paddr(X)	vaddr_to_paddr_arm(X)
> +#endif /* arm */
> +
>  #ifdef __x86__
>  int get_machdep_info_x86(void);
>  int get_versiondep_info_x86(void);
> @@ -1148,6 +1176,11 @@ struct domain_list {
>  #define PAGES_PER_MAPWORD 	(sizeof(unsigned long) * 8)
>  #define MFNS_PER_FRAME		(info->page_size / sizeof(unsigned long))
>  
> +#ifdef __arm__
> +#define kvtop_xen(X)	FALSE
> +#define get_xen_info_arch(X) FALSE
> +#endif	/* arm */
> +
>  #ifdef __x86__
>  #define HYPERVISOR_VIRT_START_PAE	(0xF5800000UL)
>  #define HYPERVISOR_VIRT_START		(0xFC000000UL)
> -- 
> 1.5.6.5
> 
> 
> _______________________________________________
> kexec mailing list
> kexec at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kexec




From lars at metafoo.de  Thu Jun 24 04:20:35 2010
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Thu, 24 Jun 2010 10:20:35 +0200
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and
	sleepinggpios)
In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE08E0855B97@Cloud.RL.local>
References: <70E876B0EA86DD4BAF101844BC814DFE08E0855B97@Cloud.RL.local>
Message-ID: <4C231553.3030001@metafoo.de>

Jon Povey wrote:
> Ryan Mallon wrote:
>
>   
>> If we strip my patch back to just introducing gpio_request_cansleep,
>> which would be used in any driver where all of the calls are
>> gpio_(set/get)_cansleep, and make gpio_request only allow non-sleeping
>> gpios then incorrect use of gpios would be caught at request time and
>> returned to the caller as an error.
>>     
>
> It seems like a good idea to catch these at request time. There is support in the API for this already (gpio_cansleep), but driver writers are not steered towards checking and thinking in these ways by the current API or documentation. Perhaps a documentation change with some cut and paste boilerplate would be enough, but I think some API enforcement/encouragement would be helpful.
>
> I think this agrees with you, Ryan:
>
> gpio_request_cansleep would be the same as current gpio_request
> gpio_request changes to error if this is a sleepy gpio.
>
> Imagine a situation where GPIOs are being assigned and passed around between drivers in some dynamic way, or some way unpredictable to the driver writer. In development only non-sleeping GPIOs have been seen and everything is fine. One day someone feeds it a GPIO on an I2C expander and the driver crashes.
> If gpio_request had this built-in check the driver could gracefuly fail to load instead with an appropriate error message.
>
>
>   
Hi

Given that that most users will only access the gpios in context where
sleeping is possible it would make more sense to add a special case for
those who use it in contexts where sleeping is not possible.
This wouldn't change the semantics of the current API and furthermore it
is possible to implement it as a small helper function on top of the
current API.

Something like:
int gpio_request_atomic(unsigned gpio, const char *label)
{
    if (gpio_cansleep(gpio))
       return -EINVAL;
    return gpio_request(gpio, label);
}


- Lars


From ext-mika.1.westerberg at nokia.com  Thu Jun 24 04:19:15 2010
From: ext-mika.1.westerberg at nokia.com (Mika Westerberg)
Date: Thu, 24 Jun 2010 11:19:15 +0300
Subject: [PATCH 3/3] add ARM crashdump support
In-Reply-To: <20100624163356.dbb849bc.igawa@mxs.nes.nec.co.jp>
References: <cover.1277188127.git.ext-mika.1.westerberg@nokia.com>
	<b567a76e7f4502ccd56f818ebd3d6509ebd4a96d.1277188128.git.ext-mika.1.westerberg@nokia.com>
	<20100624163356.dbb849bc.igawa@mxs.nes.nec.co.jp>
Message-ID: <20100624081915.GF29920@esdhcp04058.research.nokia.com>

On Thu, Jun 24, 2010 at 09:33:56AM +0200, ext Masayuki Igawa wrote:
> Hi, Mika.

(...)

> > +unsigned long long
> > +vaddr_to_paddr_arm(unsigned long vaddr)
> > +{
> > +	unsigned long long paddr;
> > +
> > +	if ((paddr = vaddr_to_paddr_general(vaddr)) != NOT_PADDR)
> > +		return paddr;
> 
> Here is a checkpatche.pl's error.
> ====
> ERROR: do not use assignment in if condition
> #303: FILE: arm.c:189:
> +       if ((paddr = vaddr_to_paddr_general(vaddr)) != NOT_PADDR)
> 
> total: 1 errors, 0 warnings, 261 lines checked
> ====

Ah, didn't notice that. Thanks.

> How about is this?
> ====
> +unsigned long long
> +vaddr_to_paddr_arm(unsigned long vaddr)
> +{
> +	unsigned long long paddr = vaddr_to_paddr_general(vaddr);
> +
> +	if (paddr != NOT_PADDR)
> +		return paddr;
> ====

Yeah, looks OK to me.

Do you want me to send a revisited version of the patches or do you change that
yourself?

> BTW, I'm testing these patches for x86/x86_64 arch now.
> I'll merge these patches after my testing.

Cool, thanks.

> But I cannot test for ARM because have no test machines of ARM.

Well I can do the testing for ARM (unless someone else, who is using ARM kdump
currently, wants to test this). If the above is the only change it should still
work.

Thanks,
MW


From rabin.vincent at stericsson.com  Thu Jun 24 04:27:47 2010
From: rabin.vincent at stericsson.com (Rabin VINCENT)
Date: Thu, 24 Jun 2010 13:57:47 +0530
Subject: [PATCH 07/12] mmci: pass power_mode to the translate_vdd callback
In-Reply-To: <AANLkTil2Cb4alVFkfEjXApMgIdkmNvEEarWkT9AhXIdU@mail.gmail.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
	<1277198267-10860-7-git-send-email-rabin.vincent@stericsson.com>
	<AANLkTil2Cb4alVFkfEjXApMgIdkmNvEEarWkT9AhXIdU@mail.gmail.com>
Message-ID: <20100624082746.GA12453@bnru01.bnr.st.com>

On Wed, Jun 23, 2010 at 00:03:47 +0200, Linus Walleij wrote:
> 2010/6/22 Rabin Vincent <rabin.vincent at stericsson.com>:
> > @@ -17,7 +17,8 @@
> > ?* mmc/host.h
> > ?* @translate_vdd: a callback function to translate a MMC_VDD_*
> > ?* mask into a value to be binary or:ed and written into the
> > - * MMCIPWR register of the block
> > + * MMCIPWR register of the block. ?May also control external power
> > + * based on the power_mode.
> 
> Actually this callback is named like that for a reason: it is to be used
> to translate the MMC_VDD_* into a u8:4 bitmask for the MMCIPWR
> register, 4 bits possibly routed out of the PL180 block on some
> designs (never seen in practice, but could be used in theory).
> 
> So it translates a voltage into a 4-bit bitmask, hence the name.
> 
> Now the semantics are altered to have other side-effects in
> the platform, so the function should be renamed, something like
> platform_vdd_handler() would be more appropriate.
> 

This is already inside platform data, so how about just ->vdd_handler()?
Or ->set_power(), like some other drivers?

Note that we'd also like to use this to do the board-specific settings
for the *DIREN and FBCLK bits, which replace the Voltage bits on some ST
variants, like so:

+static u32 mop500_sdi0_translate_vdd(struct device *dev, unsigned int vdd,
+				     unsigned char power_mode)
+{
+	if (power_mode == MMC_POWER_UP)
+		gpio_set_value(gpio_sdmmc_en, 1);
+	else if (power_mode == MMC_POWER_OFF)
+		gpio_set_value(gpio_sdmmc_en, 0);
+
+	return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
+	       MCI_DATA2DIREN | MCI_DATA31DIREN;
+}

Rabin


From ext-jani.1.nikula at nokia.com  Thu Jun 24 04:29:42 2010
From: ext-jani.1.nikula at nokia.com (Jani Nikula)
Date: Thu, 24 Jun 2010 11:29:42 +0300 (EEST)
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and
	sleepinggpios)
In-Reply-To: <70E876B0EA86DD4BAF101844BC814DFE08E0855B97@Cloud.RL.local>
References: <70E876B0EA86DD4BAF101844BC814DFE08E0855B97@Cloud.RL.local>
Message-ID: <alpine.DEB.2.00.1006241101240.11148@wnav-qrfxgbc>


On Thu, 24 Jun 2010, ext Jon Povey wrote:

> Ryan Mallon wrote:
>
>> If we strip my patch back to just introducing gpio_request_cansleep, 
>> which would be used in any driver where all of the calls are 
>> gpio_(set/get)_cansleep, and make gpio_request only allow non-sleeping 
>> gpios then incorrect use of gpios would be caught at request time and 
>> returned to the caller as an error.
>
> It seems like a good idea to catch these at request time. There is 
> support in the API for this already (gpio_cansleep), but driver writers 
> are not steered towards checking and thinking in these ways by the 
> current API or documentation. Perhaps a documentation change with some 
> cut and paste boilerplate would be enough, but I think some API 
> enforcement/encouragement would be helpful.
>
> I think this agrees with you, Ryan:
>
> gpio_request_cansleep would be the same as current gpio_request
> gpio_request changes to error if this is a sleepy gpio.
>
> Imagine a situation where GPIOs are being assigned and passed around 
> between drivers in some dynamic way, or some way unpredictable to the 
> driver writer. In development only non-sleeping GPIOs have been seen and 
> everything is fine. One day someone feeds it a GPIO on an I2C expander 
> and the driver crashes. If gpio_request had this built-in check the 
> driver could gracefuly fail to load instead with an appropriate error 
> message.

Hi -

There's no need to imagine such situations. It's not at all uncommon to 
request GPIOs in board files, and pass the already requested GPIO numbers 
to drivers. Replacing gpio_request() with gpio_request_cansleep() (or 
gpio_request_atomic() as suggested in another mail) in the board files 
does *nothing* to help such drivers use the correct gpio get/set calls. 
The driver will need to know what it's doing, in what contexts. Some 
drivers might not work with "sleepy" GPIOs, and that's fine - they can 
check using gpio_cansleep() and fail gracefully.

I'd just improve the documentation of the various calls and have gpiolib.c 
emit more warnings about incorrect use.


BR,
Jani.


From linus.walleij at stericsson.com  Thu Jun 24 04:56:09 2010
From: linus.walleij at stericsson.com (Linus WALLEIJ)
Date: Thu, 24 Jun 2010 10:56:09 +0200
Subject: [PATCH 07/12] mmci: pass power_mode to the translate_vdd callback
In-Reply-To: <20100624082746.GA12453@bnru01.bnr.st.com>
References: <1277198267-10860-1-git-send-email-rabin.vincent@stericsson.com>
	<1277198267-10860-7-git-send-email-rabin.vincent@stericsson.com>
	<AANLkTil2Cb4alVFkfEjXApMgIdkmNvEEarWkT9AhXIdU@mail.gmail.com>
	<20100624082746.GA12453@bnru01.bnr.st.com>
Message-ID: <CEE6BB42CAD6E947908279175AF8470A025FD0D483@EXDCVYMBSTM006.EQ1STM.local>

[Rabin]

> On Wed, Jun 23, 2010 at 00:03:47 +0200, Linus Walleij wrote:
> > 2010/6/22 Rabin Vincent <rabin.vincent at stericsson.com>:
> > > @@ -17,7 +17,8 @@
> > > ?* mmc/host.h
> > > ?* @translate_vdd: a callback function to translate a MMC_VDD_*
> > > ?* mask into a value to be binary or:ed and written into the
> > > - * MMCIPWR register of the block
> > > + * MMCIPWR register of the block. ?May also control external power
> > > + * based on the power_mode.
> >
> > Actually this callback is named like that for a reason: it is to be
> used
> > to translate the MMC_VDD_* into a u8:4 bitmask for the MMCIPWR
> > register, 4 bits possibly routed out of the PL180 block on some
> > designs (never seen in practice, but could be used in theory).
> >
> > So it translates a voltage into a 4-bit bitmask, hence the name.
> >
> > Now the semantics are altered to have other side-effects in
> > the platform, so the function should be renamed, something like
> > platform_vdd_handler() would be more appropriate.
> >
> 
> This is already inside platform data, so how about just -
> >vdd_handler()?
> Or ->set_power(), like some other drivers?

Any of these look good to me atleast.

But now another thing I came to think of (the fun never
ends):

Since the ux500 also have a regulator for this and since
that mechanism is mutually exclusive in the code (since the
semantics implied that it was only a voltage translation
function) you should also remove the condition that this
only gets called in case there is no regulator.

> Note that we'd also like to use this to do the board-specific settings
> for the *DIREN and FBCLK bits, which replace the Voltage bits on some
> ST
> variants, like so:
> 
> +static u32 mop500_sdi0_translate_vdd(struct device *dev, unsigned int
> vdd,
> +				     unsigned char power_mode)
> +{
> +	if (power_mode == MMC_POWER_UP)
> +		gpio_set_value(gpio_sdmmc_en, 1);
> +	else if (power_mode == MMC_POWER_OFF)
> +		gpio_set_value(gpio_sdmmc_en, 0);
> +
> +	return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
> +	       MCI_DATA2DIREN | MCI_DATA31DIREN;
> +}

OK just update the kerneldoc to reflect the fact that the platform
can OR on any *custom* bits it like to the PWR register in this
function.

Side notice: some of bits are for the ST version only, when you
patch in the latter, can you take this opportunity to also
rename MCI_FBCLKEN to MCI_ST_FBCLKEN and so on for all stuff
that is ST-specific? I think I am the sinner here, we had no
convention for how to do this naming when we first began
modifying this driver. It should be crystal clear that all
custom extensions are named MCI_<VENDOR>_FOO.

As a consequence, anything that is OR:ed into from the
vdd_handler() should typically be MCI_<VENDOR>_FOO, and
it will be clear why it's there.

Yours,
Linus Walleij


From baruch at tkos.co.il  Thu Jun 24 04:57:01 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Thu, 24 Jun 2010 11:57:01 +0300
Subject: [PATCH -next 0/2] mx25: add iomux defines
Message-ID: <cover.1277369614.git.baruch@tkos.co.il>

This series adds some iomux defines needed for the UART4 and the PWM4 devices.

This version applies to current imx-for-2.6.36.

Baruch Siach (2):
  mx25: add iomux defines for UART4 on KPP pins
  mx25: add PWM4 to iomux

 arch/arm/plat-mxc/include/mach/iomux-mx25.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)



From baruch at tkos.co.il  Thu Jun 24 04:57:02 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Thu, 24 Jun 2010 11:57:02 +0300
Subject: [PATCH -next 1/2] mx25: add iomux defines for UART4 on KPP pins
In-Reply-To: <cover.1277369614.git.baruch@tkos.co.il>
References: <cover.1277369614.git.baruch@tkos.co.il>
Message-ID: <4f6f7f79eec5d595c5fafd719ed3fab1b64e46f2.1277369614.git.baruch@tkos.co.il>

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 arch/arm/plat-mxc/include/mach/iomux-mx25.h |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index 5bea603..cbc67c7 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -386,18 +386,22 @@
 #define MX25_PAD_KPP_ROW3__GPIO_3_0	IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_KPP_COL0__KPP_COL0	IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL0__UART4_RXD_MUX IOMUX_PAD(0x3b0, 0x1b8, 0x11, 0x570, 1, NO_PAD_CTRL)
 #define MX25_PAD_KPP_COL0__AUD5_TXD	IOMUX_PAD(0x3b0, 0x1b8, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL0__GPIO_3_1	IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_KPP_COL1__KPP_COL1	IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL1__UART4_TXD_MUX IOMUX_PAD(0x3b4, 0x1bc, 0x11, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_KPP_COL1__AUD5_RXD	IOMUX_PAD(0x3b4, 0x1bc, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL1__GPIO_3_2	IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_KPP_COL2__KPP_COL2	IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL2__UART4_RTS	IOMUX_PAD(0x3b8, 0x1c0, 0x11, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_KPP_COL2__AUD5_TXC	IOMUX_PAD(0x3b8, 0x1c0, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL2__GPIO_3_3	IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_KPP_COL3__KPP_COL3	IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL3__UART4_CTS	IOMUX_PAD(0x3bc, 0x1c4, 0x11, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_KPP_COL3__AUD5_TXFS	IOMUX_PAD(0x3bc, 0x1c4, 0x12, 0, 0, PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
 #define MX25_PAD_KPP_COL3__GPIO_3_4	IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
 
-- 
1.7.1



From baruch at tkos.co.il  Thu Jun 24 04:57:03 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Thu, 24 Jun 2010 11:57:03 +0300
Subject: [PATCH -next 2/2] mx25: add PWM4 to iomux
In-Reply-To: <cover.1277369614.git.baruch@tkos.co.il>
References: <cover.1277369614.git.baruch@tkos.co.il>
Message-ID: <dd3597a30dbdd41f14c207e36123616abab78fde.1277369614.git.baruch@tkos.co.il>

Signed-off-by: Baruch Siach <baruch at tkos.co.il>
---
 arch/arm/plat-mxc/include/mach/iomux-mx25.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index cbc67c7..593c47c 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -252,6 +252,7 @@
 #define MX25_PAD_OE_ACD__GPIO_1_25	IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
 
 #define MX25_PAD_CONTRAST__CONTRAST	IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CONTRAST__PWM4_PWMO	IOMUX_PAD(0x310, 0x118, 0x14, 0, 0, NO_PAD_CTRL)
 #define MX25_PAD_CONTRAST__FEC_CRS	IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTRL)
 
 #define MX25_PAD_PWM__PWM		IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
-- 
1.7.1



From linux at arm.linux.org.uk  Thu Jun 24 05:05:02 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 24 Jun 2010 10:05:02 +0100
Subject: [PATCH 2/3] ARM: module - simplify unwind table handling
In-Reply-To: <1275567442-11370-3-git-send-email-ext-phil.2.carmody@nokia.com>
References: <1275567442-11370-1-git-send-email-ext-phil.2.carmody@nokia.com>
	<1275567442-11370-2-git-send-email-ext-phil.2.carmody@nokia.com>
	<1275567442-11370-3-git-send-email-ext-phil.2.carmody@nokia.com>
Message-ID: <20100624090502.GA1398@n2100.arm.linux.org.uk>

On Thu, Jun 03, 2010 at 03:17:21PM +0300, Phil Carmody wrote:
>  #ifdef CONFIG_ARM_UNWIND
...
> +#else
> +struct mod_arch_specific {
> +}
> +#endif

I assume no one tried building these with UNWIND disabled?  linux-next
reports most ARM builds are broken by this.

Dropped all three patches out of my git tree until it can be fixed.


From catalin.marinas at arm.com  Thu Jun 24 05:08:47 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Thu, 24 Jun 2010 10:08:47 +0100
Subject: [PATCH 2/3] ARM: module - simplify unwind table handling
In-Reply-To: <20100624090502.GA1398@n2100.arm.linux.org.uk>
References: <1275567442-11370-1-git-send-email-ext-phil.2.carmody@nokia.com>
	<1275567442-11370-2-git-send-email-ext-phil.2.carmody@nokia.com>
	<1275567442-11370-3-git-send-email-ext-phil.2.carmody@nokia.com>
	<20100624090502.GA1398@n2100.arm.linux.org.uk>
Message-ID: <1277370527.31432.0.camel@e102109-lin.cambridge.arm.com>

On Thu, 2010-06-24 at 10:05 +0100, Russell King - ARM Linux wrote:
> On Thu, Jun 03, 2010 at 03:17:21PM +0300, Phil Carmody wrote:
> >  #ifdef CONFIG_ARM_UNWIND
> ...
> > +#else
> > +struct mod_arch_specific {
> > +}
> > +#endif
> 
> I assume no one tried building these with UNWIND disabled?  linux-next
> reports most ARM builds are broken by this.
> 
> Dropped all three patches out of my git tree until it can be fixed.

It looks like a patch for fixing the build was posted on the 16th of
June, though not sure whether it went to your patch system or not.

-- 
Catalin



From u.kleine-koenig at pengutronix.de  Thu Jun 24 05:36:14 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 24 Jun 2010 11:36:14 +0200
Subject: [PATCH 09/16] arm/mx2/mbimx27: compile fixes with
	CONFIG_TOUCHSCREEN_ADS7846=y
In-Reply-To: <20100622161314.GA18606@pengutronix.de>
References: <20100524195430.GA28403@pengutronix.de>
	<1274730951-29106-9-git-send-email-u.kleine-koenig@pengutronix.de>
	<4BFADD4F.80309@eukrea.com> <20100524203428.GB29092@pengutronix.de>
	<20100622161314.GA18606@pengutronix.de>
Message-ID: <20100624093614.GB23539@pengutronix.de>

Hello,

> If we want to have ADS7846 at least compilable in .35 we should go with
> my patch as your's is (IMHO) too intrusive after -rc1.
I have somehow missed that Eric's patch is already in Sascha's
for-2.6.35 branch.  So there is nothing to do.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From kgene.kim at samsung.com  Thu Jun 24 06:16:29 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 24 Jun 2010 19:16:29 +0900
Subject: [PATCH v4] S5PV210 Correct clock register properties
In-Reply-To: <1277356687-9500-1-git-send-email-myungjoo.ham@samsung.com>
References: <1277356687-9500-1-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <010d01cb1386$554cc0f0$ffe642d0$%kim@samsung.com>

MyungJoo Ham wrote:
> 
Hi,

Thanks for your re-submitting.

But there are some comments.

It would be helpful to apply if you could keep some kind of rule about title
like following:
'ARM: S5PV210: Correct clock blahblah...'

> 1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which
were
> defined incorrectly.
> 
> 2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc,
> sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their
> twins defined in struct clk init_clocks_disable[] and struct clk
> init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK
> register to avoid the duplicated clock problem described below.
> 
> --- Duplicated Clock Problem ---

Actually, above '---' means end of git commit message.
So should not be used in here.

> Please note that each clock definition should access different control
> register; otherwise, the system may suffer lockups. For example, if we
> have two clock definitions "a" and "b" which access the same register
> (and the shift value). Then, when we do:
> 
> 	module A
> 	clk = clk_get("a");
> 	clk->clk_enable(clk);
> 
> 	module B (context switch)
> 	clk = clk_get("b");
> 	clk->clk_enable(clk);
> 	do something with clk.
> 	clk->clk_disable(clk);
> 
> 	module A (context switch)
> 	do something with clk
> 	* At this point, the system may hang.
> 
> Therefore, there should be no clock definitions with the same contol
> register/shift. If we need to create "aliases", then, creating child
> clocks sharing the clock should be fine.
> 
> 3. Corrected other sclk_* shift values and access registers.
> 
> 
> Note that becuase UART clocks are properly disabled at boot time with
> this patch, UART drivers or somebody else should turn on the clock
> to read the console; otherwise, JIG willl not show any message.
> 
I don't think so. Because the uart clocks are still under init_clocks array.
So it will be enabled at boot time.

> 
> Note that this patch revises and merges the two previous patches:
> [PATCH] S5PV210 Correct clock register properties
> [PATCH] S5PV210 Correct clock source control register properties
> And follows the previous patch
> [PATCH v2] S5PV210 Correct clock register properties
> [PATCH v3] S5PV210 Correct clock register properties
> 
As Joonyoung Shim's comments, above messages like just history should be
moved under '---'.

> 
> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-s5pv210/clock.c |  115
++++++++++++++++++++++-------------------
>  1 files changed, 62 insertions(+), 53 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> index 154bca4..b3d156c 100644
> --- a/arch/arm/mach-s5pv210/clock.c
> +++ b/arch/arm/mach-s5pv210/clock.c

(snip)

Looks good but as I commented, need to modify commit title and message.

So will apply with modifying them.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From john.ogness at linutronix.de  Thu Jun 24 06:16:39 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Thu, 24 Jun 2010 12:16:39 +0200
Subject: [PATCHv3 4/5] mtd: mxc_nand fixups
In-Reply-To: <20100624072732.GQ12115@pengutronix.de> (Sascha Hauer's message
	of "Thu, 24 Jun 2010 09:27:32 +0200")
References: <20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
	<AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
	<80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTikRj_dMkKLyFhW78yld9jIYAIFncfPaPAF8WqUY@mail.gmail.com>
	<80iq5bqd07.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTimJKNEwOoKldq4a4_ufxNY6IY7r6tAfAM055hlW@mail.gmail.com>
	<80vd9ab0d2.fsf@merkur.tec.linutronix.de>
	<AANLkTinVaXjCneg-XpxB7YNlmGOwQFTnm5RUcetPdToI@mail.gmail.com>
	<80lja6awlb.fsf@merkur.tec.linutronix.de>
	<20100624072732.GQ12115@pengutronix.de>
Message-ID: <807hloag6w.fsf@merkur.tec.linutronix.de>

On 2010-06-24, Sascha Hauer <s.hauer at pengutronix.de> wrote:
> Ok, if it's the only way out to have 5 cpu_is_* blocks, then lets go
> for it.

Here is a new patch that puts the behavior behind a "nfc_avoid_masking"
macro. The macro is only used 3 times.

I also changed the code to use a completion, since that's exactly what
we are doing there anyway.

I also added some other macros to simplify reading of the code and
reduce possible copy/paste errors relating to masking and interrupt
handling.

> BTW I observed that at least on i.MX27 the latencies introduced by
> waiting for an interrupt cause a significant performance drop. The
> driver gets much faster when we just poll all the time. I don't know
> how this affects system performance otherwise, but it may be a
> possibility to drop interrupt support at least for i.MX21. I have no
> idea how long the longest possible time we'd have to poll is though.

I don't recommend moving to pure polling. Although it may be faster for
NAND-only performance tests, I expect it would have a dramatic affect on
the rest of the system during many NAND reads/writes.


This patch is based on linux-next 20100618.

Signed-off-by: John Ogness <john.ogness at linutronix.de>
---
 drivers/mtd/nand/mxc_nand.c |   81 +++++++++++++++++++++++++---------
 1 file changed, 61 insertions(+), 20 deletions(-)

Index: linux-next-20100618/drivers/mtd/nand/mxc_nand.c
===================================================================
--- linux-next-20100618.orig/drivers/mtd/nand/mxc_nand.c
+++ linux-next-20100618/drivers/mtd/nand/mxc_nand.c
@@ -30,6 +30,8 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/completion.h>
 
 #include <asm/mach/flash.h>
 #include <mach/mxc_nand.h>
@@ -40,6 +42,13 @@
 #define nfc_is_v21()		(cpu_is_mx25() || cpu_is_mx35())
 #define nfc_is_v1()		(cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
 
+/* It has been observeed that the i.MX21 cannot read the CONFIG2:INT bit
+ * if interrupts are masked (CONFIG1:INT_MSK is set). To handle this, the
+ * driver can enable/disable the irq line rather than simply masking the
+ * interrupts. The nfc_avoid_masking() macro identifies the systems that
+ * should use this workaround. */
+#define nfc_avoid_masking()	(cpu_is_mx21())
+
 /* Addresses for NFC registers */
 #define NFC_BUF_SIZE		0xE00
 #define NFC_BUF_ADDR		0xE04
@@ -100,6 +109,18 @@
 
 #define NFC_RSLTSPARE_AREA_MASK  0xff
 
+#define nfc_interrupt_set(_regs) \
+		(readw(_regs + NFC_CONFIG2) & NFC_INT)
+#define nfc_clear_interrupt(_regs) \
+		writew(readw(_regs + NFC_CONFIG2) & ~NFC_INT, \
+		       _regs + NFC_CONFIG2)
+#define nfc_mask_irq(_regs) \
+		writew(readw(_regs + NFC_CONFIG1) | NFC_INT_MSK, \
+		       _regs + NFC_CONFIG1)
+#define nfc_unmask_irq(_regs) \
+		writew(readw(_regs + NFC_CONFIG1) & ~NFC_INT_MSK, \
+		       _regs + NFC_CONFIG1)
+
 struct mxc_nand_host {
 	struct mtd_info		mtd;
 	struct nand_chip	nand;
@@ -117,7 +138,7 @@ struct mxc_nand_host {
 	int			clk_act;
 	int			irq;
 
-	wait_queue_head_t	irq_waitq;
+	struct completion	op_completion;
 
 	uint8_t			*data_buf;
 	unsigned int		buf_start;
@@ -174,9 +195,18 @@ static irqreturn_t mxc_nfc_irq(int irq, 
 {
 	struct mxc_nand_host *host = dev_id;
 
-	disable_irq_nosync(irq);
-
-	wake_up(&host->irq_waitq);
+	/* If NFC_INT is not set, we have a spurious interrupt! */
+	if (!nfc_interrupt_set(host->regs))
+		return IRQ_NONE;
+
+	/* Even with nfc_avoid_masking() we mask the interrupt
+	 * here to avoid an interrupt flood until the irq line
+	 * is disabled by the driver thread. */
+	nfc_mask_irq(host->regs);
+
+	/* Notify the driver thread that an interrupt has occurred.
+	 * The driver thread will clear the interrupt. */
+	complete(&host->op_completion);
 
 	return IRQ_HANDLED;
 }
@@ -186,27 +216,32 @@ static irqreturn_t mxc_nfc_irq(int irq, 
  */
 static void wait_op_done(struct mxc_nand_host *host, int useirq)
 {
-	uint16_t tmp;
 	int max_retries = 8000;
 
 	if (useirq) {
-		if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
+		if (!nfc_interrupt_set(host->regs)) {
+
+			INIT_COMPLETION(host->op_completion);
 
-			enable_irq(host->irq);
+			if (nfc_avoid_masking())
+				enable_irq(host->irq);
+			else
+				nfc_unmask_irq(host->regs);
 
-			wait_event(host->irq_waitq,
-				readw(host->regs + NFC_CONFIG2) & NFC_INT);
+			/* wait for the interrupt */
+			wait_for_completion(&host->op_completion);
 
-			tmp = readw(host->regs + NFC_CONFIG2);
-			tmp  &= ~NFC_INT;
-			writew(tmp, host->regs + NFC_CONFIG2);
+			if (nfc_avoid_masking()) {
+				disable_irq(host->irq);
+				nfc_unmask_irq(host->regs);
+			}
 		}
+
+		nfc_clear_interrupt(host->regs);
 	} else {
 		while (max_retries-- > 0) {
-			if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
-				tmp = readw(host->regs + NFC_CONFIG2);
-				tmp  &= ~NFC_INT;
-				writew(tmp, host->regs + NFC_CONFIG2);
+			if (nfc_interrupt_set(host->regs)) {
+				nfc_clear_interrupt(host->regs);
 				break;
 			}
 			udelay(1);
@@ -582,9 +617,8 @@ static void preset(struct mtd_info *mtd)
 	struct mxc_nand_host *host = nand_chip->priv;
 	uint16_t tmp;
 
-	/* enable interrupt, disable spare enable, setup ECC */
+	/* disable spare-only, setup ECC */
 	tmp = readw(host->regs + NFC_CONFIG1);
-	tmp &= ~NFC_INT_MSK;
 	tmp &= ~NFC_SP_EN;
 	if (nand_chip->ecc.mode == NAND_ECC_HW) {
 		tmp |= NFC_ECC_EN;
@@ -842,11 +876,18 @@ static int __init mxcnd_probe(struct pla
 		this->options |= NAND_USE_FLASH_BBT;
 	}
 
-	init_waitqueue_head(&host->irq_waitq);
+	init_completion(&host->op_completion);
 
 	host->irq = platform_get_irq(pdev, 0);
 
-	err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
+	if (nfc_avoid_masking()) {
+		set_irq_flags(host->irq, IRQF_VALID | IRQF_NOAUTOEN);
+		nfc_unmask_irq(host->regs);
+	} else {
+		nfc_mask_irq(host->regs);
+	}
+
+	err = request_irq(host->irq, mxc_nfc_irq, 0, DRIVER_NAME, host);
 	if (err)
 		goto eirq;
 


From kgene.kim at samsung.com  Thu Jun 24 06:22:36 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 24 Jun 2010 19:22:36 +0900
Subject: [PATCH v4] S5PV210 Correct clock register properties
In-Reply-To: <4C22EF73.8030108@samsung.com>
References: <1277356687-9500-1-git-send-email-myungjoo.ham@samsung.com>
	<4C22EF73.8030108@samsung.com>
Message-ID: <010e01cb1387$2ef32330$8cd96990$%kim@samsung.com>

Joonyoung Shim wrote:
> 
> Hi,

Hi :-)

> 
> On 6/24/2010 2:18 PM, MyungJoo Ham wrote:
> > 1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which were
> > defined incorrectly.
> >
> > 2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc,
> > sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their
> > twins defined in struct clk init_clocks_disable[] and struct clk
> > init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK
> > register to avoid the duplicated clock problem described below.
> >
> > --- Duplicated Clock Problem ---
> > Please note that each clock definition should access different control
> > register; otherwise, the system may suffer lockups. For example, if we
> > have two clock definitions "a" and "b" which access the same register
> > (and the shift value). Then, when we do:
> >
> > 	module A
> > 	clk = clk_get("a");
> > 	clk->clk_enable(clk);
> >
> > 	module B (context switch)
> > 	clk = clk_get("b");
> > 	clk->clk_enable(clk);
> > 	do something with clk.
> > 	clk->clk_disable(clk);
> >
> > 	module A (context switch)
> > 	do something with clk
> > 	* At this point, the system may hang.
> >
> > Therefore, there should be no clock definitions with the same contol
> > register/shift. If we need to create "aliases", then, creating child
> > clocks sharing the clock should be fine.
> >
> > 3. Corrected other sclk_* shift values and access registers.
> >
> >
> > Note that becuase UART clocks are properly disabled at boot time with
> > this patch, UART drivers or somebody else should turn on the clock
> > to read the console; otherwise, JIG willl not show any message.
> >
> >
> > Note that this patch revises and merges the two previous patches:
> > [PATCH] S5PV210 Correct clock register properties
> > [PATCH] S5PV210 Correct clock source control register properties
> > And follows the previous patch
> > [PATCH v2] S5PV210 Correct clock register properties
> > [PATCH v3] S5PV210 Correct clock register properties
> >
> 
> The history about patch is better to go to below --- line. The contents
> of below --- line aren't included to commit message at the git.
> 
Yes, right.

One more, already there is '---' in above comments :-(

> >
> > Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> > Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > ---
> 
> Here.
> 
> >  arch/arm/mach-s5pv210/clock.c |  115 ++++++++++++++++++++++---------------
> ----
> >  1 files changed, 62 insertions(+), 53 deletions(-)
> >
> > diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> > index 154bca4..b3d156c 100644
> > --- a/arch/arm/mach-s5pv210/clock.c
> > +++ b/arch/arm/mach-s5pv210/clock.c

(snip)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From lars at metafoo.de  Thu Jun 24 06:31:13 2010
From: lars at metafoo.de (Lars-Peter Clausen)
Date: Thu, 24 Jun 2010 12:31:13 +0200
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and
	sleepinggpios)
In-Reply-To: <alpine.DEB.2.00.1006241101240.11148@wnav-qrfxgbc>
References: <70E876B0EA86DD4BAF101844BC814DFE08E0855B97@Cloud.RL.local>
	<alpine.DEB.2.00.1006241101240.11148@wnav-qrfxgbc>
Message-ID: <4C2333F1.6050102@metafoo.de>

Jani Nikula wrote:
>
> On Thu, 24 Jun 2010, ext Jon Povey wrote:
>
>> Ryan Mallon wrote:
>>
>>> If we strip my patch back to just introducing gpio_request_cansleep,
>>> which would be used in any driver where all of the calls are
>>> gpio_(set/get)_cansleep, and make gpio_request only allow
>>> non-sleeping gpios then incorrect use of gpios would be caught at
>>> request time and returned to the caller as an error.
>>
>> It seems like a good idea to catch these at request time. There is
>> support in the API for this already (gpio_cansleep), but driver
>> writers are not steered towards checking and thinking in these ways
>> by the current API or documentation. Perhaps a documentation change
>> with some cut and paste boilerplate would be enough, but I think some
>> API enforcement/encouragement would be helpful.
>>
>> I think this agrees with you, Ryan:
>>
>> gpio_request_cansleep would be the same as current gpio_request
>> gpio_request changes to error if this is a sleepy gpio.
>>
>> Imagine a situation where GPIOs are being assigned and passed around
>> between drivers in some dynamic way, or some way unpredictable to the
>> driver writer. In development only non-sleeping GPIOs have been seen
>> and everything is fine. One day someone feeds it a GPIO on an I2C
>> expander and the driver crashes. If gpio_request had this built-in
>> check the driver could gracefuly fail to load instead with an
>> appropriate error message.
>
> Hi -
>
> There's no need to imagine such situations. It's not at all uncommon
> to request GPIOs in board files, and pass the already requested GPIO
> numbers to drivers. Replacing gpio_request() with
> gpio_request_cansleep() (or gpio_request_atomic() as suggested in
> another mail) in the board files does *nothing* to help such drivers
> use the correct gpio get/set calls. The driver will need to know what
> it's doing, in what contexts. Some drivers might not work with
> "sleepy" GPIOs, and that's fine - they can check using gpio_cansleep()
> and fail gracefully.
Is there a reason, why a gpio is requested in the board file and not in
the driver? I would have considered that the later is far more common.

Sure, drivers which do not request the gpios themselves would have to
call gpio_cansleep, but for those which request the gpios themselves it
would help to reduce code clutter to have a gpio_request_atomic. The
only argument speaking against adding such a helper function would be
that drivers accessing gpios in contexts where they can not sleep are
far to rare to bother.

- Lars


From jason77.wang at gmail.com  Thu Jun 24 08:12:45 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Thu, 24 Jun 2010 20:12:45 +0800
Subject: [PATCH] spi/omap2_mcspi: disable and enable chan between each SPI
	transfer
Message-ID: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com>

In current design, the SPI channel is always enable during the period
of handling a SPI message, it is risky when more than one SPI transfer
are included in a message. Current working route like that:
[
  SPI channel enable
  configure channel
  handle transfer #1
  configure channel
  handle transfer #2
  ...
  SPI channel disable
]
If we can disable channel before configure it and reenable
channel after it is configured, it will be more safe.

The commit a330ce2 "omap2_mcspi: Flush posted writes" make this risk
to a real problem for ads7846 driver on omap3530evm. The
ads7846 driver will send a SPI messge which includes,
[
  TX_ONLY transfer (1 byte)
  RX_ONLY transfer (2 bytes)
  TX_ONLY transfer (1 byte)
  RX_ONLY transfer (2 bytes)
]
If we don't add disable/reenable channel between TX and RX transfers,
the RX transfer will get wrong datas sent from slave.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 drivers/spi/omap2_mcspi.c |   16 ++++++----------
 1 files changed, 6 insertions(+), 10 deletions(-)

diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index b3a94ca..1e3cb7b 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -408,7 +408,6 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 				count -= (word_len <= 8)  ? 2 :
 					(word_len <= 16) ? 4 :
 					/* word_len <= 32 */ 8;
-				omap2_mcspi_set_enable(spi, 1);
 				return count;
 			}
 		}
@@ -430,8 +429,10 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 				 (word_len <= 16) ? 2 :
 			       /* word_len <= 32 */ 4;
 		}
-		omap2_mcspi_set_enable(spi, 1);
 	}
+
+	omap2_mcspi_set_enable(spi, 0);
+
 	return count;
 }
 
@@ -517,8 +518,6 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 						goto out;
 					}
 					c = 0;
-				} else if (c == 0 && tx == NULL) {
-					omap2_mcspi_set_enable(spi, 0);
 				}
 
 				*rx++ = __raw_readl(rx_reg);
@@ -570,8 +569,6 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 						goto out;
 					}
 					c = 0;
-				} else if (c == 0 && tx == NULL) {
-					omap2_mcspi_set_enable(spi, 0);
 				}
 
 				*rx++ = __raw_readl(rx_reg);
@@ -623,8 +620,6 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 						goto out;
 					}
 					c = 0;
-				} else if (c == 0 && tx == NULL) {
-					omap2_mcspi_set_enable(spi, 0);
 				}
 
 				*rx++ = __raw_readl(rx_reg);
@@ -646,7 +641,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 			dev_err(&spi->dev, "EOT timed out\n");
 	}
 out:
-	omap2_mcspi_set_enable(spi, 1);
+	omap2_mcspi_set_enable(spi, 0);
 	return count - c;
 }
 
@@ -894,7 +889,6 @@ static void omap2_mcspi_work(struct work_struct *work)
 		cs = spi->controller_state;
 		cd = spi->controller_data;
 
-		omap2_mcspi_set_enable(spi, 1);
 		list_for_each_entry(t, &m->transfers, transfer_list) {
 			if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 				status = -EINVAL;
@@ -931,6 +925,8 @@ static void omap2_mcspi_work(struct work_struct *work)
 
 			mcspi_write_chconf0(spi, chconf);
 
+			omap2_mcspi_set_enable(spi, 1);
+
 			if (t->len) {
 				unsigned	count;
 
-- 
1.5.6.5



From linus.walleij at stericsson.com  Thu Jun 24 08:17:51 2010
From: linus.walleij at stericsson.com (Linus WALLEIJ)
Date: Thu, 24 Jun 2010 14:17:51 +0200
Subject: FW: Regression in next-20100618
Message-ID: <CEE6BB42CAD6E947908279175AF8470A025FD0D69A@EXDCVYMBSTM006.EQ1STM.local>

Looping in linux-arm-kernel in case there are more people having
this regression on -next since 20100618.

I verified that the regression also appears on U300, and I
suspect all platforms using PL011 to suffer from it, including
Versatile, RealView and SPEAr for example.

Symptom: garbage characters at TTY prompt after boot.

Trying to figure out what is causing this but failing :-/

Yours,
Linus Walleij

-----Original Message-----
From: Linus WALLEIJ 
Sent: den 23 juni 2010 23:54
To: 'Alan Cox'
Cc: 'Greg Kroah-Hartman'; 'linux-kernel at vger.kernel.org'
Subject: Regression in next-20100618

Hi Alan,

I have a regression in the next tree from 20100618, the prompt
freezes on the U8500. Drilling down with git bisecting found:

34ffc9670d67fe068f9d8582dd4d2a18d9a61205
Author: Alan Cox <alan at linux.intel.com>
Date:   Tue Jun 1 22:53:00 2010 +0200

    serial: Use block_til_ready helper

    Our code now rather closely resembles the helper, so switch to it.

    Signed-off-by: Alan Cox <alan at linux.intel.com>
    Cc: Arnd Bergmann <arnd at arndb.de>
    Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>

Reverting the commit makes the problem go away.

This platform is using drivers/serial/amba-pl011.c

Any ideas I could try out to help troubleshooting this one?
It could be that you're provoking some bug in amba-pl011.c.

Yours,
Linus Walleij


From david-b at pacbell.net  Thu Jun 24 06:36:18 2010
From: david-b at pacbell.net (David Brownell)
Date: Thu, 24 Jun 2010 03:36:18 -0700 (PDT)
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and
	sleepinggpios)
Message-ID: <924139.5848.qm@web180311.mail.gq1.yahoo.com>


--- On Wed, 6/23/10, Jon Povey <Jon.Povey at racelogic.co.uk> wrote:
>
> Date: Wednesday, June 23, 2010, 9:46 PM
> Ryan Mallon wrote:
> 
> > If we strip my patch back to just introducing
> gpio_request_cansleep,
> > which would be used in any driver where all of the
> calls are
> > gpio_(set/get)_cansleep, and make gpio_request only
> allow non-sleeping
> > gpios then incorrect use of gpios would be caught at
> request time and
> > returned to the caller as an error.
> 
> It seems like a good idea to catch these at request time.
> There is support in the API for this already
> (gpio_cansleep), but driver writers are not steered towards
> checking and thinking in these ways by the current API or
> 
> gpio_request_cansleep would be the same as current
> gpio_request

I wonder if, by the time I catch up on this
ever-extending email thread

... someone else will have noted that
because gpio_request() can now poke the GPIO
chip, that call might actually need to sleep.
So there'd be a difference between the two
calls:? one would *NEED* to be called in a
sleepable thread context, vs. that just being
well advised (e.g. as part of board setup in
arch init code after tasking is working)...

So that couldn't work quite that way.





From kgene.kim at samsung.com  Thu Jun 24 08:56:45 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 24 Jun 2010 21:56:45 +0900
Subject: [PATCH 1/2] ARM: S5PV210: Fix Aquila board UART FIFO mode
	configration
In-Reply-To: <1277354105-13097-1-git-send-email-jy0922.shim@samsung.com>
References: <1277354105-13097-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <012c01cb139c$b6967250$23c356f0$%kim@samsung.com>

Joonyoung Shim wrote:
> 
> The Aquila board uses max UART FIFO size to each UART channels. UART0
> supports 256 bytes FIFO, but Aquila board supports 128 bytes FIFO
> because of initial chip bug.
> 
> Also, this patch fixes to "s/smdkv210/aquila".
> 
> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-s5pv210/mach-aquila.c |   24 +++++++++++++++---------
>  1 files changed, 15 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/mach-aquila.c
b/arch/arm/mach-s5pv210/mach-
> aquila.c
> index 10bc76e..5795a7c 100644
> --- a/arch/arm/mach-s5pv210/mach-aquila.c
> +++ b/arch/arm/mach-s5pv210/mach-aquila.c
> @@ -39,38 +39,44 @@
> 
>  #define S5PV210_ULCON_DEFAULT	S3C2410_LCON_CS8
> 
> -#define S5PV210_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
> -				 S5PV210_UFCON_TXTRIG4 |	\
> -				 S5PV210_UFCON_RXTRIG4)
> +#define S5PV210_UFCON_DEFAULT	S3C2410_UFCON_FIFOMODE
> 
I think it is better to change 'S5PV210_xxx_DEFAULT' to board specific name
later.

But right now, it's ok.

> -static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
> +static struct s3c2410_uartcfg aquila_uartcfgs[] __initdata = {
>  	[0] = {
>  		.hwport		= 0,
>  		.flags		= 0,
>  		.ucon		= S5PV210_UCON_DEFAULT,
>  		.ulcon		= S5PV210_ULCON_DEFAULT,
> -		.ufcon		= S5PV210_UFCON_DEFAULT,
> +		/*
> +		 * Actually UART0 can support 256 bytes fifo, but aquila
board
> +		 * supports 128 bytes fifo because of initial chip bug
> +		 */
> +		.ufcon		= S5PV210_UFCON_DEFAULT |
> +			S5PV210_UFCON_TXTRIG128 |
> S5PV210_UFCON_RXTRIG128,
>  	},
>  	[1] = {
>  		.hwport		= 1,
>  		.flags		= 0,
>  		.ucon		= S5PV210_UCON_DEFAULT,
>  		.ulcon		= S5PV210_ULCON_DEFAULT,
> -		.ufcon		= S5PV210_UFCON_DEFAULT,
> +		.ufcon		= S5PV210_UFCON_DEFAULT |
> +			S5PV210_UFCON_TXTRIG64 |
> S5PV210_UFCON_RXTRIG64,
>  	},
>  	[2] = {
>  		.hwport		= 2,
>  		.flags		= 0,
>  		.ucon		= S5PV210_UCON_DEFAULT,
>  		.ulcon		= S5PV210_ULCON_DEFAULT,
> -		.ufcon		= S5PV210_UFCON_DEFAULT,
> +		.ufcon		= S5PV210_UFCON_DEFAULT |
> +			S5PV210_UFCON_TXTRIG16 |
> S5PV210_UFCON_RXTRIG16,
>  	},
>  	[3] = {
>  		.hwport		= 3,
>  		.flags		= 0,
>  		.ucon		= S5PV210_UCON_DEFAULT,
>  		.ulcon		= S5PV210_ULCON_DEFAULT,
> -		.ufcon		= S5PV210_UFCON_DEFAULT,
> +		.ufcon		= S5PV210_UFCON_DEFAULT |
> +			S5PV210_UFCON_TXTRIG16 |
> S5PV210_UFCON_RXTRIG16,
>  	},
>  };
> 
> @@ -124,7 +130,7 @@ static void __init aquila_map_io(void)
>  {
>  	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
>  	s3c24xx_init_clocks(24000000);
> -	s3c24xx_init_uarts(smdkv210_uartcfgs,
> ARRAY_SIZE(smdkv210_uartcfgs));
> +	s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
>  }
> 
>  static void __init aquila_machine_init(void)
> --

Will apply.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Thu Jun 24 08:57:00 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 24 Jun 2010 21:57:00 +0900
Subject: [PATCH 2/2] ARM: S5PV210: Fix GONI board UART FIFO mode
	configration
In-Reply-To: <1277354105-13097-2-git-send-email-jy0922.shim@samsung.com>
References: <1277354105-13097-1-git-send-email-jy0922.shim@samsung.com>
	<1277354105-13097-2-git-send-email-jy0922.shim@samsung.com>
Message-ID: <012d01cb139c$bf01c020$3d054060$%kim@samsung.com>

Joonyoung Shim wrote:
> 
> The GONI board uses max UART FIFO size to each UART channels.
> 
> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/mach-s5pv210/mach-goni.c |   16 +++++++++-------
>  1 files changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/mach-goni.c
b/arch/arm/mach-s5pv210/mach-
> goni.c
> index 4863b13..0cfb8db 100644
> --- a/arch/arm/mach-s5pv210/mach-goni.c
> +++ b/arch/arm/mach-s5pv210/mach-goni.c
> @@ -36,9 +36,7 @@
> 
>  #define S5PV210_ULCON_DEFAULT	S3C2410_LCON_CS8
> 
> -#define S5PV210_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
> -				 S5PV210_UFCON_TXTRIG4 |	\
> -				 S5PV210_UFCON_RXTRIG4)
> +#define S5PV210_UFCON_DEFAULT	S3C2410_UFCON_FIFOMODE
> 
>  static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
>  	[0] = {
> @@ -46,28 +44,32 @@ static struct s3c2410_uartcfg goni_uartcfgs[]
__initdata = {
>  		.flags		= 0,
>  		.ucon		= S5PV210_UCON_DEFAULT,
>  		.ulcon		= S5PV210_ULCON_DEFAULT,
> -		.ufcon		= S5PV210_UFCON_DEFAULT,
> +		.ufcon		= S5PV210_UFCON_DEFAULT |
> +			S5PV210_UFCON_TXTRIG256 |
> S5PV210_UFCON_RXTRIG256,
>  	},
>  	[1] = {
>  		.hwport		= 1,
>  		.flags		= 0,
>  		.ucon		= S5PV210_UCON_DEFAULT,
>  		.ulcon		= S5PV210_ULCON_DEFAULT,
> -		.ufcon		= S5PV210_UFCON_DEFAULT,
> +		.ufcon		= S5PV210_UFCON_DEFAULT |
> +			S5PV210_UFCON_TXTRIG64 |
> S5PV210_UFCON_RXTRIG64,
>  	},
>  	[2] = {
>  		.hwport		= 2,
>  		.flags		= 0,
>  		.ucon		= S5PV210_UCON_DEFAULT,
>  		.ulcon		= S5PV210_ULCON_DEFAULT,
> -		.ufcon		= S5PV210_UFCON_DEFAULT,
> +		.ufcon		= S5PV210_UFCON_DEFAULT |
> +			S5PV210_UFCON_TXTRIG16 |
> S5PV210_UFCON_RXTRIG16,
>  	},
>  	[3] = {
>  		.hwport		= 3,
>  		.flags		= 0,
>  		.ucon		= S5PV210_UCON_DEFAULT,
>  		.ulcon		= S5PV210_ULCON_DEFAULT,
> -		.ufcon		= S5PV210_UFCON_DEFAULT,
> +		.ufcon		= S5PV210_UFCON_DEFAULT |
> +			S5PV210_UFCON_TXTRIG16 |
> S5PV210_UFCON_RXTRIG16,
>  	},
>  };
> 
> --

OK..will apply.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Thu Jun 24 09:11:36 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Thu, 24 Jun 2010 22:11:36 +0900
Subject: [PATCH 2/3] ARM: S5P: Add System define for arch_reset()
In-Reply-To: <AANLkTim2s6syCjpl5v_qVloktrzz27JsSrR6kgWqNHUm@mail.gmail.com>
References: <1277332317-30192-1-git-send-email-kgene.kim@samsung.com>
	<1277332317-30192-3-git-send-email-kgene.kim@samsung.com>
	<AANLkTim2s6syCjpl5v_qVloktrzz27JsSrR6kgWqNHUm@mail.gmail.com>
Message-ID: <012e01cb139e$c9ac8bc0$5d05a340$%kim@samsung.com>

Kyungmin Park wrote:
> 
> On Thu, Jun 24, 2010 at 7:31 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> > From: Jongpill Lee <boyko.lee at samsung.com>
> >
> > This patch adds system define for arch_reset() using Watchdog reset.
> > And adds IO mapping for using WDT.
> 
> Are there any reason to use the WDT to system reset?

Yeah, I already commented about that.
Now Samsung SoC hardware engineer recommends to use the reset of watchdog
instead of software reset by restriction of hardware environment.

> As original purpose of WDT. doesn't it better to use system reset?

Original purpose? I think, WDT can be used as software reset.

> Since we use the WDT reset at other purpose. but if you add the WDT
> reset to system reset.
> then we can't control it. bootloader check the reset reason then
> report something wrong at previous operation.

Yeah, I know your needs. If watchdog reset used as software reset, can't
distinguish who call watchdog reset.
And actually, need to check/debug about abnormal reset status when called
watchdog reset.

> 
> So I want to use system reset as original purpose.
> 
Yes, I think so, if can be used SWRESET, will add that functionality.
But right now...no.

(snip)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From jason77.wang at gmail.com  Thu Jun 24 09:11:28 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Thu, 24 Jun 2010 21:11:28 +0800
Subject: [PATCH V3 1/2] mxc: add common debug board for 3-stack platforms
In-Reply-To: <1277385089-7399-1-git-send-email-jason77.wang@gmail.com>
References: <1277385089-7399-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <1277385089-7399-2-git-send-email-jason77.wang@gmail.com>

The debug board is little different for all mxc 3-stack(PDK)
platforms, it is possible here to add a common implementation to
support this board.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/plat-mxc/3ds_debugboard.c              |  202 +++++++++++++++++++++++
 arch/arm/plat-mxc/Kconfig                       |   11 ++
 arch/arm/plat-mxc/Makefile                      |    1 +
 arch/arm/plat-mxc/include/mach/3ds_debugboard.h |   18 ++
 4 files changed, 232 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-mxc/3ds_debugboard.c
 create mode 100644 arch/arm/plat-mxc/include/mach/3ds_debugboard.h

diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
new file mode 100644
index 0000000..639c54a
--- /dev/null
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -0,0 +1,202 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010 Jason Wang <jason77.wang at gmail.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <mach/hardware.h>
+
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR(n)	(n + 0x0)
+/* External UART */
+#define UARTA_BASE_ADDR(n)	(n + 0x8000)
+#define UARTB_BASE_ADDR(n)	(n + 0x10000)
+
+#define BOARD_IO_ADDR(n)	(n + 0x20000)
+/* LED switchs */
+#define LED_SWITCH_REG		0x00
+/* buttons */
+#define SWITCH_BUTTONS_REG	0x08
+/* status, interrupt */
+#define INTR_STATUS_REG	0x10
+#define INTR_MASK_REG		0x38
+#define INTR_RESET_REG		0x20
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER1_REG	0x40
+#define MAGIC_NUMBER2_REG	0x48
+/* CPLD code version */
+#define CPLD_CODE_VER_REG	0x50
+/* magic word for debug CPLD */
+#define MAGIC_NUMBER3_REG	0x58
+/* module reset register*/
+#define MODULE_RESET_REG	0x60
+/* CPU ID and Personality ID */
+#define MCU_BOARD_ID_REG	0x68
+
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_GPIO(irq)	((irq) - MXC_INTERNAL_IRQS)
+
+#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
+#define MXC_MAX_EXP_IO_LINES	16
+
+/* interrupts like external uart , external ethernet etc*/
+#define EXPIO_INT_ENET		(MXC_BOARD_IRQ_START + 0)
+#define EXPIO_INT_XUART_A	(MXC_BOARD_IRQ_START + 1)
+#define EXPIO_INT_XUART_B	(MXC_BOARD_IRQ_START + 2)
+#define EXPIO_INT_BUTTON_A	(MXC_BOARD_IRQ_START + 3)
+#define EXPIO_INT_BUTTON_B	(MXC_BOARD_IRQ_START + 4)
+
+static void __iomem *brd_io;
+static void expio_ack_irq(u32 irq);
+
+static struct resource smsc911x_resources[] = {
+	{
+		.flags = IORESOURCE_MEM,
+	} , {
+		.start = EXPIO_INT_ENET,
+		.end = EXPIO_INT_ENET,
+		.flags = IORESOURCE_IRQ,
+	},
+};
+
+static struct smsc911x_platform_config smsc911x_config = {
+	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+	.flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY,
+};
+
+static struct platform_device smsc_lan9217_device = {
+	.name = "smsc911x",
+	.id = 0,
+	.dev = {
+		.platform_data = &smsc911x_config,
+	},
+	.num_resources = ARRAY_SIZE(smsc911x_resources),
+	.resource = smsc911x_resources,
+};
+
+static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+	u32 imr_val;
+	u32 int_valid;
+	u32 expio_irq;
+
+	desc->chip->mask(irq);	/* irq = gpio irq number */
+
+	imr_val = __raw_readw(brd_io + INTR_MASK_REG);
+	int_valid = __raw_readw(brd_io + INTR_STATUS_REG) & ~imr_val;
+
+	expio_irq = MXC_BOARD_IRQ_START;
+	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+		struct irq_desc *d;
+		if ((int_valid & 1) == 0)
+			continue;
+		d = irq_desc + expio_irq;
+		if (unlikely(!(d->handle_irq)))
+			pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
+		else
+			d->handle_irq(expio_irq, d);
+	}
+
+	desc->chip->ack(irq);
+	desc->chip->unmask(irq);
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * Irq is an expio virtual irq number
+ */
+static void expio_mask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg |= (1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static void expio_ack_irq(u32 irq)
+{
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	__raw_writew(1 << expio, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	expio_mask_irq(irq);
+}
+
+static void expio_unmask_irq(u32 irq)
+{
+	u16 reg;
+	u32 expio = MXC_IRQ_TO_EXPIO(irq);
+
+	reg = __raw_readw(brd_io + INTR_MASK_REG);
+	reg &= ~(1 << expio);
+	__raw_writew(reg, brd_io + INTR_MASK_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+	.ack = expio_ack_irq,
+	.mask = expio_mask_irq,
+	.unmask = expio_unmask_irq,
+};
+
+int __init mxc_expio_init(u32 base, u32 p_irq)
+{
+	int i;
+
+	brd_io = ioremap(BOARD_IO_ADDR(base), SZ_4K);
+	if (brd_io == NULL)
+		return -ENOMEM;
+
+	if ((__raw_readw(brd_io + MAGIC_NUMBER1_REG) != 0xAAAA) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER2_REG) != 0x5555) ||
+	    (__raw_readw(brd_io + MAGIC_NUMBER3_REG) != 0xCAFE)) {
+		pr_info("3-Stack Debug board not detected\n");
+		iounmap(brd_io);
+		brd_io = NULL;
+		return -ENODEV;
+	}
+
+	pr_info("3-Stack Debug board detected, rev = 0x%04X\n",
+		readw(brd_io + CPLD_CODE_VER_REG));
+
+	/*
+	 * Configure INT line as GPIO input
+	 */
+	gpio_request(MXC_IRQ_TO_GPIO(p_irq), "expio_pirq");
+	gpio_direction_input(MXC_IRQ_TO_GPIO(p_irq));
+
+	/* disable the interrupt and clear the status */
+	__raw_writew(0, brd_io + INTR_MASK_REG);
+	__raw_writew(0xFFFF, brd_io + INTR_RESET_REG);
+	__raw_writew(0, brd_io + INTR_RESET_REG);
+	__raw_writew(0x1F, brd_io + INTR_MASK_REG);
+	for (i = MXC_EXP_IO_BASE;
+	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
+		set_irq_chip(i, &expio_irq_chip);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID);
+	}
+	set_irq_type(p_irq, IRQF_TRIGGER_LOW);
+	set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
+
+	/* Register Lan device on the debugboard */
+	smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
+	smsc911x_resources[0].end = LAN9217_BASE_ADDR(base) + 0x100 - 1;
+	platform_device_register(&smsc_lan9217_device);
+
+	return 0;
+}
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 7f7ad6f..8bf917e 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -81,6 +81,17 @@ config MXC_PWM
 	help
 	  Enable support for the i.MX PWM controller(s).
 
+config MXC_DEBUG_BOARD
+	bool "Enable MXC debug board(for 3-stack)"
+	help
+	  The debug board is an integral part of the MXC 3-stack(PDK)
+	  platforms, it can be attached or removed from the peripheral
+	  board. On debug board, several debug devices(ethernet, UART,
+	  buttons, LEDs and JTAG) are implemented. Between the MCU and
+	  these devices, a CPLD is added as a bridge which performs
+	  data/address de-multiplexing and decode, signal level shift,
+	  interrupt control and various board functions.
+
 config MXC_ULPI
 	bool
 
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 895bc3c..c4a24f2 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V1) += audmux-v1.o
 obj-$(CONFIG_ARCH_MXC_AUDMUX_V2) += audmux-v2.o
+obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
diff --git a/arch/arm/plat-mxc/include/mach/3ds_debugboard.h b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
new file mode 100644
index 0000000..a384fdd
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/3ds_debugboard.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __ASM_ARCH_MXC_3DS_DB_H__
+#define __ASM_ARCH_MXC_3DS_DB_H__
+
+extern int __init mxc_expio_init(u32 base, u32 p_irq);
+
+#endif /* __ASM_ARCH_MXC_3DS_DB_H__ */
-- 
1.5.6.5



From jason77.wang at gmail.com  Thu Jun 24 09:11:29 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Thu, 24 Jun 2010 21:11:29 +0800
Subject: [PATCH V3 2/2] mx31_3ds: revert 3ds debug board relate code
In-Reply-To: <1277385089-7399-2-git-send-email-jason77.wang@gmail.com>
References: <1277385089-7399-1-git-send-email-jason77.wang@gmail.com>
	<1277385089-7399-2-git-send-email-jason77.wang@gmail.com>
Message-ID: <1277385089-7399-3-git-send-email-jason77.wang@gmail.com>

Because we add a 3ds debug board support in mxc level, we remove
those redundant codes from board level.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
 arch/arm/mach-mx3/Kconfig                       |    1 +
 arch/arm/mach-mx3/mach-mx31_3ds.c               |  169 +----------------------
 arch/arm/plat-mxc/include/mach/board-mx31_3ds.h |   42 ------
 3 files changed, 5 insertions(+), 207 deletions(-)

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753f..fd422cf 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -58,6 +58,7 @@ config MACH_MX31LITE
 config MACH_MX31_3DS
 	bool "Support MX31PDK (3DS)"
 	select ARCH_MX31
+	select MXC_DEBUG_BOARD
 	help
 	  Include support for MX31PDK (3DS) platform. This includes specific
 	  configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 58e5729..067e418 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -22,7 +22,6 @@
 #include <linux/clk.h>
 #include <linux/irq.h>
 #include <linux/gpio.h>
-#include <linux/smsc911x.h>
 #include <linux/platform_device.h>
 #include <linux/mfd/mc13783.h>
 #include <linux/spi/spi.h>
@@ -42,6 +41,7 @@
 #include <mach/iomux-mx3.h>
 #include <mach/mxc_nand.h>
 #include <mach/spi.h>
+#include <mach/3ds_debugboard.h>
 #include "devices.h"
 
 /*!
@@ -213,173 +213,11 @@ static struct imxuart_platform_data uart_pdata = {
 };
 
 /*
- * Support for the SMSC9217 on the Debug board.
- */
-
-static struct smsc911x_platform_config smsc911x_config = {
-	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
-	.irq_type	= SMSC911X_IRQ_TYPE_PUSH_PULL,
-	.flags		= SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
-	.phy_interface	= PHY_INTERFACE_MODE_MII,
-};
-
-static struct resource smsc911x_resources[] = {
-	{
-		.start		= LAN9217_BASE_ADDR,
-		.end		= LAN9217_BASE_ADDR + 0xff,
-		.flags		= IORESOURCE_MEM,
-	}, {
-		.start		= EXPIO_INT_ENET,
-		.end		= EXPIO_INT_ENET,
-		.flags		= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device smsc911x_device = {
-	.name		= "smsc911x",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(smsc911x_resources),
-	.resource	= smsc911x_resources,
-	.dev		= {
-		.platform_data = &smsc911x_config,
-	},
-};
-
-/*
- * Routines for the CPLD on the debug board. It contains a CPLD handling
- * LEDs, switches, interrupts for Ethernet.
- */
-
-static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
-{
-	uint32_t imr_val;
-	uint32_t int_valid;
-	uint32_t expio_irq;
-
-	imr_val = __raw_readw(CPLD_INT_MASK_REG);
-	int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
-
-	expio_irq = MXC_EXP_IO_BASE;
-	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
-		if ((int_valid & 1) == 0)
-			continue;
-		generic_handle_irq(expio_irq);
-	}
-}
-
-/*
- * Disable an expio pin's interrupt by setting the bit in the imr.
- * @param irq           an expio virtual irq number
- */
-static void expio_mask_irq(uint32_t irq)
-{
-	uint16_t reg;
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* mask the interrupt */
-	reg = __raw_readw(CPLD_INT_MASK_REG);
-	reg |= 1 << expio;
-	__raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-/*
- * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
- * @param irq           an expanded io virtual irq number
- */
-static void expio_ack_irq(uint32_t irq)
-{
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* clear the interrupt status */
-	__raw_writew(1 << expio, CPLD_INT_RESET_REG);
-	__raw_writew(0, CPLD_INT_RESET_REG);
-	/* mask the interrupt */
-	expio_mask_irq(irq);
-}
-
-/*
- * Enable a expio pin's interrupt by clearing the bit in the imr.
- * @param irq           a expio virtual irq number
- */
-static void expio_unmask_irq(uint32_t irq)
-{
-	uint16_t reg;
-	uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
-
-	/* unmask the interrupt */
-	reg = __raw_readw(CPLD_INT_MASK_REG);
-	reg &= ~(1 << expio);
-	__raw_writew(reg, CPLD_INT_MASK_REG);
-}
-
-static struct irq_chip expio_irq_chip = {
-	.ack = expio_ack_irq,
-	.mask = expio_mask_irq,
-	.unmask = expio_unmask_irq,
-};
-
-static int __init mx31_3ds_init_expio(void)
-{
-	int i;
-	int ret;
-
-	/* Check if there's a debug board connected */
-	if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
-	    (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
-	    (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
-		/* No Debug board found */
-		return -ENODEV;
-	}
-
-	pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
-		__raw_readw(CPLD_CODE_VER_REG));
-
-	/*
-	 * Configure INT line as GPIO input
-	 */
-	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
-	if (ret)
-		pr_warning("could not get LAN irq gpio\n");
-	else
-		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-
-	/* Disable the interrupts and clear the status */
-	__raw_writew(0, CPLD_INT_MASK_REG);
-	__raw_writew(0xFFFF, CPLD_INT_RESET_REG);
-	__raw_writew(0, CPLD_INT_RESET_REG);
-	__raw_writew(0x1F, CPLD_INT_MASK_REG);
-	for (i = MXC_EXP_IO_BASE;
-	     i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
-	     i++) {
-		set_irq_chip(i, &expio_irq_chip);
-		set_irq_handler(i, handle_level_irq);
-		set_irq_flags(i, IRQF_VALID);
-	}
-	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
-	set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
-
-	return 0;
-}
-
-/*
- * This structure defines the MX31 memory map.
- */
-static struct map_desc mx31_3ds_io_desc[] __initdata = {
-	{
-		.virtual = MX31_CS5_BASE_ADDR_VIRT,
-		.pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
-		.length = MX31_CS5_SIZE,
-		.type = MT_DEVICE,
-	},
-};
-
-/*
  * Set up static virtual mappings.
  */
 static void __init mx31_3ds_map_io(void)
 {
 	mx31_map_io();
-	iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
 }
 
 /*!
@@ -402,8 +240,9 @@ static void __init mxc_board_init(void)
 	mx31_3ds_usbotg_init();
 	mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
 
-	if (!mx31_3ds_init_expio())
-		platform_device_register(&smsc911x_device);
+	if (!mxc_expio_init(CS5_BASE_ADDR, EXPIO_PARENT_INT))
+		printk(KERN_WARNING "Init of the debugboard failed, all "
+				    "devices on the board are unusable.\n");
 }
 
 static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
index da92933..c26d88d 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
@@ -12,48 +12,6 @@
 #define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
 
 /* Definitions for components on the Debug board */
-
-/* Base address of CPLD controller on the Debug board */
-#define DEBUG_BASE_ADDRESS		CS5_IO_ADDRESS(CS5_BASE_ADDR)
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR		CS5_BASE_ADDR
-
-/* CPLD config and interrupt base address */
-#define CPLD_ADDR			(DEBUG_BASE_ADDRESS + 0x20000)
-
-/* LED switchs */
-#define CPLD_LED_REG			(CPLD_ADDR + 0x00)
-/* buttons */
-#define CPLD_SWITCH_BUTTONS_REG	(EXPIO_ADDR + 0x08)
-/* status, interrupt */
-#define CPLD_INT_STATUS_REG		(CPLD_ADDR + 0x10)
-#define CPLD_INT_MASK_REG		(CPLD_ADDR + 0x38)
-#define CPLD_INT_RESET_REG		(CPLD_ADDR + 0x20)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER1_REG		(CPLD_ADDR + 0x40)
-#define CPLD_MAGIC_NUMBER2_REG		(CPLD_ADDR + 0x48)
-/* CPLD code version */
-#define CPLD_CODE_VER_REG		(CPLD_ADDR + 0x50)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER3_REG		(CPLD_ADDR + 0x58)
-/* module reset register */
-#define CPLD_MODULE_RESET_REG		(CPLD_ADDR + 0x60)
-/* CPU ID and Personality ID */
-#define CPLD_MCU_BOARD_ID_REG		(CPLD_ADDR + 0x68)
-
-/* CPLD IRQ line for external uart, external ethernet etc */
 #define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
 
-#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_ENET		(MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_XUART_A	(MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_XUART_B	(MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_BUTTON_A	(MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_BUTTON_B	(MXC_EXP_IO_BASE + 4)
-
-#define MXC_MAX_EXP_IO_LINES	16
-
 #endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
-- 
1.5.6.5



From jassisinghbrar at gmail.com  Thu Jun 24 09:19:20 2010
From: jassisinghbrar at gmail.com (Jassi Brar)
Date: Thu, 24 Jun 2010 22:19:20 +0900
Subject: [PATCH 2/3] ARM: S5P: Add System define for arch_reset()
In-Reply-To: <012e01cb139e$c9ac8bc0$5d05a340$%kim@samsung.com>
References: <1277332317-30192-1-git-send-email-kgene.kim@samsung.com>
	<1277332317-30192-3-git-send-email-kgene.kim@samsung.com>
	<AANLkTim2s6syCjpl5v_qVloktrzz27JsSrR6kgWqNHUm@mail.gmail.com>
	<012e01cb139e$c9ac8bc0$5d05a340$%kim@samsung.com>
Message-ID: <AANLkTinpn_cNnIS5vZrY8DMe9t2bg2KMHS4CNThoIt0m@mail.gmail.com>

On Thu, Jun 24, 2010 at 10:11 PM, Kukjin Kim <kgene.kim at samsung.com> wrote:
> Kyungmin Park wrote:
>>
>> On Thu, Jun 24, 2010 at 7:31 AM, Kukjin Kim <kgene.kim at samsung.com> wrote:
>> > From: Jongpill Lee <boyko.lee at samsung.com>
>> >
>> > This patch adds system define for arch_reset() using Watchdog reset.
>> > And adds IO mapping for using WDT.
>>
>> Are there any reason to use the WDT to system reset?
>
> Yeah, I already commented about that.
> Now Samsung SoC hardware engineer recommends to use the reset of watchdog
> instead of software reset by restriction of hardware environment.
>
>> As original purpose of WDT. doesn't it better to use system reset?
>
> Original purpose? I think, WDT can be used as software reset.
I agree with Kyungmin Park.
Ideally WDT shud be used as a way to detect deadlock/starvation. When
the bootloader realizes the reset was due to WDT, different course of action
should be taken than that for reset due to, say, reboot command.


From jason77.wang at gmail.com  Thu Jun 24 09:11:27 2010
From: jason77.wang at gmail.com (Jason Wang)
Date: Thu, 24 Jun 2010 21:11:27 +0800
Subject: [PATCH V3 0/2]Add mxc common 3ds debugboard support
Message-ID: <1277385089-7399-1-git-send-email-jason77.wang@gmail.com>

part2(v3):

Diff VS v1:
1) change file name from cpld_debugboard to 3ds_debugboard.
2) move all macro definitions from 3ds_debugboard.h to 3ds_debugboard.c
3) add a wrapper function in the 3ds_debugboard.c for lan9127 init.

Diff VS v2:
1) remove wrapper function for lan in 3ds_debugboard.c and 3ds_debugboard.h,
   move registration of lan device to mxc_expio_init().
2) modify calling 3ds debugboard related init function in mach-mx31_3ds.c

 [PATCH 1/2] mxc: add common debug board for 3-stack platforms
 [PATCH 2/2] mx31_3ds: revert 3ds debug board relate code




From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:49 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:49 +0200
Subject: [PATCH 53/61] ARM: imx: dynamically register spi_imx devices (imx35)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-54-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/Kconfig           |    1 +
 arch/arm/mach-mx3/devices-imx35.h   |    5 +++
 arch/arm/mach-mx3/devices.c         |   61 -----------------------------------
 arch/arm/mach-mx3/devices.h         |    5 ---
 arch/arm/mach-mx3/mach-pcm037_eet.c |    7 +---
 5 files changed, 8 insertions(+), 71 deletions(-)

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 60d58a6..a8018e8 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -45,6 +45,7 @@ config MACH_PCM037
 config MACH_PCM037_EET
 	bool "Support pcm037 EET board extensions"
 	depends on MACH_PCM037
+	select IMX_HAVE_PLATFORM_SPI_IMX
 	help
 	  Add support for PCM037 EET baseboard extensions. If you are using the
 	  OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index 6d993ae..b595fa6 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -18,3 +18,8 @@
 
 #define imx35_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
+
+#define imx35_add_spi_imx0(pdata)	\
+	imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata)
+#define imx35_add_spi_imx1(pdata)	\
+	imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 02d05ea..dd90ee9 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -380,67 +380,6 @@ struct platform_device mxc_usbh2 = {
 };
 
 #if defined(CONFIG_ARCH_MX35)
-/*
- * SPI master controller
- * 3 channels
- */
-static struct resource mxc_spi_0_resources[] = {
-	{
-	       .start = CSPI1_BASE_ADDR,
-	       .end = CSPI1_BASE_ADDR + SZ_4K - 1,
-	       .flags = IORESOURCE_MEM,
-	}, {
-	       .start = MXC_INT_CSPI1,
-	       .end = MXC_INT_CSPI1,
-	       .flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource mxc_spi_1_resources[] = {
-	{
-		.start = CSPI2_BASE_ADDR,
-		.end = CSPI2_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MXC_INT_CSPI2,
-		.end = MXC_INT_CSPI2,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-static struct resource mxc_spi_2_resources[] = {
-	{
-		.start = CSPI3_BASE_ADDR,
-		.end = CSPI3_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MXC_INT_CSPI3,
-		.end = MXC_INT_CSPI3,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_spi_device0 = {
-	.name = "spi_imx",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxc_spi_0_resources),
-	.resource = mxc_spi_0_resources,
-};
-
-struct platform_device mxc_spi_device1 = {
-	.name = "spi_imx",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(mxc_spi_1_resources),
-	.resource = mxc_spi_1_resources,
-};
-
-struct platform_device mxc_spi_device2 = {
-	.name = "spi_imx",
-	.id = 2,
-	.num_resources = ARRAY_SIZE(mxc_spi_2_resources),
-	.resource = mxc_spi_2_resources,
-};
-
 static struct resource mxc_fec_resources[] = {
 	{
 		.start	= MXC_FEC_BASE_ADDR,
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index d22a327..9380cd9 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -16,11 +16,6 @@ extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
 extern struct platform_device mxc_rnga_device;
-#if defined(CONFIG_ARCH_MX35)
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-extern struct platform_device mxc_spi_device2;
-#endif
 extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
 extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
index 8d38600..c8b9821 100644
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ b/arch/arm/mach-mx3/mach-pcm037_eet.c
@@ -13,9 +13,6 @@
 #include <linux/spi/spi.h>
 
 #include <mach/common.h>
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-#include <mach/spi.h>
-#endif
 #include <mach/iomux-mx3.h>
 
 #include <asm/mach-types.h>
@@ -64,7 +61,7 @@ static struct spi_board_info pcm037_spi_dev[] = {
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
 static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)};
 
-struct spi_imx_master pcm037_spi1_master = {
+static const struct spi_imx_master pcm037_spi1_pdata __initconst = {
 	.chipselect = pcm037_spi1_cs,
 	.num_chipselect = ARRAY_SIZE(pcm037_spi1_cs),
 };
@@ -184,7 +181,7 @@ static int eet_init_devices(void)
 	/* SPI */
 	spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-	mxc_register_device(&mxc_spi_device0, &pcm037_spi1_master);
+	imx35_add_spi_imx0(&pcm037_spi1_pdata);
 #endif
 
 	platform_device_register(&pcm037_gpio_keys_device);
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:03 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:03 +0200
Subject: [PATCH 07/61] ARM: mx3/kzm_arm11_01: fold board header in its only
	user
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-8-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/mach-kzm_arm11_01.c           |   18 ++++++++++-
 arch/arm/plat-mxc/include/mach/board-kzmarm11.h |   39 -----------------------
 2 files changed, 17 insertions(+), 40 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-kzmarm11.h

diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index f085d5d..e60f5da 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -37,7 +37,6 @@
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 
-#include <mach/board-kzmarm11.h>
 #include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/imx-uart.h>
@@ -51,6 +50,23 @@
 	IMX_IO_ADDRESS(x, MX31_CS5) ?:					\
 	MX31_IO_ADDRESS(x))
 
+/*
+ *  KZM-ARM11-01 Board Control Registers on FPGA
+ */
+#define KZM_ARM11_CTL1		(MX31_CS4_BASE_ADDR + 0x1000)
+#define KZM_ARM11_CTL2		(MX31_CS4_BASE_ADDR + 0x1001)
+#define KZM_ARM11_RSW1		(MX31_CS4_BASE_ADDR + 0x1002)
+#define KZM_ARM11_BACK_LIGHT	(MX31_CS4_BASE_ADDR + 0x1004)
+#define KZM_ARM11_FPGA_REV	(MX31_CS4_BASE_ADDR + 0x1008)
+#define KZM_ARM11_7SEG_LED	(MX31_CS4_BASE_ADDR + 0x1010)
+#define KZM_ARM11_LEDS		(MX31_CS4_BASE_ADDR + 0x1020)
+#define KZM_ARM11_DIPSW2	(MX31_CS4_BASE_ADDR + 0x1003)
+
+/*
+ * External UART for touch panel on FPGA
+ */
+#define KZM_ARM11_16550		(MX31_CS4_BASE_ADDR + 0x1050)
+
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
 /*
  * KZM-ARM11-01 has an external UART on FPGA
diff --git a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h b/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
deleted file mode 100644
index 93cc66f..0000000
--- a/arch/arm/plat-mxc/include/mach/board-kzmarm11.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *  Copyright (C) 2009  Yoichi Yuasa <yuasa at linux-mips.org>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
- */
-#ifndef __ARM_ARCH_BOARD_KZM_ARM11_H
-#define __ARM_ARCH_BOARD_KZM_ARM11_H
-
-/*
- *  KZM-ARM11-01 Board Control Registers on FPGA
- */
-#define KZM_ARM11_CTL1		(MX31_CS4_BASE_ADDR + 0x1000)
-#define KZM_ARM11_CTL2		(MX31_CS4_BASE_ADDR + 0x1001)
-#define KZM_ARM11_RSW1		(MX31_CS4_BASE_ADDR + 0x1002)
-#define KZM_ARM11_BACK_LIGHT	(MX31_CS4_BASE_ADDR + 0x1004)
-#define KZM_ARM11_FPGA_REV	(MX31_CS4_BASE_ADDR + 0x1008)
-#define KZM_ARM11_7SEG_LED	(MX31_CS4_BASE_ADDR + 0x1010)
-#define KZM_ARM11_LEDS		(MX31_CS4_BASE_ADDR + 0x1020)
-#define KZM_ARM11_DIPSW2	(MX31_CS4_BASE_ADDR + 0x1003)
-
-/*
- * External UART for touch panel on FPGA
- */
-#define KZM_ARM11_16550		(MX31_CS4_BASE_ADDR + 0x1050)
-
-#endif /* __ARM_ARCH_BOARD_KZM_ARM11_H */
-
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:22 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:22 +0200
Subject: [PATCH 26/61] ARM: imx: prepare deprecating ARCH_MX1, MACH_MX2,
	MACH_MX21 and MACH_MX27
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-27-git-send-email-u.kleine-koenig@pengutronix.de>

MACH_... is reserved for machine support, so use SOC as prefix, not MACH.

This introduces new symbols SOC_IMX1, SOC_IMX21 and SOC_IMX27.  They are
selected by the old symbols for now.  There is no substitute for MACH_MX2
as most usages of MX2 only means MX21 + MX27 but not MX25.

Later the choice about CPU and CPU family should go away and the individual
machines should select the right SOC symbol.  This is a precondition to
support more than one SOC in a single kernel image.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 08002df..5edead2 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -2,7 +2,6 @@ if ARCH_MX1
 
 config SOC_IMX1
 	select CPU_ARM920T
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	bool
 
@@ -28,14 +27,12 @@ if ARCH_MX2
 config SOC_IMX21
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	bool
 
 config SOC_IMX27
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
-	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	bool
 
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:09 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:09 +0200
Subject: [PATCH 13/61] ARM: mxc: grammar fix
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-14-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 .../plat-mxc/include/mach/board-eukrea_cpuimx27.h  |    2 +-
 arch/arm/plat-mxc/include/mach/board-mx31lilly.h   |    2 +-
 arch/arm/plat-mxc/include/mach/board-mx31lite.h    |    2 +-
 arch/arm/plat-mxc/include/mach/board-mx31moboard.h |    2 +-
 arch/arm/plat-mxc/include/mach/board-pcm038.h      |    2 +-
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
index a1fd583..45b2fb8 100644
--- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
+++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
@@ -25,7 +25,7 @@
 #ifndef __ASSEMBLY__
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  * TODO: Add your own baseboard init function and call it from
  * inside eukrea_cpuimx27_init().
  *
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
index eb5a502..0df71bf 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
@@ -31,7 +31,7 @@ enum mx31lilly_boards {
 
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  */
 
 extern void mx31lilly_db_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 2b2da03..c1ad0ae 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -32,7 +32,7 @@ enum mx31lite_boards {
 
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  */
 
 extern void mx31lite_db_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index 36ff3ce..de14543 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -31,7 +31,7 @@ enum mx31moboard_boards {
 
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  */
 
 extern void mx31moboard_devboard_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 410f978..6f371e3 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -22,7 +22,7 @@
 #ifndef __ASSEMBLY__
 /*
  * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
+ * its own devices, it calls the baseboard's init function.
  * TODO: Add your own baseboard init function and call it from
  * inside pcm038_init().
  *
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:44 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:44 +0200
Subject: [PATCH 48/61] ARM: imx: dynamically register spi_imx devices (generic
	part)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-49-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/plat-mxc/devices/Kconfig               |    3 ++
 arch/arm/plat-mxc/devices/Makefile              |    1 +
 arch/arm/plat-mxc/devices/platform-spi_imx.c    |   30 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/devices-common.h |    5 ++++
 4 files changed, 39 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-mxc/devices/platform-spi_imx.c

diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index c50a7d6..166c0c8 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -3,3 +3,6 @@ config IMX_HAVE_PLATFORM_IMX_I2C
 
 config IMX_HAVE_PLATFORM_MXC_NAND
 	bool
+
+config IMX_HAVE_PLATFORM_SPI_IMX
+	bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 4a2b2de..ceb6a42 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
new file mode 100644
index 0000000..2831a6d
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_spi_imx(int id,
+		resource_size_t iobase, resource_size_t iosize, int irq,
+		const struct spi_imx_master *pdata)
+{
+	struct resource res[] = {
+		{
+			.start = iobase,
+			.end = iobase + iosize - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = irq,
+			.end = irq,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+
+	return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res),
+			pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 8388f90..f67df87 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -24,3 +24,8 @@ struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
 		int irq, const struct mxc_nand_platform_data *pdata);
 struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
 		int irq, const struct mxc_nand_platform_data *pdata);
+
+#include <mach/spi.h>
+struct platform_device *__init imx_add_spi_imx(int id,
+		resource_size_t iobase, resource_size_t iosize, int irq,
+		const struct spi_imx_master *pdata);
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:13 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:13 +0200
Subject: [PATCH 17/61] ARM: imx: fold serial.c into devices.c
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-18-git-send-email-u.kleine-koenig@pengutronix.de>

... and use cpp magic to reduce repetition.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Makefile  |    2 +-
 arch/arm/mach-imx/devices.c |   32 ++++++++++
 arch/arm/mach-imx/serial.c  |  141 -------------------------------------------
 3 files changed, 33 insertions(+), 142 deletions(-)
 delete mode 100644 arch/arm/mach-imx/serial.c

diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 068f493..9d57ba6 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y	:=  devices.o serial.o
+obj-y	:=  devices.o
 
 obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
 
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index e708bfd..08ae763 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -32,11 +32,13 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/dma-mapping.h>
+#include <linux/serial.h>
 
 #include <mach/irqs.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/mmc.h>
+#include <mach/imx-uart.h>
 
 #include "devices.h"
 
@@ -424,6 +426,36 @@ struct platform_device mxc_usbh2 = {
 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 
+#define DEFINE_IMX_UART_DEVICE(n, baseaddr, irq)			\
+	static struct resource imx2x_uart_resources ## n[] = {		\
+		{							\
+			.start = baseaddr,				\
+			.end = baseaddr + 0xb5,				\
+			.flags = IORESOURCE_MEM,			\
+		}, {							\
+			.start = irq,					\
+			.end = irq,					\
+			.flags = IORESOURCE_IRQ,			\
+		},							\
+	};								\
+									\
+	struct platform_device mxc_uart_device ## n = {			\
+		.name = "imx-uart",					\
+		.id = n,						\
+		.num_resources = ARRAY_SIZE(imx2x_uart_resources ## n),	\
+		.resource = imx2x_uart_resources ## n,			\
+	}
+
+DEFINE_IMX_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
+DEFINE_IMX_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
+DEFINE_IMX_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
+DEFINE_IMX_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
+
+#ifdef CONFIG_MACH_MX27
+DEFINE_IMX_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
+DEFINE_IMX_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
+#endif
+
 /* GPIO port description */
 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq)				\
 	{								\
diff --git a/arch/arm/mach-imx/serial.c b/arch/arm/mach-imx/serial.c
deleted file mode 100644
index 1c0c835..0000000
--- a/arch/arm/mach-imx/serial.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel at pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <mach/hardware.h>
-#include <mach/imx-uart.h>
-#include "devices.h"
-
-static struct resource uart0[] = {
-	{
-		.start = MX2x_UART1_BASE_ADDR,
-		.end = MX2x_UART1_BASE_ADDR + 0x0B5,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MX2x_INT_UART1,
-		.end = MX2x_INT_UART1,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device0 = {
-	.name = "imx-uart",
-	.id = 0,
-	.resource = uart0,
-	.num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-	{
-		.start = MX2x_UART2_BASE_ADDR,
-		.end = MX2x_UART2_BASE_ADDR + 0x0B5,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MX2x_INT_UART2,
-		.end = MX2x_INT_UART2,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device1 = {
-	.name = "imx-uart",
-	.id = 1,
-	.resource = uart1,
-	.num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-	{
-		.start = MX2x_UART3_BASE_ADDR,
-		.end = MX2x_UART3_BASE_ADDR + 0x0B5,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MX2x_INT_UART3,
-		.end = MX2x_INT_UART3,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device2 = {
-	.name = "imx-uart",
-	.id = 2,
-	.resource = uart2,
-	.num_resources = ARRAY_SIZE(uart2),
-};
-
-static struct resource uart3[] = {
-	{
-		.start = MX2x_UART4_BASE_ADDR,
-		.end = MX2x_UART4_BASE_ADDR + 0x0B5,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MX2x_INT_UART4,
-		.end = MX2x_INT_UART4,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device3 = {
-	.name = "imx-uart",
-	.id = 3,
-	.resource = uart3,
-	.num_resources = ARRAY_SIZE(uart3),
-};
-
-#ifdef CONFIG_MACH_MX27
-static struct resource uart4[] = {
-	{
-		.start = MX27_UART5_BASE_ADDR,
-		.end = MX27_UART5_BASE_ADDR + 0x0B5,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MX27_INT_UART5,
-		.end = MX27_INT_UART5,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device4 = {
-	.name = "imx-uart",
-	.id = 4,
-	.resource = uart4,
-	.num_resources = ARRAY_SIZE(uart4),
-};
-
-static struct resource uart5[] = {
-	{
-		.start = MX27_UART6_BASE_ADDR,
-		.end = MX27_UART6_BASE_ADDR + 0x0B5,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MX27_INT_UART6,
-		.end = MX27_INT_UART6,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device5 = {
-	.name = "imx-uart",
-	.id = 5,
-	.resource = uart5,
-	.num_resources = ARRAY_SIZE(uart5),
-};
-#endif
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:57 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:57 +0200
Subject: [PATCH 61/61] ARM: mx3: complement uart init routine with an exit
	routine
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-62-git-send-email-u.kleine-koenig@pengutronix.de>

moboard_uart0_init requests a gpio.   Without an exit function that
frees that gpio again binding the uart a second time doesn't work.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/mach-mx31moboard.c |   18 +++++++++++++++---
 1 files changed, 15 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 95633bb..67776bc 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -125,13 +125,25 @@ static struct platform_device mx31moboard_flash = {
 
 static int moboard_uart0_init(struct platform_device *pdev)
 {
-	gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
-	gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
-	return 0;
+	int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
+	if (ret)
+		return ret;
+
+	ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
+	if (ret)
+		gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
+
+	return ret;
+}
+
+static void moboard_uart0_exit(struct platform_device *pdev)
+{
+	gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
 }
 
 static const struct imxuart_platform_data uart0_pdata __initconst = {
 	.init = moboard_uart0_init,
+	.exit = moboard_uart0_exit,
 };
 
 static const struct imxuart_platform_data uart4_pdata __initconst = {
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:34 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:34 +0200
Subject: [PATCH 38/61] ARM: imx: Change the way nand devices are registered
	(imx27)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-39-git-send-email-u.kleine-koenig@pengutronix.de>

Make use of new mechanism to register a nand device.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig         |    5 +++++
 arch/arm/mach-imx/devices-imx27.h |   13 +++++++++++++
 arch/arm/mach-imx/devices.c       |   24 ------------------------
 arch/arm/mach-imx/devices.h       |    3 ---
 arch/arm/mach-imx/mach-cpuimx27.c |    7 ++++---
 arch/arm/mach-imx/mach-mx27ads.c  |    6 ++++--
 arch/arm/mach-imx/mach-mxt_td60.c |    6 ++++--
 arch/arm/mach-imx/mach-pca100.c   |    6 ++++--
 arch/arm/mach-imx/mach-pcm038.c   |    6 ++++--
 9 files changed, 38 insertions(+), 38 deletions(-)
 create mode 100644 arch/arm/mach-imx/devices-imx27.h

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 2367182..5af1c22 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -81,12 +81,14 @@ comment "MX27 platforms:"
 
 config MACH_MX27ADS
 	bool "MX27ADS platform"
+	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for MX27ADS platform. This includes specific
 	  configurations for the board and its peripherals.
 
 config MACH_PCM038
 	bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
+	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
 	  Include support for phyCORE-i.MX27 (aka pcm038) platform. This
@@ -108,6 +110,7 @@ endchoice
 
 config MACH_CPUIMX27
 	bool "Eukrea CPUIMX27 module"
+	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for Eukrea CPUIMX27 platform. This includes
 	  specific configurations for the module and its peripherals.
@@ -147,6 +150,7 @@ config MACH_IMX27LITE
 
 config MACH_PCA100
 	bool "Phytec phyCARD-s (pca100)"
+	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
 	  Include support for phyCARD-s (aka pca100) platform. This
@@ -154,6 +158,7 @@ config MACH_PCA100
 
 config MACH_MXT_TD60
 	bool "Maxtrack i-MXT TD60"
+	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for i-MXT (aka td60) platform. This
 	  includes specific configurations for the module and its peripherals.
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
new file mode 100644
index 0000000..b2f6a12
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx27.h>
+#include <mach/devices-common.h>
+
+#define imx27_add_mxc_nand(pdata)	\
+	imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index dbd1460..3a599e9 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -337,30 +337,6 @@ struct platform_device mxc_w1_master_device = {
 	.resource = mxc_w1_master_resources,
 };
 
-#define DEFINE_MXC_NAND_DEVICE(pfx, baseaddr, irq)			\
-	static struct resource pfx ## _nand_resources[] = {		\
-		{							\
-			.start = baseaddr,				\
-			.end = baseaddr + SZ_4K - 1,			\
-			.flags = IORESOURCE_MEM,			\
-		}, {							\
-			.start = irq,					\
-			.end = irq,					\
-			.flags = IORESOURCE_IRQ,			\
-		},							\
-	};								\
-									\
-	struct platform_device pfx ## _nand_device = {			\
-		.name = "mxc_nand",					\
-		.id = 0,						\
-		.num_resources = ARRAY_SIZE(pfx ## _nand_resources),	\
-		.resource = pfx ## _nand_resources,			\
-	}
-
-#ifdef CONFIG_MACH_MX27
-DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
-#endif
-
 /*
  * lcdc:
  * - i.MX1: the basic controller
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index d3c381f..4ce7eef 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -26,9 +26,6 @@ extern struct platform_device imx2x_uart_device4;
 extern struct platform_device imx2x_uart_device5;
 #endif
 extern struct platform_device mxc_w1_master_device;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device imx27_nand_device;
-#endif
 extern struct platform_device mxc_fb_device;
 extern struct platform_device mxc_fec_device;
 extern struct platform_device mxc_pwm_device;
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 866a99a..5d07c2a 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -40,6 +40,7 @@
 #include <mach/imx-uart.h>
 #include <mach/mxc_nand.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static int eukrea_cpuimx27_pins[] = {
@@ -119,7 +120,8 @@ static struct imxuart_platform_data uart_pdata[] = {
 	},
 };
 
-static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
+static const struct mxc_nand_platform_data
+cpuimx27_nand_board_info __initconst = {
 	.width = 1,
 	.hw_ecc = 1,
 };
@@ -189,8 +191,7 @@ static void __init eukrea_cpuimx27_init(void)
 
 	mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]);
 
-	mxc_register_device(&imx27_nand_device,
-			&eukrea_cpuimx27_nand_board_info);
+	imx27_add_mxc_nand(&cpuimx27_nand_board_info);
 
 	i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
 				ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 186b93a..1a3ebf5 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -35,6 +35,7 @@
 #include <mach/imxfb.h>
 #include <mach/mmc.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 /*
@@ -166,7 +167,8 @@ static unsigned int mx27ads_pins[] = {
 	PB9_PF_SD2_CLK,
 };
 
-static struct mxc_nand_platform_data mx27ads_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx27ads_nand_board_info __initconst = {
 	.width = 1,
 	.hw_ecc = 1,
 };
@@ -315,7 +317,7 @@ static void __init mx27ads_board_init(void)
 	mxc_register_device(&imx2x_uart_device3, &uart_pdata[3]);
 	mxc_register_device(&imx2x_uart_device4, &uart_pdata[4]);
 	mxc_register_device(&imx2x_uart_device5, &uart_pdata[5]);
-	mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info);
+	imx27_add_mxc_nand(&mx27ads_nand_board_info);
 
 	/* only the i2c master 1 is used on this CPU card */
 	i2c_register_board_info(1, mx27ads_i2c_devices,
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 0e5ddba..447c68f 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -36,6 +36,7 @@
 #include <mach/imxfb.h>
 #include <mach/mmc.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static unsigned int mxt_td60_pins[] __initdata = {
@@ -124,7 +125,8 @@ static unsigned int mxt_td60_pins[] __initdata = {
 	PB9_PF_SD2_CLK,
 };
 
-static struct mxc_nand_platform_data mxt_td60_nand_board_info = {
+static const struct mxc_nand_platform_data
+mxt_td60_nand_board_info __initconst = {
 	.width = 1,
 	.hw_ecc = 1,
 };
@@ -253,7 +255,7 @@ static void __init mxt_td60_board_init(void)
 	mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]);
 	mxc_register_device(&imx2x_uart_device1, &uart_pdata[1]);
 	mxc_register_device(&imx2x_uart_device2, &uart_pdata[2]);
-	mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info);
+	imx27_add_mxc_nand(&mxt_td60_nand_board_info);
 
 	i2c_register_board_info(0, mxt_td60_i2c_devices,
 				ARRAY_SIZE(mxt_td60_i2c_devices));
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 984c4ca..6efbc6e 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -50,6 +50,7 @@
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 #define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
@@ -137,7 +138,8 @@ static struct imxuart_platform_data uart_pdata = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct mxc_nand_platform_data pca100_nand_board_info = {
+static const struct mxc_nand_platform_data
+pca100_nand_board_info __initconst = {
 	.width = 1,
 	.hw_ecc = 1,
 };
@@ -325,7 +327,7 @@ static void __init pca100_init(void)
 	mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
 	mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
 
-	mxc_register_device(&imx27_nand_device, &pca100_nand_board_info);
+	imx27_add_mxc_nand(&pca100_nand_board_info);
 
 	/* only the i2c master 1 is used on this CPU card */
 	i2c_register_board_info(1, pca100_i2c_devices,
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index b6a15ba..bc44d6f 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -43,6 +43,7 @@
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static int pcm038_pins[] = {
@@ -172,7 +173,8 @@ static struct imxuart_platform_data uart_pdata[] = {
 	},
 };
 
-static struct mxc_nand_platform_data pcm038_nand_board_info = {
+static const struct mxc_nand_platform_data
+pcm038_nand_board_info __initconst = {
 	.width = 1,
 	.hw_ecc = 1,
 };
@@ -310,7 +312,7 @@ static void __init pcm038_init(void)
 	mxc_register_device(&imx2x_uart_device2, &uart_pdata[2]);
 
 	mxc_gpio_mode(PE16_AF_OWIRE);
-	mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info);
+	imx27_add_mxc_nand(&pcm038_nand_board_info);
 
 	/* only the i2c master 1 is used on this CPU card */
 	i2c_register_board_info(1, pcm038_i2c_devices,
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:33 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:33 +0200
Subject: [PATCH 37/61] ARM: imx: Change the way nand devices are registered
	(imx25)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-38-git-send-email-u.kleine-koenig@pengutronix.de>

Make use of new mechanism to register a nand device.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx25/Kconfig         |    1 +
 arch/arm/mach-mx25/devices-imx25.h |   13 +++++++++++++
 arch/arm/mach-mx25/devices.c       |   20 --------------------
 arch/arm/mach-mx25/devices.h       |    1 -
 arch/arm/mach-mx25/mach-mx25_3ds.c |   10 ++++++----
 5 files changed, 20 insertions(+), 25 deletions(-)
 create mode 100644 arch/arm/mach-mx25/devices-imx25.h

diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index 54d2173..3c4f1ee 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -4,5 +4,6 @@ comment "MX25 platforms:"
 
 config MACH_MX25_3DS
 	bool "Support MX25PDK (3DS) Platform"
+	select IMX_HAVE_PLATFORM_MXC_NAND
 
 endif
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
new file mode 100644
index 0000000..f8d4ee0
--- /dev/null
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx25.h>
+#include <mach/devices-common.h>
+
+#define imx25_add_mxc_nand(pdata)	\
+	imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 80f3131..e1c3cd1 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -439,26 +439,6 @@ struct platform_device mx25_fec_device = {
 	.resource	= mx25_fec_resources,
 };
 
-static struct resource mxc_nand_resources[] = {
-	{
-		.start	= MX25_NFC_BASE_ADDR,
-		.end	= MX25_NFC_BASE_ADDR + 0x1fff,
-		.flags	= IORESOURCE_MEM,
-	},
-	{
-		.start	= MX25_INT_NANDFC,
-		.end	= MX25_INT_NANDFC,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_nand_device = {
-	.name		= "mxc_nand",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(mxc_nand_resources),
-	.resource	= mxc_nand_resources,
-};
-
 static struct resource mx25_rtc_resources[] = {
 	{
 		.start	= MX25_DRYICE_BASE_ADDR,
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index cee12c0..f212c93 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -18,7 +18,6 @@ extern struct platform_device mxc_i2c_device0;
 extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_i2c_device2;
 extern struct platform_device mx25_fec_device;
-extern struct platform_device mxc_nand_device;
 extern struct platform_device mx25_rtc_device;
 extern struct platform_device mx25_fb_device;
 extern struct platform_device mxc_wdt;
diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-mx25/mach-mx25_3ds.c
index 26ba246..e1e9886 100644
--- a/arch/arm/mach-mx25/mach-mx25_3ds.c
+++ b/arch/arm/mach-mx25/mach-mx25_3ds.c
@@ -40,11 +40,12 @@
 #include <mach/common.h>
 #include <mach/imx-uart.h>
 #include <mach/mx25.h>
-#include <mach/mxc_nand.h>
 #include <mach/imxfb.h>
-#include "devices.h"
 #include <mach/iomux-mx25.h>
 
+#include "devices-imx25.h"
+#include "devices.h"
+
 static struct imxuart_platform_data uart_pdata = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
@@ -109,7 +110,8 @@ static void __init mx25pdk_fec_reset(void)
 	gpio_set_value(FEC_RESET_B_GPIO, 1);
 }
 
-static struct mxc_nand_platform_data mx25pdk_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx25pdk_nand_board_info __initconst = {
 	.width		= 1,
 	.hw_ecc		= 1,
 	.flash_bbt	= 1,
@@ -150,7 +152,7 @@ static void __init mx25pdk_init(void)
 
 	mxc_register_device(&mxc_uart_device0, &uart_pdata);
 	mxc_register_device(&mxc_usbh2, NULL);
-	mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info);
+	imx25_add_mxc_nand(&mx25pdk_nand_board_info);
 	mxc_register_device(&mx25_rtc_device, NULL);
 	mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
 
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:50 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:50 +0200
Subject: [PATCH 54/61] ARM: imx: dynamically register imx-uart devices
	(generic part)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-55-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/plat-mxc/devices/Kconfig               |    3 +
 arch/arm/plat-mxc/devices/Makefile              |    1 +
 arch/arm/plat-mxc/devices/platform-imx-uart.c   |   60 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/devices-common.h |   11 ++++
 4 files changed, 75 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-mxc/devices/platform-imx-uart.c

diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index 166c0c8..09230f8 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -1,6 +1,9 @@
 config IMX_HAVE_PLATFORM_IMX_I2C
 	bool
 
+config IMX_HAVE_PLATFORM_IMX_UART
+	bool
+
 config IMX_HAVE_PLATFORM_MXC_NAND
 	bool
 
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index ceb6a42..5ecbb24 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -1,3 +1,4 @@
 obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
new file mode 100644
index 0000000..fa3dff1
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_imx_uart_3irq(int id,
+		resource_size_t iobase, resource_size_t iosize,
+		resource_size_t irqrx, resource_size_t irqtx,
+		resource_size_t irqrts,
+		const struct imxuart_platform_data *pdata)
+{
+	struct resource res[] = {
+		{
+			.start = iobase,
+			.end = iobase + iosize - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = irqrx,
+			.end = irqrx,
+			.flags = IORESOURCE_IRQ,
+		}, {
+			.start = irqtx,
+			.end = irqtx,
+			.flags = IORESOURCE_IRQ,
+		}, {
+			.start = irqrts,
+			.end = irqrx,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+
+	return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
+			pdata, sizeof(*pdata));
+}
+
+struct platform_device *__init imx_add_imx_uart_1irq(int id,
+		resource_size_t iobase, resource_size_t iosize,
+		resource_size_t irq,
+		const struct imxuart_platform_data *pdata)
+{
+	struct resource res[] = {
+		{
+			.start = iobase,
+			.end = iobase + iosize - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = irq,
+			.end = irq,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+
+	return imx_add_platform_device("imx-uart", id, res, ARRAY_SIZE(res),
+			pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index f67df87..05c8d3f 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -19,6 +19,17 @@ struct platform_device *__init imx_add_imx_i2c(int id,
 		resource_size_t iobase, resource_size_t iosize, int irq,
 		const struct imxi2c_platform_data *pdata);
 
+#include <mach/imx-uart.h>
+struct platform_device *__init imx_add_imx_uart_3irq(int id,
+		resource_size_t iobase, resource_size_t iosize,
+		resource_size_t irqrx, resource_size_t irqtx,
+		resource_size_t irqrts,
+		const struct imxuart_platform_data *pdata);
+struct platform_device *__init imx_add_imx_uart_1irq(int id,
+		resource_size_t iobase, resource_size_t iosize,
+		resource_size_t irq,
+		const struct imxuart_platform_data *pdata);
+
 #include <mach/mxc_nand.h>
 struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
 		int irq, const struct mxc_nand_platform_data *pdata);
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:43 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:43 +0200
Subject: [PATCH 47/61] ARM: imx: dynamically register imx-i2c devices (imx35)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-48-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/Kconfig             |    1 +
 arch/arm/mach-mx3/devices-imx35.h     |    7 ++++
 arch/arm/mach-mx3/devices.c           |   59 ---------------------------------
 arch/arm/mach-mx3/devices.h           |    5 ---
 arch/arm/mach-mx3/mach-pcm043.c       |    7 +---
 arch/arm/plat-mxc/include/mach/mx35.h |    4 +-
 6 files changed, 12 insertions(+), 71 deletions(-)

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 557a20b..b8a7610 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -103,6 +103,7 @@ config MACH_QONG
 config MACH_PCM043
 	bool "Support Phytec pcm043 (i.MX35) platforms"
 	select ARCH_MX35
+	select IMX_HAVE_PLATFORM_IMX_I2C
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index 69dac76..6d993ae 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -9,5 +9,12 @@
 #include <mach/mx35.h>
 #include <mach/devices-common.h>
 
+#define imx35_add_imx_i2c0(pdata)	\
+	imx_add_imx_i2c(0, MX35_I2C1_BASE_ADDR, SZ_4K, MX35_INT_I2C1, pdata)
+#define imx35_add_imx_i2c1(pdata)	\
+	imx_add_imx_i2c(1, MX35_I2C2_BASE_ADDR, SZ_4K, MX35_INT_I2C2, pdata)
+#define imx35_add_imx_i2c2(pdata)	\
+	imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata)
+
 #define imx35_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 0743214..a285b16 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -167,65 +167,6 @@ struct platform_device mxc_w1_master_device = {
 	.resource = mxc_w1_master_resources,
 };
 
-#if defined(CONFIG_ARCH_MX35)
-static struct resource mxc_i2c0_resources[] = {
-	{
-		.start = I2C_BASE_ADDR,
-		.end = I2C_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MXC_INT_I2C,
-		.end = MXC_INT_I2C,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_i2c_device0 = {
-	.name = "imx-i2c",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxc_i2c0_resources),
-	.resource = mxc_i2c0_resources,
-};
-
-static struct resource mxc_i2c1_resources[] = {
-	{
-		.start = I2C2_BASE_ADDR,
-		.end = I2C2_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MXC_INT_I2C2,
-		.end = MXC_INT_I2C2,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_i2c_device1 = {
-	.name = "imx-i2c",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(mxc_i2c1_resources),
-	.resource = mxc_i2c1_resources,
-};
-
-static struct resource mxc_i2c2_resources[] = {
-	{
-		.start = I2C3_BASE_ADDR,
-		.end = I2C3_BASE_ADDR + SZ_4K - 1,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MXC_INT_I2C3,
-		.end = MXC_INT_I2C3,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_i2c_device2 = {
-	.name = "imx-i2c",
-	.id = 2,
-	.num_resources = ARRAY_SIZE(mxc_i2c2_resources),
-	.resource = mxc_i2c2_resources,
-};
-#endif
-
 #ifdef CONFIG_ARCH_MX31
 static struct resource mxcsdhc0_resources[] = {
 	{
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index e108fa3..c50596a 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -5,11 +5,6 @@ extern struct platform_device mxc_uart_device2;
 extern struct platform_device mxc_uart_device3;
 extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_w1_master_device;
-#if defined(CONFIG_ARCH_MX35)
-extern struct platform_device mxc_i2c_device0;
-extern struct platform_device mxc_i2c_device1;
-extern struct platform_device mxc_i2c_device2;
-#endif
 extern struct platform_device mx3_ipu;
 extern struct platform_device mx3_fb;
 extern struct platform_device mx3_camera;
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 58de305..21305c6 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -37,9 +37,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/imx-uart.h>
-#if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
-#include <mach/i2c.h>
-#endif
 #include <mach/iomux-mx35.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
@@ -123,7 +120,7 @@ static struct imxuart_platform_data uart_pdata = {
 };
 
 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
-static struct imxi2c_platform_data pcm043_i2c_1_data = {
+static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
 	.bitrate = 50000,
 };
 
@@ -368,7 +365,7 @@ static void __init mxc_board_init(void)
 	i2c_register_board_info(0, pcm043_i2c_devices,
 			ARRAY_SIZE(pcm043_i2c_devices));
 
-	mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data);
+	imx35_add_imx_i2c0(&pcm043_i2c0_data);
 #endif
 
 	mxc_register_device(&mx3_ipu, &mx3_ipu_data);
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 526a558..cda60c7 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -18,7 +18,7 @@
 #define MX35_ETB_SLOT4_BASE_ADDR		(MX35_AIPS1_BASE_ADDR + 0x10000)
 #define MX35_ETB_SLOT5_BASE_ADDR		(MX35_AIPS1_BASE_ADDR + 0x14000)
 #define MX35_ECT_CTIO_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x18000)
-#define MX35_I2C_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x80000)
+#define MX35_I2C1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x80000)
 #define MX35_I2C3_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x84000)
 #define MX35_UART1_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x90000)
 #define MX35_UART2_BASE_ADDR			(MX35_AIPS1_BASE_ADDR + 0x94000)
@@ -123,7 +123,7 @@
 #define MX35_INT_MMC_SDHC1	7
 #define MX35_INT_MMC_SDHC2	8
 #define MX35_INT_MMC_SDHC3	9
-#define MX35_INT_I2C		10
+#define MX35_INT_I2C1		10
 #define MX35_INT_SSI1		11
 #define MX35_INT_SSI2		12
 #define MX35_INT_CSPI2		13
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:41 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:41 +0200
Subject: [PATCH 45/61] ARM: imx: dynamically register imx-i2c devices (imx27)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-46-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig             |    5 +++++
 arch/arm/mach-imx/devices-imx27.h     |    5 +++++
 arch/arm/mach-imx/devices.c           |   26 --------------------------
 arch/arm/mach-imx/devices.h           |    4 ----
 arch/arm/mach-imx/mach-cpuimx27.c     |    5 ++---
 arch/arm/mach-imx/mach-mx27ads.c      |    5 ++---
 arch/arm/mach-imx/mach-mxt_td60.c     |    9 ++++-----
 arch/arm/mach-imx/mach-pca100.c       |    5 ++---
 arch/arm/mach-imx/mach-pcm038.c       |    5 ++---
 arch/arm/plat-mxc/include/mach/mx27.h |    4 ++--
 10 files changed, 24 insertions(+), 49 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3f88d4a..2bf8078 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -82,6 +82,7 @@ comment "MX27 platforms:"
 
 config MACH_MX27ADS
 	bool "MX27ADS platform"
+	select IMX_HAVE_PLATFORM_IMX_I2C
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for MX27ADS platform. This includes specific
@@ -89,6 +90,7 @@ config MACH_MX27ADS
 
 config MACH_PCM038
 	bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
+	select IMX_HAVE_PLATFORM_IMX_I2C
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
@@ -111,6 +113,7 @@ endchoice
 
 config MACH_CPUIMX27
 	bool "Eukrea CPUIMX27 module"
+	select IMX_HAVE_PLATFORM_IMX_I2C
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for Eukrea CPUIMX27 platform. This includes
@@ -151,6 +154,7 @@ config MACH_IMX27LITE
 
 config MACH_PCA100
 	bool "Phytec phyCARD-s (pca100)"
+	select IMX_HAVE_PLATFORM_IMX_I2C
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
@@ -159,6 +163,7 @@ config MACH_PCA100
 
 config MACH_MXT_TD60
 	bool "Maxtrack i-MXT TD60"
+	select IMX_HAVE_PLATFORM_IMX_I2C
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for i-MXT (aka td60) platform. This
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index b2f6a12..5e0c40c 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -9,5 +9,10 @@
 #include <mach/mx27.h>
 #include <mach/devices-common.h>
 
+#define imx27_add_i2c_imx0(pdata)	\
+	imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata)
+#define imx27_add_i2c_imx1(pdata)	\
+	imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata)
+
 #define imx27_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index b9f5b69..f8641c2 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -368,32 +368,6 @@ struct platform_device mxc_fec_device = {
 };
 #endif
 
-#ifdef CONFIG_MACH_MX27
-#define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq)				\
-	static struct resource mxc_i2c_resources ## n[] = {		\
-		{							\
-			.start = baseaddr,				\
-			.end = baseaddr + SZ_4K - 1,			\
-			.flags = IORESOURCE_MEM,			\
-		}, {							\
-			.start = irq,					\
-			.end = irq,					\
-			.flags = IORESOURCE_IRQ,			\
-		}							\
-	};								\
-									\
-	struct platform_device mxc_i2c_device ## n = {			\
-		.name = "imx-i2c",					\
-		.id = n,						\
-		.num_resources = ARRAY_SIZE(mxc_i2c_resources ## n),	\
-		.resource = mxc_i2c_resources ## n,			\
-	}
-
-DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
-
-DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
-#endif
-
 static struct resource mxc_pwm_resources[] = {
 	{
 		.start = MX2x_PWM_BASE_ADDR,
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index dcaa4f9..4fe9935 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -28,10 +28,6 @@ extern struct platform_device mxc_w1_master_device;
 extern struct platform_device mxc_fb_device;
 extern struct platform_device mxc_fec_device;
 extern struct platform_device mxc_pwm_device;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device mxc_i2c_device0;
-extern struct platform_device mxc_i2c_device1;
-#endif
 extern struct platform_device mxc_sdhc_device0;
 extern struct platform_device mxc_sdhc_device1;
 extern struct platform_device mxc_otg_udc_device;
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 5d07c2a..06dcd23 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -35,7 +35,6 @@
 #include <mach/board-eukrea_cpuimx27.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
 #include <mach/iomux-mx27.h>
 #include <mach/imx-uart.h>
 #include <mach/mxc_nand.h>
@@ -131,7 +130,7 @@ static struct platform_device *platform_devices[] __initdata = {
 	&mxc_fec_device,
 };
 
-static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = {
+static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
 	.bitrate = 100000,
 };
 
@@ -196,7 +195,7 @@ static void __init eukrea_cpuimx27_init(void)
 	i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
 				ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
 
-	mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data);
+	imx27_add_i2c_imx1(&cpuimx27_i2c1_data);
 
 	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 1a3ebf5..f1ee335 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -31,7 +31,6 @@
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
 #include <mach/mxc_nand.h>
-#include <mach/i2c.h>
 #include <mach/imxfb.h>
 #include <mach/mmc.h>
 
@@ -195,7 +194,7 @@ static struct platform_device mx27ads_nor_mtd_device = {
 	.resource = &mx27ads_flash_resource,
 };
 
-static struct imxi2c_platform_data mx27ads_i2c_data = {
+static const struct imxi2c_platform_data mx27ads_i2c1_data __initconst = {
 	.bitrate = 100000,
 };
 
@@ -322,7 +321,7 @@ static void __init mx27ads_board_init(void)
 	/* only the i2c master 1 is used on this CPU card */
 	i2c_register_board_info(1, mx27ads_i2c_devices,
 				ARRAY_SIZE(mx27ads_i2c_devices));
-	mxc_register_device(&mxc_i2c_device1, &mx27ads_i2c_data);
+	imx27_add_i2c_imx1(&mx27ads_i2c1_data);
 	mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
 	mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
 	mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 447c68f..b80b41e 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -31,7 +31,6 @@
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
 #include <mach/mxc_nand.h>
-#include <mach/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <mach/imxfb.h>
 #include <mach/mmc.h>
@@ -131,7 +130,7 @@ mxt_td60_nand_board_info __initconst = {
 	.hw_ecc = 1,
 };
 
-static struct imxi2c_platform_data mxt_td60_i2c_data = {
+static const struct imxi2c_platform_data mxt_td60_i2c0_data __initconst = {
 	.bitrate = 100000,
 };
 
@@ -171,7 +170,7 @@ static struct i2c_board_info mxt_td60_i2c_devices[] = {
 	},
 };
 
-static struct imxi2c_platform_data mxt_td60_i2c2_data = {
+static const struct imxi2c_platform_data mxt_td60_i2c1_data __initconst = {
 	.bitrate = 100000,
 };
 
@@ -263,8 +262,8 @@ static void __init mxt_td60_board_init(void)
 	i2c_register_board_info(1, mxt_td60_i2c2_devices,
 				ARRAY_SIZE(mxt_td60_i2c2_devices));
 
-	mxc_register_device(&mxc_i2c_device0, &mxt_td60_i2c_data);
-	mxc_register_device(&mxc_i2c_device1, &mxt_td60_i2c2_data);
+	imx27_add_i2c_imx0(&mxt_td60_i2c0_data);
+	imx27_add_i2c_imx1(&mxt_td60_i2c1_data);
 	mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
 	mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
 
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 6efbc6e..6501a7a 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -36,7 +36,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
-#include <mach/i2c.h>
 #include <asm/mach/time.h>
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
 #include <mach/spi.h>
@@ -150,7 +149,7 @@ static struct platform_device *platform_devices[] __initdata = {
 	&mxc_wdt,
 };
 
-static struct imxi2c_platform_data pca100_i2c_1_data = {
+static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
 	.bitrate = 100000,
 };
 
@@ -333,7 +332,7 @@ static void __init pca100_init(void)
 	i2c_register_board_info(1, pca100_i2c_devices,
 				ARRAY_SIZE(pca100_i2c_devices));
 
-	mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
+	imx27_add_i2c_imx1(&pca100_i2c1_data);
 
 	mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
 	mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index bc44d6f..7559e0f 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -35,7 +35,6 @@
 #include <mach/board-pcm038.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
 #include <mach/iomux-mx27.h>
 #include <mach/imx-uart.h>
 #include <mach/mxc_nand.h>
@@ -194,7 +193,7 @@ static void __init pcm038_init_sram(void)
 	mx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
 }
 
-static struct imxi2c_platform_data pcm038_i2c_1_data = {
+static const struct imxi2c_platform_data pcm038_i2c1_data __initconst = {
 	.bitrate = 100000,
 };
 
@@ -318,7 +317,7 @@ static void __init pcm038_init(void)
 	i2c_register_board_info(1, pcm038_i2c_devices,
 				ARRAY_SIZE(pcm038_i2c_devices));
 
-	mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
+	imx27_add_i2c_imx1(&pcm038_i2c1_data);
 
 	/* PE18 for user-LED D40 */
 	mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index bae9cd7..a8ab2e0 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -48,7 +48,7 @@
 #define MX27_CSPI2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0f000)
 #define MX27_SSI1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x10000)
 #define MX27_SSI2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x11000)
-#define MX27_I2C_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x12000)
+#define MX27_I2C1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x12000)
 #define MX27_SDHC1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x13000)
 #define MX27_SDHC2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x14000)
 #define MX27_GPIO_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x15000)
@@ -150,7 +150,7 @@ static inline void mx27_setup_weimcs(size_t cs,
 #define MX27_INT_SDHC3		9
 #define MX27_INT_SDHC2		10
 #define MX27_INT_SDHC1		11
-#define MX27_INT_I2C		12
+#define MX27_INT_I2C1		12
 #define MX27_INT_SSI2		13
 #define MX27_INT_SSI1		14
 #define MX27_INT_CSPI2		15
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:48:56 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:48:56 +0200
Subject: No subject
Message-ID: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>

Hello,

this is the next step in the project "clean up the imx port" targeting
2.6.36.  The highlights this time are:

 - Unification of mach-mx2 and mach-mx1 into mach-imx
 - start allocating devices dynamically
   This should reduce the memory footprint because (in the end) no
   unused struct platform_device, struct resource or struct
   $platformdatafordriverX are kept in memory.  This also cleans up
   with naming conflicts.

This is intermixed with various fixes and simplifications.

I have to admit that some patches could have squashed but squashing them
now would be more work that it's worth so I kept them as they are now.

The patches are based on 67a3e12b05e055c0415c556a315a3d3eb637e29e

  Linux 2.6.35-rc1 (2010-05-30 13:21:02 -0700)

and are available in the git repository at:
  git://git.pengutronix.de/git/ukl/linux-2.6.git imx/for-2.6.36

plus sent as a reply to this mail.  Shortlog and diffstat are to be
found below.

Have fun
Uwe

Uwe Kleine-K?nig (61):
      ARM: mx3: rename mach-mx35pdk.c to mach-mx35_3ds.c matching its arch number
      ARM: mx25: rename mach-mx25pdk.c to mach-mx25_3ds.c matching its arch number
      ARM: mx1: don't use deprecated symbol names
      ARM: mx1/scb9328: fix type of uart1_mxc_exit to make compiler happy
      ARM: mx2/mx27_3ds: document alternative names and remove empty header
      ARM: imx: remove empty and unused board headers
      ARM: mx3/kzm_arm11_01: fold board header in its only user
      ARM: mx2/mx21ads: fold board header in its only user
      ARM: mx2/mx27ads: fold board header in its only user
      ARM: mx3/qong: get rid of nearly empty header
      ARM: mx3/mx31_3ds: fold board header in its only user
      ARM: mx3/mx31ads: fold board header in its only user
      ARM: mxc: grammar fix
      ARM: imx: rename mach dir for mx21 and mx27 to mach-imx
      ARM: imx/mx1: fold crm_regs.h into its only consumer
      ARM: imx: get rid of mxc_gpio_init
      ARM: imx: fold serial.c into devices.c
      ARM: imx1: rename imx_csi_device to match its .name
      ARM: imx1: rename imx_i2c_device to follow a common naming scheme
      ARM: imx1: rename imx_uart[12]_device to follow a common naming scheme
      ARM: mx3: mx31lilly: fix build error for !CONFIG_USB_ULPI
      ARM: imx: rename mxc_uart_devicex to follow a common naming scheme
      ARM: imx: move mx1 support to mach-imx
      ARM: imx: Kconfig: use an if block instead of a depend for many symbols
      ARM: imx: prepare deprecating ARCH_MX1, MACH_MX2, MACH_MX21 and MACH_MX27
      ARM: imx: prepare deprecating ARCH_MX1, MACH_MX2, MACH_MX21 and MACH_MX27
      ARM: imx: new Kconfig symbol and feature test macro for DMA on mx1 and mx2
      ARM: imx: new helper function imx_add_platform_device
      MTD: mxc_nand: make bit fields unsigned to please sparse
      ARM: imx: remove paragraphs with old address of the FSF
      ARM: mx25: remove paragraphs with old address of the FSF
      ARM: mx3: remove paragraphs with old address of the FSF
      ARM: mxc91231: remove paragraphs with old address of the FSF
      ARM: mxc: remove paragraphs with old address of the FSF
      ARM: imx: Change the way nand devices are registered (generic part)
      ARM: imx: Change the way nand devices are registered (imx21)
      ARM: imx: Change the way nand devices are registered (imx25)
      ARM: imx: Change the way nand devices are registered (imx27)
      ARM: imx: Change the way nand devices are registered (imx31)
      ARM: imx: Change the way nand devices are registered (imx35)
      ARM: imx: dynamically register imx-i2c devices (generic part)
      ARM: imx: dynamically register imx-i2c devices (imx1)
      ARM: imx: dynamically register imx-i2c devices (imx21)
      ARM: imx: dynamically register imx-i2c devices (imx25)
      ARM: imx: dynamically register imx-i2c devices (imx27)
      ARM: imx: dynamically register imx-i2c devices (imx31)
      ARM: imx: dynamically register imx-i2c devices (imx35)
      ARM: imx: dynamically register spi_imx devices (generic part)
      ARM: imx: dynamically register spi_imx devices (imx21)
      ARM: imx: dynamically register spi_imx devices (imx25)
      ARM: imx: dynamically register spi_imx devices (imx27)
      ARM: imx: dynamically register spi_imx devices (imx31)
      ARM: imx: dynamically register spi_imx devices (imx35)
      ARM: imx: dynamically register imx-uart devices (generic part)
      ARM: imx: dynamically register imx-uart devices (imx1)
      ARM: imx: dynamically register imx-uart devices (imx21)
      ARM: imx: dynamically register imx-uart devices (imx25)
      ARM: imx: dynamically register imx-uart devices (imx27)
      ARM: imx: dynamically register imx-uart devices (imx31)
      ARM: imx: dynamically register imx-uart devices (imx35)
      ARM: mx3: complement uart init routine with an exit routine

 arch/arm/Makefile                                  |    4 +-
 arch/arm/mach-imx/Kconfig                          |  186 +++++++++++
 arch/arm/{mach-mx2 => mach-imx}/Makefile           |   18 +-
 arch/arm/{mach-mx2 => mach-imx}/Makefile.boot      |    4 +
 .../{mach-mx1/clock.c => mach-imx/clock-imx1.c}    |   50 +++-
 .../clock_imx21.c => mach-imx/clock-imx21.c}       |    0
 .../clock_imx27.c => mach-imx/clock-imx27.c}       |    0
 .../{mach-mx2/cpu_imx27.c => mach-imx/cpu-imx27.c} |    0
 arch/arm/mach-imx/devices-imx1.h                   |   18 +
 arch/arm/mach-imx/devices-imx21.h                  |   30 ++
 arch/arm/mach-imx/devices-imx27.h                  |   38 +++
 arch/arm/{mach-mx2 => mach-imx}/devices.c          |  250 +++++++++------
 arch/arm/{mach-mx2 => mach-imx}/devices.h          |   30 +--
 .../{plat-mxc/dma-mx1-mx2.c => mach-imx/dma-v1.c}  |    4 +-
 .../eukrea_mbimx27-baseboard.c                     |   19 +-
 arch/arm/mach-imx/include/mach/dma-mx1-mx2.h       |   10 +
 .../include/mach/dma-v1.h}                         |   10 +-
 arch/arm/{mach-mx2 => mach-imx}/mach-cpuimx27.c    |   25 +-
 arch/arm/{mach-mx2 => mach-imx}/mach-imx27lite.c   |   11 +-
 arch/arm/{mach-mx1 => mach-imx}/mach-mx1ads.c      |   34 +-
 arch/arm/{mach-mx2 => mach-imx}/mach-mx21ads.c     |   58 +++-
 arch/arm/{mach-mx2 => mach-imx}/mach-mx27_3ds.c    |   17 +-
 arch/arm/{mach-mx2 => mach-imx}/mach-mx27ads.c     |   76 +++--
 arch/arm/{mach-mx2 => mach-imx}/mach-mxt_td60.c    |   36 +--
 arch/arm/{mach-mx2 => mach-imx}/mach-pca100.c      |   23 +-
 arch/arm/{mach-mx2 => mach-imx}/mach-pcm038.c      |   33 +--
 arch/arm/{mach-mx1 => mach-imx}/mach-scb9328.c     |   21 +-
 .../arm/{mach-mx1/generic.c => mach-imx/mm-imx1.c} |   23 +-
 arch/arm/{mach-mx2 => mach-imx}/mm-imx21.c         |    5 +-
 arch/arm/{mach-mx2 => mach-imx}/mm-imx27.c         |    5 +-
 .../ksym_mx1.c => mach-imx/mx1-camera-fiq-ksym.c}  |    0
 .../mx1_camera_fiq.S => mach-imx/mx1-camera-fiq.S} |    0
 arch/arm/{mach-mx2 => mach-imx}/pcm970-baseboard.c |    0
 arch/arm/mach-mx1/Kconfig                          |   19 -
 arch/arm/mach-mx1/Makefile                         |   15 -
 arch/arm/mach-mx1/Makefile.boot                    |    4 -
 arch/arm/mach-mx1/crm_regs.h                       |   55 ---
 arch/arm/mach-mx1/devices.c                        |  242 --------------
 arch/arm/mach-mx1/devices.h                        |    7 -
 arch/arm/mach-mx2/Kconfig                          |  116 -------
 arch/arm/mach-mx2/serial.c                         |  141 --------
 arch/arm/mach-mx25/Kconfig                         |    2 +
 arch/arm/mach-mx25/Makefile                        |    2 +-
 arch/arm/mach-mx25/devices-imx25.h                 |   38 +++
 arch/arm/mach-mx25/devices.c                       |  231 +-------------
 arch/arm/mach-mx25/devices.h                       |   12 -
 .../mach-mx25/{mach-mx25pdk.c => mach-mx25_3ds.c}  |   21 +-
 arch/arm/mach-mx25/mm.c                            |    7 +-
 arch/arm/mach-mx3/Kconfig                          |   26 ++
 arch/arm/mach-mx3/Makefile                         |    2 +-
 arch/arm/mach-mx3/devices-imx31.h                  |   38 +++
 arch/arm/mach-mx3/devices-imx35.h                  |   32 ++
 arch/arm/mach-mx3/devices.c                        |  247 +--------------
 arch/arm/mach-mx3/devices.h                        |   13 -
 arch/arm/mach-mx3/mach-armadillo5x0.c              |   17 +-
 arch/arm/mach-mx3/mach-kzm_arm11_01.c              |   31 ++-
 arch/arm/mach-mx3/mach-mx31_3ds.c                  |   64 +++--
 arch/arm/mach-mx3/mach-mx31ads.c                   |   55 +++-
 arch/arm/mach-mx3/mach-mx31lilly.c                 |   47 ++--
 arch/arm/mach-mx3/mach-mx31lite.c                  |   17 +-
 arch/arm/mach-mx3/mach-mx31moboard.c               |   50 ++--
 .../mach-mx3/{mach-mx35pdk.c => mach-mx35_3ds.c}   |   16 +-
 arch/arm/mach-mx3/mach-pcm037.c                    |   31 +-
 arch/arm/mach-mx3/mach-pcm037_eet.c                |    7 +-
 arch/arm/mach-mx3/mach-pcm043.c                    |   25 +-
 arch/arm/mach-mx3/mach-qong.c                      |   16 +-
 arch/arm/mach-mx3/mm.c                             |    7 +-
 arch/arm/mach-mx3/mx31lilly-db.c                   |   14 +-
 arch/arm/mach-mx3/mx31lite-db.c                    |   15 +-
 arch/arm/mach-mx3/mx31moboard-devboard.c           |   10 +-
 arch/arm/mach-mx3/mx31moboard-marxbot.c            |    4 -
 arch/arm/mach-mx3/mx31moboard-smartbot.c           |   11 +-
 arch/arm/mach-mx5/devices.c                        |    2 +-
 arch/arm/mach-mx5/mm.c                             |    3 +
 arch/arm/mach-mxc91231/crm_regs.h                  |    5 -
 arch/arm/mach-mxc91231/devices.c                   |    2 +-
 arch/arm/mach-mxc91231/mm.c                        |    8 +-
 arch/arm/plat-mxc/Kconfig                          |   10 +-
 arch/arm/plat-mxc/Makefile                         |    4 +-
 arch/arm/plat-mxc/audmux-v1.c                      |    4 -
 arch/arm/plat-mxc/audmux-v2.c                      |    4 -
 arch/arm/plat-mxc/devices.c                        |   33 ++
 arch/arm/plat-mxc/devices/Kconfig                  |   11 +
 arch/arm/plat-mxc/devices/Makefile                 |    4 +
 arch/arm/plat-mxc/devices/platform-imx-i2c.c       |   29 ++
 arch/arm/plat-mxc/devices/platform-imx-uart.c      |   60 ++++
 arch/arm/plat-mxc/devices/platform-mxc_nand.c      |   44 +++
 arch/arm/plat-mxc/devices/platform-spi_imx.c       |   30 ++
 arch/arm/plat-mxc/ehci.c                           |    4 -
 .../arm/plat-mxc/include/mach/board-armadillo5x0.h |   15 -
 .../plat-mxc/include/mach/board-eukrea_cpuimx27.h  |    2 +-
 arch/arm/plat-mxc/include/mach/board-kzmarm11.h    |   39 ---
 arch/arm/plat-mxc/include/mach/board-mx21ads.h     |   52 ---
 arch/arm/plat-mxc/include/mach/board-mx27ads.h     |  344 --------------------
 arch/arm/plat-mxc/include/mach/board-mx27lite.h    |   14 -
 arch/arm/plat-mxc/include/mach/board-mx27pdk.h     |   14 -
 arch/arm/plat-mxc/include/mach/board-mx31_3ds.h    |   59 ----
 arch/arm/plat-mxc/include/mach/board-mx31ads.h     |  117 -------
 arch/arm/plat-mxc/include/mach/board-mx31lilly.h   |    2 +-
 arch/arm/plat-mxc/include/mach/board-mx31lite.h    |    2 +-
 arch/arm/plat-mxc/include/mach/board-mx31moboard.h |    2 +-
 arch/arm/plat-mxc/include/mach/board-mx35pdk.h     |   22 --
 arch/arm/plat-mxc/include/mach/board-pcm037.h      |   22 --
 arch/arm/plat-mxc/include/mach/board-pcm038.h      |    2 +-
 arch/arm/plat-mxc/include/mach/board-pcm043.h      |   22 --
 arch/arm/plat-mxc/include/mach/board-qong.h        |   17 -
 arch/arm/plat-mxc/include/mach/devices-common.h    |   42 +++
 arch/arm/plat-mxc/include/mach/iomux-mxc91231.h    |    4 -
 arch/arm/plat-mxc/include/mach/mx1.h               |   28 +-
 arch/arm/plat-mxc/include/mach/mx25.h              |   28 ++-
 arch/arm/plat-mxc/include/mach/mx27.h              |    4 +-
 arch/arm/plat-mxc/include/mach/mx31.h              |    4 +-
 arch/arm/plat-mxc/include/mach/mx35.h              |    4 +-
 arch/arm/plat-mxc/include/mach/mx3_camera.h        |    4 -
 arch/arm/plat-mxc/include/mach/mxc91231.h          |    4 -
 arch/arm/plat-mxc/include/mach/mxc_nand.h          |    6 +-
 arch/arm/plat-mxc/include/mach/system.h            |    4 -
 arch/arm/plat-mxc/include/mach/timex.h             |    4 -
 arch/arm/plat-mxc/include/mach/uncompress.h        |    4 -
 arch/arm/plat-mxc/include/mach/vmalloc.h           |    4 -
 arch/arm/plat-mxc/irq.c                            |    3 -
 arch/arm/plat-mxc/system.c                         |    4 -
 arch/arm/plat-mxc/tzic.c                           |    2 -
 123 files changed, 1424 insertions(+), 2478 deletions(-)
 create mode 100644 arch/arm/mach-imx/Kconfig
 rename arch/arm/{mach-mx2 => mach-imx}/Makefile (55%)
 rename arch/arm/{mach-mx2 => mach-imx}/Makefile.boot (67%)
 rename arch/arm/{mach-mx1/clock.c => mach-imx/clock-imx1.c} (90%)
 rename arch/arm/{mach-mx2/clock_imx21.c => mach-imx/clock-imx21.c} (100%)
 rename arch/arm/{mach-mx2/clock_imx27.c => mach-imx/clock-imx27.c} (100%)
 rename arch/arm/{mach-mx2/cpu_imx27.c => mach-imx/cpu-imx27.c} (100%)
 create mode 100644 arch/arm/mach-imx/devices-imx1.h
 create mode 100644 arch/arm/mach-imx/devices-imx21.h
 create mode 100644 arch/arm/mach-imx/devices-imx27.h
 rename arch/arm/{mach-mx2 => mach-imx}/devices.c (73%)
 rename arch/arm/{mach-mx2 => mach-imx}/devices.h (54%)
 rename arch/arm/{plat-mxc/dma-mx1-mx2.c => mach-imx/dma-v1.c} (99%)
 rename arch/arm/{mach-mx2 => mach-imx}/eukrea_mbimx27-baseboard.c (93%)
 create mode 100644 arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
 rename arch/arm/{plat-mxc/include/mach/dma-mx1-mx2.h => mach-imx/include/mach/dma-v1.h} (93%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-cpuimx27.c (90%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-imx27lite.c (86%)
 rename arch/arm/{mach-mx1 => mach-imx}/mach-mx1ads.c (81%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-mx21ads.c (77%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-mx27_3ds.c (85%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-mx27ads.c (82%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-mxt_td60.c (86%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-pca100.c (93%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-pcm038.c (91%)
 rename arch/arm/{mach-mx1 => mach-imx}/mach-scb9328.c (89%)
 rename arch/arm/{mach-mx1/generic.c => mach-imx/mm-imx1.c} (68%)
 rename arch/arm/{mach-mx2 => mach-imx}/mm-imx21.c (95%)
 rename arch/arm/{mach-mx2 => mach-imx}/mm-imx27.c (95%)
 rename arch/arm/{mach-mx1/ksym_mx1.c => mach-imx/mx1-camera-fiq-ksym.c} (100%)
 rename arch/arm/{mach-mx1/mx1_camera_fiq.S => mach-imx/mx1-camera-fiq.S} (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/pcm970-baseboard.c (100%)
 delete mode 100644 arch/arm/mach-mx1/Kconfig
 delete mode 100644 arch/arm/mach-mx1/Makefile
 delete mode 100644 arch/arm/mach-mx1/Makefile.boot
 delete mode 100644 arch/arm/mach-mx1/crm_regs.h
 delete mode 100644 arch/arm/mach-mx1/devices.c
 delete mode 100644 arch/arm/mach-mx1/devices.h
 delete mode 100644 arch/arm/mach-mx2/Kconfig
 delete mode 100644 arch/arm/mach-mx2/serial.c
 create mode 100644 arch/arm/mach-mx25/devices-imx25.h
 rename arch/arm/mach-mx25/{mach-mx25pdk.c => mach-mx25_3ds.c} (91%)
 create mode 100644 arch/arm/mach-mx3/devices-imx31.h
 create mode 100644 arch/arm/mach-mx3/devices-imx35.h
 rename arch/arm/mach-mx3/{mach-mx35pdk.c => mach-mx35_3ds.c} (89%)
 create mode 100644 arch/arm/plat-mxc/devices/Kconfig
 create mode 100644 arch/arm/plat-mxc/devices/Makefile
 create mode 100644 arch/arm/plat-mxc/devices/platform-imx-i2c.c
 create mode 100644 arch/arm/plat-mxc/devices/platform-imx-uart.c
 create mode 100644 arch/arm/plat-mxc/devices/platform-mxc_nand.c
 create mode 100644 arch/arm/plat-mxc/devices/platform-spi_imx.c
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-kzmarm11.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx21ads.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx27ads.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx27lite.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx27pdk.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx31ads.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx35pdk.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-pcm037.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-pcm043.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-qong.h
 create mode 100644 arch/arm/plat-mxc/include/mach/devices-common.h


From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:42 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:42 +0200
Subject: [PATCH 46/61] ARM: imx: dynamically register imx-i2c devices (imx31)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-47-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/Kconfig             |    4 ++++
 arch/arm/mach-mx3/devices-imx31.h     |    7 +++++++
 arch/arm/mach-mx3/devices.c           |    2 ++
 arch/arm/mach-mx3/devices.h           |    2 ++
 arch/arm/mach-mx3/mach-armadillo5x0.c |    2 +-
 arch/arm/mach-mx3/mach-mx31ads.c      |    3 ++-
 arch/arm/mach-mx3/mach-mx31moboard.c  |   10 +++++-----
 arch/arm/mach-mx3/mach-pcm037.c       |    9 ++++-----
 arch/arm/plat-mxc/include/mach/mx31.h |    4 ++--
 9 files changed, 29 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 5611b23..557a20b 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -15,6 +15,7 @@ comment "MX3 platforms:"
 config MACH_MX31ADS
 	bool "Support MX31ADS platforms"
 	select ARCH_MX31
+	select IMX_HAVE_PLATFORM_IMX_I2C
 	default y
 	help
 	  Include support for MX31ADS platform. This includes specific
@@ -34,6 +35,7 @@ config MACH_MX31ADS_WM1133_EV1
 config MACH_PCM037
 	bool "Support Phytec pcm037 (i.MX31) platforms"
 	select ARCH_MX31
+	select IMX_HAVE_PLATFORM_IMX_I2C
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
@@ -77,6 +79,7 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT
 config MACH_MX31MOBOARD
 	bool "Support mx31moboard platforms (EPFL Mobots group)"
 	select ARCH_MX31
+	select IMX_HAVE_PLATFORM_IMX_I2C
 	select MXC_ULPI if USB_ULPI
 	help
 	  Include support for mx31moboard platform. This includes specific
@@ -109,6 +112,7 @@ config MACH_PCM043
 config MACH_ARMADILLO5X0
 	bool "Support Atmark Armadillo-500 Development Base Board"
 	select ARCH_MX31
+	select IMX_HAVE_PLATFORM_IMX_I2C
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
index 8bd8b38..56bc1e1 100644
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -9,5 +9,12 @@
 #include <mach/mx31.h>
 #include <mach/devices-common.h>
 
+#define imx31_add_imx_i2c0(pdata)	\
+	imx_add_imx_i2c(0, MX31_I2C1_BASE_ADDR, SZ_4K, MX31_INT_I2C1, pdata)
+#define imx31_add_imx_i2c1(pdata)	\
+	imx_add_imx_i2c(1, MX31_I2C2_BASE_ADDR, SZ_4K, MX31_INT_I2C2, pdata)
+#define imx31_add_imx_i2c2(pdata)	\
+	imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata)
+
 #define imx31_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index c8db849..0743214 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -167,6 +167,7 @@ struct platform_device mxc_w1_master_device = {
 	.resource = mxc_w1_master_resources,
 };
 
+#if defined(CONFIG_ARCH_MX35)
 static struct resource mxc_i2c0_resources[] = {
 	{
 		.start = I2C_BASE_ADDR,
@@ -223,6 +224,7 @@ struct platform_device mxc_i2c_device2 = {
 	.num_resources = ARRAY_SIZE(mxc_i2c2_resources),
 	.resource = mxc_i2c2_resources,
 };
+#endif
 
 #ifdef CONFIG_ARCH_MX31
 static struct resource mxcsdhc0_resources[] = {
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 4a224e6..e108fa3 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -5,9 +5,11 @@ extern struct platform_device mxc_uart_device2;
 extern struct platform_device mxc_uart_device3;
 extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_w1_master_device;
+#if defined(CONFIG_ARCH_MX35)
 extern struct platform_device mxc_i2c_device0;
 extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_i2c_device2;
+#endif
 extern struct platform_device mx3_ipu;
 extern struct platform_device mx3_fb;
 extern struct platform_device mx3_camera;
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 633107a..423ffe7 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -499,7 +499,6 @@ static struct imxuart_platform_data uart_pdata = {
 
 static struct platform_device *devices[] __initdata = {
 	&armadillo5x0_smc911x_device,
-	&mxc_i2c_device1,
 	&armadillo5x0_button_device,
 };
 
@@ -512,6 +511,7 @@ static void __init armadillo5x0_init(void)
 			ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
+	imx31_add_imx_i2c1(NULL);
 
 	/* Register UART */
 	mxc_register_device(&mxc_uart_device0, &uart_pdata);
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index a68b868..b6dc6c8 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -38,6 +38,7 @@
 #include <linux/mfd/wm8350/pmic.h>
 #endif
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /* Base address of PBC controller */
@@ -500,7 +501,7 @@ static void mxc_init_i2c(void)
 	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
 	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
 
-	mxc_register_device(&mxc_i2c_device1, NULL);
+	imx31_add_imx_i2c1(NULL);
 }
 #else
 static void mxc_init_i2c(void)
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 545cfdd..dd51d08 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -41,13 +41,13 @@
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
-#include <mach/i2c.h>
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/mx3_camera.h>
 #include <mach/spi.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int moboard_pins[] = {
@@ -139,11 +139,11 @@ static struct imxuart_platform_data uart4_pdata = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct imxi2c_platform_data moboard_i2c0_pdata = {
+static const struct imxi2c_platform_data moboard_i2c0_data __initconst = {
 	.bitrate = 400000,
 };
 
-static struct imxi2c_platform_data moboard_i2c1_pdata = {
+static const struct imxi2c_platform_data moboard_i2c1_data __initconst = {
 	.bitrate = 100000,
 };
 
@@ -499,8 +499,8 @@ static void __init mxc_board_init(void)
 
 	mxc_register_device(&mxc_uart_device4, &uart4_pdata);
 
-	mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
-	mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
+	imx31_add_imx_i2c0(&moboard_i2c0_data);
+	imx31_add_imx_i2c1(&moboard_i2c1_data);
 
 	mxc_register_device(&mxc_spi_device1, &moboard_spi1_master);
 	mxc_register_device(&mxc_spi_device2, &moboard_spi2_master);
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index d7fef46..7e3fc47 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -41,7 +41,6 @@
 #include <asm/mach/map.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/i2c.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
@@ -280,11 +279,11 @@ pcm037_nand_board_info __initconst = {
 	.hw_ecc = 1,
 };
 
-static struct imxi2c_platform_data pcm037_i2c_1_data = {
+static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
 	.bitrate = 100000,
 };
 
-static struct imxi2c_platform_data pcm037_i2c_2_data = {
+static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
 	.bitrate = 20000,
 };
 
@@ -630,8 +629,8 @@ static void __init mxc_board_init(void)
 	i2c_register_board_info(1, pcm037_i2c_devices,
 			ARRAY_SIZE(pcm037_i2c_devices));
 
-	mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
-	mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data);
+	imx31_add_imx_i2c1(&pcm037_i2c1_data);
+	imx31_add_imx_i2c2(&pcm037_i2c2_data);
 
 	imx31_add_mxc_nand(&pcm037_nand_board_info);
 	mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index fb90e11..afee3ab 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -23,7 +23,7 @@
 #define MX31_ETB_SLOT4_BASE_ADDR		(MX31_AIPS1_BASE_ADDR + 0x10000)
 #define MX31_ETB_SLOT5_BASE_ADDR		(MX31_AIPS1_BASE_ADDR + 0x14000)
 #define MX31_ECT_CTIO_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x18000)
-#define MX31_I2C_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x80000)
+#define MX31_I2C1_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x80000)
 #define MX31_I2C3_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x84000)
 #define MX31_OTG_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x88000)
 #define MX31_ATA_BASE_ADDR			(MX31_AIPS1_BASE_ADDR + 0x8c000)
@@ -145,7 +145,7 @@ static inline void mx31_setup_weimcs(size_t cs,
 #define MX31_INT_FIRI		7
 #define MX31_INT_MMC_SDHC2	8
 #define MX31_INT_MMC_SDHC1	9
-#define MX31_INT_I2C		10
+#define MX31_INT_I2C1		10
 #define MX31_INT_SSI2		11
 #define MX31_INT_SSI1		12
 #define MX31_INT_CSPI2		13
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:48:59 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:48:59 +0200
Subject: [PATCH 03/61] ARM: mx1: don't use deprecated symbol names
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-4-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx1/Makefile       |    1 -
 arch/arm/mach-mx1/clock.c        |    3 +-
 arch/arm/mach-mx1/crm_regs.h     |    4 +-
 arch/arm/mach-mx1/devices.c      |  117 +++++++++++++++++++-------------------
 arch/arm/mach-mx1/generic.c      |   13 ++--
 arch/arm/mach-mx1/mach-mx1ads.c  |   12 ++--
 arch/arm/mach-mx1/mach-scb9328.c |   12 ++--
 7 files changed, 81 insertions(+), 81 deletions(-)

diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile
index fc2ddf8..297d172 100644
--- a/arch/arm/mach-mx1/Makefile
+++ b/arch/arm/mach-mx1/Makefile
@@ -4,7 +4,6 @@
 
 # Object file lists.
 
-EXTRA_CFLAGS += -DIMX_NEEDS_DEPRECATED_SYMBOLS
 obj-y			+= generic.o clock.o devices.o
 
 # Support for CMOS sensor interface
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
index 6cf2d4a..610b88d 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-mx1/clock.c
@@ -596,7 +596,8 @@ int __init mx1_clocks_init(unsigned long fref)
 	clk_enable(&hclk);
 	clk_enable(&fclk);
 
-	mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT);
+	mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
+			MX1_TIM1_INT);
 
 	return 0;
 }
diff --git a/arch/arm/mach-mx1/crm_regs.h b/arch/arm/mach-mx1/crm_regs.h
index 22e866f..13e81e6 100644
--- a/arch/arm/mach-mx1/crm_regs.h
+++ b/arch/arm/mach-mx1/crm_regs.h
@@ -9,8 +9,8 @@
 #ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__
 #define __ARCH_ARM_MACH_MX1_CRM_REGS_H__
 
-#define CCM_BASE	IO_ADDRESS(CCM_BASE_ADDR)
-#define SCM_BASE	IO_ADDRESS(SCM_BASE_ADDR)
+#define CCM_BASE	MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR)
+#define SCM_BASE	MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR)
 
 /* CCM register addresses */
 #define CCM_CSCR	(CCM_BASE + 0x0)
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
index b6be29d..8064f2c 100644
--- a/arch/arm/mach-mx1/devices.c
+++ b/arch/arm/mach-mx1/devices.c
@@ -21,6 +21,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <mach/irqs.h>
@@ -34,20 +35,20 @@ static struct resource imx_csi_resources[] = {
 		.end    = 0x00224010,
 		.flags  = IORESOURCE_MEM,
 	}, {
-		.start  = CSI_INT,
-		.end    = CSI_INT,
+		.start  = MX1_CSI_INT,
+		.end    = MX1_CSI_INT,
 		.flags  = IORESOURCE_IRQ,
 	},
 };
 
-static u64 imx_csi_dmamask = 0xffffffffUL;
+static u64 imx_csi_dmamask = DMA_BIT_MASK(32);
 
 struct platform_device imx_csi_device = {
 	.name           = "mx1-camera",
 	.id             = 0, /* This is used to put cameras on this interface */
 	.dev		= {
 		.dma_mask = &imx_csi_dmamask,
-		.coherent_dma_mask = 0xffffffff,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
 	},
 	.resource       = imx_csi_resources,
 	.num_resources  = ARRAY_SIZE(imx_csi_resources),
@@ -59,8 +60,8 @@ static struct resource imx_i2c_resources[] = {
 		.end    = 0x00217010,
 		.flags  = IORESOURCE_MEM,
 	}, {
-		.start  = I2C_INT,
-		.end    = I2C_INT,
+		.start  = MX1_I2C_INT,
+		.end    = MX1_I2C_INT,
 		.flags  = IORESOURCE_IRQ,
 	},
 };
@@ -74,21 +75,21 @@ struct platform_device imx_i2c_device = {
 
 static struct resource imx_uart1_resources[] = {
 	{
-		.start	= UART1_BASE_ADDR,
-		.end	= UART1_BASE_ADDR + 0xD0,
-		.flags	= IORESOURCE_MEM,
+		.start = MX1_UART1_BASE_ADDR,
+		.end = MX1_UART1_BASE_ADDR + 0xD0,
+		.flags = IORESOURCE_MEM,
 	}, {
-		.start	= UART1_MINT_RX,
-		.end	= UART1_MINT_RX,
-		.flags	= IORESOURCE_IRQ,
+		.start = MX1_UART1_MINT_RX,
+		.end = MX1_UART1_MINT_RX,
+		.flags = IORESOURCE_IRQ,
 	}, {
-		.start	= UART1_MINT_TX,
-		.end	= UART1_MINT_TX,
-		.flags	= IORESOURCE_IRQ,
+		.start = MX1_UART1_MINT_TX,
+		.end = MX1_UART1_MINT_TX,
+		.flags = IORESOURCE_IRQ,
 	}, {
-		.start	= UART1_MINT_RTS,
-		.end	= UART1_MINT_RTS,
-		.flags	= IORESOURCE_IRQ,
+		.start = MX1_UART1_MINT_RTS,
+		.end = MX1_UART1_MINT_RTS,
+		.flags = IORESOURCE_IRQ,
 	},
 };
 
@@ -101,21 +102,21 @@ struct platform_device imx_uart1_device = {
 
 static struct resource imx_uart2_resources[] = {
 	{
-		.start	= UART2_BASE_ADDR,
-		.end	= UART2_BASE_ADDR + 0xD0,
-		.flags	= IORESOURCE_MEM,
+		.start = MX1_UART2_BASE_ADDR,
+		.end = MX1_UART2_BASE_ADDR + 0xD0,
+		.flags = IORESOURCE_MEM,
 	}, {
-		.start	= UART2_MINT_RX,
-		.end	= UART2_MINT_RX,
-		.flags	= IORESOURCE_IRQ,
+		.start = MX1_UART2_MINT_RX,
+		.end = MX1_UART2_MINT_RX,
+		.flags = IORESOURCE_IRQ,
 	}, {
-		.start	= UART2_MINT_TX,
-		.end	= UART2_MINT_TX,
-		.flags	= IORESOURCE_IRQ,
+		.start = MX1_UART2_MINT_TX,
+		.end = MX1_UART2_MINT_TX,
+		.flags = IORESOURCE_IRQ,
 	}, {
-		.start	= UART2_MINT_RTS,
-		.end	= UART2_MINT_RTS,
-		.flags	= IORESOURCE_IRQ,
+		.start = MX1_UART2_MINT_RTS,
+		.end = MX1_UART2_MINT_RTS,
+		.flags = IORESOURCE_IRQ,
 	},
 };
 
@@ -132,12 +133,12 @@ static struct resource imx_rtc_resources[] = {
 		.end    = 0x00204024,
 		.flags  = IORESOURCE_MEM,
 	}, {
-		.start  = RTC_INT,
-		.end    = RTC_INT,
+		.start  = MX1_RTC_INT,
+		.end    = MX1_RTC_INT,
 		.flags  = IORESOURCE_IRQ,
 	}, {
-		.start  = RTC_SAMINT,
-		.end    = RTC_SAMINT,
+		.start  = MX1_RTC_SAMINT,
+		.end    = MX1_RTC_SAMINT,
 		.flags  = IORESOURCE_IRQ,
 	},
 };
@@ -155,8 +156,8 @@ static struct resource imx_wdt_resources[] = {
 		.end    = 0x00201008,
 		.flags  = IORESOURCE_MEM,
 	}, {
-		.start  = WDT_INT,
-		.end    = WDT_INT,
+		.start  = MX1_WDT_INT,
+		.end    = MX1_WDT_INT,
 		.flags  = IORESOURCE_IRQ,
 	},
 };
@@ -174,32 +175,32 @@ static struct resource imx_usb_resources[] = {
 		.end	= 0x00212148,
 		.flags	= IORESOURCE_MEM,
 	}, {
-		.start	= USBD_INT0,
-		.end	= USBD_INT0,
+		.start	= MX1_USBD_INT0,
+		.end	= MX1_USBD_INT0,
 		.flags	= IORESOURCE_IRQ,
 	}, {
-		.start	= USBD_INT1,
-		.end	= USBD_INT1,
+		.start	= MX1_USBD_INT1,
+		.end	= MX1_USBD_INT1,
 		.flags	= IORESOURCE_IRQ,
 	}, {
-		.start	= USBD_INT2,
-		.end	= USBD_INT2,
+		.start	= MX1_USBD_INT2,
+		.end	= MX1_USBD_INT2,
 		.flags	= IORESOURCE_IRQ,
 	}, {
-		.start	= USBD_INT3,
-		.end	= USBD_INT3,
+		.start	= MX1_USBD_INT3,
+		.end	= MX1_USBD_INT3,
 		.flags	= IORESOURCE_IRQ,
 	}, {
-		.start	= USBD_INT4,
-		.end	= USBD_INT4,
+		.start	= MX1_USBD_INT4,
+		.end	= MX1_USBD_INT4,
 		.flags	= IORESOURCE_IRQ,
 	}, {
-		.start	= USBD_INT5,
-		.end	= USBD_INT5,
+		.start	= MX1_USBD_INT5,
+		.end	= MX1_USBD_INT5,
 		.flags	= IORESOURCE_IRQ,
 	}, {
-		.start	= USBD_INT6,
-		.end	= USBD_INT6,
+		.start	= MX1_USBD_INT6,
+		.end	= MX1_USBD_INT6,
 		.flags	= IORESOURCE_IRQ,
 	},
 };
@@ -215,23 +216,23 @@ struct platform_device imx_usb_device = {
 static struct mxc_gpio_port imx_gpio_ports[] = {
 	{
 		.chip.label = "gpio-0",
-		.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
-		.irq = GPIO_INT_PORTA,
+		.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
+		.irq = MX1_GPIO_INT_PORTA,
 		.virtual_irq_start = MXC_GPIO_IRQ_START,
 	}, {
 		.chip.label = "gpio-1",
-		.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
-		.irq = GPIO_INT_PORTB,
+		.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
+		.irq = MX1_GPIO_INT_PORTB,
 		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
 	}, {
 		.chip.label = "gpio-2",
-		.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
-		.irq = GPIO_INT_PORTC,
+		.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
+		.irq = MX1_GPIO_INT_PORTC,
 		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
 	}, {
 		.chip.label = "gpio-3",
-		.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
-		.irq = GPIO_INT_PORTD,
+		.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
+		.irq = MX1_GPIO_INT_PORTD,
 		.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
 	}
 };
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-mx1/generic.c
index 7f9fc10..5a745d9 100644
--- a/arch/arm/mach-mx1/generic.c
+++ b/arch/arm/mach-mx1/generic.c
@@ -31,23 +31,22 @@
 
 static struct map_desc imx_io_desc[] __initdata = {
 	{
-		.virtual	= IMX_IO_BASE,
-		.pfn		= __phys_to_pfn(IMX_IO_PHYS),
-		.length		= IMX_IO_SIZE,
-		.type		= MT_DEVICE
+		.virtual = MX1_IO_BASE_ADDR_VIRT,
+		.pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
+		.length = MX1_IO_SIZE,
+		.type = MT_DEVICE
 	}
 };
 
 void __init mx1_map_io(void)
 {
 	mxc_set_cpu_type(MXC_CPU_MX1);
-	mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR));
+	mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
 
 	iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
 }
 
 void __init mx1_init_irq(void)
 {
-	mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+	mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
 }
-
diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c
index 51f3cfd..27c8222 100644
--- a/arch/arm/mach-mx1/mach-mx1ads.c
+++ b/arch/arm/mach-mx1/mach-mx1ads.c
@@ -75,8 +75,8 @@ static struct physmap_flash_data mx1ads_flash_data = {
 };
 
 static struct resource flash_resource = {
-	.start	= IMX_CS0_PHYS,
-	.end	= IMX_CS0_PHYS + SZ_32M - 1,
+	.start	= MX1_CS0_PHYS,
+	.end	= MX1_CS0_PHYS + SZ_32M - 1,
 	.flags	= IORESOURCE_MEM,
 };
 
@@ -145,8 +145,8 @@ struct sys_timer mx1ads_timer = {
 
 MACHINE_START(MX1ADS, "Freescale MX1ADS")
 	/* Maintainer: Sascha Hauer, Pengutronix */
-	.phys_io	= IMX_IO_PHYS,
-	.io_pg_offst	= (IMX_IO_BASE >> 18) & 0xfffc,
+	.phys_io	= MX1_IO_BASE_ADDR,
+	.io_pg_offst	= (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
 	.boot_params	= MX1_PHYS_OFFSET + 0x100,
 	.map_io		= mx1_map_io,
 	.init_irq	= mx1_init_irq,
@@ -155,8 +155,8 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
 MACHINE_END
 
 MACHINE_START(MXLADS, "Freescale MXLADS")
-	.phys_io	= IMX_IO_PHYS,
-	.io_pg_offst	= (IMX_IO_BASE >> 18) & 0xfffc,
+	.phys_io	= MX1_IO_BASE_ADDR,
+	.io_pg_offst	= (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
 	.boot_params	= MX1_PHYS_OFFSET + 0x100,
 	.map_io		= mx1_map_io,
 	.init_irq	= mx1_init_irq,
diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-mx1/mach-scb9328.c
index 7587a7a..7c6bbe8 100644
--- a/arch/arm/mach-mx1/mach-scb9328.c
+++ b/arch/arm/mach-mx1/mach-scb9328.c
@@ -31,8 +31,8 @@
  * This scb9328 has a 32MiB flash
  */
 static struct resource flash_resource = {
-	.start	= IMX_CS0_PHYS,
-	.end	= IMX_CS0_PHYS + (32 * 1024 * 1024) - 1,
+	.start	= MX1_CS0_PHYS,
+	.end	= MX1_CS0_PHYS + (32 * 1024 * 1024) - 1,
 	.flags	= IORESOURCE_MEM,
 };
 
@@ -70,13 +70,13 @@ static struct dm9000_plat_data dm9000_platdata = {
 static struct resource dm9000x_resources[] = {
 	{
 		.name	= "address area",
-		.start	= IMX_CS5_PHYS,
-		.end	= IMX_CS5_PHYS + 1,
+		.start	= MX1_CS5_PHYS,
+		.end	= MX1_CS5_PHYS + 1,
 		.flags	= IORESOURCE_MEM,	/* address access */
 	}, {
 		.name	= "data area",
-		.start	= IMX_CS5_PHYS + 4,
-		.end	= IMX_CS5_PHYS + 5,
+		.start	= MX1_CS5_PHYS + 4,
+		.end	= MX1_CS5_PHYS + 5,
 		.flags	= IORESOURCE_MEM,	/* data access */
 	}, {
 		.start	= IRQ_GPIOC(3),
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:31 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:31 +0200
Subject: [PATCH 35/61] ARM: imx: Change the way nand devices are registered
	(generic part)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-36-git-send-email-u.kleine-koenig@pengutronix.de>

Instead of having a platform device defined in a devices.c and register
it in the machine file allocate it dynamically.  This reduces the size
of needed memory as the new function is discarded after init and only
the existing devices are created.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/plat-mxc/Kconfig                       |    2 +
 arch/arm/plat-mxc/Makefile                      |    2 +
 arch/arm/plat-mxc/devices/Kconfig               |    2 +
 arch/arm/plat-mxc/devices/Makefile              |    1 +
 arch/arm/plat-mxc/devices/platform-mxc_nand.c   |   44 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/devices-common.h |    6 +++
 6 files changed, 57 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-mxc/devices/Kconfig
 create mode 100644 arch/arm/plat-mxc/devices/Makefile
 create mode 100644 arch/arm/plat-mxc/devices/platform-mxc_nand.c

diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index d80de4e..cf053d7 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -1,5 +1,7 @@
 if ARCH_MXC
 
+source "arch/arm/plat-mxc/devices/Kconfig"
+
 menu "Freescale MXC Implementations"
 
 choice
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index f134d14..c7506a8 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -19,3 +19,5 @@ ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
 endif
+
+obj-y += devices/
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
new file mode 100644
index 0000000..09e91dd
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -0,0 +1,2 @@
+config IMX_HAVE_PLATFORM_MXC_NAND
+	bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
new file mode 100644
index 0000000..e314533
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
new file mode 100644
index 0000000..1c28641
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <asm/sizes.h>
+#include <mach/devices-common.h>
+
+static struct platform_device *__init imx_add_mxc_nand(resource_size_t iobase,
+		int irq, const struct mxc_nand_platform_data *pdata,
+		resource_size_t iosize)
+{
+	static int id = 0;
+	
+	struct resource res[] = {
+		{
+			.start = iobase,
+			.end = iobase + iosize - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = irq,
+			.end = irq,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+
+	return imx_add_platform_device("mxc_nand", id++, res, ARRAY_SIZE(res),
+			pdata, sizeof(*pdata));
+}
+
+struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
+		int irq, const struct mxc_nand_platform_data *pdata)
+{
+	return imx_add_mxc_nand(iobase, irq, pdata, SZ_4K);
+}
+
+struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
+		int irq, const struct mxc_nand_platform_data *pdata)
+{
+	return imx_add_mxc_nand(iobase, irq, pdata, SZ_8K);
+}
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 849d8ff..d5f121a 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -13,3 +13,9 @@
 struct platform_device *imx_add_platform_device(const char *name, int id,
 		const struct resource *res, unsigned int num_resources,
 		const void *data, size_t size_data);
+
+#include <mach/mxc_nand.h>
+struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
+		int irq, const struct mxc_nand_platform_data *pdata);
+struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
+		int irq, const struct mxc_nand_platform_data *pdata);
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:06 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:06 +0200
Subject: [PATCH 10/61] ARM: mx3/qong: get rid of nearly empty header
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-11-git-send-email-u.kleine-koenig@pengutronix.de>

board-qong.h only defined a single symbol that was used only once.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/mach-qong.c               |    3 +--
 arch/arm/plat-mxc/include/mach/board-qong.h |   17 -----------------
 2 files changed, 1 insertions(+), 19 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-qong.h

diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index e5b5b83..62281ad 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -34,7 +34,6 @@
 #include <mach/common.h>
 #include <asm/page.h>
 #include <asm/setup.h>
-#include <mach/board-qong.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include "devices.h"
@@ -116,7 +115,7 @@ static struct physmap_flash_data qong_flash_data = {
 
 static struct resource qong_flash_resource = {
 	.start = MX31_CS0_BASE_ADDR,
-	.end = MX31_CS0_BASE_ADDR + QONG_NOR_SIZE - 1,
+	.end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
 	.flags = IORESOURCE_MEM,
 };
 
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
deleted file mode 100644
index 6d88c7a..0000000
--- a/arch/arm/plat-mxc/include/mach/board-qong.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok at emcraft.com>
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
-#define __ASM_ARCH_MXC_BOARD_QONG_H__
-
-/* NOR FLASH */
-#define QONG_NOR_SIZE		(128*1024*1024)
-
-#endif /* __ASM_ARCH_MXC_BOARD_QONG_H__ */
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:48:58 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:48:58 +0200
Subject: [PATCH 02/61] ARM: mx25: rename mach-mx25pdk.c to mach-mx25_3ds.c
	matching its arch number
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-3-git-send-email-u.kleine-koenig@pengutronix.de>

Additionally document all known names of that machine.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx25/Makefile        |    2 +-
 arch/arm/mach-mx25/mach-mx25_3ds.c |  180 ++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mx25/mach-mx25pdk.c  |  174 ----------------------------------
 3 files changed, 181 insertions(+), 175 deletions(-)
 create mode 100644 arch/arm/mach-mx25/mach-mx25_3ds.c
 delete mode 100644 arch/arm/mach-mx25/mach-mx25pdk.c

diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
index 10cebc5..6db9603 100644
--- a/arch/arm/mach-mx25/Makefile
+++ b/arch/arm/mach-mx25/Makefile
@@ -1,3 +1,3 @@
 obj-y				:= mm.o devices.o
 obj-$(CONFIG_ARCH_MX25)		+= clock.o
-obj-$(CONFIG_MACH_MX25_3DS)	+= mach-mx25pdk.o
+obj-$(CONFIG_MACH_MX25_3DS)	+= mach-mx25_3ds.o
diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-mx25/mach-mx25_3ds.c
new file mode 100644
index 0000000..26ba246
--- /dev/null
+++ b/arch/arm/mach-mx25/mach-mx25_3ds.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright 2009 Sascha Hauer, <kernel at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+
+/*
+ * This machine is known as:
+ *  - i.MX25 3-Stack Development System
+ *  - i.MX25 Platform Development Kit (i.MX25 PDK)
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/fec.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/mx25.h>
+#include <mach/mxc_nand.h>
+#include <mach/imxfb.h>
+#include "devices.h"
+#include <mach/iomux-mx25.h>
+
+static struct imxuart_platform_data uart_pdata = {
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct pad_desc mx25pdk_pads[] = {
+	MX25_PAD_FEC_MDC__FEC_MDC,
+	MX25_PAD_FEC_MDIO__FEC_MDIO,
+	MX25_PAD_FEC_TDATA0__FEC_TDATA0,
+	MX25_PAD_FEC_TDATA1__FEC_TDATA1,
+	MX25_PAD_FEC_TX_EN__FEC_TX_EN,
+	MX25_PAD_FEC_RDATA0__FEC_RDATA0,
+	MX25_PAD_FEC_RDATA1__FEC_RDATA1,
+	MX25_PAD_FEC_RX_DV__FEC_RX_DV,
+	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
+	MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */
+	MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */
+
+	/* LCD */
+	MX25_PAD_LD0__LD0,
+	MX25_PAD_LD1__LD1,
+	MX25_PAD_LD2__LD2,
+	MX25_PAD_LD3__LD3,
+	MX25_PAD_LD4__LD4,
+	MX25_PAD_LD5__LD5,
+	MX25_PAD_LD6__LD6,
+	MX25_PAD_LD7__LD7,
+	MX25_PAD_LD8__LD8,
+	MX25_PAD_LD9__LD9,
+	MX25_PAD_LD10__LD10,
+	MX25_PAD_LD11__LD11,
+	MX25_PAD_LD12__LD12,
+	MX25_PAD_LD13__LD13,
+	MX25_PAD_LD14__LD14,
+	MX25_PAD_LD15__LD15,
+	MX25_PAD_GPIO_E__LD16,
+	MX25_PAD_GPIO_F__LD17,
+	MX25_PAD_HSYNC__HSYNC,
+	MX25_PAD_VSYNC__VSYNC,
+	MX25_PAD_LSCLK__LSCLK,
+	MX25_PAD_OE_ACD__OE_ACD,
+	MX25_PAD_CONTRAST__CONTRAST,
+};
+
+static struct fec_platform_data mx25_fec_pdata = {
+        .phy    = PHY_INTERFACE_MODE_RMII,
+};
+
+#define FEC_ENABLE_GPIO		35
+#define FEC_RESET_B_GPIO	104
+
+static void __init mx25pdk_fec_reset(void)
+{
+	gpio_request(FEC_ENABLE_GPIO, "FEC PHY enable");
+	gpio_request(FEC_RESET_B_GPIO, "FEC PHY reset");
+
+	gpio_direction_output(FEC_ENABLE_GPIO, 0);  /* drop PHY power */
+	gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
+	udelay(2);
+
+	/* turn on PHY power and lift reset */
+	gpio_set_value(FEC_ENABLE_GPIO, 1);
+	gpio_set_value(FEC_RESET_B_GPIO, 1);
+}
+
+static struct mxc_nand_platform_data mx25pdk_nand_board_info = {
+	.width		= 1,
+	.hw_ecc		= 1,
+	.flash_bbt	= 1,
+};
+
+static struct imx_fb_videomode mx25pdk_modes[] = {
+	{
+		.mode	= {
+			.name		= "CRT-VGA",
+			.refresh	= 60,
+			.xres		= 640,
+			.yres		= 480,
+			.pixclock	= 39683,
+			.left_margin	= 45,
+			.right_margin	= 114,
+			.upper_margin	= 33,
+			.lower_margin	= 11,
+			.hsync_len	= 1,
+			.vsync_len	= 1,
+		},
+		.bpp	= 16,
+		.pcr	= 0xFA208B80,
+	},
+};
+
+static struct imx_fb_platform_data mx25pdk_fb_pdata = {
+	.mode		= mx25pdk_modes,
+	.num_modes	= ARRAY_SIZE(mx25pdk_modes),
+	.pwmr		= 0x00A903FF,
+	.lscr1		= 0x00120300,
+	.dmacr		= 0x00020010,
+};
+
+static void __init mx25pdk_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
+			ARRAY_SIZE(mx25pdk_pads));
+
+	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	mxc_register_device(&mxc_usbh2, NULL);
+	mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info);
+	mxc_register_device(&mx25_rtc_device, NULL);
+	mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
+
+	mx25pdk_fec_reset();
+	mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
+}
+
+static void __init mx25pdk_timer_init(void)
+{
+	mx25_clocks_init();
+}
+
+static struct sys_timer mx25pdk_timer = {
+	.init   = mx25pdk_timer_init,
+};
+
+MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
+	/* Maintainer: Freescale Semiconductor, Inc. */
+	.phys_io	= MX25_AIPS1_BASE_ADDR,
+	.io_pg_offst	= ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+	.boot_params    = MX25_PHYS_OFFSET + 0x100,
+	.map_io         = mx25_map_io,
+	.init_irq       = mx25_init_irq,
+	.init_machine   = mx25pdk_init,
+	.timer          = &mx25pdk_timer,
+MACHINE_END
+
diff --git a/arch/arm/mach-mx25/mach-mx25pdk.c b/arch/arm/mach-mx25/mach-mx25pdk.c
deleted file mode 100644
index 83d7410..0000000
--- a/arch/arm/mach-mx25/mach-mx25pdk.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * Copyright 2009 Sascha Hauer, <kernel at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/fec.h>
-#include <linux/platform_device.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/memory.h>
-#include <asm/mach/map.h>
-#include <mach/common.h>
-#include <mach/imx-uart.h>
-#include <mach/mx25.h>
-#include <mach/mxc_nand.h>
-#include <mach/imxfb.h>
-#include "devices.h"
-#include <mach/iomux-mx25.h>
-
-static struct imxuart_platform_data uart_pdata = {
-	.flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct pad_desc mx25pdk_pads[] = {
-	MX25_PAD_FEC_MDC__FEC_MDC,
-	MX25_PAD_FEC_MDIO__FEC_MDIO,
-	MX25_PAD_FEC_TDATA0__FEC_TDATA0,
-	MX25_PAD_FEC_TDATA1__FEC_TDATA1,
-	MX25_PAD_FEC_TX_EN__FEC_TX_EN,
-	MX25_PAD_FEC_RDATA0__FEC_RDATA0,
-	MX25_PAD_FEC_RDATA1__FEC_RDATA1,
-	MX25_PAD_FEC_RX_DV__FEC_RX_DV,
-	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
-	MX25_PAD_A17__GPIO_2_3, /* FEC_EN, GPIO 35 */
-	MX25_PAD_D12__GPIO_4_8, /* FEC_RESET_B, GPIO 104 */
-
-	/* LCD */
-	MX25_PAD_LD0__LD0,
-	MX25_PAD_LD1__LD1,
-	MX25_PAD_LD2__LD2,
-	MX25_PAD_LD3__LD3,
-	MX25_PAD_LD4__LD4,
-	MX25_PAD_LD5__LD5,
-	MX25_PAD_LD6__LD6,
-	MX25_PAD_LD7__LD7,
-	MX25_PAD_LD8__LD8,
-	MX25_PAD_LD9__LD9,
-	MX25_PAD_LD10__LD10,
-	MX25_PAD_LD11__LD11,
-	MX25_PAD_LD12__LD12,
-	MX25_PAD_LD13__LD13,
-	MX25_PAD_LD14__LD14,
-	MX25_PAD_LD15__LD15,
-	MX25_PAD_GPIO_E__LD16,
-	MX25_PAD_GPIO_F__LD17,
-	MX25_PAD_HSYNC__HSYNC,
-	MX25_PAD_VSYNC__VSYNC,
-	MX25_PAD_LSCLK__LSCLK,
-	MX25_PAD_OE_ACD__OE_ACD,
-	MX25_PAD_CONTRAST__CONTRAST,
-};
-
-static struct fec_platform_data mx25_fec_pdata = {
-        .phy    = PHY_INTERFACE_MODE_RMII,
-};
-
-#define FEC_ENABLE_GPIO		35
-#define FEC_RESET_B_GPIO	104
-
-static void __init mx25pdk_fec_reset(void)
-{
-	gpio_request(FEC_ENABLE_GPIO, "FEC PHY enable");
-	gpio_request(FEC_RESET_B_GPIO, "FEC PHY reset");
-
-	gpio_direction_output(FEC_ENABLE_GPIO, 0);  /* drop PHY power */
-	gpio_direction_output(FEC_RESET_B_GPIO, 0); /* assert reset */
-	udelay(2);
-
-	/* turn on PHY power and lift reset */
-	gpio_set_value(FEC_ENABLE_GPIO, 1);
-	gpio_set_value(FEC_RESET_B_GPIO, 1);
-}
-
-static struct mxc_nand_platform_data mx25pdk_nand_board_info = {
-	.width		= 1,
-	.hw_ecc		= 1,
-	.flash_bbt	= 1,
-};
-
-static struct imx_fb_videomode mx25pdk_modes[] = {
-	{
-		.mode	= {
-			.name		= "CRT-VGA",
-			.refresh	= 60,
-			.xres		= 640,
-			.yres		= 480,
-			.pixclock	= 39683,
-			.left_margin	= 45,
-			.right_margin	= 114,
-			.upper_margin	= 33,
-			.lower_margin	= 11,
-			.hsync_len	= 1,
-			.vsync_len	= 1,
-		},
-		.bpp	= 16,
-		.pcr	= 0xFA208B80,
-	},
-};
-
-static struct imx_fb_platform_data mx25pdk_fb_pdata = {
-	.mode		= mx25pdk_modes,
-	.num_modes	= ARRAY_SIZE(mx25pdk_modes),
-	.pwmr		= 0x00A903FF,
-	.lscr1		= 0x00120300,
-	.dmacr		= 0x00020010,
-};
-
-static void __init mx25pdk_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
-			ARRAY_SIZE(mx25pdk_pads));
-
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
-	mxc_register_device(&mxc_usbh2, NULL);
-	mxc_register_device(&mxc_nand_device, &mx25pdk_nand_board_info);
-	mxc_register_device(&mx25_rtc_device, NULL);
-	mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata);
-
-	mx25pdk_fec_reset();
-	mxc_register_device(&mx25_fec_device, &mx25_fec_pdata);
-}
-
-static void __init mx25pdk_timer_init(void)
-{
-	mx25_clocks_init();
-}
-
-static struct sys_timer mx25pdk_timer = {
-	.init   = mx25pdk_timer_init,
-};
-
-MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
-	/* Maintainer: Freescale Semiconductor, Inc. */
-	.phys_io	= MX25_AIPS1_BASE_ADDR,
-	.io_pg_offst	= ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
-	.boot_params    = MX25_PHYS_OFFSET + 0x100,
-	.map_io         = mx25_map_io,
-	.init_irq       = mx25_init_irq,
-	.init_machine   = mx25pdk_init,
-	.timer          = &mx25pdk_timer,
-MACHINE_END
-
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:08 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:08 +0200
Subject: [PATCH 12/61] ARM: mx3/mx31ads: fold board header in its only user
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-13-git-send-email-u.kleine-koenig@pengutronix.de>

Moreover remove unused definitions.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/mach-mx31ads.c               |   43 +++++++--
 arch/arm/plat-mxc/include/mach/board-mx31ads.h |  117 ------------------------
 2 files changed, 36 insertions(+), 124 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx31ads.h

diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index b3d1a18..ed34b61 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -33,7 +33,6 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/board-mx31ads.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 
@@ -45,12 +44,42 @@
 
 #include "devices.h"
 
-/*!
- * @file mx31ads.c
- *
- * @brief This file contains the board-specific initialization routines.
- *
- * @ingroup System
+/* Base address of PBC controller */
+#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
+/* Offsets for the PBC Controller register */
+
+/* PBC Board interrupt status register */
+#define PBC_INTSTATUS           0x000016
+
+/* PBC Board interrupt current status register */
+#define PBC_INTCURR_STATUS      0x000018
+
+/* PBC Interrupt mask register set address */
+#define PBC_INTMASK_SET         0x00001A
+
+/* PBC Interrupt mask register clear address */
+#define PBC_INTMASK_CLEAR       0x00001C
+
+/* External UART A */
+#define PBC_SC16C652_UARTA      0x010000
+
+/* External UART B */
+#define PBC_SC16C652_UARTB      0x010010
+
+#define PBC_INTSTATUS_REG	(PBC_INTSTATUS + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_SET_REG	(PBC_INTMASK_SET + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_CLEAR_REG	(PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
+#define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
+
+#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)
+
+#define EXPIO_INT_XUART_INTA	(MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_XUART_INTB	(MXC_EXP_IO_BASE + 11)
+
+#define MXC_MAX_EXP_IO_LINES	16
+/*
+ * This file contains the board-specific initialization routines.
  */
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
deleted file mode 100644
index 095a199..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
-
-#include <mach/hardware.h>
-
-/* Base address of PBC controller */
-#define PBC_BASE_ADDRESS        MX31_CS4_BASE_ADDR_VIRT
-/* Offsets for the PBC Controller register */
-
-/* PBC Board status register offset */
-#define PBC_BSTAT               0x000002
-
-/* PBC Board control register 1 set address */
-#define PBC_BCTRL1_SET          0x000004
-
-/* PBC Board control register 1 clear address */
-#define PBC_BCTRL1_CLEAR        0x000006
-
-/* PBC Board control register 2 set address */
-#define PBC_BCTRL2_SET          0x000008
-
-/* PBC Board control register 2 clear address */
-#define PBC_BCTRL2_CLEAR        0x00000A
-
-/* PBC Board control register 3 set address */
-#define PBC_BCTRL3_SET          0x00000C
-
-/* PBC Board control register 3 clear address */
-#define PBC_BCTRL3_CLEAR        0x00000E
-
-/* PBC Board control register 4 set address */
-#define PBC_BCTRL4_SET          0x000010
-
-/* PBC Board control register 4 clear address */
-#define PBC_BCTRL4_CLEAR        0x000012
-
-/* PBC Board status register 1 */
-#define PBC_BSTAT1              0x000014
-
-/* PBC Board interrupt status register */
-#define PBC_INTSTATUS           0x000016
-
-/* PBC Board interrupt current status register */
-#define PBC_INTCURR_STATUS      0x000018
-
-/* PBC Interrupt mask register set address */
-#define PBC_INTMASK_SET         0x00001A
-
-/* PBC Interrupt mask register clear address */
-#define PBC_INTMASK_CLEAR       0x00001C
-
-/* External UART A */
-#define PBC_SC16C652_UARTA      0x010000
-
-/* External UART B */
-#define PBC_SC16C652_UARTB      0x010010
-
-/* Ethernet Controller IO base address */
-#define PBC_CS8900A_IOBASE      0x020000
-
-/* Ethernet Controller Memory base address */
-#define PBC_CS8900A_MEMBASE     0x021000
-
-/* Ethernet Controller DMA base address */
-#define PBC_CS8900A_DMABASE     0x022000
-
-/* External chip select 0 */
-#define PBC_XCS0                0x040000
-
-/* LCD Display enable */
-#define PBC_LCD_EN_B            0x060000
-
-/* Code test debug enable */
-#define PBC_CODE_B              0x070000
-
-/* PSRAM memory select */
-#define PBC_PSRAM_B             0x5000000
-
-#define PBC_INTSTATUS_REG	(PBC_INTSTATUS + PBC_BASE_ADDRESS)
-#define PBC_INTCURR_STATUS_REG	(PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
-#define PBC_INTMASK_SET_REG	(PBC_INTMASK_SET + PBC_BASE_ADDRESS)
-#define PBC_INTMASK_CLEAR_REG	(PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
-#define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
-
-#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_LOW_BAT	(MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_PB_IRQ	(MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_OTG_FS_OVR	(MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_FSH_OVR	(MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_RES4		(MXC_EXP_IO_BASE + 4)
-#define EXPIO_INT_RES5		(MXC_EXP_IO_BASE + 5)
-#define EXPIO_INT_RES6		(MXC_EXP_IO_BASE + 6)
-#define EXPIO_INT_RES7		(MXC_EXP_IO_BASE + 7)
-#define EXPIO_INT_ENET_INT	(MXC_EXP_IO_BASE + 8)
-#define EXPIO_INT_OTG_FS_INT	(MXC_EXP_IO_BASE + 9)
-#define EXPIO_INT_XUART_INTA	(MXC_EXP_IO_BASE + 10)
-#define EXPIO_INT_XUART_INTB	(MXC_EXP_IO_BASE + 11)
-#define EXPIO_INT_SYNTH_IRQ	(MXC_EXP_IO_BASE + 12)
-#define EXPIO_INT_CE_INT1	(MXC_EXP_IO_BASE + 13)
-#define EXPIO_INT_CE_INT2	(MXC_EXP_IO_BASE + 14)
-#define EXPIO_INT_RES15		(MXC_EXP_IO_BASE + 15)
-
-#define MXC_MAX_EXP_IO_LINES	16
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:05 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:05 +0200
Subject: [PATCH 09/61] ARM: mx2/mx27ads: fold board header in its only user
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-10-git-send-email-u.kleine-koenig@pengutronix.de>

Moreover remove unused definitions.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx2/mach-mx27ads.c               |   32 ++-
 arch/arm/plat-mxc/include/mach/board-mx27ads.h |  344 ------------------------
 2 files changed, 30 insertions(+), 346 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx27ads.h

diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-mx2/mach-mx27ads.c
index 6ce3236..2183e3d 100644
--- a/arch/arm/mach-mx2/mach-mx27ads.c
+++ b/arch/arm/mach-mx2/mach-mx27ads.c
@@ -34,7 +34,6 @@
 #include <mach/gpio.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
-#include <mach/board-mx27ads.h>
 #include <mach/mxc_nand.h>
 #include <mach/i2c.h>
 #include <mach/imxfb.h>
@@ -42,6 +41,36 @@
 
 #include "devices.h"
 
+/*
+ * Base address of PBC controller, CS4
+ */
+#define PBC_BASE_ADDRESS        0xf4300000
+#define PBC_REG_ADDR(offset)    (void __force __iomem *) \
+		(PBC_BASE_ADDRESS + (offset))
+
+/* When the PBC address connection is fixed in h/w, defined as 1 */
+#define PBC_ADDR_SH             0
+
+/* Offsets for the PBC Controller register */
+/*
+ * PBC Board version register offset
+ */
+#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
+/*
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
+
+/* PBC Board Control Register 1 bit definitions */
+#define PBC_BCTRL1_LCDON        0x0800	/* Enable the LCD */
+
+/* to determine the correct external crystal reference */
+#define CKIH_27MHZ_BIT_SET      (1 << 3)
+
 static unsigned int mx27ads_pins[] = {
 	/* UART0 */
 	PE12_PF_UART1_TXD,
@@ -342,4 +371,3 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
 	.init_machine   = mx27ads_board_init,
 	.timer          = &mx27ads_timer,
 MACHINE_END
-
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
deleted file mode 100644
index 7776d23..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
-
-/* external interrupt multiplexer */
-#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
-
-#define MXC_VIRTUAL_INTS_BASE	(MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
-#define MXC_SDIO1_CARD_IRQ	MXC_VIRTUAL_INTS_BASE
-#define MXC_SDIO2_CARD_IRQ	(MXC_VIRTUAL_INTS_BASE + 1)
-#define MXC_SDIO3_CARD_IRQ	(MXC_VIRTUAL_INTS_BASE + 2)
-
-#define MXC_MAX_BOARD_INTS      (MXC_MAX_EXP_IO_LINES + \
-				MXC_MAX_VIRTUAL_INTS)
-
-/*
- * @name Memory Size parameters
- */
-
-/*
- * Size of SDRAM memory
- */
-#define SDRAM_MEM_SIZE          SZ_128M
-
-/*
- * PBC Controller parameters
- */
-
-/*
- * Base address of PBC controller, CS4
- */
-#define PBC_BASE_ADDRESS        0xf4300000
-#define PBC_REG_ADDR(offset)    (void __force __iomem *) \
-		(PBC_BASE_ADDRESS + (offset))
-
-/*
- * PBC Interupt name definitions
- */
-#define PBC_GPIO1_0  0
-#define PBC_GPIO1_1  1
-#define PBC_GPIO1_2  2
-#define PBC_GPIO1_3  3
-#define PBC_GPIO1_4  4
-#define PBC_GPIO1_5  5
-
-#define PBC_INTR_MAX_NUM 6
-#define PBC_INTR_SHARED_MAX_NUM 8
-
-/* When the PBC address connection is fixed in h/w, defined as 1 */
-#define PBC_ADDR_SH             0
-
-/* Offsets for the PBC Controller register */
-/*
- * PBC Board version register offset
- */
-#define PBC_VERSION_REG         PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 1 set address.
- */
-#define PBC_BCTRL1_SET_REG      PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 1 clear address.
- */
-#define PBC_BCTRL1_CLEAR_REG    PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
-/*
- * PBC Board control register 2 set address.
- */
-#define PBC_BCTRL2_SET_REG      PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 2 clear address.
- */
-#define PBC_BCTRL2_CLEAR_REG    PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 3 set address.
- */
-#define PBC_BCTRL3_SET_REG      PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 3 clear address.
- */
-#define PBC_BCTRL3_CLEAR_REG    PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
-/*
- * PBC Board control register 3 set address.
- */
-#define PBC_BCTRL4_SET_REG      PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
-/*
- * PBC Board control register 4 clear address.
- */
-#define PBC_BCTRL4_CLEAR_REG    PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
-/*PBC_ADDR_SH
- * PBC Board status register 1.
- */
-#define PBC_BSTAT1_REG          PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
-/*
- * PBC Board interrupt status register.
- */
-#define PBC_INTSTATUS_REG       PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
-/*
- * PBC Board interrupt current status register.
- */
-#define PBC_INTCURR_STATUS_REG  PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
-/*
- * PBC Interrupt mask register set address.
- */
-#define PBC_INTMASK_SET_REG     PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
-/*
- * PBC Interrupt mask register clear address.
- */
-#define PBC_INTMASK_CLEAR_REG   PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
-/*
- * External UART A.
- */
-#define PBC_SC16C652_UARTA_REG  PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
-/*
- * UART 4 Expanding Signal Status.
- */
-#define PBC_UART_STATUS_REG     PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
-/*
- * UART 4 Expanding Signal Control Set.
- */
-#define PBC_UCTRL_SET_REG       PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
-/*
- * UART 4 Expanding Signal Control Clear.
- */
-#define PBC_UCTRL_CLR_REG       PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
-/*
- * Ethernet Controller IO base address.
- */
-#define PBC_CS8900A_IOBASE_REG  PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
-/*
- * Ethernet Controller Memory base address.
- */
-#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
-/*
- * Ethernet Controller DMA base address.
- */
-#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
-
-/* PBC Board Version Register bit definition */
-#define PBC_VERSION_ADS         0x8000	/* Bit15=1 means version for ads */
-#define PBC_VERSION_EVB_REVB    0x4000	/* BIT14=1 means version for evb revb */
-
-/* PBC Board Control Register 1 bit definitions */
-#define PBC_BCTRL1_ERST         0x0001	/* Ethernet Reset */
-#define PBC_BCTRL1_URST         0x0002	/* Reset External UART controller */
-#define PBC_BCTRL1_FRST         0x0004	/* FEC Reset */
-#define PBC_BCTRL1_ESLEEP       0x0010	/* Enable ethernet Sleep */
-#define PBC_BCTRL1_LCDON        0x0800	/* Enable the LCD */
-
-/* PBC Board Control Register 2 bit definitions */
-#define PBC_BCTRL2_VCC_EN       0x0004	/*   Enable VCC */
-#define PBC_BCTRL2_VPP_EN       0x0008	/*   Enable Vpp */
-#define PBC_BCTRL2_ATAFEC_EN    0X0010
-#define PBC_BCTRL2_ATAFEC_SEL   0X0020
-#define PBC_BCTRL2_ATA_EN       0X0040
-#define PBC_BCTRL2_IRDA_SD      0X0080
-#define PBC_BCTRL2_IRDA_EN      0X0100
-#define PBC_BCTRL2_CCTL10       0X0200
-#define PBC_BCTRL2_CCTL11       0X0400
-
-/* PBC Board Control Register 3 bit definitions */
-#define PBC_BCTRL3_HSH_EN       0X0020
-#define PBC_BCTRL3_FSH_MOD      0X0040
-#define PBC_BCTRL3_OTG_HS_EN    0X0080
-#define PBC_BCTRL3_OTG_VBUS_EN  0X0100
-#define PBC_BCTRL3_FSH_VBUS_EN  0X0200
-#define PBC_BCTRL3_USB_OTG_ON   0X0800
-#define PBC_BCTRL3_USB_FSH_ON   0X1000
-
-/* PBC Board Control Register 4 bit definitions */
-#define PBC_BCTRL4_REGEN_SEL    0X0001
-#define PBC_BCTRL4_USER_OFF     0X0002
-#define PBC_BCTRL4_VIB_EN       0X0004
-#define PBC_BCTRL4_PWRGT1_EN    0X0008
-#define PBC_BCTRL4_PWRGT2_EN    0X0010
-#define PBC_BCTRL4_STDBY_PRI    0X0020
-
-#ifndef __ASSEMBLY__
-/*
- * Enumerations for SD cards and memory stick card. This corresponds to
- * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
- */
-enum mxc_card_no {
-	MXC_CARD_SD2 = 0,
-	MXC_CARD_SD3,
-	MXC_CARD_MS,
-	MXC_CARD_SD1,
-	MXC_CARD_MIN = MXC_CARD_SD2,
-	MXC_CARD_MAX = MXC_CARD_SD1,
-};
-#endif
-
-#define MXC_CPLD_VER_1_50       0x01
-
-/*
- * PBC BSTAT Register bit definitions
- */
-#define PBC_BSTAT_PRI_INT       0X0001
-#define PBC_BSTAT_USB_BYP       0X0002
-#define PBC_BSTAT_ATA_IOCS16    0X0004
-#define PBC_BSTAT_ATA_CBLID     0X0008
-#define PBC_BSTAT_ATA_DASP      0X0010
-#define PBC_BSTAT_PWR_RDY       0X0020
-#define PBC_BSTAT_SD3_WP        0X0100
-#define PBC_BSTAT_SD2_WP        0X0200
-#define PBC_BSTAT_SD1_WP        0X0400
-#define PBC_BSTAT_SD3_DET       0X0800
-#define PBC_BSTAT_SD2_DET       0X1000
-#define PBC_BSTAT_SD1_DET       0X2000
-#define PBC_BSTAT_MS_DET        0X4000
-#define PBC_BSTAT_SD3_DET_BIT   11
-#define PBC_BSTAT_SD2_DET_BIT   12
-#define PBC_BSTAT_SD1_DET_BIT   13
-#define PBC_BSTAT_MS_DET_BIT    14
-#define MXC_BSTAT_BIT(n)        ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
-				 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
-				 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
-				 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
-					0x0))))
-
-/*
- * PBC UART Control Register bit definitions
- */
-#define PBC_UCTRL_DCE_DCD       0X0001
-#define PBC_UCTRL_DCE_DSR       0X0002
-#define PBC_UCTRL_DCE_RI        0X0004
-#define PBC_UCTRL_DTE_DTR       0X0100
-
-/*
- * PBC UART Status Register bit definitions
- */
-#define PBC_USTAT_DTE_DCD       0X0001
-#define PBC_USTAT_DTE_DSR       0X0002
-#define PBC_USTAT_DTE_RI        0X0004
-#define PBC_USTAT_DCE_DTR       0X0100
-
-/*
- * PBC Interupt mask register bit definitions
- */
-#define PBC_INTR_SD3_R_EN_BIT   4
-#define PBC_INTR_SD2_R_EN_BIT   0
-#define PBC_INTR_SD1_R_EN_BIT   6
-#define PBC_INTR_MS_R_EN_BIT    5
-#define PBC_INTR_SD3_EN_BIT     13
-#define PBC_INTR_SD2_EN_BIT     12
-#define PBC_INTR_MS_EN_BIT      14
-#define PBC_INTR_SD1_EN_BIT     15
-
-#define PBC_INTR_SD2_R_EN       0x0001
-#define PBC_INTR_LOW_BAT        0X0002
-#define PBC_INTR_OTG_FSOVER     0X0004
-#define PBC_INTR_FSH_OVER       0X0008
-#define PBC_INTR_SD3_R_EN       0x0010
-#define PBC_INTR_MS_R_EN        0x0020
-#define PBC_INTR_SD1_R_EN       0x0040
-#define PBC_INTR_FEC_INT        0X0080
-#define PBC_INTR_ENET_INT       0X0100
-#define PBC_INTR_OTGFS_INT      0X0200
-#define PBC_INTR_XUART_INT      0X0400
-#define PBC_INTR_CCTL12         0X0800
-#define PBC_INTR_SD2_EN         0x1000
-#define PBC_INTR_SD3_EN         0x2000
-#define PBC_INTR_MS_EN          0x4000
-#define PBC_INTR_SD1_EN         0x8000
-
-
-
-/* For interrupts like xuart, enet etc */
-#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX27_PIN_TIN)
-#define MXC_MAX_EXP_IO_LINES    16
-
-/*
- * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
- *
- */
-#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
-#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
-#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
-#define EXPIO_INT_FEC           (MXC_EXP_IO_BASE + 7)
-#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
-#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
-#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
-#define EXPIO_INT_CCTL12_INT    (MXC_EXP_IO_BASE + 11)
-#define EXPIO_INT_SD2_EN        (MXC_EXP_IO_BASE + 12)
-#define EXPIO_INT_SD3_EN        (MXC_EXP_IO_BASE + 13)
-#define EXPIO_INT_MS_EN         (MXC_EXP_IO_BASE + 14)
-#define EXPIO_INT_SD1_EN        (MXC_EXP_IO_BASE + 15)
-
-/*
- * This is System IRQ used by CS8900A for interrupt generation
- * taken from platform.h
- */
-#define CS8900AIRQ              EXPIO_INT_ENET_INT
-/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
-#define CS8900A_BASE_ADDRESS    (PBC_CS8900A_IOBASE_REG + 0x300)
-
-#define MXC_PMIC_INT_LINE       IOMUX_TO_IRQ(MX27_PIN_TOUT)
-
-/*
-* This is used to detect if the CPLD version is for mx27 evb board rev-a
-*/
-#define PBC_CPLD_VERSION_IS_REVA() \
-	((__raw_readw(PBC_VERSION_REG) & \
-	(PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
-	== 0)
-
-/* This is used to active or inactive ata signal in CPLD .
- *  It is dependent with hardware
- */
-#define PBC_ATA_SIGNAL_ACTIVE() \
-	__raw_writew(           \
-		PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
-		PBC_BCTRL2_CLEAR_REG)
-
-#define PBC_ATA_SIGNAL_INACTIVE() \
-	__raw_writew(  \
-		PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
-		PBC_BCTRL2_SET_REG)
-
-#define MXC_BD_LED1             (1 << 5)
-#define MXC_BD_LED2             (1 << 6)
-#define MXC_BD_LED_ON(led) \
-	__raw_writew(led, PBC_BCTRL1_SET_REG)
-#define MXC_BD_LED_OFF(led) \
-	__raw_writew(led, PBC_BCTRL1_CLEAR_REG)
-
-/* to determine the correct external crystal reference */
-#define CKIH_27MHZ_BIT_SET      (1 << 3)
-
-#endif				/* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:17 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:17 +0200
Subject: [PATCH 21/61] ARM: mx3: mx31lilly: fix build error for
	!CONFIG_USB_ULPI
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-22-git-send-email-u.kleine-koenig@pengutronix.de>

arch/arm/mach-mx3/built-in.o: In function `mx31lilly_board_init':
mach-kzm_arm11_01.c:(.init.text+0x674): undefined reference to `otg_ulpi_create'
mach-kzm_arm11_01.c:(.init.text+0x68c): undefined reference to `otg_ulpi_create'
mach-kzm_arm11_01.c:(.init.text+0x744): undefined reference to `mxc_ulpi_access_ops'
make: *** [.tmp_vmlinux1] Error 1

Signed-off-by: Daniel Mack <daniel at caiaq.de>
Cc: Sascha Hauer <s.hauer at pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
 arch/arm/mach-mx3/mach-mx31lilly.c |   33 ++++++++++++++++++++++-----------
 1 files changed, 22 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index d3d5877..b2c7f51 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -115,6 +115,8 @@ static struct platform_device physmap_flash_device = {
 
 /* USB */
 
+#if defined(CONFIG_USB_ULPI)
+
 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
 			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
 
@@ -244,10 +246,20 @@ static struct mxc_usbh_platform_data usbh2_pdata = {
 	.flags	= MXC_EHCI_POWER_PINS_ENABLED,
 };
 
-static struct platform_device *devices[] __initdata = {
-	&smsc91x_device,
-	&physmap_flash_device,
-};
+static void lilly1131_usb_init(void)
+{
+	usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
+				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
+
+	mxc_register_device(&mxc_usbh1, &usbh1_pdata);
+	mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+}
+
+#else
+static inline void lilly1131_usb_init(void) {}
+#endif /* CONFIG_USB_ULPI */
 
 /* SPI */
 
@@ -279,6 +291,11 @@ static struct spi_board_info mc13783_dev __initdata = {
 	.platform_data	= &mc13783_pdata,
 };
 
+static struct platform_device *devices[] __initdata = {
+	&smsc91x_device,
+	&physmap_flash_device,
+};
+
 static int mx31lilly_baseboard;
 core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444);
 
@@ -321,13 +338,7 @@ static void __init mx31lilly_board_init(void)
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	/* USB */
-	usbotg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
-	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
-				USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
-
-	mxc_register_device(&mxc_usbh1, &usbh1_pdata);
-	mxc_register_device(&mxc_usbh2, &usbh2_pdata);
+	lilly1131_usb_init();
 }
 
 static void __init mx31lilly_timer_init(void)
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:00 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:00 +0200
Subject: [PATCH 04/61] ARM: mx1/scb9328: fix type of uart1_mxc_exit to make
	compiler happy
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-5-git-send-email-u.kleine-koenig@pengutronix.de>

This fixes:

	arch/arm/mach-mx1/mach-scb9328.c:120: warning: initialization from incompatible pointer type

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx1/mach-scb9328.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-mx1/mach-scb9328.c
index 7c6bbe8..ed2ff16 100644
--- a/arch/arm/mach-mx1/mach-scb9328.c
+++ b/arch/arm/mach-mx1/mach-scb9328.c
@@ -108,11 +108,10 @@ static int uart1_mxc_init(struct platform_device *pdev)
 			ARRAY_SIZE(mxc_uart1_pins), "UART1");
 }
 
-static int uart1_mxc_exit(struct platform_device *pdev)
+static void uart1_mxc_exit(struct platform_device *pdev)
 {
 	mxc_gpio_release_multiple_pins(mxc_uart1_pins,
 			ARRAY_SIZE(mxc_uart1_pins));
-	return 0;
 }
 
 static struct imxuart_platform_data uart_pdata = {
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:56 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:56 +0200
Subject: [PATCH 60/61] ARM: imx: dynamically register imx-uart devices (imx35)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-61-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/Kconfig         |    2 +
 arch/arm/mach-mx3/devices-imx35.h |    7 ++++
 arch/arm/mach-mx3/devices.c       |   59 -------------------------------------
 arch/arm/mach-mx3/devices.h       |    5 ---
 arch/arm/mach-mx3/mach-mx35_3ds.c |    6 ++--
 arch/arm/mach-mx3/mach-pcm043.c   |    7 ++--
 6 files changed, 15 insertions(+), 71 deletions(-)

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 7f2d5a6..594502a 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -116,6 +116,7 @@ config MACH_PCM043
 	bool "Support Phytec pcm043 (i.MX35) platforms"
 	select ARCH_MX35
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
@@ -136,6 +137,7 @@ config MACH_ARMADILLO5X0
 config MACH_MX35_3DS
 	bool "Support MX35PDK platform"
 	select ARCH_MX35
+	select IMX_HAVE_PLATFORM_IMX_UART
 	default n
 	help
 	  Include support for MX35PDK platform. This includes specific
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index b595fa6..536d9b9 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -16,6 +16,13 @@
 #define imx35_add_imx_i2c2(pdata)	\
 	imx_add_imx_i2c(2, MX35_I2C3_BASE_ADDR, SZ_4K, MX35_INT_I2C3, pdata)
 
+#define imx35_add_imx_uart0(pdata)	\
+	imx_add_imx_uart_1irq(0, MX35_UART1_BASE_ADDR, SZ_16K, MX35_INT_UART1, pdata)
+#define imx35_add_imx_uart1(pdata)	\
+	imx_add_imx_uart_1irq(1, MX35_UART2_BASE_ADDR, SZ_16K, MX35_INT_UART2, pdata)
+#define imx35_add_imx_uart2(pdata)	\
+	imx_add_imx_uart_1irq(2, MX35_UART3_BASE_ADDR, SZ_16K, MX35_INT_UART3, pdata)
+
 #define imx35_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
 
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 5b42862..a4fd1a2 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -29,65 +29,6 @@
 
 #include "devices.h"
 
-#if defined(CONFIG_ARCH_MX35)
-static struct resource uart0[] = {
-	{
-		.start = UART1_BASE_ADDR,
-		.end = UART1_BASE_ADDR + 0x0B5,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MXC_INT_UART1,
-		.end = MXC_INT_UART1,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device0 = {
-	.name = "imx-uart",
-	.id = 0,
-	.resource = uart0,
-	.num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-	{
-		.start = UART2_BASE_ADDR,
-		.end = UART2_BASE_ADDR + 0x0B5,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MXC_INT_UART2,
-		.end = MXC_INT_UART2,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device1 = {
-	.name = "imx-uart",
-	.id = 1,
-	.resource = uart1,
-	.num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-	{
-		.start = UART3_BASE_ADDR,
-		.end = UART3_BASE_ADDR + 0x0B5,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MXC_INT_UART3,
-		.end = MXC_INT_UART3,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device2 = {
-	.name = "imx-uart",
-	.id = 2,
-	.resource = uart2,
-	.num_resources = ARRAY_SIZE(uart2),
-};
-#endif
-
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
 	{
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 5a156f1..e553523 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -1,8 +1,3 @@
-#if defined(CONFIG_ARCH_MX35)
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-#endif
 extern struct platform_device mxc_w1_master_device;
 extern struct platform_device mx3_ipu;
 extern struct platform_device mx3_fb;
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index cfac778..1c30d72 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -34,12 +34,12 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx35.h>
 
+#include "devices-imx35.h"
 #include "devices.h"
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -92,7 +92,7 @@ static void __init mxc_board_init(void)
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	imx35_add_imx_uart0(&uart_pdata);
 
 	mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
 }
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 21305c6..97cc364 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -36,7 +36,6 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx35.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
@@ -115,7 +114,7 @@ static struct platform_device pcm043_flash = {
 	.num_resources = 1,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -355,11 +354,11 @@ static void __init mxc_board_init(void)
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	imx35_add_imx_uart0(&uart_pdata);
 	imx35_add_mxc_nand(&pcm037_nand_board_info);
 	mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
 
-	mxc_register_device(&mxc_uart_device1, &uart_pdata);
+	imx35_add_imx_uart1(&uart_pdata);
 
 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
 	i2c_register_board_info(0, pcm043_i2c_devices,
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:28 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:28 +0200
Subject: [PATCH 32/61] ARM: mx3: remove paragraphs with old address of the FSF
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-33-git-send-email-u.kleine-koenig@pengutronix.de>

As the kernel contains a copy of the GPL anyhow just get rid of the address
specification instead of fixing it.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/mach-kzm_arm11_01.c    |    4 ----
 arch/arm/mach-mx3/mach-mx31_3ds.c        |    4 ----
 arch/arm/mach-mx3/mach-mx31ads.c         |    4 ----
 arch/arm/mach-mx3/mach-mx31lilly.c       |    4 ----
 arch/arm/mach-mx3/mach-mx31lite.c        |    4 ----
 arch/arm/mach-mx3/mach-mx31moboard.c     |    4 ----
 arch/arm/mach-mx3/mach-mx35_3ds.c        |    4 ----
 arch/arm/mach-mx3/mach-pcm037.c          |    4 ----
 arch/arm/mach-mx3/mach-pcm043.c          |    4 ----
 arch/arm/mach-mx3/mach-qong.c            |    4 ----
 arch/arm/mach-mx3/mm.c                   |    4 ----
 arch/arm/mach-mx3/mx31lilly-db.c         |    4 ----
 arch/arm/mach-mx3/mx31lite-db.c          |    4 ----
 arch/arm/mach-mx3/mx31moboard-devboard.c |    4 ----
 arch/arm/mach-mx3/mx31moboard-marxbot.c  |    4 ----
 arch/arm/mach-mx3/mx31moboard-smartbot.c |    4 ----
 16 files changed, 0 insertions(+), 64 deletions(-)

diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index e60f5da..1129140 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -16,10 +16,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/gpio.h>
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 53740b4..33f2554 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index ed34b61..a68b868 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index b2c7f51..b4cfbe0 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -18,10 +18,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 2b6d114..edcc711 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 62b5e40..545cfdd 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index 66ad2da..cfac778 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 /*
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 8419370..c1f335c 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 78d9185..100bb77 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index 62281ad..335b0bf 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/types.h>
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 595cf09..a378fba 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -14,10 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/mm.h>
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
index 7aebd74..2e50951 100644
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-mx3/mx31lilly-db.c
@@ -18,10 +18,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index 5f05bfb..e35d2eb 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -18,10 +18,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/kernel.h>
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 582299c..44473b1 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/gpio.h>
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 4930f8c..0551eb3 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index 293eea6..f45a500 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -10,10 +10,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/delay.h>
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:16 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:16 +0200
Subject: [PATCH 20/61] ARM: imx1: rename imx_uart[12]_device to follow a
	common naming scheme
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-21-git-send-email-u.kleine-koenig@pengutronix.de>

Note that these devices are specific for imx1 as only here three irqs are
used.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx1/devices.c      |   81 +++++++++++++------------------------
 arch/arm/mach-mx1/devices.h      |    4 +-
 arch/arm/mach-mx1/mach-mx1ads.c  |    4 +-
 arch/arm/mach-mx1/mach-scb9328.c |    2 +-
 4 files changed, 34 insertions(+), 57 deletions(-)

diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
index c770aa0..a79e613 100644
--- a/arch/arm/mach-mx1/devices.c
+++ b/arch/arm/mach-mx1/devices.c
@@ -73,59 +73,36 @@ struct platform_device imx_i2c_device0 = {
 	.num_resources  = ARRAY_SIZE(imx_i2c_resources),
 };
 
-static struct resource imx_uart1_resources[] = {
-	{
-		.start = MX1_UART1_BASE_ADDR,
-		.end = MX1_UART1_BASE_ADDR + 0xD0,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MX1_UART1_MINT_RX,
-		.end = MX1_UART1_MINT_RX,
-		.flags = IORESOURCE_IRQ,
-	}, {
-		.start = MX1_UART1_MINT_TX,
-		.end = MX1_UART1_MINT_TX,
-		.flags = IORESOURCE_IRQ,
-	}, {
-		.start = MX1_UART1_MINT_RTS,
-		.end = MX1_UART1_MINT_RTS,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device imx_uart1_device = {
-	.name		= "imx-uart",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(imx_uart1_resources),
-	.resource	= imx_uart1_resources,
-};
-
-static struct resource imx_uart2_resources[] = {
-	{
-		.start = MX1_UART2_BASE_ADDR,
-		.end = MX1_UART2_BASE_ADDR + 0xD0,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MX1_UART2_MINT_RX,
-		.end = MX1_UART2_MINT_RX,
-		.flags = IORESOURCE_IRQ,
-	}, {
-		.start = MX1_UART2_MINT_TX,
-		.end = MX1_UART2_MINT_TX,
-		.flags = IORESOURCE_IRQ,
-	}, {
-		.start = MX1_UART2_MINT_RTS,
-		.end = MX1_UART2_MINT_RTS,
-		.flags = IORESOURCE_IRQ,
-	},
-};
+#define DEFINE_IMX1_UART_DEVICE(n, baseaddr, irqrx, irqtx, irqrts)	\
+	static struct resource imx1_uart_resources ## n[] = {		\
+		{							\
+			.start = baseaddr,				\
+			.end = baseaddr + 0xd0,				\
+			.flags = IORESOURCE_MEM,			\
+		}, {							\
+			.start = irqrx,					\
+			.end = irqrx,					\
+			.flags = IORESOURCE_IRQ,			\
+		}, {							\
+			.start = irqtx,					\
+			.end = irqtx,					\
+			.flags = IORESOURCE_IRQ,			\
+		}, {							\
+			.start = irqrts,				\
+			.end = irqrts,					\
+			.flags = IORESOURCE_IRQ,			\
+		},							\
+	};								\
+									\
+	struct platform_device imx1_uart_device ## n = {		\
+		.name = "imx-uart",					\
+		.id = n,						\
+		.num_resources = ARRAY_SIZE(imx1_uart_resources ## n),	\
+		.resource = imx1_uart_resources ## n,			\
+	}
 
-struct platform_device imx_uart2_device = {
-	.name		= "imx-uart",
-	.id		= 1,
-	.num_resources	= ARRAY_SIZE(imx_uart2_resources),
-	.resource	= imx_uart2_resources,
-};
+DEFINE_IMX1_UART_DEVICE(0, MX1_UART1_BASE_ADDR, MX1_UART1_MINT_RX, MX1_UART1_MINT_TX, MX1_UART1_MINT_RTS);
+DEFINE_IMX1_UART_DEVICE(1, MX1_UART2_BASE_ADDR, MX1_UART2_MINT_RX, MX1_UART2_MINT_TX, MX1_UART2_MINT_RTS);
 
 static struct resource imx_rtc_resources[] = {
 	{
diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h
index 851d6df..1332516 100644
--- a/arch/arm/mach-mx1/devices.h
+++ b/arch/arm/mach-mx1/devices.h
@@ -1,7 +1,7 @@
 extern struct platform_device imx1_camera_device;
 extern struct platform_device imx_i2c_device0;
-extern struct platform_device imx_uart1_device;
-extern struct platform_device imx_uart2_device;
+extern struct platform_device imx1_uart_device0;
+extern struct platform_device imx1_uart_device1;
 extern struct platform_device imx_rtc_device;
 extern struct platform_device imx_wdt_device;
 extern struct platform_device imx_usb_device;
diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c
index 16adc61..5d7c85f 100644
--- a/arch/arm/mach-mx1/mach-mx1ads.c
+++ b/arch/arm/mach-mx1/mach-mx1ads.c
@@ -121,8 +121,8 @@ static void __init mx1ads_init(void)
 		ARRAY_SIZE(mx1ads_pins), "mx1ads");
 
 	/* UART */
-	mxc_register_device(&imx_uart1_device, &uart_pdata[0]);
-	mxc_register_device(&imx_uart2_device, &uart_pdata[1]);
+	mxc_register_device(&imx1_uart_device0, &uart_pdata[0]);
+	mxc_register_device(&imx1_uart_device1, &uart_pdata[1]);
 
 	/* Physmap flash */
 	mxc_register_device(&flash_device, &mx1ads_flash_data);
diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-mx1/mach-scb9328.c
index ed2ff16..482b24d 100644
--- a/arch/arm/mach-mx1/mach-scb9328.c
+++ b/arch/arm/mach-mx1/mach-scb9328.c
@@ -130,7 +130,7 @@ static struct platform_device *devices[] __initdata = {
  */
 static void __init scb9328_init(void)
 {
-	mxc_register_device(&imx_uart1_device, &uart_pdata);
+	mxc_register_device(&imx1_uart_device0, &uart_pdata);
 
 	printk(KERN_INFO"Scb9328: Adding devices\n");
 	platform_add_devices(devices, ARRAY_SIZE(devices));
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:20 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:20 +0200
Subject: [PATCH 24/61] ARM: imx: Kconfig: use an if block instead of a depend
	for many symbols
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-25-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig |   20 +++++++++++---------
 1 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c6eddd7..3ca8fa7 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -37,25 +37,32 @@ config MACH_MX27
 
 endchoice
 
-comment "MX2 platforms:"
+endif
+
+if MACH_MX21
+
+comment "MX21 platforms:"
 
 config MACH_MX21ADS
 	bool "MX21ADS platform"
-	depends on MACH_MX21
 	help
 	  Include support for MX21ADS platform. This includes specific
 	  configurations for the board and its peripherals.
 
+endif
+
+if MACH_MX27
+
+comment "MX27 platforms:"
+
 config MACH_MX27ADS
 	bool "MX27ADS platform"
-	depends on MACH_MX27
 	help
 	  Include support for MX27ADS platform. This includes specific
 	  configurations for the board and its peripherals.
 
 config MACH_PCM038
 	bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
-	depends on MACH_MX27
 	select MXC_ULPI if USB_ULPI
 	help
 	  Include support for phyCORE-i.MX27 (aka pcm038) platform. This
@@ -77,7 +84,6 @@ endchoice
 
 config MACH_CPUIMX27
 	bool "Eukrea CPUIMX27 module"
-	depends on MACH_MX27
 	help
 	  Include support for Eukrea CPUIMX27 platform. This includes
 	  specific configurations for the module and its peripherals.
@@ -105,21 +111,18 @@ endchoice
 
 config MACH_MX27_3DS
 	bool "MX27PDK platform"
-	depends on MACH_MX27
 	help
 	  Include support for MX27PDK platform. This includes specific
 	  configurations for the board and its peripherals.
 
 config MACH_IMX27LITE
 	bool "LogicPD MX27 LITEKIT platform"
-	depends on MACH_MX27
 	help
 	  Include support for MX27 LITEKIT platform. This includes specific
 	  configurations for the board and its peripherals.
 
 config MACH_PCA100
 	bool "Phytec phyCARD-s (pca100)"
-	depends on MACH_MX27
 	select MXC_ULPI if USB_ULPI
 	help
 	  Include support for phyCARD-s (aka pca100) platform. This
@@ -127,7 +130,6 @@ config MACH_PCA100
 
 config MACH_MXT_TD60
 	bool "Maxtrack i-MXT TD60"
-	depends on MACH_MX27
 	help
 	  Include support for i-MXT (aka td60) platform. This
 	  includes specific configurations for the module and its peripherals.
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:07 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:07 +0200
Subject: [PATCH 11/61] ARM: mx3/mx31_3ds: fold board header in its only user
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-12-git-send-email-u.kleine-koenig@pengutronix.de>

Moreover remove unused definitions.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/mach-mx31_3ds.c               |   42 +++++++++++++---
 arch/arm/plat-mxc/include/mach/board-mx31_3ds.h |   59 -----------------------
 2 files changed, 35 insertions(+), 66 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx31_3ds.h

diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 58e5729..53740b4 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -37,19 +37,47 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/board-mx31_3ds.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/mxc_nand.h>
 #include <mach/spi.h>
 #include "devices.h"
 
-/*!
- * @file mx31_3ds.c
- *
- * @brief This file contains the board-specific initialization routines.
- *
- * @ingroup System
+/* Definitions for components on the Debug board */
+
+/* Base address of CPLD controller on the Debug board */
+#define DEBUG_BASE_ADDRESS		CS5_IO_ADDRESS(MX3x_CS5_BASE_ADDR)
+
+/* LAN9217 ethernet base address */
+#define LAN9217_BASE_ADDR		MX3x_CS5_BASE_ADDR
+
+/* CPLD config and interrupt base address */
+#define CPLD_ADDR			(DEBUG_BASE_ADDRESS + 0x20000)
+
+/* status, interrupt */
+#define CPLD_INT_STATUS_REG		(CPLD_ADDR + 0x10)
+#define CPLD_INT_MASK_REG		(CPLD_ADDR + 0x38)
+#define CPLD_INT_RESET_REG		(CPLD_ADDR + 0x20)
+/* magic word for debug CPLD */
+#define CPLD_MAGIC_NUMBER1_REG		(CPLD_ADDR + 0x40)
+#define CPLD_MAGIC_NUMBER2_REG		(CPLD_ADDR + 0x48)
+/* CPLD code version */
+#define CPLD_CODE_VER_REG		(CPLD_ADDR + 0x50)
+/* magic word for debug CPLD */
+#define CPLD_MAGIC_NUMBER3_REG		(CPLD_ADDR + 0x58)
+
+/* CPLD IRQ line for external uart, external ethernet etc */
+#define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
+
+#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
+#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)
+
+#define EXPIO_INT_ENET		(MXC_EXP_IO_BASE + 0)
+
+#define MXC_MAX_EXP_IO_LINES	16
+
+/*
+ * This file contains the board-specific initialization routines.
  */
 
 static int mx31_3ds_pins[] = {
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h b/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
deleted file mode 100644
index da92933..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx31_3ds.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
-#define __ASM_ARCH_MXC_BOARD_MX31_3DS_H__
-
-/* Definitions for components on the Debug board */
-
-/* Base address of CPLD controller on the Debug board */
-#define DEBUG_BASE_ADDRESS		CS5_IO_ADDRESS(CS5_BASE_ADDR)
-
-/* LAN9217 ethernet base address */
-#define LAN9217_BASE_ADDR		CS5_BASE_ADDR
-
-/* CPLD config and interrupt base address */
-#define CPLD_ADDR			(DEBUG_BASE_ADDRESS + 0x20000)
-
-/* LED switchs */
-#define CPLD_LED_REG			(CPLD_ADDR + 0x00)
-/* buttons */
-#define CPLD_SWITCH_BUTTONS_REG	(EXPIO_ADDR + 0x08)
-/* status, interrupt */
-#define CPLD_INT_STATUS_REG		(CPLD_ADDR + 0x10)
-#define CPLD_INT_MASK_REG		(CPLD_ADDR + 0x38)
-#define CPLD_INT_RESET_REG		(CPLD_ADDR + 0x20)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER1_REG		(CPLD_ADDR + 0x40)
-#define CPLD_MAGIC_NUMBER2_REG		(CPLD_ADDR + 0x48)
-/* CPLD code version */
-#define CPLD_CODE_VER_REG		(CPLD_ADDR + 0x50)
-/* magic word for debug CPLD */
-#define CPLD_MAGIC_NUMBER3_REG		(CPLD_ADDR + 0x58)
-/* module reset register */
-#define CPLD_MODULE_RESET_REG		(CPLD_ADDR + 0x60)
-/* CPU ID and Personality ID */
-#define CPLD_MCU_BOARD_ID_REG		(CPLD_ADDR + 0x68)
-
-/* CPLD IRQ line for external uart, external ethernet etc */
-#define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
-
-#define MXC_EXP_IO_BASE		(MXC_BOARD_IRQ_START)
-#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_ENET		(MXC_EXP_IO_BASE + 0)
-#define EXPIO_INT_XUART_A	(MXC_EXP_IO_BASE + 1)
-#define EXPIO_INT_XUART_B	(MXC_EXP_IO_BASE + 2)
-#define EXPIO_INT_BUTTON_A	(MXC_EXP_IO_BASE + 3)
-#define EXPIO_INT_BUTTON_B	(MXC_EXP_IO_BASE + 4)
-
-#define MXC_MAX_EXP_IO_LINES	16
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX31_3DS_H__ */
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:14 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:14 +0200
Subject: [PATCH 18/61] ARM: imx1: rename imx_csi_device to match its .name
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-19-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx1/devices.c |   12 ++++++------
 arch/arm/mach-mx1/devices.h |    2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
index 860cbb7..fa3809d 100644
--- a/arch/arm/mach-mx1/devices.c
+++ b/arch/arm/mach-mx1/devices.c
@@ -29,7 +29,7 @@
 
 #include "devices.h"
 
-static struct resource imx_csi_resources[] = {
+static struct resource imx1_camera_resources[] = {
 	{
 		.start  = 0x00224000,
 		.end    = 0x00224010,
@@ -41,17 +41,17 @@ static struct resource imx_csi_resources[] = {
 	},
 };
 
-static u64 imx_csi_dmamask = DMA_BIT_MASK(32);
+static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
 
-struct platform_device imx_csi_device = {
+struct platform_device imx1_camera_device = {
 	.name           = "mx1-camera",
 	.id             = 0, /* This is used to put cameras on this interface */
 	.dev		= {
-		.dma_mask = &imx_csi_dmamask,
+		.dma_mask = &imx1_camera_dmamask,
 		.coherent_dma_mask = DMA_BIT_MASK(32),
 	},
-	.resource       = imx_csi_resources,
-	.num_resources  = ARRAY_SIZE(imx_csi_resources),
+	.resource       = imx1_camera_resources,
+	.num_resources  = ARRAY_SIZE(imx1_camera_resources),
 };
 
 static struct resource imx_i2c_resources[] = {
diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h
index 0da5d7c..899f8d9 100644
--- a/arch/arm/mach-mx1/devices.h
+++ b/arch/arm/mach-mx1/devices.h
@@ -1,4 +1,4 @@
-extern struct platform_device imx_csi_device;
+extern struct platform_device imx1_camera_device;
 extern struct platform_device imx_i2c_device;
 extern struct platform_device imx_uart1_device;
 extern struct platform_device imx_uart2_device;
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:25 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:25 +0200
Subject: [PATCH 29/61] MTD: mxc_nand: make bit fields unsigned to please sparse
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-30-git-send-email-u.kleine-koenig@pengutronix.de>

This fixes:

	arch/arm/plat-mxc/include/mach/mxc_nand.h:25:14: error: dubious one-bit signed bitfield
	arch/arm/plat-mxc/include/mach/mxc_nand.h:26:17: error: dubious one-bit signed bitfield

While at it make width unsigned, too.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/plat-mxc/include/mach/mxc_nand.h |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/mxc_nand.h b/arch/arm/plat-mxc/include/mach/mxc_nand.h
index 5d2d21d..28988c7 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_nand.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_nand.h
@@ -21,8 +21,8 @@
 #define __ASM_ARCH_NAND_H
 
 struct mxc_nand_platform_data {
-	int width;	/* data bus width in bytes */
-	int hw_ecc:1;	/* 0 if supress hardware ECC */
-	int flash_bbt:1; /* set to 1 to use a flash based bbt */
+	unsigned int width;	/* data bus width in bytes */
+	unsigned int hw_ecc:1;	/* 0 if supress hardware ECC */
+	unsigned int flash_bbt:1; /* set to 1 to use a flash based bbt */
 };
 #endif /* __ASM_ARCH_NAND_H */
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:55 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:55 +0200
Subject: [PATCH 59/61] ARM: imx: dynamically register imx-uart devices (imx31)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-60-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/Kconfig                |    9 ++++++
 arch/arm/mach-mx3/devices-imx31.h        |   11 +++++++
 arch/arm/mach-mx3/devices.c              |   43 +----------------------------
 arch/arm/mach-mx3/devices.h              |    5 +--
 arch/arm/mach-mx3/mach-armadillo5x0.c    |    7 ++---
 arch/arm/mach-mx3/mach-kzm_arm11_01.c    |    9 +++---
 arch/arm/mach-mx3/mach-mx31_3ds.c        |    5 +--
 arch/arm/mach-mx3/mach-mx31ads.c         |    5 +--
 arch/arm/mach-mx3/mach-mx31lite.c        |    1 -
 arch/arm/mach-mx3/mach-mx31moboard.c     |   10 +++----
 arch/arm/mach-mx3/mach-pcm037.c          |   10 +++---
 arch/arm/mach-mx3/mach-qong.c            |    9 +++---
 arch/arm/mach-mx3/mx31lilly-db.c         |   10 +++---
 arch/arm/mach-mx3/mx31lite-db.c          |    5 +--
 arch/arm/mach-mx3/mx31moboard-devboard.c |    6 ++--
 arch/arm/mach-mx3/mx31moboard-smartbot.c |    7 ++---
 16 files changed, 62 insertions(+), 90 deletions(-)

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index a8018e8..7f2d5a6 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -16,6 +16,7 @@ config MACH_MX31ADS
 	bool "Support MX31ADS platforms"
 	select ARCH_MX31
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_UART
 	default y
 	help
 	  Include support for MX31ADS platform. This includes specific
@@ -36,6 +37,7 @@ config MACH_PCM037
 	bool "Support Phytec pcm037 (i.MX31) platforms"
 	select ARCH_MX31
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
@@ -55,6 +57,7 @@ config MACH_MX31LITE
 	bool "Support MX31 LITEKIT (LogicPD)"
 	select ARCH_MX31
 	select MXC_ULPI if USB_ULPI
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	select IMX_HAVE_PLATFORM_SPI_IMX
 	help
@@ -64,6 +67,7 @@ config MACH_MX31LITE
 config MACH_MX31_3DS
 	bool "Support MX31PDK (3DS)"
 	select ARCH_MX31
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	select IMX_HAVE_PLATFORM_SPI_IMX
 	help
@@ -83,6 +87,7 @@ config MACH_MX31MOBOARD
 	bool "Support mx31moboard platforms (EPFL Mobots group)"
 	select ARCH_MX31
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_SPI_IMX
 	select MXC_ULPI if USB_ULPI
 	help
@@ -92,6 +97,7 @@ config MACH_MX31MOBOARD
 config MACH_MX31LILLY
 	bool "Support MX31 LILLY-1131 platforms (INCO startec)"
 	select ARCH_MX31
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_SPI_IMX
 	select MXC_ULPI if USB_ULPI
 	help
@@ -101,6 +107,7 @@ config MACH_MX31LILLY
 config MACH_QONG
 	bool "Support Dave/DENX QongEVB-LITE platform"
 	select ARCH_MX31
+	select IMX_HAVE_PLATFORM_IMX_UART
 	help
 	  Include support for Dave/DENX QongEVB-LITE platform. This includes
 	  specific configurations for the board and its peripherals.
@@ -119,6 +126,7 @@ config MACH_ARMADILLO5X0
 	bool "Support Atmark Armadillo-500 Development Base Board"
 	select ARCH_MX31
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
@@ -136,6 +144,7 @@ config MACH_MX35_3DS
 config MACH_KZM_ARM11_01
 	bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
 	select ARCH_MX31
+	select IMX_HAVE_PLATFORM_IMX_UART
 	help
 	  Include support for KZM-ARM11-01. This includes specific
 	  configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
index 1cf96ca..3b1a44a 100644
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -16,6 +16,17 @@
 #define imx31_add_imx_i2c2(pdata)	\
 	imx_add_imx_i2c(2, MX31_I2C3_BASE_ADDR, SZ_4K, MX31_INT_I2C3, pdata)
 
+#define imx31_add_imx_uart0(pdata)	\
+	imx_add_imx_uart_1irq(0, MX31_UART1_BASE_ADDR, SZ_16K, MX31_INT_UART1, pdata)
+#define imx31_add_imx_uart1(pdata)	\
+	imx_add_imx_uart_1irq(1, MX31_UART2_BASE_ADDR, SZ_16K, MX31_INT_UART2, pdata)
+#define imx31_add_imx_uart2(pdata)	\
+	imx_add_imx_uart_1irq(2, MX31_UART3_BASE_ADDR, SZ_16K, MX31_INT_UART3, pdata)
+#define imx31_add_imx_uart3(pdata)	\
+	imx_add_imx_uart_1irq(3, MX31_UART4_BASE_ADDR, SZ_16K, MX31_INT_UART4, pdata)
+#define imx31_add_imx_uart4(pdata)	\
+	imx_add_imx_uart_1irq(4, MX31_UART5_BASE_ADDR, SZ_16K, MX31_INT_UART5, pdata)
+
 #define imx31_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata)
 
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index dd90ee9..5b42862 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -25,11 +25,11 @@
 #include <mach/hardware.h>
 #include <mach/irqs.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/mx3_camera.h>
 
 #include "devices.h"
 
+#if defined(CONFIG_ARCH_MX35)
 static struct resource uart0[] = {
 	{
 		.start = UART1_BASE_ADDR,
@@ -86,46 +86,7 @@ struct platform_device mxc_uart_device2 = {
 	.resource = uart2,
 	.num_resources = ARRAY_SIZE(uart2),
 };
-
-#ifdef CONFIG_ARCH_MX31
-static struct resource uart3[] = {
-	{
-		.start = UART4_BASE_ADDR,
-		.end = UART4_BASE_ADDR + 0x0B5,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MXC_INT_UART4,
-		.end = MXC_INT_UART4,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device3 = {
-	.name = "imx-uart",
-	.id = 3,
-	.resource = uart3,
-	.num_resources = ARRAY_SIZE(uart3),
-};
-
-static struct resource uart4[] = {
-	{
-		.start = UART5_BASE_ADDR,
-		.end = UART5_BASE_ADDR + 0x0B5,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = MXC_INT_UART5,
-		.end = MXC_INT_UART5,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device4 = {
-	.name = "imx-uart",
-	.id = 4,
-	.resource = uart4,
-	.num_resources = ARRAY_SIZE(uart4),
-};
-#endif /* CONFIG_ARCH_MX31 */
+#endif
 
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 9380cd9..5a156f1 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -1,9 +1,8 @@
-
+#if defined(CONFIG_ARCH_MX35)
 extern struct platform_device mxc_uart_device0;
 extern struct platform_device mxc_uart_device1;
 extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
+#endif
 extern struct platform_device mxc_w1_master_device;
 extern struct platform_device mx3_ipu;
 extern struct platform_device mx3_fb;
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 423ffe7..96aadca 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -48,7 +48,6 @@
 #include <asm/mach/map.h>
 
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/mmc.h>
 #include <mach/ipu.h>
@@ -493,7 +492,7 @@ static struct platform_device armadillo5x0_smc911x_device = {
 };
 
 /* UART device data */
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -514,8 +513,8 @@ static void __init armadillo5x0_init(void)
 	imx31_add_imx_i2c1(NULL);
 
 	/* Register UART */
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
-	mxc_register_device(&mxc_uart_device1, &uart_pdata);
+	imx31_add_imx_uart0(&uart_pdata);
+	imx31_add_imx_uart1(&uart_pdata);
 
 	/* SMSC9118 IRQ pin */
 	gpio_direction_input(MX31_PIN_GPIO1_0);
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index 1129140..5b23e41 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -35,10 +35,10 @@
 
 #include <mach/clock.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/memory.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 #define KZM_ARM11_IO_ADDRESS(x) (					\
@@ -185,15 +185,14 @@ static inline int kzm_init_smsc9118(void)
 #endif
 
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
 static void __init kzm_init_imx_uart(void)
 {
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
-
-	mxc_register_device(&mxc_uart_device1, &uart_pdata);
+	imx31_add_imx_uart0(&uart_pdata);
+	imx31_add_imx_uart1(&uart_pdata);
 }
 #else
 static inline void kzm_init_imx_uart(void)
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 2aa3e58..4c021c5 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -33,7 +33,6 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 
 #include "devices-imx31.h"
@@ -233,7 +232,7 @@ static struct fsl_usb2_platform_data usbotg_pdata = {
 	.phy_mode	= FSL_USB2_PHY_ULPI,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -415,7 +414,7 @@ static void __init mxc_board_init(void)
 	mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
 				      "mx31_3ds");
 
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	imx31_add_imx_uart0(&uart_pdata);
 	imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
 
 	imx31_add_spi_imx0(&spi1_pdata);
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index b6dc6c8..94b3e7c 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -29,7 +29,6 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
@@ -124,7 +123,7 @@ static inline int mxc_init_extuart(void)
 #endif
 
 #if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -138,7 +137,7 @@ static unsigned int uart_pins[] = {
 static inline void mxc_init_imx_uart(void)
 {
 	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	imx31_add_imx_uart0(&uart_pdata);
 }
 #else /* !SERIAL_IMX */
 static inline void mxc_init_imx_uart(void)
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index 634b855..da236c4 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -38,7 +38,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/board-mx31lite.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/irqs.h>
 #include <mach/mxc_ehci.h>
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index 689b068..95633bb 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -38,7 +38,6 @@
 #include <mach/board-mx31moboard.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
 #include <mach/mmc.h>
@@ -131,11 +130,11 @@ static int moboard_uart0_init(struct platform_device *pdev)
 	return 0;
 }
 
-static struct imxuart_platform_data uart0_pdata = {
+static const struct imxuart_platform_data uart0_pdata __initconst = {
 	.init = moboard_uart0_init,
 };
 
-static struct imxuart_platform_data uart4_pdata = {
+static const struct imxuart_platform_data uart4_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -495,9 +494,8 @@ static void __init mxc_board_init(void)
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
-	mxc_register_device(&mxc_uart_device0, &uart0_pdata);
-
-	mxc_register_device(&mxc_uart_device4, &uart4_pdata);
+	imx31_add_imx_uart0(&uart0_pdata);
+	imx31_add_imx_uart4(&uart4_pdata);
 
 	imx31_add_imx_i2c0(&moboard_i2c0_data);
 	imx31_add_imx_i2c1(&moboard_i2c1_data);
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 7e3fc47..e71e390 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -41,7 +41,6 @@
 #include <asm/mach/map.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/ipu.h>
 #include <mach/mmc.h>
@@ -219,7 +218,7 @@ static struct platform_device pcm037_flash = {
 	.num_resources = 1,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -609,9 +608,10 @@ static void __init mxc_board_init(void)
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
-	mxc_register_device(&mxc_uart_device1, &uart_pdata);
-	mxc_register_device(&mxc_uart_device2, &uart_pdata);
+	imx31_add_imx_uart0(&uart_pdata);
+	/* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
+	imx31_add_imx_uart1(&uart_pdata);
+	imx31_add_imx_uart2(&uart_pdata);
 
 	mxc_register_device(&mxc_w1_master_device, NULL);
 
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
index 335b0bf..d44ac70 100644
--- a/arch/arm/mach-mx3/mach-qong.c
+++ b/arch/arm/mach-mx3/mach-qong.c
@@ -30,8 +30,9 @@
 #include <mach/common.h>
 #include <asm/page.h>
 #include <asm/setup.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
+
+#include "devices-imx31.h"
 #include "devices.h"
 
 /* FPGA defines */
@@ -57,7 +58,7 @@
  * This file contains the board-specific initialization routines.
  */
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -68,11 +69,11 @@ static int uart_pins[] = {
 	MX31_PIN_RXD1__RXD1
 };
 
-static inline void mxc_init_imx_uart(void)
+static inline void __init mxc_init_imx_uart(void)
 {
 	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
 			"uart-0");
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	imx31_add_imx_uart0(&uart_pdata);
 }
 
 static struct resource dnet_resources[] = {
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
index 2e50951..827fd3c 100644
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-mx3/mx31lilly-db.c
@@ -32,13 +32,13 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
 #include <mach/mmc.h>
 #include <mach/mx3fb.h>
 #include <mach/ipu.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -92,7 +92,7 @@ static unsigned int lilly_db_board_pins[] __initdata = {
 };
 
 /* UART */
-static struct imxuart_platform_data uart_pdata __initdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -213,9 +213,9 @@ void __init mx31lilly_db_init(void)
 	mxc_iomux_setup_multiple_pins(lilly_db_board_pins,
 					ARRAY_SIZE(lilly_db_board_pins),
 					"development board pins");
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
-	mxc_register_device(&mxc_uart_device1, &uart_pdata);
-	mxc_register_device(&mxc_uart_device2, &uart_pdata);
+	imx31_add_imx_uart0(&uart_pdata);
+	imx31_add_imx_uart1(&uart_pdata);
+	imx31_add_imx_uart2(&uart_pdata);
 	mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
 	mx31lilly_init_fb();
 }
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index 3786e29..7b0e74e 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -33,7 +33,6 @@
 
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lite.h>
 #include <mach/mmc.h>
@@ -72,7 +71,7 @@ static unsigned int litekit_db_board_pins[] __initdata = {
 };
 
 /* UART */
-static struct imxuart_platform_data uart_pdata __initdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -197,7 +196,7 @@ void __init mx31lite_db_init(void)
 	mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
 					ARRAY_SIZE(litekit_db_board_pins),
 					"development board pins");
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	imx31_add_imx_uart0(&uart_pdata);
 	mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
 	imx31_add_spi_imx0(&spi0_pdata);
 	platform_device_register(&litekit_led_device);
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index 44473b1..fc395a7 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -23,13 +23,13 @@
 #include <linux/usb/otg.h>
 
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/hardware.h>
 #include <mach/mmc.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int devboard_pins[] = {
@@ -52,7 +52,7 @@ static unsigned int devboard_pins[] = {
 	MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -226,7 +226,7 @@ void __init mx31moboard_devboard_init(void)
 	mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins),
 		"devboard");
 
-	mxc_register_device(&mxc_uart_device1, &uart_pdata);
+	imx31_add_imx_uart1(&uart_pdata);
 
 	mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
 
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index f45a500..40c3e75 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -26,7 +26,6 @@
 
 #include <mach/common.h>
 #include <mach/hardware.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31moboard.h>
 #include <mach/mxc_ehci.h>
@@ -34,6 +33,7 @@
 
 #include <media/soc_camera.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 static unsigned int smartbot_pins[] = {
@@ -55,7 +55,7 @@ static unsigned int smartbot_pins[] = {
 	MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -179,8 +179,7 @@ void __init mx31moboard_smartbot_init(int board)
 	mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins),
 		"smartbot");
 
-	mxc_register_device(&mxc_uart_device1, &uart_pdata);
-
+	imx31_add_imx_uart1(&uart_pdata);
 
 	switch (board) {
 	case MX31SMARTBOT:
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:40 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:40 +0200
Subject: [PATCH 44/61] ARM: imx: dynamically register imx-i2c devices (imx25)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-45-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx25/devices-imx25.h    |    7 ++++
 arch/arm/mach-mx25/devices.c          |   57 ---------------------------------
 arch/arm/mach-mx25/devices.h          |    3 --
 arch/arm/plat-mxc/include/mach/mx25.h |   14 ++++++--
 4 files changed, 17 insertions(+), 64 deletions(-)

diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
index f8d4ee0..6464be4 100644
--- a/arch/arm/mach-mx25/devices-imx25.h
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -9,5 +9,12 @@
 #include <mach/mx25.h>
 #include <mach/devices-common.h>
 
+#define imx25_add_imx_i2c0(pdata)	\
+	imx_add_imx_i2c(0, MX25_I2C1_BASE_ADDR, SZ_16K, MX25_INT_I2C1, pdata)
+#define imx25_add_imx_i2c1(pdata)	\
+	imx_add_imx_i2c(1, MX25_I2C2_BASE_ADDR, SZ_16K, MX25_INT_I2C2, pdata)
+#define imx25_add_imx_i2c2(pdata)	\
+	imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata)
+
 #define imx25_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index e1c3cd1..1af852a 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -333,63 +333,6 @@ struct platform_device mxc_pwm_device3 = {
 	.resource = mxc_pwm_resources3,
 };
 
-static struct resource mxc_i2c_1_resources[] = {
-	{
-		.start	= 0x43f80000,
-		.end	= 0x43f83fff,
-		.flags	= IORESOURCE_MEM,
-	}, {
-		.start	= 3,
-		.end	= 3,
-		.flags	= IORESOURCE_IRQ,
-	}
-};
-
-struct platform_device mxc_i2c_device0 = {
-	.name = "imx-i2c",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
-	.resource = mxc_i2c_1_resources,
-};
-
-static struct resource mxc_i2c_2_resources[] = {
-	{
-		.start	= 0x43f98000,
-		.end	= 0x43f9bfff,
-		.flags	= IORESOURCE_MEM,
-	}, {
-		.start	= 4,
-		.end	= 4,
-		.flags	= IORESOURCE_IRQ,
-	}
-};
-
-struct platform_device mxc_i2c_device1 = {
-	.name = "imx-i2c",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
-	.resource = mxc_i2c_2_resources,
-};
-
-static struct resource mxc_i2c_3_resources[] = {
-	{
-		.start	= 0x43f84000,
-		.end	= 0x43f87fff,
-		.flags	= IORESOURCE_MEM,
-	}, {
-		.start	= 10,
-		.end	= 10,
-		.flags	= IORESOURCE_IRQ,
-	}
-};
-
-struct platform_device mxc_i2c_device2 = {
-	.name = "imx-i2c",
-	.id = 2,
-	.num_resources = ARRAY_SIZE(mxc_i2c_3_resources),
-	.resource = mxc_i2c_3_resources,
-};
-
 static struct mxc_gpio_port imx_gpio_ports[] = {
 	{
 		.chip.label = "gpio-0",
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index f212c93..f277514 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -14,9 +14,6 @@ extern struct platform_device mxc_pwm_device1;
 extern struct platform_device mxc_pwm_device2;
 extern struct platform_device mxc_pwm_device3;
 extern struct platform_device mxc_keypad_device;
-extern struct platform_device mxc_i2c_device0;
-extern struct platform_device mxc_i2c_device1;
-extern struct platform_device mxc_i2c_device2;
 extern struct platform_device mx25_fec_device;
 extern struct platform_device mx25_rtc_device;
 extern struct platform_device mx25_fb_device;
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 4eb6e33..1ebf33f 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -11,6 +11,9 @@
 #define MX25_AVIC_BASE_ADDR_VIRT	0xfc400000
 #define MX25_AVIC_SIZE			SZ_1M
 
+#define MX25_I2C1_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0x80000)
+#define MX25_I2C3_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0x84000)
+#define MX25_I2C2_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0x98000)
 #define MX25_IOMUXC_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0xac000)
 
 #define MX25_CRM_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0x80000)
@@ -35,10 +38,13 @@
 #define MX25_DRYICE_BASE_ADDR		0x53ffc000
 #define MX25_LCDC_BASE_ADDR		0x53fbc000
 
-#define MX25_INT_DRYICE	25
-#define MX25_INT_FEC	57
-#define MX25_INT_NANDFC	33
-#define MX25_INT_LCDC	39
+#define MX25_INT_I2C1		3
+#define MX25_INT_I2C2		4
+#define MX25_INT_I2C3		10
+#define MX25_INT_DRYICE		25
+#define MX25_INT_FEC		57
+#define MX25_INT_NANDFC		33
+#define MX25_INT_LCDC		39
 
 #if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
 #define UART1_BASE_ADDR			MX25_UART1_BASE_ADDR
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:01 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:01 +0200
Subject: [PATCH 05/61] ARM: mx2/mx27_3ds: document alternative names and
	remove empty header
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-6-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx2/mach-mx27_3ds.c              |    7 ++++++-
 arch/arm/plat-mxc/include/mach/board-mx27pdk.h |   14 --------------
 2 files changed, 6 insertions(+), 15 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx27pdk.h

diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-mx2/mach-mx27_3ds.c
index b2f4e0d..a45df59 100644
--- a/arch/arm/mach-mx2/mach-mx27_3ds.c
+++ b/arch/arm/mach-mx2/mach-mx27_3ds.c
@@ -18,6 +18,12 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
+/*
+ * This machine is known as:
+ *  - i.MX27 3-Stack Development System
+ *  - i.MX27 Platform Development Kit (i.MX27 PDK)
+ */
+
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <asm/mach-types.h>
@@ -27,7 +33,6 @@
 #include <mach/common.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
-#include <mach/board-mx27pdk.h>
 
 #include "devices.h"
 
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
deleted file mode 100644
index fec1bcf..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
-#define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:26 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:26 +0200
Subject: [PATCH 30/61] ARM: imx: remove paragraphs with old address of the FSF
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-31-git-send-email-u.kleine-koenig@pengutronix.de>

As the kernel contains a copy of the GPL anyhow just get rid of the address
specification instead of fixing it.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/mach-imx27lite.c |    4 ----
 arch/arm/mach-imx/mach-mx21ads.c   |    4 ----
 arch/arm/mach-imx/mach-mx27_3ds.c  |    4 ----
 arch/arm/mach-imx/mach-mx27ads.c   |    4 ----
 arch/arm/mach-imx/mach-mxt_td60.c  |    4 ----
 arch/arm/mach-imx/mm-imx1.c        |    5 -----
 6 files changed, 0 insertions(+), 25 deletions(-)

diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 27da9a1..6df5c7d 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index e51f6f8..39c645a 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index c9af5f1..da3eeff 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 /*
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 771a63f..186b93a 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 4f4200b..0e5ddba 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/platform_device.h>
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 396d0a5..117ebf6 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -14,11 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
  */
 #include <linux/kernel.h>
 #include <linux/init.h>
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:53 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:53 +0200
Subject: [PATCH 57/61] ARM: imx: dynamically register imx-uart devices (imx25)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-58-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx25/Kconfig            |    1 +
 arch/arm/mach-mx25/devices-imx25.h    |   11 ++++
 arch/arm/mach-mx25/devices.c          |   95 ---------------------------------
 arch/arm/mach-mx25/devices.h          |    5 --
 arch/arm/mach-mx25/mach-mx25_3ds.c    |    5 +-
 arch/arm/plat-mxc/include/mach/mx25.h |    8 +++
 6 files changed, 22 insertions(+), 103 deletions(-)

diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index 3c4f1ee..febf841 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -4,6 +4,7 @@ comment "MX25 platforms:"
 
 config MACH_MX25_3DS
 	bool "Support MX25PDK (3DS) Platform"
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MXC_NAND
 
 endif
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
index 33a834e..2025cb9 100644
--- a/arch/arm/mach-mx25/devices-imx25.h
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -16,6 +16,17 @@
 #define imx25_add_imx_i2c2(pdata)	\
 	imx_add_imx_i2c(2, MX25_I2C3_BASE_ADDR, SZ_16K, MX25_INT_I2C3, pdata)
 
+#define imx25_add_imx_uart0(pdata)	\
+	imx_add_imx_uart_1irq(0, MX25_UART1_BASE_ADDR, SZ_16K, MX25_INT_UART1, pdata)
+#define imx25_add_imx_uart1(pdata)	\
+	imx_add_imx_uart_1irq(1, MX25_UART2_BASE_ADDR, SZ_16K, MX25_INT_UART2, pdata)
+#define imx25_add_imx_uart2(pdata)	\
+	imx_add_imx_uart_1irq(2, MX25_UART3_BASE_ADDR, SZ_16K, MX25_INT_UART3, pdata)
+#define imx25_add_imx_uart3(pdata)	\
+	imx_add_imx_uart_1irq(3, MX25_UART4_BASE_ADDR, SZ_16K, MX25_INT_UART4, pdata)
+#define imx25_add_imx_uart4(pdata)	\
+	imx_add_imx_uart_1irq(4, MX25_UART5_BASE_ADDR, SZ_16K, MX25_INT_UART5, pdata)
+
 #define imx25_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
 
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index c267087..6f98d23 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -22,101 +22,6 @@
 #include <mach/mx25.h>
 #include <mach/irqs.h>
 
-static struct resource uart0[] = {
-	{
-		.start = 0x43f90000,
-		.end = 0x43f93fff,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = 45,
-		.end = 45,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device0 = {
-	.name = "imx-uart",
-	.id = 0,
-	.resource = uart0,
-	.num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
-	{
-		.start = 0x43f94000,
-		.end = 0x43f97fff,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = 32,
-		.end = 32,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device1 = {
-	.name = "imx-uart",
-	.id = 1,
-	.resource = uart1,
-	.num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
-	{
-		.start = 0x5000c000,
-		.end = 0x5000ffff,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = 18,
-		.end = 18,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device2 = {
-	.name = "imx-uart",
-	.id = 2,
-	.resource = uart2,
-	.num_resources = ARRAY_SIZE(uart2),
-};
-
-static struct resource uart3[] = {
-	{
-		.start = 0x50008000,
-		.end = 0x5000bfff,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = 5,
-		.end = 5,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device3 = {
-	.name = "imx-uart",
-	.id = 3,
-	.resource = uart3,
-	.num_resources = ARRAY_SIZE(uart3),
-};
-
-static struct resource uart4[] = {
-	{
-		.start = 0x5002c000,
-		.end = 0x5002ffff,
-		.flags = IORESOURCE_MEM,
-	}, {
-		.start = 40,
-		.end = 40,
-		.flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_uart_device4 = {
-	.name = "imx-uart",
-	.id = 4,
-	.resource = uart4,
-	.num_resources = ARRAY_SIZE(uart4),
-};
-
 #define MX25_OTG_BASE_ADDR 0x53FF4000
 
 static u64 otg_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index 1f31cbc..31d22e1 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -1,8 +1,3 @@
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_otg;
 extern struct platform_device otg_udc_device;
 extern struct platform_device mxc_usbh2;
diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-mx25/mach-mx25_3ds.c
index e1e9886..978ad00 100644
--- a/arch/arm/mach-mx25/mach-mx25_3ds.c
+++ b/arch/arm/mach-mx25/mach-mx25_3ds.c
@@ -38,7 +38,6 @@
 #include <asm/memory.h>
 #include <asm/mach/map.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/mx25.h>
 #include <mach/imxfb.h>
 #include <mach/iomux-mx25.h>
@@ -46,7 +45,7 @@
 #include "devices-imx25.h"
 #include "devices.h"
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -150,7 +149,7 @@ static void __init mx25pdk_init(void)
 	mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
 			ARRAY_SIZE(mx25pdk_pads));
 
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	imx25_add_imx_uart0(&uart_pdata);
 	mxc_register_device(&mxc_usbh2, NULL);
 	imx25_add_mxc_nand(&mx25pdk_nand_board_info);
 	mxc_register_device(&mx25_rtc_device, NULL);
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 16ac6b6..ca95b1e 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -33,6 +33,9 @@
 
 #define MX25_UART1_BASE_ADDR		0x43f90000
 #define MX25_UART2_BASE_ADDR		0x43f94000
+#define MX25_UART3_BASE_ADDR		0x5000c000
+#define MX25_UART4_BASE_ADDR		0x50008000
+#define MX25_UART5_BASE_ADDR		0x5002c000
 
 #define MX25_CSPI3_BASE_ADDR		0x50004000
 #define MX25_CSPI2_BASE_ADDR		0x50010000
@@ -44,12 +47,17 @@
 #define MX25_INT_CSPI3		0
 #define MX25_INT_I2C1		3
 #define MX25_INT_I2C2		4
+#define MX25_INT_UART4		5
 #define MX25_INT_I2C3		10
 #define MX25_INT_CSPI2		13
 #define MX25_INT_CSPI1		14
+#define MX25_INT_UART3		18
 #define MX25_INT_DRYICE		25
+#define MX25_INT_UART2		32
 #define MX25_INT_NANDFC		33
 #define MX25_INT_LCDC		39
+#define MX25_INT_UART5		40
+#define MX25_INT_UART1		45
 #define MX25_INT_FEC		57
 
 #if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:02 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:02 +0200
Subject: [PATCH 06/61] ARM: imx: remove empty and unused board headers
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-7-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx2/mach-imx27lite.c                 |    1 -
 arch/arm/mach-mx3/mach-armadillo5x0.c              |    1 -
 arch/arm/mach-mx3/mach-pcm037.c                    |    1 -
 .../arm/plat-mxc/include/mach/board-armadillo5x0.h |   15 -------------
 arch/arm/plat-mxc/include/mach/board-mx27lite.h    |   14 ------------
 arch/arm/plat-mxc/include/mach/board-mx35pdk.h     |   22 --------------------
 arch/arm/plat-mxc/include/mach/board-pcm037.h      |   22 --------------------
 arch/arm/plat-mxc/include/mach/board-pcm043.h      |   22 --------------------
 8 files changed, 0 insertions(+), 98 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx27lite.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx35pdk.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-pcm037.h
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-pcm043.h

diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-mx2/mach-imx27lite.c
index b5710bf..fd1dddb 100644
--- a/arch/arm/mach-mx2/mach-imx27lite.c
+++ b/arch/arm/mach-mx2/mach-imx27lite.c
@@ -28,7 +28,6 @@
 #include <mach/common.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
-#include <mach/board-mx27lite.h>
 
 #include "devices.h"
 
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 5f72ec9..2a8de89 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -50,7 +50,6 @@
 #include <mach/common.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
-#include <mach/board-armadillo5x0.h>
 #include <mach/mmc.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index cce4106..8419370 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -43,7 +43,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/board-pcm037.h>
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/i2c.h>
diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
deleted file mode 100644
index 0376c13..0000000
--- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright 2009 Alberto Panizzo <maramaopercheseimorto at gmail.com>.
- * All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
-#define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
-
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
deleted file mode 100644
index ea87551..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
-#define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
deleted file mode 100644
index 383f1c0..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- *  Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
-#define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
-
-#endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h
deleted file mode 100644
index 1341170..0000000
--- a/arch/arm/plat-mxc/include/mach/board-pcm037.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- *  Copyright (C) 2008 Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
-#define __ASM_ARCH_MXC_BOARD_PCM037_H__
-
-#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/plat-mxc/include/mach/board-pcm043.h
deleted file mode 100644
index 1ac4e16..0000000
--- a/arch/arm/plat-mxc/include/mach/board-pcm043.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- *  Copyright (C) 2008 Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__
-#define __ASM_ARCH_MXC_BOARD_PCM043_H__
-
-#endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:04 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:04 +0200
Subject: [PATCH 08/61] ARM: mx2/mx21ads: fold board header in its only user
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-9-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx2/mach-mx21ads.c               |   36 ++++++++++++++++-
 arch/arm/plat-mxc/include/mach/board-mx21ads.h |   52 ------------------------
 2 files changed, 35 insertions(+), 53 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-mx21ads.h

diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-mx2/mach-mx21ads.c
index 113e58d..99f2492 100644
--- a/arch/arm/mach-mx2/mach-mx21ads.c
+++ b/arch/arm/mach-mx2/mach-mx21ads.c
@@ -33,10 +33,44 @@
 #include <mach/iomux-mx21.h>
 #include <mach/mxc_nand.h>
 #include <mach/mmc.h>
-#include <mach/board-mx21ads.h>
 
 #include "devices.h"
 
+/*
+ * Memory-mapped I/O on MX21ADS base board
+ */
+#define MX21ADS_MMIO_BASE_ADDR   0xf5000000
+#define MX21ADS_MMIO_SIZE        SZ_16M
+
+#define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
+		(MX21ADS_MMIO_BASE_ADDR + (offset))
+
+#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
+#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
+#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
+#define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
+#define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
+
+/* MX21ADS_IO_REG bit definitions */
+#define MX21ADS_IO_SD_WP        0x0001 /* read */
+#define MX21ADS_IO_TP6          0x0001 /* write */
+#define MX21ADS_IO_SW_SEL       0x0002 /* read */
+#define MX21ADS_IO_TP7          0x0002 /* write */
+#define MX21ADS_IO_RESET_E_UART 0x0004
+#define MX21ADS_IO_RESET_BASE   0x0008
+#define MX21ADS_IO_CSI_CTL2     0x0010
+#define MX21ADS_IO_CSI_CTL1     0x0020
+#define MX21ADS_IO_CSI_CTL0     0x0040
+#define MX21ADS_IO_UART1_EN     0x0080
+#define MX21ADS_IO_UART4_EN     0x0100
+#define MX21ADS_IO_LCDON        0x0200
+#define MX21ADS_IO_IRDA_EN      0x0400
+#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
+#define MX21ADS_IO_IRDA_MD0_B   0x1000
+#define MX21ADS_IO_IRDA_MD1     0x2000
+#define MX21ADS_IO_LED4_ON      0x4000
+#define MX21ADS_IO_LED3_ON      0x8000
+
 static unsigned int mx21ads_pins[] = {
 
 	/* CS8900A */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
deleted file mode 100644
index 0cf4fa2..0000000
--- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_MX21ADS_H__
-#define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
-
-/*
- * Memory-mapped I/O on MX21ADS base board
- */
-#define MX21ADS_MMIO_BASE_ADDR   0xF5000000
-#define MX21ADS_MMIO_SIZE        SZ_16M
-
-#define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
-		(MX21ADS_MMIO_BASE_ADDR + (offset))
-
-#define MX21ADS_CS8900A_IRQ         IRQ_GPIOE(11)
-#define MX21ADS_CS8900A_IOBASE_REG  MX21ADS_REG_ADDR(0x000000)
-#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
-#define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
-#define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
-
-/* MX21ADS_IO_REG bit definitions */
-#define MX21ADS_IO_SD_WP        0x0001 /* read */
-#define MX21ADS_IO_TP6          0x0001 /* write */
-#define MX21ADS_IO_SW_SEL       0x0002 /* read */
-#define MX21ADS_IO_TP7          0x0002 /* write */
-#define MX21ADS_IO_RESET_E_UART 0x0004
-#define MX21ADS_IO_RESET_BASE   0x0008
-#define MX21ADS_IO_CSI_CTL2     0x0010
-#define MX21ADS_IO_CSI_CTL1     0x0020
-#define MX21ADS_IO_CSI_CTL0     0x0040
-#define MX21ADS_IO_UART1_EN     0x0080
-#define MX21ADS_IO_UART4_EN     0x0100
-#define MX21ADS_IO_LCDON        0x0200
-#define MX21ADS_IO_IRDA_EN      0x0400
-#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
-#define MX21ADS_IO_IRDA_MD0_B   0x1000
-#define MX21ADS_IO_IRDA_MD1     0x2000
-#define MX21ADS_IO_LED4_ON      0x4000
-#define MX21ADS_IO_LED3_ON      0x8000
-
-#endif				/* __ASM_ARCH_MXC_BOARD_MX21ADS_H__ */
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:52 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:52 +0200
Subject: [PATCH 56/61] ARM: imx: dynamically register imx-uart devices (imx21)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-57-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig         |    1 +
 arch/arm/mach-imx/devices-imx21.h |    9 +++++++++
 arch/arm/mach-imx/devices.c       |    3 +--
 arch/arm/mach-imx/devices.h       |    2 +-
 arch/arm/mach-imx/mach-mx21ads.c  |   12 +++++-------
 5 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 445ce10..0fa8acc 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -71,6 +71,7 @@ comment "MX21 platforms:"
 
 config MACH_MX21ADS
 	bool "MX21ADS platform"
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for MX21ADS platform. This includes specific
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index de80ccd..42788e9 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -12,6 +12,15 @@
 #define imx21_add_i2c_imx(pdata)	\
 	imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata)
 
+#define imx21_add_imx_uart0(pdata)	\
+	imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata)
+#define imx21_add_imx_uart1(pdata)	\
+	imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata)
+#define imx21_add_imx_uart2(pdata)	\
+	imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata)
+#define imx21_add_imx_uart3(pdata)	\
+	imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata)
+
 #define imx21_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
 
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index b4bf8fc..9ea2ef1 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -483,6 +483,7 @@ struct platform_device mxc_usbh2 = {
 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 
+#ifdef CONFIG_MACH_MX27
 #define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq)			\
 	static struct resource imx2x_uart_resources ## n[] = {		\
 		{							\
@@ -507,8 +508,6 @@ DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
 DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
 DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
 DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
-
-#ifdef CONFIG_MACH_MX27
 DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
 DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
 #endif
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index e56efbc..13790fb 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -14,11 +14,11 @@ extern struct platform_device mxc_gpt4;
 extern struct platform_device mxc_gpt5;
 #endif
 extern struct platform_device mxc_wdt;
+#ifdef CONFIG_MACH_MX27
 extern struct platform_device imx2x_uart_device0;
 extern struct platform_device imx2x_uart_device1;
 extern struct platform_device imx2x_uart_device2;
 extern struct platform_device imx2x_uart_device3;
-#ifdef CONFIG_MACH_MX27
 extern struct platform_device imx2x_uart_device4;
 extern struct platform_device imx2x_uart_device5;
 #endif
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index fde2a57..96d7f81 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -24,7 +24,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
-#include <mach/imx-uart.h>
 #include <mach/imxfb.h>
 #include <mach/iomux-mx21.h>
 #include <mach/mxc_nand.h>
@@ -164,14 +163,13 @@ static struct platform_device mx21ads_nor_mtd_device = {
 	.resource = &mx21ads_flash_resource,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata_rts __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
-static struct imxuart_platform_data uart_norts_pdata = {
+static const struct imxuart_platform_data uart_pdata_norts __initconst = {
 };
 
-
 static int mx21ads_fb_init(struct platform_device *pdev)
 {
 	u16 tmp;
@@ -295,9 +293,9 @@ static void __init mx21ads_board_init(void)
 	mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
 			"mx21ads");
 
-	mxc_register_device(&imx2x_uart_device0, &uart_pdata);
-	mxc_register_device(&imx2x_uart_device2, &uart_norts_pdata);
-	mxc_register_device(&imx2x_uart_device3, &uart_pdata);
+	imx21_add_imx_uart0(&uart_pdata_rts);
+	imx21_add_imx_uart2(&uart_pdata_norts);
+	imx21_add_imx_uart3(&uart_pdata_rts);
 	mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
 	mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
 	imx21_add_mxc_nand(&mx21ads_nand_board_info);
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:36 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:36 +0200
Subject: [PATCH 40/61] ARM: imx: Change the way nand devices are registered
	(imx35)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-41-git-send-email-u.kleine-koenig@pengutronix.de>

Make use of new mechanism to register a nand device.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/Kconfig         |    1 +
 arch/arm/mach-mx3/devices-imx35.h |   13 +++++++++++++
 arch/arm/mach-mx3/devices.c       |   23 -----------------------
 arch/arm/mach-mx3/devices.h       |    3 ---
 arch/arm/mach-mx3/mach-pcm043.c   |    7 ++++---
 5 files changed, 18 insertions(+), 29 deletions(-)
 create mode 100644 arch/arm/mach-mx3/devices-imx35.h

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index cb9368f..5611b23 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -100,6 +100,7 @@ config MACH_QONG
 config MACH_PCM043
 	bool "Support Phytec pcm043 (i.MX35) platforms"
 	select ARCH_MX35
+	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
 	  Include support for Phytec pcm043 platform. This includes
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
new file mode 100644
index 0000000..69dac76
--- /dev/null
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx35.h>
+#include <mach/devices-common.h>
+
+#define imx35_add_mxc_nand(pdata)	\
+	imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index baa4bd1..c8db849 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -167,27 +167,6 @@ struct platform_device mxc_w1_master_device = {
 	.resource = mxc_w1_master_resources,
 };
 
-#if defined(CONFIG_ARCH_MX35)
-static struct resource mxc_nand_resources[] = {
-	{
-		.start	= 0, /* runtime dependent */
-		.end	= 0,
-		.flags	= IORESOURCE_MEM,
-	}, {
-		.start	= MXC_INT_NANDFC,
-		.end	= MXC_INT_NANDFC,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_nand_device = {
-	.name = "mxc_nand",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxc_nand_resources),
-	.resource = mxc_nand_resources,
-};
-#endif
-
 static struct resource mxc_i2c0_resources[] = {
 	{
 		.start = I2C_BASE_ADDR,
@@ -639,8 +618,6 @@ static int __init mx3_devices_init(void)
 #endif
 #if defined(CONFIG_ARCH_MX35)
 	if (cpu_is_mx35()) {
-		mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
-		mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff;
 		otg_resources[0].start = MX35_OTG_BASE_ADDR;
 		otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
 		otg_resources[1].start = MXC_INT_USBOTG;
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 6bb71d3..4a224e6 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -5,9 +5,6 @@ extern struct platform_device mxc_uart_device2;
 extern struct platform_device mxc_uart_device3;
 extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_w1_master_device;
-#if defined(CONFIG_ARCH_MX35)
-extern struct platform_device mxc_nand_device;
-#endif
 extern struct platform_device mxc_i2c_device0;
 extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_i2c_device2;
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 100bb77..58de305 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -43,12 +43,12 @@
 #include <mach/iomux-mx35.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 #include <mach/audmux.h>
 #include <mach/ssi.h>
 
+#include "devices-imx35.h"
 #include "devices.h"
 
 static const struct fb_videomode fb_modedb[] = {
@@ -300,7 +300,8 @@ static struct imx_ssi_platform_data pcm043_ssi_pdata = {
 	.flags = IMX_SSI_USE_AC97,
 };
 
-static struct mxc_nand_platform_data pcm037_nand_board_info = {
+static const struct mxc_nand_platform_data
+pcm037_nand_board_info __initconst = {
 	.width = 1,
 	.hw_ecc = 1,
 };
@@ -358,7 +359,7 @@ static void __init mxc_board_init(void)
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	mxc_register_device(&mxc_uart_device0, &uart_pdata);
-	mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
+	imx35_add_mxc_nand(&pcm037_nand_board_info);
 	mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
 
 	mxc_register_device(&mxc_uart_device1, &uart_pdata);
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:19 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:19 +0200
Subject: [PATCH 23/61] ARM: imx: move mx1 support to mach-imx
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-24-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/Makefile                       |    2 +-
 arch/arm/mach-imx/Kconfig               |   19 +
 arch/arm/mach-imx/Makefile              |    8 +
 arch/arm/mach-imx/Makefile.boot         |    4 +
 arch/arm/mach-imx/clock-imx1.c          |  636 +++++++++++++++++++++++++++++++
 arch/arm/mach-imx/devices.c             |  197 ++++++++++
 arch/arm/mach-imx/devices.h             |   12 +
 arch/arm/mach-imx/mach-mx1ads.c         |  165 ++++++++
 arch/arm/mach-imx/mach-scb9328.c        |  157 ++++++++
 arch/arm/mach-imx/mm-imx1.c             |   55 +++
 arch/arm/mach-imx/mx1-camera-fiq-ksym.c |   18 +
 arch/arm/mach-imx/mx1-camera-fiq.S      |   35 ++
 arch/arm/mach-mx1/Kconfig               |   19 -
 arch/arm/mach-mx1/Makefile              |   14 -
 arch/arm/mach-mx1/Makefile.boot         |    4 -
 arch/arm/mach-mx1/clock.c               |  636 -------------------------------
 arch/arm/mach-mx1/devices.c             |  220 -----------
 arch/arm/mach-mx1/devices.h             |    7 -
 arch/arm/mach-mx1/generic.c             |   55 ---
 arch/arm/mach-mx1/ksym_mx1.c            |   18 -
 arch/arm/mach-mx1/mach-mx1ads.c         |  165 --------
 arch/arm/mach-mx1/mach-scb9328.c        |  157 --------
 arch/arm/mach-mx1/mx1_camera_fiq.S      |   35 --
 arch/arm/plat-mxc/Kconfig               |    1 -
 24 files changed, 1307 insertions(+), 1332 deletions(-)
 create mode 100644 arch/arm/mach-imx/clock-imx1.c
 create mode 100644 arch/arm/mach-imx/mach-mx1ads.c
 create mode 100644 arch/arm/mach-imx/mach-scb9328.c
 create mode 100644 arch/arm/mach-imx/mm-imx1.c
 create mode 100644 arch/arm/mach-imx/mx1-camera-fiq-ksym.c
 create mode 100644 arch/arm/mach-imx/mx1-camera-fiq.S
 delete mode 100644 arch/arm/mach-mx1/Kconfig
 delete mode 100644 arch/arm/mach-mx1/Makefile
 delete mode 100644 arch/arm/mach-mx1/Makefile.boot
 delete mode 100644 arch/arm/mach-mx1/clock.c
 delete mode 100644 arch/arm/mach-mx1/devices.c
 delete mode 100644 arch/arm/mach-mx1/devices.h
 delete mode 100644 arch/arm/mach-mx1/generic.c
 delete mode 100644 arch/arm/mach-mx1/ksym_mx1.c
 delete mode 100644 arch/arm/mach-mx1/mach-mx1ads.c
 delete mode 100644 arch/arm/mach-mx1/mach-scb9328.c
 delete mode 100644 arch/arm/mach-mx1/mx1_camera_fiq.S

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c60d604..ad81ece 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -145,7 +145,7 @@ machine-$(CONFIG_ARCH_LOKI) 		:= loki
 machine-$(CONFIG_ARCH_MMP)		:= mmp
 machine-$(CONFIG_ARCH_MSM)		:= msm
 machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
-machine-$(CONFIG_ARCH_MX1)		:= mx1
+machine-$(CONFIG_ARCH_MX1)		:= imx
 machine-$(CONFIG_ARCH_MX2)		:= imx
 machine-$(CONFIG_ARCH_MX25)		:= mx25
 machine-$(CONFIG_ARCH_MX3)		:= mx3
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 742fd4e..c6eddd7 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,3 +1,22 @@
+if ARCH_MX1
+
+comment "MX1 platforms:"
+config MACH_MXLADS
+	bool
+
+config ARCH_MX1ADS
+	bool "MX1ADS platform"
+	select MACH_MXLADS
+	help
+	  Say Y here if you are using Motorola MX1ADS/MXLADS boards
+
+config MACH_SCB9328
+	bool "Synertronixx scb9328"
+	help
+	  Say Y here if you are using a Synertronixx scb9328 board
+
+endif
+
 if ARCH_MX2
 
 choice
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 9d57ba6..e56a119 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -6,12 +6,20 @@
 
 obj-y	:=  devices.o
 
+obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
 obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
 
 obj-$(CONFIG_MACH_MX27) += cpu-imx27.o
 obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
 
+# Support for CMOS sensor interface
+obj-$(CONFIG_MX1_VIDEO)	+= mx1-camera-fiq.o mx1-camera-fiq-ksym.o
+
+obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
+obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
+
 obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
+
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
 obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index e867398..7988a85 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -1,3 +1,7 @@
+zreladdr-$(CONFIG_ARCH_MX1)	:= 0x08008000
+params_phys-$(CONFIG_ARCH_MX1)	:= 0x08000100
+initrd_phys-$(CONFIG_ARCH_MX1)	:= 0x08800000
+
 zreladdr-$(CONFIG_MACH_MX21)	:= 0xC0008000
 params_phys-$(CONFIG_MACH_MX21)	:= 0xC0000100
 initrd_phys-$(CONFIG_MACH_MX21)	:= 0xC0800000
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
new file mode 100644
index 0000000..c05096c
--- /dev/null
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -0,0 +1,636 @@
+/*
+ *  Copyright (C) 2008 Sascha Hauer <s.hauer at pengutronix.de>, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/math64.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <asm/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#define IO_ADDR_CCM(off)	(MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
+
+/* CCM register addresses */
+#define CCM_CSCR	IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0	IO_ADDR_CCM(0x4)
+#define CCM_SPCTL0	IO_ADDR_CCM(0xc)
+#define CCM_PCDR	IO_ADDR_CCM(0x20)
+
+#define CCM_CSCR_CLKO_OFFSET	29
+#define CCM_CSCR_CLKO_MASK	(0x7 << 29)
+#define CCM_CSCR_USB_OFFSET	26
+#define CCM_CSCR_USB_MASK	(0x7 << 26)
+#define CCM_CSCR_OSC_EN_SHIFT	17
+#define CCM_CSCR_SYSTEM_SEL	(1 << 16)
+#define CCM_CSCR_BCLK_OFFSET	10
+#define CCM_CSCR_BCLK_MASK	(0xf << 10)
+#define CCM_CSCR_PRESC		(1 << 15)
+
+#define CCM_PCDR_PCLK3_OFFSET	16
+#define CCM_PCDR_PCLK3_MASK	(0x7f << 16)
+#define CCM_PCDR_PCLK2_OFFSET	4
+#define CCM_PCDR_PCLK2_MASK	(0xf << 4)
+#define CCM_PCDR_PCLK1_OFFSET	0
+#define CCM_PCDR_PCLK1_MASK	0xf
+
+#define IO_ADDR_SCM(off)	(MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
+
+/* SCM register addresses */
+#define SCM_GCCR	IO_ADDR_SCM(0xc)
+
+#define SCM_GCCR_DMA_CLK_EN_OFFSET	3
+#define SCM_GCCR_CSI_CLK_EN_OFFSET	2
+#define SCM_GCCR_MMA_CLK_EN_OFFSET	1
+#define SCM_GCCR_USBD_CLK_EN_OFFSET	0
+
+static int _clk_enable(struct clk *clk)
+{
+	unsigned int reg;
+
+	reg = __raw_readl(clk->enable_reg);
+	reg |= 1 << clk->enable_shift;
+	__raw_writel(reg, clk->enable_reg);
+
+	return 0;
+}
+
+static void _clk_disable(struct clk *clk)
+{
+	unsigned int reg;
+
+	reg = __raw_readl(clk->enable_reg);
+	reg &= ~(1 << clk->enable_shift);
+	__raw_writel(reg, clk->enable_reg);
+}
+
+static int _clk_can_use_parent(const struct clk *clk_arr[], unsigned int size,
+			       struct clk *parent)
+{
+	int i;
+
+	for (i = 0; i < size; i++)
+		if (parent == clk_arr[i])
+			return i;
+
+	return -EINVAL;
+}
+
+static unsigned long
+_clk_simple_round_rate(struct clk *clk, unsigned long rate, unsigned int limit)
+{
+	int div;
+	unsigned long parent_rate;
+
+	parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+	if (parent_rate % rate)
+		div++;
+
+	if (div > limit)
+		div = limit;
+
+	return parent_rate / div;
+}
+
+static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
+{
+	return clk->parent->round_rate(clk->parent, rate);
+}
+
+static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
+{
+	return clk->parent->set_rate(clk->parent, rate);
+}
+
+static unsigned long clk16m_get_rate(struct clk *clk)
+{
+	return 16000000;
+}
+
+static struct clk clk16m = {
+	.get_rate = clk16m_get_rate,
+	.enable = _clk_enable,
+	.enable_reg = CCM_CSCR,
+	.enable_shift = CCM_CSCR_OSC_EN_SHIFT,
+	.disable = _clk_disable,
+};
+
+/* in Hz */
+static unsigned long clk32_rate;
+
+static unsigned long clk32_get_rate(struct clk *clk)
+{
+	return clk32_rate;
+}
+
+static struct clk clk32 = {
+	.get_rate = clk32_get_rate,
+};
+
+static unsigned long clk32_premult_get_rate(struct clk *clk)
+{
+	return clk_get_rate(clk->parent) * 512;
+}
+
+static struct clk clk32_premult = {
+	.parent = &clk32,
+	.get_rate = clk32_premult_get_rate,
+};
+
+static const struct clk *prem_clk_clocks[] = {
+	&clk32_premult,
+	&clk16m,
+};
+
+static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+	int i;
+	unsigned int reg = __raw_readl(CCM_CSCR);
+
+	i = _clk_can_use_parent(prem_clk_clocks, ARRAY_SIZE(prem_clk_clocks),
+				parent);
+
+	switch (i) {
+	case 0:
+		reg &= ~CCM_CSCR_SYSTEM_SEL;
+		break;
+	case 1:
+		reg |= CCM_CSCR_SYSTEM_SEL;
+		break;
+	default:
+		return i;
+	}
+
+	__raw_writel(reg, CCM_CSCR);
+
+	return 0;
+}
+
+static struct clk prem_clk = {
+	.set_parent = prem_clk_set_parent,
+};
+
+static unsigned long system_clk_get_rate(struct clk *clk)
+{
+	return mxc_decode_pll(__raw_readl(CCM_SPCTL0),
+			      clk_get_rate(clk->parent));
+}
+
+static struct clk system_clk = {
+	.parent = &prem_clk,
+	.get_rate = system_clk_get_rate,
+};
+
+static unsigned long mcu_clk_get_rate(struct clk *clk)
+{
+	return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
+			      clk_get_rate(clk->parent));
+}
+
+static struct clk mcu_clk = {
+	.parent = &clk32_premult,
+	.get_rate = mcu_clk_get_rate,
+};
+
+static unsigned long fclk_get_rate(struct clk *clk)
+{
+	unsigned long fclk = clk_get_rate(clk->parent);
+
+	if (__raw_readl(CCM_CSCR) & CCM_CSCR_PRESC)
+		fclk /= 2;
+
+	return fclk;
+}
+
+static struct clk fclk = {
+	.parent = &mcu_clk,
+	.get_rate = fclk_get_rate,
+};
+
+/*
+ *  get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
+ */
+static unsigned long hclk_get_rate(struct clk *clk)
+{
+	return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
+			CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET) + 1);
+}
+
+static unsigned long hclk_round_rate(struct clk *clk, unsigned long rate)
+{
+	return _clk_simple_round_rate(clk, rate, 16);
+}
+
+static int hclk_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int div;
+	unsigned int reg;
+	unsigned long parent_rate;
+
+	parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	if (div > 16 || div < 1 || ((parent_rate / div) != rate))
+		return -EINVAL;
+
+	div--;
+
+	reg = __raw_readl(CCM_CSCR);
+	reg &= ~CCM_CSCR_BCLK_MASK;
+	reg |= div << CCM_CSCR_BCLK_OFFSET;
+	__raw_writel(reg, CCM_CSCR);
+
+	return 0;
+}
+
+static struct clk hclk = {
+	.parent = &system_clk,
+	.get_rate = hclk_get_rate,
+	.round_rate = hclk_round_rate,
+	.set_rate = hclk_set_rate,
+};
+
+static unsigned long clk48m_get_rate(struct clk *clk)
+{
+	return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
+			CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET) + 1);
+}
+
+static unsigned long clk48m_round_rate(struct clk *clk, unsigned long rate)
+{
+	return _clk_simple_round_rate(clk, rate, 8);
+}
+
+static int clk48m_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int div;
+	unsigned int reg;
+	unsigned long parent_rate;
+
+	parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	if (div > 8 || div < 1 || ((parent_rate / div) != rate))
+		return -EINVAL;
+
+	div--;
+
+	reg = __raw_readl(CCM_CSCR);
+	reg &= ~CCM_CSCR_USB_MASK;
+	reg |= div << CCM_CSCR_USB_OFFSET;
+	__raw_writel(reg, CCM_CSCR);
+
+	return 0;
+}
+
+static struct clk clk48m = {
+	.parent = &system_clk,
+	.get_rate = clk48m_get_rate,
+	.round_rate = clk48m_round_rate,
+	.set_rate = clk48m_set_rate,
+};
+
+/*
+ *  get peripheral clock 1 ( UART[12], Timer[12], PWM )
+ */
+static unsigned long perclk1_get_rate(struct clk *clk)
+{
+	return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
+			CCM_PCDR_PCLK1_MASK) >> CCM_PCDR_PCLK1_OFFSET) + 1);
+}
+
+static unsigned long perclk1_round_rate(struct clk *clk, unsigned long rate)
+{
+	return _clk_simple_round_rate(clk, rate, 16);
+}
+
+static int perclk1_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int div;
+	unsigned int reg;
+	unsigned long parent_rate;
+
+	parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	if (div > 16 || div < 1 || ((parent_rate / div) != rate))
+		return -EINVAL;
+
+	div--;
+
+	reg = __raw_readl(CCM_PCDR);
+	reg &= ~CCM_PCDR_PCLK1_MASK;
+	reg |= div << CCM_PCDR_PCLK1_OFFSET;
+	__raw_writel(reg, CCM_PCDR);
+
+	return 0;
+}
+
+/*
+ *  get peripheral clock 2 ( LCD, SD, SPI[12] )
+ */
+static unsigned long perclk2_get_rate(struct clk *clk)
+{
+	return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
+			CCM_PCDR_PCLK2_MASK) >> CCM_PCDR_PCLK2_OFFSET) + 1);
+}
+
+static unsigned long perclk2_round_rate(struct clk *clk, unsigned long rate)
+{
+	return _clk_simple_round_rate(clk, rate, 16);
+}
+
+static int perclk2_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int div;
+	unsigned int reg;
+	unsigned long parent_rate;
+
+	parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	if (div > 16 || div < 1 || ((parent_rate / div) != rate))
+		return -EINVAL;
+
+	div--;
+
+	reg = __raw_readl(CCM_PCDR);
+	reg &= ~CCM_PCDR_PCLK2_MASK;
+	reg |= div << CCM_PCDR_PCLK2_OFFSET;
+	__raw_writel(reg, CCM_PCDR);
+
+	return 0;
+}
+
+/*
+ *  get peripheral clock 3 ( SSI )
+ */
+static unsigned long perclk3_get_rate(struct clk *clk)
+{
+	return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
+			CCM_PCDR_PCLK3_MASK) >> CCM_PCDR_PCLK3_OFFSET) + 1);
+}
+
+static unsigned long perclk3_round_rate(struct clk *clk, unsigned long rate)
+{
+	return _clk_simple_round_rate(clk, rate, 128);
+}
+
+static int perclk3_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned int div;
+	unsigned int reg;
+	unsigned long parent_rate;
+
+	parent_rate = clk_get_rate(clk->parent);
+
+	div = parent_rate / rate;
+
+	if (div > 128 || div < 1 || ((parent_rate / div) != rate))
+		return -EINVAL;
+
+	div--;
+
+	reg = __raw_readl(CCM_PCDR);
+	reg &= ~CCM_PCDR_PCLK3_MASK;
+	reg |= div << CCM_PCDR_PCLK3_OFFSET;
+	__raw_writel(reg, CCM_PCDR);
+
+	return 0;
+}
+
+static struct clk perclk[] = {
+	{
+		.id = 0,
+		.parent = &system_clk,
+		.get_rate = perclk1_get_rate,
+		.round_rate = perclk1_round_rate,
+		.set_rate = perclk1_set_rate,
+	}, {
+		.id = 1,
+		.parent = &system_clk,
+		.get_rate = perclk2_get_rate,
+		.round_rate = perclk2_round_rate,
+		.set_rate = perclk2_set_rate,
+	}, {
+		.id = 2,
+		.parent = &system_clk,
+		.get_rate = perclk3_get_rate,
+		.round_rate = perclk3_round_rate,
+		.set_rate = perclk3_set_rate,
+	}
+};
+
+static const struct clk *clko_clocks[] = {
+	&perclk[0],
+	&hclk,
+	&clk48m,
+	&clk16m,
+	&prem_clk,
+	&fclk,
+};
+
+static int clko_set_parent(struct clk *clk, struct clk *parent)
+{
+	int i;
+	unsigned int reg;
+
+	i = _clk_can_use_parent(clko_clocks, ARRAY_SIZE(clko_clocks), parent);
+	if (i < 0)
+		return i;
+
+	reg = __raw_readl(CCM_CSCR) & ~CCM_CSCR_CLKO_MASK;
+	reg |= i << CCM_CSCR_CLKO_OFFSET;
+	__raw_writel(reg, CCM_CSCR);
+
+	if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) {
+		clk->set_rate = _clk_parent_set_rate;
+		clk->round_rate = _clk_parent_round_rate;
+	} else {
+		clk->set_rate = NULL;
+		clk->round_rate = NULL;
+	}
+
+	return 0;
+}
+
+static struct clk clko_clk = {
+	.set_parent = clko_set_parent,
+};
+
+static struct clk dma_clk = {
+	.parent = &hclk,
+	.round_rate = _clk_parent_round_rate,
+	.set_rate = _clk_parent_set_rate,
+	.enable = _clk_enable,
+	.enable_reg = SCM_GCCR,
+	.enable_shift = SCM_GCCR_DMA_CLK_EN_OFFSET,
+	.disable = _clk_disable,
+};
+
+static struct clk csi_clk = {
+	.parent = &hclk,
+	.round_rate = _clk_parent_round_rate,
+	.set_rate = _clk_parent_set_rate,
+	.enable = _clk_enable,
+	.enable_reg = SCM_GCCR,
+	.enable_shift = SCM_GCCR_CSI_CLK_EN_OFFSET,
+	.disable = _clk_disable,
+};
+
+static struct clk mma_clk = {
+	.parent = &hclk,
+	.round_rate = _clk_parent_round_rate,
+	.set_rate = _clk_parent_set_rate,
+	.enable = _clk_enable,
+	.enable_reg = SCM_GCCR,
+	.enable_shift = SCM_GCCR_MMA_CLK_EN_OFFSET,
+	.disable = _clk_disable,
+};
+
+static struct clk usbd_clk = {
+	.parent = &clk48m,
+	.round_rate = _clk_parent_round_rate,
+	.set_rate = _clk_parent_set_rate,
+	.enable = _clk_enable,
+	.enable_reg = SCM_GCCR,
+	.enable_shift = SCM_GCCR_USBD_CLK_EN_OFFSET,
+	.disable = _clk_disable,
+};
+
+static struct clk gpt_clk = {
+	.parent = &perclk[0],
+	.round_rate = _clk_parent_round_rate,
+	.set_rate = _clk_parent_set_rate,
+};
+
+static struct clk uart_clk = {
+	.parent = &perclk[0],
+	.round_rate = _clk_parent_round_rate,
+	.set_rate = _clk_parent_set_rate,
+};
+
+static struct clk i2c_clk = {
+	.parent = &hclk,
+	.round_rate = _clk_parent_round_rate,
+	.set_rate = _clk_parent_set_rate,
+};
+
+static struct clk spi_clk = {
+	.parent = &perclk[1],
+	.round_rate = _clk_parent_round_rate,
+	.set_rate = _clk_parent_set_rate,
+};
+
+static struct clk sdhc_clk = {
+	.parent = &perclk[1],
+	.round_rate = _clk_parent_round_rate,
+	.set_rate = _clk_parent_set_rate,
+};
+
+static struct clk lcdc_clk = {
+	.parent = &perclk[1],
+	.round_rate = _clk_parent_round_rate,
+	.set_rate = _clk_parent_set_rate,
+};
+
+static struct clk mshc_clk = {
+	.parent = &hclk,
+	.round_rate = _clk_parent_round_rate,
+	.set_rate = _clk_parent_set_rate,
+};
+
+static struct clk ssi_clk = {
+	.parent = &perclk[2],
+	.round_rate = _clk_parent_round_rate,
+	.set_rate = _clk_parent_set_rate,
+};
+
+static struct clk rtc_clk = {
+	.parent = &clk32,
+};
+
+#define _REGISTER_CLOCK(d, n, c) \
+	{ \
+		.dev_id = d, \
+		.con_id = n, \
+		.clk = &c, \
+	},
+static struct clk_lookup lookups[] __initdata = {
+	_REGISTER_CLOCK(NULL, "dma", dma_clk)
+	_REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
+	_REGISTER_CLOCK(NULL, "mma", mma_clk)
+	_REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
+	_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
+	_REGISTER_CLOCK("imx-uart.0", NULL, uart_clk)
+	_REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
+	_REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
+	_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
+	_REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
+	_REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
+	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
+	_REGISTER_CLOCK(NULL, "mshc", mshc_clk)
+	_REGISTER_CLOCK(NULL, "ssi", ssi_clk)
+	_REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
+};
+
+int __init mx1_clocks_init(unsigned long fref)
+{
+	unsigned int reg;
+
+	/* disable clocks we are able to */
+	__raw_writel(0, SCM_GCCR);
+
+	clk32_rate = fref;
+	reg = __raw_readl(CCM_CSCR);
+
+	/* detect clock reference for system PLL */
+	if (reg & CCM_CSCR_SYSTEM_SEL) {
+		prem_clk.parent = &clk16m;
+	} else {
+		/* ensure that oscillator is disabled */
+		reg &= ~(1 << CCM_CSCR_OSC_EN_SHIFT);
+		__raw_writel(reg, CCM_CSCR);
+		prem_clk.parent = &clk32_premult;
+	}
+
+	/* detect reference for CLKO */
+	reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
+	clko_clk.parent = (struct clk *)clko_clocks[reg];
+
+	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+	clk_enable(&hclk);
+	clk_enable(&fclk);
+
+	mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
+			MX1_TIM1_INT);
+
+	return 0;
+}
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index b372805..ceae641 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -11,6 +11,9 @@
  *
  * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
  * Copyright 2008 Juergen Beisert, kernel at pengutronix.de
+ * Copyright 2008 Sascha Hauer, kernel at pengutronix.de
+ * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas at teltonika.lt>
+ * Copyright (c) 2008 Darius Augulis <darius.augulis at teltonika.lt>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
@@ -41,6 +44,199 @@
 
 #include "devices.h"
 
+#if defined(CONFIG_ARCH_MX1)
+static struct resource imx1_camera_resources[] = {
+	{
+		.start  = 0x00224000,
+		.end    = 0x00224010,
+		.flags  = IORESOURCE_MEM,
+	}, {
+		.start  = MX1_CSI_INT,
+		.end    = MX1_CSI_INT,
+		.flags  = IORESOURCE_IRQ,
+	},
+};
+
+static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device imx1_camera_device = {
+	.name           = "mx1-camera",
+	.id             = 0, /* This is used to put cameras on this interface */
+	.dev		= {
+		.dma_mask = &imx1_camera_dmamask,
+		.coherent_dma_mask = DMA_BIT_MASK(32),
+	},
+	.resource       = imx1_camera_resources,
+	.num_resources  = ARRAY_SIZE(imx1_camera_resources),
+};
+
+static struct resource imx_i2c_resources[] = {
+	{
+		.start  = 0x00217000,
+		.end    = 0x00217010,
+		.flags  = IORESOURCE_MEM,
+	}, {
+		.start  = MX1_I2C_INT,
+		.end    = MX1_I2C_INT,
+		.flags  = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device imx_i2c_device0 = {
+	.name           = "imx-i2c",
+	.id             = 0,
+	.resource       = imx_i2c_resources,
+	.num_resources  = ARRAY_SIZE(imx_i2c_resources),
+};
+
+#define DEFINE_IMX1_UART_DEVICE(n, baseaddr, irqrx, irqtx, irqrts)	\
+	static struct resource imx1_uart_resources ## n[] = {		\
+		{							\
+			.start = baseaddr,				\
+			.end = baseaddr + 0xd0,				\
+			.flags = IORESOURCE_MEM,			\
+		}, {							\
+			.start = irqrx,					\
+			.end = irqrx,					\
+			.flags = IORESOURCE_IRQ,			\
+		}, {							\
+			.start = irqtx,					\
+			.end = irqtx,					\
+			.flags = IORESOURCE_IRQ,			\
+		}, {							\
+			.start = irqrts,				\
+			.end = irqrts,					\
+			.flags = IORESOURCE_IRQ,			\
+		},							\
+	};								\
+									\
+	struct platform_device imx1_uart_device ## n = {		\
+		.name = "imx-uart",					\
+		.id = n,						\
+		.num_resources = ARRAY_SIZE(imx1_uart_resources ## n),	\
+		.resource = imx1_uart_resources ## n,			\
+	}
+
+DEFINE_IMX1_UART_DEVICE(0, MX1_UART1_BASE_ADDR, MX1_UART1_MINT_RX, MX1_UART1_MINT_TX, MX1_UART1_MINT_RTS);
+DEFINE_IMX1_UART_DEVICE(1, MX1_UART2_BASE_ADDR, MX1_UART2_MINT_RX, MX1_UART2_MINT_TX, MX1_UART2_MINT_RTS);
+
+static struct resource imx_rtc_resources[] = {
+	{
+		.start  = 0x00204000,
+		.end    = 0x00204024,
+		.flags  = IORESOURCE_MEM,
+	}, {
+		.start  = MX1_RTC_INT,
+		.end    = MX1_RTC_INT,
+		.flags  = IORESOURCE_IRQ,
+	}, {
+		.start  = MX1_RTC_SAMINT,
+		.end    = MX1_RTC_SAMINT,
+		.flags  = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device imx_rtc_device = {
+	.name           = "rtc-imx",
+	.id             = 0,
+	.resource       = imx_rtc_resources,
+	.num_resources  = ARRAY_SIZE(imx_rtc_resources),
+};
+
+static struct resource imx_wdt_resources[] = {
+	{
+		.start  = 0x00201000,
+		.end    = 0x00201008,
+		.flags  = IORESOURCE_MEM,
+	}, {
+		.start  = MX1_WDT_INT,
+		.end    = MX1_WDT_INT,
+		.flags  = IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device imx_wdt_device = {
+	.name           = "imx-wdt",
+	.id             = 0,
+	.resource       = imx_wdt_resources,
+	.num_resources  = ARRAY_SIZE(imx_wdt_resources),
+};
+
+static struct resource imx_usb_resources[] = {
+	{
+		.start	= 0x00212000,
+		.end	= 0x00212148,
+		.flags	= IORESOURCE_MEM,
+	}, {
+		.start	= MX1_USBD_INT0,
+		.end	= MX1_USBD_INT0,
+		.flags	= IORESOURCE_IRQ,
+	}, {
+		.start	= MX1_USBD_INT1,
+		.end	= MX1_USBD_INT1,
+		.flags	= IORESOURCE_IRQ,
+	}, {
+		.start	= MX1_USBD_INT2,
+		.end	= MX1_USBD_INT2,
+		.flags	= IORESOURCE_IRQ,
+	}, {
+		.start	= MX1_USBD_INT3,
+		.end	= MX1_USBD_INT3,
+		.flags	= IORESOURCE_IRQ,
+	}, {
+		.start	= MX1_USBD_INT4,
+		.end	= MX1_USBD_INT4,
+		.flags	= IORESOURCE_IRQ,
+	}, {
+		.start	= MX1_USBD_INT5,
+		.end	= MX1_USBD_INT5,
+		.flags	= IORESOURCE_IRQ,
+	}, {
+		.start	= MX1_USBD_INT6,
+		.end	= MX1_USBD_INT6,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device imx_usb_device = {
+	.name		= "imx_udc",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(imx_usb_resources),
+	.resource	= imx_usb_resources,
+};
+
+/* GPIO port description */
+static struct mxc_gpio_port imx_gpio_ports[] = {
+	{
+		.chip.label = "gpio-0",
+		.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
+		.irq = MX1_GPIO_INT_PORTA,
+		.virtual_irq_start = MXC_GPIO_IRQ_START,
+	}, {
+		.chip.label = "gpio-1",
+		.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
+		.irq = MX1_GPIO_INT_PORTB,
+		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+	}, {
+		.chip.label = "gpio-2",
+		.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
+		.irq = MX1_GPIO_INT_PORTC,
+		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+	}, {
+		.chip.label = "gpio-3",
+		.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
+		.irq = MX1_GPIO_INT_PORTD,
+		.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
+	}
+};
+
+int __init imx1_register_gpios(void)
+{
+	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+}
+#endif
+
+#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
 /*
  * SPI master controller
  *
@@ -526,3 +722,4 @@ struct platform_device mx21_usbhc_device = {
 	.resource	= mx21_usbhc_resources,
 };
 #endif
+#endif
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index 65c4a43..5c1a0dc 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -1,3 +1,14 @@
+#ifdef CONFIG_ARCH_MX1
+extern struct platform_device imx1_camera_device;
+extern struct platform_device imx_i2c_device0;
+extern struct platform_device imx1_uart_device0;
+extern struct platform_device imx1_uart_device1;
+extern struct platform_device imx_rtc_device;
+extern struct platform_device imx_wdt_device;
+extern struct platform_device imx_usb_device;
+#endif
+
+#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
 extern struct platform_device mxc_gpt1;
 extern struct platform_device mxc_gpt2;
 #ifdef CONFIG_MACH_MX27
@@ -42,3 +53,4 @@ extern struct platform_device mxc_spi_device2;
 extern struct platform_device mx21_usbhc_device;
 extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
+#endif
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
new file mode 100644
index 0000000..5d7c85f
--- /dev/null
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -0,0 +1,165 @@
+/*
+ * arch/arm/mach-imx/mach-mx1ads.c
+ *
+ * Initially based on:
+ *	linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
+ *	Copyright (c) 2004 Sascha Hauer <sascha at saschahauer.de>
+ *
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/i2c.h>
+#include <linux/i2c/pcf857x.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/i2c.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx1.h>
+#include <mach/irqs.h>
+
+#include "devices.h"
+
+static int mx1ads_pins[] = {
+	/* UART1 */
+	PC9_PF_UART1_CTS,
+	PC10_PF_UART1_RTS,
+	PC11_PF_UART1_TXD,
+	PC12_PF_UART1_RXD,
+	/* UART2 */
+	PB28_PF_UART2_CTS,
+	PB29_PF_UART2_RTS,
+	PB30_PF_UART2_TXD,
+	PB31_PF_UART2_RXD,
+	/* I2C */
+	PA15_PF_I2C_SDA,
+	PA16_PF_I2C_SCL,
+	/* SPI */
+	PC13_PF_SPI1_SPI_RDY,
+	PC14_PF_SPI1_SCLK,
+	PC15_PF_SPI1_SS,
+	PC16_PF_SPI1_MISO,
+	PC17_PF_SPI1_MOSI,
+};
+
+/*
+ * UARTs platform data
+ */
+
+static struct imxuart_platform_data uart_pdata[] = {
+	{
+		.flags = IMXUART_HAVE_RTSCTS,
+	}, {
+		.flags = IMXUART_HAVE_RTSCTS,
+	},
+};
+
+/*
+ * Physmap flash
+ */
+
+static struct physmap_flash_data mx1ads_flash_data = {
+	.width		= 4,		/* bankwidth in bytes */
+};
+
+static struct resource flash_resource = {
+	.start	= MX1_CS0_PHYS,
+	.end	= MX1_CS0_PHYS + SZ_32M - 1,
+	.flags	= IORESOURCE_MEM,
+};
+
+static struct platform_device flash_device = {
+	.name	= "physmap-flash",
+	.id	= 0,
+	.resource = &flash_resource,
+	.num_resources = 1,
+};
+
+/*
+ * I2C
+ */
+static struct pcf857x_platform_data pcf857x_data[] = {
+	{
+		.gpio_base = 4 * 32,
+	}, {
+		.gpio_base = 4 * 32 + 16,
+	}
+};
+
+static struct imxi2c_platform_data mx1ads_i2c_data = {
+	.bitrate = 100000,
+};
+
+static struct i2c_board_info mx1ads_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("pcf8575", 0x22),
+		.platform_data = &pcf857x_data[0],
+	}, {
+		I2C_BOARD_INFO("pcf8575", 0x24),
+		.platform_data = &pcf857x_data[1],
+	},
+};
+
+/*
+ * Board init
+ */
+static void __init mx1ads_init(void)
+{
+	mxc_gpio_setup_multiple_pins(mx1ads_pins,
+		ARRAY_SIZE(mx1ads_pins), "mx1ads");
+
+	/* UART */
+	mxc_register_device(&imx1_uart_device0, &uart_pdata[0]);
+	mxc_register_device(&imx1_uart_device1, &uart_pdata[1]);
+
+	/* Physmap flash */
+	mxc_register_device(&flash_device, &mx1ads_flash_data);
+
+	/* I2C */
+	i2c_register_board_info(0, mx1ads_i2c_devices,
+				ARRAY_SIZE(mx1ads_i2c_devices));
+
+	mxc_register_device(&imx_i2c_device0, &mx1ads_i2c_data);
+}
+
+static void __init mx1ads_timer_init(void)
+{
+	mx1_clocks_init(32000);
+}
+
+struct sys_timer mx1ads_timer = {
+	.init	= mx1ads_timer_init,
+};
+
+MACHINE_START(MX1ADS, "Freescale MX1ADS")
+	/* Maintainer: Sascha Hauer, Pengutronix */
+	.phys_io	= MX1_IO_BASE_ADDR,
+	.io_pg_offst	= (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
+	.boot_params	= MX1_PHYS_OFFSET + 0x100,
+	.map_io		= mx1_map_io,
+	.init_irq	= mx1_init_irq,
+	.timer		= &mx1ads_timer,
+	.init_machine	= mx1ads_init,
+MACHINE_END
+
+MACHINE_START(MXLADS, "Freescale MXLADS")
+	.phys_io	= MX1_IO_BASE_ADDR,
+	.io_pg_offst	= (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
+	.boot_params	= MX1_PHYS_OFFSET + 0x100,
+	.map_io		= mx1_map_io,
+	.init_irq	= mx1_init_irq,
+	.timer		= &mx1ads_timer,
+	.init_machine	= mx1ads_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
new file mode 100644
index 0000000..482b24d
--- /dev/null
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -0,0 +1,157 @@
+/*
+ * linux/arch/arm/mach-mx1/mach-scb9328.c
+ *
+ * Copyright (c) 2004 Sascha Hauer <saschahauer at web.de>
+ * Copyright (c) 2006-2008 Juergen Beisert <jbeisert at netscape.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/interrupt.h>
+#include <linux/dm9000.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx1.h>
+
+#include "devices.h"
+
+/*
+ * This scb9328 has a 32MiB flash
+ */
+static struct resource flash_resource = {
+	.start	= MX1_CS0_PHYS,
+	.end	= MX1_CS0_PHYS + (32 * 1024 * 1024) - 1,
+	.flags	= IORESOURCE_MEM,
+};
+
+static struct physmap_flash_data scb_flash_data = {
+	.width  = 2,
+};
+
+static struct platform_device scb_flash_device = {
+	.name		= "physmap-flash",
+	.id		= 0,
+	.dev = {
+		.platform_data = &scb_flash_data,
+	},
+	.resource = &flash_resource,
+	.num_resources = 1,
+};
+
+/*
+ * scb9328 has a DM9000 network controller
+ * connected to CS5, with 16 bit data path
+ * and interrupt connected to GPIO 3
+ */
+
+/*
+ * internal datapath is fixed 16 bit
+ */
+static struct dm9000_plat_data dm9000_platdata = {
+	.flags	= DM9000_PLATF_16BITONLY,
+};
+
+/*
+ * the DM9000 drivers wants two defined address spaces
+ * to gain access to address latch registers and the data path.
+ */
+static struct resource dm9000x_resources[] = {
+	{
+		.name	= "address area",
+		.start	= MX1_CS5_PHYS,
+		.end	= MX1_CS5_PHYS + 1,
+		.flags	= IORESOURCE_MEM,	/* address access */
+	}, {
+		.name	= "data area",
+		.start	= MX1_CS5_PHYS + 4,
+		.end	= MX1_CS5_PHYS + 5,
+		.flags	= IORESOURCE_MEM,	/* data access */
+	}, {
+		.start	= IRQ_GPIOC(3),
+		.end	= IRQ_GPIOC(3),
+		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+	},
+};
+
+static struct platform_device dm9000x_device = {
+	.name		= "dm9000",
+	.id		= 0,
+	.num_resources	= ARRAY_SIZE(dm9000x_resources),
+	.resource	= dm9000x_resources,
+	.dev		= {
+		.platform_data = &dm9000_platdata,
+	}
+};
+
+static int mxc_uart1_pins[] = {
+	PC9_PF_UART1_CTS,
+	PC10_PF_UART1_RTS,
+	PC11_PF_UART1_TXD,
+	PC12_PF_UART1_RXD,
+};
+
+static int uart1_mxc_init(struct platform_device *pdev)
+{
+	return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+			ARRAY_SIZE(mxc_uart1_pins), "UART1");
+}
+
+static void uart1_mxc_exit(struct platform_device *pdev)
+{
+	mxc_gpio_release_multiple_pins(mxc_uart1_pins,
+			ARRAY_SIZE(mxc_uart1_pins));
+}
+
+static struct imxuart_platform_data uart_pdata = {
+	.init = uart1_mxc_init,
+	.exit = uart1_mxc_exit,
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct platform_device *devices[] __initdata = {
+	&scb_flash_device,
+	&dm9000x_device,
+};
+
+/*
+ * scb9328_init - Init the CPU card itself
+ */
+static void __init scb9328_init(void)
+{
+	mxc_register_device(&imx1_uart_device0, &uart_pdata);
+
+	printk(KERN_INFO"Scb9328: Adding devices\n");
+	platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+static void __init scb9328_timer_init(void)
+{
+	mx1_clocks_init(32000);
+}
+
+static struct sys_timer scb9328_timer = {
+	.init	= scb9328_timer_init,
+};
+
+MACHINE_START(SCB9328, "Synertronixx scb9328")
+    /* Sascha Hauer */
+	.phys_io	= 0x00200000,
+	.io_pg_offst	= ((0xe0200000) >> 18) & 0xfffc,
+	.boot_params	= 0x08000100,
+	.map_io		= mx1_map_io,
+	.init_irq	= mx1_init_irq,
+	.timer		= &scb9328_timer,
+	.init_machine	= scb9328_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
new file mode 100644
index 0000000..396d0a5
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -0,0 +1,55 @@
+/*
+ *  author: Sascha Hauer
+ *  Created: april 20th, 2004
+ *  Copyright: Synertronixx GmbH
+ *
+ *  Common code for i.MX1 machines
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+
+static struct map_desc imx_io_desc[] __initdata = {
+	{
+		.virtual = MX1_IO_BASE_ADDR_VIRT,
+		.pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
+		.length = MX1_IO_SIZE,
+		.type = MT_DEVICE
+	}
+};
+
+void __init mx1_map_io(void)
+{
+	mxc_set_cpu_type(MXC_CPU_MX1);
+	mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
+
+	iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
+}
+
+int imx1_register_gpios(void);
+
+void __init mx1_init_irq(void)
+{
+	imx1_register_gpios();
+	mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
+}
diff --git a/arch/arm/mach-imx/mx1-camera-fiq-ksym.c b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
new file mode 100644
index 0000000..b09ee12
--- /dev/null
+++ b/arch/arm/mach-imx/mx1-camera-fiq-ksym.c
@@ -0,0 +1,18 @@
+/*
+ * Exported ksyms of ARCH_MX1
+ *
+ * Copyright (C) 2008, Darius Augulis <augulis.darius at gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+
+#include <mach/mx1_camera.h>
+
+/* IMX camera FIQ handler */
+EXPORT_SYMBOL(mx1_camera_sof_fiq_start);
+EXPORT_SYMBOL(mx1_camera_sof_fiq_end);
diff --git a/arch/arm/mach-imx/mx1-camera-fiq.S b/arch/arm/mach-imx/mx1-camera-fiq.S
new file mode 100644
index 0000000..9c69aa6
--- /dev/null
+++ b/arch/arm/mach-imx/mx1-camera-fiq.S
@@ -0,0 +1,35 @@
+/*
+ *  Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas at teltonika.lt>
+ *
+ *  Based on linux/arch/arm/lib/floppydma.S
+ *      Copyright (C) 1995, 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+		.text
+		.global	mx1_camera_sof_fiq_end
+		.global	mx1_camera_sof_fiq_start
+mx1_camera_sof_fiq_start:
+		@ enable dma
+		ldr	r12, [r9]
+		orr	r12, r12, #0x00000001
+		str	r12, [r9]
+		@ unmask DMA interrupt
+		ldr	r12, [r8]
+		bic	r12, r12, r13
+		str	r12, [r8]
+		@ disable SOF interrupt
+		ldr	r12, [r10]
+		bic	r12, r12, #0x00010000
+		str	r12, [r10]
+		@ clear SOF flag
+		mov	r12, #0x00010000
+		str	r12, [r11]
+		@ return from FIQ
+		subs	pc, lr, #4
+mx1_camera_sof_fiq_end:
diff --git a/arch/arm/mach-mx1/Kconfig b/arch/arm/mach-mx1/Kconfig
deleted file mode 100644
index eb7660f..0000000
--- a/arch/arm/mach-mx1/Kconfig
+++ /dev/null
@@ -1,19 +0,0 @@
-if ARCH_MX1
-
-comment "MX1 platforms:"
-
-config MACH_MXLADS
-	bool
-
-config ARCH_MX1ADS
-	bool "MX1ADS platform"
-	select MACH_MXLADS
-	help
-	  Say Y here if you are using Motorola MX1ADS/MXLADS boards
-
-config MACH_SCB9328
-	bool "Synertronixx scb9328"
-	help
-	  Say Y here if you are using a Synertronixx scb9328 board
-
-endif
diff --git a/arch/arm/mach-mx1/Makefile b/arch/arm/mach-mx1/Makefile
deleted file mode 100644
index 297d172..0000000
--- a/arch/arm/mach-mx1/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y			+= generic.o clock.o devices.o
-
-# Support for CMOS sensor interface
-obj-$(CONFIG_MX1_VIDEO)	+= ksym_mx1.o mx1_camera_fiq.o
-
-# Specific board support
-obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
-obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
diff --git a/arch/arm/mach-mx1/Makefile.boot b/arch/arm/mach-mx1/Makefile.boot
deleted file mode 100644
index 8ed1492..0000000
--- a/arch/arm/mach-mx1/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
-   zreladdr-y	:= 0x08008000
-params_phys-y	:= 0x08000100
-initrd_phys-y	:= 0x08800000
-
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
deleted file mode 100644
index c05096c..0000000
--- a/arch/arm/mach-mx1/clock.c
+++ /dev/null
@@ -1,636 +0,0 @@
-/*
- *  Copyright (C) 2008 Sascha Hauer <s.hauer at pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/math64.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include <asm/clkdev.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-
-#define IO_ADDR_CCM(off)	(MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
-
-/* CCM register addresses */
-#define CCM_CSCR	IO_ADDR_CCM(0x0)
-#define CCM_MPCTL0	IO_ADDR_CCM(0x4)
-#define CCM_SPCTL0	IO_ADDR_CCM(0xc)
-#define CCM_PCDR	IO_ADDR_CCM(0x20)
-
-#define CCM_CSCR_CLKO_OFFSET	29
-#define CCM_CSCR_CLKO_MASK	(0x7 << 29)
-#define CCM_CSCR_USB_OFFSET	26
-#define CCM_CSCR_USB_MASK	(0x7 << 26)
-#define CCM_CSCR_OSC_EN_SHIFT	17
-#define CCM_CSCR_SYSTEM_SEL	(1 << 16)
-#define CCM_CSCR_BCLK_OFFSET	10
-#define CCM_CSCR_BCLK_MASK	(0xf << 10)
-#define CCM_CSCR_PRESC		(1 << 15)
-
-#define CCM_PCDR_PCLK3_OFFSET	16
-#define CCM_PCDR_PCLK3_MASK	(0x7f << 16)
-#define CCM_PCDR_PCLK2_OFFSET	4
-#define CCM_PCDR_PCLK2_MASK	(0xf << 4)
-#define CCM_PCDR_PCLK1_OFFSET	0
-#define CCM_PCDR_PCLK1_MASK	0xf
-
-#define IO_ADDR_SCM(off)	(MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
-
-/* SCM register addresses */
-#define SCM_GCCR	IO_ADDR_SCM(0xc)
-
-#define SCM_GCCR_DMA_CLK_EN_OFFSET	3
-#define SCM_GCCR_CSI_CLK_EN_OFFSET	2
-#define SCM_GCCR_MMA_CLK_EN_OFFSET	1
-#define SCM_GCCR_USBD_CLK_EN_OFFSET	0
-
-static int _clk_enable(struct clk *clk)
-{
-	unsigned int reg;
-
-	reg = __raw_readl(clk->enable_reg);
-	reg |= 1 << clk->enable_shift;
-	__raw_writel(reg, clk->enable_reg);
-
-	return 0;
-}
-
-static void _clk_disable(struct clk *clk)
-{
-	unsigned int reg;
-
-	reg = __raw_readl(clk->enable_reg);
-	reg &= ~(1 << clk->enable_shift);
-	__raw_writel(reg, clk->enable_reg);
-}
-
-static int _clk_can_use_parent(const struct clk *clk_arr[], unsigned int size,
-			       struct clk *parent)
-{
-	int i;
-
-	for (i = 0; i < size; i++)
-		if (parent == clk_arr[i])
-			return i;
-
-	return -EINVAL;
-}
-
-static unsigned long
-_clk_simple_round_rate(struct clk *clk, unsigned long rate, unsigned int limit)
-{
-	int div;
-	unsigned long parent_rate;
-
-	parent_rate = clk_get_rate(clk->parent);
-
-	div = parent_rate / rate;
-	if (parent_rate % rate)
-		div++;
-
-	if (div > limit)
-		div = limit;
-
-	return parent_rate / div;
-}
-
-static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
-{
-	return clk->parent->round_rate(clk->parent, rate);
-}
-
-static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
-{
-	return clk->parent->set_rate(clk->parent, rate);
-}
-
-static unsigned long clk16m_get_rate(struct clk *clk)
-{
-	return 16000000;
-}
-
-static struct clk clk16m = {
-	.get_rate = clk16m_get_rate,
-	.enable = _clk_enable,
-	.enable_reg = CCM_CSCR,
-	.enable_shift = CCM_CSCR_OSC_EN_SHIFT,
-	.disable = _clk_disable,
-};
-
-/* in Hz */
-static unsigned long clk32_rate;
-
-static unsigned long clk32_get_rate(struct clk *clk)
-{
-	return clk32_rate;
-}
-
-static struct clk clk32 = {
-	.get_rate = clk32_get_rate,
-};
-
-static unsigned long clk32_premult_get_rate(struct clk *clk)
-{
-	return clk_get_rate(clk->parent) * 512;
-}
-
-static struct clk clk32_premult = {
-	.parent = &clk32,
-	.get_rate = clk32_premult_get_rate,
-};
-
-static const struct clk *prem_clk_clocks[] = {
-	&clk32_premult,
-	&clk16m,
-};
-
-static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
-{
-	int i;
-	unsigned int reg = __raw_readl(CCM_CSCR);
-
-	i = _clk_can_use_parent(prem_clk_clocks, ARRAY_SIZE(prem_clk_clocks),
-				parent);
-
-	switch (i) {
-	case 0:
-		reg &= ~CCM_CSCR_SYSTEM_SEL;
-		break;
-	case 1:
-		reg |= CCM_CSCR_SYSTEM_SEL;
-		break;
-	default:
-		return i;
-	}
-
-	__raw_writel(reg, CCM_CSCR);
-
-	return 0;
-}
-
-static struct clk prem_clk = {
-	.set_parent = prem_clk_set_parent,
-};
-
-static unsigned long system_clk_get_rate(struct clk *clk)
-{
-	return mxc_decode_pll(__raw_readl(CCM_SPCTL0),
-			      clk_get_rate(clk->parent));
-}
-
-static struct clk system_clk = {
-	.parent = &prem_clk,
-	.get_rate = system_clk_get_rate,
-};
-
-static unsigned long mcu_clk_get_rate(struct clk *clk)
-{
-	return mxc_decode_pll(__raw_readl(CCM_MPCTL0),
-			      clk_get_rate(clk->parent));
-}
-
-static struct clk mcu_clk = {
-	.parent = &clk32_premult,
-	.get_rate = mcu_clk_get_rate,
-};
-
-static unsigned long fclk_get_rate(struct clk *clk)
-{
-	unsigned long fclk = clk_get_rate(clk->parent);
-
-	if (__raw_readl(CCM_CSCR) & CCM_CSCR_PRESC)
-		fclk /= 2;
-
-	return fclk;
-}
-
-static struct clk fclk = {
-	.parent = &mcu_clk,
-	.get_rate = fclk_get_rate,
-};
-
-/*
- *  get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
- */
-static unsigned long hclk_get_rate(struct clk *clk)
-{
-	return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
-			CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET) + 1);
-}
-
-static unsigned long hclk_round_rate(struct clk *clk, unsigned long rate)
-{
-	return _clk_simple_round_rate(clk, rate, 16);
-}
-
-static int hclk_set_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned int div;
-	unsigned int reg;
-	unsigned long parent_rate;
-
-	parent_rate = clk_get_rate(clk->parent);
-
-	div = parent_rate / rate;
-
-	if (div > 16 || div < 1 || ((parent_rate / div) != rate))
-		return -EINVAL;
-
-	div--;
-
-	reg = __raw_readl(CCM_CSCR);
-	reg &= ~CCM_CSCR_BCLK_MASK;
-	reg |= div << CCM_CSCR_BCLK_OFFSET;
-	__raw_writel(reg, CCM_CSCR);
-
-	return 0;
-}
-
-static struct clk hclk = {
-	.parent = &system_clk,
-	.get_rate = hclk_get_rate,
-	.round_rate = hclk_round_rate,
-	.set_rate = hclk_set_rate,
-};
-
-static unsigned long clk48m_get_rate(struct clk *clk)
-{
-	return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
-			CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET) + 1);
-}
-
-static unsigned long clk48m_round_rate(struct clk *clk, unsigned long rate)
-{
-	return _clk_simple_round_rate(clk, rate, 8);
-}
-
-static int clk48m_set_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned int div;
-	unsigned int reg;
-	unsigned long parent_rate;
-
-	parent_rate = clk_get_rate(clk->parent);
-
-	div = parent_rate / rate;
-
-	if (div > 8 || div < 1 || ((parent_rate / div) != rate))
-		return -EINVAL;
-
-	div--;
-
-	reg = __raw_readl(CCM_CSCR);
-	reg &= ~CCM_CSCR_USB_MASK;
-	reg |= div << CCM_CSCR_USB_OFFSET;
-	__raw_writel(reg, CCM_CSCR);
-
-	return 0;
-}
-
-static struct clk clk48m = {
-	.parent = &system_clk,
-	.get_rate = clk48m_get_rate,
-	.round_rate = clk48m_round_rate,
-	.set_rate = clk48m_set_rate,
-};
-
-/*
- *  get peripheral clock 1 ( UART[12], Timer[12], PWM )
- */
-static unsigned long perclk1_get_rate(struct clk *clk)
-{
-	return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
-			CCM_PCDR_PCLK1_MASK) >> CCM_PCDR_PCLK1_OFFSET) + 1);
-}
-
-static unsigned long perclk1_round_rate(struct clk *clk, unsigned long rate)
-{
-	return _clk_simple_round_rate(clk, rate, 16);
-}
-
-static int perclk1_set_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned int div;
-	unsigned int reg;
-	unsigned long parent_rate;
-
-	parent_rate = clk_get_rate(clk->parent);
-
-	div = parent_rate / rate;
-
-	if (div > 16 || div < 1 || ((parent_rate / div) != rate))
-		return -EINVAL;
-
-	div--;
-
-	reg = __raw_readl(CCM_PCDR);
-	reg &= ~CCM_PCDR_PCLK1_MASK;
-	reg |= div << CCM_PCDR_PCLK1_OFFSET;
-	__raw_writel(reg, CCM_PCDR);
-
-	return 0;
-}
-
-/*
- *  get peripheral clock 2 ( LCD, SD, SPI[12] )
- */
-static unsigned long perclk2_get_rate(struct clk *clk)
-{
-	return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
-			CCM_PCDR_PCLK2_MASK) >> CCM_PCDR_PCLK2_OFFSET) + 1);
-}
-
-static unsigned long perclk2_round_rate(struct clk *clk, unsigned long rate)
-{
-	return _clk_simple_round_rate(clk, rate, 16);
-}
-
-static int perclk2_set_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned int div;
-	unsigned int reg;
-	unsigned long parent_rate;
-
-	parent_rate = clk_get_rate(clk->parent);
-
-	div = parent_rate / rate;
-
-	if (div > 16 || div < 1 || ((parent_rate / div) != rate))
-		return -EINVAL;
-
-	div--;
-
-	reg = __raw_readl(CCM_PCDR);
-	reg &= ~CCM_PCDR_PCLK2_MASK;
-	reg |= div << CCM_PCDR_PCLK2_OFFSET;
-	__raw_writel(reg, CCM_PCDR);
-
-	return 0;
-}
-
-/*
- *  get peripheral clock 3 ( SSI )
- */
-static unsigned long perclk3_get_rate(struct clk *clk)
-{
-	return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
-			CCM_PCDR_PCLK3_MASK) >> CCM_PCDR_PCLK3_OFFSET) + 1);
-}
-
-static unsigned long perclk3_round_rate(struct clk *clk, unsigned long rate)
-{
-	return _clk_simple_round_rate(clk, rate, 128);
-}
-
-static int perclk3_set_rate(struct clk *clk, unsigned long rate)
-{
-	unsigned int div;
-	unsigned int reg;
-	unsigned long parent_rate;
-
-	parent_rate = clk_get_rate(clk->parent);
-
-	div = parent_rate / rate;
-
-	if (div > 128 || div < 1 || ((parent_rate / div) != rate))
-		return -EINVAL;
-
-	div--;
-
-	reg = __raw_readl(CCM_PCDR);
-	reg &= ~CCM_PCDR_PCLK3_MASK;
-	reg |= div << CCM_PCDR_PCLK3_OFFSET;
-	__raw_writel(reg, CCM_PCDR);
-
-	return 0;
-}
-
-static struct clk perclk[] = {
-	{
-		.id = 0,
-		.parent = &system_clk,
-		.get_rate = perclk1_get_rate,
-		.round_rate = perclk1_round_rate,
-		.set_rate = perclk1_set_rate,
-	}, {
-		.id = 1,
-		.parent = &system_clk,
-		.get_rate = perclk2_get_rate,
-		.round_rate = perclk2_round_rate,
-		.set_rate = perclk2_set_rate,
-	}, {
-		.id = 2,
-		.parent = &system_clk,
-		.get_rate = perclk3_get_rate,
-		.round_rate = perclk3_round_rate,
-		.set_rate = perclk3_set_rate,
-	}
-};
-
-static const struct clk *clko_clocks[] = {
-	&perclk[0],
-	&hclk,
-	&clk48m,
-	&clk16m,
-	&prem_clk,
-	&fclk,
-};
-
-static int clko_set_parent(struct clk *clk, struct clk *parent)
-{
-	int i;
-	unsigned int reg;
-
-	i = _clk_can_use_parent(clko_clocks, ARRAY_SIZE(clko_clocks), parent);
-	if (i < 0)
-		return i;
-
-	reg = __raw_readl(CCM_CSCR) & ~CCM_CSCR_CLKO_MASK;
-	reg |= i << CCM_CSCR_CLKO_OFFSET;
-	__raw_writel(reg, CCM_CSCR);
-
-	if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) {
-		clk->set_rate = _clk_parent_set_rate;
-		clk->round_rate = _clk_parent_round_rate;
-	} else {
-		clk->set_rate = NULL;
-		clk->round_rate = NULL;
-	}
-
-	return 0;
-}
-
-static struct clk clko_clk = {
-	.set_parent = clko_set_parent,
-};
-
-static struct clk dma_clk = {
-	.parent = &hclk,
-	.round_rate = _clk_parent_round_rate,
-	.set_rate = _clk_parent_set_rate,
-	.enable = _clk_enable,
-	.enable_reg = SCM_GCCR,
-	.enable_shift = SCM_GCCR_DMA_CLK_EN_OFFSET,
-	.disable = _clk_disable,
-};
-
-static struct clk csi_clk = {
-	.parent = &hclk,
-	.round_rate = _clk_parent_round_rate,
-	.set_rate = _clk_parent_set_rate,
-	.enable = _clk_enable,
-	.enable_reg = SCM_GCCR,
-	.enable_shift = SCM_GCCR_CSI_CLK_EN_OFFSET,
-	.disable = _clk_disable,
-};
-
-static struct clk mma_clk = {
-	.parent = &hclk,
-	.round_rate = _clk_parent_round_rate,
-	.set_rate = _clk_parent_set_rate,
-	.enable = _clk_enable,
-	.enable_reg = SCM_GCCR,
-	.enable_shift = SCM_GCCR_MMA_CLK_EN_OFFSET,
-	.disable = _clk_disable,
-};
-
-static struct clk usbd_clk = {
-	.parent = &clk48m,
-	.round_rate = _clk_parent_round_rate,
-	.set_rate = _clk_parent_set_rate,
-	.enable = _clk_enable,
-	.enable_reg = SCM_GCCR,
-	.enable_shift = SCM_GCCR_USBD_CLK_EN_OFFSET,
-	.disable = _clk_disable,
-};
-
-static struct clk gpt_clk = {
-	.parent = &perclk[0],
-	.round_rate = _clk_parent_round_rate,
-	.set_rate = _clk_parent_set_rate,
-};
-
-static struct clk uart_clk = {
-	.parent = &perclk[0],
-	.round_rate = _clk_parent_round_rate,
-	.set_rate = _clk_parent_set_rate,
-};
-
-static struct clk i2c_clk = {
-	.parent = &hclk,
-	.round_rate = _clk_parent_round_rate,
-	.set_rate = _clk_parent_set_rate,
-};
-
-static struct clk spi_clk = {
-	.parent = &perclk[1],
-	.round_rate = _clk_parent_round_rate,
-	.set_rate = _clk_parent_set_rate,
-};
-
-static struct clk sdhc_clk = {
-	.parent = &perclk[1],
-	.round_rate = _clk_parent_round_rate,
-	.set_rate = _clk_parent_set_rate,
-};
-
-static struct clk lcdc_clk = {
-	.parent = &perclk[1],
-	.round_rate = _clk_parent_round_rate,
-	.set_rate = _clk_parent_set_rate,
-};
-
-static struct clk mshc_clk = {
-	.parent = &hclk,
-	.round_rate = _clk_parent_round_rate,
-	.set_rate = _clk_parent_set_rate,
-};
-
-static struct clk ssi_clk = {
-	.parent = &perclk[2],
-	.round_rate = _clk_parent_round_rate,
-	.set_rate = _clk_parent_set_rate,
-};
-
-static struct clk rtc_clk = {
-	.parent = &clk32,
-};
-
-#define _REGISTER_CLOCK(d, n, c) \
-	{ \
-		.dev_id = d, \
-		.con_id = n, \
-		.clk = &c, \
-	},
-static struct clk_lookup lookups[] __initdata = {
-	_REGISTER_CLOCK(NULL, "dma", dma_clk)
-	_REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
-	_REGISTER_CLOCK(NULL, "mma", mma_clk)
-	_REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
-	_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
-	_REGISTER_CLOCK("imx-uart.0", NULL, uart_clk)
-	_REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
-	_REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
-	_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
-	_REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
-	_REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
-	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-	_REGISTER_CLOCK(NULL, "mshc", mshc_clk)
-	_REGISTER_CLOCK(NULL, "ssi", ssi_clk)
-	_REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
-};
-
-int __init mx1_clocks_init(unsigned long fref)
-{
-	unsigned int reg;
-
-	/* disable clocks we are able to */
-	__raw_writel(0, SCM_GCCR);
-
-	clk32_rate = fref;
-	reg = __raw_readl(CCM_CSCR);
-
-	/* detect clock reference for system PLL */
-	if (reg & CCM_CSCR_SYSTEM_SEL) {
-		prem_clk.parent = &clk16m;
-	} else {
-		/* ensure that oscillator is disabled */
-		reg &= ~(1 << CCM_CSCR_OSC_EN_SHIFT);
-		__raw_writel(reg, CCM_CSCR);
-		prem_clk.parent = &clk32_premult;
-	}
-
-	/* detect reference for CLKO */
-	reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
-	clko_clk.parent = (struct clk *)clko_clocks[reg];
-
-	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
-	clk_enable(&hclk);
-	clk_enable(&fclk);
-
-	mxc_timer_init(&gpt_clk, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
-			MX1_TIM1_INT);
-
-	return 0;
-}
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
deleted file mode 100644
index a79e613..0000000
--- a/arch/arm/mach-mx1/devices.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Sascha Hauer, kernel at pengutronix.de
- * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas at teltonika.lt>
- * Copyright (c) 2008 Darius Augulis <darius.augulis at teltonika.lt>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA  02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-
-#include "devices.h"
-
-static struct resource imx1_camera_resources[] = {
-	{
-		.start  = 0x00224000,
-		.end    = 0x00224010,
-		.flags  = IORESOURCE_MEM,
-	}, {
-		.start  = MX1_CSI_INT,
-		.end    = MX1_CSI_INT,
-		.flags  = IORESOURCE_IRQ,
-	},
-};
-
-static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
-
-struct platform_device imx1_camera_device = {
-	.name           = "mx1-camera",
-	.id             = 0, /* This is used to put cameras on this interface */
-	.dev		= {
-		.dma_mask = &imx1_camera_dmamask,
-		.coherent_dma_mask = DMA_BIT_MASK(32),
-	},
-	.resource       = imx1_camera_resources,
-	.num_resources  = ARRAY_SIZE(imx1_camera_resources),
-};
-
-static struct resource imx_i2c_resources[] = {
-	{
-		.start  = 0x00217000,
-		.end    = 0x00217010,
-		.flags  = IORESOURCE_MEM,
-	}, {
-		.start  = MX1_I2C_INT,
-		.end    = MX1_I2C_INT,
-		.flags  = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device imx_i2c_device0 = {
-	.name           = "imx-i2c",
-	.id             = 0,
-	.resource       = imx_i2c_resources,
-	.num_resources  = ARRAY_SIZE(imx_i2c_resources),
-};
-
-#define DEFINE_IMX1_UART_DEVICE(n, baseaddr, irqrx, irqtx, irqrts)	\
-	static struct resource imx1_uart_resources ## n[] = {		\
-		{							\
-			.start = baseaddr,				\
-			.end = baseaddr + 0xd0,				\
-			.flags = IORESOURCE_MEM,			\
-		}, {							\
-			.start = irqrx,					\
-			.end = irqrx,					\
-			.flags = IORESOURCE_IRQ,			\
-		}, {							\
-			.start = irqtx,					\
-			.end = irqtx,					\
-			.flags = IORESOURCE_IRQ,			\
-		}, {							\
-			.start = irqrts,				\
-			.end = irqrts,					\
-			.flags = IORESOURCE_IRQ,			\
-		},							\
-	};								\
-									\
-	struct platform_device imx1_uart_device ## n = {		\
-		.name = "imx-uart",					\
-		.id = n,						\
-		.num_resources = ARRAY_SIZE(imx1_uart_resources ## n),	\
-		.resource = imx1_uart_resources ## n,			\
-	}
-
-DEFINE_IMX1_UART_DEVICE(0, MX1_UART1_BASE_ADDR, MX1_UART1_MINT_RX, MX1_UART1_MINT_TX, MX1_UART1_MINT_RTS);
-DEFINE_IMX1_UART_DEVICE(1, MX1_UART2_BASE_ADDR, MX1_UART2_MINT_RX, MX1_UART2_MINT_TX, MX1_UART2_MINT_RTS);
-
-static struct resource imx_rtc_resources[] = {
-	{
-		.start  = 0x00204000,
-		.end    = 0x00204024,
-		.flags  = IORESOURCE_MEM,
-	}, {
-		.start  = MX1_RTC_INT,
-		.end    = MX1_RTC_INT,
-		.flags  = IORESOURCE_IRQ,
-	}, {
-		.start  = MX1_RTC_SAMINT,
-		.end    = MX1_RTC_SAMINT,
-		.flags  = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device imx_rtc_device = {
-	.name           = "rtc-imx",
-	.id             = 0,
-	.resource       = imx_rtc_resources,
-	.num_resources  = ARRAY_SIZE(imx_rtc_resources),
-};
-
-static struct resource imx_wdt_resources[] = {
-	{
-		.start  = 0x00201000,
-		.end    = 0x00201008,
-		.flags  = IORESOURCE_MEM,
-	}, {
-		.start  = MX1_WDT_INT,
-		.end    = MX1_WDT_INT,
-		.flags  = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device imx_wdt_device = {
-	.name           = "imx-wdt",
-	.id             = 0,
-	.resource       = imx_wdt_resources,
-	.num_resources  = ARRAY_SIZE(imx_wdt_resources),
-};
-
-static struct resource imx_usb_resources[] = {
-	{
-		.start	= 0x00212000,
-		.end	= 0x00212148,
-		.flags	= IORESOURCE_MEM,
-	}, {
-		.start	= MX1_USBD_INT0,
-		.end	= MX1_USBD_INT0,
-		.flags	= IORESOURCE_IRQ,
-	}, {
-		.start	= MX1_USBD_INT1,
-		.end	= MX1_USBD_INT1,
-		.flags	= IORESOURCE_IRQ,
-	}, {
-		.start	= MX1_USBD_INT2,
-		.end	= MX1_USBD_INT2,
-		.flags	= IORESOURCE_IRQ,
-	}, {
-		.start	= MX1_USBD_INT3,
-		.end	= MX1_USBD_INT3,
-		.flags	= IORESOURCE_IRQ,
-	}, {
-		.start	= MX1_USBD_INT4,
-		.end	= MX1_USBD_INT4,
-		.flags	= IORESOURCE_IRQ,
-	}, {
-		.start	= MX1_USBD_INT5,
-		.end	= MX1_USBD_INT5,
-		.flags	= IORESOURCE_IRQ,
-	}, {
-		.start	= MX1_USBD_INT6,
-		.end	= MX1_USBD_INT6,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device imx_usb_device = {
-	.name		= "imx_udc",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(imx_usb_resources),
-	.resource	= imx_usb_resources,
-};
-
-/* GPIO port description */
-static struct mxc_gpio_port imx_gpio_ports[] = {
-	{
-		.chip.label = "gpio-0",
-		.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
-		.irq = MX1_GPIO_INT_PORTA,
-		.virtual_irq_start = MXC_GPIO_IRQ_START,
-	}, {
-		.chip.label = "gpio-1",
-		.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
-		.irq = MX1_GPIO_INT_PORTB,
-		.virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-	}, {
-		.chip.label = "gpio-2",
-		.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
-		.irq = MX1_GPIO_INT_PORTC,
-		.virtual_irq_start = MXC_GPIO_IRQ_START + 64,
-	}, {
-		.chip.label = "gpio-3",
-		.base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
-		.irq = MX1_GPIO_INT_PORTD,
-		.virtual_irq_start = MXC_GPIO_IRQ_START + 96,
-	}
-};
-
-int __init imx1_register_gpios(void)
-{
-	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
-}
diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h
deleted file mode 100644
index 1332516..0000000
--- a/arch/arm/mach-mx1/devices.h
+++ /dev/null
@@ -1,7 +0,0 @@
-extern struct platform_device imx1_camera_device;
-extern struct platform_device imx_i2c_device0;
-extern struct platform_device imx1_uart_device0;
-extern struct platform_device imx1_uart_device1;
-extern struct platform_device imx_rtc_device;
-extern struct platform_device imx_wdt_device;
-extern struct platform_device imx_usb_device;
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-mx1/generic.c
deleted file mode 100644
index a9be5f1..0000000
--- a/arch/arm/mach-mx1/generic.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- *  author: Sascha Hauer
- *  Created: april 20th, 2004
- *  Copyright: Synertronixx GmbH
- *
- *  Common code for i.MX machines
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-
-static struct map_desc imx_io_desc[] __initdata = {
-	{
-		.virtual = MX1_IO_BASE_ADDR_VIRT,
-		.pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
-		.length = MX1_IO_SIZE,
-		.type = MT_DEVICE
-	}
-};
-
-void __init mx1_map_io(void)
-{
-	mxc_set_cpu_type(MXC_CPU_MX1);
-	mxc_arch_reset_init(MX1_IO_ADDRESS(MX1_WDT_BASE_ADDR));
-
-	iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
-}
-
-int imx1_register_gpios(void);
-
-void __init mx1_init_irq(void)
-{
-	imx1_register_gpios();
-	mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
-}
diff --git a/arch/arm/mach-mx1/ksym_mx1.c b/arch/arm/mach-mx1/ksym_mx1.c
deleted file mode 100644
index b09ee12..0000000
--- a/arch/arm/mach-mx1/ksym_mx1.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Exported ksyms of ARCH_MX1
- *
- * Copyright (C) 2008, Darius Augulis <augulis.darius at gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/platform_device.h>
-#include <linux/module.h>
-
-#include <mach/mx1_camera.h>
-
-/* IMX camera FIQ handler */
-EXPORT_SYMBOL(mx1_camera_sof_fiq_start);
-EXPORT_SYMBOL(mx1_camera_sof_fiq_end);
diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c
deleted file mode 100644
index 5d7c85f..0000000
--- a/arch/arm/mach-mx1/mach-mx1ads.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * arch/arm/mach-imx/mach-mx1ads.c
- *
- * Initially based on:
- *	linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
- *	Copyright (c) 2004 Sascha Hauer <sascha at saschahauer.de>
- *
- * 2004 (c) MontaVista Software, Inc.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/i2c.h>
-#include <linux/i2c/pcf857x.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/i2c.h>
-#include <mach/imx-uart.h>
-#include <mach/iomux-mx1.h>
-#include <mach/irqs.h>
-
-#include "devices.h"
-
-static int mx1ads_pins[] = {
-	/* UART1 */
-	PC9_PF_UART1_CTS,
-	PC10_PF_UART1_RTS,
-	PC11_PF_UART1_TXD,
-	PC12_PF_UART1_RXD,
-	/* UART2 */
-	PB28_PF_UART2_CTS,
-	PB29_PF_UART2_RTS,
-	PB30_PF_UART2_TXD,
-	PB31_PF_UART2_RXD,
-	/* I2C */
-	PA15_PF_I2C_SDA,
-	PA16_PF_I2C_SCL,
-	/* SPI */
-	PC13_PF_SPI1_SPI_RDY,
-	PC14_PF_SPI1_SCLK,
-	PC15_PF_SPI1_SS,
-	PC16_PF_SPI1_MISO,
-	PC17_PF_SPI1_MOSI,
-};
-
-/*
- * UARTs platform data
- */
-
-static struct imxuart_platform_data uart_pdata[] = {
-	{
-		.flags = IMXUART_HAVE_RTSCTS,
-	}, {
-		.flags = IMXUART_HAVE_RTSCTS,
-	},
-};
-
-/*
- * Physmap flash
- */
-
-static struct physmap_flash_data mx1ads_flash_data = {
-	.width		= 4,		/* bankwidth in bytes */
-};
-
-static struct resource flash_resource = {
-	.start	= MX1_CS0_PHYS,
-	.end	= MX1_CS0_PHYS + SZ_32M - 1,
-	.flags	= IORESOURCE_MEM,
-};
-
-static struct platform_device flash_device = {
-	.name	= "physmap-flash",
-	.id	= 0,
-	.resource = &flash_resource,
-	.num_resources = 1,
-};
-
-/*
- * I2C
- */
-static struct pcf857x_platform_data pcf857x_data[] = {
-	{
-		.gpio_base = 4 * 32,
-	}, {
-		.gpio_base = 4 * 32 + 16,
-	}
-};
-
-static struct imxi2c_platform_data mx1ads_i2c_data = {
-	.bitrate = 100000,
-};
-
-static struct i2c_board_info mx1ads_i2c_devices[] = {
-	{
-		I2C_BOARD_INFO("pcf8575", 0x22),
-		.platform_data = &pcf857x_data[0],
-	}, {
-		I2C_BOARD_INFO("pcf8575", 0x24),
-		.platform_data = &pcf857x_data[1],
-	},
-};
-
-/*
- * Board init
- */
-static void __init mx1ads_init(void)
-{
-	mxc_gpio_setup_multiple_pins(mx1ads_pins,
-		ARRAY_SIZE(mx1ads_pins), "mx1ads");
-
-	/* UART */
-	mxc_register_device(&imx1_uart_device0, &uart_pdata[0]);
-	mxc_register_device(&imx1_uart_device1, &uart_pdata[1]);
-
-	/* Physmap flash */
-	mxc_register_device(&flash_device, &mx1ads_flash_data);
-
-	/* I2C */
-	i2c_register_board_info(0, mx1ads_i2c_devices,
-				ARRAY_SIZE(mx1ads_i2c_devices));
-
-	mxc_register_device(&imx_i2c_device0, &mx1ads_i2c_data);
-}
-
-static void __init mx1ads_timer_init(void)
-{
-	mx1_clocks_init(32000);
-}
-
-struct sys_timer mx1ads_timer = {
-	.init	= mx1ads_timer_init,
-};
-
-MACHINE_START(MX1ADS, "Freescale MX1ADS")
-	/* Maintainer: Sascha Hauer, Pengutronix */
-	.phys_io	= MX1_IO_BASE_ADDR,
-	.io_pg_offst	= (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
-	.boot_params	= MX1_PHYS_OFFSET + 0x100,
-	.map_io		= mx1_map_io,
-	.init_irq	= mx1_init_irq,
-	.timer		= &mx1ads_timer,
-	.init_machine	= mx1ads_init,
-MACHINE_END
-
-MACHINE_START(MXLADS, "Freescale MXLADS")
-	.phys_io	= MX1_IO_BASE_ADDR,
-	.io_pg_offst	= (MX1_IO_BASE_ADDR_VIRT >> 18) & 0xfffc,
-	.boot_params	= MX1_PHYS_OFFSET + 0x100,
-	.map_io		= mx1_map_io,
-	.init_irq	= mx1_init_irq,
-	.timer		= &mx1ads_timer,
-	.init_machine	= mx1ads_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx1/mach-scb9328.c b/arch/arm/mach-mx1/mach-scb9328.c
deleted file mode 100644
index 482b24d..0000000
--- a/arch/arm/mach-mx1/mach-scb9328.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * linux/arch/arm/mach-mx1/mach-scb9328.c
- *
- * Copyright (c) 2004 Sascha Hauer <saschahauer at web.de>
- * Copyright (c) 2006-2008 Juergen Beisert <jbeisert at netscape.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/interrupt.h>
-#include <linux/dm9000.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <mach/imx-uart.h>
-#include <mach/iomux-mx1.h>
-
-#include "devices.h"
-
-/*
- * This scb9328 has a 32MiB flash
- */
-static struct resource flash_resource = {
-	.start	= MX1_CS0_PHYS,
-	.end	= MX1_CS0_PHYS + (32 * 1024 * 1024) - 1,
-	.flags	= IORESOURCE_MEM,
-};
-
-static struct physmap_flash_data scb_flash_data = {
-	.width  = 2,
-};
-
-static struct platform_device scb_flash_device = {
-	.name		= "physmap-flash",
-	.id		= 0,
-	.dev = {
-		.platform_data = &scb_flash_data,
-	},
-	.resource = &flash_resource,
-	.num_resources = 1,
-};
-
-/*
- * scb9328 has a DM9000 network controller
- * connected to CS5, with 16 bit data path
- * and interrupt connected to GPIO 3
- */
-
-/*
- * internal datapath is fixed 16 bit
- */
-static struct dm9000_plat_data dm9000_platdata = {
-	.flags	= DM9000_PLATF_16BITONLY,
-};
-
-/*
- * the DM9000 drivers wants two defined address spaces
- * to gain access to address latch registers and the data path.
- */
-static struct resource dm9000x_resources[] = {
-	{
-		.name	= "address area",
-		.start	= MX1_CS5_PHYS,
-		.end	= MX1_CS5_PHYS + 1,
-		.flags	= IORESOURCE_MEM,	/* address access */
-	}, {
-		.name	= "data area",
-		.start	= MX1_CS5_PHYS + 4,
-		.end	= MX1_CS5_PHYS + 5,
-		.flags	= IORESOURCE_MEM,	/* data access */
-	}, {
-		.start	= IRQ_GPIOC(3),
-		.end	= IRQ_GPIOC(3),
-		.flags	= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
-	},
-};
-
-static struct platform_device dm9000x_device = {
-	.name		= "dm9000",
-	.id		= 0,
-	.num_resources	= ARRAY_SIZE(dm9000x_resources),
-	.resource	= dm9000x_resources,
-	.dev		= {
-		.platform_data = &dm9000_platdata,
-	}
-};
-
-static int mxc_uart1_pins[] = {
-	PC9_PF_UART1_CTS,
-	PC10_PF_UART1_RTS,
-	PC11_PF_UART1_TXD,
-	PC12_PF_UART1_RXD,
-};
-
-static int uart1_mxc_init(struct platform_device *pdev)
-{
-	return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
-			ARRAY_SIZE(mxc_uart1_pins), "UART1");
-}
-
-static void uart1_mxc_exit(struct platform_device *pdev)
-{
-	mxc_gpio_release_multiple_pins(mxc_uart1_pins,
-			ARRAY_SIZE(mxc_uart1_pins));
-}
-
-static struct imxuart_platform_data uart_pdata = {
-	.init = uart1_mxc_init,
-	.exit = uart1_mxc_exit,
-	.flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct platform_device *devices[] __initdata = {
-	&scb_flash_device,
-	&dm9000x_device,
-};
-
-/*
- * scb9328_init - Init the CPU card itself
- */
-static void __init scb9328_init(void)
-{
-	mxc_register_device(&imx1_uart_device0, &uart_pdata);
-
-	printk(KERN_INFO"Scb9328: Adding devices\n");
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init scb9328_timer_init(void)
-{
-	mx1_clocks_init(32000);
-}
-
-static struct sys_timer scb9328_timer = {
-	.init	= scb9328_timer_init,
-};
-
-MACHINE_START(SCB9328, "Synertronixx scb9328")
-    /* Sascha Hauer */
-	.phys_io	= 0x00200000,
-	.io_pg_offst	= ((0xe0200000) >> 18) & 0xfffc,
-	.boot_params	= 0x08000100,
-	.map_io		= mx1_map_io,
-	.init_irq	= mx1_init_irq,
-	.timer		= &scb9328_timer,
-	.init_machine	= scb9328_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx1/mx1_camera_fiq.S b/arch/arm/mach-mx1/mx1_camera_fiq.S
deleted file mode 100644
index 9c69aa6..0000000
--- a/arch/arm/mach-mx1/mx1_camera_fiq.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *  Copyright (C) 2008 Paulius Zaleckas <paulius.zaleckas at teltonika.lt>
- *
- *  Based on linux/arch/arm/lib/floppydma.S
- *      Copyright (C) 1995, 1996 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-
-		.text
-		.global	mx1_camera_sof_fiq_end
-		.global	mx1_camera_sof_fiq_start
-mx1_camera_sof_fiq_start:
-		@ enable dma
-		ldr	r12, [r9]
-		orr	r12, r12, #0x00000001
-		str	r12, [r9]
-		@ unmask DMA interrupt
-		ldr	r12, [r8]
-		bic	r12, r12, r13
-		str	r12, [r8]
-		@ disable SOF interrupt
-		ldr	r12, [r10]
-		bic	r12, r12, #0x00010000
-		str	r12, [r10]
-		@ clear SOF flag
-		mov	r12, #0x00010000
-		str	r12, [r11]
-		@ return from FIQ
-		subs	pc, lr, #4
-mx1_camera_sof_fiq_end:
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 4974fcc..3adad38 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -48,7 +48,6 @@ config ARCH_MX5
 
 endchoice
 
-source "arch/arm/mach-mx1/Kconfig"
 source "arch/arm/mach-imx/Kconfig"
 source "arch/arm/mach-mx3/Kconfig"
 source "arch/arm/mach-mx25/Kconfig"
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:51 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:51 +0200
Subject: [PATCH 55/61] ARM: imx: dynamically register imx-uart devices (imx1)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-56-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig            |    2 ++
 arch/arm/mach-imx/devices-imx1.h     |    5 +++++
 arch/arm/mach-imx/devices.c          |   31 -------------------------------
 arch/arm/mach-imx/devices.h          |    2 --
 arch/arm/mach-imx/mach-mx1ads.c      |   17 ++++++++---------
 arch/arm/mach-imx/mach-scb9328.c     |    6 +++---
 arch/arm/plat-mxc/include/mach/mx1.h |   24 ++++++++++++------------
 7 files changed, 30 insertions(+), 57 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index c185ec3..445ce10 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -17,11 +17,13 @@ config ARCH_MX1ADS
 	bool "MX1ADS platform"
 	select MACH_MXLADS
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_UART
 	help
 	  Say Y here if you are using Motorola MX1ADS/MXLADS boards
 
 config MACH_SCB9328
 	bool "Synertronixx scb9328"
+	select IMX_HAVE_PLATFORM_IMX_UART
 	help
 	  Say Y here if you are using a Synertronixx scb9328 board
 
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index a5cfe04..a8d94f0 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -11,3 +11,8 @@
 
 #define imx1_add_i2c_imx(pdata)		\
 	imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata)
+
+#define imx1_add_imx_uart0(pdata)	\
+	imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata)
+#define imx1_add_imx_uart1(pdata)	\
+	imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index 84e6da6..b4bf8fc 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -70,37 +70,6 @@ struct platform_device imx1_camera_device = {
 	.num_resources  = ARRAY_SIZE(imx1_camera_resources),
 };
 
-#define DEFINE_IMX1_UART_DEVICE(n, baseaddr, irqrx, irqtx, irqrts)	\
-	static struct resource imx1_uart_resources ## n[] = {		\
-		{							\
-			.start = baseaddr,				\
-			.end = baseaddr + 0xd0,				\
-			.flags = IORESOURCE_MEM,			\
-		}, {							\
-			.start = irqrx,					\
-			.end = irqrx,					\
-			.flags = IORESOURCE_IRQ,			\
-		}, {							\
-			.start = irqtx,					\
-			.end = irqtx,					\
-			.flags = IORESOURCE_IRQ,			\
-		}, {							\
-			.start = irqrts,				\
-			.end = irqrts,					\
-			.flags = IORESOURCE_IRQ,			\
-		},							\
-	};								\
-									\
-	struct platform_device imx1_uart_device ## n = {		\
-		.name = "imx-uart",					\
-		.id = n,						\
-		.num_resources = ARRAY_SIZE(imx1_uart_resources ## n),	\
-		.resource = imx1_uart_resources ## n,			\
-	}
-
-DEFINE_IMX1_UART_DEVICE(0, MX1_UART1_BASE_ADDR, MX1_UART1_MINT_RX, MX1_UART1_MINT_TX, MX1_UART1_MINT_RTS);
-DEFINE_IMX1_UART_DEVICE(1, MX1_UART2_BASE_ADDR, MX1_UART2_MINT_RX, MX1_UART2_MINT_TX, MX1_UART2_MINT_RTS);
-
 static struct resource imx_rtc_resources[] = {
 	{
 		.start  = 0x00204000,
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index db995b1..e56efbc 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -1,7 +1,5 @@
 #ifdef CONFIG_ARCH_MX1
 extern struct platform_device imx1_camera_device;
-extern struct platform_device imx1_uart_device0;
-extern struct platform_device imx1_uart_device1;
 extern struct platform_device imx_rtc_device;
 extern struct platform_device imx_wdt_device;
 extern struct platform_device imx_usb_device;
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 339d41a..77a760c 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -26,7 +26,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/i2c.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx1.h>
 #include <mach/irqs.h>
 
@@ -59,12 +58,12 @@ static int mx1ads_pins[] = {
  * UARTs platform data
  */
 
-static struct imxuart_platform_data uart_pdata[] = {
-	{
-		.flags = IMXUART_HAVE_RTSCTS,
-	}, {
-		.flags = IMXUART_HAVE_RTSCTS,
-	},
+static const struct imxuart_platform_data uart0_pdata __initconst = {
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+       
+static const struct imxuart_platform_data uart1_pdata __initconst = {
+	.flags = IMXUART_HAVE_RTSCTS,
 };
 
 /*
@@ -122,8 +121,8 @@ static void __init mx1ads_init(void)
 		ARRAY_SIZE(mx1ads_pins), "mx1ads");
 
 	/* UART */
-	mxc_register_device(&imx1_uart_device0, &uart_pdata[0]);
-	mxc_register_device(&imx1_uart_device1, &uart_pdata[1]);
+	imx1_add_imx_uart0(&uart0_pdata);
+	imx1_add_imx_uart1(&uart1_pdata);
 
 	/* Physmap flash */
 	mxc_register_device(&flash_device, &mx1ads_flash_data);
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 482b24d..88bf0d1 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -22,9 +22,9 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx1.h>
 
+#include "devices-imx1.h"
 #include "devices.h"
 
 /*
@@ -114,7 +114,7 @@ static void uart1_mxc_exit(struct platform_device *pdev)
 			ARRAY_SIZE(mxc_uart1_pins));
 }
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.init = uart1_mxc_init,
 	.exit = uart1_mxc_exit,
 	.flags = IMXUART_HAVE_RTSCTS,
@@ -130,7 +130,7 @@ static struct platform_device *devices[] __initdata = {
  */
 static void __init scb9328_init(void)
 {
-	mxc_register_device(&imx1_uart_device0, &uart_pdata);
+	imx1_add_imx_uart0(&uart_pdata);
 
 	printk(KERN_INFO"Scb9328: Adding devices\n");
 	platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index e99c0b2..641b246 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -91,18 +91,18 @@
 #define MX1_SIM_DATA_INT	16
 #define MX1_RTC_INT		17
 #define MX1_RTC_SAMINT		18
-#define MX1_UART2_MINT_PFERR	19
-#define MX1_UART2_MINT_RTS	20
-#define MX1_UART2_MINT_DTR	21
-#define MX1_UART2_MINT_UARTC	22
-#define MX1_UART2_MINT_TX	23
-#define MX1_UART2_MINT_RX	24
-#define MX1_UART1_MINT_PFERR	25
-#define MX1_UART1_MINT_RTS	26
-#define MX1_UART1_MINT_DTR	27
-#define MX1_UART1_MINT_UARTC	28
-#define MX1_UART1_MINT_TX	29
-#define MX1_UART1_MINT_RX	30
+#define MX1_INT_UART2PFERR	19
+#define MX1_INT_UART2RTS	20
+#define MX1_INT_UART2DTR	21
+#define MX1_INT_UART2UARTC	22
+#define MX1_INT_UART2TX		23
+#define MX1_INT_UART2RX		24
+#define MX1_INT_UART1PFERR	25
+#define MX1_INT_UART1RTS	26
+#define MX1_INT_UART1DTR	27
+#define MX1_INT_UART1UARTC	28
+#define MX1_INT_UART1TX		29
+#define MX1_INT_UART1RX		30
 #define MX1_VOICE_DAC_INT	31
 #define MX1_VOICE_ADC_INT	32
 #define MX1_PEN_DATA_INT	33
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:11 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:11 +0200
Subject: [PATCH 15/61] ARM: imx/mx1: fold crm_regs.h into its only consumer
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-16-git-send-email-u.kleine-koenig@pengutronix.de>

As crm_regs.h is GPL-v2 only don't allow "(at your option) any later
version" for clock.c any more.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx1/clock.c    |   47 ++++++++++++++++++++++++++++++-----
 arch/arm/mach-mx1/crm_regs.h |   55 ------------------------------------------
 2 files changed, 40 insertions(+), 62 deletions(-)
 delete mode 100644 arch/arm/mach-mx1/crm_regs.h

diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
index 610b88d..c05096c 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-mx1/clock.c
@@ -2,18 +2,17 @@
  *  Copyright (C) 2008 Sascha Hauer <s.hauer at pengutronix.de>, Pengutronix
  *
  * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
  */
 
 #include <linux/kernel.h>
@@ -29,7 +28,41 @@
 #include <mach/clock.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include "crm_regs.h"
+
+#define IO_ADDR_CCM(off)	(MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR + (off)))
+
+/* CCM register addresses */
+#define CCM_CSCR	IO_ADDR_CCM(0x0)
+#define CCM_MPCTL0	IO_ADDR_CCM(0x4)
+#define CCM_SPCTL0	IO_ADDR_CCM(0xc)
+#define CCM_PCDR	IO_ADDR_CCM(0x20)
+
+#define CCM_CSCR_CLKO_OFFSET	29
+#define CCM_CSCR_CLKO_MASK	(0x7 << 29)
+#define CCM_CSCR_USB_OFFSET	26
+#define CCM_CSCR_USB_MASK	(0x7 << 26)
+#define CCM_CSCR_OSC_EN_SHIFT	17
+#define CCM_CSCR_SYSTEM_SEL	(1 << 16)
+#define CCM_CSCR_BCLK_OFFSET	10
+#define CCM_CSCR_BCLK_MASK	(0xf << 10)
+#define CCM_CSCR_PRESC		(1 << 15)
+
+#define CCM_PCDR_PCLK3_OFFSET	16
+#define CCM_PCDR_PCLK3_MASK	(0x7f << 16)
+#define CCM_PCDR_PCLK2_OFFSET	4
+#define CCM_PCDR_PCLK2_MASK	(0xf << 4)
+#define CCM_PCDR_PCLK1_OFFSET	0
+#define CCM_PCDR_PCLK1_MASK	0xf
+
+#define IO_ADDR_SCM(off)	(MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR + (off)))
+
+/* SCM register addresses */
+#define SCM_GCCR	IO_ADDR_SCM(0xc)
+
+#define SCM_GCCR_DMA_CLK_EN_OFFSET	3
+#define SCM_GCCR_CSI_CLK_EN_OFFSET	2
+#define SCM_GCCR_MMA_CLK_EN_OFFSET	1
+#define SCM_GCCR_USBD_CLK_EN_OFFSET	0
 
 static int _clk_enable(struct clk *clk)
 {
diff --git a/arch/arm/mach-mx1/crm_regs.h b/arch/arm/mach-mx1/crm_regs.h
deleted file mode 100644
index 13e81e6..0000000
--- a/arch/arm/mach-mx1/crm_regs.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas at teltonika.lt>
- *
- * This file may be distributed under the terms of the GNU General
- * Public License, version 2.
- */
-
-#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__
-#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__
-
-#define CCM_BASE	MX1_IO_ADDRESS(MX1_CCM_BASE_ADDR)
-#define SCM_BASE	MX1_IO_ADDRESS(MX1_SCM_BASE_ADDR)
-
-/* CCM register addresses */
-#define CCM_CSCR	(CCM_BASE + 0x0)
-#define CCM_MPCTL0	(CCM_BASE + 0x4)
-#define CCM_MPCTL1	(CCM_BASE + 0x8)
-#define CCM_SPCTL0	(CCM_BASE + 0xC)
-#define CCM_SPCTL1	(CCM_BASE + 0x10)
-#define CCM_PCDR	(CCM_BASE + 0x20)
-
-#define CCM_CSCR_CLKO_OFFSET	29
-#define CCM_CSCR_CLKO_MASK	(0x7 << 29)
-#define CCM_CSCR_USB_OFFSET	26
-#define CCM_CSCR_USB_MASK	(0x7 << 26)
-#define CCM_CSCR_SPLL_RESTART	(1 << 22)
-#define CCM_CSCR_MPLL_RESTART	(1 << 21)
-#define CCM_CSCR_OSC_EN_SHIFT	17
-#define CCM_CSCR_SYSTEM_SEL	(1 << 16)
-#define CCM_CSCR_BCLK_OFFSET	10
-#define CCM_CSCR_BCLK_MASK	(0xF << 10)
-#define CCM_CSCR_PRESC		(1 << 15)
-#define CCM_CSCR_SPEN		(1 << 1)
-#define CCM_CSCR_MPEN		(1 << 0)
-
-#define CCM_PCDR_PCLK3_OFFSET	16
-#define CCM_PCDR_PCLK3_MASK	(0x7F << 16)
-#define CCM_PCDR_PCLK2_OFFSET	4
-#define CCM_PCDR_PCLK2_MASK	(0xF << 4)
-#define CCM_PCDR_PCLK1_OFFSET	0
-#define CCM_PCDR_PCLK1_MASK	0xF
-
-/* SCM register addresses */
-#define SCM_SIDR	(SCM_BASE + 0x0)
-#define SCM_FMCR	(SCM_BASE + 0x4)
-#define SCM_GPCR	(SCM_BASE + 0x8)
-#define SCM_GCCR	(SCM_BASE + 0xC)
-
-#define SCM_GCCR_DMA_CLK_EN_OFFSET	3
-#define SCM_GCCR_CSI_CLK_EN_OFFSET	2
-#define SCM_GCCR_MMA_CLK_EN_OFFSET	1
-#define SCM_GCCR_USBD_CLK_EN_OFFSET	0
-
-#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:27 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:27 +0200
Subject: [PATCH 31/61] ARM: mx25: remove paragraphs with old address of the FSF
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-32-git-send-email-u.kleine-koenig@pengutronix.de>

As the kernel contains a copy of the GPL anyhow just get rid of the address
specification instead of fixing it.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx25/mm.c |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-mx25/mm.c
index cf4d76e..593e145 100644
--- a/arch/arm/mach-mx25/mm.c
+++ b/arch/arm/mach-mx25/mm.c
@@ -14,10 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/mm.h>
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:15 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:15 +0200
Subject: [PATCH 19/61] ARM: imx1: rename imx_i2c_device to follow a common
	naming scheme
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-20-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx1/devices.c     |    2 +-
 arch/arm/mach-mx1/devices.h     |    2 +-
 arch/arm/mach-mx1/mach-mx1ads.c |    2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
index fa3809d..c770aa0 100644
--- a/arch/arm/mach-mx1/devices.c
+++ b/arch/arm/mach-mx1/devices.c
@@ -66,7 +66,7 @@ static struct resource imx_i2c_resources[] = {
 	},
 };
 
-struct platform_device imx_i2c_device = {
+struct platform_device imx_i2c_device0 = {
 	.name           = "imx-i2c",
 	.id             = 0,
 	.resource       = imx_i2c_resources,
diff --git a/arch/arm/mach-mx1/devices.h b/arch/arm/mach-mx1/devices.h
index 899f8d9..851d6df 100644
--- a/arch/arm/mach-mx1/devices.h
+++ b/arch/arm/mach-mx1/devices.h
@@ -1,5 +1,5 @@
 extern struct platform_device imx1_camera_device;
-extern struct platform_device imx_i2c_device;
+extern struct platform_device imx_i2c_device0;
 extern struct platform_device imx_uart1_device;
 extern struct platform_device imx_uart2_device;
 extern struct platform_device imx_rtc_device;
diff --git a/arch/arm/mach-mx1/mach-mx1ads.c b/arch/arm/mach-mx1/mach-mx1ads.c
index 27c8222..16adc61 100644
--- a/arch/arm/mach-mx1/mach-mx1ads.c
+++ b/arch/arm/mach-mx1/mach-mx1ads.c
@@ -131,7 +131,7 @@ static void __init mx1ads_init(void)
 	i2c_register_board_info(0, mx1ads_i2c_devices,
 				ARRAY_SIZE(mx1ads_i2c_devices));
 
-	mxc_register_device(&imx_i2c_device, &mx1ads_i2c_data);
+	mxc_register_device(&imx_i2c_device0, &mx1ads_i2c_data);
 }
 
 static void __init mx1ads_timer_init(void)
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:29 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:29 +0200
Subject: [PATCH 33/61] ARM: mxc91231: remove paragraphs with old address of
	the FSF
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-34-git-send-email-u.kleine-koenig@pengutronix.de>

As the kernel contains a copy of the GPL anyhow just get rid of the address
specification instead of fixing it.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mxc91231/crm_regs.h |    5 -----
 arch/arm/mach-mxc91231/mm.c       |    5 -----
 2 files changed, 0 insertions(+), 10 deletions(-)

diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
index ce4f590..b989bac 100644
--- a/arch/arm/mach-mxc91231/crm_regs.h
+++ b/arch/arm/mach-mxc91231/crm_regs.h
@@ -11,11 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
  */
 
 #ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
index 1f23c74..aeccfd7 100644
--- a/arch/arm/mach-mxc91231/mm.c
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -15,11 +15,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- *
  */
 
 #include <linux/mm.h>
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:23 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:23 +0200
Subject: [PATCH 27/61] ARM: imx: new Kconfig symbol and feature test macro for
	DMA on mx1 and mx2
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-28-git-send-email-u.kleine-koenig@pengutronix.de>

This should be used instead of hard coding the corresponding platforms.
The feature test macro is needed to support different SOCs in a single
kernel image.  While at it rename dma-mx1-mx2 to dma-v1 as mx25 doesn't
use it and so the mx2 part is wrong and move the header to
arch/arm/mach-imx.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig                    |    6 +
 arch/arm/mach-imx/Makefile                   |    2 +
 arch/arm/mach-imx/dma-v1.c                   |  863 ++++++++++++++++++++++++++
 arch/arm/mach-imx/include/mach/dma-mx1-mx2.h |   10 +
 arch/arm/mach-imx/include/mach/dma-v1.h      |  107 ++++
 arch/arm/plat-mxc/Makefile                   |    2 -
 arch/arm/plat-mxc/dma-mx1-mx2.c              |  863 --------------------------
 arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h |  105 ----
 8 files changed, 988 insertions(+), 970 deletions(-)
 create mode 100644 arch/arm/mach-imx/dma-v1.c
 create mode 100644 arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
 create mode 100644 arch/arm/mach-imx/include/mach/dma-v1.h
 delete mode 100644 arch/arm/plat-mxc/dma-mx1-mx2.c
 delete mode 100644 arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 5edead2..73c70af 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,7 +1,11 @@
+config IMX_HAVE_DMA_V1
+	bool
+
 if ARCH_MX1
 
 config SOC_IMX1
 	select CPU_ARM920T
+	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	bool
 
@@ -27,12 +31,14 @@ if ARCH_MX2
 config SOC_IMX21
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
+	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	bool
 
 config SOC_IMX27
 	select CPU_ARM926T
 	select ARCH_MXC_AUDMUX_V1
+	select IMX_HAVE_DMA_V1
 	select IMX_HAVE_IOMUX_V1
 	bool
 
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e56a119..86b53e6 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -6,6 +6,8 @@
 
 obj-y	:=  devices.o
 
+obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
+
 obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
 obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
 
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
new file mode 100644
index 0000000..fd1d919
--- /dev/null
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -0,0 +1,863 @@
+/*
+ *  linux/arch/arm/plat-mxc/dma-v1.c
+ *
+ *  i.MX DMA registration and IRQ dispatching
+ *
+ * Copyright 2006 Pavel Pisa <pisa at cmp.felk.cvut.cz>
+ * Copyright 2008 Juergen Beisert, <kernel at pengutronix.de>
+ * Copyright 2008 Sascha Hauer, <s.hauer at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/scatterlist.h>
+#include <linux/io.h>
+
+#include <asm/system.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <mach/dma-v1.h>
+
+#define DMA_DCR     0x00		/* Control Register */
+#define DMA_DISR    0x04		/* Interrupt status Register */
+#define DMA_DIMR    0x08		/* Interrupt mask Register */
+#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
+#define DMA_DRTOSR  0x10		/* Request timeout Register */
+#define DMA_DSESR   0x14		/* Transfer Error Status Register */
+#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
+#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
+#define DMA_WSRA    0x40		/* W-Size Register A */
+#define DMA_XSRA    0x44		/* X-Size Register A */
+#define DMA_YSRA    0x48		/* Y-Size Register A */
+#define DMA_WSRB    0x4c		/* W-Size Register B */
+#define DMA_XSRB    0x50		/* X-Size Register B */
+#define DMA_YSRB    0x54		/* Y-Size Register B */
+#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
+#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
+#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
+#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
+#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
+#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
+#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
+#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
+#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */
+
+#define DCR_DRST           (1<<1)
+#define DCR_DEN            (1<<0)
+#define DBTOCR_EN          (1<<15)
+#define DBTOCR_CNT(x)      ((x) & 0x7fff)
+#define CNTR_CNT(x)        ((x) & 0xffffff)
+#define CCR_ACRPT          (1<<14)
+#define CCR_DMOD_LINEAR    (0x0 << 12)
+#define CCR_DMOD_2D        (0x1 << 12)
+#define CCR_DMOD_FIFO      (0x2 << 12)
+#define CCR_DMOD_EOBFIFO   (0x3 << 12)
+#define CCR_SMOD_LINEAR    (0x0 << 10)
+#define CCR_SMOD_2D        (0x1 << 10)
+#define CCR_SMOD_FIFO      (0x2 << 10)
+#define CCR_SMOD_EOBFIFO   (0x3 << 10)
+#define CCR_MDIR_DEC       (1<<9)
+#define CCR_MSEL_B         (1<<8)
+#define CCR_DSIZ_32        (0x0 << 6)
+#define CCR_DSIZ_8         (0x1 << 6)
+#define CCR_DSIZ_16        (0x2 << 6)
+#define CCR_SSIZ_32        (0x0 << 4)
+#define CCR_SSIZ_8         (0x1 << 4)
+#define CCR_SSIZ_16        (0x2 << 4)
+#define CCR_REN            (1<<3)
+#define CCR_RPT            (1<<2)
+#define CCR_FRC            (1<<1)
+#define CCR_CEN            (1<<0)
+#define RTOR_EN            (1<<15)
+#define RTOR_CLK           (1<<14)
+#define RTOR_PSC           (1<<13)
+
+/*
+ * struct imx_dma_channel - i.MX specific DMA extension
+ * @name: name specified by DMA client
+ * @irq_handler: client callback for end of transfer
+ * @err_handler: client callback for error condition
+ * @data: clients context data for callbacks
+ * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
+ * @sg: pointer to the actual read/written chunk for scatter-gather emulation
+ * @resbytes: total residual number of bytes to transfer
+ *            (it can be lower or same as sum of SG mapped chunk sizes)
+ * @sgcount: number of chunks to be read/written
+ *
+ * Structure is used for IMX DMA processing. It would be probably good
+ * @struct dma_struct in the future for external interfacing and use
+ * @struct imx_dma_channel only as extension to it.
+ */
+
+struct imx_dma_channel {
+	const char *name;
+	void (*irq_handler) (int, void *);
+	void (*err_handler) (int, void *, int errcode);
+	void (*prog_handler) (int, void *, struct scatterlist *);
+	void *data;
+	unsigned int dma_mode;
+	struct scatterlist *sg;
+	unsigned int resbytes;
+	int dma_num;
+
+	int in_use;
+
+	u32 ccr_from_device;
+	u32 ccr_to_device;
+
+	struct timer_list watchdog;
+
+	int hw_chaining;
+};
+
+static void __iomem *imx_dmav1_baseaddr;
+
+static void imx_dmav1_writel(unsigned val, unsigned offset)
+{
+	__raw_writel(val, imx_dmav1_baseaddr + offset);
+}
+
+static unsigned imx_dmav1_readl(unsigned offset)
+{
+	return __raw_readl(imx_dmav1_baseaddr + offset);
+}
+
+static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
+
+static struct clk *dma_clk;
+
+static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
+{
+	if (cpu_is_mx27())
+		return imxdma->hw_chaining;
+	else
+		return 0;
+}
+
+/*
+ * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
+ */
+static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
+{
+	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+	unsigned long now;
+
+	if (!imxdma->name) {
+		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+		       __func__, channel);
+		return 0;
+	}
+
+	now = min(imxdma->resbytes, sg->length);
+	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
+		imxdma->resbytes -= now;
+
+	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
+		imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
+	else
+		imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
+
+	imx_dmav1_writel(now, DMA_CNTR(channel));
+
+	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
+		"size 0x%08x\n", channel,
+		 imx_dmav1_readl(DMA_DAR(channel)),
+		 imx_dmav1_readl(DMA_SAR(channel)),
+		 imx_dmav1_readl(DMA_CNTR(channel)));
+
+	return now;
+}
+
+/**
+ * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
+ * device transfer
+ *
+ * @channel: i.MX DMA channel number
+ * @dma_address: the DMA/physical memory address of the linear data block
+ *		to transfer
+ * @dma_length: length of the data block in bytes
+ * @dev_addr: physical device port address
+ * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
+ *           or %DMA_MODE_WRITE from memory to the device
+ *
+ * Return value: if incorrect parameters are provided -%EINVAL.
+ *		Zero indicates success.
+ */
+int
+imx_dma_setup_single(int channel, dma_addr_t dma_address,
+		     unsigned int dma_length, unsigned int dev_addr,
+		     unsigned int dmamode)
+{
+	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+
+	imxdma->sg = NULL;
+	imxdma->dma_mode = dmamode;
+
+	if (!dma_address) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if (!dma_length) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+			"dev_addr=0x%08x for read\n",
+			channel, __func__, (unsigned int)dma_address,
+			dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+		imx_dmav1_writel(dma_address, DMA_DAR(channel));
+		imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
+	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
+			"dev_addr=0x%08x for write\n",
+			channel, __func__, (unsigned int)dma_address,
+			dma_length, dev_addr);
+
+		imx_dmav1_writel(dma_address, DMA_SAR(channel));
+		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+		imx_dmav1_writel(imxdma->ccr_to_device,
+				DMA_CCR(channel));
+	} else {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
+
+	return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_single);
+
+/**
+ * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
+ * @channel: i.MX DMA channel number
+ * @sg: pointer to the scatter-gather list/vector
+ * @sgcount: scatter-gather list hungs count
+ * @dma_length: total length of the transfer request in bytes
+ * @dev_addr: physical device port address
+ * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
+ *           or %DMA_MODE_WRITE from memory to the device
+ *
+ * The function sets up DMA channel state and registers to be ready for
+ * transfer specified by provided parameters. The scatter-gather emulation
+ * is set up according to the parameters.
+ *
+ * The full preparation of the transfer requires setup of more register
+ * by the caller before imx_dma_enable() can be called.
+ *
+ * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
+ *
+ * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
+ *
+ * %CCR(channel) has to specify transfer parameters, the next settings is
+ * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
+ * specified
+ *
+ * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
+ *
+ * The typical setup for %DMA_MODE_WRITE is specified by next options
+ * combination
+ *
+ * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
+ *
+ * Be careful here and do not mistakenly mix source and target device
+ * port sizes constants, they are really different:
+ * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
+ * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
+ *
+ * Return value: if incorrect parameters are provided -%EINVAL.
+ * Zero indicates success.
+ */
+int
+imx_dma_setup_sg(int channel,
+		 struct scatterlist *sg, unsigned int sgcount,
+		 unsigned int dma_length, unsigned int dev_addr,
+		 unsigned int dmamode)
+{
+	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+
+	if (imxdma->in_use)
+		return -EBUSY;
+
+	imxdma->sg = sg;
+	imxdma->dma_mode = dmamode;
+	imxdma->resbytes = dma_length;
+
+	if (!sg || !sgcount) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if (!sg->length) {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
+		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+			"dev_addr=0x%08x for read\n",
+			channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
+		imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
+	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
+		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
+			"dev_addr=0x%08x for write\n",
+			channel, __func__, sg, sgcount, dma_length, dev_addr);
+
+		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
+		imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
+	} else {
+		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
+		       channel);
+		return -EINVAL;
+	}
+
+	imx_dma_sg_next(channel, sg);
+
+	return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_sg);
+
+int
+imx_dma_config_channel(int channel, unsigned int config_port,
+	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
+{
+	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+	u32 dreq = 0;
+
+	imxdma->hw_chaining = 0;
+
+	if (hw_chaining) {
+		imxdma->hw_chaining = 1;
+		if (!imx_dma_hw_chain(imxdma))
+			return -EINVAL;
+	}
+
+	if (dmareq)
+		dreq = CCR_REN;
+
+	imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
+	imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
+
+	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
+
+	return 0;
+}
+EXPORT_SYMBOL(imx_dma_config_channel);
+
+void imx_dma_config_burstlen(int channel, unsigned int burstlen)
+{
+	imx_dmav1_writel(burstlen, DMA_BLR(channel));
+}
+EXPORT_SYMBOL(imx_dma_config_burstlen);
+
+/**
+ * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
+ * handlers
+ * @channel: i.MX DMA channel number
+ * @irq_handler: the pointer to the function called if the transfer
+ *		ends successfully
+ * @err_handler: the pointer to the function called if the premature
+ *		end caused by error occurs
+ * @data: user specified value to be passed to the handlers
+ */
+int
+imx_dma_setup_handlers(int channel,
+		       void (*irq_handler) (int, void *),
+		       void (*err_handler) (int, void *, int),
+		       void *data)
+{
+	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+	unsigned long flags;
+
+	if (!imxdma->name) {
+		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+		       __func__, channel);
+		return -ENODEV;
+	}
+
+	local_irq_save(flags);
+	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imxdma->irq_handler = irq_handler;
+	imxdma->err_handler = err_handler;
+	imxdma->data = data;
+	local_irq_restore(flags);
+	return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_handlers);
+
+/**
+ * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
+ * handlers
+ * @channel: i.MX DMA channel number
+ * @prog_handler: the pointer to the function called if the transfer progresses
+ */
+int
+imx_dma_setup_progression_handler(int channel,
+			void (*prog_handler) (int, void*, struct scatterlist*))
+{
+	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+	unsigned long flags;
+
+	if (!imxdma->name) {
+		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+		       __func__, channel);
+		return -ENODEV;
+	}
+
+	local_irq_save(flags);
+	imxdma->prog_handler = prog_handler;
+	local_irq_restore(flags);
+	return 0;
+}
+EXPORT_SYMBOL(imx_dma_setup_progression_handler);
+
+/**
+ * imx_dma_enable - function to start i.MX DMA channel operation
+ * @channel: i.MX DMA channel number
+ *
+ * The channel has to be allocated by driver through imx_dma_request()
+ * or imx_dma_request_by_prio() function.
+ * The transfer parameters has to be set to the channel registers through
+ * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
+ * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
+ * be set prior this function call by the channel user.
+ */
+void imx_dma_enable(int channel)
+{
+	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+	unsigned long flags;
+
+	pr_debug("imxdma%d: imx_dma_enable\n", channel);
+
+	if (!imxdma->name) {
+		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
+		       __func__, channel);
+		return;
+	}
+
+	if (imxdma->in_use)
+		return;
+
+	local_irq_save(flags);
+
+	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
+		CCR_ACRPT, DMA_CCR(channel));
+
+#ifdef CONFIG_ARCH_MX2
+	if ((cpu_is_mx21() || cpu_is_mx27()) &&
+			imxdma->sg && imx_dma_hw_chain(imxdma)) {
+		imxdma->sg = sg_next(imxdma->sg);
+		if (imxdma->sg) {
+			u32 tmp;
+			imx_dma_sg_next(channel, imxdma->sg);
+			tmp = imx_dmav1_readl(DMA_CCR(channel));
+			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
+				DMA_CCR(channel));
+		}
+	}
+#endif
+	imxdma->in_use = 1;
+
+	local_irq_restore(flags);
+}
+EXPORT_SYMBOL(imx_dma_enable);
+
+/**
+ * imx_dma_disable - stop, finish i.MX DMA channel operatin
+ * @channel: i.MX DMA channel number
+ */
+void imx_dma_disable(int channel)
+{
+	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+	unsigned long flags;
+
+	pr_debug("imxdma%d: imx_dma_disable\n", channel);
+
+	if (imx_dma_hw_chain(imxdma))
+		del_timer(&imxdma->watchdog);
+
+	local_irq_save(flags);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
+	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
+			DMA_CCR(channel));
+	imx_dmav1_writel(1 << channel, DMA_DISR);
+	imxdma->in_use = 0;
+	local_irq_restore(flags);
+}
+EXPORT_SYMBOL(imx_dma_disable);
+
+#ifdef CONFIG_ARCH_MX2
+static void imx_dma_watchdog(unsigned long chno)
+{
+	struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
+
+	imx_dmav1_writel(0, DMA_CCR(chno));
+	imxdma->in_use = 0;
+	imxdma->sg = NULL;
+
+	if (imxdma->err_handler)
+		imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
+}
+#endif
+
+static irqreturn_t dma_err_handler(int irq, void *dev_id)
+{
+	int i, disr;
+	struct imx_dma_channel *imxdma;
+	unsigned int err_mask;
+	int errcode;
+
+	disr = imx_dmav1_readl(DMA_DISR);
+
+	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
+		   imx_dmav1_readl(DMA_DRTOSR) |
+		   imx_dmav1_readl(DMA_DSESR)  |
+		   imx_dmav1_readl(DMA_DBOSR);
+
+	if (!err_mask)
+		return IRQ_HANDLED;
+
+	imx_dmav1_writel(disr & err_mask, DMA_DISR);
+
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+		if (!(err_mask & (1 << i)))
+			continue;
+		imxdma = &imx_dma_channels[i];
+		errcode = 0;
+
+		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DBTOSR);
+			errcode |= IMX_DMA_ERR_BURST;
+		}
+		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DRTOSR);
+			errcode |= IMX_DMA_ERR_REQUEST;
+		}
+		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DSESR);
+			errcode |= IMX_DMA_ERR_TRANSFER;
+		}
+		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
+			imx_dmav1_writel(1 << i, DMA_DBOSR);
+			errcode |= IMX_DMA_ERR_BUFFER;
+		}
+		if (imxdma->name && imxdma->err_handler) {
+			imxdma->err_handler(i, imxdma->data, errcode);
+			continue;
+		}
+
+		imx_dma_channels[i].sg = NULL;
+
+		printk(KERN_WARNING
+		       "DMA timeout on channel %d (%s) -%s%s%s%s\n",
+		       i, imxdma->name,
+		       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
+		       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
+		       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
+		       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
+	}
+	return IRQ_HANDLED;
+}
+
+static void dma_irq_handle_channel(int chno)
+{
+	struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
+
+	if (!imxdma->name) {
+		/*
+		 * IRQ for an unregistered DMA channel:
+		 * let's clear the interrupts and disable it.
+		 */
+		printk(KERN_WARNING
+		       "spurious IRQ for DMA channel %d\n", chno);
+		return;
+	}
+
+	if (imxdma->sg) {
+		u32 tmp;
+		struct scatterlist *current_sg = imxdma->sg;
+		imxdma->sg = sg_next(imxdma->sg);
+
+		if (imxdma->sg) {
+			imx_dma_sg_next(chno, imxdma->sg);
+
+			tmp = imx_dmav1_readl(DMA_CCR(chno));
+
+			if (imx_dma_hw_chain(imxdma)) {
+				/* FIXME: The timeout should probably be
+				 * configurable
+				 */
+				mod_timer(&imxdma->watchdog,
+					jiffies + msecs_to_jiffies(500));
+
+				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
+				imx_dmav1_writel(tmp, DMA_CCR(chno));
+			} else {
+				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
+				tmp |= CCR_CEN;
+			}
+
+			imx_dmav1_writel(tmp, DMA_CCR(chno));
+
+			if (imxdma->prog_handler)
+				imxdma->prog_handler(chno, imxdma->data,
+						current_sg);
+
+			return;
+		}
+
+		if (imx_dma_hw_chain(imxdma)) {
+			del_timer(&imxdma->watchdog);
+			return;
+		}
+	}
+
+	imx_dmav1_writel(0, DMA_CCR(chno));
+	imxdma->in_use = 0;
+	if (imxdma->irq_handler)
+		imxdma->irq_handler(chno, imxdma->data);
+}
+
+static irqreturn_t dma_irq_handler(int irq, void *dev_id)
+{
+	int i, disr;
+
+#ifdef CONFIG_ARCH_MX2
+	if (cpu_is_mx21() || cpu_is_mx27())
+		dma_err_handler(irq, dev_id);
+#endif
+
+	disr = imx_dmav1_readl(DMA_DISR);
+
+	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
+		     disr);
+
+	imx_dmav1_writel(disr, DMA_DISR);
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+		if (disr & (1 << i))
+			dma_irq_handle_channel(i);
+	}
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * imx_dma_request - request/allocate specified channel number
+ * @channel: i.MX DMA channel number
+ * @name: the driver/caller own non-%NULL identification
+ */
+int imx_dma_request(int channel, const char *name)
+{
+	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+	unsigned long flags;
+	int ret = 0;
+
+	/* basic sanity checks */
+	if (!name)
+		return -EINVAL;
+
+	if (channel >= IMX_DMA_CHANNELS) {
+		printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
+		       __func__, channel);
+		return -EINVAL;
+	}
+
+	local_irq_save(flags);
+	if (imxdma->name) {
+		local_irq_restore(flags);
+		return -EBUSY;
+	}
+	memset(imxdma, 0, sizeof(imxdma));
+	imxdma->name = name;
+	local_irq_restore(flags); /* request_irq() can block */
+
+#ifdef CONFIG_ARCH_MX2
+	if (cpu_is_mx21() || cpu_is_mx27()) {
+		ret = request_irq(MX2x_INT_DMACH0 + channel,
+				dma_irq_handler, 0, "DMA", NULL);
+		if (ret) {
+			imxdma->name = NULL;
+			pr_crit("Can't register IRQ %d for DMA channel %d\n",
+					MX2x_INT_DMACH0 + channel, channel);
+			return ret;
+		}
+		init_timer(&imxdma->watchdog);
+		imxdma->watchdog.function = &imx_dma_watchdog;
+		imxdma->watchdog.data = channel;
+	}
+#endif
+
+	return ret;
+}
+EXPORT_SYMBOL(imx_dma_request);
+
+/**
+ * imx_dma_free - release previously acquired channel
+ * @channel: i.MX DMA channel number
+ */
+void imx_dma_free(int channel)
+{
+	unsigned long flags;
+	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
+
+	if (!imxdma->name) {
+		printk(KERN_CRIT
+		       "%s: trying to free free channel %d\n",
+		       __func__, channel);
+		return;
+	}
+
+	local_irq_save(flags);
+	/* Disable interrupts */
+	imx_dma_disable(channel);
+	imxdma->name = NULL;
+
+#ifdef CONFIG_ARCH_MX2
+	if (cpu_is_mx21() || cpu_is_mx27())
+		free_irq(MX2x_INT_DMACH0 + channel, NULL);
+#endif
+
+	local_irq_restore(flags);
+}
+EXPORT_SYMBOL(imx_dma_free);
+
+/**
+ * imx_dma_request_by_prio - find and request some of free channels best
+ * suiting requested priority
+ * @channel: i.MX DMA channel number
+ * @name: the driver/caller own non-%NULL identification
+ *
+ * This function tries to find a free channel in the specified priority group
+ * This function tries to find a free channel in the specified priority group
+ * if the priority cannot be achieved it tries to look for free channel
+ * in the higher and then even lower priority groups.
+ *
+ * Return value: If there is no free channel to allocate, -%ENODEV is returned.
+ *               On successful allocation channel is returned.
+ */
+int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
+{
+	int i;
+	int best;
+
+	switch (prio) {
+	case (DMA_PRIO_HIGH):
+		best = 8;
+		break;
+	case (DMA_PRIO_MEDIUM):
+		best = 4;
+		break;
+	case (DMA_PRIO_LOW):
+	default:
+		best = 0;
+		break;
+	}
+
+	for (i = best; i < IMX_DMA_CHANNELS; i++)
+		if (!imx_dma_request(i, name))
+			return i;
+
+	for (i = best - 1; i >= 0; i--)
+		if (!imx_dma_request(i, name))
+			return i;
+
+	printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
+
+	return -ENODEV;
+}
+EXPORT_SYMBOL(imx_dma_request_by_prio);
+
+static int __init imx_dma_init(void)
+{
+	int ret = 0;
+	int i;
+
+#ifdef CONFIG_ARCH_MX1
+	if (cpu_is_mx1())
+		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
+	else
+#endif
+#ifdef CONFIG_MACH_MX21
+	if (cpu_is_mx21())
+		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
+	else
+#endif
+#ifdef CONFIG_MACH_MX27
+	if (cpu_is_mx27())
+		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
+	else
+#endif
+		BUG();
+
+	dma_clk = clk_get(NULL, "dma");
+	clk_enable(dma_clk);
+
+	/* reset DMA module */
+	imx_dmav1_writel(DCR_DRST, DMA_DCR);
+
+#ifdef CONFIG_ARCH_MX1
+	if (cpu_is_mx1()) {
+		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
+		if (ret) {
+			pr_crit("Wow!  Can't register IRQ for DMA\n");
+			return ret;
+		}
+
+		ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
+		if (ret) {
+			pr_crit("Wow!  Can't register ERRIRQ for DMA\n");
+			free_irq(MX1_DMA_INT, NULL);
+			return ret;
+		}
+	}
+#endif
+	/* enable DMA module */
+	imx_dmav1_writel(DCR_DEN, DMA_DCR);
+
+	/* clear all interrupts */
+	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
+
+	/* disable interrupts */
+	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
+
+	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
+		imx_dma_channels[i].sg = NULL;
+		imx_dma_channels[i].dma_num = i;
+	}
+
+	return ret;
+}
+
+arch_initcall(imx_dma_init);
diff --git a/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
new file mode 100644
index 0000000..df5f522
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/dma-mx1-mx2.h
@@ -0,0 +1,10 @@
+#ifndef __MACH_DMA_MX1_MX2_H__
+#define __MACH_DMA_MX1_MX2_H__
+/*
+ * Don't use this header in new code, it will go away when all users are
+ * converted to mach/dma-v1.h
+ */
+
+#include <mach/dma-v1.h>
+
+#endif /* ifndef __MACH_DMA_MX1_MX2_H__ */
diff --git a/arch/arm/mach-imx/include/mach/dma-v1.h b/arch/arm/mach-imx/include/mach/dma-v1.h
new file mode 100644
index 0000000..287431c
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/dma-v1.h
@@ -0,0 +1,107 @@
+/*
+ *  linux/arch/arm/mach-imx/include/mach/dma-v1.h
+ *
+ *  i.MX DMA registration and IRQ dispatching
+ *
+ * Copyright 2006 Pavel Pisa <pisa at cmp.felk.cvut.cz>
+ * Copyright 2008 Juergen Beisert, <kernel at pengutronix.de>
+ * Copyright 2008 Sascha Hauer, <s.hauer at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __MACH_DMA_V1_H__
+#define __MACH_DMA_V1_H__
+
+#define imx_has_dma_v1()	(cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
+
+#define IMX_DMA_CHANNELS  16
+
+#define DMA_MODE_READ		0
+#define DMA_MODE_WRITE		1
+#define DMA_MODE_MASK		1
+
+#define MX1_DMA_REG(offset)	MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
+
+/* DMA Interrupt Mask Register */
+#define MX1_DMA_DIMR		MX1_DMA_REG(0x08)
+
+/* Channel Control Register */
+#define MX1_DMA_CCR(x)		MX1_DMA_REG(0x8c + ((x) << 6))
+
+#define IMX_DMA_MEMSIZE_32	(0 << 4)
+#define IMX_DMA_MEMSIZE_8	(1 << 4)
+#define IMX_DMA_MEMSIZE_16	(2 << 4)
+#define IMX_DMA_TYPE_LINEAR	(0 << 10)
+#define IMX_DMA_TYPE_2D		(1 << 10)
+#define IMX_DMA_TYPE_FIFO	(2 << 10)
+
+#define IMX_DMA_ERR_BURST     (1 << 0)
+#define IMX_DMA_ERR_REQUEST   (1 << 1)
+#define IMX_DMA_ERR_TRANSFER  (1 << 2)
+#define IMX_DMA_ERR_BUFFER    (1 << 3)
+#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
+
+int
+imx_dma_config_channel(int channel, unsigned int config_port,
+	unsigned int config_mem, unsigned int dmareq, int hw_chaining);
+
+void
+imx_dma_config_burstlen(int channel, unsigned int burstlen);
+
+int
+imx_dma_setup_single(int channel, dma_addr_t dma_address,
+		unsigned int dma_length, unsigned int dev_addr,
+		unsigned int dmamode);
+
+
+/*
+ * Use this flag as the dma_length argument to imx_dma_setup_sg()
+ * to create an endless running dma loop. The end of the scatterlist
+ * must be linked to the beginning for this to work.
+ */
+#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
+
+int
+imx_dma_setup_sg(int channel, struct scatterlist *sg,
+		unsigned int sgcount, unsigned int dma_length,
+		unsigned int dev_addr, unsigned int dmamode);
+
+int
+imx_dma_setup_handlers(int channel,
+		void (*irq_handler) (int, void *),
+		void (*err_handler) (int, void *, int), void *data);
+
+int
+imx_dma_setup_progression_handler(int channel,
+		void (*prog_handler) (int, void*, struct scatterlist*));
+
+void imx_dma_enable(int channel);
+
+void imx_dma_disable(int channel);
+
+int imx_dma_request(int channel, const char *name);
+
+void imx_dma_free(int channel);
+
+enum imx_dma_prio {
+	DMA_PRIO_HIGH = 0,
+	DMA_PRIO_MEDIUM = 1,
+	DMA_PRIO_LOW = 2
+};
+
+int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
+
+#endif	/* __MACH_DMA_V1_H__ */
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 895bc3c..f134d14 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -8,8 +8,6 @@ obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o
 # MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o)
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 
-obj-$(CONFIG_ARCH_MX1) += dma-mx1-mx2.o
-obj-$(CONFIG_ARCH_MX2) += dma-mx1-mx2.o
 obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
 obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
 obj-$(CONFIG_MXC_PWM)  += pwm.o
diff --git a/arch/arm/plat-mxc/dma-mx1-mx2.c b/arch/arm/plat-mxc/dma-mx1-mx2.c
deleted file mode 100644
index e16014b..0000000
--- a/arch/arm/plat-mxc/dma-mx1-mx2.c
+++ /dev/null
@@ -1,863 +0,0 @@
-/*
- *  linux/arch/arm/plat-mxc/dma-mx1-mx2.c
- *
- *  i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa at cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel at pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/scatterlist.h>
-#include <linux/io.h>
-
-#include <asm/system.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/dma-mx1-mx2.h>
-
-#define DMA_DCR     0x00		/* Control Register */
-#define DMA_DISR    0x04		/* Interrupt status Register */
-#define DMA_DIMR    0x08		/* Interrupt mask Register */
-#define DMA_DBTOSR  0x0c		/* Burst timeout status Register */
-#define DMA_DRTOSR  0x10		/* Request timeout Register */
-#define DMA_DSESR   0x14		/* Transfer Error Status Register */
-#define DMA_DBOSR   0x18		/* Buffer overflow status Register */
-#define DMA_DBTOCR  0x1c		/* Burst timeout control Register */
-#define DMA_WSRA    0x40		/* W-Size Register A */
-#define DMA_XSRA    0x44		/* X-Size Register A */
-#define DMA_YSRA    0x48		/* Y-Size Register A */
-#define DMA_WSRB    0x4c		/* W-Size Register B */
-#define DMA_XSRB    0x50		/* X-Size Register B */
-#define DMA_YSRB    0x54		/* Y-Size Register B */
-#define DMA_SAR(x)  (0x80 + ((x) << 6))	/* Source Address Registers */
-#define DMA_DAR(x)  (0x84 + ((x) << 6))	/* Destination Address Registers */
-#define DMA_CNTR(x) (0x88 + ((x) << 6))	/* Count Registers */
-#define DMA_CCR(x)  (0x8c + ((x) << 6))	/* Control Registers */
-#define DMA_RSSR(x) (0x90 + ((x) << 6))	/* Request source select Registers */
-#define DMA_BLR(x)  (0x94 + ((x) << 6))	/* Burst length Registers */
-#define DMA_RTOR(x) (0x98 + ((x) << 6))	/* Request timeout Registers */
-#define DMA_BUCR(x) (0x98 + ((x) << 6))	/* Bus Utilization Registers */
-#define DMA_CCNR(x) (0x9C + ((x) << 6))	/* Channel counter Registers */
-
-#define DCR_DRST           (1<<1)
-#define DCR_DEN            (1<<0)
-#define DBTOCR_EN          (1<<15)
-#define DBTOCR_CNT(x)      ((x) & 0x7fff)
-#define CNTR_CNT(x)        ((x) & 0xffffff)
-#define CCR_ACRPT          (1<<14)
-#define CCR_DMOD_LINEAR    (0x0 << 12)
-#define CCR_DMOD_2D        (0x1 << 12)
-#define CCR_DMOD_FIFO      (0x2 << 12)
-#define CCR_DMOD_EOBFIFO   (0x3 << 12)
-#define CCR_SMOD_LINEAR    (0x0 << 10)
-#define CCR_SMOD_2D        (0x1 << 10)
-#define CCR_SMOD_FIFO      (0x2 << 10)
-#define CCR_SMOD_EOBFIFO   (0x3 << 10)
-#define CCR_MDIR_DEC       (1<<9)
-#define CCR_MSEL_B         (1<<8)
-#define CCR_DSIZ_32        (0x0 << 6)
-#define CCR_DSIZ_8         (0x1 << 6)
-#define CCR_DSIZ_16        (0x2 << 6)
-#define CCR_SSIZ_32        (0x0 << 4)
-#define CCR_SSIZ_8         (0x1 << 4)
-#define CCR_SSIZ_16        (0x2 << 4)
-#define CCR_REN            (1<<3)
-#define CCR_RPT            (1<<2)
-#define CCR_FRC            (1<<1)
-#define CCR_CEN            (1<<0)
-#define RTOR_EN            (1<<15)
-#define RTOR_CLK           (1<<14)
-#define RTOR_PSC           (1<<13)
-
-/*
- * struct imx_dma_channel - i.MX specific DMA extension
- * @name: name specified by DMA client
- * @irq_handler: client callback for end of transfer
- * @err_handler: client callback for error condition
- * @data: clients context data for callbacks
- * @dma_mode: direction of the transfer %DMA_MODE_READ or %DMA_MODE_WRITE
- * @sg: pointer to the actual read/written chunk for scatter-gather emulation
- * @resbytes: total residual number of bytes to transfer
- *            (it can be lower or same as sum of SG mapped chunk sizes)
- * @sgcount: number of chunks to be read/written
- *
- * Structure is used for IMX DMA processing. It would be probably good
- * @struct dma_struct in the future for external interfacing and use
- * @struct imx_dma_channel only as extension to it.
- */
-
-struct imx_dma_channel {
-	const char *name;
-	void (*irq_handler) (int, void *);
-	void (*err_handler) (int, void *, int errcode);
-	void (*prog_handler) (int, void *, struct scatterlist *);
-	void *data;
-	unsigned int dma_mode;
-	struct scatterlist *sg;
-	unsigned int resbytes;
-	int dma_num;
-
-	int in_use;
-
-	u32 ccr_from_device;
-	u32 ccr_to_device;
-
-	struct timer_list watchdog;
-
-	int hw_chaining;
-};
-
-static void __iomem *imx_dmav1_baseaddr;
-
-static void imx_dmav1_writel(unsigned val, unsigned offset)
-{
-	__raw_writel(val, imx_dmav1_baseaddr + offset);
-}
-
-static unsigned imx_dmav1_readl(unsigned offset)
-{
-	return __raw_readl(imx_dmav1_baseaddr + offset);
-}
-
-static struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
-
-static struct clk *dma_clk;
-
-static int imx_dma_hw_chain(struct imx_dma_channel *imxdma)
-{
-	if (cpu_is_mx27())
-		return imxdma->hw_chaining;
-	else
-		return 0;
-}
-
-/*
- * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
- */
-static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long now;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return 0;
-	}
-
-	now = min(imxdma->resbytes, sg->length);
-	if (imxdma->resbytes != IMX_DMA_LENGTH_LOOP)
-		imxdma->resbytes -= now;
-
-	if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
-		imx_dmav1_writel(sg->dma_address, DMA_DAR(channel));
-	else
-		imx_dmav1_writel(sg->dma_address, DMA_SAR(channel));
-
-	imx_dmav1_writel(now, DMA_CNTR(channel));
-
-	pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, "
-		"size 0x%08x\n", channel,
-		 imx_dmav1_readl(DMA_DAR(channel)),
-		 imx_dmav1_readl(DMA_SAR(channel)),
-		 imx_dmav1_readl(DMA_CNTR(channel)));
-
-	return now;
-}
-
-/**
- * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from
- * device transfer
- *
- * @channel: i.MX DMA channel number
- * @dma_address: the DMA/physical memory address of the linear data block
- *		to transfer
- * @dma_length: length of the data block in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- *           or %DMA_MODE_WRITE from memory to the device
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- *		Zero indicates success.
- */
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
-		     unsigned int dma_length, unsigned int dev_addr,
-		     unsigned int dmamode)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	imxdma->sg = NULL;
-	imxdma->dma_mode = dmamode;
-
-	if (!dma_address) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!dma_length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(dma_address, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s dma_addressg=0x%08x dma_length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, (unsigned int)dma_address,
-			dma_length, dev_addr);
-
-		imx_dmav1_writel(dma_address, DMA_SAR(channel));
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_to_device,
-				DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imx_dmav1_writel(dma_length, DMA_CNTR(channel));
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_single);
-
-/**
- * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
- * @channel: i.MX DMA channel number
- * @sg: pointer to the scatter-gather list/vector
- * @sgcount: scatter-gather list hungs count
- * @dma_length: total length of the transfer request in bytes
- * @dev_addr: physical device port address
- * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
- *           or %DMA_MODE_WRITE from memory to the device
- *
- * The function sets up DMA channel state and registers to be ready for
- * transfer specified by provided parameters. The scatter-gather emulation
- * is set up according to the parameters.
- *
- * The full preparation of the transfer requires setup of more register
- * by the caller before imx_dma_enable() can be called.
- *
- * %BLR(channel) holds transfer burst length in bytes, 0 means 64 bytes
- *
- * %RSSR(channel) has to be set to the DMA request line source %DMA_REQ_xxx
- *
- * %CCR(channel) has to specify transfer parameters, the next settings is
- * typical for linear or simple scatter-gather transfers if %DMA_MODE_READ is
- * specified
- *
- * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
- *
- * The typical setup for %DMA_MODE_WRITE is specified by next options
- * combination
- *
- * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
- *
- * Be careful here and do not mistakenly mix source and target device
- * port sizes constants, they are really different:
- * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
- * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
- *
- * Return value: if incorrect parameters are provided -%EINVAL.
- * Zero indicates success.
- */
-int
-imx_dma_setup_sg(int channel,
-		 struct scatterlist *sg, unsigned int sgcount,
-		 unsigned int dma_length, unsigned int dev_addr,
-		 unsigned int dmamode)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	if (imxdma->in_use)
-		return -EBUSY;
-
-	imxdma->sg = sg;
-	imxdma->dma_mode = dmamode;
-	imxdma->resbytes = dma_length;
-
-	if (!sg || !sgcount) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if (!sg->length) {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for read\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_SAR(channel));
-		imx_dmav1_writel(imxdma->ccr_from_device, DMA_CCR(channel));
-	} else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
-		pr_debug("imxdma%d: %s sg=%p sgcount=%d total length=%d "
-			"dev_addr=0x%08x for write\n",
-			channel, __func__, sg, sgcount, dma_length, dev_addr);
-
-		imx_dmav1_writel(dev_addr, DMA_DAR(channel));
-		imx_dmav1_writel(imxdma->ccr_to_device, DMA_CCR(channel));
-	} else {
-		printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
-		       channel);
-		return -EINVAL;
-	}
-
-	imx_dma_sg_next(channel, sg);
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_sg);
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	u32 dreq = 0;
-
-	imxdma->hw_chaining = 0;
-
-	if (hw_chaining) {
-		imxdma->hw_chaining = 1;
-		if (!imx_dma_hw_chain(imxdma))
-			return -EINVAL;
-	}
-
-	if (dmareq)
-		dreq = CCR_REN;
-
-	imxdma->ccr_from_device = config_port | (config_mem << 2) | dreq;
-	imxdma->ccr_to_device = config_mem | (config_port << 2) | dreq;
-
-	imx_dmav1_writel(dmareq, DMA_RSSR(channel));
-
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_config_channel);
-
-void imx_dma_config_burstlen(int channel, unsigned int burstlen)
-{
-	imx_dmav1_writel(burstlen, DMA_BLR(channel));
-}
-EXPORT_SYMBOL(imx_dma_config_burstlen);
-
-/**
- * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification
- * handlers
- * @channel: i.MX DMA channel number
- * @irq_handler: the pointer to the function called if the transfer
- *		ends successfully
- * @err_handler: the pointer to the function called if the premature
- *		end caused by error occurs
- * @data: user specified value to be passed to the handlers
- */
-int
-imx_dma_setup_handlers(int channel,
-		       void (*irq_handler) (int, void *),
-		       void (*err_handler) (int, void *, int),
-		       void *data)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return -ENODEV;
-	}
-
-	local_irq_save(flags);
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdma->irq_handler = irq_handler;
-	imxdma->err_handler = err_handler;
-	imxdma->data = data;
-	local_irq_restore(flags);
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_handlers);
-
-/**
- * imx_dma_setup_progression_handler - setup i.MX DMA channel progression
- * handlers
- * @channel: i.MX DMA channel number
- * @prog_handler: the pointer to the function called if the transfer progresses
- */
-int
-imx_dma_setup_progression_handler(int channel,
-			void (*prog_handler) (int, void*, struct scatterlist*))
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return -ENODEV;
-	}
-
-	local_irq_save(flags);
-	imxdma->prog_handler = prog_handler;
-	local_irq_restore(flags);
-	return 0;
-}
-EXPORT_SYMBOL(imx_dma_setup_progression_handler);
-
-/**
- * imx_dma_enable - function to start i.MX DMA channel operation
- * @channel: i.MX DMA channel number
- *
- * The channel has to be allocated by driver through imx_dma_request()
- * or imx_dma_request_by_prio() function.
- * The transfer parameters has to be set to the channel registers through
- * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
- * and registers %BLR(channel), %RSSR(channel) and %CCR(channel) has to
- * be set prior this function call by the channel user.
- */
-void imx_dma_enable(int channel)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	pr_debug("imxdma%d: imx_dma_enable\n", channel);
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
-		       __func__, channel);
-		return;
-	}
-
-	if (imxdma->in_use)
-		return;
-
-	local_irq_save(flags);
-
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) & ~(1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
-		CCR_ACRPT, DMA_CCR(channel));
-
-#ifdef CONFIG_ARCH_MX2
-	if ((cpu_is_mx21() || cpu_is_mx27()) &&
-			imxdma->sg && imx_dma_hw_chain(imxdma)) {
-		imxdma->sg = sg_next(imxdma->sg);
-		if (imxdma->sg) {
-			u32 tmp;
-			imx_dma_sg_next(channel, imxdma->sg);
-			tmp = imx_dmav1_readl(DMA_CCR(channel));
-			imx_dmav1_writel(tmp | CCR_RPT | CCR_ACRPT,
-				DMA_CCR(channel));
-		}
-	}
-#endif
-	imxdma->in_use = 1;
-
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_enable);
-
-/**
- * imx_dma_disable - stop, finish i.MX DMA channel operatin
- * @channel: i.MX DMA channel number
- */
-void imx_dma_disable(int channel)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-
-	pr_debug("imxdma%d: imx_dma_disable\n", channel);
-
-	if (imx_dma_hw_chain(imxdma))
-		del_timer(&imxdma->watchdog);
-
-	local_irq_save(flags);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_DIMR) | (1 << channel), DMA_DIMR);
-	imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) & ~CCR_CEN,
-			DMA_CCR(channel));
-	imx_dmav1_writel(1 << channel, DMA_DISR);
-	imxdma->in_use = 0;
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_disable);
-
-#ifdef CONFIG_ARCH_MX2
-static void imx_dma_watchdog(unsigned long chno)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
-	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
-	imxdma->sg = NULL;
-
-	if (imxdma->err_handler)
-		imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
-}
-#endif
-
-static irqreturn_t dma_err_handler(int irq, void *dev_id)
-{
-	int i, disr;
-	struct imx_dma_channel *imxdma;
-	unsigned int err_mask;
-	int errcode;
-
-	disr = imx_dmav1_readl(DMA_DISR);
-
-	err_mask = imx_dmav1_readl(DMA_DBTOSR) |
-		   imx_dmav1_readl(DMA_DRTOSR) |
-		   imx_dmav1_readl(DMA_DSESR)  |
-		   imx_dmav1_readl(DMA_DBOSR);
-
-	if (!err_mask)
-		return IRQ_HANDLED;
-
-	imx_dmav1_writel(disr & err_mask, DMA_DISR);
-
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (!(err_mask & (1 << i)))
-			continue;
-		imxdma = &imx_dma_channels[i];
-		errcode = 0;
-
-		if (imx_dmav1_readl(DMA_DBTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBTOSR);
-			errcode |= IMX_DMA_ERR_BURST;
-		}
-		if (imx_dmav1_readl(DMA_DRTOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DRTOSR);
-			errcode |= IMX_DMA_ERR_REQUEST;
-		}
-		if (imx_dmav1_readl(DMA_DSESR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DSESR);
-			errcode |= IMX_DMA_ERR_TRANSFER;
-		}
-		if (imx_dmav1_readl(DMA_DBOSR) & (1 << i)) {
-			imx_dmav1_writel(1 << i, DMA_DBOSR);
-			errcode |= IMX_DMA_ERR_BUFFER;
-		}
-		if (imxdma->name && imxdma->err_handler) {
-			imxdma->err_handler(i, imxdma->data, errcode);
-			continue;
-		}
-
-		imx_dma_channels[i].sg = NULL;
-
-		printk(KERN_WARNING
-		       "DMA timeout on channel %d (%s) -%s%s%s%s\n",
-		       i, imxdma->name,
-		       errcode & IMX_DMA_ERR_BURST ?    " burst" : "",
-		       errcode & IMX_DMA_ERR_REQUEST ?  " request" : "",
-		       errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
-		       errcode & IMX_DMA_ERR_BUFFER ?   " buffer" : "");
-	}
-	return IRQ_HANDLED;
-}
-
-static void dma_irq_handle_channel(int chno)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
-
-	if (!imxdma->name) {
-		/*
-		 * IRQ for an unregistered DMA channel:
-		 * let's clear the interrupts and disable it.
-		 */
-		printk(KERN_WARNING
-		       "spurious IRQ for DMA channel %d\n", chno);
-		return;
-	}
-
-	if (imxdma->sg) {
-		u32 tmp;
-		struct scatterlist *current_sg = imxdma->sg;
-		imxdma->sg = sg_next(imxdma->sg);
-
-		if (imxdma->sg) {
-			imx_dma_sg_next(chno, imxdma->sg);
-
-			tmp = imx_dmav1_readl(DMA_CCR(chno));
-
-			if (imx_dma_hw_chain(imxdma)) {
-				/* FIXME: The timeout should probably be
-				 * configurable
-				 */
-				mod_timer(&imxdma->watchdog,
-					jiffies + msecs_to_jiffies(500));
-
-				tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
-				imx_dmav1_writel(tmp, DMA_CCR(chno));
-			} else {
-				imx_dmav1_writel(tmp & ~CCR_CEN, DMA_CCR(chno));
-				tmp |= CCR_CEN;
-			}
-
-			imx_dmav1_writel(tmp, DMA_CCR(chno));
-
-			if (imxdma->prog_handler)
-				imxdma->prog_handler(chno, imxdma->data,
-						current_sg);
-
-			return;
-		}
-
-		if (imx_dma_hw_chain(imxdma)) {
-			del_timer(&imxdma->watchdog);
-			return;
-		}
-	}
-
-	imx_dmav1_writel(0, DMA_CCR(chno));
-	imxdma->in_use = 0;
-	if (imxdma->irq_handler)
-		imxdma->irq_handler(chno, imxdma->data);
-}
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
-	int i, disr;
-
-#ifdef CONFIG_ARCH_MX2
-	if (cpu_is_mx21() || cpu_is_mx27())
-		dma_err_handler(irq, dev_id);
-#endif
-
-	disr = imx_dmav1_readl(DMA_DISR);
-
-	pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
-		     disr);
-
-	imx_dmav1_writel(disr, DMA_DISR);
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		if (disr & (1 << i))
-			dma_irq_handle_channel(i);
-	}
-
-	return IRQ_HANDLED;
-}
-
-/**
- * imx_dma_request - request/allocate specified channel number
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- */
-int imx_dma_request(int channel, const char *name)
-{
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-	unsigned long flags;
-	int ret = 0;
-
-	/* basic sanity checks */
-	if (!name)
-		return -EINVAL;
-
-	if (channel >= IMX_DMA_CHANNELS) {
-		printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
-		       __func__, channel);
-		return -EINVAL;
-	}
-
-	local_irq_save(flags);
-	if (imxdma->name) {
-		local_irq_restore(flags);
-		return -EBUSY;
-	}
-	memset(imxdma, 0, sizeof(imxdma));
-	imxdma->name = name;
-	local_irq_restore(flags); /* request_irq() can block */
-
-#ifdef CONFIG_ARCH_MX2
-	if (cpu_is_mx21() || cpu_is_mx27()) {
-		ret = request_irq(MX2x_INT_DMACH0 + channel,
-				dma_irq_handler, 0, "DMA", NULL);
-		if (ret) {
-			imxdma->name = NULL;
-			pr_crit("Can't register IRQ %d for DMA channel %d\n",
-					MX2x_INT_DMACH0 + channel, channel);
-			return ret;
-		}
-		init_timer(&imxdma->watchdog);
-		imxdma->watchdog.function = &imx_dma_watchdog;
-		imxdma->watchdog.data = channel;
-	}
-#endif
-
-	return ret;
-}
-EXPORT_SYMBOL(imx_dma_request);
-
-/**
- * imx_dma_free - release previously acquired channel
- * @channel: i.MX DMA channel number
- */
-void imx_dma_free(int channel)
-{
-	unsigned long flags;
-	struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
-
-	if (!imxdma->name) {
-		printk(KERN_CRIT
-		       "%s: trying to free free channel %d\n",
-		       __func__, channel);
-		return;
-	}
-
-	local_irq_save(flags);
-	/* Disable interrupts */
-	imx_dma_disable(channel);
-	imxdma->name = NULL;
-
-#ifdef CONFIG_ARCH_MX2
-	if (cpu_is_mx21() || cpu_is_mx27())
-		free_irq(MX2x_INT_DMACH0 + channel, NULL);
-#endif
-
-	local_irq_restore(flags);
-}
-EXPORT_SYMBOL(imx_dma_free);
-
-/**
- * imx_dma_request_by_prio - find and request some of free channels best
- * suiting requested priority
- * @channel: i.MX DMA channel number
- * @name: the driver/caller own non-%NULL identification
- *
- * This function tries to find a free channel in the specified priority group
- * This function tries to find a free channel in the specified priority group
- * if the priority cannot be achieved it tries to look for free channel
- * in the higher and then even lower priority groups.
- *
- * Return value: If there is no free channel to allocate, -%ENODEV is returned.
- *               On successful allocation channel is returned.
- */
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio)
-{
-	int i;
-	int best;
-
-	switch (prio) {
-	case (DMA_PRIO_HIGH):
-		best = 8;
-		break;
-	case (DMA_PRIO_MEDIUM):
-		best = 4;
-		break;
-	case (DMA_PRIO_LOW):
-	default:
-		best = 0;
-		break;
-	}
-
-	for (i = best; i < IMX_DMA_CHANNELS; i++)
-		if (!imx_dma_request(i, name))
-			return i;
-
-	for (i = best - 1; i >= 0; i--)
-		if (!imx_dma_request(i, name))
-			return i;
-
-	printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
-
-	return -ENODEV;
-}
-EXPORT_SYMBOL(imx_dma_request_by_prio);
-
-static int __init imx_dma_init(void)
-{
-	int ret = 0;
-	int i;
-
-#ifdef CONFIG_ARCH_MX1
-	if (cpu_is_mx1())
-		imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
-	else
-#endif
-#ifdef CONFIG_MACH_MX21
-	if (cpu_is_mx21())
-		imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
-	else
-#endif
-#ifdef CONFIG_MACH_MX27
-	if (cpu_is_mx27())
-		imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
-	else
-#endif
-		BUG();
-
-	dma_clk = clk_get(NULL, "dma");
-	clk_enable(dma_clk);
-
-	/* reset DMA module */
-	imx_dmav1_writel(DCR_DRST, DMA_DCR);
-
-#ifdef CONFIG_ARCH_MX1
-	if (cpu_is_mx1()) {
-		ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
-		if (ret) {
-			pr_crit("Wow!  Can't register IRQ for DMA\n");
-			return ret;
-		}
-
-		ret = request_irq(MX1_DMA_ERR, dma_err_handler, 0, "DMA", NULL);
-		if (ret) {
-			pr_crit("Wow!  Can't register ERRIRQ for DMA\n");
-			free_irq(MX1_DMA_INT, NULL);
-			return ret;
-		}
-	}
-#endif
-	/* enable DMA module */
-	imx_dmav1_writel(DCR_DEN, DMA_DCR);
-
-	/* clear all interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
-
-	/* disable interrupts */
-	imx_dmav1_writel((1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
-
-	for (i = 0; i < IMX_DMA_CHANNELS; i++) {
-		imx_dma_channels[i].sg = NULL;
-		imx_dma_channels[i].dma_num = i;
-	}
-
-	return ret;
-}
-
-arch_initcall(imx_dma_init);
diff --git a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h b/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
deleted file mode 100644
index 7c4870b..0000000
--- a/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- *  linux/arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
- *
- *  i.MX DMA registration and IRQ dispatching
- *
- * Copyright 2006 Pavel Pisa <pisa at cmp.felk.cvut.cz>
- * Copyright 2008 Juergen Beisert, <kernel at pengutronix.de>
- * Copyright 2008 Sascha Hauer, <s.hauer at pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_DMA_H
-#define __ASM_ARCH_MXC_DMA_H
-
-#define IMX_DMA_CHANNELS  16
-
-#define DMA_MODE_READ		0
-#define DMA_MODE_WRITE		1
-#define DMA_MODE_MASK		1
-
-#define MX1_DMA_REG(offset)	MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR + (offset))
-
-/* DMA Interrupt Mask Register */
-#define MX1_DMA_DIMR		MX1_DMA_REG(0x08)
-
-/* Channel Control Register */
-#define MX1_DMA_CCR(x)		MX1_DMA_REG(0x8c + ((x) << 6))
-
-#define IMX_DMA_MEMSIZE_32	(0 << 4)
-#define IMX_DMA_MEMSIZE_8	(1 << 4)
-#define IMX_DMA_MEMSIZE_16	(2 << 4)
-#define IMX_DMA_TYPE_LINEAR	(0 << 10)
-#define IMX_DMA_TYPE_2D		(1 << 10)
-#define IMX_DMA_TYPE_FIFO	(2 << 10)
-
-#define IMX_DMA_ERR_BURST     (1 << 0)
-#define IMX_DMA_ERR_REQUEST   (1 << 1)
-#define IMX_DMA_ERR_TRANSFER  (1 << 2)
-#define IMX_DMA_ERR_BUFFER    (1 << 3)
-#define IMX_DMA_ERR_TIMEOUT   (1 << 4)
-
-int
-imx_dma_config_channel(int channel, unsigned int config_port,
-	unsigned int config_mem, unsigned int dmareq, int hw_chaining);
-
-void
-imx_dma_config_burstlen(int channel, unsigned int burstlen);
-
-int
-imx_dma_setup_single(int channel, dma_addr_t dma_address,
-		unsigned int dma_length, unsigned int dev_addr,
-		unsigned int dmamode);
-
-
-/*
- * Use this flag as the dma_length argument to imx_dma_setup_sg()
- * to create an endless running dma loop. The end of the scatterlist
- * must be linked to the beginning for this to work.
- */
-#define IMX_DMA_LENGTH_LOOP	((unsigned int)-1)
-
-int
-imx_dma_setup_sg(int channel, struct scatterlist *sg,
-		unsigned int sgcount, unsigned int dma_length,
-		unsigned int dev_addr, unsigned int dmamode);
-
-int
-imx_dma_setup_handlers(int channel,
-		void (*irq_handler) (int, void *),
-		void (*err_handler) (int, void *, int), void *data);
-
-int
-imx_dma_setup_progression_handler(int channel,
-		void (*prog_handler) (int, void*, struct scatterlist*));
-
-void imx_dma_enable(int channel);
-
-void imx_dma_disable(int channel);
-
-int imx_dma_request(int channel, const char *name);
-
-void imx_dma_free(int channel);
-
-enum imx_dma_prio {
-	DMA_PRIO_HIGH = 0,
-	DMA_PRIO_MEDIUM = 1,
-	DMA_PRIO_LOW = 2
-};
-
-int imx_dma_request_by_prio(const char *name, enum imx_dma_prio prio);
-
-#endif	/* _ASM_ARCH_MXC_DMA_H */
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:38 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:38 +0200
Subject: [PATCH 42/61] ARM: imx: dynamically register imx-i2c devices (imx1)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-43-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig            |    1 +
 arch/arm/mach-imx/devices-imx1.h     |   13 +++++++++++++
 arch/arm/mach-imx/devices.c          |   19 -------------------
 arch/arm/mach-imx/devices.h          |    1 -
 arch/arm/mach-imx/mach-mx1ads.c      |    5 +++--
 arch/arm/plat-mxc/include/mach/mx1.h |    4 ++--
 6 files changed, 19 insertions(+), 24 deletions(-)
 create mode 100644 arch/arm/mach-imx/devices-imx1.h

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 5af1c22..3f88d4a 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -16,6 +16,7 @@ config MACH_MXLADS
 config ARCH_MX1ADS
 	bool "MX1ADS platform"
 	select MACH_MXLADS
+	select IMX_HAVE_PLATFORM_IMX_I2C
 	help
 	  Say Y here if you are using Motorola MX1ADS/MXLADS boards
 
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
new file mode 100644
index 0000000..a5cfe04
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx1.h>
+#include <mach/devices-common.h>
+
+#define imx1_add_i2c_imx(pdata)		\
+	imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index 3a599e9..a34ad60 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -70,25 +70,6 @@ struct platform_device imx1_camera_device = {
 	.num_resources  = ARRAY_SIZE(imx1_camera_resources),
 };
 
-static struct resource imx_i2c_resources[] = {
-	{
-		.start  = 0x00217000,
-		.end    = 0x00217010,
-		.flags  = IORESOURCE_MEM,
-	}, {
-		.start  = MX1_I2C_INT,
-		.end    = MX1_I2C_INT,
-		.flags  = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device imx_i2c_device0 = {
-	.name           = "imx-i2c",
-	.id             = 0,
-	.resource       = imx_i2c_resources,
-	.num_resources  = ARRAY_SIZE(imx_i2c_resources),
-};
-
 #define DEFINE_IMX1_UART_DEVICE(n, baseaddr, irqrx, irqtx, irqrts)	\
 	static struct resource imx1_uart_resources ## n[] = {		\
 		{							\
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index 4ce7eef..b4eb8a0 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -1,6 +1,5 @@
 #ifdef CONFIG_ARCH_MX1
 extern struct platform_device imx1_camera_device;
-extern struct platform_device imx_i2c_device0;
 extern struct platform_device imx1_uart_device0;
 extern struct platform_device imx1_uart_device1;
 extern struct platform_device imx_rtc_device;
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 5d7c85f..339d41a 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -30,6 +30,7 @@
 #include <mach/iomux-mx1.h>
 #include <mach/irqs.h>
 
+#include "devices-imx1.h"
 #include "devices.h"
 
 static int mx1ads_pins[] = {
@@ -98,7 +99,7 @@ static struct pcf857x_platform_data pcf857x_data[] = {
 	}
 };
 
-static struct imxi2c_platform_data mx1ads_i2c_data = {
+static const struct imxi2c_platform_data mx1ads_i2c_data __initconst = {
 	.bitrate = 100000,
 };
 
@@ -131,7 +132,7 @@ static void __init mx1ads_init(void)
 	i2c_register_board_info(0, mx1ads_i2c_devices,
 				ARRAY_SIZE(mx1ads_i2c_devices));
 
-	mxc_register_device(&imx_i2c_device0, &mx1ads_i2c_data);
+	imx1_add_i2c_imx(&mx1ads_i2c_data);
 }
 
 static void __init mx1ads_timer_init(void)
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 5eba7e6..e99c0b2 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -108,7 +108,7 @@
 #define MX1_PEN_DATA_INT	33
 #define MX1_PWM_INT		34
 #define MX1_SDHC_INT		35
-#define MX1_I2C_INT		39
+#define MX1_INT_I2C		39
 #define MX1_CSPI_INT		41
 #define MX1_SSI_TX_INT		42
 #define MX1_SSI_TX_ERR_INT	43
@@ -245,7 +245,7 @@
 #define PEN_DATA_INT MX1_PEN_DATA_INT
 #define PWM_INT MX1_PWM_INT
 #define SDHC_INT MX1_SDHC_INT
-#define I2C_INT MX1_I2C_INT
+#define I2C_INT MX1_INT_I2C
 #define CSPI_INT MX1_CSPI_INT
 #define SSI_TX_INT MX1_SSI_TX_INT
 #define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:35 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:35 +0200
Subject: [PATCH 39/61] ARM: imx: Change the way nand devices are registered
	(imx31)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-40-git-send-email-u.kleine-koenig@pengutronix.de>

Make use of new mechanism to register a nand device.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/Kconfig             |    4 ++++
 arch/arm/mach-mx3/devices-imx31.h     |   13 +++++++++++++
 arch/arm/mach-mx3/devices.c           |    8 ++++++--
 arch/arm/mach-mx3/devices.h           |    2 ++
 arch/arm/mach-mx3/mach-armadillo5x0.c |    7 ++++---
 arch/arm/mach-mx3/mach-mx31_3ds.c     |    8 +++++---
 arch/arm/mach-mx3/mach-mx31lite.c     |    7 ++++---
 arch/arm/mach-mx3/mach-pcm037.c       |    7 ++++---
 8 files changed, 42 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/mach-mx3/devices-imx31.h

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 344753f..cb9368f 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -34,6 +34,7 @@ config MACH_MX31ADS_WM1133_EV1
 config MACH_PCM037
 	bool "Support Phytec pcm037 (i.MX31) platforms"
 	select ARCH_MX31
+	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
 	  Include support for Phytec pcm037 platform. This includes
@@ -51,6 +52,7 @@ config MACH_MX31LITE
 	bool "Support MX31 LITEKIT (LogicPD)"
 	select ARCH_MX31
 	select MXC_ULPI if USB_ULPI
+	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for MX31 LITEKIT platform. This includes specific
 	  configurations for the board and its peripherals.
@@ -58,6 +60,7 @@ config MACH_MX31LITE
 config MACH_MX31_3DS
 	bool "Support MX31PDK (3DS)"
 	select ARCH_MX31
+	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for MX31PDK (3DS) platform. This includes specific
 	  configurations for the board and its peripherals.
@@ -105,6 +108,7 @@ config MACH_PCM043
 config MACH_ARMADILLO5X0
 	bool "Support Atmark Armadillo-500 Development Base Board"
 	select ARCH_MX31
+	select IMX_HAVE_PLATFORM_MXC_NAND
 	select MXC_ULPI if USB_ULPI
 	help
 	  Include support for Atmark Armadillo-500 platform. This includes
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
new file mode 100644
index 0000000..8bd8b38
--- /dev/null
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx31.h>
+#include <mach/devices-common.h>
+
+#define imx31_add_mxc_nand(pdata)	\
+	imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index f6da0ff..baa4bd1 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -167,6 +167,7 @@ struct platform_device mxc_w1_master_device = {
 	.resource = mxc_w1_master_resources,
 };
 
+#if defined(CONFIG_ARCH_MX35)
 static struct resource mxc_nand_resources[] = {
 	{
 		.start	= 0, /* runtime dependent */
@@ -185,6 +186,7 @@ struct platform_device mxc_nand_device = {
 	.num_resources = ARRAY_SIZE(mxc_nand_resources),
 	.resource = mxc_nand_resources,
 };
+#endif
 
 static struct resource mxc_i2c0_resources[] = {
 	{
@@ -628,13 +630,14 @@ struct platform_device imx_kpp_device = {
 
 static int __init mx3_devices_init(void)
 {
+#if defined(CONFIG_ARCH_MX31)
 	if (cpu_is_mx31()) {
-		mxc_nand_resources[0].start = MX31_NFC_BASE_ADDR;
-		mxc_nand_resources[0].end = MX31_NFC_BASE_ADDR + 0xfff;
 		imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
 		imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
 		mxc_register_device(&mxc_rnga_device, NULL);
 	}
+#endif
+#if defined(CONFIG_ARCH_MX35)
 	if (cpu_is_mx35()) {
 		mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
 		mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0x1fff;
@@ -653,6 +656,7 @@ static int __init mx3_devices_init(void)
 		imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
 		imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
 	}
+#endif
 
 	return 0;
 }
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 2c3c864..6bb71d3 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -5,7 +5,9 @@ extern struct platform_device mxc_uart_device2;
 extern struct platform_device mxc_uart_device3;
 extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_w1_master_device;
+#if defined(CONFIG_ARCH_MX35)
 extern struct platform_device mxc_nand_device;
+#endif
 extern struct platform_device mxc_i2c_device0;
 extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_i2c_device2;
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index 2a8de89..633107a 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -53,10 +53,10 @@
 #include <mach/mmc.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 #include "crm_regs.h"
 
@@ -300,7 +300,8 @@ static struct platform_device armadillo5x0_button_device = {
 /*
  * NAND Flash
  */
-static struct mxc_nand_platform_data armadillo5x0_nand_flash_pdata = {
+static const struct mxc_nand_platform_data
+armadillo5x0_nand_board_info __initconst = {
 	.width		= 1,
 	.hw_ecc		= 1,
 };
@@ -531,7 +532,7 @@ static void __init armadillo5x0_init(void)
 			    &armadillo5x0_nor_flash_pdata);
 
 	/* Register NAND Flash */
-	mxc_register_device(&mxc_nand_device, &armadillo5x0_nand_flash_pdata);
+	imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
 
 	/* set NAND page size to 2k if not configured via boot mode pins */
 	__raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 33f2554..c730c09 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -35,8 +35,9 @@
 #include <mach/common.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
-#include <mach/mxc_nand.h>
 #include <mach/spi.h>
+
+#include "devices-imx31.h"
 #include "devices.h"
 
 /* Definitions for components on the Debug board */
@@ -189,7 +190,8 @@ static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
 /*
  * NAND Flash
  */
-static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
+static const struct mxc_nand_platform_data
+mx31_3ds_nand_board_info __initconst = {
 	.width		= 1,
 	.hw_ecc		= 1,
 #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
@@ -415,7 +417,7 @@ static void __init mxc_board_init(void)
 				      "mx31_3ds");
 
 	mxc_register_device(&mxc_uart_device0, &uart_pdata);
-	mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
+	imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
 
 	mxc_register_device(&mxc_spi_device1, &spi1_pdata);
 	spi_register_board_info(mx31_3ds_spi_devs,
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index edcc711..f0a68e6 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -41,11 +41,11 @@
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/irqs.h>
-#include <mach/mxc_nand.h>
 #include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -65,7 +65,8 @@ static unsigned int mx31lite_pins[] = {
 	MX31_PIN_CSPI2_SS2__SS2,
 };
 
-static struct mxc_nand_platform_data mx31lite_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx31lite_nand_board_info __initconst  = {
 	.width = 1,
 	.hw_ecc = 1,
 };
@@ -249,7 +250,7 @@ static void __init mxc_board_init(void)
 
 	/* NOR and NAND flash */
 	platform_device_register(&physmap_flash_device);
-	mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info);
+	imx31_add_mxc_nand(&mx31lite_nand_board_info);
 
 	mxc_register_device(&mxc_spi_device1, &spi1_pdata);
 	spi_register_board_info(&mc13783_spi_dev, 1);
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index c1f335c..d7fef46 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -48,10 +48,10 @@
 #include <mach/mmc.h>
 #include <mach/mx3_camera.h>
 #include <mach/mx3fb.h>
-#include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 #include "pcm037.h"
 
@@ -274,7 +274,8 @@ static struct platform_device pcm037_sram_device = {
 	.resource = &pcm038_sram_resource,
 };
 
-static struct mxc_nand_platform_data pcm037_nand_board_info = {
+static const struct mxc_nand_platform_data
+pcm037_nand_board_info __initconst = {
 	.width = 1,
 	.hw_ecc = 1,
 };
@@ -632,7 +633,7 @@ static void __init mxc_board_init(void)
 	mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
 	mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data);
 
-	mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
+	imx31_add_mxc_nand(&pcm037_nand_board_info);
 	mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
 	mxc_register_device(&mx3_ipu, &mx3_ipu_data);
 	mxc_register_device(&mx3_fb, &mx3fb_pdata);
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:39 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:39 +0200
Subject: [PATCH 43/61] ARM: imx: dynamically register imx-i2c devices (imx21)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-44-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/devices-imx21.h |    3 +++
 arch/arm/mach-imx/devices.c       |    2 +-
 arch/arm/mach-imx/devices.h       |    2 +-
 3 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index e85dcb1..c6e5f50 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -9,5 +9,8 @@
 #include <mach/mx21.h>
 #include <mach/devices-common.h>
 
+#define imx21_add_i2c_imx(pdata)	\
+	imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata)
+
 #define imx21_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index a34ad60..b9f5b69 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -368,6 +368,7 @@ struct platform_device mxc_fec_device = {
 };
 #endif
 
+#ifdef CONFIG_MACH_MX27
 #define DEFINE_IMX_I2C_DEVICE(n, baseaddr, irq)				\
 	static struct resource mxc_i2c_resources ## n[] = {		\
 		{							\
@@ -390,7 +391,6 @@ struct platform_device mxc_fec_device = {
 
 DEFINE_IMX_I2C_DEVICE(0, MX2x_I2C_BASE_ADDR, MX2x_INT_I2C);
 
-#ifdef CONFIG_MACH_MX27
 DEFINE_IMX_I2C_DEVICE(1, MX27_I2C2_BASE_ADDR, MX27_INT_I2C2);
 #endif
 
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index b4eb8a0..dcaa4f9 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -28,8 +28,8 @@ extern struct platform_device mxc_w1_master_device;
 extern struct platform_device mxc_fb_device;
 extern struct platform_device mxc_fec_device;
 extern struct platform_device mxc_pwm_device;
-extern struct platform_device mxc_i2c_device0;
 #ifdef CONFIG_MACH_MX27
+extern struct platform_device mxc_i2c_device0;
 extern struct platform_device mxc_i2c_device1;
 #endif
 extern struct platform_device mxc_sdhc_device0;
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:21 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:21 +0200
Subject: [PATCH 25/61] ARM: imx: prepare deprecating ARCH_MX1, MACH_MX2,
	MACH_MX21 and MACH_MX27
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-26-git-send-email-u.kleine-koenig@pengutronix.de>

MACH_... is reserved for machine support, so use SOC as prefix, not MACH.

This introduces new symbols SOC_IMX1, SOC_IMX21 and SOC_IMX27.  They are
selected by the old symbols for now.  There is no substitute for MACH_MX2
as most usages of MX2 only means MX21 + MX27 but not MX25.

Later the choice about CPU and CPU family should go away and the individual
machines should select the right SOC symbol.  This is a precondition to
support more than one SOC in a single kernel image.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig |   24 ++++++++++++++++++++++--
 arch/arm/plat-mxc/Kconfig |    5 +----
 2 files changed, 23 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3ca8fa7..08002df 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,5 +1,11 @@
 if ARCH_MX1
 
+config SOC_IMX1
+	select CPU_ARM920T
+	select IMX_HAVE_DMA_V1
+	select IMX_HAVE_IOMUX_V1
+	bool
+
 comment "MX1 platforms:"
 config MACH_MXLADS
 	bool
@@ -19,19 +25,33 @@ endif
 
 if ARCH_MX2
 
+config SOC_IMX21
+	select CPU_ARM926T
+	select ARCH_MXC_AUDMUX_V1
+	select IMX_HAVE_DMA_V1
+	select IMX_HAVE_IOMUX_V1
+	bool
+
+config SOC_IMX27
+	select CPU_ARM926T
+	select ARCH_MXC_AUDMUX_V1
+	select IMX_HAVE_DMA_V1
+	select IMX_HAVE_IOMUX_V1
+	bool
+
 choice
 	prompt "CPUs:"
 	default MACH_MX21
 
 config MACH_MX21
 	bool "i.MX21 support"
-	select ARCH_MXC_AUDMUX_V1
+	select SOC_IMX21
 	help
 	  This enables support for Freescale's MX2 based i.MX21 processor.
 
 config MACH_MX27
 	bool "i.MX27 support"
-	select ARCH_MXC_AUDMUX_V1
+	select SOC_IMX27
 	help
 	  This enables support for Freescale's MX2 based i.MX27 processor.
 
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 3adad38..d80de4e 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -8,15 +8,12 @@ choice
 
 config ARCH_MX1
 	bool "MX1-based"
-	select CPU_ARM920T
-	select IMX_HAVE_IOMUX_V1
+	select SOC_IMX1
 	help
 	  This enables support for systems based on the Freescale i.MX1 family
 
 config ARCH_MX2
 	bool "MX2-based"
-	select CPU_ARM926T
-	select IMX_HAVE_IOMUX_V1
 	help
 	  This enables support for systems based on the Freescale i.MX2 family
 
-- 
1.7.1



From sw1-arm-linux at gmx.de  Thu Jun 24 09:44:31 2010
From: sw1-arm-linux at gmx.de (Stefan)
Date: Thu, 24 Jun 2010 15:44:31 +0200
Subject: NXP LPC3250 LCD controller
Message-ID: <201006241544.32140.sw1-arm-linux@gmx.de>

Hi,

there is an errata for NXP LPC3250 LCD controller.

****
3.4 LCD.1: Low throughput when LCD controller accesses DDR/SDRAM

Introduction:
The LCD controller is an AHB Master that uses an internal DMA controller
to transfer frame data from memory to the LCD panel.

Problem:
The time required to read data from either SDR or DDR SDRAM using the
LCD DMA controller takes longer than expected. ...
****

Does anybody know whether LCD with greater resolution then QVGA will 
definitely not work? 
(I'll use 480x272 24Bit) 

Or is there something I could fine tune in memory arbiter?

Has somebody a lager LCD than QVGA running on Linux with this SOC?

Thanks in advance 
Stefan


From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:48:57 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:48:57 +0200
Subject: [PATCH 01/61] ARM: mx3: rename mach-mx35pdk.c to mach-mx35_3ds.c
	matching its arch number
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-2-git-send-email-u.kleine-koenig@pengutronix.de>

Additional document all known names of that machine.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/Makefile        |    2 +-
 arch/arm/mach-mx3/mach-mx35_3ds.c |  122 +++++++++++++++++++++++++++++++++++++
 arch/arm/mach-mx3/mach-mx35pdk.c  |  116 -----------------------------------
 3 files changed, 123 insertions(+), 117 deletions(-)
 create mode 100644 arch/arm/mach-mx3/mach-mx35_3ds.c
 delete mode 100644 arch/arm/mach-mx3/mach-mx35pdk.c

diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 5d650fd..2a4798d 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -22,5 +22,5 @@ obj-$(CONFIG_MACH_MX31MOBOARD)	+= mach-mx31moboard.o mx31moboard-devboard.o \
 obj-$(CONFIG_MACH_QONG)		+= mach-qong.o
 obj-$(CONFIG_MACH_PCM043)	+= mach-pcm043.o
 obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
-obj-$(CONFIG_MACH_MX35_3DS)	+= mach-mx35pdk.o
+obj-$(CONFIG_MACH_MX35_3DS)	+= mach-mx35_3ds.o
 obj-$(CONFIG_MACH_KZM_ARM11_01)	+= mach-kzm_arm11_01.o
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
new file mode 100644
index 0000000..66ad2da
--- /dev/null
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * Author: Fabio Estevam <fabio.estevam at freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * This machine is known as:
+ *  - i.MX35 3-Stack Development System
+ *  - i.MX35 Platform Development Kit (i.MX35 PDK)
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <linux/fsl_devices.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux-mx35.h>
+
+#include "devices.h"
+
+static struct imxuart_platform_data uart_pdata = {
+	.flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct platform_device *devices[] __initdata = {
+	&mxc_fec_device,
+};
+
+static struct pad_desc mx35pdk_pads[] = {
+	/* UART1 */
+	MX35_PAD_CTS1__UART1_CTS,
+	MX35_PAD_RTS1__UART1_RTS,
+	MX35_PAD_TXD1__UART1_TXD_MUX,
+	MX35_PAD_RXD1__UART1_RXD_MUX,
+	/* FEC */
+	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+	MX35_PAD_FEC_COL__FEC_COL,
+	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+	MX35_PAD_FEC_MDC__FEC_MDC,
+	MX35_PAD_FEC_MDIO__FEC_MDIO,
+	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+	MX35_PAD_FEC_CRS__FEC_CRS,
+	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+	/* USBOTG */
+	MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
+	MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
+};
+
+/* OTG config */
+static struct fsl_usb2_platform_data usb_pdata = {
+	.operating_mode	= FSL_USB2_DR_DEVICE,
+	.phy_mode	= FSL_USB2_PHY_UTMI_WIDE,
+};
+
+/*
+ * Board specific initialization.
+ */
+static void __init mxc_board_init(void)
+{
+	mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
+
+	platform_add_devices(devices, ARRAY_SIZE(devices));
+
+	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+
+	mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
+}
+
+static void __init mx35pdk_timer_init(void)
+{
+	mx35_clocks_init();
+}
+
+struct sys_timer mx35pdk_timer = {
+	.init	= mx35pdk_timer_init,
+};
+
+MACHINE_START(MX35_3DS, "Freescale MX35PDK")
+	/* Maintainer: Freescale Semiconductor, Inc */
+	.phys_io	= MX35_AIPS1_BASE_ADDR,
+	.io_pg_offst	= ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
+	.map_io         = mx35_map_io,
+	.init_irq       = mx35_init_irq,
+	.init_machine   = mxc_board_init,
+	.timer          = &mx35pdk_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx35pdk.c b/arch/arm/mach-mx3/mach-mx35pdk.c
deleted file mode 100644
index bcac84d..0000000
--- a/arch/arm/mach-mx3/mach-mx35pdk.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * Author: Fabio Estevam <fabio.estevam at freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/memory.h>
-#include <linux/gpio.h>
-#include <linux/fsl_devices.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/imx-uart.h>
-#include <mach/iomux-mx35.h>
-
-#include "devices.h"
-
-static struct imxuart_platform_data uart_pdata = {
-	.flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct platform_device *devices[] __initdata = {
-	&mxc_fec_device,
-};
-
-static struct pad_desc mx35pdk_pads[] = {
-	/* UART1 */
-	MX35_PAD_CTS1__UART1_CTS,
-	MX35_PAD_RTS1__UART1_RTS,
-	MX35_PAD_TXD1__UART1_TXD_MUX,
-	MX35_PAD_RXD1__UART1_RXD_MUX,
-	/* FEC */
-	MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
-	MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
-	MX35_PAD_FEC_RX_DV__FEC_RX_DV,
-	MX35_PAD_FEC_COL__FEC_COL,
-	MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
-	MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
-	MX35_PAD_FEC_TX_EN__FEC_TX_EN,
-	MX35_PAD_FEC_MDC__FEC_MDC,
-	MX35_PAD_FEC_MDIO__FEC_MDIO,
-	MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
-	MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
-	MX35_PAD_FEC_CRS__FEC_CRS,
-	MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
-	MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
-	MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
-	MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
-	MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
-	MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
-	/* USBOTG */
-	MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
-	MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
-};
-
-/* OTG config */
-static struct fsl_usb2_platform_data usb_pdata = {
-	.operating_mode	= FSL_USB2_DR_DEVICE,
-	.phy_mode	= FSL_USB2_PHY_UTMI_WIDE,
-};
-
-/*
- * Board specific initialization.
- */
-static void __init mxc_board_init(void)
-{
-	mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
-
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
-
-	mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
-}
-
-static void __init mx35pdk_timer_init(void)
-{
-	mx35_clocks_init();
-}
-
-struct sys_timer mx35pdk_timer = {
-	.init	= mx35pdk_timer_init,
-};
-
-MACHINE_START(MX35_3DS, "Freescale MX35PDK")
-	/* Maintainer: Freescale Semiconductor, Inc */
-	.phys_io	= MX35_AIPS1_BASE_ADDR,
-	.io_pg_offst	= ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
-	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
-	.map_io         = mx35_map_io,
-	.init_irq       = mx35_init_irq,
-	.init_machine   = mxc_board_init,
-	.timer          = &mx35pdk_timer,
-MACHINE_END
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:18 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:18 +0200
Subject: [PATCH 22/61] ARM: imx: rename mxc_uart_devicex to follow a common
	naming scheme
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-23-git-send-email-u.kleine-koenig@pengutronix.de>

Addionally remove an unneeded include.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/devices.c                  |   17 ++++++++---------
 arch/arm/mach-imx/devices.h                  |   14 ++++++++------
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c |    4 ++--
 arch/arm/mach-imx/mach-cpuimx27.c            |    4 ++--
 arch/arm/mach-imx/mach-imx27lite.c           |    2 +-
 arch/arm/mach-imx/mach-mx21ads.c             |    6 +++---
 arch/arm/mach-imx/mach-mx27_3ds.c            |    2 +-
 arch/arm/mach-imx/mach-mx27ads.c             |   12 ++++++------
 arch/arm/mach-imx/mach-mxt_td60.c            |    6 +++---
 arch/arm/mach-imx/mach-pca100.c              |    2 +-
 arch/arm/mach-imx/mach-pcm038.c              |    6 +++---
 11 files changed, 38 insertions(+), 37 deletions(-)

diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index 08ae763..b372805 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -38,7 +38,6 @@
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/mmc.h>
-#include <mach/imx-uart.h>
 
 #include "devices.h"
 
@@ -426,7 +425,7 @@ struct platform_device mxc_usbh2 = {
 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 
-#define DEFINE_IMX_UART_DEVICE(n, baseaddr, irq)			\
+#define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq)			\
 	static struct resource imx2x_uart_resources ## n[] = {		\
 		{							\
 			.start = baseaddr,				\
@@ -439,21 +438,21 @@ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 		},							\
 	};								\
 									\
-	struct platform_device mxc_uart_device ## n = {			\
+	struct platform_device imx2x_uart_device ## n = {		\
 		.name = "imx-uart",					\
 		.id = n,						\
 		.num_resources = ARRAY_SIZE(imx2x_uart_resources ## n),	\
 		.resource = imx2x_uart_resources ## n,			\
 	}
 
-DEFINE_IMX_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
-DEFINE_IMX_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
-DEFINE_IMX_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
-DEFINE_IMX_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
+DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
+DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
+DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
+DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
 
 #ifdef CONFIG_MACH_MX27
-DEFINE_IMX_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
-DEFINE_IMX_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
+DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
+DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
 #endif
 
 /* GPIO port description */
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index 84ed513..65c4a43 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -6,12 +6,14 @@ extern struct platform_device mxc_gpt4;
 extern struct platform_device mxc_gpt5;
 #endif
 extern struct platform_device mxc_wdt;
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-extern struct platform_device mxc_uart_device3;
-extern struct platform_device mxc_uart_device4;
-extern struct platform_device mxc_uart_device5;
+extern struct platform_device imx2x_uart_device0;
+extern struct platform_device imx2x_uart_device1;
+extern struct platform_device imx2x_uart_device2;
+extern struct platform_device imx2x_uart_device3;
+#ifdef CONFIG_MACH_MX27
+extern struct platform_device imx2x_uart_device4;
+extern struct platform_device imx2x_uart_device5;
+#endif
 extern struct platform_device mxc_w1_master_device;
 #ifdef CONFIG_MACH_MX21
 extern struct platform_device imx21_nand_device;
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index f3b169d..463e80d 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -222,8 +222,8 @@ void __init eukrea_mbimx27_baseboard_init(void)
 	mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
 		ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
 
-	mxc_register_device(&mxc_uart_device1, &uart_pdata[0]);
-	mxc_register_device(&mxc_uart_device2, &uart_pdata[1]);
+	mxc_register_device(&imx2x_uart_device1, &uart_pdata[0]);
+	mxc_register_device(&imx2x_uart_device2, &uart_pdata[1]);
 
 	mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
 	mxc_register_device(&mxc_sdhc_device0, NULL);
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 1f616dc..866a99a 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -187,7 +187,7 @@ static void __init eukrea_cpuimx27_init(void)
 	mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
 		ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
 
-	mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+	mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]);
 
 	mxc_register_device(&imx27_nand_device,
 			&eukrea_cpuimx27_nand_board_info);
@@ -203,7 +203,7 @@ static void __init eukrea_cpuimx27_init(void)
 	/* SDHC2 can be used for Wifi */
 	mxc_register_device(&mxc_sdhc_device1, NULL);
 	/* in which case UART4 is also used for Bluetooth */
-	mxc_register_device(&mxc_uart_device3, &uart_pdata[1]);
+	mxc_register_device(&imx2x_uart_device3, &uart_pdata[1]);
 #endif
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index fd1dddb..27da9a1 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -70,7 +70,7 @@ static void __init mx27lite_init(void)
 {
 	mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
 		"imx27lite");
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	mxc_register_device(&imx2x_uart_device0, &uart_pdata);
 	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 99f2492..e51f6f8 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -297,9 +297,9 @@ static void __init mx21ads_board_init(void)
 	mxc_gpio_setup_multiple_pins(mx21ads_pins, ARRAY_SIZE(mx21ads_pins),
 			"mx21ads");
 
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
-	mxc_register_device(&mxc_uart_device2, &uart_norts_pdata);
-	mxc_register_device(&mxc_uart_device3, &uart_pdata);
+	mxc_register_device(&imx2x_uart_device0, &uart_pdata);
+	mxc_register_device(&imx2x_uart_device2, &uart_norts_pdata);
+	mxc_register_device(&imx2x_uart_device3, &uart_pdata);
 	mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
 	mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
 	mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index a45df59..c9af5f1 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -75,7 +75,7 @@ static void __init mx27pdk_init(void)
 {
 	mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
 		"mx27pdk");
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	mxc_register_device(&imx2x_uart_device0, &uart_pdata);
 	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 2183e3d..771a63f 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -313,12 +313,12 @@ static void __init mx27ads_board_init(void)
 	mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
 			"mx27ads");
 
-	mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-	mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
-	mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
-	mxc_register_device(&mxc_uart_device3, &uart_pdata[3]);
-	mxc_register_device(&mxc_uart_device4, &uart_pdata[4]);
-	mxc_register_device(&mxc_uart_device5, &uart_pdata[5]);
+	mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]);
+	mxc_register_device(&imx2x_uart_device1, &uart_pdata[1]);
+	mxc_register_device(&imx2x_uart_device2, &uart_pdata[2]);
+	mxc_register_device(&imx2x_uart_device3, &uart_pdata[3]);
+	mxc_register_device(&imx2x_uart_device4, &uart_pdata[4]);
+	mxc_register_device(&imx2x_uart_device5, &uart_pdata[5]);
 	mxc_register_device(&imx27_nand_device, &mx27ads_nand_board_info);
 
 	/* only the i2c master 1 is used on this CPU card */
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index bc38559..4f4200b 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -254,9 +254,9 @@ static void __init mxt_td60_board_init(void)
 	mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
 			"MXT_TD60");
 
-	mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-	mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
-	mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
+	mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]);
+	mxc_register_device(&imx2x_uart_device1, &uart_pdata[1]);
+	mxc_register_device(&imx2x_uart_device2, &uart_pdata[2]);
 	mxc_register_device(&imx27_nand_device, &mxt_td60_nand_board_info);
 
 	i2c_register_board_info(0, mxt_td60_i2c_devices,
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index a87422e..984c4ca 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -320,7 +320,7 @@ static void __init pca100_init(void)
 
 	mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
 
-	mxc_register_device(&mxc_uart_device0, &uart_pdata);
+	mxc_register_device(&imx2x_uart_device0, &uart_pdata);
 
 	mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
 	mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 36c8943..b6a15ba 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -305,9 +305,9 @@ static void __init pcm038_init(void)
 
 	pcm038_init_sram();
 
-	mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
-	mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
-	mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
+	mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]);
+	mxc_register_device(&imx2x_uart_device1, &uart_pdata[1]);
+	mxc_register_device(&imx2x_uart_device2, &uart_pdata[2]);
 
 	mxc_gpio_mode(PE16_AF_OWIRE);
 	mxc_register_device(&imx27_nand_device, &pcm038_nand_board_info);
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:32 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:32 +0200
Subject: [PATCH 36/61] ARM: imx: Change the way nand devices are registered
	(imx21)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-37-git-send-email-u.kleine-koenig@pengutronix.de>

Make use of new mechanism to register a nand device.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig         |    1 +
 arch/arm/mach-imx/devices-imx21.h |   13 +++++++++++++
 arch/arm/mach-imx/devices.c       |    4 ----
 arch/arm/mach-imx/devices.h       |    3 ---
 arch/arm/mach-imx/mach-mx21ads.c  |    6 ++++--
 5 files changed, 18 insertions(+), 9 deletions(-)
 create mode 100644 arch/arm/mach-imx/devices-imx21.h

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 73c70af..2367182 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -68,6 +68,7 @@ comment "MX21 platforms:"
 
 config MACH_MX21ADS
 	bool "MX21ADS platform"
+	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for MX21ADS platform. This includes specific
 	  configurations for the board and its peripherals.
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
new file mode 100644
index 0000000..e85dcb1
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx21.h>
+#include <mach/devices-common.h>
+
+#define imx21_add_mxc_nand(pdata)	\
+	imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index ceae641..dbd1460 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -357,10 +357,6 @@ struct platform_device mxc_w1_master_device = {
 		.resource = pfx ## _nand_resources,			\
 	}
 
-#ifdef CONFIG_MACH_MX21
-DEFINE_MXC_NAND_DEVICE(imx21, MX21_NFC_BASE_ADDR, MX21_INT_NANDFC);
-#endif
-
 #ifdef CONFIG_MACH_MX27
 DEFINE_MXC_NAND_DEVICE(imx27, MX27_NFC_BASE_ADDR, MX27_INT_NANDFC);
 #endif
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index 5c1a0dc..d3c381f 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -26,9 +26,6 @@ extern struct platform_device imx2x_uart_device4;
 extern struct platform_device imx2x_uart_device5;
 #endif
 extern struct platform_device mxc_w1_master_device;
-#ifdef CONFIG_MACH_MX21
-extern struct platform_device imx21_nand_device;
-#endif
 #ifdef CONFIG_MACH_MX27
 extern struct platform_device imx27_nand_device;
 #endif
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index 39c645a..fde2a57 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -30,6 +30,7 @@
 #include <mach/mxc_nand.h>
 #include <mach/mmc.h>
 
+#include "devices-imx21.h"
 #include "devices.h"
 
 /*
@@ -257,7 +258,8 @@ static struct imxmmc_platform_data mx21ads_sdhc_pdata = {
 	.exit = mx21ads_sdhc_exit,
 };
 
-static struct mxc_nand_platform_data mx21ads_nand_board_info = {
+static const struct mxc_nand_platform_data
+mx21ads_nand_board_info __initconst = {
 	.width = 1,
 	.hw_ecc = 1,
 };
@@ -298,7 +300,7 @@ static void __init mx21ads_board_init(void)
 	mxc_register_device(&imx2x_uart_device3, &uart_pdata);
 	mxc_register_device(&mxc_fb_device, &mx21ads_fb_data);
 	mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata);
-	mxc_register_device(&imx21_nand_device, &mx21ads_nand_board_info);
+	imx21_add_mxc_nand(&mx21ads_nand_board_info);
 
 	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:12 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:12 +0200
Subject: [PATCH 16/61] ARM: imx: get rid of mxc_gpio_init
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-17-git-send-email-u.kleine-koenig@pengutronix.de>

This function is defined once for each imx family and so is in the way
when compiling a kernel for more than one SoC.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/devices.c      |   22 ++++++++--------------
 arch/arm/mach-imx/mm-imx21.c     |    3 +++
 arch/arm/mach-imx/mm-imx27.c     |    3 +++
 arch/arm/mach-mx1/devices.c      |    2 +-
 arch/arm/mach-mx1/generic.c      |    3 +++
 arch/arm/mach-mx25/devices.c     |    2 +-
 arch/arm/mach-mx25/mm.c          |    3 +++
 arch/arm/mach-mx3/devices.c      |    2 +-
 arch/arm/mach-mx3/mm.c           |    3 +++
 arch/arm/mach-mx5/devices.c      |    2 +-
 arch/arm/mach-mx5/mm.c           |    3 +++
 arch/arm/mach-mxc91231/devices.c |    2 +-
 arch/arm/mach-mxc91231/mm.c      |    3 +++
 arch/arm/plat-mxc/irq.c          |    3 ---
 arch/arm/plat-mxc/tzic.c         |    2 --
 15 files changed, 34 insertions(+), 24 deletions(-)

diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index a0aeb8a..e708bfd 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -454,26 +454,21 @@ DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 
 #ifdef CONFIG_MACH_MX21
 DEFINE_MXC_GPIO_PORTS(MX21, imx21);
+
+int __init imx21_register_gpios(void)
+{
+	return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
+}
 #endif
 
 #ifdef CONFIG_MACH_MX27
 DEFINE_MXC_GPIO_PORTS(MX27, imx27);
-#endif
 
-int __init mxc_register_gpios(void)
+int __init imx27_register_gpios(void)
 {
-#ifdef CONFIG_MACH_MX21
-	if (cpu_is_mx21())
-		return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
-	else
-#endif
-#ifdef CONFIG_MACH_MX27
-	if (cpu_is_mx27())
-		return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
-	else
-#endif
-		return 0;
+	return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
 }
+#endif
 
 #ifdef CONFIG_MACH_MX21
 static struct resource mx21_usbhc_resources[] = {
@@ -500,4 +495,3 @@ struct platform_device mx21_usbhc_device = {
 	.resource	= mx21_usbhc_resources,
 };
 #endif
-
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 115c212..68aa5d2 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -77,7 +77,10 @@ void __init mx21_map_io(void)
 	iotable_init(imx21_io_desc, ARRAY_SIZE(imx21_io_desc));
 }
 
+int imx21_register_gpios(void);
+
 void __init mx21_init_irq(void)
 {
+	imx21_register_gpios();
 	mxc_init_irq(MX21_IO_ADDRESS(MX21_AVIC_BASE_ADDR));
 }
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 89b4174..bcedce9 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -77,7 +77,10 @@ void __init mx27_map_io(void)
 	iotable_init(imx27_io_desc, ARRAY_SIZE(imx27_io_desc));
 }
 
+int imx27_register_gpios(void);
+
 void __init mx27_init_irq(void)
 {
+	imx27_register_gpios();
 	mxc_init_irq(MX27_IO_ADDRESS(MX27_AVIC_BASE_ADDR));
 }
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
index 8064f2c..860cbb7 100644
--- a/arch/arm/mach-mx1/devices.c
+++ b/arch/arm/mach-mx1/devices.c
@@ -237,7 +237,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
 	}
 };
 
-int __init mxc_register_gpios(void)
+int __init imx1_register_gpios(void)
 {
 	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 }
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-mx1/generic.c
index 5a745d9..a9be5f1 100644
--- a/arch/arm/mach-mx1/generic.c
+++ b/arch/arm/mach-mx1/generic.c
@@ -46,7 +46,10 @@ void __init mx1_map_io(void)
 	iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
 }
 
+int imx1_register_gpios(void);
+
 void __init mx1_init_irq(void)
 {
+	imx1_register_gpios();
 	mxc_init_irq(MX1_IO_ADDRESS(MX1_AVIC_BASE_ADDR));
 }
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 3a405fa..80f3131 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -414,7 +414,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
 	}
 };
 
-int __init mxc_register_gpios(void)
+int __init imx25_register_gpios(void)
 {
 	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 }
diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-mx25/mm.c
index a7e587f..cf4d76e 100644
--- a/arch/arm/mach-mx25/mm.c
+++ b/arch/arm/mach-mx25/mm.c
@@ -69,8 +69,11 @@ void __init mx25_map_io(void)
 	iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+int imx25_register_gpios(void);
+
 void __init mx25_init_irq(void)
 {
+	imx25_register_gpios();
 	mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
 }
 
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index db7acd6..f6da0ff 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -147,7 +147,7 @@ static struct mxc_gpio_port imx_gpio_ports[] = {
 	}
 };
 
-int __init mxc_register_gpios(void)
+int __init imx3x_register_gpios(void)
 {
 	return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
 }
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 6858a4f..595cf09 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -97,8 +97,11 @@ void __init mx35_map_io(void)
 }
 #endif
 
+int imx3x_register_gpios(void);
+
 void __init mx31_init_irq(void)
 {
+	imx3x_register_gpios();
 	mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
 }
 
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 7130449..f40778f 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -195,7 +195,7 @@ static struct mxc_gpio_port mxc_gpio_ports[] = {
 	},
 };
 
-int __init mxc_register_gpios(void)
+int __init imx51_register_gpios(void)
 {
 	return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
 }
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index b7677ef..2f79722 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -65,6 +65,8 @@ void __init mx51_map_io(void)
 	iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+int imx51_register_gpios(void);
+
 void __init mx51_init_irq(void)
 {
 	unsigned long tzic_addr;
@@ -79,5 +81,6 @@ void __init mx51_init_irq(void)
 	if (!tzic_virt)
 		panic("unable to map TZIC interrupt controller\n");
 
+	imx51_register_gpios();
 	tzic_init_irq(tzic_virt);
 }
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
index 353bd97..027af4f 100644
--- a/arch/arm/mach-mxc91231/devices.c
+++ b/arch/arm/mach-mxc91231/devices.c
@@ -135,7 +135,7 @@ static struct mxc_gpio_port mxc_gpio_ports[] = {
 	},
 };
 
-int __init mxc_register_gpios(void)
+int __init mxc91231_register_gpios(void)
 {
 	return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
 }
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
index 6becda3..1f23c74 100644
--- a/arch/arm/mach-mxc91231/mm.c
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -88,7 +88,10 @@ void __init mxc91231_map_io(void)
 	iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
 
+int mxc91231_register_gpios(void);
+
 void __init mxc91231_init_irq(void)
 {
+	mxc91231_register_gpios();
 	mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
 }
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 778ddfe..7331f2a 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -142,9 +142,6 @@ void __init mxc_init_irq(void __iomem *irqbase)
 	for (i = 0; i < 8; i++)
 		__raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
 
-	/* init architectures chained interrupt handler */
-	mxc_register_gpios();
-
 #ifdef CONFIG_FIQ
 	/* Initialize FIQ */
 	init_FIQ();
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 9b86d2a..b3da9aa 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -145,8 +145,6 @@ void __init tzic_init_irq(void __iomem *irqbase)
 		set_irq_handler(i, handle_level_irq);
 		set_irq_flags(i, IRQF_VALID);
 	}
-	mxc_register_gpios();
-
 	pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
 }
 
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:54 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:54 +0200
Subject: [PATCH 58/61] ARM: imx: dynamically register imx-uart devices (imx27)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-59-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig                    |    8 +++++++
 arch/arm/mach-imx/devices-imx27.h            |   13 +++++++++++
 arch/arm/mach-imx/devices.c                  |   29 --------------------------
 arch/arm/mach-imx/devices.h                  |    8 -------
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c |   14 +++---------
 arch/arm/mach-imx/mach-cpuimx27.c            |   13 +++--------
 arch/arm/mach-imx/mach-imx27lite.c           |    6 ++--
 arch/arm/mach-imx/mach-mx27_3ds.c            |    6 ++--
 arch/arm/mach-imx/mach-mx27ads.c             |   29 +++++++------------------
 arch/arm/mach-imx/mach-mxt_td60.c            |   17 ++++----------
 arch/arm/mach-imx/mach-pca100.c              |    5 +--
 arch/arm/mach-imx/mach-pcm038.c              |   17 ++++----------
 12 files changed, 55 insertions(+), 110 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0fa8acc..3da5355 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -86,6 +86,7 @@ comment "MX27 platforms:"
 config MACH_MX27ADS
 	bool "MX27ADS platform"
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for MX27ADS platform. This includes specific
@@ -94,6 +95,7 @@ config MACH_MX27ADS
 config MACH_PCM038
 	bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	select IMX_HAVE_PLATFORM_SPI_IMX
 	select MXC_ULPI if USB_ULPI
@@ -118,6 +120,7 @@ endchoice
 config MACH_CPUIMX27
 	bool "Eukrea CPUIMX27 module"
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for Eukrea CPUIMX27 platform. This includes
@@ -138,6 +141,7 @@ choice
 config MACH_EUKREA_MBIMX27_BASEBOARD
 	prompt "Eukrea MBIMX27 development board"
 	bool
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_SPI_IMX
 	help
 	  This adds board specific devices that can be found on Eukrea's
@@ -147,12 +151,14 @@ endchoice
 
 config MACH_MX27_3DS
 	bool "MX27PDK platform"
+	select IMX_HAVE_PLATFORM_IMX_UART
 	help
 	  Include support for MX27PDK platform. This includes specific
 	  configurations for the board and its peripherals.
 
 config MACH_IMX27LITE
 	bool "LogicPD MX27 LITEKIT platform"
+	select IMX_HAVE_PLATFORM_IMX_UART
 	help
 	  Include support for MX27 LITEKIT platform. This includes specific
 	  configurations for the board and its peripherals.
@@ -160,6 +166,7 @@ config MACH_IMX27LITE
 config MACH_PCA100
 	bool "Phytec phyCARD-s (pca100)"
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	select IMX_HAVE_PLATFORM_SPI_IMX
 	select MXC_ULPI if USB_ULPI
@@ -170,6 +177,7 @@ config MACH_PCA100
 config MACH_MXT_TD60
 	bool "Maxtrack i-MXT TD60"
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_IMX_UART
 	select IMX_HAVE_PLATFORM_MXC_NAND
 	help
 	  Include support for i-MXT (aka td60) platform. This
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 7da1e2b..65e7bb7 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -14,6 +14,19 @@
 #define imx27_add_i2c_imx1(pdata)	\
 	imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata)
 
+#define imx27_add_imx_uart0(pdata)	\
+	imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata)
+#define imx27_add_imx_uart1(pdata)	\
+	imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata)
+#define imx27_add_imx_uart2(pdata)	\
+	imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata)
+#define imx27_add_imx_uart3(pdata)	\
+	imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata)
+#define imx27_add_imx_uart4(pdata)	\
+	imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata)
+#define imx27_add_imx_uart5(pdata)	\
+	imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata)
+
 #define imx27_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
 
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index 9ea2ef1..9510687 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -483,35 +483,6 @@ struct platform_device mxc_usbh2 = {
 DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
 
-#ifdef CONFIG_MACH_MX27
-#define DEFINE_IMX2x_UART_DEVICE(n, baseaddr, irq)			\
-	static struct resource imx2x_uart_resources ## n[] = {		\
-		{							\
-			.start = baseaddr,				\
-			.end = baseaddr + 0xb5,				\
-			.flags = IORESOURCE_MEM,			\
-		}, {							\
-			.start = irq,					\
-			.end = irq,					\
-			.flags = IORESOURCE_IRQ,			\
-		},							\
-	};								\
-									\
-	struct platform_device imx2x_uart_device ## n = {		\
-		.name = "imx-uart",					\
-		.id = n,						\
-		.num_resources = ARRAY_SIZE(imx2x_uart_resources ## n),	\
-		.resource = imx2x_uart_resources ## n,			\
-	}
-
-DEFINE_IMX2x_UART_DEVICE(0, MX2x_UART1_BASE_ADDR, MX2x_INT_UART1);
-DEFINE_IMX2x_UART_DEVICE(1, MX2x_UART2_BASE_ADDR, MX2x_INT_UART2);
-DEFINE_IMX2x_UART_DEVICE(2, MX2x_UART3_BASE_ADDR, MX2x_INT_UART3);
-DEFINE_IMX2x_UART_DEVICE(3, MX2x_UART4_BASE_ADDR, MX2x_INT_UART4);
-DEFINE_IMX2x_UART_DEVICE(4, MX27_UART5_BASE_ADDR, MX27_INT_UART5);
-DEFINE_IMX2x_UART_DEVICE(5, MX27_UART6_BASE_ADDR, MX27_INT_UART6);
-#endif
-
 /* GPIO port description */
 #define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq)				\
 	{								\
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index 13790fb..109f26c 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -14,14 +14,6 @@ extern struct platform_device mxc_gpt4;
 extern struct platform_device mxc_gpt5;
 #endif
 extern struct platform_device mxc_wdt;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device imx2x_uart_device0;
-extern struct platform_device imx2x_uart_device1;
-extern struct platform_device imx2x_uart_device2;
-extern struct platform_device imx2x_uart_device3;
-extern struct platform_device imx2x_uart_device4;
-extern struct platform_device imx2x_uart_device5;
-#endif
 extern struct platform_device mxc_w1_master_device;
 extern struct platform_device mxc_fb_device;
 extern struct platform_device mxc_fec_device;
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index eed8143..1fb34f3 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -32,7 +32,6 @@
 #include <mach/imxfb.h>
 #include <mach/hardware.h>
 #include <mach/mmc.h>
-#include <mach/imx-uart.h>
 
 #include "devices-imx27.h"
 #include "devices.h"
@@ -154,13 +153,8 @@ static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
 	.dmacr		= 0x00040060,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-	{
-		.flags = IMXUART_HAVE_RTSCTS,
-	},
-	{
-		.flags = IMXUART_HAVE_RTSCTS,
-	},
+static const struct imxuart_platform_data uart_pdata __initconst = {
+	.flags = IMXUART_HAVE_RTSCTS,
 };
 
 #if defined(CONFIG_TOUCHSCREEN_ADS7846)
@@ -223,8 +217,8 @@ void __init eukrea_mbimx27_baseboard_init(void)
 	mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
 		ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
 
-	mxc_register_device(&imx2x_uart_device1, &uart_pdata[0]);
-	mxc_register_device(&imx2x_uart_device2, &uart_pdata[1]);
+	imx27_add_imx_uart1(&uart_pdata);
+	imx27_add_imx_uart2(&uart_pdata);
 
 	mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
 	mxc_register_device(&mxc_sdhc_device0, NULL);
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 06dcd23..09cc0c5 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -36,7 +36,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
-#include <mach/imx-uart.h>
 #include <mach/mxc_nand.h>
 
 #include "devices-imx27.h"
@@ -111,12 +110,8 @@ static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
 	.resource = &eukrea_cpuimx27_flash_resource,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-	{
-		.flags = IMXUART_HAVE_RTSCTS,
-	}, {
-		.flags = IMXUART_HAVE_RTSCTS,
-	},
+static const struct imxuart_platform_data uart_pdata __initconst = {
+	.flags = IMXUART_HAVE_RTSCTS,
 };
 
 static const struct mxc_nand_platform_data
@@ -188,7 +183,7 @@ static void __init eukrea_cpuimx27_init(void)
 	mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
 		ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
 
-	mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]);
+	imx27_add_imx_uart0(&uart_pdata);
 
 	imx27_add_mxc_nand(&cpuimx27_nand_board_info);
 
@@ -203,7 +198,7 @@ static void __init eukrea_cpuimx27_init(void)
 	/* SDHC2 can be used for Wifi */
 	mxc_register_device(&mxc_sdhc_device1, NULL);
 	/* in which case UART4 is also used for Bluetooth */
-	mxc_register_device(&imx2x_uart_device3, &uart_pdata[1]);
+	imx27_add_imx_uart3(&uart_pdata);
 #endif
 
 #if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 6df5c7d..22a2b5d 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -22,9 +22,9 @@
 #include <asm/mach/map.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static unsigned int mx27lite_pins[] = {
@@ -54,7 +54,7 @@ static unsigned int mx27lite_pins[] = {
 	PF23_AIN_FEC_TX_EN,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -66,7 +66,7 @@ static void __init mx27lite_init(void)
 {
 	mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
 		"imx27lite");
-	mxc_register_device(&imx2x_uart_device0, &uart_pdata);
+	imx27_add_imx_uart0(&uart_pdata);
 	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index da3eeff..e2a82ba 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -27,9 +27,9 @@
 #include <asm/mach/time.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static unsigned int mx27pdk_pins[] = {
@@ -59,7 +59,7 @@ static unsigned int mx27pdk_pins[] = {
 	PF23_AIN_FEC_TX_EN,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -71,7 +71,7 @@ static void __init mx27pdk_init(void)
 {
 	mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
 		"mx27pdk");
-	mxc_register_device(&imx2x_uart_device0, &uart_pdata);
+	imx27_add_imx_uart0(&uart_pdata);
 	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 }
 
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index f1ee335..9c77da9 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -28,7 +28,6 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <mach/gpio.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
 #include <mach/mxc_nand.h>
 #include <mach/imxfb.h>
@@ -289,20 +288,8 @@ static struct platform_device *platform_devices[] __initdata = {
 	&mxc_w1_master_device,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-	{
-		.flags = IMXUART_HAVE_RTSCTS,
-	}, {
-		.flags = IMXUART_HAVE_RTSCTS,
-	}, {
-		.flags = IMXUART_HAVE_RTSCTS,
-	}, {
-		.flags = IMXUART_HAVE_RTSCTS,
-	}, {
-		.flags = IMXUART_HAVE_RTSCTS,
-	}, {
-		.flags = IMXUART_HAVE_RTSCTS,
-	},
+static const struct imxuart_platform_data uart_pdata __initconst = {
+	.flags = IMXUART_HAVE_RTSCTS,
 };
 
 static void __init mx27ads_board_init(void)
@@ -310,12 +297,12 @@ static void __init mx27ads_board_init(void)
 	mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
 			"mx27ads");
 
-	mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]);
-	mxc_register_device(&imx2x_uart_device1, &uart_pdata[1]);
-	mxc_register_device(&imx2x_uart_device2, &uart_pdata[2]);
-	mxc_register_device(&imx2x_uart_device3, &uart_pdata[3]);
-	mxc_register_device(&imx2x_uart_device4, &uart_pdata[4]);
-	mxc_register_device(&imx2x_uart_device5, &uart_pdata[5]);
+	imx27_add_imx_uart0(&uart_pdata);
+	imx27_add_imx_uart1(&uart_pdata);
+	imx27_add_imx_uart2(&uart_pdata);
+	imx27_add_imx_uart3(&uart_pdata);
+	imx27_add_imx_uart4(&uart_pdata);
+	imx27_add_imx_uart5(&uart_pdata);
 	imx27_add_mxc_nand(&mx27ads_nand_board_info);
 
 	/* only the i2c master 1 is used on this CPU card */
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index b80b41e..a3a1e45 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -28,7 +28,6 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 #include <linux/gpio.h>
-#include <mach/imx-uart.h>
 #include <mach/iomux-mx27.h>
 #include <mach/mxc_nand.h>
 #include <linux/i2c/pca953x.h>
@@ -236,14 +235,8 @@ static struct platform_device *platform_devices[] __initdata = {
 	&mxc_fec_device,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-	{
-		.flags = IMXUART_HAVE_RTSCTS,
-	}, {
-		.flags = IMXUART_HAVE_RTSCTS,
-	}, {
-		.flags = IMXUART_HAVE_RTSCTS,
-	},
+static const struct imxuart_platform_data uart_pdata __initconst = {
+	.flags = IMXUART_HAVE_RTSCTS,
 };
 
 static void __init mxt_td60_board_init(void)
@@ -251,9 +244,9 @@ static void __init mxt_td60_board_init(void)
 	mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
 			"MXT_TD60");
 
-	mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]);
-	mxc_register_device(&imx2x_uart_device1, &uart_pdata[1]);
-	mxc_register_device(&imx2x_uart_device2, &uart_pdata[2]);
+	imx27_add_imx_uart0(&uart_pdata);
+	imx27_add_imx_uart1(&uart_pdata);
+	imx27_add_imx_uart2(&uart_pdata);
 	imx27_add_mxc_nand(&mxt_td60_nand_board_info);
 
 	i2c_register_board_info(0, mxt_td60_i2c_devices,
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 953cc74..ff3cf1e 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -37,7 +37,6 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
 #include <asm/mach/time.h>
-#include <mach/imx-uart.h>
 #include <mach/audmux.h>
 #include <mach/ssi.h>
 #include <mach/mxc_nand.h>
@@ -130,7 +129,7 @@ static int pca100_pins[] = {
 	PD26_AF_USBH2_DATA5,
 };
 
-static struct imxuart_platform_data uart_pdata = {
+static const struct imxuart_platform_data uart_pdata __initconst = {
 	.flags = IMXUART_HAVE_RTSCTS,
 };
 
@@ -318,7 +317,7 @@ static void __init pca100_init(void)
 
 	mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
 
-	mxc_register_device(&imx2x_uart_device0, &uart_pdata);
+	imx27_add_imx_uart0(&uart_pdata);
 
 	mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
 	mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index c09f234..9212e8f 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -36,7 +36,6 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
-#include <mach/imx-uart.h>
 #include <mach/mxc_nand.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
@@ -161,14 +160,8 @@ static struct platform_device pcm038_nor_mtd_device = {
 	.resource = &pcm038_flash_resource,
 };
 
-static struct imxuart_platform_data uart_pdata[] = {
-	{
-		.flags = IMXUART_HAVE_RTSCTS,
-	}, {
-		.flags = IMXUART_HAVE_RTSCTS,
-	}, {
-		.flags = IMXUART_HAVE_RTSCTS,
-	},
+static const struct imxuart_platform_data uart_pdata __initconst = {
+	.flags = IMXUART_HAVE_RTSCTS,
 };
 
 static const struct mxc_nand_platform_data
@@ -305,9 +298,9 @@ static void __init pcm038_init(void)
 
 	pcm038_init_sram();
 
-	mxc_register_device(&imx2x_uart_device0, &uart_pdata[0]);
-	mxc_register_device(&imx2x_uart_device1, &uart_pdata[1]);
-	mxc_register_device(&imx2x_uart_device2, &uart_pdata[2]);
+	imx27_add_imx_uart0(&uart_pdata);
+	imx27_add_imx_uart1(&uart_pdata);
+	imx27_add_imx_uart2(&uart_pdata);
 
 	mxc_gpio_mode(PE16_AF_OWIRE);
 	imx27_add_mxc_nand(&pcm038_nand_board_info);
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:30 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:30 +0200
Subject: [PATCH 34/61] ARM: mxc: remove paragraphs with old address of the FSF
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-35-git-send-email-u.kleine-koenig@pengutronix.de>

As the kernel contains a copy of the GPL anyhow just get rid of the address
specification instead of fixing it.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/plat-mxc/audmux-v1.c                   |    4 ----
 arch/arm/plat-mxc/audmux-v2.c                   |    4 ----
 arch/arm/plat-mxc/ehci.c                        |    4 ----
 arch/arm/plat-mxc/include/mach/iomux-mxc91231.h |    4 ----
 arch/arm/plat-mxc/include/mach/mx3_camera.h     |    4 ----
 arch/arm/plat-mxc/include/mach/mxc91231.h       |    4 ----
 arch/arm/plat-mxc/include/mach/system.h         |    4 ----
 arch/arm/plat-mxc/include/mach/timex.h          |    4 ----
 arch/arm/plat-mxc/include/mach/uncompress.h     |    4 ----
 arch/arm/plat-mxc/include/mach/vmalloc.h        |    4 ----
 arch/arm/plat-mxc/system.c                      |    4 ----
 11 files changed, 0 insertions(+), 44 deletions(-)

diff --git a/arch/arm/plat-mxc/audmux-v1.c b/arch/arm/plat-mxc/audmux-v1.c
index b62917c..1180bef 100644
--- a/arch/arm/plat-mxc/audmux-v1.c
+++ b/arch/arm/plat-mxc/audmux-v1.c
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #include <linux/module.h>
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 0c2cc5c..1b5e4df 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #include <linux/module.h>
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 2a86461..6cedd5d 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -11,10 +11,6 @@
  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  * for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software Foundation,
- * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #include <linux/platform_device.h>
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
index 3887f3f..15d5951 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __MACH_IOMUX_MXC91231_H__
diff --git a/arch/arm/plat-mxc/include/mach/mx3_camera.h b/arch/arm/plat-mxc/include/mach/mx3_camera.h
index 36d7ff2..f226ee3 100644
--- a/arch/arm/plat-mxc/include/mach/mx3_camera.h
+++ b/arch/arm/plat-mxc/include/mach/mx3_camera.h
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
 #ifndef _MX3_CAMERA_H_
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 5182b98..0ca3101 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #ifndef __MACH_MXC91231_H__
 #define __MACH_MXC91231_H__
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index ef00199..4acd114 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -12,10 +12,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 024416e..2d96246 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -11,10 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __ASM_ARCH_MXC_TIMEX_H__
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index b6d3d0f..d9bd37e 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -13,10 +13,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 #ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
 #define __ASM_ARCH_MXC_UNCOMPRESS_H__
diff --git a/arch/arm/plat-mxc/include/mach/vmalloc.h b/arch/arm/plat-mxc/include/mach/vmalloc.h
index 44243a2..ef6379c 100644
--- a/arch/arm/plat-mxc/include/mach/vmalloc.h
+++ b/arch/arm/plat-mxc/include/mach/vmalloc.h
@@ -11,10 +11,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #ifndef __ASM_ARCH_MXC_VMALLOC_H__
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 97f4279..925bce4 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -14,10 +14,6 @@
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
 #include <linux/kernel.h>
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:24 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:24 +0200
Subject: [PATCH 28/61] ARM: imx: new helper function imx_add_platform_device
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-29-git-send-email-u.kleine-koenig@pengutronix.de>

This should be a globally available function, see

	http://thread.gmane.org/gmane.linux.kernel/998881/focus=998882

Until this hits mainline make a similar function available for imx
platforms only.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/plat-mxc/devices.c                     |   33 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/devices-common.h |   15 ++++++++++
 2 files changed, 48 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-mxc/include/mach/devices-common.h

diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index 56f2fb5..735776d 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -18,6 +18,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/err.h>
 #include <linux/platform_device.h>
 #include <mach/common.h>
 
@@ -35,3 +36,35 @@ int __init mxc_register_device(struct platform_device *pdev, void *data)
 	return ret;
 }
 
+struct platform_device *__init imx_add_platform_device(const char *name, int id,
+		const struct resource *res, unsigned int num_resources,
+		const void *data, size_t size_data)
+{
+	int ret = -ENOMEM;
+	struct platform_device *pdev;
+
+	pdev = platform_device_alloc(name, id);
+	if (!pdev)
+		goto err;
+
+	if (res) {
+		ret = platform_device_add_resources(pdev, res, num_resources);
+		if (ret)
+			goto err;
+	}
+
+	if (data) {
+		ret = platform_device_add_data(pdev, data, size_data);
+		if (ret)
+			goto err;
+	}
+
+	ret = platform_device_add(pdev);
+	if (ret) {
+err:
+		platform_device_put(pdev);
+		return ERR_PTR(ret);
+	}
+
+	return pdev;
+}
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
new file mode 100644
index 0000000..849d8ff
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/init.h>
+
+struct platform_device *imx_add_platform_device(const char *name, int id,
+		const struct resource *res, unsigned int num_resources,
+		const void *data, size_t size_data);
-- 
1.7.1



From marek.vasut at gmail.com  Thu Jun 24 09:57:11 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 24 Jun 2010 15:57:11 +0200
Subject: [PATCH 1/3] pxa3xx: Fix HSIO bus x24 multiplier
Message-ID: <1277387833-5419-1-git-send-email-marek.vasut@gmail.com>

The value should be 24, not 0 in the possibilities array. It was just a silly
mistake.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/pxa3xx.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index f544e58..611622a 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -52,7 +52,7 @@
 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
 
 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
-static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
+static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
 
 /*
  * Get the clock frequency as reflected by CCSR and the turbo flag.
-- 
1.7.1



From marek.vasut at gmail.com  Thu Jun 24 09:57:13 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 24 Jun 2010 15:57:13 +0200
Subject: [PATCH 3/3] pxa2xx/cpufreq: Fix PCMCIA frequency scaling
In-Reply-To: <1277387833-5419-1-git-send-email-marek.vasut@gmail.com>
References: <1277387833-5419-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1277387833-5419-3-git-send-email-marek.vasut@gmail.com>

The MCxx values must be based off memory clock, not CPU core clock.

This also fixes the bug where on some machines the LCD went crazy while using
PCMCIA.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 drivers/pcmcia/pxa2xx_base.c |    5 ++---
 1 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c
index df4532e..f370476 100644
--- a/drivers/pcmcia/pxa2xx_base.c
+++ b/drivers/pcmcia/pxa2xx_base.c
@@ -178,7 +178,6 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
 			       unsigned long val,
 			       struct cpufreq_freqs *freqs)
 {
-#warning "it's not clear if this is right since the core CPU (N) clock has no effect on the memory (L) clock"
 	switch (val) {
 	case CPUFREQ_PRECHANGE:
 		if (freqs->new > freqs->old) {
@@ -186,7 +185,7 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
 			       "pre-updating\n",
 			       freqs->new / 1000, (freqs->new / 100) % 10,
 			       freqs->old / 1000, (freqs->old / 100) % 10);
-			pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
+			pxa2xx_pcmcia_set_timing(skt);
 		}
 		break;
 
@@ -196,7 +195,7 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
 			       "post-updating\n",
 			       freqs->new / 1000, (freqs->new / 100) % 10,
 			       freqs->old / 1000, (freqs->old / 100) % 10);
-			pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
+			pxa2xx_pcmcia_set_timing(skt);
 		}
 		break;
 	}
-- 
1.7.1



From alan at linux.intel.com  Thu Jun 24 09:34:26 2010
From: alan at linux.intel.com (Alan Cox)
Date: Thu, 24 Jun 2010 14:34:26 +0100
Subject: Regression in next-20100618
In-Reply-To: <CEE6BB42CAD6E947908279175AF8470A025FD0D69A@EXDCVYMBSTM006.EQ1STM.local>
References: <CEE6BB42CAD6E947908279175AF8470A025FD0D69A@EXDCVYMBSTM006.EQ1STM.local>
Message-ID: <20100624143426.083f49e9@linux.intel.com>

On Thu, 24 Jun 2010 14:17:51 +0200
Linus WALLEIJ <linus.walleij at stericsson.com> wrote:

> Looping in linux-arm-kernel in case there are more people having
> this regression on -next since 20100618.
> 
> I verified that the regression also appears on U300, and I
> suspect all platforms using PL011 to suffer from it, including
> Versatile, RealView and SPEAr for example.
> 
> Symptom: garbage characters at TTY prompt after boot.
> 
> Trying to figure out what is causing this but failing :-/

I know what the problem is - I've just not yet had time to fix it (or a
stable electricity supply this afternoon).

The serial layer doesn't cope with the fact the tty_port code manages
the active flag so needs to switch to its own - and clear it in
->shutdown/set it in open

Alan


From marek.vasut at gmail.com  Thu Jun 24 09:57:12 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 24 Jun 2010 15:57:12 +0200
Subject: [PATCH 2/3] pxa2xx/cpufreq: Simplify DRI recomputation routine
In-Reply-To: <1277387833-5419-1-git-send-email-marek.vasut@gmail.com>
References: <1277387833-5419-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1277387833-5419-2-git-send-email-marek.vasut@gmail.com>

This patch:
1) Simpifies the DRI recomputation routine by pulling out the common code
2) Fixes a bug in PXA27x DRI recomputation caused by incorrect parenthesis

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/cpufreq-pxa2xx.c |    9 +++++----
 1 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 9e4d981..bb5f21e 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -256,12 +256,13 @@ static void init_sdram_rows(void)
 
 static u32 mdrefr_dri(unsigned int freq)
 {
-	u32 dri = 0;
+	u32 dri = freq * SDRAM_TREF / sdram_rows;
 
-	if (cpu_is_pxa25x())
-		dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
 	if (cpu_is_pxa27x())
-		dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
+		dri -= 31;
+
+	dri /= 32;
+
 	return dri;
 }
 
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:47 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:47 +0200
Subject: [PATCH 51/61] ARM: imx: dynamically register spi_imx devices (imx27)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-52-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/Kconfig                    |    3 ++
 arch/arm/mach-imx/devices-imx27.h            |    7 +++++
 arch/arm/mach-imx/devices.c                  |   33 --------------------------
 arch/arm/mach-imx/devices.h                  |    5 ----
 arch/arm/mach-imx/eukrea_mbimx27-baseboard.c |    5 ++-
 arch/arm/mach-imx/mach-pca100.c              |    7 +----
 arch/arm/mach-imx/mach-pcm038.c              |    5 +--
 7 files changed, 17 insertions(+), 48 deletions(-)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 2bf8078..c185ec3 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -92,6 +92,7 @@ config MACH_PCM038
 	bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
 	select IMX_HAVE_PLATFORM_IMX_I2C
 	select IMX_HAVE_PLATFORM_MXC_NAND
+	select IMX_HAVE_PLATFORM_SPI_IMX
 	select MXC_ULPI if USB_ULPI
 	help
 	  Include support for phyCORE-i.MX27 (aka pcm038) platform. This
@@ -134,6 +135,7 @@ choice
 config MACH_EUKREA_MBIMX27_BASEBOARD
 	prompt "Eukrea MBIMX27 development board"
 	bool
+	select IMX_HAVE_PLATFORM_SPI_IMX
 	help
 	  This adds board specific devices that can be found on Eukrea's
 	  MBIMX27 evaluation board.
@@ -156,6 +158,7 @@ config MACH_PCA100
 	bool "Phytec phyCARD-s (pca100)"
 	select IMX_HAVE_PLATFORM_IMX_I2C
 	select IMX_HAVE_PLATFORM_MXC_NAND
+	select IMX_HAVE_PLATFORM_SPI_IMX
 	select MXC_ULPI if USB_ULPI
 	help
 	  Include support for phyCARD-s (aka pca100) platform. This
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 5e0c40c..7da1e2b 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -16,3 +16,10 @@
 
 #define imx27_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
+
+#define imx27_add_spi_imx0(pdata)	\
+	imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata)
+#define imx27_add_spi_imx1(pdata)	\
+	imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata)
+#define imx27_add_spi_imx2(pdata)	\
+	imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index e42eead..84e6da6 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -219,39 +219,6 @@ int __init imx1_register_gpios(void)
 
 #if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
 /*
- * SPI master controller
- *
- * - i.MX1: 2 channel (slighly different register setting)
- * - i.MX21: 2 channel
- * - i.MX27: 3 channel
- */
-#ifdef CONFIG_MACH_MX27
-#define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq)					\
-	static struct resource mxc_spi_resources ## n[] = {			\
-		{								\
-			.start = baseaddr,					\
-			.end = baseaddr + SZ_4K - 1,				\
-			.flags = IORESOURCE_MEM,				\
-		}, {								\
-			.start = irq,						\
-			.end = irq,						\
-			.flags = IORESOURCE_IRQ,				\
-		},								\
-	};									\
-										\
-	struct platform_device mxc_spi_device ## n = {				\
-		.name = "spi_imx",						\
-		.id = n,							\
-		.num_resources = ARRAY_SIZE(mxc_spi_resources ## n),		\
-		.resource = mxc_spi_resources ## n,				\
-	}
-
-DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
-DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
-DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
-#endif
-
-/*
  * General Purpose Timer
  * - i.MX21: 3 timers
  * - i.MX27: 6 timers
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index c15b0de..db995b1 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -34,11 +34,6 @@ extern struct platform_device mxc_otg_udc_device;
 extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
-#ifdef CONFIG_MACH_MX27
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-extern struct platform_device mxc_spi_device2;
-#endif
 extern struct platform_device mx21_usbhc_device;
 extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 463e80d..eed8143 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -34,6 +34,7 @@
 #include <mach/mmc.h>
 #include <mach/imx-uart.h>
 
+#include "devices-imx27.h"
 #include "devices.h"
 
 static int eukrea_mbimx27_pins[] = {
@@ -201,7 +202,7 @@ static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
 
 static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
 
-static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
+static const struct spi_imx_master eukrea_mbimx27_spi0_data __initconst = {
 	.chipselect	= eukrea_mbimx27_spi_cs,
 	.num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
 };
@@ -233,7 +234,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
 	/* SPI and ADS7846 Touchscreen controler init */
 	mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
 	mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
-	mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data);
+	imx27_add_spi_imx0(&eukrea_mbimx27_spi0_data);
 	spi_register_board_info(eukrea_mbimx27_spi_board_info,
 			ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
 	ads7846_dev_init();
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 6501a7a..953cc74 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -37,9 +37,6 @@
 #include <mach/hardware.h>
 #include <mach/iomux-mx27.h>
 #include <asm/mach/time.h>
-#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
-#include <mach/spi.h>
-#endif
 #include <mach/imx-uart.h>
 #include <mach/audmux.h>
 #include <mach/ssi.h>
@@ -192,7 +189,7 @@ static struct spi_board_info pca100_spi_board_info[] __initdata = {
 
 static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
 
-static struct spi_imx_master pca100_spi_0_data = {
+static const struct spi_imx_master pca100_spi0_data __initconst = {
 	.chipselect	= pca100_spi_cs,
 	.num_chipselect = ARRAY_SIZE(pca100_spi_cs),
 };
@@ -347,7 +344,7 @@ static void __init pca100_init(void)
 #if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
 	spi_register_board_info(pca100_spi_board_info,
 				ARRAY_SIZE(pca100_spi_board_info));
-	mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
+	imx27_add_spi_imx0(&pca100_spi_0_data);
 #endif
 
 	gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 7559e0f..c09f234 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -38,7 +38,6 @@
 #include <mach/iomux-mx27.h>
 #include <mach/imx-uart.h>
 #include <mach/mxc_nand.h>
-#include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
@@ -216,7 +215,7 @@ static struct i2c_board_info pcm038_i2c_devices[] = {
 
 static int pcm038_spi_cs[] = {GPIO_PORTD + 28};
 
-static struct spi_imx_master pcm038_spi_0_data = {
+static const struct spi_imx_master pcm038_spi0_data __initconst = {
 	.chipselect = pcm038_spi_cs,
 	.num_chipselect = ARRAY_SIZE(pcm038_spi_cs),
 };
@@ -327,7 +326,7 @@ static void __init pcm038_init(void)
 	/* MC13783 IRQ */
 	mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);
 
-	mxc_register_device(&mxc_spi_device0, &pcm038_spi_0_data);
+	imx27_add_spi_imx0(&pcm038_spi0_data);
 	spi_register_board_info(pcm038_spi_board_info,
 				ARRAY_SIZE(pcm038_spi_board_info));
 
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:48 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:48 +0200
Subject: [PATCH 52/61] ARM: imx: dynamically register spi_imx devices (imx31)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-53-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx3/Kconfig            |    4 ++++
 arch/arm/mach-mx3/devices-imx31.h    |    7 +++++++
 arch/arm/mach-mx3/devices.c          |    2 +-
 arch/arm/mach-mx3/devices.h          |    2 ++
 arch/arm/mach-mx3/mach-mx31_3ds.c    |    5 ++---
 arch/arm/mach-mx3/mach-mx31lilly.c   |   10 +++++-----
 arch/arm/mach-mx3/mach-mx31lite.c    |    5 ++---
 arch/arm/mach-mx3/mach-mx31moboard.c |    8 ++++----
 arch/arm/mach-mx3/mx31lite-db.c      |    6 +++---
 9 files changed, 30 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index b8a7610..60d58a6 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -55,6 +55,7 @@ config MACH_MX31LITE
 	select ARCH_MX31
 	select MXC_ULPI if USB_ULPI
 	select IMX_HAVE_PLATFORM_MXC_NAND
+	select IMX_HAVE_PLATFORM_SPI_IMX
 	help
 	  Include support for MX31 LITEKIT platform. This includes specific
 	  configurations for the board and its peripherals.
@@ -63,6 +64,7 @@ config MACH_MX31_3DS
 	bool "Support MX31PDK (3DS)"
 	select ARCH_MX31
 	select IMX_HAVE_PLATFORM_MXC_NAND
+	select IMX_HAVE_PLATFORM_SPI_IMX
 	help
 	  Include support for MX31PDK (3DS) platform. This includes specific
 	  configurations for the board and its peripherals.
@@ -80,6 +82,7 @@ config MACH_MX31MOBOARD
 	bool "Support mx31moboard platforms (EPFL Mobots group)"
 	select ARCH_MX31
 	select IMX_HAVE_PLATFORM_IMX_I2C
+	select IMX_HAVE_PLATFORM_SPI_IMX
 	select MXC_ULPI if USB_ULPI
 	help
 	  Include support for mx31moboard platform. This includes specific
@@ -88,6 +91,7 @@ config MACH_MX31MOBOARD
 config MACH_MX31LILLY
 	bool "Support MX31 LILLY-1131 platforms (INCO startec)"
 	select ARCH_MX31
+	select IMX_HAVE_PLATFORM_SPI_IMX
 	select MXC_ULPI if USB_ULPI
 	help
 	  Include support for mx31 based LILLY1131 modules. This includes
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
index 56bc1e1..1cf96ca 100644
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -18,3 +18,10 @@
 
 #define imx31_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata)
+
+#define imx31_add_spi_imx0(pdata)	\
+	imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata)
+#define imx31_add_spi_imx1(pdata)	\
+	imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata)
+#define imx31_add_spi_imx2(pdata)	\
+	imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index a285b16..02d05ea 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -379,6 +379,7 @@ struct platform_device mxc_usbh2 = {
 	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 };
 
+#if defined(CONFIG_ARCH_MX35)
 /*
  * SPI master controller
  * 3 channels
@@ -440,7 +441,6 @@ struct platform_device mxc_spi_device2 = {
 	.resource = mxc_spi_2_resources,
 };
 
-#ifdef CONFIG_ARCH_MX35
 static struct resource mxc_fec_resources[] = {
 	{
 		.start	= MXC_FEC_BASE_ADDR,
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index c50596a..d22a327 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -16,9 +16,11 @@ extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
 extern struct platform_device mxc_rnga_device;
+#if defined(CONFIG_ARCH_MX35)
 extern struct platform_device mxc_spi_device0;
 extern struct platform_device mxc_spi_device1;
 extern struct platform_device mxc_spi_device2;
+#endif
 extern struct platform_device imx_ssi_device0;
 extern struct platform_device imx_ssi_device1;
 extern struct platform_device imx_ssi_device1;
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index c730c09..2aa3e58 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -35,7 +35,6 @@
 #include <mach/common.h>
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
-#include <mach/spi.h>
 
 #include "devices-imx31.h"
 #include "devices.h"
@@ -170,7 +169,7 @@ static int spi1_internal_chipselect[] = {
 	MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master spi1_pdata = {
+static const struct spi_imx_master spi1_pdata __initconst = {
 	.chipselect	= spi1_internal_chipselect,
 	.num_chipselect	= ARRAY_SIZE(spi1_internal_chipselect),
 };
@@ -419,7 +418,7 @@ static void __init mxc_board_init(void)
 	mxc_register_device(&mxc_uart_device0, &uart_pdata);
 	imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
 
-	mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+	imx31_add_spi_imx0(&spi1_pdata);
 	spi_register_board_info(mx31_3ds_spi_devs,
 						ARRAY_SIZE(mx31_3ds_spi_devs));
 
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index b4cfbe0..9d6a6cc 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -42,10 +42,10 @@
 #include <mach/common.h>
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lilly.h>
-#include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -265,12 +265,12 @@ static int spi_internal_chipselect[] = {
 	MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master spi0_pdata = {
+static const struct spi_imx_master spi0_pdata __initconst = {
 	.chipselect = spi_internal_chipselect,
 	.num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
 
-static struct spi_imx_master spi1_pdata = {
+static const struct spi_imx_master spi1_pdata __initconst = {
 	.chipselect = spi_internal_chipselect,
 	.num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
 };
@@ -327,8 +327,8 @@ static void __init mx31lilly_board_init(void)
 	mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
 	mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
 
-	mxc_register_device(&mxc_spi_device0, &spi0_pdata);
-	mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+	imx31_add_spi_imx0(&spi0_pdata);
+	imx31_add_spi_imx1(&spi1_pdata);
 	spi_register_board_info(&mc13783_dev, 1);
 
 	platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index f0a68e6..634b855 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -41,7 +41,6 @@
 #include <mach/imx-uart.h>
 #include <mach/iomux-mx3.h>
 #include <mach/irqs.h>
-#include <mach/spi.h>
 #include <mach/mxc_ehci.h>
 #include <mach/ulpi.h>
 
@@ -109,7 +108,7 @@ static int spi_internal_chipselect[] = {
 	MXC_SPI_CS(0),
 };
 
-static struct spi_imx_master spi1_pdata = {
+static const struct spi_imx_master spi1_pdata __initconst = {
 	.chipselect	= spi_internal_chipselect,
 	.num_chipselect	= ARRAY_SIZE(spi_internal_chipselect),
 };
@@ -252,7 +251,7 @@ static void __init mxc_board_init(void)
 	platform_device_register(&physmap_flash_device);
 	imx31_add_mxc_nand(&mx31lite_nand_board_info);
 
-	mxc_register_device(&mxc_spi_device1, &spi1_pdata);
+	imx31_add_spi_imx1(&spi1_pdata);
 	spi_register_board_info(&mc13783_spi_dev, 1);
 
 #if defined(CONFIG_USB_ULPI)
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index dd51d08..689b068 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -152,7 +152,7 @@ static int moboard_spi1_cs[] = {
 	MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master moboard_spi1_master = {
+static const struct spi_imx_master moboard_spi1_pdata __initconst = {
 	.chipselect	= moboard_spi1_cs,
 	.num_chipselect	= ARRAY_SIZE(moboard_spi1_cs),
 };
@@ -282,7 +282,7 @@ static int moboard_spi2_cs[] = {
 	MXC_SPI_CS(1),
 };
 
-static struct spi_imx_master moboard_spi2_master = {
+static const struct spi_imx_master moboard_spi2_pdata __initconst = {
 	.chipselect	= moboard_spi2_cs,
 	.num_chipselect	= ARRAY_SIZE(moboard_spi2_cs),
 };
@@ -502,8 +502,8 @@ static void __init mxc_board_init(void)
 	imx31_add_imx_i2c0(&moboard_i2c0_data);
 	imx31_add_imx_i2c1(&moboard_i2c1_data);
 
-	mxc_register_device(&mxc_spi_device1, &moboard_spi1_master);
-	mxc_register_device(&mxc_spi_device2, &moboard_spi2_master);
+	imx31_add_spi_imx1(&moboard_spi1_pdata);
+	imx31_add_spi_imx2(&moboard_spi2_pdata);
 
 	gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
 	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index e35d2eb..3786e29 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -37,8 +37,8 @@
 #include <mach/iomux-mx3.h>
 #include <mach/board-mx31lite.h>
 #include <mach/mmc.h>
-#include <mach/spi.h>
 
+#include "devices-imx31.h"
 #include "devices.h"
 
 /*
@@ -157,7 +157,7 @@ static int spi_internal_chipselect[] = {
 	MXC_SPI_CS(2),
 };
 
-static struct spi_imx_master spi0_pdata = {
+static const struct spi_imx_master spi0_pdata __initconst = {
 	.chipselect	= spi_internal_chipselect,
 	.num_chipselect	= ARRAY_SIZE(spi_internal_chipselect),
 };
@@ -199,7 +199,7 @@ void __init mx31lite_db_init(void)
 					"development board pins");
 	mxc_register_device(&mxc_uart_device0, &uart_pdata);
 	mxc_register_device(&mxcsdhc_device0, &mmc_pdata);
-	mxc_register_device(&mxc_spi_device0, &spi0_pdata);
+	imx31_add_spi_imx0(&spi0_pdata);
 	platform_device_register(&litekit_led_device);
 	mxc_register_device(&imx_wdt_device0, NULL);
 	mxc_register_device(&imx_rtc_device0, NULL);
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:37 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:37 +0200
Subject: [PATCH 41/61] ARM: imx: dynamically register imx-i2c devices (generic
	part)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-42-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/plat-mxc/devices/Kconfig               |    3 ++
 arch/arm/plat-mxc/devices/Makefile              |    1 +
 arch/arm/plat-mxc/devices/platform-imx-i2c.c    |   29 +++++++++++++++++++++++
 arch/arm/plat-mxc/include/mach/devices-common.h |    5 ++++
 4 files changed, 38 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-mxc/devices/platform-imx-i2c.c

diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index 09e91dd..c50a7d6 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -1,2 +1,5 @@
+config IMX_HAVE_PLATFORM_IMX_I2C
+	bool
+
 config IMX_HAVE_PLATFORM_MXC_NAND
 	bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index e314533..4a2b2de 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -1 +1,2 @@
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
new file mode 100644
index 0000000..d0af9f7
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig at pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/devices-common.h>
+
+struct platform_device *__init imx_add_imx_i2c(int id,
+		resource_size_t iobase, resource_size_t iosize, int irq,
+		const struct imxi2c_platform_data *pdata)
+{
+	struct resource res[] = {
+		{
+			.start = iobase,
+			.end = iobase + iosize - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = irq,
+			.end = irq,
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+
+	return imx_add_platform_device("imx-i2c", id, res, ARRAY_SIZE(res),
+			pdata, sizeof(*pdata));
+}
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index d5f121a..8388f90 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -14,6 +14,11 @@ struct platform_device *imx_add_platform_device(const char *name, int id,
 		const struct resource *res, unsigned int num_resources,
 		const void *data, size_t size_data);
 
+#include <mach/i2c.h>
+struct platform_device *__init imx_add_imx_i2c(int id,
+		resource_size_t iobase, resource_size_t iosize, int irq,
+		const struct imxi2c_platform_data *pdata);
+
 #include <mach/mxc_nand.h>
 struct platform_device *__init imx_add_mxc_nand_v1(resource_size_t iobase,
 		int irq, const struct mxc_nand_platform_data *pdata);
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:46 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:46 +0200
Subject: [PATCH 50/61] ARM: imx: dynamically register spi_imx devices (imx25)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-51-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-mx25/devices-imx25.h    |    7 ++++
 arch/arm/mach-mx25/devices.c          |   57 ---------------------------------
 arch/arm/mach-mx25/devices.h          |    3 --
 arch/arm/plat-mxc/include/mach/mx25.h |    8 ++++-
 4 files changed, 14 insertions(+), 61 deletions(-)

diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
index 6464be4..33a834e 100644
--- a/arch/arm/mach-mx25/devices-imx25.h
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -18,3 +18,10 @@
 
 #define imx25_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
+
+#define imx25_add_spi_imx0(pdata)	\
+	imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata)
+#define imx25_add_spi_imx1(pdata)	\
+	imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata)
+#define imx25_add_spi_imx2(pdata)	\
+	imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata)
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
index 1af852a..c267087 100644
--- a/arch/arm/mach-mx25/devices.c
+++ b/arch/arm/mach-mx25/devices.c
@@ -181,63 +181,6 @@ struct platform_device mxc_usbh2 = {
 	.num_resources = ARRAY_SIZE(mxc_usbh2_resources),
 };
 
-static struct resource mxc_spi_resources0[] = {
-	{
-	       .start = 0x43fa4000,
-	       .end = 0x43fa7fff,
-	       .flags = IORESOURCE_MEM,
-	}, {
-	       .start = 14,
-	       .end = 14,
-	       .flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_spi_device0 = {
-	.name = "spi_imx",
-	.id = 0,
-	.num_resources = ARRAY_SIZE(mxc_spi_resources0),
-	.resource = mxc_spi_resources0,
-};
-
-static struct resource mxc_spi_resources1[] = {
-	{
-	       .start = 0x50010000,
-	       .end = 0x50013fff,
-	       .flags = IORESOURCE_MEM,
-	}, {
-	       .start = 13,
-	       .end = 13,
-	       .flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_spi_device1 = {
-	.name = "spi_imx",
-	.id = 1,
-	.num_resources = ARRAY_SIZE(mxc_spi_resources1),
-	.resource = mxc_spi_resources1,
-};
-
-static struct resource mxc_spi_resources2[] = {
-	{
-	       .start = 0x50004000,
-	       .end = 0x50007fff,
-	       .flags = IORESOURCE_MEM,
-	}, {
-	       .start = 0,
-	       .end = 0,
-	       .flags = IORESOURCE_IRQ,
-	},
-};
-
-struct platform_device mxc_spi_device2 = {
-	.name = "spi_imx",
-	.id = 2,
-	.num_resources = ARRAY_SIZE(mxc_spi_resources2),
-	.resource = mxc_spi_resources2,
-};
-
 static struct resource mxc_pwm_resources0[] = {
 	{
 		.start	= 0x53fe0000,
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
index f277514..1f31cbc 100644
--- a/arch/arm/mach-mx25/devices.h
+++ b/arch/arm/mach-mx25/devices.h
@@ -6,9 +6,6 @@ extern struct platform_device mxc_uart_device4;
 extern struct platform_device mxc_otg;
 extern struct platform_device otg_udc_device;
 extern struct platform_device mxc_usbh2;
-extern struct platform_device mxc_spi_device0;
-extern struct platform_device mxc_spi_device1;
-extern struct platform_device mxc_spi_device2;
 extern struct platform_device mxc_pwm_device0;
 extern struct platform_device mxc_pwm_device1;
 extern struct platform_device mxc_pwm_device2;
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index 1ebf33f..16ac6b6 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -14,6 +14,7 @@
 #define MX25_I2C1_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0x80000)
 #define MX25_I2C3_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0x84000)
 #define MX25_I2C2_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0x98000)
+#define MX25_CSPI1_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0xa4000)
 #define MX25_IOMUXC_BASE_ADDR		(MX25_AIPS1_BASE_ADDR + 0xac000)
 
 #define MX25_CRM_BASE_ADDR		(MX25_AIPS2_BASE_ADDR + 0x80000)
@@ -33,18 +34,23 @@
 #define MX25_UART1_BASE_ADDR		0x43f90000
 #define MX25_UART2_BASE_ADDR		0x43f94000
 
+#define MX25_CSPI3_BASE_ADDR		0x50004000
+#define MX25_CSPI2_BASE_ADDR		0x50010000
 #define MX25_FEC_BASE_ADDR		0x50038000
 #define MX25_NFC_BASE_ADDR		0xbb000000
 #define MX25_DRYICE_BASE_ADDR		0x53ffc000
 #define MX25_LCDC_BASE_ADDR		0x53fbc000
 
+#define MX25_INT_CSPI3		0
 #define MX25_INT_I2C1		3
 #define MX25_INT_I2C2		4
 #define MX25_INT_I2C3		10
+#define MX25_INT_CSPI2		13
+#define MX25_INT_CSPI1		14
 #define MX25_INT_DRYICE		25
-#define MX25_INT_FEC		57
 #define MX25_INT_NANDFC		33
 #define MX25_INT_LCDC		39
+#define MX25_INT_FEC		57
 
 #if defined(IMX_NEEDS_DEPRECATED_SYMBOLS)
 #define UART1_BASE_ADDR			MX25_UART1_BASE_ADDR
-- 
1.7.1



From u.kleine-koenig at pengutronix.de  Thu Jun 24 09:49:45 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 15:49:45 +0200
Subject: [PATCH 49/61] ARM: imx: dynamically register spi_imx devices (imx21)
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277387397-3467-50-git-send-email-u.kleine-koenig@pengutronix.de>

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/mach-imx/devices-imx21.h |    5 +++++
 arch/arm/mach-imx/devices.c       |    3 +--
 arch/arm/mach-imx/devices.h       |    2 +-
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index c6e5f50..de80ccd 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -14,3 +14,8 @@
 
 #define imx21_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
+
+#define imx21_add_spi_imx0(pdata)	\
+	imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata)
+#define imx21_add_spi_imx1(pdata)	\
+	imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
index f8641c2..e42eead 100644
--- a/arch/arm/mach-imx/devices.c
+++ b/arch/arm/mach-imx/devices.c
@@ -225,6 +225,7 @@ int __init imx1_register_gpios(void)
  * - i.MX21: 2 channel
  * - i.MX27: 3 channel
  */
+#ifdef CONFIG_MACH_MX27
 #define DEFINE_IMX_SPI_DEVICE(n, baseaddr, irq)					\
 	static struct resource mxc_spi_resources ## n[] = {			\
 		{								\
@@ -247,8 +248,6 @@ int __init imx1_register_gpios(void)
 
 DEFINE_IMX_SPI_DEVICE(0, MX2x_CSPI1_BASE_ADDR, MX2x_INT_CSPI1);
 DEFINE_IMX_SPI_DEVICE(1, MX2x_CSPI2_BASE_ADDR, MX2x_INT_CSPI2);
-
-#ifdef CONFIG_MACH_MX27
 DEFINE_IMX_SPI_DEVICE(2, MX27_CSPI3_BASE_ADDR, MX27_INT_CSPI3);
 #endif
 
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
index 4fe9935..c15b0de 100644
--- a/arch/arm/mach-imx/devices.h
+++ b/arch/arm/mach-imx/devices.h
@@ -34,9 +34,9 @@ extern struct platform_device mxc_otg_udc_device;
 extern struct platform_device mxc_otg_host;
 extern struct platform_device mxc_usbh1;
 extern struct platform_device mxc_usbh2;
+#ifdef CONFIG_MACH_MX27
 extern struct platform_device mxc_spi_device0;
 extern struct platform_device mxc_spi_device1;
-#ifdef CONFIG_MACH_MX27
 extern struct platform_device mxc_spi_device2;
 #endif
 extern struct platform_device mx21_usbhc_device;
-- 
1.7.1



From marek.vasut at gmail.com  Thu Jun 24 10:02:09 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 24 Jun 2010 16:02:09 +0200
Subject: [PATCH 1/4] pxa/z2: Add regulator support
Message-ID: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>

Register TPS65021 regulator in Zipit Z2.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/z2.c |   71 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 71 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index 4cba5b6..1bafb23 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -26,6 +26,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/delay.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -616,6 +617,75 @@ static inline void z2_spi_init(void) {}
 #endif
 
 /******************************************************************************
+ * Core power regulator
+ ******************************************************************************/
+#if defined(CONFIG_REGULATOR_TPS65023) || \
+	defined(CONFIG_REGULATOR_TPS65023_MODULE)
+static struct regulator_consumer_supply z2_tps65021_consumers[] = {
+	{
+		.supply	= "vcc_core",
+	}
+};
+
+static struct regulator_init_data z2_tps65021_info[] = {
+	{
+		.constraints = {
+			.name		= "vcc_core range",
+			.min_uV		= 800000,
+			.max_uV		= 1600000,
+			.always_on	= 1,
+			.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		},
+		.consumer_supplies	= z2_tps65021_consumers,
+		.num_consumer_supplies	= ARRAY_SIZE(z2_tps65021_consumers),
+	}, {
+		.constraints = {
+			.name		= "DCDC2",
+			.min_uV		= 3300000,
+			.max_uV		= 3300000,
+			.always_on	= 1,
+		},
+	}, {
+		.constraints = {
+			.name		= "DCDC3",
+			.min_uV		= 1800000,
+			.max_uV		= 1800000,
+			.always_on	= 1,
+		},
+	}, {
+		.constraints = {
+			.name		= "LDO1",
+			.min_uV		= 1000000,
+			.max_uV		= 3150000,
+			.always_on	= 1,
+		},
+	}, {
+		.constraints = {
+			.name		= "LDO2",
+			.min_uV		= 1050000,
+			.max_uV		= 3300000,
+			.always_on	= 1,
+		},
+	}
+};
+
+static struct i2c_board_info __initdata z2_pi2c_board_info[] = {
+	{
+		I2C_BOARD_INFO("tps65021", 0x48),
+		.platform_data	= &z2_tps65021_info,
+	},
+};
+
+static void __init z2_pmic_init(void)
+{
+	pxa27x_set_i2c_power_info(NULL);
+	i2c_register_board_info(1, ARRAY_AND_SIZE(z2_pi2c_board_info));
+}
+#else
+static inline void z2_pmic_init(void) {}
+#endif
+
+/******************************************************************************
  * Machine init
  ******************************************************************************/
 static void __init z2_init(void)
@@ -635,6 +705,7 @@ static void __init z2_init(void)
 	z2_pwm_init();
 	z2_leds_init();
 	z2_keys_init();
+	z2_pmic_init();
 }
 
 MACHINE_START(ZIPIT2, "Zipit Z2")
-- 
1.7.1



From marek.vasut at gmail.com  Thu Jun 24 10:02:11 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 24 Jun 2010 16:02:11 +0200
Subject: [PATCH 3/4] ARM/scoop: Add CPR register bit definitions
In-Reply-To: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1277388132-5549-3-git-send-email-marek.vasut@gmail.com>

Add bit definitions of the CPR register of the SCOOP chip into scoop.h. Also,
cleanup the GPCR definitions to match coding style.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/include/asm/hardware/scoop.h |   29 +++++++++++++++++------------
 1 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h
index 46492a6..ebb3cea 100644
--- a/arch/arm/include/asm/hardware/scoop.h
+++ b/arch/arm/include/asm/hardware/scoop.h
@@ -22,18 +22,23 @@
 #define SCOOP_GPWR 0x24
 #define SCOOP_GPRR 0x28
 
-#define SCOOP_GPCR_PA22	( 1 << 12 )
-#define SCOOP_GPCR_PA21	( 1 << 11 )
-#define SCOOP_GPCR_PA20	( 1 << 10 )
-#define SCOOP_GPCR_PA19	( 1 << 9 )
-#define SCOOP_GPCR_PA18	( 1 << 8 )
-#define SCOOP_GPCR_PA17	( 1 << 7 )
-#define SCOOP_GPCR_PA16	( 1 << 6 )
-#define SCOOP_GPCR_PA15	( 1 << 5 )
-#define SCOOP_GPCR_PA14	( 1 << 4 )
-#define SCOOP_GPCR_PA13	( 1 << 3 )
-#define SCOOP_GPCR_PA12	( 1 << 2 )
-#define SCOOP_GPCR_PA11	( 1 << 1 )
+#define SCOOP_CPR_OUT	(1 << 7)
+#define SCOOP_CPR_SD_3V	(1 << 2)
+#define SCOOP_CPR_CF_XV	(1 << 1)
+#define SCOOP_CPR_CF_3V	(1 << 0)
+
+#define SCOOP_GPCR_PA22	(1 << 12)
+#define SCOOP_GPCR_PA21	(1 << 11)
+#define SCOOP_GPCR_PA20	(1 << 10)
+#define SCOOP_GPCR_PA19	(1 << 9)
+#define SCOOP_GPCR_PA18	(1 << 8)
+#define SCOOP_GPCR_PA17	(1 << 7)
+#define SCOOP_GPCR_PA16	(1 << 6)
+#define SCOOP_GPCR_PA15	(1 << 5)
+#define SCOOP_GPCR_PA14	(1 << 4)
+#define SCOOP_GPCR_PA13	(1 << 3)
+#define SCOOP_GPCR_PA12	(1 << 2)
+#define SCOOP_GPCR_PA11	(1 << 1)
 
 struct scoop_config {
 	unsigned short io_out;
-- 
1.7.1



From marek.vasut at gmail.com  Thu Jun 24 10:02:10 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 24 Jun 2010 16:02:10 +0200
Subject: [PATCH 2/4] pxa/colibri320: Add UDC support
In-Reply-To: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1277388132-5549-2-git-send-email-marek.vasut@gmail.com>

Add support for PXA UDC.

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/colibri-pxa320.c |   40 ++++++++++++++++++++++++++++++++++++
 1 files changed, 40 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index ae835fa..99e850d 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
+#include <linux/usb/gpio_vbus.h>
 
 #include <asm/mach-types.h>
 #include <asm/sizes.h>
@@ -28,6 +29,8 @@
 #include <mach/pxafb.h>
 #include <mach/ohci.h>
 #include <mach/audio.h>
+#include <mach/pxa27x-udc.h>
+#include <mach/udc.h>
 
 #include "generic.h"
 #include "devices.h"
@@ -101,6 +104,42 @@ void __init colibri_pxa320_init_ohci(void)
 static inline void colibri_pxa320_init_ohci(void) {}
 #endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
 
+#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE)
+static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = {
+	.gpio_vbus		= mfp_to_gpio(MFP_PIN_GPIO96),
+	.gpio_pullup		= -1,
+};
+
+static struct platform_device colibri_pxa320_gpio_vbus = {
+	.name	= "gpio-vbus",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &colibri_pxa320_gpio_vbus_info,
+	},
+};
+
+static void colibri_pxa320_udc_command(int cmd)
+{
+	if (cmd == PXA2XX_UDC_CMD_CONNECT)
+		UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
+	else if (cmd == PXA2XX_UDC_CMD_DISCONNECT)
+		UP2OCR = UP2OCR_HXOE;
+}
+
+static struct pxa2xx_udc_mach_info colibri_pxa320_udc_info __initdata = {
+	.udc_command		= colibri_pxa320_udc_command,
+	.gpio_pullup		= -1,
+};
+
+static void __init colibri_pxa320_init_udc(void)
+{
+	pxa_set_udc_info(&colibri_pxa320_udc_info);
+	platform_device_register(&colibri_pxa320_gpio_vbus);
+}
+#else
+static inline void colibri_pxa320_init_udc(void) {}
+#endif
+
 static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = {
 	GPIO22_MMC1_CLK,
 	GPIO23_MMC1_CMD,
@@ -212,6 +251,7 @@ void __init colibri_pxa320_init(void)
 	colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config),
 				mfp_to_gpio(MFP_PIN_GPIO28));
 	colibri_pxa320_init_uart();
+	colibri_pxa320_init_udc();
 }
 
 MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
-- 
1.7.1



From marek.vasut at gmail.com  Thu Jun 24 10:02:12 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 24 Jun 2010 16:02:12 +0200
Subject: [PATCH 4/4] pxa/spitz: Rework spitz
In-Reply-To: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <1277388132-5549-4-git-send-email-marek.vasut@gmail.com>

This huge patch mostly shuffles code. The spitz.c file contained terrible mess
and needed a cleanup, here it is:

1) Made every part modular, components are not built in if not selected.
2) Removed loads of preprocessor goo, mostly "#ifdef MACH_AKITA .... #endif" and
   similar code. The kernel size will grow by a few kb now, but the file is much
   more readable.
3) Reworked SD/CF power setting function and made it reentrant.
4) Add ISL6271A regulator support
5) Correctly register WM8750

Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
---
 arch/arm/mach-pxa/include/mach/spitz.h |    2 -
 arch/arm/mach-pxa/spitz.c              |  813 ++++++++++++++++++--------------
 2 files changed, 470 insertions(+), 345 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
index fa1998c..685749a 100644
--- a/arch/arm/mach-pxa/include/mach/spitz.h
+++ b/arch/arm/mach-pxa/include/mach/spitz.h
@@ -185,7 +185,5 @@
 /*
  * Shared data structures
  */
-extern struct platform_device spitzscoop_device;
-extern struct platform_device spitzscoop2_device;
 extern struct platform_device spitzssp_device;
 extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index c1048a3..fa31980 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -18,14 +18,15 @@
 #include <linux/gpio_keys.h>
 #include <linux/gpio.h>
 #include <linux/leds.h>
-#include <linux/mtd/physmap.h>
 #include <linux/i2c.h>
 #include <linux/i2c/pca953x.h>
 #include <linux/spi/spi.h>
 #include <linux/spi/ads7846.h>
 #include <linux/spi/corgi_lcd.h>
+#include <linux/mtd/physmap.h>
 #include <linux/mtd/sharpsl.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -33,11 +34,9 @@
 #include <asm/mach/sharpsl_param.h>
 #include <asm/hardware/scoop.h>
 
-
 #include <mach/pxa27x.h>
 #include <mach/pxa27x-udc.h>
 #include <mach/reset.h>
-#include <plat/i2c.h>
 #include <mach/irda.h>
 #include <mach/mmc.h>
 #include <mach/ohci.h>
@@ -45,11 +44,16 @@
 #include <mach/pxa2xx_spi.h>
 #include <mach/spitz.h>
 
+#include <plat/i2c.h>
+
 #include "generic.h"
 #include "devices.h"
 #include "sharpsl.h"
 
-static unsigned long spitz_pin_config[] __initdata = {
+/******************************************************************************
+ * Pin configuration
+ ******************************************************************************/
+static unsigned long sharpslc_pin_config[] __initdata = {
 	/* Chip Selects */
 	GPIO78_nCS_2,	/* SCOOP #2 */
 	GPIO79_nCS_3,	/* NAND */
@@ -124,10 +128,13 @@ static unsigned long spitz_pin_config[] __initdata = {
 	GPIO1_GPIO | WAKEUP_ON_EDGE_FALL,	/* SPITZ_GPIO_RESET */
 };
 
-/*
- * Spitz SCOOP Device #1
- */
-static struct resource spitz_scoop_resources[] = {
+
+/******************************************************************************
+ * Scoop GPIO expander
+ ******************************************************************************/
+#if defined(CONFIG_SHARP_SCOOP) || defined(CONFIG_SHARP_SCOOP_MODULE)
+/* SCOOP Device #1 */
+static struct resource sharpslc_scoop_1_resources[] = {
 	[0] = {
 		.start		= 0x10800000,
 		.end		= 0x10800fff,
@@ -135,7 +142,7 @@ static struct resource spitz_scoop_resources[] = {
 	},
 };
 
-static struct scoop_config spitz_scoop_setup = {
+static struct scoop_config sharpslc_scoop_1_setup = {
 	.io_dir		= SPITZ_SCP_IO_DIR,
 	.io_out		= SPITZ_SCP_IO_OUT,
 	.suspend_clr	= SPITZ_SCP_SUS_CLR,
@@ -143,20 +150,18 @@ static struct scoop_config spitz_scoop_setup = {
 	.gpio_base	= SPITZ_SCP_GPIO_BASE,
 };
 
-struct platform_device spitzscoop_device = {
+struct platform_device sharpslc_scoop_1_device = {
 	.name		= "sharp-scoop",
 	.id		= 0,
 	.dev		= {
- 		.platform_data	= &spitz_scoop_setup,
+		.platform_data	= &sharpslc_scoop_1_setup,
 	},
-	.num_resources	= ARRAY_SIZE(spitz_scoop_resources),
-	.resource	= spitz_scoop_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_scoop_1_resources),
+	.resource	= sharpslc_scoop_1_resources,
 };
 
-/*
- * Spitz SCOOP Device #2
- */
-static struct resource spitz_scoop2_resources[] = {
+/* SCOOP Device #2 */
+static struct resource sharpslc_scoop_2_resources[] = {
 	[0] = {
 		.start		= 0x08800040,
 		.end		= 0x08800fff,
@@ -164,7 +169,7 @@ static struct resource spitz_scoop2_resources[] = {
 	},
 };
 
-static struct scoop_config spitz_scoop2_setup = {
+static struct scoop_config sharpslc_scoop_2_setup = {
 	.io_dir		= SPITZ_SCP2_IO_DIR,
 	.io_out		= SPITZ_SCP2_IO_OUT,
 	.suspend_clr	= SPITZ_SCP2_SUS_CLR,
@@ -172,82 +177,110 @@ static struct scoop_config spitz_scoop2_setup = {
 	.gpio_base	= SPITZ_SCP2_GPIO_BASE,
 };
 
-struct platform_device spitzscoop2_device = {
+struct platform_device sharpslc_scoop_2_device = {
 	.name		= "sharp-scoop",
 	.id		= 1,
 	.dev		= {
- 		.platform_data	= &spitz_scoop2_setup,
+		.platform_data	= &sharpslc_scoop_2_setup,
 	},
-	.num_resources	= ARRAY_SIZE(spitz_scoop2_resources),
-	.resource	= spitz_scoop2_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_scoop_2_resources),
+	.resource	= sharpslc_scoop_2_resources,
 };
 
-#define SPITZ_PWR_SD 0x01
-#define SPITZ_PWR_CF 0x02
+static void __init sharpslc_scoop_init(void)
+{
+	platform_device_register(&sharpslc_scoop_1_device);
+
+	/* Akita doesn't have the second SCOOP chip */
+	if (!machine_is_akita())
+		platform_device_register(&sharpslc_scoop_2_device);
+}
 
 /* Power control is shared with between one of the CF slots and SD */
-static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr)
+static void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr)
 {
-	unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR);
+	unsigned short cpr;
+	unsigned long flags;
 
-	if (new_cpr & 0x0007) {
+	if (new_cpr & 0x7) {
 		gpio_set_value(SPITZ_GPIO_CF_POWER, 1);
-		if (!(cpr & 0x0002) && !(cpr & 0x0004))
-		        mdelay(5);
-		if (device == SPITZ_PWR_CF)
-		        cpr |= 0x0002;
-		if (device == SPITZ_PWR_SD)
-		        cpr |= 0x0004;
-	        write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
-	} else {
-		if (device == SPITZ_PWR_CF)
-		        cpr &= ~0x0002;
-		if (device == SPITZ_PWR_SD)
-		        cpr &= ~0x0004;
-		if (!(cpr & 0x0002) && !(cpr & 0x0004)) {
-			write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, 0x0000);
-		        mdelay(1);
-			gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
-		} else {
-		        write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
-		}
+		mdelay(5);
+	}
+
+	local_irq_save(flags);
+
+	cpr = read_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR);
+
+	if (enable & new_cpr)
+		cpr |= new_cpr;
+	else
+		cpr &= ~enable;
+
+	write_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR, cpr);
+
+	local_irq_restore(flags);
+
+	if (!(cpr & 0x7)) {
+		mdelay(1);
+		gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
 	}
 }
 
-static void spitz_pcmcia_pwr(struct device *scoop, unsigned short cpr, int nr)
+#else
+static inline void sharpslc_scoop_init(void) {}
+static inline void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr) {}
+#endif
+
+/******************************************************************************
+ * PCMCIA
+ ******************************************************************************/
+#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
+static void sharpslc_pcmcia_pwr(struct device *scoop, uint16_t cpr, int nr)
 {
 	/* Only need to override behaviour for slot 0 */
 	if (nr == 0)
-		spitz_card_pwr_ctrl(SPITZ_PWR_CF, cpr);
+		sharpslc_card_pwr_ctrl(
+			cpr & (SCOOP_CPR_CF_3V | SCOOP_CPR_CF_XV), cpr);
 	else
 		write_scoop_reg(scoop, SCOOP_CPR, cpr);
 }
 
-static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
-{
-	.dev        = &spitzscoop_device.dev,
-	.irq        = SPITZ_IRQ_GPIO_CF_IRQ,
-	.cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
-	.cd_irq_str = "PCMCIA0 CD",
-},{
-	.dev        = &spitzscoop2_device.dev,
-	.irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
-	.cd_irq     = -1,
-},
+static struct scoop_pcmcia_dev sharpslc_pcmcia_scoop[] = {
+	{
+		.dev        = &sharpslc_scoop_1_device.dev,
+		.irq        = SPITZ_IRQ_GPIO_CF_IRQ,
+		.cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
+		.cd_irq_str = "PCMCIA0 CD",
+	}, {
+		.dev        = &sharpslc_scoop_2_device.dev,
+		.irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
+		.cd_irq     = -1,
+	},
 };
 
-static struct scoop_pcmcia_config spitz_pcmcia_config = {
-	.devs         = &spitz_pcmcia_scoop[0],
-	.num_devs     = 2,
-	.power_ctrl   = spitz_pcmcia_pwr,
+static struct scoop_pcmcia_config sharpslc_pcmcia_config = {
+	.devs		= &sharpslc_pcmcia_scoop[0],
+	.num_devs	= 2,
+	.power_ctrl	= sharpslc_pcmcia_pwr,
 };
 
-EXPORT_SYMBOL(spitzscoop_device);
-EXPORT_SYMBOL(spitzscoop2_device);
+static void __init sharpslc_pcmcia_init(void)
+{
+	/* Akita has only one PCMCIA slot used */
+	if (machine_is_akita())
+		sharpslc_pcmcia_config.num_devs = 1;
+
+	platform_scoop_config = &sharpslc_pcmcia_config;
+}
+#else
+static inline void sharpslc_pcmcia_init(void) {}
+#endif
+
+/******************************************************************************
+ * GPIO keyboard
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
 
-/*
- * Spitz Keyboard Device
- */
 #define SPITZ_KEY_CALENDAR	KEY_F1
 #define SPITZ_KEY_ADDRESS	KEY_F2
 #define SPITZ_KEY_FN		KEY_F3
@@ -263,7 +296,7 @@ EXPORT_SYMBOL(spitzscoop2_device);
 #define SPITZ_KEY_OK		KEY_F11
 #define SPITZ_KEY_MENU		KEY_F12
 
-static const uint32_t spitzkbd_keymap[] = {
+static const uint32_t sharpslc_keymap[] = {
 	KEY(0, 0, KEY_LEFTCTRL),
 	KEY(0, 1, KEY_1),
 	KEY(0, 2, KEY_3),
@@ -330,37 +363,48 @@ static const uint32_t spitzkbd_keymap[] = {
 	KEY(6, 8, KEY_RIGHT),
 };
 
-static const struct matrix_keymap_data spitzkbd_keymap_data = {
-	.keymap		= spitzkbd_keymap,
-	.keymap_size	= ARRAY_SIZE(spitzkbd_keymap),
+static const struct matrix_keymap_data sharpslc_keymap_data = {
+	.keymap		= sharpslc_keymap,
+	.keymap_size	= ARRAY_SIZE(sharpslc_keymap),
 };
 
-static const uint32_t spitzkbd_row_gpios[] =
+static const uint32_t sharpslc_row_gpios[] =
 		{ 12, 17, 91, 34, 36, 38, 39 };
-static const uint32_t spitzkbd_col_gpios[] =
+static const uint32_t sharpslc_col_gpios[] =
 		{ 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 };
 
-static struct matrix_keypad_platform_data spitzkbd_pdata = {
-	.keymap_data		= &spitzkbd_keymap_data,
-	.row_gpios		= spitzkbd_row_gpios,
-	.col_gpios		= spitzkbd_col_gpios,
-	.num_row_gpios		= ARRAY_SIZE(spitzkbd_row_gpios),
-	.num_col_gpios		= ARRAY_SIZE(spitzkbd_col_gpios),
+static struct matrix_keypad_platform_data sharpslc_mkp_pdata = {
+	.keymap_data		= &sharpslc_keymap_data,
+	.row_gpios		= sharpslc_row_gpios,
+	.col_gpios		= sharpslc_col_gpios,
+	.num_row_gpios		= ARRAY_SIZE(sharpslc_row_gpios),
+	.num_col_gpios		= ARRAY_SIZE(sharpslc_col_gpios),
 	.col_scan_delay_us	= 10,
 	.debounce_ms		= 10,
 	.wakeup			= 1,
 };
 
-static struct platform_device spitzkbd_device = {
+static struct platform_device sharpslc_mkp_device = {
 	.name		= "matrix-keypad",
 	.id		= -1,
 	.dev		= {
-		.platform_data = &spitzkbd_pdata,
+		.platform_data	= &sharpslc_mkp_pdata,
 	},
 };
 
+static void __init sharpslc_mkp_init(void)
+{
+	platform_device_register(&sharpslc_mkp_device);
+}
+#else
+static inline void sharpslc_mkp_init(void) {}
+#endif
 
-static struct gpio_keys_button spitz_gpio_keys[] = {
+/******************************************************************************
+ * GPIO keys
+ ******************************************************************************/
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button sharpslc_gpio_keys[] = {
 	{
 		.type	= EV_PWR,
 		.code	= KEY_SUSPEND,
@@ -383,27 +427,35 @@ static struct gpio_keys_button spitz_gpio_keys[] = {
 	},
 };
 
-static struct gpio_keys_platform_data spitz_gpio_keys_platform_data = {
-	.buttons	= spitz_gpio_keys,
-	.nbuttons	= ARRAY_SIZE(spitz_gpio_keys),
+static struct gpio_keys_platform_data sharpslc_gpio_keys_platform_data = {
+	.buttons	= sharpslc_gpio_keys,
+	.nbuttons	= ARRAY_SIZE(sharpslc_gpio_keys),
 };
 
-static struct platform_device spitz_gpio_keys_device = {
+static struct platform_device sharpslc_gpio_keys_device = {
 	.name	= "gpio-keys",
 	.id	= -1,
 	.dev	= {
-		.platform_data	= &spitz_gpio_keys_platform_data,
+		.platform_data	= &sharpslc_gpio_keys_platform_data,
 	},
 };
 
+static void __init sharpslc_keys_init(void)
+{
+	platform_device_register(&sharpslc_gpio_keys_device);
+}
+#else
+static inline void sharpslc_keys_init(void) {}
+#endif
 
-/*
- * Spitz LEDs
- */
-static struct gpio_led spitz_gpio_leds[] = {
+/******************************************************************************
+ * LEDs
+ ******************************************************************************/
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static struct gpio_led sharpslc_gpio_leds[] = {
 	{
 		.name			= "spitz:amber:charge",
-		.default_trigger	= "sharpsl-charge",
+		.default_trigger	= "sharpslc-charge",
 		.gpio			= SPITZ_GPIO_LED_ORANGE,
 	},
 	{
@@ -413,25 +465,32 @@ static struct gpio_led spitz_gpio_leds[] = {
 	},
 };
 
-static struct gpio_led_platform_data spitz_gpio_leds_info = {
-	.leds		= spitz_gpio_leds,
-	.num_leds	= ARRAY_SIZE(spitz_gpio_leds),
+static struct gpio_led_platform_data sharpslc_gpio_leds_info = {
+	.leds		= sharpslc_gpio_leds,
+	.num_leds	= ARRAY_SIZE(sharpslc_gpio_leds),
 };
 
-static struct platform_device spitzled_device = {
+static struct platform_device sharpslc_led_device = {
 	.name		= "leds-gpio",
 	.id		= -1,
 	.dev		= {
-		.platform_data = &spitz_gpio_leds_info,
+		.platform_data	= &sharpslc_gpio_leds_info,
 	},
 };
 
-#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
-static struct pxa2xx_spi_master spitz_spi_info = {
-	.num_chipselect	= 3,
-};
+static void __init sharpslc_leds_init(void)
+{
+	platform_device_register(&sharpslc_led_device);
+}
+#else
+static inline void sharpslc_leds_init(void) {}
+#endif
 
-static void spitz_wait_for_hsync(void)
+/******************************************************************************
+ * SSP Devices
+ ******************************************************************************/
+#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
+static void sharpslc_ads7846_wait_for_hsync(void)
 {
 	while (gpio_get_value(SPITZ_GPIO_HSYNC))
 		cpu_relax();
@@ -440,21 +499,21 @@ static void spitz_wait_for_hsync(void)
 		cpu_relax();
 }
 
-static struct ads7846_platform_data spitz_ads7846_info = {
+static struct ads7846_platform_data sharpslc_ads7846_info = {
 	.model			= 7846,
 	.vref_delay_usecs	= 100,
 	.x_plate_ohms		= 419,
 	.y_plate_ohms		= 486,
 	.pressure_max		= 1024,
 	.gpio_pendown		= SPITZ_GPIO_TP_INT,
-	.wait_for_sync		= spitz_wait_for_hsync,
+	.wait_for_sync		= sharpslc_ads7846_wait_for_hsync,
 };
 
-static struct pxa2xx_spi_chip spitz_ads7846_chip = {
+static struct pxa2xx_spi_chip sharpslc_ads7846_chip = {
 	.gpio_cs		= SPITZ_GPIO_ADS7846_CS,
 };
 
-static void spitz_bl_kick_battery(void)
+static void sharpslc_bl_kick_battery(void)
 {
 	void (*kick_batt)(void);
 
@@ -465,93 +524,109 @@ static void spitz_bl_kick_battery(void)
 	}
 }
 
-static struct corgi_lcd_platform_data spitz_lcdcon_info = {
+static struct corgi_lcd_platform_data sharpslc_lcdcon_info = {
 	.init_mode		= CORGI_LCD_MODE_VGA,
 	.max_intensity		= 0x2f,
 	.default_intensity	= 0x1f,
 	.limit_mask		= 0x0b,
 	.gpio_backlight_cont	= SPITZ_GPIO_BACKLIGHT_CONT,
 	.gpio_backlight_on	= SPITZ_GPIO_BACKLIGHT_ON,
-	.kick_battery		= spitz_bl_kick_battery,
+	.kick_battery		= sharpslc_bl_kick_battery,
 };
 
-static struct pxa2xx_spi_chip spitz_lcdcon_chip = {
+static struct pxa2xx_spi_chip sharpslc_lcdcon_chip = {
 	.gpio_cs	= SPITZ_GPIO_LCDCON_CS,
 };
 
-static struct pxa2xx_spi_chip spitz_max1111_chip = {
+static struct pxa2xx_spi_chip sharpslc_max1111_chip = {
 	.gpio_cs	= SPITZ_GPIO_MAX1111_CS,
 };
 
-static struct spi_board_info spitz_spi_devices[] = {
+static struct spi_board_info sharpslc_spi_devices[] = {
 	{
-		.modalias	= "ads7846",
-		.max_speed_hz	= 1200000,
-		.bus_num	= 2,
-		.chip_select	= 0,
-		.platform_data	= &spitz_ads7846_info,
-		.controller_data= &spitz_ads7846_chip,
-		.irq		= gpio_to_irq(SPITZ_GPIO_TP_INT),
+		.modalias		= "ads7846",
+		.max_speed_hz		= 1200000,
+		.bus_num		= 2,
+		.chip_select		= 0,
+		.platform_data		= &sharpslc_ads7846_info,
+		.controller_data	= &sharpslc_ads7846_chip,
+		.irq			= gpio_to_irq(SPITZ_GPIO_TP_INT),
 	}, {
-		.modalias	= "corgi-lcd",
-		.max_speed_hz	= 50000,
-		.bus_num	= 2,
-		.chip_select	= 1,
-		.platform_data	= &spitz_lcdcon_info,
-		.controller_data= &spitz_lcdcon_chip,
+		.modalias		= "corgi-lcd",
+		.max_speed_hz		= 50000,
+		.bus_num		= 2,
+		.chip_select		= 1,
+		.platform_data		= &sharpslc_lcdcon_info,
+		.controller_data	= &sharpslc_lcdcon_chip,
 	}, {
-		.modalias	= "max1111",
-		.max_speed_hz	= 450000,
-		.bus_num	= 2,
-		.chip_select	= 2,
-		.controller_data= &spitz_max1111_chip,
+		.modalias		= "max1111",
+		.max_speed_hz		= 450000,
+		.bus_num		= 2,
+		.chip_select		= 2,
+		.controller_data	= &sharpslc_max1111_chip,
 	},
 };
 
-static void __init spitz_init_spi(void)
+static struct pxa2xx_spi_master sharpslc_spi_info = {
+	.num_chipselect	= 3,
+};
+
+static void __init sharpslc_spi_init(void)
 {
+	struct corgi_lcd_platform_data *lcd_data = &sharpslc_lcdcon_info;
+
 	if (machine_is_akita()) {
-		spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
-		spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
+		lcd_data->gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
+		lcd_data->gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
 	}
 
-	pxa2xx_set_spi_info(2, &spitz_spi_info);
-	spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
+	pxa2xx_set_spi_info(2, &sharpslc_spi_info);
+	spi_register_board_info(ARRAY_AND_SIZE(sharpslc_spi_devices));
 }
 #else
-static inline void spitz_init_spi(void) {}
+static inline void sharpslc_spi_init(void) {}
 #endif
 
+/******************************************************************************
+ * SD/MMC card controller
+ ******************************************************************************/
+#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
 /*
- * MMC/SD Device
- *
- * The card detect interrupt isn't debounced so we delay it by 250ms
- * to give the card a chance to fully insert/eject.
+ * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
+ * give the card a chance to fully insert/eject.
  */
-static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
+static void sharpslc_mci_setpower(struct device *dev, unsigned int vdd)
 {
 	struct pxamci_platform_data* p_d = dev->platform_data;
 
-	if (( 1 << vdd) & p_d->ocr_mask)
-		spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0004);
+	if ((1 << vdd) & p_d->ocr_mask)
+		sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
 	else
-		spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0000);
+		sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
 }
 
-static struct pxamci_platform_data spitz_mci_platform_data = {
+static struct pxamci_platform_data sharpslc_mci_platform_data = {
 	.detect_delay_ms	= 250,
 	.ocr_mask		= MMC_VDD_32_33|MMC_VDD_33_34,
-	.setpower 		= spitz_mci_setpower,
+	.setpower		= sharpslc_mci_setpower,
 	.gpio_card_detect	= SPITZ_GPIO_nSD_DETECT,
 	.gpio_card_ro		= SPITZ_GPIO_nSD_WP,
 	.gpio_power		= -1,
 };
 
+static void __init sharpslc_mmc_init(void)
+{
+	pxa_set_mci_info(&sharpslc_mci_platform_data);
+}
+#else
+static inline void sharpslc_mmc_init(void) {}
+#endif
 
-/*
- * USB Host (OHCI)
- */
-static int spitz_ohci_init(struct device *dev)
+/******************************************************************************
+ * USB Host
+ ******************************************************************************/
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static int sharpslc_ohci_init(struct device *dev)
 {
 	int err;
 
@@ -559,88 +634,114 @@ static int spitz_ohci_init(struct device *dev)
 	if (err)
 		return err;
 
-	/* Only Port 2 is connected
-	 * Setup USB Port 2 Output Control Register
-	 */
+	/* Only Port 2 is connected, setup USB Port 2 Output Control Register */
 	UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
 
 	return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1);
 }
 
-static void spitz_ohci_exit(struct device *dev)
+static void sharpslc_ohci_exit(struct device *dev)
 {
 	gpio_free(SPITZ_GPIO_USB_HOST);
 }
 
-static struct pxaohci_platform_data spitz_ohci_platform_data = {
+static struct pxaohci_platform_data sharpslc_ohci_platform_data = {
 	.port_mode	= PMM_NPS_MODE,
-	.init		= spitz_ohci_init,
-	.exit		= spitz_ohci_exit,
+	.init		= sharpslc_ohci_init,
+	.exit		= sharpslc_ohci_exit,
 	.flags		= ENABLE_PORT_ALL | NO_OC_PROTECTION,
 	.power_budget	= 150,
 };
 
+static void __init sharpslc_uhc_init(void)
+{
+	pxa_set_ohci_info(&sharpslc_ohci_platform_data);
+}
+#else
+static inline void sharpslc_uhc_init(void) {}
+#endif
 
-/*
- * Irda
- */
-
-static struct pxaficp_platform_data spitz_ficp_platform_data = {
-/* .gpio_pwdown is set in spitz_init() and akita_init() accordingly */
+/******************************************************************************
+ * IrDA
+ ******************************************************************************/
+#if defined(CONFIG_PXA_FICP) || defined(CONFIG_PXA_FICP_MODULE)
+static struct pxaficp_platform_data sharpslc_ficp_platform_data = {
 	.transceiver_cap	= IR_SIRMODE | IR_OFF,
 };
 
+static void __init sharpslc_irda_init(void)
+{
+	if (machine_is_akita())
+		sharpslc_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
+	else
+		sharpslc_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
 
-/*
- * Spitz PXA Framebuffer
- */
+	pxa_set_ficp_info(&sharpslc_ficp_platform_data);
+}
+#else
+static inline void sharpslc_irda_init(void) {}
+#endif
 
-static struct pxafb_mode_info spitz_pxafb_modes[] = {
-{
-	.pixclock       = 19231,
-	.xres           = 480,
-	.yres           = 640,
-	.bpp            = 16,
-	.hsync_len      = 40,
-	.left_margin    = 46,
-	.right_margin   = 125,
-	.vsync_len      = 3,
-	.upper_margin   = 1,
-	.lower_margin   = 0,
-	.sync           = 0,
-},{
-	.pixclock       = 134617,
-	.xres           = 240,
-	.yres           = 320,
-	.bpp            = 16,
-	.hsync_len      = 20,
-	.left_margin    = 20,
-	.right_margin   = 46,
-	.vsync_len      = 2,
-	.upper_margin   = 1,
-	.lower_margin   = 0,
-	.sync           = 0,
-},
-};
-
-static struct pxafb_mach_info spitz_pxafb_info = {
-	.modes          = &spitz_pxafb_modes[0],
-	.num_modes      = 2,
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
+static struct pxafb_mode_info sharpslc_pxafb_modes[] = {
+	{
+		.pixclock       = 19231,
+		.xres           = 480,
+		.yres           = 640,
+		.bpp            = 16,
+		.hsync_len      = 40,
+		.left_margin    = 46,
+		.right_margin   = 125,
+		.vsync_len      = 3,
+		.upper_margin   = 1,
+		.lower_margin   = 0,
+		.sync           = 0,
+	}, {
+		.pixclock       = 134617,
+		.xres           = 240,
+		.yres           = 320,
+		.bpp            = 16,
+		.hsync_len      = 20,
+		.left_margin    = 20,
+		.right_margin   = 46,
+		.vsync_len      = 2,
+		.upper_margin   = 1,
+		.lower_margin   = 0,
+		.sync           = 0,
+	},
+};
+
+static struct pxafb_mach_info sharpslc_pxafb_info = {
+	.modes          = sharpslc_pxafb_modes,
+	.num_modes      = ARRAY_SIZE(sharpslc_pxafb_modes),
 	.fixed_modes    = 1,
 	.lcd_conn	= LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
 };
 
-static struct mtd_partition sharpsl_nand_partitions[] = {
+static void __init sharpslc_lcd_init(void)
+{
+	set_pxa_fb_info(&sharpslc_pxafb_info);
+}
+#else
+static inline void sharpslc_lcd_init(void) {}
+#endif
+
+/******************************************************************************
+ * Framebuffer
+ ******************************************************************************/
+#if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE)
+static struct mtd_partition sharpslc_nand_partitions[] = {
 	{
 		.name = "System Area",
 		.offset = 0,
 		.size = 7 * 1024 * 1024,
-	},
-	{
+	}, {
 		.name = "Root Filesystem",
 		.offset = 7 * 1024 * 1024,
-	},
-	{
+	}, {
 		.name = "Home Filesystem",
 		.offset = MTDPART_OFS_APPEND,
 		.size = MTDPART_SIZ_FULL,
@@ -649,37 +750,72 @@ static struct mtd_partition sharpsl_nand_partitions[] = {
 
 static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
 
-static struct nand_bbt_descr sharpsl_bbt = {
-	.options = 0,
-	.offs = 4,
-	.len = 2,
-	.pattern = scan_ff_pattern
+static struct nand_bbt_descr sharpslc_nand_bbt = {
+	.options	= 0,
+	.offs		= 4,
+	.len		= 2,
+	.pattern	= scan_ff_pattern
+};
+
+static struct nand_ecclayout sharpslc_akita_oobinfo = {
+	.oobfree	= { {0x08, 0x09} },
+	.eccbytes	= 24,
+	.eccpos		= {
+			0x05, 0x01, 0x02, 0x03, 0x06, 0x07, 0x15, 0x11,
+			0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
+			0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37,
+	},
 };
 
-static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
-	.badblock_pattern	= &sharpsl_bbt,
-	.partitions		= sharpsl_nand_partitions,
-	.nr_partitions		= ARRAY_SIZE(sharpsl_nand_partitions),
+static struct sharpsl_nand_platform_data sharpslc_nand_pdata = {
+	.badblock_pattern	= &sharpslc_nand_bbt,
+	.partitions		= sharpslc_nand_partitions,
+	.nr_partitions		= ARRAY_SIZE(sharpslc_nand_partitions),
 };
 
-static struct resource sharpsl_nand_resources[] = {
+static struct resource sharpslc_nand_resources[] = {
 	{
-		.start	= 0x0C000000,
-		.end	= 0x0C000FFF,
+		.start	= PXA_CS3_PHYS,
+		.end	= PXA_CS3_PHYS + SZ_4K - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 
-static struct platform_device sharpsl_nand_device = {
+static struct platform_device sharpslc_nand_device = {
 	.name		= "sharpsl-nand",
 	.id		= -1,
-	.resource	= sharpsl_nand_resources,
-	.num_resources	= ARRAY_SIZE(sharpsl_nand_resources),
-	.dev.platform_data	= &sharpsl_nand_platform_data,
+	.resource	= sharpslc_nand_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_nand_resources),
+	.dev		= {
+		.platform_data	= &sharpslc_nand_pdata,
+	}
 };
 
+static void __init sharpslc_nand_init(void)
+{
+	if (machine_is_spitz()) {
+		sharpslc_nand_partitions[1].size = 5 * 1024 * 1024;
+	} else if (machine_is_akita()) {
+		sharpslc_nand_partitions[1].size = 58 * 1024 * 1024;
+		sharpslc_nand_bbt.len = 1;
+		sharpslc_nand_pdata.ecc_layout = &sharpslc_akita_oobinfo;
+	} else if (machine_is_borzoi()) {
+		sharpslc_nand_partitions[1].size = 32 * 1024 * 1024;
+		sharpslc_nand_bbt.len = 1;
+		sharpslc_nand_pdata.ecc_layout = &sharpslc_akita_oobinfo;
+	}
+
+	platform_device_register(&sharpslc_nand_device);
+}
+#else
+static inline void sharpslc_nand_init(void) {}
+#endif
 
-static struct mtd_partition sharpsl_rom_parts[] = {
+/******************************************************************************
+ * NOR Flash
+ ******************************************************************************/
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static struct mtd_partition sharpslc_rom_parts[] = {
 	{
 		.name	="Boot PROM Filesystem",
 		.offset	= 0x00140000,
@@ -687,161 +823,152 @@ static struct mtd_partition sharpsl_rom_parts[] = {
 	},
 };
 
-static struct physmap_flash_data sharpsl_rom_data = {
+static struct physmap_flash_data sharpslc_rom_data = {
 	.width		= 2,
-	.nr_parts	= ARRAY_SIZE(sharpsl_rom_parts),
-	.parts		= sharpsl_rom_parts,
+	.nr_parts	= ARRAY_SIZE(sharpslc_rom_parts),
+	.parts		= sharpslc_rom_parts,
 };
 
-static struct resource sharpsl_rom_resources[] = {
+static struct resource sharpslc_rom_resources[] = {
 	{
-		.start	= 0x00000000,
-		.end	= 0x007fffff,
+		.start	= PXA_CS0_PHYS,
+		.end	= PXA_CS0_PHYS + SZ_8M - 1,
 		.flags	= IORESOURCE_MEM,
 	},
 };
 
-static struct platform_device sharpsl_rom_device = {
-	.name	= "physmap-flash",
-	.id	= -1,
-	.resource = sharpsl_rom_resources,
-	.num_resources = ARRAY_SIZE(sharpsl_rom_resources),
-	.dev.platform_data = &sharpsl_rom_data,
-};
-
-static struct platform_device *devices[] __initdata = {
-	&spitzscoop_device,
-	&spitzkbd_device,
-	&spitz_gpio_keys_device,
-	&spitzled_device,
-	&sharpsl_nand_device,
-	&sharpsl_rom_device,
+static struct platform_device sharpslc_rom_device = {
+	.name		= "physmap-flash",
+	.id		= -1,
+	.resource	= sharpslc_rom_resources,
+	.num_resources	= ARRAY_SIZE(sharpslc_rom_resources),
+	.dev		= {
+		.platform_data	= &sharpslc_rom_data,
+	},
 };
 
-static void spitz_poweroff(void)
+static void __init sharpslc_nor_init(void)
 {
-	arm_machine_restart('g', NULL);
+	platform_device_register(&sharpslc_rom_device);
 }
+#else
+static inline void sharpslc_nor_init(void) {}
+#endif
 
-static void spitz_restart(char mode, const char *cmd)
-{
-	/* Bootloader magic for a reboot */
-	if((MSC0 & 0xffff0000) == 0x7ff00000)
-		MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
-
-	spitz_poweroff();
-}
+/******************************************************************************
+ * GPIO expander
+ ******************************************************************************/
+#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
+static struct pca953x_platform_data akita_pca953x_pdata = {
+	.gpio_base		= AKITA_IOEXP_GPIO_BASE,
+};
 
-static void __init common_init(void)
-{
-	init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
-	pm_power_off = spitz_poweroff;
-	arm_pm_restart = spitz_restart;
+static struct i2c_board_info sharpslc_i2c_devs[] = {
+	{
+		.type		= "wm8750",
+		.addr		= 0x1b,
+	}, {
+		.type		= "max7310",
+		.addr		= 0x18,
+		.platform_data	= &akita_pca953x_pdata,
+	},
+};
 
-	if (machine_is_spitz()) {
-		sharpsl_nand_partitions[1].size = 5 * 1024 * 1024;
-	} else if (machine_is_akita()) {
-		sharpsl_nand_partitions[1].size = 58 * 1024 * 1024;
-	} else if (machine_is_borzoi()) {
-		sharpsl_nand_partitions[1].size = 32 * 1024 * 1024;
+static struct regulator_consumer_supply isl6271a_consumers[] = {
+	{
+		.supply	= "vcc_core",
 	}
+};
 
-	PMCR = 0x00;
-
-	/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
-	PCFR |= PCFR_OPDE;
+static struct regulator_init_data isl6271a_info[] = {
+	{
+		.constraints = {
+			.name		= "vcc_core range",
+			.min_uV		= 850000,
+			.max_uV		= 1600000,
+			.always_on	= 1,
+			.valid_ops_mask	= REGULATOR_CHANGE_VOLTAGE,
+		},
+	.consumer_supplies	= isl6271a_consumers,
+	.num_consumer_supplies	= ARRAY_SIZE(isl6271a_consumers),
+	}
+};
 
-	pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
+static struct i2c_board_info sharpslc_pi2c_devs[] = {
+	{
+		.type		= "isl6271a",
+		.addr		= 0x0c,
+		.platform_data	= &isl6271a_info,
+	},
+};
 
-	pxa_set_ffuart_info(NULL);
-	pxa_set_btuart_info(NULL);
-	pxa_set_stuart_info(NULL);
+static void __init sharpslc_i2c_init(void)
+{
+	int size = ARRAY_SIZE(sharpslc_i2c_devs);
 
-	spitz_init_spi();
+	/* Only Akita has the max7310 chip */
+	if (!machine_is_akita())
+		size--;
 
-	platform_add_devices(devices, ARRAY_SIZE(devices));
-	pxa_set_mci_info(&spitz_mci_platform_data);
-	pxa_set_ohci_info(&spitz_ohci_platform_data);
-	pxa_set_ficp_info(&spitz_ficp_platform_data);
-	set_pxa_fb_info(&spitz_pxafb_info);
 	pxa_set_i2c_info(NULL);
+	pxa27x_set_i2c_power_info(NULL);
+	i2c_register_board_info(0, sharpslc_i2c_devs, size);
+	i2c_register_board_info(1, ARRAY_AND_SIZE(sharpslc_pi2c_devs));
 }
-
-#if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI)
-static struct nand_bbt_descr sharpsl_akita_bbt = {
-	.options = 0,
-	.offs = 4,
-	.len = 1,
-	.pattern = scan_ff_pattern
-};
-
-static struct nand_ecclayout akita_oobinfo = {
-	.eccbytes = 24,
-	.eccpos = {
-		   0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
-		   0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
-		   0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
-	.oobfree = {{0x08, 0x09}}
-};
+#else
+static inline void sharpslc_i2c_init(void) {}
 #endif
 
-#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
-static void __init spitz_init(void)
+/******************************************************************************
+ * Machine init
+ ******************************************************************************/
+static void sharpslc_poweroff(void)
 {
-	spitz_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
-
-#ifdef CONFIG_MACH_BORZOI
-	if (machine_is_borzoi()) {
-		sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
-		sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
-	}
-#endif
-
-	platform_scoop_config = &spitz_pcmcia_config;
-
-	common_init();
-
-	platform_device_register(&spitzscoop2_device);
+	arm_machine_restart('g', NULL);
 }
-#endif
 
-#ifdef CONFIG_MACH_AKITA
-/*
- * Akita IO Expander
- */
-static struct pca953x_platform_data akita_ioexp = {
-	.gpio_base		= AKITA_IOEXP_GPIO_BASE,
-};
+static void sharpslc_restart(char mode, const char *cmd)
+{
+	/* Bootloader magic for a reboot */
+	if ((MSC0 & 0xffff0000) == 0x7ff00000)
+		MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
 
-static struct i2c_board_info akita_i2c_board_info[] = {
-	{
-		.type		= "max7310",
-		.addr		= 0x18,
-		.platform_data	= &akita_ioexp,
-	}, {
-		.type		= "wm8750",
-		.addr		= 0x1b,
-	},
-};
+	sharpslc_poweroff();
+}
 
-static void __init akita_init(void)
+static void __init sharpslc_init(void)
 {
-	spitz_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
+	init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
+	pm_power_off = sharpslc_poweroff;
+	arm_pm_restart = sharpslc_restart;
+
+	PMCR = 0x00;
 
-	sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
-	sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
+	/* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
+	PCFR |= PCFR_OPDE;
 
-	/* We just pretend the second element of the array doesn't exist */
-	spitz_pcmcia_config.num_devs = 1;
-	platform_scoop_config = &spitz_pcmcia_config;
+	pxa2xx_mfp_config(ARRAY_AND_SIZE(sharpslc_pin_config));
 
-	i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_board_info));
+	pxa_set_ffuart_info(NULL);
+	pxa_set_btuart_info(NULL);
+	pxa_set_stuart_info(NULL);
 
-	common_init();
+	sharpslc_spi_init();
+	sharpslc_scoop_init();
+	sharpslc_mkp_init();
+	sharpslc_keys_init();
+	sharpslc_leds_init();
+	sharpslc_mmc_init();
+	sharpslc_pcmcia_init();
+	sharpslc_irda_init();
+	sharpslc_uhc_init();
+	sharpslc_lcd_init();
+	sharpslc_nor_init();
+	sharpslc_nand_init();
+	sharpslc_i2c_init();
 }
-#endif
 
-static void __init fixup_spitz(struct machine_desc *desc,
+static void __init sharpslc_fixup(struct machine_desc *desc,
 		struct tag *tags, char **cmdline, struct meminfo *mi)
 {
 	sharpsl_save_param();
@@ -855,10 +982,10 @@ static void __init fixup_spitz(struct machine_desc *desc,
 MACHINE_START(SPITZ, "SHARP Spitz")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= spitz_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
@@ -867,10 +994,10 @@ MACHINE_END
 MACHINE_START(BORZOI, "SHARP Borzoi")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= spitz_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
@@ -879,10 +1006,10 @@ MACHINE_END
 MACHINE_START(AKITA, "SHARP Akita")
 	.phys_io	= 0x40000000,
 	.io_pg_offst	= (io_p2v(0x40000000) >> 18) & 0xfffc,
-	.fixup		= fixup_spitz,
+	.fixup		= sharpslc_fixup,
 	.map_io		= pxa_map_io,
 	.init_irq	= pxa27x_init_irq,
-	.init_machine	= akita_init,
+	.init_machine	= sharpslc_init,
 	.timer		= &pxa_timer,
 MACHINE_END
 #endif
-- 
1.7.1



From grinberg at compulab.co.il  Thu Jun 24 10:04:48 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Thu, 24 Jun 2010 17:04:48 +0300
Subject: [PATCH v2] otg/ulpi.c : fix register write
In-Reply-To: <1277311435-12027-1-git-send-email-eric@eukrea.com>
References: <1277311435-12027-1-git-send-email-eric@eukrea.com>
Message-ID: <4C236600.2030605@compulab.co.il>


On 06/23/10 19:43, Eric B?nard wrote:
> ulpi_set_vbus and ulpi_set_flags are using ULPI_SET(register) to write
> to the PHY's registers, which means we can only set bits in the PHY's
> register and not clear them.
> By directly using the address of the register without any offset, we
> now get the expected behaviour for these functions.
>
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> Cc: Daniel Mack <daniel at caiaq.de>
> Cc: linux-usb at vger.kernel.org
> Cc: linux-arm-kernel at lists.infradead.org
> Cc: Sascha Hauer <kernel at pengutronix.de>
> ---
> v2 :
> drop reg/val swap which is handled in a better way by Igor's patch here :
> http://comments.gmane.org/gmane.linux.usb.general/32092 
>  
>  drivers/usb/otg/ulpi.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/usb/otg/ulpi.c b/drivers/usb/otg/ulpi.c
> index b1b3469..086853b 100644
> --- a/drivers/usb/otg/ulpi.c
> +++ b/drivers/usb/otg/ulpi.c
> @@ -54,7 +54,7 @@ static int ulpi_set_flags(struct otg_transceiver *otg)
>  	if (otg->flags & USB_OTG_EXT_VBUS_INDICATOR)
>  		flags |= ULPI_OTG_CTRL_EXTVBUSIND;
>  
> -	return otg_io_write(otg, flags, ULPI_SET(ULPI_OTG_CTRL));
> +	return otg_io_write(otg, flags, ULPI_OTG_CTRL);
>  }
>   

ulpi_set_flags is used to set the OTG flags and not to clear them,
also it is a static function and is not a part of struct otg_transceiver,
so it cannot be called from outside the ulpi.c, thus after the ulpi_create,
it is never called.
I think, currently, this should stay as it is.


>  static int ulpi_init(struct otg_transceiver *otg)
> @@ -90,7 +90,7 @@ static int ulpi_set_vbus(struct otg_transceiver *otg, bool on)
>  			flags |= ULPI_OTG_CTRL_DRVVBUS_EXT;
>  	}
>  
> -	return otg_io_write(otg, flags, ULPI_SET(ULPI_OTG_CTRL));
> +	return otg_io_write(otg, flags, ULPI_OTG_CTRL);
>  }
>   

This one seems ok.

>  
>  struct otg_transceiver *
>   

-- 
Regards,
Igor.



From linux at arm.linux.org.uk  Thu Jun 24 10:08:26 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 24 Jun 2010 15:08:26 +0100
Subject: [PATCH 1/6] U6/U6715 ARM architecture files
In-Reply-To: <1274948852-9179-2-git-send-email-philippe.langlais@stericsson.com>
References: <1274948852-9179-1-git-send-email-philippe.langlais@stericsson.com>
	<1274948852-9179-2-git-send-email-philippe.langlais@stericsson.com>
Message-ID: <20100624140825.GA6523@n2100.arm.linux.org.uk>

On Thu, May 27, 2010 at 10:27:27AM +0200, Philippe Langlais wrote:
> diff --git a/arch/arm/mach-u67xx/devices.c b/arch/arm/mach-u67xx/devices.c
> new file mode 100644
> index 0000000..0ead380
> --- /dev/null
> +++ b/arch/arm/mach-u67xx/devices.c
> @@ -0,0 +1,95 @@
> +/*
> + * linux/arch/arm/mach-u67xx/devices.c
> + *
> + * Copyright (C) ST-Ericsson SA 2010
> + * Author: Philippe Langlais <philippe.langlais at stericsson.com> for ST-Ericsson.
> + * License terms:  GNU General Public License (GPL), version 2
> + *
> + * Device specification for the U67XX
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/device.h>
> +#include <linux/ioport.h>
> +#include <linux/platform_device.h>
> +#include <linux/fs.h>
> +#include <mach/hardware.h>
> +#include <mach/scon.h>
> +#include <mach/gpio.h>

linux/gpio.h

> +struct gpio_bank u6_gpio_bank[6] = {
> +	{(void __iomem *)GPIOA_PINS_REG, (void __iomem *)SCON_SYSMUX0_REG},
> +	{(void __iomem *)GPIOB_PINS_REG, (void __iomem *)SCON_SYSMUX2_REG},
> +	{(void __iomem *)GPIOC_PINS_REG, (void __iomem *)SCON_SYSMUX4_REG},
> +	{(void __iomem *)GPIOD_PINS_REG, (void __iomem *)SCON_SYSMUX6_REG},
> +	{(void __iomem *)GPIOE_PINS_REG, (void __iomem *)SCON_SYSMUX8_REG},
> +	{(void __iomem *)GPIOF_PINS_REG, (void __iomem *)SCON_SYSMUX10_REG},

Would be nice to get rid of these casts - instead moving them to the
point of definition instead - or maybe doing as other platforms do and
defining an IOMEM() macro which does the cast and using that in the
definitions.

iow, something like:

#define IOMEM(x)	((void __iomem *)(x))

#define GPIOA_PINS_REG	IOMEM(whatever)

and if you need GPIOA_PINS_REG to be usable in assembly, arrange for
the IOMEM() macro to handle that for you.

> diff --git a/arch/arm/plat-u6xxx/include/mach/entry-macro.S b/arch/arm/plat-u6xxx/include/mach/entry-macro.S
> new file mode 100644
> index 0000000..59bb2d2
> --- /dev/null
> +++ b/arch/arm/plat-u6xxx/include/mach/entry-macro.S
> @@ -0,0 +1,32 @@
> +/*
> + * linux/arch/arm/plat-u6xxx/include/mach/entry-macro.S
> + *
> + * Low-level IRQ helper macros for U6-based platforms
> + * Copyright (C) ST-Ericsson SA 2010
> + *
> + * This file is licensed under  the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <mach/hardware.h>
> +#include <mach/irqs.h>
> +
> +	.macro  arch_ret_to_user, tmp1, tmp2
> +	.endm
> +
> +	.macro	disable_fiq
> +	.endm
> +
> +	.macro  get_irqnr_preamble, base, tmp
> +	.endm

This macro is there to allow you to be a little more efficient - rather
than reloading the base address of the interrupt controller each time
around the interrupt handling loop, you can put it in the above macro
to take it outside the loop.

> +#define hw_raw_local_irq_save       raw_local_irq_save
> +#define hw_raw_local_irq_restore    raw_local_irq_restore

What's the purpose of these additional aliases?

> +/* INTC PRIOMASK_IRQ Register (32 bits) */
> +#define INTC_PRIOMASK_IRQ_OFFSET 0x0
> +#define INTC_PRIOMASK_IRQ_REG  IO_ADDRESS(INTC_BASE + INTC_PRIOMASK_IRQ_OFFSET)
> +
> +/* INTC PRIOMASK_FIQ Register (32 bits) */
> +#define INTC_PRIOMASK_FIQ_OFFSET 0x4
> +#define INTC_PRIOMASK_FIQ_REG  IO_ADDRESS(INTC_BASE + INTC_PRIOMASK_FIQ_OFFSET)
> +
> +/* INTC VECTOR_IRQ Register (32 bits) */
> +#define INTC_VECTOR_IRQ_OFFSET   0x100
> +#define INTC_VECTOR_IRQ_REG      IO_ADDRESS(INTC_BASE + INTC_VECTOR_IRQ_OFFSET)
> +
> +/* INTC VECTOR_FIQ Register (32 bits) */
> +#define INTC_VECTOR_FIQ_OFFSET   0x104
> +#define INTC_VECTOR_FIQ_REG      IO_ADDRESS(INTC_BASE + INTC_VECTOR_FIQ_OFFSET)
> +
> +/* INTC PENDING_* Registers (32 bits) */
> +#define INTC_PENDING_1_OFFSET    0x200
> +#define INTC_PENDING_2_OFFSET    0x204
> +#define INTC_PENDING_3_OFFSET    0x208
> +#define INTC_FEATURES_OFFSET     0x300
> +
> +/* INTC REQUEST 64 Registers (32 bits) */
> +#define INTC_REQUEST1_OFFSET     0x404
> +#define INTC_REQUEST64_OFFSET    0x500
> +
> +/* INTC MOD_ID Register (32 bits) */
> +#define INTC_MOD_ID_OFFSET       0xFFC
> +
> +/* interrupt x [1..64] request configuration */
> +#define INTC_REQUESTx(x)  IO_ADDRESS(INTC_BASE+INTC_REQUEST1_OFFSET+(x-1)*4)
> +
> +/* EXTINTx [0..23] configuration register */
> +#define EXTINT_CFGx(x)    IO_ADDRESS(EXTINT_BASE+(x)*4)

Does it really make sense to export all these definitions to the entire
kernel?

> diff --git a/arch/arm/plat-u6xxx/include/mach/memory.h b/arch/arm/plat-u6xxx/include/mach/memory.h
> new file mode 100644
> index 0000000..0fa6cea
> --- /dev/null
> +++ b/arch/arm/plat-u6xxx/include/mach/memory.h
> @@ -0,0 +1,24 @@
> +/*
> + * linux/arch/arm/plat-u6xxx/include/mach/memory.h
> + *
> + * Copyright (C) ST-Ericsson SA 2010
> + * Author: Philippe Langlais <philippe.langlais at stericsson.com> for ST-Ericsson.
> + * License terms:  GNU General Public License (GPL), version 2
> + */
> +
> +#ifndef __ASM_ARCH_MEMORY_H
> +#define __ASM_ARCH_MEMORY_H
> +
> +/*
> + * Physical DRAM offset.
> + */
> +#define PHYS_OFFSET		UL(0x20000000)
> +#define BOOT_PARAMS_OFFSET	(PHYS_OFFSET + 0x100)

Does it make sense to export this to the world?

> +
> +/**
> + * CONSISTENT_DMA_SIZE: Size of DMA-consistent memory region.
> + * Must be multiple of 2M,between 2MB and 14MB inclusive
> + */
> +#define CONSISTENT_DMA_SIZE (SZ_2M)

It defaults to 2MB, so this definition is redundant.

> diff --git a/arch/arm/plat-u6xxx/include/mach/platform.h b/arch/arm/plat-u6xxx/include/mach/platform.h
> new file mode 100644
> index 0000000..5265ccd
> --- /dev/null
> +++ b/arch/arm/plat-u6xxx/include/mach/platform.h
> @@ -0,0 +1,15 @@
> +/*
> + * linux/arch/arm/plat-u6xxx/include/mach/platform.h
> + *
> + * Copyright (C) ST-Ericsson SA 2010
> + * Author: Philippe Langlais <philippe.langlais at stericsson.com> for ST-Ericsson.
> + * License terms:  GNU General Public License (GPL), version 2
> + */
> +
> +#ifndef __ASM_ARCH_PLATFORM_H
> +#define __ASM_ARCH_PLATFORM_H                     1
> +
> +#include <linux/types.h>
> +#include <mach/hardware.h>
> +
> +#endif  /* __ASM_ARCH_PLATFORM_H */

If there's nothing required in this file, it doesn't need to exist.

> diff --git a/arch/arm/plat-u6xxx/include/mach/timer.h b/arch/arm/plat-u6xxx/include/mach/timer.h
> new file mode 100644
> index 0000000..049e72d
> --- /dev/null
> +++ b/arch/arm/plat-u6xxx/include/mach/timer.h
> @@ -0,0 +1,24 @@
> +/*
> + *  linux/arch/arm/plat-u6xxx/include/mach/timer.h
> + *
> + * Copyright (C) ST-Ericsson SA 2010
> + * Author: Philippe Langlais <philippe.langlais at stericsson.com> for ST-Ericsson.
> + * License terms:  GNU General Public License (GPL), version 2
> + */
> +
> +#ifndef __PLAT_TIMER_H
> +#define __PLAT_TIMER_H
> +#ifdef U6_TIMER_C
> +#define PUBLIC
> +#else
> +#define PUBLIC extern
> +#endif

Err, no - there's really no need for such hacks in C, and I can't find
anywhere which defines U6_TIMER_C.

> +
> +struct sys_timer;
> +
> +PUBLIC struct sys_timer u6_timer;
> +
> +PUBLIC void __init u6_timer_init(void);
> +
> +#undef PUBLIC
> +#endif

> diff --git a/arch/arm/plat-u6xxx/include/mach/vmalloc.h b/arch/arm/plat-u6xxx/include/mach/vmalloc.h
> new file mode 100644
> index 0000000..583033f
> --- /dev/null
> +++ b/arch/arm/plat-u6xxx/include/mach/vmalloc.h
> @@ -0,0 +1,10 @@
> +/*
> + * linux/arch/arm/plat-u6/include/mach/vmalloc.h
> + * Copyright (C) ST-Ericsson SA 2010
> + * Author: Philippe Langlais <philippe.langlais at stericsson.com> for ST-Ericsson.
> + * License terms:  GNU General Public License (GPL), version 2
> + *
> + * Virtual memory allocations
> + * End must be above the I/O registers and on an even 2MiB boundary.
> + */
> +#define VMALLOC_END       (PAGE_OFFSET + 0x28000000)

Is the upper limit of vmalloc space is dependent on PAGE_OFFSET?  If
not, then it shouldn't be using a calculation based upon that value.

> diff --git a/arch/arm/plat-u6xxx/timer.c b/arch/arm/plat-u6xxx/timer.c
> new file mode 100644
> index 0000000..62f13f5
> --- /dev/null
> +++ b/arch/arm/plat-u6xxx/timer.c
> @@ -0,0 +1,679 @@
> +/*
> + * linux/arch/arm/plat-u6xxx/timer.c
> + *
> + * Copyright (C) ST-Ericsson SA 2010
> + * Author: Vincent Guittot <vincent.guittot at stericsson.com> for ST-Ericsson.
> + * License terms:  GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/types.h>
> +#include <linux/kernel.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +
> +#include <asm/mach/time.h>
> +
> +#include <mach/hardware.h>
> +
> +#include <asm/mach/irq.h>
> +#include <linux/interrupt.h>
> +#include <mach/irqs.h>
> +
> +#include <linux/clk.h>
> +
> +#include <linux/clocksource.h>
> +#include <linux/clockchips.h>

linux/ includes before asm/ includes.  asm/ includes before mach/ includes
please.

> +#undef U6_TIMER_DEBUG
> +#if defined(U6_TIMER_DEBUG)
> +#define debug(fmt, args...)                                          \
> +	printk(PKMOD fmt, ## args)
> +#else
> +#define debug(fmt, args...)
> +#endif

You could use pr_debug() instead, and define 'DEBUG' at the top of the
file you want debug messages from.

> +static irqreturn_t
> +u6_mmtu_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
> +{
> +	uint8_t status, enable;
> +	struct mmtu_ctxt *mmtu;
> +
> +	mmtu = u6_mmtu_get_context(0);
> +
> +	status = readl((mmtu->base + MMTU_INT_OFFSET + MMTU_INT_STATUS_IDX));
> +	enable = readl((mmtu->base + MMTU_INT_OFFSET + MMTU_INT_ENABLE_IDX));
> +
> +	debug("mmtu_timer_interrupt %d\n", status);
> +
> +	if (status & enable & MMTU_IRQ_MASK) {
> +		struct clock_event_device *evt = &clockevent_mmtu;
> +
> +		writel(MMTU_IRQ_MASK, (mmtu->base + MMTU_INT_OFFSET
> +					+ MMTU_INT_CLR_STAT_IDX));
> +
> +		if (mmtu->autoreload)
> +			u6_mmtu_timer_start(mmtu->compvalue, 0);

If your hardware doesn't do reloadable timers, you're not supposed to
emulate it.  The generic time infrastructure contains all the code
that's required to handle periodic timer interrupts with timers only
capable of one-shot mode.


> +		else
> +			writel(MMTU_IRQ_MASK,
> +			       (mmtu->base + MMTU_INT_OFFSET +
> +				MMTU_INT_CLR_ENA_IDX));
> +
> +		if (evt->event_handler)
> +			evt->event_handler(evt);
> +	}
> +	return IRQ_HANDLED;
> +}
> +
> +static struct irqaction u6_mmtu_timer_irq = {
> +	.name = "U6 MMTU timer Tick",
> +	.flags = IRQF_DISABLED,
> +	.handler = (irq_handler_t) u6_mmtu_timer_interrupt,
> +};
> +
> +static inline void u6_mmtu_clk_enable(int id)
> +{
> +	struct mmtu_ctxt *mmtu = u6_mmtu_get_context(id);
> +
> +	/* Clock Multimedia Timer Unit.
> +	 */
> +	if ((mmtu->clk != NULL) && (mmtu->mode == 0)) {
> +		debug("mmtu_clk_enable\n");
> +		mmtu->mode = 1;
> +		clk_enable(mmtu->clk);
> +	}
> +}
> +
> +static inline void u6_mmtu_clk_disable(int id)
> +{
> +	struct mmtu_ctxt *mmtu = u6_mmtu_get_context(id);
> +
> +	/* Clock Multimedia Timer Unit.
> +	 */
> +	if ((mmtu->clk != NULL) && (mmtu->mode == 1)) {
> +		debug("mmtu_clk_disable\n");
> +		clk_disable(mmtu->clk);
> +		mmtu->mode = 0;
> +	}
> +}
> +
> +static inline int u6_mmtu_timer_start(unsigned long cycles, int id)
> +{
> +	struct mmtu_ctxt *mmtu = u6_mmtu_get_context(id);
> +
> +	debug("mmtu_timer_start %d\n", cycles);
> +	u6_mmtu_clk_enable(id);
> +
> +	/* MMTU limitation : can't set a value smaller or equal to tcval + 1 */
> +	cycles = cycles < 2 ? 2 : cycles;
> +
> +	mmtu->compvalue = cycles;
> +
> +	mmtu->endvalue = mmtu->compvalue
> +		+ readl((mmtu->base + MMTU_TCVAL_IDX));
> +
> +	writel(MMTU_IRQ_MASK,
> +	       (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_STAT_IDX));
> +
> +	writel(mmtu->endvalue, (mmtu->base + MMTU_USED_MATCH_IDX));
> +
> +	writel(MMTU_IRQ_MASK,
> +	       (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_SET_ENA_IDX));
> +
> +	/* the value has already expired */
> +	if ((mmtu->endvalue <= readl((mmtu->base + MMTU_TCVAL_IDX)))
> +	    && (mmtu->endvalue > mmtu->compvalue)
> +	    && !(readl((mmtu->base + MMTU_INT_OFFSET
> +				    + MMTU_INT_STATUS_IDX)) & MMTU_IRQ_MASK))
> +		writel(MMTU_IRQ_MASK, (mmtu->base + MMTU_INT_OFFSET
> +					+ MMTU_INT_SET_STAT_IDX));
> +
> +	return 0;
> +}
> +
> +static int u6_mmtu_timer_init(int id, unsigned long reload,
> +			     unsigned long prescale, int over_it)
> +{
> +
> +	struct mmtu_ctxt *mmtu = u6_mmtu_get_context(id);
> +
> +	debug("mmtu_timer_init %d\n", id);
> +
> +	/* Enable clock */
> +/*
> +	u6_mmtu_clk_enable(id);
> +	clk mngt not available yet
> +	directly enable it
> +*/
> +	{
> +		unsigned long flags;
> +		unsigned long reg;
> +		hw_raw_local_irq_save(flags);
> +		reg = readl(CGU_GATESC2_REG);
> +		reg |= 0x1 << 2;
> +		writel(reg, CGU_GATESC2_REG);
> +		hw_raw_local_irq_restore(flags);
> +	}
> +
> +	/* Reset timer */
> +	/* reset control register */
> +	writel(0x0000, (mmtu->base + MMTU_CON_IDX));
> +	writel(0x0002, (mmtu->base + MMTU_CON_IDX));
> +	/* reset control register */
> +	writel(0x0000, (mmtu->base + MMTU_CON_IDX));
> +
> +	/* clear whole enable irq register */
> +	writel(0xFF, (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_ENA_IDX));
> +	/* clear whole status register */
> +	writel(0xFF, (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_STAT_IDX));
> +
> +	/* reset pre-scaler reload register */
> +	writel(0x00000000, (mmtu->base + MMTU_PRESCALER_IDX));
> +
> +	/* reset match control register */
> +	writel(0x0000, (mmtu->base + MMTU_MATCH_CON_IDX));
> +	/* reset match 0 register */
> +	writel(0x00000000, (mmtu->base + MMTU_MATCH0_IDX));
> +	/* reset match 1 register */
> +	writel(0x00000000, (mmtu->base + MMTU_MATCH1_IDX));
> +
> +	/* Initialize timer */
> +	writel(prescale - 1, (mmtu->base + MMTU_PRESCALER_IDX));
> +	/* power of 2 system clock */
> +	writel(reload, (mmtu->base + MMTU_MATCH0_IDX));
> +
> +	/* enable counter register */
> +	writel(0x0001, (mmtu->base + MMTU_CON_IDX));
> +
> +	/* clear whole status register */
> +	writel(0xFF, (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_STAT_IDX));
> +
> +	if (id == 0)
> +		setup_irq(IRQ_MMTU, &u6_mmtu_timer_irq);
> +
> +	/* Disable clock */
> +#ifndef U6_MMTU_CLOCK_SOURCE
> +	u6_mmtu_clk_disable(id);
> +#endif
> +	return 0;
> +}
> +
> +/*** MMTU Clock event device ***/
> +
> +static int u6_mmtu_set_next_event(unsigned long cycles,
> +				 struct clock_event_device *evt)
> +{
> +	debug("mmtu_set_next_event %d\n", cycles);
> +	u6_mmtu_timer_start(cycles, 0);
> +
> +	return 0;
> +}
> +
> +static void u6_mmtu_set_mode(enum clock_event_mode mode,
> +			    struct clock_event_device *evt)
> +{
> +	struct mmtu_ctxt *mmtu = u6_mmtu_get_context(0);
> +	unsigned long reg;
> +
> +	debug("mmtu_set_mode %d\n", mode);
> +
> +	switch (mode) {
> +	case CLOCK_EVT_MODE_UNUSED:
> +		writel(MMTU_IRQ_MASK,
> +		       (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_ENA_IDX));
> +		writel(MMTU_IRQ_MASK,
> +		       (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_STAT_IDX));
> +
> +		reg = readl((mmtu->base + MMTU_TCVAL_IDX));
> +		writel(reg - 1, (mmtu->base + MMTU_USED_MATCH_IDX));
> +
> +#ifndef U6_MMTU_CLOCK_SOURCE
> +		u6_mmtu_clk_disable(0);
> +
> +		if (mmtu->clk != NULL)
> +			clk_put(mmtu->clk);
> +#endif
> +		mmtu->autoreload = 0;
> +		break;
> +	case CLOCK_EVT_MODE_SHUTDOWN:
> +		mmtu->autoreload = 0;
> +
> +		if (mmtu->clk == NULL) {
> +			mmtu->clk = clk_get(0, "MMTU");
> +			if (IS_ERR(mmtu->clk))
> +				mmtu->clk = NULL;
> +		}
> +
> +		writel(MMTU_IRQ_MASK,
> +		       (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_STAT_IDX));
> +		writel(MMTU_IRQ_MASK,
> +		       (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_SET_ENA_IDX));
> +	case CLOCK_EVT_MODE_ONESHOT:
> +	case CLOCK_EVT_MODE_RESUME:
> +		mmtu->autoreload = 0;
> +		break;
> +	case CLOCK_EVT_MODE_PERIODIC:
> +		writel(MMTU_IRQ_MASK,
> +		       (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_SET_ENA_IDX));
> +		mmtu->autoreload = 1;
> +		break;
> +	}
> +}
> +
> +static void u6_clockevent_init_mmtu(void)
> +{
> +	printk(PKMOD "clockevent_init_mmtu\n");
> +
> +	/* prescale 13Mhz -> 1Mhz */
> +#ifndef U6_MMTU_CLOCK_SOURCE
> +	u6_mmtu_timer_init(0, 0, (MMTU_SYS_FRQ / MMTU_ROOT_FRQ), 0);
> +#endif
> +
> +/* issue it is shorter than reality and generates spurious irq */
> +/*      clockevent_mmtu.mult = div_sc(MMTU_ROOT_FRQ, NSEC_PER_SEC,
> + *      clockevent_mmtu.shift) + 1;*/
> +	clockevent_mmtu.mult =
> +	    div_sc(MMTU_ROOT_FRQ, NSEC_PER_SEC, clockevent_mmtu.shift);
> +
> +/*      clockevent_mmtu.max_delta_ns = div_sc(RELOAD_COUNTER_MMTU,
> + *      clockevent_mmtu.mult, clockevent_mmtu.shift);*/
> +/*  In fact it is wider than the 32bits variable !!! */
> +	clockevent_mmtu.max_delta_ns = 0xFFFFFFFF;
> +
> +/*  MMTU HW limitation: match register can't be set w/ tcval+1 */
> +/*      clockevent_mmtu.min_delta_ns = div_sc(1, clockevent_mmtu.mult,
> + *      clockevent_mmtu.shift)+1;*/
> +	clockevent_mmtu.min_delta_ns =
> +	    div_sc(2, clockevent_mmtu.mult, clockevent_mmtu.shift) + 1;
> +	/* avoid to much timer interrupt with 10us min between 2 irq */
> +	if (clockevent_mmtu.min_delta_ns < 10000)
> +		clockevent_mmtu.min_delta_ns = 10000;
> +	else if (clockevent_mmtu.max_delta_ns < 10000)
> +		clockevent_mmtu.min_delta_ns = clockevent_mmtu.max_delta_ns>>1;
> +
> +	clockevent_mmtu.cpumask = get_cpu_mask(0);
> +	clockevents_register_device(&clockevent_mmtu);
> +
> +	u6_mmtu_set_next_event(MMTU_ROOT_FRQ / HZ, &clockevent_mmtu);
> +}
> +
> +/*** MMTU Clock source device ***/
> +#ifdef U6_MMTU_CLOCK_SOURCE
> +
> +static cycle_t u6_mmtu_read(struct clocksource *source)
> +{
> +	struct mmtu_ctxt *mmtu = u6_mmtu_get_context(0);
> +
> +	return readl((mmtu->base + MMTU_TCVAL_IDX)) & source->mask;
> +}

Clocksource read functions don't require the value masking.

> +
> +static void u6_clocksource_init_mmtu(void)
> +{
> +	printk(PKMOD "clocksource_init_mmtu\n");
> +
> +	if (MMTU_ROOT_FRQ >= 1000000)
> +		clocksource_mmtu.mult =
> +		    clocksource_khz2mult((MMTU_ROOT_FRQ / 1000),
> +					 clocksource_mmtu.shift);
> +	else
> +		clocksource_mmtu.mult = clocksource_hz2mult((MMTU_ROOT_FRQ),
> +				clocksource_mmtu.shift);
> +
> +	u6_mmtu_timer_init(0, 0, (MMTU_SYS_FRQ / MMTU_ROOT_FRQ), 0);
> +
> +	clocksource_register(&clocksource_mmtu);
> +}
> +
> +unsigned long long u6_mmtu_time(void)
> +{
> +	unsigned long long ticks64 = u6_mmtu_read(&clocksource_mmtu);
> +
> +	return (ticks64 * clocksource_mmtu.mult) >> clocksource_mmtu.shift;
> +}

Can you explain the purpose of this function please, and why you export
the ticks and value from this function via sysfs?

> +#endif
> +
> +/*** SysFs interface ***/
> +/***********************/
> +#ifdef CONFIG_U6_POWER_SYSFS
> +
> +/*** Clock event sysfs interface **/
> +
> +#define shows_one_evt(file_name, object)				\
> +static ssize_t show_##file_name##_evt					\
> +(struct kobject *kobj, char *buf)				\
> +{									\
> +	return sprintf(buf, "%s\n", clockevent_mmtu.object);		\
> +}
> +
> +#define showu_one_evt(file_name, object)				\
> +static ssize_t show_##file_name##_evt					\
> +(struct kobject *kobj, char *buf)				\
> +{									\
> +	return sprintf(buf, "%u\n", clockevent_mmtu.object);		\
> +}
> +
> +#define showlu_one_evt(file_name, object)				\
> +static ssize_t show_##file_name##_evt					\
> +(struct kobject *kobj, char *buf)				\
> +{									\
> +	return sprintf(buf, "%lu\n", clockevent_mmtu.object);		\
> +}
> +
> +#define storelu_one_evt(file_name, object)				\
> +static ssize_t store_##file_name##_evt					\
> +(struct kobject *kobj, const char *buf, size_t size)			\
> +{									\
> +	unsigned long object; \
> +	strict_strtoul(buf, 10, &object); \
> +	clockevent_mmtu.object = object; \
> +	return size;		\
> +}
> +
> +#define showx_one_evt(file_name, object)				\
> +static ssize_t show_##file_name##_evt					\
> +(struct kobject *kobj, char *buf)				\
> +{									\
> +	return sprintf(buf, "0x%x\n", clockevent_mmtu.object);		\
> +}
> +
> +shows_one_evt(name, name);
> +showu_one_evt(rating, rating);
> +showlu_one_evt(mult, mult);
> +#ifdef CONFIG_U6_TIMER_TUNE
> +storelu_one_evt(mult, mult);
> +#endif
> +showu_one_evt(shift, shift);
> +showx_one_evt(features, features);
> +showlu_one_evt(min_delta_ns, min_delta_ns);
> +showlu_one_evt(max_delta_ns, max_delta_ns);

Why do you want all these parameters exported to userspace?  Maybe you
should discuss your requirement here with the generic time people
before submitting it?


From linux at arm.linux.org.uk  Thu Jun 24 10:14:18 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 24 Jun 2010 15:14:18 +0100
Subject: [PATCH 2/6] U6715 clocks gating management U6 clock generic
	driver & U6715 cgu clock specific (V2)
In-Reply-To: <1274948852-9179-3-git-send-email-philippe.langlais@stericsson.com>
References: <1274948852-9179-1-git-send-email-philippe.langlais@stericsson.com>
	<1274948852-9179-3-git-send-email-philippe.langlais@stericsson.com>
Message-ID: <20100624141418.GB6523@n2100.arm.linux.org.uk>

On Thu, May 27, 2010 at 10:27:28AM +0200, Philippe Langlais wrote:
> +#if defined(DEBUG_CGU)
> +#define debug(fmt, args...)                                          \
> +	printk(PKMOD fmt, ## args)
> +#else
> +#define debug(fmt, args...)
> +#endif

pr_debug?
> +
> +/**
> + * U6 hw low level access clock functions
> + **/
> +static void u6_clk_disable(struct clk *clk);
> +static int u6_clk_enable(struct clk *clk);
> +
> +/**
> + * HW enable clock function.
> + **/
> +
> +static int u67xx_cgu_enable_fake_clock(struct clk *clk)
> +{
> +	debug("u67xx_cgu_enable_fake_clock for %s\n", clk->name);
> +	return 0;
> +}
> +
> +static int u67xx_cgu_enable_hw_clock(struct clk *clk)
> +{
> +	unsigned long value;
> +	debug("u67xx_cgu_enable_hw_clock for %s\n", clk->name);
> +
> +	if (unlikely(clk->enable_reg == 0)) {

These are pointers.  0 is an integer.  Use NULL.  Check your code with
sparse and you'll get warnings for these things.

> +/*** Basic clocks ***/
> +
> +/* Base external input clocks */
> +static struct clk func_32k_ck = {
> +	.name = "func_32k_ck",
> +	.rate = 32000,
> +	.flags = RATE_FIXED | ALWAYS_ENABLED,
> +	.usecount = 1,
> +};

Don't put data definitions in header files.

> +static struct clk *onchip_clks[] = {
> +	/* external root sources */
> +	&func_32k_ck,
> +	&osc_ck,
> +	&sys_ck,
> +	&sc_ck,
> +	&fix_ck,
> +	&tv_ck,
> +#ifndef U6_OPTIMIZED_TREE
> +	&dsp2_ck,
> +#endif
> +	&sdm_ck,
> +	&arm_ck,
> +	&hclk_ck,
> +	&hclk2_ck,
> +	&pclk1_ck,
> +	&pclk2_ck,
> +	&tvclk_ck,

This all looks very much like it was copied from the OMAP code as of about
a year ago.  The OMAP code has moved forwards with lots of improvements,
including using clkdev to eliminate the disgusting SoC specific code from
drivers (which clkdev is there to prevent.)


From linux at arm.linux.org.uk  Thu Jun 24 10:17:28 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 24 Jun 2010 15:17:28 +0100
Subject: [PATCH 4/6] U6715 platform serial driver It's a generic driver
	for all U6 platform (V2)
In-Reply-To: <1274948852-9179-5-git-send-email-philippe.langlais@stericsson.com>
References: <1274948852-9179-1-git-send-email-philippe.langlais@stericsson.com>
	<1274948852-9179-5-git-send-email-philippe.langlais@stericsson.com>
Message-ID: <20100624141728.GC6523@n2100.arm.linux.org.uk>

On Thu, May 27, 2010 at 10:27:30AM +0200, Philippe Langlais wrote:
> +struct u6_uart {
> +	struct clk *uartClk;
> +	struct clk *pClk_13M;
> +	struct clk *pClk_26M;
> +	struct clk *pClk_pclk;
> +	char   uart_name[7];
> +};

Passing struct clk's through platform data into drivers... what's the
point of the clk API again?


From linux at arm.linux.org.uk  Thu Jun 24 10:26:44 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 24 Jun 2010 15:26:44 +0100
Subject: [PATCH 3/6] U6715 gpio platform driver This driver is U6
	platform generic (V2)
In-Reply-To: <1274948852-9179-4-git-send-email-philippe.langlais@stericsson.com>
References: <1274948852-9179-1-git-send-email-philippe.langlais@stericsson.com>
	<1274948852-9179-4-git-send-email-philippe.langlais@stericsson.com>
Message-ID: <20100624142644.GD6523@n2100.arm.linux.org.uk>

On Thu, May 27, 2010 at 10:27:29AM +0200, Philippe Langlais wrote:
> Signed-off-by: Philippe Langlais <philippe.langlais at stericsson.com>
> ---
>  arch/arm/mach-u67xx/board_u67xx_wavex.c |  469 ++++++++++++++++++++
>  arch/arm/mach-u67xx/devices.c           |   12 +-
>  arch/arm/plat-u6xxx/Makefile            |    2 +-
>  arch/arm/plat-u6xxx/gpio.c              |  716 +++++++++++++++++++++++++++++++
>  arch/arm/plat-u6xxx/include/mach/gpio.h |  396 +++++++++++++++++
>  5 files changed, 1588 insertions(+), 7 deletions(-)
>  create mode 100644 arch/arm/plat-u6xxx/gpio.c
>  create mode 100644 arch/arm/plat-u6xxx/include/mach/gpio.h
> 
> diff --git a/arch/arm/mach-u67xx/board_u67xx_wavex.c b/arch/arm/mach-u67xx/board_u67xx_wavex.c
> index 2a806e7..a21e465 100644
> --- a/arch/arm/mach-u67xx/board_u67xx_wavex.c
> +++ b/arch/arm/mach-u67xx/board_u67xx_wavex.c
> @@ -24,6 +24,474 @@
>  #include <asm/mach/arch.h>
>  #include <mach/irqs.h>
>  #include <mach/timer.h>
> +#include <mach/gpio.h>

linux/gpio.h

> +
> +#include <mach/scon.h>
> +
> +/**
> + * SCON initial settings
> + * Allows to define the PIN multiplexing for all the platform (Linux and Modem)
> + */
> +struct u6_scon_config u6_scon_init_config[SCON_REGISTER_NB] = {
> + {
> +	(void __iomem *) SCON_SYSMUX0_REG,

IOMEM() to eliminate the cast?

> +/* GPIO def settings to avoid HW issue */
> +struct u6_gpio_config u6_gpio_init_config[] = {
> +	/* GPIO A bank */
> +	{
> +		.gpio = GPIO_A5,
> +		.dir = GPIO_DIR_OUTPUT	,

Unnecessary spaces between 'OUTPUT' and ','

> +		.value = 1,
> +	},
> +	{
> +		.gpio = GPIO_A6,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 1,
> +	},
> +	{
> +		.gpio = GPIO_A7,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	{
> +		.gpio = GPIO_A8,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 1,
> +	},
> +	{
> +		.gpio = GPIO_A9,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 1,
> +	},
> +	{
> +		.gpio = GPIO_A13,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	{
> +		.gpio = GPIO_A17,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	{
> +		.gpio = GPIO_A21,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	{
> +		.gpio = GPIO_A23,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	{
> +		.gpio = GPIO_A24,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 1,
> +	},
> +	{
> +		.gpio = GPIO_A25,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	{
> +		.gpio = GPIO_A30,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	/* GPIO B bank */
> +	/* GPIO C bank */
> +	/* GPIO D bank */
> +	{
> +		.gpio = GPIO_D0,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	{
> +		.gpio = GPIO_D24,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	{
> +		.gpio = GPIO_D29,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	/* GPIO E bank */
> +	{
> +		.gpio = GPIO_E31,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	/* GPIO F bank */
> +	{
> +		.gpio = GPIO_F0,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	{
> +		.gpio = GPIO_F1,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	{
> +		.gpio = GPIO_F2,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	},
> +	{
> +		.gpio = GPIO_F9,
> +		.dir = GPIO_DIR_OUTPUT	,
> +		.value = 0,
> +	}
> +};
> +
> +u32 gpio_to_configure = ARRAY_SIZE(u6_gpio_init_config);
>  
>  /* List of board specific devices */
>  static struct platform_device *devices[] __initdata = {
> @@ -31,6 +499,7 @@ static struct platform_device *devices[] __initdata = {
>  
>  void __init u67xx_init(void)
>  {
> +	u6_gpio_init();
>  	/* Add specific board devices */
>  	platform_add_devices(devices, ARRAY_SIZE(devices));
>  }
> diff --git a/arch/arm/mach-u67xx/devices.c b/arch/arm/mach-u67xx/devices.c
> index 0ead380..8e812fb 100644
> --- a/arch/arm/mach-u67xx/devices.c
> +++ b/arch/arm/mach-u67xx/devices.c
> @@ -48,12 +48,12 @@ unsigned char extint_to_gpio[NR_EXTINT] = {
>  EXPORT_SYMBOL(extint_to_gpio);
>  
>  struct gpio_bank u6_gpio_bank[6] = {
> -	{(void __iomem *)GPIOA_PINS_REG, (void __iomem *)SCON_SYSMUX0_REG},
> -	{(void __iomem *)GPIOB_PINS_REG, (void __iomem *)SCON_SYSMUX2_REG},
> -	{(void __iomem *)GPIOC_PINS_REG, (void __iomem *)SCON_SYSMUX4_REG},
> -	{(void __iomem *)GPIOD_PINS_REG, (void __iomem *)SCON_SYSMUX6_REG},
> -	{(void __iomem *)GPIOE_PINS_REG, (void __iomem *)SCON_SYSMUX8_REG},
> -	{(void __iomem *)GPIOF_PINS_REG, (void __iomem *)SCON_SYSMUX10_REG},
> +	{GPIOA_PINS_REG, SCON_SYSMUX0_REG},
> +	{GPIOB_PINS_REG, SCON_SYSMUX2_REG},
> +	{GPIOC_PINS_REG, SCON_SYSMUX4_REG},
> +	{GPIOD_PINS_REG, SCON_SYSMUX6_REG},
> +	{GPIOE_PINS_REG, SCON_SYSMUX8_REG},
> +	{GPIOF_PINS_REG, SCON_SYSMUX10_REG},
>  };
>  
>  static struct gpio_data u6_gpio_data = {
> diff --git a/arch/arm/plat-u6xxx/Makefile b/arch/arm/plat-u6xxx/Makefile
> index afdf82b..3d6898e 100644
> --- a/arch/arm/plat-u6xxx/Makefile
> +++ b/arch/arm/plat-u6xxx/Makefile
> @@ -3,6 +3,6 @@
>  #
>  
>  # Common support
> -obj-y := io.o irq.o clock.o
> +obj-y := io.o irq.o clock.o gpio.o
>  
>  obj-$(CONFIG_U6_MTU_TIMER) += timer.o
> diff --git a/arch/arm/plat-u6xxx/gpio.c b/arch/arm/plat-u6xxx/gpio.c
> new file mode 100644
> index 0000000..40e25fc
> --- /dev/null
> +++ b/arch/arm/plat-u6xxx/gpio.c
> @@ -0,0 +1,716 @@
> +/*
> + * linux/arch/arm/plat-u6xxx/gpio.c
> + *
> + * Copyright (C) ST-Ericsson SA 2010
> + * Author: Loic Pallardy <loic.pallardy at stericsson.com> for ST-Ericsson.
> + * License terms:  GNU General Public License (GPL), version 2
> + * Support functions for GPIO
> + */
> +
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/sched.h>
> +#include <linux/interrupt.h>
> +#include <linux/ptrace.h>
> +#include <linux/sysdev.h>
> +#include <linux/err.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +
> +#include <mach/hardware.h>
> +#include <asm/irq.h>
> +#include <mach/irqs.h>
> +#include <mach/gpio.h>
> +#include <asm/mach/irq.h>
> +#include <mach/scon.h>

asm/ before mach/.

> +
> +/*
> + * PN5220 GPIO/MUX registers
> + * defined in asm/arch/registers.h
> + */
> +
> +#define U6_GPIO_PINS_OFFSET	0
> +#define U6_GPIO_OUTPUT_OFFSET	4
> +#define U6_GPIO_DIR_OFFSET	8
> +
> +#define U6_MUX2_OFFSET		4
> +
> +static struct gpio_bank *gpio_bank_desc;
> +static int gpio_bank_count;
> +
> +static inline struct gpio_bank *get_gpio_bank(int gpio)
> +{
> +	/* 32 GPIOs per bank */
> +	return &(gpio_bank_desc[gpio >> 5]);
> +}
> +
> +static inline int get_gpio_index(int gpio)
> +{
> +	return gpio & 0x1f;
> +}
> +
> +static int check_gpio(int gpio)
> +{
> +	int retval = ((unsigned int)gpio) < GPIO_COUNT;
> +	if (unlikely(!retval)) {
> +		printk(KERN_ERR "u6-gpio: invalid GPIO %d\n", gpio);
> +		dump_stack();
> +	}

	return WARN_ON((unsigned int)gpio < GPIO_COUNT);

or use WARN(condition, format) if you want a custom message.

> +static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
> +{
> +	u32 reg = bank->gpio_base;
> +	u32 l;
> +
> +	/* select direction register */
> +	reg += U6_GPIO_DIR_OFFSET;
> +
> +	/* in register 0 = input, 1 = output */
> +	l = inl(reg);

inl/outl are for PCI/ISA based IO accesses/emulation.  I don't think your
GPIO block is a PCI/ISA peripheral, so it should not be using these macros.

> +static int initialized;
> +
> +static int __init u6_gpio_probe(struct platform_device *pdev)
> +{
> +	int i, j;
> +	int gpio = 0;
> +	struct gpio_bank *bank;
> +	struct gpio_data *data = pdev->dev.platform_data;
> +	unsigned long flags;
> +
> +	initialized = 1;

Why is this here when you're really wanting to prevent the platform
driver structure being registered more than once?

> +
> +	printk(KERN_INFO "U6 GPIO\n");
> +	gpio_bank_desc = data->gpio_bank_desc;
> +	gpio_bank_count = data->nb_banks;
> +
> +	for (i = 0; i < gpio_bank_count; i++) {
> +		int gpio_count = 32;	/* 32 GPIO per bank */
> +		bank = &gpio_bank_desc[i];
> +		bank->reserved_map = 0;
> +		spin_lock_init(&bank->lock);
> +
> +		bank->chip.request = u6_gpio_acquire;
> +		bank->chip.free = u6_gpio_release;
> +		bank->chip.direction_input = gpio_input;
> +		bank->chip.get = gpio_get;
> +		bank->chip.direction_output = gpio_output;
> +		bank->chip.set = gpio_set;
> +		bank->chip.to_irq = gpio_2irq;
> +		bank->chip.label = "gpio";
> +		bank->chip.base = gpio;
> +		gpio += gpio_count;
> +
> +		bank->chip.ngpio = gpio_count;
> +
> +		gpiochip_add(&bank->chip);
> +
> +	}
> +
> +	/* for extint */
> +	for (j = IRQ_COUNT; j < IRQ_COUNT + NR_EXTINT; j++) {
> +		set_irq_chip(j, &gpio_irq_chip);
> +		set_irq_handler(j, handle_simple_irq);
> +		set_irq_flags(j, IRQF_VALID);
> +	}
> +
> +	hw_raw_local_irq_save(flags);
> +	/* mask all EXT IRQ sources before registring handler */
> +	/* read status */
> +	j = inl(EXTINT_STATUS_REG) & inl(EXTINT_ENABLE3_REG);
> +	/* clear IRQ source(s) */
> +	outl(j, EXTINT_STATUS_REG);
> +
> +	outl(0, EXTINT_ENABLE3_REG);
> +
> +	/* set irq in low level */
> +	set_irq_type(IRQ_EXTINT3, IRQF_TRIGGER_LOW);
> +
> +	/* chained GPIO-IRQ on EXTINT3 */
> +	set_irq_chained_handler(IRQ_EXTINT3, gpio_irq_handler);
> +	hw_raw_local_irq_restore(flags);
> +
> +	return 0;
> +}
> +
> +static struct platform_driver u6_gpio_driver = {
> +	.probe = u6_gpio_probe,
> +	.remove = NULL,
> +	.suspend = NULL,
> +	.resume = NULL,
> +	.driver = {
> +		   .name = "u6-gpio",
> +		   },
> +};
> +
> +static struct sysdev_class u6_gpio_sysclass = {
> +	.name = "gpio",
> +	.suspend = 0,		/*u6_gpio_suspend, */
> +	.resume = 0,		/*u6_gpio_resume, */
> +};
> +
> +static struct sys_device u6_gpio_device = {
> +	.id = 0,
> +	.cls = &u6_gpio_sysclass,
> +};
> +
> +/*
> + * This may get called early from board specific init
> + * for boards that have interrupts routed via FPGA.
> + */
> +int u6_gpio_init(void)
> +{
> +	if (!initialized)
> +		return platform_driver_register(&u6_gpio_driver);

Shouldn't this set 'initialized' once the platform driver has been
registered to prevent the platform driver being registered again?

> +	else
> +		return 0;
> +}
> +
> +static int __init u6_gpio_sysinit(void)
> +{
> +	int ret = 0;
> +
> +	if (!initialized)
> +		ret = u6_gpio_init();

Why not just call u6_gpio_init(), which handles the special case anyway?

> +
> +	if (ret == 0) {
> +		ret = sysdev_class_register(&u6_gpio_sysclass);
> +		if (ret == 0)
> +			ret = sysdev_register(&u6_gpio_device);
> +	}
> +
> +	return ret;
> +}
> +
> +arch_initcall(u6_gpio_sysinit);
> diff --git a/arch/arm/plat-u6xxx/include/mach/gpio.h b/arch/arm/plat-u6xxx/include/mach/gpio.h
> new file mode 100644
> index 0000000..a205f1c
> --- /dev/null
> +++ b/arch/arm/plat-u6xxx/include/mach/gpio.h
> @@ -0,0 +1,396 @@
> +/*
> + * linux/arch/arm/plat-u6xxx/include/mach/gpio.h
> + *
> + * Copyright (C) ST-Ericsson SA 2010
> + * Author: Loic Pallardy <loic.pallardy at stericsson.com> for ST-Ericsson.
> + * License terms:  GNU General Public License (GPL), version 2
> + * GPIO handling defines and functions
> + */
> +
> +#ifndef __ASM_PLAT_U6_GPIO_H
> +#define __ASM_PLAT_U6_GPIO_H
> +
> +#include <linux/io.h>
> +#include <mach/hardware.h>
> +#include <mach/irqs.h>
> +#include <mach/gpio.h>

Recursive include of mach/gpio.h

> +
> +#include <linux/errno.h>
> +#include <asm-generic/gpio.h>

linux/ includes before asm and mach includes.


From linux at arm.linux.org.uk  Thu Jun 24 10:31:29 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 24 Jun 2010 15:31:29 +0100
Subject: [PATCH 5/6] U6715 8250 serial like driver
In-Reply-To: <1274948852-9179-6-git-send-email-philippe.langlais@stericsson.com>
References: <1274948852-9179-1-git-send-email-philippe.langlais@stericsson.com>
	<1274948852-9179-6-git-send-email-philippe.langlais@stericsson.com>
Message-ID: <20100624143129.GE6523@n2100.arm.linux.org.uk>

On Thu, May 27, 2010 at 10:27:31AM +0200, Philippe Langlais wrote:
> Some modifications in 16550A/8250 serial driver
> and clock management specificity

Can't say much about this; you need to get people interested in serial to
review this.  The comments about header file ordering apply.

> @@ -199,10 +199,16 @@ static const struct serial8250_config uart_config[] = {
>  	},
>  	[PORT_16550A] = {
>  		.name		= "16550A",
> +#if defined(CONFIG_SERIAL_8250_U6)
> +		.fifo_size	= 64,
> +		.tx_loadsz	= 64,
> +		.flags		= UART_CAP_FIFO | UART_CAP_AFE,

If you have auto flow control, then you don't have a 16550A.  You have
something that is compatible with a 16550A - maybe it's more closely
related to a 16750?


From roman.tereshonkov at nokia.com  Thu Jun 24 10:32:14 2010
From: roman.tereshonkov at nokia.com (roman.tereshonkov at nokia.com)
Date: Thu, 24 Jun 2010 16:32:14 +0200
Subject: [PATCH] spi/omap2_mcspi: disable and enable chan between each
	SPI transfer
In-Reply-To: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com>
References: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <E1C7579D1379824DAE67858071C810382DD83846FB@NOK-EUMSG-02.mgdnok.nokia.com>

 

>-----Original Message-----
>From: ext Jason Wang [mailto:jason77.wang at gmail.com] 
>Sent: 24 June, 2010 15:13
>To: grant.likely at secretlab.ca; Tereshonkov Roman 
>(Nokia-D/Helsinki); david-b at pacbell.net
>Cc: spi-devel-general at lists.sourceforge.net; 
>linux-arm-kernel at lists.infradead.org
>Subject: [PATCH] spi/omap2_mcspi: disable and enable chan 
>between each SPI transfer
>
>In current design, the SPI channel is always enable during the period
>of handling a SPI message, it is risky when more than one SPI transfer
>are included in a message. Current working route like that:
>[
>  SPI channel enable
>  configure channel
>  handle transfer #1
>  configure channel
>  handle transfer #2
>  ...
>  SPI channel disable
>]
>If we can disable channel before configure it and reenable
>channel after it is configured, it will be more safe.
>
>The commit a330ce2 "omap2_mcspi: Flush posted writes" make this risk
>to a real problem for ads7846 driver on omap3530evm. The
>ads7846 driver will send a SPI messge which includes,
>[
>  TX_ONLY transfer (1 byte)
>  RX_ONLY transfer (2 bytes)
>  TX_ONLY transfer (1 byte)
>  RX_ONLY transfer (2 bytes)
>]
>If we don't add disable/reenable channel between TX and RX transfers,
>the RX transfer will get wrong datas sent from slave.
>
>Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>---
> drivers/spi/omap2_mcspi.c |   16 ++++++----------
> 1 files changed, 6 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>index b3a94ca..1e3cb7b 100644
>--- a/drivers/spi/omap2_mcspi.c
>+++ b/drivers/spi/omap2_mcspi.c
>@@ -408,7 +408,6 @@ omap2_mcspi_txrx_dma(struct spi_device 
>*spi, struct spi_transfer *xfer)
> 				count -= (word_len <= 8)  ? 2 :
> 					(word_len <= 16) ? 4 :
> 					/* word_len <= 32 */ 8;
>-				omap2_mcspi_set_enable(spi, 1);
> 				return count;
> 			}
> 		}
>@@ -430,8 +429,10 @@ omap2_mcspi_txrx_dma(struct spi_device 
>*spi, struct spi_transfer *xfer)
> 				 (word_len <= 16) ? 2 :
> 			       /* word_len <= 32 */ 4;
> 		}
>-		omap2_mcspi_set_enable(spi, 1);
> 	}
>+
>+	omap2_mcspi_set_enable(spi, 0);
>+
> 	return count;
> }
> 
>@@ -517,8 +518,6 @@ omap2_mcspi_txrx_pio(struct spi_device 
>*spi, struct spi_transfer *xfer)
> 						goto out;
> 					}
> 					c = 0;
>-				} else if (c == 0 && tx == NULL) {
>-					omap2_mcspi_set_enable(spi, 0);
> 				}
> 
> 				*rx++ = __raw_readl(rx_reg);
>@@ -570,8 +569,6 @@ omap2_mcspi_txrx_pio(struct spi_device 
>*spi, struct spi_transfer *xfer)
> 						goto out;
> 					}
> 					c = 0;
>-				} else if (c == 0 && tx == NULL) {
>-					omap2_mcspi_set_enable(spi, 0);
> 				}
> 
> 				*rx++ = __raw_readl(rx_reg);
>@@ -623,8 +620,6 @@ omap2_mcspi_txrx_pio(struct spi_device 
>*spi, struct spi_transfer *xfer)
> 						goto out;
> 					}
> 					c = 0;
>-				} else if (c == 0 && tx == NULL) {
>-					omap2_mcspi_set_enable(spi, 0);
> 				}
> 
> 				*rx++ = __raw_readl(rx_reg);

Why do you do this?
Reading the last word from the shift register buffer leads to 
the receiving new data to the buffer.
The channel needs to be disabled before the last word reading.



>@@ -646,7 +641,7 @@ omap2_mcspi_txrx_pio(struct spi_device 
>*spi, struct spi_transfer *xfer)
> 			dev_err(&spi->dev, "EOT timed out\n");
> 	}
> out:
>-	omap2_mcspi_set_enable(spi, 1);
>+	omap2_mcspi_set_enable(spi, 0);
> 	return count - c;
> }
> 
>@@ -894,7 +889,6 @@ static void omap2_mcspi_work(struct 
>work_struct *work)
> 		cs = spi->controller_state;
> 		cd = spi->controller_data;
> 
>-		omap2_mcspi_set_enable(spi, 1);
> 		list_for_each_entry(t, &m->transfers, transfer_list) {
> 			if (t->tx_buf == NULL && t->rx_buf == 
>NULL && t->len) {
> 				status = -EINVAL;
>@@ -931,6 +925,8 @@ static void omap2_mcspi_work(struct 
>work_struct *work)
> 
> 			mcspi_write_chconf0(spi, chconf);
> 
>+			omap2_mcspi_set_enable(spi, 1);
>+
> 			if (t->len) {
> 				unsigned	count;
> 
>-- 
>1.5.6.5
>
>

From eric at eukrea.com  Thu Jun 24 10:37:14 2010
From: eric at eukrea.com (=?UTF-8?B?RXJpYyBCw6luYXJk?=)
Date: Thu, 24 Jun 2010 16:37:14 +0200
Subject: [PATCH v2] otg/ulpi.c : fix register write
In-Reply-To: <4C236600.2030605@compulab.co.il>
References: <1277311435-12027-1-git-send-email-eric@eukrea.com>
	<4C236600.2030605@compulab.co.il>
Message-ID: <4C236D9A.4030707@eukrea.com>

Le 24/06/2010 16:04, Igor Grinberg a ?crit :
> ulpi_set_flags is used to set the OTG flags and not to clear them,
> also it is a static function and is not a part of struct otg_transceiver,
> so it cannot be called from outside the ulpi.c, thus after the ulpi_create,
> it is never called.
> I think, currently, this should stay as it is.
>
OK, the problem that when one flag is set, you can't clear it without 
resetting the PHY.

Eric


From eric at eukrea.com  Thu Jun 24 10:42:10 2010
From: eric at eukrea.com (=?UTF-8?B?RXJpYyBCw6luYXJk?=)
Date: Thu, 24 Jun 2010 16:42:10 +0200
Subject: 
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <4C236EC2.8090506@eukrea.com>

Hi Uwe,

Le 24/06/2010 15:48, Uwe Kleine-K?nig a ?crit :
> this is the next step in the project "clean up the imx port" targeting
> 2.6.36.  The highlights this time are:
>
maybe that would be interesting to rebase your patch serie against
Sascha's imx-for-2.6.36 in order to include new boards (especially for 
the patches which change registering nand, i2c, spi and uart) ?

Eric


From grant.likely at secretlab.ca  Thu Jun 24 11:12:06 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Thu, 24 Jun 2010 09:12:06 -0600
Subject: [PATCH] spi/omap2_mcspi: disable and enable chan between each SPI
	transfer
In-Reply-To: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com>
References: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com>
Message-ID: <AANLkTin7mqe_zJIbyDcRPpCLaxPhl_dZQrSGua2z1nYW@mail.gmail.com>

On Thu, Jun 24, 2010 at 6:12 AM, Jason Wang <jason77.wang at gmail.com> wrote:
> In current design, the SPI channel is always enable during the period
> of handling a SPI message, it is risky when more than one SPI transfer
> are included in a message. Current working route like that:
> [
> ?SPI channel enable
> ?configure channel
> ?handle transfer #1
> ?configure channel
> ?handle transfer #2
> ?...
> ?SPI channel disable
> ]
> If we can disable channel before configure it and reenable
> channel after it is configured, it will be more safe.
>
> The commit a330ce2 "omap2_mcspi: Flush posted writes" make this risk
> to a real problem for ads7846 driver on omap3530evm. The
> ads7846 driver will send a SPI messge which includes,
> [
> ?TX_ONLY transfer (1 byte)
> ?RX_ONLY transfer (2 bytes)
> ?TX_ONLY transfer (1 byte)
> ?RX_ONLY transfer (2 bytes)
> ]
> If we don't add disable/reenable channel between TX and RX transfers,
> the RX transfer will get wrong datas sent from slave.

I don't understand the problem description.  Are you talking about
manipulation of the SS line, or a problem with the internal state on
the mcspi controller device?  What is the cause of the wrong data (ie.
is there a protocol error on the wire, or is the SPI controller not
performing the read correctly?)

Thanks,
g.

>
> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
> ---
> ?drivers/spi/omap2_mcspi.c | ? 16 ++++++----------
> ?1 files changed, 6 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
> index b3a94ca..1e3cb7b 100644
> --- a/drivers/spi/omap2_mcspi.c
> +++ b/drivers/spi/omap2_mcspi.c
> @@ -408,7 +408,6 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?count -= (word_len <= 8) ?? 2 :
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(word_len <= 16) ? 4 :
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?/* word_len <= 32 */ 8;
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? omap2_mcspi_set_enable(spi, 1);
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?return count;
> ? ? ? ? ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ?}
> @@ -430,8 +429,10 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (word_len <= 16) ? 2 :
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? /* word_len <= 32 */ 4;
> ? ? ? ? ? ? ? ?}
> - ? ? ? ? ? ? ? omap2_mcspi_set_enable(spi, 1);
> ? ? ? ?}
> +
> + ? ? ? omap2_mcspi_set_enable(spi, 0);
> +
> ? ? ? ?return count;
> ?}
>
> @@ -517,8 +518,6 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?goto out;
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?c = 0;
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? } else if (c == 0 && tx == NULL) {
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? omap2_mcspi_set_enable(spi, 0);
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?}
>
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?*rx++ = __raw_readl(rx_reg);
> @@ -570,8 +569,6 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?goto out;
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?c = 0;
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? } else if (c == 0 && tx == NULL) {
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? omap2_mcspi_set_enable(spi, 0);
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?}
>
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?*rx++ = __raw_readl(rx_reg);
> @@ -623,8 +620,6 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?goto out;
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?c = 0;
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? } else if (c == 0 && tx == NULL) {
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? omap2_mcspi_set_enable(spi, 0);
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?}
>
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?*rx++ = __raw_readl(rx_reg);
> @@ -646,7 +641,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
> ? ? ? ? ? ? ? ? ? ? ? ?dev_err(&spi->dev, "EOT timed out\n");
> ? ? ? ?}
> ?out:
> - ? ? ? omap2_mcspi_set_enable(spi, 1);
> + ? ? ? omap2_mcspi_set_enable(spi, 0);
> ? ? ? ?return count - c;
> ?}
>
> @@ -894,7 +889,6 @@ static void omap2_mcspi_work(struct work_struct *work)
> ? ? ? ? ? ? ? ?cs = spi->controller_state;
> ? ? ? ? ? ? ? ?cd = spi->controller_data;
>
> - ? ? ? ? ? ? ? omap2_mcspi_set_enable(spi, 1);
> ? ? ? ? ? ? ? ?list_for_each_entry(t, &m->transfers, transfer_list) {
> ? ? ? ? ? ? ? ? ? ? ? ?if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?status = -EINVAL;
> @@ -931,6 +925,8 @@ static void omap2_mcspi_work(struct work_struct *work)
>
> ? ? ? ? ? ? ? ? ? ? ? ?mcspi_write_chconf0(spi, chconf);
>
> + ? ? ? ? ? ? ? ? ? ? ? omap2_mcspi_set_enable(spi, 1);
> +
> ? ? ? ? ? ? ? ? ? ? ? ?if (t->len) {
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned ? ? ? ?count;
>
> --
> 1.5.6.5
>
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From linus.walleij at stericsson.com  Thu Jun 24 11:12:17 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 24 Jun 2010 17:12:17 +0200
Subject: [PATCH] MMC: remove regulator refcount fiddling in mmc core
Message-ID: <1277392337-27627-1-git-send-email-linus.walleij@stericsson.com>

Currently the mmc_regulator_set_ocr() fiddles with the regulator
refcount by selectively calling regulator_[enable|disable]
depending on the state of the regulator. This will confuse the
reference count if case the regulator is for example shared with
other MMC slots or user for other stuff than the MMC card.

Push regulator_[enable|disable] out into the MMC host drivers
and remove this from the MMC core so the reference count can be
trusted.

Cc: Andrew Morton <akpm at linux-foundation.org>
Cc: Liam Girdwood <lrg at slimlogic.co.uk>
Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
Cc: Tony Lindgren <tony at atomide.com>
Cc: Adrian Hunter <adrian.hunter at nokia.com>
Cc: Robert Jarzmik <robert.jarzmik at free.fr>
Cc: Sundar Iyer <sundar.iyer at stericsson.com>
Cc: Bengt Jonsson <bengt.jonsson at stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
This has been regression compiled for U300, OMAP3, PXA3XX
defconfigs, tested on U300.

We're facing problems with our regulator reference counters if
this is not fixed.
---
 drivers/mmc/core/core.c       |   66 ++++++++++++++++++-----------------------
 drivers/mmc/host/mmci.c       |   10 ++++--
 drivers/mmc/host/omap_hsmmc.c |   40 ++++++++++++++++++------
 drivers/mmc/host/pxamci.c     |   17 ++++++++--
 4 files changed, 78 insertions(+), 55 deletions(-)

diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 569e94d..904f245 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -784,47 +784,39 @@ int mmc_regulator_set_ocr(struct regulator *supply, unsigned short vdd_bit)
 {
 	int			result = 0;
 	int			min_uV, max_uV;
-	int			enabled;
+	int			tmp;
+	int			voltage;
 
-	enabled = regulator_is_enabled(supply);
-	if (enabled < 0)
-		return enabled;
-
-	if (vdd_bit) {
-		int		tmp;
-		int		voltage;
-
-		/* REVISIT mmc_vddrange_to_ocrmask() may have set some
-		 * bits this regulator doesn't quite support ... don't
-		 * be too picky, most cards and regulators are OK with
-		 * a 0.1V range goof (it's a small error percentage).
-		 */
-		tmp = vdd_bit - ilog2(MMC_VDD_165_195);
-		if (tmp == 0) {
-			min_uV = 1650 * 1000;
-			max_uV = 1950 * 1000;
-		} else {
-			min_uV = 1900 * 1000 + tmp * 100 * 1000;
-			max_uV = min_uV + 100 * 1000;
-		}
-
-		/* avoid needless changes to this voltage; the regulator
-		 * might not allow this operation
-		 */
-		voltage = regulator_get_voltage(supply);
-		if (voltage < 0)
-			result = voltage;
-		else if (voltage < min_uV || voltage > max_uV)
-			result = regulator_set_voltage(supply, min_uV, max_uV);
-		else
-			result = 0;
+	if (!vdd_bit)
+		return 0;
 
-		if (result == 0 && !enabled)
-			result = regulator_enable(supply);
-	} else if (enabled) {
-		result = regulator_disable(supply);
+	/*
+	 * REVISIT mmc_vddrange_to_ocrmask() may have set some
+	 * bits this regulator doesn't quite support ... don't
+	 * be too picky, most cards and regulators are OK with
+	 * a 0.1V range goof (it's a small error percentage).
+	 */
+	tmp = vdd_bit - ilog2(MMC_VDD_165_195);
+	if (tmp == 0) {
+		min_uV = 1650 * 1000;
+		max_uV = 1950 * 1000;
+	} else {
+		min_uV = 1900 * 1000 + tmp * 100 * 1000;
+		max_uV = min_uV + 100 * 1000;
 	}
 
+	/*
+	 * Avoid needless changes to this voltage; the regulator
+	 * might not allow this operation
+	 */
+	voltage = regulator_get_voltage(supply);
+	if (voltage < 0)
+		result = voltage;
+	else if (voltage < min_uV || voltage > max_uV)
+		result = regulator_set_voltage(supply, min_uV, max_uV);
+	else
+		result = 0;
+
 	return result;
 }
 EXPORT_SYMBOL(mmc_regulator_set_ocr);
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 4917af9..5f530b1 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -467,15 +467,17 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 
 	switch (ios->power_mode) {
 	case MMC_POWER_OFF:
-		if(host->vcc &&
-		   regulator_is_enabled(host->vcc))
+		if (host->vcc)
 			regulator_disable(host->vcc);
 		break;
 	case MMC_POWER_UP:
 #ifdef CONFIG_REGULATOR
-		if (host->vcc)
-			/* This implicitly enables the regulator */
+		if (host->vcc) {
+			if (regulator_enable(host->vcc))
+				dev_err(mmc_dev(mmc),
+					"could not enable regulator\n");
 			mmc_regulator_set_ocr(host->vcc, ios->vdd);
+		}
 #endif
 		/*
 		 * The translate_vdd function is not used if you have
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index b032828..d8d07e1 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -247,10 +247,17 @@ static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
 	if (mmc_slot(host).before_set_reg)
 		mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
 
-	if (power_on)
-		ret = mmc_regulator_set_ocr(host->vcc, vdd);
-	else
-		ret = mmc_regulator_set_ocr(host->vcc, 0);
+	if (power_on) {
+		ret = regulator_enable(host->vcc);
+		if (ret)
+			dev_err(dev, "could not enable regulator\n");
+		else
+			ret = mmc_regulator_set_ocr(host->vcc, vdd);
+	} else {
+		ret = regulator_disable(host->vcc);
+		if (ret)
+			dev_err(dev, "could not disable regulator\n");
+	}
 
 	if (mmc_slot(host).after_set_reg)
 		mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
@@ -289,7 +296,11 @@ static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
 	 * chips/cards need an interface voltage rail too.
 	 */
 	if (power_on) {
-		ret = mmc_regulator_set_ocr(host->vcc, vdd);
+		ret = regulator_enable(host->vcc);
+		if (ret < 0)
+			dev_err(dev, "could not enable regulator\n");
+		else
+			ret = mmc_regulator_set_ocr(host->vcc, vdd);
 		/* Enable interface voltage rail, if needed */
 		if (ret == 0 && host->vcc_aux) {
 			ret = regulator_enable(host->vcc_aux);
@@ -297,10 +308,15 @@ static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
 				ret = mmc_regulator_set_ocr(host->vcc, 0);
 		}
 	} else {
+		/* Shut down the rail */
 		if (host->vcc_aux)
 			ret = regulator_disable(host->vcc_aux);
-		if (ret == 0)
-			ret = mmc_regulator_set_ocr(host->vcc, 0);
+		if (ret == 0) {
+			/* Then proeeed to shut down the local regulator */
+			ret = regulator_disable(host->vcc);
+			if (ret == 0)
+				ret = mmc_regulator_set_ocr(host->vcc, 0);
+		}
 	}
 
 	if (mmc_slot(host).after_set_reg)
@@ -340,10 +356,14 @@ static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
 
 	if (cardsleep) {
 		/* VCC can be turned off if card is asleep */
-		if (sleep)
-			err = mmc_regulator_set_ocr(host->vcc, 0);
-		else
+		if (sleep) {
+			err = regulator_disable(host->vcc);
+		} else {
+			err = regulator_enable(host->vcc);
+			if (err)
+				return err;
 			err = mmc_regulator_set_ocr(host->vcc, vdd);
+		}
 	} else
 		err = regulator_set_mode(host->vcc, mode);
 	if (err)
diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
index 0a4e43f..b7e0216 100644
--- a/drivers/mmc/host/pxamci.c
+++ b/drivers/mmc/host/pxamci.c
@@ -99,13 +99,22 @@ static inline void pxamci_init_ocr(struct pxamci_host *host)
 	}
 }
 
-static inline void pxamci_set_power(struct pxamci_host *host, unsigned int vdd)
+static inline void pxamci_set_power(struct pxamci_host *host,
+				    unsigned char power_mode,
+				    unsigned int vdd)
 {
 	int on;
 
 #ifdef CONFIG_REGULATOR
-	if (host->vcc)
-		mmc_regulator_set_ocr(host->vcc, vdd);
+	if (host->vcc) {
+		if (power_mode == MMC_POWER_UP) {
+			if (regulator_enable(host->vcc))
+				dev_err(mmc_dev(host->mmc),
+					"could not enable regulator\n");
+			mmc_regulator_set_ocr(host->vcc, vdd);
+		} else if (power_mode == MMC_POWER_OFF)
+			regulator_disable(host->vcc);
+	}
 #endif
 	if (!host->vcc && host->pdata &&
 	    gpio_is_valid(host->pdata->gpio_power)) {
@@ -492,7 +501,7 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
 	if (host->power_mode != ios->power_mode) {
 		host->power_mode = ios->power_mode;
 
-		pxamci_set_power(host, ios->vdd);
+		pxamci_set_power(host, ios->power_mode, ios->vdd);
 
 		if (ios->power_mode == MMC_POWER_ON)
 			host->cmdat |= CMDAT_INIT;
-- 
1.6.3.3



From dmitry.torokhov at gmail.com  Thu Jun 24 12:39:07 2010
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Thu, 24 Jun 2010 09:39:07 -0700
Subject: [PATCH v2] input/imx_keypad: add PM support
In-Reply-To: <1276801147-4103-1-git-send-email-eric@eukrea.com>
References: <1276801147-4103-1-git-send-email-eric@eukrea.com>
Message-ID: <20100624163907.GB25119@core.coreip.homeip.net>

On Thu, Jun 17, 2010 at 08:59:01PM +0200, Eric B?nard wrote:
> We use keypad_data to enable wakeup from platform data
> 
> suspend/resume is tested on an i.MX27 when keypad is not
> in use and when it's is in use (in which case we immediatly
> get the key pressed at wakeup)
> 
> Signed-off-by: Eric B?nard <eric at eukrea.com>
> Cc: maramaopercheseimorto at gmail.com
> Cc: linux-input at vger.kernel.org
> Cc: dmitry.torokhov at gmail.com
> Cc: linux-arm-kernel at lists.infradead.org
> ---
> v2 :
> 	- simplify suspend & resume functions
> 	- convert to pm_ops
> 
>  drivers/input/keyboard/imx_keypad.c |   40 +++++++++++++++++++++++++++++++++-
>  1 files changed, 38 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/input/keyboard/imx_keypad.c b/drivers/input/keyboard/imx_keypad.c
> index d92c15c..9aa0005 100644
> --- a/drivers/input/keyboard/imx_keypad.c
> +++ b/drivers/input/keyboard/imx_keypad.c
> @@ -364,6 +364,38 @@ static void imx_keypad_inhibit(struct imx_keypad *keypad)
>  	writew(0xff00, keypad->mmio_base + KPCR);
>  }
>  
> +#ifdef CONFIG_PM
> +static int mxc_kpp_suspend(struct device *dev)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct imx_keypad *keypad = platform_get_drvdata(pdev);
> +
> +	keypad->enabled = false;
> +	synchronize_irq(keypad->irq);
> +	disable_irq(keypad->irq);
> +	clk_disable(keypad->clk);
> +

This is not correct. imx_keypad_probe() keypad->enabled = false, waiting for
imx_keypad_open() to be called. However if nobody opens the device and
you go through suspend/resume cycle you'll leave keypad->enabled = true.


BTW, why do you call new functions mxc_kpp_XXX  while the rest of the
driver uses imx_keypad_XXX naming?

Thanks.

-- 
Dmitry


From khilman at deeprootsystems.com  Thu Jun 24 13:34:52 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 24 Jun 2010 10:34:52 -0700
Subject: [PATCH 2/3] OMAP: PM: use omap_device API for suspend/resume
In-Reply-To: <alpine.DEB.2.00.1006232128390.1550@utopia.booyaka.com> (Paul
	Walmsley's message of "Thu, 24 Jun 2010 00:30:37 -0600 (MDT)")
References: <1277336224-24826-1-git-send-email-khilman@deeprootsystems.com>
	<1277336224-24826-3-git-send-email-khilman@deeprootsystems.com>
	<alpine.DEB.2.00.1006232128390.1550@utopia.booyaka.com>
Message-ID: <87bpb0gwqr.fsf@deeprootsystems.com>

Paul Walmsley <paul at pwsan.com> writes:

> Hi Kevin,
>
> aside from these comments:
>
>    http://marc.info/?l=linux-omap&m=127735008820992&w=2
>
> one other minor issue -
>
> On Wed, 23 Jun 2010, Kevin Hilman wrote:
>
>> Hook into the platform bus methods for suspend and resume and
>> use the omap_device API to automatically idle and enable the
>> device on suspend and resume.
>> 
>> This allows device drivers to get rid of direct management of their
>> clocks in their suspend/resume paths, and let omap_device do it for
>> them.
>> 
>> We currently use the _noirq (late suspend, early resume) versions of
>> the suspend/resume methods to ensure that the device is not disabled
>> too early for any drivers also using the _noirq methods.
>> 
>> NOTE: only works for devices with omap_hwmod support.
>> 
>> Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
>> ---
>>  arch/arm/mach-omap2/pm_bus.c |   61 ++++++++++++++++++++++++++++++++++++++++++
>>  1 files changed, 61 insertions(+), 0 deletions(-)
>> 
>> diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
>> index 69acaa5..3787da8 100644
>> --- a/arch/arm/mach-omap2/pm_bus.c
>> +++ b/arch/arm/mach-omap2/pm_bus.c
>> @@ -70,3 +70,64 @@ int platform_pm_runtime_idle(struct device *dev)
>>  };
>>  #endif /* CONFIG_PM_RUNTIME */
>>  
>> +#ifdef CONFIG_SUSPEND
>> +int platform_pm_suspend_noirq(struct device *dev)
>> +{
>> +	struct device_driver *drv = dev->driver;
>> +	struct platform_device *pdev = to_platform_device(dev);
>> +	struct omap_device *odev = to_omap_device(pdev);
>> +	int ret = 0;
>> +
>> +	if (!drv)
>> +		return 0;
>> +
>> +	if (drv->pm) {
>> +		if (drv->pm->suspend_noirq)
>> +			ret = drv->pm->suspend_noirq(dev);
>> +	}
>> +
>> +	if (omap_device_is_valid(odev)) {
>> +		if (odev->flags & OMAP_DEVICE_NO_BUS_SUSPEND) {
>> +			dev_dbg(dev, "no automatic bus-level system resume.\n");
>
> I guess this should read "suspend" above?
>

Yup, thanks.

Kevin


From u.kleine-koenig at pengutronix.de  Thu Jun 24 13:55:28 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Thu, 24 Jun 2010 19:55:28 +0200
Subject: 
In-Reply-To: <4C236EC2.8090506@eukrea.com>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
	<4C236EC2.8090506@eukrea.com>
Message-ID: <20100624175528.GA14838@pengutronix.de>

Hello Eric,

On Thu, Jun 24, 2010 at 04:42:10PM +0200, Eric B?nard wrote:
> Hi Uwe,
>
> Le 24/06/2010 15:48, Uwe Kleine-K?nig a ?crit :
>> this is the next step in the project "clean up the imx port" targeting
>> 2.6.36.  The highlights this time are:
>>
> maybe that would be interesting to rebase your patch serie against
> Sascha's imx-for-2.6.36 in order to include new boards (especially for  
> the patches which change registering nand, i2c, spi and uart) ?
No, I don't want to rebase it.  I hope Sascha just merges my tree.  Do
you know of any problems, I havn't checked if Sascha's branch introduces
any new users of devices I removed.  I make a mental note to check that
after Sascha merged.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From u.kleine-koenig at pengutronix.de  Thu Jun 24 13:59:02 2010
From: u.kleine-koenig at pengutronix.de (=?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?=)
Date: Thu, 24 Jun 2010 19:59:02 +0200
Subject: [PATCH 14/61] ARM: imx: rename mach dir for mx21 and mx27 to mach-imx
In-Reply-To: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <1277402342-24921-1-git-send-email-u.kleine-koenig@pengutronix.de>

Finally all imx code should end up there, start with mach-mx2.  While
touching all files rename some files to use a hyphen instead of an
underscore.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
---
 arch/arm/Makefile                                  |    2 +-
 arch/arm/{mach-mx2 => mach-imx}/Kconfig            |    0
 arch/arm/{mach-mx2 => mach-imx}/Makefile           |    6 +++---
 arch/arm/{mach-mx2 => mach-imx}/Makefile.boot      |    0
 .../clock_imx21.c => mach-imx/clock-imx21.c}       |    0
 .../clock_imx27.c => mach-imx/clock-imx27.c}       |    0
 .../{mach-mx2/cpu_imx27.c => mach-imx/cpu-imx27.c} |    0
 arch/arm/{mach-mx2 => mach-imx}/devices.c          |    0
 arch/arm/{mach-mx2 => mach-imx}/devices.h          |    0
 .../eukrea_mbimx27-baseboard.c                     |    0
 arch/arm/{mach-mx2 => mach-imx}/mach-cpuimx27.c    |    0
 arch/arm/{mach-mx2 => mach-imx}/mach-imx27lite.c   |    0
 arch/arm/{mach-mx2 => mach-imx}/mach-mx21ads.c     |    0
 arch/arm/{mach-mx2 => mach-imx}/mach-mx27_3ds.c    |    0
 arch/arm/{mach-mx2 => mach-imx}/mach-mx27ads.c     |    0
 arch/arm/{mach-mx2 => mach-imx}/mach-mxt_td60.c    |    0
 arch/arm/{mach-mx2 => mach-imx}/mach-pca100.c      |    0
 arch/arm/{mach-mx2 => mach-imx}/mach-pcm038.c      |    0
 arch/arm/{mach-mx2 => mach-imx}/mm-imx21.c         |    2 +-
 arch/arm/{mach-mx2 => mach-imx}/mm-imx27.c         |    2 +-
 arch/arm/{mach-mx2 => mach-imx}/pcm970-baseboard.c |    0
 arch/arm/{mach-mx2 => mach-imx}/serial.c           |    0
 arch/arm/plat-mxc/Kconfig                          |    2 +-
 23 files changed, 7 insertions(+), 7 deletions(-)
 rename arch/arm/{mach-mx2 => mach-imx}/Kconfig (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/Makefile (80%)
 rename arch/arm/{mach-mx2 => mach-imx}/Makefile.boot (100%)
 rename arch/arm/{mach-mx2/clock_imx21.c => mach-imx/clock-imx21.c} (100%)
 rename arch/arm/{mach-mx2/clock_imx27.c => mach-imx/clock-imx27.c} (100%)
 rename arch/arm/{mach-mx2/cpu_imx27.c => mach-imx/cpu-imx27.c} (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/devices.c (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/devices.h (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/eukrea_mbimx27-baseboard.c (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-cpuimx27.c (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-imx27lite.c (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-mx21ads.c (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-mx27_3ds.c (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-mx27ads.c (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-mxt_td60.c (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-pca100.c (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/mach-pcm038.c (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/mm-imx21.c (98%)
 rename arch/arm/{mach-mx2 => mach-imx}/mm-imx27.c (98%)
 rename arch/arm/{mach-mx2 => mach-imx}/pcm970-baseboard.c (100%)
 rename arch/arm/{mach-mx2 => mach-imx}/serial.c (100%)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 64ba313..c60d604 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -146,7 +146,7 @@ machine-$(CONFIG_ARCH_MMP)		:= mmp
 machine-$(CONFIG_ARCH_MSM)		:= msm
 machine-$(CONFIG_ARCH_MV78XX0)		:= mv78xx0
 machine-$(CONFIG_ARCH_MX1)		:= mx1
-machine-$(CONFIG_ARCH_MX2)		:= mx2
+machine-$(CONFIG_ARCH_MX2)		:= imx
 machine-$(CONFIG_ARCH_MX25)		:= mx25
 machine-$(CONFIG_ARCH_MX3)		:= mx3
 machine-$(CONFIG_ARCH_MX5)		:= mx5
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-imx/Kconfig
similarity index 100%
rename from arch/arm/mach-mx2/Kconfig
rename to arch/arm/mach-imx/Kconfig
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-imx/Makefile
similarity index 80%
rename from arch/arm/mach-mx2/Makefile
rename to arch/arm/mach-imx/Makefile
index e3254fa..068f493 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -6,10 +6,10 @@
 
 obj-y	:=  devices.o serial.o
 
-obj-$(CONFIG_MACH_MX21) += clock_imx21.o mm-imx21.o
+obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
 
-obj-$(CONFIG_MACH_MX27) += cpu_imx27.o
-obj-$(CONFIG_MACH_MX27) += clock_imx27.o mm-imx27.o
+obj-$(CONFIG_MACH_MX27) += cpu-imx27.o
+obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
 
 obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
 obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
diff --git a/arch/arm/mach-mx2/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
similarity index 100%
rename from arch/arm/mach-mx2/Makefile.boot
rename to arch/arm/mach-imx/Makefile.boot
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-imx/clock-imx21.c
similarity index 100%
rename from arch/arm/mach-mx2/clock_imx21.c
rename to arch/arm/mach-imx/clock-imx21.c
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-imx/clock-imx27.c
similarity index 100%
rename from arch/arm/mach-mx2/clock_imx27.c
rename to arch/arm/mach-imx/clock-imx27.c
diff --git a/arch/arm/mach-mx2/cpu_imx27.c b/arch/arm/mach-imx/cpu-imx27.c
similarity index 100%
rename from arch/arm/mach-mx2/cpu_imx27.c
rename to arch/arm/mach-imx/cpu-imx27.c
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-imx/devices.c
similarity index 100%
rename from arch/arm/mach-mx2/devices.c
rename to arch/arm/mach-imx/devices.c
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-imx/devices.h
similarity index 100%
rename from arch/arm/mach-mx2/devices.h
rename to arch/arm/mach-imx/devices.h
diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
similarity index 100%
rename from arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
rename to arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
diff --git a/arch/arm/mach-mx2/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
similarity index 100%
rename from arch/arm/mach-mx2/mach-cpuimx27.c
rename to arch/arm/mach-imx/mach-cpuimx27.c
diff --git a/arch/arm/mach-mx2/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
similarity index 100%
rename from arch/arm/mach-mx2/mach-imx27lite.c
rename to arch/arm/mach-imx/mach-imx27lite.c
diff --git a/arch/arm/mach-mx2/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
similarity index 100%
rename from arch/arm/mach-mx2/mach-mx21ads.c
rename to arch/arm/mach-imx/mach-mx21ads.c
diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
similarity index 100%
rename from arch/arm/mach-mx2/mach-mx27_3ds.c
rename to arch/arm/mach-imx/mach-mx27_3ds.c
diff --git a/arch/arm/mach-mx2/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
similarity index 100%
rename from arch/arm/mach-mx2/mach-mx27ads.c
rename to arch/arm/mach-imx/mach-mx27ads.c
diff --git a/arch/arm/mach-mx2/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
similarity index 100%
rename from arch/arm/mach-mx2/mach-mxt_td60.c
rename to arch/arm/mach-imx/mach-mxt_td60.c
diff --git a/arch/arm/mach-mx2/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
similarity index 100%
rename from arch/arm/mach-mx2/mach-pca100.c
rename to arch/arm/mach-imx/mach-pca100.c
diff --git a/arch/arm/mach-mx2/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
similarity index 100%
rename from arch/arm/mach-mx2/mach-pcm038.c
rename to arch/arm/mach-imx/mach-pcm038.c
diff --git a/arch/arm/mach-mx2/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
similarity index 98%
rename from arch/arm/mach-mx2/mm-imx21.c
rename to arch/arm/mach-imx/mm-imx21.c
index 6413431..115c212 100644
--- a/arch/arm/mach-mx2/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-mx2/mm-imx21.c
+ * arch/arm/mach-imx/mm-imx21.c
  *
  * Copyright (C) 2008 Juergen Beisert (kernel at pengutronix.de)
  *
diff --git a/arch/arm/mach-mx2/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
similarity index 98%
rename from arch/arm/mach-mx2/mm-imx27.c
rename to arch/arm/mach-imx/mm-imx27.c
index 3366ed4..89b4174 100644
--- a/arch/arm/mach-mx2/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -1,5 +1,5 @@
 /*
- * arch/arm/mach-mx2/mm-imx27.c
+ * arch/arm/mach-imx/mm-imx27.c
  *
  * Copyright (C) 2008 Juergen Beisert (kernel at pengutronix.de)
  *
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
similarity index 100%
rename from arch/arm/mach-mx2/pcm970-baseboard.c
rename to arch/arm/mach-imx/pcm970-baseboard.c
diff --git a/arch/arm/mach-mx2/serial.c b/arch/arm/mach-imx/serial.c
similarity index 100%
rename from arch/arm/mach-mx2/serial.c
rename to arch/arm/mach-imx/serial.c
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 7f7ad6f..4974fcc 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -49,7 +49,7 @@ config ARCH_MX5
 endchoice
 
 source "arch/arm/mach-mx1/Kconfig"
-source "arch/arm/mach-mx2/Kconfig"
+source "arch/arm/mach-imx/Kconfig"
 source "arch/arm/mach-mx3/Kconfig"
 source "arch/arm/mach-mx25/Kconfig"
 source "arch/arm/mach-mxc91231/Kconfig"
-- 
1.7.1



From lilja.magnus at gmail.com  Thu Jun 24 14:05:53 2010
From: lilja.magnus at gmail.com (Magnus Lilja)
Date: Thu, 24 Jun 2010 20:05:53 +0200
Subject: [PATCH] mx31_3ds: Allow selection between host/device modes on
	the OTG port
In-Reply-To: <343567.80487.qm@web51007.mail.re2.yahoo.com>
References: <343567.80487.qm@web51007.mail.re2.yahoo.com>
Message-ID: <4C239E81.4040805@gmail.com>

Hi Fabio,

On 2010-06-23 22:52, Fabio Estevam wrote:
> Allow selection between host/device modes on the OTG port.
> 
> Selection is made via kernel command line option:
> 
> 'otg_mode=host' or 'otg_mode=device'. Default mode is device.


Would it be possible to select between host and device during run-time, e.g. when the USB modules are loaded? I'm asking out of curiosity, I don't know if Linux supports this at all.


Regards, Magnus


From marek.vasut at gmail.com  Thu Jun 24 14:51:27 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 24 Jun 2010 20:51:27 +0200
Subject: [PATCH 3/4] pxa2xx/cpufreq: Fix PCMCIA frequency scaling
In-Reply-To: <87mxulabaw.fsf@free.fr>
References: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
	<1276840135-5982-3-git-send-email-marek.vasut@gmail.com>
	<87mxulabaw.fsf@free.fr>
Message-ID: <201006242051.27790.marek.vasut@gmail.com>

Dne St 23. ?ervna 2010 19:49:59 Robert Jarzmik napsal(a):
> Marek Vasut <marek.vasut at gmail.com> writes:
> > The MCxx values must be based off memory clock, not CPU core clock.
> > 
> > This also fixes the bug where on some machines the LCD went crazy while
> > using PCMCIA.
> 
> That looks correct to me.
> 
> Reviewed-by: Robert Jarzmik <robert.jarzmik at free.fr>
> 
> Cheers.
> 
> --
> Robert

Actually lemme rethink this ... it might still be incorrect.


From linux at arm.linux.org.uk  Thu Jun 24 15:12:08 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Thu, 24 Jun 2010 20:12:08 +0100
Subject: [PATCH 3/4] pxa2xx/cpufreq: Fix PCMCIA frequency scaling
In-Reply-To: <201006242051.27790.marek.vasut@gmail.com>
References: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
	<1276840135-5982-3-git-send-email-marek.vasut@gmail.com>
	<87mxulabaw.fsf@free.fr> <201006242051.27790.marek.vasut@gmail.com>
Message-ID: <20100624191208.GB7974@n2100.arm.linux.org.uk>

On Thu, Jun 24, 2010 at 08:51:27PM +0200, Marek Vasut wrote:
> Dne St 23. ?ervna 2010 19:49:59 Robert Jarzmik napsal(a):
> > Marek Vasut <marek.vasut at gmail.com> writes:
> > > The MCxx values must be based off memory clock, not CPU core clock.
> > > 
> > > This also fixes the bug where on some machines the LCD went crazy while
> > > using PCMCIA.
> > 
> > That looks correct to me.
> > 
> > Reviewed-by: Robert Jarzmik <robert.jarzmik at free.fr>
> > 
> > Cheers.
> > 
> > --
> > Robert
> 
> Actually lemme rethink this ... it might still be incorrect.

As Nicolas was the one who originally wrote that code, while he was
working for Montavista and interacting with Intel, I'd be surprised
if he didn't try finding out what the right answer is to that fixme.

I suspect as the fixme remained that there was no clear answer.

Nicolas, can you shed any light on this:

static int
pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
                               unsigned long val,
                               struct cpufreq_freqs *freqs)
{
#warning "it's not clear if this is right since the core CPU (N) clock has no effect on the memory (L) clock"


From marek.vasut at gmail.com  Thu Jun 24 15:33:07 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 24 Jun 2010 21:33:07 +0200
Subject: [PATCH 3/4] pxa2xx/cpufreq: Fix PCMCIA frequency scaling
In-Reply-To: <20100624191208.GB7974@n2100.arm.linux.org.uk>
References: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
	<201006242051.27790.marek.vasut@gmail.com>
	<20100624191208.GB7974@n2100.arm.linux.org.uk>
Message-ID: <201006242133.07899.marek.vasut@gmail.com>

Dne ?t 24. ?ervna 2010 21:12:08 Russell King - ARM Linux napsal(a):
> On Thu, Jun 24, 2010 at 08:51:27PM +0200, Marek Vasut wrote:
> > Dne St 23. ?ervna 2010 19:49:59 Robert Jarzmik napsal(a):
> > > Marek Vasut <marek.vasut at gmail.com> writes:
> > > > The MCxx values must be based off memory clock, not CPU core clock.
> > > > 
> > > > This also fixes the bug where on some machines the LCD went crazy
> > > > while using PCMCIA.
> > > 
> > > That looks correct to me.
> > > 
> > > Reviewed-by: Robert Jarzmik <robert.jarzmik at free.fr>
> > > 
> > > Cheers.
> > > 
> > > --
> > > Robert
> > 
> > Actually lemme rethink this ... it might still be incorrect.

Rethought ... well I think there's no problem with this. Anyway, thanks for 
CCing Nico.

This patch fixed an issue on zaurus so I believe it's ok.
> 
> As Nicolas was the one who originally wrote that code, while he was
> working for Montavista and interacting with Intel, I'd be surprised
> if he didn't try finding out what the right answer is to that fixme.
> 
> I suspect as the fixme remained that there was no clear answer.

Well if you look into some schematics, you see the pxa pcmcia is connected to 
the memory bus ... as other peripherals.

> 
> Nicolas, can you shed any light on this:
> 
> static int
> pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
>                                unsigned long val,
>                                struct cpufreq_freqs *freqs)
> {
> #warning "it's not clear if this is right since the core CPU (N) clock has
> no effect on the memory (L) clock"

Cheers

PS. Russell ... feel like doing some politics again? ;-) (take it as a joke 
please)


From eric at eukrea.com  Thu Jun 24 15:48:12 2010
From: eric at eukrea.com (=?ISO-8859-1?Q?Eric_B=E9nard?=)
Date: Thu, 24 Jun 2010 21:48:12 +0200
Subject: 
In-Reply-To: <20100624175528.GA14838@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>	<4C236EC2.8090506@eukrea.com>
	<20100624175528.GA14838@pengutronix.de>
Message-ID: <4C23B67C.7090207@eukrea.com>

Hi Uwe,

Le 24/06/2010 19:55, Uwe Kleine-K?nig a ?crit :
> On Thu, Jun 24, 2010 at 04:42:10PM +0200, Eric B?nard wrote:
>> Le 24/06/2010 15:48, Uwe Kleine-K?nig a ?crit :
>>> this is the next step in the project "clean up the imx port" targeting
>>> 2.6.36.  The highlights this time are:
>>>
>> maybe that would be interesting to rebase your patch serie against
>> Sascha's imx-for-2.6.36 in order to include new boards (especially for
>> the patches which change registering nand, i2c, spi and uart) ?
> No, I don't want to rebase it.  I hope Sascha just merges my tree.  Do
> you know of any problems, I havn't checked if Sascha's branch introduces
> any new users of devices I removed.  I make a mental note to check thatOK
> after Sascha merged.
>
There are at least my i.MX25 and i.MX35 machines that I would have 
updated to you patch serie and tested but trying to merge your branch 
over Sasha's imx-for-2.6.36 + kernel.org tree at 2.6.35-rc3 leads to at 
least 9 conflitcs.
How do you manage to merge this simply in order to test it ?
I added your branch as a remote tree, then fetched it, then merged it : 
is there any magic git sequence missing here that would help to reduce 
the number of conflicts ?

Thanks,
Eric


From nico at fluxnic.net  Thu Jun 24 15:46:51 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Thu, 24 Jun 2010 15:46:51 -0400 (EDT)
Subject: [PATCH 3/4] pxa2xx/cpufreq: Fix PCMCIA frequency scaling
In-Reply-To: <20100624191208.GB7974@n2100.arm.linux.org.uk>
References: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com>
	<1276840135-5982-3-git-send-email-marek.vasut@gmail.com>
	<87mxulabaw.fsf@free.fr> <201006242051.27790.marek.vasut@gmail.com>
	<20100624191208.GB7974@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.00.1006241542380.24097@xanadu.home>

On Thu, 24 Jun 2010, Russell King - ARM Linux wrote:

> On Thu, Jun 24, 2010 at 08:51:27PM +0200, Marek Vasut wrote:
> > Dne St 23. ?ervna 2010 19:49:59 Robert Jarzmik napsal(a):
> > > Marek Vasut <marek.vasut at gmail.com> writes:
> > > > The MCxx values must be based off memory clock, not CPU core clock.
> > > > 
> > > > This also fixes the bug where on some machines the LCD went crazy while
> > > > using PCMCIA.
> > > 
> > > That looks correct to me.
> > > 
> > > Reviewed-by: Robert Jarzmik <robert.jarzmik at free.fr>
> > > 
> > > Cheers.
> > > 
> > > --
> > > Robert
> > 
> > Actually lemme rethink this ... it might still be incorrect.
> 
> As Nicolas was the one who originally wrote that code, while he was
> working for Montavista and interacting with Intel, I'd be surprised
> if he didn't try finding out what the right answer is to that fixme.

Well, I might have tried, or I might not have and this simply was never 
revisited. But I clearly don't remember any of the context anymore.

> I suspect as the fixme remained that there was no clear answer.

Whatever works in practice is probably the best answer at this point.


Nicolas

From igawa at mxs.nes.nec.co.jp  Thu Jun 24 19:31:33 2010
From: igawa at mxs.nes.nec.co.jp (Masayuki Igawa)
Date: Fri, 25 Jun 2010 08:31:33 +0900 (JST)
Subject: [PATCH 3/3] add ARM crashdump support
In-Reply-To: <20100624081915.GF29920@esdhcp04058.research.nokia.com>
References: <b567a76e7f4502ccd56f818ebd3d6509ebd4a96d.1277188128.git.ext-mika.1.westerberg@nokia.com>
	<20100624163356.dbb849bc.igawa@mxs.nes.nec.co.jp>
	<20100624081915.GF29920@esdhcp04058.research.nokia.com>
Message-ID: <20100625.083133.77342472.igawa@mxs.nes.nec.co.jp>

Hi,

From: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
Date: Thu, 24 Jun 2010 11:19:15 +0300
> On Thu, Jun 24, 2010 at 09:33:56AM +0200, ext Masayuki Igawa wrote:
>> Hi, Mika.
> 
> (...)

>> How about is this?
>> ====
>> +unsigned long long
>> +vaddr_to_paddr_arm(unsigned long vaddr)
>> +{
>> +	unsigned long long paddr = vaddr_to_paddr_general(vaddr);
>> +
>> +	if (paddr != NOT_PADDR)
>> +		return paddr;
>> ====
> 
> Yeah, looks OK to me.
> 
> Do you want me to send a revisited version of the patches or do you change that
> yourself?

I'll change that myself.

> 
>> BTW, I'm testing these patches for x86/x86_64 arch now.
>> I'll merge these patches after my testing.
> 
> Cool, thanks.
> 
>> But I cannot test for ARM because have no test machines of ARM.
> 
> Well I can do the testing for ARM (unless someone else, who is using ARM kdump
> currently, wants to test this). If the above is the only change it should still
> work.

OK. I'll merge and push these patches (including this change).
And I'd like you to do the testing for ARM after that.

Thanks,
-- Masayuki Igawa


From khilman at deeprootsystems.com  Thu Jun 24 19:43:08 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 24 Jun 2010 16:43:08 -0700
Subject: [PATCH v2 0/3] OMAP: add runtime PM support at bus-level
Message-ID: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>

This series introduces runtime PM support at the platform bus level
for OMAP.

In a nutshell, when using the runtime PM API for any device with an
assocated omap_device (and hwmod), the omap device API will be used to
handle the hardware-level power management of that device, including
managing clocks, etc.

Today, most drivers handle this by manually enabling/disabling their
clocks when needed.  With this series (and an omap_device/hwmod for
each device) direct clock managment can be removed from the driver in
favor of using the runtime PM API.

This series applies on top v2.6.35-rc2 + Tony's omap-fixes branch and
is also available in the pm-wip/runtime branch of my linux-omap-pm git
tree:

  git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm.git

Kevin Hilman (3):
  OMAP: PM: initial runtime PM core support
  OMAP: bus-level PM: enable use of runtime PM API for suspend/resume
  OMAP1: PM: add simple runtime PM layer to manage clocks

 arch/arm/mach-omap1/Makefile |    2 +-
 arch/arm/mach-omap1/pm_bus.c |   77 +++++++++++++++++++++++++++
 arch/arm/mach-omap2/Makefile |    7 ++-
 arch/arm/mach-omap2/pm_bus.c |  118 ++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 202 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-omap1/pm_bus.c
 create mode 100644 arch/arm/mach-omap2/pm_bus.c



From khilman at deeprootsystems.com  Thu Jun 24 19:43:09 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 24 Jun 2010 16:43:09 -0700
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>

Implement the new runtime PM framework as a thin layer on top of the
omap_device API.  Since we don't have an OMAP-specific bus, override
the runtime PM hooks for the platform_bus for the OMAP specific
implementation.

While the runtime PM API has three main states (idle, suspend, resume)
This version treats idle and suspend the same way by implementing both
on top of omap_device_disable(), which follows closely with how driver
are currently using clock enable/disable calls. Longer-termm
pm_runtime_idle() could take other constraints into consideration to
make the decision, but the current

Device driver ->runtime_suspend() hooks are called just before the
device is disabled (via omap_device_idle()), and device driver
->runtime_resume() hooks are called just after device has been
enabled (via omap_device_enable().)

Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-omap2/Makefile |    7 +++-
 arch/arm/mach-omap2/pm_bus.c |   70 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 76 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap2/pm_bus.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ea52b03..8ed47ea 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -46,12 +46,17 @@ obj-$(CONFIG_ARCH_OMAP2)		+= sdrc2xxx.o
 ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)		+= pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)		+= sleep24xx.o
-obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP3)		+= pm34xx.o sleep34xx.o cpuidle34xx.o \
+					   pm_bus.o
 obj-$(CONFIG_PM_DEBUG)			+= pm-debug.o
 
 AFLAGS_sleep24xx.o			:=-Wa,-march=armv6
 AFLAGS_sleep34xx.o			:=-Wa,-march=armv7-a
 
+ifeq ($(CONFIG_PM_VERBOSE),y)
+CFLAGS_pm_bus.o				+= -DDEBUG
+endif
+
 endif
 
 # PRCM
diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
new file mode 100644
index 0000000..9719a9f
--- /dev/null
+++ b/arch/arm/mach-omap2/pm_bus.c
@@ -0,0 +1,70 @@
+/*
+ * Runtime PM support code for OMAP
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+
+#include <plat/omap_device.h>
+#include <plat/omap-pm.h>
+
+#ifdef CONFIG_PM_RUNTIME
+int platform_pm_runtime_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_device *odev = to_omap_device(pdev);
+	int r, ret = 0;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	if (dev->driver->pm && dev->driver->pm->runtime_suspend)
+		ret = dev->driver->pm->runtime_suspend(dev);
+	if (!ret && omap_device_is_valid(odev)) {
+		r = omap_device_idle(pdev);
+		WARN_ON(r);
+	}
+
+	return ret;
+};
+
+int platform_pm_runtime_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct omap_device *odev = to_omap_device(pdev);
+	int r, ret = 0;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	if (omap_device_is_valid(odev)) {
+		r = omap_device_enable(pdev);
+		WARN_ON(r);
+	}
+
+	if (dev->driver->pm && dev->driver->pm->runtime_resume)
+		ret = dev->driver->pm->runtime_resume(dev);
+
+	return ret;
+};
+
+int platform_pm_runtime_idle(struct device *dev)
+{
+	int ret;
+
+	ret = pm_runtime_suspend(dev);
+	dev_dbg(dev, "%s [%d]\n", __func__, ret);
+
+	return 0;
+};
+#endif /* CONFIG_PM_RUNTIME */
+
-- 
1.7.0.2



From khilman at deeprootsystems.com  Thu Jun 24 19:43:10 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 24 Jun 2010 16:43:10 -0700
Subject: [PATCH v2 2/3] OMAP: bus-level PM: enable use of runtime PM API for
	suspend/resume
In-Reply-To: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1277422991-25350-3-git-send-email-khilman@deeprootsystems.com>

Hook into the platform bus methods for suspend and resume and use the
runtime PM API to allow the OMAP runtime PM core (based on
omap_device) to automatically idle and enable the device on suspend
and resume.

This allows device drivers to get rid of direct management of their
clocks in their suspend/resume paths, and let omap_device do it for
them .

We currently use the _noirq (late suspend, early resume) versions of
the suspend/resume methods to ensure that the device is not disabled
too early for any drivers also using the _noirq methods.

NOTE: only works for devices with omap_hwmod support.

Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-omap2/pm_bus.c |   48 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
index 9719a9f..5e453dc 100644
--- a/arch/arm/mach-omap2/pm_bus.c
+++ b/arch/arm/mach-omap2/pm_bus.c
@@ -68,3 +68,51 @@ int platform_pm_runtime_idle(struct device *dev)
 };
 #endif /* CONFIG_PM_RUNTIME */
 
+#ifdef CONFIG_SUSPEND
+int platform_pm_suspend_noirq(struct device *dev)
+{
+	struct device_driver *drv = dev->driver;
+	int ret = 0;
+
+	if (!drv)
+		return 0;
+
+	if (drv->pm) {
+		if (drv->pm->suspend_noirq)
+			ret = drv->pm->suspend_noirq(dev);
+	}
+
+	/*
+	 * The DPM core has done a 'get' to prevent runtime PM
+	 * transitions during system PM.  This put is to balance
+	 * out that get so that this device can now be runtime
+	 * suspended.
+	 */
+	pm_runtime_put_sync(dev);
+
+	return ret;
+}
+
+int platform_pm_resume_noirq(struct device *dev)
+{
+	struct device_driver *drv = dev->driver;
+	int ret = 0;
+
+	/* 
+	 * This 'get' is to balance the 'put' in the above suspend_noirq
+	 * method so that the runtime PM usage counting is in the same
+	 * state it was when suspend was called.
+	 */
+	pm_runtime_get_sync(dev);
+
+	if (!drv)
+		return 0;
+
+	if (drv->pm) {
+		if (drv->pm->resume_noirq)
+			ret = drv->pm->resume_noirq(dev);
+	}
+
+	return ret;
+}
+#endif /* CONFIG_SUSPEND */
-- 
1.7.0.2



From khilman at deeprootsystems.com  Thu Jun 24 19:43:11 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Thu, 24 Jun 2010 16:43:11 -0700
Subject: [PATCH v2 3/3] OMAP1: PM: add simple runtime PM layer to manage clocks
In-Reply-To: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
Message-ID: <1277422991-25350-4-git-send-email-khilman@deeprootsystems.com>

On OMAP1, we do not have omap_device + omap_hwmod to manage the
device-specific idle, enable and shutdown.  Instead, just
enable/disable device clocks automatically at the runtime PM level.

This allows drivers to not have any OMAP1 specific clock management
and allows them to simply use the runtime PM API to manage clocks.

Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
---
 arch/arm/mach-omap1/Makefile |    2 +-
 arch/arm/mach-omap1/pm_bus.c |   77 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-omap1/pm_bus.c

diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index ea231c7..fd4df71 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_OMAP_MPU_TIMER)	+= time.o
 obj-$(CONFIG_OMAP_32K_TIMER)	+= timer32k.o
 
 # Power Management
-obj-$(CONFIG_PM) += pm.o sleep.o
+obj-$(CONFIG_PM) += pm.o sleep.o pm_bus.o
 
 # DSP
 obj-$(CONFIG_OMAP_MBOX_FWK)	+= mailbox_mach.o
diff --git a/arch/arm/mach-omap1/pm_bus.c b/arch/arm/mach-omap1/pm_bus.c
new file mode 100644
index 0000000..29d651a
--- /dev/null
+++ b/arch/arm/mach-omap1/pm_bus.c
@@ -0,0 +1,77 @@
+/*
+ * Runtime PM support code for OMAP1
+ *
+ * Author: Kevin Hilman, Deep Root Systems, LLC
+ *
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/pm_runtime.h>
+#include <linux/platform_device.h>
+#include <linux/mutex.h>
+
+#include <plat/omap_device.h>
+#include <plat/omap-pm.h>
+
+#ifdef CONFIG_PM_RUNTIME
+int platform_pm_runtime_suspend(struct device *dev)
+{
+	struct clk *iclk, *fclk;
+
+	dev_dbg(dev, "%s\n", __func__);
+
+	if (dev->driver->pm && dev->driver->pm->runtime_suspend)
+		ret = dev->driver->pm->runtime_suspend(dev);
+
+	fclk = clk_get(dev, "fck");
+	if (!IS_ERR(fclk)) {
+		clk_disable(fclk);
+		clk_put(fclk);
+	}
+
+	iclk = clk_get(dev, "ick");
+	if (!IS_ERR(iclk)) {
+		clk_disable(iclk);
+		clk_put(iclk);
+	}
+
+	return 0;
+};
+
+int platform_pm_runtime_resume(struct device *dev)
+{
+	int r, ret = 0;
+	struct clk *iclk, *fclk;
+
+	iclk = clk_get(dev, "ick");
+	if (!IS_ERR(iclk)) {
+		clk_enable(iclk);
+		clk_put(iclk);
+	}
+
+	fclk = clk_get(dev, "fck");
+	if (!IS_ERR(fclk)) {
+		clk_enable(fclk);
+		clk_put(fclk);
+	}
+
+	if (dev->driver->pm && dev->driver->pm->runtime_resume)
+		ret = dev->driver->pm->runtime_resume(dev);
+
+	return ret;
+};
+
+int platform_pm_runtime_idle(struct device *dev)
+{
+	ret = pm_runtime_suspend(dev);
+	dev_dbg(dev, "%s [%d]\n", __func__, ret);
+
+	return 0;
+};
+#endif /* CONFIG_PM_RUNTIME */
-- 
1.7.0.2



From rabin at rab.in  Thu Jun 24 22:09:22 2010
From: rabin at rab.in (Rabin Vincent)
Date: Fri, 25 Jun 2010 07:39:22 +0530
Subject: strange segfaults with CompactFlash in "true-ide" mode on PXA270
In-Reply-To: <19490.10015.10027.750374@ipc1.ka-ro>
References: <201006231706.33182.schindele@nentec.de>
	<19490.10015.10027.750374@ipc1.ka-ro>
Message-ID: <AANLkTilj-ma9RgIBZNtJLlNFWsSDLG5tHfdllG_0_wNY@mail.gmail.com>

On Wed, Jun 23, 2010 at 8:54 PM, Lothar Wa?mann <LW at karo-electronics.de> wrote:
>> we have a strange problem when booting from a Compact Flash card
>> as root-device. In one of 10 cases while booting an application from
>> root-filesystem dies with "Segmentation fault" without a visible error.
>> After booting the same application runs hundred times without error.
>> (we're talking about standard appl. like chat, pppd, hwclock and so on)
>>
>> For debugging purposes we put printk's in kernels IDE driver
>> and the problem disappeared. But replacing the printk by a usleep
>> or so (which is not a solution !) brings the problem back.
>> It seems that the application received faulty data from CF.
>> But how and why ?????????????????????????????
>>
>> We tested with a custom PXA270 board with a CompactFlash in
>> "true ide" on processor bus driven by "generic ide / pata_platform"
>> driver from linux-2.6.27.x.
>> (by the way linux-2.6.20.x showed the same problem).
>>
>> Any ideas, hints, experiences, patches are very welcome :-)
>> --------------------------------------------------------------
> I guess that is the old cache problem that apparently was never really
> fixed:
> http://marc.info/?t=108537828400002&r=1&w=2

Catalin recently posted some patches addressing the cache
problem:

http://thread.gmane.org/gmane.linux.ports.arm.kernel/82987

Rabin


From kgene.kim at samsung.com  Thu Jun 24 23:38:19 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 25 Jun 2010 12:38:19 +0900
Subject: [PATCH v4] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <4C22704B.50103@pobox.com>
References: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
	<4C22704B.50103@pobox.com>
Message-ID: <001f01cb1417$dce8f8d0$96baea70$%kim@samsung.com>

Jeff Garzik wrote:
> 
> On 06/14/2010 03:07 AM, Kukjin Kim wrote:
> > From: Abhilash Kesavan<a.kesavan at samsung.com>
> >
> > Adds support for the Samsung PATA controller. This driver is based on
the
> > Libata subsystem and references the earlier patches sent for IDE
subsystem.
> >
> > Signed-off-by: Abhilash Kesavan<a.kesavan at samsung.com>
> > Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
> 
> Acked-by: Jeff Garzik <jgarzik at redhat.com>
> 
> Send it through the appropriate subsystem tree for this platform...

Hi,

You mean in my case, appropriate subsystem tree is ARM tree.
But I think, as Ben commented, it's better drivers go to upstream via the
driver's tree.
And of course, I read your comments about this like below...
'platform drivers do not build and/or work without additional platform
glue...'

Hmm.
I'm not sure which way is better...

Russell,

How do you think?
May I send this to your patch tracking system?
Or...how should I handle this?

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From marek.vasut at gmail.com  Fri Jun 25 00:18:36 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Fri, 25 Jun 2010 06:18:36 +0200
Subject: [PATCH v4] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <001f01cb1417$dce8f8d0$96baea70$%kim@samsung.com>
References: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
	<4C22704B.50103@pobox.com>
	<001f01cb1417$dce8f8d0$96baea70$%kim@samsung.com>
Message-ID: <201006250618.37076.marek.vasut@gmail.com>

Dne P? 25. ?ervna 2010 05:38:19 Kukjin Kim napsal(a):
> Jeff Garzik wrote:
> > On 06/14/2010 03:07 AM, Kukjin Kim wrote:
> > > From: Abhilash Kesavan<a.kesavan at samsung.com>
> > > 
> > > Adds support for the Samsung PATA controller. This driver is based on
> 
> the
> 
> > > Libata subsystem and references the earlier patches sent for IDE
> 
> subsystem.
> 
> > > Signed-off-by: Abhilash Kesavan<a.kesavan at samsung.com>
> > > Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
> > 
> > Acked-by: Jeff Garzik <jgarzik at redhat.com>
> > 
> > Send it through the appropriate subsystem tree for this platform...
> 
> Hi,
> 
> You mean in my case, appropriate subsystem tree is ARM tree.
> But I think, as Ben commented, it's better drivers go to upstream via the
> driver's tree.
> And of course, I read your comments about this like below...
> 'platform drivers do not build and/or work without additional platform
> glue...'
> 
> Hmm.
> I'm not sure which way is better...

I pushed pata_pxa through Eric as well ... go for the linux-arm tree.
Cheers
> 
> Russell,
> 
> How do you think?
> May I send this to your patch tracking system?
> Or...how should I handle this?
> 
> Thanks.
> 
> Best regards,
> Kgene.
> --
> Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
> SW Solution Development Team, Samsung Electronics Co., Ltd.
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-ide" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From davem at davemloft.net  Fri Jun 25 01:05:48 2010
From: davem at davemloft.net (David Miller)
Date: Thu, 24 Jun 2010 22:05:48 -0700 (PDT)
Subject: [PATCH 1/2] net/fec: clean suspend/resume
In-Reply-To: <1276853351-20790-1-git-send-email-eric@eukrea.com>
References: <1276853351-20790-1-git-send-email-eric@eukrea.com>
Message-ID: <20100624.220548.02285361.davem@davemloft.net>

From: Eric B?nard <eric at eukrea.com>
Date: Fri, 18 Jun 2010 11:29:10 +0200

> Commit 59d4289b83b11379d867e2f7146904b19cc96404 converted fec to dev_pm_ops but
> didn't update the suspend/resume functions thus leading to the following warning :
> "initialization from incompatible pointer type" when CONFIG_PM is set.
> 
> This patch also fixe a few indentation and style around CONFIG_PM area.
> 
> Signed-off-by: Eric B?nard <eric at eukrea.com>

So, where's patch 2/2?


From u.kleine-koenig at pengutronix.de  Fri Jun 25 01:10:16 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 25 Jun 2010 07:10:16 +0200
Subject: 
In-Reply-To: <4C23B67C.7090207@eukrea.com>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
	<4C236EC2.8090506@eukrea.com>
	<20100624175528.GA14838@pengutronix.de>
	<4C23B67C.7090207@eukrea.com>
Message-ID: <20100625051016.GA31164@pengutronix.de>

On Thu, Jun 24, 2010 at 09:48:12PM +0200, Eric B?nard wrote:
> Hi Uwe,
>
> Le 24/06/2010 19:55, Uwe Kleine-K?nig a ?crit :
>> On Thu, Jun 24, 2010 at 04:42:10PM +0200, Eric B?nard wrote:
>>> Le 24/06/2010 15:48, Uwe Kleine-K?nig a ?crit :
>>>> this is the next step in the project "clean up the imx port" targeting
>>>> 2.6.36.  The highlights this time are:
>>>>
>>> maybe that would be interesting to rebase your patch serie against
>>> Sascha's imx-for-2.6.36 in order to include new boards (especially for
>>> the patches which change registering nand, i2c, spi and uart) ?
>> No, I don't want to rebase it.  I hope Sascha just merges my tree.  Do
>> you know of any problems, I havn't checked if Sascha's branch introduces
>> any new users of devices I removed.  I make a mental note to check thatOK
>> after Sascha merged.
>>
> There are at least my i.MX25 and i.MX35 machines that I would have  
> updated to you patch serie and tested but trying to merge your branch  
> over Sasha's imx-for-2.6.36 + kernel.org tree at 2.6.35-rc3 leads to at  
> least 9 conflitcs.
> How do you manage to merge this simply in order to test it ?
> I added your branch as a remote tree, then fetched it, then merged it :  
> is there any magic git sequence missing here that would help to reduce  
> the number of conflicts ?
No, but these conflicts aren't that hard to resolve.  Check out my
imx/for-2.6.36-merged branch.

BTW there are two warnings about 'otg_pdata' and 'usbh2_pdata' defined
but not used with the config I tested.  And it would have been more
consistent to name your machine source file mach-eukrea_cpuimx25.c.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From m.szyprowski at samsung.com  Fri Jun 25 01:33:10 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 25 Jun 2010 07:33:10 +0200
Subject: [PATCH v2 0/4] ARM: S5P: Support gpio interrupts
In-Reply-To: <004601cb12a8$c869e560$593db020$%kim@samsung.com>
References: <4C11F4CA.10802@samsung.com>
	<004601cb12a8$c869e560$593db020$%kim@samsung.com>
Message-ID: <000101cb1427$e88bfec0$b9a3fc40$%szyprowski@samsung.com>

Hello,

On Wednesday, June 23, 2010 9:51 AM Kukjin Kim wrote:

> Joonyoung Shim wrote:
> >
> > This patch v2 set is to support gpio interrupts of samsung s5p cpus, and
> > the GPIOlib gpio_to_irq goes to plat-samsung gpiolib, so patch v2 set
> > has four commit smaller than v1.
> >
> > Changes since v1:
> > - Add irq_base to s3c_gpio_chip struct
> > - GPIOlib gpio_to_irq() is implemented to samsung_gpiolib_to_irq() of
> >   plat-samsung gpiolib
> >
> > Joonyoung Shim (4):
> >       ARM: S5PV210: Add gpio interrupt support
> >       ARM: S5PC100: Use S5P gpio interrupts interface
> >       ARM: S5PC100: Move external interrupt defines
> >       ARM: SAMSUNG: Add GPIOlib gpio_to_irq
> >
> >  arch/arm/mach-s5pc100/Makefile                 |    2 +-
> >  arch/arm/mach-s5pc100/gpiolib.c                |   70 ++-----
> >  arch/arm/mach-s5pc100/include/mach/gpio.h      |    7 -
> >  arch/arm/mach-s5pc100/include/mach/irqs.h      |   18 ++-
> >  arch/arm/mach-s5pc100/include/mach/regs-gpio.h |    7 +
> >  arch/arm/mach-s5pc100/irq-gpio.c               |  266
> ------------------------
> >  arch/arm/mach-s5pv210/gpiolib.c                |   18 ++-
> >  arch/arm/mach-s5pv210/include/mach/irqs.h      |   16 ++-
> >  arch/arm/plat-s5p/Makefile                     |    2 +-
> >  arch/arm/plat-s5p/irq-gpioint.c                |  208 ++++++++++++++++++
> >  arch/arm/plat-samsung/gpiolib.c                |    9 +
> >  arch/arm/plat-samsung/include/plat/gpio-core.h |    6 +
> >  12 files changed, 295 insertions(+), 334 deletions(-)
> >  delete mode 100644 arch/arm/mach-s5pc100/irq-gpio.c
> >  create mode 100644 arch/arm/plat-s5p/irq-gpioint.c
> >
> 
> I am sure this patchset is working code, but Ben had made suggestion about
> 'sparse irq'...
> It is because there are too many gpio interrupts and having support of all
> of them is unnecessary as realistically only few of them maybe used.

Right. Ben suggested to create a pool for gpio interrupts (for example 16
interrupts) and selectively assign them in machine startup code to those
gpio pins that really need it.

The problem is that such solution is not yet ready and we really need the
gpio interrupt functionality for our boards (Aquila and GONI). 

Maybe these current patches could be merged now, and then, once the new
solution is prepared, the gpio interrupt support get converted to selective
registering?

S5PC100 already has gpio interrupt support.
 
> In fact in SMDK board there is no use of gpio in interrupt mode.

We are talking about support for Samsung S5PV210/S5PC110 SoCs in the Linux
mainline kernel, not the support for only SMDK boards. GPIO interrupts is
a feature of the SoC not a particular board.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center



From m.szyprowski at samsung.com  Fri Jun 25 01:52:07 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 25 Jun 2010 07:52:07 +0200
Subject: [PATCH 2/2] ARM: S5PV210: Add OneNAND device to the Aquila board
In-Reply-To: <1277445127-16025-1-git-send-email-m.szyprowski@samsung.com>
References: <1277445127-16025-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1277445127-16025-3-git-send-email-m.szyprowski@samsung.com>

From: Joonyoung Shim <jy0922.shim at samsung.com>

This patch is to support OneNAND device to the Aquila board.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
---
 arch/arm/mach-s5pv210/Kconfig       |    1 +
 arch/arm/mach-s5pv210/mach-aquila.c |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index d0432c6..7e2e1eb 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -51,6 +51,7 @@ config MACH_AQUILA
 	select ARCH_SPARSEMEM_ENABLE
 	select S5PV210_SETUP_FB_24BPP
 	select S3C_DEV_FB
+	select S5PC110_DEV_ONENAND
 	help
 	  Machine support for the Samsung Aquila target based on S5PC110 SoC
 
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 10bc76e..fb9dbb2 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -118,6 +118,7 @@ static struct s3c_fb_platdata aquila_lcd_pdata __initdata = {
 
 static struct platform_device *aquila_devices[] __initdata = {
 	&s3c_device_fb,
+	&s5pc110_device_onenand,
 };
 
 static void __init aquila_map_io(void)
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Fri Jun 25 01:52:06 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 25 Jun 2010 07:52:06 +0200
Subject: [PATCH 1/2] ARM: S5PV210: Add OneNAND device to the GONI board
In-Reply-To: <1277445127-16025-1-git-send-email-m.szyprowski@samsung.com>
References: <1277445127-16025-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <1277445127-16025-2-git-send-email-m.szyprowski@samsung.com>

From: Joonyoung Shim <jy0922.shim at samsung.com>

This patch is to support OneNAND device to the GONI board.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>

---
 arch/arm/mach-s5pv210/Kconfig     |    1 +
 arch/arm/mach-s5pv210/mach-goni.c |    1 +
 2 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0761eac..d0432c6 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -58,6 +58,7 @@ config MACH_GONI
 	bool "GONI"
 	select CPU_S5PV210
 	select ARCH_SPARSEMEM_ENABLE
+	select S5PC110_DEV_ONENAND
 	help
 	  Machine support for Samsung GONI board
 	  S5PC110(MCP) is one of package option of S5PV210
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 4863b13..bea812f 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -72,6 +72,7 @@ static struct s3c2410_uartcfg goni_uartcfgs[] __initdata = {
 };
 
 static struct platform_device *goni_devices[] __initdata = {
+	&s5pc110_device_onenand,
 };
 
 static void __init goni_map_io(void)
-- 
1.7.1.569.g6f426



From m.szyprowski at samsung.com  Fri Jun 25 01:52:05 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 25 Jun 2010 07:52:05 +0200
Subject: [PATCH] Add OneNAND devices to Aquila and GONI boards
Message-ID: <1277445127-16025-1-git-send-email-m.szyprowski@samsung.com>

Hello,

This short patch serie adds OneNAND devices to Aquila and GONI boards.
The patches were earlier posted to mailing list but it looks they were
lost, so I decided to resend them again.

The series contains the following patches:

[PATCH 1/2] ARM: S5PV210: Add OneNAND device to the GONI board
[PATCH 2/2] ARM: S5PV210: Add OneNAND device to the Aquila board

Best regards
-- 
Marek Szyprowski
Samsung Poland R&D Center


From m.szyprowski at samsung.com  Fri Jun 25 02:01:45 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Fri, 25 Jun 2010 08:01:45 +0200
Subject: clock updates
In-Reply-To: <20100623232422.GB16584@trinity.fluff.org>
References: <20100623232422.GB16584@trinity.fluff.org>
Message-ID: <000801cb142b$e6624420$b326cc60$%szyprowski@samsung.com>

Hello,

On Thursday, June 24, 2010 1:24 AM Ben Dooks wrote:

> I've been looking into updating the current samsung socs to use
> clkdev to lookup clocks. Currently we have a few issues that we
> could do with sorting before running the conversion to clkdev.
> 
> Firstly, the s5pc100 has some clocks that could be merged into
> common s5p, and a few which don't seem to match the others in
> the s5p series.
> 
> The i2s clocks which we should look at mergining are:
> 
> i2s_cdclk<0..2>
> pcm_cdclk<0..l>
> 
> also, clocks that have may need changing:
> 
> rotator	     => rot
> keyif	     => keypad
> 
> this isn't an complete list, still working on the changes.
> 
> The big changes with respect to drivers is that we will now be using
> clk_get(dev, NULL) to get the clock names, and any bus clocks such
> as the sdhci bus clock will be updated.
> 
> The intention with both the SDHCI and the SPI is to change the clock
> lookups to reflect the mux positions, so the sdhci clocks on the
> s3c64xx would be changed to use the following lookups:
> 
> hsmmc	=> mux0
> mmc_bus	=> mux2
> 48m	=> mux3

I like this idea, but I wonder how the drivers will be able to get/control
the additional peripheral clocks (like sclk_fimc and sclk_cam for fimc for
example)?

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center



From eric at eukrea.com  Fri Jun 25 02:52:40 2010
From: eric at eukrea.com (=?ISO-8859-1?Q?Eric_B=E9nard?=)
Date: Fri, 25 Jun 2010 08:52:40 +0200
Subject: 
In-Reply-To: <20100625051016.GA31164@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
	<4C236EC2.8090506@eukrea.com>
	<20100624175528.GA14838@pengutronix.de>
	<4C23B67C.7090207@eukrea.com>
	<20100625051016.GA31164@pengutronix.de>
Message-ID: <4C245238.7010501@eukrea.com>

Le 25/06/2010 07:10, Uwe Kleine-K?nig a ?crit :
> On Thu, Jun 24, 2010 at 09:48:12PM +0200, Eric B?nard wrote:
>> How do you manage to merge this simply in order to test it ?
>> I added your branch as a remote tree, then fetched it, then merged it :
>> is there any magic git sequence missing here that would help to reduce
>> the number of conflicts ?
> No, but these conflicts aren't that hard to resolve.  Check out my
> imx/for-2.6.36-merged branch.

most of them may not be hard to resolve but that creates more work to 
test the patches (and that create more work for Sascha to integrate the 
patches in its tree). Thanks for your merged branch, I'll test asap.

> BTW there are two warnings about 'otg_pdata' and 'usbh2_pdata' defined

should already be fixed in :
http://git.pengutronix.de/?p=imx/linux-2.6.git;a=commit;h=4ecca63bf70aec86745c4bb631ada8b15e02e855

> but not used with the config I tested.  And it would have been more
> consistent to name your machine source file mach-eukrea_cpuimx25.c.
>
OK so this would require the same renaming for cpuimx27 & 35 as actually 
its consitent between the 3 boards. Should I send a patch to rename them ?

Thanks,
Eric


From eric at eukrea.com  Fri Jun 25 02:54:48 2010
From: eric at eukrea.com (=?ISO-8859-1?Q?Eric_B=E9nard?=)
Date: Fri, 25 Jun 2010 08:54:48 +0200
Subject: [PATCH 1/2] net/fec: clean suspend/resume
In-Reply-To: <20100624.220548.02285361.davem@davemloft.net>
References: <1276853351-20790-1-git-send-email-eric@eukrea.com>
	<20100624.220548.02285361.davem@davemloft.net>
Message-ID: <4C2452B8.4030002@eukrea.com>

Le 25/06/2010 07:05, David Miller a ?crit :
> From: Eric B?nard<eric at eukrea.com>
> Date: Fri, 18 Jun 2010 11:29:10 +0200
>
>> Commit 59d4289b83b11379d867e2f7146904b19cc96404 converted fec to dev_pm_ops but
>> didn't update the suspend/resume functions thus leading to the following warning :
>> "initialization from incompatible pointer type" when CONFIG_PM is set.
>>
>> This patch also fixe a few indentation and style around CONFIG_PM area.
>>
>> Signed-off-by: Eric B?nard<eric at eukrea.com>
>
> So, where's patch 2/2?
>
Sorry, there is no patch 2/2 for netdev, the 2/2 was only for 
linux-arm-kernel : 
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/018387.html

Eric


From eric at eukrea.com  Fri Jun 25 03:06:55 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Fri, 25 Jun 2010 09:06:55 +0200
Subject: [PATCH] eukrea_mbimxsd: factorize motherboard support
Message-ID: <1277449615-3971-1-git-send-email-eric@eukrea.com>

This motherboard is used for both an i.MX25 and an i.MX35 machines
so we can have only one file to support it in plat-mxc.

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/mach-mx25/Kconfig                         |   14 -
 arch/arm/mach-mx25/Makefile                        |    1 -
 arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c      |  260 --------------------
 arch/arm/mach-mx25/mach-cpuimx25.c                 |    2 +-
 arch/arm/mach-mx3/Kconfig                          |   14 -
 arch/arm/mach-mx3/Makefile                         |    1 -
 arch/arm/mach-mx3/mach-cpuimx35.c                  |    2 +-
 arch/arm/plat-mxc/Kconfig                          |    8 +
 arch/arm/plat-mxc/Makefile                         |    1 +
 .../eukrea_mbimxsd-baseboard.c                     |  176 +++++++++++---
 .../plat-mxc/include/mach/board-eukrea_cpuimx35.h  |   40 ---
 ...d-eukrea_cpuimx25.h => board-eukrea_cpuimxsd.h} |   10 +-
 12 files changed, 158 insertions(+), 371 deletions(-)
 delete mode 100644 arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
 rename arch/arm/{mach-mx3 => plat-mxc}/eukrea_mbimxsd-baseboard.c (70%)
 delete mode 100644 arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx35.h
 rename arch/arm/plat-mxc/include/mach/{board-eukrea_cpuimx25.h => board-eukrea_cpuimxsd.h} (83%)

diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index 3a6668e..af982cd 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -9,18 +9,4 @@ config MACH_EUKREA_CPUIMX25
 	bool "Support Eukrea CPUIMX25 Platform"
 	select MXC_ULPI if USB_ULPI
 
-choice
-	prompt "Baseboard"
-	depends on MACH_EUKREA_CPUIMX25
-	default MACH_EUKREA_MBIMXSD_BASEBOARD
-
-config MACH_EUKREA_MBIMXSD_BASEBOARD
-	prompt "Eukrea MBIMXSD development board"
-	bool
-	help
-	  This adds board specific devices that can be found on Eukrea's
-	  MBIMXSD evaluation board.
-
-endchoice
-
 endif
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
index 83ab5d8..71302d4 100644
--- a/arch/arm/mach-mx25/Makefile
+++ b/arch/arm/mach-mx25/Makefile
@@ -2,4 +2,3 @@ obj-y				:= mm.o devices.o
 obj-$(CONFIG_ARCH_MX25)		+= clock.o
 obj-$(CONFIG_MACH_MX25_3DS)	+= mach-mx25pdk.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX25)		+= mach-cpuimx25.o
-obj-$(CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD)	+= eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
deleted file mode 100644
index e0f0dfd..0000000
--- a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * Copyright (C) 2010 Eric Benard - eric at eukrea.com
- *
- * Based on pcm970-baseboard.c which is :
- * Copyright (C) 2008 Juergen Beisert (kernel at pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <video/platform_lcd.h>
-
-#include <mach/board-eukrea_cpuimx25.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx25.h>
-#include <mach/common.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/mx25.h>
-#include <mach/imx-uart.h>
-#include <mach/imxfb.h>
-#include <mach/ssi.h>
-#include <mach/audmux.h>
-
-#include "devices.h"
-
-static struct pad_desc eukrea_mbimxsd_pads[] = {
-	/* LCD */
-	MX25_PAD_LD0__LD0,
-	MX25_PAD_LD1__LD1,
-	MX25_PAD_LD2__LD2,
-	MX25_PAD_LD3__LD3,
-	MX25_PAD_LD4__LD4,
-	MX25_PAD_LD5__LD5,
-	MX25_PAD_LD6__LD6,
-	MX25_PAD_LD7__LD7,
-	MX25_PAD_LD8__LD8,
-	MX25_PAD_LD9__LD9,
-	MX25_PAD_LD10__LD10,
-	MX25_PAD_LD11__LD11,
-	MX25_PAD_LD12__LD12,
-	MX25_PAD_LD13__LD13,
-	MX25_PAD_LD14__LD14,
-	MX25_PAD_LD15__LD15,
-	MX25_PAD_GPIO_E__LD16,
-	MX25_PAD_GPIO_F__LD17,
-	MX25_PAD_HSYNC__HSYNC,
-	MX25_PAD_VSYNC__VSYNC,
-	MX25_PAD_LSCLK__LSCLK,
-	MX25_PAD_OE_ACD__OE_ACD,
-	MX25_PAD_CONTRAST__CONTRAST,
-	/* LCD_PWR */
-	MX25_PAD_PWM__GPIO_1_26,
-	/* LED */
-	MX25_PAD_POWER_FAIL__GPIO_3_19,
-	/* SWITCH */
-	MX25_PAD_VSTBY_ACK__GPIO_3_18,
-	/* UART2 */
-	MX25_PAD_UART2_RTS__UART2_RTS,
-	MX25_PAD_UART2_CTS__UART2_CTS,
-	MX25_PAD_UART2_TXD__UART2_TXD,
-	MX25_PAD_UART2_RXD__UART2_RXD,
-	/* SD1 */
-	MX25_PAD_SD1_CMD__SD1_CMD,
-	MX25_PAD_SD1_CLK__SD1_CLK,
-	MX25_PAD_SD1_DATA0__SD1_DATA0,
-	MX25_PAD_SD1_DATA1__SD1_DATA1,
-	MX25_PAD_SD1_DATA2__SD1_DATA2,
-	MX25_PAD_SD1_DATA3__SD1_DATA3,
-	/* SD1 CD */
-	MX25_PAD_DE_B__GPIO_2_20,
-	/* I2S */
-	MX25_PAD_KPP_COL3__AUD5_TXFS,
-	MX25_PAD_KPP_COL2__AUD5_TXC,
-	MX25_PAD_KPP_COL1__AUD5_RXD,
-	MX25_PAD_KPP_COL0__AUD5_TXD,
-};
-
-#define GPIO_LED1	83
-#define GPIO_SWITCH1	82
-#define GPIO_SD1CD	52
-#define GPIO_LCDPWR	26
-
-static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
-	{
-		.mode	= {
-			.name		= "CMO-QVGA",
-			.refresh	= 60,
-			.xres		= 320,
-			.yres		= 240,
-			.pixclock	= KHZ2PICOS(6500),
-			.left_margin	= 30,
-			.right_margin	= 38,
-			.upper_margin	= 20,
-			.lower_margin	= 3,
-			.hsync_len	= 15,
-			.vsync_len	= 4,
-		},
-		.bpp	= 16,
-		.pcr	= 0xCAD08B80,
-	},
-};
-
-static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
-	.mode		= eukrea_mximxsd_modes,
-	.num_modes	= ARRAY_SIZE(eukrea_mximxsd_modes),
-	.pwmr		= 0x00A903FF,
-	.lscr1		= 0x00120300,
-	.dmacr		= 0x00040060,
-};
-
-static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
-				   unsigned int power)
-{
-	if (power)
-		gpio_direction_output(GPIO_LCDPWR, 1);
-	else
-		gpio_direction_output(GPIO_LCDPWR, 0);
-}
-
-static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
-	.set_power		= eukrea_mbimxsd_lcd_power_set,
-};
-
-static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
-	.name			= "platform-lcd",
-	.dev.platform_data	= &eukrea_mbimxsd_lcd_power_data,
-};
-
-static struct gpio_led eukrea_mbimxsd_leds[] = {
-	{
-		.name			= "led1",
-		.default_trigger	= "heartbeat",
-		.active_low		= 1,
-		.gpio			= GPIO_LED1,
-	},
-};
-
-static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
-	.leds		= eukrea_mbimxsd_leds,
-	.num_leds	= ARRAY_SIZE(eukrea_mbimxsd_leds),
-};
-
-static struct platform_device eukrea_mbimxsd_leds_gpio = {
-	.name	= "leds-gpio",
-	.id	= -1,
-	.dev	= {
-		.platform_data	= &eukrea_mbimxsd_led_info,
-	},
-};
-
-static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
-	{
-		.gpio		= GPIO_SWITCH1,
-		.code		= BTN_0,
-		.desc		= "BP1",
-		.active_low	= 1,
-		.wakeup		= 1,
-	},
-};
-
-static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
-	.buttons	= eukrea_mbimxsd_gpio_buttons,
-	.nbuttons	= ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
-};
-
-static struct platform_device eukrea_mbimxsd_button_device = {
-	.name		= "gpio-keys",
-	.id		= -1,
-	.num_resources	= 0,
-	.dev		= {
-		.platform_data	= &eukrea_mbimxsd_button_data,
-	}
-};
-
-static struct platform_device *platform_devices[] __initdata = {
-	&eukrea_mbimxsd_leds_gpio,
-	&eukrea_mbimxsd_button_device,
-	&eukrea_mbimxsd_lcd_powerdev,
-};
-
-static struct imxuart_platform_data uart_pdata = {
-	.flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
-	{
-		I2C_BOARD_INFO("tlv320aic23", 0x1a),
-	},
-};
-
-struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
-	.flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
-};
-
-/*
- * system init for baseboard usage. Will be called by cpuimx25 init.
- *
- * Add platform devices present on this baseboard and init
- * them from CPU side as far as required to use them later on
- */
-void __init eukrea_mbimxsd_baseboard_init(void)
-{
-	if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
-			ARRAY_SIZE(eukrea_mbimxsd_pads)))
-		printk(KERN_ERR "error setting mbimxsd pads !\n");
-
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
-	/* SSI unit master I2S codec connected to SSI_AUD5*/
-	mxc_audmux_v2_configure_port(0,
-			MXC_AUDMUX_V2_PTCR_SYN |
-			MXC_AUDMUX_V2_PTCR_TFSDIR |
-			MXC_AUDMUX_V2_PTCR_TFSEL(4) |
-			MXC_AUDMUX_V2_PTCR_TCLKDIR |
-			MXC_AUDMUX_V2_PTCR_TCSEL(4),
-			MXC_AUDMUX_V2_PDCR_RXDSEL(4)
-	);
-	mxc_audmux_v2_configure_port(4,
-			MXC_AUDMUX_V2_PTCR_SYN,
-			MXC_AUDMUX_V2_PDCR_RXDSEL(0)
-	);
-#endif
-
-	mxc_register_device(&mxc_uart_device1, &uart_pdata);
-	mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
-	mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
-
-	gpio_request(GPIO_LED1, "LED1");
-	gpio_direction_output(GPIO_LED1, 1);
-	gpio_free(GPIO_LED1);
-
-	gpio_request(GPIO_SWITCH1, "SWITCH1");
-	gpio_direction_input(GPIO_SWITCH1);
-	gpio_free(GPIO_SWITCH1);
-
-	gpio_request(GPIO_LCDPWR, "LCDPWR");
-	gpio_direction_output(GPIO_LCDPWR, 1);
-	gpio_free(GPIO_SWITCH1);
-
-	i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
-				ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
-
-	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-}
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-mx25/mach-cpuimx25.c
index 4796484..2e85d59 100644
--- a/arch/arm/mach-mx25/mach-cpuimx25.c
+++ b/arch/arm/mach-mx25/mach-cpuimx25.c
@@ -29,7 +29,7 @@
 #include <linux/usb/ulpi.h>
 #include <linux/fsl_devices.h>
 
-#include <mach/board-eukrea_cpuimx25.h>
+#include <mach/board-eukrea_cpuimxsd.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index b09e9a9..5bb9f6e 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -133,18 +133,4 @@ config MACH_EUKREA_CPUIMX35
 	  Include support for Eukrea CPUIMX35 platform. This includes
 	  specific configurations for the board and its peripherals.
 
-choice
-	prompt "Baseboard"
-	depends on MACH_EUKREA_CPUIMX35
-	default MACH_EUKREA_MBIMXSD_BASEBOARD
-
-config MACH_EUKREA_MBIMXSD_BASEBOARD
-	prompt "Eukrea MBIMXSD development board"
-	bool
-	help
-	  This adds board specific devices that can be found on Eukrea's
-	  MBIMXSD evaluation board.
-
-endchoice
-
 endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index ef68ff5..5a2525d 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -25,4 +25,3 @@ obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
 obj-$(CONFIG_MACH_MX35_3DS)	+= mach-mx35pdk.o
 obj-$(CONFIG_MACH_KZM_ARM11_01)	+= mach-kzm_arm11_01.o
 obj-$(CONFIG_MACH_EUKREA_CPUIMX35)	+= mach-cpuimx35.o
-obj-$(CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD)	+= eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 55caa5c..56e5bf0 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -37,7 +37,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
-#include <mach/board-eukrea_cpuimx35.h>
+#include <mach/board-eukrea_cpuimxsd.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
 #include <mach/imx-uart.h>
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 902ba9e..9df2706 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -82,6 +82,14 @@ config MXC_PWM
 	help
 	  Enable support for the i.MX PWM controller(s).
 
+config MACH_EUKREA_MBIMXSD_BASEBOARD
+	prompt "Eukrea MBIMXSD development board"
+	depends on MACH_EUKREA_CPUIMX25 || MACH_EUKREA_CPUIMX35
+	bool
+	help
+	  This adds board specific devices that can be found on Eukrea's
+	  MBIMXSD evaluation board.
+
 config MXC_ULPI
 	bool
 
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 895bc3c..2cc2d5c 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -21,3 +21,4 @@ ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
 endif
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD_BASEBOARD)	+= eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/plat-mxc/eukrea_mbimxsd-baseboard.c
similarity index 70%
rename from arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
rename to arch/arm/plat-mxc/eukrea_mbimxsd-baseboard.c
index 6785978..0c15843 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/plat-mxc/eukrea_mbimxsd-baseboard.c
@@ -36,48 +36,117 @@
 #include <asm/mach/time.h>
 #include <asm/mach/map.h>
 
-#include <mach/board-eukrea_cpuimx35.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
-#include <mach/imx-uart.h>
+#include <mach/board-eukrea_cpuimxsd.h>
+
+#if defined(CONFIG_MACH_EUKREA_CPUIMX25)
+#include <mach/iomux-mx25.h>
+#include <mach/mx25.h>
+#include <mach/imxfb.h>
+#include "../mach-mx25/devices.h"
+#endif
+
+#if defined(CONFIG_MACH_EUKREA_CPUIMX35)
 #include <mach/iomux-mx35.h>
 #include <mach/ipu.h>
 #include <mach/mx3fb.h>
-#include <mach/audmux.h>
+#include "../mach-mx3/devices.h"
+#endif
+
+#include <mach/imx-uart.h>
 #include <mach/ssi.h>
+#include <mach/audmux.h>
+
+#if defined(CONFIG_MACH_EUKREA_CPUIMX25)
+static struct pad_desc eukrea_mbimxsd_pads[] = {
+	/* LCD */
+	MX25_PAD_LD0__LD0,
+	MX25_PAD_LD1__LD1,
+	MX25_PAD_LD2__LD2,
+	MX25_PAD_LD3__LD3,
+	MX25_PAD_LD4__LD4,
+	MX25_PAD_LD5__LD5,
+	MX25_PAD_LD6__LD6,
+	MX25_PAD_LD7__LD7,
+	MX25_PAD_LD8__LD8,
+	MX25_PAD_LD9__LD9,
+	MX25_PAD_LD10__LD10,
+	MX25_PAD_LD11__LD11,
+	MX25_PAD_LD12__LD12,
+	MX25_PAD_LD13__LD13,
+	MX25_PAD_LD14__LD14,
+	MX25_PAD_LD15__LD15,
+	MX25_PAD_GPIO_E__LD16,
+	MX25_PAD_GPIO_F__LD17,
+	MX25_PAD_HSYNC__HSYNC,
+	MX25_PAD_VSYNC__VSYNC,
+	MX25_PAD_LSCLK__LSCLK,
+	MX25_PAD_OE_ACD__OE_ACD,
+	MX25_PAD_CONTRAST__CONTRAST,
+	/* LCD_PWR */
+	MX25_PAD_PWM__GPIO_1_26,
+	/* LED */
+	MX25_PAD_POWER_FAIL__GPIO_3_19,
+	/* SWITCH */
+	MX25_PAD_VSTBY_ACK__GPIO_3_18,
+	/* UART2 */
+	MX25_PAD_UART2_RTS__UART2_RTS,
+	MX25_PAD_UART2_CTS__UART2_CTS,
+	MX25_PAD_UART2_TXD__UART2_TXD,
+	MX25_PAD_UART2_RXD__UART2_RXD,
+	/* SD1 */
+	MX25_PAD_SD1_CMD__SD1_CMD,
+	MX25_PAD_SD1_CLK__SD1_CLK,
+	MX25_PAD_SD1_DATA0__SD1_DATA0,
+	MX25_PAD_SD1_DATA1__SD1_DATA1,
+	MX25_PAD_SD1_DATA2__SD1_DATA2,
+	MX25_PAD_SD1_DATA3__SD1_DATA3,
+	/* SD1 CD */
+	MX25_PAD_DE_B__GPIO_2_20,
+	/* I2S */
+	MX25_PAD_KPP_COL3__AUD5_TXFS,
+	MX25_PAD_KPP_COL2__AUD5_TXC,
+	MX25_PAD_KPP_COL1__AUD5_RXD,
+	MX25_PAD_KPP_COL0__AUD5_TXD,
+};
 
-#include "devices.h"
+#define GPIO_LED1	83
+#define GPIO_SWITCH1	82
+#define GPIO_SD1CD	52
+#define GPIO_LCDPWR	26
+#define SSI_PORT	4
 
-static const struct fb_videomode fb_modedb[] = {
+static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
 	{
-		.name		= "CMO_QVGA",
-		.refresh	= 60,
-		.xres		= 320,
-		.yres		= 240,
-		.pixclock	= KHZ2PICOS(6500),
-		.left_margin	= 68,
-		.right_margin	= 20,
-		.upper_margin	= 15,
-		.lower_margin	= 4,
-		.hsync_len	= 30,
-		.vsync_len	= 3,
-		.sync		= 0,
-		.vmode		= FB_VMODE_NONINTERLACED,
-		.flag		= 0,
+		.mode	= {
+			.name		= "CMO-QVGA",
+			.refresh	= 60,
+			.xres		= 320,
+			.yres		= 240,
+			.pixclock	= KHZ2PICOS(6500),
+			.left_margin	= 30,
+			.right_margin	= 38,
+			.upper_margin	= 20,
+			.lower_margin	= 3,
+			.hsync_len	= 15,
+			.vsync_len	= 4,
+		},
+		.bpp	= 16,
+		.pcr	= 0xCAD08B80,
 	},
 };
 
-static struct ipu_platform_data mx3_ipu_data = {
-	.irq_base = MXC_IPU_IRQ_START,
-};
-
-static struct mx3fb_platform_data mx3fb_pdata = {
-	.dma_dev	= &mx3_ipu.dev,
-	.name		= "CMO_QVGA",
-	.mode		= fb_modedb,
-	.num_modes	= ARRAY_SIZE(fb_modedb),
+static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = {
+	.mode		= eukrea_mximxsd_modes,
+	.num_modes	= ARRAY_SIZE(eukrea_mximxsd_modes),
+	.pwmr		= 0x00A903FF,
+	.lscr1		= 0x00120300,
+	.dmacr		= 0x00040060,
 };
+#endif
 
+#if defined(CONFIG_MACH_EUKREA_CPUIMX35)
 static struct pad_desc eukrea_mbimxsd_pads[] = {
 	/* LCD */
 	MX35_PAD_LD0__IPU_DISPB_DAT_0,
@@ -125,6 +194,38 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
 #define GPIO_LED1	(2 * 32 + 29)
 #define GPIO_SWITCH1	(2 * 32 + 25)
 #define GPIO_LCDPWR	(4)
+#define SSI_PORT	(3)
+
+static const struct fb_videomode fb_modedb[] = {
+	{
+		.name		= "CMO_QVGA",
+		.refresh	= 60,
+		.xres		= 320,
+		.yres		= 240,
+		.pixclock	= KHZ2PICOS(6500),
+		.left_margin	= 68,
+		.right_margin	= 20,
+		.upper_margin	= 15,
+		.lower_margin	= 4,
+		.hsync_len	= 30,
+		.vsync_len	= 3,
+		.sync		= 0,
+		.vmode		= FB_VMODE_NONINTERLACED,
+		.flag		= 0,
+	},
+};
+
+static struct ipu_platform_data mx3_ipu_data = {
+	.irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata = {
+	.dma_dev	= &mx3_ipu.dev,
+	.name		= "CMO_QVGA",
+	.mode		= fb_modedb,
+	.num_modes	= ARRAY_SIZE(fb_modedb),
+};
+#endif
 
 static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
 				   unsigned int power)
@@ -211,7 +312,7 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata = {
 };
 
 /*
- * system init for baseboard usage. Will be called by cpuimx35 init.
+ * system init for baseboard usage. Will be called by cpuimxX5 init.
  *
  * Add platform devices present on this baseboard and init
  * them from CPU side as far as required to use them later on
@@ -223,24 +324,31 @@ void __init eukrea_mbimxsd_baseboard_init(void)
 		printk(KERN_ERR "error setting mbimxsd pads !\n");
 
 #if defined(CONFIG_SND_SOC_EUKREA_TLV320)
-	/* SSI unit master I2S codec connected to SSI_AUD4 */
+	/* SSI unit master I2S codec connected to SSI_AUD */
 	mxc_audmux_v2_configure_port(0,
 			MXC_AUDMUX_V2_PTCR_SYN |
 			MXC_AUDMUX_V2_PTCR_TFSDIR |
-			MXC_AUDMUX_V2_PTCR_TFSEL(3) |
+			MXC_AUDMUX_V2_PTCR_TFSEL(SSI_PORT) |
 			MXC_AUDMUX_V2_PTCR_TCLKDIR |
-			MXC_AUDMUX_V2_PTCR_TCSEL(3),
-			MXC_AUDMUX_V2_PDCR_RXDSEL(3)
+			MXC_AUDMUX_V2_PTCR_TCSEL(SSI_PORT),
+			MXC_AUDMUX_V2_PDCR_RXDSEL(SSI_PORT)
 	);
-	mxc_audmux_v2_configure_port(3,
+	mxc_audmux_v2_configure_port(SSI_PORT,
 			MXC_AUDMUX_V2_PTCR_SYN,
 			MXC_AUDMUX_V2_PDCR_RXDSEL(0)
 	);
 #endif
 
 	mxc_register_device(&mxc_uart_device1, &uart_pdata);
+
+#if defined(CONFIG_MACH_EUKREA_CPUIMX25)
+	mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata);
+#endif
+
+#if defined(CONFIG_MACH_EUKREA_CPUIMX35)
 	mxc_register_device(&mx3_ipu, &mx3_ipu_data);
 	mxc_register_device(&mx3_fb, &mx3fb_pdata);
+#endif
 
 	mxc_register_device(&imx_ssi_device0, &eukrea_mbimxsd_ssi_pdata);
 
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx35.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx35.h
deleted file mode 100644
index 116eee7..0000000
--- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx35.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (C) 2010 Eric Benard - eric at eukrea.com
- *
- * Based on board-pcm038.h which is :
- * Copyright (C) 2008 Juergen Beisert (kernel at pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX35_H__
-#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX35_H__
-
-#ifndef __ASSEMBLY__
-/*
- * This CPU module needs a baseboard to work. After basic initializing
- * its own devices, it calls baseboard's init function.
- * TODO: Add your own baseboard init function and call it from
- * inside eukrea_cpuimx25_init().
- *
- * This example here is for the development board. Refer
- * eukrea_mbimx25-baseboard.c
- */
-
-extern void eukrea_mbimxsd_baseboard_init(void);
-
-#endif
-
-#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX35_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx25.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimxsd.h
similarity index 83%
rename from arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx25.h
rename to arch/arm/plat-mxc/include/mach/board-eukrea_cpuimxsd.h
index 5c9901e..96789b1 100644
--- a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx25.h
+++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimxsd.h
@@ -19,22 +19,22 @@
  * MA 02110-1301, USA.
  */
 
-#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX25_H__
-#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX25_H__
+#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMXSD_H__
+#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMXSD_H__
 
 #ifndef __ASSEMBLY__
 /*
  * This CPU module needs a baseboard to work. After basic initializing
  * its own devices, it calls baseboard's init function.
  * TODO: Add your own baseboard init function and call it from
- * inside eukrea_cpuimx25_init().
+ * inside eukrea_cpuimx25_init() or eukrea_cpuimx35_init().
  *
  * This example here is for the development board. Refer
- * eukrea_mbimx25-baseboard.c
+ * eukrea_mbimxsd-baseboard.c
  */
 
 extern void eukrea_mbimxsd_baseboard_init(void);
 
 #endif
 
-#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX25_H__ */
+#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMXSD_H__ */
-- 
1.6.3.3



From schindele at nentec.de  Fri Jun 25 03:11:28 2010
From: schindele at nentec.de (Juergen Schindele)
Date: Fri, 25 Jun 2010 09:11:28 +0200
Subject: strange segfaults with CompactFlash in "true-ide" mode on PXA270
In-Reply-To: <19490.10015.10027.750374@ipc1.ka-ro>
References: <201006231706.33182.schindele@nentec.de>
	<19490.10015.10027.750374@ipc1.ka-ro>
Message-ID: <201006250911.30277.schindele@nentec.de>

Am Mittwoch, 23. Juni 2010 schrieb Lothar Wa?mann:
> Hi,
> 
> > we have a strange problem when booting from a Compact Flash card
> > as root-device. In one of 10 cases while booting an application from
> > root-filesystem dies with "Segmentation fault" without a visible error.
> > After booting the same application runs hundred times without error.
> > (we're talking about standard appl. like chat, pppd, hwclock and so on)
> > 
> > For debugging purposes we put printk's in kernels IDE driver 
> > and the problem disappeared. But replacing the printk by a usleep
> > or so (which is not a solution !) brings the problem back.
> > It seems that the application received faulty data from CF.
> > But how and why ?????????????????????????????
> > 
> > We tested with a custom PXA270 board with a CompactFlash in 
> > "true ide" on processor bus driven by "generic ide / pata_platform"
> > driver from linux-2.6.27.x.
> > (by the way linux-2.6.20.x showed the same problem).
> > 
> > Any ideas, hints, experiences, patches are very welcome :-)
> > --------------------------------------------------------------
> I guess that is the old cache problem that apparently was never really
> fixed:
> http://marc.info/?t=108537828400002&r=1&w=2
Hello
this hint was very helpful for understanding the problem.
In the mail from Russell King at 
<http://marc.info/?l=linux-arm-kernel&m=108611676807909&w=2>
he said : .... the rule is if the CPU writes to a page cache page,
it must call flush_dcache_page afterwards to ensure cache coherency with user space".

so i made the following patch in drivers/ide/ide-taskfile.c
in the function ide_pio_sector() where blocks from disk are read
into a cached page to apply the rule from Russell. 
===================================================================
--- ide-taskfile.c
+++ ide-taskfile.c.new
@@ -278,6 +278,7 @@
                hwif->tp_ops->input_data(drive, rq, buf, SECTOR_SIZE);

        kunmap_atomic(buf, KM_BIO_SRC_IRQ);
+       flush_dcache_page(page);
 #ifdef CONFIG_HIGHMEM
        local_irq_restore(flags);
 #endif

And from there on the problem disappeared :-))
What are you think about ???
Isn't this missing for years in IDE PIO driver ???
--------------------------------------------------------------
J?rgen Schindele  
Software-Entwicklung

PSI NENTEC GmbH
Greschbachstr. 12
76229 Karlsruhe
Deutschland
Telefon: +49 721 94249-51
Telefax: +49 721 94249-10
E-Mail:  schindele at nentec.de
WEB:     www.nentec.de
 
Gesch?ftsf?hrung: Klaus Becker, Roland Knapp
Sitz der Gesellschaft: Karlsruhe
Handelsregister: Amtsgericht Mannheim HRB 107658
--------------------------------------------------------------


From u.kleine-koenig at pengutronix.de  Fri Jun 25 03:17:51 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Fri, 25 Jun 2010 09:17:51 +0200
Subject: 
In-Reply-To: <4C245238.7010501@eukrea.com>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
	<4C236EC2.8090506@eukrea.com>
	<20100624175528.GA14838@pengutronix.de>
	<4C23B67C.7090207@eukrea.com>
	<20100625051016.GA31164@pengutronix.de>
	<4C245238.7010501@eukrea.com>
Message-ID: <20100625071751.GB31164@pengutronix.de>

On Fri, Jun 25, 2010 at 08:52:40AM +0200, Eric B?nard wrote:
> Le 25/06/2010 07:10, Uwe Kleine-K?nig a ?crit :
>> On Thu, Jun 24, 2010 at 09:48:12PM +0200, Eric B?nard wrote:
>>> How do you manage to merge this simply in order to test it ?
>>> I added your branch as a remote tree, then fetched it, then merged it :
>>> is there any magic git sequence missing here that would help to reduce
>>> the number of conflicts ?
>> No, but these conflicts aren't that hard to resolve.  Check out my
>> imx/for-2.6.36-merged branch.
I'm currently fixing mx3, I missed that there appeared a new machine,
too.  I give you a ping via PM when I'm done.

> most of them may not be hard to resolve but that creates more work to  
> test the patches (and that create more work for Sascha to integrate the  
> patches in its tree). Thanks for your merged branch, I'll test asap.
rebasing creates more work for me, and if Sascha pulls my merge he has
no problems.

>> BTW there are two warnings about 'otg_pdata' and 'usbh2_pdata' defined
>
> should already be fixed in :
> http://git.pengutronix.de/?p=imx/linux-2.6.git;a=commit;h=4ecca63bf70aec86745c4bb631ada8b15e02e855
>
>> but not used with the config I tested.  And it would have been more
>> consistent to name your machine source file mach-eukrea_cpuimx25.c.
>>
> OK so this would require the same renaming for cpuimx27 & 35 as actually  
> its consitent between the 3 boards. Should I send a patch to rename them 
> ?
If you don't, then I will do :-)  I would recommend to wait until Sascha
merged though.

While testing I found another problem.  There are two definitions of
MACH_EUKREA_MBIMXSD_BASEBOARD that conflict.  For me
MACH_EUKREA_MBIMXSD_BASEBOARD doesn't appear in .config if I select
MACH_EUKREA_CPUIMX25.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From igawa at mxs.nes.nec.co.jp  Fri Jun 25 03:05:44 2010
From: igawa at mxs.nes.nec.co.jp (Masayuki Igawa)
Date: Fri, 25 Jun 2010 16:05:44 +0900 (JST)
Subject: [PATCH 3/3] add ARM crashdump support
In-Reply-To: <20100625.083133.77342472.igawa@mxs.nes.nec.co.jp>
References: <20100624163356.dbb849bc.igawa@mxs.nes.nec.co.jp>
	<20100624081915.GF29920@esdhcp04058.research.nokia.com>
	<20100625.083133.77342472.igawa@mxs.nes.nec.co.jp>
Message-ID: <20100625.160544.125902258.igawa@mxs.nes.nec.co.jp>

Hi,

From: Masayuki Igawa <igawa at mxs.nes.nec.co.jp>
Subject: Re: [PATCH 3/3] add ARM crashdump support
Date: Fri, 25 Jun 2010 08:31:33 +0900 (JST)
> From: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
> Date: Thu, 24 Jun 2010 11:19:15 +0300
>> On Thu, Jun 24, 2010 at 09:33:56AM +0200, ext Masayuki Igawa wrote:
>>> Hi, Mika.
>> 
>> (...)
> 
>>> How about is this?
>>> ====
>>> +unsigned long long
>>> +vaddr_to_paddr_arm(unsigned long vaddr)
>>> +{
>>> +	unsigned long long paddr = vaddr_to_paddr_general(vaddr);
>>> +
>>> +	if (paddr != NOT_PADDR)
>>> +		return paddr;
>>> ====
>> 
>> Yeah, looks OK to me.
>> 
>> Do you want me to send a revisited version of the patches or do you change that
>> yourself?
> 
> I'll change that myself.
> 
>> 
>>> BTW, I'm testing these patches for x86/x86_64 arch now.
>>> I'll merge these patches after my testing.
>> 
>> Cool, thanks.

I've finished my tests(x86/x86_64). No problems were found.
So I've merged and pushed these patches.

Thanks,
-- Masayuki Igawa


>> 
>>> But I cannot test for ARM because have no test machines of ARM.
>> 
>> Well I can do the testing for ARM (unless someone else, who is using ARM kdump
>> currently, wants to test this). If the above is the only change it should still
>> work.
> 
> OK. I'll merge and push these patches (including this change).
> And I'd like you to do the testing for ARM after that.



From david-b at pacbell.net  Fri Jun 25 03:19:41 2010
From: david-b at pacbell.net (David Brownell)
Date: Fri, 25 Jun 2010 00:19:41 -0700 (PDT)
Subject: [RFC PATCH] Rework gpio cansleep (was Re: gpiolib and sleeping
	gpios)
In-Reply-To: <4C22A275.3030102@bluewatersys.com>
Message-ID: <683567.34621.qm@web180314.mail.gq1.yahoo.com>



--- On Wed, 6/23/10, Ryan Mallon <ryan at bluewatersys.com> wrote:

> >> In the current code, if a driver ever calls
> gpio_(set/get)_value on a
> >> gpio then you cannot pass a sleeping gpio to that
> driver. The request
> >> will succeed,

No it won't.  Recall that those bit accessor
functions don't return success or failure!!

I'll be submitting a patch soonish, which is
a variant of Jani's patch to make the runtime
warnings trigger more consistently in the
face of such programming errors.






From eric at eukrea.com  Fri Jun 25 03:23:49 2010
From: eric at eukrea.com (=?ISO-8859-1?Q?Eric_B=E9nard?=)
Date: Fri, 25 Jun 2010 09:23:49 +0200
Subject: 
In-Reply-To: <20100625071751.GB31164@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
	<4C236EC2.8090506@eukrea.com>
	<20100624175528.GA14838@pengutronix.de>
	<4C23B67C.7090207@eukrea.com>
	<20100625051016.GA31164@pengutronix.de>
	<4C245238.7010501@eukrea.com>
	<20100625071751.GB31164@pengutronix.de>
Message-ID: <4C245985.6040703@eukrea.com>

Le 25/06/2010 09:17, Uwe Kleine-K?nig a ?crit :
>>> but not used with the config I tested.  And it would have been more
>>> consistent to name your machine source file mach-eukrea_cpuimx25.c.
>>>
>> OK so this would require the same renaming for cpuimx27&  35 as actually
>> its consitent between the 3 boards. Should I send a patch to rename them
>> ?
> If you don't, then I will do :-)  I would recommend to wait until Sascha
> merged though.
>
OK will do.

> While testing I found another problem.  There are two definitions of
> MACH_EUKREA_MBIMXSD_BASEBOARD that conflict.  For me
> MACH_EUKREA_MBIMXSD_BASEBOARD doesn't appear in .config if I select
> MACH_EUKREA_CPUIMX25.
>
Yes I saw this after tewting Sascha's tree as I was initialy working on 
different branches. I would have expected Kconfig to not care about the 
one of the unselected architecture but that not the case.
Please see the patch I just sent to merge the baseboard support in one file.

Eric


From byang1 at marvell.com  Fri Jun 25 03:35:41 2010
From: byang1 at marvell.com (Bin Yang)
Date: Fri, 25 Jun 2010 00:35:41 -0700
Subject: kprobe bug. 
In-Reply-To: <20100623195456.GC25070@n2100.arm.linux.org.uk>
Message-ID: <AAD1C6EB06EE3649B35B7E026785068D14FCB58138@SC-VEXCH2.marvell.com>

Hi Russell,

	Thanks in advance for your kind to review my question. 
	I met a kprobe bug while I used it to debug my driver. 
	Here is the scenario:
	I add a probe at function xxx(). And the assembly code of xxx() is as following,
=====================
	c035ee48 <xxx >:
c035ee48:       e59f3008        ldr     r3, [pc, #8]    ; c035ee58              <xxx+0x10>
c035ee4c:       e3a02001        mov     r2, #1  ; 0x1
c035ee50:       e5032fff        str     r2, [r3, #-4095]
c035ee54:       e12fff1e        bx      lr
c035ee58:       fe03dfff        .word   0xfe03dfff 
=====================
	The ldr emulate always load e12fff1e to r3 register. 
	After debugging, I found the pc register should be 8 after current instruction. So we should set pc to pc+8 before instruction emulation and set it back to the next instruction after singe step.
	Here is my patch: 
=======================
diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c
index 60c62c3..6e2567e 100644
--- a/arch/arm/kernel/kprobes.c
+++ b/arch/arm/kernel/kprobes.c
@@ -132,8 +132,9 @@ static void __kprobes set_current_kprobe(struct kprobe *p)
 static void __kprobes singlestep(struct kprobe *p, struct pt_regs *regs,
 				 struct kprobe_ctlblk *kcb)
 {
-	regs->ARM_pc += 4;
+	regs->ARM_pc += 8;
 	p->ainsn.insn_handler(p, regs);
+	regs->ARM_pc -= 4;
 }
 
 /*
========================

	 

Regards,
Bin








From eric.y.miao at gmail.com  Fri Jun 25 03:44:27 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 25 Jun 2010 15:44:27 +0800
Subject: [PATCH 0/4] Allow absence of mach/io.h
Message-ID: <1277451871-15319-1-git-send-email-eric.y.miao@gmail.com>

Introduce USE_DEFAULT_IO_H to allow default definitions of

  IO_SPACE_LIMIT
  __mem_pci()
  __io()

And most SoC can actually use these default definitions without the
need to have a specific mach/io.h. PXA and MMP are two examples in
the last patch, where the files are removed.



From eric.y.miao at gmail.com  Fri Jun 25 03:44:28 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 25 Jun 2010 15:44:28 +0800
Subject: [PATCH 1/4] [ARM] Remove useless __mem_isa() definitions
In-Reply-To: <1277451871-15319-1-git-send-email-eric.y.miao@gmail.com>
References: <1277451871-15319-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1277451871-15319-2-git-send-email-eric.y.miao@gmail.com>

From: Eric Miao <eric.miao at canonical.com>

__mem_isa() is used nowhere, keeping it there will just add confusion.

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/mach-davinci/include/mach/io.h  |    1 -
 arch/arm/mach-iop13xx/include/mach/io.h  |    1 -
 arch/arm/mach-ns9xxx/include/mach/io.h   |    1 -
 arch/arm/plat-stmp3xxx/include/mach/io.h |    1 -
 4 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/io.h b/arch/arm/mach-davinci/include/mach/io.h
index 62b0a90..84b4b17 100644
--- a/arch/arm/mach-davinci/include/mach/io.h
+++ b/arch/arm/mach-davinci/include/mach/io.h
@@ -19,7 +19,6 @@
  */
 #define __io(a)			__typesafe_io(a)
 #define __mem_pci(a)		(a)
-#define __mem_isa(a)		(a)
 
 #ifndef __ASSEMBLER__
 #define __arch_ioremap(p, s, t)	davinci_ioremap(p, s, t)
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
index a6e0f9e..ccf69ed 100644
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ b/arch/arm/mach-iop13xx/include/mach/io.h
@@ -23,7 +23,6 @@
 
 #define __io(a) __iop13xx_io(a)
 #define __mem_pci(a) (a)
-#define __mem_isa(a) (a)
 
 extern void __iomem * __iop13xx_io(unsigned long io_addr);
 extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h
index f08451d..c261d7b 100644
--- a/arch/arm/mach-ns9xxx/include/mach/io.h
+++ b/arch/arm/mach-ns9xxx/include/mach/io.h
@@ -15,6 +15,5 @@
 
 #define __io(a)		__typesafe_io(a)
 #define __mem_pci(a)    (a)
-#define __mem_isa(a)    (IO_BASE + (a))
 
 #endif /* ifndef __ASM_ARCH_IO_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h
index d08b1b7..7aef4d9 100644
--- a/arch/arm/plat-stmp3xxx/include/mach/io.h
+++ b/arch/arm/plat-stmp3xxx/include/mach/io.h
@@ -20,6 +20,5 @@
 
 #define __io(a) 	__typesafe_io(a)
 #define __mem_pci(a)	(a)
-#define __mem_isa(a)	(a)
 
 #endif
-- 
1.7.1



From eric.y.miao at gmail.com  Fri Jun 25 03:44:29 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 25 Jun 2010 15:44:29 +0800
Subject: [PATCH 2/4] [ARM] shmobile: change __io() definition to use
	__typesafe_io()
In-Reply-To: <1277451871-15319-1-git-send-email-eric.y.miao@gmail.com>
References: <1277451871-15319-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1277451871-15319-3-git-send-email-eric.y.miao@gmail.com>

From: Eric Miao <eric.miao at canonical.com>

Cc: Magnus Damm <magnus.damm at gmail.com>
Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/mach-shmobile/include/mach/io.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-shmobile/include/mach/io.h b/arch/arm/mach-shmobile/include/mach/io.h
index 7339fe4..df793df 100644
--- a/arch/arm/mach-shmobile/include/mach/io.h
+++ b/arch/arm/mach-shmobile/include/mach/io.h
@@ -3,7 +3,7 @@
 
 #define IO_SPACE_LIMIT		0xffffffff
 
-#define __io(a)			((void __iomem *)(a))
+#define __io(a)			__typesafe_io(a)
 #define __mem_pci(a)		(a)
 
 #endif /* __ASM_MACH_IO_H */
-- 
1.7.1



From eric.y.miao at gmail.com  Fri Jun 25 03:44:30 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 25 Jun 2010 15:44:30 +0800
Subject: [PATCH 3/4] [ARM] Introduce USE_DEFAULT_IO_H to use default
	definitions in asm/io.h
In-Reply-To: <1277451871-15319-1-git-send-email-eric.y.miao@gmail.com>
References: <1277451871-15319-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1277451871-15319-4-git-send-email-eric.y.miao@gmail.com>

From: Eric Miao <eric.miao at canonical.com>

For those machines that can just use the default definitions in asm/io.h,
there is no need to have a machine specific mach/io.h. Introduce an config
option for them.

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/Kconfig          |    3 +++
 arch/arm/include/asm/io.h |    6 ++++++
 2 files changed, 9 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..46c00a1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -189,6 +189,9 @@ config VECTORS_BASE
 	help
 	  The base address of exception vectors.
 
+config USE_DEFAULT_IO_H
+	def_bool n
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index c980156..179d317 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -97,7 +97,13 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 /*
  * Now, pick up the machine-defined IO definitions
  */
+#ifndef CONFIG_USE_DEFAULT_IO_H
 #include <mach/io.h>
+#else
+#define IO_SPACE_LIMIT	0xffffffff
+#define __io(a)		__typesafe_io(a)
+#define __mem_pci(a)	(a)
+#endif
 
 /*
  *  IO port access primitives
-- 
1.7.1



From eric.y.miao at gmail.com  Fri Jun 25 03:44:31 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 25 Jun 2010 15:44:31 +0800
Subject: [PATCH 4/4] [ARM] Make pxa and mmp to USE_DEFAULT_IO_H
In-Reply-To: <1277451871-15319-1-git-send-email-eric.y.miao@gmail.com>
References: <1277451871-15319-1-git-send-email-eric.y.miao@gmail.com>
Message-ID: <1277451871-15319-5-git-send-email-eric.y.miao@gmail.com>

From: Eric Miao <eric.miao at canonical.com>

Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/Kconfig                    |    2 ++
 arch/arm/mach-mmp/include/mach/io.h |   21 ---------------------
 arch/arm/mach-pxa/include/mach/io.h |   18 ------------------
 3 files changed, 2 insertions(+), 39 deletions(-)
 delete mode 100644 arch/arm/mach-mmp/include/mach/io.h
 delete mode 100644 arch/arm/mach-pxa/include/mach/io.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 46c00a1..f2da68a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -517,6 +517,7 @@ config ARCH_MMP
 	select GENERIC_CLOCKEVENTS
 	select TICK_ONESHOT
 	select PLAT_PXA
+	select USE_DEFAULT_IO_H
 	help
 	  Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
 
@@ -582,6 +583,7 @@ config ARCH_PXA
 	select GENERIC_CLOCKEVENTS
 	select TICK_ONESHOT
 	select PLAT_PXA
+	select USE_DEFAULT_IO_H
 	help
 	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
diff --git a/arch/arm/mach-mmp/include/mach/io.h b/arch/arm/mach-mmp/include/mach/io.h
deleted file mode 100644
index e7adf3d..0000000
--- a/arch/arm/mach-mmp/include/mach/io.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * linux/arch/arm/mach-mmp/include/mach/io.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_MACH_IO_H
-#define __ASM_MACH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-pxa/include/mach/io.h b/arch/arm/mach-pxa/include/mach/io.h
deleted file mode 100644
index 262691f..0000000
--- a/arch/arm/mach-pxa/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * arch/arm/mach-pxa/include/mach/io.h
- *
- * Copied from asm/arch/sa1100/io.h
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/*
- * We don't actually have real ISA nor PCI buses, but there is so many
- * drivers out there that might just work if we fake them...
- */
-#define __io(a)		__typesafe_io(a)
-#define __mem_pci(a)	(a)
-
-#endif
-- 
1.7.1



From eric at eukrea.com  Fri Jun 25 03:53:20 2010
From: eric at eukrea.com (=?utf-8?q?Eric=20B=C3=A9nard?=)
Date: Fri, 25 Jun 2010 09:53:20 +0200
Subject: [PATCH] imxfb: add the possibility to control PWMR
Message-ID: <1277452400-6032-1-git-send-email-eric@eukrea.com>

this adds the possibility to enable/disable the backlight through
the PWMR register, as offered in mx3fb.

Signed-off-by: Eric B?nard <eric at eukrea.com>
---
 arch/arm/plat-mxc/include/mach/imxfb.h |    1 +
 drivers/video/imxfb.c                  |   14 ++++++++++++++
 2 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
index 5263506..3c24778 100644
--- a/arch/arm/plat-mxc/include/mach/imxfb.h
+++ b/arch/arm/plat-mxc/include/mach/imxfb.h
@@ -67,6 +67,7 @@ struct imx_fb_platform_data {
 	u_int		pwmr;
 	u_int		lscr1;
 	u_int		dmacr;
+	u_int		backlight_level;
 
 	u_char * fixed_screen_cpu;
 	dma_addr_t fixed_screen_dma;
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index b4b6dec..9451200 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -169,6 +169,7 @@ struct imxfb_info {
 	u_int			pwmr;
 	u_int			lscr1;
 	u_int			dmacr;
+	u_int			backlight_level;
 	u_int			cmap_inverse:1,
 				cmap_static:1,
 				unused:30;
@@ -302,6 +303,14 @@ static int imxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 	return ret;
 }
 
+static void imx_fb_set_brightness(struct imxfb_info *fbi, uint8_t value)
+{
+	pr_debug("%s: value = %d\n", __func__, value);
+	/* This might be board-specific */
+	writel((fbi->pwmr & ~0xFF) | value, fbi->regs + LCDC_PWMR);
+	return;
+}
+
 static const struct imx_fb_videomode *imxfb_find_mode(struct imxfb_info *fbi)
 {
 	struct imx_fb_videomode *m;
@@ -470,12 +479,16 @@ static void imxfb_enable_controller(struct imxfb_info *fbi)
 		fbi->backlight_power(1);
 	if (fbi->lcd_power)
 		fbi->lcd_power(1);
+	if (fbi->backlight_level)
+		imx_fb_set_brightness(fbi, fbi->backlight_level);
 }
 
 static void imxfb_disable_controller(struct imxfb_info *fbi)
 {
 	pr_debug("Disabling LCD controller\n");
 
+	if (fbi->backlight_level)
+		imx_fb_set_brightness(fbi, 0);
 	if (fbi->backlight_power)
 		fbi->backlight_power(0);
 	if (fbi->lcd_power)
@@ -660,6 +673,7 @@ static int __init imxfb_init_fbinfo(struct platform_device *pdev)
 	fbi->pwmr			= pdata->pwmr;
 	fbi->lcd_power			= pdata->lcd_power;
 	fbi->backlight_power		= pdata->backlight_power;
+	fbi->backlight_level		= pdata->backlight_level;
 
 	for (i = 0, m = &pdata->mode[0]; i < pdata->num_modes; i++, m++)
 		info->fix.smem_len = max_t(size_t, info->fix.smem_len,
-- 
1.6.3.3



From magnus.damm at gmail.com  Fri Jun 25 04:24:45 2010
From: magnus.damm at gmail.com (Magnus Damm)
Date: Fri, 25 Jun 2010 17:24:45 +0900
Subject: [PATCH 2/4] [ARM] shmobile: change __io() definition to use 
	__typesafe_io()
In-Reply-To: <1277451871-15319-3-git-send-email-eric.y.miao@gmail.com>
References: <1277451871-15319-1-git-send-email-eric.y.miao@gmail.com>
	<1277451871-15319-3-git-send-email-eric.y.miao@gmail.com>
Message-ID: <AANLkTimcTYIX2XnZlEFjp5pHZRl5rT_b_Ik-RNjIVfHG@mail.gmail.com>

On Fri, Jun 25, 2010 at 4:44 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
> From: Eric Miao <eric.miao at canonical.com>
>
> Cc: Magnus Damm <magnus.damm at gmail.com>
> Signed-off-by: Eric Miao <eric.miao at canonical.com>
> ---

Acked-by: Magnus Damm <damm at opensource.se>

FYI, Paul Mundt handles the genesis-2.6 git tree, so you probably also
want to CC him and/or the linux-sh list.

Thank you!

/ magnus


From eric.y.miao at gmail.com  Fri Jun 25 04:29:09 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 25 Jun 2010 16:29:09 +0800
Subject: [PATCH 2/4] [ARM] shmobile: change __io() definition to use 
	__typesafe_io()
In-Reply-To: <AANLkTimcTYIX2XnZlEFjp5pHZRl5rT_b_Ik-RNjIVfHG@mail.gmail.com>
References: <1277451871-15319-1-git-send-email-eric.y.miao@gmail.com> 
	<1277451871-15319-3-git-send-email-eric.y.miao@gmail.com> 
	<AANLkTimcTYIX2XnZlEFjp5pHZRl5rT_b_Ik-RNjIVfHG@mail.gmail.com>
Message-ID: <AANLkTinuMOdKyqJidYsqPRN1vY0hkSxgsmC5Hhpk7baa@mail.gmail.com>

On Fri, Jun 25, 2010 at 4:24 PM, Magnus Damm <magnus.damm at gmail.com> wrote:
> On Fri, Jun 25, 2010 at 4:44 PM, Eric Miao <eric.y.miao at gmail.com> wrote:
>> From: Eric Miao <eric.miao at canonical.com>
>>
>> Cc: Magnus Damm <magnus.damm at gmail.com>
>> Signed-off-by: Eric Miao <eric.miao at canonical.com>
>> ---
>
> Acked-by: Magnus Damm <damm at opensource.se>
>
> FYI, Paul Mundt handles the genesis-2.6 git tree, so you probably also
> want to CC him and/or the linux-sh list.
>

Cc'ed. Thanks.


From dmitry.torokhov at gmail.com  Fri Jun 25 04:30:19 2010
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Fri, 25 Jun 2010 01:30:19 -0700
Subject: [PATCH v5 3/3] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <1277101605-2435-3-git-send-email-jy0922.shim@samsung.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<1277101605-2435-3-git-send-email-jy0922.shim@samsung.com>
Message-ID: <20100625083019.GD8546@core.coreip.homeip.net>

Hi Joonyoung,

On Mon, Jun 21, 2010 at 03:26:45PM +0900, Joonyoung Shim wrote:
> This patch adds support for keypad driver running on Samsung cpus. This
> driver is tested on GONI and Aquila board using S5PC110 cpu.
> 
> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>

Following my conversation with Thomas Gleixner reagrding "long playing"
threaded interrupt handlers I tried to convert your driver to use this
concept. The idea is to keep polling within IRQ thread context instead
of using additional work/timer structures to simplify code and ensure
race-free shutdown/unbind.

I think it was based on v4 of your driver and I'd appreciate if you could
give it a try.

Thank you.

-- 
Dmitry



Input: samsung-keypad - updates

From: Dmitry Torokhov <dmitry.torokhov at gmail.com>

Signed-off-by: Dmitry Torokhov <dtor at mail.ru>
---

 arch/arm/plat-samsung/include/plat/keypad.h      |   21 -
 arch/arm/plat-samsung/include/plat/regs-keypad.h |   49 ---
 drivers/input/keyboard/samsung-keypad.c          |  334 ++++++++++++++--------
 3 files changed, 215 insertions(+), 189 deletions(-)
 delete mode 100644 arch/arm/plat-samsung/include/plat/regs-keypad.h


diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/plat-samsung/include/plat/keypad.h
index 04ba600..0a35784 100644
--- a/arch/arm/plat-samsung/include/plat/keypad.h
+++ b/arch/arm/plat-samsung/include/plat/keypad.h
@@ -34,24 +34,11 @@
  */
 struct samsung_keypad_platdata {
 	const struct matrix_keymap_data	*keymap_data;
-	unsigned int		rows;
-	unsigned int		cols;
-	unsigned int		rep:1;
+	unsigned int rows;
+	unsigned int cols;
+	bool rep;
 
-	void	(*cfg_gpio)(unsigned int rows, unsigned int cols);
+	void (*cfg_gpio)(unsigned int rows, unsigned int cols);
 };
 
-/**
- * samsung_keypad_set_platdata - Set platform data for Samsung Keypad device.
- * @pd: Platform data to register to device.
- *
- * Register the given platform data for use with Samsung Keypad device.
- * The call will copy the platform data, so the board definitions can
- * make the structure itself __initdata.
- */
-extern void samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd);
-
-/* defined by architecture to configure gpio. */
-extern void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols);
-
 #endif /* __PLAT_SAMSUNG_KEYPAD_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-keypad.h b/arch/arm/plat-samsung/include/plat/regs-keypad.h
deleted file mode 100644
index e4688f0..0000000
--- a/arch/arm/plat-samsung/include/plat/regs-keypad.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * linux/arch/arm/plat-samsung/include/plat/regs-keypad.h
- *
- * Copyright (C) 2010 Samsung Electronics Co.Ltd
- * Author: Joonyoung Shim <jy0922.shim at samsung.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- */
-
-#ifndef __SAMSUNG_KEYPAD_H__
-#define __SAMSUNG_KEYPAD_H__
-
-#define SAMSUNG_KEYIFCON			0x00
-#define SAMSUNG_KEYIFSTSCLR			0x04
-#define SAMSUNG_KEYIFCOL			0x08
-#define SAMSUNG_KEYIFROW			0x0c
-#define SAMSUNG_KEYIFFC				0x10
-
-/* SAMSUNG_KEYIFCON */
-#define SAMSUNG_KEYIFCON_INT_F_EN		(1 << 0)
-#define SAMSUNG_KEYIFCON_INT_R_EN		(1 << 1)
-#define SAMSUNG_KEYIFCON_DF_EN			(1 << 2)
-#define SAMSUNG_KEYIFCON_FC_EN			(1 << 3)
-#define SAMSUNG_KEYIFCON_WAKEUPEN		(1 << 4)
-
-/* SAMSUNG_KEYIFSTSCLR */
-#define SAMSUNG_KEYIFSTSCLR_P_INT_MASK		(0xff << 0)
-#define SAMSUNG_KEYIFSTSCLR_R_INT_MASK		(0xff << 8)
-#define SAMSUNG_KEYIFSTSCLR_R_INT_OFFSET	8
-#define S5PV210_KEYIFSTSCLR_P_INT_MASK		(0x3fff << 0)
-#define S5PV210_KEYIFSTSCLR_R_INT_MASK		(0x3fff << 16)
-#define S5PV210_KEYIFSTSCLR_R_INT_OFFSET	16
-
-/* SAMSUNG_KEYIFCOL */
-#define SAMSUNG_KEYIFCOL_MASK			(0xff << 0)
-#define S5PV210_KEYIFCOLEN_MASK			(0xff << 8)
-
-/* SAMSUNG_KEYIFROW */
-#define SAMSUNG_KEYIFROW_MASK			(0xff << 0)
-#define S5PV210_KEYIFROW_MASK			(0x3fff << 0)
-
-/* SAMSUNG_KEYIFFC */
-#define SAMSUNG_KEYIFFC_MASK			(0x3ff << 0)
-
-#endif /* __SAMSUNG_KEYPAD_H__ */
diff --git a/drivers/input/keyboard/samsung-keypad.c b/drivers/input/keyboard/samsung-keypad.c
index 244a3b6..c243fc5 100644
--- a/drivers/input/keyboard/samsung-keypad.c
+++ b/drivers/input/keyboard/samsung-keypad.c
@@ -1,5 +1,5 @@
 /*
- * samsung-keypad.c  --  Samsung keypad driver
+ * Samsung keypad driver
  *
  * Copyright (C) 2010 Samsung Electronics Co.Ltd
  * Author: Joonyoung Shim <jy0922.shim at samsung.com>
@@ -21,8 +21,45 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
-#include <plat/keypad.h>
-#include <plat/regs-keypad.h>
+//#include <plat/keypad.h>
+#include "/home/dtor/kernel/work/arch/arm/plat-samsung/include/plat/keypad.h"
+
+MODULE_DESCRIPTION("Samsung keypad driver");
+MODULE_AUTHOR("Joonyoung Shim <jy0922.shim at samsung.com>");
+MODULE_AUTHOR("Donghwa Lee <dh09.lee at samsung.com>");
+MODULE_LICENSE("GPL");
+
+#define SAMSUNG_KEYIFCON			0x00
+#define SAMSUNG_KEYIFSTSCLR			0x04
+#define SAMSUNG_KEYIFCOL			0x08
+#define SAMSUNG_KEYIFROW			0x0c
+#define SAMSUNG_KEYIFFC				0x10
+
+/* SAMSUNG_KEYIFCON */
+#define SAMSUNG_KEYIFCON_INT_F_EN		(1 << 0)
+#define SAMSUNG_KEYIFCON_INT_R_EN		(1 << 1)
+#define SAMSUNG_KEYIFCON_DF_EN			(1 << 2)
+#define SAMSUNG_KEYIFCON_FC_EN			(1 << 3)
+#define SAMSUNG_KEYIFCON_WAKEUPEN		(1 << 4)
+
+/* SAMSUNG_KEYIFSTSCLR */
+#define SAMSUNG_KEYIFSTSCLR_P_INT_MASK		(0xff << 0)
+#define SAMSUNG_KEYIFSTSCLR_R_INT_MASK		(0xff << 8)
+#define SAMSUNG_KEYIFSTSCLR_R_INT_OFFSET	8
+#define S5PV210_KEYIFSTSCLR_P_INT_MASK		(0x3fff << 0)
+#define S5PV210_KEYIFSTSCLR_R_INT_MASK		(0x3fff << 16)
+#define S5PV210_KEYIFSTSCLR_R_INT_OFFSET	16
+
+/* SAMSUNG_KEYIFCOL */
+#define SAMSUNG_KEYIFCOL_MASK			(0xff << 0)
+#define S5PV210_KEYIFCOLEN_MASK			(0xff << 8)
+
+/* SAMSUNG_KEYIFROW */
+#define SAMSUNG_KEYIFROW_MASK			(0xff << 0)
+#define S5PV210_KEYIFROW_MASK			(0x3fff << 0)
+
+/* SAMSUNG_KEYIFFC */
+#define SAMSUNG_KEYIFFC_MASK			(0x3ff << 0)
 
 enum samsung_keypad_type {
 	KEYPAD_TYPE_SAMSUNG,
@@ -31,29 +68,28 @@ enum samsung_keypad_type {
 
 struct samsung_keypad {
 	struct input_dev *input_dev;
-	struct timer_list timer;
 	struct clk *clk;
-	struct work_struct work;
 	void __iomem *base;
-	unsigned short *keycodes;
+	wait_queue_head_t wait;
+	bool stopped;
+	int irq;
 	unsigned int row_shift;
 	unsigned int rows;
 	unsigned int cols;
 	unsigned int row_state[SAMSUNG_MAX_COLS];
-	int irq;
+	unsigned short keycodes[];
 };
 
 static int samsung_keypad_is_s5pv210(struct device *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
-	enum samsung_keypad_type type;
+	enum samsung_keypad_type type = platform_get_device_id(pdev)->driver_data;
 
-	type = platform_get_device_id(pdev)->driver_data;
 	return type == KEYPAD_TYPE_S5PV210;
 }
 
 static void samsung_keypad_scan(struct samsung_keypad *keypad,
-		unsigned int *row_state)
+				unsigned int *row_state)
 {
 	struct device *dev = keypad->input_dev->dev.parent;
 	unsigned int col;
@@ -79,29 +115,15 @@ static void samsung_keypad_scan(struct samsung_keypad *keypad,
 	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
 }
 
-static void samsung_keypad_worker(struct work_struct *work)
+static bool samsung_keypad_report(struct samsung_keypad *keypad,
+				  unsigned int *row_state)
 {
-	struct samsung_keypad *keypad = container_of(work,
-			struct samsung_keypad, work);
-	unsigned int row_state[SAMSUNG_MAX_COLS];
-	unsigned int val;
+	struct input_dev *input_dev = keypad->input_dev;
 	unsigned int changed;
 	unsigned int pressed;
 	unsigned int key_down = 0;
-	int col, row;
-
-	clk_enable(keypad->clk);
-
-	val = readl(keypad->base + SAMSUNG_KEYIFSTSCLR);
-
-	/* interrupt clear */
-	writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR);
-
-	val = readl(keypad->base + SAMSUNG_KEYIFCON);
-	val &= ~(SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN);
-	writel(val, keypad->base + SAMSUNG_KEYIFCON);
-
-	samsung_keypad_scan(keypad, row_state);
+	unsigned int val;
+	unsigned int col, row;
 
 	for (col = 0; col < keypad->cols; col++) {
 		changed = row_state[col] ^ keypad->row_state[col];
@@ -121,42 +143,108 @@ static void samsung_keypad_worker(struct work_struct *work)
 
 			val = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
 
-			input_report_key(keypad->input_dev,
+			input_event(input_dev, EV_MSC, MSC_SCAN, val);
+			input_report_key(input_dev,
 					keypad->keycodes[val], pressed);
-			input_sync(keypad->input_dev);
 		}
+		input_sync(keypad->input_dev);
 	}
+
 	memcpy(keypad->row_state, row_state, sizeof(row_state));
 
-	if (key_down)
-		mod_timer(&keypad->timer, jiffies + HZ / 20);
-	else {
-		/* enable interrupt bit */
-		val = readl(keypad->base + SAMSUNG_KEYIFCON);
-		val |= (SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN);
-		writel(val, keypad->base + SAMSUNG_KEYIFCON);
-		enable_irq(keypad->irq);
-	}
-	clk_disable(keypad->clk);
+	return key_down;
 }
 
-static irqreturn_t samsung_keypad_interrupt(int irq, void *dev_id)
+static irqreturn_t samsung_keypad_irq(int irq, void *dev_id)
 {
 	struct samsung_keypad *keypad = dev_id;
+	unsigned int row_state[SAMSUNG_MAX_COLS];
+	unsigned int val;
+	bool key_down;
 
-	if (!work_pending(&keypad->work)) {
-		disable_irq_nosync(keypad->irq);
-		schedule_work(&keypad->work);
-	}
+	do {
+		clk_enable(keypad->clk);
+
+		val = readl(keypad->base + SAMSUNG_KEYIFSTSCLR);
+		/* Clear interrupt. */
+		writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR);
+
+		samsung_keypad_scan(keypad, row_state);
+
+		clk_disable(keypad->clk);
+
+		key_down = samsung_keypad_report(keypad, row_state);
+		if (key_down)
+			wait_event_timeout(keypad->wait, keypad->stopped,
+					   msecs_to_jiffies(50));
+
+	} while (key_down && !keypad->stopped);
 
 	return IRQ_HANDLED;
 }
 
-static void samsung_keypad_timer(unsigned long data)
+static void samsung_keypad_start(struct samsung_keypad *keypad)
+{
+	unsigned int val;
+
+	/* Tell IRQ thread that it may poll the device. */
+	keypad->stopped = false;
+
+	clk_enable(keypad->clk);
+
+	/* Enable interrupt bits. */
+	val = readl(keypad->base + SAMSUNG_KEYIFCON);
+	val |= SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN;
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	/* KEYIFCOL reg clear. */
+	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+
+	clk_disable(keypad->clk);
+}
+
+static void samsung_keypad_stop(struct samsung_keypad *keypad)
 {
-	struct samsung_keypad *keypad = (struct samsung_keypad *)data;
+	unsigned int val;
+
+	/* Signal IRQ thread to stop polling and disable the handler. */
+	keypad->stopped = true;
+	wake_up(&keypad->wait);
+	disable_irq(keypad->irq);
 
-	schedule_work(&keypad->work);
+	clk_enable(keypad->clk);
+
+	/* Clear interrupt. */
+	writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR);
+
+	/* Disable interrupt bits. */
+	val = readl(keypad->base + SAMSUNG_KEYIFCON);
+	val &= ~(SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN);
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	clk_disable(keypad->clk);
+
+	/*
+	 * Now that chip should not generate interrupts we can safely
+	 * re-enable the handler.
+	 */
+	enable_irq(keypad->irq);
+}
+
+static int samsung_keypad_open(struct input_dev *input_dev)
+{
+	struct samsung_keypad *keypad = input_get_drvdata(input_dev);
+
+	samsung_keypad_start(keypad);
+
+	return 0;
+}
+
+static void samsung_keypad_close(struct input_dev *input_dev)
+{
+	struct samsung_keypad *keypad = input_get_drvdata(input_dev);
+
+	samsung_keypad_stop(keypad);
 }
 
 static int __devinit samsung_keypad_probe(struct platform_device *pdev)
@@ -166,10 +254,9 @@ static int __devinit samsung_keypad_probe(struct platform_device *pdev)
 	struct samsung_keypad *keypad;
 	struct resource *res;
 	struct input_dev *input_dev;
-	unsigned short *keycodes;
 	unsigned int row_shift;
-	unsigned int val;
-	int ret;
+	unsigned int keymap_size;
+	int error;
 
 	pdata = pdev->dev.platform_data;
 	if (!pdata) {
@@ -183,10 +270,10 @@ static int __devinit samsung_keypad_probe(struct platform_device *pdev)
 		return -EINVAL;
 	}
 
-	if (!pdata->rows || (pdata->rows > SAMSUNG_MAX_ROWS))
+	if (!pdata->rows || pdata->rows > SAMSUNG_MAX_ROWS)
 		return -EINVAL;
 
-	if (!pdata->cols || (pdata->cols > SAMSUNG_MAX_COLS))
+	if (!pdata->cols || pdata->cols > SAMSUNG_MAX_COLS)
 		return -EINVAL;
 
 	/* initialize the gpio */
@@ -194,133 +281,144 @@ static int __devinit samsung_keypad_probe(struct platform_device *pdev)
 		pdata->cfg_gpio(pdata->rows, pdata->cols);
 
 	row_shift = get_count_order(pdata->cols);
-	keypad = kzalloc(sizeof(*keypad), GFP_KERNEL);
-	keycodes = kzalloc((pdata->rows << row_shift) * sizeof(*keycodes),
-			GFP_KERNEL);
+	keymap_size = (pdata->rows << row_shift) * sizeof(keypad->keycodes[0]);
+
+	keypad = kzalloc(sizeof(*keypad) + keymap_size, GFP_KERNEL);
 	input_dev = input_allocate_device();
-	if (!keypad || !keycodes || !input_dev) {
-		ret = -ENOMEM;
+	if (!keypad || !input_dev) {
+		error = -ENOMEM;
 		goto err_free_mem;
 	}
 
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
-		ret = -ENODEV;
+		error = -ENODEV;
 		goto err_free_mem;
 	}
 
 	keypad->base = ioremap(res->start, resource_size(res));
 	if (!keypad->base) {
-		ret = -EBUSY;
+		error = -EBUSY;
 		goto err_free_mem;
 	}
 
 	keypad->clk = clk_get(&pdev->dev, "keypad");
 	if (IS_ERR(keypad->clk)) {
 		dev_err(&pdev->dev, "failed to get keypad clk\n");
-		ret = PTR_ERR(keypad->clk);
+		error = PTR_ERR(keypad->clk);
 		goto err_unmap_base;
 	}
-	clk_enable(keypad->clk);
 
 	keypad->input_dev = input_dev;
-	keypad->keycodes = keycodes;
 	keypad->row_shift = row_shift;
 	keypad->rows = pdata->rows;
 	keypad->cols = pdata->cols;
-
-	INIT_WORK(&keypad->work, samsung_keypad_worker);
-
-	setup_timer(&keypad->timer, samsung_keypad_timer,
-			(unsigned long)keypad);
-
-	/* enable interrupt and wakeup bit */
-	val = SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN |
-		SAMSUNG_KEYIFCON_WAKEUPEN;
-	writel(val, keypad->base + SAMSUNG_KEYIFCON);
-
-	/* KEYIFCOL reg clear */
-	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
-
-	keypad->irq = platform_get_irq(pdev, 0);
-	if (keypad->irq < 0) {
-		ret = keypad->irq;
-		goto err_disable_clk;
-	}
-
-	ret = request_irq(keypad->irq, samsung_keypad_interrupt, 0,
-			dev_name(&pdev->dev), keypad);
-
-	if (ret)
-		goto err_disable_clk;
+	init_waitqueue_head(&keypad->wait);
 
 	input_dev->name = pdev->name;
 	input_dev->id.bustype = BUS_HOST;
 	input_dev->dev.parent = &pdev->dev;
+	input_set_drvdata(input_dev, keypad);
+
+	input_dev->open = samsung_keypad_open;
+	input_dev->close = samsung_keypad_close;
 
 	input_dev->evbit[0] = BIT_MASK(EV_KEY);
 	if (pdata->rep)
 		input_dev->evbit[0] |= BIT_MASK(EV_REP);
 
-	input_dev->keycode = keycodes;
-	input_dev->keycodesize = sizeof(*keycodes);
+	input_dev->keycode = keypad->keycodes;
+	input_dev->keycodesize = sizeof(keypad->keycodes[0]);
 	input_dev->keycodemax = pdata->rows << row_shift;
 
 	matrix_keypad_build_keymap(keymap_data, row_shift,
 			input_dev->keycode, input_dev->keybit);
 
-	ret = input_register_device(keypad->input_dev);
-	if (ret)
+	keypad->irq = platform_get_irq(pdev, 0);
+	if (keypad->irq < 0) {
+		error = keypad->irq;
+		goto err_put_clk;
+	}
+
+	error = request_threaded_irq(keypad->irq, NULL, samsung_keypad_irq,
+				     IRQF_ONESHOT, dev_name(&pdev->dev), keypad);
+	if (error)
+		goto err_put_clk;
+
+	error = input_register_device(keypad->input_dev);
+	if (error)
 		goto err_free_irq;
 
 	platform_set_drvdata(pdev, keypad);
-	clk_disable(keypad->clk);
-
 	return 0;
 
 err_free_irq:
 	free_irq(keypad->irq, keypad);
-err_disable_clk:
-	clk_disable(keypad->clk);
+err_put_clk:
 	clk_put(keypad->clk);
 err_unmap_base:
 	iounmap(keypad->base);
 err_free_mem:
 	input_free_device(input_dev);
-	kfree(keycodes);
 	kfree(keypad);
 
-	return ret;
+	return error;
 }
 
 static int __devexit samsung_keypad_remove(struct platform_device *pdev)
 {
 	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
 
-	free_irq(keypad->irq, keypad);
-	cancel_work_sync(&keypad->work);
-	del_timer_sync(&keypad->timer);
-
 	platform_set_drvdata(pdev, NULL);
+
 	input_unregister_device(keypad->input_dev);
 
-	clk_disable(keypad->clk);
+	/*
+	 * It is safe to free IRQ after unregistering device because
+	 * samsung_keypad_close will shut off interrupts.
+	 */
+	free_irq(keypad->irq, keypad);
+
 	clk_put(keypad->clk);
 
 	iounmap(keypad->base);
-	kfree(keypad->keycodes);
 	kfree(keypad);
 
 	return 0;
 }
 
 #ifdef CONFIG_PM
+static void samsung_keypad_toggle_wakeup(struct samsung_keypad *keypad,
+					 bool enable)
+{
+	unsigned int val;
+
+	clk_enable(keypad->clk);
+
+	val = readl(keypad->base + SAMSUNG_KEYIFCON);
+	if (enable)
+		val |= SAMSUNG_KEYIFCON_WAKEUPEN;
+	else
+		val &= ~SAMSUNG_KEYIFCON_WAKEUPEN;
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	clk_disable(keypad->clk);
+}
+
 static int samsung_keypad_suspend(struct device *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
 	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+	struct input_dev *input_dev = keypad->input_dev;
 
-	disable_irq(keypad->irq);
+	mutex_lock(&input_dev->mutex);
+
+	if (input_dev->users)
+		samsung_keypad_stop(keypad);
+
+	samsung_keypad_toggle_wakeup(keypad, true);
+
+	mutex_unlock(&input_dev->mutex);
 
 	return 0;
 }
@@ -329,20 +427,16 @@ static int samsung_keypad_resume(struct device *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
 	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
-	unsigned int val;
+	struct input_dev *input_dev = keypad->input_dev;
 
-	clk_enable(keypad->clk);
+	mutex_lock(&input_dev->mutex);
 
-	/* enable interrupt and wakeup bit */
-	val = SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN |
-		SAMSUNG_KEYIFCON_WAKEUPEN;
-	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+	samsung_keypad_toggle_wakeup(keypad, false);
 
-	/* KEYIFCOL reg clear */
-	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+	if (input_dev->users)
+		samsung_keypad_start(keypad);
 
-	enable_irq(keypad->irq);
-	clk_disable(keypad->clk);
+	mutex_unlock(&input_dev->mutex);
 
 	return 0;
 }
@@ -382,16 +476,10 @@ static int __init samsung_keypad_init(void)
 {
 	return platform_driver_register(&samsung_keypad_driver);
 }
+module_init(samsung_keypad_init);
 
 static void __exit samsung_keypad_exit(void)
 {
 	platform_driver_unregister(&samsung_keypad_driver);
 }
-
-module_init(samsung_keypad_init);
 module_exit(samsung_keypad_exit);
-
-MODULE_DESCRIPTION("Samsung keypad driver");
-MODULE_AUTHOR("Joonyoung Shim <jy0922.shim at samsung.com>");
-MODULE_AUTHOR("Donghwa Lee <dh09.lee at samsung.com>");
-MODULE_LICENSE("GPL");


From sw1-arm-linux at gmx.de  Fri Jun 25 04:30:59 2010
From: sw1-arm-linux at gmx.de (Stefan)
Date: Fri, 25 Jun 2010 10:30:59 +0200
Subject: NXP LPC3250 LCD controller
In-Reply-To: <201006241544.32140.sw1-arm-linux@gmx.de>
References: <201006241544.32140.sw1-arm-linux@gmx.de>
Message-ID: <201006251030.59566.sw1-arm-linux@gmx.de>

> Hi,
>
> there is an errata for NXP LPC3250 LCD controller.

My fault. Was only the '-' initial chip revision. With 'A' rev there seems no 
problem.

Stefan


From myungjoo.ham at samsung.com  Fri Jun 25 04:38:20 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Fri, 25 Jun 2010 17:38:20 +0900
Subject: clock updates
In-Reply-To: <20100623232422.GB16584@trinity.fluff.org>
References: <20100623232422.GB16584@trinity.fluff.org>
Message-ID: <AANLkTikIOfUS-hOs8ea3cqBntYJEFTD4pEFgte8qbMTH@mail.gmail.com>

Hello,

On Thu, Jun 24, 2010 at 8:24 AM, Ben Dooks <ben-linux at fluff.org> wrote:
> I've been looking into updating the current samsung socs to use
> clkdev to lookup clocks. Currently we have a few issues that we
> could do with sorting before running the conversion to clkdev.
>
> Firstly, the s5pc100 has some clocks that could be merged into
> common s5p, and a few which don't seem to match the others in
> the s5p series.
>
> The i2s clocks which we should look at mergining are:
>
> i2s_cdclk<0..2>
> pcm_cdclk<0..l>
>
> also, clocks that have may need changing:
>
> rotator ? ? ?=> rot
> keyif ? ? ? ?=> keypad
>
> this isn't an complete list, still working on the changes.
>
> The big changes with respect to drivers is that we will now be using
> clk_get(dev, NULL) to get the clock names, and any bus clocks such
> as the sdhci bus clock will be updated.
>
> The intention with both the SDHCI and the SPI is to change the clock
> lookups to reflect the mux positions, so the sdhci clocks on the
> s3c64xx would be changed to use the following lookups:
>
> hsmmc ? => mux0
> mmc_bus => mux2
> 48m ? ? => mux3
>
> This would avoid passing the clock names through the platform data, if
> the boards or the arch needs to avoid a clock, an array of clock enable
> or disable bits. Any unimplemented clocks will return NULL to ensure
> that they can be distinguished from a clock that isn't available.
>
> The changes would be to remove the .name field from all the s3c struct clk,
> and replace it with a pointer to a lookup (so that if the clock does not
> need a name then it doesn't need a lookup).

I also like the idea using clk_get based on the name of struct device
and getting rid of name field from clk.

However, what about devices and clocks with the same name and
different id numbers (i.e., platform_device.id)? Are you going to add
.id lookup to clkdev's clk_find? There are multiple clocks with the
same name and different id number.


>
> There are also a number of clocks that probably don't need a name as they
> are part of the clock heirarchy, it would be useful to have a call that
> returns all possible parents of a given clock.
>
> I'll post the script whcih runs the changes once i've finished the last
> few details to show what happens.
>
> With resepect to the clkdev clk_get() function, we may need to do a couple of
> updates (ie, override it for ourselves) due to the following two problems:
>
> 1) The s3c/s5p devices change name depending on the soc they are attached
> ? to, which means we may need to cut the s3cxxxx- part of the device name
> ? off before running the lookup
>
> 2) Some of the lookups are done early for the serial driver, which means
> ? that the platform devices's name has not been setup, so something needs
> ? to be done about this.
>
> --
> Ben
>
>
>
>
>
>
>
>
>
>
> --
> Ben
>
> Q: ? ? ?What's a light-year?
> A: ? ? ?One-third less calories than a regular year.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>


Cheers!

-- 
MyungJoo Ham (???), Ph.D.
Mobile Software Platform Lab,
Digital Media and Communications (DMC) Business
Samsung Electronics
cell: 82-10-6714-2858


From jamie.iles at picochip.com  Fri Jun 25 04:14:01 2010
From: jamie.iles at picochip.com (Jamie Iles)
Date: Fri, 25 Jun 2010 09:14:01 +0100
Subject: [PATCH 0/2] add perf-probe support on ARM
In-Reply-To: <1277285763-16213-1-git-send-email-will.deacon@arm.com>
References: <1277285763-16213-1-git-send-email-will.deacon@arm.com>
Message-ID: <20100625081401.GL5160@wear.picochip.com>

On Wed, Jun 23, 2010 at 10:36:01AM +0100, Will Deacon wrote:
> Perf-probe uses the KProbe events tracer to place and monitor probes
> on the running Kernel.
> 
> This patch series adds both Kernel and tool support for this feature
> on ARM.
> 
> Patches based on 2.6.35-rc3 [although perf record is currently broken
> on all architectures for probe tracepoints. These patches also apply
> cleanly to -tip/master where perf record works properly.]
> 
> Cc: Jamie Iles <jamie.iles at picochip.com>
> Cc: Jean Pihet <jpihet at mvista.com>
> 
> Will Deacon (2):
>   ARM: Add kprobe-based event tracer
>   ARM: perf probe: Add ARM DWARF register number mappings
> 
>  arch/arm/Kconfig                      |    1 +
>  arch/arm/include/asm/ptrace.h         |   36 ++++++++++++
>  arch/arm/kernel/ptrace.c              |   96 +++++++++++++++++++++++++++++++++
>  tools/perf/arch/arm/Makefile          |    4 ++
>  tools/perf/arch/arm/util/dwarf-regs.c |   64 ++++++++++++++++++++++
>  5 files changed, 201 insertions(+), 0 deletions(-)
>  create mode 100644 tools/perf/arch/arm/Makefile
>  create mode 100644 tools/perf/arch/arm/util/dwarf-regs.c
Hi Will,

I've had a quick play on an ARMv6 board and these patches look good and appear
to work!

Tested-by: Jamie Iles <jamie.iles at picochip.com>

Jamie


From linux at arm.linux.org.uk  Fri Jun 25 05:08:39 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 25 Jun 2010 10:08:39 +0100
Subject: clock updates
In-Reply-To: <AANLkTikIOfUS-hOs8ea3cqBntYJEFTD4pEFgte8qbMTH@mail.gmail.com>
References: <20100623232422.GB16584@trinity.fluff.org>
	<AANLkTikIOfUS-hOs8ea3cqBntYJEFTD4pEFgte8qbMTH@mail.gmail.com>
Message-ID: <20100625090839.GA22090@n2100.arm.linux.org.uk>

On Fri, Jun 25, 2010 at 05:38:20PM +0900, MyungJoo Ham wrote:
> However, what about devices and clocks with the same name and
> different id numbers (i.e., platform_device.id)? Are you going to add
> .id lookup to clkdev's clk_find? There are multiple clocks with the
> same name and different id number.

Platform devices are assigned names which are <basename>.<id> where id != -1.
The basename is matched by the driver.  The <basename>.<id> is what you
see in sysfs, and is the name of the underlying struct device.


From sshtylyov at mvista.com  Fri Jun 25 05:45:39 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Fri, 25 Jun 2010 13:45:39 +0400
Subject: strange segfaults with CompactFlash in "true-ide" mode on PXA270
In-Reply-To: <201006250911.30277.schindele@nentec.de>
References: <201006231706.33182.schindele@nentec.de>	<19490.10015.10027.750374@ipc1.ka-ro>
	<201006250911.30277.schindele@nentec.de>
Message-ID: <4C247AC3.2050906@ru.mvista.com>

Hello.

Juergen Schindele wrote:

>>> we have a strange problem when booting from a Compact Flash card
>>> as root-device. In one of 10 cases while booting an application from
>>> root-filesystem dies with "Segmentation fault" without a visible error.
>>> After booting the same application runs hundred times without error.
>>> (we're talking about standard appl. like chat, pppd, hwclock and so on)
>>>
>>> For debugging purposes we put printk's in kernels IDE driver 
>>> and the problem disappeared. But replacing the printk by a usleep
>>> or so (which is not a solution !) brings the problem back.
>>> It seems that the application received faulty data from CF.
>>> But how and why ?????????????????????????????
>>>
>>> We tested with a custom PXA270 board with a CompactFlash in 
>>> "true ide" on processor bus driven by "generic ide / pata_platform"
>>> driver from linux-2.6.27.x.
>>> (by the way linux-2.6.20.x showed the same problem).
>>>
>>> Any ideas, hints, experiences, patches are very welcome :-)
>>> --------------------------------------------------------------
>> I guess that is the old cache problem that apparently was never really
>> fixed:
>> http://marc.info/?t=108537828400002&r=1&w=2

> Hello
> this hint was very helpful for understanding the problem.
> In the mail from Russell King at 
> <http://marc.info/?l=linux-arm-kernel&m=108611676807909&w=2>
> he said : .... the rule is if the CPU writes to a page cache page,
> it must call flush_dcache_page afterwards to ensure cache coherency with user space".

> so i made the following patch in drivers/ide/ide-taskfile.c
> in the function ide_pio_sector() where blocks from disk are read
> into a cached page to apply the rule from Russell. 
> ===================================================================
> --- ide-taskfile.c
> +++ ide-taskfile.c.new
> @@ -278,6 +278,7 @@
>                 hwif->tp_ops->input_data(drive, rq, buf, SECTOR_SIZE);
> 
>         kunmap_atomic(buf, KM_BIO_SRC_IRQ);
> +       flush_dcache_page(page);
>  #ifdef CONFIG_HIGHMEM
>         local_irq_restore(flags);
>  #endif

> And from there on the problem disappeared :-))
> What are you think about ???

    Flushing is only needed for reads and shouldn't be done for the slab pages 
(judging on libata's code).

> Isn't this missing for years in IDE PIO driver ???

    It's actually missing from the ARM port of IDE. E.g. the MIPS port 
provides for that -- see arch/mips/include/asm/mach-generic/ide.h.

WBR, Sergei


From will.deacon at arm.com  Fri Jun 25 05:51:26 2010
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 25 Jun 2010 10:51:26 +0100
Subject: [PATCH 0/2] add perf-probe support on ARM
In-Reply-To: <20100625081401.GL5160@wear.picochip.com>
References: <1277285763-16213-1-git-send-email-will.deacon@arm.com>
	<20100625081401.GL5160@wear.picochip.com>
Message-ID: <000f01cb144b$fa6be9b0$ef43bd10$@deacon@arm.com>

Hi Jamie,

> I've had a quick play on an ARMv6 board and these patches look good and appear
> to work!
> 
> Tested-by: Jamie Iles <jamie.iles at picochip.com>

Cracking, thanks for this. I'll stick them in the patch system.

Will




From jy0922.shim at samsung.com  Fri Jun 25 06:25:16 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 25 Jun 2010 19:25:16 +0900
Subject: [PATCH v5 3/3] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <20100625083019.GD8546@core.coreip.homeip.net>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<1277101605-2435-3-git-send-email-jy0922.shim@samsung.com>
	<20100625083019.GD8546@core.coreip.homeip.net>
Message-ID: <4C24840C.1000701@samsung.com>

On 6/25/2010 5:30 PM, Dmitry Torokhov wrote:
> Hi Joonyoung,
> 
> On Mon, Jun 21, 2010 at 03:26:45PM +0900, Joonyoung Shim wrote:
>> This patch adds support for keypad driver running on Samsung cpus. This
>> driver is tested on GONI and Aquila board using S5PC110 cpu.
>>
>> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> 
> Following my conversation with Thomas Gleixner reagrding "long playing"
> threaded interrupt handlers I tried to convert your driver to use this
> concept. The idea is to keep polling within IRQ thread context instead
> of using additional work/timer structures to simplify code and ensure
> race-free shutdown/unbind.
> 
> I think it was based on v4 of your driver and I'd appreciate if you could
> give it a try.
> 

Your patch gives me below patch errors.

$ patch -p1 --dry-run < 2.patch
(Stripping trailing CRs from patch.)
patching file drivers/input/keyboard/samsung-keypad.c
Hunk #3 FAILED at 68.
Hunk #4 FAILED at 116.
Hunk #5 FAILED at 158.
Hunk #6 succeeded at 196 (offset -7 lines).
Hunk #7 succeeded at 212 (offset -7 lines).
Hunk #8 FAILED at 230.
Hunk #9 FAILED at 365.
Hunk #10 FAILED at 418.
6 out of 10 hunks FAILED -- saving rejects to file
drivers/input/keyboard/samsung-keypad.c.rej

Can you give me your patch based on my v5 patches? If not, i should try
manual merge.

Thanks.


From will.deacon at arm.com  Fri Jun 25 06:35:45 2010
From: will.deacon at arm.com (Will Deacon)
Date: Fri, 25 Jun 2010 11:35:45 +0100
Subject: [PATCH 0/2] add perf-probe support on ARM
In-Reply-To: <AANLkTimU1W0feaSKyKCFHdZSG_RE6G_sFiAZ6jtU434w@mail.gmail.com>
References: <1277285763-16213-1-git-send-email-will.deacon@arm.com>
	<AANLkTimU1W0feaSKyKCFHdZSG_RE6G_sFiAZ6jtU434w@mail.gmail.com>
Message-ID: <001401cb1452$2b409e40$81c1dac0$@deacon@arm.com>

> Hi Will,

Hi Jean,

> Are more tests needed for ARMv7 (OMAP3430/3530/3517)? I hope to find some time to test it if required.

The patches don't do anything special for the different architectures
and I've tried it on a quad-core A9 board so I don't think you're required
to test it as well. Having said that, it's a pretty neat tool so you might
want to have a play :)

Thanks,

Will




From jy0922.shim at samsung.com  Fri Jun 25 06:39:49 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Fri, 25 Jun 2010 19:39:49 +0900
Subject: [PATCH v5 3/3] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <4C24840C.1000701@samsung.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<1277101605-2435-3-git-send-email-jy0922.shim@samsung.com>
	<20100625083019.GD8546@core.coreip.homeip.net>
	<4C24840C.1000701@samsung.com>
Message-ID: <4C248775.5080306@samsung.com>

On 6/25/2010 7:25 PM, Joonyoung Shim wrote:
> On 6/25/2010 5:30 PM, Dmitry Torokhov wrote:
>> Hi Joonyoung,
>>
>> On Mon, Jun 21, 2010 at 03:26:45PM +0900, Joonyoung Shim wrote:
>>> This patch adds support for keypad driver running on Samsung cpus. This
>>> driver is tested on GONI and Aquila board using S5PC110 cpu.
>>>
>>> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
>> Following my conversation with Thomas Gleixner reagrding "long playing"
>> threaded interrupt handlers I tried to convert your driver to use this
>> concept. The idea is to keep polling within IRQ thread context instead
>> of using additional work/timer structures to simplify code and ensure
>> race-free shutdown/unbind.
>>
>> I think it was based on v4 of your driver and I'd appreciate if you could
>> give it a try.
>>
> 
> Your patch gives me below patch errors.
> 

Your patch maybe seems be based on my v3 patch :)

> $ patch -p1 --dry-run < 2.patch
> (Stripping trailing CRs from patch.)
> patching file drivers/input/keyboard/samsung-keypad.c
> Hunk #3 FAILED at 68.
> Hunk #4 FAILED at 116.
> Hunk #5 FAILED at 158.
> Hunk #6 succeeded at 196 (offset -7 lines).
> Hunk #7 succeeded at 212 (offset -7 lines).
> Hunk #8 FAILED at 230.
> Hunk #9 FAILED at 365.
> Hunk #10 FAILED at 418.
> 6 out of 10 hunks FAILED -- saving rejects to file
> drivers/input/keyboard/samsung-keypad.c.rej
> 
> Can you give me your patch based on my v5 patches? If not, i should try
> manual merge.
> 
> Thanks.
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 



From augulis.darius at gmail.com  Fri Jun 25 06:55:31 2010
From: augulis.darius at gmail.com (Darius Augulis)
Date: Fri, 25 Jun 2010 13:55:31 +0300
Subject: S3C2416 fixes (gpiolib, SDHCI, compilation without FB device)
In-Reply-To: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
References: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
Message-ID: <4C248B23.7060905@gmail.com>

On 06/22/2010 04:16 PM, Yauhen Kharuzhy wrote:
> This patch series fixes SDHCI on S3C2416. I got SD card working with this patches
> and with patches for GPIO card detection support by Marek Szyprowski.
>

Unfortunately I did not get SD card working with these patches. I'm 
using custom board, not SMDK2416, but SD slot connection and schematics 
are the same like in SMDK2416. I've tried to debug a bit this problem 
and this is what I got: kernel do detection of card insert/remove, 
driver prints messages:

s3c-sdhci s3c-sdhci.1: card inserted.
s3c-sdhci s3c-sdhci.1: card removed.

Then I put some printk in s3c-sdhci driver and MMC core and found that 
mmc_rescan() is called only once at startup and no more when 
inserting/removing SD card. Also mmc_rescan() stops at that point where 
mmc_power_up() is called and does not return. And mmc_power_up() stops 
where mmc_delay(10) is called and does not return too.
Every time when inserting/removing SD card only functions 
sdhci_tasklet_card() and mmc_detect_change() are called, and nothing 
happens. Kernel doesn't detect the card inserted.
Maybe this info could help to debug where the problem is - in my custom 
board or in your patches?

Darius.


From broonie at opensource.wolfsonmicro.com  Fri Jun 25 07:22:32 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 25 Jun 2010 12:22:32 +0100
Subject: [PATCH] MMC: remove regulator refcount fiddling in mmc core
In-Reply-To: <1277392337-27627-1-git-send-email-linus.walleij@stericsson.com>
References: <1277392337-27627-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <20100625112232.GA21217@opensource.wolfsonmicro.com>

On Thu, Jun 24, 2010 at 05:12:17PM +0200, Linus Walleij wrote:

> Currently the mmc_regulator_set_ocr() fiddles with the regulator
> refcount by selectively calling regulator_[enable|disable]
> depending on the state of the regulator. This will confuse the
> reference count if case the regulator is for example shared with
> other MMC slots or user for other stuff than the MMC card.

> Push regulator_[enable|disable] out into the MMC host drivers
> and remove this from the MMC core so the reference count can be
> trusted.

So, the feedback from folks at the time this was originally written was
that the MMC code was unable to cope with sharing regulators since it
really needs to be able to set specific voltages.  This needn't be a
showstopper since people can force a single voltage in the constraints
but it does need to be considered here.


From broonie at opensource.wolfsonmicro.com  Fri Jun 25 07:52:46 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Fri, 25 Jun 2010 12:52:46 +0100
Subject: clock updates
In-Reply-To: <000801cb142b$e6624420$b326cc60$%szyprowski@samsung.com>
References: <20100623232422.GB16584@trinity.fluff.org>
	<000801cb142b$e6624420$b326cc60$%szyprowski@samsung.com>
Message-ID: <20100625115246.GE2803@sirena.org.uk>

On Fri, Jun 25, 2010 at 08:01:45AM +0200, Marek Szyprowski wrote:

> I like this idea, but I wonder how the drivers will be able to get/control
> the additional peripheral clocks (like sclk_fimc and sclk_cam for fimc for
> example)?

You can still do lookups by name for multiple clocks with clkdev
(personally I prefer to just not make use of the option of using NULL
for a default clock since it's not always clear what the default should
be for a block but there we are).


From catalin.marinas at arm.com  Fri Jun 25 08:01:27 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 25 Jun 2010 13:01:27 +0100
Subject: [PATCH 0/3] Cache maintenance on VIPT caches
Message-ID: <20100625115826.30030.89790.stgit@e102109-lin.cambridge.arm.com>

Hi,

The first and third patches have already been posted in the same form.
The second patch have been modified to handle all the VIPT caches via
__sync_icache_dcache(). The initial use case for this patch was dealing
with an SMP race condition but following suggestions from Rabin, it was
extended to cover ARMv6 onwards, both UP and SMP.

Any Tested-by's are welcome.

Thanks.


Catalin Marinas (3):
      ARM: Assume new page cache pages have dirty D-cache
      ARM: Introduce __sync_icache_dcache() for VIPT caches
      ARM: Use lazy cache flushing on ARMv7 SMP systems


 arch/arm/include/asm/cacheflush.h |    6 ++---
 arch/arm/include/asm/pgtable.h    |   26 +++++++++++++++++++--
 arch/arm/include/asm/smp_plat.h   |    4 +++
 arch/arm/include/asm/tlbflush.h   |   12 ++++++++--
 arch/arm/mm/copypage-v4mc.c       |    2 +-
 arch/arm/mm/copypage-v6.c         |    2 +-
 arch/arm/mm/copypage-xscale.c     |    2 +-
 arch/arm/mm/dma-mapping.c         |    6 +++++
 arch/arm/mm/fault-armv.c          |    8 +++---
 arch/arm/mm/flush.c               |   46 +++++++++++++++++++++++++++++--------
 10 files changed, 89 insertions(+), 25 deletions(-)

-- 
Catalin


From catalin.marinas at arm.com  Fri Jun 25 08:01:32 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 25 Jun 2010 13:01:32 +0100
Subject: [PATCH 1/3] ARM: Assume new page cache pages have dirty D-cache
In-Reply-To: <20100625115826.30030.89790.stgit@e102109-lin.cambridge.arm.com>
References: <20100625115826.30030.89790.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100625120132.30030.5577.stgit@e102109-lin.cambridge.arm.com>

There are places in Linux where writes to newly allocated page cache
pages happen without a subsequent call to flush_dcache_page() (several
PIO drivers including USB HCD). This patch changes the meaning of
PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly
mapped page in update_mmu_cache().

The patch also sets the PG_arch_1 bit in the DMA cache maintenance
function to avoid additional cache flushing in update_mmu_cache().

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Rabin Vincent <rabin.vincent at stericsson.com>
---
 arch/arm/include/asm/cacheflush.h |    6 +++---
 arch/arm/include/asm/tlbflush.h   |    2 +-
 arch/arm/mm/copypage-v4mc.c       |    2 +-
 arch/arm/mm/copypage-v6.c         |    2 +-
 arch/arm/mm/copypage-xscale.c     |    2 +-
 arch/arm/mm/dma-mapping.c         |    6 ++++++
 arch/arm/mm/fault-armv.c          |    4 ++--
 arch/arm/mm/flush.c               |    3 ++-
 8 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..d3730f0 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -137,10 +137,10 @@
 #endif
 
 /*
- * This flag is used to indicate that the page pointed to by a pte
- * is dirty and requires cleaning before returning it to the user.
+ * This flag is used to indicate that the page pointed to by a pte is clean
+ * and does not require cleaning before returning it to the user.
  */
-#define PG_dcache_dirty PG_arch_1
+#define PG_dcache_clean PG_arch_1
 
 /*
  *	MM Cache Management
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index bd863d8..40a7092 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -552,7 +552,7 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 #endif
 
 /*
- * if PG_dcache_dirty is set for the page, we need to ensure that any
+ * If PG_dcache_clean is not set for the page, we need to ensure that any
  * cache entries for the kernels virtual memory range are written
  * back to the page.
  */
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 598c51a..b806151 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -73,7 +73,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
 {
 	void *kto = kmap_atomic(to, KM_USER1);
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index f55fa10..bdba6c6 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -79,7 +79,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
 	unsigned int offset = CACHE_COLOUR(vaddr);
 	unsigned long kfrom, kto;
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	/* FIXME: not highmem safe */
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 9920c0a..649bbcd 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -95,7 +95,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
 {
 	void *kto = kmap_atomic(to, KM_USER1);
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 9e7742f..97c4744 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -508,6 +508,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
 		outer_inv_range(paddr, paddr + size);
 
 	dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+
+	/*
+	 * Mark the D-cache clean for this page to avoid extra flushing.
+	 */
+	if (dir != DMA_TO_DEVICE)
+		set_bit(PG_dcache_clean, &page->flags);
 }
 EXPORT_SYMBOL(___dma_page_dev_to_cpu);
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 9b906de..58846cb 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -141,7 +141,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
  * a page table, or changing an existing PTE.  Basically, there are two
  * things that we need to take care of:
  *
- *  1. If PG_dcache_dirty is set for the page, we need to ensure
+ *  1. If PG_dcache_clean is not set for the page, we need to ensure
  *     that any cache entries for the kernels virtual memory
  *     range are written back to the page.
  *  2. If we have multiple shared mappings of the same space in
@@ -169,7 +169,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 
 	mapping = page_mapping(page);
 #ifndef CONFIG_SMP
-	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
 		__flush_dcache_page(mapping, page);
 #endif
 	if (mapping) {
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index c6844cb..9f9919b 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -248,7 +248,7 @@ void flush_dcache_page(struct page *page)
 
 #ifndef CONFIG_SMP
 	if (!PageHighMem(page) && mapping && !mapping_mapped(mapping))
-		set_bit(PG_dcache_dirty, &page->flags);
+		clear_bit(PG_dcache_clean, &page->flags);
 	else
 #endif
 	{
@@ -257,6 +257,7 @@ void flush_dcache_page(struct page *page)
 			__flush_dcache_aliases(mapping, page);
 		else if (mapping)
 			__flush_icache_all();
+		set_bit(PG_dcache_clean, &page->flags);
 	}
 }
 EXPORT_SYMBOL(flush_dcache_page);



From catalin.marinas at arm.com  Fri Jun 25 08:01:38 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 25 Jun 2010 13:01:38 +0100
Subject: [PATCH 2/3] ARM: Introduce __sync_icache_dcache() for VIPT caches
In-Reply-To: <20100625115826.30030.89790.stgit@e102109-lin.cambridge.arm.com>
References: <20100625115826.30030.89790.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100625120138.30030.87455.stgit@e102109-lin.cambridge.arm.com>

On SMP systems, there is a small chance of a PTE becoming visible to a
different CPU before the current cache maintenance operations in
update_mmu_cache(). To avoid this, cache maintenance must be handled in
set_pte_at() (similar to IA-64 and PowerPC).

This patch provides a unified VIPT cache handling mechanism and
implements the __sync_icache_dcache() function for ARMv6 onwards
architectures. It is called from set_pte_at() and replaces the
update_mmu_cache(). The latter is still used on VIVT hardware where a
vm_area_struct is required.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Rabin Vincent <rabin.vincent at stericsson.com>
---
 arch/arm/include/asm/pgtable.h  |   26 +++++++++++++++++++++++---
 arch/arm/include/asm/tlbflush.h |   10 +++++++++-
 arch/arm/mm/fault-armv.c        |    4 ++--
 arch/arm/mm/flush.c             |   30 ++++++++++++++++++++++++++++++
 4 files changed, 64 insertions(+), 6 deletions(-)

diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index ab68cf1..42e694f 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -278,9 +278,24 @@ extern struct page *empty_zero_page;
 
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
 
-#define set_pte_at(mm,addr,ptep,pteval) do { \
-	set_pte_ext(ptep, pteval, (addr) >= TASK_SIZE ? 0 : PTE_EXT_NG); \
- } while (0)
+#if __LINUX_ARM_ARCH__ < 6
+static inline void __sync_icache_dcache(pte_t pteval)
+{
+}
+#else
+extern void __sync_icache_dcache(pte_t pteval);
+#endif
+
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+			      pte_t *ptep, pte_t pteval)
+{
+	if (addr >= TASK_SIZE)
+		set_pte_ext(ptep, pteval, 0);
+	else {
+		__sync_icache_dcache(pteval);
+		set_pte_ext(ptep, pteval, PTE_EXT_NG);
+	}
+}
 
 /*
  * The following only work if pte_present() is true.
@@ -290,8 +305,13 @@ extern struct page *empty_zero_page;
 #define pte_write(pte)		(pte_val(pte) & L_PTE_WRITE)
 #define pte_dirty(pte)		(pte_val(pte) & L_PTE_DIRTY)
 #define pte_young(pte)		(pte_val(pte) & L_PTE_YOUNG)
+#define pte_exec(pte)		(pte_val(pte) & L_PTE_EXEC)
 #define pte_special(pte)	(0)
 
+#define pte_present_user(pte) \
+	((pte_val(pte) & (L_PTE_PRESENT | L_PTE_USER)) == \
+	 (L_PTE_PRESENT | L_PTE_USER))
+
 #define PTE_BIT_FUNC(fn,op) \
 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
 
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index 40a7092..8ec4775 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -554,10 +554,18 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 /*
  * If PG_dcache_clean is not set for the page, we need to ensure that any
  * cache entries for the kernels virtual memory range are written
- * back to the page.
+ * back to the page. On ARMv6 and later, the cache coherency is handled via
+ * the set_pte_at() function.
  */
+#if __LINUX_ARM_ARCH__ < 6
 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 	pte_t *ptep);
+#else
+static inline void update_mmu_cache(struct vm_area_struct *vma,
+				    unsigned long addr, pte_t *ptep)
+{
+}
+#endif
 
 #endif
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 58846cb..8440d95 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -28,6 +28,7 @@
 
 static unsigned long shared_pte_mask = L_PTE_MT_BUFFERABLE;
 
+#if __LINUX_ARM_ARCH__ < 6
 /*
  * We take the easy way out of this problem - we make the
  * PTE uncacheable.  However, we leave the write buffer on.
@@ -168,10 +169,8 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 		return;
 
 	mapping = page_mapping(page);
-#ifndef CONFIG_SMP
 	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
 		__flush_dcache_page(mapping, page);
-#endif
 	if (mapping) {
 		if (cache_is_vivt())
 			make_coherent(mapping, vma, addr, ptep, pfn);
@@ -179,6 +178,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 			__flush_icache_all();
 	}
 }
+#endif	/* __LINUX_ARM_ARCH__ < 6 */
 
 /*
  * Check whether the write buffer has physical address aliasing
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 9f9919b..78134f5 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -215,6 +215,36 @@ static void __flush_dcache_aliases(struct address_space *mapping, struct page *p
 	flush_dcache_mmap_unlock(mapping);
 }
 
+#if __LINUX_ARM_ARCH__ >= 6
+void __sync_icache_dcache(pte_t pteval)
+{
+	unsigned long pfn;
+	struct page *page;
+	struct address_space *mapping;
+
+	if (!pte_present_user(pteval))
+		return;
+	if (cache_is_vipt_nonaliasing() && !pte_exec(pteval))
+		/* only flush non-aliasing VIPT caches for exec mappings */
+		return;
+	pfn = pte_pfn(pteval);
+	if (!pfn_valid(pfn))
+		return;
+
+	page = pfn_to_page(pfn);
+	if (cache_is_vipt_aliasing())
+		mapping = page_mapping(page);
+	else
+		mapping = NULL;
+
+	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+		__flush_dcache_page(mapping, page);
+	/* pte_exec() already checked above for non-aliasing VIPT cache */
+	if (cache_is_vipt_nonaliasing() || pte_exec(pteval))
+		__flush_icache_all();
+}
+#endif
+
 /*
  * Ensure cache coherency between kernel mapping and userspace mapping
  * of this page.



From catalin.marinas at arm.com  Fri Jun 25 08:01:43 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 25 Jun 2010 13:01:43 +0100
Subject: [PATCH 3/3] ARM: Use lazy cache flushing on ARMv7 SMP systems
In-Reply-To: <20100625115826.30030.89790.stgit@e102109-lin.cambridge.arm.com>
References: <20100625115826.30030.89790.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100625120143.30030.35665.stgit@e102109-lin.cambridge.arm.com>

ARMv7 processors like Cortex-A9 broadcast the cache maintenance
operations in hardware. This patch allows the
flush_dcache_page/update_mmu_cache pair to work in lazy flushing mode
similar to the UP case.

Note that cache flushing on SMP systems now takes place via the
set_pte_at() call (__sync_icache_dcache) and there is no race with other
CPUs executing code from the new PTE before the cache flushing took
place.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Rabin Vincent <rabin.vincent at stericsson.com>
---
 arch/arm/include/asm/smp_plat.h |    4 ++++
 arch/arm/mm/flush.c             |   13 ++++---------
 2 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/smp_plat.h b/arch/arm/include/asm/smp_plat.h
index e621530..963a338 100644
--- a/arch/arm/include/asm/smp_plat.h
+++ b/arch/arm/include/asm/smp_plat.h
@@ -13,9 +13,13 @@ static inline int tlb_ops_need_broadcast(void)
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 2;
 }
 
+#if !defined(CONFIG_SMP) || __LINUX_ARM_ARCH__ >= 7
+#define cache_ops_need_broadcast()	0
+#else
 static inline int cache_ops_need_broadcast(void)
 {
 	return ((read_cpuid_ext(CPUID_EXT_MMFR3) >> 12) & 0xf) < 1;
 }
+#endif
 
 #endif
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 78134f5..53f83a7 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -17,6 +17,7 @@
 #include <asm/smp_plat.h>
 #include <asm/system.h>
 #include <asm/tlbflush.h>
+#include <asm/smp_plat.h>
 
 #include "mm.h"
 
@@ -93,12 +94,10 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
 #define flush_pfn_alias(pfn,vaddr)	do { } while (0)
 #endif
 
-#ifdef CONFIG_SMP
 static void flush_ptrace_access_other(void *args)
 {
 	__flush_icache_all();
 }
-#endif
 
 static
 void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
@@ -122,11 +121,9 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
 	if (vma->vm_flags & VM_EXEC) {
 		unsigned long addr = (unsigned long)kaddr;
 		__cpuc_coherent_kern_range(addr, addr + len);
-#ifdef CONFIG_SMP
 		if (cache_ops_need_broadcast())
 			smp_call_function(flush_ptrace_access_other,
 					  NULL, 1);
-#endif
 	}
 }
 
@@ -276,12 +273,10 @@ void flush_dcache_page(struct page *page)
 
 	mapping = page_mapping(page);
 
-#ifndef CONFIG_SMP
-	if (!PageHighMem(page) && mapping && !mapping_mapped(mapping))
+	if (!cache_ops_need_broadcast() &&
+	    !PageHighMem(page) && mapping && !mapping_mapped(mapping))
 		clear_bit(PG_dcache_clean, &page->flags);
-	else
-#endif
-	{
+	else {
 		__flush_dcache_page(mapping, page);
 		if (mapping && cache_is_vivt())
 			__flush_dcache_aliases(mapping, page);



From jason77.wang at gmail.com  Fri Jun 25 08:05:53 2010
From: jason77.wang at gmail.com (jason)
Date: Fri, 25 Jun 2010 20:05:53 +0800
Subject: [PATCH] spi/omap2_mcspi: disable and enable chan between each
	SPI transfer
In-Reply-To: <E1C7579D1379824DAE67858071C810382DD83846FB@NOK-EUMSG-02.mgdnok.nokia.com>
References: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com>
	<E1C7579D1379824DAE67858071C810382DD83846FB@NOK-EUMSG-02.mgdnok.nokia.com>
Message-ID: <4C249BA1.8010808@gmail.com>

roman.tereshonkov at nokia.com wrote:
>  
>
>   
[snip]
>> -----Original Message-----
>>
>> 					}
>> 					c = 0;
>> -				} else if (c == 0 && tx == NULL) {
>> -					omap2_mcspi_set_enable(spi, 0);
>> 				}
>>
>> 				*rx++ = __raw_readl(rx_reg);
>>     
>
> Why do you do this?
> Reading the last word from the shift register buffer leads to 
> the receiving new data to the buffer.
> The channel needs to be disabled before the last word reading.
>
>
>   
Yes, you are right. If this patch can be accepted, i will remove those 
changes in the V2 patch.
Please see my email replying grant likely's questions.

Thanks,
Jason.
>   
>> @@ -646,7 +641,7 @@ omap2_mcspi_txrx_pio(struct spi_device 
>> *spi, struct spi_transfer *xfer)
>> 			dev_err(&spi->dev, "EOT timed out\n");
>> 	}
>> out:
>> -	omap2_mcspi_set_enable(spi, 1);
>> +	omap2_mcspi_set_enable(spi, 0);
>> 	return count - c;
>> }
>>
>> @@ -894,7 +889,6 @@ static void omap2_mcspi_work(struct 
>> work_struct *work)
>> 		cs = spi->controller_state;
>> 		cd = spi->controller_data;
>>
>> -		omap2_mcspi_set_enable(spi, 1);
>> 		list_for_each_entry(t, &m->transfers, transfer_list) {
>> 			if (t->tx_buf == NULL && t->rx_buf == 
>> NULL && t->len) {
>> 				status = -EINVAL;
>> @@ -931,6 +925,8 @@ static void omap2_mcspi_work(struct 
>> work_struct *work)
>>
>> 			mcspi_write_chconf0(spi, chconf);
>>
>> +			omap2_mcspi_set_enable(spi, 1);
>> +
>> 			if (t->len) {
>> 				unsigned	count;
>>
>> -- 
>> 1.5.6.5
>>
>>
>>     



From lamiaposta71 at gmail.com  Fri Jun 25 04:03:46 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Fri, 25 Jun 2010 10:03:46 +0200
Subject: [PATCH] ASoC: DaVinci: Added support for stereo I2S
In-Reply-To: <1277326259.31686.57.camel@vega>
References: <1277303635-5675-1-git-send-email-lamiaposta71@gmail.com>
	<1277326259.31686.57.camel@vega>
Message-ID: <AANLkTinyQSbZm59JZvPvLVnJMELws1VAK7G5XRZyFFg_@mail.gmail.com>

Hi Liam,

2010/6/23 Liam Girdwood <lrg at slimlogic.co.uk>

> On Wed, 2010-06-23 at 16:33 +0200, Raffaele Recalcati wrote:
> > From: Raffaele Recalcati <raffaele.recalcati at bticino.it>
> >
> >       Added audio playback support with [frame sync master - clock
> master] mode
> >       and with [frame sync master - clock slave].
> >       Clock slave can be important when the external codec need system
> clock
> >       and bit clock synchronized.
> >       In the clock master case there is a FIXME message in the source
> code, because we
> >       (Davide and myself) have guessed a frequency of 122000000 that
> seems the base
> >       to be divided.
> >       This patch has been developed against the
> >
> http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
> >       git tree and has been tested on bmx board (similar to dm365 evm,
> but using
> >       uda1345 as external audio codec).
> >
> > Signed-off-by: Raffaele Recalcati <raffaele.recalcati at bticino.it>
> > Signed-off-by: Davide Bonfanti <davide.bonfanti at bticino.it>
>
> Had a quick check, it looks like you have made some unintended
> formatting changes that make the patch look more complex than necessary.
>

I was making correction for keeping aligned my lines like these...
+                       srgr = DAVINCI_MCBSP_SRGR_FSGM |
+                              DAVINCI_MCBSP_SRGR_CLKSM;

and so I changed some existing ones...
but looking at CodingStyle and Greg notes, seems that, when breaking lines,
we need to keep alignment.
So maybe, if I'm right, in the future, we'll need to re-align all the file
with another patch..
I'll change anyway the code back to be simpler to be understood.


>
> > ---
> >  arch/arm/mach-davinci/include/mach/asp.h |    7 ++
> >  sound/soc/davinci/davinci-i2s.c          |  141
> ++++++++++++++++++++++++++----
> >  2 files changed, 129 insertions(+), 19 deletions(-)
> >
> > diff --git a/arch/arm/mach-davinci/include/mach/asp.h
> b/arch/arm/mach-davinci/include/mach/asp.h
> > index 834725f..b1faeb9 100644
> > --- a/arch/arm/mach-davinci/include/mach/asp.h
> > +++ b/arch/arm/mach-davinci/include/mach/asp.h
> > @@ -63,6 +63,13 @@ struct snd_platform_data {
> >       unsigned sram_size_playback;
> >       unsigned sram_size_capture;
> >
> > +     /*
> > +      * This define works when both clock and FS are output for the cpu
> > +      * and makes clock very fast (FS is not simmetrical, but sampling
> > +      * frequency is better approximated
> > +      */
> > +     int i2s_fast_clock;
> > +
> >       /* McASP specific fields */
> >       int tdm_slots;
> >       u8 op_mode;
> > diff --git a/sound/soc/davinci/davinci-i2s.c
> b/sound/soc/davinci/davinci-i2s.c
> > index adadcd3..8811d25 100644
> > --- a/sound/soc/davinci/davinci-i2s.c
> > +++ b/sound/soc/davinci/davinci-i2s.c
> > @@ -68,16 +68,23 @@
> >  #define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16)
> >  #define DAVINCI_MCBSP_RCR_RFIG               (1 << 18)
> >  #define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21)
> > +#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24)
> > +#define DAVINCI_MCBSP_RCR_RPHASE             (1 << 31)
> >
> >  #define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5)
> >  #define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8)
> >  #define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16)
> >  #define DAVINCI_MCBSP_XCR_XFIG               (1 << 18)
> >  #define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21)
> > +#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24)
> > +#define DAVINCI_MCBSP_XCR_XPHASE     (1 << 31)
> >
> > +
> > +#define CLKGDV(v)                            (v)     /* Bits 0:7 */
>
> Should you not have a DAVINCI prefix here too ?
>

Sorry, CLKGDV was not more used.
So I'm deleting it in the new patch coming today.


>
> >  #define DAVINCI_MCBSP_SRGR_FWID(v)   ((v) << 8)
> >  #define DAVINCI_MCBSP_SRGR_FPER(v)   ((v) << 16)
> >  #define DAVINCI_MCBSP_SRGR_FSGM              (1 << 28)
> > +#define DAVINCI_MCBSP_SRGR_CLKSM     (1 << 29)
> >
> >  #define DAVINCI_MCBSP_PCR_CLKRP              (1 << 0)
> >  #define DAVINCI_MCBSP_PCR_CLKXP              (1 << 1)
> > @@ -144,8 +151,17 @@ struct davinci_mcbsp_dev {
> >        * won't end up being swapped because of the underrun.
> >        */
> >       unsigned enable_channel_combine:1;
> > +
> > +     int i2s_fast_clock;
> > +};
> > +
> > +struct davinci_mcbsp_data {
> > +     unsigned int    fmt;
> > +     int             clk_div;
> >  };
> >
> > +static struct davinci_mcbsp_data mcbsp_data;
> > +
>
> This struct should be part of the dai private data.
>

done.


>
> >  static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev
> *dev,
> >                                          int reg, u32 val)
> >  {
> > @@ -255,24 +271,27 @@ static int davinci_i2s_set_dai_fmt(struct
> snd_soc_dai *cpu_dai,
> >       unsigned int pcr;
> >       unsigned int srgr;
> >       srgr = DAVINCI_MCBSP_SRGR_FSGM |
> > -             DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
> > -             DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
> > +            DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
> > +            DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
> > +     /* Attention srgr is updated by hw_params! */
> >
> > +     mcbsp_data.fmt = fmt;
> >       /* set master/slave audio interface */
> >       switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
> > +     case SND_SOC_DAIFMT_CBS_CFM:
> >       case SND_SOC_DAIFMT_CBS_CFS:
> >               /* cpu is master */
> >               pcr = DAVINCI_MCBSP_PCR_FSXM |
> > -                     DAVINCI_MCBSP_PCR_FSRM |
> > -                     DAVINCI_MCBSP_PCR_CLKXM |
> > -                     DAVINCI_MCBSP_PCR_CLKRM;
> > +                   DAVINCI_MCBSP_PCR_FSRM |
> > +                   DAVINCI_MCBSP_PCR_CLKXM |
> > +                   DAVINCI_MCBSP_PCR_CLKRM;
> >               break;
> >       case SND_SOC_DAIFMT_CBM_CFS:
> >               /* McBSP CLKR pin is the input for the Sample Rate
> Generator.
> >                * McBSP FSR and FSX are driven by the Sample Rate
> Generator. */
> >               pcr = DAVINCI_MCBSP_PCR_SCLKME |
> > -                     DAVINCI_MCBSP_PCR_FSXM |
> > -                     DAVINCI_MCBSP_PCR_FSRM;
> > +                   DAVINCI_MCBSP_PCR_FSXM |
> > +                   DAVINCI_MCBSP_PCR_FSRM;
>
> These two just look like unintended formatting changes.
>

in next patch I'll remove these changes.


>
> >               break;
> >       case SND_SOC_DAIFMT_CBM_CFM:
> >               /* codec is master */
> > @@ -372,6 +391,17 @@ static int davinci_i2s_set_dai_fmt(struct
> snd_soc_dai *cpu_dai,
> >       return 0;
> >  }
> >
> > +static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
> > +                             int div_id, int div)
> > +{
> > +     struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
> > +     int srgr;
> > +
> > +     mcbsp_data.clk_div = div;
> > +     return 0;
> > +}
> > +
> > +
> >  static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
> >                                struct snd_pcm_hw_params *params,
> >                                struct snd_soc_dai *dai)
> > @@ -380,11 +410,12 @@ static int davinci_i2s_hw_params(struct
> snd_pcm_substream *substream,
> >       struct davinci_pcm_dma_params *dma_params =
> >
> &dev->dma_params[substream->stream];
> >       struct snd_interval *i = NULL;
> > -     int mcbsp_word_length;
> > -     unsigned int rcr, xcr, srgr;
> > +     int mcbsp_word_length, master;
> > +     unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
> >       u32 spcr;
> >       snd_pcm_format_t fmt;
> >       unsigned element_cnt = 1;
> > +     struct clk *clk;
> >
> >       /* general line settings */
> >       spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
> > @@ -396,12 +427,60 @@ static int davinci_i2s_hw_params(struct
> snd_pcm_substream *substream,
> >               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
> >       }
> >
> > -     i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
> > -     srgr = DAVINCI_MCBSP_SRGR_FSGM;
> > -     srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
> > +     master = mcbsp_data.fmt & SND_SOC_DAIFMT_MASTER_MASK;
> > +     fmt = params_format(params);
> > +     mcbsp_word_length = asp_word_length[fmt];
> >
> > -     i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
> > -     srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
> > +     if (master == SND_SOC_DAIFMT_CBS_CFS) {
> > +             clk = clk_get(NULL, "pll1_sysclk6");
> > +             if (clk)
> > +                     freq = clk_get_rate(clk);
> > +             freq = 122000000; /* FIXME ask to Texas */
>
> This frequency should either be passed in as platform data or by your
> machine driver calling snd_soc_dai_set_sysclk().
>

First I need to understand its meaning.
Reading sprufi3a-1.pdf (TMS320DM36x DMSoC Multichannel Buffered Serial Port
(McBSP) Interface) at "2.5.3 Data Clock Generation" paragraph this info not
appears really clear if we are in the case of "McBSP internal input clock".
I hope some Ti developer can help me.


> > +             if (dev->i2s_fast_clock) {
> > +                     clk_div = 256;
> > +                     do {
> > +                             framesize = (freq / (--clk_div)) /
> > +                                         params->rate_num *
> > +                                         params->rate_den;
> > +                     } while (((framesize < 33) || (framesize > 4095))
> &&
> > +                              (clk_div));
> > +                     clk_div--;
> > +                     srgr = DAVINCI_MCBSP_SRGR_FSGM |
> > +                            DAVINCI_MCBSP_SRGR_CLKSM;
> > +                     srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
> > +                                                     8 - 1);
> > +                     srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
> > +             } else {
> > +                     /* simmetric waveforms */
>
> symmetric
>

thx


>
> > +                     srgr = DAVINCI_MCBSP_SRGR_FSGM |
> > +                            DAVINCI_MCBSP_SRGR_CLKSM;
> > +                     srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
> > +                                                     8 - 1);
> > +                     srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
> > +                                                     16 - 1);
> > +                     clk_div = freq / (mcbsp_word_length * 16) /
> > +                               params->rate_num * params->rate_den;
> > +             }
> > +             clk_div &= 0xFF;
> > +             srgr |= clk_div;
> > +     } else if (master == SND_SOC_DAIFMT_CBS_CFM) {
> > +             /* Clock given on CLKS */
> > +             srgr = DAVINCI_MCBSP_SRGR_FSGM;
> > +             clk_div = mcbsp_data.clk_div - 1;
> > +             srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
> > +             srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 -
> 1);
> > +             clk_div &= 0xFF;
> > +             srgr |= clk_div;
> > +     } else {
> > +             i = hw_param_interval(params,
> SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
> > +             srgr = DAVINCI_MCBSP_SRGR_FSGM;
> > +             srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
> > +             pr_debug("%s - %d  FWID set: re-read srgr = %X\n",
> > +                     __func__, __LINE__, snd_interval_value(i) - 1);
> > +
> > +             i = hw_param_interval(params,
> SNDRV_PCM_HW_PARAM_FRAME_BITS);
> > +             srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
> > +     }
> >       davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
> >
> >       rcr = DAVINCI_MCBSP_RCR_RFIG;
> > @@ -426,22 +505,45 @@ static int davinci_i2s_hw_params(struct
> snd_pcm_substream *substream,
> >                       element_cnt = 1;
> >                       fmt = double_fmt[fmt];
> >               }
> > +             if (master == SND_SOC_DAIFMT_CBS_CFS ||
> > +                             master == SND_SOC_DAIFMT_CBS_CFM) {
> > +                     rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
> > +                     xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
> > +                     rcr |= DAVINCI_MCBSP_RCR_RPHASE;
> > +                     xcr |= DAVINCI_MCBSP_XCR_XPHASE;
> > +             } else {
> > +                     /* FIXME ask to Texas */
> > +                     rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
> > +                     xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
> > +             }
> >       }
> >       dma_params->acnt = dma_params->data_type = data_type[fmt];
> >       dma_params->fifo_level = 0;
> >       mcbsp_word_length = asp_word_length[fmt];
> > -     rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
> > -     xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
> > +
> > +     if (master == SND_SOC_DAIFMT_CBS_CFS ||
> > +                     master == SND_SOC_DAIFMT_CBS_CFM) {
> > +             rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
> > +             xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
> > +     } else {
> > +             /* FIXME ask to Texas */
> > +             rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
> > +             xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
> > +     }
> >
> >       rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
> > -             DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
> > +            DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
>
> more unintended formatting ?
>
> >       xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) |
> > -             DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
> > +            DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length);
>
> ditto
>


I'll remove these changes.



>
> >
> >       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
> >               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
> >       else
> >               davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
> > +
> > +     pr_debug("%s - %d  srgr=%X\n", __func__, __LINE__, srgr);
> > +     pr_debug("%s - %d  xcr=%X\n", __func__, __LINE__, xcr);
> > +     pr_debug("%s - %d  rcr=%X\n", __func__, __LINE__, rcr);
> >       return 0;
> >  }
> >
> > @@ -500,7 +602,7 @@ static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
> >       .trigger        = davinci_i2s_trigger,
> >       .hw_params      = davinci_i2s_hw_params,
> >       .set_fmt        = davinci_i2s_set_dai_fmt,
> > -
> > +     .set_clkdiv = davinci_i2s_dai_set_clkdiv,
>
> the formatting is different to rest of struct here.
>

ok. fixing


>
> >  };
> >
> >  struct snd_soc_dai davinci_i2s_dai = {
> > @@ -548,6 +650,7 @@ static int davinci_i2s_probe(struct platform_device
> *pdev)
> >       }
> >       if (pdata) {
> >               dev->enable_channel_combine =
> pdata->enable_channel_combine;
> > +             dev->i2s_fast_clock = pdata->i2s_fast_clock;
> >               dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size =
> >                       pdata->sram_size_playback;
> >               dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
>
> The subject of the patch looks wrong as I can't really see where you are
> adding stereo support to  the DAI. This patch looks likes it adds more
> clocking options only,
>

there are these supports added.

1. SND_SOC_DAIFMT_CBS_CFS (the cpu generates clock and frame sync)
I need to clarify how is clocked McBSP interface internally.
i2s_fast_clock switch can be used to have better approximate or symmetric
waveforms.

2. SND_SOC_DAIFMT_CBS_CFM (the cpu get clock from external pin and generates
frame sync)
this is important for uda1345.

3. We haven't changed the evmdm365 support (due also to CPLD that doesn't
help to understand)
We don't know in this mode if audio stereo works on evmdm365.
Probably it does.



> Thanks
>
> Liam
> --
> Freelance Developer, SlimLogic Ltd
> ASoC and Voltage Regulator Maintainer.
> http://www.slimlogic.co.uk
>
>

The better (I hope) patch we'll come today.

Bye,
Raffaele and Davide.
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From jpihet at mvista.com  Fri Jun 25 06:26:48 2010
From: jpihet at mvista.com (Jean Pihet)
Date: Fri, 25 Jun 2010 12:26:48 +0200
Subject: [PATCH 0/2] add perf-probe support on ARM
In-Reply-To: <1277285763-16213-1-git-send-email-will.deacon@arm.com>
References: <1277285763-16213-1-git-send-email-will.deacon@arm.com>
Message-ID: <AANLkTimU1W0feaSKyKCFHdZSG_RE6G_sFiAZ6jtU434w@mail.gmail.com>

Hi Will,

Are more tests needed for ARMv7 (OMAP3430/3530/3517)? I hope to find some
time to test it if required.

Regards,
Jean

On Wed, Jun 23, 2010 at 11:36, Will Deacon <will.deacon at arm.com> wrote:

> Perf-probe uses the KProbe events tracer to place and monitor probes
> on the running Kernel.
>
> This patch series adds both Kernel and tool support for this feature
> on ARM.
>
> Patches based on 2.6.35-rc3 [although perf record is currently broken
> on all architectures for probe tracepoints. These patches also apply
> cleanly to -tip/master where perf record works properly.]
>
> Cc: Jamie Iles <jamie.iles at picochip.com>
> Cc: Jean Pihet <jpihet at mvista.com>
>
> Will Deacon (2):
>  ARM: Add kprobe-based event tracer
>  ARM: perf probe: Add ARM DWARF register number mappings
>
>  arch/arm/Kconfig                      |    1 +
>  arch/arm/include/asm/ptrace.h         |   36 ++++++++++++
>  arch/arm/kernel/ptrace.c              |   96
> +++++++++++++++++++++++++++++++++
>  tools/perf/arch/arm/Makefile          |    4 ++
>  tools/perf/arch/arm/util/dwarf-regs.c |   64 ++++++++++++++++++++++
>  5 files changed, 201 insertions(+), 0 deletions(-)
>  create mode 100644 tools/perf/arch/arm/Makefile
>  create mode 100644 tools/perf/arch/arm/util/dwarf-regs.c
>
>
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From jason77.wang at gmail.com  Fri Jun 25 08:30:58 2010
From: jason77.wang at gmail.com (jason)
Date: Fri, 25 Jun 2010 20:30:58 +0800
Subject: [PATCH] spi/omap2_mcspi: disable and enable chan between each
	SPI 	transfer
In-Reply-To: <AANLkTin7mqe_zJIbyDcRPpCLaxPhl_dZQrSGua2z1nYW@mail.gmail.com>
References: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com>
	<AANLkTin7mqe_zJIbyDcRPpCLaxPhl_dZQrSGua2z1nYW@mail.gmail.com>
Message-ID: <4C24A182.4060009@gmail.com>

Grant Likely wrote:
> On Thu, Jun 24, 2010 at 6:12 AM, Jason Wang <jason77.wang at gmail.com> wrote:
>   
>> In current design, the SPI channel is always enable during the period
>> of handling a SPI message, it is risky when more than one SPI transfer
>> are included in a message. Current working route like that:
>> [
>>  SPI channel enable
>>  configure channel
>>  handle transfer #1
>>  configure channel
>>  handle transfer #2
>>  ...
>>  SPI channel disable
>> ]
>> If we can disable channel before configure it and reenable
>> channel after it is configured, it will be more safe.
>>
>> The commit a330ce2 "omap2_mcspi: Flush posted writes" make this risk
>> to a real problem for ads7846 driver on omap3530evm. The
>> ads7846 driver will send a SPI messge which includes,
>> [
>>  TX_ONLY transfer (1 byte)
>>  RX_ONLY transfer (2 bytes)
>>  TX_ONLY transfer (1 byte)
>>  RX_ONLY transfer (2 bytes)
>> ]
>> If we don't add disable/reenable channel between TX and RX transfers,
>> the RX transfer will get wrong datas sent from slave.
>>     
>
> I don't understand the problem description.  Are you talking about
> manipulation of the SS line, or a problem with the internal state on
> the mcspi controller device?  What is the cause of the wrong data (ie.
> is there a protocol error on the wire, or is the SPI controller not
> performing the read correctly?)
>
> Thanks,
> g.
>
>   
Sorry for unclear description.  The problem is like that, when a TX_ONLY 
transfer is
followed by a RX_ONLY transfer, the first data received in RX_ONLY 
transfer will be
the last data(random data) which is received in TX_ONLY transfer instead 
of a meaningful data.

Thing like following logic,
In TX_ONLY transfer:
write data1(trigger transmit), (will receive a data simultaneously, and 
keep it in RX register)
...
write dataN(last data), (will receive the last random data and keep it 
in RX register)
in the following RX_ONLY transfer:
change SPI controller to RX_ONLY mode,
the RXS bit will be set to status register immediately,
write a dummy data to TX register to trigger this session(in fact this  
trigger  doesn't take  effect),
check the RXS bit and read the first data(the first data is the last 
random data received in TX_ONLY transfer).


But if we disable this channel after the TX_ONLY  transfer and reenable 
it  before  the RX_ONLY  transfer,
the trigger action will take effect and a meaningful data  will be  
transfered to RX register.

Thanks,
Jason.

>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>> ---
>>  drivers/spi/omap2_mcspi.c |   16 ++++++----------
>>  1 files changed, 6 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>>     
[snip]


From catalin.marinas at arm.com  Fri Jun 25 08:36:03 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 25 Jun 2010 13:36:03 +0100
Subject: Heads up: Linus plans to kill ARM defconfigs
In-Reply-To: <201006090807.20810.post@hendrik-sattler.de>
References: <201006090807.20810.post@hendrik-sattler.de>
Message-ID: <1277469363.13134.22.camel@e102109-lin.cambridge.arm.com>

On Wed, 2010-06-09 at 07:07 +0100, Hendrik Sattler wrote:
> Am Mittwoch 09 Juni 2010, 01:21:24 schrieb Ryan Mallon:
> > Yes. I thought the problem was that Kconfig doesn't work correctly for
> > this though. Does having 'select MTD_PARTITIONS' automatically cause
> > CONFIG_MTD to be set? If not, then you basically need to have the full
> > config option list, which is basically what defconfig is.
> 
> Anybody thought about improving Kconfig to make this possible?
> Specifying CONFIG_MTD and CONFIG_MTD_PARTITIONS again and again will just
> repeat information (that CONFIG_MTD_PARTITIONS depends on CONFIG_MTD).
> The recursive 'select' could have a different name.

A first step is a warning when selecting options with unmet dependencies
- http://lkml.org/lkml/2010/6/8/191.

This could be extended to automatically select the dependencies but it
many cases it could just be a Kconfig error.

-- 
Catalin



From eric.y.miao at gmail.com  Fri Jun 25 08:50:31 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Fri, 25 Jun 2010 20:50:31 +0800
Subject: [RFC PATCH v2] preliminary support for sparse IRQ
In-Reply-To: <20100521194654.GH11042@n2100.arm.linux.org.uk>
References: <AANLkTikSXcn9nnvaVHAsoDPmLN30E_TjNVdXu1vCOH74@mail.gmail.com> 
	<20100520082853.GA18885@linux-sh.org>
	<20100521194654.GH11042@n2100.arm.linux.org.uk>
Message-ID: <AANLkTinjKNQ4cFkpJfL8IdamkN2HuVirkZdzFruchw6c@mail.gmail.com>

On Sat, May 22, 2010 at 3:46 AM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Thu, May 20, 2010 at 05:28:53PM +0900, Paul Mundt wrote:
>> On Tue, May 18, 2010 at 06:34:49PM +0800, Eric Miao wrote:
>> > commit 2e2e087d96630c95dbce57036680cf917e906cf1
>> > Author: Eric Miao <eric.y.miao at gmail.com>
>> > Date: ? Mon Dec 28 12:59:59 2009 +0800
>> >
>> > ? ? [ARM] preliminary support for sparse IRQ
>> >
>> > ? ? So to allow NR_IRQS to be dynamic and platforms to specify the number
>> > ? ? of IRQs really needed.
>> >
>> > ? ? Signed-off-by: Eric Miao <eric.y.miao at gmail.com>
>> >
>> It would be nice to see this applied, we plan to use sparseirq
>> unconditionally for shmobile (as sh already does).
>
> However, it's a little late in the day for patches for this merge
> window - which could be over as early as Sunday.
>
> However, if Eric wants to submit it to the patch system, I'll see
> about queuing it, but I can't make any promises that it'll get in.
>

Done, as patch #6197.

Russell,

Guess it's better to merge this into -devel-stable, so other patches can rebase?


From rogerio.pimentel at freescale.com  Fri Jun 25 09:31:33 2010
From: rogerio.pimentel at freescale.com (Rogerio Pimentel)
Date: Fri, 25 Jun 2010 10:31:33 -0300
Subject: [PATCH] mx27_3ds: add support for the keypad
Message-ID: <4C24AFB5.4090909@freescale.com>

mx27_3ds: add support for the keypad

Signed-off-by: Rogerio Pimentel <rogerio.pimentel at freescale.com>

---
On branch imx-for-2.6.35
  arch/arm/mach-mx2/mach-mx27_3ds.c |   23 +++++++++++++++++++++++
  1 files changed, 23 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx2/mach-mx27_3ds.c 
b/arch/arm/mach-mx2/mach-mx27_3ds.c
index b2f4e0d..411f0b4 100644
--- a/arch/arm/mach-mx2/mach-mx27_3ds.c
+++ b/arch/arm/mach-mx2/mach-mx27_3ds.c
@@ -20,6 +20,7 @@

  #include <linux/platform_device.h>
  #include <linux/gpio.h>
+#include <linux/input/matrix_keypad.h>
  #include <asm/mach-types.h>
  #include <asm/mach/arch.h>
  #include <asm/mach/time.h>
@@ -58,6 +59,27 @@ static unsigned int mx27pdk_pins[] = {
      PF23_AIN_FEC_TX_EN,
  };

+/*
+ * Matrix keyboard
+ */
+
+static const uint32_t mx27_3ds_keymap[] = {
+    KEY(0, 0, KEY_UP),
+    KEY(0, 1, KEY_DOWN),
+    KEY(1, 0, KEY_RIGHT),
+    KEY(1, 1, KEY_LEFT),
+    KEY(1, 2, KEY_ENTER),
+    KEY(2, 0, KEY_F6),
+    KEY(2, 1, KEY_F8),
+    KEY(2, 2, KEY_F9),
+    KEY(2, 3, KEY_F10),
+};
+
+static struct matrix_keymap_data mx27_3ds_keymap_data = {
+    .keymap        = mx27_3ds_keymap,
+    .keymap_size    = ARRAY_SIZE(mx27_3ds_keymap),
+};
+
  static struct imxuart_platform_data uart_pdata = {
      .flags = IMXUART_HAVE_RTSCTS,
  };
@@ -71,6 +93,7 @@ static void __init mx27pdk_init(void)
      mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
          "mx27pdk");
      mxc_register_device(&mxc_uart_device0, &uart_pdata);
+    mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
      platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  }

-- 
1.7.0.4



From philippe.langlais at stericsson.com  Fri Jun 25 09:34:47 2010
From: philippe.langlais at stericsson.com (Philippe Langlais)
Date: Fri, 25 Jun 2010 15:34:47 +0200
Subject: [PATCH 1/6] U6/U6715 ARM architecture files
In-Reply-To: <20100624140825.GA6523@n2100.arm.linux.org.uk>
References: <1274948852-9179-1-git-send-email-philippe.langlais@stericsson.com>
	<1274948852-9179-2-git-send-email-philippe.langlais@stericsson.com>
	<20100624140825.GA6523@n2100.arm.linux.org.uk>
Message-ID: <4C24B077.9020909@stericsson.com>

Hi,
Many thanks for your comments.

On 06/24/10 16:08, Russell King - ARM Linux wrote:
> On Thu, May 27, 2010 at 10:27:27AM +0200, Philippe Langlais wrote:
>    
>> diff --git a/arch/arm/mach-u67xx/devices.c b/arch/arm/mach-u67xx/devices.c
>> new file mode 100644
>> index 0000000..0ead380
>> --- /dev/null
>> +++ b/arch/arm/mach-u67xx/devices.c
>> @@ -0,0 +1,95 @@
>> +/*
>> + * linux/arch/arm/mach-u67xx/devices.c
>> + *
>> + * Copyright (C) ST-Ericsson SA 2010
>> + * Author: Philippe Langlais<philippe.langlais at stericsson.com>  for ST-Ericsson.
>> + * License terms:  GNU General Public License (GPL), version 2
>> + *
>> + * Device specification for the U67XX
>> + */
>> +
>> +#include<linux/kernel.h>
>> +#include<linux/init.h>
>> +#include<linux/device.h>
>> +#include<linux/ioport.h>
>> +#include<linux/platform_device.h>
>> +#include<linux/fs.h>
>> +#include<mach/hardware.h>
>> +#include<mach/scon.h>
>> +#include<mach/gpio.h>
>>      
> linux/gpio.h
>
>    
>> +struct gpio_bank u6_gpio_bank[6] = {
>> +     {(void __iomem *)GPIOA_PINS_REG, (void __iomem *)SCON_SYSMUX0_REG},
>> +     {(void __iomem *)GPIOB_PINS_REG, (void __iomem *)SCON_SYSMUX2_REG},
>> +     {(void __iomem *)GPIOC_PINS_REG, (void __iomem *)SCON_SYSMUX4_REG},
>> +     {(void __iomem *)GPIOD_PINS_REG, (void __iomem *)SCON_SYSMUX6_REG},
>> +     {(void __iomem *)GPIOE_PINS_REG, (void __iomem *)SCON_SYSMUX8_REG},
>> +     {(void __iomem *)GPIOF_PINS_REG, (void __iomem *)SCON_SYSMUX10_REG},
>>      
> Would be nice to get rid of these casts - instead moving them to the
> point of definition instead - or maybe doing as other platforms do and
> defining an IOMEM() macro which does the cast and using that in the
> definitions.
>
> iow, something like:
>
> #define IOMEM(x)        ((void __iomem *)(x))
>
> #define GPIOA_PINS_REG  IOMEM(whatever)
>
> and if you need GPIOA_PINS_REG to be usable in assembly, arrange for
> the IOMEM() macro to handle that for you.
>
>    
OK, it's already done in PATCH 5/6, I made a mistake at patch build.
I'll delete GPIO stuff from this patch.
>> diff --git a/arch/arm/plat-u6xxx/include/mach/entry-macro.S b/arch/arm/plat-u6xxx/include/mach/entry-macro.S
>> new file mode 100644
>> index 0000000..59bb2d2
>> --- /dev/null
>> +++ b/arch/arm/plat-u6xxx/include/mach/entry-macro.S
>> @@ -0,0 +1,32 @@
>> +/*
>> + * linux/arch/arm/plat-u6xxx/include/mach/entry-macro.S
>> + *
>> + * Low-level IRQ helper macros for U6-based platforms
>> + * Copyright (C) ST-Ericsson SA 2010
>> + *
>> + * This file is licensed under  the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +#include<mach/hardware.h>
>> +#include<mach/irqs.h>
>> +
>> +     .macro  arch_ret_to_user, tmp1, tmp2
>> +     .endm
>> +
>> +     .macro  disable_fiq
>> +     .endm
>> +
>> +     .macro  get_irqnr_preamble, base, tmp
>> +     .endm
>>      
> This macro is there to allow you to be a little more efficient - rather
> than reloading the base address of the interrupt controller each time
> around the interrupt handling loop, you can put it in the above macro
> to take it outside the loop.
>
>    
OK
>> +#define hw_raw_local_irq_save       raw_local_irq_save
>> +#define hw_raw_local_irq_restore    raw_local_irq_restore
>>      
> What's the purpose of these additional aliases?
>
>    
Necessary for our para-virtualized drivers, but not for normal kernel usage.
Will be removed.
>> +/* INTC PRIOMASK_IRQ Register (32 bits) */
>> +#define INTC_PRIOMASK_IRQ_OFFSET 0x0
>> +#define INTC_PRIOMASK_IRQ_REG  IO_ADDRESS(INTC_BASE + INTC_PRIOMASK_IRQ_OFFSET)
>> +
>> +/* INTC PRIOMASK_FIQ Register (32 bits) */
>> +#define INTC_PRIOMASK_FIQ_OFFSET 0x4
>> +#define INTC_PRIOMASK_FIQ_REG  IO_ADDRESS(INTC_BASE + INTC_PRIOMASK_FIQ_OFFSET)
>> +
>> +/* INTC VECTOR_IRQ Register (32 bits) */
>> +#define INTC_VECTOR_IRQ_OFFSET   0x100
>> +#define INTC_VECTOR_IRQ_REG      IO_ADDRESS(INTC_BASE + INTC_VECTOR_IRQ_OFFSET)
>> +
>> +/* INTC VECTOR_FIQ Register (32 bits) */
>> +#define INTC_VECTOR_FIQ_OFFSET   0x104
>> +#define INTC_VECTOR_FIQ_REG      IO_ADDRESS(INTC_BASE + INTC_VECTOR_FIQ_OFFSET)
>> +
>> +/* INTC PENDING_* Registers (32 bits) */
>> +#define INTC_PENDING_1_OFFSET    0x200
>> +#define INTC_PENDING_2_OFFSET    0x204
>> +#define INTC_PENDING_3_OFFSET    0x208
>> +#define INTC_FEATURES_OFFSET     0x300
>> +
>> +/* INTC REQUEST 64 Registers (32 bits) */
>> +#define INTC_REQUEST1_OFFSET     0x404
>> +#define INTC_REQUEST64_OFFSET    0x500
>> +
>> +/* INTC MOD_ID Register (32 bits) */
>> +#define INTC_MOD_ID_OFFSET       0xFFC
>> +
>> +/* interrupt x [1..64] request configuration */
>> +#define INTC_REQUESTx(x)  IO_ADDRESS(INTC_BASE+INTC_REQUEST1_OFFSET+(x-1)*4)
>> +
>> +/* EXTINTx [0..23] configuration register */
>> +#define EXTINT_CFGx(x)    IO_ADDRESS(EXTINT_BASE+(x)*4)
>>      
> Does it really make sense to export all these definitions to the entire
> kernel?
>
>    
I'll try to move it into plat-u6xxx/irq.c
>> diff --git a/arch/arm/plat-u6xxx/include/mach/memory.h b/arch/arm/plat-u6xxx/include/mach/memory.h
>> new file mode 100644
>> index 0000000..0fa6cea
>> --- /dev/null
>> +++ b/arch/arm/plat-u6xxx/include/mach/memory.h
>> @@ -0,0 +1,24 @@
>> +/*
>> + * linux/arch/arm/plat-u6xxx/include/mach/memory.h
>> + *
>> + * Copyright (C) ST-Ericsson SA 2010
>> + * Author: Philippe Langlais<philippe.langlais at stericsson.com>  for ST-Ericsson.
>> + * License terms:  GNU General Public License (GPL), version 2
>> + */
>> +
>> +#ifndef __ASM_ARCH_MEMORY_H
>> +#define __ASM_ARCH_MEMORY_H
>> +
>> +/*
>> + * Physical DRAM offset.
>> + */
>> +#define PHYS_OFFSET          UL(0x20000000)
>> +#define BOOT_PARAMS_OFFSET   (PHYS_OFFSET + 0x100)
>>      
> Does it make sense to export this to the world?
>    
I take our U300 as example, but I can change that.
>> +
>> +/**
>> + * CONSISTENT_DMA_SIZE: Size of DMA-consistent memory region.
>> + * Must be multiple of 2M,between 2MB and 14MB inclusive
>> + */
>> +#define CONSISTENT_DMA_SIZE (SZ_2M)
>>      
> It defaults to 2MB, so this definition is redundant.
>
>    
OK, no problem
>> diff --git a/arch/arm/plat-u6xxx/include/mach/platform.h b/arch/arm/plat-u6xxx/include/mach/platform.h
>> new file mode 100644
>> index 0000000..5265ccd
>> --- /dev/null
>> +++ b/arch/arm/plat-u6xxx/include/mach/platform.h
>> @@ -0,0 +1,15 @@
>> +/*
>> + * linux/arch/arm/plat-u6xxx/include/mach/platform.h
>> + *
>> + * Copyright (C) ST-Ericsson SA 2010
>> + * Author: Philippe Langlais<philippe.langlais at stericsson.com>  for ST-Ericsson.
>> + * License terms:  GNU General Public License (GPL), version 2
>> + */
>> +
>> +#ifndef __ASM_ARCH_PLATFORM_H
>> +#define __ASM_ARCH_PLATFORM_H                     1
>> +
>> +#include<linux/types.h>
>> +#include<mach/hardware.h>
>> +
>> +#endif  /* __ASM_ARCH_PLATFORM_H */
>>      
> If there's nothing required in this file, it doesn't need to exist.
>
>    
OK
>> diff --git a/arch/arm/plat-u6xxx/include/mach/timer.h b/arch/arm/plat-u6xxx/include/mach/timer.h
>> new file mode 100644
>> index 0000000..049e72d
>> --- /dev/null
>> +++ b/arch/arm/plat-u6xxx/include/mach/timer.h
>> @@ -0,0 +1,24 @@
>> +/*
>> + *  linux/arch/arm/plat-u6xxx/include/mach/timer.h
>> + *
>> + * Copyright (C) ST-Ericsson SA 2010
>> + * Author: Philippe Langlais<philippe.langlais at stericsson.com>  for ST-Ericsson.
>> + * License terms:  GNU General Public License (GPL), version 2
>> + */
>> +
>> +#ifndef __PLAT_TIMER_H
>> +#define __PLAT_TIMER_H
>> +#ifdef U6_TIMER_C
>> +#define PUBLIC
>> +#else
>> +#define PUBLIC extern
>> +#endif
>>      
> Err, no - there's really no need for such hacks in C, and I can't find
> anywhere which defines U6_TIMER_C.
>
>    
OK
>> +
>> +struct sys_timer;
>> +
>> +PUBLIC struct sys_timer u6_timer;
>> +
>> +PUBLIC void __init u6_timer_init(void);
>> +
>> +#undef PUBLIC
>> +#endif
>>      
>    
>> diff --git a/arch/arm/plat-u6xxx/include/mach/vmalloc.h b/arch/arm/plat-u6xxx/include/mach/vmalloc.h
>> new file mode 100644
>> index 0000000..583033f
>> --- /dev/null
>> +++ b/arch/arm/plat-u6xxx/include/mach/vmalloc.h
>> @@ -0,0 +1,10 @@
>> +/*
>> + * linux/arch/arm/plat-u6/include/mach/vmalloc.h
>> + * Copyright (C) ST-Ericsson SA 2010
>> + * Author: Philippe Langlais<philippe.langlais at stericsson.com>  for ST-Ericsson.
>> + * License terms:  GNU General Public License (GPL), version 2
>> + *
>> + * Virtual memory allocations
>> + * End must be above the I/O registers and on an even 2MiB boundary.
>> + */
>> +#define VMALLOC_END       (PAGE_OFFSET + 0x28000000)
>>      
> Is the upper limit of vmalloc space is dependent on PAGE_OFFSET?  If
> not, then it shouldn't be using a calculation based upon that value.
>
>    
OK
>> diff --git a/arch/arm/plat-u6xxx/timer.c b/arch/arm/plat-u6xxx/timer.c
>> new file mode 100644
>> index 0000000..62f13f5
>> --- /dev/null
>> +++ b/arch/arm/plat-u6xxx/timer.c
>> @@ -0,0 +1,679 @@
>> +/*
>> + * linux/arch/arm/plat-u6xxx/timer.c
>> + *
>> + * Copyright (C) ST-Ericsson SA 2010
>> + * Author: Vincent Guittot<vincent.guittot at stericsson.com>  for ST-Ericsson.
>> + * License terms:  GNU General Public License (GPL), version 2
>> + */
>> +
>> +#include<linux/types.h>
>> +#include<linux/kernel.h>
>> +#include<linux/err.h>
>> +#include<linux/init.h>
>> +#include<linux/io.h>
>> +
>> +#include<asm/mach/time.h>
>> +
>> +#include<mach/hardware.h>
>> +
>> +#include<asm/mach/irq.h>
>> +#include<linux/interrupt.h>
>> +#include<mach/irqs.h>
>> +
>> +#include<linux/clk.h>
>> +
>> +#include<linux/clocksource.h>
>> +#include<linux/clockchips.h>
>>      
> linux/ includes before asm/ includes.  asm/ includes before mach/ includes
> please.
>
>    
OK
>> +#undef U6_TIMER_DEBUG
>> +#if defined(U6_TIMER_DEBUG)
>> +#define debug(fmt, args...)                                          \
>> +     printk(PKMOD fmt, ## args)
>> +#else
>> +#define debug(fmt, args...)
>> +#endif
>>      
> You could use pr_debug() instead, and define 'DEBUG' at the top of the
> file you want debug messages from.
>    
OK
>    
>> +static irqreturn_t
>> +u6_mmtu_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
>> +{
>> +     uint8_t status, enable;
>> +     struct mmtu_ctxt *mmtu;
>> +
>> +     mmtu = u6_mmtu_get_context(0);
>> +
>> +     status = readl((mmtu->base + MMTU_INT_OFFSET + MMTU_INT_STATUS_IDX));
>> +     enable = readl((mmtu->base + MMTU_INT_OFFSET + MMTU_INT_ENABLE_IDX));
>> +
>> +     debug("mmtu_timer_interrupt %d\n", status);
>> +
>> +     if (status&  enable&  MMTU_IRQ_MASK) {
>> +             struct clock_event_device *evt =&clockevent_mmtu;
>> +
>> +             writel(MMTU_IRQ_MASK, (mmtu->base + MMTU_INT_OFFSET
>> +                                     + MMTU_INT_CLR_STAT_IDX));
>> +
>> +             if (mmtu->autoreload)
>> +                     u6_mmtu_timer_start(mmtu->compvalue, 0);
>>      
> If your hardware doesn't do reloadable timers, you're not supposed to
> emulate it.  The generic time infrastructure contains all the code
> that's required to handle periodic timer interrupts with timers only
> capable of one-shot mode.
>
>    
We removed this code and it's works => OK
>    
>> +             else
>> +                     writel(MMTU_IRQ_MASK,
>> +                            (mmtu->base + MMTU_INT_OFFSET +
>> +                             MMTU_INT_CLR_ENA_IDX));
>> +
>> +             if (evt->event_handler)
>> +                     evt->event_handler(evt);
>> +     }
>> +     return IRQ_HANDLED;
>> +}
>> +
>> +static struct irqaction u6_mmtu_timer_irq = {
>> +     .name = "U6 MMTU timer Tick",
>> +     .flags = IRQF_DISABLED,
>> +     .handler = (irq_handler_t) u6_mmtu_timer_interrupt,
>> +};
>> +
>> +static inline void u6_mmtu_clk_enable(int id)
>> +{
>> +     struct mmtu_ctxt *mmtu = u6_mmtu_get_context(id);
>> +
>> +     /* Clock Multimedia Timer Unit.
>> +      */
>> +     if ((mmtu->clk != NULL)&&  (mmtu->mode == 0)) {
>> +             debug("mmtu_clk_enable\n");
>> +             mmtu->mode = 1;
>> +             clk_enable(mmtu->clk);
>> +     }
>> +}
>> +
>> +static inline void u6_mmtu_clk_disable(int id)
>> +{
>> +     struct mmtu_ctxt *mmtu = u6_mmtu_get_context(id);
>> +
>> +     /* Clock Multimedia Timer Unit.
>> +      */
>> +     if ((mmtu->clk != NULL)&&  (mmtu->mode == 1)) {
>> +             debug("mmtu_clk_disable\n");
>> +             clk_disable(mmtu->clk);
>> +             mmtu->mode = 0;
>> +     }
>> +}
>> +
>> +static inline int u6_mmtu_timer_start(unsigned long cycles, int id)
>> +{
>> +     struct mmtu_ctxt *mmtu = u6_mmtu_get_context(id);
>> +
>> +     debug("mmtu_timer_start %d\n", cycles);
>> +     u6_mmtu_clk_enable(id);
>> +
>> +     /* MMTU limitation : can't set a value smaller or equal to tcval + 1 */
>> +     cycles = cycles<  2 ? 2 : cycles;
>> +
>> +     mmtu->compvalue = cycles;
>> +
>> +     mmtu->endvalue = mmtu->compvalue
>> +             + readl((mmtu->base + MMTU_TCVAL_IDX));
>> +
>> +     writel(MMTU_IRQ_MASK,
>> +            (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_STAT_IDX));
>> +
>> +     writel(mmtu->endvalue, (mmtu->base + MMTU_USED_MATCH_IDX));
>> +
>> +     writel(MMTU_IRQ_MASK,
>> +            (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_SET_ENA_IDX));
>> +
>> +     /* the value has already expired */
>> +     if ((mmtu->endvalue<= readl((mmtu->base + MMTU_TCVAL_IDX)))
>> +&&  (mmtu->endvalue>  mmtu->compvalue)
>> +&&  !(readl((mmtu->base + MMTU_INT_OFFSET
>> +                                 + MMTU_INT_STATUS_IDX))&  MMTU_IRQ_MASK))
>> +             writel(MMTU_IRQ_MASK, (mmtu->base + MMTU_INT_OFFSET
>> +                                     + MMTU_INT_SET_STAT_IDX));
>> +
>> +     return 0;
>> +}
>> +
>> +static int u6_mmtu_timer_init(int id, unsigned long reload,
>> +                          unsigned long prescale, int over_it)
>> +{
>> +
>> +     struct mmtu_ctxt *mmtu = u6_mmtu_get_context(id);
>> +
>> +     debug("mmtu_timer_init %d\n", id);
>> +
>> +     /* Enable clock */
>> +/*
>> +     u6_mmtu_clk_enable(id);
>> +     clk mngt not available yet
>> +     directly enable it
>> +*/
>> +     {
>> +             unsigned long flags;
>> +             unsigned long reg;
>> +             hw_raw_local_irq_save(flags);
>> +             reg = readl(CGU_GATESC2_REG);
>> +             reg |= 0x1<<  2;
>> +             writel(reg, CGU_GATESC2_REG);
>> +             hw_raw_local_irq_restore(flags);
>> +     }
>> +
>> +     /* Reset timer */
>> +     /* reset control register */
>> +     writel(0x0000, (mmtu->base + MMTU_CON_IDX));
>> +     writel(0x0002, (mmtu->base + MMTU_CON_IDX));
>> +     /* reset control register */
>> +     writel(0x0000, (mmtu->base + MMTU_CON_IDX));
>> +
>> +     /* clear whole enable irq register */
>> +     writel(0xFF, (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_ENA_IDX));
>> +     /* clear whole status register */
>> +     writel(0xFF, (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_STAT_IDX));
>> +
>> +     /* reset pre-scaler reload register */
>> +     writel(0x00000000, (mmtu->base + MMTU_PRESCALER_IDX));
>> +
>> +     /* reset match control register */
>> +     writel(0x0000, (mmtu->base + MMTU_MATCH_CON_IDX));
>> +     /* reset match 0 register */
>> +     writel(0x00000000, (mmtu->base + MMTU_MATCH0_IDX));
>> +     /* reset match 1 register */
>> +     writel(0x00000000, (mmtu->base + MMTU_MATCH1_IDX));
>> +
>> +     /* Initialize timer */
>> +     writel(prescale - 1, (mmtu->base + MMTU_PRESCALER_IDX));
>> +     /* power of 2 system clock */
>> +     writel(reload, (mmtu->base + MMTU_MATCH0_IDX));
>> +
>> +     /* enable counter register */
>> +     writel(0x0001, (mmtu->base + MMTU_CON_IDX));
>> +
>> +     /* clear whole status register */
>> +     writel(0xFF, (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_STAT_IDX));
>> +
>> +     if (id == 0)
>> +             setup_irq(IRQ_MMTU,&u6_mmtu_timer_irq);
>> +
>> +     /* Disable clock */
>> +#ifndef U6_MMTU_CLOCK_SOURCE
>> +     u6_mmtu_clk_disable(id);
>> +#endif
>> +     return 0;
>> +}
>> +
>> +/*** MMTU Clock event device ***/
>> +
>> +static int u6_mmtu_set_next_event(unsigned long cycles,
>> +                              struct clock_event_device *evt)
>> +{
>> +     debug("mmtu_set_next_event %d\n", cycles);
>> +     u6_mmtu_timer_start(cycles, 0);
>> +
>> +     return 0;
>> +}
>> +
>> +static void u6_mmtu_set_mode(enum clock_event_mode mode,
>> +                         struct clock_event_device *evt)
>> +{
>> +     struct mmtu_ctxt *mmtu = u6_mmtu_get_context(0);
>> +     unsigned long reg;
>> +
>> +     debug("mmtu_set_mode %d\n", mode);
>> +
>> +     switch (mode) {
>> +     case CLOCK_EVT_MODE_UNUSED:
>> +             writel(MMTU_IRQ_MASK,
>> +                    (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_ENA_IDX));
>> +             writel(MMTU_IRQ_MASK,
>> +                    (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_STAT_IDX));
>> +
>> +             reg = readl((mmtu->base + MMTU_TCVAL_IDX));
>> +             writel(reg - 1, (mmtu->base + MMTU_USED_MATCH_IDX));
>> +
>> +#ifndef U6_MMTU_CLOCK_SOURCE
>> +             u6_mmtu_clk_disable(0);
>> +
>> +             if (mmtu->clk != NULL)
>> +                     clk_put(mmtu->clk);
>> +#endif
>> +             mmtu->autoreload = 0;
>> +             break;
>> +     case CLOCK_EVT_MODE_SHUTDOWN:
>> +             mmtu->autoreload = 0;
>> +
>> +             if (mmtu->clk == NULL) {
>> +                     mmtu->clk = clk_get(0, "MMTU");
>> +                     if (IS_ERR(mmtu->clk))
>> +                             mmtu->clk = NULL;
>> +             }
>> +
>> +             writel(MMTU_IRQ_MASK,
>> +                    (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_CLR_STAT_IDX));
>> +             writel(MMTU_IRQ_MASK,
>> +                    (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_SET_ENA_IDX));
>> +     case CLOCK_EVT_MODE_ONESHOT:
>> +     case CLOCK_EVT_MODE_RESUME:
>> +             mmtu->autoreload = 0;
>> +             break;
>> +     case CLOCK_EVT_MODE_PERIODIC:
>> +             writel(MMTU_IRQ_MASK,
>> +                    (mmtu->base + MMTU_INT_OFFSET + MMTU_INT_SET_ENA_IDX));
>> +             mmtu->autoreload = 1;
>> +             break;
>> +     }
>> +}
>> +
>> +static void u6_clockevent_init_mmtu(void)
>> +{
>> +     printk(PKMOD "clockevent_init_mmtu\n");
>> +
>> +     /* prescale 13Mhz ->  1Mhz */
>> +#ifndef U6_MMTU_CLOCK_SOURCE
>> +     u6_mmtu_timer_init(0, 0, (MMTU_SYS_FRQ / MMTU_ROOT_FRQ), 0);
>> +#endif
>> +
>> +/* issue it is shorter than reality and generates spurious irq */
>> +/*      clockevent_mmtu.mult = div_sc(MMTU_ROOT_FRQ, NSEC_PER_SEC,
>> + *      clockevent_mmtu.shift) + 1;*/
>> +     clockevent_mmtu.mult =
>> +         div_sc(MMTU_ROOT_FRQ, NSEC_PER_SEC, clockevent_mmtu.shift);
>> +
>> +/*      clockevent_mmtu.max_delta_ns = div_sc(RELOAD_COUNTER_MMTU,
>> + *      clockevent_mmtu.mult, clockevent_mmtu.shift);*/
>> +/*  In fact it is wider than the 32bits variable !!! */
>> +     clockevent_mmtu.max_delta_ns = 0xFFFFFFFF;
>> +
>> +/*  MMTU HW limitation: match register can't be set w/ tcval+1 */
>> +/*      clockevent_mmtu.min_delta_ns = div_sc(1, clockevent_mmtu.mult,
>> + *      clockevent_mmtu.shift)+1;*/
>> +     clockevent_mmtu.min_delta_ns =
>> +         div_sc(2, clockevent_mmtu.mult, clockevent_mmtu.shift) + 1;
>> +     /* avoid to much timer interrupt with 10us min between 2 irq */
>> +     if (clockevent_mmtu.min_delta_ns<  10000)
>> +             clockevent_mmtu.min_delta_ns = 10000;
>> +     else if (clockevent_mmtu.max_delta_ns<  10000)
>> +             clockevent_mmtu.min_delta_ns = clockevent_mmtu.max_delta_ns>>1;
>> +
>> +     clockevent_mmtu.cpumask = get_cpu_mask(0);
>> +     clockevents_register_device(&clockevent_mmtu);
>> +
>> +     u6_mmtu_set_next_event(MMTU_ROOT_FRQ / HZ,&clockevent_mmtu);
>> +}
>> +
>> +/*** MMTU Clock source device ***/
>> +#ifdef U6_MMTU_CLOCK_SOURCE
>> +
>> +static cycle_t u6_mmtu_read(struct clocksource *source)
>> +{
>> +     struct mmtu_ctxt *mmtu = u6_mmtu_get_context(0);
>> +
>> +     return readl((mmtu->base + MMTU_TCVAL_IDX))&  source->mask;
>> +}
>>      
> Clocksource read functions don't require the value masking.
>    
OK
>    
>> +
>> +static void u6_clocksource_init_mmtu(void)
>> +{
>> +     printk(PKMOD "clocksource_init_mmtu\n");
>> +
>> +     if (MMTU_ROOT_FRQ>= 1000000)
>> +             clocksource_mmtu.mult =
>> +                 clocksource_khz2mult((MMTU_ROOT_FRQ / 1000),
>> +                                      clocksource_mmtu.shift);
>> +     else
>> +             clocksource_mmtu.mult = clocksource_hz2mult((MMTU_ROOT_FRQ),
>> +                             clocksource_mmtu.shift);
>> +
>> +     u6_mmtu_timer_init(0, 0, (MMTU_SYS_FRQ / MMTU_ROOT_FRQ), 0);
>> +
>> +     clocksource_register(&clocksource_mmtu);
>> +}
>> +
>> +unsigned long long u6_mmtu_time(void)
>> +{
>> +     unsigned long long ticks64 = u6_mmtu_read(&clocksource_mmtu);
>> +
>> +     return (ticks64 * clocksource_mmtu.mult)>>  clocksource_mmtu.shift;
>> +}
>>      
> Can you explain the purpose of this function please, and why you export
> the ticks and value from this function via sysfs?
>    
It's for debug purpose, can be removed for standard kernel.
>    
>> +#endif
>> +
>> +/*** SysFs interface ***/
>> +/***********************/
>> +#ifdef CONFIG_U6_POWER_SYSFS
>> +
>> +/*** Clock event sysfs interface **/
>> +
>> +#define shows_one_evt(file_name, object)                             \
>> +static ssize_t show_##file_name##_evt                                        \
>> +(struct kobject *kobj, char *buf)                            \
>> +{                                                                    \
>> +     return sprintf(buf, "%s\n", clockevent_mmtu.object);            \
>> +}
>> +
>> +#define showu_one_evt(file_name, object)                             \
>> +static ssize_t show_##file_name##_evt                                        \
>> +(struct kobject *kobj, char *buf)                            \
>> +{                                                                    \
>> +     return sprintf(buf, "%u\n", clockevent_mmtu.object);            \
>> +}
>> +
>> +#define showlu_one_evt(file_name, object)                            \
>> +static ssize_t show_##file_name##_evt                                        \
>> +(struct kobject *kobj, char *buf)                            \
>> +{                                                                    \
>> +     return sprintf(buf, "%lu\n", clockevent_mmtu.object);           \
>> +}
>> +
>> +#define storelu_one_evt(file_name, object)                           \
>> +static ssize_t store_##file_name##_evt                                       \
>> +(struct kobject *kobj, const char *buf, size_t size)                 \
>> +{                                                                    \
>> +     unsigned long object; \
>> +     strict_strtoul(buf, 10,&object); \
>> +     clockevent_mmtu.object = object; \
>> +     return size;            \
>> +}
>> +
>> +#define showx_one_evt(file_name, object)                             \
>> +static ssize_t show_##file_name##_evt                                        \
>> +(struct kobject *kobj, char *buf)                            \
>> +{                                                                    \
>> +     return sprintf(buf, "0x%x\n", clockevent_mmtu.object);          \
>> +}
>> +
>> +shows_one_evt(name, name);
>> +showu_one_evt(rating, rating);
>> +showlu_one_evt(mult, mult);
>> +#ifdef CONFIG_U6_TIMER_TUNE
>> +storelu_one_evt(mult, mult);
>> +#endif
>> +showu_one_evt(shift, shift);
>> +showx_one_evt(features, features);
>> +showlu_one_evt(min_delta_ns, min_delta_ns);
>> +showlu_one_evt(max_delta_ns, max_delta_ns);
>>      
> Why do you want all these parameters exported to userspace?  Maybe you
> should discuss your requirement here with the generic time people
> before submitting it?
>    
For debug only => removed all


I'll fix this patch next week and send it to the list.

Regards,
Philippe



From catalin.marinas at arm.com  Fri Jun 25 09:39:40 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 25 Jun 2010 14:39:40 +0100
Subject: strange segfaults with CompactFlash in "true-ide" mode on PXA270
In-Reply-To: <201006250911.30277.schindele@nentec.de>
References: <201006231706.33182.schindele@nentec.de>
	<19490.10015.10027.750374@ipc1.ka-ro>
	<201006250911.30277.schindele@nentec.de>
Message-ID: <1277473180.13134.24.camel@e102109-lin.cambridge.arm.com>

On Fri, 2010-06-25 at 08:11 +0100, Juergen Schindele wrote:
> Am Mittwoch, 23. Juni 2010 schrieb Lothar Wa?mann:
> > Hi,
> >
> > > we have a strange problem when booting from a Compact Flash card
> > > as root-device. In one of 10 cases while booting an application from
> > > root-filesystem dies with "Segmentation fault" without a visible error.
> > > After booting the same application runs hundred times without error.
> > > (we're talking about standard appl. like chat, pppd, hwclock and so on)
> > >
> > > For debugging purposes we put printk's in kernels IDE driver
> > > and the problem disappeared. But replacing the printk by a usleep
> > > or so (which is not a solution !) brings the problem back.
> > > It seems that the application received faulty data from CF.
> > > But how and why ?????????????????????????????
> > >
> > > We tested with a custom PXA270 board with a CompactFlash in
> > > "true ide" on processor bus driven by "generic ide / pata_platform"
> > > driver from linux-2.6.27.x.
> > > (by the way linux-2.6.20.x showed the same problem).
> > >
> > > Any ideas, hints, experiences, patches are very welcome :-)
> > > --------------------------------------------------------------
> > I guess that is the old cache problem that apparently was never really
> > fixed:
> > http://marc.info/?t=108537828400002&r=1&w=2
> Hello
> this hint was very helpful for understanding the problem.
> In the mail from Russell King at
> <http://marc.info/?l=linux-arm-kernel&m=108611676807909&w=2>
> he said : .... the rule is if the CPU writes to a page cache page,
> it must call flush_dcache_page afterwards to ensure cache coherency with user space".
> 
> so i made the following patch in drivers/ide/ide-taskfile.c
> in the function ide_pio_sector() where blocks from disk are read
> into a cached page to apply the rule from Russell.

That rule has been discussed on several occasions on LKML. So rather
than changing all the faulty drivers, you can try this:

http://article.gmane.org/gmane.linux.ports.arm.kernel/83413

-- 
Catalin



From catalin.marinas at arm.com  Fri Jun 25 09:50:38 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 25 Jun 2010 14:50:38 +0100
Subject: [PATCH 2/2] arm: Make VFPv3 usable on ARMv6
In-Reply-To: <20100623075703.GB12255@atomide.com>
References: <20100621135125.24299.91290.stgit@baageli.muru.com>
	<1277211592.29532.20.camel@e102109-lin.cambridge.arm.com>
	<20100622132037.GV12255@atomide.com>
	<20100623075703.GB12255@atomide.com>
Message-ID: <1277473838.13134.30.camel@e102109-lin.cambridge.arm.com>

On Wed, 2010-06-23 at 08:57 +0100, Tony Lindgren wrote:
> MVFR0 and MVFR1 are only available starting with ARM1136 r1p0 release
> according to "B.5 VFP changes" in DDI0211F_arm1136_r1p0_trm.pdf. This is
> also when TLS register got added, so we can use HAS_TLS also to test for
> MVFR0 and MVFR1.
> 
> Otherwise VFPFMRX and VFPFMXR access fails and we get:
> 
> Internal error: Oops - undefined instruction: 0 [#1]
> PC is at no_old_VFP_process+0x8/0x3c
> LR is at __und_svc+0x48/0x80
> ...
> 
> Signed-off-by: Tony Lindgren <tony at atomide.com>

The new version looks fine to me.

Acked-by: Catalin Marinas <catalin.marinas at arm.com>

-- 
Catalin



From kgene.kim at samsung.com  Fri Jun 25 09:55:19 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 25 Jun 2010 22:55:19 +0900
Subject: [PATCH] serial: samsung.c: Add FRACVAL support for newer UART
Message-ID: <1277474119-6897-1-git-send-email-kgene.kim@samsung.com>

From: Changhwan Youn <chaos.youn at samsung.com>

FRACVAL register provides the same function as UDIVSLOT register which is
the 1/16ths adjustment to the baud rate but the implementaiton is easier.
To support UDIVSLOT register, UDIVSLOT table search is necessary though
supporting FRACVAL only needs the index value of UDIVSLOT table.

This patch implements the FRACVAL supports for the newer Samsung SoC UARTs.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 drivers/serial/samsung.c |    7 +++++--
 drivers/serial/samsung.h |    1 +
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/serial/samsung.c b/drivers/serial/samsung.c
index a9d6c56..09805c7 100644
--- a/drivers/serial/samsung.c
+++ b/drivers/serial/samsung.c
@@ -530,7 +530,7 @@ static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
 
 	calc->clksrc = clksrc;
 
-	if (ourport->info->has_divslot) {
+	if ((ourport->info->has_divslot) || (ourport->info->has_fracval)) {
 		unsigned long div = rate / baud;
 
 		/* The UDIVSLOT register on the newer UARTs allows us to
@@ -707,6 +707,9 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
 
 		udivslot = udivslot_table[div & 15];
 		dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
+	} else if (ourport->info->has_fracval) {
+		udivslot = (ourport->baudclk_rate / baud) & 15;
+		dbg("fracval = %04x\n", udivslot);
 	}
 
 	switch (termios->c_cflag & CSIZE) {
@@ -755,7 +758,7 @@ static void s3c24xx_serial_set_termios(struct uart_port *port,
 	wr_regl(port, S3C2410_UBRDIV, quot);
 	wr_regl(port, S3C2410_UMCON, umcon);
 
-	if (ourport->info->has_divslot)
+	if ((ourport->info->has_divslot) || (ourport->info->has_fracval))
 		wr_regl(port, S3C2443_DIVSLOT, udivslot);
 
 	dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
diff --git a/drivers/serial/samsung.h b/drivers/serial/samsung.h
index 0ac06a0..124f476 100644
--- a/drivers/serial/samsung.h
+++ b/drivers/serial/samsung.h
@@ -24,6 +24,7 @@ struct s3c24xx_uart_info {
 	/* uart port features */
 
 	unsigned int		has_divslot:1;
+	unsigned int		has_fracval:1;
 
 	/* clock source control */
 
-- 
1.6.2.5



From kgene.kim at samsung.com  Fri Jun 25 10:27:09 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 25 Jun 2010 23:27:09 +0900
Subject: [PATCH 0/8] ARM: S5PV310: Add support for Samsung S5PV310 SoC
Message-ID: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>

This patch set adds support for Samsung S5PV310/S5PC210. The S5PV310
integrates a ARM Cortex A9 microprocessor with several other peripherals
to support features such as multimedia, storage, graphics and gaming.
The S5PV310 can be used in products such as Netbooks and Mobile devices.

This patch set consists of the following patches.

[PATCH 1/8] ARM: S5P: Remove fixed uart offset dependent code
[PATCH 2/8] ARM: S5PV310: Add new CPU initialization support
[PATCH 3/8] ARM: S5PV310: Add Clock and PLL support
[PATCH 4/8] ARM: S5PV310: Add IRQ support
[PATCH 5/8] ARM: S5PV310: Add Timer support
[PATCH 6/8] ARM: S5PV310: Add new Kconfig and Makefiles
[PATCH 7/8] ARM: S5PV310: Add Board support file
[PATCH 8/8] ARM: S5PV310: Add serial port support


From kgene.kim at samsung.com  Fri Jun 25 10:27:10 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 25 Jun 2010 23:27:10 +0900
Subject: [PATCH 1/8] ARM: S5P: Remove fixed uart offset dependent code
In-Reply-To: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
References: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277476037-8806-2-git-send-email-kgene.kim@samsung.com>

From: Changhwan Youn <chaos.youn at samsung.com>

The uart offset between channels has been 0x400 for all S5P series
and to present virtual and physical offsets, both number 0x400 and
S3C_UART_OFFSET have been used together.
This patch removes the use of the number 0x400 and expands the virtual
mapping size of S3C_VA_UART from 4KB to 512KB to support the CPU with
S3C_UART_OFFSET being 0x10000.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/plat-s5p/cpu.c                  |    2 +-
 arch/arm/plat-s5p/include/plat/map-s5p.h |   11 +++++++----
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index 75cb8c3..c478441 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -81,7 +81,7 @@ static struct map_desc s5p_iodesc[] __initdata = {
 	}, {
 		.virtual	= (unsigned long)S3C_VA_UART,
 		.pfn		= __phys_to_pfn(S3C_PA_UART),
-		.length		= SZ_4K,
+		.length		= SZ_512K,
 		.type		= MT_DEVICE,
 	}, {
 		.virtual	= (unsigned long)VA_VIC0,
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index 1482852..3d815f4 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -18,12 +18,15 @@
 #define S5P_VA_SYSTIMER		S3C_ADDR(0x01200000)
 #define S5P_VA_SROMC		S3C_ADDR(0x01100000)
 
-#define S5P_VA_UART0		(S3C_VA_UART + 0x0)
-#define S5P_VA_UART1		(S3C_VA_UART + 0x400)
-#define S5P_VA_UART2		(S3C_VA_UART + 0x800)
-#define S5P_VA_UART3		(S3C_VA_UART + 0xC00)
+#define S5P_VA_UART(x)		(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_VA_UART0		S5P_VA_UART(0)
+#define S5P_VA_UART1		S5P_VA_UART(1)
+#define S5P_VA_UART2		S5P_VA_UART(2)
+#define S5P_VA_UART3		S5P_VA_UART(3)
 
+#ifndef S3C_UART_OFFSET
 #define S3C_UART_OFFSET		(0x400)
+#endif
 
 #define VA_VIC(x)		(S3C_VA_IRQ + ((x) * 0x10000))
 #define VA_VIC0			VA_VIC(0)
-- 
1.6.2.5



From kgene.kim at samsung.com  Fri Jun 25 10:27:17 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 25 Jun 2010 23:27:17 +0900
Subject: [PATCH 8/8] ARM: S5PV310: Add serial port support
In-Reply-To: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
References: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277476037-8806-9-git-send-email-kgene.kim@samsung.com>

From: Changhwan Youn <chaos.youn at samsung.com>

This patch adds UART serial port support for S5PV310 CPU.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 drivers/serial/Kconfig   |    8 +++
 drivers/serial/Makefile  |    1 +
 drivers/serial/s5pv310.c |  124 ++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 133 insertions(+), 0 deletions(-)
 create mode 100644 drivers/serial/s5pv310.c

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 8b23165..b5ff41f 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -550,6 +550,14 @@ config SERIAL_S5PV210
 	help
 	  Serial port support for Samsung's S5P Family of SoC's
 
+config SERIAL_S5PV310
+	tristate "Samsung S5PV310 Serial port support"
+	depends on SERIAL_SAMSUNG && CPU_S5PV310
+	select SERIAL_SAMSUNG_UARTS_4
+	default y
+	help
+	  Serial port support for Samsung's S5P Family of SoC's
+
 config SERIAL_MAX3100
 	tristate "MAX3100 support"
 	depends on SPI
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index 208a855..bd32d3f 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -45,6 +45,7 @@ obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o
 obj-$(CONFIG_SERIAL_S3C24A0) += s3c24a0.o
 obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o
 obj-$(CONFIG_SERIAL_S5PV210) += s5pv210.o
+obj-$(CONFIG_SERIAL_S5PV310) += s5pv310.o
 obj-$(CONFIG_SERIAL_MAX3100) += max3100.o
 obj-$(CONFIG_SERIAL_IP22_ZILOG) += ip22zilog.o
 obj-$(CONFIG_SERIAL_MUX) += mux.o
diff --git a/drivers/serial/s5pv310.c b/drivers/serial/s5pv310.c
new file mode 100644
index 0000000..1d466cf
--- /dev/null
+++ b/drivers/serial/s5pv310.c
@@ -0,0 +1,124 @@
+/* linux/drivers/serial/s5pv310.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Based on drivers/serial/s5pv210.c
+ *
+ * Driver for Samsung S5PV310 SoC UARTs.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+
+#include <plat/regs-serial.h>
+#include "samsung.h"
+
+static int s5pv310_serial_setsource(struct uart_port *port,
+				    struct s3c24xx_uart_clksrc *clk)
+{
+	/* for s5pv310, serial clock source is only uclk1 */
+	return 0;
+};
+
+static int s5pv310_serial_getsource(struct uart_port *port,
+				    struct s3c24xx_uart_clksrc *clk)
+{
+	/* for s5pv310, serial clock source is only uclk1 */
+	clk->divisor = 1;
+	clk->name = "uclk1";
+	return 0;
+};
+
+static int s5pv310_serial_resetport(struct uart_port *port,
+				    struct s3c2410_uartcfg *cfg)
+{
+	wr_regl(port, S3C2410_UCON,  cfg->ucon);
+	wr_regl(port, S3C2410_ULCON, cfg->ulcon);
+
+	/* reset both fifos */
+	wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
+	wr_regl(port, S3C2410_UFCON, cfg->ufcon);
+
+	return 0;
+}
+
+#define S5PV310_UART_DEFAULT_INFO(fifo_size)			\
+		.name		= "Samsung S5PV310 UART",	\
+		.type		= PORT_S3C6400,			\
+		.fifosize	= fifo_size,			\
+		.has_fracval	= 1,				\
+		.rx_fifomask	= S5PV210_UFSTAT_RXMASK,	\
+		.rx_fifoshift	= S5PV210_UFSTAT_RXSHIFT,	\
+		.rx_fifofull	= S5PV210_UFSTAT_RXFULL,	\
+		.tx_fifofull	= S5PV210_UFSTAT_TXFULL,	\
+		.tx_fifomask	= S5PV210_UFSTAT_TXMASK,	\
+		.tx_fifoshift	= S5PV210_UFSTAT_TXSHIFT,	\
+		.get_clksrc	= s5pv310_serial_getsource,	\
+		.set_clksrc	= s5pv310_serial_setsource,	\
+		.reset_port	= s5pv310_serial_resetport
+
+static struct s3c24xx_uart_info s5p_port_fifo256 = {
+	S5PV310_UART_DEFAULT_INFO(256),
+};
+
+static struct s3c24xx_uart_info s5p_port_fifo64 = {
+	S5PV310_UART_DEFAULT_INFO(64),
+};
+
+static struct s3c24xx_uart_info s5p_port_fifo16 = {
+	S5PV310_UART_DEFAULT_INFO(16),
+};
+
+struct s3c24xx_uart_info *s5p_uart_inf[] = {
+	[0] = &s5p_port_fifo256,
+	[1] = &s5p_port_fifo64,
+	[2] = &s5p_port_fifo16,
+	[3] = &s5p_port_fifo16,
+};
+
+/* device management */
+static int s5p_serial_probe(struct platform_device *pdev)
+{
+	return s3c24xx_serial_probe(pdev, s5p_uart_inf[pdev->id]);
+}
+
+static struct platform_driver s5p_serial_driver = {
+	.probe		= s5p_serial_probe,
+	.remove		= __devexit_p(s3c24xx_serial_remove),
+	.driver		= {
+		.name	= "s5pv310-uart",
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init s5pv310_serial_console_init(void)
+{
+	return s3c24xx_serial_initconsole(&s5p_serial_driver, s5p_uart_inf);
+}
+
+console_initcall(s5pv310_serial_console_init);
+
+static int __init s5p_serial_init(void)
+{
+	return s3c24xx_serial_init(&s5p_serial_driver, *s5p_uart_inf);
+}
+
+static void __exit s5p_serial_exit(void)
+{
+	platform_driver_unregister(&s5p_serial_driver);
+}
+
+module_init(s5p_serial_init);
+module_exit(s5p_serial_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:s5pv310-uart");
+MODULE_DESCRIPTION("Samsung S5PV310 UART Driver support");
+MODULE_AUTHOR("Changhwan Youn <chaos.youn at samsung.com>");
-- 
1.6.2.5



From kgene.kim at samsung.com  Fri Jun 25 10:27:15 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 25 Jun 2010 23:27:15 +0900
Subject: [PATCH 6/8] ARM: S5PV310: Add new Kconfig and Makefiles
In-Reply-To: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
References: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277476037-8806-7-git-send-email-kgene.kim@samsung.com>

From: Changhwan Youn <chaos.youn at samsung.com>

This patch adds the Kconfig and Makefile for the new S5PV310 SoC.
It also updates arch/arm Kconfig, Makefile and arch/arm/mm/Kconfig
to include support for the new S5PV310.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/Kconfig                    |   24 +++++++++++++++++++-----
 arch/arm/Makefile                   |    1 +
 arch/arm/mach-s5pv310/Kconfig       |   26 ++++++++++++++++++++++++++
 arch/arm/mach-s5pv310/Makefile      |   20 ++++++++++++++++++++
 arch/arm/mach-s5pv310/Makefile.boot |    2 ++
 arch/arm/mm/Kconfig                 |    3 ++-
 arch/arm/plat-s5p/Kconfig           |    5 +++--
 7 files changed, 73 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/mach-s5pv310/Kconfig
 create mode 100644 arch/arm/mach-s5pv310/Makefile
 create mode 100644 arch/arm/mach-s5pv310/Makefile.boot

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..a7a8040 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -704,6 +704,15 @@ config ARCH_S5PV210
 	help
 	  Samsung S5PV210/S5PC110 series based systems
 
+config ARCH_S5PV310
+	bool "Samsung S5PV310/S5PC210"
+	select CPU_V7
+	select GENERIC_GPIO
+	select HAVE_CLK
+	select GENERIC_CLOCKEVENTS
+	help
+	  Samsung S5PV310 series based systems
+
 config ARCH_SHARK
 	bool "Shark"
 	select CPU_SA110
@@ -904,6 +913,8 @@ source "arch/arm/mach-s5pc100/Kconfig"
 
 source "arch/arm/mach-s5pv210/Kconfig"
 
+source "arch/arm/mach-s5pv310/Kconfig"
+
 source "arch/arm/mach-shmobile/Kconfig"
 
 source "arch/arm/plat-stmp3xxx/Kconfig"
@@ -1099,10 +1110,11 @@ config SMP
 	bool "Symmetric Multi-Processing (EXPERIMENTAL)"
 	depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
 		 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
-		 ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
+		 ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_S5PV310)
 	depends on GENERIC_CLOCKEVENTS
 	select USE_GENERIC_SMP_HELPERS
-	select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
+	select HAVE_ARM_SCU if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 ||\
+			ARCH_S5PV310)
 	help
 	  This enables support for systems with more than one CPU. If you have
 	  a system with only one CPU, like most personal computers, say N. If
@@ -1171,9 +1183,10 @@ config HOTPLUG_CPU
 config LOCAL_TIMERS
 	bool "Use local timer interrupts"
 	depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
-		REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || ARCH_U8500)
+		REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
+		ARCH_U8500 || ARCH_S5PV310)
 	default y
-	select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500)
+	select HAVE_ARM_TWD if (ARCH_REALVIEW || ARCH_OMAP4 || ARCH_U8500 || ARCH_S5PV310)
 	help
 	  Enable support for local timers on SMP platforms, rather then the
 	  legacy IPI broadcast method.  Local timers allows the system
@@ -1185,7 +1198,8 @@ source kernel/Kconfig.preempt
 config HZ
 	int
 	default 128 if ARCH_L7200
-	default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PV210
+	default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || ARCH_S5P6442 || \
+		       ARCH_S5PV210 || ARCH_S5PV310
 	default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
 	default AT91_TIMER_HZ if ARCH_AT91
 	default 100
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 64ba313..d80c9f9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -170,6 +170,7 @@ machine-$(CONFIG_ARCH_S5P6440)		:= s5p6440
 machine-$(CONFIG_ARCH_S5P6442)		:= s5p6442
 machine-$(CONFIG_ARCH_S5PC100)		:= s5pc100
 machine-$(CONFIG_ARCH_S5PV210)		:= s5pv210
+machine-$(CONFIG_ARCH_S5PV310)		:= s5pv310
 machine-$(CONFIG_ARCH_SA1100)		:= sa1100
 machine-$(CONFIG_ARCH_SHARK)		:= shark
 machine-$(CONFIG_ARCH_SHMOBILE) 	:= shmobile
diff --git a/arch/arm/mach-s5pv310/Kconfig b/arch/arm/mach-s5pv310/Kconfig
new file mode 100644
index 0000000..24ef3cd
--- /dev/null
+++ b/arch/arm/mach-s5pv310/Kconfig
@@ -0,0 +1,26 @@
+# arch/arm/mach-s5pv310/Kconfig
+#
+# Copyright (c) 2010 Samsung Electronics Co., Ltd.
+#		http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+# Configuration options for the S5PV310
+
+if ARCH_S5PV310
+
+config CPU_S5PV310
+	bool
+	select PLAT_S5P
+	help
+	  Enable S5PV310 CPU support
+
+# machine support
+
+config MACH_SMDKV310
+	bool "SMDKV310"
+	select CPU_S5PV310
+	select ARCH_SPARSEMEM_ENABLE
+	help
+	  Machine support for Samsung SMDKV310
+endif
diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
new file mode 100644
index 0000000..1b263a5
--- /dev/null
+++ b/arch/arm/mach-s5pv310/Makefile
@@ -0,0 +1,20 @@
+# arch/arm/mach-s5pv310/Makefile
+#
+# Copyright (c) 2010 Samsung Electronics Co., Ltd.
+#		http://www.samsung.com/
+#
+# Licensed under GPLv2
+
+obj-y				:=
+obj-m				:=
+obj-n				:=
+obj-				:=
+
+# Core support for S5PV310 system
+
+obj-$(CONFIG_CPU_S5PV310)	+= cpu.o init.o clock.o irq-combiner.o
+obj-$(CONFIG_CPU_S5PV310)	+= setup-i2c0.o time.o
+
+obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
+obj-$(CONFIG_LOCAL_TIMERS)	+= localtimer.o
+obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
diff --git a/arch/arm/mach-s5pv310/Makefile.boot b/arch/arm/mach-s5pv310/Makefile.boot
new file mode 100644
index 0000000..d65956f
--- /dev/null
+++ b/arch/arm/mach-s5pv310/Makefile.boot
@@ -0,0 +1,2 @@
+   zreladdr-y	:= 0x40008000
+params_phys-y	:= 0x40000100
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..45284c8 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -763,7 +763,8 @@ config CACHE_L2X0
 	bool "Enable the L2x0 outer cache controller"
 	depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
 		   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || \
-		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
+		   ARCH_NOMADIK || ARCH_OMAP4 || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
+		   ARCH_S5PV310
 	default y
 	select OUTER_CACHE
 	select OUTER_CACHE_SYNC
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 11d6a1b..907ac63 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -7,9 +7,10 @@
 
 config PLAT_S5P
 	bool
-	depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210)
+	depends on (ARCH_S5P6440 || ARCH_S5P6442 || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_S5PV310)
 	default y
-	select ARM_VIC
+	select ARM_VIC if !ARCH_S5PV310
+	select ARM_GIC if ARCH_S5PV310
 	select NO_IOPORT
 	select ARCH_REQUIRE_GPIOLIB
 	select S3C_GPIO_TRACK
-- 
1.6.2.5



From kgene.kim at samsung.com  Fri Jun 25 10:27:16 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 25 Jun 2010 23:27:16 +0900
Subject: [PATCH 7/8] ARM: S5PV310: Add Board support file
In-Reply-To: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
References: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277476037-8806-8-git-send-email-kgene.kim@samsung.com>

From: Changhwan Youn <chaos.youn at samsung.com>

This patch adds Samsung SMDKV310 board support file.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pv310/Makefile        |    4 ++
 arch/arm/mach-s5pv310/mach-smdkv310.c |   94 +++++++++++++++++++++++++++++++++
 2 files changed, 98 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pv310/mach-smdkv310.c

diff --git a/arch/arm/mach-s5pv310/Makefile b/arch/arm/mach-s5pv310/Makefile
index 1b263a5..56e7693 100644
--- a/arch/arm/mach-s5pv310/Makefile
+++ b/arch/arm/mach-s5pv310/Makefile
@@ -18,3 +18,7 @@ obj-$(CONFIG_CPU_S5PV310)	+= setup-i2c0.o time.o
 obj-$(CONFIG_SMP)		+= platsmp.o headsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)	+= localtimer.o
 obj-$(CONFIG_HOTPLUG_CPU)	+= hotplug.o
+
+# machine support
+
+obj-$(CONFIG_MACH_SMDKV310)	+= mach-smdkv310.o
diff --git a/arch/arm/mach-s5pv310/mach-smdkv310.c b/arch/arm/mach-s5pv310/mach-smdkv310.c
new file mode 100644
index 0000000..6ce9ebd
--- /dev/null
+++ b/arch/arm/mach-s5pv310/mach-smdkv310.c
@@ -0,0 +1,94 @@
+/* linux/arch/arm/mach-s5pv310/mach-smdkv310.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/serial_core.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <plat/regs-serial.h>
+#include <plat/s5pv310.h>
+#include <plat/cpu.h>
+
+#include <mach/map.h>
+
+extern struct sys_timer s5pv310_timer;
+
+/* Following are default values for UCON, ULCON and UFCON UART registers */
+#define SMDKV310_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
+				 S3C2410_UCON_RXILEVEL |	\
+				 S3C2410_UCON_TXIRQMODE |	\
+				 S3C2410_UCON_RXIRQMODE |	\
+				 S3C2410_UCON_RXFIFO_TOI |	\
+				 S3C2443_UCON_RXERR_IRQEN)
+
+#define SMDKV310_ULCON_DEFAULT	S3C2410_LCON_CS8
+
+#define SMDKV310_UFCON_DEFAULT	(S3C2410_UFCON_FIFOMODE |	\
+				 S5PV210_UFCON_TXTRIG4 |	\
+				 S5PV210_UFCON_RXTRIG4)
+
+static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
+	[0] = {
+		.hwport		= 0,
+		.flags		= 0,
+		.ucon		= SMDKV310_UCON_DEFAULT,
+		.ulcon		= SMDKV310_ULCON_DEFAULT,
+		.ufcon		= SMDKV310_UFCON_DEFAULT,
+	},
+	[1] = {
+		.hwport		= 1,
+		.flags		= 0,
+		.ucon		= SMDKV310_UCON_DEFAULT,
+		.ulcon		= SMDKV310_ULCON_DEFAULT,
+		.ufcon		= SMDKV310_UFCON_DEFAULT,
+	},
+	[2] = {
+		.hwport		= 2,
+		.flags		= 0,
+		.ucon		= SMDKV310_UCON_DEFAULT,
+		.ulcon		= SMDKV310_ULCON_DEFAULT,
+		.ufcon		= SMDKV310_UFCON_DEFAULT,
+	},
+	[3] = {
+		.hwport		= 3,
+		.flags		= 0,
+		.ucon		= SMDKV310_UCON_DEFAULT,
+		.ulcon		= SMDKV310_ULCON_DEFAULT,
+		.ufcon		= SMDKV310_UFCON_DEFAULT,
+	},
+};
+
+static void __init smdkv310_map_io(void)
+{
+	s5p_init_io(NULL, 0, S5P_VA_CHIPID);
+	s3c24xx_init_clocks(24000000);
+	s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
+}
+
+static void __init smdkv310_machine_init(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+	l2x0_init(S5P_VA_L2CC, 1 << 28, 0xffffffff);
+#endif
+}
+
+MACHINE_START(SMDKV310, "SMDKV310")
+	/* Maintainer: Kukjin Kim <kgene.kim at samsung.com> */
+	/* Maintainer: Changhwan Youn <chaos.youn at samsung.com> */
+	.phys_io	= S3C_PA_UART & 0xfff00000,
+	.io_pg_offst	= (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+	.boot_params	= S5P_PA_SDRAM + 0x100,
+	.init_irq	= s5pv310_init_irq,
+	.map_io		= smdkv310_map_io,
+	.init_machine	= smdkv310_machine_init,
+	.timer		= &s5pv310_timer,
+MACHINE_END
-- 
1.6.2.5



From kgene.kim at samsung.com  Fri Jun 25 10:27:13 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 25 Jun 2010 23:27:13 +0900
Subject: [PATCH 4/8] ARM: S5PV310: Add IRQ support
In-Reply-To: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
References: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277476037-8806-5-git-send-email-kgene.kim@samsung.com>

From: Changhwan Youn <chaos.youn at samsung.com>

This patch adds IRQ support for S5PV310.
ARM GIC is installed in S5PV310 instead of VIC which is in every other CPUs
in S5P series. Several irq combiners are used to resolve the lack of irq
lines in current implementation.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pv310/include/mach/irqs.h     |   74 ++++++++++++++
 arch/arm/mach-s5pv310/include/mach/regs-irq.h |   19 ++++
 arch/arm/mach-s5pv310/irq-combiner.c          |  129 +++++++++++++++++++++++++
 arch/arm/plat-s5p/irq.c                       |    2 +
 4 files changed, 224 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pv310/include/mach/irqs.h
 create mode 100644 arch/arm/mach-s5pv310/include/mach/regs-irq.h
 create mode 100644 arch/arm/mach-s5pv310/irq-combiner.c

diff --git a/arch/arm/mach-s5pv310/include/mach/irqs.h b/arch/arm/mach-s5pv310/include/mach/irqs.h
new file mode 100644
index 0000000..56885ca
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/irqs.h
@@ -0,0 +1,74 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/irqs.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV210 - IRQ definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+
+#include <plat/irqs.h>
+
+/* Private Peripheral Interrupt */
+#define IRQ_PPI(x)		S5P_IRQ(x+16)
+
+#define IRQ_LOCALTIMER		IRQ_PPI(13)
+
+/* Shared Peripheral Interrupt */
+#define IRQ_SPI(x)		S5P_IRQ(x+32)
+
+#define IRQ_EINT0		IRQ_SPI(40)
+#define IRQ_EINT1		IRQ_SPI(41)
+#define IRQ_EINT2		IRQ_SPI(42)
+#define IRQ_EINT3		IRQ_SPI(43)
+#define IRQ_USB_HSOTG		IRQ_SPI(44)
+#define IRQ_USB_HOST		IRQ_SPI(45)
+#define IRQ_MODEM_IF		IRQ_SPI(46)
+#define IRQ_ROTATOR		IRQ_SPI(47)
+#define IRQ_JPEG		IRQ_SPI(48)
+#define IRQ_2D			IRQ_SPI(49)
+#define IRQ_PCIE		IRQ_SPI(50)
+#define IRQ_SYSTEM_TIMER	IRQ_SPI(51)
+#define IRQ_MFC			IRQ_SPI(52)
+#define IRQ_WTD			IRQ_SPI(53)
+#define IRQ_AUDIO_SS		IRQ_SPI(54)
+#define IRQ_AC97		IRQ_SPI(55)
+#define IRQ_SPDIF		IRQ_SPI(56)
+#define IRQ_KEYPAD		IRQ_SPI(57)
+#define IRQ_INTFEEDCTRL_SSS	IRQ_SPI(58)
+#define IRQ_SLIMBUS		IRQ_SPI(59)
+#define IRQ_PMU			IRQ_SPI(60)
+#define IRQ_TSI			IRQ_SPI(61)
+#define IRQ_SATA		IRQ_SPI(62)
+#define IRQ_GPS			IRQ_SPI(63)
+
+#define MAX_IRQ_IN_COMBINER	8
+#define COMBINER_GROUP(x)	((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64))
+#define COMBINER_IRQ(x, y)	(COMBINER_GROUP(x) + y)
+
+#define IRQ_TIMER0_VIC		COMBINER_IRQ(22, 0)
+#define IRQ_TIMER1_VIC		COMBINER_IRQ(22, 1)
+#define IRQ_TIMER2_VIC		COMBINER_IRQ(22, 2)
+#define IRQ_TIMER3_VIC		COMBINER_IRQ(22, 3)
+#define IRQ_TIMER4_VIC		COMBINER_IRQ(22, 4)
+
+#define IRQ_UART0		COMBINER_IRQ(26, 0)
+#define IRQ_UART1		COMBINER_IRQ(26, 1)
+#define IRQ_UART2		COMBINER_IRQ(26, 2)
+#define IRQ_UART3		COMBINER_IRQ(26, 3)
+#define IRQ_UART4		COMBINER_IRQ(26, 4)
+
+#define IRQ_IIC			COMBINER_IRQ(27, 0)
+
+/* Set the default NR_IRQS */
+#define NR_IRQS			COMBINER_IRQ(MAX_COMBINER_NR, 0)
+
+#define MAX_COMBINER_NR		39
+
+#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-irq.h b/arch/arm/mach-s5pv310/include/mach/regs-irq.h
new file mode 100644
index 0000000..c6e09c7
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-irq.h
@@ -0,0 +1,19 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/regs-irq.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV310 - IRQ register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_IRQ_H
+#define __ASM_ARCH_REGS_IRQ_H __FILE__
+
+#include <asm/hardware/gic.h>
+#include <mach/map.h>
+
+#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pv310/irq-combiner.c b/arch/arm/mach-s5pv310/irq-combiner.c
new file mode 100644
index 0000000..6d6b4f9
--- /dev/null
+++ b/arch/arm/mach-s5pv310/irq-combiner.c
@@ -0,0 +1,129 @@
+/* linux/arch/arm/mach-s5pv310/irq-combiner.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * Based on arch/arm/common/gic.c
+ *
+ * IRQ COMBINER support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/io.h>
+
+#include <asm/mach/irq.h>
+
+#define COMBINER_ENABLE_SET	0x0
+#define COMBINER_ENABLE_CLEAR	0x4
+#define COMBINER_INT_STATUS	0xC
+
+static DEFINE_SPINLOCK(irq_controller_lock);
+
+struct combiner_chip_data {
+	unsigned int irq_offset;
+	void __iomem *base;
+};
+
+static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
+
+static inline void __iomem *combiner_base(unsigned int irq)
+{
+	struct combiner_chip_data *combiner_data = get_irq_chip_data(irq);
+	return combiner_data->base;
+}
+
+static void combiner_mask_irq(unsigned int irq)
+{
+	u32 mask = 1 << (irq % 32);
+
+	spin_lock(&irq_controller_lock);
+	__raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR);
+	spin_unlock(&irq_controller_lock);
+}
+
+static void combiner_unmask_irq(unsigned int irq)
+{
+	u32 mask = 1 << (irq % 32);
+
+	spin_lock(&irq_controller_lock);
+	__raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET);
+	spin_unlock(&irq_controller_lock);
+}
+
+static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
+{
+	struct combiner_chip_data *chip_data = get_irq_data(irq);
+	struct irq_chip *chip = get_irq_chip(irq);
+	unsigned int cascade_irq, combiner_irq;
+	unsigned long status;
+
+	/* primary controller ack'ing */
+	chip->ack(irq);
+
+	spin_lock(&irq_controller_lock);
+	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
+	spin_unlock(&irq_controller_lock);
+
+	if (status == 0)
+		goto out;
+
+	for (combiner_irq = 0; combiner_irq < 32; combiner_irq++) {
+		if (status & 0x1)
+			break;
+		status >>= 1;
+	}
+
+	cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
+	if (unlikely(cascade_irq >= NR_IRQS))
+		do_bad_IRQ(cascade_irq, desc);
+	else
+		generic_handle_irq(cascade_irq);
+
+ out:
+	/* primary controller unmasking */
+	chip->unmask(irq);
+}
+
+static struct irq_chip combiner_chip = {
+	.name		= "COMBINER",
+	.mask		= combiner_mask_irq,
+	.unmask		= combiner_unmask_irq,
+};
+
+void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
+{
+	if (combiner_nr >= MAX_COMBINER_NR)
+		BUG();
+	if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0)
+		BUG();
+	set_irq_chained_handler(irq, combiner_handle_cascade_irq);
+}
+
+void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
+			  unsigned int irq_start)
+{
+	unsigned int i;
+
+	if (combiner_nr >= MAX_COMBINER_NR)
+		BUG();
+
+	combiner_data[combiner_nr].base = base;
+	combiner_data[combiner_nr].irq_offset = irq_start;
+
+	/* Disable all interrupts */
+
+	__raw_writel(0xffffffff, base + COMBINER_ENABLE_CLEAR);
+
+	/* Setup the Linux IRQ subsystem */
+
+	for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+				+ MAX_IRQ_IN_COMBINER; i++) {
+		set_irq_chip(i, &combiner_chip);
+		set_irq_chip_data(i, &combiner_data[combiner_nr]);
+		set_irq_handler(i, handle_level_irq);
+		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
+	}
+}
diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c
index 25e1eb6..5560b12 100644
--- a/arch/arm/plat-s5p/irq.c
+++ b/arch/arm/plat-s5p/irq.c
@@ -56,11 +56,13 @@ static struct s3c_uart_irq uart_irqs[] = {
 
 void __init s5p_init_irq(u32 *vic, u32 num_vic)
 {
+#ifdef CONFIG_ARM_VIC
 	int irq;
 
 	/* initialize the VICs */
 	for (irq = 0; irq < num_vic; irq++)
 		vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
+#endif
 
 	s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
 	s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
-- 
1.6.2.5



From kgene.kim at samsung.com  Fri Jun 25 10:27:14 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 25 Jun 2010 23:27:14 +0900
Subject: [PATCH 5/8] ARM: S5PV310: Add Timer support
In-Reply-To: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
References: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277476037-8806-6-git-send-email-kgene.kim@samsung.com>

From: Changhwan Youn <chaos.youn at samsung.com>

This patch adds timer support for S5PV310.
Until now, all S5P SoCs use CONFIG_ARCH_USES_GETTIMEOFFSET macro as a default
configuration. Instead, S5PV310 implements clocksource and clock_event_device
to support the high resolution timer and tickless system.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pv310/include/mach/pwm-clock.h |   70 ++++++
 arch/arm/mach-s5pv310/localtimer.c             |   25 ++
 arch/arm/mach-s5pv310/time.c                   |  289 ++++++++++++++++++++++++
 arch/arm/plat-samsung/Makefile                 |    2 +-
 4 files changed, 385 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-s5pv310/include/mach/pwm-clock.h
 create mode 100644 arch/arm/mach-s5pv310/localtimer.c
 create mode 100644 arch/arm/mach-s5pv310/time.c

diff --git a/arch/arm/mach-s5pv310/include/mach/pwm-clock.h b/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
new file mode 100644
index 0000000..7e6da27
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
@@ -0,0 +1,70 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Copyright 2008 Openmoko, Inc.
+ * Copyright 2008 Simtec Electronics
+ *      Ben Dooks <ben at simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
+ *
+ * S5PV310 - pwm clock and timer support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PWMCLK_H
+#define __ASM_ARCH_PWMCLK_H __FILE__
+
+/**
+ * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
+ *
+ * Return true if the given configuration from TCFG1 is a TCLK instead
+ * any of the TDIV clocks.
+ */
+static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
+{
+	return tcfg == S3C64XX_TCFG1_MUX_TCLK;
+}
+
+/**
+ * tcfg_to_divisor() - convert tcfg1 setting to a divisor
+ * @tcfg1: The tcfg1 setting, shifted down.
+ *
+ * Get the divisor value for the given tcfg1 setting. We assume the
+ * caller has already checked to see if this is not a TCLK source.
+ */
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+	return 1 << tcfg1;
+}
+
+/**
+ * pwm_tdiv_has_div1() - does the tdiv setting have a /1
+ *
+ * Return true if we have a /1 in the tdiv setting.
+ */
+static inline unsigned int pwm_tdiv_has_div1(void)
+{
+	return 1;
+}
+
+/**
+ * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
+ * @div: The divisor to calculate the bit information for.
+ *
+ * Turn a divisor into the necessary bit field for TCFG1.
+ */
+static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
+{
+	return ilog2(div);
+}
+
+#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
+
+#endif /* __ASM_ARCH_PWMCLK_H */
diff --git a/arch/arm/mach-s5pv310/localtimer.c b/arch/arm/mach-s5pv310/localtimer.c
new file mode 100644
index 0000000..2784036
--- /dev/null
+++ b/arch/arm/mach-s5pv310/localtimer.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-s5pv310/localtimer.c
+ *
+ * Cloned from linux/arch/arm/mach-realview/localtimer.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/clockchips.h>
+
+#include <asm/irq.h>
+#include <asm/localtimer.h>
+
+/*
+ * Setup the local clock events for a CPU.
+ */
+void __cpuinit local_timer_setup(struct clock_event_device *evt)
+{
+	evt->irq = IRQ_LOCALTIMER;
+	twd_timer_setup(evt);
+}
diff --git a/arch/arm/mach-s5pv310/time.c b/arch/arm/mach-s5pv310/time.c
new file mode 100644
index 0000000..250af60
--- /dev/null
+++ b/arch/arm/mach-s5pv310/time.c
@@ -0,0 +1,289 @@
+/* linux/arch/arm/mach-s5pv310/time.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * S5PV310 (and compatible) HRT support
+ * PWM 2/4 is used for this feature
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/platform_device.h>
+
+#include <asm/smp_twd.h>
+
+#include <mach/map.h>
+#include <plat/regs-timer.h>
+#include <asm/mach/time.h>
+
+static unsigned long clock_count_per_tick;
+
+static struct clk *tin2;
+static struct clk *tin4;
+static struct clk *tdiv2;
+static struct clk *tdiv4;
+static struct clk *timerclk;
+
+static void s5pv310_pwm_stop(unsigned int pwm_id)
+{
+	unsigned long tcon;
+
+	tcon = __raw_readl(S3C2410_TCON);
+
+	switch (pwm_id) {
+	case 2:
+		tcon &= ~S3C2410_TCON_T2START;
+		break;
+	case 4:
+		tcon &= ~S3C2410_TCON_T4START;
+		break;
+	default:
+		break;
+	}
+	__raw_writel(tcon, S3C2410_TCON);
+}
+
+static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
+{
+	unsigned long tcon;
+
+	tcon = __raw_readl(S3C2410_TCON);
+
+	/* timers reload after counting zero, so reduce the count by 1 */
+	tcnt--;
+
+	printk(KERN_DEBUG "timer tcon=%08lx, tcnt %08lx\n", tcon, tcnt);
+
+	/* ensure timer is stopped... */
+	switch (pwm_id) {
+	case 2:
+		tcon &= ~(0xf<<12);
+		tcon |= S3C2410_TCON_T2MANUALUPD;
+
+		__raw_writel(tcnt, S3C2410_TCNTB(2));
+		__raw_writel(tcnt, S3C2410_TCMPB(2));
+		__raw_writel(tcon, S3C2410_TCON);
+
+		break;
+	case 4:
+		tcon &= ~(7<<20);
+		tcon |= S3C2410_TCON_T4MANUALUPD;
+
+		__raw_writel(tcnt, S3C2410_TCNTB(4));
+		__raw_writel(tcnt, S3C2410_TCMPB(4));
+		__raw_writel(tcon, S3C2410_TCON);
+
+		break;
+	default:
+		break;
+	}
+}
+
+static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
+{
+	unsigned long tcon;
+
+	tcon  = __raw_readl(S3C2410_TCON);
+
+	switch (pwm_id) {
+	case 2:
+		tcon |= S3C2410_TCON_T2START;
+		tcon &= ~S3C2410_TCON_T2MANUALUPD;
+
+		if (periodic)
+			tcon |= S3C2410_TCON_T2RELOAD;
+		else
+			tcon &= ~S3C2410_TCON_T2RELOAD;
+		break;
+	case 4:
+		tcon |= S3C2410_TCON_T4START;
+		tcon &= ~S3C2410_TCON_T4MANUALUPD;
+
+		if (periodic)
+			tcon |= S3C2410_TCON_T4RELOAD;
+		else
+			tcon &= ~S3C2410_TCON_T4RELOAD;
+		break;
+	default:
+		break;
+	}
+	__raw_writel(tcon, S3C2410_TCON);
+}
+
+static int s5pv310_pwm_set_next_event(unsigned long cycles,
+					struct clock_event_device *evt)
+{
+	s5pv310_pwm_init(4, cycles);
+	s5pv310_pwm_start(4, 0);
+	return 0;
+}
+
+static void s5pv310_pwm_set_mode(enum clock_event_mode mode,
+				struct clock_event_device *evt)
+{
+	s5pv310_pwm_stop(4);
+
+	switch (mode) {
+	case CLOCK_EVT_MODE_PERIODIC:
+		s5pv310_pwm_init(4, clock_count_per_tick);
+		s5pv310_pwm_start(4, 1);
+		break;
+	case CLOCK_EVT_MODE_ONESHOT:
+		break;
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+	case CLOCK_EVT_MODE_RESUME:
+		break;
+	}
+}
+
+static struct clock_event_device pwm_event_device = {
+	.name		= "pwm_timer4",
+	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+	.rating		= 200,
+	.shift		= 32,
+	.set_next_event	= s5pv310_pwm_set_next_event,
+	.set_mode	= s5pv310_pwm_set_mode,
+};
+
+irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = &pwm_event_device;
+
+	evt->event_handler(evt);
+
+	return IRQ_HANDLED;
+}
+
+static struct irqaction s5pv310_clock_event_irq = {
+	.name		= "pwm_timer4_irq",
+	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+	.handler	= s5pv310_clock_event_isr,
+};
+
+static void __init s5pv310_clockevent_init(void)
+{
+	unsigned long pclk;
+	unsigned long clock_rate;
+	struct clk *tscaler;
+
+	pclk = clk_get_rate(timerclk);
+
+	/* configure clock tick */
+
+	tscaler = clk_get_parent(tdiv4);
+
+	clk_set_rate(tscaler, pclk / 2);
+	clk_set_rate(tdiv4, pclk / 2);
+	clk_set_parent(tin4, tdiv4);
+
+	clock_rate = clk_get_rate(tin4);
+
+	clock_count_per_tick = clock_rate / HZ;
+
+	pwm_event_device.mult =
+		div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift);
+	pwm_event_device.max_delta_ns =
+		clockevent_delta2ns(-1, &pwm_event_device);
+	pwm_event_device.min_delta_ns =
+		clockevent_delta2ns(1, &pwm_event_device);
+
+	pwm_event_device.cpumask = cpumask_of(0);
+	clockevents_register_device(&pwm_event_device);
+
+	setup_irq(IRQ_TIMER4, &s5pv310_clock_event_irq);
+}
+
+static cycle_t s5pv310_pwm2_read(struct clocksource *cs)
+{
+	return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x2c));
+}
+
+struct clocksource pwm_clocksource = {
+	.name		= "pwm_timer2",
+	.rating		= 250,
+	.read		= s5pv310_pwm2_read,
+	.mask		= CLOCKSOURCE_MASK(32),
+	.shift		= 20,
+	.flags		= CLOCK_SOURCE_IS_CONTINUOUS ,
+};
+
+static void __init s5pv310_clocksource_init(void)
+{
+	unsigned long pclk;
+	unsigned long clock_rate;
+
+	pclk = clk_get_rate(timerclk);
+
+	clk_set_rate(tdiv2, pclk / 2);
+	clk_set_parent(tin2, tdiv2);
+
+	clock_rate = clk_get_rate(tin2);
+
+	pwm_clocksource.mult =
+		clocksource_khz2mult(clock_rate/1000, pwm_clocksource.shift);
+
+	if (clocksource_register(&pwm_clocksource))
+		panic("%s: can't register clocksource\n", pwm_clocksource.name);
+
+	s5pv310_pwm_init(2, ~0);
+	s5pv310_pwm_start(2, 1);
+}
+
+static void __init s5pv310_timer_resources(void)
+{
+	struct platform_device tmpdev;
+
+	tmpdev.dev.bus = &platform_bus_type;
+
+	timerclk = clk_get(NULL, "timers");
+	if (IS_ERR(timerclk))
+		panic("failed to get timers clock for system timer");
+
+	clk_enable(timerclk);
+
+	tmpdev.id = 2;
+	tin2 = clk_get(&tmpdev.dev, "pwm-tin");
+	if (IS_ERR(tin2))
+		panic("failed to get pwm-tin2 clock for system timer");
+
+	tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv");
+	if (IS_ERR(tdiv2))
+		panic("failed to get pwm-tdiv2 clock for system timer");
+	clk_enable(tin2);
+
+	tmpdev.id = 4;
+	tin4 = clk_get(&tmpdev.dev, "pwm-tin");
+	if (IS_ERR(tin4))
+		panic("failed to get pwm-tin4 clock for system timer");
+
+	tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv");
+	if (IS_ERR(tdiv4))
+		panic("failed to get pwm-tdiv4 clock for system timer");
+
+	clk_enable(tin4);
+}
+
+static void __init s5pv310_timer_init(void)
+{
+#ifdef CONFIG_LOCAL_TIMERS
+	twd_base = S5P_VA_TWD;
+#endif
+
+	s5pv310_timer_resources();
+	s5pv310_clockevent_init();
+	s5pv310_clocksource_init();
+}
+
+struct sys_timer s5pv310_timer = {
+	.init		= s5pv310_timer_init,
+};
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index b1d82cc..0d5bf8a 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -12,7 +12,7 @@ obj-				:=
 # Objects we always build independent of SoC choice
 
 obj-y				+= init.o
-obj-y				+= time.o
+obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET)   += time.o
 obj-y				+= clock.o
 obj-y				+= pwm-clock.o
 obj-y				+= gpio.o
-- 
1.6.2.5



From kgene.kim at samsung.com  Fri Jun 25 10:27:12 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 25 Jun 2010 23:27:12 +0900
Subject: [PATCH 3/8] ARM: S5PV310: Add Clock and PLL support
In-Reply-To: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
References: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277476037-8806-4-git-send-email-kgene.kim@samsung.com>

From: Changhwan Youn <chaos.youn at samsung.com>

This patch adds clock and pll support for S5PV310.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pv310/clock.c                   |  544 +++++++++++++++++++++++
 arch/arm/mach-s5pv310/include/mach/regs-clock.h |   60 +++
 arch/arm/plat-s5p/include/plat/pll.h            |   41 ++
 3 files changed, 645 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pv310/clock.c
 create mode 100644 arch/arm/mach-s5pv310/include/mach/regs-clock.h

diff --git a/arch/arm/mach-s5pv310/clock.c b/arch/arm/mach-s5pv310/clock.c
new file mode 100644
index 0000000..bb671d5
--- /dev/null
+++ b/arch/arm/mach-s5pv310/clock.c
@@ -0,0 +1,544 @@
+/* linux/arch/arm/mach-s5pv310/clock.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV310 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/cpu-freq.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/s5p-clock.h>
+#include <plat/clock-clksrc.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+static struct clk clk_sclk_hdmi27m = {
+	.name           = "sclk_hdmi27m",
+	.id             = -1,
+	.rate           = 27000000,
+};
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk clk_mout_apll = {
+	.clk	= {
+		.name		= "mout_apll",
+		.id		= -1,
+	},
+	.sources	= &clk_src_apll,
+	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
+	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk clk_mout_epll = {
+	.clk	= {
+		.name		= "mout_epll",
+		.id		= -1,
+	},
+	.sources	= &clk_src_epll,
+	.reg_src	= { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk clk_mout_mpll = {
+	.clk = {
+		.name		= "mout_mpll",
+		.id		= -1,
+	},
+	.sources	= &clk_src_mpll,
+	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 4, .size = 1 },
+};
+
+static struct clk *clkset_moutcore_list[] = {
+	[0] = &clk_mout_apll.clk,
+	[1] = &clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clkset_moutcore = {
+	.sources	= clkset_moutcore_list,
+	.nr_sources	= ARRAY_SIZE(clkset_moutcore_list),
+};
+
+static struct clksrc_clk clk_moutcore = {
+	.clk	= {
+		.name		= "moutcore",
+		.id		= -1,
+	},
+	.sources	= &clkset_moutcore,
+	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk clk_coreclk = {
+	.clk	= {
+		.name		= "core_clk",
+		.id		= -1,
+		.parent		= &clk_moutcore.clk,
+	},
+	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk clk_armclk = {
+	.clk	= {
+		.name		= "armclk",
+		.id		= -1,
+		.parent		= &clk_coreclk.clk,
+	},
+};
+
+static struct clksrc_clk clk_aclk_corem0 = {
+	.clk	= {
+		.name		= "aclk_corem0",
+		.id		= -1,
+		.parent		= &clk_coreclk.clk,
+	},
+	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_cores = {
+	.clk	= {
+		.name		= "aclk_cores",
+		.id		= -1,
+		.parent		= &clk_coreclk.clk,
+	},
+	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_corem1 = {
+	.clk	= {
+		.name		= "aclk_corem1",
+		.id		= -1,
+		.parent		= &clk_coreclk.clk,
+	},
+	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk clk_periph = {
+	.clk	= {
+		.name		= "periph",
+		.id		= -1,
+		.parent		= &clk_coreclk.clk,
+	},
+	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk clk_atbout = {
+	.clk	= {
+		.name		= "atbout",
+		.id		= -1,
+		.parent		= &clk_moutcore.clk,
+	},
+	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk clk_pclk_dbg = {
+	.clk	= {
+		.name		= "pclk_dbg",
+		.id		= -1,
+		.parent		= &clk_atbout.clk,
+	},
+	.reg_div	= { .reg = S5P_CLKDIV_CPU, .shift = 20, .size = 3 },
+};
+
+/* Core list of CMU_CORE side */
+
+static struct clk *clkset_corebus_list[] = {
+	[0] = &clk_mout_mpll.clk,
+	[1] = &clk_mout_apll.clk,
+};
+
+static struct clksrc_sources clkset_mout_corebus = {
+	.sources	= clkset_corebus_list,
+	.nr_sources	= ARRAY_SIZE(clkset_corebus_list),
+};
+
+static struct clksrc_clk clk_mout_corebus = {
+	.clk	= {
+		.name		= "mout_corebus",
+		.id		= -1,
+	},
+	.sources	= &clkset_mout_corebus,
+	.reg_src	= { .reg = S5P_CLKSRC_CPU, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk clk_sclk_dmc = {
+	.clk	= {
+		.name		= "sclk_dmc",
+		.id		= -1,
+		.parent		= &clk_mout_corebus.clk,
+	},
+	.reg_div	= { .reg = S5P_CLKDIV_CORE0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_cored = {
+	.clk	= {
+		.name		= "aclk_cored",
+		.id		= -1,
+		.parent		= &clk_sclk_dmc.clk,
+	},
+	.reg_div	= { .reg = S5P_CLKDIV_CORE0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_corep = {
+	.clk	= {
+		.name		= "aclk_corep",
+		.id		= -1,
+		.parent		= &clk_aclk_cored.clk,
+	},
+	.reg_div	= { .reg = S5P_CLKDIV_CORE0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk clk_aclk_acp = {
+	.clk	= {
+		.name		= "aclk_acp",
+		.id		= -1,
+		.parent		= &clk_mout_corebus.clk,
+	},
+	.reg_div	= { .reg = S5P_CLKDIV_CORE0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk clk_pclk_acp = {
+	.clk	= {
+		.name		= "pclk_acp",
+		.id		= -1,
+		.parent		= &clk_aclk_acp.clk,
+	},
+	.reg_div	= { .reg = S5P_CLKDIV_CORE0, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+static struct clk *clkset_aclk_top_list[] = {
+	[0] = &clk_mout_mpll.clk,
+	[1] = &clk_mout_apll.clk,
+};
+
+static struct clksrc_sources clkset_aclk_200 = {
+	.sources        = clkset_aclk_top_list,
+	.nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
+};
+
+static struct clksrc_clk clk_aclk_200 = {
+	.clk    = {
+		.name           = "aclk_200",
+		.id             = -1,
+	},
+	.sources        = &clkset_aclk_200,
+	.reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
+	.reg_div	= { .reg = S5P_CLKDIV_TOP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_sources clkset_aclk_100 = {
+	.sources        = clkset_aclk_top_list,
+	.nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
+};
+
+static struct clksrc_clk clk_aclk_100 = {
+	.clk    = {
+		.name           = "aclk_100",
+		.id             = -1,
+	},
+	.sources        = &clkset_aclk_100,
+	.reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
+	.reg_div	= { .reg = S5P_CLKDIV_TOP, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_sources clkset_aclk_160 = {
+	.sources        = clkset_aclk_top_list,
+	.nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
+};
+
+static struct clksrc_clk clk_aclk_160 = {
+	.clk    = {
+		.name           = "aclk_160",
+		.id             = -1,
+	},
+	.sources        = &clkset_aclk_160,
+	.reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
+	.reg_div	= { .reg = S5P_CLKDIV_TOP, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_sources clkset_aclk_133 = {
+	.sources        = clkset_aclk_top_list,
+	.nr_sources     = ARRAY_SIZE(clkset_aclk_top_list),
+};
+
+static struct clksrc_clk clk_aclk_133 = {
+	.clk    = {
+		.name           = "aclk_133",
+		.id             = -1,
+	},
+	.sources        = &clkset_aclk_133,
+	.reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
+	.reg_div	= { .reg = S5P_CLKDIV_TOP, .shift = 12, .size = 3 },
+};
+
+static struct clk *clkset_vpllsrc_list[] = {
+	[0] = &clk_fin_vpll,
+	[1] = &clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources clkset_vpllsrc = {
+	.sources	= clkset_vpllsrc_list,
+	.nr_sources	= ARRAY_SIZE(clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk clk_vpllsrc = {
+	.clk    = {
+		.name           = "vpll_src",
+		.id             = -1,
+	},
+	.sources        = &clkset_vpllsrc,
+	.reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_sclk_vpll_list[] = {
+	[0] = &clk_vpllsrc.clk,
+	[1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources clkset_sclk_vpll = {
+	.sources        = clkset_sclk_vpll_list,
+	.nr_sources     = ARRAY_SIZE(clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk clk_sclk_vpll = {
+	.clk    = {
+		.name           = "sclk_vpll",
+		.id             = -1,
+	},
+	.sources        = &clkset_sclk_vpll,
+	.reg_src        = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
+};
+
+static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
+}
+
+static struct clk init_clocks_disable[] = {
+	{
+		.name		= "timers",
+		.id		= -1,
+		.parent		= &clk_aclk_100.clk,
+		.enable		= s5pv310_clk_ip_peril_ctrl,
+		.ctrlbit	= (1<<24),
+	}
+};
+
+static struct clk init_clocks[] = {
+	/* Nothing here yet */
+};
+
+static struct clk *clkset_group_list[] = {
+	[0] = &clk_ext_xtal_mux,
+	[1] = &clk_xusbxti,
+	[2] = &clk_sclk_hdmi27m,
+	[6] = &clk_mout_mpll.clk,
+	[7] = &clk_mout_epll.clk,
+	[8] = &clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_group = {
+	.sources	= clkset_group_list,
+	.nr_sources	= ARRAY_SIZE(clkset_group_list),
+};
+
+static struct clksrc_clk clksrcs[] = {
+	{
+		.clk	= {
+			.name		= "uclk1",
+			.id		= 0,
+			.ctrlbit	= (1 << 0),
+			.enable		= s5pv310_clk_ip_peril_ctrl,
+		},
+		.sources = &clkset_group,
+		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+		.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+	}, {
+		.clk		= {
+			.name		= "uclk1",
+			.id		= 1,
+			.enable		= s5pv310_clk_ip_peril_ctrl,
+			.ctrlbit	= (1 << 1),
+		},
+		.sources = &clkset_group,
+		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+		.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+	}, {
+		.clk		= {
+			.name		= "uclk1",
+			.id		= 2,
+			.enable		= s5pv310_clk_ip_peril_ctrl,
+			.ctrlbit	= (1 << 2),
+		},
+		.sources = &clkset_group,
+		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+		.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+	}, {
+		.clk		= {
+			.name		= "uclk1",
+			.id		= 3,
+			.enable		= s5pv310_clk_ip_peril_ctrl,
+			.ctrlbit	= (1 << 3),
+		},
+		.sources = &clkset_group,
+		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+		.reg_div = { .reg = S5P_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+	}, {
+		.clk		= {
+			.name		= "sclk_pwm",
+			.id		= -1,
+			.enable		= s5pv310_clk_ip_peril_ctrl,
+			.ctrlbit	= (1 << 24),
+		},
+		.sources = &clkset_group,
+		.reg_src = { .reg = S5P_CLKSRC_PERIL0, .shift = 24, .size = 4 },
+		.reg_div = { .reg = S5P_CLKDIV_PERIL3, .shift = 0, .size = 4 },
+	},
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *sysclks[] = {
+	&clk_mout_apll,
+	&clk_mout_epll,
+	&clk_mout_mpll,
+	&clk_moutcore,
+	&clk_coreclk,
+	&clk_armclk,
+	&clk_aclk_corem0,
+	&clk_aclk_cores,
+	&clk_aclk_corem1,
+	&clk_periph,
+	&clk_atbout,
+	&clk_pclk_dbg,
+	&clk_mout_corebus,
+	&clk_sclk_dmc,
+	&clk_aclk_cored,
+	&clk_aclk_corep,
+	&clk_aclk_acp,
+	&clk_pclk_acp,
+	&clk_vpllsrc,
+	&clk_sclk_vpll,
+	&clk_aclk_200,
+	&clk_aclk_100,
+	&clk_aclk_160,
+	&clk_aclk_133,
+};
+
+void __init_or_cpufreq s5pv310_setup_clocks(void)
+{
+	struct clk *xtal_clk;
+	unsigned long apll;
+	unsigned long mpll;
+	unsigned long epll;
+	unsigned long vpll;
+	unsigned long vpllsrc;
+	unsigned long xtal;
+	unsigned long armclk;
+	unsigned long aclk_corem0;
+	unsigned long aclk_cores;
+	unsigned long aclk_corem1;
+	unsigned long periclk;
+	unsigned long sclk_dmc;
+	unsigned long aclk_cored;
+	unsigned long aclk_corep;
+	unsigned long aclk_acp;
+	unsigned long pclk_acp;
+	unsigned int ptr;
+
+	printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+	xtal_clk = clk_get(NULL, "xtal");
+	BUG_ON(IS_ERR(xtal_clk));
+
+	xtal = clk_get_rate(xtal_clk);
+	clk_put(xtal_clk);
+
+	printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+	apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON0), pll_4508);
+	mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON0), pll_4508);
+	epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON0),
+				__raw_readl(S5P_EPLL_CON1), pll_4500);
+
+	vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
+	vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
+				__raw_readl(S5P_VPLL_CON1), pll_4502);
+
+	clk_fout_apll.rate = apll;
+	clk_fout_mpll.rate = mpll;
+	clk_fout_epll.rate = epll;
+	clk_fout_vpll.rate = vpll;
+
+	printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
+			apll, mpll, epll, vpll);
+
+	armclk = clk_get_rate(&clk_armclk.clk);
+	aclk_corem0 = clk_get_rate(&clk_aclk_corem0.clk);
+	aclk_cores = clk_get_rate(&clk_aclk_cores.clk);
+	aclk_corem1 = clk_get_rate(&clk_aclk_corem1.clk);
+	periclk = clk_get_rate(&clk_periph.clk);
+	sclk_dmc = clk_get_rate(&clk_sclk_dmc.clk);
+	aclk_cored = clk_get_rate(&clk_aclk_cored.clk);
+	aclk_corep = clk_get_rate(&clk_aclk_corep.clk);
+	aclk_acp = clk_get_rate(&clk_aclk_acp.clk);
+	pclk_acp = clk_get_rate(&clk_pclk_acp.clk);
+
+	printk(KERN_INFO "S5PV310: ARMCLK=%ld, COREM0=%ld, CORES=%ld\n"
+			 "COREM1=%ld, PERI=%ld, DMC=%ld, CORED=%ld\n"
+			 "COREP=%ld, ACLK_ACP=%ld, PCLK_ACP=%ld",
+			armclk, aclk_corem0, aclk_cores, aclk_corem1,
+			periclk, sclk_dmc, aclk_cored, aclk_corep,
+			aclk_acp, pclk_acp);
+
+	clk_f.rate = armclk;
+	clk_h.rate = sclk_dmc;
+	clk_p.rate = periclk;
+
+	for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
+		s3c_set_clksrc(&clksrcs[ptr], true);
+}
+
+static struct clk *clks[] __initdata = {
+	/* Nothing here yet */
+};
+
+void __init s5pv310_register_clocks(void)
+{
+	struct clk *clkp;
+	int ret;
+	int ptr;
+
+	ret = s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
+	if (ret > 0)
+		printk(KERN_ERR "Failed to register %u clocks\n", ret);
+
+	for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+		s3c_register_clksrc(sysclks[ptr], 1);
+
+	s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+	s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
+
+	clkp = init_clocks_disable;
+	for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+		ret = s3c24xx_register_clock(clkp);
+		if (ret < 0) {
+			printk(KERN_ERR "Failed to register clock %s (%d)\n",
+			       clkp->name, ret);
+		}
+		(clkp->enable)(clkp, 0);
+	}
+
+	s3c_pwmclk_init();
+}
diff --git a/arch/arm/mach-s5pv310/include/mach/regs-clock.h b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
new file mode 100644
index 0000000..77f637f
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/regs-clock.h
@@ -0,0 +1,60 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV310 - Clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_CLOCK_H
+#define __ASM_ARCH_REGS_CLOCK_H __FILE__
+
+#include <mach/map.h>
+
+#define S5P_CLKREG(x)			(S3C_VA_SYS + (x))
+
+#define S5P_INFORM0			S5P_CLKREG(0x800)
+
+#define S5P_EPLL_CON0			S5P_CLKREG(0x1C110)
+#define S5P_EPLL_CON1			S5P_CLKREG(0x1C114)
+#define S5P_VPLL_CON0			S5P_CLKREG(0x1C120)
+#define S5P_VPLL_CON1			S5P_CLKREG(0x1C124)
+
+#define S5P_CLKSRC_TOP0			S5P_CLKREG(0x1C210)
+#define S5P_CLKSRC_TOP1			S5P_CLKREG(0x1C214)
+
+#define S5P_CLKSRC_PERIL0		S5P_CLKREG(0x1C250)
+
+#define S5P_CLKDIV_TOP			S5P_CLKREG(0x1C510)
+
+#define S5P_CLKDIV_PERIL0		S5P_CLKREG(0x1C550)
+#define S5P_CLKDIV_PERIL1		S5P_CLKREG(0x1C554)
+#define S5P_CLKDIV_PERIL2		S5P_CLKREG(0x1C558)
+#define S5P_CLKDIV_PERIL3		S5P_CLKREG(0x1C55C)
+#define S5P_CLKDIV_PERIL4		S5P_CLKREG(0x1C560)
+#define S5P_CLKDIV_PERIL5		S5P_CLKREG(0x1C564)
+
+#define S5P_CLKGATE_IP_PERIL		S5P_CLKREG(0x1C950)
+
+#define S5P_CLKDIV_CORE0		S5P_CLKREG(0x20500)
+
+#define S5P_APLL_LOCK			S5P_CLKREG(0x24000)
+#define S5P_MPLL_LOCK			S5P_CLKREG(0x24004)
+#define S5P_APLL_CON0			S5P_CLKREG(0x24100)
+#define S5P_APLL_CON1			S5P_CLKREG(0x24104)
+#define S5P_MPLL_CON0			S5P_CLKREG(0x24108)
+#define S5P_MPLL_CON1			S5P_CLKREG(0x2410C)
+
+#define S5P_CLKSRC_CPU			S5P_CLKREG(0x24200)
+#define S5P_CLKMUX_STATCPU		S5P_CLKREG(0x24400)
+
+#define S5P_CLKDIV_CPU			S5P_CLKREG(0x24500)
+#define S5P_CLKDIV_STATCPU		S5P_CLKREG(0x24600)
+
+#define S5P_CLKGATE_SCLKCPU		S5P_CLKREG(0x24800)
+
+#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/plat-s5p/include/plat/pll.h b/arch/arm/plat-s5p/include/plat/pll.h
index 7db3227..4e8fe08 100644
--- a/arch/arm/plat-s5p/include/plat/pll.h
+++ b/arch/arm/plat-s5p/include/plat/pll.h
@@ -46,6 +46,47 @@ static inline unsigned long s5p_get_pll45xx(unsigned long baseclk, u32 pll_con,
 	return (unsigned long)fvco;
 }
 
+#define PLL46XX_KDIV_MASK	(0xFFFF)
+#define PLL46XX_MDIV_MASK	(0x1FF)
+#define PLL46XX_PDIV_MASK	(0x3F)
+#define PLL46XX_SDIV_MASK	(0x7)
+#define PLL46XX_MDIV_SHIFT	(16)
+#define PLL46XX_PDIV_SHIFT	(8)
+#define PLL46XX_SDIV_SHIFT	(0)
+
+enum pll46xx_type_t {
+	pll_4600,
+	pll_4650,
+};
+
+static inline unsigned long s5p_get_pll46xx(unsigned long baseclk,
+					    u32 pll_con0, u32 pll_con1,
+					    enum pll46xx_type_t pll_type)
+{
+	unsigned long result;
+	u32 mdiv, pdiv, sdiv, kdiv;
+	u64 tmp;
+
+	mdiv = (pll_con0 >> PLL46XX_MDIV_SHIFT) & PLL46XX_MDIV_MASK;
+	pdiv = (pll_con0 >> PLL46XX_PDIV_SHIFT) & PLL46XX_PDIV_MASK;
+	sdiv = (pll_con0 >> PLL46XX_SDIV_SHIFT) & PLL46XX_SDIV_MASK;
+	kdiv = pll_con1 & PLL46XX_KDIV_MASK;
+
+	tmp = baseclk;
+
+	if (pll_type == pll_4600) {
+		tmp *= (mdiv << 16) + kdiv;
+		do_div(tmp, (pdiv << sdiv));
+		result = tmp >> 16;
+	} else {
+		tmp *= (mdiv << 10) + kdiv;
+		do_div(tmp, (pdiv << sdiv));
+		result = tmp >> 10;
+	}
+
+	return result;
+}
+
 #define PLL90XX_MDIV_MASK	(0xFF)
 #define PLL90XX_PDIV_MASK	(0x3F)
 #define PLL90XX_SDIV_MASK	(0x7)
-- 
1.6.2.5



From kgene.kim at samsung.com  Fri Jun 25 10:27:11 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Fri, 25 Jun 2010 23:27:11 +0900
Subject: [PATCH 2/8] ARM: S5PV310: Add new CPU initialization support
In-Reply-To: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
References: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <1277476037-8806-3-git-send-email-kgene.kim@samsung.com>

From: Changhwan Youn <chaos.youn at samsung.com>

This patch adds Samsung's S5PV310/S5PC210 CPU support.
The S5PV310/S5PC210 integrates a ARM Cortex A9 multi-core.

Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pv310/cpu.c                      |  123 +++++++++++++
 arch/arm/mach-s5pv310/headsmp.S                  |   41 ++++
 arch/arm/mach-s5pv310/include/mach/debug-macro.S |   36 ++++
 arch/arm/mach-s5pv310/include/mach/entry-macro.S |   84 +++++++++
 arch/arm/mach-s5pv310/include/mach/gpio.h        |  135 ++++++++++++++
 arch/arm/mach-s5pv310/include/mach/hardware.h    |   18 ++
 arch/arm/mach-s5pv310/include/mach/io.h          |   26 +++
 arch/arm/mach-s5pv310/include/mach/map.h         |   63 +++++++
 arch/arm/mach-s5pv310/include/mach/memory.h      |   22 +++
 arch/arm/mach-s5pv310/include/mach/smp.h         |   29 +++
 arch/arm/mach-s5pv310/include/mach/system.h      |   22 +++
 arch/arm/mach-s5pv310/include/mach/timex.h       |   29 +++
 arch/arm/mach-s5pv310/include/mach/uncompress.h  |   27 +++
 arch/arm/mach-s5pv310/include/mach/vmalloc.h     |   22 +++
 arch/arm/mach-s5pv310/init.c                     |   40 ++++
 arch/arm/mach-s5pv310/platsmp.c                  |  212 ++++++++++++++++++++++
 arch/arm/mach-s5pv310/setup-i2c0.c               |   20 ++
 arch/arm/plat-s5p/cpu.c                          |   12 ++
 arch/arm/plat-s5p/include/plat/map-s5p.h         |   12 ++
 arch/arm/plat-s5p/include/plat/s5pv310.h         |   33 ++++
 20 files changed, 1006 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pv310/cpu.c
 create mode 100644 arch/arm/mach-s5pv310/headsmp.S
 create mode 100644 arch/arm/mach-s5pv310/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-s5pv310/include/mach/entry-macro.S
 create mode 100644 arch/arm/mach-s5pv310/include/mach/gpio.h
 create mode 100644 arch/arm/mach-s5pv310/include/mach/hardware.h
 create mode 100644 arch/arm/mach-s5pv310/include/mach/io.h
 create mode 100644 arch/arm/mach-s5pv310/include/mach/map.h
 create mode 100644 arch/arm/mach-s5pv310/include/mach/memory.h
 create mode 100644 arch/arm/mach-s5pv310/include/mach/smp.h
 create mode 100644 arch/arm/mach-s5pv310/include/mach/system.h
 create mode 100644 arch/arm/mach-s5pv310/include/mach/timex.h
 create mode 100644 arch/arm/mach-s5pv310/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-s5pv310/include/mach/vmalloc.h
 create mode 100644 arch/arm/mach-s5pv310/init.c
 create mode 100644 arch/arm/mach-s5pv310/platsmp.c
 create mode 100644 arch/arm/mach-s5pv310/setup-i2c0.c
 create mode 100644 arch/arm/plat-s5p/include/plat/s5pv310.h

diff --git a/arch/arm/mach-s5pv310/cpu.c b/arch/arm/mach-s5pv310/cpu.c
new file mode 100644
index 0000000..ac7a5e8
--- /dev/null
+++ b/arch/arm/mach-s5pv310/cpu.c
@@ -0,0 +1,123 @@
+/* linux/arch/arm/mach-s5pv310/cpu.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/sched.h>
+#include <linux/sysdev.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+
+#include <asm/proc-fns.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/s5pv310.h>
+
+#include <mach/regs-irq.h>
+
+void __iomem *gic_cpu_base_addr;
+
+extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
+			 unsigned int irq_start);
+extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
+
+/* Initial IO mappings */
+static struct map_desc s5pv310_iodesc[] __initdata = {
+	{
+		.virtual	= (unsigned long)S5P_VA_COREPERI_BASE,
+		.pfn		= __phys_to_pfn(S5PV310_PA_COREPERI),
+		.length		= SZ_8K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_COMBINER_BASE,
+		.pfn		= __phys_to_pfn(S5PV310_PA_COMBINER),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	}, {
+		.virtual	= (unsigned long)S5P_VA_L2CC,
+		.pfn		= __phys_to_pfn(S5PV310_PA_L2CC),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+};
+
+static void s5pv310_idle(void)
+{
+	if (!need_resched())
+		cpu_do_idle();
+
+	local_irq_enable();
+}
+
+/* s5pv310_map_io
+ *
+ * register the standard cpu IO areas
+*/
+void __init s5pv310_map_io(void)
+{
+	iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
+}
+
+void __init s5pv310_init_clocks(int xtal)
+{
+	printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+	s3c24xx_register_baseclocks(xtal);
+	s5p_register_clocks(xtal);
+	s5pv310_register_clocks();
+	s5pv310_setup_clocks();
+}
+
+void __init s5pv310_init_irq(void)
+{
+	int irq;
+
+	gic_cpu_base_addr = S5P_VA_GIC_CPU;
+	gic_dist_init(0, S5P_VA_GIC_DIST, IRQ_LOCALTIMER);
+	gic_cpu_init(0, S5P_VA_GIC_CPU);
+
+	for (irq = 0; irq < MAX_COMBINER_NR; irq++)
+		combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
+			      COMBINER_IRQ(irq, 0));
+
+	for (irq = 0; irq < MAX_COMBINER_NR; irq++)
+		combiner_cascade_irq(irq, IRQ_SPI(irq));
+
+	/* The parameters of s5p_init_irq() are for VIC init.
+	 * Theses parameters should be NULL and 0 because S5PV310
+	 * uses GIC instead of VIC.
+	 */
+	s5p_init_irq(NULL, 0);
+}
+
+struct sysdev_class s5pv310_sysclass = {
+	.name	= "s5pv310-core",
+};
+
+static struct sys_device s5pv310_sysdev = {
+	.cls	= &s5pv310_sysclass,
+};
+
+static int __init s5pv310_core_init(void)
+{
+	return sysdev_class_register(&s5pv310_sysclass);
+}
+
+core_initcall(s5pv310_core_init);
+
+int __init s5pv310_init(void)
+{
+	printk(KERN_INFO "S5PV310: Initializing architecture\n");
+
+	/* set idle function */
+	pm_idle = s5pv310_idle;
+
+	return sysdev_register(&s5pv310_sysdev);
+}
diff --git a/arch/arm/mach-s5pv310/headsmp.S b/arch/arm/mach-s5pv310/headsmp.S
new file mode 100644
index 0000000..164b7b0
--- /dev/null
+++ b/arch/arm/mach-s5pv310/headsmp.S
@@ -0,0 +1,41 @@
+/*
+ *  linux/arch/arm/mach-s5pv310/headsmp.S
+ *
+ *  Cloned from linux/arch/arm/mach-realview/headsmp.S
+ *
+ *  Copyright (c) 2003 ARM Limited
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+	__INIT
+
+/*
+ * s5pv310 specific entry point for secondary CPUs.  This provides
+ * a "holding pen" into which all secondary cores are held until we're
+ * ready for them to initialise.
+ */
+ENTRY(s5pv310_secondary_startup)
+	mrc	p15, 0, r0, c0, c0, 5
+	and	r0, r0, #15
+	adr	r4, 1f
+	ldmia	r4, {r5, r6}
+	sub	r4, r4, r5
+	add	r6, r6, r4
+pen:	ldr	r7, [r6]
+	cmp	r7, r0
+	bne	pen
+
+	/*
+	 * we've been released from the holding pen: secondary_stack
+	 * should now contain the SVC stack for this core
+	 */
+	b	secondary_startup
+
+1:	.long	.
+	.long	pen_release
diff --git a/arch/arm/mach-s5pv310/include/mach/debug-macro.S b/arch/arm/mach-s5pv310/include/mach/debug-macro.S
new file mode 100644
index 0000000..6fb3893
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/debug-macro.S
@@ -0,0 +1,36 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/debug-macro.S
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* pull in the relevant register and map files. */
+
+#include <mach/map.h>
+
+	/* note, for the boot process to work we have to keep the UART
+	 * virtual address aligned to an 1MiB boundary for the L1
+	 * mapping the head code makes. We keep the UART virtual address
+	 * aligned and add in the offset when we load the value here.
+	 */
+
+	.macro addruart, rx, tmp
+		mrc	p15, 0, \rx, c1, c0
+		tst	\rx, #1
+		ldreq	\rx, = S3C_PA_UART
+		ldrne	\rx, = S3C_VA_UART
+#if CONFIG_DEBUG_S3C_UART != 0
+		add	\rx, \rx, #(0x10000 * CONFIG_DEBUG_S3C_UART)
+#endif
+	.endm
+
+#define fifo_full fifo_full_s5pv210
+#define fifo_level fifo_level_s5pv210
+
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5pv310/include/mach/entry-macro.S b/arch/arm/mach-s5pv310/include/mach/entry-macro.S
new file mode 100644
index 0000000..e600e1d
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/entry-macro.S
@@ -0,0 +1,84 @@
+/* arch/arm/mach-s5pv310/include/mach/entry-macro.S
+ *
+ * Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for S5PV310 platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+
+#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
+
+		.macro	disable_fiq
+		.endm
+
+		.macro  get_irqnr_preamble, base, tmp
+		ldr	\base, =gic_cpu_base_addr
+		ldr	\base, [\base]
+		.endm
+
+		.macro  arch_ret_to_user, tmp1, tmp2
+		.endm
+
+		/*
+		 * The interrupt numbering scheme is defined in the
+		 * interrupt controller spec.  To wit:
+		 *
+		 * Interrupts 0-15 are IPI
+		 * 16-28 are reserved
+		 * 29-31 are local.  We allow 30 to be used for the watchdog.
+		 * 32-1020 are global
+		 * 1021-1022 are reserved
+		 * 1023 is "spurious" (no interrupt)
+		 *
+		 * For now, we ignore all local interrupts so only return an interrupt if it's
+		 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
+		 *
+		 * A simple read from the controller will tell us the number of the highest
+                 * priority enabled interrupt.  We then just need to check whether it is in the
+		 * valid range for an IRQ (30-1020 inclusive).
+		 */
+
+		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+		ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
+
+		ldr	\tmp, =1021
+
+		bic     \irqnr, \irqstat, #0x1c00
+
+		cmp     \irqnr, #29
+		cmpcc	\irqnr, \irqnr
+		cmpne	\irqnr, \tmp
+		cmpcs	\irqnr, \irqnr
+		addne	\irqnr, \irqnr, #32
+
+		.endm
+
+		/* We assume that irqstat (the raw value of the IRQ acknowledge
+		 * register) is preserved from the macro above.
+		 * If there is an IPI, we immediately signal end of interrupt on the
+		 * controller, since this requires the original irqstat value which
+		 * we won't easily be able to recreate later.
+		 */
+
+		.macro test_for_ipi, irqnr, irqstat, base, tmp
+		bic	\irqnr, \irqstat, #0x1c00
+		cmp	\irqnr, #16
+		strcc	\irqstat, [\base, #GIC_CPU_EOI]
+		cmpcs	\irqnr, \irqnr
+		.endm
+
+		/* As above, this assumes that irqstat and base are preserved.. */
+
+		.macro test_for_ltirq, irqnr, irqstat, base, tmp
+		bic	\irqnr, \irqstat, #0x1c00
+		mov	\tmp, #0
+		cmp	\irqnr, #29
+		moveq	\tmp, #1
+		streq	\irqstat, [\base, #GIC_CPU_EOI]
+		cmp	\tmp, #0
+		.endm
diff --git a/arch/arm/mach-s5pv310/include/mach/gpio.h b/arch/arm/mach-s5pv310/include/mach/gpio.h
new file mode 100644
index 0000000..20cb80c
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/gpio.h
@@ -0,0 +1,135 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/gpio.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV310 - GPIO lib support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H __FILE__
+
+#define gpio_get_value	__gpio_get_value
+#define gpio_set_value	__gpio_set_value
+#define gpio_cansleep	__gpio_cansleep
+#define gpio_to_irq	__gpio_to_irq
+
+/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
+
+/* GPIO bank sizes */
+#define S5PV310_GPIO_A0_NR	(8)
+#define S5PV310_GPIO_A1_NR	(6)
+#define S5PV310_GPIO_B_NR	(8)
+#define S5PV310_GPIO_C0_NR	(5)
+#define S5PV310_GPIO_C1_NR	(5)
+#define S5PV310_GPIO_D0_NR	(4)
+#define S5PV310_GPIO_D1_NR	(4)
+#define S5PV310_GPIO_E0_NR	(5)
+#define S5PV310_GPIO_E1_NR	(8)
+#define S5PV310_GPIO_E2_NR	(6)
+#define S5PV310_GPIO_E3_NR	(8)
+#define S5PV310_GPIO_E4_NR	(8)
+#define S5PV310_GPIO_F0_NR	(8)
+#define S5PV310_GPIO_F1_NR	(8)
+#define S5PV310_GPIO_F2_NR	(8)
+#define S5PV310_GPIO_F3_NR	(6)
+#define S5PV310_GPIO_J0_NR	(8)
+#define S5PV310_GPIO_J1_NR	(5)
+#define S5PV310_GPIO_K0_NR	(7)
+#define S5PV310_GPIO_K1_NR	(7)
+#define S5PV310_GPIO_K2_NR	(7)
+#define S5PV310_GPIO_K3_NR	(7)
+#define S5PV310_GPIO_L0_NR	(8)
+#define S5PV310_GPIO_L1_NR	(3)
+#define S5PV310_GPIO_L2_NR	(8)
+#define S5PV310_GPIO_X0_NR	(8)
+#define S5PV310_GPIO_X1_NR	(8)
+#define S5PV310_GPIO_X2_NR	(8)
+#define S5PV310_GPIO_X3_NR	(8)
+#define S5PV310_GPIO_Z_NR	(7)
+
+/* GPIO bank numbers */
+
+#define S5PV310_GPIO_NEXT(__gpio) \
+	((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+
+enum s5p_gpio_number {
+	S5PV310_GPIO_A0_START	= 0,
+	S5PV310_GPIO_A1_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_A0),
+	S5PV310_GPIO_B_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_A1),
+	S5PV310_GPIO_C0_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_B),
+	S5PV310_GPIO_C1_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_C0),
+	S5PV310_GPIO_D0_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_C1),
+	S5PV310_GPIO_D1_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_D0),
+	S5PV310_GPIO_E0_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_D1),
+	S5PV310_GPIO_E1_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_E0),
+	S5PV310_GPIO_E2_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_E1),
+	S5PV310_GPIO_E3_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_E2),
+	S5PV310_GPIO_E4_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_E3),
+	S5PV310_GPIO_F0_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_E4),
+	S5PV310_GPIO_F1_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_F0),
+	S5PV310_GPIO_F2_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_F1),
+	S5PV310_GPIO_F3_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_F2),
+	S5PV310_GPIO_J0_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_F3),
+	S5PV310_GPIO_J1_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_J0),
+	S5PV310_GPIO_K0_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_J1),
+	S5PV310_GPIO_K1_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_K0),
+	S5PV310_GPIO_K2_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_K1),
+	S5PV310_GPIO_K3_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_K2),
+	S5PV310_GPIO_L0_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_K3),
+	S5PV310_GPIO_L1_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_L0),
+	S5PV310_GPIO_L2_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_L1),
+	S5PV310_GPIO_X0_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_L2),
+	S5PV310_GPIO_X1_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_X0),
+	S5PV310_GPIO_X2_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_X1),
+	S5PV310_GPIO_X3_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_X2),
+	S5PV310_GPIO_Z_START	= S5PV310_GPIO_NEXT(S5PV310_GPIO_X3),
+};
+
+/* S5PV310 GPIO number definitions */
+#define S5PV310_GPA0(_nr)	(S5PV310_GPIO_A0_START + (_nr))
+#define S5PV310_GPA1(_nr)	(S5PV310_GPIO_A1_START + (_nr))
+#define S5PV310_GPB(_nr)	(S5PV310_GPIO_B_START + (_nr))
+#define S5PV310_GPC0(_nr)	(S5PV310_GPIO_C0_START + (_nr))
+#define S5PV310_GPC1(_nr)	(S5PV310_GPIO_C1_START + (_nr))
+#define S5PV310_GPD0(_nr)	(S5PV310_GPIO_D0_START + (_nr))
+#define S5PV310_GPD1(_nr)	(S5PV310_GPIO_D1_START + (_nr))
+#define S5PV310_GPE0(_nr)	(S5PV310_GPIO_E0_START + (_nr))
+#define S5PV310_GPE1(_nr)	(S5PV310_GPIO_E1_START + (_nr))
+#define S5PV310_GPE2(_nr)	(S5PV310_GPIO_E2_START + (_nr))
+#define S5PV310_GPE3(_nr)	(S5PV310_GPIO_E3_START + (_nr))
+#define S5PV310_GPE4(_nr)	(S5PV310_GPIO_E4_START + (_nr))
+#define S5PV310_GPF0(_nr)	(S5PV310_GPIO_F0_START + (_nr))
+#define S5PV310_GPF1(_nr)	(S5PV310_GPIO_F1_START + (_nr))
+#define S5PV310_GPF2(_nr)	(S5PV310_GPIO_F2_START + (_nr))
+#define S5PV310_GPF3(_nr)	(S5PV310_GPIO_F3_START + (_nr))
+#define S5PV310_GPJ0(_nr)	(S5PV310_GPIO_J0_START + (_nr))
+#define S5PV310_GPJ1(_nr)	(S5PV310_GPIO_J1_START + (_nr))
+#define S5PV310_GPK0(_nr)	(S5PV310_GPIO_K0_START + (_nr))
+#define S5PV310_GPK1(_nr)	(S5PV310_GPIO_K1_START + (_nr))
+#define S5PV310_GPK2(_nr)	(S5PV310_GPIO_K2_START + (_nr))
+#define S5PV310_GPK3(_nr)	(S5PV310_GPIO_K3_START + (_nr))
+#define S5PV310_GPL0(_nr)	(S5PV310_GPIO_L0_START + (_nr))
+#define S5PV310_GPL1(_nr)	(S5PV310_GPIO_L1_START + (_nr))
+#define S5PV310_GPL2(_nr)	(S5PV310_GPIO_L2_START + (_nr))
+#define S5PV310_GPX0(_nr)	(S5PV310_GPIO_X0_START + (_nr))
+#define S5PV310_GPX1(_nr)	(S5PV310_GPIO_X1_START + (_nr))
+#define S5PV310_GPX2(_nr)	(S5PV310_GPIO_X2_START + (_nr))
+#define S5PV310_GPX3(_nr)	(S5PV310_GPIO_X3_START + (_nr))
+#define S5PV310_GPZ(_nr)	(S5PV310_GPIO_Z_START + (_nr))
+
+/* the end of the S5PV310 specific gpios */
+#define S5PV310_GPIO_END	(S5PV310_GPZ(S5PV310_GPIO_Z_NR) + 1)
+#define S3C_GPIO_END		S5PV310_GPIO_END
+
+/* define the number of gpios we need to the one after the GPZ() range */
+#define ARCH_NR_GPIOS		(S5PV310_GPZ(S5PV310_GPIO_Z_NR) +	\
+				 CONFIG_SAMSUNG_GPIO_EXTRA + 1)
+
+#include <asm-generic/gpio.h>
+
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/hardware.h b/arch/arm/mach-s5pv310/include/mach/hardware.h
new file mode 100644
index 0000000..28ff988
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/hardware.h
@@ -0,0 +1,18 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/hardware.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV310 - Hardware support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H __FILE__
+
+/* currently nothing here, placeholder */
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/io.h b/arch/arm/mach-s5pv310/include/mach/io.h
new file mode 100644
index 0000000..8a7f912
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/io.h
@@ -0,0 +1,26 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/io.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Copyright 2008-2010 Ben Dooks <ben-linux at fluff.org>
+ *
+ * Based on arch/arm/mach-s5p6442/include/mach/io.h
+ *
+ * Default IO routines for S5PV310
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H __FILE__
+
+/* No current ISA/PCI bus support. */
+#define __io(a)		__typesafe_io(a)
+#define __mem_pci(a)	(a)
+
+#define IO_SPACE_LIMIT (0xFFFFFFFF)
+
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
new file mode 100644
index 0000000..e44438e
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -0,0 +1,63 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/map.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV310 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+
+#include <plat/map-base.h>
+
+/* */
+#define S3C_UART_OFFSET			(0x10000)
+
+#include <plat/map-s5p.h>
+
+#define S5PV310_PA_CHIPID		(0x10000000)
+#define S5P_PA_CHIPID			S5PV310_PA_CHIPID
+
+#define S5PV310_PA_SYSCON		(0x10020000)
+#define S5P_PA_SYSCON			S5PV310_PA_SYSCON
+
+#define S5PV310_PA_COMBINER		(0x10448000)
+
+#define S5PV310_PA_COREPERI		(0x10500000)
+#define S5PV310_PA_GIC_CPU		(0x10500100)
+#define S5PV310_PA_TWD			(0x10500600)
+#define S5PV310_PA_GIC_DIST		(0x10501000)
+#define S5PV310_PA_L2CC			(0x10502000)
+
+#define S5PV310_PA_GPIO			(0x11000000)
+#define S5P_PA_GPIO			S5PV310_PA_GPIO
+
+#define S5PV310_PA_UART			(0x13800000)
+
+#define S5P_PA_UART(x)			(S5PV310_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0			S5P_PA_UART(0)
+#define S5P_PA_UART1			S5P_PA_UART(1)
+#define S5P_PA_UART2			S5P_PA_UART(2)
+#define S5P_PA_UART3			S5P_PA_UART(3)
+#define S5P_PA_UART4			S5P_PA_UART(4)
+
+#define S5P_SZ_UART			SZ_256
+
+#define S5PV310_PA_IIC0			(0x13860000)
+
+#define S5PV310_PA_TIMER		(0x139D0000)
+#define S5P_PA_TIMER			S5PV310_PA_TIMER
+
+#define S5PV310_PA_SDRAM		(0x40000000)
+#define S5P_PA_SDRAM			S5PV310_PA_SDRAM
+
+/* compatibiltiy defines. */
+#define S3C_PA_UART			S5PV310_PA_UART
+#define S3C_PA_IIC			S5PV310_PA_IIC0
+
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/memory.h b/arch/arm/mach-s5pv310/include/mach/memory.h
new file mode 100644
index 0000000..1dffb48
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/memory.h
@@ -0,0 +1,22 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/memory.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV310 - Memory definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H __FILE__
+
+#define PHYS_OFFSET		UL(0x40000000)
+
+/* Maximum of 256MiB in one bank */
+#define MAX_PHYSMEM_BITS	32
+#define SECTION_SIZE_BITS	28
+
+#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/smp.h b/arch/arm/mach-s5pv310/include/mach/smp.h
new file mode 100644
index 0000000..990f3ba
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/smp.h
@@ -0,0 +1,29 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/smp.h
+ *
+ * Cloned from arch/arm/mach-realview/include/mach/smp.h
+*/
+
+#ifndef ASM_ARCH_SMP_H
+#define ASM_ARCH_SMP_H __FILE__
+
+#include <asm/hardware/gic.h>
+
+extern void __iomem *gic_cpu_base_addr;
+
+#define hard_smp_processor_id()			\
+	({						\
+		unsigned int cpunum;			\
+		__asm__("mrc p15, 0, %0, c0, c0, 5"	\
+			: "=r" (cpunum));		\
+		cpunum &= 0x03;				\
+	})
+
+/*
+ * We use IRQ1 as the IPI
+ */
+static inline void smp_cross_call(const struct cpumask *mask)
+{
+	gic_raise_softirq(mask, 1);
+}
+
+#endif
diff --git a/arch/arm/mach-s5pv310/include/mach/system.h b/arch/arm/mach-s5pv310/include/mach/system.h
new file mode 100644
index 0000000..d10c009
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/system.h
@@ -0,0 +1,22 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/system.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV310 - system support header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H __FILE__
+
+#include <plat/system-reset.h>
+
+static void arch_idle(void)
+{
+	/* nothing here yet */
+}
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/timex.h b/arch/arm/mach-s5pv310/include/mach/timex.h
new file mode 100644
index 0000000..bd2359b
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/timex.h
@@ -0,0 +1,29 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/timex.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Copyright (c) 2003-2010 Simtec Electronics
+ *	Ben Dooks <ben at simtec.co.uk>
+ *
+ * Based on arch/arm/mach-s5p6442/include/mach/timex.h
+ *
+ * S5PV310 - time parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H __FILE__
+
+/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
+ * a variable is useless. It seems as long as we make our timers an
+ * exact multiple of HZ, any value that makes a 1->1 correspondence
+ * for the time conversion functions to/from jiffies is acceptable.
+*/
+
+#define CLOCK_TICK_RATE 12000000
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/uncompress.h b/arch/arm/mach-s5pv310/include/mach/uncompress.h
new file mode 100644
index 0000000..ad88c24
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/uncompress.h
@@ -0,0 +1,27 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/uncompress.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * S5PV310 - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H __FILE__
+
+#include <mach/map.h>
+#include <plat/uncompress.h>
+
+static void arch_detect_cpu(void)
+{
+	/* we do not need to do any cpu detection here at the moment. */
+
+	fifo_mask = S5PV210_UFSTAT_TXMASK;
+	fifo_max = 63 << S5PV210_UFSTAT_TXSHIFT;
+}
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pv310/include/mach/vmalloc.h b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
new file mode 100644
index 0000000..426d997
--- /dev/null
+++ b/arch/arm/mach-s5pv310/include/mach/vmalloc.h
@@ -0,0 +1,22 @@
+/* linux/arch/arm/mach-s5pv310/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Copyright 2010 Ben Dooks <ben-linux at fluff.org>
+ *
+ * Based on arch/arm/mach-s5p6440/include/mach/vmalloc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S5PV310 vmalloc definition
+*/
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H __FILE__
+
+#define VMALLOC_END	  (0xE0000000)
+
+#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s5pv310/init.c b/arch/arm/mach-s5pv310/init.c
new file mode 100644
index 0000000..6c152c6
--- /dev/null
+++ b/arch/arm/mach-s5pv310/init.c
@@ -0,0 +1,40 @@
+/* linux/arch/arm/mach-s5pv310/init.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/serial_core.h>
+
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/regs-serial.h>
+
+static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
+	[0] = {
+		.name		= "uclk1",
+		.divisor	= 1,
+		.min_baud	= 0,
+		.max_baud	= 0,
+	},
+};
+
+/* uart registration process */
+void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+	struct s3c2410_uartcfg *tcfg = cfg;
+	u32 ucnt;
+
+	for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
+		if (!tcfg->clocks) {
+			tcfg->clocks = s5pv310_serial_clocks;
+			tcfg->clocks_size = ARRAY_SIZE(s5pv310_serial_clocks);
+		}
+	}
+
+	s3c24xx_init_uartdevs("s5pv310-uart", s5p_uart_resources, cfg, no);
+}
diff --git a/arch/arm/mach-s5pv310/platsmp.c b/arch/arm/mach-s5pv310/platsmp.c
new file mode 100644
index 0000000..9325ac2
--- /dev/null
+++ b/arch/arm/mach-s5pv310/platsmp.c
@@ -0,0 +1,212 @@
+/* linux/arch/arm/mach-s5pv310/platsmp.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Cloned from linux/arch/arm/mach-realview/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+
+#include <asm/cacheflush.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/localtimer.h>
+#include <asm/unified.h>
+
+#include <asm/smp_scu.h>
+#include <mach/regs-clock.h>
+
+extern void s5pv310_secondary_startup(void);
+
+/*
+ * control for which core is the next to come out of the secondary
+ * boot "holding pen"
+ */
+volatile int __cpuinitdata pen_release = -1;
+
+static void __iomem *scu_base_addr(void)
+{
+	return (void __iomem *)(S5P_VA_SCU);
+}
+
+static inline unsigned int get_core_count(void)
+{
+	void __iomem *scu_base = scu_base_addr();
+	if (scu_base)
+		return scu_get_core_count(scu_base);
+	return 1;
+}
+
+static DEFINE_SPINLOCK(boot_lock);
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+	trace_hardirqs_off();
+
+	/*
+	 * if any interrupts are already enabled for the primary
+	 * core (e.g. timer irq), then they will not have been enabled
+	 * for us: do so
+	 */
+	gic_cpu_init(0, gic_cpu_base_addr);
+
+	/*
+	 * let the primary processor know we're out of the
+	 * pen, then head off into the C entry point
+	 */
+	pen_release = -1;
+	smp_wmb();
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long timeout;
+
+	/*
+	 * set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+	/*
+	 * The secondary processor is waiting to be released from
+	 * the holding pen - release it, then wait for it to flag
+	 * that it has been released by resetting pen_release.
+	 *
+	 * Note that "pen_release" is the hardware CPU ID, whereas
+	 * "cpu" is Linux's internal ID.
+	 */
+	pen_release = cpu;
+	flush_cache_all();
+
+	/*
+	 * XXX
+	 *
+	 * This is a later addition to the booting protocol: the
+	 * bootMonitor now puts secondary cores into WFI, so
+	 * poke_milo() no longer gets the cores moving; we need
+	 * to send a soft interrupt to wake the secondary core.
+	 * Use smp_cross_call() for this, since there's little
+	 * point duplicating the code here
+	 */
+	smp_cross_call(cpumask_of(cpu));
+
+	timeout = jiffies + (1 * HZ);
+	while (time_before(jiffies, timeout)) {
+		smp_rmb();
+		if (pen_release == -1)
+			break;
+
+		udelay(10);
+	}
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return pen_release != -1 ? -ENOSYS : 0;
+}
+
+static void __init poke_milo(void)
+{
+	/* nobody is to be released from the pen yet */
+	pen_release = -1;
+
+	/*
+	 * Write the address of secondary startup into the system-wide flags
+	 * register. The BootMonitor waits for this register to become
+	 * non-zero.
+	 */
+	__raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_INFORM0);
+
+	mb();
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+	unsigned int i, ncores = get_core_count();
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+}
+
+void __init smp_prepare_cpus(unsigned int max_cpus)
+{
+	unsigned int ncores = get_core_count();
+	unsigned int cpu = smp_processor_id();
+	int i;
+
+	/* sanity check */
+	if (ncores == 0) {
+		printk(KERN_ERR
+		       "Realview: strange CM count of 0? Default to 1\n");
+
+		ncores = 1;
+	}
+
+	if (ncores > NR_CPUS) {
+		printk(KERN_WARNING
+		       "Realview: no. of cores (%d) greater than configured "
+		       "maximum of %d - clipping\n",
+		       ncores, NR_CPUS);
+		ncores = NR_CPUS;
+	}
+
+	smp_store_cpu_info(cpu);
+
+	/*
+	 * are we trying to boot more cores than exist?
+	 */
+	if (max_cpus > ncores)
+		max_cpus = ncores;
+
+	/*
+	 * Initialise the present map, which describes the set of CPUs
+	 * actually populated at the present time.
+	 */
+	for (i = 0; i < max_cpus; i++)
+		set_cpu_present(i, true);
+
+	/*
+	 * Initialise the SCU if there are more than one CPU and let
+	 * them know where to start. Note that, on modern versions of
+	 * MILO, the "poke" doesn't actually do anything until each
+	 * individual core is sent a soft interrupt to get it out of
+	 * WFI
+	 */
+	if (max_cpus > 1) {
+		/*
+		 * Enable the local timer or broadcast device for the
+		 * boot CPU, but only if we have more than one CPU.
+		 */
+		percpu_timer_setup();
+
+		scu_enable(scu_base_addr());
+		poke_milo();
+	}
+}
diff --git a/arch/arm/mach-s5pv310/setup-i2c0.c b/arch/arm/mach-s5pv310/setup-i2c0.c
new file mode 100644
index 0000000..d4f5a81
--- /dev/null
+++ b/arch/arm/mach-s5pv310/setup-i2c0.c
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-s5pv210/setup-i2c0.c
+ *
+ * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * I2C0 GPIO configuration.
+ *
+ * Based on plat-s3c64xx/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+struct platform_device; /* don't need the contents */
+
+void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+{
+/* will be implemented later */
+}
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index c478441..9261a27 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -21,6 +21,7 @@
 #include <plat/s5p6442.h>
 #include <plat/s5pc100.h>
 #include <plat/s5pv210.h>
+#include <plat/s5pv310.h>
 
 /* table of supported CPUs */
 
@@ -28,6 +29,7 @@ static const char name_s5p6440[] = "S5P6440";
 static const char name_s5p6442[] = "S5P6442";
 static const char name_s5pc100[] = "S5PC100";
 static const char name_s5pv210[] = "S5PV210/S5PC110";
+static const char name_s5pv310[] = "S5PV310";
 
 static struct cpu_table cpu_ids[] __initdata = {
 	{
@@ -62,6 +64,14 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.init_uarts	= s5pv210_init_uarts,
 		.init		= s5pv210_init,
 		.name		= name_s5pv210,
+	}, {
+		.idcode		= 0x43200000,
+		.idmask		= 0xfffff000,
+		.map_io		= s5pv310_map_io,
+		.init_clocks	= s5pv310_init_clocks,
+		.init_uarts	= s5pv310_init_uarts,
+		.init		= s5pv310_init,
+		.name		= name_s5pv310,
 	},
 };
 
@@ -83,6 +93,7 @@ static struct map_desc s5p_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(S3C_PA_UART),
 		.length		= SZ_512K,
 		.type		= MT_DEVICE,
+#ifdef CONFIG_ARM_VIC
 	}, {
 		.virtual	= (unsigned long)VA_VIC0,
 		.pfn		= __phys_to_pfn(S5P_PA_VIC0),
@@ -93,6 +104,7 @@ static struct map_desc s5p_iodesc[] __initdata = {
 		.pfn		= __phys_to_pfn(S5P_PA_VIC1),
 		.length		= SZ_16K,
 		.type		= MT_DEVICE,
+#endif
 	}, {
 		.virtual	= (unsigned long)S3C_VA_TIMER,
 		.pfn		= __phys_to_pfn(S5P_PA_TIMER),
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index 3d815f4..54e9fb9 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -18,6 +18,18 @@
 #define S5P_VA_SYSTIMER		S3C_ADDR(0x01200000)
 #define S5P_VA_SROMC		S3C_ADDR(0x01100000)
 
+#define S5P_VA_COMBINER_BASE	S3C_ADDR(0x00600000)
+#define S5P_VA_COMBINER(x)	(S5P_VA_COMBINER_BASE + ((x) >> 2) * 0x10)
+
+#define S5P_VA_COREPERI_BASE	S3C_ADDR(0x00800000)
+#define S5P_VA_COREPERI(x)	(S5P_VA_COREPERI_BASE + (x))
+#define S5P_VA_SCU		S5P_VA_COREPERI(0x0)
+#define S5P_VA_GIC_CPU		S5P_VA_COREPERI(0x100)
+#define S5P_VA_TWD		S5P_VA_COREPERI(0x600)
+#define S5P_VA_GIC_DIST		S5P_VA_COREPERI(0x1000)
+
+#define S5P_VA_L2CC		S3C_ADDR(0x00900000)
+
 #define S5P_VA_UART(x)		(S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 #define S5P_VA_UART0		S5P_VA_UART(0)
 #define S5P_VA_UART1		S5P_VA_UART(1)
diff --git a/arch/arm/plat-s5p/include/plat/s5pv310.h b/arch/arm/plat-s5p/include/plat/s5pv310.h
new file mode 100644
index 0000000..d2f05e1
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/s5pv310.h
@@ -0,0 +1,33 @@
+/* linux/arch/arm/plat-s5p/include/plat/s5pv310.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Header file for s5pv310 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* Common init code for S5PV310 related SoCs */
+
+extern void s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s5pv310_register_clocks(void);
+extern void s5pv310_setup_clocks(void);
+
+#ifdef CONFIG_CPU_S5PV310
+
+extern  int s5pv310_init(void);
+extern void s5pv310_init_irq(void);
+extern void s5pv310_map_io(void);
+extern void s5pv310_init_clocks(int xtal);
+
+#define s5pv310_init_uarts s5pv310_common_init_uarts
+
+#else
+#define s5pv310_init_clocks NULL
+#define s5pv310_init_uarts NULL
+#define s5pv310_map_io NULL
+#define s5pv310_init NULL
+#endif
-- 
1.6.2.5



From ivo.clarysse at gmail.com  Fri Jun 25 10:46:44 2010
From: ivo.clarysse at gmail.com (Ivo Clarysse)
Date: Fri, 25 Jun 2010 16:46:44 +0200
Subject: [PATCHv3 4/5] mtd: mxc_nand fixups
In-Reply-To: <20100624072732.GQ12115@pengutronix.de>
References: <20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
	<AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
	<80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTikRj_dMkKLyFhW78yld9jIYAIFncfPaPAF8WqUY@mail.gmail.com>
	<80iq5bqd07.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTimJKNEwOoKldq4a4_ufxNY6IY7r6tAfAM055hlW@mail.gmail.com>
	<80vd9ab0d2.fsf@merkur.tec.linutronix.de>
	<AANLkTinVaXjCneg-XpxB7YNlmGOwQFTnm5RUcetPdToI@mail.gmail.com>
	<80lja6awlb.fsf@merkur.tec.linutronix.de>
	<20100624072732.GQ12115@pengutronix.de>
Message-ID: <AANLkTilG2AhYtQkb8V0u9851JP1vHhqrJTWKyRDGM36F@mail.gmail.com>

On Thu, Jun 24, 2010 at 9:27 AM, Sascha Hauer <s.hauer at pengutronix.de> wrote:
[...]
>
> BTW I observed that at least on i.MX27 the latencies introduced by
> waiting for an interrupt cause a significant performance drop. The
> driver gets much faster when we just poll all the time. I don't know how
> this affects system performance otherwise, but it may be a possibility
> to drop interrupt support at least for i.MX21. I have no idea how long
> the longest possible time we'd have to poll is though.

I'm noticing the same thing on i.MX21: when using interrupts,
"Scanning device for bad blocks" takes 982 (!) seconds.  When always
using polling, the same scan takes 'only' 500 seconds.


Ivo.


From ivo.clarysse at gmail.com  Fri Jun 25 10:50:45 2010
From: ivo.clarysse at gmail.com (Ivo Clarysse)
Date: Fri, 25 Jun 2010 16:50:45 +0200
Subject: [PATCHv3 4/5] mtd: mxc_nand fixups
In-Reply-To: <807hloag6w.fsf@merkur.tec.linutronix.de>
References: <20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
	<AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
	<80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTikRj_dMkKLyFhW78yld9jIYAIFncfPaPAF8WqUY@mail.gmail.com>
	<80iq5bqd07.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTimJKNEwOoKldq4a4_ufxNY6IY7r6tAfAM055hlW@mail.gmail.com>
	<80vd9ab0d2.fsf@merkur.tec.linutronix.de>
	<AANLkTinVaXjCneg-XpxB7YNlmGOwQFTnm5RUcetPdToI@mail.gmail.com>
	<80lja6awlb.fsf@merkur.tec.linutronix.de>
	<20100624072732.GQ12115@pengutronix.de>
	<807hloag6w.fsf@merkur.tec.linutronix.de>
Message-ID: <AANLkTilTbvlPxRhioMiKrBUNggcxZeboi1YpB8Y9Bdpm@mail.gmail.com>

On Thu, Jun 24, 2010 at 12:16 PM, John Ogness <john.ogness at linutronix.de> wrote:
> On 2010-06-24, Sascha Hauer <s.hauer at pengutronix.de> wrote:
>> Ok, if it's the only way out to have 5 cpu_is_* blocks, then lets go
>> for it.
>
> Here is a new patch that puts the behavior behind a "nfc_avoid_masking"
> macro. The macro is only used 3 times.
[...]

Tested on an MX21ADS board, and it still works.

> This patch is based on linux-next 20100618.
>
> Signed-off-by: John Ogness <john.ogness at linutronix.de>
> ---
> ?drivers/mtd/nand/mxc_nand.c | ? 81 +++++++++++++++++++++++++---------
> ?1 file changed, 61 insertions(+), 20 deletions(-)
>
> Index: linux-next-20100618/drivers/mtd/nand/mxc_nand.c
> ===================================================================
> --- linux-next-20100618.orig/drivers/mtd/nand/mxc_nand.c
> +++ linux-next-20100618/drivers/mtd/nand/mxc_nand.c
[...]
> @@ -100,6 +109,18 @@
>
> ?#define NFC_RSLTSPARE_AREA_MASK ?0xff
>
> +#define nfc_interrupt_set(_regs) \
> + ? ? ? ? ? ? ? (readw(_regs + NFC_CONFIG2) & NFC_INT)
> +#define nfc_clear_interrupt(_regs) \
> + ? ? ? ? ? ? ? writew(readw(_regs + NFC_CONFIG2) & ~NFC_INT, \
> + ? ? ? ? ? ? ? ? ? ? ?_regs + NFC_CONFIG2)

Naming is not very consistent; I'd suggest nfc_set_interrupt /
nfc_clear_interrupt

> +#define nfc_mask_irq(_regs) \
> + ? ? ? ? ? ? ? writew(readw(_regs + NFC_CONFIG1) | NFC_INT_MSK, \
> + ? ? ? ? ? ? ? ? ? ? ?_regs + NFC_CONFIG1)
> +#define nfc_unmask_irq(_regs) \
> + ? ? ? ? ? ? ? writew(readw(_regs + NFC_CONFIG1) & ~NFC_INT_MSK, \
> + ? ? ? ? ? ? ? ? ? ? ?_regs + NFC_CONFIG1)
> +
[...]


From grant.likely at secretlab.ca  Fri Jun 25 11:26:43 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 25 Jun 2010 09:26:43 -0600
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com> 
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>
Message-ID: <AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>

On Thu, Jun 24, 2010 at 5:43 PM, Kevin Hilman
<khilman at deeprootsystems.com> wrote:
> Implement the new runtime PM framework as a thin layer on top of the
> omap_device API. ?Since we don't have an OMAP-specific bus, override
> the runtime PM hooks for the platform_bus for the OMAP specific
> implementation.
>
> While the runtime PM API has three main states (idle, suspend, resume)
> This version treats idle and suspend the same way by implementing both
> on top of omap_device_disable(), which follows closely with how driver
> are currently using clock enable/disable calls. Longer-termm
> pm_runtime_idle() could take other constraints into consideration to
> make the decision, but the current
>
> Device driver ->runtime_suspend() hooks are called just before the
> device is disabled (via omap_device_idle()), and device driver
> ->runtime_resume() hooks are called just after device has been
> enabled (via omap_device_enable().)

Hi Kevin,

You shouldn't hijack the platform bus in this way, for a number of
reasons.  Not all platform devices in an OMAP system are internal OMAP
devices (as you know since you do an explicit check for omap devices).
 Right there that says that the abstraction is at the wrong level.
What happens when an mostly transparent bridge is added with its own
peripherals and its own special operations?  Does this routine then
need to be extended for each new special case?  It's not maintainable
in the long run.

This approach is also not multiplatform friendly (cc'ing Eric and
Nicolas who are working on ARM multiplatform).  It won't work for
building a kernel that supports, say, both versatile and OMAP.

The kernel already has the facility to do what you need.  We talked
about it briefly at ELC, and now that I look at it closer, I thing
gregkh is absolutely right.  Just create a new bus type for OMAP
devices.  It is simple to add one.  You can probably even call out to
the platform bus ops for most of the operations.  The fact that OMAP
devices have special behaviour that needs to be handled at the bus
type level means that they are not platform devices anymore.  This
also eliminates all the omap_device_is_valid and OMAP_DEVICE_MAGIC
gymnastics.

I see from the comments in omap_device.c that doing an
omap_bus/omap_device is being considered anyway.  Please don't merge
this patch and do the omap_bus_type instead.

Also, I notice that most of these hooks open-code the generic versions
of the runtime hooks.  Instead of open coding it, can the omap hooks
call the generic hooks before/after doing the omap-specific work?

Cheers,
g.

>
> Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
> ---
> ?arch/arm/mach-omap2/Makefile | ? ?7 +++-
> ?arch/arm/mach-omap2/pm_bus.c | ? 70 ++++++++++++++++++++++++++++++++++++++++++
> ?2 files changed, 76 insertions(+), 1 deletions(-)
> ?create mode 100644 arch/arm/mach-omap2/pm_bus.c
>
> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
> index ea52b03..8ed47ea 100644
> --- a/arch/arm/mach-omap2/Makefile
> +++ b/arch/arm/mach-omap2/Makefile
> @@ -46,12 +46,17 @@ obj-$(CONFIG_ARCH_OMAP2) ? ? ? ? ? ?+= sdrc2xxx.o
> ?ifeq ($(CONFIG_PM),y)
> ?obj-$(CONFIG_ARCH_OMAP2) ? ? ? ? ? ? ? += pm24xx.o
> ?obj-$(CONFIG_ARCH_OMAP2) ? ? ? ? ? ? ? += sleep24xx.o
> -obj-$(CONFIG_ARCH_OMAP3) ? ? ? ? ? ? ? += pm34xx.o sleep34xx.o cpuidle34xx.o
> +obj-$(CONFIG_ARCH_OMAP3) ? ? ? ? ? ? ? += pm34xx.o sleep34xx.o cpuidle34xx.o \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?pm_bus.o
> ?obj-$(CONFIG_PM_DEBUG) ? ? ? ? ? ? ? ? += pm-debug.o
>
> ?AFLAGS_sleep24xx.o ? ? ? ? ? ? ? ? ? ? :=-Wa,-march=armv6
> ?AFLAGS_sleep34xx.o ? ? ? ? ? ? ? ? ? ? :=-Wa,-march=armv7-a
>
> +ifeq ($(CONFIG_PM_VERBOSE),y)
> +CFLAGS_pm_bus.o ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?+= -DDEBUG
> +endif
> +
> ?endif
>
> ?# PRCM
> diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
> new file mode 100644
> index 0000000..9719a9f
> --- /dev/null
> +++ b/arch/arm/mach-omap2/pm_bus.c
> @@ -0,0 +1,70 @@
> +/*
> + * Runtime PM support code for OMAP
> + *
> + * Author: Kevin Hilman, Deep Root Systems, LLC
> + *
> + * Copyright (C) 2010 Texas Instruments, Inc.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/io.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/platform_device.h>
> +#include <linux/mutex.h>
> +
> +#include <plat/omap_device.h>
> +#include <plat/omap-pm.h>
> +
> +#ifdef CONFIG_PM_RUNTIME
> +int platform_pm_runtime_suspend(struct device *dev)
> +{
> + ? ? ? struct platform_device *pdev = to_platform_device(dev);
> + ? ? ? struct omap_device *odev = to_omap_device(pdev);
> + ? ? ? int r, ret = 0;
> +
> + ? ? ? dev_dbg(dev, "%s\n", __func__);
> +
> + ? ? ? if (dev->driver->pm && dev->driver->pm->runtime_suspend)
> + ? ? ? ? ? ? ? ret = dev->driver->pm->runtime_suspend(dev);
> + ? ? ? if (!ret && omap_device_is_valid(odev)) {
> + ? ? ? ? ? ? ? r = omap_device_idle(pdev);
> + ? ? ? ? ? ? ? WARN_ON(r);
> + ? ? ? }
> +
> + ? ? ? return ret;
> +};
> +
> +int platform_pm_runtime_resume(struct device *dev)
> +{
> + ? ? ? struct platform_device *pdev = to_platform_device(dev);
> + ? ? ? struct omap_device *odev = to_omap_device(pdev);
> + ? ? ? int r, ret = 0;
> +
> + ? ? ? dev_dbg(dev, "%s\n", __func__);
> +
> + ? ? ? if (omap_device_is_valid(odev)) {
> + ? ? ? ? ? ? ? r = omap_device_enable(pdev);
> + ? ? ? ? ? ? ? WARN_ON(r);
> + ? ? ? }
> +
> + ? ? ? if (dev->driver->pm && dev->driver->pm->runtime_resume)
> + ? ? ? ? ? ? ? ret = dev->driver->pm->runtime_resume(dev);
> +
> + ? ? ? return ret;
> +};
> +
> +int platform_pm_runtime_idle(struct device *dev)
> +{
> + ? ? ? int ret;
> +
> + ? ? ? ret = pm_runtime_suspend(dev);
> + ? ? ? dev_dbg(dev, "%s [%d]\n", __func__, ret);
> +
> + ? ? ? return 0;
> +};
> +#endif /* CONFIG_PM_RUNTIME */
> +
> --
> 1.7.0.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From catalin.marinas at arm.com  Fri Jun 25 12:00:35 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 25 Jun 2010 17:00:35 +0100
Subject: [PATCH 0/2] Barrier changes with !ARM_DMA_MEM_BUFFERABLE
In-Reply-To: <20100621115703.7162.95491.stgit@e102109-lin.cambridge.arm.com>
References: <20100621115703.7162.95491.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <1277481635.13134.62.camel@e102109-lin.cambridge.arm.com>

Russell,

On Mon, 2010-06-21 at 13:23 +0100, Catalin Marinas wrote:
> The patches are relatively simple but without them the RealView boards
> cannot be used with L210/L220 enabled (hardware deadlock, not a software
> issue).
> 
> Catalin Marinas (2):
>       ARM: Do not use outer_sync() in mb() if !ARM_DMA_MEM_BUFFERABLE
>       ARM: Do not enable ARM_DMA_MEM_BUFFERABLE for some RealView boards

Are you ok with these patches, especially the first one?

Alternatively, I can implement the barriers in the RealView code (though
the second patch is still needed as I'll drop the outer_sync() for ARMv6
RealView).

Thanks.

-- 
Catalin



From catalin.marinas at arm.com  Fri Jun 25 12:16:01 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 25 Jun 2010 17:16:01 +0100
Subject: Question about SMP
In-Reply-To: <AANLkTilJOUmarsLJJtNzbVwrZLbLAD29gp2SHL0TZCUQ@mail.gmail.com>
References: <AANLkTilJOUmarsLJJtNzbVwrZLbLAD29gp2SHL0TZCUQ@mail.gmail.com>
Message-ID: <1277482561.13134.68.camel@e102109-lin.cambridge.arm.com>

On Mon, 2010-06-07 at 21:11 +0100, Dave Hylands wrote:
> I'm trying to understand what I need to be concerned about with SMP
> processors and sharing global data (in particular a dual Cortex-A9)
> 
> I'm familiar with spinlocks, but in this case I'm trying to work with
> some lockless data structures.

You should be really concerned about memory ordering and barriers :).
See Documentation/memory-barriers.txt in the kernel source.

> What I'm not sure is whether the following would work. Suppose I have
> a couple of 8-bit get/put indicies which are in adjacent memory
> locations (within the same 32-bit word).
> 
> If I have an ISR and a thread running on an SMP core, and the ISR is
> running on one core and the thread is running on a second core, if the
> ISR were to only write to the put pointer and the thread were only to
> write to the get pointer, does the cache maintain consistency? Or do
> the get and put pointers need to be in separate cache lines?

The consistency is maintained (though be careful about memory ordering
and when the put/get pointers become visible to the other CPUs).

> Another way of asking this: If both cores are writing to the same
> 32-bit word (but different bytes) do the writes collide?

No, though it's not very efficient because of cache line being moved
between CPUs. See http://en.wikipedia.org/wiki/MESI_protocol.

-- 
Catalin



From catalin.marinas at arm.com  Fri Jun 25 13:18:43 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Fri, 25 Jun 2010 18:18:43 +0100
Subject: [PATCH 1/1] ARM: unwind - optimise linked-list searches for
	modules
In-Reply-To: <1276605998-19275-1-git-send-email-ext-phil.2.carmody@nokia.com>
References: <1276605998-19275-1-git-send-email-ext-phil.2.carmody@nokia.com>
Message-ID: <1277486323.13134.82.camel@e102109-lin.cambridge.arm.com>

On Tue, 2010-06-15 at 13:46 +0100, Phil Carmody wrote:
> With several sections per module, and dozens of modules, the
> searches down the linked list would dominate the lookup time,
> dwarfing any savings from the binary search within the section.
> 
> A simple move-to-front optimisation exploits the commonality
> of the code paths taken, and in simple real-world tests reduces
> the number of steps in the search to barely more than 1.
> 
> Signed-off-by: Phil Carmody <ext-phil.2.carmody at nokia.com>
> ---
>  arch/arm/kernel/unwind.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
> index dd81a91..2e88abf 100644
> --- a/arch/arm/kernel/unwind.c
> +++ b/arch/arm/kernel/unwind.c
> @@ -146,6 +146,8 @@ static struct unwind_idx *unwind_find_idx(unsigned long addr)
>                             addr < table->end_addr) {
>                                 idx = search_index(addr, table->start,
>                                                    table->stop - 1);
> +                               /* MTF with 50 modules: 80 steps becomes ~1 */
> +                               list_move(&table->list, &unwind_tables);

That's a good optimisation. Could you please expand the "MTF" comment in
the code a bit more? Otherwise,

Acked-by: Catalin Marinas <catalin.marinas at arm.com>

-- 
Catalin



From khilman at deeprootsystems.com  Fri Jun 25 14:04:48 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Fri, 25 Jun 2010 11:04:48 -0700
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>
	(Grant Likely's message of "Fri, 25 Jun 2010 09:26:43 -0600")
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>
Message-ID: <874ogrng3j.fsf@deeprootsystems.com>

Grant Likely <grant.likely at secretlab.ca> writes:

> On Thu, Jun 24, 2010 at 5:43 PM, Kevin Hilman
> <khilman at deeprootsystems.com> wrote:
>> Implement the new runtime PM framework as a thin layer on top of the
>> omap_device API. ?Since we don't have an OMAP-specific bus, override
>> the runtime PM hooks for the platform_bus for the OMAP specific
>> implementation.
>>
>> While the runtime PM API has three main states (idle, suspend, resume)
>> This version treats idle and suspend the same way by implementing both
>> on top of omap_device_disable(), which follows closely with how driver
>> are currently using clock enable/disable calls. Longer-termm
>> pm_runtime_idle() could take other constraints into consideration to
>> make the decision, but the current
>>
>> Device driver ->runtime_suspend() hooks are called just before the
>> device is disabled (via omap_device_idle()), and device driver
>> ->runtime_resume() hooks are called just after device has been
>> enabled (via omap_device_enable().)
>
> Hi Kevin,

Hi Grant.  Thanks for the review and suggestions.

> You shouldn't hijack the platform bus in this way, for a number of
> reasons.  Not all platform devices in an OMAP system are internal OMAP
> devices (as you know since you do an explicit check for omap devices).
>  Right there that says that the abstraction is at the wrong level.
> What happens when an mostly transparent bridge is added with its own
> peripherals and its own special operations?  Does this routine then
> need to be extended for each new special case?  It's not maintainable
> in the long run.
>
> This approach is also not multiplatform friendly (cc'ing Eric and
> Nicolas who are working on ARM multiplatform).  It won't work for
> building a kernel that supports, say, both versatile and OMAP.

Totally agree here, but this a separate issue not specifically created
by this series (it was created when runtime PM support for SH was
added), but indeed I am continuining bad behavior. :/

The issue is that the current method to override bus methods is by
overriding weak symbols.  This clearly doesn't scale to support multiple
platforms in the same image.

What would be needed (if we continue to override the platform_bus
methods) is to have some sort of register function for overriding these
methods.  I'll look into that based on the result of discussions
below...

> The kernel already has the facility to do what you need.  We talked
> about it briefly at ELC, and now that I look at it closer, I thing
> gregkh is absolutely right.  Just create a new bus type for OMAP
> devices.  It is simple to add one.  You can probably even call out to
> the platform bus ops for most of the operations.  The fact that OMAP
> devices have special behaviour that needs to be handled at the bus
> type level means that they are not platform devices anymore.  This
> also eliminates all the omap_device_is_valid and OMAP_DEVICE_MAGIC
> gymnastics.
>
> I see from the comments in omap_device.c that doing an
> omap_bus/omap_device is being considered anyway.  Please don't merge
> this patch and do the omap_bus_type instead.

Agreed, it is logicially simpler in many ways and as you've noticed,
we've been discussing it in the OMAP community.

However, I keep coming back to extending the platform bus, primarily
since the resulting new bus code would look almost identical to the
platform bus.  All I really needed is the ability to extend a small
subset of the PM functions, so this led to me the "extend instead of
duplicate" approach.

In addition, I really don't want to duplicate all the platform_driver
and platform_device code, again because it would be identical but
especially since this would seriously impact many drivers.  For drivers
that are used on OMAP and also on other platforms, do we want drivers to
know (or care) if they are on the platform bus or on the OMAP bus?  I
think this is how it is done for OF devices, but I'm not crazy about
that approach (after our discussions at ELC, I remember thinking you'd
been through this with the OF devices as well and are moving towards
using platform_bus/platform_device for those too.  Did I understand
correctly?)

This affects many aspects of all drivers, from register and probe (for
early devices/drivers too!) to all the plaform_get_resource() usage, all
of which assumes a platform_driver and platform_device.  I didn't look
closely, but I didn't see if (or how) OF was handling early devices.

All that being said, if I could create a custom bus, but continue to use
platform_devices, that would greatly simply the changes to drivers.  Do
you think that's acceptable?  If so, I can take a stab at that and see
what it looks like.

> Also, I notice that most of these hooks open-code the generic versions
> of the runtime hooks.  Instead of open coding it, can the omap hooks
> call the generic hooks before/after doing the omap-specific work?

Ah, good point.

This patch pre-dates the creation of pm_generic_runtime_*, but certainly
should be upgraded to use those.  Thanks.

Kevin


> Cheers,
> g.
>
>>
>> Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
>> ---
>> ?arch/arm/mach-omap2/Makefile | ? ?7 +++-
>> ?arch/arm/mach-omap2/pm_bus.c | ? 70 ++++++++++++++++++++++++++++++++++++++++++
>> ?2 files changed, 76 insertions(+), 1 deletions(-)
>> ?create mode 100644 arch/arm/mach-omap2/pm_bus.c
>>
>> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
>> index ea52b03..8ed47ea 100644
>> --- a/arch/arm/mach-omap2/Makefile
>> +++ b/arch/arm/mach-omap2/Makefile
>> @@ -46,12 +46,17 @@ obj-$(CONFIG_ARCH_OMAP2) ? ? ? ? ? ?+= sdrc2xxx.o
>> ?ifeq ($(CONFIG_PM),y)
>> ?obj-$(CONFIG_ARCH_OMAP2) ? ? ? ? ? ? ? += pm24xx.o
>> ?obj-$(CONFIG_ARCH_OMAP2) ? ? ? ? ? ? ? += sleep24xx.o
>> -obj-$(CONFIG_ARCH_OMAP3) ? ? ? ? ? ? ? += pm34xx.o sleep34xx.o cpuidle34xx.o
>> +obj-$(CONFIG_ARCH_OMAP3) ? ? ? ? ? ? ? += pm34xx.o sleep34xx.o cpuidle34xx.o \
>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?pm_bus.o
>> ?obj-$(CONFIG_PM_DEBUG) ? ? ? ? ? ? ? ? += pm-debug.o
>>
>> ?AFLAGS_sleep24xx.o ? ? ? ? ? ? ? ? ? ? :=-Wa,-march=armv6
>> ?AFLAGS_sleep34xx.o ? ? ? ? ? ? ? ? ? ? :=-Wa,-march=armv7-a
>>
>> +ifeq ($(CONFIG_PM_VERBOSE),y)
>> +CFLAGS_pm_bus.o ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?+= -DDEBUG
>> +endif
>> +
>> ?endif
>>
>> ?# PRCM
>> diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
>> new file mode 100644
>> index 0000000..9719a9f
>> --- /dev/null
>> +++ b/arch/arm/mach-omap2/pm_bus.c
>> @@ -0,0 +1,70 @@
>> +/*
>> + * Runtime PM support code for OMAP
>> + *
>> + * Author: Kevin Hilman, Deep Root Systems, LLC
>> + *
>> + * Copyright (C) 2010 Texas Instruments, Inc.
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +#include <linux/init.h>
>> +#include <linux/kernel.h>
>> +#include <linux/io.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/mutex.h>
>> +
>> +#include <plat/omap_device.h>
>> +#include <plat/omap-pm.h>
>> +
>> +#ifdef CONFIG_PM_RUNTIME
>> +int platform_pm_runtime_suspend(struct device *dev)
>> +{
>> + ? ? ? struct platform_device *pdev = to_platform_device(dev);
>> + ? ? ? struct omap_device *odev = to_omap_device(pdev);
>> + ? ? ? int r, ret = 0;
>> +
>> + ? ? ? dev_dbg(dev, "%s\n", __func__);
>> +
>> + ? ? ? if (dev->driver->pm && dev->driver->pm->runtime_suspend)
>> + ? ? ? ? ? ? ? ret = dev->driver->pm->runtime_suspend(dev);
>> + ? ? ? if (!ret && omap_device_is_valid(odev)) {
>> + ? ? ? ? ? ? ? r = omap_device_idle(pdev);
>> + ? ? ? ? ? ? ? WARN_ON(r);
>> + ? ? ? }
>> +
>> + ? ? ? return ret;
>> +};
>> +
>> +int platform_pm_runtime_resume(struct device *dev)
>> +{
>> + ? ? ? struct platform_device *pdev = to_platform_device(dev);
>> + ? ? ? struct omap_device *odev = to_omap_device(pdev);
>> + ? ? ? int r, ret = 0;
>> +
>> + ? ? ? dev_dbg(dev, "%s\n", __func__);
>> +
>> + ? ? ? if (omap_device_is_valid(odev)) {
>> + ? ? ? ? ? ? ? r = omap_device_enable(pdev);
>> + ? ? ? ? ? ? ? WARN_ON(r);
>> + ? ? ? }
>> +
>> + ? ? ? if (dev->driver->pm && dev->driver->pm->runtime_resume)
>> + ? ? ? ? ? ? ? ret = dev->driver->pm->runtime_resume(dev);
>> +
>> + ? ? ? return ret;
>> +};
>> +
>> +int platform_pm_runtime_idle(struct device *dev)
>> +{
>> + ? ? ? int ret;
>> +
>> + ? ? ? ret = pm_runtime_suspend(dev);
>> + ? ? ? dev_dbg(dev, "%s [%d]\n", __func__, ret);
>> +
>> + ? ? ? return 0;
>> +};
>> +#endif /* CONFIG_PM_RUNTIME */
>> +
>> --
>> 1.7.0.2
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>


From nico at fluxnic.net  Fri Jun 25 14:30:53 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 25 Jun 2010 14:30:53 -0400 (EDT)
Subject: [PATCH 3/4] [ARM] Introduce USE_DEFAULT_IO_H to use default
	definitions in asm/io.h
In-Reply-To: <1277451871-15319-4-git-send-email-eric.y.miao@gmail.com>
References: <1277451871-15319-1-git-send-email-eric.y.miao@gmail.com>
	<1277451871-15319-4-git-send-email-eric.y.miao@gmail.com>
Message-ID: <alpine.LFD.2.00.1006251429070.24097@xanadu.home>

On Fri, 25 Jun 2010, Eric Miao wrote:

> From: Eric Miao <eric.miao at canonical.com>
> 
> For those machines that can just use the default definitions in asm/io.h,
> there is no need to have a machine specific mach/io.h. Introduce an config
> option for them.

I like this approach.  This allows us to transition specific machines 
gradually, and provide a clear set of conditions for multiple machine 
families to be eventually compilable together.


Nicolas


From xiachendong at hotmail.com  Fri Jun 25 15:43:00 2010
From: xiachendong at hotmail.com (Xiachen Dong)
Date: Fri, 25 Jun 2010 15:43:00 -0400
Subject: Possible methods for the kernel to terminate a process
In-Reply-To: <20100623004422.GB22367@shareable.org>
References: <BAY134-W142753895B5626C329E273BDC40@phx.gbl>,
	<20100623004422.GB22367@shareable.org>
Message-ID: <BAY134-W11C4AD28C06C5AABEB0F62BDC70@phx.gbl>



Thank you very much for the reply. It's very helpful.

I didn't noticed that TASK_KILLABLE(TASK_WAITKILL | TASK_UNINTERRUPTIBLE) is already defined in sched.h and I didn't know that there is such a state either.

I'll do some more testing with the simple test driver code.

Thanks,

Xiachen

----------------------------------------
> Date: Wed, 23 Jun 2010 01:44:22 +0100
> From: jamie at shareable.org
> To: xiachendong at hotmail.com
> Subject: Re: Possible methods for the kernel to terminate a process
> CC: linux-arm-kernel at lists.infradead.org
>
> Xiachen Dong wrote:
>>
>> Hi,
>>
>> We have a quick question. Besides sending signals, are there any other ways for the kernel to terminate a process?
>>
>> We have such question because we try to kill a user space process by the shell command kill and we cannot kill it probably because it is in an un-interruptible sleep/wait.
>>
>> However, we still wish to be able to kill the user space process under this circumstance. To our knowledge of the kernel, if the kernel wants to kill a process when special event such as exception happens, it usually sends a signal to the process. We really cannot think of any other methods for a kernel to terminate a process.
>>
>> Can anyone provide some hints on this? Is rebooting the machine the only solution to the problem?
>
> You can't kill a task that's in TASK_UNINTERRUPTIBLE state, except by
> the condition the task is waiting on changing.
>
> That's been a well known problem with unix for decades, because
> uninterruptible wait is used for some things (like reading a disk
> file) that it seems reasonable to be able to kill.
>
> So, to fix that, TASK_KILLABLE was added. It means you can't
> interrupt the process with most signals, but you can at least "kill
> -9" the process (SIGKILL).
>
> I think for what you're asking, if the problem is some processes tend
> to block on particular device drivers, or processes blocked while
> accessing files gets stuck, or things like that, the best thing is to
> look at the places they might be in TASK_UNINTERRUPTIBLE and
> *carefully* change the code to use TASK_KILLABLE and handle the killed
> condition.
>
> It's not possible to just search-and-replace TASK_UNINTERRUPTIBLE.
> You have to make sure the killed condition is handled by cleaning up
> locked resources, and only then change to killable.
>
> -- Jamie
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
 		 	   		  
_________________________________________________________________
Learn more ways to connect with your buddies now
http://go.microsoft.com/?linkid=9734388

From linux at arm.linux.org.uk  Fri Jun 25 16:06:59 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 25 Jun 2010 21:06:59 +0100
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>
Message-ID: <20100625200659.GB22090@n2100.arm.linux.org.uk>

On Fri, Jun 25, 2010 at 09:26:43AM -0600, Grant Likely wrote:
> This approach is also not multiplatform friendly (cc'ing Eric and
> Nicolas who are working on ARM multiplatform).  It won't work for
> building a kernel that supports, say, both versatile and OMAP.

And I should also point out that multiplatform is not the answer to
Linus' concerns.  There's no way such work is going to be anywhere
near complete come the next merge window.

Note that the loss of the defconfigs will make the integration of
multiplatform patches extremely time consuming and slow.


From grant.likely at secretlab.ca  Fri Jun 25 16:08:51 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 25 Jun 2010 14:08:51 -0600
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <874ogrng3j.fsf@deeprootsystems.com>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com> 
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com> 
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com> 
	<874ogrng3j.fsf@deeprootsystems.com>
Message-ID: <AANLkTimMnJvOJrRHDiE6PH1BXpRz2-6pY1M9nKHw7vpn@mail.gmail.com>

On Fri, Jun 25, 2010 at 12:04 PM, Kevin Hilman
<khilman at deeprootsystems.com> wrote:
> Grant Likely <grant.likely at secretlab.ca> writes:
>
>> On Thu, Jun 24, 2010 at 5:43 PM, Kevin Hilman
>> <khilman at deeprootsystems.com> wrote:
>>> Implement the new runtime PM framework as a thin layer on top of the
>>> omap_device API. ?Since we don't have an OMAP-specific bus, override
>>> the runtime PM hooks for the platform_bus for the OMAP specific
>>> implementation.
>>>
>>> While the runtime PM API has three main states (idle, suspend, resume)
>>> This version treats idle and suspend the same way by implementing both
>>> on top of omap_device_disable(), which follows closely with how driver
>>> are currently using clock enable/disable calls. Longer-termm
>>> pm_runtime_idle() could take other constraints into consideration to
>>> make the decision, but the current
>>>
>>> Device driver ->runtime_suspend() hooks are called just before the
>>> device is disabled (via omap_device_idle()), and device driver
>>> ->runtime_resume() hooks are called just after device has been
>>> enabled (via omap_device_enable().)
>>
>> Hi Kevin,
>
> Hi Grant. ?Thanks for the review and suggestions.
>
>> You shouldn't hijack the platform bus in this way, for a number of
>> reasons. ?Not all platform devices in an OMAP system are internal OMAP
>> devices (as you know since you do an explicit check for omap devices).
>> ?Right there that says that the abstraction is at the wrong level.
>> What happens when an mostly transparent bridge is added with its own
>> peripherals and its own special operations? ?Does this routine then
>> need to be extended for each new special case? ?It's not maintainable
>> in the long run.
>>
>> This approach is also not multiplatform friendly (cc'ing Eric and
>> Nicolas who are working on ARM multiplatform). ?It won't work for
>> building a kernel that supports, say, both versatile and OMAP.
>
> Totally agree here, but this a separate issue not specifically created
> by this series (it was created when runtime PM support for SH was
> added), but indeed I am continuining bad behavior. :/

I think I could successfully argue that ARM is more important that SH.
 If SH messes up it's sandbox the collateral damage isn't nearly so
severe.  Don't follow the SH lead in this case.

> The issue is that the current method to override bus methods is by
> overriding weak symbols. ?This clearly doesn't scale to support multiple
> platforms in the same image.

Agreed.  It scales better to change the hooks at runtime, which is
actually quite easy, but it still leaves the abstraction at the wrong
level.

> What would be needed (if we continue to override the platform_bus
> methods) is to have some sort of register function for overriding these
> methods. ?I'll look into that based on the result of discussions
> below...
>
>> The kernel already has the facility to do what you need. ?We talked
>> about it briefly at ELC, and now that I look at it closer, I thing
>> gregkh is absolutely right. ?Just create a new bus type for OMAP
>> devices. ?It is simple to add one. ?You can probably even call out to
>> the platform bus ops for most of the operations. ?The fact that OMAP
>> devices have special behaviour that needs to be handled at the bus
>> type level means that they are not platform devices anymore. ?This
>> also eliminates all the omap_device_is_valid and OMAP_DEVICE_MAGIC
>> gymnastics.
>>
>> I see from the comments in omap_device.c that doing an
>> omap_bus/omap_device is being considered anyway. ?Please don't merge
>> this patch and do the omap_bus_type instead.
>
> Agreed, it is logicially simpler in many ways and as you've noticed,
> we've been discussing it in the OMAP community.
>
> However, I keep coming back to extending the platform bus, primarily
> since the resulting new bus code would look almost identical to the
> platform bus. ?All I really needed is the ability to extend a small
> subset of the PM functions, so this led to me the "extend instead of
> duplicate" approach.
>
> In addition, I really don't want to duplicate all the platform_driver
> and platform_device code, again because it would be identical but
> especially since this would seriously impact many drivers. ?For drivers
> that are used on OMAP and also on other platforms, do we want drivers to
> know (or care) if they are on the platform bus or on the OMAP bus?

Some questions to make sure I understand:
Do you have a lot of these cases?
Do non-OMAP devices also have to process the omap clock enable/disable
code too, or is this only for stuff that is internal to the chip?
Or is this the case where existing non-omap device drivers can also
drive the omap SoC hardware?

> I think this is how it is done for OF devices, but I'm not crazy about
> that approach (after our discussions at ELC, I remember thinking you'd
> been through this with the OF devices as well and are moving towards
> using platform_bus/platform_device for those too. ?Did I understand
> correctly?)

Yes, I've got patches which merge of_platform_bus_type with the
platform bus.  This was an easy decision to make because the
of-specific bits (specifically, matching an of_device_id table with a
device tree node) are applicable to all bus types; i2c, spi, mdio,
platform, etc).  The needed OF data structures have been moved into
struct device and struct device_driver so that of_platform_bus_type no
longer has anything different.

The drivers still need to care about OF when extra platform data needs
to be extracted from the DT node, but for IRQs and register ranges it
is automatic.

The omap case looks different.  You've got special runtime pm ops that
you want to hook in; but only for omap_devices.  It doesn't really
apply to more than one bus type in the system.

> This affects many aspects of all drivers, from register and probe (for
> early devices/drivers too!) to all the plaform_get_resource() usage, all
> of which assumes a platform_driver and platform_device. ?I didn't look
> closely, but I didn't see if (or how) OF was handling early devices.

You don't have to reimplement the entire platform bus.  You could
simply create a new bus type, but reuse all the existing platform bus
code.  All that changes is the bus type that the device and the driver
gets registered on.  Then you could easily replace only the functions
that matter.  (do a git grep platform_bus_type to see how few
references there actually are.  It looks like there are only 5
references to it in drivers/base/platform.c that you'd need to work
around; in platform_device_add(), platform_driver_register(), 2 in
platform_driver_probe(), and the register in platform_bus_init().  You
may not even need to reimplement platform_driver_probe().

It might even be as simple as doing this:
-        pdev->dev.bus = &platform_bus_type;
+       if (!pdev->dev.bus)
+                pdev->dev.bus = &platform_bus_type;

So that a different bus type can be selected at device registration
time (but this might be a little on the dangerous side.  It might be
better to have a wrapper function that accepts an omap_device, and
then does the appropriate registration so that the compiler can
type-check it for you).

Another way to look at the problem is that these runtime
customizations are kind of a property of the parent device (the bus,
not the bus_type).  Would it make sense for parent devices to have
runtime ops to perform for each child that is suspended/resumed?  That
would make it simple to register another device that implements the
bus behaviour and attach it at runtime instead of compile time.

So, instead of having all the platform_bus_type devices as children of
the "platform" device (/sys/devices/platform/*), you could set the
omap devices to be children of an omap bus device
(/sys/devices/omap/*).  Different busses can also implement different
behaviour by using a different parent device.  For example:

/sys/devices/platform
/sys/devices/omap-bus-a
/sys/devices/omap-bus-a/omap-bus-b

Thoughts?

> All that being said, if I could create a custom bus, but continue to use
> platform_devices, that would greatly simply the changes to drivers. ?Do
> you think that's acceptable? ?If so, I can take a stab at that and see
> what it looks like.

Heh, I should read the whole email before replying.  See above.

>> Also, I notice that most of these hooks open-code the generic versions
>> of the runtime hooks. ?Instead of open coding it, can the omap hooks
>> call the generic hooks before/after doing the omap-specific work?
>
> Ah, good point.
>
> This patch pre-dates the creation of pm_generic_runtime_*, but certainly
> should be upgraded to use those. ?Thanks.
>
> Kevin
>
>
>> Cheers,
>> g.
>>
>>>
>>> Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
>>> ---
>>> ?arch/arm/mach-omap2/Makefile | ? ?7 +++-
>>> ?arch/arm/mach-omap2/pm_bus.c | ? 70 ++++++++++++++++++++++++++++++++++++++++++
>>> ?2 files changed, 76 insertions(+), 1 deletions(-)
>>> ?create mode 100644 arch/arm/mach-omap2/pm_bus.c
>>>
>>> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
>>> index ea52b03..8ed47ea 100644
>>> --- a/arch/arm/mach-omap2/Makefile
>>> +++ b/arch/arm/mach-omap2/Makefile
>>> @@ -46,12 +46,17 @@ obj-$(CONFIG_ARCH_OMAP2) ? ? ? ? ? ?+= sdrc2xxx.o
>>> ?ifeq ($(CONFIG_PM),y)
>>> ?obj-$(CONFIG_ARCH_OMAP2) ? ? ? ? ? ? ? += pm24xx.o
>>> ?obj-$(CONFIG_ARCH_OMAP2) ? ? ? ? ? ? ? += sleep24xx.o
>>> -obj-$(CONFIG_ARCH_OMAP3) ? ? ? ? ? ? ? += pm34xx.o sleep34xx.o cpuidle34xx.o
>>> +obj-$(CONFIG_ARCH_OMAP3) ? ? ? ? ? ? ? += pm34xx.o sleep34xx.o cpuidle34xx.o \
>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?pm_bus.o
>>> ?obj-$(CONFIG_PM_DEBUG) ? ? ? ? ? ? ? ? += pm-debug.o
>>>
>>> ?AFLAGS_sleep24xx.o ? ? ? ? ? ? ? ? ? ? :=-Wa,-march=armv6
>>> ?AFLAGS_sleep34xx.o ? ? ? ? ? ? ? ? ? ? :=-Wa,-march=armv7-a
>>>
>>> +ifeq ($(CONFIG_PM_VERBOSE),y)
>>> +CFLAGS_pm_bus.o ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?+= -DDEBUG
>>> +endif
>>> +
>>> ?endif
>>>
>>> ?# PRCM
>>> diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
>>> new file mode 100644
>>> index 0000000..9719a9f
>>> --- /dev/null
>>> +++ b/arch/arm/mach-omap2/pm_bus.c
>>> @@ -0,0 +1,70 @@
>>> +/*
>>> + * Runtime PM support code for OMAP
>>> + *
>>> + * Author: Kevin Hilman, Deep Root Systems, LLC
>>> + *
>>> + * Copyright (C) 2010 Texas Instruments, Inc.
>>> + *
>>> + * This file is licensed under the terms of the GNU General Public
>>> + * License version 2. This program is licensed "as is" without any
>>> + * warranty of any kind, whether express or implied.
>>> + */
>>> +#include <linux/init.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/io.h>
>>> +#include <linux/pm_runtime.h>
>>> +#include <linux/platform_device.h>
>>> +#include <linux/mutex.h>
>>> +
>>> +#include <plat/omap_device.h>
>>> +#include <plat/omap-pm.h>
>>> +
>>> +#ifdef CONFIG_PM_RUNTIME
>>> +int platform_pm_runtime_suspend(struct device *dev)
>>> +{
>>> + ? ? ? struct platform_device *pdev = to_platform_device(dev);
>>> + ? ? ? struct omap_device *odev = to_omap_device(pdev);
>>> + ? ? ? int r, ret = 0;
>>> +
>>> + ? ? ? dev_dbg(dev, "%s\n", __func__);
>>> +
>>> + ? ? ? if (dev->driver->pm && dev->driver->pm->runtime_suspend)
>>> + ? ? ? ? ? ? ? ret = dev->driver->pm->runtime_suspend(dev);
>>> + ? ? ? if (!ret && omap_device_is_valid(odev)) {
>>> + ? ? ? ? ? ? ? r = omap_device_idle(pdev);
>>> + ? ? ? ? ? ? ? WARN_ON(r);
>>> + ? ? ? }
>>> +
>>> + ? ? ? return ret;
>>> +};
>>> +
>>> +int platform_pm_runtime_resume(struct device *dev)
>>> +{
>>> + ? ? ? struct platform_device *pdev = to_platform_device(dev);
>>> + ? ? ? struct omap_device *odev = to_omap_device(pdev);
>>> + ? ? ? int r, ret = 0;
>>> +
>>> + ? ? ? dev_dbg(dev, "%s\n", __func__);
>>> +
>>> + ? ? ? if (omap_device_is_valid(odev)) {
>>> + ? ? ? ? ? ? ? r = omap_device_enable(pdev);
>>> + ? ? ? ? ? ? ? WARN_ON(r);
>>> + ? ? ? }
>>> +
>>> + ? ? ? if (dev->driver->pm && dev->driver->pm->runtime_resume)
>>> + ? ? ? ? ? ? ? ret = dev->driver->pm->runtime_resume(dev);
>>> +
>>> + ? ? ? return ret;
>>> +};
>>> +
>>> +int platform_pm_runtime_idle(struct device *dev)
>>> +{
>>> + ? ? ? int ret;
>>> +
>>> + ? ? ? ret = pm_runtime_suspend(dev);
>>> + ? ? ? dev_dbg(dev, "%s [%d]\n", __func__, ret);
>>> +
>>> + ? ? ? return 0;
>>> +};
>>> +#endif /* CONFIG_PM_RUNTIME */
>>> +
>>> --
>>> 1.7.0.2
>>>
>>>
>>> _______________________________________________
>>> linux-arm-kernel mailing list
>>> linux-arm-kernel at lists.infradead.org
>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From grant.likely at secretlab.ca  Fri Jun 25 16:13:15 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 25 Jun 2010 14:13:15 -0600
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <20100625200659.GB22090@n2100.arm.linux.org.uk>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com> 
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com> 
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com> 
	<20100625200659.GB22090@n2100.arm.linux.org.uk>
Message-ID: <AANLkTikYE6Kg8C_ZClx9aKLvOa9CQRUT587hQnB91sua@mail.gmail.com>

On Fri, Jun 25, 2010 at 2:06 PM, Russell King - ARM Linux
<linux at arm.linux.org.uk> wrote:
> On Fri, Jun 25, 2010 at 09:26:43AM -0600, Grant Likely wrote:
>> This approach is also not multiplatform friendly (cc'ing Eric and
>> Nicolas who are working on ARM multiplatform). ?It won't work for
>> building a kernel that supports, say, both versatile and OMAP.
>
> And I should also point out that multiplatform is not the answer to
> Linus' concerns. ?There's no way such work is going to be anywhere
> near complete come the next merge window.

Yes, but solving the defconfig problem isn't the reason for multiplatform.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From linux at arm.linux.org.uk  Fri Jun 25 16:20:02 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Fri, 25 Jun 2010 21:20:02 +0100
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <AANLkTikYE6Kg8C_ZClx9aKLvOa9CQRUT587hQnB91sua@mail.gmail.com>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>
	<20100625200659.GB22090@n2100.arm.linux.org.uk>
	<AANLkTikYE6Kg8C_ZClx9aKLvOa9CQRUT587hQnB91sua@mail.gmail.com>
Message-ID: <20100625202002.GC22090@n2100.arm.linux.org.uk>

On Fri, Jun 25, 2010 at 02:13:15PM -0600, Grant Likely wrote:
> On Fri, Jun 25, 2010 at 2:06 PM, Russell King - ARM Linux
> <linux at arm.linux.org.uk> wrote:
> > On Fri, Jun 25, 2010 at 09:26:43AM -0600, Grant Likely wrote:
> >> This approach is also not multiplatform friendly (cc'ing Eric and
> >> Nicolas who are working on ARM multiplatform). ?It won't work for
> >> building a kernel that supports, say, both versatile and OMAP.
> >
> > And I should also point out that multiplatform is not the answer to
> > Linus' concerns. ?There's no way such work is going to be anywhere
> > near complete come the next merge window.
> 
> Yes, but solving the defconfig problem isn't the reason for multiplatform.

Does anyone know where we are on the defconfig problem?  From what I
can see, it's mostly stalled for the time being, which is not good
news for us.


From nico at fluxnic.net  Fri Jun 25 16:49:51 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 25 Jun 2010 16:49:51 -0400 (EDT)
Subject: kprobe bug.
In-Reply-To: <AAD1C6EB06EE3649B35B7E026785068D14FCB58138@SC-VEXCH2.marvell.com>
References: <AAD1C6EB06EE3649B35B7E026785068D14FCB58138@SC-VEXCH2.marvell.com>
Message-ID: <alpine.LFD.2.00.1006251630500.24097@xanadu.home>

On Fri, 25 Jun 2010, Bin Yang wrote:

> Hi Russell,
> 
> 	Thanks in advance for your kind to review my question. 
> 	I met a kprobe bug while I used it to debug my driver. 
> 	Here is the scenario:
> 	I add a probe at function xxx(). And the assembly code of xxx() is as following,
> =====================
> 	c035ee48 <xxx >:
> c035ee48:       e59f3008        ldr     r3, [pc, #8]    ; c035ee58              <xxx+0x10>
> c035ee4c:       e3a02001        mov     r2, #1  ; 0x1
> c035ee50:       e5032fff        str     r2, [r3, #-4095]
> c035ee54:       e12fff1e        bx      lr
> c035ee58:       fe03dfff        .word   0xfe03dfff 
> =====================
> 	The ldr emulate always load e12fff1e to r3 register. 
> 	After debugging, I found the pc register should be 8 after current instruction. So we should set pc to pc+8 before instruction emulation and set it back to the next instruction after singe step.
> 	Here is my patch: 
> =======================
> diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c
> index 60c62c3..6e2567e 100644
> --- a/arch/arm/kernel/kprobes.c
> +++ b/arch/arm/kernel/kprobes.c
> @@ -132,8 +132,9 @@ static void __kprobes set_current_kprobe(struct kprobe *p)
>  static void __kprobes singlestep(struct kprobe *p, struct pt_regs *regs,
>  				 struct kprobe_ctlblk *kcb)
>  {
> -	regs->ARM_pc += 4;
> +	regs->ARM_pc += 8;
>  	p->ainsn.insn_handler(p, regs);
> +	regs->ARM_pc -= 4;
>  }
>  
>  /*
> ========================

This is wrong.  You are breaking all the emulated instructions changing 
the pc value.

What needs to be done is to add a special case in emulate_ldr() to fixup 
rnv when rn is 15.  The same fixup would be needed in emulate_str().
See emulate_alu_rflags() for example.


Nicolas


From khilman at deeprootsystems.com  Fri Jun 25 17:58:57 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Fri, 25 Jun 2010 14:58:57 -0700
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <AANLkTimMnJvOJrRHDiE6PH1BXpRz2-6pY1M9nKHw7vpn@mail.gmail.com>
	(Grant Likely's message of "Fri, 25 Jun 2010 14:08:51 -0600")
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>
	<874ogrng3j.fsf@deeprootsystems.com>
	<AANLkTimMnJvOJrRHDiE6PH1BXpRz2-6pY1M9nKHw7vpn@mail.gmail.com>
Message-ID: <87wrtmepum.fsf@deeprootsystems.com>

Grant Likely <grant.likely at secretlab.ca> writes:

> On Fri, Jun 25, 2010 at 12:04 PM, Kevin Hilman
> <khilman at deeprootsystems.com> wrote:
>> Grant Likely <grant.likely at secretlab.ca> writes:
>>
>>> On Thu, Jun 24, 2010 at 5:43 PM, Kevin Hilman
>>> <khilman at deeprootsystems.com> wrote:
>>>> Implement the new runtime PM framework as a thin layer on top of the
>>>> omap_device API. ?Since we don't have an OMAP-specific bus, override
>>>> the runtime PM hooks for the platform_bus for the OMAP specific
>>>> implementation.
>>>>
>>>> While the runtime PM API has three main states (idle, suspend, resume)
>>>> This version treats idle and suspend the same way by implementing both
>>>> on top of omap_device_disable(), which follows closely with how driver
>>>> are currently using clock enable/disable calls. Longer-termm
>>>> pm_runtime_idle() could take other constraints into consideration to
>>>> make the decision, but the current
>>>>
>>>> Device driver ->runtime_suspend() hooks are called just before the
>>>> device is disabled (via omap_device_idle()), and device driver
>>>> ->runtime_resume() hooks are called just after device has been
>>>> enabled (via omap_device_enable().)
>>>
>>> Hi Kevin,
>>
>> Hi Grant. ?Thanks for the review and suggestions.
>>
>>> You shouldn't hijack the platform bus in this way, for a number of
>>> reasons. ?Not all platform devices in an OMAP system are internal OMAP
>>> devices (as you know since you do an explicit check for omap devices).
>>> ?Right there that says that the abstraction is at the wrong level.
>>> What happens when an mostly transparent bridge is added with its own
>>> peripherals and its own special operations? ?Does this routine then
>>> need to be extended for each new special case? ?It's not maintainable
>>> in the long run.
>>>
>>> This approach is also not multiplatform friendly (cc'ing Eric and
>>> Nicolas who are working on ARM multiplatform). ?It won't work for
>>> building a kernel that supports, say, both versatile and OMAP.
>>
>> Totally agree here, but this a separate issue not specifically created
>> by this series (it was created when runtime PM support for SH was
>> added), but indeed I am continuining bad behavior. :/
>
> I think I could successfully argue that ARM is more important that SH.
>  If SH messes up it's sandbox the collateral damage isn't nearly so
> severe.  Don't follow the SH lead in this case.
>
>> The issue is that the current method to override bus methods is by
>> overriding weak symbols. ?This clearly doesn't scale to support multiple
>> platforms in the same image.
>
> Agreed.  It scales better to change the hooks at runtime, which is
> actually quite easy, but it still leaves the abstraction at the wrong
> level.
>
>> What would be needed (if we continue to override the platform_bus
>> methods) is to have some sort of register function for overriding these
>> methods. ?I'll look into that based on the result of discussions
>> below...
>>
>>> The kernel already has the facility to do what you need. ?We talked
>>> about it briefly at ELC, and now that I look at it closer, I thing
>>> gregkh is absolutely right. ?Just create a new bus type for OMAP
>>> devices. ?It is simple to add one. ?You can probably even call out to
>>> the platform bus ops for most of the operations. ?The fact that OMAP
>>> devices have special behaviour that needs to be handled at the bus
>>> type level means that they are not platform devices anymore. ?This
>>> also eliminates all the omap_device_is_valid and OMAP_DEVICE_MAGIC
>>> gymnastics.
>>>
>>> I see from the comments in omap_device.c that doing an
>>> omap_bus/omap_device is being considered anyway. ?Please don't merge
>>> this patch and do the omap_bus_type instead.
>>
>> Agreed, it is logicially simpler in many ways and as you've noticed,
>> we've been discussing it in the OMAP community.
>>
>> However, I keep coming back to extending the platform bus, primarily
>> since the resulting new bus code would look almost identical to the
>> platform bus. ?All I really needed is the ability to extend a small
>> subset of the PM functions, so this led to me the "extend instead of
>> duplicate" approach.
>>
>> In addition, I really don't want to duplicate all the platform_driver
>> and platform_device code, again because it would be identical but
>> especially since this would seriously impact many drivers. ?For drivers
>> that are used on OMAP and also on other platforms, do we want drivers to
>> know (or care) if they are on the platform bus or on the OMAP bus?
>
> Some questions to make sure I understand:
> Do you have a lot of these cases?

Yes, there are several.

There are several instances of hardware blocks that are re-used across
OMAP and DaVinci but where the device clocking and PM infrastructure is
totally different.  Runtime PM helps a lot here in that all the details
can be done in low-level, SoC specific code.  

There are even cases of OMAP-derivative parts that will change clocking
or change (or remove) PM internal details and require special handling.
We want to be able to use the same driver for all these, and not care
if it's an OMAP, Davinci, OMAP-derivative etc.

There's also the special case of the MUSB driver which is on OMAP,
Davinci and Blackfin.

> Do non-OMAP devices also have to process the omap clock enable/disable
> code too, or is this only for stuff that is internal to the chip?

This is only for on-chip devices.  But as I said above, there are
on-chip devices on OMAP that are used on other platforms, and the driver
should be re-usable, without OMAP-specific knowledge.

> Or is this the case where existing non-omap device drivers can also
> drive the omap SoC hardware?
>
>> I think this is how it is done for OF devices, but I'm not crazy about
>> that approach (after our discussions at ELC, I remember thinking you'd
>> been through this with the OF devices as well and are moving towards
>> using platform_bus/platform_device for those too. ?Did I understand
>> correctly?)
>
> Yes, I've got patches which merge of_platform_bus_type with the
> platform bus.  This was an easy decision to make because the
> of-specific bits (specifically, matching an of_device_id table with a
> device tree node) are applicable to all bus types; i2c, spi, mdio,
> platform, etc).  The needed OF data structures have been moved into
> struct device and struct device_driver so that of_platform_bus_type no
> longer has anything different.
>
> The drivers still need to care about OF when extra platform data needs
> to be extracted from the DT node, but for IRQs and register ranges it
> is automatic.

Does that mean the drivers are still doing platform_get_resource() for
either platform devices or OF devices, or are does the driver have to
know which bus it was on and call accordingly.  It's the latter that I
want to stay away from.

> The omap case looks different.  You've got special runtime pm ops that
> you want to hook in; but only for omap_devices.  It doesn't really
> apply to more than one bus type in the system.
>
>> This affects many aspects of all drivers, from register and probe (for
>> early devices/drivers too!) to all the plaform_get_resource() usage, all
>> of which assumes a platform_driver and platform_device. ?I didn't look
>> closely, but I didn't see if (or how) OF was handling early devices.
>
> You don't have to reimplement the entire platform bus.  You could
> simply create a new bus type, but reuse all the existing platform bus
> code.  All that changes is the bus type that the device and the driver
> gets registered on.  Then you could easily replace only the functions
> that matter.  (do a git grep platform_bus_type to see how few
> references there actually are.  It looks like there are only 5
> references to it in drivers/base/platform.c that you'd need to work
> around; in platform_device_add(), platform_driver_register(), 2 in
> platform_driver_probe(), and the register in platform_bus_init().  You
> may not even need to reimplement platform_driver_probe().
>
> It might even be as simple as doing this:
> -        pdev->dev.bus = &platform_bus_type;
> +       if (!pdev->dev.bus)
> +                pdev->dev.bus = &platform_bus_type;

Yeah, I found those and already started exploring that change.

> So that a different bus type can be selected at device registration
> time (but this might be a little on the dangerous side.  It might be
> better to have a wrapper function that accepts an omap_device, and
> then does the appropriate registration so that the compiler can
> type-check it for you).
>
> Another way to look at the problem is that these runtime
> customizations are kind of a property of the parent device (the bus,
> not the bus_type).  Would it make sense for parent devices to have
> runtime ops to perform for each child that is suspended/resumed?  That
> would make it simple to register another device that implements the
> bus behaviour and attach it at runtime instead of compile time.
>
> So, instead of having all the platform_bus_type devices as children of
> the "platform" device (/sys/devices/platform/*), you could set the
> omap devices to be children of an omap bus device
> (/sys/devices/omap/*).  Different busses can also implement different
> behaviour by using a different parent device.  For example:
>
> /sys/devices/platform
> /sys/devices/omap-bus-a
> /sys/devices/omap-bus-a/omap-bus-b
>
> Thoughts?

Hmm, I like this idea.  This is certainly worth exploring as a first
pass.

Thanks for the idea,

Kevin

>
>> All that being said, if I could create a custom bus, but continue to use
>> platform_devices, that would greatly simply the changes to drivers. ?Do
>> you think that's acceptable? ?If so, I can take a stab at that and see
>> what it looks like.
>
> Heh, I should read the whole email before replying.  See above.
>
>>> Also, I notice that most of these hooks open-code the generic versions
>>> of the runtime hooks. ?Instead of open coding it, can the omap hooks
>>> call the generic hooks before/after doing the omap-specific work?
>>
>> Ah, good point.
>>
>> This patch pre-dates the creation of pm_generic_runtime_*, but certainly
>> should be upgraded to use those. ?Thanks.
>>
>> Kevin
>>
>>
>>> Cheers,
>>> g.
>>>
>>>>
>>>> Signed-off-by: Kevin Hilman <khilman at deeprootsystems.com>
>>>> ---
>>>> ?arch/arm/mach-omap2/Makefile | ? ?7 +++-
>>>> ?arch/arm/mach-omap2/pm_bus.c | ? 70 ++++++++++++++++++++++++++++++++++++++++++
>>>> ?2 files changed, 76 insertions(+), 1 deletions(-)
>>>> ?create mode 100644 arch/arm/mach-omap2/pm_bus.c
>>>>
>>>> diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
>>>> index ea52b03..8ed47ea 100644
>>>> --- a/arch/arm/mach-omap2/Makefile
>>>> +++ b/arch/arm/mach-omap2/Makefile
>>>> @@ -46,12 +46,17 @@ obj-$(CONFIG_ARCH_OMAP2) ? ? ? ? ? ?+= sdrc2xxx.o
>>>> ?ifeq ($(CONFIG_PM),y)
>>>> ?obj-$(CONFIG_ARCH_OMAP2) ? ? ? ? ? ? ? += pm24xx.o
>>>> ?obj-$(CONFIG_ARCH_OMAP2) ? ? ? ? ? ? ? += sleep24xx.o
>>>> -obj-$(CONFIG_ARCH_OMAP3) ? ? ? ? ? ? ? += pm34xx.o sleep34xx.o cpuidle34xx.o
>>>> +obj-$(CONFIG_ARCH_OMAP3) ? ? ? ? ? ? ? += pm34xx.o sleep34xx.o cpuidle34xx.o \
>>>> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?pm_bus.o
>>>> ?obj-$(CONFIG_PM_DEBUG) ? ? ? ? ? ? ? ? += pm-debug.o
>>>>
>>>> ?AFLAGS_sleep24xx.o ? ? ? ? ? ? ? ? ? ? :=-Wa,-march=armv6
>>>> ?AFLAGS_sleep34xx.o ? ? ? ? ? ? ? ? ? ? :=-Wa,-march=armv7-a
>>>>
>>>> +ifeq ($(CONFIG_PM_VERBOSE),y)
>>>> +CFLAGS_pm_bus.o ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?+= -DDEBUG
>>>> +endif
>>>> +
>>>> ?endif
>>>>
>>>> ?# PRCM
>>>> diff --git a/arch/arm/mach-omap2/pm_bus.c b/arch/arm/mach-omap2/pm_bus.c
>>>> new file mode 100644
>>>> index 0000000..9719a9f
>>>> --- /dev/null
>>>> +++ b/arch/arm/mach-omap2/pm_bus.c
>>>> @@ -0,0 +1,70 @@
>>>> +/*
>>>> + * Runtime PM support code for OMAP
>>>> + *
>>>> + * Author: Kevin Hilman, Deep Root Systems, LLC
>>>> + *
>>>> + * Copyright (C) 2010 Texas Instruments, Inc.
>>>> + *
>>>> + * This file is licensed under the terms of the GNU General Public
>>>> + * License version 2. This program is licensed "as is" without any
>>>> + * warranty of any kind, whether express or implied.
>>>> + */
>>>> +#include <linux/init.h>
>>>> +#include <linux/kernel.h>
>>>> +#include <linux/io.h>
>>>> +#include <linux/pm_runtime.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <linux/mutex.h>
>>>> +
>>>> +#include <plat/omap_device.h>
>>>> +#include <plat/omap-pm.h>
>>>> +
>>>> +#ifdef CONFIG_PM_RUNTIME
>>>> +int platform_pm_runtime_suspend(struct device *dev)
>>>> +{
>>>> + ? ? ? struct platform_device *pdev = to_platform_device(dev);
>>>> + ? ? ? struct omap_device *odev = to_omap_device(pdev);
>>>> + ? ? ? int r, ret = 0;
>>>> +
>>>> + ? ? ? dev_dbg(dev, "%s\n", __func__);
>>>> +
>>>> + ? ? ? if (dev->driver->pm && dev->driver->pm->runtime_suspend)
>>>> + ? ? ? ? ? ? ? ret = dev->driver->pm->runtime_suspend(dev);
>>>> + ? ? ? if (!ret && omap_device_is_valid(odev)) {
>>>> + ? ? ? ? ? ? ? r = omap_device_idle(pdev);
>>>> + ? ? ? ? ? ? ? WARN_ON(r);
>>>> + ? ? ? }
>>>> +
>>>> + ? ? ? return ret;
>>>> +};
>>>> +
>>>> +int platform_pm_runtime_resume(struct device *dev)
>>>> +{
>>>> + ? ? ? struct platform_device *pdev = to_platform_device(dev);
>>>> + ? ? ? struct omap_device *odev = to_omap_device(pdev);
>>>> + ? ? ? int r, ret = 0;
>>>> +
>>>> + ? ? ? dev_dbg(dev, "%s\n", __func__);
>>>> +
>>>> + ? ? ? if (omap_device_is_valid(odev)) {
>>>> + ? ? ? ? ? ? ? r = omap_device_enable(pdev);
>>>> + ? ? ? ? ? ? ? WARN_ON(r);
>>>> + ? ? ? }
>>>> +
>>>> + ? ? ? if (dev->driver->pm && dev->driver->pm->runtime_resume)
>>>> + ? ? ? ? ? ? ? ret = dev->driver->pm->runtime_resume(dev);
>>>> +
>>>> + ? ? ? return ret;
>>>> +};
>>>> +
>>>> +int platform_pm_runtime_idle(struct device *dev)
>>>> +{
>>>> + ? ? ? int ret;
>>>> +
>>>> + ? ? ? ret = pm_runtime_suspend(dev);
>>>> + ? ? ? dev_dbg(dev, "%s [%d]\n", __func__, ret);
>>>> +
>>>> + ? ? ? return 0;
>>>> +};
>>>> +#endif /* CONFIG_PM_RUNTIME */
>>>> +
>>>> --
>>>> 1.7.0.2
>>>>
>>>>
>>>> _______________________________________________
>>>> linux-arm-kernel mailing list
>>>> linux-arm-kernel at lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>>
>>


From grant.likely at secretlab.ca  Fri Jun 25 18:30:56 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 25 Jun 2010 16:30:56 -0600
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <87wrtmepum.fsf@deeprootsystems.com>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com> 
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com> 
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com> 
	<874ogrng3j.fsf@deeprootsystems.com>
	<AANLkTimMnJvOJrRHDiE6PH1BXpRz2-6pY1M9nKHw7vpn@mail.gmail.com> 
	<87wrtmepum.fsf@deeprootsystems.com>
Message-ID: <AANLkTimcN6APawXLTzGIBUJ6DeGv8B0MEhbeJFkO59R-@mail.gmail.com>

On Fri, Jun 25, 2010 at 3:58 PM, Kevin Hilman
<khilman at deeprootsystems.com> wrote:
> Grant Likely <grant.likely at secretlab.ca> writes:
>> Yes, I've got patches which merge of_platform_bus_type with the
>> platform bus. ?This was an easy decision to make because the
>> of-specific bits (specifically, matching an of_device_id table with a
>> device tree node) are applicable to all bus types; i2c, spi, mdio,
>> platform, etc). ?The needed OF data structures have been moved into
>> struct device and struct device_driver so that of_platform_bus_type no
>> longer has anything different.
>>
>> The drivers still need to care about OF when extra platform data needs
>> to be extracted from the DT node, but for IRQs and register ranges it
>> is automatic.
>
> Does that mean the drivers are still doing platform_get_resource() for
> either platform devices or OF devices, or are does the driver have to
> know which bus it was on and call accordingly. ?It's the latter that I
> want to stay away from.

platform_get_resource() works for OF and non-OF platform devices with
no extra code needed in the OF case.

It's the other data that requires special code because it is provided
in the device tree instead of in a platform_data structure.  A driver
that normally uses platform_data will need extra code early in the
probe hook to go and parse the device tree and populate the private
data structures accordingly.  This behaviour has to be handled in the
driver because every driver uses a different platform_data structure.
It cannot be generic code.  The rest of the driver can remain
untouched.

In the old (bad) way, the bus type was entirely different, and drivers
used by both platform_bus_type and of_platform_bus_type needed to have
entirely separate device_driver structures and probe() hooks for each
bus type.

[...]
>> So, instead of having all the platform_bus_type devices as children of
>> the "platform" device (/sys/devices/platform/*), you could set the
>> omap devices to be children of an omap bus device
>> (/sys/devices/omap/*). ?Different busses can also implement different
>> behaviour by using a different parent device. ?For example:
>>
>> /sys/devices/platform
>> /sys/devices/omap-bus-a
>> /sys/devices/omap-bus-a/omap-bus-b
>>
>> Thoughts?
>
> Hmm, I like this idea. ?This is certainly worth exploring as a first
> pass.
>
> Thanks for the idea,

:-)
g.


From khilman at deeprootsystems.com  Fri Jun 25 18:46:02 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Fri, 25 Jun 2010 15:46:02 -0700
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <AANLkTimMnJvOJrRHDiE6PH1BXpRz2-6pY1M9nKHw7vpn@mail.gmail.com>
	(Grant Likely's message of "Fri, 25 Jun 2010 14:08:51 -0600")
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>
	<874ogrng3j.fsf@deeprootsystems.com>
	<AANLkTimMnJvOJrRHDiE6PH1BXpRz2-6pY1M9nKHw7vpn@mail.gmail.com>
Message-ID: <876316eno5.fsf@deeprootsystems.com>

Grant Likely <grant.likely at secretlab.ca> writes:

> Another way to look at the problem is that these runtime
> customizations are kind of a property of the parent device (the bus,
> not the bus_type).  Would it make sense for parent devices to have
> runtime ops to perform for each child that is suspended/resumed?  That
> would make it simple to register another device that implements the
> bus behaviour and attach it at runtime instead of compile time.

Maybe I didn't fully understand your idea, but the problem here is
devices do not have dev_pm_ops.  Only busses, classes, and types have
dev_pm_ops.

Though I'm horribly unfamiliar with the intended usage of 'struct
device_type', an interesing discovery is that dev->type also has
dev_pm_ops, and it takes precedence over the bus type in the
suspend/resume.  IOW, when suspending, when deciding which dev_pm_ops to
use, it checks class, type, then bus in that order.

I need to explore this 'type' feature a little more, but using that or
the 'class' might be another way to have custom PM ops for certain
platform_devices.

Kevin


From grant.likely at secretlab.ca  Fri Jun 25 19:04:13 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Fri, 25 Jun 2010 17:04:13 -0600
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <876316eno5.fsf@deeprootsystems.com>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com> 
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com> 
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com> 
	<874ogrng3j.fsf@deeprootsystems.com>
	<AANLkTimMnJvOJrRHDiE6PH1BXpRz2-6pY1M9nKHw7vpn@mail.gmail.com> 
	<876316eno5.fsf@deeprootsystems.com>
Message-ID: <AANLkTimB0_OfLDvtkwwTE-kVeZrardIxVIsD5IEia-vL@mail.gmail.com>

On Fri, Jun 25, 2010 at 4:46 PM, Kevin Hilman
<khilman at deeprootsystems.com> wrote:
> Grant Likely <grant.likely at secretlab.ca> writes:
>
>> Another way to look at the problem is that these runtime
>> customizations are kind of a property of the parent device (the bus,
>> not the bus_type). ?Would it make sense for parent devices to have
>> runtime ops to perform for each child that is suspended/resumed? ?That
>> would make it simple to register another device that implements the
>> bus behaviour and attach it at runtime instead of compile time.
>
> Maybe I didn't fully understand your idea, but the problem here is
> devices do not have dev_pm_ops. ?Only busses, classes, and types have
> dev_pm_ops.

Sorry, I mistyped.  What I meant was for the parent device's
device_driver to be able to have a set of child dev_pm_ops; but I'm
wading into territory (power management) I'm not particularly familiar
with, and that might be making things far too complex.

> Though I'm horribly unfamiliar with the intended usage of 'struct
> device_type', an interesing discovery is that dev->type also has
> dev_pm_ops, and it takes precedence over the bus type in the
> suspend/resume. ?IOW, when suspending, when deciding which dev_pm_ops to
> use, it checks class, type, then bus in that order.

So I guess my suggestion above boils down to somehow inserting
"parent" between type and bus in that list.

> I need to explore this 'type' feature a little more, but using that or
> the 'class' might be another way to have custom PM ops for certain
> platform_devices.

Should maybe start cc'ing Greg and linux-kernel/linux-pm in this discussion.

g.


From nico at fluxnic.net  Fri Jun 25 19:46:05 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Fri, 25 Jun 2010 19:46:05 -0400 (EDT)
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <20100625202002.GC22090@n2100.arm.linux.org.uk>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>
	<20100625200659.GB22090@n2100.arm.linux.org.uk>
	<AANLkTikYE6Kg8C_ZClx9aKLvOa9CQRUT587hQnB91sua@mail.gmail.com>
	<20100625202002.GC22090@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.00.1006251941190.24097@xanadu.home>

On Fri, 25 Jun 2010, Russell King - ARM Linux wrote:

> Does anyone know where we are on the defconfig problem?  From what I
> can see, it's mostly stalled for the time being, which is not good
> news for us.

What looked to be promizing is the work by Uwe Kleine-K?nig according to 
the preview he posted on June 10:
  
Message-id: <20100610063234.GA22533 at pengutronix.de>


Nicolas

From davem at davemloft.net  Sat Jun 26 00:36:17 2010
From: davem at davemloft.net (David Miller)
Date: Fri, 25 Jun 2010 21:36:17 -0700 (PDT)
Subject: [PATCH 1/2] net/fec: clean suspend/resume
In-Reply-To: <1276853351-20790-1-git-send-email-eric@eukrea.com>
References: <1276853351-20790-1-git-send-email-eric@eukrea.com>
Message-ID: <20100625.213617.235709938.davem@davemloft.net>

From: Eric B?nard <eric at eukrea.com>
Date: Fri, 18 Jun 2010 11:29:10 +0200

> Commit 59d4289b83b11379d867e2f7146904b19cc96404 converted fec to dev_pm_ops but
> didn't update the suspend/resume functions thus leading to the following warning :
> "initialization from incompatible pointer type" when CONFIG_PM is set.
> 
> This patch also fixe a few indentation and style around CONFIG_PM area.
> 
> Signed-off-by: Eric B?nard <eric at eukrea.com>

Applied.


From eric.miao at canonical.com  Sat Jun 26 04:47:05 2010
From: eric.miao at canonical.com (eric.miao at canonical.com)
Date: Sat, 26 Jun 2010 16:47:05 +0800
Subject: [PATCH] [ARM] Introduce patching of phys_to_virt and vice versa
Message-ID: <1277542025-19881-1-git-send-email-eric.miao@canonical.com>

From: Eric Miao <eric.miao at canonical.com>

In most cases, the delta between PHYS_OFFSET and PAGE_OFFSET is normally
16MiB aligned, which means the difference can be handled by a simple ADD
or SUB instruction with an immediate shift operand in ARM.  This will be
a bit more efficient and generic when PHYS_OFFSET goes run-time.

This idea can be made generic to allow conversions more than phys_to_virt
and virt_to_phys. A stub instruction is inserted where applicable, and it
has a form of 'add rn, rd, #imm', where the lowest 8-bit of #imm is used
to identify the type of patching.  Currently, only two types are defined,
but could be expanded in my POV to definitions like __io(), __mem_pci()
and so on. A __patch_table section is introduced to include the addresses
of all these stub instructions.

There are several places for improvement:

1. constant parameters which can be optimized by the compiler now needs
   one additional instruction (although the optimization is neither
   possible when PHYS_OFFSET goes a variable)

2. flush_cache_all() when patching is done seems to be brute but simple
   enough here in this patch to show a proof concept

Any thing else?

PS: the general idea comes from Nicolas Pitre, and is drafted at
    https://wiki.ubuntu.com/Specs/ARMSingleKernel

Cc: Nicolas Pitre <nicolas.pitre at canonical.com>
Signed-off-by: Eric Miao <eric.miao at canonical.com>
---
 arch/arm/Kconfig              |    4 +++
 arch/arm/include/asm/memory.h |   32 ++++++++++++++++++++++++++
 arch/arm/kernel/setup.c       |   50 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/vmlinux.lds.S |    4 +++
 4 files changed, 90 insertions(+), 0 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..0c171c2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -189,6 +189,9 @@ config VECTORS_BASE
 	help
 	  The base address of exception vectors.
 
+config PATCH_PHYS_VIRT
+	def_bool n
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
@@ -579,6 +582,7 @@ config ARCH_PXA
 	select GENERIC_CLOCKEVENTS
 	select TICK_ONESHOT
 	select PLAT_PXA
+	select PATCH_PHYS_VIRT if !XIP_KERNEL
 	help
 	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
 
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 4312ee5..a5f84bc 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -173,6 +173,37 @@
  */
 #define PHYS_PFN_OFFSET	(PHYS_OFFSET >> PAGE_SHIFT)
 
+#ifdef CONFIG_PATCH_PHYS_VIRT
+
+#define PATCH_TYPE_PHYS_TO_VIRT		(0)
+#define PATCH_TYPE_VIRT_TO_PHYS		(1)
+
+#define __patch_stub(from,to,type)			\
+	__asm__ __volatile__(				\
+	"1:	add	%0, %1, %2\n"			\
+	"\n"						\
+	"	.pushsection __patch_table,\"a\"\n"	\
+	"	.long	1b\n"				\
+	"	.popsection\n"				\
+	: "=r" (to)					\
+	: "r" (from), "i" (type))
+
+static inline unsigned long virt_to_phys(void *x)
+{
+	unsigned long t;
+
+	__patch_stub(x, t, PATCH_TYPE_VIRT_TO_PHYS);
+	return t;
+}
+
+static inline void *phys_to_virt(unsigned long x)
+{
+	void *t;
+
+	__patch_stub(x, t, PATCH_TYPE_PHYS_TO_VIRT);
+	return t;
+}
+#else
 /*
  * These are *only* valid on the kernel direct mapped RAM memory.
  * Note: Drivers should NOT use these.  They are the wrong
@@ -188,6 +219,7 @@ static inline void *phys_to_virt(unsigned long x)
 {
 	return (void *)(__phys_to_virt((unsigned long)(x)));
 }
+#endif
 
 /*
  * Drivers should NOT use these either.
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 122d999..d265b50 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -663,12 +663,62 @@ static int __init customize_machine(void)
 }
 arch_initcall(customize_machine);
 
+#ifdef CONFIG_PATCH_PHYS_VIRT
+
+#define PATCH_INSTR_ADD		(0x00800000)
+#define PATCH_INSTR_SUB		(0x00400000)
+
+#define PATCH_STUB_MASK		(0xffe000ff)
+#define PATCH_STUB_PHYS_TO_VIRT	(0xe2800000 | PATCH_TYPE_PHYS_TO_VIRT)
+#define PATCH_STUB_VIRT_TO_PHYS	(0xe2800000 | PATCH_TYPE_VIRT_TO_PHYS)
+
+/* patch_phys_virt - patch the stub instructions with the delta between
+ * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
+ * can be expressed by an immediate shifter operand. The stub instruction
+ * has a form of 'add rn, rd, #imm', where the lowest 8-bit of #imm is
+ * used to identify the type of patching.
+ */
+static void __init patch_phys_virt(void)
+{
+	extern unsigned int *__patch_table_begin, *__patch_table_end;
+	unsigned int **p;
+	unsigned int imm, instr[2];
+
+	if (PHYS_OFFSET & 0x00ffffff)
+		panic("Physical memory start is not 16MiB aligned\n");
+
+	if (likely(PHYS_OFFSET < PAGE_OFFSET)) {
+		imm = 0x400 | ((PAGE_OFFSET >> 24) - (PHYS_OFFSET >> 24));
+		instr[0] = PATCH_INSTR_ADD | imm;
+		instr[1] = PATCH_INSTR_SUB | imm;
+	} else {
+		imm = 0x400 | ((PHYS_OFFSET >> 24) - (PAGE_OFFSET >> 24));
+		instr[0] = PATCH_INSTR_SUB | imm;
+		instr[1] = PATCH_INSTR_ADD | imm;
+	}
+
+	for (p = &__patch_table_begin; p < &__patch_table_end; p++) {
+		unsigned int *inptr = *p;
+
+		if ((*inptr & PATCH_STUB_MASK) == PATCH_STUB_PHYS_TO_VIRT)
+			*inptr = (*inptr & ~0x00e00fff) | instr[0];
+		if ((*inptr & PATCH_STUB_MASK) == PATCH_STUB_VIRT_TO_PHYS)
+			*inptr = (*inptr & ~0x00e00fff) | instr[1];
+	}
+	flush_cache_all();
+}
+#else
+static inline void patch_phys_virt(void) {}
+#endif
+
 void __init setup_arch(char **cmdline_p)
 {
 	struct tag *tags = (struct tag *)&init_tags;
 	struct machine_desc *mdesc;
 	char *from = default_command_line;
 
+	patch_phys_virt();
+
 	unwind_init();
 
 	setup_processor();
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..c48c754 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -41,6 +41,10 @@ SECTIONS
 			*(.taglist.init)
 		__tagtable_end = .;
 
+		__patch_table_begin = .;
+			*(__patch_table)
+		__patch_table_end = .;
+
 		INIT_SETUP(16)
 
 		INIT_CALLS
-- 
1.7.1



From eric.miao at canonical.com  Sat Jun 26 04:50:32 2010
From: eric.miao at canonical.com (Eric Miao)
Date: Sat, 26 Jun 2010 16:50:32 +0800
Subject: [PATCH] [ARM] Introduce patching of phys_to_virt and vice versa
In-Reply-To: <1277542025-19881-1-git-send-email-eric.miao@canonical.com>
References: <1277542025-19881-1-git-send-email-eric.miao@canonical.com>
Message-ID: <AANLkTinVZdN0Ltbk6H9YMPDT4OZ2-2S7_3vLKcBEfxgT@mail.gmail.com>

> +config PATCH_PHYS_VIRT
> + ? ? ? def_bool n
> +
> ?source "init/Kconfig"
>
> ?source "kernel/Kconfig.freezer"
> @@ -579,6 +582,7 @@ config ARCH_PXA
> ? ? ? ?select GENERIC_CLOCKEVENTS
> ? ? ? ?select TICK_ONESHOT
> ? ? ? ?select PLAT_PXA
> + ? ? ? select PATCH_PHYS_VIRT if !XIP_KERNEL

Tested on PXA, so ignore this change at the moment.


From john.ogness at linutronix.de  Sat Jun 26 05:17:35 2010
From: john.ogness at linutronix.de (John Ogness)
Date: Sat, 26 Jun 2010 11:17:35 +0200
Subject: [PATCHv3 4/5] mtd: mxc_nand fixups
In-Reply-To: <AANLkTilTbvlPxRhioMiKrBUNggcxZeboi1YpB8Y9Bdpm@mail.gmail.com>
	(Ivo Clarysse's message of "Fri, 25 Jun 2010 16:50:45 +0200")
References: <20100618205401.GA12115@pengutronix.de>
	<80sk4ivkga.fsf@merkur.tec.linutronix.de>
	<AANLkTimA7Rbm_nHpVYpEPqaPCjrOse9s8YyiInWlhfEK@mail.gmail.com>
	<80tyoyhxey.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTikRj_dMkKLyFhW78yld9jIYAIFncfPaPAF8WqUY@mail.gmail.com>
	<80iq5bqd07.fsf_-_@merkur.tec.linutronix.de>
	<AANLkTimJKNEwOoKldq4a4_ufxNY6IY7r6tAfAM055hlW@mail.gmail.com>
	<80vd9ab0d2.fsf@merkur.tec.linutronix.de>
	<AANLkTinVaXjCneg-XpxB7YNlmGOwQFTnm5RUcetPdToI@mail.gmail.com>
	<80lja6awlb.fsf@merkur.tec.linutronix.de>
	<20100624072732.GQ12115@pengutronix.de>
	<807hloag6w.fsf@merkur.tec.linutronix.de>
	<AANLkTilTbvlPxRhioMiKrBUNggcxZeboi1YpB8Y9Bdpm@mail.gmail.com>
Message-ID: <80y6e2kv9s.fsf@merkur.tec.linutronix.de>

On 2010-06-25, Ivo Clarysse <ivo.clarysse at gmail.com> wrote:
> Tested on an MX21ADS board, and it still works.
>
> [...]
>
> Naming is not very consistent; I'd suggest nfc_set_interrupt /
> nfc_clear_interrupt

Actually, the set function is a query, not an action. I've renamed it
nfc_isset_interrupt() so that it is clearer. I also fixed a typo in one
of the comments.

This patch is based on linux-next 20100618.

Signed-off-by: John Ogness <john.ogness at linutronix.de>
---
 drivers/mtd/nand/mxc_nand.c |   81 +++++++++++++++++++++++++---------
 1 file changed, 61 insertions(+), 20 deletions(-)

Index: linux-next-20100618/drivers/mtd/nand/mxc_nand.c
===================================================================
--- linux-next-20100618.orig/drivers/mtd/nand/mxc_nand.c
+++ linux-next-20100618/drivers/mtd/nand/mxc_nand.c
@@ -30,6 +30,8 @@
 #include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/completion.h>
 
 #include <asm/mach/flash.h>
 #include <mach/mxc_nand.h>
@@ -40,6 +42,13 @@
 #define nfc_is_v21()		(cpu_is_mx25() || cpu_is_mx35())
 #define nfc_is_v1()		(cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
 
+/* It has been observed that the i.MX21 cannot read the CONFIG2:INT bit
+ * if interrupts are masked (CONFIG1:INT_MSK is set). To handle this, the
+ * driver can enable/disable the irq line rather than simply masking the
+ * interrupts. The nfc_avoid_masking() macro identifies the systems that
+ * should use this workaround. */
+#define nfc_avoid_masking()	(cpu_is_mx21())
+
 /* Addresses for NFC registers */
 #define NFC_BUF_SIZE		0xE00
 #define NFC_BUF_ADDR		0xE04
@@ -100,6 +109,18 @@
 
 #define NFC_RSLTSPARE_AREA_MASK  0xff
 
+#define nfc_isset_interrupt(_regs) \
+		(readw(_regs + NFC_CONFIG2) & NFC_INT)
+#define nfc_clear_interrupt(_regs) \
+		writew(readw(_regs + NFC_CONFIG2) & ~NFC_INT, \
+		       _regs + NFC_CONFIG2)
+#define nfc_mask_irq(_regs) \
+		writew(readw(_regs + NFC_CONFIG1) | NFC_INT_MSK, \
+		       _regs + NFC_CONFIG1)
+#define nfc_unmask_irq(_regs) \
+		writew(readw(_regs + NFC_CONFIG1) & ~NFC_INT_MSK, \
+		       _regs + NFC_CONFIG1)
+
 struct mxc_nand_host {
 	struct mtd_info		mtd;
 	struct nand_chip	nand;
@@ -117,7 +138,7 @@ struct mxc_nand_host {
 	int			clk_act;
 	int			irq;
 
-	wait_queue_head_t	irq_waitq;
+	struct completion	op_completion;
 
 	uint8_t			*data_buf;
 	unsigned int		buf_start;
@@ -174,9 +195,18 @@ static irqreturn_t mxc_nfc_irq(int irq, 
 {
 	struct mxc_nand_host *host = dev_id;
 
-	disable_irq_nosync(irq);
-
-	wake_up(&host->irq_waitq);
+	/* If NFC_INT is not set, we have a spurious interrupt! */
+	if (!nfc_isset_interrupt(host->regs))
+		return IRQ_NONE;
+
+	/* Even with nfc_avoid_masking() we mask the interrupt
+	 * here to avoid an interrupt flood until the irq line
+	 * is disabled by the driver thread. */
+	nfc_mask_irq(host->regs);
+
+	/* Notify the driver thread that an interrupt has occurred.
+	 * The driver thread will clear the interrupt. */
+	complete(&host->op_completion);
 
 	return IRQ_HANDLED;
 }
@@ -186,27 +216,32 @@ static irqreturn_t mxc_nfc_irq(int irq, 
  */
 static void wait_op_done(struct mxc_nand_host *host, int useirq)
 {
-	uint16_t tmp;
 	int max_retries = 8000;
 
 	if (useirq) {
-		if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
+		if (!nfc_isset_interrupt(host->regs)) {
+
+			INIT_COMPLETION(host->op_completion);
 
-			enable_irq(host->irq);
+			if (nfc_avoid_masking())
+				enable_irq(host->irq);
+			else
+				nfc_unmask_irq(host->regs);
 
-			wait_event(host->irq_waitq,
-				readw(host->regs + NFC_CONFIG2) & NFC_INT);
+			/* wait for the interrupt */
+			wait_for_completion(&host->op_completion);
 
-			tmp = readw(host->regs + NFC_CONFIG2);
-			tmp  &= ~NFC_INT;
-			writew(tmp, host->regs + NFC_CONFIG2);
+			if (nfc_avoid_masking()) {
+				disable_irq(host->irq);
+				nfc_unmask_irq(host->regs);
+			}
 		}
+
+		nfc_clear_interrupt(host->regs);
 	} else {
 		while (max_retries-- > 0) {
-			if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
-				tmp = readw(host->regs + NFC_CONFIG2);
-				tmp  &= ~NFC_INT;
-				writew(tmp, host->regs + NFC_CONFIG2);
+			if (nfc_isset_interrupt(host->regs)) {
+				nfc_clear_interrupt(host->regs);
 				break;
 			}
 			udelay(1);
@@ -582,9 +617,8 @@ static void preset(struct mtd_info *mtd)
 	struct mxc_nand_host *host = nand_chip->priv;
 	uint16_t tmp;
 
-	/* enable interrupt, disable spare enable, setup ECC */
+	/* disable spare-only, setup ECC */
 	tmp = readw(host->regs + NFC_CONFIG1);
-	tmp &= ~NFC_INT_MSK;
 	tmp &= ~NFC_SP_EN;
 	if (nand_chip->ecc.mode == NAND_ECC_HW) {
 		tmp |= NFC_ECC_EN;
@@ -842,11 +876,18 @@ static int __init mxcnd_probe(struct pla
 		this->options |= NAND_USE_FLASH_BBT;
 	}
 
-	init_waitqueue_head(&host->irq_waitq);
+	init_completion(&host->op_completion);
 
 	host->irq = platform_get_irq(pdev, 0);
 
-	err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
+	if (nfc_avoid_masking()) {
+		set_irq_flags(host->irq, IRQF_VALID | IRQF_NOAUTOEN);
+		nfc_unmask_irq(host->regs);
+	} else {
+		nfc_mask_irq(host->regs);
+	}
+
+	err = request_irq(host->irq, mxc_nfc_irq, 0, DRIVER_NAME, host);
 	if (err)
 		goto eirq;
 


From linux at arm.linux.org.uk  Sat Jun 26 05:54:20 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 26 Jun 2010 10:54:20 +0100
Subject: [PATCH] [ARM] Introduce patching of phys_to_virt and vice versa
In-Reply-To: <1277542025-19881-1-git-send-email-eric.miao@canonical.com>
References: <1277542025-19881-1-git-send-email-eric.miao@canonical.com>
Message-ID: <20100626095420.GA10340@n2100.arm.linux.org.uk>

Mostly like this patch, but there's a couple of issues with it which
can be worked around by documentation...

On Sat, Jun 26, 2010 at 04:47:05PM +0800, eric.miao at canonical.com wrote:
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 1f254bd..0c171c2 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -189,6 +189,9 @@ config VECTORS_BASE
>  	help
>  	  The base address of exception vectors.
>  
> +config PATCH_PHYS_VIRT

ARM_PATCH_PHYS_TO_VIRT might be a better name?

> +	def_bool n
> +
>  source "init/Kconfig"
>  
>  source "kernel/Kconfig.freezer"
> @@ -579,6 +582,7 @@ config ARCH_PXA
>  	select GENERIC_CLOCKEVENTS
>  	select TICK_ONESHOT
>  	select PLAT_PXA
> +	select PATCH_PHYS_VIRT if !XIP_KERNEL

It needs to be documented that PATCH_PHYS_VIRT is only for non-XIP and
non-Thumb2 kernels.  I suggest it goes in the help text for the config
option, or a comment before the option.

>  	help
>  	  Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
>  
> diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
> index 4312ee5..a5f84bc 100644
> --- a/arch/arm/include/asm/memory.h
> +++ b/arch/arm/include/asm/memory.h
> @@ -173,6 +173,37 @@
>   */
>  #define PHYS_PFN_OFFSET	(PHYS_OFFSET >> PAGE_SHIFT)
>  
> +#ifdef CONFIG_PATCH_PHYS_VIRT
> +
> +#define PATCH_TYPE_PHYS_TO_VIRT		(0)
> +#define PATCH_TYPE_VIRT_TO_PHYS		(1)
> +
> +#define __patch_stub(from,to,type)			\
> +	__asm__ __volatile__(				\
> +	"1:	add	%0, %1, %2\n"			\
> +	"\n"						\
> +	"	.pushsection __patch_table,\"a\"\n"	\
> +	"	.long	1b\n"				\
> +	"	.popsection\n"				\
> +	: "=r" (to)					\
> +	: "r" (from), "i" (type))

This should be "I" not "i":

    `I'
          Integer that is valid as an immediate operand in a data
          processing instruction.  That is, an integer in the range 0
          to 255 rotated by a multiple of 2

which is what 'add' takes.  "i" means any integer of any size.

> +/* patch_phys_virt - patch the stub instructions with the delta between
> + * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
> + * can be expressed by an immediate shifter operand. The stub instruction
> + * has a form of 'add rn, rd, #imm', where the lowest 8-bit of #imm is

'add rd, rn, #imm'

> + * used to identify the type of patching.
> + */
> +static void __init patch_phys_virt(void)
> +{
> +	extern unsigned int *__patch_table_begin, *__patch_table_end;
> +	unsigned int **p;
> +	unsigned int imm, instr[2];
> +
> +	if (PHYS_OFFSET & 0x00ffffff)
> +		panic("Physical memory start is not 16MiB aligned\n");
> +
> +	if (likely(PHYS_OFFSET < PAGE_OFFSET)) {
> +		imm = 0x400 | ((PAGE_OFFSET >> 24) - (PHYS_OFFSET >> 24));
> +		instr[0] = PATCH_INSTR_ADD | imm;
> +		instr[1] = PATCH_INSTR_SUB | imm;
> +	} else {
> +		imm = 0x400 | ((PHYS_OFFSET >> 24) - (PAGE_OFFSET >> 24));
> +		instr[0] = PATCH_INSTR_SUB | imm;
> +		instr[1] = PATCH_INSTR_ADD | imm;
> +	}
> +
> +	for (p = &__patch_table_begin; p < &__patch_table_end; p++) {
> +		unsigned int *inptr = *p;
> +
> +		if ((*inptr & PATCH_STUB_MASK) == PATCH_STUB_PHYS_TO_VIRT)
> +			*inptr = (*inptr & ~0x00e00fff) | instr[0];
> +		if ((*inptr & PATCH_STUB_MASK) == PATCH_STUB_VIRT_TO_PHYS)
> +			*inptr = (*inptr & ~0x00e00fff) | instr[1];
> +	}
> +	flush_cache_all();

That's not a good idea before the page tables are setup - there is CPU
support which needs to read data in order to writeback dirty entries in
the cache.  (eg, StrongARM CPUs - which corresponds with ebsa110,
footbridge, rpc, sa1100, and shark.)

This mapping does not exist before paging_init() has completed - which
presents a catch-22 situation here.  This also needs to be documented
against the config option.


From u.kleine-koenig at pengutronix.de  Sat Jun 26 06:51:33 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Sat, 26 Jun 2010 12:51:33 +0200
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <alpine.LFD.2.00.1006251941190.24097@xanadu.home>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>
	<20100625200659.GB22090@n2100.arm.linux.org.uk>
	<AANLkTikYE6Kg8C_ZClx9aKLvOa9CQRUT587hQnB91sua@mail.gmail.com>
	<20100625202002.GC22090@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006251941190.24097@xanadu.home>
Message-ID: <20100626105133.GA762@pengutronix.de>

Hello,

On Fri, Jun 25, 2010 at 07:46:05PM -0400, Nicolas Pitre wrote:
> On Fri, 25 Jun 2010, Russell King - ARM Linux wrote:
> 
> > Does anyone know where we are on the defconfig problem?  From what I
> > can see, it's mostly stalled for the time being, which is not good
> > news for us.
> 
> What looked to be promizing is the work by Uwe Kleine-K?nig according to 
> the preview he posted on June 10:
>   
> Message-id: <20100610063234.GA22533 at pengutronix.de>
I think Linus is still away?!  I plan to ping him again asking for an
opinion regarding my idea when he will be back.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From linux at arm.linux.org.uk  Sat Jun 26 07:07:45 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 26 Jun 2010 12:07:45 +0100
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <20100626105133.GA762@pengutronix.de>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>
	<20100625200659.GB22090@n2100.arm.linux.org.uk>
	<AANLkTikYE6Kg8C_ZClx9aKLvOa9CQRUT587hQnB91sua@mail.gmail.com>
	<20100625202002.GC22090@n2100.arm.linux.org.uk>
	<alpine.LFD.2.00.1006251941190.24097@xanadu.home>
	<20100626105133.GA762@pengutronix.de>
Message-ID: <20100626110745.GB10340@n2100.arm.linux.org.uk>

On Sat, Jun 26, 2010 at 12:51:33PM +0200, Uwe Kleine-K?nig wrote:
> Hello,
> 
> On Fri, Jun 25, 2010 at 07:46:05PM -0400, Nicolas Pitre wrote:
> > On Fri, 25 Jun 2010, Russell King - ARM Linux wrote:
> > 
> > > Does anyone know where we are on the defconfig problem?  From what I
> > > can see, it's mostly stalled for the time being, which is not good
> > > news for us.
> > 
> > What looked to be promizing is the work by Uwe Kleine-K?nig according to 
> > the preview he posted on June 10:
> >   
> > Message-id: <20100610063234.GA22533 at pengutronix.de>
> I think Linus is still away?!  I plan to ping him again asking for an
> opinion regarding my idea when he will be back.

It looks that way...


From linus.ml.walleij at gmail.com  Sat Jun 26 13:37:20 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Sat, 26 Jun 2010 19:37:20 +0200
Subject: [PATCH] MMC: remove regulator refcount fiddling in mmc core
In-Reply-To: <20100625112232.GA21217@opensource.wolfsonmicro.com>
References: <1277392337-27627-1-git-send-email-linus.walleij@stericsson.com>
	<20100625112232.GA21217@opensource.wolfsonmicro.com>
Message-ID: <AANLkTikiPByvzfbj-gwfyozWb5MMJXSWuINFbrLdcwtU@mail.gmail.com>

2010/6/25 Mark Brown <broonie at opensource.wolfsonmicro.com>:
> On Thu, Jun 24, 2010 at 05:12:17PM +0200, Linus Walleij wrote:
>
>> Currently the mmc_regulator_set_ocr() fiddles with the regulator
>> refcount by selectively calling regulator_[enable|disable]
>> depending on the state of the regulator. This will confuse the
>> reference count if case the regulator is for example shared with
>> other MMC slots or user for other stuff than the MMC card.
>
>> Push regulator_[enable|disable] out into the MMC host drivers
>> and remove this from the MMC core so the reference count can be
>> trusted.
>
> So, the feedback from folks at the time this was originally written was
> that the MMC code was unable to cope with sharing regulators since it
> really needs to be able to set specific voltages. ?This needn't be a
> showstopper since people can force a single voltage in the constraints
> but it does need to be considered here.

Well hm, that's not strictly true. If you only provide one standard
voltage ONLY in your OCR mask, i.e. MMC_VDD_* then you can use
the same regulator for two or more MMC cards.

Further that's a perfectly reasonable thing to do if you have e.g.
two embedded eMMC cards and you know which voltage they like
to operate on ... so share the same regulator, why not. The above
assumption comes from a slot-based world.

Another argument is that a function named
mmc_regulator_set_ocr() shouldn't be enabling/disabling regulators
anyway because it's hopeless to read the code, and the other
functions in mmc/core.c only deals with voltages, not on/off:ing.
(Maybe it's just me who have a hard time reading code like that.)

Yours,
Linus Walleij


From nico at fluxnic.net  Sat Jun 26 14:22:03 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Sat, 26 Jun 2010 14:22:03 -0400 (EDT)
Subject: [PATCH] [ARM] Introduce patching of phys_to_virt and vice versa
In-Reply-To: <20100626095420.GA10340@n2100.arm.linux.org.uk>
References: <1277542025-19881-1-git-send-email-eric.miao@canonical.com>
	<20100626095420.GA10340@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.00.1006261408530.24097@xanadu.home>

On Sat, 26 Jun 2010, Russell King - ARM Linux wrote:

> It needs to be documented that PATCH_PHYS_VIRT is only for non-XIP and
> non-Thumb2 kernels.  I suggest it goes in the help text for the config
> option, or a comment before the option.

The idea is to do the same for Thumb2 as well.

Obviously this is incompatible with XIP so should be documented as such.  
And I think we should try to make this option non user selectable if 
possible, but rather make it depend on the variable phys offset and 
linear memory layout options.


Nicolas


From linux at arm.linux.org.uk  Sat Jun 26 15:33:10 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Sat, 26 Jun 2010 20:33:10 +0100
Subject: [PATCH v4] libata: pata_samsung_cf: Add Samsung PATA
	controller driver
In-Reply-To: <001f01cb1417$dce8f8d0$96baea70$%kim@samsung.com>
References: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
	<4C22704B.50103@pobox.com>
	<001f01cb1417$dce8f8d0$96baea70$%kim@samsung.com>
Message-ID: <20100626193310.GA19339@n2100.arm.linux.org.uk>

On Fri, Jun 25, 2010 at 12:38:19PM +0900, Kukjin Kim wrote:
> Russell,
> 
> How do you think?
> May I send this to your patch tracking system?
> Or...how should I handle this?

If Jeff is happy, then I'm happy.  However, shouldn't it also have Ben's
ack?


From broonie at opensource.wolfsonmicro.com  Sat Jun 26 16:37:52 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Sat, 26 Jun 2010 21:37:52 +0100
Subject: [PATCH] MMC: remove regulator refcount fiddling in mmc core
In-Reply-To: <AANLkTikiPByvzfbj-gwfyozWb5MMJXSWuINFbrLdcwtU@mail.gmail.com>
	(sfid-20100626_183725_929817_AB417141)
References: <1277392337-27627-1-git-send-email-linus.walleij@stericsson.com>
	<20100625112232.GA21217@opensource.wolfsonmicro.com>
	<AANLkTikiPByvzfbj-gwfyozWb5MMJXSWuINFbrLdcwtU@mail.gmail.com>
	(sfid-20100626_183725_929817_AB417141)
Message-ID: <DDE00276-5AB7-4A7E-AA93-29755DE8E874@opensource.wolfsonmicro.com>

On 26 Jun 2010, at 18:37, Linus Walleij wrote:
> 2010/6/25 Mark Brown <broonie at opensource.wolfsonmicro.com>:
>> 

>> So, the feedback from folks at the time this was originally written was
>> that the MMC code was unable to cope with sharing regulators since it
>> really needs to be able to set specific voltages.  This needn't be a
>> showstopper since people can force a single voltage in the constraints
>> but it does need to be considered here.

> Well hm, that's not strictly true. If you only provide one standard
> voltage ONLY in your OCR mask, i.e. MMC_VDD_* then you can use
> the same regulator for two or more MMC cards.

This is what I'm saying about forcing a voltage in the constraints - the
existing code should i believe implement the above automatically.

> Further that's a perfectly reasonable thing to do if you have e.g.
> two embedded eMMC cards and you know which voltage they like
> to operate on ... so share the same regulator, why not. The above
> assumption comes from a slot-based world.

Right, but this code supports all MMC cards. To repeat what I said
above this does need to be considered here. I don't think it's a
particular problem, probably just turning it into a consumer capable
of sharing the regulator would be enough.

> Another argument is that a function named
> mmc_regulator_set_ocr() shouldn't be enabling/disabling regulators
> anyway because it's hopeless to read the code, and the other
> functions in mmc/core.c only deals with voltages, not on/off:ing.
> (Maybe it's just me who have a hard time reading code like that.)

This seems rather surprising - are you saying that no other MMC drivers
are able to manage power to the slot? There was a strong insistence
when this code was originally written that it was essential to be able to
power up and down the regulators for MMC applications.


From davem at davemloft.net  Sun Jun 27 00:07:28 2010
From: davem at davemloft.net (David Miller)
Date: Sat, 26 Jun 2010 21:07:28 -0700 (PDT)
Subject: [RFC 9/9] crypto: Add Samsung crypto engine driver
In-Reply-To: <4C129341.2060407@gmail.com>
References: <cover.1276284559.git.mcuelenaere@gmail.com>
	<4C129341.2060407@gmail.com>
Message-ID: <20100626.210728.90806559.davem@davemloft.net>

From: Maurus Cuelenaere <mcuelenaere at gmail.com>
Date: Fri, 11 Jun 2010 21:49:21 +0200

> This patch adds support for the Samsung crypto engine driver available in the
> S3C64XX and S5PC100 SoCs. Currently this supports AES and (T)DES with ECB and
> CBC block ciphers (also CTR for AES). Support for (HMAC)-SHA1 acceleration is
> also available in this engine, but isn't used in the driver yet.
> 
> Support for DMA has been added in the code but is currently disabled due to
> issues with data transfers.
> 
> Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>

I would personally queue up new crypto requests directly when there are
no queued up requests and ->cur_req is NULL, instead of doing all of
that work to do the submission in the tasklet.  I would also do the
completion and queue running directly in the hw IRQ handler.

The tasklet is just pure overhead.

Basically, when doing async crypto, every cycle that is consumed just
to implement crypto job submission and completion takes away from the
gains you get by doing it in hw at all.

You can see this clearly if you do performance comparisons between the
synchronous crypto routines and your async ones done in HW.


From davem at davemloft.net  Sun Jun 27 00:22:54 2010
From: davem at davemloft.net (David Miller)
Date: Sat, 26 Jun 2010 21:22:54 -0700 (PDT)
Subject: [PATCH 1/2 v2] mv643xx_eth: use sw csum for big packets
In-Reply-To: <20100620115859.GT14513@mail.wantstofly.org>
References: <20100614093237.GG14513@mail.wantstofly.org>
	<AANLkTik1QFcRKy95sLTr6MlPfhEyR84iTCcAzpuSg47D@mail.gmail.com>
	<20100620115859.GT14513@mail.wantstofly.org>
Message-ID: <20100626.212254.25140964.davem@davemloft.net>

From: Lennert Buytenhek <buytenh at wantstofly.org>
Date: Sun, 20 Jun 2010 13:58:59 +0200

> Acked-by: Lennert Buytenhek <buytenh at wantstofly.org>

If the desire is to get this into one of the networking GIT
trees, sending it to linux-net isn't going to accomplish that.

It needs to go to netdev at vger.kernel.org with all signoffs
and ACKs.

Thanks.


From grant.likely at secretlab.ca  Sun Jun 27 02:08:02 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Sun, 27 Jun 2010 00:08:02 -0600
Subject: [PATCH] spi/omap2_mcspi: disable and enable chan between each SPI
	transfer
In-Reply-To: <4C249BA1.8010808@gmail.com>
References: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com> 
	<E1C7579D1379824DAE67858071C810382DD83846FB@NOK-EUMSG-02.mgdnok.nokia.com>
	<4C249BA1.8010808@gmail.com>
Message-ID: <AANLkTinO3kndb9bIAGlz4-h2TW64NGthHBRcVlE3gqun@mail.gmail.com>

On Fri, Jun 25, 2010 at 6:05 AM, jason <jason77.wang at gmail.com> wrote:
> roman.tereshonkov at nokia.com wrote:
>>
>>
>>
>
> [snip]
>>>
>>> -----Original Message-----
>>>
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?}
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?c = 0;
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? } else if (c == 0 && tx == NULL) {
>>> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? omap2_mcspi_set_enable(spi, 0);
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?}
>>>
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?*rx++ = __raw_readl(rx_reg);
>>>
>>
>> Why do you do this?
>> Reading the last word from the shift register buffer leads to the
>> receiving new data to the buffer.
>> The channel needs to be disabled before the last word reading.
>>
>>
>>
>
> Yes, you are right. If this patch can be accepted, i will remove those
> changes in the V2 patch.
> Please see my email replying grant likely's questions.

Hi Jason.

I'm assuming I can ignore this patch and wait for your V2.  I'll still
want an ack from other omap spi users before I apply it though.

g.

>
> Thanks,
> Jason.
>>
>>
>>>
>>> @@ -646,7 +641,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
>>> spi_transfer *xfer)
>>> ? ? ? ? ? ? ? ? ? ? ? ?dev_err(&spi->dev, "EOT timed out\n");
>>> ? ? ? ?}
>>> out:
>>> - ? ? ? omap2_mcspi_set_enable(spi, 1);
>>> + ? ? ? omap2_mcspi_set_enable(spi, 0);
>>> ? ? ? ?return count - c;
>>> }
>>>
>>> @@ -894,7 +889,6 @@ static void omap2_mcspi_work(struct work_struct
>>> *work)
>>> ? ? ? ? ? ? ? ?cs = spi->controller_state;
>>> ? ? ? ? ? ? ? ?cd = spi->controller_data;
>>>
>>> - ? ? ? ? ? ? ? omap2_mcspi_set_enable(spi, 1);
>>> ? ? ? ? ? ? ? ?list_for_each_entry(t, &m->transfers, transfer_list) {
>>> ? ? ? ? ? ? ? ? ? ? ? ?if (t->tx_buf == NULL && t->rx_buf == NULL &&
>>> t->len) {
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?status = -EINVAL;
>>> @@ -931,6 +925,8 @@ static void omap2_mcspi_work(struct work_struct
>>> *work)
>>>
>>> ? ? ? ? ? ? ? ? ? ? ? ?mcspi_write_chconf0(spi, chconf);
>>>
>>> + ? ? ? ? ? ? ? ? ? ? ? omap2_mcspi_set_enable(spi, 1);
>>> +
>>> ? ? ? ? ? ? ? ? ? ? ? ?if (t->len) {
>>> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned ? ? ? ?count;
>>>
>>> --
>>> 1.5.6.5
>>>
>>>
>>>
>
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From grinberg at compulab.co.il  Sun Jun 27 03:42:01 2010
From: grinberg at compulab.co.il (Igor Grinberg)
Date: Sun, 27 Jun 2010 10:42:01 +0300
Subject: [PATCH v2] otg/ulpi.c : fix register write
In-Reply-To: <4C236D9A.4030707@eukrea.com>
References: <1277311435-12027-1-git-send-email-eric@eukrea.com>
	<4C236600.2030605@compulab.co.il> <4C236D9A.4030707@eukrea.com>
Message-ID: <4C2700C9.2090602@compulab.co.il>


On 06/24/10 17:37, Eric B?nard wrote:
> Le 24/06/2010 16:04, Igor Grinberg a ?crit :
>> ulpi_set_flags is used to set the OTG flags and not to clear them,
>> also it is a static function and is not a part of struct
>> otg_transceiver,
>> so it cannot be called from outside the ulpi.c, thus after the
>> ulpi_create,
>> it is never called.
>> I think, currently, this should stay as it is.
>>
> OK, the problem that when one flag is set, you can't clear it without
> resetting the PHY.

This is correct, but current ulpi driver is not designed for writing
multiple times
into the ULPI_OTG_CTRL register, only once when ulpi_init function is
called.
Do you call the ulpi_init function for a couple of times? Looks like a hack.

>
> Eric
>

-- 
Regards,
Igor.



From mcuelenaere at gmail.com  Sun Jun 27 07:06:03 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Sun, 27 Jun 2010 13:06:03 +0200
Subject: [RFC 9/9] crypto: Add Samsung crypto engine driver
In-Reply-To: <20100626.210728.90806559.davem@davemloft.net>
References: <cover.1276284559.git.mcuelenaere@gmail.com>	<4C129341.2060407@gmail.com>
	<20100626.210728.90806559.davem@davemloft.net>
Message-ID: <4C27309B.7010905@gmail.com>

 Op 27-06-10 06:07, David Miller schreef:
> From: Maurus Cuelenaere <mcuelenaere at gmail.com>
> Date: Fri, 11 Jun 2010 21:49:21 +0200
>
>> This patch adds support for the Samsung crypto engine driver available in the
>> S3C64XX and S5PC100 SoCs. Currently this supports AES and (T)DES with ECB and
>> CBC block ciphers (also CTR for AES). Support for (HMAC)-SHA1 acceleration is
>> also available in this engine, but isn't used in the driver yet.
>>
>> Support for DMA has been added in the code but is currently disabled due to
>> issues with data transfers.
>>
>> Signed-off-by: Maurus Cuelenaere <mcuelenaere at gmail.com>
> I would personally queue up new crypto requests directly when there are
> no queued up requests and ->cur_req is NULL, instead of doing all of
> that work to do the submission in the tasklet.  I would also do the
> completion and queue running directly in the hw IRQ handler.
>
> The tasklet is just pure overhead.
>
> Basically, when doing async crypto, every cycle that is consumed just
> to implement crypto job submission and completion takes away from the
> gains you get by doing it in hw at all.
>
> You can see this clearly if you do performance comparisons between the
> synchronous crypto routines and your async ones done in HW.

I'll rewrite it like you're suggesting.
I'd go with a threaded interrupt handler in that case then, or do you also consider this as too much overhead?

I'll do some performance comparisons of threaded interrupt handler vs normal and go with the fastest.

Thanks for the review!

--
Maurus Cuelenaere


From jason77.wang at gmail.com  Sun Jun 27 09:12:50 2010
From: jason77.wang at gmail.com (jason)
Date: Sun, 27 Jun 2010 21:12:50 +0800
Subject: [PATCH] spi/omap2_mcspi: disable and enable chan between each
	SPI 	transfer
In-Reply-To: <AANLkTinO3kndb9bIAGlz4-h2TW64NGthHBRcVlE3gqun@mail.gmail.com>
References: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com>
	<E1C7579D1379824DAE67858071C810382DD83846FB@NOK-EUMSG-02.mgdnok.nokia.com>
	<4C249BA1.8010808@gmail.com>
	<AANLkTinO3kndb9bIAGlz4-h2TW64NGthHBRcVlE3gqun@mail.gmail.com>
Message-ID: <4C274E52.1080003@gmail.com>

Grant Likely wrote:
> On Fri, Jun 25, 2010 at 6:05 AM, jason <jason77.wang at gmail.com> wrote:
>   
>> roman.tereshonkov at nokia.com wrote:
>>     
>>>
>>>       
>> [snip]
>>     
>>>> -----Original Message-----
>>>>
>>>>                                        }
>>>>                                        c = 0;
>>>> -                               } else if (c == 0 && tx == NULL) {
>>>> -                                       omap2_mcspi_set_enable(spi, 0);
>>>>                                }
>>>>
>>>>                                *rx++ = __raw_readl(rx_reg);
>>>>
>>>>         
>>> Why do you do this?
>>> Reading the last word from the shift register buffer leads to the
>>> receiving new data to the buffer.
>>> The channel needs to be disabled before the last word reading.
>>>
>>>
>>>
>>>       
>> Yes, you are right. If this patch can be accepted, i will remove those
>> changes in the V2 patch.
>> Please see my email replying grant likely's questions.
>>     
>
> Hi Jason.
>
> I'm assuming I can ignore this patch and wait for your V2.  I'll still
> want an ack from other omap spi users before I apply it though.
>
> g.
>
>   
Hi grant,
OK, i will prepare V2 and send out for review.

Hi roman,
I don't know if there is a TI omap3530evm board at your hand, if yes, 
you can
test touchscreen driver(ads7846) via tslib(ts_calibrate, ts_test).

Thanks,
Jason.
>> Thanks,
>> Jason.
>>     
>>>       
>>>> @@ -646,7 +641,7 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct
>>>> spi_transfer *xfer)
>>>>                        dev_err(&spi->dev, "EOT timed out\n");
>>>>        }
>>>> out:
>>>> -       omap2_mcspi_set_enable(spi, 1);
>>>> +       omap2_mcspi_set_enable(spi, 0);
>>>>        return count - c;
>>>> }
>>>>
>>>> @@ -894,7 +889,6 @@ static void omap2_mcspi_work(struct work_struct
>>>> *work)
>>>>                cs = spi->controller_state;
>>>>                cd = spi->controller_data;
>>>>
>>>> -               omap2_mcspi_set_enable(spi, 1);
>>>>                list_for_each_entry(t, &m->transfers, transfer_list) {
>>>>                        if (t->tx_buf == NULL && t->rx_buf == NULL &&
>>>> t->len) {
>>>>                                status = -EINVAL;
>>>> @@ -931,6 +925,8 @@ static void omap2_mcspi_work(struct work_struct
>>>> *work)
>>>>
>>>>                        mcspi_write_chconf0(spi, chconf);
>>>>
>>>> +                       omap2_mcspi_set_enable(spi, 1);
>>>> +
>>>>                        if (t->len) {
>>>>                                unsigned        count;
>>>>
>>>> --
>>>> 1.5.6.5
>>>>
>>>>
>>>>
>>>>         
>>     
>
>
>
>   



From eric at eukrea.com  Sun Jun 27 10:00:31 2010
From: eric at eukrea.com (=?UTF-8?B?RXJpYyBCw6luYXJk?=)
Date: Sun, 27 Jun 2010 16:00:31 +0200
Subject: [PATCH v2] otg/ulpi.c : fix register write
In-Reply-To: <4C2700C9.2090602@compulab.co.il>
References: <1277311435-12027-1-git-send-email-eric@eukrea.com>
	<4C236600.2030605@compulab.co.il> <4C236D9A.4030707@eukrea.com>
	<4C2700C9.2090602@compulab.co.il>
Message-ID: <4C27597F.3010902@eukrea.com>

Le 27/06/2010 09:42, Igor Grinberg a ?crit :
>
> On 06/24/10 17:37, Eric B?nard wrote:
>> Le 24/06/2010 16:04, Igor Grinberg a ?crit :
>>> ulpi_set_flags is used to set the OTG flags and not to clear them,
>>> also it is a static function and is not a part of struct
>>> otg_transceiver,
>>> so it cannot be called from outside the ulpi.c, thus after the
>>> ulpi_create,
>>> it is never called.
>>> I think, currently, this should stay as it is.
>>>
>> OK, the problem that when one flag is set, you can't clear it without
>> resetting the PHY.
>
> This is correct, but current ulpi driver is not designed for writing
> multiple times
> into the ULPI_OTG_CTRL register, only once when ulpi_init function is
> called.
> Do you call the ulpi_init function for a couple of times? Looks like a hack.
>
no hack, as I was fixing the other function, I though this one could 
also be fixed :)
I'll send a patch with only the other fix.

Eric


From freddy2_es at yahoo.com  Sun Jun 27 14:25:34 2010
From: freddy2_es at yahoo.com (=?iso-8859-1?Q?Alfredo_Quesada_S=E1nchez?=)
Date: Sun, 27 Jun 2010 11:25:34 -0700 (PDT)
Subject: Using SPI in a kernel module
Message-ID: <419523.332.qm@web33805.mail.mud.yahoo.com>

After reading many things about SPI in linux (including the kernel Documentation, that is, spi_summary.txt) and having read many source files in the kernel itself I'm not sure which is the right way to deal with SPI from a kernel module if you don't want to use the spidev (neither the spi-gpio) implementation.

My goal is to create an spidev-like module, which generates a /dev entry (that is the easy part) and hides the details of the device, such as an EEPROM. The way to communicate with userspace using /dev files is simple, but the access to spi.h features isn't that much.

According to some board specific code there is one spi device registered in the system (it's wired to a serial dataflash in my development board), but I don't know how I can get a reference to the spi_device that should give me access to it.

By looking to other existing drivers I should register my own spi_driver, mostly providing probe and remove functions. And the questions are:
- When should I receive a probe call?
- What if I have more than 1 spi device on my system (let's say.. 3)? Will I receive 3 calls to probe?
- Is this the only way to get valid references to spi_device's? Is there any other way to access to the "list" of available spi_device's?

I did a small test with a fake module, which registers a spi_driver, but I did not receive any probe call, that's why this might not be the right way to access to the spi_device.
Besides in other low level code I can see calls to 

Regards



      


From mishal at softerra.com  Sun Jun 27 16:09:55 2010
From: mishal at softerra.com (Mykhail Lodygin)
Date: Sun, 27 Jun 2010 23:09:55 +0300
Subject: Using SPI in a kernel module
In-Reply-To: <419523.332.qm@web33805.mail.mud.yahoo.com>
References: <419523.332.qm@web33805.mail.mud.yahoo.com>
Message-ID: <4C27B013.4010400@softerra.com>

Hello
How about specifying correct data (for your particular board) in the 
machine-specific code?(arch/your_arch/mach-your_machine/your_machine.c)
Basically it is enough for the system to invoke proper probes.
Mikhail
On 06/27/2010 09:25 PM, Alfredo Quesada S?nchez wrote:
> After reading many things about SPI in linux (including the kernel Documentation, that is, spi_summary.txt) and having read many source files in the kernel itself I'm not sure which is the right way to deal with SPI from a kernel module if you don't want to use the spidev (neither the spi-gpio) implementation.
>
> My goal is to create an spidev-like module, which generates a /dev entry (that is the easy part) and hides the details of the device, such as an EEPROM. The way to communicate with userspace using /dev files is simple, but the access to spi.h features isn't that much.
>
> According to some board specific code there is one spi device registered in the system (it's wired to a serial dataflash in my development board), but I don't know how I can get a reference to the spi_device that should give me access to it.
>
> By looking to other existing drivers I should register my own spi_driver, mostly providing probe and remove functions. And the questions are:
> - When should I receive a probe call?
> - What if I have more than 1 spi device on my system (let's say.. 3)? Will I receive 3 calls to probe?
> - Is this the only way to get valid references to spi_device's? Is there any other way to access to the "list" of available spi_device's?
>
> I did a small test with a fake module, which registers a spi_driver, but I did not receive any probe call, that's why this might not be the right way to access to the spi_device.
> Besides in other low level code I can see calls to
>
> Regards
>
>
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>    



From freddy2_es at yahoo.com  Sun Jun 27 16:55:51 2010
From: freddy2_es at yahoo.com (=?iso-8859-1?Q?Alfredo_Quesada_S=E1nchez?=)
Date: Sun, 27 Jun 2010 13:55:51 -0700 (PDT)
Subject: Using SPI in a kernel module
In-Reply-To: <4C27B013.4010400@softerra.com>
Message-ID: <189502.64100.qm@web33802.mail.mud.yahoo.com>

There are a few compiled files in that directory (more preciselly is arch/arm/mach-at91), including:

- board-XXX.c (well, the name of the board)

MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES")
	/* Maintainer: Atmel */
	.phys_io	= AT91_BASE_SYS,
	.io_pg_offst	= (AT91_VA_BASE_SYS >> 18) & 0xfffc,
	.boot_params	= AT91_SDRAM_BASE + 0x100,
	.timer		= &at91sam926x_timer,
	.map_io		= ek_map_io,
	.init_irq	= ek_init_irq,
	.init_machine	= ek_board_init,
MACHINE_END

In this file there is:

/*
 * SPI devices.
 */
static struct spi_board_info ek_spi_devices[] = {
	{	/* DataFlash chip */
		.modalias	= "mtd_dataflash",
		.chip_select	= 0,
		.max_speed_hz	= 15 * 1000 * 1000,
		.bus_num	= 0,
	},
};

And in ek_board_init I can see a call to:

/* SPI */
at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));


This function is in at91sam9g45_devices.c (also compiled), also having:

static struct resource spi0_resources[] = {
	[0] = {
		.start	= AT91SAM9G45_BASE_SPI0,
		.end	= AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= AT91SAM9G45_ID_SPI0,
		.end	= AT91SAM9G45_ID_SPI0,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device at91sam9g45_spi0_device = {
	.name		= "atmel_spi",
	.id		= 0,
	.dev		= {
				.dma_mask		= &spi_dmamask,
				.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= spi0_resources,
	.num_resources	= ARRAY_SIZE(spi0_resources),
};

static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };

static struct resource spi1_resources[] = {
	[0] = {
		.start	= AT91SAM9G45_BASE_SPI1,
		.end	= AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		.start	= AT91SAM9G45_ID_SPI1,
		.end	= AT91SAM9G45_ID_SPI1,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device at91sam9g45_spi1_device = {
	.name		= "atmel_spi",
	.id		= 1,
	.dev		= {
				.dma_mask		= &spi_dmamask,
				.coherent_dma_mask	= DMA_BIT_MASK(32),
	},
	.resource	= spi1_resources,
	.num_resources	= ARRAY_SIZE(spi1_resources),
};

static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };

void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
{
	int i;
	unsigned long cs_pin;
	short enable_spi0 = 0;
	short enable_spi1 = 0;

	/* Choose SPI chip-selects */
	for (i = 0; i < nr_devices; i++) {
		if (devices[i].controller_data)
			cs_pin = (unsigned long) devices[i].controller_data;
		else if (devices[i].bus_num == 0)
			cs_pin = spi0_standard_cs[devices[i].chip_select];
		else
			cs_pin = spi1_standard_cs[devices[i].chip_select];

		if (devices[i].bus_num == 0)
			enable_spi0 = 1;
		else
			enable_spi1 = 1;

		/* enable chip-select pin */
		at91_set_gpio_output(cs_pin, 1);

		/* pass chip-select pin to driver */
		devices[i].controller_data = (void *) cs_pin;
	}

	spi_register_board_info(devices, nr_devices);

	/* Configure SPI bus(es) */
	if (enable_spi0) {
		at91_set_A_periph(AT91_PIN_PB0, 0);	/* SPI0_MISO */
		at91_set_A_periph(AT91_PIN_PB1, 0);	/* SPI0_MOSI */
		at91_set_A_periph(AT91_PIN_PB2, 0);	/* SPI0_SPCK */

		at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
		platform_device_register(&at91sam9g45_spi0_device);
	}
	if (enable_spi1) {
		at91_set_A_periph(AT91_PIN_PB14, 0);	/* SPI1_MISO */
		at91_set_A_periph(AT91_PIN_PB15, 0);	/* SPI1_MOSI */
		at91_set_A_periph(AT91_PIN_PB16, 0);	/* SPI1_SPCK */

		at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
		platform_device_register(&at91sam9g45_spi1_device);
	}
}

To summarize, in the end platform_device_register should be called for SPI 0 (as you can see the board has 2 SPI channels).


So.. assuming this is working as expected, when should i see a call to my driver's probe function? and.. which spi_device will be passed as parameter? (there is only 1 registered, but for this question let's assume that i have more spi devices registered).

Regards

> Hello
> How about specifying correct data (for your particular
> board) in the 
> machine-specific
> code?(arch/your_arch/mach-your_machine/your_machine.c)
> Basically it is enough for the system to invoke proper
> probes.
> Mikhail



      


From paul at pwsan.com  Sun Jun 27 20:47:45 2010
From: paul at pwsan.com (Paul Walmsley)
Date: Sun, 27 Jun 2010 18:47:45 -0600 (MDT)
Subject: [GIT PULL] OMAP: hwmod bug fix for 2.6.35-rc
Message-ID: <alpine.DEB.2.00.1006231828120.1550@utopia.booyaka.com>


Hi Tony,

this branch contains a single patch which fixes a bug in the hwmod code in 
2.6.35-rc.


- Paul


The following changes since commit 7e27d6e778cd87b6f2415515d7127eba53fe5d02:

  Linux 2.6.35-rc3 (2010-06-11 19:14:04 -0700)

are available in the git repository at:
  git://git.pwsan.com/linux-2.6 for_2.6.35rc

Benoit Cousson (1):
      OMAP: hwmod: Fix the missing braces

 arch/arm/mach-omap2/omap_hwmod.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)


From byang1 at marvell.com  Sun Jun 27 22:27:32 2010
From: byang1 at marvell.com (Bin Yang)
Date: Sun, 27 Jun 2010 19:27:32 -0700
Subject: kprobe bug.
In-Reply-To: <alpine.LFD.2.00.1006251630500.24097@xanadu.home>
Message-ID: <AAD1C6EB06EE3649B35B7E026785068D14FCBC756F@SC-VEXCH2.marvell.com>

Thanks. 
It looks "emulate_str" had considered PC register situation already. Only " emulate_ldr" has this problem. 

Here is my new patch, thanks in advance to review it. 

===============================
From 554a86a94836d5f6c89c1253f2c2d85773cbe5eb Mon Sep 17 00:00:00 2001
From: Bin Yang <bin.yang at marvell.com>
Date: Mon, 28 Jun 2010 10:40:56 +0800
Subject: [PATCH] ARM: fix kprobe ldr instr emulate bug

Signed-off-by: Bin Yang <bin.yang at marvell.com>
---
 arch/arm/kernel/kprobes-decode.c |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c
index 81b1737..80511d5 100644
--- a/arch/arm/kernel/kprobes-decode.c
+++ b/arch/arm/kernel/kprobes-decode.c
@@ -583,13 +583,14 @@ static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs)
 {
        insn_llret_3arg_fn_t *i_fn = (insn_llret_3arg_fn_t *)&p->ainsn.insn[0];
        kprobe_opcode_t insn = p->opcode;
+       long ppc = (long)p->addr + 8;
        union reg_pair fnr;
        int rd = (insn >> 12) & 0xf;
        int rn = (insn >> 16) & 0xf;
        int rm = insn & 0xf;
        long rdv;
-       long rnv  = regs->uregs[rn];
-       long rmv  = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */
+       long rnv = (rn == 15) ? ppc : regs->uregs[rn];
+       long rmv = (rm == 15) ? ppc : regs->uregs[rm];
        long cpsr = regs->ARM_cpsr;


Bin Yang

-----Original Message-----
From: Nicolas Pitre [mailto:nico at fluxnic.net] 
Sent: 2010?6?26? 4:50
To: Bin Yang
Cc: Russell King - ARM Linux; Eric Miao; Haojian Zhuang; linux-arm-kernel
Subject: Re: kprobe bug.

On Fri, 25 Jun 2010, Bin Yang wrote:

> Hi Russell,
> 
> 	Thanks in advance for your kind to review my question. 
> 	I met a kprobe bug while I used it to debug my driver. 
> 	Here is the scenario:
> 	I add a probe at function xxx(). And the assembly code of xxx() is as following,
> =====================
> 	c035ee48 <xxx >:
> c035ee48:       e59f3008        ldr     r3, [pc, #8]    ; c035ee58              <xxx+0x10>
> c035ee4c:       e3a02001        mov     r2, #1  ; 0x1
> c035ee50:       e5032fff        str     r2, [r3, #-4095]
> c035ee54:       e12fff1e        bx      lr
> c035ee58:       fe03dfff        .word   0xfe03dfff 
> =====================
> 	The ldr emulate always load e12fff1e to r3 register. 
> 	After debugging, I found the pc register should be 8 after current instruction. So we should set pc to pc+8 before instruction emulation and set it back to the next instruction after singe step.
> 	Here is my patch: 
> =======================
> diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c
> index 60c62c3..6e2567e 100644
> --- a/arch/arm/kernel/kprobes.c
> +++ b/arch/arm/kernel/kprobes.c
> @@ -132,8 +132,9 @@ static void __kprobes set_current_kprobe(struct kprobe *p)
>  static void __kprobes singlestep(struct kprobe *p, struct pt_regs *regs,
>  				 struct kprobe_ctlblk *kcb)
>  {
> -	regs->ARM_pc += 4;
> +	regs->ARM_pc += 8;
>  	p->ainsn.insn_handler(p, regs);
> +	regs->ARM_pc -= 4;
>  }
>  
>  /*
> ========================

This is wrong.  You are breaking all the emulated instructions changing 
the pc value.

What needs to be done is to add a special case in emulate_ldr() to fixup 
rnv when rn is 15.  The same fixup would be needed in emulate_str().
See emulate_alu_rflags() for example.


Nicolas

From ccross at android.com  Sun Jun 27 22:30:01 2010
From: ccross at android.com (Colin Cross)
Date: Sun, 27 Jun 2010 19:30:01 -0700
Subject: [PATCH V2] [ARM] Add ARCH_PROVIDES_UDELAY config option
In-Reply-To: <4C200E62.4090604@codeaurora.org>
References: <1272654736-28837-1-git-send-email-ccross@android.com>
	<u2pd73d4eaf1004301237k3ceb859dobe74fe53abec774d@mail.gmail.com>
	<87d3xgd20n.fsf@deeprootsystems.com>
	<20100501100148.GE12172@n2100.arm.linux.org.uk>
	<4BF702CC.5000401@codeaurora.org>
	<20100521220653.GL11042@n2100.arm.linux.org.uk>
	<4BFF112A.2060700@codeaurora.org> <4C200E62.4090604@codeaurora.org>
Message-ID: <AANLkTim_Ct2EKfvQ119KRvMkqUyNivgnchEBkK7W4P_-@mail.gmail.com>

I am using this patch in our Tegra development tree.  So far, I
haven't come across any need for supporting udelay before iomap, but
if it is necessary, it could be handled in the per-architecture
implementation by using a busy loop with a worst-case count if a
sched_clock initialization flag is not set.

On Mon, Jun 21, 2010 at 6:14 PM, Saravana Kannan <skannan at codeaurora.org> wrote:
> Russel,
>
> Would appreciate your thoughts on this.
>
> Colin,
>
> Are you continuing to use the approach used in your patch in your
> development tree? I just want to make sure we have a solution that everyone
> can agree to.
>
> Thanks,
> Saravana
>
> Saravana Kannan wrote:
>>
>> Russell King - ARM Linux wrote:
>>>
>>> My point is not specific to sched_clock, but to counters which on ARM
>>> are 99.9% always memory mapped, and therefore inaccessible during the
>>> very early kernel boot. ?sched_clock was merely an illustration of the
>>> problem.
>>
>> Do you know any code which uses udelay that early? I can't imagine any
>> non-driver code using udelay. If it's just drivers using udelay, then they
>> need IO mapping to have been completed for the device register access to
>> work and hence udelay won't have any problems.
>>
>> -Saravana
>>
>
>


From eric.y.miao at gmail.com  Sun Jun 27 23:42:08 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 28 Jun 2010 11:42:08 +0800
Subject: [PATCH 1/4] pxa/z2: Add regulator support
In-Reply-To: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTimk9zvCogCJh8bNvS5h_Ergfpz3JI0ERU87eiD4@mail.gmail.com>

On Thu, Jun 24, 2010 at 10:02 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Register TPS65021 regulator in Zipit Z2.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Applied.

> ---
> ?arch/arm/mach-pxa/z2.c | ? 71 ++++++++++++++++++++++++++++++++++++++++++++++++
> ?1 files changed, 71 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
> index 4cba5b6..1bafb23 100644
> --- a/arch/arm/mach-pxa/z2.c
> +++ b/arch/arm/mach-pxa/z2.c
> @@ -26,6 +26,7 @@
> ?#include <linux/gpio.h>
> ?#include <linux/gpio_keys.h>
> ?#include <linux/delay.h>
> +#include <linux/regulator/machine.h>
>
> ?#include <asm/mach-types.h>
> ?#include <asm/mach/arch.h>
> @@ -616,6 +617,75 @@ static inline void z2_spi_init(void) {}
> ?#endif
>
> ?/******************************************************************************
> + * Core power regulator
> + ******************************************************************************/
> +#if defined(CONFIG_REGULATOR_TPS65023) || \
> + ? ? ? defined(CONFIG_REGULATOR_TPS65023_MODULE)
> +static struct regulator_consumer_supply z2_tps65021_consumers[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .supply = "vcc_core",
> + ? ? ? }
> +};
> +
> +static struct regulator_init_data z2_tps65021_info[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .constraints = {
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "vcc_core range",
> + ? ? ? ? ? ? ? ? ? ? ? .min_uV ? ? ? ? = 800000,
> + ? ? ? ? ? ? ? ? ? ? ? .max_uV ? ? ? ? = 1600000,
> + ? ? ? ? ? ? ? ? ? ? ? .always_on ? ? ?= 1,
> + ? ? ? ? ? ? ? ? ? ? ? .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> + ? ? ? ? ? ? ? },
> + ? ? ? ? ? ? ? .consumer_supplies ? ? ?= z2_tps65021_consumers,
> + ? ? ? ? ? ? ? .num_consumer_supplies ?= ARRAY_SIZE(z2_tps65021_consumers),
> + ? ? ? }, {
> + ? ? ? ? ? ? ? .constraints = {
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "DCDC2",
> + ? ? ? ? ? ? ? ? ? ? ? .min_uV ? ? ? ? = 3300000,
> + ? ? ? ? ? ? ? ? ? ? ? .max_uV ? ? ? ? = 3300000,
> + ? ? ? ? ? ? ? ? ? ? ? .always_on ? ? ?= 1,
> + ? ? ? ? ? ? ? },
> + ? ? ? }, {
> + ? ? ? ? ? ? ? .constraints = {
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "DCDC3",
> + ? ? ? ? ? ? ? ? ? ? ? .min_uV ? ? ? ? = 1800000,
> + ? ? ? ? ? ? ? ? ? ? ? .max_uV ? ? ? ? = 1800000,
> + ? ? ? ? ? ? ? ? ? ? ? .always_on ? ? ?= 1,
> + ? ? ? ? ? ? ? },
> + ? ? ? }, {
> + ? ? ? ? ? ? ? .constraints = {
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "LDO1",
> + ? ? ? ? ? ? ? ? ? ? ? .min_uV ? ? ? ? = 1000000,
> + ? ? ? ? ? ? ? ? ? ? ? .max_uV ? ? ? ? = 3150000,
> + ? ? ? ? ? ? ? ? ? ? ? .always_on ? ? ?= 1,
> + ? ? ? ? ? ? ? },
> + ? ? ? }, {
> + ? ? ? ? ? ? ? .constraints = {
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "LDO2",
> + ? ? ? ? ? ? ? ? ? ? ? .min_uV ? ? ? ? = 1050000,
> + ? ? ? ? ? ? ? ? ? ? ? .max_uV ? ? ? ? = 3300000,
> + ? ? ? ? ? ? ? ? ? ? ? .always_on ? ? ?= 1,
> + ? ? ? ? ? ? ? },
> + ? ? ? }
> +};
> +
> +static struct i2c_board_info __initdata z2_pi2c_board_info[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? I2C_BOARD_INFO("tps65021", 0x48),
> + ? ? ? ? ? ? ? .platform_data ?= &z2_tps65021_info,
> + ? ? ? },
> +};
> +
> +static void __init z2_pmic_init(void)
> +{
> + ? ? ? pxa27x_set_i2c_power_info(NULL);
> + ? ? ? i2c_register_board_info(1, ARRAY_AND_SIZE(z2_pi2c_board_info));
> +}
> +#else
> +static inline void z2_pmic_init(void) {}
> +#endif
> +
> +/******************************************************************************
> ?* Machine init
> ?******************************************************************************/
> ?static void __init z2_init(void)
> @@ -635,6 +705,7 @@ static void __init z2_init(void)
> ? ? ? ?z2_pwm_init();
> ? ? ? ?z2_leds_init();
> ? ? ? ?z2_keys_init();
> + ? ? ? z2_pmic_init();
> ?}
>
> ?MACHINE_START(ZIPIT2, "Zipit Z2")
> --
> 1.7.1
>
>

From eric.y.miao at gmail.com  Sun Jun 27 23:42:28 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 28 Jun 2010 11:42:28 +0800
Subject: [PATCH 2/4] pxa/colibri320: Add UDC support
In-Reply-To: <1277388132-5549-2-git-send-email-marek.vasut@gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com> 
	<1277388132-5549-2-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTinfZB-hznbD60wF9tO_6hI5pG-3EjNZPXksjSVL@mail.gmail.com>

On Thu, Jun 24, 2010 at 10:02 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Add support for PXA UDC.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Applied.

> ---
> ?arch/arm/mach-pxa/colibri-pxa320.c | ? 40 ++++++++++++++++++++++++++++++++++++
> ?1 files changed, 40 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
> index ae835fa..99e850d 100644
> --- a/arch/arm/mach-pxa/colibri-pxa320.c
> +++ b/arch/arm/mach-pxa/colibri-pxa320.c
> @@ -16,6 +16,7 @@
> ?#include <linux/platform_device.h>
> ?#include <linux/gpio.h>
> ?#include <linux/interrupt.h>
> +#include <linux/usb/gpio_vbus.h>
>
> ?#include <asm/mach-types.h>
> ?#include <asm/sizes.h>
> @@ -28,6 +29,8 @@
> ?#include <mach/pxafb.h>
> ?#include <mach/ohci.h>
> ?#include <mach/audio.h>
> +#include <mach/pxa27x-udc.h>
> +#include <mach/udc.h>
>
> ?#include "generic.h"
> ?#include "devices.h"
> @@ -101,6 +104,42 @@ void __init colibri_pxa320_init_ohci(void)
> ?static inline void colibri_pxa320_init_ohci(void) {}
> ?#endif /* CONFIG_USB_OHCI_HCD || CONFIG_USB_OHCI_HCD_MODULE */
>
> +#if defined(CONFIG_USB_GADGET_PXA27X)||defined(CONFIG_USB_GADGET_PXA27X_MODULE)
> +static struct gpio_vbus_mach_info colibri_pxa320_gpio_vbus_info = {
> + ? ? ? .gpio_vbus ? ? ? ? ? ? ?= mfp_to_gpio(MFP_PIN_GPIO96),
> + ? ? ? .gpio_pullup ? ? ? ? ? ?= -1,
> +};
> +
> +static struct platform_device colibri_pxa320_gpio_vbus = {
> + ? ? ? .name ? = "gpio-vbus",
> + ? ? ? .id ? ? = -1,
> + ? ? ? .dev ? ?= {
> + ? ? ? ? ? ? ? .platform_data ?= &colibri_pxa320_gpio_vbus_info,
> + ? ? ? },
> +};
> +
> +static void colibri_pxa320_udc_command(int cmd)
> +{
> + ? ? ? if (cmd == PXA2XX_UDC_CMD_CONNECT)
> + ? ? ? ? ? ? ? UP2OCR = UP2OCR_HXOE | UP2OCR_DPPUE;
> + ? ? ? else if (cmd == PXA2XX_UDC_CMD_DISCONNECT)
> + ? ? ? ? ? ? ? UP2OCR = UP2OCR_HXOE;
> +}
> +
> +static struct pxa2xx_udc_mach_info colibri_pxa320_udc_info __initdata = {
> + ? ? ? .udc_command ? ? ? ? ? ?= colibri_pxa320_udc_command,
> + ? ? ? .gpio_pullup ? ? ? ? ? ?= -1,
> +};
> +
> +static void __init colibri_pxa320_init_udc(void)
> +{
> + ? ? ? pxa_set_udc_info(&colibri_pxa320_udc_info);
> + ? ? ? platform_device_register(&colibri_pxa320_gpio_vbus);
> +}
> +#else
> +static inline void colibri_pxa320_init_udc(void) {}
> +#endif
> +
> ?static mfp_cfg_t colibri_pxa320_mmc_pin_config[] __initdata = {
> ? ? ? ?GPIO22_MMC1_CLK,
> ? ? ? ?GPIO23_MMC1_CMD,
> @@ -212,6 +251,7 @@ void __init colibri_pxa320_init(void)
> ? ? ? ?colibri_pxa3xx_init_mmc(ARRAY_AND_SIZE(colibri_pxa320_mmc_pin_config),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?mfp_to_gpio(MFP_PIN_GPIO28));
> ? ? ? ?colibri_pxa320_init_uart();
> + ? ? ? colibri_pxa320_init_udc();
> ?}
>
> ?MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
> --
> 1.7.1
>
>


From eric.y.miao at gmail.com  Sun Jun 27 23:42:40 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 28 Jun 2010 11:42:40 +0800
Subject: [PATCH 3/4] ARM/scoop: Add CPR register bit definitions
In-Reply-To: <1277388132-5549-3-git-send-email-marek.vasut@gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com> 
	<1277388132-5549-3-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTilLa0bazRIEUs5qyOsELiQ1aGZ8R4sDxaIeApNd@mail.gmail.com>

On Thu, Jun 24, 2010 at 10:02 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Add bit definitions of the CPR register of the SCOOP chip into scoop.h. Also,
> cleanup the GPCR definitions to match coding style.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Applied.

> ---
> ?arch/arm/include/asm/hardware/scoop.h | ? 29 +++++++++++++++++------------
> ?1 files changed, 17 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h
> index 46492a6..ebb3cea 100644
> --- a/arch/arm/include/asm/hardware/scoop.h
> +++ b/arch/arm/include/asm/hardware/scoop.h
> @@ -22,18 +22,23 @@
> ?#define SCOOP_GPWR 0x24
> ?#define SCOOP_GPRR 0x28
>
> -#define SCOOP_GPCR_PA22 ? ? ? ?( 1 << 12 )
> -#define SCOOP_GPCR_PA21 ? ? ? ?( 1 << 11 )
> -#define SCOOP_GPCR_PA20 ? ? ? ?( 1 << 10 )
> -#define SCOOP_GPCR_PA19 ? ? ? ?( 1 << 9 )
> -#define SCOOP_GPCR_PA18 ? ? ? ?( 1 << 8 )
> -#define SCOOP_GPCR_PA17 ? ? ? ?( 1 << 7 )
> -#define SCOOP_GPCR_PA16 ? ? ? ?( 1 << 6 )
> -#define SCOOP_GPCR_PA15 ? ? ? ?( 1 << 5 )
> -#define SCOOP_GPCR_PA14 ? ? ? ?( 1 << 4 )
> -#define SCOOP_GPCR_PA13 ? ? ? ?( 1 << 3 )
> -#define SCOOP_GPCR_PA12 ? ? ? ?( 1 << 2 )
> -#define SCOOP_GPCR_PA11 ? ? ? ?( 1 << 1 )
> +#define SCOOP_CPR_OUT ?(1 << 7)
> +#define SCOOP_CPR_SD_3V ? ? ? ?(1 << 2)
> +#define SCOOP_CPR_CF_XV ? ? ? ?(1 << 1)
> +#define SCOOP_CPR_CF_3V ? ? ? ?(1 << 0)
> +
> +#define SCOOP_GPCR_PA22 ? ? ? ?(1 << 12)
> +#define SCOOP_GPCR_PA21 ? ? ? ?(1 << 11)
> +#define SCOOP_GPCR_PA20 ? ? ? ?(1 << 10)
> +#define SCOOP_GPCR_PA19 ? ? ? ?(1 << 9)
> +#define SCOOP_GPCR_PA18 ? ? ? ?(1 << 8)
> +#define SCOOP_GPCR_PA17 ? ? ? ?(1 << 7)
> +#define SCOOP_GPCR_PA16 ? ? ? ?(1 << 6)
> +#define SCOOP_GPCR_PA15 ? ? ? ?(1 << 5)
> +#define SCOOP_GPCR_PA14 ? ? ? ?(1 << 4)
> +#define SCOOP_GPCR_PA13 ? ? ? ?(1 << 3)
> +#define SCOOP_GPCR_PA12 ? ? ? ?(1 << 2)
> +#define SCOOP_GPCR_PA11 ? ? ? ?(1 << 1)
>
> ?struct scoop_config {
> ? ? ? ?unsigned short io_out;
> --
> 1.7.1
>
>


From eric.y.miao at gmail.com  Sun Jun 27 23:43:12 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 28 Jun 2010 11:43:12 +0800
Subject: [PATCH 4/4] pxa/spitz: Rework spitz
In-Reply-To: <1277388132-5549-4-git-send-email-marek.vasut@gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com> 
	<1277388132-5549-4-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTilwG3Blw8s8g2pTi4V5UEys25hEWL30bfav-P6b@mail.gmail.com>

On Thu, Jun 24, 2010 at 10:02 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> This huge patch mostly shuffles code. The spitz.c file contained terrible mess
> and needed a cleanup, here it is:
>
> 1) Made every part modular, components are not built in if not selected.
> 2) Removed loads of preprocessor goo, mostly "#ifdef MACH_AKITA .... #endif" and
> ? similar code. The kernel size will grow by a few kb now, but the file is much
> ? more readable.
> 3) Reworked SD/CF power setting function and made it reentrant.
> 4) Add ISL6271A regulator support
> 5) Correctly register WM8750
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

I'd prefer to see separate small patches for this?

> ---
> ?arch/arm/mach-pxa/include/mach/spitz.h | ? ?2 -
> ?arch/arm/mach-pxa/spitz.c ? ? ? ? ? ? ?| ?813 ++++++++++++++++++--------------
> ?2 files changed, 470 insertions(+), 345 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/include/mach/spitz.h b/arch/arm/mach-pxa/include/mach/spitz.h
> index fa1998c..685749a 100644
> --- a/arch/arm/mach-pxa/include/mach/spitz.h
> +++ b/arch/arm/mach-pxa/include/mach/spitz.h
> @@ -185,7 +185,5 @@
> ?/*
> ?* Shared data structures
> ?*/
> -extern struct platform_device spitzscoop_device;
> -extern struct platform_device spitzscoop2_device;
> ?extern struct platform_device spitzssp_device;
> ?extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
> diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
> index c1048a3..fa31980 100644
> --- a/arch/arm/mach-pxa/spitz.c
> +++ b/arch/arm/mach-pxa/spitz.c
> @@ -18,14 +18,15 @@
> ?#include <linux/gpio_keys.h>
> ?#include <linux/gpio.h>
> ?#include <linux/leds.h>
> -#include <linux/mtd/physmap.h>
> ?#include <linux/i2c.h>
> ?#include <linux/i2c/pca953x.h>
> ?#include <linux/spi/spi.h>
> ?#include <linux/spi/ads7846.h>
> ?#include <linux/spi/corgi_lcd.h>
> +#include <linux/mtd/physmap.h>
> ?#include <linux/mtd/sharpsl.h>
> ?#include <linux/input/matrix_keypad.h>
> +#include <linux/regulator/machine.h>
>
> ?#include <asm/setup.h>
> ?#include <asm/mach-types.h>
> @@ -33,11 +34,9 @@
> ?#include <asm/mach/sharpsl_param.h>
> ?#include <asm/hardware/scoop.h>
>
> -
> ?#include <mach/pxa27x.h>
> ?#include <mach/pxa27x-udc.h>
> ?#include <mach/reset.h>
> -#include <plat/i2c.h>
> ?#include <mach/irda.h>
> ?#include <mach/mmc.h>
> ?#include <mach/ohci.h>
> @@ -45,11 +44,16 @@
> ?#include <mach/pxa2xx_spi.h>
> ?#include <mach/spitz.h>
>
> +#include <plat/i2c.h>
> +
> ?#include "generic.h"
> ?#include "devices.h"
> ?#include "sharpsl.h"
>
> -static unsigned long spitz_pin_config[] __initdata = {
> +/******************************************************************************
> + * Pin configuration
> + ******************************************************************************/
> +static unsigned long sharpslc_pin_config[] __initdata = {
> ? ? ? ?/* Chip Selects */
> ? ? ? ?GPIO78_nCS_2, ? /* SCOOP #2 */
> ? ? ? ?GPIO79_nCS_3, ? /* NAND */
> @@ -124,10 +128,13 @@ static unsigned long spitz_pin_config[] __initdata = {
> ? ? ? ?GPIO1_GPIO | WAKEUP_ON_EDGE_FALL, ? ? ? /* SPITZ_GPIO_RESET */
> ?};
>
> -/*
> - * Spitz SCOOP Device #1
> - */
> -static struct resource spitz_scoop_resources[] = {
> +
> +/******************************************************************************
> + * Scoop GPIO expander
> + ******************************************************************************/
> +#if defined(CONFIG_SHARP_SCOOP) || defined(CONFIG_SHARP_SCOOP_MODULE)
> +/* SCOOP Device #1 */
> +static struct resource sharpslc_scoop_1_resources[] = {
> ? ? ? ?[0] = {
> ? ? ? ? ? ? ? ?.start ? ? ? ? ?= 0x10800000,
> ? ? ? ? ? ? ? ?.end ? ? ? ? ? ?= 0x10800fff,
> @@ -135,7 +142,7 @@ static struct resource spitz_scoop_resources[] = {
> ? ? ? ?},
> ?};
>
> -static struct scoop_config spitz_scoop_setup = {
> +static struct scoop_config sharpslc_scoop_1_setup = {
> ? ? ? ?.io_dir ? ? ? ? = SPITZ_SCP_IO_DIR,
> ? ? ? ?.io_out ? ? ? ? = SPITZ_SCP_IO_OUT,
> ? ? ? ?.suspend_clr ? ?= SPITZ_SCP_SUS_CLR,
> @@ -143,20 +150,18 @@ static struct scoop_config spitz_scoop_setup = {
> ? ? ? ?.gpio_base ? ? ?= SPITZ_SCP_GPIO_BASE,
> ?};
>
> -struct platform_device spitzscoop_device = {
> +struct platform_device sharpslc_scoop_1_device = {
> ? ? ? ?.name ? ? ? ? ? = "sharp-scoop",
> ? ? ? ?.id ? ? ? ? ? ? = 0,
> ? ? ? ?.dev ? ? ? ? ? ?= {
> - ? ? ? ? ? ? ? .platform_data ?= &spitz_scoop_setup,
> + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_scoop_1_setup,
> ? ? ? ?},
> - ? ? ? .num_resources ?= ARRAY_SIZE(spitz_scoop_resources),
> - ? ? ? .resource ? ? ? = spitz_scoop_resources,
> + ? ? ? .num_resources ?= ARRAY_SIZE(sharpslc_scoop_1_resources),
> + ? ? ? .resource ? ? ? = sharpslc_scoop_1_resources,
> ?};
>
> -/*
> - * Spitz SCOOP Device #2
> - */
> -static struct resource spitz_scoop2_resources[] = {
> +/* SCOOP Device #2 */
> +static struct resource sharpslc_scoop_2_resources[] = {
> ? ? ? ?[0] = {
> ? ? ? ? ? ? ? ?.start ? ? ? ? ?= 0x08800040,
> ? ? ? ? ? ? ? ?.end ? ? ? ? ? ?= 0x08800fff,
> @@ -164,7 +169,7 @@ static struct resource spitz_scoop2_resources[] = {
> ? ? ? ?},
> ?};
>
> -static struct scoop_config spitz_scoop2_setup = {
> +static struct scoop_config sharpslc_scoop_2_setup = {
> ? ? ? ?.io_dir ? ? ? ? = SPITZ_SCP2_IO_DIR,
> ? ? ? ?.io_out ? ? ? ? = SPITZ_SCP2_IO_OUT,
> ? ? ? ?.suspend_clr ? ?= SPITZ_SCP2_SUS_CLR,
> @@ -172,82 +177,110 @@ static struct scoop_config spitz_scoop2_setup = {
> ? ? ? ?.gpio_base ? ? ?= SPITZ_SCP2_GPIO_BASE,
> ?};
>
> -struct platform_device spitzscoop2_device = {
> +struct platform_device sharpslc_scoop_2_device = {
> ? ? ? ?.name ? ? ? ? ? = "sharp-scoop",
> ? ? ? ?.id ? ? ? ? ? ? = 1,
> ? ? ? ?.dev ? ? ? ? ? ?= {
> - ? ? ? ? ? ? ? .platform_data ?= &spitz_scoop2_setup,
> + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_scoop_2_setup,
> ? ? ? ?},
> - ? ? ? .num_resources ?= ARRAY_SIZE(spitz_scoop2_resources),
> - ? ? ? .resource ? ? ? = spitz_scoop2_resources,
> + ? ? ? .num_resources ?= ARRAY_SIZE(sharpslc_scoop_2_resources),
> + ? ? ? .resource ? ? ? = sharpslc_scoop_2_resources,
> ?};
>
> -#define SPITZ_PWR_SD 0x01
> -#define SPITZ_PWR_CF 0x02
> +static void __init sharpslc_scoop_init(void)
> +{
> + ? ? ? platform_device_register(&sharpslc_scoop_1_device);
> +
> + ? ? ? /* Akita doesn't have the second SCOOP chip */
> + ? ? ? if (!machine_is_akita())
> + ? ? ? ? ? ? ? platform_device_register(&sharpslc_scoop_2_device);
> +}
>
> ?/* Power control is shared with between one of the CF slots and SD */
> -static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr)
> +static void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr)
> ?{
> - ? ? ? unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR);
> + ? ? ? unsigned short cpr;
> + ? ? ? unsigned long flags;
>
> - ? ? ? if (new_cpr & 0x0007) {
> + ? ? ? if (new_cpr & 0x7) {
> ? ? ? ? ? ? ? ?gpio_set_value(SPITZ_GPIO_CF_POWER, 1);
> - ? ? ? ? ? ? ? if (!(cpr & 0x0002) && !(cpr & 0x0004))
> - ? ? ? ? ? ? ? ? ? ? ? mdelay(5);
> - ? ? ? ? ? ? ? if (device == SPITZ_PWR_CF)
> - ? ? ? ? ? ? ? ? ? ? ? cpr |= 0x0002;
> - ? ? ? ? ? ? ? if (device == SPITZ_PWR_SD)
> - ? ? ? ? ? ? ? ? ? ? ? cpr |= 0x0004;
> - ? ? ? ? ? ? ? write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
> - ? ? ? } else {
> - ? ? ? ? ? ? ? if (device == SPITZ_PWR_CF)
> - ? ? ? ? ? ? ? ? ? ? ? cpr &= ~0x0002;
> - ? ? ? ? ? ? ? if (device == SPITZ_PWR_SD)
> - ? ? ? ? ? ? ? ? ? ? ? cpr &= ~0x0004;
> - ? ? ? ? ? ? ? if (!(cpr & 0x0002) && !(cpr & 0x0004)) {
> - ? ? ? ? ? ? ? ? ? ? ? write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, 0x0000);
> - ? ? ? ? ? ? ? ? ? ? ? mdelay(1);
> - ? ? ? ? ? ? ? ? ? ? ? gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
> - ? ? ? ? ? ? ? } else {
> - ? ? ? ? ? ? ? ? ? ? ? write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr | new_cpr);
> - ? ? ? ? ? ? ? }
> + ? ? ? ? ? ? ? mdelay(5);
> + ? ? ? }
> +
> + ? ? ? local_irq_save(flags);
> +
> + ? ? ? cpr = read_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR);
> +
> + ? ? ? if (enable & new_cpr)
> + ? ? ? ? ? ? ? cpr |= new_cpr;
> + ? ? ? else
> + ? ? ? ? ? ? ? cpr &= ~enable;
> +
> + ? ? ? write_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR, cpr);
> +
> + ? ? ? local_irq_restore(flags);
> +
> + ? ? ? if (!(cpr & 0x7)) {
> + ? ? ? ? ? ? ? mdelay(1);
> + ? ? ? ? ? ? ? gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
> ? ? ? ?}
> ?}
>
> -static void spitz_pcmcia_pwr(struct device *scoop, unsigned short cpr, int nr)
> +#else
> +static inline void sharpslc_scoop_init(void) {}
> +static inline void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr) {}
> +#endif
> +
> +/******************************************************************************
> + * PCMCIA
> + ******************************************************************************/
> +#if defined(CONFIG_PCMCIA_PXA2XX) || defined(CONFIG_PCMCIA_PXA2XX_MODULE)
> +static void sharpslc_pcmcia_pwr(struct device *scoop, uint16_t cpr, int nr)
> ?{
> ? ? ? ?/* Only need to override behaviour for slot 0 */
> ? ? ? ?if (nr == 0)
> - ? ? ? ? ? ? ? spitz_card_pwr_ctrl(SPITZ_PWR_CF, cpr);
> + ? ? ? ? ? ? ? sharpslc_card_pwr_ctrl(
> + ? ? ? ? ? ? ? ? ? ? ? cpr & (SCOOP_CPR_CF_3V | SCOOP_CPR_CF_XV), cpr);
> ? ? ? ?else
> ? ? ? ? ? ? ? ?write_scoop_reg(scoop, SCOOP_CPR, cpr);
> ?}
>
> -static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
> -{
> - ? ? ? .dev ? ? ? ?= &spitzscoop_device.dev,
> - ? ? ? .irq ? ? ? ?= SPITZ_IRQ_GPIO_CF_IRQ,
> - ? ? ? .cd_irq ? ? = SPITZ_IRQ_GPIO_CF_CD,
> - ? ? ? .cd_irq_str = "PCMCIA0 CD",
> -},{
> - ? ? ? .dev ? ? ? ?= &spitzscoop2_device.dev,
> - ? ? ? .irq ? ? ? ?= SPITZ_IRQ_GPIO_CF2_IRQ,
> - ? ? ? .cd_irq ? ? = -1,
> -},
> +static struct scoop_pcmcia_dev sharpslc_pcmcia_scoop[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .dev ? ? ? ?= &sharpslc_scoop_1_device.dev,
> + ? ? ? ? ? ? ? .irq ? ? ? ?= SPITZ_IRQ_GPIO_CF_IRQ,
> + ? ? ? ? ? ? ? .cd_irq ? ? = SPITZ_IRQ_GPIO_CF_CD,
> + ? ? ? ? ? ? ? .cd_irq_str = "PCMCIA0 CD",
> + ? ? ? }, {
> + ? ? ? ? ? ? ? .dev ? ? ? ?= &sharpslc_scoop_2_device.dev,
> + ? ? ? ? ? ? ? .irq ? ? ? ?= SPITZ_IRQ_GPIO_CF2_IRQ,
> + ? ? ? ? ? ? ? .cd_irq ? ? = -1,
> + ? ? ? },
> ?};
>
> -static struct scoop_pcmcia_config spitz_pcmcia_config = {
> - ? ? ? .devs ? ? ? ? = &spitz_pcmcia_scoop[0],
> - ? ? ? .num_devs ? ? = 2,
> - ? ? ? .power_ctrl ? = spitz_pcmcia_pwr,
> +static struct scoop_pcmcia_config sharpslc_pcmcia_config = {
> + ? ? ? .devs ? ? ? ? ? = &sharpslc_pcmcia_scoop[0],
> + ? ? ? .num_devs ? ? ? = 2,
> + ? ? ? .power_ctrl ? ? = sharpslc_pcmcia_pwr,
> ?};
>
> -EXPORT_SYMBOL(spitzscoop_device);
> -EXPORT_SYMBOL(spitzscoop2_device);
> +static void __init sharpslc_pcmcia_init(void)
> +{
> + ? ? ? /* Akita has only one PCMCIA slot used */
> + ? ? ? if (machine_is_akita())
> + ? ? ? ? ? ? ? sharpslc_pcmcia_config.num_devs = 1;
> +
> + ? ? ? platform_scoop_config = &sharpslc_pcmcia_config;
> +}
> +#else
> +static inline void sharpslc_pcmcia_init(void) {}
> +#endif
> +
> +/******************************************************************************
> + * GPIO keyboard
> + ******************************************************************************/
> +#if defined(CONFIG_KEYBOARD_MATRIX) || defined(CONFIG_KEYBOARD_MATRIX_MODULE)
>
> -/*
> - * Spitz Keyboard Device
> - */
> ?#define SPITZ_KEY_CALENDAR ? ? KEY_F1
> ?#define SPITZ_KEY_ADDRESS ? ? ?KEY_F2
> ?#define SPITZ_KEY_FN ? ? ? ? ? KEY_F3
> @@ -263,7 +296,7 @@ EXPORT_SYMBOL(spitzscoop2_device);
> ?#define SPITZ_KEY_OK ? ? ? ? ? KEY_F11
> ?#define SPITZ_KEY_MENU ? ? ? ? KEY_F12
>
> -static const uint32_t spitzkbd_keymap[] = {
> +static const uint32_t sharpslc_keymap[] = {
> ? ? ? ?KEY(0, 0, KEY_LEFTCTRL),
> ? ? ? ?KEY(0, 1, KEY_1),
> ? ? ? ?KEY(0, 2, KEY_3),
> @@ -330,37 +363,48 @@ static const uint32_t spitzkbd_keymap[] = {
> ? ? ? ?KEY(6, 8, KEY_RIGHT),
> ?};
>
> -static const struct matrix_keymap_data spitzkbd_keymap_data = {
> - ? ? ? .keymap ? ? ? ? = spitzkbd_keymap,
> - ? ? ? .keymap_size ? ?= ARRAY_SIZE(spitzkbd_keymap),
> +static const struct matrix_keymap_data sharpslc_keymap_data = {
> + ? ? ? .keymap ? ? ? ? = sharpslc_keymap,
> + ? ? ? .keymap_size ? ?= ARRAY_SIZE(sharpslc_keymap),
> ?};
>
> -static const uint32_t spitzkbd_row_gpios[] =
> +static const uint32_t sharpslc_row_gpios[] =
> ? ? ? ? ? ? ? ?{ 12, 17, 91, 34, 36, 38, 39 };
> -static const uint32_t spitzkbd_col_gpios[] =
> +static const uint32_t sharpslc_col_gpios[] =
> ? ? ? ? ? ? ? ?{ 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 };
>
> -static struct matrix_keypad_platform_data spitzkbd_pdata = {
> - ? ? ? .keymap_data ? ? ? ? ? ?= &spitzkbd_keymap_data,
> - ? ? ? .row_gpios ? ? ? ? ? ? ?= spitzkbd_row_gpios,
> - ? ? ? .col_gpios ? ? ? ? ? ? ?= spitzkbd_col_gpios,
> - ? ? ? .num_row_gpios ? ? ? ? ?= ARRAY_SIZE(spitzkbd_row_gpios),
> - ? ? ? .num_col_gpios ? ? ? ? ?= ARRAY_SIZE(spitzkbd_col_gpios),
> +static struct matrix_keypad_platform_data sharpslc_mkp_pdata = {
> + ? ? ? .keymap_data ? ? ? ? ? ?= &sharpslc_keymap_data,
> + ? ? ? .row_gpios ? ? ? ? ? ? ?= sharpslc_row_gpios,
> + ? ? ? .col_gpios ? ? ? ? ? ? ?= sharpslc_col_gpios,
> + ? ? ? .num_row_gpios ? ? ? ? ?= ARRAY_SIZE(sharpslc_row_gpios),
> + ? ? ? .num_col_gpios ? ? ? ? ?= ARRAY_SIZE(sharpslc_col_gpios),
> ? ? ? ?.col_scan_delay_us ? ? ?= 10,
> ? ? ? ?.debounce_ms ? ? ? ? ? ?= 10,
> ? ? ? ?.wakeup ? ? ? ? ? ? ? ? = 1,
> ?};
>
> -static struct platform_device spitzkbd_device = {
> +static struct platform_device sharpslc_mkp_device = {
> ? ? ? ?.name ? ? ? ? ? = "matrix-keypad",
> ? ? ? ?.id ? ? ? ? ? ? = -1,
> ? ? ? ?.dev ? ? ? ? ? ?= {
> - ? ? ? ? ? ? ? .platform_data = &spitzkbd_pdata,
> + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_mkp_pdata,
> ? ? ? ?},
> ?};
>
> +static void __init sharpslc_mkp_init(void)
> +{
> + ? ? ? platform_device_register(&sharpslc_mkp_device);
> +}
> +#else
> +static inline void sharpslc_mkp_init(void) {}
> +#endif
>
> -static struct gpio_keys_button spitz_gpio_keys[] = {
> +/******************************************************************************
> + * GPIO keys
> + ******************************************************************************/
> +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
> +static struct gpio_keys_button sharpslc_gpio_keys[] = {
> ? ? ? ?{
> ? ? ? ? ? ? ? ?.type ? = EV_PWR,
> ? ? ? ? ? ? ? ?.code ? = KEY_SUSPEND,
> @@ -383,27 +427,35 @@ static struct gpio_keys_button spitz_gpio_keys[] = {
> ? ? ? ?},
> ?};
>
> -static struct gpio_keys_platform_data spitz_gpio_keys_platform_data = {
> - ? ? ? .buttons ? ? ? ?= spitz_gpio_keys,
> - ? ? ? .nbuttons ? ? ? = ARRAY_SIZE(spitz_gpio_keys),
> +static struct gpio_keys_platform_data sharpslc_gpio_keys_platform_data = {
> + ? ? ? .buttons ? ? ? ?= sharpslc_gpio_keys,
> + ? ? ? .nbuttons ? ? ? = ARRAY_SIZE(sharpslc_gpio_keys),
> ?};
>
> -static struct platform_device spitz_gpio_keys_device = {
> +static struct platform_device sharpslc_gpio_keys_device = {
> ? ? ? ?.name ? = "gpio-keys",
> ? ? ? ?.id ? ? = -1,
> ? ? ? ?.dev ? ?= {
> - ? ? ? ? ? ? ? .platform_data ?= &spitz_gpio_keys_platform_data,
> + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_gpio_keys_platform_data,
> ? ? ? ?},
> ?};
>
> +static void __init sharpslc_keys_init(void)
> +{
> + ? ? ? platform_device_register(&sharpslc_gpio_keys_device);
> +}
> +#else
> +static inline void sharpslc_keys_init(void) {}
> +#endif
>
> -/*
> - * Spitz LEDs
> - */
> -static struct gpio_led spitz_gpio_leds[] = {
> +/******************************************************************************
> + * LEDs
> + ******************************************************************************/
> +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
> +static struct gpio_led sharpslc_gpio_leds[] = {
> ? ? ? ?{
> ? ? ? ? ? ? ? ?.name ? ? ? ? ? ? ? ? ? = "spitz:amber:charge",
> - ? ? ? ? ? ? ? .default_trigger ? ? ? ?= "sharpsl-charge",
> + ? ? ? ? ? ? ? .default_trigger ? ? ? ?= "sharpslc-charge",
> ? ? ? ? ? ? ? ?.gpio ? ? ? ? ? ? ? ? ? = SPITZ_GPIO_LED_ORANGE,
> ? ? ? ?},
> ? ? ? ?{
> @@ -413,25 +465,32 @@ static struct gpio_led spitz_gpio_leds[] = {
> ? ? ? ?},
> ?};
>
> -static struct gpio_led_platform_data spitz_gpio_leds_info = {
> - ? ? ? .leds ? ? ? ? ? = spitz_gpio_leds,
> - ? ? ? .num_leds ? ? ? = ARRAY_SIZE(spitz_gpio_leds),
> +static struct gpio_led_platform_data sharpslc_gpio_leds_info = {
> + ? ? ? .leds ? ? ? ? ? = sharpslc_gpio_leds,
> + ? ? ? .num_leds ? ? ? = ARRAY_SIZE(sharpslc_gpio_leds),
> ?};
>
> -static struct platform_device spitzled_device = {
> +static struct platform_device sharpslc_led_device = {
> ? ? ? ?.name ? ? ? ? ? = "leds-gpio",
> ? ? ? ?.id ? ? ? ? ? ? = -1,
> ? ? ? ?.dev ? ? ? ? ? ?= {
> - ? ? ? ? ? ? ? .platform_data = &spitz_gpio_leds_info,
> + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_gpio_leds_info,
> ? ? ? ?},
> ?};
>
> -#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
> -static struct pxa2xx_spi_master spitz_spi_info = {
> - ? ? ? .num_chipselect = 3,
> -};
> +static void __init sharpslc_leds_init(void)
> +{
> + ? ? ? platform_device_register(&sharpslc_led_device);
> +}
> +#else
> +static inline void sharpslc_leds_init(void) {}
> +#endif
>
> -static void spitz_wait_for_hsync(void)
> +/******************************************************************************
> + * SSP Devices
> + ******************************************************************************/
> +#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
> +static void sharpslc_ads7846_wait_for_hsync(void)
> ?{
> ? ? ? ?while (gpio_get_value(SPITZ_GPIO_HSYNC))
> ? ? ? ? ? ? ? ?cpu_relax();
> @@ -440,21 +499,21 @@ static void spitz_wait_for_hsync(void)
> ? ? ? ? ? ? ? ?cpu_relax();
> ?}
>
> -static struct ads7846_platform_data spitz_ads7846_info = {
> +static struct ads7846_platform_data sharpslc_ads7846_info = {
> ? ? ? ?.model ? ? ? ? ? ? ? ? ?= 7846,
> ? ? ? ?.vref_delay_usecs ? ? ? = 100,
> ? ? ? ?.x_plate_ohms ? ? ? ? ? = 419,
> ? ? ? ?.y_plate_ohms ? ? ? ? ? = 486,
> ? ? ? ?.pressure_max ? ? ? ? ? = 1024,
> ? ? ? ?.gpio_pendown ? ? ? ? ? = SPITZ_GPIO_TP_INT,
> - ? ? ? .wait_for_sync ? ? ? ? ?= spitz_wait_for_hsync,
> + ? ? ? .wait_for_sync ? ? ? ? ?= sharpslc_ads7846_wait_for_hsync,
> ?};
>
> -static struct pxa2xx_spi_chip spitz_ads7846_chip = {
> +static struct pxa2xx_spi_chip sharpslc_ads7846_chip = {
> ? ? ? ?.gpio_cs ? ? ? ? ? ? ? ?= SPITZ_GPIO_ADS7846_CS,
> ?};
>
> -static void spitz_bl_kick_battery(void)
> +static void sharpslc_bl_kick_battery(void)
> ?{
> ? ? ? ?void (*kick_batt)(void);
>
> @@ -465,93 +524,109 @@ static void spitz_bl_kick_battery(void)
> ? ? ? ?}
> ?}
>
> -static struct corgi_lcd_platform_data spitz_lcdcon_info = {
> +static struct corgi_lcd_platform_data sharpslc_lcdcon_info = {
> ? ? ? ?.init_mode ? ? ? ? ? ? ?= CORGI_LCD_MODE_VGA,
> ? ? ? ?.max_intensity ? ? ? ? ?= 0x2f,
> ? ? ? ?.default_intensity ? ? ?= 0x1f,
> ? ? ? ?.limit_mask ? ? ? ? ? ? = 0x0b,
> ? ? ? ?.gpio_backlight_cont ? ?= SPITZ_GPIO_BACKLIGHT_CONT,
> ? ? ? ?.gpio_backlight_on ? ? ?= SPITZ_GPIO_BACKLIGHT_ON,
> - ? ? ? .kick_battery ? ? ? ? ? = spitz_bl_kick_battery,
> + ? ? ? .kick_battery ? ? ? ? ? = sharpslc_bl_kick_battery,
> ?};
>
> -static struct pxa2xx_spi_chip spitz_lcdcon_chip = {
> +static struct pxa2xx_spi_chip sharpslc_lcdcon_chip = {
> ? ? ? ?.gpio_cs ? ? ? ?= SPITZ_GPIO_LCDCON_CS,
> ?};
>
> -static struct pxa2xx_spi_chip spitz_max1111_chip = {
> +static struct pxa2xx_spi_chip sharpslc_max1111_chip = {
> ? ? ? ?.gpio_cs ? ? ? ?= SPITZ_GPIO_MAX1111_CS,
> ?};
>
> -static struct spi_board_info spitz_spi_devices[] = {
> +static struct spi_board_info sharpslc_spi_devices[] = {
> ? ? ? ?{
> - ? ? ? ? ? ? ? .modalias ? ? ? = "ads7846",
> - ? ? ? ? ? ? ? .max_speed_hz ? = 1200000,
> - ? ? ? ? ? ? ? .bus_num ? ? ? ?= 2,
> - ? ? ? ? ? ? ? .chip_select ? ?= 0,
> - ? ? ? ? ? ? ? .platform_data ?= &spitz_ads7846_info,
> - ? ? ? ? ? ? ? .controller_data= &spitz_ads7846_chip,
> - ? ? ? ? ? ? ? .irq ? ? ? ? ? ?= gpio_to_irq(SPITZ_GPIO_TP_INT),
> + ? ? ? ? ? ? ? .modalias ? ? ? ? ? ? ? = "ads7846",
> + ? ? ? ? ? ? ? .max_speed_hz ? ? ? ? ? = 1200000,
> + ? ? ? ? ? ? ? .bus_num ? ? ? ? ? ? ? ?= 2,
> + ? ? ? ? ? ? ? .chip_select ? ? ? ? ? ?= 0,
> + ? ? ? ? ? ? ? .platform_data ? ? ? ? ?= &sharpslc_ads7846_info,
> + ? ? ? ? ? ? ? .controller_data ? ? ? ?= &sharpslc_ads7846_chip,
> + ? ? ? ? ? ? ? .irq ? ? ? ? ? ? ? ? ? ?= gpio_to_irq(SPITZ_GPIO_TP_INT),
> ? ? ? ?}, {
> - ? ? ? ? ? ? ? .modalias ? ? ? = "corgi-lcd",
> - ? ? ? ? ? ? ? .max_speed_hz ? = 50000,
> - ? ? ? ? ? ? ? .bus_num ? ? ? ?= 2,
> - ? ? ? ? ? ? ? .chip_select ? ?= 1,
> - ? ? ? ? ? ? ? .platform_data ?= &spitz_lcdcon_info,
> - ? ? ? ? ? ? ? .controller_data= &spitz_lcdcon_chip,
> + ? ? ? ? ? ? ? .modalias ? ? ? ? ? ? ? = "corgi-lcd",
> + ? ? ? ? ? ? ? .max_speed_hz ? ? ? ? ? = 50000,
> + ? ? ? ? ? ? ? .bus_num ? ? ? ? ? ? ? ?= 2,
> + ? ? ? ? ? ? ? .chip_select ? ? ? ? ? ?= 1,
> + ? ? ? ? ? ? ? .platform_data ? ? ? ? ?= &sharpslc_lcdcon_info,
> + ? ? ? ? ? ? ? .controller_data ? ? ? ?= &sharpslc_lcdcon_chip,
> ? ? ? ?}, {
> - ? ? ? ? ? ? ? .modalias ? ? ? = "max1111",
> - ? ? ? ? ? ? ? .max_speed_hz ? = 450000,
> - ? ? ? ? ? ? ? .bus_num ? ? ? ?= 2,
> - ? ? ? ? ? ? ? .chip_select ? ?= 2,
> - ? ? ? ? ? ? ? .controller_data= &spitz_max1111_chip,
> + ? ? ? ? ? ? ? .modalias ? ? ? ? ? ? ? = "max1111",
> + ? ? ? ? ? ? ? .max_speed_hz ? ? ? ? ? = 450000,
> + ? ? ? ? ? ? ? .bus_num ? ? ? ? ? ? ? ?= 2,
> + ? ? ? ? ? ? ? .chip_select ? ? ? ? ? ?= 2,
> + ? ? ? ? ? ? ? .controller_data ? ? ? ?= &sharpslc_max1111_chip,
> ? ? ? ?},
> ?};
>
> -static void __init spitz_init_spi(void)
> +static struct pxa2xx_spi_master sharpslc_spi_info = {
> + ? ? ? .num_chipselect = 3,
> +};
> +
> +static void __init sharpslc_spi_init(void)
> ?{
> + ? ? ? struct corgi_lcd_platform_data *lcd_data = &sharpslc_lcdcon_info;
> +
> ? ? ? ?if (machine_is_akita()) {
> - ? ? ? ? ? ? ? spitz_lcdcon_info.gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
> - ? ? ? ? ? ? ? spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
> + ? ? ? ? ? ? ? lcd_data->gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT;
> + ? ? ? ? ? ? ? lcd_data->gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON;
> ? ? ? ?}
>
> - ? ? ? pxa2xx_set_spi_info(2, &spitz_spi_info);
> - ? ? ? spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
> + ? ? ? pxa2xx_set_spi_info(2, &sharpslc_spi_info);
> + ? ? ? spi_register_board_info(ARRAY_AND_SIZE(sharpslc_spi_devices));
> ?}
> ?#else
> -static inline void spitz_init_spi(void) {}
> +static inline void sharpslc_spi_init(void) {}
> ?#endif
>
> +/******************************************************************************
> + * SD/MMC card controller
> + ******************************************************************************/
> +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
> ?/*
> - * MMC/SD Device
> - *
> - * The card detect interrupt isn't debounced so we delay it by 250ms
> - * to give the card a chance to fully insert/eject.
> + * NOTE: The card detect interrupt isn't debounced so we delay it by 250ms to
> + * give the card a chance to fully insert/eject.
> ?*/
> -static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
> +static void sharpslc_mci_setpower(struct device *dev, unsigned int vdd)
> ?{
> ? ? ? ?struct pxamci_platform_data* p_d = dev->platform_data;
>
> - ? ? ? if (( 1 << vdd) & p_d->ocr_mask)
> - ? ? ? ? ? ? ? spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0004);
> + ? ? ? if ((1 << vdd) & p_d->ocr_mask)
> + ? ? ? ? ? ? ? sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
> ? ? ? ?else
> - ? ? ? ? ? ? ? spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0000);
> + ? ? ? ? ? ? ? sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
> ?}
>
> -static struct pxamci_platform_data spitz_mci_platform_data = {
> +static struct pxamci_platform_data sharpslc_mci_platform_data = {
> ? ? ? ?.detect_delay_ms ? ? ? ?= 250,
> ? ? ? ?.ocr_mask ? ? ? ? ? ? ? = MMC_VDD_32_33|MMC_VDD_33_34,
> - ? ? ? .setpower ? ? ? ? ? ? ? = spitz_mci_setpower,
> + ? ? ? .setpower ? ? ? ? ? ? ? = sharpslc_mci_setpower,
> ? ? ? ?.gpio_card_detect ? ? ? = SPITZ_GPIO_nSD_DETECT,
> ? ? ? ?.gpio_card_ro ? ? ? ? ? = SPITZ_GPIO_nSD_WP,
> ? ? ? ?.gpio_power ? ? ? ? ? ? = -1,
> ?};
>
> +static void __init sharpslc_mmc_init(void)
> +{
> + ? ? ? pxa_set_mci_info(&sharpslc_mci_platform_data);
> +}
> +#else
> +static inline void sharpslc_mmc_init(void) {}
> +#endif
>
> -/*
> - * USB Host (OHCI)
> - */
> -static int spitz_ohci_init(struct device *dev)
> +/******************************************************************************
> + * USB Host
> + ******************************************************************************/
> +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
> +static int sharpslc_ohci_init(struct device *dev)
> ?{
> ? ? ? ?int err;
>
> @@ -559,88 +634,114 @@ static int spitz_ohci_init(struct device *dev)
> ? ? ? ?if (err)
> ? ? ? ? ? ? ? ?return err;
>
> - ? ? ? /* Only Port 2 is connected
> - ? ? ? ?* Setup USB Port 2 Output Control Register
> - ? ? ? ?*/
> + ? ? ? /* Only Port 2 is connected, setup USB Port 2 Output Control Register */
> ? ? ? ?UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE | UP2OCR_DMPDE;
>
> ? ? ? ?return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1);
> ?}
>
> -static void spitz_ohci_exit(struct device *dev)
> +static void sharpslc_ohci_exit(struct device *dev)
> ?{
> ? ? ? ?gpio_free(SPITZ_GPIO_USB_HOST);
> ?}
>
> -static struct pxaohci_platform_data spitz_ohci_platform_data = {
> +static struct pxaohci_platform_data sharpslc_ohci_platform_data = {
> ? ? ? ?.port_mode ? ? ?= PMM_NPS_MODE,
> - ? ? ? .init ? ? ? ? ? = spitz_ohci_init,
> - ? ? ? .exit ? ? ? ? ? = spitz_ohci_exit,
> + ? ? ? .init ? ? ? ? ? = sharpslc_ohci_init,
> + ? ? ? .exit ? ? ? ? ? = sharpslc_ohci_exit,
> ? ? ? ?.flags ? ? ? ? ?= ENABLE_PORT_ALL | NO_OC_PROTECTION,
> ? ? ? ?.power_budget ? = 150,
> ?};
>
> +static void __init sharpslc_uhc_init(void)
> +{
> + ? ? ? pxa_set_ohci_info(&sharpslc_ohci_platform_data);
> +}
> +#else
> +static inline void sharpslc_uhc_init(void) {}
> +#endif
>
> -/*
> - * Irda
> - */
> -
> -static struct pxaficp_platform_data spitz_ficp_platform_data = {
> -/* .gpio_pwdown is set in spitz_init() and akita_init() accordingly */
> +/******************************************************************************
> + * IrDA
> + ******************************************************************************/
> +#if defined(CONFIG_PXA_FICP) || defined(CONFIG_PXA_FICP_MODULE)
> +static struct pxaficp_platform_data sharpslc_ficp_platform_data = {
> ? ? ? ?.transceiver_cap ? ? ? ?= IR_SIRMODE | IR_OFF,
> ?};
>
> +static void __init sharpslc_irda_init(void)
> +{
> + ? ? ? if (machine_is_akita())
> + ? ? ? ? ? ? ? sharpslc_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
> + ? ? ? else
> + ? ? ? ? ? ? ? sharpslc_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
>
> -/*
> - * Spitz PXA Framebuffer
> - */
> + ? ? ? pxa_set_ficp_info(&sharpslc_ficp_platform_data);
> +}
> +#else
> +static inline void sharpslc_irda_init(void) {}
> +#endif
>
> -static struct pxafb_mode_info spitz_pxafb_modes[] = {
> -{
> - ? ? ? .pixclock ? ? ? = 19231,
> - ? ? ? .xres ? ? ? ? ? = 480,
> - ? ? ? .yres ? ? ? ? ? = 640,
> - ? ? ? .bpp ? ? ? ? ? ?= 16,
> - ? ? ? .hsync_len ? ? ?= 40,
> - ? ? ? .left_margin ? ?= 46,
> - ? ? ? .right_margin ? = 125,
> - ? ? ? .vsync_len ? ? ?= 3,
> - ? ? ? .upper_margin ? = 1,
> - ? ? ? .lower_margin ? = 0,
> - ? ? ? .sync ? ? ? ? ? = 0,
> -},{
> - ? ? ? .pixclock ? ? ? = 134617,
> - ? ? ? .xres ? ? ? ? ? = 240,
> - ? ? ? .yres ? ? ? ? ? = 320,
> - ? ? ? .bpp ? ? ? ? ? ?= 16,
> - ? ? ? .hsync_len ? ? ?= 20,
> - ? ? ? .left_margin ? ?= 20,
> - ? ? ? .right_margin ? = 46,
> - ? ? ? .vsync_len ? ? ?= 2,
> - ? ? ? .upper_margin ? = 1,
> - ? ? ? .lower_margin ? = 0,
> - ? ? ? .sync ? ? ? ? ? = 0,
> -},
> -};
> -
> -static struct pxafb_mach_info spitz_pxafb_info = {
> - ? ? ? .modes ? ? ? ? ?= &spitz_pxafb_modes[0],
> - ? ? ? .num_modes ? ? ?= 2,
> +/******************************************************************************
> + * Framebuffer
> + ******************************************************************************/
> +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
> +static struct pxafb_mode_info sharpslc_pxafb_modes[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .pixclock ? ? ? = 19231,
> + ? ? ? ? ? ? ? .xres ? ? ? ? ? = 480,
> + ? ? ? ? ? ? ? .yres ? ? ? ? ? = 640,
> + ? ? ? ? ? ? ? .bpp ? ? ? ? ? ?= 16,
> + ? ? ? ? ? ? ? .hsync_len ? ? ?= 40,
> + ? ? ? ? ? ? ? .left_margin ? ?= 46,
> + ? ? ? ? ? ? ? .right_margin ? = 125,
> + ? ? ? ? ? ? ? .vsync_len ? ? ?= 3,
> + ? ? ? ? ? ? ? .upper_margin ? = 1,
> + ? ? ? ? ? ? ? .lower_margin ? = 0,
> + ? ? ? ? ? ? ? .sync ? ? ? ? ? = 0,
> + ? ? ? }, {
> + ? ? ? ? ? ? ? .pixclock ? ? ? = 134617,
> + ? ? ? ? ? ? ? .xres ? ? ? ? ? = 240,
> + ? ? ? ? ? ? ? .yres ? ? ? ? ? = 320,
> + ? ? ? ? ? ? ? .bpp ? ? ? ? ? ?= 16,
> + ? ? ? ? ? ? ? .hsync_len ? ? ?= 20,
> + ? ? ? ? ? ? ? .left_margin ? ?= 20,
> + ? ? ? ? ? ? ? .right_margin ? = 46,
> + ? ? ? ? ? ? ? .vsync_len ? ? ?= 2,
> + ? ? ? ? ? ? ? .upper_margin ? = 1,
> + ? ? ? ? ? ? ? .lower_margin ? = 0,
> + ? ? ? ? ? ? ? .sync ? ? ? ? ? = 0,
> + ? ? ? },
> +};
> +
> +static struct pxafb_mach_info sharpslc_pxafb_info = {
> + ? ? ? .modes ? ? ? ? ?= sharpslc_pxafb_modes,
> + ? ? ? .num_modes ? ? ?= ARRAY_SIZE(sharpslc_pxafb_modes),
> ? ? ? ?.fixed_modes ? ?= 1,
> ? ? ? ?.lcd_conn ? ? ? = LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
> ?};
>
> -static struct mtd_partition sharpsl_nand_partitions[] = {
> +static void __init sharpslc_lcd_init(void)
> +{
> + ? ? ? set_pxa_fb_info(&sharpslc_pxafb_info);
> +}
> +#else
> +static inline void sharpslc_lcd_init(void) {}
> +#endif
> +
> +/******************************************************************************
> + * Framebuffer
> + ******************************************************************************/
> +#if defined(CONFIG_MTD_NAND_SHARPSL) || defined(CONFIG_MTD_NAND_SHARPSL_MODULE)
> +static struct mtd_partition sharpslc_nand_partitions[] = {
> ? ? ? ?{
> ? ? ? ? ? ? ? ?.name = "System Area",
> ? ? ? ? ? ? ? ?.offset = 0,
> ? ? ? ? ? ? ? ?.size = 7 * 1024 * 1024,
> - ? ? ? },
> - ? ? ? {
> + ? ? ? }, {
> ? ? ? ? ? ? ? ?.name = "Root Filesystem",
> ? ? ? ? ? ? ? ?.offset = 7 * 1024 * 1024,
> - ? ? ? },
> - ? ? ? {
> + ? ? ? }, {
> ? ? ? ? ? ? ? ?.name = "Home Filesystem",
> ? ? ? ? ? ? ? ?.offset = MTDPART_OFS_APPEND,
> ? ? ? ? ? ? ? ?.size = MTDPART_SIZ_FULL,
> @@ -649,37 +750,72 @@ static struct mtd_partition sharpsl_nand_partitions[] = {
>
> ?static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
>
> -static struct nand_bbt_descr sharpsl_bbt = {
> - ? ? ? .options = 0,
> - ? ? ? .offs = 4,
> - ? ? ? .len = 2,
> - ? ? ? .pattern = scan_ff_pattern
> +static struct nand_bbt_descr sharpslc_nand_bbt = {
> + ? ? ? .options ? ? ? ?= 0,
> + ? ? ? .offs ? ? ? ? ? = 4,
> + ? ? ? .len ? ? ? ? ? ?= 2,
> + ? ? ? .pattern ? ? ? ?= scan_ff_pattern
> +};
> +
> +static struct nand_ecclayout sharpslc_akita_oobinfo = {
> + ? ? ? .oobfree ? ? ? ?= { {0x08, 0x09} },
> + ? ? ? .eccbytes ? ? ? = 24,
> + ? ? ? .eccpos ? ? ? ? = {
> + ? ? ? ? ? ? ? ? ? ? ? 0x05, 0x01, 0x02, 0x03, 0x06, 0x07, 0x15, 0x11,
> + ? ? ? ? ? ? ? ? ? ? ? 0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
> + ? ? ? ? ? ? ? ? ? ? ? 0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37,
> + ? ? ? },
> ?};
>
> -static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
> - ? ? ? .badblock_pattern ? ? ? = &sharpsl_bbt,
> - ? ? ? .partitions ? ? ? ? ? ? = sharpsl_nand_partitions,
> - ? ? ? .nr_partitions ? ? ? ? ?= ARRAY_SIZE(sharpsl_nand_partitions),
> +static struct sharpsl_nand_platform_data sharpslc_nand_pdata = {
> + ? ? ? .badblock_pattern ? ? ? = &sharpslc_nand_bbt,
> + ? ? ? .partitions ? ? ? ? ? ? = sharpslc_nand_partitions,
> + ? ? ? .nr_partitions ? ? ? ? ?= ARRAY_SIZE(sharpslc_nand_partitions),
> ?};
>
> -static struct resource sharpsl_nand_resources[] = {
> +static struct resource sharpslc_nand_resources[] = {
> ? ? ? ?{
> - ? ? ? ? ? ? ? .start ?= 0x0C000000,
> - ? ? ? ? ? ? ? .end ? ?= 0x0C000FFF,
> + ? ? ? ? ? ? ? .start ?= PXA_CS3_PHYS,
> + ? ? ? ? ? ? ? .end ? ?= PXA_CS3_PHYS + SZ_4K - 1,
> ? ? ? ? ? ? ? ?.flags ?= IORESOURCE_MEM,
> ? ? ? ?},
> ?};
>
> -static struct platform_device sharpsl_nand_device = {
> +static struct platform_device sharpslc_nand_device = {
> ? ? ? ?.name ? ? ? ? ? = "sharpsl-nand",
> ? ? ? ?.id ? ? ? ? ? ? = -1,
> - ? ? ? .resource ? ? ? = sharpsl_nand_resources,
> - ? ? ? .num_resources ?= ARRAY_SIZE(sharpsl_nand_resources),
> - ? ? ? .dev.platform_data ? ? ?= &sharpsl_nand_platform_data,
> + ? ? ? .resource ? ? ? = sharpslc_nand_resources,
> + ? ? ? .num_resources ?= ARRAY_SIZE(sharpslc_nand_resources),
> + ? ? ? .dev ? ? ? ? ? ?= {
> + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_nand_pdata,
> + ? ? ? }
> ?};
>
> +static void __init sharpslc_nand_init(void)
> +{
> + ? ? ? if (machine_is_spitz()) {
> + ? ? ? ? ? ? ? sharpslc_nand_partitions[1].size = 5 * 1024 * 1024;
> + ? ? ? } else if (machine_is_akita()) {
> + ? ? ? ? ? ? ? sharpslc_nand_partitions[1].size = 58 * 1024 * 1024;
> + ? ? ? ? ? ? ? sharpslc_nand_bbt.len = 1;
> + ? ? ? ? ? ? ? sharpslc_nand_pdata.ecc_layout = &sharpslc_akita_oobinfo;
> + ? ? ? } else if (machine_is_borzoi()) {
> + ? ? ? ? ? ? ? sharpslc_nand_partitions[1].size = 32 * 1024 * 1024;
> + ? ? ? ? ? ? ? sharpslc_nand_bbt.len = 1;
> + ? ? ? ? ? ? ? sharpslc_nand_pdata.ecc_layout = &sharpslc_akita_oobinfo;
> + ? ? ? }
> +
> + ? ? ? platform_device_register(&sharpslc_nand_device);
> +}
> +#else
> +static inline void sharpslc_nand_init(void) {}
> +#endif
>
> -static struct mtd_partition sharpsl_rom_parts[] = {
> +/******************************************************************************
> + * NOR Flash
> + ******************************************************************************/
> +#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
> +static struct mtd_partition sharpslc_rom_parts[] = {
> ? ? ? ?{
> ? ? ? ? ? ? ? ?.name ? ="Boot PROM Filesystem",
> ? ? ? ? ? ? ? ?.offset = 0x00140000,
> @@ -687,161 +823,152 @@ static struct mtd_partition sharpsl_rom_parts[] = {
> ? ? ? ?},
> ?};
>
> -static struct physmap_flash_data sharpsl_rom_data = {
> +static struct physmap_flash_data sharpslc_rom_data = {
> ? ? ? ?.width ? ? ? ? ?= 2,
> - ? ? ? .nr_parts ? ? ? = ARRAY_SIZE(sharpsl_rom_parts),
> - ? ? ? .parts ? ? ? ? ?= sharpsl_rom_parts,
> + ? ? ? .nr_parts ? ? ? = ARRAY_SIZE(sharpslc_rom_parts),
> + ? ? ? .parts ? ? ? ? ?= sharpslc_rom_parts,
> ?};
>
> -static struct resource sharpsl_rom_resources[] = {
> +static struct resource sharpslc_rom_resources[] = {
> ? ? ? ?{
> - ? ? ? ? ? ? ? .start ?= 0x00000000,
> - ? ? ? ? ? ? ? .end ? ?= 0x007fffff,
> + ? ? ? ? ? ? ? .start ?= PXA_CS0_PHYS,
> + ? ? ? ? ? ? ? .end ? ?= PXA_CS0_PHYS + SZ_8M - 1,
> ? ? ? ? ? ? ? ?.flags ?= IORESOURCE_MEM,
> ? ? ? ?},
> ?};
>
> -static struct platform_device sharpsl_rom_device = {
> - ? ? ? .name ? = "physmap-flash",
> - ? ? ? .id ? ? = -1,
> - ? ? ? .resource = sharpsl_rom_resources,
> - ? ? ? .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
> - ? ? ? .dev.platform_data = &sharpsl_rom_data,
> -};
> -
> -static struct platform_device *devices[] __initdata = {
> - ? ? ? &spitzscoop_device,
> - ? ? ? &spitzkbd_device,
> - ? ? ? &spitz_gpio_keys_device,
> - ? ? ? &spitzled_device,
> - ? ? ? &sharpsl_nand_device,
> - ? ? ? &sharpsl_rom_device,
> +static struct platform_device sharpslc_rom_device = {
> + ? ? ? .name ? ? ? ? ? = "physmap-flash",
> + ? ? ? .id ? ? ? ? ? ? = -1,
> + ? ? ? .resource ? ? ? = sharpslc_rom_resources,
> + ? ? ? .num_resources ?= ARRAY_SIZE(sharpslc_rom_resources),
> + ? ? ? .dev ? ? ? ? ? ?= {
> + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_rom_data,
> + ? ? ? },
> ?};
>
> -static void spitz_poweroff(void)
> +static void __init sharpslc_nor_init(void)
> ?{
> - ? ? ? arm_machine_restart('g', NULL);
> + ? ? ? platform_device_register(&sharpslc_rom_device);
> ?}
> +#else
> +static inline void sharpslc_nor_init(void) {}
> +#endif
>
> -static void spitz_restart(char mode, const char *cmd)
> -{
> - ? ? ? /* Bootloader magic for a reboot */
> - ? ? ? if((MSC0 & 0xffff0000) == 0x7ff00000)
> - ? ? ? ? ? ? ? MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
> -
> - ? ? ? spitz_poweroff();
> -}
> +/******************************************************************************
> + * GPIO expander
> + ******************************************************************************/
> +#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
> +static struct pca953x_platform_data akita_pca953x_pdata = {
> + ? ? ? .gpio_base ? ? ? ? ? ? ?= AKITA_IOEXP_GPIO_BASE,
> +};
>
> -static void __init common_init(void)
> -{
> - ? ? ? init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
> - ? ? ? pm_power_off = spitz_poweroff;
> - ? ? ? arm_pm_restart = spitz_restart;
> +static struct i2c_board_info sharpslc_i2c_devs[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .type ? ? ? ? ? = "wm8750",
> + ? ? ? ? ? ? ? .addr ? ? ? ? ? = 0x1b,
> + ? ? ? }, {
> + ? ? ? ? ? ? ? .type ? ? ? ? ? = "max7310",
> + ? ? ? ? ? ? ? .addr ? ? ? ? ? = 0x18,
> + ? ? ? ? ? ? ? .platform_data ?= &akita_pca953x_pdata,
> + ? ? ? },
> +};
>
> - ? ? ? if (machine_is_spitz()) {
> - ? ? ? ? ? ? ? sharpsl_nand_partitions[1].size = 5 * 1024 * 1024;
> - ? ? ? } else if (machine_is_akita()) {
> - ? ? ? ? ? ? ? sharpsl_nand_partitions[1].size = 58 * 1024 * 1024;
> - ? ? ? } else if (machine_is_borzoi()) {
> - ? ? ? ? ? ? ? sharpsl_nand_partitions[1].size = 32 * 1024 * 1024;
> +static struct regulator_consumer_supply isl6271a_consumers[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .supply = "vcc_core",
> ? ? ? ?}
> +};
>
> - ? ? ? PMCR = 0x00;
> -
> - ? ? ? /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
> - ? ? ? PCFR |= PCFR_OPDE;
> +static struct regulator_init_data isl6271a_info[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .constraints = {
> + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "vcc_core range",
> + ? ? ? ? ? ? ? ? ? ? ? .min_uV ? ? ? ? = 850000,
> + ? ? ? ? ? ? ? ? ? ? ? .max_uV ? ? ? ? = 1600000,
> + ? ? ? ? ? ? ? ? ? ? ? .always_on ? ? ?= 1,
> + ? ? ? ? ? ? ? ? ? ? ? .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> + ? ? ? ? ? ? ? },
> + ? ? ? .consumer_supplies ? ? ?= isl6271a_consumers,
> + ? ? ? .num_consumer_supplies ?= ARRAY_SIZE(isl6271a_consumers),
> + ? ? ? }
> +};
>
> - ? ? ? pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
> +static struct i2c_board_info sharpslc_pi2c_devs[] = {
> + ? ? ? {
> + ? ? ? ? ? ? ? .type ? ? ? ? ? = "isl6271a",
> + ? ? ? ? ? ? ? .addr ? ? ? ? ? = 0x0c,
> + ? ? ? ? ? ? ? .platform_data ?= &isl6271a_info,
> + ? ? ? },
> +};
>
> - ? ? ? pxa_set_ffuart_info(NULL);
> - ? ? ? pxa_set_btuart_info(NULL);
> - ? ? ? pxa_set_stuart_info(NULL);
> +static void __init sharpslc_i2c_init(void)
> +{
> + ? ? ? int size = ARRAY_SIZE(sharpslc_i2c_devs);
>
> - ? ? ? spitz_init_spi();
> + ? ? ? /* Only Akita has the max7310 chip */
> + ? ? ? if (!machine_is_akita())
> + ? ? ? ? ? ? ? size--;
>
> - ? ? ? platform_add_devices(devices, ARRAY_SIZE(devices));
> - ? ? ? pxa_set_mci_info(&spitz_mci_platform_data);
> - ? ? ? pxa_set_ohci_info(&spitz_ohci_platform_data);
> - ? ? ? pxa_set_ficp_info(&spitz_ficp_platform_data);
> - ? ? ? set_pxa_fb_info(&spitz_pxafb_info);
> ? ? ? ?pxa_set_i2c_info(NULL);
> + ? ? ? pxa27x_set_i2c_power_info(NULL);
> + ? ? ? i2c_register_board_info(0, sharpslc_i2c_devs, size);
> + ? ? ? i2c_register_board_info(1, ARRAY_AND_SIZE(sharpslc_pi2c_devs));
> ?}
> -
> -#if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI)
> -static struct nand_bbt_descr sharpsl_akita_bbt = {
> - ? ? ? .options = 0,
> - ? ? ? .offs = 4,
> - ? ? ? .len = 1,
> - ? ? ? .pattern = scan_ff_pattern
> -};
> -
> -static struct nand_ecclayout akita_oobinfo = {
> - ? ? ? .eccbytes = 24,
> - ? ? ? .eccpos = {
> - ? ? ? ? ? ? ? ? ?0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
> - ? ? ? ? ? ? ? ? ?0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
> - ? ? ? ? ? ? ? ? ?0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
> - ? ? ? .oobfree = {{0x08, 0x09}}
> -};
> +#else
> +static inline void sharpslc_i2c_init(void) {}
> ?#endif
>
> -#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
> -static void __init spitz_init(void)
> +/******************************************************************************
> + * Machine init
> + ******************************************************************************/
> +static void sharpslc_poweroff(void)
> ?{
> - ? ? ? spitz_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
> -
> -#ifdef CONFIG_MACH_BORZOI
> - ? ? ? if (machine_is_borzoi()) {
> - ? ? ? ? ? ? ? sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
> - ? ? ? ? ? ? ? sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
> - ? ? ? }
> -#endif
> -
> - ? ? ? platform_scoop_config = &spitz_pcmcia_config;
> -
> - ? ? ? common_init();
> -
> - ? ? ? platform_device_register(&spitzscoop2_device);
> + ? ? ? arm_machine_restart('g', NULL);
> ?}
> -#endif
>
> -#ifdef CONFIG_MACH_AKITA
> -/*
> - * Akita IO Expander
> - */
> -static struct pca953x_platform_data akita_ioexp = {
> - ? ? ? .gpio_base ? ? ? ? ? ? ?= AKITA_IOEXP_GPIO_BASE,
> -};
> +static void sharpslc_restart(char mode, const char *cmd)
> +{
> + ? ? ? /* Bootloader magic for a reboot */
> + ? ? ? if ((MSC0 & 0xffff0000) == 0x7ff00000)
> + ? ? ? ? ? ? ? MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
>
> -static struct i2c_board_info akita_i2c_board_info[] = {
> - ? ? ? {
> - ? ? ? ? ? ? ? .type ? ? ? ? ? = "max7310",
> - ? ? ? ? ? ? ? .addr ? ? ? ? ? = 0x18,
> - ? ? ? ? ? ? ? .platform_data ?= &akita_ioexp,
> - ? ? ? }, {
> - ? ? ? ? ? ? ? .type ? ? ? ? ? = "wm8750",
> - ? ? ? ? ? ? ? .addr ? ? ? ? ? = 0x1b,
> - ? ? ? },
> -};
> + ? ? ? sharpslc_poweroff();
> +}
>
> -static void __init akita_init(void)
> +static void __init sharpslc_init(void)
> ?{
> - ? ? ? spitz_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
> + ? ? ? init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
> + ? ? ? pm_power_off = sharpslc_poweroff;
> + ? ? ? arm_pm_restart = sharpslc_restart;
> +
> + ? ? ? PMCR = 0x00;
>
> - ? ? ? sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
> - ? ? ? sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
> + ? ? ? /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
> + ? ? ? PCFR |= PCFR_OPDE;
>
> - ? ? ? /* We just pretend the second element of the array doesn't exist */
> - ? ? ? spitz_pcmcia_config.num_devs = 1;
> - ? ? ? platform_scoop_config = &spitz_pcmcia_config;
> + ? ? ? pxa2xx_mfp_config(ARRAY_AND_SIZE(sharpslc_pin_config));
>
> - ? ? ? i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_board_info));
> + ? ? ? pxa_set_ffuart_info(NULL);
> + ? ? ? pxa_set_btuart_info(NULL);
> + ? ? ? pxa_set_stuart_info(NULL);
>
> - ? ? ? common_init();
> + ? ? ? sharpslc_spi_init();
> + ? ? ? sharpslc_scoop_init();
> + ? ? ? sharpslc_mkp_init();
> + ? ? ? sharpslc_keys_init();
> + ? ? ? sharpslc_leds_init();
> + ? ? ? sharpslc_mmc_init();
> + ? ? ? sharpslc_pcmcia_init();
> + ? ? ? sharpslc_irda_init();
> + ? ? ? sharpslc_uhc_init();
> + ? ? ? sharpslc_lcd_init();
> + ? ? ? sharpslc_nor_init();
> + ? ? ? sharpslc_nand_init();
> + ? ? ? sharpslc_i2c_init();
> ?}
> -#endif
>
> -static void __init fixup_spitz(struct machine_desc *desc,
> +static void __init sharpslc_fixup(struct machine_desc *desc,
> ? ? ? ? ? ? ? ?struct tag *tags, char **cmdline, struct meminfo *mi)
> ?{
> ? ? ? ?sharpsl_save_param();
> @@ -855,10 +982,10 @@ static void __init fixup_spitz(struct machine_desc *desc,
> ?MACHINE_START(SPITZ, "SHARP Spitz")
> ? ? ? ?.phys_io ? ? ? ?= 0x40000000,
> ? ? ? ?.io_pg_offst ? ?= (io_p2v(0x40000000) >> 18) & 0xfffc,
> - ? ? ? .fixup ? ? ? ? ?= fixup_spitz,
> + ? ? ? .fixup ? ? ? ? ?= sharpslc_fixup,
> ? ? ? ?.map_io ? ? ? ? = pxa_map_io,
> ? ? ? ?.init_irq ? ? ? = pxa27x_init_irq,
> - ? ? ? .init_machine ? = spitz_init,
> + ? ? ? .init_machine ? = sharpslc_init,
> ? ? ? ?.timer ? ? ? ? ?= &pxa_timer,
> ?MACHINE_END
> ?#endif
> @@ -867,10 +994,10 @@ MACHINE_END
> ?MACHINE_START(BORZOI, "SHARP Borzoi")
> ? ? ? ?.phys_io ? ? ? ?= 0x40000000,
> ? ? ? ?.io_pg_offst ? ?= (io_p2v(0x40000000) >> 18) & 0xfffc,
> - ? ? ? .fixup ? ? ? ? ?= fixup_spitz,
> + ? ? ? .fixup ? ? ? ? ?= sharpslc_fixup,
> ? ? ? ?.map_io ? ? ? ? = pxa_map_io,
> ? ? ? ?.init_irq ? ? ? = pxa27x_init_irq,
> - ? ? ? .init_machine ? = spitz_init,
> + ? ? ? .init_machine ? = sharpslc_init,
> ? ? ? ?.timer ? ? ? ? ?= &pxa_timer,
> ?MACHINE_END
> ?#endif
> @@ -879,10 +1006,10 @@ MACHINE_END
> ?MACHINE_START(AKITA, "SHARP Akita")
> ? ? ? ?.phys_io ? ? ? ?= 0x40000000,
> ? ? ? ?.io_pg_offst ? ?= (io_p2v(0x40000000) >> 18) & 0xfffc,
> - ? ? ? .fixup ? ? ? ? ?= fixup_spitz,
> + ? ? ? .fixup ? ? ? ? ?= sharpslc_fixup,
> ? ? ? ?.map_io ? ? ? ? = pxa_map_io,
> ? ? ? ?.init_irq ? ? ? = pxa27x_init_irq,
> - ? ? ? .init_machine ? = akita_init,
> + ? ? ? .init_machine ? = sharpslc_init,
> ? ? ? ?.timer ? ? ? ? ?= &pxa_timer,
> ?MACHINE_END
> ?#endif
> --
> 1.7.1
>
>


From eric.y.miao at gmail.com  Sun Jun 27 23:56:10 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 28 Jun 2010 11:56:10 +0800
Subject: [PATCH 1/3] pxa3xx: Fix HSIO bus x24 multiplier
In-Reply-To: <1277387833-5419-1-git-send-email-marek.vasut@gmail.com>
References: <1277387833-5419-1-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTikAcFNXb4dWGqQKq801pVfJ6bq4SQL_7LjCfs3p@mail.gmail.com>

On Thu, Jun 24, 2010 at 9:57 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> The value should be 24, not 0 in the possibilities array. It was just a silly
> mistake.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Applied.

Note, the 312MHz for HSS was not allowed previously until in recent
DM this is enabled, so it's not that "silly" :-)

> ---
> ?arch/arm/mach-pxa/pxa3xx.c | ? ?2 +-
> ?1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
> index f544e58..611622a 100644
> --- a/arch/arm/mach-pxa/pxa3xx.c
> +++ b/arch/arm/mach-pxa/pxa3xx.c
> @@ -52,7 +52,7 @@
> ?static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
>
> ?/* crystal frequency to HSIO bus frequency multiplier (HSS) */
> -static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
> +static unsigned char hss_mult[4] = { 8, 12, 16, 24 };
>
> ?/*
> ?* Get the clock frequency as reflected by CCSR and the turbo flag.
> --
> 1.7.1
>
>


From eric.y.miao at gmail.com  Mon Jun 28 00:38:16 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 28 Jun 2010 12:38:16 +0800
Subject: [PATCH 2/3] pxa2xx/cpufreq: Simplify DRI recomputation routine
In-Reply-To: <1277387833-5419-2-git-send-email-marek.vasut@gmail.com>
References: <1277387833-5419-1-git-send-email-marek.vasut@gmail.com> 
	<1277387833-5419-2-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTilIQOmzV5JNk63dQvCViFjYOASLuZ39AZKykf6Z@mail.gmail.com>

On Thu, Jun 24, 2010 at 9:57 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> This patch:
> 1) Simpifies the DRI recomputation routine by pulling out the common code
> 2) Fixes a bug in PXA27x DRI recomputation caused by incorrect parenthesis
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

Good catch, I've modified it a bit so it's more compact and reable below
and I'll apply this to the 'fix' branch.

diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
index 9e4d981..268a9bc 100644
--- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
+++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
@@ -256,13 +256,9 @@ static void init_sdram_rows(void)

 static u32 mdrefr_dri(unsigned int freq)
 {
-       u32 dri = 0;
+       u32 interval = freq * SDRAM_TREF / sdram_rows;

-       if (cpu_is_pxa25x())
-               dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
-       if (cpu_is_pxa27x())
-               dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
-       return dri;
+       return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
 }

 /* find a valid frequency point */


> ---
> ?arch/arm/mach-pxa/cpufreq-pxa2xx.c | ? ?9 +++++----
> ?1 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> index 9e4d981..bb5f21e 100644
> --- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> +++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> @@ -256,12 +256,13 @@ static void init_sdram_rows(void)
>
> ?static u32 mdrefr_dri(unsigned int freq)
> ?{
> - ? ? ? u32 dri = 0;
> + ? ? ? u32 dri = freq * SDRAM_TREF / sdram_rows;
>
> - ? ? ? if (cpu_is_pxa25x())
> - ? ? ? ? ? ? ? dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
> ? ? ? ?if (cpu_is_pxa27x())
> - ? ? ? ? ? ? ? dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
> + ? ? ? ? ? ? ? dri -= 31;
> +
> + ? ? ? dri /= 32;
> +
> ? ? ? ?return dri;
> ?}
>
> --
> 1.7.1
>
>


From ryan at bluewatersys.com  Mon Jun 28 00:39:14 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Mon, 28 Jun 2010 16:39:14 +1200
Subject: [PATCH 2/3] at91_udc: Add vbus polarity and polling mode
In-Reply-To: <1277699955-9931-1-git-send-email-ryan@bluewatersys.com>
References: <1277699955-9931-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1277699955-9931-3-git-send-email-ryan@bluewatersys.com>

Allow the vbus signal to optionally use polling. This is required if
the vbus signal is connected to an non-interrupting io expander for
example. If vbus is in polling mode, then it is assumed that the vbus
gpio may sleep. Also add an option to have vbus be an active low
signal. Both options are set in the platform data for the device.

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-at91/include/mach/board.h |    2 +
 drivers/usb/gadget/at91_udc.c           |   66 +++++++++++++++++++++++++------
 drivers/usb/gadget/at91_udc.h           |    2 +
 3 files changed, 57 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index df2ed84..58528aa 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -44,6 +44,8 @@
  /* USB Device */
 struct at91_udc_data {
 	u8	vbus_pin;		/* high == host powering us */
+	u8	vbus_active_low;	/* vbus polarity */
+	u8	vbus_polled;		/* Use polling, not interrupt */
 	u8	pullup_pin;		/* active == D+ pulled up */
 	u8	pullup_active_low;	/* true == pullup_pin is active low */
 };
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index eaa79c8..469a64c 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -76,6 +76,7 @@
 static const char driver_name [] = "at91_udc";
 static const char ep0name[] = "ep0";
 
+#define VBUS_POLL_TIMEOUT	msecs_to_jiffies(1000)
 
 #define at91_udp_read(dev, reg) \
 	__raw_readl((dev)->udp_baseaddr + (reg))
@@ -1556,20 +1557,49 @@ static struct at91_udc controller = {
 	/* ep6 and ep7 are also reserved (custom silicon might use them) */
 };
 
+static void at91_vbus_update(struct at91_udc *udc, unsigned value)
+{
+	if (udc->board.vbus_active_low)
+		value ^= 1;
+	if (value != udc->vbus)
+		at91_vbus_session(&udc->gadget, value);
+}
+
 static irqreturn_t at91_vbus_irq(int irq, void *_udc)
 {
 	struct at91_udc	*udc = _udc;
-	unsigned	value;
 
 	/* vbus needs at least brief debouncing */
 	udelay(10);
-	value = gpio_get_value(udc->board.vbus_pin);
-	if (value != udc->vbus)
-		at91_vbus_session(&udc->gadget, value);
+	at91_vbus_update(udc, gpio_get_value(udc->board.vbus_pin));
 
 	return IRQ_HANDLED;
 }
 
+static void at91_vbus_timer_work(struct work_struct *work)
+{
+	struct at91_udc *udc = container_of(work, struct at91_udc, 
+					    vbus_timer_work);
+
+	at91_vbus_update(udc, gpio_get_value_cansleep(udc->board.vbus_pin));
+
+	if (!timer_pending(&udc->vbus_timer))
+		mod_timer(&udc->vbus_timer, jiffies + VBUS_POLL_TIMEOUT);
+}
+
+static void at91_vbus_timer(unsigned long data)
+{
+	struct at91_udc *udc = (struct at91_udc *)data;
+
+	/*
+	 * If we are polling vbus it is likely that the gpio is on an
+	 * bus such as i2c or spi which may sleep, so schedule some work
+	 * to read the vbus gpio
+	 */
+	if (!work_pending(&udc->vbus_timer_work))
+		schedule_work(&udc->vbus_timer_work);
+}
+
 int usb_gadget_register_driver (struct usb_gadget_driver *driver)
 {
 	struct at91_udc	*udc = &controller;
@@ -1763,13 +1793,22 @@ static int __init at91udc_probe(struct platform_device *pdev)
 		 * Get the initial state of VBUS - we cannot expect
 		 * a pending interrupt.
 		 */
-		udc->vbus = gpio_get_value(udc->board.vbus_pin);
-		if (request_irq(udc->board.vbus_pin, at91_vbus_irq,
-				IRQF_DISABLED, driver_name, udc)) {
-			DBG("request vbus irq %d failed\n",
-					udc->board.vbus_pin);
-			retval = -EBUSY;
-			goto fail3;
+		if (udc->board.vbus_polled) {
+			udc->vbus = gpio_get_value_cansleep(udc->board.vbus_pin);
+			INIT_WORK(&udc->vbus_timer_work, at91_vbus_timer_work);
+			setup_timer(&udc->vbus_timer, at91_vbus_timer,
+				    (unsigned long)udc);		
+			mod_timer(&udc->vbus_timer,
+				  jiffies + VBUS_POLL_TIMEOUT);
+		} else {
+			udc->vbus = gpio_get_value(udc->board.vbus_pin);
+			if (request_irq(udc->board.vbus_pin, at91_vbus_irq,
+					IRQF_DISABLED, driver_name, udc)) {
+				DBG("request vbus irq %d failed\n",
+				    udc->board.vbus_pin);
+				retval = -EBUSY;
+				goto fail3;
+			}
 		}
 	} else {
 		DBG("no VBUS detection, assuming always-on\n");
@@ -1855,7 +1894,7 @@ static int at91udc_suspend(struct platform_device *pdev, pm_message_t mesg)
 		enable_irq_wake(udc->udp_irq);
 
 	udc->active_suspend = wake;
-	if (udc->board.vbus_pin > 0 && wake)
+	if (udc->board.vbus_pin > 0 && !udc->board.vbus_polled && wake)
 		enable_irq_wake(udc->board.vbus_pin);
 	return 0;
 }
@@ -1864,7 +1903,8 @@ static int at91udc_resume(struct platform_device *pdev)
 {
 	struct at91_udc *udc = platform_get_drvdata(pdev);
 
-	if (udc->board.vbus_pin > 0 && udc->active_suspend)
+	if (udc->board.vbus_pin > 0 && !udc->board.vbus_polled && 
+	    udc->active_suspend)
 		disable_irq_wake(udc->board.vbus_pin);
 
 	/* maybe reconnect to host; if so, clocks on */
diff --git a/drivers/usb/gadget/at91_udc.h b/drivers/usb/gadget/at91_udc.h
index c65d622..a1f4f54 100644
--- a/drivers/usb/gadget/at91_udc.h
+++ b/drivers/usb/gadget/at91_udc.h
@@ -144,6 +144,8 @@ struct at91_udc {
 	struct proc_dir_entry		*pde;
 	void __iomem			*udp_baseaddr;
 	int				udp_irq;
+	struct timer_list		vbus_timer;
+	struct work_struct		vbus_timer_work;
 };
 
 static inline struct at91_udc *to_udc(struct usb_gadget *g)
-- 
1.5.5.1



From ryan at bluewatersys.com  Mon Jun 28 00:39:12 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Mon, 28 Jun 2010 16:39:12 +1200
Subject: [PATCH 0/3] at91: Add support for Bluewater Systems Snapper 9260/9G20
	modules
Message-ID: <1277699955-9931-1-git-send-email-ryan@bluewatersys.com>

Repost of the Snapper 9260/9G20 module support patch series. These
patches add support for the Bluewater Systems Snapper 9260/9G20
modules. As a preliminary for the module support the following patches
are also included in this series:

 - Define NR_BUILTIN_GPIO for at91. The Snapper 9260/9G20 modules have
an io expander which requires this to be defined.
 - Add vbus polarity and polling mode to the at91 udc driver. The
Snapper 9260/9G20 modules have the udc vbus pin connected in inverse
polarity to a sleeping io expander gpio.

Ryan Mallon (3):
  AT91: Define NR_BUILTIN_GPIO
  at91_udc: Add vbus polarity and polling mode
  at91: Add support for Bluewater Systems Snapper 9260/9G20 modules

 arch/arm/mach-at91/Kconfig              |   11 ++
 arch/arm/mach-at91/Makefile             |    3 +
 arch/arm/mach-at91/board-snapper9260.c  |  189 +++++++++++++++++++++++++++++++
 arch/arm/mach-at91/include/mach/board.h |    2 +
 arch/arm/mach-at91/include/mach/gpio.h  |    1 +
 drivers/usb/gadget/at91_udc.c           |   66 +++++++++--
 drivers/usb/gadget/at91_udc.h           |    2 +
 7 files changed, 261 insertions(+), 13 deletions(-)
 create mode 100644 arch/arm/mach-at91/board-snapper9260.c



From ryan at bluewatersys.com  Mon Jun 28 00:39:13 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Mon, 28 Jun 2010 16:39:13 +1200
Subject: [PATCH 1/3] AT91: Define NR_BUILTIN_GPIO
In-Reply-To: <1277699955-9931-1-git-send-email-ryan@bluewatersys.com>
References: <1277699955-9931-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1277699955-9931-2-git-send-email-ryan@bluewatersys.com>

Add definition for NR_BUILTIN_GPIO for AT91 family

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-at91/include/mach/gpio.h |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/include/mach/gpio.h
index 04c91e3..bfdd8ab 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/include/mach/gpio.h
@@ -19,6 +19,7 @@
 #define PIN_BASE		NR_AIC_IRQS
 
 #define MAX_GPIO_BANKS		5
+#define NR_BUILTIN_GPIO		(PIN_BASE + (MAX_GPIO_BANKS * 32))
 
 /* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
 
-- 
1.5.5.1



From ryan at bluewatersys.com  Mon Jun 28 00:39:15 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Mon, 28 Jun 2010 16:39:15 +1200
Subject: [PATCH 3/3] at91: Add support for Bluewater Systems Snapper 9260/9G20
	modules
In-Reply-To: <1277699955-9931-1-git-send-email-ryan@bluewatersys.com>
References: <1277699955-9931-1-git-send-email-ryan@bluewatersys.com>
Message-ID: <1277699955-9931-4-git-send-email-ryan@bluewatersys.com>

Add support for Bluewater Systems Snapper 9260/9G20 modules

Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>
---
 arch/arm/mach-at91/Kconfig             |   11 ++
 arch/arm/mach-at91/Makefile            |    3 +
 arch/arm/mach-at91/board-snapper9260.c |  189 ++++++++++++++++++++++++++++++++
 3 files changed, 203 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-at91/board-snapper9260.c

diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 841eaf8..939bccd 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -366,6 +366,17 @@ config MACH_STAMP9G20
 
 endif
 
+if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
+comment "AT91SAM9260/AT91SAM9G20 boards"
+
+config MACH_SNAPPER_9260
+        bool "Bluewater Systems Snapper 9260/9G20 module"
+        help
+          Select this if you are using the Bluewater Systems Snapper 9260 or
+          Snapper 9G20 modules.
+          <http://www.bluewatersys.com/>
+endif
+
 # ----------------------------------------------------------
 
 if ARCH_AT91SAM9G45
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c1f821e..ca2ac00 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -66,6 +66,9 @@ obj-$(CONFIG_MACH_CPU9G20)	+= board-cpu9krea.o
 obj-$(CONFIG_MACH_STAMP9G20)	+= board-stamp9g20.o
 obj-$(CONFIG_MACH_PORTUXG20)	+= board-stamp9g20.o
 
+# AT91SAM9260/AT91SAM9G20 board-specific support
+obj-$(CONFIG_MACH_SNAPPER_9260)	+= board-snapper9260.o
+
 # AT91SAM9G45 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
 
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
new file mode 100644
index 0000000..91ed809
--- /dev/null
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -0,0 +1,189 @@
+/*
+ * linux/arch/arm/mach-at91/board-snapper9260.c
+ *
+ *  Copyright (C) 2010 Bluewater System Ltd
+ *
+ * Author: Andre Renaud <andre at bluewatersys.com>
+ * Author: Ryan Mallon  <ryan at bluewatersys.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/i2c/pca953x.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/at91sam9_smc.h>
+
+#include "sam9_smc.h"
+#include "generic.h"
+
+#define SNAPPER9260_IO_EXP_GPIO(x)	(NR_BUILTIN_GPIO + (x))
+
+static void __init snapper9260_map_io(void)
+{
+	at91sam9260_initialize(18432000);
+
+	/* Debug on ttyS0 */
+	at91_register_uart(0, 0, 0);
+	at91_set_serial_console(0);
+
+	at91_register_uart(AT91SAM9260_ID_US0, 1, 
+			   ATMEL_UART_CTS | ATMEL_UART_RTS);
+	at91_register_uart(AT91SAM9260_ID_US1, 2,
+			   ATMEL_UART_CTS | ATMEL_UART_RTS);	
+	at91_register_uart(AT91SAM9260_ID_US2, 3, 0);	
+}
+
+static void __init snapper9260_init_irq(void)
+{
+	at91sam9260_init_interrupts(NULL);
+}
+
+static struct at91_usbh_data __initdata snapper9260_usbh_data = {
+	.ports		= 2,
+};
+
+static struct at91_udc_data __initdata snapper9260_udc_data = {
+	.vbus_pin		= SNAPPER9260_IO_EXP_GPIO(5),
+	.vbus_active_low	= 1,
+	.vbus_polled		= 1,
+};
+
+static struct at91_eth_data snapper9260_macb_data = {
+	.is_rmii	= 1,
+};
+
+static struct mtd_partition __initdata snapper9260_nand_partitions[] = {
+	{
+		.name	= "Preboot",
+		.offset	= 0,
+		.size	= SZ_128K,
+	},
+	{
+		.name	= "Bootloader",
+		.offset	= MTDPART_OFS_APPEND,
+		.size	= SZ_256K,
+	},
+	{
+		.name	= "Environment",
+		.offset	= MTDPART_OFS_APPEND,
+		.size	= SZ_128K,
+	},
+	{
+		.name	= "Kernel",
+		.offset	= MTDPART_OFS_APPEND,
+		.size	= SZ_4M,
+	},
+	{
+		.name	= "Filesystem",
+		.offset	= MTDPART_OFS_APPEND,
+		.size	= MTDPART_SIZ_FULL,
+	},
+};
+
+static struct mtd_partition * __init 
+snapper9260_nand_partition_info(int size, int *num_partitions)
+{
+	*num_partitions = ARRAY_SIZE(snapper9260_nand_partitions);
+	return snapper9260_nand_partitions;
+}
+
+static struct atmel_nand_data __initdata snapper9260_nand_data = {
+	.ale		= 21,
+	.cle		= 22,
+	.rdy_pin	= AT91_PIN_PC13,
+	.partition_info	= snapper9260_nand_partition_info,
+	.bus_width_16	= 0,
+};
+
+static struct sam9_smc_config __initdata snapper9260_nand_smc_config = {
+	.ncs_read_setup		= 0,
+	.nrd_setup		= 0,
+	.ncs_write_setup	= 0,
+	.nwe_setup		= 0,
+
+	.ncs_read_pulse		= 5,
+	.nrd_pulse		= 2,
+	.ncs_write_pulse	= 5,
+	.nwe_pulse		= 2,
+	
+	.read_cycle		= 7,
+	.write_cycle		= 7,
+
+	.mode			= (AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+				   AT91_SMC_EXNWMODE_DISABLE),
+	.tdf_cycles		= 1,
+};
+
+static struct pca953x_platform_data snapper9260_io_expander_data = {
+	.gpio_base		= SNAPPER9260_IO_EXP_GPIO(0),
+};
+
+static struct i2c_board_info __initdata snapper9260_i2c_devices[] = {
+	{
+		/* IO expander */
+		I2C_BOARD_INFO("max7312", 0x28),
+		.platform_data = &snapper9260_io_expander_data,
+	},
+	{
+		/* Audio codec */
+		I2C_BOARD_INFO("tlv320aic23", 0x1a),
+	},
+	{
+		/* RTC */
+		I2C_BOARD_INFO("isl1208", 0x6f),
+	},
+};
+
+static void __init snapper9260_add_device_nand(void)
+{
+	at91_set_A_periph(AT91_PIN_PC14, 0);
+	sam9_smc_configure(3, &snapper9260_nand_smc_config);
+	at91_add_device_nand(&snapper9260_nand_data);
+}
+
+static void __init snapper9260_board_init(void)
+{
+	at91_add_device_i2c(snapper9260_i2c_devices,
+			    ARRAY_SIZE(snapper9260_i2c_devices));
+	at91_add_device_serial();
+	at91_add_device_usbh(&snapper9260_usbh_data);
+	at91_add_device_udc(&snapper9260_udc_data);
+	at91_add_device_eth(&snapper9260_macb_data);
+	at91_add_device_ssc(AT91SAM9260_ID_SSC, (ATMEL_SSC_TF | ATMEL_SSC_TK |
+						 ATMEL_SSC_TD | ATMEL_SSC_RD));
+	snapper9260_add_device_nand();
+}
+
+MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
+	.phys_io	= AT91_BASE_SYS,
+	.io_pg_offst	= (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+	.boot_params	= AT91_SDRAM_BASE + 0x100,
+	.timer		= &at91sam926x_timer,
+	.map_io		= snapper9260_map_io,
+	.init_irq	= snapper9260_init_irq,
+	.init_machine	= snapper9260_board_init,
+MACHINE_END
+
+
-- 
1.5.5.1



From eric.y.miao at gmail.com  Mon Jun 28 00:48:58 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 28 Jun 2010 12:48:58 +0800
Subject: [PATCH 3/4] pxa2xx/cpufreq: Fix PCMCIA frequency scaling
In-Reply-To: <alpine.LFD.2.00.1006241542380.24097@xanadu.home>
References: <1276840135-5982-1-git-send-email-marek.vasut@gmail.com> 
	<1276840135-5982-3-git-send-email-marek.vasut@gmail.com>
	<87mxulabaw.fsf@free.fr> 
	<201006242051.27790.marek.vasut@gmail.com>
	<20100624191208.GB7974@n2100.arm.linux.org.uk> 
	<alpine.LFD.2.00.1006241542380.24097@xanadu.home>
Message-ID: <AANLkTikcn4RTbyKe8i0I3QaPayZawTk7mIaqpIWP6_6B@mail.gmail.com>

On Fri, Jun 25, 2010 at 3:46 AM, Nicolas Pitre <nico at fluxnic.net> wrote:
> On Thu, 24 Jun 2010, Russell King - ARM Linux wrote:
>
>> On Thu, Jun 24, 2010 at 08:51:27PM +0200, Marek Vasut wrote:
>> > Dne St 23. ?ervna 2010 19:49:59 Robert Jarzmik napsal(a):
>> > > Marek Vasut <marek.vasut at gmail.com> writes:
>> > > > The MCxx values must be based off memory clock, not CPU core clock.
>> > > >
>> > > > This also fixes the bug where on some machines the LCD went crazy while
>> > > > using PCMCIA.
>> > >
>> > > That looks correct to me.
>> > >
>> > > Reviewed-by: Robert Jarzmik <robert.jarzmik at free.fr>
>> > >
>> > > Cheers.
>> > >
>> > > --
>> > > Robert
>> >
>> > Actually lemme rethink this ... it might still be incorrect.
>>
>> As Nicolas was the one who originally wrote that code, while he was
>> working for Montavista and interacting with Intel, I'd be surprised
>> if he didn't try finding out what the right answer is to that fixme.
>
> Well, I might have tried, or I might not have and this simply was never
> revisited. But I clearly don't remember any of the context anymore.
>
>> I suspect as the fixme remained that there was no clear answer.
>
> Whatever works in practice is probably the best answer at this point.
>

Fair enough. And this looks correct to me as well. Applied to 'fix'.


From eric.y.miao at gmail.com  Mon Jun 28 00:53:00 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 28 Jun 2010 12:53:00 +0800
Subject: [PATCH 3/3] pxa2xx/cpufreq: Fix PCMCIA frequency scaling
In-Reply-To: <1277387833-5419-3-git-send-email-marek.vasut@gmail.com>
References: <1277387833-5419-1-git-send-email-marek.vasut@gmail.com> 
	<1277387833-5419-3-git-send-email-marek.vasut@gmail.com>
Message-ID: <AANLkTil1i0RIW1-DizTnPHszKshRWIfj8BtJmgXg2jX6@mail.gmail.com>

On Thu, Jun 24, 2010 at 9:57 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> The MCxx values must be based off memory clock, not CPU core clock.
>
> This also fixes the bug where on some machines the LCD went crazy while using
> PCMCIA.
>
> Signed-off-by: Marek Vasut <marek.vasut at gmail.com>

+ Reviewed-by: Robert Jarzmik <robert.jarzmik at free.fr>

Applied to 'fix'.

> ---
> ?drivers/pcmcia/pxa2xx_base.c | ? ?5 ++---
> ?1 files changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/pcmcia/pxa2xx_base.c b/drivers/pcmcia/pxa2xx_base.c
> index df4532e..f370476 100644
> --- a/drivers/pcmcia/pxa2xx_base.c
> +++ b/drivers/pcmcia/pxa2xx_base.c
> @@ -178,7 +178,6 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned long val,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? struct cpufreq_freqs *freqs)
> ?{
> -#warning "it's not clear if this is right since the core CPU (N) clock has no effect on the memory (L) clock"
> ? ? ? ?switch (val) {
> ? ? ? ?case CPUFREQ_PRECHANGE:
> ? ? ? ? ? ? ? ?if (freqs->new > freqs->old) {
> @@ -186,7 +185,7 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "pre-updating\n",
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? freqs->new / 1000, (freqs->new / 100) % 10,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? freqs->old / 1000, (freqs->old / 100) % 10);
> - ? ? ? ? ? ? ? ? ? ? ? pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
> + ? ? ? ? ? ? ? ? ? ? ? pxa2xx_pcmcia_set_timing(skt);
> ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ?break;
>
> @@ -196,7 +195,7 @@ pxa2xx_pcmcia_frequency_change(struct soc_pcmcia_socket *skt,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? "post-updating\n",
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? freqs->new / 1000, (freqs->new / 100) % 10,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? freqs->old / 1000, (freqs->old / 100) % 10);
> - ? ? ? ? ? ? ? ? ? ? ? pxa2xx_pcmcia_set_mcxx(skt, freqs->new);
> + ? ? ? ? ? ? ? ? ? ? ? pxa2xx_pcmcia_set_timing(skt);
> ? ? ? ? ? ? ? ?}
> ? ? ? ? ? ? ? ?break;
> ? ? ? ?}
> --
> 1.7.1
>
>

From davem at davemloft.net  Mon Jun 28 00:57:25 2010
From: davem at davemloft.net (David Miller)
Date: Sun, 27 Jun 2010 21:57:25 -0700 (PDT)
Subject: [RFC 9/9] crypto: Add Samsung crypto engine driver
In-Reply-To: <4C27309B.7010905@gmail.com>
References: <4C129341.2060407@gmail.com>
	<20100626.210728.90806559.davem@davemloft.net>
	<4C27309B.7010905@gmail.com>
Message-ID: <20100627.215725.226777011.davem@davemloft.net>

From: Maurus Cuelenaere <mcuelenaere at gmail.com>
Date: Sun, 27 Jun 2010 13:06:03 +0200

> I'd go with a threaded interrupt handler in that case then, or do
> you also consider this as too much overhead?
> 
> I'll do some performance comparisons of threaded interrupt handler
> vs normal and go with the fastest.

Yes, best to just measure it in order to decide which is best.


From ext-mika.1.westerberg at nokia.com  Mon Jun 28 01:14:46 2010
From: ext-mika.1.westerberg at nokia.com (Mika Westerberg)
Date: Mon, 28 Jun 2010 08:14:46 +0300
Subject: [PATCH 3/3] add ARM crashdump support
In-Reply-To: <20100625.160544.125902258.igawa@mxs.nes.nec.co.jp>
References: <20100624163356.dbb849bc.igawa@mxs.nes.nec.co.jp>
	<20100624081915.GF29920@esdhcp04058.research.nokia.com>
	<20100625.083133.77342472.igawa@mxs.nes.nec.co.jp>
	<20100625.160544.125902258.igawa@mxs.nes.nec.co.jp>
Message-ID: <20100628051446.GG29920@esdhcp04058.research.nokia.com>

On Fri, Jun 25, 2010 at 09:05:44AM +0200, ext Masayuki Igawa wrote:
> 
> I've finished my tests(x86/x86_64). No problems were found.
> So I've merged and pushed these patches.

Thanks!

I just pulled your latest tree and tested on ARM -> works well.

Regards,
MW


From igawa at mxs.nes.nec.co.jp  Mon Jun 28 01:25:52 2010
From: igawa at mxs.nes.nec.co.jp (Masayuki Igawa)
Date: Mon, 28 Jun 2010 14:25:52 +0900 (JST)
Subject: [PATCH 3/3] add ARM crashdump support
In-Reply-To: <20100628051446.GG29920@esdhcp04058.research.nokia.com>
References: <20100625.083133.77342472.igawa@mxs.nes.nec.co.jp>
	<20100625.160544.125902258.igawa@mxs.nes.nec.co.jp>
	<20100628051446.GG29920@esdhcp04058.research.nokia.com>
Message-ID: <20100628.142552.80399420.igawa@mxs.nes.nec.co.jp>

Hi,

From: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
Subject: Re: [PATCH 3/3] add ARM crashdump support
Date: Mon, 28 Jun 2010 08:14:46 +0300
> I just pulled your latest tree and tested on ARM -> works well.

Thank you for your testing!
I'm glad to hear that.

Regards,
-- Masayuki Igawa


From avictor.za at gmail.com  Mon Jun 28 01:41:43 2010
From: avictor.za at gmail.com (avictor.za at gmail.com)
Date: Mon, 28 Jun 2010 07:41:43 +0200
Subject: [PATCH 1/3] AT91: Define NR_BUILTIN_GPIO
In-Reply-To: <1277699955-9931-2-git-send-email-ryan@bluewatersys.com>
References: <1277699955-9931-1-git-send-email-ryan@bluewatersys.com>
	<1277699955-9931-2-git-send-email-ryan@bluewatersys.com>
Message-ID: <AANLkTin3DLp5sizIdr7DEbfIgXrfNhl6vgqCscNR094d@mail.gmail.com>

hi Ryan,

> Add definition for NR_BUILTIN_GPIO for AT91 family
>
> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>

Acked-by: Andrew Victor <linux at maxim.org.za>


Please submit to Russell King's patch system.


From avictor.za at gmail.com  Mon Jun 28 01:47:51 2010
From: avictor.za at gmail.com (avictor.za at gmail.com)
Date: Mon, 28 Jun 2010 07:47:51 +0200
Subject: [PATCH 3/3] at91: Add support for Bluewater Systems Snapper 
	9260/9G20 modules
In-Reply-To: <1277699955-9931-4-git-send-email-ryan@bluewatersys.com>
References: <1277699955-9931-1-git-send-email-ryan@bluewatersys.com>
	<1277699955-9931-4-git-send-email-ryan@bluewatersys.com>
Message-ID: <AANLkTilz0JJMe_I0sofRrDrvnAx_TljnUjAA1jS-goe7@mail.gmail.com>

hi Ryan,

> Add support for Bluewater Systems Snapper 9260/9G20 modules

Acked-by: Andrew Victor <linux at maxim.org.za>


From lamiaposta71 at gmail.com  Mon Jun 28 02:44:46 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Mon, 28 Jun 2010 08:44:46 +0200
Subject: [PATCH] ASoC: DaVinci: Added support for cpu clocking I2S
Message-ID: <1277707487-3371-1-git-send-email-lamiaposta71@gmail.com>

From: Raffaele Recalcati <raffaele.recalcati at bticino.it>

    Added audio playback support with [frame sync master - clock master] mode
    and with [frame sync master - clock slave].

    1. SND_SOC_DAIFMT_CBS_CFS (the cpu generates clock and frame sync)
       I need to clarify how the McBSP is clocked internally.
       Reading sprufi3a-1.pdf (TMS320DM36x DMSoC Multichannel Buffered Serial
       Port (McBSP) Interface) at "2.5.3 Data Clock Generation" paragraph this
       info not appears really clear if we are in the case of "McBSP internal
       input clock".
       I hope some Ti developers can help me.
       There is a FIXME message in the patch.

       i2s_fast_clock switch can be used to have better approximate or
       symmetric waveforms.
       clk_input_pin board info can be used to select it depending on hw
       connections

    2. SND_SOC_DAIFMT_CBS_CFM (the cpu get clock from external pin
                               and generates frame sync)
       Clock slave can be important when the external codec need system clock
       and bit clock synchronized (tested with uda1345).

    3. We haven't changed the evmdm365 support (due also to CPLD that doesn't
                                                help to understand)
        We don't know in this mode if audio stereo works on evmdm365.
        Probably it does.

	This patch has been developed against the
		http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
	git tree and has been tested on bmx board (similar to dm365 evm, but using
	uda1345 as external audio codec).

Signed-off-by: Raffaele Recalcati <raffaele.recalcati at bticino.it>
Signed-off-by: Davide Bonfanti <davide.bonfanti at bticino.it>
---
 arch/arm/mach-davinci/include/mach/asp.h |   16 ++++
 sound/soc/davinci/davinci-i2s.c          |  126 ++++++++++++++++++++++++++----
 2 files changed, 128 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
index 834725f..f9b6da2 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -63,6 +63,16 @@ struct snd_platform_data {
 	unsigned sram_size_playback;
 	unsigned sram_size_capture;
 
+	/*
+	 * This define works when both clock and FS are output for the cpu
+	 * and makes clock very fast (FS is not simmetrical, but sampling
+	 * frequency is better approximated
+	 */
+	int i2s_fast_clock;
+
+	/* To be used when cpu gets clock from extenal pin */
+	int clk_input_pin;
+
 	/* McASP specific fields */
 	int tdm_slots;
 	u8 op_mode;
@@ -78,6 +88,12 @@ enum {
 	MCASP_VERSION_2,	/* DA8xx/OMAPL1x */
 };
 
+enum {
+	MCBSP_CLKR = 0,		/* DM365 */
+	MCBSP_CLKS,
+};
+
+
 #define INACTIVE_MODE	0
 #define TX_MODE		1
 #define RX_MODE		2
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index adadcd3..786ade6 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -68,16 +68,21 @@
 #define DAVINCI_MCBSP_RCR_RDATDLY(v)	((v) << 16)
 #define DAVINCI_MCBSP_RCR_RFIG		(1 << 18)
 #define DAVINCI_MCBSP_RCR_RWDLEN2(v)	((v) << 21)
+#define DAVINCI_MCBSP_RCR_RFRLEN2(v)	((v) << 24)
+#define DAVINCI_MCBSP_RCR_RPHASE	(1 << 31)
 
 #define DAVINCI_MCBSP_XCR_XWDLEN1(v)	((v) << 5)
 #define DAVINCI_MCBSP_XCR_XFRLEN1(v)	((v) << 8)
 #define DAVINCI_MCBSP_XCR_XDATDLY(v)	((v) << 16)
 #define DAVINCI_MCBSP_XCR_XFIG		(1 << 18)
 #define DAVINCI_MCBSP_XCR_XWDLEN2(v)	((v) << 21)
+#define DAVINCI_MCBSP_XCR_XFRLEN2(v)	((v) << 24)
+#define DAVINCI_MCBSP_XCR_XPHASE	(1 << 31)
 
 #define DAVINCI_MCBSP_SRGR_FWID(v)	((v) << 8)
 #define DAVINCI_MCBSP_SRGR_FPER(v)	((v) << 16)
 #define DAVINCI_MCBSP_SRGR_FSGM		(1 << 28)
+#define DAVINCI_MCBSP_SRGR_CLKSM	(1 << 29)
 
 #define DAVINCI_MCBSP_PCR_CLKRP		(1 << 0)
 #define DAVINCI_MCBSP_PCR_CLKXP		(1 << 1)
@@ -144,6 +149,11 @@ struct davinci_mcbsp_dev {
 	 * won't end up being swapped because of the underrun.
 	 */
 	unsigned enable_channel_combine:1;
+
+	int i2s_fast_clock;
+	unsigned int fmt;
+	int clk_div;
+	int clk_input_pin;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -254,10 +264,12 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
 	unsigned int pcr;
 	unsigned int srgr;
+	/* Attention srgr is updated by hw_params! */
 	srgr = DAVINCI_MCBSP_SRGR_FSGM |
 		DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) |
 		DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1);
 
+	dev->fmt = fmt;
 	/* set master/slave audio interface */
 	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 	case SND_SOC_DAIFMT_CBS_CFS:
@@ -268,11 +280,18 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 			DAVINCI_MCBSP_PCR_CLKRM;
 		break;
 	case SND_SOC_DAIFMT_CBM_CFS:
-		/* McBSP CLKR pin is the input for the Sample Rate Generator.
-		 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
-		pcr = DAVINCI_MCBSP_PCR_SCLKME |
-			DAVINCI_MCBSP_PCR_FSXM |
-			DAVINCI_MCBSP_PCR_FSRM;
+		pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
+		if (dev->clk_input_pin == MCBSP_CLKS)
+			pcr |= DAVINCI_MCBSP_PCR_CLKXM |
+				DAVINCI_MCBSP_PCR_CLKRM;
+		else
+			/*
+			 * McBSP CLKR pin is the input for the Sample Rate
+			 * Generator.
+			 * McBSP FSR and FSX are driven by the Sample Rate
+			 * Generator.
+			 */
+			pcr |= DAVINCI_MCBSP_PCR_SCLKME;
 		break;
 	case SND_SOC_DAIFMT_CBM_CFM:
 		/* codec is master */
@@ -372,6 +391,16 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 	return 0;
 }
 
+static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
+				int div_id, int div)
+{
+	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
+	int srgr;
+
+	dev->clk_div = div;
+	return 0;
+}
+
 static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 				 struct snd_pcm_hw_params *params,
 				 struct snd_soc_dai *dai)
@@ -380,11 +409,12 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 	struct davinci_pcm_dma_params *dma_params =
 					&dev->dma_params[substream->stream];
 	struct snd_interval *i = NULL;
-	int mcbsp_word_length;
-	unsigned int rcr, xcr, srgr;
+	int mcbsp_word_length, master;
+	unsigned int rcr, xcr, srgr, clk_div, freq, framesize;
 	u32 spcr;
 	snd_pcm_format_t fmt;
 	unsigned element_cnt = 1;
+	struct clk *clk;
 
 	/* general line settings */
 	spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG);
@@ -396,12 +426,56 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr);
 	}
 
-	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
-	srgr = DAVINCI_MCBSP_SRGR_FSGM;
-	srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
+	master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK;
+	fmt = params_format(params);
+	mcbsp_word_length = asp_word_length[fmt];
 
-	i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
-	srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
+	if (master == SND_SOC_DAIFMT_CBS_CFS) {
+		clk = clk_get(NULL, "pll1_sysclk6");
+		if (clk)
+			freq = clk_get_rate(clk);
+		freq = 122000000; /* FIXME ask to Texas */
+		srgr = DAVINCI_MCBSP_SRGR_FSGM |
+		       DAVINCI_MCBSP_SRGR_CLKSM;
+		srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
+						8 - 1);
+		if (dev->i2s_fast_clock) {
+			clk_div = 256;
+			do {
+				framesize = (freq / (--clk_div)) /
+					    params->rate_num *
+					    params->rate_den;
+			} while (((framesize < 33) || (framesize > 4095)) &&
+				 (clk_div));
+			clk_div--;
+			srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
+		} else {
+			/* symmetric waveforms */
+			clk_div = freq / (mcbsp_word_length * 16) /
+				  params->rate_num * params->rate_den;
+			srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
+							16 - 1);
+		}
+		clk_div &= 0xFF;
+		srgr |= clk_div;
+	} else if (master == SND_SOC_DAIFMT_CBM_CFS) {
+		/* Clock given on CLKS */
+		srgr = DAVINCI_MCBSP_SRGR_FSGM;
+		clk_div = dev->clk_div - 1;
+		srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
+		srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1);
+		clk_div &= 0xFF;
+		srgr |= clk_div;
+	} else {
+		i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS);
+		srgr = DAVINCI_MCBSP_SRGR_FSGM;
+		srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1);
+		pr_debug("%s - %d  FWID set: re-read srgr = %X\n",
+			__func__, __LINE__, snd_interval_value(i) - 1);
+
+		i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS);
+		srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1);
+	}
 	davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr);
 
 	rcr = DAVINCI_MCBSP_RCR_RFIG;
@@ -426,12 +500,29 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 			element_cnt = 1;
 			fmt = double_fmt[fmt];
 		}
+		if (master == SND_SOC_DAIFMT_CBS_CFS ||
+				master == SND_SOC_DAIFMT_CBS_CFM) {
+			rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0);
+			xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0);
+			rcr |= DAVINCI_MCBSP_RCR_RPHASE;
+			xcr |= DAVINCI_MCBSP_XCR_XPHASE;
+		} else {
+			rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1);
+			xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1);
+		}
 	}
 	dma_params->acnt = dma_params->data_type = data_type[fmt];
 	dma_params->fifo_level = 0;
 	mcbsp_word_length = asp_word_length[fmt];
-	rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
-	xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
+
+	if (master == SND_SOC_DAIFMT_CBS_CFS ||
+			master == SND_SOC_DAIFMT_CBS_CFM) {
+		rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0);
+		xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0);
+	} else {
+		rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1);
+		xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1);
+	}
 
 	rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) |
 		DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length);
@@ -442,6 +533,10 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr);
 	else
 		davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr);
+
+	pr_debug("%s - %d  srgr=%X\n", __func__, __LINE__, srgr);
+	pr_debug("%s - %d  xcr=%X\n", __func__, __LINE__, xcr);
+	pr_debug("%s - %d  rcr=%X\n", __func__, __LINE__, rcr);
 	return 0;
 }
 
@@ -500,6 +595,7 @@ static struct snd_soc_dai_ops davinci_i2s_dai_ops = {
 	.trigger	= davinci_i2s_trigger,
 	.hw_params	= davinci_i2s_hw_params,
 	.set_fmt	= davinci_i2s_set_dai_fmt,
+	.set_clkdiv	= davinci_i2s_dai_set_clkdiv,
 
 };
 
@@ -552,6 +648,8 @@ static int davinci_i2s_probe(struct platform_device *pdev)
 			pdata->sram_size_playback;
 		dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
 			pdata->sram_size_capture;
+		dev->i2s_fast_clock = pdata->i2s_fast_clock;
+		dev->clk_input_pin = pdata->clk_input_pin;
 	}
 	dev->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(dev->clk)) {
-- 
1.7.0.4



From lamiaposta71 at gmail.com  Mon Jun 28 02:46:22 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Mon, 28 Jun 2010 08:46:22 +0200
Subject: [PATCH] DaVinci: dm365: Added clockout2 management and set_sysclk_rate
Message-ID: <1277707582-3405-1-git-send-email-lamiaposta71@gmail.com>

From: Davide Bonfanti <davide.bonfanti at bticino.it>

    Added also possibility to set sysclk frequency.

    Added possibility to set clockout2 frequency.
    Clockout2 is a child of pll1_sysclk9, because they have
    the same pll divisor.

    This patch has been developed against the
    http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
    git tree and tested on bmx board.

Signed-off-by: Davide Bonfanti <davide.bonfanti at bticino.it>
Signed-off-by: Raffaele Recalcati <raffaele.recalcati at bticino.it>
---
 arch/arm/mach-davinci/clock.c              |  113 +++++++++++++++++++++++++++-
 arch/arm/mach-davinci/clock.h              |   14 ++++
 arch/arm/mach-davinci/dm365.c              |   23 +++++-
 arch/arm/mach-davinci/include/mach/clock.h |    3 +
 4 files changed, 146 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index 054c303..464c289 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -144,6 +144,69 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
 }
 EXPORT_SYMBOL(clk_set_rate);
 
+int clkout2_set_rate(struct clk *clk, unsigned long rate)
+{
+	unsigned long flags;
+	int ret = -EINVAL;
+	int i, err, min_err, i_min_err;
+	u32 regval;
+	struct pll_data *pll;
+	struct clk *parent = clk;
+
+	if (clk == NULL || IS_ERR(clk))
+		return ret;
+	if (!cpu_is_davinci_dm365())
+		return -ENODEV;
+
+	while (parent->parent->parent)
+		parent = parent->parent;
+
+	parent = clk->parent;
+
+	if (parent == clk)
+		return -EPERM;
+
+	pll = parent->pll_data;
+	regval = __raw_readl(IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE +
+			PERI_CLKCTL));
+
+	i_min_err = min_err = INT_MAX;
+	for (i = 0x0F; i > 0; i--) {
+		if (clk->set_rate) {
+			ret = clk_set_rate(clk, rate * i) ;
+			err = clk_get_rate(clk) - rate * i;
+			if (abs(min_err) > abs(err)) {
+				min_err = err;
+				i_min_err = i;
+			}
+		}
+	}
+	i = i_min_err;
+	ret = clk->set_rate(clk, rate * i) ;
+
+	regval &= ~(0x0F << 3);
+	regval |= (i-1) << 3;
+	regval |= 1 << CLOCKOUT2EN;
+	__raw_writel(regval, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE +
+			PERI_CLKCTL));
+	rate *= i;
+
+	spin_lock_irqsave(&clockfw_lock, flags);
+	if (ret == 0) {
+		if (clk->recalc)
+			clk->rate = clk->recalc(clk);
+		propagate_rate(clk);
+		regval &= ~(1 << CLOCKOUT2EN);
+		__raw_writel(regval, IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE +
+			PERI_CLKCTL));
+	} else
+		return -EINVAL;
+	spin_unlock_irqrestore(&clockfw_lock, flags);
+
+	return ret;
+}
+EXPORT_SYMBOL(clkout2_set_rate);
+
 int clk_set_parent(struct clk *clk, struct clk *parent)
 {
 	unsigned long flags;
@@ -254,7 +317,15 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
 	u32 v, plldiv;
 	struct pll_data *pll;
 	unsigned long rate = clk->rate;
+	struct clk *parent = clk;
+
+	if (clk == NULL || IS_ERR(clk))
+		return -EINVAL;
+	while (parent->parent->parent)
+		parent = parent->parent;
 
+	if (parent == clk)
+		return -EPERM;
 	/* If this is the PLL base clock, no more calculations needed */
 	if (clk->pll_data)
 		return rate;
@@ -262,13 +333,13 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
 	if (WARN_ON(!clk->parent))
 		return rate;
 
-	rate = clk->parent->rate;
+	rate = parent->rate;
+
 
 	/* Otherwise, the parent must be a PLL */
-	if (WARN_ON(!clk->parent->pll_data))
+	if (WARN_ON(!parent->pll_data))
 		return rate;
-
-	pll = clk->parent->pll_data;
+	pll = parent->pll_data;
 
 	/* If pre-PLL, source clock is before the multiplier and divider(s) */
 	if (clk->flags & PRE_PLL)
@@ -286,6 +357,7 @@ static unsigned long clk_sysclk_recalc(struct clk *clk)
 
 	return rate;
 }
+EXPORT_SYMBOL(clk_sysclk_recalc);
 
 static unsigned long clk_leafclk_recalc(struct clk *clk)
 {
@@ -433,6 +505,39 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
 }
 EXPORT_SYMBOL(davinci_set_pllrate);
 
+int set_sysclk_rate(struct clk *clk, unsigned long rate)
+{
+	u32 clk_freq_min, clk_freq_max, plldiv;
+	struct pll_data *pll;
+	struct clk *parent = clk;
+
+	while (parent->parent->parent)
+		parent = parent->parent;
+	if (parent == clk)
+		return -EPERM;
+
+	clk_freq_max = parent->rate;
+	pll = parent->pll_data;
+	if (clk->flags & PRE_PLL)
+		clk_freq_max = pll->input_rate;
+
+	if (!clk->div_reg)
+		return -EPERM;
+
+	clk_freq_min = clk_freq_max / 0x20;
+	if ((rate < clk_freq_min) || (rate > clk_freq_max))
+		return -EINVAL;
+
+	plldiv = clk_freq_max / rate ;
+	if ((clk_freq_max % rate) < (rate >> 1))
+		plldiv--;
+	__raw_writel(plldiv & 0x1F, pll->base + clk->div_reg);
+	__raw_writel(plldiv | 0x8000, pll->base + clk->div_reg);
+	clk->rate = rate;
+	return 0;
+}
+EXPORT_SYMBOL(set_sysclk_rate);
+
 int __init davinci_clk_init(struct clk_lookup *clocks)
   {
 	struct clk_lookup *c;
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 01e3648..74ba65f 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -50,6 +50,11 @@
 #define PLLDIV_EN       BIT(15)
 #define PLLDIV_RATIO_MASK 0x1f
 
+#define PERI_CLKCTL	0x48
+#define CLOCKOUT2EN	2
+#define CLOCKOUT1EN	1
+#define CLOCKOUT0EN	0
+
 /*
  * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
  * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
@@ -95,6 +100,14 @@ struct clk {
 	struct list_head	childnode;	/* parent's child list node */
 	struct pll_data         *pll_data;
 	u32                     div_reg;
+/*
+	u32		sec_div_reg;
+	u32		sec_div_reg_max;
+	u32		sec_div_reg_shift;
+	u32		out_enable_reg;
+	u32		out_enable_bit;
+*/
+
 	unsigned long (*recalc) (struct clk *);
 	int (*set_rate) (struct clk *clk, unsigned long rate);
 	int (*round_rate) (struct clk *clk, unsigned long rate);
@@ -121,6 +134,7 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
 
 extern struct platform_device davinci_wdt_device;
 extern void davinci_watchdog_reset(struct platform_device *);
+int set_sysclk_rate(struct clk *clk, unsigned long rate);
 
 #endif
 
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 42fd4a4..1e97c62 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -40,6 +40,15 @@
 #include "mux.h"
 
 #define DM365_REF_FREQ		24000000	/* 24 MHz on the DM365 EVM */
+#define PINMUX0		0x00
+#define PINMUX1		0x04
+#define PINMUX2		0x08
+#define PINMUX3		0x0c
+#define PINMUX4		0x10
+#define INTMUX		0x18
+#define EVTMUX		0x1c
+
+
 
 static struct pll_data pll1_data = {
 	.num		= 1,
@@ -124,6 +133,7 @@ static struct clk pll1_sysclk6 = {
 	.parent		= &pll1_clk,
 	.flags		= CLK_PLL,
 	.div_reg	= PLLDIV6,
+	.set_rate	= set_sysclk_rate,
 };
 
 static struct clk pll1_sysclk7 = {
@@ -147,6 +157,15 @@ static struct clk pll1_sysclk9 = {
 	.div_reg	= PLLDIV9,
 };
 
+static struct clk clkout2_clk = {
+	.name		= "clkout2",
+	.parent		= &pll1_sysclk9,
+	.flags		= CLK_PLL,
+	.div_reg	= PLLDIV9,
+	.set_rate       = set_sysclk_rate,
+};
+
+
 static struct clk pll2_clk = {
 	.name		= "pll2",
 	.parent		= &ref_clk,
@@ -421,6 +440,7 @@ static struct clk_lookup dm365_clks[] = {
 	CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
 	CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
 	CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
+	CLK(NULL, "clkout2", &clkout2_clk),
 	CLK(NULL, "pll2", &pll2_clk),
 	CLK(NULL, "pll2_aux", &pll2_aux_clk),
 	CLK(NULL, "clkout1", &clkout1_clk),
@@ -467,9 +487,6 @@ static struct clk_lookup dm365_clks[] = {
 
 /*----------------------------------------------------------------------*/
 
-#define INTMUX		0x18
-#define EVTMUX		0x1c
-
 
 static const struct mux_config dm365_pins[] = {
 #ifdef CONFIG_DAVINCI_MUX
diff --git a/arch/arm/mach-davinci/include/mach/clock.h b/arch/arm/mach-davinci/include/mach/clock.h
index a3b0402..4296080 100644
--- a/arch/arm/mach-davinci/include/mach/clock.h
+++ b/arch/arm/mach-davinci/include/mach/clock.h
@@ -18,4 +18,7 @@ struct clk;
 extern int clk_register(struct clk *clk);
 extern void clk_unregister(struct clk *clk);
 
+int clkout2_set_rate(struct clk *clk, unsigned long rate);
+
+
 #endif
-- 
1.7.0.4



From lamiaposta71 at gmail.com  Mon Jun 28 02:47:35 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Mon, 28 Jun 2010 08:47:35 +0200
Subject: [PATCH] spi: davinci: Added support for chip select using gpio
Message-ID: <1277707655-3468-1-git-send-email-lamiaposta71@gmail.com>

From: Raffaele Recalcati <raffaele.recalcati at bticino.it>

    It is not everytime possible, due to hardware constraints,
    to use the hw chip select available on spi port.
    So I add this possibility using a gpio as chip select.
    If controller_data variable is not null it is
    the gpio to be used as chip select.
    The default case is compatible with evmdm365.
    This patch has been developed against the
    http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
    git tree and has been tested on bmx board (similar to dm365 evm but with
    gpio as spi chip select).

Signed-off-by: Raffaele Recalcati <raffaele.recalcati at bticino.it>
Signed-off-by: Davide Bonfanti <davide.bonfanti at bticino.it>
---
 arch/arm/mach-davinci/dm365.c |   10 ++++++----
 drivers/spi/davinci_spi.c     |   27 ++++++++++++++++++---------
 2 files changed, 24 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index a146849..42fd4a4 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -677,10 +677,12 @@ void __init dm365_init_spi0(unsigned chipselect_mask,
 	davinci_cfg_reg(DM365_SPI0_SDO);
 
 	/* not all slaves will be wired up */
-	if (chipselect_mask & BIT(0))
-		davinci_cfg_reg(DM365_SPI0_SDENA0);
-	if (chipselect_mask & BIT(1))
-		davinci_cfg_reg(DM365_SPI0_SDENA1);
+	if  (!((unsigned long) info->controller_data)) {
+		if (chipselect_mask & BIT(0))
+			davinci_cfg_reg(DM365_SPI0_SDENA0);
+		if (chipselect_mask & BIT(1))
+			davinci_cfg_reg(DM365_SPI0_SDENA1);
+	}
 
 	spi_register_board_info(info, len);
 
diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
index 95afb6b..621ae46 100644
--- a/drivers/spi/davinci_spi.c
+++ b/drivers/spi/davinci_spi.c
@@ -29,6 +29,7 @@
 #include <linux/spi/spi_bitbang.h>
 #include <linux/slab.h>
 
+#include <mach/gpio.h>
 #include <mach/spi.h>
 #include <mach/edma.h>
 
@@ -270,18 +271,26 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
 	pdata = davinci_spi->pdata;
 
 	/*
-	 * Board specific chip select logic decides the polarity and cs
-	 * line for the controller
-	 */
+	* Board specific chip select logic decides the polarity and cs
+	* line for the controller
+	*/
 	if (value == BITBANG_CS_INACTIVE) {
-		set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);
-
-		data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
-		iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
-
+		if  ((unsigned long) spi->controller_data) {
+			gpio_set_value(spi->controller_data, \
+				!(spi->mode & SPI_CS_HIGH));
+		} else {
+			set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);
+
+			data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
+			iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
+		}
 		while ((ioread32(davinci_spi->base + SPIBUF)
-					& SPIBUF_RXEMPTY_MASK) == 0)
+				& SPIBUF_RXEMPTY_MASK) == 0)
 			cpu_relax();
+	} else {
+		if  ((unsigned long) spi->controller_data)
+			gpio_set_value(spi->controller_data, \
+				(spi->mode & SPI_CS_HIGH));
 	}
 }
 
-- 
1.7.0.4



From m.szyprowski at samsung.com  Mon Jun 28 02:01:40 2010
From: m.szyprowski at samsung.com (Marek Szyprowski)
Date: Mon, 28 Jun 2010 08:01:40 +0200
Subject: S3C2416 fixes (gpiolib, SDHCI, compilation without FB device)
In-Reply-To: <4C248B23.7060905@gmail.com>
References: <1277212585-25605-1-git-send-email-jekhor@gmail.com>
	<4C248B23.7060905@gmail.com>
Message-ID: <000001cb1687$638b2310$2aa16930$%szyprowski@samsung.com>

Hello,

On Friday, June 25, 2010 12:56 PM Darius Augulis wrote:

> On 06/22/2010 04:16 PM, Yauhen Kharuzhy wrote:
> > This patch series fixes SDHCI on S3C2416. I got SD card working with this
> patches
> > and with patches for GPIO card detection support by Marek Szyprowski.
> >
> 
> Unfortunately I did not get SD card working with these patches. I'm
> using custom board, not SMDK2416, but SD slot connection and schematics
> are the same like in SMDK2416. I've tried to debug a bit this problem
> and this is what I got: kernel do detection of card insert/remove,
> driver prints messages:
> 
> s3c-sdhci s3c-sdhci.1: card inserted.
> s3c-sdhci s3c-sdhci.1: card removed.
> 
> Then I put some printk in s3c-sdhci driver and MMC core and found that
> mmc_rescan() is called only once at startup and no more when
> inserting/removing SD card. Also mmc_rescan() stops at that point where
> mmc_power_up() is called and does not return. And mmc_power_up() stops
> where mmc_delay(10) is called and does not return too.
> Every time when inserting/removing SD card only functions
> sdhci_tasklet_card() and mmc_detect_change() are called, and nothing
> happens. Kernel doesn't detect the card inserted.
> Maybe this info could help to debug where the problem is - in my custom
> board or in your patches?

Have you tried with polled card detection method (SDHCI_CD_NONE)? If it
doesn't work I suspect something with the hardware. Checking with mmc debug
enabled might also help figuring this issue out.

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center




From adrian.hunter at nokia.com  Mon Jun 28 03:25:15 2010
From: adrian.hunter at nokia.com (Adrian Hunter)
Date: Mon, 28 Jun 2010 10:25:15 +0300
Subject: [PATCH] MMC: remove regulator refcount fiddling in mmc core
In-Reply-To: <1277392337-27627-1-git-send-email-linus.walleij@stericsson.com>
References: <1277392337-27627-1-git-send-email-linus.walleij@stericsson.com>
Message-ID: <4C284E5B.503@nokia.com>

Linus Walleij wrote:
> Currently the mmc_regulator_set_ocr() fiddles with the regulator
> refcount by selectively calling regulator_[enable|disable]
> depending on the state of the regulator. This will confuse the
> reference count if case the regulator is for example shared with
> other MMC slots or user for other stuff than the MMC card.
> 
> Push regulator_[enable|disable] out into the MMC host drivers
> and remove this from the MMC core so the reference count can be
> trusted.

That is not a technical reason.  It would be better to provide
more regulator support in core so there is less duplication in
the drivers.

At least it should be a separate patch.

> 
> Cc: Andrew Morton <akpm at linux-foundation.org>
> Cc: Liam Girdwood <lrg at slimlogic.co.uk>
> Cc: Mark Brown <broonie at opensource.wolfsonmicro.com>
> Cc: Tony Lindgren <tony at atomide.com>
> Cc: Adrian Hunter <adrian.hunter at nokia.com>
> Cc: Robert Jarzmik <robert.jarzmik at free.fr>
> Cc: Sundar Iyer <sundar.iyer at stericsson.com>
> Cc: Bengt Jonsson <bengt.jonsson at stericsson.com>
> Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
> ---
> This has been regression compiled for U300, OMAP3, PXA3XX
> defconfigs, tested on U300.
> 
> We're facing problems with our regulator reference counters if
> this is not fixed.
> ---
>  drivers/mmc/core/core.c       |   66 ++++++++++++++++++-----------------------
>  drivers/mmc/host/mmci.c       |   10 ++++--
>  drivers/mmc/host/omap_hsmmc.c |   40 ++++++++++++++++++------
>  drivers/mmc/host/pxamci.c     |   17 ++++++++--
>  4 files changed, 78 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
> index 569e94d..904f245 100644
> --- a/drivers/mmc/core/core.c
> +++ b/drivers/mmc/core/core.c
> @@ -784,47 +784,39 @@ int mmc_regulator_set_ocr(struct regulator *supply, unsigned short vdd_bit)
>  {
>  	int			result = 0;
>  	int			min_uV, max_uV;
> -	int			enabled;
> +	int			tmp;
> +	int			voltage;
>  
> -	enabled = regulator_is_enabled(supply);
> -	if (enabled < 0)
> -		return enabled;
> -
> -	if (vdd_bit) {
> -		int		tmp;
> -		int		voltage;
> -
> -		/* REVISIT mmc_vddrange_to_ocrmask() may have set some
> -		 * bits this regulator doesn't quite support ... don't
> -		 * be too picky, most cards and regulators are OK with
> -		 * a 0.1V range goof (it's a small error percentage).
> -		 */
> -		tmp = vdd_bit - ilog2(MMC_VDD_165_195);
> -		if (tmp == 0) {
> -			min_uV = 1650 * 1000;
> -			max_uV = 1950 * 1000;
> -		} else {
> -			min_uV = 1900 * 1000 + tmp * 100 * 1000;
> -			max_uV = min_uV + 100 * 1000;
> -		}
> -
> -		/* avoid needless changes to this voltage; the regulator
> -		 * might not allow this operation
> -		 */
> -		voltage = regulator_get_voltage(supply);
> -		if (voltage < 0)
> -			result = voltage;
> -		else if (voltage < min_uV || voltage > max_uV)
> -			result = regulator_set_voltage(supply, min_uV, max_uV);
> -		else
> -			result = 0;
> +	if (!vdd_bit)
> +		return 0;
>  
> -		if (result == 0 && !enabled)
> -			result = regulator_enable(supply);
> -	} else if (enabled) {
> -		result = regulator_disable(supply);
> +	/*
> +	 * REVISIT mmc_vddrange_to_ocrmask() may have set some
> +	 * bits this regulator doesn't quite support ... don't
> +	 * be too picky, most cards and regulators are OK with
> +	 * a 0.1V range goof (it's a small error percentage).
> +	 */
> +	tmp = vdd_bit - ilog2(MMC_VDD_165_195);
> +	if (tmp == 0) {
> +		min_uV = 1650 * 1000;
> +		max_uV = 1950 * 1000;
> +	} else {
> +		min_uV = 1900 * 1000 + tmp * 100 * 1000;
> +		max_uV = min_uV + 100 * 1000;
>  	}
>  
> +	/*
> +	 * Avoid needless changes to this voltage; the regulator
> +	 * might not allow this operation
> +	 */
> +	voltage = regulator_get_voltage(supply);
> +	if (voltage < 0)
> +		result = voltage;
> +	else if (voltage < min_uV || voltage > max_uV)
> +		result = regulator_set_voltage(supply, min_uV, max_uV);
> +	else
> +		result = 0;
> +
>  	return result;
>  }
>  EXPORT_SYMBOL(mmc_regulator_set_ocr);
> diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
> index 4917af9..5f530b1 100644
> --- a/drivers/mmc/host/mmci.c
> +++ b/drivers/mmc/host/mmci.c
> @@ -467,15 +467,17 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>  
>  	switch (ios->power_mode) {
>  	case MMC_POWER_OFF:
> -		if(host->vcc &&
> -		   regulator_is_enabled(host->vcc))
> +		if (host->vcc)
>  			regulator_disable(host->vcc);
>  		break;
>  	case MMC_POWER_UP:
>  #ifdef CONFIG_REGULATOR
> -		if (host->vcc)
> -			/* This implicitly enables the regulator */
> +		if (host->vcc) {
> +			if (regulator_enable(host->vcc))
> +				dev_err(mmc_dev(mmc),
> +					"could not enable regulator\n");
>  			mmc_regulator_set_ocr(host->vcc, ios->vdd);
> +		}
>  #endif
>  		/*
>  		 * The translate_vdd function is not used if you have
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index b032828..d8d07e1 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -247,10 +247,17 @@ static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
>  	if (mmc_slot(host).before_set_reg)
>  		mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
>  
> -	if (power_on)
> -		ret = mmc_regulator_set_ocr(host->vcc, vdd);
> -	else
> -		ret = mmc_regulator_set_ocr(host->vcc, 0);
> +	if (power_on) {
> +		ret = regulator_enable(host->vcc);
> +		if (ret)
> +			dev_err(dev, "could not enable regulator\n");
> +		else
> +			ret = mmc_regulator_set_ocr(host->vcc, vdd);
> +	} else {
> +		ret = regulator_disable(host->vcc);
> +		if (ret)
> +			dev_err(dev, "could not disable regulator\n");
> +	}

Enabling the regulator before setting the voltage seems like it could
create problems, for example, enabling at an invalid voltage before
ramping to the correct voltage.  Also, while regulator_enable typically
waits for the regulator to stablize, regulator_set_voltage typically
does not.

The original code was the other way around.

>  
>  	if (mmc_slot(host).after_set_reg)
>  		mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
> @@ -289,7 +296,11 @@ static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
>  	 * chips/cards need an interface voltage rail too.
>  	 */
>  	if (power_on) {
> -		ret = mmc_regulator_set_ocr(host->vcc, vdd);
> +		ret = regulator_enable(host->vcc);
> +		if (ret < 0)
> +			dev_err(dev, "could not enable regulator\n");
> +		else
> +			ret = mmc_regulator_set_ocr(host->vcc, vdd);
>  		/* Enable interface voltage rail, if needed */
>  		if (ret == 0 && host->vcc_aux) {
>  			ret = regulator_enable(host->vcc_aux);
> @@ -297,10 +308,15 @@ static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
>  				ret = mmc_regulator_set_ocr(host->vcc, 0);
>  		}
>  	} else {
> +		/* Shut down the rail */
>  		if (host->vcc_aux)
>  			ret = regulator_disable(host->vcc_aux);
> -		if (ret == 0)
> -			ret = mmc_regulator_set_ocr(host->vcc, 0);
> +		if (ret == 0) {
> +			/* Then proeeed to shut down the local regulator */
> +			ret = regulator_disable(host->vcc);
> +			if (ret == 0)
> +				ret = mmc_regulator_set_ocr(host->vcc, 0);
> +		}
>  	}
>  
>  	if (mmc_slot(host).after_set_reg)
> @@ -340,10 +356,14 @@ static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
>  
>  	if (cardsleep) {
>  		/* VCC can be turned off if card is asleep */
> -		if (sleep)
> -			err = mmc_regulator_set_ocr(host->vcc, 0);
> -		else
> +		if (sleep) {
> +			err = regulator_disable(host->vcc);
> +		} else {
> +			err = regulator_enable(host->vcc);
> +			if (err)
> +				return err;
>  			err = mmc_regulator_set_ocr(host->vcc, vdd);
> +		}
>  	} else
>  		err = regulator_set_mode(host->vcc, mode);
>  	if (err)
> diff --git a/drivers/mmc/host/pxamci.c b/drivers/mmc/host/pxamci.c
> index 0a4e43f..b7e0216 100644
> --- a/drivers/mmc/host/pxamci.c
> +++ b/drivers/mmc/host/pxamci.c
> @@ -99,13 +99,22 @@ static inline void pxamci_init_ocr(struct pxamci_host *host)
>  	}
>  }
>  
> -static inline void pxamci_set_power(struct pxamci_host *host, unsigned int vdd)
> +static inline void pxamci_set_power(struct pxamci_host *host,
> +				    unsigned char power_mode,
> +				    unsigned int vdd)
>  {
>  	int on;
>  
>  #ifdef CONFIG_REGULATOR
> -	if (host->vcc)
> -		mmc_regulator_set_ocr(host->vcc, vdd);
> +	if (host->vcc) {
> +		if (power_mode == MMC_POWER_UP) {
> +			if (regulator_enable(host->vcc))
> +				dev_err(mmc_dev(host->mmc),
> +					"could not enable regulator\n");
> +			mmc_regulator_set_ocr(host->vcc, vdd);
> +		} else if (power_mode == MMC_POWER_OFF)
> +			regulator_disable(host->vcc);
> +	}
>  #endif
>  	if (!host->vcc && host->pdata &&
>  	    gpio_is_valid(host->pdata->gpio_power)) {
> @@ -492,7 +501,7 @@ static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
>  	if (host->power_mode != ios->power_mode) {
>  		host->power_mode = ios->power_mode;
>  
> -		pxamci_set_power(host, ios->vdd);
> +		pxamci_set_power(host, ios->power_mode, ios->vdd);
>  
>  		if (ios->power_mode == MMC_POWER_ON)
>  			host->cmdat |= CMDAT_INIT;



From p.osciak at samsung.com  Mon Jun 28 04:08:48 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:48 +0200
Subject: [PATCH v3 02/12] s3c-fb: Correct FRAMESEL1 bitfield defines for
	VIDINTCON0 register
In-Reply-To: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1277712538-23188-3-git-send-email-p.osciak@samsung.com>

FRAMESEL1 bitfield starts on 13th bit, not on 14th.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-samsung/include/plat/regs-fb.h |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index f4259e5..ac10013 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -292,11 +292,11 @@
 #define VIDINTCON0_FRAMESEL0_ACTIVE		(0x2 << 15)
 #define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)
 
-#define VIDINTCON0_FRAMESEL1			(1 << 14)
-#define VIDINTCON0_FRAMESEL1_NONE		(0x0 << 14)
-#define VIDINTCON0_FRAMESEL1_BACKPORCH		(0x1 << 14)
-#define VIDINTCON0_FRAMESEL1_VSYNC		(0x2 << 14)
-#define VIDINTCON0_FRAMESEL1_FRONTPORCH		(0x3 << 14)
+#define VIDINTCON0_FRAMESEL1			(1 << 13)
+#define VIDINTCON0_FRAMESEL1_NONE		(0x0 << 13)
+#define VIDINTCON0_FRAMESEL1_BACKPORCH		(0x1 << 13)
+#define VIDINTCON0_FRAMESEL1_VSYNC		(0x2 << 13)
+#define VIDINTCON0_FRAMESEL1_FRONTPORCH		(0x3 << 13)
 
 #define VIDINTCON0_INT_FRAME			(1 << 12)
 #define VIDINTCON0_FIFIOSEL_MASK		(0x7f << 5)
-- 
1.7.1.569.g6f426



From p.osciak at samsung.com  Mon Jun 28 04:08:51 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:51 +0200
Subject: [PATCH v3 05/12] s3c-fb: Add support for display panning
In-Reply-To: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1277712538-23188-6-git-send-email-p.osciak@samsung.com>

Supports all bpp modes.

The PRTCON register is used to disable in-hardware updates of registers
that store start and end addresses of framebuffer memory. This prevents
display corruption in case we do not make it before VSYNC with updating
them atomically. With this feature there is no need to wait for a VSYNC
interrupt before each such update.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-samsung/include/plat/regs-fb.h |    5 ++
 drivers/video/s3c-fb.c                       |   71 ++++++++++++++++++++++++++
 2 files changed, 76 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index ac10013..f454e32 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -112,6 +112,11 @@
 #define VIDCON2_ORGYCbCr			(1 << 8)
 #define VIDCON2_YUVORDCrCb			(1 << 7)
 
+/* PRTCON (S3C6410, S5PC100) */
+
+#define PRTCON					(0x0c)
+#define PRTCON_PROTECT				(1 << 11)
+
 /* VIDTCON0 */
 
 #define VIDTCON0_VBPDE_MASK			(0xff << 24)
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 59ac76a..4f3680d 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -71,6 +71,7 @@ struct s3c_fb;
  * @buf_end: Offset of buffer end registers.
  * @osd: The base for the OSD registers.
  * @palette: Address of palette memory, or 0 if none.
+ * @has_prtcon: Set if has PRTCON register.
  */
 struct s3c_fb_variant {
 	unsigned int	is_2443:1;
@@ -85,6 +86,8 @@ struct s3c_fb_variant {
 	unsigned short	osd;
 	unsigned short	osd_stride;
 	unsigned short	palette[S3C_FB_MAX_WIN];
+
+	unsigned int	has_prtcon:1;
 };
 
 /**
@@ -379,6 +382,9 @@ static int s3c_fb_set_par(struct fb_info *info)
 
 	info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
 
+	info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
+	info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
+
 	/* disable the window whilst we update it */
 	writel(0, regs + WINCON(win_no));
 
@@ -735,6 +741,66 @@ static int s3c_fb_blank(int blank_mode, struct fb_info *info)
 	return 0;
 }
 
+/**
+ * s3c_fb_pan_display() - Pan the display.
+ *
+ * Note that the offsets can be written to the device at any time, as their
+ * values are latched at each vsync automatically. This also means that only
+ * the last call to this function will have any effect on next vsync, but
+ * there is no need to sleep waiting for it to prevent tearing.
+ *
+ * @var: The screen information to verify.
+ * @info: The framebuffer device.
+ */
+static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
+			      struct fb_info *info)
+{
+	struct s3c_fb_win *win	= info->par;
+	struct s3c_fb *sfb	= win->parent;
+	void __iomem *buf	= sfb->regs + win->index * 8;
+	unsigned int start_byte_offset, end_byte_offset;
+
+	/* Offset in bytes to the start of the displayed area */
+	start_byte_offset = var->yoffset * info->fix.line_length;
+	/* X offset depends on the current bpp */
+	if (info->var.bits_per_pixel >= 8) {
+		start_byte_offset +=
+			var->xoffset * (info->var.bits_per_pixel >> 3);
+	} else {
+		switch (info->var.bits_per_pixel) {
+		case 4:
+			start_byte_offset += var->xoffset >> 1;
+			break;
+		case 2:
+			start_byte_offset += var->xoffset >> 2;
+			break;
+		case 1:
+			start_byte_offset += var->xoffset >> 3;
+			break;
+		default:
+			dev_err(sfb->dev, "invalid bpp\n");
+			return -EINVAL;
+		}
+	}
+	/* Offset in bytes to the end of the displayed area */
+	end_byte_offset = start_byte_offset + var->yres * info->fix.line_length;
+
+	/* Temporarily turn off per-vsync update from shadow registers until
+	 * both start and end addresses are updated to prevent corruption */
+	if (sfb->variant.has_prtcon)
+		writel(PRTCON_PROTECT, sfb->regs + PRTCON);
+
+	writel(info->fix.smem_start + start_byte_offset,
+		buf + sfb->variant.buf_start);
+	writel(info->fix.smem_start + end_byte_offset,
+		buf + sfb->variant.buf_end);
+
+	if (sfb->variant.has_prtcon)
+		writel(0, sfb->regs + PRTCON);
+
+	return 0;
+}
+
 static struct fb_ops s3c_fb_ops = {
 	.owner		= THIS_MODULE,
 	.fb_check_var	= s3c_fb_check_var,
@@ -744,6 +810,7 @@ static struct fb_ops s3c_fb_ops = {
 	.fb_fillrect	= cfb_fillrect,
 	.fb_copyarea	= cfb_copyarea,
 	.fb_imageblit	= cfb_imageblit,
+	.fb_pan_display	= s3c_fb_pan_display,
 };
 
 /**
@@ -1243,6 +1310,8 @@ static struct s3c_fb_driverdata s3c_fb_data_64xx __devinitdata = {
 			[3] = 0x320,
 			[4] = 0x340,
 		},
+
+		.has_prtcon	= 1,
 	},
 	.win[0]	= &s3c_fb_data_64xx_wins[0],
 	.win[1]	= &s3c_fb_data_64xx_wins[1],
@@ -1271,6 +1340,8 @@ static struct s3c_fb_driverdata s3c_fb_data_s5pc100 __devinitdata = {
 			[3] = 0x3000,
 			[4] = 0x3400,
 		},
+
+		.has_prtcon	= 1,
 	},
 	.win[0]	= &s3c_fb_data_64xx_wins[0],
 	.win[1]	= &s3c_fb_data_64xx_wins[1],
-- 
1.7.1.569.g6f426



From p.osciak at samsung.com  Mon Jun 28 04:08:46 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:46 +0200
Subject: [PATCH v3 0/12] Various s3c-fb updates
Message-ID: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>

Hello,

this series is rebased onto Ben Dook's framebuffer branch available at:
git://git.fluff.org/bjdooks/linux.git dev/s3c-fb

The main changes are the addition of an ability to wait for VSYNC and
display panning and a better support for S5PV210 SoCs. A number of bugs
has also been fixed.

The first patch attempts to fix some NULL pointer dereferences in case
of a failed framebuffer memory allocation attempt. This is a quick fix,
so please treat it more as an indication of what may be wrong with the
code in the probe function and not as something to merge.

Patches 3-4 add "new style" device name initialization for various
S3C/S5P devices. The 4th patch also separates S5PC100 and S5PV210 as
their framebuffer registers sets differ.

Patches 8, 10 add shadow register update locking (S3C6410+)
Patch 12 Adds support for DMA channel control found on S5PV210+

Patches 7, 9 and 11 are pure bugfixes.

Changes in v3:
- new patches:
  * fixing a section mismatch error
  * adding support for DMA channel control (enable/disable) found on S5PV210
  * disabling shadow register updates during set_par

- unified function for disabling register updates
- no need to initialize names for 64xx-type framebuffers (is being set as
  default anyway)
- updated to the new version of Ben's branch
- minor fixes

Changes in v2:
- added SHADOWCON register support found on S3C6410 and S5PC100 for disabling
  shadow register updates
- fixed osd and alpha register handling (different configurations for different
  machines)

The series includes:
[PATCH v3 01/12] s3c-fb: Fix various null references on framebuffer memory alloc failure
[PATCH v3 02/12] s3c-fb: Correct FRAMESEL1 bitfield defines for VIDINTCON0 register
[PATCH v3 03/12] s3c-fb: Separate S5PC100 and S5PV210 framebuffer driver data structures
[PATCH v3 04/12] s3c-fb: Add device name initialization
[PATCH v3 05/12] s3c-fb: Add support for display panning
[PATCH v3 06/12] s3c-fb: Add wait for VSYNC ioctl
[PATCH v3 07/12] s3c-fb: window 3 of 64xx+ does not have an osd_d register
[PATCH v3 08/12] s3c-fb: Add SHADOWCON shadow register locking support for S5PV210
[PATCH v3 09/12] s3c-fb: Correct window osd size and alpha register handling
[PATCH v3 10/12] s3c-fb: Protect window-specific registers during updates
[PATCH v3 11/12] s3c-fb: fix section mismatch
[PATCH v3 12/12] s3c-fb: Add support for DMA channel control on S5PV210

Best regards
--
Pawel Osciak
Linux Platform Group
Samsung Poland R&D Center


From p.osciak at samsung.com  Mon Jun 28 04:08:53 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:53 +0200
Subject: [PATCH v3 07/12] s3c-fb: window 3 of 64xx+ does not have an osd_d
	register
In-Reply-To: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1277712538-23188-8-git-send-email-p.osciak@samsung.com>

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/video/s3c-fb.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)

diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 6131ebb..0a93fca 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -1437,7 +1437,6 @@ static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] __devinitdata = {
 	},
 	[3] = {
 		.has_osd_c	= 1,
-		.has_osd_d	= 1,
 		.palette_sz	= 16,
 		.palette_16bpp	= 1,
 		.valid_bpp	= (VALID_BPP124  | VALID_BPP(16) |
-- 
1.7.1.569.g6f426



From p.osciak at samsung.com  Mon Jun 28 04:08:50 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:50 +0200
Subject: [PATCH v3 04/12] s3c-fb: Add device name initialization
In-Reply-To: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1277712538-23188-5-git-send-email-p.osciak@samsung.com>

Add framebuffer device name initialization calls for S3C2443, S3C64xx
and S5P machines.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s3c2416/s3c2416.c              |    3 +-
 arch/arm/mach-s3c2443/s3c2443.c              |    2 +
 arch/arm/mach-s5pc100/cpu.c                  |    3 ++
 arch/arm/mach-s5pv210/cpu.c                  |    7 ++---
 arch/arm/plat-samsung/include/plat/fb-core.h |   29 ++++++++++++++++++++++++++
 5 files changed, 39 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/plat-samsung/include/plat/fb-core.h

diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c
index 35dabcc..bc30245 100644
--- a/arch/arm/mach-s3c2416/s3c2416.c
+++ b/arch/arm/mach-s3c2416/s3c2416.c
@@ -55,6 +55,7 @@
 #include <plat/cpu.h>
 
 #include <plat/iic-core.h>
+#include <plat/fb-core.h>
 
 static struct map_desc s3c2416_iodesc[] __initdata = {
 	IODESC_ENT(WATCHDOG),
@@ -90,7 +91,7 @@ int __init s3c2416_init(void)
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
 
-	s3c_device_fb.name = "s3c2443-fb";
+	s3c_fb_setname("s3c2443-fb");
 
 	return sysdev_register(&s3c2416_sysdev);
 }
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c
index ce2ec32..839b6b2 100644
--- a/arch/arm/mach-s3c2443/s3c2443.c
+++ b/arch/arm/mach-s3c2443/s3c2443.c
@@ -35,6 +35,7 @@
 #include <plat/s3c2443.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/fb-core.h>
 
 static struct map_desc s3c2443_iodesc[] __initdata = {
 	IODESC_ENT(WATCHDOG),
@@ -62,6 +63,7 @@ int __init s3c2443_init(void)
 	s3c24xx_reset_hook = s3c2443_hard_reset;
 
 	s3c_device_nand.name = "s3c2412-nand";
+	s3c_fb_setname("s3c2443-fb");
 
 	/* change WDT IRQ number */
 	s3c_device_wdt.resource[1].start = IRQ_S3C2443_WDT;
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 7b5bdbc..d10276a 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -41,6 +41,7 @@
 #include <plat/iic-core.h>
 #include <plat/sdhci.h>
 #include <plat/onenand-core.h>
+#include <plat/fb-core.h>
 
 #include <plat/s5pc100.h>
 
@@ -92,6 +93,8 @@ void __init s5pc100_map_io(void)
 	s3c_i2c1_setname("s3c2440-i2c");
 
 	s3c_onenand_setname("s5pc100-onenand");
+
+	s3c_fb_setname("s5pc100-fb");
 }
 
 void __init s5pc100_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index f42c507..4d3580a 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -34,6 +34,7 @@
 #include <plat/s5pv210.h>
 #include <plat/iic-core.h>
 #include <plat/sdhci.h>
+#include <plat/fb-core.h>
 
 /* Initial IO mappings */
 
@@ -80,10 +81,6 @@ void __init s5pv210_map_io(void)
 	s3c_device_adc.name	= "s3c64xx-adc";
 #endif
 
-#ifdef CONFIG_S3C_DEV_FB
-	s3c_device_fb.name	= "s5p-fb";
-#endif
-
 	iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
 
 	/* initialise device information early */
@@ -95,6 +92,8 @@ void __init s5pv210_map_io(void)
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
 	s3c_i2c2_setname("s3c2440-i2c");
+
+	s3c_fb_setname("s5pv210-fb");
 }
 
 void __init s5pv210_init_clocks(int xtal)
diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/plat-samsung/include/plat/fb-core.h
new file mode 100644
index 0000000..bca383e
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/fb-core.h
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/plat-samsung/include/plat/fb-core.h
+ *
+ * Copyright 2010 Samsung Electronics Co., Ltd.
+ *	Pawel Osciak <p.osciak at samsung.com>
+ *
+ * Samsung framebuffer driver core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PLAT_FB_CORE_H
+#define __ASM_PLAT_FB_CORE_H __FILE__
+
+/*
+ * These functions are only for use with the core support code, such as
+ * the CPU-specific initialization code.
+ */
+
+/* Re-define device name depending on support. */
+static inline void s3c_fb_setname(char *name)
+{
+#ifdef CONFIG_S3C_DEV_FB
+	s3c_device_fb.name = name;
+#endif
+}
+
+#endif /* __ASM_PLAT_FB_CORE_H */
-- 
1.7.1.569.g6f426



From p.osciak at samsung.com  Mon Jun 28 04:08:55 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:55 +0200
Subject: [PATCH v3 09/12] s3c-fb: Correct window osd size and alpha register
	handling
In-Reply-To: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1277712538-23188-10-git-send-email-p.osciak@samsung.com>

S3C64xx and S5P OSD registers for OSD size and alpha are as follows:
VIDOSDC: win 0 - size, win 1-4: alpha
VIDOSDD: win 1-2 - size; not present for windows 0, 3 and 4

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/video/s3c-fb.c |   58 ++++++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 51 insertions(+), 7 deletions(-)

diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 94423c5..3b2c7fe 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -64,6 +64,9 @@ struct s3c_fb;
 #define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
 #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
 #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
+#define VIDOSD_SIZE(win, variant, win_variant) \
+	(OSD_BASE(win, variant) + (win_variant).osd_size_off)
+#define VIDOSD_ALPHA(win, variant, win_variant) VIDOSD_C(win, variant)
 
 /**
  * struct s3c_fb_variant - fb variant information
@@ -112,7 +115,10 @@ struct s3c_fb_variant {
 struct s3c_fb_win_variant {
 	unsigned int	has_osd_c:1;
 	unsigned int	has_osd_d:1;
+	unsigned int	has_osd_size:1;
+	unsigned int	has_osd_alpha:1;
 	unsigned int	palette_16bpp:1;
+	unsigned short	osd_size_off;
 	unsigned short	palette_sz;
 	u32		valid_bpp;
 };
@@ -365,6 +371,36 @@ static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
 }
 
 /**
+ * vidosd_set_size() - set OSD size for a window
+ *
+ * @win: the window to set OSD size for
+ * @size: OSD size register value
+ */
+static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
+{
+	struct s3c_fb *sfb = win->parent;
+
+	if (win->variant.has_osd_size)
+		writel(size, sfb->regs + VIDOSD_SIZE(win->index, sfb->variant,
+							win->variant));
+}
+
+/**
+ * vidosd_set_alpha() - set alpha transparency for a window
+ *
+ * @win: the window to set OSD size for
+ * @alpha: alpha register value
+ */
+static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
+{
+	struct s3c_fb *sfb = win->parent;
+
+	if (win->variant.has_osd_alpha)
+		writel(alpha, sfb->regs + VIDOSD_ALPHA(win->index,
+						sfb->variant, win->variant));
+}
+
+/**
  * shadow_protect_win() - disable updating values from shadow registers at vsync
  *
  * @win: window to protect registers for
@@ -408,7 +444,7 @@ static int s3c_fb_set_par(struct fb_info *info)
 	void __iomem *regs = sfb->regs;
 	void __iomem *buf = regs;
 	int win_no = win->index;
-	u32 osdc_data = 0;
+	u32 alpha = 0;
 	u32 data;
 	u32 pagewidth;
 	int clkdiv;
@@ -511,15 +547,12 @@ static int s3c_fb_set_par(struct fb_info *info)
 
 	data = var->xres * var->yres;
 
-	osdc_data = VIDISD14C_ALPHA1_R(0xf) |
+	alpha = VIDISD14C_ALPHA1_R(0xf) |
 		VIDISD14C_ALPHA1_G(0xf) |
 		VIDISD14C_ALPHA1_B(0xf);
 
-	if (win->variant.has_osd_d) {
-		writel(data, regs + VIDOSD_D(win_no, sfb->variant));
-		writel(osdc_data, regs + VIDOSD_C(win_no, sfb->variant));
-	} else
-		writel(data, regs + VIDOSD_C(win_no, sfb->variant));
+	vidosd_set_alpha(win, alpha);
+	vidosd_set_size(win, data);
 
 	data = WINCONx_ENWIN;
 
@@ -1445,12 +1478,17 @@ static int s3c_fb_resume(struct platform_device *pdev)
 static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] __devinitdata = {
 	[0] = {
 		.has_osd_c	= 1,
+		.has_osd_size	= 1,
+		.osd_size_off	= 0x8,
 		.palette_sz	= 256,
 		.valid_bpp	= VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
 	},
 	[1] = {
 		.has_osd_c	= 1,
 		.has_osd_d	= 1,
+		.has_osd_size	= 1,
+		.osd_size_off	= 0x12,
+		.has_osd_alpha	= 1,
 		.palette_sz	= 256,
 		.valid_bpp	= (VALID_BPP1248 | VALID_BPP(16) |
 				   VALID_BPP(18) | VALID_BPP(19) |
@@ -1459,6 +1497,9 @@ static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] __devinitdata = {
 	[2] = {
 		.has_osd_c	= 1,
 		.has_osd_d	= 1,
+		.has_osd_size	= 1,
+		.osd_size_off	= 0x12,
+		.has_osd_alpha	= 1,
 		.palette_sz	= 16,
 		.palette_16bpp	= 1,
 		.valid_bpp	= (VALID_BPP1248 | VALID_BPP(16) |
@@ -1467,6 +1508,7 @@ static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] __devinitdata = {
 	},
 	[3] = {
 		.has_osd_c	= 1,
+		.has_osd_alpha	= 1,
 		.palette_sz	= 16,
 		.palette_16bpp	= 1,
 		.valid_bpp	= (VALID_BPP124  | VALID_BPP(16) |
@@ -1475,6 +1517,7 @@ static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] __devinitdata = {
 	},
 	[4] = {
 		.has_osd_c	= 1,
+		.has_osd_alpha	= 1,
 		.palette_sz	= 4,
 		.palette_16bpp	= 1,
 		.valid_bpp	= (VALID_BPP(1) | VALID_BPP(2) |
@@ -1600,6 +1643,7 @@ static struct s3c_fb_driverdata s3c_fb_data_s3c2443 __devinitdata = {
 	},
 	.win[1] = &(struct s3c_fb_win_variant) {
 		.has_osd_c	= 1,
+		.has_osd_alpha	= 1,
 		.palette_sz	= 256,
 		.valid_bpp	= (VALID_BPP1248 | VALID_BPP(16) |
 				   VALID_BPP(18) | VALID_BPP(19) |
-- 
1.7.1.569.g6f426



From p.osciak at samsung.com  Mon Jun 28 04:08:58 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:58 +0200
Subject: [PATCH v3 12/12] s3c-fb: Add support for DMA channel control on
	S5PV210
In-Reply-To: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1277712538-23188-13-git-send-email-p.osciak@samsung.com>

S5PV210 SoCs allow enabling/disabling DMA channels per window. For a window
to display data from framebuffer memory, its channel has to be enabled.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-samsung/include/plat/regs-fb.h |    4 ++++
 drivers/video/s3c-fb.c                       |   15 +++++++++++++++
 2 files changed, 19 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index da54b64..f801a37 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -221,6 +221,10 @@
 /* S5PV210 */
 #define SHADOWCON				(0x34)
 #define SHADOWCON_WINx_PROTECT(_win)		(1 << (10 + _win))
+/* DMA channels (all windows) */
+#define SHADOWCON_CHx_ENABLE(_win)		(1 << (_win))
+/* Local input channels (windows 0-2) */
+#define SHADOWCON_CHx_LOCAL_ENABLE(_win)	(1 << (5 + (_win)))
 
 #define VIDOSDxA_TOPLEFT_X_MASK			(0x7ff << 11)
 #define VIDOSDxA_TOPLEFT_X_SHIFT		(11)
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index de7334c..4b3617c 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -635,6 +635,13 @@ static int s3c_fb_set_par(struct fb_info *info)
 	writel(data, regs + sfb->variant.wincon + (win_no * 4));
 	writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
 
+	/* Enable DMA channel for this window */
+	if (sfb->variant.has_shadowcon) {
+		data = readl(sfb->regs + SHADOWCON);
+		data |= SHADOWCON_CHx_ENABLE(win_no);
+		writel(data, sfb->regs + SHADOWCON);
+	}
+
 	shadow_protect_win(win, 0);
 
 	return 0;
@@ -1095,7 +1102,15 @@ static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
  */
 static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
 {
+	u32 data;
+
 	if (win->fbinfo) {
+		if (sfb->variant.has_shadowcon) {
+			data = readl(sfb->regs + SHADOWCON);
+			data &= ~SHADOWCON_CHx_ENABLE(win->index);
+			data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);
+			writel(data, sfb->regs + SHADOWCON);
+		}
 		unregister_framebuffer(win->fbinfo);
 		if (&win->fbinfo->cmap)
 			fb_dealloc_cmap(&win->fbinfo->cmap);
-- 
1.7.1.569.g6f426



From p.osciak at samsung.com  Mon Jun 28 04:08:47 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:47 +0200
Subject: [PATCH v3 01/12] s3c-fb: Fix various null references on framebuffer
	memory alloc failure
In-Reply-To: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1277712538-23188-2-git-send-email-p.osciak@samsung.com>

The following problems were found in the above situation:

sfb->windows[win] was being assigned at the end of s3c_fb_probe_win only.
This resulted in passing a NULL to s3c_fb_release_win if probe_win returned
early and a memory leak.

dma_free_writecombine does not allow its third argument to be NULL.

fb_dealloc_cmap does not verify whether its argument is not NULL.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/video/s3c-fb.c |    8 +++++---
 1 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index b00c064..d998324 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -804,7 +804,8 @@ static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
 {
 	struct fb_info *fbi = win->fbinfo;
 
-	dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
+	if (fbi->screen_base)
+		dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
 			      fbi->screen_base, fbi->fix.smem_start);
 }
 
@@ -819,7 +820,8 @@ static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
 {
 	if (win->fbinfo) {
 		unregister_framebuffer(win->fbinfo);
-		fb_dealloc_cmap(&win->fbinfo->cmap);
+		if (&win->fbinfo->cmap)
+			fb_dealloc_cmap(&win->fbinfo->cmap);
 		s3c_fb_free_memory(sfb, win);
 		framebuffer_release(win->fbinfo);
 	}
@@ -865,6 +867,7 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 	WARN_ON(windata->win_mode.yres == 0);
 
 	win = fbinfo->par;
+	*res = win;
 	var = &fbinfo->var;
 	win->variant = *variant;
 	win->fbinfo = fbinfo;
@@ -939,7 +942,6 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 		return ret;
 	}
 
-	*res = win;
 	dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
 
 	return 0;
-- 
1.7.1.569.g6f426



From p.osciak at samsung.com  Mon Jun 28 04:08:49 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:49 +0200
Subject: [PATCH v3 03/12] s3c-fb: Separate S5PC100 and S5PV210 framebuffer
	driver data structures
In-Reply-To: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1277712538-23188-4-git-send-email-p.osciak@samsung.com>

S5PC100 and S5PV210 framebuffer devices differ slightly in terms of
available registers and their driver data structures have to be separate.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/video/s3c-fb.c |   37 ++++++++++++++++++++++++++++++++++---
 1 files changed, 34 insertions(+), 3 deletions(-)

diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index d998324..59ac76a 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -1251,7 +1251,35 @@ static struct s3c_fb_driverdata s3c_fb_data_64xx __devinitdata = {
 	.win[4]	= &s3c_fb_data_64xx_wins[4],
 };
 
-static struct s3c_fb_driverdata s3c_fb_data_s5p __devinitdata = {
+static struct s3c_fb_driverdata s3c_fb_data_s5pc100 __devinitdata = {
+	.variant = {
+		.nr_windows	= 5,
+		.vidtcon	= VIDTCON0,
+		.wincon		= WINCON(0),
+		.winmap		= WINxMAP(0),
+		.keycon		= WKEYCON,
+		.osd		= VIDOSD_BASE,
+		.osd_stride	= 16,
+		.buf_start	= VIDW_BUF_START(0),
+		.buf_size	= VIDW_BUF_SIZE(0),
+		.buf_end	= VIDW_BUF_END(0),
+
+		.palette = {
+			[0] = 0x2400,
+			[1] = 0x2800,
+			[2] = 0x2c00,
+			[3] = 0x3000,
+			[4] = 0x3400,
+		},
+	},
+	.win[0]	= &s3c_fb_data_64xx_wins[0],
+	.win[1]	= &s3c_fb_data_64xx_wins[1],
+	.win[2]	= &s3c_fb_data_64xx_wins[2],
+	.win[3]	= &s3c_fb_data_64xx_wins[3],
+	.win[4]	= &s3c_fb_data_64xx_wins[4],
+};
+
+static struct s3c_fb_driverdata s3c_fb_data_s5pv210 __devinitdata = {
 	.variant = {
 		.nr_windows	= 5,
 		.vidtcon	= VIDTCON0,
@@ -1319,8 +1347,11 @@ static struct platform_device_id s3c_fb_driver_ids[] = {
 		.name		= "s3c-fb",
 		.driver_data	= (unsigned long)&s3c_fb_data_64xx,
 	}, {
-		.name		= "s5p-fb",
-		.driver_data	= (unsigned long)&s3c_fb_data_s5p,
+		.name		= "s5pc100-fb",
+		.driver_data	= (unsigned long)&s3c_fb_data_s5pc100,
+	}, {
+		.name		= "s5pv210-fb",
+		.driver_data	= (unsigned long)&s3c_fb_data_s5pv210,
 	}, {
 		.name		= "s3c2443-fb",
 		.driver_data	= (unsigned long)&s3c_fb_data_s3c2443,
-- 
1.7.1.569.g6f426



From p.osciak at samsung.com  Mon Jun 28 04:08:56 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:56 +0200
Subject: [PATCH v3 10/12] s3c-fb: Protect window-specific registers during
	updates
In-Reply-To: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1277712538-23188-11-git-send-email-p.osciak@samsung.com>

Newer hardware (S3C6410, S5P) have the ability to block updates from shadow
registers during reconfiguration. Add protect calls for set_par and clear
protection when resetting.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/video/s3c-fb.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 3b2c7fe..d461f1d 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -451,6 +451,8 @@ static int s3c_fb_set_par(struct fb_info *info)
 
 	dev_dbg(sfb->dev, "setting framebuffer parameters\n");
 
+	shadow_protect_win(win, 1);
+
 	switch (var->bits_per_pixel) {
 	case 32:
 	case 24:
@@ -633,6 +635,8 @@ static int s3c_fb_set_par(struct fb_info *info)
 	writel(data, regs + sfb->variant.wincon + (win_no * 4));
 	writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
 
+	shadow_protect_win(win, 0);
+
 	return 0;
 }
 
@@ -1232,11 +1236,14 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
 {
 	void __iomem *regs = sfb->regs;
+	u32 reg;
 
 	writel(0, regs + sfb->variant.wincon + (win * 4));
 	writel(0, regs + VIDOSD_A(win, sfb->variant));
 	writel(0, regs + VIDOSD_B(win, sfb->variant));
 	writel(0, regs + VIDOSD_C(win, sfb->variant));
+	reg = readl(regs + SHADOWCON);
+	writel(reg & ~SHADOWCON_WINx_PROTECT(win), regs + SHADOWCON);
 }
 
 static int __devinit s3c_fb_probe(struct platform_device *pdev)
-- 
1.7.1.569.g6f426



From p.osciak at samsung.com  Mon Jun 28 04:08:54 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:54 +0200
Subject: [PATCH v3 08/12] s3c-fb: Add SHADOWCON shadow register locking support
	for S5PV210
In-Reply-To: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1277712538-23188-9-git-send-email-p.osciak@samsung.com>

S5PV210 allows per-window locking of register value updates from shadow
registers.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-samsung/include/plat/regs-fb.h |    3 ++
 drivers/video/s3c-fb.c                       |   39 +++++++++++++++++++++++--
 2 files changed, 38 insertions(+), 4 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index 5bcdd09..da54b64 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -218,6 +218,9 @@
 #define WINCON1_BPPMODE_25BPP_A1888		(0xd << 2)
 #define WINCON1_BPPMODE_28BPP_A4888		(0xd << 2)
 
+/* S5PV210 */
+#define SHADOWCON				(0x34)
+#define SHADOWCON_WINx_PROTECT(_win)		(1 << (10 + _win))
 
 #define VIDOSDxA_TOPLEFT_X_MASK			(0x7ff << 11)
 #define VIDOSDxA_TOPLEFT_X_SHIFT		(11)
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 0a93fca..94423c5 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -79,6 +79,7 @@ struct s3c_fb;
  * @osd: The base for the OSD registers.
  * @palette: Address of palette memory, or 0 if none.
  * @has_prtcon: Set if has PRTCON register.
+ * @has_shadowcon: Set if has SHADOWCON register.
  */
 struct s3c_fb_variant {
 	unsigned int	is_2443:1;
@@ -95,6 +96,7 @@ struct s3c_fb_variant {
 	unsigned short	palette[S3C_FB_MAX_WIN];
 
 	unsigned int	has_prtcon:1;
+	unsigned int	has_shadowcon:1;
 };
 
 /**
@@ -363,6 +365,36 @@ static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
 }
 
 /**
+ * shadow_protect_win() - disable updating values from shadow registers at vsync
+ *
+ * @win: window to protect registers for
+ * @protect: 1 to protect (disable updates)
+ */
+static void shadow_protect_win(struct s3c_fb_win *win, int protect)
+{
+	struct s3c_fb *sfb = win->parent;
+	u32 reg;
+
+	if (protect) {
+		if (sfb->variant.has_prtcon) {
+			writel(PRTCON_PROTECT, sfb->regs + PRTCON);
+		} else if (sfb->variant.has_shadowcon) {
+			reg = readl(sfb->regs + SHADOWCON);
+			writel(reg | SHADOWCON_WINx_PROTECT(win->index),
+				sfb->regs + SHADOWCON);
+		}
+	} else {
+		if (sfb->variant.has_prtcon) {
+			writel(0, sfb->regs + PRTCON);
+		} else if (sfb->variant.has_shadowcon) {
+			reg = readl(sfb->regs + SHADOWCON);
+			writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
+				sfb->regs + SHADOWCON);
+		}
+	}
+}
+
+/**
  * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
  * @info: The framebuffer to change.
  *
@@ -811,16 +843,14 @@ static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
 
 	/* Temporarily turn off per-vsync update from shadow registers until
 	 * both start and end addresses are updated to prevent corruption */
-	if (sfb->variant.has_prtcon)
-		writel(PRTCON_PROTECT, sfb->regs + PRTCON);
+	shadow_protect_win(win, 1);
 
 	writel(info->fix.smem_start + start_byte_offset,
 		buf + sfb->variant.buf_start);
 	writel(info->fix.smem_start + end_byte_offset,
 		buf + sfb->variant.buf_end);
 
-	if (sfb->variant.has_prtcon)
-		writel(0, sfb->regs + PRTCON);
+	shadow_protect_win(win, 0);
 
 	return 0;
 }
@@ -1534,6 +1564,7 @@ static struct s3c_fb_driverdata s3c_fb_data_s5pv210 __devinitdata = {
 			[4] = 0x3400,
 		},
 
+		.has_shadowcon	= 1,
 	},
 	.win[0]	= &s3c_fb_data_64xx_wins[0],
 	.win[1]	= &s3c_fb_data_64xx_wins[1],
-- 
1.7.1.569.g6f426



From p.osciak at samsung.com  Mon Jun 28 04:08:52 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:52 +0200
Subject: [PATCH v3 06/12] s3c-fb: Add wait for VSYNC ioctl
In-Reply-To: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1277712538-23188-7-git-send-email-p.osciak@samsung.com>

Add VSYNC interrupt support and an ioctl that allows waiting for it.
Interrupts are turned on only when needed.

Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-samsung/include/plat/regs-fb.h |    1 +
 drivers/video/s3c-fb.c                       |  167 +++++++++++++++++++++++++-
 2 files changed, 167 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index f454e32..5bcdd09 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -298,6 +298,7 @@
 #define VIDINTCON0_FRAMESEL0_FRONTPORCH		(0x3 << 15)
 
 #define VIDINTCON0_FRAMESEL1			(1 << 13)
+#define VIDINTCON0_FRAMESEL1_MASK		(0x3 << 13)
 #define VIDINTCON0_FRAMESEL1_NONE		(0x0 << 13)
 #define VIDINTCON0_FRAMESEL1_BACKPORCH		(0x1 << 13)
 #define VIDINTCON0_FRAMESEL1_VSYNC		(0x2 << 13)
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 4f3680d..6131ebb 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -21,6 +21,8 @@
 #include <linux/clk.h>
 #include <linux/fb.h>
 #include <linux/io.h>
+#include <linux/uaccess.h>
+#include <linux/interrupt.h>
 
 #include <mach/map.h>
 #include <plat/regs-fb-v4.h>
@@ -48,6 +50,11 @@
 	__raw_writel(v, r); } while(0)
 #endif /* FB_S3C_DEBUG_REGWRITE */
 
+/* irq_flags bits */
+#define S3C_FB_VSYNC_IRQ_EN	0
+
+#define VSYNC_TIMEOUT_MSEC 50
+
 struct s3c_fb;
 
 #define VALID_BPP(x) (1 << ((x) - 1))
@@ -156,6 +163,16 @@ struct s3c_fb_win {
 };
 
 /**
+ * struct s3c_fb_vsync - vsync information
+ * @wait:	a queue for processes waiting for vsync
+ * @count:	vsync interrupt count
+ */
+struct s3c_fb_vsync {
+	wait_queue_head_t	wait;
+	unsigned int		count;
+};
+
+/**
  * struct s3c_fb - overall hardware state of the hardware
  * @dev: The device that we bound to, for printing, etc.
  * @regs_res: The resource we claimed for the IO registers.
@@ -165,6 +182,9 @@ struct s3c_fb_win {
  * @enabled: A bitmask of enabled hardware windows.
  * @pdata: The platform configuration data passed with the device.
  * @windows: The hardware windows that have been claimed.
+ * @irq_no: IRQ line number
+ * @irq_flags: irq flags
+ * @vsync_info: VSYNC-related information (count, queues...)
  */
 struct s3c_fb {
 	struct device		*dev;
@@ -177,6 +197,10 @@ struct s3c_fb {
 
 	struct s3c_fb_platdata	*pdata;
 	struct s3c_fb_win	*windows[S3C_FB_MAX_WIN];
+
+	int			 irq_no;
+	unsigned long		 irq_flags;
+	struct s3c_fb_vsync	 vsync_info;
 };
 
 /**
@@ -801,6 +825,124 @@ static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
 	return 0;
 }
 
+/**
+ * s3c_fb_enable_irq() - enable framebuffer interrupts
+ * @sfb: main hardware state
+ */
+static void s3c_fb_enable_irq(struct s3c_fb *sfb)
+{
+	void __iomem *regs = sfb->regs;
+	u32 irq_ctrl_reg;
+
+	if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
+		/* IRQ disabled, enable it */
+		irq_ctrl_reg = readl(regs + VIDINTCON0);
+
+		irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
+		irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
+
+		irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
+		irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
+		irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
+		irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
+
+		writel(irq_ctrl_reg, regs + VIDINTCON0);
+	}
+}
+
+/**
+ * s3c_fb_disable_irq() - disable framebuffer interrupts
+ * @sfb: main hardware state
+ */
+static void s3c_fb_disable_irq(struct s3c_fb *sfb)
+{
+	void __iomem *regs = sfb->regs;
+	u32 irq_ctrl_reg;
+
+	if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
+		/* IRQ enabled, disable it */
+		irq_ctrl_reg = readl(regs + VIDINTCON0);
+
+		irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
+		irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
+
+		writel(irq_ctrl_reg, regs + VIDINTCON0);
+	}
+}
+
+static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
+{
+	struct s3c_fb *sfb = dev_id;
+	void __iomem  *regs = sfb->regs;
+	u32 irq_sts_reg;
+
+	irq_sts_reg = readl(regs + VIDINTCON1);
+
+	if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
+
+		/* VSYNC interrupt, accept it */
+		writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
+
+		sfb->vsync_info.count++;
+		wake_up_interruptible(&sfb->vsync_info.wait);
+	}
+
+	/* We only support waiting for VSYNC for now, so it's safe
+	 * to always disable irqs here.
+	 */
+	s3c_fb_disable_irq(sfb);
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
+ * @sfb: main hardware state
+ * @crtc: head index.
+ */
+static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
+{
+	unsigned long count;
+	int ret;
+
+	if (crtc != 0)
+		return -ENODEV;
+
+	s3c_fb_enable_irq(sfb);
+	count = sfb->vsync_info.count;
+	ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
+				       count != sfb->vsync_info.count,
+				       msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));
+	if (ret == 0)
+		return -ETIMEDOUT;
+
+	return 0;
+}
+
+static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
+			unsigned long arg)
+{
+	struct s3c_fb_win *win = info->par;
+	struct s3c_fb *sfb = win->parent;
+	int ret;
+	u32 crtc;
+
+	switch (cmd) {
+	case FBIO_WAITFORVSYNC:
+		if (get_user(crtc, (u32 __user *)arg)) {
+			ret = -EFAULT;
+			break;
+		}
+
+		ret = s3c_fb_wait_for_vsync(sfb, crtc);
+		break;
+	default:
+		ret = -ENOTTY;
+	}
+
+	return ret;
+}
+
 static struct fb_ops s3c_fb_ops = {
 	.owner		= THIS_MODULE,
 	.fb_check_var	= s3c_fb_check_var,
@@ -811,6 +953,7 @@ static struct fb_ops s3c_fb_ops = {
 	.fb_copyarea	= cfb_copyarea,
 	.fb_imageblit	= cfb_imageblit,
 	.fb_pan_display	= s3c_fb_pan_display,
+	.fb_ioctl	= s3c_fb_ioctl,
 };
 
 /**
@@ -917,6 +1060,8 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 
 	dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
 
+	init_waitqueue_head(&sfb->vsync_info.wait);
+
 	palette_size = variant->palette_sz * 4;
 
 	fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
@@ -1096,6 +1241,20 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev)
 		goto err_req_region;
 	}
 
+	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+	if (!res) {
+		dev_err(dev, "failed to acquire irq resource\n");
+		ret = -ENOENT;
+		goto err_ioremap;
+	}
+	sfb->irq_no = res->start;
+	ret = request_irq(sfb->irq_no, s3c_fb_irq,
+			  0, "s3c_fb", sfb);
+	if (ret) {
+		dev_err(dev, "irq request failed\n");
+		goto err_ioremap;
+	}
+
 	dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
 
 	/* setup gpio and output polarity controls */
@@ -1130,7 +1289,7 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev)
 			dev_err(dev, "failed to create window %d\n", win);
 			for (; win >= 0; win--)
 				s3c_fb_release_win(sfb, sfb->windows[win]);
-			goto err_ioremap;
+			goto err_irq;
 		}
 	}
 
@@ -1138,6 +1297,9 @@ static int __devinit s3c_fb_probe(struct platform_device *pdev)
 
 	return 0;
 
+err_irq:
+	free_irq(sfb->irq_no, sfb);
+
 err_ioremap:
 	iounmap(sfb->regs);
 
@@ -1170,6 +1332,8 @@ static int __devexit s3c_fb_remove(struct platform_device *pdev)
 		if (sfb->windows[win])
 			s3c_fb_release_win(sfb, sfb->windows[win]);
 
+	free_irq(sfb->irq_no, sfb);
+
 	iounmap(sfb->regs);
 
 	clk_disable(sfb->bus_clk);
@@ -1370,6 +1534,7 @@ static struct s3c_fb_driverdata s3c_fb_data_s5pv210 __devinitdata = {
 			[3] = 0x3000,
 			[4] = 0x3400,
 		},
+
 	},
 	.win[0]	= &s3c_fb_data_64xx_wins[0],
 	.win[1]	= &s3c_fb_data_64xx_wins[1],
-- 
1.7.1.569.g6f426



From p.osciak at samsung.com  Mon Jun 28 04:08:57 2010
From: p.osciak at samsung.com (Pawel Osciak)
Date: Mon, 28 Jun 2010 10:08:57 +0200
Subject: [PATCH v3 11/12] s3c-fb: fix section mismatch
In-Reply-To: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
Message-ID: <1277712538-23188-12-git-send-email-p.osciak@samsung.com>

From: Marek Szyprowski <m.szyprowski at samsung.com>

This patch fixes the following section mismatch errors:

WARNING: vmlinux.o(.data+0x20b40): Section mismatch in reference from the variable s3c_fb_driver_ids to the (unknown reference) .devinit.data:(unknown)
The variable s3c_fb_driver_ids references
the (unknown reference) __devinitdata (unknown)
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*driver, *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,

WARNING: vmlinux.o(.data+0x20b58): Section mismatch in reference from the variable s3c_fb_driver_ids to the (unknown reference) .devinit.data:(unknown)
The variable s3c_fb_driver_ids references
the (unknown reference) __devinitdata (unknown)
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*driver, *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,

WARNING: vmlinux.o(.data+0x20b70): Section mismatch in reference from the variable s3c_fb_driver_ids to the (unknown reference) .devinit.data:(unknown)
The variable s3c_fb_driver_ids references
the (unknown reference) __devinitdata (unknown)
If the reference is valid then annotate the
variable with __init* or __refdata (see linux/init.h) or name the variable:
*driver, *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console,

Signed-off-by: Marek Szyprowski <m.szyprowski at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/video/s3c-fb.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index d461f1d..de7334c 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -1482,7 +1482,7 @@ static int s3c_fb_resume(struct platform_device *pdev)
 #define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
 #define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
 
-static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] __devinitdata = {
+static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {
 	[0] = {
 		.has_osd_c	= 1,
 		.has_osd_size	= 1,
@@ -1533,7 +1533,7 @@ static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] __devinitdata = {
 	},
 };
 
-static struct s3c_fb_driverdata s3c_fb_data_64xx __devinitdata = {
+static struct s3c_fb_driverdata s3c_fb_data_64xx = {
 	.variant = {
 		.nr_windows	= 5,
 		.vidtcon	= VIDTCON0,
@@ -1563,7 +1563,7 @@ static struct s3c_fb_driverdata s3c_fb_data_64xx __devinitdata = {
 	.win[4]	= &s3c_fb_data_64xx_wins[4],
 };
 
-static struct s3c_fb_driverdata s3c_fb_data_s5pc100 __devinitdata = {
+static struct s3c_fb_driverdata s3c_fb_data_s5pc100 = {
 	.variant = {
 		.nr_windows	= 5,
 		.vidtcon	= VIDTCON0,
@@ -1593,7 +1593,7 @@ static struct s3c_fb_driverdata s3c_fb_data_s5pc100 __devinitdata = {
 	.win[4]	= &s3c_fb_data_64xx_wins[4],
 };
 
-static struct s3c_fb_driverdata s3c_fb_data_s5pv210 __devinitdata = {
+static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = {
 	.variant = {
 		.nr_windows	= 5,
 		.vidtcon	= VIDTCON0,
@@ -1624,7 +1624,7 @@ static struct s3c_fb_driverdata s3c_fb_data_s5pv210 __devinitdata = {
 };
 
 /* S3C2443/S3C2416 style hardware */
-static struct s3c_fb_driverdata s3c_fb_data_s3c2443 __devinitdata = {
+static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
 	.variant = {
 		.nr_windows	= 2,
 		.is_2443	= 1,
-- 
1.7.1.569.g6f426



From viresh.kumar at st.com  Mon Jun 28 04:16:50 2010
From: viresh.kumar at st.com (Viresh KUMAR)
Date: Mon, 28 Jun 2010 13:46:50 +0530
Subject: [PATCH resend] Watchdog: Adding support for ARM Primecell	SP805
	Watchdog
In-Reply-To: <20100611053049.GM3788@infomag.iguana.be>
References: <1275465783-14052-1-git-send-email-viresh.kumar@st.com>	<4C11B711.70907@st.com>
	<20100611053049.GM3788@infomag.iguana.be>
Message-ID: <4C285A72.7030303@st.com>

On 6/11/2010 11:00 AM, Wim Van Sebroeck wrote:
> Hi Viresh,
> 
> Still need to look at it. First finishing up another project.
> Probably for this weekend.
> 
> Kind regards,
> Wim.
> 

Wim,

Have you reviewed this patch or still need to look at it?

viresh.


From jy0922.shim at samsung.com  Mon Jun 28 04:39:39 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Mon, 28 Jun 2010 17:39:39 +0900
Subject: [PATCH v5 3/3] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <20100625083019.GD8546@core.coreip.homeip.net>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<1277101605-2435-3-git-send-email-jy0922.shim@samsung.com>
	<20100625083019.GD8546@core.coreip.homeip.net>
Message-ID: <4C285FCB.3070100@samsung.com>

Hi, Dmitry.

On 6/25/2010 5:30 PM, Dmitry Torokhov wrote:
> Hi Joonyoung,
> 
> On Mon, Jun 21, 2010 at 03:26:45PM +0900, Joonyoung Shim wrote:
>> This patch adds support for keypad driver running on Samsung cpus. This
>> driver is tested on GONI and Aquila board using S5PC110 cpu.
>>
>> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
>> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> 
> Following my conversation with Thomas Gleixner reagrding "long playing"
> threaded interrupt handlers I tried to convert your driver to use this
> concept. The idea is to keep polling within IRQ thread context instead
> of using additional work/timer structures to simplify code and ensure
> race-free shutdown/unbind.
> 
> I think it was based on v4 of your driver and I'd appreciate if you could
> give it a try.
> 
> Thank you.
> 

I have tested your patch on my v5 patchset and it is working after some
fixing. I will post v6 patchset appling your patch.

Thanks.


From harishpresent at gmail.com  Sun Jun 27 12:21:57 2010
From: harishpresent at gmail.com (Harishkumar V)
Date: Sun, 27 Jun 2010 21:51:57 +0530
Subject: BUG: soft lockup - CPU#0 stuck for 61s!
In-Reply-To: <AANLkTilLOgIi_3tttL1XapPLbB3CTUPK1b_bufIsU6Sz@mail.gmail.com>
References: <AANLkTilsRHU43nqfCvS-7NW6n_E0uP1JTEKKVFPvWkxP@mail.gmail.com>
	<AANLkTilLOgIi_3tttL1XapPLbB3CTUPK1b_bufIsU6Sz@mail.gmail.com>
Message-ID: <AANLkTinGbpSfOpCpmoIIF8PT-7BseuGvIK61GSMGcxJH@mail.gmail.com>

Hi,

I am using an ARMv7 500 mhz board which is running linux-2.6.28-rc9 kernel.
I am running an application which does video processing on it. At times, the
board gets CPU soft lockup and become freezed.

Is their any fix/workaround for the following problem.

this is the one, i am getting in the console,

BUG: soft lockup - CPU#0 stuck for 61s! [linphone-3:764]
Modules linked in:

Pid: 764, comm:           linphone-3
CPU: 0    Not tainted  (2.6.28-rc9 #14)
PC is at handle_IRQ_event+0x28/0x74
LR is at handle_level_irq+0x94/0xec
pc : [<c008cc30>]    lr : [<c008e18c>]    psr: 48000113
sp : c7eede90  ip : c7eedeb0  fp : c7eedeac
r10: 0000001d  r9 : c0638ba8  r8 : 00000000
r7 : 0000005c  r6 : 00000000  r5 : 0000005c  r4 : c7a1b360
r3 : 00000000  r2 : 0000006e  r1 : c7a1b360  r0 : 0000005c
Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 10c5387d  Table: 87f48018  DAC: 00000015
[<c003b370>] (show_regs+0x0/0x50) from [<c008c738>]
(softlockup_tick+0x108/0x148)
 r5:00000104 r4:000000c7
[<c008c630>] (softlockup_tick+0x0/0x148) from [<c006f25c>]
(run_local_timers+0x1c/0x20)
 r8:c0637d08 r7:00000107 r6:297648b1 r5:c7976cc0 r4:00000000
[<c006f240>] (run_local_timers+0x0/0x20) from [<c006f2dc>]
(update_process_times+0x30/
0x60)
[<c006f2ac>] (update_process_times+0x0/0x60) from [<c0081f9c>]
(tick_sched_timer+0x90/0xc4)
 r5:c7eede48 r4:c06796d0
[<c0081f0c>] (tick_sched_timer+0x0/0xc4) from [<c007c2dc>]
(__run_hrtimer+0x30/0x70)
 r7:7fffffff r6:ffffffff r5:c0637d08 r4:c06796d0
[<c007c2ac>] (__run_hrtimer+0x0/0x70) from [<c007cf08>]
(hrtimer_interrupt+0x174/0x1e8)
 r5:00000107 r4:c06796d0
[<c007cd94>] (hrtimer_interrupt+0x0/0x1e8) from [<c004412c>]
(omap2_gp_timer_interrupt+0x28/0x34)
[<c0044104>] (omap2_gp_timer_interrupt+0x0/0x34) from [<c008cc44>]
(handle_IRQ_event+0x3c/0x74)
[<c008cc08>] (handle_IRQ_event+0x0/0x74) from [<c008e18c>]
(handle_level_irq+0x94/0xec)
 r7:0000005c r6:00000000 r5:0000005f r4:c0639b20
[<c008e0f8>] (handle_level_irq+0x0/0xec) from [<c0039068>]
(__exception_text_start+0x68/0x88)
 r5:c7eedee0 r4:0000005f
[<c0039000>] (__exception_text_start+0x0/0x88) from [<c0039a30>]
(__irq_svc+0x30/0x80)
Exception stack(0xc7eede48 to 0xc7eede90)
de40:                   0000005c c7a1b360 0000006e 00000000 c7a1b360
0000005c
de60: 00000000 0000005c 00000000 c0638ba8 0000001d c7eedeac c7eedeb0
c7eede90
de80: c008e18c c008cc30 48000113 ffffffff
 r5:d8200000 r4:ffffffff

-- 
Thanks and Regards,
Harish Kumar. V
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From freddy2_es at yahoo.com  Sun Jun 27 17:47:12 2010
From: freddy2_es at yahoo.com (=?iso-8859-1?Q?Alfredo_Quesada_S=E1nchez?=)
Date: Sun, 27 Jun 2010 14:47:12 -0700 (PDT)
Subject: Using SPI in a kernel module
In-Reply-To: <4C27C21D.6010406@softerra.com>
Message-ID: <385275.91392.qm@web33802.mail.mud.yahoo.com>

I expected to receive a call to probe as soon as i register an spi_driver, which doesn't
seem to happen. If my driver must be already registered before the machine init then it
can't be a module, it must be inside the kernel, which looks really strange.

What I don't understand is where the spi_device instance is created, and where. Looks like
it's appearing from nowhere. But even more strange is the fact that spidev only registers
its own spi_driver and according to other people it works, so the only explanation for me
is that it can only be done as long as it's part of the kernel. But even being part of the
kernel spi_driver's register should be done before the machine init, which makes no sense
imho.

Regards


--- El dom, 27/6/10, Mykhail Lodygin <mishal at softerra.com> escribi?:

De: Mykhail Lodygin <mishal at softerra.com>
Asunto: Re: Using SPI in a kernel module
Para: "Alfredo Quesada S?nchez" <freddy2_es at yahoo.com>
CC: linux-arm-kernel at lists.infradead.org
Fecha: domingo, 27 de junio, 2010 23:26





  
Invocation sequence is the same as described in ek_spi_devices. So since there is no YOUR driver in ek_spi_devices - i can't say when it would be called - for now - never.
which device? - you define it by setting .chip_select, i believe. 

You could see all calls -? just set verbosity to debug function in the
configuration.



 



      
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From harishpresent at gmail.com  Mon Jun 28 01:55:04 2010
From: harishpresent at gmail.com (Harishkumar V)
Date: Mon, 28 Jun 2010 11:25:04 +0530
Subject: soft lockup - CPU#0 stuck for 61s! problem
Message-ID: <AANLkTimqNv37LkJDyKJp9PnJapXH4naINhx-T2ysQi4D@mail.gmail.com>

Hi,

I am using an ARMv7 500 mhz board which is running linux-2.6.28-rc9 kernel.
I am running an application which does video processing on it. At times, the
board gets CPU soft lockup and become freezed.

Is their any fix/workaround for the following problem.

this is the one, i am getting in the console,

BUG: soft lockup - CPU#0 stuck for 61s! [linphone-3:764]
Modules linked in:

Pid: 764, comm:           linphone-3
CPU: 0    Not tainted  (2.6.28-rc9 #14)
PC is at handle_IRQ_event+0x28/0x74
LR is at handle_level_irq+0x94/0xec
pc : [<c008cc30>]    lr : [<c008e18c>]    psr: 48000113
sp : c7eede90  ip : c7eedeb0  fp : c7eedeac
r10: 0000001d  r9 : c0638ba8  r8 : 00000000
r7 : 0000005c  r6 : 00000000  r5 : 0000005c  r4 : c7a1b360
r3 : 00000000  r2 : 0000006e  r1 : c7a1b360  r0 : 0000005c
Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 10c5387d  Table: 87f48018  DAC: 00000015
[<c003b370>] (show_regs+0x0/0x50) from [<c008c738>]
(softlockup_tick+0x108/0x148)
 r5:00000104 r4:000000c7
[<c008c630>] (softlockup_tick+0x0/0x148) from [<c006f25c>]
(run_local_timers+0x1c/0x20)
 r8:c0637d08 r7:00000107 r6:297648b1 r5:c7976cc0 r4:00000000
[<c006f240>] (run_local_timers+0x0/0x20) from [<c006f2dc>]
(update_process_times+0x30/0x60)
[<c006f2ac>] (update_process_times+0x0/
0x60) from [<c0081f9c>] (tick_sched_timer+0x90/0xc4)
 r5:c7eede48 r4:c06796d0
[<c0081f0c>] (tick_sched_timer+0x0/0xc4) from [<c007c2dc>]
(__run_hrtimer+0x30/0x70)
 r7:7fffffff r6:ffffffff r5:c0637d08 r4:c06796d0
[<c007c2ac>] (__run_hrtimer+0x0/0x70) from [<c007cf08>]
(hrtimer_interrupt+0x174/0x1e8)
 r5:00000107 r4:c06796d0
[<c007cd94>] (hrtimer_interrupt+0x0/0x1e8) from [<c004412c>]
(omap2_gp_timer_interrupt+0x28/0x34)
[<c0044104>] (omap2_gp_timer_interrupt+0x0/0x34) from [<c008cc44>]
(handle_IRQ_event+0x3c/0x74)
[<c008cc08>] (handle_IRQ_event+0x0/0x74) from [<c008e18c>]
(handle_level_irq+0x94/0xec)
 r7:0000005c r6:00000000 r5:0000005f r4:c0639b20
[<c008e0f8>] (handle_level_irq+0x0/0xec) from [<c0039068>]
(__exception_text_start+0x68/0x88)
 r5:c7eedee0 r4:0000005f
[<c0039000>] (__exception_text_start+0x0/0x88) from [<c0039a30>]
(__irq_svc+0x30/0x80)
Exception stack(0xc7eede48 to 0xc7eede90)
de40:                   0000005c c7a1b360 0000006e 00000000 c7a1b360
0000005c
de60: 00000000 0000005c 00000000 c0638ba8 0000001d c7eedeac c7eedeb0
c7eede90
de80: c008e18c c008cc30 48000113 ffffffff
 r5:d8200000 r4:ffffffff


-- 
Thanks and Regards,
Harish Kumar. V
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From pankaj.embedded at gmail.com  Mon Jun 28 04:11:43 2010
From: pankaj.embedded at gmail.com (Pankaj Pandey)
Date: Mon, 28 Jun 2010 13:41:43 +0530
Subject: how to change MEM_SIZE ?
Message-ID: <AANLkTinksxNdkvSV9TtAsY79at9fDtQgIzioB48sAEig@mail.gmail.com>

Hi Chris,

 How to change MEM_SIZE without hardcoding it (atleast in setup.c). How is
this handled for other archs/boards? Conditional compilation?

The MEM_SIZE can be either programmed statically or passed from redboot as
ATAGS. Initially we were keeping it as static and the MEM_SIZE default value
of 16MB was changed to 128MB. Now we are using the ATAGS passed from Redboot
to set the MEM_SIZE(256MB).


Regards,
Pankaj Pandey
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From mishal at softerra.com  Sun Jun 27 17:26:53 2010
From: mishal at softerra.com (Mykhail Lodygin)
Date: Mon, 28 Jun 2010 00:26:53 +0300
Subject: Using SPI in a kernel module
In-Reply-To: <189502.64100.qm@web33802.mail.mud.yahoo.com>
References: <189502.64100.qm@web33802.mail.mud.yahoo.com>
Message-ID: <4C27C21D.6010406@softerra.com>

Invocation sequence is the same as described  in  ek_spi_devices. So since there is no YOUR driver in ek_spi_devices - i can't say when it would be called - for now - never.
which device? - you define it by setting .chip_select, i believe.

You could see all calls -  just set verbosity to debug function in the 
configuration.
On 06/27/2010 11:55 PM, Alfredo Quesada S?nchez wrote:
> There are a few compiled files in that directory (more preciselly is arch/arm/mach-at91), including:
>
> - board-XXX.c (well, the name of the board)
>
> MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES")
> 	/* Maintainer: Atmel */
> 	.phys_io	= AT91_BASE_SYS,
> 	.io_pg_offst	= (AT91_VA_BASE_SYS>>  18)&  0xfffc,
> 	.boot_params	= AT91_SDRAM_BASE + 0x100,
> 	.timer		=&at91sam926x_timer,
> 	.map_io		= ek_map_io,
> 	.init_irq	= ek_init_irq,
> 	.init_machine	= ek_board_init,
> MACHINE_END
>
> In this file there is:
>
> /*
>   * SPI devices.
>   */
> static struct spi_board_info ek_spi_devices[] = {
> 	{	/* DataFlash chip */
> 		.modalias	= "mtd_dataflash",
> 		.chip_select	= 0,
> 		.max_speed_hz	= 15 * 1000 * 1000,
> 		.bus_num	= 0,
> 	},
> };
>
> And in ek_board_init I can see a call to:
>
> /* SPI */
> at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
>
>
> This function is in at91sam9g45_devices.c (also compiled), also having:
>
> static struct resource spi0_resources[] = {
> 	[0] = {
> 		.start	= AT91SAM9G45_BASE_SPI0,
> 		.end	= AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
> 		.flags	= IORESOURCE_MEM,
> 	},
> 	[1] = {
> 		.start	= AT91SAM9G45_ID_SPI0,
> 		.end	= AT91SAM9G45_ID_SPI0,
> 		.flags	= IORESOURCE_IRQ,
> 	},
> };
>
> static struct platform_device at91sam9g45_spi0_device = {
> 	.name		= "atmel_spi",
> 	.id		= 0,
> 	.dev		= {
> 				.dma_mask		=&spi_dmamask,
> 				.coherent_dma_mask	= DMA_BIT_MASK(32),
> 	},
> 	.resource	= spi0_resources,
> 	.num_resources	= ARRAY_SIZE(spi0_resources),
> };
>
> static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
>
> static struct resource spi1_resources[] = {
> 	[0] = {
> 		.start	= AT91SAM9G45_BASE_SPI1,
> 		.end	= AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
> 		.flags	= IORESOURCE_MEM,
> 	},
> 	[1] = {
> 		.start	= AT91SAM9G45_ID_SPI1,
> 		.end	= AT91SAM9G45_ID_SPI1,
> 		.flags	= IORESOURCE_IRQ,
> 	},
> };
>
> static struct platform_device at91sam9g45_spi1_device = {
> 	.name		= "atmel_spi",
> 	.id		= 1,
> 	.dev		= {
> 				.dma_mask		=&spi_dmamask,
> 				.coherent_dma_mask	= DMA_BIT_MASK(32),
> 	},
> 	.resource	= spi1_resources,
> 	.num_resources	= ARRAY_SIZE(spi1_resources),
> };
>
> static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
>
> void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
> {
> 	int i;
> 	unsigned long cs_pin;
> 	short enable_spi0 = 0;
> 	short enable_spi1 = 0;
>
> 	/* Choose SPI chip-selects */
> 	for (i = 0; i<  nr_devices; i++) {
> 		if (devices[i].controller_data)
> 			cs_pin = (unsigned long) devices[i].controller_data;
> 		else if (devices[i].bus_num == 0)
> 			cs_pin = spi0_standard_cs[devices[i].chip_select];
> 		else
> 			cs_pin = spi1_standard_cs[devices[i].chip_select];
>
> 		if (devices[i].bus_num == 0)
> 			enable_spi0 = 1;
> 		else
> 			enable_spi1 = 1;
>
> 		/* enable chip-select pin */
> 		at91_set_gpio_output(cs_pin, 1);
>
> 		/* pass chip-select pin to driver */
> 		devices[i].controller_data = (void *) cs_pin;
> 	}
>
> 	spi_register_board_info(devices, nr_devices);
>
> 	/* Configure SPI bus(es) */
> 	if (enable_spi0) {
> 		at91_set_A_periph(AT91_PIN_PB0, 0);	/* SPI0_MISO */
> 		at91_set_A_periph(AT91_PIN_PB1, 0);	/* SPI0_MOSI */
> 		at91_set_A_periph(AT91_PIN_PB2, 0);	/* SPI0_SPCK */
>
> 		at91_clock_associate("spi0_clk",&at91sam9g45_spi0_device.dev, "spi_clk");
> 		platform_device_register(&at91sam9g45_spi0_device);
> 	}
> 	if (enable_spi1) {
> 		at91_set_A_periph(AT91_PIN_PB14, 0);	/* SPI1_MISO */
> 		at91_set_A_periph(AT91_PIN_PB15, 0);	/* SPI1_MOSI */
> 		at91_set_A_periph(AT91_PIN_PB16, 0);	/* SPI1_SPCK */
>
> 		at91_clock_associate("spi1_clk",&at91sam9g45_spi1_device.dev, "spi_clk");
> 		platform_device_register(&at91sam9g45_spi1_device);
> 	}
> }
>
> To summarize, in the end platform_device_register should be called for SPI 0 (as you can see the board has 2 SPI channels).
>
>
> So.. assuming this is working as expected, when should i see a call to my driver's probe function? and.. which spi_device will be passed as parameter? (there is only 1 registered, but for this question let's assume that i have more spi devices registered).
>
> Regards
>
>    
>> Hello
>> How about specifying correct data (for your particular
>> board) in the
>> machine-specific
>> code?(arch/your_arch/mach-your_machine/your_machine.c)
>> Basically it is enough for the system to invoke proper
>> probes.
>> Mikhail
>>      
>
>
>
>    

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From mishal at softerra.com  Sun Jun 27 18:30:24 2010
From: mishal at softerra.com (Mykhail Lodygin)
Date: Mon, 28 Jun 2010 01:30:24 +0300
Subject: Using SPI in a kernel module
In-Reply-To: <385275.91392.qm@web33802.mail.mud.yahoo.com>
References: <385275.91392.qm@web33802.mail.mud.yahoo.com>
Message-ID: <4C27D100.2030405@softerra.com>

On 06/28/2010 12:47 AM, Alfredo Quesada S?nchez wrote:
> I expected to receive a call to probe as soon as i register an 
> spi_driver, which doesn't
> seem to happen.
>
of course , you havn't fullfill the appropriate structure fields.
> If my driver must be already registered before the machine init then it
> can't be a module, it must be inside the kernel,
>
Why do you think so? spi works for many years - your driver is not the 
first and definitely not the last, please exame other drivers - you will 
see how to register.
>

> What I don't understand is where the spi_device instance is created, 
> and where. Looks like
> it's appearing from nowhere.
>
come on! drivers/spi/spi.c spi_alloc_device 
<http://lxr.linux.no/linux+*/+code=spi_alloc_device>
> But even more strange is the fact that spidev only registers
> its own spi_driver and according to other people it works, so the only 
> explanation for me
> is that it can only be done as long as it's part of the kernel. But 
> even being part of the
> kernel spi_driver's register should be done before the machine init, 
> which makes no sense
> imho.
>
Sorry but again - why do you think so? please look at several drivers 
which utilize spi_driver structure carefully - and you'll see how to do 
it yourself.
> Regards
>
>
> --- El *dom, 27/6/10, Mykhail Lodygin /<mishal at softerra.com>/* escribi?:
>
>
>     De: Mykhail Lodygin <mishal at softerra.com>
>     Asunto: Re: Using SPI in a kernel module
>     Para: "Alfredo Quesada S?nchez" <freddy2_es at yahoo.com>
>     CC: linux-arm-kernel at lists.infradead.org
>     Fecha: domingo, 27 de junio, 2010 23:26
>
>           Invocation sequence is the same as described   in   ek_spi_devices. So since there is no YOUR driver in ek_spi_devices - i can't say when it would be called - for now - never.
>     which device? - you define it by setting .chip_select, i believe.
>         
>
>     You could see all calls -  just set verbosity to debug function in
>     the configuration.
>
>

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From linux at arm.linux.org.uk  Mon Jun 28 05:00:36 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 28 Jun 2010 10:00:36 +0100
Subject: soft lockup - CPU#0 stuck for 61s! problem
In-Reply-To: <AANLkTimqNv37LkJDyKJp9PnJapXH4naINhx-T2ysQi4D@mail.gmail.com>
References: <AANLkTimqNv37LkJDyKJp9PnJapXH4naINhx-T2ysQi4D@mail.gmail.com>
Message-ID: <20100628090036.GA28510@n2100.arm.linux.org.uk>

On Mon, Jun 28, 2010 at 11:25:04AM +0530, Harishkumar V wrote:
> BUG: soft lockup - CPU#0 stuck for 61s! [linphone-3:764]
> Modules linked in:
> 
> Pid: 764, comm:           linphone-3
> CPU: 0    Not tainted  (2.6.28-rc9 #14)
> PC is at handle_IRQ_event+0x28/0x74
> LR is at handle_level_irq+0x94/0xec

That suggests a stuck IRQ.

> pc : [<c008cc30>]    lr : [<c008e18c>]    psr: 48000113
> sp : c7eede90  ip : c7eedeb0  fp : c7eedeac
> r10: 0000001d  r9 : c0638ba8  r8 : 00000000
> r7 : 0000005c  r6 : 00000000  r5 : 0000005c  r4 : c7a1b360
> r3 : 00000000  r2 : 0000006e  r1 : c7a1b360  r0 : 0000005c

which might be irq 92.

> Exception stack(0xc7eede48 to 0xc7eede90)
> de40:                   0000005c c7a1b360 0000006e 00000000 c7a1b360
> 0000005c
> de60: 00000000 0000005c 00000000 c0638ba8 0000001d c7eedeac c7eedeb0
> c7eede90
> de80: c008e18c c008cc30 48000113 ffffffff
>  r5:d8200000 r4:ffffffff

These messages should continue - and contain some further useful
information to confirm the stuck IRQ.


From dmitry.torokhov at gmail.com  Mon Jun 28 05:01:56 2010
From: dmitry.torokhov at gmail.com (Dmitry Torokhov)
Date: Mon, 28 Jun 2010 02:01:56 -0700
Subject: [PATCH v5 3/3] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <4C285FCB.3070100@samsung.com>
References: <1277101605-2435-1-git-send-email-jy0922.shim@samsung.com>
	<1277101605-2435-3-git-send-email-jy0922.shim@samsung.com>
	<20100625083019.GD8546@core.coreip.homeip.net>
	<4C285FCB.3070100@samsung.com>
Message-ID: <20100628090156.GB13523@core.coreip.homeip.net>

On Mon, Jun 28, 2010 at 05:39:39PM +0900, Joonyoung Shim wrote:
> Hi, Dmitry.
> 
> On 6/25/2010 5:30 PM, Dmitry Torokhov wrote:
> > Hi Joonyoung,
> > 
> > On Mon, Jun 21, 2010 at 03:26:45PM +0900, Joonyoung Shim wrote:
> >> This patch adds support for keypad driver running on Samsung cpus. This
> >> driver is tested on GONI and Aquila board using S5PC110 cpu.
> >>
> >> Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
> >> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> > 
> > Following my conversation with Thomas Gleixner reagrding "long playing"
> > threaded interrupt handlers I tried to convert your driver to use this
> > concept. The idea is to keep polling within IRQ thread context instead
> > of using additional work/timer structures to simplify code and ensure
> > race-free shutdown/unbind.
> > 
> > I think it was based on v4 of your driver and I'd appreciate if you could
> > give it a try.
> > 
> > Thank you.
> > 
> 
> I have tested your patch on my v5 patchset and it is working after some
> fixing. I will post v6 patchset appling your patch.

Cool, thanks.

-- 
Dmitry


From roman.tereshonkov at nokia.com  Mon Jun 28 05:12:39 2010
From: roman.tereshonkov at nokia.com (roman.tereshonkov at nokia.com)
Date: Mon, 28 Jun 2010 11:12:39 +0200
Subject: [PATCH] spi/omap2_mcspi: disable and enable chan between each
	SPI 	transfer
In-Reply-To: <4C24A182.4060009@gmail.com>
References: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com>
	<AANLkTin7mqe_zJIbyDcRPpCLaxPhl_dZQrSGua2z1nYW@mail.gmail.com>
	<4C24A182.4060009@gmail.com>
Message-ID: <E1C7579D1379824DAE67858071C810382DD8495B26@NOK-EUMSG-02.mgdnok.nokia.com>

 

>-----Original Message-----
>From: ext jason [mailto:jason77.wang at gmail.com] 
>Sent: 25 June, 2010 15:31
>To: Grant Likely
>Cc: Tereshonkov Roman (Nokia-D/Helsinki); david-b at pacbell.net; 
>spi-devel-general at lists.sourceforge.net; 
>linux-arm-kernel at lists.infradead.org
>Subject: Re: [PATCH] spi/omap2_mcspi: disable and enable chan 
>between each SPI transfer
>
>Grant Likely wrote:
>> On Thu, Jun 24, 2010 at 6:12 AM, Jason Wang 
><jason77.wang at gmail.com> wrote:
>>   
>>> In current design, the SPI channel is always enable during 
>the period
>>> of handling a SPI message, it is risky when more than one 
>SPI transfer
>>> are included in a message. Current working route like that:
>>> [
>>>  SPI channel enable
>>>  configure channel
>>>  handle transfer #1
>>>  configure channel
>>>  handle transfer #2
>>>  ...
>>>  SPI channel disable
>>> ]
>>> If we can disable channel before configure it and reenable
>>> channel after it is configured, it will be more safe.
>>>
>>> The commit a330ce2 "omap2_mcspi: Flush posted writes" make this risk
>>> to a real problem for ads7846 driver on omap3530evm. The
>>> ads7846 driver will send a SPI messge which includes,
>>> [
>>>  TX_ONLY transfer (1 byte)
>>>  RX_ONLY transfer (2 bytes)
>>>  TX_ONLY transfer (1 byte)
>>>  RX_ONLY transfer (2 bytes)
>>> ]
>>> If we don't add disable/reenable channel between TX and RX 
>transfers,
>>> the RX transfer will get wrong datas sent from slave.
>>>     
>>
>> I don't understand the problem description.  Are you talking about
>> manipulation of the SS line, or a problem with the internal state on
>> the mcspi controller device?  What is the cause of the wrong 
>data (ie.
>> is there a protocol error on the wire, or is the SPI controller not
>> performing the read correctly?)
>>
>> Thanks,
>> g.
>>
>>   
>Sorry for unclear description.  The problem is like that, when 
>a TX_ONLY 
>transfer is
>followed by a RX_ONLY transfer, the first data received in RX_ONLY 
>transfer will be
>the last data(random data) which is received in TX_ONLY 
>transfer instead 
>of a meaningful data.
>
>Thing like following logic,
>In TX_ONLY transfer:
>write data1(trigger transmit), (will receive a data 
>simultaneously, and 
>keep it in RX register)
>...
>write dataN(last data), (will receive the last random data and keep it 
>in RX register)
>in the following RX_ONLY transfer:
>change SPI controller to RX_ONLY mode,
>the RXS bit will be set to status register immediately,
>write a dummy data to TX register to trigger this session(in 
>fact this  
>trigger  doesn't take  effect),
>check the RXS bit and read the first data(the first data is the last 
>random data received in TX_ONLY transfer).
>

For me it is very strange that you have RXS bit set after TX_ONLY transmission.
The problem might be elsewhere and your solution will just mask the real problem.
Can you enable the spi debug and error logs and show them for your broken case.

Regards
Roman Tereshonkov

>
>But if we disable this channel after the TX_ONLY  transfer and 
>reenable 
>it  before  the RX_ONLY  transfer,
>the trigger action will take effect and a meaningful data  will be  
>transfered to RX register.
>
>Thanks,
>Jason.
>
>>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>>> ---
>>>  drivers/spi/omap2_mcspi.c |   16 ++++++----------
>>>  1 files changed, 6 insertions(+), 10 deletions(-)
>>>
>>> diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>>>     
>[snip]
>

From ryan at bluewatersys.com  Mon Jun 28 05:17:20 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Mon, 28 Jun 2010 21:17:20 +1200
Subject: [PATCH 3/3] at91: Add support for Bluewater Systems Snapper 
	9260/9G20 modules
In-Reply-To: <AANLkTilz0JJMe_I0sofRrDrvnAx_TljnUjAA1jS-goe7@mail.gmail.com>
References: <1277699955-9931-1-git-send-email-ryan@bluewatersys.com>	<1277699955-9931-4-git-send-email-ryan@bluewatersys.com>
	<AANLkTilz0JJMe_I0sofRrDrvnAx_TljnUjAA1jS-goe7@mail.gmail.com>
Message-ID: <4C2868A0.8080004@bluewatersys.com>

avictor.za at gmail.com wrote:
> hi Ryan,
> 
>> Add support for Bluewater Systems Snapper 9260/9G20 modules
> 
> Acked-by: Andrew Victor <linux at maxim.org.za>

Thanks Andrew. Did you want to ack patch 2/3 as well since this patch
depends on it. I can submit patch 1/3 to the patch system independently.

~Ryan



From sshtylyov at mvista.com  Mon Jun 28 06:09:34 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Mon, 28 Jun 2010 14:09:34 +0400
Subject: [PATCH v4] libata: pata_samsung_cf: Add Samsung PATA	controller
	driver
In-Reply-To: <20100626193310.GA19339@n2100.arm.linux.org.uk>
References: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
	<4C22704B.50103@pobox.com>
	<001f01cb1417$dce8f8d0$96baea70$%kim@samsung.com>
	<20100626193310.GA19339@n2100.arm.linux.org.uk>
Message-ID: <4C2874DE.7070806@ru.mvista.com>

Hello.

Russell King - ARM Linux wrote:

>> How do you think?
>> May I send this to your patch tracking system?
>> Or...how should I handle this?

> If Jeff is happy, then I'm happy.  However, shouldn't it also have Ben's
> ack?

    I for one still have comments to be addressed, will post in a jiffy...

MBR, Sergei


From sshtylyov at mvista.com  Mon Jun 28 06:12:06 2010
From: sshtylyov at mvista.com (Sergei Shtylyov)
Date: Mon, 28 Jun 2010 14:12:06 +0400
Subject: [PATCH v4] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
References: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <4C287576.6050506@ru.mvista.com>

Hello.

Kukjin Kim wrote:

> From: Abhilash Kesavan <a.kesavan at samsung.com>

> Adds support for the Samsung PATA controller. This driver is based on the
> Libata subsystem and references the earlier patches sent for IDE subsystem.

> Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>

[...]

> diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
> new file mode 100644
> index 0000000..aeb2825
> --- /dev/null
> +++ b/drivers/ata/pata_samsung_cf.c
> @@ -0,0 +1,735 @@
[...]
> +static unsigned long
> +pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
> +{
> +	int t1;
> +	int t2;
> +	int t2i;
> +	ulong piotime;
> +
> +	t1 = ata->setup;
> +	t2 = ata->act8b;
> +	t2i = ata->rec8b;

    Could be initializers...

[...]

> +/*
> + * pata_s3c_data_xfer - Transfer data by PIO
> + */
> +unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char *buf,
> +				unsigned int buflen, int rw)
> +{
> +	struct ata_port *ap = dev->link->ap;
> +	struct s3c_ide_info *info = ap->host->private_data;
> +	void __iomem *data_addr = ap->ioaddr.data_addr;
> +	unsigned int words = buflen >> 1, i;
> +	u16 *data_ptr = (u16 *)buf;
> +
> +	/* Requires wait same as in ata_inb/ata_outb */
> +	if (rw == READ)
> +		for (i = 0; i < words; i++, data_ptr++) {
> +			wait_for_host_ready(info);
> +			(void) readw(data_addr);
> +			wait_for_host_ready(info);
> +			*data_ptr = readw(info->ide_addr
> +					+ S3C_ATA_PIO_RDATA);
> +		}
> +	else
> +		for (i = 0; i < words; i++, data_ptr++) {
> +			wait_for_host_ready(info);
> +			writew(*data_ptr, data_addr);
> +		}
> +
> +	if (buflen & 0x01) {
> +		dev_err(ap->dev, "unexpected trailing data\n");
> +		return -EINVAL;

    This method should return number of bytes consumed, never error...

> +	}
> +
> +	return words << 1;
> +}

[...]

> +/*
> + * pata_s3c_devchk - PATA device presence detection
> + */
> +static unsigned int pata_s3c_devchk(struct ata_port *ap,
> +				unsigned int device)
> +{
> +	struct ata_ioports *ioaddr = &ap->ioaddr;
> +	u8 nsect, lbal;
> +
> +	ap->ops->sff_dev_select(ap, device);

    Can call pata_s3c_dev_select() directly...

> +/*
> + * pata_s3c_wait_after_reset - wait for devices to become ready after reset
> + */
> +static int pata_s3c_wait_after_reset(struct ata_link *link,
> +		unsigned int devmask, unsigned long deadline)
> +{
> +	struct ata_port *ap = link->ap;
> +	struct ata_ioports *ioaddr = &ap->ioaddr;
> +	unsigned int dev0 = devmask & (1 << 0);
> +	unsigned int dev1 = devmask & (1 << 1);
> +	int rc, ret = 0;
> +
> +	msleep(ATA_WAIT_AFTER_RESET);
> +
> +	/* always check readiness of the master device */
> +	rc = ata_sff_wait_ready(link, deadline);
> +	if (rc)
> +		return rc;
> +
> +	/* if device 1 was found in ata_devchk, wait for register
> +	 * access briefly, then wait for BSY to clear.
> +	 */
> +	if (dev1) {
> +		int i;
> +
> +		ap->ops->sff_dev_select(ap, 1);

    Ditto.

> +
> +		for (i = 0; i < 2; i++) {
> +			u8 nsect, lbal;
> +
> +			nsect = ata_inb(ap->host, ioaddr->nsect_addr);
> +			lbal = ata_inb(ap->host, ioaddr->lbal_addr);
> +			if ((nsect == 1) && (lbal == 1))
> +				break;
> +			msleep(50);	/* give drive a breather */
> +		}
> +
> +		rc = ata_sff_wait_ready(link, deadline);
> +		if (rc) {
> +			if (rc != -ENODEV)
> +				return rc;
> +			ret = rc;
> +		}
> +	}
> +

    Should have copied the original commant here, cause I dount that this 
drive selection trickery is indeed necessary...

> +	ap->ops->sff_dev_select(ap, 0);
> +	if (dev1)
> +		ap->ops->sff_dev_select(ap, 1);
> +	if (dev0)
> +		ap->ops->sff_dev_select(ap, 0);

    Ditto.

> +/*
> + * pata_s3c_softreset - reset host port via ATA SRST
> + */
> +static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
> +			 unsigned long deadline)
> +{
> +	struct ata_port *ap = link->ap;
> +	unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;

    I don't see where you set this flag, hence the check seems useless.

> +	unsigned int devmask = 0;
> +	int rc;
> +	u8 err;
> +
> +	/* determine if device 0/1 are present */
> +	if (pata_s3c_devchk(ap, 0))
> +		devmask |= (1 << 0);
> +	if (slave_possible && pata_s3c_devchk(ap, 1))
> +		devmask |= (1 << 1);
> +
> +	/* select device 0 again */
> +	ap->ops->sff_dev_select(ap, 0);

    Can call pata_s3c_dev_select() directly...

> +
> +	/* issue bus reset */
> +	rc = pata_s3c_bus_softreset(ap, devmask, deadline);
> +	/* if link is occupied, -ENODEV too is an error */
> +	if (rc && (rc != -ENODEV || sata_scr_valid(link))) {

    sata_scr_valid() doesn't apply to your PATA driver, no need to call it.

> +static void pata_s3c_hwinit(struct s3c_ide_info *info,
> +				struct s3c_ide_platdata *pdata)
> +{
> +	switch (info->cpu_type) {
> +	case TYPE_S3C64XX:
> +		/* Configure as big endian */
> +		pata_s3c_cfg_mode(info->sfr_addr);
> +		pata_s3c_set_endian(info->ide_addr, 1);
> +		pata_s3c_enable(info->ide_addr, true);
> +		msleep(100);
> +
> +		/* Remove IRQ Status */
> +		writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
> +		writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
> +	break;

    Mis-indented: one more tab needed.

> +
> +	case TYPE_S5PC100:
> +		pata_s3c_cfg_mode(info->sfr_addr);

    There should be a comment like /* FALLTHRU */ if *break* is omitted.

> +	case TYPE_S5PV210:
> +		/* Configure as little endian */
> +		pata_s3c_set_endian(info->ide_addr, 0);
> +		pata_s3c_enable(info->ide_addr, true);
> +		msleep(100);
> +
> +		/* Remove IRQ Status */
> +		writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
> +		writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
> +	break;

    Mis-indented.

> +static int __devinit pata_s3c_probe(struct platform_device *pdev)

    Is this device really hot-pluggable? Shouldn't this be '__init' instead?

> +{
> +	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
> +	struct device *dev = &pdev->dev;
> +	struct s3c_ide_info *info;
> +	struct resource *res;
> +	struct ata_port *ap;
> +	struct ata_host *host;
> +	enum s3c_cpu_type cpu_type;
> +	int ret;
> +
> +	cpu_type = platform_get_device_id(pdev)->driver_data;
> +
> +	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
> +	if (!info) {
> +		dev_err(dev, "failed to allocate memory for device data\n");
> +		return -ENOMEM;
> +	}
> +
> +	info->irq = platform_get_irq(pdev, 0);
> +	if (info->irq < 0) {
> +		dev_err(dev, "could not obtain irq number\n");

    You driver permits working without IRQ -- why require an IRQ resource even 
if there's no IRQ?

[...]

> +	if (!info->irq) {

    Should be (info->irq <= 0) instead, I think, with the above check removed.

> +		ap->flags |= ATA_FLAG_PIO_POLLING;
> +		ata_port_desc(ap, "no IRQ, using PIO polling\n");
> +	}
> +

[...]

> +static struct platform_driver pata_s3c_driver = {
> +	.probe		= pata_s3c_probe,

    If this function will be '__init', this needs to be removed.

[...]

> +static int __init pata_s3c_init(void)
> +{
> +	return platform_driver_register(&pata_s3c_driver);

    I'd coinsider platform_driver_probe() -- this device doesn't seem to be 
hot-pluggable...

MBR, Sergei


From linux at arm.linux.org.uk  Mon Jun 28 06:29:31 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Mon, 28 Jun 2010 11:29:31 +0100
Subject: soft lockup - CPU#0 stuck for 61s! problem
In-Reply-To: <AANLkTin_iY-7nUwtf1q7Fz4qdnkA0BUktEC6WwCiQdOX@mail.gmail.com>
References: <AANLkTimqNv37LkJDyKJp9PnJapXH4naINhx-T2ysQi4D@mail.gmail.com>
	<20100628090036.GA28510@n2100.arm.linux.org.uk>
	<AANLkTin_iY-7nUwtf1q7Fz4qdnkA0BUktEC6WwCiQdOX@mail.gmail.com>
Message-ID: <20100628102931.GA30050@n2100.arm.linux.org.uk>

On Mon, Jun 28, 2010 at 03:50:24PM +0530, Harishkumar V wrote:
> Will capture the further messages and mail u. Why an IRQ got struck, is
> their a way to handle this....

Normally, the kernel will disable the interrupt so the system can
continue to (mostly) function.

However, people like to return IRQ_HANDLED from interrupt handlers,
even when they've found nothing to do.  This prevents the kernel from
rescuing you from the stuck-IRQ problem.  Interrupt handlers are
supposed to return IRQ_HANDLED if they did something to handle the IRQ,
or IRQ_NONE if they found nothing to do.

I can't say much more than that - I've no idea what hardware you're
running the kernel on, and therefore I can't guess what IRQ92 might be.


From broonie at opensource.wolfsonmicro.com  Mon Jun 28 06:30:30 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Mon, 28 Jun 2010 11:30:30 +0100
Subject: [PATCH] ASoC: DaVinci: Added support for cpu clocking I2S
In-Reply-To: <1277707487-3371-1-git-send-email-lamiaposta71@gmail.com>
References: <1277707487-3371-1-git-send-email-lamiaposta71@gmail.com>
Message-ID: <20100628103030.GB14247@rakim.wolfsonmicro.main>

On Mon, Jun 28, 2010 at 08:44:46AM +0200, Raffaele Recalcati wrote:
> From: Raffaele Recalcati <raffaele.recalcati at bticino.it>

It's still very hard to understand what this patch is supposed to do.
As previously mentioned this would probably be a lot clearer if you
split this into multiple patches, for example one adding support for the
fast clock mode, one adding support for selecting the pin used for any
external clock and then further patches with any other changes.

I strongly suggest looking at the commit messages for other patches in
the kernel and trying to follow a similar style.

>     Added audio playback support with [frame sync master - clock master] mode
>     and with [frame sync master - clock slave].

What are these modes - which clock are you talking about?

>        i2s_fast_clock switch can be used to have better approximate or
>        symmetric waveforms.

Why would someone choose not to use this?

>        clk_input_pin board info can be used to select it depending on hw
>        connections

>     3. We haven't changed the evmdm365 support (due also to CPLD that doesn't
>                                                 help to understand)
>         We don't know in this mode if audio stereo works on evmdm365.
>         Probably it does.

This is what makes me unsure if you're trying to add new modes or not -
if you're adding new modes then I'd expect that existing boards would be
unaffected with any changes to use the new feature being easily
seperable.

> +	/*
> +	 * This define works when both clock and FS are output for the cpu
> +	 * and makes clock very fast (FS is not simmetrical, but sampling

symmetrical.

> +	 * frequency is better approximated
> +	 */
> +	int i2s_fast_clock;

Is this a bool?

> +	/* To be used when cpu gets clock from extenal pin */
> +	int clk_input_pin;
> +

How would one use this?

>  	case SND_SOC_DAIFMT_CBM_CFS:
> -		/* McBSP CLKR pin is the input for the Sample Rate Generator.
> -		 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
> -		pcr = DAVINCI_MCBSP_PCR_SCLKME |
> -			DAVINCI_MCBSP_PCR_FSXM |
> -			DAVINCI_MCBSP_PCR_FSRM;
> +		pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
> +		if (dev->clk_input_pin == MCBSP_CLKS)
> +			pcr |= DAVINCI_MCBSP_PCR_CLKXM |
> +				DAVINCI_MCBSP_PCR_CLKRM;
> +		else
> +			/*
> +			 * McBSP CLKR pin is the input for the Sample Rate
> +			 * Generator.
> +			 * McBSP FSR and FSX are driven by the Sample Rate
> +			 * Generator.
> +			 */
> +			pcr |= DAVINCI_MCBSP_PCR_SCLKME;

This looks like you need a switch statement for the clock selection.

> +static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
> +				int div_id, int div)
> +{
> +	struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
> +	int srgr;
> +
> +	dev->clk_div = div;
> +	return 0;
> +}
> +

I would add a clock ID here in case someone wants to configure another
clock in the patch.

> +	if (master == SND_SOC_DAIFMT_CBS_CFS) {

Use a switch staetment for this too.

> +		clk = clk_get(NULL, "pll1_sysclk6");

You're doing a clk_get() every time you go through here but never
freeing it - it would seem better to just do the clk_get() at startup.
I'd also expect this to be doing a clk_get() using the struct device for
the DAI so that the driver can function even if the clock tree for a new
SoC is different.

> +		if (clk)
> +			freq = clk_get_rate(clk);

clk_get() returns an error pointer on error, not NULL, and...

> +		freq = 122000000; /* FIXME ask to Texas */

...this presumably ought to be in an else clause (or perhaps just not
using this clocking at all if you can't find the clock?).

> +	} else if (master == SND_SOC_DAIFMT_CBM_CFS) {
> +		/* Clock given on CLKS */

What if the user selected a different clock source?

> +		if (master == SND_SOC_DAIFMT_CBS_CFS ||
> +				master == SND_SOC_DAIFMT_CBS_CFM) {

Again, switch statement.

> +	if (master == SND_SOC_DAIFMT_CBS_CFS ||
> +			master == SND_SOC_DAIFMT_CBS_CFM) {

Here too.


From mcuelenaere at gmail.com  Mon Jun 28 07:28:57 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Mon, 28 Jun 2010 13:28:57 +0200
Subject: [PATCH v3 05/12] s3c-fb: Add support for display panning
In-Reply-To: <1277712538-23188-6-git-send-email-p.osciak@samsung.com>
References: <1277712538-23188-1-git-send-email-p.osciak@samsung.com>
	<1277712538-23188-6-git-send-email-p.osciak@samsung.com>
Message-ID: <4C288779.8040702@gmail.com>

 Op 28-06-10 10:08, Pawel Osciak schreef:
> Supports all bpp modes.
>
> The PRTCON register is used to disable in-hardware updates of registers
> that store start and end addresses of framebuffer memory. This prevents
> display corruption in case we do not make it before VSYNC with updating
> them atomically. With this feature there is no need to wait for a VSYNC
> interrupt before each such update.
>
> Signed-off-by: Pawel Osciak <p.osciak at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>  arch/arm/plat-samsung/include/plat/regs-fb.h |    5 ++
>  drivers/video/s3c-fb.c                       |   71 ++++++++++++++++++++++++++
>  2 files changed, 76 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
> index ac10013..f454e32 100644
> --- a/arch/arm/plat-samsung/include/plat/regs-fb.h
> +++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
> @@ -112,6 +112,11 @@
>  #define VIDCON2_ORGYCbCr			(1 << 8)
>  #define VIDCON2_YUVORDCrCb			(1 << 7)
>  
> +/* PRTCON (S3C6410, S5PC100) */
> +
> +#define PRTCON					(0x0c)
> +#define PRTCON_PROTECT				(1 << 11)
> +
>  /* VIDTCON0 */
>  
>  #define VIDTCON0_VBPDE_MASK			(0xff << 24)
> diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
> index 59ac76a..4f3680d 100644
> --- a/drivers/video/s3c-fb.c
> +++ b/drivers/video/s3c-fb.c
> @@ -71,6 +71,7 @@ struct s3c_fb;
>   * @buf_end: Offset of buffer end registers.
>   * @osd: The base for the OSD registers.
>   * @palette: Address of palette memory, or 0 if none.
> + * @has_prtcon: Set if has PRTCON register.
>   */
>  struct s3c_fb_variant {
>  	unsigned int	is_2443:1;
> @@ -85,6 +86,8 @@ struct s3c_fb_variant {
>  	unsigned short	osd;
>  	unsigned short	osd_stride;
>  	unsigned short	palette[S3C_FB_MAX_WIN];
> +
> +	unsigned int	has_prtcon:1;
>  };
>  
>  /**
> @@ -379,6 +382,9 @@ static int s3c_fb_set_par(struct fb_info *info)
>  
>  	info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
>  
> +	info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
> +	info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;

No need for the '? 1 : 0'

> +
>  	/* disable the window whilst we update it */
>  	writel(0, regs + WINCON(win_no));
>  
> @@ -735,6 +741,66 @@ static int s3c_fb_blank(int blank_mode, struct fb_info *info)
>  	return 0;
>  }
>  
> +/**
> + * s3c_fb_pan_display() - Pan the display.
> + *
> + * Note that the offsets can be written to the device at any time, as their
> + * values are latched at each vsync automatically. This also means that only
> + * the last call to this function will have any effect on next vsync, but
> + * there is no need to sleep waiting for it to prevent tearing.
> + *
> + * @var: The screen information to verify.
> + * @info: The framebuffer device.
> + */
> +static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
> +			      struct fb_info *info)
> +{
> +	struct s3c_fb_win *win	= info->par;
> +	struct s3c_fb *sfb	= win->parent;
> +	void __iomem *buf	= sfb->regs + win->index * 8;
> +	unsigned int start_byte_offset, end_byte_offset;
> +
> +	/* Offset in bytes to the start of the displayed area */
> +	start_byte_offset = var->yoffset * info->fix.line_length;
> +	/* X offset depends on the current bpp */
> +	if (info->var.bits_per_pixel >= 8) {
> +		start_byte_offset +=
> +			var->xoffset * (info->var.bits_per_pixel >> 3);
> +	} else {
> +		switch (info->var.bits_per_pixel) {
> +		case 4:
> +			start_byte_offset += var->xoffset >> 1;
> +			break;
> +		case 2:
> +			start_byte_offset += var->xoffset >> 2;
> +			break;
> +		case 1:
> +			start_byte_offset += var->xoffset >> 3;
> +			break;
> +		default:
> +			dev_err(sfb->dev, "invalid bpp\n");
> +			return -EINVAL;
> +		}
> +	}
> +	/* Offset in bytes to the end of the displayed area */
> +	end_byte_offset = start_byte_offset + var->yres * info->fix.line_length;
> +
> +	/* Temporarily turn off per-vsync update from shadow registers until
> +	 * both start and end addresses are updated to prevent corruption */
> +	if (sfb->variant.has_prtcon)
> +		writel(PRTCON_PROTECT, sfb->regs + PRTCON);
> +
> +	writel(info->fix.smem_start + start_byte_offset,
> +		buf + sfb->variant.buf_start);
> +	writel(info->fix.smem_start + end_byte_offset,
> +		buf + sfb->variant.buf_end);
> +
> +	if (sfb->variant.has_prtcon)
> +		writel(0, sfb->regs + PRTCON);
> +
> +	return 0;
> +}
> +
>  static struct fb_ops s3c_fb_ops = {
>  	.owner		= THIS_MODULE,
>  	.fb_check_var	= s3c_fb_check_var,
> @@ -744,6 +810,7 @@ static struct fb_ops s3c_fb_ops = {
>  	.fb_fillrect	= cfb_fillrect,
>  	.fb_copyarea	= cfb_copyarea,
>  	.fb_imageblit	= cfb_imageblit,
> +	.fb_pan_display	= s3c_fb_pan_display,
>  };
>  
>  /**
> @@ -1243,6 +1310,8 @@ static struct s3c_fb_driverdata s3c_fb_data_64xx __devinitdata = {
>  			[3] = 0x320,
>  			[4] = 0x340,
>  		},
> +
> +		.has_prtcon	= 1,
>  	},
>  	.win[0]	= &s3c_fb_data_64xx_wins[0],
>  	.win[1]	= &s3c_fb_data_64xx_wins[1],
> @@ -1271,6 +1340,8 @@ static struct s3c_fb_driverdata s3c_fb_data_s5pc100 __devinitdata = {
>  			[3] = 0x3000,
>  			[4] = 0x3400,
>  		},
> +
> +		.has_prtcon	= 1,
>  	},
>  	.win[0]	= &s3c_fb_data_64xx_wins[0],
>  	.win[1]	= &s3c_fb_data_64xx_wins[1],


-- 
Maurus Cuelenaere



From jy0922.shim at samsung.com  Mon Jun 28 07:34:09 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Mon, 28 Jun 2010 20:34:09 +0900
Subject: [PATCH v6 0/3] Add samsung keypad
Message-ID: <4C2888B1.7080704@samsung.com>

This is patch v6 series to add Samsung keypad.

Changes since v1:
- Include linux/gpio.h instead of mach/gpio.h
- Switch to dev_pm_ops in the samsung keypad driver

Changes since v2:
- Add keypad device types to remove platform specific #ifdef
- Remove unnecessary include and checking codes.
- Rename from 'kp' to 'keypad'
- Rename keypad registers definition
- Modify 'rep' variable declaration

Changes since v3:
- Use schedule_delayed_work and remove timer
- Modify memory alloc codes
- Add MODULE_ALIAS() and missing error printk
- Change from rep to no_autorepeat and it's type to bool
- Add report EV_MSC/MSC_SCAN and wakeup control
- Remove s3c_set_platdata() call because there is not yet

Changes since v4:
- Add and use samsung_keypad_setname function
- Add more specific gpio comments

Changes since v5:
- Add Dmitry patch about threaded IRQs and some fixing
- Remove clock gating for irq

Joonyoung Shim (3):
      ARM: SAMSUNG: Add keypad device support
      ARM: S5PV210: Add keypad device helpers
      input: samsung-keypad - Add samsung keypad driver

 arch/arm/mach-s5pv210/Kconfig                    |    5 +
 arch/arm/mach-s5pv210/Makefile                   |    1 +
 arch/arm/mach-s5pv210/cpu.c                      |    4 +
 arch/arm/mach-s5pv210/include/mach/map.h         |    3 +
 arch/arm/mach-s5pv210/setup-keypad.c             |   34 ++
 arch/arm/plat-samsung/Kconfig                    |    5 +
 arch/arm/plat-samsung/Makefile                   |    1 +
 arch/arm/plat-samsung/dev-keypad.c               |   58 +++
 arch/arm/plat-samsung/include/plat/devs.h        |    2 +
 arch/arm/plat-samsung/include/plat/keypad-core.h |   31 ++
 arch/arm/plat-samsung/include/plat/keypad.h      |   59 +++
 drivers/input/keyboard/Kconfig                   |    9 +
 drivers/input/keyboard/Makefile                  |    1 +
 drivers/input/keyboard/samsung-keypad.c          |  491 ++++++++++++++++++++++
 14 files changed, 704 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pv210/setup-keypad.c
 create mode 100644 arch/arm/plat-samsung/dev-keypad.c
 create mode 100644 arch/arm/plat-samsung/include/plat/keypad-core.h
 create mode 100644 arch/arm/plat-samsung/include/plat/keypad.h
 create mode 100644 drivers/input/keyboard/samsung-keypad.c


From jy0922.shim at samsung.com  Mon Jun 28 07:33:42 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Mon, 28 Jun 2010 20:33:42 +0900
Subject: [PATCH v6 1/3] ARM: SAMSUNG: Add keypad device support
Message-ID: <1277724824-13308-1-git-send-email-jy0922.shim@samsung.com>

This patch adds samsung keypad device definition for samsung cpus.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/plat-samsung/Kconfig               |    5 ++
 arch/arm/plat-samsung/Makefile              |    1 +
 arch/arm/plat-samsung/dev-keypad.c          |   58 ++++++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/devs.h   |    2 +
 arch/arm/plat-samsung/include/plat/keypad.h |   59 +++++++++++++++++++++++++++
 5 files changed, 125 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/plat-samsung/dev-keypad.c
 create mode 100644 arch/arm/plat-samsung/include/plat/keypad.h

diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 2753fb3..bd007e3 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -227,6 +227,11 @@ config SAMSUNG_DEV_TS
 	help
 	    Common in platform device definitions for touchscreen device
 
+config SAMSUNG_DEV_KEYPAD
+	bool
+	help
+	  Compile in platform device definitions for keypad
+
 # DMA
 
 config S3C_DMA
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index b1d82cc..8269d80 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_S3C_DEV_RTC)	+= dev-rtc.o
 
 obj-$(CONFIG_SAMSUNG_DEV_ADC)	+= dev-adc.o
 obj-$(CONFIG_SAMSUNG_DEV_TS)	+= dev-ts.o
+obj-$(CONFIG_SAMSUNG_DEV_KEYPAD)	+= dev-keypad.o
 
 # DMA support
 
diff --git a/arch/arm/plat-samsung/dev-keypad.c b/arch/arm/plat-samsung/dev-keypad.c
new file mode 100644
index 0000000..679b444
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-keypad.c
@@ -0,0 +1,58 @@
+/*
+ * linux/arch/arm/plat-samsung/dev-keypad.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/keypad.h>
+
+static struct resource samsung_keypad_resources[] = {
+	[0] = {
+		.start	= SAMSUNG_PA_KEYPAD,
+		.end	= SAMSUNG_PA_KEYPAD + 0x20 - 1,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start	= IRQ_KEYPAD,
+		.end	= IRQ_KEYPAD,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+struct platform_device samsung_device_keypad = {
+	.name		= "samsung-keypad",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(samsung_keypad_resources),
+	.resource	= samsung_keypad_resources,
+};
+
+void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
+{
+	struct samsung_keypad_platdata *npd;
+
+	if (!pd) {
+		printk(KERN_ERR "%s: no platform data\n", __func__);
+		return;
+	}
+
+	npd = kmemdup(pd, sizeof(struct samsung_keypad_platdata), GFP_KERNEL);
+	if (!npd)
+		printk(KERN_ERR "%s: no memory for platform data\n", __func__);
+
+	if (!npd->cfg_gpio)
+		npd->cfg_gpio = samsung_keypad_cfg_gpio;
+
+	samsung_device_keypad.dev.platform_data = npd;
+}
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index e6144e4..6d9f01b 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -100,6 +100,8 @@ extern struct platform_device s5pc100_device_iis0;
 extern struct platform_device s5pc100_device_iis1;
 extern struct platform_device s5pc100_device_iis2;
 
+extern struct platform_device samsung_device_keypad;
+
 /* s3c2440 specific devices */
 
 #ifdef CONFIG_CPU_S3C2440
diff --git a/arch/arm/plat-samsung/include/plat/keypad.h b/arch/arm/plat-samsung/include/plat/keypad.h
new file mode 100644
index 0000000..f87646b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/keypad.h
@@ -0,0 +1,59 @@
+/*
+ * linux/arch/arm/plat-samsung/include/plat/keypad.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ * Samsung Platform - Keypad platform data definitions
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __PLAT_SAMSUNG_KEYPAD_H
+#define __PLAT_SAMSUNG_KEYPAD_H
+
+#include <linux/input/matrix_keypad.h>
+
+#define SAMSUNG_MAX_ROWS	8
+#define SAMSUNG_MAX_COLS	8
+
+/**
+ * struct samsung_keypad_platdata - Platform device data for Samsung Keypad.
+ * @keymap_data: pointer to &matrix_keymap_data.
+ * @rows: number of keypad row supported.
+ * @cols: number of keypad col supported.
+ * @no_autorepeat: disable key autorepeat.
+ * @wakeup: controls whether the device should be set up as wakeup source.
+ * @cfg_gpio: configure the GPIO.
+ *
+ * Initialisation data specific to either the machine or the platform
+ * for the device driver to use or call-back when configuring gpio.
+ */
+struct samsung_keypad_platdata {
+	const struct matrix_keymap_data	*keymap_data;
+	unsigned int rows;
+	unsigned int cols;
+	bool no_autorepeat;
+	bool wakeup;
+
+	void (*cfg_gpio)(unsigned int rows, unsigned int cols);
+};
+
+/**
+ * samsung_keypad_set_platdata - Set platform data for Samsung Keypad device.
+ * @pd: Platform data to register to device.
+ *
+ * Register the given platform data for use with Samsung Keypad device.
+ * The call will copy the platform data, so the board definitions can
+ * make the structure itself __initdata.
+ */
+extern void samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd);
+
+/* defined by architecture to configure gpio. */
+extern void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols);
+
+#endif /* __PLAT_SAMSUNG_KEYPAD_H */
-- 
1.7.0.4



From jy0922.shim at samsung.com  Mon Jun 28 07:33:43 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Mon, 28 Jun 2010 20:33:43 +0900
Subject: [PATCH v6 2/3] ARM: S5PV210: Add keypad device helpers
In-Reply-To: <1277724824-13308-1-git-send-email-jy0922.shim@samsung.com>
References: <1277724824-13308-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1277724824-13308-2-git-send-email-jy0922.shim@samsung.com>

This patch adds the keypad device platform helpers for S5PV210 cpu.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 arch/arm/mach-s5pv210/Kconfig                    |    5 +++
 arch/arm/mach-s5pv210/Makefile                   |    1 +
 arch/arm/mach-s5pv210/cpu.c                      |    4 ++
 arch/arm/mach-s5pv210/include/mach/map.h         |    3 ++
 arch/arm/mach-s5pv210/setup-keypad.c             |   34 ++++++++++++++++++++++
 arch/arm/plat-samsung/include/plat/keypad-core.h |   31 ++++++++++++++++++++
 6 files changed, 78 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-s5pv210/setup-keypad.c
 create mode 100644 arch/arm/plat-samsung/include/plat/keypad-core.h

diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0761eac..692d01c 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -32,6 +32,11 @@ config S5PV210_SETUP_FB_24BPP
 	help
           Common setup code for S5PV210 with an 24bpp RGB display helper.
 
+config S5PV210_SETUP_KEYPAD
+	bool
+	help
+	  Common setup code for keypad.
+
 config S5PV210_SETUP_SDHCI
         bool
         select S5PV210_SETUP_SDHCI_GPIO
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 30be9a6..aae592a 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -31,5 +31,6 @@ obj-$(CONFIG_S5PC110_DEV_ONENAND) += dev-onenand.o
 obj-$(CONFIG_S5PV210_SETUP_FB_24BPP)	+= setup-fb-24bpp.o
 obj-$(CONFIG_S5PV210_SETUP_I2C1) 	+= setup-i2c1.o
 obj-$(CONFIG_S5PV210_SETUP_I2C2) 	+= setup-i2c2.o
+obj-$(CONFIG_S5PV210_SETUP_KEYPAD)	+= setup-keypad.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_S5PV210_SETUP_SDHCI_GPIO)	+= setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 411a4a9..94c632b 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -33,6 +33,7 @@
 #include <plat/clock.h>
 #include <plat/s5pv210.h>
 #include <plat/iic-core.h>
+#include <plat/keypad-core.h>
 #include <plat/sdhci.h>
 
 /* Initial IO mappings */
@@ -91,6 +92,9 @@ void __init s5pv210_map_io(void)
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
 	s3c_i2c2_setname("s3c2440-i2c");
+
+	/* Use s5pv210-keypad instead of samsung-keypad */
+	samsung_keypad_setname("s5pv210-keypad");
 }
 
 void __init s5pv210_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 34eb168..e2f6e2a 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -32,6 +32,8 @@
 #define S5PV210_PA_SPI0		0xE1300000
 #define S5PV210_PA_SPI1		0xE1400000
 
+#define S5PV210_PA_KEYPAD	(0xE1600000)
+
 #define S5PV210_PA_IIC0		(0xE1800000)
 #define S5PV210_PA_IIC1		(0xFAB00000)
 #define S5PV210_PA_IIC2		(0xE1A00000)
@@ -104,5 +106,6 @@
 #define S3C_PA_WDT		S5PV210_PA_WATCHDOG
 
 #define SAMSUNG_PA_ADC		S5PV210_PA_ADC
+#define SAMSUNG_PA_KEYPAD	S5PV210_PA_KEYPAD
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/setup-keypad.c b/arch/arm/mach-s5pv210/setup-keypad.c
new file mode 100644
index 0000000..37b2790
--- /dev/null
+++ b/arch/arm/mach-s5pv210/setup-keypad.c
@@ -0,0 +1,34 @@
+/*
+ * linux/arch/arm/mach-s5pv210/setup-keypad.c
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/gpio.h>
+#include <plat/gpio-cfg.h>
+
+void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
+{
+	unsigned int gpio, end;
+
+	/* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
+	end = S5PV210_GPH3(rows);
+	for (gpio = S5PV210_GPH3(0); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+
+	/* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
+	end = S5PV210_GPH2(cols);
+	for (gpio = S5PV210_GPH2(0); gpio < end; gpio++) {
+		s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
+		s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+	}
+}
diff --git a/arch/arm/plat-samsung/include/plat/keypad-core.h b/arch/arm/plat-samsung/include/plat/keypad-core.h
new file mode 100644
index 0000000..d513e1b
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/keypad-core.h
@@ -0,0 +1,31 @@
+/*
+ * linux/arch/arm/plat-samsung/include/plat/keypad-core.h
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ *
+ * Samsung keypad controller core function
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __ASM_ARCH_KEYPAD_CORE_H
+#define __ASM_ARCH_KEYPAD_CORE_H
+
+/* These function are only for use with the core support code, such as
+ * the cpu specific initialisation code
+ */
+
+/* re-define device name depending on support. */
+static inline void samsung_keypad_setname(char *name)
+{
+#ifdef CONFIG_SAMSUNG_DEV_KEYPAD
+	samsung_device_keypad.name = name;
+#endif
+}
+
+#endif /* __ASM_ARCH_KEYPAD_CORE_H */
-- 
1.7.0.4



From jy0922.shim at samsung.com  Mon Jun 28 07:33:44 2010
From: jy0922.shim at samsung.com (Joonyoung Shim)
Date: Mon, 28 Jun 2010 20:33:44 +0900
Subject: [PATCH v6 3/3] input: samsung-keypad - Add samsung keypad driver
In-Reply-To: <1277724824-13308-1-git-send-email-jy0922.shim@samsung.com>
References: <1277724824-13308-1-git-send-email-jy0922.shim@samsung.com>
Message-ID: <1277724824-13308-3-git-send-email-jy0922.shim@samsung.com>

This patch adds support for keypad driver running on Samsung cpus. This
driver is tested on GONI and Aquila board using S5PC110 cpu.

Signed-off-by: Joonyoung Shim <jy0922.shim at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
 drivers/input/keyboard/Kconfig          |    9 +
 drivers/input/keyboard/Makefile         |    1 +
 drivers/input/keyboard/samsung-keypad.c |  491 +++++++++++++++++++++++++++++++
 3 files changed, 501 insertions(+), 0 deletions(-)
 create mode 100644 drivers/input/keyboard/samsung-keypad.c

diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index d8fa5d7..bf6a50f 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -342,6 +342,15 @@ config KEYBOARD_PXA930_ROTARY
 	  To compile this driver as a module, choose M here: the
 	  module will be called pxa930_rotary.
 
+config KEYBOARD_SAMSUNG
+	tristate "Samsung keypad support"
+	depends on SAMSUNG_DEV_KEYPAD
+	help
+	  Say Y here if you want to use the Samsung keypad.
+
+	  To compile this driver as a module, choose M here: the
+	  module will be called samsung-keypad.
+
 config KEYBOARD_STOWAWAY
 	tristate "Stowaway keyboard"
 	select SERIO
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 4596d0c..8f973ed 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -32,6 +32,7 @@ obj-$(CONFIG_KEYBOARD_OPENCORES)	+= opencores-kbd.o
 obj-$(CONFIG_KEYBOARD_PXA27x)		+= pxa27x_keypad.o
 obj-$(CONFIG_KEYBOARD_PXA930_ROTARY)	+= pxa930_rotary.o
 obj-$(CONFIG_KEYBOARD_QT2160)		+= qt2160.o
+obj-$(CONFIG_KEYBOARD_SAMSUNG)		+= samsung-keypad.o
 obj-$(CONFIG_KEYBOARD_SH_KEYSC)		+= sh_keysc.o
 obj-$(CONFIG_KEYBOARD_STOWAWAY)		+= stowaway.o
 obj-$(CONFIG_KEYBOARD_SUNKBD)		+= sunkbd.o
diff --git a/drivers/input/keyboard/samsung-keypad.c b/drivers/input/keyboard/samsung-keypad.c
new file mode 100644
index 0000000..e467195
--- /dev/null
+++ b/drivers/input/keyboard/samsung-keypad.c
@@ -0,0 +1,491 @@
+/*
+ * Samsung keypad driver
+ *
+ * Copyright (C) 2010 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim at samsung.com>
+ * Author: Donghwa Lee <dh09.lee at samsung.com>
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <plat/keypad.h>
+
+#define SAMSUNG_KEYIFCON			0x00
+#define SAMSUNG_KEYIFSTSCLR			0x04
+#define SAMSUNG_KEYIFCOL			0x08
+#define SAMSUNG_KEYIFROW			0x0c
+#define SAMSUNG_KEYIFFC				0x10
+
+/* SAMSUNG_KEYIFCON */
+#define SAMSUNG_KEYIFCON_INT_F_EN		(1 << 0)
+#define SAMSUNG_KEYIFCON_INT_R_EN		(1 << 1)
+#define SAMSUNG_KEYIFCON_DF_EN			(1 << 2)
+#define SAMSUNG_KEYIFCON_FC_EN			(1 << 3)
+#define SAMSUNG_KEYIFCON_WAKEUPEN		(1 << 4)
+
+/* SAMSUNG_KEYIFSTSCLR */
+#define SAMSUNG_KEYIFSTSCLR_P_INT_MASK		(0xff << 0)
+#define SAMSUNG_KEYIFSTSCLR_R_INT_MASK		(0xff << 8)
+#define SAMSUNG_KEYIFSTSCLR_R_INT_OFFSET	8
+#define S5PV210_KEYIFSTSCLR_P_INT_MASK		(0x3fff << 0)
+#define S5PV210_KEYIFSTSCLR_R_INT_MASK		(0x3fff << 16)
+#define S5PV210_KEYIFSTSCLR_R_INT_OFFSET	16
+
+/* SAMSUNG_KEYIFCOL */
+#define SAMSUNG_KEYIFCOL_MASK			(0xff << 0)
+#define S5PV210_KEYIFCOLEN_MASK			(0xff << 8)
+
+/* SAMSUNG_KEYIFROW */
+#define SAMSUNG_KEYIFROW_MASK			(0xff << 0)
+#define S5PV210_KEYIFROW_MASK			(0x3fff << 0)
+
+/* SAMSUNG_KEYIFFC */
+#define SAMSUNG_KEYIFFC_MASK			(0x3ff << 0)
+
+enum samsung_keypad_type {
+	KEYPAD_TYPE_SAMSUNG,
+	KEYPAD_TYPE_S5PV210,
+};
+
+struct samsung_keypad {
+	struct input_dev *input_dev;
+	struct clk *clk;
+	void __iomem *base;
+	wait_queue_head_t wait;
+	bool stopped;
+	int irq;
+	unsigned int row_shift;
+	unsigned int rows;
+	unsigned int cols;
+	unsigned int row_state[SAMSUNG_MAX_COLS];
+	unsigned short keycodes[];
+};
+
+static int samsung_keypad_is_s5pv210(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	enum samsung_keypad_type type =
+		platform_get_device_id(pdev)->driver_data;
+
+	return type == KEYPAD_TYPE_S5PV210;
+}
+
+static void samsung_keypad_scan(struct samsung_keypad *keypad,
+				unsigned int *row_state)
+{
+	struct device *dev = keypad->input_dev->dev.parent;
+	unsigned int col;
+	unsigned int val;
+
+	for (col = 0; col < keypad->cols; col++) {
+		if (samsung_keypad_is_s5pv210(dev)) {
+			val = S5PV210_KEYIFCOLEN_MASK;
+			val &= ~(1 << col) << 8;
+		} else {
+			val = SAMSUNG_KEYIFCOL_MASK;
+			val &= ~(1 << col);
+		}
+
+		writel(val, keypad->base + SAMSUNG_KEYIFCOL);
+		mdelay(1);
+
+		val = readl(keypad->base + SAMSUNG_KEYIFROW);
+		row_state[col] = ~val & ((1 << keypad->rows) - 1);
+	}
+
+	/* KEYIFCOL reg clear */
+	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+}
+
+static bool samsung_keypad_report(struct samsung_keypad *keypad,
+				  unsigned int *row_state)
+{
+	struct input_dev *input_dev = keypad->input_dev;
+	unsigned int changed;
+	unsigned int pressed;
+	unsigned int key_down = 0;
+	unsigned int val;
+	unsigned int col, row;
+
+	for (col = 0; col < keypad->cols; col++) {
+		changed = row_state[col] ^ keypad->row_state[col];
+		key_down |= row_state[col];
+		if (!changed)
+			continue;
+
+		for (row = 0; row < keypad->rows; row++) {
+			if (!(changed & (1 << row)))
+				continue;
+
+			pressed = row_state[col] & (1 << row);
+
+			dev_dbg(&keypad->input_dev->dev,
+				"key %s, row: %d, col: %d\n",
+				pressed ? "pressed" : "released", row, col);
+
+			val = MATRIX_SCAN_CODE(row, col, keypad->row_shift);
+
+			input_event(input_dev, EV_MSC, MSC_SCAN, val);
+			input_report_key(input_dev,
+					keypad->keycodes[val], pressed);
+		}
+		input_sync(keypad->input_dev);
+	}
+
+	memcpy(keypad->row_state, row_state,
+			sizeof(row_state) * SAMSUNG_MAX_COLS);
+
+	return key_down;
+}
+
+static irqreturn_t samsung_keypad_irq(int irq, void *dev_id)
+{
+	struct samsung_keypad *keypad = dev_id;
+	unsigned int row_state[SAMSUNG_MAX_COLS];
+	unsigned int val;
+	bool key_down;
+
+	do {
+		val = readl(keypad->base + SAMSUNG_KEYIFSTSCLR);
+		/* Clear interrupt. */
+		writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR);
+
+		samsung_keypad_scan(keypad, row_state);
+
+		key_down = samsung_keypad_report(keypad, row_state);
+		if (key_down)
+			wait_event_timeout(keypad->wait, keypad->stopped,
+					   msecs_to_jiffies(50));
+
+	} while (key_down && !keypad->stopped);
+
+	return IRQ_HANDLED;
+}
+
+static void samsung_keypad_start(struct samsung_keypad *keypad)
+{
+	unsigned int val;
+
+	/* Tell IRQ thread that it may poll the device. */
+	keypad->stopped = false;
+
+	clk_enable(keypad->clk);
+
+	/* Enable interrupt bits. */
+	val = readl(keypad->base + SAMSUNG_KEYIFCON);
+	val |= SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN;
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	/* KEYIFCOL reg clear. */
+	writel(0, keypad->base + SAMSUNG_KEYIFCOL);
+}
+
+static void samsung_keypad_stop(struct samsung_keypad *keypad)
+{
+	unsigned int val;
+
+	/* Signal IRQ thread to stop polling and disable the handler. */
+	keypad->stopped = true;
+	wake_up(&keypad->wait);
+	disable_irq(keypad->irq);
+
+	/* Clear interrupt. */
+	writel(~0x0, keypad->base + SAMSUNG_KEYIFSTSCLR);
+
+	/* Disable interrupt bits. */
+	val = readl(keypad->base + SAMSUNG_KEYIFCON);
+	val &= ~(SAMSUNG_KEYIFCON_INT_F_EN | SAMSUNG_KEYIFCON_INT_R_EN);
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	clk_disable(keypad->clk);
+
+	/*
+	 * Now that chip should not generate interrupts we can safely
+	 * re-enable the handler.
+	 */
+	enable_irq(keypad->irq);
+}
+
+static int samsung_keypad_open(struct input_dev *input_dev)
+{
+	struct samsung_keypad *keypad = input_get_drvdata(input_dev);
+
+	samsung_keypad_start(keypad);
+
+	return 0;
+}
+
+static void samsung_keypad_close(struct input_dev *input_dev)
+{
+	struct samsung_keypad *keypad = input_get_drvdata(input_dev);
+
+	samsung_keypad_stop(keypad);
+}
+
+static int __devinit samsung_keypad_probe(struct platform_device *pdev)
+{
+	const struct samsung_keypad_platdata *pdata;
+	const struct matrix_keymap_data *keymap_data;
+	struct samsung_keypad *keypad;
+	struct resource *res;
+	struct input_dev *input_dev;
+	unsigned int row_shift;
+	unsigned int keymap_size;
+	int error;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "no platform data defined\n");
+		return -EINVAL;
+	}
+
+	keymap_data = pdata->keymap_data;
+	if (!keymap_data) {
+		dev_err(&pdev->dev, "no keymap data defined\n");
+		return -EINVAL;
+	}
+
+	if (!pdata->rows || pdata->rows > SAMSUNG_MAX_ROWS)
+		return -EINVAL;
+
+	if (!pdata->cols || pdata->cols > SAMSUNG_MAX_COLS)
+		return -EINVAL;
+
+	/* initialize the gpio */
+	if (pdata->cfg_gpio)
+		pdata->cfg_gpio(pdata->rows, pdata->cols);
+
+	row_shift = get_count_order(pdata->cols);
+	keymap_size = (pdata->rows << row_shift) * sizeof(keypad->keycodes[0]);
+
+	keypad = kzalloc(sizeof(*keypad) + keymap_size, GFP_KERNEL);
+	input_dev = input_allocate_device();
+	if (!keypad || !input_dev) {
+		error = -ENOMEM;
+		goto err_free_mem;
+	}
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		error = -ENODEV;
+		goto err_free_mem;
+	}
+
+	keypad->base = ioremap(res->start, resource_size(res));
+	if (!keypad->base) {
+		error = -EBUSY;
+		goto err_free_mem;
+	}
+
+	keypad->clk = clk_get(&pdev->dev, "keypad");
+	if (IS_ERR(keypad->clk)) {
+		dev_err(&pdev->dev, "failed to get keypad clk\n");
+		error = PTR_ERR(keypad->clk);
+		goto err_unmap_base;
+	}
+
+	keypad->input_dev = input_dev;
+	keypad->row_shift = row_shift;
+	keypad->rows = pdata->rows;
+	keypad->cols = pdata->cols;
+	init_waitqueue_head(&keypad->wait);
+
+	input_dev->name = pdev->name;
+	input_dev->id.bustype = BUS_HOST;
+	input_dev->dev.parent = &pdev->dev;
+	input_set_drvdata(input_dev, keypad);
+
+	input_dev->open = samsung_keypad_open;
+	input_dev->close = samsung_keypad_close;
+
+	input_dev->evbit[0] = BIT_MASK(EV_KEY);
+	if (!pdata->no_autorepeat)
+		input_dev->evbit[0] |= BIT_MASK(EV_REP);
+
+	input_set_capability(input_dev, EV_MSC, MSC_SCAN);
+
+	input_dev->keycode = keypad->keycodes;
+	input_dev->keycodesize = sizeof(keypad->keycodes[0]);
+	input_dev->keycodemax = pdata->rows << row_shift;
+
+	matrix_keypad_build_keymap(keymap_data, row_shift,
+			input_dev->keycode, input_dev->keybit);
+
+	keypad->irq = platform_get_irq(pdev, 0);
+	if (keypad->irq < 0) {
+		error = keypad->irq;
+		goto err_put_clk;
+	}
+
+	error = request_threaded_irq(keypad->irq, NULL, samsung_keypad_irq,
+			IRQF_ONESHOT, dev_name(&pdev->dev), keypad);
+	if (error) {
+		dev_err(&pdev->dev, "failed to register keypad interrupt\n");
+		goto err_put_clk;
+	}
+
+	error = input_register_device(keypad->input_dev);
+	if (error)
+		goto err_free_irq;
+
+	device_init_wakeup(&pdev->dev, pdata->wakeup);
+	platform_set_drvdata(pdev, keypad);
+	return 0;
+
+err_free_irq:
+	free_irq(keypad->irq, keypad);
+err_put_clk:
+	clk_put(keypad->clk);
+err_unmap_base:
+	iounmap(keypad->base);
+err_free_mem:
+	input_free_device(input_dev);
+	kfree(keypad);
+
+	return error;
+}
+
+static int __devexit samsung_keypad_remove(struct platform_device *pdev)
+{
+	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+
+	device_init_wakeup(&pdev->dev, 0);
+	platform_set_drvdata(pdev, NULL);
+
+	input_unregister_device(keypad->input_dev);
+
+	/*
+	 * It is safe to free IRQ after unregistering device because
+	 * samsung_keypad_close will shut off interrupts.
+	 */
+	free_irq(keypad->irq, keypad);
+
+	clk_put(keypad->clk);
+
+	iounmap(keypad->base);
+	kfree(keypad);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static void samsung_keypad_toggle_wakeup(struct samsung_keypad *keypad,
+					 bool enable)
+{
+	struct device *dev = keypad->input_dev->dev.parent;
+	unsigned int val;
+
+	clk_enable(keypad->clk);
+
+	val = readl(keypad->base + SAMSUNG_KEYIFCON);
+	if (enable) {
+		val |= SAMSUNG_KEYIFCON_WAKEUPEN;
+		if (device_may_wakeup(dev))
+			enable_irq_wake(keypad->irq);
+	} else {
+		val &= ~SAMSUNG_KEYIFCON_WAKEUPEN;
+		if (device_may_wakeup(dev))
+			disable_irq_wake(keypad->irq);
+	}
+	writel(val, keypad->base + SAMSUNG_KEYIFCON);
+
+	clk_disable(keypad->clk);
+}
+
+static int samsung_keypad_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+	struct input_dev *input_dev = keypad->input_dev;
+
+	mutex_lock(&input_dev->mutex);
+
+	if (input_dev->users)
+		samsung_keypad_stop(keypad);
+
+	samsung_keypad_toggle_wakeup(keypad, true);
+
+	mutex_unlock(&input_dev->mutex);
+
+	return 0;
+}
+
+static int samsung_keypad_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct samsung_keypad *keypad = platform_get_drvdata(pdev);
+	struct input_dev *input_dev = keypad->input_dev;
+
+	mutex_lock(&input_dev->mutex);
+
+	samsung_keypad_toggle_wakeup(keypad, false);
+
+	if (input_dev->users)
+		samsung_keypad_start(keypad);
+
+	mutex_unlock(&input_dev->mutex);
+
+	return 0;
+}
+
+static const struct dev_pm_ops samsung_keypad_pm_ops = {
+	.suspend	= samsung_keypad_suspend,
+	.resume		= samsung_keypad_resume,
+};
+#endif
+
+static struct platform_device_id samsung_keypad_driver_ids[] = {
+	{
+		.name		= "samsung-keypad",
+		.driver_data	= KEYPAD_TYPE_SAMSUNG,
+	}, {
+		.name		= "s5pv210-keypad",
+		.driver_data	= KEYPAD_TYPE_S5PV210,
+	},
+	{ },
+};
+MODULE_DEVICE_TABLE(platform, samsung_keypad_driver_ids);
+
+static struct platform_driver samsung_keypad_driver = {
+	.probe		= samsung_keypad_probe,
+	.remove		= __devexit_p(samsung_keypad_remove),
+	.driver		= {
+		.name	= "samsung-keypad",
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &samsung_keypad_pm_ops,
+#endif
+	},
+	.id_table	= samsung_keypad_driver_ids,
+};
+
+static int __init samsung_keypad_init(void)
+{
+	return platform_driver_register(&samsung_keypad_driver);
+}
+module_init(samsung_keypad_init);
+
+static void __exit samsung_keypad_exit(void)
+{
+	platform_driver_unregister(&samsung_keypad_driver);
+}
+module_exit(samsung_keypad_exit);
+
+MODULE_DESCRIPTION("Samsung keypad driver");
+MODULE_AUTHOR("Joonyoung Shim <jy0922.shim at samsung.com>");
+MODULE_AUTHOR("Donghwa Lee <dh09.lee at samsung.com>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:samsung-keypad");
-- 
1.7.0.4



From marek.vasut at gmail.com  Mon Jun 28 08:04:56 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 28 Jun 2010 14:04:56 +0200
Subject: [PATCH 2/3] pxa2xx/cpufreq: Simplify DRI recomputation routine
In-Reply-To: <AANLkTilIQOmzV5JNk63dQvCViFjYOASLuZ39AZKykf6Z@mail.gmail.com>
References: <1277387833-5419-1-git-send-email-marek.vasut@gmail.com>
	<1277387833-5419-2-git-send-email-marek.vasut@gmail.com>
	<AANLkTilIQOmzV5JNk63dQvCViFjYOASLuZ39AZKykf6Z@mail.gmail.com>
Message-ID: <201006281404.56236.marek.vasut@gmail.com>

Dne Po 28. ?ervna 2010 06:38:16 Eric Miao napsal(a):
> On Thu, Jun 24, 2010 at 9:57 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > This patch:
> > 1) Simpifies the DRI recomputation routine by pulling out the common code
> > 2) Fixes a bug in PXA27x DRI recomputation caused by incorrect
> > parenthesis
> > 
> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> 
> Good catch, I've modified it a bit so it's more compact and reable below
> and I'll apply this to the 'fix' branch.

Ewww ... I'm kind-of missing the readability now ;-)

But I guess if you look into it for a long enough time, it's ok.

Acked-by: Marek Vasut <marek.vasut at gmail.com>

> 
> diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> index 9e4d981..268a9bc 100644
> --- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> +++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> @@ -256,13 +256,9 @@ static void init_sdram_rows(void)
> 
>  static u32 mdrefr_dri(unsigned int freq)
>  {
> -       u32 dri = 0;
> +       u32 interval = freq * SDRAM_TREF / sdram_rows;
> 
> -       if (cpu_is_pxa25x())
> -               dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
> -       if (cpu_is_pxa27x())
> -               dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
> -       return dri;
> +       return (interval - (cpu_is_pxa27x() ? 31 : 0)) / 32;
>  }
> 
>  /* find a valid frequency point */
> 
> > ---
> >  arch/arm/mach-pxa/cpufreq-pxa2xx.c |    9 +++++----
> >  1 files changed, 5 insertions(+), 4 deletions(-)
> > 
> > diff --git a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> > b/arch/arm/mach-pxa/cpufreq-pxa2xx.c index 9e4d981..bb5f21e 100644
> > --- a/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> > +++ b/arch/arm/mach-pxa/cpufreq-pxa2xx.c
> > @@ -256,12 +256,13 @@ static void init_sdram_rows(void)
> > 
> >  static u32 mdrefr_dri(unsigned int freq)
> >  {
> > -       u32 dri = 0;
> > +       u32 dri = freq * SDRAM_TREF / sdram_rows;
> > 
> > -       if (cpu_is_pxa25x())
> > -               dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
> >        if (cpu_is_pxa27x())
> > -               dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
> > +               dri -= 31;
> > +
> > +       dri /= 32;
> > +
> >        return dri;
> >  }
> > 
> > --
> > 1.7.1


From marek.vasut at gmail.com  Mon Jun 28 08:07:50 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 28 Jun 2010 14:07:50 +0200
Subject: [PATCH 4/4] pxa/spitz: Rework spitz
In-Reply-To: <AANLkTilwG3Blw8s8g2pTi4V5UEys25hEWL30bfav-P6b@mail.gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>
	<1277388132-5549-4-git-send-email-marek.vasut@gmail.com>
	<AANLkTilwG3Blw8s8g2pTi4V5UEys25hEWL30bfav-P6b@mail.gmail.com>
Message-ID: <201006281407.50202.marek.vasut@gmail.com>

Dne Po 28. ?ervna 2010 05:43:12 Eric Miao napsal(a):
> On Thu, Jun 24, 2010 at 10:02 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > This huge patch mostly shuffles code. The spitz.c file contained terrible
> > mess and needed a cleanup, here it is:
> > 
> > 1) Made every part modular, components are not built in if not selected.
> > 2) Removed loads of preprocessor goo, mostly "#ifdef MACH_AKITA ....
> > #endif" and similar code. The kernel size will grow by a few kb now, but
> > the file is much more readable.
> > 3) Reworked SD/CF power setting function and made it reentrant.
> > 4) Add ISL6271A regulator support
> > 5) Correctly register WM8750
> > 
> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> 
> I'd prefer to see separate small patches for this?

This is nearly a replacement for the whole file ... maybe we could merge 
spitz2.c or something ... or do it this way. I understand your point about 
spliting it into smaller chunks, but I don't see a reason in this case.
> 
> > ---
> >  arch/arm/mach-pxa/include/mach/spitz.h |    2 -
> >  arch/arm/mach-pxa/spitz.c              |  813
> > ++++++++++++++++++-------------- 2 files changed, 470 insertions(+), 345
> > deletions(-)
> > 
> > diff --git a/arch/arm/mach-pxa/include/mach/spitz.h
> > b/arch/arm/mach-pxa/include/mach/spitz.h index fa1998c..685749a 100644
> > --- a/arch/arm/mach-pxa/include/mach/spitz.h
> > +++ b/arch/arm/mach-pxa/include/mach/spitz.h
> > @@ -185,7 +185,5 @@
> >  /*
> >  * Shared data structures
> >  */
> > -extern struct platform_device spitzscoop_device;
> > -extern struct platform_device spitzscoop2_device;
> >  extern struct platform_device spitzssp_device;
> >  extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
> > diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
> > index c1048a3..fa31980 100644
> > --- a/arch/arm/mach-pxa/spitz.c
> > +++ b/arch/arm/mach-pxa/spitz.c
> > @@ -18,14 +18,15 @@
> >  #include <linux/gpio_keys.h>
> >  #include <linux/gpio.h>
> >  #include <linux/leds.h>
> > -#include <linux/mtd/physmap.h>
> >  #include <linux/i2c.h>
> >  #include <linux/i2c/pca953x.h>
> >  #include <linux/spi/spi.h>
> >  #include <linux/spi/ads7846.h>
> >  #include <linux/spi/corgi_lcd.h>
> > +#include <linux/mtd/physmap.h>
> >  #include <linux/mtd/sharpsl.h>
> >  #include <linux/input/matrix_keypad.h>
> > +#include <linux/regulator/machine.h>
> > 
> >  #include <asm/setup.h>
> >  #include <asm/mach-types.h>
> > @@ -33,11 +34,9 @@
> >  #include <asm/mach/sharpsl_param.h>
> >  #include <asm/hardware/scoop.h>
> > 
> > -
> >  #include <mach/pxa27x.h>
> >  #include <mach/pxa27x-udc.h>
> >  #include <mach/reset.h>
> > -#include <plat/i2c.h>
> >  #include <mach/irda.h>
> >  #include <mach/mmc.h>
> >  #include <mach/ohci.h>
> > @@ -45,11 +44,16 @@
> >  #include <mach/pxa2xx_spi.h>
> >  #include <mach/spitz.h>
> > 
> > +#include <plat/i2c.h>
> > +
> >  #include "generic.h"
> >  #include "devices.h"
> >  #include "sharpsl.h"
> > 
> > -static unsigned long spitz_pin_config[] __initdata = {
> > +/***********************************************************************
> > ******* + * Pin configuration
> > +
> > ************************************************************************
> > ******/ +static unsigned long sharpslc_pin_config[] __initdata = {
> >        /* Chip Selects */
> >        GPIO78_nCS_2,   /* SCOOP #2 */
> >        GPIO79_nCS_3,   /* NAND */
> > @@ -124,10 +128,13 @@ static unsigned long spitz_pin_config[] __initdata
> > = { GPIO1_GPIO | WAKEUP_ON_EDGE_FALL,       /* SPITZ_GPIO_RESET */ };
> > 
> > -/*
> > - * Spitz SCOOP Device #1
> > - */
> > -static struct resource spitz_scoop_resources[] = {
> > +
> > +/***********************************************************************
> > ******* + * Scoop GPIO expander
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_SHARP_SCOOP) ||
> > defined(CONFIG_SHARP_SCOOP_MODULE) +/* SCOOP Device #1 */
> > +static struct resource sharpslc_scoop_1_resources[] = {
> >        [0] = {
> >                .start          = 0x10800000,
> >                .end            = 0x10800fff,
> > @@ -135,7 +142,7 @@ static struct resource spitz_scoop_resources[] = {
> >        },
> >  };
> > 
> > -static struct scoop_config spitz_scoop_setup = {
> > +static struct scoop_config sharpslc_scoop_1_setup = {
> >        .io_dir         = SPITZ_SCP_IO_DIR,
> >        .io_out         = SPITZ_SCP_IO_OUT,
> >        .suspend_clr    = SPITZ_SCP_SUS_CLR,
> > @@ -143,20 +150,18 @@ static struct scoop_config spitz_scoop_setup = {
> >        .gpio_base      = SPITZ_SCP_GPIO_BASE,
> >  };
> > 
> > -struct platform_device spitzscoop_device = {
> > +struct platform_device sharpslc_scoop_1_device = {
> >        .name           = "sharp-scoop",
> >        .id             = 0,
> >        .dev            = {
> > -               .platform_data  = &spitz_scoop_setup,
> > +               .platform_data  = &sharpslc_scoop_1_setup,
> >        },
> > -       .num_resources  = ARRAY_SIZE(spitz_scoop_resources),
> > -       .resource       = spitz_scoop_resources,
> > +       .num_resources  = ARRAY_SIZE(sharpslc_scoop_1_resources),
> > +       .resource       = sharpslc_scoop_1_resources,
> >  };
> > 
> > -/*
> > - * Spitz SCOOP Device #2
> > - */
> > -static struct resource spitz_scoop2_resources[] = {
> > +/* SCOOP Device #2 */
> > +static struct resource sharpslc_scoop_2_resources[] = {
> >        [0] = {
> >                .start          = 0x08800040,
> >                .end            = 0x08800fff,
> > @@ -164,7 +169,7 @@ static struct resource spitz_scoop2_resources[] = {
> >        },
> >  };
> > 
> > -static struct scoop_config spitz_scoop2_setup = {
> > +static struct scoop_config sharpslc_scoop_2_setup = {
> >        .io_dir         = SPITZ_SCP2_IO_DIR,
> >        .io_out         = SPITZ_SCP2_IO_OUT,
> >        .suspend_clr    = SPITZ_SCP2_SUS_CLR,
> > @@ -172,82 +177,110 @@ static struct scoop_config spitz_scoop2_setup = {
> >        .gpio_base      = SPITZ_SCP2_GPIO_BASE,
> >  };
> > 
> > -struct platform_device spitzscoop2_device = {
> > +struct platform_device sharpslc_scoop_2_device = {
> >        .name           = "sharp-scoop",
> >        .id             = 1,
> >        .dev            = {
> > -               .platform_data  = &spitz_scoop2_setup,
> > +               .platform_data  = &sharpslc_scoop_2_setup,
> >        },
> > -       .num_resources  = ARRAY_SIZE(spitz_scoop2_resources),
> > -       .resource       = spitz_scoop2_resources,
> > +       .num_resources  = ARRAY_SIZE(sharpslc_scoop_2_resources),
> > +       .resource       = sharpslc_scoop_2_resources,
> >  };
> > 
> > -#define SPITZ_PWR_SD 0x01
> > -#define SPITZ_PWR_CF 0x02
> > +static void __init sharpslc_scoop_init(void)
> > +{
> > +       platform_device_register(&sharpslc_scoop_1_device);
> > +
> > +       /* Akita doesn't have the second SCOOP chip */
> > +       if (!machine_is_akita())
> > +               platform_device_register(&sharpslc_scoop_2_device);
> > +}
> > 
> >  /* Power control is shared with between one of the CF slots and SD */
> > -static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr)
> > +static void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr)
> >  {
> > -       unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev,
> > SCOOP_CPR); +       unsigned short cpr;
> > +       unsigned long flags;
> > 
> > -       if (new_cpr & 0x0007) {
> > +       if (new_cpr & 0x7) {
> >                gpio_set_value(SPITZ_GPIO_CF_POWER, 1);
> > -               if (!(cpr & 0x0002) && !(cpr & 0x0004))
> > -                       mdelay(5);
> > -               if (device == SPITZ_PWR_CF)
> > -                       cpr |= 0x0002;
> > -               if (device == SPITZ_PWR_SD)
> > -                       cpr |= 0x0004;
> > -               write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr |
> > new_cpr); -       } else {
> > -               if (device == SPITZ_PWR_CF)
> > -                       cpr &= ~0x0002;
> > -               if (device == SPITZ_PWR_SD)
> > -                       cpr &= ~0x0004;
> > -               if (!(cpr & 0x0002) && !(cpr & 0x0004)) {
> > -                       write_scoop_reg(&spitzscoop_device.dev,
> > SCOOP_CPR, 0x0000); -                       mdelay(1);
> > -                       gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
> > -               } else {
> > -                       write_scoop_reg(&spitzscoop_device.dev,
> > SCOOP_CPR, cpr | new_cpr); -               }
> > +               mdelay(5);
> > +       }
> > +
> > +       local_irq_save(flags);
> > +
> > +       cpr = read_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR);
> > +
> > +       if (enable & new_cpr)
> > +               cpr |= new_cpr;
> > +       else
> > +               cpr &= ~enable;
> > +
> > +       write_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR, cpr);
> > +
> > +       local_irq_restore(flags);
> > +
> > +       if (!(cpr & 0x7)) {
> > +               mdelay(1);
> > +               gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
> >        }
> >  }
> > 
> > -static void spitz_pcmcia_pwr(struct device *scoop, unsigned short cpr,
> > int nr) +#else
> > +static inline void sharpslc_scoop_init(void) {}
> > +static inline void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t
> > new_cpr) {} +#endif
> > +
> > +/***********************************************************************
> > ******* + * PCMCIA
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_PCMCIA_PXA2XX) ||
> > defined(CONFIG_PCMCIA_PXA2XX_MODULE) +static void
> > sharpslc_pcmcia_pwr(struct device *scoop, uint16_t cpr, int nr) {
> >        /* Only need to override behaviour for slot 0 */
> >        if (nr == 0)
> > -               spitz_card_pwr_ctrl(SPITZ_PWR_CF, cpr);
> > +               sharpslc_card_pwr_ctrl(
> > +                       cpr & (SCOOP_CPR_CF_3V | SCOOP_CPR_CF_XV), cpr);
> >        else
> >                write_scoop_reg(scoop, SCOOP_CPR, cpr);
> >  }
> > 
> > -static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
> > -{
> > -       .dev        = &spitzscoop_device.dev,
> > -       .irq        = SPITZ_IRQ_GPIO_CF_IRQ,
> > -       .cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
> > -       .cd_irq_str = "PCMCIA0 CD",
> > -},{
> > -       .dev        = &spitzscoop2_device.dev,
> > -       .irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
> > -       .cd_irq     = -1,
> > -},
> > +static struct scoop_pcmcia_dev sharpslc_pcmcia_scoop[] = {
> > +       {
> > +               .dev        = &sharpslc_scoop_1_device.dev,
> > +               .irq        = SPITZ_IRQ_GPIO_CF_IRQ,
> > +               .cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
> > +               .cd_irq_str = "PCMCIA0 CD",
> > +       }, {
> > +               .dev        = &sharpslc_scoop_2_device.dev,
> > +               .irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
> > +               .cd_irq     = -1,
> > +       },
> >  };
> > 
> > -static struct scoop_pcmcia_config spitz_pcmcia_config = {
> > -       .devs         = &spitz_pcmcia_scoop[0],
> > -       .num_devs     = 2,
> > -       .power_ctrl   = spitz_pcmcia_pwr,
> > +static struct scoop_pcmcia_config sharpslc_pcmcia_config = {
> > +       .devs           = &sharpslc_pcmcia_scoop[0],
> > +       .num_devs       = 2,
> > +       .power_ctrl     = sharpslc_pcmcia_pwr,
> >  };
> > 
> > -EXPORT_SYMBOL(spitzscoop_device);
> > -EXPORT_SYMBOL(spitzscoop2_device);
> > +static void __init sharpslc_pcmcia_init(void)
> > +{
> > +       /* Akita has only one PCMCIA slot used */
> > +       if (machine_is_akita())
> > +               sharpslc_pcmcia_config.num_devs = 1;
> > +
> > +       platform_scoop_config = &sharpslc_pcmcia_config;
> > +}
> > +#else
> > +static inline void sharpslc_pcmcia_init(void) {}
> > +#endif
> > +
> > +/***********************************************************************
> > ******* + * GPIO keyboard
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_KEYBOARD_MATRIX) ||
> > defined(CONFIG_KEYBOARD_MATRIX_MODULE)
> > 
> > -/*
> > - * Spitz Keyboard Device
> > - */
> >  #define SPITZ_KEY_CALENDAR     KEY_F1
> >  #define SPITZ_KEY_ADDRESS      KEY_F2
> >  #define SPITZ_KEY_FN           KEY_F3
> > @@ -263,7 +296,7 @@ EXPORT_SYMBOL(spitzscoop2_device);
> >  #define SPITZ_KEY_OK           KEY_F11
> >  #define SPITZ_KEY_MENU         KEY_F12
> > 
> > -static const uint32_t spitzkbd_keymap[] = {
> > +static const uint32_t sharpslc_keymap[] = {
> >        KEY(0, 0, KEY_LEFTCTRL),
> >        KEY(0, 1, KEY_1),
> >        KEY(0, 2, KEY_3),
> > @@ -330,37 +363,48 @@ static const uint32_t spitzkbd_keymap[] = {
> >        KEY(6, 8, KEY_RIGHT),
> >  };
> > 
> > -static const struct matrix_keymap_data spitzkbd_keymap_data = {
> > -       .keymap         = spitzkbd_keymap,
> > -       .keymap_size    = ARRAY_SIZE(spitzkbd_keymap),
> > +static const struct matrix_keymap_data sharpslc_keymap_data = {
> > +       .keymap         = sharpslc_keymap,
> > +       .keymap_size    = ARRAY_SIZE(sharpslc_keymap),
> >  };
> > 
> > -static const uint32_t spitzkbd_row_gpios[] =
> > +static const uint32_t sharpslc_row_gpios[] =
> >                { 12, 17, 91, 34, 36, 38, 39 };
> > -static const uint32_t spitzkbd_col_gpios[] =
> > +static const uint32_t sharpslc_col_gpios[] =
> >                { 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 };
> > 
> > -static struct matrix_keypad_platform_data spitzkbd_pdata = {
> > -       .keymap_data            = &spitzkbd_keymap_data,
> > -       .row_gpios              = spitzkbd_row_gpios,
> > -       .col_gpios              = spitzkbd_col_gpios,
> > -       .num_row_gpios          = ARRAY_SIZE(spitzkbd_row_gpios),
> > -       .num_col_gpios          = ARRAY_SIZE(spitzkbd_col_gpios),
> > +static struct matrix_keypad_platform_data sharpslc_mkp_pdata = {
> > +       .keymap_data            = &sharpslc_keymap_data,
> > +       .row_gpios              = sharpslc_row_gpios,
> > +       .col_gpios              = sharpslc_col_gpios,
> > +       .num_row_gpios          = ARRAY_SIZE(sharpslc_row_gpios),
> > +       .num_col_gpios          = ARRAY_SIZE(sharpslc_col_gpios),
> >        .col_scan_delay_us      = 10,
> >        .debounce_ms            = 10,
> >        .wakeup                 = 1,
> >  };
> > 
> > -static struct platform_device spitzkbd_device = {
> > +static struct platform_device sharpslc_mkp_device = {
> >        .name           = "matrix-keypad",
> >        .id             = -1,
> >        .dev            = {
> > -               .platform_data = &spitzkbd_pdata,
> > +               .platform_data  = &sharpslc_mkp_pdata,
> >        },
> >  };
> > 
> > +static void __init sharpslc_mkp_init(void)
> > +{
> > +       platform_device_register(&sharpslc_mkp_device);
> > +}
> > +#else
> > +static inline void sharpslc_mkp_init(void) {}
> > +#endif
> > 
> > -static struct gpio_keys_button spitz_gpio_keys[] = {
> > +/***********************************************************************
> > ******* + * GPIO keys
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_KEYBOARD_GPIO) ||
> > defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_button
> > sharpslc_gpio_keys[] = {
> >        {
> >                .type   = EV_PWR,
> >                .code   = KEY_SUSPEND,
> > @@ -383,27 +427,35 @@ static struct gpio_keys_button spitz_gpio_keys[] =
> > { },
> >  };
> > 
> > -static struct gpio_keys_platform_data spitz_gpio_keys_platform_data = {
> > -       .buttons        = spitz_gpio_keys,
> > -       .nbuttons       = ARRAY_SIZE(spitz_gpio_keys),
> > +static struct gpio_keys_platform_data sharpslc_gpio_keys_platform_data =
> > { +       .buttons        = sharpslc_gpio_keys,
> > +       .nbuttons       = ARRAY_SIZE(sharpslc_gpio_keys),
> >  };
> > 
> > -static struct platform_device spitz_gpio_keys_device = {
> > +static struct platform_device sharpslc_gpio_keys_device = {
> >        .name   = "gpio-keys",
> >        .id     = -1,
> >        .dev    = {
> > -               .platform_data  = &spitz_gpio_keys_platform_data,
> > +               .platform_data  = &sharpslc_gpio_keys_platform_data,
> >        },
> >  };
> > 
> > +static void __init sharpslc_keys_init(void)
> > +{
> > +       platform_device_register(&sharpslc_gpio_keys_device);
> > +}
> > +#else
> > +static inline void sharpslc_keys_init(void) {}
> > +#endif
> > 
> > -/*
> > - * Spitz LEDs
> > - */
> > -static struct gpio_led spitz_gpio_leds[] = {
> > +/***********************************************************************
> > ******* + * LEDs
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_LEDS_GPIO) ||
> > defined(CONFIG_LEDS_GPIO_MODULE) +static struct gpio_led
> > sharpslc_gpio_leds[] = {
> >        {
> >                .name                   = "spitz:amber:charge",
> > -               .default_trigger        = "sharpsl-charge",
> > +               .default_trigger        = "sharpslc-charge",
> >                .gpio                   = SPITZ_GPIO_LED_ORANGE,
> >        },
> >        {
> > @@ -413,25 +465,32 @@ static struct gpio_led spitz_gpio_leds[] = {
> >        },
> >  };
> > 
> > -static struct gpio_led_platform_data spitz_gpio_leds_info = {
> > -       .leds           = spitz_gpio_leds,
> > -       .num_leds       = ARRAY_SIZE(spitz_gpio_leds),
> > +static struct gpio_led_platform_data sharpslc_gpio_leds_info = {
> > +       .leds           = sharpslc_gpio_leds,
> > +       .num_leds       = ARRAY_SIZE(sharpslc_gpio_leds),
> >  };
> > 
> > -static struct platform_device spitzled_device = {
> > +static struct platform_device sharpslc_led_device = {
> >        .name           = "leds-gpio",
> >        .id             = -1,
> >        .dev            = {
> > -               .platform_data = &spitz_gpio_leds_info,
> > +               .platform_data  = &sharpslc_gpio_leds_info,
> >        },
> >  };
> > 
> > -#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
> > -static struct pxa2xx_spi_master spitz_spi_info = {
> > -       .num_chipselect = 3,
> > -};
> > +static void __init sharpslc_leds_init(void)
> > +{
> > +       platform_device_register(&sharpslc_led_device);
> > +}
> > +#else
> > +static inline void sharpslc_leds_init(void) {}
> > +#endif
> > 
> > -static void spitz_wait_for_hsync(void)
> > +/***********************************************************************
> > ******* + * SSP Devices
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_SPI_PXA2XX) ||
> > defined(CONFIG_SPI_PXA2XX_MODULE) +static void
> > sharpslc_ads7846_wait_for_hsync(void)
> >  {
> >        while (gpio_get_value(SPITZ_GPIO_HSYNC))
> >                cpu_relax();
> > @@ -440,21 +499,21 @@ static void spitz_wait_for_hsync(void)
> >                cpu_relax();
> >  }
> > 
> > -static struct ads7846_platform_data spitz_ads7846_info = {
> > +static struct ads7846_platform_data sharpslc_ads7846_info = {
> >        .model                  = 7846,
> >        .vref_delay_usecs       = 100,
> >        .x_plate_ohms           = 419,
> >        .y_plate_ohms           = 486,
> >        .pressure_max           = 1024,
> >        .gpio_pendown           = SPITZ_GPIO_TP_INT,
> > -       .wait_for_sync          = spitz_wait_for_hsync,
> > +       .wait_for_sync          = sharpslc_ads7846_wait_for_hsync,
> >  };
> > 
> > -static struct pxa2xx_spi_chip spitz_ads7846_chip = {
> > +static struct pxa2xx_spi_chip sharpslc_ads7846_chip = {
> >        .gpio_cs                = SPITZ_GPIO_ADS7846_CS,
> >  };
> > 
> > -static void spitz_bl_kick_battery(void)
> > +static void sharpslc_bl_kick_battery(void)
> >  {
> >        void (*kick_batt)(void);
> > 
> > @@ -465,93 +524,109 @@ static void spitz_bl_kick_battery(void)
> >        }
> >  }
> > 
> > -static struct corgi_lcd_platform_data spitz_lcdcon_info = {
> > +static struct corgi_lcd_platform_data sharpslc_lcdcon_info = {
> >        .init_mode              = CORGI_LCD_MODE_VGA,
> >        .max_intensity          = 0x2f,
> >        .default_intensity      = 0x1f,
> >        .limit_mask             = 0x0b,
> >        .gpio_backlight_cont    = SPITZ_GPIO_BACKLIGHT_CONT,
> >        .gpio_backlight_on      = SPITZ_GPIO_BACKLIGHT_ON,
> > -       .kick_battery           = spitz_bl_kick_battery,
> > +       .kick_battery           = sharpslc_bl_kick_battery,
> >  };
> > 
> > -static struct pxa2xx_spi_chip spitz_lcdcon_chip = {
> > +static struct pxa2xx_spi_chip sharpslc_lcdcon_chip = {
> >        .gpio_cs        = SPITZ_GPIO_LCDCON_CS,
> >  };
> > 
> > -static struct pxa2xx_spi_chip spitz_max1111_chip = {
> > +static struct pxa2xx_spi_chip sharpslc_max1111_chip = {
> >        .gpio_cs        = SPITZ_GPIO_MAX1111_CS,
> >  };
> > 
> > -static struct spi_board_info spitz_spi_devices[] = {
> > +static struct spi_board_info sharpslc_spi_devices[] = {
> >        {
> > -               .modalias       = "ads7846",
> > -               .max_speed_hz   = 1200000,
> > -               .bus_num        = 2,
> > -               .chip_select    = 0,
> > -               .platform_data  = &spitz_ads7846_info,
> > -               .controller_data= &spitz_ads7846_chip,
> > -               .irq            = gpio_to_irq(SPITZ_GPIO_TP_INT),
> > +               .modalias               = "ads7846",
> > +               .max_speed_hz           = 1200000,
> > +               .bus_num                = 2,
> > +               .chip_select            = 0,
> > +               .platform_data          = &sharpslc_ads7846_info,
> > +               .controller_data        = &sharpslc_ads7846_chip,
> > +               .irq                    = gpio_to_irq(SPITZ_GPIO_TP_INT),
> >        }, {
> > -               .modalias       = "corgi-lcd",
> > -               .max_speed_hz   = 50000,
> > -               .bus_num        = 2,
> > -               .chip_select    = 1,
> > -               .platform_data  = &spitz_lcdcon_info,
> > -               .controller_data= &spitz_lcdcon_chip,
> > +               .modalias               = "corgi-lcd",
> > +               .max_speed_hz           = 50000,
> > +               .bus_num                = 2,
> > +               .chip_select            = 1,
> > +               .platform_data          = &sharpslc_lcdcon_info,
> > +               .controller_data        = &sharpslc_lcdcon_chip,
> >        }, {
> > -               .modalias       = "max1111",
> > -               .max_speed_hz   = 450000,
> > -               .bus_num        = 2,
> > -               .chip_select    = 2,
> > -               .controller_data= &spitz_max1111_chip,
> > +               .modalias               = "max1111",
> > +               .max_speed_hz           = 450000,
> > +               .bus_num                = 2,
> > +               .chip_select            = 2,
> > +               .controller_data        = &sharpslc_max1111_chip,
> >        },
> >  };
> > 
> > -static void __init spitz_init_spi(void)
> > +static struct pxa2xx_spi_master sharpslc_spi_info = {
> > +       .num_chipselect = 3,
> > +};
> > +
> > +static void __init sharpslc_spi_init(void)
> >  {
> > +       struct corgi_lcd_platform_data *lcd_data = &sharpslc_lcdcon_info;
> > +
> >        if (machine_is_akita()) {
> > -               spitz_lcdcon_info.gpio_backlight_cont =
> > AKITA_GPIO_BACKLIGHT_CONT; -              
> > spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON; +        
> >       lcd_data->gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT; +      
> >         lcd_data->gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON; }
> > 
> > -       pxa2xx_set_spi_info(2, &spitz_spi_info);
> > -       spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
> > +       pxa2xx_set_spi_info(2, &sharpslc_spi_info);
> > +       spi_register_board_info(ARRAY_AND_SIZE(sharpslc_spi_devices));
> >  }
> >  #else
> > -static inline void spitz_init_spi(void) {}
> > +static inline void sharpslc_spi_init(void) {}
> >  #endif
> > 
> > +/***********************************************************************
> > ******* + * SD/MMC card controller
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
> >  /*
> > - * MMC/SD Device
> > - *
> > - * The card detect interrupt isn't debounced so we delay it by 250ms
> > - * to give the card a chance to fully insert/eject.
> > + * NOTE: The card detect interrupt isn't debounced so we delay it by
> > 250ms to + * give the card a chance to fully insert/eject.
> >  */
> > -static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
> > +static void sharpslc_mci_setpower(struct device *dev, unsigned int vdd)
> >  {
> >        struct pxamci_platform_data* p_d = dev->platform_data;
> > 
> > -       if (( 1 << vdd) & p_d->ocr_mask)
> > -               spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0004);
> > +       if ((1 << vdd) & p_d->ocr_mask)
> > +               sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
> >        else
> > -               spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0000);
> > +               sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
> >  }
> > 
> > -static struct pxamci_platform_data spitz_mci_platform_data = {
> > +static struct pxamci_platform_data sharpslc_mci_platform_data = {
> >        .detect_delay_ms        = 250,
> >        .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
> > -       .setpower               = spitz_mci_setpower,
> > +       .setpower               = sharpslc_mci_setpower,
> >        .gpio_card_detect       = SPITZ_GPIO_nSD_DETECT,
> >        .gpio_card_ro           = SPITZ_GPIO_nSD_WP,
> >        .gpio_power             = -1,
> >  };
> > 
> > +static void __init sharpslc_mmc_init(void)
> > +{
> > +       pxa_set_mci_info(&sharpslc_mci_platform_data);
> > +}
> > +#else
> > +static inline void sharpslc_mmc_init(void) {}
> > +#endif
> > 
> > -/*
> > - * USB Host (OHCI)
> > - */
> > -static int spitz_ohci_init(struct device *dev)
> > +/***********************************************************************
> > ******* + * USB Host
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_USB_OHCI_HCD) ||
> > defined(CONFIG_USB_OHCI_HCD_MODULE) +static int
> > sharpslc_ohci_init(struct device *dev)
> >  {
> >        int err;
> > 
> > @@ -559,88 +634,114 @@ static int spitz_ohci_init(struct device *dev)
> >        if (err)
> >                return err;
> > 
> > -       /* Only Port 2 is connected
> > -        * Setup USB Port 2 Output Control Register
> > -        */
> > +       /* Only Port 2 is connected, setup USB Port 2 Output Control
> > Register */ UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE |
> > UP2OCR_DMPDE;
> > 
> >        return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1);
> >  }
> > 
> > -static void spitz_ohci_exit(struct device *dev)
> > +static void sharpslc_ohci_exit(struct device *dev)
> >  {
> >        gpio_free(SPITZ_GPIO_USB_HOST);
> >  }
> > 
> > -static struct pxaohci_platform_data spitz_ohci_platform_data = {
> > +static struct pxaohci_platform_data sharpslc_ohci_platform_data = {
> >        .port_mode      = PMM_NPS_MODE,
> > -       .init           = spitz_ohci_init,
> > -       .exit           = spitz_ohci_exit,
> > +       .init           = sharpslc_ohci_init,
> > +       .exit           = sharpslc_ohci_exit,
> >        .flags          = ENABLE_PORT_ALL | NO_OC_PROTECTION,
> >        .power_budget   = 150,
> >  };
> > 
> > +static void __init sharpslc_uhc_init(void)
> > +{
> > +       pxa_set_ohci_info(&sharpslc_ohci_platform_data);
> > +}
> > +#else
> > +static inline void sharpslc_uhc_init(void) {}
> > +#endif
> > 
> > -/*
> > - * Irda
> > - */
> > -
> > -static struct pxaficp_platform_data spitz_ficp_platform_data = {
> > -/* .gpio_pwdown is set in spitz_init() and akita_init() accordingly */
> > +/***********************************************************************
> > ******* + * IrDA
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_PXA_FICP) || defined(CONFIG_PXA_FICP_MODULE)
> > +static struct pxaficp_platform_data sharpslc_ficp_platform_data = {
> > .transceiver_cap        = IR_SIRMODE | IR_OFF,
> >  };
> > 
> > +static void __init sharpslc_irda_init(void)
> > +{
> > +       if (machine_is_akita())
> > +               sharpslc_ficp_platform_data.gpio_pwdown =
> > AKITA_GPIO_IR_ON; +       else
> > +               sharpslc_ficp_platform_data.gpio_pwdown =
> > SPITZ_GPIO_IR_ON;
> > 
> > -/*
> > - * Spitz PXA Framebuffer
> > - */
> > +       pxa_set_ficp_info(&sharpslc_ficp_platform_data);
> > +}
> > +#else
> > +static inline void sharpslc_irda_init(void) {}
> > +#endif
> > 
> > -static struct pxafb_mode_info spitz_pxafb_modes[] = {
> > -{
> > -       .pixclock       = 19231,
> > -       .xres           = 480,
> > -       .yres           = 640,
> > -       .bpp            = 16,
> > -       .hsync_len      = 40,
> > -       .left_margin    = 46,
> > -       .right_margin   = 125,
> > -       .vsync_len      = 3,
> > -       .upper_margin   = 1,
> > -       .lower_margin   = 0,
> > -       .sync           = 0,
> > -},{
> > -       .pixclock       = 134617,
> > -       .xres           = 240,
> > -       .yres           = 320,
> > -       .bpp            = 16,
> > -       .hsync_len      = 20,
> > -       .left_margin    = 20,
> > -       .right_margin   = 46,
> > -       .vsync_len      = 2,
> > -       .upper_margin   = 1,
> > -       .lower_margin   = 0,
> > -       .sync           = 0,
> > -},
> > -};
> > -
> > -static struct pxafb_mach_info spitz_pxafb_info = {
> > -       .modes          = &spitz_pxafb_modes[0],
> > -       .num_modes      = 2,
> > +/***********************************************************************
> > ******* + * Framebuffer
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
> > +static struct pxafb_mode_info sharpslc_pxafb_modes[] = {
> > +       {
> > +               .pixclock       = 19231,
> > +               .xres           = 480,
> > +               .yres           = 640,
> > +               .bpp            = 16,
> > +               .hsync_len      = 40,
> > +               .left_margin    = 46,
> > +               .right_margin   = 125,
> > +               .vsync_len      = 3,
> > +               .upper_margin   = 1,
> > +               .lower_margin   = 0,
> > +               .sync           = 0,
> > +       }, {
> > +               .pixclock       = 134617,
> > +               .xres           = 240,
> > +               .yres           = 320,
> > +               .bpp            = 16,
> > +               .hsync_len      = 20,
> > +               .left_margin    = 20,
> > +               .right_margin   = 46,
> > +               .vsync_len      = 2,
> > +               .upper_margin   = 1,
> > +               .lower_margin   = 0,
> > +               .sync           = 0,
> > +       },
> > +};
> > +
> > +static struct pxafb_mach_info sharpslc_pxafb_info = {
> > +       .modes          = sharpslc_pxafb_modes,
> > +       .num_modes      = ARRAY_SIZE(sharpslc_pxafb_modes),
> >        .fixed_modes    = 1,
> >        .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
> >  };
> > 
> > -static struct mtd_partition sharpsl_nand_partitions[] = {
> > +static void __init sharpslc_lcd_init(void)
> > +{
> > +       set_pxa_fb_info(&sharpslc_pxafb_info);
> > +}
> > +#else
> > +static inline void sharpslc_lcd_init(void) {}
> > +#endif
> > +
> > +/***********************************************************************
> > ******* + * Framebuffer
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_MTD_NAND_SHARPSL) ||
> > defined(CONFIG_MTD_NAND_SHARPSL_MODULE) +static struct mtd_partition
> > sharpslc_nand_partitions[] = {
> >        {
> >                .name = "System Area",
> >                .offset = 0,
> >                .size = 7 * 1024 * 1024,
> > -       },
> > -       {
> > +       }, {
> >                .name = "Root Filesystem",
> >                .offset = 7 * 1024 * 1024,
> > -       },
> > -       {
> > +       }, {
> >                .name = "Home Filesystem",
> >                .offset = MTDPART_OFS_APPEND,
> >                .size = MTDPART_SIZ_FULL,
> > @@ -649,37 +750,72 @@ static struct mtd_partition
> > sharpsl_nand_partitions[] = {
> > 
> >  static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
> > 
> > -static struct nand_bbt_descr sharpsl_bbt = {
> > -       .options = 0,
> > -       .offs = 4,
> > -       .len = 2,
> > -       .pattern = scan_ff_pattern
> > +static struct nand_bbt_descr sharpslc_nand_bbt = {
> > +       .options        = 0,
> > +       .offs           = 4,
> > +       .len            = 2,
> > +       .pattern        = scan_ff_pattern
> > +};
> > +
> > +static struct nand_ecclayout sharpslc_akita_oobinfo = {
> > +       .oobfree        = { {0x08, 0x09} },
> > +       .eccbytes       = 24,
> > +       .eccpos         = {
> > +                       0x05, 0x01, 0x02, 0x03, 0x06, 0x07, 0x15, 0x11,
> > +                       0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
> > +                       0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37,
> > +       },
> >  };
> > 
> > -static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
> > -       .badblock_pattern       = &sharpsl_bbt,
> > -       .partitions             = sharpsl_nand_partitions,
> > -       .nr_partitions          = ARRAY_SIZE(sharpsl_nand_partitions),
> > +static struct sharpsl_nand_platform_data sharpslc_nand_pdata = {
> > +       .badblock_pattern       = &sharpslc_nand_bbt,
> > +       .partitions             = sharpslc_nand_partitions,
> > +       .nr_partitions          = ARRAY_SIZE(sharpslc_nand_partitions),
> >  };
> > 
> > -static struct resource sharpsl_nand_resources[] = {
> > +static struct resource sharpslc_nand_resources[] = {
> >        {
> > -               .start  = 0x0C000000,
> > -               .end    = 0x0C000FFF,
> > +               .start  = PXA_CS3_PHYS,
> > +               .end    = PXA_CS3_PHYS + SZ_4K - 1,
> >                .flags  = IORESOURCE_MEM,
> >        },
> >  };
> > 
> > -static struct platform_device sharpsl_nand_device = {
> > +static struct platform_device sharpslc_nand_device = {
> >        .name           = "sharpsl-nand",
> >        .id             = -1,
> > -       .resource       = sharpsl_nand_resources,
> > -       .num_resources  = ARRAY_SIZE(sharpsl_nand_resources),
> > -       .dev.platform_data      = &sharpsl_nand_platform_data,
> > +       .resource       = sharpslc_nand_resources,
> > +       .num_resources  = ARRAY_SIZE(sharpslc_nand_resources),
> > +       .dev            = {
> > +               .platform_data  = &sharpslc_nand_pdata,
> > +       }
> >  };
> > 
> > +static void __init sharpslc_nand_init(void)
> > +{
> > +       if (machine_is_spitz()) {
> > +               sharpslc_nand_partitions[1].size = 5 * 1024 * 1024;
> > +       } else if (machine_is_akita()) {
> > +               sharpslc_nand_partitions[1].size = 58 * 1024 * 1024;
> > +               sharpslc_nand_bbt.len = 1;
> > +               sharpslc_nand_pdata.ecc_layout = &sharpslc_akita_oobinfo;
> > +       } else if (machine_is_borzoi()) {
> > +               sharpslc_nand_partitions[1].size = 32 * 1024 * 1024;
> > +               sharpslc_nand_bbt.len = 1;
> > +               sharpslc_nand_pdata.ecc_layout = &sharpslc_akita_oobinfo;
> > +       }
> > +
> > +       platform_device_register(&sharpslc_nand_device);
> > +}
> > +#else
> > +static inline void sharpslc_nand_init(void) {}
> > +#endif
> > 
> > -static struct mtd_partition sharpsl_rom_parts[] = {
> > +/***********************************************************************
> > ******* + * NOR Flash
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_MTD_PHYSMAP) ||
> > defined(CONFIG_MTD_PHYSMAP_MODULE) +static struct mtd_partition
> > sharpslc_rom_parts[] = {
> >        {
> >                .name   ="Boot PROM Filesystem",
> >                .offset = 0x00140000,
> > @@ -687,161 +823,152 @@ static struct mtd_partition sharpsl_rom_parts[] =
> > { },
> >  };
> > 
> > -static struct physmap_flash_data sharpsl_rom_data = {
> > +static struct physmap_flash_data sharpslc_rom_data = {
> >        .width          = 2,
> > -       .nr_parts       = ARRAY_SIZE(sharpsl_rom_parts),
> > -       .parts          = sharpsl_rom_parts,
> > +       .nr_parts       = ARRAY_SIZE(sharpslc_rom_parts),
> > +       .parts          = sharpslc_rom_parts,
> >  };
> > 
> > -static struct resource sharpsl_rom_resources[] = {
> > +static struct resource sharpslc_rom_resources[] = {
> >        {
> > -               .start  = 0x00000000,
> > -               .end    = 0x007fffff,
> > +               .start  = PXA_CS0_PHYS,
> > +               .end    = PXA_CS0_PHYS + SZ_8M - 1,
> >                .flags  = IORESOURCE_MEM,
> >        },
> >  };
> > 
> > -static struct platform_device sharpsl_rom_device = {
> > -       .name   = "physmap-flash",
> > -       .id     = -1,
> > -       .resource = sharpsl_rom_resources,
> > -       .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
> > -       .dev.platform_data = &sharpsl_rom_data,
> > -};
> > -
> > -static struct platform_device *devices[] __initdata = {
> > -       &spitzscoop_device,
> > -       &spitzkbd_device,
> > -       &spitz_gpio_keys_device,
> > -       &spitzled_device,
> > -       &sharpsl_nand_device,
> > -       &sharpsl_rom_device,
> > +static struct platform_device sharpslc_rom_device = {
> > +       .name           = "physmap-flash",
> > +       .id             = -1,
> > +       .resource       = sharpslc_rom_resources,
> > +       .num_resources  = ARRAY_SIZE(sharpslc_rom_resources),
> > +       .dev            = {
> > +               .platform_data  = &sharpslc_rom_data,
> > +       },
> >  };
> > 
> > -static void spitz_poweroff(void)
> > +static void __init sharpslc_nor_init(void)
> >  {
> > -       arm_machine_restart('g', NULL);
> > +       platform_device_register(&sharpslc_rom_device);
> >  }
> > +#else
> > +static inline void sharpslc_nor_init(void) {}
> > +#endif
> > 
> > -static void spitz_restart(char mode, const char *cmd)
> > -{
> > -       /* Bootloader magic for a reboot */
> > -       if((MSC0 & 0xffff0000) == 0x7ff00000)
> > -               MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
> > -
> > -       spitz_poweroff();
> > -}
> > +/***********************************************************************
> > ******* + * GPIO expander
> > +
> > ************************************************************************
> > ******/ +#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
> > +static struct pca953x_platform_data akita_pca953x_pdata = {
> > +       .gpio_base              = AKITA_IOEXP_GPIO_BASE,
> > +};
> > 
> > -static void __init common_init(void)
> > -{
> > -       init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
> > -       pm_power_off = spitz_poweroff;
> > -       arm_pm_restart = spitz_restart;
> > +static struct i2c_board_info sharpslc_i2c_devs[] = {
> > +       {
> > +               .type           = "wm8750",
> > +               .addr           = 0x1b,
> > +       }, {
> > +               .type           = "max7310",
> > +               .addr           = 0x18,
> > +               .platform_data  = &akita_pca953x_pdata,
> > +       },
> > +};
> > 
> > -       if (machine_is_spitz()) {
> > -               sharpsl_nand_partitions[1].size = 5 * 1024 * 1024;
> > -       } else if (machine_is_akita()) {
> > -               sharpsl_nand_partitions[1].size = 58 * 1024 * 1024;
> > -       } else if (machine_is_borzoi()) {
> > -               sharpsl_nand_partitions[1].size = 32 * 1024 * 1024;
> > +static struct regulator_consumer_supply isl6271a_consumers[] = {
> > +       {
> > +               .supply = "vcc_core",
> >        }
> > +};
> > 
> > -       PMCR = 0x00;
> > -
> > -       /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
> > -       PCFR |= PCFR_OPDE;
> > +static struct regulator_init_data isl6271a_info[] = {
> > +       {
> > +               .constraints = {
> > +                       .name           = "vcc_core range",
> > +                       .min_uV         = 850000,
> > +                       .max_uV         = 1600000,
> > +                       .always_on      = 1,
> > +                       .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> > +               },
> > +       .consumer_supplies      = isl6271a_consumers,
> > +       .num_consumer_supplies  = ARRAY_SIZE(isl6271a_consumers),
> > +       }
> > +};
> > 
> > -       pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
> > +static struct i2c_board_info sharpslc_pi2c_devs[] = {
> > +       {
> > +               .type           = "isl6271a",
> > +               .addr           = 0x0c,
> > +               .platform_data  = &isl6271a_info,
> > +       },
> > +};
> > 
> > -       pxa_set_ffuart_info(NULL);
> > -       pxa_set_btuart_info(NULL);
> > -       pxa_set_stuart_info(NULL);
> > +static void __init sharpslc_i2c_init(void)
> > +{
> > +       int size = ARRAY_SIZE(sharpslc_i2c_devs);
> > 
> > -       spitz_init_spi();
> > +       /* Only Akita has the max7310 chip */
> > +       if (!machine_is_akita())
> > +               size--;
> > 
> > -       platform_add_devices(devices, ARRAY_SIZE(devices));
> > -       pxa_set_mci_info(&spitz_mci_platform_data);
> > -       pxa_set_ohci_info(&spitz_ohci_platform_data);
> > -       pxa_set_ficp_info(&spitz_ficp_platform_data);
> > -       set_pxa_fb_info(&spitz_pxafb_info);
> >        pxa_set_i2c_info(NULL);
> > +       pxa27x_set_i2c_power_info(NULL);
> > +       i2c_register_board_info(0, sharpslc_i2c_devs, size);
> > +       i2c_register_board_info(1, ARRAY_AND_SIZE(sharpslc_pi2c_devs));
> >  }
> > -
> > -#if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI)
> > -static struct nand_bbt_descr sharpsl_akita_bbt = {
> > -       .options = 0,
> > -       .offs = 4,
> > -       .len = 1,
> > -       .pattern = scan_ff_pattern
> > -};
> > -
> > -static struct nand_ecclayout akita_oobinfo = {
> > -       .eccbytes = 24,
> > -       .eccpos = {
> > -                  0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
> > -                  0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
> > -                  0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
> > -       .oobfree = {{0x08, 0x09}}
> > -};
> > +#else
> > +static inline void sharpslc_i2c_init(void) {}
> >  #endif
> > 
> > -#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
> > -static void __init spitz_init(void)
> > +/***********************************************************************
> > ******* + * Machine init
> > +
> > ************************************************************************
> > ******/ +static void sharpslc_poweroff(void)
> >  {
> > -       spitz_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
> > -
> > -#ifdef CONFIG_MACH_BORZOI
> > -       if (machine_is_borzoi()) {
> > -               sharpsl_nand_platform_data.badblock_pattern =
> > &sharpsl_akita_bbt; -              
> > sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo; -       }
> > -#endif
> > -
> > -       platform_scoop_config = &spitz_pcmcia_config;
> > -
> > -       common_init();
> > -
> > -       platform_device_register(&spitzscoop2_device);
> > +       arm_machine_restart('g', NULL);
> >  }
> > -#endif
> > 
> > -#ifdef CONFIG_MACH_AKITA
> > -/*
> > - * Akita IO Expander
> > - */
> > -static struct pca953x_platform_data akita_ioexp = {
> > -       .gpio_base              = AKITA_IOEXP_GPIO_BASE,
> > -};
> > +static void sharpslc_restart(char mode, const char *cmd)
> > +{
> > +       /* Bootloader magic for a reboot */
> > +       if ((MSC0 & 0xffff0000) == 0x7ff00000)
> > +               MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
> > 
> > -static struct i2c_board_info akita_i2c_board_info[] = {
> > -       {
> > -               .type           = "max7310",
> > -               .addr           = 0x18,
> > -               .platform_data  = &akita_ioexp,
> > -       }, {
> > -               .type           = "wm8750",
> > -               .addr           = 0x1b,
> > -       },
> > -};
> > +       sharpslc_poweroff();
> > +}
> > 
> > -static void __init akita_init(void)
> > +static void __init sharpslc_init(void)
> >  {
> > -       spitz_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
> > +       init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
> > +       pm_power_off = sharpslc_poweroff;
> > +       arm_pm_restart = sharpslc_restart;
> > +
> > +       PMCR = 0x00;
> > 
> > -       sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
> > -       sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
> > +       /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
> > +       PCFR |= PCFR_OPDE;
> > 
> > -       /* We just pretend the second element of the array doesn't exist
> > */ -       spitz_pcmcia_config.num_devs = 1;
> > -       platform_scoop_config = &spitz_pcmcia_config;
> > +       pxa2xx_mfp_config(ARRAY_AND_SIZE(sharpslc_pin_config));
> > 
> > -       i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_board_info));
> > +       pxa_set_ffuart_info(NULL);
> > +       pxa_set_btuart_info(NULL);
> > +       pxa_set_stuart_info(NULL);
> > 
> > -       common_init();
> > +       sharpslc_spi_init();
> > +       sharpslc_scoop_init();
> > +       sharpslc_mkp_init();
> > +       sharpslc_keys_init();
> > +       sharpslc_leds_init();
> > +       sharpslc_mmc_init();
> > +       sharpslc_pcmcia_init();
> > +       sharpslc_irda_init();
> > +       sharpslc_uhc_init();
> > +       sharpslc_lcd_init();
> > +       sharpslc_nor_init();
> > +       sharpslc_nand_init();
> > +       sharpslc_i2c_init();
> >  }
> > -#endif
> > 
> > -static void __init fixup_spitz(struct machine_desc *desc,
> > +static void __init sharpslc_fixup(struct machine_desc *desc,
> >                struct tag *tags, char **cmdline, struct meminfo *mi)
> >  {
> >        sharpsl_save_param();
> > @@ -855,10 +982,10 @@ static void __init fixup_spitz(struct machine_desc
> > *desc, MACHINE_START(SPITZ, "SHARP Spitz")
> >        .phys_io        = 0x40000000,
> >        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
> > -       .fixup          = fixup_spitz,
> > +       .fixup          = sharpslc_fixup,
> >        .map_io         = pxa_map_io,
> >        .init_irq       = pxa27x_init_irq,
> > -       .init_machine   = spitz_init,
> > +       .init_machine   = sharpslc_init,
> >        .timer          = &pxa_timer,
> >  MACHINE_END
> >  #endif
> > @@ -867,10 +994,10 @@ MACHINE_END
> >  MACHINE_START(BORZOI, "SHARP Borzoi")
> >        .phys_io        = 0x40000000,
> >        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
> > -       .fixup          = fixup_spitz,
> > +       .fixup          = sharpslc_fixup,
> >        .map_io         = pxa_map_io,
> >        .init_irq       = pxa27x_init_irq,
> > -       .init_machine   = spitz_init,
> > +       .init_machine   = sharpslc_init,
> >        .timer          = &pxa_timer,
> >  MACHINE_END
> >  #endif
> > @@ -879,10 +1006,10 @@ MACHINE_END
> >  MACHINE_START(AKITA, "SHARP Akita")
> >        .phys_io        = 0x40000000,
> >        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
> > -       .fixup          = fixup_spitz,
> > +       .fixup          = sharpslc_fixup,
> >        .map_io         = pxa_map_io,
> >        .init_irq       = pxa27x_init_irq,
> > -       .init_machine   = akita_init,
> > +       .init_machine   = sharpslc_init,
> >        .timer          = &pxa_timer,
> >  MACHINE_END
> >  #endif
> > --
> > 1.7.1


From eric.y.miao at gmail.com  Mon Jun 28 08:19:46 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Mon, 28 Jun 2010 20:19:46 +0800
Subject: [PATCH 4/4] pxa/spitz: Rework spitz
In-Reply-To: <201006281407.50202.marek.vasut@gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com> 
	<1277388132-5549-4-git-send-email-marek.vasut@gmail.com>
	<AANLkTilwG3Blw8s8g2pTi4V5UEys25hEWL30bfav-P6b@mail.gmail.com> 
	<201006281407.50202.marek.vasut@gmail.com>
Message-ID: <AANLkTikdxoqofUUpxB1c9wSlsU-zxc-uSNMmnQX_kE8m@mail.gmail.com>

On Mon, Jun 28, 2010 at 8:07 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dne Po 28. ?ervna 2010 05:43:12 Eric Miao napsal(a):
>> On Thu, Jun 24, 2010 at 10:02 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
>> > This huge patch mostly shuffles code. The spitz.c file contained terrible
>> > mess and needed a cleanup, here it is:
>> >
>> > 1) Made every part modular, components are not built in if not selected.
>> > 2) Removed loads of preprocessor goo, mostly "#ifdef MACH_AKITA ....
>> > #endif" and similar code. The kernel size will grow by a few kb now, but
>> > the file is much more readable.
>> > 3) Reworked SD/CF power setting function and made it reentrant.
>> > 4) Add ISL6271A regulator support
>> > 5) Correctly register WM8750
>> >
>> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
>>
>> I'd prefer to see separate small patches for this?
>
> This is nearly a replacement for the whole file ... maybe we could merge
> spitz2.c or something ... or do it this way. I understand your point about
> spliting it into smaller chunks, but I don't see a reason in this case.

I guess the above 1, 2, 3, 4, 5 can be well separated into 5 patches,
I don't mind merge many patches, but I'd really like to see small and
consistent changes (make it regression test friendly BTW), ;-)

>>
>> > ---
>> > ?arch/arm/mach-pxa/include/mach/spitz.h | ? ?2 -
>> > ?arch/arm/mach-pxa/spitz.c ? ? ? ? ? ? ?| ?813
>> > ++++++++++++++++++-------------- 2 files changed, 470 insertions(+), 345
>> > deletions(-)
>> >
>> > diff --git a/arch/arm/mach-pxa/include/mach/spitz.h
>> > b/arch/arm/mach-pxa/include/mach/spitz.h index fa1998c..685749a 100644
>> > --- a/arch/arm/mach-pxa/include/mach/spitz.h
>> > +++ b/arch/arm/mach-pxa/include/mach/spitz.h
>> > @@ -185,7 +185,5 @@
>> > ?/*
>> > ?* Shared data structures
>> > ?*/
>> > -extern struct platform_device spitzscoop_device;
>> > -extern struct platform_device spitzscoop2_device;
>> > ?extern struct platform_device spitzssp_device;
>> > ?extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
>> > diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
>> > index c1048a3..fa31980 100644
>> > --- a/arch/arm/mach-pxa/spitz.c
>> > +++ b/arch/arm/mach-pxa/spitz.c
>> > @@ -18,14 +18,15 @@
>> > ?#include <linux/gpio_keys.h>
>> > ?#include <linux/gpio.h>
>> > ?#include <linux/leds.h>
>> > -#include <linux/mtd/physmap.h>
>> > ?#include <linux/i2c.h>
>> > ?#include <linux/i2c/pca953x.h>
>> > ?#include <linux/spi/spi.h>
>> > ?#include <linux/spi/ads7846.h>
>> > ?#include <linux/spi/corgi_lcd.h>
>> > +#include <linux/mtd/physmap.h>
>> > ?#include <linux/mtd/sharpsl.h>
>> > ?#include <linux/input/matrix_keypad.h>
>> > +#include <linux/regulator/machine.h>
>> >
>> > ?#include <asm/setup.h>
>> > ?#include <asm/mach-types.h>
>> > @@ -33,11 +34,9 @@
>> > ?#include <asm/mach/sharpsl_param.h>
>> > ?#include <asm/hardware/scoop.h>
>> >
>> > -
>> > ?#include <mach/pxa27x.h>
>> > ?#include <mach/pxa27x-udc.h>
>> > ?#include <mach/reset.h>
>> > -#include <plat/i2c.h>
>> > ?#include <mach/irda.h>
>> > ?#include <mach/mmc.h>
>> > ?#include <mach/ohci.h>
>> > @@ -45,11 +44,16 @@
>> > ?#include <mach/pxa2xx_spi.h>
>> > ?#include <mach/spitz.h>
>> >
>> > +#include <plat/i2c.h>
>> > +
>> > ?#include "generic.h"
>> > ?#include "devices.h"
>> > ?#include "sharpsl.h"
>> >
>> > -static unsigned long spitz_pin_config[] __initdata = {
>> > +/***********************************************************************
>> > ******* + * Pin configuration
>> > +
>> > ************************************************************************
>> > ******/ +static unsigned long sharpslc_pin_config[] __initdata = {
>> > ? ? ? ?/* Chip Selects */
>> > ? ? ? ?GPIO78_nCS_2, ? /* SCOOP #2 */
>> > ? ? ? ?GPIO79_nCS_3, ? /* NAND */
>> > @@ -124,10 +128,13 @@ static unsigned long spitz_pin_config[] __initdata
>> > = { GPIO1_GPIO | WAKEUP_ON_EDGE_FALL, ? ? ? /* SPITZ_GPIO_RESET */ };
>> >
>> > -/*
>> > - * Spitz SCOOP Device #1
>> > - */
>> > -static struct resource spitz_scoop_resources[] = {
>> > +
>> > +/***********************************************************************
>> > ******* + * Scoop GPIO expander
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_SHARP_SCOOP) ||
>> > defined(CONFIG_SHARP_SCOOP_MODULE) +/* SCOOP Device #1 */
>> > +static struct resource sharpslc_scoop_1_resources[] = {
>> > ? ? ? ?[0] = {
>> > ? ? ? ? ? ? ? ?.start ? ? ? ? ?= 0x10800000,
>> > ? ? ? ? ? ? ? ?.end ? ? ? ? ? ?= 0x10800fff,
>> > @@ -135,7 +142,7 @@ static struct resource spitz_scoop_resources[] = {
>> > ? ? ? ?},
>> > ?};
>> >
>> > -static struct scoop_config spitz_scoop_setup = {
>> > +static struct scoop_config sharpslc_scoop_1_setup = {
>> > ? ? ? ?.io_dir ? ? ? ? = SPITZ_SCP_IO_DIR,
>> > ? ? ? ?.io_out ? ? ? ? = SPITZ_SCP_IO_OUT,
>> > ? ? ? ?.suspend_clr ? ?= SPITZ_SCP_SUS_CLR,
>> > @@ -143,20 +150,18 @@ static struct scoop_config spitz_scoop_setup = {
>> > ? ? ? ?.gpio_base ? ? ?= SPITZ_SCP_GPIO_BASE,
>> > ?};
>> >
>> > -struct platform_device spitzscoop_device = {
>> > +struct platform_device sharpslc_scoop_1_device = {
>> > ? ? ? ?.name ? ? ? ? ? = "sharp-scoop",
>> > ? ? ? ?.id ? ? ? ? ? ? = 0,
>> > ? ? ? ?.dev ? ? ? ? ? ?= {
>> > - ? ? ? ? ? ? ? .platform_data ?= &spitz_scoop_setup,
>> > + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_scoop_1_setup,
>> > ? ? ? ?},
>> > - ? ? ? .num_resources ?= ARRAY_SIZE(spitz_scoop_resources),
>> > - ? ? ? .resource ? ? ? = spitz_scoop_resources,
>> > + ? ? ? .num_resources ?= ARRAY_SIZE(sharpslc_scoop_1_resources),
>> > + ? ? ? .resource ? ? ? = sharpslc_scoop_1_resources,
>> > ?};
>> >
>> > -/*
>> > - * Spitz SCOOP Device #2
>> > - */
>> > -static struct resource spitz_scoop2_resources[] = {
>> > +/* SCOOP Device #2 */
>> > +static struct resource sharpslc_scoop_2_resources[] = {
>> > ? ? ? ?[0] = {
>> > ? ? ? ? ? ? ? ?.start ? ? ? ? ?= 0x08800040,
>> > ? ? ? ? ? ? ? ?.end ? ? ? ? ? ?= 0x08800fff,
>> > @@ -164,7 +169,7 @@ static struct resource spitz_scoop2_resources[] = {
>> > ? ? ? ?},
>> > ?};
>> >
>> > -static struct scoop_config spitz_scoop2_setup = {
>> > +static struct scoop_config sharpslc_scoop_2_setup = {
>> > ? ? ? ?.io_dir ? ? ? ? = SPITZ_SCP2_IO_DIR,
>> > ? ? ? ?.io_out ? ? ? ? = SPITZ_SCP2_IO_OUT,
>> > ? ? ? ?.suspend_clr ? ?= SPITZ_SCP2_SUS_CLR,
>> > @@ -172,82 +177,110 @@ static struct scoop_config spitz_scoop2_setup = {
>> > ? ? ? ?.gpio_base ? ? ?= SPITZ_SCP2_GPIO_BASE,
>> > ?};
>> >
>> > -struct platform_device spitzscoop2_device = {
>> > +struct platform_device sharpslc_scoop_2_device = {
>> > ? ? ? ?.name ? ? ? ? ? = "sharp-scoop",
>> > ? ? ? ?.id ? ? ? ? ? ? = 1,
>> > ? ? ? ?.dev ? ? ? ? ? ?= {
>> > - ? ? ? ? ? ? ? .platform_data ?= &spitz_scoop2_setup,
>> > + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_scoop_2_setup,
>> > ? ? ? ?},
>> > - ? ? ? .num_resources ?= ARRAY_SIZE(spitz_scoop2_resources),
>> > - ? ? ? .resource ? ? ? = spitz_scoop2_resources,
>> > + ? ? ? .num_resources ?= ARRAY_SIZE(sharpslc_scoop_2_resources),
>> > + ? ? ? .resource ? ? ? = sharpslc_scoop_2_resources,
>> > ?};
>> >
>> > -#define SPITZ_PWR_SD 0x01
>> > -#define SPITZ_PWR_CF 0x02
>> > +static void __init sharpslc_scoop_init(void)
>> > +{
>> > + ? ? ? platform_device_register(&sharpslc_scoop_1_device);
>> > +
>> > + ? ? ? /* Akita doesn't have the second SCOOP chip */
>> > + ? ? ? if (!machine_is_akita())
>> > + ? ? ? ? ? ? ? platform_device_register(&sharpslc_scoop_2_device);
>> > +}
>> >
>> > ?/* Power control is shared with between one of the CF slots and SD */
>> > -static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr)
>> > +static void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr)
>> > ?{
>> > - ? ? ? unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev,
>> > SCOOP_CPR); + ? ? ? unsigned short cpr;
>> > + ? ? ? unsigned long flags;
>> >
>> > - ? ? ? if (new_cpr & 0x0007) {
>> > + ? ? ? if (new_cpr & 0x7) {
>> > ? ? ? ? ? ? ? ?gpio_set_value(SPITZ_GPIO_CF_POWER, 1);
>> > - ? ? ? ? ? ? ? if (!(cpr & 0x0002) && !(cpr & 0x0004))
>> > - ? ? ? ? ? ? ? ? ? ? ? mdelay(5);
>> > - ? ? ? ? ? ? ? if (device == SPITZ_PWR_CF)
>> > - ? ? ? ? ? ? ? ? ? ? ? cpr |= 0x0002;
>> > - ? ? ? ? ? ? ? if (device == SPITZ_PWR_SD)
>> > - ? ? ? ? ? ? ? ? ? ? ? cpr |= 0x0004;
>> > - ? ? ? ? ? ? ? write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr |
>> > new_cpr); - ? ? ? } else {
>> > - ? ? ? ? ? ? ? if (device == SPITZ_PWR_CF)
>> > - ? ? ? ? ? ? ? ? ? ? ? cpr &= ~0x0002;
>> > - ? ? ? ? ? ? ? if (device == SPITZ_PWR_SD)
>> > - ? ? ? ? ? ? ? ? ? ? ? cpr &= ~0x0004;
>> > - ? ? ? ? ? ? ? if (!(cpr & 0x0002) && !(cpr & 0x0004)) {
>> > - ? ? ? ? ? ? ? ? ? ? ? write_scoop_reg(&spitzscoop_device.dev,
>> > SCOOP_CPR, 0x0000); - ? ? ? ? ? ? ? ? ? ? ? mdelay(1);
>> > - ? ? ? ? ? ? ? ? ? ? ? gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
>> > - ? ? ? ? ? ? ? } else {
>> > - ? ? ? ? ? ? ? ? ? ? ? write_scoop_reg(&spitzscoop_device.dev,
>> > SCOOP_CPR, cpr | new_cpr); - ? ? ? ? ? ? ? }
>> > + ? ? ? ? ? ? ? mdelay(5);
>> > + ? ? ? }
>> > +
>> > + ? ? ? local_irq_save(flags);
>> > +
>> > + ? ? ? cpr = read_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR);
>> > +
>> > + ? ? ? if (enable & new_cpr)
>> > + ? ? ? ? ? ? ? cpr |= new_cpr;
>> > + ? ? ? else
>> > + ? ? ? ? ? ? ? cpr &= ~enable;
>> > +
>> > + ? ? ? write_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR, cpr);
>> > +
>> > + ? ? ? local_irq_restore(flags);
>> > +
>> > + ? ? ? if (!(cpr & 0x7)) {
>> > + ? ? ? ? ? ? ? mdelay(1);
>> > + ? ? ? ? ? ? ? gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
>> > ? ? ? ?}
>> > ?}
>> >
>> > -static void spitz_pcmcia_pwr(struct device *scoop, unsigned short cpr,
>> > int nr) +#else
>> > +static inline void sharpslc_scoop_init(void) {}
>> > +static inline void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t
>> > new_cpr) {} +#endif
>> > +
>> > +/***********************************************************************
>> > ******* + * PCMCIA
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_PCMCIA_PXA2XX) ||
>> > defined(CONFIG_PCMCIA_PXA2XX_MODULE) +static void
>> > sharpslc_pcmcia_pwr(struct device *scoop, uint16_t cpr, int nr) {
>> > ? ? ? ?/* Only need to override behaviour for slot 0 */
>> > ? ? ? ?if (nr == 0)
>> > - ? ? ? ? ? ? ? spitz_card_pwr_ctrl(SPITZ_PWR_CF, cpr);
>> > + ? ? ? ? ? ? ? sharpslc_card_pwr_ctrl(
>> > + ? ? ? ? ? ? ? ? ? ? ? cpr & (SCOOP_CPR_CF_3V | SCOOP_CPR_CF_XV), cpr);
>> > ? ? ? ?else
>> > ? ? ? ? ? ? ? ?write_scoop_reg(scoop, SCOOP_CPR, cpr);
>> > ?}
>> >
>> > -static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
>> > -{
>> > - ? ? ? .dev ? ? ? ?= &spitzscoop_device.dev,
>> > - ? ? ? .irq ? ? ? ?= SPITZ_IRQ_GPIO_CF_IRQ,
>> > - ? ? ? .cd_irq ? ? = SPITZ_IRQ_GPIO_CF_CD,
>> > - ? ? ? .cd_irq_str = "PCMCIA0 CD",
>> > -},{
>> > - ? ? ? .dev ? ? ? ?= &spitzscoop2_device.dev,
>> > - ? ? ? .irq ? ? ? ?= SPITZ_IRQ_GPIO_CF2_IRQ,
>> > - ? ? ? .cd_irq ? ? = -1,
>> > -},
>> > +static struct scoop_pcmcia_dev sharpslc_pcmcia_scoop[] = {
>> > + ? ? ? {
>> > + ? ? ? ? ? ? ? .dev ? ? ? ?= &sharpslc_scoop_1_device.dev,
>> > + ? ? ? ? ? ? ? .irq ? ? ? ?= SPITZ_IRQ_GPIO_CF_IRQ,
>> > + ? ? ? ? ? ? ? .cd_irq ? ? = SPITZ_IRQ_GPIO_CF_CD,
>> > + ? ? ? ? ? ? ? .cd_irq_str = "PCMCIA0 CD",
>> > + ? ? ? }, {
>> > + ? ? ? ? ? ? ? .dev ? ? ? ?= &sharpslc_scoop_2_device.dev,
>> > + ? ? ? ? ? ? ? .irq ? ? ? ?= SPITZ_IRQ_GPIO_CF2_IRQ,
>> > + ? ? ? ? ? ? ? .cd_irq ? ? = -1,
>> > + ? ? ? },
>> > ?};
>> >
>> > -static struct scoop_pcmcia_config spitz_pcmcia_config = {
>> > - ? ? ? .devs ? ? ? ? = &spitz_pcmcia_scoop[0],
>> > - ? ? ? .num_devs ? ? = 2,
>> > - ? ? ? .power_ctrl ? = spitz_pcmcia_pwr,
>> > +static struct scoop_pcmcia_config sharpslc_pcmcia_config = {
>> > + ? ? ? .devs ? ? ? ? ? = &sharpslc_pcmcia_scoop[0],
>> > + ? ? ? .num_devs ? ? ? = 2,
>> > + ? ? ? .power_ctrl ? ? = sharpslc_pcmcia_pwr,
>> > ?};
>> >
>> > -EXPORT_SYMBOL(spitzscoop_device);
>> > -EXPORT_SYMBOL(spitzscoop2_device);
>> > +static void __init sharpslc_pcmcia_init(void)
>> > +{
>> > + ? ? ? /* Akita has only one PCMCIA slot used */
>> > + ? ? ? if (machine_is_akita())
>> > + ? ? ? ? ? ? ? sharpslc_pcmcia_config.num_devs = 1;
>> > +
>> > + ? ? ? platform_scoop_config = &sharpslc_pcmcia_config;
>> > +}
>> > +#else
>> > +static inline void sharpslc_pcmcia_init(void) {}
>> > +#endif
>> > +
>> > +/***********************************************************************
>> > ******* + * GPIO keyboard
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_KEYBOARD_MATRIX) ||
>> > defined(CONFIG_KEYBOARD_MATRIX_MODULE)
>> >
>> > -/*
>> > - * Spitz Keyboard Device
>> > - */
>> > ?#define SPITZ_KEY_CALENDAR ? ? KEY_F1
>> > ?#define SPITZ_KEY_ADDRESS ? ? ?KEY_F2
>> > ?#define SPITZ_KEY_FN ? ? ? ? ? KEY_F3
>> > @@ -263,7 +296,7 @@ EXPORT_SYMBOL(spitzscoop2_device);
>> > ?#define SPITZ_KEY_OK ? ? ? ? ? KEY_F11
>> > ?#define SPITZ_KEY_MENU ? ? ? ? KEY_F12
>> >
>> > -static const uint32_t spitzkbd_keymap[] = {
>> > +static const uint32_t sharpslc_keymap[] = {
>> > ? ? ? ?KEY(0, 0, KEY_LEFTCTRL),
>> > ? ? ? ?KEY(0, 1, KEY_1),
>> > ? ? ? ?KEY(0, 2, KEY_3),
>> > @@ -330,37 +363,48 @@ static const uint32_t spitzkbd_keymap[] = {
>> > ? ? ? ?KEY(6, 8, KEY_RIGHT),
>> > ?};
>> >
>> > -static const struct matrix_keymap_data spitzkbd_keymap_data = {
>> > - ? ? ? .keymap ? ? ? ? = spitzkbd_keymap,
>> > - ? ? ? .keymap_size ? ?= ARRAY_SIZE(spitzkbd_keymap),
>> > +static const struct matrix_keymap_data sharpslc_keymap_data = {
>> > + ? ? ? .keymap ? ? ? ? = sharpslc_keymap,
>> > + ? ? ? .keymap_size ? ?= ARRAY_SIZE(sharpslc_keymap),
>> > ?};
>> >
>> > -static const uint32_t spitzkbd_row_gpios[] =
>> > +static const uint32_t sharpslc_row_gpios[] =
>> > ? ? ? ? ? ? ? ?{ 12, 17, 91, 34, 36, 38, 39 };
>> > -static const uint32_t spitzkbd_col_gpios[] =
>> > +static const uint32_t sharpslc_col_gpios[] =
>> > ? ? ? ? ? ? ? ?{ 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 };
>> >
>> > -static struct matrix_keypad_platform_data spitzkbd_pdata = {
>> > - ? ? ? .keymap_data ? ? ? ? ? ?= &spitzkbd_keymap_data,
>> > - ? ? ? .row_gpios ? ? ? ? ? ? ?= spitzkbd_row_gpios,
>> > - ? ? ? .col_gpios ? ? ? ? ? ? ?= spitzkbd_col_gpios,
>> > - ? ? ? .num_row_gpios ? ? ? ? ?= ARRAY_SIZE(spitzkbd_row_gpios),
>> > - ? ? ? .num_col_gpios ? ? ? ? ?= ARRAY_SIZE(spitzkbd_col_gpios),
>> > +static struct matrix_keypad_platform_data sharpslc_mkp_pdata = {
>> > + ? ? ? .keymap_data ? ? ? ? ? ?= &sharpslc_keymap_data,
>> > + ? ? ? .row_gpios ? ? ? ? ? ? ?= sharpslc_row_gpios,
>> > + ? ? ? .col_gpios ? ? ? ? ? ? ?= sharpslc_col_gpios,
>> > + ? ? ? .num_row_gpios ? ? ? ? ?= ARRAY_SIZE(sharpslc_row_gpios),
>> > + ? ? ? .num_col_gpios ? ? ? ? ?= ARRAY_SIZE(sharpslc_col_gpios),
>> > ? ? ? ?.col_scan_delay_us ? ? ?= 10,
>> > ? ? ? ?.debounce_ms ? ? ? ? ? ?= 10,
>> > ? ? ? ?.wakeup ? ? ? ? ? ? ? ? = 1,
>> > ?};
>> >
>> > -static struct platform_device spitzkbd_device = {
>> > +static struct platform_device sharpslc_mkp_device = {
>> > ? ? ? ?.name ? ? ? ? ? = "matrix-keypad",
>> > ? ? ? ?.id ? ? ? ? ? ? = -1,
>> > ? ? ? ?.dev ? ? ? ? ? ?= {
>> > - ? ? ? ? ? ? ? .platform_data = &spitzkbd_pdata,
>> > + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_mkp_pdata,
>> > ? ? ? ?},
>> > ?};
>> >
>> > +static void __init sharpslc_mkp_init(void)
>> > +{
>> > + ? ? ? platform_device_register(&sharpslc_mkp_device);
>> > +}
>> > +#else
>> > +static inline void sharpslc_mkp_init(void) {}
>> > +#endif
>> >
>> > -static struct gpio_keys_button spitz_gpio_keys[] = {
>> > +/***********************************************************************
>> > ******* + * GPIO keys
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_KEYBOARD_GPIO) ||
>> > defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_button
>> > sharpslc_gpio_keys[] = {
>> > ? ? ? ?{
>> > ? ? ? ? ? ? ? ?.type ? = EV_PWR,
>> > ? ? ? ? ? ? ? ?.code ? = KEY_SUSPEND,
>> > @@ -383,27 +427,35 @@ static struct gpio_keys_button spitz_gpio_keys[] =
>> > { },
>> > ?};
>> >
>> > -static struct gpio_keys_platform_data spitz_gpio_keys_platform_data = {
>> > - ? ? ? .buttons ? ? ? ?= spitz_gpio_keys,
>> > - ? ? ? .nbuttons ? ? ? = ARRAY_SIZE(spitz_gpio_keys),
>> > +static struct gpio_keys_platform_data sharpslc_gpio_keys_platform_data =
>> > { + ? ? ? .buttons ? ? ? ?= sharpslc_gpio_keys,
>> > + ? ? ? .nbuttons ? ? ? = ARRAY_SIZE(sharpslc_gpio_keys),
>> > ?};
>> >
>> > -static struct platform_device spitz_gpio_keys_device = {
>> > +static struct platform_device sharpslc_gpio_keys_device = {
>> > ? ? ? ?.name ? = "gpio-keys",
>> > ? ? ? ?.id ? ? = -1,
>> > ? ? ? ?.dev ? ?= {
>> > - ? ? ? ? ? ? ? .platform_data ?= &spitz_gpio_keys_platform_data,
>> > + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_gpio_keys_platform_data,
>> > ? ? ? ?},
>> > ?};
>> >
>> > +static void __init sharpslc_keys_init(void)
>> > +{
>> > + ? ? ? platform_device_register(&sharpslc_gpio_keys_device);
>> > +}
>> > +#else
>> > +static inline void sharpslc_keys_init(void) {}
>> > +#endif
>> >
>> > -/*
>> > - * Spitz LEDs
>> > - */
>> > -static struct gpio_led spitz_gpio_leds[] = {
>> > +/***********************************************************************
>> > ******* + * LEDs
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_LEDS_GPIO) ||
>> > defined(CONFIG_LEDS_GPIO_MODULE) +static struct gpio_led
>> > sharpslc_gpio_leds[] = {
>> > ? ? ? ?{
>> > ? ? ? ? ? ? ? ?.name ? ? ? ? ? ? ? ? ? = "spitz:amber:charge",
>> > - ? ? ? ? ? ? ? .default_trigger ? ? ? ?= "sharpsl-charge",
>> > + ? ? ? ? ? ? ? .default_trigger ? ? ? ?= "sharpslc-charge",
>> > ? ? ? ? ? ? ? ?.gpio ? ? ? ? ? ? ? ? ? = SPITZ_GPIO_LED_ORANGE,
>> > ? ? ? ?},
>> > ? ? ? ?{
>> > @@ -413,25 +465,32 @@ static struct gpio_led spitz_gpio_leds[] = {
>> > ? ? ? ?},
>> > ?};
>> >
>> > -static struct gpio_led_platform_data spitz_gpio_leds_info = {
>> > - ? ? ? .leds ? ? ? ? ? = spitz_gpio_leds,
>> > - ? ? ? .num_leds ? ? ? = ARRAY_SIZE(spitz_gpio_leds),
>> > +static struct gpio_led_platform_data sharpslc_gpio_leds_info = {
>> > + ? ? ? .leds ? ? ? ? ? = sharpslc_gpio_leds,
>> > + ? ? ? .num_leds ? ? ? = ARRAY_SIZE(sharpslc_gpio_leds),
>> > ?};
>> >
>> > -static struct platform_device spitzled_device = {
>> > +static struct platform_device sharpslc_led_device = {
>> > ? ? ? ?.name ? ? ? ? ? = "leds-gpio",
>> > ? ? ? ?.id ? ? ? ? ? ? = -1,
>> > ? ? ? ?.dev ? ? ? ? ? ?= {
>> > - ? ? ? ? ? ? ? .platform_data = &spitz_gpio_leds_info,
>> > + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_gpio_leds_info,
>> > ? ? ? ?},
>> > ?};
>> >
>> > -#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
>> > -static struct pxa2xx_spi_master spitz_spi_info = {
>> > - ? ? ? .num_chipselect = 3,
>> > -};
>> > +static void __init sharpslc_leds_init(void)
>> > +{
>> > + ? ? ? platform_device_register(&sharpslc_led_device);
>> > +}
>> > +#else
>> > +static inline void sharpslc_leds_init(void) {}
>> > +#endif
>> >
>> > -static void spitz_wait_for_hsync(void)
>> > +/***********************************************************************
>> > ******* + * SSP Devices
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_SPI_PXA2XX) ||
>> > defined(CONFIG_SPI_PXA2XX_MODULE) +static void
>> > sharpslc_ads7846_wait_for_hsync(void)
>> > ?{
>> > ? ? ? ?while (gpio_get_value(SPITZ_GPIO_HSYNC))
>> > ? ? ? ? ? ? ? ?cpu_relax();
>> > @@ -440,21 +499,21 @@ static void spitz_wait_for_hsync(void)
>> > ? ? ? ? ? ? ? ?cpu_relax();
>> > ?}
>> >
>> > -static struct ads7846_platform_data spitz_ads7846_info = {
>> > +static struct ads7846_platform_data sharpslc_ads7846_info = {
>> > ? ? ? ?.model ? ? ? ? ? ? ? ? ?= 7846,
>> > ? ? ? ?.vref_delay_usecs ? ? ? = 100,
>> > ? ? ? ?.x_plate_ohms ? ? ? ? ? = 419,
>> > ? ? ? ?.y_plate_ohms ? ? ? ? ? = 486,
>> > ? ? ? ?.pressure_max ? ? ? ? ? = 1024,
>> > ? ? ? ?.gpio_pendown ? ? ? ? ? = SPITZ_GPIO_TP_INT,
>> > - ? ? ? .wait_for_sync ? ? ? ? ?= spitz_wait_for_hsync,
>> > + ? ? ? .wait_for_sync ? ? ? ? ?= sharpslc_ads7846_wait_for_hsync,
>> > ?};
>> >
>> > -static struct pxa2xx_spi_chip spitz_ads7846_chip = {
>> > +static struct pxa2xx_spi_chip sharpslc_ads7846_chip = {
>> > ? ? ? ?.gpio_cs ? ? ? ? ? ? ? ?= SPITZ_GPIO_ADS7846_CS,
>> > ?};
>> >
>> > -static void spitz_bl_kick_battery(void)
>> > +static void sharpslc_bl_kick_battery(void)
>> > ?{
>> > ? ? ? ?void (*kick_batt)(void);
>> >
>> > @@ -465,93 +524,109 @@ static void spitz_bl_kick_battery(void)
>> > ? ? ? ?}
>> > ?}
>> >
>> > -static struct corgi_lcd_platform_data spitz_lcdcon_info = {
>> > +static struct corgi_lcd_platform_data sharpslc_lcdcon_info = {
>> > ? ? ? ?.init_mode ? ? ? ? ? ? ?= CORGI_LCD_MODE_VGA,
>> > ? ? ? ?.max_intensity ? ? ? ? ?= 0x2f,
>> > ? ? ? ?.default_intensity ? ? ?= 0x1f,
>> > ? ? ? ?.limit_mask ? ? ? ? ? ? = 0x0b,
>> > ? ? ? ?.gpio_backlight_cont ? ?= SPITZ_GPIO_BACKLIGHT_CONT,
>> > ? ? ? ?.gpio_backlight_on ? ? ?= SPITZ_GPIO_BACKLIGHT_ON,
>> > - ? ? ? .kick_battery ? ? ? ? ? = spitz_bl_kick_battery,
>> > + ? ? ? .kick_battery ? ? ? ? ? = sharpslc_bl_kick_battery,
>> > ?};
>> >
>> > -static struct pxa2xx_spi_chip spitz_lcdcon_chip = {
>> > +static struct pxa2xx_spi_chip sharpslc_lcdcon_chip = {
>> > ? ? ? ?.gpio_cs ? ? ? ?= SPITZ_GPIO_LCDCON_CS,
>> > ?};
>> >
>> > -static struct pxa2xx_spi_chip spitz_max1111_chip = {
>> > +static struct pxa2xx_spi_chip sharpslc_max1111_chip = {
>> > ? ? ? ?.gpio_cs ? ? ? ?= SPITZ_GPIO_MAX1111_CS,
>> > ?};
>> >
>> > -static struct spi_board_info spitz_spi_devices[] = {
>> > +static struct spi_board_info sharpslc_spi_devices[] = {
>> > ? ? ? ?{
>> > - ? ? ? ? ? ? ? .modalias ? ? ? = "ads7846",
>> > - ? ? ? ? ? ? ? .max_speed_hz ? = 1200000,
>> > - ? ? ? ? ? ? ? .bus_num ? ? ? ?= 2,
>> > - ? ? ? ? ? ? ? .chip_select ? ?= 0,
>> > - ? ? ? ? ? ? ? .platform_data ?= &spitz_ads7846_info,
>> > - ? ? ? ? ? ? ? .controller_data= &spitz_ads7846_chip,
>> > - ? ? ? ? ? ? ? .irq ? ? ? ? ? ?= gpio_to_irq(SPITZ_GPIO_TP_INT),
>> > + ? ? ? ? ? ? ? .modalias ? ? ? ? ? ? ? = "ads7846",
>> > + ? ? ? ? ? ? ? .max_speed_hz ? ? ? ? ? = 1200000,
>> > + ? ? ? ? ? ? ? .bus_num ? ? ? ? ? ? ? ?= 2,
>> > + ? ? ? ? ? ? ? .chip_select ? ? ? ? ? ?= 0,
>> > + ? ? ? ? ? ? ? .platform_data ? ? ? ? ?= &sharpslc_ads7846_info,
>> > + ? ? ? ? ? ? ? .controller_data ? ? ? ?= &sharpslc_ads7846_chip,
>> > + ? ? ? ? ? ? ? .irq ? ? ? ? ? ? ? ? ? ?= gpio_to_irq(SPITZ_GPIO_TP_INT),
>> > ? ? ? ?}, {
>> > - ? ? ? ? ? ? ? .modalias ? ? ? = "corgi-lcd",
>> > - ? ? ? ? ? ? ? .max_speed_hz ? = 50000,
>> > - ? ? ? ? ? ? ? .bus_num ? ? ? ?= 2,
>> > - ? ? ? ? ? ? ? .chip_select ? ?= 1,
>> > - ? ? ? ? ? ? ? .platform_data ?= &spitz_lcdcon_info,
>> > - ? ? ? ? ? ? ? .controller_data= &spitz_lcdcon_chip,
>> > + ? ? ? ? ? ? ? .modalias ? ? ? ? ? ? ? = "corgi-lcd",
>> > + ? ? ? ? ? ? ? .max_speed_hz ? ? ? ? ? = 50000,
>> > + ? ? ? ? ? ? ? .bus_num ? ? ? ? ? ? ? ?= 2,
>> > + ? ? ? ? ? ? ? .chip_select ? ? ? ? ? ?= 1,
>> > + ? ? ? ? ? ? ? .platform_data ? ? ? ? ?= &sharpslc_lcdcon_info,
>> > + ? ? ? ? ? ? ? .controller_data ? ? ? ?= &sharpslc_lcdcon_chip,
>> > ? ? ? ?}, {
>> > - ? ? ? ? ? ? ? .modalias ? ? ? = "max1111",
>> > - ? ? ? ? ? ? ? .max_speed_hz ? = 450000,
>> > - ? ? ? ? ? ? ? .bus_num ? ? ? ?= 2,
>> > - ? ? ? ? ? ? ? .chip_select ? ?= 2,
>> > - ? ? ? ? ? ? ? .controller_data= &spitz_max1111_chip,
>> > + ? ? ? ? ? ? ? .modalias ? ? ? ? ? ? ? = "max1111",
>> > + ? ? ? ? ? ? ? .max_speed_hz ? ? ? ? ? = 450000,
>> > + ? ? ? ? ? ? ? .bus_num ? ? ? ? ? ? ? ?= 2,
>> > + ? ? ? ? ? ? ? .chip_select ? ? ? ? ? ?= 2,
>> > + ? ? ? ? ? ? ? .controller_data ? ? ? ?= &sharpslc_max1111_chip,
>> > ? ? ? ?},
>> > ?};
>> >
>> > -static void __init spitz_init_spi(void)
>> > +static struct pxa2xx_spi_master sharpslc_spi_info = {
>> > + ? ? ? .num_chipselect = 3,
>> > +};
>> > +
>> > +static void __init sharpslc_spi_init(void)
>> > ?{
>> > + ? ? ? struct corgi_lcd_platform_data *lcd_data = &sharpslc_lcdcon_info;
>> > +
>> > ? ? ? ?if (machine_is_akita()) {
>> > - ? ? ? ? ? ? ? spitz_lcdcon_info.gpio_backlight_cont =
>> > AKITA_GPIO_BACKLIGHT_CONT; -
>> > spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON; +
>> > ? ? ? lcd_data->gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT; +
>> > ? ? ? ? lcd_data->gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON; }
>> >
>> > - ? ? ? pxa2xx_set_spi_info(2, &spitz_spi_info);
>> > - ? ? ? spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
>> > + ? ? ? pxa2xx_set_spi_info(2, &sharpslc_spi_info);
>> > + ? ? ? spi_register_board_info(ARRAY_AND_SIZE(sharpslc_spi_devices));
>> > ?}
>> > ?#else
>> > -static inline void spitz_init_spi(void) {}
>> > +static inline void sharpslc_spi_init(void) {}
>> > ?#endif
>> >
>> > +/***********************************************************************
>> > ******* + * SD/MMC card controller
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_MMC_PXA) || defined(CONFIG_MMC_PXA_MODULE)
>> > ?/*
>> > - * MMC/SD Device
>> > - *
>> > - * The card detect interrupt isn't debounced so we delay it by 250ms
>> > - * to give the card a chance to fully insert/eject.
>> > + * NOTE: The card detect interrupt isn't debounced so we delay it by
>> > 250ms to + * give the card a chance to fully insert/eject.
>> > ?*/
>> > -static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
>> > +static void sharpslc_mci_setpower(struct device *dev, unsigned int vdd)
>> > ?{
>> > ? ? ? ?struct pxamci_platform_data* p_d = dev->platform_data;
>> >
>> > - ? ? ? if (( 1 << vdd) & p_d->ocr_mask)
>> > - ? ? ? ? ? ? ? spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0004);
>> > + ? ? ? if ((1 << vdd) & p_d->ocr_mask)
>> > + ? ? ? ? ? ? ? sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, SCOOP_CPR_SD_3V);
>> > ? ? ? ?else
>> > - ? ? ? ? ? ? ? spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0000);
>> > + ? ? ? ? ? ? ? sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
>> > ?}
>> >
>> > -static struct pxamci_platform_data spitz_mci_platform_data = {
>> > +static struct pxamci_platform_data sharpslc_mci_platform_data = {
>> > ? ? ? ?.detect_delay_ms ? ? ? ?= 250,
>> > ? ? ? ?.ocr_mask ? ? ? ? ? ? ? = MMC_VDD_32_33|MMC_VDD_33_34,
>> > - ? ? ? .setpower ? ? ? ? ? ? ? = spitz_mci_setpower,
>> > + ? ? ? .setpower ? ? ? ? ? ? ? = sharpslc_mci_setpower,
>> > ? ? ? ?.gpio_card_detect ? ? ? = SPITZ_GPIO_nSD_DETECT,
>> > ? ? ? ?.gpio_card_ro ? ? ? ? ? = SPITZ_GPIO_nSD_WP,
>> > ? ? ? ?.gpio_power ? ? ? ? ? ? = -1,
>> > ?};
>> >
>> > +static void __init sharpslc_mmc_init(void)
>> > +{
>> > + ? ? ? pxa_set_mci_info(&sharpslc_mci_platform_data);
>> > +}
>> > +#else
>> > +static inline void sharpslc_mmc_init(void) {}
>> > +#endif
>> >
>> > -/*
>> > - * USB Host (OHCI)
>> > - */
>> > -static int spitz_ohci_init(struct device *dev)
>> > +/***********************************************************************
>> > ******* + * USB Host
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_USB_OHCI_HCD) ||
>> > defined(CONFIG_USB_OHCI_HCD_MODULE) +static int
>> > sharpslc_ohci_init(struct device *dev)
>> > ?{
>> > ? ? ? ?int err;
>> >
>> > @@ -559,88 +634,114 @@ static int spitz_ohci_init(struct device *dev)
>> > ? ? ? ?if (err)
>> > ? ? ? ? ? ? ? ?return err;
>> >
>> > - ? ? ? /* Only Port 2 is connected
>> > - ? ? ? ?* Setup USB Port 2 Output Control Register
>> > - ? ? ? ?*/
>> > + ? ? ? /* Only Port 2 is connected, setup USB Port 2 Output Control
>> > Register */ UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE |
>> > UP2OCR_DMPDE;
>> >
>> > ? ? ? ?return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1);
>> > ?}
>> >
>> > -static void spitz_ohci_exit(struct device *dev)
>> > +static void sharpslc_ohci_exit(struct device *dev)
>> > ?{
>> > ? ? ? ?gpio_free(SPITZ_GPIO_USB_HOST);
>> > ?}
>> >
>> > -static struct pxaohci_platform_data spitz_ohci_platform_data = {
>> > +static struct pxaohci_platform_data sharpslc_ohci_platform_data = {
>> > ? ? ? ?.port_mode ? ? ?= PMM_NPS_MODE,
>> > - ? ? ? .init ? ? ? ? ? = spitz_ohci_init,
>> > - ? ? ? .exit ? ? ? ? ? = spitz_ohci_exit,
>> > + ? ? ? .init ? ? ? ? ? = sharpslc_ohci_init,
>> > + ? ? ? .exit ? ? ? ? ? = sharpslc_ohci_exit,
>> > ? ? ? ?.flags ? ? ? ? ?= ENABLE_PORT_ALL | NO_OC_PROTECTION,
>> > ? ? ? ?.power_budget ? = 150,
>> > ?};
>> >
>> > +static void __init sharpslc_uhc_init(void)
>> > +{
>> > + ? ? ? pxa_set_ohci_info(&sharpslc_ohci_platform_data);
>> > +}
>> > +#else
>> > +static inline void sharpslc_uhc_init(void) {}
>> > +#endif
>> >
>> > -/*
>> > - * Irda
>> > - */
>> > -
>> > -static struct pxaficp_platform_data spitz_ficp_platform_data = {
>> > -/* .gpio_pwdown is set in spitz_init() and akita_init() accordingly */
>> > +/***********************************************************************
>> > ******* + * IrDA
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_PXA_FICP) || defined(CONFIG_PXA_FICP_MODULE)
>> > +static struct pxaficp_platform_data sharpslc_ficp_platform_data = {
>> > .transceiver_cap ? ? ? ?= IR_SIRMODE | IR_OFF,
>> > ?};
>> >
>> > +static void __init sharpslc_irda_init(void)
>> > +{
>> > + ? ? ? if (machine_is_akita())
>> > + ? ? ? ? ? ? ? sharpslc_ficp_platform_data.gpio_pwdown =
>> > AKITA_GPIO_IR_ON; + ? ? ? else
>> > + ? ? ? ? ? ? ? sharpslc_ficp_platform_data.gpio_pwdown =
>> > SPITZ_GPIO_IR_ON;
>> >
>> > -/*
>> > - * Spitz PXA Framebuffer
>> > - */
>> > + ? ? ? pxa_set_ficp_info(&sharpslc_ficp_platform_data);
>> > +}
>> > +#else
>> > +static inline void sharpslc_irda_init(void) {}
>> > +#endif
>> >
>> > -static struct pxafb_mode_info spitz_pxafb_modes[] = {
>> > -{
>> > - ? ? ? .pixclock ? ? ? = 19231,
>> > - ? ? ? .xres ? ? ? ? ? = 480,
>> > - ? ? ? .yres ? ? ? ? ? = 640,
>> > - ? ? ? .bpp ? ? ? ? ? ?= 16,
>> > - ? ? ? .hsync_len ? ? ?= 40,
>> > - ? ? ? .left_margin ? ?= 46,
>> > - ? ? ? .right_margin ? = 125,
>> > - ? ? ? .vsync_len ? ? ?= 3,
>> > - ? ? ? .upper_margin ? = 1,
>> > - ? ? ? .lower_margin ? = 0,
>> > - ? ? ? .sync ? ? ? ? ? = 0,
>> > -},{
>> > - ? ? ? .pixclock ? ? ? = 134617,
>> > - ? ? ? .xres ? ? ? ? ? = 240,
>> > - ? ? ? .yres ? ? ? ? ? = 320,
>> > - ? ? ? .bpp ? ? ? ? ? ?= 16,
>> > - ? ? ? .hsync_len ? ? ?= 20,
>> > - ? ? ? .left_margin ? ?= 20,
>> > - ? ? ? .right_margin ? = 46,
>> > - ? ? ? .vsync_len ? ? ?= 2,
>> > - ? ? ? .upper_margin ? = 1,
>> > - ? ? ? .lower_margin ? = 0,
>> > - ? ? ? .sync ? ? ? ? ? = 0,
>> > -},
>> > -};
>> > -
>> > -static struct pxafb_mach_info spitz_pxafb_info = {
>> > - ? ? ? .modes ? ? ? ? ?= &spitz_pxafb_modes[0],
>> > - ? ? ? .num_modes ? ? ?= 2,
>> > +/***********************************************************************
>> > ******* + * Framebuffer
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_FB_PXA) || defined(CONFIG_FB_PXA_MODULE)
>> > +static struct pxafb_mode_info sharpslc_pxafb_modes[] = {
>> > + ? ? ? {
>> > + ? ? ? ? ? ? ? .pixclock ? ? ? = 19231,
>> > + ? ? ? ? ? ? ? .xres ? ? ? ? ? = 480,
>> > + ? ? ? ? ? ? ? .yres ? ? ? ? ? = 640,
>> > + ? ? ? ? ? ? ? .bpp ? ? ? ? ? ?= 16,
>> > + ? ? ? ? ? ? ? .hsync_len ? ? ?= 40,
>> > + ? ? ? ? ? ? ? .left_margin ? ?= 46,
>> > + ? ? ? ? ? ? ? .right_margin ? = 125,
>> > + ? ? ? ? ? ? ? .vsync_len ? ? ?= 3,
>> > + ? ? ? ? ? ? ? .upper_margin ? = 1,
>> > + ? ? ? ? ? ? ? .lower_margin ? = 0,
>> > + ? ? ? ? ? ? ? .sync ? ? ? ? ? = 0,
>> > + ? ? ? }, {
>> > + ? ? ? ? ? ? ? .pixclock ? ? ? = 134617,
>> > + ? ? ? ? ? ? ? .xres ? ? ? ? ? = 240,
>> > + ? ? ? ? ? ? ? .yres ? ? ? ? ? = 320,
>> > + ? ? ? ? ? ? ? .bpp ? ? ? ? ? ?= 16,
>> > + ? ? ? ? ? ? ? .hsync_len ? ? ?= 20,
>> > + ? ? ? ? ? ? ? .left_margin ? ?= 20,
>> > + ? ? ? ? ? ? ? .right_margin ? = 46,
>> > + ? ? ? ? ? ? ? .vsync_len ? ? ?= 2,
>> > + ? ? ? ? ? ? ? .upper_margin ? = 1,
>> > + ? ? ? ? ? ? ? .lower_margin ? = 0,
>> > + ? ? ? ? ? ? ? .sync ? ? ? ? ? = 0,
>> > + ? ? ? },
>> > +};
>> > +
>> > +static struct pxafb_mach_info sharpslc_pxafb_info = {
>> > + ? ? ? .modes ? ? ? ? ?= sharpslc_pxafb_modes,
>> > + ? ? ? .num_modes ? ? ?= ARRAY_SIZE(sharpslc_pxafb_modes),
>> > ? ? ? ?.fixed_modes ? ?= 1,
>> > ? ? ? ?.lcd_conn ? ? ? = LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
>> > ?};
>> >
>> > -static struct mtd_partition sharpsl_nand_partitions[] = {
>> > +static void __init sharpslc_lcd_init(void)
>> > +{
>> > + ? ? ? set_pxa_fb_info(&sharpslc_pxafb_info);
>> > +}
>> > +#else
>> > +static inline void sharpslc_lcd_init(void) {}
>> > +#endif
>> > +
>> > +/***********************************************************************
>> > ******* + * Framebuffer
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_MTD_NAND_SHARPSL) ||
>> > defined(CONFIG_MTD_NAND_SHARPSL_MODULE) +static struct mtd_partition
>> > sharpslc_nand_partitions[] = {
>> > ? ? ? ?{
>> > ? ? ? ? ? ? ? ?.name = "System Area",
>> > ? ? ? ? ? ? ? ?.offset = 0,
>> > ? ? ? ? ? ? ? ?.size = 7 * 1024 * 1024,
>> > - ? ? ? },
>> > - ? ? ? {
>> > + ? ? ? }, {
>> > ? ? ? ? ? ? ? ?.name = "Root Filesystem",
>> > ? ? ? ? ? ? ? ?.offset = 7 * 1024 * 1024,
>> > - ? ? ? },
>> > - ? ? ? {
>> > + ? ? ? }, {
>> > ? ? ? ? ? ? ? ?.name = "Home Filesystem",
>> > ? ? ? ? ? ? ? ?.offset = MTDPART_OFS_APPEND,
>> > ? ? ? ? ? ? ? ?.size = MTDPART_SIZ_FULL,
>> > @@ -649,37 +750,72 @@ static struct mtd_partition
>> > sharpsl_nand_partitions[] = {
>> >
>> > ?static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
>> >
>> > -static struct nand_bbt_descr sharpsl_bbt = {
>> > - ? ? ? .options = 0,
>> > - ? ? ? .offs = 4,
>> > - ? ? ? .len = 2,
>> > - ? ? ? .pattern = scan_ff_pattern
>> > +static struct nand_bbt_descr sharpslc_nand_bbt = {
>> > + ? ? ? .options ? ? ? ?= 0,
>> > + ? ? ? .offs ? ? ? ? ? = 4,
>> > + ? ? ? .len ? ? ? ? ? ?= 2,
>> > + ? ? ? .pattern ? ? ? ?= scan_ff_pattern
>> > +};
>> > +
>> > +static struct nand_ecclayout sharpslc_akita_oobinfo = {
>> > + ? ? ? .oobfree ? ? ? ?= { {0x08, 0x09} },
>> > + ? ? ? .eccbytes ? ? ? = 24,
>> > + ? ? ? .eccpos ? ? ? ? = {
>> > + ? ? ? ? ? ? ? ? ? ? ? 0x05, 0x01, 0x02, 0x03, 0x06, 0x07, 0x15, 0x11,
>> > + ? ? ? ? ? ? ? ? ? ? ? 0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
>> > + ? ? ? ? ? ? ? ? ? ? ? 0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37,
>> > + ? ? ? },
>> > ?};
>> >
>> > -static struct sharpsl_nand_platform_data sharpsl_nand_platform_data = {
>> > - ? ? ? .badblock_pattern ? ? ? = &sharpsl_bbt,
>> > - ? ? ? .partitions ? ? ? ? ? ? = sharpsl_nand_partitions,
>> > - ? ? ? .nr_partitions ? ? ? ? ?= ARRAY_SIZE(sharpsl_nand_partitions),
>> > +static struct sharpsl_nand_platform_data sharpslc_nand_pdata = {
>> > + ? ? ? .badblock_pattern ? ? ? = &sharpslc_nand_bbt,
>> > + ? ? ? .partitions ? ? ? ? ? ? = sharpslc_nand_partitions,
>> > + ? ? ? .nr_partitions ? ? ? ? ?= ARRAY_SIZE(sharpslc_nand_partitions),
>> > ?};
>> >
>> > -static struct resource sharpsl_nand_resources[] = {
>> > +static struct resource sharpslc_nand_resources[] = {
>> > ? ? ? ?{
>> > - ? ? ? ? ? ? ? .start ?= 0x0C000000,
>> > - ? ? ? ? ? ? ? .end ? ?= 0x0C000FFF,
>> > + ? ? ? ? ? ? ? .start ?= PXA_CS3_PHYS,
>> > + ? ? ? ? ? ? ? .end ? ?= PXA_CS3_PHYS + SZ_4K - 1,
>> > ? ? ? ? ? ? ? ?.flags ?= IORESOURCE_MEM,
>> > ? ? ? ?},
>> > ?};
>> >
>> > -static struct platform_device sharpsl_nand_device = {
>> > +static struct platform_device sharpslc_nand_device = {
>> > ? ? ? ?.name ? ? ? ? ? = "sharpsl-nand",
>> > ? ? ? ?.id ? ? ? ? ? ? = -1,
>> > - ? ? ? .resource ? ? ? = sharpsl_nand_resources,
>> > - ? ? ? .num_resources ?= ARRAY_SIZE(sharpsl_nand_resources),
>> > - ? ? ? .dev.platform_data ? ? ?= &sharpsl_nand_platform_data,
>> > + ? ? ? .resource ? ? ? = sharpslc_nand_resources,
>> > + ? ? ? .num_resources ?= ARRAY_SIZE(sharpslc_nand_resources),
>> > + ? ? ? .dev ? ? ? ? ? ?= {
>> > + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_nand_pdata,
>> > + ? ? ? }
>> > ?};
>> >
>> > +static void __init sharpslc_nand_init(void)
>> > +{
>> > + ? ? ? if (machine_is_spitz()) {
>> > + ? ? ? ? ? ? ? sharpslc_nand_partitions[1].size = 5 * 1024 * 1024;
>> > + ? ? ? } else if (machine_is_akita()) {
>> > + ? ? ? ? ? ? ? sharpslc_nand_partitions[1].size = 58 * 1024 * 1024;
>> > + ? ? ? ? ? ? ? sharpslc_nand_bbt.len = 1;
>> > + ? ? ? ? ? ? ? sharpslc_nand_pdata.ecc_layout = &sharpslc_akita_oobinfo;
>> > + ? ? ? } else if (machine_is_borzoi()) {
>> > + ? ? ? ? ? ? ? sharpslc_nand_partitions[1].size = 32 * 1024 * 1024;
>> > + ? ? ? ? ? ? ? sharpslc_nand_bbt.len = 1;
>> > + ? ? ? ? ? ? ? sharpslc_nand_pdata.ecc_layout = &sharpslc_akita_oobinfo;
>> > + ? ? ? }
>> > +
>> > + ? ? ? platform_device_register(&sharpslc_nand_device);
>> > +}
>> > +#else
>> > +static inline void sharpslc_nand_init(void) {}
>> > +#endif
>> >
>> > -static struct mtd_partition sharpsl_rom_parts[] = {
>> > +/***********************************************************************
>> > ******* + * NOR Flash
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_MTD_PHYSMAP) ||
>> > defined(CONFIG_MTD_PHYSMAP_MODULE) +static struct mtd_partition
>> > sharpslc_rom_parts[] = {
>> > ? ? ? ?{
>> > ? ? ? ? ? ? ? ?.name ? ="Boot PROM Filesystem",
>> > ? ? ? ? ? ? ? ?.offset = 0x00140000,
>> > @@ -687,161 +823,152 @@ static struct mtd_partition sharpsl_rom_parts[] =
>> > { },
>> > ?};
>> >
>> > -static struct physmap_flash_data sharpsl_rom_data = {
>> > +static struct physmap_flash_data sharpslc_rom_data = {
>> > ? ? ? ?.width ? ? ? ? ?= 2,
>> > - ? ? ? .nr_parts ? ? ? = ARRAY_SIZE(sharpsl_rom_parts),
>> > - ? ? ? .parts ? ? ? ? ?= sharpsl_rom_parts,
>> > + ? ? ? .nr_parts ? ? ? = ARRAY_SIZE(sharpslc_rom_parts),
>> > + ? ? ? .parts ? ? ? ? ?= sharpslc_rom_parts,
>> > ?};
>> >
>> > -static struct resource sharpsl_rom_resources[] = {
>> > +static struct resource sharpslc_rom_resources[] = {
>> > ? ? ? ?{
>> > - ? ? ? ? ? ? ? .start ?= 0x00000000,
>> > - ? ? ? ? ? ? ? .end ? ?= 0x007fffff,
>> > + ? ? ? ? ? ? ? .start ?= PXA_CS0_PHYS,
>> > + ? ? ? ? ? ? ? .end ? ?= PXA_CS0_PHYS + SZ_8M - 1,
>> > ? ? ? ? ? ? ? ?.flags ?= IORESOURCE_MEM,
>> > ? ? ? ?},
>> > ?};
>> >
>> > -static struct platform_device sharpsl_rom_device = {
>> > - ? ? ? .name ? = "physmap-flash",
>> > - ? ? ? .id ? ? = -1,
>> > - ? ? ? .resource = sharpsl_rom_resources,
>> > - ? ? ? .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
>> > - ? ? ? .dev.platform_data = &sharpsl_rom_data,
>> > -};
>> > -
>> > -static struct platform_device *devices[] __initdata = {
>> > - ? ? ? &spitzscoop_device,
>> > - ? ? ? &spitzkbd_device,
>> > - ? ? ? &spitz_gpio_keys_device,
>> > - ? ? ? &spitzled_device,
>> > - ? ? ? &sharpsl_nand_device,
>> > - ? ? ? &sharpsl_rom_device,
>> > +static struct platform_device sharpslc_rom_device = {
>> > + ? ? ? .name ? ? ? ? ? = "physmap-flash",
>> > + ? ? ? .id ? ? ? ? ? ? = -1,
>> > + ? ? ? .resource ? ? ? = sharpslc_rom_resources,
>> > + ? ? ? .num_resources ?= ARRAY_SIZE(sharpslc_rom_resources),
>> > + ? ? ? .dev ? ? ? ? ? ?= {
>> > + ? ? ? ? ? ? ? .platform_data ?= &sharpslc_rom_data,
>> > + ? ? ? },
>> > ?};
>> >
>> > -static void spitz_poweroff(void)
>> > +static void __init sharpslc_nor_init(void)
>> > ?{
>> > - ? ? ? arm_machine_restart('g', NULL);
>> > + ? ? ? platform_device_register(&sharpslc_rom_device);
>> > ?}
>> > +#else
>> > +static inline void sharpslc_nor_init(void) {}
>> > +#endif
>> >
>> > -static void spitz_restart(char mode, const char *cmd)
>> > -{
>> > - ? ? ? /* Bootloader magic for a reboot */
>> > - ? ? ? if((MSC0 & 0xffff0000) == 0x7ff00000)
>> > - ? ? ? ? ? ? ? MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
>> > -
>> > - ? ? ? spitz_poweroff();
>> > -}
>> > +/***********************************************************************
>> > ******* + * GPIO expander
>> > +
>> > ************************************************************************
>> > ******/ +#if defined(CONFIG_I2C_PXA) || defined(CONFIG_I2C_PXA_MODULE)
>> > +static struct pca953x_platform_data akita_pca953x_pdata = {
>> > + ? ? ? .gpio_base ? ? ? ? ? ? ?= AKITA_IOEXP_GPIO_BASE,
>> > +};
>> >
>> > -static void __init common_init(void)
>> > -{
>> > - ? ? ? init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
>> > - ? ? ? pm_power_off = spitz_poweroff;
>> > - ? ? ? arm_pm_restart = spitz_restart;
>> > +static struct i2c_board_info sharpslc_i2c_devs[] = {
>> > + ? ? ? {
>> > + ? ? ? ? ? ? ? .type ? ? ? ? ? = "wm8750",
>> > + ? ? ? ? ? ? ? .addr ? ? ? ? ? = 0x1b,
>> > + ? ? ? }, {
>> > + ? ? ? ? ? ? ? .type ? ? ? ? ? = "max7310",
>> > + ? ? ? ? ? ? ? .addr ? ? ? ? ? = 0x18,
>> > + ? ? ? ? ? ? ? .platform_data ?= &akita_pca953x_pdata,
>> > + ? ? ? },
>> > +};
>> >
>> > - ? ? ? if (machine_is_spitz()) {
>> > - ? ? ? ? ? ? ? sharpsl_nand_partitions[1].size = 5 * 1024 * 1024;
>> > - ? ? ? } else if (machine_is_akita()) {
>> > - ? ? ? ? ? ? ? sharpsl_nand_partitions[1].size = 58 * 1024 * 1024;
>> > - ? ? ? } else if (machine_is_borzoi()) {
>> > - ? ? ? ? ? ? ? sharpsl_nand_partitions[1].size = 32 * 1024 * 1024;
>> > +static struct regulator_consumer_supply isl6271a_consumers[] = {
>> > + ? ? ? {
>> > + ? ? ? ? ? ? ? .supply = "vcc_core",
>> > ? ? ? ?}
>> > +};
>> >
>> > - ? ? ? PMCR = 0x00;
>> > -
>> > - ? ? ? /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
>> > - ? ? ? PCFR |= PCFR_OPDE;
>> > +static struct regulator_init_data isl6271a_info[] = {
>> > + ? ? ? {
>> > + ? ? ? ? ? ? ? .constraints = {
>> > + ? ? ? ? ? ? ? ? ? ? ? .name ? ? ? ? ? = "vcc_core range",
>> > + ? ? ? ? ? ? ? ? ? ? ? .min_uV ? ? ? ? = 850000,
>> > + ? ? ? ? ? ? ? ? ? ? ? .max_uV ? ? ? ? = 1600000,
>> > + ? ? ? ? ? ? ? ? ? ? ? .always_on ? ? ?= 1,
>> > + ? ? ? ? ? ? ? ? ? ? ? .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
>> > + ? ? ? ? ? ? ? },
>> > + ? ? ? .consumer_supplies ? ? ?= isl6271a_consumers,
>> > + ? ? ? .num_consumer_supplies ?= ARRAY_SIZE(isl6271a_consumers),
>> > + ? ? ? }
>> > +};
>> >
>> > - ? ? ? pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
>> > +static struct i2c_board_info sharpslc_pi2c_devs[] = {
>> > + ? ? ? {
>> > + ? ? ? ? ? ? ? .type ? ? ? ? ? = "isl6271a",
>> > + ? ? ? ? ? ? ? .addr ? ? ? ? ? = 0x0c,
>> > + ? ? ? ? ? ? ? .platform_data ?= &isl6271a_info,
>> > + ? ? ? },
>> > +};
>> >
>> > - ? ? ? pxa_set_ffuart_info(NULL);
>> > - ? ? ? pxa_set_btuart_info(NULL);
>> > - ? ? ? pxa_set_stuart_info(NULL);
>> > +static void __init sharpslc_i2c_init(void)
>> > +{
>> > + ? ? ? int size = ARRAY_SIZE(sharpslc_i2c_devs);
>> >
>> > - ? ? ? spitz_init_spi();
>> > + ? ? ? /* Only Akita has the max7310 chip */
>> > + ? ? ? if (!machine_is_akita())
>> > + ? ? ? ? ? ? ? size--;
>> >
>> > - ? ? ? platform_add_devices(devices, ARRAY_SIZE(devices));
>> > - ? ? ? pxa_set_mci_info(&spitz_mci_platform_data);
>> > - ? ? ? pxa_set_ohci_info(&spitz_ohci_platform_data);
>> > - ? ? ? pxa_set_ficp_info(&spitz_ficp_platform_data);
>> > - ? ? ? set_pxa_fb_info(&spitz_pxafb_info);
>> > ? ? ? ?pxa_set_i2c_info(NULL);
>> > + ? ? ? pxa27x_set_i2c_power_info(NULL);
>> > + ? ? ? i2c_register_board_info(0, sharpslc_i2c_devs, size);
>> > + ? ? ? i2c_register_board_info(1, ARRAY_AND_SIZE(sharpslc_pi2c_devs));
>> > ?}
>> > -
>> > -#if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI)
>> > -static struct nand_bbt_descr sharpsl_akita_bbt = {
>> > - ? ? ? .options = 0,
>> > - ? ? ? .offs = 4,
>> > - ? ? ? .len = 1,
>> > - ? ? ? .pattern = scan_ff_pattern
>> > -};
>> > -
>> > -static struct nand_ecclayout akita_oobinfo = {
>> > - ? ? ? .eccbytes = 24,
>> > - ? ? ? .eccpos = {
>> > - ? ? ? ? ? ? ? ? ?0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
>> > - ? ? ? ? ? ? ? ? ?0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
>> > - ? ? ? ? ? ? ? ? ?0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
>> > - ? ? ? .oobfree = {{0x08, 0x09}}
>> > -};
>> > +#else
>> > +static inline void sharpslc_i2c_init(void) {}
>> > ?#endif
>> >
>> > -#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
>> > -static void __init spitz_init(void)
>> > +/***********************************************************************
>> > ******* + * Machine init
>> > +
>> > ************************************************************************
>> > ******/ +static void sharpslc_poweroff(void)
>> > ?{
>> > - ? ? ? spitz_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
>> > -
>> > -#ifdef CONFIG_MACH_BORZOI
>> > - ? ? ? if (machine_is_borzoi()) {
>> > - ? ? ? ? ? ? ? sharpsl_nand_platform_data.badblock_pattern =
>> > &sharpsl_akita_bbt; -
>> > sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo; - ? ? ? }
>> > -#endif
>> > -
>> > - ? ? ? platform_scoop_config = &spitz_pcmcia_config;
>> > -
>> > - ? ? ? common_init();
>> > -
>> > - ? ? ? platform_device_register(&spitzscoop2_device);
>> > + ? ? ? arm_machine_restart('g', NULL);
>> > ?}
>> > -#endif
>> >
>> > -#ifdef CONFIG_MACH_AKITA
>> > -/*
>> > - * Akita IO Expander
>> > - */
>> > -static struct pca953x_platform_data akita_ioexp = {
>> > - ? ? ? .gpio_base ? ? ? ? ? ? ?= AKITA_IOEXP_GPIO_BASE,
>> > -};
>> > +static void sharpslc_restart(char mode, const char *cmd)
>> > +{
>> > + ? ? ? /* Bootloader magic for a reboot */
>> > + ? ? ? if ((MSC0 & 0xffff0000) == 0x7ff00000)
>> > + ? ? ? ? ? ? ? MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
>> >
>> > -static struct i2c_board_info akita_i2c_board_info[] = {
>> > - ? ? ? {
>> > - ? ? ? ? ? ? ? .type ? ? ? ? ? = "max7310",
>> > - ? ? ? ? ? ? ? .addr ? ? ? ? ? = 0x18,
>> > - ? ? ? ? ? ? ? .platform_data ?= &akita_ioexp,
>> > - ? ? ? }, {
>> > - ? ? ? ? ? ? ? .type ? ? ? ? ? = "wm8750",
>> > - ? ? ? ? ? ? ? .addr ? ? ? ? ? = 0x1b,
>> > - ? ? ? },
>> > -};
>> > + ? ? ? sharpslc_poweroff();
>> > +}
>> >
>> > -static void __init akita_init(void)
>> > +static void __init sharpslc_init(void)
>> > ?{
>> > - ? ? ? spitz_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
>> > + ? ? ? init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
>> > + ? ? ? pm_power_off = sharpslc_poweroff;
>> > + ? ? ? arm_pm_restart = sharpslc_restart;
>> > +
>> > + ? ? ? PMCR = 0x00;
>> >
>> > - ? ? ? sharpsl_nand_platform_data.badblock_pattern = &sharpsl_akita_bbt;
>> > - ? ? ? sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo;
>> > + ? ? ? /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
>> > + ? ? ? PCFR |= PCFR_OPDE;
>> >
>> > - ? ? ? /* We just pretend the second element of the array doesn't exist
>> > */ - ? ? ? spitz_pcmcia_config.num_devs = 1;
>> > - ? ? ? platform_scoop_config = &spitz_pcmcia_config;
>> > + ? ? ? pxa2xx_mfp_config(ARRAY_AND_SIZE(sharpslc_pin_config));
>> >
>> > - ? ? ? i2c_register_board_info(0, ARRAY_AND_SIZE(akita_i2c_board_info));
>> > + ? ? ? pxa_set_ffuart_info(NULL);
>> > + ? ? ? pxa_set_btuart_info(NULL);
>> > + ? ? ? pxa_set_stuart_info(NULL);
>> >
>> > - ? ? ? common_init();
>> > + ? ? ? sharpslc_spi_init();
>> > + ? ? ? sharpslc_scoop_init();
>> > + ? ? ? sharpslc_mkp_init();
>> > + ? ? ? sharpslc_keys_init();
>> > + ? ? ? sharpslc_leds_init();
>> > + ? ? ? sharpslc_mmc_init();
>> > + ? ? ? sharpslc_pcmcia_init();
>> > + ? ? ? sharpslc_irda_init();
>> > + ? ? ? sharpslc_uhc_init();
>> > + ? ? ? sharpslc_lcd_init();
>> > + ? ? ? sharpslc_nor_init();
>> > + ? ? ? sharpslc_nand_init();
>> > + ? ? ? sharpslc_i2c_init();
>> > ?}
>> > -#endif
>> >
>> > -static void __init fixup_spitz(struct machine_desc *desc,
>> > +static void __init sharpslc_fixup(struct machine_desc *desc,
>> > ? ? ? ? ? ? ? ?struct tag *tags, char **cmdline, struct meminfo *mi)
>> > ?{
>> > ? ? ? ?sharpsl_save_param();
>> > @@ -855,10 +982,10 @@ static void __init fixup_spitz(struct machine_desc
>> > *desc, MACHINE_START(SPITZ, "SHARP Spitz")
>> > ? ? ? ?.phys_io ? ? ? ?= 0x40000000,
>> > ? ? ? ?.io_pg_offst ? ?= (io_p2v(0x40000000) >> 18) & 0xfffc,
>> > - ? ? ? .fixup ? ? ? ? ?= fixup_spitz,
>> > + ? ? ? .fixup ? ? ? ? ?= sharpslc_fixup,
>> > ? ? ? ?.map_io ? ? ? ? = pxa_map_io,
>> > ? ? ? ?.init_irq ? ? ? = pxa27x_init_irq,
>> > - ? ? ? .init_machine ? = spitz_init,
>> > + ? ? ? .init_machine ? = sharpslc_init,
>> > ? ? ? ?.timer ? ? ? ? ?= &pxa_timer,
>> > ?MACHINE_END
>> > ?#endif
>> > @@ -867,10 +994,10 @@ MACHINE_END
>> > ?MACHINE_START(BORZOI, "SHARP Borzoi")
>> > ? ? ? ?.phys_io ? ? ? ?= 0x40000000,
>> > ? ? ? ?.io_pg_offst ? ?= (io_p2v(0x40000000) >> 18) & 0xfffc,
>> > - ? ? ? .fixup ? ? ? ? ?= fixup_spitz,
>> > + ? ? ? .fixup ? ? ? ? ?= sharpslc_fixup,
>> > ? ? ? ?.map_io ? ? ? ? = pxa_map_io,
>> > ? ? ? ?.init_irq ? ? ? = pxa27x_init_irq,
>> > - ? ? ? .init_machine ? = spitz_init,
>> > + ? ? ? .init_machine ? = sharpslc_init,
>> > ? ? ? ?.timer ? ? ? ? ?= &pxa_timer,
>> > ?MACHINE_END
>> > ?#endif
>> > @@ -879,10 +1006,10 @@ MACHINE_END
>> > ?MACHINE_START(AKITA, "SHARP Akita")
>> > ? ? ? ?.phys_io ? ? ? ?= 0x40000000,
>> > ? ? ? ?.io_pg_offst ? ?= (io_p2v(0x40000000) >> 18) & 0xfffc,
>> > - ? ? ? .fixup ? ? ? ? ?= fixup_spitz,
>> > + ? ? ? .fixup ? ? ? ? ?= sharpslc_fixup,
>> > ? ? ? ?.map_io ? ? ? ? = pxa_map_io,
>> > ? ? ? ?.init_irq ? ? ? = pxa27x_init_irq,
>> > - ? ? ? .init_machine ? = akita_init,
>> > + ? ? ? .init_machine ? = sharpslc_init,
>> > ? ? ? ?.timer ? ? ? ? ?= &pxa_timer,
>> > ?MACHINE_END
>> > ?#endif
>> > --
>> > 1.7.1
>


From jason77.wang at gmail.com  Mon Jun 28 08:59:55 2010
From: jason77.wang at gmail.com (jason)
Date: Mon, 28 Jun 2010 20:59:55 +0800
Subject: [PATCH] spi/omap2_mcspi: disable and enable chan between each
	SPI 	transfer
In-Reply-To: <E1C7579D1379824DAE67858071C810382DD8495B26@NOK-EUMSG-02.mgdnok.nokia.com>
References: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com>
	<AANLkTin7mqe_zJIbyDcRPpCLaxPhl_dZQrSGua2z1nYW@mail.gmail.com>
	<4C24A182.4060009@gmail.com>
	<E1C7579D1379824DAE67858071C810382DD8495B26@NOK-EUMSG-02.mgdnok.nokia.com>
Message-ID: <4C289CCB.7010409@gmail.com>

roman.tereshonkov at nokia.com wrote:
>  
>
>   
>> -----Original Message-----
>> From: ext jason [mailto:jason77.wang at gmail.com] 
>> Sent: 25 June, 2010 15:31
>> To: Grant Likely
>> Cc: Tereshonkov Roman (Nokia-D/Helsinki); david-b at pacbell.net; 
>>     
>>     
[snip]
>> the RXS bit will be set to status register immediately,
>> write a dummy data to TX register to trigger this session(in 
>> fact this  
>> trigger  doesn't take  effect),
>> check the RXS bit and read the first data(the first data is the last 
>> random data received in TX_ONLY transfer).
>>
>>     
>
> For me it is very strange that you have RXS bit set after TX_ONLY transmission.
> The problem might be elsewhere and your solution will just mask the real problem.
> Can you enable the spi debug and error logs and show them for your broken case.
>
> Regards
> Roman Tereshonkov
>
>   
Hi Roman,
I don't know how to enable the spi debug and generate an error log, but 
i design
3 testcases to investigate this issue. These 3 testcases are based off 
the latest upstream.
test1: After TX_ONLY transfer, we will change this channel to RX_ONLY 
mode. And then we
will write a dummy data to trigger this RX transaction, here i add a 
polling RXS bit
before write triggering data, from the result, we can see we 
successfully to get a RXS
bit and read an unmeaningful data.(this prove the write triggering data 
is not necessary
to start a rx transaction).
test2: This time i move the polling RXS bit to the location after the 
write trigger data, we can get
RXS bit as well and read an unmeaningful data too. The data read out is 
identical to the one
in test1.(This prove the write trigger data don't take effect in fact).
test3: Except i revert the commit a330ce2 "omap2_mcspi: Flush posted 
writes", other is same as the test2.
But this time, we read out a correct data ads7846 sending out. (I don't 
know why this commit can
affect the result, maybe it is time issue. If we can disable this 
channel after TX_ONLY transfer and
reenable it before RX_ONLY transfer, we will not get RXS bit in test1, 
and will read out a correct data
both in test2 and test3).

Test1 result output & patch:
# =====SPI MESSAGE BEGIN=====
tansferTX: conf=1123d4, data=93
tansferRX: conf=1113d4, data=0
rx_data = f0
tansferTX: conf=1123d4, data=93
tansferRX: conf=1113d4, data=0
rx_data = f0
*****SPI MESSAGE END*****
=====SPI MESSAGE BEGIN=====
tansferTX: conf=1123d4, data=93
tansferRX: conf=1113d4, data=0
rx_data = f0
tansferTX: conf=1123d4, data=93
tansferRX: conf=1113d4, data=0
rx_data = f0
*****SPI MESSAGE END*****


Subject: [PATCH] SPI/test1: get rx_data in RX_ONLY transfer before 
trigger writing

get rx_data in RX_ONLY transfer before trigger writing dummy data to
TX register.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
drivers/spi/omap2_mcspi.c | 19 ++++++++++++++-----
1 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index b3a94ca..ddfe4b0 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -893,7 +893,7 @@ static void omap2_mcspi_work(struct work_struct *work)
spi = m->spi;
cs = spi->controller_state;
cd = spi->controller_data;
-
+ printk("=====SPI MESSAGE BEGIN=====\n");
omap2_mcspi_set_enable(spi, 1);
list_for_each_entry(t, &m->transfers, transfer_list) {
if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
@@ -928,17 +928,26 @@ static void omap2_mcspi_work(struct work_struct 
*work)
if (t->len > ((cs->word_len + 7) >> 3))
chconf |= OMAP2_MCSPI_CHCONF_TURBO;
}
-
+ printk("tansfer%s: conf=%x, data=%x\n", t->tx_buf ? "TX" : "RX",
+ chconf, t->tx_buf ? *(u8 *)(t->tx_buf) : 0);
mcspi_write_chconf0(spi, chconf);

if (t->len) {
unsigned count;

/* RX_ONLY mode needs dummy data in TX reg */
- if (t->tx_buf == NULL)
+ if (t->tx_buf == NULL) {
+ u8 rx_data;
+ if (mcspi_wait_for_reg_bit(cs->base + OMAP2_MCSPI_CHSTAT0,
+ OMAP2_MCSPI_CHSTAT_RXS) < 0)
+ dev_err(&spi->dev, "RXS timed out\n");
+
+ rx_data = __raw_readl(cs->base + OMAP2_MCSPI_RX0);
+ printk("rx_data = %x\n", rx_data);
+
__raw_writel(0, cs->base
+ OMAP2_MCSPI_TX0);
-
+ }
if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
count = omap2_mcspi_txrx_dma(spi, t);
else
@@ -971,7 +980,7 @@ static void omap2_mcspi_work(struct work_struct *work)
omap2_mcspi_force_cs(spi, 0);

omap2_mcspi_set_enable(spi, 0);
-
+ printk("*****SPI MESSAGE END*****\n");
m->status = status;
m->complete(m->context);

-- 
1.5.6.5


Test2 result output & patch:
# =====SPI MESSAGE BEGIN=====
tansferTX: conf=1123d4, data=93
tansferRX: conf=1113d4, data=0
rx_data = f0
tansferTX: conf=1123d4, data=93
tansferRX: conf=1113d4, data=0
rx_data = f0
*****SPI MESSAGE END*****
=====SPI MESSAGE BEGIN=====
tansferTX: conf=1123d4, data=93
tansferRX: conf=1113d4, data=0
rx_data = f0
tansferTX: conf=1123d4, data=93
tansferRX: conf=1113d4, data=0
rx_data = f0
*****SPI MESSAGE END*****

Subject: [PATCH] SPI/test2: get rx_data in RX_ONLY transfer after 
trigger writing

get rx_data in RX_ONLY transfer after trigger writing dummy data to
TX register.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
drivers/spi/omap2_mcspi.c | 18 ++++++++++++++----
1 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index b3a94ca..96c508a 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -893,7 +893,7 @@ static void omap2_mcspi_work(struct work_struct *work)
spi = m->spi;
cs = spi->controller_state;
cd = spi->controller_data;
-
+ printk("=====SPI MESSAGE BEGIN=====\n");
omap2_mcspi_set_enable(spi, 1);
list_for_each_entry(t, &m->transfers, transfer_list) {
if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
@@ -928,17 +928,27 @@ static void omap2_mcspi_work(struct work_struct 
*work)
if (t->len > ((cs->word_len + 7) >> 3))
chconf |= OMAP2_MCSPI_CHCONF_TURBO;
}
-
+ printk("tansfer%s: conf=%x, data=%x\n", t->tx_buf ? "TX" : "RX",
+ chconf, t->tx_buf ? *(u8 *)(t->tx_buf) : 0);
mcspi_write_chconf0(spi, chconf);

if (t->len) {
unsigned count;

/* RX_ONLY mode needs dummy data in TX reg */
- if (t->tx_buf == NULL)
+ if (t->tx_buf == NULL) {
+ u8 rx_data;
__raw_writel(0, cs->base
+ OMAP2_MCSPI_TX0);

+ if (mcspi_wait_for_reg_bit(cs->base + OMAP2_MCSPI_CHSTAT0,
+ OMAP2_MCSPI_CHSTAT_RXS) < 0)
+ dev_err(&spi->dev, "RXS timed out\n");
+
+ rx_data = __raw_readl(cs->base + OMAP2_MCSPI_RX0);
+ printk("rx_data = %x\n", rx_data);
+
+ }
if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
count = omap2_mcspi_txrx_dma(spi, t);
else
@@ -971,7 +981,7 @@ static void omap2_mcspi_work(struct work_struct *work)
omap2_mcspi_force_cs(spi, 0);

omap2_mcspi_set_enable(spi, 0);
-
+ printk("*****SPI MESSAGE END*****\n");
m->status = status;
m->complete(m->context);

-- 
1.5.6.5


Test3 result output & patch:
# =====SPI MESSAGE BEGIN=====
tansferTX: conf=1123d4, data=93
tansferRX: conf=1113d4, data=0
rx_data = 77
tansferTX: conf=1123d4, data=93
tansferRX: conf=1113d4, data=0
rx_data = 76
*****SPI MESSAGE END*****
=====SPI MESSAGE BEGIN=====
tansferTX: conf=1123d4, data=93
tansferRX: conf=1113d4, data=0
rx_data = 75
tansferTX: conf=1123d4, data=93
tansferRX: conf=1113d4, data=0
rx_data = 74
*****SPI MESSAGE END*****

Subject: [PATCH] SPI/test3: get rx_data in RX_ONLY transfer after 
trigger writing

At frist revert the commit a330ce2 "omap2_mcspi: Flush posted writes",
then get rx_data in RX_ONLY transfer after trigger writing dummy data
to TX register.

Signed-off-by: Jason Wang <jason77.wang at gmail.com>
---
drivers/spi/omap2_mcspi.c | 19 ++++++++++++++-----
1 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index b3a94ca..5d71cad 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -204,7 +204,6 @@ static inline void mcspi_write_chconf0(const struct 
spi_device *spi, u32 val)

cs->chconf0 = val;
mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
- mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
}

static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
@@ -893,7 +892,7 @@ static void omap2_mcspi_work(struct work_struct *work)
spi = m->spi;
cs = spi->controller_state;
cd = spi->controller_data;
-
+ printk("=====SPI MESSAGE BEGIN=====\n");
omap2_mcspi_set_enable(spi, 1);
list_for_each_entry(t, &m->transfers, transfer_list) {
if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
@@ -928,17 +927,27 @@ static void omap2_mcspi_work(struct work_struct 
*work)
if (t->len > ((cs->word_len + 7) >> 3))
chconf |= OMAP2_MCSPI_CHCONF_TURBO;
}
-
+ printk("tansfer%s: conf=%x, data=%x\n", t->tx_buf ? "TX" : "RX",
+ chconf, t->tx_buf ? *(u8 *)(t->tx_buf) : 0);
mcspi_write_chconf0(spi, chconf);

if (t->len) {
unsigned count;

/* RX_ONLY mode needs dummy data in TX reg */
- if (t->tx_buf == NULL)
+ if (t->tx_buf == NULL) {
+ u8 rx_data;
__raw_writel(0, cs->base
+ OMAP2_MCSPI_TX0);

+ if (mcspi_wait_for_reg_bit(cs->base + OMAP2_MCSPI_CHSTAT0,
+ OMAP2_MCSPI_CHSTAT_RXS) < 0)
+ dev_err(&spi->dev, "RXS timed out\n");
+
+ rx_data = __raw_readl(cs->base + OMAP2_MCSPI_RX0);
+ printk("rx_data = %x\n", rx_data);
+
+ }
if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
count = omap2_mcspi_txrx_dma(spi, t);
else
@@ -971,7 +980,7 @@ static void omap2_mcspi_work(struct work_struct *work)
omap2_mcspi_force_cs(spi, 0);

omap2_mcspi_set_enable(spi, 0);
-
+ printk("*****SPI MESSAGE END*****\n");
m->status = status;
m->complete(m->context);

-- 
1.5.6.5






>> But if we disable this channel after the TX_ONLY  transfer and 
>> reenable 
>> it  before  the RX_ONLY  transfer,
>> the trigger action will take effect and a meaningful data  will be  
>> transfered to RX register.
>>
>> Thanks,
>> Jason.
>>
>>     
>>>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>>>> ---
>>>>  drivers/spi/omap2_mcspi.c |   16 ++++++----------
>>>>  1 files changed, 6 insertions(+), 10 deletions(-)
>>>>
>>>> diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>>>>     
>>>>         
>> [snip]
>>
>>     



From rabin at rab.in  Mon Jun 28 10:22:01 2010
From: rabin at rab.in (Rabin Vincent)
Date: Mon, 28 Jun 2010 19:52:01 +0530
Subject: [PATCH 1/3] ARM: Assume new page cache pages have dirty D-cache
In-Reply-To: <20100625120132.30030.5577.stgit@e102109-lin.cambridge.arm.com>
References: <20100625115826.30030.89790.stgit@e102109-lin.cambridge.arm.com>
	<20100625120132.30030.5577.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100628142201.GA3287@debian>

On Fri, Jun 25, 2010 at 01:01:32PM +0100, Catalin Marinas wrote:
> @@ -508,6 +508,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
>  		outer_inv_range(paddr, paddr + size);
>  
>  	dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
> +
> +	/*
> +	 * Mark the D-cache clean for this page to avoid extra flushing.
> +	 */
> +	if (dir != DMA_TO_DEVICE)
> +		set_bit(PG_dcache_clean, &page->flags);

off + size does not necessarily cover the full page.  We probably
shouldn't be setting it as clean unless it does? 

Also, off + size can cover multiple physically contiguous pages, so
perhaps they too can be set as clean if they're fully covered.

Rabin


From rabin at rab.in  Mon Jun 28 10:47:43 2010
From: rabin at rab.in (Rabin Vincent)
Date: Mon, 28 Jun 2010 20:17:43 +0530
Subject: [PATCH 4/8] ARM: S5PV310: Add IRQ support
In-Reply-To: <1277476037-8806-5-git-send-email-kgene.kim@samsung.com>
References: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
	<1277476037-8806-5-git-send-email-kgene.kim@samsung.com>
Message-ID: <20100628144743.GB3287@debian>

On Fri, Jun 25, 2010 at 11:27:13PM +0900, Kukjin Kim wrote:
> +static DEFINE_SPINLOCK(irq_controller_lock);

Hmm, why is this lock needed?  The uses below don't seem like they need
locking:

> +static void combiner_mask_irq(unsigned int irq)
> +{
> +	u32 mask = 1 << (irq % 32);
> +
> +	spin_lock(&irq_controller_lock);
> +	__raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_CLEAR);
> +	spin_unlock(&irq_controller_lock);
> +}
> +
> +static void combiner_unmask_irq(unsigned int irq)
> +{
> +	u32 mask = 1 << (irq % 32);
> +
> +	spin_lock(&irq_controller_lock);
> +	__raw_writel(mask, combiner_base(irq) + COMBINER_ENABLE_SET);
> +	spin_unlock(&irq_controller_lock);
> +}
> +
> +static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
> +{
...
> +	spin_lock(&irq_controller_lock);
> +	status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
> +	spin_unlock(&irq_controller_lock);



From nico at fluxnic.net  Mon Jun 28 11:08:19 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Mon, 28 Jun 2010 11:08:19 -0400 (EDT)
Subject: kprobe bug.
In-Reply-To: <AAD1C6EB06EE3649B35B7E026785068D14FCBC756F@SC-VEXCH2.marvell.com>
References: <AAD1C6EB06EE3649B35B7E026785068D14FCBC756F@SC-VEXCH2.marvell.com>
Message-ID: <alpine.LFD.2.00.1006281107270.24097@xanadu.home>

On Sun, 27 Jun 2010, Bin Yang wrote:

> Thanks. 
> It looks "emulate_str" had considered PC register situation already. Only " emulate_ldr" has this problem. 
> 
> Here is my new patch, thanks in advance to review it. 
> 
> ===============================
> From 554a86a94836d5f6c89c1253f2c2d85773cbe5eb Mon Sep 17 00:00:00 2001
> From: Bin Yang <bin.yang at marvell.com>
> Date: Mon, 28 Jun 2010 10:40:56 +0800
> Subject: [PATCH] ARM: fix kprobe ldr instr emulate bug
> 
> Signed-off-by: Bin Yang <bin.yang at marvell.com>

Acked-by: Nicolas Pitre <nico at fluxnic.net>

Please send to RMK's p?tch system.


> ---
>  arch/arm/kernel/kprobes-decode.c |    5 +++--
>  1 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c
> index 81b1737..80511d5 100644
> --- a/arch/arm/kernel/kprobes-decode.c
> +++ b/arch/arm/kernel/kprobes-decode.c
> @@ -583,13 +583,14 @@ static void __kprobes emulate_ldr(struct kprobe *p, struct pt_regs *regs)
>  {
>         insn_llret_3arg_fn_t *i_fn = (insn_llret_3arg_fn_t *)&p->ainsn.insn[0];
>         kprobe_opcode_t insn = p->opcode;
> +       long ppc = (long)p->addr + 8;
>         union reg_pair fnr;
>         int rd = (insn >> 12) & 0xf;
>         int rn = (insn >> 16) & 0xf;
>         int rm = insn & 0xf;
>         long rdv;
> -       long rnv  = regs->uregs[rn];
> -       long rmv  = regs->uregs[rm]; /* rm/rmv may be invalid, don't care. */
> +       long rnv = (rn == 15) ? ppc : regs->uregs[rn];
> +       long rmv = (rm == 15) ? ppc : regs->uregs[rm];
>         long cpsr = regs->ARM_cpsr;
> 
> 
> Bin Yang
> 
> -----Original Message-----
> From: Nicolas Pitre [mailto:nico at fluxnic.net] 
> Sent: 2010?6?26? 4:50
> To: Bin Yang
> Cc: Russell King - ARM Linux; Eric Miao; Haojian Zhuang; linux-arm-kernel
> Subject: Re: kprobe bug.
> 
> On Fri, 25 Jun 2010, Bin Yang wrote:
> 
> > Hi Russell,
> > 
> > 	Thanks in advance for your kind to review my question. 
> > 	I met a kprobe bug while I used it to debug my driver. 
> > 	Here is the scenario:
> > 	I add a probe at function xxx(). And the assembly code of xxx() is as following,
> > =====================
> > 	c035ee48 <xxx >:
> > c035ee48:       e59f3008        ldr     r3, [pc, #8]    ; c035ee58              <xxx+0x10>
> > c035ee4c:       e3a02001        mov     r2, #1  ; 0x1
> > c035ee50:       e5032fff        str     r2, [r3, #-4095]
> > c035ee54:       e12fff1e        bx      lr
> > c035ee58:       fe03dfff        .word   0xfe03dfff 
> > =====================
> > 	The ldr emulate always load e12fff1e to r3 register. 
> > 	After debugging, I found the pc register should be 8 after current instruction. So we should set pc to pc+8 before instruction emulation and set it back to the next instruction after singe step.
> > 	Here is my patch: 
> > =======================
> > diff --git a/arch/arm/kernel/kprobes.c b/arch/arm/kernel/kprobes.c
> > index 60c62c3..6e2567e 100644
> > --- a/arch/arm/kernel/kprobes.c
> > +++ b/arch/arm/kernel/kprobes.c
> > @@ -132,8 +132,9 @@ static void __kprobes set_current_kprobe(struct kprobe *p)
> >  static void __kprobes singlestep(struct kprobe *p, struct pt_regs *regs,
> >  				 struct kprobe_ctlblk *kcb)
> >  {
> > -	regs->ARM_pc += 4;
> > +	regs->ARM_pc += 8;
> >  	p->ainsn.insn_handler(p, regs);
> > +	regs->ARM_pc -= 4;
> >  }
> >  
> >  /*
> > ========================
> 
> This is wrong.  You are breaking all the emulated instructions changing 
> the pc value.
> 
> What needs to be done is to add a special case in emulate_ldr() to fixup 
> rnv when rn is 15.  The same fixup would be needed in emulate_str().
> See emulate_alu_rflags() for example.
> 
> 
> Nicolas
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

From rabin at rab.in  Mon Jun 28 11:19:18 2010
From: rabin at rab.in (Rabin Vincent)
Date: Mon, 28 Jun 2010 20:49:18 +0530
Subject: [PATCH 5/8] ARM: S5PV310: Add Timer support
In-Reply-To: <1277476037-8806-6-git-send-email-kgene.kim@samsung.com>
References: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
	<1277476037-8806-6-git-send-email-kgene.kim@samsung.com>
Message-ID: <20100628151918.GC3287@debian>

On Fri, Jun 25, 2010 at 11:27:14PM +0900, Kukjin Kim wrote:
> +static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
> +{
> +	unsigned long tcon;
> +
> +	tcon = __raw_readl(S3C2410_TCON);
> +
> +	/* timers reload after counting zero, so reduce the count by 1 */
> +	tcnt--;
> +
> +	printk(KERN_DEBUG "timer tcon=%08lx, tcnt %08lx\n", tcon, tcnt);

This function is called from set_event().  Do you really want this
printk every time a tick is programmed?

> +static void __init s5pv310_clocksource_init(void)
> +{
> +	unsigned long pclk;
> +	unsigned long clock_rate;
> +
> +	pclk = clk_get_rate(timerclk);
> +
> +	clk_set_rate(tdiv2, pclk / 2);
> +	clk_set_parent(tin2, tdiv2);
> +
> +	clock_rate = clk_get_rate(tin2);
> +
> +	pwm_clocksource.mult =
> +		clocksource_khz2mult(clock_rate/1000, pwm_clocksource.shift);
> +
> +	if (clocksource_register(&pwm_clocksource))
> +		panic("%s: can't register clocksource\n", pwm_clocksource.name);
> +
> +	s5pv310_pwm_init(2, ~0);
> +	s5pv310_pwm_start(2, 1);
> +}
> +

It would probably be prudent to start the clocksource before registering
it, rather than after.


From marek.vasut at gmail.com  Mon Jun 28 11:29:38 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Mon, 28 Jun 2010 17:29:38 +0200
Subject: [PATCH 4/4] pxa/spitz: Rework spitz
In-Reply-To: <AANLkTikdxoqofUUpxB1c9wSlsU-zxc-uSNMmnQX_kE8m@mail.gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>
	<201006281407.50202.marek.vasut@gmail.com>
	<AANLkTikdxoqofUUpxB1c9wSlsU-zxc-uSNMmnQX_kE8m@mail.gmail.com>
Message-ID: <201006281729.38591.marek.vasut@gmail.com>

Dne Po 28. ?ervna 2010 14:19:46 Eric Miao napsal(a):
> On Mon, Jun 28, 2010 at 8:07 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > Dne Po 28. ?ervna 2010 05:43:12 Eric Miao napsal(a):
> >> On Thu, Jun 24, 2010 at 10:02 PM, Marek Vasut <marek.vasut at gmail.com> 
wrote:
> >> > This huge patch mostly shuffles code. The spitz.c file contained
> >> > terrible mess and needed a cleanup, here it is:
> >> > 
> >> > 1) Made every part modular, components are not built in if not
> >> > selected. 2) Removed loads of preprocessor goo, mostly "#ifdef
> >> > MACH_AKITA .... #endif" and similar code. The kernel size will grow
> >> > by a few kb now, but the file is much more readable.
> >> > 3) Reworked SD/CF power setting function and made it reentrant.
> >> > 4) Add ISL6271A regulator support
> >> > 5) Correctly register WM8750
> >> > 
> >> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> >> 
> >> I'd prefer to see separate small patches for this?
> > 
> > This is nearly a replacement for the whole file ... maybe we could merge
> > spitz2.c or something ... or do it this way. I understand your point
> > about spliting it into smaller chunks, but I don't see a reason in this
> > case.
> 
> I guess the above 1, 2, 3, 4, 5 can be well separated into 5 patches,
> I don't mind merge many patches, but I'd really like to see small and
> consistent changes (make it regression test friendly BTW), ;-)

I said I get your point, but I don't see the benefit here.
1) already does most of the rewrite of the file,
2) only removes the #ifdef MACH_PLAT around MACHINE_START (as the rest was done 
in 1) ),
3) is actually a part of 1) as well
4) ok, this could be separated out, but I see no benefit
5) well this is already in if I recall well, but I put it here for completeness

> 
> >> > ---
> >> >  arch/arm/mach-pxa/include/mach/spitz.h |    2 -
> >> >  arch/arm/mach-pxa/spitz.c              |  813
> >> > ++++++++++++++++++-------------- 2 files changed, 470 insertions(+),
> >> > 345 deletions(-)
> >> > 
> >> > diff --git a/arch/arm/mach-pxa/include/mach/spitz.h
> >> > b/arch/arm/mach-pxa/include/mach/spitz.h index fa1998c..685749a 100644
> >> > --- a/arch/arm/mach-pxa/include/mach/spitz.h
> >> > +++ b/arch/arm/mach-pxa/include/mach/spitz.h
> >> > @@ -185,7 +185,5 @@
> >> >  /*
> >> >  * Shared data structures
> >> >  */
> >> > -extern struct platform_device spitzscoop_device;
> >> > -extern struct platform_device spitzscoop2_device;
> >> >  extern struct platform_device spitzssp_device;
> >> >  extern struct sharpsl_charger_machinfo spitz_pm_machinfo;
> >> > diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
> >> > index c1048a3..fa31980 100644
> >> > --- a/arch/arm/mach-pxa/spitz.c
> >> > +++ b/arch/arm/mach-pxa/spitz.c
> >> > @@ -18,14 +18,15 @@
> >> >  #include <linux/gpio_keys.h>
> >> >  #include <linux/gpio.h>
> >> >  #include <linux/leds.h>
> >> > -#include <linux/mtd/physmap.h>
> >> >  #include <linux/i2c.h>
> >> >  #include <linux/i2c/pca953x.h>
> >> >  #include <linux/spi/spi.h>
> >> >  #include <linux/spi/ads7846.h>
> >> >  #include <linux/spi/corgi_lcd.h>
> >> > +#include <linux/mtd/physmap.h>
> >> >  #include <linux/mtd/sharpsl.h>
> >> >  #include <linux/input/matrix_keypad.h>
> >> > +#include <linux/regulator/machine.h>
> >> > 
> >> >  #include <asm/setup.h>
> >> >  #include <asm/mach-types.h>
> >> > @@ -33,11 +34,9 @@
> >> >  #include <asm/mach/sharpsl_param.h>
> >> >  #include <asm/hardware/scoop.h>
> >> > 
> >> > -
> >> >  #include <mach/pxa27x.h>
> >> >  #include <mach/pxa27x-udc.h>
> >> >  #include <mach/reset.h>
> >> > -#include <plat/i2c.h>
> >> >  #include <mach/irda.h>
> >> >  #include <mach/mmc.h>
> >> >  #include <mach/ohci.h>
> >> > @@ -45,11 +44,16 @@
> >> >  #include <mach/pxa2xx_spi.h>
> >> >  #include <mach/spitz.h>
> >> > 
> >> > +#include <plat/i2c.h>
> >> > +
> >> >  #include "generic.h"
> >> >  #include "devices.h"
> >> >  #include "sharpsl.h"
> >> > 
> >> > -static unsigned long spitz_pin_config[] __initdata = {
> >> > +/********************************************************************
> >> > *** ******* + * Pin configuration
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +static unsigned long sharpslc_pin_config[] __initdata = {
> >> > /* Chip Selects */
> >> >        GPIO78_nCS_2,   /* SCOOP #2 */
> >> >        GPIO79_nCS_3,   /* NAND */
> >> > @@ -124,10 +128,13 @@ static unsigned long spitz_pin_config[]
> >> > __initdata = { GPIO1_GPIO | WAKEUP_ON_EDGE_FALL,       /*
> >> > SPITZ_GPIO_RESET */ };
> >> > 
> >> > -/*
> >> > - * Spitz SCOOP Device #1
> >> > - */
> >> > -static struct resource spitz_scoop_resources[] = {
> >> > +
> >> > +/********************************************************************
> >> > *** ******* + * Scoop GPIO expander
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_SHARP_SCOOP) ||
> >> > defined(CONFIG_SHARP_SCOOP_MODULE) +/* SCOOP Device #1 */
> >> > +static struct resource sharpslc_scoop_1_resources[] = {
> >> >        [0] = {
> >> >                .start          = 0x10800000,
> >> >                .end            = 0x10800fff,
> >> > @@ -135,7 +142,7 @@ static struct resource spitz_scoop_resources[] = {
> >> >        },
> >> >  };
> >> > 
> >> > -static struct scoop_config spitz_scoop_setup = {
> >> > +static struct scoop_config sharpslc_scoop_1_setup = {
> >> >        .io_dir         = SPITZ_SCP_IO_DIR,
> >> >        .io_out         = SPITZ_SCP_IO_OUT,
> >> >        .suspend_clr    = SPITZ_SCP_SUS_CLR,
> >> > @@ -143,20 +150,18 @@ static struct scoop_config spitz_scoop_setup = {
> >> >        .gpio_base      = SPITZ_SCP_GPIO_BASE,
> >> >  };
> >> > 
> >> > -struct platform_device spitzscoop_device = {
> >> > +struct platform_device sharpslc_scoop_1_device = {
> >> >        .name           = "sharp-scoop",
> >> >        .id             = 0,
> >> >        .dev            = {
> >> > -               .platform_data  = &spitz_scoop_setup,
> >> > +               .platform_data  = &sharpslc_scoop_1_setup,
> >> >        },
> >> > -       .num_resources  = ARRAY_SIZE(spitz_scoop_resources),
> >> > -       .resource       = spitz_scoop_resources,
> >> > +       .num_resources  = ARRAY_SIZE(sharpslc_scoop_1_resources),
> >> > +       .resource       = sharpslc_scoop_1_resources,
> >> >  };
> >> > 
> >> > -/*
> >> > - * Spitz SCOOP Device #2
> >> > - */
> >> > -static struct resource spitz_scoop2_resources[] = {
> >> > +/* SCOOP Device #2 */
> >> > +static struct resource sharpslc_scoop_2_resources[] = {
> >> >        [0] = {
> >> >                .start          = 0x08800040,
> >> >                .end            = 0x08800fff,
> >> > @@ -164,7 +169,7 @@ static struct resource spitz_scoop2_resources[] =
> >> > { },
> >> >  };
> >> > 
> >> > -static struct scoop_config spitz_scoop2_setup = {
> >> > +static struct scoop_config sharpslc_scoop_2_setup = {
> >> >        .io_dir         = SPITZ_SCP2_IO_DIR,
> >> >        .io_out         = SPITZ_SCP2_IO_OUT,
> >> >        .suspend_clr    = SPITZ_SCP2_SUS_CLR,
> >> > @@ -172,82 +177,110 @@ static struct scoop_config spitz_scoop2_setup =
> >> > { .gpio_base      = SPITZ_SCP2_GPIO_BASE,
> >> >  };
> >> > 
> >> > -struct platform_device spitzscoop2_device = {
> >> > +struct platform_device sharpslc_scoop_2_device = {
> >> >        .name           = "sharp-scoop",
> >> >        .id             = 1,
> >> >        .dev            = {
> >> > -               .platform_data  = &spitz_scoop2_setup,
> >> > +               .platform_data  = &sharpslc_scoop_2_setup,
> >> >        },
> >> > -       .num_resources  = ARRAY_SIZE(spitz_scoop2_resources),
> >> > -       .resource       = spitz_scoop2_resources,
> >> > +       .num_resources  = ARRAY_SIZE(sharpslc_scoop_2_resources),
> >> > +       .resource       = sharpslc_scoop_2_resources,
> >> >  };
> >> > 
> >> > -#define SPITZ_PWR_SD 0x01
> >> > -#define SPITZ_PWR_CF 0x02
> >> > +static void __init sharpslc_scoop_init(void)
> >> > +{
> >> > +       platform_device_register(&sharpslc_scoop_1_device);
> >> > +
> >> > +       /* Akita doesn't have the second SCOOP chip */
> >> > +       if (!machine_is_akita())
> >> > +               platform_device_register(&sharpslc_scoop_2_device);
> >> > +}
> >> > 
> >> >  /* Power control is shared with between one of the CF slots and SD */
> >> > -static void spitz_card_pwr_ctrl(int device, unsigned short new_cpr)
> >> > +static void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t new_cpr)
> >> >  {
> >> > -       unsigned short cpr = read_scoop_reg(&spitzscoop_device.dev,
> >> > SCOOP_CPR); +       unsigned short cpr;
> >> > +       unsigned long flags;
> >> > 
> >> > -       if (new_cpr & 0x0007) {
> >> > +       if (new_cpr & 0x7) {
> >> >                gpio_set_value(SPITZ_GPIO_CF_POWER, 1);
> >> > -               if (!(cpr & 0x0002) && !(cpr & 0x0004))
> >> > -                       mdelay(5);
> >> > -               if (device == SPITZ_PWR_CF)
> >> > -                       cpr |= 0x0002;
> >> > -               if (device == SPITZ_PWR_SD)
> >> > -                       cpr |= 0x0004;
> >> > -               write_scoop_reg(&spitzscoop_device.dev, SCOOP_CPR, cpr
> >> > | new_cpr); -       } else {
> >> > -               if (device == SPITZ_PWR_CF)
> >> > -                       cpr &= ~0x0002;
> >> > -               if (device == SPITZ_PWR_SD)
> >> > -                       cpr &= ~0x0004;
> >> > -               if (!(cpr & 0x0002) && !(cpr & 0x0004)) {
> >> > -                       write_scoop_reg(&spitzscoop_device.dev,
> >> > SCOOP_CPR, 0x0000); -                       mdelay(1);
> >> > -                       gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
> >> > -               } else {
> >> > -                       write_scoop_reg(&spitzscoop_device.dev,
> >> > SCOOP_CPR, cpr | new_cpr); -               }
> >> > +               mdelay(5);
> >> > +       }
> >> > +
> >> > +       local_irq_save(flags);
> >> > +
> >> > +       cpr = read_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR);
> >> > +
> >> > +       if (enable & new_cpr)
> >> > +               cpr |= new_cpr;
> >> > +       else
> >> > +               cpr &= ~enable;
> >> > +
> >> > +       write_scoop_reg(&sharpslc_scoop_1_device.dev, SCOOP_CPR, cpr);
> >> > +
> >> > +       local_irq_restore(flags);
> >> > +
> >> > +       if (!(cpr & 0x7)) {
> >> > +               mdelay(1);
> >> > +               gpio_set_value(SPITZ_GPIO_CF_POWER, 0);
> >> >        }
> >> >  }
> >> > 
> >> > -static void spitz_pcmcia_pwr(struct device *scoop, unsigned short
> >> > cpr, int nr) +#else
> >> > +static inline void sharpslc_scoop_init(void) {}
> >> > +static inline void sharpslc_card_pwr_ctrl(uint8_t enable, uint8_t
> >> > new_cpr) {} +#endif
> >> > +
> >> > +/********************************************************************
> >> > *** ******* + * PCMCIA
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_PCMCIA_PXA2XX) ||
> >> > defined(CONFIG_PCMCIA_PXA2XX_MODULE) +static void
> >> > sharpslc_pcmcia_pwr(struct device *scoop, uint16_t cpr, int nr) {
> >> >        /* Only need to override behaviour for slot 0 */
> >> >        if (nr == 0)
> >> > -               spitz_card_pwr_ctrl(SPITZ_PWR_CF, cpr);
> >> > +               sharpslc_card_pwr_ctrl(
> >> > +                       cpr & (SCOOP_CPR_CF_3V | SCOOP_CPR_CF_XV),
> >> > cpr); else
> >> >                write_scoop_reg(scoop, SCOOP_CPR, cpr);
> >> >  }
> >> > 
> >> > -static struct scoop_pcmcia_dev spitz_pcmcia_scoop[] = {
> >> > -{
> >> > -       .dev        = &spitzscoop_device.dev,
> >> > -       .irq        = SPITZ_IRQ_GPIO_CF_IRQ,
> >> > -       .cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
> >> > -       .cd_irq_str = "PCMCIA0 CD",
> >> > -},{
> >> > -       .dev        = &spitzscoop2_device.dev,
> >> > -       .irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
> >> > -       .cd_irq     = -1,
> >> > -},
> >> > +static struct scoop_pcmcia_dev sharpslc_pcmcia_scoop[] = {
> >> > +       {
> >> > +               .dev        = &sharpslc_scoop_1_device.dev,
> >> > +               .irq        = SPITZ_IRQ_GPIO_CF_IRQ,
> >> > +               .cd_irq     = SPITZ_IRQ_GPIO_CF_CD,
> >> > +               .cd_irq_str = "PCMCIA0 CD",
> >> > +       }, {
> >> > +               .dev        = &sharpslc_scoop_2_device.dev,
> >> > +               .irq        = SPITZ_IRQ_GPIO_CF2_IRQ,
> >> > +               .cd_irq     = -1,
> >> > +       },
> >> >  };
> >> > 
> >> > -static struct scoop_pcmcia_config spitz_pcmcia_config = {
> >> > -       .devs         = &spitz_pcmcia_scoop[0],
> >> > -       .num_devs     = 2,
> >> > -       .power_ctrl   = spitz_pcmcia_pwr,
> >> > +static struct scoop_pcmcia_config sharpslc_pcmcia_config = {
> >> > +       .devs           = &sharpslc_pcmcia_scoop[0],
> >> > +       .num_devs       = 2,
> >> > +       .power_ctrl     = sharpslc_pcmcia_pwr,
> >> >  };
> >> > 
> >> > -EXPORT_SYMBOL(spitzscoop_device);
> >> > -EXPORT_SYMBOL(spitzscoop2_device);
> >> > +static void __init sharpslc_pcmcia_init(void)
> >> > +{
> >> > +       /* Akita has only one PCMCIA slot used */
> >> > +       if (machine_is_akita())
> >> > +               sharpslc_pcmcia_config.num_devs = 1;
> >> > +
> >> > +       platform_scoop_config = &sharpslc_pcmcia_config;
> >> > +}
> >> > +#else
> >> > +static inline void sharpslc_pcmcia_init(void) {}
> >> > +#endif
> >> > +
> >> > +/********************************************************************
> >> > *** ******* + * GPIO keyboard
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_KEYBOARD_MATRIX) ||
> >> > defined(CONFIG_KEYBOARD_MATRIX_MODULE)
> >> > 
> >> > -/*
> >> > - * Spitz Keyboard Device
> >> > - */
> >> >  #define SPITZ_KEY_CALENDAR     KEY_F1
> >> >  #define SPITZ_KEY_ADDRESS      KEY_F2
> >> >  #define SPITZ_KEY_FN           KEY_F3
> >> > @@ -263,7 +296,7 @@ EXPORT_SYMBOL(spitzscoop2_device);
> >> >  #define SPITZ_KEY_OK           KEY_F11
> >> >  #define SPITZ_KEY_MENU         KEY_F12
> >> > 
> >> > -static const uint32_t spitzkbd_keymap[] = {
> >> > +static const uint32_t sharpslc_keymap[] = {
> >> >        KEY(0, 0, KEY_LEFTCTRL),
> >> >        KEY(0, 1, KEY_1),
> >> >        KEY(0, 2, KEY_3),
> >> > @@ -330,37 +363,48 @@ static const uint32_t spitzkbd_keymap[] = {
> >> >        KEY(6, 8, KEY_RIGHT),
> >> >  };
> >> > 
> >> > -static const struct matrix_keymap_data spitzkbd_keymap_data = {
> >> > -       .keymap         = spitzkbd_keymap,
> >> > -       .keymap_size    = ARRAY_SIZE(spitzkbd_keymap),
> >> > +static const struct matrix_keymap_data sharpslc_keymap_data = {
> >> > +       .keymap         = sharpslc_keymap,
> >> > +       .keymap_size    = ARRAY_SIZE(sharpslc_keymap),
> >> >  };
> >> > 
> >> > -static const uint32_t spitzkbd_row_gpios[] =
> >> > +static const uint32_t sharpslc_row_gpios[] =
> >> >                { 12, 17, 91, 34, 36, 38, 39 };
> >> > -static const uint32_t spitzkbd_col_gpios[] =
> >> > +static const uint32_t sharpslc_col_gpios[] =
> >> >                { 88, 23, 24, 25, 26, 27, 52, 103, 107, 108, 114 };
> >> > 
> >> > -static struct matrix_keypad_platform_data spitzkbd_pdata = {
> >> > -       .keymap_data            = &spitzkbd_keymap_data,
> >> > -       .row_gpios              = spitzkbd_row_gpios,
> >> > -       .col_gpios              = spitzkbd_col_gpios,
> >> > -       .num_row_gpios          = ARRAY_SIZE(spitzkbd_row_gpios),
> >> > -       .num_col_gpios          = ARRAY_SIZE(spitzkbd_col_gpios),
> >> > +static struct matrix_keypad_platform_data sharpslc_mkp_pdata = {
> >> > +       .keymap_data            = &sharpslc_keymap_data,
> >> > +       .row_gpios              = sharpslc_row_gpios,
> >> > +       .col_gpios              = sharpslc_col_gpios,
> >> > +       .num_row_gpios          = ARRAY_SIZE(sharpslc_row_gpios),
> >> > +       .num_col_gpios          = ARRAY_SIZE(sharpslc_col_gpios),
> >> >        .col_scan_delay_us      = 10,
> >> >        .debounce_ms            = 10,
> >> >        .wakeup                 = 1,
> >> >  };
> >> > 
> >> > -static struct platform_device spitzkbd_device = {
> >> > +static struct platform_device sharpslc_mkp_device = {
> >> >        .name           = "matrix-keypad",
> >> >        .id             = -1,
> >> >        .dev            = {
> >> > -               .platform_data = &spitzkbd_pdata,
> >> > +               .platform_data  = &sharpslc_mkp_pdata,
> >> >        },
> >> >  };
> >> > 
> >> > +static void __init sharpslc_mkp_init(void)
> >> > +{
> >> > +       platform_device_register(&sharpslc_mkp_device);
> >> > +}
> >> > +#else
> >> > +static inline void sharpslc_mkp_init(void) {}
> >> > +#endif
> >> > 
> >> > -static struct gpio_keys_button spitz_gpio_keys[] = {
> >> > +/********************************************************************
> >> > *** ******* + * GPIO keys
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_KEYBOARD_GPIO) ||
> >> > defined(CONFIG_KEYBOARD_GPIO_MODULE) +static struct gpio_keys_button
> >> > sharpslc_gpio_keys[] = {
> >> >        {
> >> >                .type   = EV_PWR,
> >> >                .code   = KEY_SUSPEND,
> >> > @@ -383,27 +427,35 @@ static struct gpio_keys_button spitz_gpio_keys[]
> >> > = { },
> >> >  };
> >> > 
> >> > -static struct gpio_keys_platform_data spitz_gpio_keys_platform_data =
> >> > { -       .buttons        = spitz_gpio_keys,
> >> > -       .nbuttons       = ARRAY_SIZE(spitz_gpio_keys),
> >> > +static struct gpio_keys_platform_data
> >> > sharpslc_gpio_keys_platform_data = { +       .buttons        =
> >> > sharpslc_gpio_keys,
> >> > +       .nbuttons       = ARRAY_SIZE(sharpslc_gpio_keys),
> >> >  };
> >> > 
> >> > -static struct platform_device spitz_gpio_keys_device = {
> >> > +static struct platform_device sharpslc_gpio_keys_device = {
> >> >        .name   = "gpio-keys",
> >> >        .id     = -1,
> >> >        .dev    = {
> >> > -               .platform_data  = &spitz_gpio_keys_platform_data,
> >> > +               .platform_data  = &sharpslc_gpio_keys_platform_data,
> >> >        },
> >> >  };
> >> > 
> >> > +static void __init sharpslc_keys_init(void)
> >> > +{
> >> > +       platform_device_register(&sharpslc_gpio_keys_device);
> >> > +}
> >> > +#else
> >> > +static inline void sharpslc_keys_init(void) {}
> >> > +#endif
> >> > 
> >> > -/*
> >> > - * Spitz LEDs
> >> > - */
> >> > -static struct gpio_led spitz_gpio_leds[] = {
> >> > +/********************************************************************
> >> > *** ******* + * LEDs
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_LEDS_GPIO) ||
> >> > defined(CONFIG_LEDS_GPIO_MODULE) +static struct gpio_led
> >> > sharpslc_gpio_leds[] = {
> >> >        {
> >> >                .name                   = "spitz:amber:charge",
> >> > -               .default_trigger        = "sharpsl-charge",
> >> > +               .default_trigger        = "sharpslc-charge",
> >> >                .gpio                   = SPITZ_GPIO_LED_ORANGE,
> >> >        },
> >> >        {
> >> > @@ -413,25 +465,32 @@ static struct gpio_led spitz_gpio_leds[] = {
> >> >        },
> >> >  };
> >> > 
> >> > -static struct gpio_led_platform_data spitz_gpio_leds_info = {
> >> > -       .leds           = spitz_gpio_leds,
> >> > -       .num_leds       = ARRAY_SIZE(spitz_gpio_leds),
> >> > +static struct gpio_led_platform_data sharpslc_gpio_leds_info = {
> >> > +       .leds           = sharpslc_gpio_leds,
> >> > +       .num_leds       = ARRAY_SIZE(sharpslc_gpio_leds),
> >> >  };
> >> > 
> >> > -static struct platform_device spitzled_device = {
> >> > +static struct platform_device sharpslc_led_device = {
> >> >        .name           = "leds-gpio",
> >> >        .id             = -1,
> >> >        .dev            = {
> >> > -               .platform_data = &spitz_gpio_leds_info,
> >> > +               .platform_data  = &sharpslc_gpio_leds_info,
> >> >        },
> >> >  };
> >> > 
> >> > -#if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE)
> >> > -static struct pxa2xx_spi_master spitz_spi_info = {
> >> > -       .num_chipselect = 3,
> >> > -};
> >> > +static void __init sharpslc_leds_init(void)
> >> > +{
> >> > +       platform_device_register(&sharpslc_led_device);
> >> > +}
> >> > +#else
> >> > +static inline void sharpslc_leds_init(void) {}
> >> > +#endif
> >> > 
> >> > -static void spitz_wait_for_hsync(void)
> >> > +/********************************************************************
> >> > *** ******* + * SSP Devices
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_SPI_PXA2XX) ||
> >> > defined(CONFIG_SPI_PXA2XX_MODULE) +static void
> >> > sharpslc_ads7846_wait_for_hsync(void)
> >> >  {
> >> >        while (gpio_get_value(SPITZ_GPIO_HSYNC))
> >> >                cpu_relax();
> >> > @@ -440,21 +499,21 @@ static void spitz_wait_for_hsync(void)
> >> >                cpu_relax();
> >> >  }
> >> > 
> >> > -static struct ads7846_platform_data spitz_ads7846_info = {
> >> > +static struct ads7846_platform_data sharpslc_ads7846_info = {
> >> >        .model                  = 7846,
> >> >        .vref_delay_usecs       = 100,
> >> >        .x_plate_ohms           = 419,
> >> >        .y_plate_ohms           = 486,
> >> >        .pressure_max           = 1024,
> >> >        .gpio_pendown           = SPITZ_GPIO_TP_INT,
> >> > -       .wait_for_sync          = spitz_wait_for_hsync,
> >> > +       .wait_for_sync          = sharpslc_ads7846_wait_for_hsync,
> >> >  };
> >> > 
> >> > -static struct pxa2xx_spi_chip spitz_ads7846_chip = {
> >> > +static struct pxa2xx_spi_chip sharpslc_ads7846_chip = {
> >> >        .gpio_cs                = SPITZ_GPIO_ADS7846_CS,
> >> >  };
> >> > 
> >> > -static void spitz_bl_kick_battery(void)
> >> > +static void sharpslc_bl_kick_battery(void)
> >> >  {
> >> >        void (*kick_batt)(void);
> >> > 
> >> > @@ -465,93 +524,109 @@ static void spitz_bl_kick_battery(void)
> >> >        }
> >> >  }
> >> > 
> >> > -static struct corgi_lcd_platform_data spitz_lcdcon_info = {
> >> > +static struct corgi_lcd_platform_data sharpslc_lcdcon_info = {
> >> >        .init_mode              = CORGI_LCD_MODE_VGA,
> >> >        .max_intensity          = 0x2f,
> >> >        .default_intensity      = 0x1f,
> >> >        .limit_mask             = 0x0b,
> >> >        .gpio_backlight_cont    = SPITZ_GPIO_BACKLIGHT_CONT,
> >> >        .gpio_backlight_on      = SPITZ_GPIO_BACKLIGHT_ON,
> >> > -       .kick_battery           = spitz_bl_kick_battery,
> >> > +       .kick_battery           = sharpslc_bl_kick_battery,
> >> >  };
> >> > 
> >> > -static struct pxa2xx_spi_chip spitz_lcdcon_chip = {
> >> > +static struct pxa2xx_spi_chip sharpslc_lcdcon_chip = {
> >> >        .gpio_cs        = SPITZ_GPIO_LCDCON_CS,
> >> >  };
> >> > 
> >> > -static struct pxa2xx_spi_chip spitz_max1111_chip = {
> >> > +static struct pxa2xx_spi_chip sharpslc_max1111_chip = {
> >> >        .gpio_cs        = SPITZ_GPIO_MAX1111_CS,
> >> >  };
> >> > 
> >> > -static struct spi_board_info spitz_spi_devices[] = {
> >> > +static struct spi_board_info sharpslc_spi_devices[] = {
> >> >        {
> >> > -               .modalias       = "ads7846",
> >> > -               .max_speed_hz   = 1200000,
> >> > -               .bus_num        = 2,
> >> > -               .chip_select    = 0,
> >> > -               .platform_data  = &spitz_ads7846_info,
> >> > -               .controller_data= &spitz_ads7846_chip,
> >> > -               .irq            = gpio_to_irq(SPITZ_GPIO_TP_INT),
> >> > +               .modalias               = "ads7846",
> >> > +               .max_speed_hz           = 1200000,
> >> > +               .bus_num                = 2,
> >> > +               .chip_select            = 0,
> >> > +               .platform_data          = &sharpslc_ads7846_info,
> >> > +               .controller_data        = &sharpslc_ads7846_chip,
> >> > +               .irq                    =
> >> > gpio_to_irq(SPITZ_GPIO_TP_INT), }, {
> >> > -               .modalias       = "corgi-lcd",
> >> > -               .max_speed_hz   = 50000,
> >> > -               .bus_num        = 2,
> >> > -               .chip_select    = 1,
> >> > -               .platform_data  = &spitz_lcdcon_info,
> >> > -               .controller_data= &spitz_lcdcon_chip,
> >> > +               .modalias               = "corgi-lcd",
> >> > +               .max_speed_hz           = 50000,
> >> > +               .bus_num                = 2,
> >> > +               .chip_select            = 1,
> >> > +               .platform_data          = &sharpslc_lcdcon_info,
> >> > +               .controller_data        = &sharpslc_lcdcon_chip,
> >> >        }, {
> >> > -               .modalias       = "max1111",
> >> > -               .max_speed_hz   = 450000,
> >> > -               .bus_num        = 2,
> >> > -               .chip_select    = 2,
> >> > -               .controller_data= &spitz_max1111_chip,
> >> > +               .modalias               = "max1111",
> >> > +               .max_speed_hz           = 450000,
> >> > +               .bus_num                = 2,
> >> > +               .chip_select            = 2,
> >> > +               .controller_data        = &sharpslc_max1111_chip,
> >> >        },
> >> >  };
> >> > 
> >> > -static void __init spitz_init_spi(void)
> >> > +static struct pxa2xx_spi_master sharpslc_spi_info = {
> >> > +       .num_chipselect = 3,
> >> > +};
> >> > +
> >> > +static void __init sharpslc_spi_init(void)
> >> >  {
> >> > +       struct corgi_lcd_platform_data *lcd_data =
> >> > &sharpslc_lcdcon_info; +
> >> >        if (machine_is_akita()) {
> >> > -               spitz_lcdcon_info.gpio_backlight_cont =
> >> > AKITA_GPIO_BACKLIGHT_CONT; -
> >> > spitz_lcdcon_info.gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON; +
> >> >       lcd_data->gpio_backlight_cont = AKITA_GPIO_BACKLIGHT_CONT; +
> >> >         lcd_data->gpio_backlight_on = AKITA_GPIO_BACKLIGHT_ON; }
> >> > 
> >> > -       pxa2xx_set_spi_info(2, &spitz_spi_info);
> >> > -       spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices));
> >> > +       pxa2xx_set_spi_info(2, &sharpslc_spi_info);
> >> > +       spi_register_board_info(ARRAY_AND_SIZE(sharpslc_spi_devices));
> >> >  }
> >> >  #else
> >> > -static inline void spitz_init_spi(void) {}
> >> > +static inline void sharpslc_spi_init(void) {}
> >> >  #endif
> >> > 
> >> > +/********************************************************************
> >> > *** ******* + * SD/MMC card controller
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_MMC_PXA) ||
> >> > defined(CONFIG_MMC_PXA_MODULE) /*
> >> > - * MMC/SD Device
> >> > - *
> >> > - * The card detect interrupt isn't debounced so we delay it by 250ms
> >> > - * to give the card a chance to fully insert/eject.
> >> > + * NOTE: The card detect interrupt isn't debounced so we delay it by
> >> > 250ms to + * give the card a chance to fully insert/eject.
> >> >  */
> >> > -static void spitz_mci_setpower(struct device *dev, unsigned int vdd)
> >> > +static void sharpslc_mci_setpower(struct device *dev, unsigned int
> >> > vdd) {
> >> >        struct pxamci_platform_data* p_d = dev->platform_data;
> >> > 
> >> > -       if (( 1 << vdd) & p_d->ocr_mask)
> >> > -               spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0004);
> >> > +       if ((1 << vdd) & p_d->ocr_mask)
> >> > +               sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V,
> >> > SCOOP_CPR_SD_3V); else
> >> > -               spitz_card_pwr_ctrl(SPITZ_PWR_SD, 0x0000);
> >> > +               sharpslc_card_pwr_ctrl(SCOOP_CPR_SD_3V, 0x0);
> >> >  }
> >> > 
> >> > -static struct pxamci_platform_data spitz_mci_platform_data = {
> >> > +static struct pxamci_platform_data sharpslc_mci_platform_data = {
> >> >        .detect_delay_ms        = 250,
> >> >        .ocr_mask               = MMC_VDD_32_33|MMC_VDD_33_34,
> >> > -       .setpower               = spitz_mci_setpower,
> >> > +       .setpower               = sharpslc_mci_setpower,
> >> >        .gpio_card_detect       = SPITZ_GPIO_nSD_DETECT,
> >> >        .gpio_card_ro           = SPITZ_GPIO_nSD_WP,
> >> >        .gpio_power             = -1,
> >> >  };
> >> > 
> >> > +static void __init sharpslc_mmc_init(void)
> >> > +{
> >> > +       pxa_set_mci_info(&sharpslc_mci_platform_data);
> >> > +}
> >> > +#else
> >> > +static inline void sharpslc_mmc_init(void) {}
> >> > +#endif
> >> > 
> >> > -/*
> >> > - * USB Host (OHCI)
> >> > - */
> >> > -static int spitz_ohci_init(struct device *dev)
> >> > +/********************************************************************
> >> > *** ******* + * USB Host
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_USB_OHCI_HCD) ||
> >> > defined(CONFIG_USB_OHCI_HCD_MODULE) +static int
> >> > sharpslc_ohci_init(struct device *dev)
> >> >  {
> >> >        int err;
> >> > 
> >> > @@ -559,88 +634,114 @@ static int spitz_ohci_init(struct device *dev)
> >> >        if (err)
> >> >                return err;
> >> > 
> >> > -       /* Only Port 2 is connected
> >> > -        * Setup USB Port 2 Output Control Register
> >> > -        */
> >> > +       /* Only Port 2 is connected, setup USB Port 2 Output Control
> >> > Register */ UP2OCR = UP2OCR_HXS | UP2OCR_HXOE | UP2OCR_DPPDE |
> >> > UP2OCR_DMPDE;
> >> > 
> >> >        return gpio_direction_output(SPITZ_GPIO_USB_HOST, 1);
> >> >  }
> >> > 
> >> > -static void spitz_ohci_exit(struct device *dev)
> >> > +static void sharpslc_ohci_exit(struct device *dev)
> >> >  {
> >> >        gpio_free(SPITZ_GPIO_USB_HOST);
> >> >  }
> >> > 
> >> > -static struct pxaohci_platform_data spitz_ohci_platform_data = {
> >> > +static struct pxaohci_platform_data sharpslc_ohci_platform_data = {
> >> >        .port_mode      = PMM_NPS_MODE,
> >> > -       .init           = spitz_ohci_init,
> >> > -       .exit           = spitz_ohci_exit,
> >> > +       .init           = sharpslc_ohci_init,
> >> > +       .exit           = sharpslc_ohci_exit,
> >> >        .flags          = ENABLE_PORT_ALL | NO_OC_PROTECTION,
> >> >        .power_budget   = 150,
> >> >  };
> >> > 
> >> > +static void __init sharpslc_uhc_init(void)
> >> > +{
> >> > +       pxa_set_ohci_info(&sharpslc_ohci_platform_data);
> >> > +}
> >> > +#else
> >> > +static inline void sharpslc_uhc_init(void) {}
> >> > +#endif
> >> > 
> >> > -/*
> >> > - * Irda
> >> > - */
> >> > -
> >> > -static struct pxaficp_platform_data spitz_ficp_platform_data = {
> >> > -/* .gpio_pwdown is set in spitz_init() and akita_init() accordingly
> >> > */
> >> > +/*******************************************************************
> >> > **** ******* + * IrDA
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_PXA_FICP) ||
> >> > defined(CONFIG_PXA_FICP_MODULE) +static struct pxaficp_platform_data
> >> > sharpslc_ficp_platform_data = { .transceiver_cap        = IR_SIRMODE
> >> > | IR_OFF,
> >> >  };
> >> > 
> >> > +static void __init sharpslc_irda_init(void)
> >> > +{
> >> > +       if (machine_is_akita())
> >> > +               sharpslc_ficp_platform_data.gpio_pwdown =
> >> > AKITA_GPIO_IR_ON; +       else
> >> > +               sharpslc_ficp_platform_data.gpio_pwdown =
> >> > SPITZ_GPIO_IR_ON;
> >> > 
> >> > -/*
> >> > - * Spitz PXA Framebuffer
> >> > - */
> >> > +       pxa_set_ficp_info(&sharpslc_ficp_platform_data);
> >> > +}
> >> > +#else
> >> > +static inline void sharpslc_irda_init(void) {}
> >> > +#endif
> >> > 
> >> > -static struct pxafb_mode_info spitz_pxafb_modes[] = {
> >> > -{
> >> > -       .pixclock       = 19231,
> >> > -       .xres           = 480,
> >> > -       .yres           = 640,
> >> > -       .bpp            = 16,
> >> > -       .hsync_len      = 40,
> >> > -       .left_margin    = 46,
> >> > -       .right_margin   = 125,
> >> > -       .vsync_len      = 3,
> >> > -       .upper_margin   = 1,
> >> > -       .lower_margin   = 0,
> >> > -       .sync           = 0,
> >> > -},{
> >> > -       .pixclock       = 134617,
> >> > -       .xres           = 240,
> >> > -       .yres           = 320,
> >> > -       .bpp            = 16,
> >> > -       .hsync_len      = 20,
> >> > -       .left_margin    = 20,
> >> > -       .right_margin   = 46,
> >> > -       .vsync_len      = 2,
> >> > -       .upper_margin   = 1,
> >> > -       .lower_margin   = 0,
> >> > -       .sync           = 0,
> >> > -},
> >> > -};
> >> > -
> >> > -static struct pxafb_mach_info spitz_pxafb_info = {
> >> > -       .modes          = &spitz_pxafb_modes[0],
> >> > -       .num_modes      = 2,
> >> > +/********************************************************************
> >> > *** ******* + * Framebuffer
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_FB_PXA) ||
> >> > defined(CONFIG_FB_PXA_MODULE) +static struct pxafb_mode_info
> >> > sharpslc_pxafb_modes[] = {
> >> > +       {
> >> > +               .pixclock       = 19231,
> >> > +               .xres           = 480,
> >> > +               .yres           = 640,
> >> > +               .bpp            = 16,
> >> > +               .hsync_len      = 40,
> >> > +               .left_margin    = 46,
> >> > +               .right_margin   = 125,
> >> > +               .vsync_len      = 3,
> >> > +               .upper_margin   = 1,
> >> > +               .lower_margin   = 0,
> >> > +               .sync           = 0,
> >> > +       }, {
> >> > +               .pixclock       = 134617,
> >> > +               .xres           = 240,
> >> > +               .yres           = 320,
> >> > +               .bpp            = 16,
> >> > +               .hsync_len      = 20,
> >> > +               .left_margin    = 20,
> >> > +               .right_margin   = 46,
> >> > +               .vsync_len      = 2,
> >> > +               .upper_margin   = 1,
> >> > +               .lower_margin   = 0,
> >> > +               .sync           = 0,
> >> > +       },
> >> > +};
> >> > +
> >> > +static struct pxafb_mach_info sharpslc_pxafb_info = {
> >> > +       .modes          = sharpslc_pxafb_modes,
> >> > +       .num_modes      = ARRAY_SIZE(sharpslc_pxafb_modes),
> >> >        .fixed_modes    = 1,
> >> >        .lcd_conn       = LCD_COLOR_TFT_16BPP | LCD_ALTERNATE_MAPPING,
> >> >  };
> >> > 
> >> > -static struct mtd_partition sharpsl_nand_partitions[] = {
> >> > +static void __init sharpslc_lcd_init(void)
> >> > +{
> >> > +       set_pxa_fb_info(&sharpslc_pxafb_info);
> >> > +}
> >> > +#else
> >> > +static inline void sharpslc_lcd_init(void) {}
> >> > +#endif
> >> > +
> >> > +/********************************************************************
> >> > *** ******* + * Framebuffer
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_MTD_NAND_SHARPSL) ||
> >> > defined(CONFIG_MTD_NAND_SHARPSL_MODULE) +static struct mtd_partition
> >> > sharpslc_nand_partitions[] = {
> >> >        {
> >> >                .name = "System Area",
> >> >                .offset = 0,
> >> >                .size = 7 * 1024 * 1024,
> >> > -       },
> >> > -       {
> >> > +       }, {
> >> >                .name = "Root Filesystem",
> >> >                .offset = 7 * 1024 * 1024,
> >> > -       },
> >> > -       {
> >> > +       }, {
> >> >                .name = "Home Filesystem",
> >> >                .offset = MTDPART_OFS_APPEND,
> >> >                .size = MTDPART_SIZ_FULL,
> >> > @@ -649,37 +750,72 @@ static struct mtd_partition
> >> > sharpsl_nand_partitions[] = {
> >> > 
> >> >  static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
> >> > 
> >> > -static struct nand_bbt_descr sharpsl_bbt = {
> >> > -       .options = 0,
> >> > -       .offs = 4,
> >> > -       .len = 2,
> >> > -       .pattern = scan_ff_pattern
> >> > +static struct nand_bbt_descr sharpslc_nand_bbt = {
> >> > +       .options        = 0,
> >> > +       .offs           = 4,
> >> > +       .len            = 2,
> >> > +       .pattern        = scan_ff_pattern
> >> > +};
> >> > +
> >> > +static struct nand_ecclayout sharpslc_akita_oobinfo = {
> >> > +       .oobfree        = { {0x08, 0x09} },
> >> > +       .eccbytes       = 24,
> >> > +       .eccpos         = {
> >> > +                       0x05, 0x01, 0x02, 0x03, 0x06, 0x07, 0x15,
> >> > 0x11, +                       0x12, 0x13, 0x16, 0x17, 0x25, 0x21,
> >> > 0x22, 0x23, +                       0x26, 0x27, 0x35, 0x31, 0x32,
> >> > 0x33, 0x36, 0x37, +       },
> >> >  };
> >> > 
> >> > -static struct sharpsl_nand_platform_data sharpsl_nand_platform_data =
> >> > { -       .badblock_pattern       = &sharpsl_bbt,
> >> > -       .partitions             = sharpsl_nand_partitions,
> >> > -       .nr_partitions          = ARRAY_SIZE(sharpsl_nand_partitions),
> >> > +static struct sharpsl_nand_platform_data sharpslc_nand_pdata = {
> >> > +       .badblock_pattern       = &sharpslc_nand_bbt,
> >> > +       .partitions             = sharpslc_nand_partitions,
> >> > +       .nr_partitions          =
> >> > ARRAY_SIZE(sharpslc_nand_partitions), };
> >> > 
> >> > -static struct resource sharpsl_nand_resources[] = {
> >> > +static struct resource sharpslc_nand_resources[] = {
> >> >        {
> >> > -               .start  = 0x0C000000,
> >> > -               .end    = 0x0C000FFF,
> >> > +               .start  = PXA_CS3_PHYS,
> >> > +               .end    = PXA_CS3_PHYS + SZ_4K - 1,
> >> >                .flags  = IORESOURCE_MEM,
> >> >        },
> >> >  };
> >> > 
> >> > -static struct platform_device sharpsl_nand_device = {
> >> > +static struct platform_device sharpslc_nand_device = {
> >> >        .name           = "sharpsl-nand",
> >> >        .id             = -1,
> >> > -       .resource       = sharpsl_nand_resources,
> >> > -       .num_resources  = ARRAY_SIZE(sharpsl_nand_resources),
> >> > -       .dev.platform_data      = &sharpsl_nand_platform_data,
> >> > +       .resource       = sharpslc_nand_resources,
> >> > +       .num_resources  = ARRAY_SIZE(sharpslc_nand_resources),
> >> > +       .dev            = {
> >> > +               .platform_data  = &sharpslc_nand_pdata,
> >> > +       }
> >> >  };
> >> > 
> >> > +static void __init sharpslc_nand_init(void)
> >> > +{
> >> > +       if (machine_is_spitz()) {
> >> > +               sharpslc_nand_partitions[1].size = 5 * 1024 * 1024;
> >> > +       } else if (machine_is_akita()) {
> >> > +               sharpslc_nand_partitions[1].size = 58 * 1024 * 1024;
> >> > +               sharpslc_nand_bbt.len = 1;
> >> > +               sharpslc_nand_pdata.ecc_layout =
> >> > &sharpslc_akita_oobinfo; +       } else if (machine_is_borzoi()) {
> >> > +               sharpslc_nand_partitions[1].size = 32 * 1024 * 1024;
> >> > +               sharpslc_nand_bbt.len = 1;
> >> > +               sharpslc_nand_pdata.ecc_layout =
> >> > &sharpslc_akita_oobinfo; +       }
> >> > +
> >> > +       platform_device_register(&sharpslc_nand_device);
> >> > +}
> >> > +#else
> >> > +static inline void sharpslc_nand_init(void) {}
> >> > +#endif
> >> > 
> >> > -static struct mtd_partition sharpsl_rom_parts[] = {
> >> > +/********************************************************************
> >> > *** ******* + * NOR Flash
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_MTD_PHYSMAP) ||
> >> > defined(CONFIG_MTD_PHYSMAP_MODULE) +static struct mtd_partition
> >> > sharpslc_rom_parts[] = {
> >> >        {
> >> >                .name   ="Boot PROM Filesystem",
> >> >                .offset = 0x00140000,
> >> > @@ -687,161 +823,152 @@ static struct mtd_partition
> >> > sharpsl_rom_parts[] = { },
> >> >  };
> >> > 
> >> > -static struct physmap_flash_data sharpsl_rom_data = {
> >> > +static struct physmap_flash_data sharpslc_rom_data = {
> >> >        .width          = 2,
> >> > -       .nr_parts       = ARRAY_SIZE(sharpsl_rom_parts),
> >> > -       .parts          = sharpsl_rom_parts,
> >> > +       .nr_parts       = ARRAY_SIZE(sharpslc_rom_parts),
> >> > +       .parts          = sharpslc_rom_parts,
> >> >  };
> >> > 
> >> > -static struct resource sharpsl_rom_resources[] = {
> >> > +static struct resource sharpslc_rom_resources[] = {
> >> >        {
> >> > -               .start  = 0x00000000,
> >> > -               .end    = 0x007fffff,
> >> > +               .start  = PXA_CS0_PHYS,
> >> > +               .end    = PXA_CS0_PHYS + SZ_8M - 1,
> >> >                .flags  = IORESOURCE_MEM,
> >> >        },
> >> >  };
> >> > 
> >> > -static struct platform_device sharpsl_rom_device = {
> >> > -       .name   = "physmap-flash",
> >> > -       .id     = -1,
> >> > -       .resource = sharpsl_rom_resources,
> >> > -       .num_resources = ARRAY_SIZE(sharpsl_rom_resources),
> >> > -       .dev.platform_data = &sharpsl_rom_data,
> >> > -};
> >> > -
> >> > -static struct platform_device *devices[] __initdata = {
> >> > -       &spitzscoop_device,
> >> > -       &spitzkbd_device,
> >> > -       &spitz_gpio_keys_device,
> >> > -       &spitzled_device,
> >> > -       &sharpsl_nand_device,
> >> > -       &sharpsl_rom_device,
> >> > +static struct platform_device sharpslc_rom_device = {
> >> > +       .name           = "physmap-flash",
> >> > +       .id             = -1,
> >> > +       .resource       = sharpslc_rom_resources,
> >> > +       .num_resources  = ARRAY_SIZE(sharpslc_rom_resources),
> >> > +       .dev            = {
> >> > +               .platform_data  = &sharpslc_rom_data,
> >> > +       },
> >> >  };
> >> > 
> >> > -static void spitz_poweroff(void)
> >> > +static void __init sharpslc_nor_init(void)
> >> >  {
> >> > -       arm_machine_restart('g', NULL);
> >> > +       platform_device_register(&sharpslc_rom_device);
> >> >  }
> >> > +#else
> >> > +static inline void sharpslc_nor_init(void) {}
> >> > +#endif
> >> > 
> >> > -static void spitz_restart(char mode, const char *cmd)
> >> > -{
> >> > -       /* Bootloader magic for a reboot */
> >> > -       if((MSC0 & 0xffff0000) == 0x7ff00000)
> >> > -               MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
> >> > -
> >> > -       spitz_poweroff();
> >> > -}
> >> > +/********************************************************************
> >> > *** ******* + * GPIO expander
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +#if defined(CONFIG_I2C_PXA) ||
> >> > defined(CONFIG_I2C_PXA_MODULE) +static struct pca953x_platform_data
> >> > akita_pca953x_pdata = {
> >> > +       .gpio_base              = AKITA_IOEXP_GPIO_BASE,
> >> > +};
> >> > 
> >> > -static void __init common_init(void)
> >> > -{
> >> > -       init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
> >> > -       pm_power_off = spitz_poweroff;
> >> > -       arm_pm_restart = spitz_restart;
> >> > +static struct i2c_board_info sharpslc_i2c_devs[] = {
> >> > +       {
> >> > +               .type           = "wm8750",
> >> > +               .addr           = 0x1b,
> >> > +       }, {
> >> > +               .type           = "max7310",
> >> > +               .addr           = 0x18,
> >> > +               .platform_data  = &akita_pca953x_pdata,
> >> > +       },
> >> > +};
> >> > 
> >> > -       if (machine_is_spitz()) {
> >> > -               sharpsl_nand_partitions[1].size = 5 * 1024 * 1024;
> >> > -       } else if (machine_is_akita()) {
> >> > -               sharpsl_nand_partitions[1].size = 58 * 1024 * 1024;
> >> > -       } else if (machine_is_borzoi()) {
> >> > -               sharpsl_nand_partitions[1].size = 32 * 1024 * 1024;
> >> > +static struct regulator_consumer_supply isl6271a_consumers[] = {
> >> > +       {
> >> > +               .supply = "vcc_core",
> >> >        }
> >> > +};
> >> > 
> >> > -       PMCR = 0x00;
> >> > -
> >> > -       /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */
> >> > -       PCFR |= PCFR_OPDE;
> >> > +static struct regulator_init_data isl6271a_info[] = {
> >> > +       {
> >> > +               .constraints = {
> >> > +                       .name           = "vcc_core range",
> >> > +                       .min_uV         = 850000,
> >> > +                       .max_uV         = 1600000,
> >> > +                       .always_on      = 1,
> >> > +                       .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
> >> > +               },
> >> > +       .consumer_supplies      = isl6271a_consumers,
> >> > +       .num_consumer_supplies  = ARRAY_SIZE(isl6271a_consumers),
> >> > +       }
> >> > +};
> >> > 
> >> > -       pxa2xx_mfp_config(ARRAY_AND_SIZE(spitz_pin_config));
> >> > +static struct i2c_board_info sharpslc_pi2c_devs[] = {
> >> > +       {
> >> > +               .type           = "isl6271a",
> >> > +               .addr           = 0x0c,
> >> > +               .platform_data  = &isl6271a_info,
> >> > +       },
> >> > +};
> >> > 
> >> > -       pxa_set_ffuart_info(NULL);
> >> > -       pxa_set_btuart_info(NULL);
> >> > -       pxa_set_stuart_info(NULL);
> >> > +static void __init sharpslc_i2c_init(void)
> >> > +{
> >> > +       int size = ARRAY_SIZE(sharpslc_i2c_devs);
> >> > 
> >> > -       spitz_init_spi();
> >> > +       /* Only Akita has the max7310 chip */
> >> > +       if (!machine_is_akita())
> >> > +               size--;
> >> > 
> >> > -       platform_add_devices(devices, ARRAY_SIZE(devices));
> >> > -       pxa_set_mci_info(&spitz_mci_platform_data);
> >> > -       pxa_set_ohci_info(&spitz_ohci_platform_data);
> >> > -       pxa_set_ficp_info(&spitz_ficp_platform_data);
> >> > -       set_pxa_fb_info(&spitz_pxafb_info);
> >> >        pxa_set_i2c_info(NULL);
> >> > +       pxa27x_set_i2c_power_info(NULL);
> >> > +       i2c_register_board_info(0, sharpslc_i2c_devs, size);
> >> > +       i2c_register_board_info(1,
> >> > ARRAY_AND_SIZE(sharpslc_pi2c_devs)); }
> >> > -
> >> > -#if defined(CONFIG_MACH_AKITA) || defined(CONFIG_MACH_BORZOI)
> >> > -static struct nand_bbt_descr sharpsl_akita_bbt = {
> >> > -       .options = 0,
> >> > -       .offs = 4,
> >> > -       .len = 1,
> >> > -       .pattern = scan_ff_pattern
> >> > -};
> >> > -
> >> > -static struct nand_ecclayout akita_oobinfo = {
> >> > -       .eccbytes = 24,
> >> > -       .eccpos = {
> >> > -                  0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
> >> > -                  0x12, 0x13, 0x16, 0x17, 0x25, 0x21, 0x22, 0x23,
> >> > -                  0x26, 0x27, 0x35, 0x31, 0x32, 0x33, 0x36, 0x37},
> >> > -       .oobfree = {{0x08, 0x09}}
> >> > -};
> >> > +#else
> >> > +static inline void sharpslc_i2c_init(void) {}
> >> >  #endif
> >> > 
> >> > -#if defined(CONFIG_MACH_SPITZ) || defined(CONFIG_MACH_BORZOI)
> >> > -static void __init spitz_init(void)
> >> > +/********************************************************************
> >> > *** ******* + * Machine init
> >> > +
> >> > **********************************************************************
> >> > ** ******/ +static void sharpslc_poweroff(void)
> >> >  {
> >> > -       spitz_ficp_platform_data.gpio_pwdown = SPITZ_GPIO_IR_ON;
> >> > -
> >> > -#ifdef CONFIG_MACH_BORZOI
> >> > -       if (machine_is_borzoi()) {
> >> > -               sharpsl_nand_platform_data.badblock_pattern =
> >> > &sharpsl_akita_bbt; -
> >> > sharpsl_nand_platform_data.ecc_layout = &akita_oobinfo; -       }
> >> > -#endif
> >> > -
> >> > -       platform_scoop_config = &spitz_pcmcia_config;
> >> > -
> >> > -       common_init();
> >> > -
> >> > -       platform_device_register(&spitzscoop2_device);
> >> > +       arm_machine_restart('g', NULL);
> >> >  }
> >> > -#endif
> >> > 
> >> > -#ifdef CONFIG_MACH_AKITA
> >> > -/*
> >> > - * Akita IO Expander
> >> > - */
> >> > -static struct pca953x_platform_data akita_ioexp = {
> >> > -       .gpio_base              = AKITA_IOEXP_GPIO_BASE,
> >> > -};
> >> > +static void sharpslc_restart(char mode, const char *cmd)
> >> > +{
> >> > +       /* Bootloader magic for a reboot */
> >> > +       if ((MSC0 & 0xffff0000) == 0x7ff00000)
> >> > +               MSC0 = (MSC0 & 0xffff) | 0x7ee00000;
> >> > 
> >> > -static struct i2c_board_info akita_i2c_board_info[] = {
> >> > -       {
> >> > -               .type           = "max7310",
> >> > -               .addr           = 0x18,
> >> > -               .platform_data  = &akita_ioexp,
> >> > -       }, {
> >> > -               .type           = "wm8750",
> >> > -               .addr           = 0x1b,
> >> > -       },
> >> > -};
> >> > +       sharpslc_poweroff();
> >> > +}
> >> > 
> >> > -static void __init akita_init(void)
> >> > +static void __init sharpslc_init(void)
> >> >  {
> >> > -       spitz_ficp_platform_data.gpio_pwdown = AKITA_GPIO_IR_ON;
> >> > +       init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0);
> >> > +       pm_power_off = sharpslc_poweroff;
> >> > +       arm_pm_restart = sharpslc_restart;
> >> > +
> >> > +       PMCR = 0x00;
> >> > 
> >> > -       sharpsl_nand_platform_data.badblock_pattern =
> >> > &sharpsl_akita_bbt; -       sharpsl_nand_platform_data.ecc_layout =
> >> > &akita_oobinfo; +       /* Stop 3.6MHz and drive HIGH to PCMCIA and
> >> > CS */
> >> > +       PCFR |= PCFR_OPDE;
> >> > 
> >> > -       /* We just pretend the second element of the array doesn't
> >> > exist */ -       spitz_pcmcia_config.num_devs = 1;
> >> > -       platform_scoop_config = &spitz_pcmcia_config;
> >> > +       pxa2xx_mfp_config(ARRAY_AND_SIZE(sharpslc_pin_config));
> >> > 
> >> > -       i2c_register_board_info(0,
> >> > ARRAY_AND_SIZE(akita_i2c_board_info)); +      
> >> > pxa_set_ffuart_info(NULL);
> >> > +       pxa_set_btuart_info(NULL);
> >> > +       pxa_set_stuart_info(NULL);
> >> > 
> >> > -       common_init();
> >> > +       sharpslc_spi_init();
> >> > +       sharpslc_scoop_init();
> >> > +       sharpslc_mkp_init();
> >> > +       sharpslc_keys_init();
> >> > +       sharpslc_leds_init();
> >> > +       sharpslc_mmc_init();
> >> > +       sharpslc_pcmcia_init();
> >> > +       sharpslc_irda_init();
> >> > +       sharpslc_uhc_init();
> >> > +       sharpslc_lcd_init();
> >> > +       sharpslc_nor_init();
> >> > +       sharpslc_nand_init();
> >> > +       sharpslc_i2c_init();
> >> >  }
> >> > -#endif
> >> > 
> >> > -static void __init fixup_spitz(struct machine_desc *desc,
> >> > +static void __init sharpslc_fixup(struct machine_desc *desc,
> >> >                struct tag *tags, char **cmdline, struct meminfo *mi)
> >> >  {
> >> >        sharpsl_save_param();
> >> > @@ -855,10 +982,10 @@ static void __init fixup_spitz(struct
> >> > machine_desc *desc, MACHINE_START(SPITZ, "SHARP Spitz")
> >> >        .phys_io        = 0x40000000,
> >> >        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
> >> > -       .fixup          = fixup_spitz,
> >> > +       .fixup          = sharpslc_fixup,
> >> >        .map_io         = pxa_map_io,
> >> >        .init_irq       = pxa27x_init_irq,
> >> > -       .init_machine   = spitz_init,
> >> > +       .init_machine   = sharpslc_init,
> >> >        .timer          = &pxa_timer,
> >> >  MACHINE_END
> >> >  #endif
> >> > @@ -867,10 +994,10 @@ MACHINE_END
> >> >  MACHINE_START(BORZOI, "SHARP Borzoi")
> >> >        .phys_io        = 0x40000000,
> >> >        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
> >> > -       .fixup          = fixup_spitz,
> >> > +       .fixup          = sharpslc_fixup,
> >> >        .map_io         = pxa_map_io,
> >> >        .init_irq       = pxa27x_init_irq,
> >> > -       .init_machine   = spitz_init,
> >> > +       .init_machine   = sharpslc_init,
> >> >        .timer          = &pxa_timer,
> >> >  MACHINE_END
> >> >  #endif
> >> > @@ -879,10 +1006,10 @@ MACHINE_END
> >> >  MACHINE_START(AKITA, "SHARP Akita")
> >> >        .phys_io        = 0x40000000,
> >> >        .io_pg_offst    = (io_p2v(0x40000000) >> 18) & 0xfffc,
> >> > -       .fixup          = fixup_spitz,
> >> > +       .fixup          = sharpslc_fixup,
> >> >        .map_io         = pxa_map_io,
> >> >        .init_irq       = pxa27x_init_irq,
> >> > -       .init_machine   = akita_init,
> >> > +       .init_machine   = sharpslc_init,
> >> >        .timer          = &pxa_timer,
> >> >  MACHINE_END
> >> >  #endif
> >> > --
> >> > 1.7.1


From wim at iguana.be  Mon Jun 28 12:24:30 2010
From: wim at iguana.be (Wim Van Sebroeck)
Date: Mon, 28 Jun 2010 18:24:30 +0200
Subject: [PATCH resend] Watchdog: Adding support for ARM Primecell
	SP805 Watchdog
In-Reply-To: <4C285A72.7030303@st.com>
References: <1275465783-14052-1-git-send-email-viresh.kumar@st.com>
	<4C11B711.70907@st.com> <20100611053049.GM3788@infomag.iguana.be>
	<4C285A72.7030303@st.com>
Message-ID: <20100628162430.GN3788@infomag.iguana.be>

Hi Viresh,

> > Still need to look at it. First finishing up another project.
> > Probably for this weekend.
> > 
> > Kind regards,
> > Wim.
> > 
> 
> Wim,
> 
> Have you reviewed this patch or still need to look at it?

I'm chasing another bug and must admit I almost forgot about this one.
So, yes, I still need to look at this one.

Kind regards,
Wim.



From catalin.marinas at arm.com  Mon Jun 28 12:49:48 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Mon, 28 Jun 2010 17:49:48 +0100
Subject: [PATCH 1/3] ARM: Assume new page cache pages have dirty D-cache
In-Reply-To: <20100628142201.GA3287@debian>
References: <20100625115826.30030.89790.stgit@e102109-lin.cambridge.arm.com>
	<20100625120132.30030.5577.stgit@e102109-lin.cambridge.arm.com>
	<20100628142201.GA3287@debian>
Message-ID: <1277743788.25271.196.camel@e102109-lin.cambridge.arm.com>

On Mon, 2010-06-28 at 15:22 +0100, Rabin Vincent wrote:
> On Fri, Jun 25, 2010 at 01:01:32PM +0100, Catalin Marinas wrote:
> > @@ -508,6 +508,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
> >               outer_inv_range(paddr, paddr + size);
> > 
> >       dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
> > +
> > +     /*
> > +      * Mark the D-cache clean for this page to avoid extra flushing.
> > +      */
> > +     if (dir != DMA_TO_DEVICE)
> > +             set_bit(PG_dcache_clean, &page->flags);
> 
> off + size does not necessarily cover the full page.  We probably
> shouldn't be setting it as clean unless it does?

Good point. See below for an updated patch.

> Also, off + size can cover multiple physically contiguous pages, so
> perhaps they too can be set as clean if they're fully covered.

While it may be possible, I don't think that's common. I would only care
about the "page" argument, otherwise you have to do some conversion to
find the page structure and it may not be worth.


ARM: Assume new page cache pages have dirty D-cache

From: Catalin Marinas <catalin.marinas at arm.com>

There are places in Linux where writes to newly allocated page cache
pages happen without a subsequent call to flush_dcache_page() (several
PIO drivers including USB HCD). This patch changes the meaning of
PG_arch_1 to be PG_dcache_clean and always flush the D-cache for a newly
mapped page in update_mmu_cache().

The patch also sets the PG_arch_1 bit in the DMA cache maintenance
function to avoid additional cache flushing in update_mmu_cache().

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Rabin Vincent <rabin.vincent at stericsson.com>
---
 arch/arm/include/asm/cacheflush.h |    6 +++---
 arch/arm/include/asm/tlbflush.h   |    2 +-
 arch/arm/mm/copypage-v4mc.c       |    2 +-
 arch/arm/mm/copypage-v6.c         |    2 +-
 arch/arm/mm/copypage-xscale.c     |    2 +-
 arch/arm/mm/dma-mapping.c         |    6 ++++++
 arch/arm/mm/fault-armv.c          |    4 ++--
 arch/arm/mm/flush.c               |    3 ++-
 8 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 4656a24..d3730f0 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -137,10 +137,10 @@
 #endif
 
 /*
- * This flag is used to indicate that the page pointed to by a pte
- * is dirty and requires cleaning before returning it to the user.
+ * This flag is used to indicate that the page pointed to by a pte is clean
+ * and does not require cleaning before returning it to the user.
  */
-#define PG_dcache_dirty PG_arch_1
+#define PG_dcache_clean PG_arch_1
 
 /*
  *	MM Cache Management
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index bd863d8..40a7092 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -552,7 +552,7 @@ extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 #endif
 
 /*
- * if PG_dcache_dirty is set for the page, we need to ensure that any
+ * If PG_dcache_clean is not set for the page, we need to ensure that any
  * cache entries for the kernels virtual memory range are written
  * back to the page.
  */
diff --git a/arch/arm/mm/copypage-v4mc.c b/arch/arm/mm/copypage-v4mc.c
index 598c51a..b806151 100644
--- a/arch/arm/mm/copypage-v4mc.c
+++ b/arch/arm/mm/copypage-v4mc.c
@@ -73,7 +73,7 @@ void v4_mc_copy_user_highpage(struct page *to, struct page *from,
 {
 	void *kto = kmap_atomic(to, KM_USER1);
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/copypage-v6.c b/arch/arm/mm/copypage-v6.c
index f55fa10..bdba6c6 100644
--- a/arch/arm/mm/copypage-v6.c
+++ b/arch/arm/mm/copypage-v6.c
@@ -79,7 +79,7 @@ static void v6_copy_user_highpage_aliasing(struct page *to,
 	unsigned int offset = CACHE_COLOUR(vaddr);
 	unsigned long kfrom, kto;
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	/* FIXME: not highmem safe */
diff --git a/arch/arm/mm/copypage-xscale.c b/arch/arm/mm/copypage-xscale.c
index 9920c0a..649bbcd 100644
--- a/arch/arm/mm/copypage-xscale.c
+++ b/arch/arm/mm/copypage-xscale.c
@@ -95,7 +95,7 @@ void xscale_mc_copy_user_highpage(struct page *to, struct page *from,
 {
 	void *kto = kmap_atomic(to, KM_USER1);
 
-	if (test_and_clear_bit(PG_dcache_dirty, &from->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &from->flags))
 		__flush_dcache_page(page_mapping(from), from);
 
 	spin_lock(&minicache_lock);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 9e7742f..fa3d07d 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -508,6 +508,12 @@ void ___dma_page_dev_to_cpu(struct page *page, unsigned long off,
 		outer_inv_range(paddr, paddr + size);
 
 	dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+
+	/*
+	 * Mark the D-cache clean for this page to avoid extra flushing.
+	 */
+	if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE)
+		set_bit(PG_dcache_clean, &page->flags);
 }
 EXPORT_SYMBOL(___dma_page_dev_to_cpu);
 
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 9b906de..58846cb 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -141,7 +141,7 @@ make_coherent(struct address_space *mapping, struct vm_area_struct *vma,
  * a page table, or changing an existing PTE.  Basically, there are two
  * things that we need to take care of:
  *
- *  1. If PG_dcache_dirty is set for the page, we need to ensure
+ *  1. If PG_dcache_clean is not set for the page, we need to ensure
  *     that any cache entries for the kernels virtual memory
  *     range are written back to the page.
  *  2. If we have multiple shared mappings of the same space in
@@ -169,7 +169,7 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
 
 	mapping = page_mapping(page);
 #ifndef CONFIG_SMP
-	if (test_and_clear_bit(PG_dcache_dirty, &page->flags))
+	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
 		__flush_dcache_page(mapping, page);
 #endif
 	if (mapping) {
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index c6844cb..9f9919b 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -248,7 +248,7 @@ void flush_dcache_page(struct page *page)
 
 #ifndef CONFIG_SMP
 	if (!PageHighMem(page) && mapping && !mapping_mapped(mapping))
-		set_bit(PG_dcache_dirty, &page->flags);
+		clear_bit(PG_dcache_clean, &page->flags);
 	else
 #endif
 	{
@@ -257,6 +257,7 @@ void flush_dcache_page(struct page *page)
 			__flush_dcache_aliases(mapping, page);
 		else if (mapping)
 			__flush_icache_all();
+		set_bit(PG_dcache_clean, &page->flags);
 	}
 }
 EXPORT_SYMBOL(flush_dcache_page);




From fabioestevam at yahoo.com  Mon Jun 28 13:47:26 2010
From: fabioestevam at yahoo.com (Fabio Estevam)
Date: Mon, 28 Jun 2010 10:47:26 -0700 (PDT)
Subject: [PATCH] mx31_3ds: Allow selection between host/device modes on
	the OTG port
In-Reply-To: <4C239E81.4040805@gmail.com>
Message-ID: <538995.53508.qm@web51008.mail.re2.yahoo.com>

Hi Magnus,

--- On Thu, 6/24/10, Magnus Lilja <lilja.magnus at gmail.com> wrote:

> From: Magnus Lilja <lilja.magnus at gmail.com>
> Subject: Re: [PATCH] mx31_3ds: Allow selection between host/device modes on the OTG port
> To: "Fabio Estevam" <fabioestevam at yahoo.com>
> Cc: linux-arm-kernel at lists.infradead.org, s.hauer at pengutronix.de, maramaopercheseimorto at gmail.com
> Date: Thursday, June 24, 2010, 3:05 PM
> Hi Fabio,
> 
> On 2010-06-23 22:52, Fabio Estevam wrote:
> > Allow selection between host/device modes on the OTG
> port.
> > 
> > Selection is made via kernel command line option:
> > 
> > 'otg_mode=host' or 'otg_mode=device'. Default mode is
> device.
> 
> 
> Would it be possible to select between host and device
> during run-time, e.g. when the USB modules are loaded? I'm
> asking out of curiosity, I don't know if Linux supports this
> at all.

Not sure if would be possible to make the selection in run-time. 

I will let others comment.

Sascha,

I will resend this patch based on the current imx-for-2.6.26 branch.

Regards,

Fabio Estevam


      


From troy.kisky at boundarydevices.com  Mon Jun 28 15:11:13 2010
From: troy.kisky at boundarydevices.com (Troy Kisky)
Date: Mon, 28 Jun 2010 12:11:13 -0700
Subject: [PATCH] ASoC: DaVinci: Added support for cpu clocking I2S
In-Reply-To: <1277707487-3371-1-git-send-email-lamiaposta71@gmail.com>
References: <1277707487-3371-1-git-send-email-lamiaposta71@gmail.com>
Message-ID: <4C28F3D1.5060806@boundarydevices.com>

Raffaele Recalcati wrote:
> +		if (dev->i2s_fast_clock) {
> +			clk_div = 256;
can you have
   f = (freq / params->rate_num) * params->rate_den;
> +			do {
> +				framesize = (freq / (--clk_div)) /
> +					    params->rate_num *
> +					    params->rate_den;
and
				framesize = f / (--clk_div);
> +			} while (((framesize < 33) || (framesize > 4095)) &&
> +				 (clk_div));
> +			clk_div--;
looks like clk_div can go negative here, should the above while say (clk_div > 1)
> +			srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
> +		} else {
> +			/* symmetric waveforms */
> +			clk_div = freq / (mcbsp_word_length * 16) /
> +				  params->rate_num * params->rate_den;
> +			srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
> +							16 - 1);
> +		}
> +		clk_div &= 0xFF;
> +		srgr |= clk_div;


From xiachendong at hotmail.com  Mon Jun 28 16:39:07 2010
From: xiachendong at hotmail.com (Xiachen Dong)
Date: Mon, 28 Jun 2010 16:39:07 -0400
Subject: Flash write endurance (write cycle) test for AT91RM9200 boards
Message-ID: <BAY134-W19D664FC2A596F0209D21FBDCA0@phx.gbl>


Hi,

We use AT91RM9200 MCU and made our own motherboard for it. We wish to know how many write cycles the flash (MicroSD and DataFlash) may survive under both OS and non-OS situation. We also wish to know the behavior of the flash when the flash becomes dead.

After doing some searching on the web, we found the following information helpful:

1) Write Endurance in Flash Drives: Measurements and Analysis
http://www.ccs.neu.edu/home/pjd/papers/fast10-flash.pdf

2) NAND Testing
http://wiki.laptop.org/go/NAND_Testing

3) How Long Does a Flash Drive Last?
http://www.bress.net/blog/archives/114-How-Long-Does-a-Flash-Drive-Last.html

What we plan to do is to test the flash both under u-boot (raw, without JFFS2) and Linux OS (with ext2 fs). The test will be done with flash empty and flash full. We will also do the test under different room temperatures.

We searched the archive of the list. It looks like no posts mentioned such tests. We wonder anyone on the list has done similar test before and are there any special attention need to pay while doing such tests. Are there any professional software (either open source or commercial) for such tests? Any suggestions and comments are welcomed.

Thanks,

Xiachen

 		 	   		  
_________________________________________________________________
Turn down-time into play-time with Messenger games
http://go.microsoft.com/?linkid=9734385

From khilman at deeprootsystems.com  Mon Jun 28 17:49:23 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 28 Jun 2010 14:49:23 -0700
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <AANLkTimB0_OfLDvtkwwTE-kVeZrardIxVIsD5IEia-vL@mail.gmail.com>
	(Grant Likely's message of "Fri, 25 Jun 2010 17:04:13 -0600")
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>
	<874ogrng3j.fsf@deeprootsystems.com>
	<AANLkTimMnJvOJrRHDiE6PH1BXpRz2-6pY1M9nKHw7vpn@mail.gmail.com>
	<876316eno5.fsf@deeprootsystems.com>
	<AANLkTimB0_OfLDvtkwwTE-kVeZrardIxVIsD5IEia-vL@mail.gmail.com>
Message-ID: <87d3vaygik.fsf@deeprootsystems.com>

Grant Likely <grant.likely at secretlab.ca> writes:

> On Fri, Jun 25, 2010 at 4:46 PM, Kevin Hilman
> <khilman at deeprootsystems.com> wrote:
>> Grant Likely <grant.likely at secretlab.ca> writes:
>>
>>> Another way to look at the problem is that these runtime
>>> customizations are kind of a property of the parent device (the bus,
>>> not the bus_type). ?Would it make sense for parent devices to have
>>> runtime ops to perform for each child that is suspended/resumed? ?That
>>> would make it simple to register another device that implements the
>>> bus behaviour and attach it at runtime instead of compile time.
>>
>> Maybe I didn't fully understand your idea, but the problem here is
>> devices do not have dev_pm_ops. ?Only busses, classes, and types have
>> dev_pm_ops.
>
> Sorry, I mistyped.  What I meant was for the parent device's
> device_driver to be able to have a set of child dev_pm_ops; but I'm
> wading into territory (power management) I'm not particularly familiar
> with, and that might be making things far too complex.

I see your point now, but I think this indeed might complicate things
too much.  

Also, I'm not crazy about how this would delay the per-device PM hooks
to be essentially batched until all devices under the parent are
"ready."

But anyways, it just needs some more research on my part.
Unfortunately, I'll be away from this work on vacation for most of July,
so this won't get any attention from me until August.

>> Though I'm horribly unfamiliar with the intended usage of 'struct
>> device_type', an interesing discovery is that dev->type also has
>> dev_pm_ops, and it takes precedence over the bus type in the
>> suspend/resume. ?IOW, when suspending, when deciding which dev_pm_ops to
>> use, it checks class, type, then bus in that order.
>
> So I guess my suggestion above boils down to somehow inserting
> "parent" between type and bus in that list.
>
>> I need to explore this 'type' feature a little more, but using that or
>> the 'class' might be another way to have custom PM ops for certain
>> platform_devices.
>
> Should maybe start cc'ing Greg and linux-kernel/linux-pm in this discussion.

They were involved in the early discussions about overriding the
platform_bus dev_pm_ops methods, which led us to the current
implementation.

But as I explore the custom bus approach a bit more (in August) I'll
broaden the audience.

Thanks again for all your helpful suggestions,

Kevin


From PeterHuewe at gmx.de  Mon Jun 28 18:05:20 2010
From: PeterHuewe at gmx.de (Peter =?iso-8859-1?q?H=FCwe?=)
Date: Tue, 29 Jun 2010 00:05:20 +0200
Subject: Subject: [PATCH] arm: fix KConfig warning for mach-mx25
Message-ID: <201006290005.20875.PeterHuewe@gmx.de>

From: Peter Huewe <peterhuewe at gmx.de

This patch fixes a KConfig warning:
"arch/arm/mach-mx25/Kconfig:18:warning: choice value used outside its
choice group"

Signed-off-by: Peter Huewe <peterhuewe at gmx.de>
---
KernelVersion: linux-next-20100628
 arch/arm/mach-mx25/Kconfig |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
index 3a6668e..2f436ed 100644
--- a/arch/arm/mach-mx25/Kconfig
+++ b/arch/arm/mach-mx25/Kconfig
@@ -15,8 +15,7 @@ choice
 	default MACH_EUKREA_MBIMXSD_BASEBOARD
 
 config MACH_EUKREA_MBIMXSD_BASEBOARD
-	prompt "Eukrea MBIMXSD development board"
-	bool
+	bool "Eukrea MBIMXSD development board"
 	help
 	  This adds board specific devices that can be found on Eukrea's
 	  MBIMXSD evaluation board.
-- 
1.7.1



From grant.likely at secretlab.ca  Mon Jun 28 18:14:10 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 28 Jun 2010 15:14:10 -0700
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <87d3vaygik.fsf@deeprootsystems.com>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com> 
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com> 
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com> 
	<874ogrng3j.fsf@deeprootsystems.com>
	<AANLkTimMnJvOJrRHDiE6PH1BXpRz2-6pY1M9nKHw7vpn@mail.gmail.com> 
	<876316eno5.fsf@deeprootsystems.com>
	<AANLkTimB0_OfLDvtkwwTE-kVeZrardIxVIsD5IEia-vL@mail.gmail.com> 
	<87d3vaygik.fsf@deeprootsystems.com>
Message-ID: <AANLkTinfGMZADGx7aFQkAoQ_FmgyUMYm-VNjPosWdUhH@mail.gmail.com>

On Mon, Jun 28, 2010 at 2:49 PM, Kevin Hilman
<khilman at deeprootsystems.com> wrote:
> Grant Likely <grant.likely at secretlab.ca> writes:
>
>> On Fri, Jun 25, 2010 at 4:46 PM, Kevin Hilman
>> <khilman at deeprootsystems.com> wrote:
>>> Grant Likely <grant.likely at secretlab.ca> writes:
>>>
>>>> Another way to look at the problem is that these runtime
>>>> customizations are kind of a property of the parent device (the bus,
>>>> not the bus_type). ?Would it make sense for parent devices to have
>>>> runtime ops to perform for each child that is suspended/resumed? ?That
>>>> would make it simple to register another device that implements the
>>>> bus behaviour and attach it at runtime instead of compile time.
>>>
>>> Maybe I didn't fully understand your idea, but the problem here is
>>> devices do not have dev_pm_ops. ?Only busses, classes, and types have
>>> dev_pm_ops.
>>
>> Sorry, I mistyped. ?What I meant was for the parent device's
>> device_driver to be able to have a set of child dev_pm_ops; but I'm
>> wading into territory (power management) I'm not particularly familiar
>> with, and that might be making things far too complex.
>
> I see your point now, but I think this indeed might complicate things
> too much.
>
> Also, I'm not crazy about how this would delay the per-device PM hooks
> to be essentially batched until all devices under the parent are
> "ready."

No, delaying until all children are ready wasn't my intent.  I was
thinking about a set of childs_dev_pm_ops() that would be called once
for each child as each child suspends/resumes...  but probably a moot
point since we both agree that it adds a lot of complexity.  :-)

>
> But anyways, it just needs some more research on my part.
> Unfortunately, I'll be away from this work on vacation for most of July,
> so this won't get any attention from me until August.
>
>>> Though I'm horribly unfamiliar with the intended usage of 'struct
>>> device_type', an interesing discovery is that dev->type also has
>>> dev_pm_ops, and it takes precedence over the bus type in the
>>> suspend/resume. ?IOW, when suspending, when deciding which dev_pm_ops to
>>> use, it checks class, type, then bus in that order.
>>
>> So I guess my suggestion above boils down to somehow inserting
>> "parent" between type and bus in that list.
>>
>>> I need to explore this 'type' feature a little more, but using that or
>>> the 'class' might be another way to have custom PM ops for certain
>>> platform_devices.
>>
>> Should maybe start cc'ing Greg and linux-kernel/linux-pm in this discussion.
>
> They were involved in the early discussions about overriding the
> platform_bus dev_pm_ops methods, which led us to the current
> implementation.
>
> But as I explore the custom bus approach a bit more (in August) I'll
> broaden the audience.
>
> Thanks again for all your helpful suggestions,

np.  Talk you you later.  Have a great vacation.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From khilman at deeprootsystems.com  Mon Jun 28 19:27:23 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Mon, 28 Jun 2010 16:27:23 -0700
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com>
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com>
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com>
	<874ogrng3j.fsf@deeprootsystems.com>
	<AANLkTimMnJvOJrRHDiE6PH1BXpRz2-6pY1M9nKHw7vpn@mail.gmail.com>
Message-ID: <87fx06viuc.fsf@deeprootsystems.com>

Grant Likely <grant.likely at secretlab.ca> writes:

[...]

>
>> This affects many aspects of all drivers, from register and probe (for
>> early devices/drivers too!) to all the plaform_get_resource() usage, all
>> of which assumes a platform_driver and platform_device. ?I didn't look
>> closely, but I didn't see if (or how) OF was handling early devices.
>
> You don't have to reimplement the entire platform bus.  You could
> simply create a new bus type, but reuse all the existing platform bus
> code.  All that changes is the bus type that the device and the driver
> gets registered on.  Then you could easily replace only the functions
> that matter.  (do a git grep platform_bus_type to see how few
> references there actually are.  It looks like there are only 5
> references to it in drivers/base/platform.c that you'd need to work
> around; in platform_device_add(), platform_driver_register(), 2 in
> platform_driver_probe(), and the register in platform_bus_init().  You
> may not even need to reimplement platform_driver_probe().
>
> It might even be as simple as doing this:
> -        pdev->dev.bus = &platform_bus_type;
> +       if (!pdev->dev.bus)
> +                pdev->dev.bus = &platform_bus_type;
>
> So that a different bus type can be selected at device registration
> time 

just FYI...

as a quick proof of concept, I've done a quick hack just to prove to
myself that I could use platform_devices on a custom bus, and it indeed
works.  The small patch below[1] shows the changes required to the
platform code.

Next step was to hack up minimal custom bus code.  The quickest (and
dirtiest) way was to simply memcpy platform_bus_type into my new
omap_bus_type and then override the few dev_pm_ops functions I needed[2].

So, with these in place, and using the dev_pm_ops functions from
$SUBJECT patch, I was able register a platform_device and
platform_driver onto my custom bus and see my custom dev_pm_ops
functions being used as expected.

While admittedly a bit hacky, at least this paves the way in my head
that this is indeed do-able, and I can take my vacation in peace without
this particular problem haunting me (too much.)

Kevin

[1]
diff --git a/drivers/base/platform.c b/drivers/base/platform.c
index 4d99c8b..2cf55e2 100644
--- a/drivers/base/platform.c
+++ b/drivers/base/platform.c
@@ -241,7 +241,8 @@ int platform_device_add(struct platform_device *pdev)
 	if (!pdev->dev.parent)
 		pdev->dev.parent = &platform_bus;
 
-	pdev->dev.bus = &platform_bus_type;
+	if (!pdev->dev.bus)
+		pdev->dev.bus = &platform_bus_type;
 
 	if (pdev->id != -1)
 		dev_set_name(&pdev->dev, "%s.%d", pdev->name,  pdev->id);
@@ -482,7 +483,8 @@ static void platform_drv_shutdown(struct device *_dev)
  */
 int platform_driver_register(struct platform_driver *drv)
 {
-	drv->driver.bus = &platform_bus_type;
+	if (!drv->driver.bus)
+		drv->driver.bus = &platform_bus_type;
 	if (drv->probe)
 		drv->driver.probe = platform_drv_probe;
 	if (drv->remove)
@@ -539,12 +541,12 @@ int __init_or_module platform_driver_probe(struct platform_driver *drv,
 	 * if the probe was successful, and make sure any forced probes of
 	 * new devices fail.
 	 */
-	spin_lock(&platform_bus_type.p->klist_drivers.k_lock);
+	spin_lock(&drv->driver.bus->p->klist_drivers.k_lock);
 	drv->probe = NULL;
 	if (code == 0 && list_empty(&drv->driver.p->klist_devices.k_list))
 		retval = -ENODEV;
 	drv->driver.probe = platform_drv_probe_fail;
-	spin_unlock(&platform_bus_type.p->klist_drivers.k_lock);
+	spin_unlock(&drv->driver.bus->p->klist_drivers.k_lock);
 
 	if (code != retval)
 		platform_driver_unregister(drv);


[2] 
struct bus_type omap_bus_type;
EXPORT_SYMBOL_GPL(omap_bus_type);

static int __init omap_bus_init(void)
{
	int error;
	struct bus_type *bus = &omap_bus_type;

	pr_debug("%s\n", __func__);

	/*
	 * We're just a copy of platform_bus_type with special dev_pm_ops.
	 */
	memcpy(bus, &platform_bus_type, sizeof(struct bus_type));
	bus->name = "omap";
	bus->pm->suspend_noirq = omap_pm_suspend_noirq,
	bus->pm->resume_noirq = omap_pm_resume_noirq,
	bus->pm->runtime_suspend = omap_pm_runtime_suspend,
	bus->pm->runtime_resume = omap_pm_runtime_resume,
	bus->pm->runtime_idle = omap_pm_runtime_idle,

	error = device_register(&omap_bus);
	if (error)
		return error;
	error =  bus_register(&omap_bus_type);
	if (error)
		device_unregister(&omap_bus);

	return error;
}
arch_initcall(omap_bus_init);


From grant.likely at secretlab.ca  Mon Jun 28 19:47:49 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Mon, 28 Jun 2010 16:47:49 -0700
Subject: [PATCH v2 1/3] OMAP: PM: initial runtime PM core support
In-Reply-To: <87fx06viuc.fsf@deeprootsystems.com>
References: <1277422991-25350-1-git-send-email-khilman@deeprootsystems.com> 
	<1277422991-25350-2-git-send-email-khilman@deeprootsystems.com> 
	<AANLkTim4p54brsmph6oaKfoEZwO1GOGfgRNV9vJykOjl@mail.gmail.com> 
	<874ogrng3j.fsf@deeprootsystems.com>
	<AANLkTimMnJvOJrRHDiE6PH1BXpRz2-6pY1M9nKHw7vpn@mail.gmail.com> 
	<87fx06viuc.fsf@deeprootsystems.com>
Message-ID: <AANLkTimgPdrhpDKxd9YhficNddzLEbw_hxkM6_6rh4Wg@mail.gmail.com>

On Mon, Jun 28, 2010 at 4:27 PM, Kevin Hilman
<khilman at deeprootsystems.com> wrote:
> Grant Likely <grant.likely at secretlab.ca> writes:
>
> [...]
>
>>
>>> This affects many aspects of all drivers, from register and probe (for
>>> early devices/drivers too!) to all the plaform_get_resource() usage, all
>>> of which assumes a platform_driver and platform_device. ?I didn't look
>>> closely, but I didn't see if (or how) OF was handling early devices.
>>
>> You don't have to reimplement the entire platform bus. ?You could
>> simply create a new bus type, but reuse all the existing platform bus
>> code. ?All that changes is the bus type that the device and the driver
>> gets registered on. ?Then you could easily replace only the functions
>> that matter. ?(do a git grep platform_bus_type to see how few
>> references there actually are. ?It looks like there are only 5
>> references to it in drivers/base/platform.c that you'd need to work
>> around; in platform_device_add(), platform_driver_register(), 2 in
>> platform_driver_probe(), and the register in platform_bus_init(). ?You
>> may not even need to reimplement platform_driver_probe().
>>
>> It might even be as simple as doing this:
>> - ? ? ? ?pdev->dev.bus = &platform_bus_type;
>> + ? ? ? if (!pdev->dev.bus)
>> + ? ? ? ? ? ? ? ?pdev->dev.bus = &platform_bus_type;
>>
>> So that a different bus type can be selected at device registration
>> time
>
> just FYI...
>
> as a quick proof of concept, I've done a quick hack just to prove to
> myself that I could use platform_devices on a custom bus, and it indeed
> works. ?The small patch below[1] shows the changes required to the
> platform code.
>
> Next step was to hack up minimal custom bus code. ?The quickest (and
> dirtiest) way was to simply memcpy platform_bus_type into my new
> omap_bus_type and then override the few dev_pm_ops functions I needed[2].
>
> So, with these in place, and using the dev_pm_ops functions from
> $SUBJECT patch, I was able register a platform_device and
> platform_driver onto my custom bus and see my custom dev_pm_ops
> functions being used as expected.

Nice!

> While admittedly a bit hacky, at least this paves the way in my head
> that this is indeed do-able, and I can take my vacation in peace without
> this particular problem haunting me (too much.)

indeed.  It could be less hacky also by adding a
platform_bus_type_init() function to the common platform code.

Cheers,
g.


From linus.ml.walleij at gmail.com  Mon Jun 28 20:42:16 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Tue, 29 Jun 2010 02:42:16 +0200
Subject: PB1176 broken in 2.6.35-rc1, bisected
In-Reply-To: <1275581709.8775.14.camel@e102109-lin.cambridge.arm.com>
References: <AANLkTikoCy2FH_5ICh-iiI_wzGj6D6oszyM-zCXkNC_4@mail.gmail.com>
	<1275518783.27834.2.camel@e102109-lin.cambridge.arm.com>
	<AANLkTimJkaadEM1xvG30WVvEjJPZQXHwx216SeqWFKNp@mail.gmail.com>
	<1275581709.8775.14.camel@e102109-lin.cambridge.arm.com>
Message-ID: <AANLkTilcyi6Tjwvz1eU211Q41RcwQAwYAAkoQwhDe-Vj@mail.gmail.com>

2010/6/3 Catalin Marinas <catalin.marinas at arm.com>:
> On Thu, 2010-06-03 at 09:48 +0100, Linus Walleij wrote:
>> 2010/6/3 Catalin Marinas <catalin.marinas at arm.com>:
>> > On Wed, 2010-06-02 at 23:33 +0100, Linus Walleij wrote:
>> >> my PB1176 doesn't boot properly in 2.6.35-rc1, it goes to this point
>> >> and hangs:
>> >>
>> >> (...)
>> >> Switching to clocksource timer3
>> >> NET: Registered protocol family 2
>> >> IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
>> >> TCP established hash table entries: 4096 (order: 3, 32768 bytes)
>> >> TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
>> >> TCP: Hash tables configured (established 4096 bind 4096)
>> >> TCP reno registered
>> >> UDP hash table entries: 256 (order: 0, 4096 bytes)
>> >> UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
>> >> NET: Registered protocol family 1
>> >> RPC: Registered udp transport module.
>> >> RPC: Registered tcp transport module.
>> >> RPC: Registered tcp NFSv4.1 backchannel transport module.
>> >
>> > Have you tried disabling CONFIG_CACHE_L2X0?
>>
>> Hey it works! :-)
>>
>> I suppose your latest patches will hopefully ?get the defconfig with
>> l2x0 working again in -rc2 if they're merged?
>
> I think there is an L2 erratum (and trying to get the right workaround).
> It may be triggered by commit e7c5650f6.
>
> I'll get back on the list with a patch.

Have I missed this? My 2.6.35's and -next trees still require me to
disable the L2X0 cache on the PB1176 for it to boot.

It's a bit sad if we have a 2.6.35 which cannot even boot on this
card...

Can you send me a copy of the errata so I can look at it if
you're swamped with other stuff?

Yours,
Linus Walleij


From baruch at tkos.co.il  Tue Jun 29 02:04:52 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Tue, 29 Jun 2010 06:04:52 +0000 (UTC)
Subject: [PATCH 27/61] ARM: imx: new Kconfig symbol and feature test macro
	=?utf-8?b?Zm9yCURNQQ==?= on mx1 and mx2
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
	<1277387397-3467-28-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <loom.20100629T075846-421@post.gmane.org>

Hi Uwe,

Uwe Kleine-K?nig <u.kleine-koenig <at> pengutronix.de> writes:
> This should be used instead of hard coding the corresponding platforms.
> The feature test macro is needed to support different SOCs in a single
> kernel image.  While at it rename dma-mx1-mx2 to dma-v1 as mx25 doesn't
> use it and so the mx2 part is wrong and move the header to
> arch/arm/mach-imx.
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig <at> pengutronix.de>

This commit breaks build of the (hopefully) soon to-be-merged mx2_camera driver.
This driver is for both mx25 and mx27. Since dma-mx1-mx2.h is now under the
non-mx25 mach-imx/ directory, mx25 build can't find this header.

The solution is either:

1. move mx25 to mach-imx/ as well, or

2. postpone the dma-mx1-mx2.h header move for now, and leave it under plat-mxc/

Any thoughts?

baruch



From harishpresent at gmail.com  Tue Jun 29 02:21:34 2010
From: harishpresent at gmail.com (Harishkumar V)
Date: Tue, 29 Jun 2010 11:51:34 +0530
Subject: soft lockup - CPU#0 stuck for 61s! problem
In-Reply-To: <20100628102931.GA30050@n2100.arm.linux.org.uk>
References: <AANLkTimqNv37LkJDyKJp9PnJapXH4naINhx-T2ysQi4D@mail.gmail.com>
	<20100628090036.GA28510@n2100.arm.linux.org.uk>
	<AANLkTin_iY-7nUwtf1q7Fz4qdnkA0BUktEC6WwCiQdOX@mail.gmail.com>
	<20100628102931.GA30050@n2100.arm.linux.org.uk>
Message-ID: <AANLkTin-cXOIkMN9JXdPETP_aEjeCjF9qV2hIytc5xjU@mail.gmail.com>

Russell,

I am attaching the captured log of cpu lockup with the full trace of
information.

Thanks and Regards,
HarishKumar.V

On Mon, Jun 28, 2010 at 3:59 PM, Russell King - ARM Linux <
linux at arm.linux.org.uk> wrote:

> On Mon, Jun 28, 2010 at 03:50:24PM +0530, Harishkumar V wrote:
> > Will capture the further messages and mail u. Why an IRQ got struck, is
> > their a way to handle this....
>
> Normally, the kernel will disable the interrupt so the system can
> continue to (mostly) function.
>
> However, people like to return IRQ_HANDLED from interrupt handlers,
> even when they've found nothing to do.  This prevents the kernel from
> rescuing you from the stuck-IRQ problem.  Interrupt handlers are
> supposed to return IRQ_HANDLED if they did something to handle the IRQ,
> or IRQ_NONE if they found nothing to do.
>
> I can't say much more than that - I've no idea what hardware you're
> running the kernel on, and therefore I can't guess what IRQ92 might be.
>



-- 
Thanks and Regards,
Harish Kumar. V
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<3>BUG: soft lockup - CPU#0 stuck for 61s! [Xfbdev:723]
BUG: soft lockup - CPU#0 stuck for 61s! [Xfbdev:723]
Modules linked in:Modules linked in: cir_lin cir_lin



Pid: 723, comm:               Xfbdev
Pid: 723, comm:               Xfbdev
CPU: 0    Not tainted  (2.6.28-rc9-omap1-svn6-dirty #19)
CPU: 0    Not tainted  (2.6.28-rc9-omap1-svn6-dirty #19)
PC is at handle_IRQ_event+0x28/0x74
PC is at handle_IRQ_event+0x28/0x74
LR is at handle_level_irq+0x94/0xec
LR is at handle_level_irq+0x94/0xec
pc : [<c008fd30>]    lr : [<c009133c>]    psr: 40000113
sp : c7a7dd50  ip : c7a7dd70  fp : c7a7dd6c
pc : [<c008fd30>]    lr : [<c009133c>]    psr: 40000113
sp : c7a7dd50  ip : c7a7dd70  fp : c7a7dd6c
r10: 0000001d  r9 : c0659080  r8 : 00000000
r10: 0000001d  r9 : c0659080  r8 : 00000000
r7 : 0000003e  r6 : 00000000  r5 : 0000003e  r4 : c7b82de0
r7 : 0000003e  r6 : 00000000  r5 : 0000003e  r4 : c7b82de0
r3 : 00000000  r2 : 00000050  r1 : c7b82de0  r0 : 0000003e
r3 : 00000000  r2 : 00000050  r1 : c7b82de0  r0 : 0000003e
Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 10c5387d  Table: 87a9c018  DAC: 00000015
Control: 10c5387d  Table: 87a9c018  DAC: 00000015
[<c003c370>] [<c003c370>] (show_regs+0x0/0x50) (show_regs+0x0/0x50) from [<c008f838>] from [<c008f838>] (softlockup_tick+0x108/0x148)
(softlockup_tick+0x108/0x148)
 r5:00000a72 r5:00000a72 r4:00000a35 r4:00000a35

[<c008f730>] [<c008f730>] (softlockup_tick+0x0/0x148) (softlockup_tick+0x0/0x148) from [<c0071c78>] from [<c0071c78>] (run_local_timers+0x1c/0x20)
(run_local_timers+0x1c/0x20)
 r8:c0658198 r8:c0658198 r7:00000b27 r7:00000b27 r6:077878a1 r6:077878a1 r5:c7818040 r5:c7818040 r4:00000000 r4:00000000

[<c0071c5c>] [<c0071c5c>] (run_local_timers+0x0/0x20) (run_local_timers+0x0/0x20) from [<c0071cf8>] from [<c0071cf8>] (update_process_times+0x30/0x60)
(update_process_times+0x30/0x60)
[<c0071cc8>] [<c0071cc8>] (update_process_times+0x0/0x60) (update_process_times+0x0/0x60) from [<c0084e78>] from [<c0084e78>] (tick_sched_timer+0x90/0xc4)
(tick_sched_timer+0x90/0xc4)
 r5:c7a7dd08 r5:c7a7dd08 r4:c069a488 r4:c069a488

[<c0084de8>] [<c0084de8>] (tick_sched_timer+0x0/0xc4) (tick_sched_timer+0x0/0xc4) from [<c007f0cc>] from [<c007f0cc>] (__run_hrtimer+0x58/0xa0)
(__run_hrtimer+0x58/0xa0)
 r7:7fffffff r7:7fffffff r6:ffffffff r6:ffffffff r5:c0658198 r5:c0658198 r4:c069a488 r4:c069a488

[<c007f074>] [<c007f074>] (__run_hrtimer+0x0/0xa0) (__run_hrtimer+0x0/0xa0) from [<c007fd88>] from [<c007fd88>] (hrtimer_interrupt+0x174/0x1ec)
(hrtimer_interrupt+0x174/0x1ec)
 r5:00000b27 r5:00000b27 r4:c069a488 r4:c069a488

[<c007fc14>] [<c007fc14>] (hrtimer_interrupt+0x0/0x1ec) (hrtimer_interrupt+0x0/0x1ec) from [<c00452c4>] from [<c00452c4>] (omap2_gp_timer_interrupt+0x28/0x34)
(omap2_gp_timer_interrupt+0x28/0x34)
[<c004529c>] [<c004529c>] (omap2_gp_timer_interrupt+0x0/0x34) (omap2_gp_timer_interrupt+0x0/0x34) from [<c008fd44>] from [<c008fd44>] (handle_IRQ_event+0x3c/0x74)
(handle_IRQ_event+0x3c/0x74)
[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:0000003e r7:0000003e r6:00000000 r6:00000000 r5:0000005f r5:0000005f r4:c0659ff8 r4:c0659ff8

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
 r5:c7a7dda0 r5:c7a7dda0 r4:0000005f r4:0000005f

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7dd08 to 0xc7a7dd50)
Exception stack(0xc7a7dd08 to 0xc7a7dd50)
dd00: dd00:                                     0000003e 0000003e c7b82de0 c7b82de0 00000050 00000050 00000000 00000000 c7b82de0 c7b82de0 0000003e 0000003e 

dd20: dd20: 00000000 00000000 0000003e 0000003e 00000000 00000000 c0659080 c0659080 0000001d 0000001d c7a7dd6c c7a7dd6c c7a7dd70 c7a7dd70 c7a7dd50 c7a7dd50 

dd40: dd40: c009133c c009133c c008fd30 c008fd30 40000113 40000113 ffffffff ffffffff                                                                         

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:000000b9 r7:000000b9 r6:00000000 r6:00000000 r5:0000003e r5:0000003e r4:c065983c r4:c065983c

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
 r5:c7a7de70 r5:c7a7de70 r4:0000003e r4:0000003e

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7dda0 to 0xc7a7dde8)
Exception stack(0xc7a7dda0 to 0xc7a7dde8)
dda0: dda0: 000000b9 000000b9 c7a8a910 c7a8a910 000000cb 000000cb 00000088 00000088 c7a8a910 c7a8a910 000000b9 000000b9 00000000 00000000 000000b9 000000b9 

ddc0: ddc0: 00000000 00000000 c0659080 c0659080 0000001d 0000001d c7a7de04 c7a7de04 c7a7de08 c7a7de08 c7a7dde8 c7a7dde8 c009133c c009133c c008fd30 c008fd30 

dde0: dde0: 40000113 40000113 ffffffff ffffffff                                                                                                             

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:00000001 r7:00000001 r6:c06553bc r6:c06553bc r5:000000b9 r5:000000b9 r4:c065b510 r4:c065b510

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c004c3d0>] from [<c004c3d0>] (gpio_irq_handler+0x12c/0x16c)
(gpio_irq_handler+0x12c/0x16c)
 r5:000000b9 r5:000000b9 r4:c065b514 r4:c065b514

[<c004c2a4>] [<c004c2a4>] (gpio_irq_handler+0x0/0x16c) (gpio_irq_handler+0x0/0x16c) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7de70 to 0xc7a7deb8)
Exception stack(0xc7a7de70 to 0xc7a7deb8)
de60: de60:                                                                         0000005c 0000005c c79304b0 c79304b0 0000006e 0000006e 00000000 00000000 

de80: de80: c79304b0 c79304b0 0000005c 0000005c 00000000 00000000 0000005c 0000005c 00000002 00000002 c7a7c000 c7a7c000 0000000a 0000000a c7a7ded4 c7a7ded4 

dea0: dea0: c7a7ded8 c7a7ded8 c7a7deb8 c7a7deb8 c009133c c009133c c008fd30 c008fd30 40000113 40000113 ffffffff ffffffff                                     

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:00000108 r7:00000108 r6:c7a7c000 r6:c7a7c000 r5:0000005c r5:0000005c r4:c0659f44 r4:c0659f44

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
 r5:c7a7dfb0 r5:c7a7dfb0 r4:0000005c r4:0000005c

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7df08 to 0xc7a7df50)
Exception stack(0xc7a7df08 to 0xc7a7df50)
df00: df00:                                     40000000 40000000 c064e368 c064e368 00000000 00000000 c0698da0 c0698da0 0000003e 0000003e 00000000 00000000 

df20: df20: c7a7c000 c7a7c000 00000108 00000108 00000002 00000002 c7a7c000 c7a7c000 0000000a 0000000a c7a7df7c c7a7df7c c7a7df80 c7a7df80 c7a7df50 c7a7df50 

df40: df40: c006dc00 c006dc00 c006db0c c006db0c 20000113 20000113 ffffffff ffffffff                                                                         

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c006dac4>] [<c006dac4>] (__do_softirq+0x0/0xf4) (__do_softirq+0x0/0xf4) from [<c006dc00>] from [<c006dc00>] (irq_exit+0x48/0x8c)
(irq_exit+0x48/0x8c)
[<c006dbb8>] [<c006dbb8>] (irq_exit+0x0/0x8c) (irq_exit+0x0/0x8c) from [<c003a06c>] from [<c003a06c>] (__exception_text_start+0x6c/0x88)
(__exception_text_start+0x6c/0x88)
 r5:00000000 r5:00000000 r4:0000003e r4:0000003e

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003abf8>] from [<c003abf8>] (__irq_usr+0x38/0x80)
(__irq_usr+0x38/0x80)
Exception stack(0xc7a7dfb0 to 0xc7a7dff8)
Exception stack(0xc7a7dfb0 to 0xc7a7dff8)
dfa0: dfa0:                                                                         00000001 00000001 bee54608 bee54608 00000001 00000001 00000000 00000000 

dfc0: dfc0: 00000000 00000000 0000000c 0000000c 00000160 00000160 00000108 00000108 00000000 00000000 00000000 00000000 00000002 00000002 bee54644 bee54644 

dfe0: dfe0: 00000018 00000018 bee545d0 bee545d0 00166440 00166440 00166680 00166680 60000010 60000010 ffffffff ffffffff                                     

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

<3>BUG: soft lockup - CPU#0 stuck for 61s! [Xfbdev:723]
BUG: soft lockup - CPU#0 stuck for 61s! [Xfbdev:723]
Modules linked in:Modules linked in: cir_lin cir_lin



Pid: 723, comm:               Xfbdev
Pid: 723, comm:               Xfbdev
CPU: 0    Not tainted  (2.6.28-rc9-omap1-svn6-dirty #19)
CPU: 0    Not tainted  (2.6.28-rc9-omap1-svn6-dirty #19)
PC is at handle_IRQ_event+0x28/0x74
PC is at handle_IRQ_event+0x28/0x74
LR is at handle_edge_irq+0x108/0x14c
LR is at handle_edge_irq+0x108/0x14c
pc : [<c008fd30>]    lr : [<c0091190>]    psr: 40000113
sp : c7a7dd10  ip : c7a7dd30  fp : c7a7dd2c
pc : [<c008fd30>]    lr : [<c0091190>]    psr: 40000113
sp : c7a7dd10  ip : c7a7dd30  fp : c7a7dd2c
r10: 00000021  r9 : c0659170  r8 : 00000001
r10: 00000021  r9 : c0659170  r8 : 00000001
r7 : 00000124  r6 : 00000000  r5 : 00000124  r4 : c7a3cef8
r7 : 00000124  r6 : 00000000  r5 : 00000124  r4 : c7a3cef8
r3 : 00000001  r2 : d9056000  r1 : c7a3cef8  r0 : 00000124
r3 : 00000001  r2 : d9056000  r1 : c7a3cef8  r0 : 00000124
Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 10c5387d  Table: 87a9c018  DAC: 00000015
Control: 10c5387d  Table: 87a9c018  DAC: 00000015
[<c003c370>] [<c003c370>] (show_regs+0x0/0x50) (show_regs+0x0/0x50) from [<c008f838>] from [<c008f838>] (softlockup_tick+0x108/0x148)
(softlockup_tick+0x108/0x148)
 r5:00000aaf r5:00000aaf r4:00000a72 r4:00000a72

[<c008f730>] [<c008f730>] (softlockup_tick+0x0/0x148) (softlockup_tick+0x0/0x148) from [<c0071c78>] from [<c0071c78>] (run_local_timers+0x1c/0x20)
(run_local_timers+0x1c/0x20)
 r8:c0658198 r8:c0658198 r7:00000b68 r7:00000b68 r6:2545666c r6:2545666c r5:c7818040 r5:c7818040 r4:00000000 r4:00000000

[<c0071c5c>] [<c0071c5c>] (run_local_timers+0x0/0x20) (run_local_timers+0x0/0x20) from [<c0071cf8>] from [<c0071cf8>] (update_process_times+0x30/0x60)
(update_process_times+0x30/0x60)
[<c0071cc8>] [<c0071cc8>] (update_process_times+0x0/0x60) (update_process_times+0x0/0x60) from [<c0084e78>] from [<c0084e78>] (tick_sched_timer+0x90/0xc4)
(tick_sched_timer+0x90/0xc4)
 r5:c7a7dcc8 r5:c7a7dcc8 r4:c069a488 r4:c069a488

[<c0084de8>] [<c0084de8>] (tick_sched_timer+0x0/0xc4) (tick_sched_timer+0x0/0xc4) from [<c007f0cc>] from [<c007f0cc>] (__run_hrtimer+0x58/0xa0)
(__run_hrtimer+0x58/0xa0)
 r7:7fffffff r7:7fffffff r6:ffffffff r6:ffffffff r5:c0658198 r5:c0658198 r4:c069a488 r4:c069a488

[<c007f074>] [<c007f074>] (__run_hrtimer+0x0/0xa0) (__run_hrtimer+0x0/0xa0) from [<c007fd88>] from [<c007fd88>] (hrtimer_interrupt+0x174/0x1ec)
(hrtimer_interrupt+0x174/0x1ec)
 r5:00000b68 r5:00000b68 r4:c069a488 r4:c069a488

[<c007fc14>] [<c007fc14>] (hrtimer_interrupt+0x0/0x1ec) (hrtimer_interrupt+0x0/0x1ec) from [<c00452c4>] from [<c00452c4>] (omap2_gp_timer_interrupt+0x28/0x34)
(omap2_gp_timer_interrupt+0x28/0x34)
[<c004529c>] [<c004529c>] (omap2_gp_timer_interrupt+0x0/0x34) (omap2_gp_timer_interrupt+0x0/0x34) from [<c008fd44>] from [<c008fd44>] (handle_IRQ_event+0x3c/0x74)
(handle_IRQ_event+0x3c/0x74)
[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:00000124 r7:00000124 r6:00000000 r6:00000000 r5:0000005f r5:0000005f r4:c0659ff8 r4:c0659ff8

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
 r5:c7a7dda0 r5:c7a7dda0 r4:0000005f r4:0000005f

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7dcc8 to 0xc7a7dd10)
Exception stack(0xc7a7dcc8 to 0xc7a7dd10)
dcc0: dcc0:                                     00000124 00000124 c7a3cef8 c7a3cef8 d9056000 d9056000 00000001 00000001 c7a3cef8 c7a3cef8 00000124 00000124 

dce0: dce0: 00000000 00000000 00000124 00000124 00000001 00000001 c0659170 c0659170 00000021 00000021 c7a7dd2c c7a7dd2c c7a7dd30 c7a7dd30 c7a7dd10 c7a7dd10 

dd00: dd00: c0091190 c0091190 c008fd30 c008fd30 40000113 40000113 ffffffff ffffffff                                                                         

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c0091190>] from [<c0091190>] (handle_edge_irq+0x108/0x14c)
(handle_edge_irq+0x108/0x14c)
 r7:00000001 r7:00000001 r6:c7a3cef8 r6:c7a3cef8 r5:00000124 r5:00000124 r4:c065ce24 r4:c065ce24

[<c0091088>] [<c0091088>] (handle_edge_irq+0x0/0x14c) (handle_edge_irq+0x0/0x14c) from [<c004c3d0>] from [<c004c3d0>] (gpio_irq_handler+0x12c/0x16c)
(gpio_irq_handler+0x12c/0x16c)
 r7:00000001 r7:00000001 r6:c065554c r6:c065554c r5:00000124 r5:00000124 r4:c065ce28 r4:c065ce28

[<c004c2a4>] [<c004c2a4>] (gpio_irq_handler+0x0/0x16c) (gpio_irq_handler+0x0/0x16c) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7dda0 to 0xc7a7dde8)
Exception stack(0xc7a7dda0 to 0xc7a7dde8)
dda0: dda0: 000000b9 000000b9 c7a8a910 c7a8a910 000000cb 000000cb 00000088 00000088 c7a8a910 c7a8a910 000000b9 000000b9 00000000 00000000 000000b9 000000b9 

ddc0: ddc0: 00000000 00000000 c0659080 c0659080 0000001d 0000001d c7a7de04 c7a7de04 c7a7de08 c7a7de08 c7a7dde8 c7a7dde8 c009133c c009133c c008fd30 c008fd30 

dde0: dde0: 40000113 40000113 ffffffff ffffffff                                                                                                             

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:00000001 r7:00000001 r6:c06553bc r6:c06553bc r5:000000b9 r5:000000b9 r4:c065b510 r4:c065b510

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c004c3d0>] from [<c004c3d0>] (gpio_irq_handler+0x12c/0x16c)
(gpio_irq_handler+0x12c/0x16c)
 r5:000000b9 r5:000000b9 r4:c065b514 r4:c065b514

[<c004c2a4>] [<c004c2a4>] (gpio_irq_handler+0x0/0x16c) (gpio_irq_handler+0x0/0x16c) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7de70 to 0xc7a7deb8)
Exception stack(0xc7a7de70 to 0xc7a7deb8)
de60: de60:                                                                         0000005c 0000005c c79304b0 c79304b0 0000006e 0000006e 00000000 00000000 

de80: de80: c79304b0 c79304b0 0000005c 0000005c 00000000 00000000 0000005c 0000005c 00000002 00000002 c7a7c000 c7a7c000 0000000a 0000000a c7a7ded4 c7a7ded4 

dea0: dea0: c7a7ded8 c7a7ded8 c7a7deb8 c7a7deb8 c009133c c009133c c008fd30 c008fd30 40000113 40000113 ffffffff ffffffff                                     

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:00000108 r7:00000108 r6:c7a7c000 r6:c7a7c000 r5:0000005c r5:0000005c r4:c0659f44 r4:c0659f44

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
 r5:c7a7dfb0 r5:c7a7dfb0 r4:0000005c r4:0000005c

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7df08 to 0xc7a7df50)
Exception stack(0xc7a7df08 to 0xc7a7df50)
df00: df00:                                     40000000 40000000 c064e368 c064e368 00000000 00000000 c0698da0 c0698da0 0000003e 0000003e 00000000 00000000 

df20: df20: c7a7c000 c7a7c000 00000108 00000108 00000002 00000002 c7a7c000 c7a7c000 0000000a 0000000a c7a7df7c c7a7df7c c7a7df80 c7a7df80 c7a7df50 c7a7df50 

df40: df40: c006dc00 c006dc00 c006db0c c006db0c 20000113 20000113 ffffffff ffffffff                                                                         

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c006dac4>] [<c006dac4>] (__do_softirq+0x0/0xf4) (__do_softirq+0x0/0xf4) from [<c006dc00>] from [<c006dc00>] (irq_exit+0x48/0x8c)
(irq_exit+0x48/0x8c)
[<c006dbb8>] [<c006dbb8>] (irq_exit+0x0/0x8c) (irq_exit+0x0/0x8c) from [<c003a06c>] from [<c003a06c>] (__exception_text_start+0x6c/0x88)
(__exception_text_start+0x6c/0x88)
 r5:00000000 r5:00000000 r4:0000003e r4:0000003e

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003abf8>] from [<c003abf8>] (__irq_usr+0x38/0x80)
(__irq_usr+0x38/0x80)
Exception stack(0xc7a7dfb0 to 0xc7a7dff8)
Exception stack(0xc7a7dfb0 to 0xc7a7dff8)
dfa0: dfa0:                                                                         00000001 00000001 bee54608 bee54608 00000001 00000001 00000000 00000000 

dfc0: dfc0: 00000000 00000000 0000000c 0000000c 00000160 00000160 00000108 00000108 00000000 00000000 00000000 00000000 00000002 00000002 bee54644 bee54644 

dfe0: dfe0: 00000018 00000018 bee545d0 bee545d0 00166440 00166440 00166680 00166680 60000010 60000010 ffffffff ffffffff                                     

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

<3>BUG: soft lockup - CPU#0 stuck for 61s! [Xfbdev:723]
BUG: soft lockup - CPU#0 stuck for 61s! [Xfbdev:723]
Modules linked in:Modules linked in: cir_lin cir_lin



Pid: 723, comm:               Xfbdev
Pid: 723, comm:               Xfbdev
CPU: 0    Not tainted  (2.6.28-rc9-omap1-svn6-dirty #19)
CPU: 0    Not tainted  (2.6.28-rc9-omap1-svn6-dirty #19)
PC is at handle_IRQ_event+0x28/0x74
PC is at handle_IRQ_event+0x28/0x74
LR is at handle_level_irq+0x94/0xec
LR is at handle_level_irq+0x94/0xec
pc : [<c008fd30>]    lr : [<c009133c>]    psr: 40000113
sp : c7a7dc78  ip : c7a7dc98  fp : c7a7dc94
pc : [<c008fd30>]    lr : [<c009133c>]    psr: 40000113
sp : c7a7dc78  ip : c7a7dc98  fp : c7a7dc94
r10: 00000021  r9 : c0659170  r8 : 00000001
r10: 00000021  r9 : c0659170  r8 : 00000001
r7 : 0000003e  r6 : 00000000  r5 : 0000003e  r4 : c7b82de0
r7 : 0000003e  r6 : 00000000  r5 : 0000003e  r4 : c7b82de0
r3 : 00000000  r2 : 00000050  r1 : c7b82de0  r0 : 0000003e
r3 : 00000000  r2 : 00000050  r1 : c7b82de0  r0 : 0000003e
Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 10c5387d  Table: 87a9c018  DAC: 00000015
Control: 10c5387d  Table: 87a9c018  DAC: 00000015
[<c003c370>] [<c003c370>] (show_regs+0x0/0x50) (show_regs+0x0/0x50) from [<c008f838>] from [<c008f838>] (softlockup_tick+0x108/0x148)
(softlockup_tick+0x108/0x148)
 r5:00000aec r5:00000aec r4:00000aaf r4:00000aaf

[<c008f730>] [<c008f730>] (softlockup_tick+0x0/0x148) (softlockup_tick+0x0/0x148) from [<c0071c78>] from [<c0071c78>] (run_local_timers+0x1c/0x20)
(run_local_timers+0x1c/0x20)
 r8:c0658198 r8:c0658198 r7:00000baa r7:00000baa r6:0701430d r6:0701430d r5:c7818040 r5:c7818040 r4:00000000 r4:00000000

[<c0071c5c>] [<c0071c5c>] (run_local_timers+0x0/0x20) (run_local_timers+0x0/0x20) from [<c0071cf8>] from [<c0071cf8>] (update_process_times+0x30/0x60)
(update_process_times+0x30/0x60)
[<c0071cc8>] [<c0071cc8>] (update_process_times+0x0/0x60) (update_process_times+0x0/0x60) from [<c0084e78>] from [<c0084e78>] (tick_sched_timer+0x90/0xc4)
(tick_sched_timer+0x90/0xc4)
 r5:c7a7dc30 r5:c7a7dc30 r4:c069a488 r4:c069a488

[<c0084de8>] [<c0084de8>] (tick_sched_timer+0x0/0xc4) (tick_sched_timer+0x0/0xc4) from [<c007f0cc>] from [<c007f0cc>] (__run_hrtimer+0x58/0xa0)
(__run_hrtimer+0x58/0xa0)
 r7:7fffffff r7:7fffffff r6:ffffffff r6:ffffffff r5:c0658198 r5:c0658198 r4:c069a488 r4:c069a488

[<c007f074>] [<c007f074>] (__run_hrtimer+0x0/0xa0) (__run_hrtimer+0x0/0xa0) from [<c007fd88>] from [<c007fd88>] (hrtimer_interrupt+0x174/0x1ec)
(hrtimer_interrupt+0x174/0x1ec)
 r5:00000baa r5:00000baa r4:c069a488 r4:c069a488

[<c007fc14>] [<c007fc14>] (hrtimer_interrupt+0x0/0x1ec) (hrtimer_interrupt+0x0/0x1ec) from [<c00452c4>] from [<c00452c4>] (omap2_gp_timer_interrupt+0x28/0x34)
(omap2_gp_timer_interrupt+0x28/0x34)
[<c004529c>] [<c004529c>] (omap2_gp_timer_interrupt+0x0/0x34) (omap2_gp_timer_interrupt+0x0/0x34) from [<c008fd44>] from [<c008fd44>] (handle_IRQ_event+0x3c/0x74)
(handle_IRQ_event+0x3c/0x74)
[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:0000003e r7:0000003e r6:00000000 r6:00000000 r5:0000005f r5:0000005f r4:c0659ff8 r4:c0659ff8

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
 r5:c7a7dcc8 r5:c7a7dcc8 r4:0000005f r4:0000005f

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7dc30 to 0xc7a7dc78)
Exception stack(0xc7a7dc30 to 0xc7a7dc78)
dc20: dc20:                                                                         0000003e 0000003e c7b82de0 c7b82de0 00000050 00000050 00000000 00000000 

dc40: dc40: c7b82de0 c7b82de0 0000003e 0000003e 00000000 00000000 0000003e 0000003e 00000001 00000001 c0659170 c0659170 00000021 00000021 c7a7dc94 c7a7dc94 

dc60: dc60: c7a7dc98 c7a7dc98 c7a7dc78 c7a7dc78 c009133c c009133c c008fd30 c008fd30 40000113 40000113 ffffffff ffffffff                                     

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:00000124 r7:00000124 r6:00000000 r6:00000000 r5:0000003e r5:0000003e r4:c065983c r4:c065983c

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
 r5:c7a7dda0 r5:c7a7dda0 r4:0000003e r4:0000003e

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7dcc8 to 0xc7a7dd10)
Exception stack(0xc7a7dcc8 to 0xc7a7dd10)
dcc0: dcc0:                                     00000124 00000124 c7a3cef8 c7a3cef8 d9056000 d9056000 00000001 00000001 c7a3cef8 c7a3cef8 00000124 00000124 

dce0: dce0: 00000000 00000000 00000124 00000124 00000001 00000001 c0659170 c0659170 00000021 00000021 c7a7dd2c c7a7dd2c c7a7dd30 c7a7dd30 c7a7dd10 c7a7dd10 

dd00: dd00: c0091190 c0091190 c008fd30 c008fd30 40000113 40000113 ffffffff ffffffff                                                                         

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c0091190>] from [<c0091190>] (handle_edge_irq+0x108/0x14c)
(handle_edge_irq+0x108/0x14c)
 r7:00000001 r7:00000001 r6:c7a3cef8 r6:c7a3cef8 r5:00000124 r5:00000124 r4:c065ce24 r4:c065ce24

[<c0091088>] [<c0091088>] (handle_edge_irq+0x0/0x14c) (handle_edge_irq+0x0/0x14c) from [<c004c3d0>] from [<c004c3d0>] (gpio_irq_handler+0x12c/0x16c)
(gpio_irq_handler+0x12c/0x16c)
 r7:00000001 r7:00000001 r6:c065554c r6:c065554c r5:00000124 r5:00000124 r4:c065ce28 r4:c065ce28

[<c004c2a4>] [<c004c2a4>] (gpio_irq_handler+0x0/0x16c) (gpio_irq_handler+0x0/0x16c) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7dda0 to 0xc7a7dde8)
Exception stack(0xc7a7dda0 to 0xc7a7dde8)
dda0: dda0: 000000b9 000000b9 c7a8a910 c7a8a910 000000cb 000000cb 00000088 00000088 c7a8a910 c7a8a910 000000b9 000000b9 00000000 00000000 000000b9 000000b9 

ddc0: ddc0: 00000000 00000000 c0659080 c0659080 0000001d 0000001d c7a7de04 c7a7de04 c7a7de08 c7a7de08 c7a7dde8 c7a7dde8 c009133c c009133c c008fd30 c008fd30 

dde0: dde0: 40000113 40000113 ffffffff ffffffff                                                                                                             

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:00000001 r7:00000001 r6:c06553bc r6:c06553bc r5:000000b9 r5:000000b9 r4:c065b510 r4:c065b510

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c004c3d0>] from [<c004c3d0>] (gpio_irq_handler+0x12c/0x16c)
(gpio_irq_handler+0x12c/0x16c)
 r5:000000b9 r5:000000b9 r4:c065b514 r4:c065b514

[<c004c2a4>] [<c004c2a4>] (gpio_irq_handler+0x0/0x16c) (gpio_irq_handler+0x0/0x16c) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7de70 to 0xc7a7deb8)
Exception stack(0xc7a7de70 to 0xc7a7deb8)
de60: de60:                                                                         0000005c 0000005c c79304b0 c79304b0 0000006e 0000006e 00000000 00000000 

de80: de80: c79304b0 c79304b0 0000005c 0000005c 00000000 00000000 0000005c 0000005c 00000002 00000002 c7a7c000 c7a7c000 0000000a 0000000a c7a7ded4 c7a7ded4 

dea0: dea0: c7a7ded8 c7a7ded8 c7a7deb8 c7a7deb8 c009133c c009133c c008fd30 c008fd30 40000113 40000113 ffffffff ffffffff                                     

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:00000108 r7:00000108 r6:c7a7c000 r6:c7a7c000 r5:0000005c r5:0000005c r4:c0659f44 r4:c0659f44

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
 r5:c7a7dfb0 r5:c7a7dfb0 r4:0000005c r4:0000005c

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7df08 to 0xc7a7df50)
Exception stack(0xc7a7df08 to 0xc7a7df50)
df00: df00:                                     40000000 40000000 c064e368 c064e368 00000000 00000000 c0698da0 c0698da0 0000003e 0000003e 00000000 00000000 

df20: df20: c7a7c000 c7a7c000 00000108 00000108 00000002 00000002 c7a7c000 c7a7c000 0000000a 0000000a c7a7df7c c7a7df7c c7a7df80 c7a7df80 c7a7df50 c7a7df50 

df40: df40: c006dc00 c006dc00 c006db0c c006db0c 20000113 20000113 ffffffff ffffffff                                                                         

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c006dac4>] [<c006dac4>] (__do_softirq+0x0/0xf4) (__do_softirq+0x0/0xf4) from [<c006dc00>] from [<c006dc00>] (irq_exit+0x48/0x8c)
(irq_exit+0x48/0x8c)
[<c006dbb8>] [<c006dbb8>] (irq_exit+0x0/0x8c) (irq_exit+0x0/0x8c) from [<c003a06c>] from [<c003a06c>] (__exception_text_start+0x6c/0x88)
(__exception_text_start+0x6c/0x88)
 r5:00000000 r5:00000000 r4:0000003e r4:0000003e

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003abf8>] from [<c003abf8>] (__irq_usr+0x38/0x80)
(__irq_usr+0x38/0x80)
Exception stack(0xc7a7dfb0 to 0xc7a7dff8)
Exception stack(0xc7a7dfb0 to 0xc7a7dff8)
dfa0: dfa0:                                                                         00000001 00000001 bee54608 bee54608 00000001 00000001 00000000 00000000 

dfc0: dfc0: 00000000 00000000 0000000c 0000000c 00000160 00000160 00000108 00000108 00000000 00000000 00000000 00000000 00000002 00000002 bee54644 bee54644 

dfe0: dfe0: 00000018 00000018 bee545d0 bee545d0 00166440 00166440 00166680 00166680 60000010 60000010 ffffffff ffffffff                                     

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

<3>BUG: soft lockup - CPU#0 stuck for 61s! [Xfbdev:723]
BUG: soft lockup - CPU#0 stuck for 61s! [Xfbdev:723]
Modules linked in:Modules linked in: cir_lin cir_lin



Pid: 723, comm:               Xfbdev
Pid: 723, comm:               Xfbdev
CPU: 0    Not tainted  (2.6.28-rc9-omap1-svn6-dirty #19)
CPU: 0    Not tainted  (2.6.28-rc9-omap1-svn6-dirty #19)
PC is at handle_IRQ_event+0x28/0x74
PC is at handle_IRQ_event+0x28/0x74
LR is at handle_level_irq+0x94/0xec
LR is at handle_level_irq+0x94/0xec
pc : [<c008fd30>]    lr : [<c009133c>]    psr: 40000113
sp : c7a7dc78  ip : c7a7dc98  fp : c7a7dc94
pc : [<c008fd30>]    lr : [<c009133c>]    psr: 40000113
sp : c7a7dc78  ip : c7a7dc98  fp : c7a7dc94
r10: 00000021  r9 : c0659170  r8 : 00000001
r10: 00000021  r9 : c0659170  r8 : 00000001
r7 : 0000003e  r6 : 00000000  r5 : 0000003e  r4 : c7b82de0
r7 : 0000003e  r6 : 00000000  r5 : 0000003e  r4 : c7b82de0
r3 : 00000000  r2 : 00000050  r1 : c7b82de0  r0 : 0000003e
r3 : 00000000  r2 : 00000050  r1 : c7b82de0  r0 : 0000003e
Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Flags: nZcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
Control: 10c5387d  Table: 87a9c018  DAC: 00000015
Control: 10c5387d  Table: 87a9c018  DAC: 00000015
[<c003c370>] [<c003c370>] (show_regs+0x0/0x50) (show_regs+0x0/0x50) from [<c008f838>] from [<c008f838>] (softlockup_tick+0x108/0x148)
(softlockup_tick+0x108/0x148)
 r5:00000b29 r5:00000b29 r4:00000aec r4:00000aec

[<c008f730>] [<c008f730>] (softlockup_tick+0x0/0x148) (softlockup_tick+0x0/0x148) from [<c0071c78>] from [<c0071c78>] (run_local_timers+0x1c/0x20)
(run_local_timers+0x1c/0x20)
 r8:c0658198 r8:c0658198 r7:00000beb r7:00000beb r6:24ce30d7 r6:24ce30d7 r5:c7818040 r5:c7818040 r4:00000000 r4:00000000

[<c0071c5c>] [<c0071c5c>] (run_local_timers+0x0/0x20) (run_local_timers+0x0/0x20) from [<c0071cf8>] from [<c0071cf8>] (update_process_times+0x30/0x60)
(update_process_times+0x30/0x60)
[<c0071cc8>] [<c0071cc8>] (update_process_times+0x0/0x60) (update_process_times+0x0/0x60) from [<c0084e78>] from [<c0084e78>] (tick_sched_timer+0x90/0xc4)
(tick_sched_timer+0x90/0xc4)
 r5:c7a7dc30 r5:c7a7dc30 r4:c069a488 r4:c069a488

[<c0084de8>] [<c0084de8>] (tick_sched_timer+0x0/0xc4) (tick_sched_timer+0x0/0xc4) from [<c007f0cc>] from [<c007f0cc>] (__run_hrtimer+0x58/0xa0)
(__run_hrtimer+0x58/0xa0)
 r7:7fffffff r7:7fffffff r6:ffffffff r6:ffffffff r5:c0658198 r5:c0658198 r4:c069a488 r4:c069a488

[<c007f074>] [<c007f074>] (__run_hrtimer+0x0/0xa0) (__run_hrtimer+0x0/0xa0) from [<c007fd88>] from [<c007fd88>] (hrtimer_interrupt+0x174/0x1ec)
(hrtimer_interrupt+0x174/0x1ec)
 r5:00000beb r5:00000beb r4:c069a488 r4:c069a488

[<c007fc14>] [<c007fc14>] (hrtimer_interrupt+0x0/0x1ec) (hrtimer_interrupt+0x0/0x1ec) from [<c00452c4>] from [<c00452c4>] (omap2_gp_timer_interrupt+0x28/0x34)
(omap2_gp_timer_interrupt+0x28/0x34)
[<c004529c>] [<c004529c>] (omap2_gp_timer_interrupt+0x0/0x34) (omap2_gp_timer_interrupt+0x0/0x34) from [<c008fd44>] from [<c008fd44>] (handle_IRQ_event+0x3c/0x74)
(handle_IRQ_event+0x3c/0x74)
[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:0000003e r7:0000003e r6:00000000 r6:00000000 r5:0000005f r5:0000005f r4:c0659ff8 r4:c0659ff8

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
 r5:c7a7dcc8 r5:c7a7dcc8 r4:0000005f r4:0000005f

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7dc30 to 0xc7a7dc78)
Exception stack(0xc7a7dc30 to 0xc7a7dc78)
dc20: dc20:                                                                         0000003e 0000003e c7b82de0 c7b82de0 00000050 00000050 00000000 00000000 

dc40: dc40: c7b82de0 c7b82de0 0000003e 0000003e 00000000 00000000 0000003e 0000003e 00000001 00000001 c0659170 c0659170 00000021 00000021 c7a7dc94 c7a7dc94 

dc60: dc60: c7a7dc98 c7a7dc98 c7a7dc78 c7a7dc78 c009133c c009133c c008fd30 c008fd30 40000113 40000113 ffffffff ffffffff                                     

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:00000124 r7:00000124 r6:00000000 r6:00000000 r5:0000003e r5:0000003e r4:c065983c r4:c065983c

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
 r5:c7a7dda0 r5:c7a7dda0 r4:0000003e r4:0000003e

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7dcc8 to 0xc7a7dd10)
Exception stack(0xc7a7dcc8 to 0xc7a7dd10)
dcc0: dcc0:                                     00000124 00000124 c7a3cef8 c7a3cef8 d9056000 d9056000 00000001 00000001 c7a3cef8 c7a3cef8 00000124 00000124 

dce0: dce0: 00000000 00000000 00000124 00000124 00000001 00000001 c0659170 c0659170 00000021 00000021 c7a7dd2c c7a7dd2c c7a7dd30 c7a7dd30 c7a7dd10 c7a7dd10 

dd00: dd00: c0091190 c0091190 c008fd30 c008fd30 40000113 40000113 ffffffff ffffffff                                                                         

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c0091190>] from [<c0091190>] (handle_edge_irq+0x108/0x14c)
(handle_edge_irq+0x108/0x14c)
 r7:00000001 r7:00000001 r6:c7a3cef8 r6:c7a3cef8 r5:00000124 r5:00000124 r4:c065ce24 r4:c065ce24

[<c0091088>] [<c0091088>] (handle_edge_irq+0x0/0x14c) (handle_edge_irq+0x0/0x14c) from [<c004c3d0>] from [<c004c3d0>] (gpio_irq_handler+0x12c/0x16c)
(gpio_irq_handler+0x12c/0x16c)
 r7:00000001 r7:00000001 r6:c065554c r6:c065554c r5:00000124 r5:00000124 r4:c065ce28 r4:c065ce28

[<c004c2a4>] [<c004c2a4>] (gpio_irq_handler+0x0/0x16c) (gpio_irq_handler+0x0/0x16c) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7dda0 to 0xc7a7dde8)
Exception stack(0xc7a7dda0 to 0xc7a7dde8)
dda0: dda0: 000000b9 000000b9 c7a8a910 c7a8a910 000000cb 000000cb 00000088 00000088 c7a8a910 c7a8a910 000000b9 000000b9 00000000 00000000 000000b9 000000b9 

ddc0: ddc0: 00000000 00000000 c0659080 c0659080 0000001d 0000001d c7a7de04 c7a7de04 c7a7de08 c7a7de08 c7a7dde8 c7a7dde8 c009133c c009133c c008fd30 c008fd30 

dde0: dde0: 40000113 40000113 ffffffff ffffffff                                                                                                             

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:00000001 r7:00000001 r6:c06553bc r6:c06553bc r5:000000b9 r5:000000b9 r4:c065b510 r4:c065b510

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c004c3d0>] from [<c004c3d0>] (gpio_irq_handler+0x12c/0x16c)
(gpio_irq_handler+0x12c/0x16c)
 r5:000000b9 r5:000000b9 r4:c065b514 r4:c065b514

[<c004c2a4>] [<c004c2a4>] (gpio_irq_handler+0x0/0x16c) (gpio_irq_handler+0x0/0x16c) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7de70 to 0xc7a7deb8)
Exception stack(0xc7a7de70 to 0xc7a7deb8)
de60: de60:                                                                         0000005c 0000005c c79304b0 c79304b0 0000006e 0000006e 00000000 00000000 

de80: de80: c79304b0 c79304b0 0000005c 0000005c 00000000 00000000 0000005c 0000005c 00000002 00000002 c7a7c000 c7a7c000 0000000a 0000000a c7a7ded4 c7a7ded4 

dea0: dea0: c7a7ded8 c7a7ded8 c7a7deb8 c7a7deb8 c009133c c009133c c008fd30 c008fd30 40000113 40000113 ffffffff ffffffff                                     

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c008fd08>] [<c008fd08>] (handle_IRQ_event+0x0/0x74) (handle_IRQ_event+0x0/0x74) from [<c009133c>] from [<c009133c>] (handle_level_irq+0x94/0xec)
(handle_level_irq+0x94/0xec)
 r7:00000108 r7:00000108 r6:c7a7c000 r6:c7a7c000 r5:0000005c r5:0000005c r4:c0659f44 r4:c0659f44

[<c00912a8>] [<c00912a8>] (handle_level_irq+0x0/0xec) (handle_level_irq+0x0/0xec) from [<c003a068>] from [<c003a068>] (__exception_text_start+0x68/0x88)
(__exception_text_start+0x68/0x88)
 r5:c7a7dfb0 r5:c7a7dfb0 r4:0000005c r4:0000005c

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003aa30>] from [<c003aa30>] (__irq_svc+0x30/0x80)
(__irq_svc+0x30/0x80)
Exception stack(0xc7a7df08 to 0xc7a7df50)
Exception stack(0xc7a7df08 to 0xc7a7df50)
df00: df00:                                     40000000 40000000 c064e368 c064e368 00000000 00000000 c0698da0 c0698da0 0000003e 0000003e 00000000 00000000 

df20: df20: c7a7c000 c7a7c000 00000108 00000108 00000002 00000002 c7a7c000 c7a7c000 0000000a 0000000a c7a7df7c c7a7df7c c7a7df80 c7a7df80 c7a7df50 c7a7df50 

df40: df40: c006dc00 c006dc00 c006db0c c006db0c 20000113 20000113 ffffffff ffffffff                                                                         

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

[<c006dac4>] [<c006dac4>] (__do_softirq+0x0/0xf4) (__do_softirq+0x0/0xf4) from [<c006dc00>] from [<c006dc00>] (irq_exit+0x48/0x8c)
(irq_exit+0x48/0x8c)
[<c006dbb8>] [<c006dbb8>] (irq_exit+0x0/0x8c) (irq_exit+0x0/0x8c) from [<c003a06c>] from [<c003a06c>] (__exception_text_start+0x6c/0x88)
(__exception_text_start+0x6c/0x88)
 r5:00000000 r5:00000000 r4:0000003e r4:0000003e

[<c003a000>] [<c003a000>] (__exception_text_start+0x0/0x88) (__exception_text_start+0x0/0x88) from [<c003abf8>] from [<c003abf8>] (__irq_usr+0x38/0x80)
(__irq_usr+0x38/0x80)
Exception stack(0xc7a7dfb0 to 0xc7a7dff8)
Exception stack(0xc7a7dfb0 to 0xc7a7dff8)
dfa0: dfa0:                                                                         00000001 00000001 bee54608 bee54608 00000001 00000001 00000000 00000000 

dfc0: dfc0: 00000000 00000000 0000000c 0000000c 00000160 00000160 00000108 00000108 00000000 00000000 00000000 00000000 00000002 00000002 bee54644 bee54644 

dfe0: dfe0: 00000018 00000018 bee545d0 bee545d0 00166440 00166440 00166680 00166680 60000010 60000010 ffffffff ffffffff                                     

 r5:d8200000 r5:d8200000 r4:ffffffff r4:ffffffff

From dedekind1 at gmail.com  Tue Jun 29 02:41:36 2010
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 29 Jun 2010 09:41:36 +0300
Subject: [PATCH] mxc_nand: fix PM
In-Reply-To: <4C15D542.2060102@eukrea.com>
References: <1274942000-3580-2-git-send-email-eric@eukrea.com>
	<1274982919-13251-1-git-send-email-eric@eukrea.com>
	<4C15D542.2060102@eukrea.com>
Message-ID: <1277793696.1041.967.camel@localhost>

On Mon, 2010-06-14 at 09:07 +0200, Eric B?nard wrote:
> Hi Sascha,
> 
> Le 27/05/2010 19:55, Eric B?nard a ?crit :
> > * when resuming, we get the following log :
> > nand_resume called for a chip which is not in suspended state
> > * this happens because mtd->suspend and mtd->resume are already
> > called from the mtd layer, thus they were called a second time
> > in mxc_nand so mtd complains when trying to resume for the
> > second time
> > * the fix is to remove these call and thus remove the supend and
> > resume functions of mxc_nand
> >
> any news concerning this patch ?
> 

Pushed to l2-mtd-2.6.git / dunno

-- 
Best Regards,
Artem Bityutskiy (????? ????????)



From dedekind1 at gmail.com  Tue Jun 29 02:47:48 2010
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 29 Jun 2010 09:47:48 +0300
Subject: [PATCH] ixp4xx: add support for static flash partitions
In-Reply-To: <20100614161519.GB24877@riccoc20.at.omicron.at>
References: <20100531162434.GA4599@riccoc20.at.omicron.at>
	<1276420566.19028.184.camel@localhost>
	<20100614161519.GB24877@riccoc20.at.omicron.at>
Message-ID: <1277794068.1041.971.camel@localhost>

On Mon, 2010-06-14 at 18:15 +0200, Richard Cochran wrote:
> On Sun, Jun 13, 2010 at 12:16:06PM +0300, Artem Bityutskiy wrote:
> > I could fix your patch up myself, but I do not know the code, so please,
> > re-send a patch against the latest mtd-2.6 tree.
> 
> Okay, here it is again, this time against today's master branch of 
> git://git.infradead.org/mtd-2.6.git
> 
> Thanks,
> Richard
> 
> 
> This patch adds support for static flash partitioning from a platform
> device. Also, we clean up some weirdness where statements were separated
> by commas instead of semicolons. While we are at it, fix some minor bad
> white space, too.
> 
> Signed-off-by: Richard Cochran <richard.cochran at omicron.at>

Pushed to l2-mtd-2.6.git / dunno.

-- 
Best Regards,
Artem Bityutskiy (????? ????????)



From dedekind1 at gmail.com  Tue Jun 29 02:49:28 2010
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Tue, 29 Jun 2010 09:49:28 +0300
Subject: [PATCH] mtd: physmap.c: use resource_size()
In-Reply-To: <0D753D10438DA54287A00B02708426976371223143@AUSP01VMBX24.collaborationhost.net>
References: <0D753D10438DA54287A00B02708426976371223143@AUSP01VMBX24.collaborationhost.net>
Message-ID: <1277794168.1041.972.camel@localhost>

On Mon, 2010-06-14 at 11:57 -0500, H Hartley Sweeten wrote:
> Signed-off-by: H Hartley Sweeten <hsweeten at visionengravers.com>
> Cc: David Woodhouse <David.Woodhouse at intel.com>

Pushed to l2-mtd-2.6.git / master

-- 
Best Regards,
Artem Bityutskiy (????? ????????)



From u.kleine-koenig at pengutronix.de  Tue Jun 29 02:58:17 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Tue, 29 Jun 2010 08:58:17 +0200
Subject: Subject: [PATCH] arm: fix KConfig warning for mach-mx25
In-Reply-To: <201006290005.20875.PeterHuewe@gmx.de>
References: <201006290005.20875.PeterHuewe@gmx.de>
Message-ID: <20100629065817.GA23160@pengutronix.de>

Hiho,

[added linux-kbuild at vger.kernel.org to Cc:]

On Tue, Jun 29, 2010 at 12:05:20AM +0200, Peter H?we wrote:
> From: Peter Huewe <peterhuewe at gmx.de
> 
> This patch fixes a KConfig warning:
> "arch/arm/mach-mx25/Kconfig:18:warning: choice value used outside its
> choice group"
> 
> Signed-off-by: Peter Huewe <peterhuewe at gmx.de>
The problem also goes away when renaming one of the two
MACH_EUKREA_MBIMXSD_BASEBOARD (the other MACH_EUKREA_MBIMXSD_BASEBOARD
is in arch/arm/mach-mx3/Kconfig).  AFAIK Eric already sent a patch to
fix this.  I think this is the real issue, I don't know why the warning
goes away with your patch.

Nevertheless I like your patch.  And note there are two other variables
in arch/arm/mach-mx2 that could benefit from the same "fix".  (But as I
moved this file in my tree I suggest to wait until my changes hit Linus'
tree and then fix arch/arm/mach-imx/Kconfig.)

Best regards
Uwe

> ---
> KernelVersion: linux-next-20100628
>  arch/arm/mach-mx25/Kconfig |    3 +--
>  1 files changed, 1 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
> index 3a6668e..2f436ed 100644
> --- a/arch/arm/mach-mx25/Kconfig
> +++ b/arch/arm/mach-mx25/Kconfig
> @@ -15,8 +15,7 @@ choice
>  	default MACH_EUKREA_MBIMXSD_BASEBOARD
>  
>  config MACH_EUKREA_MBIMXSD_BASEBOARD
> -	prompt "Eukrea MBIMXSD development board"
> -	bool
> +	bool "Eukrea MBIMXSD development board"
>  	help
>  	  This adds board specific devices that can be found on Eukrea's
>  	  MBIMXSD evaluation board.
> -- 
> 1.7.1

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From kgene.kim at samsung.com  Tue Jun 29 04:25:32 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 29 Jun 2010 17:25:32 +0900
Subject: [PATCH v4] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <4C287576.6050506@ru.mvista.com>
References: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
	<4C287576.6050506@ru.mvista.com>
Message-ID: <00c601cb1764$a9231c10$fb695430$%kim@samsung.com>

Sergei Shtylyov wrote:
> 
> Hello.
> 
Hello :-)

Thanks for your review and comments.

> Kukjin Kim wrote:
> 
> > From: Abhilash Kesavan <a.kesavan at samsung.com>
> 
> > Adds support for the Samsung PATA controller. This driver is based on
the
> > Libata subsystem and references the earlier patches sent for IDE
subsystem.
> 
> > Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> 
> [...]
> 
> > diff --git a/drivers/ata/pata_samsung_cf.c
b/drivers/ata/pata_samsung_cf.c
> > new file mode 100644
> > index 0000000..aeb2825
> > --- /dev/null
> > +++ b/drivers/ata/pata_samsung_cf.c
> > @@ -0,0 +1,735 @@
> [...]
> > +static unsigned long
> > +pata_s3c_setup_timing(struct s3c_ide_info *info, const struct
ata_timing *ata)
> > +{
> > +	int t1;
> > +	int t2;
> > +	int t2i;
> > +	ulong piotime;
> > +
> > +	t1 = ata->setup;
> > +	t2 = ata->act8b;
> > +	t2i = ata->rec8b;
> 
>     Could be initializers...
> 
OK.

> [...]
> 
> > +/*
> > + * pata_s3c_data_xfer - Transfer data by PIO
> > + */
> > +unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char
*buf,
> > +				unsigned int buflen, int rw)
> > +{
> > +	struct ata_port *ap = dev->link->ap;
> > +	struct s3c_ide_info *info = ap->host->private_data;
> > +	void __iomem *data_addr = ap->ioaddr.data_addr;
> > +	unsigned int words = buflen >> 1, i;
> > +	u16 *data_ptr = (u16 *)buf;
> > +
> > +	/* Requires wait same as in ata_inb/ata_outb */
> > +	if (rw == READ)
> > +		for (i = 0; i < words; i++, data_ptr++) {
> > +			wait_for_host_ready(info);
> > +			(void) readw(data_addr);
> > +			wait_for_host_ready(info);
> > +			*data_ptr = readw(info->ide_addr
> > +					+ S3C_ATA_PIO_RDATA);
> > +		}
> > +	else
> > +		for (i = 0; i < words; i++, data_ptr++) {
> > +			wait_for_host_ready(info);
> > +			writew(*data_ptr, data_addr);
> > +		}
> > +
> > +	if (buflen & 0x01) {
> > +		dev_err(ap->dev, "unexpected trailing data\n");
> > +		return -EINVAL;
> 
>     This method should return number of bytes consumed, never error...
> 
OK..will remove the invalid return.

> > +	}
> > +
> > +	return words << 1;
> > +}
> 
> [...]
> 
> > +/*
> > + * pata_s3c_devchk - PATA device presence detection
> > + */
> > +static unsigned int pata_s3c_devchk(struct ata_port *ap,
> > +				unsigned int device)
> > +{
> > +	struct ata_ioports *ioaddr = &ap->ioaddr;
> > +	u8 nsect, lbal;
> > +
> > +	ap->ops->sff_dev_select(ap, device);
> 
>     Can call pata_s3c_dev_select() directly...
> 
Will replace it throughout the file.

> > +/*
> > + * pata_s3c_wait_after_reset - wait for devices to become ready after
reset
> > + */
> > +static int pata_s3c_wait_after_reset(struct ata_link *link,
> > +		unsigned int devmask, unsigned long deadline)
> > +{
> > +	struct ata_port *ap = link->ap;
> > +	struct ata_ioports *ioaddr = &ap->ioaddr;
> > +	unsigned int dev0 = devmask & (1 << 0);
> > +	unsigned int dev1 = devmask & (1 << 1);
> > +	int rc, ret = 0;
> > +
> > +	msleep(ATA_WAIT_AFTER_RESET);
> > +
> > +	/* always check readiness of the master device */
> > +	rc = ata_sff_wait_ready(link, deadline);
> > +	if (rc)
> > +		return rc;
> > +
> > +	/* if device 1 was found in ata_devchk, wait for register
> > +	 * access briefly, then wait for BSY to clear.
> > +	 */
> > +	if (dev1) {
> > +		int i;
> > +
> > +		ap->ops->sff_dev_select(ap, 1);
> 
>     Ditto.
> 
> > +
> > +		for (i = 0; i < 2; i++) {
> > +			u8 nsect, lbal;
> > +
> > +			nsect = ata_inb(ap->host, ioaddr->nsect_addr);
> > +			lbal = ata_inb(ap->host, ioaddr->lbal_addr);
> > +			if ((nsect == 1) && (lbal == 1))
> > +				break;
> > +			msleep(50);	/* give drive a breather */
> > +		}
> > +
> > +		rc = ata_sff_wait_ready(link, deadline);
> > +		if (rc) {
> > +			if (rc != -ENODEV)
> > +				return rc;
> > +			ret = rc;
> > +		}
> > +	}
> > +
> 
>     Should have copied the original commant here, cause I dount that this
> drive selection trickery is indeed necessary...
> 
Will add comment.

> > +	ap->ops->sff_dev_select(ap, 0);
> > +	if (dev1)
> > +		ap->ops->sff_dev_select(ap, 1);
> > +	if (dev0)
> > +		ap->ops->sff_dev_select(ap, 0);
> 
>     Ditto.
> 
> > +/*
> > + * pata_s3c_softreset - reset host port via ATA SRST
> > + */
> > +static int pata_s3c_softreset(struct ata_link *link, unsigned int
*classes,
> > +			 unsigned long deadline)
> > +{
> > +	struct ata_port *ap = link->ap;
> > +	unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
> 
>     I don't see where you set this flag, hence the check seems useless.
> 
Will remove the checks associated with this flag.

> > +	unsigned int devmask = 0;
> > +	int rc;
> > +	u8 err;
> > +
> > +	/* determine if device 0/1 are present */
> > +	if (pata_s3c_devchk(ap, 0))
> > +		devmask |= (1 << 0);
> > +	if (slave_possible && pata_s3c_devchk(ap, 1))
> > +		devmask |= (1 << 1);
> > +
> > +	/* select device 0 again */
> > +	ap->ops->sff_dev_select(ap, 0);
> 
>     Can call pata_s3c_dev_select() directly...
> 
> > +
> > +	/* issue bus reset */
> > +	rc = pata_s3c_bus_softreset(ap, devmask, deadline);
> > +	/* if link is occupied, -ENODEV too is an error */
> > +	if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
> 
>     sata_scr_valid() doesn't apply to your PATA driver, no need to call
it.
> 
OK

> > +static void pata_s3c_hwinit(struct s3c_ide_info *info,
> > +				struct s3c_ide_platdata *pdata)
> > +{
> > +	switch (info->cpu_type) {
> > +	case TYPE_S3C64XX:
> > +		/* Configure as big endian */
> > +		pata_s3c_cfg_mode(info->sfr_addr);
> > +		pata_s3c_set_endian(info->ide_addr, 1);
> > +		pata_s3c_enable(info->ide_addr, true);
> > +		msleep(100);
> > +
> > +		/* Remove IRQ Status */
> > +		writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
> > +		writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
> > +	break;
> 
>     Mis-indented: one more tab needed.
> 
> > +
> > +	case TYPE_S5PC100:
> > +		pata_s3c_cfg_mode(info->sfr_addr);
> 
>     There should be a comment like /* FALLTHRU */ if *break* is omitted.
> 
> > +	case TYPE_S5PV210:
> > +		/* Configure as little endian */
> > +		pata_s3c_set_endian(info->ide_addr, 0);
> > +		pata_s3c_enable(info->ide_addr, true);
> > +		msleep(100);
> > +
> > +		/* Remove IRQ Status */
> > +		writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
> > +		writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
> > +	break;
> 
>     Mis-indented.
> 
Will correct the indentation and add a fall through comment.

> > +static int __devinit pata_s3c_probe(struct platform_device *pdev)
> 
>     Is this device really hot-pluggable? Shouldn't this be '__init'
instead?
> 
No, it's not..will change to __init.

> > +{
> > +	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
> > +	struct device *dev = &pdev->dev;
> > +	struct s3c_ide_info *info;
> > +	struct resource *res;
> > +	struct ata_port *ap;
> > +	struct ata_host *host;
> > +	enum s3c_cpu_type cpu_type;
> > +	int ret;
> > +
> > +	cpu_type = platform_get_device_id(pdev)->driver_data;
> > +
> > +	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
> > +	if (!info) {
> > +		dev_err(dev, "failed to allocate memory for device data\n");
> > +		return -ENOMEM;
> > +	}
> > +
> > +	info->irq = platform_get_irq(pdev, 0);
> > +	if (info->irq < 0) {
> > +		dev_err(dev, "could not obtain irq number\n");
> 
>     You driver permits working without IRQ -- why require an IRQ resource
even
> if there's no IRQ?
> 
Will remove the check as driver can be used in polling mode.

> [...]
> 
> > +	if (!info->irq) {
> 
>     Should be (info->irq <= 0) instead, I think, with the above check
removed.
> 
OK

> > +		ap->flags |= ATA_FLAG_PIO_POLLING;
> > +		ata_port_desc(ap, "no IRQ, using PIO polling\n");
> > +	}
> > +
> 
> [...]
> 
> > +static struct platform_driver pata_s3c_driver = {
> > +	.probe		= pata_s3c_probe,
> 
>     If this function will be '__init', this needs to be removed.
> 
Will remove probe method and used platform_driver_probe().

> [...]
> 
> > +static int __init pata_s3c_init(void)
> > +{
> > +	return platform_driver_register(&pata_s3c_driver);
> 
>     I'd coinsider platform_driver_probe() -- this device doesn't seem to
be
> hot-pluggable...
> 

Thanks. Will re-submit updated soon.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Tue Jun 29 04:28:34 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 29 Jun 2010 17:28:34 +0900
Subject: [PATCH v4] libata: pata_samsung_cf: Add Samsung PATA	controller
	driver
In-Reply-To: <4C2874DE.7070806@ru.mvista.com>
References: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
	<4C22704B.50103@pobox.com>
	<001f01cb1417$dce8f8d0$96baea70$%kim@samsung.com>
	<20100626193310.GA19339@n2100.arm.linux.org.uk>
	<4C2874DE.7070806@ru.mvista.com>
Message-ID: <00c701cb1765$12c6df30$38549d90$%kim@samsung.com>

Sergei Shtylyov wrote:
> 
> Hello.
> 
> Russell King - ARM Linux wrote:
> 
> >> How do you think?
> >> May I send this to your patch tracking system?
> >> Or...how should I handle this?
> 
> > If Jeff is happy, then I'm happy.  However, shouldn't it also have Ben's
> > ack?
> 
>     I for one still have comments to be addressed, will post in a jiffy...
> 

OK..will address comments from you as soon as possible.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From coffbeta at gmail.com  Tue Jun 29 04:29:04 2010
From: coffbeta at gmail.com (CoffBeta)
Date: Tue, 29 Jun 2010 16:29:04 +0800
Subject: gpiolib and sleeping gpios
In-Reply-To: <4C1E88AE.5070808@bluewatersys.com>
References: <386783.17931.qm@web180310.mail.gq1.yahoo.com> 
	<4C1E88AE.5070808@bluewatersys.com>
Message-ID: <AANLkTinunR-mrXFh8uLV5YfeArC-_A1NJWz708n7r4pU@mail.gmail.com>

 non-sleeping

On Mon, Jun 21, 2010 at 05:31, Ryan Mallon <ryan at bluewatersys.com> wrote:
> On 06/19/2010 06:21 PM, David Brownell wrote:
>>
>>>
>>> The runtime warnings will only show instances where the
>>> non-sleeping
>>> versions where called instead of the sleeping versions.
>>
>> ... *AND* the GPIO requires the cansleep() version...
>>
>> Right; such calls are errors. ?We issue
>> warnings since fault returns are inapplicable.
>
> A driver which only uses the non-sleeping versions, but _could_ use the
> cansleep variants (ie all calls to gpio_(set/get)_value are made from
> contexts where it is possible to sleep) is not so easy to spot. Passing
> a sleeping to gpio to such a driver will result in spurious warnings.
>
>>> There is no
>>> warning to say that we are calling the spinlock safe
>>> version, where it is possible to sleep.
>>
>> The call context isn't what controls whether
>> gpio_get_value() or gpio_get_value_cansleep()
>> is appropriate ... it's the GPIO itself, and
>> how its implementation works.
>
> No, a driver should not know anything about a gpio which is passed to
> it. If a driver is able to call the cansleep variants, then it should,
> and it will allow any gpio, sleeping or non-sleeping, to be used with
> that driver.
>
> If a driver uses a gpio in such a way that it cannot sleep, ie the
> gpio_(get/set)_value calls are made from spinlock context, then only
> gpios which do not sleep may be used with that driver.
>
> Thats why I think specifying whether the gpio is able to sleep when it
> is requested is a good idea. A driver which cannot use a sleeping gpio
>
>
>> "possible to sleep" is a GPIO attribute,
>> exposed by a predicate. ?If spinlock-safe
>> calls are used on GPIOs with that attribute,
>> ?a warning *IS* issued.
>
> Possible to sleep is also an attribute of how a driver _uses_ a gpio.
>
>>>
>>> The point I was trying to make is that there are lots of
>>> drivers which
>>> will not work with gpios on sleeping io expanders because
>>> they call the
>>> spinlock safe gpio calls.
>>
>> And they will trigger runtime warnings, and
>> thus eventually get fixed. ?The way to do that
>> is to check if the GPIO needs the cansleep()
>> call
>
> Hmm, maybe this then for drivers which cannot accept sleeping gpios:
>
> ?if (gpio_cansleep(some_gpio)) {
> ? ? ? ? ?dev_err(&dev, "This driver only supports non-sleeping gpios");
> ? ? ? ? ?return -EINVAL;
> ?}
>
> ?err = gpio_request(some_gpio, "some_gpio");
>
> I think ideally, gpio_request should specify this via a flags argument, ie:
>
> ?#define GPIOF_NO_SLEEP ? ? ? ?0x0
> ?#define GPIOF_CANSLEEP ? ? ? ?0x1
>
> ?err = gpio_request(some_gpio, "some_gpio", GPIOF_NO_SLEEP);
>
> ~Ryan
>
> --
> Bluewater Systems Ltd - ARM Technology Solution Centre
>
> Ryan Mallon ? ? ? ? ? ? ? ? ? ? 5 Amuri Park, 404 Barbadoes St
> ryan at bluewatersys.com ? ? ? ? ? PO Box 13 889, Christchurch 8013
> http://www.bluewatersys.com ? ? New Zealand
> Phone: +64 3 3779127 ? ? ? ? ? ?Freecall: Australia 1800 148 751
> Fax: ? +64 3 3779135 ? ? ? ? ? ? ? ? ? ? ?USA 1800 261 2934
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at ?http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at ?http://www.tux.org/lkml/
>


From inki.dae at samsung.com  Tue Jun 29 04:31:46 2010
From: inki.dae at samsung.com (InKi Dae)
Date: Tue, 29 Jun 2010 17:31:46 +0900
Subject: [PATCH 0/3] ARM: S5PV210: Add MIPI-DSI support.
Message-ID: <4C29AF72.6090200@samsung.com>

Hello all,

This patch is for MIPI-DSI controller based on S5PV210 (or S5PC110).

LCD Panel can use following interfaces,
- RGB or CPU Interface.
- RGB or CPU Interface based on MIPI-DSI.

In case of small size lcd panel, it was ok only rgb or cpu interface not
using mipi controller.
But big size panel(more then 480x800) needs MIPI-DSI Interface or other
hardwares like LVDS
To transfer image data to lcd panel fine.

I tested this patch on cpu interface based on MIPI so for this patch,
Some mainline codes should be modified and also considered RGB interface.

This patch set consists of the following patches,

[PATCH 1/3] FB: Add some members for CPU Interface.
[PATCH 2/3] S5PV210: FB: Add MIPI-DSI and CPU Interface features.
[PATCH 3/3] S5PV210: Add MIPI-DSI Driver.

Best regards,
InKi Dae


From kgene.kim at samsung.com  Tue Jun 29 04:39:44 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 29 Jun 2010 17:39:44 +0900
Subject: [PATCH v4] libata: pata_samsung_cf: Add Samsung PATA	controller
	driver
In-Reply-To: <20100626193310.GA19339@n2100.arm.linux.org.uk>
References: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
	<4C22704B.50103@pobox.com>
	<001f01cb1417$dce8f8d0$96baea70$%kim@samsung.com>
	<20100626193310.GA19339@n2100.arm.linux.org.uk>
Message-ID: <00c901cb1766$a36c2df0$ea4489d0$%kim@samsung.com>

Russell King wrote:
> 
> On Fri, Jun 25, 2010 at 12:38:19PM +0900, Kukjin Kim wrote:
> > Russell,
> >
> > How do you think?
> > May I send this to your patch tracking system?
> > Or...how should I handle this?
> 
> If Jeff is happy, then I'm happy.  However, shouldn't it also have Ben's
> ack?

Sounds good :-)

Hmm..submitted has been addressed comments from Ben.
So maybe can get the Ben's ack.

But will waiting for Ben's ack.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From catalin.marinas at arm.com  Tue Jun 29 05:31:05 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 29 Jun 2010 10:31:05 +0100
Subject: PB1176 broken in 2.6.35-rc1, bisected
In-Reply-To: <AANLkTilcyi6Tjwvz1eU211Q41RcwQAwYAAkoQwhDe-Vj@mail.gmail.com>
References: <AANLkTikoCy2FH_5ICh-iiI_wzGj6D6oszyM-zCXkNC_4@mail.gmail.com>
	<1275518783.27834.2.camel@e102109-lin.cambridge.arm.com>
	<AANLkTimJkaadEM1xvG30WVvEjJPZQXHwx216SeqWFKNp@mail.gmail.com>
	<1275581709.8775.14.camel@e102109-lin.cambridge.arm.com>
	<AANLkTilcyi6Tjwvz1eU211Q41RcwQAwYAAkoQwhDe-Vj@mail.gmail.com>
Message-ID: <1277803865.19746.9.camel@e102109-lin.cambridge.arm.com>

On Tue, 2010-06-29 at 01:42 +0100, Linus Walleij wrote:
> 2010/6/3 Catalin Marinas <catalin.marinas at arm.com>:
> > On Thu, 2010-06-03 at 09:48 +0100, Linus Walleij wrote:
> >> 2010/6/3 Catalin Marinas <catalin.marinas at arm.com>:
> >> > On Wed, 2010-06-02 at 23:33 +0100, Linus Walleij wrote:
> >> >> my PB1176 doesn't boot properly in 2.6.35-rc1, it goes to this point
> >> >> and hangs:
> >> >>
> >> >> (...)
> >> >> Switching to clocksource timer3
> >> >> NET: Registered protocol family 2
> >> >> IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
> >> >> TCP established hash table entries: 4096 (order: 3, 32768 bytes)
> >> >> TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
> >> >> TCP: Hash tables configured (established 4096 bind 4096)
> >> >> TCP reno registered
> >> >> UDP hash table entries: 256 (order: 0, 4096 bytes)
> >> >> UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
> >> >> NET: Registered protocol family 1
> >> >> RPC: Registered udp transport module.
> >> >> RPC: Registered tcp transport module.
> >> >> RPC: Registered tcp NFSv4.1 backchannel transport module.
> >> >
> >> > Have you tried disabling CONFIG_CACHE_L2X0?
> >>
> >> Hey it works! :-)
> >>
> >> I suppose your latest patches will hopefully  get the defconfig with
> >> l2x0 working again in -rc2 if they're merged?
> >
> > I think there is an L2 erratum (and trying to get the right workaround).
> > It may be triggered by commit e7c5650f6.
> >
> > I'll get back on the list with a patch.
> 
> Have I missed this? My 2.6.35's and -next trees still require me to
> disable the L2X0 cache on the PB1176 for it to boot.
> 
> It's a bit sad if we have a 2.6.35 which cannot even boot on this
> card...

I posted some patches couple of times but I haven't received any
comments. I'm posting another version (now only affecting the RealView
code) and cc you. If it works for you as well, I'll send it to the patch
system.

-- 
Catalin



From catalin.marinas at arm.com  Tue Jun 29 05:31:35 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Tue, 29 Jun 2010 10:31:35 +0100
Subject: [PATCH] ARM: RealView: Do not use outer_sync() on certain with
	L210/L220
Message-ID: <20100629093135.10365.99959.stgit@e102109-lin.cambridge.arm.com>

RealView boards with certain revisions of the L210/L220 cache controller
may have issues (hardware deadlock) with the recent changes to the mb()
barrier implementation (DSB followed by an L2 cache sync). The patch
disables ARM_DMA_MEM_BUFFERABLE for the RealView boards with L210/L220
and redefines the mandatory barriers without the outer_sync() call.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Linus Walleij <linus.ml.walleij at gmail.com>
---
 arch/arm/mach-realview/Kconfig                 |    3 +++
 arch/arm/mach-realview/include/mach/barriers.h |    9 +++++++++
 arch/arm/mm/Kconfig                            |    2 ++
 3 files changed, 14 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-realview/include/mach/barriers.h

diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index ee5e392..f72b6c4 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -18,6 +18,7 @@ config REALVIEW_EB_ARM11MP
 	bool "Support ARM11MPCore tile"
 	depends on MACH_REALVIEW_EB
 	select CPU_V6
+	select ARCH_HAS_BARRIERS
 	help
 	  Enable support for the ARM11MPCore tile on the Realview platform.
 
@@ -35,6 +36,7 @@ config MACH_REALVIEW_PB11MP
 	select CPU_V6
 	select ARM_GIC
 	select HAVE_PATA_PLATFORM
+	select ARCH_HAS_BARRIERS
 	help
 	  Include support for the ARM(R) RealView MPCore Platform Baseboard.
 	  PB11MPCore is a platform with an on-board ARM11MPCore and has
@@ -44,6 +46,7 @@ config MACH_REALVIEW_PB1176
 	bool "Support RealView/PB1176 platform"
 	select CPU_V6
 	select ARM_GIC
+	select ARCH_HAS_BARRIERS
 	help
 	  Include support for the ARM(R) RealView ARM1176 Platform Baseboard.
 
diff --git a/arch/arm/mach-realview/include/mach/barriers.h b/arch/arm/mach-realview/include/mach/barriers.h
new file mode 100644
index 0000000..1014027
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/barriers.h
@@ -0,0 +1,9 @@
+/*
+ * Barriers redefined for RealView platforms with L210/L220 cache controller
+ * to work around hardware errata causing an outer_sync() operation to
+ * deadlock the system. Note that CONFIG_DMA_MEM_BUFFERABLE is not set for
+ * these platforms.
+ */
+#define mb()		dsb()
+#define rmb()		dmb()
+#define wmb()		mb()
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 3053731..9f10a9b 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -828,6 +828,8 @@ config ARM_L1_CACHE_SHIFT
 
 config ARM_DMA_MEM_BUFFERABLE
 	bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
+	depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
+		     MACH_REALVIEW_PB11MP)
 	default y if CPU_V6 || CPU_V7
 	help
 	  Historically, the kernel has used strongly ordered mappings to



From roman.tereshonkov at nokia.com  Tue Jun 29 06:20:42 2010
From: roman.tereshonkov at nokia.com (roman.tereshonkov at nokia.com)
Date: Tue, 29 Jun 2010 12:20:42 +0200
Subject: [PATCH] spi/omap2_mcspi: disable and enable chan between each
	SPI 	transfer
In-Reply-To: <4C289CCB.7010409@gmail.com>
References: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com>
	<AANLkTin7mqe_zJIbyDcRPpCLaxPhl_dZQrSGua2z1nYW@mail.gmail.com>
	<4C24A182.4060009@gmail.com>
	<E1C7579D1379824DAE67858071C810382DD8495B26@NOK-EUMSG-02.mgdnok.nokia.com>
	<4C289CCB.7010409@gmail.com>
Message-ID: <E1C7579D1379824DAE67858071C810382DD84963BC@NOK-EUMSG-02.mgdnok.nokia.com>


Hi Jason,

It is a little bit hard to analyze your logs.
1. You showed the bytes read in your own way but there is the data reading in omap2_mcspi_txrx_pio function also.
2. For your third test case. You try to read data after TX_ONLY, before triggering RX_ONLY, and get the right word.
Looks like there is something wrong.

Try to log MCSPI_CHxSTAT register to follow when RXS bit (register RX is full) is set.
And do not use the RX register reading in you own way. If you need RX logging do it from omap2_mcspi_txrx_pio function.


Regards
Roman Tereshonkov


>-----Original Message-----
>From: ext jason [mailto:jason77.wang at gmail.com] 
>Sent: 28 June, 2010 16:00
>To: Tereshonkov Roman (Nokia-D/Helsinki)
>Cc: grant.likely at secretlab.ca; david-b at pacbell.net; 
>spi-devel-general at lists.sourceforge.net; 
>linux-arm-kernel at lists.infradead.org
>Subject: Re: [PATCH] spi/omap2_mcspi: disable and enable chan 
>between each SPI transfer
>
>roman.tereshonkov at nokia.com wrote:
>>  
>>
>>   
>>> -----Original Message-----
>>> From: ext jason [mailto:jason77.wang at gmail.com] 
>>> Sent: 25 June, 2010 15:31
>>> To: Grant Likely
>>> Cc: Tereshonkov Roman (Nokia-D/Helsinki); david-b at pacbell.net; 
>>>     
>>>     
>[snip]
>>> the RXS bit will be set to status register immediately,
>>> write a dummy data to TX register to trigger this session(in 
>>> fact this  
>>> trigger  doesn't take  effect),
>>> check the RXS bit and read the first data(the first data is 
>the last 
>>> random data received in TX_ONLY transfer).
>>>
>>>     
>>
>> For me it is very strange that you have RXS bit set after 
>TX_ONLY transmission.
>> The problem might be elsewhere and your solution will just 
>mask the real problem.
>> Can you enable the spi debug and error logs and show them 
>for your broken case.
>>
>> Regards
>> Roman Tereshonkov
>>
>>   
>Hi Roman,
>I don't know how to enable the spi debug and generate an error 
>log, but 
>i design
>3 testcases to investigate this issue. These 3 testcases are based off 
>the latest upstream.
>test1: After TX_ONLY transfer, we will change this channel to RX_ONLY 
>mode. And then we
>will write a dummy data to trigger this RX transaction, here i add a 
>polling RXS bit
>before write triggering data, from the result, we can see we 
>successfully to get a RXS
>bit and read an unmeaningful data.(this prove the write 
>triggering data 
>is not necessary
>to start a rx transaction).
>test2: This time i move the polling RXS bit to the location after the 
>write trigger data, we can get
>RXS bit as well and read an unmeaningful data too. The data 
>read out is 
>identical to the one
>in test1.(This prove the write trigger data don't take effect in fact).
>test3: Except i revert the commit a330ce2 "omap2_mcspi: Flush posted 
>writes", other is same as the test2.
>But this time, we read out a correct data ads7846 sending out. 
>(I don't 
>know why this commit can
>affect the result, maybe it is time issue. If we can disable this 
>channel after TX_ONLY transfer and
>reenable it before RX_ONLY transfer, we will not get RXS bit in test1, 
>and will read out a correct data
>both in test2 and test3).
>
>Test1 result output & patch:
># =====SPI MESSAGE BEGIN=====
>tansferTX: conf=1123d4, data=93
>tansferRX: conf=1113d4, data=0
>rx_data = f0
>tansferTX: conf=1123d4, data=93
>tansferRX: conf=1113d4, data=0
>rx_data = f0
>*****SPI MESSAGE END*****
>=====SPI MESSAGE BEGIN=====
>tansferTX: conf=1123d4, data=93
>tansferRX: conf=1113d4, data=0
>rx_data = f0
>tansferTX: conf=1123d4, data=93
>tansferRX: conf=1113d4, data=0
>rx_data = f0
>*****SPI MESSAGE END*****
>
>
>Subject: [PATCH] SPI/test1: get rx_data in RX_ONLY transfer before 
>trigger writing
>
>get rx_data in RX_ONLY transfer before trigger writing dummy data to
>TX register.
>
>Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>---
>drivers/spi/omap2_mcspi.c | 19 ++++++++++++++-----
>1 files changed, 14 insertions(+), 5 deletions(-)
>
>diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>index b3a94ca..ddfe4b0 100644
>--- a/drivers/spi/omap2_mcspi.c
>+++ b/drivers/spi/omap2_mcspi.c
>@@ -893,7 +893,7 @@ static void omap2_mcspi_work(struct 
>work_struct *work)
>spi = m->spi;
>cs = spi->controller_state;
>cd = spi->controller_data;
>-
>+ printk("=====SPI MESSAGE BEGIN=====\n");
>omap2_mcspi_set_enable(spi, 1);
>list_for_each_entry(t, &m->transfers, transfer_list) {
>if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
>@@ -928,17 +928,26 @@ static void omap2_mcspi_work(struct work_struct 
>*work)
>if (t->len > ((cs->word_len + 7) >> 3))
>chconf |= OMAP2_MCSPI_CHCONF_TURBO;
>}
>-
>+ printk("tansfer%s: conf=%x, data=%x\n", t->tx_buf ? "TX" : "RX",
>+ chconf, t->tx_buf ? *(u8 *)(t->tx_buf) : 0);
>mcspi_write_chconf0(spi, chconf);
>
>if (t->len) {
>unsigned count;
>
>/* RX_ONLY mode needs dummy data in TX reg */
>- if (t->tx_buf == NULL)
>+ if (t->tx_buf == NULL) {
>+ u8 rx_data;
>+ if (mcspi_wait_for_reg_bit(cs->base + OMAP2_MCSPI_CHSTAT0,
>+ OMAP2_MCSPI_CHSTAT_RXS) < 0)
>+ dev_err(&spi->dev, "RXS timed out\n");
>+
>+ rx_data = __raw_readl(cs->base + OMAP2_MCSPI_RX0);
>+ printk("rx_data = %x\n", rx_data);
>+
>__raw_writel(0, cs->base
>+ OMAP2_MCSPI_TX0);
>-
>+ }
>if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
>count = omap2_mcspi_txrx_dma(spi, t);
>else
>@@ -971,7 +980,7 @@ static void omap2_mcspi_work(struct 
>work_struct *work)
>omap2_mcspi_force_cs(spi, 0);
>
>omap2_mcspi_set_enable(spi, 0);
>-
>+ printk("*****SPI MESSAGE END*****\n");
>m->status = status;
>m->complete(m->context);
>
>-- 
>1.5.6.5
>
>
>Test2 result output & patch:
># =====SPI MESSAGE BEGIN=====
>tansferTX: conf=1123d4, data=93
>tansferRX: conf=1113d4, data=0
>rx_data = f0
>tansferTX: conf=1123d4, data=93
>tansferRX: conf=1113d4, data=0
>rx_data = f0
>*****SPI MESSAGE END*****
>=====SPI MESSAGE BEGIN=====
>tansferTX: conf=1123d4, data=93
>tansferRX: conf=1113d4, data=0
>rx_data = f0
>tansferTX: conf=1123d4, data=93
>tansferRX: conf=1113d4, data=0
>rx_data = f0
>*****SPI MESSAGE END*****
>
>Subject: [PATCH] SPI/test2: get rx_data in RX_ONLY transfer after 
>trigger writing
>
>get rx_data in RX_ONLY transfer after trigger writing dummy data to
>TX register.
>
>Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>---
>drivers/spi/omap2_mcspi.c | 18 ++++++++++++++----
>1 files changed, 14 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>index b3a94ca..96c508a 100644
>--- a/drivers/spi/omap2_mcspi.c
>+++ b/drivers/spi/omap2_mcspi.c
>@@ -893,7 +893,7 @@ static void omap2_mcspi_work(struct 
>work_struct *work)
>spi = m->spi;
>cs = spi->controller_state;
>cd = spi->controller_data;
>-
>+ printk("=====SPI MESSAGE BEGIN=====\n");
>omap2_mcspi_set_enable(spi, 1);
>list_for_each_entry(t, &m->transfers, transfer_list) {
>if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
>@@ -928,17 +928,27 @@ static void omap2_mcspi_work(struct work_struct 
>*work)
>if (t->len > ((cs->word_len + 7) >> 3))
>chconf |= OMAP2_MCSPI_CHCONF_TURBO;
>}
>-
>+ printk("tansfer%s: conf=%x, data=%x\n", t->tx_buf ? "TX" : "RX",
>+ chconf, t->tx_buf ? *(u8 *)(t->tx_buf) : 0);
>mcspi_write_chconf0(spi, chconf);
>
>if (t->len) {
>unsigned count;
>
>/* RX_ONLY mode needs dummy data in TX reg */
>- if (t->tx_buf == NULL)
>+ if (t->tx_buf == NULL) {
>+ u8 rx_data;
>__raw_writel(0, cs->base
>+ OMAP2_MCSPI_TX0);
>
>+ if (mcspi_wait_for_reg_bit(cs->base + OMAP2_MCSPI_CHSTAT0,
>+ OMAP2_MCSPI_CHSTAT_RXS) < 0)
>+ dev_err(&spi->dev, "RXS timed out\n");
>+
>+ rx_data = __raw_readl(cs->base + OMAP2_MCSPI_RX0);
>+ printk("rx_data = %x\n", rx_data);
>+
>+ }
>if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
>count = omap2_mcspi_txrx_dma(spi, t);
>else
>@@ -971,7 +981,7 @@ static void omap2_mcspi_work(struct 
>work_struct *work)
>omap2_mcspi_force_cs(spi, 0);
>
>omap2_mcspi_set_enable(spi, 0);
>-
>+ printk("*****SPI MESSAGE END*****\n");
>m->status = status;
>m->complete(m->context);
>
>-- 
>1.5.6.5
>
>
>Test3 result output & patch:
># =====SPI MESSAGE BEGIN=====
>tansferTX: conf=1123d4, data=93
>tansferRX: conf=1113d4, data=0
>rx_data = 77
>tansferTX: conf=1123d4, data=93
>tansferRX: conf=1113d4, data=0
>rx_data = 76
>*****SPI MESSAGE END*****
>=====SPI MESSAGE BEGIN=====
>tansferTX: conf=1123d4, data=93
>tansferRX: conf=1113d4, data=0
>rx_data = 75
>tansferTX: conf=1123d4, data=93
>tansferRX: conf=1113d4, data=0
>rx_data = 74
>*****SPI MESSAGE END*****
>
>Subject: [PATCH] SPI/test3: get rx_data in RX_ONLY transfer after 
>trigger writing
>
>At frist revert the commit a330ce2 "omap2_mcspi: Flush posted writes",
>then get rx_data in RX_ONLY transfer after trigger writing dummy data
>to TX register.
>
>Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>---
>drivers/spi/omap2_mcspi.c | 19 ++++++++++++++-----
>1 files changed, 14 insertions(+), 5 deletions(-)
>
>diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>index b3a94ca..5d71cad 100644
>--- a/drivers/spi/omap2_mcspi.c
>+++ b/drivers/spi/omap2_mcspi.c
>@@ -204,7 +204,6 @@ static inline void 
>mcspi_write_chconf0(const struct 
>spi_device *spi, u32 val)
>
>cs->chconf0 = val;
>mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
>- mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
>}
>
>static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
>@@ -893,7 +892,7 @@ static void omap2_mcspi_work(struct 
>work_struct *work)
>spi = m->spi;
>cs = spi->controller_state;
>cd = spi->controller_data;
>-
>+ printk("=====SPI MESSAGE BEGIN=====\n");
>omap2_mcspi_set_enable(spi, 1);
>list_for_each_entry(t, &m->transfers, transfer_list) {
>if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
>@@ -928,17 +927,27 @@ static void omap2_mcspi_work(struct work_struct 
>*work)
>if (t->len > ((cs->word_len + 7) >> 3))
>chconf |= OMAP2_MCSPI_CHCONF_TURBO;
>}
>-
>+ printk("tansfer%s: conf=%x, data=%x\n", t->tx_buf ? "TX" : "RX",
>+ chconf, t->tx_buf ? *(u8 *)(t->tx_buf) : 0);
>mcspi_write_chconf0(spi, chconf);
>
>if (t->len) {
>unsigned count;
>
>/* RX_ONLY mode needs dummy data in TX reg */
>- if (t->tx_buf == NULL)
>+ if (t->tx_buf == NULL) {
>+ u8 rx_data;
>__raw_writel(0, cs->base
>+ OMAP2_MCSPI_TX0);
>
>+ if (mcspi_wait_for_reg_bit(cs->base + OMAP2_MCSPI_CHSTAT0,
>+ OMAP2_MCSPI_CHSTAT_RXS) < 0)
>+ dev_err(&spi->dev, "RXS timed out\n");
>+
>+ rx_data = __raw_readl(cs->base + OMAP2_MCSPI_RX0);
>+ printk("rx_data = %x\n", rx_data);
>+
>+ }
>if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
>count = omap2_mcspi_txrx_dma(spi, t);
>else
>@@ -971,7 +980,7 @@ static void omap2_mcspi_work(struct 
>work_struct *work)
>omap2_mcspi_force_cs(spi, 0);
>
>omap2_mcspi_set_enable(spi, 0);
>-
>+ printk("*****SPI MESSAGE END*****\n");
>m->status = status;
>m->complete(m->context);
>
>-- 
>1.5.6.5
>
>
>
>
>
>
>>> But if we disable this channel after the TX_ONLY  transfer and 
>>> reenable 
>>> it  before  the RX_ONLY  transfer,
>>> the trigger action will take effect and a meaningful data  will be  
>>> transfered to RX register.
>>>
>>> Thanks,
>>> Jason.
>>>
>>>     
>>>>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>>>>> ---
>>>>>  drivers/spi/omap2_mcspi.c |   16 ++++++----------
>>>>>  1 files changed, 6 insertions(+), 10 deletions(-)
>>>>>
>>>>> diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>>>>>     
>>>>>         
>>> [snip]
>>>
>>>     
>
>

From kgene.kim at samsung.com  Tue Jun 29 07:05:18 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 29 Jun 2010 20:05:18 +0900
Subject: [PATCH v5] libata: pata_samsung: Add Samsung PATA controller driver
Message-ID: <1277809518-1122-1-git-send-email-kgene.kim@samsung.com>

From: Abhilash Kesavan <a.kesavan at samsung.com>

Adds support for the Samsung PATA controller. This driver is based on the
Libata subsystem and references the earlier patches sent for IDE subsystem.

Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
Cc: Ben Dooks <ben-linux at fluff.org>
---
 drivers/ata/Kconfig           |    9 +
 drivers/ata/Makefile          |    1 +
 drivers/ata/pata_samsung_cf.c |  728 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 738 insertions(+), 0 deletions(-)
 create mode 100644 drivers/ata/pata_samsung_cf.c

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 73f8833..51e28e7 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -796,6 +796,15 @@ config PATA_RZ1000
 
 	  If unsure, say N.
 
+config PATA_SAMSUNG_CF
+	tristate "Samsung SoC PATA support"
+	depends on SAMSUNG_DEV_IDE
+	help
+	  This option enables basic support for Samsung's S3C/S5P board
+	  PATA controllers via the new ATA layer
+
+	  If unsure, say N.
+
 config PATA_WINBOND_VLB
 	tristate "Winbond W83759A VLB PATA support (Experimental)"
 	depends on ISA && EXPERIMENTAL
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index 7ef89d7..9576776 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -87,6 +87,7 @@ obj-$(CONFIG_PATA_OF_PLATFORM)	+= pata_of_platform.o
 obj-$(CONFIG_PATA_QDI)		+= pata_qdi.o
 obj-$(CONFIG_PATA_RB532)	+= pata_rb532_cf.o
 obj-$(CONFIG_PATA_RZ1000)	+= pata_rz1000.o
+obj-$(CONFIG_PATA_SAMSUNG_CF)	+= pata_samsung_cf.o
 obj-$(CONFIG_PATA_WINBOND_VLB)	+= pata_winbond.o
 
 # Should be last but two libata driver
diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
new file mode 100644
index 0000000..26b96c3
--- /dev/null
+++ b/drivers/ata/pata_samsung_cf.c
@@ -0,0 +1,728 @@
+/*
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com
+ *
+ * PATA driver for Samsung SoCs.
+ * Supports CF Interface in True IDE mode. Currently only PIO mode has been
+ * implemented; UDMA support has to be added.
+ *
+ * Based on:
+ *	PATA driver for AT91SAM9260 Static Memory Controller
+ *	PATA driver for Toshiba SCC controller
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/libata.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include <plat/ata.h>
+#include <plat/regs-ata.h>
+
+#define DRV_NAME "pata_samsung_cf"
+#define DRV_VERSION "0.1"
+
+enum s3c_cpu_type {
+	TYPE_S3C64XX,
+	TYPE_S5PC100,
+	TYPE_S5PV210,
+};
+
+/*
+ * struct s3c_ide_info - S3C PATA instance.
+ * @clk: The clock resource for this controller.
+ * @ide_addr: The area mapped for the hardware registers.
+ * @sfr_addr: The area mapped for the special function registers.
+ * @irq: The IRQ number we are using.
+ * @cpu_type: The exact type of this controller.
+ * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
+ */
+struct s3c_ide_info {
+	struct clk *clk;
+	void __iomem *ide_addr;
+	void __iomem *sfr_addr;
+	unsigned int irq;
+	enum s3c_cpu_type cpu_type;
+	unsigned int fifo_status_reg;
+};
+
+static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
+{
+	u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
+	reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
+	writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
+}
+
+static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
+{
+	/* Select true-ide as the internal operating mode */
+	writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
+		s3c_ide_sfrbase + S3C_CFATA_MUX);
+}
+
+static unsigned long
+pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
+{
+	int t1 = ata->setup;
+	int t2 = ata->act8b;
+	int t2i = ata->rec8b;
+	ulong piotime;
+
+	piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
+
+	return piotime;
+}
+
+static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
+{
+	struct s3c_ide_info *info = ap->host->private_data;
+	struct ata_timing timing;
+	int cycle_time;
+	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
+	ulong piotime;
+
+	/* Enables IORDY if mode requires it */
+	if (ata_pio_need_iordy(adev))
+		ata_cfg |= S3C_ATA_CFG_IORDYEN;
+	else
+		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
+
+	cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
+
+	ata_timing_compute(adev, adev->pio_mode, &timing,
+					cycle_time * 1000, 0);
+
+	piotime = pata_s3c_setup_timing(info, &timing);
+
+	writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
+	writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
+}
+
+/*
+ * Waits until the IDE controller is able to perform next read/write
+ * operation to the disk. Needed for 64XX series boards only.
+ */
+static int wait_for_host_ready(struct s3c_ide_info *info)
+{
+	ulong timeout;
+	void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
+
+	/* wait for maximum of 20 msec */
+	timeout = jiffies + msecs_to_jiffies(20);
+	while (time_before(jiffies, timeout)) {
+		if ((readl(fifo_reg) >> 28) == 0)
+			return 0;
+	}
+	return -EBUSY;
+}
+
+/*
+ * Writes to one of the task file registers.
+ */
+static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
+{
+	struct s3c_ide_info *info = host->private_data;
+
+	wait_for_host_ready(info);
+	writeb(addr, reg);
+}
+
+/*
+ * Reads from one of the task file registers.
+ */
+static u8 ata_inb(struct ata_host *host, void __iomem *reg)
+{
+	struct s3c_ide_info *info = host->private_data;
+	u8 temp;
+
+	wait_for_host_ready(info);
+	(void) readb(reg);
+	wait_for_host_ready(info);
+	temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
+	return temp;
+}
+
+/*
+ * pata_s3c_tf_load - send taskfile registers to host controller
+ */
+static void pata_s3c_tf_load(struct ata_port *ap,
+				const struct ata_taskfile *tf)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
+
+	if (tf->ctl != ap->last_ctl) {
+		ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
+		ap->last_ctl = tf->ctl;
+		ata_wait_idle(ap);
+	}
+
+	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
+		ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
+		ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
+		ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
+		ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
+		ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
+	}
+
+	if (is_addr) {
+		ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
+		ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
+		ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
+		ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
+		ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
+	}
+
+	if (tf->flags & ATA_TFLAG_DEVICE)
+		ata_outb(ap->host, tf->device, ioaddr->device_addr);
+
+	ata_wait_idle(ap);
+}
+
+/*
+ * pata_s3c_tf_read - input device's ATA taskfile shadow registers
+ */
+static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+
+	tf->feature = ata_inb(ap->host, ioaddr->error_addr);
+	tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+	tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+	tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
+	tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
+	tf->device = ata_inb(ap->host, ioaddr->device_addr);
+
+	if (tf->flags & ATA_TFLAG_LBA48) {
+		iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
+		tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
+		tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+		tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+		tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
+		tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
+		iowrite8(tf->ctl, ioaddr->ctl_addr);
+		ap->last_ctl = tf->ctl;
+	}
+}
+
+/*
+ * pata_s3c_exec_command - issue ATA command to host controller
+ */
+static void pata_s3c_exec_command(struct ata_port *ap,
+				const struct ata_taskfile *tf)
+{
+	ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
+	ata_sff_pause(ap);
+}
+
+/*
+ * pata_s3c_check_status - Read device status register
+ */
+static u8 pata_s3c_check_status(struct ata_port *ap)
+{
+	return ata_inb(ap->host, ap->ioaddr.status_addr);
+}
+
+/*
+ * pata_s3c_check_altstatus - Read alternate device status register
+ */
+static u8 pata_s3c_check_altstatus(struct ata_port *ap)
+{
+	return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
+}
+
+/*
+ * pata_s3c_data_xfer - Transfer data by PIO
+ */
+unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char *buf,
+				unsigned int buflen, int rw)
+{
+	struct ata_port *ap = dev->link->ap;
+	struct s3c_ide_info *info = ap->host->private_data;
+	void __iomem *data_addr = ap->ioaddr.data_addr;
+	unsigned int words = buflen >> 1, i;
+	u16 *data_ptr = (u16 *)buf;
+
+	/* Requires wait same as in ata_inb/ata_outb */
+	if (rw == READ)
+		for (i = 0; i < words; i++, data_ptr++) {
+			wait_for_host_ready(info);
+			(void) readw(data_addr);
+			wait_for_host_ready(info);
+			*data_ptr = readw(info->ide_addr
+					+ S3C_ATA_PIO_RDATA);
+		}
+	else
+		for (i = 0; i < words; i++, data_ptr++) {
+			wait_for_host_ready(info);
+			writew(*data_ptr, data_addr);
+		}
+
+	if (buflen & 0x01)
+		dev_err(ap->dev, "unexpected trailing data\n");
+
+	return words << 1;
+}
+
+/*
+ * pata_s3c_dev_select - Select device on ATA bus
+ */
+static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
+{
+	u8 tmp = ATA_DEVICE_OBS;
+
+	if (device != 0)
+		tmp |= ATA_DEV1;
+
+	ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
+	ata_sff_pause(ap);
+}
+
+/*
+ * pata_s3c_devchk - PATA device presence detection
+ */
+static unsigned int pata_s3c_devchk(struct ata_port *ap,
+				unsigned int device)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+	u8 nsect, lbal;
+
+	pata_s3c_dev_select(ap, device);
+
+	ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
+	ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
+
+	ata_outb(ap->host, 0xaa, ioaddr->nsect_addr);
+	ata_outb(ap->host, 0x55, ioaddr->lbal_addr);
+
+	ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
+	ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
+
+	nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+	lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+
+	if ((nsect == 0x55) && (lbal == 0xaa))
+		return 1;	/* we found a device */
+
+	return 0;		/* nothing found */
+}
+
+/*
+ * pata_s3c_wait_after_reset - wait for devices to become ready after reset
+ */
+static int pata_s3c_wait_after_reset(struct ata_link *link,
+		unsigned int devmask, unsigned long deadline)
+{
+	struct ata_port *ap = link->ap;
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+	unsigned int dev0 = devmask & (1 << 0);
+	unsigned int dev1 = devmask & (1 << 1);
+	int rc, ret = 0;
+
+	msleep(ATA_WAIT_AFTER_RESET);
+
+	/* always check readiness of the master device */
+	rc = ata_sff_wait_ready(link, deadline);
+	/* -ENODEV means the odd clown forgot the D7 pulldown resistor
+	 * and TF status is 0xff, bail out on it too.
+	 */
+	if (rc)
+		return rc;
+
+	/* if device 1 was found in ata_devchk, wait for register
+	 * access briefly, then wait for BSY to clear.
+	 */
+	if (dev1) {
+		int i;
+
+		pata_s3c_dev_select(ap, 1);
+
+		/* Wait for register access.  Some ATAPI devices fail
+		 * to set nsect/lbal after reset, so don't waste too
+		 * much time on it.  We're gonna wait for !BSY anyway.
+		 */
+		for (i = 0; i < 2; i++) {
+			u8 nsect, lbal;
+
+			nsect = ata_inb(ap->host, ioaddr->nsect_addr);
+			lbal = ata_inb(ap->host, ioaddr->lbal_addr);
+			if ((nsect == 1) && (lbal == 1))
+				break;
+			msleep(50);	/* give drive a breather */
+		}
+
+		rc = ata_sff_wait_ready(link, deadline);
+		if (rc) {
+			if (rc != -ENODEV)
+				return rc;
+			ret = rc;
+		}
+	}
+
+	/* is all this really necessary? */
+	pata_s3c_dev_select(ap, 0);
+	if (dev1)
+		pata_s3c_dev_select(ap, 1);
+	if (dev0)
+		pata_s3c_dev_select(ap, 0);
+
+	return ret;
+}
+
+/*
+ * pata_s3c_bus_softreset - PATA device software reset
+ */
+static unsigned int pata_s3c_bus_softreset(struct ata_port *ap,
+		unsigned int devmask, unsigned long deadline)
+{
+	struct ata_ioports *ioaddr = &ap->ioaddr;
+
+	/* software reset.  causes dev0 to be selected */
+	ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
+	udelay(20);
+	ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr);
+	udelay(20);
+	ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
+	ap->last_ctl = ap->ctl;
+
+	return pata_s3c_wait_after_reset(&ap->link, devmask, deadline);
+}
+
+/*
+ * pata_s3c_softreset - reset host port via ATA SRST
+ */
+static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
+			 unsigned long deadline)
+{
+	struct ata_port *ap = link->ap;
+	unsigned int devmask = 0;
+	int rc;
+	u8 err;
+
+	/* determine if device 0/1 are present */
+	if (pata_s3c_devchk(ap, 0))
+		devmask |= (1 << 0);
+
+	/* select device 0 again */
+	pata_s3c_dev_select(ap, 0);
+
+	/* issue bus reset */
+	rc = pata_s3c_bus_softreset(ap, devmask, deadline);
+	/* if link is occupied, -ENODEV too is an error */
+	if (rc && rc != -ENODEV) {
+		ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
+		return rc;
+	}
+
+	/* determine by signature whether we have ATA or ATAPI devices */
+	classes[0] = ata_sff_dev_classify(&ap->link.device[0],
+					  devmask & (1 << 0), &err);
+
+	return 0;
+}
+
+/*
+ * pata_s3c_set_devctl - Write device control register
+ */
+static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
+{
+	ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
+}
+
+static struct scsi_host_template pata_s3c_sht = {
+	ATA_PIO_SHT(DRV_NAME),
+};
+
+static struct ata_port_operations pata_s3c_port_ops = {
+	.inherits		= &ata_sff_port_ops,
+	.sff_check_status	= pata_s3c_check_status,
+	.sff_check_altstatus    = pata_s3c_check_altstatus,
+	.sff_tf_load		= pata_s3c_tf_load,
+	.sff_tf_read		= pata_s3c_tf_read,
+	.sff_data_xfer		= pata_s3c_data_xfer,
+	.sff_exec_command	= pata_s3c_exec_command,
+	.sff_dev_select         = pata_s3c_dev_select,
+	.sff_set_devctl         = pata_s3c_set_devctl,
+	.softreset		= pata_s3c_softreset,
+	.set_piomode		= pata_s3c_set_piomode,
+};
+
+static struct ata_port_operations pata_s5p_port_ops = {
+	.inherits		= &ata_sff_port_ops,
+	.set_piomode		= pata_s3c_set_piomode,
+};
+
+static void pata_s3c_enable(void *s3c_ide_regbase, bool state)
+{
+	u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
+	temp = state ? (temp | 1) : (temp & ~1);
+	writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
+}
+
+static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
+{
+	struct ata_host *host = dev_instance;
+	struct s3c_ide_info *info = host->private_data;
+	u32 reg;
+
+	reg = readl(info->ide_addr + S3C_ATA_IRQ);
+	writel(reg, info->ide_addr + S3C_ATA_IRQ);
+
+	return ata_sff_interrupt(irq, dev_instance);
+}
+
+static void pata_s3c_hwinit(struct s3c_ide_info *info,
+				struct s3c_ide_platdata *pdata)
+{
+	switch (info->cpu_type) {
+	case TYPE_S3C64XX:
+		/* Configure as big endian */
+		pata_s3c_cfg_mode(info->sfr_addr);
+		pata_s3c_set_endian(info->ide_addr, 1);
+		pata_s3c_enable(info->ide_addr, true);
+		msleep(100);
+
+		/* Remove IRQ Status */
+		writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
+		writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
+		break;
+
+	case TYPE_S5PC100:
+		pata_s3c_cfg_mode(info->sfr_addr);
+		/* FALLTHROUGH */
+
+	case TYPE_S5PV210:
+		/* Configure as little endian */
+		pata_s3c_set_endian(info->ide_addr, 0);
+		pata_s3c_enable(info->ide_addr, true);
+		msleep(100);
+
+		/* Remove IRQ Status */
+		writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
+		writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
+		break;
+
+	default:
+		BUG();
+	}
+}
+
+static int __init pata_s3c_probe(struct platform_device *pdev)
+{
+	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
+	struct device *dev = &pdev->dev;
+	struct s3c_ide_info *info;
+	struct resource *res;
+	struct ata_port *ap;
+	struct ata_host *host;
+	enum s3c_cpu_type cpu_type;
+	int ret;
+
+	cpu_type = platform_get_device_id(pdev)->driver_data;
+
+	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
+	if (!info) {
+		dev_err(dev, "failed to allocate memory for device data\n");
+		return -ENOMEM;
+	}
+
+	info->irq = platform_get_irq(pdev, 0);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (res == NULL) {
+		dev_err(dev, "failed to get mem resource\n");
+		return -EINVAL;
+	}
+
+	if (!devm_request_mem_region(dev, res->start,
+				resource_size(res), DRV_NAME)) {
+		dev_err(dev, "error requesting register region\n");
+		return -EBUSY;
+	}
+
+	info->ide_addr = devm_ioremap(dev, res->start, resource_size(res));
+	if (!info->ide_addr) {
+		dev_err(dev, "failed to map IO base address\n");
+		return -ENOMEM;
+	}
+
+	info->clk = clk_get(&pdev->dev, "cfcon");
+	if (IS_ERR(info->clk)) {
+		dev_err(dev, "failed to get access to cf controller clock\n");
+		ret = PTR_ERR(info->clk);
+		info->clk = NULL;
+		return ret;
+	}
+
+	clk_enable(info->clk);
+
+	/* init ata host */
+	host = ata_host_alloc(dev, 1);
+	if (!host) {
+		dev_err(dev, "failed to allocate ide host\n");
+		ret = -ENOMEM;
+		goto stop_clk;
+	}
+
+	ap = host->ports[0];
+	ap->flags |= ATA_FLAG_MMIO;
+	ap->pio_mask = ATA_PIO4;
+
+	if (cpu_type == TYPE_S3C64XX) {
+		ap->ops = &pata_s3c_port_ops;
+		info->sfr_addr = info->ide_addr + 0x1800;
+		info->ide_addr += 0x1900;
+		info->fifo_status_reg = 0x94;
+	} else if (cpu_type == TYPE_S5PC100) {
+		ap->ops = &pata_s5p_port_ops;
+		info->sfr_addr = info->ide_addr + 0x1800;
+		info->ide_addr += 0x1900;
+		info->fifo_status_reg = 0x84;
+	} else {
+		ap->ops = &pata_s5p_port_ops;
+		info->fifo_status_reg = 0x84;
+	}
+
+	info->cpu_type = cpu_type;
+
+	if (info->irq <= 0) {
+		ap->flags |= ATA_FLAG_PIO_POLLING;
+		info->irq = 0;
+		ata_port_desc(ap, "no IRQ, using PIO polling\n");
+	}
+
+	ap->ioaddr.cmd_addr =  info->ide_addr + S3C_ATA_CMD;
+	ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
+	ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
+	ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
+	ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
+	ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
+	ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
+	ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
+	ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
+	ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
+	ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
+	ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
+	ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
+
+	ata_port_desc(ap, "mmio cmd 0x%llx ",
+			(unsigned long long)res->start);
+
+	host->private_data = info;
+
+	if (pdata && pdata->setup_gpio)
+		pdata->setup_gpio();
+
+	/* Set endianness and enable the interface */
+	pata_s3c_hwinit(info, pdata);
+
+	platform_set_drvdata(pdev, host);
+
+	return ata_host_activate(host, info->irq,
+			info->irq ? pata_s3c_irq : NULL,
+			0, &pata_s3c_sht);
+
+stop_clk:
+	clk_disable(info->clk);
+	clk_put(info->clk);
+	return ret;
+}
+
+static int __exit pata_s3c_remove(struct platform_device *pdev)
+{
+	struct ata_host *host = platform_get_drvdata(pdev);
+	struct s3c_ide_info *info;
+
+	info = host->private_data;
+	ata_host_detach(host);
+
+	clk_disable(info->clk);
+	clk_put(info->clk);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int pata_s3c_suspend(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ata_host *host = platform_get_drvdata(pdev);
+	pm_message_t state = PMSG_SUSPEND;
+
+	return ata_host_suspend(host, state);
+}
+
+static int pata_s3c_resume(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct ata_host *host = platform_get_drvdata(pdev);
+	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
+	struct s3c_ide_info *info;
+
+	info = host->private_data;
+
+	pata_s3c_hwinit(info, pdata);
+	ata_host_resume(host);
+
+	return 0;
+}
+
+static const struct dev_pm_ops pata_s3c_pm_ops = {
+	.suspend	= pata_s3c_suspend,
+	.resume		= pata_s3c_resume,
+};
+#endif
+
+/* driver device registration */
+static struct platform_device_id pata_s3c_driver_ids[] = {
+	{
+		.name		= "s3c64xx-pata",
+		.driver_data	= TYPE_S3C64XX,
+	}, {
+		.name		= "s5pc100-pata",
+		.driver_data	= TYPE_S5PC100,
+	}, {
+		.name		= "s5pv210-pata",
+		.driver_data	= TYPE_S5PV210,
+	},
+	{ }
+};
+
+MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
+
+static struct platform_driver pata_s3c_driver = {
+	.remove		= __exit_p(pata_s3c_remove),
+	.id_table	= pata_s3c_driver_ids,
+	.driver		= {
+		.name	= DRV_NAME,
+		.owner	= THIS_MODULE,
+#ifdef CONFIG_PM
+		.pm	= &pata_s3c_pm_ops,
+#endif
+	},
+};
+
+static int __init pata_s3c_init(void)
+{
+	return platform_driver_probe(&pata_s3c_driver, pata_s3c_probe);
+}
+
+static void __exit pata_s3c_exit(void)
+{
+	platform_driver_unregister(&pata_s3c_driver);
+}
+
+module_init(pata_s3c_init);
+module_exit(pata_s3c_exit);
+
+MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan at samsung.com>");
+MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
-- 
1.6.6.1



From kgene.kim at samsung.com  Tue Jun 29 07:23:28 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 29 Jun 2010 20:23:28 +0900
Subject: [PATCH 5/8] ARM: S5PV310: Add Timer support
In-Reply-To: <20100628151918.GC3287@debian>
References: <1277476037-8806-1-git-send-email-kgene.kim@samsung.com>
	<1277476037-8806-6-git-send-email-kgene.kim@samsung.com>
	<20100628151918.GC3287@debian>
Message-ID: <00e501cb177d$821387e0$863a97a0$%kim@samsung.com>

Rabin Vincent wrote:
> 
Hi Rabin,

Thanks for your comments. :-)

> On Fri, Jun 25, 2010 at 11:27:14PM +0900, Kukjin Kim wrote:
> > +static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
> > +{
> > +	unsigned long tcon;
> > +
> > +	tcon = __raw_readl(S3C2410_TCON);
> > +
> > +	/* timers reload after counting zero, so reduce the count by 1 */
> > +	tcnt--;
> > +
> > +	printk(KERN_DEBUG "timer tcon=%08lx, tcnt %08lx\n", tcon, tcnt);
> 
> This function is called from set_event().  Do you really want this
> printk every time a tick is programmed?
> 
Yeah, you're right.
Will modify it.

> > +static void __init s5pv310_clocksource_init(void)
> > +{
> > +	unsigned long pclk;
> > +	unsigned long clock_rate;
> > +
> > +	pclk = clk_get_rate(timerclk);
> > +
> > +	clk_set_rate(tdiv2, pclk / 2);
> > +	clk_set_parent(tin2, tdiv2);
> > +
> > +	clock_rate = clk_get_rate(tin2);
> > +
> > +	pwm_clocksource.mult =
> > +		clocksource_khz2mult(clock_rate/1000,
pwm_clocksource.shift);
> > +
> > +	if (clocksource_register(&pwm_clocksource))
> > +		panic("%s: can't register clocksource\n",
> pwm_clocksource.name);
> > +
> > +	s5pv310_pwm_init(2, ~0);
> > +	s5pv310_pwm_start(2, 1);
> > +}
> > +
> 
> It would probably be prudent to start the clocksource before registering
> it, rather than after.

Oh, yes.
Will change it.


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Tue Jun 29 07:32:13 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Tue, 29 Jun 2010 20:32:13 +0900
Subject: [PATCH v4] libata: pata_samsung_cf: Add Samsung PATA controller
	driver
In-Reply-To: <201006250618.37076.marek.vasut@gmail.com>
References: <1276499263-12217-1-git-send-email-kgene.kim@samsung.com>
	<4C22704B.50103@pobox.com>
	<001f01cb1417$dce8f8d0$96baea70$%kim@samsung.com>
	<201006250618.37076.marek.vasut@gmail.com>
Message-ID: <00e701cb177e$bab1e550$3015aff0$%kim@samsung.com>

Marek Vasut wrote:
> 
Hello Marek,

> Dne P? 25. ?ervna 2010 05:38:19 Kukjin Kim napsal(a):
> > Jeff Garzik wrote:
> > > On 06/14/2010 03:07 AM, Kukjin Kim wrote:
> > > > From: Abhilash Kesavan<a.kesavan at samsung.com>
> > > >
> > > > Adds support for the Samsung PATA controller. This driver is based on
> >
> > the
> >
> > > > Libata subsystem and references the earlier patches sent for IDE
> >
> > subsystem.
> >
> > > > Signed-off-by: Abhilash Kesavan<a.kesavan at samsung.com>
> > > > Signed-off-by: Kukjin Kim<kgene.kim at samsung.com>
> > >
> > > Acked-by: Jeff Garzik <jgarzik at redhat.com>
> > >
> > > Send it through the appropriate subsystem tree for this platform...
> >
> > Hi,
> >
> > You mean in my case, appropriate subsystem tree is ARM tree.
> > But I think, as Ben commented, it's better drivers go to upstream via the
> > driver's tree.
> > And of course, I read your comments about this like below...
> > 'platform drivers do not build and/or work without additional platform
> > glue...'
> >
> > Hmm.
> > I'm not sure which way is better...
> 
> I pushed pata_pxa through Eric as well ... go for the linux-arm tree.

Thanks for your help ;-)

But if possible, rmk patch tracking system is better to me.
As Russell's comments, I will send to rmk with Ben's ack.

Thanks.

> Cheers
> >
> > Russell,
> >
> > How do you think?
> > May I send this to your patch tracking system?
> > Or...how should I handle this?
> >

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From tony at atomide.com  Tue Jun 29 07:47:20 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 14:47:20 +0300
Subject: [PATCH 1/6] omap: Disable VGA console for omaps
In-Reply-To: <20100629113229.16008.2931.stgit@baageli.muru.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
Message-ID: <20100629114720.16008.84291.stgit@baageli.muru.com>

Otherwise we have to disable it manually to avoid compile errors.

Cc: linux-fbdev at vger.kernel.org
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 drivers/video/console/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
index 8e8f18d..467a966 100644
--- a/drivers/video/console/Kconfig
+++ b/drivers/video/console/Kconfig
@@ -6,7 +6,7 @@ menu "Console display driver support"
 
 config VGA_CONSOLE
 	bool "VGA text console" if EMBEDDED || !X86
-	depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BLACKFIN && !AVR32 && !MN10300
+	depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && !ARCH_OMAP
 	default y
 	help
 	  Saying Y here will allow you to use Linux in text mode through a



From tony at atomide.com  Tue Jun 29 07:47:32 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 14:47:32 +0300
Subject: [PATCH 4/6] omap2/3/4: Move Kconfig options to mach-omap2/Kconfig
In-Reply-To: <20100629113229.16008.2931.stgit@baageli.muru.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
Message-ID: <20100629114732.16008.56598.stgit@baageli.muru.com>

Move omap2/3/4 specific Kconfig options to mach-omap2/Kconfig

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig |   18 ++++++++++++++++++
 arch/arm/plat-omap/Kconfig  |   18 ------------------
 2 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index e94ee6b..d306aa1 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -2,6 +2,24 @@ if ARCH_OMAP2PLUS
 
 menu "TI OMAP2/3/4 Specific Features"
 
+config ARCH_OMAP2
+	bool "TI OMAP2"
+	depends on ARCH_OMAP2PLUS
+	select CPU_V6
+
+config ARCH_OMAP3
+	bool "TI OMAP3"
+	depends on ARCH_OMAP2PLUS
+	select CPU_V7
+	select USB_ARCH_HAS_EHCI
+	select ARM_L1_CACHE_SHIFT_6
+
+config ARCH_OMAP4
+	bool "TI OMAP4"
+	depends on ARCH_OMAP2PLUS
+	select CPU_V7
+	select ARM_GIC
+
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
 
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index a4e8727..b7a3d80 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -21,24 +21,6 @@ config ARCH_OMAP2PLUS
 	help
 	  "Systems based on omap24xx, omap34xx or omap44xx"
 
-config ARCH_OMAP2
-	bool "TI OMAP2"
-	depends on ARCH_OMAP2PLUS
-	select CPU_V6
-
-config ARCH_OMAP3
-	bool "TI OMAP3"
-	depends on ARCH_OMAP2PLUS
-	select CPU_V7
-	select USB_ARCH_HAS_EHCI
-	select ARM_L1_CACHE_SHIFT_6
-
-config ARCH_OMAP4
-	bool "TI OMAP4"
-	depends on ARCH_OMAP2PLUS
-	select CPU_V7
-	select ARM_GIC
-
 endchoice
 
 comment "OMAP Feature Selections"



From tony at atomide.com  Tue Jun 29 07:47:29 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 14:47:29 +0300
Subject: [PATCH 3/6] omap: Make omap specific features appear under Kconfig
	menu
In-Reply-To: <20100629113229.16008.2931.stgit@baageli.muru.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
Message-ID: <20100629114729.16008.70219.stgit@baageli.muru.com>

This will make Kconfig look nicer for selecting omap processor type

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap1/Kconfig |    7 +++++++
 arch/arm/mach-omap2/Kconfig |    7 +++++++
 arch/arm/plat-omap/Kconfig  |    2 +-
 3 files changed, 15 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap1/Kconfig b/arch/arm/mach-omap1/Kconfig
index b18d7c2..c911cdb 100644
--- a/arch/arm/mach-omap1/Kconfig
+++ b/arch/arm/mach-omap1/Kconfig
@@ -1,3 +1,7 @@
+if ARCH_OMAP1
+
+menu "TI OMAP1 specific features"
+
 comment "OMAP Core Type"
 	depends on ARCH_OMAP1
 
@@ -237,3 +241,6 @@ config OMAP_ARM_30MHZ
 	help
           Enable 30MHz clock for OMAP CPU. If unsure, say N.
 
+endmenu
+
+endif
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f67f037..e94ee6b 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -1,3 +1,7 @@
+if ARCH_OMAP2PLUS
+
+menu "TI OMAP2/3/4 Specific Features"
+
 comment "OMAP Core Type"
 	depends on ARCH_OMAP2
 
@@ -186,3 +190,6 @@ config OMAP3_SDRC_AC_TIMING
 	  wish to say no.  Selecting yes without understanding what is
 	  going on could result in system crashes;
 
+endmenu
+
+endif
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 3e2e7a8..a4e8727 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -1,6 +1,6 @@
 if ARCH_OMAP
 
-menu "TI OMAP Implementations"
+menu "TI OMAP Common Features"
 
 config ARCH_OMAP_OTG
 	bool



From tony at atomide.com  Tue Jun 29 07:47:26 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 14:47:26 +0300
Subject: [PATCH 2/6] omap: Use 32KiHZ timer by default
In-Reply-To: <20100629113229.16008.2931.stgit@baageli.muru.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
Message-ID: <20100629114725.16008.68154.stgit@baageli.muru.com>

Use 32KiHZ timer by default as this is available on all omaps
except 15xx based systems.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/plat-omap/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 78b49a6..3e2e7a8 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -120,7 +120,7 @@ config OMAP_IOMMU_DEBUG
 
 choice
 	prompt "System timer"
-	default OMAP_MPU_TIMER
+	default OMAP_32K_TIMER if !ARCH_OMAP15XX
 
 config OMAP_MPU_TIMER
 	bool "Use mpu timer"



From tony at atomide.com  Tue Jun 29 07:47:35 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 14:47:35 +0300
Subject: [PATCH 5/6] omap2/3/4: Select all omaps and boards by default
In-Reply-To: <20100629113229.16008.2931.stgit@baageli.muru.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
Message-ID: <20100629114735.16008.76563.stgit@baageli.muru.com>

Select all omaps and boards by default

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig |   28 ++++++++++++++++++++++++++++
 1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index d306aa1..4802988 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -5,17 +5,20 @@ menu "TI OMAP2/3/4 Specific Features"
 config ARCH_OMAP2
 	bool "TI OMAP2"
 	depends on ARCH_OMAP2PLUS
+	default y
 	select CPU_V6
 
 config ARCH_OMAP3
 	bool "TI OMAP3"
 	depends on ARCH_OMAP2PLUS
+	default y
 	select CPU_V7
 	select USB_ARCH_HAS_EHCI
 	select ARM_L1_CACHE_SHIFT_6
 
 config ARCH_OMAP4
 	bool "TI OMAP4"
+	default y
 	depends on ARCH_OMAP2PLUS
 	select CPU_V7
 	select ARM_GIC
@@ -26,17 +29,20 @@ comment "OMAP Core Type"
 config ARCH_OMAP2420
 	bool "OMAP2420 support"
 	depends on ARCH_OMAP2
+	default y
 	select OMAP_DM_TIMER
 	select ARCH_OMAP_OTG
 
 config ARCH_OMAP2430
 	bool "OMAP2430 support"
 	depends on ARCH_OMAP2
+	default y
 	select ARCH_OMAP_OTG
 
 config ARCH_OMAP3430
 	bool "OMAP3430 support"
 	depends on ARCH_OMAP3
+	default y
 	select ARCH_OMAP_OTG
 
 config OMAP_PACKAGE_ZAF
@@ -63,6 +69,7 @@ comment "OMAP Board Type"
 config MACH_OMAP_GENERIC
 	bool "Generic OMAP board"
 	depends on ARCH_OMAP2
+	default y
 
 config MACH_OMAP2_TUSB6010
 	bool
@@ -72,63 +79,75 @@ config MACH_OMAP2_TUSB6010
 config MACH_OMAP_H4
 	bool "OMAP 2420 H4 board"
 	depends on ARCH_OMAP2
+	default y
 	select OMAP_PACKAGE_ZAF
 	select OMAP_DEBUG_DEVICES
 
 config MACH_OMAP_APOLLON
 	bool "OMAP 2420 Apollon board"
 	depends on ARCH_OMAP2
+	default y
 	select OMAP_PACKAGE_ZAC
 
 config MACH_OMAP_2430SDP
 	bool "OMAP 2430 SDP board"
 	depends on ARCH_OMAP2
+	default y
 	select OMAP_PACKAGE_ZAC
 
 config MACH_OMAP3_BEAGLE
 	bool "OMAP3 BEAGLE board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CBB
 
 config MACH_DEVKIT8000
 	bool "DEVKIT8000 board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CUS
 	select OMAP_MUX
 
 config MACH_OMAP_LDP
 	bool "OMAP3 LDP board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CBB
 
 config MACH_OVERO
 	bool "Gumstix Overo board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CBB
 
 config MACH_OMAP3EVM
 	bool "OMAP 3530 EVM board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CBB
 
 config MACH_OMAP3517EVM
 	bool "OMAP3517/ AM3517 EVM board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CBB
 
 config MACH_OMAP3_PANDORA
 	bool "OMAP3 Pandora"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CBB
 
 config MACH_OMAP3_TOUCHBOOK
 	bool "OMAP3 Touch Book"
 	depends on ARCH_OMAP3
+	default y
 	select BACKLIGHT_CLASS_DEVICE
 
 config MACH_OMAP_3430SDP
 	bool "OMAP 3430 SDP board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CBB
 
 config MACH_NOKIA_N800
@@ -143,6 +162,7 @@ config MACH_NOKIA_N810_WIMAX
 config MACH_NOKIA_N8X0
 	bool "Nokia N800/N810"
 	depends on ARCH_OMAP2420
+	default y
 	select OMAP_PACKAGE_ZAC
 	select MACH_NOKIA_N800
 	select MACH_NOKIA_N810
@@ -151,42 +171,50 @@ config MACH_NOKIA_N8X0
 config MACH_NOKIA_RX51
 	bool "Nokia RX-51 board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_ZOOM2
 	bool "OMAP3 Zoom2 board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CBB
 
 config MACH_OMAP_ZOOM3
 	bool "OMAP3630 Zoom3 board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CBP
 
 config MACH_CM_T35
 	bool "CompuLab CM-T35 module"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CUS
 	select OMAP_MUX
 
 config MACH_IGEP0020
 	bool "IGEP v2 board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CBB
 
 config MACH_SBC3530
 	bool "OMAP3 SBC STALKER board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CUS
 	select OMAP_MUX
 
 config MACH_OMAP_3630SDP
 	bool "OMAP3630 SDP board"
 	depends on ARCH_OMAP3
+	default y
 	select OMAP_PACKAGE_CBP
 
 config MACH_OMAP_4430SDP
 	bool "OMAP 4430 SDP board"
+	default y
 	depends on ARCH_OMAP4
 
 config OMAP3_EMU



From tony at atomide.com  Tue Jun 29 07:47:38 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 14:47:38 +0300
Subject: [PATCH 6/6] omap2/3/4: Add Kconfig option to compile in typical omap
	features
In-Reply-To: <20100629113229.16008.2931.stgit@baageli.muru.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
Message-ID: <20100629114738.16008.62006.stgit@baageli.muru.com>

This produces a sane config that's suitable for using as the
base for most omap2/3/4 boards.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4802988..84fecd0 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -2,6 +2,27 @@ if ARCH_OMAP2PLUS
 
 menu "TI OMAP2/3/4 Specific Features"
 
+config ARCH_OMAP2PLUS_TYPICAL
+	bool "Typical OMAP configuration"
+	default y
+	select AEABI
+	select REGULATOR
+	select PM
+	select PM_RUNTIME
+	select VFP
+	select NEON if ARCH_OMAP3 || ARCH_OMAP4
+	select SERIAL_8250
+	select SERIAL_CORE_CONSOLE
+	select SERIAL_8250_CONSOLE
+	select I2C
+	select I2C_OMAP
+	select MFD
+	select MENELAUS if ARCH_OMAP2
+	select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
+	select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
+	help
+	  Compile a kernel suitable for booting most boards
+
 config ARCH_OMAP2
 	bool "TI OMAP2"
 	depends on ARCH_OMAP2PLUS



From tony at atomide.com  Tue Jun 29 07:47:08 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 14:47:08 +0300
Subject: [PATCH 0/6] omap Kconfig improvments for 2.6.36 merge window
Message-ID: <20100629113229.16008.2931.stgit@baageli.muru.com>

Hi all,

Here are some Kconfig improvments to produce a mostly sane .config for
omap2/3/4 without a defconfig. This assumes that CONFIG_ARCH_OMAP is
selected, for example with:

$ echo "CONFIG_ARCH_OMAP=y" > .config && yes "" | ARCH=arm make oldconfig

or

$ rm .config; ARCH=arm make xconfig, then select System Type -> TI OMAP

Regards,

Tony

---

Tony Lindgren (6):
      omap: Disable VGA console for omaps
      omap: Use 32KiHZ timer by default
      omap: Make omap specific features appear under Kconfig menu
      omap2/3/4: Move Kconfig options to mach-omap2/Kconfig
      omap2/3/4: Select all omaps and boards by default
      omap2/3/4: Add Kconfig option to compile in typical omap features


 arch/arm/mach-omap1/Kconfig   |    7 ++++
 arch/arm/mach-omap2/Kconfig   |   74 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/plat-omap/Kconfig    |   22 +-----------
 drivers/video/console/Kconfig |    2 +
 4 files changed, 84 insertions(+), 21 deletions(-)

-- 
Signature


From tony at atomide.com  Tue Jun 29 07:54:06 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 14:54:06 +0300
Subject: [PATCH 0/4] Platform init changes for old FS USB code for 2.6.36
	merge window
Message-ID: <20100629115056.17702.56622.stgit@baageli.muru.com>

Hi all,

Here are some FS USB platform init changes to allow further improvment
of the code for muxing, register access and hwmod.

This set mostly moves the code around to split it between mach-omap1
and mach-omap2.

Regards,

Tony

---

Tony Lindgren (4):
      omap: Separate out omap2 FS USB platform init functions
      omap: Move omap2 FS USB platform init code into mach-omap2/usb-fs.c
      omap: Enable interface clock for omap2 FS USB
      omap: Move omap1 USB platform init code into mach-omap1/usb.c


 arch/arm/mach-omap1/Makefile            |    3 
 arch/arm/mach-omap1/board-ams-delta.c   |    2 
 arch/arm/mach-omap1/board-generic.c     |    4 
 arch/arm/mach-omap1/board-h2.c          |    2 
 arch/arm/mach-omap1/board-h3.c          |    2 
 arch/arm/mach-omap1/board-htcherald.c   |    2 
 arch/arm/mach-omap1/board-innovator.c   |    4 
 arch/arm/mach-omap1/board-nokia770.c    |    2 
 arch/arm/mach-omap1/board-osk.c         |    2 
 arch/arm/mach-omap1/board-palmte.c      |    2 
 arch/arm/mach-omap1/board-palmtt.c      |    2 
 arch/arm/mach-omap1/board-palmz71.c     |    2 
 arch/arm/mach-omap1/board-sx1.c         |    2 
 arch/arm/mach-omap1/board-voiceblue.c   |    2 
 arch/arm/mach-omap1/usb.c               |  530 ++++++++++++++++++++++++++
 arch/arm/mach-omap2/Makefile            |    2 
 arch/arm/mach-omap2/board-2430sdp.c     |    2 
 arch/arm/mach-omap2/board-apollon.c     |    2 
 arch/arm/mach-omap2/board-h4.c          |    2 
 arch/arm/mach-omap2/usb-fs.c            |  356 +++++++++++++++++
 arch/arm/plat-omap/include/plat/board.h |    8 
 arch/arm/plat-omap/include/plat/usb.h   |   49 ++
 arch/arm/plat-omap/usb.c                |  644 +------------------------------
 23 files changed, 981 insertions(+), 647 deletions(-)
 create mode 100644 arch/arm/mach-omap1/usb.c
 create mode 100644 arch/arm/mach-omap2/usb-fs.c

-- 
Signature


From tony at atomide.com  Tue Jun 29 07:54:11 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 14:54:11 +0300
Subject: [PATCH 1/4] omap: Separate out omap2 FS USB platform init functions
In-Reply-To: <20100629115056.17702.56622.stgit@baageli.muru.com>
References: <20100629115056.17702.56622.stgit@baageli.muru.com>
Message-ID: <20100629115411.17702.19570.stgit@baageli.muru.com>

We want to split old FS USB platform init code and stop doing pin multiplexing
under plat-omap. First move 24xx specific init code into omap2_usb[012]_init
functions.

Cc: David Brownell <dbrownell at users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/plat-omap/usb.c |  252 +++++++++++++++++++++++++++++-----------------
 1 files changed, 157 insertions(+), 95 deletions(-)

diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index d3bf17c..9c4929a 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -115,15 +115,56 @@ static void omap2_usb2_enable_5pinunitll(void)
 	omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
 }
 
+static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device)
+{
+	u32	syscon1 = 0;
+
+	omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
+
+	if (nwires == 0)
+		return 0;
+
+	if (is_device)
+		omap_cfg_reg(J20_24XX_USB0_PUEN);
+
+	omap_cfg_reg(K18_24XX_USB0_DAT);
+	omap_cfg_reg(K19_24XX_USB0_TXEN);
+	omap_cfg_reg(J14_24XX_USB0_SE0);
+	if (nwires != 3)
+		omap_cfg_reg(J18_24XX_USB0_RCV);
+
+	switch (nwires) {
+	case 3:
+		syscon1 = 2;
+		omap2_usb_devconf_set(0, USB_BIDIR);
+		break;
+	case 4:
+		syscon1 = 1;
+		omap2_usb_devconf_set(0, USB_BIDIR);
+		break;
+	case 6:
+		syscon1 = 3;
+		omap_cfg_reg(J19_24XX_USB0_VP);
+		omap_cfg_reg(K20_24XX_USB0_VM);
+		omap2_usb_devconf_set(0, USB_UNIDIR);
+		break;
+	default:
+		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+			0, nwires);
+	}
+
+	return syscon1 << 16;
+}
+
 static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 {
 	u32	syscon1 = 0;
 
 	if (cpu_is_omap24xx())
-		omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
+		return omap2_usb0_init(nwires, is_device);
 
 	if (nwires == 0) {
-		if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
+		if (!cpu_is_omap15xx()) {
 			u32 l;
 
 			/* pulldown D+/D- */
@@ -135,9 +176,7 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 	}
 
 	if (is_device) {
-		if (cpu_is_omap24xx())
-			omap_cfg_reg(J20_24XX_USB0_PUEN);
-		else if (cpu_is_omap7xx()) {
+		if (cpu_is_omap7xx()) {
 			omap_cfg_reg(AA17_7XX_USB_DM);
 			omap_cfg_reg(W16_7XX_USB_PU_EN);
 			omap_cfg_reg(W17_7XX_USB_VBUSI);
@@ -147,8 +186,7 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 			omap_cfg_reg(W4_USB_PUEN);
 	}
 
-	/* internal transceiver (unavailable on 17xx, 24xx) */
-	if (!cpu_class_is_omap2() && nwires == 2) {
+	if (nwires == 2) {
 		u32 l;
 
 		// omap_cfg_reg(P9_USB_DP);
@@ -183,26 +221,18 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 		return 0;
 	}
 
-	if (cpu_is_omap24xx()) {
-		omap_cfg_reg(K18_24XX_USB0_DAT);
-		omap_cfg_reg(K19_24XX_USB0_TXEN);
-		omap_cfg_reg(J14_24XX_USB0_SE0);
-		if (nwires != 3)
-			omap_cfg_reg(J18_24XX_USB0_RCV);
-	} else {
-		omap_cfg_reg(V6_USB0_TXD);
-		omap_cfg_reg(W9_USB0_TXEN);
-		omap_cfg_reg(W5_USB0_SE0);
-		if (nwires != 3)
-			omap_cfg_reg(Y5_USB0_RCV);
-	}
+	omap_cfg_reg(V6_USB0_TXD);
+	omap_cfg_reg(W9_USB0_TXEN);
+	omap_cfg_reg(W5_USB0_SE0);
+	if (nwires != 3)
+		omap_cfg_reg(Y5_USB0_RCV);
 
 	/* NOTE:  SPEED and SUSP aren't configured here.  OTG hosts
 	 * may be able to use I2C requests to set those bits along
 	 * with VBUS switching and overcurrent detection.
 	 */
 
-	if (cpu_class_is_omap1() && nwires != 6) {
+	if (nwires != 6) {
 		u32 l;
 
 		l = omap_readl(USB_TRANSCEIVER_CTRL);
@@ -213,21 +243,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 	switch (nwires) {
 	case 3:
 		syscon1 = 2;
-		if (cpu_is_omap24xx())
-			omap2_usb_devconf_set(0, USB_BIDIR);
 		break;
 	case 4:
 		syscon1 = 1;
-		if (cpu_is_omap24xx())
-			omap2_usb_devconf_set(0, USB_BIDIR);
 		break;
 	case 6:
 		syscon1 = 3;
-		if (cpu_is_omap24xx()) {
-			omap_cfg_reg(J19_24XX_USB0_VP);
-			omap_cfg_reg(K20_24XX_USB0_VM);
-			omap2_usb_devconf_set(0, USB_UNIDIR);
-		} else {
+		{
 			u32 l;
 
 			omap_cfg_reg(AA9_USB0_VP);
@@ -244,30 +266,66 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 	return syscon1 << 16;
 }
 
+static u32 __init omap2_usb1_init(unsigned nwires)
+{
+	u32	syscon1 = 0;
+
+	omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
+
+	if (nwires == 0)
+		return 0;
+
+	/* NOTE:  board-specific code must set up pin muxing for usb1,
+	 * since each signal could come out on either of two balls.
+	 */
+
+	switch (nwires) {
+	case 2:
+		/* NOTE: board-specific code must override this setting if
+		 * this TLL link is not using DP/DM
+		 */
+		syscon1 = 1;
+		omap2_usb_devconf_set(1, USB_BIDIR_TLL);
+		break;
+	case 3:
+		syscon1 = 2;
+		omap2_usb_devconf_set(1, USB_BIDIR);
+		break;
+	case 4:
+		syscon1 = 1;
+		omap2_usb_devconf_set(1, USB_BIDIR);
+		break;
+	case 6:
+	default:
+		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+			1, nwires);
+	}
+
+	return syscon1 << 20;
+}
+
 static u32 __init omap_usb1_init(unsigned nwires)
 {
 	u32	syscon1 = 0;
 
-	if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
+	if (cpu_is_omap24xx())
+		return omap2_usb1_init(nwires);
+
+	if (!cpu_is_omap15xx() && nwires != 6) {
 		u32 l;
 
 		l = omap_readl(USB_TRANSCEIVER_CTRL);
 		l &= ~CONF_USB1_UNI_R;
 		omap_writel(l, USB_TRANSCEIVER_CTRL);
 	}
-	if (cpu_is_omap24xx())
-		omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
-
 	if (nwires == 0)
 		return 0;
 
 	/* external transceiver */
-	if (cpu_class_is_omap1()) {
-		omap_cfg_reg(USB1_TXD);
-		omap_cfg_reg(USB1_TXEN);
-		if (nwires != 3)
-			omap_cfg_reg(USB1_RCV);
-	}
+	omap_cfg_reg(USB1_TXD);
+	omap_cfg_reg(USB1_TXEN);
+	if (nwires != 3)
+		omap_cfg_reg(USB1_RCV);
 
 	if (cpu_is_omap15xx()) {
 		omap_cfg_reg(USB1_SEO);
@@ -280,10 +338,6 @@ static u32 __init omap_usb1_init(unsigned nwires)
 	} else if (cpu_is_omap1710()) {
 		omap_cfg_reg(R13_1710_USB1_SE0);
 		// SUSP
-	} else if (cpu_is_omap24xx()) {
-		/* NOTE:  board-specific code must set up pin muxing for usb1,
-		 * since each signal could come out on either of two balls.
-		 */
 	} else {
 		pr_debug("usb%d cpu unrecognized\n", 1);
 		return 0;
@@ -291,27 +345,14 @@ static u32 __init omap_usb1_init(unsigned nwires)
 
 	switch (nwires) {
 	case 2:
-		if (!cpu_is_omap24xx())
-			goto bad;
-		/* NOTE: board-specific code must override this setting if
-		 * this TLL link is not using DP/DM
-		 */
-		syscon1 = 1;
-		omap2_usb_devconf_set(1, USB_BIDIR_TLL);
-		break;
+		goto bad;
 	case 3:
 		syscon1 = 2;
-		if (cpu_is_omap24xx())
-			omap2_usb_devconf_set(1, USB_BIDIR);
 		break;
 	case 4:
 		syscon1 = 1;
-		if (cpu_is_omap24xx())
-			omap2_usb_devconf_set(1, USB_BIDIR);
 		break;
 	case 6:
-		if (cpu_is_omap24xx())
-			goto bad;
 		syscon1 = 3;
 		omap_cfg_reg(USB1_VP);
 		omap_cfg_reg(USB1_VM);
@@ -331,20 +372,70 @@ bad:
 	return syscon1 << 20;
 }
 
-static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
+static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
 {
 	u32	syscon1 = 0;
 
-	if (cpu_is_omap24xx()) {
-		omap2_usb2_disable_5pinbitll();
-		alt_pingroup = 0;
+	omap2_usb2_disable_5pinbitll();
+	alt_pingroup = 0;
+
+	/* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
+	if (alt_pingroup || nwires == 0)
+		return 0;
+
+	omap_cfg_reg(Y11_24XX_USB2_DAT);
+	omap_cfg_reg(AA10_24XX_USB2_SE0);
+	if (nwires > 2)
+		omap_cfg_reg(AA12_24XX_USB2_TXEN);
+	if (nwires > 3)
+		omap_cfg_reg(AA6_24XX_USB2_RCV);
+
+	switch (nwires) {
+	case 2:
+		/* NOTE: board-specific code must override this setting if
+		 * this TLL link is not using DP/DM
+		 */
+		syscon1 = 1;
+		omap2_usb_devconf_set(2, USB_BIDIR_TLL);
+		break;
+	case 3:
+		syscon1 = 2;
+		omap2_usb_devconf_set(2, USB_BIDIR);
+		break;
+	case 4:
+		syscon1 = 1;
+		omap2_usb_devconf_set(2, USB_BIDIR);
+		break;
+	case 5:
+		omap_cfg_reg(AA4_24XX_USB2_TLLSE0);
+		/* NOTE: board-specific code must override this setting if
+		 * this TLL link is not using DP/DM.  Something must also
+		 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
+		 */
+		syscon1 = 3;
+		omap2_usb2_enable_5pinunitll();
+		break;
+	case 6:
+	default:
+		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+			2, nwires);
 	}
 
+	return syscon1 << 24;
+}
+
+static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
+{
+	u32	syscon1 = 0;
+
+	if (cpu_is_omap24xx())
+		return omap2_usb2_init(nwires, alt_pingroup);
+
 	/* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
 	if (alt_pingroup || nwires == 0)
 		return 0;
 
-	if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
+	if (!cpu_is_omap15xx() && nwires != 6) {
 		u32 l;
 
 		l = omap_readl(USB_TRANSCEIVER_CTRL);
@@ -367,53 +458,24 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
 		if (nwires != 3)
 			omap_cfg_reg(Y5_USB2_RCV);
 		// FIXME omap_cfg_reg(USB2_SPEED);
-	} else if (cpu_is_omap24xx()) {
-		omap_cfg_reg(Y11_24XX_USB2_DAT);
-		omap_cfg_reg(AA10_24XX_USB2_SE0);
-		if (nwires > 2)
-			omap_cfg_reg(AA12_24XX_USB2_TXEN);
-		if (nwires > 3)
-			omap_cfg_reg(AA6_24XX_USB2_RCV);
 	} else {
 		pr_debug("usb%d cpu unrecognized\n", 1);
 		return 0;
 	}
-	// if (cpu_class_is_omap1()) omap_cfg_reg(USB2_SUSP);
+	// omap_cfg_reg(USB2_SUSP);
 
 	switch (nwires) {
 	case 2:
-		if (!cpu_is_omap24xx())
-			goto bad;
-		/* NOTE: board-specific code must override this setting if
-		 * this TLL link is not using DP/DM
-		 */
-		syscon1 = 1;
-		omap2_usb_devconf_set(2, USB_BIDIR_TLL);
-		break;
+		goto bad;
 	case 3:
 		syscon1 = 2;
-		if (cpu_is_omap24xx())
-			omap2_usb_devconf_set(2, USB_BIDIR);
 		break;
 	case 4:
 		syscon1 = 1;
-		if (cpu_is_omap24xx())
-			omap2_usb_devconf_set(2, USB_BIDIR);
 		break;
 	case 5:
-		if (!cpu_is_omap24xx())
-			goto bad;
-		omap_cfg_reg(AA4_24XX_USB2_TLLSE0);
-		/* NOTE: board-specific code must override this setting if
-		 * this TLL link is not using DP/DM.  Something must also
-		 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
-		 */
-		syscon1 = 3;
-		omap2_usb2_enable_5pinunitll();
-		break;
+		goto bad;
 	case 6:
-		if (cpu_is_omap24xx())
-			goto bad;
 		syscon1 = 3;
 		if (cpu_is_omap15xx()) {
 			omap_cfg_reg(USB2_VP);



From tony at atomide.com  Tue Jun 29 07:54:23 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 14:54:23 +0300
Subject: [PATCH 3/4] omap: Enable interface clock for omap2 FS USB
In-Reply-To: <20100629115056.17702.56622.stgit@baageli.muru.com>
References: <20100629115056.17702.56622.stgit@baageli.muru.com>
Message-ID: <20100629115423.17702.36906.stgit@baageli.muru.com>

Looks like this code was only working on boards that had
the usb_l4_ick enabled in the bootloader.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/usb-fs.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
index f63e576..a445519 100644
--- a/arch/arm/mach-omap2/usb-fs.c
+++ b/arch/arm/mach-omap2/usb-fs.c
@@ -24,6 +24,8 @@
 #include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/err.h>
 
 #include <asm/irq.h>
 
@@ -330,9 +332,16 @@ static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
 
 void __init omap2_usbfs_init(struct omap_usb_config *pdata)
 {
+	struct clk *ick;
+
 	if (!cpu_is_omap24xx())
 		return;
 
+	ick = clk_get(NULL, "usb_l4_ick");
+	if (IS_ERR(ick))
+		return;
+
+	clk_enable(ick);
 	pdata->usb0_init = omap2_usb0_init;
 	pdata->usb1_init = omap2_usb1_init;
 	pdata->usb2_init = omap2_usb2_init;
@@ -340,6 +349,8 @@ void __init omap2_usbfs_init(struct omap_usb_config *pdata)
 	ohci_device_init(pdata);
 	otg_device_init(pdata);
 	omap_otg_init(pdata);
+	clk_disable(ick);
+	clk_put(ick);
 }
 
 #endif



From tony at atomide.com  Tue Jun 29 07:54:17 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 14:54:17 +0300
Subject: [PATCH 2/4] omap: Move omap2 FS USB platform init code into
	mach-omap2/usb-fs.c
In-Reply-To: <20100629115056.17702.56622.stgit@baageli.muru.com>
References: <20100629115056.17702.56622.stgit@baageli.muru.com>
Message-ID: <20100629115417.17702.81009.stgit@baageli.muru.com>

Move omap2 FS USB platform init code into mach-omap2/usb-fs.c. This will
allow further work later on to use omap hwmod for initializing the
device.

Cc: David Brownell <dbrownell at users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Makefile            |    2 
 arch/arm/mach-omap2/board-2430sdp.c     |    2 
 arch/arm/mach-omap2/board-apollon.c     |    2 
 arch/arm/mach-omap2/board-h4.c          |    2 
 arch/arm/mach-omap2/usb-fs.c            |  345 +++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/board.h |    8 +
 arch/arm/plat-omap/include/plat/usb.h   |    7 +
 arch/arm/plat-omap/usb.c                |  267 ++++++------------------
 8 files changed, 429 insertions(+), 206 deletions(-)
 create mode 100644 arch/arm/mach-omap2/usb-fs.c

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ea52b03..0416643 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -146,6 +146,8 @@ obj-$(CONFIG_MACH_OMAP3517EVM)		+= board-am3517evm.o
 obj-$(CONFIG_MACH_SBC3530)		+= board-omap3stalker.o \
 					   hsmmc.o
 # Platform specific device init code
+usbfs-$(CONFIG_ARCH_OMAP_OTG)		:= usb-fs.o
+obj-y					+= $(usbfs-m) $(usbfs-y)
 obj-y					+= usb-musb.o
 obj-$(CONFIG_MACH_OMAP2_TUSB6010)	+= usb-tusb6010.o
 obj-y					+= usb-ehci.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index a11a575..ec920c9 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -226,7 +226,7 @@ static void __init omap_2430sdp_init(void)
 	platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
 	omap_serial_init();
 	omap2_hsmmc_init(mmc);
-	omap_usb_init(&sdp2430_usb_config);
+	omap2_usbfs_init(&sdp2430_usb_config);
 	usb_musb_init(&musb_board_data);
 	board_smc91x_init();
 
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index aa69fb9..987b24d 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -306,7 +306,7 @@ static void __init apollon_usb_init(void)
 	omap_cfg_reg(P21_242X_GPIO12);
 	gpio_request(12, "USB suspend");
 	gpio_direction_output(12, 0);
-	omap_usb_init(&apollon_usb_config);
+	omap2_usbfs_init(&apollon_usb_config);
 }
 
 static void __init omap_apollon_init(void)
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 0665f2c..54a231c 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -362,7 +362,7 @@ static void __init omap_h4_init(void)
 			ARRAY_SIZE(h4_i2c_board_info));
 
 	platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
-	omap_usb_init(&h4_usb_config);
+	omap2_usbfs_init(&h4_usb_config);
 	omap_serial_init();
 }
 
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
new file mode 100644
index 0000000..f63e576
--- /dev/null
+++ b/arch/arm/mach-omap2/usb-fs.c
@@ -0,0 +1,345 @@
+/*
+ * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx
+ *
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <asm/irq.h>
+
+#include <plat/control.h>
+#include <plat/mux.h>
+#include <plat/usb.h>
+#include <plat/board.h>
+
+#define INT_USB_IRQ_GEN		INT_24XX_USB_IRQ_GEN
+#define INT_USB_IRQ_NISO	INT_24XX_USB_IRQ_NISO
+#define INT_USB_IRQ_ISO		INT_24XX_USB_IRQ_ISO
+#define INT_USB_IRQ_HGEN	INT_24XX_USB_IRQ_HGEN
+#define INT_USB_IRQ_OTG		INT_24XX_USB_IRQ_OTG
+
+#if defined(CONFIG_ARCH_OMAP2)
+
+#ifdef	CONFIG_USB_GADGET_OMAP
+
+static struct resource udc_resources[] = {
+	/* order is significant! */
+	{		/* registers */
+		.start		= UDC_BASE,
+		.end		= UDC_BASE + 0xff,
+		.flags		= IORESOURCE_MEM,
+	}, {		/* general IRQ */
+		.start		= INT_USB_IRQ_GEN,
+		.flags		= IORESOURCE_IRQ,
+	}, {		/* PIO IRQ */
+		.start		= INT_USB_IRQ_NISO,
+		.flags		= IORESOURCE_IRQ,
+	}, {		/* SOF IRQ */
+		.start		= INT_USB_IRQ_ISO,
+		.flags		= IORESOURCE_IRQ,
+	},
+};
+
+static u64 udc_dmamask = ~(u32)0;
+
+static struct platform_device udc_device = {
+	.name		= "omap_udc",
+	.id		= -1,
+	.dev = {
+		.dma_mask		= &udc_dmamask,
+		.coherent_dma_mask	= 0xffffffff,
+	},
+	.num_resources	= ARRAY_SIZE(udc_resources),
+	.resource	= udc_resources,
+};
+
+static inline void udc_device_init(struct omap_usb_config *pdata)
+{
+	pdata->udc_device = &udc_device;
+}
+
+#else
+
+static inline void udc_device_init(struct omap_usb_config *pdata)
+{
+}
+
+#endif
+
+#if	defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = ~(u32)0;
+
+static struct resource ohci_resources[] = {
+	{
+		.start	= OMAP_OHCI_BASE,
+		.end	= OMAP_OHCI_BASE + 0xff,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_USB_IRQ_HGEN,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device ohci_device = {
+	.name			= "ohci",
+	.id			= -1,
+	.dev = {
+		.dma_mask		= &ohci_dmamask,
+		.coherent_dma_mask	= 0xffffffff,
+	},
+	.num_resources	= ARRAY_SIZE(ohci_resources),
+	.resource		= ohci_resources,
+};
+
+static inline void ohci_device_init(struct omap_usb_config *pdata)
+{
+	pdata->ohci_device = &ohci_device;
+}
+
+#else
+
+static inline void ohci_device_init(struct omap_usb_config *pdata)
+{
+}
+
+#endif
+
+#if	defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
+
+static struct resource otg_resources[] = {
+	/* order is significant! */
+	{
+		.start		= OTG_BASE,
+		.end		= OTG_BASE + 0xff,
+		.flags		= IORESOURCE_MEM,
+	}, {
+		.start		= INT_USB_IRQ_OTG,
+		.flags		= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device otg_device = {
+	.name		= "omap_otg",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(otg_resources),
+	.resource	= otg_resources,
+};
+
+static inline void otg_device_init(struct omap_usb_config *pdata)
+{
+	pdata->otg_device = &otg_device;
+}
+
+#else
+
+static inline void otg_device_init(struct omap_usb_config *pdata)
+{
+}
+
+#endif
+
+static void omap2_usb_devconf_clear(u8 port, u32 mask)
+{
+	u32 r;
+
+	r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+	r &= ~USBTXWRMODEI(port, mask);
+	omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb_devconf_set(u8 port, u32 mask)
+{
+	u32 r;
+
+	r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+	r |= USBTXWRMODEI(port, mask);
+	omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb2_disable_5pinbitll(void)
+{
+	u32 r;
+
+	r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+	r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
+	omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static void omap2_usb2_enable_5pinunitll(void)
+{
+	u32 r;
+
+	r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+	r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
+	omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
+}
+
+static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device)
+{
+	u32	syscon1 = 0;
+
+	omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
+
+	if (nwires == 0)
+		return 0;
+
+	if (is_device)
+		omap_cfg_reg(J20_24XX_USB0_PUEN);
+
+	omap_cfg_reg(K18_24XX_USB0_DAT);
+	omap_cfg_reg(K19_24XX_USB0_TXEN);
+	omap_cfg_reg(J14_24XX_USB0_SE0);
+	if (nwires != 3)
+		omap_cfg_reg(J18_24XX_USB0_RCV);
+
+	switch (nwires) {
+	case 3:
+		syscon1 = 2;
+		omap2_usb_devconf_set(0, USB_BIDIR);
+		break;
+	case 4:
+		syscon1 = 1;
+		omap2_usb_devconf_set(0, USB_BIDIR);
+		break;
+	case 6:
+		syscon1 = 3;
+		omap_cfg_reg(J19_24XX_USB0_VP);
+		omap_cfg_reg(K20_24XX_USB0_VM);
+		omap2_usb_devconf_set(0, USB_UNIDIR);
+		break;
+	default:
+		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+			0, nwires);
+	}
+
+	return syscon1 << 16;
+}
+
+static u32 __init omap2_usb1_init(unsigned nwires)
+{
+	u32	syscon1 = 0;
+
+	omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
+
+	if (nwires == 0)
+		return 0;
+
+	/* NOTE:  board-specific code must set up pin muxing for usb1,
+	 * since each signal could come out on either of two balls.
+	 */
+
+	switch (nwires) {
+	case 2:
+		/* NOTE: board-specific code must override this setting if
+		 * this TLL link is not using DP/DM
+		 */
+		syscon1 = 1;
+		omap2_usb_devconf_set(1, USB_BIDIR_TLL);
+		break;
+	case 3:
+		syscon1 = 2;
+		omap2_usb_devconf_set(1, USB_BIDIR);
+		break;
+	case 4:
+		syscon1 = 1;
+		omap2_usb_devconf_set(1, USB_BIDIR);
+		break;
+	case 6:
+	default:
+		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+			1, nwires);
+	}
+
+	return syscon1 << 20;
+}
+
+static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
+{
+	u32	syscon1 = 0;
+
+	omap2_usb2_disable_5pinbitll();
+	alt_pingroup = 0;
+
+	/* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
+	if (alt_pingroup || nwires == 0)
+		return 0;
+
+	omap_cfg_reg(Y11_24XX_USB2_DAT);
+	omap_cfg_reg(AA10_24XX_USB2_SE0);
+	if (nwires > 2)
+		omap_cfg_reg(AA12_24XX_USB2_TXEN);
+	if (nwires > 3)
+		omap_cfg_reg(AA6_24XX_USB2_RCV);
+
+	switch (nwires) {
+	case 2:
+		/* NOTE: board-specific code must override this setting if
+		 * this TLL link is not using DP/DM
+		 */
+		syscon1 = 1;
+		omap2_usb_devconf_set(2, USB_BIDIR_TLL);
+		break;
+	case 3:
+		syscon1 = 2;
+		omap2_usb_devconf_set(2, USB_BIDIR);
+		break;
+	case 4:
+		syscon1 = 1;
+		omap2_usb_devconf_set(2, USB_BIDIR);
+		break;
+	case 5:
+		omap_cfg_reg(AA4_24XX_USB2_TLLSE0);
+		/* NOTE: board-specific code must override this setting if
+		 * this TLL link is not using DP/DM.  Something must also
+		 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
+		 */
+		syscon1 = 3;
+		omap2_usb2_enable_5pinunitll();
+		break;
+	case 6:
+	default:
+		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+			2, nwires);
+	}
+
+	return syscon1 << 24;
+}
+
+void __init omap2_usbfs_init(struct omap_usb_config *pdata)
+{
+	if (!cpu_is_omap24xx())
+		return;
+
+	pdata->usb0_init = omap2_usb0_init;
+	pdata->usb1_init = omap2_usb1_init;
+	pdata->usb2_init = omap2_usb2_init;
+	udc_device_init(pdata);
+	ohci_device_init(pdata);
+	otg_device_init(pdata);
+	omap_otg_init(pdata);
+}
+
+#endif
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 5cd6220..3cf4fa2 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -85,6 +85,14 @@ struct omap_usb_config {
 	 *  6 == 6 wire unidirectional (or TLL)
 	 */
 	u8		pins[3];
+
+	struct platform_device *udc_device;
+	struct platform_device *ohci_device;
+	struct platform_device *otg_device;
+
+	u32 (*usb0_init)(unsigned nwires, unsigned is_device);
+	u32 (*usb1_init)(unsigned nwires);
+	u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
 };
 
 struct omap_lcd_config {
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 98eef53..9f79224 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -81,7 +81,14 @@ extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
 
 #endif
 
+void omap_otg_init(struct omap_usb_config *config);
 void omap_usb_init(struct omap_usb_config *pdata);
+void omap2_usbfs_init(struct omap_usb_config *pdata);
+#else
+static inline omap2_usbfs_init(struct omap_usb_config *pdata)
+{
+}
+#endif
 
 /*-------------------------------------------------------------------------*/
 
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 9c4929a..27b471c 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -38,25 +38,12 @@
 #include <plat/usb.h>
 #include <plat/board.h>
 
-#ifdef CONFIG_ARCH_OMAP1
-
 #define INT_USB_IRQ_GEN		IH2_BASE + 20
 #define INT_USB_IRQ_NISO	IH2_BASE + 30
 #define INT_USB_IRQ_ISO		IH2_BASE + 29
 #define INT_USB_IRQ_HGEN	INT_USB_HHC_1
 #define INT_USB_IRQ_OTG		IH2_BASE + 8
 
-#else
-
-#define INT_USB_IRQ_GEN		INT_24XX_USB_IRQ_GEN
-#define INT_USB_IRQ_NISO	INT_24XX_USB_IRQ_NISO
-#define INT_USB_IRQ_ISO		INT_24XX_USB_IRQ_ISO
-#define INT_USB_IRQ_HGEN	INT_24XX_USB_IRQ_HGEN
-#define INT_USB_IRQ_OTG		INT_24XX_USB_IRQ_OTG
-
-#endif
-
-
 /* These routines should handle the standard chip-specific modes
  * for usb0/1/2 ports, covering basic mux and transceiver setup.
  *
@@ -79,90 +66,10 @@
 
 #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
 
-static void omap2_usb_devconf_clear(u8 port, u32 mask)
-{
-	u32 r;
-
-	r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-	r &= ~USBTXWRMODEI(port, mask);
-	omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static void omap2_usb_devconf_set(u8 port, u32 mask)
-{
-	u32 r;
-
-	r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-	r |= USBTXWRMODEI(port, mask);
-	omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static void omap2_usb2_disable_5pinbitll(void)
-{
-	u32 r;
-
-	r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-	r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
-	omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static void omap2_usb2_enable_5pinunitll(void)
-{
-	u32 r;
-
-	r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-	r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
-	omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device)
-{
-	u32	syscon1 = 0;
-
-	omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
-
-	if (nwires == 0)
-		return 0;
-
-	if (is_device)
-		omap_cfg_reg(J20_24XX_USB0_PUEN);
-
-	omap_cfg_reg(K18_24XX_USB0_DAT);
-	omap_cfg_reg(K19_24XX_USB0_TXEN);
-	omap_cfg_reg(J14_24XX_USB0_SE0);
-	if (nwires != 3)
-		omap_cfg_reg(J18_24XX_USB0_RCV);
-
-	switch (nwires) {
-	case 3:
-		syscon1 = 2;
-		omap2_usb_devconf_set(0, USB_BIDIR);
-		break;
-	case 4:
-		syscon1 = 1;
-		omap2_usb_devconf_set(0, USB_BIDIR);
-		break;
-	case 6:
-		syscon1 = 3;
-		omap_cfg_reg(J19_24XX_USB0_VP);
-		omap_cfg_reg(K20_24XX_USB0_VM);
-		omap2_usb_devconf_set(0, USB_UNIDIR);
-		break;
-	default:
-		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-			0, nwires);
-	}
-
-	return syscon1 << 16;
-}
-
 static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 {
 	u32	syscon1 = 0;
 
-	if (cpu_is_omap24xx())
-		return omap2_usb0_init(nwires, is_device);
-
 	if (nwires == 0) {
 		if (!cpu_is_omap15xx()) {
 			u32 l;
@@ -266,51 +173,10 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
 	return syscon1 << 16;
 }
 
-static u32 __init omap2_usb1_init(unsigned nwires)
-{
-	u32	syscon1 = 0;
-
-	omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
-
-	if (nwires == 0)
-		return 0;
-
-	/* NOTE:  board-specific code must set up pin muxing for usb1,
-	 * since each signal could come out on either of two balls.
-	 */
-
-	switch (nwires) {
-	case 2:
-		/* NOTE: board-specific code must override this setting if
-		 * this TLL link is not using DP/DM
-		 */
-		syscon1 = 1;
-		omap2_usb_devconf_set(1, USB_BIDIR_TLL);
-		break;
-	case 3:
-		syscon1 = 2;
-		omap2_usb_devconf_set(1, USB_BIDIR);
-		break;
-	case 4:
-		syscon1 = 1;
-		omap2_usb_devconf_set(1, USB_BIDIR);
-		break;
-	case 6:
-	default:
-		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-			1, nwires);
-	}
-
-	return syscon1 << 20;
-}
-
 static u32 __init omap_usb1_init(unsigned nwires)
 {
 	u32	syscon1 = 0;
 
-	if (cpu_is_omap24xx())
-		return omap2_usb1_init(nwires);
-
 	if (!cpu_is_omap15xx() && nwires != 6) {
 		u32 l;
 
@@ -372,65 +238,10 @@ bad:
 	return syscon1 << 20;
 }
 
-static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
-{
-	u32	syscon1 = 0;
-
-	omap2_usb2_disable_5pinbitll();
-	alt_pingroup = 0;
-
-	/* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
-	if (alt_pingroup || nwires == 0)
-		return 0;
-
-	omap_cfg_reg(Y11_24XX_USB2_DAT);
-	omap_cfg_reg(AA10_24XX_USB2_SE0);
-	if (nwires > 2)
-		omap_cfg_reg(AA12_24XX_USB2_TXEN);
-	if (nwires > 3)
-		omap_cfg_reg(AA6_24XX_USB2_RCV);
-
-	switch (nwires) {
-	case 2:
-		/* NOTE: board-specific code must override this setting if
-		 * this TLL link is not using DP/DM
-		 */
-		syscon1 = 1;
-		omap2_usb_devconf_set(2, USB_BIDIR_TLL);
-		break;
-	case 3:
-		syscon1 = 2;
-		omap2_usb_devconf_set(2, USB_BIDIR);
-		break;
-	case 4:
-		syscon1 = 1;
-		omap2_usb_devconf_set(2, USB_BIDIR);
-		break;
-	case 5:
-		omap_cfg_reg(AA4_24XX_USB2_TLLSE0);
-		/* NOTE: board-specific code must override this setting if
-		 * this TLL link is not using DP/DM.  Something must also
-		 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
-		 */
-		syscon1 = 3;
-		omap2_usb2_enable_5pinunitll();
-		break;
-	case 6:
-	default:
-		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-			2, nwires);
-	}
-
-	return syscon1 << 24;
-}
-
 static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
 {
 	u32	syscon1 = 0;
 
-	if (cpu_is_omap24xx())
-		return omap2_usb2_init(nwires, alt_pingroup);
-
 	/* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
 	if (alt_pingroup || nwires == 0)
 		return 0;
@@ -498,6 +309,10 @@ bad:
 	return syscon1 << 24;
 }
 
+#else
+#define omap_usb0_init		NULL
+#define omap_usb1_init		NULL
+#define omap_usb2_init		NULL
 #endif
 
 /*-------------------------------------------------------------------------*/
@@ -535,6 +350,17 @@ static struct platform_device udc_device = {
 	.resource	= udc_resources,
 };
 
+static inline void udc_device_init(struct omap_usb_config *pdata)
+{
+	pdata->udc_device = &udc_device;
+}
+
+#else
+
+static inline void udc_device_init(struct omap_usb_config *pdata)
+{
+}
+
 #endif
 
 #if	defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
@@ -565,6 +391,17 @@ static struct platform_device ohci_device = {
 	.resource		= ohci_resources,
 };
 
+static inline void ohci_device_init(struct omap_usb_config *pdata)
+{
+	pdata->ohci_device = &ohci_device;
+}
+
+#else
+
+static inline void ohci_device_init(struct omap_usb_config *pdata)
+{
+}
+
 #endif
 
 #if	defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
@@ -588,6 +425,17 @@ static struct platform_device otg_device = {
 	.resource	= otg_resources,
 };
 
+static inline void otg_device_init(struct omap_usb_config *pdata)
+{
+	pdata->otg_device = &otg_device;
+}
+
+#else
+
+static inline void otg_device_init(struct omap_usb_config *pdata)
+{
+}
+
 #endif
 
 /*-------------------------------------------------------------------------*/
@@ -622,9 +470,9 @@ omap_otg_init(struct omap_usb_config *config)
 	/* pin muxing and transceiver pinouts */
 	if (config->pins[0] > 2)	/* alt pingroup 2 */
 		alt_pingroup = 1;
-	syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config));
-	syscon |= omap_usb1_init(config->pins[1]);
-	syscon |= omap_usb2_init(config->pins[2], alt_pingroup);
+	syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
+	syscon |= config->usb1_init(config->pins[1]);
+	syscon |= config->usb2_init(config->pins[2], alt_pingroup);
 	pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
 	omap_writel(syscon, OTG_SYSCON_1);
 
@@ -672,15 +520,17 @@ omap_otg_init(struct omap_usb_config *config)
 
 #ifdef	CONFIG_USB_GADGET_OMAP
 	if (config->otg || config->register_dev) {
+		struct platform_device *udc_device = config->udc_device;
+
 		syscon &= ~DEV_IDLE_EN;
-		udc_device.dev.platform_data = config;
+		udc_device->dev.platform_data = config;
 		/* IRQ numbers for omap7xx */
 		if(cpu_is_omap7xx()) {
 			udc_resources[1].start = INT_7XX_USB_GENI;
 			udc_resources[2].start = INT_7XX_USB_NON_ISO;
 			udc_resources[3].start = INT_7XX_USB_ISO;
 		}
-		status = platform_device_register(&udc_device);
+		status = platform_device_register(udc_device);
 		if (status)
 			pr_debug("can't register UDC device, %d\n", status);
 	}
@@ -688,11 +538,13 @@ omap_otg_init(struct omap_usb_config *config)
 
 #if	defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
 	if (config->otg || config->register_host) {
+		struct platform_device *ohci_device = config->ohci_device;
+
 		syscon &= ~HST_IDLE_EN;
-		ohci_device.dev.platform_data = config;
+		ohci_device->dev.platform_data = config;
 		if (cpu_is_omap7xx())
 			ohci_resources[1].start = INT_7XX_USB_HHC_1;
-		status = platform_device_register(&ohci_device);
+		status = platform_device_register(ohci_device);
 		if (status)
 			pr_debug("can't register OHCI device, %d\n", status);
 	}
@@ -700,11 +552,13 @@ omap_otg_init(struct omap_usb_config *config)
 
 #ifdef	CONFIG_USB_OTG
 	if (config->otg) {
+		struct platform_device *otg_device = config->otg_device;
+
 		syscon &= ~OTG_IDLE_EN;
-		otg_device.dev.platform_data = config;
+		otg_device->dev.platform_data = config;
 		if (cpu_is_omap7xx())
 			otg_resources[1].start = INT_7XX_USB_OTG;
-		status = platform_device_register(&otg_device);
+		status = platform_device_register(otg_device);
 		if (status)
 			pr_debug("can't register OTG device, %d\n", status);
 	}
@@ -716,7 +570,7 @@ omap_otg_init(struct omap_usb_config *config)
 }
 
 #else
-static inline void omap_otg_init(struct omap_usb_config *config) {}
+void omap_otg_init(struct omap_usb_config *config) {}
 #endif
 
 /*-------------------------------------------------------------------------*/
@@ -737,9 +591,9 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
 	unsigned int val;
 	u16 w;
 
-	omap_usb0_init(config->pins[0], is_usb0_device(config));
-	omap_usb1_init(config->pins[1]);
-	omap_usb2_init(config->pins[2], 0);
+	config->usb0_init(config->pins[0], is_usb0_device(config));
+	config->usb1_init(config->pins[1]);
+	config->usb2_init(config->pins[2], 0);
 
 	val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
 	val |= (config->hmc_mode << 1);
@@ -807,7 +661,14 @@ static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
 
 void __init omap_usb_init(struct omap_usb_config *pdata)
 {
-	if (cpu_is_omap7xx() || cpu_is_omap16xx() || cpu_is_omap24xx())
+	pdata->usb0_init = omap_usb0_init;
+	pdata->usb1_init = omap_usb1_init;
+	pdata->usb2_init = omap_usb2_init;
+	udc_device_init(pdata);
+	ohci_device_init(pdata);
+	otg_device_init(pdata);
+
+	if (cpu_is_omap7xx() || cpu_is_omap16xx())
 		omap_otg_init(pdata);
 	else if (cpu_is_omap15xx())
 		omap_1510_usb_init(pdata);



From tony at atomide.com  Tue Jun 29 07:54:26 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 14:54:26 +0300
Subject: [PATCH 4/4] omap: Move omap1 USB platform init code into
	mach-omap1/usb.c
In-Reply-To: <20100629115056.17702.56622.stgit@baageli.muru.com>
References: <20100629115056.17702.56622.stgit@baageli.muru.com>
Message-ID: <20100629115426.17702.37783.stgit@baageli.muru.com>

Move omap1 FS USB platform init code into mach-omap1/usb.c

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap1/Makefile          |    3 
 arch/arm/mach-omap1/board-ams-delta.c |    2 
 arch/arm/mach-omap1/board-generic.c   |    4 
 arch/arm/mach-omap1/board-h2.c        |    2 
 arch/arm/mach-omap1/board-h3.c        |    2 
 arch/arm/mach-omap1/board-htcherald.c |    2 
 arch/arm/mach-omap1/board-innovator.c |    4 
 arch/arm/mach-omap1/board-nokia770.c  |    2 
 arch/arm/mach-omap1/board-osk.c       |    2 
 arch/arm/mach-omap1/board-palmte.c    |    2 
 arch/arm/mach-omap1/board-palmtt.c    |    2 
 arch/arm/mach-omap1/board-palmz71.c   |    2 
 arch/arm/mach-omap1/board-sx1.c       |    2 
 arch/arm/mach-omap1/board-voiceblue.c |    2 
 arch/arm/mach-omap1/usb.c             |  530 +++++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/usb.h |   42 +++
 arch/arm/plat-omap/usb.c              |  535 ---------------------------------
 17 files changed, 589 insertions(+), 551 deletions(-)
 create mode 100644 arch/arm/mach-omap1/usb.c

diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index ea231c7..facfaeb 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -23,6 +23,9 @@ obj-y					+= $(i2c-omap-m) $(i2c-omap-y)
 
 led-y := leds.o
 
+usb-fs-$(CONFIG_USB)			:= usb.o
+obj-y					+= $(usb-fs-m) $(usb-fs-y)
+
 # Specific board support
 obj-$(CONFIG_MACH_OMAP_H2)		+= board-h2.o board-h2-mmc.o
 obj-$(CONFIG_MACH_OMAP_INNOVATOR)	+= board-innovator.o
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index fdd1dd5..c6a81ff 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -235,7 +235,7 @@ static void __init ams_delta_init(void)
 	/* Clear latch2 (NAND, LCD, modem enable) */
 	ams_delta_latch2_write(~0, 0);
 
-	omap_usb_init(&ams_delta_usb_config);
+	omap1_usb_init(&ams_delta_usb_config);
 	platform_add_devices(ams_delta_devices, ARRAY_SIZE(ams_delta_devices));
 
 #ifdef CONFIG_AMS_DELTA_FIQ
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index e1195a3..e9ed8bf 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -72,12 +72,12 @@ static void __init omap_generic_init(void)
 		omap_cfg_reg(UART3_TX);
 		omap_cfg_reg(UART3_RX);
 
-		omap_usb_init(&generic1510_usb_config);
+		omap1_usb_init(&generic1510_usb_config);
 	}
 #endif
 #if defined(CONFIG_ARCH_OMAP16XX)
 	if (!cpu_is_omap1510()) {
-		omap_usb_init(&generic1610_usb_config);
+		omap1_usb_init(&generic1610_usb_config);
 	}
 #endif
 
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index d1100e4..5f30188 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -452,7 +452,7 @@ static void __init h2_init(void)
 	omap_serial_init();
 	omap_register_i2c_bus(1, 100, h2_i2c_board_info,
 			      ARRAY_SIZE(h2_i2c_board_info));
-	omap_usb_init(&h2_usb_config);
+	omap1_usb_init(&h2_usb_config);
 	h2_mmc_init();
 }
 
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index a53ab82..0be1d3b 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -405,7 +405,7 @@ static void __init h3_init(void)
 	omap_serial_init();
 	omap_register_i2c_bus(1, 100, h3_i2c_board_info,
 			      ARRAY_SIZE(h3_i2c_board_info));
-	omap_usb_init(&h3_usb_config);
+	omap1_usb_init(&h3_usb_config);
 	h3_mmc_init();
 }
 
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 8e313b4..736e4c2 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -287,7 +287,7 @@ static void __init htcherald_init(void)
 	htcherald_disable_watchdog();
 
 	htcherald_usb_enable();
-	omap_usb_init(&htcherald_usb_config);
+	omap1_usb_init(&htcherald_usb_config);
 }
 
 static void __init htcherald_init_irq(void)
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 5d12fd3..3c04e90 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -422,13 +422,13 @@ static void __init innovator_init(void)
 
 #ifdef CONFIG_ARCH_OMAP15XX
 	if (cpu_is_omap1510()) {
-		omap_usb_init(&innovator1510_usb_config);
+		omap1_usb_init(&innovator1510_usb_config);
 		innovator_config[1].data = &innovator1510_lcd_config;
 	}
 #endif
 #ifdef CONFIG_ARCH_OMAP16XX
 	if (cpu_is_omap1610()) {
-		omap_usb_init(&h2_usb_config);
+		omap1_usb_init(&h2_usb_config);
 		innovator_config[1].data = &innovator1610_lcd_config;
 	}
 #endif
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 71e1a3f..c9e9e37 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -386,7 +386,7 @@ static void __init omap_nokia770_init(void)
 	hwa742_dev_init();
 	ads7846_dev_init();
 	mipid_dev_init();
-	omap_usb_init(&nokia770_usb_config);
+	omap1_usb_init(&nokia770_usb_config);
 	nokia770_mmc_init();
 }
 
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 80d8620..b28c46a 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -560,7 +560,7 @@ static void __init osk_init(void)
 	l |= (3 << 1);
 	omap_writel(l, USB_TRANSCEIVER_CTRL);
 
-	omap_usb_init(&osk_usb_config);
+	omap1_usb_init(&osk_usb_config);
 
 	/* irq for tps65010 chip */
 	/* bootloader effectively does:  omap_cfg_reg(U19_1610_MPUIO1); */
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 569b4c9..51d5c4d 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -359,7 +359,7 @@ static void __init omap_palmte_init(void)
 	spi_register_board_info(palmte_spi_info, ARRAY_SIZE(palmte_spi_info));
 	palmte_misc_gpio_setup();
 	omap_serial_init();
-	omap_usb_init(&palmte_usb_config);
+	omap1_usb_init(&palmte_usb_config);
 	omap_register_i2c_bus(1, 100, NULL, 0);
 }
 
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 6ad49a2..c0bcfc6 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -307,7 +307,7 @@ static void __init omap_palmtt_init(void)
 
 	spi_register_board_info(palmtt_boardinfo,ARRAY_SIZE(palmtt_boardinfo));
 	omap_serial_init();
-	omap_usb_init(&palmtt_usb_config);
+	omap1_usb_init(&palmtt_usb_config);
 	omap_register_i2c_bus(1, 100, NULL, 0);
 }
 
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 6641de9..f431b44 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -325,7 +325,7 @@ omap_palmz71_init(void)
 
 	spi_register_board_info(palmz71_boardinfo,
 				ARRAY_SIZE(palmz71_boardinfo));
-	omap_usb_init(&palmz71_usb_config);
+	omap1_usb_init(&palmz71_usb_config);
 	omap_serial_init();
 	omap_register_i2c_bus(1, 100, NULL, 0);
 	palmz71_gpio_setup(0);
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 2fb1e5f..7b21190 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -392,7 +392,7 @@ static void __init omap_sx1_init(void)
 	omap_board_config_size = ARRAY_SIZE(sx1_config);
 	omap_serial_init();
 	omap_register_i2c_bus(1, 100, NULL, 0);
-	omap_usb_init(&sx1_usb_config);
+	omap1_usb_init(&sx1_usb_config);
 	sx1_mmc_init();
 
 	/* turn on USB power */
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 87b9436..7810754 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -198,7 +198,7 @@ static void __init voiceblue_init(void)
 	omap_board_config = voiceblue_config;
 	omap_board_config_size = ARRAY_SIZE(voiceblue_config);
 	omap_serial_init();
-	omap_usb_init(&voiceblue_usb_config);
+	omap1_usb_init(&voiceblue_usb_config);
 	omap_register_i2c_bus(1, 100, NULL, 0);
 
 	/* There is a good chance board is going up, so enable power LED
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
new file mode 100644
index 0000000..19de03b
--- /dev/null
+++ b/arch/arm/mach-omap1/usb.c
@@ -0,0 +1,530 @@
+/*
+ * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx
+ *
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <asm/irq.h>
+
+#include <plat/mux.h>
+#include <plat/usb.h>
+
+/* These routines should handle the standard chip-specific modes
+ * for usb0/1/2 ports, covering basic mux and transceiver setup.
+ *
+ * Some board-*.c files will need to set up additional mux options,
+ * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup.
+ */
+
+/* TESTED ON:
+ *  - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables
+ *  - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables
+ *  - 5912 OSK UDC, with *nonstandard* A-to-A cable
+ *  - 1510 Innovator UDC with bundled usb0 cable
+ *  - 1510 Innovator OHCI with bundled usb1/usb2 cable
+ *  - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS
+ *  - 1710 custom development board using alternate pin group
+ *  - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables
+ */
+
+#define INT_USB_IRQ_GEN		IH2_BASE + 20
+#define INT_USB_IRQ_NISO	IH2_BASE + 30
+#define INT_USB_IRQ_ISO		IH2_BASE + 29
+#define INT_USB_IRQ_HGEN	INT_USB_HHC_1
+#define INT_USB_IRQ_OTG		IH2_BASE + 8
+
+#ifdef	CONFIG_USB_GADGET_OMAP
+
+static struct resource udc_resources[] = {
+	/* order is significant! */
+	{		/* registers */
+		.start		= UDC_BASE,
+		.end		= UDC_BASE + 0xff,
+		.flags		= IORESOURCE_MEM,
+	}, {		/* general IRQ */
+		.start		= INT_USB_IRQ_GEN,
+		.flags		= IORESOURCE_IRQ,
+	}, {		/* PIO IRQ */
+		.start		= INT_USB_IRQ_NISO,
+		.flags		= IORESOURCE_IRQ,
+	}, {		/* SOF IRQ */
+		.start		= INT_USB_IRQ_ISO,
+		.flags		= IORESOURCE_IRQ,
+	},
+};
+
+static u64 udc_dmamask = ~(u32)0;
+
+static struct platform_device udc_device = {
+	.name		= "omap_udc",
+	.id		= -1,
+	.dev = {
+		.dma_mask		= &udc_dmamask,
+		.coherent_dma_mask	= 0xffffffff,
+	},
+	.num_resources	= ARRAY_SIZE(udc_resources),
+	.resource	= udc_resources,
+};
+
+static inline void udc_device_init(struct omap_usb_config *pdata)
+{
+	/* IRQ numbers for omap7xx */
+	if(cpu_is_omap7xx()) {
+		udc_resources[1].start = INT_7XX_USB_GENI;
+		udc_resources[2].start = INT_7XX_USB_NON_ISO;
+		udc_resources[3].start = INT_7XX_USB_ISO;
+	}
+	pdata->udc_device = &udc_device;
+}
+
+#else
+
+static inline void udc_device_init(struct omap_usb_config *pdata)
+{
+}
+
+#endif
+
+#if	defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = ~(u32)0;
+
+static struct resource ohci_resources[] = {
+	{
+		.start	= OMAP_OHCI_BASE,
+		.end	= OMAP_OHCI_BASE + 0xff,
+		.flags	= IORESOURCE_MEM,
+	},
+	{
+		.start	= INT_USB_IRQ_HGEN,
+		.flags	= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device ohci_device = {
+	.name			= "ohci",
+	.id			= -1,
+	.dev = {
+		.dma_mask		= &ohci_dmamask,
+		.coherent_dma_mask	= 0xffffffff,
+	},
+	.num_resources	= ARRAY_SIZE(ohci_resources),
+	.resource		= ohci_resources,
+};
+
+static inline void ohci_device_init(struct omap_usb_config *pdata)
+{
+	if (cpu_is_omap7xx())
+		ohci_resources[1].start = INT_7XX_USB_HHC_1;
+	pdata->ohci_device = &ohci_device;
+}
+
+#else
+
+static inline void ohci_device_init(struct omap_usb_config *pdata)
+{
+}
+
+#endif
+
+#if	defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
+
+static struct resource otg_resources[] = {
+	/* order is significant! */
+	{
+		.start		= OTG_BASE,
+		.end		= OTG_BASE + 0xff,
+		.flags		= IORESOURCE_MEM,
+	}, {
+		.start		= INT_USB_IRQ_OTG,
+		.flags		= IORESOURCE_IRQ,
+	},
+};
+
+static struct platform_device otg_device = {
+	.name		= "omap_otg",
+	.id		= -1,
+	.num_resources	= ARRAY_SIZE(otg_resources),
+	.resource	= otg_resources,
+};
+
+static inline void otg_device_init(struct omap_usb_config *pdata)
+{
+	if (cpu_is_omap7xx())
+		otg_resources[1].start = INT_7XX_USB_OTG;
+	pdata->otg_device = &otg_device;
+}
+
+#else
+
+static inline void otg_device_init(struct omap_usb_config *pdata)
+{
+}
+
+#endif
+
+u32 __init omap1_usb0_init(unsigned nwires, unsigned is_device)
+{
+	u32	syscon1 = 0;
+
+	if (nwires == 0) {
+		if (!cpu_is_omap15xx()) {
+			u32 l;
+
+			/* pulldown D+/D- */
+			l = omap_readl(USB_TRANSCEIVER_CTRL);
+			l &= ~(3 << 1);
+			omap_writel(l, USB_TRANSCEIVER_CTRL);
+		}
+		return 0;
+	}
+
+	if (is_device) {
+		if (cpu_is_omap7xx()) {
+			omap_cfg_reg(AA17_7XX_USB_DM);
+			omap_cfg_reg(W16_7XX_USB_PU_EN);
+			omap_cfg_reg(W17_7XX_USB_VBUSI);
+			omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
+			omap_cfg_reg(W19_7XX_USB_DCRST);
+		} else
+			omap_cfg_reg(W4_USB_PUEN);
+	}
+
+	if (nwires == 2) {
+		u32 l;
+
+		// omap_cfg_reg(P9_USB_DP);
+		// omap_cfg_reg(R8_USB_DM);
+
+		if (cpu_is_omap15xx()) {
+			/* This works on 1510-Innovator */
+			return 0;
+		}
+
+		/* NOTES:
+		 *  - peripheral should configure VBUS detection!
+		 *  - only peripherals may use the internal D+/D- pulldowns
+		 *  - OTG support on this port not yet written
+		 */
+
+		/* Don't do this for omap7xx -- it causes USB to not work correctly */
+		if (!cpu_is_omap7xx()) {
+			l = omap_readl(USB_TRANSCEIVER_CTRL);
+			l &= ~(7 << 4);
+			if (!is_device)
+				l |= (3 << 1);
+			omap_writel(l, USB_TRANSCEIVER_CTRL);
+		}
+
+		return 3 << 16;
+	}
+
+	/* alternate pin config, external transceiver */
+	if (cpu_is_omap15xx()) {
+		printk(KERN_ERR "no usb0 alt pin config on 15xx\n");
+		return 0;
+	}
+
+	omap_cfg_reg(V6_USB0_TXD);
+	omap_cfg_reg(W9_USB0_TXEN);
+	omap_cfg_reg(W5_USB0_SE0);
+	if (nwires != 3)
+		omap_cfg_reg(Y5_USB0_RCV);
+
+	/* NOTE:  SPEED and SUSP aren't configured here.  OTG hosts
+	 * may be able to use I2C requests to set those bits along
+	 * with VBUS switching and overcurrent detection.
+	 */
+
+	if (nwires != 6) {
+		u32 l;
+
+		l = omap_readl(USB_TRANSCEIVER_CTRL);
+		l &= ~CONF_USB2_UNI_R;
+		omap_writel(l, USB_TRANSCEIVER_CTRL);
+	}
+
+	switch (nwires) {
+	case 3:
+		syscon1 = 2;
+		break;
+	case 4:
+		syscon1 = 1;
+		break;
+	case 6:
+		syscon1 = 3;
+		{
+			u32 l;
+
+			omap_cfg_reg(AA9_USB0_VP);
+			omap_cfg_reg(R9_USB0_VM);
+			l = omap_readl(USB_TRANSCEIVER_CTRL);
+			l |= CONF_USB2_UNI_R;
+			omap_writel(l, USB_TRANSCEIVER_CTRL);
+		}
+		break;
+	default:
+		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+			0, nwires);
+	}
+
+	return syscon1 << 16;
+}
+
+u32 __init omap1_usb1_init(unsigned nwires)
+{
+	u32	syscon1 = 0;
+
+	if (!cpu_is_omap15xx() && nwires != 6) {
+		u32 l;
+
+		l = omap_readl(USB_TRANSCEIVER_CTRL);
+		l &= ~CONF_USB1_UNI_R;
+		omap_writel(l, USB_TRANSCEIVER_CTRL);
+	}
+	if (nwires == 0)
+		return 0;
+
+	/* external transceiver */
+	omap_cfg_reg(USB1_TXD);
+	omap_cfg_reg(USB1_TXEN);
+	if (nwires != 3)
+		omap_cfg_reg(USB1_RCV);
+
+	if (cpu_is_omap15xx()) {
+		omap_cfg_reg(USB1_SEO);
+		omap_cfg_reg(USB1_SPEED);
+		// SUSP
+	} else if (cpu_is_omap1610() || cpu_is_omap5912()) {
+		omap_cfg_reg(W13_1610_USB1_SE0);
+		omap_cfg_reg(R13_1610_USB1_SPEED);
+		// SUSP
+	} else if (cpu_is_omap1710()) {
+		omap_cfg_reg(R13_1710_USB1_SE0);
+		// SUSP
+	} else {
+		pr_debug("usb%d cpu unrecognized\n", 1);
+		return 0;
+	}
+
+	switch (nwires) {
+	case 2:
+		goto bad;
+	case 3:
+		syscon1 = 2;
+		break;
+	case 4:
+		syscon1 = 1;
+		break;
+	case 6:
+		syscon1 = 3;
+		omap_cfg_reg(USB1_VP);
+		omap_cfg_reg(USB1_VM);
+		if (!cpu_is_omap15xx()) {
+			u32 l;
+
+			l = omap_readl(USB_TRANSCEIVER_CTRL);
+			l |= CONF_USB1_UNI_R;
+			omap_writel(l, USB_TRANSCEIVER_CTRL);
+		}
+		break;
+	default:
+bad:
+		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+			1, nwires);
+	}
+
+	return syscon1 << 20;
+}
+
+u32 __init omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
+{
+	u32	syscon1 = 0;
+
+	/* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
+	if (alt_pingroup || nwires == 0)
+		return 0;
+
+	if (!cpu_is_omap15xx() && nwires != 6) {
+		u32 l;
+
+		l = omap_readl(USB_TRANSCEIVER_CTRL);
+		l &= ~CONF_USB2_UNI_R;
+		omap_writel(l, USB_TRANSCEIVER_CTRL);
+	}
+
+	/* external transceiver */
+	if (cpu_is_omap15xx()) {
+		omap_cfg_reg(USB2_TXD);
+		omap_cfg_reg(USB2_TXEN);
+		omap_cfg_reg(USB2_SEO);
+		if (nwires != 3)
+			omap_cfg_reg(USB2_RCV);
+		/* there is no USB2_SPEED */
+	} else if (cpu_is_omap16xx()) {
+		omap_cfg_reg(V6_USB2_TXD);
+		omap_cfg_reg(W9_USB2_TXEN);
+		omap_cfg_reg(W5_USB2_SE0);
+		if (nwires != 3)
+			omap_cfg_reg(Y5_USB2_RCV);
+		// FIXME omap_cfg_reg(USB2_SPEED);
+	} else {
+		pr_debug("usb%d cpu unrecognized\n", 1);
+		return 0;
+	}
+
+	// omap_cfg_reg(USB2_SUSP);
+
+	switch (nwires) {
+	case 2:
+		goto bad;
+	case 3:
+		syscon1 = 2;
+		break;
+	case 4:
+		syscon1 = 1;
+		break;
+	case 5:
+		goto bad;
+	case 6:
+		syscon1 = 3;
+		if (cpu_is_omap15xx()) {
+			omap_cfg_reg(USB2_VP);
+			omap_cfg_reg(USB2_VM);
+		} else {
+			u32 l;
+
+			omap_cfg_reg(AA9_USB2_VP);
+			omap_cfg_reg(R9_USB2_VM);
+			l = omap_readl(USB_TRANSCEIVER_CTRL);
+			l |= CONF_USB2_UNI_R;
+			omap_writel(l, USB_TRANSCEIVER_CTRL);
+		}
+		break;
+	default:
+bad:
+		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
+			2, nwires);
+	}
+
+	return syscon1 << 24;
+}
+
+#ifdef	CONFIG_ARCH_OMAP15XX
+
+/* ULPD_DPLL_CTRL */
+#define DPLL_IOB		(1 << 13)
+#define DPLL_PLL_ENABLE		(1 << 4)
+#define DPLL_LOCK		(1 << 0)
+
+/* ULPD_APLL_CTRL */
+#define APLL_NDPLL_SWITCH	(1 << 0)
+
+static void __init omap_1510_usb_init(struct omap_usb_config *config)
+{
+	unsigned int val;
+	u16 w;
+
+	config->usb0_init(config->pins[0], is_usb0_device(config));
+	config->usb1_init(config->pins[1]);
+	config->usb2_init(config->pins[2], 0);
+
+	val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
+	val |= (config->hmc_mode << 1);
+	omap_writel(val, MOD_CONF_CTRL_0);
+
+	printk("USB: hmc %d", config->hmc_mode);
+	if (config->pins[0])
+		printk(", usb0 %d wires%s", config->pins[0],
+			is_usb0_device(config) ? " (dev)" : "");
+	if (config->pins[1])
+		printk(", usb1 %d wires", config->pins[1]);
+	if (config->pins[2])
+		printk(", usb2 %d wires", config->pins[2]);
+	printk("\n");
+
+	/* use DPLL for 48 MHz function clock */
+	pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
+			omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
+
+	w = omap_readw(ULPD_APLL_CTRL);
+	w &= ~APLL_NDPLL_SWITCH;
+	omap_writew(w, ULPD_APLL_CTRL);
+
+	w = omap_readw(ULPD_DPLL_CTRL);
+	w |= DPLL_IOB | DPLL_PLL_ENABLE;
+	omap_writew(w, ULPD_DPLL_CTRL);
+
+	w = omap_readw(ULPD_SOFT_REQ);
+	w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
+	omap_writew(w, ULPD_SOFT_REQ);
+
+	while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
+		cpu_relax();
+
+#ifdef	CONFIG_USB_GADGET_OMAP
+	if (config->register_dev) {
+		int status;
+
+		udc_device.dev.platform_data = config;
+		status = platform_device_register(&udc_device);
+		if (status)
+			pr_debug("can't register UDC device, %d\n", status);
+		/* udc driver gates 48MHz by D+ pullup */
+	}
+#endif
+
+#if	defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+	if (config->register_host) {
+		int status;
+
+		ohci_device.dev.platform_data = config;
+		status = platform_device_register(&ohci_device);
+		if (status)
+			pr_debug("can't register OHCI device, %d\n", status);
+		/* hcd explicitly gates 48MHz */
+	}
+#endif
+}
+
+#else
+static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
+#endif
+
+void __init omap1_usb_init(struct omap_usb_config *pdata)
+{
+	pdata->usb0_init = omap1_usb0_init;
+	pdata->usb1_init = omap1_usb1_init;
+	pdata->usb2_init = omap1_usb2_init;
+	udc_device_init(pdata);
+	ohci_device_init(pdata);
+	otg_device_init(pdata);
+
+	if (cpu_is_omap7xx() || cpu_is_omap16xx())
+		omap_otg_init(pdata);
+	else if (cpu_is_omap15xx())
+		omap_1510_usb_init(pdata);
+	else
+		printk(KERN_ERR "USB: No init for your chip yet\n");
+}
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 9f79224..2a9427c 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -81,8 +81,28 @@ extern void usb_ohci_init(const struct ohci_hcd_omap_platform_data *pdata);
 
 #endif
 
+
+/*
+ * FIXME correct answer depends on hmc_mode,
+ * as does (on omap1) any nonzero value for config->otg port number
+ */
+#ifdef	CONFIG_USB_GADGET_OMAP
+#define	is_usb0_device(config)	1
+#else
+#define	is_usb0_device(config)	0
+#endif
+
 void omap_otg_init(struct omap_usb_config *config);
-void omap_usb_init(struct omap_usb_config *pdata);
+
+#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
+void omap1_usb_init(struct omap_usb_config *pdata);
+#else
+static inline void omap1_usb_init(struct omap_usb_config *pdata)
+{
+}
+#endif
+
+#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
 void omap2_usbfs_init(struct omap_usb_config *pdata);
 #else
 static inline omap2_usbfs_init(struct omap_usb_config *pdata)
@@ -199,4 +219,24 @@ static inline omap2_usbfs_init(struct omap_usb_config *pdata)
 #	define	USB0PUENACTLOI		(1 << 16)
 #	define	USBSTANDBYCTRL		(1 << 15)
 
+#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB)
+u32 omap1_usb0_init(unsigned nwires, unsigned is_device);
+u32 omap1_usb1_init(unsigned nwires);
+u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup);
+#else
+static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device)
+{
+	return 0;
+}
+static inline u32 omap1_usb1_init(unsigned nwires)
+{
+	return 0;
+
+}
+static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup)
+{
+	return 0;
+}
+#endif
+
 #endif	/* __ASM_ARCH_OMAP_USB_H */
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index 27b471c..f357088 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -22,434 +22,13 @@
 
 #include <linux/module.h>
 #include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/errno.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/usb/otg.h>
 #include <linux/io.h>
 
-#include <asm/irq.h>
-#include <asm/system.h>
-#include <mach/hardware.h>
-
-#include <plat/control.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 
-#define INT_USB_IRQ_GEN		IH2_BASE + 20
-#define INT_USB_IRQ_NISO	IH2_BASE + 30
-#define INT_USB_IRQ_ISO		IH2_BASE + 29
-#define INT_USB_IRQ_HGEN	INT_USB_HHC_1
-#define INT_USB_IRQ_OTG		IH2_BASE + 8
-
-/* These routines should handle the standard chip-specific modes
- * for usb0/1/2 ports, covering basic mux and transceiver setup.
- *
- * Some board-*.c files will need to set up additional mux options,
- * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup.
- */
-
-/* TESTED ON:
- *  - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables
- *  - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables
- *  - 5912 OSK UDC, with *nonstandard* A-to-A cable
- *  - 1510 Innovator UDC with bundled usb0 cable
- *  - 1510 Innovator OHCI with bundled usb1/usb2 cable
- *  - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS
- *  - 1710 custom development board using alternate pin group
- *  - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables
- */
-
-/*-------------------------------------------------------------------------*/
-
-#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX)
-
-static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
-{
-	u32	syscon1 = 0;
-
-	if (nwires == 0) {
-		if (!cpu_is_omap15xx()) {
-			u32 l;
-
-			/* pulldown D+/D- */
-			l = omap_readl(USB_TRANSCEIVER_CTRL);
-			l &= ~(3 << 1);
-			omap_writel(l, USB_TRANSCEIVER_CTRL);
-		}
-		return 0;
-	}
-
-	if (is_device) {
-		if (cpu_is_omap7xx()) {
-			omap_cfg_reg(AA17_7XX_USB_DM);
-			omap_cfg_reg(W16_7XX_USB_PU_EN);
-			omap_cfg_reg(W17_7XX_USB_VBUSI);
-			omap_cfg_reg(W18_7XX_USB_DMCK_OUT);
-			omap_cfg_reg(W19_7XX_USB_DCRST);
-		} else
-			omap_cfg_reg(W4_USB_PUEN);
-	}
-
-	if (nwires == 2) {
-		u32 l;
-
-		// omap_cfg_reg(P9_USB_DP);
-		// omap_cfg_reg(R8_USB_DM);
-
-		if (cpu_is_omap15xx()) {
-			/* This works on 1510-Innovator */
-			return 0;
-		}
-
-		/* NOTES:
-		 *  - peripheral should configure VBUS detection!
-		 *  - only peripherals may use the internal D+/D- pulldowns
-		 *  - OTG support on this port not yet written
-		 */
-
-		/* Don't do this for omap7xx -- it causes USB to not work correctly */
-		if (!cpu_is_omap7xx()) {
-			l = omap_readl(USB_TRANSCEIVER_CTRL);
-			l &= ~(7 << 4);
-			if (!is_device)
-				l |= (3 << 1);
-			omap_writel(l, USB_TRANSCEIVER_CTRL);
-		}
-
-		return 3 << 16;
-	}
-
-	/* alternate pin config, external transceiver */
-	if (cpu_is_omap15xx()) {
-		printk(KERN_ERR "no usb0 alt pin config on 15xx\n");
-		return 0;
-	}
-
-	omap_cfg_reg(V6_USB0_TXD);
-	omap_cfg_reg(W9_USB0_TXEN);
-	omap_cfg_reg(W5_USB0_SE0);
-	if (nwires != 3)
-		omap_cfg_reg(Y5_USB0_RCV);
-
-	/* NOTE:  SPEED and SUSP aren't configured here.  OTG hosts
-	 * may be able to use I2C requests to set those bits along
-	 * with VBUS switching and overcurrent detection.
-	 */
-
-	if (nwires != 6) {
-		u32 l;
-
-		l = omap_readl(USB_TRANSCEIVER_CTRL);
-		l &= ~CONF_USB2_UNI_R;
-		omap_writel(l, USB_TRANSCEIVER_CTRL);
-	}
-
-	switch (nwires) {
-	case 3:
-		syscon1 = 2;
-		break;
-	case 4:
-		syscon1 = 1;
-		break;
-	case 6:
-		syscon1 = 3;
-		{
-			u32 l;
-
-			omap_cfg_reg(AA9_USB0_VP);
-			omap_cfg_reg(R9_USB0_VM);
-			l = omap_readl(USB_TRANSCEIVER_CTRL);
-			l |= CONF_USB2_UNI_R;
-			omap_writel(l, USB_TRANSCEIVER_CTRL);
-		}
-		break;
-	default:
-		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-			0, nwires);
-	}
-	return syscon1 << 16;
-}
-
-static u32 __init omap_usb1_init(unsigned nwires)
-{
-	u32	syscon1 = 0;
-
-	if (!cpu_is_omap15xx() && nwires != 6) {
-		u32 l;
-
-		l = omap_readl(USB_TRANSCEIVER_CTRL);
-		l &= ~CONF_USB1_UNI_R;
-		omap_writel(l, USB_TRANSCEIVER_CTRL);
-	}
-	if (nwires == 0)
-		return 0;
-
-	/* external transceiver */
-	omap_cfg_reg(USB1_TXD);
-	omap_cfg_reg(USB1_TXEN);
-	if (nwires != 3)
-		omap_cfg_reg(USB1_RCV);
-
-	if (cpu_is_omap15xx()) {
-		omap_cfg_reg(USB1_SEO);
-		omap_cfg_reg(USB1_SPEED);
-		// SUSP
-	} else if (cpu_is_omap1610() || cpu_is_omap5912()) {
-		omap_cfg_reg(W13_1610_USB1_SE0);
-		omap_cfg_reg(R13_1610_USB1_SPEED);
-		// SUSP
-	} else if (cpu_is_omap1710()) {
-		omap_cfg_reg(R13_1710_USB1_SE0);
-		// SUSP
-	} else {
-		pr_debug("usb%d cpu unrecognized\n", 1);
-		return 0;
-	}
-
-	switch (nwires) {
-	case 2:
-		goto bad;
-	case 3:
-		syscon1 = 2;
-		break;
-	case 4:
-		syscon1 = 1;
-		break;
-	case 6:
-		syscon1 = 3;
-		omap_cfg_reg(USB1_VP);
-		omap_cfg_reg(USB1_VM);
-		if (!cpu_is_omap15xx()) {
-			u32 l;
-
-			l = omap_readl(USB_TRANSCEIVER_CTRL);
-			l |= CONF_USB1_UNI_R;
-			omap_writel(l, USB_TRANSCEIVER_CTRL);
-		}
-		break;
-	default:
-bad:
-		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-			1, nwires);
-	}
-	return syscon1 << 20;
-}
-
-static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
-{
-	u32	syscon1 = 0;
-
-	/* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
-	if (alt_pingroup || nwires == 0)
-		return 0;
-
-	if (!cpu_is_omap15xx() && nwires != 6) {
-		u32 l;
-
-		l = omap_readl(USB_TRANSCEIVER_CTRL);
-		l &= ~CONF_USB2_UNI_R;
-		omap_writel(l, USB_TRANSCEIVER_CTRL);
-	}
-
-	/* external transceiver */
-	if (cpu_is_omap15xx()) {
-		omap_cfg_reg(USB2_TXD);
-		omap_cfg_reg(USB2_TXEN);
-		omap_cfg_reg(USB2_SEO);
-		if (nwires != 3)
-			omap_cfg_reg(USB2_RCV);
-		/* there is no USB2_SPEED */
-	} else if (cpu_is_omap16xx()) {
-		omap_cfg_reg(V6_USB2_TXD);
-		omap_cfg_reg(W9_USB2_TXEN);
-		omap_cfg_reg(W5_USB2_SE0);
-		if (nwires != 3)
-			omap_cfg_reg(Y5_USB2_RCV);
-		// FIXME omap_cfg_reg(USB2_SPEED);
-	} else {
-		pr_debug("usb%d cpu unrecognized\n", 1);
-		return 0;
-	}
-	// omap_cfg_reg(USB2_SUSP);
-
-	switch (nwires) {
-	case 2:
-		goto bad;
-	case 3:
-		syscon1 = 2;
-		break;
-	case 4:
-		syscon1 = 1;
-		break;
-	case 5:
-		goto bad;
-	case 6:
-		syscon1 = 3;
-		if (cpu_is_omap15xx()) {
-			omap_cfg_reg(USB2_VP);
-			omap_cfg_reg(USB2_VM);
-		} else {
-			u32 l;
-
-			omap_cfg_reg(AA9_USB2_VP);
-			omap_cfg_reg(R9_USB2_VM);
-			l = omap_readl(USB_TRANSCEIVER_CTRL);
-			l |= CONF_USB2_UNI_R;
-			omap_writel(l, USB_TRANSCEIVER_CTRL);
-		}
-		break;
-	default:
-bad:
-		printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-			2, nwires);
-	}
-	return syscon1 << 24;
-}
-
-#else
-#define omap_usb0_init		NULL
-#define omap_usb1_init		NULL
-#define omap_usb2_init		NULL
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef	CONFIG_USB_GADGET_OMAP
-
-static struct resource udc_resources[] = {
-	/* order is significant! */
-	{		/* registers */
-		.start		= UDC_BASE,
-		.end		= UDC_BASE + 0xff,
-		.flags		= IORESOURCE_MEM,
-	}, {		/* general IRQ */
-		.start		= INT_USB_IRQ_GEN,
-		.flags		= IORESOURCE_IRQ,
-	}, {		/* PIO IRQ */
-		.start		= INT_USB_IRQ_NISO,
-		.flags		= IORESOURCE_IRQ,
-	}, {		/* SOF IRQ */
-		.start		= INT_USB_IRQ_ISO,
-		.flags		= IORESOURCE_IRQ,
-	},
-};
-
-static u64 udc_dmamask = ~(u32)0;
-
-static struct platform_device udc_device = {
-	.name		= "omap_udc",
-	.id		= -1,
-	.dev = {
-		.dma_mask		= &udc_dmamask,
-		.coherent_dma_mask	= 0xffffffff,
-	},
-	.num_resources	= ARRAY_SIZE(udc_resources),
-	.resource	= udc_resources,
-};
-
-static inline void udc_device_init(struct omap_usb_config *pdata)
-{
-	pdata->udc_device = &udc_device;
-}
-
-#else
-
-static inline void udc_device_init(struct omap_usb_config *pdata)
-{
-}
-
-#endif
-
-#if	defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32)0;
-
-static struct resource ohci_resources[] = {
-	{
-		.start	= OMAP_OHCI_BASE,
-		.end	= OMAP_OHCI_BASE + 0xff,
-		.flags	= IORESOURCE_MEM,
-	},
-	{
-		.start	= INT_USB_IRQ_HGEN,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device ohci_device = {
-	.name			= "ohci",
-	.id			= -1,
-	.dev = {
-		.dma_mask		= &ohci_dmamask,
-		.coherent_dma_mask	= 0xffffffff,
-	},
-	.num_resources	= ARRAY_SIZE(ohci_resources),
-	.resource		= ohci_resources,
-};
-
-static inline void ohci_device_init(struct omap_usb_config *pdata)
-{
-	pdata->ohci_device = &ohci_device;
-}
-
-#else
-
-static inline void ohci_device_init(struct omap_usb_config *pdata)
-{
-}
-
-#endif
-
-#if	defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
-
-static struct resource otg_resources[] = {
-	/* order is significant! */
-	{
-		.start		= OTG_BASE,
-		.end		= OTG_BASE + 0xff,
-		.flags		= IORESOURCE_MEM,
-	}, {
-		.start		= INT_USB_IRQ_OTG,
-		.flags		= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device otg_device = {
-	.name		= "omap_otg",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(otg_resources),
-	.resource	= otg_resources,
-};
-
-static inline void otg_device_init(struct omap_usb_config *pdata)
-{
-	pdata->otg_device = &otg_device;
-}
-
-#else
-
-static inline void otg_device_init(struct omap_usb_config *pdata)
-{
-}
-
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-// FIXME correct answer depends on hmc_mode,
-// as does (on omap1) any nonzero value for config->otg port number
-#ifdef	CONFIG_USB_GADGET_OMAP
-#define	is_usb0_device(config)	1
-#else
-#define	is_usb0_device(config)	0
-#endif
-
-/*-------------------------------------------------------------------------*/
-
 #ifdef	CONFIG_ARCH_OMAP_OTG
 
 void __init
@@ -524,12 +103,6 @@ omap_otg_init(struct omap_usb_config *config)
 
 		syscon &= ~DEV_IDLE_EN;
 		udc_device->dev.platform_data = config;
-		/* IRQ numbers for omap7xx */
-		if(cpu_is_omap7xx()) {
-			udc_resources[1].start = INT_7XX_USB_GENI;
-			udc_resources[2].start = INT_7XX_USB_NON_ISO;
-			udc_resources[3].start = INT_7XX_USB_ISO;
-		}
 		status = platform_device_register(udc_device);
 		if (status)
 			pr_debug("can't register UDC device, %d\n", status);
@@ -542,8 +115,6 @@ omap_otg_init(struct omap_usb_config *config)
 
 		syscon &= ~HST_IDLE_EN;
 		ohci_device->dev.platform_data = config;
-		if (cpu_is_omap7xx())
-			ohci_resources[1].start = INT_7XX_USB_HHC_1;
 		status = platform_device_register(ohci_device);
 		if (status)
 			pr_debug("can't register OHCI device, %d\n", status);
@@ -556,8 +127,6 @@ omap_otg_init(struct omap_usb_config *config)
 
 		syscon &= ~OTG_IDLE_EN;
 		otg_device->dev.platform_data = config;
-		if (cpu_is_omap7xx())
-			otg_resources[1].start = INT_7XX_USB_OTG;
 		status = platform_device_register(otg_device);
 		if (status)
 			pr_debug("can't register OTG device, %d\n", status);
@@ -572,107 +141,3 @@ omap_otg_init(struct omap_usb_config *config)
 #else
 void omap_otg_init(struct omap_usb_config *config) {}
 #endif
-
-/*-------------------------------------------------------------------------*/
-
-#ifdef	CONFIG_ARCH_OMAP15XX
-
-/* ULPD_DPLL_CTRL */
-#define DPLL_IOB		(1 << 13)
-#define DPLL_PLL_ENABLE		(1 << 4)
-#define DPLL_LOCK		(1 << 0)
-
-/* ULPD_APLL_CTRL */
-#define APLL_NDPLL_SWITCH	(1 << 0)
-
-
-static void __init omap_1510_usb_init(struct omap_usb_config *config)
-{
-	unsigned int val;
-	u16 w;
-
-	config->usb0_init(config->pins[0], is_usb0_device(config));
-	config->usb1_init(config->pins[1]);
-	config->usb2_init(config->pins[2], 0);
-
-	val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1);
-	val |= (config->hmc_mode << 1);
-	omap_writel(val, MOD_CONF_CTRL_0);
-
-	printk("USB: hmc %d", config->hmc_mode);
-	if (config->pins[0])
-		printk(", usb0 %d wires%s", config->pins[0],
-			is_usb0_device(config) ? " (dev)" : "");
-	if (config->pins[1])
-		printk(", usb1 %d wires", config->pins[1]);
-	if (config->pins[2])
-		printk(", usb2 %d wires", config->pins[2]);
-	printk("\n");
-
-	/* use DPLL for 48 MHz function clock */
-	pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
-			omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
-
-	w = omap_readw(ULPD_APLL_CTRL);
-	w &= ~APLL_NDPLL_SWITCH;
-	omap_writew(w, ULPD_APLL_CTRL);
-
-	w = omap_readw(ULPD_DPLL_CTRL);
-	w |= DPLL_IOB | DPLL_PLL_ENABLE;
-	omap_writew(w, ULPD_DPLL_CTRL);
-
-	w = omap_readw(ULPD_SOFT_REQ);
-	w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
-	omap_writew(w, ULPD_SOFT_REQ);
-
-	while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
-		cpu_relax();
-
-#ifdef	CONFIG_USB_GADGET_OMAP
-	if (config->register_dev) {
-		int status;
-
-		udc_device.dev.platform_data = config;
-		status = platform_device_register(&udc_device);
-		if (status)
-			pr_debug("can't register UDC device, %d\n", status);
-		/* udc driver gates 48MHz by D+ pullup */
-	}
-#endif
-
-#if	defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-	if (config->register_host) {
-		int status;
-
-		ohci_device.dev.platform_data = config;
-		status = platform_device_register(&ohci_device);
-		if (status)
-			pr_debug("can't register OHCI device, %d\n", status);
-		/* hcd explicitly gates 48MHz */
-	}
-#endif
-}
-
-#else
-static inline void omap_1510_usb_init(struct omap_usb_config *config) {}
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-void __init omap_usb_init(struct omap_usb_config *pdata)
-{
-	pdata->usb0_init = omap_usb0_init;
-	pdata->usb1_init = omap_usb1_init;
-	pdata->usb2_init = omap_usb2_init;
-	udc_device_init(pdata);
-	ohci_device_init(pdata);
-	otg_device_init(pdata);
-
-	if (cpu_is_omap7xx() || cpu_is_omap16xx())
-		omap_otg_init(pdata);
-	else if (cpu_is_omap15xx())
-		omap_1510_usb_init(pdata);
-	else
-		printk(KERN_ERR "USB: No init for your chip yet\n");
-}
-



From cbouatmailru at gmail.com  Tue Jun 29 08:07:24 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Tue, 29 Jun 2010 16:07:24 +0400
Subject: [PATCH 1/6] omap: Disable VGA console for omaps
In-Reply-To: <20100629114720.16008.84291.stgit@baageli.muru.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
	<20100629114720.16008.84291.stgit@baageli.muru.com>
Message-ID: <20100629120724.GA23884@oksana.dev.rtsoft.ru>

On Tue, Jun 29, 2010 at 02:47:20PM +0300, Tony Lindgren wrote:
> Otherwise we have to disable it manually to avoid compile errors.
> 
> Cc: linux-fbdev at vger.kernel.org
> Signed-off-by: Tony Lindgren <tony at atomide.com>

We'll need this for mach-cns3xxx too. And doing that change for
every ARM subarch is going to produce lots of rejects.

I'd suggest to disable (or make it 'default n') for all ARMs,
except these:

$ git grep VGA_CONSOLE= arch/arm/configs/
arch/arm/configs/footbridge_defconfig:CONFIG_VGA_CONSOLE=y
arch/arm/configs/integrator_defconfig:CONFIG_VGA_CONSOLE=y
arch/arm/configs/netwinder_defconfig:CONFIG_VGA_CONSOLE=y

Thanks!

> ---
>  drivers/video/console/Kconfig |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/video/console/Kconfig b/drivers/video/console/Kconfig
> index 8e8f18d..467a966 100644
> --- a/drivers/video/console/Kconfig
> +++ b/drivers/video/console/Kconfig
> @@ -6,7 +6,7 @@ menu "Console display driver support"
>  
>  config VGA_CONSOLE
>  	bool "VGA text console" if EMBEDDED || !X86
> -	depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BLACKFIN && !AVR32 && !MN10300
> +	depends on !ARCH_ACORN && !ARCH_EBSA110 && !4xx && !8xx && !SPARC && !M68K && !PARISC && !FRV && !ARCH_VERSATILE && !SUPERH && !BLACKFIN && !AVR32 && !MN10300 && !ARCH_OMAP
>  	default y
>  	help
>  	  Saying Y here will allow you to use Linux in text mode through a

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2


From jason77.wang at gmail.com  Tue Jun 29 09:17:27 2010
From: jason77.wang at gmail.com (jason)
Date: Tue, 29 Jun 2010 21:17:27 +0800
Subject: [PATCH] spi/omap2_mcspi: disable and enable chan between each
	SPI 	transfer
In-Reply-To: <E1C7579D1379824DAE67858071C810382DD84963BC@NOK-EUMSG-02.mgdnok.nokia.com>
References: <1277381565-6305-1-git-send-email-jason77.wang@gmail.com>
	<AANLkTin7mqe_zJIbyDcRPpCLaxPhl_dZQrSGua2z1nYW@mail.gmail.com>
	<4C24A182.4060009@gmail.com>
	<E1C7579D1379824DAE67858071C810382DD8495B26@NOK-EUMSG-02.mgdnok.nokia.com>
	<4C289CCB.7010409@gmail.com>
	<E1C7579D1379824DAE67858071C810382DD84963BC@NOK-EUMSG-02.mgdnok.nokia.com>
Message-ID: <4C29F267.9030007@gmail.com>

roman.tereshonkov at nokia.com wrote:
> Hi Jason,
>
> It is a little bit hard to analyze your logs.
> 1. You showed the bytes read in your own way but there is the data reading in omap2_mcspi_txrx_pio function also.
>   
I add polling RXS bit and read rx register after TX_ONLY and before 
triggering RX_ONLY just to prove
this triggering is not necessary(test case1).
> 2. For your third test case. You try to read data after TX_ONLY, before triggering RX_ONLY, and get the right word.
> Looks like there is something wrong.
>   
My 2nd test case is to read data after TX_ONLY and after triggering 
RX_ONLY, get wrong word just as
test case 1.
My 3rd test case revert a commit at first, then to read data after 
TX_ONLY and after triggering RX_ONLY,
this time get right word, the difference between case 3 and case 2 is 
only reverting a commit.
> Try to log MCSPI_CHxSTAT register to follow when RXS bit (register RX is full) is set.
> And do not use the RX register reading in you own way. If you need RX logging do it from omap2_mcspi_txrx_pio function.
>
>   
OK, i will try to generate a log as your suggestion.

Thanks,
Jason.
> Regards
> Roman Tereshonkov
>
>
>   
>> -----Original Message-----
>> From: ext jason [mailto:jason77.wang at gmail.com] 
>> Sent: 28 June, 2010 16:00
>> To: Tereshonkov Roman (Nokia-D/Helsinki)
>> Cc: grant.likely at secretlab.ca; david-b at pacbell.net; 
>> spi-devel-general at lists.sourceforge.net; 
>> linux-arm-kernel at lists.infradead.org
>> Subject: Re: [PATCH] spi/omap2_mcspi: disable and enable chan 
>> between each SPI transfer
>>
>> roman.tereshonkov at nokia.com wrote:
>>     
>>>  
>>>
>>>   
>>>       
>>>> -----Original Message-----
>>>> From: ext jason [mailto:jason77.wang at gmail.com] 
>>>> Sent: 25 June, 2010 15:31
>>>> To: Grant Likely
>>>> Cc: Tereshonkov Roman (Nokia-D/Helsinki); david-b at pacbell.net; 
>>>>     
>>>>     
>>>>         
>> [snip]
>>     
>>>> the RXS bit will be set to status register immediately,
>>>> write a dummy data to TX register to trigger this session(in 
>>>> fact this  
>>>> trigger  doesn't take  effect),
>>>> check the RXS bit and read the first data(the first data is 
>>>>         
>> the last 
>>     
>>>> random data received in TX_ONLY transfer).
>>>>
>>>>     
>>>>         
>>> For me it is very strange that you have RXS bit set after 
>>>       
>> TX_ONLY transmission.
>>     
>>> The problem might be elsewhere and your solution will just 
>>>       
>> mask the real problem.
>>     
>>> Can you enable the spi debug and error logs and show them 
>>>       
>> for your broken case.
>>     
>>> Regards
>>> Roman Tereshonkov
>>>
>>>   
>>>       
>> Hi Roman,
>> I don't know how to enable the spi debug and generate an error 
>> log, but 
>> i design
>> 3 testcases to investigate this issue. These 3 testcases are based off 
>> the latest upstream.
>> test1: After TX_ONLY transfer, we will change this channel to RX_ONLY 
>> mode. And then we
>> will write a dummy data to trigger this RX transaction, here i add a 
>> polling RXS bit
>> before write triggering data, from the result, we can see we 
>> successfully to get a RXS
>> bit and read an unmeaningful data.(this prove the write 
>> triggering data 
>> is not necessary
>> to start a rx transaction).
>> test2: This time i move the polling RXS bit to the location after the 
>> write trigger data, we can get
>> RXS bit as well and read an unmeaningful data too. The data 
>> read out is 
>> identical to the one
>> in test1.(This prove the write trigger data don't take effect in fact).
>> test3: Except i revert the commit a330ce2 "omap2_mcspi: Flush posted 
>> writes", other is same as the test2.
>> But this time, we read out a correct data ads7846 sending out. 
>> (I don't 
>> know why this commit can
>> affect the result, maybe it is time issue. If we can disable this 
>> channel after TX_ONLY transfer and
>> reenable it before RX_ONLY transfer, we will not get RXS bit in test1, 
>> and will read out a correct data
>> both in test2 and test3).
>>
>> Test1 result output & patch:
>> # =====SPI MESSAGE BEGIN=====
>> tansferTX: conf=1123d4, data=93
>> tansferRX: conf=1113d4, data=0
>> rx_data = f0
>> tansferTX: conf=1123d4, data=93
>> tansferRX: conf=1113d4, data=0
>> rx_data = f0
>> *****SPI MESSAGE END*****
>> =====SPI MESSAGE BEGIN=====
>> tansferTX: conf=1123d4, data=93
>> tansferRX: conf=1113d4, data=0
>> rx_data = f0
>> tansferTX: conf=1123d4, data=93
>> tansferRX: conf=1113d4, data=0
>> rx_data = f0
>> *****SPI MESSAGE END*****
>>
>>
>> Subject: [PATCH] SPI/test1: get rx_data in RX_ONLY transfer before 
>> trigger writing
>>
>> get rx_data in RX_ONLY transfer before trigger writing dummy data to
>> TX register.
>>
>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>> ---
>> drivers/spi/omap2_mcspi.c | 19 ++++++++++++++-----
>> 1 files changed, 14 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>> index b3a94ca..ddfe4b0 100644
>> --- a/drivers/spi/omap2_mcspi.c
>> +++ b/drivers/spi/omap2_mcspi.c
>> @@ -893,7 +893,7 @@ static void omap2_mcspi_work(struct 
>> work_struct *work)
>> spi = m->spi;
>> cs = spi->controller_state;
>> cd = spi->controller_data;
>> -
>> + printk("=====SPI MESSAGE BEGIN=====\n");
>> omap2_mcspi_set_enable(spi, 1);
>> list_for_each_entry(t, &m->transfers, transfer_list) {
>> if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
>> @@ -928,17 +928,26 @@ static void omap2_mcspi_work(struct work_struct 
>> *work)
>> if (t->len > ((cs->word_len + 7) >> 3))
>> chconf |= OMAP2_MCSPI_CHCONF_TURBO;
>> }
>> -
>> + printk("tansfer%s: conf=%x, data=%x\n", t->tx_buf ? "TX" : "RX",
>> + chconf, t->tx_buf ? *(u8 *)(t->tx_buf) : 0);
>> mcspi_write_chconf0(spi, chconf);
>>
>> if (t->len) {
>> unsigned count;
>>
>> /* RX_ONLY mode needs dummy data in TX reg */
>> - if (t->tx_buf == NULL)
>> + if (t->tx_buf == NULL) {
>> + u8 rx_data;
>> + if (mcspi_wait_for_reg_bit(cs->base + OMAP2_MCSPI_CHSTAT0,
>> + OMAP2_MCSPI_CHSTAT_RXS) < 0)
>> + dev_err(&spi->dev, "RXS timed out\n");
>> +
>> + rx_data = __raw_readl(cs->base + OMAP2_MCSPI_RX0);
>> + printk("rx_data = %x\n", rx_data);
>> +
>> __raw_writel(0, cs->base
>> + OMAP2_MCSPI_TX0);
>> -
>> + }
>> if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
>> count = omap2_mcspi_txrx_dma(spi, t);
>> else
>> @@ -971,7 +980,7 @@ static void omap2_mcspi_work(struct 
>> work_struct *work)
>> omap2_mcspi_force_cs(spi, 0);
>>
>> omap2_mcspi_set_enable(spi, 0);
>> -
>> + printk("*****SPI MESSAGE END*****\n");
>> m->status = status;
>> m->complete(m->context);
>>
>> -- 
>> 1.5.6.5
>>
>>
>> Test2 result output & patch:
>> # =====SPI MESSAGE BEGIN=====
>> tansferTX: conf=1123d4, data=93
>> tansferRX: conf=1113d4, data=0
>> rx_data = f0
>> tansferTX: conf=1123d4, data=93
>> tansferRX: conf=1113d4, data=0
>> rx_data = f0
>> *****SPI MESSAGE END*****
>> =====SPI MESSAGE BEGIN=====
>> tansferTX: conf=1123d4, data=93
>> tansferRX: conf=1113d4, data=0
>> rx_data = f0
>> tansferTX: conf=1123d4, data=93
>> tansferRX: conf=1113d4, data=0
>> rx_data = f0
>> *****SPI MESSAGE END*****
>>
>> Subject: [PATCH] SPI/test2: get rx_data in RX_ONLY transfer after 
>> trigger writing
>>
>> get rx_data in RX_ONLY transfer after trigger writing dummy data to
>> TX register.
>>
>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>> ---
>> drivers/spi/omap2_mcspi.c | 18 ++++++++++++++----
>> 1 files changed, 14 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>> index b3a94ca..96c508a 100644
>> --- a/drivers/spi/omap2_mcspi.c
>> +++ b/drivers/spi/omap2_mcspi.c
>> @@ -893,7 +893,7 @@ static void omap2_mcspi_work(struct 
>> work_struct *work)
>> spi = m->spi;
>> cs = spi->controller_state;
>> cd = spi->controller_data;
>> -
>> + printk("=====SPI MESSAGE BEGIN=====\n");
>> omap2_mcspi_set_enable(spi, 1);
>> list_for_each_entry(t, &m->transfers, transfer_list) {
>> if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
>> @@ -928,17 +928,27 @@ static void omap2_mcspi_work(struct work_struct 
>> *work)
>> if (t->len > ((cs->word_len + 7) >> 3))
>> chconf |= OMAP2_MCSPI_CHCONF_TURBO;
>> }
>> -
>> + printk("tansfer%s: conf=%x, data=%x\n", t->tx_buf ? "TX" : "RX",
>> + chconf, t->tx_buf ? *(u8 *)(t->tx_buf) : 0);
>> mcspi_write_chconf0(spi, chconf);
>>
>> if (t->len) {
>> unsigned count;
>>
>> /* RX_ONLY mode needs dummy data in TX reg */
>> - if (t->tx_buf == NULL)
>> + if (t->tx_buf == NULL) {
>> + u8 rx_data;
>> __raw_writel(0, cs->base
>> + OMAP2_MCSPI_TX0);
>>
>> + if (mcspi_wait_for_reg_bit(cs->base + OMAP2_MCSPI_CHSTAT0,
>> + OMAP2_MCSPI_CHSTAT_RXS) < 0)
>> + dev_err(&spi->dev, "RXS timed out\n");
>> +
>> + rx_data = __raw_readl(cs->base + OMAP2_MCSPI_RX0);
>> + printk("rx_data = %x\n", rx_data);
>> +
>> + }
>> if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
>> count = omap2_mcspi_txrx_dma(spi, t);
>> else
>> @@ -971,7 +981,7 @@ static void omap2_mcspi_work(struct 
>> work_struct *work)
>> omap2_mcspi_force_cs(spi, 0);
>>
>> omap2_mcspi_set_enable(spi, 0);
>> -
>> + printk("*****SPI MESSAGE END*****\n");
>> m->status = status;
>> m->complete(m->context);
>>
>> -- 
>> 1.5.6.5
>>
>>
>> Test3 result output & patch:
>> # =====SPI MESSAGE BEGIN=====
>> tansferTX: conf=1123d4, data=93
>> tansferRX: conf=1113d4, data=0
>> rx_data = 77
>> tansferTX: conf=1123d4, data=93
>> tansferRX: conf=1113d4, data=0
>> rx_data = 76
>> *****SPI MESSAGE END*****
>> =====SPI MESSAGE BEGIN=====
>> tansferTX: conf=1123d4, data=93
>> tansferRX: conf=1113d4, data=0
>> rx_data = 75
>> tansferTX: conf=1123d4, data=93
>> tansferRX: conf=1113d4, data=0
>> rx_data = 74
>> *****SPI MESSAGE END*****
>>
>> Subject: [PATCH] SPI/test3: get rx_data in RX_ONLY transfer after 
>> trigger writing
>>
>> At frist revert the commit a330ce2 "omap2_mcspi: Flush posted writes",
>> then get rx_data in RX_ONLY transfer after trigger writing dummy data
>> to TX register.
>>
>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>> ---
>> drivers/spi/omap2_mcspi.c | 19 ++++++++++++++-----
>> 1 files changed, 14 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>> index b3a94ca..5d71cad 100644
>> --- a/drivers/spi/omap2_mcspi.c
>> +++ b/drivers/spi/omap2_mcspi.c
>> @@ -204,7 +204,6 @@ static inline void 
>> mcspi_write_chconf0(const struct 
>> spi_device *spi, u32 val)
>>
>> cs->chconf0 = val;
>> mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, val);
>> - mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
>> }
>>
>> static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
>> @@ -893,7 +892,7 @@ static void omap2_mcspi_work(struct 
>> work_struct *work)
>> spi = m->spi;
>> cs = spi->controller_state;
>> cd = spi->controller_data;
>> -
>> + printk("=====SPI MESSAGE BEGIN=====\n");
>> omap2_mcspi_set_enable(spi, 1);
>> list_for_each_entry(t, &m->transfers, transfer_list) {
>> if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
>> @@ -928,17 +927,27 @@ static void omap2_mcspi_work(struct work_struct 
>> *work)
>> if (t->len > ((cs->word_len + 7) >> 3))
>> chconf |= OMAP2_MCSPI_CHCONF_TURBO;
>> }
>> -
>> + printk("tansfer%s: conf=%x, data=%x\n", t->tx_buf ? "TX" : "RX",
>> + chconf, t->tx_buf ? *(u8 *)(t->tx_buf) : 0);
>> mcspi_write_chconf0(spi, chconf);
>>
>> if (t->len) {
>> unsigned count;
>>
>> /* RX_ONLY mode needs dummy data in TX reg */
>> - if (t->tx_buf == NULL)
>> + if (t->tx_buf == NULL) {
>> + u8 rx_data;
>> __raw_writel(0, cs->base
>> + OMAP2_MCSPI_TX0);
>>
>> + if (mcspi_wait_for_reg_bit(cs->base + OMAP2_MCSPI_CHSTAT0,
>> + OMAP2_MCSPI_CHSTAT_RXS) < 0)
>> + dev_err(&spi->dev, "RXS timed out\n");
>> +
>> + rx_data = __raw_readl(cs->base + OMAP2_MCSPI_RX0);
>> + printk("rx_data = %x\n", rx_data);
>> +
>> + }
>> if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
>> count = omap2_mcspi_txrx_dma(spi, t);
>> else
>> @@ -971,7 +980,7 @@ static void omap2_mcspi_work(struct 
>> work_struct *work)
>> omap2_mcspi_force_cs(spi, 0);
>>
>> omap2_mcspi_set_enable(spi, 0);
>> -
>> + printk("*****SPI MESSAGE END*****\n");
>> m->status = status;
>> m->complete(m->context);
>>
>> -- 
>> 1.5.6.5
>>
>>
>>
>>
>>
>>
>>     
>>>> But if we disable this channel after the TX_ONLY  transfer and 
>>>> reenable 
>>>> it  before  the RX_ONLY  transfer,
>>>> the trigger action will take effect and a meaningful data  will be  
>>>> transfered to RX register.
>>>>
>>>> Thanks,
>>>> Jason.
>>>>
>>>>     
>>>>         
>>>>>> Signed-off-by: Jason Wang <jason77.wang at gmail.com>
>>>>>> ---
>>>>>>  drivers/spi/omap2_mcspi.c |   16 ++++++----------
>>>>>>  1 files changed, 6 insertions(+), 10 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
>>>>>>     
>>>>>>         
>>>>>>             
>>>> [snip]
>>>>
>>>>     
>>>>         
>>     



From schindele at nentec.de  Tue Jun 29 09:29:43 2010
From: schindele at nentec.de (Juergen Schindele)
Date: Tue, 29 Jun 2010 15:29:43 +0200
Subject: [PATCH v5] libata: pata_samsung: Add Samsung PATA controller
	driver
In-Reply-To: <1277809518-1122-1-git-send-email-kgene.kim@samsung.com>
References: <1277809518-1122-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <201006291529.45822.schindele@nentec.de>

Am Dienstag, 29. Juni 2010 schrieb Kukjin Kim:
> From: Abhilash Kesavan <a.kesavan at samsung.com>
> 
> Adds support for the Samsung PATA controller. This driver is based on the
> Libata subsystem and references the earlier patches sent for IDE subsystem.
Dear Kukjin Kim,
as i had trouble with CF / trueIDE on PXA, have you read this thread ??
<http://www.spinics.net/lists/arm-kernel/msg91461.html>
Are you sure you dont need a "dcache_flush-page" ???
Its just a thought to help you avoid problems.

Bye
> Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> Cc: Ben Dooks <ben-linux at fluff.org>
> ---
>  drivers/ata/Kconfig           |    9 +
>  drivers/ata/Makefile          |    1 +
>  drivers/ata/pata_samsung_cf.c |  728 +++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 738 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/ata/pata_samsung_cf.c
> 
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index 73f8833..51e28e7 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -796,6 +796,15 @@ config PATA_RZ1000
>  
>  	  If unsure, say N.
>  
> +config PATA_SAMSUNG_CF
> +	tristate "Samsung SoC PATA support"
> +	depends on SAMSUNG_DEV_IDE
> +	help
> +	  This option enables basic support for Samsung's S3C/S5P board
> +	  PATA controllers via the new ATA layer
> +
> +	  If unsure, say N.
> +
>  config PATA_WINBOND_VLB
>  	tristate "Winbond W83759A VLB PATA support (Experimental)"
>  	depends on ISA && EXPERIMENTAL
> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> index 7ef89d7..9576776 100644
> --- a/drivers/ata/Makefile
> +++ b/drivers/ata/Makefile
> @@ -87,6 +87,7 @@ obj-$(CONFIG_PATA_OF_PLATFORM)	+= pata_of_platform.o
>  obj-$(CONFIG_PATA_QDI)		+= pata_qdi.o
>  obj-$(CONFIG_PATA_RB532)	+= pata_rb532_cf.o
>  obj-$(CONFIG_PATA_RZ1000)	+= pata_rz1000.o
> +obj-$(CONFIG_PATA_SAMSUNG_CF)	+= pata_samsung_cf.o
>  obj-$(CONFIG_PATA_WINBOND_VLB)	+= pata_winbond.o
>  
>  # Should be last but two libata driver
> diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
> new file mode 100644
> index 0000000..26b96c3
> --- /dev/null
> +++ b/drivers/ata/pata_samsung_cf.c
> @@ -0,0 +1,728 @@
> +/*
> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * PATA driver for Samsung SoCs.
> + * Supports CF Interface in True IDE mode. Currently only PIO mode has been
> + * implemented; UDMA support has to be added.
> + *
> + * Based on:
> + *	PATA driver for AT91SAM9260 Static Memory Controller
> + *	PATA driver for Toshiba SCC controller
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2
> + * as published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/clk.h>
> +#include <linux/libata.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include <plat/ata.h>
> +#include <plat/regs-ata.h>
> +
> +#define DRV_NAME "pata_samsung_cf"
> +#define DRV_VERSION "0.1"
> +
> +enum s3c_cpu_type {
> +	TYPE_S3C64XX,
> +	TYPE_S5PC100,
> +	TYPE_S5PV210,
> +};
> +
> +/*
> + * struct s3c_ide_info - S3C PATA instance.
> + * @clk: The clock resource for this controller.
> + * @ide_addr: The area mapped for the hardware registers.
> + * @sfr_addr: The area mapped for the special function registers.
> + * @irq: The IRQ number we are using.
> + * @cpu_type: The exact type of this controller.
> + * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
> + */
> +struct s3c_ide_info {
> +	struct clk *clk;
> +	void __iomem *ide_addr;
> +	void __iomem *sfr_addr;
> +	unsigned int irq;
> +	enum s3c_cpu_type cpu_type;
> +	unsigned int fifo_status_reg;
> +};
> +
> +static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
> +{
> +	u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
> +	reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
> +	writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
> +}
> +
> +static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
> +{
> +	/* Select true-ide as the internal operating mode */
> +	writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
> +		s3c_ide_sfrbase + S3C_CFATA_MUX);
> +}
> +
> +static unsigned long
> +pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
> +{
> +	int t1 = ata->setup;
> +	int t2 = ata->act8b;
> +	int t2i = ata->rec8b;
> +	ulong piotime;
> +
> +	piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
> +
> +	return piotime;
> +}
> +
> +static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
> +{
> +	struct s3c_ide_info *info = ap->host->private_data;
> +	struct ata_timing timing;
> +	int cycle_time;
> +	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
> +	ulong piotime;
> +
> +	/* Enables IORDY if mode requires it */
> +	if (ata_pio_need_iordy(adev))
> +		ata_cfg |= S3C_ATA_CFG_IORDYEN;
> +	else
> +		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
> +
> +	cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
> +
> +	ata_timing_compute(adev, adev->pio_mode, &timing,
> +					cycle_time * 1000, 0);
> +
> +	piotime = pata_s3c_setup_timing(info, &timing);
> +
> +	writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
> +	writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
> +}
> +
> +/*
> + * Waits until the IDE controller is able to perform next read/write
> + * operation to the disk. Needed for 64XX series boards only.
> + */
> +static int wait_for_host_ready(struct s3c_ide_info *info)
> +{
> +	ulong timeout;
> +	void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
> +
> +	/* wait for maximum of 20 msec */
> +	timeout = jiffies + msecs_to_jiffies(20);
> +	while (time_before(jiffies, timeout)) {
> +		if ((readl(fifo_reg) >> 28) == 0)
> +			return 0;
> +	}
> +	return -EBUSY;
> +}
> +
> +/*
> + * Writes to one of the task file registers.
> + */
> +static void ata_outb(struct ata_host *host, u8 addr, void __iomem *reg)
> +{
> +	struct s3c_ide_info *info = host->private_data;
> +
> +	wait_for_host_ready(info);
> +	writeb(addr, reg);
> +}
> +
> +/*
> + * Reads from one of the task file registers.
> + */
> +static u8 ata_inb(struct ata_host *host, void __iomem *reg)
> +{
> +	struct s3c_ide_info *info = host->private_data;
> +	u8 temp;
> +
> +	wait_for_host_ready(info);
> +	(void) readb(reg);
> +	wait_for_host_ready(info);
> +	temp = readb(info->ide_addr + S3C_ATA_PIO_RDATA);
> +	return temp;
> +}
> +
> +/*
> + * pata_s3c_tf_load - send taskfile registers to host controller
> + */
> +static void pata_s3c_tf_load(struct ata_port *ap,
> +				const struct ata_taskfile *tf)
> +{
> +	struct ata_ioports *ioaddr = &ap->ioaddr;
> +	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
> +
> +	if (tf->ctl != ap->last_ctl) {
> +		ata_outb(ap->host, tf->ctl, ioaddr->ctl_addr);
> +		ap->last_ctl = tf->ctl;
> +		ata_wait_idle(ap);
> +	}
> +
> +	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
> +		ata_outb(ap->host, tf->hob_feature, ioaddr->feature_addr);
> +		ata_outb(ap->host, tf->hob_nsect, ioaddr->nsect_addr);
> +		ata_outb(ap->host, tf->hob_lbal, ioaddr->lbal_addr);
> +		ata_outb(ap->host, tf->hob_lbam, ioaddr->lbam_addr);
> +		ata_outb(ap->host, tf->hob_lbah, ioaddr->lbah_addr);
> +	}
> +
> +	if (is_addr) {
> +		ata_outb(ap->host, tf->feature, ioaddr->feature_addr);
> +		ata_outb(ap->host, tf->nsect, ioaddr->nsect_addr);
> +		ata_outb(ap->host, tf->lbal, ioaddr->lbal_addr);
> +		ata_outb(ap->host, tf->lbam, ioaddr->lbam_addr);
> +		ata_outb(ap->host, tf->lbah, ioaddr->lbah_addr);
> +	}
> +
> +	if (tf->flags & ATA_TFLAG_DEVICE)
> +		ata_outb(ap->host, tf->device, ioaddr->device_addr);
> +
> +	ata_wait_idle(ap);
> +}
> +
> +/*
> + * pata_s3c_tf_read - input device's ATA taskfile shadow registers
> + */
> +static void pata_s3c_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
> +{
> +	struct ata_ioports *ioaddr = &ap->ioaddr;
> +
> +	tf->feature = ata_inb(ap->host, ioaddr->error_addr);
> +	tf->nsect = ata_inb(ap->host, ioaddr->nsect_addr);
> +	tf->lbal = ata_inb(ap->host, ioaddr->lbal_addr);
> +	tf->lbam = ata_inb(ap->host, ioaddr->lbam_addr);
> +	tf->lbah = ata_inb(ap->host, ioaddr->lbah_addr);
> +	tf->device = ata_inb(ap->host, ioaddr->device_addr);
> +
> +	if (tf->flags & ATA_TFLAG_LBA48) {
> +		iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
> +		tf->hob_feature = ata_inb(ap->host, ioaddr->error_addr);
> +		tf->hob_nsect = ata_inb(ap->host, ioaddr->nsect_addr);
> +		tf->hob_lbal = ata_inb(ap->host, ioaddr->lbal_addr);
> +		tf->hob_lbam = ata_inb(ap->host, ioaddr->lbam_addr);
> +		tf->hob_lbah = ata_inb(ap->host, ioaddr->lbah_addr);
> +		iowrite8(tf->ctl, ioaddr->ctl_addr);
> +		ap->last_ctl = tf->ctl;
> +	}
> +}
> +
> +/*
> + * pata_s3c_exec_command - issue ATA command to host controller
> + */
> +static void pata_s3c_exec_command(struct ata_port *ap,
> +				const struct ata_taskfile *tf)
> +{
> +	ata_outb(ap->host, tf->command, ap->ioaddr.command_addr);
> +	ata_sff_pause(ap);
> +}
> +
> +/*
> + * pata_s3c_check_status - Read device status register
> + */
> +static u8 pata_s3c_check_status(struct ata_port *ap)
> +{
> +	return ata_inb(ap->host, ap->ioaddr.status_addr);
> +}
> +
> +/*
> + * pata_s3c_check_altstatus - Read alternate device status register
> + */
> +static u8 pata_s3c_check_altstatus(struct ata_port *ap)
> +{
> +	return ata_inb(ap->host, ap->ioaddr.altstatus_addr);
> +}
> +
> +/*
> + * pata_s3c_data_xfer - Transfer data by PIO
> + */
> +unsigned int pata_s3c_data_xfer(struct ata_device *dev, unsigned char *buf,
> +				unsigned int buflen, int rw)
> +{
> +	struct ata_port *ap = dev->link->ap;
> +	struct s3c_ide_info *info = ap->host->private_data;
> +	void __iomem *data_addr = ap->ioaddr.data_addr;
> +	unsigned int words = buflen >> 1, i;
> +	u16 *data_ptr = (u16 *)buf;
> +
> +	/* Requires wait same as in ata_inb/ata_outb */
> +	if (rw == READ)
> +		for (i = 0; i < words; i++, data_ptr++) {
> +			wait_for_host_ready(info);
> +			(void) readw(data_addr);
> +			wait_for_host_ready(info);
> +			*data_ptr = readw(info->ide_addr
> +					+ S3C_ATA_PIO_RDATA);
> +		}
> +	else
> +		for (i = 0; i < words; i++, data_ptr++) {
> +			wait_for_host_ready(info);
> +			writew(*data_ptr, data_addr);
> +		}
> +
> +	if (buflen & 0x01)
> +		dev_err(ap->dev, "unexpected trailing data\n");
> +
> +	return words << 1;
> +}
> +
> +/*
> + * pata_s3c_dev_select - Select device on ATA bus
> + */
> +static void pata_s3c_dev_select(struct ata_port *ap, unsigned int device)
> +{
> +	u8 tmp = ATA_DEVICE_OBS;
> +
> +	if (device != 0)
> +		tmp |= ATA_DEV1;
> +
> +	ata_outb(ap->host, tmp, ap->ioaddr.device_addr);
> +	ata_sff_pause(ap);
> +}
> +
> +/*
> + * pata_s3c_devchk - PATA device presence detection
> + */
> +static unsigned int pata_s3c_devchk(struct ata_port *ap,
> +				unsigned int device)
> +{
> +	struct ata_ioports *ioaddr = &ap->ioaddr;
> +	u8 nsect, lbal;
> +
> +	pata_s3c_dev_select(ap, device);
> +
> +	ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
> +	ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
> +
> +	ata_outb(ap->host, 0xaa, ioaddr->nsect_addr);
> +	ata_outb(ap->host, 0x55, ioaddr->lbal_addr);
> +
> +	ata_outb(ap->host, 0x55, ioaddr->nsect_addr);
> +	ata_outb(ap->host, 0xaa, ioaddr->lbal_addr);
> +
> +	nsect = ata_inb(ap->host, ioaddr->nsect_addr);
> +	lbal = ata_inb(ap->host, ioaddr->lbal_addr);
> +
> +	if ((nsect == 0x55) && (lbal == 0xaa))
> +		return 1;	/* we found a device */
> +
> +	return 0;		/* nothing found */
> +}
> +
> +/*
> + * pata_s3c_wait_after_reset - wait for devices to become ready after reset
> + */
> +static int pata_s3c_wait_after_reset(struct ata_link *link,
> +		unsigned int devmask, unsigned long deadline)
> +{
> +	struct ata_port *ap = link->ap;
> +	struct ata_ioports *ioaddr = &ap->ioaddr;
> +	unsigned int dev0 = devmask & (1 << 0);
> +	unsigned int dev1 = devmask & (1 << 1);
> +	int rc, ret = 0;
> +
> +	msleep(ATA_WAIT_AFTER_RESET);
> +
> +	/* always check readiness of the master device */
> +	rc = ata_sff_wait_ready(link, deadline);
> +	/* -ENODEV means the odd clown forgot the D7 pulldown resistor
> +	 * and TF status is 0xff, bail out on it too.
> +	 */
> +	if (rc)
> +		return rc;
> +
> +	/* if device 1 was found in ata_devchk, wait for register
> +	 * access briefly, then wait for BSY to clear.
> +	 */
> +	if (dev1) {
> +		int i;
> +
> +		pata_s3c_dev_select(ap, 1);
> +
> +		/* Wait for register access.  Some ATAPI devices fail
> +		 * to set nsect/lbal after reset, so don't waste too
> +		 * much time on it.  We're gonna wait for !BSY anyway.
> +		 */
> +		for (i = 0; i < 2; i++) {
> +			u8 nsect, lbal;
> +
> +			nsect = ata_inb(ap->host, ioaddr->nsect_addr);
> +			lbal = ata_inb(ap->host, ioaddr->lbal_addr);
> +			if ((nsect == 1) && (lbal == 1))
> +				break;
> +			msleep(50);	/* give drive a breather */
> +		}
> +
> +		rc = ata_sff_wait_ready(link, deadline);
> +		if (rc) {
> +			if (rc != -ENODEV)
> +				return rc;
> +			ret = rc;
> +		}
> +	}
> +
> +	/* is all this really necessary? */
> +	pata_s3c_dev_select(ap, 0);
> +	if (dev1)
> +		pata_s3c_dev_select(ap, 1);
> +	if (dev0)
> +		pata_s3c_dev_select(ap, 0);
> +
> +	return ret;
> +}
> +
> +/*
> + * pata_s3c_bus_softreset - PATA device software reset
> + */
> +static unsigned int pata_s3c_bus_softreset(struct ata_port *ap,
> +		unsigned int devmask, unsigned long deadline)
> +{
> +	struct ata_ioports *ioaddr = &ap->ioaddr;
> +
> +	/* software reset.  causes dev0 to be selected */
> +	ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
> +	udelay(20);
> +	ata_outb(ap->host, ap->ctl | ATA_SRST, ioaddr->ctl_addr);
> +	udelay(20);
> +	ata_outb(ap->host, ap->ctl, ioaddr->ctl_addr);
> +	ap->last_ctl = ap->ctl;
> +
> +	return pata_s3c_wait_after_reset(&ap->link, devmask, deadline);
> +}
> +
> +/*
> + * pata_s3c_softreset - reset host port via ATA SRST
> + */
> +static int pata_s3c_softreset(struct ata_link *link, unsigned int *classes,
> +			 unsigned long deadline)
> +{
> +	struct ata_port *ap = link->ap;
> +	unsigned int devmask = 0;
> +	int rc;
> +	u8 err;
> +
> +	/* determine if device 0/1 are present */
> +	if (pata_s3c_devchk(ap, 0))
> +		devmask |= (1 << 0);
> +
> +	/* select device 0 again */
> +	pata_s3c_dev_select(ap, 0);
> +
> +	/* issue bus reset */
> +	rc = pata_s3c_bus_softreset(ap, devmask, deadline);
> +	/* if link is occupied, -ENODEV too is an error */
> +	if (rc && rc != -ENODEV) {
> +		ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
> +		return rc;
> +	}
> +
> +	/* determine by signature whether we have ATA or ATAPI devices */
> +	classes[0] = ata_sff_dev_classify(&ap->link.device[0],
> +					  devmask & (1 << 0), &err);
> +
> +	return 0;
> +}
> +
> +/*
> + * pata_s3c_set_devctl - Write device control register
> + */
> +static void pata_s3c_set_devctl(struct ata_port *ap, u8 ctl)
> +{
> +	ata_outb(ap->host, ctl, ap->ioaddr.ctl_addr);
> +}
> +
> +static struct scsi_host_template pata_s3c_sht = {
> +	ATA_PIO_SHT(DRV_NAME),
> +};
> +
> +static struct ata_port_operations pata_s3c_port_ops = {
> +	.inherits		= &ata_sff_port_ops,
> +	.sff_check_status	= pata_s3c_check_status,
> +	.sff_check_altstatus    = pata_s3c_check_altstatus,
> +	.sff_tf_load		= pata_s3c_tf_load,
> +	.sff_tf_read		= pata_s3c_tf_read,
> +	.sff_data_xfer		= pata_s3c_data_xfer,
> +	.sff_exec_command	= pata_s3c_exec_command,
> +	.sff_dev_select         = pata_s3c_dev_select,
> +	.sff_set_devctl         = pata_s3c_set_devctl,
> +	.softreset		= pata_s3c_softreset,
> +	.set_piomode		= pata_s3c_set_piomode,
> +};
> +
> +static struct ata_port_operations pata_s5p_port_ops = {
> +	.inherits		= &ata_sff_port_ops,
> +	.set_piomode		= pata_s3c_set_piomode,
> +};
> +
> +static void pata_s3c_enable(void *s3c_ide_regbase, bool state)
> +{
> +	u32 temp = readl(s3c_ide_regbase + S3C_ATA_CTRL);
> +	temp = state ? (temp | 1) : (temp & ~1);
> +	writel(temp, s3c_ide_regbase + S3C_ATA_CTRL);
> +}
> +
> +static irqreturn_t pata_s3c_irq(int irq, void *dev_instance)
> +{
> +	struct ata_host *host = dev_instance;
> +	struct s3c_ide_info *info = host->private_data;
> +	u32 reg;
> +
> +	reg = readl(info->ide_addr + S3C_ATA_IRQ);
> +	writel(reg, info->ide_addr + S3C_ATA_IRQ);
> +
> +	return ata_sff_interrupt(irq, dev_instance);
> +}
> +
> +static void pata_s3c_hwinit(struct s3c_ide_info *info,
> +				struct s3c_ide_platdata *pdata)
> +{
> +	switch (info->cpu_type) {
> +	case TYPE_S3C64XX:
> +		/* Configure as big endian */
> +		pata_s3c_cfg_mode(info->sfr_addr);
> +		pata_s3c_set_endian(info->ide_addr, 1);
> +		pata_s3c_enable(info->ide_addr, true);
> +		msleep(100);
> +
> +		/* Remove IRQ Status */
> +		writel(0x1f, info->ide_addr + S3C_ATA_IRQ);
> +		writel(0x1b, info->ide_addr + S3C_ATA_IRQ_MSK);
> +		break;
> +
> +	case TYPE_S5PC100:
> +		pata_s3c_cfg_mode(info->sfr_addr);
> +		/* FALLTHROUGH */
> +
> +	case TYPE_S5PV210:
> +		/* Configure as little endian */
> +		pata_s3c_set_endian(info->ide_addr, 0);
> +		pata_s3c_enable(info->ide_addr, true);
> +		msleep(100);
> +
> +		/* Remove IRQ Status */
> +		writel(0x3f, info->ide_addr + S3C_ATA_IRQ);
> +		writel(0x3f, info->ide_addr + S3C_ATA_IRQ_MSK);
> +		break;
> +
> +	default:
> +		BUG();
> +	}
> +}
> +
> +static int __init pata_s3c_probe(struct platform_device *pdev)
> +{
> +	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
> +	struct device *dev = &pdev->dev;
> +	struct s3c_ide_info *info;
> +	struct resource *res;
> +	struct ata_port *ap;
> +	struct ata_host *host;
> +	enum s3c_cpu_type cpu_type;
> +	int ret;
> +
> +	cpu_type = platform_get_device_id(pdev)->driver_data;
> +
> +	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
> +	if (!info) {
> +		dev_err(dev, "failed to allocate memory for device data\n");
> +		return -ENOMEM;
> +	}
> +
> +	info->irq = platform_get_irq(pdev, 0);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (res == NULL) {
> +		dev_err(dev, "failed to get mem resource\n");
> +		return -EINVAL;
> +	}
> +
> +	if (!devm_request_mem_region(dev, res->start,
> +				resource_size(res), DRV_NAME)) {
> +		dev_err(dev, "error requesting register region\n");
> +		return -EBUSY;
> +	}
> +
> +	info->ide_addr = devm_ioremap(dev, res->start, resource_size(res));
> +	if (!info->ide_addr) {
> +		dev_err(dev, "failed to map IO base address\n");
> +		return -ENOMEM;
> +	}
> +
> +	info->clk = clk_get(&pdev->dev, "cfcon");
> +	if (IS_ERR(info->clk)) {
> +		dev_err(dev, "failed to get access to cf controller clock\n");
> +		ret = PTR_ERR(info->clk);
> +		info->clk = NULL;
> +		return ret;
> +	}
> +
> +	clk_enable(info->clk);
> +
> +	/* init ata host */
> +	host = ata_host_alloc(dev, 1);
> +	if (!host) {
> +		dev_err(dev, "failed to allocate ide host\n");
> +		ret = -ENOMEM;
> +		goto stop_clk;
> +	}
> +
> +	ap = host->ports[0];
> +	ap->flags |= ATA_FLAG_MMIO;
> +	ap->pio_mask = ATA_PIO4;
> +
> +	if (cpu_type == TYPE_S3C64XX) {
> +		ap->ops = &pata_s3c_port_ops;
> +		info->sfr_addr = info->ide_addr + 0x1800;
> +		info->ide_addr += 0x1900;
> +		info->fifo_status_reg = 0x94;
> +	} else if (cpu_type == TYPE_S5PC100) {
> +		ap->ops = &pata_s5p_port_ops;
> +		info->sfr_addr = info->ide_addr + 0x1800;
> +		info->ide_addr += 0x1900;
> +		info->fifo_status_reg = 0x84;
> +	} else {
> +		ap->ops = &pata_s5p_port_ops;
> +		info->fifo_status_reg = 0x84;
> +	}
> +
> +	info->cpu_type = cpu_type;
> +
> +	if (info->irq <= 0) {
> +		ap->flags |= ATA_FLAG_PIO_POLLING;
> +		info->irq = 0;
> +		ata_port_desc(ap, "no IRQ, using PIO polling\n");
> +	}
> +
> +	ap->ioaddr.cmd_addr =  info->ide_addr + S3C_ATA_CMD;
> +	ap->ioaddr.data_addr = info->ide_addr + S3C_ATA_PIO_DTR;
> +	ap->ioaddr.error_addr = info->ide_addr + S3C_ATA_PIO_FED;
> +	ap->ioaddr.feature_addr = info->ide_addr + S3C_ATA_PIO_FED;
> +	ap->ioaddr.nsect_addr = info->ide_addr + S3C_ATA_PIO_SCR;
> +	ap->ioaddr.lbal_addr = info->ide_addr + S3C_ATA_PIO_LLR;
> +	ap->ioaddr.lbam_addr = info->ide_addr + S3C_ATA_PIO_LMR;
> +	ap->ioaddr.lbah_addr = info->ide_addr + S3C_ATA_PIO_LHR;
> +	ap->ioaddr.device_addr = info->ide_addr + S3C_ATA_PIO_DVR;
> +	ap->ioaddr.status_addr = info->ide_addr + S3C_ATA_PIO_CSD;
> +	ap->ioaddr.command_addr = info->ide_addr + S3C_ATA_PIO_CSD;
> +	ap->ioaddr.altstatus_addr = info->ide_addr + S3C_ATA_PIO_DAD;
> +	ap->ioaddr.ctl_addr = info->ide_addr + S3C_ATA_PIO_DAD;
> +
> +	ata_port_desc(ap, "mmio cmd 0x%llx ",
> +			(unsigned long long)res->start);
> +
> +	host->private_data = info;
> +
> +	if (pdata && pdata->setup_gpio)
> +		pdata->setup_gpio();
> +
> +	/* Set endianness and enable the interface */
> +	pata_s3c_hwinit(info, pdata);
> +
> +	platform_set_drvdata(pdev, host);
> +
> +	return ata_host_activate(host, info->irq,
> +			info->irq ? pata_s3c_irq : NULL,
> +			0, &pata_s3c_sht);
> +
> +stop_clk:
> +	clk_disable(info->clk);
> +	clk_put(info->clk);
> +	return ret;
> +}
> +
> +static int __exit pata_s3c_remove(struct platform_device *pdev)
> +{
> +	struct ata_host *host = platform_get_drvdata(pdev);
> +	struct s3c_ide_info *info;
> +
> +	info = host->private_data;
> +	ata_host_detach(host);
> +
> +	clk_disable(info->clk);
> +	clk_put(info->clk);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int pata_s3c_suspend(struct device *dev)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct ata_host *host = platform_get_drvdata(pdev);
> +	pm_message_t state = PMSG_SUSPEND;
> +
> +	return ata_host_suspend(host, state);
> +}
> +
> +static int pata_s3c_resume(struct device *dev)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct ata_host *host = platform_get_drvdata(pdev);
> +	struct s3c_ide_platdata *pdata = pdev->dev.platform_data;
> +	struct s3c_ide_info *info;
> +
> +	info = host->private_data;
> +
> +	pata_s3c_hwinit(info, pdata);
> +	ata_host_resume(host);
> +
> +	return 0;
> +}
> +
> +static const struct dev_pm_ops pata_s3c_pm_ops = {
> +	.suspend	= pata_s3c_suspend,
> +	.resume		= pata_s3c_resume,
> +};
> +#endif
> +
> +/* driver device registration */
> +static struct platform_device_id pata_s3c_driver_ids[] = {
> +	{
> +		.name		= "s3c64xx-pata",
> +		.driver_data	= TYPE_S3C64XX,
> +	}, {
> +		.name		= "s5pc100-pata",
> +		.driver_data	= TYPE_S5PC100,
> +	}, {
> +		.name		= "s5pv210-pata",
> +		.driver_data	= TYPE_S5PV210,
> +	},
> +	{ }
> +};
> +
> +MODULE_DEVICE_TABLE(platform, pata_s3c_driver_ids);
> +
> +static struct platform_driver pata_s3c_driver = {
> +	.remove		= __exit_p(pata_s3c_remove),
> +	.id_table	= pata_s3c_driver_ids,
> +	.driver		= {
> +		.name	= DRV_NAME,
> +		.owner	= THIS_MODULE,
> +#ifdef CONFIG_PM
> +		.pm	= &pata_s3c_pm_ops,
> +#endif
> +	},
> +};
> +
> +static int __init pata_s3c_init(void)
> +{
> +	return platform_driver_probe(&pata_s3c_driver, pata_s3c_probe);
> +}
> +
> +static void __exit pata_s3c_exit(void)
> +{
> +	platform_driver_unregister(&pata_s3c_driver);
> +}
> +
> +module_init(pata_s3c_init);
> +module_exit(pata_s3c_exit);
> +
> +MODULE_AUTHOR("Abhilash Kesavan, <a.kesavan at samsung.com>");
> +MODULE_DESCRIPTION("low-level driver for Samsung PATA controller");
> +MODULE_LICENSE("GPL");
> +MODULE_VERSION(DRV_VERSION);



-- 
--------------------------------------------------------------
J?rgen Schindele  
Software-Entwicklung

PSI NENTEC GmbH
Greschbachstr. 12
76229 Karlsruhe
Deutschland
Telefon: +49 721 94249-51
Telefax: +49 721 94249-10
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Sitz der Gesellschaft: Karlsruhe
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From santosh.shilimkar at ti.com  Tue Jun 29 09:53:15 2010
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 29 Jun 2010 19:23:15 +0530
Subject: [PATCH 6/6] omap2/3/4: Add Kconfig option to compile in typical
	omap	features
In-Reply-To: <20100629114738.16008.62006.stgit@baageli.muru.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
	<20100629114738.16008.62006.stgit@baageli.muru.com>
Message-ID: <EAF47CD23C76F840A9E7FCE10091EFAB02C5DB6FC3@dbde02.ent.ti.com>

Tony,
> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Tony Lindgren
> Sent: Tuesday, June 29, 2010 5:18 PM
> To: linux-arm-kernel at lists.infradead.org
> Cc: linux-omap at vger.kernel.org
> Subject: [PATCH 6/6] omap2/3/4: Add Kconfig option to compile in typical
> omap features
> 
> This produces a sane config that's suitable for using as the
> base for most omap2/3/4 boards.
> 
> Signed-off-by: Tony Lindgren <tony at atomide.com>
> ---
>  arch/arm/mach-omap2/Kconfig |   21 +++++++++++++++++++++
>  1 files changed, 21 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 4802988..84fecd0 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -2,6 +2,27 @@ if ARCH_OMAP2PLUS
> 
>  menu "TI OMAP2/3/4 Specific Features"
> 
> +config ARCH_OMAP2PLUS_TYPICAL
> +	bool "Typical OMAP configuration"
> +	default y
> +	select AEABI
> +	select REGULATOR
> +	select PM
> +	select PM_RUNTIME
> +	select VFP
> +	select NEON if ARCH_OMAP3 || ARCH_OMAP4
> +	select SERIAL_8250
> +	select SERIAL_CORE_CONSOLE
> +	select SERIAL_8250_CONSOLE
> +	select I2C
> +	select I2C_OMAP
> +	select MFD
> +	select MENELAUS if ARCH_OMAP2
> +	select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
> +	select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
> +	help
> +	  Compile a kernel suitable for booting most boards
> +
>  config ARCH_OMAP2
>  	bool "TI OMAP2"
>  	depends on ARCH_OMAP2PLUS
> 
With your series OMAP4 build breaks because of PM and SMP dependencies.
To ensure that build doesn't break on OMAP4, I needed below change. With
This change I tried your series and it boots OK on OMAP4430 SDP

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 84fecd0..f48f275 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -7,8 +7,8 @@ config ARCH_OMAP2PLUS_TYPICAL
        default y
        select AEABI
        select REGULATOR
-       select PM
-       select PM_RUNTIME
+       select PM if !ARCH_OMAP4
+       select PM_RUNTIME if !ARCH_OMAP4
        select VFP
        select NEON if ARCH_OMAP3 || ARCH_OMAP4
        select SERIAL_8250

Regards
Santosh





From tony at atomide.com  Tue Jun 29 10:18:36 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 17:18:36 +0300
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100623133636.GC7058@shareable.org>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
	<20100623073912.GA12255@atomide.com>
	<20100623133636.GC7058@shareable.org>
Message-ID: <20100629141836.GM2822@atomide.com>

* Jamie Lokier <jamie at shareable.org> [100623 16:30]:
> Tony Lindgren wrote:
> > * Jamie Lokier <jamie at shareable.org> [100622 19:54]:
> > > Tony Lindgren wrote:
> > > >  __kuser_get_tls:				@ 0xffff0fe0
> > > > -
> > > > -#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
> > > > -	ldr	r0, [pc, #(16 - 8)]		@ TLS stored at 0xffff0ff0
> > > > -#else
> > > > -	mrc	p15, 0, r0, c13, c0, 3		@ read TLS register
> > > > -#endif
> > > > +	ldr     r0, [pc, #(20 - 8)]		@ software TLS set in 0xffff0ff4?
> > > > +	cmp	r0, #0				@ hardware TLS if flag not set
> > > > +	mrceq	p15, 0, r0, c13, c0, 3		@ read hardware TLS register
> > > > +	ldrne	r0, [pc, #(12 - 8)]		@ software TLS val at 0xffff0ff8
> > > >  	usr_ret	lr
> > > > -
> > > > -	.rep	5
> > > > -	.word	0			@ pad up to __kuser_helper_version
> > > > -	.endr
> > > > +	.word	0				@ non-zero for software TLS
> > > > +	.word	0				@ software TLS value
> > > 
> > > It'd be nice not to waste instructions checking for HWCAP_TLS on archs
> > > which definitely don't have it.  I guess it doesn't matter elsewhere;
> > > I'd expect this to be a warm path for some programs making extensive
> > > use of TLS (I haven't measured though).
> > 
> > OK, but let's try to figure out a way that does not add more ifdef else
> > code as that makes it harder to build support for multiple ARM cores.
> >  
> > > As it's only a single instruction, and the code is in a writable page
> > > already (copied at init), how about just patching the instruction
> > > when ELF_HWCAP is set?
> > 
> > Yeah that can be done for __kuser_get_tls if it's always writable.
> > But __switch_to is trickier because of the CONFIG_MMU ifdefs there.
> 
> __kuser_get_tls must be writable in kernels where !HAS_TLS_REG is
> supported, because the TLS value is written to the same page.
> 
> I was thinking of changing *only* __kuser_get_tls, by the way.  Out of
> all the different places, that's the only one I'd expect to be a hot
> path in some TLS-using programs.

OK. Sorry for the delay again. Here's an updated version that sets
__kuser_get_tls instruction dynamically. Does this do what you were
thinking, or did I miss something?

Also, can we detect somehow the hardware that uses CONFIG_TLS_REG_EMUL?
Might be possible to remove that Kconfig option too later on..

Regards,

Tony
-------------- next part --------------
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From tony at atomide.com  Tue Jun 29 10:21:45 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 17:21:45 +0300
Subject: [PATCH 1/6] omap: Disable VGA console for omaps
In-Reply-To: <20100629120724.GA23884@oksana.dev.rtsoft.ru>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
	<20100629114720.16008.84291.stgit@baageli.muru.com>
	<20100629120724.GA23884@oksana.dev.rtsoft.ru>
Message-ID: <20100629142144.GN2822@atomide.com>

* Anton Vorontsov <cbouatmailru at gmail.com> [100629 15:04]:
> On Tue, Jun 29, 2010 at 02:47:20PM +0300, Tony Lindgren wrote:
> > Otherwise we have to disable it manually to avoid compile errors.
> > 
> > Cc: linux-fbdev at vger.kernel.org
> > Signed-off-by: Tony Lindgren <tony at atomide.com>
> 
> We'll need this for mach-cns3xxx too. And doing that change for
> every ARM subarch is going to produce lots of rejects.
> 
> I'd suggest to disable (or make it 'default n') for all ARMs,
> except these:
> 
> $ git grep VGA_CONSOLE= arch/arm/configs/
> arch/arm/configs/footbridge_defconfig:CONFIG_VGA_CONSOLE=y
> arch/arm/configs/integrator_defconfig:CONFIG_VGA_CONSOLE=y
> arch/arm/configs/netwinder_defconfig:CONFIG_VGA_CONSOLE=y

Good idea, will post a modified patch tomorrow.

Tony


From linus.walleij at stericsson.com  Tue Jun 29 07:36:07 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 29 Jun 2010 13:36:07 +0200
Subject: [PATCH 1/2] DMAENGINE: correct PL080 register header file
Message-ID: <1277811367-17694-1-git-send-email-linus.walleij@stericsson.com>

This PL008 among all other variables named PL080 doesn't seem
right. Fix it. Also add some missing defined that I use in the
new PL08x driver.

Cc: Ben Dooks <ben-linux at fluff.org>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
Ben can you ACK this? Shouldn't be any big deal.
---
 arch/arm/include/asm/hardware/pl080.h |    4 +++-
 arch/arm/mach-s3c64xx/dma.c           |    2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/hardware/pl080.h b/arch/arm/include/asm/hardware/pl080.h
index 6a6c66b..f35b86e 100644
--- a/arch/arm/include/asm/hardware/pl080.h
+++ b/arch/arm/include/asm/hardware/pl080.h
@@ -43,7 +43,7 @@
 
 /* Per channel configuration registers */
 
-#define PL008_Cx_STRIDE				(0x20)
+#define PL080_Cx_STRIDE				(0x20)
 #define PL080_Cx_BASE(x)			((0x100 + (x * 0x20)))
 #define PL080_Cx_SRC_ADDR(x)			((0x100 + (x * 0x20)))
 #define PL080_Cx_DST_ADDR(x)			((0x104 + (x * 0x20)))
@@ -68,6 +68,8 @@
 #define PL080_CONTROL_TC_IRQ_EN			(1 << 31)
 #define PL080_CONTROL_PROT_MASK			(0x7 << 28)
 #define PL080_CONTROL_PROT_SHIFT		(28)
+#define PL080_CONTROL_PROT_CACHE		(1 << 30)
+#define PL080_CONTROL_PROT_BUFF			(1 << 29)
 #define PL080_CONTROL_PROT_SYS			(1 << 28)
 #define PL080_CONTROL_DST_INCR			(1 << 27)
 #define PL080_CONTROL_SRC_INCR			(1 << 26)
diff --git a/arch/arm/mach-s3c64xx/dma.c b/arch/arm/mach-s3c64xx/dma.c
index 5567e03..e7d03ab 100644
--- a/arch/arm/mach-s3c64xx/dma.c
+++ b/arch/arm/mach-s3c64xx/dma.c
@@ -697,7 +697,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
 		chptr->number = chno;
 		chptr->dmac = dmac;
 		chptr->regs = regptr;
-		regptr += PL008_Cx_STRIDE;
+		regptr += PL080_Cx_STRIDE;
 	}
 
 	/* for the moment, permanently enable the controller */
-- 
1.7.0.1



From santosh.shilimkar at ti.com  Tue Jun 29 10:46:20 2010
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Tue, 29 Jun 2010 20:16:20 +0530
Subject: [PATCH 6/6] omap2/3/4: Add Kconfig option to compile in typical
	omap	features
In-Reply-To: <EAF47CD23C76F840A9E7FCE10091EFAB02C5DB6FC3@dbde02.ent.ti.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
	<20100629114738.16008.62006.stgit@baageli.muru.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C5DB6FC3@dbde02.ent.ti.com>
Message-ID: <EAF47CD23C76F840A9E7FCE10091EFAB02C5DB7026@dbde02.ent.ti.com>

> -----Original Message-----
> From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> owner at vger.kernel.org] On Behalf Of Shilimkar, Santosh
> Sent: Tuesday, June 29, 2010 7:23 PM
> To: Tony Lindgren; linux-arm-kernel at lists.infradead.org
> Cc: linux-omap at vger.kernel.org
> Subject: RE: [PATCH 6/6] omap2/3/4: Add Kconfig option to compile in
> typical omap features
> 
> Tony,
> > -----Original Message-----
> > From: linux-omap-owner at vger.kernel.org [mailto:linux-omap-
> > owner at vger.kernel.org] On Behalf Of Tony Lindgren
> > Sent: Tuesday, June 29, 2010 5:18 PM
> > To: linux-arm-kernel at lists.infradead.org
> > Cc: linux-omap at vger.kernel.org
> > Subject: [PATCH 6/6] omap2/3/4: Add Kconfig option to compile in typical
> > omap features
> >
> > This produces a sane config that's suitable for using as the
> > base for most omap2/3/4 boards.
> >
> > Signed-off-by: Tony Lindgren <tony at atomide.com>
> > ---
> >  arch/arm/mach-omap2/Kconfig |   21 +++++++++++++++++++++
> >  1 files changed, 21 insertions(+), 0 deletions(-)
> >
> > diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> > index 4802988..84fecd0 100644
> > --- a/arch/arm/mach-omap2/Kconfig
> > +++ b/arch/arm/mach-omap2/Kconfig
> > @@ -2,6 +2,27 @@ if ARCH_OMAP2PLUS
> >
> >  menu "TI OMAP2/3/4 Specific Features"
> >
> > +config ARCH_OMAP2PLUS_TYPICAL
> > +	bool "Typical OMAP configuration"
> > +	default y
> > +	select AEABI
> > +	select REGULATOR
> > +	select PM
> > +	select PM_RUNTIME
> > +	select VFP
> > +	select NEON if ARCH_OMAP3 || ARCH_OMAP4
> > +	select SERIAL_8250
> > +	select SERIAL_CORE_CONSOLE
> > +	select SERIAL_8250_CONSOLE
> > +	select I2C
> > +	select I2C_OMAP
> > +	select MFD
> > +	select MENELAUS if ARCH_OMAP2
> > +	select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
> > +	select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4
> > +	help
> > +	  Compile a kernel suitable for booting most boards
> > +
> >  config ARCH_OMAP2
> >  	bool "TI OMAP2"
> >  	depends on ARCH_OMAP2PLUS
> >
> With your series OMAP4 build breaks because of PM and SMP dependencies.
> To ensure that build doesn't break on OMAP4, I needed below change. With
> This change I tried your series and it boots OK on OMAP4430 SDP
> 
Also tested the multi-omap build on OMAP3430 SDP and OMAP4430 SDP. Both boots OK.

> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index 84fecd0..f48f275 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -7,8 +7,8 @@ config ARCH_OMAP2PLUS_TYPICAL
>         default y
>         select AEABI
>         select REGULATOR
> -       select PM
> -       select PM_RUNTIME
> +       select PM if !ARCH_OMAP4
> +       select PM_RUNTIME if !ARCH_OMAP4
>         select VFP
>         select NEON if ARCH_OMAP3 || ARCH_OMAP4
>         select SERIAL_8250
> 
> Regards
> Santosh
> 
> 
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


From linus.walleij at stericsson.com  Tue Jun 29 07:36:31 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Tue, 29 Jun 2010 13:36:31 +0200
Subject: [PATCH 2/2] DMAENGINE: driver for the ARM PL080/PL081 PrimeCells
Message-ID: <1277811391-17966-1-git-send-email-linus.walleij@stericsson.com>

This creates a DMAengine driver for the ARM PL080/PL081 PrimeCells
based on the implementation earlier submitted by Peter Pearse.
This is working like a charm for memcpy and slave DMA to the PL011
PrimeCell on the PB11MPCore.

This DMA controller is used in mostly unmodified form in the ARM
RealView and Versatile platforms, in the ST-Ericsson Nomadik, and
in the ST SPEAr platform.

It has been converted to use the header from the Samsung PL080
derivate instead of its own defintions. The Samsungs have a custom
driver in their mach-* folders though, atleast we can share the
register definitions.

Cc: Peter Pearse <peter.pearse at arm.com>
Cc: Ben Dooks <ben-linux at fluff.org>
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Alessandro Rubini <rubini at unipv.it>
Cc: Viresh Kumar <viresh.kumar at st.com>
Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
Changes since last revision: this has now been successfully tested
with PL011 UART on the PB11MPCore.

It now uses the generic runtime slave control and not the PrimeCell
extensions, and thus depends only on that patch set. With the previous
patch to the header file this is cleanly separated from the ARM tree
and any PrimeCell drivers and can go into the async_tx tree as it is
without further dependencies.
---
 drivers/dma/Kconfig        |    8 +
 drivers/dma/Makefile       |    1 +
 drivers/dma/amba-pl08x.c   | 2027 ++++++++++++++++++++++++++++++++++++++++++++
 include/linux/amba/pl08x.h |  183 ++++
 4 files changed, 2219 insertions(+), 0 deletions(-)
 create mode 100644 drivers/dma/amba-pl08x.c
 create mode 100644 include/linux/amba/pl08x.h

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 8344375..8acb284 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -36,6 +36,14 @@ comment "DMA Devices"
 config ASYNC_TX_DISABLE_CHANNEL_SWITCH
 	bool
 
+config AMBA_PL08X
+	bool "ARM PrimeCell PL080 or PL081 support"
+	depends on ARM_AMBA && EXPERIMENTAL
+	select DMA_ENGINE
+	help
+	  Platform has a PL08x DMAC device
+	  which can provide DMA engine support
+
 config INTEL_IOATDMA
 	tristate "Intel I/OAT DMA support"
 	depends on PCI && X86
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 0fe5ebb..c51dbc8 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_AMCC_PPC440SPE_ADMA) += ppc4xx/
 obj-$(CONFIG_TIMB_DMA) += timb_dma.o
 obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
 obj-$(CONFIG_PL330_DMA) += pl330.o
+obj-$(CONFIG_AMBA_PL08X) += amba-pl08x.o
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
new file mode 100644
index 0000000..69ef4f9
--- /dev/null
+++ b/drivers/dma/amba-pl08x.c
@@ -0,0 +1,2027 @@
+/*
+ * Copyright (c) 2006 ARM Ltd.
+ * Copyright (c) 2010 ST-Ericsson SA
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ * The full GNU General Public License is iin this distribution in the
+ * file called COPYING.
+ *
+ * Documentation: ARM DDI 0196G == PL080
+ * Documentation: ARM DDI 0218E	== PL081
+ *
+ * PL080 & PL081 both have 16 sets of DMA signals that can be routed to
+ * any channel.
+ *
+ * The PL080 has 8 channels available for simultaneous use, and the PL081
+ * has only two channels. So on these DMA controllers the number of channels
+ * and the number of incoming DMA signals are two totally different things.
+ * It is usually not possible to theoretically handle all physical signals,
+ * so a multiplexing scheme with possible denial of use is necessary.
+ *
+ * The PL080 has a dual bus master, PL081 has a single master.
+ *
+ * Memory to peripheral transfer may be visualized as
+ *	Get data from memory to DMAC
+ *	Until no data left
+ *		On burst request from peripheral
+ *			Destination burst from DMAC to peripheral
+ *			Clear burst request
+ *	Raise terminal count interrupt
+ *
+ * For peripherals with a FIFO:
+ * Source      burst size == half the depth of the peripheral FIFO
+ * Destination burst size == the depth of the peripheral FIFO
+ *
+ * (Bursts are irrelevant for mem to mem transfers - there are no burst
+ * signals, the DMA controller will simply facilitate its AHB master.)
+ *
+ * ASSUMES default (little) endianness for DMA transfers
+ *
+ * Only DMAC flow control is implemented
+ *
+ * Global TODO:
+ * - Break out common code from arch/arm/mach-s3c64xx and share
+ */
+#include <linux/device.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/dmapool.h>
+#include <linux/amba/bus.h>
+#include <linux/dmaengine.h>
+#include <linux/amba/pl08x.h>
+#include <linux/clk.h>
+
+#include <asm/hardware/pl080.h>
+#include <asm/dma.h>
+#include <asm/mach/dma.h>
+#include <asm/atomic.h>
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+
+#define DRIVER_NAME	"pl08xdmac"
+
+/**
+ * struct vendor_data - vendor-specific config parameters
+ * for PL08x derivates
+ * @name: the name of this specific variant
+ * @channels: the number of channels available in this variant
+ * @dualmaster: whether this version supports dual AHB masters
+ * or not.
+ */
+struct vendor_data {
+	char *name;
+	u8 channels;
+	bool dualmaster;
+};
+
+/*
+ * PL08X private data structures
+ * An LLI struct - see pl08x TRM
+ * Note that next uses bit[0] as a bus bit,
+ * start & end do not - their bus bit info
+ * is in cctl
+ */
+struct lli {
+	dma_addr_t src;
+	dma_addr_t dst;
+	dma_addr_t next;
+	u32 cctl;
+};
+
+/**
+ * struct pl08x_driver_data - the local state holder for the PL08x
+ * @base: virtual memory base (remapped) for the PL08x
+ * @adev: the corresponding AMBA (PrimeCell) bus entry
+ * @vd: vendor data for this PL08x variant
+ * @pd: platform data passed in from the platform/machine
+ * @clk: a clock to be enabled for this device to run
+ * @phy_chans: array of data for the physical channels
+ * @pool: a pool for the LLI descriptors
+ * @pool_ctr: counter of LLIs in the pool
+ * @lock: a spinlock for this struct
+ */
+struct pl08x_driver_data {
+	void __iomem *base;
+	struct amba_device *adev;
+	struct vendor_data *vd;
+	struct pl08x_platform_data *pd;
+	struct clk *clk;
+	struct pl08x_phy_chan *phy_chans;
+	struct dma_pool *pool;
+	int pool_ctr;
+	spinlock_t lock;
+};
+
+#ifdef MODULE
+
+# error "AMBA PL08X DMA CANNOT BE COMPILED AS A LOADABLE MODULE AT PRESENT"
+
+/*
+	a) Some devices might make use of DMA during boot
+	   (esp true for DMAENGINE implementation)
+	b) Memory allocation will need much more attention
+	   before load/unload can be supported
+ */
+#endif
+
+/*
+ * PL08X specific defines
+ */
+
+/*
+ * Memory boundaries: the manual for PL08x says that the controller
+ * cannot read past a 1KiB boundary, so these defines are used to
+ * create transfer LLIs that do not cross such boundaries.
+ */
+#define PL08X_BOUNDARY_SHIFT		(10)	/* 1KB 0x400 */
+#define PL08X_BOUNDARY_SIZE		(1 << PL08X_BOUNDARY_SHIFT)
+
+/* Minimum period between work queue runs */
+#define PL08X_WQ_PERIODMIN	20
+
+/* Size (bytes) of each LLI buffer allocated for one transfer */
+# define PL08X_LLI_TSFR_SIZE	0x2000
+
+/* Maximimum times we call dma_pool_alloc on this pool without freeing */
+#define PL08X_MAX_ALLOCS	0x40
+#define MAX_NUM_TSFR_LLIS	(PL08X_LLI_TSFR_SIZE/sizeof(struct lli))
+#define PL08X_ALIGN		8
+
+static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
+{
+	return container_of(chan, struct pl08x_dma_chan, chan);
+}
+
+/*
+ * Physical channel handling
+ */
+
+/* Whether a certain channel is busy or not */
+static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
+{
+	unsigned int val;
+
+	val = readl(ch->base + PL080_CH_CONFIG);
+	return val & PL080_CONFIG_ACTIVE;
+}
+
+/*
+ * Set the initial DMA register values i.e. those for the first LLI
+ * The next lli pointer and the configuration interrupt bit have
+ * been set when the LLIs were constructed
+ */
+static void pl08x_set_cregs(struct pl08x_driver_data *pl08x,
+			    struct pl08x_phy_chan *ch)
+{
+	/* Wait for channel inactive */
+	while (pl08x_phy_channel_busy(ch))
+		;
+
+	dev_vdbg(&pl08x->adev->dev,
+		"WRITE channel %d: csrc=%08x, cdst=%08x, "
+		 "cctl=%08x, clli=%08x, ccfg=%08x\n",
+		ch->id,
+		ch->csrc,
+		ch->cdst,
+		ch->cctl,
+		ch->clli,
+		ch->ccfg);
+
+	writel(ch->csrc, ch->base + PL080_CH_SRC_ADDR);
+	writel(ch->cdst, ch->base + PL080_CH_DST_ADDR);
+	writel(ch->clli, ch->base + PL080_CH_LLI);
+	writel(ch->cctl, ch->base + PL080_CH_CONTROL);
+	writel(ch->ccfg, ch->base + PL080_CH_CONFIG);
+	mb();
+}
+
+static inline void pl08x_config_phychan_for_txd(struct pl08x_dma_chan *plchan)
+{
+	struct pl08x_channel_data *cd = plchan->cd;
+	struct pl08x_phy_chan *phychan = plchan->phychan;
+	struct pl08x_txd *txd = plchan->at;
+
+	/* Copy the basic control register calculated at transfer config */
+	phychan->csrc = txd->csrc;
+	phychan->cdst = txd->cdst;
+	phychan->clli = txd->clli;
+	phychan->cctl = txd->cctl;
+
+	/* Assign the signal to the proper control registers */
+	phychan->ccfg = cd->ccfg;
+	phychan->ccfg &= ~PL080_CONFIG_SRC_SEL_MASK;
+	phychan->ccfg &= ~PL080_CONFIG_DST_SEL_MASK;
+	/* If it wasn't set from AMBA, ignore it */
+	if (txd->direction == DMA_TO_DEVICE)
+		/* Select signal as destination */
+		phychan->ccfg |=
+			(phychan->signal << PL080_CONFIG_DST_SEL_SHIFT);
+	else if (txd->direction == DMA_FROM_DEVICE)
+		/* Select signal as source */
+		phychan->ccfg |=
+			(phychan->signal << PL080_CONFIG_SRC_SEL_SHIFT);
+	/* Always enable error interrupts */
+	phychan->ccfg |= PL080_CONFIG_ERR_IRQ_MASK;
+	/* Always enable terminal interrupts */
+	phychan->ccfg |= PL080_CONFIG_TC_IRQ_MASK;
+}
+
+/*
+ * Enable the DMA channel
+ * Assumes all other configuration bits have been set
+ * as desired before this code is called
+ */
+static void pl08x_enable_phy_chan(struct pl08x_driver_data *pl08x,
+				  struct pl08x_phy_chan *ch)
+{
+	u32 val;
+
+	/*
+	 * Do not access config register until channel shows as disabled
+	 */
+	while (readl(pl08x->base + PL080_EN_CHAN) & (1 << ch->id))
+		;
+
+	/*
+	 * Do not access config register until channel shows as inactive
+	 */
+	val = readl(ch->base + PL080_CH_CONFIG);
+	while ((val & PL080_CONFIG_ACTIVE) || (val & PL080_CONFIG_ENABLE))
+		val = readl(ch->base + PL080_CH_CONFIG);
+
+	writel(val | PL080_CONFIG_ENABLE, ch->base + PL080_CH_CONFIG);
+	mb();
+}
+
+/*
+ * Overall DMAC remains enabled always.
+ *
+ * Disabling individual channels could lose data.
+ *
+ * Disable the peripheral DMA after disabling the DMAC
+ * in order to allow the DMAC FIFO to drain, and
+ * hence allow the channel to show inactive
+ *
+ */
+static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
+{
+	u32 val;
+
+	/* Set the HALT bit and wait for the FIFO to drain */
+	val = readl(ch->base + PL080_CH_CONFIG);
+	val |= PL080_CONFIG_HALT;
+	writel(val, ch->base + PL080_CH_CONFIG);
+
+	/* Wait for channel inactive */
+	while (pl08x_phy_channel_busy(ch))
+		;
+	mb();
+}
+
+static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
+{
+	u32 val;
+
+	/* Clear the HALT bit */
+	val = readl(ch->base + PL080_CH_CONFIG);
+	val &= ~PL080_CONFIG_HALT;
+	writel(val, ch->base + PL080_CH_CONFIG);
+	mb();
+}
+
+
+/* Stops the channel */
+static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
+{
+	u32 val;
+
+	pl08x_pause_phy_chan(ch);
+
+	/* Disable channel */
+	val = readl(ch->base + PL080_CH_CONFIG);
+	val &= ~PL080_CONFIG_ENABLE;
+	writel(val, ch->base + PL080_CH_CONFIG);
+	mb();
+}
+
+static inline u32 get_bytes_in_cctl(u32 cctl)
+{
+	/* The source width defines the number of bytes */
+	u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK;
+
+	switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) {
+	case PL080_WIDTH_8BIT:
+		break;
+	case PL080_WIDTH_16BIT:
+		bytes *= 2;
+		break;
+	case PL080_WIDTH_32BIT:
+		bytes *= 4;
+		break;
+	}
+	return bytes;
+}
+
+/* The channel should be paused when calling this */
+static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
+{
+	struct pl08x_phy_chan *ch;
+	struct pl08x_txd *txdi = NULL;
+	struct pl08x_txd *txd;
+	unsigned long flags;
+	u32 bytes = 0;
+
+	spin_lock_irqsave(&plchan->lock, flags);
+
+	ch = plchan->phychan;
+	txd = plchan->at;
+
+	/*
+	 * Next follow the LLIs to get the number of pending bytes in the
+	 * currently active transaction.
+	 */
+	if (ch && txd) {
+		struct lli *llis_va = txd->llis_va;
+		struct lli *llis_bus = (struct lli *) txd->llis_bus;
+		u32 clli = readl(ch->base + PL080_CH_LLI);
+
+		/* First get the bytes in the current active LLI */
+		bytes = get_bytes_in_cctl(readl(ch->base + PL080_CH_CONTROL));
+
+		if (clli) {
+			int i = 0;
+
+			/* Forward to the LLI pointed to by clli */
+			while ((clli != (u32) &(llis_bus[i])) &&
+			       (i < MAX_NUM_TSFR_LLIS))
+				i++;
+
+			while (clli) {
+				bytes += get_bytes_in_cctl(llis_va[i].cctl);
+				/*
+				 * A clli of 0x00000000 will terminate the
+				 * LLI list
+				 */
+				clli = llis_va[i].next;
+				i++;
+			}
+		}
+	}
+
+	/* Sum up all queued transactions */
+	if (!list_empty(&plchan->desc_list)) {
+		list_for_each_entry(txdi, &plchan->desc_list, node) {
+			bytes += txdi->len;
+		}
+
+	}
+
+	spin_unlock_irqrestore(&plchan->lock, flags);
+
+	return bytes;
+}
+
+/*
+ * Allocate a physical channel for a virtual channel
+ */
+static struct pl08x_phy_chan *
+pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
+		      struct pl08x_dma_chan *virt_chan)
+{
+	struct pl08x_phy_chan *ch = NULL;
+	unsigned long flags;
+	int i;
+
+	/*
+	 * Try to locate a physical channel to be used for
+	 * this transfer. If all are taken return NULL and
+	 * the requester will have to cope by using some fallback
+	 * PIO mode or retrying later.
+	 */
+	for (i = 0; i < pl08x->vd->channels; i++) {
+		ch = &pl08x->phy_chans[i];
+
+		spin_lock_irqsave(&ch->lock, flags);
+
+		if (!ch->serving) {
+			ch->serving = virt_chan;
+			ch->signal = -1;
+			spin_unlock_irqrestore(&ch->lock, flags);
+			break;
+		}
+
+		spin_unlock_irqrestore(&ch->lock, flags);
+	}
+
+	if (i == pl08x->vd->channels) {
+		/* No physical channel available, cope with it */
+		return NULL;
+	}
+
+	return ch;
+}
+
+static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
+					 struct pl08x_phy_chan *ch)
+{
+	unsigned long flags;
+
+	/* Stop the channel and clear its interrupts */
+	pl08x_stop_phy_chan(ch);
+	writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
+	writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
+
+	/* Mark it as free */
+	spin_lock_irqsave(&ch->lock, flags);
+	ch->serving = NULL;
+	ch->signal = -1;
+	spin_unlock_irqrestore(&ch->lock, flags);
+}
+
+/*
+ * LLI handling
+ */
+
+static inline unsigned int pl08x_get_bytes_for_cctl(unsigned int coded)
+{
+	switch (coded) {
+	case PL080_WIDTH_8BIT:
+		return 1;
+	case PL080_WIDTH_16BIT:
+		return 2;
+	case PL080_WIDTH_32BIT:
+		return 4;
+	default:
+		break;
+	}
+	BUG();
+	return 0;
+}
+
+static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth,
+				  u32 tsize)
+{
+	u32 retbits = cctl;
+
+	/* Remove all src, dst and transfersize bits */
+	retbits &= ~PL080_CONTROL_DWIDTH_MASK;
+	retbits &= ~PL080_CONTROL_SWIDTH_MASK;
+	retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
+
+	/* Then set the bits according to the parameters */
+	switch (srcwidth) {
+	case 1:
+		retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT;
+		break;
+	case 2:
+		retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT;
+		break;
+	case 4:
+		retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	switch (dstwidth) {
+	case 1:
+		retbits |= PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
+		break;
+	case 2:
+		retbits |= PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
+		break;
+	case 4:
+		retbits |= PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
+		break;
+	default:
+		BUG();
+		break;
+	}
+
+	retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
+	return retbits;
+}
+
+/*
+ * Autoselect a master bus to use for the transfer
+ * this prefers the destination bus if both available
+ * if fixed address on one bus the other will be chosen
+ */
+void pl08x_choose_master_bus(struct pl08x_bus_data *src_bus,
+	struct pl08x_bus_data *dst_bus, struct pl08x_bus_data **mbus,
+	struct pl08x_bus_data **sbus, u32 cctl)
+{
+	if (!(cctl & PL080_CONTROL_DST_INCR)) {
+		*mbus = src_bus;
+		*sbus = dst_bus;
+	} else if (!(cctl & PL080_CONTROL_SRC_INCR)) {
+		*mbus = dst_bus;
+		*sbus = src_bus;
+	} else {
+		if (dst_bus->buswidth == 4) {
+			*mbus = dst_bus;
+			*sbus = src_bus;
+		} else if (src_bus->buswidth == 4) {
+			*mbus = src_bus;
+			*sbus = dst_bus;
+		} else if (dst_bus->buswidth == 2) {
+			*mbus = dst_bus;
+			*sbus = src_bus;
+		} else if (src_bus->buswidth == 2) {
+			*mbus = src_bus;
+			*sbus = dst_bus;
+		} else {
+			/* src_bus->buswidth == 1 */
+			*mbus = dst_bus;
+			*sbus = src_bus;
+		}
+	}
+}
+
+/*
+ * Fills in one LLI for a certain transfer descriptor
+ * and advance the counter
+ */
+int pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
+			    struct pl08x_txd *txd, int num_llis, int len,
+			    u32 cctl, u32 *remainder)
+{
+	struct lli *llis_va = txd->llis_va;
+	struct lli *llis_bus = (struct lli *) txd->llis_bus;
+
+	BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
+
+	llis_va[num_llis].cctl		= cctl;
+	llis_va[num_llis].src		= txd->srcbus.addr;
+	llis_va[num_llis].dst		= txd->dstbus.addr;
+
+	/*
+	 * On versions with dual masters, you can optionally AND on
+	 * PL080_LLI_LM_AHB2 to the LLI to tell the hardware to read
+	 * in new LLIs with that controller, but we always try to
+	 * choose AHB1 to point into memory. The idea is to have AHB2
+	 * fixed on the peripheral and AHB1 messing around in the
+	 * memory. So we don't manipulate this bit currently.
+	 */
+
+	llis_va[num_llis].next =
+		(dma_addr_t)((u32) &(llis_bus[num_llis + 1]));
+
+	if (cctl & PL080_CONTROL_SRC_INCR)
+		txd->srcbus.addr += len;
+	if (cctl & PL080_CONTROL_DST_INCR)
+		txd->dstbus.addr += len;
+
+	*remainder -= len;
+
+	return num_llis + 1;
+}
+
+/*
+ * Return number of bytes to fill to boundary, or len
+ */
+static inline u32 pl08x_pre_boundary(u32 addr, u32 len)
+{
+	u32 boundary;
+
+	boundary = ((addr >> PL08X_BOUNDARY_SHIFT) + 1)
+		<< PL08X_BOUNDARY_SHIFT;
+
+	if (boundary < addr + len)
+		return boundary - addr;
+	else
+		return len;
+}
+
+/*
+ * This fills in the table of LLIs for the transfer descriptor
+ * Note that we assume we never have to change the burst sizes
+ * Return 0 for error
+ */
+static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
+			      struct pl08x_txd *txd)
+{
+	struct pl08x_channel_data *cd = txd->cd;
+	struct pl08x_bus_data *mbus, *sbus;
+	u32 remainder;
+	int num_llis = 0;
+	u32 cctl;
+	int max_bytes_per_lli;
+	int total_bytes = 0;
+	struct lli *llis_va;
+	struct lli *llis_bus;
+
+	if (!txd) {
+		dev_err(&pl08x->adev->dev, "%s no descriptor\n", __func__);
+		return 0;
+	}
+
+	txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_KERNEL,
+				      &txd->llis_bus);
+	if (!txd->llis_va) {
+		dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
+		return 0;
+	}
+
+	pl08x->pool_ctr++;
+
+	/*
+	 * Initialize bus values for this transfer
+	 * from the passed optimal values
+	 */
+	if (!cd) {
+		dev_err(&pl08x->adev->dev, "%s no channel data\n", __func__);
+		return 0;
+	}
+
+	/* Get the default CCTL from the platform data */
+	cctl = cd->cctl;
+
+	/*
+	 * On the PL080 we have two bus masters and we
+	 * should select one for source and one for
+	 * destination. We try to use AHB2 for the
+	 * bus which does not increment (typically the
+	 * peripheral) else we just choose something.
+	 */
+	cctl &= ~(PL080_CONTROL_DST_AHB2 | PL080_CONTROL_SRC_AHB2);
+	if (pl08x->vd->dualmaster) {
+		if (cctl & PL080_CONTROL_SRC_INCR)
+			/* Source increments, use AHB2 for destination */
+			cctl |= PL080_CONTROL_DST_AHB2;
+		else if (cctl & PL080_CONTROL_DST_INCR)
+			/* Destination increments, use AHB2 for source */
+			cctl |= PL080_CONTROL_SRC_AHB2;
+		else
+			/* Just pick something, source AHB1 dest AHB2 */
+			cctl |= PL080_CONTROL_DST_AHB2;
+	}
+
+	/* Find maximum width of the source bus */
+	txd->srcbus.maxwidth =
+		pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >>
+				       PL080_CONTROL_SWIDTH_SHIFT);
+
+	/* Find maximum width of the destination bus */
+	txd->dstbus.maxwidth =
+		pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >>
+				       PL080_CONTROL_DWIDTH_SHIFT);
+
+	/* Set up the bus widths to the maximum */
+	txd->srcbus.buswidth = txd->srcbus.maxwidth;
+	txd->dstbus.buswidth = txd->dstbus.maxwidth;
+	dev_vdbg(&pl08x->adev->dev,
+		 "%s source bus is %d bytes wide, dest bus is %d bytes wide\n",
+		 __func__, txd->srcbus.buswidth, txd->dstbus.buswidth);
+
+
+	/*
+	 * Bytes transferred == tsize * MIN(buswidths), not max(buswidths)
+	 */
+	max_bytes_per_lli = min(txd->srcbus.buswidth, txd->dstbus.buswidth) *
+		PL080_CONTROL_TRANSFER_SIZE_MASK;
+	dev_vdbg(&pl08x->adev->dev,
+		 "%s max bytes per lli = %d\n",
+		 __func__, max_bytes_per_lli);
+
+	/* We need to count this down to zero */
+	remainder = txd->len;
+	dev_vdbg(&pl08x->adev->dev,
+		 "%s remainder = %d\n",
+		 __func__, remainder);
+
+	/*
+	 * Choose bus to align to
+	 * - prefers destination bus if both available
+	 * - if fixed address on one bus chooses other
+	 * - modifies cctl to choose an apropriate master
+	 */
+	pl08x_choose_master_bus(&txd->srcbus, &txd->dstbus,
+				&mbus, &sbus, cctl);
+
+
+	/*
+	 * The lowest bit of the LLI register
+	 * is also used to indicate which master to
+	 * use for reading the LLIs.
+	 */
+
+	if (txd->len < mbus->buswidth) {
+		/*
+		 * Less than a bus width available
+		 * - send as single bytes
+		 */
+		while (remainder) {
+			dev_vdbg(&pl08x->adev->dev,
+				 "%s single byte LLIs for a transfer of "
+				 "less than a bus width (remain %08x)\n",
+				 __func__, remainder);
+			cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
+			num_llis =
+				pl08x_fill_lli_for_desc(pl08x, txd, num_llis, 1,
+					cctl, &remainder);
+			total_bytes++;
+		}
+	} else {
+		/*
+		 *  Make one byte LLIs until master bus is aligned
+		 *  - slave will then be aligned also
+		 */
+		while ((mbus->addr) % (mbus->buswidth)) {
+			dev_vdbg(&pl08x->adev->dev,
+				"%s adjustment lli for less than bus width "
+				 "(remain %08x)\n",
+				 __func__, remainder);
+			cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
+			num_llis = pl08x_fill_lli_for_desc
+				(pl08x, txd, num_llis, 1, cctl, &remainder);
+			total_bytes++;
+		}
+
+		/*
+		 *  Master now aligned
+		 * - if slave is not then we must set its width down
+		 */
+		if (sbus->addr % sbus->buswidth) {
+			dev_dbg(&pl08x->adev->dev,
+				"%s set down bus width to one byte\n",
+				 __func__);
+
+			sbus->buswidth = 1;
+		}
+
+		/*
+		 * Make largest possible LLIs until less than one bus
+		 * width left
+		 */
+		while (remainder > (mbus->buswidth - 1)) {
+			int lli_len, target_len;
+			int tsize;
+			int odd_bytes;
+
+			/*
+			 * If enough left try to send max possible,
+			 * otherwise try to send the remainder
+			 */
+			target_len = remainder;
+			if (remainder > max_bytes_per_lli)
+				target_len = max_bytes_per_lli;
+
+			/*
+			 * Set bus lengths for incrementing busses
+			 * to number of bytes which fill to next memory
+			 * boundary
+			 */
+			if (cctl & PL080_CONTROL_SRC_INCR)
+				txd->srcbus.fill_bytes =
+					pl08x_pre_boundary(
+						txd->srcbus.addr,
+						remainder);
+			else
+				txd->srcbus.fill_bytes =
+					max_bytes_per_lli;
+
+			if (cctl & PL080_CONTROL_DST_INCR)
+				txd->dstbus.fill_bytes =
+					pl08x_pre_boundary(
+						txd->dstbus.addr,
+						remainder);
+			else
+				txd->dstbus.fill_bytes =
+						max_bytes_per_lli;
+
+			/*
+			 *  Find the nearest
+			 */
+			lli_len	= min(txd->srcbus.fill_bytes,
+				txd->dstbus.fill_bytes);
+
+			BUG_ON(lli_len > remainder);
+
+			if (lli_len <= 0) {
+				dev_err(&pl08x->adev->dev,
+					"%s lli_len is %d, <= 0\n",
+						__func__, lli_len);
+				return 0;
+			}
+
+			if (lli_len == target_len) {
+				/*
+				 * Can send what we wanted
+				 */
+				/*
+				 *  Maintain alignment
+				 */
+				lli_len	= (lli_len/mbus->buswidth) *
+							mbus->buswidth;
+				odd_bytes = 0;
+			} else {
+				/*
+				 * So now we know how many bytes to transfer
+				 * to get to the nearest boundary
+				 * The next lli will past the boundary
+				 * - however we may be working to a boundary
+				 *   on the slave bus
+				 *   We need to ensure the master stays aligned
+				 */
+				odd_bytes = lli_len % mbus->buswidth;
+				/*
+				 * - and that we are working in multiples
+				 *   of the bus widths
+				 */
+				lli_len -= odd_bytes;
+
+			}
+
+			if (lli_len) {
+				/*
+				 * Check against minimum bus alignment:
+				 * Calculate actual transfer size in relation
+				 * to bus width an get a maximum remainder of
+				 * the smallest bus width - 1
+				 */
+				/* FIXME: use round_down()? */
+				tsize = lli_len / min(mbus->buswidth,
+						      sbus->buswidth);
+				lli_len	= tsize * min(mbus->buswidth,
+						      sbus->buswidth);
+
+				if (target_len != lli_len) {
+					dev_vdbg(&pl08x->adev->dev,
+					"%s can't send what we want. Desired %08x, lli of %08x bytes in txd of %08x\n",
+					__func__, target_len, lli_len, txd->len);
+				}
+
+				cctl = pl08x_cctl_bits(cctl,
+						       txd->srcbus.buswidth,
+						       txd->dstbus.buswidth,
+						       tsize);
+
+				dev_vdbg(&pl08x->adev->dev,
+					"%s fill lli with single lli chunk of size %08x (remainder %08x)\n",
+					__func__, lli_len, remainder);
+				num_llis = pl08x_fill_lli_for_desc(pl08x, txd,
+						num_llis, lli_len, cctl,
+						&remainder);
+				total_bytes += lli_len;
+			}
+
+
+			if (odd_bytes) {
+				/*
+				 * Creep past the boundary,
+				 * maintaining master alignment
+				 */
+				int j;
+				for (j = 0; (j < mbus->buswidth)
+						&& (remainder); j++) {
+					cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
+					dev_vdbg(&pl08x->adev->dev,
+						"%s align with boundardy, single byte (remain %08x)\n",
+						__func__, remainder);
+					num_llis =
+						pl08x_fill_lli_for_desc(pl08x,
+							txd, num_llis, 1,
+							cctl, &remainder);
+					total_bytes++;
+				}
+			}
+		}
+
+		/*
+		 * Send any odd bytes
+		 */
+		if (remainder < 0) {
+			dev_err(&pl08x->adev->dev, "%s remainder not fitted 0x%08x bytes\n",
+					__func__, remainder);
+			return 0;
+		}
+
+		while (remainder) {
+			cctl = pl08x_cctl_bits(cctl, 1, 1, 1);
+			dev_vdbg(&pl08x->adev->dev,
+				"%s align with boundardy, single odd byte (remain %d)\n",
+				__func__, remainder);
+			num_llis = pl08x_fill_lli_for_desc(pl08x, txd, num_llis,
+					1, cctl, &remainder);
+			total_bytes++;
+		}
+	}
+	if (total_bytes != txd->len) {
+		dev_err(&pl08x->adev->dev,
+			"%s size of encoded lli:s don't match total txd, transferred 0x%08x from size 0x%08x\n",
+			__func__, total_bytes, txd->len);
+		return 0;
+	}
+
+	if (num_llis >= MAX_NUM_TSFR_LLIS) {
+		dev_err(&pl08x->adev->dev,
+			"%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
+			__func__, (u32) MAX_NUM_TSFR_LLIS);
+		return 0;
+	}
+	/*
+	 * Decide whether this is a loop or a terminated transfer
+	 */
+	llis_va = txd->llis_va;
+	llis_bus = (struct lli *) txd->llis_bus;
+
+	if (cd->circular_buffer) {
+		/*
+		 * Loop the circular buffer so that the next element
+		 * points back to the beginning of the LLI.
+		 */
+		llis_va[num_llis - 1].next =
+			(dma_addr_t)((unsigned int)&(llis_bus[0]));
+	} else {
+		/*
+		 * On non-circular buffers, the final LLI terminates
+		 * the LLI.
+		 */
+		llis_va[num_llis - 1].next = 0;
+		/*
+		 * The final LLI element shall also fire an interrupt
+		 */
+		llis_va[num_llis - 1].cctl |= PL080_CONTROL_TC_IRQ_EN;
+	}
+
+	/* Now store the channel register values */
+	txd->csrc = llis_va[0].src;
+	txd->cdst = llis_va[0].dst;
+	if (num_llis > 1)
+		txd->clli = llis_va[0].next;
+	else
+		txd->clli = 0;
+
+	txd->cctl = llis_va[0].cctl;
+	/* ccfg will be set at physical channel allocation time */
+
+#ifdef VERBOSE_DEBUG
+	{
+		int i;
+
+		for (i = 0; i < num_llis; i++) {
+			dev_vdbg(&pl08x->adev->dev,
+				 "lli %d @%p: csrc=%08x, cdst=%08x, cctl=%08x, clli=%08x\n",
+				 i,
+				 &llis_va[i],
+				 llis_va[i].src,
+				 llis_va[i].dst,
+				 llis_va[i].cctl,
+				 llis_va[i].next
+				);
+		}
+	}
+#endif
+
+	return num_llis;
+}
+
+/* You should call this with the struct pl08x lock held */
+static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
+			   struct pl08x_txd *txd)
+{
+	if (!txd)
+		dev_err(&pl08x->adev->dev,
+			"%s no descriptor to free\n",
+			__func__);
+
+	/* Free the LLI */
+	dma_pool_free(pl08x->pool, txd->llis_va,
+		      txd->llis_bus);
+
+	pl08x->pool_ctr--;
+
+	kfree(txd);
+}
+
+static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
+				struct pl08x_dma_chan *plchan)
+{
+	struct pl08x_txd *txdi = NULL;
+	struct pl08x_txd *next;
+
+	if (!list_empty(&plchan->desc_list)) {
+		list_for_each_entry_safe(txdi,
+					 next, &plchan->desc_list, node) {
+			list_del(&txdi->node);
+			pl08x_free_txd(pl08x, txdi);
+		}
+
+	}
+}
+
+static void pl08x_tasklet(unsigned long data)
+{
+	struct pl08x_dma_chan *plchan = (struct pl08x_dma_chan *) data;
+	struct pl08x_phy_chan *phychan = plchan->phychan;
+	struct pl08x_driver_data *pl08x = plchan->host;
+	unsigned long flags;
+
+	if (!plchan)
+		BUG();
+
+	spin_lock_irqsave(&plchan->lock, flags);
+
+	if (plchan->at) {
+		dma_async_tx_callback callback =
+			plchan->at->tx.callback;
+		void *callback_param =
+			plchan->at->tx.callback_param;
+
+		/*
+		 * Update last completed
+		 */
+		plchan->lc =
+			(plchan->at->tx.cookie);
+
+		/*
+		 * Callback to signal completion
+		 */
+		if (callback)
+			callback(callback_param);
+
+		/*
+		 * Device callbacks should NOT clear
+		 * the current transaction on the channel
+		 * Linus: sometimes they should?
+		 */
+		if (!plchan->at)
+			BUG();
+
+		/*
+		 * Free the descriptor if it's not for a device
+		 * using a circular buffer
+		 */
+		if (!plchan->at->cd->circular_buffer) {
+			pl08x_free_txd(pl08x, plchan->at);
+			plchan->at = NULL;
+		}
+		/*
+		 * else descriptor for circular
+		 * buffers only freed when
+		 * client has disabled dma
+		 */
+	}
+	/*
+	 * If a new descriptor is queued, set it up
+	 * plchan->at is NULL here
+	 */
+	if (!list_empty(&plchan->desc_list)) {
+		struct pl08x_txd *next;
+
+		next = list_first_entry(&plchan->desc_list,
+					struct pl08x_txd,
+					node);
+		list_del(&next->node);
+		plchan->at = next;
+		/* Configure the physical channel for the next txd */
+		pl08x_config_phychan_for_txd(plchan);
+		pl08x_set_cregs(pl08x, plchan->phychan);
+		pl08x_enable_phy_chan(pl08x, plchan->phychan);
+	} else {
+		/*
+		 * No more jobs, so free up the physical channel
+		 * Free any allocated signal on slave transfers too
+		 */
+		if ((phychan->signal >= 0) && pl08x->pd->put_signal)
+			pl08x->pd->put_signal(plchan);
+		pl08x_put_phy_channel(pl08x, phychan);
+		plchan->phychan = NULL;
+	}
+
+	spin_unlock_irqrestore(&plchan->lock, flags);
+}
+
+static irqreturn_t pl08x_irq(int irq, void *dev)
+{
+	struct pl08x_driver_data *pl08x = dev;
+	u32 mask = 0;
+	u32 val;
+	int i;
+
+	val = readl(pl08x->base + PL080_ERR_STATUS);
+	mb();
+	if (val) {
+		/*
+		 * An error interrupt (on one or more channels)
+		 */
+		dev_err(&pl08x->adev->dev,
+			"%s error interrupt, register value 0x%08x\n",
+				__func__, val);
+		/*
+		 * Simply clear ALL PL08X error interrupts,
+		 * regardless of channel and cause
+		 * FIXME: should be 0x00000003 on PL081 really.
+		 */
+		writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
+	}
+	val = readl(pl08x->base + PL080_INT_STATUS);
+	mb();
+	for (i = 0; i < pl08x->vd->channels; i++) {
+		if ((1 << i) & val) {
+			/* Locate physical channel */
+			struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
+			struct pl08x_dma_chan *plchan = phychan->serving;
+
+			/* Schedule tasklet on this channel */
+			tasklet_schedule(&plchan->tasklet);
+
+			mask |= (1 << i);
+		}
+	}
+	/*
+	 * Clear only the terminal interrupts on channels we processed
+	 */
+	writel(mask, pl08x->base + PL080_TC_CLEAR);
+	mb();
+
+	return mask ? IRQ_HANDLED : IRQ_NONE;
+}
+
+
+/*
+ * The DMA ENGINE API
+ */
+static int pl08x_alloc_chan_resources(struct dma_chan *chan)
+{
+	return 0;
+}
+
+static void pl08x_free_chan_resources(struct dma_chan *chan)
+{
+}
+
+/*
+ * This should be called with the channel plchan->lock held
+ */
+static int prep_phy_channel(struct pl08x_dma_chan *plchan,
+			    struct pl08x_txd *txd)
+{
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_phy_chan *ch;
+	int ret;
+
+	/* Check if we already have a channel */
+	if (plchan->phychan)
+		return 0;
+
+	ch = pl08x_get_phy_channel(pl08x, plchan);
+	if (!ch) {
+		/* No physical channel available, cope with it */
+		dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
+		return -EBUSY;
+	}
+
+	/*
+	 * OK we have a physical channel: for memcpy() this is all we
+	 * need, but for slaves the physical siglals may be muxed!
+	 * Can the platform allow us to use this channel?
+	 */
+	if ((txd->direction == DMA_FROM_DEVICE ||
+	     txd->direction == DMA_TO_DEVICE) &&
+	    pl08x->pd->get_signal) {
+		ret = pl08x->pd->get_signal(plchan);
+		if (ret < 0) {
+			dev_dbg(&pl08x->adev->dev,
+				"unable to use physical channel %d for transfer on %s due to platform restrictions\n",
+				ch->id, plchan->name);
+			/* Release physical channel & return */
+			pl08x_put_phy_channel(pl08x, ch);
+			return -EBUSY;
+		}
+		ch->signal = ret;
+	}
+
+	dev_dbg(&pl08x->adev->dev, "allocated physical channel %d and signal %d for xfer on %s\n",
+		 ch->id,
+		 ch->signal,
+		 plchan->name);
+
+	plchan->phychan = ch;
+
+	return 0;
+}
+
+/*
+ * First make the LLIs (could/should we do this earlier??)
+ * slave (m/p) - no queued transactions allowed at present
+ *	TODO allow queued transactions for non circular buffers
+ * Set up the channel active txd as inactive
+ * m2m	- transactions may be queued
+ * If no active txd on channel
+ *	set it up as inactive
+ *	- issue_pending() will set active & start
+ * else
+ *	queue it
+ * Lock channel since there may be (at least for m2m) multiple calls
+ *
+ * Return < 0 for error
+ */
+
+static dma_cookie_t pl08x_tx_submit(struct dma_async_tx_descriptor *tx)
+{
+	int num_llis;
+	unsigned long flags;
+	struct pl08x_txd *txd = container_of(tx, struct pl08x_txd, tx);
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(tx->chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	int ret;
+
+	num_llis = pl08x_fill_llis_for_desc(pl08x, txd);
+
+	if (!num_llis)
+		return -EINVAL;
+
+	spin_lock_irqsave(&plchan->lock, flags);
+
+	atomic_inc(&plchan->last_issued);
+	tx->cookie = atomic_read(&plchan->last_issued);
+
+	/*
+	 * If this device is not using a circular buffer then
+	 * queue this new descriptor for transfer.
+	 * The descriptor for a circular buffer continues
+	 * to be used until the channel is freed.
+	 */
+	if (txd->cd->circular_buffer)
+		dev_err(&pl08x->adev->dev,
+			"%s attempting to queue a circular buffer\n",
+			__func__);
+	else
+		list_add_tail(&txd->node,
+			      &plchan->desc_list);
+
+	/*
+	 * See if we already have a physical channel allocated,
+	 * else this is the time to try to get one.
+	 */
+	ret = prep_phy_channel(plchan, txd);
+	if (ret) {
+		/* No physical channel available, cope with it */
+		spin_unlock_irqrestore(&plchan->lock, flags);
+		return -EBUSY;
+	}
+
+	spin_unlock_irqrestore(&plchan->lock, flags);
+
+	return tx->cookie;
+}
+
+static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
+		struct dma_chan *chan, unsigned long flags)
+{
+	struct dma_async_tx_descriptor *retval = NULL;
+
+	return retval;
+}
+
+/*
+ * Code accessing dma_async_is_complete() in a tight loop
+ * may give problems - could schedule where indicated.
+ * If slaves are relying on interrupts to signal completion this
+ * function must not be called with interrupts disabled
+ */
+static enum dma_status
+pl08x_dma_tx_status(struct dma_chan *chan,
+		    dma_cookie_t cookie,
+		    struct dma_tx_state *txstate)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	dma_cookie_t last_used;
+	dma_cookie_t last_complete;
+	enum dma_status ret;
+	u32 bytesleft = 0;
+
+	last_used = atomic_read(&plchan->last_issued);
+	last_complete = plchan->lc;
+
+	ret = dma_async_is_complete(cookie, last_complete, last_used);
+	if (ret == DMA_SUCCESS) {
+		dma_set_tx_state(txstate, last_complete, last_used, 0);
+		return ret;
+	}
+
+	/*
+	 * schedule(); could be inserted here
+	 */
+
+	/*
+	 * This cookie not complete yet
+	 */
+	last_used = atomic_read(&plchan->last_issued);
+	last_complete = plchan->lc;
+
+	/* Get number of bytes left in the active transactions and queue */
+	bytesleft = pl08x_getbytes_chan(plchan);
+
+	dma_set_tx_state(txstate, last_complete, last_used,
+			 bytesleft);
+
+	if (plchan->paused)
+		return DMA_PAUSED;
+
+	return DMA_IN_PROGRESS;
+}
+
+/* PrimeCell DMA extension */
+struct burst_table {
+	int burstwords;
+	u32 reg;
+};
+
+static const struct burst_table burst_sizes[] = {
+	{
+		.burstwords = 256,
+		.reg = (PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 128,
+		.reg = (PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 64,
+		.reg = (PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 32,
+		.reg = (PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 16,
+		.reg = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 8,
+		.reg = (PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 4,
+		.reg = (PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+	{
+		.burstwords = 1,
+		.reg = (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT),
+	},
+};
+
+static void dma_set_runtime_config(struct dma_chan *chan,
+			       struct dma_slave_config *config)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_channel_data *cd = plchan->cd;
+	int maxburst = config->maxburst;
+	u32 cctl = 0;
+	/* Mask out all except src and dst channel */
+	u32 ccfg = cd->ccfg & 0x000003DEU;
+	int i = 0;
+
+	plchan->runtime_addr = config->addr;
+	plchan->runtime_direction = config->direction;
+
+	switch (config->addr_width) {
+	case 1:
+		cctl |= (PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT) |
+			(PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT);
+		break;
+	case 2:
+		cctl |= (PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT) |
+			(PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT);
+		break;
+	case 4:
+		cctl |= (PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT) |
+			(PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT);
+		break;
+	default:
+		dev_err(&pl08x->adev->dev,
+			"bad runtime_config: alien address width\n");
+		return;
+	}
+
+	/*
+	 * Now decide on a maxburst:
+	 * If this channel will only request single transfers, set
+	 * this down to ONE element.
+	 */
+	if (plchan->cd->single) {
+		cctl |= (PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT) |
+			(PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT);
+	} else {
+		while (i < ARRAY_SIZE(burst_sizes)) {
+			if (burst_sizes[i].burstwords <= maxburst)
+				break;
+			i++;
+		}
+		cctl |= burst_sizes[i].reg;
+	}
+
+	/* Transfer direction */
+	if (config->direction == DMA_TO_DEVICE) {
+		cctl |= PL080_CONTROL_SRC_INCR;
+		ccfg |= PL080_FLOW_MEM2PER << PL080_CONFIG_FLOW_CONTROL_SHIFT;
+	} else if (config->direction == DMA_FROM_DEVICE) {
+		cctl |= PL080_CONTROL_DST_INCR;
+		ccfg |= PL080_FLOW_PER2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
+	} else {
+		dev_err(&pl08x->adev->dev,
+			"bad runtime_config: alien transfer direction\n");
+	}
+
+	/* Access the cell in privileged mode, non-bufferable, non-cacheable */
+	cctl &= ~PL080_CONTROL_PROT_MASK;
+	cctl |= PL080_CONTROL_PROT_SYS;
+
+	/* Modify the default channel data to fit PrimeCell request */
+	cd->cctl = cctl;
+	cd->ccfg = ccfg;
+
+	dev_dbg(&pl08x->adev->dev,
+		"configured channel %s (%s) for %s, data width %d, "
+		"maxburst %d words, LE, CCTL=%08x, CCFG=%08x\n",
+		dma_chan_name(chan), plchan->name,
+		(config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
+		config->addr_width,
+		config->maxburst,
+		cctl, ccfg);
+}
+
+/*
+ * Slave transactions callback to the slave device to allow
+ * synchronization of slave DMA signals with the DMAC enable
+ */
+static void pl08x_issue_pending(struct dma_chan *chan)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	unsigned long flags;
+
+
+	spin_lock_irqsave(&plchan->lock, flags);
+	/* Something is already active */
+	if (plchan->at) {
+			spin_unlock_irqrestore(&plchan->lock, flags);
+			return;
+	}
+
+	/* Take the first element in the queue and execute it */
+	if (!list_empty(&plchan->desc_list)) {
+		struct pl08x_txd *next;
+
+		next = list_first_entry(&plchan->desc_list,
+					struct pl08x_txd,
+					node);
+		list_del(&next->node);
+		plchan->at = next;
+
+		/* Configure the physical channel for the active txd */
+		pl08x_config_phychan_for_txd(plchan);
+		pl08x_set_cregs(pl08x, plchan->phychan);
+		pl08x_enable_phy_chan(pl08x, plchan->phychan);
+	}
+
+	spin_unlock_irqrestore(&plchan->lock, flags);
+}
+
+/*
+ * Initialize a descriptor to be used by memcpy submit
+ */
+static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
+		struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
+		size_t len, unsigned long flags)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_txd *txd;
+
+	txd = kzalloc(sizeof(struct pl08x_txd), GFP_KERNEL);
+	if (!txd) {
+		dev_err(&pl08x->adev->dev,
+			"%s no memory for descriptor\n", __func__);
+		return NULL;
+	}
+
+	dma_async_tx_descriptor_init(&txd->tx, chan);
+	txd->direction = DMA_NONE;
+	txd->srcbus.addr = src;
+	txd->dstbus.addr = dest;
+
+	/* Set platform data for m2m */
+	txd->cd = &pl08x->pd->memcpy_channel;
+	/* Both to be incremented or the code will break */
+	txd->cd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
+	txd->tx.tx_submit = pl08x_tx_submit;
+	txd->tx.callback = NULL;
+	txd->tx.callback_param = NULL;
+	txd->len = len;
+
+	INIT_LIST_HEAD(&txd->node);
+
+	return &txd->tx;
+}
+
+struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
+		struct dma_chan *chan, struct scatterlist *sgl,
+		unsigned int sg_len, enum dma_data_direction direction,
+		unsigned long flags)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	struct pl08x_txd *txd;
+
+	/*
+	 * Current implementation ASSUMES only one sg
+	 */
+	if (sg_len != 1) {
+		dev_err(&pl08x->adev->dev, "%s prepared too long sglist\n",
+			__func__);
+		BUG();
+	}
+
+	dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
+		__func__, sgl->length, plchan->name);
+
+	txd = kzalloc(sizeof(struct pl08x_txd), GFP_KERNEL);
+	if (!txd) {
+		dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
+		return NULL;
+	}
+
+	dma_async_tx_descriptor_init(&txd->tx, chan);
+
+	if (direction != plchan->runtime_direction)
+		dev_err(&pl08x->adev->dev, "%s DMA setup does not match "
+			"the direction configured for the PrimeCell\n",
+			__func__);
+
+	/*
+	 * Set up addresses, the PrimeCell configured address
+	 * will take precedence since this may configure the
+	 * channel target address dynamically at runtime.
+	 */
+	txd->direction = direction;
+	if (direction == DMA_TO_DEVICE) {
+		txd->srcbus.addr = sgl->dma_address;
+		if (plchan->runtime_addr)
+			txd->dstbus.addr = plchan->runtime_addr;
+		else
+			txd->dstbus.addr = plchan->cd->addr;
+	} else if (direction == DMA_FROM_DEVICE) {
+		if (plchan->runtime_addr)
+			txd->srcbus.addr = plchan->runtime_addr;
+		else
+			txd->srcbus.addr = plchan->cd->addr;
+		txd->dstbus.addr = sgl->dma_address;
+	} else {
+		dev_err(&pl08x->adev->dev,
+			"%s direction unsupported\n", __func__);
+		return NULL;
+	}
+	txd->cd = plchan->cd;
+	txd->tx.tx_submit = pl08x_tx_submit;
+	txd->tx.callback = NULL;
+	txd->tx.callback_param = NULL;
+	txd->len = sgl->length;
+	INIT_LIST_HEAD(&txd->node);
+
+	return &txd->tx;
+}
+
+static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+			 unsigned long arg)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	struct pl08x_driver_data *pl08x = plchan->host;
+	unsigned long flags;
+	int ret = 0;
+
+	/* Controls applicable to inactive channels */
+	if (cmd == DMA_SLAVE_CONFIG) {
+		dma_set_runtime_config(chan,
+				       (struct dma_slave_config *)
+				       arg);
+		return 0;
+	}
+
+	/*
+	 * Anything succeeds on channels with no physical allocation and
+	 * no queued transfers.
+	 */
+	spin_lock_irqsave(&plchan->lock, flags);
+	if (!plchan->phychan && !plchan->at) {
+		spin_unlock_irqrestore(&plchan->lock, flags);
+		return 0;
+	}
+
+	switch (cmd) {
+	case DMA_TERMINATE_ALL:
+		plchan->paused = false;
+
+		if (plchan->phychan) {
+			pl08x_stop_phy_chan(plchan->phychan);
+
+			/*
+			 * Mark physical channel as free and free any slave
+			 * signal
+			 */
+			if ((plchan->phychan->signal >= 0) &&
+			    pl08x->pd->put_signal)
+				pl08x->pd->put_signal(plchan);
+			pl08x_put_phy_channel(pl08x, plchan->phychan);
+			plchan->phychan = NULL;
+		}
+
+		/* Dequeue jobs and free LLIs */
+		if (plchan->at) {
+			pl08x_free_txd(pl08x, plchan->at);
+			pl08x_free_txd_list(pl08x, plchan);
+			plchan->at = NULL;
+		}
+		break;
+	case DMA_PAUSE:
+		pl08x_pause_phy_chan(plchan->phychan);
+		plchan->paused = true;
+		break;
+	case DMA_RESUME:
+		pl08x_resume_phy_chan(plchan->phychan);
+		plchan->paused = false;
+		break;
+	default:
+		/* Unknown command */
+		ret = -ENXIO;
+		break;
+	}
+
+	spin_unlock_irqrestore(&plchan->lock, flags);
+
+	return ret;
+}
+
+bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
+{
+	struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
+	char *name = chan_id;
+
+	/* Check that the channel is not taken! */
+	if (!strcmp(plchan->name, name))
+		return true;
+
+	return false;
+}
+
+static struct dma_device dmac_memcpy = {
+	.device_alloc_chan_resources	= pl08x_alloc_chan_resources,
+	.device_free_chan_resources	= pl08x_free_chan_resources,
+	.device_prep_dma_memcpy		= pl08x_prep_dma_memcpy,
+	.device_prep_dma_xor		= NULL,
+	.device_prep_dma_memset		= NULL,
+	.device_prep_dma_interrupt	= pl08x_prep_dma_interrupt,
+	.device_tx_status		= pl08x_dma_tx_status,
+	.device_issue_pending		= pl08x_issue_pending,
+	.device_control			= pl08x_control,
+	/*
+	 * Align to 4-byte boundary
+	 * This makes the DMAtests fail with grace on PB1176
+	 * broken DMA hardware instead of locking everything
+	 * up.
+	 */
+	/* .copy_align			= 2, */
+};
+
+static struct dma_device dmac_slave = {
+	.device_alloc_chan_resources	= pl08x_alloc_chan_resources,
+	.device_free_chan_resources	= pl08x_free_chan_resources,
+	.device_prep_dma_xor		= NULL,
+	.device_prep_dma_memset		= NULL,
+	.device_prep_dma_interrupt	= pl08x_prep_dma_interrupt,
+	.device_tx_status		= pl08x_dma_tx_status,
+	.device_issue_pending		= pl08x_issue_pending,
+	.device_prep_slave_sg		= pl08x_prep_slave_sg,
+	.device_control			= pl08x_control,
+};
+
+
+/*
+ * Just check that the device is there and active
+ * TODO: turn this bit on/off depending on the number of
+ * physical channels actually used, if it is zero... well
+ * shut it off. That will save some power. Cut the clock
+ * at the same time.
+ */
+static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
+{
+	u32 val;
+
+	val = readl(pl08x->base + PL080_CONFIG);
+	val &= ~(PL080_CONFIG_M2_BE | PL080_CONFIG_M1_BE | PL080_CONFIG_ENABLE);
+	/* We implictly clear bit 1 and that means little-endian mode */
+	val |= PL080_CONFIG_ENABLE;
+	mb();
+	writel(val, pl08x->base + PL080_CONFIG);
+	mb();
+}
+
+/*
+ * Initialise the DMAC memcpy/slave channels.
+ * Make a local wrapper to hold required data
+ */
+static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
+					   struct dma_device *dmadev,
+					   unsigned int channels,
+					   bool slave)
+{
+	struct pl08x_dma_chan *chan;
+	int i;
+
+	INIT_LIST_HEAD(&dmadev->channels);
+	/*
+	 * Register as many many memcpy as we have physical channels,
+	 * we won't always be able to use all but the code will have
+	 * to cope with that situation.
+	 */
+	for (i = 0; i < channels; i++) {
+		chan = kzalloc(sizeof(struct pl08x_dma_chan), GFP_KERNEL);
+		if (!chan) {
+			dev_err(&pl08x->adev->dev,
+				"%s no memory for channel\n", __func__);
+			return -ENOMEM;
+		}
+
+		chan->host = pl08x;
+
+		if (slave) {
+			chan->name = pl08x->pd->slave_channels[i].bus_id;
+			chan->cd = &pl08x->pd->slave_channels[i];
+		} else {
+			chan->cd = &pl08x->pd->memcpy_channel;
+			chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
+			if (!chan->name) {
+				kfree(chan);
+				return -ENOMEM;
+			}
+		}
+		dev_info(&pl08x->adev->dev,
+			 "initialize virtual channel \"%s\"\n",
+			 chan->name);
+
+		chan->chan.device = dmadev;
+		atomic_set(&chan->last_issued, 0);
+		chan->lc = atomic_read(&chan->last_issued);
+
+		spin_lock_init(&chan->lock);
+		INIT_LIST_HEAD(&chan->desc_list);
+		tasklet_init(&chan->tasklet, pl08x_tasklet,
+			     (unsigned long) chan);
+
+		list_add_tail(&chan->chan.device_node, &dmadev->channels);
+	}
+	dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
+		 i, slave ? "slave" : "memcpy");
+	return i;
+}
+
+static int pl08x_probe(struct amba_device *adev, struct amba_id *id)
+{
+	struct pl08x_driver_data *pl08x;
+	struct vendor_data *vd = id->data;
+	int ret = 0;
+	int i;
+
+	ret = amba_request_regions(adev, NULL);
+	if (ret)
+		return ret;
+
+	/* Create the driver state holder */
+	pl08x = kzalloc(sizeof(struct pl08x_driver_data), GFP_KERNEL);
+	if (!pl08x) {
+		ret = -ENOMEM;
+		goto out_no_pl08x;
+	}
+
+	/* Assign useful pointers to the driver state */
+	pl08x->adev = adev;
+	pl08x->vd = vd;
+
+	pl08x->clk = clk_get(&adev->dev, NULL);
+	if (IS_ERR(pl08x->clk)) {
+		ret = PTR_ERR(pl08x->clk);
+		if (ret == -ENOENT) {
+			dev_info(&adev->dev, "no clock supplied, assume always on\n");
+			pl08x->clk = NULL;
+		} else
+			goto out_no_clk;
+	}
+	/* Constantly enabled for now, we can control this dynamically */
+	if (pl08x->clk)
+		clk_enable(pl08x->clk);
+
+	/* A DMA memory pool for LLIs, align on 1-byte boundary */
+	pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
+			PL08X_LLI_TSFR_SIZE, PL08X_ALIGN, 0);
+	if (!pl08x->pool) {
+		ret = -ENOMEM;
+		goto out_no_lli_pool;
+	}
+
+	spin_lock_init(&pl08x->lock);
+
+	pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
+	if (!pl08x->base) {
+		ret = -ENOMEM;
+		goto out_no_ioremap;
+	}
+
+	/* Turn on the PL08x */
+	pl08x_ensure_on(pl08x);
+
+	/*
+	 * Attach the interrupt handler
+	 */
+	writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
+	writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
+	mb();
+
+	ret = request_irq(adev->irq[0], pl08x_irq, IRQF_DISABLED,
+			  vd->name, pl08x);
+	if (ret) {
+		dev_err(&adev->dev, "%s failed to request interrupt %d\n",
+			__func__, adev->irq[0]);
+		goto out_no_irq;
+	}
+
+	/* Initialize physical channels */
+	pl08x->phy_chans = kmalloc((vd->channels * sizeof(struct pl08x_phy_chan)),
+			GFP_KERNEL);
+	if (!pl08x->phy_chans) {
+		dev_err(&adev->dev, "%s failed to allocate "
+			"physical channel holders\n",
+			__func__);
+		goto out_no_phychans;
+	}
+
+	for (i = 0; i < vd->channels; i++) {
+		struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
+
+		ch->id = i;
+		ch->base = pl08x->base + PL080_Cx_BASE(i);
+		spin_lock_init(&ch->lock);
+		ch->serving = NULL;
+		ch->signal = -1;
+		dev_info(&adev->dev,
+			 "physical channel %d is %s\n", i,
+			 pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
+	}
+
+	/* Get the platform data */
+	pl08x->pd = dev_get_platdata(&adev->dev);
+
+	/* Set caps */
+	dma_cap_set(DMA_MEMCPY, dmac_memcpy.cap_mask);
+	dma_cap_set(DMA_SLAVE, dmac_slave.cap_mask);
+	dmac_memcpy.dev = &adev->dev;
+	dmac_slave.dev = &adev->dev;
+
+	/* Register as many memcpy channels as there are physical channels */
+	ret = pl08x_dma_init_virtual_channels(pl08x, &dmac_memcpy,
+					      pl08x->vd->channels, false);
+	if (ret <= 0) {
+		dev_warn(&pl08x->adev->dev,
+			 "%s failed to enumerate memcpy channels - %d\n",
+			 __func__, ret);
+		goto out_no_memcpy;
+	}
+	dmac_memcpy.chancnt = ret;
+
+	/* Register slave channels */
+	ret = pl08x_dma_init_virtual_channels(pl08x, &dmac_slave,
+					      pl08x->pd->num_slave_channels,
+					      true);
+	if (ret <= 0) {
+		dev_warn(&pl08x->adev->dev,
+			"%s failed to enumerate slave channels - %d\n",
+				__func__, ret);
+		goto out_no_slave;
+	}
+	dmac_slave.chancnt = ret;
+
+	ret = dma_async_device_register(&dmac_memcpy);
+	if (ret) {
+		dev_warn(&pl08x->adev->dev,
+			"%s failed to register memcpy as an async device - %d\n",
+			__func__, ret);
+		goto out_no_memcpy_reg;
+	}
+
+	ret = dma_async_device_register(&dmac_slave);
+	if (ret) {
+		dev_warn(&pl08x->adev->dev,
+			"%s failed to register slave as an async device - %d\n",
+			__func__, ret);
+		goto out_no_slave_reg;
+	}
+
+	amba_set_drvdata(adev, pl08x);
+	dev_info(&pl08x->adev->dev, "ARM(R) %s DMA block initialized @%08x\n",
+		vd->name, adev->res.start);
+	return 0;
+
+out_no_slave_reg:
+	dma_async_device_unregister(&dmac_memcpy);
+out_no_memcpy_reg:
+	/* FIXME: free slave channels */
+out_no_slave:
+	/* FIXME: free memcpy channels */
+out_no_memcpy:
+	kfree(pl08x->phy_chans);
+out_no_phychans:
+	free_irq(adev->irq[0], pl08x);
+out_no_irq:
+	iounmap(pl08x->base);
+out_no_ioremap:
+	dma_pool_destroy(pl08x->pool);
+out_no_lli_pool:
+	clk_put(pl08x->clk);
+out_no_clk:
+	kfree(pl08x);
+out_no_pl08x:
+	amba_release_regions(adev);
+	return ret;
+}
+
+/* PL080 has 8 channels and the PL080 have just 2 */
+static struct vendor_data vendor_pl080 = {
+	.name = "PL080",
+	.channels = 8,
+	.dualmaster = true,
+};
+
+static struct vendor_data vendor_pl081 = {
+	.name = "PL081",
+	.channels = 2,
+	.dualmaster = false,
+};
+
+static struct amba_id pl08x_ids[] = {
+	/* PL080 */
+	{
+		.id	= 0x00041080,
+		.mask	= 0x000fffff,
+		.data	= &vendor_pl080,
+	},
+	/* PL081 */
+	{
+		.id	= 0x00041081,
+		.mask	= 0x000fffff,
+		.data	= &vendor_pl081,
+	},
+	/* Nomadik 8815 PL080 variant */
+	{
+		.id	= 0x00280880,
+		.mask	= 0x00ffffff,
+		.data	= &vendor_pl080,
+	},
+	{ 0, 0 },
+};
+
+static struct amba_driver pl08x_amba_driver = {
+	.drv.name	= DRIVER_NAME,
+	.id_table	= pl08x_ids,
+	.probe		= pl08x_probe,
+};
+
+static int __init pl08x_init(void)
+{
+	int retval;
+	retval = amba_driver_register(&pl08x_amba_driver);
+	if (retval)
+		printk(KERN_WARNING DRIVER_NAME
+		       "failed to register as an amba device (%d)\n",
+		       retval);
+	return retval;
+}
+subsys_initcall(pl08x_init);
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h
new file mode 100644
index 0000000..809839c
--- /dev/null
+++ b/include/linux/amba/pl08x.h
@@ -0,0 +1,183 @@
+/*
+ *	linux/amba/pl08x.h - ARM PrimeCell DMA Controller driver
+ *
+ *	Copyright (C) 2005 ARM Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * pl08x information required by platform code
+ *
+ * Please credit ARM.com
+ * Documentation: ARM DDI 0196D
+ *
+ */
+
+#ifndef AMBA_PL08X_H
+#define AMBA_PL08X_H
+
+/* We need sizes of structs from this header */
+#include <linux/dmaengine.h>
+
+/**
+ * struct pl08x_channel_data - data structure to pass info between
+ * platform and PL08x driver regarding channel configuration
+ * @bus_id: name of this device channel, not just a device name since
+ * devices may have more than one channel e.g. "foo_tx"
+ * @min_signal: the minimum DMA signal number to be muxed in for this
+ * channel (for platforms supporting muxed signals). If you have
+ * static assignments, make sure this is set to the assigned signal
+ * number, PL08x have 16 possible signals in number 0 thru 15 so
+ * when these are not enough they often get muxed (in hardware)
+ * disabling simultaneous use of the same channel for two devices.
+ * @max_signal: the maximum DMA signal number to be muxed in for
+ * the channel. Set to the same as min_signal for
+ * devices with static assignments
+ * @muxval: a number usually used to poke into some mux regiser to
+ * mux in the signal to this channel
+ * @cctl_opt: default options for the channel control register
+ * @addr: source/target address in physical memory for this DMA channel,
+ * can be the address of a FIFO register for burst requests for example.
+ * This can be left undefined if the PrimeCell API is used for configuring
+ * this.
+ * @circular_buffer: whether the buffer passed in is circular and
+ * shall simply be looped round round (like a record baby round
+ * round round round)
+ * @single: the device connected to this channel will request single
+ * DMA transfers, not bursts. (Bursts are default.)
+ */
+struct pl08x_channel_data {
+	char *bus_id;
+	int min_signal;
+	int max_signal;
+	u32 muxval;
+	u32 cctl;
+	u32 ccfg;
+	dma_addr_t addr;
+	bool circular_buffer;
+	bool single;
+};
+
+/**
+ * Struct pl08x_bus_data - information of source or destination
+ * busses for a transfer
+ * @addr: current address
+ * @maxwidth: the maximum width of a transfer on this bus
+ * @buswidth: the width of this bus in bytes: 1, 2 or 4
+ * @fill_bytes: bytes required to fill to the next bus memory
+ * boundary
+ */
+struct pl08x_bus_data {
+	dma_addr_t addr;
+	u8 maxwidth;
+	u8 buswidth;
+	u32 fill_bytes;
+};
+
+/**
+ * struct pl08x_phy_chan - holder for the physical channels
+ * @id: physical index to this channel
+ * @lock: a lock to use when altering an instance of this struct
+ * @signal: the physical signal (aka channel) serving this
+ * physical channel right now
+ * @serving: the virtual channel currently being served by this
+ * physical channel
+ */
+struct pl08x_phy_chan {
+	unsigned int id;
+	void __iomem *base;
+	spinlock_t lock;
+	int signal;
+	struct pl08x_dma_chan *serving;
+	u32 csrc;
+	u32 cdst;
+	u32 clli;
+	u32 cctl;
+	u32 ccfg;
+};
+
+/**
+ * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
+ * @llis_bus: DMA memory address (physical) start for the LLIs
+ * @llis_va: virtual memory address start for the LLIs
+ */
+struct pl08x_txd {
+	struct dma_async_tx_descriptor tx;
+	struct list_head node;
+	enum dma_data_direction	direction;
+	struct pl08x_bus_data srcbus;
+	struct pl08x_bus_data dstbus;
+	int len;
+	dma_addr_t llis_bus;
+	void *llis_va;
+	struct pl08x_channel_data *cd;
+	bool active;
+	/* Settings to be put into the physical channel when we submit this txd */
+	u32 csrc;
+	u32 cdst;
+	u32 clli;
+	u32 cctl;
+};
+
+/**
+ * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
+ * @chan: wrappped abstract channel
+ * @phychan: the physical channel utilized by this channel, if there is one
+ * @tasklet: tasklet scheduled by the IRQ to handle actual work etc
+ * @name: name of channel
+ * @cd: channel platform data
+ * @runtime_addr: address for RX/TX according to the runtime config
+ * @runtime_direction: current direction of this channel according to
+ * runtime config
+ * @lc: last completed transaction on this channel
+ * @desc_list: queued transactions pending on this channel
+ * @at: active transaction on this channel
+ * @lock: a lock for this channel data
+ * @host: a pointer to the host (internal use)
+ * @paused: whether the channel is paused
+ */
+struct pl08x_dma_chan {
+	struct dma_chan chan;
+	struct pl08x_phy_chan *phychan;
+	struct tasklet_struct tasklet;
+	char *name;
+	struct pl08x_channel_data *cd;
+	dma_addr_t runtime_addr;
+	enum dma_data_direction	runtime_direction;
+	atomic_t last_issued;
+	dma_cookie_t lc;
+	struct list_head desc_list;
+	struct pl08x_txd *at;
+	spinlock_t lock;
+	void *host;
+	bool paused;
+};
+
+/**
+ * struct pl08x_platform_data - the platform configuration for the
+ * PL08x PrimeCells.
+ * @slave_channels: the channels defined for the different devices on the
+ * platform, all inclusive, including multiplexed channels. The available
+ * physical channels will be multiplexed around these signals as they
+ * are requested, just enumerate all possible channels.
+ * @get_signal: request a physical signal to be used for a DMA
+ * transfer immediately: if there is some multiplexing or similar blocking
+ * the use of the channel the transfer can be denied by returning
+ * less than zero, else it returns the allocated signal number
+ * @put_signal: indicate to the platform that this physical signal is not
+ * running any DMA transfer and multiplexing can be recycled
+ * @bus_bit_lli: Bit[0] of the address indicated which AHB bus master the
+ * LLI addresses are on 0/1 Master 1/2.
+ */
+struct pl08x_platform_data {
+	struct pl08x_channel_data *slave_channels;
+	unsigned int num_slave_channels;
+	struct pl08x_channel_data memcpy_channel;
+	int (*get_signal)(struct pl08x_dma_chan *);
+	void (*put_signal)(struct pl08x_dma_chan *);
+};
+
+bool pl08x_filter_id(struct dma_chan *chan, void *chan_id);
+
+#endif	/* AMBA_PL08X_H */
-- 
1.7.0.1



From harishpresent at gmail.com  Mon Jun 28 06:20:24 2010
From: harishpresent at gmail.com (Harishkumar V)
Date: Mon, 28 Jun 2010 15:50:24 +0530
Subject: soft lockup - CPU#0 stuck for 61s! problem
In-Reply-To: <20100628090036.GA28510@n2100.arm.linux.org.uk>
References: <AANLkTimqNv37LkJDyKJp9PnJapXH4naINhx-T2ysQi4D@mail.gmail.com>
	<20100628090036.GA28510@n2100.arm.linux.org.uk>
Message-ID: <AANLkTin_iY-7nUwtf1q7Fz4qdnkA0BUktEC6WwCiQdOX@mail.gmail.com>

Russell,

thanks,

Will capture the further messages and mail u. Why an IRQ got struck, is
their a way to handle this....

On Mon, Jun 28, 2010 at 2:30 PM, Russell King - ARM Linux <
linux at arm.linux.org.uk> wrote:

> On Mon, Jun 28, 2010 at 11:25:04AM +0530, Harishkumar V wrote:
> > BUG: soft lockup - CPU#0 stuck for 61s! [linphone-3:764]
> > Modules linked in:
> >
> > Pid: 764, comm:           linphone-3
> > CPU: 0    Not tainted  (2.6.28-rc9 #14)
> > PC is at handle_IRQ_event+0x28/0x74
> > LR is at handle_level_irq+0x94/0xec
>
> That suggests a stuck IRQ.
>
> > pc : [<c008cc30>]    lr : [<c008e18c>]    psr: 48000113
> > sp : c7eede90  ip : c7eedeb0  fp : c7eedeac
> > r10: 0000001d  r9 : c0638ba8  r8 : 00000000
> > r7 : 0000005c  r6 : 00000000  r5 : 0000005c  r4 : c7a1b360
> > r3 : 00000000  r2 : 0000006e  r1 : c7a1b360  r0 : 0000005c
>
> which might be irq 92.
>
> > Exception stack(0xc7eede48 to 0xc7eede90)
> > de40:                   0000005c c7a1b360 0000006e 00000000 c7a1b360
> > 0000005c
> > de60: 00000000 0000005c 00000000 c0638ba8 0000001d c7eedeac c7eedeb0
> > c7eede90
> > de80: c008e18c c008cc30 48000113 ffffffff
> >  r5:d8200000 r4:ffffffff
>
> These messages should continue - and contain some further useful
> information to confirm the stuck IRQ.
>



-- 
Thanks and Regards,
Harish Kumar. V
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From inki.dae at samsung.com  Tue Jun 29 06:49:33 2010
From: inki.dae at samsung.com (InKi Dae)
Date: Tue, 29 Jun 2010 19:49:33 +0900
Subject: [PATCH 1/3] FB: Add some members for CPU Interface.
Message-ID: <4C29CFBD.3040205@samsung.com>

 CPU interface needs cs, wr setup, wr act and hold delay.
I added some members for them to common framework.

Signed-off-by: InKi Dae <inki.dae at samsung.com <mailto:p.osciak at samsung.com>>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com
<mailto:kyungmin.park at samsung.com>>
---

diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c

index 0a4dbdc..74122d1 100644
--- a/drivers/video/modedb.c
+++ b/drivers/video/modedb.c
@@ -759,6 +759,27 @@ void fb_videomode_to_var(struct fb_var_screeninfo *var,
 }
 
 /**
+ * fb_cpumode_to_var - convert fb_cpumode to fb_var_screeninfo
+ * @var: pointer to struct fb_var_screeninfo
+ * @mode: pointer to struct fb_cpumode
+ */
+void fb_cmdmode_to_var(struct fb_var_screeninfo *var,
+			 const struct fb_cmdmode *mode)
+{
+	var->xres = mode->xres;
+	var->yres = mode->yres;
+	var->xres_virtual = mode->xres;
+	var->yres_virtual = mode->yres;
+	var->xoffset = 0;
+	var->yoffset = 0;
+	var->pixclock = mode->pixclock;
+	var->cs_setup = mode->cs_setup;
+	var->wr_setup = mode->wr_setup;
+	var->wr_act = mode->wr_act;
+	var->wr_hold = mode->wr_hold;
+}
+
+/**
  * fb_mode_is_equal - compare 2 videomodes
  * @mode1: first videomode
  * @mode2: second videomode
@@ -1048,6 +1069,7 @@ finished:
 EXPORT_SYMBOL(fb_find_best_display);
 
 EXPORT_SYMBOL(fb_videomode_to_var);
+EXPORT_SYMBOL(fb_cmdmode_to_var);
 EXPORT_SYMBOL(fb_var_to_videomode);
 EXPORT_SYMBOL(fb_mode_is_equal);
 EXPORT_SYMBOL(fb_add_videomode);
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 907ace3..73381c3 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -269,6 +269,12 @@ struct fb_var_screeninfo {
 	__u32 vmode;			/* see FB_VMODE_*		*/
 	__u32 rotate;			/* angle we rotate counter clockwise */
 	__u32 reserved[5];		/* Reserved for future compatibility */
+
+	/* For cpu interface timing. */
+	__u32 cs_setup;
+	__u32 wr_setup;
+	__u32 wr_act;
+	__u32 wr_hold;
 };
 
 struct fb_cmap {
@@ -1117,11 +1123,24 @@ struct fb_videomode {
 	u32 lower_margin;
 	u32 hsync_len;
 	u32 vsync_len;
+	u32 cmd_allow_len;
 	u32 sync;
 	u32 vmode;
 	u32 flag;
 };
 
+struct fb_cmdmode {
+	const char *name;	/* optional */
+	u32 refresh;		/* optional */
+	u32 xres;
+	u32 yres;
+	u32 pixclock;
+	u32 cs_setup;
+	u32 wr_setup;
+	u32 wr_act;
+	u32 wr_hold;
+};
+
 extern const char *fb_mode_option;
 extern const struct fb_videomode vesa_modes[];
 


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From inki.dae at samsung.com  Tue Jun 29 06:51:15 2010
From: inki.dae at samsung.com (InKi Dae)
Date: Tue, 29 Jun 2010 19:51:15 +0900
Subject: [PATCH 2/3] S5PV210: FB: Add MIPI-DSI and CPU Interface features.
Message-ID: <4C29D023.7090105@samsung.com>

 this patch adds features for supportting MIPI Interface and CPU mode to
s3c-fb.c

for this, I added following features.
. add struct fb_cmdmode
- this structure would be used for cpu interface.
. add interface_mode to struct s3c_fb_platdata.
- this variable would be used to distinguishe whether CPU or RGB mode.
. add two functions for cpu interface.
- s3c_fb_set_trigger would be used for to send trigger signal to FIMD.
- s3c_fb_is_i80_frame_done would be used to check framedone status.
. add a function for setting timing.
- I added this function because it have to distinguishe interfaces.
(CPU or RGB mode)
. add register definitions for using MIPI-DSI mode.

Signed-off-by: InKi Dae <inki.dae at samsung.com <mailto:p.osciak at samsung.com>>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com
<mailto:kyungmin.park at samsung.com>>
---

diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 27d3b49..193f6ea 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -22,6 +22,11 @@
  */
 #define S3C_FB_MAX_WIN	(5)
 
+enum {
+	FIMD_VIDEO_MODE = 0,
+	FIMD_COMMAND_MODE
+};
+
 /**
  * struct s3c_fb_pd_win - per window setup data
  * @win_mode: The display parameters to initialise (not for window 0)
@@ -30,6 +35,7 @@
  */
 struct s3c_fb_pd_win {
 	struct fb_videomode	win_mode;
+	struct fb_cmdmode	cmd_mode;
 
 	unsigned short		default_bpp;
 	unsigned short		max_bpp;
@@ -42,6 +48,7 @@ struct s3c_fb_pd_win {
  * @setup_gpio: Setup the external GPIO pins to the right state to transfer
  *		the data from the display system to the connected display
  *		device.
+ * @interface_mode: cpu mode or rgb mode.
  * @vidcon0: The base vidcon0 values to control the panel data format.
  * @vidcon1: The base vidcon1 values to control the panel data output.
  * @win: The setup data for each hardware window, or NULL for unused.
@@ -57,6 +64,7 @@ struct s3c_fb_platdata {
 	void	(*setup_gpio)(void);
 
 	struct s3c_fb_pd_win	*win[S3C_FB_MAX_WIN];
+	u32			interface_mode;
 
 	u32			 vidcon0;
 	u32			 vidcon1;
@@ -91,4 +99,10 @@ extern void s5pc100_fb_gpio_setup_24bpp(void);
  */
 extern void s5pv210_fb_gpio_setup_24bpp(void);
 
+struct fb_info;
+
+extern void s3c_fb_set_trigger(struct fb_info *info);
+
+extern int s3c_fb_is_i80_frame_done(struct fb_info *info);
+
 #endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
index 0f43599..4d5954b 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb-v4.h
@@ -135,6 +135,22 @@
 
 #define WPALCON					(0x1A0)
 
+/* For CPU interface. */
+#define TRIGCON						(0x1a4)
+#define TRGMODE_I80_ENABLE				(1 << 0)
+#define SWTRGCMD_I80_TRIGGER				(1 << 1)
+#define SWFRSTATUS_I80					(1 << 2)
+
+#define I80IFCONA0					(0x1b0)
+#define I80IFEN_ENABLE					(1 << 0)
+#define RSPOL_HIGH					(1 << 2)
+#define LCD_WR_HOLD(x)					(((x) & 0xf) << 4)
+#define LCD_WR_ACT(x)					(((x) & 0xf) << 8)
+#define LCD_WR_SETUP(x)					(((x) & 0xf) << 12)
+#define LCD_CS_SETUP(x)					(((x) & 0xf) << 16)
+
+#define I80IFCONB0					(0x1b8)
+
 /* Palette control */
 /* Note for S5PC100: you can still use those macros on WPALCON (aka WPALCON_L),
  * but make sure that WPALCON_H W2PAL-W4PAL entries are zeroed out */
diff --git a/arch/arm/plat-samsung/include/plat/regs-fb.h b/arch/arm/plat-samsung/include/plat/regs-fb.h
index 0ef806e..70342aa 100644
--- a/arch/arm/plat-samsung/include/plat/regs-fb.h
+++ b/arch/arm/plat-samsung/include/plat/regs-fb.h
@@ -38,6 +38,7 @@
 #define VIDCON0_VIDOUT_TV			(0x1 << 26)
 #define VIDCON0_VIDOUT_I80_LDI0			(0x2 << 26)
 #define VIDCON0_VIDOUT_I80_LDI1			(0x3 << 26)
+#define VIDCON0_DSI_EN_ENABLE			(1 << 30)
 
 #define VIDCON0_L1_DATA_MASK			(0x7 << 23)
 #define VIDCON0_L1_DATA_SHIFT			(23)
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 9682ecc..8063427 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -135,6 +135,18 @@ static int s3c_fb_check_var(struct fb_var_screeninfo *var,
 	var->transp.offset = 0;
 	var->transp.length = 0;
 
+	/* ensure input timing values are same as machine setting ones. */
+	if (sfb->pdata->interface_mode == FIMD_COMMAND_MODE) {
+		if (var->cs_setup != info->var.cs_setup)
+			var->cs_setup = info->var.cs_setup;
+		if (var->wr_setup != info->var.wr_setup)
+			var->wr_setup = info->var.wr_setup;
+		if (var->wr_act != info->var.wr_act)
+			var->wr_act = info->var.wr_act;
+		if (var->wr_hold != info->var.wr_hold)
+			var->wr_hold = info->var.wr_hold;
+	}
+
 	switch (var->bits_per_pixel) {
 	case 1:
 	case 2:
@@ -255,6 +267,70 @@ static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
 }
 
 /**
+ * s3c_fb_set_trigger - fimd trigger based on cpu interface.
+ */
+void s3c_fb_set_trigger(struct fb_info *info)
+{
+	struct s3c_fb_win *win = info->par;
+	struct s3c_fb *sfb = win->parent;
+	void __iomem *regs = sfb->regs;
+	u32 reg = 0;
+
+	reg = readl(regs + TRIGCON);
+
+	reg |= TRGMODE_I80_ENABLE | SWTRGCMD_I80_TRIGGER;
+
+	writel(reg, regs + TRIGCON);
+}
+
+/**
+ * s3c_fb_is_i80_frame_done - get i80 frame done status.
+ */
+int s3c_fb_is_i80_frame_done(struct fb_info *info)
+{
+	struct s3c_fb_win *win = info->par;
+	struct s3c_fb *sfb = win->parent;
+	void __iomem *regs = sfb->regs;
+	u32 reg = 0;
+
+	reg =  readl(regs + TRIGCON);
+
+	return (((reg & SWFRSTATUS_I80) == SWFRSTATUS_I80) ? 1 : 0);
+}
+
+/**
+ * s3c_fb_set_cpu_timing - set cpu timing.
+ */
+static void s3c_fb_set_timing(struct s3c_fb *sfb, struct fb_var_screeninfo *var)
+{
+	void __iomem *regs = sfb->regs;
+	u32 reg = 0;
+
+	if (sfb->pdata->interface_mode == FIMD_VIDEO_MODE) {
+		reg = VIDTCON0_VBPD(var->upper_margin - 1) |
+		       VIDTCON0_VFPD(var->lower_margin - 1) |
+		       VIDTCON0_VSPW(var->vsync_len - 1);
+
+		writel(reg, regs + VIDTCON0);
+
+		reg = VIDTCON1_HBPD(var->left_margin - 1) |
+		       VIDTCON1_HFPD(var->right_margin - 1) |
+		       VIDTCON1_HSPW(var->hsync_len - 1);
+
+		writel(reg, regs + VIDTCON1);
+	} else if (sfb->pdata->interface_mode == FIMD_COMMAND_MODE) {
+		reg = LCD_CS_SETUP(var->cs_setup) |
+			LCD_WR_SETUP(var->wr_setup) |
+			LCD_WR_ACT(var->wr_act) |
+			LCD_WR_HOLD(var->wr_hold) |
+			I80IFEN_ENABLE;
+
+		writel(reg, regs + I80IFCONA0);
+	} else
+		dev_warn(sfb->dev, "wrong interface type.\n");
+}
+
+/**
  * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
  * @info: The framebuffer to change.
  *
@@ -318,17 +394,7 @@ static int s3c_fb_set_par(struct fb_info *info)
 		data |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 		writel(data, regs + VIDCON0);
 
-		data = VIDTCON0_VBPD(var->upper_margin - 1) |
-		       VIDTCON0_VFPD(var->lower_margin - 1) |
-		       VIDTCON0_VSPW(var->vsync_len - 1);
-
-		writel(data, regs + VIDTCON0);
-
-		data = VIDTCON1_HBPD(var->left_margin - 1) |
-		       VIDTCON1_HFPD(var->right_margin - 1) |
-		       VIDTCON1_HSPW(var->hsync_len - 1);
-
-		writel(data, regs + VIDTCON1);
+		s3c_fb_set_timing(sfb, var);
 
 		data = VIDTCON2_LINEVAL(var->yres - 1) |
 		       VIDTCON2_HOZVAL(var->xres - 1);
@@ -744,7 +810,8 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 				      struct s3c_fb_win **res)
 {
 	struct fb_var_screeninfo *var;
-	struct fb_videomode *initmode;
+	struct fb_videomode *videomode;
+	struct fb_cmdmode *cmdmode;
 	struct s3c_fb_pd_win *windata;
 	struct s3c_fb_win *win;
 	struct fb_info *fbinfo;
@@ -763,11 +830,20 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 	}
 
 	windata = sfb->pdata->win[win_no];
-	initmode = &windata->win_mode;
 
 	WARN_ON(windata->max_bpp == 0);
-	WARN_ON(windata->win_mode.xres == 0);
-	WARN_ON(windata->win_mode.yres == 0);
+
+	if (sfb->pdata->interface_mode == FIMD_VIDEO_MODE) {
+		WARN_ON(windata->win_mode.xres == 0);
+		WARN_ON(windata->win_mode.yres == 0);
+
+		videomode = &windata->win_mode;
+	} else {
+		WARN_ON(windata->cmd_mode.xres == 0);
+		WARN_ON(windata->cmd_mode.yres == 0);
+
+		cmdmode = &windata->cmd_mode;
+	}
 
 	win = fbinfo->par;
 	var = &fbinfo->var;
@@ -777,18 +853,24 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 	win->index = win_no;
 	win->palette_buffer = (u32 *)(win + 1);
 
-	ret = s3c_fb_alloc_memory(sfb, win);
-	if (ret) {
-		dev_err(sfb->dev, "failed to allocate display memory\n");
-		return ret;
+	/* setup the initial video or cpu modefrom the window */
+	if (sfb->pdata->interface_mode == FIMD_VIDEO_MODE)
+		fb_videomode_to_var(&fbinfo->var, videomode);
+	else {
+		var->xres = cmdmode->xres;
+		var->yres = cmdmode->yres;
+		var->xres_virtual = cmdmode->xres;
+		var->yres_virtual = cmdmode->yres;
+		var->xoffset = 0;
+		var->yoffset = 0;
+		var->pixclock = cmdmode->pixclock;
+
+		var->cs_setup = cmdmode->cs_setup;
+		var->wr_setup = cmdmode->wr_setup;
+		var->wr_act = cmdmode->wr_act;
+		var->wr_hold = cmdmode->wr_hold;
 	}
 
-	/* setup the r/b/g positions for the window's palette */
-	s3c_fb_init_palette(win_no, &win->palette);
-
-	/* setup the initial video mode from the window */
-	fb_videomode_to_var(&fbinfo->var, initmode);
-
 	fbinfo->fix.type	= FB_TYPE_PACKED_PIXELS;
 	fbinfo->fix.accel	= FB_ACCEL_NONE;
 	fbinfo->var.activate	= FB_ACTIVATE_NOW;
@@ -798,6 +880,15 @@ static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
 	fbinfo->flags		= FBINFO_FLAG_DEFAULT;
 	fbinfo->pseudo_palette  = &win->pseudo_palette;
 
+	ret = s3c_fb_alloc_memory(sfb, win);
+	if (ret) {
+		dev_err(sfb->dev, "failed to allocate display memory\n");
+		return ret;
+	}
+
+	/* setup the r/b/g positions for the window's palette */
+	s3c_fb_init_palette(win_no, &win->palette);
+
 	/* prepare to actually start the framebuffer */
 
 	ret = s3c_fb_check_var(&fbinfo->var, fbinfo);


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From inki.dae at samsung.com  Tue Jun 29 06:52:37 2010
From: inki.dae at samsung.com (InKi Dae)
Date: Tue, 29 Jun 2010 19:52:37 +0900
Subject: [PATCH 3/3] S5PV210: Add MIPI-DSI Driver.
Message-ID: <4C29D075.1070605@samsung.com>

 this patch addes MIPI-DSI Driver.

to use this driver, some structures below should be added to machine
specific file.

struct dsim_config
- define clock info, data lane count and video mode info for MIPI-DSI
Controller.

struct dsim_lcd_config
- define interface mode, channel ID, Pixel format and so on.

struct s5p_platform_dsim
- define callbacks for initializing D-PHY, MIPI reset and trigger
releated interfaces of s3c-fb.c file.

Signed-off-by: InKi Dae <inki.dae at samsung.com <mailto:p.osciak at samsung.com>>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com
<mailto:kyungmin.park at samsung.com>>
---

diff --git a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
b/arch/arm/mach-s5pv210/include/mach/regs-clock.h

index 2a25ab4..f716678 100644
--- a/arch/arm/mach-s5pv210/include/mach/regs-clock.h
+++ b/arch/arm/mach-s5pv210/include/mach/regs-clock.h
@@ -162,6 +162,7 @@
 
 /* MIPI */
 #define S5P_MIPI_DPHY_EN		(3)
+#define S5P_MIPI_M_RESETN		(1 << 1)
 
 /* S5P_DAC_CONTROL */
 #define S5P_DAC_ENABLE			(1)
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index b1d82cc..3cd43f2 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -49,6 +49,9 @@ obj-$(CONFIG_S3C_DEV_RTC)	+= dev-rtc.o
 obj-$(CONFIG_SAMSUNG_DEV_ADC)	+= dev-adc.o
 obj-$(CONFIG_SAMSUNG_DEV_TS)	+= dev-ts.o
 
+# Device setup - MIPI-DSI
+obj-$(CONFIG_S5P_MIPI_DSI)  += setup-dsim.o
+
 # DMA support
 
 obj-$(CONFIG_S3C_DMA)		+= dma.o
diff --git a/arch/arm/plat-samsung/include/plat/dsim.h b/arch/arm/plat-samsung/include/plat/dsim.h
new file mode 100644
index 0000000..28bc595
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/dsim.h
@@ -0,0 +1,470 @@
+/* linux/arm/arch/mach-s5pc110/include/mach/dsim.h
+ *
+ * Platform data header for Samsung MIPI-DSIM.
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ * InKi Dae <inki.dae at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _DSIM_H
+#define _DSIM_H
+
+#include <linux/device.h>
+
+/* h/w configuration */
+#define MIPI_FIN		24000000
+#define DSIM_TIMEOUT_MS		5000
+#define DSIM_NO_OF_INTERRUPT	26
+#define DSIM_PM_STABLE_TIME	10
+
+#define DSIM_TRUE		1
+#define DSIM_FALSE		0
+
+#define DSIM_HEADER_FIFO_SZ	16
+
+enum dsim_interface_type {
+	DSIM_COMMAND = 0,
+	DSIM_VIDEO = 1,
+};
+
+enum dsim_state {
+	DSIM_STATE_RESET = 0,
+	DSIM_STATE_INIT = 1,
+	DSIM_STATE_STOP = 2,
+	DSIM_STATE_HSCLKEN = 3,
+	DSIM_STATE_ULPS = 4,
+};
+
+enum {
+	DSIM_NONE_STATE = 0,
+	DSIM_RESUME_COMPLETE = 1,
+	DSIM_FRAME_DONE = 2,
+};
+
+enum dsim_virtual_ch_no {
+	DSIM_VIRTUAL_CH_0 = 0,
+	DSIM_VIRTUAL_CH_1 = 1,
+	DSIM_VIRTUAL_CH_2 = 2,
+	DSIM_VIRTUAL_CH_3 = 3,
+};
+
+enum dsim_video_mode_type {
+	DSIM_NON_BURST_SYNC_EVENT = 0,
+	DSIM_NON_BURST_SYNC_PULSE = 2,
+	DSIM_BURST = 3,
+	DSIM_NON_VIDEO_MODE = 4,
+};
+
+enum dsim_fifo_state {
+	DSIM_RX_DATA_FULL = (1 << 25),
+	DSIM_RX_DATA_EMPTY = (1 << 24),
+	SFR_HEADER_FULL = (1 << 23),
+	SFR_HEADER_EMPTY = (1 << 22),
+	SFR_PAYLOAD_FULL = (1 << 21),
+	SFR_PAYLOAD_EMPTY = (1 << 20),
+	I80_HEADER_FULL = (1 << 19),
+	I80_HEADER_EMPTY = (1 << 18),
+	I80_PALOAD_FULL = (1 << 17),
+	I80_PALOAD_EMPTY = (1 << 16),
+	SUB_DISP_HEADER_FULL = (1 << 15),
+	SUB_DISP_HEADER_EMPTY = (1 << 14),
+	SUB_DISP_PAYLOAD_FULL = (1 << 13),
+	SUB_DISP_PAYLOAD_EMPTY = (1 << 12),
+	MAIN_DISP_HEADER_FULL = (1 << 11),
+	MAIN_DISP_HEADER_EMPTY = (1 << 10),
+	MAIN_DISP_PAYLOAD_FULL = (1 << 9),
+	MAIN_DISP_PAYLOAD_EMPTY = (1 << 8),
+};
+
+enum dsim_no_of_data_lane {
+	DSIM_DATA_LANE_1 = 0,
+	DSIM_DATA_LANE_2 = 1,
+	DSIM_DATA_LANE_3 = 2,
+	DSIM_DATA_LANE_4 = 3,
+};
+
+enum dsim_byte_clk_src {
+	DSIM_PLL_OUT_DIV8 = 0,
+	DSIM_EXT_CLK_DIV8 = 1,
+	DSIM_EXT_CLK_BYPASS = 2,
+};
+
+enum dsim_lane {
+	DSIM_LANE_DATA0 = (1 << 0),
+	DSIM_LANE_DATA1 = (1 << 1),
+	DSIM_LANE_DATA2 = (1 << 2),
+	DSIM_LANE_DATA3 = (1 << 3),
+	DSIM_LANE_DATA_ALL = 0xf,
+	DSIM_LANE_CLOCK = (1 << 4),
+	DSIM_LANE_ALL = DSIM_LANE_CLOCK | DSIM_LANE_DATA_ALL,
+};
+
+enum dsim_pixel_format {
+	DSIM_CMD_3BPP = 0,
+	DSIM_CMD_8BPP = 1,
+	DSIM_CMD_12BPP = 2,
+	DSIM_CMD_16BPP = 3,
+	DSIM_VID_16BPP_565 = 4,
+	DSIM_VID_18BPP_666PACKED = 5,
+	DSIM_18BPP_666LOOSELYPACKED = 6,
+	DSIM_24BPP_888 = 7,
+};
+
+enum dsim_lane_state {
+	DSIM_LANE_STATE_HS_READY,
+	DSIM_LANE_STATE_ULPS,
+	DSIM_LANE_STATE_STOP,
+	DSIM_LANE_STATE_LPDT,
+};
+
+enum dsim_transfer {
+	DSIM_TRANSFER_NEITHER	= 0,
+	DSIM_TRANSFER_BYCPU	= (1 << 7),
+	DSIM_TRANSFER_BYLCDC	= (1 << 6),
+	DSIM_TRANSFER_BOTH	= (0x3 << 6)
+};
+
+enum dsim_lane_change {
+	DSIM_NO_CHANGE = 0,
+	DSIM_DATA_LANE_CHANGE = 1,
+	DSIM_CLOCK_NALE_CHANGE = 2,
+	DSIM_ALL_LANE_CHANGE = 3,
+};
+
+enum dsim_int_src {
+	DSIM_ALL_OF_INTR = 0xffffffff,
+	DSIM_PLL_STABLE = (1 << 31),
+};
+
+enum dsim_data_id {
+	/* short packet types of packet types for command */
+	GEN_SHORT_WR_NO_PARA	= 0x03,
+	GEN_SHORT_WR_1_PARA	= 0x13,
+	GEN_SHORT_WR_2_PARA	= 0x23,
+	GEN_RD_NO_PARA		= 0x04,
+	GEN_RD_1_PARA		= 0x14,
+	GEN_RD_2_PARA		= 0x24,
+	DCS_WR_NO_PARA		= 0x05,
+	DCS_WR_1_PARA		= 0x15,
+	DCS_RD_NO_PARA		= 0x06,
+	SET_MAX_RTN_PKT_SIZE	= 0x37,
+
+	/* long packet types of packet types for command */
+	NULL_PKT		= 0x09,
+	BLANKING_PKT		= 0x19,
+	GEN_LONG_WR		= 0x29,
+	DCS_LONG_WR		= 0x39,
+
+	/* short packet types of generic command */
+	CMD_OFF			= 0x02,
+	CMD_ON			= 0x12,
+	SHUT_DOWN		= 0x22,
+	TURN_ON			= 0x32,
+
+	/* short packet types for video data */
+	VSYNC_START		= 0x01,
+	VSYNC_END		= 0x11,
+	HSYNC_START		= 0x21,
+	HSYNC_END		= 0x31,
+	EOT_PKT			= 0x08,
+
+	/* long packet types for video data */
+	RGB565_PACKED		= 0x0e,
+	RGB666_PACKED		= 0x1e,
+	RGB666_LOOSLY		= 0x2e,
+	RGB888_PACKED		= 0x3e,
+};
+
+/**
+ * struct dsim_config - interface for configuring mipi-dsi controller.
+ *
+ * @auto_flush: enable or disable Auto flush of MD FIFO using VSYNC pulse.
+ * @eot_disable: enable or disable EoT packet in HS mode.
+ * @auto_vertical_cnt: specifies auto vertical count mode.
+ *	in Video mode, the vertical line transition uses line counter
+ *	configured by VSA, VBP, and Vertical resolution.
+ *	If this bit is set to '1', the line counter does not use VSA and VBP
+ *	registers.(in command mode, this variable is ignored)
+ * @hse: set horizontal sync event mode.
+ *	In VSYNC pulse and Vporch area, MIPI DSI master transfers only HSYNC
+ *	start packet to MIPI DSI slave at MIPI DSI spec1.1r02.
+ *	this bit transfers HSYNC end packet in VSYNC pulse and Vporch area
+ *	(in mommand mode, this variable is ignored)
+ * @hfp: specifies HFP disable mode.
+ *	if this variable is set, DSI master ignores HFP area in VIDEO mode.
+ *	(in command mode, this variable is ignored)
+ * @hbp: specifies HBP disable mode.
+ *	if this variable is set, DSI master ignores HBP area in VIDEO mode.
+ *	(in command mode, this variable is ignored)
+ * @hsa: specifies HSA disable mode.
+ *	if this variable is set, DSI master ignores HSA area in VIDEO mode.
+ *	(in command mode, this variable is ignored)
+ * @e_no_data_lane: specifies data lane count to be used by Master.
+ * @e_byte_clk: select byte clock source. (it must be DSIM_PLL_OUT_DIV8)
+ *	DSIM_EXT_CLK_DIV8 and DSIM_EXT_CLK_BYPASSS are not supported.
+ * @pll_stable_time: specifies the PLL Timer for stability of the ganerated
+ *	clock(System clock cycle base)
+ *	if the timer value goes to 0x00000000, the clock stable bit of status
+ *	and interrupt register is set.
+ * @esc_clk: specifies escape clock frequency for getting the escape clock
+ *	prescaler value.
+ * @stop_holding_cnt: specifies the interval value between transmitting
+ *	read packet(or write "set_tear_on" command) and BTA request.
+ *	after transmitting read packet or write "set_tear_on" command,
+ *	BTA requests to D-PHY automatically. this counter value specifies
+ *	the interval between them.
+ * @bta_timeout: specifies the timer for BTA.
+ *	this register specifies time out from BTA request to change
+ *	the direction with respect to Tx escape clock.
+ * @rx_timeout: specifies the timer for LP Rx mode timeout.
+ *	this register specifies time out on how long RxValid deasserts,
+ *	after RxLpdt asserts with respect to Tx escape clock.
+ *	- RxValid specifies Rx data valid indicator.
+ *	- RxLpdt specifies an indicator that D-PHY is under RxLpdt mode.
+ *	- RxValid and RxLpdt specifies signal from D-PHY.
+ * @e_lane_swap: swaps Dp/Dn channel of Clock lane or Data lane.
+ *	if this bit is set, Dp and Dn channel would be swapped each other.
+ */
+struct dsim_config {
+	unsigned char auto_flush;
+	unsigned char eot_disable;
+
+	unsigned char auto_vertical_cnt;
+	unsigned char hse;
+	unsigned char hfp;
+	unsigned char hbp;
+	unsigned char hsa;
+
+	enum dsim_no_of_data_lane e_no_data_lane;
+	enum dsim_byte_clk_src e_byte_clk;
+
+	/*
+	 * ===========================================
+	 * |    P    |    M    |    S    |    MHz    |
+	 * -------------------------------------------
+	 * |    3    |   100   |    3    |    100    |
+	 * |    3    |   100   |    2    |    200    |
+	 * |    3    |    63   |    1    |    252    |
+	 * |    4    |   100   |    1    |    300    |
+	 * |    4    |   110   |    1    |    330    |
+	 * |   12    |   350   |    1    |    350    |
+	 * |    3    |   100   |    1    |    400    |
+	 * |    4    |   150   |    1    |    450    |
+	 * |    3    |   118   |    1    |    472    |
+	 * |   12    |   250   |    0    |    500    |
+	 * |    4    |   100   |    0    |    600    |
+	 * |    3    |    81   |    0    |    648    |
+	 * |    3    |    88   |    0    |    704    |
+	 * |    3    |    90   |    0    |    720    |
+	 * |    3    |   100   |    0    |    800    |
+	 * |   12    |   425   |    0    |    850    |
+	 * |    4    |   150   |    0    |    900    |
+	 * |   12    |   475   |    0    |    950    |
+	 * |    6    |   250   |    0    |   1000    |
+	 * -------------------------------------------
+	 */
+	unsigned char p;
+	unsigned short m;
+	unsigned char s;
+
+	unsigned int pll_stable_time;
+	unsigned long esc_clk;
+
+	unsigned short stop_holding_cnt;
+	unsigned char bta_timeout;
+	unsigned short rx_timeout;
+	enum dsim_video_mode_type e_lane_swap;
+};
+
+/**
+ * struct dsim_lcd_config - interface for configuring mipi-dsi based lcd panel.
+ *
+ * @e_interface: specifies interface to be used.(CPU or RGB interface)
+ * @parameter[0]: specifies virtual channel number
+ *	that main or sub diaplsy uses.
+ * @parameter[1]: specifies pixel stream format for main or sub display.
+ * @parameter[2]: selects Burst mode in Video mode.
+ *	in Non-burst mode, RGB data area is filled with RGB data and NULL
+ *	packets, according to input bandwidth of RGB interface.
+ *	In Burst mode, RGB data area is filled with RGB data only.
+ * @lcd_panel_info: pointer for lcd panel specific structure.
+ *	this structure specifies width, height, timing and polarity and so on.
+ * @mipi_ddi_pd: pointer for lcd panel platform data.
+ */
+struct dsim_lcd_config {
+	enum dsim_interface_type e_interface;
+	unsigned int parameter[3];
+
+	void *lcd_panel_info;
+	void *mipi_ddi_pd;
+};
+
+struct dsim_global;
+struct fb_info;
+
+/**
+ * struct s5p_platform_dsim - interface to platform data for mipi-dsi driver.
+ *
+ * @clk_name: specifies clock name for mipi-dsi.
+ * @lcd_panel_name: specifies lcd panel name registered to mipi-dsi driver.
+ *	lcd panel driver searched would be actived.
+ * @platfrom_rev: specifies platform revision number.
+ *	revision number should become 1.
+ * @dsim_config: pointer of structure for configuring mipi-dsi controller.
+ * @dsim_lcd_info: pointer to structure for configuring
+ *	mipi-dsi based lcd panel.
+ * @mipi_power: callback pointer for enabling or disabling mipi power.
+ * @part_reset: callback pointer for reseting mipi phy.
+ * @init_d_phy: callback pointer for enabing d_phy of dsi master.
+ * @get_fb_frame_done: callback pointer for getting frame done status of the
+ *	display controller(FIMD).
+ * @trigger: callback pointer for triggering display controller(FIMD)
+ *	in case of CPU mode.
+ * @delay_for_stabilization: specifies stable time.
+ *	this delay needs when writing data on SFR
+ *	after mipi mode became LP mode.
+ */
+struct s5p_platform_dsim {
+	char	*clk_name;
+	char	lcd_panel_name[64];
+	unsigned int platform_rev;
+
+	struct dsim_config *dsim_info;
+	struct dsim_lcd_config *dsim_lcd_info;
+
+	unsigned int delay_for_stabilization;
+
+	int (*mipi_power) (struct dsim_global *dsim, void *p_mipi_1_1v,
+		void *p_mipi_1_8v, int enable);
+	int (*part_reset) (struct dsim_global *dsim);
+	int (*init_d_phy) (struct dsim_global *dsim);
+	int (*get_fb_frame_done) (struct fb_info *info);
+	void (*trigger) (struct fb_info *info);
+};
+
+/**
+ * struct dsim_global - global interface for mipi-dsi driver.
+ *
+ * @dev: driver model representation of the device.
+ * @clock: pointer to MIPI-DSI clock of clock framework.
+ * @irq: interrupt number to MIPI-DSI controller.
+ * @reg_base: base address to memory mapped SRF of MIPI-DSI controller.
+ *	(virtual address)
+ * @r_mipi_1_1v: pointer to regulator for MIPI 1.1v power.
+ * @r_mipi_1_8v: pointer to regulator for MIPI 1.8v power.
+ * @pd: pointer to MIPI-DSI driver platform data.
+ * @dsim_lcd_info: pointer to structure for configuring
+ *	mipi-dsi based lcd panel.
+ * @lcd_panel_info: pointer for lcd panel specific structure.
+ *	this structure specifies width, height, timing and polarity and so on.
+ * @mipi_ddi_pd: pointer for lcd panel platform data.
+ * @mipi_drv: pointer to driver structure for mipi-dsi based lcd panel.
+ * @s3cfb_notif: kernel notifier structure to be registered
+ *	by device specific framebuffer driver.
+ *	this notifier could be used by fb_blank of device specifiec
+ *	framebuffer driver.
+ * @state: specifies status of MIPI-DSI controller.
+ *	the status could be RESET, INIT, STOP, HSCLKEN and ULPS.
+ * @data_lane: specifiec enabled data lane number.
+ *	this variable would be set by driver according to e_no_data_lane
+ *	automatically.
+ * @e_clk_src: select byte clock source.
+ *	this variable would be set by driver according to e_byte_clock
+ *	automatically.
+ * @hs_clk: HS clock rate.
+ *	this variable would be set by driver automatically.
+ * @byte_clk: Byte clock rate.
+ *	this variable would be set by driver automatically.
+ * @escape_clk: ESCAPE clock rate.
+ *	this variable would be set by driver automatically.
+ * @freq_band: indicates Bitclk frequency band for D-PHY global timing.
+ *	Serial Clock(=ByteClk X 8)		FreqBand[3:0]
+ *		~ 99.99 MHz				0000
+ *		100 ~ 119.99 MHz			0001
+ *		120 ~ 159.99 MHz			0010
+ *		160 ~ 199.99 MHz			0011
+ *		200 ~ 239.99 MHz			0100
+ *		140 ~ 319.99 MHz			0101
+ *		320 ~ 389.99 MHz			0110
+ *		390 ~ 449.99 MHz			0111
+ *		450 ~ 509.99 MHz			1000
+ *		510 ~ 559.99 MHz			1001
+ *		560 ~ 639.99 MHz			1010
+ *		640 ~ 689.99 MHz			1011
+ *		690 ~ 769.99 MHz			1100
+ *		770 ~ 869.99 MHz			1101
+ *		870 ~ 949.99 MHz			1110
+ *		950 ~ 1000 MHz				1111
+ *	this variable would be calculated by driver automatically.
+ *
+ * @header_fifo_index: specifies header fifo index.
+ *	this variable is not used yet.
+ */
+struct dsim_global {
+	struct device *dev;
+	struct clk *clock;
+	unsigned int irq;
+	unsigned int reg_base;
+
+	struct regulator *r_mipi_1_1v;
+	struct regulator *r_mipi_1_8v;
+
+	struct s5p_platform_dsim *pd;
+	struct dsim_config *dsim_info;
+	struct dsim_lcd_config *dsim_lcd_info;
+	struct fb_videomode *lcd_panel_info;
+	struct mipi_ddi_platform_data *mipi_ddi_pd;
+	struct mipi_lcd_driver *mipi_drv;
+	struct notifier_block s3cfb_notif;
+
+	unsigned char state;
+	unsigned int data_lane;
+	enum dsim_byte_clk_src e_clk_src;
+	unsigned long hs_clk;
+	unsigned long byte_clk;
+	unsigned long escape_clk;
+	unsigned char freq_band;
+
+	char header_fifo_index[DSIM_HEADER_FIFO_SZ];
+};
+
+/*
+ * driver structure for mipi-dsi based lcd panel.
+ *
+ * this structure should be registered by lcd panel driver.
+ * mipi-dsi driver seeks lcd panel registered through name field
+ * and calls these callback functions in appropriate time.
+ */
+struct mipi_lcd_driver {
+	s8	name[64];
+
+	s32	(*init)(struct device *dev);
+	void	(*display_on)(struct device *dev);
+	s32	(*set_link)(struct mipi_ddi_platform_data *pd);
+	s32	(*probe)(struct device *dev);
+	s32	(*remove)(struct device *dev);
+	void	(*shutdown)(struct device *dev);
+	s32	(*suspend)(struct device *dev, pm_message_t mesg);
+	s32	(*resume)(struct device *dev);
+};
+
+/*
+ * register mipi_lcd_driver object defined by lcd panel driver
+ * to mipi-dsi driver.
+ */
+extern int s5p_dsim_register_lcd_driver(struct mipi_lcd_driver *lcd_drv);
+
+/* reset MIPI PHY through MIPI PHY CONTROL REGISTER. */
+extern int s5p_dsim_part_reset(struct dsim_global *dsim);
+/* enable MIPI D-PHY and DSI Master block. */
+extern int s5p_dsim_init_d_phy(struct dsim_global *dsim);
+
+/* enable regulators to MIPI-DSI power. */
+extern int s5p_dsim_mipi_power(struct dsim_global *dsim, void *p_mipi_1_1v,
+	void *p_mipi_1_8v, int enable);
+
+#endif /* _DSIM_H */
diff --git a/arch/arm/plat-samsung/include/plat/mipi_ddi.h b/arch/arm/plat-samsung/include/plat/mipi_ddi.h
new file mode 100644
index 0000000..57ed613
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/mipi_ddi.h
@@ -0,0 +1,98 @@
+/* linux/arm/arch/mach-s5pc110/include/mach/mipi_ddi.h
+ *
+ * definitions for DDI based MIPI-DSI.
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ * InKi Dae <inki.dae at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _MIPI_DDI_H
+#define _MIPI_DDI_H
+
+enum mipi_ddi_interface {
+	RGB_IF = 0x4000,
+	I80_IF = 0x8000,
+	YUV_601 = 0x10000,
+	YUV_656 = 0x20000,
+	MIPI_VIDEO = 0x1000,
+	MIPI_COMMAND = 0x2000,
+};
+
+enum mipi_ddi_panel_select {
+	DDI_MAIN_LCD = 0,
+	DDI_SUB_LCD = 1,
+};
+
+enum mipi_ddi_model {
+	S6DR117 = 0,
+};
+
+enum mipi_ddi_parameter {
+	/* DSIM video interface parameter */
+	DSI_VIRTUAL_CH_ID = 0,
+	DSI_FORMAT = 1,
+	DSI_VIDEO_MODE_SEL = 2,
+};
+
+struct lcd_device;
+struct fb_info;
+
+struct mipi_ddi_platform_data {
+	void *dsim_data;
+	/*
+	 * it is used for command mode lcd panel and
+	 * when all contents of framebuffer in panel module are transfered
+	 * to lcd panel it occurs te signal.
+	 *
+	 * note:
+	 * - in case of command mode(cpu mode), it should be triggered only
+	 *   when TE signal of lcd panel and frame done interrupt of display
+	 *   controller or mipi controller occurs.
+	 */
+	unsigned int te_irq;
+
+	/*
+	 * it is used for PM stable time at te interrupt handler and
+	 * could be used according to lcd panel characteristic or not.
+	 */
+	unsigned int resume_complete;
+
+	int (*lcd_reset) (struct lcd_device *ld);
+	int (*lcd_power_on) (struct lcd_device *ld, int enable);
+	int (*backlight_on) (int enable);
+
+	/* transfer command to lcd panel at LP mode. */
+	int (*cmd_write) (void *dsim_data, unsigned int data_id,
+		unsigned int data0, unsigned int data1);
+	int (*cmd_read) (void *dsim_data, unsigned int data_id,
+		unsigned int data0, unsigned int data1);
+	/*
+	 * get the status that all screen data have been transferred
+	 * to mipi-dsi.
+	 */
+	int (*get_dsim_frame_done) (void *dsim_data);
+	int (*clear_dsim_frame_done) (void *dsim_data);
+
+	/*
+	 * changes mipi transfer mode to LP or HS mode.
+	 *
+	 * LP mode needs when some commands like gamma values transfers
+	 * to lcd panel.
+	 */
+	int (*change_dsim_transfer_mode) (int mode);
+
+	/* get frame done status of display controller. */
+	int (*get_fb_frame_done) (struct fb_info *info);
+	/* trigger display controller in case of cpu mode. */
+	void (*trigger) (struct fb_info *info);
+
+	unsigned int reset_delay;
+	unsigned int power_on_delay;
+	unsigned int power_off_delay;
+};
+
+#endif /* _MIPI_DDI_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-dsim.h b/arch/arm/plat-samsung/include/plat/regs-dsim.h
new file mode 100644
index 0000000..dc83089
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/regs-dsim.h
@@ -0,0 +1,281 @@
+/* linux/arch/arm/plat-s5pc11x/include/plat/regs-dsim.h
+ *
+ * Register definition file for Samsung MIPI-DSIM driver
+ *
+ * InKi Dae <inki.dae at samsung.com>, Copyright (c) 2009 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _REGS_DSIM_H
+#define _REGS_DSIM_H
+
+#define S5P_DSIM_STATUS		(0x0)	/* Status register */
+#define S5P_DSIM_SWRST		(0x4)	/* Software reset register */
+#define S5P_DSIM_CLKCTRL	(0x8)	/* Clock control register */
+#define S5P_DSIM_TIMEOUT	(0xc)	/* Time out register */
+#define S5P_DSIM_CONFIG		(0x10)	/* Configuration register */
+#define S5P_DSIM_ESCMODE	(0x14)	/* Escape mode register */
+
+/* Main display image resolution register */
+#define S5P_DSIM_MDRESOL	(0x18)
+#define S5P_DSIM_MVPORCH	(0x1c)	/* Main display Vporch register */
+#define S5P_DSIM_MHPORCH	(0x20)	/* Main display Hporch register */
+#define S5P_DSIM_MSYNC		(0x24)	/* Main display sync area register */
+
+/* Sub display image resolution register */
+#define S5P_DSIM_SDRESOL	(0x28)
+#define S5P_DSIM_INTSRC		(0x2c)	/* Interrupt source register */
+#define S5P_DSIM_INTMSK		(0x30)	/* Interrupt mask register */
+#define S5P_DSIM_PKTHDR		(0x34)	/* Packet Header FIFO register */
+#define S5P_DSIM_PAYLOAD	(0x38)	/* Payload FIFO register */
+#define S5P_DSIM_RXFIFO		(0x3c)	/* Read FIFO register */
+#define S5P_DSIM_FIFOTHLD	(0x40)	/* FIFO threshold level register */
+#define S5P_DSIM_FIFOCTRL	(0x44)	/* FIFO status and control register */
+
+/* FIFO memory AC characteristic register */
+#define S5P_DSIM_MEMACCHR	(0x48)
+#define S5P_DSIM_PLLCTRL	(0x4c)	/* PLL control register */
+#define S5P_DSIM_PLLTMR		(0x50)	/* PLL timer register */
+#define S5P_DSIM_PHYACCHR	(0x54)	/* D-PHY AC characteristic register */
+#define S5P_DSIM_PHYACCHR1	(0x58)	/* D-PHY AC characteristic register1 */
+
+/* DSIM_SWRST */
+#define DSIM_FUNCRST		(1 << 16)
+#define DSIM_SWRST		(1 << 0)
+
+/* S5P_DSIM_TIMEOUT */
+#define DSIM_LPDR_TOUT_SHIFT	(0)
+#define DSIM_BTA_TOUT_SHIFT	(16)
+#define DSIM_LPDR_TOUT(x)	(((x) & 0xffff) << DSIM_LPDR_TOUT_SHIFT)
+#define DSIM_BTA_TOUT(x)	(((x) & 0xff) << DSIM_BTA_TOUT_SHIFT)
+
+/* S5P_DSIM_CLKCTRL */
+#define DSIM_ESC_PRESCALER_SHIFT	(0)
+#define DSIM_LANE_ESC_CLKEN_SHIFT	(19)
+#define DSIM_BYTE_CLKEN_SHIFT		(24)
+#define DSIM_BYTE_CLK_SRC_SHIFT		(25)
+#define DSIM_PLL_BYPASS_SHIFT		(27)
+#define DSIM_ESC_CLKEN_SHIFT		(28)
+#define DSIM_TX_REQUEST_HSCLK_SHIFT	(31)
+#define DSIM_ESC_PRESCALER(x)		(((x) & 0xffff) << \
+						DSIM_ESC_PRESCALER_SHIFT)
+#define DSIM_LANE_ESC_CLKEN(x)		(((x) & 0x1f) << \
+						DSIM_LANE_ESC_CLKEN_SHIFT)
+#define DSIM_BYTE_CLK_ENABLE		(1 << DSIM_BYTE_CLKEN_SHIFT)
+#define DSIM_BYTE_CLK_DISABLE		(0 << DSIM_BYTE_CLKEN_SHIFT)
+#define DSIM_BYTE_CLKSRC(x)		(((x) & 0x3) << DSIM_BYTE_CLK_SRC_SHIFT)
+#define DSIM_PLL_BYPASS_PLL		(0 << DSIM_PLL_BYPASS_SHIFT)
+#define DSIM_PLL_BYPASS_EXTERNAL	(1 << DSIM_PLL_BYPASS_SHIFT)
+#define DSIM_ESC_CLKEN_ENABLE		(1 << DSIM_ESC_CLKEN_SHIFT)
+#define DSIM_ESC_CLKEN_DISABLE		(0 << DSIM_ESC_CLKEN_SHIFT)
+
+/* S5P_DSIM_CONFIG */
+#define DSIM_LANE_EN_SHIFT		(0)
+#define DSIM_NUM_OF_DATALANE_SHIFT	(5)
+#define DSIM_SUB_PIX_FORMAT_SHIFT	(8)
+#define DSIM_MAIN_PIX_FORMAT_SHIFT	(12)
+#define DSIM_SUB_VC_SHIFT		(16)
+#define DSIM_MAIN_VC_SHIFT		(18)
+#define DSIM_HSA_MODE_SHIFT		(20)
+#define DSIM_HBP_MODE_SHIFT		(21)
+#define DSIM_HFP_MODE_SHIFT		(22)
+#define DSIM_HSE_MODE_SHIFT		(23)
+#define DSIM_AUTO_MODE_SHIFT		(24)
+#define DSIM_VIDEO_MODE_SHIFT		(25)
+#define DSIM_BURST_MODE_SHIFT		(26)
+#define DSIM_SYNC_INFORM_SHIFT		(27)
+#define DSIM_EOT_R03_SHIFT		(28)
+#define DSIM_LANE_ENx(x)		((1) << x)
+
+/* in case of Gemunus, it should be 0x1. */
+#define DSIM_NUM_OF_DATA_LANE(x)	((x) << 5)
+#define DSIM_SUB_PIX_FORMAT_3BPP	(0 << 8)	/* command mode only */
+#define DSIM_SUB_PIX_FORMAT_8BPP	(1 << 8)	/* command mode only */
+#define DSIM_SUB_PIX_FORMAT_12BPP	(2 << 8)	/* command mode only */
+#define DSIM_SUB_PIX_FORMAT_16BPP	(3 << 8)	/* command mode only */
+#define DSIM_SUB_PIX_FORMAT_16BPP_RGB	(4 << 8)	/* video mode only */
+#define DSIM_SUB_PIX_FORMAT_18BPP_PRGB	(5 << 8)	/* video mode only */
+#define DSIM_SUB_PIX_FORMAT_18BPP_LRGB	(6 << 8)	/* common */
+#define DSIM_SUB_PIX_FORMAT_24BPP_RGB	(7 << 8)	/* common */
+#define DSIM_MAIN_PIX_FORMAT_3BPP	(0 << 12)	/* command mode only */
+#define DSIM_MAIN_PIX_FORMAT_8BPP	(1 << 12)	/* command mode only */
+#define DSIM_MAIN_PIX_FORMAT_12BPP	(2 << 12)	/* command mode only */
+#define DSIM_MAIN_PIX_FORMAT_16BPP	(3 << 12)	/* command mode only */
+#define DSIM_MAIN_PIX_FORMAT_16BPP_RGB	(4 << 12)	/* video mode only */
+#define DSIM_MAIN_PIX_FORMAT_18BPP_PRGB	(5 << 12)	/* video mode only */
+#define DSIM_MAIN_PIX_FORMAT_18BPP_LRGB	(6 << 12)	/* common */
+#define DSIM_MAIN_PIX_FORMAT_24BPP_RGB	(7 << 12)	/* common */
+
+/* Virtual channel number for sub display */
+#define DSIM_SUB_VC(x)			(((x) & 0x3) << 16)
+/* Virtual channel number for main display */
+#define DSIM_MAIN_VC(x)			(((x) & 0x3) << 18)
+#define DSIM_HSA_MODE_ENABLE		(1 << 20)
+#define DSIM_HSA_MODE_DISABLE		(0 << 20)
+#define DSIM_HBP_MODE_ENABLE		(1 << 21)
+#define DSIM_HBP_MODE_DISABLE		(0 << 21)
+#define DSIM_HFP_MODE_ENABLE		(1 << 22)
+#define DSIM_HFP_MODE_DISABLE		(0 << 22)
+#define DSIM_HSE_MODE_ENABLE		(1 << 23)
+#define DSIM_HSE_MODE_DISABLE		(0 << 23)
+#define DSIM_AUTO_MODE			(1 << 24)
+#define DSIM_CONFIGURATION_MODE		(0 << 24)
+#define DSIM_VIDEO_MODE			(1 << 25)
+#define DSIM_COMMAND_MODE		(0 << 25)
+#define DSIM_BURST_MODE			(1 << 26)
+#define DSIM_NON_BURST_MODE		(0 << 26)
+#define DSIM_SYNC_INFORM_PULSE		(1 << 27)
+#define DSIM_SYNC_INFORM_EVENT		(0 << 27)
+/* enable EoT packet generation for V1.01r11 */
+#define DSIM_EOT_R03_ENABLE		(0 << 28)
+/* disable EoT packet generation for V1.01r03 */
+#define DSIM_EOT_R03_DISABLE		(1 << 28)
+
+/* S5P_DSIM_ESCMODE */
+#define DSIM_STOP_STATE_CNT_SHIFT	(21)
+#define DSIM_STOP_STATE_CNT(x)		(((x) & 0x3ff) << \
+						DSIM_STOP_STATE_CNT_SHIFT)
+#define DSIM_FORCE_STOP_STATE_SHIFT	(20)
+#define DSIM_FORCE_BTA_SHIFT		(16)
+#define DSIM_CMD_LPDT_HS_MODE		(0 << 7)
+#define DSIM_CMD_LPDT_LP_MODE		(1 << 7)
+#define DSIM_TX_LPDT_HS_MODE		(0 << 6)
+#define DSIM_TX_LPDT_LP_MODE		(1 << 6)
+#define DSIM_TX_TRIGGER_RST_SHIFT	(4)
+#define DSIM_TX_UIPS_DAT_SHIFT		(3)
+#define DSIM_TX_UIPS_EXIT_SHIFT		(2)
+#define DSIM_TX_UIPS_CLK_SHIFT		(1)
+#define DSIM_TX_UIPS_CLK_EXIT_SHIFT	(0)
+
+/* S5P_DSIM_MDRESOL */
+#define DSIM_MAIN_STAND_BY		(1 << 31)
+#define DSIM_MAIN_NOT_READY		(0 << 31)
+#define DSIM_MAIN_VRESOL(x)		(((x) & 0x7ff) << 16)
+#define DSIM_MAIN_HRESOL(x)		(((x) & 0X7ff) << 0)
+
+/* S5P_DSIM_MVPORCH */
+#define DSIM_CMD_ALLOW_SHIFT		(28)
+#define DSIM_STABLE_VFP_SHIFT		(16)
+#define DSIM_MAIN_VBP_SHIFT		(0)
+#define DSIM_CMD_ALLOW_MASK		(0xf << DSIM_CMD_ALLOW_SHIFT)
+#define DSIM_STABLE_VFP_MASK		(0x7ff << DSIM_STABLE_VFP_SHIFT)
+#define DSIM_MAIN_VBP_MASK		(0x7ff << DSIM_MAIN_VBP_SHIFT)
+#define DSIM_CMD_ALLOW(x)		(((x) & 0xf) << DSIM_CMD_ALLOW_SHIFT)
+#define DSIM_STABLE_VFP(x)		(((x) & 0x7ff) << DSIM_STABLE_VFP_SHIFT)
+#define DSIM_MAIN_VBP(x)		(((x) & 0x7ff) << DSIM_MAIN_VBP_SHIFT)
+
+/* S5P_DSIM_MHPORCH */
+#define DSIM_MAIN_HFP_SHIFT		(16)
+#define DSIM_MAIN_HBP_SHIFT		(0)
+#define DSIM_MAIN_HFP_MASK		((0xffff) << DSIM_MAIN_HFP_SHIFT)
+#define DSIM_MAIN_HBP_MASK		((0xffff) << DSIM_MAIN_HBP_SHIFT)
+#define DSIM_MAIN_HFP(x)		(((x) & 0xffff) << DSIM_MAIN_HFP_SHIFT)
+#define DSIM_MAIN_HBP(x)		(((x) & 0xffff) << DSIM_MAIN_HBP_SHIFT)
+
+/* S5P_DSIM_MSYNC */
+#define DSIM_MAIN_VSA_SHIFT		(22)
+#define DSIM_MAIN_HSA_SHIFT		(0)
+#define DSIM_MAIN_VSA_MASK		((0x3ff) << DSIM_MAIN_VSA_SHIFT)
+#define DSIM_MAIN_HSA_MASK		((0xffff) << DSIM_MAIN_HSA_SHIFT)
+#define DSIM_MAIN_VSA(x)		(((x) & 0x3ff) << DSIM_MAIN_VSA_SHIFT)
+#define DSIM_MAIN_HSA(x)		(((x) & 0xffff) << DSIM_MAIN_HSA_SHIFT)
+
+/* S5P_DSIM_SDRESOL */
+#define DSIM_SUB_STANDY_SHIFT		(31)
+#define DSIM_SUB_VRESOL_SHIFT		(16)
+#define DSIM_SUB_HRESOL_SHIFT		(0)
+#define DSIM_SUB_STANDY_MASK		((0x1) << DSIM_SUB_STANDY_SHIFT)
+#define DSIM_SUB_VRESOL_MASK		((0x7ff) << DSIM_SUB_VRESOL_SHIFT)
+#define DSIM_SUB_HRESOL_MASK		((0x7ff) << DSIM_SUB_HRESOL_SHIFT)
+#define DSIM_SUB_STANDY			(1 << DSIM_SUB_STANDY_SHIFT)
+#define DSIM_SUB_NOT_READY		(0 << DSIM_SUB_STANDY_SHIFT)
+#define DSIM_SUB_VRESOL(x)		(((x) & 0x7ff) << DSIM_SUB_VRESOL_SHIFT)
+#define DSIM_SUB_HRESOL(x)		(((x) & 0x7ff) << DSIM_SUB_HRESOL_SHIFT)
+
+/* S5P_DSIM_INTSRC */
+#define INTSRC_ERR_CONTENT_LP1		(1 << 0)
+#define INTSRC_ERR_CONTENT_LP0		(1 << 1)
+#define INTSRC_ERR_CONTROL0		(1 << 2)
+#define INTSRC_ERR_CONTROL1		(1 << 3)
+#define INTSRC_ERR_CONTROL2		(1 << 4)
+#define INTSRC_ERR_CONTROL3		(1 << 5)
+#define INTSRC_ERR_SYNC0		(1 << 6)
+#define INTSRC_ERR_SYNC1		(1 << 7)
+#define INTSRC_ERR_SYNC2		(1 << 8)
+#define INTSRC_ERR_SYNC3		(1 << 9)
+#define INTSRC_ERR_ESC0			(1 << 10)
+#define INTSRC_ERR_ESC1			(1 << 11)
+#define INTSRC_ERR_ESC2			(1 << 12)
+#define INTSRC_ERR_ESC3			(1 << 13)
+#define INTSRC_ERR_RX_CRC		(1 << 14)
+#define INTSRC_ERR_RX_ECC		(1 << 15)
+#define INTSRC_RX_ACK			(1 << 16)
+#define INTSRC_RX_TE			(1 << 17)
+#define INTSRC_RX_DAT_DONE		(1 << 18)
+#define INTSRC_TA_TOUT			(1 << 20)
+#define INTSRC_LPDR_TOUT		(1 << 21)
+#define INTSRC_FRAME_DONE		(1 << 24)
+#define INTSRC_BUS_TURN_OVER		(1 << 25)
+#define INTSRC_SYNC_OVERRIDE		(1 << 28)
+#define INTSRC_SFR_FIFO_EMPTY		(1 << 29)
+#define INTSRC_SW_RST_RELEASE		(1 << 30)
+#define INTSRC_PLL_STABLE		(1 << 31)
+
+/* S5P_DSIM_INTMSK */
+#define INTMSK_ERR_CONTENT_LP1		(1 << 0)
+#define INTMSK_ERR_CONTENT_LP0		(1 << 1)
+#define INTMSK_ERR_CONTROL0		(1 << 2)
+#define INTMSK_ERR_CONTROL1		(1 << 3)
+#define INTMSK_ERR_CONTROL2		(1 << 4)
+#define INTMSK_ERR_CONTROL3		(1 << 5)
+#define INTMSK_ERR_SYNC0		(1 << 6)
+#define INTMSK_ERR_SYNC1		(1 << 7)
+#define INTMSK_ERR_SYNC2		(1 << 8)
+#define INTMSK_ERR_SYNC3		(1 << 9)
+#define INTMSK_ERR_ESC0			(1 << 10)
+#define INTMSK_ERR_ESC1			(1 << 11)
+#define INTMSK_ERR_ESC2			(1 << 12)
+#define INTMSK_ERR_ESC3			(1 << 13)
+#define INTMSK_ERR_RX_CRC		(1 << 14)
+#define INTMSK_ERR_RX_ECC		(1 << 15)
+#define INTMSK_RX_ACK			(1 << 16)
+#define INTMSK_RX_TE			(1 << 17)
+#define INTMSK_RX_DAT_DONE		(1 << 18)
+#define INTMSK_TA_TOUT			(1 << 20)
+#define INTMSK_LPDR_TOUT		(1 << 21)
+#define INTMSK_FRAME_DONE		(1 << 24)
+#define INTMSK_BUS_TURN_OVER		(1 << 25)
+#define INTMSK_SFR_FIFO_EMPTY		(1 << 29)
+#define INTMSK_SW_RST_RELEASE		(1 << 30)
+#define INTMSK_PLL_STABLE		(1 << 31)
+
+/* S5P_DSIM_PKTHDR */
+#define DSIM_PACKET_HEADER_DI(x)	(((x) & 0xff) << 0)
+/* Word count lower byte for long packet */
+#define DSIM_PACKET_HEADER_DAT0(x)	(((x) & 0xff) << 8)
+/* Word count upper byte for long packet */
+#define DSIM_PACKET_HEADER_DAT1(x)	(((x) & 0xff) << 16)
+
+/* S5P_DSIM_FIFOCTRL */
+#define DSIM_RX_FIFO			(1 << 4)
+#define DSIM_TX_SFR_FIFO		(1 << 3)
+#define DSIM_I80_FIFO			(1 << 2)
+#define DSIM_SUB_DISP_FIFO		(1 << 1)
+#define DSIM_MAIN_DISP_FIFO		(1 << 0)
+
+/* S5P_DSIM_PHYACCHR */
+#define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
+#define DSIM_AFC_ENABLE			(1 << 14)
+#define DSIM_AFC_DISABLE		(0 << 14)
+
+/* S5P_DSIM_PLLCTRL */
+#define DSIM_PMS_SHIFT			(1)
+#define DSIM_PLL_EN_SHIFT		(23)
+#define DSIM_FREQ_BAND_SHIFT		(24)
+#define DSIM_PMS(x)			(((x) & 0x7ffff) << DSIM_PMS_SHIFT)
+#define DSIM_FREQ_BAND(x)		(((x) & 0xf) << DSIM_FREQ_BAND_SHIFT)
+
+#endif /* _REGS_DSIM_H */
diff --git a/arch/arm/plat-samsung/setup-dsim.c b/arch/arm/plat-samsung/setup-dsim.c
new file mode 100644
index 0000000..833ade2
--- /dev/null
+++ b/arch/arm/plat-samsung/setup-dsim.c
@@ -0,0 +1,161 @@
+/*
+ * S5PC110 MIPI-DSIM driver.
+ *
+ * Author: InKi Dae <inki.dae at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/regulator/consumer.h>
+
+#include <mach/map.h>
+#include <mach/regs-clock.h>
+
+#include <plat/dsim.h>
+#include <plat/clock.h>
+#include <plat/regs-dsim.h>
+
+static int s5p_dsim_enable_d_phy(struct dsim_global *dsim, unsigned int enable)
+{
+	unsigned int reg;
+
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim is NULL.\n");
+		return -EFAULT;
+	}
+
+	reg = (readl(S5P_MIPI_CONTROL)) & ~(1 << 0);
+	reg |= (enable << 0);
+	writel(reg, S5P_MIPI_CONTROL);
+
+	dev_dbg(dsim->dev, "%s : %x\n", __func__, reg);
+
+	return 0;
+}
+
+static int s5p_dsim_enable_dsi_master(struct dsim_global *dsim,
+	unsigned int enable)
+{
+	unsigned int reg;
+
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim is NULL.\n");
+		return -EFAULT;
+	}
+
+	reg = (readl(S5P_MIPI_CONTROL)) & ~(1 << 2);
+	reg |= (enable << 2);
+	writel(reg, S5P_MIPI_CONTROL);
+
+	dev_dbg(dsim->dev, "%s : %x\n", __func__, reg);
+
+	return 0;
+}
+
+int s5p_dsim_part_reset(struct dsim_global *dsim)
+{
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim is NULL.\n");
+		return -EFAULT;
+	}
+
+	writel(S5P_MIPI_M_RESETN, S5P_MIPI_PHY_CON0);
+
+	dev_dbg(dsim->dev, "%s\n", __func__);
+
+	return 0;
+}
+
+int s5p_dsim_init_d_phy(struct dsim_global *dsim)
+{
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim is NULL.\n");
+		return -EFAULT;
+	}
+
+	/* enable D-PHY */
+	s5p_dsim_enable_d_phy(dsim, 1);
+
+	/* enable DSI master block */
+	s5p_dsim_enable_dsi_master(dsim, 1);
+
+	dev_dbg(dsim->dev, "%s\n", __func__);
+
+	return 0;
+}
+
+int s5p_dsim_mipi_power(struct dsim_global *dsim, void *p_mipi_1_1v,
+	void *p_mipi_1_8v, int enable)
+{
+	struct regulator *r_mipi_1_1v = NULL, *r_mipi_1_8v = NULL;
+	int ret = -1;
+
+	r_mipi_1_1v = (struct regulator *) p_mipi_1_1v;
+	r_mipi_1_8v = (struct regulator *) p_mipi_1_8v;
+
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim is NULL.\n");
+		return -EFAULT;
+	}
+
+	if (IS_ERR(r_mipi_1_1v) || IS_ERR(r_mipi_1_8v)) {
+		dev_err(dsim->dev, "r_mipi_1_1v or r_mipi_1_8v is NULL.\n");
+		return -EINVAL;
+	}
+
+	if (enable) {
+		if (r_mipi_1_1v)
+			ret = regulator_enable(r_mipi_1_1v);
+
+		if (ret < 0) {
+			dev_err(dsim->dev,
+				"failed to enable regulator mipi_1_1v.\n");
+			return ret;
+		}
+
+		if (r_mipi_1_8v)
+			ret = regulator_enable(r_mipi_1_8v);
+
+		if (ret < 0) {
+			dev_err(dsim->dev,
+				"failed to enable regulator mipi_1_8v.\n");
+			return ret;
+		}
+	} else {
+		if (r_mipi_1_1v)
+			ret = regulator_force_disable(r_mipi_1_1v);
+		if (ret < 0) {
+			dev_err(dsim->dev,
+				"failed to disable regulator mipi_1_1v.\n");
+			return ret;
+		}
+
+		if (r_mipi_1_8v)
+			ret = regulator_force_disable(r_mipi_1_8v);
+		if (ret < 0) {
+			dev_err(dsim->dev,
+				"failed to disable regulator mipi_1_8v.\n");
+			return ret;
+		}
+	}
+
+	return ret;
+}
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 3d94a14..c916ac1 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -1930,7 +1930,7 @@ config FB_TMIO_ACCELL
 
 config FB_S3C
 	tristate "Samsung S3C framebuffer support"
-	depends on FB && ARCH_S3C64XX
+	depends on FB && (ARCH_S3C64XX || ARCH_S5PV210)
 	select FB_CFB_FILLRECT
 	select FB_CFB_COPYAREA
 	select FB_CFB_IMAGEBLIT
@@ -1975,6 +1975,13 @@ config FB_S3C2410_DEBUG
 	  Turn on debugging messages. Note that you can set/unset at run time
 	  through sysfs
 
+config S5P_MIPI_DSI
+	tristate "Samsung SoC MIPI-DSI support."
+	depends on FB_S3C && ARCH_S5PV210
+	default n
+	---help---
+	  This enables support for MIPI-DSI device.
+
 config FB_NUC900
         bool "NUC900 LCD framebuffer support"
         depends on FB && ARCH_W90X900
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index ddc2af2..d841433 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -115,6 +115,8 @@ obj-$(CONFIG_FB_SH7760)		  += sh7760fb.o
 obj-$(CONFIG_FB_IMX)              += imxfb.o
 obj-$(CONFIG_FB_S3C)		  += s3c-fb.o
 obj-$(CONFIG_FB_S3C2410)	  += s3c2410fb.o
+obj-$(CONFIG_S5P_MIPI_DSI)	  += s5p-dsim.o s5p_dsim_common.o \
+    					s5p_dsim_lowlevel.o
 obj-$(CONFIG_FB_FSL_DIU)	  += fsl-diu-fb.o
 obj-$(CONFIG_FB_COBALT)           += cobalt_lcdfb.o
 obj-$(CONFIG_FB_PNX4008_DUM)	  += pnx4008/
diff --git a/drivers/video/s5p-dsim.c b/drivers/video/s5p-dsim.c
new file mode 100644
index 0000000..96893bc
--- /dev/null
+++ b/drivers/video/s5p-dsim.c
@@ -0,0 +1,483 @@
+/* linux/drivers/video/samsung/s5p-dsim.c
+ *
+ * Samsung MIPI-DSIM driver.
+ *
+ * InKi Dae, <inki.dae at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/wait.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/fb.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/memory.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/kthread.h>
+#include <linux/regulator/consumer.h>
+#include <linux/notifier.h>
+
+#include <plat/fb.h>
+#include <plat/regs-dsim.h>
+#include <plat/dsim.h>
+#include <plat/mipi_ddi.h>
+
+#include <mach/map.h>
+
+#include "s5p_dsim_common.h"
+
+struct mipi_lcd_info {
+	struct list_head	list;
+	struct mipi_lcd_driver	*mipi_drv;
+};
+
+static LIST_HEAD(lcd_info_list);
+static DEFINE_MUTEX(mipi_lock);
+
+struct dsim_global dsim;
+
+struct s5p_platform_dsim *to_dsim_plat(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+
+	return (struct s5p_platform_dsim *)pdev->dev.platform_data;
+}
+
+/*
+ * notifier callback function for fb_blank
+ * - this function would be called by device specific fb_blank.
+ */
+static int s5p_dsim_notifier_callback(struct notifier_block *self,
+	unsigned long event, void *data)
+{
+	pm_message_t pm;
+
+	pm.event = 0;
+
+	switch (event) {
+	case FB_BLANK_UNBLANK:
+	case FB_BLANK_NORMAL:
+		if (dsim.pd->mipi_power)
+			dsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v,
+				(void *) dsim.r_mipi_1_8v, 1);
+
+		clk_enable(dsim.clock);
+
+		if (dsim.mipi_drv->resume)
+			dsim.mipi_drv->resume(dsim.dev);
+
+		s5p_dsim_init_dsim(&dsim);
+		s5p_dsim_init_link(&dsim);
+
+		s5p_dsim_set_hs_enable(&dsim);
+		s5p_dsim_set_data_transfer_mode(&dsim,
+			DSIM_TRANSFER_BYCPU, 1);
+
+		/* it needs delay for stabilization */
+		mdelay(dsim.pd->delay_for_stabilization);
+
+		if (dsim.mipi_drv->init)
+			dsim.mipi_drv->init(dsim.dev);
+		else
+			dev_warn(dsim.dev, "init func is null.\n");
+
+		s5p_dsim_set_display_mode(&dsim, dsim.dsim_lcd_info, NULL);
+
+		s5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYLCDC, 1);
+		dsim.mipi_ddi_pd->resume_complete = 1;
+
+		dev_dbg(dsim.dev, "FB_BLANK_NORMAL or UNBLANK.\n");
+
+		break;
+	case FB_BLANK_POWERDOWN:
+		dsim.mipi_ddi_pd->resume_complete = 0;
+
+		if (dsim.mipi_drv->suspend)
+			dsim.mipi_drv->suspend(dsim.dev, pm);
+
+		clk_disable(dsim.clock);
+
+		if (dsim.pd->mipi_power)
+			dsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v,
+				(void *) dsim.r_mipi_1_8v, 0);
+
+		dev_dbg(dsim.dev, "FB_BLANK_POWERDOWN.\n");
+		break;
+	default:
+		dev_warn(dsim.dev, "unknown FB_BLANK command.\n");
+		break;
+	}
+
+	return 0;
+}
+
+static int s5p_dsim_register_notif(struct device *dev)
+{
+	memset(&dsim.s3cfb_notif, 0, sizeof(struct notifier_block));
+	dsim.s3cfb_notif.notifier_call = s5p_dsim_notifier_callback;
+
+	return 0/*s3cfb_register_client(&dsim.s3cfb_notif)*/;
+}
+
+static irqreturn_t s5p_dsim_interrupt_handler(int irq, void *dev_id)
+{
+	disable_irq(irq);
+
+	/* additional work. */
+
+	enable_irq(irq);
+
+	return IRQ_HANDLED;
+}
+
+int s5p_dsim_register_lcd_driver(struct mipi_lcd_driver *lcd_drv)
+{
+	struct mipi_lcd_info	*lcd_info = NULL;
+
+	lcd_info = kmalloc(sizeof(struct mipi_lcd_info), GFP_KERNEL);
+	if (lcd_info == NULL)
+		return -ENOMEM;
+
+	lcd_info->mipi_drv = kmalloc(sizeof(struct mipi_lcd_driver),
+		GFP_KERNEL);
+	if (lcd_info->mipi_drv == NULL)
+		return -ENOMEM;
+
+
+	memcpy(lcd_info->mipi_drv, lcd_drv, sizeof(struct mipi_lcd_driver));
+
+	mutex_lock(&mipi_lock);
+	list_add_tail(&lcd_info->list, &lcd_info_list);
+	mutex_unlock(&mipi_lock);
+
+	dev_dbg(dsim.dev, "registered panel driver(%s) to mipi-dsi driver.\n",
+		lcd_drv->name);
+
+	return 0;
+}
+
+/*
+ * This function is wrapper for changing transfer mode.
+ * It is used to in panel driver before and after changing gamma value.
+ */
+static int s5p_dsim_change_transfer_mode(int mode)
+{
+	if (mode < 0 || mode > 1) {
+		dev_err(dsim.dev, "mode range should be 0 or 1.\n");
+		return -EFAULT;
+	}
+
+	if (mode == 0)
+		s5p_dsim_set_data_transfer_mode(&dsim,
+			DSIM_TRANSFER_BYCPU, mode);
+	else
+		s5p_dsim_set_data_transfer_mode(&dsim,
+			DSIM_TRANSFER_BYLCDC, mode);
+
+	return 0;
+}
+
+struct mipi_lcd_driver *scan_mipi_driver(const char *name)
+{
+	struct mipi_lcd_info *lcd_info;
+	struct mipi_lcd_driver *mipi_drv = NULL;
+
+	mutex_lock(&mipi_lock);
+
+	dev_dbg(dsim.dev, "find lcd panel driver(%s).\n",
+		name);
+
+	list_for_each_entry(lcd_info, &lcd_info_list, list) {
+		mipi_drv = lcd_info->mipi_drv;
+
+		if ((strcmp(mipi_drv->name, name)) == 0) {
+			mutex_unlock(&mipi_lock);
+			dev_dbg(dsim.dev, "found!!!(%s).\n", mipi_drv->name);
+			return mipi_drv;
+		}
+	}
+
+	dev_warn(dsim.dev, "failed to find lcd panel driver(%s).\n",
+		name);
+
+	mutex_unlock(&mipi_lock);
+
+	return NULL;
+}
+
+static int s5p_dsim_probe(struct platform_device *pdev)
+{
+	struct resource *res;
+	int ret = -1;
+
+	dsim.pd = to_dsim_plat(&pdev->dev);
+	dsim.dev = &pdev->dev;
+
+	/* set dsim config data, dsim lcd config data and lcd panel data. */
+	dsim.dsim_info = dsim.pd->dsim_info;
+	dsim.dsim_lcd_info = dsim.pd->dsim_lcd_info;
+	dsim.lcd_panel_info =
+		(struct fb_videomode *) dsim.dsim_lcd_info->lcd_panel_info;
+	dsim.mipi_ddi_pd =
+		(struct mipi_ddi_platform_data *)
+			dsim.dsim_lcd_info->mipi_ddi_pd;
+
+	dsim.mipi_ddi_pd->resume_complete = 0;
+
+	dsim.r_mipi_1_1v = regulator_get(&pdev->dev, "VMIPI_1.1V");
+	if (IS_ERR(dsim.r_mipi_1_1v)) {
+		dev_err(&pdev->dev, "failed to get regulator VMIPI_1.1V.\n");
+		goto regulator_get_err;
+	}
+
+	dsim.r_mipi_1_8v = regulator_get(&pdev->dev, "VMIPI_1.8V");
+	if (IS_ERR(dsim.r_mipi_1_8v)) {
+		dev_err(&pdev->dev, "failed to get regulator VMIPI_1.8V.\n");
+		goto regulator_get_err;
+	}
+
+	/* clock */
+	dsim.clock = clk_get(&pdev->dev, dsim.pd->clk_name);
+	if (IS_ERR(dsim.clock)) {
+		dev_err(&pdev->dev, "failed to get dsim clock source\n");
+		return -EINVAL;
+	}
+
+	clk_enable(dsim.clock);
+
+	/* io memory */
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to get io memory region\n");
+		ret = -EINVAL;
+		goto err_clk_disable;
+	}
+
+	/* request mem region */
+	res = request_mem_region(res->start,
+				 res->end - res->start + 1, pdev->name);
+	if (!res) {
+		dev_err(&pdev->dev, "failed to request io memory region\n");
+		ret = -EINVAL;
+		goto err_clk_disable;
+	}
+
+	/* ioremap for register block */
+	dsim.reg_base = (unsigned int) ioremap(res->start,
+		res->end - res->start + 1);
+	if (!dsim.reg_base) {
+		dev_err(&pdev->dev, "failed to remap io region\n");
+		ret = -EINVAL;
+		goto err_clk_disable;
+	}
+
+	/* it is used for MIPI-DSI based lcd panel driver. */
+	dsim.mipi_ddi_pd->dsim_data = (void *)&dsim;
+
+	/*
+	 * it uses frame done interrupt handler
+	 * only in case of MIPI Video mode.
+	 */
+	if (dsim.dsim_lcd_info->e_interface == DSIM_VIDEO) {
+		dsim.irq = platform_get_irq(pdev, 0);
+		if (request_irq(dsim.irq, s5p_dsim_interrupt_handler,
+				IRQF_TRIGGER_RISING, "mipi-dsi", &dsim)) {
+			dev_err(&pdev->dev, "request_irq failed.\n");
+			goto err_trigger_irq;
+		}
+	}
+
+	if (dsim.pd->mipi_power)
+		dsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v,
+			(void *) dsim.r_mipi_1_8v, 1);
+	else {
+		dev_err(&pdev->dev, "mipi_power is NULL.\n");
+		goto mipi_power_err;
+	}
+
+	/* find lcd panel driver registered to mipi-dsi driver. */
+	dsim.mipi_drv = scan_mipi_driver(dsim.pd->lcd_panel_name);
+	if (dsim.mipi_drv == NULL) {
+		dev_err(&pdev->dev, "mipi_drv is NULL.\n");
+		goto mipi_drv_err;
+	}
+
+	/* register callback functions that lcd panel driver needs. */
+	dsim.mipi_ddi_pd->cmd_write = s5p_dsim_wr_data;
+	dsim.mipi_ddi_pd->cmd_read = NULL;
+	dsim.mipi_ddi_pd->get_dsim_frame_done =
+		s5p_dsim_get_frame_done_status;
+	dsim.mipi_ddi_pd->clear_dsim_frame_done = s5p_dsim_clear_frame_done;
+	dsim.mipi_ddi_pd->change_dsim_transfer_mode =
+		s5p_dsim_change_transfer_mode;
+	dsim.mipi_ddi_pd->get_fb_frame_done = dsim.pd->get_fb_frame_done;
+	dsim.mipi_ddi_pd->trigger = dsim.pd->trigger;
+
+	/* set lcd panel driver link */
+	ret = dsim.mipi_drv->set_link(dsim.mipi_ddi_pd);
+	if (ret < 0) {
+		dev_err(&pdev->dev, "failed to set link.\n");
+		goto mipi_drv_err;
+	}
+
+	dsim.mipi_drv->probe(&pdev->dev);
+
+	s5p_dsim_init_dsim(&dsim);
+	s5p_dsim_init_link(&dsim);
+
+	s5p_dsim_set_hs_enable(&dsim);
+	s5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYCPU, 1);
+
+	/* it needs delay for stabilization */
+	mdelay(dsim.pd->delay_for_stabilization);
+
+	/* initialize lcd panel */
+	if (dsim.mipi_drv->init)
+		dsim.mipi_drv->init(&pdev->dev);
+	else
+		dev_warn(&pdev->dev, "init func is null.\n");
+
+	if (dsim.mipi_drv->display_on)
+		dsim.mipi_drv->display_on(&pdev->dev);
+	else
+		dev_warn(&pdev->dev, "display_on func is null.\n");
+
+	s5p_dsim_set_display_mode(&dsim, dsim.dsim_lcd_info, NULL);
+
+	s5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYLCDC, 1);
+
+	s5p_dsim_register_notif(&pdev->dev);
+
+	/* in case of command mode, trigger. */
+	if (dsim.dsim_lcd_info->e_interface == DSIM_COMMAND) {
+		if (dsim.pd->trigger)
+			dsim.pd->trigger(registered_fb[0]);
+		else
+			dev_warn(&pdev->dev, "trigger is null.\n");
+	}
+
+	dev_info(&pdev->dev, "mipi-dsi driver(%s mode) has been probed.\n",
+		(dsim.dsim_lcd_info->e_interface == DSIM_COMMAND) ?
+			"CPU" : "RGB");
+
+	return 0;
+
+err_trigger_irq:
+mipi_drv_err:
+	dsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v,
+		(void *) dsim.r_mipi_1_8v, 0);
+
+mipi_power_err:
+	iounmap((void __iomem *) dsim.reg_base);
+
+err_clk_disable:
+	clk_disable(dsim.clock);
+
+regulator_get_err:
+
+	return ret;
+
+}
+
+static int s5p_dsim_remove(struct platform_device *pdev)
+{
+	return 0;
+}
+
+#ifdef CONFIG_PM
+int s5p_dsim_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	dsim.mipi_ddi_pd->resume_complete = 0;
+
+	if (dsim.mipi_drv->suspend)
+		dsim.mipi_drv->suspend(&pdev->dev, state);
+
+	clk_disable(dsim.clock);
+
+	if (dsim.pd->mipi_power)
+		dsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v,
+			(void *) dsim.r_mipi_1_8v, 0);
+
+	return 0;
+}
+
+int s5p_dsim_resume(struct platform_device *pdev)
+{
+	if (dsim.pd->mipi_power)
+		dsim.pd->mipi_power(&dsim, (void *) dsim.r_mipi_1_1v,
+			(void *) dsim.r_mipi_1_8v, 1);
+
+	clk_enable(dsim.clock);
+
+	if (dsim.mipi_drv->resume)
+		dsim.mipi_drv->resume(&pdev->dev);
+
+	s5p_dsim_init_dsim(&dsim);
+	s5p_dsim_init_link(&dsim);
+
+	s5p_dsim_set_hs_enable(&dsim);
+	s5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYCPU, 1);
+
+	/* it needs delay for stabilization */
+	mdelay(dsim.pd->delay_for_stabilization);
+
+	/* initialize lcd panel */
+	if (dsim.mipi_drv->init)
+		dsim.mipi_drv->init(&pdev->dev);
+	else
+		dev_warn(&pdev->dev, "init func is null.\n");
+
+	s5p_dsim_set_display_mode(&dsim, dsim.dsim_lcd_info, NULL);
+
+	s5p_dsim_set_data_transfer_mode(&dsim, DSIM_TRANSFER_BYLCDC, 1);
+
+	dsim.mipi_ddi_pd->resume_complete = 1;
+
+	return 0;
+}
+#else
+#define s5p_dsim_suspend NULL
+#define s5p_dsim_resume NULL
+#endif
+
+static struct platform_driver s5p_dsim_driver = {
+	.probe = s5p_dsim_probe,
+	.remove = s5p_dsim_remove,
+	.suspend = s5p_dsim_suspend,
+	.resume = s5p_dsim_resume,
+	.driver = {
+		   .name = "s5p-dsim",
+		   .owner = THIS_MODULE,
+	},
+};
+
+static int s5p_dsim_register(void)
+{
+	platform_driver_register(&s5p_dsim_driver);
+
+	return 0;
+}
+
+static void s5p_dsim_unregister(void)
+{
+	platform_driver_unregister(&s5p_dsim_driver);
+}
+
+module_init(s5p_dsim_register);
+module_exit(s5p_dsim_unregister);
+
+MODULE_AUTHOR("InKi Dae <inki.dae at samsung.com>");
+MODULE_DESCRIPTION("Samusung MIPI-DSIM driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/s5p_dsim_common.c b/drivers/video/s5p_dsim_common.c
new file mode 100644
index 0000000..4d70e2c
--- /dev/null
+++ b/drivers/video/s5p_dsim_common.c
@@ -0,0 +1,754 @@
+/* linux/drivers/video/samsung/s5p_dsim_common.c
+ *
+ * Samsung MIPI-DSIM common driver.
+ *
+ * InKi Dae, <inki.dae at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+#include <linux/wait.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/fb.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/memory.h>
+#include <linux/delay.h>
+#include <linux/kthread.h>
+
+#include <plat/fb.h>
+#include <plat/regs-dsim.h>
+
+#include <mach/map.h>
+#include <plat/dsim.h>
+#include <plat/mipi_ddi.h>
+
+#include "s5p_dsim_lowlevel.h"
+
+static void s5p_dsim_long_data_wr(struct dsim_global *dsim, unsigned int data0,
+	unsigned int data1)
+{
+	unsigned int data_cnt = 0, payload = 0;
+
+	/* in case that data count is more then 4 */
+	for (data_cnt = 0; data_cnt < data1; data_cnt += 4) {
+		/*
+		 * after sending 4bytes per one time,
+		 * send remainder data less then 4.
+		 */
+		if ((data1 - data_cnt) < 4) {
+			if ((data1 - data_cnt) == 3) {
+				payload = *(u8 *)(data0 + data_cnt) |
+				    (*(u8 *)(data0 + (data_cnt + 1))) << 8 |
+					(*(u8 *)(data0 + (data_cnt + 2))) << 16;
+			dev_dbg(dsim->dev, "count = 3 payload = %x, %x %x %x\n",
+				payload, *(u8 *)(data0 + data_cnt),
+				*(u8 *)(data0 + (data_cnt + 1)),
+				*(u8 *)(data0 + (data_cnt + 2)));
+			} else if ((data1 - data_cnt) == 2) {
+				payload = *(u8 *)(data0 + data_cnt) |
+					(*(u8 *)(data0 + (data_cnt + 1))) << 8;
+			dev_dbg(dsim->dev,
+				"count = 2 payload = %x, %x %x\n", payload,
+				*(u8 *)(data0 + data_cnt),
+				*(u8 *)(data0 + (data_cnt + 1)));
+			} else if ((data1 - data_cnt) == 1) {
+				payload = *(u8 *)(data0 + data_cnt);
+			}
+
+			s5p_dsim_wr_tx_data(dsim, payload);
+		/* send 4bytes per one time. */
+		} else {
+			payload = *(u8 *)(data0 + data_cnt) |
+				(*(u8 *)(data0 + (data_cnt + 1))) << 8 |
+				(*(u8 *)(data0 + (data_cnt + 2))) << 16 |
+				(*(u8 *)(data0 + (data_cnt + 3))) << 24;
+
+			dev_dbg(dsim->dev,
+				"count = 4 payload = %x, %x %x %x %x\n",
+				payload, *(u8 *)(data0 + data_cnt),
+				*(u8 *)(data0 + (data_cnt + 1)),
+				*(u8 *)(data0 + (data_cnt + 2)),
+				*(u8 *)(data0 + (data_cnt + 3)));
+
+			s5p_dsim_wr_tx_data(dsim, payload);
+		}
+	}
+}
+
+int s5p_dsim_wr_data(void *dsim_data, unsigned int data_id,
+	unsigned int data0, unsigned int data1)
+{
+	struct dsim_global *dsim = NULL;
+	unsigned int timeout = 5000 * 2;
+	unsigned long delay_val, udelay;
+	unsigned char check_rx_ack = 0;
+
+	dsim = (struct dsim_global *)dsim_data;
+
+	if (dsim == NULL) {
+		dev_err(dsim->dev, "dsim_data is NULL.\n");
+		return -EFAULT;
+	}
+
+
+	if (dsim->state == DSIM_STATE_ULPS) {
+		dev_err(dsim->dev, "state is ULPS.\n");
+
+		return -EINVAL;
+	}
+
+	delay_val = 1000000 / dsim->dsim_info->esc_clk;
+	udelay = 10 * delay_val;
+
+	mdelay(udelay);
+
+	/* only if transfer mode is LPDT, wait SFR becomes empty. */
+	if (dsim->state == DSIM_STATE_STOP) {
+		while (!(s5p_dsim_get_fifo_state(dsim) &
+				SFR_HEADER_EMPTY)) {
+			if ((timeout--) > 0)
+				mdelay(1);
+			else {
+				dev_err(dsim->dev,
+					"SRF header fifo is not empty.\n");
+				return -EINVAL;
+			}
+		}
+	}
+
+	switch (data_id) {
+	/* short packet types of packet types for command. */
+	case GEN_SHORT_WR_NO_PARA:
+	case GEN_SHORT_WR_1_PARA:
+	case GEN_SHORT_WR_2_PARA:
+	case DCS_WR_NO_PARA:
+	case DCS_WR_1_PARA:
+	case SET_MAX_RTN_PKT_SIZE:
+		s5p_dsim_wr_tx_header(dsim, (unsigned char) data_id,
+			(unsigned char) data0, (unsigned char) data1);
+		if (check_rx_ack)
+			/* process response func should be implemented */
+			return 0;
+		else
+			return -EINVAL;
+
+	/* general command */
+	case CMD_OFF:
+	case CMD_ON:
+	case SHUT_DOWN:
+	case TURN_ON:
+		s5p_dsim_wr_tx_header(dsim, (unsigned char) data_id,
+			(unsigned char) data0, (unsigned char) data1);
+		if (check_rx_ack)
+			/* process response func should be implemented. */
+			return 0;
+		else
+			return -EINVAL;
+
+	/* packet types for video data */
+	case VSYNC_START:
+	case VSYNC_END:
+	case HSYNC_START:
+	case HSYNC_END:
+	case EOT_PKT:
+		return 0;
+
+	/* short and response packet types for command */
+	case GEN_RD_1_PARA:
+	case GEN_RD_2_PARA:
+	case GEN_RD_NO_PARA:
+	case DCS_RD_NO_PARA:
+		s5p_dsim_clear_interrupt(dsim, 0xffffffff);
+		s5p_dsim_wr_tx_header(dsim, (unsigned char) data_id,
+			(unsigned char) data0, (unsigned char) data1);
+		/* process response func should be implemented. */
+		return 0;
+
+	/* long packet type and null packet */
+	case NULL_PKT:
+	case BLANKING_PKT:
+		return 0;
+	case GEN_LONG_WR:
+	case DCS_LONG_WR:
+	{
+		unsigned int size, data_cnt = 0, payload = 0;
+
+		size = data1 * 4;
+
+		/* if data count is less then 4, then send 3bytes data.  */
+		if (data1 < 4) {
+			payload = *(u8 *)(data0) |
+				*(u8 *)(data0 + 1) << 8 |
+				*(u8 *)(data0 + 2) << 16;
+
+			s5p_dsim_wr_tx_data(dsim, payload);
+
+			dev_dbg(dsim->dev, "count = %d payload = %x,%x %x %x\n",
+				data1, payload,
+				*(u8 *)(data0 + data_cnt),
+				*(u8 *)(data0 + (data_cnt + 1)),
+				*(u8 *)(data0 + (data_cnt + 2)));
+		/* in case that data count is more then 4 */
+		} else
+			s5p_dsim_long_data_wr(dsim, data0, data1);
+
+		/* put data into header fifo */
+		s5p_dsim_wr_tx_header(dsim, (unsigned char) data_id,
+			(unsigned char) (((unsigned short) data1) & 0xff),
+			(unsigned char) ((((unsigned short) data1) & 0xff00) >>
+				8));
+
+	}
+	if (check_rx_ack)
+		/* process response func should be implemented. */
+		return 0;
+	else
+		return -EINVAL;
+
+	/* packet typo for video data */
+	case RGB565_PACKED:
+	case RGB666_PACKED:
+	case RGB666_LOOSLY:
+	case RGB888_PACKED:
+		if (check_rx_ack)
+			/* process response func should be implemented. */
+			return 0;
+		else
+			return -EINVAL;
+	default:
+		dev_warn(dsim->dev,
+			"data id %x is not supported current DSI spec.\n",
+			data_id);
+
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int s5p_dsim_init_header_fifo(struct dsim_global *dsim)
+{
+	unsigned int cnt;
+
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim_global pointer is NULL.\n");
+		return -EFAULT;
+	}
+
+	for (cnt = 0; cnt < DSIM_HEADER_FIFO_SZ; cnt++)
+		dsim->header_fifo_index[cnt] = -1;
+	return 0;
+}
+
+int s5p_dsim_pll_on(struct dsim_global *dsim, unsigned char enable)
+{
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim_global pointer is NULL.\n");
+		return -EFAULT;
+	}
+
+	if (enable) {
+		int sw_timeout = 1000;
+		s5p_dsim_clear_interrupt(dsim, DSIM_PLL_STABLE);
+		s5p_dsim_enable_pll(dsim, 1);
+		while (1) {
+			sw_timeout--;
+			if (s5p_dsim_is_pll_stable(dsim))
+				return 0;
+			if (sw_timeout == 0)
+				return -EINVAL;
+		}
+	} else
+		s5p_dsim_enable_pll(dsim, 0);
+
+	return 0;
+}
+
+unsigned long s5p_dsim_change_pll(struct dsim_global *dsim,
+	unsigned char pre_divider, unsigned short main_divider,
+	unsigned char scaler)
+{
+	unsigned long dfin_pll, dfvco, dpll_out;
+	unsigned char freq_band;
+
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim_global pointer is NULL.\n");
+		return 0;
+	}
+
+	dfin_pll = (MIPI_FIN / pre_divider);
+
+	if (dfin_pll < 6 * 1000 * 1000 || dfin_pll > 12 * 1000 * 1000) {
+		dev_warn(dsim->dev, "warning!!\n");
+		dev_warn(dsim->dev, "fin_pll range is 6MHz ~ 12MHz\n");
+		dev_warn(dsim->dev, "fin_pll of mipi dphy pll is %luMHz\n",
+			(dfin_pll / 1000000));
+
+		s5p_dsim_enable_afc(dsim, 0, 0);
+	} else {
+		if (dfin_pll < 7 * 1000000)
+			s5p_dsim_enable_afc(dsim, 1, 0x1);
+		else if (dfin_pll < 8 * 1000000)
+			s5p_dsim_enable_afc(dsim, 1, 0x0);
+		else if (dfin_pll < 9 * 1000000)
+			s5p_dsim_enable_afc(dsim, 1, 0x3);
+		else if (dfin_pll < 10 * 1000000)
+			s5p_dsim_enable_afc(dsim, 1, 0x2);
+		else if (dfin_pll < 11 * 1000000)
+			s5p_dsim_enable_afc(dsim, 1, 0x5);
+		else
+			s5p_dsim_enable_afc(dsim, 1, 0x4);
+	}
+
+	dfvco = dfin_pll * main_divider;
+	dev_dbg(dsim->dev, "dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",
+		dfvco, dfin_pll, main_divider);
+	if (dfvco < 500000000 || dfvco > 1000000000) {
+		dev_warn(dsim->dev, "Caution!!\n");
+		dev_warn(dsim->dev, "fvco range is 500MHz ~ 1000MHz\n");
+		dev_warn(dsim->dev, "fvco of mipi dphy pll is %luMHz\n",
+			(dfvco / 1000000));
+	}
+
+	dpll_out = dfvco / (1 << scaler);
+	dev_dbg(dsim->dev, "dpll_out = %lu, dfvco = %lu, scaler = %d\n",
+		dpll_out, dfvco, scaler);
+	if (dpll_out < 100 * 1000000)
+		freq_band = 0x0;
+	else if (dpll_out < 120 * 1000000)
+		freq_band = 0x1;
+	else if (dpll_out < 170 * 1000000)
+		freq_band = 0x2;
+	else if (dpll_out < 220 * 1000000)
+		freq_band = 0x3;
+	else if (dpll_out < 270 * 1000000)
+		freq_band = 0x4;
+	else if (dpll_out < 320 * 1000000)
+		freq_band = 0x5;
+	else if (dpll_out < 390 * 1000000)
+		freq_band = 0x6;
+	else if (dpll_out < 450 * 1000000)
+		freq_band = 0x7;
+	else if (dpll_out < 510 * 1000000)
+		freq_band = 0x8;
+	else if (dpll_out < 560 * 1000000)
+		freq_band = 0x9;
+	else if (dpll_out < 640 * 1000000)
+		freq_band = 0xa;
+	else if (dpll_out < 690 * 1000000)
+		freq_band = 0xb;
+	else if (dpll_out < 770 * 1000000)
+		freq_band = 0xc;
+	else if (dpll_out < 870 * 1000000)
+		freq_band = 0xd;
+	else if (dpll_out < 950 * 1000000)
+		freq_band = 0xe;
+	else
+		freq_band = 0xf;
+
+	dev_dbg(dsim->dev, "freq_band = %d\n", freq_band);
+
+	s5p_dsim_pll_freq(dsim, pre_divider, main_divider, scaler);
+
+	{
+	    unsigned char temp0, temp1;
+
+	    temp0 = 0;
+	    s5p_dsim_hs_zero_ctrl(dsim, temp0);
+	    temp1 = 0;
+	    s5p_dsim_prep_ctrl(dsim, temp1);
+	}
+
+	/* Freq Band */
+	s5p_dsim_pll_freq_band(dsim, freq_band);
+
+	/* Stable time */
+	s5p_dsim_pll_stable_time(dsim,
+		dsim->dsim_info->pll_stable_time);
+
+	/* Enable PLL */
+	dev_dbg(dsim->dev, "FOUT of mipi dphy pll is %luMHz\n",
+		(dpll_out / 1000000));
+
+	return dpll_out;
+}
+
+int s5p_dsim_set_clock(struct dsim_global *dsim,
+	unsigned char byte_clk_sel, unsigned char enable)
+{
+	unsigned int esc_div;
+	unsigned long esc_clk_error_rate;
+
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim_global pointer is NULL.\n");
+		return -EINVAL;
+	}
+
+	if (enable) {
+		dsim->e_clk_src = byte_clk_sel;
+
+		/* Escape mode clock and byte clock source */
+		s5p_dsim_set_byte_clock_src(dsim, byte_clk_sel);
+
+		/* DPHY, DSIM Link : D-PHY clock out */
+		if (byte_clk_sel == DSIM_PLL_OUT_DIV8) {
+			dsim->hs_clk = s5p_dsim_change_pll(dsim,
+				dsim->dsim_info->p, dsim->dsim_info->m,
+				dsim->dsim_info->s);
+			if (dsim->hs_clk == 0) {
+				dev_err(dsim->dev,
+					"failed to get hs clock.\n");
+				return -EINVAL;
+			}
+
+			dsim->byte_clk = dsim->hs_clk / 8;
+			s5p_dsim_enable_pll_bypass(dsim, 0);
+			s5p_dsim_pll_on(dsim, 1);
+		/* DPHY : D-PHY clock out, DSIM link : external clock out */
+		} else if (byte_clk_sel == DSIM_EXT_CLK_DIV8)
+			dev_warn(dsim->dev,
+				"this project is not support \
+				external clock source for MIPI DSIM\n");
+		else if (byte_clk_sel == DSIM_EXT_CLK_BYPASS)
+			dev_warn(dsim->dev,
+				"this project is not support \
+				external clock source for MIPI DSIM\n");
+
+		/* escape clock divider */
+		esc_div = dsim->byte_clk / (dsim->dsim_info->esc_clk);
+		dev_dbg(dsim->dev,
+			"esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",
+			esc_div, dsim->byte_clk, dsim->dsim_info->esc_clk);
+		if ((dsim->byte_clk / esc_div) >= 20000000 ||
+			(dsim->byte_clk / esc_div) > dsim->dsim_info->esc_clk)
+			esc_div += 1;
+
+		dsim->escape_clk = dsim->byte_clk / esc_div;
+		dev_dbg(dsim->dev,
+			"escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",
+			dsim->escape_clk, dsim->byte_clk, esc_div);
+
+		/*
+		 * enable escclk on lane
+		 *
+		 * in case of evt0, DSIM_TRUE is enable and
+		 * DSIM_FALSE is enable for evt1.
+		 */
+		if (dsim->pd->platform_rev == 1)
+			s5p_dsim_enable_byte_clock(dsim, DSIM_FALSE);
+		else
+			s5p_dsim_enable_byte_clock(dsim, DSIM_TRUE);
+
+		/* enable byte clk and escape clock */
+		s5p_dsim_set_esc_clk_prs(dsim, 1, esc_div);
+		/* escape clock on lane */
+		s5p_dsim_enable_esc_clk_on_lane(dsim,
+			(DSIM_LANE_CLOCK | dsim->data_lane), 1);
+
+		dev_dbg(dsim->dev, "byte clock is %luMHz\n",
+			(dsim->byte_clk / 1000000));
+		dev_dbg(dsim->dev, "escape clock that user's need is %lu\n",
+			(dsim->dsim_info->esc_clk / 1000000));
+		dev_dbg(dsim->dev, "escape clock divider is %x\n", esc_div);
+		dev_dbg(dsim->dev, "escape clock is %luMHz\n",
+			((dsim->byte_clk / esc_div) / 1000000));
+
+		if ((dsim->byte_clk / esc_div) > dsim->escape_clk) {
+			esc_clk_error_rate = dsim->escape_clk /
+				(dsim->byte_clk / esc_div);
+			dev_warn(dsim->dev, "error rate is %lu over.\n",
+				(esc_clk_error_rate / 100));
+		} else if ((dsim->byte_clk / esc_div) < (dsim->escape_clk)) {
+			esc_clk_error_rate = (dsim->byte_clk / esc_div) /
+				dsim->escape_clk;
+			dev_warn(dsim->dev, "error rate is %lu under.\n",
+				(esc_clk_error_rate / 100));
+		}
+	} else {
+		s5p_dsim_enable_esc_clk_on_lane(dsim,
+			(DSIM_LANE_CLOCK | dsim->data_lane), 0);
+		s5p_dsim_set_esc_clk_prs(dsim, 0, 0);
+
+		/*
+		 * in case of evt0, DSIM_FALSE is disable and
+		 * DSIM_TRUE is disable for evt1.
+		 */
+		if (dsim->pd->platform_rev == 1)
+			s5p_dsim_enable_byte_clock(dsim, DSIM_TRUE);
+		else
+			s5p_dsim_enable_byte_clock(dsim, DSIM_FALSE);
+
+		if (byte_clk_sel == DSIM_PLL_OUT_DIV8)
+			s5p_dsim_pll_on(dsim, 0);
+	}
+
+	return 0;
+}
+
+int s5p_dsim_init_dsim(struct dsim_global *dsim)
+{
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim_global pointer is NULL.\n");
+		return -EFAULT;
+	}
+
+	if (dsim->pd->init_d_phy)
+		dsim->pd->init_d_phy(dsim);
+
+	dsim->state = DSIM_STATE_RESET;
+
+	switch (dsim->dsim_info->e_no_data_lane) {
+	case DSIM_DATA_LANE_1:
+		dsim->data_lane = DSIM_LANE_DATA0;
+		break;
+	case DSIM_DATA_LANE_2:
+		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1;
+		break;
+	case DSIM_DATA_LANE_3:
+		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
+			DSIM_LANE_DATA2;
+		break;
+	case DSIM_DATA_LANE_4:
+		dsim->data_lane = DSIM_LANE_DATA0 | DSIM_LANE_DATA1 |
+			DSIM_LANE_DATA2 | DSIM_LANE_DATA3;
+		break;
+	default:
+		dev_info(dsim->dev, "data lane is invalid.\n");
+		return -EINVAL;
+	};
+
+	s5p_dsim_init_header_fifo(dsim);
+	s5p_dsim_sw_reset(dsim);
+	s5p_dsim_dp_dn_swap(dsim, dsim->dsim_info->e_lane_swap);
+
+	return 0;
+}
+
+int s5p_dsim_enable_frame_done_int(struct dsim_global *dsim, int enable)
+{
+	/* enable only frame done interrupt */
+	s5p_dsim_set_interrupt_mask(dsim, INTMSK_FRAME_DONE, enable);
+
+	return 0;
+}
+
+int s5p_dsim_set_display_mode(struct dsim_global *dsim,
+	struct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd)
+{
+	struct fb_videomode *mlcd_video = NULL;
+	struct fb_cmdmode *mlcd_command = NULL;
+	struct s3c_fb_pd_win *pd;
+	unsigned int width = 0, height = 0;
+
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim_global pointer is NULL.\n");
+		return -EFAULT;
+	}
+
+	pd = (struct s3c_fb_pd_win *)main_lcd->lcd_panel_info;
+
+	/* in case of VIDEO MODE (RGB INTERFACE) */
+	if (dsim->dsim_lcd_info->e_interface == (u32) DSIM_VIDEO) {
+		mlcd_video = (struct fb_videomode *)&pd->win_mode;
+		width = mlcd_video->xres;
+		height = mlcd_video->yres;
+
+		if (dsim->dsim_info->auto_vertical_cnt == DSIM_FALSE) {
+			s5p_dsim_set_main_disp_vporch(dsim,
+				mlcd_video->upper_margin,
+				mlcd_video->lower_margin,
+				mlcd_video->cmd_allow_len);
+			s5p_dsim_set_main_disp_hporch(dsim,
+				mlcd_video->left_margin,
+				mlcd_video->right_margin);
+			s5p_dsim_set_main_disp_sync_area(dsim,
+				mlcd_video->vsync_len,
+				mlcd_video->hsync_len);
+		}
+	} else {	/* in case of COMMAND MODE (CPU or I80 INTERFACE) */
+		mlcd_command = (struct fb_cmdmode *)&pd->cmd_mode;
+		width = mlcd_command->xres;
+		height = mlcd_command->yres;
+	}
+
+	s5p_dsim_set_main_disp_resol(dsim, height, width);
+
+	if (sub_lcd != NULL)
+			dev_warn(dsim->dev, "sub lcd isn't supported yet.\n");
+
+	s5p_dsim_display_config(dsim, dsim->dsim_lcd_info, NULL);
+
+	return 0;
+}
+
+int s5p_dsim_init_link(struct dsim_global *dsim)
+{
+	unsigned int time_out = 100;
+
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim_global pointer is NULL.\n");
+		return -EFAULT;
+	}
+
+	switch (dsim->state) {
+	case DSIM_STATE_RESET:
+		s5p_dsim_sw_reset(dsim);
+	case DSIM_STATE_INIT:
+		s5p_dsim_init_fifo_pointer(dsim, 0x1f);
+
+		/* dsi configuration */
+		s5p_dsim_init_config(dsim, dsim->dsim_lcd_info,
+			NULL, dsim->dsim_info);
+		s5p_dsim_enable_lane(dsim, DSIM_LANE_CLOCK, 1);
+		s5p_dsim_enable_lane(dsim, dsim->data_lane, 1);
+
+		/* set clock configuration */
+		s5p_dsim_set_clock(dsim, dsim->dsim_info->e_byte_clk,
+			1);
+
+		/* check clock and data lane state is stop state */
+		while (!(s5p_dsim_is_lane_state(dsim, DSIM_LANE_CLOCK)
+			    == DSIM_LANE_STATE_STOP) &&
+			!(s5p_dsim_is_lane_state(dsim,
+				dsim->data_lane) == DSIM_LANE_STATE_STOP)) {
+			time_out--;
+			if (time_out == 0) {
+				dev_info(dsim->dev,
+					"DSI Master is not stop state.\n");
+				dev_info(dsim->dev,
+					"Check initialization process\n");
+
+				return -EINVAL;
+			}
+		}
+
+		if (time_out != 0) {
+			dev_info(dsim->dev,
+				"initialization of DSI Master is successful\n");
+			dev_info(dsim->dev, "DSI Master state is stop state\n");
+		}
+
+		dsim->state = DSIM_STATE_STOP;
+
+		/* BTA sequence counters */
+		s5p_dsim_set_stop_state_counter(dsim,
+			dsim->dsim_info->stop_holding_cnt);
+		s5p_dsim_set_bta_timeout(dsim,
+			dsim->dsim_info->bta_timeout);
+		s5p_dsim_set_lpdr_timeout(dsim,
+			dsim->dsim_info->rx_timeout);
+
+		/* default LPDT by both cpu and lcd controller */
+		s5p_dsim_set_data_mode(dsim, DSIM_TRANSFER_BOTH,
+			DSIM_STATE_STOP);
+
+		return 0;
+	default:
+		dev_info(dsim->dev, "DSI Master is already init.\n");
+		return 0;
+	}
+
+	return 0;
+}
+
+int s5p_dsim_set_hs_enable(struct dsim_global *dsim)
+{
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim_global pointer is NULL.\n");
+		return -EFAULT;
+	}
+
+	if (dsim->state == DSIM_STATE_STOP) {
+		if (dsim->e_clk_src != DSIM_EXT_CLK_BYPASS) {
+			dsim->state = DSIM_STATE_HSCLKEN;
+			s5p_dsim_set_data_mode(dsim,
+				DSIM_TRANSFER_BOTH, DSIM_STATE_HSCLKEN);
+			s5p_dsim_enable_hs_clock(dsim, 1);
+
+			return 0;
+		} else
+			dev_warn(dsim->dev,
+				"clock source is external bypass.\n");
+	} else
+		dev_warn(dsim->dev, "DSIM is not stop state.\n");
+
+	return 0;
+}
+
+int s5p_dsim_set_data_transfer_mode(struct dsim_global *dsim,
+	unsigned char data_path, unsigned char hs_enable)
+{
+	int ret = -1;
+
+	if (dsim == NULL) {
+		printk(KERN_ERR "dsim_global pointer is NULL.\n");
+		return -EFAULT;
+	}
+
+	if (hs_enable) {
+		if (dsim->state == DSIM_STATE_HSCLKEN) {
+			s5p_dsim_set_data_mode(dsim, data_path,
+				DSIM_STATE_HSCLKEN);
+			ret = 0;
+		} else {
+			dev_err(dsim->dev, "HS Clock lane is not enabled.\n");
+			ret = -EINVAL;
+		}
+	} else {
+		if (dsim->state == DSIM_STATE_INIT || dsim->state ==
+			DSIM_STATE_ULPS) {
+			dev_err(dsim->dev,
+				"DSI Master is not STOP or HSDT state.\n");
+			ret = -EINVAL;
+		} else {
+			s5p_dsim_set_data_mode(dsim, data_path,
+				DSIM_STATE_STOP);
+			ret = 0;
+		}
+	}
+
+	return ret;
+}
+
+int s5p_dsim_get_frame_done_status(void *dsim_data)
+{
+	struct dsim_global *dsim = NULL;
+
+	dsim = (struct dsim_global *)dsim_data;
+
+	if (dsim == NULL) {
+		dev_err(dsim->dev, "dsim_global pointer is NULL.\n");
+		return -EFAULT;
+	}
+
+	return _s5p_dsim_get_frame_done_status(dsim);
+}
+
+int s5p_dsim_clear_frame_done(void *dsim_data)
+{
+	struct dsim_global *dsim = NULL;
+
+	dsim = (struct dsim_global *)dsim_data;
+
+	if (dsim == NULL) {
+		dev_err(dsim->dev, "dsim_global pointer is NULL.\n");
+		return -EFAULT;
+	}
+
+	_s5p_dsim_clear_frame_done(dsim);
+
+	return 0;
+}
+
+MODULE_AUTHOR("InKi Dae <inki.dae at samsung.com>");
+MODULE_DESCRIPTION("Samusung MIPI-DSIM common driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/s5p_dsim_common.h b/drivers/video/s5p_dsim_common.h
new file mode 100644
index 0000000..deefca1
--- /dev/null
+++ b/drivers/video/s5p_dsim_common.h
@@ -0,0 +1,38 @@
+/* linux/drivers/video/samsung/s5p_dsim_common.h
+ *
+ * Header file for Samsung MIPI-DSI common driver.
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ * InKi Dae <inki.dae at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _S5P_DSIM_COMMON_H
+#define _S5P_DSIM_COMMON_H
+
+extern int s5p_dsim_wr_data(void *dsim_data, unsigned int data_id,
+	unsigned int data0, unsigned int data1);
+extern int s5p_dsim_init_header_fifo(struct dsim_global *dsim);
+extern int s5p_dsim_pll_on(struct dsim_global *dsim, unsigned char enable);
+extern unsigned long s5p_dsim_change_pll(struct dsim_global *dsim,
+	unsigned char pre_divider, unsigned short main_divider,
+	unsigned char scaler);
+extern int s5p_dsim_set_clock(struct dsim_global *dsim,
+	unsigned char byte_clk_sel, unsigned char enable);
+extern int s5p_dsim_init_dsim(struct dsim_global *dsim);
+extern int s5p_dsim_set_display_mode(struct dsim_global *dsim,
+	struct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd);
+extern int s5p_dsim_init_link(struct dsim_global *dsim);
+extern int s5p_dsim_set_hs_enable(struct dsim_global *dsim);
+extern int s5p_dsim_set_data_transfer_mode(struct dsim_global *dsim,
+	unsigned char data_path, unsigned char hs_enable);
+extern int s5p_dsim_get_frame_done_status(void *dsim_data);
+extern int s5p_dsim_clear_frame_done(void *dsim_data);
+extern int s5p_dsim_enable_frame_done_int(struct dsim_global *dsim, int enable);
+
+extern struct fb_info *registered_fb[FB_MAX] __read_mostly;
+
+#endif /* _S5P_DSIM_COMMON_H */
diff --git a/drivers/video/s5p_dsim_lowlevel.c b/drivers/video/s5p_dsim_lowlevel.c
new file mode 100644
index 0000000..6a27395
--- /dev/null
+++ b/drivers/video/s5p_dsim_lowlevel.c
@@ -0,0 +1,562 @@
+/* linux/drivers/video/samsung/s5p-dsim.c
+ *
+ * Samsung MIPI-DSIM lowlevel driver.
+ *
+ * InKi Dae, <inki.dae at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+#include <linux/wait.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/mm.h>
+#include <linux/ctype.h>
+#include <linux/io.h>
+
+#include <mach/map.h>
+
+#include <plat/dsim.h>
+#include <plat/mipi_ddi.h>
+#include <plat/regs-dsim.h>
+
+void s5p_dsim_func_reset(struct dsim_global *dsim)
+{
+	unsigned int cfg = 0;
+
+	cfg = DSIM_FUNCRST;
+
+	writel(cfg, dsim->reg_base + S5P_DSIM_SWRST);
+}
+
+void s5p_dsim_sw_reset(struct dsim_global *dsim)
+{
+	unsigned int cfg = 0;
+
+	cfg = DSIM_SWRST;
+
+	writel(cfg, dsim->reg_base + S5P_DSIM_SWRST);
+}
+
+void s5p_dsim_set_interrupt_mask(struct dsim_global *dsim, unsigned int mode,
+	unsigned int mask)
+{
+	unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTMSK);
+
+	if (mask)
+		reg |= mode;
+	else
+		reg &= ~(mode);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_INTMSK);
+}
+
+void s5p_dsim_init_fifo_pointer(struct dsim_global *dsim, unsigned char cfg)
+{
+	unsigned int reg;
+
+	reg = readl(dsim->reg_base + S5P_DSIM_FIFOCTRL);
+
+	writel(reg & ~(cfg), dsim->reg_base + S5P_DSIM_FIFOCTRL);
+	mdelay(10);
+	reg |= cfg;
+
+	writel(reg, dsim->reg_base + S5P_DSIM_FIFOCTRL);
+}
+
+/*
+ * this function set PLL P, M and S value in D-PHY
+ */
+void s5p_dsim_set_phy_tunning(struct dsim_global *dsim, unsigned int value)
+{
+	writel(DSIM_AFC_CTL(value), dsim->reg_base + S5P_DSIM_PHYACCHR);
+}
+
+void s5p_dsim_set_main_disp_resol(struct dsim_global *dsim,
+	unsigned short vert_resol, unsigned short hori_resol)
+{
+	unsigned int reg;
+
+	/* standby should be set after configuration so set to not ready*/
+	reg = (readl(dsim->reg_base + S5P_DSIM_MDRESOL)) &
+		~(DSIM_MAIN_STAND_BY);
+	writel(reg, dsim->reg_base + S5P_DSIM_MDRESOL);
+
+	reg &= ~(0x7ff << 16) & ~(0x7ff << 0);
+	reg |= DSIM_MAIN_VRESOL(vert_resol) | DSIM_MAIN_HRESOL(hori_resol);
+
+	reg |= DSIM_MAIN_STAND_BY;
+	writel(reg, dsim->reg_base + S5P_DSIM_MDRESOL);
+}
+
+void s5p_dsim_set_main_disp_vporch(struct dsim_global *dsim,
+	unsigned int cmd_allow, unsigned int vfront, unsigned int vback)
+{
+	unsigned int reg;
+
+	reg = (readl(dsim->reg_base + S5P_DSIM_MVPORCH)) &
+		~(DSIM_CMD_ALLOW_MASK) & ~(DSIM_STABLE_VFP_MASK) &
+		~(DSIM_MAIN_VBP_MASK);
+
+	reg |= ((cmd_allow & 0xf) << DSIM_CMD_ALLOW_SHIFT) |
+		((vfront & 0x7ff) << DSIM_STABLE_VFP_SHIFT) |
+		((vback & 0x7ff) << DSIM_MAIN_VBP_SHIFT);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_MVPORCH);
+}
+
+void s5p_dsim_set_main_disp_hporch(struct dsim_global *dsim,
+	unsigned short front, unsigned short back)
+{
+	unsigned int reg;
+
+	reg = (readl(dsim->reg_base + S5P_DSIM_MHPORCH)) &
+		~(DSIM_MAIN_HFP_MASK) & ~(DSIM_MAIN_HBP_MASK);
+
+	reg |= (front << DSIM_MAIN_HFP_SHIFT) | (back << DSIM_MAIN_HBP_SHIFT);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_MHPORCH);
+}
+
+void s5p_dsim_set_main_disp_sync_area(struct dsim_global *dsim,
+	unsigned short vert, unsigned short hori)
+{
+	unsigned int reg;
+
+	reg = (readl(dsim->reg_base + S5P_DSIM_MSYNC)) &
+		~(DSIM_MAIN_VSA_MASK) & ~(DSIM_MAIN_HSA_MASK);
+
+	reg |= ((vert & 0x3ff) << DSIM_MAIN_VSA_SHIFT) |
+		(hori << DSIM_MAIN_HSA_SHIFT);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_MSYNC);
+}
+
+void s5p_dsim_set_sub_disp_resol(struct dsim_global *dsim,
+	unsigned short vert, unsigned short hori)
+{
+	unsigned int reg;
+
+	reg = (readl(dsim->reg_base + S5P_DSIM_SDRESOL)) &
+		~(DSIM_SUB_STANDY_MASK);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_SDRESOL);
+
+	reg &= ~(DSIM_SUB_VRESOL_MASK) | ~(DSIM_SUB_HRESOL_MASK);
+	reg |= ((vert & 0x7ff) << DSIM_SUB_VRESOL_SHIFT) |
+		((hori & 0x7ff) << DSIM_SUB_HRESOL_SHIFT);
+	writel(reg, dsim->reg_base + S5P_DSIM_SDRESOL);
+
+	reg |= (1 << DSIM_SUB_STANDY_SHIFT);
+	writel(reg, dsim->reg_base + S5P_DSIM_SDRESOL);
+}
+
+void s5p_dsim_init_config(struct dsim_global *dsim,
+	struct dsim_lcd_config *main_lcd_info,
+	struct dsim_lcd_config *sub_lcd_info, struct dsim_config *dsim_info)
+{
+	unsigned int cfg = (readl(dsim->reg_base + S5P_DSIM_CONFIG)) &
+		~(1 << 28) & ~(0x1f << 20) & ~(0x3 << 5);
+
+	cfg =	(dsim_info->auto_flush << 29) |
+		(dsim_info->eot_disable << 28) |
+		(dsim_info->auto_vertical_cnt << DSIM_AUTO_MODE_SHIFT) |
+		(dsim_info->hse << DSIM_HSE_MODE_SHIFT) |
+		(dsim_info->hfp << DSIM_HFP_MODE_SHIFT) |
+		(dsim_info->hbp << DSIM_HBP_MODE_SHIFT) |
+		(dsim_info->hsa << DSIM_HSA_MODE_SHIFT) |
+		(dsim_info->e_no_data_lane << DSIM_NUM_OF_DATALANE_SHIFT);
+
+	writel(cfg, dsim->reg_base + S5P_DSIM_CONFIG);
+}
+
+void s5p_dsim_display_config(struct dsim_global *dsim,
+	struct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd)
+{
+	u32 reg = (readl(dsim->reg_base + S5P_DSIM_CONFIG)) &
+		~(0x3 << 26) & ~(1 << 25) & ~(0x3 << 18) & ~(0x7 << 12) &
+		~(0x3 << 16) & ~(0x7 << 8);
+
+	if (main_lcd->e_interface == DSIM_VIDEO)
+		reg |= (1 << 25);
+	else if (main_lcd->e_interface == DSIM_COMMAND)
+		reg &= ~(1 << 25);
+	else {
+		dev_err(dsim->dev, "this ddi is not MIPI interface.\n");
+		return;
+	}
+
+	/* main lcd */
+	reg |= ((u8) (main_lcd->parameter[DSI_VIDEO_MODE_SEL]) & 0x3) << 26 |
+		((u8) (main_lcd->parameter[DSI_VIRTUAL_CH_ID]) & 0x3) << 18 |
+		((u8) (main_lcd->parameter[DSI_FORMAT]) & 0x7) << 12;
+
+	writel(reg, dsim->reg_base + S5P_DSIM_CONFIG);
+}
+
+void s5p_dsim_enable_lane(struct dsim_global *dsim, unsigned char lane,
+	unsigned char enable)
+{
+	unsigned int reg;
+
+	reg = readl(dsim->reg_base + S5P_DSIM_CONFIG);
+
+	if (lane == DSIM_LANE_CLOCK) {
+		if (enable)
+			reg |= (1 << 0);
+		else
+			reg &= ~(1 << 0);
+	} else {
+		if (enable)
+			reg |= (lane << 1);
+		else
+			reg &= ~(lane << 1);
+	}
+
+	writel(reg, dsim->reg_base + S5P_DSIM_CONFIG);
+}
+
+
+void s5p_dsim_set_data_lane_number(struct dsim_global *dsim,
+	unsigned char count)
+{
+	unsigned int cfg = 0;
+
+	/* get the data lane number. */
+	cfg = DSIM_NUM_OF_DATA_LANE(count);
+
+	writel(cfg, dsim->reg_base + S5P_DSIM_CONFIG);
+}
+
+void s5p_dsim_enable_afc(struct dsim_global *dsim, unsigned char enable,
+	unsigned char afc_code)
+{
+	unsigned int reg = readl(dsim->reg_base + S5P_DSIM_PHYACCHR);
+
+	if (enable) {
+		reg |= (1 << 14);
+		reg &= ~(0x7 << 5);
+		reg |= (afc_code & 0x7) << 5;
+	} else
+		reg &= ~(1 << 14);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_PHYACCHR);
+}
+
+void s5p_dsim_enable_pll_bypass(struct dsim_global *dsim,
+	unsigned char enable)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &
+		~(DSIM_PLL_BYPASS_EXTERNAL);
+
+	reg |= enable << DSIM_PLL_BYPASS_SHIFT;
+
+	writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);
+}
+
+void s5p_dsim_set_pll_pms(struct dsim_global *dsim, unsigned char p,
+	unsigned short m, unsigned short s)
+{
+	unsigned int reg = readl(dsim->reg_base + S5P_DSIM_PLLCTRL);
+
+	reg |= ((p & 0x3f) << 13) | ((m & 0x1ff) << 4) | ((s & 0x7) << 1);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);
+}
+
+void s5p_dsim_pll_freq_band(struct dsim_global *dsim, unsigned char freq_band)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &
+		~(0x1f << DSIM_FREQ_BAND_SHIFT);
+
+	reg |= ((freq_band & 0x1f) << DSIM_FREQ_BAND_SHIFT);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);
+}
+
+void s5p_dsim_pll_freq(struct dsim_global *dsim, unsigned char pre_divider,
+	unsigned short main_divider, unsigned char scaler)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &
+		~(0x7ffff << 1);
+
+	reg |= (pre_divider & 0x3f) << 13 | (main_divider & 0x1ff) << 4 |
+		(scaler & 0x7) << 1;
+
+	writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);
+}
+
+void s5p_dsim_pll_stable_time(struct dsim_global *dsim,
+	unsigned int lock_time)
+{
+	writel(lock_time, dsim->reg_base + S5P_DSIM_PLLTMR);
+}
+
+void s5p_dsim_enable_pll(struct dsim_global *dsim, unsigned char enable)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &
+		~(0x1 << DSIM_PLL_EN_SHIFT);
+
+	reg |= ((enable & 0x1) << DSIM_PLL_EN_SHIFT);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);
+}
+
+void s5p_dsim_set_byte_clock_src(struct dsim_global *dsim, unsigned char src)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &
+		~(0x3 << DSIM_BYTE_CLK_SRC_SHIFT);
+
+	reg |= ((unsigned int) src) << DSIM_BYTE_CLK_SRC_SHIFT;
+
+	writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);
+}
+
+void s5p_dsim_enable_byte_clock(struct dsim_global *dsim,
+	unsigned char enable)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &
+		~(1 << DSIM_BYTE_CLKEN_SHIFT);
+
+	reg |= enable << DSIM_BYTE_CLKEN_SHIFT;
+
+	writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);
+}
+
+void s5p_dsim_set_esc_clk_prs(struct dsim_global *dsim, unsigned char enable,
+	unsigned short prs_val)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &
+		~(1 << DSIM_ESC_CLKEN_SHIFT) & ~(0xffff);
+
+	reg |= enable << DSIM_ESC_CLKEN_SHIFT;
+	if (enable)
+		reg |= prs_val;
+
+	writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);
+}
+
+void s5p_dsim_enable_esc_clk_on_lane(struct dsim_global *dsim,
+	unsigned char lane_sel, unsigned char enable)
+{
+	unsigned int reg = readl(dsim->reg_base + S5P_DSIM_CLKCTRL);
+
+	if (enable) {
+		if (lane_sel & DSIM_LANE_CLOCK)
+			reg |= 1 << DSIM_LANE_ESC_CLKEN_SHIFT;
+		if (lane_sel & DSIM_LANE_DATA0)
+			reg |= 1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 1);
+		if (lane_sel & DSIM_LANE_DATA1)
+			reg |= 1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 2);
+		if (lane_sel & DSIM_LANE_DATA2)
+			reg |= 1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 3);
+		if (lane_sel & DSIM_LANE_DATA2)
+			reg |= 1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 4);
+	} else {
+		if (lane_sel & DSIM_LANE_CLOCK)
+			reg &= ~(1 << DSIM_LANE_ESC_CLKEN_SHIFT);
+		if (lane_sel & DSIM_LANE_DATA0)
+			reg &= ~(1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 1));
+		if (lane_sel & DSIM_LANE_DATA1)
+			reg &= ~(1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 2));
+		if (lane_sel & DSIM_LANE_DATA2)
+			reg &= ~(1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 3));
+		if (lane_sel & DSIM_LANE_DATA2)
+			reg &= ~(1 << (DSIM_LANE_ESC_CLKEN_SHIFT + 4));
+	}
+
+	writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);
+}
+
+void s5p_dsim_force_dphy_stop_state(struct dsim_global *dsim,
+	unsigned char enable)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_ESCMODE)) &
+		~(0x1 << DSIM_FORCE_STOP_STATE_SHIFT);
+
+	reg |= ((enable & 0x1) << DSIM_FORCE_STOP_STATE_SHIFT);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE);
+}
+
+unsigned char s5p_dsim_is_lane_state(struct dsim_global *dsim,
+	unsigned char lane)
+{
+	unsigned int reg = readl(dsim->reg_base + S5P_DSIM_STATUS);
+
+	if ((lane & DSIM_LANE_ALL) > DSIM_LANE_CLOCK) { /* all lane state */
+		if ((reg & 0x7ff) ^ (((lane & 0xf) << 4) | (1 << 9)))
+			return DSIM_LANE_STATE_ULPS;
+		else if ((reg & 0x7ff) ^ (((lane & 0xf) << 0) | (1 << 8)))
+			return DSIM_LANE_STATE_STOP;
+		else {
+			dev_err(dsim->dev, "land state is unknown.\n");
+			return -1;
+		}
+	} else if (lane & DSIM_LANE_DATA_ALL) {	/* data lane */
+		if (reg & (lane << 4))
+			return DSIM_LANE_STATE_ULPS;
+		else if (reg & (lane << 0))
+			return DSIM_LANE_STATE_STOP;
+		else {
+			dev_err(dsim->dev, "data lane state is unknown.\n");
+			return -1;
+		}
+	} else if (lane & DSIM_LANE_CLOCK) { /* clock lane */
+		if (reg & (1 << 9))
+			return DSIM_LANE_STATE_ULPS;
+		else if (reg & (1 << 8))
+			return DSIM_LANE_STATE_STOP;
+		else if (reg & (1 << 10))
+			return DSIM_LANE_STATE_HS_READY;
+		else {
+			dev_err(dsim->dev, "data lane state is unknown.\n");
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+void s5p_dsim_set_stop_state_counter(struct dsim_global *dsim,
+	unsigned short cnt_val)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_ESCMODE)) &
+		~(0x7ff << DSIM_STOP_STATE_CNT_SHIFT);
+
+	reg |= ((cnt_val & 0x7ff) << DSIM_STOP_STATE_CNT_SHIFT);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE);
+}
+
+void s5p_dsim_set_bta_timeout(struct dsim_global *dsim, unsigned char timeout)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_TIMEOUT)) &
+		~(0xff << DSIM_BTA_TOUT_SHIFT);
+
+	reg |= (timeout << DSIM_BTA_TOUT_SHIFT);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_TIMEOUT);
+}
+
+void s5p_dsim_set_lpdr_timeout(struct dsim_global *dsim,
+	unsigned short timeout)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_TIMEOUT)) &
+		~(0xffff << DSIM_LPDR_TOUT_SHIFT);
+
+	reg |= (timeout << DSIM_LPDR_TOUT_SHIFT);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_TIMEOUT);
+}
+
+void s5p_dsim_set_data_mode(struct dsim_global *dsim, unsigned char data,
+	unsigned char state)
+{
+	unsigned int reg = readl(dsim->reg_base + S5P_DSIM_ESCMODE);
+
+	if (state == DSIM_STATE_HSCLKEN)
+		reg &= ~data;
+	else
+		reg |= data;
+
+	writel(reg, dsim->reg_base + S5P_DSIM_ESCMODE);
+}
+
+void s5p_dsim_enable_hs_clock(struct dsim_global *dsim, unsigned char enable)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_CLKCTRL)) &
+		~(1 << DSIM_TX_REQUEST_HSCLK_SHIFT);
+
+	reg |= enable << DSIM_TX_REQUEST_HSCLK_SHIFT;
+
+	writel(reg, dsim->reg_base + S5P_DSIM_CLKCTRL);
+}
+
+void s5p_dsim_dp_dn_swap(struct dsim_global *dsim, unsigned char swap_en)
+{
+	unsigned int reg = readl(dsim->reg_base + S5P_DSIM_PHYACCHR1);
+
+	reg &= ~(0x3 << 0);
+	reg |= (swap_en & 0x3) << 0;
+
+	writel(reg, dsim->reg_base + S5P_DSIM_PHYACCHR1);
+}
+
+void s5p_dsim_hs_zero_ctrl(struct dsim_global *dsim, unsigned char hs_zero)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &
+		~(0xf << 28);
+
+	reg |= ((hs_zero & 0xf) << 28);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);
+}
+
+void s5p_dsim_prep_ctrl(struct dsim_global *dsim, unsigned char prep)
+{
+	unsigned int reg = (readl(dsim->reg_base + S5P_DSIM_PLLCTRL)) &
+		~(0x7 << 20);
+
+	reg |= ((prep & 0x7) << 20);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_PLLCTRL);
+}
+
+void s5p_dsim_clear_interrupt(struct dsim_global *dsim, unsigned int int_src)
+{
+	unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC);
+
+	reg |= int_src;
+
+	writel(reg, dsim->reg_base + S5P_DSIM_INTSRC);
+}
+
+unsigned char s5p_dsim_is_pll_stable(struct dsim_global *dsim)
+{
+	return (unsigned char) ((readl(dsim->reg_base + S5P_DSIM_STATUS) &
+		    (1 << 31)) >> 31);
+}
+
+unsigned int s5p_dsim_get_fifo_state(struct dsim_global *dsim)
+{
+	unsigned int ret = 0;
+
+	ret = (readl(dsim->reg_base + S5P_DSIM_FIFOCTRL) & ~(0x1f));
+
+	return ret;
+}
+
+void s5p_dsim_wr_tx_header(struct dsim_global *dsim,
+	unsigned char di, unsigned char data0, unsigned char data1)
+{
+	unsigned int reg = (data1 << 16) | (data0 << 8) | ((di & 0x3f) << 0);
+
+	writel(reg, dsim->reg_base + S5P_DSIM_PKTHDR);
+}
+
+unsigned int _s5p_dsim_get_frame_done_status(struct dsim_global *dsim)
+{
+	unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC);
+
+	return (reg & INTSRC_FRAME_DONE) ? 1 : 0;
+}
+
+void _s5p_dsim_clear_frame_done(struct dsim_global *dsim)
+{
+	unsigned int reg = readl(dsim->reg_base + S5P_DSIM_INTSRC);
+
+	writel(reg | INTSRC_FRAME_DONE, dsim->reg_base +
+		S5P_DSIM_INTSRC);
+}
+
+void s5p_dsim_wr_tx_data(struct dsim_global *dsim, unsigned int tx_data)
+{
+	writel(tx_data, dsim->reg_base + S5P_DSIM_PAYLOAD);
+}
diff --git a/drivers/video/s5p_dsim_lowlevel.h b/drivers/video/s5p_dsim_lowlevel.h
new file mode 100644
index 0000000..ff950ba
--- /dev/null
+++ b/drivers/video/s5p_dsim_lowlevel.h
@@ -0,0 +1,101 @@
+/* linux/drivers/video/samsung/s5p_dsim_lowlevel.h
+ *
+ * Header file for Samsung MIPI-DSIM lowlevel driver.
+ *
+ * Copyright (c) 2009 Samsung Electronics
+ * InKi Dae <inki.dae at samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef _S5P_DSIM_LOWLEVEL_H
+#define _S5P_DSIM_LOWLEVEL_H
+
+struct dsim_global;
+
+extern void s5p_dsim_func_reset(struct dsim_global *dsim);
+extern void s5p_dsim_sw_reset(struct dsim_global *dsim);
+extern void s5p_dsim_set_interrupt_mask(struct dsim_global *dsim,
+	unsigned int mode, unsigned int mask);
+extern void s5p_dsim_set_data_lane_number(struct dsim_global *dsim,
+	unsigned char count);
+extern void s5p_dsim_init_fifo_pointer(struct dsim_global *dsim,
+	unsigned char cfg);
+extern void s5p_dsim_set_phy_tunning(struct dsim_global *dsim,
+	unsigned int value);
+extern void s5p_dsim_set_phy_tunning(struct dsim_global *dsim,
+	unsigned int value);
+extern void s5p_dsim_set_main_disp_resol(struct dsim_global *dsim,
+	unsigned short vert_resol, unsigned short hori_resol);
+extern void s5p_dsim_set_main_disp_vporch(struct dsim_global *dsim,
+	unsigned short cmd_allow, unsigned short vfront, unsigned short vback);
+extern void s5p_dsim_set_main_disp_hporch(struct dsim_global *dsim,
+	unsigned short front, unsigned short back);
+extern void s5p_dsim_set_main_disp_sync_area(struct dsim_global *dsim,
+	unsigned short vert, unsigned short hori);
+extern void s5p_dsim_set_sub_disp_resol(struct dsim_global *dsim,
+	unsigned short vert, unsigned short hori);
+extern void s5p_dsim_init_config(struct dsim_global *dsim,
+	struct dsim_lcd_config *main_lcd_info,
+	struct dsim_lcd_config *sub_lcd_info, struct dsim_config *dsim_info);
+extern void s5p_dsim_display_config(struct dsim_global *dsim,
+	struct dsim_lcd_config *main_lcd, struct dsim_lcd_config *sub_lcd);
+extern void s5p_dsim_set_data_lane_number(struct dsim_global *dsim,
+	unsigned char count);
+extern void s5p_dsim_enable_lane(struct dsim_global *dsim, unsigned char lane,
+	unsigned char enable);
+extern void s5p_dsim_enable_afc(struct dsim_global *dsim, unsigned char enable,
+	unsigned char afc_code);
+extern void s5p_dsim_enable_pll_bypass(struct dsim_global *dsim,
+	unsigned char enable);
+extern void s5p_dsim_set_pll_pms(struct dsim_global *dsim, unsigned char p,
+	unsigned short m, unsigned short s);
+extern void s5p_dsim_pll_freq_band(struct dsim_global *dsim,
+	unsigned char freq_band);
+extern void s5p_dsim_pll_freq(struct dsim_global *dsim,
+	unsigned char pre_divider, unsigned short main_divider,
+	unsigned char scaler);
+extern void s5p_dsim_pll_stable_time(struct dsim_global *dsim,
+	unsigned int lock_time);
+extern void s5p_dsim_enable_pll(struct dsim_global *dsim,
+	unsigned char enable);
+extern void s5p_dsim_set_byte_clock_src(struct dsim_global *dsim,
+	unsigned char src);
+extern void s5p_dsim_enable_byte_clock(struct dsim_global *dsim,
+	unsigned char enable);
+extern void s5p_dsim_set_esc_clk_prs(struct dsim_global *dsim,
+	unsigned char enable, unsigned short prs_val);
+extern void s5p_dsim_enable_esc_clk_on_lane(struct dsim_global *dsim,
+	unsigned char lane_sel, unsigned char enable);
+extern void s5p_dsim_force_dphy_stop_state(struct dsim_global *dsim,
+	unsigned char enable);
+extern unsigned char s5p_dsim_is_lane_state(struct dsim_global *dsim,
+	unsigned char lane);
+extern void s5p_dsim_set_stop_state_counter(struct dsim_global *dsim,
+	unsigned short cnt_val);
+extern void s5p_dsim_set_bta_timeout(struct dsim_global *dsim,
+	unsigned char timeout);
+extern void s5p_dsim_set_lpdr_timeout(struct dsim_global *dsim,
+	unsigned short timeout);
+extern void s5p_dsim_set_data_mode(struct dsim_global *dsim,
+	unsigned char data, unsigned char state);
+extern void s5p_dsim_enable_hs_clock(struct dsim_global *dsim,
+	unsigned char enable);
+extern void s5p_dsim_dp_dn_swap(struct dsim_global *dsim,
+	unsigned char swap_en);
+extern void s5p_dsim_hs_zero_ctrl(struct dsim_global *dsim,
+	unsigned char hs_zero);
+extern void s5p_dsim_prep_ctrl(struct dsim_global *dsim, unsigned char prep);
+extern void s5p_dsim_clear_interrupt(struct dsim_global *dsim,
+	unsigned int int_src);
+extern unsigned char s5p_dsim_is_pll_stable(struct dsim_global *dsim);
+extern unsigned int s5p_dsim_get_fifo_state(struct dsim_global *dsim);
+extern unsigned int _s5p_dsim_get_frame_done_status(struct dsim_global *dsim);
+extern void _s5p_dsim_clear_frame_done(struct dsim_global *dsim);
+extern void s5p_dsim_wr_tx_header(struct dsim_global *dsim,
+	unsigned char di, unsigned char data0, unsigned char data1);
+extern void s5p_dsim_wr_tx_data(struct dsim_global *dsim, unsigned int tx_data);
+
+#endif /* _S5P_DSIM_LOWLEVEL_H */


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From PeterHuewe at gmx.de  Tue Jun 29 13:35:39 2010
From: PeterHuewe at gmx.de (Peter =?iso-8859-1?q?H=FCwe?=)
Date: Tue, 29 Jun 2010 19:35:39 +0200
Subject: [PATCH] serial: fix rs485 for atmel_serial on avr32
Message-ID: <201006291935.40229.PeterHuewe@gmx.de>

From: Peter Huewe <peterhuewe at gmx.de>

This patch fixes a build failure [1-4] in the atmel_serial code introduced by
patch the patch ARM: 6092/1: atmel_serial: support for RS485
communications (e8faff7330a3501eafc9bfe5f4f15af444be29f5)

The build failure was caused by missing struct field and missing defines
for the avr32 board - the patch fixes this.

Signed-off-by: Peter Huewe <peterhuewe at gmx.de>
---
Despite so many reviewers of the original patch no one seemed to 
notice this issue :/

KernelVersion: linux-next-20100629

References:
[1] http://kisskb.ellerman.id.au/kisskb/buildresult/2575242/ - first failure
in linux-next, may 11th
[2] http://kisskb.ellerman.id.au/kisskb/buildresult/2816418/ - still
exists as of today
[3] http://kisskb.ellerman.id.au/kisskb/buildresult/2617511/ - first
failure in Linus' tree - May 20th - did really no one notice this?!
[4] http://kisskb.ellerman.id.au/kisskb/buildresult/2813956/ - still
exists in Linus' tree as of today

 arch/avr32/include/asm/ioctls.h             |    3 +++
 arch/avr32/mach-at32ap/include/mach/board.h |    2 ++
 drivers/serial/atmel_serial.c               |    1 +
 3 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/avr32/include/asm/ioctls.h b/arch/avr32/include/asm/ioctls.h
index bb32b6f..b7dd324 100644
--- a/arch/avr32/include/asm/ioctls.h
+++ b/arch/avr32/include/asm/ioctls.h
@@ -55,6 +55,9 @@
 #define TIOCSPTLCK	_IOW('T',0x31, int)  /* Lock/unlock Pty */
 #define TIOCSIG		_IOW('T',0x36, int)  /* Generate signal on Pty slave */
 
+#define TIOCGRS485      0x542E
+#define TIOCSRS485      0x542F
+
 #define FIONCLEX	0x5450
 #define FIOCLEX		0x5451
 #define FIOASYNC	0x5452
diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
index c7f25bb..6174020 100644
--- a/arch/avr32/mach-at32ap/include/mach/board.h
+++ b/arch/avr32/mach-at32ap/include/mach/board.h
@@ -5,6 +5,7 @@
 #define __ASM_ARCH_BOARD_H
 
 #include <linux/types.h>
+#include <linux/serial.h>
 
 #define GPIO_PIN_NONE	(-1)
 
@@ -35,6 +36,7 @@ struct atmel_uart_data {
 	short		use_dma_tx;	/* use transmit DMA? */
 	short		use_dma_rx;	/* use receive DMA? */
 	void __iomem	*regs;		/* virtual base address, if any */
+	struct serial_rs485	rs485;		/* rs485 settings */
 };
 void at32_map_usart(unsigned int hw_id, unsigned int line, int flags);
 struct platform_device *at32_add_device_usart(unsigned int id);
diff --git a/drivers/serial/atmel_serial.c b/drivers/serial/atmel_serial.c
index eed3c2d..a182def 100644
--- a/drivers/serial/atmel_serial.c
+++ b/drivers/serial/atmel_serial.c
@@ -41,6 +41,7 @@
 #include <linux/uaccess.h>
 
 #include <asm/io.h>
+#include <asm/ioctls.h>
 
 #include <asm/mach/serial_at91.h>
 #include <mach/board.h>
-- 
1.7.1



From mcuelenaere at gmail.com  Tue Jun 29 14:33:06 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Tue, 29 Jun 2010 20:33:06 +0200
Subject: [PATCH v5] libata: pata_samsung: Add Samsung PATA controller
	driver
In-Reply-To: <1277809518-1122-1-git-send-email-kgene.kim@samsung.com>
References: <1277809518-1122-1-git-send-email-kgene.kim@samsung.com>
Message-ID: <4C2A3C62.4090101@gmail.com>

 Op 29-06-10 13:05, Kukjin Kim schreef:
> From: Abhilash Kesavan <a.kesavan at samsung.com>
>
> Adds support for the Samsung PATA controller. This driver is based on the
> Libata subsystem and references the earlier patches sent for IDE subsystem.
>
> Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> Cc: Ben Dooks <ben-linux at fluff.org>
> ---
>  drivers/ata/Kconfig           |    9 +
>  drivers/ata/Makefile          |    1 +
>  drivers/ata/pata_samsung_cf.c |  728 +++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 738 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/ata/pata_samsung_cf.c
>
> diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> index 73f8833..51e28e7 100644
> --- a/drivers/ata/Kconfig
> +++ b/drivers/ata/Kconfig
> @@ -796,6 +796,15 @@ config PATA_RZ1000
>  
>  	  If unsure, say N.
>  
> +config PATA_SAMSUNG_CF
> +	tristate "Samsung SoC PATA support"
> +	depends on SAMSUNG_DEV_IDE
> +	help
> +	  This option enables basic support for Samsung's S3C/S5P board
> +	  PATA controllers via the new ATA layer
> +
> +	  If unsure, say N.
> +
>  config PATA_WINBOND_VLB
>  	tristate "Winbond W83759A VLB PATA support (Experimental)"
>  	depends on ISA && EXPERIMENTAL
> diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> index 7ef89d7..9576776 100644
> --- a/drivers/ata/Makefile
> +++ b/drivers/ata/Makefile
> @@ -87,6 +87,7 @@ obj-$(CONFIG_PATA_OF_PLATFORM)	+= pata_of_platform.o
>  obj-$(CONFIG_PATA_QDI)		+= pata_qdi.o
>  obj-$(CONFIG_PATA_RB532)	+= pata_rb532_cf.o
>  obj-$(CONFIG_PATA_RZ1000)	+= pata_rz1000.o
> +obj-$(CONFIG_PATA_SAMSUNG_CF)	+= pata_samsung_cf.o
>  obj-$(CONFIG_PATA_WINBOND_VLB)	+= pata_winbond.o
>  
>  # Should be last but two libata driver
> diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
> new file mode 100644
> index 0000000..26b96c3
> --- /dev/null
> +++ b/drivers/ata/pata_samsung_cf.c
> @@ -0,0 +1,728 @@
> +/*
> + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> + *		http://www.samsung.com
> + *
> + * PATA driver for Samsung SoCs.
> + * Supports CF Interface in True IDE mode. Currently only PIO mode has been
> + * implemented; UDMA support has to be added.
> + *
> + * Based on:
> + *	PATA driver for AT91SAM9260 Static Memory Controller
> + *	PATA driver for Toshiba SCC controller
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2
> + * as published by the Free Software Foundation.
> +*/
> +
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/init.h>
> +#include <linux/clk.h>
> +#include <linux/libata.h>
> +#include <linux/platform_device.h>
> +#include <linux/slab.h>
> +
> +#include <plat/ata.h>
> +#include <plat/regs-ata.h>
> +
> +#define DRV_NAME "pata_samsung_cf"
> +#define DRV_VERSION "0.1"
> +
> +enum s3c_cpu_type {
> +	TYPE_S3C64XX,
> +	TYPE_S5PC100,
> +	TYPE_S5PV210,
> +};
> +
> +/*
> + * struct s3c_ide_info - S3C PATA instance.
> + * @clk: The clock resource for this controller.
> + * @ide_addr: The area mapped for the hardware registers.
> + * @sfr_addr: The area mapped for the special function registers.
> + * @irq: The IRQ number we are using.
> + * @cpu_type: The exact type of this controller.
> + * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
> + */
> +struct s3c_ide_info {
> +	struct clk *clk;
> +	void __iomem *ide_addr;
> +	void __iomem *sfr_addr;
> +	unsigned int irq;
> +	enum s3c_cpu_type cpu_type;
> +	unsigned int fifo_status_reg;
> +};
> +
> +static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
> +{
> +	u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
> +	reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg | S3C_ATA_CFG_SWAP);
> +	writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
> +}
> +
> +static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
> +{
> +	/* Select true-ide as the internal operating mode */
> +	writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) | S3C_CFATA_MUX_TRUEIDE,
> +		s3c_ide_sfrbase + S3C_CFATA_MUX);
> +}
> +
> +static unsigned long
> +pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
> +{
> +	int t1 = ata->setup;
> +	int t2 = ata->act8b;
> +	int t2i = ata->rec8b;
> +	ulong piotime;
> +
> +	piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
> +
> +	return piotime;
> +}
> +
> +static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
> +{
> +	struct s3c_ide_info *info = ap->host->private_data;
> +	struct ata_timing timing;
> +	int cycle_time;
> +	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
> +	ulong piotime;
> +
> +	/* Enables IORDY if mode requires it */
> +	if (ata_pio_need_iordy(adev))
> +		ata_cfg |= S3C_ATA_CFG_IORDYEN;
> +	else
> +		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
> +
> +	cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
> +
> +	ata_timing_compute(adev, adev->pio_mode, &timing,
> +					cycle_time * 1000, 0);
> +
> +	piotime = pata_s3c_setup_timing(info, &timing);
> +
> +	writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
> +	writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
> +}
> +
> +/*
> + * Waits until the IDE controller is able to perform next read/write
> + * operation to the disk. Needed for 64XX series boards only.
> + */
> +static int wait_for_host_ready(struct s3c_ide_info *info)
> +{
> +	ulong timeout;
> +	void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
> +

Shouldn't this have an if (type != S3C64XX) return 0; ?

> +	/* wait for maximum of 20 msec */
> +	timeout = jiffies + msecs_to_jiffies(20);
> +	while (time_before(jiffies, timeout)) {
> +		if ((readl(fifo_reg) >> 28) == 0)
> +			return 0;
> +	}
> +	return -EBUSY;
> +}

-- 
Maurus Cuelenaere


From nico at fluxnic.net  Tue Jun 29 15:20:33 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 29 Jun 2010 15:20:33 -0400 (EDT)
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100629141836.GM2822@atomide.com>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
	<20100623073912.GA12255@atomide.com>
	<20100623133636.GC7058@shareable.org>
	<20100629141836.GM2822@atomide.com>
Message-ID: <alpine.LFD.2.00.1006291355520.24097@xanadu.home>

On Tue, 29 Jun 2010, Tony Lindgren wrote:

> OK. Sorry for the delay again. Here's an updated version that sets
> __kuser_get_tls instruction dynamically. Does this do what you were
> thinking, or did I miss something?

See my comments below.

> Also, can we detect somehow the hardware that uses CONFIG_TLS_REG_EMUL?
> Might be possible to remove that Kconfig option too later on..

Well... I don't think we _should_ try to detect it as it is not widely 
available if at all.

And there is actually a "bug" with __kuser_get_tls because if ever 
CONFIG_TLS_REG_EMUL is selected then a call to __kuser_get_tls is 
currently doing nothing while it should actually use the mrc 
instruction.

> diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
> index f7bd52b..c1062c3 100644
> --- a/arch/arm/include/asm/hwcap.h
> +++ b/arch/arm/include/asm/hwcap.h
> @@ -19,6 +19,7 @@
>  #define HWCAP_NEON	4096
>  #define HWCAP_VFPv3	8192
>  #define HWCAP_VFPv3D16	16384
> +#define HWCAP_TLS	32768
>  
>  #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
>  /*
> diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
> index 7ee48e7..949df9b 100644
> --- a/arch/arm/kernel/entry-armv.S
> +++ b/arch/arm/kernel/entry-armv.S
> @@ -739,11 +739,13 @@ ENTRY(__switch_to)
>  #ifdef CONFIG_MMU
>  	ldr	r6, [r2, #TI_CPU_DOMAIN]
>  #endif
> -#if defined(CONFIG_HAS_TLS_REG)
> -	mcr	p15, 0, r3, c13, c0, 3		@ set TLS register
> -#elif !defined(CONFIG_TLS_REG_EMUL)
> -	mov	r4, #0xffff0fff
> -	str	r3, [r4, #-15]			@ TLS val at 0xffff0ff0
> +#if !defined(CONFIG_TLS_REG_EMUL)
> +	ldr	r4, =elf_hwcap
> +	ldr	r4, [r4, #0]
> +	mov	r5, #0xffff0fff
> +	tst	r4, #HWCAP_TLS			@ hardware TLS available?
> +	mcrne	p15, 0, r3, c13, c0, 3		@ yes, set TLS register
> +	streq	r3, [r5, #-15]			@ set TLS value at 0xffff0ff0
>  #endif

Could this be a tristate instead?  There are actually 3 cases:

1) We know the TLS reg is _always_ available i.e. ARMv6K, ARMV7 and 
   above.  In that case the test on elf_hwcap is redundant and wasteful.

2) We know the TLS reg is _never_ available i.e. pre-ARMv6.  The test on 
   elf_hwcap is again redundant and wasteful.

3) We're unsure as the actual CPU is known only at run time.

Case #1 will become the common case in the future.  Case #2 is still 
widely relevant for deployed systems in the field, and some popular 
ARMv5TE based SOCs are still produced right now.  So instead of 
replacing #1 and #2 with #3, I think you should add #3 to the other 
cases instead.

>  #ifdef CONFIG_MMU
>  	mcr	p15, 0, r6, c3, c0, 0		@ Set domain register
> @@ -1009,16 +1011,13 @@ kuser_cmpxchg_fixup:
>   */
>  
>  __kuser_get_tls:				@ 0xffff0fe0
> -
> -#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
> -	ldr	r0, [pc, #(16 - 8)]		@ TLS stored at 0xffff0ff0
> -#else
> -	mrc	p15, 0, r0, c13, c0, 3		@ read TLS register
> -#endif
> +	nop				@ read TLS, set in kuser_get_tls_init
>  	usr_ret	lr
> -
> -	.rep	5
> -	.word	0			@ pad up to __kuser_helper_version
> +	mrc	p15, 0, r0, c13, c0, 3	@ 0xffff0fe8 hardware TLS code
> +	ldr	r0, [pc, #(16 - 8)]	@ 0xffff0fec software TLS code
> +	.word	0			@ 0xffff0ff0 software TLS value
> +	nop				@ pad up to __kuser_helper_version
> +	nop
>  	.endr

This looks obscur.  The idea of patching the appropriate instruction at 
runtime here is a good one.  However I'd simply keep the ldr version in 
place otherwise the pc displacement doesn't match anymore when 
disassembling.  And simply overwrite it with the mrc version when 
necessary.

BTW you left a stray .endr here.

>  /*
> diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
> index 122d999..a675260 100644
> --- a/arch/arm/kernel/setup.c
> +++ b/arch/arm/kernel/setup.c
> @@ -269,6 +269,27 @@ static void __init cacheid_init(void)
>  extern struct proc_info_list *lookup_processor_type(unsigned int);
>  extern struct machine_desc *lookup_machine_type(unsigned int);
>  
> +#ifdef CONFIG_CPU_V6
> +static void __init feat_v6_fixup(void)
> +{
> +	int id = read_cpuid_id();
> +
> +	if (id & 0x000f0000 != 0x00070000)
> +		return;
> +
> +	/*
> +	 * HWCAP_TLS is available only on 1136 r1p0 and later,
> +	 * see also kuser_get_tls_init.
> +	 */
> +	if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
> +		elf_hwcap &= ~HWCAP_TLS;

You should probably test for the vendor ID as well (ARM in this case).

> +}
> +#else
> +static inline void feat_v6_fixup(void)
> +{
> +}
> +#endif

I think the #ifdef is unnecessary here.  This is __init code anyway, so 
this could as well be always compiled in.

> +
>  static void __init setup_processor(void)
>  {
>  	struct proc_info_list *list;
> @@ -311,6 +332,8 @@ static void __init setup_processor(void)
>  	elf_hwcap &= ~HWCAP_THUMB;
>  #endif
>  
> +	feat_v6_fixup();
> +
>  	cacheid_init();
>  	cpu_proc_init();
>  }
> diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
> index 1621e53..85dd001 100644
> --- a/arch/arm/kernel/traps.c
> +++ b/arch/arm/kernel/traps.c
> @@ -518,16 +518,19 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
>  
>  	case NR(set_tls):
>  		thread->tp_value = regs->ARM_r0;
> -#if defined(CONFIG_HAS_TLS_REG)
> -		asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
> -#elif !defined(CONFIG_TLS_REG_EMUL)
> -		/*
> -		 * User space must never try to access this directly.
> -		 * Expect your app to break eventually if you do so.
> -		 * The user helper at 0xffff0fe0 must be used instead.
> -		 * (see entry-armv.S for details)
> -		 */
> -		*((unsigned int *)0xffff0ff0) = regs->ARM_r0;
> +#if !defined(CONFIG_TLS_REG_EMUL)
> +		if (elf_hwcap & HWCAP_TLS) {
> +			asm ("mcr p15, 0, %0, c13, c0, 3"
> +				: : "r" (regs->ARM_r0));
> +		} else {
> +			/*
> +			 * User space must never try to access this directly.
> +			 * Expect your app to break eventually if you do so.
> +			 * The user helper at 0xffff0fe0 must be used instead.
> +			 * (see entry-armv.S for details)
> +			 */
> +			*((unsigned int *)0xffff0ff0) = regs->ARM_r0;
> +		}
>  #endif

The same comment as for __kuser_get_tls would apply here.  However, 
instead of duplicating the code block, you could define a macro, such as 
has_tls_reg(), that would be either 0, 1, or ((elf_hwcap & HWCAP_TLS).

>  		return 0;
>  
> @@ -743,6 +746,21 @@ void __init trap_init(void)
>  	return;
>  }
>  
> +#if defined(CONFIG_TLS_REG_EMUL)
> +static void __init kuser_get_tls_init(unsigned long vectors)
> +{
> +	memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
> +}
> +#else
> +static void __init kuser_get_tls_init(unsigned long vectors)
> +{
> +	if (elf_hwcap & HWCAP_TLS)
> +		memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
> +	else
> +		memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfec, 4);
> +}
> +#endif

Please move the #ifdef within the function body.  Also it would be nice 
to add comments about what those magic offsets are.


Nicolas


From g.liakhovetski at gmx.de  Tue Jun 29 15:47:42 2010
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Tue, 29 Jun 2010 21:47:42 +0200 (CEST)
Subject: [PATCHv4 1/3] mx2_camera: Add soc_camera support for i.MX25/i.MX27
In-Reply-To: <03d6e55c39690618e92a91a580ec34549a135c79.1277096909.git.baruch@tkos.co.il>
References: <cover.1277096909.git.baruch@tkos.co.il>
	<03d6e55c39690618e92a91a580ec34549a135c79.1277096909.git.baruch@tkos.co.il>
Message-ID: <Pine.LNX.4.64.1006292145001.22603@axis700.grange>

Hi Baruch

On Mon, 21 Jun 2010, Baruch Siach wrote:

> This is the soc_camera support developed by Sascha Hauer for the i.MX27.  Alan
> Carvalho de Assis modified the original driver to get it working on more recent
> kernels. I modified it further to add support for i.MX25. This driver has been
> tested on i.MX25 and i.MX27 based platforms.

This looks good to me, thanks! Overflow on eMMA is, probably, still 
broken, but it will, most probably, remain so, until someone tests and 
fixes it. One question though: do you know whether this imx/mxc overhaul: 
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/thread.html#18844 
affects your driver? I can ask Uwe, but maybe you have an idea or could 
test your patches with Uwe's git tree?

Thanks
Guennadi

> 
> Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> ---
>  arch/arm/plat-mxc/include/mach/memory.h  |    4 +-
>  arch/arm/plat-mxc/include/mach/mx2_cam.h |   46 +
>  drivers/media/video/Kconfig              |   13 +
>  drivers/media/video/Makefile             |    1 +
>  drivers/media/video/mx2_camera.c         | 1493 ++++++++++++++++++++++++++++++
>  5 files changed, 1555 insertions(+), 2 deletions(-)
>  create mode 100644 arch/arm/plat-mxc/include/mach/mx2_cam.h
>  create mode 100644 drivers/media/video/mx2_camera.c
> 
> diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
> index c4b40c3..5803836 100644
> --- a/arch/arm/plat-mxc/include/mach/memory.h
> +++ b/arch/arm/plat-mxc/include/mach/memory.h
> @@ -44,12 +44,12 @@
>   */
>  #define CONSISTENT_DMA_SIZE SZ_8M
>  
> -#elif defined(CONFIG_MX1_VIDEO)
> +#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_MX2_VIDEO)
>  /*
>   * Increase size of DMA-consistent memory region.
>   * This is required for i.MX camera driver to capture at least four VGA frames.
>   */
>  #define CONSISTENT_DMA_SIZE SZ_4M
> -#endif /* CONFIG_MX1_VIDEO */
> +#endif /* CONFIG_MX1_VIDEO || CONFIG_MX2_VIDEO */
>  
>  #endif /* __ASM_ARCH_MXC_MEMORY_H__ */
> diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h
> new file mode 100644
> index 0000000..3c080a3
> --- /dev/null
> +++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h
> @@ -0,0 +1,46 @@
> +/*
> + * mx2-cam.h - i.MX27/i.MX25 camera driver header file
> + *
> + * Copyright (C) 2003, Intel Corporation
> + * Copyright (C) 2008, Sascha Hauer <s.hauer at pengutronix.de>
> + * Copyright (C) 2010, Baruch Siach <baruch at tkos.co.il>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
> + */
> +
> +#ifndef __MACH_MX2_CAM_H_
> +#define __MACH_MX2_CAM_H_
> +
> +#define MX2_CAMERA_SWAP16		(1 << 0)
> +#define MX2_CAMERA_EXT_VSYNC		(1 << 1)
> +#define MX2_CAMERA_CCIR			(1 << 2)
> +#define MX2_CAMERA_CCIR_INTERLACE	(1 << 3)
> +#define MX2_CAMERA_HSYNC_HIGH		(1 << 4)
> +#define MX2_CAMERA_GATED_CLOCK		(1 << 5)
> +#define MX2_CAMERA_INV_DATA		(1 << 6)
> +#define MX2_CAMERA_PCLK_SAMPLE_RISING	(1 << 7)
> +#define MX2_CAMERA_PACK_DIR_MSB		(1 << 8)
> +
> +/**
> + * struct mx2_camera_platform_data - optional platform data for mx2_camera
> + * @flags: any combination of MX2_CAMERA_*
> + * @clk: clock rate of the csi block / 2
> + */
> +struct mx2_camera_platform_data {
> +	unsigned long flags;
> +	unsigned long clk;
> +};
> +
> +#endif /* __MACH_MX2_CAM_H_ */
> diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
> index bdbc9d3..47bf6e6 100644
> --- a/drivers/media/video/Kconfig
> +++ b/drivers/media/video/Kconfig
> @@ -969,6 +969,19 @@ config VIDEO_OMAP2
>  	---help---
>  	  This is a v4l2 driver for the TI OMAP2 camera capture interface
>  
> +config MX2_VIDEO
> +        bool
> +
> +config VIDEO_MX2
> +	tristate "i.MX27/i.MX25 Camera Sensor Interface driver"
> +	depends on VIDEO_DEV && SOC_CAMERA && (MACH_MX27 || ARCH_MX25)
> +	select VIDEOBUF_DMA_CONTIG
> +	select MX2_VIDEO
> +	---help---
> +	  This is a v4l2 driver for the i.MX27 and the i.MX25 Camera Sensor
> +	  Interface
> +
> +
>  #
>  # USB Multimedia device configuration
>  #
> diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
> index cc93859..b08bd2b 100644
> --- a/drivers/media/video/Makefile
> +++ b/drivers/media/video/Makefile
> @@ -162,6 +162,7 @@ obj-$(CONFIG_SOC_CAMERA)		+= soc_camera.o soc_mediabus.o
>  obj-$(CONFIG_SOC_CAMERA_PLATFORM)	+= soc_camera_platform.o
>  # soc-camera host drivers have to be linked after camera drivers
>  obj-$(CONFIG_VIDEO_MX1)			+= mx1_camera.o
> +obj-$(CONFIG_VIDEO_MX2)			+= mx2_camera.o
>  obj-$(CONFIG_VIDEO_MX3)			+= mx3_camera.o
>  obj-$(CONFIG_VIDEO_PXA27x)		+= pxa_camera.o
>  obj-$(CONFIG_VIDEO_SH_MOBILE_CEU)	+= sh_mobile_ceu_camera.o
> diff --git a/drivers/media/video/mx2_camera.c b/drivers/media/video/mx2_camera.c
> new file mode 100644
> index 0000000..79ad522
> --- /dev/null
> +++ b/drivers/media/video/mx2_camera.c
> @@ -0,0 +1,1493 @@
> +/*
> + * V4L2 Driver for i.MX27/i.MX25 camera host
> + *
> + * Copyright (C) 2008, Sascha Hauer, Pengutronix
> + * Copyright (C) 2010, Baruch Siach, Orex Computed Radiography
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/io.h>
> +#include <linux/delay.h>
> +#include <linux/slab.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/errno.h>
> +#include <linux/fs.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/mm.h>
> +#include <linux/moduleparam.h>
> +#include <linux/time.h>
> +#include <linux/version.h>
> +#include <linux/device.h>
> +#include <linux/platform_device.h>
> +#include <linux/mutex.h>
> +#include <linux/clk.h>
> +
> +#include <media/v4l2-common.h>
> +#include <media/v4l2-dev.h>
> +#include <media/videobuf-dma-contig.h>
> +#include <media/soc_camera.h>
> +#include <media/soc_mediabus.h>
> +
> +#include <linux/videodev2.h>
> +
> +#include <mach/mx2_cam.h>
> +#include <mach/dma-mx1-mx2.h>
> +#include <mach/hardware.h>
> +
> +#include <asm/dma.h>
> +
> +#define MX2_CAM_DRV_NAME "mx2-camera"
> +#define MX2_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
> +#define MX2_CAM_DRIVER_DESCRIPTION "i.MX2x_Camera"
> +
> +/* reset values */
> +#define CSICR1_RESET_VAL	0x40000800
> +#define CSICR2_RESET_VAL	0x0
> +#define CSICR3_RESET_VAL	0x0
> +
> +/* csi control reg 1 */
> +#define CSICR1_SWAP16_EN	(1 << 31)
> +#define CSICR1_EXT_VSYNC	(1 << 30)
> +#define CSICR1_EOF_INTEN	(1 << 29)
> +#define CSICR1_PRP_IF_EN	(1 << 28)
> +#define CSICR1_CCIR_MODE	(1 << 27)
> +#define CSICR1_COF_INTEN	(1 << 26)
> +#define CSICR1_SF_OR_INTEN	(1 << 25)
> +#define CSICR1_RF_OR_INTEN	(1 << 24)
> +#define CSICR1_STATFF_LEVEL	(3 << 22)
> +#define CSICR1_STATFF_INTEN	(1 << 21)
> +#define CSICR1_RXFF_LEVEL(l)	(((l) & 3) << 19)	/* MX27 */
> +#define CSICR1_FB2_DMA_INTEN	(1 << 20)		/* MX25 */
> +#define CSICR1_FB1_DMA_INTEN	(1 << 19)		/* MX25 */
> +#define CSICR1_RXFF_INTEN	(1 << 18)
> +#define CSICR1_SOF_POL		(1 << 17)
> +#define CSICR1_SOF_INTEN	(1 << 16)
> +#define CSICR1_MCLKDIV(d)	(((d) & 0xF) << 12)
> +#define CSICR1_HSYNC_POL	(1 << 11)
> +#define CSICR1_CCIR_EN		(1 << 10)
> +#define CSICR1_MCLKEN		(1 << 9)
> +#define CSICR1_FCC		(1 << 8)
> +#define CSICR1_PACK_DIR		(1 << 7)
> +#define CSICR1_CLR_STATFIFO	(1 << 6)
> +#define CSICR1_CLR_RXFIFO	(1 << 5)
> +#define CSICR1_GCLK_MODE	(1 << 4)
> +#define CSICR1_INV_DATA		(1 << 3)
> +#define CSICR1_INV_PCLK		(1 << 2)
> +#define CSICR1_REDGE		(1 << 1)
> +
> +#define SHIFT_STATFF_LEVEL	22
> +#define SHIFT_RXFF_LEVEL	19
> +#define SHIFT_MCLKDIV		12
> +
> +/* control reg 3 */
> +#define CSICR3_FRMCNT		(0xFFFF << 16)
> +#define CSICR3_FRMCNT_RST	(1 << 15)
> +#define CSICR3_DMA_REFLASH_RFF	(1 << 14)
> +#define CSICR3_DMA_REFLASH_SFF	(1 << 13)
> +#define CSICR3_DMA_REQ_EN_RFF	(1 << 12)
> +#define CSICR3_DMA_REQ_EN_SFF	(1 << 11)
> +#define CSICR3_RXFF_LEVEL(l)	(((l) & 7) << 4)	/* MX25 */
> +#define CSICR3_CSI_SUP		(1 << 3)
> +#define CSICR3_ZERO_PACK_EN	(1 << 2)
> +#define CSICR3_ECC_INT_EN	(1 << 1)
> +#define CSICR3_ECC_AUTO_EN	(1 << 0)
> +
> +#define SHIFT_FRMCNT		16
> +
> +/* csi status reg */
> +#define CSISR_SFF_OR_INT	(1 << 25)
> +#define CSISR_RFF_OR_INT	(1 << 24)
> +#define CSISR_STATFF_INT	(1 << 21)
> +#define CSISR_DMA_TSF_FB2_INT	(1 << 20)	/* MX25 */
> +#define CSISR_DMA_TSF_FB1_INT	(1 << 19)	/* MX25 */
> +#define CSISR_RXFF_INT		(1 << 18)
> +#define CSISR_EOF_INT		(1 << 17)
> +#define CSISR_SOF_INT		(1 << 16)
> +#define CSISR_F2_INT		(1 << 15)
> +#define CSISR_F1_INT		(1 << 14)
> +#define CSISR_COF_INT		(1 << 13)
> +#define CSISR_ECC_INT		(1 << 1)
> +#define CSISR_DRDY		(1 << 0)
> +
> +#define CSICR1			0x00
> +#define CSICR2			0x04
> +#define CSISR			(cpu_is_mx27() ? 0x08 : 0x18)
> +#define CSISTATFIFO		0x0c
> +#define CSIRFIFO		0x10
> +#define CSIRXCNT		0x14
> +#define CSICR3			(cpu_is_mx27() ? 0x1C : 0x08)
> +#define CSIDMASA_STATFIFO	0x20
> +#define CSIDMATA_STATFIFO	0x24
> +#define CSIDMASA_FB1		0x28
> +#define CSIDMASA_FB2		0x2c
> +#define CSIFBUF_PARA		0x30
> +#define CSIIMAG_PARA		0x34
> +
> +/* EMMA PrP */
> +#define PRP_CNTL			0x00
> +#define PRP_INTR_CNTL			0x04
> +#define PRP_INTRSTATUS			0x08
> +#define PRP_SOURCE_Y_PTR		0x0c
> +#define PRP_SOURCE_CB_PTR		0x10
> +#define PRP_SOURCE_CR_PTR		0x14
> +#define PRP_DEST_RGB1_PTR		0x18
> +#define PRP_DEST_RGB2_PTR		0x1c
> +#define PRP_DEST_Y_PTR			0x20
> +#define PRP_DEST_CB_PTR			0x24
> +#define PRP_DEST_CR_PTR			0x28
> +#define PRP_SRC_FRAME_SIZE		0x2c
> +#define PRP_DEST_CH1_LINE_STRIDE	0x30
> +#define PRP_SRC_PIXEL_FORMAT_CNTL	0x34
> +#define PRP_CH1_PIXEL_FORMAT_CNTL	0x38
> +#define PRP_CH1_OUT_IMAGE_SIZE		0x3c
> +#define PRP_CH2_OUT_IMAGE_SIZE		0x40
> +#define PRP_SRC_LINE_STRIDE		0x44
> +#define PRP_CSC_COEF_012		0x48
> +#define PRP_CSC_COEF_345		0x4c
> +#define PRP_CSC_COEF_678		0x50
> +#define PRP_CH1_RZ_HORI_COEF1		0x54
> +#define PRP_CH1_RZ_HORI_COEF2		0x58
> +#define PRP_CH1_RZ_HORI_VALID		0x5c
> +#define PRP_CH1_RZ_VERT_COEF1		0x60
> +#define PRP_CH1_RZ_VERT_COEF2		0x64
> +#define PRP_CH1_RZ_VERT_VALID		0x68
> +#define PRP_CH2_RZ_HORI_COEF1		0x6c
> +#define PRP_CH2_RZ_HORI_COEF2		0x70
> +#define PRP_CH2_RZ_HORI_VALID		0x74
> +#define PRP_CH2_RZ_VERT_COEF1		0x78
> +#define PRP_CH2_RZ_VERT_COEF2		0x7c
> +#define PRP_CH2_RZ_VERT_VALID		0x80
> +
> +#define PRP_CNTL_CH1EN		(1 << 0)
> +#define PRP_CNTL_CH2EN		(1 << 1)
> +#define PRP_CNTL_CSIEN		(1 << 2)
> +#define PRP_CNTL_DATA_IN_YUV420	(0 << 3)
> +#define PRP_CNTL_DATA_IN_YUV422	(1 << 3)
> +#define PRP_CNTL_DATA_IN_RGB16	(2 << 3)
> +#define PRP_CNTL_DATA_IN_RGB32	(3 << 3)
> +#define PRP_CNTL_CH1_OUT_RGB8	(0 << 5)
> +#define PRP_CNTL_CH1_OUT_RGB16	(1 << 5)
> +#define PRP_CNTL_CH1_OUT_RGB32	(2 << 5)
> +#define PRP_CNTL_CH1_OUT_YUV422	(3 << 5)
> +#define PRP_CNTL_CH2_OUT_YUV420	(0 << 7)
> +#define PRP_CNTL_CH2_OUT_YUV422 (1 << 7)
> +#define PRP_CNTL_CH2_OUT_YUV444	(2 << 7)
> +#define PRP_CNTL_CH1_LEN	(1 << 9)
> +#define PRP_CNTL_CH2_LEN	(1 << 10)
> +#define PRP_CNTL_SKIP_FRAME	(1 << 11)
> +#define PRP_CNTL_SWRST		(1 << 12)
> +#define PRP_CNTL_CLKEN		(1 << 13)
> +#define PRP_CNTL_WEN		(1 << 14)
> +#define PRP_CNTL_CH1BYP		(1 << 15)
> +#define PRP_CNTL_IN_TSKIP(x)	((x) << 16)
> +#define PRP_CNTL_CH1_TSKIP(x)	((x) << 19)
> +#define PRP_CNTL_CH2_TSKIP(x)	((x) << 22)
> +#define PRP_CNTL_INPUT_FIFO_LEVEL(x)	((x) << 25)
> +#define PRP_CNTL_RZ_FIFO_LEVEL(x)	((x) << 27)
> +#define PRP_CNTL_CH2B1EN	(1 << 29)
> +#define PRP_CNTL_CH2B2EN	(1 << 30)
> +#define PRP_CNTL_CH2FEN		(1 << 31)
> +
> +/* IRQ Enable and status register */
> +#define PRP_INTR_RDERR		(1 << 0)
> +#define PRP_INTR_CH1WERR	(1 << 1)
> +#define PRP_INTR_CH2WERR	(1 << 2)
> +#define PRP_INTR_CH1FC		(1 << 3)
> +#define PRP_INTR_CH2FC		(1 << 5)
> +#define PRP_INTR_LBOVF		(1 << 7)
> +#define PRP_INTR_CH2OVF		(1 << 8)
> +
> +#define mx27_camera_emma(pcdev)	(cpu_is_mx27() && pcdev->use_emma)
> +
> +#define MAX_VIDEO_MEM	16
> +
> +struct mx2_camera_dev {
> +	struct device		*dev;
> +	struct soc_camera_host	soc_host;
> +	struct soc_camera_device *icd;
> +	struct clk		*clk_csi, *clk_emma;
> +
> +	unsigned int		irq_csi, irq_emma;
> +	void __iomem		*base_csi, *base_emma;
> +	unsigned long		base_dma;
> +
> +	struct mx2_camera_platform_data *pdata;
> +	struct resource		*res_csi, *res_emma;
> +	unsigned long		platform_flags;
> +
> +	struct list_head	capture;
> +	struct list_head	active_bufs;
> +
> +	spinlock_t		lock;
> +
> +	int			dma;
> +	struct mx2_buffer	*active;
> +	struct mx2_buffer	*fb1_active;
> +	struct mx2_buffer	*fb2_active;
> +
> +	int			use_emma;
> +
> +	u32			csicr1;
> +
> +	void __iomem		*discard_buffer;
> +	dma_addr_t		discard_buffer_dma;
> +	size_t			discard_size;
> +};
> +
> +/* buffer for one video frame */
> +struct mx2_buffer {
> +	/* common v4l buffer stuff -- must be first */
> +	struct videobuf_buffer		vb;
> +
> +	enum v4l2_mbus_pixelcode	code;
> +
> +	int bufnum;
> +};
> +
> +static void mx2_camera_deactivate(struct mx2_camera_dev *pcdev)
> +{
> +	unsigned long flags;
> +
> +	clk_disable(pcdev->clk_csi);
> +	writel(0, pcdev->base_csi + CSICR1);
> +	if (mx27_camera_emma(pcdev)) {
> +		writel(0, pcdev->base_emma + PRP_CNTL);
> +	} else if (cpu_is_mx25()) {
> +		spin_lock_irqsave(&pcdev->lock, flags);
> +		pcdev->fb1_active = NULL;
> +		pcdev->fb2_active = NULL;
> +		writel(0, pcdev->base_csi + CSIDMASA_FB1);
> +		writel(0, pcdev->base_csi + CSIDMASA_FB2);
> +		spin_unlock_irqrestore(&pcdev->lock, flags);
> +	}
> +}
> +
> +/*
> + * The following two functions absolutely depend on the fact, that
> + * there can be only one camera on mx2 camera sensor interface
> + */
> +static int mx2_camera_add_device(struct soc_camera_device *icd)
> +{
> +	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
> +	struct mx2_camera_dev *pcdev = ici->priv;
> +	int ret;
> +	u32 csicr1;
> +
> +	if (pcdev->icd)
> +		return -EBUSY;
> +
> +	ret = clk_enable(pcdev->clk_csi);
> +	if (ret < 0)
> +		return ret;
> +
> +	csicr1 = CSICR1_MCLKEN;
> +
> +	if (mx27_camera_emma(pcdev)) {
> +		csicr1 |= CSICR1_PRP_IF_EN | CSICR1_FCC |
> +			CSICR1_RXFF_LEVEL(0);
> +	} else if (cpu_is_mx27())
> +		csicr1 |= CSICR1_SOF_INTEN | CSICR1_RXFF_LEVEL(2);
> +
> +	pcdev->csicr1 = csicr1;
> +	writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
> +
> +	pcdev->icd = icd;
> +
> +	dev_info(icd->dev.parent, "Camera driver attached to camera %d\n",
> +		 icd->devnum);
> +
> +	return 0;
> +}
> +
> +static void mx2_camera_remove_device(struct soc_camera_device *icd)
> +{
> +	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
> +	struct mx2_camera_dev *pcdev = ici->priv;
> +
> +	BUG_ON(icd != pcdev->icd);
> +
> +	dev_info(icd->dev.parent, "Camera driver detached from camera %d\n",
> +		 icd->devnum);
> +
> +	mx2_camera_deactivate(pcdev);
> +
> +	if (pcdev->discard_buffer) {
> +		dma_free_coherent(ici->v4l2_dev.dev, pcdev->discard_size,
> +				pcdev->discard_buffer,
> +				pcdev->discard_buffer_dma);
> +		pcdev->discard_buffer = NULL;
> +	}
> +
> +	pcdev->icd = NULL;
> +}
> +
> +static void mx27_camera_dma_enable(struct mx2_camera_dev *pcdev)
> +{
> +	u32 tmp;
> +
> +	imx_dma_enable(pcdev->dma);
> +
> +	tmp = readl(pcdev->base_csi + CSICR1);
> +	tmp |= CSICR1_RF_OR_INTEN;
> +	writel(tmp, pcdev->base_csi + CSICR1);
> +}
> +
> +static irqreturn_t mx27_camera_irq(int irq_csi, void *data)
> +{
> +	struct mx2_camera_dev *pcdev = data;
> +	u32 status = readl(pcdev->base_csi + CSISR);
> +
> +	if (status & CSISR_SOF_INT && pcdev->active) {
> +		u32 tmp;
> +
> +		tmp = readl(pcdev->base_csi + CSICR1);
> +		writel(tmp | CSICR1_CLR_RXFIFO, pcdev->base_csi + CSICR1);
> +		mx27_camera_dma_enable(pcdev);
> +	}
> +
> +	writel(CSISR_SOF_INT | CSISR_RFF_OR_INT, pcdev->base_csi + CSISR);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static void mx25_camera_frame_done(struct mx2_camera_dev *pcdev, int fb,
> +		int state)
> +{
> +	struct videobuf_buffer *vb;
> +	struct mx2_buffer *buf;
> +	struct mx2_buffer **fb_active = fb == 1 ? &pcdev->fb1_active :
> +		&pcdev->fb2_active;
> +	u32 fb_reg = fb == 1 ? CSIDMASA_FB1 : CSIDMASA_FB2;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&pcdev->lock, flags);
> +
> +	vb = &(*fb_active)->vb;
> +	dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
> +		vb, vb->baddr, vb->bsize);
> +
> +	vb->state = state;
> +	do_gettimeofday(&vb->ts);
> +	vb->field_count++;
> +
> +	wake_up(&vb->done);
> +
> +	if (list_empty(&pcdev->capture)) {
> +		buf = NULL;
> +		writel(0, pcdev->base_csi + fb_reg);
> +	} else {
> +		buf = list_entry(pcdev->capture.next, struct mx2_buffer,
> +				vb.queue);
> +		vb = &buf->vb;
> +		list_del(&vb->queue);
> +		vb->state = VIDEOBUF_ACTIVE;
> +		writel(videobuf_to_dma_contig(vb), pcdev->base_csi + fb_reg);
> +	}
> +
> +	*fb_active = buf;
> +
> +	spin_unlock_irqrestore(&pcdev->lock, flags);
> +}
> +
> +static irqreturn_t mx25_camera_irq(int irq_csi, void *data)
> +{
> +	struct mx2_camera_dev *pcdev = data;
> +	u32 status = readl(pcdev->base_csi + CSISR);
> +
> +	if (status & CSISR_DMA_TSF_FB1_INT)
> +		mx25_camera_frame_done(pcdev, 1, VIDEOBUF_DONE);
> +	else if (status & CSISR_DMA_TSF_FB2_INT)
> +		mx25_camera_frame_done(pcdev, 2, VIDEOBUF_DONE);
> +
> +	/* FIXME: handle CSISR_RFF_OR_INT */
> +
> +	writel(status, pcdev->base_csi + CSISR);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +/*
> + *  Videobuf operations
> + */
> +static int mx2_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
> +			      unsigned int *size)
> +{
> +	struct soc_camera_device *icd = vq->priv_data;
> +	int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
> +			icd->current_fmt->host_fmt);
> +
> +	dev_dbg(&icd->dev, "count=%d, size=%d\n", *count, *size);
> +
> +	if (bytes_per_line < 0)
> +		return bytes_per_line;
> +
> +	*size = bytes_per_line * icd->user_height;
> +
> +	if (0 == *count)
> +		*count = 32;
> +	if (*size * *count > MAX_VIDEO_MEM * 1024 * 1024)
> +		*count = (MAX_VIDEO_MEM * 1024 * 1024) / *size;
> +
> +	return 0;
> +}
> +
> +static void free_buffer(struct videobuf_queue *vq, struct mx2_buffer *buf)
> +{
> +	struct soc_camera_device *icd = vq->priv_data;
> +	struct videobuf_buffer *vb = &buf->vb;
> +
> +	dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
> +		vb, vb->baddr, vb->bsize);
> +
> +	/*
> +	 * This waits until this buffer is out of danger, i.e., until it is no
> +	 * longer in STATE_QUEUED or STATE_ACTIVE
> +	 */
> +	videobuf_waiton(vb, 0, 0);
> +
> +	videobuf_dma_contig_free(vq, vb);
> +	dev_dbg(&icd->dev, "%s freed\n", __func__);
> +
> +	vb->state = VIDEOBUF_NEEDS_INIT;
> +}
> +
> +static int mx2_videobuf_prepare(struct videobuf_queue *vq,
> +		struct videobuf_buffer *vb, enum v4l2_field field)
> +{
> +	struct soc_camera_device *icd = vq->priv_data;
> +	struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
> +	int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
> +			icd->current_fmt->host_fmt);
> +	int ret = 0;
> +
> +	dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
> +		vb, vb->baddr, vb->bsize);
> +
> +	if (bytes_per_line < 0)
> +		return bytes_per_line;
> +
> +#ifdef DEBUG
> +	/*
> +	 * This can be useful if you want to see if we actually fill
> +	 * the buffer with something
> +	 */
> +	memset((void *)vb->baddr, 0xaa, vb->bsize);
> +#endif
> +
> +	if (buf->code	!= icd->current_fmt->code ||
> +	    vb->width	!= icd->user_width ||
> +	    vb->height	!= icd->user_height ||
> +	    vb->field	!= field) {
> +		buf->code	= icd->current_fmt->code;
> +		vb->width	= icd->user_width;
> +		vb->height	= icd->user_height;
> +		vb->field	= field;
> +		vb->state	= VIDEOBUF_NEEDS_INIT;
> +	}
> +
> +	vb->size = bytes_per_line * vb->height;
> +	if (vb->baddr && vb->bsize < vb->size) {
> +		ret = -EINVAL;
> +		goto out;
> +	}
> +
> +	if (vb->state == VIDEOBUF_NEEDS_INIT) {
> +		ret = videobuf_iolock(vq, vb, NULL);
> +		if (ret)
> +			goto fail;
> +
> +		vb->state = VIDEOBUF_PREPARED;
> +	}
> +
> +	return 0;
> +
> +fail:
> +	free_buffer(vq, buf);
> +out:
> +	return ret;
> +}
> +
> +static void mx2_videobuf_queue(struct videobuf_queue *vq,
> +			       struct videobuf_buffer *vb)
> +{
> +	struct soc_camera_device *icd = vq->priv_data;
> +	struct soc_camera_host *ici =
> +		to_soc_camera_host(icd->dev.parent);
> +	struct mx2_camera_dev *pcdev = ici->priv;
> +	struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
> +	unsigned long flags;
> +	int ret;
> +
> +	dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
> +		vb, vb->baddr, vb->bsize);
> +
> +	spin_lock_irqsave(&pcdev->lock, flags);
> +
> +	vb->state = VIDEOBUF_QUEUED;
> +	list_add_tail(&vb->queue, &pcdev->capture);
> +
> +	if (mx27_camera_emma(pcdev)) {
> +		goto out;
> +	} else if (cpu_is_mx27()) {
> +		if (pcdev->active == NULL) {
> +			ret = imx_dma_setup_single(pcdev->dma,
> +					videobuf_to_dma_contig(vb), vb->size,
> +					(u32)pcdev->base_dma + 0x10,
> +					DMA_MODE_READ);
> +			if (ret) {
> +				vb->state = VIDEOBUF_ERROR;
> +				wake_up(&vb->done);
> +				goto out;
> +			}
> +
> +			vb->state = VIDEOBUF_ACTIVE;
> +			pcdev->active = buf;
> +		}
> +	} else { /* cpu_is_mx25() */
> +		u32 csicr3, dma_inten = 0;
> +
> +		if (pcdev->fb1_active == NULL) {
> +			writel(videobuf_to_dma_contig(vb),
> +					pcdev->base_csi + CSIDMASA_FB1);
> +			pcdev->fb1_active = buf;
> +			dma_inten = CSICR1_FB1_DMA_INTEN;
> +		} else if (pcdev->fb2_active == NULL) {
> +			writel(videobuf_to_dma_contig(vb),
> +					pcdev->base_csi + CSIDMASA_FB2);
> +			pcdev->fb2_active = buf;
> +			dma_inten = CSICR1_FB2_DMA_INTEN;
> +		}
> +
> +		if (dma_inten) {
> +			list_del(&vb->queue);
> +			vb->state = VIDEOBUF_ACTIVE;
> +
> +			csicr3 = readl(pcdev->base_csi + CSICR3);
> +
> +			/* Reflash DMA */
> +			writel(csicr3 | CSICR3_DMA_REFLASH_RFF,
> +					pcdev->base_csi + CSICR3);
> +
> +			/* clear & enable interrupts */
> +			writel(dma_inten, pcdev->base_csi + CSISR);
> +			pcdev->csicr1 |= dma_inten;
> +			writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
> +
> +			/* enable DMA */
> +			csicr3 |= CSICR3_DMA_REQ_EN_RFF | CSICR3_RXFF_LEVEL(1);
> +			writel(csicr3, pcdev->base_csi + CSICR3);
> +		}
> +	}
> +
> +out:
> +	spin_unlock_irqrestore(&pcdev->lock, flags);
> +}
> +
> +static void mx2_videobuf_release(struct videobuf_queue *vq,
> +				 struct videobuf_buffer *vb)
> +{
> +	struct soc_camera_device *icd = vq->priv_data;
> +	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
> +	struct mx2_camera_dev *pcdev = ici->priv;
> +	struct mx2_buffer *buf = container_of(vb, struct mx2_buffer, vb);
> +	unsigned long flags;
> +
> +#ifdef DEBUG
> +	dev_dbg(&icd->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
> +		vb, vb->baddr, vb->bsize);
> +
> +	switch (vb->state) {
> +	case VIDEOBUF_ACTIVE:
> +		dev_info(&icd->dev, "%s (active)\n", __func__);
> +		break;
> +	case VIDEOBUF_QUEUED:
> +		dev_info(&icd->dev, "%s (queued)\n", __func__);
> +		break;
> +	case VIDEOBUF_PREPARED:
> +		dev_info(&icd->dev, "%s (prepared)\n", __func__);
> +		break;
> +	default:
> +		dev_info(&icd->dev, "%s (unknown) %d\n", __func__,
> +				vb->state);
> +		break;
> +	}
> +#endif
> +
> +	/*
> +	 * Terminate only queued but inactive buffers. Active buffers are
> +	 * released when they become inactive after videobuf_waiton().
> +	 *
> +	 * FIXME: implement forced termination of active buffers, so that the
> +	 * user won't get stuck in an uninterruptible state. This requires a
> +	 * specific handling for each of the three DMA types that this driver
> +	 * supports.
> +	 */
> +	spin_lock_irqsave(&pcdev->lock, flags);
> +	if (vb->state == VIDEOBUF_QUEUED) {
> +		list_del(&vb->queue);
> +		vb->state = VIDEOBUF_ERROR;
> +	}
> +	spin_unlock_irqrestore(&pcdev->lock, flags);
> +
> +	free_buffer(vq, buf);
> +}
> +
> +static struct videobuf_queue_ops mx2_videobuf_ops = {
> +	.buf_setup      = mx2_videobuf_setup,
> +	.buf_prepare    = mx2_videobuf_prepare,
> +	.buf_queue      = mx2_videobuf_queue,
> +	.buf_release    = mx2_videobuf_release,
> +};
> +
> +static void mx2_camera_init_videobuf(struct videobuf_queue *q,
> +			      struct soc_camera_device *icd)
> +{
> +	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
> +	struct mx2_camera_dev *pcdev = ici->priv;
> +
> +	videobuf_queue_dma_contig_init(q, &mx2_videobuf_ops, pcdev->dev,
> +			&pcdev->lock, V4L2_BUF_TYPE_VIDEO_CAPTURE,
> +			V4L2_FIELD_NONE, sizeof(struct mx2_buffer), icd);
> +}
> +
> +#define MX2_BUS_FLAGS	(SOCAM_DATAWIDTH_8 | \
> +			SOCAM_MASTER | \
> +			SOCAM_VSYNC_ACTIVE_HIGH | \
> +			SOCAM_VSYNC_ACTIVE_LOW | \
> +			SOCAM_HSYNC_ACTIVE_HIGH | \
> +			SOCAM_HSYNC_ACTIVE_LOW | \
> +			SOCAM_PCLK_SAMPLE_RISING | \
> +			SOCAM_PCLK_SAMPLE_FALLING | \
> +			SOCAM_DATA_ACTIVE_HIGH | \
> +			SOCAM_DATA_ACTIVE_LOW)
> +
> +static int mx27_camera_emma_prp_reset(struct mx2_camera_dev *pcdev)
> +{
> +	u32 cntl;
> +	int count = 0;
> +
> +	cntl = readl(pcdev->base_emma + PRP_CNTL);
> +	writel(PRP_CNTL_SWRST, pcdev->base_emma + PRP_CNTL);
> +	while (count++ < 100) {
> +		if (!(readl(pcdev->base_emma + PRP_CNTL) & PRP_CNTL_SWRST))
> +			return 0;
> +		barrier();
> +		udelay(1);
> +	}
> +
> +	return -ETIMEDOUT;
> +}
> +
> +static void mx27_camera_emma_buf_init(struct soc_camera_device *icd,
> +		int bytesperline)
> +{
> +	struct soc_camera_host *ici =
> +		to_soc_camera_host(icd->dev.parent);
> +	struct mx2_camera_dev *pcdev = ici->priv;
> +
> +	writel(pcdev->discard_buffer_dma,
> +			pcdev->base_emma + PRP_DEST_RGB1_PTR);
> +	writel(pcdev->discard_buffer_dma,
> +			pcdev->base_emma + PRP_DEST_RGB2_PTR);
> +
> +	/*
> +	 * We only use the EMMA engine to get rid of the broken
> +	 * DMA Engine. No color space consversion at the moment.
> +	 * We adjust incoming and outgoing pixelformat to rgb16
> +	 * and adjust the bytesperline accordingly.
> +	 */
> +	writel(PRP_CNTL_CH1EN |
> +			PRP_CNTL_CSIEN |
> +			PRP_CNTL_DATA_IN_RGB16 |
> +			PRP_CNTL_CH1_OUT_RGB16 |
> +			PRP_CNTL_CH1_LEN |
> +			PRP_CNTL_CH1BYP |
> +			PRP_CNTL_CH1_TSKIP(0) |
> +			PRP_CNTL_IN_TSKIP(0),
> +			pcdev->base_emma + PRP_CNTL);
> +
> +	writel(((bytesperline >> 1) << 16) | icd->user_height,
> +			pcdev->base_emma + PRP_SRC_FRAME_SIZE);
> +	writel(((bytesperline >> 1) << 16) | icd->user_height,
> +			pcdev->base_emma + PRP_CH1_OUT_IMAGE_SIZE);
> +	writel(bytesperline,
> +			pcdev->base_emma + PRP_DEST_CH1_LINE_STRIDE);
> +	writel(0x2ca00565, /* RGB565 */
> +			pcdev->base_emma + PRP_SRC_PIXEL_FORMAT_CNTL);
> +	writel(0x2ca00565, /* RGB565 */
> +			pcdev->base_emma + PRP_CH1_PIXEL_FORMAT_CNTL);
> +
> +	/* Enable interrupts */
> +	writel(PRP_INTR_RDERR |
> +			PRP_INTR_CH1WERR |
> +			PRP_INTR_CH2WERR |
> +			PRP_INTR_CH1FC |
> +			PRP_INTR_CH2FC |
> +			PRP_INTR_LBOVF |
> +			PRP_INTR_CH2OVF,
> +			pcdev->base_emma + PRP_INTR_CNTL);
> +}
> +
> +static int mx2_camera_set_bus_param(struct soc_camera_device *icd,
> +		__u32 pixfmt)
> +{
> +	struct soc_camera_host *ici =
> +		to_soc_camera_host(icd->dev.parent);
> +	struct mx2_camera_dev *pcdev = ici->priv;
> +	unsigned long camera_flags, common_flags;
> +	int ret = 0;
> +	int bytesperline;
> +	u32 csicr1 = pcdev->csicr1;
> +
> +	camera_flags = icd->ops->query_bus_param(icd);
> +
> +	common_flags = soc_camera_bus_param_compatible(camera_flags,
> +				MX2_BUS_FLAGS);
> +	if (!common_flags)
> +		return -EINVAL;
> +
> +	if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
> +	    (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
> +		if (pcdev->platform_flags & MX2_CAMERA_HSYNC_HIGH)
> +			common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
> +		else
> +			common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
> +	}
> +
> +	if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
> +	    (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
> +		if (pcdev->platform_flags & MX2_CAMERA_PCLK_SAMPLE_RISING)
> +			common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
> +		else
> +			common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
> +	}
> +
> +	ret = icd->ops->set_bus_param(icd, common_flags);
> +	if (ret < 0)
> +		return ret;
> +
> +	if (common_flags & SOCAM_PCLK_SAMPLE_FALLING)
> +		csicr1 |= CSICR1_INV_PCLK;
> +	if (common_flags & SOCAM_VSYNC_ACTIVE_HIGH)
> +		csicr1 |= CSICR1_SOF_POL;
> +	if (common_flags & SOCAM_HSYNC_ACTIVE_HIGH)
> +		csicr1 |= CSICR1_HSYNC_POL;
> +	if (pcdev->platform_flags & MX2_CAMERA_SWAP16)
> +		csicr1 |= CSICR1_SWAP16_EN;
> +	if (pcdev->platform_flags & MX2_CAMERA_EXT_VSYNC)
> +		csicr1 |= CSICR1_EXT_VSYNC;
> +	if (pcdev->platform_flags & MX2_CAMERA_CCIR)
> +		csicr1 |= CSICR1_CCIR_EN;
> +	if (pcdev->platform_flags & MX2_CAMERA_CCIR_INTERLACE)
> +		csicr1 |= CSICR1_CCIR_MODE;
> +	if (pcdev->platform_flags & MX2_CAMERA_GATED_CLOCK)
> +		csicr1 |= CSICR1_GCLK_MODE;
> +	if (pcdev->platform_flags & MX2_CAMERA_INV_DATA)
> +		csicr1 |= CSICR1_INV_DATA;
> +	if (pcdev->platform_flags & MX2_CAMERA_PACK_DIR_MSB)
> +		csicr1 |= CSICR1_PACK_DIR;
> +
> +	pcdev->csicr1 = csicr1;
> +
> +	bytesperline = soc_mbus_bytes_per_line(icd->user_width,
> +			icd->current_fmt->host_fmt);
> +	if (bytesperline < 0)
> +		return bytesperline;
> +
> +	if (mx27_camera_emma(pcdev)) {
> +		ret = mx27_camera_emma_prp_reset(pcdev);
> +		if (ret)
> +			return ret;
> +
> +		if (pcdev->discard_buffer)
> +			dma_free_coherent(ici->v4l2_dev.dev,
> +				pcdev->discard_size, pcdev->discard_buffer,
> +				pcdev->discard_buffer_dma);
> +
> +		/*
> +		 * I didn't manage to properly enable/disable the prp
> +		 * on a per frame basis during running transfers,
> +		 * thus we allocate a buffer here and use it to
> +		 * discard frames when no buffer is available.
> +		 * Feel free to work on this ;)
> +		 */
> +		pcdev->discard_size = icd->user_height * bytesperline;
> +		pcdev->discard_buffer = dma_alloc_coherent(ici->v4l2_dev.dev,
> +				pcdev->discard_size, &pcdev->discard_buffer_dma,
> +				GFP_KERNEL);
> +		if (!pcdev->discard_buffer)
> +			return -ENOMEM;
> +
> +		mx27_camera_emma_buf_init(icd, bytesperline);
> +	} else if (cpu_is_mx25()) {
> +		writel((bytesperline * icd->user_height) >> 2,
> +				pcdev->base_csi + CSIRXCNT);
> +		writel((bytesperline << 16) | icd->user_height,
> +				pcdev->base_csi + CSIIMAG_PARA);
> +	}
> +
> +	writel(pcdev->csicr1, pcdev->base_csi + CSICR1);
> +
> +	return 0;
> +}
> +
> +static int mx2_camera_set_crop(struct soc_camera_device *icd,
> +				struct v4l2_crop *a)
> +{
> +	struct v4l2_rect *rect = &a->c;
> +	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
> +	struct v4l2_mbus_framefmt mf;
> +	int ret;
> +
> +	soc_camera_limit_side(&rect->left, &rect->width, 0, 2, 4096);
> +	soc_camera_limit_side(&rect->top, &rect->height, 0, 2, 4096);
> +
> +	ret = v4l2_subdev_call(sd, video, s_crop, a);
> +	if (ret < 0)
> +		return ret;
> +
> +	/* The capture device might have changed its output  */
> +	ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
> +	if (ret < 0)
> +		return ret;
> +
> +	dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n",
> +		mf.width, mf.height);
> +
> +	icd->user_width		= mf.width;
> +	icd->user_height	= mf.height;
> +
> +	return ret;
> +}
> +
> +static int mx2_camera_set_fmt(struct soc_camera_device *icd,
> +			       struct v4l2_format *f)
> +{
> +	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
> +	struct mx2_camera_dev *pcdev = ici->priv;
> +	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
> +	const struct soc_camera_format_xlate *xlate;
> +	struct v4l2_pix_format *pix = &f->fmt.pix;
> +	struct v4l2_mbus_framefmt mf;
> +	int ret;
> +
> +	xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
> +	if (!xlate) {
> +		dev_warn(icd->dev.parent, "Format %x not found\n",
> +				pix->pixelformat);
> +		return -EINVAL;
> +	}
> +
> +	/* eMMA can only do RGB565 */
> +	if (mx27_camera_emma(pcdev) && pix->pixelformat != V4L2_PIX_FMT_RGB565)
> +		return -EINVAL;
> +
> +	mf.width	= pix->width;
> +	mf.height	= pix->height;
> +	mf.field	= pix->field;
> +	mf.colorspace	= pix->colorspace;
> +	mf.code		= xlate->code;
> +
> +	ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
> +	if (ret < 0 && ret != -ENOIOCTLCMD)
> +		return ret;
> +
> +	if (mf.code != xlate->code)
> +		return -EINVAL;
> +
> +	pix->width		= mf.width;
> +	pix->height		= mf.height;
> +	pix->field		= mf.field;
> +	pix->colorspace		= mf.colorspace;
> +	icd->current_fmt	= xlate;
> +
> +	return 0;
> +}
> +
> +static int mx2_camera_try_fmt(struct soc_camera_device *icd,
> +				  struct v4l2_format *f)
> +{
> +	struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
> +	struct mx2_camera_dev *pcdev = ici->priv;
> +	struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
> +	const struct soc_camera_format_xlate *xlate;
> +	struct v4l2_pix_format *pix = &f->fmt.pix;
> +	struct v4l2_mbus_framefmt mf;
> +	__u32 pixfmt = pix->pixelformat;
> +	unsigned int width_limit;
> +	int ret;
> +
> +	xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
> +	if (pixfmt && !xlate) {
> +		dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt);
> +		return -EINVAL;
> +	}
> +
> +	/* FIXME: implement MX27 limits */
> +
> +	/* eMMA can only do RGB565 */
> +	if (mx27_camera_emma(pcdev) && pixfmt != V4L2_PIX_FMT_RGB565)
> +		return -EINVAL;
> +
> +	/* limit to MX25 hardware capabilities */
> +	if (cpu_is_mx25()) {
> +		if (xlate->host_fmt->bits_per_sample <= 8)
> +			width_limit = 0xffff * 4;
> +		else
> +			width_limit = 0xffff * 2;
> +		/* CSIIMAG_PARA limit */
> +		if (pix->width > width_limit)
> +			pix->width = width_limit;
> +		if (pix->height > 0xffff)
> +			pix->height = 0xffff;
> +
> +		pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
> +				xlate->host_fmt);
> +		if (pix->bytesperline < 0)
> +			return pix->bytesperline;
> +		pix->sizeimage = pix->height * pix->bytesperline;
> +		if (pix->sizeimage > (4 * 0x3ffff)) { /* CSIRXCNT limit */
> +			dev_warn(icd->dev.parent,
> +					"Image size (%u) above limit\n",
> +					pix->sizeimage);
> +			return -EINVAL;
> +		}
> +	}
> +
> +	/* limit to sensor capabilities */
> +	mf.width	= pix->width;
> +	mf.height	= pix->height;
> +	mf.field	= pix->field;
> +	mf.colorspace	= pix->colorspace;
> +	mf.code		= xlate->code;
> +
> +	ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
> +	if (ret < 0)
> +		return ret;
> +
> +	if (mf.field == V4L2_FIELD_ANY)
> +		mf.field = V4L2_FIELD_NONE;
> +	if (mf.field != V4L2_FIELD_NONE) {
> +		dev_err(icd->dev.parent, "Field type %d unsupported.\n",
> +				mf.field);
> +		return -EINVAL;
> +	}
> +
> +	pix->width	= mf.width;
> +	pix->height	= mf.height;
> +	pix->field	= mf.field;
> +	pix->colorspace	= mf.colorspace;
> +
> +	return 0;
> +}
> +
> +static int mx2_camera_querycap(struct soc_camera_host *ici,
> +			       struct v4l2_capability *cap)
> +{
> +	/* cap->name is set by the friendly caller:-> */
> +	strlcpy(cap->card, MX2_CAM_DRIVER_DESCRIPTION, sizeof(cap->card));
> +	cap->version = MX2_CAM_VERSION_CODE;
> +	cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
> +
> +	return 0;
> +}
> +
> +static int mx2_camera_reqbufs(struct soc_camera_file *icf,
> +			      struct v4l2_requestbuffers *p)
> +{
> +	int i;
> +
> +	for (i = 0; i < p->count; i++) {
> +		struct mx2_buffer *buf = container_of(icf->vb_vidq.bufs[i],
> +						      struct mx2_buffer, vb);
> +		INIT_LIST_HEAD(&buf->vb.queue);
> +	}
> +
> +	return 0;
> +}
> +
> +static void mx27_camera_frame_done(struct mx2_camera_dev *pcdev, int state)
> +{
> +	struct videobuf_buffer *vb;
> +	struct mx2_buffer *buf;
> +	unsigned long flags;
> +	int ret;
> +
> +	spin_lock_irqsave(&pcdev->lock, flags);
> +
> +	if (!pcdev->active) {
> +		dev_err(pcdev->dev, "%s called with no active buffer!\n",
> +				__func__);
> +		goto out;
> +	}
> +
> +	vb = &pcdev->active->vb;
> +	buf = container_of(vb, struct mx2_buffer, vb);
> +	WARN_ON(list_empty(&vb->queue));
> +	dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
> +		vb, vb->baddr, vb->bsize);
> +
> +	/* _init is used to debug races, see comment in pxa_camera_reqbufs() */
> +	list_del_init(&vb->queue);
> +	vb->state = state;
> +	do_gettimeofday(&vb->ts);
> +	vb->field_count++;
> +
> +	wake_up(&vb->done);
> +
> +	if (list_empty(&pcdev->capture)) {
> +		pcdev->active = NULL;
> +		goto out;
> +	}
> +
> +	pcdev->active = list_entry(pcdev->capture.next,
> +			struct mx2_buffer, vb.queue);
> +
> +	vb = &pcdev->active->vb;
> +	vb->state = VIDEOBUF_ACTIVE;
> +
> +	ret = imx_dma_setup_single(pcdev->dma, videobuf_to_dma_contig(vb),
> +			vb->size, (u32)pcdev->base_dma + 0x10, DMA_MODE_READ);
> +
> +	if (ret) {
> +		vb->state = VIDEOBUF_ERROR;
> +		pcdev->active = NULL;
> +		wake_up(&vb->done);
> +	}
> +
> +out:
> +	spin_unlock_irqrestore(&pcdev->lock, flags);
> +}
> +
> +static void mx27_camera_dma_err_callback(int channel, void *data, int err)
> +{
> +	struct mx2_camera_dev *pcdev = data;
> +
> +	mx27_camera_frame_done(pcdev, VIDEOBUF_ERROR);
> +}
> +
> +static void mx27_camera_dma_callback(int channel, void *data)
> +{
> +	struct mx2_camera_dev *pcdev = data;
> +
> +	mx27_camera_frame_done(pcdev, VIDEOBUF_DONE);
> +}
> +
> +#define DMA_REQ_CSI_RX          31 /* FIXME: Add this to a resource */
> +
> +static int __devinit mx27_camera_dma_init(struct platform_device *pdev,
> +		struct mx2_camera_dev *pcdev)
> +{
> +	int err;
> +
> +	pcdev->dma = imx_dma_request_by_prio("CSI RX DMA", DMA_PRIO_HIGH);
> +	if (pcdev->dma < 0) {
> +		dev_err(&pdev->dev, "%s failed to request DMA channel\n",
> +				__func__);
> +		return pcdev->dma;
> +	}
> +
> +	err = imx_dma_setup_handlers(pcdev->dma, mx27_camera_dma_callback,
> +					mx27_camera_dma_err_callback, pcdev);
> +	if (err) {
> +		dev_err(&pdev->dev, "%s failed to set DMA callback\n",
> +				__func__);
> +		goto err_out;
> +	}
> +
> +	err = imx_dma_config_channel(pcdev->dma,
> +			IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO,
> +			IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR,
> +			DMA_REQ_CSI_RX, 1);
> +	if (err) {
> +		dev_err(&pdev->dev, "%s failed to config DMA channel\n",
> +				__func__);
> +		goto err_out;
> +	}
> +
> +	imx_dma_config_burstlen(pcdev->dma, 64);
> +
> +	return 0;
> +
> +err_out:
> +	imx_dma_free(pcdev->dma);
> +
> +	return err;
> +}
> +
> +static unsigned int mx2_camera_poll(struct file *file, poll_table *pt)
> +{
> +	struct soc_camera_file *icf = file->private_data;
> +
> +	return videobuf_poll_stream(file, &icf->vb_vidq, pt);
> +}
> +
> +static struct soc_camera_host_ops mx2_soc_camera_host_ops = {
> +	.owner		= THIS_MODULE,
> +	.add		= mx2_camera_add_device,
> +	.remove		= mx2_camera_remove_device,
> +	.set_fmt	= mx2_camera_set_fmt,
> +	.set_crop	= mx2_camera_set_crop,
> +	.try_fmt	= mx2_camera_try_fmt,
> +	.init_videobuf	= mx2_camera_init_videobuf,
> +	.reqbufs	= mx2_camera_reqbufs,
> +	.poll		= mx2_camera_poll,
> +	.querycap	= mx2_camera_querycap,
> +	.set_bus_param	= mx2_camera_set_bus_param,
> +};
> +
> +static void mx27_camera_frame_done_emma(struct mx2_camera_dev *pcdev,
> +		int bufnum, int state)
> +{
> +	struct mx2_buffer *buf;
> +	struct videobuf_buffer *vb;
> +	unsigned long phys;
> +
> +	if (!list_empty(&pcdev->active_bufs)) {
> +		buf = list_entry(pcdev->active_bufs.next,
> +			struct mx2_buffer, vb.queue);
> +
> +		BUG_ON(buf->bufnum != bufnum);
> +
> +		vb = &buf->vb;
> +#ifdef DEBUG
> +		phys = videobuf_to_dma_contig(vb);
> +		if (readl(pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum)
> +				!= phys) {
> +			dev_err(pcdev->dev, "%p != %p\n", phys,
> +					readl(pcdev->base_emma +
> +						PRP_DEST_RGB1_PTR +
> +						4 * bufnum));
> +		}
> +#endif
> +		dev_dbg(pcdev->dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__, vb,
> +				vb->baddr, vb->bsize);
> +
> +		list_del(&vb->queue);
> +		vb->state = state;
> +		do_gettimeofday(&vb->ts);
> +		vb->field_count++;
> +
> +		wake_up(&vb->done);
> +	}
> +
> +	if (list_empty(&pcdev->capture)) {
> +		writel(pcdev->discard_buffer_dma, pcdev->base_emma +
> +				PRP_DEST_RGB1_PTR + 4 * bufnum);
> +		return;
> +	}
> +
> +	buf = list_entry(pcdev->capture.next,
> +			struct mx2_buffer, vb.queue);
> +
> +	buf->bufnum = bufnum;
> +
> +	list_move_tail(pcdev->capture.next, &pcdev->active_bufs);
> +
> +	vb = &buf->vb;
> +	vb->state = VIDEOBUF_ACTIVE;
> +
> +	phys = videobuf_to_dma_contig(vb);
> +	writel(phys, pcdev->base_emma + PRP_DEST_RGB1_PTR + 4 * bufnum);
> +}
> +
> +static irqreturn_t mx27_camera_emma_irq(int irq_emma, void *data)
> +{
> +	struct mx2_camera_dev *pcdev = data;
> +	unsigned int status = readl(pcdev->base_emma + PRP_INTRSTATUS);
> +	struct mx2_buffer *buf;
> +
> +	if (status & (1 << 7)) { /* overflow */
> +		u32 cntl;
> +		/*
> +		 * We only disable channel 1 here since this is the only
> +		 * enabled channel
> +		 *
> +		 * FIXME: the correct DMA overflow handling should be resetting
> +		 * the buffer, returning an error frame, and continuing with
> +		 * the next one.
> +		 */
> +		cntl = readl(pcdev->base_emma + PRP_CNTL);
> +		writel(cntl & ~PRP_CNTL_CH1EN, pcdev->base_emma + PRP_CNTL);
> +		writel(cntl, pcdev->base_emma + PRP_CNTL);
> +	}
> +	if ((status & (3 << 5)) == (3 << 5)
> +			&& !list_empty(&pcdev->active_bufs)) {
> +		/*
> +		 * Both buffers have triggered, process the one we're expecting
> +		 * to first
> +		 */
> +		buf = list_entry(pcdev->active_bufs.next,
> +			struct mx2_buffer, vb.queue);
> +		mx27_camera_frame_done_emma(pcdev, buf->bufnum, VIDEOBUF_DONE);
> +		status &= ~(1 << (6 - buf->bufnum)); /* mark processed */
> +	}
> +	if (status & (1 << 6))
> +		mx27_camera_frame_done_emma(pcdev, 0, VIDEOBUF_DONE);
> +	if (status & (1 << 5))
> +		mx27_camera_frame_done_emma(pcdev, 1, VIDEOBUF_DONE);
> +
> +	writel(status, pcdev->base_emma + PRP_INTRSTATUS);
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static int __devinit mx27_camera_emma_init(struct mx2_camera_dev *pcdev)
> +{
> +	struct resource *res_emma = pcdev->res_emma;
> +	int err = 0;
> +
> +	if (!request_mem_region(res_emma->start, resource_size(res_emma),
> +				MX2_CAM_DRV_NAME)) {
> +		err = -EBUSY;
> +		goto out;
> +	}
> +
> +	pcdev->base_emma = ioremap(res_emma->start, resource_size(res_emma));
> +	if (!pcdev->base_emma) {
> +		err = -ENOMEM;
> +		goto exit_release;
> +	}
> +
> +	err = request_irq(pcdev->irq_emma, mx27_camera_emma_irq, 0,
> +			MX2_CAM_DRV_NAME, pcdev);
> +	if (err) {
> +		dev_err(pcdev->dev, "Camera EMMA interrupt register failed \n");
> +		goto exit_iounmap;
> +	}
> +
> +	pcdev->clk_emma = clk_get(NULL, "emma");
> +	if (IS_ERR(pcdev->clk_emma)) {
> +		err = PTR_ERR(pcdev->clk_emma);
> +		goto exit_free_irq;
> +	}
> +
> +	clk_enable(pcdev->clk_emma);
> +
> +	err = mx27_camera_emma_prp_reset(pcdev);
> +	if (err)
> +		goto exit_clk_emma_put;
> +
> +	return err;
> +
> +exit_clk_emma_put:
> +	clk_disable(pcdev->clk_emma);
> +	clk_put(pcdev->clk_emma);
> +exit_free_irq:
> +	free_irq(pcdev->irq_emma, pcdev);
> +exit_iounmap:
> +	iounmap(pcdev->base_emma);
> +exit_release:
> +	release_mem_region(res_emma->start, resource_size(res_emma));
> +out:
> +	return err;
> +}
> +
> +static int __devinit mx2_camera_probe(struct platform_device *pdev)
> +{
> +	struct mx2_camera_dev *pcdev;
> +	struct resource *res_csi, *res_emma;
> +	void __iomem *base_csi;
> +	int irq_csi, irq_emma;
> +	irq_handler_t mx2_cam_irq_handler = cpu_is_mx25() ? mx25_camera_irq
> +		: mx27_camera_irq;
> +	int err = 0;
> +
> +	dev_dbg(&pdev->dev, "initialising\n");
> +
> +	res_csi = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	irq_csi = platform_get_irq(pdev, 0);
> +	if (res_csi == NULL || irq_csi < 0) {
> +		dev_err(&pdev->dev, "Missing platform resources data\n");
> +		err = -ENODEV;
> +		goto exit;
> +	}
> +
> +	pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
> +	if (!pcdev) {
> +		dev_err(&pdev->dev, "Could not allocate pcdev\n");
> +		err = -ENOMEM;
> +		goto exit;
> +	}
> +
> +	pcdev->clk_csi = clk_get(&pdev->dev, NULL);
> +	if (IS_ERR(pcdev->clk_csi)) {
> +		err = PTR_ERR(pcdev->clk_csi);
> +		goto exit_kfree;
> +	}
> +
> +	dev_dbg(&pdev->dev, "Camera clock frequency: %ld\n",
> +			clk_get_rate(pcdev->clk_csi));
> +
> +	/* Initialize DMA */
> +	if (cpu_is_mx27()) {
> +		err = mx27_camera_dma_init(pdev, pcdev);
> +		if (err)
> +			goto exit_clk_put;
> +	}
> +
> +	pcdev->res_csi = res_csi;
> +	pcdev->pdata = pdev->dev.platform_data;
> +	if (pcdev->pdata) {
> +		long rate;
> +
> +		pcdev->platform_flags = pcdev->pdata->flags;
> +
> +		rate = clk_round_rate(pcdev->clk_csi, pcdev->pdata->clk * 2);
> +		if (rate <= 0) {
> +			err = -ENODEV;
> +			goto exit_dma_free;
> +		}
> +		err = clk_set_rate(pcdev->clk_csi, rate);
> +		if (err < 0)
> +			goto exit_dma_free;
> +	}
> +
> +	INIT_LIST_HEAD(&pcdev->capture);
> +	INIT_LIST_HEAD(&pcdev->active_bufs);
> +	spin_lock_init(&pcdev->lock);
> +
> +	/*
> +	 * Request the regions.
> +	 */
> +	if (!request_mem_region(res_csi->start, resource_size(res_csi),
> +				MX2_CAM_DRV_NAME)) {
> +		err = -EBUSY;
> +		goto exit_dma_free;
> +	}
> +
> +	base_csi = ioremap(res_csi->start, resource_size(res_csi));
> +	if (!base_csi) {
> +		err = -ENOMEM;
> +		goto exit_release;
> +	}
> +	pcdev->irq_csi = irq_csi;
> +	pcdev->base_csi = base_csi;
> +	pcdev->base_dma = res_csi->start;
> +	pcdev->dev = &pdev->dev;
> +
> +	err = request_irq(pcdev->irq_csi, mx2_cam_irq_handler, 0,
> +			MX2_CAM_DRV_NAME, pcdev);
> +	if (err) {
> +		dev_err(pcdev->dev, "Camera interrupt register failed \n");
> +		goto exit_iounmap;
> +	}
> +
> +	if (cpu_is_mx27()) {
> +		/* EMMA support */
> +		res_emma = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> +		irq_emma = platform_get_irq(pdev, 1);
> +
> +		if (res_emma && irq_emma >= 0) {
> +			dev_info(&pdev->dev, "Using EMMA\n");
> +			pcdev->use_emma = 1;
> +			pcdev->res_emma = res_emma;
> +			pcdev->irq_emma = irq_emma;
> +			if (mx27_camera_emma_init(pcdev))
> +				goto exit_free_irq;
> +		}
> +	}
> +
> +	pcdev->soc_host.drv_name	= MX2_CAM_DRV_NAME,
> +	pcdev->soc_host.ops		= &mx2_soc_camera_host_ops,
> +	pcdev->soc_host.priv		= pcdev;
> +	pcdev->soc_host.v4l2_dev.dev	= &pdev->dev;
> +	pcdev->soc_host.nr		= pdev->id;
> +	err = soc_camera_host_register(&pcdev->soc_host);
> +	if (err)
> +		goto exit_free_emma;
> +
> +	return 0;
> +
> +exit_free_emma:
> +	if (mx27_camera_emma(pcdev)) {
> +		free_irq(pcdev->irq_emma, pcdev);
> +		clk_disable(pcdev->clk_emma);
> +		clk_put(pcdev->clk_emma);
> +		iounmap(pcdev->base_emma);
> +		release_mem_region(res_emma->start, resource_size(res_emma));
> +	}
> +exit_free_irq:
> +	free_irq(pcdev->irq_csi, pcdev);
> +exit_iounmap:
> +	iounmap(base_csi);
> +exit_release:
> +	release_mem_region(res_csi->start, resource_size(res_csi));
> +exit_dma_free:
> +	if (cpu_is_mx27())
> +		imx_dma_free(pcdev->dma);
> +exit_clk_put:
> +	clk_put(pcdev->clk_csi);
> +exit_kfree:
> +	kfree(pcdev);
> +exit:
> +	return err;
> +}
> +
> +static int __devexit mx2_camera_remove(struct platform_device *pdev)
> +{
> +	struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
> +	struct mx2_camera_dev *pcdev = container_of(soc_host,
> +			struct mx2_camera_dev, soc_host);
> +	struct resource *res;
> +
> +	clk_put(pcdev->clk_csi);
> +	if (cpu_is_mx27())
> +		imx_dma_free(pcdev->dma);
> +	free_irq(pcdev->irq_csi, pcdev);
> +	if (mx27_camera_emma(pcdev))
> +		free_irq(pcdev->irq_emma, pcdev);
> +
> +	soc_camera_host_unregister(&pcdev->soc_host);
> +
> +	iounmap(pcdev->base_csi);
> +
> +	if (mx27_camera_emma(pcdev)) {
> +		clk_disable(pcdev->clk_emma);
> +		clk_put(pcdev->clk_emma);
> +		iounmap(pcdev->base_emma);
> +		res = pcdev->res_emma;
> +		release_mem_region(res->start, resource_size(res));
> +	}
> +
> +	res = pcdev->res_csi;
> +	release_mem_region(res->start, resource_size(res));
> +
> +	kfree(pcdev);
> +
> +	dev_info(&pdev->dev, "MX2 Camera driver unloaded\n");
> +
> +	return 0;
> +}
> +
> +static struct platform_driver mx2_camera_driver = {
> +	.driver 	= {
> +		.name	= MX2_CAM_DRV_NAME,
> +	},
> +	.remove		= __devexit_p(mx2_camera_remove),
> +};
> +
> +
> +static int __init mx2_camera_init(void)
> +{
> +	return platform_driver_probe(&mx2_camera_driver, &mx2_camera_probe);
> +}
> +
> +static void __exit mx2_camera_exit(void)
> +{
> +	return platform_driver_unregister(&mx2_camera_driver);
> +}
> +
> +module_init(mx2_camera_init);
> +module_exit(mx2_camera_exit);
> +
> +MODULE_DESCRIPTION("i.MX27/i.MX25 SoC Camera Host driver");
> +MODULE_AUTHOR("Sascha Hauer <sha at pengutronix.de>");
> +MODULE_LICENSE("GPL");
> -- 
> 1.7.1
> 

---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From linux at arm.linux.org.uk  Tue Jun 29 16:05:50 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Tue, 29 Jun 2010 21:05:50 +0100
Subject: soft lockup - CPU#0 stuck for 61s! problem
In-Reply-To: <AANLkTin-cXOIkMN9JXdPETP_aEjeCjF9qV2hIytc5xjU@mail.gmail.com>
References: <AANLkTimqNv37LkJDyKJp9PnJapXH4naINhx-T2ysQi4D@mail.gmail.com>
	<20100628090036.GA28510@n2100.arm.linux.org.uk>
	<AANLkTin_iY-7nUwtf1q7Fz4qdnkA0BUktEC6WwCiQdOX@mail.gmail.com>
	<20100628102931.GA30050@n2100.arm.linux.org.uk>
	<AANLkTin-cXOIkMN9JXdPETP_aEjeCjF9qV2hIytc5xjU@mail.gmail.com>
Message-ID: <20100629200550.GA14704@n2100.arm.linux.org.uk>

On Tue, Jun 29, 2010 at 11:51:34AM +0530, Harishkumar V wrote:
> <3>BUG: soft lockup - CPU#0 stuck for 61s! [Xfbdev:723]
> BUG: soft lockup - CPU#0 stuck for 61s! [Xfbdev:723]
> Modules linked in:Modules linked in: cir_lin cir_lin

ARGH.  Disable the debugging printascii please.  It's *ONLY* there for
debugging the very early boot of the kernel, and once that's working
it should be disabled as soon as possible after that fact.

Leaving it on results in these messages becoming unreadable.

However, as I said subsequently, you need to investigate why your
IRQ92 handler is always returning IRQ_HANDLED.


From jayakumar.lkml at gmail.com  Tue Jun 29 20:02:31 2010
From: jayakumar.lkml at gmail.com (Jaya Kumar)
Date: Wed, 30 Jun 2010 08:02:31 +0800
Subject: [PATCH 1/3] FB: Add some members for CPU Interface.
In-Reply-To: <4C29CFBD.3040205@samsung.com>
References: <4C29CFBD.3040205@samsung.com>
Message-ID: <AANLkTilgB3s8hy5Qg7IYpyBzwHCgK_GswVZqpxhryU5L@mail.gmail.com>

2010/6/29 InKi Dae <inki.dae at samsung.com>:
> CPU interface needs cs, wr setup, wr act and hold delay.
> I added some members for them to common framework.

Hi InKi Dae,

The patch looks interesting. Could you help us understand more about
it from a big picture perspective? ie: how is this "cpu interface"
used? I think fb_var_screeninfo is intended to be a very generic data
structure and since it is exposed to userspace we should be cautious
about what we add to it. I didn't understand the purpose of exposing
cs, wr setup, wr act and hold delay to userspace. Are the MIPI display
parameters being specified from userspace? I also didn't understand
the fb_cmdmode_to_var export. I looked through the other 2 patches
(3/3 and 2/3) and didn't see it used so I might have missed something.
Also, I wanted to ask, since there are now multiple MIPI-DSI host
controller drivers in fbdev (omap and also mobile-sh), is there any
work that could be done to make these implementations share more code?

Thanks,
jaya

>
> Signed-off-by: InKi Dae <inki.dae at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
>
> diff --git a/drivers/video/modedb.c b/drivers/video/modedb.c
>
> index 0a4dbdc..74122d1 100644
> --- a/drivers/video/modedb.c
> +++ b/drivers/video/modedb.c
> @@ -759,6 +759,27 @@ void fb_videomode_to_var(struct fb_var_screeninfo *var,
>  }
>
>  /**
> + * fb_cpumode_to_var - convert fb_cpumode to fb_var_screeninfo
> + * @var: pointer to struct fb_var_screeninfo
> + * @mode: pointer to struct fb_cpumode
> + */
> +void fb_cmdmode_to_var(struct fb_var_screeninfo *var,
> +			 const struct fb_cmdmode *mode)
> +{
> +	var->xres = mode->xres;
> +	var->yres = mode->yres;
> +	var->xres_virtual = mode->xres;
> +	var->yres_virtual = mode->yres;
> +	var->xoffset = 0;
> +	var->yoffset = 0;
> +	var->pixclock = mode->pixclock;
> +	var->cs_setup = mode->cs_setup;
> +	var->wr_setup = mode->wr_setup;
> +	var->wr_act = mode->wr_act;
> +	var->wr_hold = mode->wr_hold;
> +}
> +
> +/**
>   * fb_mode_is_equal - compare 2 videomodes
>   * @mode1: first videomode
>   * @mode2: second videomode
> @@ -1048,6 +1069,7 @@ finished:
>  EXPORT_SYMBOL(fb_find_best_display);
>
>  EXPORT_SYMBOL(fb_videomode_to_var);
> +EXPORT_SYMBOL(fb_cmdmode_to_var);
>  EXPORT_SYMBOL(fb_var_to_videomode);
>  EXPORT_SYMBOL(fb_mode_is_equal);
>  EXPORT_SYMBOL(fb_add_videomode);
> diff --git a/include/linux/fb.h b/include/linux/fb.h
> index 907ace3..73381c3 100644
> --- a/include/linux/fb.h
> +++ b/include/linux/fb.h
> @@ -269,6 +269,12 @@ struct fb_var_screeninfo {
>  	__u32 vmode;			/* see FB_VMODE_*		*/
>  	__u32 rotate;			/* angle we rotate counter clockwise */
>  	__u32 reserved[5];		/* Reserved for future compatibility */
> +
> +	/* For cpu interface timing. */
> +	__u32 cs_setup;
> +	__u32 wr_setup;
> +	__u32 wr_act;
> +	__u32 wr_hold;
>  };
>
>  struct fb_cmap {
> @@ -1117,11 +1123,24 @@ struct fb_videomode {
>  	u32 lower_margin;
>  	u32 hsync_len;
>  	u32 vsync_len;
> +	u32 cmd_allow_len;
>  	u32 sync;
>  	u32 vmode;
>  	u32 flag;
>  };
>
> +struct fb_cmdmode {
> +	const char *name;	/* optional */
> +	u32 refresh;		/* optional */
> +	u32 xres;
> +	u32 yres;
> +	u32 pixclock;
> +	u32 cs_setup;
> +	u32 wr_setup;
> +	u32 wr_act;
> +	u32 wr_hold;
> +};
> +
>  extern const char *fb_mode_option;
>  extern const struct fb_videomode vesa_modes[];
>
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>


From baruch at tkos.co.il  Tue Jun 29 23:03:16 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed, 30 Jun 2010 06:03:16 +0300
Subject: [PATCHv4 1/3] mx2_camera: Add soc_camera support for i.MX25/i.MX27
In-Reply-To: <Pine.LNX.4.64.1006292145001.22603@axis700.grange>
References: <cover.1277096909.git.baruch@tkos.co.il>
	<03d6e55c39690618e92a91a580ec34549a135c79.1277096909.git.baruch@tkos.co.il>
	<Pine.LNX.4.64.1006292145001.22603@axis700.grange>
Message-ID: <20100630030315.GA23534@tarshish>

On Tue, Jun 29, 2010 at 09:47:42PM +0200, Guennadi Liakhovetski wrote:
> On Mon, 21 Jun 2010, Baruch Siach wrote:
> 
> > This is the soc_camera support developed by Sascha Hauer for the i.MX27.  Alan
> > Carvalho de Assis modified the original driver to get it working on more recent
> > kernels. I modified it further to add support for i.MX25. This driver has been
> > tested on i.MX25 and i.MX27 based platforms.
> 
> This looks good to me, thanks! Overflow on eMMA is, probably, still 
> broken, but it will, most probably, remain so, until someone tests and 
> fixes it. One question though: do you know whether this imx/mxc overhaul: 
> http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/thread.html#18844 
> affects your driver?

I tested this yesterday, and, unfortunately, it does :(. See 
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/019111.html.  
However, this issue does not affect mx27 builds. So I think this should not 
stop the merge of this driver, for now. I hope Uwe and I will find an 
acceptable solution before the .36 merge window opens.

baruch

> I can ask Uwe, but maybe you have an idea or could test your patches with 
> Uwe's git tree?
> 
> Thanks
> Guennadi
> 
> > 
> > Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> > ---

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From nico at fluxnic.net  Tue Jun 29 23:55:02 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Tue, 29 Jun 2010 23:55:02 -0400 (EDT)
Subject: Git pull request: some security features missing on ARM
Message-ID: <alpine.LFD.2.00.1006292342210.24097@xanadu.home>

Russell, could you pull the following for the next merge window:

	git://git.linaro.org/nico/arm_security

This contains a few security features that are present on x86 and 
missing on ARM.  Those patches were posted on the list a while ago and 
no objections came back.

Nicolas Pitre (4):
      [ARM] implement arch_randomize_brk()
      [ARM] add address randomization to mmap()
      ARM: initial stack protector (-fstack-protector) support
      ARM: stack protector: change the canary value per task

 arch/arm/Kconfig                      |   12 ++++++++
 arch/arm/Makefile                     |    4 +++
 arch/arm/include/asm/elf.h            |    3 ++
 arch/arm/include/asm/stackprotector.h |   38 +++++++++++++++++++++++++++
 arch/arm/kernel/asm-offsets.c         |    3 ++
 arch/arm/kernel/entry-armv.S          |    8 +++++
 arch/arm/kernel/process.c             |   13 +++++++++
 arch/arm/mm/mmap.c                    |    4 +++
 8 files changed, 85 insertions(+), 0 deletions(-)



From daeinki at gmail.com  Wed Jun 30 00:36:31 2010
From: daeinki at gmail.com (InKi Dae)
Date: Wed, 30 Jun 2010 13:36:31 +0900
Subject: [PATCH 1/3] FB: Add some members for CPU Interface.
In-Reply-To: <AANLkTilgB3s8hy5Qg7IYpyBzwHCgK_GswVZqpxhryU5L@mail.gmail.com>
References: <4C29CFBD.3040205@samsung.com>
	<AANLkTilgB3s8hy5Qg7IYpyBzwHCgK_GswVZqpxhryU5L@mail.gmail.com>
Message-ID: <AANLkTikxu_p-F4iJnwiY7GvP0Zkf-WsZEAeLzfJuljlB@mail.gmail.com>

Hi Jaya,

2010/6/30 Jaya Kumar <jayakumar.lkml at gmail.com>:
> 2010/6/29 InKi Dae <inki.dae at samsung.com>:
>> CPU interface needs cs, wr setup, wr act and hold delay.
>> I added some members for them to common framework.
>
> Hi InKi Dae,
>
> The patch looks interesting. Could you help us understand more about
> it from a big picture perspective? ie: how is this "cpu interface"
> used? I think fb_var_screeninfo is intended to be a very generic data
> structure and since it is exposed to userspace we should be cautious
> about what we add to it. I didn't understand the purpose of exposing
> cs, wr setup, wr act and hold delay to userspace.

in case of lcd panel with cpu interface, it could get screen data
through arm core
or display controller supporting cpu interface mode.
display controller of s5pv210 chip can create cpu interface signal according to
cs, wr setup, wr act and hold time setting.
the reason I added cpu timing variables to fb_var_screeninfo is for using common
framework when setting them to the display controller as cpu timing info.
please, see [PATCH 2/3], s3c_fb_set_timing function part.

and cpu timing could be adjusted by user through fb_var_screeninfo,
for this, suitable checking should be considered at machine specific
fb_check_var func.
also you can see that through [PATCH 2/3], s3c_fb_check_var.

> Are the MIPI display
> parameters being specified from userspace? I also didn't understand
> the fb_cmdmode_to_var export. I looked through the other 2 patches
> (3/3 and 2/3) and didn't see it used so I might have missed something.

I just exported fb_cmdmode_to_var for future use. it doesn't use this func yet.
now, modedb.c and fb.h have no variables for cpu interface. perhaps, more codes
for cpu interface should be added to them.

> Also, I wanted to ask, since there are now multiple MIPI-DSI host
> controller drivers in fbdev (omap and also mobile-sh), is there any
> work that could be done to make these implementations share more code?

can MIPI-DSI host controller drivers you said use commonly?
I think these drivers are machine specific. so driver for MIPI-DSI
controller of S5PV210
should be implemented.

this patch code is MIPI Master driver and it can registered multiple
MIPI client driver
(mipi based lcd panel driver).
to use master driver, mipi client driver have to define some callbacks to struct
mipi_lcd_driver, and register them through s5p_dsim_register_lcd_driver func.
after this, client driver would be registered to master driver, and
client driver registered
would be probed when master driver was probed scaning client driver name.

please, see [PATCH 3/3], s5p_dsim_probe func part.

thank you for your interesting.

Best Regards,
InKi Dae.


From myungjoo.ham at samsung.com  Wed Jun 30 00:56:51 2010
From: myungjoo.ham at samsung.com (MyungJoo Ham)
Date: Wed, 30 Jun 2010 13:56:51 +0900
Subject: [PATCH v5] ARM: S5PV210: Correct clock register properties
Message-ID: <1277873811-2823-1-git-send-email-myungjoo.ham@samsung.com>

1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which were
defined incorrectly.

2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc,
sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their
twins defined in struct clk init_clocks_disable[] and struct clk
init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK
register to avoid the duplicated clock problem described below.


What is Duplicated Clock Problem?

Please note that each clock definition should access different control
register; otherwise, the system may suffer lockups. For example, if we
have two clock definitions "a" and "b" which access the same register
(and the shift value). Then, when we do:

	module A
	clk = clk_get("a");
	clk->clk_enable(clk);

	module B (context switch)
	clk = clk_get("b");
	clk->clk_enable(clk);
	do something with clk.
	clk->clk_disable(clk);

	module A (context switch)
	do something with clk
	* At this point, the system may hang.

Therefore, there should be no clock definitions with the same contol
register/shift. If we need to create "aliases", then, creating child
clocks sharing the clock should be fine.

3. Corrected other sclk_* shift values and access registers.


Note that becuase UART clocks are properly disabled at boot time with
this patch, UART drivers or somebody else should turn on the clock
to read the console; otherwise, JIG willl not show any message.



Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
---
Note that this patch revises and merges the two previous patches:
[PATCH] S5PV210 Correct clock register properties
[PATCH] S5PV210 Correct clock source control register properties
And follows the previous patch
[PATCH v2] S5PV210 Correct clock register properties
[PATCH v3] S5PV210 Correct clock register properties
[PATCH v4] S5PV210 Correct clock register properties
v5 revises comments only from v4.
 arch/arm/mach-s5pv210/clock.c |  115 ++++++++++++++++++++++-------------------
 1 files changed, 62 insertions(+), 53 deletions(-)

diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 154bca4..b3d156c 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -183,6 +183,11 @@ static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
 	return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
 }
 
+static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
+{
+	return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
+}
+
 static struct clk clk_sclk_hdmi27m = {
 	.name		= "sclk_hdmi27m",
 	.id		= -1,
@@ -406,14 +411,14 @@ static struct clk init_clocks_disable[] = {
 		.id		= 0,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
+		.ctrlbit	= (1 << 5),
 	}, {
 		.name		= "i2s_v32",
 		.id		= 1,
 		.parent		= &clk_p,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<4),
-	}
+		.ctrlbit	= (1 << 6),
+	},
 };
 
 static struct clk init_clocks[] = {
@@ -429,25 +434,25 @@ static struct clk init_clocks[] = {
 		.id		= 0,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<7),
+		.ctrlbit	= (1 << 17),
 	}, {
 		.name		= "uart",
 		.id		= 1,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<8),
+		.ctrlbit	= (1 << 18),
 	}, {
 		.name		= "uart",
 		.id		= 2,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<9),
+		.ctrlbit	= (1 << 19),
 	}, {
 		.name		= "uart",
 		.id		= 3,
 		.parent		= &clk_pclk_psys.clk,
 		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1<<10),
+		.ctrlbit	= (1 << 20),
 	},
 };
 
@@ -497,8 +502,8 @@ static struct clksrc_clk clk_sclk_dac = {
 	.clk		= {
 		.name		= "sclk_dac",
 		.id		= -1,
-		.ctrlbit	= (1 << 10),
-		.enable		= s5pv210_clk_ip1_ctrl,
+		.ctrlbit	= (1 << 2),
+		.enable		= s5pv210_clk_mask0_ctrl,
 	},
 	.sources	= &clkset_sclk_dac,
 	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
@@ -527,8 +532,8 @@ static struct clksrc_clk clk_sclk_hdmi = {
 	.clk		= {
 		.name		= "sclk_hdmi",
 		.id		= -1,
-		.enable		= s5pv210_clk_ip1_ctrl,
-		.ctrlbit	= (1 << 11),
+		.ctrlbit	= (1 << 0),
+		.enable		= s5pv210_clk_mask0_ctrl,
 	},
 	.sources	= &clkset_sclk_hdmi,
 	.reg_src	= { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
@@ -565,8 +570,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 0,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 4),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 24),
 	},
 	.sources = &clkset_sclk_audio0,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
@@ -594,8 +599,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 1,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 5),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 25),
 	},
 	.sources = &clkset_sclk_audio1,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
@@ -623,8 +628,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
 	.clk		= {
 		.name		= "sclk_audio",
 		.id		= 2,
-		.enable		= s5pv210_clk_ip3_ctrl,
-		.ctrlbit	= (1 << 6),
+		.enable		= s5pv210_clk_mask0_ctrl,
+		.ctrlbit	= (1 << 26),
 	},
 	.sources = &clkset_sclk_audio2,
 	.reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
@@ -680,8 +685,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "uclk1",
 			.id		= 0,
-			.ctrlbit	= (1<<17),
-			.enable		= s5pv210_clk_ip3_ctrl,
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 12),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
@@ -690,8 +695,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 18),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 13),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
@@ -700,8 +705,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 19),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 14),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
@@ -710,8 +715,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "uclk1",
 			.id		= 3,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 20),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 15),
 		},
 		.sources = &clkset_uart,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
@@ -720,8 +725,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_mixer",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip1_ctrl,
-			.ctrlbit	= (1 << 9),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 1),
 		},
 		.sources = &clkset_sclk_mixer,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
@@ -738,8 +743,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_fimc",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 24),
+			.enable		= s5pv210_clk_mask1_ctrl,
+			.ctrlbit	= (1 << 2),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
@@ -748,8 +753,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_fimc",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 25),
+			.enable		= s5pv210_clk_mask1_ctrl,
+			.ctrlbit	= (1 << 3),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
@@ -758,8 +763,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk	= {
 			.name		= "sclk_fimc",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 26),
+			.enable		= s5pv210_clk_mask1_ctrl,
+			.ctrlbit	= (1 << 4),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
@@ -768,6 +773,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_cam",
 			.id		= 0,
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 3),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
@@ -776,6 +783,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_cam",
 			.id		= 1,
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 4),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
@@ -784,8 +793,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_fimd",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip1_ctrl,
-			.ctrlbit	= (1 << 0),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 5),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
@@ -794,8 +803,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 16),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 8),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
@@ -804,8 +813,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 17),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 9),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
@@ -814,8 +823,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 2,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 18),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 10),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
@@ -824,8 +833,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_mmc",
 			.id		= 3,
-			.enable		= s5pv210_clk_ip2_ctrl,
-			.ctrlbit	= (1 << 19),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 11),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
@@ -864,8 +873,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_csis",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip0_ctrl,
-			.ctrlbit	= (1 << 31),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 6),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
@@ -874,8 +883,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_spi",
 			.id		= 0,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 12),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 16),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
@@ -884,8 +893,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_spi",
 			.id		= 1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 13),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 17),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
@@ -894,8 +903,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_pwi",
 			.id		= -1,
-			.enable		= &s5pv210_clk_ip4_ctrl,
-			.ctrlbit	= (1 << 2),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 29),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
@@ -904,8 +913,8 @@ static struct clksrc_clk clksrcs[] = {
 		.clk		= {
 			.name		= "sclk_pwm",
 			.id		= -1,
-			.enable		= s5pv210_clk_ip3_ctrl,
-			.ctrlbit	= (1 << 23),
+			.enable		= s5pv210_clk_mask0_ctrl,
+			.ctrlbit	= (1 << 19),
 		},
 		.sources = &clkset_group2,
 		.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
-- 
1.6.3.3



From zpfeffer at codeaurora.org  Wed Jun 30 01:55:48 2010
From: zpfeffer at codeaurora.org (Zach Pfeffer)
Date: Tue, 29 Jun 2010 22:55:48 -0700
Subject: [RFC 1/3] mm: iommu: An API to unify IOMMU,
	CPU and device memory management
Message-ID: <1277877350-2147-1-git-send-email-zpfeffer@codeaurora.org>

This patch contains the documentation for the API, termed the Virtual
Contiguous Memory Manager. Its use would allow all of the IOMMU to VM,
VM to device and device to IOMMU interoperation code to be refactored
into platform independent code.

Comments, suggestions and criticisms are welcome and wanted.

Signed-off-by: Zach Pfeffer <zpfeffer at codeaurora.org>
---
 Documentation/vcm.txt |  583 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 583 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/vcm.txt

diff --git a/Documentation/vcm.txt b/Documentation/vcm.txt
new file mode 100644
index 0000000..d29c757
--- /dev/null
+++ b/Documentation/vcm.txt
@@ -0,0 +1,583 @@
+What is this document about?
+============================
+
+This document covers how to use the Virtual Contiguous Memory Manager
+(VCMM), how the first implmentation works with a specific low-level
+Input/Output Memory Management Unit (IOMMU) and the way the VCMM is used
+from user-space. It also contains a section that describes why something
+like the VCMM is needed in the kernel.
+
+If anything in this document is wrong please send patches to the
+maintainer of this file, listed at the bottom of the document.
+
+
+The Virtual Contiguous Memory Manager
+=====================================
+
+The VCMM was built to solve the system-wide memory mapping issues that
+occur when many bus-masters have IOMMUs.
+
+An IOMMU maps device addresses to physical addresses. It also insulates
+the system from spurious or malicious device bus transactions and allows
+fine-grained mapping attribute control. The Linux kernel core does not
+contain a generic API to handle IOMMU mapped memory; device driver writers
+must implement device specific code to interoperate with the Linux kernel
+core. As the number of IOMMUs increases, coordinating the many address
+spaces mapped by all discrete IOMMUs becomes difficult without in-kernel
+support.
+
+The VCMM API enables device independent IOMMU control, virtual memory
+manager (VMM) interoperation and non-IOMMU enabled device interoperation
+by treating devices with or without IOMMUs and all CPUs with or without
+MMUs, their mapping contexts and their mappings using common
+abstractions. Physical hardware is given a generic device type and mapping
+contexts are abstracted into Virtual Contiguous Memory (VCM)
+regions. Users "reserve" memory from VCMs and "back" their reservations
+with physical memory.
+
+Why the VCMM is Needed
+----------------------
+
+Driver writers who control devices with IOMMUs must contend with device
+control and memory management. Driver writers have a large device driver
+API that they can leverage to control their devices, but they are lacking
+a unified API to help them program mappings into IOMMUs and share those
+mappings with other devices and CPUs in the system.
+
+Sharing is complicated by Linux's CPU centric VMM. The CPU centric model
+generally makes sense because average hardware only contains a MMU for the
+CPU and possibly a graphics MMU. If every device in the system has one or
+more MMUs the CPU centric memory management (MM) programming model breaks
+down.
+
+Abstracting IOMMU device programming into a common API has already begun
+in the Linux kernel. It was built to abstract the difference between AMDs
+and Intels IOMMUs to support x86 virtualization on both platforms. The
+interface is listed in kernel/include/linux/iommu.h. It contains
+interfaces for mapping and unmapping as well as domain management. This
+interface has not gained widespread use outside the x86; PA-RISC, Alpha
+and SPARC architectures and ARM and PowerPC platforms all use their own
+mapping modules to control their IOMMUs. The VCMM contains an IOMMU
+programming layer, but since its abstraction supports map management
+independent of device control, the layer is not used directly. This
+higher-level view enables a new kernel service, not just an IOMMU
+interoperation layer.
+
+The General Idea: Map Management using Graphs
+---------------------------------------------
+
+Looking at mapping from a system-wide perspective reveals a general graph
+problem. The VCMMs API is built to manage the general mapping graph. Each
+node that talks to memory, either through an MMU or directly (physically
+mapped) can be thought of as the device-end of a mapping edge. The other
+edge is the physical memory (or intermediate virtual space) that is
+mapped.
+
+In the direct mapped case the device is assigned a one-to-one MMU. This
+scheme allows direct mapped devices to participate in general graph
+management.
+
+The CPU nodes can also be brought under the same mapping abstraction with
+the use of a light overlay on the existing VMM. This light overlay allows
+VMM managed mappings to interoperate with the common API. The light
+overlay enables this without substantial modifications to the existing
+VMM.
+
+In addition to CPU nodes that are running Linux (and the VMM), remote CPU
+nodes that may be running other operating systems can be brought into the
+general abstraction. Routing all memory management requests from a remote
+node through the central memory management framework enables new features
+like system-wide memory migration. This feature may only be feasible for
+large buffers that are managed outside of the fast-path, but having remote
+allocation in a system enables features that are impossible to build
+without it.
+
+The fundamental objects that support graph-based map management are:
+
+1) Virtual Contiguous Memory Regions
+
+2) Reservations
+
+3) Associated Virtual Contiguous Memory Regions
+
+4) Memory Targets
+
+5) Physical Memory Allocations
+
+Usage Overview
+--------------
+
+In a nut-shell, users allocate Virtual Contiguous Memory Regions and
+associate those regions with one or more devices by creating an Associated
+Virtual Contiguous Memory Region. Users then create Reservations from the
+Virtual Contiguous Memory Region. At this point no physical memory has
+been committed to the reservation. To associate physical memory with a
+reservation a Physical Memory Allocation is created and the Reservation is
+backed with this allocation.
+
+include/linux/vcm.h includes comments documenting each API.
+
+Virtual Contiguous Memory Regions
+---------------------------------
+
+A Virtual Contiguous Memory Region (VCM) abstracts the memory space a
+device sees. The addresses of the region are only used by the devices
+which are associated with the region. This address space would normally be
+implemented as a device page-table.
+
+A VCM is created and destroyed with three functions:
+
+    struct vcm *vcm_create(size_t start_addr, size_t len);
+
+    struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id);
+
+    int vcm_free(struct vcm *vcm);
+
+start_addr is an offset into the address space where allocations will
+start from. len is the length from start_addr of the VCM. Both functions
+generate an instance of a VCM.
+
+ext_vcm_id is used to pass a request to the VMM to generate a VCM
+instance. In the current implementation the call simply makes a note that
+the VCM instance is a VMM VCM instance for other interfaces usage. This
+muxing is seen throughout the implementation.
+
+vcm_create() and vcm_create_from_prebuilt() produce VCM instances for
+virtually mapped devices (IOMMUs and CPUs). To create a one-to-one mapped
+VCM users pass the start_addr and len of the physical region. The VCMM
+matches this and records that the VCM instance is a one-to-one VCM.
+
+The newly created VCM instance can be passed to any function that needs to
+operate on or with a virtual contiguous memory region. Its main attributes
+are a start_addr and a len as well as an internal setting that allows the
+implementation to mux between true virtual spaces, one-to-one mapped
+spaces and VMM managed spaces.
+
+The current implementation uses the genalloc library to manage the VCM for
+IOMMU devices. Return values and more in-depth per-function documentation
+for these and the ones listed below are in include/linux/vcm.h.
+
+Reservations
+------------
+
+A Reservation is a contiguous region allocated from a VCM. There is no
+physical memory associated with it.
+
+A Reservation is created and destroyed with:
+
+    struct res *vcm_reserve(struct vcm *vcm, size_t len, uint32_t attr);
+
+    int vcm_unreserve(struct res *res);
+
+A vcm is a VCM created above. len is the length of the request. It can be
+up to the length of the VCM region the reservation is being created
+from. attr are mapping attributes: read, write, execute, user, supervisor,
+secure, not-cached, write-back/write-allocate, write-back/no
+write-allocate, write-through. These attrs are appropriate for ARM but can
+be changed to match to any architecture.
+
+The implementation calls gen_pool_alloc() for IOMMU devices,
+alloc_vm_area() for VMM areas and is a pass through for one-to-one mapped
+areas.
+
+Associated Virtual Contiguous Memory Regions and Activation
+-----------------------------------------------------------
+
+An Associated Virtual Contiguous Memory Region (AVCM) is a mapping of a
+VCM to a device. The mapping can be active or inactive.
+
+An AVCM is managed with:
+
+struct avcm *vcm_assoc(struct vcm *vcm, size_t dev, uint32_t attr);
+
+    int vcm_deassoc(struct avcm *avcm);
+
+    int vcm_activate(struct avcm *avcm);
+
+    int vcm_deactivate(struct avcm *avcm);
+
+A VCM instance is a VCM created above. A dev is an opaque device handle
+thats passed down to the device driver the VCMM muxes in to handle a
+request. attr are association attributes: split, use-high or
+use-low. split controls which transactions hit a high-address page-table
+and which transactions hit a low-address page-table. For instance, all
+transactions whose most significant address bit is one would use the
+high-address page-table, any other transaction would use the low address
+page-table. This scheme is ARM specific and could be changed in other
+architectures. One VCM instance can be associated with many devices and
+many VCM instances can be associated with one device.
+
+An AVCM is only a link. To program and deprogram a device with a VCM the
+user calls vcm_activate() and vcm_deactivate().For IOMMU devices,
+activating a mapping programs the base address of a page-table into an
+IOMMU. For VMM and one-to-one based devices, mappings are active
+immediately but the API does require an activation call for them for
+internal reference counting.
+
+Memory Targets
+--------------
+
+A Memory Target is a platform independent way of specifying a physical
+pool; it abstracts a pool of physical memory. The physical memory pool may
+be physically discontiguous, need to be allocated from in a unique way or
+have other user-defined attributes.
+
+Physical Memory Allocation and Reservation Backing
+--------------------------------------------------
+
+Physical memory is allocated as a separate step from reserving
+memory. This allows multiple reservations to back the same physical
+memory.
+
+A Physical Memory Allocation is managed using the following functions:
+
+    struct physmem *vcm_phys_alloc(enum memtype_t memtype, size_t len,
+                                   uint32_t attr);
+
+    int vcm_phys_free(struct physmem *physmem);
+
+    int vcm_back(struct res *res, struct physmem *physmem);
+
+    int vcm_unback(struct res *res);
+
+attr can include an alignment request, a specification to map memory using
+various block sizes and/or to use physically contiguous memory. memtype is
+one of the memory types listed in Memory Targets.
+
+The current implementation manages two pools of memory. One pool is a
+contiguous block of memory and the other is a set of contiguous block
+pools. In the current implementation the block pools contain 4K, 64K and
+1M blocks. The physical allocator does not try to split blocks from the
+contiguous block pools to satisfy requests.
+
+The use of 4K, 64K and 1M blocks solves a problem with some IOMMU
+hardware. IOMMUs are placed in front of multimedia engines to provide a
+contiguous address space to the device. Multimedia devices need large
+buffers and large buffers may map to a large number of physical
+blocks. IOMMUs tend to have small translation lookaside buffers
+(TLBs). Since the TLB is small the number of physical blocks that map a
+given range needs to be small or else the IOMMU will continually fetch new
+translations during a typical streamed multimedia flow. By using a 1 MB
+mapping (or 64K mapping) instead of a 4K mapping the number of misses can
+be minimized, allowing the multimedia block to meet its performance goals.
+
+Low Level Control
+-----------------
+
+It is necessary in some instances to access attributes and provide
+higher-level control of the low-level hardware abstraction. The API
+contains many functions for this task but the two that are typically used
+are:
+
+    size_t vcm_get_dev_addr(struct res *res);
+
+    int vcm_hook(size_t dev, vcm_handler handler, void *data);
+
+The first function, vcm_get_dev_addr() returns a device address given a
+reservation. This device address is a virtual IOMMU address for
+reservations on IOMMU VCMs, a virtual VMM address for reservations on VMM
+VCMs and a virtual (really physical since its one-to-one mapped) address
+for one-to-one devices.
+
+The second function, vcm_hook allows a caller in the kernel to register a
+user_handler. The handler is passed the data member passed to vcm_hook
+during a fault. The user can return 1 to indicate that the underlying
+driver should handle the fault and retry the transaction or they can
+return 0 to halt the transaction. If the user doesn't register a handler
+the low-level driver will print a warning and terminate the transaction.
+
+A Detailed Walk Through
+-----------------------
+
+The following call sequence walks through a typical allocation
+sequence. In the first stage the memory for a device is reserved and
+backed. This occurs without mapping the memory into a VMM VCM region. The
+second stage maps the first VCM region into a VMM VCM region so the kernel
+can read or write it. The second stage is not necessary if the VMM does
+not need to read or modify the contents of the original mapping.
+
+    Stage 1: Map and Allocate Memory for a Device
+
+    The call sequence starts by creating a VCM region:
+
+        vcm = vcm_create(start_addr, len);
+
+    The next call associates a VCM region with a device:
+
+        avcm = vcm_assoc(vcm, dev, attr);
+
+    To activate the association users call vcm_activate() on the avcm from
+    the associate call. This programs the underlining device with the
+    mappings.
+
+        ret = vcm_activate(avcm);
+
+    Once a VCM region is created and associated it can be reserved from
+    with:
+
+        res = vcm_reserve(vcm, res_len, res_attr);
+
+    A user then allocates physical memory with:
+
+        physmem = vcm_phys_alloc(memtype, len, phys_attr);
+
+    To back the reservation with the physical memory allocation the user
+    calls:
+
+        vcm_back(res, physmem);
+
+
+    Stage 2: Map the Device's Memory into the VMM's VCM region
+
+    If the VMM needs to read and/or write the region that was just created
+    the following calls are made.
+
+    The first call creates a prebuilt VCM with:
+
+        vcm_vmm = vcm_from_prebuilt(ext_vcm_id);
+
+    The prebuilt VCM is associated with the CPU device and activated with:
+
+        avcm_vmm = vcm_assoc(vcm_vmm, dev_cpu, attr);
+        vcm_activate(avcm_vmm);
+
+    A reservation is made on the VMM VCM with:
+
+        res_vmm = vcm_reserve(vcm_vmm, res_len, attr);
+
+    Finally, once the topology has been set up a vcm_back() allows the VMM
+    to read the memory using the physmem generated in stage 1:
+
+        vcm_back(res_vmm, physmem);
+
+Mapping IOMMU, one-to-one and VMM Reservations
+----------------------------------------------
+
+The following example demonstrates mapping IOMMU, one-to-one and VMM
+reservations to the same physical memory. It shows the use of phys_addr
+and phys_size to create a contiguous VCM for one-to-one mapped devices.
+
+    The user allocates physical memory:
+
+        physmem = vcm_phys_alloc(memtype, SZ_2MB + SZ_4K, CONTIGUOUS);
+
+    Creates an IOMMU VCM:
+
+        vcm_iommu = vcm_create(SZ_1K, SZ_16M);
+
+    Creates an one-to-one VCM:
+
+        vcm_onetoone = vcm_create(phys_addr, phys_size);
+
+    Creates a Prebuit VCM:
+
+        vcm_vmm = vcm_from_prebuit(ext_vcm_id);
+
+    Associate and activate all three to their respective devices:
+
+        avcm_iommu = vcm_assoc(vcm_iommu, dev_iommu, attr0);
+        avcm_onetoone = vcm_assoc(vcm_onetoone, dev_onetoone, attr1);
+        avcm_vmm = vcm_assoc(vcm_vmm, dev_cpu, attr2);
+        vcm_activate(avcm_iommu);
+        vcm_activate(avcm_onetoone);
+        vcm_activate(avcm_vmm);
+
+    And finally, creates and backs reservations on all 3 such that they
+    all point to the same memory:
+
+        res_iommu = vcm_reserve(vcm_iommu, SZ_2MB + SZ_4K, attr);
+        res_onetoone = vcm_reserve(vcm_onetoone, SZ_2MB + SZ_4K, attr);
+        res_vmm = vcm_reserve(vcm_vmm, SZ_2MB + SZ_4K, attr);
+        vcm_back(res_iommu, physmem);
+        vcm_back(res_onetoone, physmem);
+        vcm_back(res_vmm, physmem);
+
+VCM Summary
+-----------
+
+The VCMM is an attempt to abstract attributes of three distinct classes of
+mappings into one API. The VCMM allows users to reason about mappings as
+first class objects. It also allows memory mappings to flow from the
+traditional 4K mappings prevalent on systems today to more efficient block
+sizes. Finally, it allows users to manage mapping interoperation without
+becoming VMM experts. These features will allow future systems with many
+MMU mapped devices to interoperate simply and therefore correctly.
+
+
+IOMMU Hardware Control
+======================
+
+The VCM currently supports a single type of IOMMU, a Qualcomm System MMU
+(SMMU). The SMMU interface contains functions to map and unmap virtual
+addresses, perform address translations and initialize hardware. A
+Qualcomm SMMU can contain multiple MMU contexts. Each context can
+translate in parallel. All contexts in a SMMU share one global translation
+look-aside buffer (TLB).
+
+To support context muxing the SMMU module creates and manages device
+independent virtual contexts. These context abstractions are bound to
+actual contexts at run-time. Once bound, a context can be activated. This
+activation programs the underlying context with the virtual context
+affecting a context switch.
+
+The following functions are all documented in:
+
+    arch/arm/mach-msm/include/mach/smmu_driver.h.
+
+Mapping
+-------
+
+To map and unmap a virtual page into physical space the VCM calls:
+
+    int smmu_map(struct smmu_dev *dev, unsigned long pa,
+                 unsigned long va, unsigned long len, unsigned int attr);
+
+    int smmu_unmap(struct smmu_dev *dev, unsigned long va,
+                   unsigned long len);
+
+    int smmu_update_start(struct smmu_dev *dev);
+
+    int smmu_update_done(struct smmu_dev *dev);
+
+The size given to map must be 4K, 64K, 1M or 16M and the VA and PA must be
+aligned to the given size. smmu_update_start() and smmu_update_done()
+should be called before and after each map or unmap.
+
+Translation
+-----------
+
+To request a hardware VA to PA translation on a single address the VCM
+calls:
+
+    unsigned long smmu_translate(struct smmu_dev *dev,
+                                 unsigned long va);
+
+Fault Handling
+--------------
+
+To register an interrupt handler for a context the VCM calls:
+
+    int smmu_hook_irpt(struct smmu_dev *dev, vcm_handler handler,
+                       void *data);
+
+The registered interrupt handler should return 1 if it wants the SMMU
+driver to retry the transaction again and 0 if it wants the SMMU driver to
+terminate the transaction.
+
+Managing SMMU Initialization and Contexts
+-----------------------------------------
+
+SMMU hardware initialization and management happens in 2 steps. The first
+step initializes global SMMU devices and abstract device contexts. The
+second step binds contexts and devices.
+
+A SMMU hardware instance is built with:
+
+    int smmu_drvdata_init(struct smmu_driver *drv, unsigned long base,
+                          int irq);
+
+A SMMU context is Initialized and deinitialized with:
+
+    struct smmu_dev *smmu_ctx_init(int ctx);
+    int smmu_ctx_deinit(struct smmu_dev *dev);
+
+An abstract SMMU context is bound to a particular SMMU with:
+
+    int smmu_ctx_bind(struct smmu_dev *ctx, struct smmu_driver *drv);
+
+Activation
+----------
+
+Activation affects a context switch.
+
+Activation, deactivation and activation state testing are done with:
+
+    int smmu_activate(struct smmu_dev *dev);
+    int smmu_deactivate(struct smmu_dev *dev);
+    int smmu_is_active(struct smmu_dev *dev);
+
+
+Userspace Access to Devices with IOMMUs
+=======================================
+
+A device that issues transactions through an IOMMU must work with two
+APIs. The first API is the VCM. The VCM API is device independent. Users
+pass the VCM a dev_id and the VCM makes calls on the hardware device it
+has been configured with using this dev_id. The second API is whatever
+device topology has been created to organize the particular IOMMUs in a
+system. The only constraint on this second API is that it must give the
+user a single dev_id that it can pass through the VCM.
+
+For the Qualcomm SMMUs the second API consists of a tree of platform
+devices and two platform drivers as well as a context lookup function that
+traverses the device tree and returns a dev_id given a context name.
+
+Qualcomm SMMU Device Tree
+-------------------------
+
+The current tree organizes the devices into a tree that looks like the
+following:
+
+smmu/
+               smmu0/
+                                ctx0
+                                ctx1
+                                ctx2
+               smmu1/
+                                ctx3
+
+
+Each context, ctx[n] and each smmu, smmu[n] is given a name. Since users
+are interested in contexts not smmus, the contexts name is passed to a
+function to find the dev_id associated with that name. The functions to
+find, free and get the base address (since the device probe function calls
+ioremap to map the SMMUs configuration registers into the kernel) are
+listed here:
+
+    struct smmu_dev *smmu_get_ctx_instance(char *ctx_name);
+    int smmu_free_ctx_instance(struct smmu_dev *dev);
+    unsigned long smmu_get_base_addr(struct smmu_dev *dev);
+
+Documentation for these functions is in:
+
+    arch/arm/mach-msm/include/mach/smmu_device.h
+
+Each context is given a dev node named after the context. For example:
+
+    /dev/vcodec_a_mm1
+    /dev/vcodec_b_mm2
+    /dev/vcodec_stream
+    etc...
+
+Users open, close and mmap these nodes to access VCM buffers from
+userspace in the same way that they used to open, close and mmap /dev
+nodes that represented large physically contiguous buffers (called PMEM
+buffers on Android).
+
+Example
+-------
+
+An abbreviated example is shown here:
+
+Users get the dev_id associated with their target context, create a VCM
+topology appropriate for their device and finally associate the VCMs of
+the topology with the contexts that will take the VCMs:
+
+    dev_id = smmu_get_ctx_instance(vcodec_a_stream);
+
+create vcm and needed topology
+
+    avcm = vcm_assoc(vcm, dev_id, attr);
+
+Tying it all Together
+---------------------
+
+VCMs, IOMMUs and the device tree all work to support system-wide memory
+mappings. The use of each API in this system allows users to concentrate
+on the relevant details without needing to worry about low-level
+details. The APIs clear separation of memory spaces and the devices that
+support those memory spaces continues Linuxs tradition of abstracting the
+what from the how.
+
+
+Maintainer: Zach Pfeffer <zpfeffer at codeaurora.org>
-- 
1.7.0.2



From tony at atomide.com  Wed Jun 30 02:17:26 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 09:17:26 +0300
Subject: [PATCH 6/6] omap2/3/4: Add Kconfig option to compile in
	typical omap	features
In-Reply-To: <EAF47CD23C76F840A9E7FCE10091EFAB02C5DB7026@dbde02.ent.ti.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
	<20100629114738.16008.62006.stgit@baageli.muru.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C5DB6FC3@dbde02.ent.ti.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C5DB7026@dbde02.ent.ti.com>
Message-ID: <20100630061726.GQ2822@atomide.com>

* Shilimkar, Santosh <santosh.shilimkar at ti.com> [100629 17:40]:
> > >
> > With your series OMAP4 build breaks because of PM and SMP dependencies.
> > To ensure that build doesn't break on OMAP4, I needed below change. With
> > This change I tried your series and it boots OK on OMAP4430 SDP

Hmm the build does not break for me?
 
> Also tested the multi-omap build on OMAP3430 SDP and OMAP4430 SDP. Both boots OK.
> 
> > diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> > index 84fecd0..f48f275 100644
> > --- a/arch/arm/mach-omap2/Kconfig
> > +++ b/arch/arm/mach-omap2/Kconfig
> > @@ -7,8 +7,8 @@ config ARCH_OMAP2PLUS_TYPICAL
> >         default y
> >         select AEABI
> >         select REGULATOR
> > -       select PM
> > -       select PM_RUNTIME
> > +       select PM if !ARCH_OMAP4
> > +       select PM_RUNTIME if !ARCH_OMAP4
> >         select VFP
> >         select NEON if ARCH_OMAP3 || ARCH_OMAP4
> >         select SERIAL_8250

Let's rather fix whatever the issue is for booting (or building?)
omap4 with CONFIG_PM and CONFIG_PM_RUNTIME. If we can't implement
PM yet for omap4, we can just return early if cpu_is_omap44xx.

CONFIG_SMP we can't enable as that requires various ARM changes
to work on unicore systems. But hopefully we can enable that too
at some point with select SMP if ARCH_OMAP4.

Regards,

Tony


From u.kleine-koenig at pengutronix.de  Wed Jun 30 02:24:03 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 30 Jun 2010 08:24:03 +0200
Subject: [PATCHv4 1/3] mx2_camera: Add soc_camera support for i.MX25/i.MX27
In-Reply-To: <20100630030315.GA23534@tarshish>
References: <cover.1277096909.git.baruch@tkos.co.il>
	<03d6e55c39690618e92a91a580ec34549a135c79.1277096909.git.baruch@tkos.co.il>
	<Pine.LNX.4.64.1006292145001.22603@axis700.grange>
	<20100630030315.GA23534@tarshish>
Message-ID: <20100630062403.GD23160@pengutronix.de>

On Wed, Jun 30, 2010 at 06:03:16AM +0300, Baruch Siach wrote:
> On Tue, Jun 29, 2010 at 09:47:42PM +0200, Guennadi Liakhovetski wrote:
> > On Mon, 21 Jun 2010, Baruch Siach wrote:
> > 
> > > This is the soc_camera support developed by Sascha Hauer for the i.MX27.  Alan
> > > Carvalho de Assis modified the original driver to get it working on more recent
> > > kernels. I modified it further to add support for i.MX25. This driver has been
> > > tested on i.MX25 and i.MX27 based platforms.
> > 
> > This looks good to me, thanks! Overflow on eMMA is, probably, still 
> > broken, but it will, most probably, remain so, until someone tests and 
> > fixes it. One question though: do you know whether this imx/mxc overhaul: 
> > http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/thread.html#18844 
> > affects your driver?
> 
> I tested this yesterday, and, unfortunately, it does :(. See 
> http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/019111.html.  
> However, this issue does not affect mx27 builds. So I think this should not 
> stop the merge of this driver, for now. I hope Uwe and I will find an 
> acceptable solution before the .36 merge window opens.
Sascha already pulled my tree, but he wants to rebase it on top of his
for-2.6.35 branch, so we can sort that out, too.  I will coordinate with
him.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From tony at atomide.com  Wed Jun 30 02:33:53 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 09:33:53 +0300
Subject: [PATCH] ARM: Disable VGA console for ARM in most cases (Re: [PATCH
	1/6] omap: Disable VGA console for omaps)
In-Reply-To: <20100629142144.GN2822@atomide.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
	<20100629114720.16008.84291.stgit@baageli.muru.com>
	<20100629120724.GA23884@oksana.dev.rtsoft.ru>
	<20100629142144.GN2822@atomide.com>
Message-ID: <20100630063352.GR2822@atomide.com>

* Tony Lindgren <tony at atomide.com> [100629 17:15]:
> * Anton Vorontsov <cbouatmailru at gmail.com> [100629 15:04]:
> > On Tue, Jun 29, 2010 at 02:47:20PM +0300, Tony Lindgren wrote:
> > > Otherwise we have to disable it manually to avoid compile errors.
> > > 
> > > Cc: linux-fbdev at vger.kernel.org
> > > Signed-off-by: Tony Lindgren <tony at atomide.com>
> > 
> > We'll need this for mach-cns3xxx too. And doing that change for
> > every ARM subarch is going to produce lots of rejects.
> > 
> > I'd suggest to disable (or make it 'default n') for all ARMs,
> > except these:
> > 
> > $ git grep VGA_CONSOLE= arch/arm/configs/
> > arch/arm/configs/footbridge_defconfig:CONFIG_VGA_CONSOLE=y
> > arch/arm/configs/integrator_defconfig:CONFIG_VGA_CONSOLE=y
> > arch/arm/configs/netwinder_defconfig:CONFIG_VGA_CONSOLE=y
> 
> Good idea, will post a modified patch tomorrow.

Here's this one updated.

Tony
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From santosh.shilimkar at ti.com  Wed Jun 30 02:47:23 2010
From: santosh.shilimkar at ti.com (Shilimkar, Santosh)
Date: Wed, 30 Jun 2010 12:17:23 +0530
Subject: [PATCH 6/6] omap2/3/4: Add Kconfig option to compile in typical
	omap	features
In-Reply-To: <20100630061726.GQ2822@atomide.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
	<20100629114738.16008.62006.stgit@baageli.muru.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C5DB6FC3@dbde02.ent.ti.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C5DB7026@dbde02.ent.ti.com>
	<20100630061726.GQ2822@atomide.com>
Message-ID: <EAF47CD23C76F840A9E7FCE10091EFAB02C5E4124A@dbde02.ent.ti.com>

> -----Original Message-----
> From: Tony Lindgren [mailto:tony at atomide.com]
> Sent: Wednesday, June 30, 2010 11:47 AM
> To: Shilimkar, Santosh
> Cc: linux-arm-kernel at lists.infradead.org; linux-omap at vger.kernel.org
> Subject: Re: [PATCH 6/6] omap2/3/4: Add Kconfig option to compile in
> typical omap features
> 
> * Shilimkar, Santosh <santosh.shilimkar at ti.com> [100629 17:40]:
> > > >
> > > With your series OMAP4 build breaks because of PM and SMP
> dependencies.
> > > To ensure that build doesn't break on OMAP4, I needed below change.
> With
> > > This change I tried your series and it boots OK on OMAP4430 SDP
> 
> Hmm the build does not break for me?
>
Looks like I am missing something here. How do you build OMAP4 alone with
these new changes ??
 
> > Also tested the multi-omap build on OMAP3430 SDP and OMAP4430 SDP. Both
> boots OK.
> >
> > > diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> > > index 84fecd0..f48f275 100644
> > > --- a/arch/arm/mach-omap2/Kconfig
> > > +++ b/arch/arm/mach-omap2/Kconfig
> > > @@ -7,8 +7,8 @@ config ARCH_OMAP2PLUS_TYPICAL
> > >         default y
> > >         select AEABI
> > >         select REGULATOR
> > > -       select PM
> > > -       select PM_RUNTIME
> > > +       select PM if !ARCH_OMAP4
> > > +       select PM_RUNTIME if !ARCH_OMAP4
> > >         select VFP
> > >         select NEON if ARCH_OMAP3 || ARCH_OMAP4
> > >         select SERIAL_8250
> 
> Let's rather fix whatever the issue is for booting (or building?)
> omap4 with CONFIG_PM and CONFIG_PM_RUNTIME. If we can't implement
> PM yet for omap4, we can just return early if cpu_is_omap44xx.
> 
> CONFIG_SMP we can't enable as that requires various ARM changes
> to work on unicore systems. But hopefully we can enable that too
> at some point with select SMP if ARCH_OMAP4.
> 



From eric.y.miao at gmail.com  Wed Jun 30 02:57:57 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 30 Jun 2010 14:57:57 +0800
Subject: [PATCH 4/4] pxa/spitz: Rework spitz
In-Reply-To: <201006281729.38591.marek.vasut@gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com> 
	<201006281407.50202.marek.vasut@gmail.com>
	<AANLkTikdxoqofUUpxB1c9wSlsU-zxc-uSNMmnQX_kE8m@mail.gmail.com> 
	<201006281729.38591.marek.vasut@gmail.com>
Message-ID: <AANLkTinRkgIg1q8LfRF6jWOoxLNY__xMi3iJjEv1FhWL@mail.gmail.com>

On Mon, Jun 28, 2010 at 11:29 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dne Po 28. ?ervna 2010 14:19:46 Eric Miao napsal(a):
>> On Mon, Jun 28, 2010 at 8:07 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
>> > Dne Po 28. ?ervna 2010 05:43:12 Eric Miao napsal(a):
>> >> On Thu, Jun 24, 2010 at 10:02 PM, Marek Vasut <marek.vasut at gmail.com>
> wrote:
>> >> > This huge patch mostly shuffles code. The spitz.c file contained
>> >> > terrible mess and needed a cleanup, here it is:
>> >> >
>> >> > 1) Made every part modular, components are not built in if not
>> >> > selected. 2) Removed loads of preprocessor goo, mostly "#ifdef
>> >> > MACH_AKITA .... #endif" and similar code. The kernel size will grow
>> >> > by a few kb now, but the file is much more readable.
>> >> > 3) Reworked SD/CF power setting function and made it reentrant.
>> >> > 4) Add ISL6271A regulator support
>> >> > 5) Correctly register WM8750
>> >> >
>> >> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
>> >>
>> >> I'd prefer to see separate small patches for this?
>> >
>> > This is nearly a replacement for the whole file ... maybe we could merge
>> > spitz2.c or something ... or do it this way. I understand your point
>> > about spliting it into smaller chunks, but I don't see a reason in this
>> > case.
>>
>> I guess the above 1, 2, 3, 4, 5 can be well separated into 5 patches,
>> I don't mind merge many patches, but I'd really like to see small and
>> consistent changes (make it regression test friendly BTW), ;-)
>
> I said I get your point, but I don't see the benefit here.
> 1) already does most of the rewrite of the file,
> 2) only removes the #ifdef MACH_PLAT around MACHINE_START (as the rest was done
> in 1) ),
> 3) is actually a part of 1) as well
> 4) ok, this could be separated out, but I see no benefit
> 5) well this is already in if I recall well, but I put it here for completeness
>

Several of other comments, though:

1. It doesn't look necessary to me to change spitz_* to sharpslc_*. spitz_*
   isn't a good prefix, neither is sharpslc_* (think about the corgi series,
   which is normally called Sharp SL-C7xx). And this is also going to save
   many unnecessary changes.

2. Direct references of spitzscoop[12]_device are still there, which I'd
   prefer a cleaner patch for this

3. Others seem to be coding style changes - which can be separated


From u.kleine-koenig at pengutronix.de  Wed Jun 30 03:07:17 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 30 Jun 2010 09:07:17 +0200
Subject: [PATCHv4 1/3] mx2_camera: Add soc_camera support for i.MX25/i.MX27
In-Reply-To: <03d6e55c39690618e92a91a580ec34549a135c79.1277096909.git.baruch@tkos.co.il>
References: <cover.1277096909.git.baruch@tkos.co.il>
	<03d6e55c39690618e92a91a580ec34549a135c79.1277096909.git.baruch@tkos.co.il>
Message-ID: <20100630070717.GA11746@pengutronix.de>

On Mon, Jun 21, 2010 at 08:15:58AM +0300, Baruch Siach wrote:
> This is the soc_camera support developed by Sascha Hauer for the i.MX27.  Alan
> Carvalho de Assis modified the original driver to get it working on more recent
> kernels. I modified it further to add support for i.MX25. This driver has been
> tested on i.MX25 and i.MX27 based platforms.
> 
> Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> ---
>  arch/arm/plat-mxc/include/mach/memory.h  |    4 +-
>  arch/arm/plat-mxc/include/mach/mx2_cam.h |   46 +
>  drivers/media/video/Kconfig              |   13 +
>  drivers/media/video/Makefile             |    1 +
>  drivers/media/video/mx2_camera.c         | 1493 ++++++++++++++++++++++++++++++
>  5 files changed, 1555 insertions(+), 2 deletions(-)
>  create mode 100644 arch/arm/plat-mxc/include/mach/mx2_cam.h
>  create mode 100644 drivers/media/video/mx2_camera.c
> 
> diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
> index c4b40c3..5803836 100644
> --- a/arch/arm/plat-mxc/include/mach/memory.h
> +++ b/arch/arm/plat-mxc/include/mach/memory.h
> @@ -44,12 +44,12 @@
>   */
>  #define CONSISTENT_DMA_SIZE SZ_8M
>  
> -#elif defined(CONFIG_MX1_VIDEO)
> +#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_MX2_VIDEO)
>  /*
>   * Increase size of DMA-consistent memory region.
>   * This is required for i.MX camera driver to capture at least four VGA frames.
>   */
>  #define CONSISTENT_DMA_SIZE SZ_4M
> -#endif /* CONFIG_MX1_VIDEO */
> +#endif /* CONFIG_MX1_VIDEO || CONFIG_MX2_VIDEO */
Why not use CONFIG_VIDEO_MX2 here and get rid of CONFIG_MX2_VIDEO?
 
Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From u.kleine-koenig at pengutronix.de  Wed Jun 30 03:17:18 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 30 Jun 2010 09:17:18 +0200
Subject: [PATCH 27/61] ARM: imx: new Kconfig symbol and feature test
	macro for?DMA on mx1 and mx2
In-Reply-To: <loom.20100629T075846-421@post.gmane.org>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
	<1277387397-3467-28-git-send-email-u.kleine-koenig@pengutronix.de>
	<loom.20100629T075846-421@post.gmane.org>
Message-ID: <20100630071718.GB11746@pengutronix.de>

On Tue, Jun 29, 2010 at 06:04:52AM +0000, Baruch Siach wrote:
> Hi Uwe,
> 
> Uwe Kleine-K?nig <u.kleine-koenig <at> pengutronix.de> writes:
> > This should be used instead of hard coding the corresponding platforms.
> > The feature test macro is needed to support different SOCs in a single
> > kernel image.  While at it rename dma-mx1-mx2 to dma-v1 as mx25 doesn't
> > use it and so the mx2 part is wrong and move the header to
> > arch/arm/mach-imx.
> > 
> > Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig <at> pengutronix.de>
> 
> This commit breaks build of the (hopefully) soon to-be-merged mx2_camera driver.
> This driver is for both mx25 and mx27. Since dma-mx1-mx2.h is now under the
> non-mx25 mach-imx/ directory, mx25 build can't find this header.
> 
> The solution is either:
> 
> 1. move mx25 to mach-imx/ as well, or
> 
> 2. postpone the dma-mx1-mx2.h header move for now, and leave it under plat-mxc/

3. don't include dma-mx1-mx2.h for mx25 builds.

An mx25 kernel doesn't provide the functions declared in dma-mx1-mx2.h,
so I assume it's due to compiler optimizations that you don't get a
build failure.

I wouldn't do 1. in the .36 merge window because I want to continue with
some cleanups first.  I have no problems with 2 and can do it, but I
think 3 is more correct, though it add #ifdefery to your driver, which
is bad.  What do you think?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From u.kleine-koenig at pengutronix.de  Wed Jun 30 03:18:51 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 30 Jun 2010 09:18:51 +0200
Subject: [PATCH 26/61] ARM: imx: prepare deprecating ARCH_MX1,
	MACH_MX2, MACH_MX21 and MACH_MX27
In-Reply-To: <1277387397-3467-27-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
	<1277387397-3467-27-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20100630071851.GC11746@pengutronix.de>

On Thu, Jun 24, 2010 at 03:49:22PM +0200, Uwe Kleine-K?nig wrote:
> MACH_... is reserved for machine support, so use SOC as prefix, not MACH.
> 
> This introduces new symbols SOC_IMX1, SOC_IMX21 and SOC_IMX27.  They are
> selected by the old symbols for now.  There is no substitute for MACH_MX2
> as most usages of MX2 only means MX21 + MX27 but not MX25.
> 
> Later the choice about CPU and CPU family should go away and the individual
> machines should select the right SOC symbol.  This is a precondition to
> support more than one SOC in a single kernel image.
> 
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig at pengutronix.de>
I squash this into patch 25 as it reverts changes that currently are in
that patch but belong (only) into patch 27.

Uwe
> ---
>  arch/arm/mach-imx/Kconfig |    3 ---
>  1 files changed, 0 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index 08002df..5edead2 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -2,7 +2,6 @@ if ARCH_MX1
>  
>  config SOC_IMX1
>  	select CPU_ARM920T
> -	select IMX_HAVE_DMA_V1
>  	select IMX_HAVE_IOMUX_V1
>  	bool
>  
> @@ -28,14 +27,12 @@ if ARCH_MX2
>  config SOC_IMX21
>  	select CPU_ARM926T
>  	select ARCH_MXC_AUDMUX_V1
> -	select IMX_HAVE_DMA_V1
>  	select IMX_HAVE_IOMUX_V1
>  	bool
>  
>  config SOC_IMX27
>  	select CPU_ARM926T
>  	select ARCH_MXC_AUDMUX_V1
> -	select IMX_HAVE_DMA_V1
>  	select IMX_HAVE_IOMUX_V1
>  	bool
>  
> -- 
> 1.7.1

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From g.liakhovetski at gmx.de  Wed Jun 30 03:20:36 2010
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Wed, 30 Jun 2010 09:20:36 +0200 (CEST)
Subject: [PATCHv4 1/3] mx2_camera: Add soc_camera support for i.MX25/i.MX27
In-Reply-To: <20100630070717.GA11746@pengutronix.de>
References: <cover.1277096909.git.baruch@tkos.co.il>
	<03d6e55c39690618e92a91a580ec34549a135c79.1277096909.git.baruch@tkos.co.il>
	<20100630070717.GA11746@pengutronix.de>
Message-ID: <Pine.LNX.4.64.1006300918190.17489@axis700.grange>

On Wed, 30 Jun 2010, Uwe Kleine-K?nig wrote:

> On Mon, Jun 21, 2010 at 08:15:58AM +0300, Baruch Siach wrote:
> > This is the soc_camera support developed by Sascha Hauer for the i.MX27.  Alan
> > Carvalho de Assis modified the original driver to get it working on more recent
> > kernels. I modified it further to add support for i.MX25. This driver has been
> > tested on i.MX25 and i.MX27 based platforms.
> > 
> > Signed-off-by: Baruch Siach <baruch at tkos.co.il>
> > ---
> >  arch/arm/plat-mxc/include/mach/memory.h  |    4 +-
> >  arch/arm/plat-mxc/include/mach/mx2_cam.h |   46 +
> >  drivers/media/video/Kconfig              |   13 +
> >  drivers/media/video/Makefile             |    1 +
> >  drivers/media/video/mx2_camera.c         | 1493 ++++++++++++++++++++++++++++++
> >  5 files changed, 1555 insertions(+), 2 deletions(-)
> >  create mode 100644 arch/arm/plat-mxc/include/mach/mx2_cam.h
> >  create mode 100644 drivers/media/video/mx2_camera.c
> > 
> > diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
> > index c4b40c3..5803836 100644
> > --- a/arch/arm/plat-mxc/include/mach/memory.h
> > +++ b/arch/arm/plat-mxc/include/mach/memory.h
> > @@ -44,12 +44,12 @@
> >   */
> >  #define CONSISTENT_DMA_SIZE SZ_8M
> >  
> > -#elif defined(CONFIG_MX1_VIDEO)
> > +#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_MX2_VIDEO)
> >  /*
> >   * Increase size of DMA-consistent memory region.
> >   * This is required for i.MX camera driver to capture at least four VGA frames.
> >   */
> >  #define CONSISTENT_DMA_SIZE SZ_4M
> > -#endif /* CONFIG_MX1_VIDEO */
> > +#endif /* CONFIG_MX1_VIDEO || CONFIG_MX2_VIDEO */
> Why not use CONFIG_VIDEO_MX2 here and get rid of CONFIG_MX2_VIDEO?

Well, firstly for uniformity with MX1 and MX3, secondly not to have to use 
(CONFIG_VIDEO_MX2 || CONFIG_VIDEO_MX2_MODULE), also note, that 
CONFIG_MX1_VIDEO is also used for linking of the FIQ handler for the camera.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From tony at atomide.com  Wed Jun 30 03:24:44 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 10:24:44 +0300
Subject: [PATCH 6/6] omap2/3/4: Add Kconfig option to compile in
	typical omap	features
In-Reply-To: <EAF47CD23C76F840A9E7FCE10091EFAB02C5E4124A@dbde02.ent.ti.com>
References: <20100629113229.16008.2931.stgit@baageli.muru.com>
	<20100629114738.16008.62006.stgit@baageli.muru.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C5DB6FC3@dbde02.ent.ti.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C5DB7026@dbde02.ent.ti.com>
	<20100630061726.GQ2822@atomide.com>
	<EAF47CD23C76F840A9E7FCE10091EFAB02C5E4124A@dbde02.ent.ti.com>
Message-ID: <20100630072443.GW2822@atomide.com>

* Shilimkar, Santosh <santosh.shilimkar at ti.com> [100630 09:41]:
> > -----Original Message-----
> > From: Tony Lindgren [mailto:tony at atomide.com]
> > Sent: Wednesday, June 30, 2010 11:47 AM
> > To: Shilimkar, Santosh
> > Cc: linux-arm-kernel at lists.infradead.org; linux-omap at vger.kernel.org
> > Subject: Re: [PATCH 6/6] omap2/3/4: Add Kconfig option to compile in
> > typical omap features
> > 
> > * Shilimkar, Santosh <santosh.shilimkar at ti.com> [100629 17:40]:
> > > > >
> > > > With your series OMAP4 build breaks because of PM and SMP
> > dependencies.
> > > > To ensure that build doesn't break on OMAP4, I needed below change.
> > With
> > > > This change I tried your series and it boots OK on OMAP4430 SDP
> > 
> > Hmm the build does not break for me?
> >
> Looks like I am missing something here. How do you build OMAP4 alone with
> these new changes ??

Use your old config file, or just unselect CONFIG_ARCH_OMAP2
and CONFIG_ARCH_OMAP3. Note that if you now do:

$ yes "" | ARCH=arm make oldconfig

with your old omap4 only config file, then by default the
typical features get added by default. So what you probably
want to do is (untested):

$ echo "# CONFIG_ARCH_OMAP2PLUS_TYPICAL is not set" >> .config
$ yes "" | ARCH=arm make oldconfig

Then it should not change your old config file.

To see how the boards and features show up, you can also play
with it with make xconfig:

System Type -> TI OMAP2/3/4 Specific Features

Uncheck TI OMAP2 and TI OMAP3 so only TI OMAP4 is selected.

Regards,

Tony


From u.kleine-koenig at pengutronix.de  Wed Jun 30 03:28:08 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 30 Jun 2010 09:28:08 +0200
Subject: [PATCHv4 1/3] mx2_camera: Add soc_camera support for i.MX25/i.MX27
In-Reply-To: <Pine.LNX.4.64.1006300918190.17489@axis700.grange>
References: <cover.1277096909.git.baruch@tkos.co.il>
	<03d6e55c39690618e92a91a580ec34549a135c79.1277096909.git.baruch@tkos.co.il>
	<20100630070717.GA11746@pengutronix.de>
	<Pine.LNX.4.64.1006300918190.17489@axis700.grange>
Message-ID: <20100630072808.GD11746@pengutronix.de>

Hi Guennadi,

On Wed, Jun 30, 2010 at 09:20:36AM +0200, Guennadi Liakhovetski wrote:
> > > --- a/arch/arm/plat-mxc/include/mach/memory.h
> > > +++ b/arch/arm/plat-mxc/include/mach/memory.h
> > > @@ -44,12 +44,12 @@
> > >   */
> > >  #define CONSISTENT_DMA_SIZE SZ_8M
> > >  
> > > -#elif defined(CONFIG_MX1_VIDEO)
> > > +#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_MX2_VIDEO)
> > >  /*
> > >   * Increase size of DMA-consistent memory region.
> > >   * This is required for i.MX camera driver to capture at least four VGA frames.
> > >   */
> > >  #define CONSISTENT_DMA_SIZE SZ_4M
> > > -#endif /* CONFIG_MX1_VIDEO */
> > > +#endif /* CONFIG_MX1_VIDEO || CONFIG_MX2_VIDEO */
> > Why not use CONFIG_VIDEO_MX2 here and get rid of CONFIG_MX2_VIDEO?
> 
> Well, firstly for uniformity with MX1 and MX3,
Using a common scheme for names on all platforms is fine, but if the
existing names are bad better establish a nicer scheme.

>                                                secondly not to have to use 
> (CONFIG_VIDEO_MX2 || CONFIG_VIDEO_MX2_MODULE),
ah, didn't notice that MX?_VIDEO is bool while VIDEO_MX? is tristate.
That's fine.  Still I would prefer a better naming that doesn't force
having to look up which variable is for the driver and which is for the
arch stuff.

>                                                also note, that 
> CONFIG_MX1_VIDEO is also used for linking of the FIQ handler for the camera.
This is just a matter of fixing the corresponding Makefile.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From u.kleine-koenig at pengutronix.de  Wed Jun 30 03:37:06 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 30 Jun 2010 09:37:06 +0200
Subject: [PATCH 21/61] ARM: mx3: mx31lilly: fix build error for
	!CONFIG_USB_ULPI
In-Reply-To: <1277387397-3467-22-git-send-email-u.kleine-koenig@pengutronix.de>
References: <1277387397-3467-1-git-send-email-u.kleine-koenig@pengutronix.de>
	<1277387397-3467-22-git-send-email-u.kleine-koenig@pengutronix.de>
Message-ID: <20100630073706.GE11746@pengutronix.de>

On Thu, Jun 24, 2010 at 03:49:17PM +0200, Uwe Kleine-K?nig wrote:
> arch/arm/mach-mx3/built-in.o: In function `mx31lilly_board_init':
> mach-kzm_arm11_01.c:(.init.text+0x674): undefined reference to `otg_ulpi_create'
> mach-kzm_arm11_01.c:(.init.text+0x68c): undefined reference to `otg_ulpi_create'
> mach-kzm_arm11_01.c:(.init.text+0x744): undefined reference to `mxc_ulpi_access_ops'
> make: *** [.tmp_vmlinux1] Error 1
> 
> Signed-off-by: Daniel Mack <daniel at caiaq.de>
> Cc: Sascha Hauer <s.hauer at pengutronix.de>
> Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
I dropped this from my series as it's only cherry-picked from Sascha's
tree for my build tests.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From linus.ml.walleij at gmail.com  Wed Jun 30 04:13:59 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Wed, 30 Jun 2010 10:13:59 +0200
Subject: [PATCH] ARM: RealView: Do not use outer_sync() on certain with 
	L210/L220
In-Reply-To: <20100629093135.10365.99959.stgit@e102109-lin.cambridge.arm.com>
References: <20100629093135.10365.99959.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <AANLkTinpAz52QfsnvzIY5fleJoflVr0Z40JpRNrlXY9k@mail.gmail.com>

2010/6/29 Catalin Marinas <catalin.marinas at arm.com>:

> RealView boards with certain revisions of the L210/L220 cache controller
> may have issues (hardware deadlock) with the recent changes to the mb()
> barrier implementation (DSB followed by an L2 cache sync). The patch
> disables ARM_DMA_MEM_BUFFERABLE for the RealView boards with L210/L220
> and redefines the mandatory barriers without the outer_sync() call.
>
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Linus Walleij <linus.ml.walleij at gmail.com>

Works like a charm on the PB1176!

Tested-by: Linus Walleij <linus.walleij at stericsson.com>

Yours,
Linus Walleij


From zpfeffer at codeaurora.org  Wed Jun 30 01:55:49 2010
From: zpfeffer at codeaurora.org (Zach Pfeffer)
Date: Tue, 29 Jun 2010 22:55:49 -0700
Subject: [RFC 2/3] mm: iommu: A physical allocator for the VCMM
In-Reply-To: <1277877350-2147-1-git-send-email-zpfeffer@codeaurora.org>
References: <1277877350-2147-1-git-send-email-zpfeffer@codeaurora.org>
Message-ID: <1277877350-2147-2-git-send-email-zpfeffer@codeaurora.org>

The Virtual Contiguous Memory Manager (VCMM) needs a physical pool to
allocate from. It breaks up the pool into sub-pools of same-sized
chunks. In particular, it breaks the pool it manages into sub-pools of
1 MB, 64 KB and 4 KB chunks.

When a user makes a request, this allocator satisfies that request
from the sub-pools using a "maximum-munch" strategy. This strategy
attempts to satisfy a request using the largest chunk-size without
over-allocating, then moving on to the next smallest size without
over-allocating and finally completing the request with the smallest
sized chunk, over-allocating if necessary.

The maximum-munch strategy allows physical page allocation for small
TLBs that need to map a given range using the minimum number of mappings.

Although the allocator has been configured for 1 MB, 64 KB and 4 KB
chunks, it can be easily extended to other chunk sizes.

Signed-off-by: Zach Pfeffer <zpfeffer at codeaurora.org>
---
 arch/arm/mm/vcm_alloc.c   |  425 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/vcm_alloc.h |   70 ++++++++
 2 files changed, 495 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mm/vcm_alloc.c
 create mode 100644 include/linux/vcm_alloc.h

diff --git a/arch/arm/mm/vcm_alloc.c b/arch/arm/mm/vcm_alloc.c
new file mode 100644
index 0000000..e592e71
--- /dev/null
+++ b/arch/arm/mm/vcm_alloc.c
@@ -0,0 +1,425 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/vcm_alloc.h>
+#include <linux/string.h>
+#include <asm/sizes.h>
+
+/* Amount of memory managed by VCM */
+#define TOTAL_MEM_SIZE SZ_32M
+
+static unsigned int base_pa = 0x80000000;
+int basicalloc_init;
+
+int chunk_sizes[NUM_CHUNK_SIZES] = {SZ_1M, SZ_64K, SZ_4K};
+int init_num_chunks[] = {
+	(TOTAL_MEM_SIZE/2) / SZ_1M,
+	(TOTAL_MEM_SIZE/4) / SZ_64K,
+	(TOTAL_MEM_SIZE/4) / SZ_4K
+};
+#define LAST_SZ() (ARRAY_SIZE(chunk_sizes) - 1)
+
+#define vcm_alloc_err(a, ...)						\
+	pr_err("ERROR %s %i " a, __func__, __LINE__, ##__VA_ARGS__)
+
+struct phys_chunk_head {
+	struct list_head head;
+	int num;
+};
+
+struct phys_mem {
+	struct phys_chunk_head heads[ARRAY_SIZE(chunk_sizes)];
+} phys_mem;
+
+static int is_allocated(struct list_head *allocated)
+{
+	/* This should not happen under normal conditions */
+	if (!allocated) {
+		vcm_alloc_err("no allocated\n");
+		return 0;
+	}
+
+	if (!basicalloc_init) {
+		vcm_alloc_err("no basicalloc_init\n");
+		return 0;
+	}
+	return !list_empty(allocated);
+}
+
+static int count_allocated_size(enum chunk_size_idx idx)
+{
+	int cnt = 0;
+	struct phys_chunk *chunk, *tmp;
+
+	if (!basicalloc_init) {
+		vcm_alloc_err("no basicalloc_init\n");
+		return 0;
+	}
+
+	list_for_each_entry_safe(chunk, tmp,
+				 &phys_mem.heads[idx].head, list) {
+		if (is_allocated(&chunk->allocated))
+			cnt++;
+	}
+
+	return cnt;
+}
+
+
+int vcm_alloc_get_mem_size(void)
+{
+	return TOTAL_MEM_SIZE;
+}
+EXPORT_SYMBOL(vcm_alloc_get_mem_size);
+
+
+int vcm_alloc_blocks_avail(enum chunk_size_idx idx)
+{
+	if (!basicalloc_init) {
+		vcm_alloc_err("no basicalloc_init\n");
+		return 0;
+	}
+
+	return phys_mem.heads[idx].num;
+}
+EXPORT_SYMBOL(vcm_alloc_blocks_avail);
+
+
+int vcm_alloc_get_num_chunks(void)
+{
+	return ARRAY_SIZE(chunk_sizes);
+}
+EXPORT_SYMBOL(vcm_alloc_get_num_chunks);
+
+
+int vcm_alloc_all_blocks_avail(void)
+{
+	int i;
+	int cnt = 0;
+
+	if (!basicalloc_init) {
+		vcm_alloc_err("no basicalloc_init\n");
+		return 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i)
+		cnt += vcm_alloc_blocks_avail(i);
+	return cnt;
+}
+EXPORT_SYMBOL(vcm_alloc_all_blocks_avail);
+
+
+int vcm_alloc_count_allocated(void)
+{
+	int i;
+	int cnt = 0;
+
+	if (!basicalloc_init) {
+		vcm_alloc_err("no basicalloc_init\n");
+		return 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i)
+		cnt += count_allocated_size(i);
+	return cnt;
+}
+EXPORT_SYMBOL(vcm_alloc_count_allocated);
+
+
+void vcm_alloc_print_list(int just_allocated)
+{
+	int i;
+	struct phys_chunk *chunk, *tmp;
+
+	if (!basicalloc_init) {
+		vcm_alloc_err("no basicalloc_init\n");
+		return;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i) {
+		if (list_empty(&phys_mem.heads[i].head))
+			continue;
+		list_for_each_entry_safe(chunk, tmp,
+					 &phys_mem.heads[i].head, list) {
+			if (just_allocated && !is_allocated(&chunk->allocated))
+				continue;
+
+			printk(KERN_INFO "pa = %#x, size = %#x\n",
+			       chunk->pa, chunk_sizes[chunk->size_idx]);
+		}
+	}
+}
+EXPORT_SYMBOL(vcm_alloc_print_list);
+
+
+int vcm_alloc_idx_to_size(int idx)
+{
+	return chunk_sizes[idx];
+}
+EXPORT_SYMBOL(vcm_alloc_idx_to_size);
+
+
+int vcm_alloc_destroy(void)
+{
+	int i;
+	struct phys_chunk *chunk, *tmp;
+
+	if (!basicalloc_init) {
+		vcm_alloc_err("no basicalloc_init\n");
+		return -1;
+	}
+
+	/* can't destroy a space that has allocations */
+	if (vcm_alloc_count_allocated()) {
+		vcm_alloc_err("allocations still present\n");
+		return -1;
+	}
+	for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i) {
+
+		if (list_empty(&phys_mem.heads[i].head))
+			continue;
+		list_for_each_entry_safe(chunk, tmp,
+					 &phys_mem.heads[i].head, list) {
+			list_del(&chunk->list);
+			memset(chunk, 0, sizeof(*chunk));
+			kfree(chunk);
+		}
+	}
+
+	basicalloc_init = 0;
+
+	return 0;
+}
+EXPORT_SYMBOL(vcm_alloc_destroy);
+
+
+int vcm_alloc_init(unsigned int set_base_pa)
+{
+	int i = 0, j = 0;
+	struct phys_chunk *chunk;
+	int pa;
+
+	if (set_base_pa)
+		base_pa = set_base_pa;
+
+	pa = base_pa;
+
+	/* no double inits */
+	if (basicalloc_init) {
+		vcm_alloc_err("double basicalloc_init\n");
+		BUG();
+		return -1;
+	}
+
+	/* separate out to ensure good cleanup */
+	for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i) {
+		INIT_LIST_HEAD(&phys_mem.heads[i].head);
+		phys_mem.heads[i].num = 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i) {
+		for (j = 0; j < init_num_chunks[i]; ++j) {
+			chunk = kzalloc(sizeof(*chunk), GFP_KERNEL);
+			if (!chunk) {
+				vcm_alloc_err("null chunk\n");
+				goto fail;
+			}
+			chunk->pa = pa; pa += chunk_sizes[i];
+			chunk->size_idx = i;
+			INIT_LIST_HEAD(&chunk->allocated);
+			list_add_tail(&chunk->list, &phys_mem.heads[i].head);
+			phys_mem.heads[i].num++;
+		}
+	}
+
+	basicalloc_init = 1;
+	return 0;
+fail:
+	vcm_alloc_destroy();
+	return -1;
+}
+EXPORT_SYMBOL(vcm_alloc_init);
+
+
+int vcm_alloc_free_blocks(struct phys_chunk *alloc_head)
+{
+	struct phys_chunk *chunk, *tmp;
+
+	if (!basicalloc_init) {
+		vcm_alloc_err("no basicalloc_init\n");
+		goto fail;
+	}
+
+	if (!alloc_head) {
+		vcm_alloc_err("no alloc_head\n");
+		goto fail;
+	}
+
+	list_for_each_entry_safe(chunk, tmp, &alloc_head->allocated,
+				 allocated) {
+		list_del_init(&chunk->allocated);
+		phys_mem.heads[chunk->size_idx].num++;
+	}
+
+	return 0;
+fail:
+	return -1;
+}
+EXPORT_SYMBOL(vcm_alloc_free_blocks);
+
+
+int vcm_alloc_num_blocks(int num,
+			 enum chunk_size_idx idx, /* chunk size */
+			 struct phys_chunk *alloc_head)
+{
+	struct phys_chunk *chunk;
+	int num_allocated = 0;
+
+	if (!basicalloc_init) {
+		vcm_alloc_err("no basicalloc_init\n");
+		goto fail;
+	}
+
+	if (!alloc_head) {
+		vcm_alloc_err("no alloc_head\n");
+		goto fail;
+	}
+
+	if (list_empty(&phys_mem.heads[idx].head)) {
+		vcm_alloc_err("list is empty\n");
+		goto fail;
+	}
+
+	if (vcm_alloc_blocks_avail(idx) < num) {
+		vcm_alloc_err("not enough blocks? num=%d\n", num);
+		goto fail;
+	}
+
+	list_for_each_entry(chunk, &phys_mem.heads[idx].head, list) {
+		if (num_allocated == num)
+			break;
+		if (is_allocated(&chunk->allocated))
+			continue;
+
+		list_add_tail(&chunk->allocated, &alloc_head->allocated);
+		phys_mem.heads[idx].num--;
+		num_allocated++;
+	}
+	return num_allocated;
+fail:
+	return 0;
+}
+EXPORT_SYMBOL(vcm_alloc_num_blocks);
+
+
+int vcm_alloc_max_munch(int len,
+			struct phys_chunk *alloc_head)
+{
+	int i;
+
+	int blocks_req = 0;
+	int block_residual = 0;
+	int blocks_allocated = 0;
+
+	int ba = 0;
+
+	if (!basicalloc_init) {
+		vcm_alloc_err("basicalloc_init is 0\n");
+		goto fail;
+	}
+
+	if (!alloc_head) {
+		vcm_alloc_err("alloc_head is NULL\n");
+		goto fail;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(chunk_sizes); ++i) {
+		blocks_req = len / chunk_sizes[i];
+		block_residual = len % chunk_sizes[i];
+
+		len = block_residual; /* len left */
+		if (blocks_req) {
+			int blocks_available = 0;
+			int blocks_diff = 0;
+			int bytes_diff = 0;
+
+			blocks_available = vcm_alloc_blocks_avail(i);
+			if (blocks_available < blocks_req) {
+				blocks_diff =
+					(blocks_req - blocks_available);
+				bytes_diff =
+					blocks_diff * chunk_sizes[i];
+
+				/* add back in the rest */
+				len += bytes_diff;
+			} else {
+				/* got all the blocks I need */
+				blocks_available =
+					(blocks_available > blocks_req)
+					? blocks_req : blocks_available;
+			}
+
+			ba = vcm_alloc_num_blocks(blocks_available, i,
+						  alloc_head);
+
+			if (ba != blocks_available) {
+				vcm_alloc_err("blocks allocated (%i) !="
+					      " blocks_available (%i):"
+					      " chunk size = %#x,"
+					      " alloc_head = %p\n",
+					      ba, blocks_available,
+					      i, (void *) alloc_head);
+				goto fail;
+			}
+			blocks_allocated += blocks_available;
+		}
+	}
+
+	if (len) {
+		int blocks_available = 0;
+
+		blocks_available = vcm_alloc_blocks_avail(LAST_SZ());
+
+		if (blocks_available > 1) {
+			ba = vcm_alloc_num_blocks(1, LAST_SZ(), alloc_head);
+			if (ba != 1) {
+				vcm_alloc_err("blocks allocated (%i) !="
+					      " blocks_available (%i):"
+					      " chunk size = %#x,"
+					      " alloc_head = %p\n",
+					      ba, 1,
+					      LAST_SZ(),
+					      (void *) alloc_head);
+				goto fail;
+			}
+			blocks_allocated += 1;
+		} else {
+			vcm_alloc_err("blocks_available (%#x) <= 1\n",
+				      blocks_available);
+			goto fail;
+		}
+	}
+
+	return blocks_allocated;
+fail:
+	vcm_alloc_free_blocks(alloc_head);
+	return 0;
+}
+EXPORT_SYMBOL(vcm_alloc_max_munch);
diff --git a/include/linux/vcm_alloc.h b/include/linux/vcm_alloc.h
new file mode 100644
index 0000000..e3e3b31
--- /dev/null
+++ b/include/linux/vcm_alloc.h
@@ -0,0 +1,70 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef VCM_ALLOC_H
+#define VCM_ALLOC_H
+
+#include <linux/list.h>
+
+#define NUM_CHUNK_SIZES 3
+
+enum chunk_size_idx {
+	IDX_1M = 0,
+	IDX_64K,
+	IDX_4K
+};
+
+struct phys_chunk {
+	struct list_head list;
+	struct list_head allocated; /* used to record is allocated */
+
+	struct list_head refers_to;
+
+	/* TODO: change to unsigned long */
+	int pa;
+	int size_idx;
+};
+
+int vcm_alloc_get_mem_size(void);
+int vcm_alloc_blocks_avail(enum chunk_size_idx idx);
+int vcm_alloc_get_num_chunks(void);
+int vcm_alloc_all_blocks_avail(void);
+int vcm_alloc_count_allocated(void);
+void vcm_alloc_print_list(int just_allocated);
+int vcm_alloc_idx_to_size(int idx);
+int vcm_alloc_destroy(void);
+int vcm_alloc_init(unsigned int set_base_pa);
+int vcm_alloc_free_blocks(struct phys_chunk *alloc_head);
+int vcm_alloc_num_blocks(int num,
+			 enum chunk_size_idx idx, /* chunk size */
+			 struct phys_chunk *alloc_head);
+int vcm_alloc_max_munch(int len,
+			struct phys_chunk *alloc_head);
+
+#endif /* VCM_ALLOC_H */
-- 
1.7.0.2



From zpfeffer at codeaurora.org  Wed Jun 30 01:55:50 2010
From: zpfeffer at codeaurora.org (Zach Pfeffer)
Date: Tue, 29 Jun 2010 22:55:50 -0700
Subject: [RFC 3/3] mm: iommu: The Virtual Contiguous Memory Manager
In-Reply-To: <1277877350-2147-1-git-send-email-zpfeffer@codeaurora.org>
References: <1277877350-2147-1-git-send-email-zpfeffer@codeaurora.org>
Message-ID: <1277877350-2147-3-git-send-email-zpfeffer@codeaurora.org>

The Virtual Contiguous Memory Manager (VCMM) allows the CPU, IOMMU
devices and physically mapped devices to map the same physical memory
using a common API. It achieves this by abstracting mapping into graph
management.

Within the graph abstraction, the device end-points are CPUs with and
without MMUs and devices with and without IOMMUs. The mapped memory is
the other end-point. In the [IO]MMU case this is readily apparent. In
the non-[IO]MMU case, it is as apparent if you give each device a
"one-to-one" mapper. These mappings are wrapped up into "reservations"
represented by struct res's.

Also part of this graph is a mapping of a virtual space, struct vcm,
to a device. One virtual space may be associated with multiple devices
and multiple virtual-spaces may be associated with the same device. In
the case of a one-to-one device this virtual-space mirrors the
physical-space. A virtual-space is tied to a device using a
"association", a struct avcm. A device may be associated with a
virtual-space without being programed to translate based on that
virtual-space. Programming occurs using an activate call.

The physical side of the mapping (or intermediate address-space side
in virtualized environments) is represented by a struct physmem. Due to
the peculiar needs of various IOMMUs, the VCM contains a physical
allocation subsystem that manages blocks of different sizes from
different pools. This allows fine grained control of block and
physical placement, a feature many advanced IOMMU devices need.

Once a user has made a reservation on a VCM and allocated physical
memory, the two graph end-points are joined in a backing step. This
step allows multiple reservations to map the same physical location.

Many of the functions in the API take various attributes that provide
fine grained control of the objects they create. For instance,
reservations can map cachable memory and physical allocations can be
constrained to use a particular subset of block sizes.

Signed-off-by: Zach Pfeffer <zpfeffer at codeaurora.org>
---
 arch/arm/mm/vcm.c         | 1901 +++++++++++++++++++++++++++++++++++++++++++++
 include/linux/vcm.h       |  701 +++++++++++++++++
 include/linux/vcm_types.h |  318 ++++++++
 3 files changed, 2920 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mm/vcm.c
 create mode 100644 include/linux/vcm.h
 create mode 100644 include/linux/vcm_types.h

diff --git a/arch/arm/mm/vcm.c b/arch/arm/mm/vcm.c
new file mode 100644
index 0000000..04ff2d4
--- /dev/null
+++ b/arch/arm/mm/vcm.c
@@ -0,0 +1,1901 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/vcm_mm.h>
+#include <linux/vcm.h>
+#include <linux/vcm_types.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+
+#include <asm/page.h>
+#include <asm/sizes.h>
+
+#ifdef CONFIG_SMMU
+#include <mach/smmu_driver.h>
+#endif
+
+/* alloc_vm_area */
+#include <linux/pfn.h>
+#include <linux/mm.h>
+#include <linux/vmalloc.h>
+
+/* may be temporary */
+#include <linux/bootmem.h>
+
+#include <asm/cacheflush.h>
+#include <asm/mach/map.h>
+
+#define BOOTMEM_SZ	SZ_32M
+#define BOOTMEM_ALIGN	SZ_1M
+
+#define CONT_SZ		SZ_8M
+#define CONT_ALIGN	SZ_1M
+
+#define ONE_TO_ONE_CHK 1
+
+#define vcm_err(a, ...)							\
+	pr_err("ERROR %s %i " a, __func__, __LINE__, ##__VA_ARGS__)
+
+static void *bootmem;
+static void *bootmem_cont;
+static struct vcm *cont_vcm_id;
+static struct phys_chunk *cont_phys_chunk;
+
+DEFINE_SPINLOCK(vcmlock);
+
+static int vcm_no_res(struct vcm *vcm)
+{
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	return list_empty(&vcm->res_head);
+fail:
+	return -EINVAL;
+}
+
+static int vcm_no_assoc(struct vcm *vcm)
+{
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	return list_empty(&vcm->assoc_head);
+fail:
+	return -EINVAL;
+}
+
+static int vcm_all_activated(struct vcm *vcm)
+{
+	struct avcm *avcm;
+
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	list_for_each_entry(avcm, &vcm->assoc_head, assoc_elm)
+		if (!avcm->is_active)
+			return 0;
+
+	return 1;
+fail:
+	return -1;
+}
+
+static void vcm_destroy_common(struct vcm *vcm)
+{
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		return;
+	}
+
+	memset(vcm, 0, sizeof(*vcm));
+	kfree(vcm);
+}
+
+static struct vcm *vcm_create_common(void)
+{
+	struct vcm *vcm = 0;
+
+	vcm = kzalloc(sizeof(*vcm), GFP_KERNEL);
+	if (!vcm) {
+		vcm_err("kzalloc(%i, GFP_KERNEL) ret 0\n",
+			sizeof(*vcm));
+		goto fail;
+	}
+
+	INIT_LIST_HEAD(&vcm->res_head);
+	INIT_LIST_HEAD(&vcm->assoc_head);
+
+	return vcm;
+
+fail:
+	return NULL;
+}
+
+
+static int vcm_create_pool(struct vcm *vcm, size_t start_addr, size_t len)
+{
+	int ret = 0;
+
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	vcm->start_addr = start_addr;
+	vcm->len = len;
+
+	vcm->pool = gen_pool_create(PAGE_SHIFT, -1);
+	if (!vcm->pool) {
+		vcm_err("gen_pool_create(%x, -1) ret 0\n", PAGE_SHIFT);
+		goto fail;
+	}
+
+	ret = gen_pool_add(vcm->pool, start_addr, len, -1);
+	if (ret) {
+		vcm_err("gen_pool_add(%p, %p, %i, -1) ret %i\n", vcm->pool,
+			(void *) start_addr, len, ret);
+		goto fail2;
+	}
+
+	return 0;
+
+fail2:
+	gen_pool_destroy(vcm->pool);
+fail:
+	return -1;
+}
+
+
+static struct vcm *vcm_create_flagged(int flag, size_t start_addr, size_t len)
+{
+	int ret = 0;
+	struct vcm *vcm = 0;
+
+	vcm = vcm_create_common();
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	/* special one-to-one mapping case */
+	if ((flag & ONE_TO_ONE_CHK) &&
+	    bootmem_cont &&
+	    __pa(bootmem_cont) &&
+	    start_addr == __pa(bootmem_cont) &&
+	    len == CONT_SZ) {
+		vcm->type = VCM_ONE_TO_ONE;
+	} else {
+		ret = vcm_create_pool(vcm, start_addr, len);
+		vcm->type = VCM_DEVICE;
+	}
+
+	if (ret) {
+		vcm_err("vcm_create_pool(%p, %p, %i) ret %i\n", vcm,
+			(void *) start_addr, len, ret);
+		goto fail2;
+	}
+
+	return vcm;
+
+fail2:
+	vcm_destroy_common(vcm);
+fail:
+	return NULL;
+}
+
+struct vcm *vcm_create(size_t start_addr, size_t len)
+{
+	unsigned long flags;
+	struct vcm *vcm;
+
+	spin_lock_irqsave(&vcmlock, flags);
+	vcm = vcm_create_flagged(ONE_TO_ONE_CHK, start_addr, len);
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return vcm;
+}
+
+
+static int ext_vcm_id_valid(size_t ext_vcm_id)
+{
+	return ((ext_vcm_id == VCM_PREBUILT_KERNEL) ||
+		(ext_vcm_id == VCM_PREBUILT_USER));
+}
+
+
+struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id)
+{
+	unsigned long flags;
+	struct vcm *vcm = 0;
+
+	spin_lock_irqsave(&vcmlock, flags);
+
+	if (!ext_vcm_id_valid(ext_vcm_id)) {
+		vcm_err("ext_vcm_id_valid(%i) ret 0\n", ext_vcm_id);
+		goto fail;
+	}
+
+	vcm = vcm_create_common();
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	if (ext_vcm_id == VCM_PREBUILT_KERNEL)
+		vcm->type = VCM_EXT_KERNEL;
+	else if (ext_vcm_id == VCM_PREBUILT_USER)
+		vcm->type = VCM_EXT_USER;
+	else {
+		vcm_err("UNREACHABLE ext_vcm_id is illegal\n");
+		goto fail_free;
+	}
+
+	/* TODO: set kernel and userspace start_addr and len, if this
+	 * makes sense */
+
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return vcm;
+
+fail_free:
+	vcm_destroy_common(vcm);
+fail:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return NULL;
+}
+
+
+struct vcm *vcm_clone(struct vcm *vcm_id)
+{
+	return 0;
+}
+
+
+/* No lock needed, vcm->start_addr is never updated after creation */
+size_t vcm_get_start_addr(struct vcm *vcm)
+{
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		return 1;
+	}
+
+	return vcm->start_addr;
+}
+
+
+/* No lock needed, vcm->len is never updated after creation */
+size_t vcm_get_len(struct vcm *vcm)
+{
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		return 0;
+	}
+
+	return vcm->len;
+}
+
+
+static int vcm_free_common_rule(struct vcm *vcm)
+{
+	int ret;
+
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	ret = vcm_no_res(vcm);
+	if (!ret) {
+		vcm_err("vcm_no_res(%p) ret 0\n", vcm);
+		goto fail_busy;
+	}
+
+	if (ret == -EINVAL) {
+		vcm_err("vcm_no_res(%p) ret -EINVAL\n", vcm);
+		goto fail;
+	}
+
+	ret = vcm_no_assoc(vcm);
+	if (!ret) {
+		vcm_err("vcm_no_assoc(%p) ret 0\n", vcm);
+		goto fail_busy;
+	}
+
+	if (ret == -EINVAL) {
+		vcm_err("vcm_no_assoc(%p) ret -EINVAL\n", vcm);
+		goto fail;
+	}
+
+	return 0;
+
+fail_busy:
+	return -EBUSY;
+fail:
+	return -EINVAL;
+}
+
+
+static int vcm_free_pool_rule(struct vcm *vcm)
+{
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	/* A vcm always has a valid pool, don't free the vcm because
+	   what we got is probably invalid.
+	*/
+	if (!vcm->pool) {
+		vcm_err("NULL vcm->pool\n");
+		goto fail;
+	}
+
+	return 0;
+
+fail:
+	return -EINVAL;
+}
+
+
+static void vcm_free_common(struct vcm *vcm)
+{
+	memset(vcm, 0, sizeof(*vcm));
+
+	kfree(vcm);
+}
+
+
+static int vcm_free_pool(struct vcm *vcm)
+{
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	gen_pool_destroy(vcm->pool);
+
+	return 0;
+
+fail:
+	return -1;
+}
+
+
+static int __vcm_free(struct vcm *vcm)
+{
+	int ret;
+
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	ret = vcm_free_common_rule(vcm);
+	if (ret != 0) {
+		vcm_err("vcm_free_common_rule(%p) ret %i\n", vcm, ret);
+		goto fail;
+	}
+
+	if (vcm->type == VCM_DEVICE) {
+		ret = vcm_free_pool_rule(vcm);
+		if (ret != 0) {
+			vcm_err("vcm_free_pool_rule(%p) ret %i\n",
+				(void *) vcm, ret);
+			goto fail;
+		}
+
+		ret = vcm_free_pool(vcm);
+		if (ret != 0) {
+			vcm_err("vcm_free_pool(%p) ret %i", (void *) vcm, ret);
+			goto fail;
+		}
+	}
+
+	vcm_free_common(vcm);
+
+	return 0;
+
+fail:
+	return -EINVAL;
+}
+
+int vcm_free(struct vcm *vcm)
+{
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&vcmlock, flags);
+	ret = __vcm_free(vcm);
+	spin_unlock_irqrestore(&vcmlock, flags);
+
+	return ret;
+}
+
+
+static struct res *__vcm_reserve(struct vcm *vcm, size_t len, uint32_t attr)
+{
+	struct res *res = NULL;
+
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	if (len == 0) {
+		vcm_err("len is 0\n");
+		goto fail;
+	}
+
+	res = kzalloc(sizeof(*res), GFP_KERNEL);
+	if (!res) {
+		vcm_err("kzalloc(%i, GFP_KERNEL) ret 0", sizeof(*res));
+		goto fail;
+	}
+
+	INIT_LIST_HEAD(&res->res_elm);
+	res->vcm_id = vcm;
+	res->len = len;
+	res->attr = attr;
+
+	if (len/SZ_1M)
+		res->alignment_req = SZ_1M;
+	else if (len/SZ_64K)
+		res->alignment_req = SZ_64K;
+	else
+		res->alignment_req = SZ_4K;
+
+	res->aligned_len = res->alignment_req + len;
+
+	switch (vcm->type) {
+	case VCM_DEVICE:
+		/* should always be not zero */
+		if (!vcm->pool) {
+			vcm_err("NULL vcm->pool\n");
+			goto fail2;
+		}
+
+		res->ptr = gen_pool_alloc(vcm->pool, res->aligned_len);
+		if (!res->ptr) {
+			vcm_err("gen_pool_alloc(%p, %i) ret 0\n",
+				vcm->pool, res->aligned_len);
+			goto fail2;
+		}
+
+		/* Calculate alignment... this will all change anyway */
+		res->aligned_ptr = res->ptr +
+			(res->alignment_req -
+			 (res->ptr & (res->alignment_req - 1)));
+
+		break;
+	case VCM_EXT_KERNEL:
+		res->vm_area = alloc_vm_area(res->aligned_len);
+		res->mapped = 0; /* be explicit */
+		if (!res->vm_area) {
+			vcm_err("NULL res->vm_area\n");
+			goto fail2;
+		}
+
+		res->aligned_ptr = (size_t) res->vm_area->addr +
+			(res->alignment_req -
+			 ((size_t) res->vm_area->addr &
+			  (res->alignment_req - 1)));
+
+		break;
+	case VCM_ONE_TO_ONE:
+		break;
+	default:
+		vcm_err("%i is an invalid vcm->type\n", vcm->type);
+		goto fail2;
+	}
+
+	list_add_tail(&res->res_elm, &vcm->res_head);
+
+	return res;
+
+fail2:
+	kfree(res);
+fail:
+	return 0;
+}
+
+
+struct res *vcm_reserve(struct vcm *vcm, size_t len, uint32_t attr)
+{
+	unsigned long flags;
+	struct res *res;
+
+	spin_lock_irqsave(&vcmlock, flags);
+	res = __vcm_reserve(vcm, len, attr);
+	spin_unlock_irqrestore(&vcmlock, flags);
+
+	return res;
+}
+
+
+struct res *vcm_reserve_at(enum memtarget_t memtarget, struct vcm* vcm,
+		     size_t len, uint32_t attr)
+{
+	return 0;
+}
+
+
+/* No lock needed, res->vcm_id is never updated after creation */
+struct vcm *vcm_get_vcm_from_res(struct res *res)
+{
+	if (!res) {
+		vcm_err("NULL res\n");
+		return 0;
+	}
+
+	return res->vcm_id;
+}
+
+
+static int __vcm_unreserve(struct res *res)
+{
+	struct vcm *vcm;
+
+	if (!res) {
+		vcm_err("NULL res\n");
+		goto fail;
+	}
+
+	if (!res->vcm_id) {
+		vcm_err("NULL res->vcm_id\n");
+		goto fail;
+	}
+
+	vcm = res->vcm_id;
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	switch (vcm->type) {
+	case VCM_DEVICE:
+		if (!res->vcm_id->pool) {
+			vcm_err("NULL (res->vcm_id))->pool\n");
+			goto fail;
+		}
+
+		/* res->ptr could be zero, this isn't an error */
+		gen_pool_free(res->vcm_id->pool, res->ptr,
+			      res->aligned_len);
+		break;
+	case VCM_EXT_KERNEL:
+		if (res->mapped) {
+			vcm_err("res->mapped is true\n");
+			goto fail;
+		}
+
+		/* This may take a little explaining.
+		 * In the kernel vunmap will free res->vm_area
+		 * so if we've called it then we shouldn't call
+		 * free_vm_area(). If we've called it we set
+		 * res->vm_area to 0.
+		 */
+		if (res->vm_area) {
+			free_vm_area(res->vm_area);
+			res->vm_area = 0;
+		}
+
+		break;
+	case VCM_ONE_TO_ONE:
+		break;
+	default:
+		vcm_err("%i is an invalid vcm->type\n", vcm->type);
+		goto fail;
+	}
+
+	list_del(&res->res_elm);
+
+	/* be extra careful by clearing the memory before freeing it */
+	memset(res, 0, sizeof(*res));
+
+	kfree(res);
+
+	return 0;
+
+fail:
+	return -EINVAL;
+}
+
+
+int vcm_unreserve(struct res *res)
+{
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&vcmlock, flags);
+	ret = __vcm_unreserve(res);
+	spin_unlock_irqrestore(&vcmlock, flags);
+
+	return ret;
+}
+
+
+/* No lock needed, res->len is never updated after creation */
+size_t vcm_get_res_len(struct res *res)
+{
+	if (!res) {
+		vcm_err("res is 0\n");
+		return 0;
+	}
+
+	return res->len;
+}
+
+
+int vcm_set_res_attr(struct res *res, uint32_t attr)
+{
+	return 0;
+}
+
+
+uint32_t vcm_get_res_attr(struct res *res)
+{
+	return 0;
+}
+
+
+size_t vcm_get_num_res(struct vcm *vcm)
+{
+	return 0;
+}
+
+
+struct res *vcm_get_next_res(struct vcm *vcm, struct res *res)
+{
+	return 0;
+}
+
+
+size_t vcm_res_copy(struct res *to, size_t to_off, struct res *from,
+		    size_t from_off, size_t len)
+{
+	return 0;
+}
+
+
+size_t vcm_get_min_page_size(void)
+{
+	return PAGE_SIZE;
+}
+
+
+static int vcm_to_smmu_attr(uint32_t attr)
+{
+	int smmu_attr = 0;
+
+	switch (attr & VCM_CACHE_POLICY) {
+	case VCM_NOTCACHED:
+		smmu_attr = VCM_DEV_ATTR_NONCACHED;
+		break;
+	case VCM_WB_WA:
+		smmu_attr = VCM_DEV_ATTR_CACHED_WB_WA;
+		smmu_attr |= VCM_DEV_ATTR_SH;
+		break;
+	case VCM_WB_NWA:
+		smmu_attr = VCM_DEV_ATTR_CACHED_WB_NWA;
+		smmu_attr |= VCM_DEV_ATTR_SH;
+		break;
+	case VCM_WT:
+		smmu_attr = VCM_DEV_ATTR_CACHED_WT;
+		smmu_attr |= VCM_DEV_ATTR_SH;
+		break;
+	default:
+		return -1;
+	}
+
+	return smmu_attr;
+}
+
+
+/* TBD if you vcm_back again what happens? */
+int vcm_back(struct res *res, struct physmem *physmem)
+{
+	unsigned long flags;
+	struct vcm *vcm;
+	struct phys_chunk *chunk;
+	size_t va = 0;
+	int ret;
+	int attr;
+
+	spin_lock_irqsave(&vcmlock, flags);
+
+	if (!res) {
+		vcm_err("NULL res\n");
+		goto fail;
+	}
+
+	vcm = res->vcm_id;
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	switch (vcm->type) {
+	case VCM_DEVICE:
+	case VCM_EXT_KERNEL: /* hack part 1 */
+		attr = vcm_to_smmu_attr(res->attr);
+		if (attr == -1) {
+			vcm_err("Bad SMMU attr\n");
+			goto fail;
+		}
+		break;
+	default:
+		attr = 0;
+		break;
+	}
+
+	if (!physmem) {
+		vcm_err("NULL physmem\n");
+		goto fail;
+	}
+
+	if (res->len == 0) {
+		vcm_err("res->len is 0\n");
+		goto fail;
+	}
+
+	if (physmem->len == 0) {
+		vcm_err("physmem->len is 0\n");
+		goto fail;
+	}
+
+	if (res->len != physmem->len) {
+		vcm_err("res->len (%i) != physmem->len (%i)\n",
+			res->len, physmem->len);
+		goto fail;
+	}
+
+	if (physmem->is_cont) {
+		if (physmem->res == 0) {
+			vcm_err("cont physmem->res is 0");
+			goto fail;
+		}
+	} else {
+		/* fail if no physmem */
+		if (list_empty(&physmem->alloc_head.allocated)) {
+			vcm_err("no allocated phys memory");
+			goto fail;
+		}
+	}
+
+	ret = vcm_no_assoc(res->vcm_id);
+	if (ret == 1) {
+		vcm_err("can't back un associated VCM\n");
+		goto fail;
+	}
+
+	if (ret == -1) {
+		vcm_err("vcm_no_assoc() ret -1\n");
+		goto fail;
+	}
+
+	ret = vcm_all_activated(res->vcm_id);
+	if (ret == 0) {
+		vcm_err("can't back, not all associations are activated\n");
+		goto fail_eagain;
+	}
+
+	if (ret == -1) {
+		vcm_err("vcm_all_activated() ret -1\n");
+		goto fail;
+	}
+
+	va = res->aligned_ptr;
+
+	list_for_each_entry(chunk, &physmem->alloc_head.allocated,
+			    allocated) {
+		struct vcm *vcm = res->vcm_id;
+		size_t chunk_size =  vcm_alloc_idx_to_size(chunk->size_idx);
+
+		switch (vcm->type) {
+		case VCM_DEVICE:
+		{
+#ifdef CONFIG_SMMU
+			struct avcm *avcm;
+			/* map all */
+			list_for_each_entry(avcm, &vcm->assoc_head,
+					    assoc_elm) {
+
+				ret = smmu_map(
+					(struct smmu_dev *) avcm->dev_id,
+					chunk->pa, va, chunk_size, attr);
+				if (ret != 0) {
+					vcm_err("smmu_map(%p, %p, %p, 0x%x,"
+						"0x%x)"
+						" ret %i",
+						(void *) avcm->dev_id,
+						(void *) chunk->pa,
+						(void *) va,
+						(int) chunk_size, attr, ret);
+					goto fail;
+					/* TODO handle weird inter-map case */
+				}
+			}
+			break;
+#else
+			vcm_err("No SMMU support - VCM_DEVICE not supported\n");
+			goto fail;
+#endif
+		}
+
+		case VCM_EXT_KERNEL:
+		{
+			unsigned int pages_in_chunk = chunk_size / PAGE_SIZE;
+			unsigned long loc_va = va;
+			unsigned long loc_pa = chunk->pa;
+
+			const struct mem_type *mtype;
+
+			/* TODO: get this based on MEMTYPE */
+			mtype = get_mem_type(MT_DEVICE);
+			if (!mtype) {
+				vcm_err("mtype is 0\n");
+				goto fail;
+			}
+
+			/* TODO: Map with the same chunk size */
+			while (pages_in_chunk--) {
+				ret = ioremap_page(loc_va,
+						   loc_pa,
+						   mtype);
+				if (ret != 0) {
+					vcm_err("ioremap_page(%p, %p, %p) ret"
+						" %i", (void *) loc_va,
+						(void *) loc_pa,
+						(void *) mtype, ret);
+					goto fail;
+					/* TODO handle weird
+					   inter-map case */
+				}
+
+				/* hack part 2 */
+				/* we're changing the PT entry behind
+				 * linux's back
+				 */
+				ret = cpu_set_attr(loc_va, PAGE_SIZE, attr);
+				if (ret != 0) {
+					vcm_err("cpu_set_attr(%p, %lu, %x)"
+						"ret %i\n",
+						(void *) loc_va, PAGE_SIZE,
+						attr, ret);
+					goto fail;
+					/* TODO handle weird
+					   inter-map case */
+				}
+
+				res->mapped = 1;
+
+				loc_va += PAGE_SIZE;
+				loc_pa += PAGE_SIZE;
+			}
+
+			flush_cache_vmap(va, loc_va);
+			break;
+		}
+		case VCM_ONE_TO_ONE:
+			va = chunk->pa;
+			break;
+		default:
+			/* this should never happen */
+			goto fail;
+		}
+
+		va += chunk_size;
+		/* also add res to the allocated chunk list of refs */
+	}
+
+	/* note the reservation */
+	res->physmem_id = physmem;
+
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return 0;
+fail_eagain:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -EAGAIN;
+fail:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -EINVAL;
+}
+
+
+int vcm_unback(struct res *res)
+{
+	unsigned long flags;
+	struct vcm *vcm;
+	struct physmem *physmem;
+	int ret;
+
+	spin_lock_irqsave(&vcmlock, flags);
+
+	if (!res)
+		goto fail;
+
+	vcm = res->vcm_id;
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	if (!res->physmem_id) {
+		vcm_err("can't unback a non-backed reservation\n");
+		goto fail;
+	}
+
+	physmem = res->physmem_id;
+	if (!physmem) {
+		vcm_err("physmem is NULL\n");
+		goto fail;
+	}
+
+	if (list_empty(&physmem->alloc_head.allocated)) {
+		vcm_err("physmem allocation is empty\n");
+		goto fail;
+	}
+
+	ret = vcm_no_assoc(res->vcm_id);
+	if (ret == 1) {
+		vcm_err("can't unback a unassociated reservation\n");
+		goto fail;
+	}
+
+	if (ret == -1) {
+		vcm_err("vcm_no_assoc(%p) ret -1\n", (void *) res->vcm_id);
+		goto fail;
+	}
+
+	ret = vcm_all_activated(res->vcm_id);
+	if (ret == 0) {
+		vcm_err("can't unback, not all associations are active\n");
+		goto fail_eagain;
+	}
+
+	if (ret == -1) {
+		vcm_err("vcm_all_activated(%p) ret -1\n", (void *) res->vcm_id);
+		goto fail;
+	}
+
+
+	switch (vcm->type) {
+	case VCM_EXT_KERNEL:
+		if (!res->mapped) {
+			vcm_err("can't unback an unmapped VCM_EXT_KERNEL"
+				" VCM\n");
+			goto fail;
+		}
+
+		/* vunmap free's vm_area */
+		vunmap(res->vm_area->addr);
+		res->vm_area = 0;
+
+		res->mapped = 0;
+		break;
+
+	case VCM_DEVICE:
+	{
+#ifdef CONFIG_SMMU
+		struct phys_chunk *chunk;
+		size_t va = res->aligned_ptr;
+
+		list_for_each_entry(chunk, &physmem->alloc_head.allocated,
+				    allocated) {
+			struct vcm *vcm = res->vcm_id;
+			size_t chunk_size =
+				vcm_alloc_idx_to_size(chunk->size_idx);
+			struct avcm *avcm;
+
+			/* un map all */
+			list_for_each_entry(avcm, &vcm->assoc_head, assoc_elm) {
+				ret = smmu_unmap(
+					(struct smmu_dev *) avcm->dev_id,
+					va, chunk_size);
+				if (ret != 0) {
+					vcm_err("smmu_unmap(%p, %p, 0x%x)"
+						" ret %i",
+						(void *) avcm->dev_id,
+						(void *) va,
+						(int) chunk_size, ret);
+					goto fail;
+					/* TODO handle weird inter-unmap state*/
+				}
+			}
+			va += chunk_size;
+			/* may to a light unback, depending on the requested
+			 * functionality
+			 */
+		}
+#else
+		vcm_err("No SMMU support - VCM_DEVICE memory not supported\n");
+		goto fail;
+#endif
+		break;
+	}
+
+	case VCM_ONE_TO_ONE:
+		break;
+	default:
+		/* this should never happen */
+		goto fail;
+	}
+
+	/* clear the reservation */
+	res->physmem_id = 0;
+
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return 0;
+fail_eagain:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -EAGAIN;
+fail:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -EINVAL;
+}
+
+
+enum memtarget_t vcm_get_memtype_of_res(struct res *res)
+{
+	return VCM_INVALID;
+}
+
+static int vcm_free_max_munch_cont(struct phys_chunk *head)
+{
+	struct phys_chunk *chunk, *tmp;
+
+	if (!head)
+		return -1;
+
+	list_for_each_entry_safe(chunk, tmp, &head->allocated,
+				 allocated) {
+		list_del_init(&chunk->allocated);
+	}
+
+	return 0;
+}
+
+static int vcm_alloc_max_munch_cont(size_t start_addr, size_t len,
+				    struct phys_chunk *head)
+{
+	/* this function should always succeed, since it
+	   parallels a VCM */
+
+	int i, j;
+
+	if (!head) {
+		vcm_err("head is NULL in continuous map.\n");
+		goto fail;
+	}
+
+	if (start_addr < __pa(bootmem_cont)) {
+		vcm_err("phys start addr (%p) < base (%p)\n",
+			(void *) start_addr, (void *) __pa(bootmem_cont));
+		goto fail;
+	}
+
+	if ((start_addr + len) >= (__pa(bootmem_cont) + CONT_SZ)) {
+		vcm_err("requested region (%p + %i) > "
+			" available region (%p + %i)",
+			(void *) start_addr, (int) len,
+			(void *) __pa(bootmem_cont), CONT_SZ);
+		goto fail;
+	}
+
+	i = (start_addr - __pa(bootmem_cont))/SZ_4K;
+
+	for (j = 0; j < ARRAY_SIZE(chunk_sizes); ++j) {
+		while (len/chunk_sizes[j]) {
+			if (!list_empty(&cont_phys_chunk[i].allocated)) {
+				vcm_err("chunk %i ( addr %p) already mapped\n",
+					i, (void *) (start_addr +
+						     (i*chunk_sizes[j])));
+				goto fail_free;
+			}
+			list_add_tail(&cont_phys_chunk[i].allocated,
+				      &head->allocated);
+			cont_phys_chunk[i].size_idx = j;
+
+			len -= chunk_sizes[j];
+			i += chunk_sizes[j]/SZ_4K;
+		}
+	}
+
+	if (len % SZ_4K) {
+		if (!list_empty(&cont_phys_chunk[i].allocated)) {
+			vcm_err("chunk %i (addr %p) already mapped\n",
+				i, (void *) (start_addr + (i*SZ_4K)));
+			goto fail_free;
+		}
+		len -= SZ_4K;
+		list_add_tail(&cont_phys_chunk[i].allocated,
+			      &head->allocated);
+
+		i++;
+	}
+
+	return i;
+
+fail_free:
+	{
+		struct phys_chunk *chunk, *tmp;
+		/* just remove from list, if we're double alloc'ing
+		   we don't want to stamp on the other guy */
+		list_for_each_entry_safe(chunk, tmp, &head->allocated,
+					 allocated) {
+			list_del(&chunk->allocated);
+		}
+	}
+fail:
+	return 0;
+}
+
+struct physmem *vcm_phys_alloc(enum memtype_t memtype, size_t len,
+			       uint32_t attr)
+{
+	unsigned long flags;
+	int ret;
+	struct physmem *physmem = NULL;
+	int blocks_allocated;
+
+	spin_lock_irqsave(&vcmlock, flags);
+
+	physmem = kzalloc(sizeof(*physmem), GFP_KERNEL);
+	if (!physmem) {
+		vcm_err("physmem is NULL\n");
+		goto fail;
+	}
+
+	physmem->memtype = memtype;
+	physmem->len = len;
+	physmem->attr = attr;
+
+	INIT_LIST_HEAD(&physmem->alloc_head.allocated);
+
+	if (attr & VCM_PHYS_CONT) {
+		if (!cont_vcm_id) {
+			vcm_err("cont_vcm_id is NULL\n");
+			goto fail2;
+		}
+
+		physmem->is_cont = 1;
+
+		/* TODO: get attributes */
+		physmem->res = __vcm_reserve(cont_vcm_id, len, 0);
+		if (physmem->res == 0) {
+			vcm_err("contiguous space allocation failed\n");
+			goto fail2;
+		}
+
+		/* if we're here we know we have memory, create
+		   the shadow physmem links*/
+		blocks_allocated =
+			vcm_alloc_max_munch_cont(
+				vcm_get_dev_addr(physmem->res),
+				len,
+				&physmem->alloc_head);
+
+		if (blocks_allocated == 0) {
+			vcm_err("shadow physmem allocation failed\n");
+			goto fail3;
+		}
+	} else {
+		blocks_allocated = vcm_alloc_max_munch(len,
+						       &physmem->alloc_head);
+		if (blocks_allocated == 0) {
+			vcm_err("physical allocation failed:"
+				" vcm_alloc_max_munch(%i, %p) ret 0\n",
+				len, &physmem->alloc_head);
+			goto fail2;
+		}
+	}
+
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return physmem;
+
+fail3:
+	ret = __vcm_unreserve(physmem->res);
+	if (ret != 0) {
+		vcm_err("vcm_unreserve(%p) ret %i during cleanup",
+			(void *) physmem->res, ret);
+		spin_unlock_irqrestore(&vcmlock, flags);
+		return 0;
+	}
+fail2:
+	kfree(physmem);
+fail:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return 0;
+}
+
+
+int vcm_phys_free(struct physmem *physmem)
+{
+	unsigned long flags;
+	int ret;
+
+	spin_lock_irqsave(&vcmlock, flags);
+
+	if (!physmem) {
+		vcm_err("physmem is NULL\n");
+		goto fail;
+	}
+
+	if (physmem->is_cont) {
+		if (physmem->res == 0) {
+			vcm_err("contiguous reservation is NULL\n");
+			goto fail;
+		}
+
+		ret = vcm_free_max_munch_cont(&physmem->alloc_head);
+		if (ret != 0) {
+			vcm_err("failed to free physical blocks:"
+				" vcm_free_max_munch_cont(%p) ret %i\n",
+				(void *) &physmem->alloc_head, ret);
+			goto fail;
+		}
+
+		ret = __vcm_unreserve(physmem->res);
+		if (ret != 0) {
+			vcm_err("failed to free virtual blocks:"
+				" vcm_unreserve(%p) ret %i\n",
+				(void *) physmem->res, ret);
+			goto fail;
+		}
+
+	} else {
+
+		ret = vcm_alloc_free_blocks(&physmem->alloc_head);
+		if (ret != 0) {
+			vcm_err("failed to free physical blocks:"
+				" vcm_alloc_free_blocks(%p) ret %i\n",
+				(void *) &physmem->alloc_head, ret);
+			goto fail;
+		}
+	}
+
+	memset(physmem, 0, sizeof(*physmem));
+
+	kfree(physmem);
+
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return 0;
+
+fail:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -EINVAL;
+}
+
+
+struct avcm *vcm_assoc(struct vcm *vcm, size_t dev_id, uint32_t attr)
+{
+	unsigned long flags;
+	struct avcm *avcm = NULL;
+
+	spin_lock_irqsave(&vcmlock, flags);
+
+	if (!vcm) {
+		vcm_err("vcm is NULL\n");
+		goto fail;
+	}
+
+	if (!dev_id) {
+		vcm_err("dev_id is NULL\n");
+		goto fail;
+	}
+
+	if (vcm->type == VCM_EXT_KERNEL && !list_empty(&vcm->assoc_head)) {
+		vcm_err("only one device may be assocoated with a"
+			" VCM_EXT_KERNEL\n");
+		goto fail;
+	}
+
+	avcm = kzalloc(sizeof(*avcm), GFP_KERNEL);
+	if (!avcm) {
+		vcm_err("kzalloc(%i, GFP_KERNEL) ret NULL\n", sizeof(*avcm));
+		goto fail;
+	}
+
+	avcm->dev_id = dev_id;
+
+	avcm->vcm_id = vcm;
+	avcm->attr = attr;
+	avcm->is_active = 0;
+
+	INIT_LIST_HEAD(&avcm->assoc_elm);
+	list_add(&avcm->assoc_elm, &vcm->assoc_head);
+
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return avcm;
+
+fail:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return 0;
+}
+
+
+int vcm_deassoc(struct avcm *avcm)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&vcmlock, flags);
+
+	if (!avcm) {
+		vcm_err("avcm is NULL\n");
+		goto fail;
+	}
+
+	if (list_empty(&avcm->assoc_elm)) {
+		vcm_err("nothing to deassociate\n");
+		goto fail;
+	}
+
+	if (avcm->is_active) {
+		vcm_err("association still activated\n");
+		goto fail_busy;
+	}
+
+	list_del(&avcm->assoc_elm);
+
+	memset(avcm, 0, sizeof(*avcm));
+
+	kfree(avcm);
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return 0;
+fail_busy:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -EBUSY;
+fail:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -EINVAL;
+}
+
+
+int vcm_set_assoc_attr(struct avcm *avcm, uint32_t attr)
+{
+	return 0;
+}
+
+
+uint32_t vcm_get_assoc_attr(struct avcm *avcm)
+{
+	return 0;
+}
+
+
+int vcm_activate(struct avcm *avcm)
+{
+	unsigned long flags;
+	struct vcm *vcm;
+
+	spin_lock_irqsave(&vcmlock, flags);
+
+	if (!avcm) {
+		vcm_err("avcm is NULL\n");
+		goto fail;
+	}
+
+	vcm = avcm->vcm_id;
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	if (!avcm->dev_id) {
+		vcm_err("cannot activate without a device\n");
+		goto fail_nodev;
+	}
+
+	if (avcm->is_active) {
+		vcm_err("double activate\n");
+		goto fail_busy;
+	}
+
+	if (vcm->type == VCM_DEVICE) {
+#ifdef CONFIG_SMMU
+		int ret = smmu_is_active((struct smmu_dev *) avcm->dev_id);
+		if (ret == -1) {
+			vcm_err("smmu_is_active(%p) ret -1\n",
+				(void *) avcm->dev_id);
+			goto fail_dev;
+		}
+
+		if (ret == 1) {
+			vcm_err("SMMU is already active\n");
+			goto fail_busy;
+		}
+
+		/* TODO, pmem check */
+		ret = smmu_activate((struct smmu_dev *) avcm->dev_id);
+		if (ret != 0) {
+			vcm_err("smmu_activate(%p) ret %i"
+				" SMMU failed to activate\n",
+				(void *) avcm->dev_id, ret);
+			goto fail_dev;
+		}
+#else
+		vcm_err("No SMMU support - cannot activate/deactivate\n");
+		goto fail_nodev;
+#endif
+	}
+
+	avcm->is_active = 1;
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return 0;
+
+#ifdef CONFIG_SMMU
+fail_dev:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -1;
+#endif
+fail_busy:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -EBUSY;
+fail_nodev:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -ENODEV;
+fail:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -EINVAL;
+}
+
+
+int vcm_deactivate(struct avcm *avcm)
+{
+	unsigned long flags;
+	struct vcm *vcm;
+
+	spin_lock_irqsave(&vcmlock, flags);
+
+	if (!avcm)
+		goto fail;
+
+	vcm = avcm->vcm_id;
+	if (!vcm) {
+		vcm_err("NULL vcm\n");
+		goto fail;
+	}
+
+	if (!avcm->dev_id) {
+		vcm_err("cannot deactivate without a device\n");
+		goto fail;
+	}
+
+	if (!avcm->is_active) {
+		vcm_err("double deactivate\n");
+		goto fail_nobusy;
+	}
+
+	if (vcm->type == VCM_DEVICE) {
+#ifdef CONFIG_SMMU
+		int ret = smmu_is_active((struct smmu_dev *) avcm->dev_id);
+		if (ret == -1) {
+			vcm_err("smmu_is_active(%p) ret %i\n",
+				(void *) avcm->dev_id, ret);
+			goto fail_dev;
+		}
+
+		if (ret == 0) {
+			vcm_err("double SMMU deactivation\n");
+			goto fail_nobusy;
+		}
+
+		/* TODO, pmem check */
+		ret = smmu_deactivate((struct smmu_dev *) avcm->dev_id);
+		if (ret != 0) {
+			vcm_err("smmu_deactivate(%p) ret %i\n",
+				(void *) avcm->dev_id, ret);
+			goto fail_dev;
+		}
+#else
+		vcm_err("No SMMU support - cannot activate/deactivate\n");
+		goto fail;
+#endif
+	}
+
+	avcm->is_active = 0;
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return 0;
+#ifdef CONFIG_SMMU
+fail_dev:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -1;
+#endif
+fail_nobusy:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -ENOENT;
+fail:
+	spin_unlock_irqrestore(&vcmlock, flags);
+	return -EINVAL;
+}
+
+struct bound *vcm_create_bound(struct vcm *vcm, size_t len)
+{
+	return 0;
+}
+
+
+int vcm_free_bound(struct bound *bound)
+{
+	return -1;
+}
+
+
+struct res *vcm_reserve_from_bound(struct bound *bound, size_t len,
+				   uint32_t attr)
+{
+	return 0;
+}
+
+
+size_t vcm_get_bound_start_addr(struct bound *bound)
+{
+	return 0;
+}
+
+
+size_t vcm_get_bound_len(struct bound *bound)
+{
+	return 0;
+}
+
+
+struct physmem *vcm_map_phys_addr(size_t phys, size_t len)
+{
+	return 0;
+}
+
+
+size_t vcm_get_next_phys_addr(struct physmem *physmem, size_t phys, size_t *len)
+{
+	return 0;
+}
+
+
+size_t vcm_get_dev_addr(struct res *res)
+{
+	if (!res) {
+		vcm_err("res is NULL\n");
+		return 0;
+	}
+
+	return res->aligned_ptr;
+}
+
+
+struct res *vcm_get_res(size_t dev_addr, struct vcm *vcm)
+{
+	return 0;
+}
+
+
+size_t vcm_translate(size_t src_dev, struct vcm *src_vcm, struct vcm *dst_vcm)
+{
+	return 0;
+}
+
+
+size_t vcm_get_phys_num_res(size_t phys)
+{
+	return 0;
+}
+
+
+struct res *vcm_get_next_phys_res(size_t phys, struct res *res_id, size_t *len)
+{
+	return 0;
+}
+
+
+size_t vcm_get_pgtbl_pa(struct vcm *vcm)
+{
+	return 0;
+}
+
+
+/* No lock needed, smmu_translate has its own lock */
+size_t vcm_dev_addr_to_phys_addr(size_t dev_id, size_t dev_addr)
+{
+#ifdef CONFIG_SMMU
+	int ret;
+	ret = smmu_translate((struct smmu_dev *) dev_id, dev_addr);
+	if (ret == -1)
+		vcm_err("smmu_translate(%p, %p) ret %i\n",
+			(void *) dev_id, (void *) dev_addr, ret);
+
+	return ret;
+#else
+	vcm_err("No support for SMMU - manual translation not supported\n");
+	return -1;
+#endif
+}
+
+
+/* No lock needed, bootmem_cont never changes after  */
+size_t vcm_get_cont_memtype_pa(enum memtype_t memtype)
+{
+	if (memtype != VCM_MEMTYPE_0) {
+		vcm_err("memtype != VCM_MEMTYPE_0\n");
+		goto fail;
+	}
+
+	if (!bootmem_cont) {
+		vcm_err("bootmem_cont 0\n");
+		goto fail;
+	}
+
+	return (size_t) __pa(bootmem_cont);
+fail:
+	return 0;
+}
+
+
+/* No lock needed, constant */
+size_t vcm_get_cont_memtype_len(enum memtype_t memtype)
+{
+	if (memtype != VCM_MEMTYPE_0) {
+		vcm_err("memtype != VCM_MEMTYPE_0\n");
+		return 0;
+	}
+
+	return CONT_SZ;
+}
+
+int vcm_hook(size_t dev_id, vcm_handler handler, void *data)
+{
+#ifdef CONFIG_SMMU
+	int ret;
+
+	ret = smmu_hook_irpt((struct smmu_dev *) dev_id, handler, data);
+	if (ret != 0)
+		vcm_err("smmu_hook_irpt(%p, %p, %p) ret %i\n", (void *) dev_id,
+			(void *) handler, (void *) data, ret);
+
+	return ret;
+#else
+	vcm_err("No support for SMMU - interrupts not supported\n");
+	return -1;
+#endif
+}
+
+
+size_t vcm_hw_ver(size_t dev_id)
+{
+	return 0;
+}
+
+
+static int vcm_cont_phys_chunk_init(void)
+{
+	int i;
+	int cont_pa;
+
+	if (!cont_phys_chunk) {
+		vcm_err("cont_phys_chunk 0\n");
+		goto fail;
+	}
+
+	if (!bootmem_cont) {
+		vcm_err("bootmem_cont 0\n");
+		goto fail;
+	}
+
+	cont_pa = (int) __pa(bootmem_cont);
+
+	for (i = 0; i < CONT_SZ/PAGE_SIZE; ++i) {
+		cont_phys_chunk[i].pa = (int) cont_pa; cont_pa += PAGE_SIZE;
+		cont_phys_chunk[i].size_idx = IDX_4K;
+		INIT_LIST_HEAD(&cont_phys_chunk[i].allocated);
+	}
+
+	return 0;
+
+fail:
+	return -1;
+}
+
+
+int vcm_sys_init(void)
+{
+	int ret;
+	printk(KERN_INFO "VCM Initialization\n");
+	if (!bootmem) {
+		vcm_err("bootmem is 0\n");
+		ret = -1;
+		goto fail;
+	}
+
+	if (!bootmem_cont) {
+		vcm_err("bootmem_cont is 0\n");
+		ret = -1;
+		goto fail;
+	}
+
+	ret = vcm_setup_tex_classes();
+	if (ret != 0) {
+		printk(KERN_INFO "Could not determine TEX attribute mapping\n");
+		ret = -1;
+		goto fail;
+	}
+
+
+	ret = vcm_alloc_init(__pa(bootmem));
+	if (ret != 0) {
+		vcm_err("vcm_alloc_init(%p) ret %i\n", (void *) __pa(bootmem),
+			ret);
+		ret = -1;
+		goto fail;
+	}
+
+	cont_phys_chunk = kzalloc(sizeof(*cont_phys_chunk)*(CONT_SZ/PAGE_SIZE),
+				  GFP_KERNEL);
+	if (!cont_phys_chunk) {
+		vcm_err("kzalloc(%lu, GFP_KERNEL) ret 0",
+			sizeof(*cont_phys_chunk)*(CONT_SZ/PAGE_SIZE));
+		goto fail_free;
+	}
+
+	/* the address and size will hit our special case unless we
+	   pass an override */
+	cont_vcm_id = vcm_create_flagged(0, __pa(bootmem_cont), CONT_SZ);
+	if (cont_vcm_id == 0) {
+		vcm_err("vcm_create_flagged(0, %p, %i) ret 0\n",
+			(void *) __pa(bootmem_cont), CONT_SZ);
+		ret = -1;
+		goto fail_free2;
+	}
+
+	ret = vcm_cont_phys_chunk_init();
+	if (ret != 0) {
+		vcm_err("vcm_cont_phys_chunk_init() ret %i\n", ret);
+		goto fail_free3;
+	}
+
+	printk(KERN_INFO "VCM Initialization OK\n");
+	return 0;
+
+fail_free3:
+	ret = __vcm_free(cont_vcm_id);
+	if (ret != 0) {
+		vcm_err("vcm_free(%p) ret %i during failure path\n",
+			(void *) cont_vcm_id, ret);
+		return -1;
+	}
+
+fail_free2:
+	kfree(cont_phys_chunk);
+	cont_phys_chunk = 0;
+
+fail_free:
+	ret = vcm_alloc_destroy();
+	if (ret != 0)
+		vcm_err("vcm_alloc_destroy() ret %i during failure path\n",
+			ret);
+
+	ret = -1;
+fail:
+	return ret;
+}
+
+
+int vcm_sys_destroy(void)
+{
+	int ret = 0;
+
+	if (!cont_phys_chunk) {
+		vcm_err("cont_phys_chunk is 0\n");
+		return -1;
+	}
+
+	if (!cont_vcm_id) {
+		vcm_err("cont_vcm_id is 0\n");
+		return -1;
+	}
+
+	ret = __vcm_free(cont_vcm_id);
+	if (ret != 0) {
+		vcm_err("vcm_free(%p) ret %i\n", (void *) cont_vcm_id, ret);
+		return -1;
+	}
+
+	cont_vcm_id = 0;
+
+	kfree(cont_phys_chunk);
+	cont_phys_chunk = 0;
+
+	ret = vcm_alloc_destroy();
+	if (ret != 0) {
+		vcm_err("vcm_alloc_destroy() ret %i\n", ret);
+		return -1;
+	}
+
+	return ret;
+}
+
+int vcm_init(void)
+{
+	int ret;
+
+	bootmem = __alloc_bootmem(BOOTMEM_SZ, BOOTMEM_ALIGN, 0);
+	if (!bootmem) {
+		vcm_err("segregated block pool alloc failed:"
+			" __alloc_bootmem(%i, %i, 0)\n",
+			BOOTMEM_SZ, BOOTMEM_ALIGN);
+		goto fail;
+	}
+
+	bootmem_cont = __alloc_bootmem(CONT_SZ, CONT_ALIGN, 0);
+	if (!bootmem_cont) {
+		vcm_err("contiguous pool alloc failed:"
+			" __alloc_bootmem(%i, %i, 0)\n",
+			CONT_SZ, CONT_ALIGN);
+		goto fail_free;
+	}
+
+	ret = vcm_sys_init();
+	if (ret != 0) {
+		vcm_err("vcm_sys_init() ret %i\n", ret);
+		goto fail_free2;
+	}
+
+	return 0;
+
+fail_free2:
+	free_bootmem(__pa(bootmem_cont), CONT_SZ);
+fail_free:
+	free_bootmem(__pa(bootmem), BOOTMEM_SZ);
+fail:
+	return -1;
+};
+
+/* Useful for testing, and if VCM is ever unloaded */
+void vcm_exit(void)
+{
+	int ret;
+
+	if (!bootmem_cont) {
+		vcm_err("bootmem_cont is 0\n");
+		goto fail;
+	}
+
+	if (!bootmem) {
+		vcm_err("bootmem is 0\n");
+		goto fail;
+	}
+
+	ret = vcm_sys_destroy();
+	if (ret != 0) {
+		vcm_err("vcm_sys_destroy() ret %i\n", ret);
+		goto fail;
+	}
+
+	free_bootmem(__pa(bootmem_cont), CONT_SZ);
+	free_bootmem(__pa(bootmem), BOOTMEM_SZ);
+fail:
+	return;
+}
+early_initcall(vcm_init);
+module_exit(vcm_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Zach Pfeffer <zpfeffer at codeaurora.org>");
diff --git a/include/linux/vcm.h b/include/linux/vcm.h
new file mode 100644
index 0000000..d2a1cd1
--- /dev/null
+++ b/include/linux/vcm.h
@@ -0,0 +1,701 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _VCM_H_
+#define _VCM_H_
+
+/* All undefined types must be defined using platform specific headers */
+
+#include <linux/vcm_types.h>
+
+/*
+ * Virtual contiguous memory (VCM) region primitives.
+ *
+ * Current memory mapping software uses a CPU centric management
+ * model. This makes sense in general, average hardware only contains an
+ * CPU MMU and possibly a graphics MMU. If every device in the system
+ * has one or more MMUs a CPU centric MM programming model breaks down.
+ *
+ * Looking at mapping from a system-wide perspective reveals a general
+ * graph problem. Each node that talks to memory, either through an MMU
+ * or directly (via physical memory) can be thought of as the device end
+ * of a mapping edge. The other edge is the physical memory that is
+ * mapped.
+ *
+ * In the direct mapped case, it is useful to give the device an
+ * MMU. This one-to-one MMU allows direct mapped devices to
+ * participate in graph management, they simply see memory through a
+ * one-to-one mapping.
+ *
+ * The CPU nodes can also be brought under the same mapping
+ * abstraction with the use of a light overlay on the existing
+ * VMM. This light overlay brings the VMM's page table abstraction for
+ * each process and the kernel into the graph management API.
+ *
+ * Taken together this system wide approach provides a capability that
+ * is greater than the sum of its parts by allowing users to reason
+ * about system wide mapping issues without getting bogged down in CPU
+ * centric device page table management issues.
+ */
+
+
+/*
+ * Creating, freeing and managing VCMs.
+ *
+ * A VCM region is a virtual space that can be reserved from and
+ * associated with one or more devices. At creation the user can
+ * specify an offset to start addresses and a length of the entire VCM
+ * region. Reservations out of a VCM region are always contiguous.
+ */
+
+/**
+ * vcm_create() - Create a VCM region
+ * @start_addr	The starting address of the VCM region.
+ * @len		The len of the VCM region. This must be at least
+ *		vcm_get_min_page_size() bytes.
+ *
+ * A VCM typically abstracts a page table.
+ *
+ * All functions in this API are passed and return opaque things
+ * because the underlying implementations will vary. The goal
+ * is really graph management. vcm_create() creates the "device end"
+ * of an edge in the mapping graph.
+ *
+ * The return value is non-zero if a VCM has successfully been
+ * created. It will return zero if a VCM region cannot be created or
+ * len is invalid.
+ */
+struct vcm *vcm_create(size_t start_addr, size_t len);
+
+
+/**
+ * vcm_create_from_prebuilt() - Create a VCM region from an existing region
+ * @ext_vcm_id	An external opaque value that allows the
+ *		implementation to reference an already built table.
+ *
+ * The ext_vcm_id will probably reference a page table that's been built
+ * by the VM.
+ *
+ * The platform specific implementation will provide this.
+ *
+ * The return value is non-zero if a VCM has successfully been created.
+ */
+struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id);
+
+
+/**
+ * vcm_clone() - Clone a VCM
+ * @vcm_id	A VCM to clone from.
+ *
+ * Perform a VCM "deep copy." The resulting VCM will match the original at
+ * the point of cloning. Subsequent updates to either VCM will only be
+ * seen by that VCM.
+ *
+ * The return value is non-zero if a VCM has been successfully cloned.
+ */
+struct vcm *vcm_clone(struct vcm *vcm_id);
+
+
+/**
+ * vcm_get_start_addr() - Get the starting address of the VCM region.
+ * @vcm_id	The VCM we're interested in getting the starting address of.
+ *
+ * The return value will be 1 if an error has occurred.
+ */
+size_t vcm_get_start_addr(struct vcm *vcm_id);
+
+
+/**
+ * vcm_get_len() - Get the length of the VCM region.
+ * @vcm_id	The VCM we're interested in reading the length from.
+ *
+ * The return value will be non-zero for a valid VCM. VCM regions
+ * cannot have 0 len.
+ */
+size_t vcm_get_len(struct vcm *vcm_id);
+
+
+/**
+ * vcm_free() - Free a VCM.
+ * @vcm_id	The VCM we're interested in freeing.
+ *
+ * The return value is 0 if the VCM has been freed or:
+ * -EBUSY	The VCM region contains reservations or has been associated
+ *		(active or not) and cannot be freed.
+ * -EINVAL	The vcm argument is invalid.
+ */
+int vcm_free(struct vcm *vcm_id);
+
+
+/*
+ * Creating, freeing and managing reservations out of a VCM.
+ *
+ */
+
+/**
+ * vcm_reserve() - Create a reservation from a VCM region.
+ * @vcm_id	The VCM region to reserve from.
+ * @len		The length of the reservation. Must be at least
+ * 		vcm_get_min_page_size() bytes.
+ * @attr	See 'Reservation Attributes'.
+ *
+ * A reservation, res_t, is a contiguous range from a VCM region.
+ *
+ * The return value is non-zero if a reservation has been successfully
+ * created. It is 0 if any of the parameters are invalid.
+ */
+struct res *vcm_reserve(struct vcm *vcm_id, size_t len, uint32_t attr);
+
+
+/**
+ * vcm_reserve_at() - Make a reservation at a given logical location.
+ * @memtarget	A logical location to start the reservation from.
+ * @vcm_id	The VCM region to start the reservation from.
+ * @len		The length of the reservation.
+ * @attr	See 'Reservation Attributes'.
+ *
+ * The return value is non-zero if a reservation has been successfully
+ * created.
+ */
+struct res *vcm_reserve_at(enum memtarget_t memtarget, struct vcm *vcm_id,
+		     size_t len, uint32_t attr);
+
+
+/**
+ * vcm_get_vcm_from_res() - Return the VCM region of a reservation.
+ * @res_id	The reservation to return the VCM region of.
+ *
+ * Te return value will be non-zero if the reservation is valid. A valid
+ * reservation is always associated with a VCM region; there is no such
+ * thing as an orphan reservation.
+ */
+struct vcm *vcm_get_vcm_from_res(struct res *res_id);
+
+
+/**
+ * vcm_unreserve() - Unreserve the reservation.
+ * @res_id	The reservation to unreserve.
+ *
+ * The return value will be 0 if the reservation was successfully
+ * unreserved and:
+ * -EBUSY	The reservation is still backed,
+ * -EINVAL	The vcm argument is invalid.
+ */
+int vcm_unreserve(struct res *res_id);
+
+
+/**
+ * vcm_get_res_len() - Return a reservations contiguous length.
+ * @res_id	The reservation of interest.
+ *
+ * The return value will be 0 if res is invalid; reservations cannot
+ * have 0 length so there's no error return value ambiguity.
+ */
+size_t vcm_get_res_len(struct res *res_id);
+
+
+/**
+ * vcm_set_res_attr() - Set attributes of an existing reservation.
+ * @res_id	An existing reservation of interest.
+ * @attr	See 'Reservation Attributes'.
+ *
+ * This function can only be used on an existing reservation; there
+ * are no orphan reservations. All attributes can be set on a existing
+ * reservation.
+ *
+ * The return value will be 0 for a success, otherwise it will be:
+ * -EINVAL	res or attr are invalid.
+ */
+int vcm_set_res_attr(struct res *res_id, uint32_t attr);
+
+
+/**
+ * vcm_get_res_attr() - Return a reservation's attributes.
+ * @res_id	An existing reservation of interest.
+ *
+ * The return value will be 0 if res is invalid.
+ */
+uint32_t vcm_get_res_attr(struct res *res_id);
+
+
+/**
+ * vcm_get_num_res() - Return the number of reservations in a VCM region.
+ * @vcm_id	The VCM region of interest.
+ */
+size_t vcm_get_num_res(struct vcm *vcm_id);
+
+
+/**
+ * vcm_get_next_res() - Read each reservation one at a time.
+ * @vcm_id	The VCM region of interest.
+ * @res_id	Contains the last reservation. Pass NULL on the first call.
+ *
+ * This function works like a foreach reservation in a VCM region.
+ *
+ * The return value will be non-zero for each reservation in a VCM. A
+ * zero indicates no further reservations.
+ */
+struct res *vcm_get_next_res(struct vcm *vcm_id, struct res *res_id);
+
+
+/**
+ * vcm_res_copy() - Copy len bytes from one reservation to another.
+ * @to		The reservation to copy to.
+ * @from	The reservation to copy from.
+ * @len		The length of bytes to copy.
+ *
+ * The return value is the number of bytes copied.
+ */
+size_t vcm_res_copy(struct res *to, size_t to_off, struct res *from, size_t
+		    from_off, size_t len);
+
+
+/**
+ * vcm_get_min_page_size() - Return the minimum page size supported by
+ * 			     the architecture.
+ */
+size_t vcm_get_min_page_size(void);
+
+
+/**
+ * vcm_back() - Physically back a reservation.
+ * @res_id	The reservation containing the virtual contiguous region to
+ * 		back.
+ * @physmem_id	The physical memory that will back the virtual contiguous
+ * 		memory region.
+ *
+ * One VCM can be associated with multiple devices. When you vcm_back()
+ * each association must be active. This is not strictly necessary. It may
+ * be changed in the future.
+ *
+ * This function returns 0 on a successful physical backing. Otherwise
+ * it returns:
+ * -EINVAL	res or physmem is invalid or res's len
+ *		is different from physmem's len.
+ * -EAGAIN	try again, one of the devices hasn't been activated.
+ */
+int vcm_back(struct res *res_id, struct physmem *physmem_id);
+
+
+/**
+ * vcm_unback() - Unback a reservation.
+ * @res_id	The reservation to unback.
+ *
+ * One VCM can be associated with multiple devices. When you vcm_unback()
+ * each association must be active.
+ *
+ * This function returns 0 on a successful unbacking. Otherwise
+ * it returns:
+ * -EINVAL	res is invalid.
+ * -EAGAIN	try again, one of the devices hasn't been activated.
+ */
+int vcm_unback(struct res *res_id);
+
+
+/**
+ * vcm_phys_alloc() - Allocate physical memory for the VCM region.
+ * @memtype	The memory type to allocate.
+ * @len		The length of the allocation.
+ * @attr	See 'Physical Allocation Attributes'.
+ *
+ * This function will allocate chunks of memory according to the attr
+ * it is passed.
+ *
+ * The return value is non-zero if physical memory has been
+ * successfully allocated.
+ */
+struct physmem *vcm_phys_alloc(enum memtype_t memtype, size_t len,
+			       uint32_t attr);
+
+
+/**
+ * vcm_phys_free() - Free a physical allocation.
+ * @physmem_id	The physical allocation to free.
+ *
+ * The return value is 0 if the physical allocation has been freed or:
+ * -EBUSY	Their are reservation mapping the physical memory.
+ * -EINVAL	The physmem argument is invalid.
+ */
+int vcm_phys_free(struct physmem *physmem_id);
+
+
+/**
+ * vcm_get_physmem_from_res() - Return a reservation's physmem_id
+ * @ res_id	An existing reservation of interest.
+ *
+ * The return value will be non-zero on success, otherwise it will be:
+ * -EINVAL	res is invalid
+ * -ENOMEM	res is unbacked
+ */
+struct physmem *vcm_get_physmem_from_res(struct res *res_id);
+
+
+/**
+ * vcm_get_memtype_of_physalloc() - Return the memtype of a reservation.
+ * @physmem_id	The physical allocation of interest.
+ *
+ * This function returns the memtype of a reservation or VCM_INVALID
+ * if res is invalid.
+ */
+enum memtype_t vcm_get_memtype_of_physalloc(struct physmem *physmem_id);
+
+
+/*
+ * Associate a VCM with a device, activate that association and remove it.
+ *
+ */
+
+/**
+ * vcm_assoc() - Associate a VCM with a device.
+ * @vcm_id	The VCM region of interest.
+ * @dev_id	The device to associate the VCM with.
+ * @attr	See 'Association Attributes'.
+ *
+ * This function returns non-zero if a association is made. It returns 0
+ * if any of its parameters are invalid or VCM_ATTR_VALID is not present.
+ */
+struct avcm *vcm_assoc(struct vcm *vcm_id, size_t dev_id, uint32_t attr);
+
+
+/**
+ * vcm_deassoc() - Deassociate a VCM from a device.
+ * @avcm_id	The association we want to break.
+ *
+ * The function returns 0 on success or:
+ * -EBUSY	The association is currently activated.
+ * -EINVAL	The avcm parameter is invalid.
+ */
+int vcm_deassoc(struct avcm *avcm_id);
+
+
+/**
+ * vcm_set_assoc_attr() - Set an AVCM's attributes.
+ * @avcm_id	The AVCM of interest.
+ * @attr	The new attr. See 'Association Attributes'.
+ *
+ * Every attribute can be set at runtime if an association isn't activated.
+ *
+ * This function returns 0 on success or:
+ * -EBUSY	The association is currently activated.
+ * -EINVAL	The avcm parameter is invalid.
+ */
+int vcm_set_assoc_attr(struct avcm *avcm_id, uint32_t attr);
+
+
+/**
+ * vcm_get_assoc_attr() - Return an AVCM's attributes.
+ * @avcm_id	The AVCM of interest.
+ *
+ * This function returns 0 on error.
+ */
+uint32_t vcm_get_assoc_attr(struct avcm *avcm_id);
+
+
+/**
+ * vcm_activate() - Activate an AVCM.
+ * @avcm_id	The AVCM to activate.
+ *
+ * You have to deactivate, before you activate.
+ *
+ * This function returns 0 on success or:
+ * -EINVAL   	avcm is invalid
+ * -ENODEV	no device
+ * -EBUSY	device is already active
+ * -1		hardware failure
+ */
+int vcm_activate(struct avcm *avcm_id);
+
+
+/**
+ * vcm_deactivate() - Deactivate an association.
+ * @avcm_id	The AVCM to deactivate.
+ *
+ * This function returns 0 on success or:
+ * -ENOENT     	avcm is not activate
+ * -EINVAL	avcm is invalid
+ * -1		hardware failure
+ */
+int vcm_deactivate(struct avcm *avcm_id);
+
+
+/**
+ * vcm_is_active() - Query if an AVCM is active.
+ * @avcm_id	The AVCM of interest.
+ *
+ * returns 0 for not active, 1 for active or -EINVAL for error.
+ *
+ */
+int vcm_is_active(struct avcm *avcm_id);
+
+
+
+/*
+ * Create, manage and remove a boundary in a VCM.
+ */
+
+/**
+ * vcm_create_bound() - Create a bound in a VCM.
+ * @vcm_id 	The VCM that needs a bound.
+ * @len		The len of the bound.
+ *
+ * The allocator picks the virtual addresses of the bound.
+ *
+ * This function returns non-zero if a bound was created.
+ */
+struct bound *vcm_create_bound(struct vcm *vcm_id, size_t len);
+
+
+/**
+ * vcm_free_bound() - Free a bound.
+ * @bound_id	The bound to remove.
+ *
+ * This function returns 0 if bound has been removed or:
+ * -EBUSY	The bound contains reservations and cannot be removed.
+ * -EINVAL	The bound is invalid.
+ */
+int vcm_free_bound(struct bound *bound_id);
+
+
+/**
+ * vcm_reserve_from_bound() - Make a reservation from a bounded area.
+ * @bound_id	The bound to reserve from.
+ * @len		The len of the reservation.
+ * @attr	See 'Reservation Attributes'.
+ *
+ * The return value is non-zero on success. It is 0 if any parameter
+ * is invalid.
+ */
+struct res *vcm_reserve_from_bound(struct bound *bound_id, size_t len,
+				   uint32_t attr);
+
+
+/**
+ * vcm_get_bound_start_addr() - Return the starting device address of the bound.
+ * @bound_id	The bound of interest.
+ *
+ * On success this function returns the starting addres of the bound. On error
+ * it returns:
+ * 1	bound_id is invalid.
+ */
+size_t vcm_get_bound_start_addr(struct bound *bound_id);
+
+
+/**
+ * vcm_get_bound_len() - Return the len of a bound.
+ * @bound_id	The bound of interest.
+ *
+ * This function return non-zero on success, 0 on failure.
+ */
+size_t vcm_get_bound_len(struct bound *bound_id);
+
+
+
+/*
+ * Perform low-level control over VCM regions and reservations.
+ */
+
+/**
+ * vcm_map_phys_addr() - Produce a physmem_id from a contiguous
+ *                       physical address
+ *
+ * @phys	The physical address of the contiguous range.
+ * @len		The len of the contiguous address range.
+ *
+ * Returns non-zero on success, 0 on failure.
+ */
+struct physmem *vcm_map_phys_addr(size_t phys, size_t len);
+
+
+/**
+ * vcm_get_next_phys_addr() - Get the next physical addr and len of a
+ * 			      physmem_id.
+ * @res_id	The physmem_id of interest.
+ * @phys	The current physical address. Set this to NULL to start the
+ *		iteration.
+ * @len		An output: the len of the next physical segment.
+ *
+ * physmem_id's may contain physically discontiguous sections. This
+ * function returns the next physical address and len. Pass NULL to
+ * phys to get the first physical address. The len of the physical
+ * segment is returned in *len.
+ *
+ * Returns 0 if there is no next physical address.
+ */
+size_t vcm_get_next_phys_addr(struct physmem *physmem_id, size_t phys,
+			      size_t *len);
+
+
+/**
+ * vcm_get_dev_addr() - Return the device address of a reservation.
+ * @res_id	The reservation of interest.
+ *
+ *
+ * On success this function returns the device address of a reservation. On
+ * error it returns:
+ * 1	res_id is invalid.
+ *
+ * Note: This may return a kernel address if the reservation was
+ * created from vcm_create_from_prebuilt() and the prebuilt ext_vcm_id
+ * references a VM page table.
+ */
+size_t vcm_get_dev_addr(struct res *res_id);
+
+
+/**
+ * vcm_get_res() - Return the reservation from a device address and a VCM
+ * @dev_addr	The device address of interest.
+ * @vcm_id	The VCM that contains the reservation
+ *
+ * This function returns 0 if there is no reservation whose device
+ * address is dev_addr.
+ */
+struct res *vcm_get_res(size_t dev_addr, struct vcm *vcm_id);
+
+
+/**
+ * vcm_translate() - Translate from one device address to another.
+ * @src_dev_id	The source device address.
+ * @src_vcm_id	The source VCM region.
+ * @dst_vcm_id	The destination VCM region.
+ *
+ * Derive the device address from a VCM region that maps the same physical
+ * memory as a device address from another VCM region.
+ *
+ * On success this function returns the device address of a translation. On
+ * error it returns:
+ * 1	res_id is invalid.
+ */
+size_t vcm_translate(size_t src_dev_id, struct vcm *src_vcm_id,
+		     struct vcm *dst_vcm_id);
+
+
+/**
+ * vcm_get_phys_num_res() - Return the number of reservations mapping a
+ *           		    physical address.
+ * @phys	The physical address to read.
+ */
+size_t vcm_get_phys_num_res(size_t phys);
+
+
+/**
+ * vcm_get_next_phys_res() - Return the next reservation mapped to a physical
+ *			     address.
+ * @phys	The physical address to map.
+ * @res_id	The starting reservation. Set this to NULL for the first
+ *		reservation.
+ * @len		The virtual length of the reservation
+ *
+ * This function returns 0 for the last reservation or no reservation.
+ */
+struct res *vcm_get_next_phys_res(size_t phys, struct res *res_id, size_t *len);
+
+
+/**
+ * vcm_get_pgtbl_pa() - Return the physcial address of a VCM's page table.
+ * @vcm_id	The VCM region of interest.
+ *
+ * This function returns non-zero on success.
+ */
+size_t vcm_get_pgtbl_pa(struct vcm *vcm_id);
+
+
+/**
+ * vcm_get_cont_memtype_pa() - Return the phys base addr of a memtype's
+ * 			       first contiguous region.
+ * @memtype	The memtype of interest.
+ *
+ * This function returns non-zero on success. A zero return indicates that
+ * the given memtype does not have a contiguous region or that the memtype
+ * is invalid.
+ */
+size_t vcm_get_cont_memtype_pa(enum memtype_t memtype);
+
+
+/**
+ * vcm_get_cont_memtype_len() - Return the len of a memtype's
+ * 			       	first contiguous region.
+ * @memtype	The memtype of interest.
+ *
+ * This function returns non-zero on success. A zero return indicates that
+ * the given memtype does not have a contiguous region or that the memtype
+ * is invalid.
+ */
+size_t vcm_get_cont_memtype_len(enum memtype_t memtype);
+
+
+/**
+ * vcm_dev_addr_to_phys_addr() - Perform a device address page-table lookup.
+ * @dev_id	The device that has the table.
+ * @dev_addr	The device address to map.
+ *
+ * This function returns the pa of a va from a device's page-table. It will
+ * fault if the dev_addr is not mapped.
+ */
+size_t vcm_dev_addr_to_phys_addr(size_t dev_id, size_t dev_addr);
+
+
+/*
+ * Fault Hooks
+ *
+ * vcm_hook()
+ */
+
+/**
+ * vcm_hook() - Add a fault handler.
+ * @dev_id	The device.
+ * @handler	The handler.
+ * @data	A private piece of data that will get passed to the handler.
+ *
+ * This function returns 0 for a successful registration or:
+ * -EINVAL	The arguments are invalid.
+ */
+int vcm_hook(size_t dev_id, vcm_handler handler, void *data);
+
+
+
+/*
+ * Low level, platform agnostic, HW control.
+ *
+ * vcm_hw_ver()
+ */
+
+/**
+ * vcm_hw_ver() - Return the hardware version of a device, if it has one.
+ * @dev_id	The device.
+ */
+size_t vcm_hw_ver(size_t dev_id);
+
+
+
+/* bring-up init, destroy */
+int vcm_sys_init(void);
+int vcm_sys_destroy(void);
+
+#endif /* _VCM_H_ */
+
diff --git a/include/linux/vcm_types.h b/include/linux/vcm_types.h
new file mode 100644
index 0000000..2cc4770
--- /dev/null
+++ b/include/linux/vcm_types.h
@@ -0,0 +1,318 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above
+ *       copyright notice, this list of conditions and the following
+ *       disclaimer in the documentation and/or other materials provided
+ *       with the distribution.
+ *     * Neither the name of Code Aurora Forum, Inc. nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+ * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef VCM_TYPES_H
+#define VCM_TYPES_H
+
+#include <linux/types.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/genalloc.h>
+#include <linux/vcm_alloc.h>
+#include <linux/list.h>
+
+/*
+ * Reservation Attributes
+ *
+ * Used in vcm_reserve(), vcm_reserve_at(), vcm_set_res_attr() and
+ * vcm_reserve_bound().
+ *
+ *	VCM_READ	Specifies that the reservation can be read.
+ *	VCM_WRITE	Specifies that the reservation can be written.
+ *	VCM_EXECUTE	Specifies that the reservation can be executed.
+ *	VCM_USER	Specifies that this reservation is used for
+ *			userspace access.
+ *	VCM_SUPERVISOR	Specifies that this reservation is used for
+ *				supervisor access.
+ *	VCM_SECURE	Specifies that the target of the reservation is
+ *			secure. The usage of this setting is TBD.
+ *
+ *	Caching behavior as a 4 bit field:
+ *		VCM_NOTCACHED		The VCM region is not cached.
+ *		VCM_INNER_WB_WA		The VCM region is inner cached
+ *					and is write-back and write-allocate.
+ *		VCM_INNER_WT_NWA	The VCM region is inner cached and is
+ *					write-through and no-write-allocate.
+ *		VCM_INNER_WB_NWA	The VCM region is inner cached and is
+ *					write-back and no-write-allocate.
+ *		VCM_OUTER_WB_WA		The VCM region is outer cached and is
+ *					write-back and write-allocate.
+ *		VCM_OUTER_WT_NWA	The VCM region is outer cached and is
+ *					write-through and no-write-allocate.
+ *		VCM_OUTER_WB_NWA	The VCM region is outer cached and is
+ *					write-back and no-write-allocate.
+ *		VCM_WB_WA		The VCM region is cached and is write
+ *					-back and write-allocate.
+ *		VCM_WT_NWA		The VCM region is cached and is write
+ *					-through and no-write-allocate.
+ *		VCM_WB_NWA		The VCM region is cached and is write
+ *					-back and no-write-allocate.
+ */
+
+#define VCM_CACHE_POLICY	(0xF << 0)
+
+#define VCM_READ		(1UL << 9)
+#define VCM_WRITE		(1UL << 8)
+#define VCM_EXECUTE		(1UL << 7)
+#define VCM_USER		(1UL << 6)
+#define VCM_SUPERVISOR		(1UL << 5)
+#define VCM_SECURE		(1UL << 4)
+#define VCM_NOTCACHED		(0UL << 0)
+#define VCM_WB_WA		(1UL << 0)
+#define VCM_WB_NWA		(2UL << 0)
+#define VCM_WT			(3UL << 0)
+
+
+/*
+ * Physical Allocation Attributes
+ *
+ * Used in vcm_phys_alloc().
+ *
+ *	Alignment as a power of 2 starting at 4 KB. 5 bit field.
+ *	1 = 4KB, 2 = 8KB, etc.
+ *
+ *			Specifies that the reservation should have the
+ *			alignment specified.
+ *
+ *	VCM_4KB		Specifies that the reservation should use 4KB pages.
+ *	VCM_64KB	Specifies that the reservation should use 64KB pages.
+ *	VCM_1MB		specifies that the reservation should use 1MB pages.
+ *	VCM_ALL		Specifies that the reservation should use all
+ *			available page sizes.
+ *	VCM_PHYS_CONT	Specifies that a reservation should be backed with
+ *			physically contiguous memory.
+ *	VCM_COHERENT	Specifies that the reservation must be kept coherent
+ *			because it's shared.
+ */
+
+#define VCM_ALIGNMENT_MASK      (0x1FUL << 6) /* 5-bit field */
+#define VCM_4KB			(1UL << 5)
+#define VCM_64KB		(1UL << 4)
+#define VCM_1MB			(1UL << 3)
+#define VCM_ALL			(1UL << 2)
+#define VCM_PAGE_SEL_MASK       (0xFUL << 2)
+#define VCM_PHYS_CONT		(1UL << 1)
+#define VCM_COHERENT		(1UL << 0)
+
+
+#define SHIFT_4KB               (12)
+
+#define ALIGN_REQ_BYTES(attr) (1UL << (((attr & VCM_ALIGNMENT_MASK) >> 6) + 12))
+/* set the alignment in pow 2, 0 = 4KB */
+#define SET_ALIGN_REQ_BYTES(attr, align) \
+	((attr & ~VCM_ALIGNMENT_MASK) | ((align << 6) & VCM_ALIGNMENT_MASK))
+
+/*
+ * Association Attributes
+ *
+ * Used in vcm_assoc(), vcm_set_assoc_attr().
+ *
+ * 	VCM_USE_LOW_BASE	Use the low base register.
+ *	VCM_USE_HIGH_BASE	Use the high base register.
+ *
+ *	VCM_SPLIT		A 5 bit field that defines the
+ *				high/low split.  This value defines
+ *				the number of 0's left-filled into the
+ *				split register. Addresses that match
+ *				this will use VCM_USE_LOW_BASE
+ *				otherwise they'll use
+ *				VCM_USE_HIGH_BASE. An all 0's value
+ *				directs all translations to
+ *				VCM_USE_LOW_BASE.
+ */
+
+#define VCM_SPLIT		(1UL << 3)
+#define VCM_USE_LOW_BASE	(1UL << 2)
+#define VCM_USE_HIGH_BASE	(1UL << 1)
+
+
+/*
+ * External VCMs
+ *
+ * Used in vcm_create_from_prebuilt()
+ *
+ * Externally created VCM IDs for creating kernel and user space
+ * mappings to VCMs and kernel and user space buffers out of
+ * VCM_MEMTYPE_0,1,2, etc.
+ *
+ */
+#define VCM_PREBUILT_KERNEL		1
+#define VCM_PREBUILT_USER		2
+
+/**
+ * enum memtarget_t - A logical location in a VCM.
+ *
+ * VCM_START	Indicates the start of a VCM_REGION.
+ */
+enum memtarget_t {
+	VCM_START
+};
+
+
+/**
+ * enum memtype_t - A logical location in a VCM.
+ *
+ * VCM_MEMTYPE_0	Generic memory type 0
+ * VCM_MEMTYPE_1	Generic memory type 1
+ * VCM_MEMTYPE_2	Generic memory type 2
+ *
+ * A memtype encapsulates a platform specific memory arrangement. The
+ * memtype needn't refer to a single type of memory, it can refer to a
+ * set of memories that can back a reservation.
+ *
+ */
+enum memtype_t {
+	VCM_INVALID,
+	VCM_MEMTYPE_0,
+	VCM_MEMTYPE_1,
+	VCM_MEMTYPE_2,
+};
+
+
+/**
+ * vcm_handler - The signature of the fault hook.
+ * @dev_id	The device id of the faulting device.
+ * @data	The generic data pointer.
+ * @fault_data	System specific common fault data.
+ *
+ * The handler should return 0 for success. This indicates that the
+ * fault was handled. A non-zero return value is an error and will be
+ * propagated up the stack.
+ */
+typedef int (*vcm_handler)(size_t dev_id, void *data, void *fault_data);
+
+
+enum vcm_type {
+	VCM_DEVICE,
+	VCM_EXT_KERNEL,
+	VCM_EXT_USER,
+	VCM_ONE_TO_ONE,
+};
+
+
+/**
+ * vcm - A Virtually Contiguous Memory region.
+ * @start_addr	The starting address of the VCM region.
+ * @len 	The len of the VCM region. This must be at least
+ *		vcm_min() bytes.
+ */
+struct vcm {
+	enum vcm_type type;
+
+	size_t start_addr;
+	size_t len;
+
+	size_t dev_id; /* opaque device control */
+
+	/* allocator dependent */
+	struct gen_pool *pool;
+
+	struct list_head res_head;
+
+	/* this will be a very short list */
+	struct list_head assoc_head;
+};
+
+/**
+ * avcm - A VCM to device association
+ * @vcm		The VCM region of interest.
+ * @dev_id	The device to associate the VCM with.
+ * @attr	See 'Association Attributes'.
+ */
+struct avcm {
+	struct vcm *vcm_id;
+	size_t dev_id;
+	uint32_t attr;
+
+	struct list_head assoc_elm;
+
+	int is_active; /* is this particular association active */
+};
+
+/**
+ * bound - A boundary to reserve from in a VCM region.
+ * @vcm		The VCM that needs a bound.
+ * @len		The len of the bound.
+ */
+struct bound {
+	struct vcm *vcm_id;
+	size_t len;
+};
+
+
+/**
+ * physmem - A physical memory allocation.
+ * @memtype	The memory type of the VCM region.
+ * @len		The len of the physical memory allocation.
+ * @attr 	See 'Physical Allocation Attributes'.
+ *
+ */
+
+struct physmem {
+	enum memtype_t memtype;
+	size_t len;
+	uint32_t attr;
+
+	struct phys_chunk alloc_head;
+
+	/* if the physmem is cont then use the built in VCM */
+	int is_cont;
+	struct res *res;
+};
+
+/**
+ * res - A reservation in a VCM region.
+ * @vcm		The VCM region to reserve from.
+ * @len		The length of the reservation. Must be at least vcm_min()
+ *		bytes.
+ * @attr	See 'Reservation Attributes'.
+ */
+struct res {
+	struct vcm *vcm_id;
+	struct physmem *physmem_id;
+	size_t len;
+	uint32_t attr;
+
+	/* allocator dependent */
+	size_t alignment_req;
+	size_t aligned_len;
+	unsigned long ptr;
+	size_t aligned_ptr;
+
+	struct list_head res_elm;
+
+
+	/* type VCM_EXT_KERNEL */
+	struct vm_struct *vm_area;
+	int mapped;
+};
+
+extern int chunk_sizes[NUM_CHUNK_SIZES];
+
+#endif /* VCM_TYPES_H */
-- 
1.7.0.2



From lamiaposta71 at gmail.com  Wed Jun 30 04:17:40 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Wed, 30 Jun 2010 10:17:40 +0200
Subject: [PATCH] ASoC: DaVinci: Added support for cpu clocking I2S
In-Reply-To: <20100628103030.GB14247@rakim.wolfsonmicro.main>
References: <1277707487-3371-1-git-send-email-lamiaposta71@gmail.com>
	<20100628103030.GB14247@rakim.wolfsonmicro.main>
Message-ID: <AANLkTimedG3X-rQbZvS6QfxUGkPIAtCgliI0xWknmNA9@mail.gmail.com>

2010/6/28 Mark Brown <broonie at opensource.wolfsonmicro.com>

> On Mon, Jun 28, 2010 at 08:44:46AM +0200, Raffaele Recalcati wrote:
> > From: Raffaele Recalcati <raffaele.recalcati at bticino.it>
>
> It's still very hard to understand what this patch is supposed to do.
> As previously mentioned this would probably be a lot clearer if you
> split this into multiple patches, for example one adding support for the
> fast clock mode, one adding support for selecting the pin used for any
> external clock and then further patches with any other changes.
>

Looking at other paches, they are simpler than mine.
I'll try to split it, hoping to obtain the final result.


>
> I strongly suggest looking at the commit messages for other patches in
> the kernel and trying to follow a similar style.
>
> >     Added audio playback support with [frame sync master - clock master]
> mode
> >     and with [frame sync master - clock slave].
>
> What are these modes - which clock are you talking about?
>

McBSP i2s interface to external codec.


>
> >        i2s_fast_clock switch can be used to have better approximate or
> >        symmetric waveforms.
>
> Why would someone choose not to use this?
>

I was not sure if symmetric waveform can be a must.
In general I think it is better a non symmetric, but better approximate,
waveform.
Anyway, it is better to have the possibility to choose in my opinion,
because I have not so much experience in i2s communication.


>
> >        clk_input_pin board info can be used to select it depending on hw
> >        connections
>
> >     3. We haven't changed the evmdm365 support (due also to CPLD that
> doesn't
> >                                                 help to understand)
> >         We don't know in this mode if audio stereo works on evmdm365.
> >         Probably it does.
>
> This is what makes me unsure if you're trying to add new modes or not -
> if you're adding new modes then I'd expect that existing boards would be
> unaffected with any changes to use the new feature being easily
> seperable.
>

Some tests are needed, but it requires time.
I'll try try to make some tests on evmdm365, but I'm not sure to have time
to do it.


> > +     /*
> > +      * This define works when both clock and FS are output for the cpu
> > +      * and makes clock very fast (FS is not simmetrical, but sampling
>
> symmetrical.
>

thx


>
> > +      * frequency is better approximated
> > +      */
> > +     int i2s_fast_clock;
>
> Is this a bool?
>

yes, I'll change it.


>
> > +     /* To be used when cpu gets clock from extenal pin */
> > +     int clk_input_pin;
> > +
>
> How would one use this?
>

looking at 2.5 Clock, Frames, and Data in
you can select MCBSP_CLKS or other input clock pins.

From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.59.1277886068.27306.linux-arm-kernel@lists.infradead.org>

static struct snd_platform_data dm365_bmx_snd_data[] =3D {
        {
        },
        {
                .i2s_fast_clock =3D 0,
                .clk_input_pin =3D MCBSP_CLKS,
        },
};

If not set, it works as evm works, that is the default mode.


> >       case SND_SOC_DAIFMT_CBM_CFS:
> > -             /* McBSP CLKR pin is the input for the Sample Rate
> Generator.
> > -              * McBSP FSR and FSX are driven by the Sample Rate
> Generator. */
> > -             pcr =3D DAVINCI_MCBSP_PCR_SCLKME |
> > -                     DAVINCI_MCBSP_PCR_FSXM |
> > -                     DAVINCI_MCBSP_PCR_FSRM;
> > +             pcr =3D DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
> > +             if (dev->clk_input_pin =3D=3D MCBSP_CLKS)
> > +                     pcr |=3D DAVINCI_MCBSP_PCR_CLKXM |
> > +                             DAVINCI_MCBSP_PCR_CLKRM;
> > +             else
> > +                     /*
> > +                      * McBSP CLKR pin is the input for the Sample Rat=
e
> > +                      * Generator.
> > +                      * McBSP FSR and FSX are driven by the Sample Rat=
e
> > +                      * Generator.
> > +                      */
> > +                     pcr |=3D DAVINCI_MCBSP_PCR_SCLKME;
>
> This looks like you need a switch statement for the clock selection.
>


ok.



> > +static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
> > +                             int div_id, int div)
> > +{
> > +     struct davinci_mcbsp_dev *dev =3D cpu_dai->private_data;
> > +     int srgr;
> > +
> > +     dev->clk_div =3D div;
> > +     return 0;
> > +}
> > +
>
> I would add a clock ID here in case someone wants to configure another
> clock in the patch.
>

Can you explain better,
please?


>
> > +     if (master =3D=3D SND_SOC_DAIFMT_CBS_CFS) {
>
> Use a switch staetment for this too.
>
> > +             clk =3D clk_get(NULL, "pll1_sysclk6");
>
> You're doing a clk_get() every time you go through here but never
> freeing it - it would seem better to just do the clk_get() at startup.
>

Thx for this.
I think it could create problems, right?
I can do it in the probe, I think, similarly to other drivers.


> I'd also expect this to be doing a clk_get() using the struct device for
> the DAI so that the driver can function even if the clock tree for a new.=
.
> SoC is different.
>

Sorry, I don't understand, can you explain me better?



>
> > +             if (clk)
> > +                     freq =3D clk_get_rate(clk);
>
> clk_get() returns an error pointer on error, not NULL, and...
>


gueSsing that I have to use this example code:
        aemif_clk =3D clk_get(NULL, "aemif");
        if (IS_ERR(aemif_clk))
                return;

I'll do it.


>
> > +             freq =3D 122000000; /* FIXME ask to Texas */
>
> ...this presumably ought to be in an else clause (or perhaps just not
> using this clocking at all if you can't find the clock?).
>

freq is used to obtain clk_div.
The real problem is that, as explained in the manual, it is not clear its
value.
I hope someone can help!!


>
> > +     } else if (master =3D=3D SND_SOC_DAIFMT_CBM_CFS) {
> > +             /* Clock given on CLKS */
>
> What if the user selected a different clock source?
>

I need another check,
right!


>
> > +             if (master =3D=3D SND_SOC_DAIFMT_CBS_CFS ||
> > +                             master =3D=3D SND_SOC_DAIFMT_CBS_CFM) {
>
> Again, switch statement.
>

ok


>
> > +     if (master =3D=3D SND_SOC_DAIFMT_CBS_CFS ||
> > +                     master =3D=3D SND_SOC_DAIFMT_CBS_CFM) {
>
> Here too.
>

again.


Conclusion
I split patches and I do fixes above.
Than I'll submit again and wait for new info.

The freq problem is describe here below, but it is not clear to me:


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.60.1277886068.27306.linux-arm-kernel@lists.infradead.org>

.
A) <http://www.ti.com/litv/pdf/sprufi3a>*
2.5.3 Data Clock Generation
When the receive/transmit clock mode is set to 1 (CLK(R/X)M =3D 1 in the pi=
n
control register (PCR)), the
data clocks (CLK(R/X)) are driven by the internal sample rate generator
output clock, CLKG. You can
select for the receiver and transmitter from a variety of data bit clocks
including:
=95 The input clock to the sample rate generator, which can be either the
internal clock source or a
dedicated external clock source via the MCBSP_CLKX, MCBSP_CLKR, or
MCBSP_CLKS pins. The
McBSP internal clock is the CPU/6 clock. See Section 2.5.3.1 for details on
the source of the McBSP
internal clock.
=95 The input clock source (internal clock source or external clock
MCBSP_CLKX/MCBSP_CLKR/MCBSP_CLKS) to the sample rate generator can be
divided-down by a
programmable value (CLKGDV bit in the sample rate generator register (SRGR)=
)
to drive CLKG.
Regardless of the source to the sample rate generator, the rising edge of
CLKSRG (see Figure 5)
generates CLKG and FSG.

CPU/6 is not clear.


regards,
Raffaele

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Content-Type: text/html; charset=windows-1252
Content-Transfer-Encoding: quoted-printable

<br><br><div class=3D"gmail_quote">2010/6/28 Mark Brown <span dir=3D"ltr">&=
lt;<a href=3D"mailto:broonie at opensource.wolfsonmicro.com" target=3D"_blank"=
>broonie at opensource.wolfsonmicro.com</a>&gt;</span><br><blockquote class=3D=
"gmail_quote" style=3D"margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rg=
b(204, 204, 204); padding-left: 1ex;">


<div>On Mon, Jun 28, 2010 at 08:44:46AM +0200, Raffaele Recalcati wrote:<br=
>
&gt; From: Raffaele Recalcati &lt;<a href=3D"mailto:raffaele.recalcati at btic=
ino.it" target=3D"_blank">raffaele.recalcati at bticino.it</a>&gt;<br>
<br>
</div>It&#39;s still very hard to understand what this patch is supposed to=
 do.<br>
As previously mentioned this would probably be a lot clearer if you<br>
split this into multiple patches, for example one adding support for the<br=
>
fast clock mode, one adding support for selecting the pin used for any<br>
external clock and then further patches with any other changes.<br></blockq=
uote><div><br>Looking at other paches, they are simpler than mine.<br>I&#39=
;ll try to split it, hoping to obtain the final result.<br>=A0</div>

<blockquote class=3D"gmail_quote" style=3D"margin: 0pt 0pt 0pt 0.8ex; borde=
r-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<br>
I strongly suggest looking at the commit messages for other patches in<br>
the kernel and trying to follow a similar style.<br>
<div><br>
&gt; =A0 =A0 Added audio playback support with [frame sync master - clock m=
aster] mode<br>
&gt; =A0 =A0 and with [frame sync master - clock slave].<br>
<br>
</div>What are these modes - which clock are you talking about?<br></blockq=
uote><div><br>McBSP i2s interface to external codec.<br>=A0</div><blockquot=
e class=3D"gmail_quote" style=3D"margin: 0pt 0pt 0pt 0.8ex; border-left: 1p=
x solid rgb(204, 204, 204); padding-left: 1ex;">



<div><br>
&gt; =A0 =A0 =A0 =A0i2s_fast_clock switch can be used to have better approx=
imate or<br>
&gt; =A0 =A0 =A0 =A0symmetric waveforms.<br>
<br>
</div>Why would someone choose not to use this?<br></blockquote><div><br>I =
was not sure if symmetric waveform can be a must.<br>In general I think it =
is better a non symmetric, but better approximate, waveform.<br>Anyway, it =
is better to have the possibility to choose in my opinion, because I have n=
ot so much experience in i2s communication.<br>


=A0</div><blockquote class=3D"gmail_quote" style=3D"margin: 0pt 0pt 0pt 0.8=
ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<div><br>
&gt; =A0 =A0 =A0 =A0clk_input_pin board info can be used to select it depen=
ding on hw<br>
&gt; =A0 =A0 =A0 =A0connections<br>
<br>
</div><div>&gt; =A0 =A0 3. We haven&#39;t changed the evmdm365 support (due=
 also to CPLD that doesn&#39;t<br>
&gt; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 help to understand)<br>
&gt; =A0 =A0 =A0 =A0 We don&#39;t know in this mode if audio stereo works o=
n evmdm365.<br>
&gt; =A0 =A0 =A0 =A0 Probably it does.<br>
<br>
</div>This is what makes me unsure if you&#39;re trying to add new modes or=
 not -<br>
if you&#39;re adding new modes then I&#39;d expect that existing boards wou=
ld be<br>
unaffected with any changes to use the new feature being easily<br>
seperable.<br></blockquote><div><br>Some tests are needed, but it requires =
time.<br>I&#39;ll try try to make some tests on evmdm365, but I&#39;m not s=
ure to have time to do it.<br><br></div><blockquote class=3D"gmail_quote" s=
tyle=3D"margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204=
); padding-left: 1ex;">



<div><br>
&gt; + =A0 =A0 /*<br>
&gt; + =A0 =A0 =A0* This define works when both clock and FS are output for=
 the cpu<br>
&gt; + =A0 =A0 =A0* and makes clock very fast (FS is not simmetrical, but s=
ampling<br>
<br>
</div>symmetrical.<br></blockquote><div><br>thx<br>=A0<br></div><blockquote=
 class=3D"gmail_quote" style=3D"margin: 0pt 0pt 0pt 0.8ex; border-left: 1px=
 solid rgb(204, 204, 204); padding-left: 1ex;">
<div><br>
&gt; + =A0 =A0 =A0* frequency is better approximated<br>
&gt; + =A0 =A0 =A0*/<br>
&gt; + =A0 =A0 int i2s_fast_clock;<br>
<br>
</div>Is this a bool?<br></blockquote><div><br>yes, I&#39;ll change it.<br>=
=A0</div><blockquote class=3D"gmail_quote" style=3D"margin: 0pt 0pt 0pt 0.8=
ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<div><br>
&gt; + =A0 =A0 /* To be used when cpu gets clock from extenal pin */<br>
&gt; + =A0 =A0 int clk_input_pin;<br>
&gt; +<br>
<br>
</div>How would one use this?<br></blockquote><div><br>looking at 2.5 Clock=
, Frames, and Data in <br>you can select MCBSP_CLKS or other input clock pi=
ns.<br><br>From board file you can select the possibilites:<br>static struc=
t snd_platform_data dm365_bmx_snd_data[] =3D {<br>


=A0=A0=A0=A0=A0=A0=A0 {<br>=A0=A0=A0=A0=A0=A0=A0 },<br>=A0=A0=A0=A0=A0=A0=
=A0 {<br>=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 .i2s_fast_clock =3D =
0,<br>=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 .clk_input_pin =3D MCBS=
P_CLKS,<br>=A0=A0=A0=A0=A0=A0=A0 },<br>};<br><br>If not set, it works as ev=
m works, that is the default mode.<br><br>
</div><blockquote class=3D"gmail_quote" style=3D"margin: 0pt 0pt 0pt 0.8ex;=
 border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">


<div><br>
&gt; =A0 =A0 =A0 case SND_SOC_DAIFMT_CBM_CFS:<br>
&gt; - =A0 =A0 =A0 =A0 =A0 =A0 /* McBSP CLKR pin is the input for the Sampl=
e Rate Generator.<br>
&gt; - =A0 =A0 =A0 =A0 =A0 =A0 =A0* McBSP FSR and FSX are driven by the Sam=
ple Rate Generator. */<br>
&gt; - =A0 =A0 =A0 =A0 =A0 =A0 pcr =3D DAVINCI_MCBSP_PCR_SCLKME |<br>
&gt; - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DAVINCI_MCBSP_PCR_FSXM |<br>
&gt; - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DAVINCI_MCBSP_PCR_FSRM;<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 pcr =3D DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCB=
SP_PCR_FSXM;<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 if (dev-&gt;clk_input_pin =3D=3D MCBSP_CLKS)=
<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 pcr |=3D DAVINCI_MCBSP_PCR_C=
LKXM |<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DAVINCI_MCBS=
P_PCR_CLKRM;<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 else<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /*<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0* McBSP CLKR pin is the i=
nput for the Sample Rate<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0* Generator.<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0* McBSP FSR and FSX are d=
riven by the Sample Rate<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0* Generator.<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0*/<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 pcr |=3D DAVINCI_MCBSP_PCR_S=
CLKME;<br>
<br>
</div>This looks like you need a switch statement for the clock selection.<=
br></blockquote><div><br><br>ok.<br><br><br></div><blockquote class=3D"gmai=
l_quote" style=3D"margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204=
, 204, 204); padding-left: 1ex;">



<div><br>
&gt; +static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,<br=
>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 int div_id, =
int div)<br>
&gt; +{<br>
&gt; + =A0 =A0 struct davinci_mcbsp_dev *dev =3D cpu_dai-&gt;private_data;<=
br>
&gt; + =A0 =A0 int srgr;<br>
&gt; +<br>
&gt; + =A0 =A0 dev-&gt;clk_div =3D div;<br>
&gt; + =A0 =A0 return 0;<br>
&gt; +}<br>
&gt; +<br>
<br>
</div>I would add a clock ID here in case someone wants to configure anothe=
r<br>
clock in the patch.<br></blockquote><div><br>Can you explain better,<br>ple=
ase?<br>=A0</div><blockquote class=3D"gmail_quote" style=3D"margin: 0pt 0pt=
 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<div><br>
&gt; + =A0 =A0 if (master =3D=3D SND_SOC_DAIFMT_CBS_CFS) {<br>
<br>
</div>Use a switch staetment for this too.<br>
<div><br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 clk =3D clk_get(NULL, &quot;pll1_sysclk6&quo=
t;);<br>
<br>
</div>You&#39;re doing a clk_get() every time you go through here but never=
<br>
freeing it - it would seem better to just do the clk_get() at startup.<br><=
/blockquote><div><br>Thx for this.<br>
I think it could create problems, right?<br>I can do it in the probe, I thi=
nk, similarly to other drivers.<br>=A0</div><blockquote class=3D"gmail_quot=
e" style=3D"margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204,=
 204); padding-left: 1ex;">

I&#39;d also expect this to be doing a clk_get() using the struct device fo=
r<br>
the DAI so that the driver can function even if the clock tree for a new..<=
br>
SoC is different.<br></blockquote><div><br>Sorry, I don&#39;t understand, c=
an you explain me better?<br><br>=A0</div><blockquote class=3D"gmail_quote"=
 style=3D"margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(204, 204, 2=
04); padding-left: 1ex;">

<div><br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 if (clk)<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 freq =3D clk_get_rate(clk);<=
br>
<br>
</div>clk_get() returns an error pointer on error, not NULL, and...<br></bl=
ockquote><div><br><br>gueSsing that I have to use this example code:<br>=A0=
=A0=A0=A0=A0=A0=A0 aemif_clk =3D clk_get(NULL, &quot;aemif&quot;);<br>=A0=
=A0=A0=A0=A0=A0=A0 if (IS_ERR(aemif_clk))<br>


=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0=A0 return;<br><br>I&#39;ll do it=
.<br>=A0</div><blockquote class=3D"gmail_quote" style=3D"margin: 0pt 0pt 0p=
t 0.8ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<div><br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 freq =3D 122000000; /* FIXME ask to Texas */=
<br>
<br>
</div>...this presumably ought to be in an else clause (or perhaps just not=
<br>
using this clocking at all if you can&#39;t find the clock?).<br></blockquo=
te><div><br>freq is used to obtain clk_div.<br>The real problem is that, as=
 explained in the manual, it is not clear its value.<br>I hope someone can =
help!!<br>


=A0</div><blockquote class=3D"gmail_quote" style=3D"margin: 0pt 0pt 0pt 0.8=
ex; border-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<div><br>
&gt; + =A0 =A0 } else if (master =3D=3D SND_SOC_DAIFMT_CBM_CFS) {<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 /* Clock given on CLKS */<br>
<br>
</div>What if the user selected a different clock source?<br></blockquote><=
div><br>I need another check, <br>right!<br>=A0</div><blockquote class=3D"g=
mail_quote" style=3D"margin: 0pt 0pt 0pt 0.8ex; border-left: 1px solid rgb(=
204, 204, 204); padding-left: 1ex;">



<div><br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 if (master =3D=3D SND_SOC_DAIFMT_CBS_CFS ||<=
br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 master =3D=
=3D SND_SOC_DAIFMT_CBS_CFM) {<br>
<br>
</div>Again, switch statement.<br></blockquote><div><br>ok<br>=A0<br></div>=
<blockquote class=3D"gmail_quote" style=3D"margin: 0pt 0pt 0pt 0.8ex; borde=
r-left: 1px solid rgb(204, 204, 204); padding-left: 1ex;">
<div><br>
&gt; + =A0 =A0 if (master =3D=3D SND_SOC_DAIFMT_CBS_CFS ||<br>
&gt; + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 master =3D=3D SND_SOC_DAIFMT=
_CBS_CFM) {<br>
<br>
</div>Here too.<br>
</blockquote></div><br>again.<br><br><br>Conclusion<br>I split patches and =
I do fixes above.<br>
Than I&#39;ll submit again and wait for new info.<br><br>The freq problem i=
s describe here below, but it is not clear to me:<br><br>From <b><a href=3D=
"http://www.ti.com/litv/pdf/sprufi3a" target=3D"_blank" name=3D"&amp;lid=3D=
en_US_folder_p_tech_docs_user_guides_action_link">TMS320DM36x
 DMSoC Multichannel Buffered Serial Port User&#39;s Guide (Rev. A)</a></b>
                                                           =20
                                                           =20
                                                           =20
                                                       =20
                                                       =20
                                                       =20
                                                            <br>2.5.3 Data =
Clock Generation<br>When the receive/transmit clock mode is set to 1 (CLK(R=
/X)M =3D 1 in the pin control register (PCR)), the<br>data clocks (CLK(R/X)=
) are driven by the internal sample rate generator output clock, CLKG. You =
can<br>
select for the receiver and transmitter from a variety of data bit clocks i=
ncluding:<br>=95 The input clock to the sample rate generator, which can be=
 either the internal clock source or a<br>dedicated external clock source v=
ia the MCBSP_CLKX, MCBSP_CLKR, or MCBSP_CLKS pins. The<br>
McBSP internal clock is the CPU/6 clock. See Section 2.5.3.1 for details on=
 the source of the McBSP<br>internal clock.<br>=95 The input clock source (=
internal clock source or external clock<br>MCBSP_CLKX/MCBSP_CLKR/MCBSP_CLKS=
) to the sample rate generator can be divided-down by a<br>
programmable value (CLKGDV bit in the sample rate generator register (SRGR)=
) to drive CLKG.<br>Regardless of the source to the sample rate generator, =
the rising edge of CLKSRG (see Figure 5)<br>generates CLKG and FSG.<br>
<br>CPU/6 is not clear.<br><br><br>regards,<br>Raffaele<br>
<br>



--00163692034dc5a041048a3afc4c--


From catalin.marinas at arm.com  Wed Jun 30 04:56:56 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 30 Jun 2010 09:56:56 +0100
Subject: [PATCH] ARM: RealView: Do not use outer_sync() on certain with
	L210/L220
In-Reply-To: <AANLkTinpAz52QfsnvzIY5fleJoflVr0Z40JpRNrlXY9k@mail.gmail.com>
References: <20100629093135.10365.99959.stgit@e102109-lin.cambridge.arm.com>
	<AANLkTinpAz52QfsnvzIY5fleJoflVr0Z40JpRNrlXY9k@mail.gmail.com>
Message-ID: <1277888217.13942.0.camel@e102109-lin.cambridge.arm.com>

On Wed, 2010-06-30 at 09:13 +0100, Linus Walleij wrote:
> 2010/6/29 Catalin Marinas <catalin.marinas at arm.com>:
> 
> > RealView boards with certain revisions of the L210/L220 cache controller
> > may have issues (hardware deadlock) with the recent changes to the mb()
> > barrier implementation (DSB followed by an L2 cache sync). The patch
> > disables ARM_DMA_MEM_BUFFERABLE for the RealView boards with L210/L220
> > and redefines the mandatory barriers without the outer_sync() call.
> >
> > Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> > Cc: Linus Walleij <linus.ml.walleij at gmail.com>
> 
> Works like a charm on the PB1176!
> 
> Tested-by: Linus Walleij <linus.walleij at stericsson.com>

Thanks for testing. Just to be sure - was this with the CACHE_L2X0
enabled in your configuration?

-- 
Catalin



From g.liakhovetski at gmx.de  Wed Jun 30 05:08:41 2010
From: g.liakhovetski at gmx.de (Guennadi Liakhovetski)
Date: Wed, 30 Jun 2010 11:08:41 +0200 (CEST)
Subject: [PATCHv4 1/3] mx2_camera: Add soc_camera support for i.MX25/i.MX27
In-Reply-To: <20100630072808.GD11746@pengutronix.de>
References: <cover.1277096909.git.baruch@tkos.co.il>
	<03d6e55c39690618e92a91a580ec34549a135c79.1277096909.git.baruch@tkos.co.il>
	<20100630070717.GA11746@pengutronix.de>
	<Pine.LNX.4.64.1006300918190.17489@axis700.grange>
	<20100630072808.GD11746@pengutronix.de>
Message-ID: <Pine.LNX.4.64.1006301058170.17489@axis700.grange>

Mauro, there's a question for you below.

On Wed, 30 Jun 2010, Uwe Kleine-K?nig wrote:

> Hi Guennadi,
> 
> On Wed, Jun 30, 2010 at 09:20:36AM +0200, Guennadi Liakhovetski wrote:
> > > > --- a/arch/arm/plat-mxc/include/mach/memory.h
> > > > +++ b/arch/arm/plat-mxc/include/mach/memory.h
> > > > @@ -44,12 +44,12 @@
> > > >   */
> > > >  #define CONSISTENT_DMA_SIZE SZ_8M
> > > >  
> > > > -#elif defined(CONFIG_MX1_VIDEO)
> > > > +#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_MX2_VIDEO)
> > > >  /*
> > > >   * Increase size of DMA-consistent memory region.
> > > >   * This is required for i.MX camera driver to capture at least four VGA frames.
> > > >   */
> > > >  #define CONSISTENT_DMA_SIZE SZ_4M
> > > > -#endif /* CONFIG_MX1_VIDEO */
> > > > +#endif /* CONFIG_MX1_VIDEO || CONFIG_MX2_VIDEO */
> > > Why not use CONFIG_VIDEO_MX2 here and get rid of CONFIG_MX2_VIDEO?
> > 
> > Well, firstly for uniformity with MX1 and MX3,
> Using a common scheme for names on all platforms is fine, but if the
> existing names are bad better establish a nicer scheme.
> 
> >                                                secondly not to have to use 
> > (CONFIG_VIDEO_MX2 || CONFIG_VIDEO_MX2_MODULE),
> ah, didn't notice that MX?_VIDEO is bool while VIDEO_MX? is tristate.
> That's fine.  Still I would prefer a better naming that doesn't force
> having to look up which variable is for the driver and which is for the
> arch stuff.
> 
> >                                                also note, that 
> > CONFIG_MX1_VIDEO is also used for linking of the FIQ handler for the camera.
> This is just a matter of fixing the corresponding Makefile.

So, you call a change like

 # Support for CMOS sensor interface
-obj-$(CONFIG_MX1_VIDEO)	+= ksym_mx1.o mx1_camera_fiq.o
+ifneq ($(CONFIG_VIDEO_MX1),)
+obj-y				+= ksym_mx1.o mx1_camera_fiq.o
+endif

a fix?... In any case, I'm fine with the patch as it is, so, here's

Acked-by: Guennadi Liakhovetski <g.liakhovetski at gmx.de>

I think, it would be better if you, Uwe, or Sascha pull all these 3 
patches via one of your tree, because patches 2/3 and 3/3 are ARM/MX2 
stuff anyway and this patch changes some files under arch/arm and collides 
with some mx2 changes. Mauro, do you agree? Do we need your ack too? So, 
taking them all via IMX/MXC would make synchronisation easier. However, if 
you change anything under drivers/media (including Makefile / Kconfig) or 
include/media, please let me know, so that I can ack it again.

Thanks
Guennadi
---
Guennadi Liakhovetski, Ph.D.
Freelance Open-Source Software Developer
http://www.open-technology.de/


From u.kleine-koenig at pengutronix.de  Wed Jun 30 05:38:55 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 30 Jun 2010 11:38:55 +0200
Subject: [PATCHv4 1/3] mx2_camera: Add soc_camera support for i.MX25/i.MX27
In-Reply-To: <Pine.LNX.4.64.1006301058170.17489@axis700.grange>
References: <cover.1277096909.git.baruch@tkos.co.il>
	<03d6e55c39690618e92a91a580ec34549a135c79.1277096909.git.baruch@tkos.co.il>
	<20100630070717.GA11746@pengutronix.de>
	<Pine.LNX.4.64.1006300918190.17489@axis700.grange>
	<20100630072808.GD11746@pengutronix.de>
	<Pine.LNX.4.64.1006301058170.17489@axis700.grange>
Message-ID: <20100630093855.GF11746@pengutronix.de>

Hello,

On Wed, Jun 30, 2010 at 11:08:41AM +0200, Guennadi Liakhovetski wrote:
> Mauro, there's a question for you below.
> 
> On Wed, 30 Jun 2010, Uwe Kleine-K?nig wrote:
> 
> > Hi Guennadi,
> > 
> > On Wed, Jun 30, 2010 at 09:20:36AM +0200, Guennadi Liakhovetski wrote:
> > > > > --- a/arch/arm/plat-mxc/include/mach/memory.h
> > > > > +++ b/arch/arm/plat-mxc/include/mach/memory.h
> > > > > @@ -44,12 +44,12 @@
> > > > >   */
> > > > >  #define CONSISTENT_DMA_SIZE SZ_8M
> > > > >  
> > > > > -#elif defined(CONFIG_MX1_VIDEO)
> > > > > +#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_MX2_VIDEO)
> > > > >  /*
> > > > >   * Increase size of DMA-consistent memory region.
> > > > >   * This is required for i.MX camera driver to capture at least four VGA frames.
> > > > >   */
> > > > >  #define CONSISTENT_DMA_SIZE SZ_4M
> > > > > -#endif /* CONFIG_MX1_VIDEO */
> > > > > +#endif /* CONFIG_MX1_VIDEO || CONFIG_MX2_VIDEO */
> > > > Why not use CONFIG_VIDEO_MX2 here and get rid of CONFIG_MX2_VIDEO?
> > > 
> > > Well, firstly for uniformity with MX1 and MX3,
> > Using a common scheme for names on all platforms is fine, but if the
> > existing names are bad better establish a nicer scheme.
> > 
> > >                                                secondly not to have to use 
> > > (CONFIG_VIDEO_MX2 || CONFIG_VIDEO_MX2_MODULE),
> > ah, didn't notice that MX?_VIDEO is bool while VIDEO_MX? is tristate.
> > That's fine.  Still I would prefer a better naming that doesn't force
> > having to look up which variable is for the driver and which is for the
> > arch stuff.
> > 
> > >                                                also note, that 
> > > CONFIG_MX1_VIDEO is also used for linking of the FIQ handler for the camera.
> > This is just a matter of fixing the corresponding Makefile.
> 
> So, you call a change like
> 
>  # Support for CMOS sensor interface
> -obj-$(CONFIG_MX1_VIDEO)	+= ksym_mx1.o mx1_camera_fiq.o
> +ifneq ($(CONFIG_VIDEO_MX1),)
> +obj-y				+= ksym_mx1.o mx1_camera_fiq.o
> +endif
No, I'd do something like

	config VIDEO_MX1_HOSTSUPPORT
		bool

	config VIDEO_MX1
		tristate ...
		selects VIDEO_MX1_HOSTSUPPORT
 
I'm not entirely happy with "...HOSTSUPPORT" but it's better than
MX1_VIDEO.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From ospite at studenti.unina.it  Wed Jun 30 05:53:10 2010
From: ospite at studenti.unina.it (Antonio Ospite)
Date: Wed, 30 Jun 2010 11:53:10 +0200
Subject: pxa27x_udc: Oops on probe with usb cable connected.
Message-ID: <20100630115310.bcf967c1.ospite@studenti.unina.it>

Hi,

this is a quite old issue but I'd like to bring it back on.
I get this Oops when pxa27x_udc is probed with the usb cable plugged,
this happens on a Motorola A780 phone using the openezx kernel[1] and
the gen-blob[2] second stage bootloader which disables the UDC before
booting the kernel from flash.

See the trace here:
http://people.openezx.org/ao2/tmp/pxa27x-udc_BUG/log_CRASH.txt

Here is the log of a working case (cable not plugged):
http://people.openezx.org/ao2/tmp/pxa27x-udc_BUG/log_OK.txt

Note that using the original blob bootloader from Motorola there is no
Oops but the UDC does not work at all, but maybe this is another
issue, I mean: should pxa27x_udc probe consider the case when UDC is
already active?

Here a log for this last case:
http://people.openezx.org/ao2/tmp/pxa27x-udc_BUG/log_NOCRASH_NOT_WORKING.txt

Tell me how can i help debugging this, I've put the binary and the
disassembled code in http://people.openezx.org/ao2/tmp/pxa27x-udc_BUG/
plus some notes about old discussions on the same matter.

Thanks,
   Antonio

[1] http://git.openezx.org/openezx.git
[2] http://git.openezx.org/gen-blob.git

-- 
Antonio Ospite
http://ao2.it

PGP public key ID: 0x4553B001

A: Because it messes up the order in which people normally read text.
   See http://en.wikipedia.org/wiki/Posting_style
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?
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From linux at arm.linux.org.uk  Wed Jun 30 06:12:23 2010
From: linux at arm.linux.org.uk (Russell King - ARM Linux)
Date: Wed, 30 Jun 2010 11:12:23 +0100
Subject: Pending patches for -rc
Message-ID: <20100630101223.GA24284@n2100.arm.linux.org.uk>

Given Linus' concerns about the code which is going in during the -rc
period, and the clamp-down we had for -rc3, I've re-reviewed the
changes which I have in my master branch.  The following changes do not
feel like critical rc material:

ARM: mx3: pcm037: remove unused variable
pcm037/pcm043/pca100: fix ULPI-related build warnings
eukrea_mbimx27-baseboard: add generic-bl and platform-lcd controls
eukrea_mbimx27-baseboard: add timings for DVI output
cpuimx27 and mbimx27: allow fine control of UART4 and SDHC2 usage
mach-cpuimx27: add USB Host2 and OTG support
mach-cpuimx27: register wdt and w1_master resources
mxcmmc: add card detect through DAT3 possibility
eukrea_mbimx27: use card detect through DAT3 for SDHC1
MX2X: Add Keypad device definition for MX2X arch
eukrea_mbimx27: add support for the keyboard
eukrea_mbimx27: add audio codec
mxc_nand: add support for platform defined partitions
mx25: add platform code for imx-keypad
mx25pdk: add keypad support
mx5: Add i2c to Freescale MX51 Babbage HW
mx5: Register i2c on Freescale MX51 Babbage HW
ARM: 6189/1: Add support for the MOVW/MOVT relocations in Thumb-2
ARM: 6190/1: Remove dummy loads from the original relocation address
ARM: 6191/1: Do not compile the Thumb-2 module relocations on an ARM kernel

The diffstat looks like this (worst offenders):

 arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c |  181 +++++++++++++++++++++++---
 arch/arm/mach-mx2/mach-cpuimx27.c            |   93 +++++++++++++-
 arch/arm/mach-mx5/devices.c                  |   58 ++++++++
 arch/arm/plat-mxc/clock.c                    |   37 ++++--
 arch/arm/mach-mx25/mach-mx25pdk.c            |   36 +++++
 arch/arm/kernel/module.c                     |   34 +++++
 arch/arm/mach-mx3/mach-mx31lilly.c           |   34 ++++--
 drivers/mtd/nand/mxc_nand.c                  |   33 +----
 44 files changed, 659 insertions(+), 139 deletions(-)

and I think that if I try to push these to Linus, we'll be on the receipt
of another complaint - quite rightfully too - the above does not look like
bug fixes.

Therefore, I won't be pushing my master branch to Linus, but instead merging
it into -devel and re-starting my master branch afresh.


From ext-mika.1.westerberg at nokia.com  Wed Jun 30 06:09:10 2010
From: ext-mika.1.westerberg at nokia.com (Mika Westerberg)
Date: Wed, 30 Jun 2010 13:09:10 +0300
Subject: [PATCH 2/4] crash: add support for ARM kernel image
In-Reply-To: <cover.1277891104.git.ext-mika.1.westerberg@nokia.com>
References: <cover.1277891104.git.ext-mika.1.westerberg@nokia.com>
Message-ID: <55d51316a7423a6da6ce952744933f9d8e532b7c.1277891104.git.ext-mika.1.westerberg@nokia.com>

ARM kernel image is slightly different than the currently supported images so
implement necessary support for it.

Signed-off-by: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
---
 kernel.c            |    2 +-
 lkcd_vmdump_v2_v3.h |    4 ++--
 symbols.c           |    8 +++++++-
 3 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/kernel.c b/kernel.c
index 5fc27d3..c24f7a4 100644
--- a/kernel.c
+++ b/kernel.c
@@ -736,7 +736,7 @@ verify_version(void)
 
 	if (!(sp = symbol_search("linux_banner")))
 		error(FATAL, "linux_banner symbol does not exist?\n");
-	else if ((sp->type == 'R') || (sp->type == 'r'))
+	else if ((sp->type == 'R') || (sp->type == 'r') || (sp->type == 'T'))
 		linux_banner = symbol_value("linux_banner");
 	else
 		get_symbol_data("linux_banner", sizeof(ulong), &linux_banner);
diff --git a/lkcd_vmdump_v2_v3.h b/lkcd_vmdump_v2_v3.h
index 006b0b6..afdcc53 100644
--- a/lkcd_vmdump_v2_v3.h
+++ b/lkcd_vmdump_v2_v3.h
@@ -35,7 +35,7 @@
 #include <asm/vmdump.h>                 /* for architecture-specific header */
 #endif
 
-#if defined(X86) || defined(PPC) || defined(S390) || defined(S390X)
+#if defined(ARM) || defined(X86) || defined(PPC) || defined(S390) || defined(S390X)
 
 /*
  * Kernel header file for Linux crash dumps.
@@ -92,7 +92,7 @@ typedef struct _dump_header_asm_s {
 
 #endif /* _ASM_VMDUMP_H */
 
-#endif /* X86 || PPC */
+#endif /* ARM || X86 || PPC */
 
 #if defined(ALPHA) || defined(IA64) || defined(X86_64) || defined(PPC64)
 
diff --git a/symbols.c b/symbols.c
index e92de1a..a6c0449 100644
--- a/symbols.c
+++ b/symbols.c
@@ -490,7 +490,8 @@ get_text_init_space(void)
 		return;
 
 	if (((section = get_kernel_section(".text.init")) == NULL) &&
-	    ((section = get_kernel_section(".init.text")) == NULL)) {
+	    ((section = get_kernel_section(".init.text")) == NULL) &&
+	    ((section = get_kernel_section(".init")) == NULL)) {
 		error(WARNING, "cannot determine text init space\n");
 		return;
 	}
@@ -2660,6 +2661,11 @@ is_kernel(char *file)
 				goto bailout;
 			break;
 
+		case EM_ARM:
+			if (machine_type_mismatch(file, "ARM", NULL, 0))
+				goto bailout;
+			break;
+
 		default:
 			if (machine_type_mismatch(file, "(unknown)", NULL, 0))
 				goto bailout;
-- 
1.5.6.5



From ext-mika.1.westerberg at nokia.com  Wed Jun 30 06:09:08 2010
From: ext-mika.1.westerberg at nokia.com (Mika Westerberg)
Date: Wed, 30 Jun 2010 13:09:08 +0300
Subject: [PATCH 0/4] crash utility: add ARM crashdump support
Message-ID: <cover.1277891104.git.ext-mika.1.westerberg@nokia.com>

Hello Dave,

First of all, thanks for the great tool! It is the best post-mortem analysis
tool I've ever used.

This series implements ARM support for the crash utility. Current implementation
provides following:

	o Virtual to physical address translation through page tables
	o Stack unwinding support using ARM unwind tables
	o And some more to get minimal support for ARM architecture

There are limitations, however:

	o Only one CPU is supported (I don't have access to ARM SMP hardware)
	o No support for stack unwinding with CONFIG_FRAMEPOINTER
	o Only diskdump format is supported (generated by makedumpfile)

These apply on top of crash 5.0.5 sources. Please let me know, if there is
something that needs to be changed. It would be great if you would consider
taking these in upstream crash.

With these patches, the crash utility can analyze ARM crashdumps pretty well (at
least in my testing environment). What is missing, can be implemented later on
when we have kernel[1] support and users.

After this, all necessary userspace components should be ready for ARM
architecture (kexec-tools, makedumpfile and crash utility).

I've tested this on OMAP3 based platforms with 2.6.32 and latest mainline
kernels (with the kdump patches).

Regards,
MW

[1]
Note that kernel crashdump support is not yet in mainline but I'm hoping that it
will be merged eventually (patches are in RMK's patch tracker already).

Mika Westerberg (4):
  configure: add support for ARM targets
  crash: add support for ARM kernel image
  crash: add ARM diskdump support
  crash: add ARM crashdump support

 Makefile            |   12 +-
 arm.c               | 1188 +++++++++++++++++++++++++++++++++++++++++++++++++++
 configure.c         |   14 +
 defs.h              |  131 ++++++
 diskdump.c          |   50 ++-
 kernel.c            |    2 +-
 lkcd_vmdump_v2_v3.h |    4 +-
 symbols.c           |    8 +-
 unwind_arm.c        |  702 ++++++++++++++++++++++++++++++
 9 files changed, 2102 insertions(+), 9 deletions(-)
 create mode 100644 arm.c
 create mode 100644 unwind_arm.c



From ext-mika.1.westerberg at nokia.com  Wed Jun 30 06:09:09 2010
From: ext-mika.1.westerberg at nokia.com (Mika Westerberg)
Date: Wed, 30 Jun 2010 13:09:09 +0300
Subject: [PATCH 1/4] configure: add support for ARM targets
In-Reply-To: <cover.1277891104.git.ext-mika.1.westerberg@nokia.com>
References: <cover.1277891104.git.ext-mika.1.westerberg@nokia.com>
Message-ID: <98c5cb9237f8ddab7b01eaeb1aa38d142392d3f0.1277891104.git.ext-mika.1.westerberg@nokia.com>

Signed-off-by: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
---
 configure.c |   14 ++++++++++++++
 1 files changed, 14 insertions(+), 0 deletions(-)

diff --git a/configure.c b/configure.c
index 627bb83..c8f1305 100644
--- a/configure.c
+++ b/configure.c
@@ -90,6 +90,7 @@ void make_spec_file(struct supported_gdb_version *);
 #undef S390X
 #undef PPC64
 #undef X86_64
+#undef ARM
 
 #define X86     1
 #define ALPHA   2
@@ -99,6 +100,7 @@ void make_spec_file(struct supported_gdb_version *);
 #define S390X   6
 #define PPC64   7
 #define X86_64  8
+#define ARM	9
 
 #define TARGET_X86    "TARGET=X86"
 #define TARGET_ALPHA  "TARGET=ALPHA"
@@ -108,6 +110,7 @@ void make_spec_file(struct supported_gdb_version *);
 #define TARGET_S390X  "TARGET=S390X"
 #define TARGET_PPC64  "TARGET=PPC64"
 #define TARGET_X86_64 "TARGET=X86_64"
+#define TARGET_ARM    "TARGET=ARM"
 
 #define TARGET_CFLAGS_X86    "TARGET_CFLAGS=-D_FILE_OFFSET_BITS=64"
 #define TARGET_CFLAGS_ALPHA  "TARGET_CFLAGS="
@@ -117,6 +120,7 @@ void make_spec_file(struct supported_gdb_version *);
 #define TARGET_CFLAGS_S390X  "TARGET_CFLAGS="
 #define TARGET_CFLAGS_PPC64  "TARGET_CFLAGS=-m64"
 #define TARGET_CFLAGS_X86_64 "TARGET_CFLAGS="
+#define TARGET_CFLAGS_ARM    "TARGET_CFLAGS=-D_FILE_OFFSET_BITS=64"
 
 /*
  *  The original plan was to allow the use of a particular version
@@ -274,6 +278,9 @@ get_current_configuration(void)
 #ifdef __x86_64__
         target_data.target = X86_64;
 #endif
+#ifdef __arm__
+        target_data.target = ARM;
+#endif
 
         if ((fp = fopen("Makefile", "r")) == NULL) {
 		perror("Makefile");
@@ -374,6 +381,9 @@ show_configuration(void)
 	case X86_64:
 		printf("TARGET: X86_64\n");
 		break;
+	case ARM:
+		printf("TARGET: ARM\n");
+		break;
 	}
 
 	if (strlen(target_data.program)) {
@@ -437,6 +447,10 @@ build_configure(struct supported_gdb_version *sp)
                 target = TARGET_X86_64;
                 target_CFLAGS = TARGET_CFLAGS_X86_64;
                 break;
+	case ARM:
+                target = TARGET_ARM;
+                target_CFLAGS = TARGET_CFLAGS_ARM;
+                break;
 	}
 
 	makefile_setup(&fp1, &fp2);
-- 
1.5.6.5



From ext-mika.1.westerberg at nokia.com  Wed Jun 30 06:09:11 2010
From: ext-mika.1.westerberg at nokia.com (Mika Westerberg)
Date: Wed, 30 Jun 2010 13:09:11 +0300
Subject: [PATCH 3/4] crash: add ARM diskdump support
In-Reply-To: <cover.1277891104.git.ext-mika.1.westerberg@nokia.com>
References: <cover.1277891104.git.ext-mika.1.westerberg@nokia.com>
Message-ID: <bcc0d885382447b67edc3db375744cbbf0b4c015.1277891104.git.ext-mika.1.westerberg@nokia.com>

This patch adds support for reading diskdumps (generated by makedumpfile) for
ARM architecture.

Signed-off-by: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
---
 diskdump.c |   50 +++++++++++++++++++++++++++++++++++++++++++++++---
 1 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/diskdump.c b/diskdump.c
index 79e72ad..2a22057 100644
--- a/diskdump.c
+++ b/diskdump.c
@@ -249,6 +249,9 @@ restart:
 	else if (STRNEQ(header->utsname.machine, "ppc64") &&
 	    machine_type_mismatch(file, "PPC64", NULL, 0))
 		goto err;
+	else if (STRNEQ(header->utsname.machine, "arm") &&
+	    machine_type_mismatch(file, "ARM", NULL, 0))
+		goto err;
 
 	if (header->block_size != block_size) {
 		block_size = header->block_size;
@@ -335,7 +338,9 @@ restart:
 
 	dd->header = header;
 
-	if (machine_type("X86"))
+	if (machine_type("ARM"))
+		dd->machine_type = EM_ARM;
+	else if (machine_type("X86"))
 		dd->machine_type = EM_386;
 	else if (machine_type("X86_64"))
 		dd->machine_type = EM_X86_64;
@@ -516,6 +521,33 @@ page_is_cached(physaddr_t paddr)
 }
 
 /*
+ * Translate physical address in paddr to PFN number. This means normally that
+ * we just shift paddr by some constant. Some architectures need special
+ * handling for this, however.
+ */
+static ulong
+paddr_to_pfn(physaddr_t paddr)
+{
+	ulong pfn;
+
+	switch (dd->machine_type) {
+	case EM_ARM:
+		/*
+		 * In ARM, PFN 0 means first page in kernel direct-mapped view.
+		 * This is also first page in mem_map as well.
+		 */
+		pfn = (paddr - machdep->machspec->phys_base) >> dd->block_shift;
+		break;
+
+	default:
+		pfn = paddr >> dd->block_shift;
+		break;
+	}
+
+	return pfn;
+}
+
+/*
  *  Cache the page's data.
  *
  *  If an empty page cache location is available, take it.  Otherwise, evict
@@ -560,7 +592,7 @@ cache_page(physaddr_t paddr)
 	dd->page_cache_hdr[i].pg_hit_count++;
 
 	/* find page descriptor */
-	pfn = paddr >> dd->block_shift;
+	pfn = paddr_to_pfn(paddr);
 	desc_pos = pfn_to_pos(pfn);
 	seek_offset = dd->data_offset
 			+ (off_t)(desc_pos - 1)*sizeof(page_desc_t);
@@ -613,7 +645,7 @@ read_diskdump(int fd, void *bufptr, int cnt, ulong addr, physaddr_t paddr)
 	physaddr_t curpaddr;
 	ulong pfn, page_offset;
 
-	pfn = paddr >> dd->block_shift;
+	pfn = paddr_to_pfn(paddr);
 
 	if (KDUMP_SPLIT()) {
 		/* Find proper dd */
@@ -687,6 +719,12 @@ get_diskdump_regs_ppc64(struct bt_info *bt, ulong *eip, ulong *esp)
 	machdep->get_stack_frame(bt, eip, esp);
 }
 
+static void
+get_diskdump_regs_arm(struct bt_info *bt, ulong *eip, ulong *esp)
+{
+	machdep->get_stack_frame(bt, eip, esp);
+}
+
 /*
  *  Send the request to the proper architecture hander.
  */
@@ -696,6 +734,10 @@ get_diskdump_regs(struct bt_info *bt, ulong *eip, ulong *esp)
 {
 	switch (dd->machine_type) 
 	{
+	case EM_ARM:
+		get_diskdump_regs_arm(bt, eip, esp);
+		break;
+
 	case EM_386:
 		return get_netdump_regs_x86(bt, eip, esp);
 		break;
@@ -784,6 +826,8 @@ __diskdump_memory_dump(FILE *fp)
         fprintf(fp, "      machine_type: %d ", dd->machine_type);
 	switch (dd->machine_type)
 	{
+	case EM_ARM:
+		fprintf(fp, "(EM_ARM)\n"); break;
 	case EM_386:
 		fprintf(fp, "(EM_386)\n"); break;
 	case EM_X86_64:
-- 
1.5.6.5



From ext-mika.1.westerberg at nokia.com  Wed Jun 30 06:09:12 2010
From: ext-mika.1.westerberg at nokia.com (Mika Westerberg)
Date: Wed, 30 Jun 2010 13:09:12 +0300
Subject: [PATCH 4/4] crash: add ARM crashdump support
In-Reply-To: <cover.1277891104.git.ext-mika.1.westerberg@nokia.com>
References: <cover.1277891104.git.ext-mika.1.westerberg@nokia.com>
Message-ID: <fb49a2f47cad6fa573119ab5b173b257dbaf6dd9.1277891104.git.ext-mika.1.westerberg@nokia.com>

This patch adds minimal support for reading ARM crashdumps (currently only
diskdump format is supported). It contains necessary virtual to physical
translations and stack unwinding support.

Signed-off-by: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
---
 Makefile     |   12 +-
 arm.c        | 1188 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 defs.h       |  131 +++++++
 unwind_arm.c |  702 ++++++++++++++++++++++++++++++++++
 4 files changed, 2031 insertions(+), 2 deletions(-)
 create mode 100644 arm.c
 create mode 100644 unwind_arm.c

diff --git a/Makefile b/Makefile
index 3ea6539..61d88c0 100644
--- a/Makefile
+++ b/Makefile
@@ -74,11 +74,12 @@ UNWIND_HFILES=unwind.h unwind_i.h rse.h unwind_x86.h unwind_x86_64.h
 CFILES=main.c tools.c global_data.c memory.c filesys.c help.c task.c \
 	kernel.c test.c gdb_interface.c configure.c net.c dev.c \
 	alpha.c x86.c ppc.c ia64.c s390.c s390x.c s390dbf.c ppc64.c x86_64.c \
+	arm.c \
 	extensions.c remote.c va_server.c va_server_v1.c symbols.c cmdline.c \
 	lkcd_common.c lkcd_v1.c lkcd_v2_v3.c lkcd_v5.c lkcd_v7.c lkcd_v8.c\
 	lkcd_fix_mem.c s390_dump.c lkcd_x86_trace.c \
 	netdump.c diskdump.c xendump.c unwind.c unwind_decoder.c \
-	unwind_x86_32_64.c \
+	unwind_x86_32_64.c unwind_arm.c \
  	xen_hyper.c xen_hyper_command.c xen_hyper_global_data.c \
 	xen_hyper_dump_tables.c kvmdump.c qemu.c qemu-load.c
 
@@ -90,11 +91,12 @@ SOURCE_FILES=${CFILES} ${GENERIC_HFILES} ${MCORE_HFILES} \
 OBJECT_FILES=main.o tools.o global_data.o memory.o filesys.o help.o task.o \
 	build_data.o kernel.o test.o gdb_interface.o net.o dev.o \
 	alpha.o x86.o ppc.o ia64.o s390.o s390x.o s390dbf.o ppc64.o x86_64.o \
+	arm.o \
 	extensions.o remote.o va_server.o va_server_v1.o symbols.o cmdline.o \
 	lkcd_common.o lkcd_v1.o lkcd_v2_v3.o lkcd_v5.o lkcd_v7.o lkcd_v8.o \
 	lkcd_fix_mem.o s390_dump.o netdump.o diskdump.o xendump.o \
 	lkcd_x86_trace.o unwind_v1.o unwind_v2.o unwind_v3.o \
-	unwind_x86_32_64.o \
+	unwind_x86_32_64.o unwind_arm.o \
  	xen_hyper.o xen_hyper_command.o xen_hyper_global_data.o \
 	xen_hyper_dump_tables.o kvmdump.o qemu.o qemu-load.o
 
@@ -407,6 +409,9 @@ ppc64.o: ${GENERIC_HFILES} ppc64.c
 x86_64.o: ${GENERIC_HFILES} ${REDHAT_HFILES} x86_64.c
 	cc -c ${CRASH_CFLAGS} x86_64.c ${WARNING_OPTIONS} ${WARNING_ERROR}
 
+arm.o: ${GENERIC_HFILES} ${REDHAT_HFILES} arm.c
+	cc -c ${CRASH_CFLAGS} arm.c ${WARNING_OPTIONS} ${WARNING_ERROR}
+
 s390.o: ${GENERIC_HFILES} ${IBM_HFILES} s390.c
 	cc -c ${CRASH_CFLAGS} s390.c ${WARNING_OPTIONS} ${WARNING_ERROR}
 
@@ -448,6 +453,9 @@ lkcd_x86_trace.o: ${GENERIC_HFILES} ${LKCD_TRACE_HFILES} lkcd_x86_trace.c
 unwind_x86_32_64.o: ${GENERIC_HFILES} ${UNWIND_HFILES} unwind_x86_32_64.c
 	cc -c ${CRASH_CFLAGS} unwind_x86_32_64.c -o unwind_x86_32_64.o ${WARNING_OPTIONS} ${WARNING_ERROR}
 
+unwind_arm.o: ${GENERIC_HFILES} ${UNWIND_HFILES} unwind_arm.c
+	cc -c ${CRASH_CFLAGS} unwind_arm.c -o unwind_arm.o ${WARNING_OPTIONS} ${WARNING_ERROR}
+
 unwind_v1.o: ${GENERIC_HFILES} ${UNWIND_HFILES} unwind.c unwind_decoder.c
 	cc -c ${CRASH_CFLAGS} unwind.c -DREDHAT -DUNWIND_V1 -o unwind_v1.o ${WARNING_OPTIONS} ${WARNING_ERROR}
 
diff --git a/arm.c b/arm.c
new file mode 100644
index 0000000..40c860a
--- /dev/null
+++ b/arm.c
@@ -0,0 +1,1188 @@
+/*
+ * arm.c - core analysis suite
+ *
+ * Created by: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifdef ARM
+#include <elf.h>
+
+#include "defs.h"
+
+static int arm_get_crash_notes(void);
+static int arm_verify_symbol(const char *, ulong, char);
+static int arm_is_module_addr(ulong);
+static int arm_is_kvaddr(ulong);
+static int arm_in_exception_text(ulong);
+static void arm_back_trace_cmd(struct bt_info *);
+static ulong arm_processor_speed(void);
+static int arm_translate_pte(ulong, void *, ulonglong);
+static int arm_vtop(ulong, ulong *, physaddr_t *, int);
+static int arm_kvtop(struct task_context *, ulong, physaddr_t *, int);
+static int arm_uvtop(struct task_context *, ulong, physaddr_t *, int);
+static int arm_get_frame(struct bt_info *, ulong *, ulong *);
+static int arm_get_dumpfile_stack_frame(struct bt_info *, ulong *, ulong *);
+static void arm_get_stack_frame(struct bt_info *, ulong *, ulong *);
+static void arm_dump_exception_stack(ulong, ulong);
+static ulong arm_vmalloc_start(void);
+static int arm_is_task_addr(ulong);
+static int arm_dis_filter(ulong, char *);
+static int arm_eframe_search(struct bt_info *);
+static ulong arm_get_task_pgd(ulong);
+static void arm_cmd_mach(void);
+static void arm_display_machine_stats(void);
+static int arm_get_smp_cpus(void);
+static void arm_init_machspec(void);
+
+static struct line_number_hook arm_line_number_hooks[];
+static struct machine_specific arm_machine_specific;
+
+/**
+ * struct arm_cpu_context_save - idle task registers
+ *
+ * This structure holds idle task registers. Only FP, SP, and PC are needed for
+ * unwinding the stack.
+ */
+struct arm_cpu_context_save {
+	ulong	fp;
+	ulong	sp;
+	ulong	pc;
+};
+
+/*
+ * Holds registers during the crash.
+ */
+static struct arm_pt_regs panic_task_regs;
+
+#define PGDIR_SIZE() (4 * PAGESIZE())
+#define PGDIR_OFFSET(X) (((ulong)(X)) & (PGDIR_SIZE() - 1))
+
+#define _SECTION_PAGE_MASK	(~((MEGABYTES(1))-1))
+
+#define PMD_TYPE_MASK   3
+#define PMD_TYPE_SECT   2
+#define PMD_TYPE_TABLE  1
+
+static inline ulong *
+pmd_page_addr(ulong pmd)
+{
+	ulong ptr;
+
+	ptr = pmd & ~(PTRS_PER_PTE * sizeof(void *) - 1);
+	ptr += PTRS_PER_PTE * sizeof(void *);
+
+	return (ulong *)ptr;
+}
+
+/*
+ * "Linux" PTE definitions.
+ */
+#define L_PTE_PRESENT		(1 << 0)
+#define L_PTE_YOUNG		(1 << 1)
+#define L_PTE_FILE		(1 << 2)
+#define L_PTE_DIRTY		(1 << 6)
+#define L_PTE_WRITE		(1 << 7)
+#define L_PTE_USER		(1 << 8)
+#define L_PTE_EXEC		(1 << 9)
+#define L_PTE_SHARED		(1 << 10)
+
+#define pte_val(pte)		(pte)
+
+#define pte_present(pte)	(pte_val(pte) & L_PTE_PRESENT)
+#define pte_write(pte)		(pte_val(pte) & L_PTE_WRITE)
+#define pte_dirty(pte)		(pte_val(pte) & L_PTE_DIRTY)
+#define pte_young(pte)		(pte_val(pte) & L_PTE_YOUNG)
+
+/*
+ * Following stuff is taken directly from the kernel sources. These are used in
+ * dump_exception_stack() to format an exception stack entry.
+ */
+#define USR26_MODE	0x00000000
+#define FIQ26_MODE	0x00000001
+#define IRQ26_MODE	0x00000002
+#define SVC26_MODE	0x00000003
+#define USR_MODE	0x00000010
+#define FIQ_MODE	0x00000011
+#define IRQ_MODE	0x00000012
+#define SVC_MODE	0x00000013
+#define ABT_MODE	0x00000017
+#define UND_MODE	0x0000001b
+#define SYSTEM_MODE	0x0000001f
+#define MODE32_BIT	0x00000010
+#define MODE_MASK	0x0000001f
+#define PSR_T_BIT	0x00000020
+#define PSR_F_BIT	0x00000040
+#define PSR_I_BIT	0x00000080
+#define PSR_A_BIT	0x00000100
+#define PSR_E_BIT	0x00000200
+#define PSR_J_BIT	0x01000000
+#define PSR_Q_BIT	0x08000000
+#define PSR_V_BIT	0x10000000
+#define PSR_C_BIT	0x20000000
+#define PSR_Z_BIT	0x40000000
+#define PSR_N_BIT	0x80000000
+
+#define isa_mode(regs) \
+	((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
+	 (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
+
+#define processor_mode(regs) \
+	((regs)->ARM_cpsr & MODE_MASK)
+
+#define interrupts_enabled(regs) \
+	(!((regs)->ARM_cpsr & PSR_I_BIT))
+
+#define fast_interrupts_enabled(regs) \
+	(!((regs)->ARM_cpsr & PSR_F_BIT))
+
+static const char *processor_modes[] = {
+	"USER_26", "FIQ_26", "IRQ_26", "SVC_26", "UK4_26", "UK5_26",
+	"UK6_26", "UK7_26" , "UK8_26", "UK9_26", "UK10_26", "UK11_26",
+	"UK12_26", "UK13_26", "UK14_26", "UK15_26", "USER_32", "FIQ_32",
+	"IRQ_32", "SVC_32", "UK4_32", "UK5_32", "UK6_32", "ABT_32",
+	"UK8_32", "UK9_32", "UK10_32", "UND_32", "UK12_32", "UK13_32",
+	"UK14_32", "SYS_32",
+};
+
+static const char *isa_modes[] = {
+	"ARM" , "Thumb" , "Jazelle", "ThumbEE",
+};
+
+#define NOT_IMPLEMENTED() \
+	error(FATAL, "%s: N/A\n", __func__)
+
+/*
+ * Do all necessary machine-specific setup here. This is called several times
+ * during initialization.
+ */
+void
+arm_init(int when)
+{
+	switch (when) {
+	case PRE_SYMTAB:
+		machdep->verify_symbol = arm_verify_symbol;
+		machdep->machspec = &arm_machine_specific;
+		if (pc->flags & KERNEL_DEBUG_QUERY)
+			return;
+		machdep->pagesize = memory_page_size();
+		machdep->pageshift = ffs(machdep->pagesize) - 1;
+		machdep->pageoffset = machdep->pagesize - 1;
+		machdep->pagemask = ~((ulonglong)machdep->pageoffset);
+		machdep->stacksize = machdep->pagesize * 2;
+		machdep->last_pgd_read = 0;
+		machdep->last_pmd_read = 0;
+		machdep->last_ptbl_read = 0;
+		machdep->verify_paddr = generic_verify_paddr;
+		machdep->ptrs_per_pgd = PTRS_PER_PGD;
+		break;
+
+	case PRE_GDB:
+		if ((machdep->pgd = (char *)malloc(PGDIR_SIZE())) == NULL)
+			error(FATAL, "cannot malloc pgd space.");
+		if ((machdep->ptbl = (char *)malloc(PAGESIZE())) == NULL)
+			error(FATAL, "cannot malloc ptbl space.");
+
+		/*
+		 * Kernel text starts 16k after PAGE_OFFSET.
+		 */
+	        machdep->kvbase = symbol_value("_stext") & 0xffff0000UL;
+		machdep->identity_map_base = machdep->kvbase;
+		machdep->is_kvaddr = arm_is_kvaddr;
+		machdep->is_uvaddr = generic_is_uvaddr;
+		machdep->eframe_search = arm_eframe_search;
+		machdep->back_trace = arm_back_trace_cmd;
+		machdep->processor_speed = arm_processor_speed;
+		machdep->uvtop = arm_uvtop;
+		machdep->kvtop = arm_kvtop;
+		machdep->get_task_pgd = arm_get_task_pgd;
+		machdep->get_stack_frame = arm_get_stack_frame;
+		machdep->get_stackbase = generic_get_stackbase;
+		machdep->get_stacktop = generic_get_stacktop;
+		machdep->translate_pte = arm_translate_pte;
+		machdep->memory_size = generic_memory_size;
+		machdep->vmalloc_start = arm_vmalloc_start;
+		machdep->is_task_addr = arm_is_task_addr;
+		machdep->dis_filter = arm_dis_filter;
+		machdep->cmd_mach = arm_cmd_mach;
+		machdep->get_smp_cpus = arm_get_smp_cpus;
+		machdep->line_number_hooks = arm_line_number_hooks;
+		machdep->value_to_symbol = generic_machdep_value_to_symbol;
+		machdep->init_kernel_pgd = NULL;
+
+		if (symbol_exists("irq_desc"))
+			machdep->dump_irq = generic_dump_irq;
+
+		arm_init_machspec();
+		break;
+
+	case POST_GDB:
+		if (symbol_exists("irq_desc"))
+			ARRAY_LENGTH_INIT(machdep->nr_irqs, irq_desc,
+					  "irq_desc", NULL, 0);
+		/*
+		 * Registers for idle threads are saved in
+		 * thread_info.cpu_context.
+		 */
+		STRUCT_SIZE_INIT(cpu_context_save, "cpu_context_save");
+		MEMBER_OFFSET_INIT(cpu_context_save_fp,
+			"cpu_context_save", "fp");
+		MEMBER_OFFSET_INIT(cpu_context_save_sp,
+			"cpu_context_save", "sp");
+		MEMBER_OFFSET_INIT(cpu_context_save_pc,
+			"cpu_context_save", "pc");
+		MEMBER_OFFSET_INIT(thread_info_cpu_context,
+			"thread_info", "cpu_context");
+
+		/*
+		 * We need to have information about note_buf_t which is used to
+		 * hold ELF note containing registers and status of the thread
+		 * that panic'd.
+		 */
+		STRUCT_SIZE_INIT(note_buf, "note_buf_t");
+
+		STRUCT_SIZE_INIT(elf_prstatus, "elf_prstatus");
+		MEMBER_OFFSET_INIT(elf_prstatus_pr_pid, "elf_prstatus",
+				   "pr_pid");
+		MEMBER_OFFSET_INIT(elf_prstatus_pr_reg, "elf_prstatus",
+				   "pr_reg");
+
+		/*
+		 * crash_notes contains machine specific information about the
+		 * crash. In particular, it contains CPU registers at the time
+		 * of the crash. We need this information to extract correct
+		 * backtraces from the panic task.
+		 */
+		if (!arm_get_crash_notes())
+			error(WARNING, "Couldn't retrieve crash_notes\n");
+		break;
+
+	case POST_VM:
+		machdep->machspec->vmalloc_start_addr = vt->high_memory;
+		/*
+		 * Modules are placed in first vmalloc'd area. This is 16MB
+		 * below PAGE_OFFSET.
+		 */
+		machdep->machspec->modules_vaddr = first_vmalloc_address();
+		machdep->machspec->modules_end = machdep->kvbase - 1;
+
+		if (!init_unwind_tables()) {
+			error(WARNING, "Couldn't initialize unwind tables.\n"
+			      "This means that stack unwinding is not\n"
+			      "available for this core file.\n");
+		}
+		break;
+	}
+}
+
+void
+arm_dump_machdep_table(ulong arg)
+{
+	const struct machine_specific *ms;
+	int others, i;
+
+        others = 0;
+        fprintf(fp, "              flags: %lx (", machdep->flags);
+	if (machdep->flags & KSYMS_START)
+		fprintf(fp, "%sKSYMS_START", others++ ? "|" : "");
+        fprintf(fp, ")\n");
+
+	fprintf(fp, "             kvbase: %lx\n", machdep->kvbase);
+	fprintf(fp, "  identity_map_base: %lx\n", machdep->kvbase);
+	fprintf(fp, "           pagesize: %d\n", machdep->pagesize);
+	fprintf(fp, "          pageshift: %d\n", machdep->pageshift);
+	fprintf(fp, "           pagemask: %lx\n", (ulong)machdep->pagemask);
+	fprintf(fp, "         pageoffset: %lx\n", machdep->pageoffset);
+	fprintf(fp, "          stacksize: %ld\n", machdep->stacksize);
+	fprintf(fp, "                 hz: %d\n", machdep->hz);
+	fprintf(fp, "                mhz: %ld\n", machdep->mhz);
+	fprintf(fp, "            memsize: %lld (0x%llx)\n",
+		machdep->memsize, machdep->memsize);
+	fprintf(fp, "               bits: %d\n", machdep->bits);
+	fprintf(fp, "            nr_irqs: %d\n", machdep->nr_irqs);
+	fprintf(fp, "      eframe_search: arm_eframe_search()\n");
+	fprintf(fp, "         back_trace: arm_back_trace_cmd()\n");
+	fprintf(fp, "    processor_speed: arm_processor_speed()\n");
+	fprintf(fp, "              uvtop: arm_uvtop()\n");
+	fprintf(fp, "              kvtop: arm_kvtop()\n");
+	fprintf(fp, "       get_task_pgd: arm_get_task_pgd()\n");
+	fprintf(fp, "           dump_irq: generic_dump_irq()\n");
+	fprintf(fp, "    get_stack_frame: arm_get_stack_frame()\n");
+	fprintf(fp, "      get_stackbase: generic_get_stackbase()\n");
+	fprintf(fp, "       get_stacktop: generic_get_stacktop()\n");
+	fprintf(fp, "      translate_pte: arm_translate_pte()\n");
+	fprintf(fp, "        memory_size: generic_memory_size()\n");
+	fprintf(fp, "      vmalloc_start: arm_vmalloc_start()\n");
+	fprintf(fp, "       is_task_addr: arm_is_task_addr()\n");
+	fprintf(fp, "      verify_symbol: arm_verify_symbol()\n");
+	fprintf(fp, "         dis_filter: arm_dis_filter()\n");
+	fprintf(fp, "           cmd_mach: arm_cmd_mach()\n");
+	fprintf(fp, "       get_smp_cpus: arm_get_smp_cpus()\n");
+	fprintf(fp, "          is_kvaddr: generic_is_kvaddr()\n");
+	fprintf(fp, "          is_uvaddr: generic_is_uvaddr()\n");
+	fprintf(fp, "       verify_paddr: generic_verify_paddr()\n");
+	fprintf(fp, " xendump_p2m_create: NULL\n");
+	fprintf(fp, "xen_kdump_p2m_create: NULL\n");
+	fprintf(fp, "  line_number_hooks: arm_line_number_hooks\n");
+	fprintf(fp, "      last_pgd_read: %lx\n", machdep->last_pgd_read);
+	fprintf(fp, "      last_pmd_read: %lx\n", machdep->last_pmd_read);
+	fprintf(fp, "     last_ptbl_read: %lx\n", machdep->last_ptbl_read);
+	fprintf(fp, "clear_machdep_cache: NULL\n");
+	fprintf(fp, "                pgd: %lx\n", (ulong)machdep->pgd);
+	fprintf(fp, "                pmd: %lx\n", (ulong)machdep->pmd);
+	fprintf(fp, "               ptbl: %lx\n", (ulong)machdep->ptbl);
+	fprintf(fp, "       ptrs_per_pgd: %d\n", machdep->ptrs_per_pgd);
+	fprintf(fp, "  section_size_bits: %ld\n", machdep->section_size_bits);
+	fprintf(fp, "   max_physmem_bits: %ld\n", machdep->max_physmem_bits);
+	fprintf(fp, "  sections_per_root: %ld\n", machdep->sections_per_root);
+
+	for (i = 0; i < MAX_MACHDEP_ARGS; i++) {
+		fprintf(fp, "    cmdline_args[%d]: %s\n",
+			i, machdep->cmdline_args[i] ?
+			machdep->cmdline_args[i] : "(unused)");
+	}
+
+	ms = machdep->machspec;
+
+	fprintf(fp, "           machspec: %lx\n", (ulong)ms);
+	fprintf(fp, "          phys_base: %lx\n", ms->phys_base);
+	fprintf(fp, " vmalloc_start_addr: %lx\n", ms->vmalloc_start_addr);
+	fprintf(fp, "      modules_vaddr: %lx\n", ms->modules_vaddr);
+	fprintf(fp, "        modules_end: %lx\n", ms->modules_end);
+	fprintf(fp, "  kernel_text_start: %lx\n", ms->kernel_text_start);
+	fprintf(fp, "    kernel_text_end: %lx\n", ms->kernel_text_end);
+	fprintf(fp, "exception_text_start: %lx\n", ms->exception_text_start);
+	fprintf(fp, " exception_text_end: %lx\n", ms->exception_text_end);
+	fprintf(fp, "     crash_task_pid: %ld\n", ms->crash_task_pid);
+	fprintf(fp, "    crash_task_regs: %lx\n", (ulong)ms->crash_task_regs);
+}
+
+/*
+ * Retrieve task registers for the time of the crash.
+ */
+static int
+arm_get_crash_notes(void)
+{
+	struct machine_specific *ms = machdep->machspec;
+	ulong crash_notes;
+	Elf32_Nhdr *note;
+	ulong ptr, offset;
+	char *buf, *p;
+
+	if (!symbol_exists("crash_notes"))
+		return FALSE;
+
+	crash_notes = symbol_value("crash_notes");
+
+	if (kt->cpus > 1)
+		error(WARNING, "only one CPU is currently supported\n");
+
+	/*
+	 * Read crash_notes for the first CPU. crash_notes are in standard ELF
+	 * note format.
+	 */
+	if (!readmem(crash_notes, KVADDR, &ptr, sizeof(ptr), "crash_notes",
+		     RETURN_ON_ERROR)) {
+		error(WARNING, "cannot read crash_notes\n");
+		return FALSE;
+	}
+
+	buf = GETBUF(SIZE(note_buf));
+
+	if (!readmem(ptr, KVADDR, buf, SIZE(note_buf), "note_buf_t",
+		     RETURN_ON_ERROR)) {
+		error(WARNING, "failed to read note_buf_t\n");
+		goto fail;
+	}
+
+	/*
+	 * Do some sanity checks for this note before reading registers from it.
+	 */
+	note = (Elf32_Nhdr *)buf;
+	p = buf + sizeof(Elf32_Nhdr);
+
+	if (note->n_type != NT_PRSTATUS) {
+		error(WARNING, "invalid note (n_type != NT_PRSTATUS)\n");
+		goto fail;
+	}
+	if (p[0] != 'C' || p[1] != 'O' || p[2] != 'R' || p[3] != 'E') {
+		error(WARNING, "invalid note (name != \"CORE\"\n");
+		goto fail;
+	}
+
+	/*
+	 * Find correct location of note data. This contains elf_prstatus
+	 * structure which has registers etc. for the crashed task.
+	 */
+	offset = sizeof(Elf32_Nhdr);
+	offset = roundup(offset + note->n_namesz, 4);
+	p = buf + offset; /* start of elf_prstatus */
+
+	BCOPY(p + OFFSET(elf_prstatus_pr_reg), &panic_task_regs,
+	      sizeof(panic_task_regs));
+
+	/*
+	 * And finally we have pid and registers for the crashed task. This is
+	 * used later on when dumping backtrace.
+	 */
+	ms->crash_task_pid = *(ulong *)(p + OFFSET(elf_prstatus_pr_pid));
+	ms->crash_task_regs = &panic_task_regs;
+
+	FREEBUF(buf);
+	return TRUE;
+
+fail:
+	FREEBUF(buf);
+	return FALSE;
+}
+
+/*
+ * Accept or reject a symbol from the kernel namelist.
+ */
+static int
+arm_verify_symbol(const char *name, ulong value, char type)
+{
+	if (STREQ(name, "swapper_pg_dir"))
+		machdep->flags |= KSYMS_START;
+
+	if (!name || !strlen(name) || !(machdep->flags & KSYMS_START))
+		return FALSE;
+
+	if (STREQ(name, "$a") || STREQ(name, "$n") || STREQ(name, "$d"))
+		return FALSE;
+
+	if (CRASHDEBUG(8) && name && strlen(name))
+		fprintf(fp, "%08lx %s\n", value, name);
+
+	return TRUE;
+}
+
+static int
+arm_is_module_addr(ulong vaddr)
+{
+	ulong modules_start;
+	ulong modules_end = machdep->kvbase - 1;
+
+	if (!MODULES_VADDR) {
+		/*
+		 * In case we are still initializing, and vm_init() has not been
+		 * called, we use defaults here which is 16MB below kernel start
+		 * address.
+		 */
+		modules_start = machdep->kvbase - 16 * 1024 * 1024;
+	} else {
+		modules_start = MODULES_VADDR;
+	}
+
+	return (vaddr >= modules_start && vaddr <= modules_end);
+}
+
+int
+arm_is_vmalloc_addr(ulong vaddr)
+{
+	if (arm_is_module_addr(vaddr))
+		return TRUE;
+
+	if (!VMALLOC_START)
+		return FALSE;
+
+	return (vaddr >= VMALLOC_START);
+}
+
+/*
+ * Check whether given address falls inside kernel address space (including
+ * modules).
+ */
+static int
+arm_is_kvaddr(ulong vaddr)
+{
+	if (arm_is_module_addr(vaddr))
+		return TRUE;
+
+	return (vaddr >= machdep->kvbase);
+}
+
+/*
+ * Returns TRUE if given pc is in exception area.
+ */
+static int
+arm_in_exception_text(ulong pc)
+{
+	ulong exception_start = machdep->machspec->exception_text_start;
+	ulong exception_end = machdep->machspec->exception_text_end;
+
+	if (exception_start && exception_end)
+		return (pc >= exception_start && pc < exception_end);
+
+	return FALSE;
+}
+
+/*
+ * Unroll a kernel stack.
+ */
+static void
+arm_back_trace_cmd(struct bt_info *bt)
+{
+	if (!(kt->flags & DWARF_UNWIND)) {
+		error(WARNING, "unwinding without unwind tables is not "
+		      "supported yet!\n");
+		return;
+	}
+
+	if (!INSTACK(bt->stkptr, bt)) {
+		error(WARNING, "unwinding exception stack is not supported\n");
+		return;
+	}
+
+	unwind_backtrace(bt);
+}
+
+/*
+ * Calculate and return the speed of the processor.
+ */
+static ulong
+arm_processor_speed(void)
+{
+	/*
+	 * For now, we don't support reading CPU speed.
+	 */
+	return 0;
+}
+
+/*
+ * Translate a PTE, returning TRUE if the page is present. If a physaddr pointer
+ * is passed in, don't print anything.
+ */
+static int
+arm_translate_pte(ulong pte, void *physaddr, ulonglong pae_pte)
+{
+	char ptebuf[BUFSIZE];
+	char physbuf[BUFSIZE];
+	char buf[BUFSIZE];
+	int page_present;
+	ulong paddr;
+	int len1, len2, others;
+
+	page_present = pte_present(pte);
+	paddr = PAGEBASE(pte);
+
+	if (physaddr) {
+		*((ulong *)physaddr) = paddr;
+		return page_present;
+	}
+
+	sprintf(ptebuf, "%lx", pte);
+	len1 = MAX(strlen(ptebuf), strlen("PTE"));
+	fprintf(fp, "%s  ", mkstring(buf, len1, CENTER | LJUST, "PTE"));
+
+	if (!page_present && pte) {
+		/* swap page, not handled yet */
+		return page_present;
+	}
+
+	sprintf(physbuf, "%lx", paddr);
+	len2 = MAX(strlen(physbuf), strlen("PHYSICAL"));
+	fprintf(fp, "%s  ", mkstring(buf, len2, CENTER | LJUST, "PHYSICAL"));
+
+	fprintf(fp, "FLAGS\n");
+	fprintf(fp, "%s  %s  ",
+		mkstring(ptebuf, len1, CENTER | RJUST, NULL),
+		mkstring(physbuf, len2, CENTER | RJUST, NULL));
+
+	fprintf(fp, "(");
+	others = 0;
+
+	if (pte) {
+		if (pte_present(pte))
+			fprintf(fp, "%sPRESENT", others++ ? "|" : "");
+		if (pte_write(pte))
+			fprintf(fp, "%sWRITE", others++ ? "|" : "");
+		if (pte_dirty(pte))
+			fprintf(fp, "%sDIRTY", others++ ? "|" : "");
+		if (pte_young(pte))
+			fprintf(fp, "%sYOUNG", others++ ? "|" : "");
+	} else {
+		fprintf(fp, "no mapping");
+	}
+
+	fprintf(fp, ")\n");
+
+	return 0;
+}
+
+/*
+ * Virtual to physical memory translation. This function will be called by both
+ * arm_kvtop() and arm_uvtop().
+ */
+static int
+arm_vtop(ulong vaddr, ulong *pgd, physaddr_t *paddr, int verbose)
+{
+	char buf[BUFSIZE];
+	ulong *page_dir;
+	ulong *page_middle;
+	ulong *page_table;
+	ulong pgd_pte;
+	ulong pmd_pte;
+	ulong pte;
+
+	/*
+	 * Page tables in ARM Linux
+	 *
+	 * In hardware PGD is 16k (having 4096 pointers to PTE) and PTE is 1k
+	 * (containing 256 translations).
+	 *
+	 * Linux, however, wants to have PTEs as page sized entities. This means
+	 * that in ARM Linux we have following setup (see also
+	 * arch/arm/include/asm/pgtable.h)
+	 *
+	 *     PGD                   PTE
+	 * +---------+
+	 * |         | 0  ---->  +------------+
+	 * +- - - - -+           | h/w pt 0   |
+	 * |         | 4  ---->  +------------+ +1024
+	 * +- - - - -+           | h/w pt 1   |
+	 * .         .           +------------+ +2048
+	 * .         .           | Linux pt 0 |
+	 * .         .           +------------+ +3072
+	 * |         | 4095      | Linux pt 1 |
+	 * +---------+           +------------+ +4096
+	 *
+	 * So in Linux implementation we have two hardware pointers to second
+	 * level page tables. After these come "Linux" versions of the page
+	 * tables.
+	 *
+	 * Linux PT entries contain bits that are not supported on hardware, for
+	 * example "young" and "dirty" flags.
+	 *
+	 * Our translation scheme only uses Linux PTEs here. Hardware entries
+	 * are 1024 bytes below Linux versions.
+	 */
+
+	if (verbose)
+		fprintf(fp, "PAGE DIRECTORY: %lx\n", (ulong)pgd);
+
+	/*
+	 * pgd_offset(pgd, vaddr)
+	 */
+	page_dir = pgd + PGD_OFFSET(vaddr) * 2;
+
+	FILL_PGD(PAGEBASE(pgd), KVADDR, PGDIR_SIZE());
+	pgd_pte = ULONG(machdep->pgd + PGDIR_OFFSET(page_dir));
+
+	if (verbose)
+		fprintf(fp, "  PGD: %s => %lx\n",
+			mkstring(buf, VADDR_PRLEN, RJUST | LONG_HEX,
+			MKSTR((ulong)page_dir)), pgd_pte);
+
+	if (!pgd_pte)
+		return FALSE;
+
+	/*
+	 * pmd_offset(pgd, vaddr)
+	 *
+	 * Here PMD is folded into a PGD.
+	 */
+	pmd_pte = pgd_pte;
+	page_middle = page_dir;
+
+	if (verbose)
+		fprintf(fp, "  PMD: %s => %lx\n",
+			mkstring(buf, VADDR_PRLEN, RJUST | LONG_HEX,
+			MKSTR((ulong)page_middle)), pmd_pte);
+
+	if ((pmd_pte & PMD_TYPE_MASK) == PMD_TYPE_SECT) {
+		if (verbose) {
+			fprintf(fp, " PAGE: %s  (1MB)\n\n",
+				mkstring(buf, VADDR_PRLEN, RJUST | LONG_HEX,
+				MKSTR(PAGEBASE(pmd_pte))));
+		}
+		*paddr = PAGEBASE(pmd_pte) + (vaddr & ~_SECTION_PAGE_MASK);
+		return TRUE;
+	}
+
+	/*
+	 * pte_offset_map(pmd, vaddr)
+	 */
+	page_table = (ulong *)PTOV(pmd_page_addr(pmd_pte)) + PTE_OFFSET(vaddr);
+
+	FILL_PTBL(PAGEBASE(page_table), KVADDR, PAGESIZE());
+	pte = ULONG(machdep->ptbl + PAGEOFFSET(page_table));
+
+	if (verbose) {
+		fprintf(fp, "  PTE: %s => %lx\n\n",
+			mkstring(buf, VADDR_PRLEN, RJUST | LONG_HEX,
+			MKSTR((ulong)page_table)), pte);
+	}
+
+	if (!pte_present(pte)) {
+		if (pte && verbose) {
+			fprintf(fp, "\n");
+			arm_translate_pte(pte, 0, 0);
+		}
+		return FALSE;
+	}
+
+	*paddr = PAGEBASE(pte) + PAGEOFFSET(vaddr);
+
+	if (verbose) {
+		fprintf(fp, " PAGE: %s\n\n",
+			mkstring(buf, VADDR_PRLEN, RJUST | LONG_HEX,
+			MKSTR(PAGEBASE(pte))));
+		arm_translate_pte(pte, 0, 0);
+	}
+
+	return TRUE;
+}
+
+/*
+ * Translates a user virtual address to its physical address. cmd_vtop() sets
+ * the verbose flag so that the pte translation gets displayed; all other
+ * callers quietly accept the translation.
+ */
+static int
+arm_uvtop(struct task_context *tc, ulong uvaddr, physaddr_t *paddr, int verbose)
+{
+	ulong *pgd;
+	ulong mm;
+
+	if (!tc)
+		error(FATAL, "current context invalid\n");
+
+	*paddr = 0;
+
+	if (IS_KVADDR(uvaddr))
+		return arm_kvtop(tc, uvaddr, paddr, verbose);
+
+	mm = task_mm(tc->task, TRUE);
+	if (mm)
+		pgd = ULONG_PTR(tt->mm_struct + OFFSET(mm_struct_pgd));
+	else
+		readmem(tc->mm_struct + OFFSET(mm_struct_pgd), KVADDR, &pgd,
+			sizeof(long), "mm_struct pgd", FAULT_ON_ERROR);
+
+	return arm_vtop(uvaddr, pgd, paddr, verbose);
+}
+
+/*
+ * Translates a kernel virtual address to its physical address. cmd_vtop() sets
+ * the verbose flag so that the pte translation gets displayed; all other
+ * callers quietly accept the translation.
+ */
+static int
+arm_kvtop(struct task_context *tc, ulong kvaddr, physaddr_t *paddr, int verbose)
+{
+	if (!IS_KVADDR(kvaddr))
+		return FALSE;
+
+	if (!vt->vmalloc_start) {
+		*paddr = VTOP(kvaddr);
+		return TRUE;
+	}
+
+	if (!IS_VMALLOC_ADDR(kvaddr)) {
+		*paddr = VTOP(kvaddr);
+		if (!verbose)
+			return TRUE;
+	}
+
+	return arm_vtop(kvaddr, (ulong *)vt->kernel_pgd[0], paddr, verbose);
+}
+
+/*
+ * Get SP and PC values for idle tasks.
+ */
+static int
+arm_get_frame(struct bt_info *bt, ulong *pcp, ulong *spp)
+{
+	const char *cpu_context;
+
+	if (!bt->tc || !(tt->flags & THREAD_INFO))
+		return FALSE;
+
+	/*
+	 * Update thread_info in tt.
+	 */
+	if (!fill_thread_info(bt->tc->thread_info))
+		return FALSE;
+
+	cpu_context = tt->thread_info + OFFSET(thread_info_cpu_context);
+
+#define GET_REG(ptr, cp, off) ((*ptr) = (*((ulong *)((cp) + OFFSET(off)))))
+	/*
+	 * Unwinding code needs FP value also so we pass it with bt.
+	 */
+	GET_REG(&bt->frameptr, cpu_context, cpu_context_save_fp);
+	GET_REG(spp, cpu_context, cpu_context_save_sp);
+	GET_REG(pcp, cpu_context, cpu_context_save_pc);
+
+	return TRUE;
+}
+
+/*
+ * Get the starting point for the active cpu in a diskdump.
+ *
+ * Note that we currently support only UP machines. In future we might want to
+ * support SMP machines as well.
+ */
+static int
+arm_get_dumpfile_stack_frame(struct bt_info *bt, ulong *nip, ulong *ksp)
+{
+	const struct machine_specific *ms = machdep->machspec;
+
+	if (!ms->crash_task_regs)
+		return FALSE;
+
+	if (tt->panic_task != bt->task || bt->tc->pid != ms->crash_task_pid)
+		return FALSE;
+
+	/*
+	 * We got registers for panic task from crash_notes. Just return them.
+	 */
+	*nip = ms->crash_task_regs->ARM_pc;
+	*ksp = ms->crash_task_regs->ARM_sp;
+
+	/*
+	 * Also store pointer to all registers in case unwinding code needs
+	 * to access LR.
+	 */
+	bt->machdep = ms->crash_task_regs;
+
+	return TRUE;
+}
+
+/*
+ * Get a stack frame combination of PC and SP from the most relevant spot.
+ */
+static void
+arm_get_stack_frame(struct bt_info *bt, ulong *pcp, ulong *spp)
+{
+	ulong ip, sp;
+	int ret;
+
+	ip = sp = 0;
+	bt->machdep = NULL;
+
+	if (DUMPFILE() && is_task_active(bt->task))
+		ret = arm_get_dumpfile_stack_frame(bt, &ip, &sp);
+	else
+		ret = arm_get_frame(bt, &ip, &sp);
+
+	if (!ret) {
+		error(WARNING, "cannot get stackframe for task\n");
+		return;
+	}
+
+	if (pcp)
+		*pcp = ip;
+	if (spp)
+		*spp = sp;
+}
+
+/*
+ * Prints out exception stack starting from start.
+ */
+static void
+arm_dump_exception_stack(ulong start, ulong end)
+{
+	struct arm_pt_regs regs;
+	ulong flags;
+	char buf[64];
+
+	if (!readmem(start, KVADDR, &regs, sizeof(regs),
+		     "exception regs", RETURN_ON_ERROR)) {
+		error(WARNING, "failed to read exception registers\n");
+		return;
+	}
+
+	fprintf(fp, "    pc : [<%08lx>]    lr : [<%08lx>]    psr: %08lx\n"
+		"    sp : %08lx  ip : %08lx  fp : %08lx\n",
+		regs.ARM_pc, regs.ARM_lr, regs.ARM_cpsr,
+		regs.ARM_sp, regs.ARM_ip, regs.ARM_fp);
+	fprintf(fp, "    r10: %08lx  r9 : %08lx  r8 : %08lx\n",
+		regs.ARM_r10, regs.ARM_r9, regs.ARM_r8);
+	fprintf(fp, "    r7 : %08lx  r6 : %08lx  r5 : %08lx  r4 : %08lx\n",
+		regs.ARM_r7, regs.ARM_r6,
+		regs.ARM_r5, regs.ARM_r4);
+	fprintf(fp, "    r3 : %08lx  r2 : %08lx  r1 : %08lx  r0 : %08lx\n",
+		regs.ARM_r3, regs.ARM_r2,
+		regs.ARM_r1, regs.ARM_r0);
+
+	flags = regs.ARM_cpsr;
+	buf[0] = flags & PSR_N_BIT ? 'N' : 'n';
+	buf[1] = flags & PSR_Z_BIT ? 'Z' : 'z';
+	buf[2] = flags & PSR_C_BIT ? 'C' : 'c';
+	buf[3] = flags & PSR_V_BIT ? 'V' : 'v';
+	buf[4] = '\0';
+
+	fprintf(fp, "    Flags: %s  IRQs o%s  FIQs o%s  Mode %s  ISA %s\n",
+		buf, interrupts_enabled(&regs) ? "n" : "ff",
+		fast_interrupts_enabled(&regs) ? "n" : "ff",
+		processor_modes[processor_mode(&regs)],
+		isa_modes[isa_mode(&regs)]);
+}
+
+/*
+ * Pretty prints a single stack frame.
+ */
+void
+arm_dump_backtrace_entry(struct bt_info *bt, int level, ulong where,
+			 ulong from, ulong frame)
+{
+	struct load_module *lm;
+	const char *name;
+
+	name = closest_symbol(where);
+
+	if (module_symbol(where, NULL, &lm, NULL, 0)) {
+		fprintf(fp, "%s#%d [<%08lx>] (%s [%s]) from [<%08lx>]\n",
+			level < 10 ? " " : "",
+			level, where, name, lm->mod_name, from);
+	} else {
+		fprintf(fp, "%s#%d [<%08lx>] (%s) from [<%08lx>]\n",
+			level < 10 ? " " : "",
+			level, where, name, from);
+	}
+
+	if (bt->flags & BT_LINE_NUMBERS) {
+		char buf[BUFSIZE];
+
+		get_line_number(where, buf, FALSE);
+		if (strlen(buf))
+			fprintf(fp, "    %s\n", buf);
+	}
+
+	if (arm_in_exception_text(where)) {
+		ulong frame_start = frame + 4;
+		ulong frame_end = frame_start + sizeof(struct arm_pt_regs);
+
+		arm_dump_exception_stack(frame_start, frame_end);
+	}
+}
+
+/*
+ * Determine where vmalloc'd memory starts.
+ */
+static ulong
+arm_vmalloc_start(void)
+{
+	return vt->high_memory;
+}
+
+/*
+ * Checks whether given task is valid task address.
+ */
+static int
+arm_is_task_addr(ulong task)
+{
+	if (tt->flags & THREAD_INFO)
+		return IS_KVADDR(task);
+
+	return (IS_KVADDR(task) && ALIGNED_STACK_OFFSET(task) == 0);
+}
+
+/*
+ * Filter dissassembly output if the output radix is not gdb's default 10
+ */
+static int
+arm_dis_filter(ulong vaddr, char *inbuf)
+{
+	char buf1[BUFSIZE];
+	char buf2[BUFSIZE];
+	char *colon, *p1;
+	int argc;
+	char *argv[MAXARGS];
+	ulong value;
+
+	if (!inbuf)
+		return TRUE;
+/*
+ *  For some reason gdb can go off into the weeds translating text addresses,
+ *  (on alpha -- not necessarily seen on arm) so this routine both fixes the
+ *  references as well as imposing the current output radix on the translations.
+ */
+	console("IN: %s", inbuf);
+
+	colon = strstr(inbuf, ":");
+
+	if (colon) {
+		sprintf(buf1, "0x%lx <%s>", vaddr,
+			value_to_symstr(vaddr, buf2, pc->output_radix));
+		sprintf(buf2, "%s%s", buf1, colon);
+		strcpy(inbuf, buf2);
+	}
+
+	strcpy(buf1, inbuf);
+	argc = parse_line(buf1, argv);
+
+	if ((FIRSTCHAR(argv[argc-1]) == '<') &&
+	    (LASTCHAR(argv[argc-1]) == '>')) {
+		p1 = rindex(inbuf, '<');
+		while ((p1 > inbuf) && !STRNEQ(p1, " 0x"))
+			p1--;
+
+		if (!STRNEQ(p1, " 0x"))
+			return FALSE;
+		p1++;
+
+		if (!extract_hex(p1, &value, NULLCHAR, TRUE))
+			return FALSE;
+
+		sprintf(buf1, "0x%lx <%s>\n", value,
+			value_to_symstr(value, buf2, pc->output_radix));
+
+		sprintf(p1, buf1);
+	}
+
+	console("    %s", inbuf);
+
+	return TRUE;
+}
+
+/*
+ * Look for likely exception frames in a stack.
+ */
+static int
+arm_eframe_search(struct bt_info *bt)
+{
+	return (NOT_IMPLEMENTED());
+}
+
+/*
+ * Get the relevant page directory pointer from a task structure.
+ */
+static ulong
+arm_get_task_pgd(ulong task)
+{
+	return (NOT_IMPLEMENTED());
+}
+
+/*
+ * Machine dependent command.
+ */
+static void
+arm_cmd_mach(void)
+{
+	int c;
+
+	while ((c = getopt(argcnt, args, "cm")) != -1) {
+		switch (c) {
+		case 'c':
+		case 'm':
+			fprintf(fp, "ARM: '-%c' option is not supported\n", c);
+			break;
+
+		default:
+			argerrs++;
+			break;
+		}
+	}
+
+	if (argerrs)
+		cmd_usage(pc->curcmd, SYNOPSIS);
+
+	arm_display_machine_stats();
+}
+
+static void
+arm_display_machine_stats(void)
+{
+	struct new_utsname *uts;
+	char buf[BUFSIZE];
+	ulong mhz;
+
+	uts = &kt->utsname;
+
+	fprintf(fp, "       MACHINE TYPE: %s\n", uts->machine);
+	fprintf(fp, "        MEMORY SIZE: %s\n", get_memory_size(buf));
+	fprintf(fp, "               CPUS: %d\n", get_cpus_to_display());
+	fprintf(fp, "    PROCESSOR SPEED: ");
+	if ((mhz = machdep->processor_speed()))
+		fprintf(fp, "%ld Mhz\n", mhz);
+	else
+		fprintf(fp, "(unknown)\n");
+	fprintf(fp, "                 HZ: %d\n", machdep->hz);
+	fprintf(fp, "          PAGE SIZE: %d\n", PAGESIZE());
+	fprintf(fp, "KERNEL VIRTUAL BASE: %lx\n", machdep->kvbase);
+	fprintf(fp, "KERNEL VMALLOC BASE: %lx\n", vt->vmalloc_start);
+	fprintf(fp, "  KERNEL STACK SIZE: %ld\n", STACKSIZE());
+}
+
+static int
+arm_get_smp_cpus(void)
+{
+	return get_cpus_online();
+}
+
+/*
+ * Initialize ARM specific stuff.
+ */
+static void
+arm_init_machspec(void)
+{
+	struct machine_specific *ms = machdep->machspec;
+	ulong phys_base;
+
+	if (!DISKDUMP_DUMPFILE())
+		error(FATAL, "Only diskdump format is currently supported!\n");
+
+	/*
+	 * First determine actual phys_base. This was set in place by
+	 * makedumpfile so we can just read what diskdump gives us.
+	 */
+	if (!diskdump_phys_base(&phys_base))
+		error(FATAL, "Cannot determine phys_base\n");
+
+	ms->phys_base = phys_base;
+
+	if (symbol_exists("__exception_text_start") &&
+	    symbol_exists("__exception_text_end")) {
+		ms->exception_text_start = symbol_value("__exception_text_start");
+		ms->exception_text_end = symbol_value("__exception_text_end");
+	}
+
+	if (symbol_exists("_stext") && symbol_exists("_etext")) {
+		ms->kernel_text_start = symbol_value("_stext");
+		ms->kernel_text_end = symbol_value("_etext");
+	}
+
+	if (CRASHDEBUG(1)) {
+		fprintf(fp, "compressed kdump: phys_base: %lx\n",
+			phys_base);
+		fprintf(fp, "kernel text: [%lx - %lx]\n",
+			ms->kernel_text_start, ms->kernel_text_end);
+		fprintf(fp, "exception text: [%lx - %lx]\n",
+			ms->exception_text_start, ms->exception_text_end);
+	}
+}
+
+static const char *hook_files[] = {
+	"arch/arm/kernel/entry-armv.S",
+	"arch/arm/kernel/entry-common.S",
+};
+
+#define ENTRY_ARMV_S	((char **)&hook_files[0])
+#define ENTRY_COMMON_S	((char **)&hook_files[1])
+
+static struct line_number_hook arm_line_number_hooks[] = {
+	{ "__dabt_svc", ENTRY_ARMV_S },
+	{ "__irq_svc", ENTRY_ARMV_S },
+	{ "__und_svc", ENTRY_ARMV_S },
+	{ "__pabt_svc", ENTRY_ARMV_S },
+	{ "__switch_to", ENTRY_ARMV_S },
+
+	{ "ret_fast_syscall", ENTRY_COMMON_S },
+	{ "ret_slow_syscall", ENTRY_COMMON_S },
+	{ "ret_from_fork", ENTRY_COMMON_S },
+	{ NULL, NULL },
+};
+#endif /* ARM */
diff --git a/defs.h b/defs.h
index bd8d492..0f63539 100644
--- a/defs.h
+++ b/defs.h
@@ -84,6 +84,9 @@
 #ifdef S390X
 #define NR_CPUS  (64)
 #endif
+#ifdef ARM
+#define NR_CPUS  (1)
+#endif
 
 #define BUFSIZE  (1500)
 #define NULLCHAR ('\0')
@@ -976,6 +979,7 @@ struct offset_table {                    /* stash of commonly-used offsets */
 	long thread_info_cpu;
 	long thread_info_previous_esp;
 	long thread_info_flags;
+	long thread_info_cpu_context;
 	long nsproxy_mnt_ns;
 	long mnt_namespace_root;
 	long mnt_namespace_list;
@@ -1427,6 +1431,13 @@ struct offset_table {                    /* stash of commonly-used offsets */
         long unwind_table_size;
         long unwind_table_link;
         long unwind_table_name;
+	long unwind_table_list;
+	long unwind_table_start;
+	long unwind_table_stop;
+	long unwind_table_begin_addr;
+	long unwind_table_end_addr;
+	long unwind_idx_addr;
+	long unwind_idx_insn;
 	long rq_cfs;
 	long rq_rt;
 	long rq_nr_running;
@@ -1504,6 +1515,11 @@ struct offset_table {                    /* stash of commonly-used offsets */
 	long mm_rss_stat_count;
 	long module_module_init;
 	long module_init_text_size;
+	long cpu_context_save_fp;
+	long cpu_context_save_sp;
+	long cpu_context_save_pc;
+	long elf_prstatus_pr_pid;
+	long elf_prstatus_pr_reg;
 };
 
 struct size_table {         /* stash of commonly-used sizes */
@@ -1601,6 +1617,7 @@ struct size_table {         /* stash of commonly-used sizes */
 	long mem_section;
 	long pid_link;
 	long unwind_table;
+	long unwind_idx;
 	long rlimit;
 	long kmem_cache;
 	long kmem_cache_node;
@@ -1616,6 +1633,9 @@ struct size_table {         /* stash of commonly-used sizes */
 	long module_sect_attr;
 	long task_struct_utime;
 	long task_struct_stime;
+	long cpu_context_save;
+	long note_buf;
+	long elf_prstatus;
 };
 
 struct array_table {
@@ -2090,6 +2110,49 @@ struct load_module {
  *  Machine specific stuff
  */
 
+#ifdef ARM
+#define _32BIT_
+#define MACHINE_TYPE		"ARM"
+
+#define PAGEBASE(X)		(((ulong)(X)) & (ulong)machdep->pagemask)
+
+#define PTOV(X) \
+	((unsigned long)(X)-(machdep->machspec->phys_base)+(machdep->kvbase))
+#define VTOP(X) \
+	((unsigned long)(X)-(machdep->kvbase)+(machdep->machspec->phys_base))
+
+#define IS_VMALLOC_ADDR(X) 	arm_is_vmalloc_addr((ulong)(X))
+
+#define MODULES_VADDR   	(machdep->machspec->modules_vaddr)
+#define MODULES_END     	(machdep->machspec->modules_end)
+#define VMALLOC_START   	(machdep->machspec->vmalloc_start_addr)
+#define VMALLOC_END     	(machdep->machspec->vmalloc_end)
+
+#define PGDIR_SHIFT   		(21)
+#define PTRS_PER_PTE		(512)
+#define PTRS_PER_PGD		(2048)
+
+#define PGD_OFFSET(vaddr)       ((vaddr) >> PGDIR_SHIFT)
+#define PTE_OFFSET(vaddr)       (((vaddr) >> PAGESHIFT()) & (PTRS_PER_PTE - 1))
+
+#define __SWP_TYPE_SHIFT	3
+#define __SWP_TYPE_BITS		6
+#define __SWP_TYPE_MASK		((1 << __SWP_TYPE_BITS) - 1)
+#define __SWP_OFFSET_SHIFT	(__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
+
+#define SWP_TYPE(entry)		(((entry) >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
+#define SWP_OFFSET(entry)	((entry) >> __SWP_OFFSET_SHIFT)
+
+#define __swp_type(entry)	SWP_TYPE(entry)
+#define __swp_offset(entry)	SWP_OFFSET(entry)
+
+#define TIF_SIGPENDING		(2)
+
+#define _SECTION_SIZE_BITS	28
+#define _MAX_PHYSMEM_BITS	32
+
+#endif  /* ARM */
+
 #ifdef X86
 #define _32BIT_
 #define MACHINE_TYPE       "X86"
@@ -2786,6 +2849,10 @@ struct efi_memory_desc_t {
 #define SIZEOF_16BIT  (2)
 #define SIZEOF_8BIT   (1)
 
+#ifdef ARM
+#define MAX_HEXADDR_STRLEN (8)
+#define UVADDR_PRLEN       (8)
+#endif
 #ifdef X86
 #define MAX_HEXADDR_STRLEN (8)             
 #define UVADDR_PRLEN       (8)
@@ -2873,6 +2940,13 @@ struct efi_memory_desc_t {
 #define IRQ_LEVEL       64      /* IRQ level triggered */
 #define IRQ_MASKED      128     /* IRQ masked - shouldn't be seen again */
 
+#ifdef ARM
+#define SA_PROBE                SA_ONESHOT
+#define SA_SAMPLE_RANDOM        SA_RESTART
+#define SA_SHIRQ                0x04000000
+#define SA_RESTORER             0x04000000
+#endif
+
 #ifdef X86
 #define SA_PROBE                SA_ONESHOT
 #define SA_SAMPLE_RANDOM        SA_RESTART
@@ -3203,6 +3277,9 @@ void program_usage(int);
 #define SHORT_FORM (0)
 void dump_program_context(void);
 void dump_build_data(void);
+#ifdef ARM
+#define machdep_init(X) arm_init(X)
+#endif
 #ifdef X86
 #define machdep_init(X) x86_init(X)
 #endif
@@ -3561,6 +3638,9 @@ void help_init(void);
 void cmd_usage(char *, int);
 void display_version(void);
 void display_help_screen(char *);
+#ifdef ARM
+#define dump_machdep_table(X) arm_dump_machdep_table(X)
+#endif
 #ifdef X86
 #define dump_machdep_table(X) x86_dump_machdep_table(X)
 #endif
@@ -3839,6 +3919,57 @@ void read_in_kernel_config(int);
 void dev_init(void);
 void dump_dev_table(void);
 
+#ifdef ARM
+void arm_init(int);
+void arm_dump_machdep_table(ulong);
+void arm_display_idt_table(void);
+int arm_is_vmalloc_addr(ulong);
+void arm_dump_backtrace_entry(struct bt_info *, int, ulong, ulong, ulong);
+#define display_idt_table() \
+        error(FATAL, "-d option is not applicable to ARM architecture\n")
+
+struct arm_pt_regs {
+	ulong uregs[18];
+};
+
+#define ARM_cpsr	uregs[16]
+#define ARM_pc		uregs[15]
+#define ARM_lr		uregs[14]
+#define ARM_sp		uregs[13]
+#define ARM_ip		uregs[12]
+#define ARM_fp		uregs[11]
+#define ARM_r10		uregs[10]
+#define ARM_r9		uregs[9]
+#define ARM_r8		uregs[8]
+#define ARM_r7		uregs[7]
+#define ARM_r6		uregs[6]
+#define ARM_r5		uregs[5]
+#define ARM_r4		uregs[4]
+#define ARM_r3		uregs[3]
+#define ARM_r2		uregs[2]
+#define ARM_r1		uregs[1]
+#define ARM_r0		uregs[0]
+#define ARM_ORIG_r0	uregs[17]
+
+#define KSYMS_START	(0x1)
+
+struct machine_specific {
+	ulong phys_base;
+	ulong vmalloc_start_addr;
+	ulong modules_vaddr;
+	ulong modules_end;
+	ulong kernel_text_start;
+	ulong kernel_text_end;
+	ulong exception_text_start;
+	ulong exception_text_end;
+	ulong crash_task_pid;
+	struct arm_pt_regs *crash_task_regs;
+};
+
+int init_unwind_tables(void);
+void unwind_backtrace(struct bt_info *);
+#endif /* ARM */
+
 /*
  *  alpha.c
  */
diff --git a/unwind_arm.c b/unwind_arm.c
new file mode 100644
index 0000000..f3497a8
--- /dev/null
+++ b/unwind_arm.c
@@ -0,0 +1,702 @@
+/*
+ * Stack unwinding support for ARM
+ *
+ * This code is derived from the kernel source:
+ * arch/arm/kernel/unwind.c
+ * Copyright (C) 2008 ARM Limited
+ *
+ * Created by: Mika Westerberg <ext-mika.1.westerberg at nokia.com>
+ * Copyright (C) 2010 Nokia Corporation
+ *
+ * For more information about ARM unwind tables see "Exception handling ABI for
+ * the ARM architecture" document at:
+ *
+ * http://infocenter.arm.com/help/topic/com.arm.doc.subset.swdev.abi/index.html
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifdef ARM
+
+#include "defs.h"
+
+/**
+ * struct unwind_idx - index table entry
+ * @addr: prel31 offset to the start of the function
+ * @insn: index table entry.
+ *
+ * @insn can be encoded as follows:
+ *     1. if bit31 is clear this points to the start of the EHT entry
+ *        (prel31 offset)
+ *     2. if bit31 is set, this contains the EHT entry itself
+ *     3. if 0x1, cannot unwind.
+ *
+ * In case 1. @insn points to the EH table that comes directly after index
+ * table. This offset is relative to address of @insn which implies that we must
+ * allocate both index table and EH table in single chunk.
+ */
+struct unwind_idx {
+	ulong	addr;
+	ulong	insn;
+};
+
+/**
+ * struct unwind_table - per-module unwind table
+ * @idx: pointer to the star of the unwind table
+ * @start: pointer to the start of the index table
+ * @end: pointer to the last element +1 of the index table
+ * @begin_addr: start address which this table covers
+ * @end_addr: end address which this table covers
+ *
+ * Kernel stores per-module unwind tables in this format. There can be more than
+ * one table per module as we have different ELF sections in the module.
+ */
+struct unwind_table {
+	struct unwind_idx	*idx;
+	struct unwind_idx	*start;
+	struct unwind_idx	*end;
+	ulong			begin_addr;
+	ulong			end_addr;
+};
+
+/*
+ * Unwind table pointers to master kernel table and for modules.
+ */
+static struct unwind_table	*kernel_unwind_table;
+static struct unwind_table	*module_unwind_tables;
+
+struct unwind_ctrl_block {
+	ulong	vrs[16];
+	ulong	*insn;
+	int	entries;
+	int	byte;
+};
+
+enum regs {
+	FP = 11,
+	SP = 13,
+	LR = 14,
+	PC = 15,
+};
+
+struct stackframe {
+	ulong	fp;
+	ulong	sp;
+	ulong	lr;
+	ulong	pc;
+};
+
+static int init_kernel_unwind_table(void);
+static void free_kernel_unwind_table(void);
+static int read_module_unwind_table(struct unwind_table *, ulong);
+static int init_module_unwind_tables(void);
+static ulong unwind_get_byte(struct unwind_ctrl_block *);
+static ulong get_value_from_stack(ulong *);
+static int unwind_exec_insn(struct unwind_ctrl_block *);
+static int is_core_kernel_text(ulong);
+static struct unwind_idx *search_index(ulong);
+static ulong *prel31_to_addr(ulong *);
+static int unwind_frame(struct stackframe *, ulong);
+
+/*
+ * Function reads in-memory kernel and module unwind tables and makes
+ * local copy of them for unwinding. If unwinding tables cannot be found, this
+ * function returns FALSE, otherwise TRUE.
+ */
+int
+init_unwind_tables(void)
+{
+	if (!symbol_exists("__start_unwind_idx") ||
+	    !symbol_exists("__stop_unwind_idx") ||
+	    !symbol_exists("__start_unwind_tab") ||
+	    !symbol_exists("__stop_unwind_tab") ||
+	    !symbol_exists("unwind_tables")) {
+		return FALSE;
+	}
+
+	if (!init_kernel_unwind_table()) {
+		error(WARNING,
+		      "UNWIND: failed to initialize kernel unwind table\n");
+		return FALSE;
+	}
+
+	/*
+	 * Initialize symbols for per-module unwind tables. Actually there are
+	 * several tables per module (one per code section).
+	 */
+	STRUCT_SIZE_INIT(unwind_table, "unwind_table");
+	MEMBER_OFFSET_INIT(unwind_table_list, "unwind_table", "list");
+	MEMBER_OFFSET_INIT(unwind_table_start, "unwind_table", "start");
+	MEMBER_OFFSET_INIT(unwind_table_stop, "unwind_table", "stop");
+	MEMBER_OFFSET_INIT(unwind_table_begin_addr, "unwind_table",
+			   "begin_addr");
+	MEMBER_OFFSET_INIT(unwind_table_end_addr, "unwind_table", "end_addr");
+
+	STRUCT_SIZE_INIT(unwind_idx, "unwind_idx");
+	MEMBER_OFFSET_INIT(unwind_idx_addr, "unwind_idx", "addr");
+	MEMBER_OFFSET_INIT(unwind_idx_insn, "unwind_idx", "insn");
+
+	if (!init_module_unwind_tables()) {
+		error(WARNING,
+		      "UNWIND: failed to initialize module unwind tables\n");
+		free_kernel_unwind_table();
+		return FALSE;
+	}
+
+	/*
+	 * We abuse DWARF_UNWIND flag a little here as ARM unwinding tables are
+	 * not in DWARF format but we can use the flags to indicate that we have
+	 * unwind tables support ready.
+	 */
+	kt->flags |= DWARF_UNWIND_CAPABLE;
+	kt->flags |= DWARF_UNWIND;
+
+	return TRUE;
+}
+
+/*
+ * Allocate and fill master kernel unwind table.
+ */
+static int
+init_kernel_unwind_table(void)
+{
+	ulong idx_start, idx_end, idx_size;
+	ulong tab_end, tab_size;
+
+	kernel_unwind_table = calloc(sizeof(*kernel_unwind_table), 1);
+	if (!kernel_unwind_table)
+		return FALSE;
+
+	idx_start = symbol_value("__start_unwind_idx");
+	idx_end = symbol_value("__stop_unwind_idx");
+	tab_end = symbol_value("__stop_unwind_tab");
+
+	/*
+	 * Calculate sizes of the idx table and the EH table.
+	 */
+	idx_size = idx_end - idx_start;
+	tab_size = tab_end - idx_start;
+
+	kernel_unwind_table->idx = calloc(tab_size, 1);
+	if (!kernel_unwind_table->idx)
+		goto fail;
+
+	/*
+	 * Now read in both the index table and the EH table. We need to read in
+	 * both because prel31 offsets in the index table are relative to the
+	 * index address.
+	 */
+	if (!readmem(idx_start, KVADDR, kernel_unwind_table->idx, tab_size,
+		     "master kernel unwind table", RETURN_ON_ERROR))
+		goto fail;
+
+	kernel_unwind_table->start = kernel_unwind_table->idx;
+	kernel_unwind_table->end = (struct unwind_idx *)
+		((char *)kernel_unwind_table->idx + idx_size);
+	kernel_unwind_table->begin_addr = kernel_unwind_table->start->addr;
+	kernel_unwind_table->end_addr = (kernel_unwind_table->end - 1)->addr;
+
+	if (CRASHDEBUG(1)) {
+		fprintf(fp, "UNWIND: master kernel table start\n");
+		fprintf(fp, "UNWIND: size      : %ld\n", tab_size);
+		fprintf(fp, "UNWIND: start     : %p\n", kernel_unwind_table->start);
+		fprintf(fp, "UNWIND: end       : %p\n", kernel_unwind_table->end);
+		fprintf(fp, "UNWIND: begin_addr: 0x%lx\n",
+			kernel_unwind_table->begin_addr);
+		fprintf(fp, "UNWIND: begin_addr: 0x%lx\n",
+			kernel_unwind_table->end_addr);
+		fprintf(fp, "UNWIND: master kernel table end\n");
+	}
+
+	return TRUE;
+
+fail:
+	free(kernel_unwind_table->idx);
+	free(kernel_unwind_table);
+	return FALSE;
+}
+
+static void
+free_kernel_unwind_table(void)
+{
+	free(kernel_unwind_table->idx);
+	free(kernel_unwind_table);
+}
+
+/*
+ * Read single module unwind table from addr.
+ */
+static int
+read_module_unwind_table(struct unwind_table *tbl, ulong addr)
+{
+	ulong idx_start, idx_stop, idx_size;
+	char *buf;
+
+	buf = GETBUF(SIZE(unwind_table));
+
+	/*
+	 * First read in the unwind table for this module. It then contains
+	 * pointers to the index table which we will read later.
+	 */
+	if (!readmem(addr, KVADDR, buf, SIZE(unwind_table),
+		     "module unwind table", RETURN_ON_ERROR)) {
+		error(WARNING, "UNWIND: cannot read unwind table\n");
+		goto fail;
+	}
+
+#define TABLE_VALUE(b, offs) (*((ulong *)((b) + OFFSET(offs))))
+
+	idx_start = TABLE_VALUE(buf, unwind_table_start);
+	idx_stop = TABLE_VALUE(buf, unwind_table_stop);
+	idx_size = idx_stop - idx_start;
+
+	/*
+	 * We know the size of the index table. Allocate memory for the table
+	 * (including the EH table) and read the contents from the kernel
+	 * memory.
+	 */
+	tbl->idx = calloc(idx_size, 1);
+	if (!tbl->idx)
+		goto fail;
+
+	if (!readmem(idx_start, KVADDR, tbl->idx, idx_size,
+		     "module unwind index table", RETURN_ON_ERROR)) {
+		free(tbl->idx);
+		goto fail;
+	}
+
+	tbl->start = &tbl->idx[0];
+	tbl->end = (struct unwind_idx *)((char *)tbl->start + idx_size);
+	tbl->begin_addr = TABLE_VALUE(buf, unwind_table_begin_addr);
+	tbl->end_addr = TABLE_VALUE(buf, unwind_table_end_addr);
+
+	if (CRASHDEBUG(1)) {
+		fprintf(fp, "UNWIND: module table start\n");
+		fprintf(fp, "UNWIND: start     : %p\n", tbl->start);
+		fprintf(fp, "UNWIND: end       : %p\n", tbl->end);
+		fprintf(fp, "UNWIND: begin_addr: 0x%lx\n", tbl->begin_addr);
+		fprintf(fp, "UNWIND: begin_addr: 0x%lx\n", tbl->end_addr);
+		fprintf(fp, "UNWIND: module table end\n");
+	}
+
+	FREEBUF(buf);
+	return TRUE;
+
+fail:
+	FREEBUF(buf);
+	free(tbl->idx);
+	return FALSE;
+}
+
+/*
+ * Allocate and fill per-module unwind tables.
+ */
+static int
+init_module_unwind_tables(void)
+{
+	ulong head = symbol_value("unwind_tables");
+	struct unwind_table *tbl;
+	struct list_data ld;
+	ulong *table_list;
+	int cnt, i, n;
+
+	BZERO(&ld, sizeof(ld));
+	ld.start = head;
+	ld.member_offset = OFFSET(unwind_table_list);
+
+	if (CRASHDEBUG(1))
+		ld.flags |= VERBOSE;
+
+	/*
+	 * Iterate through unwind table list and store start address of each
+	 * table in table_list.
+	 */
+	hq_open();
+	cnt = do_list(&ld);
+	table_list = (ulong *)GETBUF(cnt * sizeof(ulong));
+	cnt = retrieve_list(table_list, cnt);
+	hq_close();
+
+	module_unwind_tables = calloc(sizeof(struct unwind_table), cnt);
+	if (!module_unwind_tables) {
+		error(WARNING,
+		      "UNWIND: failed to allocate memory for (%d tables)\n",
+		      cnt);
+		FREEBUF(table_list);
+		return FALSE;
+	}
+
+	/* we skip the first address as it is just head pointer */
+	for (i = 1, n = 0; i < cnt; i++, n++) {
+		tbl = &module_unwind_tables[n];
+		if (!read_module_unwind_table(tbl, table_list[i]))
+			goto fail;
+	}
+
+	/* just in case, zero the last entry (again) */
+	BZERO(&module_unwind_tables[n], sizeof(module_unwind_tables[n]));
+
+	FREEBUF(table_list);
+	return TRUE;
+
+fail:
+	FREEBUF(table_list);
+
+	while (--n >= 0) {
+		tbl = &module_unwind_tables[n];
+		free(tbl->idx);
+	}
+
+	free(module_unwind_tables);
+	return FALSE;
+}
+
+/*
+ * Return next insn byte from ctl or 0 in case of failure. As a side-effect,
+ * changes ctrl according the next byte.
+ */
+static ulong
+unwind_get_byte(struct unwind_ctrl_block *ctrl)
+{
+	ulong ret;
+
+	if (ctrl->entries <= 0) {
+		error(WARNING, "UNWIND: corrupt unwind entry\n");
+		return 0;
+	}
+
+	ret = (*ctrl->insn >> (ctrl->byte * 8)) & 0xff;
+
+	if (!ctrl->byte) {
+		ctrl->insn++;
+		ctrl->entries--;
+		ctrl->byte = 3;
+	} else {
+		ctrl->byte--;
+	}
+
+	return ret;
+}
+
+/*
+ * Gets one value from stack pointed by vsp.
+ */
+static ulong
+get_value_from_stack(ulong *vsp)
+{
+	ulong val;
+
+	/*
+	 * We just read the value from kernel memory instead of peeking it from
+	 * the bt->stack.
+	 */
+	if (!readmem((ulong)vsp, KVADDR, &val, sizeof(val),
+		"unwind stack value", RETURN_ON_ERROR)) {
+		error(FATAL, "unwind: failed to read value from stack\n");
+	}
+
+	return val;
+}
+
+/*
+ * Execute the next unwind instruction.
+ */
+static int
+unwind_exec_insn(struct unwind_ctrl_block *ctrl)
+{
+	ulong insn = unwind_get_byte(ctrl);
+
+	if ((insn & 0xc0) == 0) {
+		/*
+		 * 00xx xxxx: vsp = vsp + (xx xxx << 2) + 4
+		 *
+		 * Note that it seems that there is a typo in the spec and this
+		 * is corrected in kernel.
+		 */
+		ctrl->vrs[SP] += ((insn & 0x3f) << 2) + 4;
+	} else if ((insn & 0xc0) == 0x40) {
+		/* 00xx xxxx: vsp = vsp + (xx xxx << 2) + 4 */
+		ctrl->vrs[SP] -= ((insn & 0x3f) << 2) + 4;
+	} else if ((insn & 0xf0) == 0x80) {
+		/*
+		 * Pop up to 12 integer registers under masks
+		 * {r15-r12}, {r11-r4}.
+		 */
+		ulong mask;
+		ulong *vsp = (ulong *)ctrl->vrs[SP];
+		int load_sp, reg = 4;
+
+		insn = (insn << 8) | unwind_get_byte(ctrl);
+		mask = insn & 0x0fff;
+		if (mask == 0) {
+			error(WARNING, "UNWIND: refuse to unwind\n");
+			return FALSE;
+		}
+
+		/* pop {r4-r15} according to mask */
+		load_sp = mask & (1 << (13 - 4));
+		while (mask) {
+			if (mask & 1)
+				ctrl->vrs[reg] = get_value_from_stack(vsp++);
+			mask >>= 1;
+			reg++;
+		}
+		if (!load_sp)
+			ctrl->vrs[SP] = (ulong)vsp;
+	} else if ((insn & 0xf0) == 0x90 &&
+		   (insn & 0x0d) != 0x0d) {
+		/* 1001 nnnn: set vsp = r[nnnn] */
+		ctrl->vrs[SP] = ctrl->vrs[insn & 0x0f];
+	} else if ((insn & 0xf0) == 0xa0) {
+		/*
+		 * 1010 0nnn: pop r4-r[4+nnn]
+		 * 1010 1nnn: pop r4-r[4+nnn], r14
+		 */
+		ulong *vsp = (ulong *)ctrl->vrs[SP];
+		int reg;
+
+		for (reg = 4; reg <= 4 + (insn & 7); reg++)
+			ctrl->vrs[reg] = get_value_from_stack(vsp++);
+
+		if (insn & 0x80)
+			ctrl->vrs[14] = get_value_from_stack(vsp++);
+
+		ctrl->vrs[SP] = (ulong)vsp;
+	} else if (insn == 0xb0) {
+		/* 1011 0000: finish */
+		if (ctrl->vrs[PC] == 0)
+			ctrl->vrs[PC] = ctrl->vrs[LR];
+		/* no further processing */
+		ctrl->entries = 0;
+	} else if (insn == 0xb1) {
+		/* 1011 0001 xxxx yyyy: spare */
+		ulong mask = unwind_get_byte(ctrl);
+		ulong *vsp = (ulong *)ctrl->vrs[SP];
+		int reg = 0;
+
+		if (mask == 0 || mask & 0xf0) {
+			error(WARNING, "UNWIND: spare error\n");
+			return FALSE;
+		}
+
+		/* pop r0-r3 according to mask */
+		while (mask) {
+			if (mask & 1)
+				ctrl->vrs[reg] = get_value_from_stack(vsp++);
+			mask >>= 1;
+			reg++;
+		}
+		ctrl->vrs[SP] = (ulong)vsp;
+	} else if (insn == 0xb2) {
+		/* 1011 0010 uleb128: vsp = vsp + 0x204 (uleb128 << 2) */
+		ulong uleb128 = unwind_get_byte(ctrl);
+
+		ctrl->vrs[SP] += 0x204 + (uleb128 << 2);
+	} else {
+		error(WARNING, "UNWIND: unhandled instruction: %02lx\n", insn);
+		return FALSE;
+	}
+
+	return TRUE;
+}
+
+static int
+is_core_kernel_text(ulong pc)
+{
+	ulong text_start = machdep->machspec->kernel_text_start;
+	ulong text_end = machdep->machspec->kernel_text_end;
+
+	if (text_start && text_end)
+		return (pc >= text_start && pc <= text_end);
+
+	return FALSE;
+}
+
+static struct unwind_idx *
+search_index(ulong ip)
+{
+	struct unwind_idx *start = NULL;
+	struct unwind_idx *end = NULL;
+
+	/*
+	 * First check if this address is in the master kernel unwind table or
+	 * some of the module unwind tables.
+	 */
+	if (is_core_kernel_text(ip)) {
+		start = kernel_unwind_table->start;
+		end = kernel_unwind_table->end;
+	} else {
+		struct unwind_table *tbl;
+
+		for (tbl = &module_unwind_tables[0]; tbl->idx; tbl++) {
+			if (ip >= tbl->begin_addr && ip < tbl->end_addr) {
+				start = tbl->start;
+				end = tbl->end;
+				break;
+			}
+		}
+	}
+
+	if (start && end) {
+		/*
+		 * Do a binary search for the addresses in the index table.
+		 * Addresses are guaranteed to be sorted in ascending order.
+		 */
+		while (start < end - 1) {
+			struct unwind_idx *mid = start + ((end - start + 1) >> 1);
+
+			if (ip < mid->addr)
+				end = mid;
+			else
+				start = mid;
+		}
+
+		return start;
+	}
+
+	return NULL;
+}
+
+/*
+ * Convert a prel31 symbol to an absolute address.
+ */
+static ulong *
+prel31_to_addr(ulong *ptr)
+{
+	/* sign extend to 32 bits */
+	long offset = (((long)*ptr) << 1) >> 1;
+	return (ulong *)((ulong)ptr + offset);
+}
+
+static int
+unwind_frame(struct stackframe *frame, ulong stacktop)
+{
+	struct unwind_ctrl_block ctrl;
+	struct unwind_idx *idx;
+	ulong low, high;
+
+	low = frame->sp;
+	high = stacktop;
+
+	idx = search_index(frame->pc);
+	if (!idx) {
+		error(WARNING, "UNWIND: cannot find index for %lx\n",
+		      frame->pc);
+		return FALSE;
+	}
+
+	ctrl.vrs[FP] = frame->fp;
+	ctrl.vrs[SP] = frame->sp;
+	ctrl.vrs[LR] = frame->lr;
+	ctrl.vrs[PC] = 0;
+
+	if (CRASHDEBUG(5)) {
+		fprintf(fp, "UNWIND: >frame: FP=%lx\n", ctrl.vrs[FP]);
+		fprintf(fp, "UNWIND: >frame: SP=%lx\n", ctrl.vrs[SP]);
+		fprintf(fp, "UNWIND: >frame: LR=%lx\n", ctrl.vrs[LR]);
+		fprintf(fp, "UNWIND: >frame: PC=%lx\n", ctrl.vrs[PC]);
+	}
+
+	if (idx->insn == 1) {
+		/* can't unwind */
+		return FALSE;
+	} else if ((idx->insn & 0x80000000) == 0) {
+		/* insn contains offset to eht entry */
+		ctrl.insn = prel31_to_addr(&idx->insn);
+	} else if ((idx->insn & 0xff000000) == 0x80000000) {
+		/* eht entry is in insn itself */
+		ctrl.insn = &idx->insn;
+	} else {
+		error(WARNING, "UNWIND: unsupported instruction %lx\n",
+		      idx->insn);
+		return FALSE;
+	}
+
+	/* check the personality routine */
+	if ((*ctrl.insn & 0xff000000) == 0x80000000) {
+		ctrl.byte = 2;
+		ctrl.entries = 1;
+	} else if ((*ctrl.insn & 0xff000000) == 0x81000000) {
+		ctrl.byte = 1;
+		ctrl.entries = 1 + ((*ctrl.insn & 0x00ff0000) >> 16);
+	} else {
+		error(WARNING, "UNWIND: unsupported personality routine\n");
+		return FALSE;
+	}
+
+	/* now, execute the instructions */
+	while (ctrl.entries > 0) {
+		if (!unwind_exec_insn(&ctrl)) {
+			error(WARNING, "UNWIND: failed to exec instruction\n");
+			return FALSE;
+		}
+
+		if (ctrl.vrs[SP] < low || ctrl.vrs[SP] >= high)
+			return FALSE;
+	}
+
+	if (ctrl.vrs[PC] == 0)
+		ctrl.vrs[PC] = ctrl.vrs[LR];
+
+	if (frame->pc == ctrl.vrs[PC])
+		return FALSE;
+
+	frame->fp = ctrl.vrs[FP];
+	frame->sp = ctrl.vrs[SP];
+	frame->lr = ctrl.vrs[LR];
+	frame->pc = ctrl.vrs[PC];
+
+	if (CRASHDEBUG(5)) {
+		fprintf(fp, "UNWIND: <frame: FP=%lx\n", ctrl.vrs[FP]);
+		fprintf(fp, "UNWIND: <frame: SP=%lx\n", ctrl.vrs[SP]);
+		fprintf(fp, "UNWIND: <frame: LR=%lx\n", ctrl.vrs[LR]);
+		fprintf(fp, "UNWIND: <frame: PC=%lx\n", ctrl.vrs[PC]);
+	}
+
+	return TRUE;
+}
+
+void
+unwind_backtrace(struct bt_info *bt)
+{
+	struct stackframe frame;
+	int n = 0;
+
+	BZERO(&frame, sizeof(frame));
+	frame.fp = bt->frameptr;
+	frame.sp = bt->stkptr;
+	frame.pc = bt->instptr;
+
+	/*
+	 * In case bt->machdep contains pointer to a full register set, we take
+	 * LR from there.
+	 */
+	if (bt->machdep) {
+		const struct arm_pt_regs *regs = bt->machdep;
+
+		frame.lr = regs->ARM_lr;
+	}
+
+	while (1) {
+		ulong where = frame.pc;
+
+		if (!IS_KVADDR(where))
+			break;
+
+		if (!unwind_frame(&frame, bt->stacktop))
+			break;
+
+		/* call back to ARM code to actually print this frame */
+		arm_dump_backtrace_entry(bt, n++, where, frame.pc,
+					 frame.sp - 4);
+	}
+}
+#endif /* ARM */
-- 
1.5.6.5



From kgene.kim at samsung.com  Wed Jun 30 06:35:42 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 30 Jun 2010 19:35:42 +0900
Subject: [PATCH v5] libata: pata_samsung: Add Samsung PATA controller
	driver
In-Reply-To: <201006291529.45822.schindele@nentec.de>
References: <1277809518-1122-1-git-send-email-kgene.kim@samsung.com>
	<201006291529.45822.schindele@nentec.de>
Message-ID: <016e01cb1840$00bea9e0$023bfda0$%kim@samsung.com>

Juergen Schindele wrote:
> 
> Am Dienstag, 29. Juni 2010 schrieb Kukjin Kim:
> > From: Abhilash Kesavan <a.kesavan at samsung.com>
> >
> > Adds support for the Samsung PATA controller. This driver is based on
the
> > Libata subsystem and references the earlier patches sent for IDE
subsystem.
> Dear Kukjin Kim,

Hello, Juergen :-)

> as i had trouble with CF / trueIDE on PXA, have you read this thread ??
> <http://www.spinics.net/lists/arm-kernel/msg91461.html>
> Are you sure you dont need a "dcache_flush-page" ???
> Its just a thought to help you avoid problems.
> 
Thanks for your information.

Hmm..Abhilash and I have tested booting root fs on CF several times and
haven't found any problems yet.
Will test some more to make sure.

> Bye
> > Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> > Cc: Ben Dooks <ben-linux at fluff.org>
> > ---
> >  drivers/ata/Kconfig           |    9 +
> >  drivers/ata/Makefile          |    1 +
> >  drivers/ata/pata_samsung_cf.c |  728
> +++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 738 insertions(+), 0 deletions(-)
> >  create mode 100644 drivers/ata/pata_samsung_cf.c
> >

(snip)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From kgene.kim at samsung.com  Wed Jun 30 06:39:25 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 30 Jun 2010 19:39:25 +0900
Subject: [PATCH v5] libata: pata_samsung: Add Samsung PATA controller
	driver
In-Reply-To: <4C2A3C62.4090101@gmail.com>
References: <1277809518-1122-1-git-send-email-kgene.kim@samsung.com>
	<4C2A3C62.4090101@gmail.com>
Message-ID: <016f01cb1840$850c4ae0$8f24e0a0$%kim@samsung.com>

Maurus Cuelenaere wrote:
> 
Hi Maurus :-)

>  Op 29-06-10 13:05, Kukjin Kim schreef:
> > From: Abhilash Kesavan <a.kesavan at samsung.com>
> >
> > Adds support for the Samsung PATA controller. This driver is based on the
> > Libata subsystem and references the earlier patches sent for IDE subsystem.
> >
> > Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
> > Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
> > Cc: Ben Dooks <ben-linux at fluff.org>
> > ---
> >  drivers/ata/Kconfig           |    9 +
> >  drivers/ata/Makefile          |    1 +
> >  drivers/ata/pata_samsung_cf.c |  728
> +++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 738 insertions(+), 0 deletions(-)
> >  create mode 100644 drivers/ata/pata_samsung_cf.c
> >
> > diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
> > index 73f8833..51e28e7 100644
> > --- a/drivers/ata/Kconfig
> > +++ b/drivers/ata/Kconfig
> > @@ -796,6 +796,15 @@ config PATA_RZ1000
> >
> >  	  If unsure, say N.
> >
> > +config PATA_SAMSUNG_CF
> > +	tristate "Samsung SoC PATA support"
> > +	depends on SAMSUNG_DEV_IDE
> > +	help
> > +	  This option enables basic support for Samsung's S3C/S5P board
> > +	  PATA controllers via the new ATA layer
> > +
> > +	  If unsure, say N.
> > +
> >  config PATA_WINBOND_VLB
> >  	tristate "Winbond W83759A VLB PATA support (Experimental)"
> >  	depends on ISA && EXPERIMENTAL
> > diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
> > index 7ef89d7..9576776 100644
> > --- a/drivers/ata/Makefile
> > +++ b/drivers/ata/Makefile
> > @@ -87,6 +87,7 @@ obj-$(CONFIG_PATA_OF_PLATFORM)	+=
> pata_of_platform.o
> >  obj-$(CONFIG_PATA_QDI)		+= pata_qdi.o
> >  obj-$(CONFIG_PATA_RB532)	+= pata_rb532_cf.o
> >  obj-$(CONFIG_PATA_RZ1000)	+= pata_rz1000.o
> > +obj-$(CONFIG_PATA_SAMSUNG_CF)	+= pata_samsung_cf.o
> >  obj-$(CONFIG_PATA_WINBOND_VLB)	+= pata_winbond.o
> >
> >  # Should be last but two libata driver
> > diff --git a/drivers/ata/pata_samsung_cf.c b/drivers/ata/pata_samsung_cf.c
> > new file mode 100644
> > index 0000000..26b96c3
> > --- /dev/null
> > +++ b/drivers/ata/pata_samsung_cf.c
> > @@ -0,0 +1,728 @@
> > +/*
> > + * Copyright (c) 2010 Samsung Electronics Co., Ltd.
> > + *		http://www.samsung.com
> > + *
> > + * PATA driver for Samsung SoCs.
> > + * Supports CF Interface in True IDE mode. Currently only PIO mode has been
> > + * implemented; UDMA support has to be added.
> > + *
> > + * Based on:
> > + *	PATA driver for AT91SAM9260 Static Memory Controller
> > + *	PATA driver for Toshiba SCC controller
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms of the GNU General Public License version 2
> > + * as published by the Free Software Foundation.
> > +*/
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/init.h>
> > +#include <linux/clk.h>
> > +#include <linux/libata.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/slab.h>
> > +
> > +#include <plat/ata.h>
> > +#include <plat/regs-ata.h>
> > +
> > +#define DRV_NAME "pata_samsung_cf"
> > +#define DRV_VERSION "0.1"
> > +
> > +enum s3c_cpu_type {
> > +	TYPE_S3C64XX,
> > +	TYPE_S5PC100,
> > +	TYPE_S5PV210,
> > +};
> > +
> > +/*
> > + * struct s3c_ide_info - S3C PATA instance.
> > + * @clk: The clock resource for this controller.
> > + * @ide_addr: The area mapped for the hardware registers.
> > + * @sfr_addr: The area mapped for the special function registers.
> > + * @irq: The IRQ number we are using.
> > + * @cpu_type: The exact type of this controller.
> > + * @fifo_status_reg: The ATA_FIFO_STATUS register offset.
> > + */
> > +struct s3c_ide_info {
> > +	struct clk *clk;
> > +	void __iomem *ide_addr;
> > +	void __iomem *sfr_addr;
> > +	unsigned int irq;
> > +	enum s3c_cpu_type cpu_type;
> > +	unsigned int fifo_status_reg;
> > +};
> > +
> > +static void pata_s3c_set_endian(void __iomem *s3c_ide_regbase, u8 mode)
> > +{
> > +	u32 reg = readl(s3c_ide_regbase + S3C_ATA_CFG);
> > +	reg = mode ? (reg & ~S3C_ATA_CFG_SWAP) : (reg |
> S3C_ATA_CFG_SWAP);
> > +	writel(reg, s3c_ide_regbase + S3C_ATA_CFG);
> > +}
> > +
> > +static void pata_s3c_cfg_mode(void __iomem *s3c_ide_sfrbase)
> > +{
> > +	/* Select true-ide as the internal operating mode */
> > +	writel(readl(s3c_ide_sfrbase + S3C_CFATA_MUX) |
> S3C_CFATA_MUX_TRUEIDE,
> > +		s3c_ide_sfrbase + S3C_CFATA_MUX);
> > +}
> > +
> > +static unsigned long
> > +pata_s3c_setup_timing(struct s3c_ide_info *info, const struct ata_timing *ata)
> > +{
> > +	int t1 = ata->setup;
> > +	int t2 = ata->act8b;
> > +	int t2i = ata->rec8b;
> > +	ulong piotime;
> > +
> > +	piotime = ((t2i & 0xff) << 12) | ((t2 & 0xff) << 4) | (t1 & 0xf);
> > +
> > +	return piotime;
> > +}
> > +
> > +static void pata_s3c_set_piomode(struct ata_port *ap, struct ata_device *adev)
> > +{
> > +	struct s3c_ide_info *info = ap->host->private_data;
> > +	struct ata_timing timing;
> > +	int cycle_time;
> > +	ulong ata_cfg = readl(info->ide_addr + S3C_ATA_CFG);
> > +	ulong piotime;
> > +
> > +	/* Enables IORDY if mode requires it */
> > +	if (ata_pio_need_iordy(adev))
> > +		ata_cfg |= S3C_ATA_CFG_IORDYEN;
> > +	else
> > +		ata_cfg &= ~S3C_ATA_CFG_IORDYEN;
> > +
> > +	cycle_time = (int)(1000000000UL / clk_get_rate(info->clk));
> > +
> > +	ata_timing_compute(adev, adev->pio_mode, &timing,
> > +					cycle_time * 1000, 0);
> > +
> > +	piotime = pata_s3c_setup_timing(info, &timing);
> > +
> > +	writel(ata_cfg, info->ide_addr + S3C_ATA_CFG);
> > +	writel(piotime, info->ide_addr + S3C_ATA_PIO_TIME);
> > +}
> > +
> > +/*
> > + * Waits until the IDE controller is able to perform next read/write
> > + * operation to the disk. Needed for 64XX series boards only.
> > + */
> > +static int wait_for_host_ready(struct s3c_ide_info *info)
> > +{
> > +	ulong timeout;
> > +	void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
> > +
> 
> Shouldn't this have an if (type != S3C64XX) return 0; ?
> 
Actually, wait_for_host_ready() is called only by pata_s3c_port_ops methods which applies specifically to s3c64xx.

> > +	/* wait for maximum of 20 msec */
> > +	timeout = jiffies + msecs_to_jiffies(20);
> > +	while (time_before(jiffies, timeout)) {
> > +		if ((readl(fifo_reg) >> 28) == 0)
> > +			return 0;
> > +	}
> > +	return -EBUSY;
> > +}
> 
> --


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From mcuelenaere at gmail.com  Wed Jun 30 06:40:44 2010
From: mcuelenaere at gmail.com (Maurus Cuelenaere)
Date: Wed, 30 Jun 2010 12:40:44 +0200
Subject: [PATCH v5] libata: pata_samsung: Add Samsung PATA controller
	driver
In-Reply-To: <016f01cb1840$850c4ae0$8f24e0a0$%kim@samsung.com>
References: <1277809518-1122-1-git-send-email-kgene.kim@samsung.com>
	<4C2A3C62.4090101@gmail.com>
	<016f01cb1840$850c4ae0$8f24e0a0$%kim@samsung.com>
Message-ID: <4C2B1F2C.9070705@gmail.com>

 Op 30-06-10 12:39, Kukjin Kim schreef:
> Maurus Cuelenaere wrote:
> Hi Maurus :-)

Hi Kukjin

>>  Op 29-06-10 13:05, Kukjin Kim schreef:
>>> From: Abhilash Kesavan <a.kesavan at samsung.com>
>>>
>>> Adds support for the Samsung PATA controller. This driver is based on the
>>> Libata subsystem and references the earlier patches sent for IDE subsystem.
>>>
>>> Signed-off-by: Abhilash Kesavan <a.kesavan at samsung.com>
>>> Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
>>> Cc: Ben Dooks <ben-linux at fluff.org>
<snip>
>>> +/*
>>> + * Waits until the IDE controller is able to perform next read/write
>>> + * operation to the disk. Needed for 64XX series boards only.
>>> + */
>>> +static int wait_for_host_ready(struct s3c_ide_info *info)
>>> +{
>>> +	ulong timeout;
>>> +	void __iomem *fifo_reg = info->ide_addr + info->fifo_status_reg;
>>> +
>> Shouldn't this have an if (type != S3C64XX) return 0; ?
>>
> Actually, wait_for_host_ready() is called only by pata_s3c_port_ops methods 

Oh, ok. Sorry for the noise.

-- 
Maurus Cuelenaere


From u.kleine-koenig at pengutronix.de  Wed Jun 30 06:40:43 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 30 Jun 2010 12:40:43 +0200
Subject: ARM defconfig files
In-Reply-To: <20100614083214.GA2104@pengutronix.de>
References: <20100603074548.GA12104@flint.arm.linux.org.uk>
	<alpine.LFD.2.00.1006030725420.8175@i5.linux-foundation.org>
	<20100603181010.GA25779@flint.arm.linux.org.uk>
	<1275589230.23384.19.camel@c-dwalke-linux.qualcomm.com>
	<alpine.LFD.2.00.1006031119440.8175@i5.linux-foundation.org>
	<20100614083214.GA2104@pengutronix.de>
Message-ID: <20100630104043.GG11746@pengutronix.de>

Hi Linus,

I think my mail hit your inbox during your vacation.  As this is quite
important for the ARM people and there isn't much time left, can you
please comment?

Thanks in advance
Uwe

On Mon, Jun 14, 2010 at 10:32:14AM +0200, Uwe Kleine-K?nig wrote:
> Hello,
> 
> [Added linux-arm-kernel ML to Cc, note that it's moderated for
> non-subscribers.]
> 
> On Thu, Jun 03, 2010 at 11:21:59AM -0700, Linus Torvalds wrote:
> > 
> > 
> > On Thu, 3 Jun 2010, Daniel Walker wrote:
> > > 
> > > I don't see how we can do without defconfigs altogether tho. I mean , if
> > > you want to run a Beagle board or a Nexus one we can't just give the
> > > users a slim ARM config and let them troll through 1000's of drivers
> > > trying to find just those ones that work on their given board.
> > 
> > Well, you also don't need the full defconfig's with the kernel.
> > 
> > Right now they are just noise. They actually _hide_ things, because 
> > diffstat (and dirstat) information becomes pointless, and the diffs become 
> > totally unreadable by any human (trust me - when the choice is between 
> > "search for next relevant diff" or "blast it, I can't be bothered with 
> > walking through this crap", quite often the choice is the latter).
> I wrote a script that throws out all unneeded lines in all arm
> defconfigs that don't influence the resulting .config for .34 and
> .35-rc1 and compared .34<->.35-rc with .34-reduced<->.35-rc1-reduced.
> 
> Here are the results:
> 
> 	$ git diff --dirstat v2.6.34 v2.6.35-rc1 arch/arm
> 	  11.8% arch/arm/configs/
> 	  10.0% arch/arm/mach-msm/
> 	  10.8% arch/arm/mach-omap2/
> 	   4.8% arch/arm/mach-pxa/
> 	   4.5% arch/arm/mach-s5pc100/
> 	   3.3% arch/arm/mach-s5pv210/
> 	   4.4% arch/arm/mach-spear3xx/
> 	   3.1% arch/arm/mach-ux500/
> 	   5.1% arch/arm/plat-s5pc1xx/
> 	   3.1% arch/arm/plat-samsung/
> 	  38.2% arch/arm/
> 
> 	$ git diff --dirstat arm/defconfig/reduced-v2.6.34 arm/defconfig/reduced-v2.6.35-rc1 arch/arm
> 	   3.1% arch/arm/mach-davinci/
> 	  11.3% arch/arm/mach-msm/
> 	  12.2% arch/arm/mach-omap2/
> 	   5.4% arch/arm/mach-pxa/
> 	   5.1% arch/arm/mach-s5pc100/
> 	   3.7% arch/arm/mach-s5pv210/
> 	   5.0% arch/arm/mach-spear3xx/
> 	   3.5% arch/arm/mach-ux500/
> 	   5.8% arch/arm/plat-s5pc1xx/
> 	   3.5% arch/arm/plat-samsung/
> 	  40.9% arch/arm/
> 
> 	$ git diff --dirstat=0 arm/defconfig/reduced-v2.6.34 arm/defconfig/reduced-v2.6.35-rc1 arch/arm | grep config
> 	   1.1% arch/arm/configs/
> 
> 	$ git diff --shortstat v2.6.35-rc1 arm/defconfig/reduced-v2.6.35-rc1
> 	 177 files changed, 652 insertions(+), 194157 deletions(-)
> 
> (The insertions above are only moved lines I think, I didn't check them
> all.)
> 
> The branches arm/defconfig/reduced-v2.6.34 and
> arm/defconfig/reduced-v2.6.35-rc1 are available at my repo at
> git://git.pengutronix.de/git/ukl/linux-2.6.git .  (There is a gitweb at
> http://git.pengutronix.de/?p=ukl/linux-2.6.git)
> 
> So maintaining these minimal defconfigs would have reduced the defconfig
> noise from 11.8% down to 1.1%.  And probably it could be considerably
> reduced further with constructs like:
> 
> 	config HAVE_MTD_NAND_MXC
> 		bool
> 
> 	config MTD_NAND_MXC
> 		tristate "MXC NAND support"
> 		...
> 		default m if HAVE_MTD_NAND_MXC
> 		help
> 		  ...
> 
> 	...
> 	config MACH_MX27ADS
> 		...
> 		select HAVE_MTD_NAND_MXC
> 
> .  Compared with selecting everything in Kconfig files this approach
> allows further tweaking of a config.  (E.g. "I have a mx27ads machine,
> but I don't need nand support.")  Compared with the SAT-Solver it's an
> idea that works today.
> 
> One downside of this approach (when done with my script only) is that
> too much is removed.  E.g. in mx3_defconfig CONFIG_ARCH_MX3 is removed.
> This is OK from a logical POV but then changing the default of the
> corresponding choice (and I intend to do that in the near future) would
> break this defconfig.
> 
> I can share my script and I'm willing to support maintaining the
> minimality of the defconfig files if they are an acceptable (maybe
> intermediate) step for Linus.
> 
> Together with the efforts to reduce the number of defconfigs as thought
> about in other mails of this thread the situation should become quite
> better for Linus.  (I'm currently working on merging support for all
> Freescale SoCs into a single mach- directory and so merge mx1_defconfig,
> mx21_defconfig, mx27_defconfig, mx31pdk_defconfig, mx3_defconfig and
> mx51_defconfig.)
> 
> Linus: I would really appreciate if you wouldn't remove all (or nearly
> all) defconfig files.  I think you would force a quicker solution to
> this problem, but during that time the ARM community would loose compile
> coverage.
> 
> Thoughts on this?
> 
> Best regards
> Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From catalin.marinas at arm.com  Wed Jun 30 06:45:23 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 30 Jun 2010 11:45:23 +0100
Subject: [PATCH 0/2] RealView barriers and ARM_DMA_MEM_BUFFERABLE
Message-ID: <20100630104105.16712.66741.stgit@e102109-lin.cambridge.arm.com>

Hi,

This series is quite similar to the patch that Linus W. tested on
PB1176. The difference is that the RealView mandatory barriers are only
redefined for the ARM11MPCore boards in SMP configurations. For the UP
ones, the second patch is sufficient because of the #ifdef in system.h.

I split the patch in two so that the first one is applicable to 2.6.34
can can be sent to stable at kernel.org.

Linus, could you please confirm that the second patch still fixes the
PB1176 issues for you?

Thanks.


Catalin Marinas (2):
      ARM: RealView: Do not use outer_sync() on ARM11MPCore boards with L220
      ARM: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards with L210/L220


 arch/arm/mach-realview/Kconfig                 |    2 ++
 arch/arm/mach-realview/include/mach/barriers.h |    8 ++++++++
 arch/arm/mm/Kconfig                            |    2 ++
 3 files changed, 12 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-realview/include/mach/barriers.h

-- 
Catalin


From catalin.marinas at arm.com  Wed Jun 30 06:45:29 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 30 Jun 2010 11:45:29 +0100
Subject: [PATCH 1/2] ARM: RealView: Do not use outer_sync() on ARM11MPCore
	boards with L220
In-Reply-To: <20100630104105.16712.66741.stgit@e102109-lin.cambridge.arm.com>
References: <20100630104105.16712.66741.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100630104528.16712.39066.stgit@e102109-lin.cambridge.arm.com>

RealView boards with certain revisions of the L220 cache controller (ARM11*
processors only) may have issues (hardware deadlock) with the recent changes to
the mb() barrier implementation (DSB followed by an L2 cache sync). The patch
redefines the RealView ARM11MPCore mandatory barriers without the outer_sync()
call.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Russell King <rmk at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/mach-realview/Kconfig                 |    2 ++
 arch/arm/mach-realview/include/mach/barriers.h |    8 ++++++++
 2 files changed, 10 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-realview/include/mach/barriers.h

diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index ee5e392..b4575ae 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -18,6 +18,7 @@ config REALVIEW_EB_ARM11MP
 	bool "Support ARM11MPCore tile"
 	depends on MACH_REALVIEW_EB
 	select CPU_V6
+	select ARCH_HAS_BARRIERS if SMP
 	help
 	  Enable support for the ARM11MPCore tile on the Realview platform.
 
@@ -35,6 +36,7 @@ config MACH_REALVIEW_PB11MP
 	select CPU_V6
 	select ARM_GIC
 	select HAVE_PATA_PLATFORM
+	select ARCH_HAS_BARRIERS if SMP
 	help
 	  Include support for the ARM(R) RealView MPCore Platform Baseboard.
 	  PB11MPCore is a platform with an on-board ARM11MPCore and has
diff --git a/arch/arm/mach-realview/include/mach/barriers.h b/arch/arm/mach-realview/include/mach/barriers.h
new file mode 100644
index 0000000..0c5d749
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/barriers.h
@@ -0,0 +1,8 @@
+/*
+ * Barriers redefined for RealView ARM11MPCore platforms with L220 cache
+ * controller to work around hardware errata causing the outer_sync()
+ * operation to deadlock the system.
+ */
+#define mb()		dsb()
+#define rmb()		dmb()
+#define wmb()		mb()



From catalin.marinas at arm.com  Wed Jun 30 06:45:35 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 30 Jun 2010 11:45:35 +0100
Subject: [PATCH 2/2] ARM: Do not ARM_DMA_MEM_BUFFERABLE on RealView boards
	with L210/L220
In-Reply-To: <20100630104105.16712.66741.stgit@e102109-lin.cambridge.arm.com>
References: <20100630104105.16712.66741.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <20100630104534.16712.60870.stgit@e102109-lin.cambridge.arm.com>

RealView boards with certain revisions of the L210/L220 cache controller
may have issues (hardware deadlock) with the mandatory barriers (DSB
followed by an L2 cache sync) when ARM_DMA_MEM_BUFFERABLE is enabled.
The patch disables ARM_DMA_MEM_BUFFERABLE for these boards.

Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
Cc: Russell King <rmk at arm.linux.org.uk>
Cc: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/mm/Kconfig |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 3053731..9f10a9b 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -828,6 +828,8 @@ config ARM_L1_CACHE_SHIFT
 
 config ARM_DMA_MEM_BUFFERABLE
 	bool "Use non-cacheable memory for DMA" if CPU_V6 && !CPU_V7
+	depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
+		     MACH_REALVIEW_PB11MP)
 	default y if CPU_V6 || CPU_V7
 	help
 	  Historically, the kernel has used strongly ordered mappings to



From catalin.marinas at arm.com  Wed Jun 30 06:48:32 2010
From: catalin.marinas at arm.com (Catalin Marinas)
Date: Wed, 30 Jun 2010 11:48:32 +0100
Subject: Pending patches for -rc
In-Reply-To: <20100630101223.GA24284@n2100.arm.linux.org.uk>
References: <20100630101223.GA24284@n2100.arm.linux.org.uk>
Message-ID: <1277894912.13942.29.camel@e102109-lin.cambridge.arm.com>

On Wed, 2010-06-30 at 11:12 +0100, Russell King - ARM Linux wrote:
> ARM: 6189/1: Add support for the MOVW/MOVT relocations in Thumb-2

Thumb-2 modules of certain size may get these relocations and they'll
fail to load.

> ARM: 6190/1: Remove dummy loads from the original relocation address
> ARM: 6191/1: Do not compile the Thumb-2 module relocations on an ARM
> kernel

These two aren't critical, I agree.

BTW, should these patches be re-submitted or you would carry them to the
next merging window?

-- 
Catalin



From kgene.kim at samsung.com  Wed Jun 30 06:49:14 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 30 Jun 2010 19:49:14 +0900
Subject: [PATCH v5] ARM: S5PV210: Correct clock register properties
In-Reply-To: <1277873811-2823-1-git-send-email-myungjoo.ham@samsung.com>
References: <1277873811-2823-1-git-send-email-myungjoo.ham@samsung.com>
Message-ID: <017001cb1841$e43d8910$acb89b30$%kim@samsung.com>

MyungJoo Ham wrote:
> 
Hi MyungJoo,

Didn't check my previous reply?
Would be helpful to me if you could reply at that time about your any
problem or other opinion.

Actually, already applied your updated v4 patch.

> 1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which
were
> defined incorrectly.
> 
> 2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc,
> sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their
> twins defined in struct clk init_clocks_disable[] and struct clk
> init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK
> register to avoid the duplicated clock problem described below.
> 
> 
> What is Duplicated Clock Problem?
> 
> Please note that each clock definition should access different control
> register; otherwise, the system may suffer lockups. For example, if we
> have two clock definitions "a" and "b" which access the same register
> (and the shift value). Then, when we do:
> 
> 	module A
> 	clk = clk_get("a");
> 	clk->clk_enable(clk);
> 
> 	module B (context switch)
> 	clk = clk_get("b");
> 	clk->clk_enable(clk);
> 	do something with clk.
> 	clk->clk_disable(clk);
> 
> 	module A (context switch)
> 	do something with clk
> 	* At this point, the system may hang.
> 
> Therefore, there should be no clock definitions with the same contol
> register/shift. If we need to create "aliases", then, creating child
> clocks sharing the clock should be fine.
> 
> 3. Corrected other sclk_* shift values and access registers.
> 
> 
> Note that becuase UART clocks are properly disabled at boot time with
> this patch, UART drivers or somebody else should turn on the clock
> to read the console; otherwise, JIG willl not show any message.
> 
Please check my previous reply.
> 
> 
> Signed-off-by: MyungJoo Ham <myungjoo.ham at samsung.com>
> Signed-off-by: Kyungmin Park <kyungmin.park at samsung.com>
> ---
> Note that this patch revises and merges the two previous patches:
> [PATCH] S5PV210 Correct clock register properties
> [PATCH] S5PV210 Correct clock source control register properties
> And follows the previous patch
> [PATCH v2] S5PV210 Correct clock register properties
> [PATCH v3] S5PV210 Correct clock register properties
> [PATCH v4] S5PV210 Correct clock register properties
> v5 revises comments only from v4.
>  arch/arm/mach-s5pv210/clock.c |  115
++++++++++++++++++++++-------------------
>  1 files changed, 62 insertions(+), 53 deletions(-)
> 
> diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
> index 154bca4..b3d156c 100644
> --- a/arch/arm/mach-s5pv210/clock.c
> +++ b/arch/arm/mach-s5pv210/clock.c
(snip)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From tony at atomide.com  Wed Jun 30 07:08:29 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 14:08:29 +0300
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <alpine.LFD.2.00.1006291355520.24097@xanadu.home>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
	<20100623073912.GA12255@atomide.com>
	<20100623133636.GC7058@shareable.org>
	<20100629141836.GM2822@atomide.com>
	<alpine.LFD.2.00.1006291355520.24097@xanadu.home>
Message-ID: <20100630110828.GZ2822@atomide.com>

* Nicolas Pitre <nico at fluxnic.net> [100629 22:14]:
> On Tue, 29 Jun 2010, Tony Lindgren wrote:
> 
> > Also, can we detect somehow the hardware that uses CONFIG_TLS_REG_EMUL?
> > Might be possible to remove that Kconfig option too later on..
> 
> Well... I don't think we _should_ try to detect it as it is not widely 
> available if at all.

OK
 
> And there is actually a "bug" with __kuser_get_tls because if ever 
> CONFIG_TLS_REG_EMUL is selected then a call to __kuser_get_tls is 
> currently doing nothing while it should actually use the mrc 
> instruction.

I've changed it to initialize to mrc if (tls_emu || has_tls).

> Could this be a tristate instead?  There are actually 3 cases:
> 
> 1) We know the TLS reg is _always_ available i.e. ARMv6K, ARMV7 and 
>    above.  In that case the test on elf_hwcap is redundant and wasteful.
> 
> 2) We know the TLS reg is _never_ available i.e. pre-ARMv6.  The test on 
>    elf_hwcap is again redundant and wasteful.
> 
> 3) We're unsure as the actual CPU is known only at run time.
> 
> Case #1 will become the common case in the future.  Case #2 is still 
> widely relevant for deployed systems in the field, and some popular 
> ARMv5TE based SOCs are still produced right now.  So instead of 
> replacing #1 and #2 with #3, I think you should add #3 to the other 
> cases instead.

OK. I've implemented this logic in new file tls.h.

> >  #ifdef CONFIG_MMU
> >  	mcr	p15, 0, r6, c3, c0, 0		@ Set domain register
> > @@ -1009,16 +1011,13 @@ kuser_cmpxchg_fixup:
> >   */
> >  
> >  __kuser_get_tls:				@ 0xffff0fe0
> > -
> > -#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
> > -	ldr	r0, [pc, #(16 - 8)]		@ TLS stored at 0xffff0ff0
> > -#else
> > -	mrc	p15, 0, r0, c13, c0, 3		@ read TLS register
> > -#endif
> > +	nop				@ read TLS, set in kuser_get_tls_init
> >  	usr_ret	lr
> > -
> > -	.rep	5
> > -	.word	0			@ pad up to __kuser_helper_version
> > +	mrc	p15, 0, r0, c13, c0, 3	@ 0xffff0fe8 hardware TLS code
> > +	ldr	r0, [pc, #(16 - 8)]	@ 0xffff0fec software TLS code
> > +	.word	0			@ 0xffff0ff0 software TLS value
> > +	nop				@ pad up to __kuser_helper_version
> > +	nop
> >  	.endr
> 
> This looks obscur.  The idea of patching the appropriate instruction at 
> runtime here is a good one.  However I'd simply keep the ldr version in 
> place otherwise the pc displacement doesn't match anymore when 
> disassembling.  And simply overwrite it with the mrc version when 
> necessary.

OK, changed to use the ldr by default.
 
> BTW you left a stray .endr here.

Oops. I've put back the .rep .endrep instead of the nops now.
 
> > +	if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
> > +		elf_hwcap &= ~HWCAP_TLS;
> 
> You should probably test for the vendor ID as well (ARM in this case).

OK, added.
 
> > +}
> > +#else
> > +static inline void feat_v6_fixup(void)
> > +{
> > +}
> > +#endif
> 
> I think the #ifdef is unnecessary here.  This is __init code anyway, so 
> this could as well be always compiled in.

Removed.
 
> > diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
> > index 1621e53..85dd001 100644
> > --- a/arch/arm/kernel/traps.c
> > +++ b/arch/arm/kernel/traps.c
> > @@ -518,16 +518,19 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
> >  
> >  	case NR(set_tls):
> >  		thread->tp_value = regs->ARM_r0;
> > -#if defined(CONFIG_HAS_TLS_REG)
> > -		asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
> > -#elif !defined(CONFIG_TLS_REG_EMUL)
> > -		/*
> > -		 * User space must never try to access this directly.
> > -		 * Expect your app to break eventually if you do so.
> > -		 * The user helper at 0xffff0fe0 must be used instead.
> > -		 * (see entry-armv.S for details)
> > -		 */
> > -		*((unsigned int *)0xffff0ff0) = regs->ARM_r0;
> > +#if !defined(CONFIG_TLS_REG_EMUL)
> > +		if (elf_hwcap & HWCAP_TLS) {
> > +			asm ("mcr p15, 0, %0, c13, c0, 3"
> > +				: : "r" (regs->ARM_r0));
> > +		} else {
> > +			/*
> > +			 * User space must never try to access this directly.
> > +			 * Expect your app to break eventually if you do so.
> > +			 * The user helper at 0xffff0fe0 must be used instead.
> > +			 * (see entry-armv.S for details)
> > +			 */
> > +			*((unsigned int *)0xffff0ff0) = regs->ARM_r0;
> > +		}
> >  #endif
> 
> The same comment as for __kuser_get_tls would apply here.  However, 
> instead of duplicating the code block, you could define a macro, such as 
> has_tls_reg(), that would be either 0, 1, or ((elf_hwcap & HWCAP_TLS).

Now using tls_emu and has_tls defines.
 
> >  		return 0;
> >  
> > @@ -743,6 +746,21 @@ void __init trap_init(void)
> >  	return;
> >  }
> >  
> > +#if defined(CONFIG_TLS_REG_EMUL)
> > +static void __init kuser_get_tls_init(unsigned long vectors)
> > +{
> > +	memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
> > +}
> > +#else
> > +static void __init kuser_get_tls_init(unsigned long vectors)
> > +{
> > +	if (elf_hwcap & HWCAP_TLS)
> > +		memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
> > +	else
> > +		memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfec, 4);
> > +}
> > +#endif
> 
> Please move the #ifdef within the function body.  Also it would be nice 
> to add comments about what those magic offsets are.

This is now cleaner too with if (tls_emu || has_tls).

Updated patch below.

Regards,

Tony
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From rajkumar278 at hotmail.com  Wed Jun 30 07:22:01 2010
From: rajkumar278 at hotmail.com (Raj Kumar)
Date: Wed, 30 Jun 2010 16:52:01 +0530
Subject: Run time power management in linux kernel from 2.6.32
Message-ID: <BLU102-W152BFD91AB0F2CE91B71FEBCC0@phx.gbl>



Hi,
 
I am working in power management. I have few questions about run time power management
 
which was merged in linux 2.6.32 kernel onwards. Since the run time power management 
 
defines that when idle, suspend and resume will be scheduled, now the thing is from
 
device driver perspective, it is bus driver that will suspend and resume its devices.
 
but what from driver perspective driver needs to implement means as run time power
 
management has also helper functions which will tell PM core that when to call various
 
callbacks for suspend and resume for drivers (device, bus). 
 
But it might be case when the whole bus is not idle and still some drivers can be put
 
into low power mode. Then does bus driver will be responsible for invoking the driver's
 
suspend and resume (run time) or PM core will do that ?
 
Use cases:
------------
 
1) When the bus is idle
2) When the bus is not idle but still some peripherals can be put into low power mode......
 
 
 
 
 
Regards
Raj 		 	   		  

From kgene.kim at samsung.com  Wed Jun 30 07:38:10 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 30 Jun 2010 20:38:10 +0900
Subject: [PATCH] Add OneNAND devices to Aquila and GONI boards
In-Reply-To: <1277445127-16025-1-git-send-email-m.szyprowski@samsung.com>
References: <1277445127-16025-1-git-send-email-m.szyprowski@samsung.com>
Message-ID: <000901cb1848$bac66ff0$30534fd0$%kim@samsung.com>

Marek Szyprowski wrote:
> 
> Hello,
> 
> This short patch serie adds OneNAND devices to Aquila and GONI boards.
> The patches were earlier posted to mailing list but it looks they were
> lost, so I decided to resend them again.
> 
> The series contains the following patches:
> 
> [PATCH 1/2] ARM: S5PV210: Add OneNAND device to the GONI board
> [PATCH 2/2] ARM: S5PV210: Add OneNAND device to the Aquila board
> 
OK..will apply.

And please add Ben Dooks to 'cc'.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From tony at atomide.com  Wed Jun 30 07:39:19 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 14:39:19 +0300
Subject: [GIT PULL] omap fixes for 2.6.35-rc3
Message-ID: <20100630113919.GB2822@atomide.com>

Hi Linus,

Please pull omap fixes from:

git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git omap-fixes-for-linus

These all should match your "major bugs or regressions" criteria for
various omaps :)

Regards,

Tony


The following changes since commit 7e27d6e778cd87b6f2415515d7127eba53fe5d02:

  Linux 2.6.35-rc3 (2010-06-11 19:14:04 -0700)

are available in the git repository at:
  git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6.git omap-fixes

Amit Kucheria (1):
      omap: fix build failure due to missing include dma-mapping.h

Benoit Cousson (1):
      OMAP: hwmod: Fix the missing braces

Kevin Hilman (2):
      omap: GPIO: fix auto-disable of debounce clock
      OMAP3: PM: fix IO daisy chain enable to use PM_WKEN reg

Santosh Shilimkar (2):
      omap: Stalker board: switch over to gpio_set_debounce
      OMAP4: clock: Fix multi-omap boot with reset un-used clocks

Satish (1):
      omap iommu: Fix Memory leak

Tero Kristo (1):
      omap: DMTIMER: Ack pending interrupt always when stopping a timer

Tony Lindgren (1):
      Merge branch 'for_2.6.35rc' of git://git.pwsan.com/linux-2.6 into omap-fixes-for-linus

 arch/arm/mach-omap2/board-omap3stalker.c |    4 +---
 arch/arm/mach-omap2/clock44xx_data.c     |    2 ++
 arch/arm/mach-omap2/omap_hwmod.c         |    9 ++++++---
 arch/arm/mach-omap2/pm34xx.c             |    4 ++--
 arch/arm/mach-omap2/usb-ehci.c           |    2 ++
 arch/arm/plat-omap/dmtimer.c             |    6 +++---
 arch/arm/plat-omap/gpio.c                |    1 +
 arch/arm/plat-omap/iovmm.c               |    4 +++-
 8 files changed, 20 insertions(+), 12 deletions(-)


From tony at atomide.com  Wed Jun 30 08:06:23 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:06:23 +0300
Subject: [PATCH 00/16] omap mux updates for 2.6.36 merge window
Message-ID: <20100630120226.2637.31198.stgit@baageli.muru.com>

Hi all,

This series converts the remaining mach-omap2 code to use the
new mux framework that's already in use for omap3. After this
series we still need to add the mux data for omap4.

Regards,

Tony

---

Tony Lindgren (16):
      omap: mux: Fix omap_mux_init_gpio for omap24xx
      omap: mux: Renumber package defines to make room for older 24xx packages
      omap: mux: Allow compiling in new mux code on all mach-omap2 systems
      omap: mux: Remove unncessary parens from mux34xx.c
      omap: mux: Add data for 2420
      omap: mux: Add data for 2430
      omap: mux: Select SIP package for H4
      omap: mux: Select POP package for Apollon
      omap: mux: Select POP package for N8X0
      omap: mux: Select POP package for 2430SDP
      omap: mux: Make omap2 FS USB code use new mux functions
      omap: mux: Do keypad muxing in board-*.c files
      omap: mux: Mux Apollon LCD power in board-apollon.c
      omap: mux: Mux 2430 USB0HS_STP in board-2430.c
      omap: mux: Convert 2420 platform init code to use new mux code
      omap: mux: Remove old mux code


 arch/arm/mach-omap1/board-fsample.c          |   12 
 arch/arm/mach-omap1/board-h2.c               |   13 
 arch/arm/mach-omap1/board-h3.c               |   13 
 arch/arm/mach-omap1/board-perseus2.c         |   12 
 arch/arm/mach-omap2/Kconfig                  |   10 
 arch/arm/mach-omap2/Makefile                 |    2 
 arch/arm/mach-omap2/board-2430sdp.c          |   15 
 arch/arm/mach-omap2/board-3630sdp.c          |    1 
 arch/arm/mach-omap2/board-apollon.c          |   28 +
 arch/arm/mach-omap2/board-generic.c          |    1 
 arch/arm/mach-omap2/board-h4.c               |   36 +
 arch/arm/mach-omap2/board-n8x0.c             |   11 
 arch/arm/mach-omap2/board-rx51-peripherals.c |    1 
 arch/arm/mach-omap2/board-rx51-video.c       |    1 
 arch/arm/mach-omap2/devices.c                |   25 -
 arch/arm/mach-omap2/i2c.c                    |   27 -
 arch/arm/mach-omap2/io.c                     |    2 
 arch/arm/mach-omap2/mcbsp.c                  |   13 
 arch/arm/mach-omap2/mux.c                    |  308 ----------
 arch/arm/mach-omap2/mux.h                    |   28 +
 arch/arm/mach-omap2/mux2420.c                |  688 +++++++++++++++++++++++
 arch/arm/mach-omap2/mux2420.h                |  282 +++++++++
 arch/arm/mach-omap2/mux2430.c                |  791 ++++++++++++++++++++++++++
 arch/arm/mach-omap2/mux2430.h                |  370 ++++++++++++
 arch/arm/mach-omap2/mux34xx.c                |    8 
 arch/arm/mach-omap2/pm24xx.c                 |    1 
 arch/arm/mach-omap2/usb-ehci.c               |    1 
 arch/arm/mach-omap2/usb-fs.c                 |   33 +
 arch/arm/mach-omap2/usb-musb.c               |    1 
 arch/arm/mach-omap2/usb-tusb6010.c           |   14 
 arch/arm/plat-omap/devices.c                 |   61 --
 arch/arm/plat-omap/include/plat/mux.h        |  220 -------
 arch/arm/plat-omap/mux.c                     |    2 
 drivers/usb/musb/omap2430.c                  |    4 
 drivers/video/omap/lcd_apollon.c             |    3 
 35 files changed, 2359 insertions(+), 679 deletions(-)
 create mode 100644 arch/arm/mach-omap2/mux2420.c
 create mode 100644 arch/arm/mach-omap2/mux2420.h
 create mode 100644 arch/arm/mach-omap2/mux2430.c
 create mode 100644 arch/arm/mach-omap2/mux2430.h

-- 
Signature


From tony at atomide.com  Wed Jun 30 08:06:29 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:06:29 +0300
Subject: [PATCH 01/16] omap: mux: Fix omap_mux_init_gpio for omap24xx
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120629.2637.28177.stgit@baageli.muru.com>

Looks like 24xx uses mode3 instead of mode4 for muxable GPIO pins.
This will be needed when 24xx mux code is converted to use the new
mux functions.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/mux.c |   10 +++++++++-
 1 files changed, 9 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 8b3d269..76b5bf7 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -43,6 +43,7 @@
 
 #define OMAP_MUX_BASE_OFFSET		0x30	/* Offset from CTRL_BASE */
 #define OMAP_MUX_BASE_SZ		0x5ca
+#define MUXABLE_GPIO_MODE3		BIT(0)
 
 struct omap_mux_entry {
 	struct omap_mux		mux;
@@ -51,6 +52,7 @@ struct omap_mux_entry {
 
 static unsigned long mux_phys;
 static void __iomem *mux_base;
+static u8 omap_mux_flags;
 
 u16 omap_mux_read(u16 reg)
 {
@@ -394,7 +396,10 @@ int __init omap_mux_init_gpio(int gpio, int val)
 
 			old_mode = omap_mux_read(m->reg_offset);
 			mux_mode = val & ~(OMAP_MUX_NR_MODES - 1);
-			mux_mode |= OMAP_MUX_MODE4;
+			if (omap_mux_flags & MUXABLE_GPIO_MODE3)
+				mux_mode |= OMAP_MUX_MODE3;
+			else
+				mux_mode |= OMAP_MUX_MODE4;
 			printk(KERN_DEBUG "mux: Setting signal "
 				"%s.gpio%i 0x%04x -> 0x%04x\n",
 				m->muxnames[0], gpio, old_mode, mux_mode);
@@ -1032,6 +1037,9 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
 		return -ENODEV;
 	}
 
+	if (cpu_is_omap24xx())
+		omap_mux_flags = MUXABLE_GPIO_MODE3;
+
 	omap_mux_init_package(superset, package_subset, package_balls);
 	omap_mux_init_list(superset);
 	omap_mux_init_signals(board_mux);



From tony at atomide.com  Wed Jun 30 08:06:35 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:06:35 +0300
Subject: [PATCH 02/16] omap: mux: Renumber package defines to make room for
	older 24xx packages
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120635.2637.4819.stgit@baageli.muru.com>

Only POP and SIP are known to exist for 2420, 2430 seems to only have
SIP package available.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/mux.h |   10 ++++++----
 1 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 480abc5..46315f2 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -56,10 +56,12 @@
 
 /* Flags for omap_mux_init */
 #define OMAP_PACKAGE_MASK		0xffff
-#define OMAP_PACKAGE_CBP		4		/* 515-pin 0.40 0.50 */
-#define OMAP_PACKAGE_CUS		3		/* 423-pin 0.65 */
-#define OMAP_PACKAGE_CBB		2		/* 515-pin 0.40 0.50 */
-#define OMAP_PACKAGE_CBC		1		/* 515-pin 0.50 0.65 */
+#define OMAP_PACKAGE_CBP		6		/* 515-pin 0.40 0.50 */
+#define OMAP_PACKAGE_CUS		5		/* 423-pin 0.65 */
+#define OMAP_PACKAGE_CBB		4		/* 515-pin 0.40 0.50 */
+#define OMAP_PACKAGE_CBC		3		/* 515-pin 0.50 0.65 */
+#define OMAP_PACKAGE_ZAC		2		/* 24xx 447-pin POP */
+#define OMAP_PACKAGE_ZAF		1		/* 2420 447-pin SIP */
 
 
 #define OMAP_MUX_NR_MODES	8			/* Available modes */



From tony at atomide.com  Wed Jun 30 08:06:39 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:06:39 +0300
Subject: [PATCH 03/16] omap: mux: Allow compiling in new mux code on all
	mach-omap2 systems
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120639.2637.54819.stgit@baageli.muru.com>

Allow compiling in new mux code on all mach-omap2 systems

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/mux.c |    2 +-
 arch/arm/mach-omap2/mux.h |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 76b5bf7..197e295 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -372,7 +372,7 @@ int __init omap2_mux_init(void)
 
 /*----------------------------------------------------------------------------*/
 
-#ifdef CONFIG_ARCH_OMAP3
+#ifdef CONFIG_ARCH_OMAP2PLUS
 static LIST_HEAD(muxmodes);
 static DEFINE_MUTEX(muxmode_mutex);
 
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 46315f2..937a8ca 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -104,7 +104,7 @@ struct omap_board_mux {
 	u16	value;
 };
 
-#if defined(CONFIG_OMAP_MUX) && defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_OMAP_MUX)
 
 /**
  * omap_mux_init_gpio - initialize a signal based on the GPIO number



From tony at atomide.com  Wed Jun 30 08:06:42 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:06:42 +0300
Subject: [PATCH 04/16] omap: mux: Remove unncessary parens from mux34xx.c
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120642.2637.81925.stgit@baageli.muru.com>

Remove unncessary parens from mux34xx.c

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/mux34xx.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-omap2/mux34xx.c b/arch/arm/mach-omap2/mux34xx.c
index 2ff4dce..f64d7ee 100644
--- a/arch/arm/mach-omap2/mux34xx.c
+++ b/arch/arm/mach-omap2/mux34xx.c
@@ -2032,19 +2032,19 @@ int __init omap3_mux_init(struct omap_board_mux *board_subset, int flags)
 	struct omap_ball *package_balls;
 
 	switch (flags & OMAP_PACKAGE_MASK) {
-	case (OMAP_PACKAGE_CBC):
+	case OMAP_PACKAGE_CBC:
 		package_subset = omap3_cbc_subset;
 		package_balls = omap3_cbc_ball;
 		break;
-	case (OMAP_PACKAGE_CBB):
+	case OMAP_PACKAGE_CBB:
 		package_subset = omap3_cbb_subset;
 		package_balls = omap3_cbb_ball;
 		break;
-	case (OMAP_PACKAGE_CUS):
+	case OMAP_PACKAGE_CUS:
 		package_subset = omap3_cus_subset;
 		package_balls = omap3_cus_ball;
 		break;
-	case (OMAP_PACKAGE_CBP):
+	case OMAP_PACKAGE_CBP:
 		package_subset = omap36xx_cbp_subset;
 		package_balls = omap36xx_cbp_ball;
 		break;



From tony at atomide.com  Wed Jun 30 08:06:46 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:06:46 +0300
Subject: [PATCH 05/16] omap: mux: Add data for 2420
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120645.2637.55163.stgit@baageli.muru.com>

Add data for 2420. Big thanks to Paul Walmsley <paul at pwsan.com>
for generating usable mux data out of TRMs.

Cc: Benoit Cousson <b-cousson at ti.com>
Signed-off-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig   |    6 
 arch/arm/mach-omap2/Makefile  |    1 
 arch/arm/mach-omap2/mux.h     |    8 
 arch/arm/mach-omap2/mux2420.c |  688 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/mux2420.h |  282 +++++++++++++++++
 5 files changed, 985 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-omap2/mux2420.c
 create mode 100644 arch/arm/mach-omap2/mux2420.h

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b31b6f1..d3932d3 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -17,6 +17,12 @@ config ARCH_OMAP3430
 	depends on ARCH_OMAP3
 	select ARCH_OMAP_OTG
 
+config OMAP_PACKAGE_ZAF
+       bool
+
+config OMAP_PACKAGE_ZAC
+       bool
+
 config OMAP_PACKAGE_CBC
        bool
 
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 0416643..b7e5537 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -36,6 +36,7 @@ AFLAGS_sram243x.o			:=-Wa,-march=armv6
 AFLAGS_sram34xx.o			:=-Wa,-march=armv7-a
 
 # Pin multiplexing
+obj-$(CONFIG_ARCH_OMAP2420)		+= mux2420.o
 obj-$(CONFIG_ARCH_OMAP3)		+= mux34xx.o
 
 # SMS/SDRC
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index 937a8ca..e14cd4d 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -7,6 +7,7 @@
  * published by the Free Software Foundation.
  */
 
+#include "mux2420.h"
 #include "mux34xx.h"
 
 #define OMAP_MUX_TERMINATOR	0xffff
@@ -173,6 +174,13 @@ void omap_mux_write(u16 val, u16 mux_offset);
 void omap_mux_write_array(struct omap_board_mux *board_mux);
 
 /**
+ * omap2420_mux_init() - initialize mux system with board specific set
+ * @board_mux:		Board specific mux table
+ * @flags:		OMAP package type used for the board
+ */
+int omap2420_mux_init(struct omap_board_mux *board_mux, int flags);
+
+/**
  * omap3_mux_init() - initialize mux system with board specific set
  * @board_mux:		Board specific mux table
  * @flags:		OMAP package type used for the board
diff --git a/arch/arm/mach-omap2/mux2420.c b/arch/arm/mach-omap2/mux2420.c
new file mode 100644
index 0000000..fdb04a7
--- /dev/null
+++ b/arch/arm/mach-omap2/mux2420.c
@@ -0,0 +1,688 @@
+/*
+ * Copyright (C) 2010 Nokia
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_OMAP_MUX
+
+#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)		\
+{									\
+	.reg_offset	= (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET),	\
+	.gpio		= (g),						\
+	.muxnames	= { m0, m1, m2, m3, m4, m5, m6, m7 },		\
+}
+
+#else
+
+#define _OMAP2420_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)		\
+{									\
+	.reg_offset	= (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET),	\
+	.gpio		= (g),						\
+}
+
+#endif
+
+#define _OMAP2420_BALLENTRY(M0, bb, bt)					\
+{									\
+	.reg_offset	= (OMAP2420_CONTROL_PADCONF_##M0##_OFFSET),	\
+	.balls		= { bb, bt },					\
+}
+
+/*
+ * Superset of all mux modes for omap2420
+ */
+static struct omap_mux __initdata omap2420_muxmodes[] = {
+	_OMAP2420_MUXENTRY(CAM_D0, 54,
+		"cam_d0", "hw_dbg2", "sti_dout", "gpio_54",
+		NULL, NULL, "etk_d2", NULL),
+	_OMAP2420_MUXENTRY(CAM_D1, 53,
+		"cam_d1", "hw_dbg3", "sti_din", "gpio_53",
+		NULL, NULL, "etk_d3", NULL),
+	_OMAP2420_MUXENTRY(CAM_D2, 52,
+		"cam_d2", "hw_dbg4", "mcbsp1_clkx", "gpio_52",
+		NULL, NULL, "etk_d4", NULL),
+	_OMAP2420_MUXENTRY(CAM_D3, 51,
+		"cam_d3", "hw_dbg5", "mcbsp1_dr", "gpio_51",
+		NULL, NULL, "etk_d5", NULL),
+	_OMAP2420_MUXENTRY(CAM_D4, 50,
+		"cam_d4", "hw_dbg6", "mcbsp1_fsr", "gpio_50",
+		NULL, NULL, "etk_d6", NULL),
+	_OMAP2420_MUXENTRY(CAM_D5, 49,
+		"cam_d5", "hw_dbg7", "mcbsp1_clkr", "gpio_49",
+		NULL, NULL, "etk_d7", NULL),
+	_OMAP2420_MUXENTRY(CAM_D6, 0,
+		"cam_d6", "hw_dbg8", NULL, NULL,
+		NULL, NULL, "etk_d8", NULL),
+	_OMAP2420_MUXENTRY(CAM_D7, 0,
+		"cam_d7", "hw_dbg9", NULL, NULL,
+		NULL, NULL, "etk_d9", NULL),
+	_OMAP2420_MUXENTRY(CAM_D8, 54,
+		"cam_d8", "hw_dbg10", NULL, "gpio_54",
+		NULL, NULL, "etk_d10", NULL),
+	_OMAP2420_MUXENTRY(CAM_D9, 53,
+		"cam_d9", "hw_dbg11", NULL, "gpio_53",
+		NULL, NULL, "etk_d11", NULL),
+	_OMAP2420_MUXENTRY(CAM_HS, 55,
+		"cam_hs", "hw_dbg1", "mcbsp1_dx", "gpio_55",
+		NULL, NULL, "etk_d1", NULL),
+	_OMAP2420_MUXENTRY(CAM_LCLK, 57,
+		"cam_lclk", NULL, "mcbsp_clks", "gpio_57",
+		NULL, NULL, "etk_c1", NULL),
+	_OMAP2420_MUXENTRY(CAM_VS, 56,
+		"cam_vs", "hw_dbg0", "mcbsp1_fsx", "gpio_56",
+		NULL, NULL, "etk_d0", NULL),
+	_OMAP2420_MUXENTRY(CAM_XCLK, 0,
+		"cam_xclk", NULL, "sti_clk", NULL,
+		NULL, NULL, "etk_c2", NULL),
+	_OMAP2420_MUXENTRY(DSS_ACBIAS, 48,
+		"dss_acbias", NULL, "mcbsp2_fsx", "gpio_48",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(DSS_DATA10, 40,
+		"dss_data10", NULL, NULL, "gpio_40",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(DSS_DATA11, 41,
+		"dss_data11", NULL, NULL, "gpio_41",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(DSS_DATA12, 42,
+		"dss_data12", NULL, NULL, "gpio_42",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(DSS_DATA13, 43,
+		"dss_data13", NULL, NULL, "gpio_43",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(DSS_DATA14, 44,
+		"dss_data14", NULL, NULL, "gpio_44",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(DSS_DATA15, 45,
+		"dss_data15", NULL, NULL, "gpio_45",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(DSS_DATA16, 46,
+		"dss_data16", NULL, NULL, "gpio_46",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(DSS_DATA17, 47,
+		"dss_data17", NULL, NULL, "gpio_47",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(DSS_DATA8, 38,
+		"dss_data8", NULL, NULL, "gpio_38",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(DSS_DATA9, 39,
+		"dss_data9", NULL, NULL, "gpio_39",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(EAC_AC_DIN, 115,
+		"eac_ac_din", "mcbsp2_dr", NULL, "gpio_115",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(EAC_AC_DOUT, 116,
+		"eac_ac_dout", "mcbsp2_dx", NULL, "gpio_116",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(EAC_AC_FS, 114,
+		"eac_ac_fs", "mcbsp2_fsx", NULL, "gpio_114",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(EAC_AC_MCLK, 117,
+		"eac_ac_mclk", NULL, NULL, "gpio_117",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(EAC_AC_RST, 118,
+		"eac_ac_rst", "eac_bt_din", NULL, "gpio_118",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(EAC_AC_SCLK, 113,
+		"eac_ac_sclk", "mcbsp2_clkx", NULL, "gpio_113",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(EAC_BT_DIN, 73,
+		"eac_bt_din", NULL, NULL, "gpio_73",
+		NULL, NULL, "etk_d9", NULL),
+	_OMAP2420_MUXENTRY(EAC_BT_DOUT, 74,
+		"eac_bt_dout", NULL, "sti_clk", "gpio_74",
+		NULL, NULL, "etk_d8", NULL),
+	_OMAP2420_MUXENTRY(EAC_BT_FS, 72,
+		"eac_bt_fs", NULL, NULL, "gpio_72",
+		NULL, NULL, "etk_d10", NULL),
+	_OMAP2420_MUXENTRY(EAC_BT_SCLK, 71,
+		"eac_bt_sclk", NULL, NULL, "gpio_71",
+		NULL, NULL, "etk_d11", NULL),
+	_OMAP2420_MUXENTRY(GPIO_119, 119,
+		"gpio_119", NULL, "sti_din", "gpio_119",
+		NULL, "sys_boot0", "etk_d12", NULL),
+	_OMAP2420_MUXENTRY(GPIO_120, 120,
+		"gpio_120", NULL, "sti_dout", "gpio_120",
+		"cam_d9", "sys_boot1", "etk_d13", NULL),
+	_OMAP2420_MUXENTRY(GPIO_121, 121,
+		"gpio_121", NULL, NULL, "gpio_121",
+		"jtag_emu2", "sys_boot2", "etk_d14", NULL),
+	_OMAP2420_MUXENTRY(GPIO_122, 122,
+		"gpio_122", NULL, NULL, "gpio_122",
+		"jtag_emu3", "sys_boot3", "etk_d15", NULL),
+	_OMAP2420_MUXENTRY(GPIO_124, 124,
+		"gpio_124", NULL, NULL, "gpio_124",
+		NULL, "sys_boot5", NULL, NULL),
+	_OMAP2420_MUXENTRY(GPIO_125, 125,
+		"gpio_125", "sys_jtagsel1", "sys_jtagsel2", "gpio_125",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPIO_36, 36,
+		"gpio_36", NULL, NULL, "gpio_36",
+		NULL, "sys_boot4", NULL, NULL),
+	_OMAP2420_MUXENTRY(GPIO_62, 62,
+		"gpio_62", "uart1_rx", "usb1_dat", "gpio_62",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPIO_6, 6,
+		"gpio_6", "tv_detpulse", NULL, "gpio_6",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_A10, 3,
+		"gpmc_a10", NULL, "sys_ndmareq5", "gpio_3",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_A1, 12,
+		"gpmc_a1", "dss_data18", NULL, "gpio_12",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_A2, 11,
+		"gpmc_a2", "dss_data19", NULL, "gpio_11",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_A3, 10,
+		"gpmc_a3", "dss_data20", NULL, "gpio_10",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_A4, 9,
+		"gpmc_a4", "dss_data21", NULL, "gpio_9",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_A5, 8,
+		"gpmc_a5", "dss_data22", NULL, "gpio_8",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_A6, 7,
+		"gpmc_a6", "dss_data23", NULL, "gpio_7",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_A7, 6,
+		"gpmc_a7", NULL, "sys_ndmareq2", "gpio_6",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_A8, 5,
+		"gpmc_a8", NULL, "sys_ndmareq3", "gpio_5",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_A9, 4,
+		"gpmc_a9", NULL, "sys_ndmareq4", "gpio_4",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_CLK, 21,
+		"gpmc_clk", NULL, NULL, "gpio_21",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_D10, 18,
+		"gpmc_d10", "ssi2_rdy_rx", NULL, "gpio_18",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_D11, 17,
+		"gpmc_d11", "ssi2_flag_rx", NULL, "gpio_17",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_D12, 16,
+		"gpmc_d12", "ssi2_dat_rx", NULL, "gpio_16",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_D13, 15,
+		"gpmc_d13", "ssi2_rdy_tx", NULL, "gpio_15",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_D14, 14,
+		"gpmc_d14", "ssi2_flag_tx", NULL, "gpio_14",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_D15, 13,
+		"gpmc_d15", "ssi2_dat_tx", NULL, "gpio_13",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_D8, 20,
+		"gpmc_d8", NULL, NULL, "gpio_20",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_D9, 19,
+		"gpmc_d9", "ssi2_wake", NULL, "gpio_19",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_NBE0, 29,
+		"gpmc_nbe0", NULL, NULL, "gpio_29",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_NBE1, 30,
+		"gpmc_nbe1", NULL, NULL, "gpio_30",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_NCS1, 22,
+		"gpmc_ncs1", NULL, NULL, "gpio_22",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_NCS2, 23,
+		"gpmc_ncs2", NULL, NULL, "gpio_23",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_NCS3, 24,
+		"gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_NCS4, 25,
+		"gpmc_ncs4", NULL, NULL, "gpio_25",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_NCS5, 26,
+		"gpmc_ncs5", NULL, NULL, "gpio_26",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_NCS6, 27,
+		"gpmc_ncs6", NULL, NULL, "gpio_27",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_NCS7, 28,
+		"gpmc_ncs7", "gpmc_io_dir", "gpio_28", NULL,
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_NWP, 31,
+		"gpmc_nwp", NULL, NULL, "gpio_31",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_WAIT1, 33,
+		"gpmc_wait1", NULL, NULL, "gpio_33",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_WAIT2, 34,
+		"gpmc_wait2", NULL, NULL, "gpio_34",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(GPMC_WAIT3, 35,
+		"gpmc_wait3", NULL, NULL, "gpio_35",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(HDQ_SIO, 101,
+		"hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(I2C2_SCL, 99,
+		"i2c2_scl", NULL, "gpt9_pwm_evt", "gpio_99",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(I2C2_SDA, 100,
+		"i2c2_sda", NULL, "spi2_ncs1", "gpio_100",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(JTAG_EMU0, 127,
+		"jtag_emu0", NULL, NULL, "gpio_127",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(JTAG_EMU1, 126,
+		"jtag_emu1", NULL, NULL, "gpio_126",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MCBSP1_CLKR, 92,
+		"mcbsp1_clkr", "ssi2_dat_tx", "vlynq_tx1", "gpio_92",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MCBSP1_CLKX, 98,
+		"mcbsp1_clkx", "ssi2_wake", "vlynq_nla", "gpio_98",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MCBSP1_DR, 95,
+		"mcbsp1_dr", "ssi2_dat_rx", "vlynq_rx1", "gpio_95",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MCBSP1_DX, 94,
+		"mcbsp1_dx", "ssi2_rdy_tx", "vlynq_clk", "gpio_94",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MCBSP1_FSR, 93,
+		"mcbsp1_fsr", "ssi2_flag_tx", "vlynq_tx0", "gpio_93",
+		"spi2_ncs1", NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MCBSP1_FSX, 97,
+		"mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MCBSP2_CLKX, 12,
+		"mcbsp2_clkx", NULL, "dss_data23", "gpio_12",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MCBSP2_DR, 11,
+		"mcbsp2_dr", NULL, "dss_data22", "gpio_11",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MCBSP_CLKS, 96,
+		"mcbsp_clks", "ssi2_flag_rx", "vlynq_rx0", "gpio_96",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MMC_CLKI, 59,
+		"sdmmc_clki", "ms_clki", NULL, "gpio_59",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MMC_CLKO, 0,
+		"sdmmc_clko", "ms_clko", NULL, NULL,
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MMC_CMD_DIR, 8,
+		"sdmmc_cmd_dir", NULL, NULL, "gpio_8",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MMC_CMD, 0,
+		"sdmmc_cmd", "ms_bs", NULL, NULL,
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MMC_DAT_DIR0, 7,
+		"sdmmc_dat_dir0", "ms_dat0_dir", NULL, "gpio_7",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MMC_DAT0, 0,
+		"sdmmc_dat0", "ms_dat0", NULL, NULL,
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MMC_DAT_DIR1, 78,
+		"sdmmc_dat_dir1", "ms_datu_dir", "uart2_rts", "gpio_78",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MMC_DAT1, 75,
+		"sdmmc_dat1", "ms_dat1", NULL, "gpio_75",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MMC_DAT_DIR2, 79,
+		"sdmmc_dat_dir2", "ms_datu_dir", "uart2_tx", "gpio_79",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MMC_DAT2, 76,
+		"sdmmc_dat2", "ms_dat2", "uart2_cts", "gpio_76",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MMC_DAT_DIR3, 80,
+		"sdmmc_dat_dir3", "ms_datu_dir", "uart2_rx", "gpio_80",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(MMC_DAT3, 77,
+		"sdmmc_dat3", "ms_dat3", NULL, "gpio_77",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SDRC_A12, 2,
+		"sdrc_a12", NULL, NULL, "gpio_2",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SDRC_A13, 1,
+		"sdrc_a13", NULL, NULL, "gpio_1",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SDRC_A14, 0,
+		"sdrc_a14", NULL, NULL, "gpio_0",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SDRC_CKE1, 38,
+		"sdrc_cke1", NULL, NULL, "gpio_38",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SDRC_NCS1, 37,
+		"sdrc_ncs1", NULL, NULL, "gpio_37",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SPI1_CLK, 81,
+		"spi1_clk", NULL, NULL, "gpio_81",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SPI1_NCS0, 84,
+		"spi1_ncs0", NULL, NULL, "gpio_84",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SPI1_NCS1, 85,
+		"spi1_ncs1", NULL, NULL, "gpio_85",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SPI1_NCS2, 86,
+		"spi1_ncs2", NULL, NULL, "gpio_86",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SPI1_NCS3, 87,
+		"spi1_ncs3", NULL, NULL, "gpio_87",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SPI1_SIMO, 82,
+		"spi1_simo", NULL, NULL, "gpio_82",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SPI1_SOMI, 83,
+		"spi1_somi", NULL, NULL, "gpio_83",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SPI2_CLK, 88,
+		"spi2_clk", NULL, NULL, "gpio_88",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SPI2_NCS0, 91,
+		"spi2_ncs0", "gpt12_pwm_evt", NULL, "gpio_91",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SPI2_SIMO, 89,
+		"spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SPI2_SOMI, 90,
+		"spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SSI1_DAT_RX, 63,
+		"ssi1_dat_rx", "eac_md_sclk", NULL, "gpio_63",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SSI1_DAT_TX, 59,
+		"ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SSI1_FLAG_RX, 64,
+		"ssi1_flag_rx", "eac_md_din", NULL, "gpio_64",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SSI1_FLAG_TX, 25,
+		"ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_25",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SSI1_RDY_RX, 65,
+		"ssi1_rdy_rx", "eac_md_dout", NULL, "gpio_65",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SSI1_RDY_TX, 61,
+		"ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SSI1_WAKE, 66,
+		"ssi1_wake", "eac_md_fs", NULL, "gpio_66",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SYS_CLKOUT, 123,
+		"sys_clkout", NULL, NULL, "gpio_123",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SYS_CLKREQ, 52,
+		"sys_clkreq", NULL, NULL, "gpio_52",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(SYS_NIRQ, 60,
+		"sys_nirq", NULL, NULL, "gpio_60",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(UART1_CTS, 32,
+		"uart1_cts", NULL, "dss_data18", "gpio_32",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(UART1_RTS, 8,
+		"uart1_rts", NULL, "dss_data19", "gpio_8",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(UART1_RX, 10,
+		"uart1_rx", NULL, "dss_data21", "gpio_10",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(UART1_TX, 9,
+		"uart1_tx", NULL, "dss_data20", "gpio_9",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(UART2_CTS, 67,
+		"uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(UART2_RTS, 68,
+		"uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(UART2_RX, 70,
+		"uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(UART2_TX, 69,
+		"uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(UART3_CTS_RCTX, 102,
+		"uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(UART3_RTS_SD, 103,
+		"uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(UART3_RX_IRRX, 105,
+		"uart3_rx_irrx", NULL, NULL, "gpio_105",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(UART3_TX_IRTX, 104,
+		"uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(USB0_DAT, 112,
+		"usb0_dat", "uart3_rx_irrx", "uart2_rx", "gpio_112",
+		"uart2_tx", NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(USB0_PUEN, 106,
+		"usb0_puen", "mcbsp2_dx", NULL, "gpio_106",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(USB0_RCV, 109,
+		"usb0_rcv", "mcbsp2_fsx", NULL, "gpio_109",
+		"uart2_cts", NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(USB0_SE0, 111,
+		"usb0_se0", "uart3_tx_irtx", "uart2_tx", "gpio_111",
+		"uart2_rx", NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(USB0_TXEN, 110,
+		"usb0_txen", "uart3_cts_rctx", "uart2_cts", "gpio_110",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(USB0_VM, 108,
+		"usb0_vm", "mcbsp2_clkx", NULL, "gpio_108",
+		"uart2_rx", NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(USB0_VP, 107,
+		"usb0_vp", "mcbsp2_dr", NULL, "gpio_107",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(VLYNQ_CLK, 13,
+		"vlynq_clk", "usb2_se0", "sys_ndmareq0", "gpio_13",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(VLYNQ_NLA, 58,
+		"vlynq_nla", NULL, NULL, "gpio_58",
+		"cam_d6", NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(VLYNQ_RX0, 15,
+		"vlynq_rx0", "usb2_tllse0", NULL, "gpio_15",
+		"cam_d7", NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(VLYNQ_RX1, 14,
+		"vlynq_rx1", "usb2_rcv", "sys_ndmareq1", "gpio_14",
+		"cam_d8", NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(VLYNQ_TX0, 17,
+		"vlynq_tx0", "usb2_txen", NULL, "gpio_17",
+		NULL, NULL, NULL, NULL),
+	_OMAP2420_MUXENTRY(VLYNQ_TX1, 16,
+		"vlynq_tx1", "usb2_dat", "sys_clkout2", "gpio_16",
+		NULL, NULL, NULL, NULL),
+	{ .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for 447-pin POP package
+ */
+#ifdef CONFIG_DEBUG_FS
+struct omap_ball __initdata omap2420_pop_ball[] = {
+	_OMAP2420_BALLENTRY(CAM_D0, "y4", NULL),
+	_OMAP2420_BALLENTRY(CAM_D1, "y3", NULL),
+	_OMAP2420_BALLENTRY(CAM_D2, "u7", NULL),
+	_OMAP2420_BALLENTRY(CAM_D3, "ab3", NULL),
+	_OMAP2420_BALLENTRY(CAM_D4, "v2", NULL),
+	_OMAP2420_BALLENTRY(CAM_D5, "ad3", NULL),
+	_OMAP2420_BALLENTRY(CAM_D6, "aa4", NULL),
+	_OMAP2420_BALLENTRY(CAM_D7, "ab4", NULL),
+	_OMAP2420_BALLENTRY(CAM_D8, "ac6", NULL),
+	_OMAP2420_BALLENTRY(CAM_D9, "ac7", NULL),
+	_OMAP2420_BALLENTRY(CAM_HS, "v4", NULL),
+	_OMAP2420_BALLENTRY(CAM_LCLK, "ad6", NULL),
+	_OMAP2420_BALLENTRY(CAM_VS, "p7", NULL),
+	_OMAP2420_BALLENTRY(CAM_XCLK, "w4", NULL),
+	_OMAP2420_BALLENTRY(DSS_ACBIAS, "ae8", NULL),
+	_OMAP2420_BALLENTRY(DSS_DATA10, "ac12", NULL),
+	_OMAP2420_BALLENTRY(DSS_DATA11, "ae11", NULL),
+	_OMAP2420_BALLENTRY(DSS_DATA12, "ae13", NULL),
+	_OMAP2420_BALLENTRY(DSS_DATA13, "ad13", NULL),
+	_OMAP2420_BALLENTRY(DSS_DATA14, "ac13", NULL),
+	_OMAP2420_BALLENTRY(DSS_DATA15, "y12", NULL),
+	_OMAP2420_BALLENTRY(DSS_DATA16, "ad14", NULL),
+	_OMAP2420_BALLENTRY(DSS_DATA17, "y13", NULL),
+	_OMAP2420_BALLENTRY(DSS_DATA8, "ad11", NULL),
+	_OMAP2420_BALLENTRY(DSS_DATA9, "ad12", NULL),
+	_OMAP2420_BALLENTRY(EAC_AC_DIN, "ad19", NULL),
+	_OMAP2420_BALLENTRY(EAC_AC_DOUT, "af22", NULL),
+	_OMAP2420_BALLENTRY(EAC_AC_FS, "ad16", NULL),
+	_OMAP2420_BALLENTRY(EAC_AC_MCLK, "y17", NULL),
+	_OMAP2420_BALLENTRY(EAC_AC_RST, "ae22", NULL),
+	_OMAP2420_BALLENTRY(EAC_AC_SCLK, "ac18", NULL),
+	_OMAP2420_BALLENTRY(EAC_BT_DIN, "u8", NULL),
+	_OMAP2420_BALLENTRY(EAC_BT_DOUT, "ad5", NULL),
+	_OMAP2420_BALLENTRY(EAC_BT_FS, "w7", NULL),
+	_OMAP2420_BALLENTRY(EAC_BT_SCLK, "ad4", NULL),
+	_OMAP2420_BALLENTRY(GPIO_119, "af6", NULL),
+	_OMAP2420_BALLENTRY(GPIO_120, "af4", NULL),
+	_OMAP2420_BALLENTRY(GPIO_121, "ae6", NULL),
+	_OMAP2420_BALLENTRY(GPIO_122, "w3", NULL),
+	_OMAP2420_BALLENTRY(GPIO_124, "y19", NULL),
+	_OMAP2420_BALLENTRY(GPIO_125, "ae24", NULL),
+	_OMAP2420_BALLENTRY(GPIO_36, "y18", NULL),
+	_OMAP2420_BALLENTRY(GPIO_6, "d6", NULL),
+	_OMAP2420_BALLENTRY(GPIO_62, "ad18", NULL),
+	_OMAP2420_BALLENTRY(GPMC_A1, "m8", NULL),
+	_OMAP2420_BALLENTRY(GPMC_A10, "d5", NULL),
+	_OMAP2420_BALLENTRY(GPMC_A2, "w9", NULL),
+	_OMAP2420_BALLENTRY(GPMC_A3, "af10", NULL),
+	_OMAP2420_BALLENTRY(GPMC_A4, "w8", NULL),
+	_OMAP2420_BALLENTRY(GPMC_A5, "ae16", NULL),
+	_OMAP2420_BALLENTRY(GPMC_A6, "af9", NULL),
+	_OMAP2420_BALLENTRY(GPMC_A7, "e4", NULL),
+	_OMAP2420_BALLENTRY(GPMC_A8, "j7", NULL),
+	_OMAP2420_BALLENTRY(GPMC_A9, "ae18", NULL),
+	_OMAP2420_BALLENTRY(GPMC_CLK, "p1", "l1"),
+	_OMAP2420_BALLENTRY(GPMC_D10, "t1", "n1"),
+	_OMAP2420_BALLENTRY(GPMC_D11, "u2", "p2"),
+	_OMAP2420_BALLENTRY(GPMC_D12, "u1", "p1"),
+	_OMAP2420_BALLENTRY(GPMC_D13, "p2", "m1"),
+	_OMAP2420_BALLENTRY(GPMC_D14, "h2", "j2"),
+	_OMAP2420_BALLENTRY(GPMC_D15, "h1", "k2"),
+	_OMAP2420_BALLENTRY(GPMC_D8, "v1", "r1"),
+	_OMAP2420_BALLENTRY(GPMC_D9, "y1", "t1"),
+	_OMAP2420_BALLENTRY(GPMC_NBE0, "af12", "aa10"),
+	_OMAP2420_BALLENTRY(GPMC_NBE1, "u3", NULL),
+	_OMAP2420_BALLENTRY(GPMC_NCS1, "af14", "w1"),
+	_OMAP2420_BALLENTRY(GPMC_NCS2, "g4", NULL),
+	_OMAP2420_BALLENTRY(GPMC_NCS3, "t8", NULL),
+	_OMAP2420_BALLENTRY(GPMC_NCS4, "h8", NULL),
+	_OMAP2420_BALLENTRY(GPMC_NCS5, "k3", NULL),
+	_OMAP2420_BALLENTRY(GPMC_NCS6, "m7", NULL),
+	_OMAP2420_BALLENTRY(GPMC_NCS7, "p3", NULL),
+	_OMAP2420_BALLENTRY(GPMC_NWP, "ae15", "y5"),
+	_OMAP2420_BALLENTRY(GPMC_WAIT1, "ae20", "y8"),
+	_OMAP2420_BALLENTRY(GPMC_WAIT2, "n2", NULL),
+	_OMAP2420_BALLENTRY(GPMC_WAIT3, "t4", NULL),
+	_OMAP2420_BALLENTRY(HDQ_SIO, "t23", NULL),
+	_OMAP2420_BALLENTRY(I2C2_SCL, "l2", NULL),
+	_OMAP2420_BALLENTRY(I2C2_SDA, "k19", NULL),
+	_OMAP2420_BALLENTRY(JTAG_EMU0, "n24", NULL),
+	_OMAP2420_BALLENTRY(JTAG_EMU1, "ac22", NULL),
+	_OMAP2420_BALLENTRY(MCBSP1_CLKR, "y24", NULL),
+	_OMAP2420_BALLENTRY(MCBSP1_CLKX, "t19", NULL),
+	_OMAP2420_BALLENTRY(MCBSP1_DR, "u23", NULL),
+	_OMAP2420_BALLENTRY(MCBSP1_DX, "r24", NULL),
+	_OMAP2420_BALLENTRY(MCBSP1_FSR, "r20", NULL),
+	_OMAP2420_BALLENTRY(MCBSP1_FSX, "r23", NULL),
+	_OMAP2420_BALLENTRY(MCBSP2_CLKX, "t24", NULL),
+	_OMAP2420_BALLENTRY(MCBSP2_DR, "p20", NULL),
+	_OMAP2420_BALLENTRY(MCBSP_CLKS, "p23", NULL),
+	_OMAP2420_BALLENTRY(MMC_CLKI, "c23", NULL),
+	_OMAP2420_BALLENTRY(MMC_CLKO, "h23", NULL),
+	_OMAP2420_BALLENTRY(MMC_CMD, "j23", NULL),
+	_OMAP2420_BALLENTRY(MMC_CMD_DIR, "j24", NULL),
+	_OMAP2420_BALLENTRY(MMC_DAT0, "h17", NULL),
+	_OMAP2420_BALLENTRY(MMC_DAT_DIR0, "f23", NULL),
+	_OMAP2420_BALLENTRY(MMC_DAT1, "g19", NULL),
+	_OMAP2420_BALLENTRY(MMC_DAT_DIR1, "d23", NULL),
+	_OMAP2420_BALLENTRY(MMC_DAT2, "h20", NULL),
+	_OMAP2420_BALLENTRY(MMC_DAT_DIR2, "g23", NULL),
+	_OMAP2420_BALLENTRY(MMC_DAT3, "d24", NULL),
+	_OMAP2420_BALLENTRY(MMC_DAT_DIR3, "e23", NULL),
+	_OMAP2420_BALLENTRY(SDRC_A12, "w26", "r21"),
+	_OMAP2420_BALLENTRY(SDRC_A13, "w25", "aa15"),
+	_OMAP2420_BALLENTRY(SDRC_A14, "aa26", "y12"),
+	_OMAP2420_BALLENTRY(SDRC_CKE1, "ae25", "y13"),
+	_OMAP2420_BALLENTRY(SDRC_NCS1, "y25", "t20"),
+	_OMAP2420_BALLENTRY(SPI1_CLK, "y23", NULL),
+	_OMAP2420_BALLENTRY(SPI1_NCS0, "w24", NULL),
+	_OMAP2420_BALLENTRY(SPI1_NCS1, "w23", NULL),
+	_OMAP2420_BALLENTRY(SPI1_NCS2, "v23", NULL),
+	_OMAP2420_BALLENTRY(SPI1_NCS3, "u20", NULL),
+	_OMAP2420_BALLENTRY(SPI1_SIMO, "h10", NULL),
+	_OMAP2420_BALLENTRY(SPI1_SOMI, "v19", NULL),
+	_OMAP2420_BALLENTRY(SPI2_CLK, "v24", NULL),
+	_OMAP2420_BALLENTRY(SPI2_NCS0, "aa24", NULL),
+	_OMAP2420_BALLENTRY(SPI2_SIMO, "u24", NULL),
+	_OMAP2420_BALLENTRY(SPI2_SOMI, "v25", NULL),
+	_OMAP2420_BALLENTRY(SSI1_DAT_RX, "w15", NULL),
+	_OMAP2420_BALLENTRY(SSI1_DAT_TX, "w13", NULL),
+	_OMAP2420_BALLENTRY(SSI1_FLAG_RX, "af11", NULL),
+	_OMAP2420_BALLENTRY(SSI1_FLAG_TX, "ac15", NULL),
+	_OMAP2420_BALLENTRY(SSI1_RDY_RX, "ac16", NULL),
+	_OMAP2420_BALLENTRY(SSI1_RDY_TX, "af15", NULL),
+	_OMAP2420_BALLENTRY(SSI1_WAKE, "ad15", NULL),
+	_OMAP2420_BALLENTRY(SYS_CLKOUT, "ae19", NULL),
+	_OMAP2420_BALLENTRY(SYS_CLKREQ, "ad20", NULL),
+	_OMAP2420_BALLENTRY(SYS_NIRQ, "y20", NULL),
+	_OMAP2420_BALLENTRY(UART1_CTS, "g20", NULL),
+	_OMAP2420_BALLENTRY(UART1_RTS, "k20", NULL),
+	_OMAP2420_BALLENTRY(UART1_RX, "t20", NULL),
+	_OMAP2420_BALLENTRY(UART1_TX, "h12", NULL),
+	_OMAP2420_BALLENTRY(UART2_CTS, "ac24", NULL),
+	_OMAP2420_BALLENTRY(UART2_RTS, "w20", NULL),
+	_OMAP2420_BALLENTRY(UART2_RX, "ad24", NULL),
+	_OMAP2420_BALLENTRY(UART2_TX, "ab24", NULL),
+	_OMAP2420_BALLENTRY(UART3_CTS_RCTX, "k24", NULL),
+	_OMAP2420_BALLENTRY(UART3_RTS_SD, "m20", NULL),
+	_OMAP2420_BALLENTRY(UART3_RX_IRRX, "h24", NULL),
+	_OMAP2420_BALLENTRY(UART3_TX_IRTX, "g24", NULL),
+	_OMAP2420_BALLENTRY(USB0_DAT, "j25", NULL),
+	_OMAP2420_BALLENTRY(USB0_PUEN, "l23", NULL),
+	_OMAP2420_BALLENTRY(USB0_RCV, "k23", NULL),
+	_OMAP2420_BALLENTRY(USB0_SE0, "l24", NULL),
+	_OMAP2420_BALLENTRY(USB0_TXEN, "m24", NULL),
+	_OMAP2420_BALLENTRY(USB0_VM, "n23", NULL),
+	_OMAP2420_BALLENTRY(USB0_VP, "m23", NULL),
+	_OMAP2420_BALLENTRY(VLYNQ_CLK, "w12", NULL),
+	_OMAP2420_BALLENTRY(VLYNQ_NLA, "ae10", NULL),
+	_OMAP2420_BALLENTRY(VLYNQ_RX0, "ad7", NULL),
+	_OMAP2420_BALLENTRY(VLYNQ_RX1, "w10", NULL),
+	_OMAP2420_BALLENTRY(VLYNQ_TX0, "y15", NULL),
+	_OMAP2420_BALLENTRY(VLYNQ_TX1, "w14", NULL),
+	{ .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap2420_pop_ball	 NULL
+#endif
+
+int __init omap2420_mux_init(struct omap_board_mux *board_subset, int flags)
+{
+	struct omap_ball *package_balls = NULL;
+
+	switch (flags & OMAP_PACKAGE_MASK) {
+	case OMAP_PACKAGE_ZAC:
+		package_balls = omap2420_pop_ball;
+		break;
+	case OMAP_PACKAGE_ZAF:
+		/* REVISIT: Please add data */
+	default:
+		pr_warning("mux: No ball data available for omap2420 package\n");
+	}
+
+	return omap_mux_init(OMAP2420_CONTROL_PADCONF_MUX_PBASE,
+			     OMAP2420_CONTROL_PADCONF_MUX_SIZE,
+				omap2420_muxmodes, NULL, board_subset,
+				package_balls);
+}
diff --git a/arch/arm/mach-omap2/mux2420.h b/arch/arm/mach-omap2/mux2420.h
new file mode 100644
index 0000000..0f555aa
--- /dev/null
+++ b/arch/arm/mach-omap2/mux2420.h
@@ -0,0 +1,282 @@
+/*
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define OMAP2420_CONTROL_PADCONF_MUX_PBASE			0x48000030LU
+
+#define OMAP2420_MUX(mode0, mux_value)					\
+{									\
+	.reg_offset	= (OMAP2420_CONTROL_PADCONF_##mode0##_OFFSET),	\
+	.value		= (mux_value),					\
+}
+
+/*
+ * OMAP2420 CONTROL_PADCONF* register offsets for pin-muxing
+ *
+ * Extracted from the TRM.  Add 0x48000030 to these values to get the
+ * absolute addresses.  The name in the macro is the mode-0 name of
+ * the pin.  NOTE: These registers are 8-bits wide.
+ */
+#define OMAP2420_CONTROL_PADCONF_SDRC_A14_OFFSET			0x000
+#define OMAP2420_CONTROL_PADCONF_SDRC_A13_OFFSET			0x001
+#define OMAP2420_CONTROL_PADCONF_SDRC_A12_OFFSET			0x002
+#define OMAP2420_CONTROL_PADCONF_SDRC_BA1_OFFSET			0x003
+#define OMAP2420_CONTROL_PADCONF_SDRC_BA0_OFFSET			0x004
+#define OMAP2420_CONTROL_PADCONF_SDRC_A11_OFFSET			0x005
+#define OMAP2420_CONTROL_PADCONF_SDRC_A10_OFFSET			0x006
+#define OMAP2420_CONTROL_PADCONF_SDRC_A9_OFFSET				0x007
+#define OMAP2420_CONTROL_PADCONF_SDRC_A8_OFFSET				0x008
+#define OMAP2420_CONTROL_PADCONF_SDRC_A7_OFFSET				0x009
+#define OMAP2420_CONTROL_PADCONF_SDRC_A6_OFFSET				0x00a
+#define OMAP2420_CONTROL_PADCONF_SDRC_A5_OFFSET				0x00b
+#define OMAP2420_CONTROL_PADCONF_SDRC_A4_OFFSET				0x00c
+#define OMAP2420_CONTROL_PADCONF_SDRC_A3_OFFSET				0x00d
+#define OMAP2420_CONTROL_PADCONF_SDRC_A2_OFFSET				0x00e
+#define OMAP2420_CONTROL_PADCONF_SDRC_A1_OFFSET				0x00f
+#define OMAP2420_CONTROL_PADCONF_SDRC_A0_OFFSET				0x010
+#define OMAP2420_CONTROL_PADCONF_SDRC_D31_OFFSET			0x021
+#define OMAP2420_CONTROL_PADCONF_SDRC_D30_OFFSET			0x022
+#define OMAP2420_CONTROL_PADCONF_SDRC_D29_OFFSET			0x023
+#define OMAP2420_CONTROL_PADCONF_SDRC_D28_OFFSET			0x024
+#define OMAP2420_CONTROL_PADCONF_SDRC_D27_OFFSET			0x025
+#define OMAP2420_CONTROL_PADCONF_SDRC_D26_OFFSET			0x026
+#define OMAP2420_CONTROL_PADCONF_SDRC_D25_OFFSET			0x027
+#define OMAP2420_CONTROL_PADCONF_SDRC_D24_OFFSET			0x028
+#define OMAP2420_CONTROL_PADCONF_SDRC_D23_OFFSET			0x029
+#define OMAP2420_CONTROL_PADCONF_SDRC_D22_OFFSET			0x02a
+#define OMAP2420_CONTROL_PADCONF_SDRC_D21_OFFSET			0x02b
+#define OMAP2420_CONTROL_PADCONF_SDRC_D20_OFFSET			0x02c
+#define OMAP2420_CONTROL_PADCONF_SDRC_D19_OFFSET			0x02d
+#define OMAP2420_CONTROL_PADCONF_SDRC_D18_OFFSET			0x02e
+#define OMAP2420_CONTROL_PADCONF_SDRC_D17_OFFSET			0x02f
+#define OMAP2420_CONTROL_PADCONF_SDRC_D16_OFFSET			0x030
+#define OMAP2420_CONTROL_PADCONF_SDRC_D15_OFFSET			0x031
+#define OMAP2420_CONTROL_PADCONF_SDRC_D14_OFFSET			0x032
+#define OMAP2420_CONTROL_PADCONF_SDRC_D13_OFFSET			0x033
+#define OMAP2420_CONTROL_PADCONF_SDRC_D12_OFFSET			0x034
+#define OMAP2420_CONTROL_PADCONF_SDRC_D11_OFFSET			0x035
+#define OMAP2420_CONTROL_PADCONF_SDRC_D10_OFFSET			0x036
+#define OMAP2420_CONTROL_PADCONF_SDRC_D9_OFFSET				0x037
+#define OMAP2420_CONTROL_PADCONF_SDRC_D8_OFFSET				0x038
+#define OMAP2420_CONTROL_PADCONF_SDRC_D7_OFFSET				0x039
+#define OMAP2420_CONTROL_PADCONF_SDRC_D6_OFFSET				0x03a
+#define OMAP2420_CONTROL_PADCONF_SDRC_D5_OFFSET				0x03b
+#define OMAP2420_CONTROL_PADCONF_SDRC_D4_OFFSET				0x03c
+#define OMAP2420_CONTROL_PADCONF_SDRC_D3_OFFSET				0x03d
+#define OMAP2420_CONTROL_PADCONF_SDRC_D2_OFFSET				0x03e
+#define OMAP2420_CONTROL_PADCONF_SDRC_D1_OFFSET				0x03f
+#define OMAP2420_CONTROL_PADCONF_SDRC_D0_OFFSET				0x040
+#define OMAP2420_CONTROL_PADCONF_GPMC_A10_OFFSET			0x041
+#define OMAP2420_CONTROL_PADCONF_GPMC_A9_OFFSET				0x042
+#define OMAP2420_CONTROL_PADCONF_GPMC_A8_OFFSET				0x043
+#define OMAP2420_CONTROL_PADCONF_GPMC_A7_OFFSET				0x044
+#define OMAP2420_CONTROL_PADCONF_GPMC_A6_OFFSET				0x045
+#define OMAP2420_CONTROL_PADCONF_GPMC_A5_OFFSET				0x046
+#define OMAP2420_CONTROL_PADCONF_GPMC_A4_OFFSET				0x047
+#define OMAP2420_CONTROL_PADCONF_GPMC_A3_OFFSET				0x048
+#define OMAP2420_CONTROL_PADCONF_GPMC_A2_OFFSET				0x049
+#define OMAP2420_CONTROL_PADCONF_GPMC_A1_OFFSET				0x04a
+#define OMAP2420_CONTROL_PADCONF_GPMC_D15_OFFSET			0x04b
+#define OMAP2420_CONTROL_PADCONF_GPMC_D14_OFFSET			0x04c
+#define OMAP2420_CONTROL_PADCONF_GPMC_D13_OFFSET			0x04d
+#define OMAP2420_CONTROL_PADCONF_GPMC_D12_OFFSET			0x04e
+#define OMAP2420_CONTROL_PADCONF_GPMC_D11_OFFSET			0x04f
+#define OMAP2420_CONTROL_PADCONF_GPMC_D10_OFFSET			0x050
+#define OMAP2420_CONTROL_PADCONF_GPMC_D9_OFFSET				0x051
+#define OMAP2420_CONTROL_PADCONF_GPMC_D8_OFFSET				0x052
+#define OMAP2420_CONTROL_PADCONF_GPMC_D7_OFFSET				0x053
+#define OMAP2420_CONTROL_PADCONF_GPMC_D6_OFFSET				0x054
+#define OMAP2420_CONTROL_PADCONF_GPMC_D5_OFFSET				0x055
+#define OMAP2420_CONTROL_PADCONF_GPMC_D4_OFFSET				0x056
+#define OMAP2420_CONTROL_PADCONF_GPMC_D3_OFFSET				0x057
+#define OMAP2420_CONTROL_PADCONF_GPMC_D2_OFFSET				0x058
+#define OMAP2420_CONTROL_PADCONF_GPMC_D1_OFFSET				0x059
+#define OMAP2420_CONTROL_PADCONF_GPMC_D0_OFFSET				0x05a
+#define OMAP2420_CONTROL_PADCONF_GPMC_CLK_OFFSET			0x05b
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS0_OFFSET			0x05c
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS1_OFFSET			0x05d
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS2_OFFSET			0x05e
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS3_OFFSET			0x05f
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS4_OFFSET			0x060
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS5_OFFSET			0x061
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS6_OFFSET			0x062
+#define OMAP2420_CONTROL_PADCONF_GPMC_NCS7_OFFSET			0x063
+#define OMAP2420_CONTROL_PADCONF_GPMC_NALE_ALE_OFFSET			0x064
+#define OMAP2420_CONTROL_PADCONF_GPMC_NOE_OFFSET			0x065
+#define OMAP2420_CONTROL_PADCONF_GPMC_NWE_OFFSET			0x066
+#define OMAP2420_CONTROL_PADCONF_GPMC_NBE0_OFFSET			0x067
+#define OMAP2420_CONTROL_PADCONF_GPMC_NBE1_OFFSET			0x068
+#define OMAP2420_CONTROL_PADCONF_GPMC_NWP_OFFSET			0x069
+#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT0_OFFSET			0x06a
+#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT1_OFFSET			0x06b
+#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT2_OFFSET			0x06c
+#define OMAP2420_CONTROL_PADCONF_GPMC_WAIT3_OFFSET			0x06d
+#define OMAP2420_CONTROL_PADCONF_SDRC_CLK_OFFSET			0x06e
+#define OMAP2420_CONTROL_PADCONF_SDRC_NCLK_OFFSET			0x06f
+#define OMAP2420_CONTROL_PADCONF_SDRC_NCS0_OFFSET			0x070
+#define OMAP2420_CONTROL_PADCONF_SDRC_NCS1_OFFSET			0x071
+#define OMAP2420_CONTROL_PADCONF_SDRC_CKE0_OFFSET			0x072
+#define OMAP2420_CONTROL_PADCONF_SDRC_CKE1_OFFSET			0x073
+#define OMAP2420_CONTROL_PADCONF_SDRC_NRAS_OFFSET			0x074
+#define OMAP2420_CONTROL_PADCONF_SDRC_NCAS_OFFSET			0x075
+#define OMAP2420_CONTROL_PADCONF_SDRC_NWE_OFFSET			0x076
+#define OMAP2420_CONTROL_PADCONF_SDRC_DM0_OFFSET			0x077
+#define OMAP2420_CONTROL_PADCONF_SDRC_DM1_OFFSET			0x078
+#define OMAP2420_CONTROL_PADCONF_SDRC_DM2_OFFSET			0x079
+#define OMAP2420_CONTROL_PADCONF_SDRC_DM3_OFFSET			0x07a
+#define OMAP2420_CONTROL_PADCONF_SDRC_DQS0_OFFSET			0x07f
+#define OMAP2420_CONTROL_PADCONF_SDRC_DQS1_OFFSET			0x080
+#define OMAP2420_CONTROL_PADCONF_SDRC_DQS2_OFFSET			0x081
+#define OMAP2420_CONTROL_PADCONF_SDRC_DQS3_OFFSET			0x082
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA0_OFFSET			0x083
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA1_OFFSET			0x084
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA2_OFFSET			0x085
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA3_OFFSET			0x086
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA4_OFFSET			0x087
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA5_OFFSET			0x088
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA6_OFFSET			0x089
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA7_OFFSET			0x08a
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA8_OFFSET			0x08b
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA9_OFFSET			0x08c
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA10_OFFSET			0x08d
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA11_OFFSET			0x08e
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA12_OFFSET			0x08f
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA13_OFFSET			0x090
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA14_OFFSET			0x091
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA15_OFFSET			0x092
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA16_OFFSET			0x093
+#define OMAP2420_CONTROL_PADCONF_DSS_DATA17_OFFSET			0x094
+#define OMAP2420_CONTROL_PADCONF_UART1_CTS_OFFSET			0x095
+#define OMAP2420_CONTROL_PADCONF_UART1_RTS_OFFSET			0x096
+#define OMAP2420_CONTROL_PADCONF_UART1_TX_OFFSET			0x097
+#define OMAP2420_CONTROL_PADCONF_UART1_RX_OFFSET			0x098
+#define OMAP2420_CONTROL_PADCONF_MCBSP2_DR_OFFSET			0x099
+#define OMAP2420_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET			0x09a
+#define OMAP2420_CONTROL_PADCONF_DSS_PCL_OFFSET				0x09b
+#define OMAP2420_CONTROL_PADCONF_DSS_VSYNC_OFFSET			0x09c
+#define OMAP2420_CONTROL_PADCONF_DSS_HSYNC_OFFSET			0x09d
+#define OMAP2420_CONTROL_PADCONF_DSS_ACBIAS_OFFSET			0x09e
+#define OMAP2420_CONTROL_PADCONF_CAM_D9_OFFSET				0x09f
+#define OMAP2420_CONTROL_PADCONF_CAM_D8_OFFSET				0x0a0
+#define OMAP2420_CONTROL_PADCONF_CAM_D7_OFFSET				0x0a1
+#define OMAP2420_CONTROL_PADCONF_CAM_D6_OFFSET				0x0a2
+#define OMAP2420_CONTROL_PADCONF_CAM_D5_OFFSET				0x0a3
+#define OMAP2420_CONTROL_PADCONF_CAM_D4_OFFSET				0x0a4
+#define OMAP2420_CONTROL_PADCONF_CAM_D3_OFFSET				0x0a5
+#define OMAP2420_CONTROL_PADCONF_CAM_D2_OFFSET				0x0a6
+#define OMAP2420_CONTROL_PADCONF_CAM_D1_OFFSET				0x0a7
+#define OMAP2420_CONTROL_PADCONF_CAM_D0_OFFSET				0x0a8
+#define OMAP2420_CONTROL_PADCONF_CAM_HS_OFFSET				0x0a9
+#define OMAP2420_CONTROL_PADCONF_CAM_VS_OFFSET				0x0aa
+#define OMAP2420_CONTROL_PADCONF_CAM_LCLK_OFFSET			0x0ab
+#define OMAP2420_CONTROL_PADCONF_CAM_XCLK_OFFSET			0x0ac
+#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET			0x0ad
+#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET			0x0ae
+#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET			0x0af
+#define OMAP2420_CONTROL_PADCONF_GPIO_62_OFFSET				0x0b0
+#define OMAP2420_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET			0x0b1
+#define OMAP2420_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET			0x0b2
+#define OMAP2420_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET			0x0b3
+#define OMAP2420_CONTROL_PADCONF_SSI1_WAKE_OFFSET			0x0b4
+#define OMAP2420_CONTROL_PADCONF_VLYNQ_CLK_OFFSET			0x0b5
+#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX1_OFFSET			0x0b6
+#define OMAP2420_CONTROL_PADCONF_VLYNQ_RX0_OFFSET			0x0b7
+#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX1_OFFSET			0x0b8
+#define OMAP2420_CONTROL_PADCONF_VLYNQ_TX0_OFFSET			0x0b9
+#define OMAP2420_CONTROL_PADCONF_VLYNQ_NLA_OFFSET			0x0ba
+#define OMAP2420_CONTROL_PADCONF_UART2_CTS_OFFSET			0x0bb
+#define OMAP2420_CONTROL_PADCONF_UART2_RTS_OFFSET			0x0bc
+#define OMAP2420_CONTROL_PADCONF_UART2_TX_OFFSET			0x0bd
+#define OMAP2420_CONTROL_PADCONF_UART2_RX_OFFSET			0x0be
+#define OMAP2420_CONTROL_PADCONF_EAC_BT_SCLK_OFFSET			0x0bf
+#define OMAP2420_CONTROL_PADCONF_EAC_BT_FS_OFFSET			0x0c0
+#define OMAP2420_CONTROL_PADCONF_EAC_BT_DIN_OFFSET			0x0c1
+#define OMAP2420_CONTROL_PADCONF_EAC_BT_DOUT_OFFSET			0x0c2
+#define OMAP2420_CONTROL_PADCONF_MMC_CLKO_OFFSET			0x0c3
+#define OMAP2420_CONTROL_PADCONF_MMC_CMD_OFFSET				0x0c4
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT0_OFFSET			0x0c5
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT1_OFFSET			0x0c6
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT2_OFFSET			0x0c7
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT3_OFFSET			0x0c8
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR0_OFFSET			0x0c9
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR1_OFFSET			0x0ca
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR2_OFFSET			0x0cb
+#define OMAP2420_CONTROL_PADCONF_MMC_DAT_DIR3_OFFSET			0x0cc
+#define OMAP2420_CONTROL_PADCONF_MMC_CMD_DIR_OFFSET			0x0cd
+#define OMAP2420_CONTROL_PADCONF_MMC_CLKI_OFFSET			0x0ce
+#define OMAP2420_CONTROL_PADCONF_SPI1_CLK_OFFSET			0x0cf
+#define OMAP2420_CONTROL_PADCONF_SPI1_SIMO_OFFSET			0x0d0
+#define OMAP2420_CONTROL_PADCONF_SPI1_SOMI_OFFSET			0x0d1
+#define OMAP2420_CONTROL_PADCONF_SPI1_NCS0_OFFSET			0x0d2
+#define OMAP2420_CONTROL_PADCONF_SPI1_NCS1_OFFSET			0x0d3
+#define OMAP2420_CONTROL_PADCONF_SPI1_NCS2_OFFSET			0x0d4
+#define OMAP2420_CONTROL_PADCONF_SPI1_NCS3_OFFSET			0x0d5
+#define OMAP2420_CONTROL_PADCONF_SPI2_CLK_OFFSET			0x0d6
+#define OMAP2420_CONTROL_PADCONF_SPI2_SIMO_OFFSET			0x0d7
+#define OMAP2420_CONTROL_PADCONF_SPI2_SOMI_OFFSET			0x0d8
+#define OMAP2420_CONTROL_PADCONF_SPI2_NCS0_OFFSET			0x0d9
+#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET			0x0da
+#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSR_OFFSET			0x0db
+#define OMAP2420_CONTROL_PADCONF_MCBSP1_DX_OFFSET			0x0dc
+#define OMAP2420_CONTROL_PADCONF_MCBSP1_DR_OFFSET			0x0dd
+#define OMAP2420_CONTROL_PADCONF_MCBSP_CLKS_OFFSET			0x0de
+#define OMAP2420_CONTROL_PADCONF_MCBSP1_FSX_OFFSET			0x0df
+#define OMAP2420_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET			0x0e0
+#define OMAP2420_CONTROL_PADCONF_I2C1_SCL_OFFSET			0x0e1
+#define OMAP2420_CONTROL_PADCONF_I2C1_SDA_OFFSET			0x0e2
+#define OMAP2420_CONTROL_PADCONF_I2C2_SCL_OFFSET			0x0e3
+#define OMAP2420_CONTROL_PADCONF_I2C2_SDA_OFFSET			0x0e4
+#define OMAP2420_CONTROL_PADCONF_HDQ_SIO_OFFSET				0x0e5
+#define OMAP2420_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET			0x0e6
+#define OMAP2420_CONTROL_PADCONF_UART3_RTS_SD_OFFSET			0x0e7
+#define OMAP2420_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET			0x0e8
+#define OMAP2420_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET			0x0e9
+#define OMAP2420_CONTROL_PADCONF_TV_CVBS_OFFSET				0x0ea
+#define OMAP2420_CONTROL_PADCONF_TV_VREF_OFFSET				0x0eb
+#define OMAP2420_CONTROL_PADCONF_TV_RREF_OFFSET				0x0ec
+#define OMAP2420_CONTROL_PADCONF_USB0_PUEN_OFFSET			0x0ed
+#define OMAP2420_CONTROL_PADCONF_USB0_VP_OFFSET				0x0ee
+#define OMAP2420_CONTROL_PADCONF_USB0_VM_OFFSET				0x0ef
+#define OMAP2420_CONTROL_PADCONF_USB0_RCV_OFFSET			0x0f0
+#define OMAP2420_CONTROL_PADCONF_USB0_TXEN_OFFSET			0x0f1
+#define OMAP2420_CONTROL_PADCONF_USB0_SE0_OFFSET			0x0f2
+#define OMAP2420_CONTROL_PADCONF_USB0_DAT_OFFSET			0x0f3
+#define OMAP2420_CONTROL_PADCONF_EAC_AC_SCLK_OFFSET			0x0f4
+#define OMAP2420_CONTROL_PADCONF_EAC_AC_FS_OFFSET			0x0f5
+#define OMAP2420_CONTROL_PADCONF_EAC_AC_DIN_OFFSET			0x0f6
+#define OMAP2420_CONTROL_PADCONF_EAC_AC_DOUT_OFFSET			0x0f7
+#define OMAP2420_CONTROL_PADCONF_EAC_AC_MCLK_OFFSET			0x0f8
+#define OMAP2420_CONTROL_PADCONF_EAC_AC_RST_OFFSET			0x0f9
+#define OMAP2420_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET			0x0fa
+#define OMAP2420_CONTROL_PADCONF_SYS_NRESWARM_OFFSET			0x0fb
+#define OMAP2420_CONTROL_PADCONF_SYS_NIRQ_OFFSET			0x0fc
+#define OMAP2420_CONTROL_PADCONF_SYS_NV_OFFSET				0x0fd
+#define OMAP2420_CONTROL_PADCONF_GPIO_119_OFFSET			0x0fe
+#define OMAP2420_CONTROL_PADCONF_GPIO_120_OFFSET			0x0ff
+#define OMAP2420_CONTROL_PADCONF_GPIO_121_OFFSET			0x100
+#define OMAP2420_CONTROL_PADCONF_GPIO_122_OFFSET			0x101
+#define OMAP2420_CONTROL_PADCONF_SYS_32K_OFFSET				0x102
+#define OMAP2420_CONTROL_PADCONF_SYS_XTALIN_OFFSET			0x103
+#define OMAP2420_CONTROL_PADCONF_SYS_XTALOUT_OFFSET			0x104
+#define OMAP2420_CONTROL_PADCONF_GPIO_36_OFFSET				0x105
+#define OMAP2420_CONTROL_PADCONF_SYS_CLKREQ_OFFSET			0x106
+#define OMAP2420_CONTROL_PADCONF_SYS_CLKOUT_OFFSET			0x107
+#define OMAP2420_CONTROL_PADCONF_GPIO_6_OFFSET				0x108
+#define OMAP2420_CONTROL_PADCONF_GPIO_124_OFFSET			0x109
+#define OMAP2420_CONTROL_PADCONF_GPIO_125_OFFSET			0x10a
+#define OMAP2420_CONTROL_PADCONF_JTAG_EMU1_OFFSET			0x10b
+#define OMAP2420_CONTROL_PADCONF_JTAG_EMU0_OFFSET			0x10c
+#define OMAP2420_CONTROL_PADCONF_JTAG_NTRST_OFFSET			0x10d
+#define OMAP2420_CONTROL_PADCONF_JTAG_TCK_OFFSET			0x10e
+#define OMAP2420_CONTROL_PADCONF_JTAG_RTCK_OFFSET			0x10f
+#define OMAP2420_CONTROL_PADCONF_JTAG_TMS_OFFSET			0x110
+#define OMAP2420_CONTROL_PADCONF_JTAG_TDI_OFFSET			0x111
+#define OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET			0x112
+
+#define OMAP2420_CONTROL_PADCONF_MUX_SIZE			\
+		(OMAP2420_CONTROL_PADCONF_JTAG_TDO_OFFSET + 0x1)



From tony at atomide.com  Wed Jun 30 08:06:55 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:06:55 +0300
Subject: [PATCH 07/16] omap: mux: Select SIP package for H4
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120655.2637.13954.stgit@baageli.muru.com>

Select SIP package for H4

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig    |    1 +
 arch/arm/mach-omap2/board-h4.c |   12 ++++++++++++
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index d3932d3..b59cdb7 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -50,6 +50,7 @@ config MACH_OMAP2_TUSB6010
 config MACH_OMAP_H4
 	bool "OMAP 2420 H4 board"
 	depends on ARCH_OMAP2
+	select OMAP_PACKAGE_ZAF
 	select OMAP_DEBUG_DEVICES
 
 config MACH_OMAP_APOLLON
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 54a231c..8c58f51 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -42,6 +42,8 @@
 #include <plat/dma.h>
 #include <plat/gpmc.h>
 
+#include "mux.h"
+
 #define H4_FLASH_CS	0
 #define H4_SMC91X_CS	1
 
@@ -338,8 +340,18 @@ static struct i2c_board_info __initdata h4_i2c_board_info[] = {
 	},
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+	{ .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux	NULL
+#endif
+
 static void __init omap_h4_init(void)
 {
+	omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF);
+
 	/*
 	 * Make sure the serial ports are muxed on at this point.
 	 * You have to mux them off in device drivers later on



From tony at atomide.com  Wed Jun 30 08:06:50 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:06:50 +0300
Subject: [PATCH 06/16] omap: mux: Add data for 2430
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120650.2637.9581.stgit@baageli.muru.com>

Add data for 2430. Big thanks to Paul Walmsley <paul at pwsan.com>
for generating usable mux data out of TRMs.

Cc: Benoit Cousson <b-cousson at ti.com>
Signed-off-by: Paul Walmsley <paul at pwsan.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Makefile  |    1 
 arch/arm/mach-omap2/mux.h     |    8 
 arch/arm/mach-omap2/mux2430.c |  791 +++++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-omap2/mux2430.h |  370 +++++++++++++++++++
 4 files changed, 1170 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-omap2/mux2430.c
 create mode 100644 arch/arm/mach-omap2/mux2430.h

diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b7e5537..0f2f508 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -37,6 +37,7 @@ AFLAGS_sram34xx.o			:=-Wa,-march=armv7-a
 
 # Pin multiplexing
 obj-$(CONFIG_ARCH_OMAP2420)		+= mux2420.o
+obj-$(CONFIG_ARCH_OMAP2430)		+= mux2430.o
 obj-$(CONFIG_ARCH_OMAP3)		+= mux34xx.o
 
 # SMS/SDRC
diff --git a/arch/arm/mach-omap2/mux.h b/arch/arm/mach-omap2/mux.h
index e14cd4d..a8e040c 100644
--- a/arch/arm/mach-omap2/mux.h
+++ b/arch/arm/mach-omap2/mux.h
@@ -8,6 +8,7 @@
  */
 
 #include "mux2420.h"
+#include "mux2430.h"
 #include "mux34xx.h"
 
 #define OMAP_MUX_TERMINATOR	0xffff
@@ -181,6 +182,13 @@ void omap_mux_write_array(struct omap_board_mux *board_mux);
 int omap2420_mux_init(struct omap_board_mux *board_mux, int flags);
 
 /**
+ * omap2430_mux_init() - initialize mux system with board specific set
+ * @board_mux:		Board specific mux table
+ * @flags:		OMAP package type used for the board
+ */
+int omap2430_mux_init(struct omap_board_mux *board_mux, int flags);
+
+/**
  * omap3_mux_init() - initialize mux system with board specific set
  * @board_mux:		Board specific mux table
  * @flags:		OMAP package type used for the board
diff --git a/arch/arm/mach-omap2/mux2430.c b/arch/arm/mach-omap2/mux2430.c
new file mode 100644
index 0000000..7dcaaa8
--- /dev/null
+++ b/arch/arm/mach-omap2/mux2430.c
@@ -0,0 +1,791 @@
+/*
+ * Copyright (C) 2010 Nokia
+ * Copyright (C) 2010 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "mux.h"
+
+#ifdef CONFIG_OMAP_MUX
+
+#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)		\
+{									\
+	.reg_offset	= (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET),	\
+	.gpio		= (g),						\
+	.muxnames	= { m0, m1, m2, m3, m4, m5, m6, m7 },		\
+}
+
+#else
+
+#define _OMAP2430_MUXENTRY(M0, g, m0, m1, m2, m3, m4, m5, m6, m7)		\
+{									\
+	.reg_offset	= (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET),	\
+	.gpio		= (g),						\
+}
+
+#endif
+
+#define _OMAP2430_BALLENTRY(M0, bb, bt)					\
+{									\
+	.reg_offset	= (OMAP2430_CONTROL_PADCONF_##M0##_OFFSET),	\
+	.balls		= { bb, bt },					\
+}
+
+/*
+ * Superset of all mux modes for omap2430
+ */
+static struct omap_mux __initdata omap2430_muxmodes[] = {
+	_OMAP2430_MUXENTRY(CAM_D0, 133,
+		"cam_d0", "hw_dbg0", "sti_dout", "gpio_133",
+		NULL, NULL, "etk_d2", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_D10, 146,
+		"cam_d10", NULL, NULL, "gpio_146",
+		NULL, NULL, "etk_d12", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_D11, 145,
+		"cam_d11", NULL, NULL, "gpio_145",
+		NULL, NULL, "etk_d13", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_D1, 132,
+		"cam_d1", "hw_dbg1", "sti_din", "gpio_132",
+		NULL, NULL, "etk_d3", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_D2, 129,
+		"cam_d2", "hw_dbg2", "mcbsp1_clkx", "gpio_129",
+		NULL, NULL, "etk_d4", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_D3, 128,
+		"cam_d3", "hw_dbg3", "mcbsp1_dr", "gpio_128",
+		NULL, NULL, "etk_d5", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_D4, 143,
+		"cam_d4", "hw_dbg4", "mcbsp1_fsr", "gpio_143",
+		NULL, NULL, "etk_d6", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_D5, 112,
+		"cam_d5", "hw_dbg5", "mcbsp1_clkr", "gpio_112",
+		NULL, NULL, "etk_d7", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_D6, 137,
+		"cam_d6", "hw_dbg6", NULL, "gpio_137",
+		NULL, NULL, "etk_d8", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_D7, 136,
+		"cam_d7", "hw_dbg7", NULL, "gpio_136",
+		NULL, NULL, "etk_d9", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_D8, 135,
+		"cam_d8", "hw_dbg8", NULL, "gpio_135",
+		NULL, NULL, "etk_d10", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_D9, 134,
+		"cam_d9", "hw_dbg9", NULL, "gpio_134",
+		NULL, NULL, "etk_d11", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_HS, 11,
+		"cam_hs", "hw_dbg10", "mcbsp1_dx", "gpio_11",
+		NULL, NULL, "etk_d1", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_LCLK, 0,
+		"cam_lclk", NULL, "mcbsp_clks", NULL,
+		NULL, NULL, "etk_c1", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_VS, 12,
+		"cam_vs", "hw_dbg11", "mcbsp1_fsx", "gpio_12",
+		NULL, NULL, "etk_d0", "safe_mode"),
+	_OMAP2430_MUXENTRY(CAM_XCLK, 0,
+		"cam_xclk", NULL, "sti_clk", NULL,
+		NULL, NULL, "etk_c2", NULL),
+	_OMAP2430_MUXENTRY(DSS_ACBIAS, 48,
+		"dss_acbias", NULL, "mcbsp2_fsx", "gpio_48",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA0, 40,
+		"dss_data0", "uart1_cts", NULL, "gpio_40",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA10, 128,
+		"dss_data10", "sdi_data1n", NULL, "gpio_128",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA11, 129,
+		"dss_data11", "sdi_data1p", NULL, "gpio_129",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA12, 130,
+		"dss_data12", "sdi_data2n", NULL, "gpio_130",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA13, 131,
+		"dss_data13", "sdi_data2p", NULL, "gpio_131",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA14, 132,
+		"dss_data14", "sdi_data3n", NULL, "gpio_132",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA15, 133,
+		"dss_data15", "sdi_data3p", NULL, "gpio_133",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA16, 46,
+		"dss_data16", NULL, NULL, "gpio_46",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA17, 47,
+		"dss_data17", NULL, NULL, "gpio_47",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA1, 41,
+		"dss_data1", "uart1_rts", NULL, "gpio_41",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA2, 42,
+		"dss_data2", "uart1_tx", NULL, "gpio_42",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA3, 43,
+		"dss_data3", "uart1_rx", NULL, "gpio_43",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA4, 44,
+		"dss_data4", "uart3_rx_irrx", NULL, "gpio_44",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA5, 45,
+		"dss_data5", "uart3_tx_irtx", NULL, "gpio_45",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA6, 144,
+		"dss_data6", NULL, NULL, "gpio_144",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA7, 147,
+		"dss_data7", NULL, NULL, "gpio_147",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA8, 38,
+		"dss_data8", NULL, NULL, "gpio_38",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_DATA9, 39,
+		"dss_data9", NULL, NULL, "gpio_39",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(DSS_HSYNC, 110,
+		"dss_hsync", NULL, NULL, "gpio_110",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_113, 113,
+		"gpio_113", "mcbsp2_clkx", NULL, "gpio_113",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_114, 114,
+		"gpio_114", "mcbsp2_fsx", NULL, "gpio_114",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_115, 115,
+		"gpio_115", "mcbsp2_dr", NULL, "gpio_115",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_116, 116,
+		"gpio_116", "mcbsp2_dx", NULL, "gpio_116",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_128, 128,
+		"gpio_128", NULL, "sti_din", "gpio_128",
+		NULL, "sys_boot0", NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_129, 129,
+		"gpio_129", NULL, "sti_dout", "gpio_129",
+		NULL, "sys_boot1", NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_130, 130,
+		"gpio_130", NULL, NULL, "gpio_130",
+		"jtag_emu2", "sys_boot2", NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_131, 131,
+		"gpio_131", NULL, NULL, "gpio_131",
+		"jtag_emu3", "sys_boot3", NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_132, 132,
+		"gpio_132", NULL, NULL, "gpio_132",
+		NULL, "sys_boot4", NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_133, 133,
+		"gpio_133", NULL, NULL, "gpio_133",
+		NULL, "sys_boot5", NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_134, 134,
+		"gpio_134", "ccp_datn", NULL, "gpio_134",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_135, 135,
+		"gpio_135", "ccp_datp", NULL, "gpio_135",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_136, 136,
+		"gpio_136", "ccp_clkn", NULL, "gpio_136",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_137, 137,
+		"gpio_137", "ccp_clkp", NULL, "gpio_137",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_138, 138,
+		"gpio_138", "spi3_clk", NULL, "gpio_138",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_139, 139,
+		"gpio_139", "spi3_cs0", "sys_ndmareq3", "gpio_139",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_140, 140,
+		"gpio_140", "spi3_simo", "sys_ndmareq4", "gpio_140",
+		NULL, NULL, "etk_d14", "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_141, 141,
+		"gpio_141", "spi3_somi", NULL, "gpio_141",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_142, 142,
+		"gpio_142", "spi3_cs1", "sys_ndmareq2", "gpio_142",
+		NULL, NULL, "etk_d15", "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_148, 148,
+		"gpio_148", "mcbsp5_fsx", NULL, "gpio_148",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_149, 149,
+		"gpio_149", "mcbsp5_dx", NULL, "gpio_149",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_150, 150,
+		"gpio_150", "mcbsp5_dr", NULL, "gpio_150",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_151, 151,
+		"gpio_151", "sys_pwrok", NULL, "gpio_151",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_152, 152,
+		"gpio_152", "uart1_cts", "sys_ndmareq1", "gpio_152",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_153, 153,
+		"gpio_153", "uart1_rx", "sys_ndmareq0", "gpio_153",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_154, 154,
+		"gpio_154", "mcbsp5_clkx", NULL, "gpio_154",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_63, 63,
+		"gpio_63", "mcbsp4_clkx", NULL, "gpio_63",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_78, 78,
+		"gpio_78", NULL, "uart2_rts", "gpio_78",
+		"uart3_rts_sd", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_79, 79,
+		"gpio_79", "secure_indicator", "uart2_tx", "gpio_79",
+		"uart3_tx_irtx", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_7, 7,
+		"gpio_7", NULL, "uart2_cts", "gpio_7",
+		"uart3_cts_rctx", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPIO_80, 80,
+		"gpio_80", NULL, "uart2_rx", "gpio_80",
+		"uart3_rx_irrx", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_A10, 3,
+		"gpmc_a10", NULL, "sys_ndmareq0", "gpio_3",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_A1, 31,
+		"gpmc_a1", NULL, NULL, "gpio_31",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_A2, 30,
+		"gpmc_a2", NULL, NULL, "gpio_30",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_A3, 29,
+		"gpmc_a3", NULL, NULL, "gpio_29",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_A4, 49,
+		"gpmc_a4", NULL, NULL, "gpio_49",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_A5, 53,
+		"gpmc_a5", NULL, NULL, "gpio_53",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_A6, 52,
+		"gpmc_a6", NULL, NULL, "gpio_52",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_A7, 6,
+		"gpmc_a7", NULL, NULL, "gpio_6",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_A8, 5,
+		"gpmc_a8", NULL, NULL, "gpio_5",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_A9, 4,
+		"gpmc_a9", NULL, "sys_ndmareq1", "gpio_4",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_CLK, 21,
+		"gpmc_clk", NULL, NULL, "gpio_21",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_D10, 18,
+		"gpmc_d10", NULL, NULL, "gpio_18",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_D11, 57,
+		"gpmc_d11", NULL, NULL, "gpio_57",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_D12, 77,
+		"gpmc_d12", NULL, NULL, "gpio_77",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_D13, 76,
+		"gpmc_d13", NULL, NULL, "gpio_76",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_D14, 55,
+		"gpmc_d14", NULL, NULL, "gpio_55",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_D15, 54,
+		"gpmc_d15", NULL, NULL, "gpio_54",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_D8, 20,
+		"gpmc_d8", NULL, NULL, "gpio_20",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_D9, 19,
+		"gpmc_d9", NULL, NULL, "gpio_19",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_NCS1, 22,
+		"gpmc_ncs1", NULL, NULL, "gpio_22",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_NCS2, 23,
+		"gpmc_ncs2", NULL, NULL, "gpio_23",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_NCS3, 24,
+		"gpmc_ncs3", "gpmc_io_dir", NULL, "gpio_24",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_NCS4, 25,
+		"gpmc_ncs4", NULL, NULL, "gpio_25",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_NCS5, 26,
+		"gpmc_ncs5", NULL, NULL, "gpio_26",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_NCS6, 27,
+		"gpmc_ncs6", NULL, NULL, "gpio_27",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_NCS7, 28,
+		"gpmc_ncs7", "gpmc_io_dir", NULL, "gpio_28",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_WAIT1, 33,
+		"gpmc_wait1", NULL, NULL, "gpio_33",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_WAIT2, 34,
+		"gpmc_wait2", NULL, NULL, "gpio_34",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(GPMC_WAIT3, 35,
+		"gpmc_wait3", NULL, NULL, "gpio_35",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(HDQ_SIO, 101,
+		"hdq_sio", "usb2_tllse0", "sys_altclk", "gpio_101",
+		"uart3_rx_irrx", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(I2C1_SCL, 50,
+		"i2c1_scl", NULL, NULL, "gpio_50",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(I2C1_SDA, 51,
+		"i2c1_sda", NULL, NULL, "gpio_51",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(I2C2_SCL, 99,
+		"i2c2_scl", NULL, NULL, "gpio_99",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(I2C2_SDA, 100,
+		"i2c2_sda", NULL, NULL, "gpio_100",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(JTAG_EMU0, 127,
+		"jtag_emu0", "secure_indicator", NULL, "gpio_127",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(JTAG_EMU1, 126,
+		"jtag_emu1", NULL, NULL, "gpio_126",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP1_CLKR, 92,
+		"mcbsp1_clkr", "ssi2_dat_tx", NULL, "gpio_92",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP1_CLKX, 98,
+		"mcbsp1_clkx", "ssi2_wake", NULL, "gpio_98",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP1_DR, 95,
+		"mcbsp1_dr", "ssi2_dat_rx", NULL, "gpio_95",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP1_DX, 94,
+		"mcbsp1_dx", "ssi2_rdy_tx", NULL, "gpio_94",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP1_FSR, 93,
+		"mcbsp1_fsr", "ssi2_flag_tx", NULL, "gpio_93",
+		"spi2_cs1", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP1_FSX, 97,
+		"mcbsp1_fsx", "ssi2_rdy_rx", NULL, "gpio_97",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP2_CLKX, 147,
+		"mcbsp2_clkx", "sdi_clkp", "dss_data23", "gpio_147",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP2_DR, 144,
+		"mcbsp2_dr", "sdi_clkn", "dss_data22", "gpio_144",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP3_CLKX, 71,
+		"mcbsp3_clkx", NULL, NULL, "gpio_71",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP3_DR, 73,
+		"mcbsp3_dr", NULL, NULL, "gpio_73",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP3_DX, 74,
+		"mcbsp3_dx", NULL, "sti_clk", "gpio_74",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP3_FSX, 72,
+		"mcbsp3_fsx", NULL, NULL, "gpio_72",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(MCBSP_CLKS, 96,
+		"mcbsp_clks", "ssi2_flag_rx", NULL, "gpio_96",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SDMMC1_CLKO, 0,
+		"sdmmc1_clko", "ms_clko", NULL, NULL,
+		NULL, "hw_dbg9", "hw_dbg3", "safe_mode"),
+	_OMAP2430_MUXENTRY(SDMMC1_CMD, 0,
+		"sdmmc1_cmd", "ms_bs", NULL, NULL,
+		NULL, "hw_dbg8", "hw_dbg2", "safe_mode"),
+	_OMAP2430_MUXENTRY(SDMMC1_DAT0, 0,
+		"sdmmc1_dat0", "ms_dat0", NULL, NULL,
+		NULL, "hw_dbg7", "hw_dbg1", "safe_mode"),
+	_OMAP2430_MUXENTRY(SDMMC1_DAT1, 75,
+		"sdmmc1_dat1", "ms_dat1", NULL, "gpio_75",
+		NULL, "hw_dbg6", "hw_dbg0", "safe_mode"),
+	_OMAP2430_MUXENTRY(SDMMC1_DAT2, 0,
+		"sdmmc1_dat2", "ms_dat2", NULL, NULL,
+		NULL, "hw_dbg5", "hw_dbg10", "safe_mode"),
+	_OMAP2430_MUXENTRY(SDMMC1_DAT3, 0,
+		"sdmmc1_dat3", "ms_dat3", NULL, NULL,
+		NULL, "hw_dbg4", "hw_dbg11", "safe_mode"),
+	_OMAP2430_MUXENTRY(SDMMC2_CLKO, 13,
+		"sdmmc2_clko", NULL, NULL, "gpio_13",
+		NULL, "spi3_clk", NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SDMMC2_CMD, 15,
+		"sdmmc2_cmd", "usb2_rcv", NULL, "gpio_15",
+		NULL, "spi3_simo", NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SDMMC2_DAT0, 16,
+		"sdmmc2_dat0", "usb2_tllse0", NULL, "gpio_16",
+		NULL, "spi3_somi", NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SDMMC2_DAT1, 58,
+		"sdmmc2_dat1", "usb2_txen", NULL, "gpio_58",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SDMMC2_DAT2, 17,
+		"sdmmc2_dat2", "usb2_dat", NULL, "gpio_17",
+		NULL, "spi3_cs1", NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SDMMC2_DAT3, 14,
+		"sdmmc2_dat3", "usb2_se0", NULL, "gpio_14",
+		NULL, "spi3_cs0", NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SDRC_A12, 2,
+		"sdrc_a12", NULL, NULL, "gpio_2",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SDRC_A13, 1,
+		"sdrc_a13", NULL, NULL, "gpio_1",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SDRC_A14, 0,
+		"sdrc_a14", NULL, NULL, "gpio_0",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SDRC_CKE1, 36,
+		"sdrc_cke1", NULL, NULL, "gpio_36",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SDRC_NCS1, 37,
+		"sdrc_ncs1", NULL, NULL, "gpio_37",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SPI1_CLK, 81,
+		"spi1_clk", NULL, NULL, "gpio_81",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SPI1_CS0, 84,
+		"spi1_cs0", NULL, NULL, "gpio_84",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SPI1_CS1, 85,
+		"spi1_cs1", NULL, NULL, "gpio_85",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SPI1_CS2, 86,
+		"spi1_cs2", NULL, NULL, "gpio_86",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SPI1_CS3, 87,
+		"spi1_cs3", "spi2_cs1", NULL, "gpio_87",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SPI1_SIMO, 82,
+		"spi1_simo", NULL, NULL, "gpio_82",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SPI1_SOMI, 83,
+		"spi1_somi", NULL, NULL, "gpio_83",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SPI2_CLK, 88,
+		"spi2_clk", "gpt9_pwm_evt", NULL, "gpio_88",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SPI2_CS0, 91,
+		"spi2_cs0", "gpt12_pwm_evt", NULL, "gpio_91",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SPI2_SIMO, 89,
+		"spi2_simo", "gpt10_pwm_evt", NULL, "gpio_89",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SPI2_SOMI, 90,
+		"spi2_somi", "gpt11_pwm_evt", NULL, "gpio_90",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SSI1_DAT_RX, 62,
+		"ssi1_dat_rx", "uart1_rx", "usb1_dat", "gpio_62",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SSI1_DAT_TX, 59,
+		"ssi1_dat_tx", "uart1_tx", "usb1_se0", "gpio_59",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SSI1_FLAG_RX, 64,
+		"ssi1_flag_rx", "mcbsp4_dr", NULL, "gpio_64",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SSI1_FLAG_TX, 60,
+		"ssi1_flag_tx", "uart1_rts", "usb1_rcv", "gpio_60",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SSI1_RDY_RX, 65,
+		"ssi1_rdy_rx", "mcbsp4_dx", NULL, "gpio_65",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SSI1_RDY_TX, 61,
+		"ssi1_rdy_tx", "uart1_cts", "usb1_txen", "gpio_61",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SSI1_WAKE, 66,
+		"ssi1_wake", "mcbsp4_fsx", NULL, "gpio_66",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SYS_CLKOUT, 111,
+		"sys_clkout", NULL, NULL, "gpio_111",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SYS_DRM_MSECURE, 118,
+		"sys_drm_msecure", NULL, "sys_ndmareq6", "gpio_118",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SYS_NIRQ0, 56,
+		"sys_nirq0", NULL, NULL, "gpio_56",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(SYS_NIRQ1, 125,
+		"sys_nirq1", NULL, "sys_ndmareq5", "gpio_125",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(UART1_CTS, 32,
+		"uart1_cts", "sdi_vsync", "dss_data18", "gpio_32",
+		"mcbsp5_clkx", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(UART1_RTS, 8,
+		"uart1_rts", "sdi_hsync", "dss_data19", "gpio_8",
+		"mcbsp5_fsx", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(UART1_RX, 10,
+		"uart1_rx", "sdi_stp", "dss_data21", "gpio_10",
+		"mcbsp5_dr", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(UART1_TX, 9,
+		"uart1_tx", "sdi_den", "dss_data20", "gpio_9",
+		"mcbsp5_dx", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(UART2_CTS, 67,
+		"uart2_cts", "usb1_rcv", "gpt9_pwm_evt", "gpio_67",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(UART2_RTS, 68,
+		"uart2_rts", "usb1_txen", "gpt10_pwm_evt", "gpio_68",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(UART2_RX, 70,
+		"uart2_rx", "usb1_dat", "gpt12_pwm_evt", "gpio_70",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(UART2_TX, 69,
+		"uart2_tx", "usb1_se0", "gpt11_pwm_evt", "gpio_69",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(UART3_CTS_RCTX, 102,
+		"uart3_cts_rctx", "uart3_rx_irrx", NULL, "gpio_102",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(UART3_RTS_SD, 103,
+		"uart3_rts_sd", "uart3_tx_irtx", NULL, "gpio_103",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(UART3_RX_IRRX, 105,
+		"uart3_rx_irrx", NULL, NULL, "gpio_105",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(UART3_TX_IRTX, 104,
+		"uart3_tx_irtx", "uart3_cts_rctx", NULL, "gpio_104",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(USB0HS_CLK, 120,
+		"usb0hs_clk", NULL, NULL, "gpio_120",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(USB0HS_DATA0, 0,
+		"usb0hs_data0", "uart3_tx_irtx", NULL, NULL,
+		"usb0_txen", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(USB0HS_DATA1, 0,
+		"usb0hs_data1", "uart3_rx_irrx", NULL, NULL,
+		"usb0_dat", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(USB0HS_DATA2, 0,
+		"usb0hs_data2", "uart3_rts_sd", NULL, NULL,
+		"usb0_se0", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(USB0HS_DATA3, 106,
+		"usb0hs_data3", NULL, "uart3_cts_rctx", "gpio_106",
+		"usb0_puen", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(USB0HS_DATA4, 107,
+		"usb0hs_data4", "mcbsp2_dr", NULL, "gpio_107",
+		"usb0_vp", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(USB0HS_DATA5, 108,
+		"usb0hs_data5", "mcbsp2_dx", NULL, "gpio_108",
+		"usb0_vm", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(USB0HS_DATA6, 109,
+		"usb0hs_data6", "mcbsp2_fsx", NULL, "gpio_109",
+		"usb0_rcv", NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(USB0HS_DATA7, 124,
+		"usb0hs_data7", "mcbsp2_clkx", NULL, "gpio_124",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(USB0HS_DIR, 121,
+		"usb0hs_dir", NULL, NULL, "gpio_121",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(USB0HS_NXT, 123,
+		"usb0hs_nxt", NULL, NULL, "gpio_123",
+		NULL, NULL, NULL, "safe_mode"),
+	_OMAP2430_MUXENTRY(USB0HS_STP, 122,
+		"usb0hs_stp", NULL, NULL, "gpio_122",
+		NULL, NULL, NULL, "safe_mode"),
+	{ .reg_offset = OMAP_MUX_TERMINATOR },
+};
+
+/*
+ * Balls for POP package
+ * 447-pin s-PBGA Package, 0.00mm Ball Pitch (Bottom)
+ */
+#ifdef CONFIG_DEBUG_FS
+struct omap_ball __initdata omap2430_pop_ball[] = {
+	_OMAP2430_BALLENTRY(CAM_D0, "t8", NULL),
+	_OMAP2430_BALLENTRY(CAM_D1, "t4", NULL),
+	_OMAP2430_BALLENTRY(CAM_D10, "r4", NULL),
+	_OMAP2430_BALLENTRY(CAM_D11, "w3", NULL),
+	_OMAP2430_BALLENTRY(CAM_D2, "r2", NULL),
+	_OMAP2430_BALLENTRY(CAM_D3, "u3", NULL),
+	_OMAP2430_BALLENTRY(CAM_D4, "u2", NULL),
+	_OMAP2430_BALLENTRY(CAM_D5, "v1", NULL),
+	_OMAP2430_BALLENTRY(CAM_D6, "t3", NULL),
+	_OMAP2430_BALLENTRY(CAM_D7, "r3", NULL),
+	_OMAP2430_BALLENTRY(CAM_D8, "u7", NULL),
+	_OMAP2430_BALLENTRY(CAM_D9, "t7", NULL),
+	_OMAP2430_BALLENTRY(CAM_HS, "p2", NULL),
+	_OMAP2430_BALLENTRY(CAM_LCLK, "r7", NULL),
+	_OMAP2430_BALLENTRY(CAM_VS, "n2", NULL),
+	_OMAP2430_BALLENTRY(CAM_XCLK, "p3", NULL),
+	_OMAP2430_BALLENTRY(DSS_ACBIAS, "y3", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA0, "v8", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA1, "w1", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA10, "k25", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA11, "j25", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA12, "k24", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA13, "j24", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA14, "h25", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA15, "g25", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA16, "ac3", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA17, "y7", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA2, "u8", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA3, "u4", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA4, "v3", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA5, "aa4", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA6, "w8", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA7, "y1", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA8, "aa2", NULL),
+	_OMAP2430_BALLENTRY(DSS_DATA9, "ab4", NULL),
+	_OMAP2430_BALLENTRY(DSS_HSYNC, "v2", NULL),
+	_OMAP2430_BALLENTRY(GPIO_113, "ad16", NULL),
+	_OMAP2430_BALLENTRY(GPIO_114, "ac10", NULL),
+	_OMAP2430_BALLENTRY(GPIO_115, "ad13", NULL),
+	_OMAP2430_BALLENTRY(GPIO_116, "ae15", NULL),
+	_OMAP2430_BALLENTRY(GPIO_128, "p1", NULL),
+	_OMAP2430_BALLENTRY(GPIO_129, "r1", NULL),
+	_OMAP2430_BALLENTRY(GPIO_130, "p7", NULL),
+	_OMAP2430_BALLENTRY(GPIO_131, "l8", NULL),
+	_OMAP2430_BALLENTRY(GPIO_132, "w24", NULL),
+	_OMAP2430_BALLENTRY(GPIO_133, "aa24", NULL),
+	_OMAP2430_BALLENTRY(GPIO_134, "ae12", NULL),
+	_OMAP2430_BALLENTRY(GPIO_135, "ae11", NULL),
+	_OMAP2430_BALLENTRY(GPIO_136, "ad12", NULL),
+	_OMAP2430_BALLENTRY(GPIO_137, "ad11", NULL),
+	_OMAP2430_BALLENTRY(GPIO_138, "y12", NULL),
+	_OMAP2430_BALLENTRY(GPIO_139, "ad17", NULL),
+	_OMAP2430_BALLENTRY(GPIO_140, "l7", NULL),
+	_OMAP2430_BALLENTRY(GPIO_141, "ac24", NULL),
+	_OMAP2430_BALLENTRY(GPIO_142, "m3", NULL),
+	_OMAP2430_BALLENTRY(GPIO_148, "af12", NULL),
+	_OMAP2430_BALLENTRY(GPIO_149, "k7", NULL),
+	_OMAP2430_BALLENTRY(GPIO_150, "m1", NULL),
+	_OMAP2430_BALLENTRY(GPIO_151, "ad14", NULL),
+	_OMAP2430_BALLENTRY(GPIO_152, "ad18", NULL),
+	_OMAP2430_BALLENTRY(GPIO_153, "u24", NULL),
+	_OMAP2430_BALLENTRY(GPIO_154, "ae16", NULL),
+	_OMAP2430_BALLENTRY(GPIO_63, "n3", NULL),
+	_OMAP2430_BALLENTRY(GPIO_7, "ac23", NULL),
+	_OMAP2430_BALLENTRY(GPIO_78, "ad10", NULL),
+	_OMAP2430_BALLENTRY(GPIO_79, "ae10", NULL),
+	_OMAP2430_BALLENTRY(GPIO_80, "ae13", NULL),
+	_OMAP2430_BALLENTRY(GPMC_A1, "a9", NULL),
+	_OMAP2430_BALLENTRY(GPMC_A10, "g12", NULL),
+	_OMAP2430_BALLENTRY(GPMC_A2, "b8", NULL),
+	_OMAP2430_BALLENTRY(GPMC_A3, "g10", NULL),
+	_OMAP2430_BALLENTRY(GPMC_A4, "g11", NULL),
+	_OMAP2430_BALLENTRY(GPMC_A5, "a10", NULL),
+	_OMAP2430_BALLENTRY(GPMC_A6, "g13", NULL),
+	_OMAP2430_BALLENTRY(GPMC_A7, "a6", NULL),
+	_OMAP2430_BALLENTRY(GPMC_A8, "h1", NULL),
+	_OMAP2430_BALLENTRY(GPMC_A9, "c8", NULL),
+	_OMAP2430_BALLENTRY(GPMC_CLK, "n1", "l1"),
+	_OMAP2430_BALLENTRY(GPMC_D10, "d1", "n1"),
+	_OMAP2430_BALLENTRY(GPMC_D11, "d2", "p2"),
+	_OMAP2430_BALLENTRY(GPMC_D12, "e1", "p1"),
+	_OMAP2430_BALLENTRY(GPMC_D13, "e3", "m1"),
+	_OMAP2430_BALLENTRY(GPMC_D14, "c7", "j2"),
+	_OMAP2430_BALLENTRY(GPMC_D15, "f3", "k2"),
+	_OMAP2430_BALLENTRY(GPMC_D8, "e2", "r1"),
+	_OMAP2430_BALLENTRY(GPMC_D9, "ab1", "t1"),
+	_OMAP2430_BALLENTRY(GPMC_NCS1, "ac1", "w1"),
+	_OMAP2430_BALLENTRY(GPMC_NCS2, "c6", NULL),
+	_OMAP2430_BALLENTRY(GPMC_NCS3, "b9", NULL),
+	_OMAP2430_BALLENTRY(GPMC_NCS4, "b4", NULL),
+	_OMAP2430_BALLENTRY(GPMC_NCS5, "a4", NULL),
+	_OMAP2430_BALLENTRY(GPMC_NCS6, "f1", NULL),
+	_OMAP2430_BALLENTRY(GPMC_NCS7, "a7", NULL),
+	_OMAP2430_BALLENTRY(GPMC_WAIT1, "j1", "y8"),
+	_OMAP2430_BALLENTRY(GPMC_WAIT2, "b7", NULL),
+	_OMAP2430_BALLENTRY(GPMC_WAIT3, "g14", NULL),
+	_OMAP2430_BALLENTRY(HDQ_SIO, "h20", NULL),
+	_OMAP2430_BALLENTRY(I2C1_SCL, "y17", NULL),
+	_OMAP2430_BALLENTRY(I2C1_SDA, "ac19", NULL),
+	_OMAP2430_BALLENTRY(I2C2_SCL, "n7", NULL),
+	_OMAP2430_BALLENTRY(I2C2_SDA, "m4", NULL),
+	_OMAP2430_BALLENTRY(JTAG_EMU0, "e25", NULL),
+	_OMAP2430_BALLENTRY(JTAG_EMU1, "e24", NULL),
+	_OMAP2430_BALLENTRY(MCBSP1_CLKR, "ab2", NULL),
+	_OMAP2430_BALLENTRY(MCBSP1_CLKX, "y9", NULL),
+	_OMAP2430_BALLENTRY(MCBSP1_DR, "af3", NULL),
+	_OMAP2430_BALLENTRY(MCBSP1_DX, "aa1", NULL),
+	_OMAP2430_BALLENTRY(MCBSP1_FSR, "ad5", NULL),
+	_OMAP2430_BALLENTRY(MCBSP1_FSX, "ab3", NULL),
+	_OMAP2430_BALLENTRY(MCBSP2_CLKX, "j26", NULL),
+	_OMAP2430_BALLENTRY(MCBSP2_DR, "k26", NULL),
+	_OMAP2430_BALLENTRY(MCBSP3_CLKX, "ac9", NULL),
+	_OMAP2430_BALLENTRY(MCBSP3_DR, "ae2", NULL),
+	_OMAP2430_BALLENTRY(MCBSP3_DX, "af4", NULL),
+	_OMAP2430_BALLENTRY(MCBSP3_FSX, "ae4", NULL),
+	_OMAP2430_BALLENTRY(MCBSP_CLKS, "ad6", NULL),
+	_OMAP2430_BALLENTRY(SDMMC1_CLKO, "n23", NULL),
+	_OMAP2430_BALLENTRY(SDMMC1_CMD, "l23", NULL),
+	_OMAP2430_BALLENTRY(SDMMC1_DAT0, "m24", NULL),
+	_OMAP2430_BALLENTRY(SDMMC1_DAT1, "p23", NULL),
+	_OMAP2430_BALLENTRY(SDMMC1_DAT2, "t20", NULL),
+	_OMAP2430_BALLENTRY(SDMMC1_DAT3, "r20", NULL),
+	_OMAP2430_BALLENTRY(SDMMC2_CLKO, "v26", NULL),
+	_OMAP2430_BALLENTRY(SDMMC2_CMD, "w20", NULL),
+	_OMAP2430_BALLENTRY(SDMMC2_DAT0, "v23", NULL),
+	_OMAP2430_BALLENTRY(SDMMC2_DAT1, "y24", NULL),
+	_OMAP2430_BALLENTRY(SDMMC2_DAT2, "v25", NULL),
+	_OMAP2430_BALLENTRY(SDMMC2_DAT3, "v24", NULL),
+	_OMAP2430_BALLENTRY(SDRC_A12, "w26", "r21"),
+	_OMAP2430_BALLENTRY(SDRC_A13, "af20", "aa15"),
+	_OMAP2430_BALLENTRY(SDRC_A14, "af16", "y12"),
+	_OMAP2430_BALLENTRY(SDRC_CKE1, "af15", "y13"),
+	_OMAP2430_BALLENTRY(SDRC_NCS1, "aa25", "t20"),
+	_OMAP2430_BALLENTRY(SPI1_CLK, "y18", NULL),
+	_OMAP2430_BALLENTRY(SPI1_CS0, "u1", NULL),
+	_OMAP2430_BALLENTRY(SPI1_CS1, "af19", NULL),
+	_OMAP2430_BALLENTRY(SPI1_CS2, "ae19", NULL),
+	_OMAP2430_BALLENTRY(SPI1_CS3, "h24", NULL),
+	_OMAP2430_BALLENTRY(SPI1_SIMO, "ad15", NULL),
+	_OMAP2430_BALLENTRY(SPI1_SOMI, "ae17", NULL),
+	_OMAP2430_BALLENTRY(SPI2_CLK, "y20", NULL),
+	_OMAP2430_BALLENTRY(SPI2_CS0, "y19", NULL),
+	_OMAP2430_BALLENTRY(SPI2_SIMO, "ac20", NULL),
+	_OMAP2430_BALLENTRY(SPI2_SOMI, "ad19", NULL),
+	_OMAP2430_BALLENTRY(SSI1_DAT_RX, "aa26", NULL),
+	_OMAP2430_BALLENTRY(SSI1_DAT_TX, "ad24", NULL),
+	_OMAP2430_BALLENTRY(SSI1_FLAG_RX, "ad23", NULL),
+	_OMAP2430_BALLENTRY(SSI1_FLAG_TX, "ab24", NULL),
+	_OMAP2430_BALLENTRY(SSI1_RDY_RX, "ab25", NULL),
+	_OMAP2430_BALLENTRY(SSI1_RDY_TX, "y25", NULL),
+	_OMAP2430_BALLENTRY(SSI1_WAKE, "ac25", NULL),
+	_OMAP2430_BALLENTRY(SYS_CLKOUT, "r25", NULL),
+	_OMAP2430_BALLENTRY(SYS_DRM_MSECURE, "ae3", NULL),
+	_OMAP2430_BALLENTRY(SYS_NIRQ0, "w25", NULL),
+	_OMAP2430_BALLENTRY(SYS_NIRQ1, "ad21", NULL),
+	_OMAP2430_BALLENTRY(UART1_CTS, "p24", NULL),
+	_OMAP2430_BALLENTRY(UART1_RTS, "p25", NULL),
+	_OMAP2430_BALLENTRY(UART1_RX, "n24", NULL),
+	_OMAP2430_BALLENTRY(UART1_TX, "r24", NULL),
+	_OMAP2430_BALLENTRY(UART2_CTS, "u25", NULL),
+	_OMAP2430_BALLENTRY(UART2_RTS, "t23", NULL),
+	_OMAP2430_BALLENTRY(UART2_RX, "t24", NULL),
+	_OMAP2430_BALLENTRY(UART2_TX, "u20", NULL),
+	_OMAP2430_BALLENTRY(UART3_CTS_RCTX, "m2", NULL),
+	_OMAP2430_BALLENTRY(UART3_RTS_SD, "k2", NULL),
+	_OMAP2430_BALLENTRY(UART3_RX_IRRX, "l3", NULL),
+	_OMAP2430_BALLENTRY(UART3_TX_IRTX, "l2", NULL),
+	_OMAP2430_BALLENTRY(USB0HS_CLK, "ae8", NULL),
+	_OMAP2430_BALLENTRY(USB0HS_DATA0, "ad4", NULL),
+	_OMAP2430_BALLENTRY(USB0HS_DATA1, "ae6", NULL),
+	_OMAP2430_BALLENTRY(USB0HS_DATA2, "af9", NULL),
+	_OMAP2430_BALLENTRY(USB0HS_DATA3, "ad9", NULL),
+	_OMAP2430_BALLENTRY(USB0HS_DATA4, "y11", NULL),
+	_OMAP2430_BALLENTRY(USB0HS_DATA5, "ad7", NULL),
+	_OMAP2430_BALLENTRY(USB0HS_DATA6, "ae7", NULL),
+	_OMAP2430_BALLENTRY(USB0HS_DATA7, "ac7", NULL),
+	_OMAP2430_BALLENTRY(USB0HS_DIR, "ad8", NULL),
+	_OMAP2430_BALLENTRY(USB0HS_NXT, "ae9", NULL),
+	_OMAP2430_BALLENTRY(USB0HS_STP, "ae5", NULL),
+	{ .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap2430_pop_ball	 NULL
+#endif
+
+int __init omap2430_mux_init(struct omap_board_mux *board_subset, int flags)
+{
+	struct omap_ball *package_balls = NULL;
+
+	switch (flags & OMAP_PACKAGE_MASK) {
+	case OMAP_PACKAGE_ZAC:
+		package_balls = omap2430_pop_ball;
+		break;
+	default:
+		pr_warning("mux: No ball data available for omap2420 package\n");
+	}
+
+	return omap_mux_init(OMAP2430_CONTROL_PADCONF_MUX_PBASE,
+			     OMAP2430_CONTROL_PADCONF_MUX_SIZE,
+				omap2430_muxmodes, NULL, board_subset,
+				package_balls);
+}
diff --git a/arch/arm/mach-omap2/mux2430.h b/arch/arm/mach-omap2/mux2430.h
new file mode 100644
index 0000000..adbea0d
--- /dev/null
+++ b/arch/arm/mach-omap2/mux2430.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009 Texas Instruments
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define OMAP2430_CONTROL_PADCONF_MUX_PBASE			0x49002030LU
+
+#define OMAP2430_MUX(mode0, mux_value)					\
+{									\
+	.reg_offset	= (OMAP2430_CONTROL_PADCONF_##mode0##_OFFSET),	\
+	.value		= (mux_value),					\
+}
+
+/*
+ * OMAP2430 CONTROL_PADCONF* register offsets for pin-muxing
+ *
+ * Extracted from the TRM.  Add 0x49002030 to these values to get the
+ * absolute addresses.  The name in the macro is the mode-0 name of
+ * the pin.  NOTE: These registers are 8-bits wide.
+ *
+ * Note that these defines use SDMMC instead of MMC for compability
+ * with signal names used in 3630.
+ */
+#define OMAP2430_CONTROL_PADCONF_GPMC_CLK_OFFSET		0x000
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS0_OFFSET		0x001
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS1_OFFSET		0x002
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS2_OFFSET		0x003
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS3_OFFSET		0x004
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS4_OFFSET		0x005
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS5_OFFSET		0x006
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS6_OFFSET		0x007
+#define OMAP2430_CONTROL_PADCONF_GPMC_NCS7_OFFSET		0x008
+#define OMAP2430_CONTROL_PADCONF_GPMC_NADV_ALE_OFFSET		0x009
+#define OMAP2430_CONTROL_PADCONF_GPMC_NOE_NRE_OFFSET		0x00a
+#define OMAP2430_CONTROL_PADCONF_GPMC_NWE_OFFSET		0x00b
+#define OMAP2430_CONTROL_PADCONF_GPMC_NBE0_CLE_OFFSET		0x00c
+#define OMAP2430_CONTROL_PADCONF_GPMC_NBE1_OFFSET		0x00d
+#define OMAP2430_CONTROL_PADCONF_GPMC_NWP_OFFSET		0x00e
+#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT0_OFFSET		0x00f
+#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT1_OFFSET		0x010
+#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT2_OFFSET		0x011
+#define OMAP2430_CONTROL_PADCONF_GPMC_WAIT3_OFFSET		0x012
+#define OMAP2430_CONTROL_PADCONF_SDRC_CLK_OFFSET		0x013
+#define OMAP2430_CONTROL_PADCONF_SDRC_NCLK_OFFSET		0x014
+#define OMAP2430_CONTROL_PADCONF_SDRC_NCS0_OFFSET		0x015
+#define OMAP2430_CONTROL_PADCONF_SDRC_NCS1_OFFSET		0x016
+#define OMAP2430_CONTROL_PADCONF_SDRC_CKE0_OFFSET		0x017
+#define OMAP2430_CONTROL_PADCONF_SDRC_CKE1_OFFSET		0x018
+#define OMAP2430_CONTROL_PADCONF_SDRC_NRAS_OFFSET		0x019
+#define OMAP2430_CONTROL_PADCONF_SDRC_NCAS_OFFSET		0x01a
+#define OMAP2430_CONTROL_PADCONF_SDRC_NWE_OFFSET		0x01b
+#define OMAP2430_CONTROL_PADCONF_SDRC_DM0_OFFSET		0x01c
+#define OMAP2430_CONTROL_PADCONF_SDRC_DM1_OFFSET		0x01d
+#define OMAP2430_CONTROL_PADCONF_SDRC_DM2_OFFSET		0x01e
+#define OMAP2430_CONTROL_PADCONF_SDRC_DM3_OFFSET		0x01f
+#define OMAP2430_CONTROL_PADCONF_SDRC_DQS0_OFFSET		0x020
+#define OMAP2430_CONTROL_PADCONF_SDRC_DQS1_OFFSET		0x021
+#define OMAP2430_CONTROL_PADCONF_SDRC_DQS2_OFFSET		0x022
+#define OMAP2430_CONTROL_PADCONF_SDRC_DQS3_OFFSET		0x023
+#define OMAP2430_CONTROL_PADCONF_SDRC_A14_OFFSET		0x024
+#define OMAP2430_CONTROL_PADCONF_SDRC_A13_OFFSET		0x025
+#define OMAP2430_CONTROL_PADCONF_SDRC_A12_OFFSET		0x026
+#define OMAP2430_CONTROL_PADCONF_SDRC_BA1_OFFSET		0x027
+#define OMAP2430_CONTROL_PADCONF_SDRC_BA0_OFFSET		0x028
+#define OMAP2430_CONTROL_PADCONF_SDRC_A11_OFFSET		0x029
+#define OMAP2430_CONTROL_PADCONF_SDRC_A10_OFFSET		0x02a
+#define OMAP2430_CONTROL_PADCONF_SDRC_A9_OFFSET			0x02b
+#define OMAP2430_CONTROL_PADCONF_SDRC_A8_OFFSET			0x02c
+#define OMAP2430_CONTROL_PADCONF_SDRC_A7_OFFSET			0x02d
+#define OMAP2430_CONTROL_PADCONF_SDRC_A6_OFFSET			0x02e
+#define OMAP2430_CONTROL_PADCONF_SDRC_A5_OFFSET			0x02f
+#define OMAP2430_CONTROL_PADCONF_SDRC_A4_OFFSET			0x030
+#define OMAP2430_CONTROL_PADCONF_SDRC_A3_OFFSET			0x031
+#define OMAP2430_CONTROL_PADCONF_SDRC_A2_OFFSET			0x032
+#define OMAP2430_CONTROL_PADCONF_SDRC_A1_OFFSET			0x033
+#define OMAP2430_CONTROL_PADCONF_SDRC_A0_OFFSET			0x034
+#define OMAP2430_CONTROL_PADCONF_SDRC_D31_OFFSET		0x035
+#define OMAP2430_CONTROL_PADCONF_SDRC_D30_OFFSET		0x036
+#define OMAP2430_CONTROL_PADCONF_SDRC_D29_OFFSET		0x037
+#define OMAP2430_CONTROL_PADCONF_SDRC_D28_OFFSET		0x038
+#define OMAP2430_CONTROL_PADCONF_SDRC_D27_OFFSET		0x039
+#define OMAP2430_CONTROL_PADCONF_SDRC_D26_OFFSET		0x03a
+#define OMAP2430_CONTROL_PADCONF_SDRC_D25_OFFSET		0x03b
+#define OMAP2430_CONTROL_PADCONF_SDRC_D24_OFFSET		0x03c
+#define OMAP2430_CONTROL_PADCONF_SDRC_D23_OFFSET		0x03d
+#define OMAP2430_CONTROL_PADCONF_SDRC_D22_OFFSET		0x03e
+#define OMAP2430_CONTROL_PADCONF_SDRC_D21_OFFSET		0x03f
+#define OMAP2430_CONTROL_PADCONF_SDRC_D20_OFFSET		0x040
+#define OMAP2430_CONTROL_PADCONF_SDRC_D19_OFFSET		0x041
+#define OMAP2430_CONTROL_PADCONF_SDRC_D18_OFFSET		0x042
+#define OMAP2430_CONTROL_PADCONF_SDRC_D17_OFFSET		0x043
+#define OMAP2430_CONTROL_PADCONF_SDRC_D16_OFFSET		0x044
+#define OMAP2430_CONTROL_PADCONF_SDRC_D15_OFFSET		0x045
+#define OMAP2430_CONTROL_PADCONF_SDRC_D14_OFFSET		0x046
+#define OMAP2430_CONTROL_PADCONF_SDRC_D13_OFFSET		0x047
+#define OMAP2430_CONTROL_PADCONF_SDRC_D12_OFFSET		0x048
+#define OMAP2430_CONTROL_PADCONF_SDRC_D11_OFFSET		0x049
+#define OMAP2430_CONTROL_PADCONF_SDRC_D10_OFFSET		0x04a
+#define OMAP2430_CONTROL_PADCONF_SDRC_D9_OFFSET			0x04b
+#define OMAP2430_CONTROL_PADCONF_SDRC_D8_OFFSET			0x04c
+#define OMAP2430_CONTROL_PADCONF_SDRC_D7_OFFSET			0x04d
+#define OMAP2430_CONTROL_PADCONF_SDRC_D6_OFFSET			0x04e
+#define OMAP2430_CONTROL_PADCONF_SDRC_D5_OFFSET			0x04f
+#define OMAP2430_CONTROL_PADCONF_SDRC_D4_OFFSET			0x050
+#define OMAP2430_CONTROL_PADCONF_SDRC_D3_OFFSET			0x051
+#define OMAP2430_CONTROL_PADCONF_SDRC_D2_OFFSET			0x052
+#define OMAP2430_CONTROL_PADCONF_SDRC_D1_OFFSET			0x053
+#define OMAP2430_CONTROL_PADCONF_SDRC_D0_OFFSET			0x054
+#define OMAP2430_CONTROL_PADCONF_GPMC_A10_OFFSET		0x055
+#define OMAP2430_CONTROL_PADCONF_GPMC_A9_OFFSET			0x056
+#define OMAP2430_CONTROL_PADCONF_GPMC_A8_OFFSET			0x057
+#define OMAP2430_CONTROL_PADCONF_GPMC_A7_OFFSET			0x058
+#define OMAP2430_CONTROL_PADCONF_GPMC_A6_OFFSET			0x059
+#define OMAP2430_CONTROL_PADCONF_GPMC_A5_OFFSET			0x05a
+#define OMAP2430_CONTROL_PADCONF_GPMC_A4_OFFSET			0x05b
+#define OMAP2430_CONTROL_PADCONF_GPMC_A3_OFFSET			0x05c
+#define OMAP2430_CONTROL_PADCONF_GPMC_A2_OFFSET			0x05d
+#define OMAP2430_CONTROL_PADCONF_GPMC_A1_OFFSET			0x05e
+#define OMAP2430_CONTROL_PADCONF_GPMC_D15_OFFSET		0x05f
+#define OMAP2430_CONTROL_PADCONF_GPMC_D14_OFFSET		0x060
+#define OMAP2430_CONTROL_PADCONF_GPMC_D13_OFFSET		0x061
+#define OMAP2430_CONTROL_PADCONF_GPMC_D12_OFFSET		0x062
+#define OMAP2430_CONTROL_PADCONF_GPMC_D11_OFFSET		0x063
+#define OMAP2430_CONTROL_PADCONF_GPMC_D10_OFFSET		0x064
+#define OMAP2430_CONTROL_PADCONF_GPMC_D9_OFFSET			0x065
+#define OMAP2430_CONTROL_PADCONF_GPMC_D8_OFFSET			0x066
+#define OMAP2430_CONTROL_PADCONF_GPMC_D7_OFFSET			0x067
+#define OMAP2430_CONTROL_PADCONF_GPMC_D6_OFFSET			0x068
+#define OMAP2430_CONTROL_PADCONF_GPMC_D5_OFFSET			0x069
+#define OMAP2430_CONTROL_PADCONF_GPMC_D4_OFFSET			0x06a
+#define OMAP2430_CONTROL_PADCONF_GPMC_D3_OFFSET			0x06b
+#define OMAP2430_CONTROL_PADCONF_GPMC_D2_OFFSET			0x06c
+#define OMAP2430_CONTROL_PADCONF_GPMC_D1_OFFSET			0x06d
+#define OMAP2430_CONTROL_PADCONF_GPMC_D0_OFFSET			0x06e
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA0_OFFSET		0x06f
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA1_OFFSET		0x070
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA2_OFFSET		0x071
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA3_OFFSET		0x072
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA4_OFFSET		0x073
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA5_OFFSET		0x074
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA6_OFFSET		0x075
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA7_OFFSET		0x076
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA8_OFFSET		0x077
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA9_OFFSET		0x078
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA10_OFFSET		0x079
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA11_OFFSET		0x07a
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA12_OFFSET		0x07b
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA13_OFFSET		0x07c
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA14_OFFSET		0x07d
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA15_OFFSET		0x07e
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA16_OFFSET		0x07f
+#define OMAP2430_CONTROL_PADCONF_DSS_DATA17_OFFSET		0x080
+#define OMAP2430_CONTROL_PADCONF_UART1_CTS_OFFSET		0x081
+#define OMAP2430_CONTROL_PADCONF_UART1_RTS_OFFSET		0x082
+#define OMAP2430_CONTROL_PADCONF_UART1_TX_OFFSET		0x083
+#define OMAP2430_CONTROL_PADCONF_UART1_RX_OFFSET		0x084
+#define OMAP2430_CONTROL_PADCONF_MCBSP2_DR_OFFSET		0x085
+#define OMAP2430_CONTROL_PADCONF_MCBSP2_CLKX_OFFSET		0x086
+#define OMAP2430_CONTROL_PADCONF_DSS_PCLK_OFFSET		0x087
+#define OMAP2430_CONTROL_PADCONF_DSS_VSYNC_OFFSET		0x088
+#define OMAP2430_CONTROL_PADCONF_DSS_HSYNC_OFFSET		0x089
+#define OMAP2430_CONTROL_PADCONF_DSS_ACBIAS_OFFSET		0x08a
+#define OMAP2430_CONTROL_PADCONF_SYS_NRESPWRON_OFFSET		0x08b
+#define OMAP2430_CONTROL_PADCONF_SYS_NRESWARM_OFFSET		0x08c
+#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ0_OFFSET		0x08d
+#define OMAP2430_CONTROL_PADCONF_SYS_NIRQ1_OFFSET		0x08e
+#define OMAP2430_CONTROL_PADCONF_SYS_VMODE_OFFSET		0x08f
+#define OMAP2430_CONTROL_PADCONF_GPIO_128_OFFSET		0x090
+#define OMAP2430_CONTROL_PADCONF_GPIO_129_OFFSET		0x091
+#define OMAP2430_CONTROL_PADCONF_GPIO_130_OFFSET		0x092
+#define OMAP2430_CONTROL_PADCONF_GPIO_131_OFFSET		0x093
+#define OMAP2430_CONTROL_PADCONF_SYS_32K_OFFSET			0x094
+#define OMAP2430_CONTROL_PADCONF_SYS_XTALIN_OFFSET		0x095
+#define OMAP2430_CONTROL_PADCONF_SYS_XTALOUT_OFFSET		0x096
+#define OMAP2430_CONTROL_PADCONF_GPIO_132_OFFSET		0x097
+#define OMAP2430_CONTROL_PADCONF_SYS_CLKREQ_OFFSET		0x098
+#define OMAP2430_CONTROL_PADCONF_SYS_CLKOUT_OFFSET		0x099
+#define OMAP2430_CONTROL_PADCONF_GPIO_151_OFFSET		0x09a
+#define OMAP2430_CONTROL_PADCONF_GPIO_133_OFFSET		0x09b
+#define OMAP2430_CONTROL_PADCONF_JTAG_EMU1_OFFSET		0x09c
+#define OMAP2430_CONTROL_PADCONF_JTAG_EMU0_OFFSET		0x09d
+#define OMAP2430_CONTROL_PADCONF_JTAG_NTRST_OFFSET		0x09e
+#define OMAP2430_CONTROL_PADCONF_JTAG_TCK_OFFSET		0x09f
+#define OMAP2430_CONTROL_PADCONF_JTAG_RTCK_OFFSET		0x0a0
+#define OMAP2430_CONTROL_PADCONF_JTAG_TMS_OFFSET		0x0a1
+#define OMAP2430_CONTROL_PADCONF_JTAG_TDI_OFFSET		0x0a2
+#define OMAP2430_CONTROL_PADCONF_JTAG_TDO_OFFSET		0x0a3
+#define OMAP2430_CONTROL_PADCONF_CAM_D9_OFFSET			0x0a4
+#define OMAP2430_CONTROL_PADCONF_CAM_D8_OFFSET			0x0a5
+#define OMAP2430_CONTROL_PADCONF_CAM_D7_OFFSET			0x0a6
+#define OMAP2430_CONTROL_PADCONF_CAM_D6_OFFSET			0x0a7
+#define OMAP2430_CONTROL_PADCONF_CAM_D5_OFFSET			0x0a8
+#define OMAP2430_CONTROL_PADCONF_CAM_D4_OFFSET			0x0a9
+#define OMAP2430_CONTROL_PADCONF_CAM_D3_OFFSET			0x0aa
+#define OMAP2430_CONTROL_PADCONF_CAM_D2_OFFSET			0x0ab
+#define OMAP2430_CONTROL_PADCONF_CAM_D1_OFFSET			0x0ac
+#define OMAP2430_CONTROL_PADCONF_CAM_D0_OFFSET			0x0ad
+#define OMAP2430_CONTROL_PADCONF_CAM_HS_OFFSET			0x0ae
+#define OMAP2430_CONTROL_PADCONF_CAM_VS_OFFSET			0x0af
+#define OMAP2430_CONTROL_PADCONF_CAM_LCLK_OFFSET		0x0b0
+#define OMAP2430_CONTROL_PADCONF_CAM_XCLK_OFFSET		0x0b1
+#define OMAP2430_CONTROL_PADCONF_CAM_D11_OFFSET			0x0b2
+#define OMAP2430_CONTROL_PADCONF_CAM_D10_OFFSET			0x0b3
+#define OMAP2430_CONTROL_PADCONF_GPIO_134_OFFSET		0x0b4
+#define OMAP2430_CONTROL_PADCONF_GPIO_135_OFFSET		0x0b5
+#define OMAP2430_CONTROL_PADCONF_GPIO_136_OFFSET		0x0b6
+#define OMAP2430_CONTROL_PADCONF_GPIO_137_OFFSET		0x0b7
+#define OMAP2430_CONTROL_PADCONF_GPIO_138_OFFSET		0x0b8
+#define OMAP2430_CONTROL_PADCONF_GPIO_139_OFFSET		0x0b9
+#define OMAP2430_CONTROL_PADCONF_GPIO_140_OFFSET		0x0ba
+#define OMAP2430_CONTROL_PADCONF_GPIO_141_OFFSET		0x0bb
+#define OMAP2430_CONTROL_PADCONF_GPIO_142_OFFSET		0x0bc
+#define OMAP2430_CONTROL_PADCONF_GPIO_154_OFFSET		0x0bd
+#define OMAP2430_CONTROL_PADCONF_GPIO_148_OFFSET		0x0be
+#define OMAP2430_CONTROL_PADCONF_GPIO_149_OFFSET		0x0bf
+#define OMAP2430_CONTROL_PADCONF_GPIO_150_OFFSET		0x0c0
+#define OMAP2430_CONTROL_PADCONF_GPIO_152_OFFSET		0x0c1
+#define OMAP2430_CONTROL_PADCONF_GPIO_153_OFFSET		0x0c2
+#define OMAP2430_CONTROL_PADCONF_SDMMC1_CLKO_OFFSET		0x0c3
+#define OMAP2430_CONTROL_PADCONF_SDMMC1_CMD_OFFSET		0x0c4
+#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT0_OFFSET		0x0c5
+#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT1_OFFSET		0x0c6
+#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT2_OFFSET		0x0c7
+#define OMAP2430_CONTROL_PADCONF_SDMMC1_DAT3_OFFSET		0x0c8
+#define OMAP2430_CONTROL_PADCONF_SDMMC2_CLKO_OFFSET		0x0c9
+#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT3_OFFSET		0x0ca
+#define OMAP2430_CONTROL_PADCONF_SDMMC2_CMD_OFFSET		0x0cb
+#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT0_OFFSET		0x0cc
+#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT2_OFFSET		0x0cd
+#define OMAP2430_CONTROL_PADCONF_SDMMC2_DAT1_OFFSET		0x0ce
+#define OMAP2430_CONTROL_PADCONF_UART2_CTS_OFFSET		0x0cf
+#define OMAP2430_CONTROL_PADCONF_UART2_RTS_OFFSET		0x0d0
+#define OMAP2430_CONTROL_PADCONF_UART2_TX_OFFSET		0x0d1
+#define OMAP2430_CONTROL_PADCONF_UART2_RX_OFFSET		0x0d2
+#define OMAP2430_CONTROL_PADCONF_MCBSP3_CLKX_OFFSET		0x0d3
+#define OMAP2430_CONTROL_PADCONF_MCBSP3_FSX_OFFSET		0x0d4
+#define OMAP2430_CONTROL_PADCONF_MCBSP3_DR_OFFSET		0x0d5
+#define OMAP2430_CONTROL_PADCONF_MCBSP3_DX_OFFSET		0x0d6
+#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_TX_OFFSET		0x0d7
+#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_TX_OFFSET		0x0d8
+#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_TX_OFFSET		0x0d9
+#define OMAP2430_CONTROL_PADCONF_SSI1_DAT_RX_OFFSET		0x0da
+#define OMAP2430_CONTROL_PADCONF_GPIO_63_OFFSET			0x0db
+#define OMAP2430_CONTROL_PADCONF_SSI1_FLAG_RX_OFFSET		0x0dc
+#define OMAP2430_CONTROL_PADCONF_SSI1_RDY_RX_OFFSET		0x0dd
+#define OMAP2430_CONTROL_PADCONF_SSI1_WAKE_OFFSET		0x0de
+#define OMAP2430_CONTROL_PADCONF_SPI1_CLK_OFFSET		0x0df
+#define OMAP2430_CONTROL_PADCONF_SPI1_SIMO_OFFSET		0x0e0
+#define OMAP2430_CONTROL_PADCONF_SPI1_SOMI_OFFSET		0x0e1
+#define OMAP2430_CONTROL_PADCONF_SPI1_CS0_OFFSET		0x0e2
+#define OMAP2430_CONTROL_PADCONF_SPI1_CS1_OFFSET		0x0e3
+#define OMAP2430_CONTROL_PADCONF_SPI1_CS2_OFFSET		0x0e4
+#define OMAP2430_CONTROL_PADCONF_SPI1_CS3_OFFSET		0x0e5
+#define OMAP2430_CONTROL_PADCONF_SPI2_CLK_OFFSET		0x0e6
+#define OMAP2430_CONTROL_PADCONF_SPI2_SIMO_OFFSET		0x0e7
+#define OMAP2430_CONTROL_PADCONF_SPI2_SOMI_OFFSET		0x0e8
+#define OMAP2430_CONTROL_PADCONF_SPI2_CS0_OFFSET		0x0e9
+#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKR_OFFSET		0x0ea
+#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSR_OFFSET		0x0eb
+#define OMAP2430_CONTROL_PADCONF_MCBSP1_DX_OFFSET		0x0ec
+#define OMAP2430_CONTROL_PADCONF_MCBSP1_DR_OFFSET		0x0ed
+#define OMAP2430_CONTROL_PADCONF_MCBSP_CLKS_OFFSET		0x0ee
+#define OMAP2430_CONTROL_PADCONF_MCBSP1_FSX_OFFSET		0x0ef
+#define OMAP2430_CONTROL_PADCONF_MCBSP1_CLKX_OFFSET		0x0f0
+#define OMAP2430_CONTROL_PADCONF_I2C1_SCL_OFFSET		0x0f1
+#define OMAP2430_CONTROL_PADCONF_I2C1_SDA_OFFSET		0x0f2
+#define OMAP2430_CONTROL_PADCONF_I2C2_SCL_OFFSET		0x0f3
+#define OMAP2430_CONTROL_PADCONF_I2C2_SDA_OFFSET		0x0f4
+#define OMAP2430_CONTROL_PADCONF_HDQ_SIO_OFFSET			0x0f5
+#define OMAP2430_CONTROL_PADCONF_UART3_CTS_RCTX_OFFSET		0x0f6
+#define OMAP2430_CONTROL_PADCONF_UART3_RTS_SD_OFFSET		0x0f7
+#define OMAP2430_CONTROL_PADCONF_UART3_TX_IRTX_OFFSET		0x0f8
+#define OMAP2430_CONTROL_PADCONF_UART3_RX_IRRX_OFFSET		0x0f9
+#define OMAP2430_CONTROL_PADCONF_GPIO_7_OFFSET			0x0fa
+#define OMAP2430_CONTROL_PADCONF_GPIO_78_OFFSET			0x0fb
+#define OMAP2430_CONTROL_PADCONF_GPIO_79_OFFSET			0x0fc
+#define OMAP2430_CONTROL_PADCONF_GPIO_80_OFFSET			0x0fd
+#define OMAP2430_CONTROL_PADCONF_GPIO_113_OFFSET		0x0fe
+#define OMAP2430_CONTROL_PADCONF_GPIO_114_OFFSET		0x0ff
+#define OMAP2430_CONTROL_PADCONF_GPIO_115_OFFSET		0x100
+#define OMAP2430_CONTROL_PADCONF_GPIO_116_OFFSET		0x101
+#define OMAP2430_CONTROL_PADCONF_SYS_DRM_MSECURE_OFFSET		0x102
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA3_OFFSET		0x103
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA4_OFFSET		0x104
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA5_OFFSET		0x105
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA6_OFFSET		0x106
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA2_OFFSET		0x107
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA0_OFFSET		0x108
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA1_OFFSET		0x109
+#define OMAP2430_CONTROL_PADCONF_USB0HS_CLK_OFFSET		0x10a
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DIR_OFFSET		0x10b
+#define OMAP2430_CONTROL_PADCONF_USB0HS_STP_OFFSET		0x10c
+#define OMAP2430_CONTROL_PADCONF_USB0HS_NXT_OFFSET		0x10d
+#define OMAP2430_CONTROL_PADCONF_USB0HS_DATA7_OFFSET		0x10e
+#define OMAP2430_CONTROL_PADCONF_TV_OUT_OFFSET			0x10f
+#define OMAP2430_CONTROL_PADCONF_TV_VREF_OFFSET			0x110
+#define OMAP2430_CONTROL_PADCONF_TV_RSET_OFFSET			0x111
+#define OMAP2430_CONTROL_PADCONF_TV_VFB_OFFSET			0x112
+#define OMAP2430_CONTROL_PADCONF_TV_DACOUT_OFFSET		0x113
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD0_OFFSET		0x114
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD1_OFFSET		0x115
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD2_OFFSET		0x116
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD3_OFFSET		0x117
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD4_OFFSET		0x118
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD5_OFFSET		0x119
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD6_OFFSET		0x11a
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD7_OFFSET		0x11b
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD8_OFFSET		0x11c
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD9_OFFSET		0x11d
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD10_OFFSET		0x11e
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD11_OFFSET		0x11f
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD12_OFFSET		0x120
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD13_OFFSET		0x121
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD14_OFFSET		0x122
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD15_OFFSET		0x123
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD16_OFFSET		0x124
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD17_OFFSET		0x125
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD18_OFFSET		0x126
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD19_OFFSET		0x127
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD20_OFFSET		0x128
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD21_OFFSET		0x129
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD22_OFFSET		0x12a
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD23_OFFSET		0x12b
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD24_OFFSET		0x12c
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD25_OFFSET		0x12d
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD26_OFFSET		0x12e
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD27_OFFSET		0x12f
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD28_OFFSET		0x130
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD29_OFFSET		0x131
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD30_OFFSET		0x132
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD31_OFFSET		0x133
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD32_OFFSET		0x134
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD33_OFFSET		0x135
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD34_OFFSET		0x136
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD35_OFFSET		0x137
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD36_OFFSET		0x138
+#define OMAP2430_CONTROL_PADCONF_AD2DMCAD37_OFFSET		0x139
+#define OMAP2430_CONTROL_PADCONF_AD2DMWRITE_OFFSET		0x13a
+#define OMAP2430_CONTROL_PADCONF_D2DCLK26MI_OFFSET		0x13b
+#define OMAP2430_CONTROL_PADCONF_D2DNRESPWRON1_OFFSET		0x13c
+#define OMAP2430_CONTROL_PADCONF_D2DNRESWARM_OFFSET		0x13d
+#define OMAP2430_CONTROL_PADCONF_D2DARM9NIRQ_OFFSET		0x13e
+#define OMAP2430_CONTROL_PADCONF_D2DUMA2P6FIQ_OFFSET		0x13f
+#define OMAP2430_CONTROL_PADCONF_D2DSPINT_OFFSET		0x140
+#define OMAP2430_CONTROL_PADCONF_D2DFRINT_OFFSET		0x141
+#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ0_OFFSET		0x142
+#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ1_OFFSET		0x143
+#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ2_OFFSET		0x144
+#define OMAP2430_CONTROL_PADCONF_D2DDMAREQ3_OFFSET		0x145
+#define OMAP2430_CONTROL_PADCONF_D2DN3GTRST_OFFSET		0x146
+#define OMAP2430_CONTROL_PADCONF_D2DN3GTDI_OFFSET		0x147
+#define OMAP2430_CONTROL_PADCONF_D2DN3GTDO_OFFSET		0x148
+#define OMAP2430_CONTROL_PADCONF_D2DN3GTMS_OFFSET		0x149
+#define OMAP2430_CONTROL_PADCONF_D2DN3GTCK_OFFSET		0x14a
+#define OMAP2430_CONTROL_PADCONF_D2DN3GRTCK_OFFSET		0x14b
+#define OMAP2430_CONTROL_PADCONF_D2DMSTDBY_OFFSET		0x14c
+#define OMAP2430_CONTROL_PADCONF_AD2DSREAD_OFFSET		0x14d
+#define OMAP2430_CONTROL_PADCONF_D2DSWAKEUP_OFFSET		0x14e
+#define OMAP2430_CONTROL_PADCONF_D2DIDLEREQ_OFFSET		0x14f
+#define OMAP2430_CONTROL_PADCONF_D2DIDLEACK_OFFSET		0x150
+#define OMAP2430_CONTROL_PADCONF_D2DSPARE0_OFFSET		0x151
+#define OMAP2430_CONTROL_PADCONF_AD2DSWRITE_OFFSET		0x152
+#define OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET		0x153
+
+#define OMAP2430_CONTROL_PADCONF_MUX_SIZE			\
+		(OMAP2430_CONTROL_PADCONF_AD2DMREAD_OFFSET + 0x1)



From tony at atomide.com  Wed Jun 30 08:06:59 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:06:59 +0300
Subject: [PATCH 08/16] omap: mux: Select POP package for Apollon
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120659.2637.21973.stgit@baageli.muru.com>

Select POP package for Apollon

Cc: Kyungmin Park <kyungmin.park at samsung.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig         |    1 +
 arch/arm/mach-omap2/board-apollon.c |   12 ++++++++++++
 2 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index b59cdb7..269f84f 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -56,6 +56,7 @@ config MACH_OMAP_H4
 config MACH_OMAP_APOLLON
 	bool "OMAP 2420 Apollon board"
 	depends on ARCH_OMAP2
+	select OMAP_PACKAGE_ZAC
 
 config MACH_OMAP_2430SDP
 	bool "OMAP 2430 SDP board"
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 987b24d..b86a879 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -42,6 +42,8 @@
 #include <plat/gpmc.h>
 #include <plat/control.h>
 
+#include "mux.h"
+
 /* LED & Switch macros */
 #define LED0_GPIO13		13
 #define LED1_GPIO14		14
@@ -309,10 +311,20 @@ static void __init apollon_usb_init(void)
 	omap2_usbfs_init(&apollon_usb_config);
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+	{ .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux	NULL
+#endif
+
 static void __init omap_apollon_init(void)
 {
 	u32 v;
 
+	omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
+
 	apollon_led_init();
 	apollon_flash_init();
 	apollon_usb_init();



From tony at atomide.com  Wed Jun 30 08:07:02 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:07:02 +0300
Subject: [PATCH 09/16] omap: mux: Select POP package for N8X0
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120702.2637.12923.stgit@baageli.muru.com>

Select POP package for N8X0

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig      |    1 +
 arch/arm/mach-omap2/board-n8x0.c |   11 +++++++++++
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 269f84f..4158368 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -120,6 +120,7 @@ config MACH_NOKIA_N810_WIMAX
 config MACH_NOKIA_N8X0
 	bool "Nokia N800/N810"
 	depends on ARCH_OMAP2420
+	select OMAP_PACKAGE_ZAC
 	select MACH_NOKIA_N800
 	select MACH_NOKIA_N810
 	select MACH_NOKIA_N810_WIMAX
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 3ccc34e..5b9bbdc 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -33,6 +33,8 @@
 #include <plat/mmc.h>
 #include <plat/serial.h>
 
+#include "mux.h"
+
 static int slot1_cover_open;
 static int slot2_cover_open;
 static struct device *mmc_device;
@@ -649,8 +651,17 @@ static void __init n8x0_init_irq(void)
 	omap_gpio_init();
 }
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+	{ .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux	NULL
+#endif
+
 static void __init n8x0_init_machine(void)
 {
+	omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
 	/* FIXME: add n810 spi devices */
 	spi_register_board_info(n800_spi_board_info,
 				ARRAY_SIZE(n800_spi_board_info));



From tony at atomide.com  Wed Jun 30 08:07:06 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:07:06 +0300
Subject: [PATCH 10/16] omap: mux: Select POP package for 2430SDP
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120706.2637.40524.stgit@baageli.muru.com>

Select POP package for 2430SDP

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/Kconfig         |    1 +
 arch/arm/mach-omap2/board-2430sdp.c |   11 +++++++++++
 2 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4158368..f67f037 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -61,6 +61,7 @@ config MACH_OMAP_APOLLON
 config MACH_OMAP_2430SDP
 	bool "OMAP 2430 SDP board"
 	depends on ARCH_OMAP2
+	select OMAP_PACKAGE_ZAC
 
 config MACH_OMAP3_BEAGLE
 	bool "OMAP3 BEAGLE board"
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index ec920c9..281aa13 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -38,6 +38,7 @@
 #include <plat/usb.h>
 #include <plat/gpmc-smc91x.h>
 
+#include "mux.h"
 #include "hsmmc.h"
 
 #define SDP2430_CS0_BASE	0x04000000
@@ -217,10 +218,20 @@ static struct omap_usb_config sdp2430_usb_config __initdata = {
 	.pins[0]	= 3,
 };
 
+#ifdef CONFIG_OMAP_MUX
+static struct omap_board_mux board_mux[] __initdata = {
+	{ .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define board_mux	NULL
+#endif
+
 static void __init omap_2430sdp_init(void)
 {
 	int ret;
 
+	omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
+
 	omap2430_i2c_init();
 
 	platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));



From tony at atomide.com  Wed Jun 30 08:07:10 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:07:10 +0300
Subject: [PATCH 11/16] omap: mux: Make omap2 FS USB code use new mux functions
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120710.2637.93333.stgit@baageli.muru.com>

Make omap2 FS USB code use new mux functions. Do not mux usb2_tllse0
as it has multiple options.

Cc: David Brownell <dbrownell at users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/usb-fs.c |   33 ++++++++++++++++++---------------
 1 files changed, 18 insertions(+), 15 deletions(-)

diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
index a445519..a216d88 100644
--- a/arch/arm/mach-omap2/usb-fs.c
+++ b/arch/arm/mach-omap2/usb-fs.c
@@ -30,7 +30,6 @@
 #include <asm/irq.h>
 
 #include <plat/control.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 
@@ -40,6 +39,8 @@
 #define INT_USB_IRQ_HGEN	INT_24XX_USB_IRQ_HGEN
 #define INT_USB_IRQ_OTG		INT_24XX_USB_IRQ_OTG
 
+#include "mux.h"
+
 #if defined(CONFIG_ARCH_OMAP2)
 
 #ifdef	CONFIG_USB_GADGET_OMAP
@@ -209,13 +210,13 @@ static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device)
 		return 0;
 
 	if (is_device)
-		omap_cfg_reg(J20_24XX_USB0_PUEN);
+		omap_mux_init_signal("usb0_puen", 0);
 
-	omap_cfg_reg(K18_24XX_USB0_DAT);
-	omap_cfg_reg(K19_24XX_USB0_TXEN);
-	omap_cfg_reg(J14_24XX_USB0_SE0);
+	omap_mux_init_signal("usb0_dat", 0);
+	omap_mux_init_signal("usb0_txen", 0);
+	omap_mux_init_signal("usb0_se0", 0);
 	if (nwires != 3)
-		omap_cfg_reg(J18_24XX_USB0_RCV);
+		omap_mux_init_signal("usb0_rcv", 0);
 
 	switch (nwires) {
 	case 3:
@@ -228,8 +229,8 @@ static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device)
 		break;
 	case 6:
 		syscon1 = 3;
-		omap_cfg_reg(J19_24XX_USB0_VP);
-		omap_cfg_reg(K20_24XX_USB0_VM);
+		omap_mux_init_signal("usb0_vp", 0);
+		omap_mux_init_signal("usb0_vm", 0);
 		omap2_usb_devconf_set(0, USB_UNIDIR);
 		break;
 	default:
@@ -289,12 +290,12 @@ static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
 	if (alt_pingroup || nwires == 0)
 		return 0;
 
-	omap_cfg_reg(Y11_24XX_USB2_DAT);
-	omap_cfg_reg(AA10_24XX_USB2_SE0);
+	omap_mux_init_signal("usb2_dat", 0);
+	omap_mux_init_signal("usb2_se0", 0);
 	if (nwires > 2)
-		omap_cfg_reg(AA12_24XX_USB2_TXEN);
+		omap_mux_init_signal("usb2_txen", 0);
 	if (nwires > 3)
-		omap_cfg_reg(AA6_24XX_USB2_RCV);
+		omap_mux_init_signal("usb2_rcv", 0);
 
 	switch (nwires) {
 	case 2:
@@ -313,11 +314,13 @@ static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
 		omap2_usb_devconf_set(2, USB_BIDIR);
 		break;
 	case 5:
-		omap_cfg_reg(AA4_24XX_USB2_TLLSE0);
-		/* NOTE: board-specific code must override this setting if
-		 * this TLL link is not using DP/DM.  Something must also
+		/* NOTE: board-specific code must mux this setting depending
+		 * on TLL link using DP/DM.  Something must also
 		 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
+		 * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0
+		 * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0
 		 */
+
 		syscon1 = 3;
 		omap2_usb2_enable_5pinunitll();
 		break;



From tony at atomide.com  Wed Jun 30 08:07:15 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:07:15 +0300
Subject: [PATCH 12/16] omap: mux: Do keypad muxing in board-*.c files
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120715.2637.7678.stgit@baageli.muru.com>

This way we get pin muxing out of plat-omap and can convert H4 to use the
new mux functions.

Note that it should be safe to assume we can mux all the keypad pins
except on H4 which may have Menelaus connected.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap1/board-fsample.c  |   12 +++++++
 arch/arm/mach-omap1/board-h2.c       |   13 +++++++
 arch/arm/mach-omap1/board-h3.c       |   13 +++++++
 arch/arm/mach-omap1/board-perseus2.c |   12 +++++++
 arch/arm/mach-omap2/board-h4.c       |   17 +++++++++
 arch/arm/plat-omap/devices.c         |   61 ----------------------------------
 6 files changed, 67 insertions(+), 61 deletions(-)

diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 096f2ed..405ff7a 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -292,6 +292,18 @@ static void __init omap_fsample_init(void)
 	omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
 	omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
 
+	/* Mux pins for keypad */
+	omap_cfg_reg(E2_7XX_KBR0);
+	omap_cfg_reg(J7_7XX_KBR1);
+	omap_cfg_reg(E1_7XX_KBR2);
+	omap_cfg_reg(F3_7XX_KBR3);
+	omap_cfg_reg(D2_7XX_KBR4);
+	omap_cfg_reg(C2_7XX_KBC0);
+	omap_cfg_reg(D3_7XX_KBC1);
+	omap_cfg_reg(E4_7XX_KBC2);
+	omap_cfg_reg(F4_7XX_KBC3);
+	omap_cfg_reg(E3_7XX_KBC4);
+
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	omap_board_config = fsample_config;
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 5f30188..ee46974 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -437,6 +437,19 @@ static void __init h2_init(void)
 	/* omap_cfg_reg(U19_ARMIO1); */		/* CD */
 	omap_cfg_reg(BALLOUT_V8_ARMIO3);	/* WP */
 
+	/* Mux pins for keypad */
+	omap_cfg_reg(F18_1610_KBC0);
+	omap_cfg_reg(D20_1610_KBC1);
+	omap_cfg_reg(D19_1610_KBC2);
+	omap_cfg_reg(E18_1610_KBC3);
+	omap_cfg_reg(C21_1610_KBC4);
+	omap_cfg_reg(G18_1610_KBR0);
+	omap_cfg_reg(F19_1610_KBR1);
+	omap_cfg_reg(H14_1610_KBR2);
+	omap_cfg_reg(E20_1610_KBR3);
+	omap_cfg_reg(E19_1610_KBR4);
+	omap_cfg_reg(N19_1610_KBR5);
+
 	/* Irda */
 #if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
 	omap_writel(omap_readl(FUNC_MUX_CTRL_A) | 7, FUNC_MUX_CTRL_A);
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 0be1d3b..a228e9d 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -397,6 +397,19 @@ static void __init h3_init(void)
 	/* GPIO10 pullup/down register, Enable pullup on GPIO10 */
 	omap_cfg_reg(V2_1710_GPIO10);
 
+	/* Mux pins for keypad */
+	omap_cfg_reg(F18_1610_KBC0);
+	omap_cfg_reg(D20_1610_KBC1);
+	omap_cfg_reg(D19_1610_KBC2);
+	omap_cfg_reg(E18_1610_KBC3);
+	omap_cfg_reg(C21_1610_KBC4);
+	omap_cfg_reg(G18_1610_KBR0);
+	omap_cfg_reg(F19_1610_KBR1);
+	omap_cfg_reg(H14_1610_KBR2);
+	omap_cfg_reg(E20_1610_KBR3);
+	omap_cfg_reg(E19_1610_KBR4);
+	omap_cfg_reg(N19_1610_KBR5);
+
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 	spi_register_board_info(h3_spi_board_info,
 				ARRAY_SIZE(h3_spi_board_info));
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index e854d57..5069034 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -260,6 +260,18 @@ static void __init omap_perseus2_init(void)
 	omap_cfg_reg(L3_1610_FLASH_CS2B_OE);
 	omap_cfg_reg(M8_1610_FLASH_CS2B_WE);
 
+	/* Mux pins for keypad */
+	omap_cfg_reg(E2_7XX_KBR0);
+	omap_cfg_reg(J7_7XX_KBR1);
+	omap_cfg_reg(E1_7XX_KBR2);
+	omap_cfg_reg(F3_7XX_KBR3);
+	omap_cfg_reg(D2_7XX_KBR4);
+	omap_cfg_reg(C2_7XX_KBC0);
+	omap_cfg_reg(D3_7XX_KBC1);
+	omap_cfg_reg(E4_7XX_KBC2);
+	omap_cfg_reg(F4_7XX_KBC3);
+	omap_cfg_reg(E3_7XX_KBC4);
+
 	platform_add_devices(devices, ARRAY_SIZE(devices));
 
 	omap_board_config = perseus2_config;
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 8c58f51..cdcd4fb 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -363,11 +363,28 @@ static void __init omap_h4_init(void)
 #endif
 
 #if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
+	omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP);
+	omap_mux_init_gpio(89, OMAP_PULL_ENA | OMAP_PULL_UP);
+	omap_mux_init_gpio(124, OMAP_PULL_ENA | OMAP_PULL_UP);
+	omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
 	if (omap_has_menelaus()) {
+		omap_mux_init_signal("sdrc_a14.gpio0",
+			OMAP_PULL_ENA | OMAP_PULL_UP);
+		omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
+		omap_mux_init_signal("gpio_98", 0);
 		row_gpios[5] = 0;
 		col_gpios[2] = 15;
 		col_gpios[6] = 18;
+	} else {
+		omap_mux_init_signal("gpio_96", OMAP_PULL_ENA | OMAP_PULL_UP);
+		omap_mux_init_signal("gpio_100", 0);
+		omap_mux_init_signal("gpio_98", 0);
 	}
+	omap_mux_init_signal("gpio_90", 0);
+	omap_mux_init_signal("gpio_91", 0);
+	omap_mux_init_signal("gpio_36", 0);
+	omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
+	omap_mux_init_signal("gpio_97", 0);
 #endif
 
 	i2c_register_board_info(1, h4_i2c_board_info,
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 95677d1..ca5b229 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -24,7 +24,6 @@
 #include <plat/control.h>
 #include <plat/board.h>
 #include <plat/mmc.h>
-#include <plat/mux.h>
 #include <mach/gpio.h>
 #include <plat/menelaus.h>
 #include <plat/mcbsp.h>
@@ -93,66 +92,7 @@ static inline void omap_init_dsp(void) { }
 #endif	/* CONFIG_OMAP_DSP */
 
 /*-------------------------------------------------------------------------*/
-#if	defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
 
-static void omap_init_kp(void)
-{
-	/* 2430 and 34xx keypad is on TWL4030 */
-	if (cpu_is_omap2430() || cpu_is_omap34xx())
-		return;
-
-	if (machine_is_omap_h2() || machine_is_omap_h3()) {
-		omap_cfg_reg(F18_1610_KBC0);
-		omap_cfg_reg(D20_1610_KBC1);
-		omap_cfg_reg(D19_1610_KBC2);
-		omap_cfg_reg(E18_1610_KBC3);
-		omap_cfg_reg(C21_1610_KBC4);
-
-		omap_cfg_reg(G18_1610_KBR0);
-		omap_cfg_reg(F19_1610_KBR1);
-		omap_cfg_reg(H14_1610_KBR2);
-		omap_cfg_reg(E20_1610_KBR3);
-		omap_cfg_reg(E19_1610_KBR4);
-		omap_cfg_reg(N19_1610_KBR5);
-	} else if (machine_is_omap_perseus2() || machine_is_omap_fsample()) {
-		omap_cfg_reg(E2_7XX_KBR0);
-		omap_cfg_reg(J7_7XX_KBR1);
-		omap_cfg_reg(E1_7XX_KBR2);
-		omap_cfg_reg(F3_7XX_KBR3);
-		omap_cfg_reg(D2_7XX_KBR4);
-
-		omap_cfg_reg(C2_7XX_KBC0);
-		omap_cfg_reg(D3_7XX_KBC1);
-		omap_cfg_reg(E4_7XX_KBC2);
-		omap_cfg_reg(F4_7XX_KBC3);
-		omap_cfg_reg(E3_7XX_KBC4);
-	} else if (machine_is_omap_h4()) {
-		omap_cfg_reg(T19_24XX_KBR0);
-		omap_cfg_reg(R19_24XX_KBR1);
-		omap_cfg_reg(V18_24XX_KBR2);
-		omap_cfg_reg(M21_24XX_KBR3);
-		omap_cfg_reg(E5__24XX_KBR4);
-		if (omap_has_menelaus()) {
-			omap_cfg_reg(B3__24XX_KBR5);
-			omap_cfg_reg(AA4_24XX_KBC2);
-			omap_cfg_reg(B13_24XX_KBC6);
-		} else {
-			omap_cfg_reg(M18_24XX_KBR5);
-			omap_cfg_reg(H19_24XX_KBC2);
-			omap_cfg_reg(N19_24XX_KBC6);
-		}
-		omap_cfg_reg(R20_24XX_KBC0);
-		omap_cfg_reg(M14_24XX_KBC1);
-		omap_cfg_reg(V17_24XX_KBC3);
-		omap_cfg_reg(P21_24XX_KBC4);
-		omap_cfg_reg(L14_24XX_KBC5);
-	}
-}
-#else
-static inline void omap_init_kp(void) {}
-#endif
-
-/*-------------------------------------------------------------------------*/
 #if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
 
 static struct platform_device **omap_mcbsp_devices;
@@ -420,7 +360,6 @@ static int __init omap_init_devices(void)
 	 * in alphabetical order so they're easier to sort through.
 	 */
 	omap_init_dsp();
-	omap_init_kp();
 	omap_init_rng();
 	omap_init_mcpdm();
 	omap_init_uwire();



From tony at atomide.com  Wed Jun 30 08:07:19 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:07:19 +0300
Subject: [PATCH 13/16] omap: mux: Mux Apollon LCD power in board-apollon.c
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120719.2637.65586.stgit@baageli.muru.com>

Use the new mux function for that.

Cc: Kyungmin Park <kyungmin.park at samsung.com>
Cc: Tomi Valkeinen <tomi.valkeinen at nokia.com>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-apollon.c |    3 +++
 drivers/video/omap/lcd_apollon.c    |    3 ---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index b86a879..bc67026 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -332,6 +332,9 @@ static void __init omap_apollon_init(void)
 	/* REVISIT: where's the correct place */
 	omap_cfg_reg(W19_24XX_SYS_NIRQ);
 
+	/* LCD PWR_EN */
+	omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
+
 	/* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
 	v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
 	v |= (1 << 24);
diff --git a/drivers/video/omap/lcd_apollon.c b/drivers/video/omap/lcd_apollon.c
index 2be94eb..10459d8 100644
--- a/drivers/video/omap/lcd_apollon.c
+++ b/drivers/video/omap/lcd_apollon.c
@@ -25,7 +25,6 @@
 #include <linux/platform_device.h>
 
 #include <mach/gpio.h>
-#include <plat/mux.h>
 
 #include "omapfb.h"
 
@@ -34,8 +33,6 @@
 static int apollon_panel_init(struct lcd_panel *panel,
 				struct omapfb_device *fbdev)
 {
-	/* configure LCD PWR_EN */
-	omap_cfg_reg(M21_242X_GPIO11);
 	return 0;
 }
 



From tony at atomide.com  Wed Jun 30 08:07:23 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:07:23 +0300
Subject: [PATCH 14/16] omap: mux: Mux 2430 USB0HS_STP in board-2430.c
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120723.2637.54397.stgit@baageli.muru.com>

Use new mux functions for that. There are no other known 2430 boards
that need this mux.

Cc: Felipe Balbi <felipe.balbi at nokia.com>
Cc: David Brownell <dbrownell at users.sourceforge.net>
Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-2430sdp.c |    4 +++-
 drivers/usb/musb/omap2430.c         |    4 ----
 2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 281aa13..71bf509 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -31,7 +31,6 @@
 #include <asm/mach/map.h>
 
 #include <mach/gpio.h>
-#include <plat/mux.h>
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/gpmc.h>
@@ -238,7 +237,10 @@ static void __init omap_2430sdp_init(void)
 	omap_serial_init();
 	omap2_hsmmc_init(mmc);
 	omap2_usbfs_init(&sdp2430_usb_config);
+
+	omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
 	usb_musb_init(&musb_board_data);
+
 	board_smc91x_init();
 
 	/* Turn off secondary LCD backlight */
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index e06d65e..5f04d3f 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -194,10 +194,6 @@ int __init musb_platform_init(struct musb *musb, void *board_data)
 	u32 l;
 	struct omap_musb_board_data *data = board_data;
 
-#if defined(CONFIG_ARCH_OMAP2430)
-	omap_cfg_reg(AE5_2430_USB0HS_STP);
-#endif
-
 	/* We require some kind of external transceiver, hooked
 	 * up through ULPI.  TWL4030-family PMICs include one,
 	 * which needs a driver, drivers aren't always needed.



From tony at atomide.com  Wed Jun 30 08:07:27 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:07:27 +0300
Subject: [PATCH 15/16] omap: mux: Convert 2420 platform init code to use new
	mux code
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120727.2637.12658.stgit@baageli.muru.com>

Convert 2420 platform init code to use new mux code

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-apollon.c |   13 ++++++-------
 arch/arm/mach-omap2/board-h4.c      |    7 +++----
 arch/arm/mach-omap2/devices.c       |   25 ++++++++++++-------------
 arch/arm/mach-omap2/i2c.c           |   27 +++++++--------------------
 arch/arm/mach-omap2/mcbsp.c         |   13 +++++++------
 arch/arm/mach-omap2/usb-tusb6010.c  |   14 +++++++-------
 6 files changed, 42 insertions(+), 57 deletions(-)

diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index bc67026..8cea623 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -35,7 +35,6 @@
 
 #include <mach/gpio.h>
 #include <plat/led.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/common.h>
@@ -246,7 +245,7 @@ static inline void __init apollon_init_smc91x(void)
 	apollon_smc91x_resources[0].end   = base + 0x30f;
 	udelay(100);
 
-	omap_cfg_reg(W4__24XX_GPIO74);
+	omap_mux_init_gpio(74, 0);
 	if (gpio_request(APOLLON_ETHR_GPIO_IRQ, "SMC91x irq") < 0) {
 		printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n",
 			APOLLON_ETHR_GPIO_IRQ);
@@ -288,15 +287,15 @@ static void __init omap_apollon_init_irq(void)
 static void __init apollon_led_init(void)
 {
 	/* LED0 - AA10 */
-	omap_cfg_reg(AA10_242X_GPIO13);
+	omap_mux_init_signal("vlynq_clk.gpio_13", 0);
 	gpio_request(LED0_GPIO13, "LED0");
 	gpio_direction_output(LED0_GPIO13, 0);
 	/* LED1  - AA6 */
-	omap_cfg_reg(AA6_242X_GPIO14);
+	omap_mux_init_signal("vlynq_rx1.gpio_14", 0);
 	gpio_request(LED1_GPIO14, "LED1");
 	gpio_direction_output(LED1_GPIO14, 0);
 	/* LED2  - AA4 */
-	omap_cfg_reg(AA4_242X_GPIO15);
+	omap_mux_init_signal("vlynq_rx0.gpio_15", 0);
 	gpio_request(LED2_GPIO15, "LED2");
 	gpio_direction_output(LED2_GPIO15, 0);
 }
@@ -305,7 +304,7 @@ static void __init apollon_usb_init(void)
 {
 	/* USB device */
 	/* DEVICE_SUSPEND */
-	omap_cfg_reg(P21_242X_GPIO12);
+	omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
 	gpio_request(12, "USB suspend");
 	gpio_direction_output(12, 0);
 	omap2_usbfs_init(&apollon_usb_config);
@@ -330,7 +329,7 @@ static void __init omap_apollon_init(void)
 	apollon_usb_init();
 
 	/* REVISIT: where's the correct place */
-	omap_cfg_reg(W19_24XX_SYS_NIRQ);
+	omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP);
 
 	/* LCD PWR_EN */
 	omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index cdcd4fb..2d9ff0f 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -33,7 +33,6 @@
 
 #include <plat/control.h>
 #include <mach/gpio.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/common.h>
@@ -248,7 +247,7 @@ static inline void __init h4_init_debug(void)
 
 	udelay(100);
 
-	omap_cfg_reg(M15_24XX_GPIO92);
+	omap_mux_init_gpio(92, 0);
 	if (debug_card_init(cs_mem_base, H4_ETHR_GPIO_IRQ) < 0)
 		gpmc_cs_free(eth_cs);
 
@@ -358,8 +357,8 @@ static void __init omap_h4_init(void)
 	 * if not needed.
 	 */
 #if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
-	omap_cfg_reg(K15_24XX_UART3_TX);
-	omap_cfg_reg(K14_24XX_UART3_RX);
+	omap_mux_init_signal("uart3_tx_irtx.uart3_tx_irtx", 0);
+	omap_mux_init_signal("uart3_rx_irrx.uart3_rx_irrx", 0);
 #endif
 
 #if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 03e6c9e..3ae9d0a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -25,7 +25,6 @@
 #include <plat/control.h>
 #include <plat/tc.h>
 #include <plat/board.h>
-#include <plat/mux.h>
 #include <mach/gpio.h>
 #include <plat/mmc.h>
 #include <plat/dma.h>
@@ -672,19 +671,19 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
 					OMAP_PIN_INPUT_PULLUP);
 
 	if (cpu_is_omap2420() && controller_nr == 0) {
-		omap_cfg_reg(H18_24XX_MMC_CMD);
-		omap_cfg_reg(H15_24XX_MMC_CLKI);
-		omap_cfg_reg(G19_24XX_MMC_CLKO);
-		omap_cfg_reg(F20_24XX_MMC_DAT0);
-		omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
-		omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
+		omap_mux_init_signal("sdmmc_cmd", 0);
+		omap_mux_init_signal("sdmmc_clki", 0);
+		omap_mux_init_signal("sdmmc_clko", 0);
+		omap_mux_init_signal("sdmmc_dat0", 0);
+		omap_mux_init_signal("sdmmc_dat_dir0", 0);
+		omap_mux_init_signal("sdmmc_cmd_dir", 0);
 		if (mmc_controller->slots[0].wires == 4) {
-			omap_cfg_reg(H14_24XX_MMC_DAT1);
-			omap_cfg_reg(E19_24XX_MMC_DAT2);
-			omap_cfg_reg(D19_24XX_MMC_DAT3);
-			omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
-			omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
-			omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
+			omap_mux_init_signal("sdmmc_dat1", 0);
+			omap_mux_init_signal("sdmmc_dat2", 0);
+			omap_mux_init_signal("sdmmc_dat3", 0);
+			omap_mux_init_signal("sdmmc_dat_dir1", 0);
+			omap_mux_init_signal("sdmmc_dat_dir2", 0);
+			omap_mux_init_signal("sdmmc_dat_dir3", 0);
 		}
 
 		/*
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index 7951ae1..79c478c 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -21,32 +21,19 @@
 
 #include <plat/cpu.h>
 #include <plat/i2c.h>
-#include <plat/mux.h>
 
 #include "mux.h"
 
 void __init omap2_i2c_mux_pins(int bus_id)
 {
-	if (cpu_is_omap24xx()) {
-		const int omap24xx_pins[][2] = {
-			{ M19_24XX_I2C1_SCL, L15_24XX_I2C1_SDA },
-			{ J15_24XX_I2C2_SCL, H19_24XX_I2C2_SDA },
-		};
-		int scl, sda;
-
-		scl = omap24xx_pins[bus_id - 1][0];
-		sda = omap24xx_pins[bus_id - 1][1];
-		omap_cfg_reg(sda);
-		omap_cfg_reg(scl);
-	}
+	char mux_name[sizeof("i2c2_scl.i2c2_scl")];
 
 	/* First I2C bus is not muxable */
-	if (cpu_is_omap34xx() && bus_id > 1) {
-		char mux_name[sizeof("i2c2_scl.i2c2_scl")];
+	if (bus_id == 1)
+		return;
 
-		sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
-		omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
-		sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
-		omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
-	}
+	sprintf(mux_name, "i2c%i_scl.i2c%i_scl", bus_id, bus_id);
+	omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
+	sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
+	omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
 }
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index c293370..87aa4c9 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -20,17 +20,18 @@
 
 #include <mach/irqs.h>
 #include <plat/dma.h>
-#include <plat/mux.h>
 #include <plat/cpu.h>
 #include <plat/mcbsp.h>
 
+#include "mux.h"
+
 static void omap2_mcbsp2_mux_setup(void)
 {
-	omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
-	omap_cfg_reg(R14_24XX_MCBSP2_FSX);
-	omap_cfg_reg(W15_24XX_MCBSP2_DR);
-	omap_cfg_reg(V15_24XX_MCBSP2_DX);
-	omap_cfg_reg(V14_24XX_GPIO117);
+	omap_mux_init_signal("eac_ac_sclk.mcbsp2_clkx", OMAP_PULL_ENA);
+	omap_mux_init_signal("eac_ac_fs.mcbsp2_fsx", OMAP_PULL_ENA);
+	omap_mux_init_signal("eac_ac_din.mcbsp2_dr", OMAP_PULL_ENA);
+	omap_mux_init_signal("eac_ac_dout.mcbsp2_dx", OMAP_PULL_ENA);
+	omap_mux_init_gpio(117, OMAP_PULL_ENA);
 	/*
 	 * TODO: Need to add MUX settings for OMAP 2430 SDP
 	 */
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 10a2013..64a0112 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -17,8 +17,8 @@
 #include <linux/usb/musb.h>
 
 #include <plat/gpmc.h>
-#include <plat/mux.h>
 
+#include "mux.h"
 
 static u8		async_cs, sync_cs;
 static unsigned		refclk_psec;
@@ -325,17 +325,17 @@ tusb6010_setup_interface(struct musb_hdrc_platform_data *data,
 	else {
 		/* assume OMAP 2420 ES2.0 and later */
 		if (dmachan & (1 << 0))
-			omap_cfg_reg(AA10_242X_DMAREQ0);
+			omap_mux_init_signal("sys_ndmareq0", 0);
 		if (dmachan & (1 << 1))
-			omap_cfg_reg(AA6_242X_DMAREQ1);
+			omap_mux_init_signal("sys_ndmareq1", 0);
 		if (dmachan & (1 << 2))
-			omap_cfg_reg(E4_242X_DMAREQ2);
+			omap_mux_init_signal("sys_ndmareq2", 0);
 		if (dmachan & (1 << 3))
-			omap_cfg_reg(G4_242X_DMAREQ3);
+			omap_mux_init_signal("sys_ndmareq3", 0);
 		if (dmachan & (1 << 4))
-			omap_cfg_reg(D3_242X_DMAREQ4);
+			omap_mux_init_signal("sys_ndmareq4", 0);
 		if (dmachan & (1 << 5))
-			omap_cfg_reg(E3_242X_DMAREQ5);
+			omap_mux_init_signal("sys_ndmareq5", 0);
 	}
 
 	/* so far so good ... register the device */



From tony at atomide.com  Wed Jun 30 08:07:31 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:07:31 +0300
Subject: [PATCH 16/16] omap: mux: Remove old mux code
In-Reply-To: <20100630120226.2637.31198.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
Message-ID: <20100630120731.2637.92183.stgit@baageli.muru.com>

All mach-omap2 omaps should now use the new mux code.

Signed-off-by: Tony Lindgren <tony at atomide.com>
---
 arch/arm/mach-omap2/board-3630sdp.c          |    1 
 arch/arm/mach-omap2/board-generic.c          |    1 
 arch/arm/mach-omap2/board-rx51-peripherals.c |    1 
 arch/arm/mach-omap2/board-rx51-video.c       |    1 
 arch/arm/mach-omap2/io.c                     |    2 
 arch/arm/mach-omap2/mux.c                    |  298 --------------------------
 arch/arm/mach-omap2/pm24xx.c                 |    1 
 arch/arm/mach-omap2/usb-ehci.c               |    1 
 arch/arm/mach-omap2/usb-musb.c               |    1 
 arch/arm/plat-omap/include/plat/mux.h        |  220 -------------------
 arch/arm/plat-omap/mux.c                     |    2 
 11 files changed, 1 insertions(+), 528 deletions(-)

diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 504d2bd..f267dc0 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -18,7 +18,6 @@
 #include <plat/common.h>
 #include <plat/board.h>
 #include <plat/gpmc-smc91x.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 
 #include <mach/board-zoom.h>
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 16cc068..9a7f790 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -26,7 +26,6 @@
 #include <asm/mach/map.h>
 
 #include <mach/gpio.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/common.h>
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index abdf321..5ddf156 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -25,7 +25,6 @@
 #include <linux/mmc/host.h>
 
 #include <plat/mcspi.h>
-#include <plat/mux.h>
 #include <plat/board.h>
 #include <plat/common.h>
 #include <plat/dma.h>
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index b743a4f..5a1005b 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -16,7 +16,6 @@
 #include <linux/mm.h>
 
 #include <asm/mach-types.h>
-#include <plat/mux.h>
 #include <plat/display.h>
 #include <plat/vram.h>
 #include <plat/mcspi.h>
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3cfb425..b12d715 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -28,7 +28,6 @@
 
 #include <asm/mach/map.h>
 
-#include <plat/mux.h>
 #include <plat/sram.h>
 #include <plat/sdrc.h>
 #include <plat/gpmc.h>
@@ -324,7 +323,6 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
 		omap2430_hwmod_init();
 	else if (cpu_is_omap34xx())
 		omap3xxx_hwmod_init();
-	omap2_mux_init();
 	/* The OPP tables have to be registered before a clk init */
 	omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
 
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 197e295..be52fab 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -37,7 +37,6 @@
 #include <asm/system.h>
 
 #include <plat/control.h>
-#include <plat/mux.h>
 
 #include "mux.h"
 
@@ -78,301 +77,6 @@ void omap_mux_write_array(struct omap_board_mux *board_mux)
 	}
 }
 
-#if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_OMAP_MUX)
-
-static struct omap_mux_cfg arch_mux_cfg;
-
-/* NOTE: See mux.h for the enumeration */
-
-static struct pin_config __initdata_or_module omap24xx_pins[] = {
-/*
- *	description			mux	mux	pull	pull	debug
- *					offset	mode	ena	type
- */
-
-/* 24xx I2C */
-MUX_CFG_24XX("M19_24XX_I2C1_SCL",	0x111,	0,	0,	0,	1)
-MUX_CFG_24XX("L15_24XX_I2C1_SDA",	0x112,	0,	0,	0,	1)
-MUX_CFG_24XX("J15_24XX_I2C2_SCL",	0x113,	0,	0,	1,	1)
-MUX_CFG_24XX("H19_24XX_I2C2_SDA",	0x114,	0,	0,	0,	1)
-
-/* Menelaus interrupt */
-MUX_CFG_24XX("W19_24XX_SYS_NIRQ",	0x12c,	0,	1,	1,	1)
-
-/* 24xx clocks */
-MUX_CFG_24XX("W14_24XX_SYS_CLKOUT",	0x137,	0,	1,	1,	1)
-
-/* 24xx GPMC chipselects, wait pin monitoring */
-MUX_CFG_24XX("E2_GPMC_NCS2",		0x08e,	0,	1,	1,	1)
-MUX_CFG_24XX("L2_GPMC_NCS7",		0x093,	0,	1,	1,	1)
-MUX_CFG_24XX("L3_GPMC_WAIT0",		0x09a,	0,	1,	1,	1)
-MUX_CFG_24XX("N7_GPMC_WAIT1",		0x09b,	0,	1,	1,	1)
-MUX_CFG_24XX("M1_GPMC_WAIT2",		0x09c,	0,	1,	1,	1)
-MUX_CFG_24XX("P1_GPMC_WAIT3",		0x09d,	0,	1,	1,	1)
-
-/* 24xx McBSP */
-MUX_CFG_24XX("Y15_24XX_MCBSP2_CLKX",	0x124,	1,	1,	0,	1)
-MUX_CFG_24XX("R14_24XX_MCBSP2_FSX",	0x125,	1,	1,	0,	1)
-MUX_CFG_24XX("W15_24XX_MCBSP2_DR",	0x126,	1,	1,	0,	1)
-MUX_CFG_24XX("V15_24XX_MCBSP2_DX",	0x127,	1,	1,	0,	1)
-
-/* 24xx GPIO */
-MUX_CFG_24XX("M21_242X_GPIO11",		0x0c9,	3,	1,	1,	1)
-MUX_CFG_24XX("P21_242X_GPIO12",		0x0ca,	3,	0,	0,	1)
-MUX_CFG_24XX("AA10_242X_GPIO13",	0x0e5,	3,	0,	0,	1)
-MUX_CFG_24XX("AA6_242X_GPIO14",		0x0e6,	3,	0,	0,	1)
-MUX_CFG_24XX("AA4_242X_GPIO15",		0x0e7,	3,	0,	0,	1)
-MUX_CFG_24XX("Y11_242X_GPIO16",		0x0e8,	3,	0,	0,	1)
-MUX_CFG_24XX("AA12_242X_GPIO17",	0x0e9,	3,	0,	0,	1)
-MUX_CFG_24XX("AA8_242X_GPIO58",		0x0ea,	3,	0,	0,	1)
-MUX_CFG_24XX("Y20_24XX_GPIO60",		0x12c,	3,	0,	0,	1)
-MUX_CFG_24XX("W4__24XX_GPIO74",		0x0f2,	3,	0,	0,	1)
-MUX_CFG_24XX("N15_24XX_GPIO85",		0x103,	3,	0,	0,	1)
-MUX_CFG_24XX("M15_24XX_GPIO92",		0x10a,	3,	0,	0,	1)
-MUX_CFG_24XX("P20_24XX_GPIO93",		0x10b,	3,	0,	0,	1)
-MUX_CFG_24XX("P18_24XX_GPIO95",		0x10d,	3,	0,	0,	1)
-MUX_CFG_24XX("M18_24XX_GPIO96",		0x10e,	3,	0,	0,	1)
-MUX_CFG_24XX("L14_24XX_GPIO97",		0x10f,	3,	0,	0,	1)
-MUX_CFG_24XX("J15_24XX_GPIO99",		0x113,	3,	1,	1,	1)
-MUX_CFG_24XX("V14_24XX_GPIO117",	0x128,	3,	1,	0,	1)
-MUX_CFG_24XX("P14_24XX_GPIO125",	0x140,	3,	1,	1,	1)
-
-/* 242x DBG GPIO */
-MUX_CFG_24XX("V4_242X_GPIO49",		0xd3,	3,	0,	0,	1)
-MUX_CFG_24XX("W2_242X_GPIO50",		0xd4,	3,	0,	0,	1)
-MUX_CFG_24XX("U4_242X_GPIO51",		0xd5,	3,	0,	0,	1)
-MUX_CFG_24XX("V3_242X_GPIO52",		0xd6,	3,	0,	0,	1)
-MUX_CFG_24XX("V2_242X_GPIO53",		0xd7,	3,	0,	0,	1)
-MUX_CFG_24XX("V6_242X_GPIO53",		0xcf,	3,	0,	0,	1)
-MUX_CFG_24XX("T4_242X_GPIO54",		0xd8,	3,	0,	0,	1)
-MUX_CFG_24XX("Y4_242X_GPIO54",		0xd0,	3,	0,	0,	1)
-MUX_CFG_24XX("T3_242X_GPIO55",		0xd9,	3,	0,	0,	1)
-MUX_CFG_24XX("U2_242X_GPIO56",		0xda,	3,	0,	0,	1)
-
-/* 24xx external DMA requests */
-MUX_CFG_24XX("AA10_242X_DMAREQ0",	0x0e5,	2,	0,	0,	1)
-MUX_CFG_24XX("AA6_242X_DMAREQ1",	0x0e6,	2,	0,	0,	1)
-MUX_CFG_24XX("E4_242X_DMAREQ2",		0x074,	2,	0,	0,	1)
-MUX_CFG_24XX("G4_242X_DMAREQ3",		0x073,	2,	0,	0,	1)
-MUX_CFG_24XX("D3_242X_DMAREQ4",		0x072,	2,	0,	0,	1)
-MUX_CFG_24XX("E3_242X_DMAREQ5",		0x071,	2,	0,	0,	1)
-
-/* UART3 */
-MUX_CFG_24XX("K15_24XX_UART3_TX",	0x118,	0,	0,	0,	1)
-MUX_CFG_24XX("K14_24XX_UART3_RX",	0x119,	0,	0,	0,	1)
-
-/* MMC/SDIO */
-MUX_CFG_24XX("G19_24XX_MMC_CLKO",	0x0f3,	0,	0,	0,	1)
-MUX_CFG_24XX("H18_24XX_MMC_CMD",	0x0f4,	0,	0,	0,	1)
-MUX_CFG_24XX("F20_24XX_MMC_DAT0",	0x0f5,	0,	0,	0,	1)
-MUX_CFG_24XX("H14_24XX_MMC_DAT1",	0x0f6,	0,	0,	0,	1)
-MUX_CFG_24XX("E19_24XX_MMC_DAT2",	0x0f7,	0,	0,	0,	1)
-MUX_CFG_24XX("D19_24XX_MMC_DAT3",	0x0f8,	0,	0,	0,	1)
-MUX_CFG_24XX("F19_24XX_MMC_DAT_DIR0",	0x0f9,	0,	0,	0,	1)
-MUX_CFG_24XX("E20_24XX_MMC_DAT_DIR1",	0x0fa,	0,	0,	0,	1)
-MUX_CFG_24XX("F18_24XX_MMC_DAT_DIR2",	0x0fb,	0,	0,	0,	1)
-MUX_CFG_24XX("E18_24XX_MMC_DAT_DIR3",	0x0fc,	0,	0,	0,	1)
-MUX_CFG_24XX("G18_24XX_MMC_CMD_DIR",	0x0fd,	0,	0,	0,	1)
-MUX_CFG_24XX("H15_24XX_MMC_CLKI",	0x0fe,	0,	0,	0,	1)
-
-/* Full speed USB */
-MUX_CFG_24XX("J20_24XX_USB0_PUEN",	0x11d,	0,	0,	0,	1)
-MUX_CFG_24XX("J19_24XX_USB0_VP",	0x11e,	0,	0,	0,	1)
-MUX_CFG_24XX("K20_24XX_USB0_VM",	0x11f,	0,	0,	0,	1)
-MUX_CFG_24XX("J18_24XX_USB0_RCV",	0x120,	0,	0,	0,	1)
-MUX_CFG_24XX("K19_24XX_USB0_TXEN",	0x121,	0,	0,	0,	1)
-MUX_CFG_24XX("J14_24XX_USB0_SE0",	0x122,	0,	0,	0,	1)
-MUX_CFG_24XX("K18_24XX_USB0_DAT",	0x123,	0,	0,	0,	1)
-
-MUX_CFG_24XX("N14_24XX_USB1_SE0",	0x0ed,	2,	0,	0,	1)
-MUX_CFG_24XX("W12_24XX_USB1_SE0",	0x0dd,	3,	0,	0,	1)
-MUX_CFG_24XX("P15_24XX_USB1_DAT",	0x0ee,	2,	0,	0,	1)
-MUX_CFG_24XX("R13_24XX_USB1_DAT",	0x0e0,	3,	0,	0,	1)
-MUX_CFG_24XX("W20_24XX_USB1_TXEN",	0x0ec,	2,	0,	0,	1)
-MUX_CFG_24XX("P13_24XX_USB1_TXEN",	0x0df,	3,	0,	0,	1)
-MUX_CFG_24XX("V19_24XX_USB1_RCV",	0x0eb,	2,	0,	0,	1)
-MUX_CFG_24XX("V12_24XX_USB1_RCV",	0x0de,	3,	0,	0,	1)
-
-MUX_CFG_24XX("AA10_24XX_USB2_SE0",	0x0e5,	2,	0,	0,	1)
-MUX_CFG_24XX("Y11_24XX_USB2_DAT",	0x0e8,	2,	0,	0,	1)
-MUX_CFG_24XX("AA12_24XX_USB2_TXEN",	0x0e9,	2,	0,	0,	1)
-MUX_CFG_24XX("AA6_24XX_USB2_RCV",	0x0e6,	2,	0,	0,	1)
-MUX_CFG_24XX("AA4_24XX_USB2_TLLSE0",	0x0e7,	2,	0,	0,	1)
-
-/* Keypad GPIO*/
-MUX_CFG_24XX("T19_24XX_KBR0",		0x106,	3,	1,	1,	1)
-MUX_CFG_24XX("R19_24XX_KBR1",		0x107,	3,	1,	1,	1)
-MUX_CFG_24XX("V18_24XX_KBR2",		0x139,	3,	1,	1,	1)
-MUX_CFG_24XX("M21_24XX_KBR3",		0xc9,	3,	1,	1,	1)
-MUX_CFG_24XX("E5__24XX_KBR4",		0x138,	3,	1,	1,	1)
-MUX_CFG_24XX("M18_24XX_KBR5",		0x10e,	3,	1,	1,	1)
-MUX_CFG_24XX("R20_24XX_KBC0",		0x108,	3,	0,	0,	1)
-MUX_CFG_24XX("M14_24XX_KBC1",		0x109,	3,	0,	0,	1)
-MUX_CFG_24XX("H19_24XX_KBC2",		0x114,	3,	0,	0,	1)
-MUX_CFG_24XX("V17_24XX_KBC3",		0x135,	3,	0,	0,	1)
-MUX_CFG_24XX("P21_24XX_KBC4",		0xca,	3,	0,	0,	1)
-MUX_CFG_24XX("L14_24XX_KBC5",		0x10f,	3,	0,	0,	1)
-MUX_CFG_24XX("N19_24XX_KBC6",		0x110,	3,	0,	0,	1)
-
-/* 24xx Menelaus Keypad GPIO */
-MUX_CFG_24XX("B3__24XX_KBR5",		0x30,	3,	1,	1,	1)
-MUX_CFG_24XX("AA4_24XX_KBC2",		0xe7,	3,	0,	0,	1)
-MUX_CFG_24XX("B13_24XX_KBC6",		0x110,	3,	0,	0,	1)
-
-/* 2430 USB */
-MUX_CFG_24XX("AD9_2430_USB0_PUEN",	0x133,	4,	0,	0,	1)
-MUX_CFG_24XX("Y11_2430_USB0_VP",	0x134,	4,	0,	0,	1)
-MUX_CFG_24XX("AD7_2430_USB0_VM",	0x135,	4,	0,	0,	1)
-MUX_CFG_24XX("AE7_2430_USB0_RCV",	0x136,	4,	0,	0,	1)
-MUX_CFG_24XX("AD4_2430_USB0_TXEN",	0x137,	4,	0,	0,	1)
-MUX_CFG_24XX("AF9_2430_USB0_SE0",	0x138,	4,	0,	0,	1)
-MUX_CFG_24XX("AE6_2430_USB0_DAT",	0x139,	4,	0,	0,	1)
-MUX_CFG_24XX("AD24_2430_USB1_SE0",	0x107,	2,	0,	0,	1)
-MUX_CFG_24XX("AB24_2430_USB1_RCV",	0x108,	2,	0,	0,	1)
-MUX_CFG_24XX("Y25_2430_USB1_TXEN",	0x109,	2,	0,	0,	1)
-MUX_CFG_24XX("AA26_2430_USB1_DAT",	0x10A,	2,	0,	0,	1)
-
-/* 2430 HS-USB */
-MUX_CFG_24XX("AD9_2430_USB0HS_DATA3",	0x133,	0,	0,	0,	1)
-MUX_CFG_24XX("Y11_2430_USB0HS_DATA4",	0x134,	0,	0,	0,	1)
-MUX_CFG_24XX("AD7_2430_USB0HS_DATA5",	0x135,	0,	0,	0,	1)
-MUX_CFG_24XX("AE7_2430_USB0HS_DATA6",	0x136,	0,	0,	0,	1)
-MUX_CFG_24XX("AD4_2430_USB0HS_DATA2",	0x137,	0,	0,	0,	1)
-MUX_CFG_24XX("AF9_2430_USB0HS_DATA0",	0x138,	0,	0,	0,	1)
-MUX_CFG_24XX("AE6_2430_USB0HS_DATA1",	0x139,	0,	0,	0,	1)
-MUX_CFG_24XX("AE8_2430_USB0HS_CLK",	0x13A,	0,	0,	0,	1)
-MUX_CFG_24XX("AD8_2430_USB0HS_DIR",	0x13B,	0,	0,	0,	1)
-MUX_CFG_24XX("AE5_2430_USB0HS_STP",	0x13c,	0,	1,	1,	1)
-MUX_CFG_24XX("AE9_2430_USB0HS_NXT",	0x13D,	0,	0,	0,	1)
-MUX_CFG_24XX("AC7_2430_USB0HS_DATA7",	0x13E,	0,	0,	0,	1)
-
-/* 2430 McBSP */
-MUX_CFG_24XX("AD6_2430_MCBSP_CLKS",	0x011E,	0,	0,	0,	1)
-
-MUX_CFG_24XX("AB2_2430_MCBSP1_CLKR",	0x011A,	0,	0,	0,	1)
-MUX_CFG_24XX("AD5_2430_MCBSP1_FSR",	0x011B,	0,	0,	0,	1)
-MUX_CFG_24XX("AA1_2430_MCBSP1_DX",	0x011C,	0,	0,	0,	1)
-MUX_CFG_24XX("AF3_2430_MCBSP1_DR",	0x011D,	0,	0,	0,	1)
-MUX_CFG_24XX("AB3_2430_MCBSP1_FSX",	0x011F,	0,	0,	0,	1)
-MUX_CFG_24XX("Y9_2430_MCBSP1_CLKX",	0x0120,	0,	0,	0,	1)
-
-MUX_CFG_24XX("AC10_2430_MCBSP2_FSX",	0x012E,	1,	0,	0,	1)
-MUX_CFG_24XX("AD16_2430_MCBSP2_CLX",	0x012F,	1,	0,	0,	1)
-MUX_CFG_24XX("AE13_2430_MCBSP2_DX",	0x0130,	1,	0,	0,	1)
-MUX_CFG_24XX("AD13_2430_MCBSP2_DR",	0x0131,	1,	0,	0,	1)
-MUX_CFG_24XX("AC10_2430_MCBSP2_FSX_OFF",0x012E,	0,	0,	0,	1)
-MUX_CFG_24XX("AD16_2430_MCBSP2_CLX_OFF",0x012F,	0,	0,	0,	1)
-MUX_CFG_24XX("AE13_2430_MCBSP2_DX_OFF",	0x0130,	0,	0,	0,	1)
-MUX_CFG_24XX("AD13_2430_MCBSP2_DR_OFF",	0x0131,	0,	0,	0,	1)
-
-MUX_CFG_24XX("AC9_2430_MCBSP3_CLKX",	0x0103,	0,	0,	0,	1)
-MUX_CFG_24XX("AE4_2430_MCBSP3_FSX",	0x0104,	0,	0,	0,	1)
-MUX_CFG_24XX("AE2_2430_MCBSP3_DR",	0x0105,	0,	0,	0,	1)
-MUX_CFG_24XX("AF4_2430_MCBSP3_DX",	0x0106,	0,	0,	0,	1)
-
-MUX_CFG_24XX("N3_2430_MCBSP4_CLKX",	0x010B,	1,	0,	0,	1)
-MUX_CFG_24XX("AD23_2430_MCBSP4_DR",	0x010C,	1,	0,	0,	1)
-MUX_CFG_24XX("AB25_2430_MCBSP4_DX",	0x010D,	1,	0,	0,	1)
-MUX_CFG_24XX("AC25_2430_MCBSP4_FSX",	0x010E,	1,	0,	0,	1)
-
-MUX_CFG_24XX("AE16_2430_MCBSP5_CLKX",	0x00ED,	1,	0,	0,	1)
-MUX_CFG_24XX("AF12_2430_MCBSP5_FSX",	0x00ED,	1,	0,	0,	1)
-MUX_CFG_24XX("K7_2430_MCBSP5_DX",	0x00EF,	1,	0,	0,	1)
-MUX_CFG_24XX("M1_2430_MCBSP5_DR",	0x00F0,	1,	0,	0,	1)
-
-/* 2430 MCSPI1 */
-MUX_CFG_24XX("Y18_2430_MCSPI1_CLK",	0x010F,	0,	0,	0,	1)
-MUX_CFG_24XX("AD15_2430_MCSPI1_SIMO",	0x0110,	0,	0,	0,	1)
-MUX_CFG_24XX("AE17_2430_MCSPI1_SOMI",	0x0111,	0,	0,	0,	1)
-MUX_CFG_24XX("U1_2430_MCSPI1_CS0",	0x0112,	0,	0,	0,	1)
-
-/* Touchscreen GPIO */
-MUX_CFG_24XX("AF19_2430_GPIO_85",	0x0113,	3,	0,	0,	1)
-
-};
-
-#define OMAP24XX_PINS_SZ	ARRAY_SIZE(omap24xx_pins)
-
-#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
-
-static void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u16 reg)
-{
-	u16 orig;
-	u8 warn = 0, debug = 0;
-
-	orig = omap_mux_read(cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
-
-#ifdef	CONFIG_OMAP_MUX_DEBUG
-	debug = cfg->debug;
-#endif
-	warn = (orig != reg);
-	if (debug || warn)
-		printk(KERN_WARNING
-			"MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n",
-			cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
-			orig, reg);
-}
-#else
-#define omap2_cfg_debug(x, y)	do {} while (0)
-#endif
-
-static int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
-{
-	static DEFINE_SPINLOCK(mux_spin_lock);
-	unsigned long flags;
-	u8 reg = 0;
-
-	spin_lock_irqsave(&mux_spin_lock, flags);
-	reg |= cfg->mask & 0x7;
-	if (cfg->pull_val)
-		reg |= OMAP2_PULL_ENA;
-	if (cfg->pu_pd_val)
-		reg |= OMAP2_PULL_UP;
-	omap2_cfg_debug(cfg, reg);
-	omap_mux_write(reg, cfg->mux_reg - OMAP_MUX_BASE_OFFSET);
-	spin_unlock_irqrestore(&mux_spin_lock, flags);
-
-	return 0;
-}
-
-int __init omap2_mux_init(void)
-{
-	u32 mux_pbase;
-
-	if (cpu_is_omap2420())
-		mux_pbase = OMAP2420_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
-	else if (cpu_is_omap2430())
-		mux_pbase = OMAP243X_CTRL_BASE + OMAP_MUX_BASE_OFFSET;
-	else
-		return -ENODEV;
-
-	mux_base = ioremap(mux_pbase, OMAP_MUX_BASE_SZ);
-	if (!mux_base) {
-		printk(KERN_ERR "mux: Could not ioremap\n");
-		return -ENODEV;
-	}
-
-	if (cpu_is_omap24xx()) {
-		arch_mux_cfg.pins	= omap24xx_pins;
-		arch_mux_cfg.size	= OMAP24XX_PINS_SZ;
-		arch_mux_cfg.cfg_reg	= omap24xx_cfg_reg;
-
-		return omap_mux_register(&arch_mux_cfg);
-	}
-
-	return 0;
-}
-
-#else
-int __init omap2_mux_init(void)
-{
-	return 0;
-}
-#endif	/* CONFIG_OMAP_MUX */
-
-/*----------------------------------------------------------------------------*/
-
-#ifdef CONFIG_ARCH_OMAP2PLUS
 static LIST_HEAD(muxmodes);
 static DEFINE_MUTEX(muxmode_mutex);
 
@@ -1047,5 +751,3 @@ int __init omap_mux_init(u32 mux_pbase, u32 mux_size,
 	return 0;
 }
 
-#endif	/* CONFIG_ARCH_OMAP3 */
-
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index e321281..6aeedea 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -39,7 +39,6 @@
 #include <plat/clock.h>
 #include <plat/sram.h>
 #include <plat/control.h>
-#include <plat/mux.h>
 #include <plat/dma.h>
 #include <plat/board.h>
 
diff --git a/arch/arm/mach-omap2/usb-ehci.c b/arch/arm/mach-omap2/usb-ehci.c
index d72d1ac..b11bf38 100644
--- a/arch/arm/mach-omap2/usb-ehci.c
+++ b/arch/arm/mach-omap2/usb-ehci.c
@@ -23,7 +23,6 @@
 #include <linux/dma-mapping.h>
 
 #include <asm/io.h>
-#include <plat/mux.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index 96f6787..33a5cde 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -28,7 +28,6 @@
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <plat/mux.h>
 #include <plat/usb.h>
 
 #ifdef CONFIG_USB_MUSB_SOC
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index c7472a2..e1da7b1 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -114,28 +114,11 @@
 	PU_PD_REG(NA, 0)		\
 },
 
-#define MUX_CFG_24XX(desc, reg_offset, mode,			\
-				pull_en, pull_mode, dbg)	\
-{								\
-	.name		= desc,					\
-	.debug		= dbg,					\
-	.mux_reg	= reg_offset,				\
-	.mask		= mode,					\
-	.pull_val	= pull_en,				\
-	.pu_pd_val	= pull_mode,				\
-},
-
-/* 24xx/34xx mux bit defines */
-#define OMAP2_PULL_ENA		(1 << 3)
-#define OMAP2_PULL_UP		(1 << 4)
-#define OMAP2_ALTELECTRICALSEL	(1 << 5)
-
 struct pin_config {
 	char 			*name;
 	const unsigned int 	mux_reg;
 	unsigned char		debug;
 
-#if	defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2)
 	const unsigned char mask_offset;
 	const unsigned char mask;
 
@@ -147,7 +130,6 @@ struct pin_config {
 	const char *pu_pd_name;
 	const unsigned int pu_pd_reg;
 	const unsigned char pu_pd_val;
-#endif
 
 #if	defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
 	const char *mux_reg_name;
@@ -446,208 +428,6 @@ enum omap1xxx_index {
 
 };
 
-enum omap24xx_index {
-	/* 24xx I2C */
-	M19_24XX_I2C1_SCL,
-	L15_24XX_I2C1_SDA,
-	J15_24XX_I2C2_SCL,
-	H19_24XX_I2C2_SDA,
-
-	/* 24xx Menelaus interrupt */
-	W19_24XX_SYS_NIRQ,
-
-	/* 24xx clock */
-	W14_24XX_SYS_CLKOUT,
-
-	/* 24xx GPMC chipselects, wait pin monitoring */
-	E2_GPMC_NCS2,
-	L2_GPMC_NCS7,
-	L3_GPMC_WAIT0,
-	N7_GPMC_WAIT1,
-	M1_GPMC_WAIT2,
-	P1_GPMC_WAIT3,
-
-	/* 242X McBSP */
-	Y15_24XX_MCBSP2_CLKX,
-	R14_24XX_MCBSP2_FSX,
-	W15_24XX_MCBSP2_DR,
-	V15_24XX_MCBSP2_DX,
-
-	/* 24xx GPIO */
-	M21_242X_GPIO11,
-	P21_242X_GPIO12,
-	AA10_242X_GPIO13,
-	AA6_242X_GPIO14,
-	AA4_242X_GPIO15,
-	Y11_242X_GPIO16,
-	AA12_242X_GPIO17,
-	AA8_242X_GPIO58,
-	Y20_24XX_GPIO60,
-	W4__24XX_GPIO74,
-	N15_24XX_GPIO85,
-	M15_24XX_GPIO92,
-	P20_24XX_GPIO93,
-	P18_24XX_GPIO95,
-	M18_24XX_GPIO96,
-	L14_24XX_GPIO97,
-	J15_24XX_GPIO99,
-	V14_24XX_GPIO117,
-	P14_24XX_GPIO125,
-
-	/* 242x DBG GPIO */
-	V4_242X_GPIO49,
-	W2_242X_GPIO50,
-	U4_242X_GPIO51,
-	V3_242X_GPIO52,
-	V2_242X_GPIO53,
-	V6_242X_GPIO53,
-	T4_242X_GPIO54,
-	Y4_242X_GPIO54,
-	T3_242X_GPIO55,
-	U2_242X_GPIO56,
-
-	/* 24xx external DMA requests */
-	AA10_242X_DMAREQ0,
-	AA6_242X_DMAREQ1,
-	E4_242X_DMAREQ2,
-	G4_242X_DMAREQ3,
-	D3_242X_DMAREQ4,
-	E3_242X_DMAREQ5,
-
-	/* UART3 */
-	K15_24XX_UART3_TX,
-	K14_24XX_UART3_RX,
-
-	/* MMC/SDIO */
-	G19_24XX_MMC_CLKO,
-	H18_24XX_MMC_CMD,
-	F20_24XX_MMC_DAT0,
-	H14_24XX_MMC_DAT1,
-	E19_24XX_MMC_DAT2,
-	D19_24XX_MMC_DAT3,
-	F19_24XX_MMC_DAT_DIR0,
-	E20_24XX_MMC_DAT_DIR1,
-	F18_24XX_MMC_DAT_DIR2,
-	E18_24XX_MMC_DAT_DIR3,
-	G18_24XX_MMC_CMD_DIR,
-	H15_24XX_MMC_CLKI,
-
-	/* Full speed USB */
-	J20_24XX_USB0_PUEN,
-	J19_24XX_USB0_VP,
-	K20_24XX_USB0_VM,
-	J18_24XX_USB0_RCV,
-	K19_24XX_USB0_TXEN,
-	J14_24XX_USB0_SE0,
-	K18_24XX_USB0_DAT,
-
-	N14_24XX_USB1_SE0,
-	W12_24XX_USB1_SE0,
-	P15_24XX_USB1_DAT,
-	R13_24XX_USB1_DAT,
-	W20_24XX_USB1_TXEN,
-	P13_24XX_USB1_TXEN,
-	V19_24XX_USB1_RCV,
-	V12_24XX_USB1_RCV,
-
-	AA10_24XX_USB2_SE0,
-	Y11_24XX_USB2_DAT,
-	AA12_24XX_USB2_TXEN,
-	AA6_24XX_USB2_RCV,
-	AA4_24XX_USB2_TLLSE0,
-
-	/* Keypad GPIO*/
-	T19_24XX_KBR0,
-	R19_24XX_KBR1,
-	V18_24XX_KBR2,
-	M21_24XX_KBR3,
-	E5__24XX_KBR4,
-	M18_24XX_KBR5,
-	R20_24XX_KBC0,
-	M14_24XX_KBC1,
-	H19_24XX_KBC2,
-	V17_24XX_KBC3,
-	P21_24XX_KBC4,
-	L14_24XX_KBC5,
-	N19_24XX_KBC6,
-
-	/* 24xx Menelaus Keypad GPIO */
-	B3__24XX_KBR5,
-	AA4_24XX_KBC2,
-	B13_24XX_KBC6,
-
-	/* 2430 USB */
-	AD9_2430_USB0_PUEN,
-	Y11_2430_USB0_VP,
-	AD7_2430_USB0_VM,
-	AE7_2430_USB0_RCV,
-	AD4_2430_USB0_TXEN,
-	AF9_2430_USB0_SE0,
-	AE6_2430_USB0_DAT,
-	AD24_2430_USB1_SE0,
-	AB24_2430_USB1_RCV,
-	Y25_2430_USB1_TXEN,
-	AA26_2430_USB1_DAT,
-
-	/* 2430 HS-USB */
-	AD9_2430_USB0HS_DATA3,
-	Y11_2430_USB0HS_DATA4,
-	AD7_2430_USB0HS_DATA5,
-	AE7_2430_USB0HS_DATA6,
-	AD4_2430_USB0HS_DATA2,
-	AF9_2430_USB0HS_DATA0,
-	AE6_2430_USB0HS_DATA1,
-	AE8_2430_USB0HS_CLK,
-	AD8_2430_USB0HS_DIR,
-	AE5_2430_USB0HS_STP,
-	AE9_2430_USB0HS_NXT,
-	AC7_2430_USB0HS_DATA7,
-
-	/* 2430 McBSP */
-	AD6_2430_MCBSP_CLKS,
-
-	AB2_2430_MCBSP1_CLKR,
-	AD5_2430_MCBSP1_FSR,
-	AA1_2430_MCBSP1_DX,
-	AF3_2430_MCBSP1_DR,
-	AB3_2430_MCBSP1_FSX,
-	Y9_2430_MCBSP1_CLKX,
-
-	AC10_2430_MCBSP2_FSX,
-	AD16_2430_MCBSP2_CLX,
-	AE13_2430_MCBSP2_DX,
-	AD13_2430_MCBSP2_DR,
-	AC10_2430_MCBSP2_FSX_OFF,
-	AD16_2430_MCBSP2_CLX_OFF,
-	AE13_2430_MCBSP2_DX_OFF,
-	AD13_2430_MCBSP2_DR_OFF,
-
-	AC9_2430_MCBSP3_CLKX,
-	AE4_2430_MCBSP3_FSX,
-	AE2_2430_MCBSP3_DR,
-	AF4_2430_MCBSP3_DX,
-
-	N3_2430_MCBSP4_CLKX,
-	AD23_2430_MCBSP4_DR,
-	AB25_2430_MCBSP4_DX,
-	AC25_2430_MCBSP4_FSX,
-
-	AE16_2430_MCBSP5_CLKX,
-	AF12_2430_MCBSP5_FSX,
-	K7_2430_MCBSP5_DX,
-	M1_2430_MCBSP5_DR,
-
-	/* 2430 McSPI*/
-	Y18_2430_MCSPI1_CLK,
-	AD15_2430_MCSPI1_SIMO,
-	AE17_2430_MCSPI1_SOMI,
-	U1_2430_MCSPI1_CS0,
-
-	/* Touchscreen GPIO */
-	AF19_2430_GPIO_85,
-
-};
-
 struct omap_mux_cfg {
 	struct pin_config	*pins;
 	unsigned long		size;
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index 0670363..0d4aa0d 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -54,7 +54,7 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
 {
 	struct pin_config *reg;
 
-	if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+	if (!cpu_class_is_omap1()) {
 		printk(KERN_ERR "mux: Broken omap_cfg_reg(%lu) entry\n",
 				index);
 		WARN_ON(1);



From felipe.balbi at nokia.com  Wed Jun 30 08:28:11 2010
From: felipe.balbi at nokia.com (Felipe Balbi)
Date: Wed, 30 Jun 2010 15:28:11 +0300
Subject: [PATCH 14/16] omap: mux: Mux 2430 USB0HS_STP in board-2430.c
In-Reply-To: <20100630120723.2637.54397.stgit@baageli.muru.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
	<20100630120723.2637.54397.stgit@baageli.muru.com>
Message-ID: <20100630122811.GR3843@nokia.com>

hi,

On Wed, Jun 30, 2010 at 02:07:23PM +0200, ext Tony Lindgren wrote:
>diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
>index e06d65e..5f04d3f 100644
>--- a/drivers/usb/musb/omap2430.c
>+++ b/drivers/usb/musb/omap2430.c
>@@ -194,10 +194,6 @@ int __init musb_platform_init(struct musb *musb, void *board_data)
> 	u32 l;
> 	struct omap_musb_board_data *data = board_data;
>
>-#if defined(CONFIG_ARCH_OMAP2430)
>-	omap_cfg_reg(AE5_2430_USB0HS_STP);
>-#endif

there's a patch from Anand taking care of this hunk, could you send only 
the hunk on board-2430sdp.c ?

this part on omap2430.c will go on next merge window.

-- 
balbi

DefectiveByDesign.org


From tony at atomide.com  Wed Jun 30 08:40:12 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 15:40:12 +0300
Subject: [PATCH 14/16] omap: mux: Mux 2430 USB0HS_STP in board-2430.c
In-Reply-To: <20100630122811.GR3843@nokia.com>
References: <20100630120226.2637.31198.stgit@baageli.muru.com>
	<20100630120723.2637.54397.stgit@baageli.muru.com>
	<20100630122811.GR3843@nokia.com>
Message-ID: <20100630124012.GE2822@atomide.com>

* Felipe Balbi <felipe.balbi at nokia.com> [100630 15:26]:
> hi,
> 
> On Wed, Jun 30, 2010 at 02:07:23PM +0200, ext Tony Lindgren wrote:
> >diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
> >index e06d65e..5f04d3f 100644
> >--- a/drivers/usb/musb/omap2430.c
> >+++ b/drivers/usb/musb/omap2430.c
> >@@ -194,10 +194,6 @@ int __init musb_platform_init(struct musb *musb, void *board_data)
> >	u32 l;
> >	struct omap_musb_board_data *data = board_data;
> >
> >-#if defined(CONFIG_ARCH_OMAP2430)
> >-	omap_cfg_reg(AE5_2430_USB0HS_STP);
> >-#endif
> 
> there's a patch from Anand taking care of this hunk, could you send
> only the hunk on board-2430sdp.c ?
> 
> this part on omap2430.c will go on next merge window.

OK, updated patch below.

Regards,

Tony
-------------- next part --------------
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From will.deacon at arm.com  Wed Jun 30 08:49:35 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 30 Jun 2010 13:49:35 +0100
Subject: [PATCH] Versatile Express: add support for local timers on CA9X4
	daughterboard
In-Reply-To: <1275904430-15995-1-git-send-email-will.deacon@arm.com>
References: <1275904430-15995-1-git-send-email-will.deacon@arm.com>
Message-ID: <003801cb1852$b1e91ae0$15bb50a0$@deacon@arm.com>

Hi Russell,

> [PATCH] Versatile Express: add support for local timers on CA9X4 daughterboard
> 
> This patch adds support for the Cortex-A9 local timers available when
> using the CA9X4 daughterboard with the Versatile Express.
> 
> Cc: Russell King - ARM Linux <linux at arm.linux.org.uk>
> Reviewed-by: Catalin Marinas <catalin.marinas at arm.com>
> Signed-off-by: Will Deacon <will.deacon at arm.com>
> ---
>  arch/arm/Kconfig                               |    5 +++--
>  arch/arm/mach-vexpress/ct-ca9x4.c              |   14 ++++++++------
>  arch/arm/mach-vexpress/include/mach/ct-ca9x4.h |    1 +
>  3 files changed, 12 insertions(+), 8 deletions(-)
> 

Do you have any objections to this patch, or can I submit it to
the patch system please? There are some timer init functions
in ct-ca9x4.c that are commented out so I'd like to make sure
I'm not interfering with any future plans.

Thanks,

Will




From kgene.kim at samsung.com  Wed Jun 30 08:59:09 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 30 Jun 2010 21:59:09 +0900
Subject: [PATCH] ARM: SAMSUNG: Implement set_name function for ADC devices
Message-ID: <1277902749-12882-1-git-send-email-kgene.kim@samsung.com>

From: Naveen Krishna Ch <ch.naveen at samsung.com>

This patch implements s3c_adc_setname() for Samsung SoCs.
Also updates its usage in S3C64XX, S5P6440, and S5PV210.

Signed-off-by: Naveen Krishna Ch <ch.naveen at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s3c64xx/s3c6410.c               |    4 +-
 arch/arm/mach-s5p6440/cpu.c                   |    3 +-
 arch/arm/mach-s5pv210/cpu.c                   |    7 ++---
 arch/arm/plat-samsung/include/plat/adc-core.h |   28 +++++++++++++++++++++++++
 4 files changed, 35 insertions(+), 7 deletions(-)
 create mode 100644 arch/arm/plat-samsung/include/plat/adc-core.h

diff --git a/arch/arm/mach-s3c64xx/s3c6410.c b/arch/arm/mach-s3c64xx/s3c6410.c
index 014401c..2b29ac0 100644
--- a/arch/arm/mach-s3c64xx/s3c6410.c
+++ b/arch/arm/mach-s3c64xx/s3c6410.c
@@ -37,8 +37,8 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
 #include <plat/sdhci.h>
+#include <plat/adc-core.h>
 #include <plat/iic-core.h>
-#include <plat/adc.h>
 #include <plat/onenand-core.h>
 #include <mach/s3c6400.h>
 #include <mach/s3c6410.h>
@@ -54,7 +54,7 @@ void __init s3c6410_map_io(void)
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
 
-	s3c_device_adc.name	= "s3c64xx-adc";
+	s3c_adc_setname("s3c64xx-adc");
 	s3c_device_nand.name = "s3c6400-nand";
 	s3c_onenand_setname("s3c6410-onenand");
 	s3c64xx_onenand1_setname("s3c6410-onenand");
diff --git a/arch/arm/mach-s5p6440/cpu.c b/arch/arm/mach-s5p6440/cpu.c
index b2fe6a5..526f33a 100644
--- a/arch/arm/mach-s5p6440/cpu.c
+++ b/arch/arm/mach-s5p6440/cpu.c
@@ -37,6 +37,7 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
 #include <plat/s5p6440.h>
+#include <plat/adc-core.h>
 
 static void s5p6440_idle(void)
 {
@@ -61,7 +62,7 @@ static void s5p6440_idle(void)
 void __init s5p6440_map_io(void)
 {
 	/* initialize any device information early */
-	s3c_device_adc.name	= "s3c64xx-adc";
+	s3c_adc_setname("s3c64xx-adc");
 }
 
 void __init s5p6440_init_clocks(int xtal)
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 411a4a9..68317a4 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -32,6 +32,7 @@
 #include <plat/devs.h>
 #include <plat/clock.h>
 #include <plat/s5pv210.h>
+#include <plat/adc-core.h>
 #include <plat/iic-core.h>
 #include <plat/sdhci.h>
 
@@ -76,10 +77,6 @@ static void s5pv210_idle(void)
 
 void __init s5pv210_map_io(void)
 {
-#ifdef CONFIG_S3C_DEV_ADC
-	s3c_device_adc.name	= "s3c64xx-adc";
-#endif
-
 	iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
 
 	/* initialise device information early */
@@ -87,6 +84,8 @@ void __init s5pv210_map_io(void)
 	s5pv210_default_sdhci1();
 	s5pv210_default_sdhci2();
 
+	s3c_adc_setname("s3c64xx-adc");
+
 	/* the i2c devices are directly compatible with s3c2440 */
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
diff --git a/arch/arm/plat-samsung/include/plat/adc-core.h b/arch/arm/plat-samsung/include/plat/adc-core.h
new file mode 100644
index 0000000..a281568
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/adc-core.h
@@ -0,0 +1,28 @@
+/* linux/arch/arm/plat-samsung/include/plat/adc-core.h
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ *		http://www.samsung.com/
+ *
+ * Samsung ADC Controller core functions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_PLAT_ADC_CORE_H
+#define __ASM_PLAT_ADC_CORE_H __FILE__
+
+/* These functions are only for use with the core support code, such as
+ * the cpu specific initialisation code
+ */
+
+/* re-define device name depending on support. */
+static inline void s3c_adc_setname(char *name)
+{
+#ifdef CONFIG_SAMSUNG_DEV_ADC
+	s3c_device_adc.name = name;
+#endif
+}
+
+#endif /* __ASM_PLAT_ADC_CORE_H */
-- 
1.6.2.5



From kgene.kim at samsung.com  Wed Jun 30 08:59:22 2010
From: kgene.kim at samsung.com (Kukjin Kim)
Date: Wed, 30 Jun 2010 21:59:22 +0900
Subject: [PATCH] ARM: S5PC100: Add Touchscreen support.
Message-ID: <1277902762-12916-1-git-send-email-kgene.kim@samsung.com>

From: Naveen Krishna Ch <ch.naveen at samsung.com>

This patch adds touchscreen support for S5PC100.

Signed-off-by: Naveen Krishna Ch <ch.naveen at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim at samsung.com>
---
 arch/arm/mach-s5pc100/Kconfig            |    2 ++
 arch/arm/mach-s5pc100/cpu.c              |    3 +++
 arch/arm/mach-s5pc100/include/mach/map.h |    5 ++++-
 arch/arm/mach-s5pc100/mach-smdkc100.c    |   12 ++++++++++++
 4 files changed, 21 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index b2a11df..4cc740e 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -39,11 +39,13 @@ config S5PC100_SETUP_SDHCI_GPIO
 config MACH_SMDKC100
 	bool "SMDKC100"
 	select CPU_S5PC100
+	select SAMSUNG_DEV_ADC
 	select S3C_DEV_FB
 	select S3C_DEV_I2C1
 	select S3C_DEV_HSMMC
 	select S3C_DEV_HSMMC1
 	select S3C_DEV_HSMMC2
+	select SAMSUNG_DEV_TS
 	select S5PC100_SETUP_FB_24BPP
 	select S5PC100_SETUP_I2C1
 	select S5PC100_SETUP_SDHCI
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
index 7b5bdbc..5edd8e9 100644
--- a/arch/arm/mach-s5pc100/cpu.c
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -40,6 +40,7 @@
 #include <plat/clock.h>
 #include <plat/iic-core.h>
 #include <plat/sdhci.h>
+#include <plat/adc-core.h>
 #include <plat/onenand-core.h>
 
 #include <plat/s5pc100.h>
@@ -87,6 +88,8 @@ void __init s5pc100_map_io(void)
 	s5pc100_default_sdhci1();
 	s5pc100_default_sdhci2();
 
+	s3c_adc_setname("s3c64xx-adc");
+
 	/* the i2c devices are directly compatible with s3c2440 */
 	s3c_i2c0_setname("s3c2440-i2c");
 	s3c_i2c1_setname("s3c2440-i2c");
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index cadae43..56d02c0 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -104,6 +104,8 @@
 #define S5PC100_PA_PCM0		0xF2400000
 #define S5PC100_PA_PCM1		0xF2500000
 
+#define S5PC100_PA_TSADC	(0xF3000000)
+
 /* KEYPAD */
 #define S5PC100_PA_KEYPAD	(0xF3100000)
 
@@ -130,9 +132,10 @@
 #define S3C_PA_HSMMC1		S5PC100_PA_HSMMC(1)
 #define S3C_PA_HSMMC2		S5PC100_PA_HSMMC(2)
 #define S3C_PA_KEYPAD		S5PC100_PA_KEYPAD
-#define S3C_PA_TSADC		S5PC100_PA_TSADC
 #define S3C_PA_ONENAND		S5PC100_PA_ONENAND
 #define S3C_PA_ONENAND_BUF	S5PC100_PA_ONENAND_BUF
 #define S3C_SZ_ONENAND_BUF	S5PC100_SZ_ONENAND_BUF
 
+#define SAMSUNG_PA_ADC		S5PC100_PA_TSADC
+
 #endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index af22f82..ebb682b 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -42,6 +42,8 @@
 #include <plat/s5pc100.h>
 #include <plat/fb.h>
 #include <plat/iic.h>
+#include <plat/adc.h>
+#include <plat/ts.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
 #define S5PC100_UCON_DEFAULT	(S3C2410_UCON_TXILEVEL |	\
@@ -150,16 +152,24 @@ static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
 };
 
 static struct platform_device *smdkc100_devices[] __initdata = {
+	&s3c_device_adc,
 	&s3c_device_i2c0,
 	&s3c_device_i2c1,
 	&s3c_device_fb,
 	&s3c_device_hsmmc0,
 	&s3c_device_hsmmc1,
 	&s3c_device_hsmmc2,
+	&s3c_device_ts,
 	&smdkc100_lcd_powerdev,
 	&s5pc100_device_iis0,
 	&s5pc100_device_ac97,
 };
+
+static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
+	.delay			= 10000,
+	.presc			= 49,
+	.oversampling_shift	= 2,
+};
 
 static void __init smdkc100_map_io(void)
 {
@@ -170,6 +180,8 @@ static void __init smdkc100_map_io(void)
 
 static void __init smdkc100_machine_init(void)
 {
+	s3c24xx_ts_set_platdata(&s3c_ts_platform);
+
 	/* I2C */
 	s3c_i2c0_set_platdata(NULL);
 	s3c_i2c1_set_platdata(NULL);
-- 
1.6.2.5



From anderson at redhat.com  Wed Jun 30 09:10:58 2010
From: anderson at redhat.com (Dave Anderson)
Date: Wed, 30 Jun 2010 09:10:58 -0400 (EDT)
Subject: [PATCH 0/4] crash utility: add ARM crashdump support
In-Reply-To: <1093965077.507331277902686384.JavaMail.root@zmail05.collab.prod.int.phx2.redhat.com>
Message-ID: <482970280.508981277903458507.JavaMail.root@zmail05.collab.prod.int.phx2.redhat.com>


----- "Mika Westerberg" <ext-mika.1.westerberg at nokia.com> wrote:

> Hello Dave,
> 
> First of all, thanks for the great tool! It is the best post-mortem analysis
> tool I've ever used.
> 
> This series implements ARM support for the crash utility. Current implementation
> provides following:
> 
> 	o Virtual to physical address translation through page tables
> 	o Stack unwinding support using ARM unwind tables
> 	o And some more to get minimal support for ARM architecture
> 
> There are limitations, however:
> 
> 	o Only one CPU is supported (I don't have access to ARM SMP hardware)
> 	o No support for stack unwinding with CONFIG_FRAMEPOINTER
> 	o Only diskdump format is supported (generated by makedumpfile)
> 
> These apply on top of crash 5.0.5 sources. Please let me know, if there is
> something that needs to be changed. It would be great if you would consider
> taking these in upstream crash.

Hi Mike,

Actually I have a problem with this -- although I think it's a good one for you...

As I understand it, this patch-set will run on an ARM host against either
an ARM kdump-ELF or makedumpfile-generated dumpfile, and presumably on a
live ARM system.

As it turns out, over the last couple of weeks, I've been going back-and-forth
with another ARM-support patch-set created by Jan Karlsson and Thomas Fange of 
Sony Ericcson.  However, their patch set is designed to be built on and run
on a 32-bit x86 host, although I think that with a very minor tweak, it could
also could be built and run on an ARM host.  For that reason, it doesn't support
running on a live ARM system, but rather only for ARM dumpfiles running
on an x86 host (or x86_64 given its capability of running 32-bit binaries).

In any case, I'm more than happy to fold in ARM support, but I don't know what
to do in this case.

I wonder if it would it be possible for you, Jan and Thomas to somehow collaborate
on this effort?  It seems that both sides would benefit from the work of the other
side.  I've added them to the cc list.

This should be interesting...

Dave 

 
> With these patches, the crash utility can analyze ARM crashdumps pretty well (at
> least in my testing environment). What is missing, can be implemented later on
> when we have kernel[1] support and users.
> 
> After this, all necessary userspace components should be ready for ARM
> architecture (kexec-tools, makedumpfile and crash utility).
> 
> I've tested this on OMAP3 based platforms with 2.6.32 and latest mainline
> kernels (with the kdump patches).
> 
> Regards,
> MW
> 
> [1]
> Note that kernel crashdump support is not yet in mainline but I'm hoping that it
> will be merged eventually (patches are in RMK's patch tracker already).
> 
> Mika Westerberg (4):
>   configure: add support for ARM targets
>   crash: add support for ARM kernel image
>   crash: add ARM diskdump support
>   crash: add ARM crashdump support
> 
>  Makefile            |   12 +-
>  arm.c               | 1188
> +++++++++++++++++++++++++++++++++++++++++++++++++++
>  configure.c         |   14 +
>  defs.h              |  131 ++++++
>  diskdump.c          |   50 ++-
>  kernel.c            |    2 +-
>  lkcd_vmdump_v2_v3.h |    4 +-
>  symbols.c           |    8 +-
>  unwind_arm.c        |  702 ++++++++++++++++++++++++++++++
>  9 files changed, 2102 insertions(+), 9 deletions(-)
>  create mode 100644 arm.c
>  create mode 100644 unwind_arm.c


From tony at atomide.com  Wed Jun 30 09:17:37 2010
From: tony at atomide.com (Tony Lindgren)
Date: Wed, 30 Jun 2010 16:17:37 +0300
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100630110828.GZ2822@atomide.com>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
	<20100623073912.GA12255@atomide.com>
	<20100623133636.GC7058@shareable.org>
	<20100629141836.GM2822@atomide.com>
	<alpine.LFD.2.00.1006291355520.24097@xanadu.home>
	<20100630110828.GZ2822@atomide.com>
Message-ID: <20100630131737.GF2822@atomide.com>

* Tony Lindgren <tony at atomide.com> [100630 14:02]:
> * Nicolas Pitre <nico at fluxnic.net> [100629 22:14]:
> 
> Updated patch below.

And a bug crept in..

> +	.macro set_tls_v6, tp, tmp1, tmp2
> +	ldr	\tmp1, =elf_hwcap
> +	ldr	\tmp1, [\tmp1, #0]
> +	mov	\tmp2, #0xffff0fff
> +	tst	\tmp2, #HWCAP_TLS		@ hardware TLS available?
> +	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
> +	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
> +	.endm

The tst	\tmp2, #HWCAP_TLS should of course use \tmp1.

Also fixed a warning about adding parentheses around comparison
if (id & 0x410f0000) != 0x41070000).

Again, updated patch below.

Tony

From tony at atomide.com  Tue Jun 29 06:34:53 2010
From: tony at atomide.com (Tony Lindgren)
Date: Tue, 29 Jun 2010 13:34:53 +0300
Subject: [PATCH] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and check for it on V6
Message-ID: <mailman.61.1277903856.27306.linux-arm-kernel@lists.infradead.org>

The TLS register is only available on ARM1136 r1p0 and later.
Set HWCAP_TLS flags if hardware TLS is available and test for
it if CONFIG_CPU_32v6K is not set for V6.

Note that we set the TLS instruction in __kuser_get_tls
dynamically as suggested by Jamie Lokier <jamie at shareable.org>.

Also the __switch_to code is optimized out in most cases as
suggested by Nicolas Pitre <nico at fluxnic.net>.

Signed-off-by: Tony Lindgren <tony at atomide.com>

diff --git a/arch/arm/include/asm/hwcap.h b/arch/arm/include/asm/hwcap.h
index f7bd52b..c1062c3 100644
--- a/arch/arm/include/asm/hwcap.h
+++ b/arch/arm/include/asm/hwcap.h
@@ -19,6 +19,7 @@
 #define HWCAP_NEON	4096
 #define HWCAP_VFPv3	8192
 #define HWCAP_VFPv3D16	16384
+#define HWCAP_TLS	32768
 
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 /*
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
new file mode 100644
index 0000000..e565f33
--- /dev/null
+++ b/arch/arm/include/asm/tls.h
@@ -0,0 +1,46 @@
+#ifndef __ASMARM_TLS_H
+#define __ASMARM_TLS_H
+
+#ifdef __ASSEMBLY__
+	.macro set_tls_none, tp, tmp1, tmp2
+	.endm
+
+	.macro set_tls_v6k, tp, tmp1, tmp2
+	mcr	p15, 0, \tp, c13, c0, 3		@ set TLS register
+	.endm
+
+	.macro set_tls_v6, tp, tmp1, tmp2
+	ldr	\tmp1, =elf_hwcap
+	ldr	\tmp1, [\tmp1, #0]
+	mov	\tmp2, #0xffff0fff
+	tst	\tmp1, #HWCAP_TLS		@ hardware TLS available?
+	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
+	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
+	.endm
+
+	.macro set_tls_software, tp, tmp1, tmp2
+	mov	\tmp1, #0xffff0fff
+	str	\tp, [\tmp1, #-15]		@ set TLS value at 0xffff0ff0
+	.endm
+#endif
+
+#ifdef CONFIG_TLS_REG_EMUL
+#define tls_emu		1
+#define has_tls		1
+#define set_tls		set_tls_none
+#elif __LINUX_ARM_ARCH__ >= 7 ||					\
+	(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
+#define tls_emu		0
+#define has_tls		1
+#define set_tls		set_tls_v6k
+#elif __LINUX_ARM_ARCH__ == 6
+#define tls_emu		0
+#define has_tls		(elf_hwcap & HWCAP_TLS)
+#define set_tls		set_tls_v6
+#else
+#define tls_emu		0
+#define has_tls		0
+#define set_tls		set_tls_software
+#endif
+
+#endif	/* __ASMARM_TLS_H */
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 7ee48e7..a6cfb17 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -22,6 +22,7 @@
 #include <asm/thread_notify.h>
 #include <asm/unwind.h>
 #include <asm/unistd.h>
+#include <asm/tls.h>
 
 #include "entry-header.S"
 
@@ -739,12 +740,7 @@ ENTRY(__switch_to)
 #ifdef CONFIG_MMU
 	ldr	r6, [r2, #TI_CPU_DOMAIN]
 #endif
-#if defined(CONFIG_HAS_TLS_REG)
-	mcr	p15, 0, r3, c13, c0, 3		@ set TLS register
-#elif !defined(CONFIG_TLS_REG_EMUL)
-	mov	r4, #0xffff0fff
-	str	r3, [r4, #-15]			@ TLS val at 0xffff0ff0
-#endif
+	set_tls	r3, r4, r5
 #ifdef CONFIG_MMU
 	mcr	p15, 0, r6, c3, c0, 0		@ Set domain register
 #endif
@@ -1009,17 +1005,12 @@ kuser_cmpxchg_fixup:
  */
 
 __kuser_get_tls:				@ 0xffff0fe0
-
-#if !defined(CONFIG_HAS_TLS_REG) && !defined(CONFIG_TLS_REG_EMUL)
-	ldr	r0, [pc, #(16 - 8)]		@ TLS stored at 0xffff0ff0
-#else
-	mrc	p15, 0, r0, c13, c0, 3		@ read TLS register
-#endif
+	ldr	r0, [pc, #(16 - 8)]	@ read TLS, set in kuser_get_tls_init
 	usr_ret	lr
-
-	.rep	5
-	.word	0			@ pad up to __kuser_helper_version
-	.endr
+	mrc	p15, 0, r0, c13, c0, 3	@ 0xffff0fe8 hardware TLS code
+	.rep	4
+	.word	0			@ 0xffff0ff0 software TLS value, then
+	.endr				@ pad up to __kuser_helper_version
 
 /*
  * Reference declaration:
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 122d999..6e2c6f9 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -269,6 +269,21 @@ static void __init cacheid_init(void)
 extern struct proc_info_list *lookup_processor_type(unsigned int);
 extern struct machine_desc *lookup_machine_type(unsigned int);
 
+static void __init feat_v6_fixup(void)
+{
+	int id = read_cpuid_id();
+
+	if ((id & 0x410f0000) != 0x41070000)
+		return;
+
+	/*
+	 * HWCAP_TLS is available only on 1136 r1p0 and later,
+	 * see also kuser_get_tls_init.
+	 */
+	if ((((id >> 4) & 0xfff) == 0xb36) && (((id >> 20) & 3) == 0))
+		elf_hwcap &= ~HWCAP_TLS;
+}
+
 static void __init setup_processor(void)
 {
 	struct proc_info_list *list;
@@ -311,6 +326,8 @@ static void __init setup_processor(void)
 	elf_hwcap &= ~HWCAP_THUMB;
 #endif
 
+	feat_v6_fixup();
+
 	cacheid_init();
 	cpu_proc_init();
 }
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 1621e53..e84d210 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -30,6 +30,7 @@
 #include <asm/unistd.h>
 #include <asm/traps.h>
 #include <asm/unwind.h>
+#include <asm/tls.h>
 
 #include "ptrace.h"
 #include "signal.h"
@@ -518,17 +519,20 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
 
 	case NR(set_tls):
 		thread->tp_value = regs->ARM_r0;
-#if defined(CONFIG_HAS_TLS_REG)
-		asm ("mcr p15, 0, %0, c13, c0, 3" : : "r" (regs->ARM_r0) );
-#elif !defined(CONFIG_TLS_REG_EMUL)
-		/*
-		 * User space must never try to access this directly.
-		 * Expect your app to break eventually if you do so.
-		 * The user helper at 0xffff0fe0 must be used instead.
-		 * (see entry-armv.S for details)
-		 */
-		*((unsigned int *)0xffff0ff0) = regs->ARM_r0;
-#endif
+		if (tls_emu)
+			return 0;
+		if (has_tls) {
+			asm ("mcr p15, 0, %0, c13, c0, 3"
+				: : "r" (regs->ARM_r0));
+		} else {
+			/*
+			 * User space must never try to access this directly.
+			 * Expect your app to break eventually if you do so.
+			 * The user helper at 0xffff0fe0 must be used instead.
+			 * (see entry-armv.S for details)
+			 */
+			*((unsigned int *)0xffff0ff0) = regs->ARM_r0;
+		}
 		return 0;
 
 #ifdef CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG
@@ -743,6 +747,16 @@ void __init trap_init(void)
 	return;
 }
 
+static void __init kuser_get_tls_init(unsigned long vectors)
+{
+	/*
+	 * vectors + 0xfe0 = __kuser_get_tls
+	 * vectors + 0xfe8 = hardware TLS instruction at 0xffff0fe8
+	 */
+	if (tls_emu || has_tls)
+		memcpy((void *)vectors + 0xfe0, (void *)vectors + 0xfe8, 4);
+}
+
 void __init early_trap_init(void)
 {
 	unsigned long vectors = CONFIG_VECTORS_BASE;
@@ -761,6 +775,11 @@ void __init early_trap_init(void)
 	memcpy((void *)vectors + 0x1000 - kuser_sz, __kuser_helper_start, kuser_sz);
 
 	/*
+	 * Do processor specific fixups for the kuser helpers
+	 */
+	kuser_get_tls_init(vectors);
+
+	/*
 	 * Copy signal return handlers into the vector page, and
 	 * set sigreturn to be a pointer to these.
 	 */
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 346ae14..71d5d5e 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -717,17 +717,6 @@ config TLS_REG_EMUL
 	  a few prototypes like that in existence) and therefore access to
 	  that required register must be emulated.
 
-config HAS_TLS_REG
-	bool
-	depends on !TLS_REG_EMUL
-	default y if SMP || CPU_32v7
-	help
-	  This selects support for the CP15 thread register.
-	  It is defined to be available on some ARMv6 processors (including
-	  all SMP capable ARMv6's) or later processors.  User space may
-	  assume directly accessing that register and always obtain the
-	  expected value only on ARMv7 and above.
-
 config NEEDS_SYSCALL_FOR_CMPXCHG
 	bool
 	help
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 7a5337e..e10626a 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -239,7 +239,8 @@ __v6_proc_info:
 	b	__v6_setup
 	.long	cpu_arch_name
 	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
+	/* See also feat_v6_fixup() for HWCAP_TLS */
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
 	.long	cpu_v6_name
 	.long	v6_processor_functions
 	.long	v6wbi_tlb_fns
@@ -262,7 +263,8 @@ __pj4_v6_proc_info:
 	b	__v6_setup
 	.long	cpu_arch_name
 	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+	/* See also feat_v6_fixup() for HWCAP_TLS */
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
 	.long	cpu_pj4_name
 	.long	v6_processor_functions
 	.long	v6wbi_tlb_fns
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 7aaf88a..8071bcd 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -344,7 +344,7 @@ __v7_proc_info:
 	b	__v7_setup
 	.long	cpu_arch_name
 	.long	cpu_elf_name
-	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
 	.long	cpu_v7_name
 	.long	v7_processor_functions
 	.long	v7wbi_tlb_fns

--kjpMrWxdCilgNbo1--


From lamiaposta71 at gmail.com  Wed Jun 30 09:47:58 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Wed, 30 Jun 2010 15:47:58 +0200
Subject: [PATCH 3/3] ASoC: DaVinci: Added fast clock timing for McBSP (I2S)
In-Reply-To: <1277905678-4695-1-git-send-email-lamiaposta71@gmail.com>
References: <1277905678-4695-1-git-send-email-lamiaposta71@gmail.com>
Message-ID: <1277905678-4695-4-git-send-email-lamiaposta71@gmail.com>

From: Raffaele Recalcati <raffaele.recalcati at bticino.it>

    i2s_fast_clock switch can be used to have a better approximate
    frequency.
    The waveform will be not symmetric.

    This patch has been developed against the
        http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
    git tree and has been tested on bmx board (similar to dm365 evm, but using
    uda1345 as external audio codec).

Signed-off-by: Raffaele Recalcati <raffaele.recalcati at bticino.it>
Signed-off-by: Davide Bonfanti <davide.bonfanti at bticino.it>
---
 arch/arm/mach-davinci/include/mach/asp.h |    7 +++++++
 sound/soc/davinci/davinci-i2s.c          |   24 +++++++++++++++++++-----
 2 files changed, 26 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
index 314570d..2d8f8af 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -63,6 +63,13 @@ struct snd_platform_data {
 	unsigned sram_size_playback;
 	unsigned sram_size_capture;
 
+	/*
+	 * This define works when both clock and FS are output for the cpu
+	 * and makes clock very fast (FS is not symmetrical, but sampling
+	 * frequency is better approximated
+	 */
+	bool i2s_fast_clock;
+
 	/* To be used when cpu gets clock from external pin */
 	int clk_input_pin;
 
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index e478be9..0af5bae 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -150,6 +150,7 @@ struct davinci_mcbsp_dev {
 	 */
 	unsigned enable_channel_combine:1;
 
+	bool i2s_fast_clock;
 	unsigned int fmt;
 	int clk_div;
 	int clk_input_pin;
@@ -443,11 +444,23 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 		       DAVINCI_MCBSP_SRGR_CLKSM;
 		srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length *
 						8 - 1);
-		/* symmetric waveforms */
-		clk_div = freq / (mcbsp_word_length * 16) /
-			  params->rate_num * params->rate_den;
-		srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
-						16 - 1);
+		if (dev->i2s_fast_clock) {
+			clk_div = 256;
+			do {
+				framesize = (freq / (--clk_div)) /
+					    params->rate_num *
+					    params->rate_den;
+			} while (((framesize < 33) || (framesize > 4095)) &&
+				 (clk_div));
+			clk_div--;
+			srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
+		} else {
+			/* symmetric waveforms */
+			clk_div = freq / (mcbsp_word_length * 16) /
+				  params->rate_num * params->rate_den;
+			srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
+							16 - 1);
+		}
 		clk_div &= 0xFF;
 		srgr |= clk_div;
 		break;
@@ -643,6 +656,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
 			pdata->sram_size_playback;
 		dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
 			pdata->sram_size_capture;
+		dev->i2s_fast_clock = pdata->i2s_fast_clock;
 		dev->clk_input_pin = pdata->clk_input_pin;
 	}
 	dev->clk = clk_get(&pdev->dev, NULL);
-- 
1.7.0.4



From lamiaposta71 at gmail.com  Wed Jun 30 09:47:57 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Wed, 30 Jun 2010 15:47:57 +0200
Subject: [PATCH 2/3] ASoC: DaVinci: Added selection of clk input pin for McBSP
In-Reply-To: <1277905678-4695-1-git-send-email-lamiaposta71@gmail.com>
References: <1277905678-4695-1-git-send-email-lamiaposta71@gmail.com>
Message-ID: <1277905678-4695-3-git-send-email-lamiaposta71@gmail.com>

From: Raffaele Recalcati <raffaele.recalcati at bticino.it>

    When McBSP peripheral gets the clock from an external pin,
    there are three possible chooses, MCBSP_CLKX, MCBSP_CLKR
    and MCBSP_CLKS.
    evm-dm365 uses MCBSP_CLKR, instead in bmx board I have a different
    hardware connection and I use MCBSP_CLKS, so I have added
    this possibility.

    This patch has been developed against the:
        http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
    git tree and has been tested on bmx board (similar to dm365 evm)

Signed-off-by: Raffaele Recalcati <raffaele.recalcati at bticino.it>
Signed-off-by: Davide Bonfanti <davide.bonfanti at bticino.it>
---
 arch/arm/mach-davinci/include/mach/asp.h |    8 ++++++++
 sound/soc/davinci/davinci-i2s.c          |   28 +++++++++++++++++++++++-----
 2 files changed, 31 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
index 834725f..314570d 100644
--- a/arch/arm/mach-davinci/include/mach/asp.h
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -63,6 +63,9 @@ struct snd_platform_data {
 	unsigned sram_size_playback;
 	unsigned sram_size_capture;
 
+	/* To be used when cpu gets clock from external pin */
+	int clk_input_pin;
+
 	/* McASP specific fields */
 	int tdm_slots;
 	u8 op_mode;
@@ -78,6 +81,11 @@ enum {
 	MCASP_VERSION_2,	/* DA8xx/OMAPL1x */
 };
 
+enum {
+	MCBSP_CLKR = 0,		/* DM365 */
+	MCBSP_CLKS,
+};
+
 #define INACTIVE_MODE	0
 #define TX_MODE		1
 #define RX_MODE		2
diff --git a/sound/soc/davinci/davinci-i2s.c b/sound/soc/davinci/davinci-i2s.c
index 319e8ca..e478be9 100644
--- a/sound/soc/davinci/davinci-i2s.c
+++ b/sound/soc/davinci/davinci-i2s.c
@@ -152,6 +152,7 @@ struct davinci_mcbsp_dev {
 
 	unsigned int fmt;
 	int clk_div;
+	int clk_input_pin;
 };
 
 static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev,
@@ -278,11 +279,26 @@ static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 			DAVINCI_MCBSP_PCR_CLKRM;
 		break;
 	case SND_SOC_DAIFMT_CBM_CFS:
-		/* McBSP CLKR pin is the input for the Sample Rate Generator.
-		 * McBSP FSR and FSX are driven by the Sample Rate Generator. */
-		pcr = DAVINCI_MCBSP_PCR_SCLKME |
-			DAVINCI_MCBSP_PCR_FSXM |
-			DAVINCI_MCBSP_PCR_FSRM;
+		pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM;
+		/*
+		 * Selection of the clock input pin that is the
+		 * input for the Sample Rate Generator.
+		 * McBSP FSR and FSX are driven by the Sample Rate
+		 * Generator.
+		 */
+		switch (dev->clk_input_pin) {
+		case MCBSP_CLKS:
+			pcr |= DAVINCI_MCBSP_PCR_CLKXM |
+				DAVINCI_MCBSP_PCR_CLKRM;
+			break;
+		case MCBSP_CLKR:
+			pcr |= DAVINCI_MCBSP_PCR_SCLKME;
+			break;
+		default:
+			printk(KERN_ERR "%s:bad clk_input_pin\n", __func__);
+			return -EINVAL;
+		}
+
 		break;
 	case SND_SOC_DAIFMT_CBM_CFM:
 		/* codec is master */
@@ -436,6 +452,7 @@ static int davinci_i2s_hw_params(struct snd_pcm_substream *substream,
 		srgr |= clk_div;
 		break;
 	case SND_SOC_DAIFMT_CBM_CFS:
+		/* Clock given on CLKS */
 		srgr = DAVINCI_MCBSP_SRGR_FSGM;
 		clk_div = dev->clk_div - 1;
 		srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1);
@@ -626,6 +643,7 @@ static int davinci_i2s_probe(struct platform_device *pdev)
 			pdata->sram_size_playback;
 		dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size =
 			pdata->sram_size_capture;
+		dev->clk_input_pin = pdata->clk_input_pin;
 	}
 	dev->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(dev->clk)) {
-- 
1.7.0.4



From will.deacon at arm.com  Wed Jun 30 10:04:45 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 30 Jun 2010 15:04:45 +0100
Subject: [PATCH 1/4] ARM: atomic ops: fix register constraints for
	atomic64_add_unless
In-Reply-To: <1277906688-12065-1-git-send-email-will.deacon@arm.com>
References: <1277906688-12065-1-git-send-email-will.deacon@arm.com>
Message-ID: <1277906688-12065-2-git-send-email-will.deacon@arm.com>

The atomic64_add_unless function compares an atomic variable with
a given value and, if they are not equal, adds another given value
to the atomic variable. The function returns zero if the addition
did not occur and non-zero otherwise.

On ARM, the return value is initialised to 1 in C code. Inline assembly
code then performs the atomic64_add_unless operation, setting the
return value to 0 iff the addition does not occur. This means that
when the addition *does* occur, the value of ret must be preserved
across the inline assembly and therefore requires a "+r" constraint
rather than the current one of "=&r".

Thanks to Nicolas Pitre for helping to spot this.

Cc: Nicolas Pitre <nico at fluxnic.net>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/atomic.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index a0162fa..e9e56c0 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -440,7 +440,7 @@ static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
 "	teq	%2, #0\n"
 "	bne	1b\n"
 "2:"
-	: "=&r" (val), "=&r" (ret), "=&r" (tmp)
+	: "=&r" (val), "+r" (ret), "=&r" (tmp)
 	: "r" (&v->counter), "r" (u), "r" (a)
 	: "cc");
 
-- 
1.6.3.3



From will.deacon at arm.com  Wed Jun 30 10:04:46 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 30 Jun 2010 15:04:46 +0100
Subject: [PATCH 2/4] ARM: atomic ops: reduce critical region in
	atomic64_cmpxchg
In-Reply-To: <1277906688-12065-2-git-send-email-will.deacon@arm.com>
References: <1277906688-12065-1-git-send-email-will.deacon@arm.com>
	<1277906688-12065-2-git-send-email-will.deacon@arm.com>
Message-ID: <1277906688-12065-3-git-send-email-will.deacon@arm.com>

In order to reduce the likelihood of failure in a load/store
exclusive block, the number of intervening instructions should
be kept to a minimum.

This patch hoists a mov operation out of the critical region
in atomic64_cmpxchg.

Cc: Nicolas Pitre <nico at fluxnic.net>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/atomic.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index e9e56c0..4f0f282 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -358,8 +358,8 @@ static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new)
 
 	do {
 		__asm__ __volatile__("@ atomic64_cmpxchg\n"
-		"ldrexd		%1, %H1, [%2]\n"
 		"mov		%0, #0\n"
+		"ldrexd		%1, %H1, [%2]\n"
 		"teq		%1, %3\n"
 		"teqeq		%H1, %H3\n"
 		"strexdeq	%0, %4, %H4, [%2]"
-- 
1.6.3.3



From will.deacon at arm.com  Wed Jun 30 10:04:48 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 30 Jun 2010 15:04:48 +0100
Subject: [PATCH 4/4] ARM: atomic64_test: add ARM as supported architecture
In-Reply-To: <1277906688-12065-4-git-send-email-will.deacon@arm.com>
References: <1277906688-12065-1-git-send-email-will.deacon@arm.com>
	<1277906688-12065-2-git-send-email-will.deacon@arm.com>
	<1277906688-12065-3-git-send-email-will.deacon@arm.com>
	<1277906688-12065-4-git-send-email-will.deacon@arm.com>
Message-ID: <1277906688-12065-5-git-send-email-will.deacon@arm.com>

ARM has support for the atomic64_dec_if_positive operation
so ensure that it is tested by the atomic64_test routine.

Cc: Nicolas Pitre <nico at fluxnic.net>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 lib/atomic64_test.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/lib/atomic64_test.c b/lib/atomic64_test.c
index 250ed11..44524cc 100644
--- a/lib/atomic64_test.c
+++ b/lib/atomic64_test.c
@@ -114,7 +114,7 @@ static __init int test_atomic64(void)
 	BUG_ON(v.counter != r);
 
 #if defined(CONFIG_X86) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
-    defined(CONFIG_S390) || defined(_ASM_GENERIC_ATOMIC64_H)
+    defined(CONFIG_S390) || defined(_ASM_GENERIC_ATOMIC64_H) || defined(CONFIG_ARM)
 	INIT(onestwos);
 	BUG_ON(atomic64_dec_if_positive(&v) != (onestwos - 1));
 	r -= one;
-- 
1.6.3.3



From will.deacon at arm.com  Wed Jun 30 10:04:44 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 30 Jun 2010 15:04:44 +0100
Subject: [PATCH 0/4] Fix atomic operations so that atomic64_test passes on ARM
	[V2]
Message-ID: <1277906688-12065-1-git-send-email-will.deacon@arm.com>

This is version 2 of the patches originally posted here:

http://lists.infradead.org/pipermail/linux-arm-kernel/2010-June/018742.html

There are quite a few changes, mainly because I now understand the compiler
bug I was hitting previously.

A recently introduced Kernel feature is the atomic64_test on boot.
ARM fails these tests because the compiler is not correctly informed about
updates occuring to memory and is at liberty to constant-fold atomic64_t
variables.

This patch series fixes some problems with the current atomic64 operations,
adds the correct memory constraints to all of the atomic operations and finally
enables all of the atomic64 tests for ARM. I had to speak with the GCC guys at
ARM to get the memory constraints right in patch 3/4. The problem with the "m"
constraint likely affects other parts of the Kernel, for example, kprobes-decode
seems to have multiple uses of an "m" operand within a single block of inline
asm.

Cc: Nigel Stephens <nigel.stephens at arm.com>
Cc: Nicolas Pitre <nico at fluxnic.net>

Will Deacon (4):
  ARM: atomic ops: fix register constraints for atomic64_add_unless
  ARM: atomic ops: reduce critical region in atomic64_cmpxchg
  ARM: atomic ops: add memory constraints to inline asm
  ARM: atomic64_test: add ARM as supported architecture

 arch/arm/include/asm/atomic.h |  132 ++++++++++++++++++++--------------------
 lib/atomic64_test.c           |    2 +-
 2 files changed, 67 insertions(+), 67 deletions(-)



From will.deacon at arm.com  Wed Jun 30 10:04:47 2010
From: will.deacon at arm.com (Will Deacon)
Date: Wed, 30 Jun 2010 15:04:47 +0100
Subject: [PATCH 3/4] ARM: atomic ops: add memory constraints to inline asm
In-Reply-To: <1277906688-12065-3-git-send-email-will.deacon@arm.com>
References: <1277906688-12065-1-git-send-email-will.deacon@arm.com>
	<1277906688-12065-2-git-send-email-will.deacon@arm.com>
	<1277906688-12065-3-git-send-email-will.deacon@arm.com>
Message-ID: <1277906688-12065-4-git-send-email-will.deacon@arm.com>

Currently, the 32-bit and 64-bit atomic operations on ARM do not
include memory constraints in the inline assembly blocks. In the
case of barrier-less operations [for example, atomic_add], this
means that the compiler may constant fold values which have actually
been modified by a call to an atomic operation.

This issue can be observed in the atomic64_test routine in
<kernel root>/lib/atomic64_test.c:

00000000 <test_atomic64>:
   0:	e1a0c00d 	mov	ip, sp
   4:	e92dd830 	push	{r4, r5, fp, ip, lr, pc}
   8:	e24cb004 	sub	fp, ip, #4
   c:	e24dd008 	sub	sp, sp, #8
  10:	e24b3014 	sub	r3, fp, #20
  14:	e30d000d 	movw	r0, #53261	; 0xd00d
  18:	e3011337 	movw	r1, #4919	; 0x1337
  1c:	e34c0001 	movt	r0, #49153	; 0xc001
  20:	e34a1aa3 	movt	r1, #43683	; 0xaaa3
  24:	e16300f8 	strd	r0, [r3, #-8]!
  28:	e30c0afe 	movw	r0, #51966	; 0xcafe
  2c:	e30b1eef 	movw	r1, #48879	; 0xbeef
  30:	e34d0eaf 	movt	r0, #57007	; 0xdeaf
  34:	e34d1ead 	movt	r1, #57005	; 0xdead
  38:	e1b34f9f 	ldrexd	r4, [r3]
  3c:	e1a34f90 	strexd	r4, r0, [r3]
  40:	e3340000 	teq	r4, #0
  44:	1afffffb 	bne	38 <test_atomic64+0x38>
  48:	e59f0004 	ldr	r0, [pc, #4]	; 54 <test_atomic64+0x54>
  4c:	e3a0101e 	mov	r1, #30
  50:	ebfffffe 	bl	0 <__bug>
  54:	00000000 	.word	0x00000000

The atomic64_set (0x38-0x44) writes to the atomic64_t, but the
compiler doesn't see this, assumes the test condition is always
false and generates an unconditional branch to __bug. The rest of the
test is optimised away.

This patch adds suitable memory constraints to the atomic operations on ARM
to ensure that the compiler is informed of the correct data hazards. We have
to use the "Qo" constraints to avoid hitting the GCC anomaly described at
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=44492 , where the compiler
makes assumptions about the writeback in the addressing mode used by the
inline assembly. These constraints forbid the use of auto{inc,dec} addressing
modes, so it doesn't matter if we don't use the operand exactly once.

Cc: Nicolas Pitre <nico at fluxnic.net>
Signed-off-by: Will Deacon <will.deacon at arm.com>
---
 arch/arm/include/asm/atomic.h |  132 ++++++++++++++++++++--------------------
 1 files changed, 66 insertions(+), 66 deletions(-)

diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 4f0f282..99ab659 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -40,12 +40,12 @@ static inline void atomic_add(int i, atomic_t *v)
 	int result;
 
 	__asm__ __volatile__("@ atomic_add\n"
-"1:	ldrex	%0, [%2]\n"
-"	add	%0, %0, %3\n"
-"	strex	%1, %0, [%2]\n"
+"1:	ldrex	%0, [%3]\n"
+"	add	%0, %0, %4\n"
+"	strex	%1, %0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
 	: "r" (&v->counter), "Ir" (i)
 	: "cc");
 }
@@ -58,12 +58,12 @@ static inline int atomic_add_return(int i, atomic_t *v)
 	smp_mb();
 
 	__asm__ __volatile__("@ atomic_add_return\n"
-"1:	ldrex	%0, [%2]\n"
-"	add	%0, %0, %3\n"
-"	strex	%1, %0, [%2]\n"
+"1:	ldrex	%0, [%3]\n"
+"	add	%0, %0, %4\n"
+"	strex	%1, %0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
 	: "r" (&v->counter), "Ir" (i)
 	: "cc");
 
@@ -78,12 +78,12 @@ static inline void atomic_sub(int i, atomic_t *v)
 	int result;
 
 	__asm__ __volatile__("@ atomic_sub\n"
-"1:	ldrex	%0, [%2]\n"
-"	sub	%0, %0, %3\n"
-"	strex	%1, %0, [%2]\n"
+"1:	ldrex	%0, [%3]\n"
+"	sub	%0, %0, %4\n"
+"	strex	%1, %0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
 	: "r" (&v->counter), "Ir" (i)
 	: "cc");
 }
@@ -96,12 +96,12 @@ static inline int atomic_sub_return(int i, atomic_t *v)
 	smp_mb();
 
 	__asm__ __volatile__("@ atomic_sub_return\n"
-"1:	ldrex	%0, [%2]\n"
-"	sub	%0, %0, %3\n"
-"	strex	%1, %0, [%2]\n"
+"1:	ldrex	%0, [%3]\n"
+"	sub	%0, %0, %4\n"
+"	strex	%1, %0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
 	: "r" (&v->counter), "Ir" (i)
 	: "cc");
 
@@ -118,11 +118,11 @@ static inline int atomic_cmpxchg(atomic_t *ptr, int old, int new)
 
 	do {
 		__asm__ __volatile__("@ atomic_cmpxchg\n"
-		"ldrex	%1, [%2]\n"
+		"ldrex	%1, [%3]\n"
 		"mov	%0, #0\n"
-		"teq	%1, %3\n"
-		"strexeq %0, %4, [%2]\n"
-		    : "=&r" (res), "=&r" (oldval)
+		"teq	%1, %4\n"
+		"strexeq %0, %5, [%3]\n"
+		    : "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
 		    : "r" (&ptr->counter), "Ir" (old), "r" (new)
 		    : "cc");
 	} while (res);
@@ -137,12 +137,12 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
 	unsigned long tmp, tmp2;
 
 	__asm__ __volatile__("@ atomic_clear_mask\n"
-"1:	ldrex	%0, [%2]\n"
-"	bic	%0, %0, %3\n"
-"	strex	%1, %0, [%2]\n"
+"1:	ldrex	%0, [%3]\n"
+"	bic	%0, %0, %4\n"
+"	strex	%1, %0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (tmp), "=&r" (tmp2)
+	: "=&r" (tmp), "=&r" (tmp2), "+Qo" (*addr)
 	: "r" (addr), "Ir" (mask)
 	: "cc");
 }
@@ -249,7 +249,7 @@ static inline u64 atomic64_read(atomic64_t *v)
 	__asm__ __volatile__("@ atomic64_read\n"
 "	ldrexd	%0, %H0, [%1]"
 	: "=&r" (result)
-	: "r" (&v->counter)
+	: "r" (&v->counter), "Qo" (v->counter)
 	);
 
 	return result;
@@ -260,11 +260,11 @@ static inline void atomic64_set(atomic64_t *v, u64 i)
 	u64 tmp;
 
 	__asm__ __volatile__("@ atomic64_set\n"
-"1:	ldrexd	%0, %H0, [%1]\n"
-"	strexd	%0, %2, %H2, [%1]\n"
+"1:	ldrexd	%0, %H0, [%2]\n"
+"	strexd	%0, %3, %H3, [%2]\n"
 "	teq	%0, #0\n"
 "	bne	1b"
-	: "=&r" (tmp)
+	: "=&r" (tmp), "=Qo" (v->counter)
 	: "r" (&v->counter), "r" (i)
 	: "cc");
 }
@@ -275,13 +275,13 @@ static inline void atomic64_add(u64 i, atomic64_t *v)
 	unsigned long tmp;
 
 	__asm__ __volatile__("@ atomic64_add\n"
-"1:	ldrexd	%0, %H0, [%2]\n"
-"	adds	%0, %0, %3\n"
-"	adc	%H0, %H0, %H3\n"
-"	strexd	%1, %0, %H0, [%2]\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
+"	adds	%0, %0, %4\n"
+"	adc	%H0, %H0, %H4\n"
+"	strexd	%1, %0, %H0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
 	: "r" (&v->counter), "r" (i)
 	: "cc");
 }
@@ -294,13 +294,13 @@ static inline u64 atomic64_add_return(u64 i, atomic64_t *v)
 	smp_mb();
 
 	__asm__ __volatile__("@ atomic64_add_return\n"
-"1:	ldrexd	%0, %H0, [%2]\n"
-"	adds	%0, %0, %3\n"
-"	adc	%H0, %H0, %H3\n"
-"	strexd	%1, %0, %H0, [%2]\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
+"	adds	%0, %0, %4\n"
+"	adc	%H0, %H0, %H4\n"
+"	strexd	%1, %0, %H0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
 	: "r" (&v->counter), "r" (i)
 	: "cc");
 
@@ -315,13 +315,13 @@ static inline void atomic64_sub(u64 i, atomic64_t *v)
 	unsigned long tmp;
 
 	__asm__ __volatile__("@ atomic64_sub\n"
-"1:	ldrexd	%0, %H0, [%2]\n"
-"	subs	%0, %0, %3\n"
-"	sbc	%H0, %H0, %H3\n"
-"	strexd	%1, %0, %H0, [%2]\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
+"	subs	%0, %0, %4\n"
+"	sbc	%H0, %H0, %H4\n"
+"	strexd	%1, %0, %H0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
 	: "r" (&v->counter), "r" (i)
 	: "cc");
 }
@@ -334,13 +334,13 @@ static inline u64 atomic64_sub_return(u64 i, atomic64_t *v)
 	smp_mb();
 
 	__asm__ __volatile__("@ atomic64_sub_return\n"
-"1:	ldrexd	%0, %H0, [%2]\n"
-"	subs	%0, %0, %3\n"
-"	sbc	%H0, %H0, %H3\n"
-"	strexd	%1, %0, %H0, [%2]\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
+"	subs	%0, %0, %4\n"
+"	sbc	%H0, %H0, %H4\n"
+"	strexd	%1, %0, %H0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
 	: "r" (&v->counter), "r" (i)
 	: "cc");
 
@@ -359,11 +359,11 @@ static inline u64 atomic64_cmpxchg(atomic64_t *ptr, u64 old, u64 new)
 	do {
 		__asm__ __volatile__("@ atomic64_cmpxchg\n"
 		"mov		%0, #0\n"
-		"ldrexd		%1, %H1, [%2]\n"
-		"teq		%1, %3\n"
-		"teqeq		%H1, %H3\n"
-		"strexdeq	%0, %4, %H4, [%2]"
-		: "=&r" (res), "=&r" (oldval)
+		"ldrexd		%1, %H1, [%3]\n"
+		"teq		%1, %4\n"
+		"teqeq		%H1, %H4\n"
+		"strexdeq	%0, %5, %H5, [%3]"
+		: "=&r" (res), "=&r" (oldval), "+Qo" (ptr->counter)
 		: "r" (&ptr->counter), "r" (old), "r" (new)
 		: "cc");
 	} while (res);
@@ -381,11 +381,11 @@ static inline u64 atomic64_xchg(atomic64_t *ptr, u64 new)
 	smp_mb();
 
 	__asm__ __volatile__("@ atomic64_xchg\n"
-"1:	ldrexd	%0, %H0, [%2]\n"
-"	strexd	%1, %3, %H3, [%2]\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
+"	strexd	%1, %4, %H4, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+Qo" (ptr->counter)
 	: "r" (&ptr->counter), "r" (new)
 	: "cc");
 
@@ -402,16 +402,16 @@ static inline u64 atomic64_dec_if_positive(atomic64_t *v)
 	smp_mb();
 
 	__asm__ __volatile__("@ atomic64_dec_if_positive\n"
-"1:	ldrexd	%0, %H0, [%2]\n"
+"1:	ldrexd	%0, %H0, [%3]\n"
 "	subs	%0, %0, #1\n"
 "	sbc	%H0, %H0, #0\n"
 "	teq	%H0, #0\n"
 "	bmi	2f\n"
-"	strexd	%1, %0, %H0, [%2]\n"
+"	strexd	%1, %0, %H0, [%3]\n"
 "	teq	%1, #0\n"
 "	bne	1b\n"
 "2:"
-	: "=&r" (result), "=&r" (tmp)
+	: "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
 	: "r" (&v->counter)
 	: "cc");
 
@@ -429,18 +429,18 @@ static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
 	smp_mb();
 
 	__asm__ __volatile__("@ atomic64_add_unless\n"
-"1:	ldrexd	%0, %H0, [%3]\n"
-"	teq	%0, %4\n"
-"	teqeq	%H0, %H4\n"
+"1:	ldrexd	%0, %H0, [%4]\n"
+"	teq	%0, %5\n"
+"	teqeq	%H0, %H5\n"
 "	moveq	%1, #0\n"
 "	beq	2f\n"
-"	adds	%0, %0, %5\n"
-"	adc	%H0, %H0, %H5\n"
-"	strexd	%2, %0, %H0, [%3]\n"
+"	adds	%0, %0, %6\n"
+"	adc	%H0, %H0, %H6\n"
+"	strexd	%2, %0, %H0, [%4]\n"
 "	teq	%2, #0\n"
 "	bne	1b\n"
 "2:"
-	: "=&r" (val), "+r" (ret), "=&r" (tmp)
+	: "=&r" (val), "+r" (ret), "=&r" (tmp), "+Qo" (v->counter)
 	: "r" (&v->counter), "r" (u), "r" (a)
 	: "cc");
 
-- 
1.6.3.3



From marek.vasut at gmail.com  Wed Jun 30 10:09:04 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 30 Jun 2010 16:09:04 +0200
Subject: [PATCH 4/4] pxa/spitz: Rework spitz
In-Reply-To: <AANLkTinRkgIg1q8LfRF6jWOoxLNY__xMi3iJjEv1FhWL@mail.gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>
	<201006281729.38591.marek.vasut@gmail.com>
	<AANLkTinRkgIg1q8LfRF6jWOoxLNY__xMi3iJjEv1FhWL@mail.gmail.com>
Message-ID: <201006301609.04907.marek.vasut@gmail.com>

Dne St 30. ?ervna 2010 08:57:57 Eric Miao napsal(a):
> On Mon, Jun 28, 2010 at 11:29 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > Dne Po 28. ?ervna 2010 14:19:46 Eric Miao napsal(a):
> >> On Mon, Jun 28, 2010 at 8:07 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> >> > Dne Po 28. ?ervna 2010 05:43:12 Eric Miao napsal(a):
> >> >> On Thu, Jun 24, 2010 at 10:02 PM, Marek Vasut <marek.vasut at gmail.com>
> > 
> > wrote:
> >> >> > This huge patch mostly shuffles code. The spitz.c file contained
> >> >> > terrible mess and needed a cleanup, here it is:
> >> >> > 
> >> >> > 1) Made every part modular, components are not built in if not
> >> >> > selected. 2) Removed loads of preprocessor goo, mostly "#ifdef
> >> >> > MACH_AKITA .... #endif" and similar code. The kernel size will grow
> >> >> > by a few kb now, but the file is much more readable.
> >> >> > 3) Reworked SD/CF power setting function and made it reentrant.
> >> >> > 4) Add ISL6271A regulator support
> >> >> > 5) Correctly register WM8750
> >> >> > 
> >> >> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> >> >> 
> >> >> I'd prefer to see separate small patches for this?
> >> > 
> >> > This is nearly a replacement for the whole file ... maybe we could
> >> > merge spitz2.c or something ... or do it this way. I understand your
> >> > point about spliting it into smaller chunks, but I don't see a reason
> >> > in this case.
> >> 
> >> I guess the above 1, 2, 3, 4, 5 can be well separated into 5 patches,
> >> I don't mind merge many patches, but I'd really like to see small and
> >> consistent changes (make it regression test friendly BTW), ;-)
> > 
> > I said I get your point, but I don't see the benefit here.
> > 1) already does most of the rewrite of the file,
> > 2) only removes the #ifdef MACH_PLAT around MACHINE_START (as the rest
> > was done in 1) ),
> > 3) is actually a part of 1) as well
> > 4) ok, this could be separated out, but I see no benefit
> > 5) well this is already in if I recall well, but I put it here for
> > completeness
> 
> Several of other comments, though:
> 
> 1. It doesn't look necessary to me to change spitz_* to sharpslc_*. spitz_*
>    isn't a good prefix, neither is sharpslc_* (think about the corgi
> series, which is normally called Sharp SL-C7xx). And this is also going to
> save many unnecessary changes.

I know, but what prefix do you sugest then?
> 
> 2. Direct references of spitzscoop[12]_device are still there, which I'd
>    prefer a cleaner patch for this

I'd prefer rewriting the whole scoop driver and patching the pcmcia driver so 
all this crap can get lot.
> 
> 3. Others seem to be coding style changes - which can be separated

You're right.


From eric.y.miao at gmail.com  Wed Jun 30 10:14:27 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Wed, 30 Jun 2010 22:14:27 +0800
Subject: [PATCH 4/4] pxa/spitz: Rework spitz
In-Reply-To: <201006301609.04907.marek.vasut@gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com> 
	<201006281729.38591.marek.vasut@gmail.com>
	<AANLkTinRkgIg1q8LfRF6jWOoxLNY__xMi3iJjEv1FhWL@mail.gmail.com> 
	<201006301609.04907.marek.vasut@gmail.com>
Message-ID: <AANLkTil1qsmLVgaBnLTy31NaW2T2_PzFioUf1BgtHkMw@mail.gmail.com>

On Wed, Jun 30, 2010 at 10:09 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> Dne St 30. ?ervna 2010 08:57:57 Eric Miao napsal(a):
>> On Mon, Jun 28, 2010 at 11:29 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
>> > Dne Po 28. ?ervna 2010 14:19:46 Eric Miao napsal(a):
>> >> On Mon, Jun 28, 2010 at 8:07 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
>> >> > Dne Po 28. ?ervna 2010 05:43:12 Eric Miao napsal(a):
>> >> >> On Thu, Jun 24, 2010 at 10:02 PM, Marek Vasut <marek.vasut at gmail.com>
>> >
>> > wrote:
>> >> >> > This huge patch mostly shuffles code. The spitz.c file contained
>> >> >> > terrible mess and needed a cleanup, here it is:
>> >> >> >
>> >> >> > 1) Made every part modular, components are not built in if not
>> >> >> > selected. 2) Removed loads of preprocessor goo, mostly "#ifdef
>> >> >> > MACH_AKITA .... #endif" and similar code. The kernel size will grow
>> >> >> > by a few kb now, but the file is much more readable.
>> >> >> > 3) Reworked SD/CF power setting function and made it reentrant.
>> >> >> > 4) Add ISL6271A regulator support
>> >> >> > 5) Correctly register WM8750
>> >> >> >
>> >> >> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
>> >> >>
>> >> >> I'd prefer to see separate small patches for this?
>> >> >
>> >> > This is nearly a replacement for the whole file ... maybe we could
>> >> > merge spitz2.c or something ... or do it this way. I understand your
>> >> > point about spliting it into smaller chunks, but I don't see a reason
>> >> > in this case.
>> >>
>> >> I guess the above 1, 2, 3, 4, 5 can be well separated into 5 patches,
>> >> I don't mind merge many patches, but I'd really like to see small and
>> >> consistent changes (make it regression test friendly BTW), ;-)
>> >
>> > I said I get your point, but I don't see the benefit here.
>> > 1) already does most of the rewrite of the file,
>> > 2) only removes the #ifdef MACH_PLAT around MACHINE_START (as the rest
>> > was done in 1) ),
>> > 3) is actually a part of 1) as well
>> > 4) ok, this could be separated out, but I see no benefit
>> > 5) well this is already in if I recall well, but I put it here for
>> > completeness
>>
>> Several of other comments, though:
>>
>> 1. It doesn't look necessary to me to change spitz_* to sharpslc_*. spitz_*
>> ? ?isn't a good prefix, neither is sharpslc_* (think about the corgi
>> series, which is normally called Sharp SL-C7xx). And this is also going to
>> save many unnecessary changes.
>
> I know, but what prefix do you sugest then?

spitz_* is just OK in my POV if there is nothing better, provided it doesn't
introduce too many naming changes.

>>
>> 2. Direct references of spitzscoop[12]_device are still there, which I'd
>> ? ?prefer a cleaner patch for this
>
> I'd prefer rewriting the whole scoop driver and patching the pcmcia driver so
> all this crap can get lot.
>>
>> 3. Others seem to be coding style changes - which can be separated
>
> You're right.
>


From marek.vasut at gmail.com  Wed Jun 30 10:17:46 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 30 Jun 2010 16:17:46 +0200
Subject: Flash write endurance (write cycle) test for AT91RM9200 boards
In-Reply-To: <BAY134-W19D664FC2A596F0209D21FBDCA0@phx.gbl>
References: <BAY134-W19D664FC2A596F0209D21FBDCA0@phx.gbl>
Message-ID: <201006301617.46700.marek.vasut@gmail.com>

Dne Po 28. ?ervna 2010 22:39:07 Xiachen Dong napsal(a):
> Hi,
> 
> We use AT91RM9200 MCU and made our own motherboard for it. We wish to know
> how many write cycles the flash (MicroSD and DataFlash) may survive under
> both OS and non-OS situation. We also wish to know the behavior of the
> flash when the flash becomes dead.

I believe the number of write cycles is unlimited, but at some point, you won't 
be able to read the data back ;-) If the flash becomes dead, kernel will mark a 
bad block and that's all (you'll be informed). Writes to this block will be 
redirected to some healthy block. You'll probably have the flash partitioned and 
run some FS on top of it, which will take care of load balancing the flash 
blocks. You don't have to worry that the flash will die fast if you don't swap 
on it.

Cheers 
> 
> After doing some searching on the web, we found the following information
> helpful:
> 
> 1) Write Endurance in Flash Drives: Measurements and Analysis
> http://www.ccs.neu.edu/home/pjd/papers/fast10-flash.pdf
> 
> 2) NAND Testing
> http://wiki.laptop.org/go/NAND_Testing
> 
> 3) How Long Does a Flash Drive Last?
> http://www.bress.net/blog/archives/114-How-Long-Does-a-Flash-Drive-Last.htm
> l
> 
> What we plan to do is to test the flash both under u-boot (raw, without
> JFFS2) and Linux OS (with ext2 fs). The test will be done with flash empty
> and flash full. We will also do the test under different room
> temperatures.
> 
> We searched the archive of the list. It looks like no posts mentioned such
> tests. We wonder anyone on the list has done similar test before and are
> there any special attention need to pay while doing such tests. Are there
> any professional software (either open source or commercial) for such
> tests? Any suggestions and comments are welcomed.
> 
> Thanks,
> 
> Xiachen
> 
> 
> _________________________________________________________________
> Turn down-time into play-time with Messenger games
> http://go.microsoft.com/?linkid=9734385
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From Hiroshi.DOYU at nokia.com  Wed Jun 30 10:28:01 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Wed, 30 Jun 2010 17:28:01 +0300
Subject: [RFC][PATCH 1/1] ARM: Add initial hibernation support
In-Reply-To: <1277908081-17195-1-git-send-email-Hiroshi.DOYU@nokia.com>
References: <1277908081-17195-1-git-send-email-Hiroshi.DOYU@nokia.com>
Message-ID: <1277908081-17195-2-git-send-email-Hiroshi.DOYU@nokia.com>

From: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>

Hibernation (a.k.a: Suspend-To-Disk) support for ARM

Based on the original work from Romit and Raghu at TI. The original
patch(*1) was sent to LOML by Teerth Reddy <teerth at ti.com>

*1: https://patchwork.kernel.org/patch/96442/

Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
---
 arch/arm/Kconfig                |    4 +
 arch/arm/include/asm/memory.h   |    1 +
 arch/arm/include/asm/suspend.h  |    6 +
 arch/arm/kernel/Makefile        |    1 +
 arch/arm/kernel/hibernate.c     |  234 +++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/hibernate_asm.S |  135 ++++++++++++++++++++++
 arch/arm/kernel/vmlinux.lds.S   |    3 +-
 7 files changed, 383 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/include/asm/suspend.h
 create mode 100644 arch/arm/kernel/hibernate.c
 create mode 100644 arch/arm/kernel/hibernate_asm.S

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1f254bd..c19a206 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -189,6 +189,10 @@ config VECTORS_BASE
 	help
 	  The base address of exception vectors.
 
+config ARCH_HIBERNATION_POSSIBLE
+	def_bool y
+	depends on CPU_V7 && !SMP
+
 source "init/Kconfig"
 
 source "kernel/Kconfig.freezer"
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 4312ee5..cd49706 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -194,6 +194,7 @@ static inline void *phys_to_virt(unsigned long x)
  */
 #define __pa(x)			__virt_to_phys((unsigned long)(x))
 #define __va(x)			((void *)__phys_to_virt((unsigned long)(x)))
+#define __pa_symbol(x)		__pa(RELOC_HIDE((unsigned long)(x),0))
 #define pfn_to_kaddr(pfn)	__va((pfn) << PAGE_SHIFT)
 
 /*
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
new file mode 100644
index 0000000..8857c79
--- /dev/null
+++ b/arch/arm/include/asm/suspend.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARM_SUSPEND_H
+#define __ASM_ARM_SUSPEND_H
+
+static inline int arch_prepare_suspend(void) { return 0; }
+
+#endif	/* __ASM_ARM_SUSPEND_H */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 26d302c..38a0b10 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_ARM_THUMBEE)	+= thumbee.o
 obj-$(CONFIG_KGDB)		+= kgdb.o
 obj-$(CONFIG_ARM_UNWIND)	+= unwind.o
 obj-$(CONFIG_HAVE_TCM)		+= tcm.o
+obj-$(CONFIG_HIBERNATION)       += hibernate.o hibernate_asm.o
 
 obj-$(CONFIG_CRUNCH)		+= crunch.o crunch-bits.o
 AFLAGS_crunch-bits.o		:= -Wa,-mcpu=ep9312
diff --git a/arch/arm/kernel/hibernate.c b/arch/arm/kernel/hibernate.c
new file mode 100644
index 0000000..692c720
--- /dev/null
+++ b/arch/arm/kernel/hibernate.c
@@ -0,0 +1,234 @@
+/*
+ * Hibernation support specific for ARM
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2006 Rafael J. Wysocki <rjw at sisk.pl>
+ *
+ * Contact: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/module.h>
+#include <linux/mm.h>
+
+/*
+ * Image of the saved processor state
+ *
+ * coprocessor 15 registers(RW)
+ */
+struct saved_context {
+/*
+ * FIXME: Only support for Cortex A8 now
+ */
+	/* CR0 */
+	u32 cssr;	/* Cache Size Selection */
+	/* CR1 */
+	u32 cr;		/* Control */
+	u32 cacr;	/* Coprocessor Access Control */
+	/* CR2 */
+	u32 ttb_0r;	/* Translation Table Base 0 */
+	u32 ttb_1r;	/* Translation Table Base 1 */
+	u32 ttbcr;	/* Translation Talbe Base Control */
+	/* CR3 */
+	u32 dacr;	/* Domain Access Control */
+	/* CR5 */
+	u32 d_fsr;	/* Data Fault Status */
+	u32 i_fsr;	/* Instruction Fault Status */
+	u32 d_afsr;	/* Data Auxilirary Fault Status */	 ;
+	u32 i_afsr;	/* Instruction Auxilirary Fault Status */;
+	/* CR6 */
+	u32 d_far;	/* Data Fault Address */
+	u32 i_far;	/* Instruction Fault Address */
+	/* CR7 */
+	u32 par;	/* Physical Address */
+	/* CR9 */	/* FIXME: Are they necessary? */
+	u32 pmcontrolr;	/* Performance Monitor Control */
+	u32 cesr;      	/* Count Enable Set */
+	u32 cecr;      	/* Count Enable Clear */
+	u32 ofsr;      	/* Overflow Flag Status */
+	u32 sir;       	/* Software Increment */
+	u32 pcsr;      	/* Performance Counter Selection */
+	u32 ccr;       	/* Cycle Count */
+	u32 esr;       	/* Event Selection */
+	u32 pmcountr;  	/* Performance Monitor Count */
+	u32 uer;       	/* User Enable */
+	u32 iesr;      	/* Interrupt Enable Set */
+	u32 iecr;      	/* Interrupt Enable Clear */
+	u32 l2clr;     	/* L2 Cache Lockdown */
+	/* CR10 */
+	u32 d_tlblr;	/* Data TLB Lockdown Register */
+	u32 i_tlblr;	/* Instruction TLB Lockdown Register */
+	u32 prrr;	/* Primary Region Remap Register */
+	u32 nrrr;	/* Normal Memory Remap Register */
+	/* CR11 */
+	u32 pleuar;	/* PLE User Accessibility */
+	u32 plecnr;	/* PLE Channel Number */
+	u32 plecr;	/* PLE Control */
+	u32 pleisar;	/* PLE Internal Start Address */
+	u32 pleiear;	/* PLE Internal End Address */
+	u32 plecidr;	/* PLE Context ID */
+	/* CR12 */
+	u32 snsvbar;	/* Secure or Nonsecure Vector Base Address */
+	/* CR13 */
+	u32 fcse;	/* FCSE PID */
+	u32 cid;	/* Context ID */
+	u32 urwtpid;	/* User read/write Thread and Process ID */
+	u32 urotpid;	/* User read-only Thread and Process ID */
+	u32 potpid;	/* Privileged only Thread and Process ID */
+} __attribute__((packed));
+
+/* Used in hibernate_asm.S */
+#define USER_CONTEXT_SIZE (sizeof(u32) * 15)
+unsigned long saved_context_r0[USER_CONTEXT_SIZE];
+unsigned long saved_cpsr;
+unsigned long saved_context_r13_svc;
+unsigned long saved_context_r14_svc;
+unsigned long saved_spsr_svc;
+
+static struct saved_context saved_context;
+
+/* References to section boundaries */
+extern const void __nosave_begin, __nosave_end;
+
+/*
+ * pfn_is_nosave - check if given pfn is in the 'nosave' section
+ */
+int pfn_is_nosave(unsigned long pfn)
+{
+	unsigned long nosave_begin_pfn = __pa_symbol(&__nosave_begin) >> PAGE_SHIFT;
+	unsigned long nosave_end_pfn = PAGE_ALIGN(__pa_symbol(&__nosave_end)) >> PAGE_SHIFT;
+
+	return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
+}
+
+static inline void __save_processor_state(struct saved_context *ctxt)
+{
+	/* CR0 */
+	asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r"(ctxt->cssr));
+	/* CR1 */
+	asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r"(ctxt->cr));
+	asm volatile ("mrc p15, 0, %0, c1, c0, 2" : "=r"(ctxt->cacr));
+	/* CR2 */
+	asm volatile ("mrc p15, 0, %0, c2, c0, 0" : "=r"(ctxt->ttb_0r));
+	asm volatile ("mrc p15, 0, %0, c2, c0, 1" : "=r"(ctxt->ttb_1r));
+	asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r"(ctxt->ttbcr));
+	/* CR3 */
+	asm volatile ("mrc p15, 0, %0, c3, c0, 0" : "=r"(ctxt->dacr));
+	/* CR5 */
+	asm volatile ("mrc p15, 0, %0, c5, c0, 0" : "=r"(ctxt->d_fsr));
+	asm volatile ("mrc p15, 0, %0, c5, c0, 1" : "=r"(ctxt->i_fsr));
+	asm volatile ("mrc p15, 0, %0, c5, c1, 0" : "=r"(ctxt->d_afsr));
+	asm volatile ("mrc p15, 0, %0, c5, c1, 1" : "=r"(ctxt->i_afsr));
+	/* CR6 */
+	asm volatile ("mrc p15, 0, %0, c6, c0, 0" : "=r"(ctxt->d_far));
+	asm volatile ("mrc p15, 0, %0, c6, c0, 2" : "=r"(ctxt->i_far));
+	/* CR7 */
+	asm volatile ("mrc p15, 0, %0, c7, c4, 0" : "=r"(ctxt->par));
+	/* CR9 */
+	asm volatile ("mrc p15, 0, %0, c9, c12, 0" : "=r"(ctxt->pmcontrolr));
+	asm volatile ("mrc p15, 0, %0, c9, c12, 1" : "=r"(ctxt->cesr));
+	asm volatile ("mrc p15, 0, %0, c9, c12, 2" : "=r"(ctxt->cecr));
+	asm volatile ("mrc p15, 0, %0, c9, c12, 3" : "=r"(ctxt->ofsr));
+	asm volatile ("mrc p15, 0, %0, c9, c12, 4" : "=r"(ctxt->sir));
+	asm volatile ("mrc p15, 0, %0, c9, c12, 5" : "=r"(ctxt->pcsr));
+	asm volatile ("mrc p15, 0, %0, c9, c13, 0" : "=r"(ctxt->ccr));
+	asm volatile ("mrc p15, 0, %0, c9, c13, 1" : "=r"(ctxt->esr));
+	asm volatile ("mrc p15, 0, %0, c9, c13, 2" : "=r"(ctxt->pmcountr));
+	asm volatile ("mrc p15, 0, %0, c9, c14, 0" : "=r"(ctxt->uer));
+	asm volatile ("mrc p15, 0, %0, c9, c14, 1" : "=r"(ctxt->iesr));
+	asm volatile ("mrc p15, 0, %0, c9, c14, 2" : "=r"(ctxt->iecr));
+	asm volatile ("mrc p15, 1, %0, c9, c0, 0" : "=r"(ctxt->l2clr));
+	/* CR10 */
+	asm volatile ("mrc p15, 0, %0, c10, c0, 0" : "=r"(ctxt->d_tlblr));
+	asm volatile ("mrc p15, 0, %0, c10, c0, 1" : "=r"(ctxt->i_tlblr));
+	asm volatile ("mrc p15, 0, %0, c10, c2, 0" : "=r"(ctxt->prrr));
+	asm volatile ("mrc p15, 0, %0, c10, c2, 1" : "=r"(ctxt->nrrr));
+	/* CR11 */
+	asm volatile ("mrc p15, 0, %0, c11, c1, 0" : "=r"(ctxt->pleuar));
+	asm volatile ("mrc p15, 0, %0, c11, c2, 0" : "=r"(ctxt->plecnr));
+	asm volatile ("mrc p15, 0, %0, c11, c4, 0" : "=r"(ctxt->plecr));
+	asm volatile ("mrc p15, 0, %0, c11, c5, 0" : "=r"(ctxt->pleisar));
+	asm volatile ("mrc p15, 0, %0, c11, c7, 0" : "=r"(ctxt->pleiear));
+	asm volatile ("mrc p15, 0, %0, c11, c15, 0" : "=r"(ctxt->plecidr));
+	/* CR12 */
+	asm volatile ("mrc p15, 0, %0, c12, c0, 0" : "=r"(ctxt->snsvbar));
+	/* CR13 */
+	asm volatile ("mrc p15, 0, %0, c13, c0, 0" : "=r"(ctxt->fcse));
+	asm volatile ("mrc p15, 0, %0, c13, c0, 1" : "=r"(ctxt->cid));
+	asm volatile ("mrc p15, 0, %0, c13, c0, 2" : "=r"(ctxt->urwtpid));
+	asm volatile ("mrc p15, 0, %0, c13, c0, 3" : "=r"(ctxt->urotpid));
+	asm volatile ("mrc p15, 0, %0, c13, c0, 4" : "=r"(ctxt->potpid));
+}
+
+static inline void __restore_processor_state(struct saved_context *ctxt)
+{
+	/* CR0 */
+	asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r"(ctxt->cssr));
+	/* CR1 */
+	asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r"(ctxt->cr));
+	asm volatile ("mcr p15, 0, %0, c1, c0, 2" : : "r"(ctxt->cacr));
+	/* CR2 */
+	asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r"(ctxt->ttb_0r));
+	asm volatile ("mcr p15, 0, %0, c2, c0, 1" : : "r"(ctxt->ttb_1r));
+	asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r"(ctxt->ttbcr));
+	/* CR3 */
+	asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r"(ctxt->dacr));
+	/* CR5 */
+	asm volatile ("mcr p15, 0, %0, c5, c0, 0" : : "r"(ctxt->d_fsr));
+	asm volatile ("mcr p15, 0, %0, c5, c0, 1" : : "r"(ctxt->i_fsr));
+	asm volatile ("mcr p15, 0, %0, c5, c1, 0" : : "r"(ctxt->d_afsr));
+	asm volatile ("mcr p15, 0, %0, c5, c1, 1" : : "r"(ctxt->i_afsr));
+	/* CR6 */
+	asm volatile ("mcr p15, 0, %0, c6, c0, 0" : : "r"(ctxt->d_far));
+	asm volatile ("mcr p15, 0, %0, c6, c0, 2" : : "r"(ctxt->i_far));
+	/* CR7 */
+	asm volatile ("mcr p15, 0, %0, c7, c4, 0" : : "r"(ctxt->par));
+	/* CR9 */
+	asm volatile ("mcr p15, 0, %0, c9, c12, 0" : : "r"(ctxt->pmcontrolr));
+	asm volatile ("mcr p15, 0, %0, c9, c12, 1" : : "r"(ctxt->cesr));
+	asm volatile ("mcr p15, 0, %0, c9, c12, 2" : : "r"(ctxt->cecr));
+	asm volatile ("mcr p15, 0, %0, c9, c12, 3" : : "r"(ctxt->ofsr));
+	asm volatile ("mcr p15, 0, %0, c9, c12, 4" : : "r"(ctxt->sir));
+	asm volatile ("mcr p15, 0, %0, c9, c12, 5" : : "r"(ctxt->pcsr));
+	asm volatile ("mcr p15, 0, %0, c9, c13, 0" : : "r"(ctxt->ccr));
+	asm volatile ("mcr p15, 0, %0, c9, c13, 1" : : "r"(ctxt->esr));
+	asm volatile ("mcr p15, 0, %0, c9, c13, 2" : : "r"(ctxt->pmcountr));
+	asm volatile ("mcr p15, 0, %0, c9, c14, 0" : : "r"(ctxt->uer));
+	asm volatile ("mcr p15, 0, %0, c9, c14, 1" : : "r"(ctxt->iesr));
+	asm volatile ("mcr p15, 0, %0, c9, c14, 2" : : "r"(ctxt->iecr));
+	asm volatile ("mcr p15, 1, %0, c9, c0, 0" : : "r"(ctxt->l2clr));
+	/* CR10 */
+	asm volatile ("mcr p15, 0, %0, c10, c0, 0" : : "r"(ctxt->d_tlblr));
+	asm volatile ("mcr p15, 0, %0, c10, c0, 1" : : "r"(ctxt->i_tlblr));
+	asm volatile ("mcr p15, 0, %0, c10, c2, 0" : : "r"(ctxt->prrr));
+	asm volatile ("mcr p15, 0, %0, c10, c2, 1" : : "r"(ctxt->nrrr));
+	/* CR11 */
+	asm volatile ("mcr p15, 0, %0, c11, c1, 0" : : "r"(ctxt->pleuar));
+	asm volatile ("mcr p15, 0, %0, c11, c2, 0" : : "r"(ctxt->plecnr));
+	asm volatile ("mcr p15, 0, %0, c11, c4, 0" : : "r"(ctxt->plecr));
+	asm volatile ("mcr p15, 0, %0, c11, c5, 0" : : "r"(ctxt->pleisar));
+	asm volatile ("mcr p15, 0, %0, c11, c7, 0" : : "r"(ctxt->pleiear));
+	asm volatile ("mcr p15, 0, %0, c11, c15, 0" : : "r"(ctxt->plecidr));
+	/* CR12 */
+	asm volatile ("mcr p15, 0, %0, c12, c0, 0" : : "r"(ctxt->snsvbar));
+	/* CR13 */
+	asm volatile ("mcr p15, 0, %0, c13, c0, 0" : : "r"(ctxt->fcse));
+	asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r"(ctxt->cid));
+	asm volatile ("mcr p15, 0, %0, c13, c0, 2" : : "r"(ctxt->urwtpid));
+	asm volatile ("mcr p15, 0, %0, c13, c0, 3" : : "r"(ctxt->urotpid));
+	asm volatile ("mcr p15, 0, %0, c13, c0, 4" : : "r"(ctxt->potpid));
+}
+
+void save_processor_state(void)
+{
+	preempt_disable();
+	__save_processor_state(&saved_context);
+}
+
+void restore_processor_state(void)
+{
+	__restore_processor_state(&saved_context);
+	preempt_enable();
+}
diff --git a/arch/arm/kernel/hibernate_asm.S b/arch/arm/kernel/hibernate_asm.S
new file mode 100644
index 0000000..6fc199c
--- /dev/null
+++ b/arch/arm/kernel/hibernate_asm.S
@@ -0,0 +1,135 @@
+/*
+ * Hibernation support specific for ARM
+ *
+ * Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2006 Rafael J. Wysocki <rjw at sisk.pl>
+ *
+ * Contact: Hiroshi DOYU <Hiroshi.DOYU at nokia.com>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#include <linux/linkage.h>
+	.text
+ENTRY(swsusp_arch_suspend)
+	/*
+	 * Save current program status register
+	 */
+	ldr     r3, .Lsaved_cpsr
+	mrs     r0, cpsr
+	str     r0, [r3]
+
+	/*
+	 * Change to system(user) mode
+	 */
+	mov     r1, r0
+	orr     r1, r1, #0x1f
+	msr     cpsr_c, r1
+
+	/*
+	 * Save User context
+	 */
+	ldr     r3, .Lsaved_context_r0
+	stmia   r3, {r0-r14}
+
+	/*
+	 * Go back to original SVC mode
+	 */
+	msr     cpsr_c, r0
+
+	/*
+	 * Save SVC context
+	 */
+	ldr     r3, .Lsaved_context_r13_svc
+	stmia   r3, {r13-r14}
+	ldr     r3, .Lsaved_spsr_svc
+	mrs     r1, spsr
+	str     r1, [r3]
+
+	bl      swsusp_save
+
+	/*
+	 * Restore return address
+	 */
+	ldr     r3, .Lsaved_context_r14_svc
+	ldr     lr, [r3]
+	mov     pc, lr
+ENDPROC(swsusp_arch_suspend)
+
+ENTRY(swsusp_arch_resume)
+	/*
+	 * Restore_pblist is the starting point for loaded pages
+	 */
+	ldr     r0, .Lrestore_pblist
+	ldr     r6, [r0]
+
+.Lcopy_loop:
+	ldr     r4, [r6]     /* src IOW present address */
+	ldr     r5, [r6, #4] /* dst IOW original address*/
+	mov     r9, #1024    /* No. of entries in one page, where each entry is 4 bytes */
+
+.Lcopy_one_page:
+	/*
+	 * This loop could be optimized by using stm and ldm.
+	 */
+	ldr     r8, [r4], #4
+	str     r8, [r5], #4
+	subs    r9, r9, #1
+	bne     .Lcopy_one_page
+
+	/* The last field of struct pbe is a pointer to the next pbe structure */
+	ldr     r6, [r6, #8]
+	cmp     r6, #0
+	bne     .Lcopy_loop
+
+	/*
+	 * Restore SVC context
+	 */
+	ldr     r3, .Lsaved_context_r13_svc
+	ldmia   r3, {r13-r14}
+	ldr     r3, .Lsaved_spsr_svc
+	ldr     r1, [r3]
+	msr     spsr_cxsf, r1
+
+	mrs     r0, cpsr	/* Save current mode into r0 */
+
+	/*
+	 * Change to system(user) mode
+	 */
+	mov     r1, r0
+	orr     r1, r1, #0x1f
+	msr     cpsr_c, r1
+
+	/*
+	 * Restore User context
+	 */
+	ldr     r3, .Lsaved_context_r0
+	ldmia   r3, {r0-r14}
+	ldr     r3, .Lsaved_cpsr
+	ldr     r1, [r3]
+	msr     cpsr_cxsf, r1
+
+	msr     cpsr_c, r0	/* Restore original mode from r0 */
+
+	/*
+	 * Flush TLB (Invalidate unified TLB unlocked entries)
+	 */
+	mov     r1, #0
+	mcr     p15, 0, r1, c8, c7, 0
+
+	/* Set the return value */
+	mov	r0, #0
+
+	/* Restore return address */
+	ldr     r3, .Lsaved_context_r14_svc
+	ldr     lr, [r3]
+	mov     pc, lr
+ENDPROC(swsusp_arch_resume)
+	.align	4
+.Lsaved_context_r0:		.long	saved_context_r0
+.Lsaved_cpsr:			.long	saved_cpsr
+.Lsaved_context_r13_svc: 	.long	saved_context_r13_svc
+.Lsaved_context_r14_svc:	.long	saved_context_r14_svc
+.Lsaved_spsr_svc:		.long	saved_spsr_svc
+.Lrestore_pblist:		.long	restore_pblist
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b16c079..799c79c 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -149,7 +149,6 @@ SECTIONS
 		__init_end = .;
 #endif
 
-		NOSAVE_DATA
 		CACHELINE_ALIGNED_DATA(32)
 
 		/*
@@ -172,6 +171,8 @@ SECTIONS
 	}
 	_edata_loc = __data_loc + SIZEOF(.data);
 
+	NOSAVE_DATA
+
 #ifdef CONFIG_HAVE_TCM
         /*
 	 * We align everything to a page boundary so we can
-- 
1.7.1.rc2



From Hiroshi.DOYU at nokia.com  Wed Jun 30 10:28:00 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Wed, 30 Jun 2010 17:28:00 +0300
Subject: [RFC][PATCH 0/1] ARM: Add initial hibernation support
Message-ID: <1277908081-17195-1-git-send-email-Hiroshi.DOYU@nokia.com>

This is the experimental patch to add hibernation (a.k.a:
Suspend-To-Disk) support for ARM architecutre.

Presently it seems to work with OMAP3, and apparently it still needs
more efforts to make it enough stable and to support other ARM
platforms cleanly but I am sending this patch to get some feedbacks at
its early phase to find out the further direction. It would be really
appreciated if you give some comment on this.

This patch is based on the one sent to loml(*1) by Teerth Reddy, which
was originally from Romit and Raghu at TI.

    *1: https://patchwork.kernel.org/patch/96442/

Hiroshi DOYU (1):
  ARM: Add initial hibernation support

 arch/arm/Kconfig                |    4 +
 arch/arm/include/asm/memory.h   |    1 +
 arch/arm/include/asm/suspend.h  |    6 +
 arch/arm/kernel/Makefile        |    1 +
 arch/arm/kernel/hibernate.c     |  234 +++++++++++++++++++++++++++++++++++++++
 arch/arm/kernel/hibernate_asm.S |  135 ++++++++++++++++++++++
 arch/arm/kernel/vmlinux.lds.S   |    3 +-
 7 files changed, 383 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/include/asm/suspend.h
 create mode 100644 arch/arm/kernel/hibernate.c
 create mode 100644 arch/arm/kernel/hibernate_asm.S



From marek.vasut at gmail.com  Wed Jun 30 10:34:31 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 30 Jun 2010 16:34:31 +0200
Subject: [PATCH 4/4] pxa/spitz: Rework spitz
In-Reply-To: <AANLkTil1qsmLVgaBnLTy31NaW2T2_PzFioUf1BgtHkMw@mail.gmail.com>
References: <1277388132-5549-1-git-send-email-marek.vasut@gmail.com>
	<201006301609.04907.marek.vasut@gmail.com>
	<AANLkTil1qsmLVgaBnLTy31NaW2T2_PzFioUf1BgtHkMw@mail.gmail.com>
Message-ID: <201006301634.31774.marek.vasut@gmail.com>

Dne St 30. ?ervna 2010 16:14:27 Eric Miao napsal(a):
> On Wed, Jun 30, 2010 at 10:09 PM, Marek Vasut <marek.vasut at gmail.com> wrote:
> > Dne St 30. ?ervna 2010 08:57:57 Eric Miao napsal(a):
> >> On Mon, Jun 28, 2010 at 11:29 PM, Marek Vasut <marek.vasut at gmail.com> 
wrote:
> >> > Dne Po 28. ?ervna 2010 14:19:46 Eric Miao napsal(a):
> >> >> On Mon, Jun 28, 2010 at 8:07 PM, Marek Vasut <marek.vasut at gmail.com> 
wrote:
> >> >> > Dne Po 28. ?ervna 2010 05:43:12 Eric Miao napsal(a):
> >> >> >> On Thu, Jun 24, 2010 at 10:02 PM, Marek Vasut
> >> >> >> <marek.vasut at gmail.com>
> >> > 
> >> > wrote:
> >> >> >> > This huge patch mostly shuffles code. The spitz.c file contained
> >> >> >> > terrible mess and needed a cleanup, here it is:
> >> >> >> > 
> >> >> >> > 1) Made every part modular, components are not built in if not
> >> >> >> > selected. 2) Removed loads of preprocessor goo, mostly "#ifdef
> >> >> >> > MACH_AKITA .... #endif" and similar code. The kernel size will
> >> >> >> > grow by a few kb now, but the file is much more readable.
> >> >> >> > 3) Reworked SD/CF power setting function and made it reentrant.
> >> >> >> > 4) Add ISL6271A regulator support
> >> >> >> > 5) Correctly register WM8750
> >> >> >> > 
> >> >> >> > Signed-off-by: Marek Vasut <marek.vasut at gmail.com>
> >> >> >> 
> >> >> >> I'd prefer to see separate small patches for this?
> >> >> > 
> >> >> > This is nearly a replacement for the whole file ... maybe we could
> >> >> > merge spitz2.c or something ... or do it this way. I understand
> >> >> > your point about spliting it into smaller chunks, but I don't see
> >> >> > a reason in this case.
> >> >> 
> >> >> I guess the above 1, 2, 3, 4, 5 can be well separated into 5 patches,
> >> >> I don't mind merge many patches, but I'd really like to see small and
> >> >> consistent changes (make it regression test friendly BTW), ;-)
> >> > 
> >> > I said I get your point, but I don't see the benefit here.
> >> > 1) already does most of the rewrite of the file,
> >> > 2) only removes the #ifdef MACH_PLAT around MACHINE_START (as the rest
> >> > was done in 1) ),
> >> > 3) is actually a part of 1) as well
> >> > 4) ok, this could be separated out, but I see no benefit
> >> > 5) well this is already in if I recall well, but I put it here for
> >> > completeness
> >> 
> >> Several of other comments, though:
> >> 
> >> 1. It doesn't look necessary to me to change spitz_* to sharpslc_*.
> >> spitz_* isn't a good prefix, neither is sharpslc_* (think about the
> >> corgi series, which is normally called Sharp SL-C7xx). And this is also
> >> going to save many unnecessary changes.
> > 
> > I know, but what prefix do you sugest then?
> 
> spitz_* is just OK in my POV if there is nothing better, provided it
> doesn't introduce too many naming changes.

But this doesn't cover only spitz ... Especiall if you register some devices, 
which are specific for only akita and borzoi ...
> 
> >> 2. Direct references of spitzscoop[12]_device are still there, which I'd
> >>    prefer a cleaner patch for this
> > 
> > I'd prefer rewriting the whole scoop driver and patching the pcmcia
> > driver so all this crap can get lot.
> > 
> >> 3. Others seem to be coding style changes - which can be separated
> > 
> > You're right.


From nico at fluxnic.net  Wed Jun 30 10:42:18 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 30 Jun 2010 10:42:18 -0400 (EDT)
Subject: [PATCH 1/2] arm: Replace CONFIG_HAS_TLS_REG with HWCAP_TLS and
	check for it on V6
In-Reply-To: <20100630131737.GF2822@atomide.com>
References: <20100621133749.24299.36154.stgit@baageli.muru.com>
	<20100621135120.24299.98499.stgit@baageli.muru.com>
	<20100622170020.GF4371@shareable.org>
	<20100623073912.GA12255@atomide.com>
	<20100623133636.GC7058@shareable.org>
	<20100629141836.GM2822@atomide.com>
	<alpine.LFD.2.00.1006291355520.24097@xanadu.home>
	<20100630110828.GZ2822@atomide.com> <20100630131737.GF2822@atomide.com>
Message-ID: <alpine.LFD.2.00.1006301011520.24097@xanadu.home>

On Wed, 30 Jun 2010, Tony Lindgren wrote:

> * Tony Lindgren <tony at atomide.com> [100630 14:02]:
> > * Nicolas Pitre <nico at fluxnic.net> [100629 22:14]:
> > 
> > Updated patch below.
> 
> And a bug crept in..
> 
> > +	.macro set_tls_v6, tp, tmp1, tmp2
> > +	ldr	\tmp1, =elf_hwcap
> > +	ldr	\tmp1, [\tmp1, #0]
> > +	mov	\tmp2, #0xffff0fff
> > +	tst	\tmp2, #HWCAP_TLS		@ hardware TLS available?
> > +	mcrne	p15, 0, \tp, c13, c0, 3		@ yes, set TLS register
> > +	streq	\tp, [\tmp2, #-15]		@ set TLS value at 0xffff0ff0
> > +	.endm
> 
> The tst	\tmp2, #HWCAP_TLS should of course use \tmp1.
> 
> Also fixed a warning about adding parentheses around comparison
> if (id & 0x410f0000) != 0x41070000).

Here you probably want (id & 0xff0f0000) and not (id & 0x410f0000).

> Again, updated patch below.

I like it.  However, in proc-v6.S, you don't need to add a reference to 
feat_v6_fixup() to the __pj4_v6_proc_info block.  Simply adding 
HWCAP_TLS in that case should be fine as PJ4 always has the TLS reg.

With the above fixes, you can add

Reviewed-by: Nicolas Pitre <nicolas.pitre at linaro.org>


Nicolas


From broonie at opensource.wolfsonmicro.com  Wed Jun 30 10:53:42 2010
From: broonie at opensource.wolfsonmicro.com (Mark Brown)
Date: Wed, 30 Jun 2010 15:53:42 +0100
Subject: [PATCH] ASoC: DaVinci: Added support for cpu clocking I2S
In-Reply-To: <AANLkTimedG3X-rQbZvS6QfxUGkPIAtCgliI0xWknmNA9@mail.gmail.com>
References: <1277707487-3371-1-git-send-email-lamiaposta71@gmail.com>
	<20100628103030.GB14247@rakim.wolfsonmicro.main>
	<AANLkTimedG3X-rQbZvS6QfxUGkPIAtCgliI0xWknmNA9@mail.gmail.com>
Message-ID: <20100630145342.GE3634@rakim.wolfsonmicro.main>

On Wed, Jun 30, 2010 at 10:17:40AM +0200, Raffaele Recalcati wrote:
> 2010/6/28 Mark Brown <broonie at opensource.wolfsonmicro.com>

> > It's still very hard to understand what this patch is supposed to do.
> > As previously mentioned this would probably be a lot clearer if you
> > split this into multiple patches, for example one adding support for the
> > fast clock mode, one adding support for selecting the pin used for any
> > external clock and then further patches with any other changes.

> Looking at other paches, they are simpler than mine.

The big problem is you're just making some general (and not particularly
clear) statements about features without saying anything concrete about
what the patch actually does - is there a bug being fixed, a feature
implemented, or what?  

> > >     Added audio playback support with [frame sync master - clock master]
> > mode
> > >     and with [frame sync master - clock slave].

> > What are these modes - which clock are you talking about?

> McBSP i2s interface to external codec.

Perhaps you mean the bit clock on the I2S interface?  There are multiple
clocks on the actual I2S link itself, and often people lump in the
master clock for the I2S interface into the interface itself.

> > >        i2s_fast_clock switch can be used to have better approximate or
> > >        symmetric waveforms.

> > Why would someone choose not to use this?

> I was not sure if symmetric waveform can be a must.
> In general I think it is better a non symmetric, but better approximate,
> waveform.
> Anyway, it is better to have the possibility to choose in my opinion,
> because I have not so much experience in i2s communication.

If I understand this correctly when you say "approximate" what you mean
is "approximate clock rate" so the tradeoff is between the accuracy of
the rate generated and the duty cycle of the output signal?

> > > +     /* To be used when cpu gets clock from extenal pin */
> > > +     int clk_input_pin;

> > How would one use this?

> looking at 2.5 Clock, Frames, and Data in
> you can select MCBSP_CLKS or other input clock pins.

You need to put this in the comments.

> > > +static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
> > > +                             int div_id, int div)
> > > +{
> > > +     struct davinci_mcbsp_dev *dev = cpu_dai->private_data;
> > > +     int srgr;
> > > +
> > > +     dev->clk_div = div;
> > > +     return 0;
> > > +}

> > I would add a clock ID here in case someone wants to configure another
> > clock in the patch.

> Can you explain better,
> please?

You need to require a value for div_id.

> > I'd also expect this to be doing a clk_get() using the struct device for
> > the DAI so that the driver can function even if the clock tree for a new..
> > SoC is different.

> Sorry, I don't understand, can you explain me better?

clk_get() takes two parameters, a struct device and a name.  You should
be using a clock specified in terms of a particular device, not one with
a NULL pointer for the struct device.

> > > +             freq = 122000000; /* FIXME ask to Texas */

> > ...this presumably ought to be in an else clause (or perhaps just not
> > using this clocking at all if you can't find the clock?).

> freq is used to obtain clk_div.
> The real problem is that, as explained in the manual, it is not clear its
> value.
> I hope someone can help!!

I would very strongly expect that the division would be from the clock
rate of the source clock which you can obtain by using clk_get().


From nico at fluxnic.net  Wed Jun 30 11:07:52 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 30 Jun 2010 11:07:52 -0400 (EDT)
Subject: Pending patches for -rc
In-Reply-To: <20100630101223.GA24284@n2100.arm.linux.org.uk>
References: <20100630101223.GA24284@n2100.arm.linux.org.uk>
Message-ID: <alpine.LFD.2.00.1006301101521.24097@xanadu.home>

On Wed, 30 Jun 2010, Russell King - ARM Linux wrote:

>  44 files changed, 659 insertions(+), 139 deletions(-)
> 
> and I think that if I try to push these to Linus, we'll be on the receipt
> of another complaint - quite rightfully too - the above does not look like
> bug fixes.
> 
> Therefore, I won't be pushing my master branch to Linus, but instead merging
> it into -devel and re-starting my master branch afresh.

I completely agree.  I think that "ARM: 6189/1: Add support for the 
MOVW/MOVT relocations in Thumb-2" could remain though.  All the rest 
from your list could certainly be deferred to the next merge window.


Nicolas


From siccegge at cs.fau.de  Wed Jun 30 11:53:52 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:53:52 +0200
Subject: [PATCH 01/33] Removing dead MTD_NAND_AT91_BUSWIDTH_16
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <4c6fe9a4c298214223ff89d06401ac7b66f81c98.1277911346.git.siccegge@cs.fau.de>

MTD_NAND_AT91_BUSWIDTH_16 doesn't exist in Kconfig, therefore removing
all references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-at91/board-at572d940hf_ek.c |    4 ----
 arch/arm/mach-at91/board-sam9m10g45ek.c   |    4 ----
 2 files changed, 0 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c
index 5daff27..889a442 100644
--- a/arch/arm/mach-at91/board-at572d940hf_ek.c
+++ b/arch/arm/mach-at91/board-at572d940hf_ek.c
@@ -216,11 +216,7 @@ static struct atmel_nand_data __initdata eb_nand_data = {
 /*	.rdy_pin	= AT91_PIN_PC16, */
 	.enable_pin	= AT91_PIN_PA15,
 	.partition_info	= nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
-	.bus_width_16	= 1,
-#else
 	.bus_width_16	= 0,
-#endif
 };
 
 static struct sam9_smc_config __initdata eb_nand_smc_config = {
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ee80059..49ef850 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -135,11 +135,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
 	.rdy_pin	= AT91_PIN_PC8,
 	.enable_pin	= AT91_PIN_PC14,
 	.partition_info	= nand_partitions,
-#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
-	.bus_width_16	= 1,
-#else
 	.bus_width_16	= 0,
-#endif
 };
 
 static struct sam9_smc_config __initdata ek_nand_smc_config = {
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:54:42 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:54:42 +0200
Subject: [PATCH 03/33] Removing dead OMAP_MUX_ERRORS
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <b6ca168f9459162f2c96aa8ef999047a3c4f6f9c.1277911346.git.siccegge@cs.fau.de>

OMAP_MUX_ERRORS doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-omap1/mux.c |    5 -----
 1 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 8434137..1ddb02c 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -439,12 +439,7 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
 			       cfg->pull_name, cfg->pull_reg, pull_orig, pull);
 	}
 #endif
-
-#ifdef CONFIG_OMAP_MUX_ERRORS
-	return warn ? -ETXTBSY : 0;
-#else
 	return 0;
-#endif
 }
 
 int __init omap1_mux_init(void)
-- 
1.7.0.4



From javier.martin at vista-silicon.com  Wed Jun 30 11:44:21 2010
From: javier.martin at vista-silicon.com (Javier Martin)
Date: Wed, 30 Jun 2010 17:44:21 +0200
Subject: [PATCH] Add support for Vista Silicon i.MX27 Visstrim_M10 board.
Message-ID: <1277912661-24065-1-git-send-email-javier.martin@vista-silicon.com>


Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
---
 arch/arm/mach-mx2/Kconfig                          |    8 +
 arch/arm/mach-mx2/Makefile                         |    1 +
 arch/arm/mach-mx2/mach-imx27_visstrim_m10.c        |  279 ++++++++++++++++++++
 .../include/mach/board-imx27_visstrim_m10.h        |   24 ++
 4 files changed, 312 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-mx2/mach-imx27_visstrim_m10.c
 create mode 100644 arch/arm/plat-mxc/include/mach/board-imx27_visstrim_m10.h

diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index 742fd4e..432eb78 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -91,6 +91,14 @@ config MACH_MX27_3DS
 	  Include support for MX27PDK platform. This includes specific
 	  configurations for the board and its peripherals.
 
+config MACH_IMX27_VISSTRIM_M10
+	bool "Vista Silicon i.MX27 Visstrim_m10"
+	depends on MACH_MX27
+	help
+	  Include support for Visstrim_m10 platform and its different variants.
+	  This includes specific configurations for the board and its
+	  peripherals.
+
 config MACH_IMX27LITE
 	bool "LogicPD MX27 LITEKIT platform"
 	depends on MACH_MX27
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index e3254fa..fbc54a9 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
 obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
 obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
+obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
 obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
 obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
 obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
diff --git a/arch/arm/mach-mx2/mach-imx27_visstrim_m10.c b/arch/arm/mach-mx2/mach-imx27_visstrim_m10.c
new file mode 100644
index 0000000..1acd47a
--- /dev/null
+++ b/arch/arm/mach-mx2/mach-imx27_visstrim_m10.c
@@ -0,0 +1,279 @@
+/*
+ * mach-imx27_visstrim_m10.c
+ *
+ * Copyright 2010 Vista Silicon S.L.
+ *		Javier Martin <javier.martin at vista-silicon.com>
+ *
+ * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA  02111-1307  USA
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <mach/common.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/gpio.h>
+#include <mach/mmc.h>
+#include <mach/imx-uart.h>
+#include <mach/iomux.h>
+#include <mach/board-imx27_visstrim_m10.h>
+#include <mach/mxc_ehci.h>
+#include <mach/i2c.h>
+#include <linux/i2c.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include "devices.h"
+
+static int visstrim_m10_pins[] = {
+	/* UART1 (console) */
+	PE12_PF_UART1_TXD,
+	PE13_PF_UART1_RXD,
+	PE14_PF_UART1_CTS,
+	PE15_PF_UART1_RTS,
+	/* FEC */
+	PD0_AIN_FEC_TXD0,
+	PD1_AIN_FEC_TXD1,
+	PD2_AIN_FEC_TXD2,
+	PD3_AIN_FEC_TXD3,
+	PD4_AOUT_FEC_RX_ER,
+	PD5_AOUT_FEC_RXD1,
+	PD6_AOUT_FEC_RXD2,
+	PD7_AOUT_FEC_RXD3,
+	PD8_AF_FEC_MDIO,
+	PD9_AIN_FEC_MDC,
+	PD10_AOUT_FEC_CRS,
+	PD11_AOUT_FEC_TX_CLK,
+	PD12_AOUT_FEC_RXD0,
+	PD13_AOUT_FEC_RX_DV,
+	PD14_AOUT_FEC_RX_CLK,
+	PD15_AOUT_FEC_COL,
+	PD16_AIN_FEC_TX_ER,
+	PF23_AIN_FEC_TX_EN,
+	/* SDHC1 */
+	PE18_PF_SD1_D0,
+	PE19_PF_SD1_D1,
+	PE20_PF_SD1_D2,
+	PE21_PF_SD1_D3,
+	PE22_PF_SD1_CMD,
+	PE23_PF_SD1_CLK,
+	/* I2C1 */
+	PD17_PF_I2C_DATA,
+	PD18_PF_I2C_CLK,
+	/* USB OTG */
+	OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
+	PC9_PF_USBOTG_DATA0,
+	PC11_PF_USBOTG_DATA1,
+	PC10_PF_USBOTG_DATA2,
+	PC13_PF_USBOTG_DATA3,
+	PC12_PF_USBOTG_DATA4,
+	PC7_PF_USBOTG_DATA5,
+	PC8_PF_USBOTG_DATA6,
+	PE25_PF_USBOTG_DATA7,
+	PE24_PF_USBOTG_CLK,
+	PE2_PF_USBOTG_DIR,
+	PE0_PF_USBOTG_NXT,
+	PE1_PF_USBOTG_STP,
+	PB23_PF_USB_PWR,
+	PB24_PF_USB_OC,
+};
+
+/* GPIOs used as events for applications */
+static struct gpio_keys_button visstrim_gpio_keys[] = {
+	{
+		.type	= EV_KEY,
+		.code	= KEY_RESTART,
+		.gpio	= (GPIO_PORTC + 15),
+		.desc	= "Default config",
+		.active_low = 0,
+		.wakeup = 1,
+	},
+	{
+		.type	= EV_KEY,
+		.code	= KEY_RECORD,
+		.gpio	= (GPIO_PORTF + 14),
+		.desc	= "Record",
+		.active_low = 0,
+		.wakeup = 1,
+	},
+	{
+		.type   = EV_KEY,
+		.code   = KEY_STOP,
+		.gpio   = (GPIO_PORTF + 13),
+		.desc   = "Stop",
+		.active_low = 0,
+		.wakeup = 1,
+	}
+};
+
+static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = {
+	.buttons	= visstrim_gpio_keys,
+	.nbuttons	= ARRAY_SIZE(visstrim_gpio_keys),
+};
+
+static struct platform_device visstrim_gpio_keys_device = {
+	.name	= "gpio-keys",
+	.id	= -1,
+	.dev	= {
+		.platform_data	= &visstrim_gpio_keys_platform_data,
+	},
+};
+
+/* Visstrim_SM10 has a microSD slot connected to sdhc2*/
+static int visstrim_m10_sdhc1_init(struct device *dev,
+		irq_handler_t detect_irq, void *data)
+{
+	int ret;
+
+	ret = request_irq(IRQ_GPIOB(25), detect_irq, IRQF_TRIGGER_FALLING,
+				"mmc-detect", data);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
+{
+	free_irq(IRQ_GPIOB(25), data);
+}
+
+static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = {
+	.init = visstrim_m10_sdhc1_init,
+	.exit = visstrim_m10_sdhc1_exit,
+};
+
+/* Visstrim_SM10 NOR flash */
+static struct physmap_flash_data visstrim_m10_flash_data = {
+	.width = 2,
+};
+
+static struct resource visstrim_m10_flash_resource = {
+	.start = 0xc0000000,
+	.end = 0xc0000000 + 0x04000000 - 1,
+	.flags = IORESOURCE_MEM,
+
+};
+
+static struct platform_device visstrim_m10_nor_mtd_device = {
+	.name = "physmap-flash",
+	.id = 0,
+	.dev = {
+		.platform_data = &visstrim_m10_flash_data,
+	},
+	.num_resources = 1,
+	.resource = &visstrim_m10_flash_resource,
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+	&visstrim_m10_nor_mtd_device,
+	&mxc_fec_device,
+};
+
+/* Visstrim_M10 uses UART0 as console */
+static struct imxuart_platform_data uart_pdata[] = {
+	{
+		.flags = IMXUART_HAVE_RTSCTS,
+	},
+};
+
+/* Visstrim_M10 has several devices attached to I2C1 */
+static struct imxi2c_platform_data visstrim_m10_i2c_1_data = {
+	.bitrate = 100000,
+};
+
+static int visstrim_m10_pca9555_setup(struct i2c_client *client,
+				unsigned gpio_base, unsigned ngpio,
+				void *context)
+{
+	int i;
+
+	for (i = 0; i < ngpio; i++) {
+		gpio_request(gpio_base + i, "Visstrim_m10 GPIO Exp");
+		gpio_export(gpio_base + i, 1);
+	}
+	return 0;
+}
+
+static struct pca953x_platform_data visstrim_m10_pca9555_pdata = {
+	.gpio_base = 240, /* After MX27 internal GPIOs */
+	.invert = 0,
+	.setup = visstrim_m10_pca9555_setup,
+};
+
+static struct i2c_board_info visstrim_m10_i2c_devices[] = {
+	{
+		I2C_BOARD_INFO("pca9555", 0x20),
+		.platform_data = &visstrim_m10_pca9555_pdata,
+	},
+};
+
+/* USB OTG */
+static int otg_phy_init(struct platform_device *pdev)
+{
+	gpio_set_value(OTG_PHY_CS_GPIO, 0);
+	return 0;
+}
+
+static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = {
+	.init = otg_phy_init,
+	.portsc	= MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+	.flags	= MXC_EHCI_POWER_PINS_ENABLED,
+};
+
+static void __init visstrim_m10_board_init(void)
+{
+	int ret;
+
+	ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins,
+			ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10");
+	if (ret)
+		printk(KERN_ERR "visstrim_m10: Failed tu setup pins (%d)\n",
+				ret);
+
+	mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+
+	i2c_register_board_info(0, visstrim_m10_i2c_devices,
+				ARRAY_SIZE(visstrim_m10_i2c_devices));
+
+	mxc_register_device(&mxc_i2c_device0, &visstrim_m10_i2c_1_data);
+	mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata);
+	mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata);
+	platform_device_register(&visstrim_gpio_keys_device);
+	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+
+static void __init visstrim_m10_timer_init(void)
+{
+	mx27_clocks_init((unsigned long)25000000);
+}
+
+static struct sys_timer visstrim_m10_timer = {
+	.init	= visstrim_m10_timer_init,
+};
+
+MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
+	.phys_io        = MX27_AIPI_BASE_ADDR,
+	.io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+	.boot_params    = MX27_PHYS_OFFSET + 0x100,
+	.map_io         = mx27_map_io,
+	.init_irq       = mx27_init_irq,
+	.init_machine   = visstrim_m10_board_init,
+	.timer          = &visstrim_m10_timer,
+MACHINE_END
diff --git a/arch/arm/plat-mxc/include/mach/board-imx27_visstrim_m10.h b/arch/arm/plat-mxc/include/mach/board-imx27_visstrim_m10.h
new file mode 100644
index 0000000..9ef1531
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-imx27_visstrim_m10.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2009 Javier Martin - javier.martin at vista-silicon.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef __ASM_ARCH_MXC_BOARD_IMX27_VISSTRIM_M10_H__
+#define __ASM_ARCH_MXC_BOARD_IMX27_VISSTRIM_M10_H__
+
+	#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
+
+#endif		/* __ASM_ARCH_MXC_BOARD_IMX27_VISSTRIM_M10_H__ */
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:55:03 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:55:03 +0200
Subject: [PATCH 04/33] Removing dead MSM7X00A_IDLE
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <c7e75d44aebaaabfdff9cf5fbda54512d0062728.1277911346.git.siccegge@cs.fau.de>

MSM7X00A_IDLE doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-msm/idle.S |   13 -------------
 1 files changed, 0 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-msm/idle.S b/arch/arm/mach-msm/idle.S
index 6a94f05..d8e8027 100644
--- a/arch/arm/mach-msm/idle.S
+++ b/arch/arm/mach-msm/idle.S
@@ -20,17 +20,4 @@
 #include <asm/assembler.h>
 
 ENTRY(arch_idle)
-#ifdef CONFIG_MSM7X00A_IDLE
-	mrc     p15, 0, r1, c1, c0, 0    /* read current CR    */
-	bic     r0, r1, #(1 << 2)        /* clear dcache bit   */
-	bic     r0, r0, #(1 << 12)       /* clear icache bit   */
-	mcr     p15, 0, r0, c1, c0, 0    /* disable d/i cache  */
-
-	mov     r0, #0                   /* prepare wfi value  */
-	mcr     p15, 0, r0, c7, c10, 0   /* flush the cache    */
-	mcr     p15, 0, r0, c7, c10, 4   /* memory barrier     */
-	mcr     p15, 0, r0, c7, c0, 4    /* wait for interrupt */
-
-	mcr     p15, 0, r1, c1, c0, 0    /* restore d/i cache  */
-#endif
 	mov     pc, lr
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:55:22 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:55:22 +0200
Subject: [PATCH 05/33] Removing dead OMAP_IR
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <b7209c2cb666c73a3affbb44c2637a4f2086af08.1277911346.git.siccegge@cs.fau.de>

OMAP_IR doesn't exist in Kconfig, therefore removing all references
for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-omap1/board-h2.c |   18 ------------------
 arch/arm/mach-omap2/board-h4.c |    4 ----
 2 files changed, 0 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index d1100e4..d7640d3 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -292,15 +292,6 @@ static struct platform_device h2_kp_device = {
 
 #define H2_IRDA_FIRSEL_GPIO_PIN	17
 
-#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
-static int h2_transceiver_mode(struct device *dev, int state)
-{
-	/* SIR when low, else MIR/FIR when HIGH */
-	gpio_set_value(H2_IRDA_FIRSEL_GPIO_PIN, !(state & IR_SIRMODE));
-	return 0;
-}
-#endif
-
 static struct omap_irda_config h2_irda_data = {
 	.transceiver_cap	= IR_SIRMODE | IR_MIRMODE | IR_FIRMODE,
 	.rx_channel		= OMAP_DMA_UART3_RX,
@@ -437,15 +428,6 @@ static void __init h2_init(void)
 	/* omap_cfg_reg(U19_ARMIO1); */		/* CD */
 	omap_cfg_reg(BALLOUT_V8_ARMIO3);	/* WP */
 
-	/* Irda */
-#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
-	omap_writel(omap_readl(FUNC_MUX_CTRL_A) | 7, FUNC_MUX_CTRL_A);
-	if (gpio_request(H2_IRDA_FIRSEL_GPIO_PIN, "IRDA mode") < 0)
-		BUG();
-	gpio_direction_output(H2_IRDA_FIRSEL_GPIO_PIN, 0);
-	h2_irda_data.transceiver_mode = h2_transceiver_mode;
-#endif
-
 	platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
 	omap_board_config = h2_config;
 	omap_board_config_size = ARRAY_SIZE(h2_config);
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 0665f2c..ce4292b 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -345,10 +345,6 @@ static void __init omap_h4_init(void)
 	 * You have to mux them off in device drivers later on
 	 * if not needed.
 	 */
-#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
-	omap_cfg_reg(K15_24XX_UART3_TX);
-	omap_cfg_reg(K14_24XX_UART3_RX);
-#endif
 
 #if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
 	if (omap_has_menelaus()) {
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:55:42 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:55:42 +0200
Subject: [PATCH 06/33] Removing dead SHARPSL_LOCOMO
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <b43850b1a1909496718e39687d1ca00543aa30ec.1277911346.git.siccegge@cs.fau.de>

SHARPSL_LOCOMO doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-sa1100/include/mach/irqs.h |    2 --
 1 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
index 8c8845b..123c6c9 100644
--- a/arch/arm/mach-sa1100/include/mach/irqs.h
+++ b/arch/arm/mach-sa1100/include/mach/irqs.h
@@ -77,8 +77,6 @@
  */
 #ifdef CONFIG_SA1111
 #define NR_IRQS			(IRQ_BOARD_END + 55)
-#elif defined(CONFIG_SHARPSL_LOCOMO)
-#define NR_IRQS			(IRQ_BOARD_START + 4)
 #else
 #define NR_IRQS			(IRQ_BOARD_START)
 #endif
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:56:03 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:56:03 +0200
Subject: [PATCH 07/33] Removing dead CPU_S3C2400
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <5faaae77335d035246d1985c4c6c46830188d85e.1277911346.git.siccegge@cs.fau.de>

CPU_S3C2400 doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-s3c2410/include/mach/gpio-fns.h  |    5 ----
 arch/arm/mach-s3c2410/include/mach/regs-gpio.h |    4 ---
 arch/arm/plat-s3c24xx/cpu.c                    |   15 -----------
 arch/arm/plat-s3c24xx/include/plat/s3c2400.h   |   31 ------------------------
 4 files changed, 0 insertions(+), 55 deletions(-)
 delete mode 100644 arch/arm/plat-s3c24xx/include/plat/s3c2400.h

diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
index f453c4f..fdee4be 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -52,11 +52,6 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
 
 extern int s3c2410_gpio_getirq(unsigned int pin);
 
-#ifdef CONFIG_CPU_S3C2400
-
-extern int s3c2400_gpio_getirq(unsigned int pin);
-
-#endif /* CONFIG_CPU_S3C2400 */
 
 /* s3c2410_gpio_irqfilter
  *
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index a0a89d4..d4a3ad7 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -16,11 +16,7 @@
 
 #include <mach/gpio-nrs.h>
 
-#ifdef CONFIG_CPU_S3C2400
-#define S3C24XX_MISCCR		S3C2400_MISCCR
-#else
 #define S3C24XX_MISCCR		S3C24XX_GPIOREG2(0x80)
-#endif /* CONFIG_CPU_S3C2400 */
 
 /* general configuration options */
 
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 76d0858..edbbbe7 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -46,7 +46,6 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
-#include <plat/s3c2400.h>
 #include <plat/s3c2410.h>
 #include <plat/s3c2412.h>
 #include <plat/s3c2416.h>
@@ -55,7 +54,6 @@
 
 /* table of supported CPUs */
 
-static const char name_s3c2400[]  = "S3C2400";
 static const char name_s3c2410[]  = "S3C2410";
 static const char name_s3c2412[]  = "S3C2412";
 static const char name_s3c2416[]  = "S3C2416/S3C2450";
@@ -157,15 +155,6 @@ static struct cpu_table cpu_ids[] __initdata = {
 		.init		= s3c2443_init,
 		.name		= name_s3c2443,
 	},
-	{
-		.idcode		= 0x0,   /* S3C2400 doesn't have an idcode */
-		.idmask		= 0xffffffff,
-		.map_io		= s3c2400_map_io,
-		.init_clocks	= s3c2400_init_clocks,
-		.init_uarts	= s3c2400_init_uarts,
-		.init		= s3c2400_init,
-		.name		= name_s3c2400
-	},
 };
 
 /* minimal IO mapping */
@@ -200,11 +189,7 @@ static unsigned long s3c24xx_read_idcode_v5(void)
 
 static unsigned long s3c24xx_read_idcode_v4(void)
 {
-#ifndef CONFIG_CPU_S3C2400
 	return __raw_readl(S3C2410_GSTATUS1);
-#else
-	return 0UL;
-#endif
 }
 
 /* Hook for arm_pm_restart to ensure we execute the reset code
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
deleted file mode 100644
index b3feaea..0000000
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2400.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *	Ben Dooks <ben at simtec.co.uk>
- *
- * Header file for S3C2400 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Modifications:
- *     09-Fev-2006 LCVR  First version, based on s3c2410.h
-*/
-
-#ifdef CONFIG_CPU_S3C2400
-
-extern  int s3c2400_init(void);
-
-extern void s3c2400_map_io(void);
-
-extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2400_init_clocks(int xtal);
-
-#else
-#define s3c2400_init_clocks NULL
-#define s3c2400_init_uarts NULL
-#define s3c2400_map_io NULL
-#define s3c2400_init NULL
-#endif
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:56:26 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:56:26 +0200
Subject: [PATCH 08/33] Removing dead SA1101
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <7488ec29cdb90212e965f6cd1173141c576c0955.1277911346.git.siccegge@cs.fau.de>

SA1101 doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-sa1100/include/mach/SA-1101.h  |  925 --------------------------
 arch/arm/mach-sa1100/include/mach/hardware.h |    4 -
 2 files changed, 0 insertions(+), 929 deletions(-)
 delete mode 100644 arch/arm/mach-sa1100/include/mach/SA-1101.h

diff --git a/arch/arm/mach-sa1100/include/mach/SA-1101.h b/arch/arm/mach-sa1100/include/mach/SA-1101.h
deleted file mode 100644
index 5d2ad7d..0000000
--- a/arch/arm/mach-sa1100/include/mach/SA-1101.h
+++ /dev/null
@@ -1,925 +0,0 @@
-/*
- * SA-1101.h
- *
- * Copyright (c) Peter Danielsson 1999
- *
- * Definition of constants related to the sa1101
- * support chip for the sa1100
- *
- */
-
-
-/* Be sure that virtual mapping is defined right */
-#ifndef __ASM_ARCH_HARDWARE_H
-#error You must include hardware.h not SA-1101.h
-#endif
-
-#ifndef SA1101_BASE
-#error You must define SA-1101 physical base address
-#endif
-
-#ifndef LANGUAGE
-# ifdef __ASSEMBLY__
-#  define LANGUAGE Assembly
-# else
-#  define LANGUAGE C
-# endif
-#endif
-
-/*
- * We have mapped the sa1101 depending on the value of SA1101_BASE.
- * It then appears from 0xf4000000.
- */
-
-#define SA1101_p2v( x )         ((x) - SA1101_BASE + 0xf4000000)
-#define SA1101_v2p( x )         ((x) - 0xf4000000  + SA1101_BASE)
-
-#ifndef SA1101_p2v
-#define SA1101_p2v(PhAdd)  (PhAdd)
-#endif
-
-#include <mach/bitfield.h>
-
-#define C               0
-#define Assembly        1
-
-
-/*
- * Memory map
- */
-
-#define __SHMEM_CONTROL0	0x00000000
-#define __SYSTEM_CONTROL1	0x00000400
-#define __ARBITER		0x00020000
-#define __SYSTEM_CONTROL2	0x00040000
-#define __SYSTEM_CONTROL3	0x00060000
-#define __PARALLEL_PORT		0x00080000
-#define __VIDMEM_CONTROL	0x00100000
-#define __UPDATE_FIFO		0x00120000
-#define __SHMEM_CONTROL1	0x00140000
-#define __INTERRUPT_CONTROL	0x00160000
-#define __USB_CONTROL		0x00180000
-#define __TRACK_INTERFACE	0x001a0000
-#define __MOUSE_INTERFACE	0x001b0000
-#define __KEYPAD_INTERFACE	0x001c0000
-#define __PCMCIA_INTERFACE	0x001e0000
-#define	__VGA_CONTROL		0x00200000
-#define __GPIO_INTERFACE	0x00300000
-
-/*
- * Macro that calculates real address for registers in the SA-1101
- */
-
-#define _SA1101( x )    ((x) + SA1101_BASE)
-
-/*
- * Interface and shared memory controller registers
- *
- * Registers
- *	SKCR		SA-1101 control register (read/write)
- *	SMCR		Shared Memory Controller Register
- *	SNPR		Snoop Register
- */
-
-#define _SKCR		_SA1101( 0x00000000 ) /* SA-1101 Control Reg. */
-#define _SMCR		_SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */
-#define _SNPR		_SA1101( 0x00140400 ) /* Snoop Reg. */
-
-#if LANGUAGE == C
-#define SKCR		(*((volatile Word *) SA1101_p2v (_SKCR)))
-#define SMCR		(*((volatile Word *) SA1101_p2v (_SMCR)))
-#define SNPR		(*((volatile Word *) SA1101_p2v (_SNPR)))
-
-#define SKCR_PLLEn	  0x0001	  /* Enable On-Chip PLL */
-#define SKCR_BCLKEn	  0x0002	  /* Enables BCLK */
-#define SKCR_Sleep	  0x0004	  /* Sleep Mode */
-#define SKCR_IRefEn	  0x0008	  /* DAC Iref input enable */
-#define SKCR_VCOON	  0x0010	  /* VCO bias */
-#define SKCR_ScanTestEn	  0x0020	  /* Enables scan test */
-#define SKCR_ClockTestEn  0x0040	  /* Enables clock test */
-
-#define SMCR_DCAC	  Fld(2,0)	  /* Number of column address bits */
-#define SMCR_DRAC	  Fld(2,2)	  /* Number of row address bits */
-#define SMCR_ArbiterBias  0x0008	  /* favor video or USB */
-#define SMCR_TopVidMem	  Fld(4,5)	  /* Top 4 bits of vidmem addr. */
-
-#define SMCR_ColAdrBits( x )		  /* col. addr bits 8..11 */ \
-	(( (x) - 8 ) << FShft (SMCR_DCAC))
-#define SMCR_RowAdrBits( x )		  /* row addr bits 9..12 */\
-	(( (x) - 9 ) << FShft (SMCR_DRAC))
-
-#define SNPR_VFBstart	  Fld(12,0)	/* Video frame buffer addr */
-#define SNPR_VFBsize	  Fld(11,12)	/* Video frame buffer size */
-#define SNPR_WholeBank	  (1 << 23)	/* Whole bank bit */
-#define SNPR_BankSelect	  Fld(2,27)	/* Bank select */
-#define SNPR_SnoopEn	  (1 << 31)	/* Enable snoop operation */
-
-#define SNPR_Set_VFBsize( x )   /* set frame buffer size (in kb) */ \
-	( (x) << FShft (SNPR_VFBsize))
-#define SNPR_Select_Bank(x)     /* select bank 0 or 1 */  \
-	(( (x) + 1 ) << FShft (SNPR_BankSelect ))
-
-#endif /* LANGUAGE == C */
-
-/*
- * Video Memory Controller
- *
- * Registers
- *    VMCCR	Configuration register
- *    VMCAR	VMC address register
- *    VMCDR	VMC data register
- *
- */
-
-#define _VMCCR		_SA1101( 0x00100000 )	/* Configuration register */
-#define _VMCAR		_SA1101( 0x00101000 )	/* VMC address register */
-#define _VMCDR		_SA1101( 0x00101400 )	/* VMC data register */
-
-#if LANGUAGE == C
-#define VMCCR		(*((volatile Word *) SA1101_p2v (_VMCCR)))
-#define VMCAR		(*((volatile Word *) SA1101_p2v (_VMCAR)))
-#define VMCDR		(*((volatile Word *) SA1101_p2v (_VMCDR)))
-
-#define VMCCR_RefreshEn	    0x0000	  /* Enable memory refresh */
-#define VMCCR_Config	    0x0001	  /* DRAM size */
-#define VMCCR_RefPeriod	    Fld(2,3)	  /* Refresh period */
-#define VMCCR_StaleDataWait Fld(4,5)	  /* Stale FIFO data timeout counter */
-#define VMCCR_SleepState    (1<<9)	  /* State of interface pins in sleep*/
-#define VMCCR_RefTest	    (1<<10)	  /* refresh test */
-#define VMCCR_RefLow	    Fld(6,11)	  /* refresh low counter */
-#define VMCCR_RefHigh	    Fld(7,17)	  /* refresh high counter */
-#define VMCCR_SDTCTest	    Fld(7,24)	  /* stale data timeout counter */
-#define VMCCR_ForceSelfRef  (1<<31)	  /* Force self refresh */
-
-#endif LANGUAGE == C
-
-
-/* Update FIFO
- *
- * Registers
- *    UFCR	Update FIFO Control Register
- *    UFSR	Update FIFO Status Register
- *    UFLVLR	update FIFO level register
- *    UFDR	update FIFO data register
- */
-
-#define _UFCR	_SA1101(0x00120000)   /* Update FIFO Control Reg. */
-#define _UFSR	_SA1101(0x00120400)   /* Update FIFO Status Reg. */	
-#define _UFLVLR	_SA1101(0x00120800)   /* Update FIFO level reg. */
-#define _UFDR	_SA1101(0x00120c00)   /* Update FIFO data reg. */
-
-#if LANGUAGE == C
-
-#define UFCR 	(*((volatile Word *) SA1101_p2v (_UFCR)))
-#define UFSR	(*((volatile Word *) SA1101_p2v (_UFSR)))
-#define UFLVLR	(*((volatile Word *) SA1101_p2v (_UFLVLR))) 
-#define UFDR	(*((volatile Word *) SA1101_p2v (_UFDR)))
-
-
-#define UFCR_FifoThreshhold	Fld(7,0)	/* Level for FifoGTn flag */
-
-#define UFSR_FifoGTnFlag	0x01		/* FifoGTn flag */#define UFSR_FifoEmpty		0x80		/* FIFO is empty */
-
-#endif /* LANGUAGE == C */
-
-/* System Controller
- *
- * Registers
- *    SKPCR	Power Control Register
- *    SKCDR	Clock Divider Register
- *    DACDR1	DAC1 Data register
- *    DACDR2	DAC2 Data register
- */
-
-#define _SKPCR		_SA1101(0x00000400)
-#define _SKCDR		_SA1101(0x00040000)
-#define _DACDR1		_SA1101(0x00060000)
-#define _DACDR2		_SA1101(0x00060400)
-
-#if LANGUAGE == C
-#define SKPCR 	(*((volatile Word *) SA1101_p2v (_SKPCR)))
-#define SKCDR	(*((volatile Word *) SA1101_p2v (_SKCDR)))
-#define DACDR1	(*((volatile Word *) SA1101_p2v (_DACDR1)))
-#define DACDR2	(*((volatile Word *) SA1101_p2v (_DACDR2)))
-
-#define SKPCR_UCLKEn	     0x01    /* USB Enable */
-#define SKPCR_PCLKEn	     0x02    /* PS/2 Enable */
-#define SKPCR_ICLKEn	     0x04    /* Interrupt Controller Enable */
-#define SKPCR_VCLKEn	     0x08    /* Video Controller Enable */
-#define SKPCR_PICLKEn	     0x10    /* parallel port Enable */
-#define SKPCR_DCLKEn	     0x20    /* DACs Enable */
-#define SKPCR_nKPADEn	     0x40    /* Multiplexer */
-
-#define SKCDR_PLLMul	     Fld(7,0)	/* PLL Multiplier */
-#define SKCDR_VCLKEn	     Fld(2,7)	/* Video controller clock divider */
-#define SKDCR_BCLKEn	     (1<<9)	/* BCLK Divider */
-#define SKDCR_UTESTCLKEn     (1<<10)	/* Route USB clock during test mode */
-#define SKDCR_DivRValue	     Fld(6,11)	/* Input clock divider for PLL */
-#define SKDCR_DivNValue	     Fld(5,17)	/* Output clock divider for PLL */
-#define SKDCR_PLLRSH	     Fld(3,22)	/* PLL bandwidth control */
-#define SKDCR_ChargePump     (1<<25)	/* Charge pump control */
-#define SKDCR_ClkTestMode    (1<<26)	/* Clock output test mode */
-#define SKDCR_ClkTestEn	     (1<<27)	/* Test clock generator */
-#define SKDCR_ClkJitterCntl  Fld(3,28)	/* video clock jitter compensation */
-
-#define DACDR_DACCount	     Fld(8,0)	/* Count value */
-#define DACDR1_DACCount	     DACDR_DACCount
-#define DACDR2_DACCount	     DACDR_DACCount
-
-#endif /* LANGUAGE == C */
-
-/*
- * Parallel Port Interface
- *
- * Registers
- *    IEEE_Config	IEEE mode selection and programmable attributes
- *    IEEE_Control	Controls the states of IEEE port control outputs
- *    IEEE_Data		Forward transfer data register
- *    IEEE_Addr		Forward transfer address register
- *    IEEE_Status	Port IO signal status register
- *    IEEE_IntStatus	Port interrupts status register
- *    IEEE_FifoLevels   Rx and Tx FIFO interrupt generation levels
- *    IEEE_InitTime	Forward timeout counter initial value
- *    IEEE_TimerStatus	Forward timeout counter current value
- *    IEEE_FifoReset	Reset forward transfer FIFO
- *    IEEE_ReloadValue	Counter reload value
- *    IEEE_TestControl	Control testmode
- *    IEEE_TestDataIn	Test data register
- *    IEEE_TestDataInEn	Enable test data
- *    IEEE_TestCtrlIn	Test control signals
- *    IEEE_TestCtrlInEn	Enable test control signals
- *    IEEE_TestDataStat	Current data bus value
- *
- */
-
-/*
- * The control registers are defined as offsets from a base address 
- */
- 
-#define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT )
-
-#define _IEEE_Config	    _IEEE( 0x0000 )
-#define _IEEE_Control	    _IEEE( 0x0400 )
-#define _IEEE_Data	    _IEEE( 0x4000 )
-#define _IEEE_Addr	    _IEEE( 0x0800 )
-#define _IEEE_Status	    _IEEE( 0x0c00 )
-#define _IEEE_IntStatus	    _IEEE( 0x1000 )
-#define _IEEE_FifoLevels    _IEEE( 0x1400 )
-#define _IEEE_InitTime	    _IEEE( 0x1800 )
-#define _IEEE_TimerStatus   _IEEE( 0x1c00 )
-#define _IEEE_FifoReset	    _IEEE( 0x2000 )
-#define _IEEE_ReloadValue   _IEEE( 0x3c00 )
-#define _IEEE_TestControl   _IEEE( 0x2400 )
-#define _IEEE_TestDataIn    _IEEE( 0x2800 )
-#define _IEEE_TestDataInEn  _IEEE( 0x2c00 )
-#define _IEEE_TestCtrlIn    _IEEE( 0x3000 )
-#define _IEEE_TestCtrlInEn  _IEEE( 0x3400 )
-#define _IEEE_TestDataStat  _IEEE( 0x3800 )
- 
-
-#if LANGUAGE == C
-#define IEEE_Config	    (*((volatile Word *) SA1101_p2v (_IEEE_Config)))
-#define IEEE_Control	    (*((volatile Word *) SA1101_p2v (_IEEE_Control)))
-#define IEEE_Data	    (*((volatile Word *) SA1101_p2v (_IEEE_Data)))
-#define IEEE_Addr	    (*((volatile Word *) SA1101_p2v (_IEEE_Addr)))
-#define IEEE_Status	    (*((volatile Word *) SA1101_p2v (_IEEE_Status)))
-#define IEEE_IntStatus	    (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus)))
-#define IEEE_FifoLevels	    (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels)))
-#define IEEE_InitTime	    (*((volatile Word *) SA1101_p2v (_IEEE_InitTime)))
-#define IEEE_TimerStatus    (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus)))
-#define IEEE_FifoReset	    (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset)))
-#define IEEE_ReloadValue    (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue)))
-#define IEEE_TestControl    (*((volatile Word *) SA1101_p2v (_IEEE_TestControl)))
-#define IEEE_TestDataIn     (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn)))
-#define IEEE_TestDataInEn   (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn)))
-#define IEEE_TestCtrlIn     (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn)))
-#define IEEE_TestCtrlInEn   (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn)))
-#define IEEE_TestDataStat   (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat)))
-
-
-#define IEEE_Config_M	    Fld(3,0)	 /* Mode select */
-#define IEEE_Config_D	    0x04	 /* FIFO access enable */
-#define IEEE_Config_B	    0x08	 /* 9-bit word enable */
-#define IEEE_Config_T	    0x10	 /* Data transfer enable */
-#define IEEE_Config_A	    0x20	 /* Data transfer direction */
-#define IEEE_Config_E	    0x40	 /* Timer enable */
-#define IEEE_Control_A	    0x08	 /* AutoFd output */
-#define IEEE_Control_E	    0x04	 /* Selectin output */
-#define IEEE_Control_T	    0x02	 /* Strobe output */
-#define IEEE_Control_I	    0x01	 /* Port init output */
-#define IEEE_Data_C	    (1<<31)	 /* Byte count */
-#define IEEE_Data_Db	    Fld(9,16)	 /* Data byte 2 */
-#define IEEE_Data_Da	    Fld(9,0)	 /* Data byte 1 */
-#define IEEE_Addr_A	    Fld(8,0)	 /* forward address transfer byte */
-#define IEEE_Status_A	    0x0100	 /* nAutoFd port output status */
-#define IEEE_Status_E	    0x0080	 /* nSelectIn port output status */
-#define IEEE_Status_T	    0x0040	 /* nStrobe port output status */
-#define IEEE_Status_I	    0x0020	 /* nInit port output status */
-#define IEEE_Status_B	    0x0010	 /* Busy port inout status */
-#define IEEE_Status_S	    0x0008	 /* Select port input status */
-#define IEEE_Status_K	    0x0004	 /* nAck port input status */
-#define IEEE_Status_F	    0x0002	 /* nFault port input status */
-#define IEEE_Status_R	    0x0001	 /* pError port input status */
-
-#define IEEE_IntStatus_IntReqDat	 0x0100
-#define IEEE_IntStatus_IntReqEmp	 0x0080
-#define IEEE_IntStatus_IntReqInt	 0x0040
-#define IEEE_IntStatus_IntReqRav	 0x0020
-#define IEEE_IntStatus_IntReqTim	 0x0010
-#define IEEE_IntStatus_RevAddrComp	 0x0008
-#define IEEE_IntStatus_RevDataComp	 0x0004
-#define IEEE_IntStatus_FwdAddrComp	 0x0002
-#define IEEE_IntStatus_FwdDataComp	 0x0001
-#define IEEE_FifoLevels_RevFifoLevel	 2
-#define IEEE_FifoLevels_FwdFifoLevel	 1
-#define IEEE_InitTime_TimValInit	 Fld(22,0)
-#define IEEE_TimerStatus_TimValStat	 Fld(22,0)
-#define IEEE_ReloadValue_Reload		 Fld(4,0)
-
-#define IEEE_TestControl_RegClk		 0x04
-#define IEEE_TestControl_ClockSelect	 Fld(2,1)
-#define IEEE_TestControl_TimerTestModeEn 0x01
-#define IEEE_TestCtrlIn_PError		 0x10
-#define IEEE_TestCtrlIn_nFault		 0x08
-#define IEEE_TestCtrlIn_nAck		 0x04
-#define IEEE_TestCtrlIn_PSel		 0x02
-#define IEEE_TestCtrlIn_Busy		 0x01
-
-#endif /* LANGUAGE == C */
-
-/*
- * VGA Controller
- *
- * Registers
- *    VideoControl	Video Control Register
- *    VgaTiming0	VGA Timing Register 0
- *    VgaTiming1	VGA Timing Register 1
- *    VgaTiming2	VGA Timing Register 2
- *    VgaTiming3	VGA Timing Register 3
- *    VgaBorder		VGA Border Color Register
- *    VgaDBAR		VGADMA Base Address Register
- *    VgaDCAR		VGADMA Channel Current Address Register
- *    VgaStatus		VGA Status Register
- *    VgaInterruptMask	VGA Interrupt Mask Register
- *    VgaPalette	VGA Palette Registers
- *    DacControl	DAC Control Register
- *    VgaTest		VGA Controller Test Register
- */
-
-#define _VGA( x )	_SA1101( ( x ) + __VGA_CONTROL )
-
-#define _VideoControl	    _VGA( 0x0000 )
-#define _VgaTiming0	    _VGA( 0x0400 )
-#define _VgaTiming1	    _VGA( 0x0800 )
-#define _VgaTiming2	    _VGA( 0x0c00 )
-#define _VgaTiming3	    _VGA( 0x1000 )
-#define _VgaBorder	    _VGA( 0x1400 )
-#define _VgaDBAR	    _VGA( 0x1800 )
-#define _VgaDCAR	    _VGA( 0x1c00 )
-#define _VgaStatus	    _VGA( 0x2000 )
-#define _VgaInterruptMask   _VGA( 0x2400 )
-#define _VgaPalette	    _VGA( 0x40000 )
-#define _DacControl	    _VGA( 0x3000 )
-#define _VgaTest	    _VGA( 0x2c00 )
-
-#if (LANGUAGE == C)
-#define VideoControl   (*((volatile Word *) SA1101_p2v (_VideoControl)))
-#define VgaTiming0     (*((volatile Word *) SA1101_p2v (_VgaTiming0)))
-#define VgaTiming1     (*((volatile Word *) SA1101_p2v (_VgaTiming1)))
-#define VgaTiming2     (*((volatile Word *) SA1101_p2v (_VgaTiming2)))
-#define VgaTiming3     (*((volatile Word *) SA1101_p2v (_VgaTiming3)))
-#define VgaBorder      (*((volatile Word *) SA1101_p2v (_VgaBorder)))
-#define VgaDBAR	       (*((volatile Word *) SA1101_p2v (_VgaDBAR)))
-#define VgaDCAR	       (*((volatile Word *) SA1101_p2v (_VgaDCAR)))
-#define VgaStatus      (*((volatile Word *) SA1101_p2v (_VgaStatus)))
-#define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask)))
-#define VgaPalette     (*((volatile Word *) SA1101_p2v (_VgaPalette)))
-#define DacControl     (*((volatile Word *) SA1101_p2v (_DacControl)))
-#define VgaTest        (*((volatile Word *) SA1101_p2v (_VgaTest)))
-
-#define VideoControl_VgaEn    0x00000000
-#define VideoControl_BGR      0x00000001
-#define VideoControl_VCompVal Fld(2,2)
-#define VideoControl_VgaReq   Fld(4,4)
-#define VideoControl_VBurstL  Fld(4,8)
-#define VideoControl_VMode    (1<<12)
-#define VideoControl_PalRead  (1<<13)
-
-#define VgaTiming0_PPL	      Fld(6,2)
-#define VgaTiming0_HSW	      Fld(8,8)
-#define VgaTiming0_HFP	      Fld(8,16)
-#define VgaTiming0_HBP	      Fld(8,24)
-
-#define VgaTiming1_LPS	      Fld(10,0)
-#define VgaTiming1_VSW	      Fld(6,10)
-#define VgaTiming1_VFP	      Fld(8,16)
-#define VgaTiming1_VBP	      Fld(8,24)
-
-#define VgaTiming2_IVS	      0x01
-#define VgaTiming2_IHS	      0x02
-#define VgaTiming2_CVS	      0x04
-#define VgaTiming2_CHS	      0x08
-
-#define VgaTiming3_HBS	      Fld(8,0)
-#define VgaTiming3_HBE	      Fld(8,8)
-#define VgaTiming3_VBS	      Fld(8,16)
-#define VgaTiming3_VBE	      Fld(8,24)
-
-#define VgaBorder_BCOL	      Fld(24,0)
-
-#define VgaStatus_VFUF	      0x01
-#define VgaStatus_VNext	      0x02
-#define VgaStatus_VComp	      0x04
-
-#define VgaInterruptMask_VFUFMask   0x00
-#define VgaInterruptMask_VNextMask  0x01
-#define VgaInterruptMask_VCompMask  0x02
-
-#define VgaPalette_R	      Fld(8,0)
-#define VgaPalette_G	      Fld(8,8)
-#define VgaPalette_B	      Fld(8,16)
-
-#define DacControl_DACON      0x0001
-#define DacControl_COMPON     0x0002
-#define DacControl_PEDON      0x0004
-#define DacControl_RTrim      Fld(5,4)
-#define DacControl_GTrim      Fld(5,9)
-#define DacControl_BTrim      Fld(5,14)
-
-#define VgaTest_TDAC	      0x00
-#define VgaTest_Datatest      Fld(4,1)
-#define VgaTest_DACTESTDAC    0x10
-#define VgaTest_DACTESTOUT    Fld(3,5)
-
-#endif /* LANGUAGE == C */
-
-/*
- * USB Host Interface Controller
- *
- * Registers
- *    Revision
- *    Control
- *    CommandStatus
- *    InterruptStatus
- *    InterruptEnable
- *    HCCA
- *    PeriodCurrentED
- *    ControlHeadED
- *    BulkHeadED
- *    BulkCurrentED
- *    DoneHead
- *    FmInterval
- *    FmRemaining
- *    FmNumber
- *    PeriodicStart
- *    LSThreshold
- *    RhDescriptorA
- *    RhDescriptorB
- *    RhStatus
- *    RhPortStatus
- *    USBStatus
- *    USBReset
- *    USTAR
- *    USWER
- *    USRFR
- *    USNFR
- *    USTCSR
- *    USSR
- *    
- */
-
-#define _USB( x )	_SA1101( ( x ) + __USB_CONTROL )
-
-
-#define _Revision	  _USB( 0x0000 )
-#define _Control	  _USB( 0x0888 )
-#define _CommandStatus	  _USB( 0x0c00 )
-#define _InterruptStatus  _USB( 0x1000 )
-#define _InterruptEnable  _USB( 0x1400 )
-#define _HCCA		  _USB( 0x1800 )
-#define _PeriodCurrentED  _USB( 0x1c00 )
-#define _ControlHeadED	  _USB( 0x2000 )
-#define _BulkHeadED	  _USB( 0x2800 )
-#define _BulkCurrentED	  _USB( 0x2c00 )
-#define _DoneHead	  _USB( 0x3000 )
-#define _FmInterval	  _USB( 0x3400 )
-#define _FmRemaining	  _USB( 0x3800 )
-#define _FmNumber	  _USB( 0x3c00 )
-#define _PeriodicStart	  _USB( 0x4000 )
-#define _LSThreshold	  _USB( 0x4400 )
-#define _RhDescriptorA	  _USB( 0x4800 )
-#define _RhDescriptorB	  _USB( 0x4c00 )
-#define _RhStatus	  _USB( 0x5000 )
-#define _RhPortStatus	  _USB( 0x5400 )
-#define _USBStatus	  _USB( 0x11800 )
-#define _USBReset	  _USB( 0x11c00 )
-
-#define _USTAR		  _USB( 0x10400 )
-#define _USWER		  _USB( 0x10800 )
-#define _USRFR		  _USB( 0x10c00 )
-#define _USNFR		  _USB( 0x11000 )
-#define _USTCSR		  _USB( 0x11400 )
-#define _USSR		  _USB( 0x11800 )
-
-
-#if (LANGUAGE == C)
-
-#define Revision	(*((volatile Word *) SA1101_p2v (_Revision)))
-#define Control		(*((volatile Word *) SA1101_p2v (_Control)))
-#define CommandStatus	(*((volatile Word *) SA1101_p2v (_CommandStatus)))
-#define InterruptStatus	(*((volatile Word *) SA1101_p2v (_InterruptStatus)))
-#define InterruptEnable	(*((volatile Word *) SA1101_p2v (_InterruptEnable)))
-#define HCCA		(*((volatile Word *) SA1101_p2v (_HCCA)))
-#define PeriodCurrentED	(*((volatile Word *) SA1101_p2v (_PeriodCurrentED)))
-#define ControlHeadED	(*((volatile Word *) SA1101_p2v (_ControlHeadED)))
-#define BulkHeadED	(*((volatile Word *) SA1101_p2v (_BulkHeadED)))
-#define BulkCurrentED	(*((volatile Word *) SA1101_p2v (_BulkCurrentED)))
-#define DoneHead	(*((volatile Word *) SA1101_p2v (_DoneHead)))
-#define FmInterval	(*((volatile Word *) SA1101_p2v (_FmInterval)))
-#define FmRemaining	(*((volatile Word *) SA1101_p2v (_FmRemaining)))
-#define FmNumber	(*((volatile Word *) SA1101_p2v (_FmNumber)))
-#define PeriodicStart	(*((volatile Word *) SA1101_p2v (_PeriodicStart)))
-#define LSThreshold	(*((volatile Word *) SA1101_p2v (_LSThreshold)))
-#define RhDescriptorA	(*((volatile Word *) SA1101_p2v (_RhDescriptorA)))
-#define RhDescriptorB	(*((volatile Word *) SA1101_p2v (_RhDescriptorB)))
-#define RhStatus	(*((volatile Word *) SA1101_p2v (_RhStatus)))
-#define RhPortStatus	(*((volatile Word *) SA1101_p2v (_RhPortStatus)))
-#define USBStatus	(*((volatile Word *) SA1101_p2v (_USBStatus)))
-#define USBReset	(*((volatile Word *) SA1101_p2v (_USBReset)))
-#define USTAR		(*((volatile Word *) SA1101_p2v (_USTAR)))
-#define USWER		(*((volatile Word *) SA1101_p2v (_USWER)))
-#define USRFR		(*((volatile Word *) SA1101_p2v (_USRFR)))
-#define USNFR		(*((volatile Word *) SA1101_p2v (_USNFR)))
-#define USTCSR		(*((volatile Word *) SA1101_p2v (_USTCSR)))
-#define USSR		(*((volatile Word *) SA1101_p2v (_USSR)))
-
-
-#define USBStatus_IrqHciRmtWkp	     (1<<7)
-#define USBStatus_IrqHciBuffAcc	     (1<<8)
-#define USBStatus_nIrqHciM	     (1<<9)
-#define USBStatus_nHciMFClr	     (1<<10)
-
-#define USBReset_ForceIfReset	     0x01
-#define USBReset_ForceHcReset	     0x02
-#define USBReset_ClkGenReset	     0x04
-
-#define USTCR_RdBstCntrl	     Fld(3,0)
-#define USTCR_ByteEnable	     Fld(4,3)
-#define USTCR_WriteEn		     (1<<7)
-#define USTCR_FifoCir		     (1<<8)
-#define USTCR_TestXferSel	     (1<<9)
-#define USTCR_FifoCirAtEnd	     (1<<10)
-#define USTCR_nSimScaleDownClk	     (1<<11)
-
-#define USSR_nAppMDEmpty	     0x01
-#define USSR_nAppMDFirst	     0x02
-#define USSR_nAppMDLast		     0x04
-#define USSR_nAppMDFull		     0x08
-#define USSR_nAppMAFull		     0x10
-#define USSR_XferReq		     0x20
-#define USSR_XferEnd		     0x40
-
-#endif /* LANGUAGE == C */
-
-
-/*
- * Interrupt Controller
- *
- * Registers
- *    INTTEST0		Test register 0
- *    INTTEST1		Test register 1
- *    INTENABLE0	Interrupt Enable register 0
- *    INTENABLE1	Interrupt Enable register 1
- *    INTPOL0		Interrupt Polarity selection 0
- *    INTPOL1		Interrupt Polarity selection 1
- *    INTTSTSEL		Interrupt source selection
- *    INTSTATCLR0	Interrupt Status 0
- *    INTSTATCLR1	Interrupt Status 1
- *    INTSET0		Interrupt Set 0
- *    INTSET1		Interrupt Set 1
- */
-
-#define _INT( x )	_SA1101( ( x ) + __INTERRUPT_CONTROL)
-
-#define _INTTEST0	_INT( 0x1000 )
-#define _INTTEST1	_INT( 0x1400 )
-#define _INTENABLE0	_INT( 0x2000 )
-#define _INTENABLE1	_INT( 0x2400 )
-#define _INTPOL0	_INT( 0x3000 )
-#define _INTPOL1	_INT( 0x3400 )
-#define _INTTSTSEL     	_INT( 0x5000 )
-#define _INTSTATCLR0	_INT( 0x6000 )
-#define _INTSTATCLR1	_INT( 0x6400 )
-#define _INTSET0	_INT( 0x7000 )
-#define _INTSET1	_INT( 0x7400 )
-
-#if ( LANGUAGE == C )
-#define INTTEST0	(*((volatile Word *) SA1101_p2v (_INTTEST0)))
-#define INTTEST1	(*((volatile Word *) SA1101_p2v (_INTTEST1)))
-#define INTENABLE0	(*((volatile Word *) SA1101_p2v (_INTENABLE0)))
-#define INTENABLE1	(*((volatile Word *) SA1101_p2v (_INTENABLE1)))
-#define INTPOL0		(*((volatile Word *) SA1101_p2v (_INTPOL0)))
-#define INTPOL1		(*((volatile Word *) SA1101_p2v (_INTPOL1)))
-#define INTTSTSEL	(*((volatile Word *) SA1101_p2v (_INTTSTSEL)))
-#define INTSTATCLR0	(*((volatile Word *) SA1101_p2v (_INTSTATCLR0)))
-#define INTSTATCLR1	(*((volatile Word *) SA1101_p2v (_INTSTATCLR1)))
-#define INTSET0		(*((volatile Word *) SA1101_p2v (_INTSET0)))
-#define INTSET1		(*((volatile Word *) SA1101_p2v (_INTSET1)))
-
-#endif /* LANGUAGE == C */
-
-/*
- * PS/2 Trackpad and Mouse Interfaces
- *
- * Registers   (prefix kbd applies to trackpad interface, mse to mouse)
- *    KBDCR		Control Register
- *    KBDSTAT		Status Register
- *    KBDDATA		Transmit/Receive Data register
- *    KBDCLKDIV		Clock Division Register
- *    KBDPRECNT		Clock Precount Register
- *    KBDTEST1		Test register 1
- *    KBDTEST2		Test register 2
- *    KBDTEST3		Test register 3
- *    KBDTEST4		Test register 4
- *    MSECR	
- *    MSESTAT
- *    MSEDATA
- *    MSECLKDIV
- *    MSEPRECNT
- *    MSETEST1
- *    MSETEST2
- *    MSETEST3
- *    MSETEST4
- *     
- */
-
-#define _KBD( x )	_SA1101( ( x ) + __TRACK_INTERFACE )
-#define _MSE( x )	_SA1101( ( x ) + __MOUSE_INTERFACE )
-
-#define _KBDCR		_KBD( 0x0000 )
-#define _KBDSTAT	_KBD( 0x0400 )
-#define _KBDDATA	_KBD( 0x0800 )
-#define _KBDCLKDIV	_KBD( 0x0c00 )
-#define _KBDPRECNT	_KBD( 0x1000 )
-#define	_KBDTEST1	_KBD( 0x2000 )
-#define _KBDTEST2	_KBD( 0x2400 )
-#define _KBDTEST3	_KBD( 0x2800 )
-#define _KBDTEST4	_KBD( 0x2c00 )
-#define _MSECR		_MSE( 0x0000 )
-#define _MSESTAT	_MSE( 0x0400 )
-#define _MSEDATA	_MSE( 0x0800 )
-#define _MSECLKDIV	_MSE( 0x0c00 )
-#define _MSEPRECNT	_MSE( 0x1000 )
-#define	_MSETEST1	_MSE( 0x2000 )
-#define _MSETEST2	_MSE( 0x2400 )
-#define _MSETEST3	_MSE( 0x2800 )
-#define _MSETEST4	_MSE( 0x2c00 )
-
-#if ( LANGUAGE == C )
-
-#define KBDCR	    (*((volatile Word *) SA1101_p2v (_KBDCR)))
-#define KBDSTAT	    (*((volatile Word *) SA1101_p2v (_KBDSTAT)))
-#define KBDDATA	    (*((volatile Word *) SA1101_p2v (_KBDDATA)))
-#define KBDCLKDIV   (*((volatile Word *) SA1101_p2v (_KBDCLKDIV)))
-#define KBDPRECNT   (*((volatile Word *) SA1101_p2v (_KBDPRECNT)))
-#define KBDTEST1    (*((volatile Word *) SA1101_p2v (_KBDTEST1)))
-#define KBDTEST2    (*((volatile Word *) SA1101_p2v (_KBDTEST2)))
-#define KBDTEST3    (*((volatile Word *) SA1101_p2v (_KBDTEST3)))
-#define KBDTEST4    (*((volatile Word *) SA1101_p2v (_KBDTEST4)))
-#define MSECR	    (*((volatile Word *) SA1101_p2v (_MSECR)))
-#define MSESTAT	    (*((volatile Word *) SA1101_p2v (_MSESTAT)))
-#define MSEDATA	    (*((volatile Word *) SA1101_p2v (_MSEDATA)))
-#define MSECLKDIV   (*((volatile Word *) SA1101_p2v (_MSECLKDIV)))
-#define MSEPRECNT   (*((volatile Word *) SA1101_p2v (_MSEPRECNT)))
-#define MSETEST1    (*((volatile Word *) SA1101_p2v (_MSETEST1)))
-#define MSETEST2    (*((volatile Word *) SA1101_p2v (_MSETEST2)))
-#define MSETEST3    (*((volatile Word *) SA1101_p2v (_MSETEST3)))
-#define MSETEST4    (*((volatile Word *) SA1101_p2v (_MSETEST4)))
-
-
-#define KBDCR_ENA		 0x08
-#define KBDCR_FKD		 0x02
-#define KBDCR_FKC		 0x01
-
-#define KBDSTAT_TXE		 0x80
-#define KBDSTAT_TXB		 0x40
-#define KBDSTAT_RXF		 0x20
-#define KBDSTAT_RXB		 0x10
-#define KBDSTAT_ENA		 0x08
-#define KBDSTAT_RXP		 0x04
-#define KBDSTAT_KBD		 0x02
-#define KBDSTAT_KBC		 0x01
-
-#define KBDCLKDIV_DivVal	 Fld(4,0)
-
-#define MSECR_ENA		 0x08
-#define MSECR_FKD		 0x02
-#define MSECR_FKC		 0x01
-
-#define MSESTAT_TXE		 0x80
-#define MSESTAT_TXB		 0x40
-#define MSESTAT_RXF		 0x20
-#define MSESTAT_RXB		 0x10
-#define MSESTAT_ENA		 0x08
-#define MSESTAT_RXP		 0x04	
-#define MSESTAT_MSD		 0x02
-#define MSESTAT_MSC		 0x01
-
-#define MSECLKDIV_DivVal	 Fld(4,0)
-
-#define KBDTEST1_CD		 0x80
-#define KBDTEST1_RC1		 0x40
-#define KBDTEST1_MC		 0x20
-#define KBDTEST1_C		 Fld(2,3)
-#define KBDTEST1_T2		 0x40
-#define KBDTEST1_T1		 0x20
-#define KBDTEST1_T0		 0x10
-#define KBDTEST2_TICBnRES	 0x08
-#define KBDTEST2_RKC		 0x04
-#define KBDTEST2_RKD		 0x02
-#define KBDTEST2_SEL		 0x01
-#define KBDTEST3_ms_16		 0x80
-#define KBDTEST3_us_64		 0x40
-#define KBDTEST3_us_16		 0x20
-#define KBDTEST3_DIV8		 0x10
-#define KBDTEST3_DIn		 0x08
-#define KBDTEST3_CIn		 0x04
-#define KBDTEST3_KD		 0x02
-#define KBDTEST3_KC		 0x01
-#define KBDTEST4_BC12		 0x80
-#define KBDTEST4_BC11		 0x40
-#define KBDTEST4_TRES		 0x20
-#define KBDTEST4_CLKOE		 0x10
-#define KBDTEST4_CRES		 0x08
-#define KBDTEST4_RXB		 0x04
-#define KBDTEST4_TXB		 0x02
-#define KBDTEST4_SRX		 0x01
-
-#define MSETEST1_CD		 0x80
-#define MSETEST1_RC1		 0x40
-#define MSETEST1_MC		 0x20
-#define MSETEST1_C		 Fld(2,3)
-#define MSETEST1_T2		 0x40
-#define MSETEST1_T1		 0x20
-#define MSETEST1_T0		 0x10
-#define MSETEST2_TICBnRES	 0x08
-#define MSETEST2_RKC		 0x04
-#define MSETEST2_RKD		 0x02
-#define MSETEST2_SEL		 0x01
-#define MSETEST3_ms_16		 0x80
-#define MSETEST3_us_64		 0x40
-#define MSETEST3_us_16		 0x20
-#define MSETEST3_DIV8		 0x10
-#define MSETEST3_DIn		 0x08
-#define MSETEST3_CIn		 0x04
-#define MSETEST3_KD		 0x02
-#define MSETEST3_KC		 0x01
-#define MSETEST4_BC12		 0x80
-#define MSETEST4_BC11		 0x40
-#define MSETEST4_TRES		 0x20
-#define MSETEST4_CLKOE		 0x10
-#define MSETEST4_CRES		 0x08
-#define MSETEST4_RXB		 0x04
-#define MSETEST4_TXB		 0x02
-#define MSETEST4_SRX		 0x01
-
-#endif  /* LANGUAGE == C */
-
-
-/*
- * General-Purpose I/O Interface
- *
- * Registers
- *    PADWR	Port A Data Write Register
- *    PBDWR	Port B Data Write Register
- *    PADRR	Port A Data Read Register
- *    PBDRR	Port B Data Read Register
- *    PADDR	Port A Data Direction Register
- *    PBDDR	Port B Data Direction Register
- *    PASSR	Port A Sleep State Register
- *    PBSSR	Port B Sleep State Register
- *
- */
-
-#define _PIO( x )      _SA1101( ( x ) + __GPIO_INTERFACE )
-
-#define _PADWR	       _PIO( 0x0000 )
-#define _PBDWR	       _PIO( 0x0400 )
-#define _PADRR	       _PIO( 0x0000 )
-#define _PBDRR	       _PIO( 0x0400 )
-#define _PADDR	       _PIO( 0x0800 )
-#define _PBDDR	       _PIO( 0x0c00 )
-#define _PASSR	       _PIO( 0x1000 )
-#define _PBSSR	       _PIO( 0x1400 )
-
-
-#if ( LANGUAGE == C )
-
-
-#define PADWR	    (*((volatile Word *) SA1101_p2v (_PADWR)))
-#define PBDWR	    (*((volatile Word *) SA1101_p2v (_PBDWR)))
-#define PADRR	    (*((volatile Word *) SA1101_p2v (_PADRR)))
-#define PBDRR	    (*((volatile Word *) SA1101_p2v (_PBDRR)))
-#define PADDR	    (*((volatile Word *) SA1101_p2v (_PADDR)))
-#define PBDDR	    (*((volatile Word *) SA1101_p2v (_PBDDR)))
-#define PASSR	    (*((volatile Word *) SA1101_p2v (_PASSR)))
-#define PBSSR	    (*((volatile Word *) SA1101_p2v (_PBSSR)))
-
-#endif
-
-
-
-/*
- * Keypad Interface
- *
- * Registers
- *    PXDWR
- *    PXDRR
- *    PYDWR
- *    PYDRR
- *
- */
-
-#define _KEYPAD( x )	_SA1101( ( x ) + __KEYPAD_INTERFACE ) 
-
-#define _PXDWR	   _KEYPAD( 0x0000 )
-#define _PXDRR	   _KEYPAD( 0x0000 )
-#define _PYDWR	   _KEYPAD( 0x0400 )
-#define _PYDRR	   _KEYPAD( 0x0400 )
-
-#if ( LANGUAGE == C )
-
-
-#define PXDWR	    (*((volatile Word *) SA1101_p2v (_PXDWR)))
-#define PXDRR	    (*((volatile Word *) SA1101_p2v (_PXDRR)))
-#define PYDWR	    (*((volatile Word *) SA1101_p2v (_PYDWR)))
-#define PYDRR	    (*((volatile Word *) SA1101_p2v (_PYDRR)))
-
-#endif
-
-
-
-/*
- * PCMCIA Interface
- *
- * Registers
- *    PCSR	Status Register
- *    PCCR	Control Register
- *    PCSSR	Sleep State Register
- *
- */
-
-#define _CARD( x )	_SA1101( ( x ) + __PCMCIA_INTERFACE )
-
-#define _PCSR	   _CARD( 0x0000 )
-#define _PCCR	   _CARD( 0x0400 )
-#define _PCSSR	   _CARD( 0x0800 )
-
-#if ( LANGUAGE == C )
-#define PCSR    (*((volatile Word *) SA1101_p2v (_PCSR)))
-#define PCCR	(*((volatile Word *) SA1101_p2v (_PCCR)))
-#define PCSSR	(*((volatile Word *) SA1101_p2v (_PCSSR)))
-
-#define PCSR_S0_ready		0x0001
-#define PCSR_S1_ready		0x0002
-#define PCSR_S0_detected	0x0004
-#define PCSR_S1_detected	0x0008
-#define PCSR_S0_VS1		0x0010
-#define PCSR_S0_VS2		0x0020
-#define PCSR_S1_VS1		0x0040
-#define PCSR_S1_VS2		0x0080
-#define PCSR_S0_WP		0x0100
-#define PCSR_S1_WP		0x0200
-#define PCSR_S0_BVD1_nSTSCHG	0x0400
-#define PCSR_S0_BVD2_nSPKR	0x0800
-#define PCSR_S1_BVD1_nSTSCHG	0x1000
-#define PCSR_S1_BVD2_nSPKR	0x2000
-
-#define PCCR_S0_VPP0		0x0001
-#define PCCR_S0_VPP1		0x0002
-#define PCCR_S0_VCC0		0x0004
-#define PCCR_S0_VCC1		0x0008
-#define PCCR_S1_VPP0		0x0010
-#define PCCR_S1_VPP1		0x0020
-#define PCCR_S1_VCC0		0x0040
-#define PCCR_S1_VCC1		0x0080
-#define PCCR_S0_reset		0x0100
-#define PCCR_S1_reset		0x0200
-#define PCCR_S0_float		0x0400
-#define PCCR_S1_float		0x0800
-
-#define PCSSR_S0_VCC0		0x0001
-#define PCSSR_S0_VCC1		0x0002
-#define PCSSR_S0_VPP0		0x0004
-#define PCSSR_S0_VPP1		0x0008
-#define PCSSR_S0_control	0x0010
-#define PCSSR_S1_VCC0		0x0020
-#define PCSSR_S1_VCC1		0x0040
-#define PCSSR_S1_VPP0		0x0080
-#define PCSSR_S1_VPP1		0x0100
-#define PCSSR_S1_control	0x0200
-
-#endif
-
-#undef C
-#undef Assembly
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 99f5856..ee5d2bb 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -72,8 +72,4 @@ static inline unsigned long get_clock_tick_rate(void)
 
 #include "SA-1100.h"
 
-#ifdef CONFIG_SA1101
-#include "SA-1101.h"
-#endif
-
 #endif  /* _ASM_ARCH_HARDWARE_H */
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:56:46 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:56:46 +0200
Subject: [PATCH 09/33] Removing dead MAGICV
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <a770ecd46d47e48a60d98e7aeaeb4c2583609a4a.1277911346.git.siccegge@cs.fau.de>

MAGICV doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-at91/at572d940hf_devices.c |   73 ------------------------------
 1 files changed, 0 insertions(+), 73 deletions(-)

diff --git a/arch/arm/mach-at91/at572d940hf_devices.c b/arch/arm/mach-at91/at572d940hf_devices.c
index 0fc20a2..bff703e 100644
--- a/arch/arm/mach-at91/at572d940hf_devices.c
+++ b/arch/arm/mach-at91/at572d940hf_devices.c
@@ -878,80 +878,7 @@ void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
 #endif
 
-
-/* --------------------------------------------------------------------
- *  mAgic
- * -------------------------------------------------------------------- */
-
-#ifdef CONFIG_MAGICV
-static struct resource mAgic_resources[] = {
-	{
-		.start = AT91_MAGIC_PM_BASE,
-		.end   = AT91_MAGIC_PM_BASE + AT91_MAGIC_PM_SIZE - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = AT91_MAGIC_DM_I_BASE,
-		.end   = AT91_MAGIC_DM_I_BASE + AT91_MAGIC_DM_I_SIZE - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = AT91_MAGIC_DM_F_BASE,
-		.end   = AT91_MAGIC_DM_F_BASE + AT91_MAGIC_DM_F_SIZE - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = AT91_MAGIC_DM_DB_BASE,
-		.end   = AT91_MAGIC_DM_DB_BASE + AT91_MAGIC_DM_DB_SIZE - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = AT91_MAGIC_REGS_BASE,
-		.end   = AT91_MAGIC_REGS_BASE + AT91_MAGIC_REGS_SIZE - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start = AT91_MAGIC_EXTPAGE_BASE,
-		.end   = AT91_MAGIC_EXTPAGE_BASE + AT91_MAGIC_EXTPAGE_SIZE - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	{
-		.start  = AT572D940HF_ID_MSIRQ0,
-		.end    = AT572D940HF_ID_MSIRQ0,
-		.flags  = IORESOURCE_IRQ,
-	},
-	{
-		.start  = AT572D940HF_ID_MHALT,
-		.end    = AT572D940HF_ID_MHALT,
-		.flags  = IORESOURCE_IRQ,
-	},
-	{
-		.start  = AT572D940HF_ID_MEXC,
-		.end    = AT572D940HF_ID_MEXC,
-		.flags  = IORESOURCE_IRQ,
-	},
-	{
-		.start  = AT572D940HF_ID_MEDMA,
-		.end    = AT572D940HF_ID_MEDMA,
-		.flags  = IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device mAgic_device = {
-	.name           = "mAgic",
-	.id             = -1,
-	.num_resources  = ARRAY_SIZE(mAgic_resources),
-	.resource       = mAgic_resources,
-};
-
-void __init at91_add_device_mAgic(void)
-{
-	platform_device_register(&mAgic_device);
-}
-#else
 void __init at91_add_device_mAgic(void) {}
-#endif
-
 
 /* -------------------------------------------------------------------- */
 
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:57:06 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:57:06 +0200
Subject: [PATCH 10/33] Removing dead VIDEO_AT91_ISI
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <ee303ddacab78fe3a1032485d880f313244c0c70.1277911346.git.siccegge@cs.fau.de>

VIDEO_AT91_ISI doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-at91/at91sam9263_devices.c |   49 ------------------------------
 1 files changed, 0 insertions(+), 49 deletions(-)

diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index fb5c23a..511d348 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -862,56 +862,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
 #endif
 
-
-/* --------------------------------------------------------------------
- *  Image Sensor Interface
- * -------------------------------------------------------------------- */
-
-#if defined(CONFIG_VIDEO_AT91_ISI) || defined(CONFIG_VIDEO_AT91_ISI_MODULE)
-
-struct resource isi_resources[] = {
-	[0] = {
-		.start	= AT91SAM9263_BASE_ISI,
-		.end	= AT91SAM9263_BASE_ISI + SZ_16K - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= AT91SAM9263_ID_ISI,
-		.end	= AT91SAM9263_ID_ISI,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device at91sam9263_isi_device = {
-	.name		= "at91_isi",
-	.id		= -1,
-	.resource	= isi_resources,
-	.num_resources	= ARRAY_SIZE(isi_resources),
-};
-
-void __init at91_add_device_isi(void)
-{
-	at91_set_A_periph(AT91_PIN_PE0, 0);	/* ISI_D0 */
-	at91_set_A_periph(AT91_PIN_PE1, 0);	/* ISI_D1 */
-	at91_set_A_periph(AT91_PIN_PE2, 0);	/* ISI_D2 */
-	at91_set_A_periph(AT91_PIN_PE3, 0);	/* ISI_D3 */
-	at91_set_A_periph(AT91_PIN_PE4, 0);	/* ISI_D4 */
-	at91_set_A_periph(AT91_PIN_PE5, 0);	/* ISI_D5 */
-	at91_set_A_periph(AT91_PIN_PE6, 0);	/* ISI_D6 */
-	at91_set_A_periph(AT91_PIN_PE7, 0);	/* ISI_D7 */
-	at91_set_A_periph(AT91_PIN_PE8, 0);	/* ISI_PCK */
-	at91_set_A_periph(AT91_PIN_PE9, 0);	/* ISI_HSYNC */
-	at91_set_A_periph(AT91_PIN_PE10, 0);	/* ISI_VSYNC */
-	at91_set_B_periph(AT91_PIN_PE11, 0);	/* ISI_MCK (PCK3) */
-	at91_set_B_periph(AT91_PIN_PE12, 0);	/* ISI_PD8 */
-	at91_set_B_periph(AT91_PIN_PE13, 0);	/* ISI_PD9 */
-	at91_set_B_periph(AT91_PIN_PE14, 0);	/* ISI_PD10 */
-	at91_set_B_periph(AT91_PIN_PE15, 0);	/* ISI_PD11 */
-}
-#else
 void __init at91_add_device_isi(void) {}
-#endif
-
 
 /* --------------------------------------------------------------------
  *  Timer/Counter block
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:57:26 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:57:26 +0200
Subject: [PATCH 11/33] Removing dead OMAP_DSP
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <fc9feac62dc4eb90e8c3b7039729fa102ad0ac98.1277911346.git.siccegge@cs.fau.de>

OMAP_DSP doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-omap1/board-nokia770.c         |  132 --------------------------
 arch/arm/mach-omap1/devices.c                |   37 -------
 arch/arm/mach-omap1/mcbsp.c                  |    3 -
 arch/arm/plat-omap/devices.c                 |   62 ------------
 arch/arm/plat-omap/include/plat/dsp_common.h |   40 --------
 5 files changed, 0 insertions(+), 274 deletions(-)
 delete mode 100644 arch/arm/plat-omap/include/plat/dsp_common.h

diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 71e1a3f..825b4c8 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -242,138 +242,6 @@ static inline void nokia770_mmc_init(void)
 }
 #endif
 
-#if	defined(CONFIG_OMAP_DSP)
-/*
- * audio power control
- */
-#define	HEADPHONE_GPIO		14
-#define	AMPLIFIER_CTRL_GPIO	58
-
-static struct clk *dspxor_ck;
-static DEFINE_MUTEX(audio_pwr_lock);
-/*
- * audio_pwr_state
- * +--+-------------------------+---------------------------------------+
- * |-1|down			|power-up request -> 0			|
- * +--+-------------------------+---------------------------------------+
- * | 0|up			|power-down(1) request -> 1		|
- * |  |				|power-down(2) request -> (ignore)	|
- * +--+-------------------------+---------------------------------------+
- * | 1|up,			|power-up request -> 0			|
- * |  |received down(1) request	|power-down(2) request -> -1		|
- * +--+-------------------------+---------------------------------------+
- */
-static int audio_pwr_state = -1;
-
-static inline void aic23_power_up(void)
-{
-}
-static inline void aic23_power_down(void)
-{
-}
-
-/*
- * audio_pwr_up / down should be called under audio_pwr_lock
- */
-static void nokia770_audio_pwr_up(void)
-{
-	clk_enable(dspxor_ck);
-
-	/* Turn on codec */
-	aic23_power_up();
-
-	if (gpio_get_value(HEADPHONE_GPIO))
-		/* HP not connected, turn on amplifier */
-		gpio_set_value(AMPLIFIER_CTRL_GPIO, 1);
-	else
-		/* HP connected, do not turn on amplifier */
-		printk("HP connected\n");
-}
-
-static void codec_delayed_power_down(struct work_struct *work)
-{
-	mutex_lock(&audio_pwr_lock);
-	if (audio_pwr_state == -1)
-		aic23_power_down();
-	clk_disable(dspxor_ck);
-	mutex_unlock(&audio_pwr_lock);
-}
-
-static DECLARE_DELAYED_WORK(codec_power_down_work, codec_delayed_power_down);
-
-static void nokia770_audio_pwr_down(void)
-{
-	/* Turn off amplifier */
-	gpio_set_value(AMPLIFIER_CTRL_GPIO, 0);
-
-	/* Turn off codec: schedule delayed work */
-	schedule_delayed_work(&codec_power_down_work, HZ / 20);	/* 50ms */
-}
-
-static int
-nokia770_audio_pwr_up_request(struct dsp_kfunc_device *kdev, int stage)
-{
-	mutex_lock(&audio_pwr_lock);
-	if (audio_pwr_state == -1)
-		nokia770_audio_pwr_up();
-	/* force audio_pwr_state = 0, even if it was 1. */
-	audio_pwr_state = 0;
-	mutex_unlock(&audio_pwr_lock);
-	return 0;
-}
-
-static int
-nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage)
-{
-	mutex_lock(&audio_pwr_lock);
-	switch (stage) {
-	case 1:
-		if (audio_pwr_state == 0)
-			audio_pwr_state = 1;
-		break;
-	case 2:
-		if (audio_pwr_state == 1) {
-			nokia770_audio_pwr_down();
-			audio_pwr_state = -1;
-		}
-		break;
-	}
-	mutex_unlock(&audio_pwr_lock);
-	return 0;
-}
-
-static struct dsp_kfunc_device nokia770_audio_device = {
-	.name	 = "audio",
-	.type	 = DSP_KFUNC_DEV_TYPE_AUDIO,
-	.enable  = nokia770_audio_pwr_up_request,
-	.disable = nokia770_audio_pwr_down_request,
-};
-
-static __init int omap_dsp_init(void)
-{
-	int ret;
-
-	dspxor_ck = clk_get(0, "dspxor_ck");
-	if (IS_ERR(dspxor_ck)) {
-		printk(KERN_ERR "couldn't acquire dspxor_ck\n");
-		return PTR_ERR(dspxor_ck);
-	}
-
-	ret = dsp_kfunc_device_register(&nokia770_audio_device);
-	if (ret) {
-		printk(KERN_ERR
-		       "KFUNC device registration faild: %s\n",
-		       nokia770_audio_device.name);
-		goto out;
-	}
-	return 0;
- out:
-	return ret;
-}
-#else
-#define omap_dsp_init()		do {} while (0)
-#endif	/* CONFIG_OMAP_DSP */
-
 static void __init omap_nokia770_init(void)
 {
 	platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 379100c..c00d602 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -63,44 +63,7 @@ static void omap_init_rtc(void)
 static inline void omap_init_rtc(void) {}
 #endif
 
-#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
-
-#if defined(CONFIG_ARCH_OMAP15XX)
-#  define OMAP1_MBOX_SIZE	0x23
-#  define INT_DSP_MAILBOX1	INT_1510_DSP_MAILBOX1
-#elif defined(CONFIG_ARCH_OMAP16XX)
-#  define OMAP1_MBOX_SIZE	0x2f
-#  define INT_DSP_MAILBOX1	INT_1610_DSP_MAILBOX1
-#endif
-
-#define OMAP1_MBOX_BASE		OMAP16XX_MAILBOX_BASE
-
-static struct resource mbox_resources[] = {
-	{
-		.start		= OMAP1_MBOX_BASE,
-		.end		= OMAP1_MBOX_BASE + OMAP1_MBOX_SIZE,
-		.flags		= IORESOURCE_MEM,
-	},
-	{
-		.start		= INT_DSP_MAILBOX1,
-		.flags		= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device mbox_device = {
-	.name		= "omap1-mailbox",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(mbox_resources),
-	.resource	= mbox_resources,
-};
-
-static inline void omap_init_mbox(void)
-{
-	platform_device_register(&mbox_device);
-}
-#else
 static inline void omap_init_mbox(void) { }
-#endif
 
 /*-------------------------------------------------------------------------*/
 
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index e9bdff1..b3a796a 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -23,7 +23,6 @@
 #include <plat/mux.h>
 #include <plat/cpu.h>
 #include <plat/mcbsp.h>
-#include <plat/dsp_common.h>
 
 #define DPS_RSTCT2_PER_EN	(1 << 0)
 #define DSP_RSTCT2_WD_PER_EN	(1 << 1)
@@ -46,7 +45,6 @@ static void omap1_mcbsp_request(unsigned int id)
 				clk_enable(api_clk);
 				clk_enable(dsp_clk);
 
-				omap_dsp_request_mem();
 				/*
 				 * DSP external peripheral reset
 				 * FIXME: This should be moved to dsp code
@@ -62,7 +60,6 @@ static void omap1_mcbsp_free(unsigned int id)
 {
 	if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
 		if (--dsp_use == 0) {
-			omap_dsp_release_mem();
 			if (!IS_ERR(api_clk)) {
 				clk_disable(api_clk);
 				clk_put(api_clk);
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 95677d1..a3997ec 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -31,67 +31,6 @@
 #include <plat/dsp_common.h>
 #include <plat/omap44xx.h>
 
-#if	defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
-
-static struct dsp_platform_data dsp_pdata = {
-	.kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
-};
-
-static struct resource omap_dsp_resources[] = {
-	{
-		.name	= "dsp_mmu",
-		.start	= -1,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device omap_dsp_device = {
-	.name		= "dsp",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(omap_dsp_resources),
-	.resource	= omap_dsp_resources,
-	.dev = {
-		.platform_data = &dsp_pdata,
-	},
-};
-
-static inline void omap_init_dsp(void)
-{
-	struct resource *res;
-	int irq;
-
-	if (cpu_is_omap15xx())
-		irq = INT_1510_DSP_MMU;
-	else if (cpu_is_omap16xx())
-		irq = INT_1610_DSP_MMU;
-	else if (cpu_is_omap24xx())
-		irq = INT_24XX_DSP_MMU;
-
-	res = platform_get_resource_byname(&omap_dsp_device,
-					   IORESOURCE_IRQ, "dsp_mmu");
-	res->start = irq;
-
-	platform_device_register(&omap_dsp_device);
-}
-
-int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev)
-{
-	static DEFINE_MUTEX(dsp_pdata_lock);
-
-	spin_lock_init(&kdev->lock);
-
-	mutex_lock(&dsp_pdata_lock);
-	list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
-	mutex_unlock(&dsp_pdata_lock);
-
-	return 0;
-}
-EXPORT_SYMBOL(dsp_kfunc_device_register);
-
-#else
-static inline void omap_init_dsp(void) { }
-#endif	/* CONFIG_OMAP_DSP */
-
 /*-------------------------------------------------------------------------*/
 #if	defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
 
@@ -419,7 +358,6 @@ static int __init omap_init_devices(void)
 	/* please keep these calls, and their implementations above,
 	 * in alphabetical order so they're easier to sort through.
 	 */
-	omap_init_dsp();
 	omap_init_kp();
 	omap_init_rng();
 	omap_init_mcpdm();
diff --git a/arch/arm/plat-omap/include/plat/dsp_common.h b/arch/arm/plat-omap/include/plat/dsp_common.h
deleted file mode 100644
index da97736..0000000
--- a/arch/arm/plat-omap/include/plat/dsp_common.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
- *
- * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
- *
- * Contact: Toshihiro Kobayashi <toshihiro.kobayashi at nokia.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#ifndef ASM_ARCH_DSP_COMMON_H
-#define ASM_ARCH_DSP_COMMON_H
-
-#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
-extern void omap_dsp_request_mpui(void);
-extern void omap_dsp_release_mpui(void);
-extern int omap_dsp_request_mem(void);
-extern int omap_dsp_release_mem(void);
-#else
-static inline int omap_dsp_request_mem(void)
-{
-	return 0;
-}
-#define omap_dsp_release_mem()	do {} while (0)
-#endif
-
-#endif /* ASM_ARCH_DSP_COMMON_H */
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:57:45 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:57:45 +0200
Subject: [PATCH 12/33] Removing dead OMAP_STI
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <35d3c6a25b5cc05a5eee3037075ccede85b1917f.1277911346.git.siccegge@cs.fau.de>

OMAP_STI doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-omap1/devices.c |   35 -------------------------
 arch/arm/mach-omap2/devices.c |   57 -----------------------------------------
 2 files changed, 0 insertions(+), 92 deletions(-)

diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index c00d602..aa07256 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -193,42 +193,7 @@ static inline void omap_init_spi100k(void)
 
 /*-------------------------------------------------------------------------*/
 
-#if defined(CONFIG_OMAP_STI)
-
-#define OMAP1_STI_BASE		0xfffea000
-#define OMAP1_STI_CHANNEL_BASE	(OMAP1_STI_BASE + 0x400)
-
-static struct resource sti_resources[] = {
-	{
-		.start		= OMAP1_STI_BASE,
-		.end		= OMAP1_STI_BASE + SZ_1K - 1,
-		.flags		= IORESOURCE_MEM,
-	},
-	{
-		.start		= OMAP1_STI_CHANNEL_BASE,
-		.end		= OMAP1_STI_CHANNEL_BASE + SZ_1K - 1,
-		.flags		= IORESOURCE_MEM,
-	},
-	{
-		.start		= INT_1610_STI,
-		.flags		= IORESOURCE_IRQ,
-	}
-};
-
-static struct platform_device sti_device = {
-	.name		= "sti",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(sti_resources),
-	.resource	= sti_resources,
-};
-
-static inline void omap_init_sti(void)
-{
-	platform_device_register(&sti_device);
-}
-#else
 static inline void omap_init_sti(void) {}
-#endif
 
 /*-------------------------------------------------------------------------*/
 
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 03e6c9e..b9c1f98 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -230,64 +230,7 @@ static inline void omap_init_mbox(void)
 static inline void omap_init_mbox(void) { }
 #endif /* CONFIG_OMAP_MBOX_FWK */
 
-#if defined(CONFIG_OMAP_STI)
-
-#if defined(CONFIG_ARCH_OMAP2)
-
-#define OMAP2_STI_BASE		0x48068000
-#define OMAP2_STI_CHANNEL_BASE	0x54000000
-#define OMAP2_STI_IRQ		4
-
-static struct resource sti_resources[] = {
-	{
-		.start		= OMAP2_STI_BASE,
-		.end		= OMAP2_STI_BASE + 0x7ff,
-		.flags		= IORESOURCE_MEM,
-	},
-	{
-		.start		= OMAP2_STI_CHANNEL_BASE,
-		.end		= OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
-		.flags		= IORESOURCE_MEM,
-	},
-	{
-		.start		= OMAP2_STI_IRQ,
-		.flags		= IORESOURCE_IRQ,
-	}
-};
-#elif defined(CONFIG_ARCH_OMAP3)
-
-#define OMAP3_SDTI_BASE		0x54500000
-#define OMAP3_SDTI_CHANNEL_BASE	0x54600000
-
-static struct resource sti_resources[] = {
-	{
-		.start		= OMAP3_SDTI_BASE,
-		.end		= OMAP3_SDTI_BASE + 0xFFF,
-		.flags		= IORESOURCE_MEM,
-	},
-	{
-		.start		= OMAP3_SDTI_CHANNEL_BASE,
-		.end		= OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
-		.flags		= IORESOURCE_MEM,
-	}
-};
-
-#endif
-
-static struct platform_device sti_device = {
-	.name		= "sti",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(sti_resources),
-	.resource	= sti_resources,
-};
-
-static inline void omap_init_sti(void)
-{
-	platform_device_register(&sti_device);
-}
-#else
 static inline void omap_init_sti(void) {}
-#endif
 
 #if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
 
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:58:07 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:58:07 +0200
Subject: [PATCH 13/33] Replacing LEDS_OMAP_DEBUG with OMAP_DEBUG_LEDS
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <b1363abf63cf2e35450acae82765ba679f1979bc.1277911346.git.siccegge@cs.fau.de>

LEDS_OMAP_DEBUG doesn't exist in Kconfig, therefore replacing all
references for it with OMAP_DEBUG_LEDS from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/plat-omap/Kconfig      |    2 +-
 arch/arm/plat-omap/debug-leds.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 78b49a6..a5337c8 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -51,7 +51,7 @@ config OMAP_DEBUG_DEVICES
 config OMAP_DEBUG_LEDS
 	bool
 	depends on OMAP_DEBUG_DEVICES
-	default y if LEDS || LEDS_OMAP_DEBUG
+	default y if LEDS
 
 config OMAP_RESET_CLOCKS
 	bool "Reset unused clocks during boot"
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index 53fcef7..fc05b10 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -39,7 +39,7 @@ static struct h2p2_dbg_fpga __iomem	*fpga;
 static u16				led_state, hw_led_state;
 
 
-#ifdef	CONFIG_LEDS_OMAP_DEBUG
+#ifdef	CONFIG_OMAP_DEBUG_LEDS
 #define new_led_api()	1
 #else
 #define new_led_api()	0
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:58:25 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:58:25 +0200
Subject: [PATCH 14/33] Removing dead SDMA_IRAM
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <3dc9983ca244c19f18da8951444e1cc9fae0226f.1277911346.git.siccegge@cs.fau.de>

SDMA_IRAM doesn't exist in Kconfig, therefore removing all references
for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/plat-mxc/include/mach/mx51.h |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 5aad344..fd5ec07 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -149,11 +149,7 @@
 #define MX51_MXC_DMA_CHANNEL_SSI1_RX	MXC_DMA_DYNAMIC_CHANNEL
 #define MX51_MXC_DMA_CHANNEL_SSI1_TX	MXC_DMA_DYNAMIC_CHANNEL
 #define MX51_MXC_DMA_CHANNEL_SSI2_RX	MXC_DMA_DYNAMIC_CHANNEL
-#ifdef CONFIG_SDMA_IRAM
-#define MX51_MXC_DMA_CHANNEL_SSI2_TX	(MX51_MXC_DMA_CHANNEL_IRAM + 1)
-#else				/*CONFIG_SDMA_IRAM */
 #define MX51_MXC_DMA_CHANNEL_SSI2_TX	MXC_DMA_DYNAMIC_CHANNEL
-#endif				/*CONFIG_SDMA_IRAM */
 #define MX51_MXC_DMA_CHANNEL_CSPI1_RX	MXC_DMA_DYNAMIC_CHANNEL
 #define MX51_MXC_DMA_CHANNEL_CSPI1_TX	MXC_DMA_DYNAMIC_CHANNEL
 #define MX51_MXC_DMA_CHANNEL_CSPI2_RX	MXC_DMA_DYNAMIC_CHANNEL
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:58:48 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:58:48 +0200
Subject: [PATCH 15/33] Removing dead PROCESSOR_NS9750
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <73d2b3929175d36d8bfdedf2d49150d2ed911b2a.1277911346.git.siccegge@cs.fau.de>

PROCESSOR_NS9750 doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-ns9xxx/gpio.c |    8 --------
 1 files changed, 0 insertions(+), 8 deletions(-)

diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c
index 5503ca0..58f4f50 100644
--- a/arch/arm/mach-ns9xxx/gpio.c
+++ b/arch/arm/mach-ns9xxx/gpio.c
@@ -25,9 +25,6 @@
 
 #if defined(CONFIG_PROCESSOR_NS9360)
 #define GPIO_MAX 72
-#elif defined(CONFIG_PROCESSOR_NS9750)
-#define GPIO_MAX 49
-#endif
 
 /* protects BBU_GCONFx and BBU_GCTRLx */
 static spinlock_t gpio_lock = __SPIN_LOCK_UNLOCKED(gpio_lock);
@@ -42,11 +39,6 @@ static inline int ns9xxx_valid_gpio(unsigned gpio)
 		return gpio <= 72;
 	else
 #endif
-#if defined(CONFIG_PROCESSOR_NS9750)
-	if (processor_is_ns9750())
-		return gpio <= 49;
-	else
-#endif
 	{
 		BUG();
 		return 0;
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:59:06 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:59:06 +0200
Subject: [PATCH 16/33] Removing dead APM
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <51c095a4c49baacbfdd6ed332d1375ab64209753.1277911346.git.siccegge@cs.fau.de>

APM doesn't exist in Kconfig, therefore removing all references for it
from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-omap1/board-palmte.c |   84 ------------------------------------
 1 files changed, 0 insertions(+), 84 deletions(-)

diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 569b4c9..23bb0c9 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -213,90 +213,6 @@ static struct omap_lcd_config palmte_lcd_config __initdata = {
 	.ctrl_name	= "internal",
 };
 
-#ifdef CONFIG_APM
-/*
- * Values measured in 10 minute intervals averaged over 10 samples.
- * May differ slightly from device to device but should be accurate
- * enough to give basic idea of battery life left and trigger
- * potential alerts.
- */
-static const int palmte_battery_sample[] = {
-	2194, 2157, 2138, 2120,
-	2104, 2089, 2075, 2061,
-	2048, 2038, 2026, 2016,
-	2008, 1998, 1989, 1980,
-	1970, 1958, 1945, 1928,
-	1910, 1888, 1860, 1827,
-	1791, 1751, 1709, 1656,
-};
-
-#define INTERVAL		10
-#define BATTERY_HIGH_TRESHOLD	66
-#define BATTERY_LOW_TRESHOLD	33
-
-static void palmte_get_power_status(struct apm_power_info *info, int *battery)
-{
-	int charging, batt, hi, lo, mid;
-
-	charging = !gpio_get_value(PALMTE_DC_GPIO);
-	batt = battery[0];
-	if (charging)
-		batt -= 60;
-
-	hi = ARRAY_SIZE(palmte_battery_sample);
-	lo = 0;
-
-	info->battery_flag = 0;
-	info->units = APM_UNITS_MINS;
-
-	if (batt > palmte_battery_sample[lo]) {
-		info->battery_life = 100;
-		info->time = INTERVAL * ARRAY_SIZE(palmte_battery_sample);
-	} else if (batt <= palmte_battery_sample[hi - 1]) {
-		info->battery_life = 0;
-		info->time = 0;
-	} else {
-		while (hi > lo + 1) {
-			mid = (hi + lo) >> 1;
-			if (batt <= palmte_battery_sample[mid])
-				lo = mid;
-			else
-				hi = mid;
-		}
-
-		mid = palmte_battery_sample[lo] - palmte_battery_sample[hi];
-		hi = palmte_battery_sample[lo] - batt;
-		info->battery_life = 100 - (100 * lo + 100 * hi / mid) /
-			ARRAY_SIZE(palmte_battery_sample);
-		info->time = INTERVAL * (ARRAY_SIZE(palmte_battery_sample) -
-				lo) - INTERVAL * hi / mid;
-	}
-
-	if (charging) {
-		info->ac_line_status = APM_AC_ONLINE;
-		info->battery_status = APM_BATTERY_STATUS_CHARGING;
-		info->battery_flag |= APM_BATTERY_FLAG_CHARGING;
-	} else {
-		info->ac_line_status = APM_AC_OFFLINE;
-		if (info->battery_life > BATTERY_HIGH_TRESHOLD)
-			info->battery_status = APM_BATTERY_STATUS_HIGH;
-		else if (info->battery_life > BATTERY_LOW_TRESHOLD)
-			info->battery_status = APM_BATTERY_STATUS_LOW;
-		else
-			info->battery_status = APM_BATTERY_STATUS_CRITICAL;
-	}
-
-	if (info->battery_life > BATTERY_HIGH_TRESHOLD)
-		info->battery_flag |= APM_BATTERY_FLAG_HIGH;
-	else if (info->battery_life > BATTERY_LOW_TRESHOLD)
-		info->battery_flag |= APM_BATTERY_FLAG_LOW;
-	else
-		info->battery_flag |= APM_BATTERY_FLAG_CRITICAL;
-}
-#else
-#define palmte_get_power_status	NULL
-#endif
-
 static struct omap_board_config_kernel palmte_config[] __initdata = {
 	{ OMAP_TAG_LCD,		&palmte_lcd_config },
 };
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:59:25 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:59:25 +0200
Subject: [PATCH 17/33] Removing dead SX1_OLD_FLASH
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <5b21086199b139a61888c16e92d3efe6b205dae2.1277911346.git.siccegge@cs.fau.de>

SX1_OLD_FLASH doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-omap1/board-sx1.c |   26 --------------------------
 1 files changed, 0 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 2fb1e5f..1de809d 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -295,31 +295,6 @@ static struct physmap_flash_data sx1_flash_data = {
 	.nr_parts	= ARRAY_SIZE(sx1_partitions),
 };
 
-#ifdef CONFIG_SX1_OLD_FLASH
-/* MTD Intel StrataFlash - old flashes */
-static struct resource sx1_old_flash_resource[] = {
-	[0] = {
-		.start	= OMAP_CS0_PHYS,	/* Physical */
-		.end	= OMAP_CS0_PHYS + SZ_16M - 1,,
-		.flags	= IORESOURCE_MEM,
-	},
-	[1] = {
-		.start	= OMAP_CS1_PHYS,
-		.end	= OMAP_CS1_PHYS + SZ_8M - 1,
-		.flags	= IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device sx1_flash_device = {
-	.name		= "physmap-flash",
-	.id		= 0,
-	.dev		= {
-		.platform_data	= &sx1_flash_data,
-	},
-	.num_resources	= 2,
-	.resource	= &sx1_old_flash_resource,
-};
-#else
 /* MTD Intel 4000 flash - new flashes */
 static struct resource sx1_new_flash_resource = {
 	.start		= OMAP_CS0_PHYS,
@@ -336,7 +311,6 @@ static struct platform_device sx1_flash_device = {
 	.num_resources	= 1,
 	.resource	= &sx1_new_flash_resource,
 };
-#endif
 
 /*----------- USB -------------------------*/
 
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 11:59:45 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:59:45 +0200
Subject: [PATCH 18/33] Removing dead OMAP_ARM_96MHZ
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <8304abb0dbda307c488b6fe2b3cc8df3c9909eb6.1277911346.git.siccegge@cs.fau.de>

OMAP_ARM_96MHZ doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-omap1/opp_data.c |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mach-omap1/opp_data.c b/arch/arm/mach-omap1/opp_data.c
index 75a5465..060df86 100644
--- a/arch/arm/mach-omap1/opp_data.c
+++ b/arch/arm/mach-omap1/opp_data.c
@@ -45,9 +45,6 @@ struct mpu_rate omap1_rate_table[] = {
 #if defined(CONFIG_OMAP_ARM_120MHZ)
 	{ 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
 #endif
-#if defined(CONFIG_OMAP_ARM_96MHZ)
-	{  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
-#endif
 #if defined(CONFIG_OMAP_ARM_60MHZ)
 	{  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
 #endif
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:00:05 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:00:05 +0200
Subject: [PATCH 19/33] Removing dead MACH_OMAP_H4_OTG
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <9d4f00439829dfb8dae18a532e6d21094f2043e5.1277911346.git.siccegge@cs.fau.de>

MACH_OMAP_H4_OTG doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-omap2/board-h4.c |   17 -----------------
 1 files changed, 0 insertions(+), 17 deletions(-)

diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index ce4292b..85d7fb8 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -277,22 +277,6 @@ static struct omap_usb_config h4_usb_config __initdata = {
 	.pins[1]	= 4,
 #endif
 
-#ifdef	CONFIG_MACH_OMAP_H4_OTG
-	/* S1.10 ON -- USB OTG port
-	 * usb0 switched to Mini-AB port and isp1301 transceiver;
-	 * S2.POS3 = OFF, S2.POS4 = ON ... to allow battery charging
-	 */
-	.otg		= 1,
-	.pins[0]	= 4,
-#ifdef	CONFIG_USB_GADGET_OMAP
-	/* use OTG cable, or standard A-to-MiniB */
-	.hmc_mode	= 0x14,	/* 0:dev/otg 1:host 2:disable */
-#elif	defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-	/* use OTG cable, or NONSTANDARD (B-to-MiniB) */
-	.hmc_mode	= 0x11,	/* 0:host 1:host 2:disable */
-#endif	/* XX */
-
-#else
 	/* S1.10 OFF -- usb "download port"
 	 * usb0 switched to Mini-B port and isp1105 transceiver;
 	 * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging
@@ -301,7 +285,6 @@ static struct omap_usb_config h4_usb_config __initdata = {
 	.pins[0]	= 3,
 /*	.hmc_mode	= 0x14,*/	/* 0:dev 1:host 2:disable */
 	.hmc_mode	= 0x00,		/* 0:dev|otg 1:disable 2:disable */
-#endif
 };
 
 static struct omap_board_config_kernel h4_config[] = {
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:00:23 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:00:23 +0200
Subject: [PATCH 20/33] Removing dead MACH_OMAP2_H4_USB1
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <24b01f2edebd09e37306c35f14401819d8219549.1277911346.git.siccegge@cs.fau.de>

MACH_OMAP2_H4_USB1 doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-omap2/board-h4.c |    5 -----
 1 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 85d7fb8..f0c2701 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -272,11 +272,6 @@ static struct omap_lcd_config h4_lcd_config __initdata = {
 };
 
 static struct omap_usb_config h4_usb_config __initdata = {
-#ifdef	CONFIG_MACH_OMAP2_H4_USB1
-	/* NOTE:  usb1 could also be used with 3 wire signaling */
-	.pins[1]	= 4,
-#endif
-
 	/* S1.10 OFF -- usb "download port"
 	 * usb0 switched to Mini-B port and isp1105 transceiver;
 	 * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:00:41 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:00:41 +0200
Subject: [PATCH 21/33] Removing dead OMAP2_VENC_OUT_TYPE_SVIDEO,
	OMAP2_VENC_OUT_TYPE_COMPOSITE
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <2709d1406900af2436f6f8af00555507baf8dac9.1277911346.git.siccegge@cs.fau.de>

OMAP2_VENC_OUT_TYPE_SVIDEO, OMAP2_VENC_OUT_TYPE_COMPOSITE doesn't
exist in Kconfig, therefore removing all references for it from the
source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-omap2/board-omap3stalker.c |    5 -----
 1 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index f848ba8..b38afd5 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -181,11 +181,6 @@ static struct omap_dss_device omap3_stalker_tv_device = {
 	.name			= "tv",
 	.driver_name		= "venc",
 	.type			= OMAP_DISPLAY_TYPE_VENC,
-#if defined(CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO)
-	.phy.venc.type		= OMAP_DSS_VENC_TYPE_SVIDEO,
-#elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE)
-	.u.venc.type		= OMAP_DSS_VENC_TYPE_COMPOSITE,
-#endif
 	.platform_enable	= omap3_stalker_enable_tv,
 	.platform_disable	= omap3_stalker_disable_tv,
 };
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:01:01 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:01:01 +0200
Subject: [PATCH 22/33] Removing dead MPU_{BRIDGE,TESLA}_IOMMU
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <fcfa44a43c21c70f89ced96b96d7c1489d28cc51.1277911346.git.siccegge@cs.fau.de>

MPU_{BRIDGE,TESLA}_IOMMU doesn't exist in Kconfig, therefore removing
all references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-omap2/omap-iommu.c |   22 ----------------------
 1 files changed, 0 insertions(+), 22 deletions(-)

diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index eb9bee7..3aa3fe9 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -35,17 +35,6 @@ static struct iommu_device omap3_devices[] = {
 			.clk_name = "cam_ick",
 		},
 	},
-#if defined(CONFIG_MPU_BRIDGE_IOMMU)
-	{
-		.base = 0x5d000000,
-		.irq = 28,
-		.pdata = {
-			.name = "iva2",
-			.nr_tlb_entries = 32,
-			.clk_name = "iva2_ck",
-		},
-	},
-#endif
 };
 #define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices)
 static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES];
@@ -66,17 +55,6 @@ static struct iommu_device omap4_devices[] = {
 			.clk_name = "ducati_ick",
 		},
 	},
-#if defined(CONFIG_MPU_TESLA_IOMMU)
-	{
-		.base = OMAP4_MMU2_BASE,
-		.irq = INT_44XX_DSP_MMU,
-		.pdata = {
-			.name = "tesla",
-			.nr_tlb_entries = 32,
-			.clk_name = "tesla_ick",
-		},
-	},
-#endif
 };
 #define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices)
 static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES];
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:01:20 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:01:20 +0200
Subject: [PATCH 23/33] Removing dead BACKLIGHT_CORGI
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <daefd019d1a302665a0cc5817ed50cfb4b7b1c44.1277911346.git.siccegge@cs.fau.de>

BACKLIGHT_CORGI doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-pxa/corgi_pm.c   |    2 --
 arch/arm/mach-pxa/sharpsl_pm.c |   15 ---------------
 arch/arm/mach-pxa/spitz_pm.c   |    2 --
 3 files changed, 0 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
index 3f1dc74..a735205 100644
--- a/arch/arm/mach-pxa/corgi_pm.c
+++ b/arch/arm/mach-pxa/corgi_pm.c
@@ -165,8 +165,6 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = {
 	.should_wakeup   = corgi_should_wakeup,
 #if defined(CONFIG_LCD_CORGI)
 	.backlight_limit = corgi_lcd_limit_intensity,
-#elif defined(CONFIG_BACKLIGHT_CORGI)
-	.backlight_limit = corgibl_limit_intensity,
 #endif
 	.charge_on_volt	  = SHARPSL_CHARGE_ON_VOLT,
 	.charge_on_temp	  = SHARPSL_CHARGE_ON_TEMP,
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index cb47672..582701e 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -277,21 +277,6 @@ static void sharpsl_battery_thread(struct work_struct *private_)
 	dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
 			sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
 
-#ifdef CONFIG_BACKLIGHT_CORGI
-	/* If battery is low. limit backlight intensity to save power. */
-	if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
-	    && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW)
-	    || (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL))) {
-		if (!(sharpsl_pm.flags & SHARPSL_BL_LIMIT)) {
-			sharpsl_pm.machinfo->backlight_limit(1);
-			sharpsl_pm.flags |= SHARPSL_BL_LIMIT;
-		}
-	} else if (sharpsl_pm.flags & SHARPSL_BL_LIMIT) {
-		sharpsl_pm.machinfo->backlight_limit(0);
-		sharpsl_pm.flags &= ~SHARPSL_BL_LIMIT;
-	}
-#endif
-
 	/* Suspend if critical battery level */
 	if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
 	     && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL)
diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
index 4209ddf..b36f0ae 100644
--- a/arch/arm/mach-pxa/spitz_pm.c
+++ b/arch/arm/mach-pxa/spitz_pm.c
@@ -212,8 +212,6 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = {
 	.should_wakeup    = spitz_should_wakeup,
 #if defined(CONFIG_LCD_CORGI)
 	.backlight_limit = corgi_lcd_limit_intensity,
-#elif defined(CONFIG_BACKLIGHT_CORGI)
-	.backlight_limit  = corgibl_limit_intensity,
 #endif
 	.charge_on_volt	  = SHARPSL_CHARGE_ON_VOLT,
 	.charge_on_temp	  = SHARPSL_CHARGE_ON_TEMP,
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:01:39 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:01:39 +0200
Subject: [PATCH 24/33] Removing dead ARCH_GUMSTIX_ORIG
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <e2a294ec1d41f1198f7ffae0e8bed2f67b41bbe8.1277911346.git.siccegge@cs.fau.de>

ARCH_GUMSTIX_ORIG doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-pxa/include/mach/gumstix.h |   12 +-----------
 1 files changed, 1 insertions(+), 11 deletions(-)

diff --git a/arch/arm/mach-pxa/include/mach/gumstix.h b/arch/arm/mach-pxa/include/mach/gumstix.h
index 06abd41..9b89868 100644
--- a/arch/arm/mach-pxa/include/mach/gumstix.h
+++ b/arch/arm/mach-pxa/include/mach/gumstix.h
@@ -14,25 +14,15 @@
 
 /*
 GPIOn - Input from MAX823 (or equiv), normalizing USB +5V into a clean
-interrupt signal for determining cable presence. On the original gumstix,
-this is GPIO81, and GPIO83 needs to be defined as well. On the gumstix F,
+interrupt signal for determining cable presence. On the gumstix F,
 this moves to GPIO17 and GPIO37. */
 
 /* GPIOx - Connects to USB D+ and used as a pull-up after GPIOn
 has detected a cable insertion; driven low otherwise. */
 
-#ifdef CONFIG_ARCH_GUMSTIX_ORIG
-
-#define GPIO_GUMSTIX_USB_GPIOn		81
-#define GPIO_GUMSTIX_USB_GPIOx		83
-
-#else
-
 #define GPIO_GUMSTIX_USB_GPIOn		35
 #define GPIO_GUMSTIX_USB_GPIOx		41
 
-#endif
-
 /* usb state change */
 #define GUMSTIX_USB_INTR_IRQ		IRQ_GPIO(GPIO_GUMSTIX_USB_GPIOn)
 
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:01:56 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:01:56 +0200
Subject: [PATCH 25/33] Removing dead CORGI_SSP_DEPRECATED
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <80c10751fb5b7d9be55656ac35827a403a5d6b2b.1277911346.git.siccegge@cs.fau.de>

CORGI_SSP_DEPRECATED doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-pxa/sharpsl_pm.c |    5 -----
 1 files changed, 0 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 582701e..d8c5301 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -180,17 +180,12 @@ int sharpsl_pm_pxa_read_max1111(int channel)
 	if (machine_is_tosa())
 	    return 0;
 
-#ifdef CONFIG_CORGI_SSP_DEPRECATED
-	return corgi_ssp_max1111_get((channel << MAXCTRL_SEL_SH) | MAXCTRL_PD0 | MAXCTRL_PD1
-			| MAXCTRL_SGL | MAXCTRL_UNI | MAXCTRL_STR);
-#else
 	extern int max1111_read_channel(int);
 
 	/* max1111 accepts channels from 0-3, however,
 	 * it is encoded from 0-7 here in the code.
 	 */
 	return max1111_read_channel(channel >> 1);
-#endif
 }
 
 static int get_percentage(int voltage)
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:02:14 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:02:14 +0200
Subject: [PATCH 26/33] Removing dead XSCALE_CACHE_ERRATA
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <e9515441013afc8e866f3081dd35bbe0122ece5e.1277911346.git.siccegge@cs.fau.de>

XSCALE_CACHE_ERRATA doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-pxa/sleep.S |    7 -------
 1 files changed, 0 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S
index 2ed95f3..52c30b0 100644
--- a/arch/arm/mach-pxa/sleep.S
+++ b/arch/arm/mach-pxa/sleep.S
@@ -339,10 +339,6 @@ ENTRY(pxa_cpu_resume)
 	mcr	p15, 0, r1, c8, c7, 0   	@ invalidate I & D TLBs
 	mcr	p15, 0, r1, c7, c7, 0		@ invalidate I & D caches, BTB
 
-#ifdef CONFIG_XSCALE_CACHE_ERRATA
-	bic     r9, r9, #0x0004			@ see cpu_xscale_proc_init
-#endif
-
 	mcr	p14, 0, r3, c6, c0, 0		@ clock configuration, turbo mode.
 	mcr	p15, 0, r4, c15, c1, 0		@ CP access reg
 	mcr	p15, 0, r5, c13, c0, 0		@ PID
@@ -368,9 +364,6 @@ sleep_save_sp:
 
 	.text
 resume_after_mmu:
-#ifdef CONFIG_XSCALE_CACHE_ERRATA
-	bl	cpu_xscale_proc_init
-#endif
 	ldmfd	sp!, {r2, r3}
 #ifndef CONFIG_IWMMXT
 	mar	acc0, r2, r3
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:02:32 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:02:32 +0200
Subject: [PATCH 27/33] Removing dead IDE_PXA_CF
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <a332e637ee15cb15f7099f5dfc19a384b2bf772b.1277911346.git.siccegge@cs.fau.de>

IDE_PXA_CF doesn't exist in Kconfig, therefore removing all references
for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-pxa/trizeps4.c |    6 +-----
 1 files changed, 1 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 6968911..0acff17 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -530,13 +530,9 @@ static void __init trizeps4_init(void)
 	i2c_register_board_info(0, trizeps4_i2c_devices,
 					ARRAY_SIZE(trizeps4_i2c_devices));
 
-#ifdef CONFIG_IDE_PXA_CF
-	/* if boot direct from compact flash dont disable power */
-	trizeps_conxs_bcr = 0x0009;
-#else
 	/* this is the reset value */
 	trizeps_conxs_bcr = 0x00A0;
-#endif
+
 	BCR_writew(trizeps_conxs_bcr);
 	board_backlight_power(1);
 }
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:02:51 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:02:51 +0200
Subject: [PATCH 28/33] Removing dead CPU_S3C24XX
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <787416813d524b042dc933fbcfbbae22fd5ca2ca.1277911346.git.siccegge@cs.fau.de>

CPU_S3C24XX doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-s3c2410/include/mach/gpio.h |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h b/arch/arm/mach-s3c2410/include/mach/gpio.h
index b649bf2..a37d274 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
@@ -30,8 +30,4 @@
 #include <mach/gpio-nrs.h>
 #include <mach/gpio-fns.h>
 
-#ifdef CONFIG_CPU_S3C24XX
-#define S3C_GPIO_END	(S3C2410_GPIO_BANKJ + 32)
-#else
 #define S3C_GPIO_END	(S3C2410_GPIO_BANKH + 32)
-#endif
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:03:10 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:03:10 +0200
Subject: [PATCH 29/33] Removing dead SND_SOC_SMDK2443_WM9710
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <e5391de6858597bbfd43874aed124a73f74850b5.1277911346.git.siccegge@cs.fau.de>

SND_SOC_SMDK2443_WM9710 doesn't exist in Kconfig, therefore removing
all references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-s3c2443/mach-smdk2443.c |    7 -------
 1 files changed, 0 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index 4c863d3..47414c9 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -106,9 +106,6 @@ static struct platform_device *smdk2443_devices[] __initdata = {
 	&s3c_device_wdt,
 	&s3c_device_i2c0,
 	&s3c_device_hsmmc0,
-#ifdef CONFIG_SND_SOC_SMDK2443_WM9710
-	&s3c_device_ac97,
-#endif
 };
 
 static void __init smdk2443_map_io(void)
@@ -122,10 +119,6 @@ static void __init smdk2443_machine_init(void)
 {
 	s3c_i2c0_set_platdata(NULL);
 
-#ifdef CONFIG_SND_SOC_SMDK2443_WM9710
-	s3c24xx_ac97_setup_gpio(S3C24XX_AC97_GPE0);
-#endif
-
 	platform_add_devices(smdk2443_devices, ARRAY_SIZE(smdk2443_devices));
 	smdk_machine_init();
 }
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:03:26 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:03:26 +0200
Subject: [PATCH 30/33] Removing dead S3C_DEV_ADC
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <7baaebb4983ce9482e3f83ca42240b864157cb79.1277911346.git.siccegge@cs.fau.de>

S3C_DEV_ADC doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-s5pv210/cpu.c |    4 ----
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 411a4a9..c5d53ab 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -76,10 +76,6 @@ static void s5pv210_idle(void)
 
 void __init s5pv210_map_io(void)
 {
-#ifdef CONFIG_S3C_DEV_ADC
-	s3c_device_adc.name	= "s3c64xx-adc";
-#endif
-
 	iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
 
 	/* initialise device information early */
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:03:43 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:03:43 +0200
Subject: [PATCH 31/33] Removing dead MACH_U300_BS26
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <2a81bf5506ce15ac839ca4fa58dc8af4112ff531.1277911346.git.siccegge@cs.fau.de>

MACH_U300_BS26 doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-u300/core.c |    7 -------
 1 files changed, 0 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 5f34eb6..653b3e0 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1561,13 +1561,6 @@ static void __init u300_init_check_chip(void)
 	printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
 	       "(chip ID 0x%04x)\n", chipname, val);
 
-#ifdef CONFIG_MACH_U300_BS26
-	if ((val & 0xFF00U) != 0xc800) {
-		printk(KERN_ERR "Platform configured for BS25/BS26 " \
-		       "with DB3150 but %s detected, expect problems!",
-		       chipname);
-	}
-#endif
 #ifdef CONFIG_MACH_U300_BS330
 	if ((val & 0xFF00U) != 0xd800) {
 		printk(KERN_ERR "Platform configured for BS330 " \
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:04:01 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:04:01 +0200
Subject: [PATCH 32/33] Removing dead CPU_ICACHE_STREAMING_DISABLE
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <c09196cb2149f5a1a845ead405b73add3c1a804f.1277911346.git.siccegge@cs.fau.de>

CPU_ICACHE_STREAMING_DISABLE doesn't exist in Kconfig, therefore
removing all references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mm/proc-arm925.S |    3 ---
 1 files changed, 0 insertions(+), 3 deletions(-)

diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 3c6cffe..2a3bb73 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -437,9 +437,6 @@ ENTRY(cpu_arm925_set_pte_ext)
 	.type	__arm925_setup, #function
 __arm925_setup:
 	mov	r0, #0
-#if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE)
-        orr     r0,r0,#1 << 7
-#endif
 
 	/* Transparent on, D-cache clean & flush mode. See  NOTE2 above */
         orr     r0,r0,#1 << 1			@ transparent mode on
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:04:18 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:04:18 +0200
Subject: [PATCH 33/33] Removing dead MACH_U300_USE_I2S_AS_MASTER
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <41be9a8afe8951b4ad23d43fcb57aca9a662cf43.1277911346.git.siccegge@cs.fau.de>

MACH_U300_USE_I2S_AS_MASTER doesn't exist in Kconfig, therefore
removing all references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-u300/clock.c |   91 --------------------------------------------
 1 files changed, 0 insertions(+), 91 deletions(-)

diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
index 5af71d5..80972a0 100644
--- a/arch/arm/mach-u300/clock.c
+++ b/arch/arm/mach-u300/clock.c
@@ -216,85 +216,6 @@ static u16 syscon_clk_get_rate(void)
 	return val;
 }
 
-#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
-static void enable_i2s0_vcxo(void)
-{
-	u16 val;
-	unsigned long iflags;
-
-	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-	/* Set I2S0 to use the VCXO 26 MHz clock */
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
-	val |= U300_SYSCON_CCR_TURN_VCXO_ON;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-	val |= U300_SYSCON_CCR_I2S0_USE_VCXO;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-	val |= U300_SYSCON_CEFR_I2S0_CLK_EN;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-}
-
-static void enable_i2s1_vcxo(void)
-{
-	u16 val;
-	unsigned long iflags;
-
-	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-	/* Set I2S1 to use the VCXO 26 MHz clock */
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
-	val |= U300_SYSCON_CCR_TURN_VCXO_ON;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-	val |= U300_SYSCON_CCR_I2S1_USE_VCXO;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-	val |= U300_SYSCON_CEFR_I2S1_CLK_EN;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-}
-
-static void disable_i2s0_vcxo(void)
-{
-	u16 val;
-	unsigned long iflags;
-
-	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-	/* Disable I2S0 use of the VCXO 26 MHz clock */
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
-	val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-	/* Deactivate VCXO if noone else is using VCXO */
-	if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
-		val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-	val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-}
-
-static void disable_i2s1_vcxo(void)
-{
-	u16 val;
-	unsigned long iflags;
-
-	spin_lock_irqsave(&syscon_clkreg_lock, iflags);
-	/* Disable I2S1 use of the VCXO 26 MHz clock */
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
-	val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-	/* Deactivate VCXO if noone else is using VCXO */
-	if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
-		val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
-	val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-	val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
-	writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
-	spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
-}
-#endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */
-
-
 static void syscon_clk_rate_set_mclk(unsigned long rate)
 {
 	u16 val;
@@ -383,12 +304,6 @@ void clk_disable(struct clk *clk)
 		if (likely((u32)clk->parent))
 			clk_disable(clk->parent);
 	}
-#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
-	if (unlikely(!strcmp(clk->name, "I2S0")))
-		disable_i2s0_vcxo();
-	if (unlikely(!strcmp(clk->name, "I2S1")))
-		disable_i2s1_vcxo();
-#endif
 	spin_unlock_irqrestore(&clk->lock, iflags);
 }
 EXPORT_SYMBOL(clk_disable);
@@ -411,12 +326,6 @@ int clk_enable(struct clk *clk)
 			/* clocks without enable function are always on */
 			if (clk->enable)
 				clk->enable(clk);
-#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
-			if (unlikely(!strcmp(clk->name, "I2S0")))
-				enable_i2s0_vcxo();
-			if (unlikely(!strcmp(clk->name, "I2S1")))
-				enable_i2s1_vcxo();
-#endif
 		}
 	}
 	spin_unlock_irqrestore(&clk->lock, iflags);
-- 
1.7.0.4



From siccegge at cs.fau.de  Wed Jun 30 12:05:38 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 18:05:38 +0200
Subject: [PATCH 02/33] Removing dead ARCH_DAVINCI_TNETV107X
In-Reply-To: <cover.1277911345.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
Message-ID: <88ee583babc6f0aecb2238a57644f64159d5c395.1277911346.git.siccegge@cs.fau.de>

ARCH_DAVINCI_TNETV107X doesn't exist in Kconfig, therefore removing
all references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
---
 arch/arm/mach-davinci/include/mach/cputype.h |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
index cea6b89..6143022 100644
--- a/arch/arm/mach-davinci/include/mach/cputype.h
+++ b/arch/arm/mach-davinci/include/mach/cputype.h
@@ -85,10 +85,4 @@ IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
 #define cpu_is_davinci_da850() 0
 #endif
 
-#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
-#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
-#else
-#define cpu_is_davinci_tnetv107x() 0
-#endif
-
 #endif
-- 
1.7.0.4



From arnaud.patard at rtp-net.org  Wed Jun 30 12:24:20 2010
From: arnaud.patard at rtp-net.org (Arnaud Patard (Rtp))
Date: Wed, 30 Jun 2010 18:24:20 +0200
Subject: [PATCH 30/33] Removing dead S3C_DEV_ADC
In-Reply-To: <7baaebb4983ce9482e3f83ca42240b864157cb79.1277911346.git.siccegge@cs.fau.de>
	(Christoph Egger's message of "Wed\,
	30 Jun 2010 18\:03\:26 +0200")
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<7baaebb4983ce9482e3f83ca42240b864157cb79.1277911346.git.siccegge@cs.fau.de>
Message-ID: <876310pjyj.fsf@lechat.rtp-net.org>

Christoph Egger <siccegge at cs.fau.de> writes:

> S3C_DEV_ADC doesn't exist in Kconfig, therefore removing all
> references for it from the source code.
>
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> ---
>  arch/arm/mach-s5pv210/cpu.c |    4 ----
>  1 files changed, 0 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
> index 411a4a9..c5d53ab 100644
> --- a/arch/arm/mach-s5pv210/cpu.c
> +++ b/arch/arm/mach-s5pv210/cpu.c
> @@ -76,10 +76,6 @@ static void s5pv210_idle(void)
>  
>  void __init s5pv210_map_io(void)
>  {
> -#ifdef CONFIG_S3C_DEV_ADC
> -	s3c_device_adc.name	= "s3c64xx-adc";
> -#endif
> -

too bad, should have been SAMSUNG_DEV_ADC :(
Anyway, a patch called "[PATCH] ARM: SAMSUNG: Implement set_name
function for ADC devices" has been sent for review today and is
addressing this same issue.

Thanks,
Arnaud


From nico at fluxnic.net  Wed Jun 30 12:57:43 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 30 Jun 2010 12:57:43 -0400 (EDT)
Subject: [PATCH 08/33] Removing dead SA1101
In-Reply-To: <7488ec29cdb90212e965f6cd1173141c576c0955.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<7488ec29cdb90212e965f6cd1173141c576c0955.1277911346.git.siccegge@cs.fau.de>
Message-ID: <alpine.LFD.2.00.1006301255260.24097@xanadu.home>

On Wed, 30 Jun 2010, Christoph Egger wrote:

> SA1101 doesn't exist in Kconfig, therefore removing all
> references for it from the source code.
> 
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>

Acked-by: Nicolas Pitre <nico at fluxnic.net>

> ---
>  arch/arm/mach-sa1100/include/mach/SA-1101.h  |  925 --------------------------
>  arch/arm/mach-sa1100/include/mach/hardware.h |    4 -
>  2 files changed, 0 insertions(+), 929 deletions(-)
>  delete mode 100644 arch/arm/mach-sa1100/include/mach/SA-1101.h
> 
[...]


Nicolas


From baruch at tkos.co.il  Wed Jun 30 13:00:26 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed, 30 Jun 2010 20:00:26 +0300
Subject: [PATCH] Add support for Vista Silicon i.MX27 Visstrim_M10 board.
In-Reply-To: <1277912661-24065-1-git-send-email-javier.martin@vista-silicon.com>
References: <1277912661-24065-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20100630170025.GD23534@tarshish>

Hi Javier,

On Wed, Jun 30, 2010 at 05:44:21PM +0200, Javier Martin wrote:
> 
> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
> ---
>  arch/arm/mach-mx2/Kconfig                          |    8 +
>  arch/arm/mach-mx2/Makefile                         |    1 +
>  arch/arm/mach-mx2/mach-imx27_visstrim_m10.c        |  279 ++++++++++++++++++++

This directory are no more. You should rebase your work on the imx-for-2.6.36 
branch of the imx tree at git://git.pengutronix.de/git/imx/linux-2.6.git

>  .../include/mach/board-imx27_visstrim_m10.h        |   24 ++

Any reason not to fold this file into mach-imx27_visstrim_m10.c?

baruch

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From baruch at tkos.co.il  Wed Jun 30 13:07:31 2010
From: baruch at tkos.co.il (Baruch Siach)
Date: Wed, 30 Jun 2010 20:07:31 +0300
Subject: [PATCH 02/33] Removing dead ARCH_DAVINCI_TNETV107X
In-Reply-To: <88ee583babc6f0aecb2238a57644f64159d5c395.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<88ee583babc6f0aecb2238a57644f64159d5c395.1277911346.git.siccegge@cs.fau.de>
Message-ID: <20100630170730.GE23534@tarshish>

Hi Christoph,

On Wed, Jun 30, 2010 at 06:05:38PM +0200, Christoph Egger wrote:
> ARCH_DAVINCI_TNETV107X doesn't exist in Kconfig, therefore removing
> all references for it from the source code.
> 
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> ---
>  arch/arm/mach-davinci/include/mach/cputype.h |    6 ------
>  1 files changed, 0 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
> index cea6b89..6143022 100644
> --- a/arch/arm/mach-davinci/include/mach/cputype.h
> +++ b/arch/arm/mach-davinci/include/mach/cputype.h
> @@ -85,10 +85,4 @@ IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
>  #define cpu_is_davinci_da850() 0
>  #endif
>  
> -#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
> -#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
> -#else
> -#define cpu_is_davinci_tnetv107x() 0

Why remove the #else part?

baruch

> -#endif
> -
>  #endif
> -- 
> 1.7.0.4

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -


From eric at eukrea.com  Wed Jun 30 13:36:49 2010
From: eric at eukrea.com (=?ISO-8859-1?Q?Eric_B=E9nard?=)
Date: Wed, 30 Jun 2010 19:36:49 +0200
Subject: [PATCH] Add support for Vista Silicon i.MX27 Visstrim_M10 board.
In-Reply-To: <20100630170025.GD23534@tarshish>
References: <1277912661-24065-1-git-send-email-javier.martin@vista-silicon.com>
	<20100630170025.GD23534@tarshish>
Message-ID: <4C2B80B1.1090308@eukrea.com>

Hi Baruch,

Le 30/06/2010 19:00, Baruch Siach a ?crit :
> On Wed, Jun 30, 2010 at 05:44:21PM +0200, Javier Martin wrote:
>>
>> Signed-off-by: Javier Martin<javier.martin at vista-silicon.com>
>> ---
>>   arch/arm/mach-mx2/Kconfig                          |    8 +
>>   arch/arm/mach-mx2/Makefile                         |    1 +
>>   arch/arm/mach-mx2/mach-imx27_visstrim_m10.c        |  279 ++++++++++++++++++++
>
> This directory are no more. You should rebase your work on the imx-for-2.6.36
> branch of the imx tree at git://git.pengutronix.de/git/imx/linux-2.6.git
>
unless I made a mistake with git, Uwe's patch serie seems to have been 
removed from this branch (I think it was merged this morning but I don't 
find it anymore now).

It is still available here : 
git://git.pengutronix.de/git/ukl/linux-2.6.git in branch 
imx/for-2.6.36-merged

Eric


From kirill at shutemov.name  Wed Jun 30 13:53:24 2010
From: kirill at shutemov.name (Kirill A. Shutemov)
Date: Wed, 30 Jun 2010 20:53:24 +0300
Subject: [PATCH 01/33] Removing dead MTD_NAND_AT91_BUSWIDTH_16
In-Reply-To: <4c6fe9a4c298214223ff89d06401ac7b66f81c98.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<4c6fe9a4c298214223ff89d06401ac7b66f81c98.1277911346.git.siccegge@cs.fau.de>
Message-ID: <20100630175324.GA3969@shutemov.name>

On Wed, Jun 30, 2010 at 05:53:52PM +0200, Christoph Egger wrote:
> MTD_NAND_AT91_BUSWIDTH_16 doesn't exist in Kconfig, therefore removing
> all references for it from the source code.

It was renamed to MTD_NAND_ATMEL_BUSWIDTH_16 (see f6ed6f7).

I think better to rename it here too.

> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> ---
>  arch/arm/mach-at91/board-at572d940hf_ek.c |    4 ----
>  arch/arm/mach-at91/board-sam9m10g45ek.c   |    4 ----
>  2 files changed, 0 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/board-at572d940hf_ek.c b/arch/arm/mach-at91/board-at572d940hf_ek.c
> index 5daff27..889a442 100644
> --- a/arch/arm/mach-at91/board-at572d940hf_ek.c
> +++ b/arch/arm/mach-at91/board-at572d940hf_ek.c
> @@ -216,11 +216,7 @@ static struct atmel_nand_data __initdata eb_nand_data = {
>  /*	.rdy_pin	= AT91_PIN_PC16, */
>  	.enable_pin	= AT91_PIN_PA15,
>  	.partition_info	= nand_partitions,
> -#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
> -	.bus_width_16	= 1,
> -#else
>  	.bus_width_16	= 0,
> -#endif
>  };
>  
>  static struct sam9_smc_config __initdata eb_nand_smc_config = {
> diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
> index ee80059..49ef850 100644
> --- a/arch/arm/mach-at91/board-sam9m10g45ek.c
> +++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
> @@ -135,11 +135,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
>  	.rdy_pin	= AT91_PIN_PC8,
>  	.enable_pin	= AT91_PIN_PC14,
>  	.partition_info	= nand_partitions,
> -#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
> -	.bus_width_16	= 1,
> -#else
>  	.bus_width_16	= 0,
> -#endif
>  };
>  
>  static struct sam9_smc_config __initdata ek_nand_smc_config = {
> -- 
> 1.7.0.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
 Kirill A. Shutemov


From anarsoul at gmail.com  Wed Jun 30 12:19:45 2010
From: anarsoul at gmail.com (Vasily Khoruzhick)
Date: Wed, 30 Jun 2010 19:19:45 +0300
Subject: [PATCH 28/33] Removing dead CPU_S3C24XX
In-Reply-To: <787416813d524b042dc933fbcfbbae22fd5ca2ca.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<787416813d524b042dc933fbcfbbae22fd5ca2ca.1277911346.git.siccegge@cs.fau.de>
Message-ID: <201006301919.51697.anarsoul@gmail.com>

? ????????? ?? 30 ???? 2010 19:02:51 ????? Christoph Egger ???????:
> CPU_S3C24XX doesn't exist in Kconfig, therefore removing all
> references for it from the source code.
> 
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> ---
>  arch/arm/mach-s3c2410/include/mach/gpio.h |    4 ----
>  1 files changed, 0 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/mach-s3c2410/include/mach/gpio.h
> b/arch/arm/mach-s3c2410/include/mach/gpio.h index b649bf2..a37d274 100644
> --- a/arch/arm/mach-s3c2410/include/mach/gpio.h
> +++ b/arch/arm/mach-s3c2410/include/mach/gpio.h
> @@ -30,8 +30,4 @@
>  #include <mach/gpio-nrs.h>
>  #include <mach/gpio-fns.h>
> 
> -#ifdef CONFIG_CPU_S3C24XX
> -#define S3C_GPIO_END	(S3C2410_GPIO_BANKJ + 32)
> -#else
>  #define S3C_GPIO_END	(S3C2410_GPIO_BANKH + 32)
> -#endif

This patch conflicts with Yaugen Kharuzhy patch (ARM: S3C24XX: Fix gpiolib 
support for ports K..M), S3C24XX is just a typo, it should be S3C244X and that 
was fixed by mentioned patch

Regards
Vasily
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From marek.vasut at gmail.com  Wed Jun 30 14:17:28 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 30 Jun 2010 20:17:28 +0200
Subject: [PATCH 27/33] Removing dead IDE_PXA_CF
In-Reply-To: <a332e637ee15cb15f7099f5dfc19a384b2bf772b.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<a332e637ee15cb15f7099f5dfc19a384b2bf772b.1277911346.git.siccegge@cs.fau.de>
Message-ID: <201006302017.28731.marek.vasut@gmail.com>

Dne St 30. ?ervna 2010 18:02:32 Christoph Egger napsal(a):
> IDE_PXA_CF doesn't exist in Kconfig, therefore removing all references
> for it from the source code.

This thing would be on purpose I believe ... maybe documenting it better won't 
hurt though.
> 
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> ---
>  arch/arm/mach-pxa/trizeps4.c |    6 +-----
>  1 files changed, 1 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
> index 6968911..0acff17 100644
> --- a/arch/arm/mach-pxa/trizeps4.c
> +++ b/arch/arm/mach-pxa/trizeps4.c
> @@ -530,13 +530,9 @@ static void __init trizeps4_init(void)
>  	i2c_register_board_info(0, trizeps4_i2c_devices,
>  					ARRAY_SIZE(trizeps4_i2c_devices));
> 
> -#ifdef CONFIG_IDE_PXA_CF
> -	/* if boot direct from compact flash dont disable power */
> -	trizeps_conxs_bcr = 0x0009;
> -#else
>  	/* this is the reset value */
>  	trizeps_conxs_bcr = 0x00A0;
> -#endif
> +
>  	BCR_writew(trizeps_conxs_bcr);
>  	board_backlight_power(1);
>  }


From marek.vasut at gmail.com  Wed Jun 30 14:20:52 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 30 Jun 2010 20:20:52 +0200
Subject: [PATCH 08/33] Removing dead SA1101
In-Reply-To: <alpine.LFD.2.00.1006301255260.24097@xanadu.home>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<7488ec29cdb90212e965f6cd1173141c576c0955.1277911346.git.siccegge@cs.fau.de>
	<alpine.LFD.2.00.1006301255260.24097@xanadu.home>
Message-ID: <201006302020.52270.marek.vasut@gmail.com>

Dne St 30. ?ervna 2010 18:57:43 Nicolas Pitre napsal(a):
> On Wed, 30 Jun 2010, Christoph Egger wrote:
> > SA1101 doesn't exist in Kconfig, therefore removing all
> > references for it from the source code.
> > 
> > Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> 
> Acked-by: Nicolas Pitre <nico at fluxnic.net>

You're dropping support for a whole CPU here ... is the code redundant or 
something ?
> 
> > ---
> > 
> >  arch/arm/mach-sa1100/include/mach/SA-1101.h  |  925
> >  -------------------------- arch/arm/mach-sa1100/include/mach/hardware.h
> >  |    4 -
> >  2 files changed, 0 insertions(+), 929 deletions(-)
> >  delete mode 100644 arch/arm/mach-sa1100/include/mach/SA-1101.h
> 
> [...]
> 
> 
> Nicolas
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel


From Hiroshi.DOYU at nokia.com  Wed Jun 30 14:23:46 2010
From: Hiroshi.DOYU at nokia.com (Hiroshi DOYU)
Date: Wed, 30 Jun 2010 21:23:46 +0300 (EEST)
Subject: [PATCH 22/33] Removing dead MPU_{BRIDGE,TESLA}_IOMMU
In-Reply-To: <fcfa44a43c21c70f89ced96b96d7c1489d28cc51.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<fcfa44a43c21c70f89ced96b96d7c1489d28cc51.1277911346.git.siccegge@cs.fau.de>
Message-ID: <20100630.212346.226780589.Hiroshi.DOYU@nokia.com>

From: ext Christoph Egger <siccegge at cs.fau.de>
Subject: [PATCH 22/33] Removing dead MPU_{BRIDGE,TESLA}_IOMMU
Date: Wed, 30 Jun 2010 18:01:01 +0200

> MPU_{BRIDGE,TESLA}_IOMMU doesn't exist in Kconfig, therefore removing
> all references for it from the source code.

Coming soon, I guess. Hari?

> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> ---
>  arch/arm/mach-omap2/omap-iommu.c |   22 ----------------------
>  1 files changed, 0 insertions(+), 22 deletions(-)
> 
> diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
> index eb9bee7..3aa3fe9 100644
> --- a/arch/arm/mach-omap2/omap-iommu.c
> +++ b/arch/arm/mach-omap2/omap-iommu.c
> @@ -35,17 +35,6 @@ static struct iommu_device omap3_devices[] = {
>  			.clk_name = "cam_ick",
>  		},
>  	},
> -#if defined(CONFIG_MPU_BRIDGE_IOMMU)
> -	{
> -		.base = 0x5d000000,
> -		.irq = 28,
> -		.pdata = {
> -			.name = "iva2",
> -			.nr_tlb_entries = 32,
> -			.clk_name = "iva2_ck",
> -		},
> -	},
> -#endif
>  };
>  #define NR_OMAP3_IOMMU_DEVICES ARRAY_SIZE(omap3_devices)
>  static struct platform_device *omap3_iommu_pdev[NR_OMAP3_IOMMU_DEVICES];
> @@ -66,17 +55,6 @@ static struct iommu_device omap4_devices[] = {
>  			.clk_name = "ducati_ick",
>  		},
>  	},
> -#if defined(CONFIG_MPU_TESLA_IOMMU)
> -	{
> -		.base = OMAP4_MMU2_BASE,
> -		.irq = INT_44XX_DSP_MMU,
> -		.pdata = {
> -			.name = "tesla",
> -			.nr_tlb_entries = 32,
> -			.clk_name = "tesla_ick",
> -		},
> -	},
> -#endif
>  };
>  #define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices)
>  static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES];
> -- 
> 1.7.0.4
> 


From marek.vasut at gmail.com  Wed Jun 30 14:23:47 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 30 Jun 2010 20:23:47 +0200
Subject: [PATCH 16/33] Removing dead APM
In-Reply-To: <51c095a4c49baacbfdd6ed332d1375ab64209753.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<51c095a4c49baacbfdd6ed332d1375ab64209753.1277911346.git.siccegge@cs.fau.de>
Message-ID: <201006302023.47382.marek.vasut@gmail.com>

Dne St 30. ?ervna 2010 17:59:06 Christoph Egger napsal(a):
> APM doesn't exist in Kconfig, therefore removing all references for it
> from the source code.

Tony, do you know Andrzej Zaborowski's new email address? Maybe he should be 
CCed here
> 
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> ---
>  arch/arm/mach-omap1/board-palmte.c |   84
> ------------------------------------ 1 files changed, 0 insertions(+), 84
> deletions(-)
> 
> diff --git a/arch/arm/mach-omap1/board-palmte.c
> b/arch/arm/mach-omap1/board-palmte.c index 569b4c9..23bb0c9 100644
> --- a/arch/arm/mach-omap1/board-palmte.c
> +++ b/arch/arm/mach-omap1/board-palmte.c
> @@ -213,90 +213,6 @@ static struct omap_lcd_config palmte_lcd_config
> __initdata = { .ctrl_name	= "internal",
>  };
> 
> -#ifdef CONFIG_APM
> -/*
> - * Values measured in 10 minute intervals averaged over 10 samples.
> - * May differ slightly from device to device but should be accurate
> - * enough to give basic idea of battery life left and trigger
> - * potential alerts.
> - */
> -static const int palmte_battery_sample[] = {
> -	2194, 2157, 2138, 2120,
> -	2104, 2089, 2075, 2061,
> -	2048, 2038, 2026, 2016,
> -	2008, 1998, 1989, 1980,
> -	1970, 1958, 1945, 1928,
> -	1910, 1888, 1860, 1827,
> -	1791, 1751, 1709, 1656,
> -};
> -
> -#define INTERVAL		10
> -#define BATTERY_HIGH_TRESHOLD	66
> -#define BATTERY_LOW_TRESHOLD	33
> -
> -static void palmte_get_power_status(struct apm_power_info *info, int
> *battery) -{
> -	int charging, batt, hi, lo, mid;
> -
> -	charging = !gpio_get_value(PALMTE_DC_GPIO);
> -	batt = battery[0];
> -	if (charging)
> -		batt -= 60;
> -
> -	hi = ARRAY_SIZE(palmte_battery_sample);
> -	lo = 0;
> -
> -	info->battery_flag = 0;
> -	info->units = APM_UNITS_MINS;
> -
> -	if (batt > palmte_battery_sample[lo]) {
> -		info->battery_life = 100;
> -		info->time = INTERVAL * ARRAY_SIZE(palmte_battery_sample);
> -	} else if (batt <= palmte_battery_sample[hi - 1]) {
> -		info->battery_life = 0;
> -		info->time = 0;
> -	} else {
> -		while (hi > lo + 1) {
> -			mid = (hi + lo) >> 1;
> -			if (batt <= palmte_battery_sample[mid])
> -				lo = mid;
> -			else
> -				hi = mid;
> -		}
> -
> -		mid = palmte_battery_sample[lo] - palmte_battery_sample[hi];
> -		hi = palmte_battery_sample[lo] - batt;
> -		info->battery_life = 100 - (100 * lo + 100 * hi / mid) /
> -			ARRAY_SIZE(palmte_battery_sample);
> -		info->time = INTERVAL * (ARRAY_SIZE(palmte_battery_sample) -
> -				lo) - INTERVAL * hi / mid;
> -	}
> -
> -	if (charging) {
> -		info->ac_line_status = APM_AC_ONLINE;
> -		info->battery_status = APM_BATTERY_STATUS_CHARGING;
> -		info->battery_flag |= APM_BATTERY_FLAG_CHARGING;
> -	} else {
> -		info->ac_line_status = APM_AC_OFFLINE;
> -		if (info->battery_life > BATTERY_HIGH_TRESHOLD)
> -			info->battery_status = APM_BATTERY_STATUS_HIGH;
> -		else if (info->battery_life > BATTERY_LOW_TRESHOLD)
> -			info->battery_status = APM_BATTERY_STATUS_LOW;
> -		else
> -			info->battery_status = APM_BATTERY_STATUS_CRITICAL;
> -	}
> -
> -	if (info->battery_life > BATTERY_HIGH_TRESHOLD)
> -		info->battery_flag |= APM_BATTERY_FLAG_HIGH;
> -	else if (info->battery_life > BATTERY_LOW_TRESHOLD)
> -		info->battery_flag |= APM_BATTERY_FLAG_LOW;
> -	else
> -		info->battery_flag |= APM_BATTERY_FLAG_CRITICAL;
> -}
> -#else
> -#define palmte_get_power_status	NULL
> -#endif
> -
>  static struct omap_board_config_kernel palmte_config[] __initdata = {
>  	{ OMAP_TAG_LCD,		&palmte_lcd_config },
>  };


From marek.vasut at gmail.com  Wed Jun 30 14:24:46 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 30 Jun 2010 20:24:46 +0200
Subject: [PATCH 17/33] Removing dead SX1_OLD_FLASH
In-Reply-To: <5b21086199b139a61888c16e92d3efe6b205dae2.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<5b21086199b139a61888c16e92d3efe6b205dae2.1277911346.git.siccegge@cs.fau.de>
Message-ID: <201006302024.47025.marek.vasut@gmail.com>

Dne St 30. ?ervna 2010 17:59:25 Christoph Egger napsal(a):
> SX1_OLD_FLASH doesn't exist in Kconfig, therefore removing all
> references for it from the source code.

There were two models of the phone made, you can toggle between old and new 
version. Maybe better documentation won't hurt.
> 
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> ---
>  arch/arm/mach-omap1/board-sx1.c |   26 --------------------------
>  1 files changed, 0 insertions(+), 26 deletions(-)
> 
> diff --git a/arch/arm/mach-omap1/board-sx1.c
> b/arch/arm/mach-omap1/board-sx1.c index 2fb1e5f..1de809d 100644
> --- a/arch/arm/mach-omap1/board-sx1.c
> +++ b/arch/arm/mach-omap1/board-sx1.c
> @@ -295,31 +295,6 @@ static struct physmap_flash_data sx1_flash_data = {
>  	.nr_parts	= ARRAY_SIZE(sx1_partitions),
>  };
> 
> -#ifdef CONFIG_SX1_OLD_FLASH
> -/* MTD Intel StrataFlash - old flashes */
> -static struct resource sx1_old_flash_resource[] = {
> -	[0] = {
> -		.start	= OMAP_CS0_PHYS,	/* Physical */
> -		.end	= OMAP_CS0_PHYS + SZ_16M - 1,,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -	[1] = {
> -		.start	= OMAP_CS1_PHYS,
> -		.end	= OMAP_CS1_PHYS + SZ_8M - 1,
> -		.flags	= IORESOURCE_MEM,
> -	},
> -};
> -
> -static struct platform_device sx1_flash_device = {
> -	.name		= "physmap-flash",
> -	.id		= 0,
> -	.dev		= {
> -		.platform_data	= &sx1_flash_data,
> -	},
> -	.num_resources	= 2,
> -	.resource	= &sx1_old_flash_resource,
> -};
> -#else
>  /* MTD Intel 4000 flash - new flashes */
>  static struct resource sx1_new_flash_resource = {
>  	.start		= OMAP_CS0_PHYS,
> @@ -336,7 +311,6 @@ static struct platform_device sx1_flash_device = {
>  	.num_resources	= 1,
>  	.resource	= &sx1_new_flash_resource,
>  };
> -#endif
> 
>  /*----------- USB -------------------------*/


From marek.vasut at gmail.com  Wed Jun 30 14:25:14 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Wed, 30 Jun 2010 20:25:14 +0200
Subject: [PATCH 18/33] Removing dead OMAP_ARM_96MHZ
In-Reply-To: <8304abb0dbda307c488b6fe2b3cc8df3c9909eb6.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<8304abb0dbda307c488b6fe2b3cc8df3c9909eb6.1277911346.git.siccegge@cs.fau.de>
Message-ID: <201006302025.14881.marek.vasut@gmail.com>

Dne St 30. ?ervna 2010 17:59:45 Christoph Egger napsal(a):
> OMAP_ARM_96MHZ doesn't exist in Kconfig, therefore removing all
> references for it from the source code.

I'd be for adding it to Kconfig rather than removing from here
> 
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> ---
>  arch/arm/mach-omap1/opp_data.c |    3 ---
>  1 files changed, 0 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/mach-omap1/opp_data.c
> b/arch/arm/mach-omap1/opp_data.c index 75a5465..060df86 100644
> --- a/arch/arm/mach-omap1/opp_data.c
> +++ b/arch/arm/mach-omap1/opp_data.c
> @@ -45,9 +45,6 @@ struct mpu_rate omap1_rate_table[] = {
>  #if defined(CONFIG_OMAP_ARM_120MHZ)
>  	{ 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
>  #endif
> -#if defined(CONFIG_OMAP_ARM_96MHZ)
> -	{  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
> -#endif
>  #if defined(CONFIG_OMAP_ARM_60MHZ)
>  	{  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
>  #endif


From h-kanigeri2 at ti.com  Wed Jun 30 14:44:14 2010
From: h-kanigeri2 at ti.com (Kanigeri, Hari)
Date: Wed, 30 Jun 2010 13:44:14 -0500
Subject: [PATCH 22/33] Removing dead MPU_{BRIDGE,TESLA}_IOMMU
In-Reply-To: <20100630.212346.226780589.Hiroshi.DOYU@nokia.com>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<fcfa44a43c21c70f89ced96b96d7c1489d28cc51.1277911346.git.siccegge@cs.fau.de>
	<20100630.212346.226780589.Hiroshi.DOYU@nokia.com>
Message-ID: <8F7AF80515AF0D4D93307E594F3CB40E4CA55915@dlee03.ent.ti.com>


> -----Original Message-----
> From: Hiroshi DOYU [mailto:Hiroshi.DOYU at nokia.com]
> Sent: Wednesday, June 30, 2010 1:24 PM
> To: siccegge at cs.fau.de; Kanigeri, Hari
> Cc: tony at atomide.com; linux at arm.linux.org.uk; linux-omap at vger.kernel.org;
> linux-arm-kernel at lists.infradead.org; linux-kernel at vger.kernel.org;
> vamos at i4.informatik.uni-erlangen.de
> Subject: Re: [PATCH 22/33] Removing dead MPU_{BRIDGE,TESLA}_IOMMU
> 
> From: ext Christoph Egger <siccegge at cs.fau.de>
> Subject: [PATCH 22/33] Removing dead MPU_{BRIDGE,TESLA}_IOMMU
> Date: Wed, 30 Jun 2010 18:01:01 +0200
> 
> > MPU_{BRIDGE,TESLA}_IOMMU doesn't exist in Kconfig, therefore removing
> > all references for it from the source code.
> 
> Coming soon, I guess. Hari?

Coming soon for both Bridge and Tesla. As I am writing this email, Fernando is preparing the Bridge patches to migrate to iommu.

Thank you,
Best regards,
Hari


From nico at fluxnic.net  Wed Jun 30 14:59:05 2010
From: nico at fluxnic.net (Nicolas Pitre)
Date: Wed, 30 Jun 2010 14:59:05 -0400 (EDT)
Subject: [PATCH 08/33] Removing dead SA1101
In-Reply-To: <201006302020.52270.marek.vasut@gmail.com>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<7488ec29cdb90212e965f6cd1173141c576c0955.1277911346.git.siccegge@cs.fau.de>
	<alpine.LFD.2.00.1006301255260.24097@xanadu.home>
	<201006302020.52270.marek.vasut@gmail.com>
Message-ID: <alpine.LFD.2.00.1006301453450.24097@xanadu.home>

On Wed, 30 Jun 2010, Marek Vasut wrote:

> Dne St 30. ?ervna 2010 18:57:43 Nicolas Pitre napsal(a):
> > On Wed, 30 Jun 2010, Christoph Egger wrote:
> > > SA1101 doesn't exist in Kconfig, therefore removing all
> > > references for it from the source code.
> > > 
> > > Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> > 
> > Acked-by: Nicolas Pitre <nico at fluxnic.net>
> 
> You're dropping support for a whole CPU here ... is the code redundant or 
> something ?

The SA1101 is not a CPU.  It is a companion chipset for the SA1100.  And 
so far we have no target using it in the tree, and that isn't likely to 
change more than 10 years after the chip availability.  Needless to say 
that the SA1101 has long been unavailable either.

We also have support for the SA1111 which is a similar companion chipset 
for the SA1110.  This is not going away as at least the Neponset 
expansion board for the Assabet development board is using a SA1111.


Nicolas

From u.kleine-koenig at pengutronix.de  Wed Jun 30 15:16:37 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 30 Jun 2010 21:16:37 +0200
Subject: [PATCH] Add support for Vista Silicon i.MX27 Visstrim_M10 board.
In-Reply-To: <4C2B80B1.1090308@eukrea.com>
References: <1277912661-24065-1-git-send-email-javier.martin@vista-silicon.com>
	<20100630170025.GD23534@tarshish> <4C2B80B1.1090308@eukrea.com>
Message-ID: <20100630191637.GA11643@pengutronix.de>

On Wed, Jun 30, 2010 at 07:36:49PM +0200, Eric B?nard wrote:
> Hi Baruch,
>
> Le 30/06/2010 19:00, Baruch Siach a ?crit :
>> On Wed, Jun 30, 2010 at 05:44:21PM +0200, Javier Martin wrote:
>>>
>>> Signed-off-by: Javier Martin<javier.martin at vista-silicon.com>
>>> ---
>>>   arch/arm/mach-mx2/Kconfig                          |    8 +
>>>   arch/arm/mach-mx2/Makefile                         |    1 +
>>>   arch/arm/mach-mx2/mach-imx27_visstrim_m10.c        |  279 ++++++++++++++++++++
>>
>> This directory are no more. You should rebase your work on the imx-for-2.6.36
>> branch of the imx tree at git://git.pengutronix.de/git/imx/linux-2.6.git
>>
> unless I made a mistake with git, Uwe's patch serie seems to have been  
> removed from this branch (I think it was merged this morning but I don't  
> find it anymore now).
>
> It is still available here :  
> git://git.pengutronix.de/git/ukl/linux-2.6.git in branch  
> imx/for-2.6.36-merged
Note that this changed earlier today, too.  Sascha rebased his branch
and I merged his new tree after doing some cosmetics to mine, too.  I
expect Sascha to pull my -merged branch soon.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From u.kleine-koenig at pengutronix.de  Wed Jun 30 15:22:55 2010
From: u.kleine-koenig at pengutronix.de (Uwe =?iso-8859-1?Q?Kleine-K=F6nig?=)
Date: Wed, 30 Jun 2010 21:22:55 +0200
Subject: [PATCH] Add support for Vista Silicon i.MX27 Visstrim_M10 board.
In-Reply-To: <1277912661-24065-1-git-send-email-javier.martin@vista-silicon.com>
References: <1277912661-24065-1-git-send-email-javier.martin@vista-silicon.com>
Message-ID: <20100630192255.GB11643@pengutronix.de>

Hello Javier,

On Wed, Jun 30, 2010 at 05:44:21PM +0200, Javier Martin wrote:
> 
> Signed-off-by: Javier Martin <javier.martin at vista-silicon.com>
> ---
>  arch/arm/mach-mx2/Kconfig                          |    8 +
>  arch/arm/mach-mx2/Makefile                         |    1 +
>  arch/arm/mach-mx2/mach-imx27_visstrim_m10.c        |  279 ++++++++++++++++++++
>  .../include/mach/board-imx27_visstrim_m10.h        |   24 ++
>  4 files changed, 312 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-mx2/mach-imx27_visstrim_m10.c
>  create mode 100644 arch/arm/plat-mxc/include/mach/board-imx27_visstrim_m10.h
> 
> diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
> index 742fd4e..432eb78 100644
> --- a/arch/arm/mach-mx2/Kconfig
> +++ b/arch/arm/mach-mx2/Kconfig
> @@ -91,6 +91,14 @@ config MACH_MX27_3DS
>  	  Include support for MX27PDK platform. This includes specific
>  	  configurations for the board and its peripherals.
>  
> +config MACH_IMX27_VISSTRIM_M10
> +	bool "Vista Silicon i.MX27 Visstrim_m10"
> +	depends on MACH_MX27
> +	help
> +	  Include support for Visstrim_m10 platform and its different variants.
> +	  This includes specific configurations for the board and its
> +	  peripherals.
> +
>  config MACH_IMX27LITE
>  	bool "LogicPD MX27 LITEKIT platform"
>  	depends on MACH_MX27
> diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
> index e3254fa..fbc54a9 100644
> --- a/arch/arm/mach-mx2/Makefile
> +++ b/arch/arm/mach-mx2/Makefile
> @@ -17,6 +17,7 @@ obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
>  obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
>  obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
>  obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
> +obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
>  obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
>  obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
>  obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
> diff --git a/arch/arm/mach-mx2/mach-imx27_visstrim_m10.c b/arch/arm/mach-mx2/mach-imx27_visstrim_m10.c
> new file mode 100644
> index 0000000..1acd47a
> --- /dev/null
> +++ b/arch/arm/mach-mx2/mach-imx27_visstrim_m10.c
> @@ -0,0 +1,279 @@
> +/*
> + * mach-imx27_visstrim_m10.c
> + *
> + * Copyright 2010 Vista Silicon S.L.
> + *		Javier Martin <javier.martin at vista-silicon.com>
> + *
> + * Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA  02111-1307  USA
This address is old, I suggest to just remove the last paragraph.
> + */
> +
> +#include <linux/platform_device.h>
> +#include <linux/mtd/physmap.h>
> +#include <mach/common.h>
> +#include <asm/mach-types.h>
> +#include <asm/mach/arch.h>
> +#include <asm/mach/time.h>
> +#include <mach/gpio.h>
> +#include <mach/mmc.h>
> +#include <mach/imx-uart.h>
> +#include <mach/iomux.h>
> +#include <mach/board-imx27_visstrim_m10.h>
> +#include <mach/mxc_ehci.h>
> +#include <mach/i2c.h>
> +#include <linux/i2c.h>
> +#include <linux/i2c/pca953x.h>
> +#include <linux/gpio_keys.h>
> +#include <linux/input.h>

As Baruch already pointed out, you need some adaptions after the latest
changes I did.  Just ask if you have problems.  (Hint, you have to
include devices-imx27.h and use the macros defined in that header.  You
can make all pdata __initconst then.)

> +#include "devices.h"
> +
> +static int visstrim_m10_pins[] = {
> +	/* UART1 (console) */
> +	PE12_PF_UART1_TXD,
> +	PE13_PF_UART1_RXD,
> +	PE14_PF_UART1_CTS,
> +	PE15_PF_UART1_RTS,
> +	/* FEC */
> +	PD0_AIN_FEC_TXD0,
> +	PD1_AIN_FEC_TXD1,
> +	PD2_AIN_FEC_TXD2,
> +	PD3_AIN_FEC_TXD3,
> +	PD4_AOUT_FEC_RX_ER,
> +	PD5_AOUT_FEC_RXD1,
> +	PD6_AOUT_FEC_RXD2,
> +	PD7_AOUT_FEC_RXD3,
> +	PD8_AF_FEC_MDIO,
> +	PD9_AIN_FEC_MDC,
> +	PD10_AOUT_FEC_CRS,
> +	PD11_AOUT_FEC_TX_CLK,
> +	PD12_AOUT_FEC_RXD0,
> +	PD13_AOUT_FEC_RX_DV,
> +	PD14_AOUT_FEC_RX_CLK,
> +	PD15_AOUT_FEC_COL,
> +	PD16_AIN_FEC_TX_ER,
> +	PF23_AIN_FEC_TX_EN,
> +	/* SDHC1 */
> +	PE18_PF_SD1_D0,
> +	PE19_PF_SD1_D1,
> +	PE20_PF_SD1_D2,
> +	PE21_PF_SD1_D3,
> +	PE22_PF_SD1_CMD,
> +	PE23_PF_SD1_CLK,
> +	/* I2C1 */
> +	PD17_PF_I2C_DATA,
> +	PD18_PF_I2C_CLK,
> +	/* USB OTG */
> +	OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
> +	PC9_PF_USBOTG_DATA0,
> +	PC11_PF_USBOTG_DATA1,
> +	PC10_PF_USBOTG_DATA2,
> +	PC13_PF_USBOTG_DATA3,
> +	PC12_PF_USBOTG_DATA4,
> +	PC7_PF_USBOTG_DATA5,
> +	PC8_PF_USBOTG_DATA6,
> +	PE25_PF_USBOTG_DATA7,
> +	PE24_PF_USBOTG_CLK,
> +	PE2_PF_USBOTG_DIR,
> +	PE0_PF_USBOTG_NXT,
> +	PE1_PF_USBOTG_STP,
> +	PB23_PF_USB_PWR,
> +	PB24_PF_USB_OC,
> +};
> +
> +/* GPIOs used as events for applications */
> +static struct gpio_keys_button visstrim_gpio_keys[] = {
> +	{
> +		.type	= EV_KEY,
> +		.code	= KEY_RESTART,
> +		.gpio	= (GPIO_PORTC + 15),
> +		.desc	= "Default config",
> +		.active_low = 0,
> +		.wakeup = 1,
> +	},
> +	{
> +		.type	= EV_KEY,
> +		.code	= KEY_RECORD,
> +		.gpio	= (GPIO_PORTF + 14),
> +		.desc	= "Record",
> +		.active_low = 0,
> +		.wakeup = 1,
> +	},
> +	{
> +		.type   = EV_KEY,
> +		.code   = KEY_STOP,
> +		.gpio   = (GPIO_PORTF + 13),
> +		.desc   = "Stop",
> +		.active_low = 0,
> +		.wakeup = 1,
> +	}
> +};
> +
> +static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = {
> +	.buttons	= visstrim_gpio_keys,
> +	.nbuttons	= ARRAY_SIZE(visstrim_gpio_keys),
> +};
> +
> +static struct platform_device visstrim_gpio_keys_device = {
> +	.name	= "gpio-keys",
> +	.id	= -1,
> +	.dev	= {
> +		.platform_data	= &visstrim_gpio_keys_platform_data,
> +	},
> +};
> +
> +/* Visstrim_SM10 has a microSD slot connected to sdhc2*/
> +static int visstrim_m10_sdhc1_init(struct device *dev,
> +		irq_handler_t detect_irq, void *data)
> +{
> +	int ret;
> +
> +	ret = request_irq(IRQ_GPIOB(25), detect_irq, IRQF_TRIGGER_FALLING,
> +				"mmc-detect", data);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
> +{
> +	free_irq(IRQ_GPIOB(25), data);
> +}
> +
> +static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = {
> +	.init = visstrim_m10_sdhc1_init,
> +	.exit = visstrim_m10_sdhc1_exit,
> +};
> +
> +/* Visstrim_SM10 NOR flash */
> +static struct physmap_flash_data visstrim_m10_flash_data = {
> +	.width = 2,
> +};
> +
> +static struct resource visstrim_m10_flash_resource = {
> +	.start = 0xc0000000,
> +	.end = 0xc0000000 + 0x04000000 - 1,
> +	.flags = IORESOURCE_MEM,
> +
> +};
> +
> +static struct platform_device visstrim_m10_nor_mtd_device = {
> +	.name = "physmap-flash",
> +	.id = 0,
> +	.dev = {
> +		.platform_data = &visstrim_m10_flash_data,
> +	},
> +	.num_resources = 1,
> +	.resource = &visstrim_m10_flash_resource,
> +};
> +
> +static struct platform_device *platform_devices[] __initdata = {
> +	&visstrim_m10_nor_mtd_device,
> +	&mxc_fec_device,
> +};
> +
> +/* Visstrim_M10 uses UART0 as console */
> +static struct imxuart_platform_data uart_pdata[] = {
> +	{
> +		.flags = IMXUART_HAVE_RTSCTS,
> +	},
> +};
> +
> +/* Visstrim_M10 has several devices attached to I2C1 */
> +static struct imxi2c_platform_data visstrim_m10_i2c_1_data = {
> +	.bitrate = 100000,
> +};
> +
> +static int visstrim_m10_pca9555_setup(struct i2c_client *client,
> +				unsigned gpio_base, unsigned ngpio,
> +				void *context)
> +{
> +	int i;
> +
> +	for (i = 0; i < ngpio; i++) {
> +		gpio_request(gpio_base + i, "Visstrim_m10 GPIO Exp");
> +		gpio_export(gpio_base + i, 1);
> +	}
> +	return 0;
> +}
> +
> +static struct pca953x_platform_data visstrim_m10_pca9555_pdata = {
> +	.gpio_base = 240, /* After MX27 internal GPIOs */
> +	.invert = 0,
> +	.setup = visstrim_m10_pca9555_setup,
> +};
> +
> +static struct i2c_board_info visstrim_m10_i2c_devices[] = {
> +	{
> +		I2C_BOARD_INFO("pca9555", 0x20),
> +		.platform_data = &visstrim_m10_pca9555_pdata,
> +	},
> +};
> +
> +/* USB OTG */
> +static int otg_phy_init(struct platform_device *pdev)
> +{
> +	gpio_set_value(OTG_PHY_CS_GPIO, 0);
> +	return 0;
> +}
> +
> +static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = {
> +	.init = otg_phy_init,
> +	.portsc	= MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
> +	.flags	= MXC_EHCI_POWER_PINS_ENABLED,
> +};
> +
> +static void __init visstrim_m10_board_init(void)
> +{
> +	int ret;
> +
> +	ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins,
> +			ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10");
> +	if (ret)
> +		printk(KERN_ERR "visstrim_m10: Failed tu setup pins (%d)\n",
> +				ret);
> +
> +	mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
> +
> +	i2c_register_board_info(0, visstrim_m10_i2c_devices,
> +				ARRAY_SIZE(visstrim_m10_i2c_devices));
> +
> +	mxc_register_device(&mxc_i2c_device0, &visstrim_m10_i2c_1_data);
> +	mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata);
> +	mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata);
> +	platform_device_register(&visstrim_gpio_keys_device);
> +	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
> +}
> +
> +static void __init visstrim_m10_timer_init(void)
> +{
> +	mx27_clocks_init((unsigned long)25000000);
> +}
> +
> +static struct sys_timer visstrim_m10_timer = {
> +	.init	= visstrim_m10_timer_init,
> +};
> +
> +MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
> +	.phys_io        = MX27_AIPI_BASE_ADDR,
> +	.io_pg_offst    = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
> +	.boot_params    = MX27_PHYS_OFFSET + 0x100,
> +	.map_io         = mx27_map_io,
> +	.init_irq       = mx27_init_irq,
> +	.init_machine   = visstrim_m10_board_init,
> +	.timer          = &visstrim_m10_timer,
> +MACHINE_END
> diff --git a/arch/arm/plat-mxc/include/mach/board-imx27_visstrim_m10.h b/arch/arm/plat-mxc/include/mach/board-imx27_visstrim_m10.h
> new file mode 100644
> index 0000000..9ef1531
> --- /dev/null
> +++ b/arch/arm/plat-mxc/include/mach/board-imx27_visstrim_m10.h
> @@ -0,0 +1,24 @@
> +/*
> + * Copyright (C) 2009 Javier Martin - javier.martin at vista-silicon.com
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301, USA.
This is the correct address :-)

> + */
> +
> +#ifndef __ASM_ARCH_MXC_BOARD_IMX27_VISSTRIM_M10_H__
> +#define __ASM_ARCH_MXC_BOARD_IMX27_VISSTRIM_M10_H__
> +
> +	#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
> +
> +#endif		/* __ASM_ARCH_MXC_BOARD_IMX27_VISSTRIM_M10_H__ */

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From kirill at shutemov.name  Wed Jun 30 15:49:42 2010
From: kirill at shutemov.name (Kirill A. Shutemov)
Date: Wed, 30 Jun 2010 22:49:42 +0300
Subject: [PATCH 02/33] Removing dead ARCH_DAVINCI_TNETV107X
In-Reply-To: <20100630170730.GE23534@tarshish>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<88ee583babc6f0aecb2238a57644f64159d5c395.1277911346.git.siccegge@cs.fau.de>
	<20100630170730.GE23534@tarshish>
Message-ID: <20100630194942.GB3969@shutemov.name>

On Wed, Jun 30, 2010 at 08:07:31PM +0300, Baruch Siach wrote:
> Hi Christoph,
> 
> On Wed, Jun 30, 2010 at 06:05:38PM +0200, Christoph Egger wrote:
> > ARCH_DAVINCI_TNETV107X doesn't exist in Kconfig, therefore removing
> > all references for it from the source code.
> > 
> > Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> > ---
> >  arch/arm/mach-davinci/include/mach/cputype.h |    6 ------
> >  1 files changed, 0 insertions(+), 6 deletions(-)
> > 
> > diff --git a/arch/arm/mach-davinci/include/mach/cputype.h b/arch/arm/mach-davinci/include/mach/cputype.h
> > index cea6b89..6143022 100644
> > --- a/arch/arm/mach-davinci/include/mach/cputype.h
> > +++ b/arch/arm/mach-davinci/include/mach/cputype.h
> > @@ -85,10 +85,4 @@ IS_DAVINCI_CPU(tnetv107x, DAVINCI_CPU_ID_TNETV107X)
> >  #define cpu_is_davinci_da850() 0
> >  #endif
> >  
> > -#ifdef CONFIG_ARCH_DAVINCI_TNETV107X
> > -#define cpu_is_davinci_tnetv107x() is_davinci_tnetv107x()
> > -#else
> > -#define cpu_is_davinci_tnetv107x() 0
> 
> Why remove the #else part?

Nobody uses cpu_is_davinci_tnetv107x as well.

Acked-by: Kirill A. Shutemov <kirill at shutemov.name>

-- 
 Kirill A. Shutemov


From kirill at shutemov.name  Wed Jun 30 15:54:09 2010
From: kirill at shutemov.name (Kirill A. Shutemov)
Date: Wed, 30 Jun 2010 22:54:09 +0300
Subject: [PATCH 03/33] Removing dead OMAP_MUX_ERRORS
In-Reply-To: <b6ca168f9459162f2c96aa8ef999047a3c4f6f9c.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<b6ca168f9459162f2c96aa8ef999047a3c4f6f9c.1277911346.git.siccegge@cs.fau.de>
Message-ID: <20100630195409.GC3969@shutemov.name>

On Wed, Jun 30, 2010 at 05:54:42PM +0200, Christoph Egger wrote:
> OMAP_MUX_ERRORS doesn't exist in Kconfig, therefore removing all
> references for it from the source code.

IIUC, CONFIG_OMAP_MUX_WARNINGS should be used here instead of it.

> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> ---
>  arch/arm/mach-omap1/mux.c |    5 -----
>  1 files changed, 0 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
> index 8434137..1ddb02c 100644
> --- a/arch/arm/mach-omap1/mux.c
> +++ b/arch/arm/mach-omap1/mux.c
> @@ -439,12 +439,7 @@ int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
>  			       cfg->pull_name, cfg->pull_reg, pull_orig, pull);
>  	}
>  #endif
> -
> -#ifdef CONFIG_OMAP_MUX_ERRORS
> -	return warn ? -ETXTBSY : 0;
> -#else
>  	return 0;
> -#endif
>  }
>  
>  int __init omap1_mux_init(void)
> -- 
> 1.7.0.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
 Kirill A. Shutemov


From kirill at shutemov.name  Wed Jun 30 15:59:33 2010
From: kirill at shutemov.name (Kirill A. Shutemov)
Date: Wed, 30 Jun 2010 22:59:33 +0300
Subject: [PATCH 04/33] Removing dead MSM7X00A_IDLE
In-Reply-To: <c7e75d44aebaaabfdff9cf5fbda54512d0062728.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<c7e75d44aebaaabfdff9cf5fbda54512d0062728.1277911346.git.siccegge@cs.fau.de>
Message-ID: <20100630195933.GD3969@shutemov.name>

On Wed, Jun 30, 2010 at 05:55:03PM +0200, Christoph Egger wrote:
> MSM7X00A_IDLE doesn't exist in Kconfig, therefore removing all
> references for it from the source code.

It was removed in commit 1637de0c9. I'm not sure if it's correct.

Brian Swetland added to CC list.

> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> ---
>  arch/arm/mach-msm/idle.S |   13 -------------
>  1 files changed, 0 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/mach-msm/idle.S b/arch/arm/mach-msm/idle.S
> index 6a94f05..d8e8027 100644
> --- a/arch/arm/mach-msm/idle.S
> +++ b/arch/arm/mach-msm/idle.S
> @@ -20,17 +20,4 @@
>  #include <asm/assembler.h>
>  
>  ENTRY(arch_idle)
> -#ifdef CONFIG_MSM7X00A_IDLE
> -	mrc     p15, 0, r1, c1, c0, 0    /* read current CR    */
> -	bic     r0, r1, #(1 << 2)        /* clear dcache bit   */
> -	bic     r0, r0, #(1 << 12)       /* clear icache bit   */
> -	mcr     p15, 0, r0, c1, c0, 0    /* disable d/i cache  */
> -
> -	mov     r0, #0                   /* prepare wfi value  */
> -	mcr     p15, 0, r0, c7, c10, 0   /* flush the cache    */
> -	mcr     p15, 0, r0, c7, c10, 4   /* memory barrier     */
> -	mcr     p15, 0, r0, c7, c0, 4    /* wait for interrupt */
> -
> -	mcr     p15, 0, r1, c1, c0, 0    /* restore d/i cache  */
> -#endif
>  	mov     pc, lr
> -- 
> 1.7.0.4
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
 Kirill A. Shutemov


From dwalker at codeaurora.org  Wed Jun 30 16:03:31 2010
From: dwalker at codeaurora.org (Daniel Walker)
Date: Wed, 30 Jun 2010 13:03:31 -0700
Subject: [PATCH 04/33] Removing dead MSM7X00A_IDLE
In-Reply-To: <20100630195933.GD3969@shutemov.name>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<c7e75d44aebaaabfdff9cf5fbda54512d0062728.1277911346.git.siccegge@cs.fau.de>
	<20100630195933.GD3969@shutemov.name>
Message-ID: <1277928211.30401.39.camel@c-dwalke-linux.qualcomm.com>

On Wed, 2010-06-30 at 22:59 +0300, Kirill A. Shutemov wrote:
> On Wed, Jun 30, 2010 at 05:55:03PM +0200, Christoph Egger wrote:
> > MSM7X00A_IDLE doesn't exist in Kconfig, therefore removing all
> > references for it from the source code.
> 
> It was removed in commit 1637de0c9. I'm not sure if it's correct.
> 
> Brian Swetland added to CC list.

Yeah, it looks like it was missed in the original commit.

Daniel

-- 
Sent by a consultant of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.



From khilman at deeprootsystems.com  Wed Jun 30 16:36:16 2010
From: khilman at deeprootsystems.com (Kevin Hilman)
Date: Wed, 30 Jun 2010 13:36:16 -0700
Subject: [PATCH 02/33] Removing dead ARCH_DAVINCI_TNETV107X
In-Reply-To: <88ee583babc6f0aecb2238a57644f64159d5c395.1277911346.git.siccegge@cs.fau.de>
	(Christoph Egger's message of "Wed, 30 Jun 2010 18:05:38 +0200")
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<88ee583babc6f0aecb2238a57644f64159d5c395.1277911346.git.siccegge@cs.fau.de>
Message-ID: <87vd90jm0v.fsf@deeprootsystems.com>

Christoph Egger <siccegge at cs.fau.de> writes:

> ARCH_DAVINCI_TNETV107X doesn't exist in Kconfig, therefore removing
> all references for it from the source code.
>
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>

Please leave this define in.

The full support for this platform is currently in linux-next and will
be merged for 2.6.36.

Kevin


From ryan at bluewatersys.com  Wed Jun 30 17:02:05 2010
From: ryan at bluewatersys.com (Ryan Mallon)
Date: Thu, 01 Jul 2010 09:02:05 +1200
Subject: [PATCH 2/3] at91_udc: Add vbus polarity and polling mode
In-Reply-To: <1277699955-9931-3-git-send-email-ryan@bluewatersys.com>
References: <1277699955-9931-1-git-send-email-ryan@bluewatersys.com>
	<1277699955-9931-3-git-send-email-ryan@bluewatersys.com>
Message-ID: <4C2BB0CD.3020700@bluewatersys.com>

On 06/28/2010 04:39 PM, Ryan Mallon wrote:
> Allow the vbus signal to optionally use polling. This is required if
> the vbus signal is connected to an non-interrupting io expander for
> example. If vbus is in polling mode, then it is assumed that the vbus
> gpio may sleep. Also add an option to have vbus be an active low
> signal. Both options are set in the platform data for the device.
> 
> Signed-off-by: Ryan Mallon <ryan at bluewatersys.com>

Is anybody able to review this patch please? I have an ack for a patch
which depends on this one. This patch should have no impact (other than
slight code/data size increase) on existing users of the at91 udc driver
since it only adds an alternative code path for the case where vbus is
on a gpio which may sleep. The addition of the vbus polarity should also
not affect existing users since the default is active high.

Thanks,
~Ryan

> ---
>  arch/arm/mach-at91/include/mach/board.h |    2 +
>  drivers/usb/gadget/at91_udc.c           |   66 +++++++++++++++++++++++++------
>  drivers/usb/gadget/at91_udc.h           |    2 +
>  3 files changed, 57 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
> index df2ed84..58528aa 100644
> --- a/arch/arm/mach-at91/include/mach/board.h
> +++ b/arch/arm/mach-at91/include/mach/board.h
> @@ -44,6 +44,8 @@
>   /* USB Device */
>  struct at91_udc_data {
>  	u8	vbus_pin;		/* high == host powering us */
> +	u8	vbus_active_low;	/* vbus polarity */
> +	u8	vbus_polled;		/* Use polling, not interrupt */
>  	u8	pullup_pin;		/* active == D+ pulled up */
>  	u8	pullup_active_low;	/* true == pullup_pin is active low */
>  };
> diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
> index eaa79c8..469a64c 100644
> --- a/drivers/usb/gadget/at91_udc.c
> +++ b/drivers/usb/gadget/at91_udc.c
> @@ -76,6 +76,7 @@
>  static const char driver_name [] = "at91_udc";
>  static const char ep0name[] = "ep0";
>  
> +#define VBUS_POLL_TIMEOUT	msecs_to_jiffies(1000)
>  
>  #define at91_udp_read(dev, reg) \
>  	__raw_readl((dev)->udp_baseaddr + (reg))
> @@ -1556,20 +1557,49 @@ static struct at91_udc controller = {
>  	/* ep6 and ep7 are also reserved (custom silicon might use them) */
>  };
>  
> +static void at91_vbus_update(struct at91_udc *udc, unsigned value)
> +{
> +	if (udc->board.vbus_active_low)
> +		value ^= 1;
> +	if (value != udc->vbus)
> +		at91_vbus_session(&udc->gadget, value);
> +}
> +
>  static irqreturn_t at91_vbus_irq(int irq, void *_udc)
>  {
>  	struct at91_udc	*udc = _udc;
> -	unsigned	value;
>  
>  	/* vbus needs at least brief debouncing */
>  	udelay(10);
> -	value = gpio_get_value(udc->board.vbus_pin);
> -	if (value != udc->vbus)
> -		at91_vbus_session(&udc->gadget, value);
> +	at91_vbus_update(udc, gpio_get_value(udc->board.vbus_pin));
>  
>  	return IRQ_HANDLED;
>  }
>  
> +static void at91_vbus_timer_work(struct work_struct *work)
> +{
> +	struct at91_udc *udc = container_of(work, struct at91_udc, 
> +					    vbus_timer_work);
> +
> +	at91_vbus_update(udc, gpio_get_value_cansleep(udc->board.vbus_pin));
> +
> +	if (!timer_pending(&udc->vbus_timer))
> +		mod_timer(&udc->vbus_timer, jiffies + VBUS_POLL_TIMEOUT);
> +}
> +
> +static void at91_vbus_timer(unsigned long data)
> +{
> +	struct at91_udc *udc = (struct at91_udc *)data;
> +
> +	/*
> +	 * If we are polling vbus it is likely that the gpio is on an
> +	 * bus such as i2c or spi which may sleep, so schedule some work
> +	 * to read the vbus gpio
> +	 */
> +	if (!work_pending(&udc->vbus_timer_work))
> +		schedule_work(&udc->vbus_timer_work);
> +}
> +
>  int usb_gadget_register_driver (struct usb_gadget_driver *driver)
>  {
>  	struct at91_udc	*udc = &controller;
> @@ -1763,13 +1793,22 @@ static int __init at91udc_probe(struct platform_device *pdev)
>  		 * Get the initial state of VBUS - we cannot expect
>  		 * a pending interrupt.
>  		 */
> -		udc->vbus = gpio_get_value(udc->board.vbus_pin);
> -		if (request_irq(udc->board.vbus_pin, at91_vbus_irq,
> -				IRQF_DISABLED, driver_name, udc)) {
> -			DBG("request vbus irq %d failed\n",
> -					udc->board.vbus_pin);
> -			retval = -EBUSY;
> -			goto fail3;
> +		if (udc->board.vbus_polled) {
> +			udc->vbus = gpio_get_value_cansleep(udc->board.vbus_pin);
> +			INIT_WORK(&udc->vbus_timer_work, at91_vbus_timer_work);
> +			setup_timer(&udc->vbus_timer, at91_vbus_timer,
> +				    (unsigned long)udc);		
> +			mod_timer(&udc->vbus_timer,
> +				  jiffies + VBUS_POLL_TIMEOUT);
> +		} else {
> +			udc->vbus = gpio_get_value(udc->board.vbus_pin);
> +			if (request_irq(udc->board.vbus_pin, at91_vbus_irq,
> +					IRQF_DISABLED, driver_name, udc)) {
> +				DBG("request vbus irq %d failed\n",
> +				    udc->board.vbus_pin);
> +				retval = -EBUSY;
> +				goto fail3;
> +			}
>  		}
>  	} else {
>  		DBG("no VBUS detection, assuming always-on\n");
> @@ -1855,7 +1894,7 @@ static int at91udc_suspend(struct platform_device *pdev, pm_message_t mesg)
>  		enable_irq_wake(udc->udp_irq);
>  
>  	udc->active_suspend = wake;
> -	if (udc->board.vbus_pin > 0 && wake)
> +	if (udc->board.vbus_pin > 0 && !udc->board.vbus_polled && wake)
>  		enable_irq_wake(udc->board.vbus_pin);
>  	return 0;
>  }
> @@ -1864,7 +1903,8 @@ static int at91udc_resume(struct platform_device *pdev)
>  {
>  	struct at91_udc *udc = platform_get_drvdata(pdev);
>  
> -	if (udc->board.vbus_pin > 0 && udc->active_suspend)
> +	if (udc->board.vbus_pin > 0 && !udc->board.vbus_polled && 
> +	    udc->active_suspend)
>  		disable_irq_wake(udc->board.vbus_pin);
>  
>  	/* maybe reconnect to host; if so, clocks on */
> diff --git a/drivers/usb/gadget/at91_udc.h b/drivers/usb/gadget/at91_udc.h
> index c65d622..a1f4f54 100644
> --- a/drivers/usb/gadget/at91_udc.h
> +++ b/drivers/usb/gadget/at91_udc.h
> @@ -144,6 +144,8 @@ struct at91_udc {
>  	struct proc_dir_entry		*pde;
>  	void __iomem			*udp_baseaddr;
>  	int				udp_irq;
> +	struct timer_list		vbus_timer;
> +	struct work_struct		vbus_timer_work;
>  };
>  
>  static inline struct at91_udc *to_udc(struct usb_gadget *g)


-- 
Bluewater Systems Ltd - ARM Technology Solution Centre

Ryan Mallon         		5 Amuri Park, 404 Barbadoes St
ryan at bluewatersys.com         	PO Box 13 889, Christchurch 8013
http://www.bluewatersys.com	New Zealand
Phone: +64 3 3779127		Freecall: Australia 1800 148 751
Fax:   +64 3 3779135			  USA 1800 261 2934


From cbouatmailru at gmail.com  Wed Jun 30 17:11:31 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Thu, 1 Jul 2010 01:11:31 +0400
Subject: [GIT PULL v2] Some Cavium CNS3xxx updates for 2.6.36
In-Reply-To: <20100608170030.GA26992@oksana.dev.rtsoft.ru>
References: <20100608170030.GA26992@oksana.dev.rtsoft.ru>
Message-ID: <20100630211131.GA29737@oksana.dev.rtsoft.ru>

Hello Russell,

On Tue, Jun 08, 2010 at 09:00:30PM +0400, Anton Vorontsov wrote:
> The main reason for the v2 is, obviously, the defconfigs situation.
> I dropped the defconfig update in this pull request.
> 
> There are also few improvements as suggested by by Ben Dooks and
> Sergei Shtylyov, plus there is no longer the ugly
> "../../../drivers/mmc/host/sdhci.h" include anymore.
> 
> As usual, I'm posting the updated patches as well.
> 
> The following changes since commit 9dda696f0de87a2e5cfabb147e28c76b7d3c6846:
>   Linus Torvalds (1):
>         Merge branch 'release' of git://git.kernel.org/.../aegl/linux-2.6
> 
> are available in the git repository at:
> 
>   git://git.infradead.org/users/cbou/linux-cns3xxx.git master

I noticed that you pulled some other trees, but not this one.
Is there any particular reason, or it's in the queue?

Thanks,

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2


From cbouatmailru at gmail.com  Wed Jun 30 17:16:35 2010
From: cbouatmailru at gmail.com (Anton Vorontsov)
Date: Thu, 1 Jul 2010 01:16:35 +0400
Subject: [PATCH v2 3/3] ARM: cns3xxx: Add support for SMP
In-Reply-To: <20100618203702.GC9155@oksana.dev.rtsoft.ru>
References: <20100618181707.GA21578@n2100.arm.linux.org.uk>
	<20100618203702.GC9155@oksana.dev.rtsoft.ru>
Message-ID: <20100630211635.GB29737@oksana.dev.rtsoft.ru>

On Sat, Jun 19, 2010 at 12:37:02AM +0400, Anton Vorontsov wrote:
> Thanks to the previous refactorings, nothing fancy needs to be
> done, just use generic SCU routines.
> 
> Signed-off-by: Anton Vorontsov <avorontsov at mvista.com>
> ---
[...]
> @@ -3,6 +3,7 @@ menu "CNS3XXX platform type"
>  
>  config MACH_CNS3420VB
>  	bool "Support for CNS3420 Validation Board"
> +	select HAVE_ARM_SCU

This should be 'select HAVE_ARM_SCU if SMP', otherwise non-SMP build
fails.

Apart from this, Russell, do these patches look OK?

-- 
Anton Vorontsov
email: cbouatmailru at gmail.com
irc://irc.freenode.net/bd2


From linus.ml.walleij at gmail.com  Wed Jun 30 17:32:09 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Wed, 30 Jun 2010 23:32:09 +0200
Subject: [PATCH] ARM: RealView: Do not use outer_sync() on certain with 
	L210/L220
In-Reply-To: <1277888217.13942.0.camel@e102109-lin.cambridge.arm.com>
References: <20100629093135.10365.99959.stgit@e102109-lin.cambridge.arm.com>
	<AANLkTinpAz52QfsnvzIY5fleJoflVr0Z40JpRNrlXY9k@mail.gmail.com>
	<1277888217.13942.0.camel@e102109-lin.cambridge.arm.com>
Message-ID: <AANLkTimyCm7K-3clFnxl1BirvozucaDrj4Abl3899jtN@mail.gmail.com>

2010/6/30 Catalin Marinas <catalin.marinas at arm.com>:

> On Wed, 2010-06-30 at 09:13 +0100, Linus Walleij wrote:
>> 2010/6/29 Catalin Marinas <catalin.marinas at arm.com>:
>>
>> > RealView boards with certain revisions of the L210/L220 cache controller
>> > may have issues (hardware deadlock) with the recent changes to the mb()
>> > barrier implementation (DSB followed by an L2 cache sync). The patch
>> > disables ARM_DMA_MEM_BUFFERABLE for the RealView boards with L210/L220
>> > and redefines the mandatory barriers without the outer_sync() call.
>> >
>> > Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
>> > Cc: Linus Walleij <linus.ml.walleij at gmail.com>
>>
>> Works like a charm on the PB1176!
>>
>> Tested-by: Linus Walleij <linus.walleij at stericsson.com>
>
> Thanks for testing. Just to be sure - was this with the CACHE_L2X0
> enabled in your configuration?

Yep it was!

Yours,
Linus Walleij


From linus.ml.walleij at gmail.com  Wed Jun 30 17:58:42 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Wed, 30 Jun 2010 23:58:42 +0200
Subject: [PATCH 0/2] RealView barriers and ARM_DMA_MEM_BUFFERABLE
In-Reply-To: <20100630104105.16712.66741.stgit@e102109-lin.cambridge.arm.com>
References: <20100630104105.16712.66741.stgit@e102109-lin.cambridge.arm.com>
Message-ID: <AANLkTikBTz8qqohhcfhSWW9cO384pientK2tXPtKuYVv@mail.gmail.com>

2010/6/30 Catalin Marinas <catalin.marinas at arm.com>:

> Linus, could you please confirm that the second patch still fixes the
> PB1176 issues for you?

It does, the system comes up, prints:
L2x0 series cache controller enabled
l2x0: 8 ways, CACHE_ID 0x41000486, AUX_CTRL 0x02730fff

No hangs whatsoever.
Tested-by: Linus Walleij <linus.walleij at stericsson.com>

Please queue this up for the -rc series...

Yours,
Linus Walleij


From linus.walleij at stericsson.com  Wed Jun 30 18:00:59 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Thu, 1 Jul 2010 00:00:59 +0200
Subject: [PATCH 31/33] Removing dead MACH_U300_BS26
In-Reply-To: <2a81bf5506ce15ac839ca4fa58dc8af4112ff531.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<2a81bf5506ce15ac839ca4fa58dc8af4112ff531.1277911346.git.siccegge@cs.fau.de>
Message-ID: <AANLkTikyk4fu72kWFfxQyEV_GHTc5flLYytF9cnHDBE_@mail.gmail.com>

2010/6/30 Christoph Egger <siccegge at cs.fau.de>:

> MACH_U300_BS26 doesn't exist in Kconfig, therefore removing all
> references for it from the source code.
>
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>

OK then,
Acked-by: Linus Walleij <linus.walleij at stericsson.com>

Yours,
Linus Walleij


From linus.ml.walleij at gmail.com  Wed Jun 30 18:03:29 2010
From: linus.ml.walleij at gmail.com (Linus Walleij)
Date: Thu, 1 Jul 2010 00:03:29 +0200
Subject: [PATCH 33/33] Removing dead MACH_U300_USE_I2S_AS_MASTER
In-Reply-To: <41be9a8afe8951b4ad23d43fcb57aca9a662cf43.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<41be9a8afe8951b4ad23d43fcb57aca9a662cf43.1277911346.git.siccegge@cs.fau.de>
Message-ID: <AANLkTinHA5PsD_5i-YgRNSNzddsqc1JojDN5AvC9ot8C@mail.gmail.com>

2010/6/30 Christoph Egger <siccegge at cs.fau.de>:

> MACH_U300_USE_I2S_AS_MASTER doesn't exist in Kconfig, therefore
> removing all references for it from the source code.
>
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>

I remember the pain of writing that code, but until I get around to merge that
ancient driver I see no point in keeping it around, so:
Acked-by: Linus Walleij <linus.walleij at stericsson.com>

Yours,
Linus Walleij


From linus.walleij at stericsson.com  Wed Jun 30 17:34:46 2010
From: linus.walleij at stericsson.com (Linus Walleij)
Date: Wed, 30 Jun 2010 23:34:46 +0200
Subject: [PATCH] ARM: Fixups for the RealView PB1176
Message-ID: <1277933686-17415-1-git-send-email-linus.walleij@stericsson.com>

This is a number of basic fixes to the PB1176 that makes it tick
properly:

- Detect MMC insertion/removal even when PL061 GPIO is not compiled
  in. The register to read this status directly is removed on the
  PB1176.
- Define the UART3 on the DevChip (where is actually is) and define
  the new UART4 serial port on the FPGA.
- Also define the clocks for these two UARTs apropriately.
- Remove the false notion that the PB1176 should have its CLCD
  on the ISSP, this is not the case, it is in the DevChip.
- Remove the defintions and the previously commented-out PL081
  DMAC. As confirmed by mail this was found to be broken on the
  PB1176 board and removed from the subsequent FPGA images.

Signed-off-by: Linus Walleij <linus.walleij at stericsson.com>
---
 arch/arm/mach-realview/core.c                      |   23 +++++++++++++++++++-
 arch/arm/mach-realview/include/mach/board-pb1176.h |    1 +
 arch/arm/mach-realview/realview_pb1176.c           |   14 +++++-------
 3 files changed, 29 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 1195e07..4b3d2fd 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -231,6 +231,21 @@ static unsigned int realview_mmc_status(struct device *dev)
 	struct amba_device *adev = container_of(dev, struct amba_device, dev);
 	u32 mask;
 
+	if (machine_is_realview_pb1176()) {
+		static bool inserted = false;
+
+		/*
+		 * The PB1176 does not have the status register,
+		 * assume it is inserted at startup, then invert
+		 * for each call so card insertion/removal will
+		 * be detected anyway. This will not be called if
+		 * GPIO on PL061 is active, which is the proper
+		 * way to do this on the PB1176.
+		 */
+		inserted = !inserted;
+		return inserted ? 0 : 1;
+	}
+
 	if (adev->res.start == REALVIEW_MMCI0_BASE)
 		mask = 1;
 	else
@@ -312,6 +327,12 @@ static struct clk_lookup lookups[] = {
 	}, {	/* UART3 */
 		.dev_id		= "fpga:uart3",
 		.clk		= &ref24_clk,
+	}, {	/* UART3 is on the dev chip in PB1176 */
+		.dev_id		= "dev:uart3",
+		.clk		= &ref24_clk,
+	}, {	/* UART4 only exists in PB1176 */
+		.dev_id		= "fpga:uart4",
+		.clk		= &ref24_clk,
 	}, {	/* KMI0 */
 		.dev_id		= "fpga:kmi0",
 		.clk		= &ref24_clk,
@@ -321,7 +342,7 @@ static struct clk_lookup lookups[] = {
 	}, {	/* MMC0 */
 		.dev_id		= "fpga:mmc0",
 		.clk		= &ref24_clk,
-	}, {	/* EB:CLCD */
+	}, {	/* CLCD is in the PB1176 and EB DevChip */
 		.dev_id		= "dev:clcd",
 		.clk		= &oscvco_clk,
 	}, {	/* PB:CLCD */
diff --git a/arch/arm/mach-realview/include/mach/board-pb1176.h b/arch/arm/mach-realview/include/mach/board-pb1176.h
index 2f5ccb2..002ab5d 100644
--- a/arch/arm/mach-realview/include/mach/board-pb1176.h
+++ b/arch/arm/mach-realview/include/mach/board-pb1176.h
@@ -26,6 +26,7 @@
 /*
  * Peripheral addresses
  */
+#define REALVIEW_PB1176_UART4_BASE		0x10009000 /* UART 4 */
 #define REALVIEW_PB1176_SCTL_BASE		0x10100000 /* System controller */
 #define REALVIEW_PB1176_SMC_BASE		0x10111000 /* SMC */
 #define REALVIEW_PB1176_DMC_BASE		0x10109000 /* DMC configuration */
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 099a1f1..9f02350 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -144,8 +144,6 @@ static struct pl061_platform_data gpio2_plat_data = {
 #define MPMC_DMA	{ 0, 0 }
 #define PB1176_CLCD_IRQ	{ IRQ_DC1176_CLCD, NO_IRQ }
 #define PB1176_CLCD_DMA	{ 0, 0 }
-#define DMAC_IRQ	{ IRQ_PB1176_DMAC, NO_IRQ }
-#define DMAC_DMA	{ 0, 0 }
 #define SCTL_IRQ	{ NO_IRQ, NO_IRQ }
 #define SCTL_DMA	{ 0, 0 }
 #define PB1176_WATCHDOG_IRQ	{ IRQ_DC1176_WATCHDOG, NO_IRQ }
@@ -166,6 +164,8 @@ static struct pl061_platform_data gpio2_plat_data = {
 #define PB1176_UART2_DMA	{ 11, 10 }
 #define PB1176_UART3_IRQ	{ IRQ_DC1176_UART3, NO_IRQ }
 #define PB1176_UART3_DMA	{ 0x86, 0x87 }
+#define PB1176_UART4_IRQ	{ IRQ_PB1176_UART4, NO_IRQ }
+#define PB1176_UART4_DMA	{ 0, 0 }
 #define PB1176_SSP_IRQ		{ IRQ_PB1176_SSP, NO_IRQ }
 #define PB1176_SSP_DMA		{ 9, 8 }
 
@@ -174,7 +174,7 @@ AMBA_DEVICE(aaci,	"fpga:aaci",	AACI,		NULL);
 AMBA_DEVICE(mmc0,	"fpga:mmc0",	MMCI0,		&realview_mmc0_plat_data);
 AMBA_DEVICE(kmi0,	"fpga:kmi0",	KMI0,		NULL);
 AMBA_DEVICE(kmi1,	"fpga:kmi1",	KMI1,		NULL);
-AMBA_DEVICE(uart3,	"fpga:uart3",	PB1176_UART3,	NULL);
+AMBA_DEVICE(uart4,	"fpga:uart4",	PB1176_UART4,	NULL);
 
 /* DevChip Primecells */
 AMBA_DEVICE(smc,	"dev:smc",	PB1176_SMC,	NULL);
@@ -188,18 +188,16 @@ AMBA_DEVICE(sci0,	"dev:sci0",	SCI,		NULL);
 AMBA_DEVICE(uart0,	"dev:uart0",	PB1176_UART0,	NULL);
 AMBA_DEVICE(uart1,	"dev:uart1",	PB1176_UART1,	NULL);
 AMBA_DEVICE(uart2,	"dev:uart2",	PB1176_UART2,	NULL);
+AMBA_DEVICE(uart3,	"dev:uart3",	PB1176_UART3,	NULL);
 AMBA_DEVICE(ssp0,	"dev:ssp0",	PB1176_SSP,	NULL);
-
-/* Primecells on the NEC ISSP chip */
-AMBA_DEVICE(clcd,	"issp:clcd",	PB1176_CLCD,	&clcd_plat_data);
-//AMBA_DEVICE(dmac,	"issp:dmac",	PB1176_DMAC,	NULL);
+AMBA_DEVICE(clcd,	"dev:clcd",	PB1176_CLCD,	&clcd_plat_data);
 
 static struct amba_device *amba_devs[] __initdata = {
-//	&dmac_device,
 	&uart0_device,
 	&uart1_device,
 	&uart2_device,
 	&uart3_device,
+	&uart4_device,
 	&smc_device,
 	&clcd_device,
 	&sctl_device,
-- 
1.7.0.1



From grant.likely at secretlab.ca  Wed Jun 30 19:03:22 2010
From: grant.likely at secretlab.ca (Grant Likely)
Date: Wed, 30 Jun 2010 17:03:22 -0600
Subject: [PATCH] spi: davinci: Added support for chip select using gpio
In-Reply-To: <1277707655-3468-1-git-send-email-lamiaposta71@gmail.com>
References: <1277707655-3468-1-git-send-email-lamiaposta71@gmail.com>
Message-ID: <AANLkTilnVxNfsfJ4nCWITM_DhOb6BDGZQC8cMiM0RkiF@mail.gmail.com>

On Mon, Jun 28, 2010 at 12:47 AM, Raffaele Recalcati
<lamiaposta71 at gmail.com> wrote:
> From: Raffaele Recalcati <raffaele.recalcati at bticino.it>
>
> ? ?It is not everytime possible, due to hardware constraints,
> ? ?to use the hw chip select available on spi port.
> ? ?So I add this possibility using a gpio as chip select.
> ? ?If controller_data variable is not null it is
> ? ?the gpio to be used as chip select.
> ? ?The default case is compatible with evmdm365.
> ? ?This patch has been developed against the
> ? ?http://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-davinci.git
> ? ?git tree and has been tested on bmx board (similar to dm365 evm but with
> ? ?gpio as spi chip select).
>
> Signed-off-by: Raffaele Recalcati <raffaele.recalcati at bticino.it>
> Signed-off-by: Davide Bonfanti <davide.bonfanti at bticino.it>

The davinci SPI driver is getting completely replaced (as soon as I
receive the respun patches), and I assume this patch will no longer
apply after the fact, so I'm not going to pick this patch up.  You
should coordinate with Brian Niebuhr to get this feature into his new
driver.

Cheers,
g.

> ---
> ?arch/arm/mach-davinci/dm365.c | ? 10 ++++++----
> ?drivers/spi/davinci_spi.c ? ? | ? 27 ++++++++++++++++++---------
> ?2 files changed, 24 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
> index a146849..42fd4a4 100644
> --- a/arch/arm/mach-davinci/dm365.c
> +++ b/arch/arm/mach-davinci/dm365.c
> @@ -677,10 +677,12 @@ void __init dm365_init_spi0(unsigned chipselect_mask,
> ? ? ? ?davinci_cfg_reg(DM365_SPI0_SDO);
>
> ? ? ? ?/* not all slaves will be wired up */
> - ? ? ? if (chipselect_mask & BIT(0))
> - ? ? ? ? ? ? ? davinci_cfg_reg(DM365_SPI0_SDENA0);
> - ? ? ? if (chipselect_mask & BIT(1))
> - ? ? ? ? ? ? ? davinci_cfg_reg(DM365_SPI0_SDENA1);
> + ? ? ? if ?(!((unsigned long) info->controller_data)) {
> + ? ? ? ? ? ? ? if (chipselect_mask & BIT(0))
> + ? ? ? ? ? ? ? ? ? ? ? davinci_cfg_reg(DM365_SPI0_SDENA0);
> + ? ? ? ? ? ? ? if (chipselect_mask & BIT(1))
> + ? ? ? ? ? ? ? ? ? ? ? davinci_cfg_reg(DM365_SPI0_SDENA1);
> + ? ? ? }
>
> ? ? ? ?spi_register_board_info(info, len);
>
> diff --git a/drivers/spi/davinci_spi.c b/drivers/spi/davinci_spi.c
> index 95afb6b..621ae46 100644
> --- a/drivers/spi/davinci_spi.c
> +++ b/drivers/spi/davinci_spi.c
> @@ -29,6 +29,7 @@
> ?#include <linux/spi/spi_bitbang.h>
> ?#include <linux/slab.h>
>
> +#include <mach/gpio.h>
> ?#include <mach/spi.h>
> ?#include <mach/edma.h>
>
> @@ -270,18 +271,26 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
> ? ? ? ?pdata = davinci_spi->pdata;
>
> ? ? ? ?/*
> - ? ? ? ?* Board specific chip select logic decides the polarity and cs
> - ? ? ? ?* line for the controller
> - ? ? ? ?*/
> + ? ? ? * Board specific chip select logic decides the polarity and cs
> + ? ? ? * line for the controller
> + ? ? ? */
> ? ? ? ?if (value == BITBANG_CS_INACTIVE) {
> - ? ? ? ? ? ? ? set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);
> -
> - ? ? ? ? ? ? ? data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
> - ? ? ? ? ? ? ? iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
> -
> + ? ? ? ? ? ? ? if ?((unsigned long) spi->controller_data) {
> + ? ? ? ? ? ? ? ? ? ? ? gpio_set_value(spi->controller_data, \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? !(spi->mode & SPI_CS_HIGH));
> + ? ? ? ? ? ? ? } else {
> + ? ? ? ? ? ? ? ? ? ? ? set_io_bits(davinci_spi->base + SPIDEF, CS_DEFAULT);
> +
> + ? ? ? ? ? ? ? ? ? ? ? data1_reg_val |= CS_DEFAULT << SPIDAT1_CSNR_SHIFT;
> + ? ? ? ? ? ? ? ? ? ? ? iowrite32(data1_reg_val, davinci_spi->base + SPIDAT1);
> + ? ? ? ? ? ? ? }
> ? ? ? ? ? ? ? ?while ((ioread32(davinci_spi->base + SPIBUF)
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIBUF_RXEMPTY_MASK) == 0)
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? & SPIBUF_RXEMPTY_MASK) == 0)
> ? ? ? ? ? ? ? ? ? ? ? ?cpu_relax();
> + ? ? ? } else {
> + ? ? ? ? ? ? ? if ?((unsigned long) spi->controller_data)
> + ? ? ? ? ? ? ? ? ? ? ? gpio_set_value(spi->controller_data, \
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (spi->mode & SPI_CS_HIGH));
> ? ? ? ?}
> ?}
>
> --
> 1.7.0.4
>
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.


From randy.dunlap at Oracle.COM  Wed Jun 30 19:40:58 2010
From: randy.dunlap at Oracle.COM (Randy Dunlap)
Date: Wed, 30 Jun 2010 16:40:58 -0700
Subject: [RFC 1/3] mm: iommu: An API to unify IOMMU, CPU and device
	memory management
In-Reply-To: <1277877350-2147-1-git-send-email-zpfeffer@codeaurora.org>
References: <1277877350-2147-1-git-send-email-zpfeffer@codeaurora.org>
Message-ID: <20100630164058.aa6aa3a2.randy.dunlap@oracle.com>

On Tue, 29 Jun 2010 22:55:48 -0700 Zach Pfeffer wrote:

> This patch contains the documentation for the API, termed the Virtual
> Contiguous Memory Manager. Its use would allow all of the IOMMU to VM,
> VM to device and device to IOMMU interoperation code to be refactored
> into platform independent code.
> 
> Comments, suggestions and criticisms are welcome and wanted.
> 
> Signed-off-by: Zach Pfeffer <zpfeffer at codeaurora.org>
> ---
>  Documentation/vcm.txt |  583 +++++++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 583 insertions(+), 0 deletions(-)
>  create mode 100644 Documentation/vcm.txt
> 
> diff --git a/Documentation/vcm.txt b/Documentation/vcm.txt
> new file mode 100644
> index 0000000..d29c757
> --- /dev/null
> +++ b/Documentation/vcm.txt
> @@ -0,0 +1,583 @@
> +What is this document about?
> +============================
> +
> +This document covers how to use the Virtual Contiguous Memory Manager
> +(VCMM), how the first implmentation works with a specific low-level
> +Input/Output Memory Management Unit (IOMMU) and the way the VCMM is used
> +from user-space. It also contains a section that describes why something
> +like the VCMM is needed in the kernel.
> +
> +If anything in this document is wrong please send patches to the

                                is wrong,

> +maintainer of this file, listed at the bottom of the document.
> +
> +
> +The Virtual Contiguous Memory Manager
> +=====================================
> +
> +The VCMM was built to solve the system-wide memory mapping issues that
> +occur when many bus-masters have IOMMUs.
> +
> +An IOMMU maps device addresses to physical addresses. It also insulates
> +the system from spurious or malicious device bus transactions and allows
> +fine-grained mapping attribute control. The Linux kernel core does not
> +contain a generic API to handle IOMMU mapped memory; device driver writers
> +must implement device specific code to interoperate with the Linux kernel
> +core. As the number of IOMMUs increases, coordinating the many address
> +spaces mapped by all discrete IOMMUs becomes difficult without in-kernel
> +support.
> +
> +The VCMM API enables device independent IOMMU control, virtual memory
> +manager (VMM) interoperation and non-IOMMU enabled device interoperation
> +by treating devices with or without IOMMUs and all CPUs with or without
> +MMUs, their mapping contexts and their mappings using common
> +abstractions. Physical hardware is given a generic device type and mapping
> +contexts are abstracted into Virtual Contiguous Memory (VCM)
> +regions. Users "reserve" memory from VCMs and "back" their reservations
> +with physical memory.
> +
> +Why the VCMM is Needed
> +----------------------
> +
> +Driver writers who control devices with IOMMUs must contend with device
> +control and memory management. Driver writers have a large device driver
> +API that they can leverage to control their devices, but they are lacking
> +a unified API to help them program mappings into IOMMUs and share those
> +mappings with other devices and CPUs in the system.
> +
> +Sharing is complicated by Linux's CPU centric VMM. The CPU centric model

                                     CPU-centric          CPU-centric

> +generally makes sense because average hardware only contains a MMU for the
> +CPU and possibly a graphics MMU. If every device in the system has one or
> +more MMUs the CPU centric memory management (MM) programming model breaks

                 ditto

> +down.
> +
> +Abstracting IOMMU device programming into a common API has already begun
> +in the Linux kernel. It was built to abstract the difference between AMDs

                                                                        AMD's
(or just "AMD")

> +and Intels IOMMUs to support x86 virtualization on both platforms. The

       Intel's (or just "Intel")

> +interface is listed in kernel/include/linux/iommu.h. It contains

                          drop "kernel/"

> +interfaces for mapping and unmapping as well as domain management. This
> +interface has not gained widespread use outside the x86; PA-RISC, Alpha
> +and SPARC architectures and ARM and PowerPC platforms all use their own
> +mapping modules to control their IOMMUs. The VCMM contains an IOMMU
> +programming layer, but since its abstraction supports map management
> +independent of device control, the layer is not used directly. This
> +higher-level view enables a new kernel service, not just an IOMMU
> +interoperation layer.
> +
> +The General Idea: Map Management using Graphs
> +---------------------------------------------
> +
> +Looking at mapping from a system-wide perspective reveals a general graph
> +problem. The VCMMs API is built to manage the general mapping graph. Each

                VMCC's

> +node that talks to memory, either through an MMU or directly (physically
> +mapped) can be thought of as the device-end of a mapping edge. The other
> +edge is the physical memory (or intermediate virtual space) that is
> +mapped.
> +
> +In the direct mapped case the device is assigned a one-to-one MMU. This

          direct-mapped

> +scheme allows direct mapped devices to participate in general graph
> +management.
> +
> +The CPU nodes can also be brought under the same mapping abstraction with
> +the use of a light overlay on the existing VMM. This light overlay allows
> +VMM managed mappings to interoperate with the common API. The light

   VMM-managed

> +overlay enables this without substantial modifications to the existing
> +VMM.
> +
> +In addition to CPU nodes that are running Linux (and the VMM), remote CPU
> +nodes that may be running other operating systems can be brought into the
> +general abstraction. Routing all memory management requests from a remote
> +node through the central memory management framework enables new features
> +like system-wide memory migration. This feature may only be feasible for
> +large buffers that are managed outside of the fast-path, but having remote
> +allocation in a system enables features that are impossible to build
> +without it.
> +
> +The fundamental objects that support graph-based map management are:
> +
> +1) Virtual Contiguous Memory Regions
> +
> +2) Reservations
> +
> +3) Associated Virtual Contiguous Memory Regions
> +
> +4) Memory Targets
> +
> +5) Physical Memory Allocations
> +
> +Usage Overview
> +--------------
> +
> +In a nut-shell, users allocate Virtual Contiguous Memory Regions and

        nutshell,

> +associate those regions with one or more devices by creating an Associated
> +Virtual Contiguous Memory Region. Users then create Reservations from the
> +Virtual Contiguous Memory Region. At this point no physical memory has
> +been committed to the reservation. To associate physical memory with a
> +reservation a Physical Memory Allocation is created and the Reservation is
> +backed with this allocation.
> +
> +include/linux/vcm.h includes comments documenting each API.
> +
> +Virtual Contiguous Memory Regions
> +---------------------------------
> +
> +A Virtual Contiguous Memory Region (VCM) abstracts the memory space a
> +device sees. The addresses of the region are only used by the devices
> +which are associated with the region. This address space would normally be
> +implemented as a device page-table.

                           page table.

> +
> +A VCM is created and destroyed with three functions:
> +
> +    struct vcm *vcm_create(size_t start_addr, size_t len);

Seems odd to use size_t for start_addr.

> +    struct vcm *vcm_create_from_prebuilt(size_t ext_vcm_id);
> +
> +    int vcm_free(struct vcm *vcm);
> +
> +start_addr is an offset into the address space where allocations will
> +start from. len is the length from start_addr of the VCM. Both functions
> +generate an instance of a VCM.
> +
> +ext_vcm_id is used to pass a request to the VMM to generate a VCM
> +instance. In the current implementation the call simply makes a note that
> +the VCM instance is a VMM VCM instance for other interfaces usage. This
> +muxing is seen throughout the implementation.
> +
> +vcm_create() and vcm_create_from_prebuilt() produce VCM instances for
> +virtually mapped devices (IOMMUs and CPUs). To create a one-to-one mapped
> +VCM users pass the start_addr and len of the physical region. The VCMM

   VCM,

> +matches this and records that the VCM instance is a one-to-one VCM.
> +
> +The newly created VCM instance can be passed to any function that needs to
> +operate on or with a virtual contiguous memory region. Its main attributes
> +are a start_addr and a len as well as an internal setting that allows the
> +implementation to mux between true virtual spaces, one-to-one mapped
> +spaces and VMM managed spaces.
> +
> +The current implementation uses the genalloc library to manage the VCM for
> +IOMMU devices. Return values and more in-depth per-function documentation
> +for these and the ones listed below are in include/linux/vcm.h.
> +
> +Reservations
> +------------
> +
> +A Reservation is a contiguous region allocated from a VCM. There is no
> +physical memory associated with it.
> +
> +A Reservation is created and destroyed with:
> +
> +    struct res *vcm_reserve(struct vcm *vcm, size_t len, uint32_t attr);

s/uint32_t/u32/ ?

> +    int vcm_unreserve(struct res *res);
> +
> +A vcm is a VCM created above. len is the length of the request. It can be
> +up to the length of the VCM region the reservation is being created
> +from. attr are mapping attributes: read, write, execute, user, supervisor,
> +secure, not-cached, write-back/write-allocate, write-back/no
> +write-allocate, write-through. These attrs are appropriate for ARM but can
> +be changed to match to any architecture.
> +
> +The implementation calls gen_pool_alloc() for IOMMU devices,
> +alloc_vm_area() for VMM areas and is a pass through for one-to-one mapped

                                          pass-through

> +areas.
> +
> +Associated Virtual Contiguous Memory Regions and Activation
> +-----------------------------------------------------------
> +
> +An Associated Virtual Contiguous Memory Region (AVCM) is a mapping of a
> +VCM to a device. The mapping can be active or inactive.
> +
> +An AVCM is managed with:
> +
> +struct avcm *vcm_assoc(struct vcm *vcm, size_t dev, uint32_t attr);
> +
> +    int vcm_deassoc(struct avcm *avcm);
> +
> +    int vcm_activate(struct avcm *avcm);
> +
> +    int vcm_deactivate(struct avcm *avcm);
> +
> +A VCM instance is a VCM created above. A dev is an opaque device handle
> +thats passed down to the device driver the VCMM muxes in to handle a
> +request. attr are association attributes: split, use-high or

size_t used for an opaque device handle seems odd.

> +use-low. split controls which transactions hit a high-address page-table
> +and which transactions hit a low-address page-table. For instance, all
> +transactions whose most significant address bit is one would use the
> +high-address page-table, any other transaction would use the low address
> +page-table. This scheme is ARM specific and could be changed in other

                              ARM-specific

> +architectures. One VCM instance can be associated with many devices and
> +many VCM instances can be associated with one device.
> +
> +An AVCM is only a link. To program and deprogram a device with a VCM the
> +user calls vcm_activate() and vcm_deactivate().For IOMMU devices,

                                 vcm_deactivate(). For

> +activating a mapping programs the base address of a page-table into an

                                                       page table

> +IOMMU. For VMM and one-to-one based devices, mappings are active
> +immediately but the API does require an activation call for them for
> +internal reference counting.
> +
> +Memory Targets
> +--------------
> +
> +A Memory Target is a platform independent way of specifying a physical
> +pool; it abstracts a pool of physical memory. The physical memory pool may
> +be physically discontiguous, need to be allocated from in a unique way or
> +have other user-defined attributes.
> +
> +Physical Memory Allocation and Reservation Backing
> +--------------------------------------------------
> +
> +Physical memory is allocated as a separate step from reserving
> +memory. This allows multiple reservations to back the same physical
> +memory.
> +
> +A Physical Memory Allocation is managed using the following functions:
> +
> +    struct physmem *vcm_phys_alloc(enum memtype_t memtype, size_t len,
> +                                   uint32_t attr);
> +
> +    int vcm_phys_free(struct physmem *physmem);
> +
> +    int vcm_back(struct res *res, struct physmem *physmem);
> +
> +    int vcm_unback(struct res *res);
> +
> +attr can include an alignment request, a specification to map memory using
> +various block sizes and/or to use physically contiguous memory. memtype is
> +one of the memory types listed in Memory Targets.
> +
> +The current implementation manages two pools of memory. One pool is a
> +contiguous block of memory and the other is a set of contiguous block
> +pools. In the current implementation the block pools contain 4K, 64K and
> +1M blocks. The physical allocator does not try to split blocks from the
> +contiguous block pools to satisfy requests.
> +
> +The use of 4K, 64K and 1M blocks solves a problem with some IOMMU
> +hardware. IOMMUs are placed in front of multimedia engines to provide a
> +contiguous address space to the device. Multimedia devices need large
> +buffers and large buffers may map to a large number of physical
> +blocks. IOMMUs tend to have small translation lookaside buffers
> +(TLBs). Since the TLB is small the number of physical blocks that map a
> +given range needs to be small or else the IOMMU will continually fetch new
> +translations during a typical streamed multimedia flow. By using a 1 MB
> +mapping (or 64K mapping) instead of a 4K mapping the number of misses can
> +be minimized, allowing the multimedia block to meet its performance goals.
> +
> +Low Level Control
> +-----------------
> +
> +It is necessary in some instances to access attributes and provide
> +higher-level control of the low-level hardware abstraction. The API
> +contains many functions for this task but the two that are typically used
> +are:
> +
> +    size_t vcm_get_dev_addr(struct res *res);
> +
> +    int vcm_hook(size_t dev, vcm_handler handler, void *data);
> +
> +The first function, vcm_get_dev_addr() returns a device address given a
> +reservation. This device address is a virtual IOMMU address for
> +reservations on IOMMU VCMs, a virtual VMM address for reservations on VMM
> +VCMs and a virtual (really physical since its one-to-one mapped) address
> +for one-to-one devices.
> +
> +The second function, vcm_hook allows a caller in the kernel to register a

                        vcm_hook,

> +user_handler. The handler is passed the data member passed to vcm_hook
> +during a fault. The user can return 1 to indicate that the underlying
> +driver should handle the fault and retry the transaction or they can
> +return 0 to halt the transaction. If the user doesn't register a handler
> +the low-level driver will print a warning and terminate the transaction.
> +
> +A Detailed Walk Through
> +-----------------------
> +
> +The following call sequence walks through a typical allocation
> +sequence. In the first stage the memory for a device is reserved and
> +backed. This occurs without mapping the memory into a VMM VCM region. The
> +second stage maps the first VCM region into a VMM VCM region so the kernel
> +can read or write it. The second stage is not necessary if the VMM does
> +not need to read or modify the contents of the original mapping.
> +
> +    Stage 1: Map and Allocate Memory for a Device
> +
> +    The call sequence starts by creating a VCM region:
> +
> +        vcm = vcm_create(start_addr, len);
> +
> +    The next call associates a VCM region with a device:
> +
> +        avcm = vcm_assoc(vcm, dev, attr);
> +
> +    To activate the association users call vcm_activate() on the avcm from

                       association,

> +    the associate call. This programs the underlining device with the
> +    mappings.
> +
> +        ret = vcm_activate(avcm);
> +
> +    Once a VCM region is created and associated it can be reserved from
> +    with:
> +
> +        res = vcm_reserve(vcm, res_len, res_attr);
> +
> +    A user then allocates physical memory with:
> +
> +        physmem = vcm_phys_alloc(memtype, len, phys_attr);
> +
> +    To back the reservation with the physical memory allocation the user
> +    calls:
> +
> +        vcm_back(res, physmem);
> +
> +
> +    Stage 2: Map the Device's Memory into the VMM's VCM region
> +
> +    If the VMM needs to read and/or write the region that was just created

                                                                      created,

> +    the following calls are made.
> +
> +    The first call creates a prebuilt VCM with:
> +
> +        vcm_vmm = vcm_from_prebuilt(ext_vcm_id);
> +
> +    The prebuilt VCM is associated with the CPU device and activated with:
> +
> +        avcm_vmm = vcm_assoc(vcm_vmm, dev_cpu, attr);
> +        vcm_activate(avcm_vmm);
> +
> +    A reservation is made on the VMM VCM with:
> +
> +        res_vmm = vcm_reserve(vcm_vmm, res_len, attr);
> +
> +    Finally, once the topology has been set up a vcm_back() allows the VMM
> +    to read the memory using the physmem generated in stage 1:
> +
> +        vcm_back(res_vmm, physmem);
> +
> +Mapping IOMMU, one-to-one and VMM Reservations
> +----------------------------------------------
> +
> +The following example demonstrates mapping IOMMU, one-to-one and VMM
> +reservations to the same physical memory. It shows the use of phys_addr
> +and phys_size to create a contiguous VCM for one-to-one mapped devices.
> +
> +    The user allocates physical memory:
> +
> +        physmem = vcm_phys_alloc(memtype, SZ_2MB + SZ_4K, CONTIGUOUS);
> +
> +    Creates an IOMMU VCM:
> +
> +        vcm_iommu = vcm_create(SZ_1K, SZ_16M);
> +
> +    Creates an one-to-one VCM:

               a one-to-one

> +
> +        vcm_onetoone = vcm_create(phys_addr, phys_size);
> +
> +    Creates a Prebuit VCM:
> +
> +        vcm_vmm = vcm_from_prebuit(ext_vcm_id);
> +
> +    Associate and activate all three to their respective devices:
> +
> +        avcm_iommu = vcm_assoc(vcm_iommu, dev_iommu, attr0);
> +        avcm_onetoone = vcm_assoc(vcm_onetoone, dev_onetoone, attr1);
> +        avcm_vmm = vcm_assoc(vcm_vmm, dev_cpu, attr2);

error handling on vcm_assoc() failures?

> +        vcm_activate(avcm_iommu);
> +        vcm_activate(avcm_onetoone);
> +        vcm_activate(avcm_vmm);
> +
> +    And finally, creates and backs reservations on all 3 such that they
> +    all point to the same memory:
> +
> +        res_iommu = vcm_reserve(vcm_iommu, SZ_2MB + SZ_4K, attr);
> +        res_onetoone = vcm_reserve(vcm_onetoone, SZ_2MB + SZ_4K, attr);
> +        res_vmm = vcm_reserve(vcm_vmm, SZ_2MB + SZ_4K, attr);

error handling?

> +        vcm_back(res_iommu, physmem);
> +        vcm_back(res_onetoone, physmem);
> +        vcm_back(res_vmm, physmem);
> +
> +VCM Summary
> +-----------
> +
> +The VCMM is an attempt to abstract attributes of three distinct classes of
> +mappings into one API. The VCMM allows users to reason about mappings as
> +first class objects. It also allows memory mappings to flow from the
> +traditional 4K mappings prevalent on systems today to more efficient block
> +sizes. Finally, it allows users to manage mapping interoperation without
> +becoming VMM experts. These features will allow future systems with many
> +MMU mapped devices to interoperate simply and therefore correctly.
> +
> +
> +IOMMU Hardware Control
> +======================
> +
> +The VCM currently supports a single type of IOMMU, a Qualcomm System MMU
> +(SMMU). The SMMU interface contains functions to map and unmap virtual
> +addresses, perform address translations and initialize hardware. A
> +Qualcomm SMMU can contain multiple MMU contexts. Each context can
> +translate in parallel. All contexts in a SMMU share one global translation
> +look-aside buffer (TLB).
> +
> +To support context muxing the SMMU module creates and manages device
> +independent virtual contexts. These context abstractions are bound to
> +actual contexts at run-time. Once bound, a context can be activated. This
> +activation programs the underlying context with the virtual context
> +affecting a context switch.
> +
> +The following functions are all documented in:
> +
> +    arch/arm/mach-msm/include/mach/smmu_driver.h.
> +
> +Mapping
> +-------
> +
> +To map and unmap a virtual page into physical space the VCM calls:
> +
> +    int smmu_map(struct smmu_dev *dev, unsigned long pa,
> +                 unsigned long va, unsigned long len, unsigned int attr);
> +
> +    int smmu_unmap(struct smmu_dev *dev, unsigned long va,
> +                   unsigned long len);
> +
> +    int smmu_update_start(struct smmu_dev *dev);
> +
> +    int smmu_update_done(struct smmu_dev *dev);
> +
> +The size given to map must be 4K, 64K, 1M or 16M and the VA and PA must be
> +aligned to the given size. smmu_update_start() and smmu_update_done()
> +should be called before and after each map or unmap.
> +
> +Translation
> +-----------
> +
> +To request a hardware VA to PA translation on a single address the VCM
> +calls:
> +
> +    unsigned long smmu_translate(struct smmu_dev *dev,
> +                                 unsigned long va);
> +
> +Fault Handling
> +--------------
> +
> +To register an interrupt handler for a context the VCM calls:
> +
> +    int smmu_hook_irpt(struct smmu_dev *dev, vcm_handler handler,
> +                       void *data);

We try to spell out things like "interrupt" in function names
because I/we can't remember just how you decided to abbreviate it.

> +
> +The registered interrupt handler should return 1 if it wants the SMMU
> +driver to retry the transaction again and 0 if it wants the SMMU driver to
> +terminate the transaction.
> +
> +Managing SMMU Initialization and Contexts
> +-----------------------------------------
> +
> +SMMU hardware initialization and management happens in 2 steps. The first
> +step initializes global SMMU devices and abstract device contexts. The
> +second step binds contexts and devices.
> +
> +A SMMU hardware instance is built with:

   An SMMU

> +
> +    int smmu_drvdata_init(struct smmu_driver *drv, unsigned long base,
> +                          int irq);
> +
> +A SMMU context is Initialized and deinitialized with:

   An SMMU           initialized

> +
> +    struct smmu_dev *smmu_ctx_init(int ctx);
> +    int smmu_ctx_deinit(struct smmu_dev *dev);
> +
> +An abstract SMMU context is bound to a particular SMMU with:
> +
> +    int smmu_ctx_bind(struct smmu_dev *ctx, struct smmu_driver *drv);
> +
> +Activation
> +----------
> +
> +Activation affects a context switch.
> +
> +Activation, deactivation and activation state testing are done with:
> +
> +    int smmu_activate(struct smmu_dev *dev);
> +    int smmu_deactivate(struct smmu_dev *dev);
> +    int smmu_is_active(struct smmu_dev *dev);
> +
> +
> +Userspace Access to Devices with IOMMUs
> +=======================================
> +
> +A device that issues transactions through an IOMMU must work with two
> +APIs. The first API is the VCM. The VCM API is device independent. Users
> +pass the VCM a dev_id and the VCM makes calls on the hardware device it
> +has been configured with using this dev_id. The second API is whatever
> +device topology has been created to organize the particular IOMMUs in a
> +system. The only constraint on this second API is that it must give the
> +user a single dev_id that it can pass through the VCM.
> +
> +For the Qualcomm SMMUs the second API consists of a tree of platform
> +devices and two platform drivers as well as a context lookup function that
> +traverses the device tree and returns a dev_id given a context name.
> +
> +Qualcomm SMMU Device Tree
> +-------------------------
> +
> +The current tree organizes the devices into a tree that looks like the
> +following:
> +
> +smmu/
> +               smmu0/
> +                                ctx0
> +                                ctx1
> +                                ctx2
> +               smmu1/
> +                                ctx3
> +
> +
> +Each context, ctx[n] and each smmu, smmu[n] is given a name. Since users
> +are interested in contexts not smmus, the contexts name is passed to a

                                             context

> +function to find the dev_id associated with that name. The functions to
> +find, free and get the base address (since the device probe function calls
> +ioremap to map the SMMUs configuration registers into the kernel) are
> +listed here:
> +
> +    struct smmu_dev *smmu_get_ctx_instance(char *ctx_name);
> +    int smmu_free_ctx_instance(struct smmu_dev *dev);
> +    unsigned long smmu_get_base_addr(struct smmu_dev *dev);
> +
> +Documentation for these functions is in:
> +
> +    arch/arm/mach-msm/include/mach/smmu_device.h
> +
> +Each context is given a dev node named after the context. For example:
> +
> +    /dev/vcodec_a_mm1
> +    /dev/vcodec_b_mm2
> +    /dev/vcodec_stream
> +    etc...
> +
> +Users open, close and mmap these nodes to access VCM buffers from
> +userspace in the same way that they used to open, close and mmap /dev
> +nodes that represented large physically contiguous buffers (called PMEM
> +buffers on Android).
> +
> +Example
> +-------
> +
> +An abbreviated example is shown here:
> +
> +Users get the dev_id associated with their target context, create a VCM
> +topology appropriate for their device and finally associate the VCMs of
> +the topology with the contexts that will take the VCMs:
> +
> +    dev_id = smmu_get_ctx_instance(vcodec_a_stream);
> +
> +create vcm and needed topology
> +
> +    avcm = vcm_assoc(vcm, dev_id, attr);
> +
> +Tying it all Together
> +---------------------
> +
> +VCMs, IOMMUs and the device tree all work to support system-wide memory
> +mappings. The use of each API in this system allows users to concentrate
> +on the relevant details without needing to worry about low-level
> +details. The APIs clear separation of memory spaces and the devices that

                API's

> +support those memory spaces continues Linuxs tradition of abstracting the

                                         the Linux tradition

> +what from the how.
> +
> +
> +Maintainer: Zach Pfeffer <zpfeffer at codeaurora.org>
> -- 


---
~Randy
*** Remember to use Documentation/SubmitChecklist when testing your code ***


From marek.vasut at gmail.com  Wed Jun 30 20:01:05 2010
From: marek.vasut at gmail.com (Marek Vasut)
Date: Thu, 1 Jul 2010 02:01:05 +0200
Subject: [PATCH 08/33] Removing dead SA1101
In-Reply-To: <alpine.LFD.2.00.1006301453450.24097@xanadu.home>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<201006302020.52270.marek.vasut@gmail.com>
	<alpine.LFD.2.00.1006301453450.24097@xanadu.home>
Message-ID: <201007010201.05424.marek.vasut@gmail.com>

Dne St 30. ?ervna 2010 20:59:05 Nicolas Pitre napsal(a):
> On Wed, 30 Jun 2010, Marek Vasut wrote:
> > Dne St 30. ?ervna 2010 18:57:43 Nicolas Pitre napsal(a):
> > > On Wed, 30 Jun 2010, Christoph Egger wrote:
> > > > SA1101 doesn't exist in Kconfig, therefore removing all
> > > > references for it from the source code.
> > > > 
> > > > Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> > > 
> > > Acked-by: Nicolas Pitre <nico at fluxnic.net>
> > 
> > You're dropping support for a whole CPU here ... is the code redundant or
> > something ?
> 
> The SA1101 is not a CPU.  It is a companion chipset for the SA1100.  And
> so far we have no target using it in the tree, and that isn't likely to
> change more than 10 years after the chip availability.  Needless to say
> that the SA1101 has long been unavailable either.
> 
> We also have support for the SA1111 which is a similar companion chipset
> for the SA1110.  This is not going away as at least the Neponset
> expansion board for the Assabet development board is using a SA1111.
> 
> 
> Nicolas

Oh I see. Thanks for clearing that.


From coffbeta at gmail.com  Wed Jun 30 22:26:50 2010
From: coffbeta at gmail.com (CoffBeta)
Date: Thu, 1 Jul 2010 10:26:50 +0800
Subject: TQ 2440 problem
Message-ID: <AANLkTildbEzpPZsFyx7vGD36MNeNTUlAqoqQNxMraLvw@mail.gmail.com>

NOW, Booting Linux......
Uncompressing Linux.............................................................
s3c24xx_serial_initconsole
s3c24xx_serial_initconsole
s3c24xx_serial_init_ports: initialising ports...
s3c24xx_serial_init_port: port=c03939ec, platdev=c03a3700
s3c24xx_serial_init_port: c03939ec (hw 0)...
resource c0387c38 (50000000..50003fff)
port: map=50000000, mem=f5000000, irq=70, clock=1
s3c2440_serial_resetport: port=c03939ec (50000000), cfg=c03a367c
                                                                s3c24xx_serial_0
s3c24xx_serial_init_port: c0393a84 (hw 1)...
resource c0387c70 (50004000..50007fff)
port: map=50004000, mem=f5004000, irq=73, clock=1
s3c2440_serial_resetport: port=c0393a84 (50004000), cfg=c03a3698
s3c24xx_serial_init_port: port=c0393b1c, platdev=c0387e08
s3c24xx_serial_init_port: c0393b1c (hw 2)...
resource c0387ca8 (50008000..5000bfff)
port: map=50008000, mem=f5008000, irq=76, clock=1
s3c2440_serial_resetport: port=c0393b1c (50008000), cfg=c03a36b4
s3c24xx_serial_console_setup: co=c0393ba0 (0), <NULL>
s3c24xx_serial_console_setup: port=c03939ec (0)
s3c24xx_serial_get_options: port=c03939ec
registers: ulcon=00000003, ucon=000003c5, ubdriv=0000001a
calculated baud 115740
s3c24xx_serial_console_setup: baud 115740
config: 8bits/char
setting ulcon to 00000003, brddiv to 26
uart: ulcon = 0x00000003, ucon = 0x000003c5, ufcon = 0x00000051
Linux version 2.6.27-EmbedSky (ymcheng at ymcheng-desktop) (gcc version 4.3.3 (Sou0
CPU: ARM920T [41129200] revision 0 (ARMv4T), cr=c0007177
Machine: SMDK2440
ATAG_INITRD is deprecated; please update your bootloader.
Memory policy: ECC disabled, Data cache writeback
CPU S3C2440A (id 0x32440001)
S3C244X: core 400.000 MHz, memory 100.000 MHz, peripheral 50.000 MHz
S3C24XX Clocks, (c) 2004 Simtec Electronics
CLOCK: Slow mode (1.500 MHz), fast, MPLL on, UPLL on
CPU0: D VIVT write-back cache
CPU0: I cache: 16384 bytes, associativity 64, 32 byte lines, 8 sets
CPU0: D cache: 16384 bytes, associativity 64, 32 byte lines, 8 sets
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 16256
Kernel command line: noinitrd root=/dev/mtdblock2 init=/linuxrc console=ttySAC0
irq: clearing pending ext status 00080000
irq: clearing subpending status 00000003
irq: clearing subpending status 00000002
PID hash table entries: 256 (order: 8, 1024 bytes)
timer tcon=00500000, tcnt a2c1, tcfg 00000200,00000000, usec 00001eb8
Console: colour dummy device 80x30
console [ttySAC0] enabled
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 64MB = 64MB total
Memory: 60980KB available (3428K code, 303K data, 128K init)
Calibrating delay loop... 199.47 BogoMIPS (lpj=498688)
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok

...............linux 2.6.27...............
net_namespace: 440 bytes
NET: Registered protocol family 16
------------[ cut here ]------------
WARNING: at fs/sysfs/dir.c:463 sysfs_add_one+0x30/0x44()
sysfs: duplicate filename 'dm9000.0' can not be created
Modules linked in:
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0046f70>] (warn_slowpath+0x64/0x80)
[<c0046f0c>] (warn_slowpath+0x0/0x80) from [<c00cdb74>] (sysfs_add_one+0x30/0x4)
 r3:c3841ea0 r2:c03396e6
 r6:c0389288 r5:c3849248 r4:ffffffef
[<c00cdb44>] (sysfs_add_one+0x0/0x44) from [<c00ce140>] (create_dir+0x58/0xa8)
 r5:c3849248 r4:c3819dc0
[<c00ce0e8>] (create_dir+0x0/0xa8) from [<c00ce1d0>] (sysfs_create_dir+0x40/0x6)
 r8:c0394128 r7:c03892ac r6:c0394128 r5:00000000 r4:c0389288
[<c00ce190>] (sysfs_create_dir+0x0/0x60) from [<c01334dc>] (kobject_add_interna)
 r4:c0389288
[<c013341c>] (kobject_add_internal+0x0/0x194) from [<c013368c>] (kobject_add_va)
 r9:00000000 r8:c03892ac r7:c03892ac r6:c0394128 r5:00000000
r4:c0389288
[<c013364c>] (kobject_add_varg+0x0/0x50) from [<c0133738>] (kobject_add+0x58/0x)
 r7:c03892ac r6:c0389218 r5:c0389220 r4:00000054
[<c01336e0>] (kobject_add+0x0/0x64) from [<c0175de0>] (device_add+0x78/0x50c)
 r3:c03892ac r2:c0355bea
[<c0175d68>] (device_add+0x0/0x50c) from [<c017932c>] (platform_device_add+0x10)
[<c017922c>] (platform_device_add+0x0/0x150) from [<c017939c>] (platform_device)
 r7:00000006 r6:00000000 r5:c002514c r4:c0389218
[<c017937c>] (platform_device_register+0x0/0x24) from [<c0179594>] (platform_ad)
 r5:c002514c r4:00000005
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
---[ end trace 1b75b31a2719ed1c ]---
kobject_add_internal failed for dm9000.0 with -EEXIST, don't try to register th.
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0133568>] (kobject_add_internal+0x14)
[<c013341c>] (kobject_add_internal+0x0/0x194) from [<c013368c>] (kobject_add_va)
 r9:00000000 r8:c03892ac r7:c03892ac r6:c0394128 r5:00000000
r4:c0389288
[<c013364c>] (kobject_add_varg+0x0/0x50) from [<c0133738>] (kobject_add+0x58/0x)
 r7:c03892ac r6:c0389218 r5:c0389220 r4:00000054
[<c01336e0>] (kobject_add+0x0/0x64) from [<c0175de0>] (device_add+0x78/0x50c)
 r3:c03892ac r2:c0355bea
[<c0175d68>] (device_add+0x0/0x50c) from [<c017932c>] (platform_device_add+0x10)
[<c017922c>] (platform_device_add+0x0/0x150) from [<c017939c>] (platform_device)
 r7:00000006 r6:00000000 r5:c002514c r4:c0389218
[<c017937c>] (platform_device_register+0x0/0x24) from [<c0179594>] (platform_ad)
 r5:c002514c r4:00000005
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
------------[ cut here ]------------
WARNING: at drivers/base/core.c:122 device_release+0x6c/0x78()
Device 's3c24xx_led.3' does not have a release() function, it is broken and mus.
Modules linked in:
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0046f70>] (warn_slowpath+0x64/0x80)
[<c0046f0c>] (warn_slowpath+0x0/0x80) from [<c01753b0>] (device_release+0x6c/0x)
 r3:c0389184 r2:c0349209
 r6:c3841f80 r5:c0393f70 r4:c0389160
[<c0175344>] (device_release+0x0/0x78) from [<c0133384>] (kobject_release+0x5c/)
[<c0133328>] (kobject_release+0x0/0x70) from [<c01340a8>] (kref_put+0x68/0x78)
 r7:00000006 r6:ffffffef r5:c0133328 r4:c038917c
[<c0134040>] (kref_put+0x0/0x78) from [<c0133268>] (kobject_put+0x48/0x60)
 r5:c0025158 r4:c0389160
[<c0133220>] (kobject_put+0x0/0x60) from [<c0174f48>] (put_device+0x1c/0x20)
 r4:c03890f0
[<c0174f2c>] (put_device+0x0/0x20) from [<c01794e8>] (platform_device_put+0x1c/)
[<c01794cc>] (platform_device_put+0x0/0x20) from [<c017956c>] (platform_device_)
[<c0179550>] (platform_device_unregister+0x0/0x20) from [<c01795b0>] (platform_)
 r5:c0025158 r4:00000004
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
---[ end trace 1b75b31a2719ed1c ]---
------------[ cut here ]------------
WARNING: at drivers/base/core.c:122 device_release+0x6c/0x78()
Device 's3c24xx_led.2' does not have a release() function, it is broken and mus.
Modules linked in:
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0046f70>] (warn_slowpath+0x64/0x80)
[<c0046f0c>] (warn_slowpath+0x0/0x80) from [<c01753b0>] (device_release+0x6c/0x)
 r3:c038905c r2:c0349209
 r6:c3841220 r5:c0393f70 r4:c0389038
[<c0175344>] (device_release+0x0/0x78) from [<c0133384>] (kobject_release+0x5c/)
[<c0133328>] (kobject_release+0x0/0x70) from [<c01340a8>] (kref_put+0x68/0x78)
 r7:00000006 r6:ffffffef r5:c0133328 r4:c0389054
[<c0134040>] (kref_put+0x0/0x78) from [<c0133268>] (kobject_put+0x48/0x60)
 r5:c0025154 r4:c0389038
[<c0133220>] (kobject_put+0x0/0x60) from [<c0174f48>] (put_device+0x1c/0x20)
 r4:c0388fc8
[<c0174f2c>] (put_device+0x0/0x20) from [<c01794e8>] (platform_device_put+0x1c/)
[<c01794cc>] (platform_device_put+0x0/0x20) from [<c017956c>] (platform_device_)
[<c0179550>] (platform_device_unregister+0x0/0x20) from [<c01795b0>] (platform_)
 r5:c0025154 r4:00000003
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
---[ end trace 1b75b31a2719ed1c ]---
------------[ cut here ]------------
WARNING: at drivers/base/core.c:122 device_release+0x6c/0x78()
Device 's3c24xx_led.1' does not have a release() function, it is broken and mus.
Modules linked in:
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0046f70>] (warn_slowpath+0x64/0x80)
[<c0046f0c>] (warn_slowpath+0x0/0x80) from [<c01753b0>] (device_release+0x6c/0x)
 r3:c0388f34 r2:c0349209
 r6:c38412e0 r5:c0393f70 r4:c0388f10
[<c0175344>] (device_release+0x0/0x78) from [<c0133384>] (kobject_release+0x5c/)
[<c0133328>] (kobject_release+0x0/0x70) from [<c01340a8>] (kref_put+0x68/0x78)
 r7:00000006 r6:ffffffef r5:c0133328 r4:c0388f2c
[<c0134040>] (kref_put+0x0/0x78) from [<c0133268>] (kobject_put+0x48/0x60)
 r5:c0025150 r4:c0388f10
[<c0133220>] (kobject_put+0x0/0x60) from [<c0174f48>] (put_device+0x1c/0x20)
 r4:c0388ea0
[<c0174f2c>] (put_device+0x0/0x20) from [<c01794e8>] (platform_device_put+0x1c/)
[<c01794cc>] (platform_device_put+0x0/0x20) from [<c017956c>] (platform_device_)
[<c0179550>] (platform_device_unregister+0x0/0x20) from [<c01795b0>] (platform_)
 r5:c0025150 r4:00000002
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
---[ end trace 1b75b31a2719ed1c ]---
------------[ cut here ]------------
WARNING: at drivers/base/core.c:122 device_release+0x6c/0x78()
Device 's3c24xx_led.0' does not have a release() function, it is broken and mus.
Modules linked in:
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0046f70>] (warn_slowpath+0x64/0x80)
[<c0046f0c>] (warn_slowpath+0x0/0x80) from [<c01753b0>] (device_release+0x6c/0x)
 r3:c0388e0c r2:c0349209
 r6:c38413a0 r5:c0393f70 r4:c0388de8
[<c0175344>] (device_release+0x0/0x78) from [<c0133384>] (kobject_release+0x5c/)
[<c0133328>] (kobject_release+0x0/0x70) from [<c01340a8>] (kref_put+0x68/0x78)
 r7:00000006 r6:ffffffef r5:c0133328 r4:c0388e04
[<c0134040>] (kref_put+0x0/0x78) from [<c0133268>] (kobject_put+0x48/0x60)
 r5:c002514c r4:c0388de8
[<c0133220>] (kobject_put+0x0/0x60) from [<c0174f48>] (put_device+0x1c/0x20)
 r4:c0388d78
[<c0174f2c>] (put_device+0x0/0x20) from [<c01794e8>] (platform_device_put+0x1c/)
[<c01794cc>] (platform_device_put+0x0/0x20) from [<c017956c>] (platform_device_)
[<c0179550>] (platform_device_unregister+0x0/0x20) from [<c01795b0>] (platform_)
 r5:c002514c r4:00000001
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
---[ end trace 1b75b31a2719ed1c ]---
------------[ cut here ]------------
WARNING: at drivers/base/core.c:122 device_release+0x6c/0x78()
Device 's3c2440-nand' does not have a release() function, it is broken and must.
Modules linked in:
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0046f70>] (warn_slowpath+0x64/0x80)
[<c0046f0c>] (warn_slowpath+0x0/0x80) from [<c01753b0>] (device_release+0x6c/0x)
 r3:c0387014 r2:c0349209
 r6:c3841460 r5:c0393f70 r4:c0386ff0
[<c0175344>] (device_release+0x0/0x78) from [<c0133384>] (kobject_release+0x5c/)
[<c0133328>] (kobject_release+0x0/0x70) from [<c01340a8>] (kref_put+0x68/0x78)
 r7:00000006 r6:ffffffef r5:c0133328 r4:c038700c
[<c0134040>] (kref_put+0x0/0x78) from [<c0133268>] (kobject_put+0x48/0x60)
 r5:c0025148 r4:c0386ff0
[<c0133220>] (kobject_put+0x0/0x60) from [<c0174f48>] (put_device+0x1c/0x20)
 r4:c0386f80
[<c0174f2c>] (put_device+0x0/0x20) from [<c01794e8>] (platform_device_put+0x1c/)
[<c01794cc>] (platform_device_put+0x0/0x20) from [<c017956c>] (platform_device_)
[<c0179550>] (platform_device_unregister+0x0/0x20) from [<c01795b0>] (platform_)
 r5:c0025148 r4:00000000
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
---[ end trace 1b75b31a2719ed1c ]---
S3C2410 Power Management, (c) 2004 Simtec Electronics
S3C2440: Initialising architecture
S3C2440: IRQ Support
S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics
DMA channel 0 at c4800000, irq 33
DMA channel 1 at c4800040, irq 34
DMA channel 2 at c4800080, irq 35
DMA channel 3 at c48000c0, irq 36
S3C244X: Clock Support, DVS off
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
NET: Registered protocol family 1
NetWinder Floating Point Emulator V0.97 (extended precision)
JFFS2 version 2.2. (NAND) (SUMMARY)  ?? 2001-2006 Red Hat, Inc.
yaffs Jun  7 2010 15:39:55 Installing.
msgmni has been set to 119
io scheduler noop registered
io scheduler anticipatory registered (default)
io scheduler deadline registered
io scheduler cfq registered
Console: switching to colour frame buffer device 40x30
fb0: s3c2410fb frame buffer device
lp: driver loaded but no devices found
ppdev: user-space parallel port driver
s3c24xx_serial_init(c0393c44,c0393c94)
s3c24xx_serial_init(c0393cc4,c0393d14)
s3c2440_serial_probe: dev=c03a3700
s3c24xx_serial_probe(c03a3700, c0393d14) 0
s3c24xx_serial_probe: initialising port c03939d8...
s3c24xx_serial_init_port: port=c03939ec, platdev=c03a3700
s3c24xx_serial_probe: adding port
s3c2440-uart.0: tq2440_serial0 at MMIO 0x50000000 (irq = 70) is a S3C2440
s3c2440_serial_probe: dev=c0387ce0
s3c24xx_serial_probe(c0387ce0, c0393d14) 1
s3c24xx_serial_probe: initialising port c0393a70...
s3c24xx_serial_init_port: port=c0393a84, platdev=c0387ce0
s3c24xx_serial_probe: adding port
s3c2440-uart.1: tq2440_serial1 at MMIO 0x50004000 (irq = 73) is a S3C2440
s3c2440_serial_probe: dev=c0387e08
s3c24xx_serial_probe(c0387e08, c0393d14) 2
s3c24xx_serial_probe: initialising port c0393b08...
s3c24xx_serial_init_port: port=c0393b1c, platdev=c0387e08
s3c24xx_serial_probe: adding port
s3c2440-uart.2: tq2440_serial2 at MMIO 0x50008000 (irq = 76) is a S3C2440
brd: module loaded
loop: module loaded
dm9000 Ethernet Driver, V1.31
Now use the default MAC address: 10:23:45:67:89:ab
dm9000 dm9000.0: eth%d: Invalid ethernet MAC address. Please set using ifconfig
eth0: dm9000e at c485e000,c4860004 IRQ 51 MAC: 00:00:00:00:00:00 (chip)
Uniform Multi-Platform E-IDE driver
st: Version 20080504, fixed bufsize 32768, s/g segs 256
Driver 'st' needs updating - please use bus_type methods
Driver 'sd' needs updating - please use bus_type methods
S3C24XX NAND Driver, (c) 2004 Simtec Electronics
usbmon: debugfs is not available
s3c2410-ohci s3c2410-ohci: S3C24XX OHCI
s3c2410-ohci s3c2410-ohci: new USB bus registered, assigned bus number 1
s3c2410-ohci s3c2410-ohci: irq 42, io mem 0x49000000
usb usb1: configuration #1 chosen from 1 choice
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
usbcore: registered new interface driver libusual
usbcore: registered new interface driver usbserial
usbserial: USB Serial support registered for generic
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial Driver core
usbserial: USB Serial support registered for FTDI USB Serial Device
usbcore: registered new interface driver ftdi_sio
ftdi_sio: v1.4.3:USB FTDI Serial Converters Driver
usbserial: USB Serial support registered for pl2303
usbcore: registered new interface driver pl2303
pl2303: Prolific PL2303 USB to serial adaptor driver
mice: PS/2 mouse device common for all mice
S3C24XX RTC, (c) 2004,2006 Simtec Electronics
i2c /dev entries driver
s3c2440-i2c s3c2440-i2c: slave address 0x10
s3c2440-i2c s3c2440-i2c: bus frequency set to 390 KHz
s3c2440-i2c s3c2440-i2c: i2c-0: S3C I2C adapter
S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics
s3c2410-wdt s3c2410-wdt: watchdog inactive, reset disabled, irq enabled
usbcore: registered new interface driver hiddev
usbcore: registered new interface driver usbhid
usbhid: v2.6:USB HID core driver
Advanced Linux Sound Architecture Driver Version 1.0.17.
ALSA device list:
  No soundcards found.
TCP cubic registered
NET: Registered protocol family 17
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
Root-NFS: No NFS server available, giving up.
VFS: Unable to mount root fs via NFS, trying floppy.
VFS: Cannot open root device "mtdblock2" or unknown-block(2,0)
Please append a correct "root=" boot option; here are the available partitions:
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(2,0)







all the above is my start information.I don't know why can't able to
mount root fs?how
can I do? Thanks


From coffbeta at gmail.com  Wed Jun 30 22:31:43 2010
From: coffbeta at gmail.com (CoffBeta)
Date: Thu, 1 Jul 2010 10:31:43 +0800
Subject: tq 2440
Message-ID: <AANLkTimyBHliUa62qmfja_ke6YTTysiVAtJcZfi8l2gG@mail.gmail.com>

NOW, Booting Linux......
Uncompressing Linux.............................................................
s3c24xx_serial_initconsole
s3c24xx_serial_initconsole
s3c24xx_serial_init_ports: initialising ports...
s3c24xx_serial_init_port: port=c03939ec, platdev=c03a3700
s3c24xx_serial_init_port: c03939ec (hw 0)...
resource c0387c38 (50000000..50003fff)
port: map=50000000, mem=f5000000, irq=70, clock=1
s3c2440_serial_resetport: port=c03939ec (50000000), cfg=c03a367c
                                                               s3c24xx_serial_0
s3c24xx_serial_init_port: c0393a84 (hw 1)...
resource c0387c70 (50004000..50007fff)
port: map=50004000, mem=f5004000, irq=73, clock=1
s3c2440_serial_resetport: port=c0393a84 (50004000), cfg=c03a3698
s3c24xx_serial_init_port: port=c0393b1c, platdev=c0387e08
s3c24xx_serial_init_port: c0393b1c (hw 2)...
resource c0387ca8 (50008000..5000bfff)
port: map=50008000, mem=f5008000, irq=76, clock=1
s3c2440_serial_resetport: port=c0393b1c (50008000), cfg=c03a36b4
s3c24xx_serial_console_setup: co=c0393ba0 (0), <NULL>
s3c24xx_serial_console_setup: port=c03939ec (0)
s3c24xx_serial_get_options: port=c03939ec
registers: ulcon=00000003, ucon=000003c5, ubdriv=0000001a
calculated baud 115740
s3c24xx_serial_console_setup: baud 115740
config: 8bits/char
setting ulcon to 00000003, brddiv to 26
uart: ulcon = 0x00000003, ucon = 0x000003c5, ufcon = 0x00000051
Linux version 2.6.27-EmbedSky (ymcheng at ymcheng-desktop) (gcc version 4.3.3 (Sou0
CPU: ARM920T [41129200] revision 0 (ARMv4T), cr=c0007177
Machine: SMDK2440
ATAG_INITRD is deprecated; please update your bootloader.
Memory policy: ECC disabled, Data cache writeback
CPU S3C2440A (id 0x32440001)
S3C244X: core 400.000 MHz, memory 100.000 MHz, peripheral 50.000 MHz
S3C24XX Clocks, (c) 2004 Simtec Electronics
CLOCK: Slow mode (1.500 MHz), fast, MPLL on, UPLL on
CPU0: D VIVT write-back cache
CPU0: I cache: 16384 bytes, associativity 64, 32 byte lines, 8 sets
CPU0: D cache: 16384 bytes, associativity 64, 32 byte lines, 8 sets
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 16256
Kernel command line: noinitrd root=/dev/mtdblock2 init=/linuxrc console=ttySAC0
irq: clearing pending ext status 00080000
irq: clearing subpending status 00000003
irq: clearing subpending status 00000002
PID hash table entries: 256 (order: 8, 1024 bytes)
timer tcon=00500000, tcnt a2c1, tcfg 00000200,00000000, usec 00001eb8
Console: colour dummy device 80x30
console [ttySAC0] enabled
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 64MB = 64MB total
Memory: 60980KB available (3428K code, 303K data, 128K init)
Calibrating delay loop... 199.47 BogoMIPS (lpj=498688)
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok

...............linux 2.6.27...............
net_namespace: 440 bytes
NET: Registered protocol family 16
------------[ cut here ]------------
WARNING: at fs/sysfs/dir.c:463 sysfs_add_one+0x30/0x44()
sysfs: duplicate filename 'dm9000.0' can not be created
Modules linked in:
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0046f70>] (warn_slowpath+0x64/0x80)
[<c0046f0c>] (warn_slowpath+0x0/0x80) from [<c00cdb74>] (sysfs_add_one+0x30/0x4)
 r3:c3841ea0 r2:c03396e6
 r6:c0389288 r5:c3849248 r4:ffffffef
[<c00cdb44>] (sysfs_add_one+0x0/0x44) from [<c00ce140>] (create_dir+0x58/0xa8)
 r5:c3849248 r4:c3819dc0
[<c00ce0e8>] (create_dir+0x0/0xa8) from [<c00ce1d0>] (sysfs_create_dir+0x40/0x6)
 r8:c0394128 r7:c03892ac r6:c0394128 r5:00000000 r4:c0389288
[<c00ce190>] (sysfs_create_dir+0x0/0x60) from [<c01334dc>] (kobject_add_interna)
 r4:c0389288
[<c013341c>] (kobject_add_internal+0x0/0x194) from [<c013368c>] (kobject_add_va)
 r9:00000000 r8:c03892ac r7:c03892ac r6:c0394128 r5:00000000
r4:c0389288
[<c013364c>] (kobject_add_varg+0x0/0x50) from [<c0133738>] (kobject_add+0x58/0x)
 r7:c03892ac r6:c0389218 r5:c0389220 r4:00000054
[<c01336e0>] (kobject_add+0x0/0x64) from [<c0175de0>] (device_add+0x78/0x50c)
 r3:c03892ac r2:c0355bea
[<c0175d68>] (device_add+0x0/0x50c) from [<c017932c>] (platform_device_add+0x10)
[<c017922c>] (platform_device_add+0x0/0x150) from [<c017939c>] (platform_device)
 r7:00000006 r6:00000000 r5:c002514c r4:c0389218
[<c017937c>] (platform_device_register+0x0/0x24) from [<c0179594>] (platform_ad)
 r5:c002514c r4:00000005
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
---[ end trace 1b75b31a2719ed1c ]---
kobject_add_internal failed for dm9000.0 with -EEXIST, don't try to register th.
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0133568>] (kobject_add_internal+0x14)
[<c013341c>] (kobject_add_internal+0x0/0x194) from [<c013368c>] (kobject_add_va)
 r9:00000000 r8:c03892ac r7:c03892ac r6:c0394128 r5:00000000
r4:c0389288
[<c013364c>] (kobject_add_varg+0x0/0x50) from [<c0133738>] (kobject_add+0x58/0x)
 r7:c03892ac r6:c0389218 r5:c0389220 r4:00000054
[<c01336e0>] (kobject_add+0x0/0x64) from [<c0175de0>] (device_add+0x78/0x50c)
 r3:c03892ac r2:c0355bea
[<c0175d68>] (device_add+0x0/0x50c) from [<c017932c>] (platform_device_add+0x10)
[<c017922c>] (platform_device_add+0x0/0x150) from [<c017939c>] (platform_device)
 r7:00000006 r6:00000000 r5:c002514c r4:c0389218
[<c017937c>] (platform_device_register+0x0/0x24) from [<c0179594>] (platform_ad)
 r5:c002514c r4:00000005
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
------------[ cut here ]------------
WARNING: at drivers/base/core.c:122 device_release+0x6c/0x78()
Device 's3c24xx_led.3' does not have a release() function, it is broken and mus.
Modules linked in:
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0046f70>] (warn_slowpath+0x64/0x80)
[<c0046f0c>] (warn_slowpath+0x0/0x80) from [<c01753b0>] (device_release+0x6c/0x)
 r3:c0389184 r2:c0349209
 r6:c3841f80 r5:c0393f70 r4:c0389160
[<c0175344>] (device_release+0x0/0x78) from [<c0133384>] (kobject_release+0x5c/)
[<c0133328>] (kobject_release+0x0/0x70) from [<c01340a8>] (kref_put+0x68/0x78)
 r7:00000006 r6:ffffffef r5:c0133328 r4:c038917c
[<c0134040>] (kref_put+0x0/0x78) from [<c0133268>] (kobject_put+0x48/0x60)
 r5:c0025158 r4:c0389160
[<c0133220>] (kobject_put+0x0/0x60) from [<c0174f48>] (put_device+0x1c/0x20)
 r4:c03890f0
[<c0174f2c>] (put_device+0x0/0x20) from [<c01794e8>] (platform_device_put+0x1c/)
[<c01794cc>] (platform_device_put+0x0/0x20) from [<c017956c>] (platform_device_)
[<c0179550>] (platform_device_unregister+0x0/0x20) from [<c01795b0>] (platform_)
 r5:c0025158 r4:00000004
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
---[ end trace 1b75b31a2719ed1c ]---
------------[ cut here ]------------
WARNING: at drivers/base/core.c:122 device_release+0x6c/0x78()
Device 's3c24xx_led.2' does not have a release() function, it is broken and mus.
Modules linked in:
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0046f70>] (warn_slowpath+0x64/0x80)
[<c0046f0c>] (warn_slowpath+0x0/0x80) from [<c01753b0>] (device_release+0x6c/0x)
 r3:c038905c r2:c0349209
 r6:c3841220 r5:c0393f70 r4:c0389038
[<c0175344>] (device_release+0x0/0x78) from [<c0133384>] (kobject_release+0x5c/)
[<c0133328>] (kobject_release+0x0/0x70) from [<c01340a8>] (kref_put+0x68/0x78)
 r7:00000006 r6:ffffffef r5:c0133328 r4:c0389054
[<c0134040>] (kref_put+0x0/0x78) from [<c0133268>] (kobject_put+0x48/0x60)
 r5:c0025154 r4:c0389038
[<c0133220>] (kobject_put+0x0/0x60) from [<c0174f48>] (put_device+0x1c/0x20)
 r4:c0388fc8
[<c0174f2c>] (put_device+0x0/0x20) from [<c01794e8>] (platform_device_put+0x1c/)
[<c01794cc>] (platform_device_put+0x0/0x20) from [<c017956c>] (platform_device_)
[<c0179550>] (platform_device_unregister+0x0/0x20) from [<c01795b0>] (platform_)
 r5:c0025154 r4:00000003
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
---[ end trace 1b75b31a2719ed1c ]---
------------[ cut here ]------------
WARNING: at drivers/base/core.c:122 device_release+0x6c/0x78()
Device 's3c24xx_led.1' does not have a release() function, it is broken and mus.
Modules linked in:
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0046f70>] (warn_slowpath+0x64/0x80)
[<c0046f0c>] (warn_slowpath+0x0/0x80) from [<c01753b0>] (device_release+0x6c/0x)
 r3:c0388f34 r2:c0349209
 r6:c38412e0 r5:c0393f70 r4:c0388f10
[<c0175344>] (device_release+0x0/0x78) from [<c0133384>] (kobject_release+0x5c/)
[<c0133328>] (kobject_release+0x0/0x70) from [<c01340a8>] (kref_put+0x68/0x78)
 r7:00000006 r6:ffffffef r5:c0133328 r4:c0388f2c
[<c0134040>] (kref_put+0x0/0x78) from [<c0133268>] (kobject_put+0x48/0x60)
 r5:c0025150 r4:c0388f10
[<c0133220>] (kobject_put+0x0/0x60) from [<c0174f48>] (put_device+0x1c/0x20)
 r4:c0388ea0
[<c0174f2c>] (put_device+0x0/0x20) from [<c01794e8>] (platform_device_put+0x1c/)
[<c01794cc>] (platform_device_put+0x0/0x20) from [<c017956c>] (platform_device_)
[<c0179550>] (platform_device_unregister+0x0/0x20) from [<c01795b0>] (platform_)
 r5:c0025150 r4:00000002
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
---[ end trace 1b75b31a2719ed1c ]---
------------[ cut here ]------------
WARNING: at drivers/base/core.c:122 device_release+0x6c/0x78()
Device 's3c24xx_led.0' does not have a release() function, it is broken and mus.
Modules linked in:
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0046f70>] (warn_slowpath+0x64/0x80)
[<c0046f0c>] (warn_slowpath+0x0/0x80) from [<c01753b0>] (device_release+0x6c/0x)
 r3:c0388e0c r2:c0349209
 r6:c38413a0 r5:c0393f70 r4:c0388de8
[<c0175344>] (device_release+0x0/0x78) from [<c0133384>] (kobject_release+0x5c/)
[<c0133328>] (kobject_release+0x0/0x70) from [<c01340a8>] (kref_put+0x68/0x78)
 r7:00000006 r6:ffffffef r5:c0133328 r4:c0388e04
[<c0134040>] (kref_put+0x0/0x78) from [<c0133268>] (kobject_put+0x48/0x60)
 r5:c002514c r4:c0388de8
[<c0133220>] (kobject_put+0x0/0x60) from [<c0174f48>] (put_device+0x1c/0x20)
 r4:c0388d78
[<c0174f2c>] (put_device+0x0/0x20) from [<c01794e8>] (platform_device_put+0x1c/)
[<c01794cc>] (platform_device_put+0x0/0x20) from [<c017956c>] (platform_device_)
[<c0179550>] (platform_device_unregister+0x0/0x20) from [<c01795b0>] (platform_)
 r5:c002514c r4:00000001
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
---[ end trace 1b75b31a2719ed1c ]---
------------[ cut here ]------------
WARNING: at drivers/base/core.c:122 device_release+0x6c/0x78()
Device 's3c2440-nand' does not have a release() function, it is broken and must.
Modules linked in:
[<c02a4bf8>] (dump_stack+0x0/0x14) from [<c0046f70>] (warn_slowpath+0x64/0x80)
[<c0046f0c>] (warn_slowpath+0x0/0x80) from [<c01753b0>] (device_release+0x6c/0x)
 r3:c0387014 r2:c0349209
 r6:c3841460 r5:c0393f70 r4:c0386ff0
[<c0175344>] (device_release+0x0/0x78) from [<c0133384>] (kobject_release+0x5c/)
[<c0133328>] (kobject_release+0x0/0x70) from [<c01340a8>] (kref_put+0x68/0x78)
 r7:00000006 r6:ffffffef r5:c0133328 r4:c038700c
[<c0134040>] (kref_put+0x0/0x78) from [<c0133268>] (kobject_put+0x48/0x60)
 r5:c0025148 r4:c0386ff0
[<c0133220>] (kobject_put+0x0/0x60) from [<c0174f48>] (put_device+0x1c/0x20)
 r4:c0386f80
[<c0174f2c>] (put_device+0x0/0x20) from [<c01794e8>] (platform_device_put+0x1c/)
[<c01794cc>] (platform_device_put+0x0/0x20) from [<c017956c>] (platform_device_)
[<c0179550>] (platform_device_unregister+0x0/0x20) from [<c01795b0>] (platform_)
 r5:c0025148 r4:00000000
[<c0179570>] (platform_add_devices+0x0/0x68) from [<c0011b50>] (smdk_machine_in)
 r7:c000e6ac r6:00000000 r5:00000000 r4:c0024ebc
[<c0011acc>] (smdk_machine_init+0x0/0x98) from [<c0010950>] (smdk2440_machine_i)
[<c0010928>] (smdk2440_machine_init+0x0/0x54) from [<c000e6cc>] (customize_mach)
 r5:00000000 r4:c00226c4
[<c000e6ac>] (customize_machine+0x0/0x2c) from [<c00282c0>] (do_one_initcall+0x)
[<c0028268>] (do_one_initcall+0x0/0x180) from [<c00085c4>] (kernel_init+0x88/0x)
[<c000853c>] (kernel_init+0x0/0xfc) from [<c0049fa8>] (do_exit+0x0/0x6bc)
 r4:00000000
---[ end trace 1b75b31a2719ed1c ]---
S3C2410 Power Management, (c) 2004 Simtec Electronics
S3C2440: Initialising architecture
S3C2440: IRQ Support
S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics
DMA channel 0 at c4800000, irq 33
DMA channel 1 at c4800040, irq 34
DMA channel 2 at c4800080, irq 35
DMA channel 3 at c48000c0, irq 36
S3C244X: Clock Support, DVS off
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 2048 (order: 2, 16384 bytes)
TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
NET: Registered protocol family 1
NetWinder Floating Point Emulator V0.97 (extended precision)
JFFS2 version 2.2. (NAND) (SUMMARY)  ?? 2001-2006 Red Hat, Inc.
yaffs Jun  7 2010 15:39:55 Installing.
msgmni has been set to 119
io scheduler noop registered
io scheduler anticipatory registered (default)
io scheduler deadline registered
io scheduler cfq registered
Console: switching to colour frame buffer device 40x30
fb0: s3c2410fb frame buffer device
lp: driver loaded but no devices found
ppdev: user-space parallel port driver
s3c24xx_serial_init(c0393c44,c0393c94)
s3c24xx_serial_init(c0393cc4,c0393d14)
s3c2440_serial_probe: dev=c03a3700
s3c24xx_serial_probe(c03a3700, c0393d14) 0
s3c24xx_serial_probe: initialising port c03939d8...
s3c24xx_serial_init_port: port=c03939ec, platdev=c03a3700
s3c24xx_serial_probe: adding port
s3c2440-uart.0: tq2440_serial0 at MMIO 0x50000000 (irq = 70) is a S3C2440
s3c2440_serial_probe: dev=c0387ce0
s3c24xx_serial_probe(c0387ce0, c0393d14) 1
s3c24xx_serial_probe: initialising port c0393a70...
s3c24xx_serial_init_port: port=c0393a84, platdev=c0387ce0
s3c24xx_serial_probe: adding port
s3c2440-uart.1: tq2440_serial1 at MMIO 0x50004000 (irq = 73) is a S3C2440
s3c2440_serial_probe: dev=c0387e08
s3c24xx_serial_probe(c0387e08, c0393d14) 2
s3c24xx_serial_probe: initialising port c0393b08...
s3c24xx_serial_init_port: port=c0393b1c, platdev=c0387e08
s3c24xx_serial_probe: adding port
s3c2440-uart.2: tq2440_serial2 at MMIO 0x50008000 (irq = 76) is a S3C2440
brd: module loaded
loop: module loaded
dm9000 Ethernet Driver, V1.31
Now use the default MAC address: 10:23:45:67:89:ab
dm9000 dm9000.0: eth%d: Invalid ethernet MAC address. Please set using ifconfig
eth0: dm9000e at c485e000,c4860004 IRQ 51 MAC: 00:00:00:00:00:00 (chip)
Uniform Multi-Platform E-IDE driver
st: Version 20080504, fixed bufsize 32768, s/g segs 256
Driver 'st' needs updating - please use bus_type methods
Driver 'sd' needs updating - please use bus_type methods
S3C24XX NAND Driver, (c) 2004 Simtec Electronics
usbmon: debugfs is not available
s3c2410-ohci s3c2410-ohci: S3C24XX OHCI
s3c2410-ohci s3c2410-ohci: new USB bus registered, assigned bus number 1
s3c2410-ohci s3c2410-ohci: irq 42, io mem 0x49000000
usb usb1: configuration #1 chosen from 1 choice
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 2 ports detected
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
usbcore: registered new interface driver libusual
usbcore: registered new interface driver usbserial
usbserial: USB Serial support registered for generic
usbcore: registered new interface driver usbserial_generic
usbserial: USB Serial Driver core
usbserial: USB Serial support registered for FTDI USB Serial Device
usbcore: registered new interface driver ftdi_sio
ftdi_sio: v1.4.3:USB FTDI Serial Converters Driver
usbserial: USB Serial support registered for pl2303
usbcore: registered new interface driver pl2303
pl2303: Prolific PL2303 USB to serial adaptor driver
mice: PS/2 mouse device common for all mice
S3C24XX RTC, (c) 2004,2006 Simtec Electronics
i2c /dev entries driver
s3c2440-i2c s3c2440-i2c: slave address 0x10
s3c2440-i2c s3c2440-i2c: bus frequency set to 390 KHz
s3c2440-i2c s3c2440-i2c: i2c-0: S3C I2C adapter
S3C2410 Watchdog Timer, (c) 2004 Simtec Electronics
s3c2410-wdt s3c2410-wdt: watchdog inactive, reset disabled, irq enabled
usbcore: registered new interface driver hiddev
usbcore: registered new interface driver usbhid
usbhid: v2.6:USB HID core driver
Advanced Linux Sound Architecture Driver Version 1.0.17.
ALSA device list:
 No soundcards found.
TCP cubic registered
NET: Registered protocol family 17
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
Root-NFS: No NFS server available, giving up.
VFS: Unable to mount root fs via NFS, trying floppy.
VFS: Cannot open root device "mtdblock2" or unknown-block(2,0)
Please append a correct "root=" boot option; here are the available partitions:
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(2,0)







all the above is my start information.I don't know why can't able to
mount root fs?how
can I do? Thanks


From eric.y.miao at gmail.com  Wed Jun 30 22:34:13 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Thu, 1 Jul 2010 10:34:13 +0800
Subject: [PATCH 06/33] Removing dead SHARPSL_LOCOMO
In-Reply-To: <b43850b1a1909496718e39687d1ca00543aa30ec.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<b43850b1a1909496718e39687d1ca00543aa30ec.1277911346.git.siccegge@cs.fau.de>
Message-ID: <AANLkTimVRdxeeQKazgFSIQJYtbmHnjDN5lUnTrVv6uoI@mail.gmail.com>

On Wed, Jun 30, 2010 at 11:55 PM, Christoph Egger <siccegge at cs.fau.de> wrote:
> SHARPSL_LOCOMO doesn't exist in Kconfig, therefore removing all
> references for it from the source code.
>

A good catch, though SHARPSL_LOCOMO has be changed to SHARP_LOCOMO
later, so a better fix would be the name change only.

> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
> ---
> ?arch/arm/mach-sa1100/include/mach/irqs.h | ? ?2 --
> ?1 files changed, 0 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-sa1100/include/mach/irqs.h b/arch/arm/mach-sa1100/include/mach/irqs.h
> index 8c8845b..123c6c9 100644
> --- a/arch/arm/mach-sa1100/include/mach/irqs.h
> +++ b/arch/arm/mach-sa1100/include/mach/irqs.h
> @@ -77,8 +77,6 @@
> ?*/
> ?#ifdef CONFIG_SA1111
> ?#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ? ?(IRQ_BOARD_END + 55)
> -#elif defined(CONFIG_SHARPSL_LOCOMO)
> -#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ? ?(IRQ_BOARD_START + 4)
> ?#else
> ?#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ? ?(IRQ_BOARD_START)
> ?#endif
> --
> 1.7.0.4
>
>


From eric.y.miao at gmail.com  Wed Jun 30 22:56:31 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Thu, 1 Jul 2010 10:56:31 +0800
Subject: [PATCH 27/33] Removing dead IDE_PXA_CF
In-Reply-To: <a332e637ee15cb15f7099f5dfc19a384b2bf772b.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<a332e637ee15cb15f7099f5dfc19a384b2bf772b.1277911346.git.siccegge@cs.fau.de>
Message-ID: <AANLkTikXk-NPcDlf0lCSbf8HYHfoZoWh-7bnQar80UMC@mail.gmail.com>

On Thu, Jul 1, 2010 at 12:02 AM, Christoph Egger <siccegge at cs.fau.de> wrote:
> IDE_PXA_CF doesn't exist in Kconfig, therefore removing all references
> for it from the source code.
>
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>

Acked-by: Eric Miao <eric.y.miao at gmail.com>

Include Jurgen though, in case he has any idea.

> ---
> ?arch/arm/mach-pxa/trizeps4.c | ? ?6 +-----
> ?1 files changed, 1 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
> index 6968911..0acff17 100644
> --- a/arch/arm/mach-pxa/trizeps4.c
> +++ b/arch/arm/mach-pxa/trizeps4.c
> @@ -530,13 +530,9 @@ static void __init trizeps4_init(void)
> ? ? ? ?i2c_register_board_info(0, trizeps4_i2c_devices,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ARRAY_SIZE(trizeps4_i2c_devices));
>
> -#ifdef CONFIG_IDE_PXA_CF
> - ? ? ? /* if boot direct from compact flash dont disable power */
> - ? ? ? trizeps_conxs_bcr = 0x0009;
> -#else
> ? ? ? ?/* this is the reset value */
> ? ? ? ?trizeps_conxs_bcr = 0x00A0;
> -#endif
> +
> ? ? ? ?BCR_writew(trizeps_conxs_bcr);
> ? ? ? ?board_backlight_power(1);
> ?}
> --
> 1.7.0.4
>
>


From dedekind1 at gmail.com  Wed Jun 30 23:47:52 2010
From: dedekind1 at gmail.com (Artem Bityutskiy)
Date: Thu, 01 Jul 2010 06:47:52 +0300
Subject: [PATCH] mxc_nand: fix PM
In-Reply-To: <4C15D542.2060102@eukrea.com>
References: <1274942000-3580-2-git-send-email-eric@eukrea.com>
	<1274982919-13251-1-git-send-email-eric@eukrea.com>
	<4C15D542.2060102@eukrea.com>
Message-ID: <1277956072.3599.29.camel@localhost.localdomain>

On Mon, 2010-06-14 at 09:07 +0200, Eric B?nard wrote:
> Hi Sascha,
> 
> Le 27/05/2010 19:55, Eric B?nard a ?crit :
> > * when resuming, we get the following log :
> > nand_resume called for a chip which is not in suspended state
> > * this happens because mtd->suspend and mtd->resume are already
> > called from the mtd layer, thus they were called a second time
> > in mxc_nand so mtd complains when trying to resume for the
> > second time
> > * the fix is to remove these call and thus remove the supend and
> > resume functions of mxc_nand
> >
> any news concerning this patch ?

Pushed to l2-mtd-2.6.git / dunno

-- 
Best Regards,
Artem Bityutskiy (????? ????????)



From eric.y.miao at gmail.com  Wed Jun 30 23:50:36 2010
From: eric.y.miao at gmail.com (Eric Miao)
Date: Thu, 1 Jul 2010 11:50:36 +0800
Subject: [PATCH 23/33] Removing dead BACKLIGHT_CORGI
In-Reply-To: <daefd019d1a302665a0cc5817ed50cfb4b7b1c44.1277911346.git.siccegge@cs.fau.de>
References: <cover.1277911345.git.siccegge@cs.fau.de>
	<daefd019d1a302665a0cc5817ed50cfb4b7b1c44.1277911346.git.siccegge@cs.fau.de>
Message-ID: <AANLkTikeR3hzF8KGBxPoRTiAmXXK62UB4CZ4t8tctC5_@mail.gmail.com>

On Thu, Jul 1, 2010 at 12:01 AM, Christoph Egger <siccegge at cs.fau.de> wrote:
> BACKLIGHT_CORGI doesn't exist in Kconfig, therefore removing all
> references for it from the source code.
>
> Signed-off-by: Christoph Egger <siccegge at cs.fau.de>

BACKLIGHT_CORGI was renamed to BACKLIGHT_GENERIC in commit
d00ba726725c6f41e43df00f83e484ba8f9fac5c.

Since it's now safe to completely transition to LCD_CORGI, which not only
includes the backlight functionality but also the LCD, so

Acked-by: Eric Miao <eric.y.miao at gmail.com>

> ---
> ?arch/arm/mach-pxa/corgi_pm.c ? | ? ?2 --
> ?arch/arm/mach-pxa/sharpsl_pm.c | ? 15 ---------------
> ?arch/arm/mach-pxa/spitz_pm.c ? | ? ?2 --
> ?3 files changed, 0 insertions(+), 19 deletions(-)
>
> diff --git a/arch/arm/mach-pxa/corgi_pm.c b/arch/arm/mach-pxa/corgi_pm.c
> index 3f1dc74..a735205 100644
> --- a/arch/arm/mach-pxa/corgi_pm.c
> +++ b/arch/arm/mach-pxa/corgi_pm.c
> @@ -165,8 +165,6 @@ static struct sharpsl_charger_machinfo corgi_pm_machinfo = {
> ? ? ? ?.should_wakeup ? = corgi_should_wakeup,
> ?#if defined(CONFIG_LCD_CORGI)
> ? ? ? ?.backlight_limit = corgi_lcd_limit_intensity,
> -#elif defined(CONFIG_BACKLIGHT_CORGI)
> - ? ? ? .backlight_limit = corgibl_limit_intensity,
> ?#endif
> ? ? ? ?.charge_on_volt ? = SHARPSL_CHARGE_ON_VOLT,
> ? ? ? ?.charge_on_temp ? = SHARPSL_CHARGE_ON_TEMP,
> diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
> index cb47672..582701e 100644
> --- a/arch/arm/mach-pxa/sharpsl_pm.c
> +++ b/arch/arm/mach-pxa/sharpsl_pm.c
> @@ -277,21 +277,6 @@ static void sharpsl_battery_thread(struct work_struct *private_)
> ? ? ? ?dev_dbg(sharpsl_pm.dev, "Battery: voltage: %d, status: %d, percentage: %d, time: %ld\n", voltage,
> ? ? ? ? ? ? ? ? ? ? ? ?sharpsl_pm.battstat.mainbat_status, sharpsl_pm.battstat.mainbat_percent, jiffies);
>
> -#ifdef CONFIG_BACKLIGHT_CORGI
> - ? ? ? /* If battery is low. limit backlight intensity to save power. */
> - ? ? ? if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
> - ? ? ? ? ? && ((sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_LOW)
> - ? ? ? ? ? || (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL))) {
> - ? ? ? ? ? ? ? if (!(sharpsl_pm.flags & SHARPSL_BL_LIMIT)) {
> - ? ? ? ? ? ? ? ? ? ? ? sharpsl_pm.machinfo->backlight_limit(1);
> - ? ? ? ? ? ? ? ? ? ? ? sharpsl_pm.flags |= SHARPSL_BL_LIMIT;
> - ? ? ? ? ? ? ? }
> - ? ? ? } else if (sharpsl_pm.flags & SHARPSL_BL_LIMIT) {
> - ? ? ? ? ? ? ? sharpsl_pm.machinfo->backlight_limit(0);
> - ? ? ? ? ? ? ? sharpsl_pm.flags &= ~SHARPSL_BL_LIMIT;
> - ? ? ? }
> -#endif
> -
> ? ? ? ?/* Suspend if critical battery level */
> ? ? ? ?if ((sharpsl_pm.battstat.ac_status != APM_AC_ONLINE)
> ? ? ? ? ? ? && (sharpsl_pm.battstat.mainbat_status == APM_BATTERY_STATUS_CRITICAL)
> diff --git a/arch/arm/mach-pxa/spitz_pm.c b/arch/arm/mach-pxa/spitz_pm.c
> index 4209ddf..b36f0ae 100644
> --- a/arch/arm/mach-pxa/spitz_pm.c
> +++ b/arch/arm/mach-pxa/spitz_pm.c
> @@ -212,8 +212,6 @@ struct sharpsl_charger_machinfo spitz_pm_machinfo = {
> ? ? ? ?.should_wakeup ? ?= spitz_should_wakeup,
> ?#if defined(CONFIG_LCD_CORGI)
> ? ? ? ?.backlight_limit = corgi_lcd_limit_intensity,
> -#elif defined(CONFIG_BACKLIGHT_CORGI)
> - ? ? ? .backlight_limit ?= corgibl_limit_intensity,
> ?#endif
> ? ? ? ?.charge_on_volt ? = SHARPSL_CHARGE_ON_VOLT,
> ? ? ? ?.charge_on_temp ? = SHARPSL_CHARGE_ON_TEMP,
> --
> 1.7.0.4
>
>


From lamiaposta71 at gmail.com  Wed Jun 30 04:52:30 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Wed, 30 Jun 2010 10:52:30 +0200
Subject: [PATCH] ASoC: DaVinci: Added support for cpu clocking I2S
In-Reply-To: <4C28F3D1.5060806@boundarydevices.com>
References: <1277707487-3371-1-git-send-email-lamiaposta71@gmail.com>
	<4C28F3D1.5060806@boundarydevices.com>
Message-ID: <AANLkTikhqZRWYoNnZ2PSnVVpV0rUqQQyRxfz99a25EMU@mail.gmail.com>

2010/6/28 Troy Kisky <troy.kisky at boundarydevices.com>

> Raffaele Recalcati wrote:
> > +             if (dev->i2s_fast_clock) {
> > +                     clk_div = 256;
> can you have
>   f = (freq / params->rate_num) * params->rate_den;
> > +                     do {
> > +                             framesize = (freq / (--clk_div)) /
> > +                                         params->rate_num *
> > +                                         params->rate_den;
> and
>                                framesize = f / (--clk_div);
> > +                     } while (((framesize < 33) || (framesize > 4095))
> &&
> > +                              (clk_div));
> > +                     clk_div--;
> looks like clk_div can go negative here, should the above while say
> (clk_div > 1)
>

> +                     } while (((framesize < 33) || (framesize > 4095)) &&
> +                              (clk_div));

only if clk_div not null stay inside the while.

> +                     clk_div--;

and here can at minumum be 0, not negative.



> > +                     srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1);
> > +             } else {
> > +                     /* symmetric waveforms */
> > +                     clk_div = freq / (mcbsp_word_length * 16) /
> > +                               params->rate_num * params->rate_den;
> > +                     srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length *
> > +                                                     16 - 1);
> > +             }
> > +             clk_div &= 0xFF;
> > +             srgr |= clk_div;
>


so, dividing for (CLKGDV + 1) it is ok.

Raffaele
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From lamiaposta71 at gmail.com  Wed Jun 30 06:00:45 2010
From: lamiaposta71 at gmail.com (Raffaele Recalcati)
Date: Wed, 30 Jun 2010 12:00:45 +0200
Subject: [PATCH] ASoC: DaVinci: Added support for cpu clocking I2S
In-Reply-To: <AANLkTimedG3X-rQbZvS6QfxUGkPIAtCgliI0xWknmNA9@mail.gmail.com>
References: <1277707487-3371-1-git-send-email-lamiaposta71@gmail.com>
	<20100628103030.GB14247@rakim.wolfsonmicro.main>
	<AANLkTimedG3X-rQbZvS6QfxUGkPIAtCgliI0xWknmNA9@mail.gmail.com>
Message-ID: <AANLkTilqE9E2lFwCKu5hx0EYZajIWubM7Qzf_n3vQfLq@mail.gmail.com>

> The freq problem is describe here below, but it is not clear to me:
>
> From *TMS320DM36x DMSoC Multichannel Buffered Serial Port User's Guide
> (Rev. A) <http://www.ti.com/litv/pdf/sprufi3a>*
> 2.5.3 Data Clock Generation
> When the receive/transmit clock mode is set to 1 (CLK(R/X)M = 1 in the pin
> control register (PCR)), the
> data clocks (CLK(R/X)) are driven by the internal sample rate generator
> output clock, CLKG. You can
> select for the receiver and transmitter from a variety of data bit clocks
> including:
> ? The input clock to the sample rate generator, which can be either the
> internal clock source or a
> dedicated external clock source via the MCBSP_CLKX, MCBSP_CLKR, or
> MCBSP_CLKS pins. The
> McBSP internal clock is the CPU/6 clock. See Section 2.5.3.1 for details on
> the source of the McBSP
> internal clock.
> ? The input clock source (internal clock source or external clock
> MCBSP_CLKX/MCBSP_CLKR/MCBSP_CLKS) to the sample rate generator can be
> divided-down by a
> programmable value (CLKGDV bit in the sample rate generator register
> (SRGR)) to drive CLKG.
> Regardless of the source to the sample rate generator, the rising edge of
> CLKSRG (see Figure 5)
> generates CLKG and FSG.
>
> CPU/6 is not clear.
>


Reading better the documentation the point seems now clear.
We have pllc1 sysclk4 that is the clock of McBSP peripheral.
And so it was abviously this frequency to be used when McBSP has to generate
the clock.
Sorry..

Raffaele
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From siccegge at cs.fau.de  Wed Jun 30 11:53:01 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 17:53:01 +0200
Subject: [PATCH 00/33] Removing dead code
Message-ID: <cover.1277911345.git.siccegge@cs.fau.de>

Hi all!

        As part of the VAMOS[0] research project at the University of
Erlangen we are looking at multiple integrity errors in linux'
configuration system.

	I've been running a check on the arch/arm sourcetree for
config Items not defined in Kconfig and found 33 such cases. Sourcecode
blocks depending on these Items are not reachable from a vanilla
kernel -- dead code. I've seen such dead blocks made on purpose
e.g. while integrating new features into the kernel but generally
they're just useless.

	Each of the patches in this patchset removes on such dead
config Item, I'd be glad if you consider applying them. I've been
doing deeper analysis of such issues before and can do so again but
I'm not so sure they were fastly usefull. Unfortunately arm doesn't
allow some allyesconfig build covering all of that code so I couldn't
build-test all of them, sorry for that.

        Please keep me informed of this patch getting confirmed /
merged so we can keep track of it.

Regards

        Christoph Egger

[0] http://vamos1.informatik.uni-erlangen.de/

Christoph Egger (33):
  Removing dead MTD_NAND_AT91_BUSWIDTH_16
  Removing dead ARCH_DAVINCI_TNETV107X
  Removing dead OMAP_MUX_ERRORS
  Removing dead MSM7X00A_IDLE
  Removing dead OMAP_IR
  Removing dead SHARPSL_LOCOMO
  Removing dead CPU_S3C2400
  Removing dead SA1101
  Removing dead MAGICV
  Removing dead VIDEO_AT91_ISI
  Removing dead OMAP_DSP
  Removing dead OMAP_STI
  Replacing LEDS_OMAP_DEBUG with OMAP_DEBUG_LEDS
  Removing dead SDMA_IRAM
  Removing dead PROCESSOR_NS9750
  Removing dead APM
  Removing dead SX1_OLD_FLASH
  Removing dead OMAP_ARM_96MHZ
  Removing dead MACH_OMAP_H4_OTG
  Removing dead MACH_OMAP2_H4_USB1
  Removing dead OMAP2_VENC_OUT_TYPE_SVIDEO,
    OMAP2_VENC_OUT_TYPE_COMPOSITE
  Removing dead MPU_{BRIDGE,TESLA}_IOMMU
  Removing dead BACKLIGHT_CORGI
  Removing dead ARCH_GUMSTIX_ORIG
  Removing dead CORGI_SSP_DEPRECATED
  Removing dead XSCALE_CACHE_ERRATA
  Removing dead IDE_PXA_CF
  Removing dead CPU_S3C24XX
  Removing dead SND_SOC_SMDK2443_WM9710
  Removing dead S3C_DEV_ADC
  Removing dead MACH_U300_BS26
  Removing dead CPU_ICACHE_STREAMING_DISABLE
  Removing dead MACH_U300_USE_I2S_AS_MASTER

 arch/arm/mach-at91/at572d940hf_devices.c       |   73 --
 arch/arm/mach-at91/at91sam9263_devices.c       |   49 --
 arch/arm/mach-at91/board-at572d940hf_ek.c      |    4 -
 arch/arm/mach-at91/board-sam9m10g45ek.c        |    4 -
 arch/arm/mach-davinci/include/mach/cputype.h   |    6 -
 arch/arm/mach-msm/idle.S                       |   13 -
 arch/arm/mach-ns9xxx/gpio.c                    |    8 -
 arch/arm/mach-omap1/board-h2.c                 |   18 -
 arch/arm/mach-omap1/board-nokia770.c           |  132 ----
 arch/arm/mach-omap1/board-palmte.c             |   84 ---
 arch/arm/mach-omap1/board-sx1.c                |   26 -
 arch/arm/mach-omap1/devices.c                  |   72 --
 arch/arm/mach-omap1/mcbsp.c                    |    3 -
 arch/arm/mach-omap1/mux.c                      |    5 -
 arch/arm/mach-omap1/opp_data.c                 |    3 -
 arch/arm/mach-omap2/board-h4.c                 |   26 -
 arch/arm/mach-omap2/board-omap3stalker.c       |    5 -
 arch/arm/mach-omap2/devices.c                  |   57 --
 arch/arm/mach-omap2/omap-iommu.c               |   22 -
 arch/arm/mach-pxa/corgi_pm.c                   |    2 -
 arch/arm/mach-pxa/include/mach/gumstix.h       |   12 +-
 arch/arm/mach-pxa/sharpsl_pm.c                 |   20 -
 arch/arm/mach-pxa/sleep.S                      |    7 -
 arch/arm/mach-pxa/spitz_pm.c                   |    2 -
 arch/arm/mach-pxa/trizeps4.c                   |    6 +-
 arch/arm/mach-s3c2410/include/mach/gpio-fns.h  |    5 -
 arch/arm/mach-s3c2410/include/mach/gpio.h      |    4 -
 arch/arm/mach-s3c2410/include/mach/regs-gpio.h |    4 -
 arch/arm/mach-s3c2443/mach-smdk2443.c          |    7 -
 arch/arm/mach-s5pv210/cpu.c                    |    4 -
 arch/arm/mach-sa1100/include/mach/SA-1101.h    |  925 ------------------------
 arch/arm/mach-sa1100/include/mach/hardware.h   |    4 -
 arch/arm/mach-sa1100/include/mach/irqs.h       |    2 -
 arch/arm/mach-u300/clock.c                     |   91 ---
 arch/arm/mach-u300/core.c                      |    7 -
 arch/arm/mm/proc-arm925.S                      |    3 -
 arch/arm/plat-mxc/include/mach/mx51.h          |    4 -
 arch/arm/plat-omap/Kconfig                     |    2 +-
 arch/arm/plat-omap/debug-leds.c                |    2 +-
 arch/arm/plat-omap/devices.c                   |   62 --
 arch/arm/plat-omap/include/plat/dsp_common.h   |   40 -
 arch/arm/plat-s3c24xx/cpu.c                    |   15 -
 arch/arm/plat-s3c24xx/include/plat/s3c2400.h   |   31 -
 43 files changed, 4 insertions(+), 1867 deletions(-)
 delete mode 100644 arch/arm/mach-sa1100/include/mach/SA-1101.h
 delete mode 100644 arch/arm/plat-omap/include/plat/dsp_common.h
 delete mode 100644 arch/arm/plat-s3c24xx/include/plat/s3c2400.h



From siccegge at cs.fau.de  Wed Jun 30 11:55:22 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 15:55:22 +0000
Subject: [PATCH] Removing dead OMAP_IR
Message-ID: <mailman.62.1278317711.27306.linux-arm-kernel@lists.infradead.org>

OMAP_IR doesn't exist in Kconfig, therefore removing all references
for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
[tony at atomide.com: updated for new mux code]
Signed-off-by: Tony Lindgren <tony at atomide.com>

diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index ee46974..2efa427 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -292,15 +292,6 @@ static struct platform_device h2_kp_device = {
 
 #define H2_IRDA_FIRSEL_GPIO_PIN	17
 
-#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
-static int h2_transceiver_mode(struct device *dev, int state)
-{
-	/* SIR when low, else MIR/FIR when HIGH */
-	gpio_set_value(H2_IRDA_FIRSEL_GPIO_PIN, !(state & IR_SIRMODE));
-	return 0;
-}
-#endif
-
 static struct omap_irda_config h2_irda_data = {
 	.transceiver_cap	= IR_SIRMODE | IR_MIRMODE | IR_FIRMODE,
 	.rx_channel		= OMAP_DMA_UART3_RX,
@@ -450,15 +441,6 @@ static void __init h2_init(void)
 	omap_cfg_reg(E19_1610_KBR4);
 	omap_cfg_reg(N19_1610_KBR5);
 
-	/* Irda */
-#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
-	omap_writel(omap_readl(FUNC_MUX_CTRL_A) | 7, FUNC_MUX_CTRL_A);
-	if (gpio_request(H2_IRDA_FIRSEL_GPIO_PIN, "IRDA mode") < 0)
-		BUG();
-	gpio_direction_output(H2_IRDA_FIRSEL_GPIO_PIN, 0);
-	h2_irda_data.transceiver_mode = h2_transceiver_mode;
-#endif
-
 	platform_add_devices(h2_devices, ARRAY_SIZE(h2_devices));
 	omap_board_config = h2_config;
 	omap_board_config_size = ARRAY_SIZE(h2_config);
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 2d9ff0f..9044dcf 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -356,10 +356,6 @@ static void __init omap_h4_init(void)
 	 * You have to mux them off in device drivers later on
 	 * if not needed.
 	 */
-#if defined(CONFIG_OMAP_IR) || defined(CONFIG_OMAP_IR_MODULE)
-	omap_mux_init_signal("uart3_tx_irtx.uart3_tx_irtx", 0);
-	omap_mux_init_signal("uart3_rx_irrx.uart3_rx_irrx", 0);
-#endif
 
 #if defined(CONFIG_KEYBOARD_OMAP) || defined(CONFIG_KEYBOARD_OMAP_MODULE)
 	omap_mux_init_gpio(88, OMAP_PULL_ENA | OMAP_PULL_UP);

--6TrnltStXW4iwmi0--


From siccegge at cs.fau.de  Wed Jun 30 11:57:26 2010
From: siccegge at cs.fau.de (Christoph Egger)
Date: Wed, 30 Jun 2010 15:57:26 +0000
Subject: [PATCH] Removing dead OMAP_DSP
Message-ID: <mailman.63.1278318071.27306.linux-arm-kernel@lists.infradead.org>

OMAP_DSP doesn't exist in Kconfig, therefore removing all
references for it from the source code.

Signed-off-by: Christoph Egger <siccegge at cs.fau.de>
[tony at atomide.com: updated to apply on top of already queued patches]
Signed-off-by: Tony Lindgren <tony at atomide.com>

diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index c9e9e37..5a7b638 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -242,138 +242,6 @@ static inline void nokia770_mmc_init(void)
 }
 #endif
 
-#if	defined(CONFIG_OMAP_DSP)
-/*
- * audio power control
- */
-#define	HEADPHONE_GPIO		14
-#define	AMPLIFIER_CTRL_GPIO	58
-
-static struct clk *dspxor_ck;
-static DEFINE_MUTEX(audio_pwr_lock);
-/*
- * audio_pwr_state
- * +--+-------------------------+---------------------------------------+
- * |-1|down			|power-up request -> 0			|
- * +--+-------------------------+---------------------------------------+
- * | 0|up			|power-down(1) request -> 1		|
- * |  |				|power-down(2) request -> (ignore)	|
- * +--+-------------------------+---------------------------------------+
- * | 1|up,			|power-up request -> 0			|
- * |  |received down(1) request	|power-down(2) request -> -1		|
- * +--+-------------------------+---------------------------------------+
- */
-static int audio_pwr_state = -1;
-
-static inline void aic23_power_up(void)
-{
-}
-static inline void aic23_power_down(void)
-{
-}
-
-/*
- * audio_pwr_up / down should be called under audio_pwr_lock
- */
-static void nokia770_audio_pwr_up(void)
-{
-	clk_enable(dspxor_ck);
-
-	/* Turn on codec */
-	aic23_power_up();
-
-	if (gpio_get_value(HEADPHONE_GPIO))
-		/* HP not connected, turn on amplifier */
-		gpio_set_value(AMPLIFIER_CTRL_GPIO, 1);
-	else
-		/* HP connected, do not turn on amplifier */
-		printk("HP connected\n");
-}
-
-static void codec_delayed_power_down(struct work_struct *work)
-{
-	mutex_lock(&audio_pwr_lock);
-	if (audio_pwr_state == -1)
-		aic23_power_down();
-	clk_disable(dspxor_ck);
-	mutex_unlock(&audio_pwr_lock);
-}
-
-static DECLARE_DELAYED_WORK(codec_power_down_work, codec_delayed_power_down);
-
-static void nokia770_audio_pwr_down(void)
-{
-	/* Turn off amplifier */
-	gpio_set_value(AMPLIFIER_CTRL_GPIO, 0);
-
-	/* Turn off codec: schedule delayed work */
-	schedule_delayed_work(&codec_power_down_work, HZ / 20);	/* 50ms */
-}
-
-static int
-nokia770_audio_pwr_up_request(struct dsp_kfunc_device *kdev, int stage)
-{
-	mutex_lock(&audio_pwr_lock);
-	if (audio_pwr_state == -1)
-		nokia770_audio_pwr_up();
-	/* force audio_pwr_state = 0, even if it was 1. */
-	audio_pwr_state = 0;
-	mutex_unlock(&audio_pwr_lock);
-	return 0;
-}
-
-static int
-nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage)
-{
-	mutex_lock(&audio_pwr_lock);
-	switch (stage) {
-	case 1:
-		if (audio_pwr_state == 0)
-			audio_pwr_state = 1;
-		break;
-	case 2:
-		if (audio_pwr_state == 1) {
-			nokia770_audio_pwr_down();
-			audio_pwr_state = -1;
-		}
-		break;
-	}
-	mutex_unlock(&audio_pwr_lock);
-	return 0;
-}
-
-static struct dsp_kfunc_device nokia770_audio_device = {
-	.name	 = "audio",
-	.type	 = DSP_KFUNC_DEV_TYPE_AUDIO,
-	.enable  = nokia770_audio_pwr_up_request,
-	.disable = nokia770_audio_pwr_down_request,
-};
-
-static __init int omap_dsp_init(void)
-{
-	int ret;
-
-	dspxor_ck = clk_get(0, "dspxor_ck");
-	if (IS_ERR(dspxor_ck)) {
-		printk(KERN_ERR "couldn't acquire dspxor_ck\n");
-		return PTR_ERR(dspxor_ck);
-	}
-
-	ret = dsp_kfunc_device_register(&nokia770_audio_device);
-	if (ret) {
-		printk(KERN_ERR
-		       "KFUNC device registration faild: %s\n",
-		       nokia770_audio_device.name);
-		goto out;
-	}
-	return 0;
- out:
-	return ret;
-}
-#else
-#define omap_dsp_init()		do {} while (0)
-#endif	/* CONFIG_OMAP_DSP */
-
 static void __init omap_nokia770_init(void)
 {
 	platform_add_devices(nokia770_devices, ARRAY_SIZE(nokia770_devices));
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 379100c..c00d602 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -63,44 +63,7 @@ static void omap_init_rtc(void)
 static inline void omap_init_rtc(void) {}
 #endif
 
-#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
-
-#if defined(CONFIG_ARCH_OMAP15XX)
-#  define OMAP1_MBOX_SIZE	0x23
-#  define INT_DSP_MAILBOX1	INT_1510_DSP_MAILBOX1
-#elif defined(CONFIG_ARCH_OMAP16XX)
-#  define OMAP1_MBOX_SIZE	0x2f
-#  define INT_DSP_MAILBOX1	INT_1610_DSP_MAILBOX1
-#endif
-
-#define OMAP1_MBOX_BASE		OMAP16XX_MAILBOX_BASE
-
-static struct resource mbox_resources[] = {
-	{
-		.start		= OMAP1_MBOX_BASE,
-		.end		= OMAP1_MBOX_BASE + OMAP1_MBOX_SIZE,
-		.flags		= IORESOURCE_MEM,
-	},
-	{
-		.start		= INT_DSP_MAILBOX1,
-		.flags		= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device mbox_device = {
-	.name		= "omap1-mailbox",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(mbox_resources),
-	.resource	= mbox_resources,
-};
-
-static inline void omap_init_mbox(void)
-{
-	platform_device_register(&mbox_device);
-}
-#else
 static inline void omap_init_mbox(void) { }
-#endif
 
 /*-------------------------------------------------------------------------*/
 
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index e9bdff1..b3a796a 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -23,7 +23,6 @@
 #include <plat/mux.h>
 #include <plat/cpu.h>
 #include <plat/mcbsp.h>
-#include <plat/dsp_common.h>
 
 #define DPS_RSTCT2_PER_EN	(1 << 0)
 #define DSP_RSTCT2_WD_PER_EN	(1 << 1)
@@ -46,7 +45,6 @@ static void omap1_mcbsp_request(unsigned int id)
 				clk_enable(api_clk);
 				clk_enable(dsp_clk);
 
-				omap_dsp_request_mem();
 				/*
 				 * DSP external peripheral reset
 				 * FIXME: This should be moved to dsp code
@@ -62,7 +60,6 @@ static void omap1_mcbsp_free(unsigned int id)
 {
 	if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
 		if (--dsp_use == 0) {
-			omap_dsp_release_mem();
 			if (!IS_ERR(api_clk)) {
 				clk_disable(api_clk);
 				clk_put(api_clk);
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index ca5b229..9d5466d 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -30,67 +30,6 @@
 #include <plat/dsp_common.h>
 #include <plat/omap44xx.h>
 
-#if	defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
-
-static struct dsp_platform_data dsp_pdata = {
-	.kdev_list = LIST_HEAD_INIT(dsp_pdata.kdev_list),
-};
-
-static struct resource omap_dsp_resources[] = {
-	{
-		.name	= "dsp_mmu",
-		.start	= -1,
-		.flags	= IORESOURCE_IRQ,
-	},
-};
-
-static struct platform_device omap_dsp_device = {
-	.name		= "dsp",
-	.id		= -1,
-	.num_resources	= ARRAY_SIZE(omap_dsp_resources),
-	.resource	= omap_dsp_resources,
-	.dev = {
-		.platform_data = &dsp_pdata,
-	},
-};
-
-static inline void omap_init_dsp(void)
-{
-	struct resource *res;
-	int irq;
-
-	if (cpu_is_omap15xx())
-		irq = INT_1510_DSP_MMU;
-	else if (cpu_is_omap16xx())
-		irq = INT_1610_DSP_MMU;
-	else if (cpu_is_omap24xx())
-		irq = INT_24XX_DSP_MMU;
-
-	res = platform_get_resource_byname(&omap_dsp_device,
-					   IORESOURCE_IRQ, "dsp_mmu");
-	res->start = irq;
-
-	platform_device_register(&omap_dsp_device);
-}
-
-int dsp_kfunc_device_register(struct dsp_kfunc_device *kdev)
-{
-	static DEFINE_MUTEX(dsp_pdata_lock);
-
-	spin_lock_init(&kdev->lock);
-
-	mutex_lock(&dsp_pdata_lock);
-	list_add_tail(&kdev->entry, &dsp_pdata.kdev_list);
-	mutex_unlock(&dsp_pdata_lock);
-
-	return 0;
-}
-EXPORT_SYMBOL(dsp_kfunc_device_register);
-
-#else
-static inline void omap_init_dsp(void) { }
-#endif	/* CONFIG_OMAP_DSP */
-
 /*-------------------------------------------------------------------------*/
 
 #if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
@@ -359,7 +298,6 @@ static int __init omap_init_devices(void)
 	/* please keep these calls, and their implementations above,
 	 * in alphabetical order so they're easier to sort through.
 	 */
-	omap_init_dsp();
 	omap_init_rng();
 	omap_init_mcpdm();
 	omap_init_uwire();
diff --git a/arch/arm/plat-omap/include/plat/dsp_common.h b/arch/arm/plat-omap/include/plat/dsp_common.h
deleted file mode 100644
index da97736..0000000
--- a/arch/arm/plat-omap/include/plat/dsp_common.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of OMAP DSP driver (DSP Gateway version 3.3.1)
- *
- * Copyright (C) 2004-2006 Nokia Corporation. All rights reserved.
- *
- * Contact: Toshihiro Kobayashi <toshihiro.kobayashi at nokia.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
- */
-
-#ifndef ASM_ARCH_DSP_COMMON_H
-#define ASM_ARCH_DSP_COMMON_H
-
-#if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_OMAP_MMU_FWK)
-extern void omap_dsp_request_mpui(void);
-extern void omap_dsp_release_mpui(void);
-extern int omap_dsp_request_mem(void);
-extern int omap_dsp_release_mem(void);
-#else
-static inline int omap_dsp_request_mem(void)
-{
-	return 0;
-}
-#define omap_dsp_release_mem()	do {} while (0)
-#endif
-
-#endif /* ASM_ARCH_DSP_COMMON_H */

--wzJLGUyc3ArbnUjN--


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.67.1278928723.27306.linux-arm-kernel@lists.infradead.org>

SMDKC110 # bdinfo
arch_number =3D 0x00000891
env_t       =3D 0x00000000
boot_params =3D 0x20000100
DRAM bank   =3D 0x00000000
-> start    =3D 0x20000000
-> size     =3D 0x05000000
DRAM bank   =3D 0x00000001
-> start    =3D 0x40000000
-> size     =3D 0x10000000
DRAM bank   =3D 0x00000002
-> start    =3D 0x50000000
-> size     =3D 0x08000000


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.68.1278928723.27306.linux-arm-kernel@lists.infradead.org>

SMDKC110 # bootm c0008000
Boot with zImage

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Linux version 2.6.35-rc4-00008-g98c749c (kgene at starstone) (gcc version =
4.4.1
(Sourcery G++ Lite 2009q3-67) ) #1 PREEMPT Mon Jul 12 18:47:04 KST 2010
CPU: ARMv7 Processor [412fc082] revision 2 (ARMv7), cr=3D10c53c7f
CPU: VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
Machine: SMDKC110
...
Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
Memory: 80MB 256MB 128MB =3D 464MB total
Memory: 459616k/459616k available, 15520k reserved, 0K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    DMA     : 0xff000000 - 0xffe00000   (  14 MB)
    vmalloc : 0xb8800000 - 0xe0000000   ( 632 MB)
    lowmem  : 0x80000000 - 0xb8000000   ( 896 MB)
    modules : 0x7f000000 - 0x80000000   (  16 MB)
      .init : 0x80008000 - 0x8001e000   (  88 kB)
      .text : 0x8001e000 - 0x801be000   (1664 kB)
      .data : 0x801ce000 - 0x801e6600   (  98 kB)
SLUB: Genslabs=3D9, HWalign=3D64, Order=3D0-3, MinObjects=3D0, CPUs=3D1, =
Nodes=3D1
Hierarchical RCU implementation.
        RCU-based detection of stalled CPUs is disabled.
        Verbose stalled-CPUs detection is disabled.
...

And SECTION_SIZE_BITS is 28, not 27.

> Thank you,
> Kyungmin Park
>=20
> On Mon, Jul 12, 2010 at 5:32 PM, Kukjin Kim <kgene.kim at samsung.com> =
wrote:
> > Russell,
> >
> > Hi,
> >
> > Kukjin Kim wrote:
> >> Russell wrote:
> >> > So, memory starts at 0x20000000 and finishes at 0x25000000. =
=A0That's
> > fine.
> >> > That doesn't mean the section size is 16MB.
> >> >
> >> > As I've already said, the section size has _nothing_ what so ever =
to
do
> >> > with the size of memory, or the granularity of the size of =
memory.
=A0By
> >> > way of illustration, it is perfectly legal to have a section size =
of
> >> > 256MB but only have 1MB in a section and this is perfectly legal. =
=A0So
> >> > sections do not have to be completely filled.
> >> >
> >> Actually, as you know, the hole's area of mem_map is freed from =
bootmem
if
> > a
> >> section has a hole when initializing sparse memory.
> >>
> >> I identified that a section doesn't need to be a contiguous area of
> > physical
> >> memory when reading your comment with the fact that the mem_map of =
a
> > section
> >> can be smaller than the size of a section.
> >>
> >> I found, however, the kernel panics when modifying min_free_kbytes =
file
in
> >> the proc filesystem if a section has a hole.
> >>
> >> While processing the change of min_free_kbytes in the kernel, page
> >> descriptors in a hole of an online section is accessed.
> >
> > As I said, following error happens.
> > It would be helpful to me if any opinions or comments.
> >
> > ---


(snip)


Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.



From sundar.iyer at stericsson.com  Sun Jun  6 09:46:03 2010
From: sundar.iyer at stericsson.com (Sundar R Iyer)
Date: Sun, 6 Jun 2010 19:16:03 +0530
Subject: [PATCH v3 2/2] ux500: add ab8500-regulators machine specific data
Message-ID: <mailman.73.1279037640.27306.linux-arm-kernel@lists.infradead.org>

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Acked-by: Bengt JONSSON <bengt.g.jonsson at stericsson.com>
Signed-off-by: Sundar R Iyer <sundar.iyer at stericsson.com>
---
CHANGELOG

v2 -> v3 
 - Empty the regulator_consumer_supply since there is no actual
   device to supply

v1 -> v2
 - Removed NULL device reference

 arch/arm/mach-ux500/Makefile                  |    1 +
 arch/arm/mach-ux500/board-mop500-regulators.c |  179 +++++++++++++++++++++++++
 2 files changed, 180 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-ux500/board-mop500-regulators.c

diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index 0753a69..311f996 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_LOCAL_TIMERS)	+= localtimer.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
 obj-$(CONFIG_CPU_FREQ)		+= cpufreq.o
 obj-$(CONFIG_AB8500_PRCMU_I2C)	+= ab8500-prcmu-i2c.o
+obj-$(CONFIG_REGULATOR_AB8500)	+= board-mop500-regulators.o
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
new file mode 100644
index 0000000..08bc966
--- /dev/null
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * Author: Sundar Iyer <sundar.iyer at stericsson.com> for ST-Ericsson
+ *
+ * MOP500 board specific initialization for regulators
+ */
+#include <linux/kernel.h>
+#include <linux/regulator/machine.h>
+
+static struct regulator_consumer_supply ab8500_vaux1_consumers[] = {
+};
+
+struct regulator_init_data ab8500_vaux1_regulator = {
+	.supply_regulator_dev = NULL,
+	.constraints = {
+		.name = "ab8500-vaux1",
+		.min_uV = 1100000,
+		.max_uV = 3300000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+					REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers),
+	.consumer_supplies = ab8500_vaux1_consumers,
+};
+
+static struct regulator_consumer_supply ab8500_vaux2_consumers[] = {
+};
+
+struct regulator_init_data ab8500_vaux2_regulator = {
+	.supply_regulator_dev = NULL,
+	.constraints = {
+		.name = "ab8500-vaux2",
+		.min_uV = 1100000,
+		.max_uV = 3300000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+					REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(ab8500_vaux2_consumers),
+	.consumer_supplies = ab8500_vaux2_consumers,
+};
+
+static struct regulator_consumer_supply ab8500_vaux3_consumers[] = {
+};
+
+struct regulator_init_data ab8500_vaux3_regulator = {
+	.supply_regulator_dev = NULL,
+	.constraints = {
+		.name = "ab8500-vaux3",
+		.min_uV = 1100000,
+		.max_uV = 3300000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+					REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(ab8500_vaux3_consumers),
+	.consumer_supplies = ab8500_vaux3_consumers,
+};
+
+/* supply for tvout, gpadc, TVOUT LDO */
+static struct regulator_consumer_supply ab8500_vtvout_consumers[] = {
+};
+
+struct regulator_init_data ab8500_vtvout_init = {
+	.supply_regulator_dev = NULL,
+	.constraints = {
+		.name = "ab8500-vtvout",
+		.min_uV = 1900000,
+		.max_uV = 2100000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+					REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(ab8500_vtvout_consumers),
+	.consumer_supplies = ab8500_vtvout_consumers,
+};
+
+/* supply for ab8500-vaudio, VAUDIO LDO */
+static struct regulator_consumer_supply ab8500_vaudio_consumers[] = {
+};
+
+struct regulator_init_data ab8500_vaudio_init = {
+	.supply_regulator_dev = NULL,
+	.constraints = {
+		.name = "ab8500-vaudio",
+		.min_uV = 1925000,
+		.max_uV = 2075000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+					REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(ab8500_vaudio_consumers),
+	.consumer_supplies = ab8500_vaudio_consumers,
+};
+
+/* supply for v-anamic1 VAMic1-LDO */
+static struct regulator_consumer_supply ab8500_vamic1_consumers[] = {
+};
+
+struct regulator_init_data ab8500_vamic1_init = {
+	.supply_regulator_dev = NULL,
+	.constraints = {
+		.name = "ab8500-vamic1",
+		.min_uV = 2000000,
+		.max_uV = 2100000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+					REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(ab8500_vamic1_consumers),
+	.consumer_supplies = ab8500_vamic1_consumers,
+};
+
+/* supply for v-amic2, VAMIC2 LDO*/
+static struct regulator_consumer_supply ab8500_vamic2_consumers[] = {
+};
+
+struct regulator_init_data ab8500_vamic2_init = {
+	.supply_regulator_dev = NULL,
+	.constraints = {
+		.name = "ab8500-vamic2",
+		.min_uV = 2000000,
+		.max_uV = 2100000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+					REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(ab8500_vamic2_consumers),
+	.consumer_supplies = ab8500_vamic2_consumers,
+};
+
+/* supply for v-dmic, VDMIC LDO */
+static struct regulator_consumer_supply ab8500_vdmic_consumers[] = {
+};
+
+struct regulator_init_data ab8500_vdmic_init = {
+	.supply_regulator_dev = NULL,
+	.constraints = {
+		.name = "ab8500-vdmic",
+		.min_uV = 1700000,
+		.max_uV = 1950000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+					REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(ab8500_vdmic_consumers),
+	.consumer_supplies = ab8500_vdmic_consumers,
+};
+
+/* supply for v-intcore12, VINTCORE12 LDO */
+static struct regulator_consumer_supply ab8500_vintcore_consumers[] = {
+};
+
+struct regulator_init_data ab8500_vintcore_init = {
+	.supply_regulator_dev = NULL,
+	.constraints = {
+		.name = "ab8500-vintcore",
+		.min_uV = 1200000,
+		.max_uV = 1350000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+					REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(ab8500_vintcore_consumers),
+	.consumer_supplies = ab8500_vintcore_consumers,
+};
+
+/* supply for U8500 CSI/DSI, VANA LDO */
+static struct regulator_consumer_supply ab8500_vana_consumers[] = {
+};
+
+struct regulator_init_data ab8500_vana_init = {
+	.supply_regulator_dev = NULL,
+	.constraints = {
+		.name = "ab8500-vana",
+		.min_uV = 0,
+		.max_uV = 1200000,
+		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE|
+					REGULATOR_CHANGE_STATUS,
+	},
+	.num_consumer_supplies = ARRAY_SIZE(ab8500_vana_consumers),
+	.consumer_supplies = ab8500_vana_consumers,
+};
+
-- 
1.7.0



From sundar.iyer at stericsson.com  Sun Jun  6 09:42:12 2010
From: sundar.iyer at stericsson.com (Sundar R Iyer)
Date: Sun, 6 Jun 2010 19:12:12 +0530
Subject: [PATCH v3 1/2] regulator: add support for regulators on the ab8500 MFD
Message-ID: <mailman.74.1279037956.27306.linux-arm-kernel@lists.infradead.org>

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Acked-by: Bengt JONSSON <bengt.g.jonsson at stericsson.com>
Signed-off-by: Sundar R Iyer <sundar.iyer at stericsson.com>
---
CHANGELOG

v2 -> v3
 - replaced dev_dbg calls with dev_err.

v1 -> v2
 - Fixed comments from Mark

 drivers/regulator/Kconfig  |    8 +
 drivers/regulator/Makefile |    1 +
 drivers/regulator/ab8500.c |  427 ++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 436 insertions(+), 0 deletions(-)
 create mode 100644 drivers/regulator/ab8500.c

diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 7cd8a29..6c14afd 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -221,5 +221,13 @@ config REGULATOR_AD5398
 	help
 	  This driver supports AD5398 and AD5821 current regulator chips.
 	  If building into module, its name is ad5398.ko.
+
+config REGULATOR_AB8500
+	bool "ST-Ericsson AB8500 Power Regulators"
+	depends on AB8500_CORE
+	help
+	  This driver supports the regulators found on the ST-Ericsson mixed
+	  signal AB8500 PMIC
+
 endif
 
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index 74a4638..fc696c5 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -34,5 +34,6 @@ obj-$(CONFIG_REGULATOR_TPS65023) += tps65023-regulator.o
 obj-$(CONFIG_REGULATOR_TPS6507X) += tps6507x-regulator.o
 obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
 obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
+obj-$(CONFIG_REGULATOR_AB8500)	+= ab8500.o
 
 ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/ab8500.c b/drivers/regulator/ab8500.c
new file mode 100644
index 0000000..dc3f1a4
--- /dev/null
+++ b/drivers/regulator/ab8500.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * Author: Sundar Iyer <sundar.iyer at stericsson.com> for ST-Ericsson
+ *
+ * AB8500 peripheral regulators
+ *
+ * AB8500 supports the following regulators,
+ * LDOs - VAUDIO, VANAMIC2/2, VDIGMIC, VINTCORE12, VTVOUT,
+ *        VAUX1/2/3, VANA
+ *
+ * for DB8500 cut 1.0 and previous versions of the silicon, all accesses
+ * to registers are through the DB8500 SPI. In cut 1.1 onwards, these
+ * accesses are through the DB8500 PRCMU I2C
+ *
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/ab8500.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/ab8500.h>
+
+/**
+ * struct ab8500_regulator_info - ab8500 regulator information
+ * @desc: regulator description
+ * @ab8500: ab8500 parent
+ * @regulator_dev: regulator device
+ * @max_uV: maximum voltage (for variable voltage supplies)
+ * @min_uV: minimum voltage (for variable voltage supplies)
+ * @fixed_uV: typical voltage (for fixed voltage supplies)
+ * @update_reg: register to control on/off
+ * @mask: mask to enable/disable regulator
+ * @enable: bits to enable the regulator in normal(high power) mode
+ * @voltage_reg: register to control regulator voltage
+ * @voltage_mask: mask to control regulator voltage
+ * @supported_voltages: supported voltage table
+ * @voltages_len: number of supported voltages for the regulator
+ */
+struct ab8500_regulator_info {
+	struct device		*dev;
+	struct regulator_desc	desc;
+	struct ab8500		*ab8500;
+	struct regulator_dev	*regulator;
+	int max_uV;
+	int min_uV;
+	int fixed_uV;
+	int update_reg;
+	int mask;
+	int enable;
+	int voltage_reg;
+	int voltage_mask;
+	int const *supported_voltages;
+	int voltages_len;
+};
+
+/* voltage tables for the vauxn/vintcore supplies */
+static const int ldo_vauxn_voltages[] = {
+	1100000,
+	1200000,
+	1300000,
+	1400000,
+	1500000,
+	1800000,
+	1850000,
+	1900000,
+	2500000,
+	2650000,
+	2700000,
+	2750000,
+	2800000,
+	2900000,
+	3000000,
+	3300000,
+};
+
+static const int ldo_vintcore_voltages[] = {
+	1200000,
+	1225000,
+	1250000,
+	1275000,
+	1300000,
+	1325000,
+	1350000,
+};
+
+static int ab8500_regulator_enable(struct regulator_dev *rdev)
+{
+	int regulator_id, ret;
+	struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
+
+	regulator_id = rdev_get_id(rdev);
+	if (regulator_id >= AB8500_NUM_REGULATORS)
+		return -EINVAL;
+
+	ret = ab8500_set_bits(info->ab8500, info->update_reg,
+			info->mask, info->enable);
+	if (ret < 0)
+		dev_err(rdev_get_dev(rdev),
+			"couldn't set enable bits for regulator\n");
+	return ret;
+}
+
+static int ab8500_regulator_disable(struct regulator_dev *rdev)
+{
+	int regulator_id, ret;
+	struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
+
+	regulator_id = rdev_get_id(rdev);
+	if (regulator_id >= AB8500_NUM_REGULATORS)
+		return -EINVAL;
+
+	ret = ab8500_set_bits(info->ab8500, info->update_reg,
+			info->mask, 0x0);
+	if (ret < 0)
+		dev_err(rdev_get_dev(rdev),
+			"couldn't set disable bits for regulator\n");
+	return ret;
+}
+
+static int ab8500_regulator_is_enabled(struct regulator_dev *rdev)
+{
+	int regulator_id, ret;
+	struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
+
+	regulator_id = rdev_get_id(rdev);
+	if (regulator_id >= AB8500_NUM_REGULATORS)
+		return -EINVAL;
+
+	ret = ab8500_read(info->ab8500, info->update_reg);
+	if (ret < 0) {
+		dev_err(rdev_get_dev(rdev),
+			"couldn't read 0x%x register\n", info->update_reg);
+		return ret;
+	}
+
+	if (ret & info->mask)
+		return true;
+	else
+		return false;
+}
+
+static int ab8500_list_voltage(struct regulator_dev *rdev, unsigned selector)
+{
+	int regulator_id;
+	struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
+
+	regulator_id = rdev_get_id(rdev);
+	if (regulator_id >= AB8500_NUM_REGULATORS)
+		return -EINVAL;
+
+	/* return the uV for the fixed regulators */
+	if (info->fixed_uV)
+		return info->fixed_uV;
+
+	if (selector > info->voltages_len)
+		return -EINVAL;
+
+	return info->supported_voltages[selector];
+}
+
+static int ab8500_regulator_get_voltage(struct regulator_dev *rdev)
+{
+	int regulator_id, ret, val;
+	struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
+
+	regulator_id = rdev_get_id(rdev);
+	if (regulator_id >= AB8500_NUM_REGULATORS)
+		return -EINVAL;
+
+	ret = ab8500_read(info->ab8500, info->voltage_reg);
+	if (ret < 0) {
+		dev_err(rdev_get_dev(rdev),
+			"couldn't read voltage reg for regulator\n");
+		return ret;
+	}
+
+	/* vintcore has a different layout */
+	val = ret & info->voltage_mask;
+	if (regulator_id == AB8500_LDO_INTCORE)
+		ret = info->supported_voltages[val >> 0x3];
+	else
+		ret = info->supported_voltages[val];
+
+	return ret;
+}
+
+static int ab8500_get_best_voltage_index(struct regulator_dev *rdev,
+		int min_uV, int max_uV)
+{
+	struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
+	int i;
+
+	/* check the supported voltage */
+	for (i = 0; i < info->voltages_len; i++) {
+		if ((info->supported_voltages[i] >= min_uV) &&
+		    (info->supported_voltages[i] <= max_uV))
+			return i;
+	}
+
+	return -EINVAL;
+}
+
+static int ab8500_regulator_set_voltage(struct regulator_dev *rdev,
+		int min_uV, int max_uV)
+{
+	int regulator_id, ret;
+	struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
+
+	regulator_id = rdev_get_id(rdev);
+	if (regulator_id >= AB8500_NUM_REGULATORS)
+		return -EINVAL;
+
+	/* get the appropriate voltages within the range */
+	ret = ab8500_get_best_voltage_index(rdev, min_uV, max_uV);
+	if (ret < 0) {
+		dev_err(rdev_get_dev(rdev),
+				"couldn't get best voltage for regulator\n");
+		return ret;
+	}
+
+	/* set the registers for the request */
+	ret = ab8500_set_bits(info->ab8500, info->voltage_reg,
+				info->voltage_mask, ret);
+	if (ret < 0)
+		dev_err(rdev_get_dev(rdev),
+		"couldn't set voltage reg for regulator\n");
+
+	return ret;
+}
+
+static struct regulator_ops ab8500_regulator_ops = {
+	.enable		= ab8500_regulator_enable,
+	.disable	= ab8500_regulator_disable,
+	.is_enabled	= ab8500_regulator_is_enabled,
+	.get_voltage	= ab8500_regulator_get_voltage,
+	.set_voltage	= ab8500_regulator_set_voltage,
+	.list_voltage	= ab8500_list_voltage,
+};
+
+static int ab8500_fixed_get_voltage(struct regulator_dev *rdev)
+{
+	int regulator_id;
+	struct ab8500_regulator_info *info = rdev_get_drvdata(rdev);
+
+	regulator_id = rdev_get_id(rdev);
+	if (regulator_id >= AB8500_NUM_REGULATORS)
+		return -EINVAL;
+
+	return info->fixed_uV;
+}
+
+static struct regulator_ops ab8500_ldo_fixed_ops = {
+	.enable		= ab8500_regulator_enable,
+	.disable	= ab8500_regulator_disable,
+	.is_enabled	= ab8500_regulator_is_enabled,
+	.get_voltage	= ab8500_fixed_get_voltage,
+	.list_voltage	= ab8500_list_voltage,
+};
+
+#define AB8500_LDO(_id, min, max, reg, reg_mask, reg_enable,	\
+		volt_reg, volt_mask, voltages,			\
+			len_volts)				\
+{								\
+	.desc	= {						\
+		.name	= "LDO-" #_id,				\
+		.ops	= &ab8500_regulator_ops,		\
+		.type	= REGULATOR_VOLTAGE,			\
+		.id	= AB8500_LDO_##_id,			\
+		.owner	= THIS_MODULE,				\
+	},							\
+	.min_uV		= (min) * 1000,				\
+	.max_uV		= (max) * 1000,				\
+	.update_reg	= reg,					\
+	.mask		= reg_mask,				\
+	.enable		= reg_enable,				\
+	.voltage_reg	= volt_reg,				\
+	.voltage_mask	= volt_mask,				\
+	.supported_voltages = voltages,				\
+	.voltages_len	= len_volts,				\
+	.fixed_uV	= 0,					\
+}
+
+#define AB8500_FIXED_LDO(_id, fixed, reg, reg_mask,	\
+				reg_enable)		\
+{							\
+	.desc	= {					\
+		.name	= "LDO-" #_id,			\
+		.ops	= &ab8500_ldo_fixed_ops,	\
+		.type	= REGULATOR_VOLTAGE,		\
+		.id	= AB8500_LDO_##_id,		\
+		.owner	= THIS_MODULE,			\
+	},						\
+	.fixed_uV	= fixed * 1000,			\
+	.update_reg	= reg,				\
+	.mask		= reg_mask,			\
+	.enable		= reg_enable,			\
+}
+
+static struct ab8500_regulator_info ab8500_regulator_info[] = {
+	/*
+	 * Variable Voltage LDOs
+	 * name, min uV, max uV, ctrl reg, reg mask, enable mask,
+	 *	volt ctrl reg, volt ctrl mask, volt table, num supported volts
+	 */
+	AB8500_LDO(AUX1, 1100, 3300, 0x0409, 0x3, 0x1, 0x041f, 0xf,
+			ldo_vauxn_voltages, ARRAY_SIZE(ldo_vauxn_voltages)),
+	AB8500_LDO(AUX2, 1100, 3300, 0x0409, 0xc, 0x4, 0x0420, 0xf,
+			ldo_vauxn_voltages, ARRAY_SIZE(ldo_vauxn_voltages)),
+	AB8500_LDO(AUX3, 1100, 3300, 0x040a, 0x3, 0x1, 0x0421, 0xf,
+			ldo_vauxn_voltages, ARRAY_SIZE(ldo_vauxn_voltages)),
+	AB8500_LDO(INTCORE, 1100, 3300, 0x0380, 0x4, 0x4, 0x0380, 0x38,
+		ldo_vintcore_voltages, ARRAY_SIZE(ldo_vintcore_voltages)),
+
+	/*
+	 * Fixed Voltage LDOs
+	 *		 name,	o/p uV, ctrl reg, enable, disable
+	 */
+	AB8500_FIXED_LDO(TVOUT,	  2000,   0x0380,   0x2,    0x2),
+	AB8500_FIXED_LDO(AUDIO,   2000,   0x0383,   0x2,    0x2),
+	AB8500_FIXED_LDO(ANAMIC1, 2050,   0x0383,   0x4,    0x4),
+	AB8500_FIXED_LDO(ANAMIC2, 2050,   0x0383,   0x8,    0x8),
+	AB8500_FIXED_LDO(DMIC,    1800,   0x0383,   0x10,   0x10),
+	AB8500_FIXED_LDO(ANA,     1200,   0x0383,   0xc,    0x4),
+};
+
+static inline struct ab8500_regulator_info *find_regulator_info(int id)
+{
+	struct ab8500_regulator_info *info;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ab8500_regulator_info); i++) {
+		info = &ab8500_regulator_info[i];
+		if (info->desc.id == id)
+			return info;
+	}
+	return NULL;
+}
+
+static __devinit int ab8500_regulator_probe(struct platform_device *pdev)
+{
+	struct ab8500 *ab8500 = dev_get_drvdata(pdev->dev.parent);
+	struct ab8500_platform_data *pdata = dev_get_platdata(ab8500->dev);
+	int i, err;
+
+	if (!ab8500) {
+		dev_err(&pdev->dev, "null mfd parent\n");
+		return -EINVAL;
+	}
+
+	/* register all regulators */
+	for (i = 0; i < ARRAY_SIZE(ab8500_regulator_info); i++) {
+		struct ab8500_regulator_info *info = NULL;
+
+		/* assign per-regulator data */
+		info = &ab8500_regulator_info[i];
+		info->dev = &pdev->dev;
+		info->ab8500 = ab8500;
+
+		info->regulator = regulator_register(&info->desc, &pdev->dev,
+				pdata->regulator[i], info);
+		if (IS_ERR(info->regulator)) {
+			err = PTR_ERR(info->regulator);
+			dev_err(&pdev->dev, "failed to register regulator %s\n",
+					info->desc.name);
+			/* when we fail, un-register all earlier regulators */
+			i--;
+			while (i > 0) {
+				info = &ab8500_regulator_info[i];
+				regulator_unregister(info->regulator);
+				i--;
+			}
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+static __devexit int ab8500_regulator_remove(struct platform_device *pdev)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ab8500_regulator_info); i++) {
+		struct ab8500_regulator_info *info = NULL;
+		info = &ab8500_regulator_info[i];
+		regulator_unregister(info->regulator);
+	}
+
+	return 0;
+}
+
+static struct platform_driver ab8500_regulator_driver = {
+	.probe = ab8500_regulator_probe,
+	.remove = __devexit_p(ab8500_regulator_remove),
+	.driver         = {
+		.name   = "ab8500-regulator",
+		.owner  = THIS_MODULE,
+	},
+};
+
+static int __init ab8500_regulator_init(void)
+{
+	int ret;
+
+	ret = platform_driver_register(&ab8500_regulator_driver);
+	if (ret != 0)
+		pr_err("Failed to register ab8500 regulator: %d\n", ret);
+
+	return ret;
+}
+subsys_initcall(ab8500_regulator_init);
+
+static void __exit ab8500_regulator_exit(void)
+{
+	platform_driver_unregister(&ab8500_regulator_driver);
+}
+module_exit(ab8500_regulator_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Sundar Iyer <sundar.iyer at stericsson.com>");
+MODULE_DESCRIPTION("Regulator Driver for ST-Ericsson AB8500 Mixed-Sig PMIC");
+MODULE_ALIAS("platform:ab8500-regulator");
-- 
1.7.0



From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.79.1279555416.27306.linux-arm-kernel@lists.infradead.org>

of road to cover though, let's see if I can figure it out.

The way I read the code I still have to provide some
kind of dummychip on the bus in order to perform a
loopback test on a bus with no devices connected,
am I right?

Yours,
Linus Walleij


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.85.1280108246.27306.linux-arm-kernel@lists.infradead.org>

boot up time. This because it will improve the start up time of your
final kernel _and_ your boot loader as well if you use kexec.

Cheers,

/ magnus


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.92.1280216615.27306.linux-arm-kernel@lists.infradead.org>

usage scenarios better or worse. This results in higher or lower memory
fragmentation. System use cases are something that kernel or drivers are
definitely not aware, so only user space can tune this parameter to get the
best possible system behavior.

> We can always add more complex scenarios later, but for an initial version
> I'd keep it simple.
> 
> > +
> > +    2. CMA allows a run-time configuration of the memory regions it
> > +       will use to allocate chunks of memory from.  The set of memory
> > +       regions is given on command line so it can be easily changed
> > +       without the need for recompiling the kernel.
> > +
> > +       Each region has it's own size, alignment demand, a start
> > +       address (physical address where it should be placed) and an
> > +       allocator algorithm assigned to the region.
> > +
> > +       This means that there can be different algorithms running at
> > +       the same time, if different devices on the platform have
> > +       distinct memory usage characteristics and different algorithm
> > +       match those the best way.
> 
> Seems overengineering to me. Just ensure that the code can be extended
> later to such hypothetical scenarios. They are hypothetical, right?

Not really. Having the possibility to reconfigure memory configuration
without kernel recompilation is very handy when one is tuning the
configuration for the specific use case.

> > +    3. When requesting memory, devices have to introduce themselves.
> > +       This way CMA knows who the memory is allocated for.  This
> > +       allows for the system architect to specify which memory regions
> > +       each device should use.
> > +
> > +       3a. Devices can also specify a "kind" of memory they want.
> > +           This makes it possible to configure the system in such
> > +           a way, that a single device may get memory from different
> > +           memory regions, depending on the "kind" of memory it
> > +           requested.  For example, a video codec driver might want to
> > +           allocate some shared buffers from the first memory bank and
> > +           the other from the second to get the highest possible
> > +           memory throughput.
> 
> Not sure I understand this. Isn't this just two regions, one for each
> memory bank,
> and the driver requests some buffers from one region and some from the
> other?

Right.

> Not sure how a 'kind of memory' features in this.

This 'kind' is a just cookie or a label used by the driver to distinguish
requests for both memory banks. This functionality is essential for our
hardware (just for hardware video codec we have 3 'kinds' of memory: memory
bank A, memory bank B and special region for the firmware).

> > +    4. For greater flexibility and extensibility, the framework allows
> > +       device drivers to register private regions of reserved memory
> > +       which then may be used only by them.
> > +
> > +       As an effect, if a driver would not use the rest of the CMA
> > +       interface, it can still use CMA allocators and other
> > +       mechanisms.
> 
> Why would you? Is there an actual driver that will need this?

This feature has been added after posting v1 of this rfc/patch. Jonathan 
Corbet suggested in <http://article.gmane.org/gmane.linux.kernel.mm/50689> 
that viafb driver might register its own private memory and use cma just
as an allocator. IMHO this is a good idea, this way we might remove a bunch
of custom allocators from the drivers (yes, there are such all over the
kernel).

> > +       4a. Early in boot process, device drivers can also request the
> > +           CMA framework to a reserve a region of memory for them
> > +           which then will be used as a private region.
> > +
> > +           This way, drivers do not need to directly call bootmem,
> > +           memblock or similar early allocator but merely register an
> > +           early region and the framework will handle the rest
> > +           including choosing the right early allocator.
> 
> The whole concept of private regions seems unnecessary to me.
> 
> <big snip>
> 
> It looks to me as if you tried to think of all possible hypothetical
> situations
> and write a framework for that. Of course, you may know more than I do, and
> some of these situations actually happen.

Not exactly. We tried to design a solution that would cover all requirements
for OUR (quite specific) embedded hardware. However we didn't want to tie it
only to our platform. We just generalized most of our requirements so they can
be reused for other systems.

> The basic design ideas are solid, I think. But you should get rid of all
> the fancy features and go back to basics. We can always add those features
> later should that become necessary. But removing features is much, much
harder.

Well, please keep in mind that we cannot remove features that are essential
for our solution. We know that a simple framework have some advantages
(well, the most important one is the fact that it is easy to understand),
but making it too simple would render it useless from our point of view
(if it would not provide functionality required by our drivers and hardware).

Best regards
--
Marek Szyprowski
Samsung Poland R&D Center





From leiwen at marvell.com  Tue Jun 22 08:19:35 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 20:19:35 +0800
Subject: [PATCH 02/29] pxa3xx_nand: fix compile warning
Message-ID: <mailman.95.1280296581.27306.linux-arm-kernel@lists.infradead.org>

The compile output as below:
WARNING: modpost: Found 1 section mismatch(es).

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 3ffcbcd..52cec28 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1069,7 +1069,7 @@ static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
 	this->chip_delay = 25;
 }

-static int pxa3xx_nand_probe(struct platform_device *pdev)
+static int __devinit pxa3xx_nand_probe(struct platform_device *pdev)
 {
 	struct pxa3xx_nand_platform_data *pdata;
 	struct pxa3xx_nand_info *info;
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 08:28:19 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 20:28:19 +0800
Subject: [PATCH 04/29] pxa3xx_nand: remove the flash info in driver structure
Message-ID: <mailman.98.1280296600.27306.linux-arm-kernel@lists.infradead.org>

After probe, all info already transfer to driver structure.
There is no need to keep the original flash info.
So that we could safely free the flash info in memory, which may grows
larger when more flash is suported.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  116 +++++++++++++++-------------------------
 1 files changed, 44 insertions(+), 72 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index b605147..50e08db 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -117,7 +117,7 @@ struct pxa3xx_nand_info {
 	struct nand_chip	nand_chip;

 	struct platform_device	 *pdev;
-	const struct pxa3xx_nand_flash *flash_info;
+	struct pxa3xx_nand_cmdset *cmdset;

 	struct clk		*clk;
 	void __iomem		*mmio_base;
@@ -131,6 +131,7 @@ struct pxa3xx_nand_info {
 	int			drcmr_cmd;

 	unsigned char		*data_buff;
+	unsigned char		*oob_buff;
 	dma_addr_t 		data_buff_phys;
 	size_t			data_buff_size;
 	int 			data_dma_ch;
@@ -149,7 +150,8 @@ struct pxa3xx_nand_info {
 	int			use_ecc;	/* use HW ECC ? */
 	int			use_dma;	/* use DMA ? */

-	size_t			data_size;	/* data size in FIFO */
+	unsigned int		page_size;	/* page size of attached chip */
+	unsigned int		data_size;	/* data size in FIFO */
 	int 			retcode;
 	struct completion 	cmd_complete;

@@ -158,6 +160,10 @@ struct pxa3xx_nand_info {
 	uint32_t		ndcb1;
 	uint32_t		ndcb2;

+	/* timing calcuted from setting */
+	uint32_t		ndtr0cs0;
+	uint32_t		ndtr1cs0;
+
 	/* calculated from pxa3xx_nand_flash data */
 	size_t		oob_size;
 	size_t		read_id_bytes;
@@ -174,8 +180,6 @@ MODULE_PARM_DESC(use_dma, "enable DMA for data
transfering to/from NAND HW");
  * Default NAND flash controller configuration setup by the
  * bootloader. This configuration is used only when pdata->keep_config is set
  */
-static struct pxa3xx_nand_timing default_timing;
-static struct pxa3xx_nand_flash default_flash;
 static struct pxa3xx_nand_cmdset default_cmdset = {
 	.read1		= 0x3000,
 	.read2		= 0x0050,
@@ -223,23 +227,9 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
 #define NDTR1_tWHR(c)	(min((c), 15) << 4)
 #define NDTR1_tAR(c)	(min((c), 15) << 0)

-#define tCH_NDTR0(r)	(((r) >> 19) & 0x7)
-#define tCS_NDTR0(r)	(((r) >> 16) & 0x7)
-#define tWH_NDTR0(r)	(((r) >> 11) & 0x7)
-#define tWP_NDTR0(r)	(((r) >> 8) & 0x7)
-#define tRH_NDTR0(r)	(((r) >> 3) & 0x7)
-#define tRP_NDTR0(r)	(((r) >> 0) & 0x7)
-
-#define tR_NDTR1(r)	(((r) >> 16) & 0xffff)
-#define tWHR_NDTR1(r)	(((r) >> 4) & 0xf)
-#define tAR_NDTR1(r)	(((r) >> 0) & 0xf)
-
 /* convert nano-seconds to nand flash controller clock cycles */
 #define ns2cycle(ns, clk)	(int)(((ns) * (clk / 1000000) / 1000) - 1)

-/* convert nand flash controller clock cycles to nano-seconds */
-#define cycle2ns(c, clk)	((((c) + 1) * 1000000 + clk / 500) / (clk / 1000))
-
 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
 				   const struct pxa3xx_nand_timing *t)
 {
@@ -257,6 +247,8 @@ static void pxa3xx_nand_set_timing(struct
pxa3xx_nand_info *info,
 		NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
 		NDTR1_tAR(ns2cycle(t->tAR, nand_clk));

+	info->ndtr0cs0 = ndtr0;
+	info->ndtr1cs0 = ndtr1;
 	nand_writel(info, NDTR0CS0, ndtr0);
 	nand_writel(info, NDTR1CS0, ndtr1);
 }
@@ -280,23 +272,24 @@ static int wait_for_event(struct
pxa3xx_nand_info *info, uint32_t event)
 	return -ETIMEDOUT;
 }

-static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
-			uint16_t cmd, int column, int page_addr)
+static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 {
-	const struct pxa3xx_nand_flash *f = info->flash_info;
-	const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
-
 	/* calculate data size */
-	switch (f->page_size) {
+	switch (info->page_size) {
 	case 2048:
 		info->data_size = (info->use_ecc) ? 2088 : 2112;
 		break;
 	case 512:
 		info->data_size = (info->use_ecc) ? 520 : 528;
 		break;
-	default:
-		return -EINVAL;
 	}
+}
+
+static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
+		uint16_t cmd, int column, int page_addr)
+{
+	const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
+	pxa3xx_set_datasize(info);

 	/* generate values for NDCBx registers */
 	info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
@@ -335,7 +328,7 @@ static int prepare_erase_cmd(struct pxa3xx_nand_info *info,

 static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
 {
-	const struct pxa3xx_nand_cmdset *cmdset = info->flash_info->cmdset;
+	const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;

 	info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
 	info->ndcb1 = 0;
@@ -421,6 +414,7 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
 	case STATE_PIO_READING:
 		__raw_readsl(info->mmio_base + NDDB, info->data_buff,
 				DIV_ROUND_UP(info->data_size, 4));
+
 		break;
 	default:
 		printk(KERN_ERR "%s: invalid state %d\n", __func__,
@@ -572,8 +566,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 				int column, int page_addr)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
-	const struct pxa3xx_nand_flash *flash_info = info->flash_info;
-	const struct pxa3xx_nand_cmdset *cmdset = flash_info->cmdset;
+	const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
 	int ret;

 	info->use_dma = (use_dma) ? 1 : 0;
@@ -797,8 +790,7 @@ static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,

 static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
 {
-	const struct pxa3xx_nand_flash *f = info->flash_info;
-	const struct pxa3xx_nand_cmdset *cmdset = f->cmdset;
+	const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
 	uint32_t ndcr;
 	uint8_t  id_buff[8];

@@ -840,6 +832,9 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 		return -EINVAL;

 	/* calculate flash information */
+	info->cmdset = f->cmdset;
+	info->page_size = f->page_size;
+	info->oob_buff = info->data_buff + f->page_size;
 	info->oob_size = (f->page_size == 2048) ? 64 : 16;
 	info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;

@@ -864,44 +859,20 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	info->reg_ndcr = ndcr;

 	pxa3xx_nand_set_timing(info, f->timing);
-	info->flash_info = f;
 	return 0;
 }

-static void pxa3xx_nand_detect_timing(struct pxa3xx_nand_info *info,
-				      struct pxa3xx_nand_timing *t)
-{
-	unsigned long nand_clk = clk_get_rate(info->clk);
-	uint32_t ndtr0 = nand_readl(info, NDTR0CS0);
-	uint32_t ndtr1 = nand_readl(info, NDTR1CS0);
-
-	t->tCH = cycle2ns(tCH_NDTR0(ndtr0), nand_clk);
-	t->tCS = cycle2ns(tCS_NDTR0(ndtr0), nand_clk);
-	t->tWH = cycle2ns(tWH_NDTR0(ndtr0), nand_clk);
-	t->tWP = cycle2ns(tWP_NDTR0(ndtr0), nand_clk);
-	t->tRH = cycle2ns(tRH_NDTR0(ndtr0), nand_clk);
-	t->tRP = cycle2ns(tRP_NDTR0(ndtr0), nand_clk);
-
-	t->tR = cycle2ns(tR_NDTR1(ndtr1), nand_clk);
-	t->tWHR = cycle2ns(tWHR_NDTR1(ndtr1), nand_clk);
-	t->tAR = cycle2ns(tAR_NDTR1(ndtr1), nand_clk);
-}
-
 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 {
 	uint32_t ndcr = nand_readl(info, NDCR);
 	struct nand_flash_dev *type = NULL;
-	uint32_t id = -1;
+	uint32_t id = -1, page_per_block, num_blocks;
 	int i;

-	default_flash.page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
-	default_flash.page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
-	default_flash.flash_width = ndcr & NDCR_DWIDTH_M ? 16 : 8;
-	default_flash.dfc_width = ndcr & NDCR_DWIDTH_C ? 16 : 8;
-
+	page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
+	info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
 	/* set info fields needed to __readid */
-	info->flash_info = &default_flash;
-	info->read_id_bytes = (default_flash.page_size == 2048) ? 4 : 2;
+	info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
 	info->reg_ndcr = ndcr;

 	if (__readid(info, &id))
@@ -920,22 +891,22 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand_info *info)
 		return -ENODEV;

 	/* fill the missing flash information */
-	i = __ffs(default_flash.page_per_block * default_flash.page_size);
-	default_flash.num_blocks = type->chipsize << (20 - i);
+	i = __ffs(page_per_block * info->page_size);
+	num_blocks = type->chipsize << (20 - i);

-	info->oob_size = (default_flash.page_size == 2048) ? 64 : 16;
+	info->oob_size = (info->page_size == 2048) ? 64 : 16;

 	/* calculate addressing information */
-	info->col_addr_cycles = (default_flash.page_size == 2048) ? 2 : 1;
+	info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1;

-	if (default_flash.num_blocks * default_flash.page_per_block > 65536)
+	if (num_blocks * page_per_block > 65536)
 		info->row_addr_cycles = 3;
 	else
 		info->row_addr_cycles = 2;

-	pxa3xx_nand_detect_timing(info, &default_timing);
-	default_flash.timing = &default_timing;
-	default_flash.cmdset = &default_cmdset;
+	info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
+	info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
+	info->cmdset = &default_cmdset;

 	return 0;
 }
@@ -1036,10 +1007,9 @@ static struct nand_ecclayout hw_largepage_ecclayout = {
 static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
 				 struct pxa3xx_nand_info *info)
 {
-	const struct pxa3xx_nand_flash *f = info->flash_info;
 	struct nand_chip *this = &info->nand_chip;

-	this->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
+	this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;

 	this->waitfunc		= pxa3xx_nand_waitfunc;
 	this->select_chip	= pxa3xx_nand_select_chip;
@@ -1055,9 +1025,9 @@ static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
 	this->ecc.hwctl		= pxa3xx_nand_ecc_hwctl;
 	this->ecc.calculate	= pxa3xx_nand_ecc_calculate;
 	this->ecc.correct	= pxa3xx_nand_ecc_correct;
-	this->ecc.size		= f->page_size;
+	this->ecc.size		= info->page_size;

-	if (f->page_size == 2048)
+	if (info->page_size == 2048)
 		this->ecc.layout = &hw_largepage_ecclayout;
 	else
 		this->ecc.layout = &hw_smallpage_ecclayout;
@@ -1264,9 +1234,11 @@ static int pxa3xx_nand_resume(struct
platform_device *pdev)
 	struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
 	struct pxa3xx_nand_info *info = mtd->priv;

+	nand_writel(info, NDTR0CS0, info->ndtr0cs0);
+	nand_writel(info, NDTR1CS0, info->ndtr1cs0);
 	clk_enable(info->clk);

-	return pxa3xx_nand_config_flash(info, info->flash_info);
+	return 0;
 }
 #else
 #define pxa3xx_nand_suspend	NULL
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 08:20:16 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 20:20:16 +0800
Subject: [PATCH 03/29] pxa3xx_nand: introduce default timing to reduce
Message-ID: <mailman.100.1280296615.27306.linux-arm-kernel@lists.infradead.org>

read id times

We certainly don't need to send read id command times by times, since
we already know what the id is after the first read id...

So create a default timing which could ensure it would successfully read
id out all supported chip. Then follow the build-in table to reconfigure
the timing.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |   56 ++++++++++++++++++---------------------
 1 files changed, 26 insertions(+), 30 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 52cec28..b605147 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -190,15 +190,18 @@ static struct pxa3xx_nand_cmdset default_cmdset = {
 };

 static struct pxa3xx_nand_timing __devinitdata timing[] = {
-	{ 10,  0, 20, 40, 30, 40, 11123, 110, 10, },
-	{ 10, 25, 15, 25, 15, 30, 25000,  60, 10, },
-	{ 10, 35, 15, 25, 15, 25, 25000,  60, 10, },
+	{ 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
+	{ 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
+	{ 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
+	{ 10, 35, 15,  25, 15,  25, 25000,  60, 10, },
 };

-#define NAND_SETTING_SAMSUNG     &default_cmdset, &timing[0]
-#define NAND_SETTING_MICRON      &default_cmdset, &timing[1]
-#define NAND_SETTING_ST          &default_cmdset, &timing[2]
+#define NAND_SETTING_DEFAULT     &default_cmdset, &timing[0]
+#define NAND_SETTING_SAMSUNG     &default_cmdset, &timing[1]
+#define NAND_SETTING_MICRON      &default_cmdset, &timing[2]
+#define NAND_SETTING_ST          &default_cmdset, &timing[3]
 static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
+	{      0,   0, 2048,  8,  8,    0, NAND_SETTING_DEFAULT, },
 	{ 0x46ec,  32,  512, 16, 16, 4096, NAND_SETTING_SAMSUNG, },
 	{ 0xdaec,  64, 2048,  8,  8, 2048, NAND_SETTING_SAMSUNG, },
 	{ 0xd7ec, 128, 4096,  8,  8, 8192, NAND_SETTING_SAMSUNG, },
@@ -948,36 +951,29 @@ static int pxa3xx_nand_detect_flash(struct
pxa3xx_nand_info *info,
 		if (pxa3xx_nand_detect_config(info) == 0)
 			return 0;

-	for (i = 0; i<pdata->num_flash; ++i) {
-		f = pdata->flash + i;
-
-		if (pxa3xx_nand_config_flash(info, f))
-			continue;
-
-		if (__readid(info, &id))
-			continue;
-
-		if (id == f->chip_id)
-			return 0;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(builtin_flash_types); i++) {
-
-		f = &builtin_flash_types[i];
-
-		if (pxa3xx_nand_config_flash(info, f))
-			continue;
-
-		if (__readid(info, &id))
-			continue;
-
-		if (id == f->chip_id)
+	/* we use default timing to detect id */
+	f = &builtin_flash_types[0];
+	pxa3xx_nand_config_flash(info, f);
+	if (__readid(info, &id))
+		goto fail_detect;
+
+	for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
+		/* we first choose the flash definition from platfrom */
+		if (i < pdata->num_flash)
+			f = pdata->flash + i;
+		else
+			f = &builtin_flash_types[i - pdata->num_flash + 1];
+		if (f->chip_id == id) {
+			dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
+			pxa3xx_nand_config_flash(info, f);
 			return 0;
+		}
 	}

 	dev_warn(&info->pdev->dev,
 		 "failed to detect configured nand flash; found %04x instead of\n",
 		 id);
+fail_detect:
 	return -ENODEV;
 }

-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 09:01:04 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 21:01:04 +0800
Subject: [PATCH 05/29] pxa3xx_nand: set oob length in the runtime
Message-ID: <mailman.101.1280296629.27306.linux-arm-kernel@lists.infradead.org>

For different command need different oob requirement, set the proper
oob length by different cmd.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |   25 ++++++++++++++++++-------
 1 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 50e08db..26c0286 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -274,13 +274,20 @@ static int wait_for_event(struct
pxa3xx_nand_info *info, uint32_t event)

 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 {
-	/* calculate data size */
+	int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
+
+	info->data_size = info->page_size;
+	if (!oob_enable) {
+		info->oob_size = 0;
+		return;
+	}
+
 	switch (info->page_size) {
 	case 2048:
-		info->data_size = (info->use_ecc) ? 2088 : 2112;
+		info->oob_size = (info->use_ecc) ? 40 : 64;
 		break;
 	case 512:
-		info->data_size = (info->use_ecc) ? 520 : 528;
+		info->oob_size = (info->use_ecc) ? 8 : 16;
 		break;
 	}
 }
@@ -334,6 +341,7 @@ static int prepare_other_cmd(struct
pxa3xx_nand_info *info, uint16_t cmd)
 	info->ndcb1 = 0;
 	info->ndcb2 = 0;

+	info->oob_size = 0;
 	if (cmd == cmdset->read_id) {
 		info->ndcb0 |= NDCB0_CMD_TYPE(3);
 		info->data_size = 8;
@@ -402,6 +410,9 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
 	case STATE_PIO_WRITING:
 		__raw_writesl(info->mmio_base + NDDB, info->data_buff,
 				DIV_ROUND_UP(info->data_size, 4));
+		if (info->oob_size > 0)
+			__raw_writesl(info->mmio_base + NDDB, info->oob_buff,
+					DIV_ROUND_UP(info->oob_size, 4));

 		enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);

@@ -414,6 +425,9 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
 	case STATE_PIO_READING:
 		__raw_readsl(info->mmio_base + NDDB, info->data_buff,
 				DIV_ROUND_UP(info->data_size, 4));
+		if (info->oob_size > 0)
+			__raw_readsl(info->mmio_base + NDDB, info->oob_buff,
+					DIV_ROUND_UP(info->oob_size, 4));

 		break;
 	default:
@@ -429,7 +443,7 @@ static int handle_data_pio(struct pxa3xx_nand_info *info)
 static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
 {
 	struct pxa_dma_desc *desc = info->data_desc;
-	int dma_len = ALIGN(info->data_size, 32);
+	int dma_len = ALIGN(info->data_size + info->oob_size, 32);

 	desc->ddadr = DDADR_STOP;
 	desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
@@ -835,7 +849,6 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	info->cmdset = f->cmdset;
 	info->page_size = f->page_size;
 	info->oob_buff = info->data_buff + f->page_size;
-	info->oob_size = (f->page_size == 2048) ? 64 : 16;
 	info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;

 	/* calculate addressing information */
@@ -894,8 +907,6 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand_info *info)
 	i = __ffs(page_per_block * info->page_size);
 	num_blocks = type->chipsize << (20 - i);

-	info->oob_size = (info->page_size == 2048) ? 64 : 16;
-
 	/* calculate addressing information */
 	info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1;

-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 09:01:27 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 21:01:27 +0800
Subject: [PATCH 06/29] pxa3xx_nand: make scan procedure more clear
Message-ID: <mailman.104.1280296645.27306.linux-arm-kernel@lists.infradead.org>

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |   88 ++++++++++++++++++++++-----------------
 1 files changed, 50 insertions(+), 38 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 26c0286..8d030ec 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -126,6 +126,7 @@ struct pxa3xx_nand_info {
 	unsigned int 		buf_start;
 	unsigned int		buf_count;

+	struct mtd_info         *mtd;
 	/* DMA information */
 	int			drcmr_dat;
 	int			drcmr_cmd;
@@ -1046,21 +1047,13 @@ static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
 	this->chip_delay = 25;
 }

-static int __devinit pxa3xx_nand_probe(struct platform_device *pdev)
+static int alloc_nand_resource(struct platform_device *pdev)
 {
-	struct pxa3xx_nand_platform_data *pdata;
+	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 	struct pxa3xx_nand_info *info;
-	struct nand_chip *this;
 	struct mtd_info *mtd;
 	struct resource *r;
-	int ret = 0, irq;
-
-	pdata = pdev->dev.platform_data;
-
-	if (!pdata) {
-		dev_err(&pdev->dev, "no platform data defined\n");
-		return -ENODEV;
-	}
+	int ret, irq;

 	mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
 			GFP_KERNEL);
@@ -1072,8 +1065,8 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 	info = (struct pxa3xx_nand_info *)(&mtd[1]);
 	info->pdev = pdev;

-	this = &info->nand_chip;
 	mtd->priv = info;
+	info->mtd = mtd;
 	mtd->owner = THIS_MODULE;

 	info->clk = clk_get(&pdev->dev, NULL);
@@ -1151,27 +1144,9 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 	}

 	pxa3xx_nand_init_mtd(mtd, info);
+	platform_set_drvdata(pdev, info);

-	platform_set_drvdata(pdev, mtd);
-
-	if (nand_scan(mtd, 1)) {
-		dev_err(&pdev->dev, "failed to scan nand\n");
-		ret = -ENXIO;
-		goto fail_free_irq;
-	}
-
-	if (mtd_has_cmdlinepart()) {
-		static const char *probes[] = { "cmdlinepart", NULL };
-		struct mtd_partition *parts;
-		int nr_parts;
-
-		nr_parts = parse_mtd_partitions(mtd, probes, &parts, 0);
-
-		if (nr_parts)
-			return add_mtd_partitions(mtd, parts, nr_parts);
-	}
-
-	return add_mtd_partitions(mtd, pdata->parts, pdata->nr_parts);
+	return 0;

 fail_free_irq:
 	free_irq(irq, info);
@@ -1196,8 +1171,8 @@ fail_free_mtd:

 static int pxa3xx_nand_remove(struct platform_device *pdev)
 {
-	struct mtd_info *mtd = platform_get_drvdata(pdev);
-	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
+	struct mtd_info *mtd = info->mtd;
 	struct resource *r;
 	int irq;

@@ -1226,11 +1201,48 @@ static int pxa3xx_nand_remove(struct
platform_device *pdev)
 	return 0;
 }

+static int __devinit pxa3xx_nand_probe(struct platform_device *pdev)
+{
+	struct pxa3xx_nand_platform_data *pdata;
+	struct pxa3xx_nand_info *info;
+	int ret;
+
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		dev_err(&pdev->dev, "no platform data defined\n");
+		return -ENODEV;
+	}
+
+	ret = alloc_nand_resource(pdev);
+	if (ret)
+		return ret;
+
+	info = platform_get_drvdata(pdev);
+	if (nand_scan(info->mtd, 1)) {
+		dev_err(&pdev->dev, "failed to scan nand\n");
+		pxa3xx_nand_remove(pdev);
+		return -ENODEV;
+	}
+
+	if (mtd_has_cmdlinepart()) {
+		static const char *probes[] = { "cmdlinepart", NULL };
+		struct mtd_partition *parts;
+		int nr_parts;
+
+		nr_parts = parse_mtd_partitions(info->mtd, probes, &parts, 0);
+
+		if (nr_parts)
+			return add_mtd_partitions(info->mtd, parts, nr_parts);
+	}
+
+	return add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts);
+}
+
 #ifdef CONFIG_PM
 static int pxa3xx_nand_suspend(struct platform_device *pdev,
pm_message_t state)
 {
-	struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
-	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
+	struct mtd_info *mtd = info->mtd;

 	if (info->state != STATE_READY) {
 		dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
@@ -1242,8 +1254,8 @@ static int pxa3xx_nand_suspend(struct
platform_device *pdev, pm_message_t state)

 static int pxa3xx_nand_resume(struct platform_device *pdev)
 {
-	struct mtd_info *mtd = (struct mtd_info *)platform_get_drvdata(pdev);
-	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
+	struct mtd_info *mtd = info->mtd;

 	nand_writel(info, NDTR0CS0, info->ndtr0cs0);
 	nand_writel(info, NDTR1CS0, info->ndtr1cs0);
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 09:19:40 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 21:19:40 +0800
Subject: [PATCH 07/29] pxa3xx_nand: rework irq logic
Message-ID: <mailman.105.1280296662.27306.linux-arm-kernel@lists.infradead.org>

Enable all irq when we start the nand controller, and
put all the transaction logic in the pxa3xx_nand_irq.

By doing this way, we could dramatically increase the
performance by avoid unnecessary delay.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  308 ++++++++++++++++++----------------------
 1 files changed, 140 insertions(+), 168 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 8d030ec..0d97463 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -27,6 +27,7 @@
 #include <plat/pxa3xx_nand.h>

 #define	CHIP_DELAY_TIMEOUT	(2 * HZ/10)
+#define NAND_STOP_DELAY		(2 * HZ/50)

 /* registers and bit definitions */
 #define NDCR		(0x00) /* Control register */
@@ -49,6 +50,7 @@
 #define NDCR_DWIDTH_M		(0x1 << 26)
 #define NDCR_PAGE_SZ		(0x1 << 24)
 #define NDCR_NCSX		(0x1 << 23)
+#define NDCR_STOP_ON_UNCOR	(0x1 << 22)
 #define NDCR_ND_MODE		(0x3 << 21)
 #define NDCR_NAND_MODE   	(0x0)
 #define NDCR_CLR_PG_CNT		(0x1 << 20)
@@ -59,9 +61,11 @@
 #define NDCR_RA_START		(0x1 << 15)
 #define NDCR_PG_PER_BLK		(0x1 << 14)
 #define NDCR_ND_ARB_EN		(0x1 << 12)
+#define NDCR_INT_MASK           (0xFFF)

 #define NDSR_MASK		(0xfff)
-#define NDSR_RDY		(0x1 << 11)
+#define NDSR_RDY                (0x1 << 12)
+#define NDSR_FLASH_RDY          (0x1 << 11)
 #define NDSR_CS0_PAGED		(0x1 << 10)
 #define NDSR_CS1_PAGED		(0x1 << 9)
 #define NDSR_CS0_CMDD		(0x1 << 8)
@@ -104,13 +108,14 @@ enum {
 };

 enum {
-	STATE_READY	= 0,
-	STATE_CMD_HANDLE,
-	STATE_DMA_READING,
-	STATE_DMA_WRITING,
-	STATE_DMA_DONE,
-	STATE_PIO_READING,
-	STATE_PIO_WRITING,
+	STATE_CMD_WAIT_DONE	= 1,
+	STATE_DATA_PROCESSING	= (1 << 1),
+	STATE_DATA_DONE		= (1 << 2),
+	STATE_PAGE_DONE		= (1 << 3),
+	STATE_CMD_DONE		= (1 << 4),
+	STATE_READY		= (1 << 5),
+	STATE_CMD_PREPARED	= (1 << 6),
+	STATE_IS_WRITE		= (1 << 7),
 };

 struct pxa3xx_nand_info {
@@ -293,7 +298,47 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
 	}
 }

-static int prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
+/**
+ * NOTE: it is a must to set ND_RUN firstly, then write
+ * command buffer, otherwise, it does not work.
+ * We enable all the interrupt at the same time, and
+ * let pxa3xx_nand_irq to handle all logic.
+ */
+static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
+{
+	uint32_t ndcr;
+
+	ndcr = info->reg_ndcr;
+	ndcr |= NDCR_ECC_EN;
+	ndcr |= info->use_dma ? NDCR_DMA_EN : NDCR_STOP_ON_UNCOR;
+	ndcr |= NDCR_ND_RUN;
+
+	/* clear status bits and run */
+	nand_writel(info, NDCR, 0);
+	nand_writel(info, NDSR, NDSR_MASK);
+	nand_writel(info, NDCR, ndcr);
+}
+
+static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
+{
+	uint32_t ndcr;
+	int timeout = NAND_STOP_DELAY;
+
+	/* wait RUN bit in NDCR become 0 */
+	do {
+		/* clear status bits */
+		nand_writel(info, NDSR, NDSR_MASK);
+		ndcr = nand_readl(info, NDCR);
+		udelay(1);
+	} while ((ndcr & NDCR_ND_RUN) && (timeout -- > 0));
+
+	if (timeout <= 0) {
+		ndcr &= ~(NDCR_ND_RUN);
+		nand_writel(info, NDCR, ndcr);
+	}
+}
+
+static void prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
 		uint16_t cmd, int column, int page_addr)
 {
 	const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
@@ -320,21 +365,18 @@ static int prepare_read_prog_cmd(struct
pxa3xx_nand_info *info,

 	if (cmd == cmdset->program)
 		info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
-
-	return 0;
 }

-static int prepare_erase_cmd(struct pxa3xx_nand_info *info,
+static void prepare_erase_cmd(struct pxa3xx_nand_info *info,
 			uint16_t cmd, int page_addr)
 {
 	info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
 	info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
 	info->ndcb1 = page_addr;
 	info->ndcb2 = 0;
-	return 0;
 }

-static int prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
+static void prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
 {
 	const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;

@@ -352,10 +394,7 @@ static int prepare_other_cmd(struct
pxa3xx_nand_info *info, uint16_t cmd)
 	} else if (cmd == cmdset->reset || cmd == cmdset->lock ||
 		   cmd == cmdset->unlock) {
 		info->ndcb0 |= NDCB0_CMD_TYPE(5);
-	} else
-		return -EINVAL;
-
-	return 0;
+	}
 }

 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
@@ -403,42 +442,23 @@ static int write_cmd(struct pxa3xx_nand_info *info)
 	return 0;
 }

-static int handle_data_pio(struct pxa3xx_nand_info *info)
+static void handle_data_pio(struct pxa3xx_nand_info *info)
 {
-	int ret, timeout = CHIP_DELAY_TIMEOUT;
-
-	switch (info->state) {
-	case STATE_PIO_WRITING:
+	if (info->state & STATE_IS_WRITE) {
 		__raw_writesl(info->mmio_base + NDDB, info->data_buff,
 				DIV_ROUND_UP(info->data_size, 4));
 		if (info->oob_size > 0)
 			__raw_writesl(info->mmio_base + NDDB, info->oob_buff,
 					DIV_ROUND_UP(info->oob_size, 4));

-		enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
-
-		ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
-		if (!ret) {
-			printk(KERN_ERR "program command time out\n");
-			return -1;
-		}
-		break;
-	case STATE_PIO_READING:
+	}
+	else {
 		__raw_readsl(info->mmio_base + NDDB, info->data_buff,
 				DIV_ROUND_UP(info->data_size, 4));
 		if (info->oob_size > 0)
 			__raw_readsl(info->mmio_base + NDDB, info->oob_buff,
 					DIV_ROUND_UP(info->oob_size, 4));
-
-		break;
-	default:
-		printk(KERN_ERR "%s: invalid state %d\n", __func__,
-				info->state);
-		return -EINVAL;
 	}
-
-	info->state = STATE_READY;
-	return 0;
 }

 static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
@@ -474,93 +494,59 @@ static void pxa3xx_nand_data_dma_irq(int
channel, void *data)

 	if (dcsr & DCSR_BUSERR) {
 		info->retcode = ERR_DMABUSERR;
-		complete(&info->cmd_complete);
 	}

-	if (info->state == STATE_DMA_WRITING) {
-		info->state = STATE_DMA_DONE;
-		enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
-	} else {
-		info->state = STATE_READY;
-		complete(&info->cmd_complete);
-	}
+	enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
 }

 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 {
 	struct pxa3xx_nand_info *info = devid;
-	unsigned int status;
+	unsigned int status, is_completed = 0;

 	status = nand_readl(info, NDSR);

-	if (status & (NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR)) {
-		if (status & NDSR_DBERR)
-			info->retcode = ERR_DBERR;
-		else if (status & NDSR_SBERR)
-			info->retcode = ERR_SBERR;
-
-		disable_int(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
+	if (status & NDSR_DBERR)
+		info->retcode = ERR_DBERR;
+	if (status & NDSR_SBERR)
+		info->retcode = ERR_SBERR;
+	if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {

+		info->state |= STATE_DATA_PROCESSING;
+		/* whether use dma to transfer data */
 		if (info->use_dma) {
-			info->state = STATE_DMA_READING;
+			disable_int(info, NDSR_WRDREQ);
 			start_data_dma(info, 0);
-		} else {
-			info->state = STATE_PIO_READING;
-			complete(&info->cmd_complete);
-		}
-	} else if (status & NDSR_WRDREQ) {
-		disable_int(info, NDSR_WRDREQ);
-		if (info->use_dma) {
-			info->state = STATE_DMA_WRITING;
-			start_data_dma(info, 1);
-		} else {
-			info->state = STATE_PIO_WRITING;
-			complete(&info->cmd_complete);
-		}
-	} else if (status & (NDSR_CS0_BBD | NDSR_CS0_CMDD)) {
-		if (status & NDSR_CS0_BBD)
-			info->retcode = ERR_BBERR;
+			goto NORMAL_IRQ_EXIT;
+		} else
+			handle_data_pio(info);

-		disable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
-		info->state = STATE_READY;
-		complete(&info->cmd_complete);
+		info->state |= STATE_DATA_DONE;
 	}
-	nand_writel(info, NDSR, status);
-	return IRQ_HANDLED;
-}
-
-static int pxa3xx_nand_do_cmd(struct pxa3xx_nand_info *info, uint32_t event)
-{
-	uint32_t ndcr;
-	int ret, timeout = CHIP_DELAY_TIMEOUT;
-
-	if (write_cmd(info)) {
-		info->retcode = ERR_SENDCMD;
-		goto fail_stop;
+	if (status & NDSR_CS0_CMDD) {
+		info->state |= STATE_CMD_DONE;
+		is_completed = 1;
 	}
-
-	info->state = STATE_CMD_HANDLE;
-
-	enable_int(info, event);
-
-	ret = wait_for_completion_timeout(&info->cmd_complete, timeout);
-	if (!ret) {
-		printk(KERN_ERR "command execution timed out\n");
-		info->retcode = ERR_SENDCMD;
-		goto fail_stop;
+	if (status & NDSR_FLASH_RDY)
+		info->state |= STATE_READY;
+	if (status & NDSR_CS0_PAGED)
+		info->state |= STATE_PAGE_DONE;
+
+	if (status & NDSR_WRCMDREQ) {
+		nand_writel(info, NDSR, NDSR_WRCMDREQ);
+		status &= ~NDSR_WRCMDREQ;
+		info->state |= STATE_CMD_WAIT_DONE;
+		nand_writel(info, NDCB0, info->ndcb0);
+		nand_writel(info, NDCB0, info->ndcb1);
+		nand_writel(info, NDCB0, info->ndcb2);
 	}

-	if (info->use_dma == 0 && info->data_size > 0)
-		if (handle_data_pio(info))
-			goto fail_stop;
-
-	return 0;
-
-fail_stop:
-	ndcr = nand_readl(info, NDCR);
-	nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
-	udelay(10);
-	return -ETIMEDOUT;
+	/* clear NDSR to let the controller exit the IRQ */
+	nand_writel(info, NDSR, status);
+	if (is_completed)
+		complete(&info->cmd_complete);
+NORMAL_IRQ_EXIT:
+	return IRQ_HANDLED;
 }

 static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
@@ -582,14 +568,12 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
 	const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
-	int ret;
+	int ret, exec_cmd = 0;

 	info->use_dma = (use_dma) ? 1 : 0;
 	info->use_ecc = 0;
 	info->data_size = 0;
-	info->state = STATE_READY;
-
-	init_completion(&info->cmd_complete);
+	info->state = 0;

 	switch (command) {
 	case NAND_CMD_READOOB:
@@ -598,14 +582,12 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 		info->buf_start = mtd->writesize + column;
 		memset(info->data_buff, 0xFF, info->buf_count);

-		if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
-			break;
-
-		pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
-
+		prepare_read_prog_cmd(info, cmdset->read1, column, page_addr);
 		/* We only are OOB, so if the data has error, does not matter */
 		if (info->retcode == ERR_DBERR)
 			info->retcode = ERR_NONE;
+
+		exec_cmd = 1;
 		break;

 	case NAND_CMD_READ0:
@@ -615,11 +597,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 		info->buf_count = mtd->writesize + mtd->oobsize;
 		memset(info->data_buff, 0xFF, info->buf_count);

-		if (prepare_read_prog_cmd(info, cmdset->read1, column, page_addr))
-			break;
-
-		pxa3xx_nand_do_cmd(info, NDSR_RDDREQ | NDSR_DBERR | NDSR_SBERR);
-
+		prepare_read_prog_cmd(info, cmdset->read1, column, page_addr);
 		if (info->retcode == ERR_DBERR) {
 			/* for blank page (all 0xff), HW will calculate its ECC as
 			 * 0, which is different from the ECC information within
@@ -628,6 +606,8 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 			if (is_buf_blank(info->data_buff, mtd->writesize))
 				info->retcode = ERR_NONE;
 		}
+
+		exec_cmd = 1;
 		break;
 	case NAND_CMD_SEQIN:
 		info->buf_start = column;
@@ -641,17 +621,14 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 	case NAND_CMD_PAGEPROG:
 		info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;

-		if (prepare_read_prog_cmd(info, cmdset->program,
-				info->seqin_column, info->seqin_page_addr))
-			break;
-
-		pxa3xx_nand_do_cmd(info, NDSR_WRDREQ);
+		prepare_read_prog_cmd(info, cmdset->program,
+				info->seqin_column, info->seqin_page_addr);
+		info->state |= STATE_IS_WRITE;
+		exec_cmd = 1;
 		break;
 	case NAND_CMD_ERASE1:
-		if (prepare_erase_cmd(info, cmdset->erase, page_addr))
-			break;
-
-		pxa3xx_nand_do_cmd(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
+		prepare_erase_cmd(info, cmdset->erase, page_addr);
+		exec_cmd = 1;
 		break;
 	case NAND_CMD_ERASE2:
 		break;
@@ -662,39 +639,37 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 		info->buf_count = (command == NAND_CMD_READID) ?
 				info->read_id_bytes : 1;

-		if (prepare_other_cmd(info, (command == NAND_CMD_READID) ?
-				cmdset->read_id : cmdset->read_status))
-			break;
-
-		pxa3xx_nand_do_cmd(info, NDSR_RDDREQ);
+		prepare_other_cmd(info, (command == NAND_CMD_READID) ?
+				cmdset->read_id : cmdset->read_status);
+		exec_cmd = 1;
 		break;
 	case NAND_CMD_RESET:
-		if (prepare_other_cmd(info, cmdset->reset))
-			break;
-
-		ret = pxa3xx_nand_do_cmd(info, NDSR_CS0_CMDD);
-		if (ret == 0) {
-			int timeout = 2;
-			uint32_t ndcr;
-
-			while (timeout--) {
-				if (nand_readl(info, NDSR) & NDSR_RDY)
-					break;
-				msleep(10);
-			}
-
-			ndcr = nand_readl(info, NDCR);
-			nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
-		}
+		prepare_other_cmd(info, cmdset->reset);
+		exec_cmd = 1;
 		break;
 	default:
 		printk(KERN_ERR "non-supported command.\n");
 		break;
 	}

-	if (info->retcode == ERR_DBERR) {
-		printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
-		info->retcode = ERR_NONE;
+	if (exec_cmd) {
+		init_completion(&info->cmd_complete);
+		info->state |= STATE_CMD_PREPARED;
+		pxa3xx_nand_start(info);
+
+		ret = wait_for_completion_timeout(&info->cmd_complete,
+				CHIP_DELAY_TIMEOUT);
+		if (!ret) {
+			printk(KERN_ERR "Wait time out!!!\n");
+		}
+		/* Stop State Machine for next command cycle */
+		pxa3xx_nand_stop(info);
+		disable_int(info, NDCR_INT_MASK);
+		info->state &= ~STATE_CMD_PREPARED;
+		if (info->retcode == ERR_DBERR) {
+			printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
+			info->retcode = ERR_NONE;
+		}
 	}
 }

@@ -809,10 +784,7 @@ static int __readid(struct pxa3xx_nand_info
*info, uint32_t *id)
 	uint32_t ndcr;
 	uint8_t  id_buff[8];

-	if (prepare_other_cmd(info, cmdset->read_id)) {
-		printk(KERN_ERR "failed to prepare command\n");
-		return -EINVAL;
-	}
+	prepare_other_cmd(info, cmdset->read_id);

 	/* Send command */
 	if (write_cmd(info))
@@ -889,11 +861,12 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand_info *info)
 	info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
 	info->reg_ndcr = ndcr;

-	if (__readid(info, &id))
+	pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
+	id = *((uint16_t *)(info->data_buff));
+	if (id == 0)
 		return -ENODEV;

 	/* Lookup the flash id */
-	id = (id >> 8) & 0xff;		/* device id is byte 2 */
 	for (i = 0; nand_flash_ids[i].name != NULL; i++) {
 		if (id == nand_flash_ids[i].id) {
 			type =  &nand_flash_ids[i];
@@ -937,8 +910,8 @@ static int pxa3xx_nand_detect_flash(struct
pxa3xx_nand_info *info,
 	/* we use default timing to detect id */
 	f = &builtin_flash_types[0];
 	pxa3xx_nand_config_flash(info, f);
-	if (__readid(info, &id))
-		goto fail_detect;
+	pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
+	id = *((uint16_t *)(info->data_buff));

 	for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
 		/* we first choose the flash definition from platfrom */
@@ -956,7 +929,6 @@ static int pxa3xx_nand_detect_flash(struct
pxa3xx_nand_info *info,
 	dev_warn(&info->pdev->dev,
 		 "failed to detect configured nand flash; found %04x instead of\n",
 		 id);
-fail_detect:
 	return -ENODEV;
 }

@@ -1244,7 +1216,7 @@ static int pxa3xx_nand_suspend(struct
platform_device *pdev, pm_message_t state)
 	struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
 	struct mtd_info *mtd = info->mtd;

-	if (info->state != STATE_READY) {
+	if (info->state & STATE_CMD_PREPARED) {
 		dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
 		return -EAGAIN;
 	}
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 09:32:46 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 21:32:46 +0800
Subject: [PATCH 10/29] pxa3xx_nand: mtd scan id process could be
Message-ID: <mailman.109.1280296681.27306.linux-arm-kernel@lists.infradead.org>

defined by driver itself

Different NAND driver may require its unique detection. For pxa3xx_nand,
it use its self id database to get the necessary info.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  253 ++++++++++++++++++++++++++--------------
 1 files changed, 163 insertions(+), 90 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index e7b54dd..617bc69 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -123,6 +123,7 @@ enum {
 struct pxa3xx_nand_info {
 	struct nand_chip	nand_chip;

+	struct nand_hw_control	controller;
 	struct platform_device	 *pdev;
 	struct pxa3xx_nand_cmdset *cmdset;

@@ -224,6 +225,8 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
 	{ 0xba20,  64, 2048, 16, 16, 2048, NAND_SETTING_ST, },
 };

+static const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
+
 #define NDTR0_tCH(c)	(min((c), 7) << 19)
 #define NDTR0_tCS(c)	(min((c), 7) << 16)
 #define NDTR0_tWH(c)	(min((c), 7) << 11)
@@ -830,42 +833,6 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand_info *info)
 	return 0;
 }

-static int pxa3xx_nand_detect_flash(struct pxa3xx_nand_info *info,
-				    const struct pxa3xx_nand_platform_data *pdata)
-{
-	const struct pxa3xx_nand_flash *f;
-	uint32_t id = -1;
-	int i;
-
-	if (pdata->keep_config)
-		if (pxa3xx_nand_detect_config(info) == 0)
-			return 0;
-
-	/* we use default timing to detect id */
-	f = &builtin_flash_types[0];
-	pxa3xx_nand_config_flash(info, f);
-	pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
-	id = *((uint16_t *)(info->data_buff));
-
-	for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
-		/* we first choose the flash definition from platfrom */
-		if (i < pdata->num_flash)
-			f = pdata->flash + i;
-		else
-			f = &builtin_flash_types[i - pdata->num_flash + 1];
-		if (f->chip_id == id) {
-			dev_info(&info->pdev->dev, "detect chip id: 0x%x\n", id);
-			pxa3xx_nand_config_flash(info, f);
-			return 0;
-		}
-	}
-
-	dev_warn(&info->pdev->dev,
-		 "failed to detect configured nand flash; found %04x instead of\n",
-		 id);
-	return -ENODEV;
-}
-
 /* the maximum possible buffer size for large page with OOB data
  * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
  * data buffer and the DMA descriptor
@@ -907,56 +874,153 @@ static int pxa3xx_nand_init_buff(struct
pxa3xx_nand_info *info)
 	return 0;
 }

-static struct nand_ecclayout hw_smallpage_ecclayout = {
-	.eccbytes = 6,
-	.eccpos = {8, 9, 10, 11, 12, 13 },
-	.oobfree = { {2, 6} }
-};
+static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
+		struct nand_chip *chip, uint8_t *buf, int page)
+{
+	struct pxa3xx_nand_info *info = mtd->priv;

-static struct nand_ecclayout hw_largepage_ecclayout = {
-	.eccbytes = 24,
-	.eccpos = {
-		40, 41, 42, 43, 44, 45, 46, 47,
-		48, 49, 50, 51, 52, 53, 54, 55,
-		56, 57, 58, 59, 60, 61, 62, 63},
-	.oobfree = { {2, 38} }
-};
+	chip->read_buf(mtd, buf, mtd->writesize);
+	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+	if (info->retcode == ERR_SBERR) {
+		switch (info->use_ecc) {
+			case 1:
+				mtd->ecc_stats.corrected ++;
+				break;
+
+			case 0:
+			default:
+				break;
+		}
+	}
+	else if (info->retcode == ERR_DBERR) {
+		int buf_blank;
+
+		buf_blank = is_buf_blank(buf, mtd->writesize);
+		if (!buf_blank)
+			mtd->ecc_stats.failed++;
+	}
+
+	return 0;
+}
+
+static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
+		struct nand_chip *chip, const uint8_t *buf)
+{
+	chip->write_buf(mtd, buf, mtd->writesize);
+	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+}
+
+static void pxa3xx_nand_erase_cmd(struct mtd_info *mtd, int page)
+{
+	struct nand_chip *chip = mtd->priv;
+	/* Send commands to erase a block */
+	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+}

-static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
-				 struct pxa3xx_nand_info *info)
+static int __devinit pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
 {
-	struct nand_chip *this = &info->nand_chip;
-
-	this->options = (info->reg_ndcr & NDCR_DWIDTH_C) ? NAND_BUSWIDTH_16: 0;
-
-	this->waitfunc		= pxa3xx_nand_waitfunc;
-	this->select_chip	= pxa3xx_nand_select_chip;
-	this->dev_ready		= pxa3xx_nand_dev_ready;
-	this->cmdfunc		= pxa3xx_nand_cmdfunc;
-	this->read_word		= pxa3xx_nand_read_word;
-	this->read_byte		= pxa3xx_nand_read_byte;
-	this->read_buf		= pxa3xx_nand_read_buf;
-	this->write_buf		= pxa3xx_nand_write_buf;
-	this->verify_buf	= pxa3xx_nand_verify_buf;
-
-	this->ecc.mode		= NAND_ECC_HW;
-	this->ecc.hwctl		= pxa3xx_nand_ecc_hwctl;
-	this->ecc.calculate	= pxa3xx_nand_ecc_calculate;
-	this->ecc.correct	= pxa3xx_nand_ecc_correct;
-	this->ecc.size		= info->page_size;
-
-	if (info->page_size == 2048)
-		this->ecc.layout = &hw_largepage_ecclayout;
+	struct mtd_info *mtd = info->mtd;
+	struct nand_chip *chip = mtd->priv;
+
+	/* use the common timing to make a try */
+	pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
+	chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
+	if (info->state & STATE_READY)
+		return 1;
 	else
-		this->ecc.layout = &hw_smallpage_ecclayout;
+		return 0;
+}

-	this->chip_delay = 25;
+static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd)
+{
+	struct pxa3xx_nand_info *info = mtd->priv;
+	struct platform_device *pdev = info->pdev;
+	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
+	const struct pxa3xx_nand_flash *f = NULL;
+	struct nand_chip *chip = mtd->priv;
+	uint32_t id = -1;
+	int i, ret;
+
+	if (pdata->keep_config)
+		if (pxa3xx_nand_detect_config(info) == 0)
+			return 0;
+
+	ret = pxa3xx_nand_sensing(info);
+	if (!ret) {
+		kfree(mtd);
+		info->mtd = NULL;
+		printk(KERN_INFO "There is no nand chip on cs 0!\n");
+
+		return -EINVAL;
+	}
+
+	chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
+	id = *((uint16_t *)(info->data_buff));
+	if (id != 0)
+		printk(KERN_INFO "Detect a flash id %x\n", id);
+	else {
+		kfree(mtd);
+		info->mtd = NULL;
+		printk(KERN_WARNING "Read out ID 0, potential timing set wrong!!\n");
+
+		return -EINVAL;
+	}
+
+	for (i=0; i<ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1; i++) {
+		if (i < pdata->num_flash)
+			f = pdata->flash + i;
+		else
+			f = &builtin_flash_types[i - pdata->num_flash + 1];
+
+		/* find the chip in default list */
+		if (f->chip_id == id) {
+			pxa3xx_nand_config_flash(info, f);
+			mtd->writesize = f->page_size;
+			mtd->writesize_shift = ffs(mtd->writesize) - 1;
+			mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
+			mtd->oobsize = mtd->writesize / 32;
+			mtd->erasesize = f->page_size * f->page_per_block;
+			mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
+			mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
+
+			mtd->name = mtd_names[0];
+			break;
+		}
+	}
+
+	if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash)) {
+		kfree(mtd);
+		info->mtd = NULL;
+		printk(KERN_ERR "ERROR!! flash not defined!!!\n");
+
+		return -EINVAL;
+	}
+
+	chip->ecc.mode = NAND_ECC_HW;
+	chip->ecc.size = f->page_size;
+	chip->chipsize 	= (uint64_t)f->num_blocks * f->page_per_block
+				* f->page_size;
+	mtd->size = chip->chipsize;
+
+	/* Calculate the address shift from the page size */
+	chip->page_shift = ffs(mtd->writesize) - 1;
+	chip->pagemask = mtd_div_by_ws(chip->chipsize, mtd) - 1;
+	chip->numchips = 1;
+	chip->bbt_erase_shift = chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
+
+	chip->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
+	chip->options |= NAND_NO_AUTOINCR;
+	chip->options |= NAND_NO_READRDY;
+	chip->options |= NAND_USE_FLASH_BBT;
+
+	return nand_scan_tail(mtd);
 }

 static int alloc_nand_resource(struct platform_device *pdev)
 {
-	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 	struct pxa3xx_nand_info *info;
+	struct nand_chip *chip;
 	struct mtd_info *mtd;
 	struct resource *r;
 	int ret, irq;
@@ -969,12 +1033,31 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 	}

 	info = (struct pxa3xx_nand_info *)(&mtd[1]);
+	chip = (struct nand_chip *)(&mtd[1]);
 	info->pdev = pdev;
-
-	mtd->priv = info;
 	info->mtd = mtd;
+	mtd->priv = info;
 	mtd->owner = THIS_MODULE;

+	chip->ecc.read_page	= pxa3xx_nand_read_page_hwecc;
+	chip->ecc.write_page	= pxa3xx_nand_write_page_hwecc;
+	chip->ecc.hwctl		= pxa3xx_nand_ecc_hwctl;
+	chip->ecc.calculate	= pxa3xx_nand_ecc_calculate;
+	chip->ecc.correct	= pxa3xx_nand_ecc_correct;
+	chip->controller        = &info->controller;
+	chip->waitfunc		= pxa3xx_nand_waitfunc;
+	chip->select_chip	= pxa3xx_nand_select_chip;
+	chip->dev_ready		= pxa3xx_nand_dev_ready;
+	chip->cmdfunc		= pxa3xx_nand_cmdfunc;
+	chip->read_word		= pxa3xx_nand_read_word;
+	chip->read_byte		= pxa3xx_nand_read_byte;
+	chip->read_buf		= pxa3xx_nand_read_buf;
+	chip->write_buf		= pxa3xx_nand_write_buf;
+	chip->verify_buf	= pxa3xx_nand_verify_buf;
+	chip->erase_cmd		= pxa3xx_nand_erase_cmd;
+
+	spin_lock_init(&chip->controller->lock);
+	init_waitqueue_head(&chip->controller->wq);
 	info->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(info->clk)) {
 		dev_err(&pdev->dev, "failed to get nand clock\n");
@@ -1042,21 +1125,11 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		goto fail_free_buf;
 	}

-	ret = pxa3xx_nand_detect_flash(info, pdata);
-	if (ret) {
-		dev_err(&pdev->dev, "failed to detect flash\n");
-		ret = -ENODEV;
-		goto fail_free_irq;
-	}
-
-	pxa3xx_nand_init_mtd(mtd, info);
 	platform_set_drvdata(pdev, info);
-
 	return 0;

-fail_free_irq:
-	free_irq(irq, info);
 fail_free_buf:
+	free_irq(irq, info);
 	if (use_dma) {
 		pxa_free_dma(info->data_dma_ch);
 		dma_free_coherent(&pdev->dev, info->data_buff_size,
@@ -1124,7 +1197,7 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 		return ret;

 	info = platform_get_drvdata(pdev);
-	if (nand_scan(info->mtd, 1)) {
+	if (pxa3xx_nand_scan(info->mtd)) {
 		dev_err(&pdev->dev, "failed to scan nand\n");
 		pxa3xx_nand_remove(pdev);
 		return -ENODEV;
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 09:41:47 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 21:41:47 +0800
Subject: [PATCH 12/29] pxa3xx_nand: clean the keep configure code
Message-ID: <mailman.113.1280296715.27306.linux-arm-kernel@lists.infradead.org>

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa3xx_nand.h |    1 +
 drivers/mtd/nand/pxa3xx_nand.c               |  107 +++++++++-----------------
 2 files changed, 38 insertions(+), 70 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index 0bf1bcf..6d9212b 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -30,6 +30,7 @@ struct pxa3xx_nand_cmdset {
 };

 struct pxa3xx_nand_flash {
+	char		*name;
 	uint32_t	chip_id;
 	uint16_t	page_per_block; /* Pages per block (PG_PER_BLK) */
 	uint16_t 	page_size;	/* Page size in bytes (PAGE_SZ) */
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 617bc69..d4e34aa 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -214,15 +214,15 @@ static struct pxa3xx_nand_timing __devinitdata
timing[] = {
 #define NAND_SETTING_MICRON      &default_cmdset, &timing[2]
 #define NAND_SETTING_ST          &default_cmdset, &timing[3]
 static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
-	{      0,   0, 2048,  8,  8,    0, NAND_SETTING_DEFAULT, },
-	{ 0x46ec,  32,  512, 16, 16, 4096, NAND_SETTING_SAMSUNG, },
-	{ 0xdaec,  64, 2048,  8,  8, 2048, NAND_SETTING_SAMSUNG, },
-	{ 0xd7ec, 128, 4096,  8,  8, 8192, NAND_SETTING_SAMSUNG, },
-	{ 0xa12c,  64, 2048,  8,  8, 1024, NAND_SETTING_MICRON, },
-	{ 0xb12c,  64, 2048, 16, 16, 1024, NAND_SETTING_MICRON, },
-	{ 0xdc2c,  64, 2048,  8,  8, 4096, NAND_SETTING_MICRON, },
-	{ 0xcc2c,  64, 2048, 16, 16, 4096, NAND_SETTING_MICRON, },
-	{ 0xba20,  64, 2048, 16, 16, 2048, NAND_SETTING_ST, },
+{ "DEFAULT FLASH",      0,   0, 2048,  8,  8,    0, NAND_SETTING_DEFAULT, },
+{ "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, NAND_SETTING_SAMSUNG, },
+{ "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, NAND_SETTING_SAMSUNG, },
+{ "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, NAND_SETTING_SAMSUNG, },
+{ "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, NAND_SETTING_MICRON, },
+{ "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, NAND_SETTING_MICRON, },
+{ "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, 4096, NAND_SETTING_MICRON, },
+{ "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, 4096, NAND_SETTING_MICRON, },
+{ "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, NAND_SETTING_ST, },
 };

 static const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
@@ -758,7 +758,6 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	/* calculate flash information */
 	info->cmdset = f->cmdset;
 	info->page_size = f->page_size;
-	info->oob_buff = info->data_buff + f->page_size;
 	info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;

 	/* calculate addressing information */
@@ -788,44 +787,12 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
 {
 	uint32_t ndcr = nand_readl(info, NDCR);
-	struct nand_flash_dev *type = NULL;
-	uint32_t id = -1, page_per_block, num_blocks;
-	int i;

-	page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
 	info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
 	/* set info fields needed to read id */
 	info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
 	info->reg_ndcr = ndcr;

-	pxa3xx_nand_cmdfunc(info->mtd, NAND_CMD_READID, 0, 0);
-	id = *((uint16_t *)(info->data_buff));
-	if (id == 0)
-		return -ENODEV;
-
-	/* Lookup the flash id */
-	for (i = 0; nand_flash_ids[i].name != NULL; i++) {
-		if (id == nand_flash_ids[i].id) {
-			type =  &nand_flash_ids[i];
-			break;
-		}
-	}
-
-	if (!type)
-		return -ENODEV;
-
-	/* fill the missing flash information */
-	i = __ffs(page_per_block * info->page_size);
-	num_blocks = type->chipsize << (20 - i);
-
-	/* calculate addressing information */
-	info->col_addr_cycles = (info->page_size == 2048) ? 2 : 1;
-
-	if (num_blocks * page_per_block > 65536)
-		info->row_addr_cycles = 3;
-	else
-		info->row_addr_cycles = 2;
-
 	info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
 	info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
 	info->cmdset = &default_cmdset;
@@ -937,14 +904,17 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 	struct pxa3xx_nand_info *info = mtd->priv;
 	struct platform_device *pdev = info->pdev;
 	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
+	struct nand_flash_dev pxa3xx_flash_ids[2] = {{NULL,}, {NULL,}};
 	const struct pxa3xx_nand_flash *f = NULL;
 	struct nand_chip *chip = mtd->priv;
 	uint32_t id = -1;
+	uint64_t chipsize;
 	int i, ret;

-	if (pdata->keep_config)
+	if (pdata->keep_config) {
 		if (pxa3xx_nand_detect_config(info) == 0)
-			return 0;
+			goto KEEP_CONFIG;
+	}

 	ret = pxa3xx_nand_sensing(info);
 	if (!ret) {
@@ -974,22 +944,11 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 			f = &builtin_flash_types[i - pdata->num_flash + 1];

 		/* find the chip in default list */
-		if (f->chip_id == id) {
-			pxa3xx_nand_config_flash(info, f);
-			mtd->writesize = f->page_size;
-			mtd->writesize_shift = ffs(mtd->writesize) - 1;
-			mtd->writesize_mask = (1 << mtd->writesize_shift) - 1;
-			mtd->oobsize = mtd->writesize / 32;
-			mtd->erasesize = f->page_size * f->page_per_block;
-			mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
-			mtd->erasesize_mask = (1 << mtd->erasesize_shift) - 1;
-
-			mtd->name = mtd_names[0];
+		if (f->chip_id == id)
 			break;
-		}
 	}

-	if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash)) {
+	if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
 		kfree(mtd);
 		info->mtd = NULL;
 		printk(KERN_ERR "ERROR!! flash not defined!!!\n");
@@ -997,20 +956,28 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 		return -EINVAL;
 	}

+	pxa3xx_nand_config_flash(info, f);
+	pxa3xx_flash_ids[0].name = f->name;
+	pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff;
+	pxa3xx_flash_ids[0].pagesize = f->page_size;
+	chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
+	pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
+	pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
+	pxa3xx_flash_ids[0].options = (f->flash_width == 16) ? NAND_BUSWIDTH_16 : 0;
+KEEP_CONFIG:
+	if (nand_scan_ident(mtd, 1, pxa3xx_flash_ids))
+		return -ENODEV;
+	/* calculate addressing information */
+	info->col_addr_cycles = (mtd->writesize >= 2048) ? 2 : 1;
+	info->oob_buff = info->data_buff + mtd->writesize;
+	if ((mtd->size >> chip->page_shift) > 65536)
+		info->row_addr_cycles = 3;
+	else
+		info->row_addr_cycles = 2;
+	mtd->name = mtd_names[0];
 	chip->ecc.mode = NAND_ECC_HW;
-	chip->ecc.size = f->page_size;
-	chip->chipsize 	= (uint64_t)f->num_blocks * f->page_per_block
-				* f->page_size;
-	mtd->size = chip->chipsize;
-
-	/* Calculate the address shift from the page size */
-	chip->page_shift = ffs(mtd->writesize) - 1;
-	chip->pagemask = mtd_div_by_ws(chip->chipsize, mtd) - 1;
-	chip->numchips = 1;
-	chip->bbt_erase_shift = chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
-
-	chip->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16: 0;
-	chip->options |= NAND_NO_AUTOINCR;
+	chip->ecc.size = mtd->writesize;
+	chip->options = (info->reg_ndcr & NDCR_DWIDTH_M) ? NAND_BUSWIDTH_16: 0;
 	chip->options |= NAND_NO_READRDY;
 	chip->options |= NAND_USE_FLASH_BBT;

-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 09:32:09 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 21:32:09 +0800
Subject: [PATCH 09/29] pxa3xx_nand: unify prepare command
Message-ID: <mailman.115.1280296738.27306.linux-arm-kernel@lists.infradead.org>

Make the interface simpler which could make both debug
and enhancement easier.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  261 +++++++++++++++++++++-------------------
 1 files changed, 135 insertions(+), 126 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 5dd03ea..e7b54dd 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -28,6 +28,7 @@

 #define	CHIP_DELAY_TIMEOUT	(2 * HZ/10)
 #define NAND_STOP_DELAY		(2 * HZ/50)
+#define PAGE_CHUNK_SIZE		(2048)

 /* registers and bit definitions */
 #define NDCR		(0x00) /* Control register */
@@ -78,6 +79,7 @@
 #define NDSR_RDDREQ		(0x1 << 1)
 #define NDSR_WRCMDREQ		(0x1)

+#define NDCB0_ST_ROW_EN         (0x1 << 26)
 #define NDCB0_AUTO_RS		(0x1 << 25)
 #define NDCB0_CSEL		(0x1 << 24)
 #define NDCB0_CMD_TYPE_MASK	(0x7 << 21)
@@ -290,7 +292,7 @@ static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
 	uint32_t ndcr;

 	ndcr = info->reg_ndcr;
-	ndcr |= NDCR_ECC_EN;
+	ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
 	ndcr |= info->use_dma ? NDCR_DMA_EN : NDCR_STOP_ON_UNCOR;
 	ndcr |= NDCR_ND_RUN;

@@ -319,65 +321,6 @@ static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
 	}
 }

-static void prepare_read_prog_cmd(struct pxa3xx_nand_info *info,
-		uint16_t cmd, int column, int page_addr)
-{
-	const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
-	pxa3xx_set_datasize(info);
-
-	/* generate values for NDCBx registers */
-	info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
-	info->ndcb1 = 0;
-	info->ndcb2 = 0;
-	info->ndcb0 |= NDCB0_ADDR_CYC(info->row_addr_cycles + info->col_addr_cycles);
-
-	if (info->col_addr_cycles == 2) {
-		/* large block, 2 cycles for column address
-		 * row address starts from 3rd cycle
-		 */
-		info->ndcb1 |= page_addr << 16;
-		if (info->row_addr_cycles == 3)
-			info->ndcb2 = (page_addr >> 16) & 0xff;
-	} else
-		/* small block, 1 cycles for column address
-		 * row address starts from 2nd cycle
-		 */
-		info->ndcb1 = page_addr << 8;
-
-	if (cmd == cmdset->program)
-		info->ndcb0 |= NDCB0_CMD_TYPE(1) | NDCB0_AUTO_RS;
-}
-
-static void prepare_erase_cmd(struct pxa3xx_nand_info *info,
-			uint16_t cmd, int page_addr)
-{
-	info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
-	info->ndcb0 |= NDCB0_CMD_TYPE(2) | NDCB0_AUTO_RS | NDCB0_ADDR_CYC(3);
-	info->ndcb1 = page_addr;
-	info->ndcb2 = 0;
-}
-
-static void prepare_other_cmd(struct pxa3xx_nand_info *info, uint16_t cmd)
-{
-	const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
-
-	info->ndcb0 = cmd | ((cmd & 0xff00) ? NDCB0_DBC : 0);
-	info->ndcb1 = 0;
-	info->ndcb2 = 0;
-
-	info->oob_size = 0;
-	if (cmd == cmdset->read_id) {
-		info->ndcb0 |= NDCB0_CMD_TYPE(3);
-		info->data_size = 8;
-	} else if (cmd == cmdset->read_status) {
-		info->ndcb0 |= NDCB0_CMD_TYPE(4);
-		info->data_size = 8;
-	} else if (cmd == cmdset->reset || cmd == cmdset->lock ||
-		   cmd == cmdset->unlock) {
-		info->ndcb0 |= NDCB0_CMD_TYPE(5);
-	}
-}
-
 static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
 {
 	uint32_t ndcr;
@@ -515,95 +458,165 @@ static inline int is_buf_blank(uint8_t *buf, size_t len)
 	return 1;
 }

-static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
-				int column, int page_addr)
+static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
+		uint16_t column, int page_addr)
 {
-	struct pxa3xx_nand_info *info = mtd->priv;
-	const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
-	int ret, exec_cmd = 0;
+	uint16_t cmd;
+	int addr_cycle, exec_cmd, ndcb0;
+	struct mtd_info *mtd = info->mtd;

-	info->use_dma = (use_dma) ? 1 : 0;
-	info->use_ecc = 0;
-	info->data_size = 0;
-	info->state = 0;
+	ndcb0 = 0;
+	addr_cycle = 0;
+	exec_cmd = 1;
+
+	/* reset data and oob column point to handle data */
+	info->buf_start		= 0;
+	info->buf_count		= 0;
+	info->oob_size		= 0;
+	info->use_ecc		= 0;

 	switch (command) {
+	case NAND_CMD_READ0:
+	case NAND_CMD_PAGEPROG:
+		info->use_ecc = 1;
 	case NAND_CMD_READOOB:
-		/* disable HW ECC to get all the OOB data */
-		info->buf_count = mtd->writesize + mtd->oobsize;
-		info->buf_start = mtd->writesize + column;
-		memset(info->data_buff, 0xFF, info->buf_count);
-
-		prepare_read_prog_cmd(info, cmdset->read1, column, page_addr);
-		/* We only are OOB, so if the data has error, does not matter */
-		if (info->retcode == ERR_DBERR)
-			info->retcode = ERR_NONE;
-
-		exec_cmd = 1;
+		pxa3xx_set_datasize(info);
+		break;
+	case NAND_CMD_SEQIN:
+		exec_cmd = 0;
+		break;
+	default:
+		info->ndcb1 = 0;
+		info->ndcb2 = 0;
 		break;
+	}
+
+	info->ndcb0 = ndcb0;
+	addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
+			+ info->col_addr_cycles);

+	switch (command) {
+	case NAND_CMD_READOOB:
 	case NAND_CMD_READ0:
-		info->use_ecc = 1;
-		info->retcode = ERR_NONE;
-		info->buf_start = column;
-		info->buf_count = mtd->writesize + mtd->oobsize;
-		memset(info->data_buff, 0xFF, info->buf_count);
+		cmd  = info->cmdset->read1;
+		if (command == NAND_CMD_READOOB)
+			info->buf_start = mtd->writesize + column;
+		else
+			info->buf_start = column;

-		prepare_read_prog_cmd(info, cmdset->read1, column, page_addr);
-		if (info->retcode == ERR_DBERR) {
-			/* for blank page (all 0xff), HW will calculate its ECC as
-			 * 0, which is different from the ECC information within
-			 * OOB, ignore such double bit errors
-			 */
-			if (is_buf_blank(info->data_buff, mtd->writesize))
-				info->retcode = ERR_NONE;
-		}
+		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
+			info->ndcb0 |= NDCB0_CMD_TYPE(0)
+					| addr_cycle
+					| (cmd & NDCB0_CMD1_MASK);
+		else
+			info->ndcb0 |= NDCB0_CMD_TYPE(0)
+					| NDCB0_DBC
+					| addr_cycle
+					| cmd;

-		exec_cmd = 1;
-		break;
 	case NAND_CMD_SEQIN:
-		info->buf_start = column;
+		/* small page addr setting */
+		if (unlikely(info->page_size < PAGE_CHUNK_SIZE)) {
+			info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
+					| (column & 0xFF);
+
+			info->ndcb2 = 0;
+		}
+		else {
+			info->ndcb1 = ((page_addr & 0xFFFF) << 16)
+					| (column & 0xFFFF);
+
+			if (page_addr & 0xFF0000)
+				info->ndcb2 = (page_addr & 0xFF0000) >> 16;
+			else
+				info->ndcb2 = 0;
+		}
+
 		info->buf_count = mtd->writesize + mtd->oobsize;
-		memset(info->data_buff, 0xff, info->buf_count);
+		memset(info->data_buff, 0xFF, info->buf_count);

-		/* save column/page_addr for next CMD_PAGEPROG */
-		info->seqin_column = column;
-		info->seqin_page_addr = page_addr;
 		break;
+
 	case NAND_CMD_PAGEPROG:
-		info->use_ecc = (info->seqin_column >= mtd->writesize) ? 0 : 1;
+		if (is_buf_blank(info->data_buff, (mtd->writesize + mtd->oobsize))) {
+			exec_cmd = 0;
+			break;
+		}

-		prepare_read_prog_cmd(info, cmdset->program,
-				info->seqin_column, info->seqin_page_addr);
+		cmd = info->cmdset->program;
 		info->state |= STATE_IS_WRITE;
-		exec_cmd = 1;
-		break;
-	case NAND_CMD_ERASE1:
-		prepare_erase_cmd(info, cmdset->erase, page_addr);
-		exec_cmd = 1;
-		break;
-	case NAND_CMD_ERASE2:
+		info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
+				| NDCB0_AUTO_RS
+				| NDCB0_ST_ROW_EN
+				| NDCB0_DBC
+				| cmd
+				| addr_cycle;
 		break;
+
 	case NAND_CMD_READID:
+		cmd = info->cmdset->read_id;
+		info->buf_count = info->read_id_bytes;
+		info->ndcb0 |= NDCB0_CMD_TYPE(3)
+				| NDCB0_ADDR_CYC(1)
+				| cmd;
+
+		info->data_size = 8;
+		break;
 	case NAND_CMD_STATUS:
-		info->use_dma = 0;	/* force PIO read */
-		info->buf_start = 0;
-		info->buf_count = (command == NAND_CMD_READID) ?
-				info->read_id_bytes : 1;
-
-		prepare_other_cmd(info, (command == NAND_CMD_READID) ?
-				cmdset->read_id : cmdset->read_status);
-		exec_cmd = 1;
+		cmd = info->cmdset->read_status;
+		info->buf_count = 1;
+		info->ndcb0 |= NDCB0_CMD_TYPE(4)
+				| NDCB0_ADDR_CYC(1)
+				| cmd;
+
+		info->data_size = 8;
+		break;
+
+	case NAND_CMD_ERASE1:
+		cmd = info->cmdset->erase;
+		info->ndcb0 |= NDCB0_CMD_TYPE(2)
+				| NDCB0_AUTO_RS
+				| NDCB0_ADDR_CYC(3)
+				| NDCB0_DBC
+				| cmd;
+		info->ndcb1 = page_addr;
+		info->ndcb2 = 0;
+
 		break;
 	case NAND_CMD_RESET:
-		prepare_other_cmd(info, cmdset->reset);
-		exec_cmd = 1;
+		cmd = info->cmdset->reset;
+		info->ndcb0 |= NDCB0_CMD_TYPE(5)
+				| cmd;
+
+		break;
+
+	case NAND_CMD_ERASE2:
+		exec_cmd = 0;
 		break;
+
 	default:
-		printk(KERN_ERR "non-supported command.\n");
+		exec_cmd = 0;
+		printk(KERN_ERR "pxa3xx-nand: non-supported command %x\n", command);
 		break;
 	}

+	return exec_cmd;
+}
+
+static void pxa3xx_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
+		int column, int page_addr)
+{
+	struct pxa3xx_nand_info *info = mtd->priv;
+	int ret, exec_cmd;
+
+	/* if this is a x16 device ,then convert the input
+	 * "byte" address into a "word" address appropriate
+	 * for indexing a word-oriented device
+	 */
+	if (info->reg_ndcr & NDCR_DWIDTH_M)
+		column /= 2;
+
+	exec_cmd = prepare_command_pool(info, command, column, page_addr);
 	if (exec_cmd) {
 		init_completion(&info->cmd_complete);
 		info->state |= STATE_CMD_PREPARED;
@@ -618,10 +631,6 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 		pxa3xx_nand_stop(info);
 		disable_int(info, NDCR_INT_MASK);
 		info->state &= ~STATE_CMD_PREPARED;
-		if (info->retcode == ERR_DBERR) {
-			printk(KERN_ERR "double bit error @ page %08x\n", page_addr);
-			info->retcode = ERR_NONE;
-		}
 	}
 }

-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 09:46:47 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 21:46:47 +0800
Subject: [PATCH 13/29] pxa3xx_nand: add two chip select
Message-ID: <mailman.116.1280296750.27306.linux-arm-kernel@lists.infradead.org>

Current pxa3xx_nand controller has two chip select which
both be workable. This patch enable this feature.

Update platform driver to support this feature.

Another notice should be taken that:
When you want to use this feature, you should not enable the
keep configuration feature, for two chip select could be
attached with different nand chip. The different page size
and timing requirement make the keep configuration impossible.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/mach-mmp/aspenite.c                 |    4 +-
 arch/arm/mach-mmp/avengers_lite.c            |   50 ++
 arch/arm/mach-pxa/cm-x300.c                  |    4 +-
 arch/arm/mach-pxa/colibri-pxa3xx.c           |    4 +-
 arch/arm/mach-pxa/littleton.c                |    4 +-
 arch/arm/mach-pxa/mxm8x10.c                  |    8 +-
 arch/arm/mach-pxa/raumfeld.c                 |    4 +-
 arch/arm/mach-pxa/zylonite.c                 |    4 +-
 arch/arm/plat-pxa/include/plat/pxa3xx_nand.h |    5 +-
 drivers/mtd/nand/pxa3xx_nand.c               |  770 +++++++++++++-------------
 10 files changed, 463 insertions(+), 394 deletions(-)

diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 244655d..81ad58d 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -126,8 +126,8 @@ static struct mtd_partition aspenite_nand_partitions[] = {

 static struct pxa3xx_nand_platform_data aspenite_nand_info = {
 	.enable_arbiter	= 1,
-	.parts		= aspenite_nand_partitions,
-	.nr_parts	= ARRAY_SIZE(aspenite_nand_partitions),
+	.parts[0]	= aspenite_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(aspenite_nand_partitions),
 };

 static struct i2c_board_info aspenite_i2c_info[] __initdata = {
diff --git a/arch/arm/mach-mmp/avengers_lite.c
b/arch/arm/mach-mmp/avengers_lite.c
index 8c3fa5d..a828b1c 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -32,12 +32,62 @@ static unsigned long
avengers_lite_pin_config_V16F[] __initdata = {
 	GPIO89_UART2_RXD,
 };

+static struct mtd_partition avengers_nand_partitions_0[] = {
+	{
+		.name		= "bootloader",
+		.offset		= 0,
+		.size		= SZ_1M,
+		.mask_flags	= MTD_WRITEABLE,
+	}, {
+		.name		= "kernel",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= (SZ_2M + SZ_1M),
+	}, {
+		.name		= "mass0",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_48M,
+	}
+};
+
+static struct mtd_partition avengers_nand_partitions_1[] = {
+	{
+		.name		= "reserved",
+		.offset		= 0,
+		.size		= SZ_2M,
+		.mask_flags	= MTD_WRITEABLE,
+	}, {
+		.name		= "filesystem",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_512M,
+	}, {
+		.name		= "mass1",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_16M,
+	}, {
+		.name		= "mass2",
+		.offset		= MTDPART_OFS_APPEND,
+		.size		= SZ_256M,
+	}
+};
+
+static struct pxa3xx_nand_platform_data avengers_nand_info;
+static void __init avengers_init_flash(void)
+{
+	avengers_nand_info.parts[0] = avengers_nand_partitions_0;
+	avengers_nand_info.nr_parts[0] = ARRAY_SIZE(avengers_nand_partitions_0);
+	avengers_nand_info.parts[1] = avengers_nand_partitions_1;
+	avengers_nand_info.nr_parts[1] = ARRAY_SIZE(avengers_nand_partitions_1);
+	avengers_nand_info.enable_arbiter = 1;
+	pxa168_add_nand(&avengers_nand_info);
+}
+
 static void __init avengers_lite_init(void)
 {
 	mfp_config(ARRAY_AND_SIZE(avengers_lite_pin_config_V16F));

 	/* on-chip devices */
 	pxa168_add_uart(2);
+	avengers_init_flash();
 }

 MACHINE_START(AVENGERS_LITE, "PXA168 Avengers lite Development Platform")
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index fdda6be..ce1f6d3 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -419,8 +419,8 @@ static struct mtd_partition cm_x300_nand_partitions[] = {
 static struct pxa3xx_nand_platform_data cm_x300_nand_info = {
 	.enable_arbiter	= 1,
 	.keep_config	= 1,
-	.parts		= cm_x300_nand_partitions,
-	.nr_parts	= ARRAY_SIZE(cm_x300_nand_partitions),
+	.parts[0]	= cm_x300_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(cm_x300_nand_partitions),
 };

 static void __init cm_x300_init_nand(void)
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c
b/arch/arm/mach-pxa/colibri-pxa3xx.c
index 199afa2..b33559c 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -188,8 +188,8 @@ static struct mtd_partition colibri_nand_partitions[] = {
 static struct pxa3xx_nand_platform_data colibri_nand_info = {
 	.enable_arbiter	= 1,
 	.keep_config	= 1,
-	.parts		= colibri_nand_partitions,
-	.nr_parts	= ARRAY_SIZE(colibri_nand_partitions),
+	.parts[0]	= colibri_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(colibri_nand_partitions),
 };

 void __init colibri_pxa3xx_init_nand(void)
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 9b90461..717cf92 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -325,8 +325,8 @@ static struct mtd_partition littleton_nand_partitions[] = {

 static struct pxa3xx_nand_platform_data littleton_nand_info = {
 	.enable_arbiter	= 1,
-	.parts		= littleton_nand_partitions,
-	.nr_parts	= ARRAY_SIZE(littleton_nand_partitions),
+	.parts[0]	= littleton_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(littleton_nand_partitions),
 };

 static void __init littleton_init_nand(void)
diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c
index 462167a..66c2086 100644
--- a/arch/arm/mach-pxa/mxm8x10.c
+++ b/arch/arm/mach-pxa/mxm8x10.c
@@ -389,10 +389,10 @@ static struct mtd_partition mxm_8x10_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data mxm_8x10_nand_info = {
-	.enable_arbiter = 1,
-	.keep_config = 1,
-	.parts = mxm_8x10_nand_partitions,
-	.nr_parts = ARRAY_SIZE(mxm_8x10_nand_partitions)
+	.enable_arbiter	= 1,
+	.keep_config	= 1,
+	.parts[0]	= mxm_8x10_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(mxm_8x10_nand_partitions)
 };

 static void __init mxm_8x10_nand_init(void)
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index d4b61b3..df75d4d 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -350,8 +350,8 @@ static struct mtd_partition raumfeld_nand_partitions[] = {
 static struct pxa3xx_nand_platform_data raumfeld_nand_info = {
 	.enable_arbiter	= 1,
 	.keep_config	= 1,
-	.parts		= raumfeld_nand_partitions,
-	.nr_parts	= ARRAY_SIZE(raumfeld_nand_partitions),
+	.parts[0]	= raumfeld_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(raumfeld_nand_partitions),
 };

 /**
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index c479cbe..9e5c6cd 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -356,8 +356,8 @@ static struct mtd_partition zylonite_nand_partitions[] = {

 static struct pxa3xx_nand_platform_data zylonite_nand_info = {
 	.enable_arbiter	= 1,
-	.parts		= zylonite_nand_partitions,
-	.nr_parts	= ARRAY_SIZE(zylonite_nand_partitions),
+	.parts[0]	= zylonite_nand_partitions,
+	.nr_parts[0]	= ARRAY_SIZE(zylonite_nand_partitions),
 };

 static void __init zylonite_init_nand(void)
diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index 6d9212b..cf42f97 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -41,6 +41,7 @@ struct pxa3xx_nand_flash {
 	struct pxa3xx_nand_timing *timing;	/* NAND Flash timing */
 };

+#define NUM_CHIP_SELECT		(2)
 struct pxa3xx_nand_platform_data {

 	/* the data flash bus is shared between the Static Memory
@@ -52,8 +53,8 @@ struct pxa3xx_nand_platform_data {
 	/* allow platform code to keep OBM/bootloader defined NFC config */
 	int	keep_config;

-	const struct mtd_partition		*parts;
-	unsigned int				nr_parts;
+	const struct mtd_partition		*parts[NUM_CHIP_SELECT];
+	unsigned int				nr_parts[NUM_CHIP_SELECT];

 	const struct pxa3xx_nand_flash * 	flash;
 	size_t					num_flash;
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index d4e34aa..3dea0fe 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -51,11 +51,9 @@
 #define NDCR_DWIDTH_M		(0x1 << 26)
 #define NDCR_PAGE_SZ		(0x1 << 24)
 #define NDCR_NCSX		(0x1 << 23)
-#define NDCR_STOP_ON_UNCOR	(0x1 << 22)
 #define NDCR_ND_MODE		(0x3 << 21)
-#define NDCR_NAND_MODE   	(0x0)
 #define NDCR_CLR_PG_CNT		(0x1 << 20)
-#define NDCR_CLR_ECC		(0x1 << 19)
+#define NDCR_STOP_ON_UNCOR	(0x1 << 19)
 #define NDCR_RD_ID_CNT_MASK	(0x7 << 16)
 #define NDCR_RD_ID_CNT(x)	(((x) << 16) & NDCR_RD_ID_CNT_MASK)

@@ -98,6 +96,8 @@

 #define nand_readl(info, off)		\
 	__raw_readl((info)->mmio_base + (off))
+#define get_mtd_by_info(info)		\
+	(struct mtd_info *)((void *)info - sizeof(struct mtd_info))

 /* error code and state */
 enum {
@@ -122,63 +122,64 @@ enum {

 struct pxa3xx_nand_info {
 	struct nand_chip	nand_chip;
-
-	struct nand_hw_control	controller;
-	struct platform_device	 *pdev;
 	struct pxa3xx_nand_cmdset *cmdset;
+	/* page size of attached chip */
+	uint16_t		page_size;
+	uint8_t			chip_select;
+	uint8_t			use_ecc;
+
+	/* calculated from pxa3xx_nand_flash data */
+	uint8_t			col_addr_cycles;
+	uint8_t			row_addr_cycles;
+	uint8_t			read_id_bytes;
+
+	/* cached register value */
+	uint32_t		reg_ndcr;
+	uint32_t		ndtr0cs0;
+	uint32_t		ndtr1cs0;

+	void			*nand_data;
+};
+
+struct pxa3xx_nand {
 	struct clk		*clk;
 	void __iomem		*mmio_base;
 	unsigned long		mmio_phys;
+	struct nand_hw_control	controller;
+	struct completion 	cmd_complete;
+	struct platform_device	 *pdev;

-	unsigned int 		buf_start;
-	unsigned int		buf_count;
-
-	struct mtd_info         *mtd;
 	/* DMA information */
 	int			drcmr_dat;
 	int			drcmr_cmd;
-
-	unsigned char		*data_buff;
-	unsigned char		*oob_buff;
-	dma_addr_t 		data_buff_phys;
-	size_t			data_buff_size;
 	int 			data_dma_ch;
-	struct pxa_dma_desc	*data_desc;
+	dma_addr_t 		data_buff_phys;
 	dma_addr_t 		data_desc_addr;
+	struct pxa_dma_desc	*data_desc;

-	uint32_t		reg_ndcr;
-
-	/* saved column/page_addr during CMD_SEQIN */
-	int			seqin_column;
-	int			seqin_page_addr;
+	struct pxa3xx_nand_info *info[NUM_CHIP_SELECT];
+	uint32_t		command;
+	uint16_t		data_size;	/* data size in FIFO */
+	uint16_t		oob_size;
+	uint32_t		bad_count;
+	unsigned char		*dma_buff;
+	unsigned char		*data_buff;
+	unsigned char		*oob_buff;
+	uint32_t		buf_start;
+	uint32_t		buf_count;
+	uint8_t			total_cmds;

 	/* relate to the command */
+	uint8_t			chip_select;
 	unsigned int		state;
-
 	int			use_ecc;	/* use HW ECC ? */
 	int			use_dma;	/* use DMA ? */
-
-	unsigned int		page_size;	/* page size of attached chip */
-	unsigned int		data_size;	/* data size in FIFO */
 	int 			retcode;
-	struct completion 	cmd_complete;

 	/* generated NDCBx register values */
 	uint32_t		ndcb0;
 	uint32_t		ndcb1;
 	uint32_t		ndcb2;
-
-	/* timing calcuted from setting */
-	uint32_t		ndtr0cs0;
-	uint32_t		ndtr1cs0;
-
-	/* calculated from pxa3xx_nand_flash data */
-	size_t		oob_size;
-	size_t		read_id_bytes;
-
-	unsigned int	col_addr_cycles;
-	unsigned int	row_addr_cycles;
 };

 static int use_dma = 1;
@@ -217,6 +218,7 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
 { "DEFAULT FLASH",      0,   0, 2048,  8,  8,    0, NAND_SETTING_DEFAULT, },
 { "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, NAND_SETTING_SAMSUNG, },
 { "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, NAND_SETTING_SAMSUNG, },
+{ "1GiB 8-bit",    0xd3ec, 128, 2048,  8,  8, 4096, NAND_SETTING_SAMSUNG, },
 { "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, NAND_SETTING_SAMSUNG, },
 { "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, NAND_SETTING_MICRON, },
 { "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, NAND_SETTING_MICRON, },
@@ -225,7 +227,7 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
 { "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, NAND_SETTING_ST, },
 };

-static const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
+static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};

 #define NDTR0_tCH(c)	(min((c), 7) << 19)
 #define NDTR0_tCS(c)	(min((c), 7) << 16)
@@ -244,9 +246,11 @@ static const char *mtd_names[] = {"pxa3xx_nand-0", NULL};
 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
 				   const struct pxa3xx_nand_timing *t)
 {
-	unsigned long nand_clk = clk_get_rate(info->clk);
+	struct pxa3xx_nand *nand = info->nand_data;
+	unsigned long nand_clk;
 	uint32_t ndtr0, ndtr1;

+	nand_clk = clk_get_rate(nand->clk);
 	ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
 		NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
 		NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
@@ -260,26 +264,27 @@ static void pxa3xx_nand_set_timing(struct
pxa3xx_nand_info *info,

 	info->ndtr0cs0 = ndtr0;
 	info->ndtr1cs0 = ndtr1;
-	nand_writel(info, NDTR0CS0, ndtr0);
-	nand_writel(info, NDTR1CS0, ndtr1);
+	nand_writel(nand, NDTR0CS0, ndtr0);
+	nand_writel(nand, NDTR1CS0, ndtr1);
 }

 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 {
+	struct pxa3xx_nand *nand = info->nand_data;
 	int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;

-	info->data_size = info->page_size;
+	nand->data_size = info->page_size;
 	if (!oob_enable) {
-		info->oob_size = 0;
+		nand->oob_size = 0;
 		return;
 	}

 	switch (info->page_size) {
 	case 2048:
-		info->oob_size = (info->use_ecc) ? 40 : 64;
+		nand->oob_size = (nand->use_ecc) ? 40 : 64;
 		break;
 	case 512:
-		info->oob_size = (info->use_ecc) ? 8 : 16;
+		nand->oob_size = (nand->use_ecc) ? 8 : 16;
 		break;
 	}
 }
@@ -290,22 +295,24 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
  * We enable all the interrupt at the same time, and
  * let pxa3xx_nand_irq to handle all logic.
  */
-static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
+static void pxa3xx_nand_start(struct pxa3xx_nand *nand)
 {
+	struct pxa3xx_nand_info *info;
 	uint32_t ndcr;

+	info = nand->info[nand->chip_select];
 	ndcr = info->reg_ndcr;
-	ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
-	ndcr |= info->use_dma ? NDCR_DMA_EN : NDCR_STOP_ON_UNCOR;
+	ndcr |= nand->use_ecc ? NDCR_ECC_EN : 0;
+	ndcr |= nand->use_dma ? NDCR_DMA_EN : NDCR_STOP_ON_UNCOR;
 	ndcr |= NDCR_ND_RUN;

 	/* clear status bits and run */
-	nand_writel(info, NDCR, 0);
-	nand_writel(info, NDSR, NDSR_MASK);
-	nand_writel(info, NDCR, ndcr);
+	nand_writel(nand, NDCR, 0);
+	nand_writel(nand, NDSR, NDSR_MASK);
+	nand_writel(nand, NDCR, ndcr);
 }

-static void pxa3xx_nand_stop(struct pxa3xx_nand_info *info)
+static void pxa3xx_nand_stop(struct pxa3xx_nand *nand)
 {
 	uint32_t ndcr;
 	int timeout = NAND_STOP_DELAY;
@@ -313,146 +320,149 @@ static void pxa3xx_nand_stop(struct
pxa3xx_nand_info *info)
 	/* wait RUN bit in NDCR become 0 */
 	do {
 		/* clear status bits */
-		nand_writel(info, NDSR, NDSR_MASK);
-		ndcr = nand_readl(info, NDCR);
+		nand_writel(nand, NDSR, NDSR_MASK);
+		ndcr = nand_readl(nand, NDCR);
 		udelay(1);
 	} while ((ndcr & NDCR_ND_RUN) && (timeout -- > 0));

 	if (timeout <= 0) {
 		ndcr &= ~(NDCR_ND_RUN);
-		nand_writel(info, NDCR, ndcr);
+		nand_writel(nand, NDCR, ndcr);
 	}
 }

-static void enable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
+static void enable_int(struct pxa3xx_nand *nand, uint32_t int_mask)
 {
 	uint32_t ndcr;

-	ndcr = nand_readl(info, NDCR);
-	nand_writel(info, NDCR, ndcr & ~int_mask);
+	ndcr = nand_readl(nand, NDCR);
+	nand_writel(nand, NDCR, ndcr & ~int_mask);
 }

-static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
+static void disable_int(struct pxa3xx_nand *nand, uint32_t int_mask)
 {
 	uint32_t ndcr;

-	ndcr = nand_readl(info, NDCR);
-	nand_writel(info, NDCR, ndcr | int_mask);
+	ndcr = nand_readl(nand, NDCR);
+	nand_writel(nand, NDCR, ndcr | int_mask);
 }

-static void handle_data_pio(struct pxa3xx_nand_info *info)
+static void handle_data_pio(struct pxa3xx_nand *nand)
 {
-	if (info->state & STATE_IS_WRITE) {
-		__raw_writesl(info->mmio_base + NDDB, info->data_buff,
-				DIV_ROUND_UP(info->data_size, 4));
-		if (info->oob_size > 0)
-			__raw_writesl(info->mmio_base + NDDB, info->oob_buff,
-					DIV_ROUND_UP(info->oob_size, 4));
+	if (nand->state & STATE_IS_WRITE) {
+		__raw_writesl(nand->mmio_base + NDDB, nand->data_buff,
+				DIV_ROUND_UP(nand->data_size, 4));
+		if (nand->oob_size > 0)
+			__raw_writesl(nand->mmio_base + NDDB, nand->oob_buff,
+					DIV_ROUND_UP(nand->oob_size, 4));

 	}
 	else {
-		__raw_readsl(info->mmio_base + NDDB, info->data_buff,
-				DIV_ROUND_UP(info->data_size, 4));
-		if (info->oob_size > 0)
-			__raw_readsl(info->mmio_base + NDDB, info->oob_buff,
-					DIV_ROUND_UP(info->oob_size, 4));
+		__raw_readsl(nand->mmio_base + NDDB, nand->data_buff,
+				DIV_ROUND_UP(nand->data_size, 4));
+		if (nand->oob_size > 0)
+			__raw_readsl(nand->mmio_base + NDDB, nand->oob_buff,
+					DIV_ROUND_UP(nand->oob_size, 4));
 	}
 }

-static void start_data_dma(struct pxa3xx_nand_info *info, int dir_out)
+static void start_data_dma(struct pxa3xx_nand *nand, int dir_out)
 {
-	struct pxa_dma_desc *desc = info->data_desc;
-	int dma_len = ALIGN(info->data_size + info->oob_size, 32);
+	struct pxa_dma_desc *desc = nand->data_desc;
+	int dma_len = ALIGN(nand->data_size + nand->oob_size, 32);

 	desc->ddadr = DDADR_STOP;
 	desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;

 	if (dir_out) {
-		desc->dsadr = info->data_buff_phys;
-		desc->dtadr = info->mmio_phys + NDDB;
+		desc->dsadr = nand->data_buff_phys;
+		desc->dtadr = nand->mmio_phys + NDDB;
 		desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
 	} else {
-		desc->dtadr = info->data_buff_phys;
-		desc->dsadr = info->mmio_phys + NDDB;
+		desc->dtadr = nand->data_buff_phys;
+		desc->dsadr = nand->mmio_phys + NDDB;
 		desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
 	}

-	DRCMR(info->drcmr_dat) = DRCMR_MAPVLD | info->data_dma_ch;
-	DDADR(info->data_dma_ch) = info->data_desc_addr;
-	DCSR(info->data_dma_ch) |= DCSR_RUN;
+	DRCMR(nand->drcmr_dat) = DRCMR_MAPVLD | nand->data_dma_ch;
+	DDADR(nand->data_dma_ch) = nand->data_desc_addr;
+	DCSR(nand->data_dma_ch) |= DCSR_RUN;
 }

 static void pxa3xx_nand_data_dma_irq(int channel, void *data)
 {
-	struct pxa3xx_nand_info *info = data;
+	struct pxa3xx_nand *nand = data;
 	uint32_t dcsr;

 	dcsr = DCSR(channel);
 	DCSR(channel) = dcsr;

 	if (dcsr & DCSR_BUSERR) {
-		info->retcode = ERR_DMABUSERR;
+		nand->retcode = ERR_DMABUSERR;
 	}

-	enable_int(info, NDSR_CS0_BBD | NDSR_CS0_CMDD);
+	enable_int(nand, NDCR_INT_MASK);
+	nand_writel(nand, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
 }

 static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 {
-	struct pxa3xx_nand_info *info = devid;
-	unsigned int status, is_completed = 0;
+	struct pxa3xx_nand *nand = devid;
+	struct pxa3xx_nand_info *info;
+	unsigned int status, is_completed = 0, cs;
+	unsigned int ready, cmd_done, page_done, badblock_detect;

-	status = nand_readl(info, NDSR);
+	cs		= nand->chip_select;
+	ready           = (cs) ? NDSR_RDY : NDSR_FLASH_RDY;
+	cmd_done        = (cs) ? NDSR_CS1_CMDD : NDSR_CS0_CMDD;
+	page_done       = (cs) ? NDSR_CS1_PAGED : NDSR_CS0_PAGED;
+	badblock_detect = (cs) ? NDSR_CS1_BBD : NDSR_CS0_BBD;
+	info            = nand->info[cs];

+	status = nand_readl(nand, NDSR);
 	if (status & NDSR_DBERR)
-		info->retcode = ERR_DBERR;
+		nand->retcode = ERR_DBERR;
 	if (status & NDSR_SBERR)
-		info->retcode = ERR_SBERR;
+		nand->retcode = ERR_SBERR;
 	if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {

-		info->state |= STATE_DATA_PROCESSING;
+		nand->state |= STATE_DATA_PROCESSING;
 		/* whether use dma to transfer data */
-		if (info->use_dma) {
-			disable_int(info, NDSR_WRDREQ);
-			start_data_dma(info, 0);
+		if (nand->use_dma) {
+			disable_int(nand, NDCR_INT_MASK);
+			start_data_dma(nand, nand->state & STATE_IS_WRITE);
 			goto NORMAL_IRQ_EXIT;
 		} else
-			handle_data_pio(info);
+			handle_data_pio(nand);

-		info->state |= STATE_DATA_DONE;
+		nand->state |= STATE_DATA_DONE;
 	}
-	if (status & NDSR_CS0_CMDD) {
-		info->state |= STATE_CMD_DONE;
+	if (status & cmd_done) {
+		nand->state |= STATE_CMD_DONE;
 		is_completed = 1;
 	}
-	if (status & NDSR_FLASH_RDY)
-		info->state |= STATE_READY;
-	if (status & NDSR_CS0_PAGED)
-		info->state |= STATE_PAGE_DONE;
+	if (status & ready)
+		nand->state |= STATE_READY;
+	if (status & page_done)
+		nand->state |= STATE_PAGE_DONE;

 	if (status & NDSR_WRCMDREQ) {
-		nand_writel(info, NDSR, NDSR_WRCMDREQ);
+		nand_writel(nand, NDSR, NDSR_WRCMDREQ);
 		status &= ~NDSR_WRCMDREQ;
-		info->state |= STATE_CMD_WAIT_DONE;
-		nand_writel(info, NDCB0, info->ndcb0);
-		nand_writel(info, NDCB0, info->ndcb1);
-		nand_writel(info, NDCB0, info->ndcb2);
+		nand->state |= STATE_CMD_WAIT_DONE;
+		nand_writel(nand, NDCB0, nand->ndcb0);
+		nand_writel(nand, NDCB0, nand->ndcb1);
+		nand_writel(nand, NDCB0, nand->ndcb2);
 	}

 	/* clear NDSR to let the controller exit the IRQ */
-	nand_writel(info, NDSR, status);
+	nand_writel(nand, NDSR, status);
 	if (is_completed)
-		complete(&info->cmd_complete);
+		complete(&nand->cmd_complete);
 NORMAL_IRQ_EXIT:
 	return IRQ_HANDLED;
 }

-static int pxa3xx_nand_dev_ready(struct mtd_info *mtd)
-{
-	struct pxa3xx_nand_info *info = mtd->priv;
-	return (nand_readl(info, NDSR) & NDSR_RDY) ? 1 : 0;
-}
-
 static inline int is_buf_blank(uint8_t *buf, size_t len)
 {
 	for (; len > 0; len--)
@@ -461,40 +471,48 @@ static inline int is_buf_blank(uint8_t *buf, size_t len)
 	return 1;
 }

-static int prepare_command_pool(struct pxa3xx_nand_info *info, int command,
+static int prepare_command_pool(struct pxa3xx_nand *nand, int command,
 		uint16_t column, int page_addr)
 {
 	uint16_t cmd;
 	int addr_cycle, exec_cmd, ndcb0;
-	struct mtd_info *mtd = info->mtd;
+	struct mtd_info *mtd;
+	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];

-	ndcb0 = 0;
+	mtd = get_mtd_by_info(info);
+	ndcb0 = (nand->chip_select) ? NDCB0_CSEL : 0;;
 	addr_cycle = 0;
 	exec_cmd = 1;

 	/* reset data and oob column point to handle data */
-	info->buf_start		= 0;
-	info->buf_count		= 0;
-	info->oob_size		= 0;
-	info->use_ecc		= 0;
+	nand->buf_start		= 0;
+	nand->buf_count		= 0;
+	nand->ndcb0		= ndcb0;
+	nand->data_size		= 0;
+	nand->oob_size		= 0;
+	nand->use_ecc		= 0;
+	nand->use_dma		= 0;
+	nand->state		= 0;
+	nand->command		= command;

 	switch (command) {
 	case NAND_CMD_READ0:
 	case NAND_CMD_PAGEPROG:
-		info->use_ecc = 1;
+		nand->use_ecc = 1;
 	case NAND_CMD_READOOB:
 		pxa3xx_set_datasize(info);
+		nand->oob_buff = nand->data_buff + nand->data_size;
+		nand->use_dma = use_dma;
 		break;
 	case NAND_CMD_SEQIN:
 		exec_cmd = 0;
 		break;
 	default:
-		info->ndcb1 = 0;
-		info->ndcb2 = 0;
+		nand->ndcb1 = 0;
+		nand->ndcb2 = 0;
 		break;
 	}

-	info->ndcb0 = ndcb0;
 	addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
 			+ info->col_addr_cycles);

@@ -503,16 +521,16 @@ static int prepare_command_pool(struct
pxa3xx_nand_info *info, int command,
 	case NAND_CMD_READ0:
 		cmd  = info->cmdset->read1;
 		if (command == NAND_CMD_READOOB)
-			info->buf_start = mtd->writesize + column;
+			nand->buf_start = mtd->writesize + column;
 		else
-			info->buf_start = column;
+			nand->buf_start = column;

 		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
-			info->ndcb0 |= NDCB0_CMD_TYPE(0)
+			nand->ndcb0 |= NDCB0_CMD_TYPE(0)
 					| addr_cycle
 					| (cmd & NDCB0_CMD1_MASK);
 		else
-			info->ndcb0 |= NDCB0_CMD_TYPE(0)
+			nand->ndcb0 |= NDCB0_CMD_TYPE(0)
 					| NDCB0_DBC
 					| addr_cycle
 					| cmd;
@@ -520,35 +538,35 @@ static int prepare_command_pool(struct
pxa3xx_nand_info *info, int command,
 	case NAND_CMD_SEQIN:
 		/* small page addr setting */
 		if (unlikely(info->page_size < PAGE_CHUNK_SIZE)) {
-			info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
+			nand->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
 					| (column & 0xFF);

-			info->ndcb2 = 0;
+			nand->ndcb2 = 0;
 		}
 		else {
-			info->ndcb1 = ((page_addr & 0xFFFF) << 16)
+			nand->ndcb1 = ((page_addr & 0xFFFF) << 16)
 					| (column & 0xFFFF);

 			if (page_addr & 0xFF0000)
-				info->ndcb2 = (page_addr & 0xFF0000) >> 16;
+				nand->ndcb2 = (page_addr & 0xFF0000) >> 16;
 			else
-				info->ndcb2 = 0;
+				nand->ndcb2 = 0;
 		}

-		info->buf_count = mtd->writesize + mtd->oobsize;
-		memset(info->data_buff, 0xFF, info->buf_count);
+		nand->buf_count = mtd->writesize + mtd->oobsize;
+		memset(nand->data_buff, 0xFF, nand->buf_count);

 		break;

 	case NAND_CMD_PAGEPROG:
-		if (is_buf_blank(info->data_buff, (mtd->writesize + mtd->oobsize))) {
+		if (is_buf_blank(nand->data_buff, (mtd->writesize + mtd->oobsize))) {
 			exec_cmd = 0;
 			break;
 		}

 		cmd = info->cmdset->program;
-		info->state |= STATE_IS_WRITE;
-		info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
+		nand->state |= STATE_IS_WRITE;
+		nand->ndcb0 |= NDCB0_CMD_TYPE(0x1)
 				| NDCB0_AUTO_RS
 				| NDCB0_ST_ROW_EN
 				| NDCB0_DBC
@@ -558,37 +576,37 @@ static int prepare_command_pool(struct
pxa3xx_nand_info *info, int command,

 	case NAND_CMD_READID:
 		cmd = info->cmdset->read_id;
-		info->buf_count = info->read_id_bytes;
-		info->ndcb0 |= NDCB0_CMD_TYPE(3)
+		nand->buf_count = info->read_id_bytes;
+		nand->ndcb0 |= NDCB0_CMD_TYPE(3)
 				| NDCB0_ADDR_CYC(1)
 				| cmd;

-		info->data_size = 8;
+		nand->data_size = 8;
 		break;
 	case NAND_CMD_STATUS:
 		cmd = info->cmdset->read_status;
-		info->buf_count = 1;
-		info->ndcb0 |= NDCB0_CMD_TYPE(4)
+		nand->buf_count = 1;
+		nand->ndcb0 |= NDCB0_CMD_TYPE(4)
 				| NDCB0_ADDR_CYC(1)
 				| cmd;

-		info->data_size = 8;
+		nand->data_size = 8;
 		break;

 	case NAND_CMD_ERASE1:
 		cmd = info->cmdset->erase;
-		info->ndcb0 |= NDCB0_CMD_TYPE(2)
+		nand->ndcb0 |= NDCB0_CMD_TYPE(2)
 				| NDCB0_AUTO_RS
 				| NDCB0_ADDR_CYC(3)
 				| NDCB0_DBC
 				| cmd;
-		info->ndcb1 = page_addr;
-		info->ndcb2 = 0;
+		nand->ndcb1 = page_addr;
+		nand->ndcb2 = 0;

 		break;
 	case NAND_CMD_RESET:
 		cmd = info->cmdset->reset;
-		info->ndcb0 |= NDCB0_CMD_TYPE(5)
+		nand->ndcb0 |= NDCB0_CMD_TYPE(5)
 				| cmd;

 		break;
@@ -599,7 +617,7 @@ static int prepare_command_pool(struct
pxa3xx_nand_info *info, int command,

 	default:
 		exec_cmd = 0;
-		printk(KERN_ERR "pxa3xx-nand: non-supported command %x\n", command);
+		dev_err(&nand->pdev->dev, "non-supported command %x\n", command);
 		break;
 	}

@@ -610,6 +628,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 		int column, int page_addr)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;
 	int ret, exec_cmd;

 	/* if this is a x16 device ,then convert the input
@@ -619,32 +638,40 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 	if (info->reg_ndcr & NDCR_DWIDTH_M)
 		column /= 2;

-	exec_cmd = prepare_command_pool(info, command, column, page_addr);
+	/* reset timing */
+	if (nand->chip_select != info->chip_select) {
+		nand->chip_select = info->chip_select;
+		nand_writel(nand, NDTR0CS0, info->ndtr0cs0);
+		nand_writel(nand, NDTR1CS0, info->ndtr1cs0);
+	}
+
+	exec_cmd = prepare_command_pool(nand, command, column, page_addr);
 	if (exec_cmd) {
-		init_completion(&info->cmd_complete);
-		info->state |= STATE_CMD_PREPARED;
-		pxa3xx_nand_start(info);
+		init_completion(&nand->cmd_complete);
+		nand->state |= STATE_CMD_PREPARED;
+		pxa3xx_nand_start(nand);

-		ret = wait_for_completion_timeout(&info->cmd_complete,
+		ret = wait_for_completion_timeout(&nand->cmd_complete,
 				CHIP_DELAY_TIMEOUT);
 		if (!ret) {
-			printk(KERN_ERR "Wait time out!!!\n");
+			dev_err(&nand->pdev->dev, "Wait time out!!!\n");
 		}
 		/* Stop State Machine for next command cycle */
-		pxa3xx_nand_stop(info);
-		disable_int(info, NDCR_INT_MASK);
-		info->state &= ~STATE_CMD_PREPARED;
+		pxa3xx_nand_stop(nand);
+		disable_int(nand, NDCR_INT_MASK);
+		nand->state &= ~STATE_CMD_PREPARED;
 	}
 }

 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;
 	char retval = 0xFF;

-	if (info->buf_start < info->buf_count)
+	if (nand->buf_start < nand->buf_count)
 		/* Has just send a new command? */
-		retval = info->data_buff[info->buf_start++];
+		retval = nand->data_buff[nand->buf_start++];

 	return retval;
 }
@@ -652,11 +679,12 @@ static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
 static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;
 	u16 retval = 0xFFFF;

-	if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
-		retval = *((u16 *)(info->data_buff+info->buf_start));
-		info->buf_start += 2;
+	if (!(nand->buf_start & 0x01) && nand->buf_start < nand->buf_count) {
+		retval = *((u16 *)(nand->data_buff+nand->buf_start));
+		nand->buf_start += 2;
 	}
 	return retval;
 }
@@ -664,20 +692,22 @@ static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
 static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
-	int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
+	struct pxa3xx_nand *nand = info->nand_data;
+	int real_len = min_t(size_t, len, nand->buf_count - nand->buf_start);

-	memcpy(buf, info->data_buff + info->buf_start, real_len);
-	info->buf_start += real_len;
+	memcpy(buf, nand->data_buff + nand->buf_start, real_len);
+	nand->buf_start += real_len;
 }

 static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
 		const uint8_t *buf, int len)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
-	int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
+	struct pxa3xx_nand *nand = info->nand_data;
+	int real_len = min_t(size_t, len, nand->buf_count - nand->buf_start);

-	memcpy(info->data_buff + info->buf_start, buf, real_len);
-	info->buf_start += real_len;
+	memcpy(nand->data_buff + nand->buf_start, buf, real_len);
+	nand->buf_start += real_len;
 }

 static int pxa3xx_nand_verify_buf(struct mtd_info *mtd,
@@ -694,10 +724,11 @@ static void pxa3xx_nand_select_chip(struct
mtd_info *mtd, int chip)
 static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;

 	/* pxa3xx_nand_send_command has waited for command complete */
 	if (this->state == FL_WRITING || this->state == FL_ERASING) {
-		if (info->retcode == ERR_NONE)
+		if (nand->retcode == ERR_NONE)
 			return 0;
 		else {
 			/*
@@ -711,41 +742,11 @@ static int pxa3xx_nand_waitfunc(struct mtd_info
*mtd, struct nand_chip *this)
 	return 0;
 }

-static void pxa3xx_nand_ecc_hwctl(struct mtd_info *mtd, int mode)
-{
-	return;
-}
-
-static int pxa3xx_nand_ecc_calculate(struct mtd_info *mtd,
-		const uint8_t *dat, uint8_t *ecc_code)
-{
-	return 0;
-}
-
-static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
-		uint8_t *dat, uint8_t *read_ecc, uint8_t *calc_ecc)
-{
-	struct pxa3xx_nand_info *info = mtd->priv;
-	/*
-	 * Any error include ERR_SEND_CMD, ERR_DBERR, ERR_BUSERR, we
-	 * consider it as a ecc error which will tell the caller the
-	 * read fail We have distinguish all the errors, but the
-	 * nand_read_ecc only check this function return value
-	 *
-	 * Corrected (single-bit) errors must also be noted.
-	 */
-	if (info->retcode == ERR_SBERR)
-		return 1;
-	else if (info->retcode != ERR_NONE)
-		return -1;
-
-	return 0;
-}
-
 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
 				    const struct pxa3xx_nand_flash *f)
 {
-	struct platform_device *pdev = info->pdev;
+	struct pxa3xx_nand *nand = info->nand_data;
+	struct platform_device *pdev = nand->pdev;
 	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 	uint32_t ndcr = 0x00000FFF; /* disable all interrupts */

@@ -779,22 +780,28 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	ndcr |= NDCR_SPARE_EN; /* enable spare by default */

 	info->reg_ndcr = ndcr;
+	info->use_ecc = 1;

 	pxa3xx_nand_set_timing(info, f->timing);
 	return 0;
 }

-static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
+static int pxa3xx_nand_detect_config(struct pxa3xx_nand *nand)
 {
-	uint32_t ndcr = nand_readl(info, NDCR);
+	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
+	uint32_t ndcr = nand_readl(nand, NDCR);

+	if (nand->chip_select > 0) {
+		printk(KERN_ERR "We could not detect configure if two cs is supported!!\n");
+		BUG();
+	}
 	info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
 	/* set info fields needed to read id */
 	info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
 	info->reg_ndcr = ndcr;

-	info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
-	info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
+	info->ndtr0cs0 = nand_readl(nand, NDTR0CS0);
+	info->ndtr1cs0 = nand_readl(nand, NDTR1CS0);
 	info->cmdset = &default_cmdset;

 	return 0;
@@ -805,62 +812,40 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand_info *info)
  * data buffer and the DMA descriptor
  */
 #define MAX_BUFF_SIZE	PAGE_SIZE
-
-static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
+static void free_cs_resource(struct pxa3xx_nand_info *info, int cs)
 {
-	struct platform_device *pdev = info->pdev;
-	int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
-
-	if (use_dma == 0) {
-		info->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
-		if (info->data_buff == NULL)
-			return -ENOMEM;
-		return 0;
-	}
-
-	info->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
-				&info->data_buff_phys, GFP_KERNEL);
-	if (info->data_buff == NULL) {
-		dev_err(&pdev->dev, "failed to allocate dma buffer\n");
-		return -ENOMEM;
-	}
-
-	info->data_buff_size = MAX_BUFF_SIZE;
-	info->data_desc = (void *)info->data_buff + data_desc_offset;
-	info->data_desc_addr = info->data_buff_phys + data_desc_offset;
+	struct pxa3xx_nand *nand;
+	struct mtd_info *mtd;

-	info->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
-				pxa3xx_nand_data_dma_irq, info);
-	if (info->data_dma_ch < 0) {
-		dev_err(&pdev->dev, "failed to request data dma\n");
-		dma_free_coherent(&pdev->dev, info->data_buff_size,
-				info->data_buff, info->data_buff_phys);
-		return info->data_dma_ch;
-	}
+	if (!info)
+		return;

-	return 0;
+	nand = info->nand_data;
+	mtd = get_mtd_by_info(info);
+	kfree(mtd);
+	nand->info[cs] = NULL;
 }

 static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
 		struct nand_chip *chip, uint8_t *buf, int page)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;

 	chip->read_buf(mtd, buf, mtd->writesize);
 	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);

-	if (info->retcode == ERR_SBERR) {
-		switch (info->use_ecc) {
+	if (nand->retcode == ERR_SBERR) {
+		switch (nand->use_ecc) {
 			case 1:
-				mtd->ecc_stats.corrected ++;
+				mtd->ecc_stats.corrected++;
 				break;

 			case 0:
 			default:
 				break;
 		}
-	}
-	else if (info->retcode == ERR_DBERR) {
+	} else if (nand->retcode == ERR_DBERR) {
 		int buf_blank;

 		buf_blank = is_buf_blank(buf, mtd->writesize);
@@ -880,20 +865,19 @@ static void pxa3xx_nand_write_page_hwecc(struct
mtd_info *mtd,

 static void pxa3xx_nand_erase_cmd(struct mtd_info *mtd, int page)
 {
-	struct nand_chip *chip = mtd->priv;
 	/* Send commands to erase a block */
-	chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
+	pxa3xx_nand_cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
 }

-static int __devinit pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
+static int __devinit pxa3xx_nand_sensing(struct pxa3xx_nand *nand)
 {
-	struct mtd_info *mtd = info->mtd;
-	struct nand_chip *chip = mtd->priv;
+	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
+	struct mtd_info *mtd = get_mtd_by_info(info);

 	/* use the common timing to make a try */
 	pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
-	chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
-	if (info->state & STATE_READY)
+	pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
+	if (nand->state & STATE_READY)
 		return 1;
 	else
 		return 0;
@@ -902,7 +886,8 @@ static int __devinit pxa3xx_nand_sensing(struct
pxa3xx_nand_info *info)
 static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
-	struct platform_device *pdev = info->pdev;
+	struct pxa3xx_nand *nand = info->nand_data;
+	struct platform_device *pdev = nand->pdev;
 	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 	struct nand_flash_dev pxa3xx_flash_ids[2] = {{NULL,}, {NULL,}};
 	const struct pxa3xx_nand_flash *f = NULL;
@@ -912,28 +897,23 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 	int i, ret;

 	if (pdata->keep_config) {
-		if (pxa3xx_nand_detect_config(info) == 0)
+		if (pxa3xx_nand_detect_config(nand) == 0)
 			goto KEEP_CONFIG;
 	}

-	ret = pxa3xx_nand_sensing(info);
+	ret = pxa3xx_nand_sensing(nand);
 	if (!ret) {
-		kfree(mtd);
-		info->mtd = NULL;
-		printk(KERN_INFO "There is no nand chip on cs 0!\n");
-
+		free_cs_resource(info, nand->chip_select);
 		return -EINVAL;
 	}

 	chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
-	id = *((uint16_t *)(info->data_buff));
+	id = *((uint16_t *)(nand->data_buff));
 	if (id != 0)
-		printk(KERN_INFO "Detect a flash id %x\n", id);
+		dev_info(&nand->pdev->dev, "Detect a flash id %x\n", id);
 	else {
-		kfree(mtd);
-		info->mtd = NULL;
-		printk(KERN_WARNING "Read out ID 0, potential timing set wrong!!\n");
-
+		dev_warn(&nand->pdev->dev, "Read out ID 0, potential timing set wrong!!\n");
+		free_cs_resource(info, nand->chip_select);
 		return -EINVAL;
 	}

@@ -949,10 +929,8 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd)
 	}

 	if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
-		kfree(mtd);
-		info->mtd = NULL;
-		printk(KERN_ERR "ERROR!! flash not defined!!!\n");
-
+		dev_err(&nand->pdev->dev, "ERROR!! flash not defined!!!\n");
+		free_cs_resource(info, nand->chip_select);
 		return -EINVAL;
 	}

@@ -969,15 +947,15 @@ KEEP_CONFIG:
 		return -ENODEV;
 	/* calculate addressing information */
 	info->col_addr_cycles = (mtd->writesize >= 2048) ? 2 : 1;
-	info->oob_buff = info->data_buff + mtd->writesize;
 	if ((mtd->size >> chip->page_shift) > 65536)
 		info->row_addr_cycles = 3;
 	else
 		info->row_addr_cycles = 2;
-	mtd->name = mtd_names[0];
+	info->page_size = mtd->writesize;
+	mtd->name = mtd_names[nand->chip_select];
 	chip->ecc.mode = NAND_ECC_HW;
 	chip->ecc.size = mtd->writesize;
-	chip->options = (info->reg_ndcr & NDCR_DWIDTH_M) ? NAND_BUSWIDTH_16: 0;
+	chip->options |= (info->reg_ndcr & NDCR_DWIDTH_M) ? NAND_BUSWIDTH_16: 0;
 	chip->options |= NAND_NO_READRDY;
 	chip->options |= NAND_USE_FLASH_BBT;

@@ -989,49 +967,25 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 	struct pxa3xx_nand_info *info;
 	struct nand_chip *chip;
 	struct mtd_info *mtd;
+	struct pxa3xx_nand *nand;
 	struct resource *r;
-	int ret, irq;
+	int ret, irq, cs;
+	int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);

-	mtd = kzalloc(sizeof(struct mtd_info) + sizeof(struct pxa3xx_nand_info),
-			GFP_KERNEL);
-	if (!mtd) {
+	nand = kzalloc(sizeof(struct pxa3xx_nand), GFP_KERNEL);
+	if (!nand) {
 		dev_err(&pdev->dev, "failed to allocate memory\n");
 		return -ENOMEM;
 	}

-	info = (struct pxa3xx_nand_info *)(&mtd[1]);
-	chip = (struct nand_chip *)(&mtd[1]);
-	info->pdev = pdev;
-	info->mtd = mtd;
-	mtd->priv = info;
-	mtd->owner = THIS_MODULE;
-
-	chip->ecc.read_page	= pxa3xx_nand_read_page_hwecc;
-	chip->ecc.write_page	= pxa3xx_nand_write_page_hwecc;
-	chip->ecc.hwctl		= pxa3xx_nand_ecc_hwctl;
-	chip->ecc.calculate	= pxa3xx_nand_ecc_calculate;
-	chip->ecc.correct	= pxa3xx_nand_ecc_correct;
-	chip->controller        = &info->controller;
-	chip->waitfunc		= pxa3xx_nand_waitfunc;
-	chip->select_chip	= pxa3xx_nand_select_chip;
-	chip->dev_ready		= pxa3xx_nand_dev_ready;
-	chip->cmdfunc		= pxa3xx_nand_cmdfunc;
-	chip->read_word		= pxa3xx_nand_read_word;
-	chip->read_byte		= pxa3xx_nand_read_byte;
-	chip->read_buf		= pxa3xx_nand_read_buf;
-	chip->write_buf		= pxa3xx_nand_write_buf;
-	chip->verify_buf	= pxa3xx_nand_verify_buf;
-	chip->erase_cmd		= pxa3xx_nand_erase_cmd;
-
-	spin_lock_init(&chip->controller->lock);
-	init_waitqueue_head(&chip->controller->wq);
-	info->clk = clk_get(&pdev->dev, NULL);
-	if (IS_ERR(info->clk)) {
+	nand->pdev = pdev;
+	nand->clk = clk_get(&pdev->dev, NULL);
+	if (IS_ERR(nand->clk)) {
 		dev_err(&pdev->dev, "failed to get nand clock\n");
-		ret = PTR_ERR(info->clk);
-		goto fail_free_mtd;
+		ret = PTR_ERR(nand->clk);
+		goto fail_alloc;
 	}
-	clk_enable(info->clk);
+	clk_enable(nand->clk);

 	r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 	if (r == NULL) {
@@ -1039,7 +993,7 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		ret = -ENXIO;
 		goto fail_put_clk;
 	}
-	info->drcmr_dat = r->start;
+	nand->drcmr_dat = r->start;

 	r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 	if (r == NULL) {
@@ -1047,14 +1001,7 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		ret = -ENXIO;
 		goto fail_put_clk;
 	}
-	info->drcmr_cmd = r->start;
-
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0) {
-		dev_err(&pdev->dev, "no IRQ resource defined\n");
-		ret = -ENXIO;
-		goto fail_put_clk;
-	}
+	nand->drcmr_cmd = r->start;

 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (r == NULL) {
@@ -1070,80 +1017,142 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		goto fail_put_clk;
 	}

-	info->mmio_base = ioremap(r->start, resource_size(r));
-	if (info->mmio_base == NULL) {
+	nand->mmio_base = ioremap(r->start, resource_size(r));
+	if (nand->mmio_base == NULL) {
 		dev_err(&pdev->dev, "ioremap() failed\n");
 		ret = -ENODEV;
 		goto fail_free_res;
 	}
-	info->mmio_phys = r->start;
-
-	ret = pxa3xx_nand_init_buff(info);
-	if (ret)
-		goto fail_free_io;
+	nand->mmio_phys = r->start;

 	/* initialize all interrupts to be disabled */
-	disable_int(info, NDSR_MASK);
+	disable_int(nand, NDSR_MASK);
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(&pdev->dev, "no IRQ resource defined\n");
+		ret = -ENXIO;
+		goto fail_put_clk;
+	}

 	ret = request_irq(irq, pxa3xx_nand_irq, IRQF_DISABLED,
-			  pdev->name, info);
+			  pdev->name, nand);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "failed to request IRQ\n");
+		ret = -ENXIO;
+		goto fail_free_irq;
+	}
+
+	platform_set_drvdata(pdev, nand);
+	spin_lock_init(&nand->controller.lock);
+	init_waitqueue_head(&nand->controller.wq);
+	for (cs = 0; cs < NUM_CHIP_SELECT; cs++) {
+		mtd = kzalloc(sizeof(struct mtd_info)
+				+ sizeof(struct pxa3xx_nand_info),
+				GFP_KERNEL);
+		if (!mtd) {
+			dev_err(&pdev->dev, "failed to allocate memory\n");
+			ret = -ENOMEM;
+			goto fail_free_irq;
+		}
+
+		info = (struct pxa3xx_nand_info *)(&mtd[1]);
+		info->nand_data = nand;
+		info->chip_select = cs;
+		mtd->priv = info;
+		mtd->owner = THIS_MODULE;
+		nand->info[cs] = info;
+
+		chip = (struct nand_chip *)(&mtd[1]);
+		chip->controller        = &nand->controller;
+		chip->ecc.read_page	= pxa3xx_nand_read_page_hwecc;
+		chip->ecc.write_page	= pxa3xx_nand_write_page_hwecc;
+		chip->waitfunc		= pxa3xx_nand_waitfunc;
+		chip->select_chip	= pxa3xx_nand_select_chip;
+		chip->cmdfunc		= pxa3xx_nand_cmdfunc;
+		chip->read_word		= pxa3xx_nand_read_word;
+		chip->read_byte		= pxa3xx_nand_read_byte;
+		chip->read_buf		= pxa3xx_nand_read_buf;
+		chip->write_buf		= pxa3xx_nand_write_buf;
+		chip->verify_buf	= pxa3xx_nand_verify_buf;
+		chip->erase_cmd		= pxa3xx_nand_erase_cmd;
+	}
+
+	if (use_dma == 0) {
+		nand->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
+		if (nand->data_buff == NULL) {
+			ret = -ENOMEM;
+			goto fail_free_buf;
+		}
+		goto success_exit;
+	}
+
+	nand->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
+			&nand->data_buff_phys, GFP_KERNEL);
+	if (nand->data_buff == NULL) {
+		dev_err(&pdev->dev, "failed to allocate dma buffer\n");
+		ret = -ENOMEM;
 		goto fail_free_buf;
 	}

-	platform_set_drvdata(pdev, info);
+	nand->data_desc = (void *)nand->data_buff + data_desc_offset;
+	nand->data_desc_addr = nand->data_buff_phys + data_desc_offset;
+	nand->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
+			pxa3xx_nand_data_dma_irq, nand);
+	if (nand->data_dma_ch < 0) {
+		dev_err(&pdev->dev, "failed to request data dma\n");
+		ret = -ENXIO;
+		goto fail_free_buf;
+	}
+success_exit:
 	return 0;

 fail_free_buf:
-	free_irq(irq, info);
-	if (use_dma) {
-		pxa_free_dma(info->data_dma_ch);
-		dma_free_coherent(&pdev->dev, info->data_buff_size,
-			info->data_buff, info->data_buff_phys);
-	} else
-		kfree(info->data_buff);
-fail_free_io:
-	iounmap(info->mmio_base);
+	for (cs = 0; cs < NUM_CHIP_SELECT; cs++) {
+		info = nand->info[cs];
+		free_cs_resource(info, cs);
+	}
+fail_free_irq:
+	free_irq(irq, nand);
+	iounmap(nand->mmio_base);
 fail_free_res:
 	release_mem_region(r->start, resource_size(r));
 fail_put_clk:
-	clk_disable(info->clk);
-	clk_put(info->clk);
-fail_free_mtd:
-	kfree(mtd);
+	clk_disable(nand->clk);
+	clk_put(nand->clk);
+fail_alloc:
+	kfree(nand);
 	return ret;
 }

 static int pxa3xx_nand_remove(struct platform_device *pdev)
 {
-	struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
-	struct mtd_info *mtd = info->mtd;
+	struct pxa3xx_nand *nand = platform_get_drvdata(pdev);
+	struct pxa3xx_nand_info *info;
+	struct mtd_info *mtd;
 	struct resource *r;
-	int irq;
+	int irq, cs;

 	platform_set_drvdata(pdev, NULL);

-	del_mtd_device(mtd);
-	del_mtd_partitions(mtd);
 	irq = platform_get_irq(pdev, 0);
 	if (irq >= 0)
-		free_irq(irq, info);
-	if (use_dma) {
-		pxa_free_dma(info->data_dma_ch);
-		dma_free_writecombine(&pdev->dev, info->data_buff_size,
-				info->data_buff, info->data_buff_phys);
-	} else
-		kfree(info->data_buff);
-
-	iounmap(info->mmio_base);
+		free_irq(irq, nand);
+
+	iounmap(nand->mmio_base);
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	release_mem_region(r->start, resource_size(r));
-
-	clk_disable(info->clk);
-	clk_put(info->clk);
-
-	kfree(mtd);
+	clk_disable(nand->clk);
+	clk_put(nand->clk);
+
+	for (cs = 0; cs < NUM_CHIP_SELECT; cs++) {
+		info = nand->info[cs];
+		if (!info)
+			continue;
+		mtd = get_mtd_by_info(info);
+		del_mtd_partitions(mtd);
+		del_mtd_device(mtd);
+		free_cs_resource(info, cs);
+	}
 	return 0;
 }

@@ -1151,7 +1160,11 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 {
 	struct pxa3xx_nand_platform_data *pdata;
 	struct pxa3xx_nand_info *info;
-	int ret;
+	struct pxa3xx_nand *nand;
+	struct mtd_info *mtd;
+	static const char *probes[] = { "cmdlinepart", NULL };
+	struct mtd_partition *parts;
+	int nr_parts, ret, cs, probe_success = 0;

 	pdata = pdev->dev.platform_data;
 	if (!pdata) {
@@ -1163,25 +1176,30 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 	if (ret)
 		return ret;

-	info = platform_get_drvdata(pdev);
-	if (pxa3xx_nand_scan(info->mtd)) {
-		dev_err(&pdev->dev, "failed to scan nand\n");
-		pxa3xx_nand_remove(pdev);
-		return -ENODEV;
-	}
-
-	if (mtd_has_cmdlinepart()) {
-		static const char *probes[] = { "cmdlinepart", NULL };
-		struct mtd_partition *parts;
-		int nr_parts;
-
-		nr_parts = parse_mtd_partitions(info->mtd, probes, &parts, 0);
-
-		if (nr_parts)
-			return add_mtd_partitions(info->mtd, parts, nr_parts);
+	nand = platform_get_drvdata(pdev);
+	for (cs = 0; cs < NUM_CHIP_SELECT; cs++) {
+		info = nand->info[cs];
+		mtd = get_mtd_by_info(info);
+		if (pxa3xx_nand_scan(mtd)) {
+			dev_err(&pdev->dev, "failed to scan cs#%d nand\n", cs);
+			continue;
+		}
+		nr_parts = 0;
+		if (mtd_has_cmdlinepart()) {
+			nr_parts = parse_mtd_partitions(mtd, probes, &parts, 0);
+			if (nr_parts)
+				ret = add_mtd_partitions(mtd, parts, nr_parts);
+		}
+		if (!nr_parts)
+			ret = add_mtd_partitions(mtd, pdata->parts[cs],
+					pdata->nr_parts[cs]);
+		if (!ret)
+			probe_success = 1;
 	}

-	return add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts);
+	if (!probe_success)
+		pxa3xx_nand_remove(pdev);
+	return ret;
 }

 #ifdef CONFIG_PM
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 09:52:09 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 21:52:09 +0800
Subject: [PATCH 14/29] pxa3xx_nand: add bch ecc support
Message-ID: <mailman.118.1280296772.27306.linux-arm-kernel@lists.infradead.org>

Enable the controller internal bch ecc engine when need.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa3xx_nand.h |   11 ++-
 drivers/mtd/nand/pxa3xx_nand.c               |  119 ++++++++++++++++++-------
 2 files changed, 94 insertions(+), 36 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index cf42f97..9b1f9df 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -3,6 +3,12 @@

 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
+/* error code and state */
+enum {
+	ECC_NONE = 0,
+	ECC_HAMMIN,
+	ECC_BCH,
+};

 struct pxa3xx_nand_timing {
 	unsigned int	tCH;  /* Enable signal hold time */
@@ -32,10 +38,11 @@ struct pxa3xx_nand_cmdset {
 struct pxa3xx_nand_flash {
 	char		*name;
 	uint32_t	chip_id;
-	uint16_t	page_per_block; /* Pages per block (PG_PER_BLK) */
-	uint16_t 	page_size;	/* Page size in bytes (PAGE_SZ) */
+	uint16_t	page_per_block; /* Pages per block */
+	uint16_t 	page_size;	/* Page size in bytes */
 	uint8_t		flash_width;	/* Width of Flash memory (DWIDTH_M) */
 	uint8_t 	dfc_width;	/* Width of flash controller(DWIDTH_C) */
+	uint8_t		ecc_type;	/* Which ECC is applied */
 	uint32_t	num_blocks;	/* Number of physical blocks in Flash */
 	struct pxa3xx_nand_cmdset *cmdset;	/* NAND command set */
 	struct pxa3xx_nand_timing *timing;	/* NAND Flash timing */
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 3dea0fe..94df2bd 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -29,6 +29,7 @@
 #define	CHIP_DELAY_TIMEOUT	(2 * HZ/10)
 #define NAND_STOP_DELAY		(2 * HZ/50)
 #define PAGE_CHUNK_SIZE		(2048)
+#define BCH_THRESHOLD           (8)

 /* registers and bit definitions */
 #define NDCR		(0x00) /* Control register */
@@ -38,12 +39,15 @@
 #define NDPCR		(0x18) /* Page Count Register */
 #define NDBDR0		(0x1C) /* Bad Block Register 0 */
 #define NDBDR1		(0x20) /* Bad Block Register 1 */
+#define NDECCCTRL	(0x28) /* ECC Control Register */
 #define NDDB		(0x40) /* Data Buffer */
 #define NDCB0		(0x48) /* Command Buffer0 */
 #define NDCB1		(0x4C) /* Command Buffer1 */
 #define NDCB2		(0x50) /* Command Buffer2 */

 #define NDCR_SPARE_EN		(0x1 << 31)
+#define NDSR_ERR_CNT_MASK       (0x1F << 16)
+#define NDSR_ERR_CNT(x)         (((x) << 16) & NDSR_ERR_CNT_MASK)
 #define NDCR_ECC_EN		(0x1 << 30)
 #define NDCR_DMA_EN		(0x1 << 29)
 #define NDCR_ND_RUN		(0x1 << 28)
@@ -90,6 +94,13 @@
 #define NDCB0_CMD1_MASK		(0xff)
 #define NDCB0_ADDR_CYC_SHIFT	(16)

+/* ECC Control Register */
+#define NDECCCTRL_ECC_SPARE_MSK (0xFF << 7)
+#define NDECCCTRL_ECC_SPARE(x)  (((x) << 7) & NDECCCTRL_ECC_SPARE_MSK)
+#define NDECCCTRL_ECC_THR_MSK   (0x3F << 1)
+#define NDECCCTRL_ECC_THRESH(x) (((x) << 1) & NDECCCTRL_ECC_THR_MSK)
+#define NDECCCTRL_BCH_EN        (0x1)
+
 /* macros for registers read/write */
 #define nand_writel(info, off, val)	\
 	__raw_writel((val), (info)->mmio_base + (off))
@@ -215,16 +226,16 @@ static struct pxa3xx_nand_timing __devinitdata
timing[] = {
 #define NAND_SETTING_MICRON      &default_cmdset, &timing[2]
 #define NAND_SETTING_ST          &default_cmdset, &timing[3]
 static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
-{ "DEFAULT FLASH",      0,   0, 2048,  8,  8,    0, NAND_SETTING_DEFAULT, },
-{ "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, 4096, NAND_SETTING_SAMSUNG, },
-{ "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, 2048, NAND_SETTING_SAMSUNG, },
-{ "1GiB 8-bit",    0xd3ec, 128, 2048,  8,  8, 4096, NAND_SETTING_SAMSUNG, },
-{ "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, 8192, NAND_SETTING_SAMSUNG, },
-{ "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, 1024, NAND_SETTING_MICRON, },
-{ "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, 1024, NAND_SETTING_MICRON, },
-{ "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, 4096, NAND_SETTING_MICRON, },
-{ "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, 4096, NAND_SETTING_MICRON, },
-{ "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, 2048, NAND_SETTING_ST, },
+{ "DEFAULT FLASH",      0,   0, 2048,  8,  8, ECC_NONE,      0,
NAND_SETTING_DEFAULT, },
+{ "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, ECC_HAMMIN, 4096,
NAND_SETTING_SAMSUNG, },
+{ "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, ECC_HAMMIN, 2048,
NAND_SETTING_SAMSUNG, },
+{ "1GiB 8-bit",    0xd3ec, 128, 2048,  8,  8, ECC_BCH,    4096,
NAND_SETTING_SAMSUNG, },
+{ "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, ECC_BCH,    8192,
NAND_SETTING_SAMSUNG, },
+{ "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, ECC_HAMMIN, 1024,
NAND_SETTING_MICRON, },
+{ "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, ECC_HAMMIN, 1024,
NAND_SETTING_MICRON, },
+{ "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, ECC_HAMMIN, 4096,
NAND_SETTING_MICRON, },
+{ "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, ECC_HAMMIN, 4096,
NAND_SETTING_MICRON, },
+{ "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, ECC_HAMMIN, 2048,
NAND_SETTING_ST, },
 };

 static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
@@ -273,19 +284,43 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
 	struct pxa3xx_nand *nand = info->nand_data;
 	int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;

-	nand->data_size = info->page_size;
-	if (!oob_enable) {
-		nand->oob_size = 0;
-		return;
-	}
+	if (info->page_size >= PAGE_CHUNK_SIZE) {
+		nand->data_size = PAGE_CHUNK_SIZE;
+		if (!oob_enable) {
+			nand->oob_size = 0;
+			return;
+		}

-	switch (info->page_size) {
-	case 2048:
-		nand->oob_size = (nand->use_ecc) ? 40 : 64;
-		break;
-	case 512:
-		nand->oob_size = (nand->use_ecc) ? 8 : 16;
-		break;
+		switch (nand->use_ecc) {
+		case ECC_HAMMIN:
+			nand->oob_size = 40;
+			break;
+		case ECC_BCH:
+			nand->oob_size = 32;
+			break;
+		default:
+			nand->oob_size = 64;
+			break;
+		}
+	} else {
+		nand->data_size = 512;
+		if (!oob_enable) {
+			nand->oob_size = 0;
+			return;
+		}
+
+		switch (nand->use_ecc) {
+		case ECC_HAMMIN:
+			nand->oob_size = 8;
+			break;
+		case ECC_BCH:
+			printk("Don't support BCH on small page device!!!\n");
+			BUG();
+			break;
+		default:
+			nand->oob_size = 16;
+			break;
+		}
 	}
 }

@@ -298,16 +333,26 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
 static void pxa3xx_nand_start(struct pxa3xx_nand *nand)
 {
 	struct pxa3xx_nand_info *info;
-	uint32_t ndcr;
+	uint32_t ndcr, ndeccctrl = 0;

 	info = nand->info[nand->chip_select];
 	ndcr = info->reg_ndcr;
-	ndcr |= nand->use_ecc ? NDCR_ECC_EN : 0;
 	ndcr |= nand->use_dma ? NDCR_DMA_EN : NDCR_STOP_ON_UNCOR;
 	ndcr |= NDCR_ND_RUN;

+	switch (nand->use_ecc) {
+	case ECC_BCH:
+		ndeccctrl |= NDECCCTRL_BCH_EN;
+		ndeccctrl |= NDECCCTRL_ECC_THRESH(BCH_THRESHOLD);
+	case ECC_HAMMIN:
+		ndcr |= NDCR_ECC_EN;
+	default:
+		break;
+	}
+
 	/* clear status bits and run */
 	nand_writel(nand, NDCR, 0);
+	nand_writel(nand, NDECCCTRL, ndeccctrl);
 	nand_writel(nand, NDSR, NDSR_MASK);
 	nand_writel(nand, NDCR, ndcr);
 }
@@ -420,6 +465,7 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 	info            = nand->info[cs];

 	status = nand_readl(nand, NDSR);
+	nand->bad_count = (status & NDSR_ERR_CNT_MASK) >> 16;
 	if (status & NDSR_DBERR)
 		nand->retcode = ERR_DBERR;
 	if (status & NDSR_SBERR)
@@ -498,7 +544,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 	switch (command) {
 	case NAND_CMD_READ0:
 	case NAND_CMD_PAGEPROG:
-		nand->use_ecc = 1;
+		nand->use_ecc = info->use_ecc;
 	case NAND_CMD_READOOB:
 		pxa3xx_set_datasize(info);
 		nand->oob_buff = nand->data_buff + nand->data_size;
@@ -757,6 +803,7 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 		return -EINVAL;

 	/* calculate flash information */
+	info->use_ecc = f->ecc_type;
 	info->cmdset = f->cmdset;
 	info->page_size = f->page_size;
 	info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;
@@ -780,7 +827,6 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	ndcr |= NDCR_SPARE_EN; /* enable spare by default */

 	info->reg_ndcr = ndcr;
-	info->use_ecc = 1;

 	pxa3xx_nand_set_timing(info, f->timing);
 	return 0;
@@ -790,6 +836,7 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand *nand)
 {
 	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
 	uint32_t ndcr = nand_readl(nand, NDCR);
+	uint32_t ndeccctrl = nand_readl(nand, NDECCCTRL);

 	if (nand->chip_select > 0) {
 		printk(KERN_ERR "We could not detect configure if two cs is supported!!\n");
@@ -802,6 +849,7 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand *nand)

 	info->ndtr0cs0 = nand_readl(nand, NDTR0CS0);
 	info->ndtr1cs0 = nand_readl(nand, NDTR1CS0);
+	info->use_ecc = (ndeccctrl & NDECCCTRL_BCH_EN) ? ECC_BCH : ECC_HAMMIN;
 	info->cmdset = &default_cmdset;

 	return 0;
@@ -837,13 +885,16 @@ static int pxa3xx_nand_read_page_hwecc(struct
mtd_info *mtd,

 	if (nand->retcode == ERR_SBERR) {
 		switch (nand->use_ecc) {
-			case 1:
-				mtd->ecc_stats.corrected++;
-				break;
-
-			case 0:
-			default:
-				break;
+		case ECC_BCH:
+			if (nand->bad_count > BCH_THRESHOLD)
+				mtd->ecc_stats.corrected +=
+					(nand->bad_count - BCH_THRESHOLD);
+			break;
+		case ECC_HAMMIN:
+			mtd->ecc_stats.corrected ++;
+		case ECC_NONE:
+		default:
+			break;
 		}
 	} else if (nand->retcode == ERR_DBERR) {
 		int buf_blank;
@@ -1026,8 +1077,8 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 	nand->mmio_phys = r->start;

 	/* initialize all interrupts to be disabled */
-	disable_int(nand, NDSR_MASK);
 	irq = platform_get_irq(pdev, 0);
+	disable_int(nand, NDCR_INT_MASK);
 	if (irq < 0) {
 		dev_err(&pdev->dev, "no IRQ resource defined\n");
 		ret = -ENXIO;
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 10:29:21 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 22:29:21 +0800
Subject: [PATCH 16/29] pxa3xx_nand: enable 4k page operation
Message-ID: <mailman.121.1280296792.27306.linux-arm-kernel@lists.infradead.org>

For limitation of our controller, we only could do large page
nand chip by dividing the original page size into what we could
afford. We call one divide operation as chunk.

The divide operation need naked command support, which may not
be existed in so old version. You should check it first before
you want to use this feature.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  363 +++++++++++++++++++++++++++++++---------
 1 files changed, 284 insertions(+), 79 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 204c9d6..45c9660 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -29,7 +29,10 @@
 #define	CHIP_DELAY_TIMEOUT	(2 * HZ/10)
 #define NAND_STOP_DELAY		(2 * HZ/50)
 #define PAGE_CHUNK_SIZE		(2048)
+#define OOB_CHUNK_SIZE		(64)
 #define BCH_THRESHOLD           (8)
+#define CMD_POOL_SIZE           (5)
+#define READ_ID_BYTES		(4)

 /* registers and bit definitions */
 #define NDCR		(0x00) /* Control register */
@@ -39,33 +42,50 @@
 #define NDPCR		(0x18) /* Page Count Register */
 #define NDBDR0		(0x1C) /* Bad Block Register 0 */
 #define NDBDR1		(0x20) /* Bad Block Register 1 */
+#define NDREDEL		(0x24) /* Read Enable Return Delay Register */
 #define NDECCCTRL	(0x28) /* ECC Control Register */
+#define NDBZCNT		(0x2C) /* Timer for NDRnB0 and NDRnB1 */
 #define NDDB		(0x40) /* Data Buffer */
 #define NDCB0		(0x48) /* Command Buffer0 */
 #define NDCB1		(0x4C) /* Command Buffer1 */
 #define NDCB2		(0x50) /* Command Buffer2 */

 #define NDCR_SPARE_EN		(0x1 << 31)
-#define NDSR_ERR_CNT_MASK       (0x1F << 16)
-#define NDSR_ERR_CNT(x)         (((x) << 16) & NDSR_ERR_CNT_MASK)
 #define NDCR_ECC_EN		(0x1 << 30)
 #define NDCR_DMA_EN		(0x1 << 29)
 #define NDCR_ND_RUN		(0x1 << 28)
 #define NDCR_DWIDTH_C		(0x1 << 27)
 #define NDCR_DWIDTH_M		(0x1 << 26)
-#define NDCR_PAGE_SZ		(0x1 << 24)
-#define NDCR_NCSX		(0x1 << 23)
-#define NDCR_ND_MODE		(0x3 << 21)
+#define NDCR_PAGE_SZ_MASK	(0x3 << 24)
+#define NDCR_PAGE_SZ(x)		(((x) << 24) & NDCR_PAGE_SZ_MASK)
+#define NDCR_SEQ_DIS		(0x1 << 23)
+#define NDCR_ND_STOP		(0x1 << 22)
+#define NDCR_FORCE_CSX		(0x1 << 21)
 #define NDCR_CLR_PG_CNT		(0x1 << 20)
 #define NDCR_STOP_ON_UNCOR	(0x1 << 19)
 #define NDCR_RD_ID_CNT_MASK	(0x7 << 16)
 #define NDCR_RD_ID_CNT(x)	(((x) << 16) & NDCR_RD_ID_CNT_MASK)

 #define NDCR_RA_START		(0x1 << 15)
-#define NDCR_PG_PER_BLK		(0x1 << 14)
+#define NDCR_PG_PER_BLK_MASK	(0x3 << 13)
+#define NDCR_PG_PER_BLK(x)	(((x) << 13) & NDCR_PG_PER_BLK_MASK)
 #define NDCR_ND_ARB_EN		(0x1 << 12)
 #define NDCR_INT_MASK           (0xFFF)
+#define NDCR_RDYM               (0x1 << 11)
+#define NDCR_CS0_PAGEDM         (0x1 << 10)
+#define NDCR_CS1_PAGEDM         (0x1 << 9)
+#define NDCR_CS0_CMDDM          (0x1 << 8)
+#define NDCR_CS1_CMDDM          (0x1 << 7)
+#define NDCR_CS0_BBDM           (0x1 << 6)
+#define NDCR_CS1_BBDM           (0x1 << 5)
+#define NDCR_UNCERRM            (0x1 << 4)
+#define NDCR_CORERRM            (0x1 << 3)
+#define NDCR_WRDREQM            (0x1 << 2)
+#define NDCR_RDDREQM            (0x1 << 1)
+#define NDCR_WRCMDREQM          (0x1)

+#define NDSR_ERR_CNT_MASK       (0x1F << 16)
+#define NDSR_ERR_CNT(x)         (((x) << 16) & NDSR_ERR_CNT_MASK)
 #define NDSR_MASK		(0xfff)
 #define NDSR_RDY                (0x1 << 12)
 #define NDSR_FLASH_RDY          (0x1 << 11)
@@ -81,6 +101,8 @@
 #define NDSR_RDDREQ		(0x1 << 1)
 #define NDSR_WRCMDREQ		(0x1)

+#define NDCB0_CMD_XTYPE_MASK    (0x7 << 29)
+#define NDCB0_CMD_XTYPE(x)      (((x) << 29) & NDCB0_CMD_XTYPE_MASK)
 #define NDCB0_ST_ROW_EN         (0x1 << 26)
 #define NDCB0_AUTO_RS		(0x1 << 25)
 #define NDCB0_CSEL		(0x1 << 24)
@@ -110,6 +132,7 @@
 #define get_mtd_by_info(info)		\
 	(struct mtd_info *)((void *)info - sizeof(struct mtd_info))

+#define STATE_MASK		(0x3f)
 /* error code and state */
 enum {
 	ERR_NONE	= 0,
@@ -142,7 +165,6 @@ struct pxa3xx_nand_info {
 	/* calculated from pxa3xx_nand_flash data */
 	uint8_t			col_addr_cycles;
 	uint8_t			row_addr_cycles;
-	uint8_t			read_id_bytes;

 	/* cached register value */
 	uint32_t		reg_ndcr;
@@ -178,7 +200,8 @@ struct pxa3xx_nand {
 	unsigned char		*oob_buff;
 	uint32_t		buf_start;
 	uint32_t		buf_count;
-	uint8_t			total_cmds;
+	uint16_t		data_column;
+	uint16_t		oob_column;

 	/* relate to the command */
 	uint8_t			chip_select;
@@ -187,8 +210,11 @@ struct pxa3xx_nand {
 	int			use_dma;	/* use DMA ? */
 	int 			retcode;

-	/* generated NDCBx register values */
-	uint32_t		ndcb0;
+	/* cached register value */
+	uint8_t			cmd_seqs;
+	uint8_t			total_cmds;
+	uint8_t			wait_ready[CMD_POOL_SIZE];
+	uint32_t		ndcb0[CMD_POOL_SIZE];
 	uint32_t		ndcb1;
 	uint32_t		ndcb2;
 };
@@ -235,6 +261,7 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
 { "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, ECC_HAMMIN, 1024,
NAND_SETTING_MICRON, },
 { "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, ECC_HAMMIN, 4096,
NAND_SETTING_MICRON, },
 { "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, ECC_HAMMIN, 4096,
NAND_SETTING_MICRON, },
+{ "1GiB 8-bit",    0x382c, 128, 4096,  8,  8, ECC_BCH,    2048,
NAND_SETTING_MICRON },
 { "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, ECC_HAMMIN, 2048,
NAND_SETTING_ST, },
 };

@@ -392,41 +419,98 @@ static void disable_int(struct pxa3xx_nand
*nand, uint32_t int_mask)
 	nand_writel(nand, NDCR, ndcr | int_mask);
 }

+static void nand_error_dump(struct pxa3xx_nand *nand)
+{
+	int i;
+
+	printk(KERN_ERR "NAND controller state wrong!!!\n");
+	printk(KERN_ERR "command %x, state %x, current seqs %d, errcode %x,
bad count %d\n",
+			nand->command, nand->state, nand->cmd_seqs,
+			nand->retcode, nand->bad_count);
+	printk(KERN_ERR "Totally %d command for sending\n",
+			nand->total_cmds);
+	for (i = 0; i < nand->total_cmds; i ++)
+		printk(KERN_ERR "NDCB0:%d: %x\n",
+				i, nand->ndcb0[i]);
+	printk(KERN_ERR "NDCB1: %x; NDCB2 %x\n", nand->ndcb1, nand->ndcb2);
+
+	printk(KERN_ERR "\nRegister DUMPing ##############\n");
+	printk(KERN_ERR "NDCR %x\n"
+			"NDSR %x\n"
+			"NDCB0 %x\n"
+			"NDCB1 %x\n"
+			"NDCB2 %x\n"
+			"NDTR0CS0 %x\n"
+			"NDTR1CS0 %x\n"
+			"NDBDR0 %x\n"
+			"NDBDR1 %x\n"
+			"NDREDEL %x\n"
+			"NDECCCTRL %x\n"
+			"NDBZCNT %x\n\n",
+			nand_readl(nand, NDCR),
+			nand_readl(nand, NDSR),
+			nand_readl(nand, NDCB0),
+			nand_readl(nand, NDCB1),
+			nand_readl(nand, NDCB2),
+			nand_readl(nand, NDTR0CS0),
+			nand_readl(nand, NDTR1CS0),
+			nand_readl(nand, NDBDR0),
+			nand_readl(nand, NDBDR1),
+			nand_readl(nand, NDREDEL),
+			nand_readl(nand, NDECCCTRL),
+			nand_readl(nand, NDBZCNT));
+}
+
 static void handle_data_pio(struct pxa3xx_nand *nand)
 {
+	unsigned int data_size, oob_size;
+
+	data_size = DIV_ROUND_UP(nand->data_size, 4);
+	oob_size = DIV_ROUND_UP(nand->oob_size, 4);
 	if (nand->state & STATE_IS_WRITE) {
-		__raw_writesl(nand->mmio_base + NDDB, nand->data_buff,
-				DIV_ROUND_UP(nand->data_size, 4));
+		__raw_writesl(nand->mmio_base + NDDB,
+				nand->data_buff + nand->data_column, data_size);
 		if (nand->oob_size > 0)
-			__raw_writesl(nand->mmio_base + NDDB, nand->oob_buff,
-					DIV_ROUND_UP(nand->oob_size, 4));
-
+			__raw_writesl(nand->mmio_base + NDDB,
+				nand->oob_buff + nand->oob_column, oob_size);
 	}
 	else {
-		__raw_readsl(nand->mmio_base + NDDB, nand->data_buff,
-				DIV_ROUND_UP(nand->data_size, 4));
+		__raw_readsl(nand->mmio_base + NDDB,
+				nand->data_buff + nand->data_column, data_size);
 		if (nand->oob_size > 0)
-			__raw_readsl(nand->mmio_base + NDDB, nand->oob_buff,
-					DIV_ROUND_UP(nand->oob_size, 4));
+			__raw_readsl(nand->mmio_base + NDDB,
+				nand->oob_buff + nand->oob_column, oob_size);
 	}
+	nand->data_column += (data_size << 2);
+	nand->oob_column += (oob_size << 2);
 }

 static void start_data_dma(struct pxa3xx_nand *nand, int dir_out)
 {
+	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
 	struct pxa_dma_desc *desc = nand->data_desc;
-	int dma_len = ALIGN(nand->data_size + nand->oob_size, 32);
-
-	desc->ddadr = DDADR_STOP;
-	desc->dcmd = DCMD_ENDIRQEN | DCMD_WIDTH4 | DCMD_BURST32 | dma_len;
+	struct pxa_dma_desc *desc_oob = nand->data_desc + 1;
+	unsigned int data_len = ALIGN(nand->data_size, 32);
+	unsigned int oob_len = ALIGN(nand->oob_size, 32);

+	desc_oob->ddadr = desc->ddadr = DDADR_STOP;
+	desc_oob->dcmd = desc->dcmd = DCMD_WIDTH4 | DCMD_BURST32;
 	if (dir_out) {
-		desc->dsadr = nand->data_buff_phys;
+		desc->dsadr = nand->data_buff_phys + nand->data_column;
 		desc->dtadr = nand->mmio_phys + NDDB;
-		desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG;
+		desc->dcmd |= DCMD_ENDIRQEN | DCMD_INCSRCADDR | DCMD_FLOWTRG |
(data_len + oob_len);
 	} else {
-		desc->dtadr = nand->data_buff_phys;
-		desc->dsadr = nand->mmio_phys + NDDB;
-		desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC;
+		if (nand->oob_size > 0) {
+			desc_oob->dtadr = nand->data_buff_phys
+					+ info->page_size + nand->oob_column;
+			desc_oob->dcmd |= DCMD_ENDIRQEN | DCMD_INCTRGADDR | DCMD_FLOWSRC | oob_len;
+			desc->ddadr = nand->data_desc_addr + sizeof(struct pxa_dma_desc);
+			desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC | data_len;
+		}
+		else
+			desc->dcmd |= DCMD_ENDIRQEN | DCMD_INCTRGADDR | DCMD_FLOWSRC | data_len;
+		desc->dtadr = nand->data_buff_phys + nand->data_column;
+		desc_oob->dsadr = desc->dsadr = nand->mmio_phys + NDDB;
 	}

 	DRCMR(nand->drcmr_dat) = DRCMR_MAPVLD | nand->data_dma_ch;
@@ -446,6 +530,8 @@ static void pxa3xx_nand_data_dma_irq(int channel,
void *data)
 		nand->retcode = ERR_DMABUSERR;
 	}

+	nand->data_column += nand->data_size;
+	nand->oob_column += nand->oob_size;
 	enable_int(nand, NDCR_INT_MASK);
 	nand_writel(nand, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
 }
@@ -454,7 +540,7 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 {
 	struct pxa3xx_nand *nand = devid;
 	struct pxa3xx_nand_info *info;
-	unsigned int status, is_completed = 0, cs;
+	unsigned int status, is_completed = 0, cs, cmd_seqs, ndcb1, ndcb2;
 	unsigned int ready, cmd_done, page_done, badblock_detect;

 	cs		= nand->chip_select;
@@ -463,13 +549,14 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 	page_done       = (cs) ? NDSR_CS1_PAGED : NDSR_CS0_PAGED;
 	badblock_detect = (cs) ? NDSR_CS1_BBD : NDSR_CS0_BBD;
 	info            = nand->info[cs];
+	cmd_seqs	= nand->cmd_seqs;

 	status = nand_readl(nand, NDSR);
 	nand->bad_count = (status & NDSR_ERR_CNT_MASK) >> 16;
-	if (status & NDSR_DBERR)
-		nand->retcode = ERR_DBERR;
 	if (status & NDSR_SBERR)
 		nand->retcode = ERR_SBERR;
+	if (status & NDSR_DBERR)
+		nand->retcode = ERR_DBERR;
 	if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {

 		nand->state |= STATE_DATA_PROCESSING;
@@ -483,24 +570,51 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)

 		nand->state |= STATE_DATA_DONE;
 	}
+	if (status & page_done)
+		nand->state |= STATE_PAGE_DONE;
+	if (status & ready) {
+		nand->state |= STATE_READY;
+		if (nand->wait_ready[cmd_seqs]) {
+			enable_int(nand, NDCR_WRCMDREQM);
+			if (cmd_seqs == nand->total_cmds)
+				is_completed = 1;
+		}
+	}
 	if (status & cmd_done) {
 		nand->state |= STATE_CMD_DONE;
-		is_completed = 1;
+		if (cmd_seqs == nand->total_cmds && !nand->wait_ready[cmd_seqs])
+			is_completed = 1;
 	}
-	if (status & ready)
-		nand->state |= STATE_READY;
-	if (status & page_done)
-		nand->state |= STATE_PAGE_DONE;

 	if (status & NDSR_WRCMDREQ) {
-		nand_writel(nand, NDSR, NDSR_WRCMDREQ);
 		status &= ~NDSR_WRCMDREQ;
-		nand->state |= STATE_CMD_WAIT_DONE;
-		nand_writel(nand, NDCB0, nand->ndcb0);
-		nand_writel(nand, NDCB0, nand->ndcb1);
-		nand_writel(nand, NDCB0, nand->ndcb2);
+		if (nand->wait_ready[cmd_seqs] && !(nand->state & STATE_READY)) {
+			disable_int(nand, NDCR_WRCMDREQM);
+			goto IRQ_FORCE_EXIT;
+		}
+
+		nand_writel(nand, NDSR, NDSR_WRCMDREQ);
+		if (cmd_seqs < nand->total_cmds) {
+			nand->cmd_seqs ++;
+			if (cmd_seqs == 0) {
+				ndcb1 = nand->ndcb1;
+				ndcb2 = nand->ndcb2;
+			}
+			else {
+				ndcb1 = 0;
+				ndcb2 = 0;
+			}
+			nand->state &= ~STATE_MASK;
+			nand->state |= STATE_CMD_WAIT_DONE;
+			nand_writel(nand, NDCB0, nand->ndcb0[cmd_seqs]);
+			nand_writel(nand, NDCB0, ndcb1);
+			nand_writel(nand, NDCB0, ndcb2);
+		}
+		else
+			is_completed = 1;
 	}

+IRQ_FORCE_EXIT:
 	/* clear NDSR to let the controller exit the IRQ */
 	nand_writel(nand, NDSR, status);
 	if (is_completed)
@@ -521,7 +635,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 		uint16_t column, int page_addr)
 {
 	uint16_t cmd;
-	int addr_cycle, exec_cmd, ndcb0;
+	int addr_cycle, exec_cmd, ndcb0, i, chunks = 0;
 	struct mtd_info *mtd;
 	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];

@@ -531,14 +645,19 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 	exec_cmd = 1;

 	/* reset data and oob column point to handle data */
+	nand->data_column	= 0;
+	nand->oob_column	= 0;
 	nand->buf_start		= 0;
 	nand->buf_count		= 0;
-	nand->ndcb0		= ndcb0;
+	nand->total_cmds	= 1;
+	nand->cmd_seqs		= 0;
 	nand->data_size		= 0;
 	nand->oob_size		= 0;
 	nand->use_ecc		= 0;
 	nand->use_dma		= 0;
 	nand->state		= 0;
+	nand->bad_count		= 0;
+	nand->retcode		= ERR_NONE;
 	nand->command		= command;

 	switch (command) {
@@ -549,6 +668,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 		pxa3xx_set_datasize(info);
 		nand->oob_buff = nand->data_buff + nand->data_size;
 		nand->use_dma = use_dma;
+		chunks = info->page_size / nand->data_size;
 		break;
 	case NAND_CMD_SEQIN:
 		exec_cmd = 0;
@@ -559,6 +679,11 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 		break;
 	}

+	/* clear the command buffer */
+	for (i = 0; i < CMD_POOL_SIZE; i ++) {
+		nand->ndcb0[i] = ndcb0;
+		nand->wait_ready[i] = 0;
+	}
 	addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
 			+ info->col_addr_cycles);

@@ -572,14 +697,37 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 			nand->buf_start = column;

 		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
-			nand->ndcb0 |= NDCB0_CMD_TYPE(0)
+			nand->ndcb0[0] |= NDCB0_CMD_TYPE(0)
 					| addr_cycle
 					| (cmd & NDCB0_CMD1_MASK);
-		else
-			nand->ndcb0 |= NDCB0_CMD_TYPE(0)
-					| NDCB0_DBC
-					| addr_cycle
-					| cmd;
+		else {
+			if (chunks == 1)
+				nand->ndcb0[0] |= NDCB0_CMD_TYPE(0)
+						| NDCB0_DBC
+						| addr_cycle
+						| cmd;
+			else {
+				nand->total_cmds = chunks + 1;
+				nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x6)
+						| NDCB0_CMD_TYPE(0)
+						| NDCB0_DBC
+						| NDCB0_NC
+						| addr_cycle
+						| cmd;
+
+				nand->ndcb0[1] |= NDCB0_CMD_XTYPE(0x5)
+						| NDCB0_NC
+						| addr_cycle;
+
+				for (i = 2; i <= chunks; i ++)
+					nand->ndcb0[i] = nand->ndcb0[1];
+
+				nand->ndcb0[chunks] &= ~NDCB0_NC;
+				/* we should wait RnB go high again
+				 * before read out data*/
+				nand->wait_ready[1] = 1;
+			}
+		}

 	case NAND_CMD_SEQIN:
 		/* small page addr setting */
@@ -612,18 +760,46 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,

 		cmd = info->cmdset->program;
 		nand->state |= STATE_IS_WRITE;
-		nand->ndcb0 |= NDCB0_CMD_TYPE(0x1)
-				| NDCB0_AUTO_RS
-				| NDCB0_ST_ROW_EN
-				| NDCB0_DBC
-				| cmd
-				| addr_cycle;
+		if (chunks == 1)
+			nand->ndcb0[0] |= NDCB0_CMD_TYPE(0x1)
+					| NDCB0_AUTO_RS
+					| NDCB0_ST_ROW_EN
+					| NDCB0_DBC
+					| cmd
+					| addr_cycle;
+		else {
+			nand->total_cmds = chunks + 1;
+			nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x4)
+					| NDCB0_CMD_TYPE(0x1)
+					| NDCB0_NC
+					| NDCB0_AUTO_RS
+					| (cmd & NDCB0_CMD1_MASK)
+					| addr_cycle;
+
+			for (i = 1; i < chunks; i ++)
+				nand->ndcb0[i] |= NDCB0_CMD_XTYPE(0x5)
+						| NDCB0_NC
+						| NDCB0_AUTO_RS
+						| NDCB0_CMD_TYPE(0x1)
+						| addr_cycle;
+
+			nand->ndcb0[chunks] |= NDCB0_CMD_XTYPE(0x3)
+						| NDCB0_CMD_TYPE(0x1)
+						| NDCB0_ST_ROW_EN
+						| NDCB0_DBC
+						| (cmd & NDCB0_CMD2_MASK)
+						| NDCB0_CMD1_MASK
+						| addr_cycle;
+			/* we should wait for RnB goes high which
+			 * indicate the data has been written succesfully*/
+			nand->wait_ready[nand->total_cmds] = 1;
+		}
 		break;

 	case NAND_CMD_READID:
 		cmd = info->cmdset->read_id;
-		nand->buf_count = info->read_id_bytes;
-		nand->ndcb0 |= NDCB0_CMD_TYPE(3)
+		nand->buf_count = READ_ID_BYTES;
+		nand->ndcb0[0] |= NDCB0_CMD_TYPE(3)
 				| NDCB0_ADDR_CYC(1)
 				| cmd;

@@ -632,7 +808,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 	case NAND_CMD_STATUS:
 		cmd = info->cmdset->read_status;
 		nand->buf_count = 1;
-		nand->ndcb0 |= NDCB0_CMD_TYPE(4)
+		nand->ndcb0[0] |= NDCB0_CMD_TYPE(4)
 				| NDCB0_ADDR_CYC(1)
 				| cmd;

@@ -641,7 +817,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,

 	case NAND_CMD_ERASE1:
 		cmd = info->cmdset->erase;
-		nand->ndcb0 |= NDCB0_CMD_TYPE(2)
+		nand->ndcb0[0] |= NDCB0_CMD_TYPE(2)
 				| NDCB0_AUTO_RS
 				| NDCB0_ADDR_CYC(3)
 				| NDCB0_DBC
@@ -652,7 +828,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 		break;
 	case NAND_CMD_RESET:
 		cmd = info->cmdset->reset;
-		nand->ndcb0 |= NDCB0_CMD_TYPE(5)
+		nand->ndcb0[0] |= NDCB0_CMD_TYPE(5)
 				| cmd;

 		break;
@@ -701,10 +877,10 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 				CHIP_DELAY_TIMEOUT);
 		if (!ret) {
 			dev_err(&nand->pdev->dev, "Wait time out!!!\n");
+			nand_error_dump(nand);
+			/* Stop State Machine for next command cycle */
+			pxa3xx_nand_stop(nand);
 		}
-		/* Stop State Machine for next command cycle */
-		pxa3xx_nand_stop(nand);
-		disable_int(nand, NDCR_INT_MASK);
 		nand->state &= ~STATE_CMD_PREPARED;
 	}
 }
@@ -796,20 +972,25 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
 	uint32_t ndcr = 0x00000FFF; /* disable all interrupts */

-	if (f->page_size != 2048 && f->page_size != 512)
+	if (f->page_size != 4096 && f->page_size != 2048 && f->page_size != 512)
 		return -EINVAL;

 	if (f->flash_width != 16 && f->flash_width != 8)
 		return -EINVAL;

+	if (f->page_size > PAGE_CHUNK_SIZE
+			&& !(pdata->controller_attrs & PXA3XX_NAKED_CMD_EN)) {
+		printk(KERN_ERR "Your controller don't support 4k or larger "
+			       "page NAND for don't support naked command\n");
+		return -EINVAL;
+	}
 	/* calculate flash information */
 	info->use_ecc = f->ecc_type;
 	info->cmdset = f->cmdset;
 	info->page_size = f->page_size;
-	info->read_id_bytes = (f->page_size == 2048) ? 4 : 2;

 	/* calculate addressing information */
-	info->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
+	info->col_addr_cycles = (f->page_size >= 2048) ? 2 : 1;

 	if (f->num_blocks * f->page_per_block > 65536)
 		info->row_addr_cycles = 3;
@@ -818,16 +999,39 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,

 	ndcr |= (pdata->controller_attrs & PXA3XX_ARBI_EN) ? NDCR_ND_ARB_EN : 0;
 	ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
-	ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
-	ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
 	ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
 	ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
+	switch (f->page_per_block) {
+	case 32:
+		ndcr |= NDCR_PG_PER_BLK(0x0);
+		break;
+	case 128:
+		ndcr |= NDCR_PG_PER_BLK(0x1);
+		break;
+	case 256:
+		ndcr |= NDCR_PG_PER_BLK(0x3);
+		break;
+	case 64:
+	default:
+		ndcr |= NDCR_PG_PER_BLK(0x2);
+		break;
+	}

-	ndcr |= NDCR_RD_ID_CNT(info->read_id_bytes);
+	switch (f->page_size) {
+	case 512:
+		ndcr |= NDCR_PAGE_SZ(0x0);
+		break;
+	case 2048:
+	default:
+		ndcr |= NDCR_PAGE_SZ(0x1);
+		ndcr |= NDCR_FORCE_CSX;
+		break;
+	}
+
+	ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
 	ndcr |= NDCR_SPARE_EN; /* enable spare by default */

 	info->reg_ndcr = ndcr;
-
 	pxa3xx_nand_set_timing(info, f->timing);
 	return 0;
 }
@@ -842,9 +1046,8 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand *nand)
 		printk(KERN_ERR "We could not detect configure if two cs is supported!!\n");
 		BUG();
 	}
-	info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
+	info->page_size = ndcr & NDCR_PAGE_SZ_MASK ? 2048 : 512;
 	/* set info fields needed to read id */
-	info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
 	info->reg_ndcr = ndcr;

 	info->ndtr0cs0 = nand_readl(nand, NDTR0CS0);
@@ -855,11 +1058,10 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand *nand)
 	return 0;
 }

-/* the maximum possible buffer size for large page with OOB data
- * is: 2048 + 64 = 2112 bytes, allocate a page here for both the
- * data buffer and the DMA descriptor
+/* the max buff size should be large than the largest size
+ * of page of NAND flash that currently controller support
  */
-#define MAX_BUFF_SIZE	PAGE_SIZE
+#define MAX_BUFF_SIZE	((PAGE_CHUNK_SIZE + OOB_CHUNK_SIZE) * 2) +
sizeof(struct pxa_dma_desc) * 2
 static void free_cs_resource(struct pxa3xx_nand_info *info, int cs)
 {
 	struct pxa3xx_nand *nand;
@@ -926,7 +1128,8 @@ static int __devinit pxa3xx_nand_sensing(struct
pxa3xx_nand *nand)
 	struct mtd_info *mtd = get_mtd_by_info(info);

 	/* use the common timing to make a try */
-	pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
+	if (pxa3xx_nand_config_flash(info, &builtin_flash_types[0]))
+		return 0;
 	pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
 	if (nand->state & STATE_READY)
 		return 1;
@@ -947,6 +1150,7 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd)
 	uint64_t chipsize;
 	int i, ret;

+	nand->chip_select = info->chip_select;
 	if (pdata->controller_attrs & PXA3XX_KEEP_CONFIG) {
 		if (pxa3xx_nand_detect_config(nand) == 0)
 			goto KEEP_CONFIG;
@@ -985,7 +1189,8 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd)
 		return -EINVAL;
 	}

-	pxa3xx_nand_config_flash(info, f);
+	if (pxa3xx_nand_config_flash(info, f))
+		return -EINVAL;
 	pxa3xx_flash_ids[0].name = f->name;
 	pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff;
 	pxa3xx_flash_ids[0].pagesize = f->page_size;
@@ -1021,7 +1226,7 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 	struct pxa3xx_nand *nand;
 	struct resource *r;
 	int ret, irq, cs;
-	int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc);
+	int data_desc_offset = MAX_BUFF_SIZE - sizeof(struct pxa_dma_desc) * 2;

 	nand = kzalloc(sizeof(struct pxa3xx_nand), GFP_KERNEL);
 	if (!nand) {
-- 
1.7.0.4


From leiwen at marvell.com  Thu Jun  3 04:21:04 2010
From: leiwen at marvell.com (Lei Wen)
Date: Thu, 3 Jun 2010 16:21:04 +0800
Subject: [PATCH 18/29] mmp: add nand support to mmp2
Message-ID: <mailman.124.1280296821.27306.linux-arm-kernel@lists.infradead.org>

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/configs/mmp2_defconfig       |    4 +-
 arch/arm/mach-mmp/include/mach/mmp2.h |    6 ++++
 arch/arm/mach-mmp/jasper.c            |   52 +++++++++++++++++++++++++++++++++
 3 files changed, 60 insertions(+), 2 deletions(-)

diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
index 4b55dcb..e63dec3 100644
--- a/arch/arm/configs/mmp2_defconfig
+++ b/arch/arm/configs/mmp2_defconfig
@@ -469,7 +469,7 @@ CONFIG_MTD_CMDLINE_PARTS=y
 #
 # User Modules And Translation Layers
 #
-# CONFIG_MTD_CHAR is not set
+CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLKDEVS=y
 CONFIG_MTD_BLOCK=y
 # CONFIG_FTL is not set
@@ -525,7 +525,7 @@ CONFIG_MTD_NAND=y
 # CONFIG_MTD_NAND_GPIO is not set
 CONFIG_MTD_NAND_IDS=y
 # CONFIG_MTD_NAND_DISKONCHIP is not set
-# CONFIG_MTD_NAND_PXA3xx is not set
+CONFIG_MTD_NAND_PXA3xx=y
 # CONFIG_MTD_NAND_NANDSIM is not set
 # CONFIG_MTD_NAND_PLATFORM is not set
 CONFIG_MTD_ONENAND=y
diff --git a/arch/arm/mach-mmp/include/mach/mmp2.h
b/arch/arm/mach-mmp/include/mach/mmp2.h
index fec220b..d68890b 100644
--- a/arch/arm/mach-mmp/include/mach/mmp2.h
+++ b/arch/arm/mach-mmp/include/mach/mmp2.h
@@ -4,6 +4,7 @@
 #include <linux/i2c.h>
 #include <mach/devices.h>
 #include <plat/i2c.h>
+#include <plat/pxa3xx_nand.h>

 extern struct pxa_device_desc mmp2_device_uart1;
 extern struct pxa_device_desc mmp2_device_uart2;
@@ -15,6 +16,7 @@ extern struct pxa_device_desc mmp2_device_twsi3;
 extern struct pxa_device_desc mmp2_device_twsi4;
 extern struct pxa_device_desc mmp2_device_twsi5;
 extern struct pxa_device_desc mmp2_device_twsi6;
+extern struct pxa_device_desc mmp2_device_nand;

 static inline int mmp2_add_uart(int id)
 {
@@ -56,5 +58,9 @@ static inline int mmp2_add_twsi(int id, struct
i2c_pxa_platform_data *data,
 	return pxa_register_device(d, data, sizeof(*data));
 }

+static inline int mmp2_add_nand(struct pxa3xx_nand_platform_data *data)
+{
+	return pxa_register_device(&mmp2_device_nand, data, sizeof(*data));
+}
 #endif /* __ASM_MACH_MMP2_H */

diff --git a/arch/arm/mach-mmp/jasper.c b/arch/arm/mach-mmp/jasper.c
index d77dd41..5d055f3 100644
--- a/arch/arm/mach-mmp/jasper.c
+++ b/arch/arm/mach-mmp/jasper.c
@@ -67,6 +67,57 @@ static unsigned long jasper_pin_config[] __initdata = {
 	PMIC_PMIC_INT | MFP_LPM_EDGE_FALL,
 };

+static struct mtd_partition jasper_nand_partitions[] = {
+	[0] = {
+		.name		= "Bootloader",
+		.offset		= 0,
+		.size		= 0x100000,
+		.mask_flags	= MTD_WRITEABLE,
+	},
+	[1] = {
+		.name		= "Reserve",
+		.offset		= 0x100000,
+		.size		= 0x080000,
+	},
+	[2] = {
+		.name		= "Reserve",
+		.offset		= 0x180000,
+		.size		= 0x800000,
+		.mask_flags	= MTD_WRITEABLE,
+	},
+	[3] = {
+		.name		= "Kernel",
+		.offset		= 0x980000,
+		.size		= 0x300000,
+		.mask_flags	= MTD_WRITEABLE,
+	},
+	[4] = {
+		.name		= "system",
+		.offset		= 0x0c80000,
+		.size		= 0x7000000,
+	},
+	[5] = {
+		.name		= "userdata",
+		.offset		= 0x7c80000,
+		.size		= 0x7000000,
+	},
+	[6] = {
+		.name		= "filesystem",
+		.offset		= 0x0ec80000,
+		.size		= MTDPART_SIZ_FULL,
+	}
+};
+
+static struct pxa3xx_nand_platform_data jasper_nand_info;
+static void __init jasper_init_flash(void)
+{
+	jasper_nand_info.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_NAKED_CMD_EN
+		| PXA3XX_DMA_EN | PXA3XX_ADV_TIME_TUNING | PXA3XX_TWO_CHIP_EN;
+	jasper_nand_info.parts[0] = jasper_nand_partitions;
+	jasper_nand_info.nr_parts[0] = ARRAY_SIZE(jasper_nand_partitions);
+	mmp2_add_nand(&jasper_nand_info);
+}
+
 static struct regulator_consumer_supply max8649_supply[] = {
 	REGULATOR_SUPPLY("vcc_core", NULL),
 };
@@ -128,6 +179,7 @@ static void __init jasper_init(void)
 	/* on-chip devices */
 	mmp2_add_uart(1);
 	mmp2_add_uart(3);
+	jasper_init_flash();
 	mmp2_add_twsi(1, NULL, ARRAY_AND_SIZE(jasper_twsi1_info));

 	regulator_has_full_constraints();
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 11:06:01 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 23:06:01 +0800
Subject: [PATCH 22/29] pxa3xx_nand: support ecc requirement higher
Message-ID: <mailman.129.1280296882.27306.linux-arm-kernel@lists.infradead.org>

than 4bit per 512 bytes

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa3xx_nand.h |    2 +-
 drivers/mtd/nand/pxa3xx_nand.c               |  117 +++++++++++++++----------
 2 files changed, 71 insertions(+), 48 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index c20ac35..2f1a1cf 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -43,7 +43,7 @@ struct pxa3xx_nand_flash {
 	uint16_t 	page_size;	/* Page size in bytes */
 	uint8_t		flash_width;	/* Width of Flash memory (DWIDTH_M) */
 	uint8_t 	dfc_width;	/* Width of flash controller(DWIDTH_C) */
-	uint8_t		ecc_type;	/* Which ECC is applied */
+	uint8_t		ecc_strength;	/* How strong a ecc should be applied */
 	uint32_t	num_blocks;	/* Number of physical blocks in Flash */
 	struct pxa3xx_nand_cmdset *cmdset;	/* NAND command set */
 	struct pxa3xx_nand_timing *timing;	/* NAND Flash timing */
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index b0a0ccf..8f7ab2d 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -33,6 +33,8 @@
 #define BCH_THRESHOLD           (8)
 #define CMD_POOL_SIZE           (5)
 #define READ_ID_BYTES		(4)
+#define BCH_STRENGTH		(4)
+#define HAMMING_STRENGTH	(1)

 /* registers and bit definitions */
 #define NDCR		(0x00) /* Control register */
@@ -84,9 +86,9 @@
 #define NDCR_RDDREQM            (0x1 << 1)
 #define NDCR_WRCMDREQM          (0x1)

+#define NDSR_MASK		(0xffffffff)
 #define NDSR_ERR_CNT_MASK       (0x1F << 16)
 #define NDSR_ERR_CNT(x)         (((x) << 16) & NDSR_ERR_CNT_MASK)
-#define NDSR_MASK		(0xfff)
 #define NDSR_RDY                (0x1 << 12)
 #define NDSR_FLASH_RDY          (0x1 << 11)
 #define NDSR_CS0_PAGED		(0x1 << 10)
@@ -103,6 +105,7 @@

 #define NDCB0_CMD_XTYPE_MASK    (0x7 << 29)
 #define NDCB0_CMD_XTYPE(x)      (((x) << 29) & NDCB0_CMD_XTYPE_MASK)
+#define NDCB0_LEN_OVRD		(0x1 << 28)
 #define NDCB0_ST_ROW_EN         (0x1 << 26)
 #define NDCB0_AUTO_RS		(0x1 << 25)
 #define NDCB0_CSEL		(0x1 << 24)
@@ -161,7 +164,7 @@ struct pxa3xx_nand_info {
 	int			page_addr;
 	uint16_t		page_size;
 	uint8_t			chip_select;
-	uint8_t			use_ecc;
+	uint8_t			ecc_strength;

 	/* calculated from pxa3xx_nand_flash data */
 	uint8_t			col_addr_cycles;
@@ -206,8 +209,8 @@ struct pxa3xx_nand {

 	/* relate to the command */
 	uint8_t			chip_select;
+	uint8_t			ecc_strength;
 	unsigned int		state;
-	int			use_ecc;	/* use HW ECC ? */
 	int			use_dma;	/* use DMA ? */
 	int 			retcode;

@@ -218,6 +221,7 @@ struct pxa3xx_nand {
 	uint32_t		ndcb0[CMD_POOL_SIZE];
 	uint32_t		ndcb1;
 	uint32_t		ndcb2;
+	uint32_t		ndcb3[CMD_POOL_SIZE];
 };

 static int use_dma = 1;
@@ -253,17 +257,17 @@ static struct pxa3xx_nand_timing __devinitdata
timing[] = {
 #define NAND_SETTING_MICRON      &default_cmdset, &timing[2]
 #define NAND_SETTING_ST          &default_cmdset, &timing[3]
 static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
-{ "DEFAULT FLASH",      0,       0,  0, 2048,  8,  8, ECC_NONE,
0, NAND_SETTING_DEFAULT, },
-{ "64MiB 16-bit",  0x46ec, 0xffff,  32,  512, 16, 16, ECC_HAMMIN,
4096, NAND_SETTING_SAMSUNG, },
-{ "256MiB 8-bit",  0xdaec, 0xffff,  64, 2048,  8,  8, ECC_HAMMIN,
2048, NAND_SETTING_SAMSUNG, },
-{ "1GiB 8-bit",    0xd3ec, 0xffff, 128, 2048,  8,  8, ECC_BCH,
4096, NAND_SETTING_SAMSUNG, },
-{ "4GiB 8-bit",    0xd7ec, 0x29d5, 128, 4096,  8,  8, ECC_BCH,
8192, NAND_SETTING_SAMSUNG, },
-{ "128MiB 8-bit",  0xa12c, 0xffff,  64, 2048,  8,  8, ECC_HAMMIN,
1024, NAND_SETTING_MICRON, },
-{ "128MiB 16-bit", 0xb12c, 0xffff,  64, 2048, 16, 16, ECC_HAMMIN,
1024, NAND_SETTING_MICRON, },
-{ "512MiB 8-bit",  0xdc2c, 0xffff,  64, 2048,  8,  8, ECC_HAMMIN,
4096, NAND_SETTING_MICRON, },
-{ "512MiB 16-bit", 0xcc2c, 0xffff,  64, 2048, 16, 16, ECC_HAMMIN,
4096, NAND_SETTING_MICRON, },
-{ "1GiB 8-bit",    0x382c, 0xffff, 128, 4096,  8,  8, ECC_BCH,
2048, NAND_SETTING_MICRON },
-{ "256MiB 16-bit", 0xba20, 0xffff,  64, 2048, 16, 16, ECC_HAMMIN,
2048, NAND_SETTING_ST, },
+{ "DEFAULT FLASH",      0,       0,  0, 2048,  8,  8, 0,    0,
NAND_SETTING_DEFAULT, },
+{ "64MiB 16-bit",  0x46ec, 0xffff,  32,  512, 16, 16, 1, 4096,
NAND_SETTING_SAMSUNG, },
+{ "256MiB 8-bit",  0xdaec, 0xffff,  64, 2048,  8,  8, 1, 2048,
NAND_SETTING_SAMSUNG, },
+{ "1GiB 8-bit",    0xd3ec, 0xffff, 128, 2048,  8,  8, 4, 4096,
NAND_SETTING_SAMSUNG, },
+{ "4GiB 8-bit",    0xd7ec, 0x29d5, 128, 4096,  8,  8, 8, 8192,
NAND_SETTING_SAMSUNG, },
+{ "128MiB 8-bit",  0xa12c, 0xffff,  64, 2048,  8,  8, 1, 1024,
NAND_SETTING_MICRON, },
+{ "128MiB 16-bit", 0xb12c, 0xffff,  64, 2048, 16, 16, 1, 1024,
NAND_SETTING_MICRON, },
+{ "512MiB 8-bit",  0xdc2c, 0xffff,  64, 2048,  8,  8, 1, 4096,
NAND_SETTING_MICRON, },
+{ "512MiB 16-bit", 0xcc2c, 0xffff,  64, 2048, 16, 16, 1, 4096,
NAND_SETTING_MICRON, },
+{ "1GiB 8-bit",    0x382c, 0xffff, 128, 4096,  8,  8, 4, 2048,
NAND_SETTING_MICRON },
+{ "256MiB 16-bit", 0xba20, 0xffff,  64, 2048, 16, 16, 1, 2048,
NAND_SETTING_ST, },
 };

 static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
@@ -319,16 +323,15 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
 			return;
 		}

-		switch (nand->use_ecc) {
-		case ECC_HAMMIN:
-			nand->oob_size = 40;
+		switch (nand->ecc_strength) {
+		case 0:
+			nand->oob_size = 64;
 			break;
-		case ECC_BCH:
-			nand->oob_size = 32;
+		case HAMMING_STRENGTH:
+			nand->oob_size = 40;
 			break;
 		default:
-			nand->oob_size = 64;
-			break;
+			nand->oob_size = 32;
 		}
 	} else {
 		nand->data_size = 512;
@@ -337,17 +340,16 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
 			return;
 		}

-		switch (nand->use_ecc) {
-		case ECC_HAMMIN:
+		switch (nand->ecc_strength) {
+		case 0:
+			nand->oob_size = 16;
+			break;
+		case HAMMING_STRENGTH:
 			nand->oob_size = 8;
 			break;
-		case ECC_BCH:
+		default:
 			printk("Don't support BCH on small page device!!!\n");
 			BUG();
-			break;
-		default:
-			nand->oob_size = 16;
-			break;
 		}
 	}
 }
@@ -365,16 +367,16 @@ static void pxa3xx_nand_start(struct pxa3xx_nand *nand)

 	info = nand->info[nand->chip_select];
 	ndcr = info->reg_ndcr;
-	ndcr |= nand->use_dma ? NDCR_DMA_EN : NDCR_STOP_ON_UNCOR;
+	ndcr |= nand->use_dma ? NDCR_DMA_EN : 0;
 	ndcr |= NDCR_ND_RUN;

-	switch (nand->use_ecc) {
-	case ECC_BCH:
+	switch (nand->ecc_strength) {
+	default:
 		ndeccctrl |= NDECCCTRL_BCH_EN;
 		ndeccctrl |= NDECCCTRL_ECC_THRESH(BCH_THRESHOLD);
-	case ECC_HAMMIN:
+	case HAMMING_STRENGTH:
 		ndcr |= NDCR_ECC_EN;
-	default:
+	case 0:
 		break;
 	}

@@ -610,6 +612,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 			nand_writel(nand, NDCB0, nand->ndcb0[cmd_seqs]);
 			nand_writel(nand, NDCB0, ndcb1);
 			nand_writel(nand, NDCB0, ndcb2);
+			if (nand->ndcb3[cmd_seqs])
+				nand_writel(nand, NDCB0, nand->ndcb3[cmd_seqs]);
 		}
 		else
 			is_completed = 1;
@@ -654,7 +658,6 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 	nand->cmd_seqs		= 0;
 	nand->data_size		= 0;
 	nand->oob_size		= 0;
-	nand->use_ecc		= 0;
 	nand->use_dma		= 0;
 	nand->state		= 0;
 	nand->bad_count		= 0;
@@ -667,11 +670,23 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 		pxa3xx_set_datasize(info);
 		nand->use_dma = use_dma;
 		chunks = info->page_size / nand->data_size;
+		if (info->ecc_strength > BCH_STRENGTH) {
+			i = info->ecc_strength / BCH_STRENGTH;
+			nand->data_size /= i;
+			ndcb0 |= NDCB0_LEN_OVRD;
+			chunks *= i;
+		}
 		break;
+	case NAND_CMD_READOOB:
+		if (info->ecc_strength > BCH_STRENGTH) {
+			printk(KERN_ERR "we don't support oob command if use"
+				     " 8bit per 512bytes ecc feature!!\n");
+			BUG();
+		}
 	default:
 		nand->ndcb1 = 0;
 		nand->ndcb2 = 0;
-		nand->use_ecc = ECC_NONE;
+		nand->ecc_strength = 0;
 		break;
 	}
 	if (nand->use_dma) {
@@ -683,6 +698,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 	for (i = 0; i < CMD_POOL_SIZE; i ++) {
 		nand->ndcb0[i] = ndcb0;
 		nand->wait_ready[i] = 0;
+		nand->ndcb3[i] = (ndcb0 & NDCB0_LEN_OVRD)? nand->data_size : 0;
 	}
 	addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
 			+ info->col_addr_cycles);
@@ -690,7 +706,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 	switch (command) {
 	case NAND_CMD_READ0:
 	case NAND_CMD_SEQIN:
-		nand->use_ecc = info->use_ecc;
+		nand->ecc_strength = info->ecc_strength;
 	case NAND_CMD_READOOB:
 		memset(nand->data_buff, 0xff, column);
 		nand->buf_count = mtd->writesize + mtd->oobsize;
@@ -737,7 +753,8 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 				| NDCB0_NC
 				| addr_cycle
 				| cmd;
-
+		nand->ndcb0[0] &= ~NDCB0_LEN_OVRD;
+		nand->ndcb3[0] = 0;
 		nand->ndcb0[1] |= NDCB0_CMD_XTYPE(0x5)
 				| NDCB0_NC
 				| addr_cycle;
@@ -792,6 +809,8 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 				| (cmd & NDCB0_CMD2_MASK)
 				| NDCB0_CMD1_MASK
 				| addr_cycle;
+		nand->ndcb0[chunks] &= ~NDCB0_LEN_OVRD;
+		nand->ndcb3[chunks] = 0;
 		/* we should wait for RnB goes high which
 		 * indicate the data has been written succesfully*/
 		nand->wait_ready[nand->total_cmds] = 1;
@@ -988,7 +1007,12 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 		return -EINVAL;
 	}
 	/* calculate flash information */
-	info->use_ecc = f->ecc_type;
+	if (f->ecc_strength != 0 && f->ecc_strength != HAMMING_STRENGTH
+	    && (f->ecc_strength % BCH_STRENGTH != 0)) {
+		printk(KERN_ERR "ECC strength definition error, please recheck!!\n");
+		return -EINVAL;
+	}
+	info->ecc_strength = f->ecc_strength;
 	info->cmdset = f->cmdset;
 	info->page_size = f->page_size;

@@ -1032,7 +1056,9 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	}

 	ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
-	ndcr |= NDCR_SPARE_EN; /* enable spare by default */
+	/* only enable spare area when ecc is lower than 8bits per 512 bytes */
+	if (f->ecc_strength <= BCH_STRENGTH)
+		ndcr |= NDCR_SPARE_EN;

 	info->reg_ndcr = ndcr;
 	pxa3xx_nand_set_timing(info, f->timing);
@@ -1055,7 +1081,7 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand *nand)

 	info->ndtr0cs0 = nand_readl(nand, NDTR0CS0);
 	info->ndtr1cs0 = nand_readl(nand, NDTR1CS0);
-	info->use_ecc = (ndeccctrl & NDECCCTRL_BCH_EN) ? ECC_BCH : ECC_HAMMIN;
+	info->ecc_strength = (ndeccctrl & NDECCCTRL_BCH_EN) ? BCH_STRENGTH :
HAMMING_STRENGTH;
 	info->cmdset = &default_cmdset;

 	return 0;
@@ -1091,19 +1117,16 @@ static void pxa3xx_read_page(struct mtd_info
*mtd, uint8_t *buf)
 	pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RNDOUT, 0, info->page_addr);
 	switch (nand->retcode) {
 	case ERR_SBERR:
-		switch (nand->use_ecc) {
-		case ECC_BCH:
+		switch (nand->ecc_strength) {
+		default:
 			if (nand->bad_count > BCH_THRESHOLD)
 				mtd->ecc_stats.corrected +=
 					(nand->bad_count - BCH_THRESHOLD);
 			break;

-		case ECC_HAMMIN:
+		case HAMMING_STRENGTH:
 			mtd->ecc_stats.corrected ++;
-			break;
-
-		case ECC_NONE:
-		default:
+		case 0:
 			break;
 		}
 		break;
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 11:09:03 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 23:09:03 +0800
Subject: [PATCH 23/29] pxa3xx_nand: add advanced timing tuning feature
Message-ID: <mailman.131.1280296904.27306.linux-arm-kernel@lists.infradead.org>

For new controller, it has more power at more precise timing
tuning.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa3xx_nand.h |    2 +
 drivers/mtd/nand/pxa3xx_nand.c               |   91 ++++++++++++++++++--------
 2 files changed, 65 insertions(+), 28 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index 2f1a1cf..f7c16d3 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -11,6 +11,7 @@ enum {
 };

 struct pxa3xx_nand_timing {
+	unsigned int	tADL; /* Adress to Write Data delay */
 	unsigned int	tCH;  /* Enable signal hold time */
 	unsigned int	tCS;  /* Enable signal setup time */
 	unsigned int	tWH;  /* ND_nWE high duration */
@@ -18,6 +19,7 @@ struct pxa3xx_nand_timing {
 	unsigned int	tRH;  /* ND_nRE high duration */
 	unsigned int	tRP;  /* ND_nRE pulse width */
 	unsigned int	tR;   /* ND_nWE high to ND_nRE low for read */
+	unsigned int	tRHW; /* delay for next command issue */
 	unsigned int	tWHR; /* ND_nWE high to ND_nRE low for status read */
 	unsigned int	tAR;  /* ND_ALE low to ND_nRE low delay */
 };
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 8f7ab2d..9a37517 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -246,10 +246,10 @@ static struct pxa3xx_nand_cmdset default_cmdset = {
 };

 static struct pxa3xx_nand_timing __devinitdata timing[] = {
-	{ 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
-	{ 10,  0, 20,  40, 30,  40, 11123, 110, 10, },
-	{ 10, 25, 15,  25, 15,  30, 25000,  60, 10, },
-	{ 10, 35, 15,  25, 15,  25, 25000,  60, 10, },
+	{   0, 40, 80, 60, 100, 80, 100, 90000,  0, 400, 40, },
+	{ 200, 10,  0, 20,  40, 30,  40, 11123, 20, 110, 10, },
+	{   0, 10, 25, 15,  25, 15,  30, 25000,  0,  60, 10, },
+	{   0, 10, 35, 15,  25, 15,  25, 25000,  0,  60, 10, },
 };

 #define NAND_SETTING_DEFAULT     &default_cmdset, &timing[0]
@@ -272,16 +272,20 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {

 static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};

-#define NDTR0_tCH(c)	(min((c), 7) << 19)
-#define NDTR0_tCS(c)	(min((c), 7) << 16)
-#define NDTR0_tWH(c)	(min((c), 7) << 11)
-#define NDTR0_tWP(c)	(min((c), 7) << 8)
-#define NDTR0_tRH(c)	(min((c), 7) << 3)
-#define NDTR0_tRP(c)	(min((c), 7) << 0)
-
-#define NDTR1_tR(c)	(min((c), 65535) << 16)
-#define NDTR1_tWHR(c)	(min((c), 15) << 4)
-#define NDTR1_tAR(c)	(min((c), 15) << 0)
+#define NDTR0_tADL(c)		(min_t(uint32_t, (c), 31) << 27)
+#define NDTR0_tCH(c)		(min_t(uint32_t, (c), 7) << 19)
+#define NDTR0_tCS(c)		(min_t(uint32_t, (c), 7) << 16)
+#define NDTR0_tWH(c)		(min_t(uint32_t, (c), 7) << 11)
+#define NDTR0_tWP(c)		(min_t(uint32_t, (c), 7) << 8)
+#define NDTR0_ETRP		(0x1 << 6)
+#define NDTR0_tRH(c)		(min_t(uint32_t, (c), 7) << 3)
+#define NDTR0_tRP(c)		(min_t(uint32_t, (c), 7) << 0)
+
+#define NDTR1_tR(c)		(min_t(uint32_t, (c), 65535) << 16)
+#define NDTR1_PRESCALE		(0x1 << 14)
+#define NDTR1_tRHW(c)		(min_t(uint32_t, (c), 3) << 8)
+#define NDTR1_tWHR(c)		(min_t(uint32_t, (c), 15) << 4)
+#define NDTR1_tAR(c)		(min_t(uint32_t, (c), 15) << 0)

 /* convert nano-seconds to nand flash controller clock cycles */
 #define ns2cycle(ns, clk)	(int)((ns) * (clk / 1000000) / 1000)
@@ -290,20 +294,51 @@ static void pxa3xx_nand_set_timing(struct
pxa3xx_nand_info *info,
 				   const struct pxa3xx_nand_timing *t)
 {
 	struct pxa3xx_nand *nand = info->nand_data;
-	unsigned long nand_clk;
-	uint32_t ndtr0, ndtr1;
-
-	nand_clk = clk_get_rate(nand->clk);
-	ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
-		NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
-		NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
-		NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
-		NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
-		NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
-
-	ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
-		NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
-		NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
+	struct platform_device *pdev = nand->pdev;
+	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
+	unsigned long nand_clk = clk_get_rate(nand->clk);
+	uint32_t ndtr0, ndtr1, tRP, tR, tRHW, tADL;
+
+	tR = ns2cycle(t->tR, nand_clk);
+	tRP = ns2cycle(t->tRP, nand_clk);
+	tRHW = tADL = ndtr0 = ndtr1 = 0;
+	if (pdata->controller_attrs & PXA3XX_NAKED_CMD_EN)
+		tR = 0;
+	if (pdata->controller_attrs & PXA3XX_ADV_TIME_TUNING) {
+		if (tRP > 0x7) {
+			ndtr0 |= NDTR0_ETRP;
+			tRP -= 0x7;
+		}
+		if (tR > 0xffff) {
+			ndtr1 |= NDTR1_PRESCALE;
+			tR /= 16;
+		}
+		if (t->tRHW > 0) {
+			tRHW = ns2cycle(t->tRHW, nand_clk);
+			if (tRHW < 16)
+				tRHW = 1;
+			else {
+				if (tRHW < 32)
+					tRHW = 2;
+				else
+					tRHW = 3;
+			}
+		}
+		tADL = ns2cycle(t->tADL, nand_clk);
+	}
+
+	ndtr0 |= NDTR0_tADL(tADL)
+		| NDTR0_tCH(ns2cycle(t->tCH, nand_clk))
+		| NDTR0_tCS(ns2cycle(t->tCS, nand_clk))
+		| NDTR0_tWH(ns2cycle(t->tWH, nand_clk))
+		| NDTR0_tWP(ns2cycle(t->tWP, nand_clk))
+		| NDTR0_tRH(ns2cycle(t->tRH, nand_clk))
+		| NDTR0_tRP(tRP);
+
+	ndtr1 |= NDTR1_tR(tR)
+		| NDTR1_tRHW(tRHW)
+		| NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk))
+		| NDTR1_tAR(ns2cycle(t->tAR, nand_clk));

 	info->ndtr0cs0 = ndtr0;
 	info->ndtr1cs0 = ndtr1;
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 10:08:13 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 22:08:13 +0800
Subject: [PATCH 15/29] pxa3xx_nand: add more attribute that platform
Message-ID: <mailman.133.1280296951.27306.linux-arm-kernel@lists.infradead.org>

could choose from

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 arch/arm/mach-mmp/aspenite.c                 |    3 ++-
 arch/arm/mach-mmp/avengers_lite.c            |    3 ++-
 arch/arm/mach-pxa/cm-x300.c                  |    3 +--
 arch/arm/mach-pxa/colibri-pxa3xx.c           |    3 +--
 arch/arm/mach-pxa/littleton.c                |    2 +-
 arch/arm/mach-pxa/mxm8x10.c                  |    3 +--
 arch/arm/mach-pxa/raumfeld.c                 |    3 +--
 arch/arm/mach-pxa/zylonite.c                 |    2 +-
 arch/arm/plat-pxa/include/plat/pxa3xx_nand.h |   23 +++++++++++++----------
 drivers/mtd/nand/pxa3xx_nand.c               |   11 +++++++----
 10 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
index 81ad58d..8d739d1 100644
--- a/arch/arm/mach-mmp/aspenite.c
+++ b/arch/arm/mach-mmp/aspenite.c
@@ -125,7 +125,8 @@ static struct mtd_partition aspenite_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data aspenite_nand_info = {
-	.enable_arbiter	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_NAKED_CMD_EN | PXA3XX_DMA_EN
+				| PXA3XX_ADV_TIME_TUNING | PXA3XX_TWO_CHIP_EN,
 	.parts[0]	= aspenite_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(aspenite_nand_partitions),
 };
diff --git a/arch/arm/mach-mmp/avengers_lite.c
b/arch/arm/mach-mmp/avengers_lite.c
index a828b1c..3a07613 100644
--- a/arch/arm/mach-mmp/avengers_lite.c
+++ b/arch/arm/mach-mmp/avengers_lite.c
@@ -77,7 +77,8 @@ static void __init avengers_init_flash(void)
 	avengers_nand_info.nr_parts[0] = ARRAY_SIZE(avengers_nand_partitions_0);
 	avengers_nand_info.parts[1] = avengers_nand_partitions_1;
 	avengers_nand_info.nr_parts[1] = ARRAY_SIZE(avengers_nand_partitions_1);
-	avengers_nand_info.enable_arbiter = 1;
+	avengers_nand_info.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_NAKED_CMD_EN
+		| PXA3XX_DMA_EN | PXA3XX_ADV_TIME_TUNING | PXA3XX_TWO_CHIP_EN;
 	pxa168_add_nand(&avengers_nand_info);
 }

diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index ce1f6d3..9f0282b 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -417,8 +417,7 @@ static struct mtd_partition cm_x300_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data cm_x300_nand_info = {
-	.enable_arbiter	= 1,
-	.keep_config	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_DMA_EN | PXA3XX_KEEP_CONFIG,
 	.parts[0]	= cm_x300_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(cm_x300_nand_partitions),
 };
diff --git a/arch/arm/mach-pxa/colibri-pxa3xx.c
b/arch/arm/mach-pxa/colibri-pxa3xx.c
index b33559c..627b289 100644
--- a/arch/arm/mach-pxa/colibri-pxa3xx.c
+++ b/arch/arm/mach-pxa/colibri-pxa3xx.c
@@ -186,8 +186,7 @@ static struct mtd_partition colibri_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data colibri_nand_info = {
-	.enable_arbiter	= 1,
-	.keep_config	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_DMA_EN | PXA3XX_KEEP_CONFIG,
 	.parts[0]	= colibri_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(colibri_nand_partitions),
 };
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 717cf92..e63451c 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -324,7 +324,7 @@ static struct mtd_partition littleton_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data littleton_nand_info = {
-	.enable_arbiter	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_DMA_EN,
 	.parts[0]	= littleton_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(littleton_nand_partitions),
 };
diff --git a/arch/arm/mach-pxa/mxm8x10.c b/arch/arm/mach-pxa/mxm8x10.c
index 66c2086..baca736 100644
--- a/arch/arm/mach-pxa/mxm8x10.c
+++ b/arch/arm/mach-pxa/mxm8x10.c
@@ -389,8 +389,7 @@ static struct mtd_partition mxm_8x10_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data mxm_8x10_nand_info = {
-	.enable_arbiter	= 1,
-	.keep_config	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_DMA_EN | PXA3XX_KEEP_CONFIG,
 	.parts[0]	= mxm_8x10_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(mxm_8x10_nand_partitions)
 };
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index df75d4d..8761775 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -348,8 +348,7 @@ static struct mtd_partition raumfeld_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data raumfeld_nand_info = {
-	.enable_arbiter	= 1,
-	.keep_config	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_DMA_EN | PXA3XX_KEEP_CONFIG,
 	.parts[0]	= raumfeld_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(raumfeld_nand_partitions),
 };
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 9e5c6cd..5cf3d10 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -355,7 +355,7 @@ static struct mtd_partition zylonite_nand_partitions[] = {
 };

 static struct pxa3xx_nand_platform_data zylonite_nand_info = {
-	.enable_arbiter	= 1,
+	.controller_attrs = PXA3XX_ARBI_EN | PXA3XX_DMA_EN,
 	.parts[0]	= zylonite_nand_partitions,
 	.nr_parts[0]	= ARRAY_SIZE(zylonite_nand_partitions),
 };
diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index 9b1f9df..ed7d623 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -49,17 +49,20 @@ struct pxa3xx_nand_flash {
 };

 #define NUM_CHIP_SELECT		(2)
+/* the data flash bus is shared between the Static Memory
+ * Controller and the Data Flash Controller,  the arbiter
+ * controls the ownership of the bus
+ */
+#define PXA3XX_ARBI_EN		(1)
+#define PXA3XX_NAKED_CMD_EN	(1 << 1)
+#define PXA3XX_TWO_CHIP_EN	(1 << 2)
+#define PXA3XX_DMA_EN		(1 << 3)
+/* for newer controller support more precise timing tuning, only
+ * enable such tuning for those platform which support it */
+#define PXA3XX_ADV_TIME_TUNING	(1 << 4)
+#define PXA3XX_KEEP_CONFIG	(1 << 5)
 struct pxa3xx_nand_platform_data {
-
-	/* the data flash bus is shared between the Static Memory
-	 * Controller and the Data Flash Controller,  the arbiter
-	 * controls the ownership of the bus
-	 */
-	int	enable_arbiter;
-
-	/* allow platform code to keep OBM/bootloader defined NFC config */
-	int	keep_config;
-
+	unsigned int				controller_attrs;
 	const struct mtd_partition		*parts[NUM_CHIP_SELECT];
 	unsigned int				nr_parts[NUM_CHIP_SELECT];

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 94df2bd..204c9d6 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -816,7 +816,7 @@ static int pxa3xx_nand_config_flash(struct
pxa3xx_nand_info *info,
 	else
 		info->row_addr_cycles = 2;

-	ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
+	ndcr |= (pdata->controller_attrs & PXA3XX_ARBI_EN) ? NDCR_ND_ARB_EN : 0;
 	ndcr |= (info->col_addr_cycles == 2) ? NDCR_RA_START : 0;
 	ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
 	ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
@@ -947,7 +947,7 @@ static int __devinit pxa3xx_nand_scan(struct mtd_info *mtd)
 	uint64_t chipsize;
 	int i, ret;

-	if (pdata->keep_config) {
+	if (pdata->controller_attrs & PXA3XX_KEEP_CONFIG) {
 		if (pxa3xx_nand_detect_config(nand) == 0)
 			goto KEEP_CONFIG;
 	}
@@ -1215,7 +1215,7 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 	struct mtd_info *mtd;
 	static const char *probes[] = { "cmdlinepart", NULL };
 	struct mtd_partition *parts;
-	int nr_parts, ret, cs, probe_success = 0;
+	int nr_parts, ret, cs, probe_success = 0, cs_to_scan;

 	pdata = pdev->dev.platform_data;
 	if (!pdata) {
@@ -1223,12 +1223,15 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 		return -ENODEV;
 	}

+	if (!(pdata->controller_attrs & PXA3XX_DMA_EN))
+		use_dma = 0;
 	ret = alloc_nand_resource(pdev);
 	if (ret)
 		return ret;

 	nand = platform_get_drvdata(pdev);
-	for (cs = 0; cs < NUM_CHIP_SELECT; cs++) {
+	cs_to_scan = (pdata->controller_attrs & PXA3XX_TWO_CHIP_EN)? 2 : 1;
+	for (cs = 0; cs < cs_to_scan; cs++) {
 		info = nand->info[cs];
 		mtd = get_mtd_by_info(info);
 		if (pxa3xx_nand_scan(mtd)) {
-- 
1.7.0.4


From leiwen at marvell.com  Thu Jun  3 03:46:50 2010
From: leiwen at marvell.com (Lei Wen)
Date: Thu, 3 Jun 2010 15:46:50 +0800
Subject: [PATCH 17/29] mmp: correct nand clock setting for pxa168 and pxa910
Message-ID: <mailman.134.1280296963.27306.linux-arm-kernel@lists.infradead.org>

There is no clock setting at 208Mhz for nand on pxa168 and pxa910
platform. Set correct register and lock the clock at
156MHZ.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 arch/arm/mach-mmp/pxa168.c |    2 +-
 arch/arm/mach-mmp/pxa910.c |    2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 652ae66..70d2231 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -78,7 +78,7 @@ static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
 static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
 static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);

-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19B, 156000000);

 /* device and clock bindings */
 static struct clk_lookup pxa168_clkregs[] = {
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 46f2d69..96f2b61 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -110,7 +110,7 @@ static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
 static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
 static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);

-static APMU_CLK(nand, NAND, 0x01db, 208000000);
+static APMU_CLK(nand, NAND, 0x19B, 156000000);

 /* device and clock bindings */
 static struct clk_lookup pxa910_clkregs[] = {
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 10:32:54 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 22:32:54 +0800
Subject: [PATCH 19/29] pxa3xx_nand: update ns2cycle calculation method
Message-ID: <mailman.135.1280296992.27306.linux-arm-kernel@lists.infradead.org>

For the original method change from plus 1 to minus 1,
this way make the default timing like tCS become 0 after calculation,
although we set the timing as 0xa...

Change the method to no plus and minus, and make the result
closer to what the timing specified in the NAND chip spec.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 45c9660..50f653b 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -279,7 +279,7 @@ static const char *mtd_names[] = {"pxa3xx_nand-0",
"pxa3xx_nand-1", NULL};
 #define NDTR1_tAR(c)	(min((c), 15) << 0)

 /* convert nano-seconds to nand flash controller clock cycles */
-#define ns2cycle(ns, clk)	(int)(((ns) * (clk / 1000000) / 1000) - 1)
+#define ns2cycle(ns, clk)	(int)((ns) * (clk / 1000000) / 1000)

 static void pxa3xx_nand_set_timing(struct pxa3xx_nand_info *info,
 				   const struct pxa3xx_nand_timing *t)
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 10:47:13 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 22:47:13 +0800
Subject: [PATCH 20/29] pxa3xx_nand: use the buff passed from upper
Message-ID: <mailman.136.1280297004.27306.linux-arm-kernel@lists.infradead.org>

layer if not use dma

For dma enabling case, we couldn't avoid the memcpy, for the buffer
in the upper layer may not be the physical consecutive.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  297 ++++++++++++++++++++++++----------------
 1 files changed, 181 insertions(+), 116 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 50f653b..048b576 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -158,6 +158,7 @@ struct pxa3xx_nand_info {
 	struct nand_chip	nand_chip;
 	struct pxa3xx_nand_cmdset *cmdset;
 	/* page size of attached chip */
+	int			page_addr;
 	uint16_t		page_size;
 	uint8_t			chip_select;
 	uint8_t			use_ecc;
@@ -186,8 +187,8 @@ struct pxa3xx_nand {
 	int			drcmr_dat;
 	int			drcmr_cmd;
 	int 			data_dma_ch;
-	dma_addr_t 		data_buff_phys;
-	dma_addr_t 		data_desc_addr;
+	dma_addr_t 		dma_buff_phys;
+	dma_addr_t 		dma_desc_addr;
 	struct pxa_dma_desc	*data_desc;

 	struct pxa3xx_nand_info *info[NUM_CHIP_SELECT];
@@ -496,25 +497,25 @@ static void start_data_dma(struct pxa3xx_nand
*nand, int dir_out)
 	desc_oob->ddadr = desc->ddadr = DDADR_STOP;
 	desc_oob->dcmd = desc->dcmd = DCMD_WIDTH4 | DCMD_BURST32;
 	if (dir_out) {
-		desc->dsadr = nand->data_buff_phys + nand->data_column;
+		desc->dsadr = nand->dma_buff_phys + nand->data_column;
 		desc->dtadr = nand->mmio_phys + NDDB;
 		desc->dcmd |= DCMD_ENDIRQEN | DCMD_INCSRCADDR | DCMD_FLOWTRG |
(data_len + oob_len);
 	} else {
 		if (nand->oob_size > 0) {
-			desc_oob->dtadr = nand->data_buff_phys
+			desc_oob->dtadr = nand->dma_buff_phys
 					+ info->page_size + nand->oob_column;
 			desc_oob->dcmd |= DCMD_ENDIRQEN | DCMD_INCTRGADDR | DCMD_FLOWSRC | oob_len;
-			desc->ddadr = nand->data_desc_addr + sizeof(struct pxa_dma_desc);
+			desc->ddadr = nand->dma_desc_addr + sizeof(struct pxa_dma_desc);
 			desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC | data_len;
 		}
 		else
 			desc->dcmd |= DCMD_ENDIRQEN | DCMD_INCTRGADDR | DCMD_FLOWSRC | data_len;
-		desc->dtadr = nand->data_buff_phys + nand->data_column;
+		desc->dtadr = nand->dma_buff_phys + nand->data_column;
 		desc_oob->dsadr = desc->dsadr = nand->mmio_phys + NDDB;
 	}

 	DRCMR(nand->drcmr_dat) = DRCMR_MAPVLD | nand->data_dma_ch;
-	DDADR(nand->data_dma_ch) = nand->data_desc_addr;
+	DDADR(nand->data_dma_ch) = nand->dma_desc_addr;
 	DCSR(nand->data_dma_ch) |= DCSR_RUN;
 }

@@ -638,6 +639,8 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 	int addr_cycle, exec_cmd, ndcb0, i, chunks = 0;
 	struct mtd_info *mtd;
 	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
+	struct platform_device *pdev = nand->pdev;
+	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;

 	mtd = get_mtd_by_info(info);
 	ndcb0 = (nand->chip_select) ? NDCB0_CSEL : 0;;
@@ -647,8 +650,6 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 	/* reset data and oob column point to handle data */
 	nand->data_column	= 0;
 	nand->oob_column	= 0;
-	nand->buf_start		= 0;
-	nand->buf_count		= 0;
 	nand->total_cmds	= 1;
 	nand->cmd_seqs		= 0;
 	nand->data_size		= 0;
@@ -658,26 +659,25 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 	nand->state		= 0;
 	nand->bad_count		= 0;
 	nand->retcode		= ERR_NONE;
-	nand->command		= command;
+	nand->buf_start		= column;

 	switch (command) {
-	case NAND_CMD_READ0:
 	case NAND_CMD_PAGEPROG:
-		nand->use_ecc = info->use_ecc;
-	case NAND_CMD_READOOB:
+	case NAND_CMD_RNDOUT:
 		pxa3xx_set_datasize(info);
-		nand->oob_buff = nand->data_buff + nand->data_size;
 		nand->use_dma = use_dma;
 		chunks = info->page_size / nand->data_size;
 		break;
-	case NAND_CMD_SEQIN:
-		exec_cmd = 0;
-		break;
 	default:
 		nand->ndcb1 = 0;
 		nand->ndcb2 = 0;
+		nand->use_ecc = ECC_NONE;
 		break;
 	}
+	if (nand->use_dma) {
+		nand->data_buff = nand->dma_buff;
+		nand->oob_buff = nand->dma_buff + mtd->writesize;
+	}

 	/* clear the command buffer */
 	for (i = 0; i < CMD_POOL_SIZE; i ++) {
@@ -688,68 +688,67 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 			+ info->col_addr_cycles);

 	switch (command) {
-	case NAND_CMD_READOOB:
 	case NAND_CMD_READ0:
-		cmd  = info->cmdset->read1;
-		if (command == NAND_CMD_READOOB)
-			nand->buf_start = mtd->writesize + column;
-		else
-			nand->buf_start = column;
-
-		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
-			nand->ndcb0[0] |= NDCB0_CMD_TYPE(0)
-					| addr_cycle
-					| (cmd & NDCB0_CMD1_MASK);
-		else {
-			if (chunks == 1)
-				nand->ndcb0[0] |= NDCB0_CMD_TYPE(0)
-						| NDCB0_DBC
-						| addr_cycle
-						| cmd;
-			else {
-				nand->total_cmds = chunks + 1;
-				nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x6)
-						| NDCB0_CMD_TYPE(0)
-						| NDCB0_DBC
-						| NDCB0_NC
-						| addr_cycle
-						| cmd;
-
-				nand->ndcb0[1] |= NDCB0_CMD_XTYPE(0x5)
-						| NDCB0_NC
-						| addr_cycle;
-
-				for (i = 2; i <= chunks; i ++)
-					nand->ndcb0[i] = nand->ndcb0[1];
-
-				nand->ndcb0[chunks] &= ~NDCB0_NC;
-				/* we should wait RnB go high again
-				 * before read out data*/
-				nand->wait_ready[1] = 1;
-			}
-		}
-
 	case NAND_CMD_SEQIN:
+		nand->use_ecc = info->use_ecc;
+	case NAND_CMD_READOOB:
+		memset(nand->data_buff, 0xff, column);
+		nand->buf_count = mtd->writesize + mtd->oobsize;
+		exec_cmd = 0;
+		info->page_addr = page_addr;
 		/* small page addr setting */
-		if (unlikely(info->page_size < PAGE_CHUNK_SIZE)) {
+		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
 			nand->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
 					| (column & 0xFF);
-
-			nand->ndcb2 = 0;
-		}
 		else {
 			nand->ndcb1 = ((page_addr & 0xFFFF) << 16)
 					| (column & 0xFFFF);

 			if (page_addr & 0xFF0000)
 				nand->ndcb2 = (page_addr & 0xFF0000) >> 16;
+		}
+		break;
+
+	case NAND_CMD_RNDOUT:
+		cmd = info->cmdset->read1;
+		if (nand->command == NAND_CMD_READOOB) {
+			nand->buf_start = mtd->writesize + column;
+			nand->buf_count = mtd->oobsize;
+		}
+
+		if (unlikely(info->page_size < PAGE_CHUNK_SIZE)
+			|| !(pdata->controller_attrs & PXA3XX_NAKED_CMD_EN)) {
+			if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
+				nand->ndcb0[0] |= NDCB0_CMD_TYPE(0)
+						| addr_cycle
+						| (cmd & NDCB0_CMD1_MASK);
 			else
-				nand->ndcb2 = 0;
+				nand->ndcb0[0] |= NDCB0_CMD_TYPE(0)
+						| NDCB0_DBC
+						| addr_cycle
+						| cmd;
+			break;
 		}

-		nand->buf_count = mtd->writesize + mtd->oobsize;
-		memset(nand->data_buff, 0xFF, nand->buf_count);
+		nand->total_cmds = chunks + 1;
+		nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x6)
+				| NDCB0_CMD_TYPE(0)
+				| NDCB0_DBC
+				| NDCB0_NC
+				| addr_cycle
+				| cmd;
+
+		nand->ndcb0[1] |= NDCB0_CMD_XTYPE(0x5)
+				| NDCB0_NC
+				| addr_cycle;
+
+		for (i = 2; i <= chunks; i ++)
+			nand->ndcb0[i] = nand->ndcb0[1];

+		nand->ndcb0[chunks] &= ~NDCB0_NC;
+		/* we should wait RnB go high again
+		 * before read out data*/
+		nand->wait_ready[1] = 1;
 		break;

 	case NAND_CMD_PAGEPROG:
@@ -760,40 +759,42 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,

 		cmd = info->cmdset->program;
 		nand->state |= STATE_IS_WRITE;
-		if (chunks == 1)
+		if (unlikely(info->page_size < PAGE_CHUNK_SIZE)
+			|| !(pdata->controller_attrs & PXA3XX_NAKED_CMD_EN)) {
 			nand->ndcb0[0] |= NDCB0_CMD_TYPE(0x1)
 					| NDCB0_AUTO_RS
 					| NDCB0_ST_ROW_EN
 					| NDCB0_DBC
 					| cmd
 					| addr_cycle;
-		else {
-			nand->total_cmds = chunks + 1;
-			nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x4)
-					| NDCB0_CMD_TYPE(0x1)
+			break;
+		}
+
+		nand->total_cmds = chunks + 1;
+		nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x4)
+				| NDCB0_CMD_TYPE(0x1)
+				| NDCB0_NC
+				| NDCB0_AUTO_RS
+				| (cmd & NDCB0_CMD1_MASK)
+				| addr_cycle;
+
+		for (i = 1; i < chunks; i ++)
+			nand->ndcb0[i] |= NDCB0_CMD_XTYPE(0x5)
 					| NDCB0_NC
 					| NDCB0_AUTO_RS
-					| (cmd & NDCB0_CMD1_MASK)
+					| NDCB0_CMD_TYPE(0x1)
 					| addr_cycle;

-			for (i = 1; i < chunks; i ++)
-				nand->ndcb0[i] |= NDCB0_CMD_XTYPE(0x5)
-						| NDCB0_NC
-						| NDCB0_AUTO_RS
-						| NDCB0_CMD_TYPE(0x1)
-						| addr_cycle;
-
-			nand->ndcb0[chunks] |= NDCB0_CMD_XTYPE(0x3)
-						| NDCB0_CMD_TYPE(0x1)
-						| NDCB0_ST_ROW_EN
-						| NDCB0_DBC
-						| (cmd & NDCB0_CMD2_MASK)
-						| NDCB0_CMD1_MASK
-						| addr_cycle;
-			/* we should wait for RnB goes high which
-			 * indicate the data has been written succesfully*/
-			nand->wait_ready[nand->total_cmds] = 1;
-		}
+		nand->ndcb0[chunks] |= NDCB0_CMD_XTYPE(0x3)
+				| NDCB0_CMD_TYPE(0x1)
+				| NDCB0_ST_ROW_EN
+				| NDCB0_DBC
+				| (cmd & NDCB0_CMD2_MASK)
+				| NDCB0_CMD1_MASK
+				| addr_cycle;
+		/* we should wait for RnB goes high which
+		 * indicate the data has been written succesfully*/
+		nand->wait_ready[nand->total_cmds] = 1;
 		break;

 	case NAND_CMD_READID:
@@ -807,6 +808,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 		break;
 	case NAND_CMD_STATUS:
 		cmd = info->cmdset->read_status;
+		nand->data_buff = nand->dma_buff;
 		nand->buf_count = 1;
 		nand->ndcb0[0] |= NDCB0_CMD_TYPE(4)
 				| NDCB0_ADDR_CYC(1)
@@ -843,6 +845,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 		break;
 	}

+	nand->command = command;
 	return exec_cmd;
 }

@@ -1076,44 +1079,104 @@ static void free_cs_resource(struct
pxa3xx_nand_info *info, int cs)
 	nand->info[cs] = NULL;
 }

-static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
-		struct nand_chip *chip, uint8_t *buf, int page)
+static void pxa3xx_read_page(struct mtd_info *mtd, uint8_t *buf)
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
+	struct nand_chip *chip = mtd->priv;
 	struct pxa3xx_nand *nand = info->nand_data;
+	int buf_blank;

-	chip->read_buf(mtd, buf, mtd->writesize);
-	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
-
-	if (nand->retcode == ERR_SBERR) {
+	nand->data_buff = buf;
+	nand->oob_buff = chip->oob_poi;
+	pxa3xx_nand_cmdfunc(mtd, NAND_CMD_RNDOUT, 0, info->page_addr);
+	switch (nand->retcode) {
+	case ERR_SBERR:
 		switch (nand->use_ecc) {
 		case ECC_BCH:
 			if (nand->bad_count > BCH_THRESHOLD)
 				mtd->ecc_stats.corrected +=
 					(nand->bad_count - BCH_THRESHOLD);
 			break;
+
 		case ECC_HAMMIN:
 			mtd->ecc_stats.corrected ++;
+			break;
+
 		case ECC_NONE:
 		default:
 			break;
 		}
-	} else if (nand->retcode == ERR_DBERR) {
-		int buf_blank;
-
-		buf_blank = is_buf_blank(buf, mtd->writesize);
+		break;
+	case ERR_DBERR:
+		buf_blank = is_buf_blank(nand->data_buff, mtd->writesize);
 		if (!buf_blank)
 			mtd->ecc_stats.failed++;
+		break;
+	case ERR_NONE:
+		break;
+	default:
+		mtd->ecc_stats.failed++;
+		break;
+	}
+}
+
+static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
+		struct nand_chip *chip, uint8_t *buf, int page)
+{
+	pxa3xx_read_page(mtd, buf);
+	if (use_dma) {
+		chip->read_buf(mtd, buf, mtd->writesize);
+		chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 	}
+	return 0;
+}

+static int pxa3xx_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
+		int page, int sndcmd)
+{
+	if (sndcmd) {
+		pxa3xx_nand_cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
+		pxa3xx_read_page(mtd, chip->oob_poi);
+	}
+	if (use_dma)
+		chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
 	return 0;
 }

 static void pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
 		struct nand_chip *chip, const uint8_t *buf)
 {
-	chip->write_buf(mtd, buf, mtd->writesize);
-	chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;
+	if (use_dma) {
+		chip->write_buf(mtd, buf, mtd->writesize);
+		chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+	}
+	else {
+		nand->data_buff = (uint8_t *)buf;
+		nand->oob_buff = chip->oob_poi;
+	}
+}
+
+static int pxa3xx_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
+			      int page)
+{
+	struct pxa3xx_nand_info *info = mtd->priv;
+	struct pxa3xx_nand *nand = info->nand_data;
+	int status = 0;
+
+	nand->data_buff = nand->dma_buff;
+	chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
+	if (use_dma)
+		chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
+	else
+		nand->oob_buff = chip->oob_poi;
+	/* Send command to program the OOB data */
+	chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
+
+	status = chip->waitfunc(mtd, chip);
+
+	return status & NAND_STATUS_FAIL ? -EIO : 0;
 }

 static void pxa3xx_nand_erase_cmd(struct mtd_info *mtd, int page)
@@ -1162,8 +1225,8 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 		return -EINVAL;
 	}

+	nand->data_buff = (unsigned char *)&id;
 	chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
-	id = *((uint16_t *)(nand->data_buff));
 	if (id != 0)
 		dev_info(&nand->pdev->dev, "Detect a flash id %x\n", id);
 	else {
@@ -1321,7 +1384,11 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		chip = (struct nand_chip *)(&mtd[1]);
 		chip->controller        = &nand->controller;
 		chip->ecc.read_page	= pxa3xx_nand_read_page_hwecc;
+		chip->ecc.read_page_raw = pxa3xx_nand_read_page_hwecc;
+		chip->ecc.read_oob      = pxa3xx_nand_read_oob;
 		chip->ecc.write_page	= pxa3xx_nand_write_page_hwecc;
+		chip->ecc.write_page_raw= pxa3xx_nand_write_page_hwecc;
+		chip->ecc.write_oob     = pxa3xx_nand_write_oob;
 		chip->waitfunc		= pxa3xx_nand_waitfunc;
 		chip->select_chip	= pxa3xx_nand_select_chip;
 		chip->cmdfunc		= pxa3xx_nand_cmdfunc;
@@ -1333,25 +1400,16 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		chip->erase_cmd		= pxa3xx_nand_erase_cmd;
 	}

-	if (use_dma == 0) {
-		nand->data_buff = kmalloc(MAX_BUFF_SIZE, GFP_KERNEL);
-		if (nand->data_buff == NULL) {
-			ret = -ENOMEM;
-			goto fail_free_buf;
-		}
-		goto success_exit;
-	}
-
-	nand->data_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
-			&nand->data_buff_phys, GFP_KERNEL);
-	if (nand->data_buff == NULL) {
+	nand->dma_buff = dma_alloc_coherent(&pdev->dev, MAX_BUFF_SIZE,
+			&nand->dma_buff_phys, GFP_KERNEL);
+	if (nand->dma_buff == NULL) {
 		dev_err(&pdev->dev, "failed to allocate dma buffer\n");
 		ret = -ENOMEM;
 		goto fail_free_buf;
 	}

-	nand->data_desc = (void *)nand->data_buff + data_desc_offset;
-	nand->data_desc_addr = nand->data_buff_phys + data_desc_offset;
+	nand->data_desc = (void *)nand->dma_buff + data_desc_offset;
+	nand->dma_desc_addr = nand->dma_buff_phys + data_desc_offset;
 	nand->data_dma_ch = pxa_request_dma("nand-data", DMA_PRIO_LOW,
 			pxa3xx_nand_data_dma_irq, nand);
 	if (nand->data_dma_ch < 0) {
@@ -1359,7 +1417,6 @@ static int alloc_nand_resource(struct
platform_device *pdev)
 		ret = -ENXIO;
 		goto fail_free_buf;
 	}
-success_exit:
 	return 0;

 fail_free_buf:
@@ -1409,6 +1466,14 @@ static int pxa3xx_nand_remove(struct
platform_device *pdev)
 		del_mtd_device(mtd);
 		free_cs_resource(info, cs);
 	}
+	if (nand->dma_buff_phys) {
+		if (nand->data_dma_ch >= 0)
+			pxa_free_dma(nand->data_dma_ch);
+		if (nand->dma_buff)
+			dma_free_coherent(&nand->pdev->dev, MAX_BUFF_SIZE,
+					nand->dma_buff, nand->dma_buff_phys);
+		nand->dma_buff_phys = 0;
+	}
 	return 0;
 }

-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 10:57:04 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 22:57:04 +0800
Subject: [PATCH 21/29] pxa3xx_nand: add ext id check
Message-ID: <mailman.137.1280297020.27306.linux-arm-kernel@lists.infradead.org>

For K9LBG08U0M and K9LBG08UXD two nand chip, they have the same chip id
as
0xd7ec. So we should use the ext id to distinguish them.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa3xx_nand.h |    3 +-
 drivers/mtd/nand/pxa3xx_nand.c               |   32 +++++++++++++-------------
 2 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index ed7d623..c20ac35 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -37,7 +37,8 @@ struct pxa3xx_nand_cmdset {

 struct pxa3xx_nand_flash {
 	char		*name;
-	uint32_t	chip_id;
+	uint16_t	chip_id;	/* chip id */
+	uint16_t	ext_id;		/* Extend id */
 	uint16_t	page_per_block; /* Pages per block */
 	uint16_t 	page_size;	/* Page size in bytes */
 	uint8_t		flash_width;	/* Width of Flash memory (DWIDTH_M) */
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 048b576..b0a0ccf 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -253,17 +253,17 @@ static struct pxa3xx_nand_timing __devinitdata
timing[] = {
 #define NAND_SETTING_MICRON      &default_cmdset, &timing[2]
 #define NAND_SETTING_ST          &default_cmdset, &timing[3]
 static struct pxa3xx_nand_flash __devinitdata builtin_flash_types[] = {
-{ "DEFAULT FLASH",      0,   0, 2048,  8,  8, ECC_NONE,      0,
NAND_SETTING_DEFAULT, },
-{ "64MiB 16-bit",  0x46ec,  32,  512, 16, 16, ECC_HAMMIN, 4096,
NAND_SETTING_SAMSUNG, },
-{ "256MiB 8-bit",  0xdaec,  64, 2048,  8,  8, ECC_HAMMIN, 2048,
NAND_SETTING_SAMSUNG, },
-{ "1GiB 8-bit",    0xd3ec, 128, 2048,  8,  8, ECC_BCH,    4096,
NAND_SETTING_SAMSUNG, },
-{ "4GiB 8-bit",    0xd7ec, 128, 4096,  8,  8, ECC_BCH,    8192,
NAND_SETTING_SAMSUNG, },
-{ "128MiB 8-bit",  0xa12c,  64, 2048,  8,  8, ECC_HAMMIN, 1024,
NAND_SETTING_MICRON, },
-{ "128MiB 16-bit", 0xb12c,  64, 2048, 16, 16, ECC_HAMMIN, 1024,
NAND_SETTING_MICRON, },
-{ "512MiB 8-bit",  0xdc2c,  64, 2048,  8,  8, ECC_HAMMIN, 4096,
NAND_SETTING_MICRON, },
-{ "512MiB 16-bit", 0xcc2c,  64, 2048, 16, 16, ECC_HAMMIN, 4096,
NAND_SETTING_MICRON, },
-{ "1GiB 8-bit",    0x382c, 128, 4096,  8,  8, ECC_BCH,    2048,
NAND_SETTING_MICRON },
-{ "256MiB 16-bit", 0xba20,  64, 2048, 16, 16, ECC_HAMMIN, 2048,
NAND_SETTING_ST, },
+{ "DEFAULT FLASH",      0,       0,  0, 2048,  8,  8, ECC_NONE,
0, NAND_SETTING_DEFAULT, },
+{ "64MiB 16-bit",  0x46ec, 0xffff,  32,  512, 16, 16, ECC_HAMMIN,
4096, NAND_SETTING_SAMSUNG, },
+{ "256MiB 8-bit",  0xdaec, 0xffff,  64, 2048,  8,  8, ECC_HAMMIN,
2048, NAND_SETTING_SAMSUNG, },
+{ "1GiB 8-bit",    0xd3ec, 0xffff, 128, 2048,  8,  8, ECC_BCH,
4096, NAND_SETTING_SAMSUNG, },
+{ "4GiB 8-bit",    0xd7ec, 0x29d5, 128, 4096,  8,  8, ECC_BCH,
8192, NAND_SETTING_SAMSUNG, },
+{ "128MiB 8-bit",  0xa12c, 0xffff,  64, 2048,  8,  8, ECC_HAMMIN,
1024, NAND_SETTING_MICRON, },
+{ "128MiB 16-bit", 0xb12c, 0xffff,  64, 2048, 16, 16, ECC_HAMMIN,
1024, NAND_SETTING_MICRON, },
+{ "512MiB 8-bit",  0xdc2c, 0xffff,  64, 2048,  8,  8, ECC_HAMMIN,
4096, NAND_SETTING_MICRON, },
+{ "512MiB 16-bit", 0xcc2c, 0xffff,  64, 2048, 16, 16, ECC_HAMMIN,
4096, NAND_SETTING_MICRON, },
+{ "1GiB 8-bit",    0x382c, 0xffff, 128, 4096,  8,  8, ECC_BCH,
2048, NAND_SETTING_MICRON },
+{ "256MiB 16-bit", 0xba20, 0xffff,  64, 2048, 16, 16, ECC_HAMMIN,
2048, NAND_SETTING_ST, },
 };

 static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};
@@ -1209,7 +1209,7 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 	struct nand_flash_dev pxa3xx_flash_ids[2] = {{NULL,}, {NULL,}};
 	const struct pxa3xx_nand_flash *f = NULL;
 	struct nand_chip *chip = mtd->priv;
-	uint32_t id = -1;
+	uint16_t id[2];
 	uint64_t chipsize;
 	int i, ret;

@@ -1225,10 +1225,10 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 		return -EINVAL;
 	}

-	nand->data_buff = (unsigned char *)&id;
+	nand->data_buff = (unsigned char *)id;
 	chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
-	if (id != 0)
-		dev_info(&nand->pdev->dev, "Detect a flash id %x\n", id);
+	if (id[0] != 0)
+		dev_info(&nand->pdev->dev, "Detect a flash id %x\n", id[0]);
 	else {
 		dev_warn(&nand->pdev->dev, "Read out ID 0, potential timing set wrong!!\n");
 		free_cs_resource(info, nand->chip_select);
@@ -1242,7 +1242,7 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)
 			f = &builtin_flash_types[i - pdata->num_flash + 1];

 		/* find the chip in default list */
-		if (f->chip_id == id)
+		if ((f->chip_id == id[0]) && ((f->ext_id & id[1]) == id[1]))
 			break;
 	}

-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 11:10:42 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 23:10:42 +0800
Subject: [PATCH 24/29] pxa3xx_nand: add polling mode support
Message-ID: <mailman.138.1280297033.27306.linux-arm-kernel@lists.infradead.org>

Add polling mode to facilitate debugging.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 arch/arm/plat-pxa/include/plat/pxa3xx_nand.h |    1 +
 drivers/mtd/nand/pxa3xx_nand.c               |   58 ++++++++++++++++++++------
 2 files changed, 46 insertions(+), 13 deletions(-)

diff --git a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
index f7c16d3..9e00267 100644
--- a/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
+++ b/arch/arm/plat-pxa/include/plat/pxa3xx_nand.h
@@ -64,6 +64,7 @@ struct pxa3xx_nand_flash {
  * enable such tuning for those platform which support it */
 #define PXA3XX_ADV_TIME_TUNING	(1 << 4)
 #define PXA3XX_KEEP_CONFIG	(1 << 5)
+#define PXA3XX_POOLING_MODE	(1 << 6)
 struct pxa3xx_nand_platform_data {
 	unsigned int				controller_attrs;
 	const struct mtd_partition		*parts[NUM_CHIP_SELECT];
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 9a37517..fbe455e 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -228,10 +228,9 @@ static int use_dma = 1;
 module_param(use_dma, bool, 0444);
 MODULE_PARM_DESC(use_dma, "enable DMA for data transfering to/from NAND HW");

-/*
- * Default NAND flash controller configuration setup by the
- * bootloader. This configuration is used only when pdata->keep_config is set
- */
+static int use_polling = 0;
+module_param(use_polling, bool, 0444);
+MODULE_PARM_DESC(use_polling, "Use full polling mode");
 static struct pxa3xx_nand_cmdset default_cmdset = {
 	.read1		= 0x3000,
 	.read2		= 0x0050,
@@ -403,6 +402,7 @@ static void pxa3xx_nand_start(struct pxa3xx_nand *nand)
 	info = nand->info[nand->chip_select];
 	ndcr = info->reg_ndcr;
 	ndcr |= nand->use_dma ? NDCR_DMA_EN : 0;
+	ndcr |= use_polling ? NDCR_INT_MASK : 0;
 	ndcr |= NDCR_ND_RUN;

 	switch (nand->ecc_strength) {
@@ -574,9 +574,8 @@ static void pxa3xx_nand_data_dma_irq(int channel,
void *data)
 	nand_writel(nand, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
 }

-static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
+static int pxa3xx_nand_transaction(struct pxa3xx_nand *nand)
 {
-	struct pxa3xx_nand *nand = devid;
 	struct pxa3xx_nand_info *info;
 	unsigned int status, is_completed = 0, cs, cmd_seqs, ndcb1, ndcb2;
 	unsigned int ready, cmd_done, page_done, badblock_detect;
@@ -613,13 +612,20 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 	if (status & ready) {
 		nand->state |= STATE_READY;
 		if (nand->wait_ready[cmd_seqs]) {
-			enable_int(nand, NDCR_WRCMDREQM);
+			if (!use_polling)
+				enable_int(nand, NDCR_WRCMDREQM | NDCR_CS0_CMDDM
+						| NDCR_CS1_CMDDM);
 			if (cmd_seqs == nand->total_cmds)
 				is_completed = 1;
 		}
 	}
 	if (status & cmd_done) {
 		nand->state |= STATE_CMD_DONE;
+		if (nand->wait_ready[cmd_seqs] && !(nand->state & STATE_READY)) {
+			status &= ~cmd_done;
+			if (!use_polling)
+				disable_int(nand, NDCR_CS0_CMDDM | NDCR_CS1_CMDDM);
+		}
 		if (cmd_seqs == nand->total_cmds && !nand->wait_ready[cmd_seqs])
 			is_completed = 1;
 	}
@@ -627,7 +633,8 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 	if (status & NDSR_WRCMDREQ) {
 		status &= ~NDSR_WRCMDREQ;
 		if (nand->wait_ready[cmd_seqs] && !(nand->state & STATE_READY)) {
-			disable_int(nand, NDCR_WRCMDREQM);
+			if (!use_polling)
+				disable_int(nand, NDCR_WRCMDREQM);
 			goto IRQ_FORCE_EXIT;
 		}

@@ -657,12 +664,32 @@ static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
 IRQ_FORCE_EXIT:
 	/* clear NDSR to let the controller exit the IRQ */
 	nand_writel(nand, NDSR, status);
-	if (is_completed)
-		complete(&nand->cmd_complete);
 NORMAL_IRQ_EXIT:
+	return is_completed;
+}
+
+static irqreturn_t pxa3xx_nand_irq(int irq, void *devid)
+{
+	struct pxa3xx_nand *nand = devid;
+	if (pxa3xx_nand_transaction(nand))
+		complete(&nand->cmd_complete);
 	return IRQ_HANDLED;
 }

+static int pxa3xx_nand_polling(struct pxa3xx_nand *nand, unsigned long timeout)
+{
+	int i, ret = 0;
+
+	for (i = 0; i < timeout; i++) {
+		ret = pxa3xx_nand_transaction(nand);
+		if (ret)
+			break;
+		udelay(10);
+	}
+
+	return ret;
+}
+
 static inline int is_buf_blank(uint8_t *buf, size_t len)
 {
 	for (; len > 0; len--)
@@ -930,8 +957,11 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 		nand->state |= STATE_CMD_PREPARED;
 		pxa3xx_nand_start(nand);

-		ret = wait_for_completion_timeout(&nand->cmd_complete,
-				CHIP_DELAY_TIMEOUT);
+		if (!use_polling)
+			ret = wait_for_completion_timeout(&nand->cmd_complete,
+					CHIP_DELAY_TIMEOUT);
+		else
+			ret = pxa3xx_nand_polling(nand, CHIP_DELAY_TIMEOUT);
 		if (!ret) {
 			dev_err(&nand->pdev->dev, "Wait time out!!!\n");
 			nand_error_dump(nand);
@@ -1551,7 +1581,9 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 		return -ENODEV;
 	}

-	if (!(pdata->controller_attrs & PXA3XX_DMA_EN))
+	if (pdata->controller_attrs & PXA3XX_POOLING_MODE)
+		use_polling = 1;
+	if (!(pdata->controller_attrs & PXA3XX_DMA_EN) || use_polling)
 		use_dma = 0;
 	ret = alloc_nand_resource(pdev);
 	if (ret)
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 09:20:47 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 21:20:47 +0800
Subject: [PATCH 08/29] pxa3xx_nand: discard wait_for_event, write_cmd,
Message-ID: <mailman.145.1280297090.27306.linux-arm-kernel@lists.infradead.org>

__readid function

Since we have rework the irq process, we don't need additional
delay in wait_for_event. Also write_cmd and __readid is also
discarded for the same reason.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |   77 +---------------------------------------
 1 files changed, 1 insertions(+), 76 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 0d97463..5dd03ea 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -259,25 +259,6 @@ static void pxa3xx_nand_set_timing(struct
pxa3xx_nand_info *info,
 	nand_writel(info, NDTR1CS0, ndtr1);
 }

-#define WAIT_EVENT_TIMEOUT	10
-
-static int wait_for_event(struct pxa3xx_nand_info *info, uint32_t event)
-{
-	int timeout = WAIT_EVENT_TIMEOUT;
-	uint32_t ndsr;
-
-	while (timeout--) {
-		ndsr = nand_readl(info, NDSR) & NDSR_MASK;
-		if (ndsr & event) {
-			nand_writel(info, NDSR, ndsr);
-			return 0;
-		}
-		udelay(10);
-	}
-
-	return -ETIMEDOUT;
-}
-
 static void pxa3xx_set_datasize(struct pxa3xx_nand_info *info)
 {
 	int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;
@@ -413,35 +394,6 @@ static void disable_int(struct pxa3xx_nand_info
*info, uint32_t int_mask)
 	nand_writel(info, NDCR, ndcr | int_mask);
 }

-/* NOTE: it is a must to set ND_RUN firstly, then write command buffer
- * otherwise, it does not work
- */
-static int write_cmd(struct pxa3xx_nand_info *info)
-{
-	uint32_t ndcr;
-
-	/* clear status bits and run */
-	nand_writel(info, NDSR, NDSR_MASK);
-
-	ndcr = info->reg_ndcr;
-
-	ndcr |= info->use_ecc ? NDCR_ECC_EN : 0;
-	ndcr |= info->use_dma ? NDCR_DMA_EN : 0;
-	ndcr |= NDCR_ND_RUN;
-
-	nand_writel(info, NDCR, ndcr);
-
-	if (wait_for_event(info, NDSR_WRCMDREQ)) {
-		printk(KERN_ERR "timed out writing command\n");
-		return -ETIMEDOUT;
-	}
-
-	nand_writel(info, NDCB0, info->ndcb0);
-	nand_writel(info, NDCB0, info->ndcb1);
-	nand_writel(info, NDCB0, info->ndcb2);
-	return 0;
-}
-
 static void handle_data_pio(struct pxa3xx_nand_info *info)
 {
 	if (info->state & STATE_IS_WRITE) {
@@ -778,33 +730,6 @@ static int pxa3xx_nand_ecc_correct(struct mtd_info *mtd,
 	return 0;
 }

-static int __readid(struct pxa3xx_nand_info *info, uint32_t *id)
-{
-	const struct pxa3xx_nand_cmdset *cmdset = info->cmdset;
-	uint32_t ndcr;
-	uint8_t  id_buff[8];
-
-	prepare_other_cmd(info, cmdset->read_id);
-
-	/* Send command */
-	if (write_cmd(info))
-		goto fail_timeout;
-
-	/* Wait for CMDDM(command done successfully) */
-	if (wait_for_event(info, NDSR_RDDREQ))
-		goto fail_timeout;
-
-	__raw_readsl(info->mmio_base + NDDB, id_buff, 2);
-	*id = id_buff[0] | (id_buff[1] << 8);
-	return 0;
-
-fail_timeout:
-	ndcr = nand_readl(info, NDCR);
-	nand_writel(info, NDCR, ndcr & ~NDCR_ND_RUN);
-	udelay(10);
-	return -ETIMEDOUT;
-}
-
 static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
 				    const struct pxa3xx_nand_flash *f)
 {
@@ -857,7 +782,7 @@ static int pxa3xx_nand_detect_config(struct
pxa3xx_nand_info *info)

 	page_per_block = ndcr & NDCR_PG_PER_BLK ? 64 : 32;
 	info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
-	/* set info fields needed to __readid */
+	/* set info fields needed to read id */
 	info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
 	info->reg_ndcr = ndcr;

-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 11:13:05 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 23:13:05 +0800
Subject: [PATCH 25/29] pxa3xx_nand: reimplement the read oob logic
Message-ID: <mailman.146.1280297104.27306.linux-arm-kernel@lists.infradead.org>

For readoob command only need the content of oob part, it certainly
don't need the controller transfer the data part, which greatly
downgrade the performance.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |  182 +++++++++++++++++++++-------------------
 1 files changed, 96 insertions(+), 86 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index fbe455e..ba15baf 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -198,30 +198,28 @@ struct pxa3xx_nand {
 	uint32_t		command;
 	uint16_t		data_size;	/* data size in FIFO */
 	uint16_t		oob_size;
-	uint32_t		bad_count;
 	unsigned char		*dma_buff;
 	unsigned char		*data_buff;
 	unsigned char		*oob_buff;
+	uint8_t			chip_select;
+	uint8_t			total_cmds;
 	uint32_t		buf_start;
 	uint32_t		buf_count;
+
+	uint32_t		state;
+	uint32_t		bad_count;
 	uint16_t		data_column;
 	uint16_t		oob_column;
-
-	/* relate to the command */
-	uint8_t			chip_select;
-	uint8_t			ecc_strength;
-	unsigned int		state;
 	int			use_dma;	/* use DMA ? */
 	int 			retcode;
+	uint8_t			ecc_strength;

 	/* cached register value */
 	uint8_t			cmd_seqs;
-	uint8_t			total_cmds;
 	uint8_t			wait_ready[CMD_POOL_SIZE];
 	uint32_t		ndcb0[CMD_POOL_SIZE];
-	uint32_t		ndcb1;
+	uint32_t		ndcb1[CMD_POOL_SIZE];
 	uint32_t		ndcb2;
-	uint32_t		ndcb3[CMD_POOL_SIZE];
 };

 static int use_dma = 1;
@@ -350,8 +348,8 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)
 	struct pxa3xx_nand *nand = info->nand_data;
 	int oob_enable = info->reg_ndcr & NDCR_SPARE_EN;

-	if (info->page_size >= PAGE_CHUNK_SIZE) {
-		nand->data_size = PAGE_CHUNK_SIZE;
+	if (info->page_size < PAGE_CHUNK_SIZE) {
+		nand->data_size = 512;
 		if (!oob_enable) {
 			nand->oob_size = 0;
 			return;
@@ -359,32 +357,54 @@ static void pxa3xx_set_datasize(struct
pxa3xx_nand_info *info)

 		switch (nand->ecc_strength) {
 		case 0:
-			nand->oob_size = 64;
+			nand->oob_size = 16;
 			break;
 		case HAMMING_STRENGTH:
-			nand->oob_size = 40;
+			nand->oob_size = 8;
 			break;
 		default:
-			nand->oob_size = 32;
-		}
-	} else {
-		nand->data_size = 512;
-		if (!oob_enable) {
-			nand->oob_size = 0;
-			return;
+			printk("Don't support BCH on small page device!!!\n");
+			BUG();
 		}
+		return;
+	}
+	nand->data_size = PAGE_CHUNK_SIZE;
+	if (!oob_enable) {
+		nand->oob_size = 0;
+		return;
+	}

-		switch (nand->ecc_strength) {
-		case 0:
-			nand->oob_size = 16;
-			break;
+	if (nand->command == NAND_CMD_READOOB) {
+		switch (info->ecc_strength) {
 		case HAMMING_STRENGTH:
-			nand->oob_size = 8;
+			nand->ndcb1[3] = 2 * PAGE_CHUNK_SIZE + OOB_CHUNK_SIZE;
+			nand->data_size = 40;
+			break;
+		case BCH_STRENGTH:
+			nand->ndcb1[3] = 2 * PAGE_CHUNK_SIZE + OOB_CHUNK_SIZE - 2;
+			nand->data_size = 32;
 			break;
 		default:
-			printk("Don't support BCH on small page device!!!\n");
 			BUG();
 		}
+		if (info->reg_ndcr & NDCR_DWIDTH_M) {
+			nand->ndcb1[1] = PAGE_CHUNK_SIZE / 2;
+			nand->ndcb1[3] /= 2;
+		}
+		else
+			nand->ndcb1[1] = PAGE_CHUNK_SIZE;
+		nand->oob_size = 0;
+		return;
+	}
+	switch (nand->ecc_strength) {
+	case 0:
+		nand->oob_size = 64;
+		break;
+	case HAMMING_STRENGTH:
+		nand->oob_size = 40;
+		break;
+	default:
+		nand->oob_size = 32;
 	}
 }

@@ -468,9 +488,8 @@ static void nand_error_dump(struct pxa3xx_nand *nand)
 	printk(KERN_ERR "Totally %d command for sending\n",
 			nand->total_cmds);
 	for (i = 0; i < nand->total_cmds; i ++)
-		printk(KERN_ERR "NDCB0:%d: %x\n",
-				i, nand->ndcb0[i]);
-	printk(KERN_ERR "NDCB1: %x; NDCB2 %x\n", nand->ndcb1, nand->ndcb2);
+		printk(KERN_ERR "%d::NDCB0: %x, NDCB1: %x, NDCB2: %x\n",
+			i, nand->ndcb0[i], nand->ndcb1[i], nand->ndcb2);

 	printk(KERN_ERR "\nRegister DUMPing ##############\n");
 	printk(KERN_ERR "NDCR %x\n"
@@ -577,8 +596,8 @@ static void pxa3xx_nand_data_dma_irq(int channel,
void *data)
 static int pxa3xx_nand_transaction(struct pxa3xx_nand *nand)
 {
 	struct pxa3xx_nand_info *info;
-	unsigned int status, is_completed = 0, cs, cmd_seqs, ndcb1, ndcb2;
-	unsigned int ready, cmd_done, page_done, badblock_detect;
+	unsigned int status, is_completed = 0, cs, cmd_seqs;
+	unsigned int ready, cmd_done, page_done, badblock_detect, ndcb2;

 	cs		= nand->chip_select;
 	ready           = (cs) ? NDSR_RDY : NDSR_FLASH_RDY;
@@ -640,22 +659,19 @@ static int pxa3xx_nand_transaction(struct
pxa3xx_nand *nand)

 		nand_writel(nand, NDSR, NDSR_WRCMDREQ);
 		if (cmd_seqs < nand->total_cmds) {
-			nand->cmd_seqs ++;
-			if (cmd_seqs == 0) {
-				ndcb1 = nand->ndcb1;
+			if (cmd_seqs == 0)
 				ndcb2 = nand->ndcb2;
-			}
-			else {
-				ndcb1 = 0;
+			else
 				ndcb2 = 0;
-			}
+			nand->cmd_seqs ++;
 			nand->state &= ~STATE_MASK;
 			nand->state |= STATE_CMD_WAIT_DONE;
 			nand_writel(nand, NDCB0, nand->ndcb0[cmd_seqs]);
-			nand_writel(nand, NDCB0, ndcb1);
+			nand_writel(nand, NDCB0, nand->ndcb1[cmd_seqs]);
 			nand_writel(nand, NDCB0, ndcb2);
-			if (nand->ndcb3[cmd_seqs])
-				nand_writel(nand, NDCB0, nand->ndcb3[cmd_seqs]);
+			if (nand->ndcb0[cmd_seqs] & NDCB0_LEN_OVRD)
+				nand_writel(nand, NDCB0, nand->data_size
+						+ nand->oob_size);
 		}
 		else
 			is_completed = 1;
@@ -714,24 +730,15 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 	exec_cmd = 1;

 	/* reset data and oob column point to handle data */
-	nand->data_column	= 0;
-	nand->oob_column	= 0;
-	nand->total_cmds	= 1;
-	nand->cmd_seqs		= 0;
-	nand->data_size		= 0;
-	nand->oob_size		= 0;
-	nand->use_dma		= 0;
-	nand->state		= 0;
-	nand->bad_count		= 0;
-	nand->retcode		= ERR_NONE;
-	nand->buf_start		= column;
+	nand->total_cmds = 1;
+	nand->buf_start	= column;

 	switch (command) {
 	case NAND_CMD_PAGEPROG:
 	case NAND_CMD_RNDOUT:
 		pxa3xx_set_datasize(info);
 		nand->use_dma = use_dma;
-		chunks = info->page_size / nand->data_size;
+		chunks = info->page_size / PAGE_CHUNK_SIZE;
 		if (info->ecc_strength > BCH_STRENGTH) {
 			i = info->ecc_strength / BCH_STRENGTH;
 			nand->data_size /= i;
@@ -746,9 +753,8 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 			BUG();
 		}
 	default:
-		nand->ndcb1 = 0;
-		nand->ndcb2 = 0;
-		nand->ecc_strength = 0;
+		i = (uint32_t)(&nand->state) - (uint32_t)nand;
+		memset(&nand->state, 0, sizeof(struct pxa3xx_nand) - i);
 		break;
 	}
 	if (nand->use_dma) {
@@ -757,11 +763,8 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 	}

 	/* clear the command buffer */
-	for (i = 0; i < CMD_POOL_SIZE; i ++) {
+	for (i = 0; i < CMD_POOL_SIZE; i ++)
 		nand->ndcb0[i] = ndcb0;
-		nand->wait_ready[i] = 0;
-		nand->ndcb3[i] = (ndcb0 & NDCB0_LEN_OVRD)? nand->data_size : 0;
-	}
 	addr_cycle = NDCB0_ADDR_CYC(info->row_addr_cycles
 			+ info->col_addr_cycles);

@@ -776,10 +779,10 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 		info->page_addr = page_addr;
 		/* small page addr setting */
 		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
-			nand->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
+			nand->ndcb1[0] = ((page_addr & 0xFFFFFF) << 8)
 					| (column & 0xFF);
 		else {
-			nand->ndcb1 = ((page_addr & 0xFFFF) << 16)
+			nand->ndcb1[0] = ((page_addr & 0xFFFF) << 16)
 					| (column & 0xFFFF);

 			if (page_addr & 0xFF0000)
@@ -789,11 +792,6 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,

 	case NAND_CMD_RNDOUT:
 		cmd = info->cmdset->read1;
-		if (nand->command == NAND_CMD_READOOB) {
-			nand->buf_start = mtd->writesize + column;
-			nand->buf_count = mtd->oobsize;
-		}
-
 		if (unlikely(info->page_size < PAGE_CHUNK_SIZE)
 			|| !(pdata->controller_attrs & PXA3XX_NAKED_CMD_EN)) {
 			if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
@@ -805,10 +803,18 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 						| NDCB0_DBC
 						| addr_cycle
 						| cmd;
+			if (nand->command == NAND_CMD_READOOB) {
+				nand->buf_start = mtd->writesize + column;
+				nand->buf_count = mtd->oobsize;
+			}
 			break;
 		}

-		nand->total_cmds = chunks + 1;
+		if (nand->command == NAND_CMD_READOOB)
+			nand->total_cmds = 2 * chunks + 1;
+		else
+			nand->total_cmds = chunks + 1;
+
 		nand->ndcb0[0] |= NDCB0_CMD_XTYPE(0x6)
 				| NDCB0_CMD_TYPE(0)
 				| NDCB0_DBC
@@ -816,15 +822,23 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 				| addr_cycle
 				| cmd;
 		nand->ndcb0[0] &= ~NDCB0_LEN_OVRD;
-		nand->ndcb3[0] = 0;
-		nand->ndcb0[1] |= NDCB0_CMD_XTYPE(0x5)
-				| NDCB0_NC
-				| addr_cycle;

-		for (i = 2; i <= chunks; i ++)
-			nand->ndcb0[i] = nand->ndcb0[1];
+		for (i = 1; i <= nand->total_cmds - 1;) {
+			if (nand->command == NAND_CMD_READOOB) {
+				nand->ndcb0[i ++] |= NDCB0_CMD_XTYPE(0x6)
+						| NDCB0_CMD_TYPE(0)
+						| NDCB0_ADDR_CYC(info->col_addr_cycles)
+						| NDCB0_DBC
+						| NDCB0_NC
+						| (NAND_CMD_RNDOUTSTART << 8)
+						| NAND_CMD_RNDOUT;
+				nand->ndcb0[i] |= NDCB0_LEN_OVRD;
+			}
+			nand->ndcb0[i ++] |= NDCB0_CMD_XTYPE(0x5)
+					| NDCB0_NC;
+		}

-		nand->ndcb0[chunks] &= ~NDCB0_NC;
+		nand->ndcb0[nand->total_cmds - 1] &= ~NDCB0_NC;
 		/* we should wait RnB go high again
 		 * before read out data*/
 		nand->wait_ready[1] = 1;
@@ -861,18 +875,15 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 			nand->ndcb0[i] |= NDCB0_CMD_XTYPE(0x5)
 					| NDCB0_NC
 					| NDCB0_AUTO_RS
-					| NDCB0_CMD_TYPE(0x1)
-					| addr_cycle;
+					| NDCB0_CMD_TYPE(0x1);

 		nand->ndcb0[chunks] |= NDCB0_CMD_XTYPE(0x3)
-				| NDCB0_CMD_TYPE(0x1)
-				| NDCB0_ST_ROW_EN
-				| NDCB0_DBC
-				| (cmd & NDCB0_CMD2_MASK)
-				| NDCB0_CMD1_MASK
-				| addr_cycle;
+					| NDCB0_CMD_TYPE(0x1)
+					| NDCB0_ST_ROW_EN
+					| NDCB0_DBC
+					| (cmd & NDCB0_CMD2_MASK)
+					| NDCB0_CMD1_MASK;
 		nand->ndcb0[chunks] &= ~NDCB0_LEN_OVRD;
-		nand->ndcb3[chunks] = 0;
 		/* we should wait for RnB goes high which
 		 * indicate the data has been written succesfully*/
 		nand->wait_ready[nand->total_cmds] = 1;
@@ -905,8 +916,7 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 				| NDCB0_ADDR_CYC(3)
 				| NDCB0_DBC
 				| cmd;
-		nand->ndcb1 = page_addr;
-		nand->ndcb2 = 0;
+		nand->ndcb1[0] = page_addr;

 		break;
 	case NAND_CMD_RESET:
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 11:14:21 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 23:14:21 +0800
Subject: [PATCH 26/29] pxa3xx_nand: fix reset timeout on mmp2
Message-ID: <mailman.147.1280297119.27306.linux-arm-kernel@lists.infradead.org>

For mmp2 board, reset command would always have timeout when enable
the IRQ processing. The command done would comes after exit the IRQ
processing whatever the timeout value is set.

Change reset command use polling mode fix the issue.

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index ba15baf..cad97df 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -920,6 +920,10 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,

 		break;
 	case NAND_CMD_RESET:
+		/* on some platform, it is stranger that when issue reset command,
+		 * cmd done would not come till timeout cause irq exit.
+		 * Force polling mode for reset command*/
+		use_polling = 1;
 		cmd = info->cmdset->reset;
 		nand->ndcb0[0] |= NDCB0_CMD_TYPE(5)
 				| cmd;
@@ -945,7 +949,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 {
 	struct pxa3xx_nand_info *info = mtd->priv;
 	struct pxa3xx_nand *nand = info->nand_data;
-	int ret, exec_cmd;
+	int ret, exec_cmd, polling_mode;

 	/* if this is a x16 device ,then convert the input
 	 * "byte" address into a "word" address appropriate
@@ -961,6 +965,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 		nand_writel(nand, NDTR1CS0, info->ndtr1cs0);
 	}

+	polling_mode = use_polling;
 	exec_cmd = prepare_command_pool(nand, command, column, page_addr);
 	if (exec_cmd) {
 		init_completion(&nand->cmd_complete);
@@ -980,6 +985,7 @@ static void pxa3xx_nand_cmdfunc(struct mtd_info
*mtd, unsigned command,
 		}
 		nand->state &= ~STATE_CMD_PREPARED;
 	}
+	use_polling = polling_mode;
 }

 static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 11:16:58 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 23:16:58 +0800
Subject: [PATCH 27/29] pxa3xx_nand: fix write oob bug
Message-ID: <mailman.148.1280297133.27306.linux-arm-kernel@lists.infradead.org>

For column addressing is only used to subpage and oob operation,
and the fact that our controller is performing poor at such two
operations, disable the column addressing in writing the ndcb1.

If not add this patch, write_oob function would fail.

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |   42 +++++++++++++++++++++++++++++++--------
 1 files changed, 33 insertions(+), 9 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index cad97df..65cf54c 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -267,6 +267,20 @@ static struct pxa3xx_nand_flash __devinitdata
builtin_flash_types[] = {
 { "256MiB 16-bit", 0xba20, 0xffff,  64, 2048, 16, 16, 1, 2048,
NAND_SETTING_ST, },
 };

+static struct nand_ecclayout nand_oob_128_BCH = {
+	.eccbytes = 64,
+	.eccpos = {
+		64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75,
+		76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87,
+		88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99,
+		100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
+		110, 111, 112, 113, 114, 115, 116, 117, 118, 119,
+		120, 121, 122, 123, 124, 125, 126, 127},
+	.oobfree = {
+		{.offset = 2,
+		.length = 62}}
+};
+
 static const char *mtd_names[] = {"pxa3xx_nand-0", "pxa3xx_nand-1", NULL};

 #define NDTR0_tADL(c)		(min_t(uint32_t, (c), 31) << 27)
@@ -553,13 +567,19 @@ static void start_data_dma(struct pxa3xx_nand
*nand, int dir_out)
 	desc_oob->ddadr = desc->ddadr = DDADR_STOP;
 	desc_oob->dcmd = desc->dcmd = DCMD_WIDTH4 | DCMD_BURST32;
 	if (dir_out) {
+		if (nand->oob_size > 0) {
+			desc_oob->dsadr = nand->dma_buff_phys + info->page_size + nand->oob_column;
+			desc_oob->dcmd |= DCMD_ENDIRQEN | DCMD_INCSRCADDR | DCMD_FLOWTRG | oob_len;
+			desc->ddadr = nand->dma_desc_addr + sizeof(struct pxa_dma_desc);
+			desc->dcmd |= DCMD_INCSRCADDR | DCMD_FLOWTRG | data_len;
+		}
+		else
+			desc->dcmd |= DCMD_ENDIRQEN | DCMD_INCSRCADDR | DCMD_FLOWTRG | data_len;
 		desc->dsadr = nand->dma_buff_phys + nand->data_column;
-		desc->dtadr = nand->mmio_phys + NDDB;
-		desc->dcmd |= DCMD_ENDIRQEN | DCMD_INCSRCADDR | DCMD_FLOWTRG |
(data_len + oob_len);
+		desc_oob->dtadr = desc->dtadr = nand->mmio_phys + NDDB;
 	} else {
 		if (nand->oob_size > 0) {
-			desc_oob->dtadr = nand->dma_buff_phys
-					+ info->page_size + nand->oob_column;
+			desc_oob->dtadr = nand->dma_buff_phys + info->page_size + nand->oob_column;
 			desc_oob->dcmd |= DCMD_ENDIRQEN | DCMD_INCTRGADDR | DCMD_FLOWSRC | oob_len;
 			desc->ddadr = nand->dma_desc_addr + sizeof(struct pxa_dma_desc);
 			desc->dcmd |= DCMD_INCTRGADDR | DCMD_FLOWSRC | data_len;
@@ -720,11 +740,13 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 	uint16_t cmd;
 	int addr_cycle, exec_cmd, ndcb0, i, chunks = 0;
 	struct mtd_info *mtd;
+	struct nand_chip *chip;
 	struct pxa3xx_nand_info *info = nand->info[nand->chip_select];
 	struct platform_device *pdev = nand->pdev;
 	struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;

 	mtd = get_mtd_by_info(info);
+	chip = mtd->priv;
 	ndcb0 = (nand->chip_select) ? NDCB0_CSEL : 0;;
 	addr_cycle = 0;
 	exec_cmd = 1;
@@ -779,11 +801,9 @@ static int prepare_command_pool(struct
pxa3xx_nand *nand, int command,
 		info->page_addr = page_addr;
 		/* small page addr setting */
 		if (unlikely(info->page_size < PAGE_CHUNK_SIZE))
-			nand->ndcb1[0] = ((page_addr & 0xFFFFFF) << 8)
-					| (column & 0xFF);
+			nand->ndcb1[0] = ((page_addr & 0xFFFFFF) << 8);
 		else {
-			nand->ndcb1[0] = ((page_addr & 0xFFFF) << 16)
-					| (column & 0xFFFF);
+			nand->ndcb1[0] = ((page_addr & 0xFFFF) << 16);

 			if (page_addr & 0xFF0000)
 				nand->ndcb2 = (page_addr & 0xFF0000) >> 16;
@@ -845,7 +865,9 @@ static int prepare_command_pool(struct pxa3xx_nand
*nand, int command,
 		break;

 	case NAND_CMD_PAGEPROG:
-		if (is_buf_blank(nand->data_buff, (mtd->writesize + mtd->oobsize))) {
+		if (is_buf_blank(nand->data_buff, mtd->writesize) &&
+		    is_buf_blank(nand->oob_buff + chip->ecc.layout->oobfree[0].offset,
+			    chip->ecc.layout->oobfree[0].length)) {
 			exec_cmd = 0;
 			break;
 		}
@@ -1358,6 +1380,8 @@ static int __devinit pxa3xx_nand_scan(struct
mtd_info *mtd)

 	if (pxa3xx_nand_config_flash(info, f))
 		return -EINVAL;
+	if (f->page_size == 4096 && f->ecc_strength == 4)
+		chip->ecc.layout = &nand_oob_128_BCH;
 	pxa3xx_flash_ids[0].name = f->name;
 	pxa3xx_flash_ids[0].id = (f->chip_id >> 8) & 0xffff;
 	pxa3xx_flash_ids[0].pagesize = f->page_size;
-- 
1.7.0.4


From leiwen at marvell.com  Tue Jun 22 11:17:36 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 23:17:36 +0800
Subject: [PATCH 28/29] pxa3xx_nand: fix power management support
Message-ID: <mailman.149.1280297145.27306.linux-arm-kernel@lists.infradead.org>

Signed-off-by: Lei Wen <leiwen at marvell.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |   48 +++++++++++++++++++++++++++++++--------
 1 files changed, 38 insertions(+), 10 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 65cf54c..bc2f56d 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1659,26 +1659,54 @@ static int __devinit pxa3xx_nand_probe(struct
platform_device *pdev)
 #ifdef CONFIG_PM
 static int pxa3xx_nand_suspend(struct platform_device *pdev,
pm_message_t state)
 {
-	struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
-	struct mtd_info *mtd = info->mtd;
+	struct pxa3xx_nand *nand= platform_get_drvdata(pdev);
+	struct pxa3xx_nand_info *info;
+	struct mtd_info *mtd;
+	int ret = 0;
+	uint8_t cs;

-	if (info->state & STATE_CMD_PREPARED) {
-		dev_err(&pdev->dev, "driver busy, state = %d\n", info->state);
+	if (nand->state & STATE_CMD_PREPARED) {
+		dev_err(&pdev->dev, "driver busy, state = %d\n", nand->state);
 		return -EAGAIN;
 	}

-	return 0;
+	for (cs = 0; cs < NUM_CHIP_SELECT; cs ++) {
+		info = nand->info[cs];
+		if (!info)
+			continue;
+		mtd = get_mtd_by_info(info);
+		ret = mtd->suspend(mtd);
+	}
+
+	return ret;
 }

 static int pxa3xx_nand_resume(struct platform_device *pdev)
 {
-	struct pxa3xx_nand_info *info = platform_get_drvdata(pdev);
-	struct mtd_info *mtd = info->mtd;
+	struct pxa3xx_nand *nand= platform_get_drvdata(pdev);
+	struct pxa3xx_nand_info *info;
+	struct mtd_info *mtd;
+	uint8_t cs;

-	nand_writel(info, NDTR0CS0, info->ndtr0cs0);
-	nand_writel(info, NDTR1CS0, info->ndtr1cs0);
-	clk_enable(info->clk);
+	for (cs = 0; cs < NUM_CHIP_SELECT; cs ++) {
+		info = nand->info[cs];
+		if (!info)
+			continue;
+		nand_writel(nand, NDTR0CS0, info->ndtr0cs0);
+		nand_writel(nand, NDTR1CS0, info->ndtr1cs0);
+		nand->chip_select = cs;
+		/* Sometimes nand chip would raise a ready interrupt
+		 * when resume, reset the by start and stop to prevent
+		 * it damage driver's state machine */
+		pxa3xx_nand_start(nand);
+		pxa3xx_nand_stop(nand);
+		mtd = get_mtd_by_info(info);
+		mtd->resume(mtd);
+	}

+	/* set the controller cs to a invalid num to let driver
+	 * reconfigure the timing when it call the cmdfunc */
+	nand->chip_select = 0xff;
 	return 0;
 }
 #else
-- 
1.7.0.4


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.151.1280365110.27306.linux-arm-kernel@lists.infradead.org>

AMD/Intel to allow the kvm code to work with a common IOMMU interface. To
that end, it isn't really a generic IOMMU interface. We have chosen to use
our own interface because it provides us with a lightweight way of
managing mappings for more esoteric MSM-specific use cases.

These map functions also take into account the way in which we map buffers
that we get from our own physical pool, because the current API was not
intended to deal with prioritized allocation of things like on/off-chip
memory. We are currently evaluating how to use the DMA API with our own
specialized allocator, which has been undergoing some discussion on the
other lists. We would like to use this allocator to maximize TLB
performance, as well as to prioritize the allocation from several
different memory pools.

Steve



From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.153.1280740994.27306.linux-arm-kernel@lists.infradead.org>

additional IRQs to that.  That's quite small compared to some platforms
which have in the order of 512 or even 1024 IRQs.

> And current kernel don't support the sparse irq feature. then it's
> reasonable to merge it first and revise it later.

sparse irq support has been queued for almost a month for the merge
window which has just this morning opened.  This doesn't help you if
you instantiate all your 360 interrupts though - just because you
don't _use_ an interrupt which has been declared as existing doesn't
reduce the size of the arrays.

> Another why FIMC support is missing? we modified it as his requested
> and send it properly.
> [PATCH v3 3/8] ARM: Samsung: Add platform definitions and helpers for
> http://marc.info/?l=linux-arm-kernel&m=127990218813931&w=2

This looks like it's been missed.  People get busy and miss things on
the mailing list, there's nothing special about that.

> [PATCH v3 1/8] ARM: Samsung: Add register definitions for Samsung S5P
> http://marc.info/?l=linux-arm-kernel&m=127990218613922&w=2

Kukjin Kim replied to this one with a point requiring an answer, but
nothing came back.

   "Looks ok...however, I'm still thinking whether really need all these
    definitions."

Seems to be a perfectly reasonable point to raise, and if there's no
reply to justify them...


From rabin.vincent at stericsson.com  Wed Jun 16 06:28:59 2010
From: rabin.vincent at stericsson.com (Rabin Vincent)
Date: Wed, 16 Jun 2010 15:58:59 +0530
Subject: [PATCH] mmci: allow the card detect GPIO value not to be inverted
Message-ID: <mailman.165.1281350283.27306.linux-arm-kernel@lists.infradead.org>

On some platforms, the GPIO value from the gpio_cd pin doesn't need to
be inverted to get it active high.  Add a cd_invert platform data
parameter and change existing platforms using GPIO for CD (only
Realview) to enable it.

Acked-by: Linus Walleij <linus.walleij at stericsson.com>
Signed-off-by: Rabin Vincent <rabin.vincent at stericsson.com>
---
 arch/arm/mach-realview/core.c |    2 ++
 drivers/mmc/host/mmci.c       |    5 +++--
 include/linux/amba/mmci.h     |    2 ++
 3 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 2fa38df..07c0815 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -259,6 +259,7 @@ struct mmci_platform_data realview_mmc0_plat_data = {
 	.status		= realview_mmc_status,
 	.gpio_wp	= 17,
 	.gpio_cd	= 16,
+	.cd_invert	= true,
 };
 
 struct mmci_platform_data realview_mmc1_plat_data = {
@@ -266,6 +267,7 @@ struct mmci_platform_data realview_mmc1_plat_data = {
 	.status		= realview_mmc_status,
 	.gpio_wp	= 19,
 	.gpio_cd	= 18,
+	.cd_invert	= true,
 };
 
 /*
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 840b301..9a9aeac 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -570,12 +570,13 @@ static int mmci_get_ro(struct mmc_host *mmc)
 static int mmci_get_cd(struct mmc_host *mmc)
 {
 	struct mmci_host *host = mmc_priv(mmc);
+	struct mmci_platform_data *plat = host->plat;
 	unsigned int status;
 
 	if (host->gpio_cd == -ENOSYS)
-		status = host->plat->status(mmc_dev(host->mmc));
+		status = plat->status(mmc_dev(host->mmc));
 	else
-		status = !gpio_get_value(host->gpio_cd);
+		status = !!gpio_get_value(host->gpio_cd) ^ plat->cd_invert;
 
 	/*
 	 * Use positive logic throughout - status is zero for no card,
diff --git a/include/linux/amba/mmci.h b/include/linux/amba/mmci.h
index ca84ce7..f4ee9ac 100644
--- a/include/linux/amba/mmci.h
+++ b/include/linux/amba/mmci.h
@@ -24,6 +24,7 @@
  * whether a card is present in the MMC slot or not
  * @gpio_wp: read this GPIO pin to see if the card is write protected
  * @gpio_cd: read this GPIO pin to detect card insertion
+ * @cd_invert: true if the gpio_cd pin value is active low
  * @capabilities: the capabilities of the block as implemented in
  * this platform, signify anything MMC_CAP_* from mmc/host.h
  */
@@ -35,6 +36,7 @@ struct mmci_platform_data {
 	unsigned int (*status)(struct device *);
 	int	gpio_wp;
 	int	gpio_cd;
+	bool	cd_invert;
 	unsigned long capabilities;
 };
 
-- 
1.7.2.dirty



From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.166.1281687448.27306.linux-arm-kernel@lists.infradead.org>

bootloader issue, isn't it.

I don't know exactly what "internal boot mode" means, but assuming the
ROM code doesn't make any output to UART1 at least this clock smells
like a bootloader problem.  If you're conviced this is a chip problem,
did you consider to contact FSL about it?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.178.1281999291.27306.linux-arm-kernel@lists.infradead.org>

#define CHECK(e,l,h) (var->e < l || var->e > h)
	if (CHECK(right_margin, (5+1), 256) ||	/* back porch */
	    CHECK(left_margin, (5+1), 256) ||	/* front porch */
	    CHECK(hsync_len, (5+1), 256) ||
	    var->xres > 4096 ||

These 4 checks don't match the actual values that can be
generated by the CLCD controller. The minimum values for left
and right horizontal porch and HSYNC width can go down to
1 clock.

The maximum x resolution for the pl11x devices is 1024 pixels.

I know this function can be overridden for platforms using the
clcd driver, but does anyone have any problem making this
function match the hardware?

thanks,
Kevin


From leiwen at marvell.com  Tue Jun 22 08:19:35 2010
From: leiwen at marvell.com (Lei Wen)
Date: Tue, 22 Jun 2010 20:19:35 +0800
Subject: [PATCH 03/06] pxa3xx_nand: fix compile warning
Message-ID: <mailman.186.1282048196.27306.linux-arm-kernel@lists.infradead.org>

The compile output as below:
WARNING: modpost: Found 1 section mismatch(es).

Signed-off-by: Lei Wen <leiwen at marvell.com>
---
 drivers/mtd/nand/pxa3xx_nand.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 02a4466..e3061bc 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1066,7 +1066,7 @@ static void pxa3xx_nand_init_mtd(struct mtd_info *mtd,
 	this->chip_delay = 25;
 }

-static int pxa3xx_nand_probe(struct platform_device *pdev)
+static int __devinit pxa3xx_nand_probe(struct platform_device *pdev)
 {
 	struct pxa3xx_nand_platform_data *pdata;
 	struct pxa3xx_nand_info *info;
-- 
1.7.0.4

--000e0ce043362ad62d048e041b32
Content-Type: text/x-patch; charset=US-ASCII; 
	name="0003-pxa3xx_nand-fix-compile-warning.patch"
Content-Disposition: attachment; 
	filename="0003-pxa3xx_nand-fix-compile-warning.patch"
Content-Transfer-Encoding: base64
X-Attachment-Id: f_gcyq3hvh0


bmZvOwotLSAKMS43LjAuNAoK
--000e0ce043362ad62d048e041b32--


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.210.1282609719.27306.linux-arm-kernel@lists.infradead.org>

drivers/usb/core/hub.c.

Any ideas?

Regards,
Hartley=


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.228.1283456688.27306.linux-arm-kernel@lists.infradead.org>

> + =A0 =A0 =A0 struct clk *clk0;
> +
> + =A0 =A0 =A0 clk0 =3D clk_get_sys("mtu0", NULL);
> +
> + =A0 =A0 =A0 clk_enable(clk0);
> +
> +       if (clk_get_rate(clk0) > (16 << 20))
> +               cr |=3D MTU_CRn_PRESCALE_16;
> +       else
> +               cr |=3D MTU_CRn_PRESCALE_1;

To here can be removed actually.

We happen to know that this rate is not changing on the
MTU using systems.

And since we know the rate is not going to change...

Just save the rate and prescaler setting in a static local variable
and remove the other clock lookup and divisions.
(You still need to have a struct clk* pointer around for
enable/disable too.)

> (...)
> =A0void __init nmdk_timer_init(void)
> =A0{
> =A0 =A0 =A0 =A0unsigned long rate;
> =A0 =A0 =A0 =A0struct clk *clk0;
> - =A0 =A0 =A0 u32 cr;
>
> + =A0 =A0 =A0 /*
> + =A0 =A0 =A0 =A0* On MTU block 0: timer0 is used as source,
> + =A0 =A0 =A0 =A0* timer1 is used for events.
> + =A0 =A0 =A0 =A0*/
> =A0 =A0 =A0 =A0clk0 =3D clk_get_sys("mtu0", NULL);
> =A0 =A0 =A0 =A0BUG_ON(IS_ERR(clk0));
>
> - =A0 =A0 =A0 clk_enable(clk0);
> -
> =A0 =A0 =A0 =A0/*
> - =A0 =A0 =A0 =A0* Tick rate is 2.4MHz for Nomadik and 110MHz for ux500:
> + =A0 =A0 =A0 =A0* Tick rate is 2.4MHz for Nomadik and 100 or 133MHz for =
ux500:
> =A0 =A0 =A0 =A0 * use a divide-by-16 counter if it's more than 16MHz
> =A0 =A0 =A0 =A0 */
> - =A0 =A0 =A0 cr =3D MTU_CRn_32BITS;;
> =A0 =A0 =A0 =A0rate =3D clk_get_rate(clk0);
> - =A0 =A0 =A0 if (rate > 16 << 20) {
> + =A0 =A0 =A0 if (rate > (16 << 20))

Whatever it is we're gonna look for check it agains
a #define like

#define PRESCALER_16_LIMIT (1 << 20)

(Or whatever we would come up with in this thread)
And:

if (rate > PRESCALER_16_LIMIT)

.. whatever that may be in the end...


Yours,
Linus Walleij


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.229.1283456741.27306.linux-arm-kernel@lists.infradead.org>

> + =A0 =A0 =A0 struct clk *clk0;
> +
> + =A0 =A0 =A0 clk0 =3D clk_get_sys("mtu0", NULL);
> +
> + =A0 =A0 =A0 clk_enable(clk0);
> +
> +       if (clk_get_rate(clk0) > (16 << 20))
> +               cr |=3D MTU_CRn_PRESCALE_16;
> +       else
> +               cr |=3D MTU_CRn_PRESCALE_1;

To here can be removed actually.

We happen to know that this rate is not changing on the
MTU using systems.

And since we know the rate is not going to change...

Just save the rate and prescaler setting in a static local variable
and remove the other clock lookup and divisions.
(You still need to have a struct clk* pointer around for
enable/disable too.)

> (...)
> =A0void __init nmdk_timer_init(void)
> =A0{
> =A0 =A0 =A0 =A0unsigned long rate;
> =A0 =A0 =A0 =A0struct clk *clk0;
> - =A0 =A0 =A0 u32 cr;
>
> + =A0 =A0 =A0 /*
> + =A0 =A0 =A0 =A0* On MTU block 0: timer0 is used as source,
> + =A0 =A0 =A0 =A0* timer1 is used for events.
> + =A0 =A0 =A0 =A0*/
> =A0 =A0 =A0 =A0clk0 =3D clk_get_sys("mtu0", NULL);
> =A0 =A0 =A0 =A0BUG_ON(IS_ERR(clk0));
>
> - =A0 =A0 =A0 clk_enable(clk0);
> -
> =A0 =A0 =A0 =A0/*
> - =A0 =A0 =A0 =A0* Tick rate is 2.4MHz for Nomadik and 110MHz for ux500:
> + =A0 =A0 =A0 =A0* Tick rate is 2.4MHz for Nomadik and 100 or 133MHz for =
ux500:
> =A0 =A0 =A0 =A0 * use a divide-by-16 counter if it's more than 16MHz
> =A0 =A0 =A0 =A0 */
> - =A0 =A0 =A0 cr =3D MTU_CRn_32BITS;;
> =A0 =A0 =A0 =A0rate =3D clk_get_rate(clk0);
> - =A0 =A0 =A0 if (rate > 16 << 20) {
> + =A0 =A0 =A0 if (rate > (16 << 20))

Whatever it is we're gonna look for check it agains
a #define like

#define PRESCALER_16_LIMIT (1 << 20)

(Or whatever we would come up with in this thread)
And:

if (rate > PRESCALER_16_LIMIT)

.. whatever that may be in the end...


Yours,
Linus Walleij


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.232.1283546836.27306.linux-arm-kernel@lists.infradead.org>

So I think this be changed to

	default 0x30008000 if \
		ARCH_S3C2410 ||\
		ARCH_S3C2440

.  Ben?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.233.1283556889.27306.linux-arm-kernel@lists.infradead.org>

    apply: fix copy/rename breakage
    
    7ebd52a (Merge branch 'dz/apply-again', 2008-07-01) taught "git-apply" to
    grok a (non-git) patch that is a concatenation of separate patches that
    touch the same file number of times, by recording the postimage of patch
    application of previous round and using it as the preimage for later
    rounds.
    
    This "incremental" mode of patch application fundamentally contradicts
    with the way git rename/copy patches are designed.  When a git patch talks
    about a file A getting modified, and a new file B created out of A, like
    this:
    
        diff --git a/A b/A
        --- a/A
        +++ b/A
        ... change text here ...
        diff --git a/A b/B
        copy from A
        copy to B
        --- a/A
        +++ b/B
        ... change text here ...
    
    the second change to produce B does not depend on what is done to A with
    the first change in any way.  This is explicitly done so for reviewability
    of individual patches.
    
    With this commit, we do not look at 'fn_table' that records the postimage
    of previous round when applying a patch to produce a new file out of an
    existing file.

> How was this patch generated: with git itself?

Yes, the patch basically agrees with what I get by applying it and running

 git format-patch -M -B HEAD^..HEAD


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.234.1283864025.27306.linux-arm-kernel@lists.infradead.org>

the same thing was nacked - there are regulator API facilties for hiding
missing regulators from drivers when needed to get systems going, unless
the device genuinely can cope without supplies it should be relying on
those.


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.242.1284676037.27306.linux-arm-kernel@lists.infradead.org>

used loops that counted udelay(1) I've noticed that the
PLLE_MISC_READY is set after up to 3usecs.

> <snip>
>
>> +static struct clk_ops tegra_pcie_clk_ops =3D {
>> + =A0 =A0 =A0 .enable =A0 =A0 =3D tegra2_periph_clk_enable,
>> + =A0 =A0 =A0 .disable =A0 =A0=3D tegra2_periph_clk_disable,
>> +};
> Why is this needed? =A0Won't the regular periph ops work?

They didn't. I haven't found anything about what feeds these clocks,
can they change rate, what clock can be their parent and if there is
any muxing options for these clocks.

> <snip>
>
>> +static struct clk tegra_clk_pex =3D {
>> + =A0 =A0 =A0 .name =A0 =A0 =A0=3D "pex",
>> + =A0 =A0 =A0 .flags =A0 =A0 =3D PERIPH_MANUAL_RESET,
>> + =A0 =A0 =A0 .ops =A0 =A0 =A0 =3D &tegra_pcie_clk_ops,
>> + =A0 =A0 =A0 .clk_num =A0 =3D 70,
>> +};
>> +
>> +static struct clk tegra_clk_afi =3D {
>> + =A0 =A0 =A0 .name =A0 =A0 =A0=3D "afi",
>> + =A0 =A0 =A0 .flags =A0 =A0 =3D PERIPH_MANUAL_RESET,
>> + =A0 =A0 =A0 .ops =A0 =A0 =A0 =3D &tegra_pcie_clk_ops,
>> + =A0 =A0 =A0 .clk_num =A0 =3D 72,
>> +};
>> +
>> +/* the pcie_xclk is required for reset of PCIE subsystem */
>> +static struct clk tegra_clk_pcie_xclk =3D {
>> + =A0 =A0 =A0 .name =A0 =A0 =A0=3D "pcie_xclk",
>> + =A0 =A0 =A0 .clk_num =A0 =3D 74,
>> +};
> These should probably all be defined in the CLK_PERIPH table.

See the comment above :)

> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>



--=20
=A0 =A0 Sincerely Yours,
=A0 =A0 =A0 =A0 Mike.


From bogus@does.not.exist.com  Sun Jun  6 12:36:48 2010
From: bogus@does.not.exist.com ()
Date: Sun, 06 Jun 2010 16:36:48 -0000
Subject: No subject
Message-ID: <mailman.243.1284718717.27306.linux-arm-kernel@lists.infradead.org>


From gdavis at mvista.com  Wed Jun  9 11:59:19 2010
From: gdavis at mvista.com (George G. Davis)
Date: Wed, 9 Jun 2010 11:59:19 -0400
Subject: mpcore_wdt: Add percpu support for ARM11 MPCore watchdogs
Message-ID: <mailman.3.1285171006.1886.linux-arm-kernel@lists.infradead.org>

Signed-off-by: George G. Davis <gdavis at mvista.com>

diff --git a/drivers/watchdog/mpcore_wdt.c b/drivers/watchdog/mpcore_wdt.c
index b8ec7ac..d624d8d 100644
--- a/drivers/watchdog/mpcore_wdt.c
+++ b/drivers/watchdog/mpcore_wdt.c
@@ -42,11 +42,14 @@ struct mpcore_wdt {
 	int		irq;
 	unsigned int	perturb;
 	char		expect_close;
+	int		margin;
+	int		nowayout;
+	int		noboot;
+	char		name[12];
+	spinlock_t	lock;
+	struct miscdevice miscdev;
 };
 
-static struct platform_device *mpcore_wdt_dev;
-static DEFINE_SPINLOCK(wdt_lock);
-
 #define TIMER_MARGIN	60
 static int mpcore_margin = TIMER_MARGIN;
 module_param(mpcore_margin, int, 0);
@@ -97,25 +100,25 @@ static void mpcore_wdt_keepalive(struct mpcore_wdt *wdt)
 {
 	unsigned long count;
 
-	spin_lock(&wdt_lock);
+	spin_lock(&wdt->lock);
 	/* Assume prescale is set to 256 */
 	count =  __raw_readl(wdt->base + TWD_WDOG_COUNTER);
 	count = (0xFFFFFFFFU - count) * (HZ / 5);
-	count = (count / 256) * mpcore_margin;
+	count = (count / 256) * wdt->margin;
 
 	/* Reload the counter */
 	writel(count + wdt->perturb, wdt->base + TWD_WDOG_LOAD);
 	wdt->perturb = wdt->perturb ? 0 : 1;
-	spin_unlock(&wdt_lock);
+	spin_unlock(&wdt->lock);
 }
 
 static void mpcore_wdt_stop(struct mpcore_wdt *wdt)
 {
-	spin_lock(&wdt_lock);
+	spin_lock(&wdt->lock);
 	writel(0x12345678, wdt->base + TWD_WDOG_DISABLE);
 	writel(0x87654321, wdt->base + TWD_WDOG_DISABLE);
 	writel(0x0, wdt->base + TWD_WDOG_CONTROL);
-	spin_unlock(&wdt_lock);
+	spin_unlock(&wdt->lock);
 }
 
 static void mpcore_wdt_start(struct mpcore_wdt *wdt)
@@ -125,7 +128,7 @@ static void mpcore_wdt_start(struct mpcore_wdt *wdt)
 	/* This loads the count register but does NOT start the count yet */
 	mpcore_wdt_keepalive(wdt);
 
-	if (mpcore_noboot) {
+	if (wdt->noboot) {
 		/* Enable watchdog - prescale=256, watchdog mode=0, enable=1 */
 		writel(0x0000FF01, wdt->base + TWD_WDOG_CONTROL);
 	} else {
@@ -134,12 +137,12 @@ static void mpcore_wdt_start(struct mpcore_wdt *wdt)
 	}
 }
 
-static int mpcore_wdt_set_heartbeat(int t)
+static int mpcore_wdt_set_heartbeat(int *p, int t)
 {
 	if (t < 0x0001 || t > 0xFFFF)
 		return -EINVAL;
 
-	mpcore_margin = t;
+	*p = t;
 	return 0;
 }
 
@@ -148,12 +151,13 @@ static int mpcore_wdt_set_heartbeat(int t)
  */
 static int mpcore_wdt_open(struct inode *inode, struct file *file)
 {
-	struct mpcore_wdt *wdt = platform_get_drvdata(mpcore_wdt_dev);
+	struct mpcore_wdt *wdt = container_of(file->private_data,
+					      struct mpcore_wdt, miscdev);
 
 	if (test_and_set_bit(0, &wdt->timer_alive))
 		return -EBUSY;
 
-	if (nowayout)
+	if (wdt->nowayout)
 		__module_get(THIS_MODULE);
 
 	file->private_data = wdt;
@@ -172,7 +176,7 @@ static int mpcore_wdt_release(struct inode *inode, struct file *file)
 
 	/*
 	 *	Shut off the timer.
-	 * 	Lock it in if it's a module and we set nowayout
+	 * 	Lock it in if it's a module and we set wdt->nowayout
 	 */
 	if (wdt->expect_close == 42)
 		mpcore_wdt_stop(wdt);
@@ -195,7 +199,7 @@ static ssize_t mpcore_wdt_write(struct file *file, const char *data,
 	 *	Refresh the timer.
 	 */
 	if (len) {
-		if (!nowayout) {
+		if (!wdt->nowayout) {
 			size_t i;
 
 			/* In case it was set long ago */
@@ -271,14 +275,14 @@ static long mpcore_wdt_ioctl(struct file *file, unsigned int cmd,
 		break;
 
 	case WDIOC_SETTIMEOUT:
-		ret = mpcore_wdt_set_heartbeat(uarg.i);
+		ret = mpcore_wdt_set_heartbeat(&wdt->margin, uarg.i);
 		if (ret)
 			break;
 
 		mpcore_wdt_keepalive(wdt);
 		/* Fall */
 	case WDIOC_GETTIMEOUT:
-		uarg.i = mpcore_margin;
+		uarg.i = wdt->margin;
 		ret = 0;
 		break;
 
@@ -318,20 +322,14 @@ static const struct file_operations mpcore_wdt_fops = {
 	.release	= mpcore_wdt_release,
 };
 
-static struct miscdevice mpcore_wdt_miscdev = {
-	.minor		= WATCHDOG_MINOR,
-	.name		= "watchdog",
-	.fops		= &mpcore_wdt_fops,
-};
-
 static int __devinit mpcore_wdt_probe(struct platform_device *dev)
 {
 	struct mpcore_wdt *wdt;
 	struct resource *res;
 	int ret;
 
-	/* We only accept one device, and it must have an id of -1 */
-	if (dev->id != -1)
+	/* Support up to four devices having an id of 0..3 */
+	if (dev->id < 0 || dev->id > 3)
 		return -ENODEV;
 
 	res = platform_get_resource(dev, IORESOURCE_MEM, 0);
@@ -358,8 +356,12 @@ static int __devinit mpcore_wdt_probe(struct platform_device *dev)
 		goto err_free;
 	}
 
-	mpcore_wdt_miscdev.parent = &dev->dev;
-	ret = misc_register(&mpcore_wdt_miscdev);
+	snprintf(wdt->name, ARRAY_SIZE(wdt->name), "watchdog%d", dev->id);
+	wdt->miscdev.parent = &dev->dev;
+	wdt->miscdev.minor = MISC_DYNAMIC_MINOR,
+	wdt->miscdev.name = wdt->name,
+	wdt->miscdev.fops = &mpcore_wdt_fops,
+	ret = misc_register(&wdt->miscdev);
 	if (ret) {
 		dev_printk(KERN_ERR, wdt->dev,
 			"cannot register miscdev on minor=%d (err=%d)\n",
@@ -367,22 +369,28 @@ static int __devinit mpcore_wdt_probe(struct platform_device *dev)
 		goto err_misc;
 	}
 
-	ret = request_irq(wdt->irq, mpcore_wdt_fire, IRQF_DISABLED,
-							"mpcore_wdt", wdt);
+	ret = request_irq(wdt->irq, mpcore_wdt_fire,
+			  IRQF_DISABLED |
+			  IRQF_SHARED |
+			  IRQF_NOBALANCING |
+			  IRQF_PERCPU, "mpcore_wdt", wdt);
 	if (ret) {
 		dev_printk(KERN_ERR, wdt->dev,
 			"cannot register IRQ%d for watchdog\n", wdt->irq);
 		goto err_irq;
 	}
 
+	spin_lock_init(&wdt->lock);
+	wdt->margin = mpcore_margin;
+	wdt->nowayout = nowayout;
+	wdt->noboot = mpcore_noboot;
 	mpcore_wdt_stop(wdt);
 	platform_set_drvdata(dev, wdt);
-	mpcore_wdt_dev = dev;
 
 	return 0;
 
 err_irq:
-	misc_deregister(&mpcore_wdt_miscdev);
+	misc_deregister(&wdt->miscdev);
 err_misc:
 	iounmap(wdt->base);
 err_free:
@@ -397,9 +405,7 @@ static int __devexit mpcore_wdt_remove(struct platform_device *dev)
 
 	platform_set_drvdata(dev, NULL);
 
-	misc_deregister(&mpcore_wdt_miscdev);
-
-	mpcore_wdt_dev = NULL;
+	misc_deregister(&wdt->miscdev);
 
 	free_irq(wdt->irq, wdt);
 	iounmap(wdt->base);
@@ -421,7 +427,7 @@ static struct platform_driver mpcore_wdt_driver = {
 };
 
 static char banner[] __initdata = KERN_INFO "MPcore Watchdog Timer: 0.1. "
-		"mpcore_noboot=%d mpcore_margin=%d sec (nowayout= %d)\n";
+		"mpcore_noboot=%d mpcore_margin=%d sec (nowayout=%d)\n";
 
 static int __init mpcore_wdt_init(void)
 {
@@ -429,8 +435,8 @@ static int __init mpcore_wdt_init(void)
 	 * Check that the margin value is within it's range;
 	 * if not reset to the default
 	 */
-	if (mpcore_wdt_set_heartbeat(mpcore_margin)) {
-		mpcore_wdt_set_heartbeat(TIMER_MARGIN);
+	if (mpcore_wdt_set_heartbeat(&mpcore_margin, mpcore_margin)) {
+		mpcore_wdt_set_heartbeat(&mpcore_margin, TIMER_MARGIN);
 		printk(KERN_INFO "mpcore_margin value must be 0 < mpcore_margin < 65536, using %d\n",
 			TIMER_MARGIN);
 	}


HTH!

--
Regards,
George

> 
> Thanks,
> John
> 
> 
> 
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